diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_CubeIDE/Boot/Debug/openblt_stm32h743.elf b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_CubeIDE/Boot/Debug/openblt_stm32h743.elf
index 61205949..d04f517d 100644
Binary files a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_CubeIDE/Boot/Debug/openblt_stm32h743.elf and b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_CubeIDE/Boot/Debug/openblt_stm32h743.elf differ
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_CubeIDE/Boot/Debug/openblt_stm32h743.srec b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_CubeIDE/Boot/Debug/openblt_stm32h743.srec
index c456b45c..842a6ed5 100644
--- a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_CubeIDE/Boot/Debug/openblt_stm32h743.srec
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_CubeIDE/Boot/Debug/openblt_stm32h743.srec
@@ -43,16 +43,16 @@ S31508000280D5090008D5090008D509000800000000AE
 S30D0800029000000000D509000872
 S3150800029810B5054C237833B9044B13B10448AFF3AA
 S315080002A800800123237010BDC80000240000000048
-S315080002B8DC61000808B5034B1BB103490348AFF3D3
-S315080002C8008008BD00000000CC000024DC6100089E
-S315080002D808B505F047FA08BD08B505F051FA08BD8E
+S315080002B8F061000808B5034B1BB103490348AFF3BF
+S315080002C8008008BD00000000CC000024F06100088A
+S315080002D808B505F051FA08BD08B505F05BFA08BD7A
 S315080002E808B5054B1B6913F4005F01D0002008BD4B
 S315080002F800F03EF80120FAE70008025808B564201D
 S3150800030800F008F808BD08B500F00AF808BD7047F7
 S3150800031870477047014B1880704700BFE4000024F7
-S3150800032808B504F0DFFF0E4B1B6898420FD30D4B38
+S3150800032808B504F0E9FF0E4B1B6898420FD30D4B2E
 S315080003381B786BB90B4B01221A700B4B80229A61FA
-S3150800034804F0D0FF094B1B881844054B186008BDF4
+S3150800034804F0DAFF094B1B881844054B186008BDEA
 S31508000358044B00221A70044B4FF400029A61EFE727
 S31508000368E8000024E600002400040258E4000024FB
 S31508000378024B4FF400029A61704700BF0004025806
@@ -66,17 +66,17 @@ S315080003E80102C3F8E020D3F8E02002F001020292E5
 S315080003F8029AD3F8E02042F00202C3F8E020D3F8C4
 S31508000408E03003F002030193019B0E4E4FF40003FC
 S31508000418B3610CAD4FF4005345F8183D29460A4810
-S3150800042802F022FC80230693012307930894099473
-S315080004380A942946304602F017FC0CB070BD00BF76
+S3150800042802F026FC8023069301230793089409946F
+S315080004380A942946304602F01BFC0CB070BD00BF72
 S3150800044800440258000402580008025810B590B033
-S31508000458202200210DEB020005F0B3FE00240494C7
+S31508000458202200210DEB020005F0BDFE00240494BD
 S31508000468059406942B4BD3F8E82042F48022C3F867
 S31508000478E820D3F8E82002F480220192019AD3F8FA
 S31508000488E02042F00802C3F8E020D3F8E03003F091
 S3150800049808030093009B4FF44073029302230393C7
-S315080004A80723079302A91C4802F0DEFB08944FF4B9
+S315080004A80723079302A91C4802F0E2FB08944FF4B5
 S315080004B8E13309930A940B940C940C230D930E9428
-S315080004C80F94164C08A9204602F076FFA36823F075
+S315080004C80F94164C08A9204602F07AFFA36823F071
 S315080004D86043A360A36823F06063A360236823F0DE
 S315080004E800532360636823F490436360A36823F08A
 S315080004F82A03A360236843F001032360074BDB69DB
@@ -101,7 +101,7 @@ S31508000618A361A36923F00F0343F00803A361E36901
 S3150800062823F0700343F04003E361E36923F4E063CE
 S3150800063843F48063E361A36923F0700343F040033E
 S31508000648A361236A23F0700343F0400323620F482B
-S3150800065803F0F0FC002000F0FDF90D4A136823F0BA
+S3150800065803F0F4FC002000F0FDF90D4A136823F0B6
 S3150800066807031360236D23F040532365636D23F452
 S31508000678401343F48013636510BD00BF0020005281
 S31508000688004802580044025800FEFFFF00389C1C28
@@ -115,21 +115,21 @@ S315080006F804FB134BD3F8EC2042F48072C3F8EC20C1
 S31508000708D3F8EC2002F480720192019AD3F8E0201B
 S3150800071842F00202C3F8E020D3F8E03003F00203FF
 S315080007280293029B4FF4407303930223049309230D
-S31508000738079303A9034801F0B3F8D7E700A00040D8
+S31508000738079303A9034801F0B7F8D7E700A00040D4
 S31508000748004402580004025810B588B000230393E1
 S3150800075804930593069307930268154B9A4201D0AA
 S3150800076808B010BD134CD4F8E03043F00103C4F8C0
 S31508000778E030D4F8E03003F001030193019B4FF40D
 S31508000788C0530393022304930A23079303A90A4829
-S3150800079801F086F8D4F8D83043F00063C4F8D830A6
+S3150800079801F08AF8D4F8D83043F00063C4F8D830A2
 S315080007A8D4F8D83003F000630293029BD8E700BF59
 S315080007B800000840004402580000025808B50268BC
 S315080007C8084B9A4200D008BD074AD2F8D83023F019
-S315080007D80063C2F8D8304FF4C051044801F050F904
+S315080007D80063C2F8D8304FF4C051044801F054F900
 S315080007E8F1E700BF0000084000440258000002581C
-S315080007F810B502F09FFA214C4FF40003A361204874
-S3150800080802F046F91F4802F043F9204602F040F97B
-S315080008181D4802F03DF91D4BD3F8D82022F0006296
+S315080007F810B502F0A3FA214C4FF40003A361204870
+S3150800080802F04AF91F4802F047F9204602F044F96F
+S315080008181D4802F041F91D4BD3F8D82022F0006292
 S31508000828C3F8D820D3F8EC2022F48072C3F8EC2059
 S31508000838D3F8E82022F48022C3F8E820D3F8E02089
 S3150800084822F00802C3F8E020D3F8E02022F00402D8
@@ -154,8 +154,8 @@ S31508000968000202020000FF01800201010010005C7B
 S315080009780000FFFF0881005100400052DFF834D01C
 S31508000988FFF792FF002103E00B4B5B5843500431F5
 S315080009980A480B4B42189A42F6D30A4A02E0002341
-S315080009A842F8043B084B9A42F9D305F0DBFBFFF7FC
-S315080009B871FE704700000824A86400080000002497
+S315080009A842F8043B084B9A42F9D305F0E5FBFFF7F2
+S315080009B871FE704700000824BC6400080000002483
 S315080009C8C8000024C800002498150024FEE7000083
 S315080009D810B5194B194ADA670024DC67184AC3F8B0
 S315080009E88020C3F8804040F27122C3F88420C3F8F7
@@ -170,16 +170,16 @@ S31508000A6804464FF47A70B0FBF3F30C4A1068B0FBEF
 S31508000A78F3F000F0A9F868B90F2C01D901200AE0AB
 S31508000A88002221464FF0FF3000F06CF8044B1C603A
 S31508000A98002000E0012010BD080000240000002402
-S31508000AA80C00002410B5032000F04AF801F0D8FE1F
+S31508000AA80C00002410B5032000F04AF801F0DCFE1B
 S31508000AB80F498B69C3F303230E4AD35C03F01F035C
 S31508000AC8D8408B6903F00F03D35C03F01F0320FAA1
 S31508000AD803F3094A1360094B18600020FFF7BAFFA9
 S31508000AE810B10124204610BD0446FFF7E1FDF9E7D9
-S31508000AF8004402584062000804000024000000244C
+S31508000AF80044025854620008040000240000002438
 S31508000B08034B1B78034A11680B441360704700BFF0
-S31508000B18080000243813002438B5044604F0EAFB14
+S31508000B18080000243813002438B5044604F0F4FB0A
 S31508000B280546B4F1FF3F02D0044B1B781C4404F079
-S31508000B38E1FB401BA042FAD338BD00BF08000024D9
+S31508000B38EBFB401BA042FAD338BD00BF08000024CF
 S31508000B480649CB6823F4E0631B041B0C000200F477
 S31508000B58E0600343024A1A43CA60704700ED00E0A2
 S31508000B680000FA0530B4154BDB68C3F30223C3F15A
@@ -228,16 +228,16 @@ S31508000E086C600835002015E00E698C6826430C6866
 S31508000E18264346F08046E0E71418E678A3781B04CC
 S31508000E2843EA0663647843EA0423145C234345F8D3
 S31508000E38043B0430CB89034CE35C8342ECD8F0BC12
-S31508000E48704700BF5062000830B595B004464C227A
-S31508000E58A04901A805F0AAF9002C00F038812368F2
+S31508000E48704700BF6462000830B595B004464C2266
+S31508000E58A04901A805F0B4F9002C00F038812368E8
 S31508000E689D4A934220D094F898300BB32268936928
-S31508000E7823F01003936104F03DFA054623689A693E
-S31508000E8812F0080F1AD004F035FA401B0A28F5D9CB
+S31508000E7823F01003936104F047FA054623689A6934
+S31508000E8812F0080F1AD004F03FFA401B0A28F5D9C1
 S31508000E98D4F89C3043F00103C4F89C30032384F843
 S31508000EA89830012015B030BD03F580736360DAE722
 S31508000EB884F899302046FFF70DFCD7E79A6942F07F
-S31508000EC801029A6104F016FA054623689A6912F02F
-S31508000ED8010F0FD104F00EFA401B0A28F5D9D4F8E9
+S31508000EC801029A6104F020FA054623689A6912F025
+S31508000ED8010F0FD104F018FA401B0A28F5D9D4F8DF
 S31508000EE89C3043F00103C4F89C30032384F89830F7
 S31508000EF80120D7E79A6942F002029A61237C012BFE
 S31508000F0840D02268936943F040039361637C012BC0
@@ -269,7 +269,7 @@ S31508001098B1FD07E72268936943F02003936188E75F
 S315080010A8A36A013BE26A013A43EA0223226B013A40
 S315080010B843EA0213626A013A216843EA0243CB60AB
 S315080010C88BE76268936823F003039360D6E70120E9
-S315080010D8E8E600BFF461000800A0004090F89830E0
+S315080010D8E8E600BF0862000800A0004090F89830CB
 S315080010E8013BDBB2012B07D9D0F89C3043F0020349
 S315080010F8C0F89C3001207047CB680A68D2B9072B1C
 S315080011080ED08A68DB0643EA82730A6943EA024311
@@ -278,1351 +278,1352 @@ S315080011280A69CB691B0243EA02438A69134343F0F7
 S315080011386053EFE710B40A6942EA4372072B0ED0E8
 S315080011488C684B6943EA8473006F496800EBC104ED
 S3150800115840F83120636000205DF8044B70478B69BE
-S31508001168F2E790F89830DBB2012B07D0D0F89C301C
-S3150800117843F00403C0F89C3001207047022380F826
-S3150800118898300268936923F0010393610023C0F835
-S315080011989C301846704770B590F89840013CE4B200
-S315080011A8012C07D9D0F89C3043F00203C0F89C30CC
-S315080011B8012070BD93FAA3F5B5FA85F50668D6F841
-S315080011C8C040C4F30544A5420BD2D6F8CC401C420D
-S315080011D80FD0D0F89C3043F04003C0F89C3001206B
-S315080011E8E7E7D0F89C3043F02003C0F89C3001208C
-S315080011F8DFE793FAA3F3B3FA83F3FFF7E5FD0020D5
-S31508001208D7E790F89830DBB2022B07D0D0F89C3095
-S3150800121843F00803C0F89C30012070470368C3F8F8
-S31508001228D010002070470000F0B490F89840E4B257
-S31508001238022C08D0D0F89C3043F00803C0F89C303C
-S315080012480120F0BC7047402939D0412964D0046D83
-S315080012588C4240F28E80C46F456D01FB05F504EBA0
-S3150800126885044FF0000C256805F080455560002D6B
-S3150800127840F087802568C5F38A451560256805F016
-S3150800128800559560256805F000451561A588D5615E
-S31508001298656805F47025D560656805F48015556197
-S315080012A8656805F400159561E57905F07F05156209
-S315080012B86568ED0F556204F10805002469E00468BD
-S315080012C8D4F8A05015F4FE0F16D0D4F8A45015F08B
-S315080012D87F0F19D0D4F8A45015F0807F01D0D4F820
-S315080012E8A050D4F8A440C4F3052C446F456C0CFBF5
-S315080012F805F504EB8504B6E7D0F89C3043F02003DF
-S31508001308C0F89C3001209CE7D0F89C3043F48073E1
-S31508001318C0F89C30012094E70468D4F8B05015F456
-S31508001328FE0F16D0D4F8B45015F07F0F19D0D4F89C
-S31508001338B45015F0807F01D0D4F8B050D4F8B44032
-S31508001348C4F3052C846FC56C0CFB05F504EB850402
-S3150800135889E7D0F89C3043F02003C0F89C30012078
-S315080013686FE7D0F89C3043F48073C0F89C300120AE
-S3150800137867E7D0F89C3043F02003C0F89C3001207A
-S315080013885FE7256825F06045156077E72E5D1E55E9
-S315080013980134D689124FBE5DA642F7D840290BD02C
-S315080013A841290ED01F2911D80268012303FA01F131
-S315080013B8C2F89810002044E70368C3F8A8C00020BC
-S315080013C83FE70368C3F8B8C000203AE701F01F01F1
-S315080013D80268012303FA01F1C2F89C10002030E7DD
-S315080013E8506200080368D3F89820D3F89C001F2990
-S315080013F803D8CA4012F0010F17D01F2905D901F0E2
-S315080014081F02D04010F0010F11D01F2907D901F08B
-S315080014181F01012000FA01F1C3F89C10704701204A
-S3150800142800FA01F1C3F898107047002070470020A9
-S3150800143870470368D3F8CC300B4201D001207047B7
-S3150800144800207047144BDB6813F0010F09D0124BC4
-S31508001458124A5A6002F188325A60DB6813F0010FA3
-S3150800146816D10D4BD3F80C3113F0010F12D00A4BD5
-S315080014780A4AC3F8042102F18832C3F80421D3F8CA
-S315080014880C3113F0010F01D1002070470120704775
-S315080014980120704700207047002000522301674545
-S315080014A80D4BDA6842F00102DA60DB6813F0010FC7
-S315080014B80FD0094BD3F80C2142F00102C3F80C21CE
-S315080014C8D3F80C3113F0010F01D000207047012022
-S315080014D870470120704700BF002000522DE9F041EF
-S315080014E805460F46384B1E6903F004FF8046022F4F
-S315080014F807D026F0684626F48016760C7604042467
-S3150800150820E0314BD3F8106126F0684626F4801699
-S31508001518760C760446F000462C4C13E003F0EAFEF7
-S31508001528A0EB0800A84248D865B9032025E0264B51
-S315080015381B6934EA03030CBF0123002383B1B5F101
-S31508001548FF3FEBD134F00403F1D01F4BD3F8103129
-S3150800155824EA030333F000430CBF01230023EDE715
-S3150800156836F000410FD01A4A936933439361002E27
-S3150800157805DA154BC3F814110120BDE8F081124BA2
-S315080015885E610120F9E7012F0CD00F4BD3F8103113
-S3150800159813F4803F15D00C4B4FF48032C3F814214E
-S315080015A80020EAE7084B1B6913F4803F07D0064B6F
-S315080015B84FF480325A610020DFE70320DDE7002078
-S315080015C8DBE70020D9E700BF0020005204000080AE
-S315080015D83C1300242F4B1B7D012B56D070B50C46A7
-S315080015E815462C4B01221A7501F17843B3F5801F6D
-S315080015F83DD3A1F10161B1F5801F49D20226254BD9
-S3150800160800229A6131464CF25030FFF767FF0346CD
-S3150800161840BB012E2DD0204AD2F80C3143F00203E4
-S31508001628C2F80C31BFF36F8FBFF34F8F082355F8F5
-S31508001638042B44F8042B013B13F0FF03F7D1BFF33F
-S315080016486F8FBFF34F8F31464CF25030FFF746FF86
-S315080016580346012E13D01049D1F80C2122F00202B4
-S31508001668C1F80C210B4A00211175184670BD0126D0
-S31508001678C5E7094AD36843F00203D360D2E70649A7
-S31508001688CA6822F00202CA60ECE7022318467047C5
-S315080016980123EAE73C1300240020005201F0030363
-S315080016A8032B24D011F0010F0BD01D4BDA6822F05A
-S315080016B83002DA60DA680243DA60DA6842F08802E9
-S315080016C8DA6011F0020F11D0154BD3F80C2122F06D
-S315080016D83002C3F80C21D3F80C211043C3F80C01C7
-S315080016E8D3F80C2142F08802C3F80C2170470C4B3A
-S315080016F8DA6822F03002DA60D3F80C2122F03002D8
-S31508001708C3F80C21DA680243DA60D3F80C211043CF
-S31508001718C3F80C019A6942F010029A61704700BF33
-S315080017280020005230B411F0010F0BD0104CE368BA
-S3150800173823F4E663E360E36842EA00252B4343F0B3
-S315080017488403E36011F0020F0FD00949D1F80C3170
-S3150800175823F4E663C1F80C31D1F80C3142EA0022C9
-S315080017681A4342F08402C1F80C2130BC704700BF06
-S3150800177800200052F8B5474B1B7D012B00F08880E6
-S315080017880F460446434B01221A7500229A6143689C
-S3150800179813F0010F0DD10026636813F0020F12D15A
-S315080017A8CEB92368012B1BD04FF0FF333B60A568E1
-S315080017B84CE001214CF25030FFF790FE064600280F
-S315080017C8EAD00126E8E702214CF25030FFF786FEF8
-S315080017D80028E5D001262F4B00221A753046F8BD99
-S315080017E861682069FFF75AFF636813F0010F12D181
-S315080017F8636813F0020FEED002214CF25030FFF75F
-S315080018086DFE00B10126244AD2F80C3123F00803EC
-S31508001818C2F80C31DFE701214CF25030FFF75EFEC3
-S3150800182800B101261C4AD36823F00803D360DFE712
-S3150800183801214CF25030FFF751FE0646164AD16888
-S31508001848164B0B40D3600FE006BB0135E368A26868
-S315080018581344AB42BFD9226961682846FFF762FF7D
-S31508001868636813F0010FE3D1636813F0020FEBD036
-S3150800187802214CF25030FFF731FE0646064AD2F8E6
-S315080018880C11064B0B40C2F80C31DDE73D60A2E7A8
-S315080018980226A3E73C13002400200052FBF8FFFFAA
-S315080018A8F0B583B000233AE0092400E00024B440E8
-S315080018B83C4302356E4E46F825406E4C2568D4439F
-S315080018C804EA05064F6817F4803F01D042EA050680
-S315080018D8684D2E606E6804EA06054F6817F4003FDF
-S315080018E801D042EA0605634E75604FF0B0452D688B
-S315080018F804EA05064F6817F4801F01D042EA050670
-S315080019084FF0B0452E606D682C404E6816F4001FDF
-S3150800191801D042EA05044FF0B042546001330A6820
-S3150800192832FA03F400F0A28001249C402240F5D044
-S315080019384D686E1E112D18BF012E01D9122D12D110
-S3150800194886685F000325BD4026EA0506CD68BD40C2
-S3150800195835438560466826EA04064D68C5F30014CB
-S315080019689C4034434460C6685F000325BD40EC4389
-S3150800197826408D68BD403543C5604D68122D18BF91
-S31508001988022D13D1DE08083650F826E003F00705BD
-S315080019984FEA850C0F2505FA0CF52EEA050E0D6992
-S315080019A805FA0CF545EA0E0540F82650056825405F
-S315080019B84C6804F00304BC402C4304604C6814F0DB
-S315080019C8805FABD02C4CD4F8F45045F00205C4F827
-S315080019D8F450D4F8F44004F002040194019C9D08DC
-S315080019E8AE1C234C54F8267003F00304A6000F24F3
-S315080019F8B44027EA0407214CA0423FF457AF04F540
-S31508001A088064A04222D004F58064A04220D004F560
-S31508001A188064A0421ED004F58064A0421CD004F558
-S31508001A288064A0421AD004F58064A04218D004F550
-S31508001A388064A04216D004F58064A04214D004F548
-S31508001A488064A0423FF430AF0A2430E701242EE729
-S31508001A5802242CE703242AE7042428E7052426E792
-S31508001A68062424E7072422E7082420E703B0F0BD64
-S31508001A780004005880000058004402580000025824
-S31508001A88002331FA03F200F09880F0B52CE0092714
-S31508001A9800E0002707FA04F4B44273D005685C002E
-S31508001AA8032606FA04F42543056023FA06F50835DD
-S31508001AB850F8256003F007074FEA870C0F2707FA3F
-S31508001AC80CF726EA070640F82560C568E44325406A
-S31508001AD8C560456825EA0202426082681440846047
-S31508001AE8013331FA03F267D001229A4012EA010556
-S31508001AF8F6D04FEA930E0EF10206304C54F82660DB
-S31508001B0803F00304A4004FF00F0C0CFA04FC0CEACB
-S31508001B1806062B4FB842BCD007F58067B84221D0D5
-S31508001B2807F58067B8421FD007F58067B8421DD009
-S31508001B3807F58067B8421BD007F58067B84219D001
-S31508001B4807F58067B84217D007F58067B84215D0F9
-S31508001B5807F58067B84213D007F58067B84296D06C
-S31508001B680A2797E7012795E7022793E7032791E7C7
-S31508001B7804278FE705278DE706278BE7072789E7D1
-S31508001B88082787E70F4C2668ED432E4026606668C7
-S31508001B982E4066604FF0B04426682E402660666878
-S31508001BA835406560054E0EF1020456F8245025EABC
-S31508001BB80C0546F8245071E7F0BD70470004005834
-S31508001BC800000258800000582DE9F04782B00768DF
-S31508001BD8CA00521A930003445A6D1B6D9A4257D885
-S31508001BE8B8469B1AC1EBC104A2000244526C9A4239
-S31508001BF800D31A460C46064602F1030A4FEA9A0A21
-S31508001C0816E009F1030A4FEA9A0AE3001B1B9D002E
-S31508001C183544A96C337C00931FFA89F3E2B2384637
-S31508001C2801F0B8FFAB6C4B44AB646B6D4B446B650A
-S31508001C3808EB441303F510639B699BB2534513D30A
-S31508001C48E3001B1B9A003244516D136D99420BD25F
-S31508001C5853B15B1AC4EBC4018A003244D2F84490E3
-S31508001C689945CED39946CCE7E3001B1B9800064452
-S31508001C78326D736D9A420FD804F00F040121A14002
-S31508001C88D7F8344824EA0104C7F83448002000E0A5
-S31508001C98012002B0BDE8F0870020FAE7F0B58BB05E
-S31508001CA8002800F091800446056890F8BD3323B3F0
-S31508001CB8032384F8BD33EB6B13F4807F01D100232B
-S31508001CC82361206801F004FD254655F8107B6E4609
-S31508001CD80FCD0FC60FCD0FC695E8030086E803009B
-S31508001CE8231D0ECB384601F031FC58B1022384F87F
-S31508001CF8BD33012528460BB0F0BD80F8BC33FEF786
-S31508001D0823FDD5E70021206801F0E8FC002315E04B
-S31508001D18D900C81A82002244012082F83D0082F8B8
-S31508001D283C30A2F84230002082F83F0050649064A4
-S31508001D38CA1A9100214408650133DBB26568AB42CB
-S31508001D48E6D3002315E0D800C11A8A0022440021E8
-S31508001D5882F8FD1182F8FC3182F8FF11C2F80412E4
-S31508001D68C2F80812C21A90002044C0F810120133AB
-S31508001D78DBB29D42E7D8254655F8107B6E460FCD4F
-S31508001D880FC60FCD0FC695E8030086E80300231D86
-S31508001D980ECB384601F0E8FC054660B9002384F8FE
-S31508001DA83830012384F8BD33636A012B08D02068CC
-S31508001DB802F0BFF89EE7022384F8BD33012599E7A8
-S31508001DC8204600F02FFDF2E7012593E7026890F810
-S31508001DD8BC33012B19D010B5012380F8BC33836AAC
-S31508001DE8012B0AD00446006802F097F8206801F02B
-S31508001DF869FC002084F8BC0310BD8369012BF1D067
-S31508001E08936B43F480339363ECE70220704738B545
-S31508001E1890F8BC33012B18D00446012380F8BC334C
-S31508001E28006801F055FC206802F043F8054628B119
-S31508001E38002384F8BC330125284638BD206802F0FB
-S31508001E4878F8002384F8BC33F6E70225F4E768B186
-S31508001E5810B50446032380F8BD33FFF7D8FF20469C
-S31508001E68FEF7ACFC002084F8BD0310BD01207047BE
-S31508001E7870B504460D460068066C00EB411303F579
-S31508001E8830639A682169012911D037498E4254D09E
-S31508001E983DB9C5EBC50293002344D3F81032002B8D
-S31508001EA85CD0E9B2204604F02BF8002070BD12F089
-S31508001EB8080F09D02D498E42F7D912F4004FF4D0ED
-S31508001EC84FF400429A60F0E712F0200F28D112F07A
-S31508001ED8280FEAD125498E4202D912F4004F22D199
-S31508001EE8E900491B8A002244D2F804121B69C3F385
-S31508001EF81203C91AC2F81412D2F80412D2F8083210
-S31508001F080B44C2F8083235B9C5EBC5029300234419
-S31508001F18D3F810325BB1E9B2204603F0F1FFC4E703
-S31508001F2820229A60C1E74FF400429A60BDE704F59B
-S31508001F387172012102F04EF8EDE712F4004F09D14B
-S31508001F4812F0200F01D020229A60E9B2204603F049
-S31508001F58D7FFAAE74FF400429A60A6E704F571721C
-S31508001F68002102F037F89CE70A31544F0A30544FDB
-S31508001F7838B5044603681D6C03EB4111D1F8082BE4
-S31508001F880E4B9D4207D901F5306112F4004F02D075
-S31508001F984FF400438B60204603F0AAFF074B9D4287
-S31508001FA802D92369012B01D0002038BD04F57172C6
-S31508001FB80121206802F00EF8F6E700BF0A30544FF0
-S31508001FC82DE9F84F04460568284601F0EFFF08B1E1
-S31508001FD8BDE8F88F2F460646206801F0B6FF0028A8
-S31508001FE8F6D0206801F0B1FF10F0020F04D022687D
-S31508001FF8536903F002035361206801F0A6FF10F045
-S31508002008100F15D02268936923F010039361D5F849
-S31508002018208008F00F09C8F34343022B00F0858097
-S31508002028062B00F0A5802268936943F01003936194
-S31508002038206801F08AFF10F4002F40F0AD80206870
-S3150800204801F083FF10F4802F40F0F180206801F03A
-S315080020587CFF0028C0F25F81206801F076FF10F443
-S31508002068006F0AD0D5F8083813F0010F40F06D81D3
-S315080020782268536903F400635361206801F065FF19
-S3150800208810F0006F15D02268536903F00063536196
-S3150800209894F8F433002B40F05C81012184F8F4139A
-S315080020A823685B6DC3F38303C4F8F833204600F04E
-S315080020B8CDFB206801F049FF10F4805F40F04D81A0
-S315080020C8206801F042FF10F4005F40F0AB812068F9
-S315080020D801F03BFF10F0080F40F0BC81206801F0C2
-S315080020E834FF10F4801F40F0BE81206801F02DFFF0
-S315080020F810F4001F40F0C181206801F026FF10F097
-S31508002108804F40F0C481206801F01FFF10F0040FCB
-S315080021183FF45EAF23685D6815F0040F40F0C08190
-S31508002128226853682B43536052E747F6F07318EA58
-S31508002138030F3FF478AF4FEAC90BABEB09034FEA35
-S31508002148830AA2444FEA1818C8F30A02DAF80812EA
-S31508002158284601F03FFEC8F30A08DAF8083243446D
-S31508002168CAF80832DAF814324344CAF814325AE775
-S31508002178082204F57171284601F02CFEC8F30A18DE
-S315080021884FEAC903A3EB09018A002244D2F814329C
-S315080021984344C2F8143246E7206801F0DAFE80465E
-S315080021A8B14617E007EB49130122C3F8082B49463D
-S315080021B82046FFF75DFE1DE007EB49130822C3F822
-S315080021C8082B49462046FFF7D3FE16E009F1010910
-S315080021D84FEA5808B8F1000F3FF431AF18F0010F6D
-S315080021E8F4D05FFA89F1206801F0C3FE824610F040
-S315080021F8010FD7D11AF0080FDED11AF0100F04D044
-S3150800220807EB49131022C3F8082B1AF0200F04D03D
-S3150800221807EB49132022C3F8082B1AF4005FD5D018
-S3150800222807EB49134FF40052C3F8082BCEE720688A
-S3150800223801F097FE8046B1462AE05946204603F043
-S315080022486BFE1AF0080F04D007EB49130822C3F8E7
-S3150800225808291AF0100F04D007EB49131022C3F8FF
-S3150800226808291AF0400F04D007EB49134022C3F88F
-S3150800227808291AF0020F04D007EB49130222C3F8FB
-S3150800228808291AF0800F41D109F101094FEA5808BF
-S31508002298B8F1000F3FF4DAAE18F0010FF4D05FFA80
-S315080022A889FB5946206801F06DFE824610F0010F39
-S315080022B8C7D009F00F03012101FA03F2D7F8343819
-S315080022C823EA0203C7F8343807EB4913C3F8081991
-S315080022D823698B42B1D14FEAC902A2EB09029300DE
-S315080022E82344596C9A6C0A449A64B9F1000FA4D12C
-S315080022F8C9EBC902930023441B6D002B9DD104F535
-S3150800230871720121206801F065FE96E74946204664
-S31508002318FFF75AFCB8E7D5F8043823F00103C5F8DF
-S31508002328043894F8F433012B08D0204603F03AFE13
-S315080023382268536903F0004353618DE6002184F847
-S31508002348F413204600F082FAF2E7204603F010FE5E
-S315080023588EE6204603F00CFEABE605F50068D8F8CD
-S31508002368043023F00103C8F804301021206801F06E
-S31508002378CDF920E007EB46134FF67F31C3F8081965
-S31508002388D3F8002922F40012C3F80029D3F8002943
-S3150800239842F00062C3F80029C3F8081BD3F8002BDB
-S315080023A822F40012C3F8002BD3F8002B42F000627F
-S315080023B8C3F8002B01366368B342DBD8D8F81C305B
-S315080023C843F00113C8F81C30236BEBB1D8F88430F6
-S315080023D843F00B03C8F88430D8F8443043F00B03AD
-S315080023E8C8F84430D5F8003823F4FE63C5F8003831
-S315080023F804F57172217C206801F0ECFD22685369A6
-S3150800240803F4805353615BE6D8F8142042F22B0391
-S315080024181343C8F81430D8F8103043F00B03C8F83B
-S315080024281030DFE7206801F0C5FD206801F060FA82
-S31508002438E060256800F00AFB227B0146284601F081
-S31508002448CBF8204603F07AFD2268536903F4005353
-S3150800245853613CE6204603F06AFD2268536903F097
-S31508002468080353613AE60021204603F0AAFD2268CC
-S31508002478536903F48013536137E60021204603F0B5
-S315080024889AFD2268536903F40013536134E620461B
-S3150800249803F09DFD2268536903F08043536132E6D1
-S315080024A8204603F09EFD3BE6026890F8BC33012BF4
-S315080024B816D010B5012380F8BC33836A012B07D0E0
-S315080024C80446006801F029FD002084F8BC0310BD05
-S315080024D88369012BF4D0936B43F480339363EFE756
-S315080024E80220704790F8BC33012B0BD010B5044670
-S315080024F8012380F8BC33006801F01BFD002084F82E
-S31508002508BC0310BD0220704790F8BC33012B0DD0D0
-S3150800251810B50446012380F8BC3380F838100068E3
-S3150800252801F0EBFC002084F8BC0310BD02207047BC
-S31508002538F8B511F0800F28D101F00F06F500AF1B8A
-S31508002548BC00274604F5FC74044404343E46064495
-S31508002558002586F8FD5101F00F012170A260E3708D
-S31508002568627802B1E180022B1ED090F8BC33012BA9
-S315080025781DD00546012380F8BC332146006801F0C2
-S31508002588C7F9002085F8BC03F8BD01F00F06F50069
-S31508002598AF1BBC0027463834044404343E46064478
-S315080025A8012586F83D50D6E700232371DDE702208A
-S315080025B8EAE738B511F0800F21D101F00F05EA00D6
-S315080025C8541BA3001C4603F5FC7303440433254631
-S315080025D80544002285F8FD2101F00F01197090F8CD
-S315080025E8BC23012A1AD00446012280F8BC231946BE
-S315080025F8006801F0D5F9002084F8BC0338BD01F05D
-S315080026080F04E200151BAB001D4638330344043398
-S315080026182C460444012284F83D20DDE70220EDE734
-S3150800262870B501F00F05EE00711B8C0004F5FC74FB
-S315080026380444211D761BB4000444C4F80822C4F8CF
-S3150800264810320023C4F8143284F8FD3184F8FC519A
-S315080026580369012B06D065B1DAB2006801F0AEFA53
-S31508002668002070BDC5EBC506B4000444C4F80C22A6
-S31508002678F1E7DAB2006801F001FAF1E701F00F01B3
-S31508002688C1EBC1018B001844D0F81402704770B525
-S3150800269801F00F05EE00711B8C0038340444211D27
-S315080026A8761BB4000444A2642365002363650123EA
-S315080026B884F83D3084F83C500369012B06D05DB197
-S315080026C8DAB2006801F07AFA002070BDC5EBC506D3
-S315080026D8B4000444E264F2E7DAB2006801F0CEF91D
-S315080026E8F2E738B501F00F0543689D4236D811F070
-S315080026F8800F20D1CA00541AA3001C4603F5FC73A0
-S315080027080344043322460244002182F8FD110122BB
-S315080027189A701D7090F8BC23012A21D0044601221C
-S3150800272880F8BC231946006801F068FB7DB10020D3
-S3150800273884F8BC0313E0EA00511B8B0019463833AA
-S31508002748034404330144012281F83D20DFE704F5F8
-S315080027587172217C206801F03DFCE8E7012038BD4C
-S315080027680220FCE710B501F00F0443689C422CD8F8
-S3150800277811F0800F1DD1E3001A1B91000A4601F5D6
-S31508002788FC71014404310244002382F8FD31002318
-S315080027988B700C7090F8BC33012B18D004460123B3
-S315080027A880F8BC33006801F056FB002084F8BC03A7
-S315080027B80CE0E3001A1B91000A463831014404313B
-S315080027C80244012382F83D30E1E7012010BD0220CA
-S315080027D8FCE730B40468606A29B10D46A36A00EBC1
-S315080027E8134000230CE040EA0240A06212E003F11D
-S315080027F8400104EB8101496800EB11400133DBB263
-S31508002808691E8B42F3D340EA024005F13F0104EB07
-S3150800281881014860002030BC70470368596200206F
-S3150800282870470000024603680121C0F8FC1300201F
-S3150800283882F8F4039A6942F000629A61596D024A6D
-S315080028480A435A65704700BF030000107047000026
-S31508002858024AD36843F08073D36070470048025829
-S31508002868724B1B6903F03803102B00F0DB80182B1A
-S3150800287810D00BB16E4870476C4B1B6813F0200FCD
-S3150800288800F0D280694B1868C0F3C100694B23FA77
-S3150800289800F07047654A916A01F00301906AC0F32F
-S315080028A80510D36A03F00103526BC2F3CC0203FB8B
-S315080028B802F307EE903AF8EE677A002800F0B5803A
-S315080028C8012966D0F9B1022900F08F8007EE100AAF
-S315080028D8F8EE476A9FED586A86EE267A534B1B6BC5
-S315080028E8C3F3080306EE903AF8EE666A9FED536A54
-S315080028F867EE867A76EEA77AF7EE006A77EEA67A14
-S3150800290827EE277A61E0494B1B6813F0200F23D07E
-S3150800291846490A68C2F3C102464BD34007EE103A45
-S31508002928F8EE476A07EE100AB8EE476A86EE867A20
-S315080029380B6BC3F3080306EE903AF8EE666A9FED4A
-S315080029483F6A67EE867A76EEA77AF7EE006A77EE3A
-S31508002958A67A27EE277A38E007EE100AF8EE476ACD
-S315080029689FED376A86EE267A304B1B6BC3F308034E
-S3150800297806EE903AF8EE666A9FED306A67EE867A52
-S3150800298876EEA77AF7EE006A77EEA67A27EE277A22
-S315080029981BE007EE100AF8EE476A9FED276A86EEEF
-S315080029A8267A224B1B6BC3F3080306EE903AF8EE19
-S315080029B8666A9FED226A67EE867A76EEA77AF7EE5A
-S315080029C8006A77EEA67A27EE277A184B1B6BC3F3AD
-S315080029D84623013307EE903AF8EE677AC7EE276A78
-S315080029E8FCEEE67A17EE900A704707EE100AF8EE3C
-S315080029F8476A9FED146A86EE267A0C4B1B6BC3F35F
-S31508002A08080306EE903AF8EE666A9FED0C6A67EEDA
-S31508002A18867A76EEA77AF7EE006A77EEA67A27EE32
-S31508002A28277AD2E708487047024870470044025890
-S31508002A3800093D000090D0030024744A00000039BC
-S31508002A480024744C0024F44A00127A0008B5FFF7EB
-S31508002A5807FF0B4A9369C3F303230A49CB5C03F0C0
-S31508002A681F0320FA03F3926902F00F02885C00F04C
-S31508002A781F0023FA00F0044A1060044A136008BDD0
-S31508002A88004402584062000804000024000000249C
-S31508002A986A4B984222D06A4B98422FD0694B984283
-S31508002AA83CD0694B984249D0684B984256D0684BF7
-S31508002AB8984263D0674B984270D0674B98427DD04E
-S31508002AC8664B984200F08A80654B984200F09680DB
-S31508002AD8644B984200F0A2800120704703F58843AA
-S31508002AE8D3F8882042F00102C3F88820D3F8882052
-S31508002AF822F00102C3F888200020704703F58043B6
-S31508002B08D3F8882042F00202C3F88820D3F8882030
-S31508002B1822F00202C3F888200020704703F5705394
-S31508002B28D3F8882042F00402C3F88820D3F888200E
-S31508002B3822F00402C3F888200020704703F5605382
-S31508002B48D3F8882042F00802C3F88820D3F88820EA
-S31508002B5822F00802C3F888200020704703F550536E
-S31508002B68D3F8882042F01002C3F88820D3F88820C2
-S31508002B7822F01002C3F888200020704703F5405356
-S31508002B88D3F8882042F02002C3F88820D3F8882092
-S31508002B9822F02002C3F888200020704703F5305336
-S31508002BA8D3F8882042F04002C3F88820D3F8882052
-S31508002BB822F04002C3F888200020704703F5205306
-S31508002BC8D3F8882042F08002C3F88820D3F88820F2
-S31508002BD822F08002C3F888200020704703F51053B6
-S31508002BE8D3F8882042F48072C3F88820D3F888205E
-S31508002BF822F48072C3F888200020704703F5005332
-S31508002C08D3F8882042F40072C3F88820D3F88820BD
-S31508002C1822F40072C3F888200020704703F5E053B1
-S31508002C28D3F8882042F48062C3F88820D3F888202D
-S31508002C3822F48062C3F888200020704700000258F2
-S31508002C480004025800080258000C025800100258DE
-S31508002C580014025800180258001C0258002002588E
-S31508002C680024025800280258F0B40A6892FAA2F218
-S31508002C78B2FA82F216E00F69C66803FB03F505EB9C
-S31508002C884504E443264005FB07F73E43C6604E68FD
-S31508002C98022E29D04B680668344005FB03F3234304
-S31508002CA8036001320B6833FA02F440D001249440D9
-S31508002CB82340F6D04C68013C012CDCD88E68846821
-S31508002CC803FB03F505EB450724EA070405FB06F5A8
-S31508002CD82C4384600E68CD68446824EA060405FB1C
-S31508002CE806F52C434460C6E7FF2B0ED8066A05FB93
-S31508002CF803F707FB03F3C3EB031726EA07074E692F
-S31508002D0803FB06F33B430362C4E7466A1B0A03FB55
-S31508002D1803F707FB03F707FB03F3C3EB031726EAD7
-S31508002D2807074E6903FB06F33B434362B2E70020F5
-S31508002D38F0BC70472D4B1B6803F00F03062B06D80B
-S31508002D482A4A136823F00F0343F007031360284A37
-S31508002D58136843F001031360254B1B6813F0040F2F
-S31508002D68FAD0234B00221A611968224A0A401A60C7
-S31508002D781F4B1B6813F0007FFAD11D4B1B6813F015
-S31508002D88006FFAD11A4B1B6813F0005FFAD1184B7B
-S31508002D9800229A61DA611A62174999621749D96253
-S31508002DA8174919635A639963DA6319645A6419687F
-S31508002DB821F4802119601A66996E40F2FF720A4357
-S31508002DC89A66D3F8D02042F48032C3F8D020074B4D
-S31508002DD81B6803F00F03072B06D9044A136823F068
-S31508002DE80F0343F007031360704700BF0020005223
-S31508002DF80044025845EDF6EA000202020000FF0107
-S31508002E088002010107EE900AF8EE676A07EE901A43
-S31508002E18F8EE677A86EEA77A07EE902AF8EE677ACA
-S31508002E2806EE903AF8EE666A9FED096A66EE866AD5
-S31508002E3877EEA67A27EE277ADDED007AF8EE677A36
-S31508002E48C7EE276AFCEEE67A17EE900A704700BFC7
-S31508002E58000000392DE9F04182B03F4B9B6A03F028
-S31508002E680303012B60D0002B52D0022B63D0002716
-S31508002E780023036043608360374B9E6AC6F30516D2
-S31508002E881A6BC2F30802551CDB6A13F0010F5FD0F0
-S31508002E98314B5B6BC3F3CC08002E36D004462E4B59
-S31508002EA8DB6A13F4803F0CD02B4B1B6BC3F346230A
-S31508002EB80133009343462A4631463846FFF7A2FFB0
-S31508002EC82060254BDB6A13F4003F0CD0224B1B6BA2
-S31508002ED8C3F306430133009343462A463146384628
-S31508002EE8FFF790FF60601C4BDB6A13F4802F0CD049
-S31508002EF8194B1B6BC3F306630133009343462A46F3
-S31508002F0831463846FFF77EFFA06002B0BDE8F0817B
-S31508002F18114B1B6813F0040F14D00F4B1B68C3F32F
-S31508002F28C1030E4FDF40A3E70B4B1B6813F4807FE2
-S31508002F380AD100279CE7084B1B6813F4003F05D104
-S31508002F48002795E7002793E7054F91E7054F8FE791
-S31508002F584FF00008A0E700BF004402580090D003CD
-S31508002F6800093D0000127A002DE9F04182B03F4B76
-S31508002F789B6A03F00303012B60D0002B52D0022B67
-S31508002F8863D000270023036043608360374B9E6A3B
-S31508002F98C6F305369A6BC2F30802551CDB6A13F0AA
-S31508002FA8100F5FD0314BDB6BC3F3CC08002E36D03D
-S31508002FB804462E4BDB6A13F4002F0CD02B4B9B6B65
-S31508002FC8C3F346230133009343462A463146384617
-S31508002FD8FFF718FF2060254BDB6A13F4801F0CD017
-S31508002FE8224B9B6BC3F306430133009343462A4699
-S31508002FF831463846FFF706FF60601C4BDB6A13F458
-S31508003008001F0CD0194B9B6BC3F30663013300935F
-S3150800301843462A4631463846FFF7F4FEA06002B012
-S31508003028BDE8F081114B1B6813F0040F14D00F4B41
-S315080030381B68C3F3C1030E4FDF40A3E70B4B1B689E
-S3150800304813F4807F0AD100279CE7084B1B6813F402
-S31508003058003F05D1002795E7002793E7054F91E735
-S31508003068054F8FE74FF00008A0E700BF0044025855
-S315080030780090D00300093D0000127A002DE9F041BE
-S3150800308882B0434B9B6A03F00303012B69D0002BDC
-S315080030985BD0022B6CD00025002303604360836055
-S315080030A83B4B9C6AC4F305541A6CC2F30802561CB7
-S315080030B8DB6A13F4807F68D0354B5F6CC7F3CC079F
-S315080030C82B1C18BF0123002C08BF0023002B39D05E
-S315080030D880462F4BDB6A13F4800F0DD02C4B1B6CE4
-S315080030E8C3F34623013300933B4632462146284616
-S315080030F8FFF788FEC8F80000254BDB6A13F4000FB3
-S315080031080DD0234B1B6CC3F30643013300933B4690
-S31508003118324621462846FFF775FEC8F804001C4BB8
-S31508003128DB6A13F0807F0DD0194B1B6CC3F306635B
-S31508003138013300933B46324621462846FFF762FE8E
-S31508003148C8F8080002B0BDE8F081114B1B6813F0F7
-S31508003158040F14D00E4B1B68C3F3C1030D4DDD4095
-S315080031689AE70B4B1B6813F4807F0AD1002593E76F
-S31508003178074B1B6813F4003F05D100258CE700258B
-S315080031888AE7054D88E7054D86E7002798E700BFD3
-S31508003198004402580090D00300093D0000127A0046
-S315080031A8154B1B6903F03803182B0ED8DFE803F014
-S315080031B80F0D0D0D0D0D0D0D210D0D0D0D0D0D0D13
-S315080031C8160D0D0D0D0D0D0D1800002070470A4B34
-S315080031D81B68C3F3C1030948D840704708487047B5
-S315080031E800B585B001A8FFF735FE019805B05DF86A
-S315080031F804FB0448704700BF004402580090D003F7
-S3150800320800127A0000093D00044B9B6903F00F037E
-S31508003218034AD35C03F01F03D8407047004402589A
-S3150800322860620008044BDB69C3F30213034AD35CE4
-S3150800323803F01F03D840704700440258606200082C
-S31508003248044BDB69C3F30223034AD35C03F01F0369
-S31508003258D8407047004402586062000800B585B037
-S31508003268C2B24C4BD358020EC0F304218A4013400D
-S31508003278CB4040EA0340484B984228D02ED8A3F5BD
-S315080032888133A3F5807398425DD019D8A3F58033A6
-S31508003298984248D003F5407398422ED1FFF780FF2D
-S315080032A83E4B9B69C3F303233D4AD35C03F01F03D4
-S315080032B8D840FFF7A9FFFFF7C3FF05B05DF804FB81
-S315080032C8384B98423FD003F57D43984215D1334B86
-S315080032D81B6813F0005F42D10020EEE7324B984294
-S315080032E842D00CD9314B984245D003F540739842E1
-S315080032F841D0A3F58033984236D00020DDE7A3F500
-S315080033088033984203D003F540739842F5D1234B8E
-S315080033181B6813F0040F35D0204B1B68C3F3C10391
-S315080033282348D840C9E7FFF73BFF1C4B9B69C3F303
-S3150800333803231B4AD35C03F01F03D840FFF764FF37
-S31508003348FFF770FFB9E7154B1B6813F0006F01D13B
-S315080033580020B2E701A8FFF707FE0298ADE701A823
-S31508003368FFF78CFE0298A8E70C4B1B6813F4807FBE
-S315080033780AD10020A1E7094B1B6F13F0020F05D1EC
-S3150800338800209AE7002098E70A4896E74FF4004095
-S3150800339893E700BF4C440258080302070044025842
-S315080033A86062000808030107080004070800050703
-S315080033B80090D00300093D0038B5036813F0010FE3
-S315080033C840F08C800D4604460368454A1A408B68C7
-S315080033D809690B4369690B43E9690B43134303609E
-S315080033E8EB68426822F4405213434360AB6982682B
-S315080033F822F44072134383603A4B984216D03A4BEC
-S3150800340898421CD0394B98421DD0394B98421ED049
-S31508003418384B98421FD0384B984220D0374B9842A1
-S3150800342821D0374B984222D001204EE03548FFF785
-S3150800343815FF002848D06A68EAB9012045E03248ED
-S31508003448FFF70CFFF5E73048FFF708FFF1E72E48C6
-S31508003458FFF704FFEDE72C48FFF700FFE9E72948DF
-S31508003468FFF7FCFEE5E72848FFF7F8FEE1E72648F8
-S31508003478FFF7F4FEDDE72B68E9690B2B2CD8B1F5C5
-S31508003488004F0DD0DBB2214951F82330B0FBF3F3D6
-S3150800349803EB5203B3FBF2F39BB2E360002014E09C
-S315080034A8DBB21A4951F82330B0FBF3F0530803EBA3
-S315080034B84000B0FBF2F34FF6F0721A40C3F342032A
-S315080034C81343E360002000E00120E26A22F00F02BD
-S315080034D82B881343E36238BD0020F6E70120FAE794
-S315080034E8F369FFEF0010014000440040004800401F
-S315080034F8004C00400050004000140140007800408D
-S31508003508007C0040080300070800000770620008EE
-S31508003518002301330C4A934211D80269002AF8DAC3
-S31508003528036943F00103036100230133064A934202
-S3150800353807D8026912F0010FF7D100207047032057
-S3150800354870470320704700BF400D030084B010B5CC
-S31508003558044603A880E80E00089B012B1DD1A36B1F
-S3150800356823F48033A363E2681A4B1340E360E368E5
-S3150800357823F44013E3600F9B012B09D02046FFF77D
-S31508003588C7FF069B012B1BD0BDE8104004B0704747
-S31508003598E36843F48013E360F0E7E36843F0400325
-S315080035A8E3602046FFF7B4FF0C9B23B9A36B43F4EB
-S315080035B88033A363E5E7A36B23F48033A363E0E7CB
-S315080035C8A36843F00603A360A36843F02003A36037
-S315080035D8DAE700BFBFFFBDFF022A0AD00921C26881
-S315080035E822F47052C260C36843EA8123C36000208C
-S315080035F87047274B0B44274A934239D9264B0B4425
-S31508003608264A934236D9264B0B44264A934233D93F
-S31508003618254B0B4402F5C332A03293422ED9234BCD
-S315080036280B44234A93422BD9224B0B4402F5922288
-S3150800363802F57872934225D91F4B0B4402F5C3222B
-S3150800364802F5207293421FD91C4B0B4402F5B71298
-S3150800365802F55872934219D9194B0B4402F51222EE
-S3150800366802F5F862934201D90621B8E70721B6E7B9
-S315080036780F21B4E70E21B2E70D21B0E70C21AEE71A
-S315080036880B21ACE70A21AAE70921A8E70821A6E73A
-S31508003698405327FFFF340C00401E1BFF3F420F0014
-S315080036A800DC0BFF7F4F1200808CF9FE60B6E5FE42
-S315080036B85FE3160000D3CEFEC05BB3FE00CA91FED8
-S315080036C8E05459FE836843F001038360002070477D
-S315080036D8836823F0010383600020704708B5C36830
-S315080036E823F0C043C360012909D069B9C36843F008
-S315080036F88043C3603220FDF70FFA002008BDC3686F
-S3150800370843F00053C360F5E70120F7E7890141F064
-S315080037182001016100230133054A934205D802694D
-S3150800372812F0200FF7D1002070470320704700BF1A
-S31508003738400D03001023036100230133054A934211
-S3150800374805D8026912F0100FF7D100207047032038
-S31508003758704700BF400D0300D0F800381943C0F879
-S31508003768001800207047000084B02DE9F04104468F
-S3150800377807A880E80E002546002306E003F1400264
-S3150800378804EB82020021516001330E2BF6D9119BF6
-S3150800379823BBD4F8043843F00203C4F80438A36BEF
-S315080037A823F40013A363236843F0400323602368C4
-S315080037B843F0800323600023C4F8003E04F500663E
-S315080037C8D4F80038C4F800380C9B012B10D1099B93
-S315080037D84BB900212046FFF7BFFF0DE0A36B43F462
-S315080037E80013A363E7E701212046FFF7B5FF03E0C7
-S315080037F803212046FFF7B0FF10212046FFF786FF72
-S31508003808804608B14FF001082046FFF793FF08B134
-S315080038184FF00108002333617361F3610AE0C3B905
-S315080038284FF00060C2F8000900220A614FF67F329D
-S315080038388A6001330799994210D905EB431202F5B4
-S315080038481061D2F800090028E9DB0020C2F800094F
-S31508003858EAE74FF09040C2F80009E5E700230AE0D6
-S31508003868BBB14FF09047C2F8007B002202614FF6C1
-S315080038787F3282600133994210D905EB431202F56B
-S315080038883060D2F8007B002FEADB0027C2F8007BFD
-S31508003898EBE74FF00067C2F8007BE6E7336923F4E5
-S315080038A8807333610023A3616FF0804363610A9BC9
-S315080038B81BB9A36943F01003A361A2690A4B134312
-S315080038C8A3610D9B1BB1A36943F00803A361119B70
-S315080038D8012B04D04046BDE8F04104B07047A26900
-S315080038E8024B1343A361F5E700383C800400004007
-S315080038F8D0F8083813F0060305D0062B18BF022B94
-S3150800390803D102207047002070470F207047000037
-S3150800391870B40B784A78012A20D0D0F81C2803F00E
-S315080039280F060124B44042EA0442C0F81C2800EBFA
-S315080039384310D0F8003B13F4004F0CD1D0F8002BF5
-S315080039488B68C3F30A03C97843EA81431343134AC6
-S315080039581A43C0F8002B002070BC7047D0F81C48E2
-S3150800396803F00F06B24092B22243C0F81C2800EBB7
-S315080039784310D0F8002912F4004FECD1D0F80049CA
-S315080039888A68C2F30A02C97842EA814242EA83533C
-S315080039982343024A1A43C0F80029DCE700800010CE
-S315080039A830B40B784A78012A24D000EB4313D3F8AD
-S315080039B8002B002A50DBD0F83C580A7802F00F0290
-S315080039C8012404FA02F225EA0242C0F83C28D0F893
-S315080039D81C28097801F00F018C4022EA0444C0F833
-S315080039E81C48D3F8001B234A0A40C3F8002B0020BA
-S315080039F830BC704700EB4313D3F80029002A1EDBB6
-S31508003A08D0F83C580A7802F00F02012404FA02F2A8
-S31508003A1892B225EA0202C0F83C28D0F81C28097890
-S31508003A2801F00F018C40A4B222EA0404C0F81C482D
-S31508003A38D3F80019104A0A40C3F80029D7E7D3F87B
-S31508003A48002942F00062C3F80029D3F8002942F099
-S31508003A588042C3F80029D3E7D3F8002B42F0006266
-S31508003A68C3F8002BD3F8002B42F08042C3F8002B8A
-S31508003A78A1E700BF0078F3EF007833EC70B40B7851
-S31508003A884C78012C24D000EB431000F530631D69EF
-S31508003A983E4C2C401C611D693D4C2C401C614C69F0
-S31508003AA80CB18C684C611C6944F400241C611C69BF
-S31508003AB88D68C5F312052C431C61012A61D0D0F81C
-S31508003AC8003B43F00443C0F8003B002070BC704735
-S31508003AD84C695CBB00EB4314D4F810692C4D35408F
-S31508003AE8C4F81059D4F8105945F40025C4F81059E3
-S31508003AF8D4F81069254D3540C4F81059012A31D033
-S31508003B0800EB4313D3F8002942F00442C3F800290E
-S31508003B184B69002BD9D0D0F83428097801F00F045E
-S31508003B280121A1400A43C0F83428CEE700EB431424
-S31508003B3804F510642669154D354025612669144D26
-S31508003B48354025614E698D68AE4200D94D612569B3
-S31508003B5845F40025256125694E69C6F312063543DD
-S31508003B682561CBE70A691AB100EB4311C1F8142994
-S31508003B7800EB4310D0F8002942F00442C0F80029A7
-S31508003B88A3E7CA68002A9AD05A6198E70000F8FF9E
-S31508003B98FFFF07E070B49DF80C4064B903339D082D
-S31508003BA807E000EB023303F5805351F8046B1E60F7
-S31508003BB80134AC42F5D3002070BC7047F0B583B029
-S31508003BC80B784C78012C29D000EB431303F53064A5
-S31508003BD826697D4D3540256126697C4D3540256128
-S31508003BE84D69002D40F0C18025698E68C6F3120616
-S31508003BF835432561256945F400252561012A00F024
-S31508003C08C980CA78012A00F0CB80D3F8002B42F085
-S31508003C180442C3F8002B002003B0F0BD4C6974BBFE
-S31508003C2800EB4314D4F81069684D3540C4F81059A8
-S31508003C38D4F8105945F40025C4F81059D4F8106971
-S31508003C48614D3540C4F81059012A4AD000EB431390
-S31508003C58D3F8004944F00444C3F80049CC78012C49
-S31508003C6868D04B69002BD6D0D0F83428097801F0EB
-S31508003C780F040121A1400A43C0F83428CBE700EB1A
-S31508003C884314D4F81069504D3540C4F81059D4F87F
-S31508003C9810694E4D3540C4F81059D4F810694D6965
-S31508003CA88F683D44013DB5FBF7F5494F07EAC54519
-S31508003CB83543C4F81059D4F810594E69C6F3120694
-S31508003CC83543C4F8105904F51064CD78012DBBD1D5
-S31508003CD8256925F0C0452561256945F00055256102
-S31508003CE8B2E70A691AB100EB4314C4F81429CA786A
-S31508003CF8012A08D000EB4313D3F8002942F00442FE
-S31508003D08C3F8002987E7D0F8082812F4807F08D175
-S31508003D1800EB4311D1F8002942F00052C1F80029F6
-S31508003D28E8E700EB4311D1F8002942F08052C1F8C0
-S31508003D380029DFE7D0F8084814F4807F0ED1D3F8B5
-S31508003D48004944F00054C3F8004914460B46C968AC
-S31508003D581A789B8A0094FFF71DFF5CE7D3F8004999
-S31508003D6844F08054C3F80049EFE78E683544013DAE
-S31508003D78B5FBF6F52669164F07EAC5473E43266199
-S31508003D8827698E68ADB206FB05F5C5F312053D43EE
-S31508003D98256133E7CA68002A3FF433AF626130E722
-S31508003DA8D0F8082812F4807F06D1D3F8002B42F001
-S31508003DB80052C3F8002B28E7D3F8002B42F08052AC
-S31508003DC8C3F8002B21E700BF0000F8FFFFFF07E054
-S31508003DD80000F81F03329208002393420CD210B44D
-S31508003DE800F58054246841F8044B01339342F7D30D
-S31508003DF808465DF8044B7047084670470B784A78BA
-S31508003E08012A14D000EB4310D0F8002B002A06DB51
-S31508003E182BB1D0F8003B23F08043C0F8003BD0F81C
-S31508003E28003B43F40013C0F8003B0020704700EB42
-S31508003E384310D0F80029002A06DB2BB1D0F8003940
-S31508003E4823F08043C0F80039D0F8003943F400134A
-S31508003E58C0F80039E9E70B784A78012A0ED000EB52
-S31508003E684310D0F8003B23F40013C0F8003BCB7886
-S31508003E78023BDBB2012B15D90020704700EB431033
-S31508003E88D0F8003923F40013C0F80039CB78023B80
-S31508003E98DBB2012BF0D8D0F8003943F08053C0F8CC
-S31508003EA80039E9E7D0F8003B43F08053C0F8003BF7
-S31508003EB8E2E738B505460446002208E004EB421353
-S31508003EC84FF67F31C3F80819C3F8081B01320E2AC2
-S31508003ED8F4D90022C5F81028C5F81428C5F81C28EE
-S31508003EE82846FFF727FC034608B1184638BD1021AF
-S31508003EF82846FFF70BFC0346F7E7D0F8003823F403
-S31508003F08FE63C0F80038D0F80038090101F4FE61EC
-S31508003F180B43C0F800380020704708B5D0F80438B5
-S31508003F2823F00203C0F804380320FCF7F5FD002047
-S31508003F3808BD08B5D0F8043843F00203C0F80438B9
-S31508003F480320FCF7E9FD002008BD42698069104096
-S31508003F587047D0F8183800F50060C0691840000C9A
-S31508003F687047D0F8183800F50060C069184080B264
-S31508003F78704700EB4111D1F8082B00F5006040693D
-S31508003F881040704710B4D0F81048D0F8343801F00B
-S31508003F980F02D340DB01DBB2234300EB411000F5E7
-S31508003FA81060806818405DF8044B7047406900F057
-S31508003FB801007047D0F80029054B1340C0F80039AE
-S31508003FC8D0F8043843F48073C0F8043800207047E2
-S31508003FD800F8FFFF10B4046C154B9C4203D9D0F8BF
-S31508003FE8003B002B16DB0024C0F8104BD0F8104B0A
-S31508003FF844F40024C0F8104BD0F8104B44F01804C9
-S31508004008C0F8104BD0F8104B44F0C044C0F8104B19
-S31508004018012903D000205DF8044B7047C0F8142B1B
-S31508004028D0F8003B43F08023C0F8003BF2E700BF16
-S315080040380A30544F014B1860704700BF000000242F
-S31508004048C0B108B50346D0F8B80210B10020C3F8C5
-S31508004058B802D3F8CC0210B10020C3F8CC0209B1D3
-S31508004068C3F8B4121846012380F89C32027001F08E
-S31508004078C3FF08BD0320704710B50446012380F81E
-S315080040889C32D0F8B83213B15B6801799847D4F8EE
-S31508004098CC3213B10023C4F8CC32204602F01EF8FD
-S315080040A8034608B1184610BD204602F007F803462D
-S315080040B8F8E710B582B00023ADF8063059B10446C2
-S315080040C8C4F8B812CB6A0DF106009847C4F8CC02B2
-S315080040D8002002B010BD0320FBE708B501F0F6FF83
-S315080040E808BD08B5D0F8B83213B11B68984708BD9B
-S315080040F80320FCE708B5D0F8B8320BB15B689847D7
-S31508004108002008BD38B5044600F2AA25284600F05E
-S315080041182DF90123C4F89432B4F8B032C4F89832A9
-S3150800412894F8AA1201F01F03012B0DD03BB1022BFC
-S315080041380FD001F08001204601F0EBFF03E0294685
-S31508004148204600F0CEFA38BD2946204600F004FB82
-S31508004158F9E72946204600F033FBF4E710B504468C
-S3150800416829BB1346D0F89422032A01D0002029E057
-S31508004178D0F85C11D0F8602191420DD8D0F8B83241
-S315080041881B6923B190F89C22032A00D19847204638
-S3150800419800F067FC002015E0891AC0F85C118A420D
-S315080041A828BF0A46194600F054FC00200AE00A46C9
-S315080041B8D0F8B8329B6933B190F89C12032904D118
-S315080041C81146984710BD0320FCE70320FAE710B507
-S315080041D80446002946D11346D0F89422022A05D067
-S315080041E894F8A032012B39D0002046E0C269016A4A
-S315080041F88A4213D88A421DD0D4F8B832DB682BB164
-S3150800420894F89C22032A01D1204698478021204603
-S3150800421801F07FFF204600F02FFCE1E7521AC26141
-S31508004228194600F00EFC00231A461946204601F0E6
-S3150800423890FFD5E783699942DED8D0F89822934249
-S31508004248DAD20022114600F0FCFB0021C4F89812C5
-S315080042580B460A46204601F07CFFC1E7002084F891
-S31508004268A0020AE00A46D0F8B8325B6933B190F87A
-S315080042789C12032904D11146984710BD0320FCE770
-S315080042880320FAE770B50446012380F89C32002318
-S31508004298C0F894324360C0F8A432D0F8BC3223B1CF
-S315080042A8D0F8B8325B6800219847402300221146A7
-S315080042B8204601F01BFF0126A4F864614025C4F8CE
-S315080042C860512B4600228021204601F00FFFA68464
-S315080042D82562002070BD01740020704790F89C3252
-S315080042E880F89D32042380F89C320020704790F8A5
-S315080042F89C32042B01D00020704790F89D3280F834
-S315080043089C32F8E708B590F89C32032B01D00020B8
-S3150800431808BDD0F8B832DB69002BF8D09847F6E71D
-S3150800432800207047002070470020704708B5012311
-S3150800433880F89C32D0F8B83213B15B68017998478F
-S31508004348002008BD002302E00133DBB20130027801
-S31508004358002AF9D11846704708B54B88012B00D0B2
-S3150800436808BDC0F8A43200F07CFBF9E70B780370A7
-S315080043784B7843708B78CA7843EA022343800B79D3
-S315080043884A7943EA022383808B79CA7943EA022366
-S31508004398C380704710B50446802101F0BAFE002193
-S315080043A8204601F0B6FE10BD30B583B004460D466A
-S315080043B80023ADF806304A88130A013B062B00F29B
-S315080043C8AB80DFE803F0041F33A9A98D9A00D0F85B
-S315080043D8B4321B680DF10601007C9847EA88002A62
-S315080043E800F0A380BDF80630002B00F099809A42A9
-S315080043F828BF1A46ADF806200146204600F014FBE9
-S3150800440803B030BD037C43B9D0F8B8329B6A0DF1C6
-S315080044180600984702234370E0E7D0F8B832DB6A0B
-S315080044280DF10600984702234370D7E7D2B2052A4A
-S3150800443852D8DFE802F003101D2A3744D0F8B43200
-S315080044485B6823B10DF10601007C9847C6E7294643
-S31508004458FFF7A0FFD4E7D0F8B4329B6823B10DF173
-S315080044680601007C9847B9E72946FFF793FFC7E78F
-S31508004478D0F8B432DB6823B10DF10601007C984701
-S31508004488ACE72946FFF786FFBAE7D0F8B4321B69C6
-S3150800449823B10DF10601007C98479FE72946FFF7E7
-S315080044A879FFADE7D0F8B4325B6923B10DF106019F
-S315080044B8007C984792E72946FFF76CFFA0E7D0F8F3
-S315080044C8B4329B6923B10DF10601007C984785E74C
-S315080044D82946FFF75FFF93E72946FFF75BFF8FE754
-S315080044E8037C33B9D0F8B8325B6B0DF106009847F0
-S315080044F874E72946FFF74EFF82E7037C43B9D0F8ED
-S31508004508B8321B6B0DF1060098470723437065E719
-S315080045182946FFF73FFF73E72946FFF73BFF6FE793
-S3150800452829462046FFF736FF6AE7204600F099FA3B
-S3150800453866E738B504468B88F3B9CB88E3B94B8860
-S315080045487F2B19D803F07F0590F89C32032B0CD0E3
-S3150800455880F89E52294601F0ECFD204600F081FAC3
-S3150800456835B1022384F89C3209E0FFF713FF06E009
-S31508004578012384F89C3202E02046FFF70BFF38BD7A
-S3150800458870B504460D4689782E4B197001290FD83F
-S3150800459890F89C32022B11D0032B25D02946FFF719
-S315080045A8F9FE284B19782046FFF7A4FD032603E0F1
-S315080045B82946FFF7EFFE0326304670BD81B14160F4
-S315080045C8FFF78FFD064620B129462046FFF7E2FE8B
-S315080045D8F2E7204600F045FA032384F89C32EBE715
-S315080045E800F03FFA0026E7E7C9B14368994225D0A3
-S315080045F8D9B2FFF77FFD134B197861602046FFF79C
-S3150800460870FD0646B0B129462046FFF7C3FE217954
-S315080046182046FFF76FFD022384F89C32CCE7022375
-S3150800462880F89C324160FFF765FD204600F019FACC
-S315080046380026C1E7204600F014FABDE700F011FA93
-S315080046480026B9E7EC00002408B5CB88012B0BD166
-S3150800465890F89C329BB1022B09D9032B0FD1012262
-S31508004668011D00F0E1F901E0FFF794FE08BD0146D7
-S31508004678002341F8083F012200F0D6F9F6E7FFF7CC
-S3150800468889FEF3E708B590F89C32013B022B12D84D
-S31508004698CB88022B0CD10123C360D0F8A4320BB106
-S315080046A80323C360022200F10C0100F0BDF908BD1E
-S315080046B8FFF770FEFBE7FFF76DFEF8E708B590F819
-S315080046C89C32013B022B09D84B88012B00D008BD28
-S315080046D80023C0F8A43200F0C4F9F8E7FFF75AFE39
-S315080046E8F5E708B50B7803F06003202B06D0402BB6
-S315080046F804D043B1FFF74EFE002003E0D0F8B832E5
-S315080047089B68984708BD4B78092B21D8DFE803F042
-S31508004718141C201820090520100DFFF745FE002057
-S31508004728F0E7FFF706FF0020ECE7FFF729FFE9E7C0
-S31508004738FFF78AFF0020E5E7FFF7A4FF0020E1E777
-S31508004748FFF70AFE0020DDE7FFF7B8FF0020D9E7E4
-S31508004758FFF720FE0020D5E770B505460C460B780E
-S3150800476803F06003202B07D0402B05D023B1FFF7B1
-S3150800477811FE0026304670BD95F89C32013B022B87
-S3150800478818D82379012B0FD8D5F8B8329B68214653
-S31508004798284698470646E388002BEBD10028E9D136
-S315080047A8284600F05EF9E5E721462846FFF7F2FDB8
-S315080047B80026DFE721462846FFF7ECFD0026D9E75D
-S315080047C838B505460C468A880B7803F06003202B13
-S315080047D808D0D1B2402B05D05BB12146FFF7DAFDE8
-S315080047E8002005E0D5F8B8329B6821462846984740
-S315080047F838BD6378012B38D0002B6BD0032B40F0DB
-S31508004808F08090F89C32022B06D0032B19D021464B
-S31508004818FFF7C0FD0020EBE7B1F1800318BF0123BD
-S31508004828002908BF00233BB101F073FC8021284604
-S3150800483801F06FFC0020DBE72146FFF7ABFD0020FF
-S31508004848D6E763884BB9B1F1800318BF012300295D
-S3150800485808BF00230BB1E38823B1284600F001F905
-S315080048680020C5E701F055FCF7E790F89C32022BC3
-S3150800487806D0032B19D02146FFF78CFD0020B7E791
-S31508004888B1F1800318BF0123002908BF00233BB1F3
-S3150800489801F03FFC8021284601F03BFC0020A7E7F1
-S315080048A82146FFF777FD0020A2E76388002B40F032
-S315080048B89D8011F07F0F0AD1284600F0D2F8D5F866
-S315080048C8B8329B68214628469847002090E701F0A9
-S315080048D828FCF1E790F89C32022B06D0032B2FD040
-S315080048E82146FFF757FD002082E7B1F1800318BF7C
-S315080048F80123002908BF00239BB912F0800F15D1A0
-S3150800490801F07F0101EB81018B0003F5A8710144D1
-S31508004918043100240C600222284600F085F8204657
-S3150800492866E72146FFF736FD002061E701F07F01BB
-S3150800493801EB81018B0003F1100101440431E8E71A
-S3150800494852B2002A24DB01F00F0303EB8303980015
-S315080049582844B0F8643153B3002A2EDB01F07F02ED
-S3150800496802EB8202930003F5A8742C4404348029C8
-S3150800497814BF00230123002908BF01233BB30023E2
-S31508004988236002222146284600F04EF800202FE729
-S3150800499801F00F0303EB830398002844838C002B4C
-S315080049A8DAD121462846FFF7F5FC002020E72146FC
-S315080049B82846FFF7EFFC00201AE701F07F0202EB12
-S315080049C88202930003F110042C440434CFE72846E6
-S315080049D801F04EFB10B101232360D2E700232360C0
-S315080049E8CFE72146FFF7D6FC002001E70020FFE6BF
-S315080049F8C8B170B50D4616460446FFF7A3FC013044
-S31508004A0840003080287003236B70022307E0EA54BD
-S31508004A1801345A1CD2B20021A9540233DBB22278D7
-S31508004A28002AF4D170BD704710B513460222C0F8A3
-S31508004A3894228361C3610A46002101F082FB0020A3
-S31508004A4810BD08B513460A46002101F07AFB002076
-S31508004A5808BD08B513460A46002101F07AFB00206E
-S31508004A6808BD08B50423C0F8943200231A46194627
-S31508004A7801F067FB002008BD08B50523C0F8943285
-S31508004A8800231A46194601F064FB002008BD72B6D1
-S31508004A98704762B670470000F0B4194D2C6D24F0C3
-S31508004AA840542C65002401E00134E4B2112C23D8C3
-S31508004AB8144D15F8146005EB44056F78F51905FBD0
-S31508004AC800054FF4FA5CBCFBF5FC05FB0CF5B5F5DF
-S31508004AD8FA5FE9D135463D4405FB000C4FF4FA5513
-S31508004AE8B5FBFCF50D80013DADB2B5F5007FDBD20F
-S31508004AF816701F70012000E00020F0BC704700BF48
-S31508004B0800440258DC62000870B58AB00022ADF885
-S31508004B1826208DF825200AAB03F8042D0DF1250269
-S31508004B280DF126014FF4FA70FFF7B6FF00283CD0BE
-S31508004B38204C214B23600025A560E56001262674D4
-S31508004B486574A574BDF826306361A6619DF825309D
-S31508004B58E3619DF8243023626662A662E6622663EC
-S31508004B686563A663E563256404236364A564E3644F
-S31508004B7826656365A565E66525666566A3662046B2
-S31508004B88FCF762F90195029503960723049340F208
-S31508004B98676305930693079501A92046FCF79EFACD
-S31508004BA82046FCF7DEFA0AB070BDB821034800F0C3
-S31508004BB88BFDBDE7F000002400A00040A0620008B5
-S31508004BC810B58AB040F2E173019300230293039368
-S31508004BD809040491059306930793089352230993A6
-S31508004BE80123024601A90E48FCF7D5FA08B10AB00E
-S31508004BF810BD01210A48FCF704FB0028F7D100F08C
-S31508004C0871FB00F1320401210548FCF712FC002863
-S31508004C18EDD000F063FE00F065FBA042F3D9E6E7A5
-S31508004C28F000002430B58BB004460D460021104824
-S31508004C38FCF7D8FB10B900200BB030BD23466A46EE
-S31508004C4800210B48FCF7F0FA68B9009A40F2676346
-S31508004C589A4201D00020EFE7019B33B99DF80E3040
-S31508004C682B700120E8E70020E6E70020E4E700BF0C
-S31508004C78F000002408B5FFF70AFF08BD10B500F0D4
-S31508004C883DFA00B910BDFBF72BFB0028FAD000F057
-S31508004C98CFFDFBF79DFE00F0FBFA00F033FA054B53
-S31508004CA80340054A936000F02DFA4468FFF7F1FEC1
-S31508004CB8A047E7E780FFFF1F00ED00E070B508E0B2
-S31508004CC84D1C461C0B78037000F008FE3046294632
-S31508004CD82246531E9CB2002AF2D170BD38B5054645
-S31508004CE8002401E00134E4B20E2C12D800F0F6FDD7
-S31508004CF804EB44029300084AD358AB42F2D804EBB3
-S31508004D0844029100044A0A4452681344AB42E9D95A
-S31508004D1800E0FF24204638BD0063000808B5C1F343
-S31508004D28090353B903688B4209D040F8041B4FF4AA
-S31508004D388062FFF7C3FF012000E0002008BD0120BC
-S31508004D48FCE72DE9F04107460068FFF7C7FFFF288B
-S31508004D582DD0FCF777FB00264FF0010805E04FF049
-S31508004D680008B8F1000F1DD001361F2E1AD83D6865
-S31508004D78740125443C44043400F0B0FD2246294613
-S31508004D880120FCF727FC58B900231F2BE9D8595DE1
-S31508004D98C9B2E25CD2B29142E1D10133DBB2F4E79F
-S31508004DA84FF00008FCF77CFB4046BDE8F0814FF061
-S31508004DB80008F9E770B50E460E4B984212D004461D
-S31508004DC80D4B994209D10B4D2C4625B13146204643
-S31508004DD8FFF7A4FF58B1284670BDFFF7B2FF20B108
-S31508004DE82546F2E7054D2C46EFE70025EDE70025B1
-S31508004DF8F1E700BF9405002400000208900100248A
-S31508004E082DE9F84305460C4617461E46DFF8848002
-S31508004E1801EA08080368B3F1FF3F0AD02B6843453F
-S31508004E280ED14FF00109B9F1010F12D04846BDE875
-S31508004E38F8834146FFF772FF81460028F3D0EDE76D
-S31508004E4841462846FFF7B6FF0546E8B14FF001097F
-S31508004E58E9E72B68E41A2C44043405E017F8013B03
-S31508004E6804F8013B013EE1D000F038FD2B1DE31A9A
-S31508004E78B3F5806FF2D308F580612846FFF79AFFE5
-S31508004E88054620B1041DE9E74FF00009CEE74FF0C3
-S31508004E980009CBE700FCFFFF70B586B004460D464F
-S31508004EA800230093884203D80E2937D8012600E044
-S31508004EB8002616B9304606B070BDFCF7C3FAAC42F0
-S31508004EC827D800F00BFD1649630023449A008B186F
-S31508004ED88A585B68002B18BFB2F1FF3F18D0002329
-S31508004EE80193202305930A4663001819810008468A
-S31508004EF81144497A02910244137A039301230493CD
-S31508004F08694601A8FCF736FC30B90134E4B2D6E79D
-S31508004F180026FCF7C5FACDE70026FAE70026C9E712
-S31508004F28006300084FF0FF33024A1360024A136011
-S31508004F38704700BF900100249405002470B5044604
-S31508004F480D4616464A1E154B1B1A9A4203D90020C7
-S31508004F5801280CD070BDFFF7C1FEFF281AD0281902
-S31508004F680138FFF7BBFEFF2816D00120F0E70C4BE7
-S31508004F7823400C4A934206D02B46324621460A4815
-S31508004F88FFF73EFFE6E72B46324621460748FFF776
-S31508004F9837FFDFE70020DDE70020DBE7FFFF1F0814
-S31508004FA800FCFFFF00000208900100249405002475
-S31508004FB870B54A1E0F4B1B1A9A4205D9FF210E4691
-S31508004FC80020012812D070BD05460C46FFF786FE5C
-S31508004FD8064660190138FFF781FE0146FF2818BF03
-S31508004FE8FF2E01D00120ECE70020EAE73046FFF75C
-S31508004FF853FFE8E7FFFF1F08104B1B68B3F1FF3F95
-S315080050081AD000B583B00D4A536891680B44D16825
-S315080050180B4411690B4451690B4491690B44D269D5
-S3150800502813445B4202AA42F8043D04210448FFF7E8
-S3150800503885FF03B05DF804FB01207047940500243A
-S31508005048980202080D4B1B680D4A12681A440D4B44
-S315080050581B6813440C4A126813440C4A12681A440B
-S315080050680B4B1B681A440B4B1B6813440A4A1268F5
-S31508005078DA4201D000207047012070470000020874
-S3150800508804000208080002080C00020810000208BA
-S3150800509814000208180002089802020808B50D4B01
-S315080050A81B68B3F1FF3F0BD10B4B1B68B3F1FF3FEE
-S315080050B80DD00948FFF745FE034648B1012307E026
-S315080050C80448FFF73EFE03460028EDD100E0012319
-S315080050D8184608BD94050024900100240048704726
-S315080050E80000020808B5FFF71DFF08BD08B5FFF759
-S315080050F825FF08BD08B5FFF75BFF08BD08B5FFF72C
-S31508005108A1FF08BD08B5FFF7E9FF08BD08B5FFF711
-S3150800511873FF034608B9184608BDFFF7BFFF0346DD
-S31508005128F9E70000054BDB6913F0200F04D0034BA1
-S315080051385B6A0370012070470020704700480040EA
-S3150800514810B5094B986200F0CDF800F10A04064B31
-S31508005158DB6913F0800F05D100F0C0FB00F0C2F838
-S31508005168A042F4D910BD00BF0048004010B588B069
-S315080051780D4C236823F001032360002300934FF4A2
-S31508005188614201920293039304930C2205920693B3
-S31508005198079369462046FEF70FF9236843F001038B
-S315080051A8236008B010BD00BF0048004070B5064629
-S315080051B80D46402904D82846FFF7C2FF00240BE00D
-S315080051C88421074800F080FAF5E700F087FB305D90
-S315080051D8FFF7B6FF0134A4B2ABB2A342F5D870BD47
-S315080051E8B463000870B5254B1C78BCB92448FFF78A
-S315080051F899FF012801D0204670BD214B1B78013B39
-S31508005208DBB23F2BF7D800F06DF81E4B18601E4B23
-S3150800521800221A70194B01221A70ECE706460D4649
-S31508005228194B1B78013316481844FFF77BFF0446C9
-S31508005238012815D1144B1A780132D2B21A70104BBC
-S315080052481B789A4201D00024D5E710493046FFF763
-S3150800525835FD0A4B00221A700B4B1B782B70CAE7D0
-S3150800526800F040F8074B1B686433984203D90024BA
-S31508005278024B1C70BFE70024BDE700BFD90900240C
-S3150800528898090024DC090024DA090024990900246D
-S31508005298024B00221A605A609A60704710E000E0D4
-S315080052A808B5FFF7F5FF054B054A5A6000229A60CC
-S315080052B805211960034B1A6008BD00BF10E000E01D
-S315080052C8FF520700E0090024044B1B6813F4803FCB
-S315080052D803D0034A136801331360704710E000E0EF
-S315080052E8E009002408B5FFF7EFFF014B186808BD69
-S315080052F8E009002408B5FFF7F5FF08BD094B03F1D7
-S315080053081801002232B19A7400225A61064B054ADE
-S315080053181A6070479A745961183318310132D2B233
-S31508005328F0E700BF240A0024540A00240A4B1B6825
-S3150800533883B110B45C69084A146019749860D86017
-S3150800534800225A741860013908445860987C5DF838
-S31508005358044B7047FF207047540A002438B50446A2
-S315080053680D4601281CD862002244D100114B0B4473
-S315080053785A7C1B7C9A4219D00E4B0B44DA68157076
-S315080053885A7C01325A74DA680132DA605B689A42E2
-S315080053980ED9084A084651580244D160012038BD3A
-S315080053A84FF4E171044800F08FF9DCE70020F6E7CE
-S315080053B80120F4E7240A0024F463000808B5014626
-S315080053C8024B1878FFF7CAFF08BD00BF580A002421
-S315080053D838B504460D4601281ED804EB4403DA00FE
-S315080053E8124B13445B7CEBB162002244D1000F4B8D
-S315080053F80B449A6812782A705A7C013A5A749A6841
-S3150800540801329A605B689A420ED9084A084651588A
-S3150800541802449160012006E04FF4F271044800F056
-S3150800542853F9DAE7002038BD0120FCE7240A0024EE
-S31508005438F463000808B50146024B1878FFF7C8FF59
-S3150800544808BD00BF9C0A002410B50446012804D9E3
-S315080054584FF40171044800F037F904EB4404E200FC
-S31508005468024B1344587C10BDF4630008240A002430
-S3150800547838B5FFF743FF1B4C4021601CFFF756FF62
-S315080054882070194D4021681CFFF750FF28702378B3
-S31508005498FF2B1DD0FF281BD0144C00221449204688
-S315080054A8FEF7CEFD13492046FEF703FE0120FAF75C
-S315080054B82EFF2046FEF711FEFDF7CAF9D4F8C402F6
-S315080054C8FCF7F2FF00F02CF9B0F5FA6F05D338BDF2
-S315080054D88521094800F0F8F8DEE74FF4FA6000F08D
-S315080054E819F9F4E7580A00249C0A0024E00A00245B
-S315080054F87800002414000024F463000810B5064C4C
-S31508005508D4F8C402FCF7EEFF2046FEF7B5FD0020E6
-S31508005518FAF7FDFE10BD00BFE00A002470B506467E
-S315080055280D463F2906D82846FFF748FF012806D121
-S3150800553800240BE0BB210D4800F0C6F8F3E7BF21AD
-S315080055480A4800F0C1F8F3E70134A4B2ABB2A342A3
-S315080055580BD900F0C3F9305DFFF730FF0128F3D007
-S31508005568C821024800F0B0F8EEE770BDF4630008F9
-S3150800557870B506460D461F4BD3F8C402FCF720FD46
-S315080055881D4B1C789CB91D48FFF754FF012801D00C
-S31508005598204670BD194B1B78013BDBB23E2BF7D86A
-S315080055A8154B01221A70164B00221A70F0E7144B95
-S315080055B81B78013311481844FFF73CFF04460128B5
-S315080055C801D00024E4E70E4B1A780132D2B21A70D9
-S315080055D80A4B1B789A4201D00024D9E70949304674
-S315080055E8FFF76CFB044B00221A70054B1B782B70CF
-S315080055F8CEE700BFE00A0024F00D0024B00D002411
-S31508005608F10D0024B10D002430B583B0144B187879
-S31508005618FFF71AFF08B30546402800D94025002495
-S3150800562805E09DF807200F4B1A550134E4B2A54248
-S315080056380DD90DF107010A4B1878FFF7C9FE01289D
-S31508005648EFD04FF4A471084800F03EF8E9E72B4676
-S31508005658044A8121054800F074FD03B030BD00BF37
-S31508005668580A0024E4090024F4630008E00A002420
-S3150800567870B5044600F0A8FB064621460F4800F018
-S315080056880EFD85B2002401E00134A4B2AC420CD266
-S31508005698315D0B4B1878FFF761FE0128F4D04FF4FB
-S315080056A8B571084800F010F8EEE700F08DFB4023C6
-S315080056B802460121014800F04CFD70BDE00A0024AD
-S315080056C89C0A0024F463000808B500F007F9FCE70B
-S315080056D808B500F0F7F8012803D00B4B1B78012B07
-S315080056E800D008BDFFF7FEFD084B1B68084A12687C
-S315080056F8134403F5FA739842F3D3034B00221A703E
-S31508005708FFF7BCFAEDE700BFF80D0024F40D0024F6
-S31508005718FC0D0024014B1860704700BFF40D0024E7
-S31508005728014B1868704700BFF40D002408B5054BEF
-S315080057381B78012B00D008BDFFF7D4FD024B186073
-S31508005748F9E700BFF80D0024FC0D002408B5044B42
-S3150800575801221A70FFF7EAFFFFF7BAFF08BD00BF74
-S31508005768F80D002408B5FFF785FA00F0B3F8FFF737
-S3150800577897FDFFF7B7FC00F00DF8FFF7E7FF08BD40
-S3150800578808B500F0ABF8FFF79FFD00F017F8FFF72C
-S315080057989FFF08BD10B500F00FFAFFF7B5F9064CDC
-S315080057A801232370FFF7E2FC00232370FFF760FE4E
-S315080057B80223237010BD00BF1000002400B583B073
-S315080057C80DF107011848FFF72DFA012810D00DF139
-S315080057D807011548FFF706FD012812D00DF1070144
-S315080057E81148FFF7C5FE012814D003B05DF804FB7D
-S315080057F80E4B01221A709DF807100B4800F0FCF9A9
-S31508005808E5E70A4B00221A709DF80710064800F0CB
-S31508005818F3F9E3E7054B02221A709DF807100248C8
-S3150800582800F0EAF9E1E700BF000E002410000024A2
-S3150800583808B5FFF763FE08BD38B504460D460E4B96
-S315080058481B78012B09D00C4B1B7853B10A4B1B78D4
-S31508005858022B0BD000F0C8F938BDC9B2FFF7B0F96A
-S31508005868F1E7E9B22046FFF7A1FCEFE7E9B22046DF
-S31508005878FFF754FEEEE700BF10000024074B1B781D
-S31508005888022B05D0032B05D0012B05D040207047E5
-S315080058983F207047002070470820704710000024F2
-S315080058A8074B1B78022B05D0032B05D0012B05D0F7
-S315080058B8402070473F2070470020704708207047EF
-S315080058C81000002408B500F085F9034600B1012345
-S315080058D8184608BD08B5FAF711FD08BD08B5FAF760
-S315080058E812FD08BD014B00225A707047400E00246D
-S315080058F8034BFE22DA7018710222A3F84420704777
-S31508005908400E002410B5054C00232370FFF7EAFF64
-S31508005918FF23E3700123A4F8443010BD400E002489
-S31508005928064BFF22DA7000221A71597859719A7152
-S31508005938DA711A720622A3F844207047400E00242A
-S3150800594808B50020FFF7D4FF08BD0000074BFF2263
-S31508005958DA70074A9A6400221A715A719A710722EC
-S31508005968C3F807200822A3F844207047400E0024ED
-S3150800597830640008044BFF22DA7042689A640122F0
-S31508005988A3F84420704700BF400E002408B531200C
-S31508005998FFF7AEFF08BD000038B5084CFF23E370D3
-S315080059A8002525716571FFF769FFA071E5712572F4
-S315080059B865720723A4F8443038BD00BF400E00249A
-S315080059C838B5FFF78FFF0E4C01252570FF23E370C6
-S315080059D81023237100236371FFF750FFA071FFF7A7
-S315080059E85FFFE071FFF75CFFC0F30720207265725E
-S315080059F8A5720823A4F84430FFF774FB38BD00BF26
-S31508005A08400E002438B505464478FFF737FF0138B5
-S31508005A18844210DC0A4C6A78A16C201DFFF74EF9FF
-S31508005A28FF23E3706A78A36C1344A3646B78013385
-S31508005A38A4F8443038BD2220FFF75AFFFAE700BF1A
-S31508005A48400E002438B504464578FFF717FF013895
-S31508005A58854211DC61680A4DA9646278281DFFF73A
-S31508005A682DF9FF23EB706278AB6C1344AB6463784B
-S31508005A780133A5F8443038BD2220FFF739FFFAE785
-S31508005A88400E0024F8B505461746002406E015F822
-S31508005A98013B1C44E4B2FFF721FF31464E1E00299C
-S31508005AA8F5D13C600120F8BD10B5084CFF23E3701A
-S31508005AB8E21D4168A06CFFF7E5FF207100236371BA
-S31508005AC8A3710823A4F8443010BD00BF400E002473
-S31508005AD838B505460D4B9C6CFFF7D0FE6A1C411E6F
-S31508005AE82046FFF703FB60B1084CFF23E370FFF776
-S31508005AF8C5FE0138A36C0344A3640123A4F8443003
-S31508005B0838BD3120FFF7F4FEFAE700BF400E00243F
-S31508005B1838B504464578FFF7B1FE023885420EDCEB
-S31508005B28114BFF22DA700122A3F84420617851B993
-S31508005B38FFF7ECFA30B93120FFF7DAFE02E0222047
-S31508005B48FFF7D6FE38BDA21C074B986CFFF7CEFAAE
-S31508005B5828B16178044A936C0B449364F2E73120C0
-S31508005B68FFF7C6FEEEE700BF400E002408B54168F9
-S31508005B78074B986CFFF7BEFA30B1054BFF22DA706F
-S31508005B880122A3F8442008BD3120FFF7B1FEFAE741
-S31508005B98400E002408B5FFF771F8034BFF22DA70A8
-S31508005BA80122A3F8442008BD400E002408B589B28E
-S31508005BB8FFF742FE08BD0000054B00221A709A64DA
-S31508005BC883F84320A3F844209A705A70704700BF98
-S31508005BD8400E0024034B1B780BB1012070470020A8
-S31508005BE8704700BF400E0024024B002283F843206A
-S31508005BF8704700BF400E002408B50378FF2B04D071
-S31508005C08354A1278012A14D008BDFFF7D9FE324B57
-S31508005C1893F84330012B5AD02F4BB3F94410002977
-S31508005C28F2DD1846012380F843300330FFF7BEFF3C
-S31508005C38EAE7C93B352B46D8DFE803F03345454242
-S31508005C4845453F363C394545454545454545454518
-S31508005C5845454545454545454545454545454545DE
-S31508005C68454545454545241E1B2145454527452A9D
-S31508005C782D30FFF7C7FECAE7FFF7E4FEC7E7FFF7C9
-S31508005C8879FEC4E7FFF710FFC1E7FFF75FFEBEE737
-S31508005C98FFF756FEBBE7FFF743FEB8E7FFF732FE06
-S31508005CA8B5E7FFF715FFB2E7FFF732FFAFE7FFF7EC
-S31508005CB873FEACE7FFF75AFFA9E7FFF76BFFA6E7FE
-S31508005CC8FFF764FEA3E72020FFF712FE9FE71020E0
-S31508005CD8FFF70EFEA0E700BF400E0024202303802E
-S31508005CE8004870474C0000240A2303800048704780
-S31508005CF86C00002408B590F89C32032B01D00020CC
-S31508005D0808BDFFF781FCFAE708B5FFF77DFC002018
-S31508005D1808BD08B50846FFF7ABFC002008BD00001B
-S31508005D2808B50B7813F0600F06D14B780A2B14D0F8
-S31508005D380B2B17D0062B01D0002008BD4B881B0A51
-S31508005D48212B04D00B491722FEF76EFEF4E7CA8802
-S31508005D58172A28BF17220849F6E701220749FEF736
-S31508005D6863FEE9E78B7813B9044A1360E4E7FEF79C
-S31508005D7811FBE1E7550000245E0000248C0E002480
-S31508005D8810B50446812100F0BCF90121204600F02F
-S31508005D98B8F9002010BD000010B5044640230222B9
-S31508005DA8812100F0A3F9402302220121204600F0B0
-S31508005DB89DF94023034A0121204600F0CAF900202C
-S31508005DC810BD00BF58130024004870475813002414
-S31508005DD812230B80004870479400002404230B8084
-S31508005DE800487047A80000240023934216D230B40E
-S31508005DF80BE0373401F8134000015C000134002534
-S31508005E080D550133DBB2934206D2040F092CF0D89C
-S31508005E18303401F81340EFE730BC7047704700008C
-S31508005E2838B50A4B186804331C6804331B68C0184D
-S31508005E3800D138BD064D0822A91CFFF7D5FF042254
-S31508005E4805F112012046FFF7CFFFF2E700E8F11F38
-S31508005E58AC00002408B51A230B80FFF7E1FF0148B8
-S31508005E6808BD00BFAC00002408B50A4628B1054994
-S31508005E780548FEF7BDFD034808BD02490248FEF776
-S31508005E88B7FDF8E7981300246864000810B5044CB1
-S31508005E980A4621460348FEF7ABFD204610BD00BF5B
-S31508005EA8981300245864000808B50A4628B1054915
-S31508005EB80548FEF79DFD034808BD02490248FEF756
-S31508005EC897FDF8E7981300243864000808B50A46C9
-S31508005ED828B105490548FEF78BFD034808BD024960
-S31508005EE80248FEF785FDF8E7981300244064000881
-S31508005EF808B500F57171D0F80404FEF703F908BD72
-S31508005F0808B5C1EBC10293000344D3F80822D0F8B8
-S31508005F180404FEF723F908BD08B5C1EBC1029300CE
-S31508005F2803449A6CD0F80404FEF751F908BD08B57D
-S31508005F38D0F80404FEF7E6F908BD000010B50446D3
-S31508005F48C3683BB1022B0FD091210848FFF7BCFB69
-S31508005F58012100E00021D4F80404FEF7BCF9D4F8BE
-S31508005F680404FEF78FF910BD0121F4E77C640008E4
-S31508005F7810B50446D0F80404FEF7B0F92268D2F83A
-S31508005F88003E43F00103C2F8003E236A23B1044ADF
-S31508005F98136943F006031361FAF7BAF910BD00BF8F
-S31508005FA800ED00E010B50446FAF7B3F9D4F804048E
-S31508005FB8FEF79DF910BD08B5D0F80404FEF7B2F946
-S31508005FC808BD08B5D0F80404FEF7AAF908BD10B547
-S31508005FD804460120FAF79BF9D4F80404FEF7A4F955
-S31508005FE810BD10B504460020FAF791F9D4F8040450
-S31508005FF8FEF79CF910BD000003780BB10020704726
-S3150800600810B503461748C0F80434C3F8C402164B3B
-S315080060180360092343600222C26000230361826188
-S315080060280122C261036243628362C3620363FBF7A8
-S3150800603835FE80B90B4C80212046FCF7EEFB402242
-S3150800604800212046FCF7C5FB802201212046FCF7E3
-S31508006058C0FB002010BD4FF493710448FFF734FBCA
-S31508006068E8E700BF900E0024000008407C6400089A
-S31508006078D0F8C43211F0800F08D101F07F01C1EBC6
-S31508006088C1018A00134493F8FE01704701F07F01A5
-S31508006098C1EBC1018A00134493F83E00704708B55E
-S315080060A8D0F8C402FCF7EAFA08BD18B1022803D0EA
-S315080060B803207047002070470120704708B5D0F8BC
-S315080060C8C402FBF7C4FEFFF7F0FF08BD08B5D0F811
-S315080060D8C402FBF77BFEFFF7E8FF08BD08B5D0F852
-S315080060E8C402FBF794FEFFF7E0FF08BD10B51C468F
-S315080060F813462246D0F8C402FCF71AFAFFF7D5FF6A
-S3150800610810BD08B5D0F8C402FCF753FAFFF7CDFF5F
-S3150800611808BD08B5D0F8C402FCF7E3FAFFF7C5FFCF
-S3150800612808BD08B5D0F8C402FCF71CFBFFF7BDFF8D
-S3150800613808BD08B5D0F8C402FCF7E6F9FFF7B5FFBD
-S3150800614808BD08B5D0F8C402FCF7A1FAFFF7ADFFF9
-S3150800615808BD08B5D0F8C402FCF762FAFFF7A5FF30
-S3150800616808BD000070B50D4E0D4CA41BA4100025E3
-S31508006178A54209D10B4E0C4C00F02CF8A41BA41010
-S315080061880025A54205D170BD56F825309847013532
-S31508006198EEE756F8253098470135F2E7A064000877
-S315080061A8A0640008A0640008A464000810B5431E8B
-S315080061B80A44914200D110BD11F8014B03F8014F6A
-S315080061C8F7E702440346934200D1704703F8011BD8
-S315080061D8F9E70000F8B500BFF8BC08BC9E4670474A
-S311080061E8F8B500BFF8BC08BC9E4670471E
-S315080061F4000000000000000000000000000000008D
-S315080062040000000001000000020000000300000076
-S315080062140400000000000000050000000000000063
-S315080062240000000000000000060000000000000056
-S315080062340000000000000000070000000000000045
-S315080062440102030401020304060708090001020304
-S3150800625404050607080C1014182030400000000036
-S3150800626401020304010203040607080901000000E9
-S3150800627402000000040000000600000008000000F8
-S315080062840A0000000C0000001000000020000000B6
-S31508006294400000008000000000010000433A2F5728
-S315080062A46F726B2F736F6674776172652F4F7065A3
-S315080062B46E424C542F5461726765742F536F75720E
-S315080062C463652F41524D434D375F53544D3332481E
-S315080062D4372F63616E2E6300050206020603070361
-S315080062E40803090309040A040B040C040C050D0528
-S315080062F40E050F050F061006100710080000020801
-S315080063040000020001010000000004080000020069
-S315080063140201000000000608000002000301000054
-S3150800632400000808000002000401000000000A0832
-S31508006334000002000501000000000C08000002002D
-S315080063440601000000000E08000002000701000014
-S3150800635400001008000002000002000000001208F5
-S3150800636400000200010200000000140800000200F8
-S3150800637402020000000016080000020003020000E2
-S3150800638400001808000002000402000000001A08B1
-S31508006394000002000502000000001C0800000200BC
-S315080063A40602000000001E080000020007020000A2
-S315080063B4433A2F576F726B2F736F667477617265E2
-S315080063C42F4F70656E424C542F5461726765742F53
-S315080063D4536F757263652F41524D434D375F53545E
-S315080063E44D333248372F72733233322E630000002E
-S315080063F4433A2F576F726B2F736F667477617265A2
-S315080064042F4F70656E424C542F5461726765742F12
-S31508006414536F757263652F41524D434D375F53541D
-S315080064244D333248372F7573622E63004F70656E8D
-S31508006434424C540044656661756C740057696E5520
-S3150800644453422042756C6B20496E746572666163AB
-S31508006454650000004F70656E424C54205573657292
-S315080064640000000057696E5553422042756C6B2034
-S3150800647444657669636500002E2E2F5553425F44A2
-S3150800648445564943452F5461726765742F7573627F
-S31108006494645F636F6E662E6300000000F4
-S309080064A0BD02000823
-S309080064A49902000843
-S315080064A80090D0030090D0030100000010000000FF
-S315080064B804000000A15D0008895D0008295D000840
-S315080064C80000000000000000115D00081B5D0008C0
-S315080064D8FD5C000800000000000000000000000045
-S315080064E8E55C000800000000F15C000809022000CD
-S315080064F8010100C0320904000002FF000000070578
-S3150800650881024000FF070501024000FF0A06000253
-S315080065180000004001000000D95D0008E55D00089C
-S31508006528955E0008715E00085D5E0008B15E0008A9
-S31508006538D55E00081201000200000040501DAC603C
-S315080065480002010203010000040309041A030000FB
-S315080065580000000000000000000000000000000025
-S30D0800656800000000000000001D
+S31508001168F2E710B490F89840E4B2012C09D0D0F808
+S315080011789C3043F00403C0F89C3001205DF8044B0A
+S315080011887047920042EA011141EA4303026801994D
+S315080011980B43C2F880300020F0E790F89830DBB2AD
+S315080011A8012B07D0D0F89C3043F00403C0F89C30D4
+S315080011B801207047022380F898300268936923F063
+S315080011C8010393610023C0F89C301846704770B530
+S315080011D890F89840013CE4B2012C07D9D0F89C3025
+S315080011E843F00203C0F89C30012070BD93FAA3F5BA
+S315080011F8B5FA85F50668D6F8C040C4F30544A5428D
+S315080012080BD2D6F8CC401C420FD0D0F89C3043F00D
+S315080012184003C0F89C300120E7E7D0F89C3043F03B
+S315080012282003C0F89C300120DFE793FAA3F3B3FA4A
+S3150800123883F3FFF7C9FD0020D7E790F89830DBB2AB
+S31508001248022B07D0D0F89C3043F00803C0F89C302E
+S31508001258012070470368C3F8D010002070470000C3
+S31508001268F0B490F89840E4B2022C08D0D0F89C3034
+S3150800127843F00803C0F89C300120F0BC70474029A9
+S3150800128839D0412964D0046D8C4240F28E80C46FEF
+S31508001298456D01FB05F504EB85044FF0000C256840
+S315080012A805F080455560002D40F087802568C5F310
+S315080012B88A451560256805F000559560256805F086
+S315080012C800451561A588D561656805F47025D5605A
+S315080012D8656805F480155561656805F40015956116
+S315080012E8E57905F07F0515626568ED0F556204F125
+S315080012F80805002469E00468D4F8A05015F4FE0F20
+S3150800130816D0D4F8A45015F07F0F19D0D4F8A450E5
+S3150800131815F0807F01D0D4F8A050D4F8A440C4F3BF
+S31508001328052C446F456C0CFB05F504EB8504B6E7FC
+S31508001338D0F89C3043F02003C0F89C3001209CE785
+S31508001348D0F89C3043F48073C0F89C30012094E7A9
+S315080013580468D4F8B05015F4FE0F16D0D4F8B45073
+S3150800136815F07F0F19D0D4F8B45015F0807F01D046
+S31508001378D4F8B050D4F8B440C4F3052C846FC56CBF
+S315080013880CFB05F504EB850489E7D0F89C3043F097
+S315080013982003C0F89C3001206FE7D0F89C3043F44E
+S315080013A88073C0F89C30012067E7D0F89C3043F07A
+S315080013B82003C0F89C3001205FE7256825F06045C2
+S315080013C8156077E72E5D1E550134D689124FBE5D26
+S315080013D8A642F7D840290BD041290ED01F2911D883
+S315080013E80268012303FA01F1C2F89810002044E7BD
+S315080013F80368C3F8A8C000203FE70368C3F8B8C065
+S3150800140800203AE701F01F010268012303FA01F1F7
+S31508001418C2F89C10002030E7646200080368D3F815
+S31508001428CC300B4201D00120704700207047402974
+S3150800143805D00368D3F8B40000F07F007047036846
+S31508001448D3F8A40000F07F0070470000144BDB684F
+S3150800145813F0010F09D0124B124A5A6002F188326A
+S315080014685A60DB6813F0010F16D10D4BD3F80C310F
+S3150800147813F0010F12D00A4B0A4AC3F8042102F1E5
+S315080014888832C3F80421D3F80C3113F0010F01D1BF
+S3150800149800207047012070470120704700207047D8
+S315080014A800200052230167450D4BDA6842F0010215
+S315080014B8DA60DB6813F0010F0FD0094BD3F80C215B
+S315080014C842F00102C3F80C21D3F80C3113F0010FCE
+S315080014D801D000207047012070470120704700BFDF
+S315080014E8002000522DE9F04105460F46384B1E6983
+S315080014F803F00AFF8046022F07D026F0684626F42E
+S315080015088016760C7604042420E0314BD3F8106153
+S3150800151826F0684626F48016760C760446F00046C9
+S315080015282C4C13E003F0F0FEA0EB0800A84248D8BC
+S3150800153865B9032025E0264B1B6934EA03030CBF6B
+S315080015480123002383B1B5F1FF3FEBD134F004033F
+S31508001558F1D01F4BD3F8103124EA030333F00043C4
+S315080015680CBF01230023EDE736F000410FD01A4AD5
+S31508001578936933439361002E05DA154BC3F81411A2
+S315080015880120BDE8F081124B5E610120F9E7012FC1
+S315080015980CD00F4BD3F8103113F4803F15D00C4BF1
+S315080015A84FF48032C3F814210020EAE7084B1B6978
+S315080015B813F4803F07D0064B4FF480325A61002057
+S315080015C8DFE70320DDE70020DBE70020D9E700BFD7
+S315080015D800200052040000803C1300242F4B1B7D7A
+S315080015E8012B56D070B50C4615462C4B01221A7598
+S315080015F801F17843B3F5801F3DD3A1F10161B1F537
+S31508001608801F49D20226254B00229A6131464CF2A0
+S315080016185030FFF767FF034640BB012E2DD0204AFE
+S31508001628D2F80C3143F00203C2F80C31BFF36F8FBE
+S31508001638BFF34F8F082355F8042B44F8042B013BB6
+S3150800164813F0FF03F7D1BFF36F8FBFF34F8F314600
+S315080016584CF25030FFF746FF0346012E13D01049C7
+S31508001668D1F80C2122F00202C1F80C210B4A0021FC
+S315080016781175184670BD0126C5E7094AD36843F0AF
+S315080016880203D360D2E70649CA6822F00202CA6092
+S31508001698ECE70223184670470123EAE73C130024BF
+S315080016A80020005201F00303032B24D011F0010F88
+S315080016B80BD01D4BDA6822F03002DA60DA6802438A
+S315080016C8DA60DA6842F08802DA6011F0020F11D09F
+S315080016D8154BD3F80C2122F03002C3F80C21D3F8A5
+S315080016E80C211043C3F80C01D3F80C2142F08802E8
+S315080016F8C3F80C2170470C4BDA6822F03002DA601E
+S31508001708D3F80C2122F03002C3F80C21DA68024318
+S31508001718DA60D3F80C211043C3F80C019A6942F031
+S3150800172810029A61704700BF0020005230B411F0C9
+S31508001738010F0BD0104CE36823F4E663E360E36813
+S3150800174842EA00252B4343F08403E36011F0020FB5
+S315080017580FD00949D1F80C3123F4E663C1F80C31E6
+S31508001768D1F80C3142EA00221A4342F08402C1F841
+S315080017780C2130BC704700BF00200052F8B5474B13
+S315080017881B7D012B00F088800F460446434B012237
+S315080017981A7500229A61436813F0010F0DD10026C5
+S315080017A8636813F0020F12D1CEB92368012B1BD038
+S315080017B84FF0FF333B60A5684CE001214CF25030EE
+S315080017C8FFF790FE06460028EAD00126E8E7022138
+S315080017D84CF25030FFF786FE0028E5D001262F4B3D
+S315080017E800221A753046F8BD61682069FFF75AFF66
+S315080017F8636813F0010F12D1636813F0020FEED075
+S3150800180802214CF25030FFF76DFE00B10126244A3A
+S31508001818D2F80C3123F00803C2F80C31DFE70121AE
+S315080018284CF25030FFF75EFE00B101261C4AD36819
+S3150800183823F00803D360DFE701214CF25030FFF7A5
+S3150800184851FE0646164AD168164B0B40D3600FE080
+S3150800185806BB0135E368A2681344AB42BFD92269BF
+S3150800186861682846FFF762FF636813F0010FE3D142
+S31508001878636813F0020FEBD002214CF25030FFF7E1
+S3150800188831FE0646064AD2F80C11064B0B40C2F83A
+S315080018980C31DDE73D60A2E70226A3E73C130024E6
+S315080018A800200052FBF8FFFFF0B583B000233AE0AA
+S315080018B8092400E00024B4403C4302356E4E46F83D
+S315080018C825406E4C2568D44304EA05064F6817F484
+S315080018D8803F01D042EA0506684D2E606E6804EA24
+S315080018E806054F6817F4003F01D042EA0605634E1D
+S315080018F875604FF0B0452D6804EA05064F6817F479
+S31508001908801F01D042EA05064FF0B0452E606D6883
+S315080019182C404E6816F4001F01D042EA05044FF021
+S31508001928B042546001330A6832FA03F400F0A28020
+S3150800193801249C402240F5D04D686E1E112D18BF13
+S31508001948012E01D9122D12D186685F000325BD40E4
+S3150800195826EA0506CD68BD4035438560466826EA09
+S3150800196804064D68C5F300149C4034434460C668B1
+S315080019785F000325BD40EC4326408D68BD403543CE
+S31508001988C5604D68122D18BF022D13D1DE0808361A
+S3150800199850F826E003F007054FEA850C0F2505FAE7
+S315080019A80CF52EEA050E0D6905FA0CF545EA0E053D
+S315080019B840F82650056825404C6804F00304BC40E6
+S315080019C82C4304604C6814F0805FABD02C4CD4F8D8
+S315080019D8F45045F00205C4F8F450D4F8F44004F07D
+S315080019E802040194019C9D08AE1C234C54F82670E9
+S315080019F803F00304A6000F24B44027EA0407214C81
+S31508001A08A0423FF457AF04F58064A04222D004F5FB
+S31508001A188064A04220D004F58064A0421ED004F554
+S31508001A288064A0421CD004F58064A0421AD004F54C
+S31508001A388064A04218D004F58064A04216D004F544
+S31508001A488064A04214D004F58064A0423FF430AF05
+S31508001A580A2430E701242EE702242CE703242AE780
+S31508001A68042428E7052426E7062424E7072422E78A
+S31508001A78082420E703B0F0BD000400588000005889
+S31508001A880044025800000258002331FA03F200F015
+S31508001A989880F0B52CE0092700E0002707FA04F437
+S31508001AA8B44273D005685C00032606FA04F4254395
+S31508001AB8056023FA06F5083550F8256003F0070788
+S31508001AC84FEA870C0F2707FA0CF726EA070640F8A5
+S31508001AD82560C568E4432540C560456825EA0202CD
+S31508001AE84260826814408460013331FA03F267D091
+S31508001AF801229A4012EA0105F6D04FEA930E0EF132
+S31508001B080206304C54F8266003F00304A4004FF08C
+S31508001B180F0C0CFA04FC0CEA06062B4FB842BCD08C
+S31508001B2807F58067B84221D007F58067B8421FD005
+S31508001B3807F58067B8421DD007F58067B8421BD0FD
+S31508001B4807F58067B84219D007F58067B84217D0F5
+S31508001B5807F58067B84215D007F58067B84213D0ED
+S31508001B6807F58067B84296D00A2797E7012795E7C9
+S31508001B78022793E7032791E704278FE705278DE7C9
+S31508001B8806278BE7072789E7082787E70F4C26687C
+S31508001B98ED432E40266066682E4066604FF0B044D6
+S31508001BA826682E402660666835406560054E0EF143
+S31508001BB8020456F8245025EA0C0546F8245071E71D
+S31508001BC8F0BD70470004005800000258800000580D
+S31508001BD82DE9F04782B00768CA00521A93000344F1
+S31508001BE85A6D1B6D9A4257D8B8469B1AC1EBC10461
+S31508001BF8A2000244526C9A4200D31A460C4606467C
+S31508001C0802F1030A4FEA9A0A16E009F1030A4FEAAB
+S31508001C189A0AE3001B1B9D003544A96C337C009384
+S31508001C281FFA89F3E2B2384601F0B8FFAB6C4B44A9
+S31508001C38AB646B6D4B446B6508EB441303F5106393
+S31508001C489B699BB2534513D3E3001B1B9A00324486
+S31508001C58516D136D99420BD253B15B1AC4EBC4018B
+S31508001C688A003244D2F844909945CED39946CCE7AF
+S31508001C78E3001B1B98000644326D736D9A420FD811
+S31508001C8804F00F040121A140D7F8344824EA0104D6
+S31508001C98C7F83448002000E0012002B0BDE8F08704
+S31508001CA80020FAE7F0B58BB0002800F091800446CA
+S31508001CB8056890F8BD3323B3032384F8BD33EB6B6B
+S31508001CC813F4807F01D100232361206801F004FD05
+S31508001CD8254655F8107B6E460FCD0FC60FCD0FC695
+S31508001CE895E8030086E80300231D0ECB384601F065
+S31508001CF831FC58B1022384F8BD33012528460BB0B8
+S31508001D08F0BD80F8BC33FEF71FFDD5E70021206833
+S31508001D1801F0E8FC002315E0D900C81A820022441D
+S31508001D28012082F83D0082F83C30A2F842300020B3
+S31508001D3882F83F0050649064CA1A910021440865E5
+S31508001D480133DBB26568AB42E6D3002315E0D80059
+S31508001D58C11A8A002244002182F8FD1182F8FC3152
+S31508001D6882F8FF11C2F80412C2F80812C21A9000C3
+S31508001D782044C0F810120133DBB29D42E7D8254645
+S31508001D8855F8107B6E460FCD0FC60FCD0FC695E8D2
+S31508001D98030086E80300231D0ECB384601F0E8FC4D
+S31508001DA8054660B9002384F83830012384F8BD3322
+S31508001DB8636A012B08D0206802F0BFF89EE7022361
+S31508001DC884F8BD33012599E7204600F02FFDF2E790
+S31508001DD8012593E7026890F8BC33012B19D010B592
+S31508001DE8012380F8BC33836A012B0AD004460068AD
+S31508001DF802F097F8206801F069FC002084F8BC0313
+S31508001E0810BD8369012BF1D0936B43F48033936338
+S31508001E18ECE70220704738B590F8BC33012B18D088
+S31508001E280446012380F8BC33006801F055FC206895
+S31508001E3802F043F8054628B1002384F8BC33012587
+S31508001E48284638BD206802F078F8002384F8BC33A1
+S31508001E58F6E70225F4E768B110B50446032380F8C7
+S31508001E68BD33FFF7D8FF2046FEF7A8FC002084F804
+S31508001E78BD0310BD0120704770B504460D460068BD
+S31508001E88066C00EB411303F530639A68216901294A
+S31508001E9811D037498E4254D03DB9C5EBC5029300D7
+S31508001EA82344D3F81032002B5CD0E9B2204604F05C
+S31508001EB831F8002070BD12F0080F09D02D498E425E
+S31508001EC8F7D912F4004FF4D04FF400429A60F0E7BD
+S31508001ED812F0200F28D112F0280FEAD125498E4290
+S31508001EE802D912F4004F22D1E900491B8A0022447C
+S31508001EF8D2F804121B69C3F31203C91AC2F81412DA
+S31508001F08D2F80412D2F808320B44C2F8083235B9A6
+S31508001F18C5EBC50293002344D3F810325BB1E9B286
+S31508001F28204603F0F7FFC4E720229A60C1E74FF47A
+S31508001F3800429A60BDE704F57172012102F04EF875
+S31508001F48EDE712F4004F09D112F0200F01D0202234
+S31508001F589A60E9B2204603F0DDFFAAE74FF400428B
+S31508001F689A60A6E704F57172002102F037F89CE733
+S31508001F780A31544F0A30544F38B5044603681D6C65
+S31508001F8803EB4111D1F8082B0E4B9D4207D901F5F1
+S31508001F98306112F4004F02D04FF400438B6020469C
+S31508001FA803F0B0FF074B9D4202D92369012B01D0E4
+S31508001FB8002038BD04F571720121206802F00EF878
+S31508001FC8F6E700BF0A30544F2DE9F84F044605686E
+S31508001FD8284601F0EFFF08B1BDE8F88F2F460646F8
+S31508001FE8206801F0B6FF0028F6D0206801F0B1FF96
+S31508001FF810F0020F04D02268536903F002035361F4
+S31508002008206801F0A6FF10F0100F15D02268936912
+S3150800201823F010039361D5F8208008F00F09C8F358
+S315080020284343022B00F08580062B00F0A580226822
+S31508002038936943F010039361206801F08AFF10F44E
+S31508002048002F40F0AD80206801F083FF10F4802F40
+S3150800205840F0F180206801F07CFF0028C0F25F811B
+S31508002068206801F076FF10F4006F0AD0D5F8083812
+S3150800207813F0010F40F06D812268536903F4006379
+S315080020885361206801F065FF10F0006F15D02268CB
+S31508002098536903F00063536194F8F433002B40F056
+S315080020A85C81012184F8F41323685B6DC3F3830309
+S315080020B8C4F8F833204600F0CDFB206801F049FF44
+S315080020C810F4805F40F04D81206801F042FF10F45B
+S315080020D8005F40F0AB81206801F03BFF10F0080F65
+S315080020E840F0BC81206801F034FF10F4801F40F0EE
+S315080020F8BE81206801F02DFF10F4001F40F0C18151
+S31508002108206801F026FF10F0804F40F0C48120684F
+S3150800211801F01FFF10F0040F3FF45EAF23685D68F7
+S3150800212815F0040F40F0C081226853682B435360AA
+S3150800213852E747F6F07318EA030F3FF478AF4FEA09
+S31508002148C90BABEB09034FEA830AA2444FEA1818EE
+S31508002158C8F30A02DAF80812284601F03FFEC8F35F
+S315080021680A08DAF808324344CAF80832DAF81432A0
+S315080021784344CAF814325AE7082204F57171284606
+S3150800218801F02CFEC8F30A184FEAC903A3EB0901A4
+S315080021988A002244D2F814324344C2F8143246E775
+S315080021A8206801F0DAFE8046B14617E007EB4913C6
+S315080021B80122C3F8082B49462046FFF75DFE1DE0B5
+S315080021C807EB49130822C3F8082B49462046FFF7A8
+S315080021D8D3FE16E009F101094FEA5808B8F1000FCD
+S315080021E83FF431AF18F0010FF4D05FFA89F120688F
+S315080021F801F0C3FE824610F0010FD7D11AF0080F76
+S31508002208DED11AF0100F04D007EB49131022C3F8D1
+S31508002218082B1AF0200F04D007EB49132022C3F81D
+S31508002228082B1AF4005FD5D007EB49134FF4005270
+S31508002238C3F8082BCEE7206801F097FE8046B1461A
+S315080022482AE05946204603F071FE1AF0080F04D012
+S3150800225807EB49130822C3F808291AF0100F04D007
+S3150800226807EB49131022C3F808291AF0400F04D0BF
+S3150800227807EB49134022C3F808291AF0020F04D0BD
+S3150800228807EB49130222C3F808291AF0800F41D12F
+S3150800229809F101094FEA5808B8F1000F3FF4DAAE18
+S315080022A818F0010FF4D05FFA89FB5946206801F047
+S315080022B86DFE824610F0010FC7D009F00F03012101
+S315080022C801FA03F2D7F8343823EA0203C7F8343890
+S315080022D807EB4913C3F8081923698B42B1D14FEAAA
+S315080022E8C902A2EB090293002344596C9A6C0A4462
+S315080022F89A64B9F1000FA4D1C9EBC9029300234423
+S315080023081B6D002B9DD104F571720121206801F01F
+S3150800231865FE96E749462046FFF75AFCB8E7D5F81A
+S31508002328043823F00103C5F8043894F8F433012B6C
+S3150800233808D0204603F040FE2268536903F000439C
+S3150800234853618DE6002184F8F413204600F082FADA
+S31508002358F2E7204603F016FE8EE6204603F012FE44
+S31508002368ABE605F50068D8F8043023F00103C8F889
+S3150800237804301021206801F0CDF920E007EB461358
+S315080023884FF67F31C3F80819D3F8002922F400124A
+S31508002398C3F80029D3F8002942F00062C3F80029D7
+S315080023A8C3F8081BD3F8002B22F40012C3F8002B35
+S315080023B8D3F8002B42F00062C3F8002B0136636895
+S315080023C8B342DBD8D8F81C3043F00113C8F81C30E0
+S315080023D8236BEBB1D8F8843043F00B03C8F8843084
+S315080023E8D8F8443043F00B03C8F84430D5F8003819
+S315080023F823F4FE63C5F8003804F57172217C206859
+S3150800240801F0ECFD2268536903F4805353615BE6D7
+S31508002418D8F8142042F22B031343C8F81430D8F816
+S31508002428103043F00B03C8F81030DFE7206801F0D6
+S31508002438C5FD206801F060FAE060256800F00AFB2F
+S31508002448227B0146284601F0CBF8204603F080FD9A
+S315080024582268536903F4005353613CE6204603F0A7
+S3150800246870FD2268536903F0080353613AE60021B0
+S31508002478204603F0B0FD2268536903F480135361BC
+S3150800248837E60021204603F0A0FD2268536903F4C5
+S315080024980013536134E6204603F0A3FD2268536906
+S315080024A803F08043536132E6204603F0A4FD3BE679
+S315080024B8026890F8BC33012B16D010B5012380F8B2
+S315080024C8BC33836A012B07D00446006801F029FD4E
+S315080024D8002084F8BC0310BD8369012BF4D0936BE4
+S315080024E843F480339363EFE70220704790F8BC33D0
+S315080024F8012B0BD010B50446012380F8BC330068BD
+S3150800250801F01BFD002084F8BC0310BD02207047AB
+S3150800251890F8BC33012B0DD010B50446012380F87A
+S31508002528BC3380F83810006801F0EBFC002084F80A
+S31508002538BC0310BD02207047F8B511F0800F28D1EA
+S3150800254801F00F06F500AF1BBC00274604F5FC741E
+S31508002558044404343E460644002586F8FD5101F035
+S315080025680F012170A260E370627802B1E180022B44
+S315080025781ED090F8BC33012B1DD00546012380F8E0
+S31508002588BC332146006801F0C7F9002085F8BC036A
+S31508002598F8BD01F00F06F500AF1BBC002746383416
+S315080025A8044404343E460644012586F83D50D6E7D9
+S315080025B800232371DDE70220EAE738B511F0800F1A
+S315080025C821D101F00F05EA00541BA3001C4603F5A8
+S315080025D8FC730344043325460544002285F8FD2187
+S315080025E801F00F01197090F8BC23012A1AD0044685
+S315080025F8012280F8BC231946006801F0D5F90020A5
+S3150800260884F8BC0338BD01F00F04E200151BAB00C3
+S315080026181D463833034404332C460444012284F8FF
+S315080026283D20DDE70220EDE770B501F00F05EE0065
+S31508002638711B8C0004F5FC740444211D761BB40038
+S315080026480444C4F80822C4F810320023C4F8143223
+S3150800265884F8FD3184F8FC510369012B06D065B16D
+S31508002668DAB2006801F0AEFA002070BDC5EBC506FF
+S31508002678B4000444C4F80C22F1E7DAB2006801F0A1
+S3150800268801FAF1E701F00F01C1EBC1018B0018440B
+S31508002698D0F81402704770B501F00F05EE00711BEB
+S315080026A88C0038340444211D761BB4000444A26403
+S315080026B8236500236365012384F83D3084F83C507C
+S315080026C80369012B06D05DB1DAB2006801F07AFA1F
+S315080026D8002070BDC5EBC506B4000444E264F2E701
+S315080026E8DAB2006801F0CEF9F2E738B501F00F055D
+S315080026F843689D4236D811F0800F20D1CA00541A73
+S31508002708A3001C4603F5FC7303440433224602441B
+S31508002718002182F8FD1101229A701D7090F8BC23D9
+S31508002728012A21D00446012280F8BC2319460068EC
+S3150800273801F068FB7DB1002084F8BC0313E0EA00C9
+S31508002748511B8B00194638330344043301440122CC
+S3150800275881F83D20DFE704F57172217C206801F0D5
+S315080027683DFCE8E7012038BD0220FCE710B501F07A
+S315080027780F0443689C422CD811F0800F1DD1E30042
+S315080027881A1B91000A4601F5FC71014404310244FA
+S31508002798002382F8FD3100238B700C7090F8BC3347
+S315080027A8012B18D00446012380F8BC33006801F0D1
+S315080027B856FB002084F8BC030CE0E3001A1B9100C2
+S315080027C80A463831014404310244012382F83D306F
+S315080027D8E1E7012010BD0220FCE730B40468606A0E
+S315080027E829B10D46A36A00EB134000230CE040EA22
+S315080027F80240A06212E003F1400104EB8101496836
+S3150800280800EB11400133DBB2691E8B42F3D340EA71
+S31508002818024005F13F0104EB81014860002030BC05
+S31508002828704703685962002070470000024603682B
+S315080028380121C0F8FC13002082F8F4039A6942F0D3
+S3150800284800629A61596D024A0A435A65704700BF81
+S315080028580300001070470000024AD36843F08073EB
+S31508002868D360704700480258724B1B6903F0380357
+S31508002878102B00F0DB80182B10D00BB16E48704770
+S315080028886C4B1B6813F0200F00F0D280694B186850
+S31508002898C0F3C100694B23FA00F07047654A916A8C
+S315080028A801F00301906AC0F30510D36A03F0010327
+S315080028B8526BC2F3CC0203FB02F307EE903AF8EE2A
+S315080028C8677A002800F0B580012966D0F9B102298F
+S315080028D800F08F8007EE100AF8EE476A9FED586AEF
+S315080028E886EE267A534B1B6BC3F3080306EE903A1B
+S315080028F8F8EE666A9FED536A67EE867A76EEA77AE9
+S31508002908F7EE006A77EEA67A27EE277A61E0494B52
+S315080029181B6813F0200F23D046490A68C2F3C10280
+S31508002928464BD34007EE103AF8EE476A07EE100A08
+S31508002938B8EE476A86EE867A0B6BC3F3080306EE8B
+S31508002948903AF8EE666A9FED3F6A67EE867A76EE03
+S31508002958A77AF7EE006A77EEA67A27EE277A38E09E
+S3150800296807EE100AF8EE476A9FED376A86EE267A6A
+S31508002978304B1B6BC3F3080306EE903AF8EE666A0B
+S315080029889FED306A67EE867A76EEA77AF7EE006AE2
+S3150800299877EEA67A27EE277A1BE007EE100AF8EEF6
+S315080029A8476A9FED276A86EE267A224B1B6BC3F386
+S315080029B8080306EE903AF8EE666A9FED226A67EE15
+S315080029C8867A76EEA77AF7EE006A77EEA67A27EE83
+S315080029D8277A184B1B6BC3F34623013307EE903A45
+S315080029E8F8EE677AC7EE276AFCEEE67A17EE900ADB
+S315080029F8704707EE100AF8EE476A9FED146A86EEE6
+S31508002A08267A0C4B1B6BC3F3080306EE903AF8EECE
+S31508002A18666A9FED0C6A67EE867A76EEA77AF7EE0F
+S31508002A28006A77EEA67A27EE277AD2E7084870472B
+S31508002A38024870470044025800093D000090D00338
+S31508002A480024744A000000390024744C0024F44A0F
+S31508002A5800127A0008B5FFF707FF0B4A9369C3F314
+S31508002A6803230A49CB5C03F01F0320FA03F3926990
+S31508002A7802F00F02885C00F01F0023FA00F0044AEF
+S31508002A881060044A136008BD0044025854620008DE
+S31508002A9804000024000000246A4B984222D06A4B9E
+S31508002AA898422FD0694B98423CD0694B984249D0F6
+S31508002AB8684B984256D0684B984263D0674B984201
+S31508002AC870D0674B98427DD0664B984200F08A8052
+S31508002AD8654B984200F09680644B984200F0A280B5
+S31508002AE80120704703F58843D3F8882042F001028D
+S31508002AF8C3F88820D3F8882022F00102C3F8882072
+S31508002B080020704703F58043D3F8882042F0020274
+S31508002B18C3F88820D3F8882022F00202C3F8882050
+S31508002B280020704703F57053D3F8882042F0040252
+S31508002B38C3F88820D3F8882022F00402C3F888202E
+S31508002B480020704703F56053D3F8882042F008023E
+S31508002B58C3F88820D3F8882022F00802C3F888200A
+S31508002B680020704703F55053D3F8882042F0100226
+S31508002B78C3F88820D3F8882022F01002C3F88820E2
+S31508002B880020704703F54053D3F8882042F0200206
+S31508002B98C3F88820D3F8882022F02002C3F88820B2
+S31508002BA80020704703F53053D3F8882042F04002D6
+S31508002BB8C3F88820D3F8882022F04002C3F8882072
+S31508002BC80020704703F52053D3F8882042F0800286
+S31508002BD8C3F88820D3F8882022F08002C3F8882012
+S31508002BE80020704703F51053D3F8882042F4807202
+S31508002BF8C3F88820D3F8882022F48072C3F888207E
+S31508002C080020704703F50053D3F8882042F4007271
+S31508002C18C3F88820D3F8882022F40072C3F88820DD
+S31508002C280020704703F5E053D3F8882042F4806201
+S31508002C38C3F88820D3F8882022F48062C3F888204D
+S31508002C48002070470000025800040258000802587D
+S31508002C58000C0258001002580014025800180258AE
+S31508002C68001C02580020025800240258002802585E
+S31508002C78F0B40A6892FAA2F2B2FA82F216E00F697A
+S31508002C88C66803FB03F505EB4504E443264005FB44
+S31508002C9807F73E43C6604E68022E29D04B68066879
+S31508002CA8344005FB03F32343036001320B6833FA08
+S31508002CB802F440D0012494402340F6D04C68013CE5
+S31508002CC8012CDCD88E68846803FB03F505EB4507F9
+S31508002CD824EA070405FB06F52C4384600E68CD68CC
+S31508002CE8446824EA060405FB06F52C434460C6E74F
+S31508002CF8FF2B0ED8066A05FB03F707FB03F3C3EB9E
+S31508002D08031726EA07074E6903FB06F33B430362E4
+S31508002D18C4E7466A1B0A03FB03F707FB03F707FB27
+S31508002D2803F3C3EB031726EA07074E6903FB06F303
+S31508002D383B434362B2E70020F0BC70472D4B1B6843
+S31508002D4803F00F03062B06D82A4A136823F00F0345
+S31508002D5843F007031360284A136843F00103136016
+S31508002D68254B1B6813F0040FFAD0234B00221A616F
+S31508002D781968224A0A401A601F4B1B6813F0007F1D
+S31508002D88FAD11D4B1B6813F0006FFAD11A4B1B6852
+S31508002D9813F0005FFAD1184B00229A61DA611A62B9
+S31508002DA8174999621749D962174919635A63996382
+S31508002DB8DA6319645A64196821F4802119601A6655
+S31508002DC8996E40F2FF720A439A66D3F8D02042F405
+S31508002DD88032C3F8D020074B1B6803F00F03072B74
+S31508002DE806D9044A136823F00F0343F00703136050
+S31508002DF8704700BF002000520044025845EDF6EA25
+S31508002E08000202020000FF018002010107EE900A93
+S31508002E18F8EE676A07EE901AF8EE677A86EEA77AEA
+S31508002E2807EE902AF8EE677A06EE903AF8EE666AA2
+S31508002E389FED096A66EE866A77EEA67A27EE277AFE
+S31508002E48DDED007AF8EE677AC7EE276AFCEEE67AD1
+S31508002E5817EE900A704700BF000000392DE9F041C7
+S31508002E6882B03F4B9B6A03F00303012B60D0002B0B
+S31508002E7852D0022B63D00027002303604360836087
+S31508002E88374B9E6AC6F305161A6BC2F30802551C19
+S31508002E98DB6A13F0010F5FD0314B5B6BC3F3CC08C9
+S31508002EA8002E36D004462E4BDB6A13F4803F0CD02E
+S31508002EB82B4B1B6BC3F346230133009343462A4621
+S31508002EC831463846FFF7A2FF2060254BDB6A13F424
+S31508002ED8003F0CD0224B1B6BC3F306430133009308
+S31508002EE843462A4631463846FFF790FF60601C4B32
+S31508002EF8DB6A13F4802F0CD0194B1B6BC3F30663DC
+S31508002F080133009343462A4631463846FFF77EFF83
+S31508002F18A06002B0BDE8F081114B1B6813F0040FDE
+S31508002F2814D00F4B1B68C3F3C1030E4FDF40A3E74A
+S31508002F380B4B1B6813F4807F0AD100279CE7084BC4
+S31508002F481B6813F4003F05D1002795E7002793E788
+S31508002F58054F91E7054F8FE74FF00008A0E700BF38
+S31508002F68004402580090D00300093D0000127A0078
+S31508002F782DE9F04182B03F4B9B6A03F00303012B0E
+S31508002F8860D0002B52D0022B63D0002700230360A1
+S31508002F9843608360374B9E6AC6F305369A6BC2F35D
+S31508002FA80802551CDB6A13F0100F5FD0314BDB6B38
+S31508002FB8C3F3CC08002E36D004462E4BDB6A13F42E
+S31508002FC8002F0CD02B4B9B6BC3F34623013300937E
+S31508002FD843462A4631463846FFF718FF2060254BF0
+S31508002FE8DB6A13F4801F0CD0224B9B6BC3F3064392
+S31508002FF80133009343462A4631463846FFF706FF0B
+S3150800300860601C4BDB6A13F4001F0CD0194B9B6BD2
+S31508003018C3F306630133009343462A4631463846C6
+S31508003028FFF7F4FEA06002B0BDE8F081114B1B68FB
+S3150800303813F0040F14D00F4B1B68C3F3C1030E4FCC
+S31508003048DF40A3E70B4B1B6813F4807F0AD10027E0
+S315080030589CE7084B1B6813F4003F05D1002795E742
+S31508003068002793E7054F91E7054F8FE74FF00008CC
+S31508003078A0E700BF004402580090D00300093D00AD
+S3150800308800127A002DE9F04182B0434B9B6A03F09F
+S315080030980303012B69D0002B5BD0022B6CD00025CB
+S315080030A800230360436083603B4B9C6AC4F3055462
+S315080030B81A6CC2F30802561CDB6A13F4807F68D0C0
+S315080030C8354B5F6CC7F3CC072B1C18BF0123002CA4
+S315080030D808BF0023002B39D080462F4BDB6A13F430
+S315080030E8800F0DD02C4B1B6CC3F34623013300937A
+S315080030F83B46324621462846FFF788FEC8F80000B0
+S31508003108254BDB6A13F4000F0DD0234B1B6CC3F356
+S315080031180643013300933B46324621462846FFF7C5
+S3150800312875FEC8F804001C4BDB6A13F0807F0DD0C7
+S31508003138194B1B6CC3F30663013300933B463246AF
+S3150800314821462846FFF762FEC8F8080002B0BDE81F
+S31508003158F081114B1B6813F0040F14D00E4B1B6833
+S31508003168C3F3C1030D4DDD409AE70B4B1B6813F4F7
+S31508003178807F0AD1002593E7074B1B6813F4003FA5
+S3150800318805D100258CE700258AE7054D88E7054D12
+S3150800319886E7002798E700BF004402580090D00346
+S315080031A800093D0000127A00154B1B6903F0380325
+S315080031B8182B0ED8DFE803F00F0D0D0D0D0D0D0DAC
+S315080031C8210D0D0D0D0D0D0D160D0D0D0D0D0D0DFC
+S315080031D81800002070470A4B1B68C3F3C103094847
+S315080031E8D84070470848704700B585B001A8FFF76A
+S315080031F835FE019805B05DF804FB0448704700BF22
+S31508003208004402580090D00300127A0000093D00D5
+S31508003218044B9B6903F00F03034AD35C03F01F03AF
+S31508003228D84070470044025874620008044BDB69AA
+S31508003238C3F30213034AD35C03F01F03D84070474D
+S315080032480044025874620008044BDB69C3F302237E
+S31508003258034AD35C03F01F03D8407047004402585A
+S315080032687462000800B585B0C2B24C4BD358020E3A
+S31508003278C0F304218A401340CB4040EA0340484B38
+S31508003288984228D02ED8A3F58133A3F5807398429F
+S315080032985DD019D8A3F58033984248D003F5407312
+S315080032A898422ED1FFF780FF3E4B9B69C3F3032351
+S315080032B83D4AD35C03F01F03D840FFF7A9FFFFF781
+S315080032C8C3FF05B05DF804FB384B98423FD003F5B9
+S315080032D87D43984215D1334B1B6813F0005F42D1E2
+S315080032E80020EEE7324B984242D00CD9314B98422F
+S315080032F845D003F54073984241D0A3F580339842E8
+S3150800330836D00020DDE7A3F58033984203D003F5CD
+S3150800331840739842F5D1234B1B6813F0040F35D038
+S31508003328204B1B68C3F3C1032348D840C9E7FFF7F6
+S315080033383BFF1C4B9B69C3F303231B4AD35C03F06F
+S315080033481F03D840FFF764FFFFF770FFB9E7154B6F
+S315080033581B6813F0006F01D10020B2E701A8FFF738
+S3150800336807FE0298ADE701A8FFF78CFE0298A8E7C2
+S315080033780C4B1B6813F4807F0AD10020A1E7094B80
+S315080033881B6F13F0020F05D100209AE7002098E773
+S315080033980A4896E74FF4004093E700BF4C440258A2
+S315080033A80803020700440258746200080803010764
+S315080033B808000407080005070090D00300093D0027
+S315080033C838B5036813F0010F40F08C800D460446A3
+S315080033D80368454A1A408B6809690B4369690B43B0
+S315080033E8E9690B4313430360EB68426822F44052C9
+S315080033F813434360AB69826822F4407213438360BF
+S315080034083A4B984216D03A4B98421CD0394B9842B8
+S315080034181DD0394B98421ED0384B98421FD0384B8E
+S31508003428984220D0374B984221D0374B984222D021
+S3150800343801204EE03548FFF715FF002848D06A688E
+S31508003448EAB9012045E03248FFF70CFFF5E73048AE
+S31508003458FFF708FFF1E72E48FFF704FFEDE72C48CA
+S31508003468FFF700FFE9E72948FFF7FCFEE5E72848E4
+S31508003478FFF7F8FEE1E72648FFF7F4FEDDE72B68D5
+S31508003488E9690B2B2CD8B1F5004F0DD0DBB22149D1
+S3150800349851F82330B0FBF3F303EB5203B3FBF2F313
+S315080034A89BB2E360002014E0DBB21A4951F82330D6
+S315080034B8B0FBF3F0530803EB4000B0FBF2F34FF60A
+S315080034C8F0721A40C3F342031343E360002000E096
+S315080034D80120E26A22F00F022B881343E36238BD03
+S315080034E80020F6E70120FAE7F369FFEF001001402C
+S315080034F80044004000480040004C0040005000408E
+S315080035080014014000780040007C004008030007CA
+S315080035180800000784620008002301330C4A934216
+S3150800352811D80269002AF8DA036943F0010303612E
+S3150800353800230133064A934207D8026912F0010F9D
+S31508003548F7D100207047032070470320704700BF53
+S31508003558400D030084B010B5044603A880E80E00A1
+S31508003568089B012B1DD1A36B23F48033A363E26860
+S315080035781A4B1340E360E36823F44013E3600F9B98
+S31508003588012B09D02046FFF7C7FF069B012B1BD046
+S31508003598BDE8104004B07047E36843F48013E3605D
+S315080035A8F0E7E36843F04003E3602046FFF7B4FF1B
+S315080035B80C9B23B9A36B43F48033A363E5E7A36B9A
+S315080035C823F48033A363E0E7A36843F00603A36004
+S315080035D8A36843F02003A360DAE700BFBFFFBDFF77
+S315080035E8022A0AD00921C26822F47052C260C36846
+S315080035F843EA8123C36000207047274B0B44274AB8
+S31508003608934239D9264B0B44264A934236D9264B38
+S315080036180B44264A934233D9254B0B4402F5C33249
+S31508003628A03293422ED9234B0B44234A93422BD9D3
+S31508003638224B0B4402F5922202F57872934225D959
+S315080036481F4B0B4402F5C32202F5207293421FD979
+S315080036581C4B0B4402F5B71202F55872934219D956
+S31508003668194B0B4402F5122202F5F862934201D966
+S315080036780621B8E70721B6E70F21B4E70E21B2E716
+S315080036880D21B0E70C21AEE70B21ACE70A21AAE722
+S315080036980921A8E70821A6E7405327FFFF340C00AD
+S315080036A8401E1BFF3F420F0000DC0BFF7F4F120036
+S315080036B8808CF9FE60B6E5FE5FE3160000D3CEFE01
+S315080036C8C05BB3FE00CA91FEE05459FE836843F016
+S315080036D80103836000207047836823F00103836031
+S315080036E80020704708B5C36823F0C043C3600129A2
+S315080036F809D069B9C36843F08043C3603220FDF72F
+S315080037080BFA002008BDC36843F00053C360F5E709
+S315080037180120F7E7890141F02001016100230133FF
+S31508003728054A934205D8026912F0200FF7D10020FE
+S3150800373870470320704700BF400D0300102303613C
+S3150800374800230133054A934205D8026912F0100F7F
+S31508003758F7D1002070470320704700BF400D0300CB
+S31508003768D0F800381943C0F8001800207047000040
+S3150800377884B02DE9F041044607A880E80E002546DE
+S31508003788002306E003F1400204EB8202002151609F
+S3150800379801330E2BF6D9119B23BBD4F8043843F012
+S315080037A80203C4F80438A36B23F40013A36323683D
+S315080037B843F040032360236843F080032360002313
+S315080037C8C4F8003E04F50066D4F80038C4F8003892
+S315080037D80C9B012B10D1099B4BB900212046FFF7FA
+S315080037E8BFFF0DE0A36B43F40013A363E7E70121CA
+S315080037F82046FFF7B5FF03E003212046FFF7B0FF91
+S3150800380810212046FFF786FF804608B14FF00108C9
+S315080038182046FFF793FF08B14FF0010800233361EC
+S315080038287361F3610AE0C3B94FF00060C2F8000992
+S3150800383800220A614FF67F328A6001330799994256
+S3150800384810D905EB431202F51061D2F800090028D1
+S31508003858E9DB0020C2F80009EAE74FF09040C2F811
+S315080038680009E5E700230AE0BBB14FF09047C2F824
+S31508003878007B002202614FF67F328260013399424B
+S3150800388810D905EB431202F53060D2F8007B002FF9
+S31508003898EADB0027C2F8007BEBE74FF00067C2F8BF
+S315080038A8007BE6E7336923F4807333610023A36159
+S315080038B86FF0804363610A9B1BB9A36943F0100341
+S315080038C8A361A2690A4B1343A3610D9B1BB1A369A4
+S315080038D843F00803A361119B012B04D04046BDE8B9
+S315080038E8F04104B07047A269024B1343A361F5E798
+S315080038F800383C8004000040D0F8083813F0060366
+S3150800390805D0062B18BF022B03D1022070470020CA
+S3150800391870470F207047000070B40B784A78012A60
+S3150800392820D0D0F81C2803F00F060124B44042EA38
+S315080039380442C0F81C2800EB4310D0F8003B13F4E7
+S31508003948004F0CD1D0F8002B8B68C3F30A03C9784B
+S3150800395843EA81431343134A1A43C0F8002B00204D
+S3150800396870BC7047D0F81C4803F00F06B24092B2F4
+S315080039782243C0F81C2800EB4310D0F8002912F49B
+S31508003988004FECD1D0F800498A68C2F30A02C97810
+S3150800399842EA814242EA83532343024A1A43C0F859
+S315080039A80029DCE70080001030B40B784A78012A31
+S315080039B824D000EB4313D3F8002B002A50DBD0F8A9
+S315080039C83C580A7802F00F02012404FA02F225EAA2
+S315080039D80242C0F83C28D0F81C28097801F00F01E3
+S315080039E88C4022EA0444C0F81C48D3F8001B234A32
+S315080039F80A40C3F8002B002030BC704700EB43137D
+S31508003A08D3F80029002A1EDBD0F83C580A7802F0B9
+S31508003A180F02012404FA02F292B225EA0202C0F859
+S31508003A283C28D0F81C28097801F00F018C40A4B26C
+S31508003A3822EA0404C0F81C48D3F80019104A0A40B8
+S31508003A48C3F80029D7E7D3F8002942F00062C3F87B
+S31508003A580029D3F8002942F08042C3F80029D3E7A1
+S31508003A68D3F8002B42F00062C3F8002BD3F8002BDA
+S31508003A7842F08042C3F8002BA1E700BF0078F3EFB5
+S31508003A88007833EC70B40B784C78012C24D000EB12
+S31508003A98431000F530631D693E4C2C401C611D69B6
+S31508003AA83D4C2C401C614C690CB18C684C611C69F6
+S31508003AB844F400241C611C698D68C5F312052C435F
+S31508003AC81C61012A61D0D0F8003B43F00443C0F8D2
+S31508003AD8003B002070BC70474C695CBB00EB431484
+S31508003AE8D4F810692C4D3540C4F81059D4F8105933
+S31508003AF845F40025C4F81059D4F81069254D354001
+S31508003B08C4F81059012A31D000EB4313D3F8002919
+S31508003B1842F00442C3F800294B69002BD9D0D0F8E3
+S31508003B283428097801F00F040121A1400A43C0F896
+S31508003B383428CEE700EB431404F510642669154DBE
+S31508003B48354025612669144D354025614E698D68CD
+S31508003B58AE4200D94D61256945F4002525612569D8
+S31508003B684E69C6F3120635432561CBE70A691AB1C9
+S31508003B7800EB4311C1F8142900EB4310D0F80029CB
+S31508003B8842F00442C0F80029A3E7CA68002A9AD076
+S31508003B985A6198E70000F8FFFFFF07E070B49DF840
+S31508003BA80C4064B903339D0807E000EB023303F5BC
+S31508003BB8805351F8046B1E600134AC42F5D30020DB
+S31508003BC870BC7047F0B583B00B784C78012C29D0B7
+S31508003BD800EB431303F5306426697D4D35402561AE
+S31508003BE826697C4D354025614D69002D40F0C18018
+S31508003BF825698E68C6F3120635432561256945F495
+S31508003C0800252561012A00F0C980CA78012A00F032
+S31508003C18CB80D3F8002B42F00442C3F8002B0020CF
+S31508003C2803B0F0BD4C6974BB00EB4314D4F81069B3
+S31508003C38684D3540C4F81059D4F8105945F400258C
+S31508003C48C4F81059D4F81069614D3540C4F81059AC
+S31508003C58012A4AD000EB4313D3F8004944F0044438
+S31508003C68C3F80049CC78012C68D04B69002BD6D00C
+S31508003C78D0F83428097801F00F040121A1400A4335
+S31508003C88C0F83428CBE700EB4314D4F81069504D34
+S31508003C983540C4F81059D4F810694E4D3540C4F863
+S31508003CA81059D4F810694D698F683D44013DB5FB34
+S31508003CB8F7F5494F07EAC5453543C4F81059D4F806
+S31508003CC810594E69C6F312063543C4F8105904F557
+S31508003CD81064CD78012DBBD1256925F0C04525612D
+S31508003CE8256945F000552561B2E70A691AB100EB5E
+S31508003CF84314C4F81429CA78012A08D000EB4313D8
+S31508003D08D3F8002942F00442C3F8002987E7D0F817
+S31508003D18082812F4807F08D100EB4311D1F800294E
+S31508003D2842F00052C1F80029E8E700EB4311D1F840
+S31508003D38002942F08052C1F80029DFE7D0F8084880
+S31508003D4814F4807F0ED1D3F8004944F00054C3F820
+S31508003D58004914460B46C9681A789B8A0094FFF7E7
+S31508003D681DFF5CE7D3F8004944F08054C3F80049BE
+S31508003D78EFE78E683544013DB5FBF6F52669164F1B
+S31508003D8807EAC5473E43266127698E68ADB206FB32
+S31508003D9805F5C5F312053D43256133E7CA68002AC8
+S31508003DA83FF433AF626130E7D0F8082812F4807F11
+S31508003DB806D1D3F8002B42F00052C3F8002B28E7A7
+S31508003DC8D3F8002B42F08052C3F8002B21E700BF36
+S31508003DD80000F8FFFFFF07E00000F81F033292080B
+S31508003DE8002393420CD210B400F58054246841F895
+S31508003DF8044B01339342F7D308465DF8044B7047E2
+S31508003E08084670470B784A78012A14D000EB431005
+S31508003E18D0F8002B002A06DB2BB1D0F8003B23F09C
+S31508003E288043C0F8003BD0F8003B43F40013C0F8C1
+S31508003E38003B0020704700EB4310D0F80029002A01
+S31508003E4806DB2BB1D0F8003923F08043C0F80039D7
+S31508003E58D0F8003943F40013C0F80039E9E70B78BD
+S31508003E684A78012A0ED000EB4310D0F8003B23F419
+S31508003E780013C0F8003BCB78023BDBB2012B15D9FF
+S31508003E880020704700EB4310D0F8003923F40013DC
+S31508003E98C0F80039CB78023BDBB2012BF0D8D0F852
+S31508003EA8003943F08053C0F80039E9E7D0F8003BF9
+S31508003EB843F08053C0F8003BE2E738B505460446A8
+S31508003EC8002208E004EB42134FF67F31C3F80819BD
+S31508003ED8C3F8081B01320E2AF4D90022C5F810289F
+S31508003EE8C5F81428C5F81C282846FFF727FC0346F2
+S31508003EF808B1184638BD10212846FFF70BFC0346BB
+S31508003F08F7E7D0F8003823F4FE63C0F80038D0F88D
+S31508003F180038090101F4FE610B43C0F80038002097
+S31508003F28704708B5D0F8043823F00203C0F80438F7
+S31508003F380320FCF7F1FD002008BD08B5D0F80438C1
+S31508003F4843F00203C0F804380320FCF7E5FD002017
+S31508003F5808BD4269806910407047D0F8183800F5DE
+S31508003F680060C0691840000C7047D0F8183800F58A
+S31508003F780060C069184080B2704700EB4111D1F85B
+S31508003F88082B00F5006040691040704710B4D0F857
+S31508003F981048D0F8343801F00F02D340DB01DBB201
+S31508003FA8234300EB411000F51060806818405DF85F
+S31508003FB8044B7047406900F001007047D0F80029A3
+S31508003FC8054B1340C0F80039D0F8043843F4807319
+S31508003FD8C0F804380020704700F8FFFF10B4046CD6
+S31508003FE8154B9C4203D9D0F8003B002B16DB00245E
+S31508003FF8C0F8104BD0F8104B44F40024C0F8104B06
+S31508004008D0F8104B44F01804C0F8104BD0F8104BF1
+S3150800401844F0C044C0F8104B012903D000205DF8CD
+S31508004028044B7047C0F8142BD0F8003B43F08023A4
+S31508004038C0F8003BF2E700BF0A30544F014B18603E
+S31508004048704700BF00000024C0B108B50346D0F881
+S31508004058B80210B10020C3F8B802D3F8CC0210B1E0
+S315080040680020C3F8CC0209B1C3F8B41218460123D4
+S3150800407880F89C32027001F0C9FF08BD032070471A
+S3150800408810B50446012380F89C32D0F8B83213B12B
+S315080040985B6801799847D4F8CC3213B10023C4F881
+S315080040A8CC32204602F024F8034608B1184610BD5B
+S315080040B8204602F00DF80346F8E710B582B000234B
+S315080040C8ADF8063059B10446C4F8B812CB6A0DF1F2
+S315080040D806009847C4F8CC02002002B010BD032099
+S315080040E8FBE708B501F0FCFF08BD08B5D0F8B832FB
+S315080040F813B11B68984708BD0320FCE708B5D0F834
+S31508004108B8320BB15B689847002008BD38B5044635
+S3150800411800F2AA25284600F02DF90123C4F894329E
+S31508004128B4F8B032C4F8983294F8AA1201F01F030A
+S31508004138012B0DD03BB1022B0FD001F08001204690
+S3150800414801F0F1FF03E02946204600F0CEFA38BD13
+S315080041582946204600F004FBF9E72946204600F0E0
+S3150800416833FBF4E710B5044629BB1346D0F8942266
+S31508004178032A01D0002029E0D0F85C11D0F8602184
+S3150800418891420DD8D0F8B8321B6923B190F89C2211
+S31508004198032A00D19847204600F067FC002015E05E
+S315080041A8891AC0F85C118A4228BF0A46194600F0DF
+S315080041B854FC00200AE00A46D0F8B8329B6933B1A5
+S315080041C890F89C12032904D11146984710BD03207C
+S315080041D8FCE70320FAE710B50446002946D113463A
+S315080041E8D0F89422022A05D094F8A032012B39D0A7
+S315080041F8002046E0C269016A8A4213D88A421DD05D
+S31508004208D4F8B832DB682BB194F89C22032A01D17A
+S31508004218204698478021204601F085FF204600F071
+S315080042282FFCE1E7521AC261194600F00EFC00237A
+S315080042381A461946204601F096FFD5E7836999423A
+S31508004248DED8D0F898229342DAD20022114600F036
+S31508004258FCFB0021C4F898120B460A46204601F0D2
+S3150800426882FFC1E7002084F8A0020AE00A46D0F8CF
+S31508004278B8325B6933B190F89C12032904D1114608
+S31508004288984710BD0320FCE70320FAE770B50446F3
+S31508004298012380F89C320023C0F894324360C0F8A2
+S315080042A8A432D0F8BC3223B1D0F8B8325B68002102
+S315080042B89847402300221146204601F021FF01268F
+S315080042C8A4F864614025C4F860512B460022802171
+S315080042D8204601F015FFA6842562002070BD0174EA
+S315080042E80020704790F89C3280F89D32042380F8A5
+S315080042F89C320020704790F89C32042B01D000208D
+S31508004308704790F89D3280F89C32F8E708B590F81F
+S315080043189C32032B01D0002008BDD0F8B832DB69DF
+S31508004328002BF8D09847F6E700207047002070471A
+S315080043380020704708B5012380F89C32D0F8B832B7
+S3150800434813B15B6801799847002008BD002302E08D
+S315080043580133DBB201300278002AF9D118467047D2
+S3150800436808B54B88012B00D008BDC0F8A43200F068
+S315080043787CFBF9E70B7803704B7843708B78CA781F
+S3150800438843EA022343800B794A7943EA0223838066
+S315080043988B79CA7943EA0223C380704710B5044665
+S315080043A8802101F0C0FE0021204601F0BCFE10BDA8
+S315080043B830B583B004460D460023ADF806304A8862
+S315080043C8130A013B062B00F2AB80DFE803F0041F53
+S315080043D833A9A98D9A00D0F8B4321B680DF10601E5
+S315080043E8007C9847EA88002A00F0A380BDF80630C2
+S315080043F8002B00F099809A4228BF1A46ADF8062085
+S315080044080146204600F014FB03B030BD037C43B9CF
+S31508004418D0F8B8329B6A0DF1060098470223437014
+S31508004428E0E7D0F8B832DB6A0DF1060098470223B0
+S315080044384370D7E7D2B2052A52D8DFE802F003104C
+S315080044481D2A3744D0F8B4325B6823B10DF106014A
+S31508004458007C9847C6E72946FFF7A0FFD4E7D0F8B7
+S31508004468B4329B6823B10DF10601007C9847B9E779
+S315080044782946FFF793FFC7E7D0F8B432DB6823B1BC
+S315080044880DF10601007C9847ACE72946FFF786FF39
+S31508004498BAE7D0F8B4321B6923B10DF10601007CDE
+S315080044A898479FE72946FFF779FFADE7D0F8B43272
+S315080044B85B6923B10DF10601007C984792E7294606
+S315080044C8FFF76CFFA0E7D0F8B4329B6923B10DF16A
+S315080044D80601007C984785E72946FFF75FFF93E7BB
+S315080044E82946FFF75BFF8FE7037C33B9D0F8B83264
+S315080044F85B6B0DF10600984774E72946FFF74EFFF0
+S3150800450882E7037C43B9D0F8B8321B6B0DF1060075
+S3150800451898470723437065E72946FFF73FFF73E780
+S315080045282946FFF73BFF6FE729462046FFF736FF80
+S315080045386AE7204600F099FA66E738B504468B8894
+S31508004548F3B9CB88E3B94B887F2B19D803F07F05D5
+S3150800455890F89C32032B0CD080F89E52294601F01D
+S31508004568F2FD204600F081FA35B1022384F89C3220
+S3150800457809E0FFF713FF06E0012384F89C3202E0FE
+S315080045882046FFF70BFF38BD70B504460D468978F7
+S315080045982E4B197001290FD890F89C32022B11D08E
+S315080045A8032B25D02946FFF7F9FE284B197820460C
+S315080045B8FFF7A4FD032603E02946FFF7EFFE0326C7
+S315080045C8304670BD81B14160FFF78FFD064620B1C0
+S315080045D829462046FFF7E2FEF2E7204600F045FAAC
+S315080045E8032384F89C32EBE700F03FFA0026E7E756
+S315080045F8C9B14368994225D0D9B2FFF77FFD134B55
+S31508004608197861602046FFF770FD0646B0B129465D
+S315080046182046FFF7C3FE21792046FFF76FFD0223E0
+S3150800462884F89C32CCE7022380F89C324160FFF775
+S3150800463865FD204600F019FA0026C1E7204600F075
+S3150800464814FABDE700F011FA0026B9E7EC000024D1
+S3150800465808B5CB88012B0BD190F89C329BB1022B5D
+S3150800466809D9032B0FD10122011D00F0E1F901E058
+S31508004678FFF794FE08BD0146002341F8083F0122CA
+S3150800468800F0D6F9F6E7FFF789FEF3E708B590F8DC
+S315080046989C32013B022B12D8CB88022B0CD1012362
+S315080046A8C360D0F8A4320BB10323C360022200F119
+S315080046B80C0100F0BDF908BDFFF770FEFBE7FFF730
+S315080046C86DFEF8E708B590F89C32013B022B09D82D
+S315080046D84B88012B00D008BD0023C0F8A43200F08F
+S315080046E8C4F9F8E7FFF75AFEF5E708B50B7803F0BB
+S315080046F86003202B06D0402B04D043B1FFF74EFEAB
+S31508004708002003E0D0F8B8329B68984708BD4B7874
+S31508004718092B21D8DFE803F0141C201820090520E6
+S31508004728100DFFF745FE0020F0E7FFF706FF00200B
+S31508004738ECE7FFF729FFE9E7FFF78AFF0020E5E737
+S31508004748FFF7A4FF0020E1E7FFF70AFE0020DDE7F0
+S31508004758FFF7B8FF0020D9E7FFF720FE0020D5E7C6
+S3150800476870B505460C460B7803F06003202B07D076
+S31508004778402B05D023B1FFF711FE0026304670BD41
+S3150800478895F89C32013B022B18D82379012B0FD8B0
+S31508004798D5F8B8329B682146284698470646E388DE
+S315080047A8002BEBD10028E9D1284600F05EF9E5E7A9
+S315080047B821462846FFF7F2FD0026DFE72146284668
+S315080047C8FFF7ECFD0026D9E738B505460C468A8872
+S315080047D80B7803F06003202B08D0D1B2402B05D004
+S315080047E85BB12146FFF7DAFD002005E0D5F8B832B7
+S315080047F89B6821462846984738BD6378012B38D0E8
+S31508004808002B6BD0032B40F0F08090F89C32022BDB
+S3150800481806D0032B19D02146FFF7C0FD0020EBE789
+S31508004828B1F1800318BF0123002908BF00233BB153
+S3150800483801F079FC8021284601F075FC0020DBE7A9
+S315080048482146FFF7ABFD0020D6E763884BB9B1F1DF
+S31508004858800318BF0123002908BF00230BB1E3888A
+S3150800486823B1284600F001F90020C5E701F05BFCF2
+S31508004878F7E790F89C32022B06D0032B19D021466D
+S31508004888FFF78CFD0020B7E7B1F1800318BF0123B5
+S31508004898002908BF00233BB101F045FC80212846C2
+S315080048A801F041FC0020A7E72146FFF777FD002025
+S315080048B8A2E76388002B40F09D8011F07F0F0AD18C
+S315080048C8284600F0D2F8D5F8B8329B68214628461B
+S315080048D89847002090E701F02EFCF1E790F89C3203
+S315080048E8022B06D0032B2FD02146FFF757FD0020B1
+S315080048F882E7B1F1800318BF0123002908BF002306
+S315080049089BB912F0800F15D101F07F0101EB8101E7
+S315080049188B0003F5A8710144043100240C600222B7
+S31508004928284600F085F8204666E72146FFF736FD53
+S31508004938002061E701F07F0101EB81018B0003F19B
+S31508004948100101440431E8E752B2002A24DB01F0D9
+S315080049580F0303EB830398002844B0F8643153B374
+S31508004968002A2EDB01F07F0202EB8202930003F590
+S31508004978A8742C440434802914BF00230123002971
+S3150800498808BF01233BB30023236002222146284699
+S3150800499800F04EF800202FE701F00F0303EB83031E
+S315080049A898002844838C002BDAD121462846FFF73D
+S315080049B8F5FC002020E721462846FFF7EFFC0020F3
+S315080049C81AE701F07F0202EB8202930003F1100452
+S315080049D82C440434CFE7284601F054FB10B10123D0
+S315080049E82360D2E700232360CFE72146FFF7D6FCEA
+S315080049F8002001E70020FFE6C8B170B50D46164647
+S31508004A080446FFF7A3FC01304000308028700323D2
+S31508004A186B70022307E0EA5401345A1CD2B200210B
+S31508004A28A9540233DBB22278002AF4D170BD704744
+S31508004A3810B513460222C0F894228361C3610A4658
+S31508004A48002101F088FB002010BD08B513460A4668
+S31508004A58002101F080FB002008BD08B513460A4668
+S31508004A68002101F080FB002008BD08B50423C0F822
+S31508004A78943200231A46194601F06DFB002008BD3A
+S31508004A8808B50523C0F8943200231A46194601F0DA
+S31508004A986AFB002008BD72B6704762B67047000008
+S31508004AA8F0B4194D2C6D24F040542C65002401E00F
+S31508004AB80134E4B2112C23D8144D15F8146005EB0B
+S31508004AC844056F78F51905FB00054FF4FA5CBCFB3D
+S31508004AD8F5FC05FB0CF5B5F5FA5FE9D135463D4415
+S31508004AE805FB000C4FF4FA55B5FBFCF50D80013DA6
+S31508004AF8ADB2B5F5007FDBD216701F70012000E055
+S31508004B080020F0BC704700BF00440258F062000855
+S31508004B1870B58CB00022ADF82E208DF82D200CAB80
+S31508004B2803F8042D0DF12D020DF12E014FF4FA703C
+S31508004B38FFF7B6FF002842D0234C244B23600025F4
+S31508004B48A560E560012626746574A574BDF82E303F
+S31508004B586361A6619DF82D30E3619DF82C302362C8
+S31508004B686662A662E66226636563A663E5632664EB
+S31508004B7804236364A564E36425656365A565E6653A
+S31508004B8825666566A3662046FCF75EF903950495CF
+S31508004B980596069640F2676307930893099503A94D
+S31508004BA82046FCF79BFA0096334602221146204611
+S31508004BB8FCF7D7FA2046FCF7F0FA0CB070BDB82116
+S31508004BC8034800F08BFDB7E7F000002400A000407A
+S31508004BD8B462000810B58AB040F2E1730193002365
+S31508004BE8029303930904049105930693079308937C
+S31508004BF8522309930123024601A90E48FCF7E7FA4E
+S31508004C0808B10AB010BD01210A48FCF716FB0028AE
+S31508004C18F7D100F071FB00F1320401210548FCF7D1
+S31508004C28FDFB0028EDD000F063FE00F065FBA0420E
+S31508004C38F3D9E6E7F000002430B58BB004460D46F4
+S31508004C4840211048FCF7F3FB10B900200BB030BD23
+S31508004C5823466A4640210B48FCF702FB68B9009AC6
+S31508004C6840F267639A4201D00020EFE7019B33B907
+S31508004C789DF80E302B700120E8E70020E6E70020B3
+S31508004C88E4E700BFF000002408B5FFF704FF08BDF5
+S31508004C9810B500F03DFA00B910BDFBF721FB002856
+S31508004CA8FAD000F0CFFDFBF793FE00F0FBFA00F010
+S31508004CB833FA054B0340054A936000F02DFA446819
+S31508004CC8FFF7EBFEA047E7E780FFFF1F00ED00E0D0
+S31508004CD870B508E04D1C461C0B78037000F008FEFA
+S31508004CE8304629462246531E9CB2002AF2D170BD88
+S31508004CF838B50546002401E00134E4B20E2C12D872
+S31508004D0800F0F6FD04EB44029300084AD358AB4278
+S31508004D18F2D804EB44029100044A0A445268134440
+S31508004D28AB42E9D900E0FF24204638BD14630008E1
+S31508004D3808B5C1F3090353B903688B4209D040F88B
+S31508004D48041B4FF48062FFF7C3FF012000E0002030
+S31508004D5808BD0120FCE72DE9F04107460068FFF782
+S31508004D68C7FFFF282CD0FCF771FB00264FF0010877
+S31508004D7805E04FF00008B8F1000F1CD001361F2EC9
+S31508004D8819D83D68740125443C44043400F0B0FD44
+S31508004D98224629460120FCF721FC50B900231F2B7F
+S31508004DA8E9D8595DE25CD2B29142E2D10133DBB26D
+S31508004DB8F5E74FF00008FCF777FB4046BDE8F081B9
+S31508004DC84FF00008F9E7000070B50E460E4B9842FA
+S31508004DD812D004460D4B994209D10B4D2C4625B1E4
+S31508004DE831462046FFF7A4FF58B1284670BDFFF79D
+S31508004DF8B2FF20B12546F2E7054D2C46EFE7002518
+S31508004E08EDE70025F1E700BF940500240000020835
+S31508004E18900100242DE9F84305460C4617461E4618
+S31508004E28DFF8848001EA08080368B3F1FF3F0AD06F
+S31508004E382B6843450ED14FF00109B9F1010F12D07D
+S31508004E484846BDE8F8834146FFF772FF81460028C1
+S31508004E58F3D0EDE741462846FFF7B6FF0546E8B121
+S31508004E684FF00109E9E72B68E41A2C44043405E0F5
+S31508004E7817F8013B04F8013B013EE1D000F038FD84
+S31508004E882B1DE31AB3F5806FF2D308F5806128461F
+S31508004E98FFF79AFF054620B1041DE9E74FF0000918
+S31508004EA8CEE74FF00009CBE700FCFFFF70B586B0E8
+S31508004EB804460D4600230093884203D80E2937D89E
+S31508004EC8012600E0002616B9304606B070BDFCF784
+S31508004ED8BDFAAC4227D800F00BFD164963002344F7
+S31508004EE89A008B188A585B68002B18BFB2F1FF3FE7
+S31508004EF818D000230193202305930A46630018193E
+S31508004F08810008461144497A02910244137A0393A8
+S31508004F1801230493694601A8FCF730FC30B901342B
+S31508004F28E4B2D6E70026FCF7BFFACDE70026FAE78B
+S31508004F380026C9E7146300084FF0FF33024A1360D6
+S31508004F48024A1360704700BF9001002494050024A4
+S31508004F5870B504460D4616464A1E154B1B1A9A4244
+S31508004F6803D9002001280CD070BDFFF7C1FEFF2821
+S31508004F781AD028190138FFF7BBFEFF2816D00120DA
+S31508004F88F0E70C4B23400C4A934206D02B46324690
+S31508004F9821460A48FFF73EFFE6E72B4632462146F2
+S31508004FA80748FFF737FFDFE70020DDE70020DBE7E4
+S31508004FB8FFFF1F0800FCFFFF0000020890010024FD
+S31508004FC89405002470B54A1E0F4B1B1A9A4205D938
+S31508004FD8FF210E460020012812D070BD05460C4652
+S31508004FE8FFF786FE064660190138FFF781FE014677
+S31508004FF8FF2818BFFF2E01D00120ECE70020EAE7BA
+S315080050083046FFF753FFE8E7FFFF1F08104B1B68FA
+S31508005018B3F1FF3F1AD000B583B00D4A53689168BB
+S315080050280B44D1680B4411690B4451690B449169C7
+S315080050380B44D26913445B4202AA42F8043D042190
+S315080050480448FFF785FF03B05DF804FB01207047A5
+S3150800505894050024980202080D4B1B680D4A12682D
+S315080050681A440D4B1B6813440C4A126813440C4A1D
+S3150800507812681A440B4B1B681A440B4B1B681344DB
+S315080050880A4A1268DA4201D00020704701207047A0
+S315080050980000020804000208080002080C000208BA
+S315080050A810000208140002081800020898020208EC
+S315080050B808B50D4B1B68B3F1FF3F0BD10B4B1B68AB
+S315080050C8B3F1FF3F0DD00948FFF745FE034648B13F
+S315080050D8012307E00448FFF73EFE03460028EDD102
+S315080050E800E00123184608BD940500249001002411
+S315080050F8004870470000020808B5FFF71DFF08BDFD
+S3150800510808B5FFF725FF08BD08B5FFF75BFF08BD1B
+S3150800511808B5FFF7A1FF08BD08B5FFF7E9FF08BD01
+S3150800512808B5FFF773FF034608B9184608BDFFF721
+S31508005138BFFF0346F9E70000054BDB6913F0200FAC
+S3150800514804D0034B5B6A0370012070470020704740
+S315080051580048004010B5094B986200F0CDF800F1F8
+S315080051680A04064BDB6913F0800F05D100F0C0FB73
+S3150800517800F0C2F8A042F4D910BD00BF00480040AC
+S3150800518810B588B00D4C236823F00103236000236B
+S3150800519800934FF4614201920293039304930C22FD
+S315080051A805920693079369462046FEF709F9236888
+S315080051B843F00103236008B010BD00BF0048004053
+S315080051C870B506460D46402904D82846FFF7C2FF9B
+S315080051D800240BE08421074800F080FAF5E700F080
+S315080051E887FB305DFFF7B6FF0134A4B2ABB2A34222
+S315080051F8F5D870BDC863000870B5254B1C78BCB9CE
+S315080052082448FFF799FF012801D0204670BD214B95
+S315080052181B78013BDBB23F2BF7D800F06DF81E4B25
+S3150800522818601E4B00221A70194B01221A70ECE7F7
+S3150800523806460D46194B1B78013316481844FFF7DE
+S315080052487BFF0446012815D1144B1A780132D2B2CD
+S315080052581A70104B1B789A4201D00024D5E71049DA
+S315080052683046FFF735FD0A4B00221A700B4B1B78A0
+S315080052782B70CAE700F040F8074B1B68643398425E
+S3150800528803D90024024B1C70BFE70024BDE700BF02
+S31508005298D909002498090024DC090024DA0900241D
+S315080052A899090024024B00221A605A609A607047CE
+S315080052B810E000E008B5FFF7F5FF054B054A5A6008
+S315080052C800229A6005211960034B1A6008BD00BFC1
+S315080052D810E000E0FF520700E0090024044B1B68B1
+S315080052E813F4803F03D0034A1368013313607047E9
+S315080052F810E000E0E009002408B5FFF7EFFF014BCE
+S31508005308186808BDE009002408B5FFF7F5FF08BDC9
+S31508005318094B03F11801002232B19A7400225A6126
+S31508005328064B054A1A6070479A745961183318313A
+S315080053380132D2B2F0E700BF240A0024540A002436
+S315080053480A4B1B6883B110B45C69084A146019745F
+S315080053589860D86000225A74186001390844586061
+S31508005368987C5DF8044B7047FF207047540A002460
+S3150800537838B504460D4601281CD862002244D100D7
+S31508005388114B0B445A7C1B7C9A4219D00E4B0B4482
+S31508005398DA6815705A7C01325A74DA680132DA60AA
+S315080053A85B689A420ED9084A084651580244D160A1
+S315080053B8012038BD4FF4E171044800F08FF9DCE7A5
+S315080053C80020F6E70120F4E7240A00240864000808
+S315080053D808B50146024B1878FFF7CAFF08BD00BF93
+S315080053E8580A002438B504460D4601281ED804EB89
+S315080053F84403DA00124B13445B7CEBB16200224487
+S31508005408D1000F4B0B449A6812782A705A7C013AD5
+S315080054185A749A6801329A605B689A420ED9084AA1
+S315080054280846515802449160012006E04FF4F2718B
+S31508005438044800F053F9DAE7002038BD0120FCE7F4
+S31508005448240A00240864000808B50146024B18789F
+S31508005458FFF7C8FF08BD00BF9C0A002410B504461C
+S31508005468012804D94FF40171044800F037F904EB10
+S315080054784404E200024B1344587C10BD0864000833
+S31508005488240A002438B5FFF743FF1B4C4021601C4B
+S31508005498FFF756FF2070194D4021681CFFF750FF8B
+S315080054A828702378FF2B1DD0FF281BD0144C002208
+S315080054B814492046FEF7C8FD13492046FEF7FDFDA8
+S315080054C80120FAF724FF2046FEF70BFEFDF7C4F97C
+S315080054D8D4F8C402FCF7ECFF00F02CF9B0F5FA6F23
+S315080054E805D338BD8521094800F0F8F8DEE74FF4FA
+S315080054F8FA6000F019F9F4E7580A00249C0A00240F
+S31508005508E00A00247800002414000024086400082F
+S3150800551810B5064CD4F8C402FCF7E8FF2046FEF797
+S31508005528AFFD0020FAF7F3FE10BD00BFE00A00241D
+S3150800553870B506460D463F2906D82846FFF748FFA0
+S31508005548012806D100240BE0BB210D4800F0C6F857
+S31508005558F3E7BF210A4800F0C1F8F3E70134A4B21B
+S31508005568ABB2A3420BD900F0C3F9305DFFF730FFA1
+S315080055780128F3D0C821024800F0B0F8EEE770BD5C
+S315080055880864000870B506460D461F4BD3F8C402D2
+S31508005598FCF71AFD1D4B1C789CB91D48FFF754FFEC
+S315080055A8012801D0204670BD194B1B78013BDBB298
+S315080055B83E2BF7D8154B01221A70164B00221A7083
+S315080055C8F0E7144B1B78013311481844FFF73CFFE2
+S315080055D80446012801D00024E4E70E4B1A78013264
+S315080055E8D2B21A700A4B1B789A4201D00024D9E71E
+S315080055F809493046FFF76CFB044B00221A70054B25
+S315080056081B782B70CEE700BFE00A0024F00D0024B3
+S31508005618B00D0024F10D0024B10D002430B583B077
+S31508005628144B1878FFF71AFF08B30546402800D91F
+S315080056384025002405E09DF807200F4B1A5501342C
+S31508005648E4B2A5420DD90DF107010A4B1878FFF700
+S31508005658C9FE0128EFD04FF4A471084800F03EF8B7
+S31508005668E9E72B46044A8121054800F074FD03B092
+S3150800567830BD00BF580A0024E4090024086400085D
+S31508005688E00A002470B5044600F0A8FB0646214641
+S315080056980F4800F00EFD85B2002401E00134A4B2DB
+S315080056A8AC420CD2315D0B4B1878FFF761FE012826
+S315080056B8F4D04FF4B571084800F010F8EEE700F09A
+S315080056C88DFB402302460121014800F04CFD70BDC0
+S315080056D8E00A00249C0A00240864000808B500F0BB
+S315080056E807F9FCE708B500F0F7F8012803D00B4BD3
+S315080056F81B78012B00D008BDFFF7FEFD084B1B6879
+S31508005708084A1268134403F5FA739842F3D3034B0D
+S3150800571800221A70FFF7BCFAEDE700BFF80D00245F
+S31508005728F40D0024FC0D0024014B1860704700BFD7
+S31508005738F40D0024014B1868704700BFF40D0024C7
+S3150800574808B5054B1B78012B00D008BDFFF7D4FD1B
+S31508005758024B1860F9E700BFF80D0024FC0D002479
+S3150800576808B5044B01221A70FFF7EAFFFFF7BAFFDC
+S3150800577808BD00BFF80D002408B5FFF785FA00F044
+S31508005788B3F8FFF797FDFFF7B7FC00F00DF8FFF73A
+S31508005798E7FF08BD08B500F0ABF8FFF79FFD00F076
+S315080057A817F8FFF79FFF08BD10B500F00FFAFFF7C7
+S315080057B8AFF9064C01232370FFF7E2FC0023237098
+S315080057C8FFF760FE0223237010BD00BF10000024F7
+S315080057D800B583B00DF107011848FFF72DFA01281F
+S315080057E810D00DF107011548FFF706FD012812D05C
+S315080057F80DF107011148FFF7C5FE012814D003B0BB
+S315080058085DF804FB0E4B01221A709DF807100B4829
+S3150800581800F0FCF9E5E70A4B00221A709DF8071014
+S31508005828064800F0F3F9E3E7054B02221A709DF8DB
+S315080058380710024800F0EAF9E1E700BF000E002465
+S315080058481000002408B5FFF763FE08BD38B50446FE
+S315080058580D460E4B1B78012B09D00C4B1B7853B100
+S315080058680A4B1B78022B0BD000F0C8F938BDC9B211
+S31508005878FFF7B0F9F1E7E9B22046FFF7A1FCEFE731
+S31508005888E9B22046FFF754FEEEE700BF10000024F1
+S31508005898074B1B78022B05D0032B05D0012B05D007
+S315080058A8402070473F2070470020704708207047FF
+S315080058B810000024074B1B78022B05D0032B05D0B4
+S315080058C8012B05D0402070473F20704700207047BD
+S315080058D8082070471000002408B500F085F903462B
+S315080058E800B10123184608BD08B5FAF707FD08BD33
+S315080058F808B5FAF708FD08BD014B00225A7070472B
+S31508005908400E0024034BFE22DA7018710222A3F80F
+S3150800591844207047400E002410B5054C0023237018
+S31508005928FFF7EAFFFF23E3700123A4F8443010BD0C
+S31508005938400E0024064BFF22DA7000221A715978A5
+S3150800594859719A71DA711A720622A3F844207047B7
+S31508005958400E002408B50020FFF7D4FF08BD000054
+S31508005968074BFF22DA70074A9A6400221A715A719D
+S315080059789A710722C3F807200822A3F8442070471B
+S31508005988400E002444640008044BFF22DA7042687B
+S315080059989A640122A3F84420704700BF400E0024E9
+S315080059A808B53120FFF7AEFF08BD000038B5084C2A
+S315080059B8FF23E370002525716571FFF769FFA0715C
+S315080059C8E571257265720723A4F8443038BD00BF0F
+S315080059D8400E002438B5FFF78FFF0E4C01252570B9
+S315080059E8FF23E3701023237100236371FFF750FF29
+S315080059F8A071FFF75FFFE071FFF75CFFC0F30720B0
+S31508005A0820726572A5720823A4F84430FFF774FB60
+S31508005A1838BD00BF400E002438B505464478FFF760
+S31508005A2837FF0138844210DC0A4C6A78A16C201DBD
+S31508005A38FFF74EF9FF23E3706A78A36C1344A3644F
+S31508005A486B780133A4F8443038BD2220FFF75AFF93
+S31508005A58FAE700BF400E002438B504464578FFF734
+S31508005A6817FF0138854211DC61680A4DA964627816
+S31508005A78281DFFF72DF9FF23EB706278AB6C1344EA
+S31508005A88AB6463780133A5F8443038BD2220FFF7A4
+S31508005A9839FFFAE7400E0024F8B5054617460024EC
+S31508005AA806E015F8013B1C44E4B2FFF721FF31462E
+S31508005AB84E1E0029F5D13C600120F8BD10B5084CEA
+S31508005AC8FF23E370E21D4168A06CFFF7E5FF20712C
+S31508005AD800236371A3710823A4F8443010BD00BFDE
+S31508005AE8400E002438B505460D4B9C6CFFF7D0FED2
+S31508005AF86A1C411E2046FFF703FB60B1084CFF23CA
+S31508005B08E370FFF7C5FE0138A36C0344A3640123B9
+S31508005B18A4F8443038BD3120FFF7F4FEFAE700BF91
+S31508005B28400E002438B504464578FFF7B1FE02381A
+S31508005B3885420EDC114BFF22DA700122A3F84420B5
+S31508005B48617851B9FFF7ECFA30B93120FFF7DAFE78
+S31508005B5802E02220FFF7D6FE38BDA21C074B986C38
+S31508005B68FFF7CEFA28B16178044A936C0B4493641C
+S31508005B78F2E73120FFF7C6FEEEE700BF400E002425
+S31508005B8808B54168074B986CFFF7BEFA30B1054B64
+S31508005B98FF22DA700122A3F8442008BD3120FFF756
+S31508005BA8B1FEFAE7400E002408B5FFF771F8034B73
+S31508005BB8FF22DA700122A3F8442008BD400E00240B
+S31508005BC808B589B2FFF742FE08BD0000054B00225A
+S31508005BD81A709A6483F84320A3F844209A705A7076
+S31508005BE8704700BF400E0024034B1B780BB10120F9
+S31508005BF870470020704700BF400E0024024B002261
+S31508005C0883F84320704700BF400E002408B5037880
+S31508005C18FF2B04D0354A1278012A14D008BDFFF79D
+S31508005C28D9FE324B93F84330012B5AD02F4BB3F990
+S31508005C3844100029F2DD1846012380F84330033062
+S31508005C48FFF7BEFFEAE7C93B352B46D8DFE803F07E
+S31508005C583345454245453F363C394545454545451D
+S31508005C6845454545454545454545454545454545CE
+S31508005C7845454545454545454545241E1B21454554
+S31508005C884527452A2D30FFF7C7FECAE7FFF7E4FE82
+S31508005C98C7E7FFF779FEC4E7FFF710FFC1E7FFF785
+S31508005CA85FFEBEE7FFF756FEBBE7FFF743FEB8E71A
+S31508005CB8FFF732FEB5E7FFF715FFB2E7FFF732FF42
+S31508005CC8AFE7FFF773FEACE7FFF75AFFA9E7FFF759
+S31508005CD86BFFA6E7FFF764FEA3E72020FFF712FE8F
+S31508005CE89FE71020FFF70EFEA0E700BF400E00242E
+S31508005CF820230380004870474C0000240A230380A9
+S31508005D08004870476C00002408B590F89C32032BAD
+S31508005D1801D0002008BDFFF781FCFAE708B5FFF7B0
+S31508005D287DFC002008BD08B50846FFF7ABFC002037
+S31508005D3808BD000008B50B7813F0600F06D14B783C
+S31508005D480A2B14D00B2B17D0062B01D0002008BD20
+S31508005D584B881B0A212B04D00B491722FEF768FE2D
+S31508005D68F4E7CA88172A28BF17220849F6E701223E
+S31508005D780749FEF75DFEE9E78B7813B9044A13600D
+S31508005D88E4E7FEF70BFBE1E7550000245E00002474
+S31508005D988C0E002410B50446812100F0BCF90121B7
+S31508005DA8204600F0B8F9002010BD000010B50446DA
+S31508005DB840230222812100F0A3F94023022201216F
+S31508005DC8204600F09DF94023034A0121204600F0A9
+S31508005DD8CAF9002010BD00BF5813002400487047B0
+S31508005DE85813002412230B80004870479400002497
+S31508005DF804230B8000487047A80000240023934218
+S31508005E0816D230B40BE0373401F8134000015C00B1
+S31508005E18013400250D550133DBB2934206D2040F2F
+S31508005E28092CF0D8303401F81340EFE730BC704736
+S31508005E387047000038B50A4B186804331C680433E1
+S31508005E481B68C01800D138BD064D0822A91CFFF7E3
+S31508005E58D5FF042205F112012046FFF7CFFFF2E726
+S31508005E6800E8F11FAC00002408B51A230B80FFF7D9
+S31508005E78E1FF014808BD00BFAC00002408B50A4682
+S31508005E8828B105490548FEF7B7FD034808BD024984
+S31508005E980248FEF7B1FDF8E7981300247C64000869
+S31508005EA810B5044C0A4621460348FEF7A5FD2046C8
+S31508005EB810BD00BF981300246C64000808B50A468C
+S31508005EC828B105490548FEF797FD034808BD024964
+S31508005ED80248FEF791FDF8E7981300244C64000879
+S31508005EE808B50A4628B105490548FEF785FD034859
+S31508005EF808BD02490248FEF77FFDF8E79813002413
+S31508005F085464000808B500F57171D0F80404FEF762
+S31508005F18FDF808BD08B5C1EBC10293000344D3F8E0
+S31508005F280822D0F80404FEF71DF908BD08B5C1EB28
+S31508005F38C102930003449A6CD0F80404FEF74BF99F
+S31508005F4808BD08B5D0F80404FEF7E0F908BD000056
+S31508005F5810B50446C3683BB1022B0FD091210848F7
+S31508005F68FFF7BCFB012100E00021D4F80404FEF782
+S31508005F78B6F9D4F80404FEF789F910BD0121F4E747
+S31508005F889064000810B50446D0F80404FEF7AAF988
+S31508005F982268D2F8003E43F00103C2F8003E236A9D
+S31508005FA823B1044A136943F006031361FAF7B0F9F3
+S31508005FB810BD00BF00ED00E010B50446FAF7A9F9D0
+S31508005FC8D4F80404FEF797F910BD08B5D0F8040408
+S31508005FD8FEF7ACF908BD08B5D0F80404FEF7A4F92D
+S31508005FE808BD10B504460120FAF791F9D4F8040457
+S31508005FF8FEF79EF910BD10B504460020FAF787F992
+S31508006008D4F80404FEF796F910BD000003780BB11E
+S315080060180020704710B503461748C0F80434C3F87B
+S31508006028C402164B0360092343600222C260002398
+S31508006038036182610122C261036243628362C362A9
+S315080060480363FBF72FFE80B90B4C80212046FCF72B
+S31508006058E8FB402200212046FCF7BFFB80220121ED
+S315080060682046FCF7BAFB002010BD4FF4937104488C
+S31508006078FFF734FBE8E700BF900E0024000008404D
+S3150800608890640008D0F8C43211F0800F08D101F0E6
+S315080060987F01C1EBC1018A00134493F8FE017047DA
+S315080060A801F07F01C1EBC1018A00134493F83E0051
+S315080060B8704708B5D0F8C402FCF7E4FA08BD18B169
+S315080060C8022803D003207047002070470120704734
+S315080060D808B5D0F8C402FBF7BEFEFFF7F0FF08BD07
+S315080060E808B5D0F8C402FBF775FEFFF7E8FF08BD48
+S315080060F808B5D0F8C402FBF78EFEFFF7E0FF08BD27
+S3150800610810B51C4613462246D0F8C402FCF714FA02
+S31508006118FFF7D5FF10BD08B5D0F8C402FCF74DFA4D
+S31508006128FFF7CDFF08BD08B5D0F8C402FCF7DDFABD
+S31508006138FFF7C5FF08BD08B5D0F8C402FCF716FB7B
+S31508006148FFF7BDFF08BD08B5D0F8C402FCF7E0F9AB
+S31508006158FFF7B5FF08BD08B5D0F8C402FCF79BFAE7
+S31508006168FFF7ADFF08BD08B5D0F8C402FCF75CFA1E
+S31508006178FFF7A5FF08BD000070B50D4E0D4CA41B12
+S31508006188A4100025A54209D10B4E0C4C00F02CF89A
+S31508006198A41BA4100025A54205D170BD56F82530C4
+S315080061A898470135EEE756F8253098470135F2E75E
+S315080061B8B4640008B4640008B4640008B864000845
+S315080061C810B5431E0A44914200D110BD11F8014B7F
+S315080061D803F8014FF7E702440346934200D1704794
+S315080061E803F8011BF9E70000F8B500BFF8BC08BCBE
+S315080061F89E467047F8B500BFF8BC08BC9E4670476F
+S315080062080000000000000000000000000000000078
+S315080062180000000001000000020000000300000062
+S31508006228040000000000000005000000000000004F
+S315080062380000000000000000060000000000000042
+S315080062480000000000000000070000000000000031
+S3150800625801020304010203040607080900010203F0
+S3150800626804050607080C1014182030400000000022
+S3150800627801020304010203040607080901000000D5
+S3150800628802000000040000000600000008000000E4
+S315080062980A0000000C0000001000000020000000A2
+S315080062A8400000008000000000010000433A2F5714
+S315080062B86F726B2F736F6674776172652F4F70658F
+S315080062C86E424C542F5461726765742F536F7572FA
+S315080062D863652F41524D434D375F53544D3332480A
+S315080062E8372F63616E2E630005020602060307034D
+S315080062F80803090309040A040B040C040C050D0514
+S315080063080E050F050F0610061007100800000208EC
+S315080063180000020001010000000004080000020055
+S315080063280201000000000608000002000301000040
+S3150800633800000808000002000401000000000A081E
+S31508006348000002000501000000000C080000020019
+S315080063580601000000000E08000002000701000000
+S3150800636800001008000002000002000000001208E1
+S3150800637800000200010200000000140800000200E4
+S3150800638802020000000016080000020003020000CE
+S3150800639800001808000002000402000000001A089D
+S315080063A8000002000502000000001C0800000200A8
+S315080063B80602000000001E0800000200070200008E
+S315080063C8433A2F576F726B2F736F667477617265CE
+S315080063D82F4F70656E424C542F5461726765742F3F
+S315080063E8536F757263652F41524D434D375F53544A
+S315080063F84D333248372F72733233322E630000001A
+S31508006408433A2F576F726B2F736F6674776172658D
+S315080064182F4F70656E424C542F5461726765742FFE
+S31508006428536F757263652F41524D434D375F535409
+S315080064384D333248372F7573622E63004F70656E79
+S31508006448424C540044656661756C740057696E550C
+S3150800645853422042756C6B20496E74657266616397
+S31508006468650000004F70656E424C5420557365727E
+S315080064780000000057696E5553422042756C6B2020
+S3150800648844657669636500002E2E2F5553425F448E
+S3150800649845564943452F5461726765742F7573626B
+S311080064A8645F636F6E662E6300000000E0
+S309080064B4BD0200080F
+S309080064B8990200082F
+S315080064BC0090D0030090D0030100000010000000EB
+S315080064CC04000000B55D00089D5D00083D5D0008F0
+S315080064DC0000000000000000255D00082F5D000884
+S315080064EC115D00080000000000000000000000001C
+S315080064FCF95C000800000000055D00080902200090
+S3150800650C010100C0320904000002FF000000070563
+S3150800651C81024000FF070501024000FF0A0600023F
+S3150800652C0000004001000000ED5D0008F95D000860
+S3150800653CA95E0008855E0008715E0008C55E000845
+S3150800654CE95E00081201000200000040501DAC6014
+S3150800655C0002010203010000040309041A030000E7
+S3150800656C0000000000000000000000000000000011
+S30D0800657C000000000000000009
 S7050800098564
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_CubeIDE/Prog/App/boot.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_CubeIDE/Prog/App/boot.c
index c4c17b9d..9c07f926 100644
--- a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_CubeIDE/Prog/App/boot.c
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_CubeIDE/Prog/App/boot.c
@@ -376,12 +376,12 @@ static void BootComCanInit(void)
     canHandle.Init.StdFiltersNbr = 0;
     canHandle.Init.ExtFiltersNbr = 1;
   }
-  /* only one reception buffer is needed. reception FIFO 0 and 1 are not used. */
-  canHandle.Init.RxFifo0ElmtsNbr = 0;
+  /* only reception FIFO 0 is used. */
+  canHandle.Init.RxFifo0ElmtsNbr = 1;
   canHandle.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_8;
   canHandle.Init.RxFifo1ElmtsNbr = 0;
   canHandle.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_8;
-  canHandle.Init.RxBuffersNbr = 1;
+  canHandle.Init.RxBuffersNbr = 0;
   canHandle.Init.RxBufferSize = FDCAN_DATA_BYTES_8;
   /* no transmit buffer is needed. transmit FIFO is not used. */
   canHandle.Init.TxEventsNbr = 0;
@@ -411,12 +411,16 @@ static void BootComCanInit(void)
   }
   filterConfig.FilterIndex = 0;
   filterConfig.FilterType = FDCAN_FILTER_DUAL;
-  filterConfig.FilterConfig = FDCAN_FILTER_TO_RXBUFFER;
+  filterConfig.FilterConfig = FDCAN_FILTER_TO_RXFIFO0;
   filterConfig.FilterID1 = rxMsgId;
   filterConfig.FilterID2 = rxMsgId;
   filterConfig.RxBufferIndex = 0;
   (void)HAL_FDCAN_ConfigFilter(&canHandle, &filterConfig);
 
+  /* configure global filter to reject all non-matching frames. */
+  HAL_FDCAN_ConfigGlobalFilter(&canHandle, FDCAN_REJECT, FDCAN_REJECT, 
+                               FDCAN_REJECT_REMOTE, FDCAN_REJECT_REMOTE);
+  
   /* start the CAN peripheral. no need to evaluate the return value as there is nothing
    * we can do about a faulty CAN controller. */
   (void)HAL_FDCAN_Start(&canHandle);
@@ -440,10 +444,10 @@ static void BootComCanCheckActivationRequest(void)
 
 
   /* poll for received CAN messages that await processing. */
-  if (HAL_FDCAN_IsRxBufferMessageAvailable(&canHandle, FDCAN_RX_BUFFER0) > 0)
+  if (HAL_FDCAN_GetRxFifoFillLevel(&canHandle, FDCAN_RX_FIFO0) > 0)
   {
     /* attempt to read the newly received CAN message from its buffer. */
-    rxStatus = HAL_FDCAN_GetRxMessage(&canHandle, FDCAN_RX_BUFFER0, &rxMsgHeader,
+    rxStatus = HAL_FDCAN_GetRxMessage(&canHandle, FDCAN_RX_FIFO0, &rxMsgHeader,
                                       rxMsgData);
   }
 
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_CubeIDE/Prog/Debug/demoprog_stm32h743.elf b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_CubeIDE/Prog/Debug/demoprog_stm32h743.elf
index be15e841..b96dc245 100644
Binary files a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_CubeIDE/Prog/Debug/demoprog_stm32h743.elf and b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_CubeIDE/Prog/Debug/demoprog_stm32h743.elf differ
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_CubeIDE/Prog/Debug/demoprog_stm32h743.srec b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_CubeIDE/Prog/Debug/demoprog_stm32h743.srec
index f8bfca73..d15e0669 100644
--- a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_CubeIDE/Prog/Debug/demoprog_stm32h743.srec
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_CubeIDE/Prog/Debug/demoprog_stm32h743.srec
@@ -1,50 +1,50 @@
 S01A000064656D6F70726F675F73746D3332683734332E737265638F
-S3150802000000000824490C02085D0B02085F0B02086F
-S31508020010610B0208630B0208650B02080000000068
-S31508020020000000000000000000000000670B020844
-S31508020030690B0208000000006B0B02086D0B020830
-S31508020040990C0208990C0208990C0208990C0208E4
-S31508020050990C0208990C0208990C0208990C0208D4
-S31508020060990C0208990C0208990C0208990C0208C4
-S31508020070990C0208990C0208990C0208990C0208B4
-S31508020080990C0208990C0208990C0208990C0208A4
-S31508020090990C0208990C0208990C0208990C020894
-S315080200A0990C0208990C0208990C0208990C020884
-S315080200B0990C0208990C0208990C0208990C020874
-S315080200C0990C0208990C0208990C0208990C020864
-S315080200D0990C0208990C0208990C0208990C020854
-S315080200E0990C0208990C020800000000990C0208F3
-S315080200F0990C0208990C0208990C0208990C020834
-S31508020100990C0208990C0208990C0208990C020823
-S31508020110990C0208990C0208990C0208990C020813
-S31508020120990C0208990C0208990C0208990C020803
-S31508020130990C0208990C0208990C0208990C0208F3
+S3150802000000000824550C0208690B02086B0B02084B
+S315080200106D0B02086F0B0208710B02080000000044
+S31508020020000000000000000000000000730B020838
+S31508020030750B020800000000770B0208790B02080C
+S31508020040A50C0208A50C0208A50C0208A50C0208B4
+S31508020050A50C0208A50C0208A50C0208A50C0208A4
+S31508020060A50C0208A50C0208A50C0208A50C020894
+S31508020070A50C0208A50C0208A50C0208A50C020884
+S31508020080A50C0208A50C0208A50C0208A50C020874
+S31508020090A50C0208A50C0208A50C0208A50C020864
+S315080200A0A50C0208A50C0208A50C0208A50C020854
+S315080200B0A50C0208A50C0208A50C0208A50C020844
+S315080200C0A50C0208A50C0208A50C0208A50C020834
+S315080200D0A50C0208A50C0208A50C0208A50C020824
+S315080200E0A50C0208A50C020800000000A50C0208CF
+S315080200F0A50C0208A50C0208A50C0208A50C020804
+S31508020100A50C0208A50C0208A50C0208A50C0208F3
+S31508020110A50C0208A50C0208A50C0208A50C0208E3
+S31508020120A50C0208A50C0208A50C0208A50C0208D3
+S31508020130A50C0208A50C0208A50C0208A50C0208C3
 S31508020140000000000000000000000000000000009F
-S31508020150990C0208990C0208990C0208990C0208D3
-S31508020160990C0208990C0208990C0208990C0208C3
-S31508020170990C0208990C0208990C02080000000062
-S31508020180990C0208990C0208990C0208990C0208A3
-S31508020190990C0208990C0208990C0208990C020893
-S315080201A0990C0208990C0208990C0208990C020883
-S315080201B0990C0208990C0208990C0208990C020873
-S315080201C0990C0208990C0208990C0208990C020863
-S315080201D0990C0208990C0208990C0208990C020853
-S315080201E0990C0208990C0208990C0208990C020843
-S315080201F0990C0208990C0208990C0208990C020833
-S31508020200990C0208990C0208990C0208990C020822
-S31508020210990C0208990C0208990C0208990C020812
-S31508020220990C0208990C0208990C020800000000B1
-S31508020230990C0208990C020800000000990C0208A1
-S31508020240990C0208990C0208990C0208990C0208E2
-S31508020250990C0208990C0208990C0208990C0208D2
-S31508020260990C0208990C0208990C0208990C0208C2
-S31508020270990C0208990C0208990C02080000000061
-S31508020280990C0208990C0208990C02080000000051
-S3110802029000000000990C0208EE11AA55A5
+S31508020150A50C0208A50C0208A50C0208A50C0208A3
+S31508020160A50C0208A50C0208A50C0208A50C020893
+S31508020170A50C0208A50C0208A50C0208000000003E
+S31508020180A50C0208A50C0208A50C0208A50C020873
+S31508020190A50C0208A50C0208A50C0208A50C020863
+S315080201A0A50C0208A50C0208A50C0208A50C020853
+S315080201B0A50C0208A50C0208A50C0208A50C020843
+S315080201C0A50C0208A50C0208A50C0208A50C020833
+S315080201D0A50C0208A50C0208A50C0208A50C020823
+S315080201E0A50C0208A50C0208A50C0208A50C020813
+S315080201F0A50C0208A50C0208A50C0208A50C020803
+S31508020200A50C0208A50C0208A50C0208A50C0208F2
+S31508020210A50C0208A50C0208A50C0208A50C0208E2
+S31508020220A50C0208A50C0208A50C0208000000008D
+S31508020230A50C0208A50C020800000000A50C02087D
+S31508020240A50C0208A50C0208A50C0208A50C0208B2
+S31508020250A50C0208A50C0208A50C0208A50C0208A2
+S31508020260A50C0208A50C0208A50C0208A50C020892
+S31508020270A50C0208A50C0208A50C0208000000003D
+S31508020280A50C0208A50C0208A50C0208000000002D
+S3110802029000000000A50C0208EE11AA5599
 S3150802029C10B5054C237833B9044B13B10448AFF3A4
 S315080202AC00800123237010BD1000002400000000FA
-S315080202BC643C020808B5034B1BB103490348AFF368
-S315080202CC008008BD0000000014000024643C0208EB
+S315080202BC743C020808B5034B1BB103490348AFF358
+S315080202CC008008BD0000000014000024743C0208DB
 S315080202DC53B94AB9002908BF00281CBF4FF0FF3191
 S315080202EC4FF0FF3000F072B9ADF1080C6DE904CE8F
 S315080202FC00F006F8DDF804E0DDE9022304B07047E5
@@ -93,893 +93,894 @@ S3150802059C1846FBE64145ABD2B8EB020A69EB0E02EA
 S315080205AC01381346A4E76046E9E7184695E7674615
 S315080205BCD1E781467CE702382C4447E7ACF1020CBA
 S315080205CC2B442FE7384608E73746E9E6704700BF5B
-S315080205DC08B500F071F900F03FF900F0ADF808BD66
-S315080205EC08B500F043F900F031F908BDF0B400245F
+S315080205DC08B500F077F900F045F900F0B3F808BD54
+S315080205EC08B500F049F900F037F908BDF0B4002453
 S315080205FC01E00134E4B2112C20D8124D15F814700E
 S3150802060C05EB440595F801C007EB0C0606FB00063C
 S3150802061C4FF4FA55B5FBF6F506FB05F5B5F5FA5F93
 S3150802062CE7D1B5FBF6F60E80013EB6B2B6F5007FFB
 S3150802063CDFD2177083F800C0012000E00020F0BC5E
-S3150802064C704700BFC83C020808B50948094B036045
+S3150802064C704700BFD83C020808B50948094B036035
 S3150802065C4FF46143436000238360C36003610C2239
-S3150802066C42618361C3610362836203F08AFA08BD3D
-S3150802067CCC0000240048004070B58AB00025ADF8BD
-S3150802068C26508DF825500AAB03F8045D0DF12502A8
-S3150802069C0DF126014FF4FA70FFF7A8FF1D4C1E4BFD
+S3150802066C42618361C3610362836203F092FA08BD35
+S3150802067CCC0000240048004070B58CB00025ADF8BB
+S3150802068C2E508DF82D500CAB03F8045D0DF12D028E
+S3150802069C0DF12E014FF4FA70FFF7A8FF204C214BEF
 S315080206AC2360A560E560012626746574A574BDF8F9
-S315080206BC26306361A6619DF82530E3619DF82430E6
+S315080206BC2E306361A6619DF82D30E3619DF82C30CE
 S315080206CC23626662A662E66226636563A663E563CF
-S315080206DC256404236364A564E36426656365A565DA
-S315080206ECE56525666566A366204600F083FC0195DA
-S315080206FC029503960723049340F2676305930693C0
-S3150802070C079501A9204600F0BFFD204600F0FFFD23
-S3150802071C0AB070BD2C00002400A0004008B50023C6
-S3150802072C01220146034803F05DF908B1002008BD11
-S3150802073C0120FCE7CC00002408B5FFF785FFFFF77C
-S3150802074C9BFF08BDBFF34F8F0549CA6802F4E062E6
-S3150802075C044B1343CB60BFF34F8F00BFFDE700BFBB
-S3150802076C00ED00E00400FA0508B5214B1B78B3B975
-S3150802077C2048FFF7D3FF012800D008BD1D4B1B7874
-S3150802078C013BDBB23F2BF8D800F097F81A4B1860EE
-S3150802079C174B01221A70194B00221A70EDE7174BE8
-S315080207AC1B78013313481844FFF7B8FF012813D1F5
-S315080207BC124A13780133DBB213700E4A127893423B
-S315080207CCDBD10B4A002111700A4A5278FF2AD4D17E
-S315080207DC022BD2D1FFF7B6FF00F06FF8064B1B6857
-S315080207EC64339842C9D9024B00221A70C5E700BF76
-S315080207FC99010024580100249C0100249A01002422
-S3150802080C00B58DB00021104800F07AFE10B90DB073
-S3150802081C5DF804FB6B4602AA00210B4800F092FD18
-S3150802082C0028F4D1029A40F267639A42EFD1039BED
-S3150802083C002BECD19DF816209DF80030FF2BE6D143
-S3150802084C022AE4D1FFF77EFF2C00002408B5FFF735
-S3150802085C8BFFFFF7D5FF08BD08B500228021024899
-S3150802086C00F066FF08BD00BF0004025810B500F080
-S3150802087C24F80E4B1B68C31AB3F5FA7F0CD304463D
-S3150802088C0B4B1B784BB90122094B1A70802109486C
-S3150802089C00F04EFF054B1C6010BD0022044B1A706B
-S315080208AC8021044800F044FFF4E700BFA4010024A9
-S315080208BCA001002400040258704708B500F04AFA51
-S315080208CC08BD0000014A024B9A60704700000208F4
-S315080208DC00ED00E030B589B0002403940494059425
-S315080208EC069407941B4BD3F8E02042F08002C3F817
-S315080208FCE020D3F8E02002F080020092009AD3F8A6
-S3150802090CE02042F00802C3F8E020D3F8E02002F017
-S3150802091C08020192019AD3F8E02042F00202C3F8C7
-S3150802092CE020D3F8E03003F002030293029B0A4D4F
-S3150802093C22468021284600F0FBFE802303930123DE
-S3150802094C04930594069403A9284600F001FE09B0FF
-S3150802095C30BD00BF004402580004025830B5CDB071
-S3150802096C4C22002139A803F06EF92022002131A865
-S3150802097C03F069F9BC22002102A803F064F90220EB
-S3150802098C00F0DCFE00230193254B9A6942F440429F
-S3150802099C9A619B6903F440430193224BDA6A42F04B
-S315080209AC0102DA62DB6A03F001030193019B1C4B19
-S315080209BC9B6913F4005FFAD0012339934FF4A023F1
-S315080209CC3A93022342934393042544954FF4F072C7
-S315080209DC4592469347954893499500244A944B94D5
-S315080209EC39A800F0D5FE3F2331930323329333946F
-S315080209FC082334934023359336934FF48062379207
-S31508020A0C3893294631A801F0DDFA48F2020302931B
-S31508020A1C1D941F9402A801F071FD4DB030BD00BFA4
-S31508020A2C004802580004005808B5FFF74BFF00F0BF
-S31508020A3C57F9FFF793FFFFF74DFFFFF7C9FDFFF7CE
-S31508020A4CCFFDFCE782B0074BD3F8F42042F0020242
-S31508020A5CC3F8F420D3F8F43003F002030193019B94
-S31508020A6C02B070470044025800B589B000230393BC
-S31508020A7C04930593069307930268154B9A4202D080
-S31508020A8C09B05DF804FB134BD3F8EC2042F48072E0
-S31508020A9CC3F8EC20D3F8EC2002F480720192019A86
-S31508020AACD3F8E02042F00202C3F8E020D3F8E03093
-S31508020ABC03F002030293029B4FF44073039302233F
-S31508020ACC04930923079303A9034800F041FDD7E7CA
-S31508020ADC00A00040004402580004025800B589B030
-S31508020AEC0023039304930593069307930268154B05
-S31508020AFC9A4202D009B05DF804FB134BD3F8E820EE
-S31508020B0C42F48022C3F8E820D3F8E82002F48022C3
-S31508020B1C0192019AD3F8E02042F00802C3F8E020C9
-S31508020B2CD3F8E03003F008030293029B4FF44073A8
-S31508020B3C0393022304930723079303A9034800F09C
-S31508020B4C07FDD7E70048004000440258000C02583B
-S31508020B5C7047FEE7FEE7FEE7FEE770477047704709
-S31508020B6C08B500F0EBF808BD294AD2F8883043F4E8
-S31508020B7C7003C2F88830274B1B6803F00F03062B49
-S31508020B8C06D8244A136823F00F0343F007031360AD
-S31508020B9C214B1A6842F001021A6000221A6119687E
-S31508020BAC1E4A0A401A601B4B1B6803F00F03072BDD
-S31508020BBC06D9184A136823F00F0343F00703136088
-S31508020BCC154B00229A61DA611A621549996215491E
-S31508020BDCD962154919635A639963DA6319645A64B3
-S31508020BEC196821F4802119601A66104B1A68104B81
-S31508020BFC1340B3F1005F02D20E4B01221A600E4B60
-S31508020C0C43F2D2021A60024B4FF000629A607047A6
-S31508020C1C00ED00E000200052004402587FEDF6EA8F
-S31508020C2C000202020000FF01800201010010005CB2
-S31508020C3C0000FFFF0881005100400052DFF834D053
-S31508020C4CFFF792FF002103E00B4B5B58435004312C
-S31508020C5C0A480B4B42189A42F6D30A4A02E0002378
-S31508020C6C42F8043B084B9A42F9D302F0BDFFFFF750
-S31508020C7CDBFE704700000824343D020800000024FD
-S31508020C8C1000002410000024AC010024FEE700002A
-S31508020C9C104B1B780BB90120704710B504464FF45C
-S31508020CAC7A70B0FBF3F30C4A1068B0FBF3F000F061
-S31508020CBCA1F868B90F2C01D901200AE000222146B5
-S31508020CCC4FF0FF3000F064F8044B1C60002000E083
-S31508020CDC012010BD08000024000000240C0000248A
-S31508020CEC10B5032000F042F801F076F80F498B692B
-S31508020CFCC3F303230E4AD35C03F01F03D8408B6954
-S31508020D0C03F00F03D35C03F01F0320FA03F3094A1B
-S31508020D1C1360094B18600020FFF7BAFF10B10124C3
-S31508020D2C204610BD0446FFF78DFEF9E7004402582B
-S31508020D3CEC3C02080400002400000024034B1B7838
-S31508020D4C034A11680B441360704700BF080000245D
-S31508020D5CA8010024014B1868704700BFA80100249B
-S31508020D6C014B1868000C70470010005C0649CB68EA
-S31508020D7C23F4E0631B041B0C000200F4E06003433B
-S31508020D8C024A1A43CA60704700ED00E00000FA05F1
-S31508020D9C30B4154BDB68C3F30223C3F10704042CE6
-S31508020DAC28BF04241D1D062D14D9033B4FF0FF350D
-S31508020DBC05FA04F421EA0401994005FA03F322EA36
-S31508020DCC03031943002807DB0901C9B2074B195457
-S31508020DDC30BC70470023E9E700F00F000901C9B2DD
-S31508020DEC034B1954F4E700BF00ED00E000E400E001
-S31508020DFC14ED00E00138B0F1807F0AD2064B586038
-S31508020E0C064AF02182F823100020986007221A60FD
-S31508020E1C70470120704700BF10E000E000ED00E0CB
-S31508020E2C30B4446B0268D2F884106F4B194041EA0D
-S31508020E3C8401C2F884100268D2F8841021F47F0166
-S31508020E4C856B41EA0541C2F88410826B2244046818
-S31508020E5CD4F88810194041EA8201C4F8881004684B
-S31508020E6CD4F8881021F4FE01C56B41EA0541C4F891
-S31508020E7C8810C16B02EB41020468D4F8A010194021
-S31508020E8C41EA8201C4F8A0100468D4F8A01021F42F
-S31508020E9CFE01056C41EA0541C4F8A010046C416CCC
-S31508020EAC01FB04240268D2F8B010194041EA840105
-S31508020EBCC2F8B0100268D2F8B01021F4FE01856CA3
-S31508020ECC41EA0541C2F8B010826CC16C01FB0244BE
-S31508020EDC0268D2F8AC10194041EA8401C2F8AC1087
-S31508020EEC026D416D01FB02420468D4F8F0101940F8
-S31508020EFC41EA8201C4F8F0100468D4F8F01021F41F
-S31508020F0C7C11856D41EA0541C4F8F010816D02EB3E
-S31508020F1C41020468D4F8C0100B4043EA8202C4F8B2
-S31508020F2CC0200268D2F8C03023F47C13C16D43EAA0
-S31508020F3C0143C2F8C0300268D2F8C03023F07C53A1
-S31508020F4C016E43EA0163C2F8C030436B274A1A445E
-S31508020F5C9200C266836B02EB83030367C16B03EBD6
-S31508020F6CC1034367046C416C01FB04F103EB810377
-S31508020F7C8367846CC16C01FB04F103EB8103C367C1
-S31508020F8C046D416D01FB04F103EB8103C0F880305B
-S31508020F9C816D03EBC103C0F88430C46D856E05FB05
-S31508020FAC04F403EB8403C0F88830016E01FB05F1E7
-S31508020FBC03EB8103C0F890300D498B420DD9D0F85A
-S31508020FCC9C3043F02003C0F89C30032380F89830F9
-S31508020FDC012007E0002342F8043BD0F890309342F4
-S31508020FECF8D8002030BC70470300FFFF002B001016
-S31508020FFCFCD3004030B595B004464C22A04901A852
-S3150802100C02F016FE002C00F0388123689D4A9342A2
-S3150802101C20D094F898300BB32268936923F0100306
-S3150802102C9361FFF797FE054623689A6912F0080F33
-S3150802103C1AD0FFF78FFE401B0A28F5D9D4F89C3034
-S3150802104C43F00103C4F89C30032384F8983001203A
-S3150802105C15B030BD03F580736360DAE784F899300E
-S3150802106C2046FFF701FDD7E79A6942F001029A6119
-S3150802107CFFF770FE054623689A6912F0010F0FD125
-S3150802108CFFF768FE401B0A28F5D9D4F89C3043F0C2
-S3150802109C0103C4F89C30032384F898300120D7E75F
-S315080210AC9A6942F002029A61237C012B40D022688B
-S315080210BC936943F040039361637C012B3ED022680B
-S315080210CC936923F480439361A37C012B3CD0226859
-S315080210DC936943F4805393612268936923F44073AA
-S315080210ECA1680B4393612268936923F0A403936165
-S315080210FC2268136923F010031361E368012B29D0C4
-S3150802110C002B2CD0022B00F09B802268936943F0AB
-S3150802111C800393612268136943F010031361E36831
-S3150802112C032B1CD12268936943F02003936116E0C2
-S3150802113C2268936923F040039361BDE72268936999
-S3150802114C43F480439361BFE72268936923F480537F
-S3150802115C9361C1E72268936943F004039361A36917
-S3150802116C5A1EE369013B1B0243EA4263226A013AAD
-S3150802117C13436269013A216843EA0243CB61A368C5
-S3150802118CB3F5407F62D0236E33B12268D2F8C030F1
-S3150802119C616E0B43C2F8C030E36D226ED3420DD09A
-S315080211AC2168D1F8C83023F00703A26E14A800EB05
-S315080211BC820252F84C2C1343C1F8C830236C6BB11B
-S315080211CC2168D1F8BC3023F00703626C14A800EB33
-S315080211DC820252F84C2C1343C1F8BC30A36C73B17F
-S315080211EC2168D1F8BC3023F07003E26C14A800EB2A
-S315080211FC820252F84C2C43EA0213C1F8BC30236D16
-S3150802120C73B12168D1F8BC3023F4E063626D14A87B
-S3150802121C00EB820252F84C2C43EA0223C1F8BC308A
-S3150802122C2268184B9A4222D00023C4F89430C4F888
-S3150802123C9C30012384F898302046FFF7F1FD07E726
-S3150802124C2268936943F02003936188E7A36A013BFA
-S3150802125CE26A013A43EA0223226B013A43EA02138F
-S3150802126C626A013A216843EA0243CB608BE76268F9
-S3150802127C936823F003039360D6E70120E8E600BFE0
-S3150802128C7C3C020800A0004090F89830013BDBB287
-S3150802129C012B07D9D0F89C3043F00203C0F89C30D6
-S315080212AC01207047CB680A68D2B9072B0ED08A6818
-S315080212BCDB0643EA82730A6943EA02434A69134321
-S315080212CCC26E496842F82130002070470A69CB6918
-S315080212DC1B0243EA02438A69134343F06053EFE75E
-S315080212EC10B40A6942EA4372072B0ED08C684B6912
-S315080212FC43EA8473006F496800EBC10440F8312055
-S3150802130C636000205DF8044B70478B69F2E790F82E
-S3150802131C9830DBB2012B07D0D0F89C3043F004038B
-S3150802132CC0F89C3001207047022380F89830026876
-S3150802133C936923F0010393610023C0F89C30184685
-S3150802134C70470000F0B490F89840E4B2022C08D02A
-S3150802135CD0F89C3043F00803C0F89C300120F0BC4E
-S3150802136C7047402939D0412964D0046D8C4240F229
-S3150802137C8E80C46F456D01FB05F504EB85044FF0B1
-S3150802138C000C256805F080455560002D40F08780D5
-S3150802139C2568C5F38A451560256805F000559560DC
-S315080213AC256805F000451561A588D561656805F4BB
-S315080213BC7025D560656805F480155561656805F470
-S315080213CC00159561E57905F07F0515626568ED0FDF
-S315080213DC556204F10805002469E00468D4F8A050A3
-S315080213EC15F4FE0F16D0D4F8A45015F07F0F19D0A9
-S315080213FCD4F8A45015F0807F01D0D4F8A050D4F8B4
-S3150802140CA440C4F3052C446F456C0CFB05F504EBA0
-S3150802141C8504B6E7D0F89C3043F02003C0F89C301C
-S3150802142C01209CE7D0F89C3043F48073C0F89C30BA
-S3150802143C012094E70468D4F8B05015F4FE0F16D0C0
-S3150802144CD4F8B45015F07F0F19D0D4F8B45015F05F
-S3150802145C807F01D0D4F8B050D4F8B440C4F3052C2C
-S3150802146C846FC56C0CFB05F504EB850489E7D0F88B
-S3150802147C9C3043F02003C0F89C3001206FE7D0F86B
-S3150802148C9C3043F48073C0F89C30012067E7D0F88F
-S3150802149C9C3043F02003C0F89C3001205FE7256896
-S315080214AC25F06045156077E72E5D1E550134D68901
-S315080214BC124FBE5DA642F7D840290BD041290ED051
-S315080214CC1F2911D80268012303FA01F1C2F89810F0
-S315080214DC002044E70368C3F8A8C000203FE7036866
-S315080214ECC3F8B8C000203AE701F01F0102680123CD
-S315080214FC03FA01F1C2F89C10002030E7FC3C020802
-S3150802150C0368D3F89820D3F89C001F2903D8CA403D
-S3150802151C12F0010F17D01F2905D901F01F02D0406E
-S3150802152C10F0010F11D01F2907D901F01F01012054
-S3150802153C00FA01F1C3F89C107047012000FA01F178
-S3150802154CC3F89810704700207047002070470000B7
-S3150802155CF0B583B000233AE0092400E00024B44035
-S3150802156C3C4302356E4E46F825406E4C2568D443EC
-S3150802157C04EA05064F6817F4803F01D042EA0506CD
-S3150802158C684D2E606E6804EA06054F6817F4003F2C
-S3150802159C01D042EA0605634E75604FF0B0452D68D8
-S315080215AC04EA05064F6817F4801F01D042EA0506BD
-S315080215BC4FF0B0452E606D682C404E6816F4001F2D
-S315080215CC01D042EA05044FF0B042546001330A686E
-S315080215DC32FA03F400F0A28001249C402240F5D092
-S315080215EC4D686E1E112D18BF012E01D9122D12D15E
-S315080215FC86685F000325BD4026EA0506CD68BD4010
-S3150802160C35438560466826EA04064D68C5F3001418
-S3150802161C9C4034434460C6685F000325BD40EC43D6
-S3150802162C26408D68BD403543C5604D68122D18BFDE
-S3150802163C022D13D1DE08083650F826E003F007050A
-S3150802164C4FEA850C0F2505FA0CF52EEA050E0D69DF
-S3150802165C05FA0CF545EA0E0540F8265005682540AC
-S3150802166C4C6804F00304BC402C4304604C6814F028
-S3150802167C805FABD02C4CD4F8F45045F00205C4F874
-S3150802168CF450D4F8F44004F002040194019C9D0829
-S3150802169CAE1C234C54F8267003F00304A6000F2440
-S315080216ACB44027EA0407214CA0423FF457AF04F58D
-S315080216BC8064A04222D004F58064A04220D004F5AE
-S315080216CC8064A0421ED004F58064A0421CD004F5A6
-S315080216DC8064A0421AD004F58064A04218D004F59E
-S315080216EC8064A04216D004F58064A04214D004F596
-S315080216FC8064A0423FF430AF0A2430E701242EE777
-S3150802170C02242CE703242AE7042428E7052426E7DF
-S3150802171C062424E7072422E7082420E703B0F0BDB1
-S3150802172C0004005880000058004402580000025871
-S3150802173C12B909048161704781617047134BDB68E2
-S3150802174C13F0040F07D1114BDB6803F0070383422E
-S3150802175C1AD00120704710B50C4AD36823F0070338
-S3150802176C1843D060FFF7F6FA0446084B5B6813F485
-S3150802177C005F07D1FFF7EEFA001BB0F57A7FF4D9B2
-S3150802178C012000E0002010BD0020704700480258D6
-S3150802179C002800F00C8338B50446036813F0010FD1
-S315080217AC25D09D4A136903F03803926A102B15D07B
-S315080217BC182B0FD06368B3F5803F3FD0002B53D15B
-S315080217CC954B1A6822F480321A601A6822F480221F
-S315080217DC1A6038E002F00302022AEBD18E4B1B6820
-S315080217EC13F4003F03D06368002B00F0E2822368EF
-S315080217FC13F0020F00F08B80874A1369926A13F072
-S3150802180C38035AD0182B55D0E368002B00F0C88041
-S3150802181C81490A6822F0190213430B60FFF79AFAF8
-S3150802182C05467D4B1B6813F0040F40F09780FFF7B3
-S3150802183C91FA401B0228F4D90320BFE2764A1368B0
-S3150802184C43F48033136063682BB3FFF783FA0546B8
-S3150802185C714B1B6813F4003FC9D1FFF77BFA401B87
-S3150802186C6428F5D90320A9E2B3F5A02F09D06A4B4F
-S3150802187C1A6822F480321A601A6822F480221A60D4
-S3150802188CE1E7654B1A6842F480221A601A6842F438
-S3150802189C80321A60D7E7FFF75DFA05465E4B1B687E
-S315080218AC13F4003FA3D0FFF755FA401B6428F5D969
-S315080218BC032083E212F0030FA6D1574B1B6813F0D1
-S315080218CC040F03D0E368002B00F07582FFF748FA81
-S315080218DC41F20303984212D82269402A07D04E498C
-S315080218EC4B6823F47C3343EA02334B600FE04A4AD3
-S315080218FC536823F47C3343F40033536007E0464AB7
-S3150802190C536823F0FE43216943EA01635360236853
-S3150802191C13F0100F00F08A803F4A136903F038035C
-S3150802192C926A082B54D0182B4ED0E369002B00F080
-S3150802193CBA80394A136843F080031360FFF70AFA30
-S3150802194C0546354B1B6813F4807F40F08A80FFF7F7
-S3150802195C01FA401B0228F4D903202FE2FFF700FAFA
-S3150802196C41F20303984212D82269402A07D02A491F
-S3150802197C4B6823F47C3343EA02334B60C7E7264AA7
-S3150802198C536823F47C3343F400335360BFE7224A8B
-S3150802199C536823F0FE43216943EA01635360B6E7B1
-S315080219AC1D4A136823F001031360FFF7D3F90546A2
-S315080219BC194B1B6813F0040FA9D0FFF7CBF9401B80
-S315080219CC0228F5D90320F9E102F00302012AACD167
-S315080219DC114B1B6813F4807F04D0E369802B01D06A
-S315080219EC0120EBE1FFF7BCF941F20303984215D843
-S315080219FC226A202A07D008494B6823F0F84343EA9F
-S31508021A0C82634B6012E0044A536823F0F84343F0AE
-S31508021A1C804353600AE000BF004402589A4AD368CE
-S31508021A2C23F07C53216A43EA0163D360236813F0DB
-S31508021A3C080F60D06369002B49D0934A536F43F061
-S31508021A4C01035367FFF786F905468F4B5B6F13F055
-S31508021A5C020F50D1FFF77EF9401B0228F5D9032055
-S31508021A6CACE1FFF77DF941F20303984212D8226AD8
-S31508021A7C202A07D084494B6823F0F84343EA826349
-S31508021A8C4B60D3E7804A536823F0F84343F080430C
-S31508021A9C5360CBE77C4AD36823F07C53216A43EA2A
-S31508021AAC0163D360C2E7784A136823F08003136094
-S31508021ABCFFF750F90546744B1B6813F4807FB5D0B3
-S31508021ACCFFF748F9401B0228F5D9032076E16E4A3E
-S31508021ADC536F23F001035367FFF73CF905466A4B2C
-S31508021AEC5B6F13F0020F06D0FFF734F9401B02287E
-S31508021AFCF5D9032062E1236813F0200F29D0A369D4
-S31508021B0C9BB1614A136843F480531360FFF722F9B9
-S31508021B1C05465D4B1B6813F4005F1AD1FFF71AF9D9
-S31508021B2C401B0228F5D9032048E1574A136823F4C7
-S31508021B3C80531360FFF70EF90546534B1B6813F4D3
-S31508021B4C005F06D0FFF706F9401B0228F5D90320D9
-S31508021B5C34E1236813F0040F21D1636A002B00F0D9
-S31508021B6C2C81494A126902F03802182A00F0EE80D2
-S31508021B7C022B75D0444A136823F080731360FFF75F
-S31508021B8CE9F80446404B1B6813F0007F00F0DC8032
-S31508021B9CFFF7E0F8001B0228F4D903200EE13B4AB2
-S31508021BAC136843F480731360FFF7D4F80546374B72
-S31508021BBC1B6813F4807F06D1FFF7CCF8401B642808
-S31508021BCCF5D90320FAE0A368012B0AD00BBB2E4BDE
-S31508021BDC1A6F22F001021A671A6F22F004021A67A8
-S31508021BEC04E0294A136F43F001031367A36833B35E
-S31508021BFCFFF7B0F80546244B1B6F13F0020FACD156
-S31508021C0CFFF7A8F8401B41F288339842F3D9032010
-S31508021C1CD4E0052B09D01C4B1A6F22F001021A6765
-S31508021C2C1A6F22F004021A67E0E7174B1A6F42F092
-S31508021C3C04021A671A6F42F001021A67D6E7FFF70F
-S31508021C4C89F80546104B1B6F13F0020F85D0FFF768
-S31508021C5C81F8401B41F288339842F3D90320ADE050
-S31508021C6C094A136823F080731360FFF773F8054665
-S31508021C7C054B1B6813F0007F0AD0FFF76BF8401B65
-S31508021C8C0228F5D9032099E0004402580048025864
-S31508021C9C4E4B996A4E4A0A40A16AE06A41EA001119
-S31508021CAC0A439A62226B013AC2F30802616B013942
-S31508021CBC490289B20A43A16B0139090401F4FE01EE
-S31508021CCC0A43E16B0139090601F0FE410A431A631C
-S31508021CDCDA6A22F00102DA62596B3E4A0A40A16CB0
-S31508021CEC42EAC1025A63DA6A22F00C02216C0A43EE
-S31508021CFCDA62DA6A22F00202616C0A43DA62DA6A98
-S31508021D0C42F48032DA62DA6A42F40032DA62DA6A67
-S31508021D1C42F48022DA62DA6A42F00102DA621A685C
-S31508021D2C42F080721A60FFF715F80446274B1B68B7
-S31508021D3C13F0007F06D1FFF70DF8001B0228F5D920
-S31508021D4C03203BE0002039E0002037E01F4A916A65
-S31508021D5C106B012B33D001F00303A26A934201D014
-S31508021D6C01202BE0C1F30511E36A994201D0012047
-S31508021D7C24E0C0F30802236B013B9A4201D00120EE
-S31508021D8C1CE0C0F34622636B013B9A4201D0012048
-S31508021D9C14E0C0F30642A36B013B9A4211D1C0F37D
-S31508021DAC0660E36B013B98420DD0012006E0012048
-S31508021DBC7047012002E0012000E0002038BD012016
-S31508021DCCFCE70120FAE70020F8E700BF00440258B6
-S31508021DDC0CFCFFFF0700FFFF724B1B6903F038036D
-S31508021DEC102B00F0DB80182B10D00BB16E48704705
-S31508021DFC6C4B1B6813F0200F00F0D280694B1868E5
-S31508021E0CC0F3C100694B23FA00F07047654A916A20
-S31508021E1C01F00301906AC0F30510D36A03F00103BB
-S31508021E2C526BC2F3CC0203FB02F307EE903AF8EEBE
-S31508021E3C677A002800F0B580012966D0F9B1022923
-S31508021E4C00F08F8007EE100AF8EE476A9FED586A83
-S31508021E5C86EE267A534B1B6BC3F3080306EE903AAF
-S31508021E6CF8EE666A9FED536A67EE867A76EEA77A7D
-S31508021E7CF7EE006A77EEA67A27EE277A61E0494BE7
-S31508021E8C1B6813F0200F23D046490A68C2F3C10215
-S31508021E9C464BD34007EE103AF8EE476A07EE100A9D
-S31508021EACB8EE476A86EE867A0B6BC3F3080306EE20
-S31508021EBC903AF8EE666A9FED3F6A67EE867A76EE98
-S31508021ECCA77AF7EE006A77EEA67A27EE277A38E033
-S31508021EDC07EE100AF8EE476A9FED376A86EE267AFF
-S31508021EEC304B1B6BC3F3080306EE903AF8EE666AA0
-S31508021EFC9FED306A67EE867A76EEA77AF7EE006A77
-S31508021F0C77EEA67A27EE277A1BE007EE100AF8EE8A
-S31508021F1C476A9FED276A86EE267A224B1B6BC3F31A
-S31508021F2C080306EE903AF8EE666A9FED226A67EEA9
-S31508021F3C867A76EEA77AF7EE006A77EEA67A27EE17
-S31508021F4C277A184B1B6BC3F34623013307EE903AD9
-S31508021F5CF8EE677AC7EE276AFCEEE67A17EE900A6F
-S31508021F6C704707EE100AF8EE476A9FED146A86EE7A
-S31508021F7C267A0C4B1B6BC3F3080306EE903AF8EE63
-S31508021F8C666A9FED0C6A67EE867A76EEA77AF7EEA4
-S31508021F9C006A77EEA67A27EE277AD2E708487047C0
-S31508021FAC024870470044025800093D000090D003CD
-S31508021FBC0024744A000000390024744C0024F44AA4
-S31508021FCC00127A00002800F0368103469C4A1268F1
-S31508021FDC02F00F028A420CD29948026822F00F02CA
-S31508021FEC0A430260026802F00F028A4201D00120FB
-S31508021FFC704770B51A6812F0040F0CD01869914A1A
-S3150802200C926902F07002904205D98E4CA26922F0AE
-S3150802201C70021043A0611A6812F0080F0CD05869A6
-S3150802202C884AD26902F07002904205D9854CE26957
-S3150802203C22F070021043E0611A6812F0100F0CD0ED
-S3150802204C9869804AD26902F4E062904205D97D4CBD
-S3150802205CE26922F4E0621043E0611A6812F0200F7A
-S3150802206C0CD0D869774A126A02F07002904205D9E6
-S3150802207C744C226A22F07002104320621A6812F01B
-S3150802208C020F0CD0D8686F4A926902F00F0290427E
-S3150802209C05D96C4CA26922F00F021043A0611C46AA
-S315080220AC0D461B6813F0010F41D0664A936923F457
-S315080220BC7063A1680B4393616368022B0AD0032BE6
-S315080220CC27D0012B2CD05F4A126812F0040F06D1C6
-S315080220DC0120AFE0126812F4003F00F0AE805949B5
-S315080220EC0A6922F0070213430B61FEF733FE064612
-S315080220FC544B1B6903F038036268B3EBC20F16D054
-S3150802210CFEF728FE801B41F288339842F0D9032049
-S3150802211C90E04C4A126812F0007FE0D1012089E067
-S3150802212C484A126812F4807FD9D1012082E02368CA
-S3150802213C13F0020F0CD0E268424B9B6903F00F03B3
-S3150802214C9A4205D23F498B6923F00F031A438A61D7
-S3150802215C3B4B1B6803F00F03AB420CD9384A136886
-S3150802216C23F00F032B431360136803F00F03AB42E0
-S3150802217C01D001205EE0236813F0040F0CD022690B
-S3150802218C304B9B6903F070039A4205D22D498B6931
-S3150802219C23F070031A438A61236813F0080F0CD0D4
-S315080221AC6269284BDB6903F070039A4205D225490A
-S315080221BCCB6923F070031A43CA61236813F0100F14
-S315080221CC0CD0A2691F4BDB6903F4E0639A4205D271
-S315080221DC1C49CB6923F4E0631A43CA61236813F0DA
-S315080221EC200F0CD0E269174B1B6A03F070039A4254
-S315080221FC05D214490B6A23F070031A430A62FFF7D5
-S3150802220CEBFD10498B69C3F303230F4AD35C03F026
-S3150802221C1F03D8408B6903F00F03D35C03F01F032B
-S3150802222C20FA03F3094A1360094B1860094B18681C
-S3150802223CFEF72EFD70BD012070470120FAE700BF9C
-S3150802224C0020005200440258EC3C02080400002408
-S3150802225C000000240C00002408B5FFF7BDFD0B4A4C
-S3150802226C9369C3F303230A49CB5C03F01F0320FAD1
-S3150802227C03F3926902F00F02885C00F01F0023FA3E
-S3150802228C00F0044A1060044A136008BD0044025860
-S3150802229CEC3C0208040000240000002408B5FFF7F1
-S315080222ACDBFF054BDB69C3F30213044AD35C03F069
-S315080222BC1F03D84008BD00BF00440258EC3C020874
-S315080222CC08B5FFF7C9FF054BDB69C3F30223044ABA
-S315080222DCD35C03F01F03D84008BD00BF0044025864
-S315080222ECEC3C0208404B9B6A03F00303032B79D0A0
-S315080222FC70B50E4604463C4A136823F08063136095
-S3150802230CFEF728FD0546384B1B6813F0006F06D0FE
-S3150802231CFEF720FD401B0228F5D9032070BD324B6F
-S3150802232C9A6A22F47C32216842EA01329A6262681B
-S3150802233C013AC2F30802A1680139490289B20A4371
-S3150802234CE1680139090401F4FE010A4321690139DC
-S3150802235C090601F0FE410A439A63DA6A22F0C002C0
-S3150802236C61690A43DA62DA6A22F02002A1690A432F
-S3150802237CDA62DA6A22F01002DA62D96B1B4A0A406E
-S3150802238CE16942EAC102DA63DA6A42F01002DA62F7
-S3150802239CC6B91A46DB6A43F40023D362124A136897
-S315080223AC43F080631360FEF7D5FC04460E4B1B689C
-S315080223BC13F0006F14D1FEF7CDFC001B0228F5D9D9
-S315080223CC0320ABE7012E05D0074AD36A43F4001360
-S315080223DCD362E3E7044AD36A43F48013D362DDE794
-S315080223EC00209BE701207047004402580700FFFFB4
-S315080223FC404B9B6A03F00303032B79D070B50E4648
-S3150802240C04463C4A136823F080531360FEF7A2FC79
-S3150802241C0546384B1B6813F0005F06D0FEF79AFC8C
-S3150802242C401B0228F5D9032070BD324B9A6A22F05A
-S3150802243C7C72216842EA01529A626268013AC2F3D4
-S3150802244C0802A1680139490289B20A43E1680139CD
-S3150802245C090401F4FE010A4321690139090601F04E
-S3150802246CFE410A431A64DA6A22F4406261690A4333
-S3150802247CDA62DA6A22F40072A1690A43DA62DA6A61
-S3150802248C22F48072DA62596C1B4A0A40E16942EA02
-S3150802249CC1025A64DA6A42F48072DA62C6B91A4618
-S315080224ACDB6A43F48003D362124A136843F08053FF
-S315080224BC1360FEF74FFC04460E4B1B6813F0005FC5
-S315080224CC14D1FEF747FC001B0228F5D90320ABE70B
-S315080224DC012E05D0074AD36A43F08073D362E3E729
-S315080224EC044AD36A43F40003D362DDE700209BE770
-S315080224FC01207047004402580700FFFFF8B504464E
-S3150802250C036813F0006F2BD0436EB3F5801F18D0F7
-S3150802251C07D9B3F5001F1DD0B3F5401F2ED10025E0
-S3150802252C06E05BBB934AD36A43F40033D3620025B5
-S3150802253C904A136D23F44013616E0B431365002600
-S3150802254C10E002210430FFF7CDFE0546002DEFD030
-S3150802255C2E4607E002212430FFF74AFF0546F5E727
-S3150802256C00263546236813F4807F17D0636D042B37
-S3150802257C32D8DFE803F006242A0B0B00012635466F
-S3150802258CF0E77C4AD36A43F40033D3623DBB794AFB
-S3150802259C136D23F00703616D0B431365236813F45C
-S315080225AC007F33D0A36D802B44D01AD80BB3402BA3
-S315080225BC1CD10021201DFFF795FE05461EE00021C1
-S315080225CC201DFFF78FFE0546E0E7002104F12400E3
-S315080225DCFFF70EFF0546D9E701263546DEE72E46F6
-S315080225ECDCE7C02B0AD0B3F5807F07D00126354627
-S315080225FC0CE0604AD36A43F40033D3620DBB5D4ADE
-S3150802260C136D23F4E073A16D0B431365236813F45E
-S3150802261C806F2FD0D4F8A430B3F5800F3ED012D8E1
-S3150802262CD3B1B3F5001F14D10021201DFFF75AFEB2
-S3150802263C054616E0002104F12400FFF7D9FE0546EB
-S3150802264CDCE72E46E2E7B3F5C00F0AD0B3F5000F66
-S3150802265C07D0012635460DE0464AD36A43F40033C1
-S3150802266CD36215BB434A936D23F46003D4F8A410C2
-S3150802267C0B439365236813F4006F2FD0D4F8A83054
-S3150802268CB3F1007F37D012D8D3B1B3F1807F14D10E
-S3150802269C0021201DFFF726FE054616E0002104F14F
-S315080226AC2400FFF7A5FE0546DBE72E46E2E7B3F163
-S315080226BC407F0AD0B3F1806F07D0012635460DE06C
-S315080226CC2C4AD36A43F40033D362DDB9294A936D93
-S315080226DC23F0E063D4F8A8100B439365236813F030
-S315080226EC007F2AD0A36C102B12D00DD9202B1DD00B
-S315080226FC302B12D009E0002104F12400FFF778FEF2
-S3150802270C0546E2E72E46E9E73BB10126354614E0D3
-S3150802271C184AD36A43F40033D3626DB9154AD36C9B
-S3150802272C23F03003A16C0B43D36406E00221201D6F
-S3150802273CFFF7D8FD0546F0E72E46236813F4805FAB
-S3150802274C27D0E36DB3F5005F3ED009D8A3B1B3F534
-S3150802275C805F0BD10021201DFFF7C4FD054610E052
-S3150802276CB3F5405F0DD0B3F5804F0AD00126354636
-S3150802277C0FE000BF00440258934AD36A43F400336D
-S3150802278CD36245BB904A136D23F4E043E16D0B43C8
-S3150802279C1365236813F4005F33D0236EB3F5003F39
-S315080227AC27D01AD83BB1B3F5803F1FD10121201D82
-S315080227BCFFF798FD05461DBB834A136D23F4E023E8
-S315080227CC216E0B4313651CE0002104F12400FFF76C
-S315080227DC0FFE0546D5E72E46DBE7B3F5802FEAD082
-S315080227ECB3F5A02FE7D0B3F5403FE4D00126354622
-S315080227FC07E0012104F12400FFF7FAFD0546DAE7A2
-S3150802280C2E46236813F4804F2CD0D4F8AC30B3F18F
-S3150802281C005F1FD012D83BB1B3F1805F17D10121EB
-S3150802282C201DFFF75FFD0546DDB9674A936D23F058
-S3150802283CE043D4F8AC100B43936513E0B3F1804F25
-S3150802284CF2D0B3F1A04FEFD0B3F1405FECD0012632
-S3150802285C354607E0012104F12400FFF7C9FD0546B8
-S3150802286CE2E72E46236813F4004F1FD0E36EB3F14A
-S3150802287C805F06D0B3F1005F11D03BB10126354615
-S3150802288C14E0514AD36A43F40033D3626DB94E4A03
-S3150802289C136D23F04053E16E0B43136506E00121D9
-S315080228AC201DFFF71FFD0546F0E72E46236813F099
-S315080228BC807F1ED0636C032B17D8DFE803F0070260
-S315080228CC1007414AD36A43F40033D36285B93E4AA8
-S315080228DCD36C23F00303616C0B43D36409E0022126
-S315080228EC201DFFF7FFFC0546F0E70126354600E0FA
-S315080228FC2E46236813F4800F1FD1236813F0010F99
-S3150802290C00F09E80A36F282B00F29680DFE803F076
-S3150802291C84949494949494947F9494949494949480
-S3150802292C8D94949494949494849494949494949462
-S3150802293C84949494949494948400244A136843F447
-S3150802294C80731360FEF706FA0746204B1B6813F4CE
-S3150802295C807F05D1FEF7FEF9C01B6428F5D903253D
-S3150802296C002D50D1184B1B6FD4F8B020534013F4DA
-S3150802297C407F0CD0144B1A6F22F44072196F41F433
-S3150802298C80311967196F21F4803119671A67D4F8DF
-S3150802299CB030B3F5807F1BD0002D36D1D4F8B030C9
-S315080229AC03F44072B2F5407F23D0074A136923F425
-S315080229BC7C53136104490B6FD4F8B020C2F30B0293
-S315080229CC13430B6799E700BF0044025800480258A4
-S315080229DCFEF7C0F90746AC4B1B6F13F0020FDBD19F
-S315080229ECFEF7B8F9C01B41F288339842F3D903258E
-S315080229FCD2E7A548026922F47C52A44901EA1313C8
-S31508022A0C13430361D6E72E4677E72E4675E701216F
-S31508022A1C201DFFF767FC05468DB99B4A536D23F0BB
-S31508022A2C3803A16F0B4353650AE0012104F1240014
-S31508022A3CFFF7DEFC0546EFE70126354600E02E4693
-S31508022A4C236813F0020F20D0636F052B19D8DFE821
-S31508022A5C03F00803110808080121201DFFF742FCA0
-S31508022A6C05468DB9884A536D23F00703616F0B43EC
-S31508022A7C53650AE0012104F12400FFF7B9FC054667
-S31508022A8CEFE70126354600E02E46236813F0040FBD
-S31508022A9C22D0D4F89030052B1AD8DFE803F00803B5
-S31508022AAC120808080121201DFFF71CFC054695B9DA
-S31508022ABC754A936D23F00703D4F890100B4393656C
-S31508022ACC0AE0012104F12400FFF792FC0546EEE721
-S31508022ADC0126354600E02E46236813F0200F2CD02B
-S31508022AECD4F88C30B3F1005F1FD012D83BB1B3F1D6
-S31508022AFC805F17D10021201DFFF7F4FB0546DDB9CF
-S31508022B0C614A536D23F0E043D4F88C100B4353659A
-S31508022B1C13E0B3F1804FF2D0B3F1A04FEFD0B3F17B
-S31508022B2C405FECD00126354607E0022104F1240069
-S31508022B3CFFF75EFC0546E2E72E46236813F0400FC4
-S31508022B4C2CD0D4F89830B3F5006F1FD012D83BB1FD
-S31508022B5CB3F5806F17D10021201DFFF7C3FB05467D
-S31508022B6CDDB9494A936D23F4E053D4F898100B4314
-S31508022B7C936513E0B3F5805FF2D0B3F5A05FEFD09F
-S31508022B8CB3F5406FECD00126354607E0022104F175
-S31508022B9C2400FFF72DFC0546E2E72E46236813F0C0
-S31508022BAC800F2CD0D4F89C30B3F5804F1FD012D896
-S31508022BBC3BB1B3F5005F17D10021201DFFF792FB3D
-S31508022BCC0546DDB9304A936D23F46043D4F89C105C
-S31508022BDC0B43936513E0B3F5004FF2D0B3F5204FD0
-S31508022BECEFD0B3F5C04FECD00126354607E00221EB
-S31508022BFC04F12400FFF7FCFB0546E2E72E462368A0
-S31508022C0C13F0080F0CD0D4F88030B3F5805F28D0B7
-S31508022C1C1D4A536D23F44053D4F880100B43536565
-S31508022C2C236813F0100F0CD0D4F89430B3F5807FC8
-S31508022C3C20D0154A936D23F44073D4F894100B43A1
-S31508022C4C9365236813F4002F39D0D4F8A030B3F562
-S31508022C5C803F2CD0B3F5003F1FD0CBB101263546A9
-S31508022C6C2DE0022104F12400FFF7C2FB0028CFD085
-S31508022C7C0126CDE7022104F12400FFF7B9FB00284F
-S31508022C8CD7D00126D5E700BF00440258CFFFFF0074
-S31508022C9C0021201DFFF726FB05467DB9644A936D74
-S31508022CAC23F44033D4F8A0100B43936507E00221B2
-S31508022CBC04F12400FFF79CFB0546EEE72E46236833
-S31508022CCC13F4802F24D0D4F88430B3F5001F17D010
-S31508022CDCB3F5401F0AD0B3F5801F02D0012635463C
-S31508022CEC16E0534AD36A43F40033D3627DB9504A89
-S31508022CFC536D23F44013D4F884100B43536507E041
-S31508022D0C012104F12400FFF773FB0546EEE72E4674
-S31508022D1C236813F4803F14D0E36C2BB1B3F5803FD0
-S31508022D2C23D0012635460CE0414AD36A43F40033D4
-S31508022D3CD36205BB3E4AD36C23F48033E16C0B4356
-S31508022D4CD364236813F0005F17D1236813F4003F8A
-S31508022D5C2DD0E36FB3F5807F1BD017D9B3F5007F5F
-S31508022D6C1CD0B3F5407F12D118E00221201DFFF7C3
-S31508022D7CB9FA0546DDE72E46E3E7022104F12400FB
-S31508022D8CFFF736FB0028E0D00126DEE733B1012631
-S31508022D9C0DE0274AD36A43F40033D362002D3DD1A2
-S31508022DAC234A536D23F44073E16F0B43536523682F
-S31508022DBC13F4801F06D01E4A136D23F00043216FAD
-S31508022DCC0B431365236813F0805F07D0184A1369FF
-S31508022DDC23F48043D4F8B4100B431361236813F419
-S31508022DEC001F06D0124A136D23F08073A16E0B4393
-S31508022DFC1365236813F0804F09D00D4B1A6922F418
-S31508022E0C00421A611A69D4F8B8100A431A6123687F
-S31508022E1C002B05DB06B101263046F8BD2E46C6E761
-S31508022E2C034AD36C23F04053216D0B43D364F1E769
-S31508022E3C0044025808B5FFF70FFA054B1B6AC3F391
-S31508022E4C0213044AD35C03F01F03D84008BD00BF23
-S31508022E5C00440258EC3C020810B478498C6A8A6A17
-S31508022E6CC2F30532CB6AC3F30013C96BC1F3CC01A7
-S31508022E7C03FB01F3002A00F0DB8004F0030407EEDF
-S31508022E8C903AF8EE677A012C66D0FCB1022C00F067
-S31508022E9CB28007EE102AB8EE477A9FED696AC6EE3B
-S31508022EAC076A664B9B6BC3F3080307EE103AB8EE38
-S31508022EBC477A9FED646A67EE867A77EE277AB7EEDB
-S31508022ECC007A77EE877A66EEA76A61E05B4B1B6837
-S31508022EDC13F0200F23D0594C2168C1F3C1015A4B68
-S31508022EECCB4007EE103AB8EE477A06EE902AB8EEC1
-S31508022EFC666AC7EE066AA36BC3F3080307EE103AB3
-S31508022F0CB8EE477A9FED4F6A67EE867A77EE277A9E
-S31508022F1CB7EE007A77EE877A66EEA76A38E007EE9E
-S31508022F2C102AB8EE477A9FED496AC6EE076A434BF2
-S31508022F3C9B6BC3F3080307EE103AB8EE477A9FED7C
-S31508022F4C416A67EE867A77EE277AB7EE007A77EEDB
-S31508022F5C877A66EEA76A1BE007EE102AB8EE477A5E
-S31508022F6C9FED376AC6EE076A344B9B6BC3F30803AD
-S31508022F7C07EE103AB8EE477A9FED326A67EE867A12
-S31508022F8C77EE277AB7EE007A77EE877A66EEA76A35
-S31508022F9C2A4A936BC3F3462307EE103AB8EE477ADE
-S31508022FACB7EE006A37EE067AC6EE877AFCEEE77A51
-S31508022FBCC0ED007A936BC3F3064307EE103AB8EEEC
-S31508022FCC477A37EE067AC6EE877AFCEEE77AC0EDD2
-S31508022FDC017A936BC3F3066307EE903AF8EE677AB7
-S31508022FEC77EE867A86EEA77ABCEEC77A80ED027AF7
-S31508022FFC5DF8044B704707EE102AB8EE477A9FED38
-S3150802300C146AC6EE076A0D4B9B6BC3F3080307EEED
-S3150802301C103AB8EE477A9FED0B6A67EE867A77EE28
-S3150802302C277AB7EE007A77EE877A66EEA76AAFE763
-S3150802303C0023036043608360DAE700BF004402584A
-S3150802304C0024744A000000390090D0030024744C02
-S3150802305C0024F44A10B478498C6A8A6AC2F3055277
-S3150802306CCB6AC3F30023496CC1F3CC0103FB01F30E
-S3150802307C002A00F0DB8004F0030407EE903AF8EE1F
-S3150802308C677A012C66D0FCB1022C00F0B28007EEEE
-S3150802309C102AB8EE477A9FED696AC6EE076A664B3E
-S315080230AC1B6CC3F3080307EE103AB8EE477A9FED8A
-S315080230BC646A67EE867A77EE277AB7EE007A77EE47
-S315080230CC877A66EEA76A61E05B4B1B6813F0200FE2
-S315080230DC23D0594C2168C1F3C1015A4BCB4007EE98
-S315080230EC103AB8EE477A06EE902AB8EE666AC7EE3A
-S315080230FC066A236CC3F3080307EE103AB8EE477A4E
-S3150802310C9FED4F6A67EE867A77EE277AB7EE007AE4
-S3150802311C77EE877A66EEA76A38E007EE102AB8EEDB
-S3150802312C477A9FED496AC6EE076A434B1B6CC3F393
-S3150802313C080307EE103AB8EE477A9FED416A67EE36
-S3150802314C867A77EE277AB7EE007A77EE877A66EE84
-S3150802315CA76A1BE007EE102AB8EE477A9FED376A84
-S3150802316CC6EE076A344B1B6CC3F3080307EE103A18
-S3150802317CB8EE477A9FED326A67EE867A77EE277A49
-S3150802318CB7EE007A77EE877A66EEA76A2A4A136C46
-S3150802319CC3F3462307EE103AB8EE477AB7EE006A3F
-S315080231AC37EE067AC6EE877AFCEEE77AC0ED007A37
-S315080231BC136CC3F3064307EE103AB8EE477A37EEAA
-S315080231CC067AC6EE877AFCEEE77AC0ED017A136CBC
-S315080231DCC3F3066307EE903AF8EE677A77EE867AC9
-S315080231EC86EEA77ABCEEC77A80ED027A5DF8044BB6
-S315080231FC704707EE102AB8EE477A9FED146AC6EEA8
-S3150802320C076A0D4B1B6CC3F3080307EE103AB8EEAC
-S3150802321C477A9FED0B6A67EE867A77EE277AB7EED0
-S3150802322C007A77EE877A66EEA76AAFE70023036021
-S3150802323C43608360DAE700BF004402580024744AEC
-S3150802324C000000390090D0030024744C0024F44A80
-S3150802325C2DE9F04387B00446016883680269134373
-S3150802326C42691343C2691343426E13430868884A78
-S3150802327C02401A430A602268536823F44053E168F1
-S3150802328C0B435360A1692268824B9A4201D0236A86
-S3150802329C19439068804B03400B4393602268D36AA8
-S315080232AC23F00F03616A0B43D36223687B4A93426A
-S315080232BC1FD07B4A934259D07A4A934270D07A4AA3
-S315080232CC934200F08780794A934200F09D80784AAF
-S315080232DC934200F0B380774A934200F0F180764A23
-S315080232EC934200F004816B4A934200F017818022C4
-S315080232FC2DE1724A526D02F03802282A34D8DFE8D8
-S3150802330C12F0290033003300330033003300330044
-S3150802331C3300250133003300330033003300330006
-S3150802332C33002B00330033003300330033003300F1
-S3150802333C33002D00330033003300330033003300DF
-S3150802334C33002F00330033003300330033003300CD
-S3150802335C330031000122FAE00822F8E01022F6E0E6
-S3150802336C2022F4E04022F2E08022F0E0534A526D29
-S3150802337C02F00702052A11D8DFE812F00600370117
-S3150802338C08000A000C000E000022E0E00822DEE02B
-S3150802339C1022DCE02022DAE04022D8E08022D6E0B5
-S315080233AC464A526D02F00702052A11D8DFE812F0D6
-S315080233BC06001F0108000A000C000E000022C6E0D7
-S315080233CC0822C4E01022C2E02022C0E04022BEE05D
-S315080233DC8022BCE0394A526D02F00702052A11D83E
-S315080233ECDFE812F00600070108000A000C000E00BE
-S315080233FC0022ACE00822AAE01022A8E02022A6E0CD
-S3150802340C4022A4E08022A2E02C4A526D02F0070266
-S3150802341C052A11D8DFE812F00600EF0008000A00A8
-S3150802342C0C000E00002292E0082290E010228EE098
-S3150802343C20228CE040228AE0802288E01F4A526DC4
-S3150802344C02F03802282A20D8DFE802F0151F1F1FBF
-S3150802345C1F1F1F1FD71F1F1F1F1F1F1F171F1F1FB0
-S3150802346C1F1F1F1F191F1F1F1F1F1F1F1B1F1F1F5A
-S3150802347C1F1F1F1F1D00012269E0082267E0102288
-S3150802348C65E0202263E0402261E080225FE000BF13
-S3150802349CF369FFCF000C0058FFF4FF11001001402E
-S315080234AC0044004000480040004C004000500040D8
-S315080234BC0014014000780040007C00400044025889
-S315080234CC824A526D02F00702052A0ED8DFE802F08C
-S315080234DC03970507090B002239E0082237E0102268
-S315080234EC35E0202233E0402231E080222FE0774A71
-S315080234FC526D02F00702052A0ED8DFE802F00382A3
-S3150802350C0507090B002222E0082220E010221EE001
-S3150802351C20221CE040221AE0802218E002F50E3224
-S3150802352C926D02F00702052A0ED8DFE802F0036C48
-S3150802353C0507090B02220AE0082208E0102206E017
-S3150802354C202204E0402202E0802200E004226049A4
-S3150802355C8B425AD0E369B3F5004F00F0C380402A78
-S3150802356C00F27981DFE812F027014B017701770126
-S3150802357C4E017701770177015301770177017701BC
-S3150802358C770177017701770158017701770177017E
-S3150802359C770177017701770177017701770177014F
-S315080235AC7701770177017701250177017701770191
-S315080235BC770177017701770177017701770177012F
+S315080206DC266404236364A564E36425656365A565DA
+S315080206ECE56525666566A366204600F089FC0395D2
+S315080206FC04950596069640F267630793089309953F
+S3150802070C03A9204600F0C6FD00963346022211467E
+S3150802071C204600F002FE204600F01BFE0CB070BD0F
+S3150802072C2C00002400A0004008B500230122014633
+S3150802073C034803F05FF908B1002008BD0120FCE765
+S3150802074CCC00002408B5FFF77FFFFFF795FF08BD1D
+S3150802075CBFF34F8F0549CA6802F4E062044B134390
+S3150802076CCB60BFF34F8F00BFFDE700BF00ED00E083
+S3150802077C0400FA0508B5214B1B78B3B92048FFF7D4
+S3150802078CD3FF012800D008BD1D4B1B78013BDBB2F9
+S3150802079C3F2BF8D800F097F81A4B1860174B012222
+S315080207AC1A70194B00221A70EDE7174B1B78013396
+S315080207BC13481844FFF7B8FF012813D1124A1378C5
+S315080207CC0133DBB213700E4A12789342DBD10B4A11
+S315080207DC002111700A4A5278FF2AD4D1022BD2D19F
+S315080207ECFFF7B6FF00F06FF8064B1B6864339842A6
+S315080207FCC9D9024B00221A70C5E700BF9901002419
+S3150802080C580100249C0100249A01002400B58DB0DD
+S3150802081C4021104800F096FE10B90DB05DF804FBA5
+S3150802082C6B4602AA40210B4800F0AEFD0028F4D113
+S3150802083C029A40F267639A42EFD1039B002BECD1E2
+S3150802084C9DF816209DF80030FF2BE6D1022AE4D13A
+S3150802085CFFF77EFF2C00002408B5FFF78BFFFFF786
+S3150802086CD5FF08BD08B500228021024800F068FFB2
+S3150802087C08BD00BF0004025810B500F024F80E4B50
+S3150802088C1B68C31AB3F5FA7F0CD304460B4B1B78B9
+S3150802089C4BB90122094B1A708021094800F050FF06
+S315080208AC054B1C6010BD0022044B1A7080210448AB
+S315080208BC00F046FFF4E700BFA4010024A0010024BF
+S315080208CC00040258704708B500F04AFA08BD000041
+S315080208DC014A024B9A6070470000020800ED00E0DC
+S315080208EC30B589B0002403940494059406940794AD
+S315080208FC1B4BD3F8E02042F08002C3F8E020D3F871
+S3150802090CE02002F080020092009AD3F8E02042F02E
+S3150802091C0802C3F8E020D3F8E02002F0080201929C
+S3150802092C019AD3F8E02042F00202C3F8E020D3F889
+S3150802093CE03003F002030293029B0A4D2246802101
+S3150802094C284600F0FDFE80230393012304930594A5
+S3150802095C069403A9284600F003FE09B030BD00BF71
+S3150802096C004402580004025830B5CDB04C2200217E
+S3150802097C39A803F070F92022002131A803F06BF98B
+S3150802098CBC22002102A803F066F9022000F0DEFE62
+S3150802099C00230193254B9A6942F440429A619B695A
+S315080209AC03F440430193224BDA6A42F00102DA62FB
+S315080209BCDB6A03F001030193019B1C4B9B6913F43D
+S315080209CC005FFAD0012339934FF4A0233A930223FA
+S315080209DC42934393042544954FF4F07245924693F9
+S315080209EC47954893499500244A944B9439A800F0A4
+S315080209FCD7FE3F233193032332933394082334933C
+S31508020A0C4023359336934FF48062379238932946AE
+S31508020A1C31A801F0DFFA48F2020302931D941F94DF
+S31508020A2C02A801F073FD4DB030BD00BF0048025854
+S31508020A3C0004005808B5FFF74BFF00F057F9FFF70B
+S31508020A4C93FFFFF74DFFFFF7C3FDFFF7C9FDFCE761
+S31508020A5C82B0074BD3F8F42042F00202C3F8F42012
+S31508020A6CD3F8F43003F002030193019B02B07047EA
+S31508020A7C0044025800B589B00023039304930593E6
+S31508020A8C069307930268154B9A4202D009B05DF891
+S31508020A9C04FB134BD3F8EC2042F48072C3F8EC2017
+S31508020AACD3F8EC2002F480720192019AD3F8E02072
+S31508020ABC42F00202C3F8E020D3F8E03003F0020356
+S31508020ACC0293029B4FF44073039302230493092364
+S31508020ADC079303A9034800F043FDD7E700A000409B
+S31508020AEC004402580004025800B589B00023039347
+S31508020AFC04930593069307930268154B9A4202D000
+S31508020B0C09B05DF804FB134BD3F8E82042F48022B3
+S31508020B1CC3F8E820D3F8E82002F480220192019A5D
+S31508020B2CD3F8E02042F00802C3F8E020D3F8E0300C
+S31508020B3C03F008030293029B4FF4407303930223B8
+S31508020B4C04930723079303A9034800F009FDD7E783
+S31508020B5C0048004000440258000C02587047FEE751
+S31508020B6CFEE7FEE7FEE770477047704708B500F0E8
+S31508020B7CEBF808BD294AD2F8883043F47003C2F858
+S31508020B8C8830274B1B6803F00F03062B06D8244A1A
+S31508020B9C136823F00F0343F007031360214B1A68FB
+S31508020BAC42F001021A6000221A6119681E4A0A40AA
+S31508020BBC1A601B4B1B6803F00F03072B06D9184A3E
+S31508020BCC136823F00F0343F007031360154B002237
+S31508020BDC9A61DA611A62154999621549D9621549F7
+S31508020BEC19635A639963DA6319645A64196821F4A6
+S31508020BFC802119601A66104B1A68104B1340B3F110
+S31508020C0C005F02D20E4B01221A600E4B43F2D2023D
+S31508020C1C1A60024B4FF000629A60704700ED00E0D2
+S31508020C2C00200052004402587FEDF6EA0002020246
+S31508020C3C0000FF01800201010010005C0000FFFFAA
+S31508020C4C0881005100400052DFF834D0FFF792FFBA
+S31508020C5C002103E00B4B5B58435004310A480B4BFB
+S31508020C6C42189A42F6D30A4A02E0002342F8043B97
+S31508020C7C084B9A42F9D302F0BFFFFFF7DBFE704727
+S31508020C8C00000824443D0208000000241000002439
+S31508020C9C10000024AC010024FEE70000104B1B7860
+S31508020CAC0BB90120704710B504464FF47A70B0FBA5
+S31508020CBCF3F30C4A1068B0FBF3F000F0A1F868B92C
+S31508020CCC0F2C01D901200AE0002221464FF0FF30F1
+S31508020CDC00F064F8044B1C60002000E0012010BDF3
+S31508020CEC08000024000000240C00002410B5032080
+S31508020CFC00F042F801F078F80F498B69C3F3032325
+S31508020D0C0E4AD35C03F01F03D8408B6903F00F031A
+S31508020D1CD35C03F01F0320FA03F3094A1360094B49
+S31508020D2C18600020FFF7BAFF10B10124204610BD47
+S31508020D3C0446FFF78DFEF9E700440258FC3C02080C
+S31508020D4C0400002400000024034B1B78034A116894
+S31508020D5C0B441360704700BF08000024A801002446
+S31508020D6C014B1868704700BFA8010024014B18688C
+S31508020D7C000C70470010005C0649CB6823F4E0634C
+S31508020D8C1B041B0C000200F4E0600343024A1A43DC
+S31508020D9CCA60704700ED00E00000FA0530B4154B46
+S31508020DACDB68C3F30223C3F10704042C28BF04240B
+S31508020DBC1D1D062D14D9033B4FF0FF3505FA04F415
+S31508020DCC21EA0401994005FA03F322EA03031943BB
+S31508020DDC002807DB0901C9B2074B195430BC704706
+S31508020DEC0023E9E700F00F000901C9B2034B1954B5
+S31508020DFCF4E700BF00ED00E000E400E014ED00E0CB
+S31508020E0C0138B0F1807F0AD2064B5860064AF021A7
+S31508020E1C82F823100020986007221A607047012076
+S31508020E2C704700BF10E000E000ED00E030B4446B00
+S31508020E3C0268D2F884106F4B194041EA8401C2F851
+S31508020E4C84100268D2F8841021F47F01856B41EA7A
+S31508020E5C0541C2F88410826B22440468D4F88810BF
+S31508020E6C194041EA8201C4F888100468D4F888103B
+S31508020E7C21F4FE01C56B41EA0541C4F88810C16B21
+S31508020E8C02EB41020468D4F8A010194041EA820127
+S31508020E9CC4F8A0100468D4F8A01021F4FE01056C5D
+S31508020EAC41EA0541C4F8A010046C416C01FB042408
+S31508020EBC0268D2F8B010194041EA8401C2F8B0109F
+S31508020ECC0268D2F8B01021F4FE01856C41EA05419C
+S31508020EDCC2F8B010826CC16C01FB02440268D2F8EB
+S31508020EECAC10194041EA8401C2F8AC10026D416D8E
+S31508020EFC01FB02420468D4F8F010194041EA820157
+S31508020F0CC4F8F0100468D4F8F01021F47C11856D3D
+S31508020F1C41EA0541C4F8F010816D02EB41020468FE
+S31508020F2CD4F8C0100B4043EA8202C4F8C020026807
+S31508020F3CD2F8C03023F47C13C16D43EA0143C2F8DC
+S31508020F4CC0300268D2F8C03023F07C53016E43EAF3
+S31508020F5C0163C2F8C030436B274A1A449200C26630
+S31508020F6C836B02EB83030367C16B03EBC103436712
+S31508020F7C046C416C01FB04F103EB81038367846CFB
+S31508020F8CC16C01FB04F103EB8103C367046D416D6C
+S31508020F9C01FB04F103EB8103C0F88030816D03EB8E
+S31508020FACC103C0F88430C46D856E05FB04F403EBEB
+S31508020FBC8403C0F88830016E01FB05F103EB81034B
+S31508020FCCC0F890300D498B420DD9D0F89C3043F0BD
+S31508020FDC2003C0F89C30032380F89830012007E0E0
+S31508020FEC002342F8043BD0F890309342F8D80020FC
+S31508020FFC30BC70470300FFFF002B0010FCD30040E7
+S3150802100C30B595B004464C22A04901A802F018FE48
+S3150802101C002C00F0388123689D4A934220D094F81C
+S3150802102C98300BB32268936923F010039361FFF788
+S3150802103C97FE054623689A6912F0080F1AD0FFF72D
+S3150802104C8FFE401B0A28F5D9D4F89C3043F00103CD
+S3150802105CC4F89C30032384F89830012015B030BDAF
+S3150802106C03F580736360DAE784F899302046FFF754
+S3150802107C01FDD7E79A6942F001029A61FFF770FE01
+S3150802108C054623689A6912F0010F0FD1FFF768FE1D
+S3150802109C401B0A28F5D9D4F89C3043F00103C4F84E
+S315080210AC9C30032384F898300120D7E79A6942F0DA
+S315080210BC02029A61237C012B40D02268936943F081
+S315080210CC40039361637C012B3ED02268936923F417
+S315080210DC80439361A37C012B3CD02268936943F429
+S315080210EC805393612268936923F44073A1680B4376
+S315080210FC93612268936923F0A403936122681369A6
+S3150802110C23F010031361E368012B29D0002B2CD092
+S3150802111C022B00F09B802268936943F0800393614B
+S3150802112C2268136943F010031361E368032B1CD17D
+S3150802113C2268936943F02003936116E02268936947
+S3150802114C23F040039361BDE72268936943F4804315
+S3150802115C9361BFE72268936923F480539361C1E7CD
+S3150802116C2268936943F004039361A3695A1EE369DF
+S3150802117C013B1B0243EA4263226A013A1343626940
+S3150802118C013A216843EA0243CB61A368B3F5407F6F
+S3150802119C62D0236E33B12268D2F8C030616E0B432B
+S315080211ACC2F8C030E36D226ED3420DD02168D1F855
+S315080211BCC83023F00703A26E14A800EB820252F879
+S315080211CC4C2C1343C1F8C830236C6BB12168D1F887
+S315080211DCBC3023F00703626C14A800EB820252F8A7
+S315080211EC4C2C1343C1F8BC30A36C73B12168D1F8EB
+S315080211FCBC3023F07003E26C14A800EB820252F89E
+S3150802120C4C2C43EA0213C1F8BC30236D73B1216826
+S3150802121CD1F8BC3023F4E063626D14A800EB8202A9
+S3150802122C52F84C2C43EA0223C1F8BC302268184BFC
+S3150802123C9A4222D00023C4F89430C4F89C30012375
+S3150802124C84F898302046FFF7F1FD07E72268936980
+S3150802125C43F02003936188E7A36A013BE26A013AE9
+S3150802126C43EA0223226B013A43EA0213626A013AFF
+S3150802127C216843EA0243CB608BE76268936823F0E2
+S3150802128C03039360D6E70120E8E600BF8C3C02080C
+S3150802129C00A0004090F89830013BDBB2012B07D92D
+S315080212ACD0F89C3043F00203C0F89C3001207047FA
+S315080212BCCB680A68D2B9072B0ED08A68DB0643EAD2
+S315080212CC82730A6943EA02434A691343C26E49683E
+S315080212DC42F82130002070470A69CB691B0243EA9F
+S315080212EC02438A69134343F06053EFE710B40A6961
+S315080212FC42EA4372072B0ED08C684B6943EA847315
+S3150802130C006F496800EBC10440F831206360002085
+S3150802131C5DF8044B70478B69F2E710B490F8984065
+S3150802132CE4B2012C09D0D0F89C3043F00403C0F87F
+S3150802133C9C3001205DF8044B7047920042EA011179
+S3150802134C41EA4303026801990B43C2F88030002034
+S3150802135CF0E790F89830DBB2012B07D0D0F89C3026
+S3150802136C43F00403C0F89C3001207047022380F82E
+S3150802137C98300268936923F0010393610023C0F83D
+S3150802138C9C30184670470000F0B490F89840E4B2C6
+S3150802139C022C08D0D0F89C3043F00803C0F89C30D5
+S315080213AC0120F0BC7047402939D0412964D0046D1C
+S315080213BC8C4240F28E80C46F456D01FB05F504EB39
+S315080213CC85044FF0000C256805F080455560002D04
+S315080213DC40F087802568C5F38A451560256805F0AF
+S315080213EC00559560256805F000451561A588D561F7
+S315080213FC656805F47025D560656805F48015556130
+S3150802140C656805F400159561E57905F07F051562A1
+S3150802141C6568ED0F556204F10805002469E0046855
+S3150802142CD4F8A05015F4FE0F16D0D4F8A45015F023
+S3150802143C7F0F19D0D4F8A45015F0807F01D0D4F8B8
+S3150802144CA050D4F8A440C4F3052C446F456C0CFB8D
+S3150802145C05F504EB8504B6E7D0F89C3043F0200377
+S3150802146CC0F89C3001209CE7D0F89C3043F480737A
+S3150802147CC0F89C30012094E70468D4F8B05015F4EF
+S3150802148CFE0F16D0D4F8B45015F07F0F19D0D4F835
+S3150802149CB45015F0807F01D0D4F8B050D4F8B440CB
+S315080214ACC4F3052C846FC56C0CFB05F504EB85049B
+S315080214BC89E7D0F89C3043F02003C0F89C30012011
+S315080214CC6FE7D0F89C3043F48073C0F89C30012047
+S315080214DC67E7D0F89C3043F02003C0F89C30012013
+S315080214EC5FE7256825F06045156077E72E5D1E5582
+S315080214FC0134D689124FBE5DA642F7D840290BD0C5
+S3150802150C41290ED01F2911D80268012303FA01F1C9
+S3150802151CC2F89810002044E70368C3F8A8C0002054
+S3150802152C3FE70368C3F8B8C000203AE701F01F0189
+S3150802153C0268012303FA01F1C2F89C10002030E775
+S3150802154C0C3D0208402905D00368D3F8B40000F014
+S3150802155C7F0070470368D3F8A40000F07F00704739
+S3150802156CF0B583B000233AE0092400E00024B44025
+S3150802157C3C4302356E4E46F825406E4C2568D443DC
+S3150802158C04EA05064F6817F4803F01D042EA0506BD
+S3150802159C684D2E606E6804EA06054F6817F4003F1C
+S315080215AC01D042EA0605634E75604FF0B0452D68C8
+S315080215BC04EA05064F6817F4801F01D042EA0506AD
+S315080215CC4FF0B0452E606D682C404E6816F4001F1D
+S315080215DC01D042EA05044FF0B042546001330A685E
+S315080215EC32FA03F400F0A28001249C402240F5D082
+S315080215FC4D686E1E112D18BF012E01D9122D12D14E
+S3150802160C86685F000325BD4026EA0506CD68BD40FF
+S3150802161C35438560466826EA04064D68C5F3001408
+S3150802162C9C4034434460C6685F000325BD40EC43C6
+S3150802163C26408D68BD403543C5604D68122D18BFCE
+S3150802164C022D13D1DE08083650F826E003F00705FA
+S3150802165C4FEA850C0F2505FA0CF52EEA050E0D69CF
+S3150802166C05FA0CF545EA0E0540F82650056825409C
+S3150802167C4C6804F00304BC402C4304604C6814F018
+S3150802168C805FABD02C4CD4F8F45045F00205C4F864
+S3150802169CF450D4F8F44004F002040194019C9D0819
+S315080216ACAE1C234C54F8267003F00304A6000F2430
+S315080216BCB44027EA0407214CA0423FF457AF04F57D
+S315080216CC8064A04222D004F58064A04220D004F59E
+S315080216DC8064A0421ED004F58064A0421CD004F596
+S315080216EC8064A0421AD004F58064A04218D004F58E
+S315080216FC8064A04216D004F58064A04214D004F586
+S3150802170C8064A0423FF430AF0A2430E701242EE766
+S3150802171C02242CE703242AE7042428E7052426E7CF
+S3150802172C062424E7072422E7082420E703B0F0BDA1
+S3150802173C0004005880000058004402580000025861
+S3150802174C12B909048161704781617047134BDB68D2
+S3150802175C13F0040F07D1114BDB6803F0070383421E
+S3150802176C1AD00120704710B50C4AD36823F0070328
+S3150802177C1843D060FFF7F4FA0446084B5B6813F477
+S3150802178C005F07D1FFF7ECFA001BB0F57A7FF4D9A4
+S3150802179C012000E0002010BD0020704700480258C6
+S315080217AC002800F00C8338B50446036813F0010FC1
+S315080217BC25D09D4A136903F03803926A102B15D06B
+S315080217CC182B0FD06368B3F5803F3FD0002B53D14B
+S315080217DC954B1A6822F480321A601A6822F480220F
+S315080217EC1A6038E002F00302022AEBD18E4B1B6810
+S315080217FC13F4003F03D06368002B00F0E2822368DF
+S3150802180C13F0020F00F08B80874A1369926A13F061
+S3150802181C38035AD0182B55D0E368002B00F0C88031
+S3150802182C81490A6822F0190213430B60FFF798FAEA
+S3150802183C05467D4B1B6813F0040F40F09780FFF7A3
+S3150802184C8FFA401B0228F4D90320BFE2764A1368A2
+S3150802185C43F48033136063682BB3FFF781FA0546AA
+S3150802186C714B1B6813F4003FC9D1FFF779FA401B79
+S3150802187C6428F5D90320A9E2B3F5A02F09D06A4B3F
+S3150802188C1A6822F480321A601A6822F480221A60C4
+S3150802189CE1E7654B1A6842F480221A601A6842F428
+S315080218AC80321A60D7E7FFF75BFA05465E4B1B6870
+S315080218BC13F4003FA3D0FFF753FA401B6428F5D95B
+S315080218CC032083E212F0030FA6D1574B1B6813F0C1
+S315080218DC040F03D0E368002B00F07582FFF746FA73
+S315080218EC41F20303984212D82269402A07D04E497C
+S315080218FC4B6823F47C3343EA02334B600FE04A4AC3
+S3150802190C536823F47C3343F40033536007E0464AA6
+S3150802191C536823F0FE43216943EA01635360236843
+S3150802192C13F0100F00F08A803F4A136903F038034C
+S3150802193C926A082B54D0182B4ED0E369002B00F070
+S3150802194CBA80394A136843F080031360FFF708FA22
+S3150802195C0546354B1B6813F4807F40F08A80FFF7E7
+S3150802196CFFF9401B0228F4D903202FE2FFF7FEF9F0
+S3150802197C41F20303984212D82269402A07D02A490F
+S3150802198C4B6823F47C3343EA02334B60C7E7264A97
+S3150802199C536823F47C3343F400335360BFE7224A7B
+S315080219AC536823F0FE43216943EA01635360B6E7A1
+S315080219BC1D4A136823F001031360FFF7D1F9054694
+S315080219CC194B1B6813F0040FA9D0FFF7C9F9401B72
+S315080219DC0228F5D90320F9E102F00302012AACD157
+S315080219EC114B1B6813F4807F04D0E369802B01D05A
+S315080219FC0120EBE1FFF7BAF941F20303984215D835
+S31508021A0C226A202A07D008494B6823F0F84343EA8E
+S31508021A1C82634B6012E0044A536823F0F84343F09E
+S31508021A2C804353600AE000BF004402589A4AD368BE
+S31508021A3C23F07C53216A43EA0163D360236813F0CB
+S31508021A4C080F60D06369002B49D0934A536F43F051
+S31508021A5C01035367FFF784F905468F4B5B6F13F047
+S31508021A6C020F50D1FFF77CF9401B0228F5D9032047
+S31508021A7CACE1FFF77BF941F20303984212D8226ACA
+S31508021A8C202A07D084494B6823F0F84343EA826339
+S31508021A9C4B60D3E7804A536823F0F84343F08043FC
+S31508021AAC5360CBE77C4AD36823F07C53216A43EA1A
+S31508021ABC0163D360C2E7784A136823F08003136084
+S31508021ACCFFF74EF90546744B1B6813F4807FB5D0A5
+S31508021ADCFFF746F9401B0228F5D9032076E16E4A30
+S31508021AEC536F23F001035367FFF73AF905466A4B1E
+S31508021AFC5B6F13F0020F06D0FFF732F9401B022870
+S31508021B0CF5D9032062E1236813F0200F29D0A369C3
+S31508021B1C9BB1614A136843F480531360FFF720F9AB
+S31508021B2C05465D4B1B6813F4005F1AD1FFF718F9CB
+S31508021B3C401B0228F5D9032048E1574A136823F4B7
+S31508021B4C80531360FFF70CF90546534B1B6813F4C5
+S31508021B5C005F06D0FFF704F9401B0228F5D90320CB
+S31508021B6C34E1236813F0040F21D1636A002B00F0C9
+S31508021B7C2C81494A126902F03802182A00F0EE80C2
+S31508021B8C022B75D0444A136823F080731360FFF74F
+S31508021B9CE7F80446404B1B6813F0007F00F0DC8024
+S31508021BACFFF7DEF8001B0228F4D903200EE13B4AA4
+S31508021BBC136843F480731360FFF7D2F80546374B64
+S31508021BCC1B6813F4807F06D1FFF7CAF8401B6428FA
+S31508021BDCF5D90320FAE0A368012B0AD00BBB2E4BCE
+S31508021BEC1A6F22F001021A671A6F22F004021A6798
+S31508021BFC04E0294A136F43F001031367A36833B34E
+S31508021C0CFFF7AEF80546244B1B6F13F0020FACD147
+S31508021C1CFFF7A6F8401B41F288339842F3D9032002
+S31508021C2CD4E0052B09D01C4B1A6F22F001021A6755
+S31508021C3C1A6F22F004021A67E0E7174B1A6F42F082
+S31508021C4C04021A671A6F42F001021A67D6E7FFF7FF
+S31508021C5C87F80546104B1B6F13F0020F85D0FFF75A
+S31508021C6C7FF8401B41F288339842F3D90320ADE042
+S31508021C7C094A136823F080731360FFF771F8054657
+S31508021C8C054B1B6813F0007F0AD0FFF769F8401B57
+S31508021C9C0228F5D9032099E0004402580048025854
+S31508021CAC4E4B996A4E4A0A40A16AE06A41EA001109
+S31508021CBC0A439A62226B013AC2F30802616B013932
+S31508021CCC490289B20A43A16B0139090401F4FE01DE
+S31508021CDC0A43E16B0139090601F0FE410A431A630C
+S31508021CECDA6A22F00102DA62596B3E4A0A40A16CA0
+S31508021CFC42EAC1025A63DA6A22F00C02216C0A43DE
+S31508021D0CDA62DA6A22F00202616C0A43DA62DA6A87
+S31508021D1C42F48032DA62DA6A42F40032DA62DA6A57
+S31508021D2C42F48022DA62DA6A42F00102DA621A684C
+S31508021D3C42F080721A60FFF713F80446274B1B68A9
+S31508021D4C13F0007F06D1FFF70BF8001B0228F5D912
+S31508021D5C03203BE0002039E0002037E01F4A916A55
+S31508021D6C106B012B33D001F00303A26A934201D004
+S31508021D7C01202BE0C1F30511E36A994201D0012037
+S31508021D8C24E0C0F30802236B013B9A4201D00120DE
+S31508021D9C1CE0C0F34622636B013B9A4201D0012038
+S31508021DAC14E0C0F30642A36B013B9A4211D1C0F36D
+S31508021DBC0660E36B013B98420DD0012006E0012038
+S31508021DCC7047012002E0012000E0002038BD012006
+S31508021DDCFCE70120FAE70020F8E700BF00440258A6
+S31508021DEC0CFCFFFF0700FFFF724B1B6903F038035D
+S31508021DFC102B00F0DB80182B10D00BB16E487047F5
+S31508021E0C6C4B1B6813F0200F00F0D280694B1868D4
+S31508021E1CC0F3C100694B23FA00F07047654A916A10
+S31508021E2C01F00301906AC0F30510D36A03F00103AB
+S31508021E3C526BC2F3CC0203FB02F307EE903AF8EEAE
+S31508021E4C677A002800F0B580012966D0F9B1022913
+S31508021E5C00F08F8007EE100AF8EE476A9FED586A73
+S31508021E6C86EE267A534B1B6BC3F3080306EE903A9F
+S31508021E7CF8EE666A9FED536A67EE867A76EEA77A6D
+S31508021E8CF7EE006A77EEA67A27EE277A61E0494BD7
+S31508021E9C1B6813F0200F23D046490A68C2F3C10205
+S31508021EAC464BD34007EE103AF8EE476A07EE100A8D
+S31508021EBCB8EE476A86EE867A0B6BC3F3080306EE10
+S31508021ECC903AF8EE666A9FED3F6A67EE867A76EE88
+S31508021EDCA77AF7EE006A77EEA67A27EE277A38E023
+S31508021EEC07EE100AF8EE476A9FED376A86EE267AEF
+S31508021EFC304B1B6BC3F3080306EE903AF8EE666A90
+S31508021F0C9FED306A67EE867A76EEA77AF7EE006A66
+S31508021F1C77EEA67A27EE277A1BE007EE100AF8EE7A
+S31508021F2C476A9FED276A86EE267A224B1B6BC3F30A
+S31508021F3C080306EE903AF8EE666A9FED226A67EE99
+S31508021F4C867A76EEA77AF7EE006A77EEA67A27EE07
+S31508021F5C277A184B1B6BC3F34623013307EE903AC9
+S31508021F6CF8EE677AC7EE276AFCEEE67A17EE900A5F
+S31508021F7C704707EE100AF8EE476A9FED146A86EE6A
+S31508021F8C267A0C4B1B6BC3F3080306EE903AF8EE53
+S31508021F9C666A9FED0C6A67EE867A76EEA77AF7EE94
+S31508021FAC006A77EEA67A27EE277AD2E708487047B0
+S31508021FBC024870470044025800093D000090D003BD
+S31508021FCC0024744A000000390024744C0024F44A94
+S31508021FDC00127A00002800F0368103469C4A1268E1
+S31508021FEC02F00F028A420CD29948026822F00F02BA
+S31508021FFC0A430260026802F00F028A4201D00120EB
+S3150802200C704770B51A6812F0040F0CD01869914A09
+S3150802201C926902F07002904205D98E4CA26922F09E
+S3150802202C70021043A0611A6812F0080F0CD0586996
+S3150802203C884AD26902F07002904205D9854CE26947
+S3150802204C22F070021043E0611A6812F0100F0CD0DD
+S3150802205C9869804AD26902F4E062904205D97D4CAD
+S3150802206CE26922F4E0621043E0611A6812F0200F6A
+S3150802207C0CD0D869774A126A02F07002904205D9D6
+S3150802208C744C226A22F07002104320621A6812F00B
+S3150802209C020F0CD0D8686F4A926902F00F0290426E
+S315080220AC05D96C4CA26922F00F021043A0611C469A
+S315080220BC0D461B6813F0010F41D0664A936923F447
+S315080220CC7063A1680B4393616368022B0AD0032BD6
+S315080220DC27D0012B2CD05F4A126812F0040F06D1B6
+S315080220EC0120AFE0126812F4003F00F0AE805949A5
+S315080220FC0A6922F0070213430B61FEF731FE064604
+S3150802210C544B1B6903F038036268B3EBC20F16D043
+S3150802211CFEF726FE801B41F288339842F0D903203B
+S3150802212C90E04C4A126812F0007FE0D1012089E057
+S3150802213C484A126812F4807FD9D1012082E02368BA
+S3150802214C13F0020F0CD0E268424B9B6903F00F03A3
+S3150802215C9A4205D23F498B6923F00F031A438A61C7
+S3150802216C3B4B1B6803F00F03AB420CD9384A136876
+S3150802217C23F00F032B431360136803F00F03AB42D0
+S3150802218C01D001205EE0236813F0040F0CD02269FB
+S3150802219C304B9B6903F070039A4205D22D498B6921
+S315080221AC23F070031A438A61236813F0080F0CD0C4
+S315080221BC6269284BDB6903F070039A4205D22549FA
+S315080221CCCB6923F070031A43CA61236813F0100F04
+S315080221DC0CD0A2691F4BDB6903F4E0639A4205D261
+S315080221EC1C49CB6923F4E0631A43CA61236813F0CA
+S315080221FC200F0CD0E269174B1B6A03F070039A4244
+S3150802220C05D214490B6A23F070031A430A62FFF7C4
+S3150802221CEBFD10498B69C3F303230F4AD35C03F016
+S3150802222C1F03D8408B6903F00F03D35C03F01F031B
+S3150802223C20FA03F3094A1360094B1860094B18680C
+S3150802224CFEF72CFD70BD012070470120FAE700BF8E
+S3150802225C0020005200440258FC3C020804000024E8
+S3150802226C000000240C00002408B5FFF7BDFD0B4A3C
+S3150802227C9369C3F303230A49CB5C03F01F0320FAC1
+S3150802228C03F3926902F00F02885C00F01F0023FA2E
+S3150802229C00F0044A1060044A136008BD0044025850
+S315080222ACFC3C0208040000240000002408B5FFF7D1
+S315080222BCDBFF054BDB69C3F30213044AD35C03F059
+S315080222CC1F03D84008BD00BF00440258FC3C020854
+S315080222DC08B5FFF7C9FF054BDB69C3F30223044AAA
+S315080222ECD35C03F01F03D84008BD00BF0044025854
+S315080222FCFC3C0208404B9B6A03F00303032B79D080
+S3150802230C70B50E4604463C4A136823F08063136084
+S3150802231CFEF726FD0546384B1B6813F0006F06D0F0
+S3150802232CFEF71EFD401B0228F5D9032070BD324B61
+S3150802233C9A6A22F47C32216842EA01329A6262680B
+S3150802234C013AC2F30802A1680139490289B20A4361
+S3150802235CE1680139090401F4FE010A4321690139CC
+S3150802236C090601F0FE410A439A63DA6A22F0C002B0
+S3150802237C61690A43DA62DA6A22F02002A1690A431F
+S3150802238CDA62DA6A22F01002DA62D96B1B4A0A405E
+S3150802239CE16942EAC102DA63DA6A42F01002DA62E7
+S315080223ACC6B91A46DB6A43F40023D362124A136887
+S315080223BC43F080631360FEF7D3FC04460E4B1B688E
+S315080223CC13F0006F14D1FEF7CBFC001B0228F5D9CB
+S315080223DC0320ABE7012E05D0074AD36A43F4001350
+S315080223ECD362E3E7044AD36A43F48013D362DDE784
+S315080223FC00209BE701207047004402580700FFFFA4
+S3150802240C404B9B6A03F00303032B79D070B50E4637
+S3150802241C04463C4A136823F080531360FEF7A0FC6B
+S3150802242C0546384B1B6813F0005F06D0FEF798FC7E
+S3150802243C401B0228F5D9032070BD324B9A6A22F04A
+S3150802244C7C72216842EA01529A626268013AC2F3C4
+S3150802245C0802A1680139490289B20A43E1680139BD
+S3150802246C090401F4FE010A4321690139090601F03E
+S3150802247CFE410A431A64DA6A22F4406261690A4323
+S3150802248CDA62DA6A22F40072A1690A43DA62DA6A51
+S3150802249C22F48072DA62596C1B4A0A40E16942EAF2
+S315080224ACC1025A64DA6A42F48072DA62C6B91A4608
+S315080224BCDB6A43F48003D362124A136843F08053EF
+S315080224CC1360FEF74DFC04460E4B1B6813F0005FB7
+S315080224DC14D1FEF745FC001B0228F5D90320ABE7FD
+S315080224EC012E05D0074AD36A43F08073D362E3E719
+S315080224FC044AD36A43F40003D362DDE700209BE760
+S3150802250C01207047004402580700FFFFF8B504463D
+S3150802251C036813F0006F2BD0436EB3F5801F18D0E7
+S3150802252C07D9B3F5001F1DD0B3F5401F2ED10025D0
+S3150802253C06E05BBB934AD36A43F40033D3620025A5
+S3150802254C904A136D23F44013616E0B4313650026F0
+S3150802255C10E002210430FFF7CDFE0546002DEFD020
+S3150802256C2E4607E002212430FFF74AFF0546F5E717
+S3150802257C00263546236813F4807F17D0636D042B27
+S3150802258C32D8DFE803F006242A0B0B00012635465F
+S3150802259CF0E77C4AD36A43F40033D3623DBB794AEB
+S315080225AC136D23F00703616D0B431365236813F44C
+S315080225BC007F33D0A36D802B44D01AD80BB3402B93
+S315080225CC1CD10021201DFFF795FE05461EE00021B1
+S315080225DC201DFFF78FFE0546E0E7002104F12400D3
+S315080225ECFFF70EFF0546D9E701263546DEE72E46E6
+S315080225FCDCE7C02B0AD0B3F5807F07D00126354617
+S3150802260C0CE0604AD36A43F40033D3620DBB5D4ACD
+S3150802261C136D23F4E073A16D0B431365236813F44E
+S3150802262C806F2FD0D4F8A430B3F5800F3ED012D8D1
+S3150802263CD3B1B3F5001F14D10021201DFFF75AFEA2
+S3150802264C054616E0002104F12400FFF7D9FE0546DB
+S3150802265CDCE72E46E2E7B3F5C00F0AD0B3F5000F56
+S3150802266C07D0012635460DE0464AD36A43F40033B1
+S3150802267CD36215BB434A936D23F46003D4F8A410B2
+S3150802268C0B439365236813F4006F2FD0D4F8A83044
+S3150802269CB3F1007F37D012D8D3B1B3F1807F14D1FE
+S315080226AC0021201DFFF726FE054616E0002104F13F
+S315080226BC2400FFF7A5FE0546DBE72E46E2E7B3F153
+S315080226CC407F0AD0B3F1806F07D0012635460DE05C
+S315080226DC2C4AD36A43F40033D362DDB9294A936D83
+S315080226EC23F0E063D4F8A8100B439365236813F020
+S315080226FC007F2AD0A36C102B12D00DD9202B1DD0FB
+S3150802270C302B12D009E0002104F12400FFF778FEE1
+S3150802271C0546E2E72E46E9E73BB10126354614E0C3
+S3150802272C184AD36A43F40033D3626DB9154AD36C8B
+S3150802273C23F03003A16C0B43D36406E00221201D5F
+S3150802274CFFF7D8FD0546F0E72E46236813F4805F9B
+S3150802275C27D0E36DB3F5005F3ED009D8A3B1B3F524
+S3150802276C805F0BD10021201DFFF7C4FD054610E042
+S3150802277CB3F5405F0DD0B3F5804F0AD00126354626
+S3150802278C0FE000BF00440258934AD36A43F400335D
+S3150802279CD36245BB904A136D23F4E043E16D0B43B8
+S315080227AC1365236813F4005F33D0236EB3F5003F29
+S315080227BC27D01AD83BB1B3F5803F1FD10121201D72
+S315080227CCFFF798FD05461DBB834A136D23F4E023D8
+S315080227DC216E0B4313651CE0002104F12400FFF75C
+S315080227EC0FFE0546D5E72E46DBE7B3F5802FEAD072
+S315080227FCB3F5A02FE7D0B3F5403FE4D00126354612
+S3150802280C07E0012104F12400FFF7FAFD0546DAE791
+S3150802281C2E46236813F4804F2CD0D4F8AC30B3F17F
+S3150802282C005F1FD012D83BB1B3F1805F17D10121DB
+S3150802283C201DFFF75FFD0546DDB9674A936D23F048
+S3150802284CE043D4F8AC100B43936513E0B3F1804F15
+S3150802285CF2D0B3F1A04FEFD0B3F1405FECD0012622
+S3150802286C354607E0012104F12400FFF7C9FD0546A8
+S3150802287CE2E72E46236813F4004F1FD0E36EB3F13A
+S3150802288C805F06D0B3F1005F11D03BB10126354605
+S3150802289C14E0514AD36A43F40033D3626DB94E4AF3
+S315080228AC136D23F04053E16E0B43136506E00121C9
+S315080228BC201DFFF71FFD0546F0E72E46236813F089
+S315080228CC807F1ED0636C032B17D8DFE803F0070250
+S315080228DC1007414AD36A43F40033D36285B93E4A98
+S315080228ECD36C23F00303616C0B43D36409E0022116
+S315080228FC201DFFF7FFFC0546F0E70126354600E0EA
+S3150802290C2E46236813F4800F1FD1236813F0010F88
+S3150802291C00F09E80A36F282B00F29680DFE803F066
+S3150802292C84949494949494947F9494949494949470
+S3150802293C8D94949494949494849494949494949452
+S3150802294C84949494949494948400244A136843F437
+S3150802295C80731360FEF704FA0746204B1B6813F4C0
+S3150802296C807F05D1FEF7FCF9C01B6428F5D903252F
+S3150802297C002D50D1184B1B6FD4F8B020534013F4CA
+S3150802298C407F0CD0144B1A6F22F44072196F41F423
+S3150802299C80311967196F21F4803119671A67D4F8CF
+S315080229ACB030B3F5807F1BD0002D36D1D4F8B030B9
+S315080229BC03F44072B2F5407F23D0074A136923F415
+S315080229CC7C53136104490B6FD4F8B020C2F30B0283
+S315080229DC13430B6799E700BF004402580048025894
+S315080229ECFEF7BEF90746AC4B1B6F13F0020FDBD191
+S315080229FCFEF7B6F9C01B41F288339842F3D9032580
+S31508022A0CD2E7A548026922F47C52A44901EA1313B7
+S31508022A1C13430361D6E72E4677E72E4675E701215F
+S31508022A2C201DFFF767FC05468DB99B4A536D23F0AB
+S31508022A3C3803A16F0B4353650AE0012104F1240004
+S31508022A4CFFF7DEFC0546EFE70126354600E02E4683
+S31508022A5C236813F0020F20D0636F052B19D8DFE811
+S31508022A6C03F00803110808080121201DFFF742FC90
+S31508022A7C05468DB9884A536D23F00703616F0B43DC
+S31508022A8C53650AE0012104F12400FFF7B9FC054657
+S31508022A9CEFE70126354600E02E46236813F0040FAD
+S31508022AAC22D0D4F89030052B1AD8DFE803F00803A5
+S31508022ABC120808080121201DFFF71CFC054695B9CA
+S31508022ACC754A936D23F00703D4F890100B4393655C
+S31508022ADC0AE0012104F12400FFF792FC0546EEE711
+S31508022AEC0126354600E02E46236813F0200F2CD01B
+S31508022AFCD4F88C30B3F1005F1FD012D83BB1B3F1C6
+S31508022B0C805F17D10021201DFFF7F4FB0546DDB9BE
+S31508022B1C614A536D23F0E043D4F88C100B4353658A
+S31508022B2C13E0B3F1804FF2D0B3F1A04FEFD0B3F16B
+S31508022B3C405FECD00126354607E0022104F1240059
+S31508022B4CFFF75EFC0546E2E72E46236813F0400FB4
+S31508022B5C2CD0D4F89830B3F5006F1FD012D83BB1ED
+S31508022B6CB3F5806F17D10021201DFFF7C3FB05466D
+S31508022B7CDDB9494A936D23F4E053D4F898100B4304
+S31508022B8C936513E0B3F5805FF2D0B3F5A05FEFD08F
+S31508022B9CB3F5406FECD00126354607E0022104F165
+S31508022BAC2400FFF72DFC0546E2E72E46236813F0B0
+S31508022BBC800F2CD0D4F89C30B3F5804F1FD012D886
+S31508022BCC3BB1B3F5005F17D10021201DFFF792FB2D
+S31508022BDC0546DDB9304A936D23F46043D4F89C104C
+S31508022BEC0B43936513E0B3F5004FF2D0B3F5204FC0
+S31508022BFCEFD0B3F5C04FECD00126354607E00221DB
+S31508022C0C04F12400FFF7FCFB0546E2E72E4623688F
+S31508022C1C13F0080F0CD0D4F88030B3F5805F28D0A7
+S31508022C2C1D4A536D23F44053D4F880100B43536555
+S31508022C3C236813F0100F0CD0D4F89430B3F5807FB8
+S31508022C4C20D0154A936D23F44073D4F894100B4391
+S31508022C5C9365236813F4002F39D0D4F8A030B3F552
+S31508022C6C803F2CD0B3F5003F1FD0CBB10126354699
+S31508022C7C2DE0022104F12400FFF7C2FB0028CFD075
+S31508022C8C0126CDE7022104F12400FFF7B9FB00283F
+S31508022C9CD7D00126D5E700BF00440258CFFFFF0064
+S31508022CAC0021201DFFF726FB05467DB9644A936D64
+S31508022CBC23F44033D4F8A0100B43936507E00221A2
+S31508022CCC04F12400FFF79CFB0546EEE72E46236823
+S31508022CDC13F4802F24D0D4F88430B3F5001F17D000
+S31508022CECB3F5401F0AD0B3F5801F02D0012635462C
+S31508022CFC16E0534AD36A43F40033D3627DB9504A79
+S31508022D0C536D23F44013D4F884100B43536507E030
+S31508022D1C012104F12400FFF773FB0546EEE72E4664
+S31508022D2C236813F4803F14D0E36C2BB1B3F5803FC0
+S31508022D3C23D0012635460CE0414AD36A43F40033C4
+S31508022D4CD36205BB3E4AD36C23F48033E16C0B4346
+S31508022D5CD364236813F0005F17D1236813F4003F7A
+S31508022D6C2DD0E36FB3F5807F1BD017D9B3F5007F4F
+S31508022D7C1CD0B3F5407F12D118E00221201DFFF7B3
+S31508022D8CB9FA0546DDE72E46E3E7022104F12400EB
+S31508022D9CFFF736FB0028E0D00126DEE733B1012621
+S31508022DAC0DE0274AD36A43F40033D362002D3DD192
+S31508022DBC234A536D23F44073E16F0B43536523681F
+S31508022DCC13F4801F06D01E4A136D23F00043216F9D
+S31508022DDC0B431365236813F0805F07D0184A1369EF
+S31508022DEC23F48043D4F8B4100B431361236813F409
+S31508022DFC001F06D0124A136D23F08073A16E0B4383
+S31508022E0C1365236813F0804F09D00D4B1A6922F407
+S31508022E1C00421A611A69D4F8B8100A431A6123686F
+S31508022E2C002B05DB06B101263046F8BD2E46C6E751
+S31508022E3C034AD36C23F04053216D0B43D364F1E759
+S31508022E4C0044025808B5FFF70FFA054B1B6AC3F381
+S31508022E5C0213044AD35C03F01F03D84008BD00BF13
+S31508022E6C00440258FC3C020810B478498C6A8A6AF7
+S31508022E7CC2F30532CB6AC3F30013C96BC1F3CC0197
+S31508022E8C03FB01F3002A00F0DB8004F0030407EECF
+S31508022E9C903AF8EE677A012C66D0FCB1022C00F057
+S31508022EACB28007EE102AB8EE477A9FED696AC6EE2B
+S31508022EBC076A664B9B6BC3F3080307EE103AB8EE28
+S31508022ECC477A9FED646A67EE867A77EE277AB7EECB
+S31508022EDC007A77EE877A66EEA76A61E05B4B1B6827
+S31508022EEC13F0200F23D0594C2168C1F3C1015A4B58
+S31508022EFCCB4007EE103AB8EE477A06EE902AB8EEB1
+S31508022F0C666AC7EE066AA36BC3F3080307EE103AA2
+S31508022F1CB8EE477A9FED4F6A67EE867A77EE277A8E
+S31508022F2CB7EE007A77EE877A66EEA76A38E007EE8E
+S31508022F3C102AB8EE477A9FED496AC6EE076A434BE2
+S31508022F4C9B6BC3F3080307EE103AB8EE477A9FED6C
+S31508022F5C416A67EE867A77EE277AB7EE007A77EECB
+S31508022F6C877A66EEA76A1BE007EE102AB8EE477A4E
+S31508022F7C9FED376AC6EE076A344B9B6BC3F308039D
+S31508022F8C07EE103AB8EE477A9FED326A67EE867A02
+S31508022F9C77EE277AB7EE007A77EE877A66EEA76A25
+S31508022FAC2A4A936BC3F3462307EE103AB8EE477ACE
+S31508022FBCB7EE006A37EE067AC6EE877AFCEEE77A41
+S31508022FCCC0ED007A936BC3F3064307EE103AB8EEDC
+S31508022FDC477A37EE067AC6EE877AFCEEE77AC0EDC2
+S31508022FEC017A936BC3F3066307EE903AF8EE677AA7
+S31508022FFC77EE867A86EEA77ABCEEC77A80ED027AE7
+S3150802300C5DF8044B704707EE102AB8EE477A9FED27
+S3150802301C146AC6EE076A0D4B9B6BC3F3080307EEDD
+S3150802302C103AB8EE477A9FED0B6A67EE867A77EE18
+S3150802303C277AB7EE007A77EE877A66EEA76AAFE753
+S3150802304C0023036043608360DAE700BF004402583A
+S3150802305C0024744A000000390090D0030024744CF2
+S3150802306C0024F44A10B478498C6A8A6AC2F3055267
+S3150802307CCB6AC3F30023496CC1F3CC0103FB01F3FE
+S3150802308C002A00F0DB8004F0030407EE903AF8EE0F
+S3150802309C677A012C66D0FCB1022C00F0B28007EEDE
+S315080230AC102AB8EE477A9FED696AC6EE076A664B2E
+S315080230BC1B6CC3F3080307EE103AB8EE477A9FED7A
+S315080230CC646A67EE867A77EE277AB7EE007A77EE37
+S315080230DC877A66EEA76A61E05B4B1B6813F0200FD2
+S315080230EC23D0594C2168C1F3C1015A4BCB4007EE88
+S315080230FC103AB8EE477A06EE902AB8EE666AC7EE2A
+S3150802310C066A236CC3F3080307EE103AB8EE477A3D
+S3150802311C9FED4F6A67EE867A77EE277AB7EE007AD4
+S3150802312C77EE877A66EEA76A38E007EE102AB8EECB
+S3150802313C477A9FED496AC6EE076A434B1B6CC3F383
+S3150802314C080307EE103AB8EE477A9FED416A67EE26
+S3150802315C867A77EE277AB7EE007A77EE877A66EE74
+S3150802316CA76A1BE007EE102AB8EE477A9FED376A74
+S3150802317CC6EE076A344B1B6CC3F3080307EE103A08
+S3150802318CB8EE477A9FED326A67EE867A77EE277A39
+S3150802319CB7EE007A77EE877A66EEA76A2A4A136C36
+S315080231ACC3F3462307EE103AB8EE477AB7EE006A2F
+S315080231BC37EE067AC6EE877AFCEEE77AC0ED007A27
+S315080231CC136CC3F3064307EE103AB8EE477A37EE9A
+S315080231DC067AC6EE877AFCEEE77AC0ED017A136CAC
+S315080231ECC3F3066307EE903AF8EE677A77EE867AB9
+S315080231FC86EEA77ABCEEC77A80ED027A5DF8044BA6
+S3150802320C704707EE102AB8EE477A9FED146AC6EE97
+S3150802321C076A0D4B1B6CC3F3080307EE103AB8EE9C
+S3150802322C477A9FED0B6A67EE867A77EE277AB7EEC0
+S3150802323C007A77EE877A66EEA76AAFE70023036011
+S3150802324C43608360DAE700BF004402580024744ADC
+S3150802325C000000390090D0030024744C0024F44A70
+S3150802326C2DE9F04387B00446016883680269134363
+S3150802327C42691343C2691343426E13430868884A68
+S3150802328C02401A430A602268536823F44053E168E1
+S3150802329C0B435360A1692268824B9A4201D0236A76
+S315080232AC19439068804B03400B4393602268D36A98
+S315080232BC23F00F03616A0B43D36223687B4A93425A
+S315080232CC1FD07B4A934259D07A4A934270D07A4A93
+S315080232DC934200F08780794A934200F09D80784A9F
+S315080232EC934200F0B380774A934200F0F180764A13
+S315080232FC934200F004816B4A934200F017818022B4
+S3150802330C2DE1724A526D02F03802282A34D8DFE8C7
+S3150802331C12F0290033003300330033003300330034
+S3150802332C33002501330033003300330033003300F6
+S3150802333C33002B00330033003300330033003300E1
+S3150802334C33002D00330033003300330033003300CF
+S3150802335C33002F00330033003300330033003300BD
+S3150802336C330031000122FAE00822F8E01022F6E0D6
+S3150802337C2022F4E04022F2E08022F0E0534A526D19
+S3150802338C02F00702052A11D8DFE812F00600370107
+S3150802339C08000A000C000E000022E0E00822DEE01B
+S315080233AC1022DCE02022DAE04022D8E08022D6E0A5
+S315080233BC464A526D02F00702052A11D8DFE812F0C6
+S315080233CC06001F0108000A000C000E000022C6E0C7
+S315080233DC0822C4E01022C2E02022C0E04022BEE04D
+S315080233EC8022BCE0394A526D02F00702052A11D82E
+S315080233FCDFE812F00600070108000A000C000E00AE
+S3150802340C0022ACE00822AAE01022A8E02022A6E0BC
+S3150802341C4022A4E08022A2E02C4A526D02F0070256
+S3150802342C052A11D8DFE812F00600EF0008000A0098
+S3150802343C0C000E00002292E0082290E010228EE088
+S3150802344C20228CE040228AE0802288E01F4A526DB4
+S3150802345C02F03802282A20D8DFE802F0151F1F1FAF
+S3150802346C1F1F1F1FD71F1F1F1F1F1F1F171F1F1FA0
+S3150802347C1F1F1F1F191F1F1F1F1F1F1F1B1F1F1F4A
+S3150802348C1F1F1F1F1D00012269E0082267E0102278
+S3150802349C65E0202263E0402261E080225FE000BF03
+S315080234ACF369FFCF000C0058FFF4FF11001001401E
+S315080234BC0044004000480040004C004000500040C8
+S315080234CC0014014000780040007C00400044025879
+S315080234DC824A526D02F00702052A0ED8DFE802F07C
+S315080234EC03970507090B002239E0082237E0102258
+S315080234FC35E0202233E0402231E080222FE0774A61
+S3150802350C526D02F00702052A0ED8DFE802F0038292
+S3150802351C0507090B002222E0082220E010221EE0F1
+S3150802352C20221CE040221AE0802218E002F50E3214
+S3150802353C926D02F00702052A0ED8DFE802F0036C38
+S3150802354C0507090B02220AE0082208E0102206E007
+S3150802355C202204E0402202E0802200E00422604994
+S3150802356C8B425AD0E369B3F5004F00F0C380402A68
+S3150802357C00F27981DFE812F027014B017701770116
+S3150802358C4E017701770177015301770177017701AC
+S3150802359C770177017701770158017701770177016E
+S315080235AC770177017701770177017701770177013F
+S315080235BC7701770177017701250177017701770181
 S315080235CC770177017701770177017701770177011F
 S315080235DC770177017701770177017701770177010F
-S315080235EC770177017701770164010422AFE7042298
-S315080235FCADE70422ABE70422A9E70422A7E70422D3
-S3150802360CA5E70422A3E70422A1E7082A48D007D98A
-S3150802361C202A0ED0402A54D0102A46D00120E3E0A4
-S3150802362C022A08D0042AF9D103A8FFF715FC049834
-S3150802363C03E0284804E0FFF7FDFB002800F0FD80B4
-S3150802364C626A254B33F81220B0FBF2F3656805EB78
-S3150802365C4501994200F2F380B3EB053F00F2F18083
-S3150802366C4FF0000892B200234146FCF731FE0F02D6
-S3150802367C47EA1067060268082A46434616EB00080C
-S3150802368C47F1000940464946FCF722FEA0F540726E
-S3150802369C124B9A4200F2D7802368D8600020A3E026
-S315080236AC6846FFF7D7FC0198C7E7084B1B6813F067
-S315080236BC200F09D0054B1B68C3F3C1030848D84031
-S315080236CCBBE74FF40040BBE70548B9E7004402588C
-S315080236DC000C005800093D000C3D0208FFFC0F00C7
-S315080236EC0090D003402A00F2B080DFE802F02344AF
-S315080236FCAEAE47AEAEAE4CAEAEAEAEAEAEAE51AEF4
-S3150802370CAEAEAEAEAEAEAEAEAEAEAEAEAEAE21AE4A
-S3150802371CAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAD
-S3150802372CAEAEAEAEAEAEAEAEAEAEAEAEAEAE5D009C
-S3150802373C4C4804E0FEF7B2FD002800F08880626A65
-S3150802374C494B33F81230B0FBF3F06268530803EBBB
-S3150802375C4003B3FBF2F39BB2A3F110014FF6EF72DF
-S3150802376C914276D823F00F02C3F34203134322681D
-S3150802377CD360002038E0FEF7A3FDDDE703A8FFF7C8
-S3150802378C6BFB0498D8E76846FFF764FC0198D3E705
-S3150802379C364B1B6813F0200F09D0344B1B68C3F346
-S315080237ACC1033348D840C7E74FF40040C7E730484F
-S315080237BCC5E72C4803E0FEF771FD00284DD0626A76
-S315080237CC294B33F81230B0FBF3F0636800EB530065
-S315080237DCB0FBF3F080B2A0F110024FF6EF739A42E7
-S315080237EC3DD82368D86000200123A4F86A30A4F8CF
-S315080237FC68300023E366236707B0BDE8F083FEF75B
-S3150802380C5FFDDAE703A8FFF727FB0498D5E76846B6
-S3150802381CFFF720FC0198D0E7144B1B6813F0200F16
-S3150802382C09D0124B1B68C3F3C1031148D840C4E72D
-S3150802383C4FF40040C3E70E48C1E70020D4E7012045
-S3150802384CD2E70120D0E70120CEE70120CCE7002001
-S3150802385CCAE70120C8E70120C6E70020C4E7012011
-S3150802386CC2E700BF00093D000C3D0208004402589D
-S3150802387C0090D003836A13F0010F06D002685368CE
-S3150802388C23F40033C16A0B435360836A13F0020FA5
-S3150802389C06D00268536823F48033016B0B435360DA
-S315080238AC836A13F0040F06D00268536823F4802344
-S315080238BC416B0B435360836A13F0080F06D00268F8
-S315080238CC536823F40043816B0B435360836A13F0EA
-S315080238DC100F06D00268936823F48053C16B0B430E
-S315080238EC9360836A13F0200F06D00268936823F458
-S315080238FC0053016C0B439360836A13F0400F0AD092
-S3150802390C0268536823F48013416C0B435360436C6F
-S3150802391CB3F5801F0BD0836A13F0800F06D00268AA
-S3150802392C536823F40023C16C0B4353607047026837
-S3150802393C536823F4C003816C0B435360EBE72DE900
-S3150802394CF04104460F4616469846069D2368DB69DF
-S3150802395C37EA03030CBF01230023B3423FD1B5F167
-S3150802396CFF3FF3D0FDF7F6F9A0EB0800A84222D8E0
-S3150802397C0DB323681A6812F0040FE7D0DA6912F449
-S3150802398C006FE3D04FF400621A622268136823F4BC
-S3150802399CD07313602268936823F001039360202383
-S315080239ACC4F88030C4F88430C4F88830002384F80C
-S315080239BC7C30032014E02268136823F4D073136056
-S315080239CC2268936823F0010393602023C4F880309D
-S315080239DCC4F88430002384F87C30032000E00020ED
-S315080239ECBDE8F0812DE9F04383B01E46D0F8843049
-S315080239FC202B40F0838004460D469046B2FA82F399
-S31508023A0C5B09002908BF0123002B7BD190F87C3077
-S31508023A1C012B79D0012380F87C300023C0F888303A
-S31508023A2C2223C0F88430FDF795F90746A4F85C8082
-S31508023A3CA4F85E80A368B3F5805F06D0A3B92269A1
-S31508023A4C72B9FF22A4F8602014E0226922B940F266
-S31508023A5CFF12A4F860200DE0FF22A4F8602009E00A
-S31508023A6C7F22A4F8602005E0B3F1805F0DD0002216
-S31508023A7CA4F86020B4F86080B3F5805F0FD04FF0DD
-S31508023A8C0009002384F87C301DE022691AB97F22CA
-S31508023A9CA4F86020EEE73F22A4F86020EAE723693F
-S31508023AAC13B14FF00009ECE7A9460025E9E72368AC
-S31508023ABC5B6A08EA030329F8023BB4F85E30013B59
-S31508023ACC9BB2A4F85E30B4F85E309BB28BB100960A
-S31508023ADC3B46002220212046FFF731FFB0B9002DC4
-S31508023AECE5D023685A6A5FFA88F3134005F8013B56
-S31508023AFCE3E72023C4F88430002000E0022003B058
-S31508023B0CBDE8F0830120FAE70220F8E70320F6E77E
-S31508023B1C30B583B004460023C0F88830FDF71AF98D
-S31508023B2C054623681B6813F0080F0ED123681B6819
-S31508023B3C13F0040F17D12023C4F88030C4F884304C
-S31508023B4C002084F87C0003B030BD6FF07E430093EE
-S31508023B5C034600224FF400112046FFF7F0FE002818
-S31508023B6CE4D00320EFE76FF07E4300932B46002246
-S31508023B7C4FF480012046FFF7E2FE0028DBD0032033
-S31508023B8CE1E778B310B50446D0F880300BB324239A
-S31508023B9CC4F880302268136823F0010313602046A8
-S31508023BACFFF756FB012813D0A36ABBB922685368E0
-S31508023BBC23F4904353602268936823F02A03936094
-S31508023BCC2268136843F0010313602046FFF7A0FF2F
-S31508023BDC10BD80F87C30FCF781FFD8E72046FFF74A
-S31508023BEC49FEE3E70120704770B50D4E0D4CA41B38
-S31508023BFCA4100025A54209D10B4E0C4C00F02CF84A
-S31508023C0CA41BA4100025A54205D170BD56F8253073
-S31508023C1C98470135EEE756F8253098470135F2E70D
-S31508023C2C2C3D02082C3D02082C3D0208303D0208A8
-S31508023C3C10B5431E0A44914200D110BD11F8014B2E
-S31508023C4C03F8014FF7E702440346934200D1704743
-S31508023C5C03F8011BF9E70000F8B500BFF8BC08BC6D
-S31508023C6C9E467047F8B500BFF8BC08BC9E4670471E
-S31508023C7C0000000000000000000000000000000028
-S31508023C8C0000000001000000020000000300000012
-S31508023C9C04000000000000000500000000000000FF
-S31508023CAC00000000000000000600000000000000F2
-S31508023CBC00000000000000000700000005020602D2
-S31508023CCC060307030803090309040A040B040C0474
-S31508023CDC0C050D050E050F050F0610061007100824
-S31508023CEC0000000001020304010203040607080986
-S31508023CFC0001020304050607080C101418203040AC
-S31508023D0C010002000400060008000A000C0010005C
-S30D08023D1C2000400080000001AE
-S30D08023D24E8C5FF7F010000005B
-S30908023D2CC1020208B6
-S30908023D309D020208D6
-S31508023D340090D0030090D003010000001000000098
-S70508020C499B
+S315080235EC77017701770177017701770177017701FF
+S315080235FC770177017701770164010422AFE7042288
+S3150802360CADE70422ABE70422A9E70422A7E70422C2
+S3150802361CA5E70422A3E70422A1E7082A48D007D97A
+S3150802362C202A0ED0402A54D0102A46D00120E3E094
+S3150802363C022A08D0042AF9D103A8FFF715FC049824
+S3150802364C03E0284804E0FFF7FDFB002800F0FD80A4
+S3150802365C626A254B33F81220B0FBF2F3656805EB68
+S3150802366C4501994200F2F380B3EB053F00F2F18073
+S3150802367C4FF0000892B200234146FCF729FE0F02CE
+S3150802368C47EA1067060268082A46434616EB0008FC
+S3150802369C47F1000940464946FCF71AFEA0F5407266
+S315080236AC124B9A4200F2D7802368D8600020A3E016
+S315080236BC6846FFF7D7FC0198C7E7084B1B6813F057
+S315080236CC200F09D0054B1B68C3F3C1030848D84021
+S315080236DCBBE74FF40040BBE70548B9E7004402587C
+S315080236EC000C005800093D001C3D0208FFFC0F00A7
+S315080236FC0090D003402A00F2B080DFE802F023449F
+S3150802370CAEAE47AEAEAE4CAEAEAEAEAEAEAE51AEE3
+S3150802371CAEAEAEAEAEAEAEAEAEAEAEAEAEAE21AE3A
+S3150802372CAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAE9D
+S3150802373CAEAEAEAEAEAEAEAEAEAEAEAEAEAE5D008C
+S3150802374C4C4804E0FEF7B2FD002800F08880626A55
+S3150802375C494B33F81230B0FBF3F06268530803EBAB
+S3150802376C4003B3FBF2F39BB2A3F110014FF6EF72CF
+S3150802377C914276D823F00F02C3F34203134322680D
+S3150802378CD360002038E0FEF7A3FDDDE703A8FFF7B8
+S3150802379C6BFB0498D8E76846FFF764FC0198D3E7F5
+S315080237AC364B1B6813F0200F09D0344B1B68C3F336
+S315080237BCC1033348D840C7E74FF40040C7E730483F
+S315080237CCC5E72C4803E0FEF771FD00284DD0626A66
+S315080237DC294B33F81230B0FBF3F0636800EB530055
+S315080237ECB0FBF3F080B2A0F110024FF6EF739A42D7
+S315080237FC3DD82368D86000200123A4F86A30A4F8BF
+S3150802380C68300023E366236707B0BDE8F083FEF74A
+S3150802381C5FFDDAE703A8FFF727FB0498D5E76846A6
+S3150802382CFFF720FC0198D0E7144B1B6813F0200F06
+S3150802383C09D0124B1B68C3F3C1031148D840C4E71D
+S3150802384C4FF40040C3E70E48C1E70020D4E7012035
+S3150802385CD2E70120D0E70120CEE70120CCE70020F1
+S3150802386CCAE70120C8E70120C6E70020C4E7012001
+S3150802387CC2E700BF00093D001C3D0208004402587D
+S3150802388C0090D003836A13F0010F06D002685368BE
+S3150802389C23F40033C16A0B435360836A13F0020F95
+S315080238AC06D00268536823F48033016B0B435360CA
+S315080238BC836A13F0040F06D00268536823F4802334
+S315080238CC416B0B435360836A13F0080F06D00268E8
+S315080238DC536823F40043816B0B435360836A13F0DA
+S315080238EC100F06D00268936823F48053C16B0B43FE
+S315080238FC9360836A13F0200F06D00268936823F448
+S3150802390C0053016C0B439360836A13F0400F0AD081
+S3150802391C0268536823F48013416C0B435360436C5F
+S3150802392CB3F5801F0BD0836A13F0800F06D002689A
+S3150802393C536823F40023C16C0B4353607047026827
+S3150802394C536823F4C003816C0B435360EBE72DE9F0
+S3150802395CF04104460F4616469846069D2368DB69CF
+S3150802396C37EA03030CBF01230023B3423FD1B5F157
+S3150802397CFF3FF3D0FDF7F4F9A0EB0800A84222D8D2
+S3150802398C0DB323681A6812F0040FE7D0DA6912F439
+S3150802399C006FE3D04FF400621A622268136823F4AC
+S315080239ACD07313602268936823F001039360202373
+S315080239BCC4F88030C4F88430C4F88830002384F8FC
+S315080239CC7C30032014E02268136823F4D073136046
+S315080239DC2268936823F0010393602023C4F880308D
+S315080239ECC4F88430002384F87C30032000E00020DD
+S315080239FCBDE8F0812DE9F04383B01E46D0F8843039
+S31508023A0C202B40F0838004460D469046B2FA82F388
+S31508023A1C5B09002908BF0123002B7BD190F87C3067
+S31508023A2C012B79D0012380F87C300023C0F888302A
+S31508023A3C2223C0F88430FDF793F90746A4F85C8074
+S31508023A4CA4F85E80A368B3F5805F06D0A3B9226991
+S31508023A5C72B9FF22A4F8602014E0226922B940F256
+S31508023A6CFF12A4F860200DE0FF22A4F8602009E0FA
+S31508023A7C7F22A4F8602005E0B3F1805F0DD0002206
+S31508023A8CA4F86020B4F86080B3F5805F0FD04FF0CD
+S31508023A9C0009002384F87C301DE022691AB97F22BA
+S31508023AACA4F86020EEE73F22A4F86020EAE723692F
+S31508023ABC13B14FF00009ECE7A9460025E9E723689C
+S31508023ACC5B6A08EA030329F8023BB4F85E30013B49
+S31508023ADC9BB2A4F85E30B4F85E309BB28BB10096FA
+S31508023AEC3B46002220212046FFF731FFB0B9002DB4
+S31508023AFCE5D023685A6A5FFA88F3134005F8013B46
+S31508023B0CE3E72023C4F88430002000E0022003B047
+S31508023B1CBDE8F0830120FAE70220F8E70320F6E76E
+S31508023B2C30B583B004460023C0F88830FDF718F97F
+S31508023B3C054623681B6813F0080F0ED123681B6809
+S31508023B4C13F0040F17D12023C4F88030C4F884303C
+S31508023B5C002084F87C0003B030BD6FF07E430093DE
+S31508023B6C034600224FF400112046FFF7F0FE002808
+S31508023B7CE4D00320EFE76FF07E4300932B46002236
+S31508023B8C4FF480012046FFF7E2FE0028DBD0032023
+S31508023B9CE1E778B310B50446D0F880300BB324238A
+S31508023BACC4F880302268136823F001031360204698
+S31508023BBCFFF756FB012813D0A36ABBB922685368D0
+S31508023BCC23F4904353602268936823F02A03936084
+S31508023BDC2268136843F0010313602046FFF7A0FF1F
+S31508023BEC10BD80F87C30FCF77FFFD8E72046FFF73C
+S31508023BFC49FEE3E70120704770B50D4E0D4CA41B28
+S31508023C0CA4100025A54209D10B4E0C4C00F02CF839
+S31508023C1CA41BA4100025A54205D170BD56F8253063
+S31508023C2C98470135EEE756F8253098470135F2E7FD
+S31508023C3C3C3D02083C3D02083C3D0208403D020858
+S31508023C4C10B5431E0A44914200D110BD11F8014B1E
+S31508023C5C03F8014FF7E702440346934200D1704733
+S31508023C6C03F8011BF9E70000F8B500BFF8BC08BC5D
+S31508023C7C9E467047F8B500BFF8BC08BC9E4670470E
+S31508023C8C0000000000000000000000000000000018
+S31508023C9C0000000001000000020000000300000002
+S31508023CAC04000000000000000500000000000000EF
+S31508023CBC00000000000000000600000000000000E2
+S31508023CCC00000000000000000700000005020602C2
+S31508023CDC060307030803090309040A040B040C0464
+S31508023CEC0C050D050E050F050F0610061007100814
+S31508023CFC0000000001020304010203040607080976
+S31508023D0C0001020304050607080C1014182030409B
+S31508023D1C010002000400060008000A000C0010004C
+S30D08023D2C20004000800000019E
+S30D08023D34D8C5FF7F010000005B
+S30908023D3CC1020208A6
+S30908023D409D020208C6
+S31508023D440090D0030090D003010000001000000088
+S70508020C558F
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_GCC/Boot/bin/openblt_stm32h743.elf b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_GCC/Boot/bin/openblt_stm32h743.elf
index 09ccd1bc..ce8d2a1e 100755
Binary files a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_GCC/Boot/bin/openblt_stm32h743.elf and b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_GCC/Boot/bin/openblt_stm32h743.elf differ
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_GCC/Boot/bin/openblt_stm32h743.srec b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_GCC/Boot/bin/openblt_stm32h743.srec
index 3ec43eab..50459f8c 100755
--- a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_GCC/Boot/bin/openblt_stm32h743.srec
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_GCC/Boot/bin/openblt_stm32h743.srec
@@ -2,7 +2,7 @@ S01D000062696E2F6F70656E626C745F73746D3332683734332E737265638D
 S3150800000000000220050400085504000855040008ED
 S3150800001055040008550400085504000800000000AF
 S315080000200000000000000000000000005504000861
-S31508000030550400080000000055040008715C00081B
+S31508000030550400080000000055040008550400088F
 S31508000040550400085504000855040008550400081E
 S31508000050550400085504000855040008550400080E
 S3150800006055040008550400085504000855040008FE
@@ -43,18 +43,18 @@ S31508000280550400085504000855040008000000003D
 S30D080002900000000055040008F7
 S3150800029810B5054C237833B9044B13B10448AFF3AA
 S315080002A800800123237010BDF00400200000000020
-S315080002B8985C000808B5034B1BB103490348AFF31C
-S315080002C8008008BD00000000F4040020985C0008BF
+S315080002B8B05C000808B5034B1BB103490348AFF304
+S315080002C8008008BD00000000F4040020B05C0008A7
 S315080002D870B50D4E0D4D761BB61006D000240134A8
 S315080002E855F8043B9847A642F9D1094E094D761B9D
-S315080002F805F0CEFCB61006D00024013455F8043BA8
-S315080003089847A642F9D170BD105F0008105F00082B
-S31508000318185F0008105F0008024B13B1024800F086
+S315080002F805F0DAFCB61006D00024013455F8043B9C
+S315080003089847A642F9D170BD285F0008285F0008FB
+S31508000318305F0008285F0008024B13B1024800F056
 S3150800032805B870470000000041030008002301468D
 S315080003381A46184600F01EB838B50A4C0A4D641B0A
 S31508000348A4100AD004F18043013B05EB8305013C60
 S3150800035855F804399847002CF9D1BDE8384005F016
-S315080003689DBC00BF1C5F0008185F0008704700BFE7
+S31508000368A9BC00BF345F0008305F0008704700BFAB
 S31508000378704700BF2DE9F0411E4C05462068904697
 S315080003881F460E46FFF7F2FF1B4B1A68D2F848318C
 S3150800039833B35A6820681F2A27DC4DB9911C0132E5
@@ -63,1543 +63,1544 @@ S315080003B803EB82010124C1F8888004FA02FED3F807
 S315080003C88841022D44EA0E0CC3F888C1C1F80871A1
 S315080003D8E4D1D3F88C114EEA0104C3F88C41DDE761
 S315080003E802F5A673C2F84831D3E7FFF7C1FF4FF005
-S315080003F8FF30DBE728040020FC5C0008DFF834D06F
+S315080003F8FF30DBE728040020145D0008DFF834D056
 S31508000408002103E00C4B5B58435004310B480C4B56
 S3150800041842189A42F6D30B4A02E0002342F8043BF4
-S31508000428094B9A42F9D303F09FFDFFF751FF00F0F5
-S3150800043843FA7047000002201C5F000800000020ED
-S31508000448F0040020F004002034190020FEE708B55F
-S3150800045800F57171D0F8040403F00DFE08BD08B55F
-S31508000468C1EBC10293000344D3F80822D0F8040468
-S3150800047803F02FFE08BD08B5C1EBC102930003447B
-S315080004889A6CD0F8040403F06EFE08BD08B5D0F8D7
-S31508000498040403F013FF08BD10B50446C3684BB13E
-S315080004A8022B01D1012106E09121074804F0BEFD7F
-S315080004B8012100E00021D4F8040403F0E8FED4F88A
-S315080004C8040403F0BCFE10BD005D000810B5044620
-S315080004D8D0F8040403F0DEFE2268D2F8003E43F0A2
-S315080004E80103C2F8003E236A23B1044A136943F09C
-S315080004F80603136100F000FB10BD00BF00ED00E025
-S3150800050810B5044600F0F9FAD4F8040403F0CBFE53
-S3150800051810BD08B5D0F8040403F0E0FE08BD08B518
-S31508000528D0F8040403F0D8FE08BD10B50446012027
-S3150800053800F0E1FAD4F8040403F0D2FE10BD10B5B1
-S315080005480446002000F0D7FAD4F8040403F0CAFEDB
-S3150800055810BD000003780BB10020704710B503469C
-S315080005681748C0F80434C3F8C002164B03600923B9
-S3150800057843600222C2600023036182610122C261CC
-S31508000588036243628362C362036301F00FFF80B9A3
-S315080005980B4C8021204600F0DFFB40220021204634
-S315080005A800F0B6FB80220121204600F0B1FB0020AE
-S315080005B810BD4FF49371044804F038FDE8E700BF0E
-S315080005C8D012002000000840005D0008D0F8C032AC
-S315080005D811F0800F08D101F07F01C1EBC1018A0033
-S315080005E8134493F8FE01704701F07F01C1EBC1017E
-S315080005F88A00134493F83E00704708B5D0F8C0023D
-S3150800060802F0C4FB08BD022807D8DFE800F0020696
-S31508000618040000207047012070470220704708B57B
-S31508000628D0F8C00201F09CFFFFF7EDFF08BD08B53A
-S31508000638D0F8C00201F053FFFFF7E5FF08BD08B57B
-S31508000648D0F8C00201F06CFFFFF7DDFF08BD10B552
-S315080006581C4613462246D0F8C00202F0F3FAFFF702
-S31508000668D2FF10BD08B5D0F8C00202F02BFBFFF781
-S31508000678CAFF08BD08B5D0F8C00202F0BAFBFFF7F2
-S31508000688C2FF08BD08B5D0F8C00202F0F3FBFFF7B1
-S31508000698BAFF08BD08B5D0F8C00202F0BFFAFFF7DE
-S315080006A8B2FF08BD08B5D0F8C00202F078FBFFF71C
-S315080006B8AAFF08BD08B5D0F8C00202F039FBFFF753
-S315080006C8A2FF08BD014B1880704700BF0C05002023
-S315080006D808B505F0BDFA0E4B1B6898420FD30D4BAB
-S315080006E81B786BB90B4B01221A700B4B80229A6147
-S315080006F805F0AEFA094B1B881844054B186008BD67
-S31508000708044B00221A70044B4FF400029A61EFE773
-S31508000718100500200E050020000402580C050020CC
-S31508000728024B4FF400029A61704700BF0004025852
-S3150800073808B5574A136823F00F0343F004031360F8
-S31508000748136803F00F03042B40F09C80514AD368C2
-S3150800075823F0070343F00203D360936943F4404345
-S3150800076893614D4B1A6842F480221A601A6842F45B
-S3150800077880321A60484B1B6813F4003FFAD0464B80
-S315080007889A6A22F0030242F002029A62DA6A42F48C
-S315080007988032DA62DA6A42F40032DA62DA6A22F017
-S315080007A80C0242F00402DA62DA6A22F00202DA621B
-S315080007B89A6A22F47C7242F040029A621A6B3749A6
-S315080007C8114040F2DF120A431A631A6B22F47E427A
-S315080007D842F400721A631A6B22F4FE0242F4981263
-S315080007E81A631A6B22F0FE4242F080721A631A687C
-S315080007F842F080721A60284B1B6813F0007FFAD003
-S31508000808254B9A6922F00F0242F008029A611A6982
-S3150800081822F0070242F003021A619A6922F470620A
-S315080008289A619A6922F00F0242F008029A61DA6917
-S3150800083822F0700242F04002DA61DA6922F4E062D4
-S3150800084842F48062DA619A6922F0700242F0400244
-S315080008589A611A6A22F0700242F040021A62104936
-S315080008680A6822F007020A601A6D22F040521A65D1
-S315080008785A6D22F4401242F480125A65094800F06B
-S3150800088825FC08BD6721084804F0D0FB5EE700BFD1
-S3150800089800200052004802580044025800FEFFFF94
-S315080008A85444025800389C1C0C5D000808B500F032
-S315080008B8C5FAFFF73DFF08BD08B5FFF7F7FF04F0CF
-S315080008C84BFB04F057FBFCE72DE9F0418EB0514C81
-S315080008D8D4F8F43043F00203C4F8F430D4F8F4300A
-S315080008E803F002030793079BD4F8E03043F00103AB
-S315080008F8C4F8E030D4F8E03003F001030693069B09
-S31508000908D4F8E03043F00203C4F8E030D4F8E03015
-S3150800091803F002030593059BD4F8E03043F004037B
-S31508000928C4F8E030D4F8E03003F004030493049BD9
-S31508000938D4F8E03043F00803C4F8E030D4F8E030DF
-S3150800094803F008030393039BD4F8E83043F48023A1
-S31508000958C4F8E830D4F8E83003F480230293029BFD
-S31508000968D4F8EC3043F48073C4F8EC30D4F8EC309F
-S3150800097803F480730193019B802308930123099349
-S3150800098800250A950B950C95234F08A9384601F0BA
-S315080009983DFC4FF40053089309950C9508A91F4880
-S315080009A801F034FC4FF44078CDF8208002260996E9
-S315080009B80A950B950C9507230D9308A9184801F075
-S315080009C825FCCDF8208009960A960B950C950923DF
-S315080009D80D9308A9384601F019FC4FF4C05308933B
-S315080009E8099603230A930B950C950A230D9308A9D0
-S315080009F80C4801F00BFCD4F8D83043F00063C4F86F
-S31508000A08D830D4F8D83003F000630093009B0EB0B2
-S31508000A18BDE8F0810044025800040258000802584C
-S31508000A28000C02580000025810B502F075FE214C59
-S31508000A384FF40003A361204801F0FCFA1F4801F0AF
-S31508000A48F9FA204601F0F6FA1D4801F0F3FA1D4BAB
-S31508000A58D3F8D82022F00062C3F8D820D3F8EC20BF
-S31508000A6822F48072C3F8EC20D3F8E82022F4802216
-S31508000A78C3F8E820D3F8E02022F00802C3F8E020FB
-S31508000A88D3F8E02022F00402C3F8E020D3F8E020E7
-S31508000A9822F00202C3F8E020D3F8E02022F001028F
-S31508000AA8C3F8E020D3F8F42022F00202C3F8F420B1
-S31508000AB810BD00BF00040258000C0258000802586E
-S31508000AC8000002580044025808B5054B1B6913F480
-S31508000AD8005F03D1FFF724FE012008BD0020FCE7CC
-S31508000AE80008025808B56420FFF7ECFD08BD08B5EC
-S31508000AF8FFF7EEFD08BD704770477047202303804F
-S31508000B0800487047640400200A2303800048704799
-S31508000B188404002008B590F89C32032B01D00020E5
-S31508000B2808BD04F02FFCFAE708B504F02BFC0020F2
-S31508000B3808BD08B5084604F059FC002008BD0000A1
-S31508000B4808B50B7813F0600F06D14B780A2B14D02A
-S31508000B580B2B17D0062B01D0002008BD4B881B0A83
-S31508000B68212B04D00B49172203F028FFF4E7CA887B
-S31508000B78172A28BF17220849F6E70122074903F06A
-S31508000B881DFFE9E78B7813B9044A1360E4E703F015
-S31508000B98DBFBE1E76D04002076040020140500203D
-S31508000BA810B504468121FFF75DFD01212046FFF7B0
-S31508000BB859FD002010BD000010B504464023022246
-S31508000BC88121FFF744FD4023022201212046FFF731
-S31508000BD83EFD4023034A01212046FFF76BFD00200E
-S31508000BE810BD00BFD816002000487047D816002048
-S31508000BF812230B8000487047AC04002004230B809E
-S31508000C0800487047C00400200023934216D230B427
-S31508000C180BE0373401F8134000015C000134002565
-S31508000C280D550133DBB2934206D2040F092CF0D8CE
-S31508000C38303401F81340EFE730BC704770470000BE
-S31508000C4838B50A4B186804331C6804331B68C0187F
-S31508000C5800D138BD064D0822A91CFFF7D5FF042286
-S31508000C6805F112012046FFF7CFFFF2E700E8F11F6A
-S31508000C78C404002008B51A230B80FFF7E1FF0148D2
-S31508000C8808BD00BFC404002008B50A4628B90549A6
-S31508000C98054803F078FE034808BD0249024803F0F0
-S31508000CA872FEF8E718170020445D000810B5044CD2
-S31508000CB80A462146034803F066FE204610BD00BFD3
-S31508000CC818170020345D000808B50A4628B90549EA
-S31508000CD8054803F058FE034808BD0249024803F0D0
-S31508000CE852FEF8E718170020145D000808B50A46EA
-S31508000CF828B90549054803F046FE034808BD0249D0
-S31508000D08024803F040FEF8E7181700201C5D0008A3
-S31508000D1830B40468606A29B940EA0240A062002033
-S31508000D2830BC70470D46A36A00EB13400023691EC2
-S31508000D388B4209D203F1400104EB8101496800EBB3
-S31508000D4811400133DBB2F2E740EA024005F13F0100
-S31508000D5804EB81014860E2E703685962002070479E
-S31508000D68024603680121C0F8FC13002082F8F40340
-S31508000D789A6942F000629A61596D024A0A435A65AD
-S31508000D88704700BF030000107047000010B5164BE7
-S31508000D986FF00042DA670024DC674FF0FF32C3F8C9
-S31508000DA88020C3F88040C3F88420C3F88440C3F879
-S31508000DB88820C3F88840C3F88C20C3F88C40C3F849
-S31508000DC89020C3F89040C3F89420C3F89440C3F819
-S31508000DD89820C3F89840C3F89C20C3F89C40FFF7AE
-S31508000DE823FE204610BD00BF00440258104B1B784E
-S31508000DF80BB90120704710B504464FF47A70B0FB5A
-S31508000E08F3F30C4A1068B0FBF3F000F09DF868B9E4
-S31508000E180F2C01D901200AE0002221464FF0FF30A5
-S31508000E2800F060F8044B1C60002000E0012010BDAB
-S31508000E38DE040020E4040020E004002010B50320A6
-S31508000E4800F03EF800F048F90F498B69C3F303230D
-S31508000E580E4AD35C03F01F03D8408B6903F00F03CF
-S31508000E68D35C03F01F0320FA03F3094A1360094BFE
-S31508000E7818600020FFF7BAFF10B10124204610BDFC
-S31508000E880446FFF721FDF9E700440258A85D000863
-S31508000E98E8040020E404002038B5044604F0E0FE1F
-S31508000EA80546B4F1FF3F02D0044B1B781C4404F0F6
-S31508000EB8D7FE401BA042FAD338BD00BFDE04002087
-S31508000EC80649CB6823F4E0631B041B0C000200F4F4
-S31508000ED8E0600343024A1A43CA60704700ED00E01F
-S31508000EE80000FA0530B4154BDB68C3F30223C3F1D7
-S31508000EF80704042C28BF04241D1D062D01D9033B0D
-S31508000F0800E000234FF0FF3505FA04F421EA04014E
-S31508000F18994005FA03F322EA03031943002805DB77
-S31508000F280901C9B2064B195430BC704700F00F00C6
-S31508000F380901C9B2034B1954F6E700BF00ED00E0F2
-S31508000F4800E400E014ED00E00138B0F1807F0AD231
-S31508000F58064B5860064AF02182F82310002098604C
-S31508000F6807221A6070470120704700BF10E000E0AA
-S31508000F7800ED00E038B5036813F0010F40F08C80E7
-S31508000F880D4604460368454A1A408B6809690B43A7
-S31508000F9869690B43E9690B4313430360EB684268C5
-S31508000FA822F4405213434360AB69826822F44072C4
-S31508000FB8134383603A4B984216D03A4B98421CD052
-S31508000FC8394B98421DD0394B98421ED0384B984217
-S31508000FD81FD0384B984220D0374B984221D0374BF0
-S31508000FE8984222D001204EE0354802F007FE002834
-S31508000FF848D06A68EAB9012045E0324802F0FEFDA1
-S31508001008F5E7304802F0FAFDF1E72E4802F0F6FD5A
-S31508001018EDE72C4802F0F2FDE9E7294802F0EEFD73
-S31508001028E5E7284802F0EAFDE1E7264802F0E6FD8A
-S31508001038DDE72B68E9690B2B2CD8B1F5004F0DD0E5
-S31508001048DBB2214951F82330B0FBF3F303EB520323
-S31508001058B3FBF2F39BB2E360002014E0DBB21A4953
-S3150800106851F82330B0FBF3F0530803EB4000B0FB0C
-S31508001078F2F34FF6F0721A40C3F342031343E360E0
-S31508001088002000E00120E26A22F00F022B881343B1
-S31508001098E36202E00020F6E7012038BDF369FFEFB6
-S315080010A8001001400044004000480040004C004041
-S315080010B8005000400014014000780040007C0040C1
-S315080010C80803000708000007585D0008014B186068
-S315080010D8704700BFE4040020724B1B6903F038030D
-S315080010E8102B00F0DB80182B10D00BB16E48704718
-S315080010F86C4B1B6813F0200F00F0D280694B1868F8
-S31508001108C0F3C100694B23FA00F07047654A916A33
-S3150800111801F00301906AC0F30510D36A03F00103CE
-S31508001128526BC2F3CC0203FB02F307EE903AF8EED1
-S31508001138677A002800F0B580012966D0F9B1022936
-S3150800114800F08F8007EE100AF8EE476A9FED586A96
-S3150800115886EE267A534B1B6BC3F3080306EE903AC2
-S31508001168F8EE666A9FED536A67EE867A76EEA77A90
-S31508001178F7EE006A77EEA67A27EE277A61E0494BFA
-S315080011881B6813F0200F23D046490A68C2F3C10228
-S31508001198464BD34007EE103AF8EE476A07EE100AB0
-S315080011A8B8EE476A86EE867A0B6BC3F3080306EE33
-S315080011B8903AF8EE666A9FED3F6A67EE867A76EEAB
-S315080011C8A77AF7EE006A77EEA67A27EE277A38E046
-S315080011D807EE100AF8EE476A9FED376A86EE267A12
-S315080011E8304B1B6BC3F3080306EE903AF8EE666AB3
-S315080011F89FED306A67EE867A76EEA77AF7EE006A8A
-S3150800120877EEA67A27EE277A1BE007EE100AF8EE9D
-S31508001218476A9FED276A86EE267A224B1B6BC3F32D
-S31508001228080306EE903AF8EE666A9FED226A67EEBC
-S31508001238867A76EEA77AF7EE006A77EEA67A27EE2A
-S31508001248277A184B1B6BC3F34623013307EE903AEC
-S31508001258F8EE677AC7EE276AFCEEE67A17EE900A82
-S31508001268704707EE100AF8EE476A9FED146A86EE8D
-S31508001278267A0C4B1B6BC3F3080306EE903AF8EE76
-S31508001288666A9FED0C6A67EE867A76EEA77AF7EEB7
-S31508001298006A77EEA67A27EE277AD2E708487047D3
-S315080012A8024870470044025800093D000090D003E0
-S315080012B80024744A000000390024744C0024F44AB7
-S315080012C800127A0008B5FFF707FF0B4A9369C3F3BC
-S315080012D803230A49CB5C03F01F0320FA03F3926938
-S315080012E802F00F02885C00F01F0023FA00F0044A97
-S315080012F81060044A136008BD00440258A85D000837
-S31508001308E8040020E4040020002301330C4A934231
-S3150800131811D80269002AF8DA036943F00103036160
-S3150800132800230133064A934207D8026912F0010FCF
-S31508001338F7D100207047032070470320704700BF85
-S31508001348400D030084B010B5044603A880E80E00D3
-S31508001358089B012B1DD1A36B23F48033A363E26892
-S315080013681A4B1340E360E36823F44013E3600F9BCA
-S31508001378012B09D02046FFF7C7FF069B012B1BD078
-S31508001388BDE8104004B07047E36843F48013E3608F
-S31508001398F0E7E36843F04003E3602046FFF7B4FF4D
-S315080013A80C9B23B9A36B43F48033A363E5E7A36BCC
-S315080013B823F48033A363E0E7A36843F00603A36036
-S315080013C8A36843F02003A360DAE700BFBFFFBDFFA9
-S315080013D8022A0AD00921C26822F47052C260C36878
-S315080013E843EA8123C36000207047274B0B44274AEA
-S315080013F8934237D9264B0B44264A934234D9264B6F
-S315080014080B44264A934231D9254B0B4402F5C3327D
-S31508001418A03293422CD9234B0B44234A934229D909
-S31508001428224B0B4402F5922202F57872934223D98D
-S315080014381F4B0B4402F5C32202F5207293421DD9AD
-S315080014481C4B0B4402F5B71202F55872934217D98A
-S31508001458194B0B4402F5122202F5F862934211D889
-S315080014680721B8E70F21B6E70E21B4E70D21B2E741
-S315080014780C21B0E70B21AEE70A21ACE70921AAE758
-S315080014880821A8E70621A6E7405327FFFF340C00E2
-S31508001498401E1BFF3F420F0000DC0BFF7F4F120068
-S315080014A8808CF9FE60B6E5FE5FE3160000D3CEFE33
-S315080014B8C05BB3FE00CA91FEE05459FE836843F048
-S315080014C80103836000207047836823F00103836063
-S315080014D80020704708B5C36823F0C043C3600129D4
-S315080014E809D069B9C36843F08043C3603220FFF75F
-S315080014F8D3FC002008BDC36843F00053C360F5E772
-S315080015080120F7E7890141F0200101610023013331
-S31508001518054A934205D8026912F0200FF7D1002030
-S3150800152870470320704700BF400D0300102303616E
-S3150800153800230133054A934205D8026912F0100FB1
-S31508001548F7D1002070470320704700BF400D0300FD
-S31508001558D0F800381943C0F8001800207047000072
-S3150800156884B0F8B5044607A880E80E002546002387
-S315080015780E2B07D803F1400204EB820200215160C2
-S315080015880133F5E7119B23BBD4F8043843F002036B
-S31508001598C4F80438A36B23F40013A363236843F041
-S315080015A840032360236843F0800323600023C4F8BC
-S315080015B8003E04F50066D4F80038C4F800380C9BD9
-S315080015C8012B10D1099B4BB900212046FFF7C0FF14
-S315080015D80DE0A36B43F40013A363E7E70121204654
-S315080015E8FFF7B6FF03E003212046FFF7B1FF1021F6
-S315080015F82046FFF787FF074600B101272046FFF771
-S3150800160895FF00B10127002333617361F3610AE08E
-S31508001618C3B94FF00060C2F8000900220A614FF604
-S315080016287F328A600133079A9A4210D905EB43122A
-S3150800163802F51061D2F800090028E9DB0020C2F893
-S315080016480009EAE74FF09040C2F80009E5E70023E9
-S315080016580AE0C3B94FF00060C2F8000B00220A611D
-S315080016684FF67F328A600133079A9A4210D905EBFA
-S31508001678431202F53061D2F8000B0028E9DB002096
-S31508001688C2F8000BEAE74FF09040C2F8000BE5E70E
-S31508001698336923F4807333610023A3616FF08043B1
-S315080016A863610A9B1BB9A36943F01003A361A26986
-S315080016B80A4B1343A3610D9B1BB1A36943F00803A7
-S315080016C8A361119B012B04D03846BDE8F84004B045
-S315080016D87047A269024B1343A361F5E700383C80BB
-S315080016E804000040D0F8083813F0060305D0062B86
-S315080016F818BF022B03D102207047002070470F201D
-S315080017087047000070B40B784A78012A20D0D0F8C0
-S315080017181C2803F00F060124B44042EA0442C0F824
-S315080017281C2800EB4310D0F8003B13F4004F0CD1EB
-S31508001738D0F8002B8B68C3F30A03C97843EA8143B8
-S315080017481343134A1A43C0F8002B002070BC70478D
-S31508001758D0F81C4803F00F06B24092B22243C0F8EC
-S315080017681C2800EB4310D0F8002912F4004FECD1DE
-S31508001778D0F800498A68C2F30A02C97842EA81425F
-S3150800178842EA8353234302491943C0F80019DCE7A0
-S315080017980080001070B40B784A78012A1FD0D0F858
-S315080017A83C5803F00F06012404FA06F625EA06450E
-S315080017B8C0F83C58D0F81C58097801F00F018C403D
-S315080017C825EA0444C0F81C4800EB4310D0F8002B5F
-S315080017D8124B1340C0F8003B002070BC7047D0F885
-S315080017E83C6803F00F0402FA04F4A4B226EA0404D7
-S315080017F8C0F83C48D0F81C48097801F00F018A401F
-S3150800180892B224EA0202C0F81C2800EB4310D0F86A
-S315080018180039034A1A40C0F80029DDE70078F3EFD3
-S31508001828007833EC70B40B784C78012C24D000EB94
-S31508001838431000F530631D693E4C2C401C611D6938
-S315080018483D4C2C401C614C690CB18C684C611C6978
-S3150800185844F400241C611C698D68C5F312052C43E1
-S315080018681C61012A61D0D0F8003B43F00443C0F854
-S31508001878003B002070BC70474C695CBB00EB431406
-S31508001888D4F810692C4D3540C4F81059D4F81059B5
-S3150800189845F40025C4F81059D4F81069254D354083
-S315080018A8C4F81059012A31D000EB4313D3F800299C
-S315080018B842F00442C3F800294B69002BD9D0D0F866
-S315080018C83428097801F00F040121A1400A43C0F819
-S315080018D83428CEE700EB431404F510642669154D41
-S315080018E8354025612669144D354025614E698D6850
-S315080018F8AE4200D94D61256945F40025256125695B
-S315080019084E69C6F3120635432561CBE70A691AB14B
-S3150800191800EB4311C1F8142900EB4310D0F800294D
-S3150800192842F00442C0F80029A3E7CA68002A9AD0F8
-S315080019385A6198E70000F8FFFFFF07E070B49DF8C2
-S315080019480C4064B903339E08B44208D200EB02334C
-S3150800195803F5805351F8045B1D600134F4E7002051
-S3150800196870BC7047F0B583B00B784C78012C29D039
-S3150800197800EB431303F5306426697C4D3540256131
-S3150800198826697B4D354025614D69002D40F0BF809D
-S3150800199825698E68C6F3120635432561256945F417
-S315080019A800252561012A00F0C780CA78012A00F0B7
-S315080019B8C980D3F8002B42F00442C3F8002B002054
-S315080019C803B0F0BD4C6974BB00EB4314D4F8106936
-S315080019D8674D3540C4F81059D4F8105945F4002510
-S315080019E8C4F81059D4F81069604D3540C4F8105930
-S315080019F8012A4AD000EB4313D3F8004944F00444BB
-S31508001A08C3F80049CC78012C68D04B69002BD6D08E
-S31508001A18D0F83428097801F00F040121A1400A43B7
-S31508001A28C0F83428CBE700EB4314D4F810694F4DB7
-S31508001A383540C4F81059D4F810694D4D3540C4F8E6
-S31508001A481059D4F810694D698F683D44013DB5FBB6
-S31508001A58F7F5484F07EAC5453543C4F81059D4F889
-S31508001A6810594E69C6F312063543C4F8105904F5D9
-S31508001A781064CD78012DBBD1256925F0C0452561AF
-S31508001A88256945F000552561B2E70A691AB100EBE0
-S31508001A984314C4F81429CA78012A08D000EB43135A
-S31508001AA8D3F8002942F00442C3F8002987E7D0F89A
-S31508001AB8082812F4807F08D100EB4311D1F80029D1
-S31508001AC842F00052C1F80029E8E700EB4311D1F8C3
-S31508001AD8002942F08052C1F80029DFE7D0F8084803
-S31508001AE814F4807F0CD1D3F8004944F00054C3F8A5
-S31508001AF8004900928B8A0A78C968FFF71FFF5EE7D4
-S31508001B08D3F8004944F08054C3F80049F1E78E68D1
-S31508001B183544013DB5FBF6F52669164F07EAC5476C
-S31508001B283E43266127698E68ADB206FB05F5C5F3FF
-S31508001B3812053D43256135E7CA68002A3FF435AFE3
-S31508001B48626132E7D0F8082812F4807F06D1D3F804
-S31508001B58002B42F00052C3F8002B2AE7D3F8002BD3
-S31508001B6842F08052C3F8002B23E700BF0000F8FFB5
-S31508001B78FFFF07E00000F81F03329208002393428C
-S31508001B880CD210B400F58054246841F8044B01338C
-S31508001B989342F7D308465DF8044B704708467047E2
-S31508001BA80B784A78012A14D000EB4310D0F8002B9A
-S31508001BB8002A06DB2BB1D0F8003B23F08043C0F897
-S31508001BC8003BD0F8003B43F40013C0F8003B002064
-S31508001BD8704700EB4310D0F80029002A06DB2BB122
-S31508001BE8D0F8003923F08043C0F80039D0F8003916
-S31508001BF843F40013C0F80039E9E70B784A78012A54
-S31508001C080ED000EB4310D0F8003B23F40013C0F8BD
-S31508001C18003BCB78023BDBB2012B15D90020704775
-S31508001C2800EB4310D0F8003923F40013C0F8003944
-S31508001C38CB78023BDBB2012BF0D8D0F8003943F059
-S31508001C488053C0F80039E9E7D0F8003B43F08053E1
-S31508001C58C0F8003BE2E738B50546044600220E2AD6
-S31508001C6809D804EB42134FF67F31C3F80819C3F8AD
-S31508001C78081B0132F3E70022C5F81028C5F814280E
-S31508001C88C5F81C282846FFF751FC034608B118462C
-S31508001C9838BD10212846FFF735FC0346F7E7D0F884
-S31508001CA8003823F4FE63C0F80038D0F80038090174
-S31508001CB801F4FE610B43C0F800380020704708B5E8
-S31508001CC8D0F8043823F00203C0F804380320FFF7D5
-S31508001CD8E3F8002008BD08B5D0F8043843F0020335
-S31508001CE8C0F804380320FFF7D7F8002008BD426972
-S31508001CF8806910407047D0F8183800F50060C06948
-S31508001D081840000C7047D0F8183800F50060C0690C
-S31508001D18184080B2704700EB4111D1F8082B00F53E
-S31508001D28006040691040704710B4D0F81048D0F8E1
-S31508001D38343801F00F02D340DB01DBB2234300EB52
-S31508001D48411000F51060806818405DF8044B70472C
-S31508001D58406900F001007047D0F80029054B134088
-S31508001D68C0F80039D0F8043843F48073C0F804384A
-S31508001D780020704700F8FFFF10B4046C154B9C420E
-S31508001D8803D9D0F8003B002B16DB0024C0F8104B0B
-S31508001D98D0F8104B44F40024C0F8104BD0F8104B78
-S31508001DA844F01804C0F8104BD0F8104B44F0C0445F
-S31508001DB8C0F8104B012903D000205DF8044B704782
-S31508001DC8C0F8142BD0F8003B43F08023C0F8003B3A
-S31508001DD8F2E700BF0A30544F144BDB6813F0010FC3
-S31508001DE809D0124B124A5A6002F188325A60DB68E7
-S31508001DF813F0010F14D10D4BD3F80C3113F0010F62
-S31508001E0810D00A4B0A4AC3F8042102F18832C3F8EB
-S31508001E180421D3F80C3113F0010F05D100207047BF
-S31508001E2801207047002070470120704700200052A3
-S31508001E38230167450D4BDA6842F00102DA60DB6870
-S31508001E4813F0010F0DD0094BD3F80C2142F001020B
-S31508001E58C3F80C21D3F80C3113F0010F03D0002076
-S31508001E687047012070470120704700BF00200052C4
-S31508001E78F8B505460E4603F0F3FE0746012E09D0C7
-S31508001E88364C17E003F0ECFEC01BA84260D88DB9A3
-S31508001E9803204EE004240DE0314BD3F8103124EA30
-S31508001EA8030333F000430CBF012300236BB1B5F1DC
-S31508001EB8FF3FE7D134F00403EED1294B1B6934EA16
-S31508001EC803030CBF01230023F0E7012E1CD0244B83
-S31508001ED8D3F8103123F0684323F480135B0C5B04B2
-S31508001EE843F0004333F0024217D1012E25D01C4B8C
-S31508001EF8D3F8103113F4803F2ED0194B4FF48032A3
-S31508001F08C3F81421002014E0154B1B6923F0684315
-S31508001F1823F480135B0C5B04E4E712498A691A43C5
-S31508001F288A61002B06DA23F000430D4AC2F81431F9
-S31508001F380120F8BD0A4A5361FAE7094B1B6913F4ED
-S31508001F48803F07D0064B4FF480325A610020F0E7ED
-S31508001F580320EEE70020ECE70020EAE7040000800B
-S31508001F6800200052181900202C4B1B7D012B51D03C
-S31508001F7870B50C461546294B01221A7501F17841A8
-S31508001F88B1F5801F38D21646244B00229A6131468D
-S31508001F984CF25030FFF76CFF034640BB012E2DD09C
-S31508001FA81F4AD2F80C3143F00203C2F80C31BFF3CA
-S31508001FB86F8FBFF34F8F082355F8042B44F8042B6B
-S31508001FC8013B13F0FF03F7D1BFF36F8FBFF34F8FB2
-S31508001FD831464CF25030FFF74BFF0346012E13D01B
-S31508001FE80F49D1F80C2122F00202C1F80C210B4A3C
-S31508001FF800211175184670BD0226C5E7084AD36838
-S3150800200843F00203D360D2E70549CA6822F0020200
-S31508002018CA60ECE702231846704700BF1819002063
-S3150800202800200052024AD36843F08073D360704791
-S31508002038004802586A4B984222D06A4B98422FD0D9
-S31508002048694B98423CD0694B984249D0684B9842AC
-S3150800205856D0684B984263D0674B984270D0674B06
-S3150800206898427DD0664B984200F08A80654B984224
-S3150800207800F09680644B984200F0A28001207047D1
-S3150800208803F58843D3F8882042F00102C3F888206C
-S31508002098D3F8882022F00102C3F888200020704768
-S315080020A803F58043D3F8882042F00202C3F8882053
-S315080020B8D3F8882022F00202C3F888200020704747
-S315080020C803F57053D3F8882042F00402C3F8882031
-S315080020D8D3F8882022F00402C3F888200020704725
-S315080020E803F56053D3F8882042F00802C3F888201D
-S315080020F8D3F8882022F00802C3F888200020704701
-S3150800210803F55053D3F8882042F01002C3F8882004
-S31508002118D3F8882022F01002C3F8882000207047D8
-S3150800212803F54053D3F8882042F02002C3F88820E4
-S31508002138D3F8882022F02002C3F8882000207047A8
-S3150800214803F53053D3F8882042F04002C3F88820B4
-S31508002158D3F8882022F04002C3F888200020704768
-S3150800216803F52053D3F8882042F08002C3F8882064
-S31508002178D3F8882022F08002C3F888200020704708
-S3150800218803F51053D3F8882042F48072C3F88820E0
-S31508002198D3F8882022F48072C3F888200020704774
-S315080021A803F50053D3F8882042F40072C3F8882050
-S315080021B8D3F8882022F40072C3F8882000207047D4
-S315080021C803F5E053D3F8882042F48062C3F88820E0
-S315080021D8D3F8882022F48062C3F888200020704744
-S315080021E8000002580004025800080258000C025859
-S315080021F8001002580014025800180258001C025809
-S31508002208002002580024025800280258F0B40C6826
-S3150800221894FAA4F4B4FA84F42BE08E68826803FB73
-S3150800222803F505EB450722EA070205FB06F52A43E7
-S3150800223882600E68CD68426822EA060205FB06F542
-S315080022482A4342600F69C66803FB03F505EB450296
-S31508002258D243164005FB07F73E43C6604E68022E72
-S3150800226814D04B680668324005FB03F31343036032
-S3150800227801340B6833FA04F22BD00122A24013402A
-S31508002288F6D04A68013A012ADCD8C6E7FF2B0ED8E9
-S31508002298066A05FB03F707FB03F3C3EB031726EAEE
-S315080022A807074E6903FB06F33B430362D9E7466A09
-S315080022B81B0A03FB03F707FB03F707FB03F3C3EB49
-S315080022C8031726EA07074E6903FB06F33B434362EF
-S315080022D8C7E70020F0BC70472DE9F04782B0D0F870
-S315080022E80080CA00521A930003445A6D1B6D9A421D
-S315080022F855D8C1469B1AC1EBC104A2000244526CC8
-S315080023089A4200D31A460C46074602F1030A4FEAD0
-S315080023189A0A15E006F1030A4FEA9A0AE3001B1B14
-S315080023289D003D44A96C3B7C0093B3B2E2B240469B
-S31508002338FFF704FBAB6C3344AB646B6D1E446E65E8
-S3150800234809EB441303F510639B699BB2534512D3F3
-S31508002358E3001B1B9A003A44516D136D99420AD241
-S315080023684BB15B1AC4EBC4018A003A44566C9E42C8
-S31508002378D0D31E46CEE7E3001B1B980007443A6DE8
-S315080023887B6D9A420FD804F00F040123A340D8F8AE
-S31508002398344824EA0304C8F83448002000E0012039
-S315080023A802B0BDE8F0870020FAE77047F0B58BB0B1
-S315080023B8002800F091800446056890F8BD3323B3D9
-S315080023C8032384F8BD33EB6B13F4807F01D1002314
-S315080023D823612068FFF778F8254655F8107B6E467E
-S315080023E80FCD0FC60FCD0FC695E8030086E8030084
-S315080023F8231D0ECB3846FEF7A5FF58B1022384F8ED
-S31508002408BD33012528460BB0F0BD80F8BC33FFF76D
-S31508002418CCFFD5E700212068FFF75CF8002365683C
-S31508002428AB4216D2D900C81A82002244012082F883
-S315080024383D0082F83C30A2F84230002082F83F007E
-S3150800244850649064CA1A9100214408650133DBB2C6
-S31508002458E5E700239D4216D9D800C11A8A00224406
-S31508002468002182F8FD1182F8FC3182F8FF11C2F8C2
-S315080024780412C2F80812C21A90002044C0F81012B2
-S315080024880133DBB2E6E7254655F8107B6E460FCDD5
-S315080024980FC60FCD0FC695E8030086E80300231D6F
-S315080024A80ECB3846FFF75CF8054660B9002384F872
-S315080024B83830012384F8BD33636A012B08D02068B5
-S315080024C8FFF709FC9EE7022384F8BD33012599E73F
-S315080024D82046FEF745FCF2E7012593E770470268B0
-S315080024E890F8BC33012B19D010B5012380F8BC33FA
-S315080024F8836A012B0AD004460068FFF7E0FB2068C8
-S31508002508FEF7DCFF002084F8BC0310BD8369012BA5
-S31508002518F1D0936B43F480339363ECE7022070475A
-S3150800252838B590F8BC33012B18D00446012380F837
-S31508002538BC330068FEF7C8FF2068FFF78CFB054622
-S3150800254828B1002384F8BC330125284638BD2068FD
-S31508002558FFF7C1FB002384F8BC33F6E70225F4E746
-S3150800256868B110B50446032380F8BD33FFF7D8FFD2
-S315080025782046FFF7B3FF002084F8BD0310BD0120ED
-S315080025887047000070B504460D460068066C00EBF7
-S31508002598411303F530639A682169012911D037492F
-S315080025A88E4254D03DB9C5EBC50293002344D3F8EF
-S315080025B81032002B5CD0E9B22046FDF750FF002008
-S315080025C870BD12F0080F09D02D498E42F7D912F4BA
-S315080025D8004FF4D04FF400429A60F0E712F0200F4B
-S315080025E802D020229A60EAE712F0280FE7D1244998
-S315080025F88E4206D912F4004F03D04FF400429A606F
-S31508002608DDE7E900491B8A002244D2F804121B694F
-S31508002618C3F31203C91AC2F81412D2F80412D2F86C
-S3150800262808320B44C2F8083235B9C5EBC50293001F
-S315080026382344D3F8103223B1E9B22046FDF70FFF39
-S31508002648BDE704F571720121FFF796FBF4E712F46A
-S31508002658004F03D04FF400429A60B0E712F0200FFB
-S3150800266801D020229A60E9B22046FDF7F8FEA6E7CF
-S3150800267804F571720021FFF77FFB9CE70A31544F76
-S315080026880A30544F38B5044603681D6C03EB4111EC
-S31508002698D1F8082B0E4B9D4207D901F5306112F483
-S315080026A8004F02D04FF400438B602046FDF7CFFE5B
-S315080026B8074B9D4202D92369012B01D0002038BD5A
-S315080026C804F5717201212068FFF756FBF6E700BF8B
-S315080026D80A30544F2DE9F84F044605682846FFF78F
-S315080026E837FB08B1BDE8F88F2F4606462068FFF77E
-S315080026F8FEFA0028F6D02068FFF7F9FA10F0020F5C
-S3150800270804D02268536903F0020353612068FFF76F
-S31508002718EEFA10F0100F15D02268936923F010030B
-S315080027289361D5F8208008F00F09C8F34343022BB4
-S3150800273800F08580062B00F0A5802268936943F08F
-S31508002748100393612068FFF7D2FA10F4002F40F0BF
-S31508002758AD802068FFF7CBFA10F4802F40F0F1809F
-S315080027682068FFF7C4FA0028C0F25F812068FFF7DF
-S31508002778BEFA10F4006F0AD0D5F8083813F0010F1E
-S3150800278840F06D812268536903F400635361206839
-S31508002798FFF7ADFA10F0006F15D02268536903F0F9
-S315080027A80063536194F8F433002B40F05C810121EF
-S315080027B884F8F41323685B6DC3F38303C4F8F8330A
-S315080027C82046FEF7E1FA2068FFF791FA10F4805FD1
-S315080027D840F04D812068FFF78AFA10F4005F40F050
-S315080027E8AB812068FFF783FA10F0080F40F0BC8128
-S315080027F82068FFF77CFA10F4801F40F0BE81206835
-S31508002808FFF775FA10F4001F40F0C1812068FFF73A
-S315080028186EFA10F0804F40F0C4812068FFF767FA17
-S3150800282810F0040F3FF45EAF23685D6815F0040FD7
-S3150800283840F0C081226853682B43536052E747F635
-S31508002848F07318EA030F3FF478AF4FEA18184FEAFF
-S31508002858C90BABEB09034FEA830AA244C8F30A0279
-S31508002868DAF808122846FFF787F9C8F30A08DAF8E3
-S3150800287808324344CAF80832DAF814324344CAF824
-S3150800288814325AE7082204F571712846FFF774F9D5
-S31508002898C8F30A184FEAC903A3EB09018A002244B8
-S315080028A8D2F814324344C2F8143246E72068FFF7D0
-S315080028B822FA8046B14617E007EB49130122C3F806
-S315080028C8082B49462046FFF75DFE1DE007EB49132E
-S315080028D80822C3F8082B49462046FFF7D3FE16E018
-S315080028E809F101094FEA5808B8F1000F3FF431AF6A
-S315080028F818F0010FF4D05FFA89F12068FFF70BFA90
-S31508002908824610F0010FD7D11AF0080FDED11AF057
-S31508002918100F04D007EB49131022C3F8082B1AF036
-S31508002928200F04D007EB49132022C3F8082B1AF402
-S31508002938005FD5D007EB49134FF40052C3F8082BAC
-S31508002948CEE72068FFF7DFF98046B1462AE0594600
-S315080029582046FDF790FD1AF0080F04D007EB491337
-S315080029680822C3F808291AF0100F04D007EB4913F0
-S315080029781022C3F808291AF0400F04D007EB4913A8
-S315080029884022C3F808291AF0020F04D007EB4913A6
-S315080029980222C3F808291AF0800F41D109F1010962
-S315080029A84FEA5808B8F1000F3FF4DAAE18F0010FED
-S315080029B8F4D05FFA89FB59462068FFF7B5F98246CD
-S315080029C810F0010FC7D009F00F03012101FA03F22D
-S315080029D8D7F8343823EA0203C7F8343807EB49131B
-S315080029E8C3F8081923698B42B1D14FEAC902A2EB89
-S315080029F8090293002344596C9A6C0A449A64B9F1FB
-S31508002A08000FA4D1C9EBC902930023441B6D002B00
-S31508002A189DD104F5717201212068FFF7ADF996E793
-S31508002A2849462046FFF758FCB8E7D5F8043823F096
-S31508002A380103C5F8043894F8F433012B08D0204666
-S31508002A48FDF75EFD2268536903F0004353618DE67E
-S31508002A58002184F8F4132046FEF796F9F2E7204693
-S31508002A68FDF734FD8EE62046FDF730FDABE605F5A5
-S31508002A780068D8F8043023F00103C8F80430102198
-S31508002A882068FEF73FFD20E007EB46134FF67F3137
-S31508002A98C3F80819D3F8002922F40012C3F8002944
-S31508002AA8D3F8002942F00062C3F80029C3F8081BC6
-S31508002AB8D3F8002B22F40012C3F8002BD3F8002B06
-S31508002AC842F00062C3F8002B01366368B342DBD8CC
-S31508002AD8D8F81C3043F00113C8F81C30236BEBB147
-S31508002AE8D8F8843043F00B03C8F88430D8F8443053
-S31508002AF843F00B03C8F84430D5F8003823F4FE63CE
-S31508002B08C5F8003804F57172217C2068FFF734F996
-S31508002B182268536903F4805353615BE6D8F8142096
-S31508002B2842F22B031343C8F81430D8F8103043F090
-S31508002B380B03C8F81030DFE72068FFF70DF920689F
-S31508002B48FEF7D0FDE0602568FEF7BCFB227B014650
-S31508002B582846FEF73DFC2046FDF79EFC2268536989
-S31508002B6803F4005353613CE62046FDF78FFC2268C0
-S31508002B78536903F0080353613AE600212046FDF736
-S31508002B88CEFC2268536903F48013536137E60021A3
-S31508002B982046FDF7BEFC2268536903F40013536107
-S31508002BA834E62046FDF7C1FC2268536903F08043E2
-S31508002BB8536132E62046FDF7C2FC3BE6026890F808
-S31508002BC8BC33012B16D010B5012380F8BC33836AB1
-S31508002BD8012B07D004460068FFF771F8002084F82F
-S31508002BE8BC0310BD8369012BF4D0936B43F480337F
-S31508002BF89363EFE70220704790F8BC33012B0BD09C
-S31508002C0810B50446012380F8BC330068FFF763F85B
-S31508002C18002084F8BC0310BD0220704790F8BC3326
-S31508002C28012B0DD010B50446012380F8BC3380F873
-S31508002C3838100068FFF733F8002084F8BC0310BD85
-S31508002C4802207047F8B511F0800F27D101F00F055B
-S31508002C58EE00771BBC00274604F5FC7404440434CC
-S31508002C680744002587F8FD5101F00F012170A2607D
-S31508002C78E370627802B1E180022B1ED090F8BC336B
-S31508002C88012B1DD00546012380F8BC332146006870
-S31508002C98FEF738FD002085F8BC03F8BD01F00F06DD
-S31508002CA8F500AF1BBC0027463834044404343E46B6
-S31508002CB80644012586F83D50D6E700232371DDE74B
-S31508002CC80220EAE738B511F0800F20D101F00F0489
-S31508002CD8E200151BAB001D4603F5FC7303440433D9
-S31508002CE80544002285F8FD2101F00F01197090F8B6
-S31508002CF8BC23012A1AD00446012280F8BC231946A7
-S31508002D080068FEF747FD002084F8BC0338BD01F0CB
-S31508002D180F04E200151BAB001D4638330344043381
-S31508002D282C460444012284F83D20DDE70220EDE71D
-S31508002D3870B501F00F05EE00711B8C0004F5FC74E4
-S31508002D480444211D761BB4000444C4F80822C4F8B8
-S31508002D5810320023C4F8143284F8FD3184F8FC5183
-S31508002D680369012B06D065B9DAB20068FEF75AFD81
-S31508002D78002070BDC5EBC506B4000444C4F80C228F
-S31508002D88F1E7DAB20068FEF7EDFDF1E701F00F01A9
-S31508002D98C1EBC1018B001844D0F81402704770B50E
-S31508002DA801F00F05EE00711B8C0038340444211D10
-S31508002DB8761BB4000444A2642365002363650123D3
-S31508002DC884F83D3084F83C500369012B06D05DB978
-S31508002DD8DAB20068FEF726FD002070BDC5EBC50609
-S31508002DE8B4000444E264F2E7DAB20068FEF7BAFD12
-S31508002DF8F2E738B501F00F0543689D4236D811F059
-S31508002E08800F20D1CA00541AA3001C4603F5FC7388
-S31508002E180344043322460244002182F8FD110122A4
-S31508002E289A701D7090F8BC23012A21D00446012205
-S31508002E3880F8BC2319460068FEF7B2FE7DB100206B
-S31508002E4884F8BC0338BDEA00511B8B001946383391
-S31508002E58034404330144012281F83D20DFE704F5E1
-S31508002E687172217C2068FEF787FFE8E70120E9E709
-S31508002E780220E7E710B501F00F0443689C422CD8F6
-S31508002E8811F0800F1DD1E3001A1B91000A4601F5BF
-S31508002E98FC71014404310244002382F8FD31002301
-S31508002EA88B700C7090F8BC33012B18D0044601239C
-S31508002EB880F8BC330068FEF7A0FE002084F8BC033F
-S31508002EC810BDE3001A1B91000A4638310144043143
-S31508002ED80244012382F83D30E1E70120F0E70220A9
-S31508002EE8EEE7000030B4446B0268D2F88410704BE1
-S31508002EF8194041EA8401C2F884100268D2F884109D
-S31508002F0821F47F01856B41EA0541C2F88410826B7A
-S31508002F1822440468D4F88810194041EA8201C4F8A2
-S31508002F2888100468D4F8881021F4FE01C56B41EAB4
-S31508002F380541C4F88810C16B02EB41020468D4F84D
-S31508002F48A010194041EA8201C4F8A0100468D4F810
-S31508002F58A01021F4FE01056C41EA0541C4F8A01049
-S31508002F68046C416C01FB04240268D2F8B0101940BD
-S31508002F7841EA8401C2F8B0100268D2F8B01021F408
-S31508002F88FE01856C41EA0541C2F8B010826CC16C35
-S31508002F9801FB02440268D2F8AC10194041EA8401E0
-S31508002FA8C2F8AC10026D416D01FB02420468D4F800
-S31508002FB8F010194041EA8201C4F8F0100468D4F800
-S31508002FC8F01021F47C11856D41EA0541C4F8F0102A
-S31508002FD8816D02EB41020468D4F8C0100B4043EA3D
-S31508002FE88202C4F8C0200268D2F8C03023F47C13E1
-S31508002FF8C16D43EA0143C2F8C0300268D2F8C0304E
-S3150800300823F07C53016E43EA0163C2F8C030436B70
-S31508003018284A1A449200C266836B02EB8303036745
-S31508003028C16B03EBC1034367046C416C01FB04F1F4
-S3150800303803EB81038367846CC16C01FB04F103EB22
-S315080030488103C367046D416D01FB04F103EB81033A
-S31508003058C0F88030816D03EBC103C0F88430C46DB5
-S31508003068856E05FB04F403EB8403C0F88830016E0B
-S3150800307801FB05F103EB8103C0F890300E498B423A
-S3150800308807D8D0F8903093420ED9002342F8043B6B
-S31508003098F7E7D0F89C3043F02003C0F89C300323A8
-S315080030A880F89830012000E0002030BC704700BF47
-S315080030B80300FFFF002B0010FCD30040F0B44C6857
-S315080030C8002C2FD10E698C6826430C6846EA84467C
-S315080030D80D6ACC6944EA05648D692C434D692C430D
-S315080030E8CD682C43D0F88470806E03FB00F307EB99
-S315080030F8830547F823606C6008350020CB890E4C99
-S31508003108E35C834216D91418E678A3781B0443EAC5
-S315080031180663647843EA0423145C234345F8043BAE
-S315080031280430EBE70C698E6826430C68264346F09C
-S315080031388046CDE7F0BC7047885D000870470000F8
-S3150800314830B595B004464C22A04901A802F091FD75
-S31508003158002C00F0388123689D4A934220D094F8C1
-S3150800316898300BB32268936923F01003936102F031
-S3150800317877FD054623689A6912F0080F1AD002F0F7
-S315080031886FFD401B0A28F5D9D4F89C3043F0010393
-S31508003198C4F89C30032384F89830012015B030BD54
-S315080031A803F580736360DAE784F899302046FFF7F9
-S315080031B8C5FFD7E79A6942F001029A6102F050FD05
-S315080031C8054623689A6912F0010F0FD102F048FDE7
-S315080031D8401B0A28F5D9D4F89C3043F00103C4F8F3
-S315080031E89C30032384F898300120D7E79A6942F07F
-S315080031F802029A61237C012B40D02268936943F026
-S3150800320840039361637C012B3ED02268936923F4BB
-S3150800321880439361A37C012B3CD02268936943F4CD
-S31508003228805393612268936923F44073A1680B431A
-S3150800323893612268936923F0A4039361226813694A
-S3150800324823F010031361E368012B29D0002B2CD037
-S31508003258022B00F09B802268936943F080039361F0
-S315080032682268136943F010031361E368032B1CD122
-S315080032782268936943F02003936116E022689369EC
-S3150800328823F040039361BDE72268936943F48043BA
-S315080032989361BFE72268936923F480539361C1E772
-S315080032A82268936943F004039361A3695A1EE36984
-S315080032B8013B1B0243EA4263226A013A13436269E5
-S315080032C8013A216843EA0243CB61A368B3F5407F14
-S315080032D862D0236E33B12268D2F8C030616E0B43D0
-S315080032E8C2F8C030E36D226ED3420DD02168D1F8FA
-S315080032F8C83023F00703A26E14A800EB820252F81E
-S315080033084C2C1343C1F8C830236C6BB12168D1F82B
-S31508003318BC3023F00703626C14A800EB820252F84B
-S315080033284C2C1343C1F8BC30A36C73B12168D1F88F
-S31508003338BC3023F07003E26C14A800EB820252F842
-S315080033484C2C43EA0213C1F8BC30236D73B12168CB
-S31508003358D1F8BC3023F4E063626D14A800EB82024E
-S3150800336852F84C2C43EA0223C1F8BC302268184BA1
-S315080033789A4222D00023C4F89430C4F89C3001231A
-S3150800338884F898302046FFF7ADFD07E72268936969
-S3150800339843F02003936188E7A36A013BE26A013A8E
-S315080033A843EA0223226B013A43EA0213626A013AA4
-S315080033B8216843EA0243CB608BE76268936823F087
-S315080033C803039360D6E70120E8E600BFB05C00086F
-S315080033D800A0004090F89830013BDBB2012B07D9D2
-S315080033E8D0F89C3043F00203C0F89C30012070479F
-S315080033F8CB680A68D2B9072B0ED08A68DB0643EA77
-S3150800340882730A6943EA02434A691343C26E4968E2
-S3150800341842F82130002070470A69CB691B0243EA43
-S3150800342802438A69134343F06053EFE710B40A6905
-S3150800343842EA4372072B0ED08C684B6943EA8473B9
-S31508003448006F496800EBC10440F83120636000202A
-S315080034585DF8044B70478B69F2E790F89830DBB251
-S31508003468012B07D0D0F89C3043F00403C0F89C30F1
-S3150800347801207047022380F898300268936923F080
-S31508003488010393610023C0F89C301846704770B54D
-S3150800349890F89840013CE4B2012C26D893FAA3F593
-S315080034A8B5FA85F50668D6F8C040C4F30544A542BA
-S315080034B80BD2D6F8CC401C420FD0D0F89C3043F03B
-S315080034C84003C0F89C30012016E0D0F89C3043F041
-S315080034D82003C0F89C3001200EE093FAA3F3B3FA50
-S315080034E883F3FFF7EBFD002006E0D0F89C3043F0A5
-S315080034F80203C0F89C30012070BD90F89830DBB202
-S31508003508022B07D0D0F89C3043F00803C0F89C304B
-S31508003518012070470368C3F8D010002070470000E0
-S31508003528F0B490F89840E4B2022C40F0BA804029EA
-S315080035380CD0412930D0046D8C4253D8D0F89C3031
-S3150800354843F02003C0F89C300120B1E00468D4F8A1
-S31508003558A05015F4FE0F0CD0D4F8A45015F07F0F20
-S315080035680FD1D0F89C3043F48073C0F89C30012002
-S315080035789EE0D0F89C3043F02003C0F89C30012028
-S3150800358896E0D4F8A440C4F3052C446F456C0CFBAC
-S3150800359805F504EB85042DE00468D4F8B05015F455
-S315080035A8FE0F0CD0D4F8B45015F07F0F0FD1D0F811
-S315080035B89C3043F48073C0F89C30012078E0D0F83A
-S315080035C89C3043F02003C0F89C30012070E0D4F802
-S315080035D8B440C4F3052C846FC56C0CFB05F504EBE5
-S315080035E8850407E0C46F456D01FB05F504EB850402
-S315080035F84FF0000C256805F080455560002D2CD144
-S315080036082568C5F38A451560256805F0005595604F
-S31508003618256805F000451561A588D561656805F42E
-S315080036287025D560656805F480155561656805F4E3
-S3150800363800159561E57905F07F0515626568ED0F52
-S31508003648556204F108050024D6891A4FBE5DA642BC
-S3150800365808D92E5D1E550134F6E7256825F060451C
-S315080036681560D1E740290AD041290DD01F290FD85E
-S315080036780268012303FA01F1C2F8981002E0036808
-S31508003688C3F8A8C0002013E00368C3F8B8C0F9E770
-S3150800369801F01F010268012303FA01F1C2F89C1020
-S315080036A8F0E7D0F89C3043F00803C0F89C300120B6
-S315080036B8F0BC7047885D00080368D3F89820D3F8EB
-S315080036C89C001F2903D8CA4012F0010F17D01F29DA
-S315080036D805D901F01F02D04010F0010F11D01F299B
-S315080036E805D8012000FA01F1C3F89810704701F0CF
-S315080036F81F01012000FA01F1C3F89C107047002049
-S315080037087047002070470368D3F8CC300B4201D0C5
-S315080037180120704700207047204A136843F00103C8
-S3150800372813601E4B1B6813F0040FFAD01B4B0022BC
-S315080037381A6119681A4A0A401A60184B1B6813F066
-S31508003748007FFAD1154B1B6813F0006FFAD1134B9B
-S315080037581B6813F0005FFAD1104B00229A61DA61F0
-S315080037681A62104999621049D962104919635A634D
-S315080037789963DA6319645A64196821F4802119600F
-S315080037881A66996E40F2FF720A439A66D3F8D020F1
-S3150800379842F48032C3F8D020704700BF004402586C
-S315080037A845EDF6EA000202020000FF018002010167
-S315080037B807EE900AF8EE676A07EE901AF8EE677A47
-S315080037C886EEA77A07EE902AF8EE677A06EE903A1A
-S315080037D8F8EE666A9FED096A66EE866A77EEA67A55
-S315080037E827EE277ADDED007AF8EE677AC7EE276ABC
-S315080037F8FCEEE67A17EE900A704700BF000000391B
-S315080038082DE9F04182B03E4B9B6A03F00303012B76
-S3150800381824D0BBB1022B28D00027002303604360BD
-S315080038288360374B9E6AC6F305161A6BC2F30802FD
-S31508003838551CDB6A13F0010F24D0314B5B6BC3F3BD
-S31508003848CC0821E02E4B1B6813F0040F14D02C4B20
-S315080038581B68C3F3C1032B4FDF40DEE7284B1B6801
-S3150800386813F4807F0AD10027D7E7254B1B6813F482
-S31508003878003F05D10027D0E70027CEE7224FCCE73F
-S31508003888224FCAE74FF00008002E36D004461C4BD4
-S31508003898DB6A13F4803F0CD0194B1B6BC3F3462322
-S315080038A80133009343462A4631463846FFF780FFD8
-S315080038B82060134BDB6A13F4003F0CD0104B1B6BCC
-S315080038C8C3F306430133009343462A46314638462E
-S315080038D8FFF76EFF60600A4BDB6A13F4802F0CD083
-S315080038E8074B1B6BC3F306630133009343462A460B
-S315080038F831463846FFF75CFFA06002B0BDE8F081A4
-S31508003908004402580090D00300093D0000127A00CE
-S315080039182DE9F04182B03E4B9B6A03F00303012B65
-S3150800392824D0BBB1022B28D00027002303604360AC
-S315080039388360374B9E6AC6F305369A6BC2F308024C
-S31508003948551CDB6A13F0100F24D0314BDB6BC3F31D
-S31508003958CC0821E02E4B1B6813F0040F14D02C4B0F
-S315080039681B68C3F3C1032B4FDF40DEE7284B1B68F0
-S3150800397813F4807F0AD10027D7E7254B1B6813F471
-S31508003988003F05D10027D0E70027CEE7224FCCE72E
-S31508003998224FCAE74FF00008002E36D004461C4BC3
-S315080039A8DB6A13F4002F0CD0194B9B6BC3F3462321
-S315080039B80133009343462A4631463846FFF7F8FE50
-S315080039C82060134BDB6A13F4801F0CD0104B9B6BDB
-S315080039D8C3F306430133009343462A46314638461D
-S315080039E8FFF7E6FE60600A4BDB6A13F4001F0CD08B
-S315080039F8074B9B6BC3F306630133009343462A467A
-S31508003A0831463846FFF7D4FEA06002B0BDE8F0811B
-S31508003A18004402580090D00300093D0000127A00BD
-S31508003A282DE9F04182B0424B9B6A03F00303012B50
-S31508003A3824D0BBB1022B28D000250023036043609D
-S31508003A4883603B4B9C6AC4F305541A6CC2F308029C
-S31508003A58561CDB6A13F4807F24D0354B5F6CC7F39A
-S31508003A68CC0720E0324B1B6813F0040F14D0304BF8
-S31508003A781B68C3F3C1032F4DDD40DEE72C4B1B68DB
-S31508003A8813F4807F0AD10025D7E7294B1B6813F45E
-S31508003A98003F05D10025D0E70025CEE7264DCCE71F
-S31508003AA8264DCAE700272B1C18BF0123002C08BF80
-S31508003AB80023002B39D080461D4BDB6A13F4800F90
-S31508003AC80DD01B4B1B6CC3F34623013300933B46AF
-S31508003AD8324621462846FFF76BFEC8F80000144B05
-S31508003AE8DB6A13F4000F0DD0114B1B6CC3F30643A6
-S31508003AF8013300933B46324621462846FFF758FECF
-S31508003B08C8F804000A4BDB6A13F0807F0DD0084B0F
-S31508003B181B6CC3F30663013300933B4632462146C2
-S31508003B282846FFF745FEC8F8080002B0BDE8F08148
-S31508003B38004402580090D00300093D0000127A009C
-S31508003B48154B1B6903F03803182B0ED8DFE803F06A
-S31508003B580F0D0D0D0D0D0D0D210D0D0D0D0D0D0D69
-S31508003B68160D0D0D0D0D0D0D1800002070470A4B8A
-S31508003B781B68C3F3C1030948D8407047084870470B
-S31508003B8800B585B001A8FFF73BFE019805B05DF8BA
-S31508003B9804FB0448704700BF004402580090D0034D
-S31508003BA800127A0000093D00044B9B6903F00F03D5
-S31508003BB8034AD35C03F01F03D840704700440258F1
-S31508003BC8985D0008044BDB69C3F30213034AD35C08
-S31508003BD803F01F03D840704700440258985D000850
-S31508003BE8044BDB69C3F30223034AD35C03F01F03C0
-S31508003BF8D840704700440258985D000800B585B05B
-S31508003C08C2B24F4BD358020EC0F304218A40134060
-S31508003C18CB4040EA03404B4B984228D033D8A3F50B
-S31508003C288133A3F58073984266D019D8A3F58033F3
-S31508003C38984251D003F5407398420FD1FFF780FF99
-S31508003C48414B9B69C3F30323404AD35C03F01F0324
-S31508003C58D840FFF7A9FFFFF7C3FF24E0002022E0BA
-S31508003C683B4B984248D003F57D43984209D1364BD9
-S31508003C781B6813F0005F59D001A8FFF7D1FE029818
-S31508003C8811E000200FE0334B98423FD00ED9324B53
-S31508003C98984242D003F5407398423ED0A3F5803344
-S31508003CA8984233D0002005B05DF804FBA3F58033AD
-S31508003CB8984203D003F5407398420BD1224B1B68F0
-S31508003CC813F0040F34D0204B1B68C3F3C1032348F1
-S31508003CD8D840E8E70020E6E7FFF732FF1A4B9B696A
-S31508003CE8C3F30323194AD35C03F01F03D840FFF72D
-S31508003CF85BFFFFF767FFD6E7134B1B6813F0006FE8
-S31508003D0812D001A8FFF704FE0298CCE70E4B1B68F1
-S31508003D1813F4807F0ED10020C5E70B4B1B6F13F0F9
-S31508003D28020F09D10020BEE70020BCE70020BAE749
-S31508003D380020B8E70A48B6E74FF40040B3E700BFE3
-S31508003D484C4402580803020700440258985D0008C4
-S31508003D580803010708000407080005070090D003B0
-S31508003D6800093D0001F00303032B24D011F0010FCD
-S31508003D780BD01D4BDA6822F03002DA60DA680243A3
-S31508003D88DA60DA6842F08802DA6011F0020F11D0B8
-S31508003D98154BD3F80C2122F03002C3F80C21D3F8BE
-S31508003DA80C211043C3F80C01D3F80C2142F0880201
-S31508003DB8C3F80C2170470C4BDA6822F03002DA6037
-S31508003DC8D3F80C2122F03002C3F80C21DA68024332
-S31508003DD8DA60D3F80C211043C3F80C019A6942F04B
-S31508003DE810029A61704700BF0020005230B411F0E3
-S31508003DF8010F0BD0104DEB6823F4E663EB60EC6813
-S31508003E0842EA00231C4344F08404EC6011F0020FD4
-S31508003E180FD00949D1F80C3123F4E663C1F80C31FF
-S31508003E28D1F80C3142EA0022134343F08403C1F85F
-S31508003E380C3130BC704700BF00200052F8B5474B1C
-S31508003E481B7D012B00F088800F460446434B012250
-S31508003E581A7500229A61436813F0010F0DD10026DE
-S31508003E68636813F0020F12D1CEB92368012B1BD051
-S31508003E784FF0FF333B60A56859E001214CF25030FA
-S31508003E88FDF7F6FF06460028EAD00126E8E70221EC
-S31508003E984CF25030FDF7ECFF0028E5D001262F4BF1
-S31508003EA800221A753046F8BD61682069FFF75AFF7F
-S31508003EB8636813F0010F12D1636813F0020FEED08E
-S31508003EC802214CF25030FDF7D3FF00B10126244AEF
-S31508003ED8D2F80C3123F00803C2F80C31DFE70121C8
-S31508003EE84CF25030FDF7C4FF00B101261C4AD368CE
-S31508003EF823F00803D360DFE701214CF25030FDF7C1
-S31508003F08B7FF0646164AD168164B0B40D3601CE025
-S31508003F1802214CF25030FDF7ABFF0646104AD2F89C
-S31508003F280C11104B0B40C2F80C319EB90135E368E9
-S31508003F38A2681344AB42B2D9226961682846FFF7DA
-S31508003F4855FF636813F0010FD6D1636813F0020FA3
-S31508003F58EBD0DDE73D60A2E70226A3E718190020A3
-S31508003F6800200052FBF8FFFF184AD2F8883043F4BD
-S31508003F787003C2F88830164B1A6842F001021A60B4
-S31508003F8800221A6118681349014019609A61DA61B2
-S31508003F981A629A62DA621A635A639A63DA631A6465
-S31508003FA85A64196821F4802119601A660A4B1A6836
-S31508003FB80A4B1340B3F1005F02D2094B01221A607B
-S31508003FC8024B4FF000629A60704700BF00ED00E0B0
-S31508003FD8004402587FEDF6EA0010005C0000FFFF77
-S31508003FE80881005198B108B50346D0F8B40210B153
-S31508003FF80020C3F8B40209B1C3F8B0121846012361
-S3150800400880F89C320270FCF7A5FA002008BD022049
-S31508004018704710B50446012380F89C32D0F8B432AC
-S315080040285B68017998472046FCF709FB2046FCF7A8
-S31508004038F6FA002010BD19B1C0F8B412002070476E
-S315080040480220704708B5FCF7F2FA002008BD08B543
-S31508004058D0F8B43233B11B68984708B9002008BDB0
-S315080040680220FCE70220FAE708B5D0F8B4325B6804
-S315080040789847002008BD38B5044600F52A7528462D
-S3150800408800F04EF90123C4F89432B4F8AE32C4F8F5
-S31508004098983294F8A81201F01F03012B0FD05AB2D0
-S315080040A83AB1022B10D001F080012046FCF7E2FA5B
-S315080040B803E02946204600F0E1FA002038BD2946E3
-S315080040C8204600F00FFBF8E72946204600F03AFBA1
-S315080040D8F3E738B50446A9BB1046D4F89432032B3F
-S315080040E803D0052B25D0002038E0D4F86031D4F861
-S315080040F8642193420DD99B1AC4F860319A4206D9AD
-S315080041089AB20146204600F06EFC002026E092B2DC
-S31508004118F7E7D4F8B4321B691BB194F89C22032A32
-S3150800412804D0204600F067FC002017E02046984790
-S31508004138F7E70025C4F8945229462046FCF79AFA68
-S3150800414828460BE00A46D0F8B4329B693BB190F88A
-S315080041589C12032905D111469847002038BD02202C
-S31508004168FCE70220FAE710B50446002956D110469E
-S31508004178D4F89432022B09D0002B18BF042B44D04C
-S3150800418894F8A032012B45D0002010BD236A626A34
-S3150800419893421BD8E169B1FBF2F302FB13132BB95F
-S315080041A88A4203D8D4F8983299421DD3D4F8B4323F
-S315080041B8DB681BB194F89C22032A23D08021204669
-S315080041C8FCF758FA204600F021FCD9E79A1A226229
-S315080041D892B20146204600F0FEFB00231A4619460D
-S315080041E82046FCF767FACBE700221146204600F07E
-S315080041F8F2FB0021C4F898120B460A462046FCF73B
-S3150800420859FABDE720469847D8E780212046FCF7A3
-S3150800421831FAB5E7002084F8A002B6E70A46D0F8CE
-S31508004228B4325B693BB190F89C12032905D1114653
-S3150800423898470020A9E70220A7E70220A5E770B556
-S315080042480446402300221146FCF701FA0125C4F862
-S3150800425858514026C4F86461334600228021204616
-S31508004268FCF7F5F9A561666284F89C520023C4F840
-S3150800427894326360C4F8A432D4F8B8322BB1D4F8AF
-S31508004288B4325B68002120469847002070BD017447
-S315080042980020704790F89C3280F89D32042380F8F5
-S315080042A89C320020704790F89C32042B01D00020DD
-S315080042B8704790F89D3280F89C32F8E708B590F870
-S315080042C89C32032B01D0002008BDD0F8B432DB6934
-S315080042D8002BF8D09847F6E700207047002070476B
-S315080042E80020704708B5012280F89C22D0F8B4222D
-S315080042F8526801799047002008BD002302781AB150
-S315080043080133DBB20130F9E71846704708B54B8820
-S31508004318012B00D008BDC0F8A43200F06CFBF9E701
-S315080043280B7803704B7843708B78CA7803EB0223B3
-S3150800433843800B794A7903EB022383808B79CA7900
-S3150800434803EB0223C380704710B504468021FCF7A7
-S3150800435891F900212046FCF78DF910BD30B583B0D8
-S3150800436805460C460023ADF806304A88130A013B71
-S31508004378062B00F2A480DFE803F004182CA2A28614
-S315080043889300D0F8B0321B680DF10601007C9847F7
-S31508004398BDF806201AB1E388002B40F09480E3881C
-S315080043A8002B00F09A8003B030BD037C43B9D0F8DF
-S315080043B8B4329B6A0DF10600984702234370E7E773
-S315080043C8D0F8B432DB6A0DF1060098470223437029
-S315080043D8DEE7D2B2052A52D8DFE802F003101D2A12
-S315080043E83744D0F8B0325B6823B10DF10601007C7A
-S315080043F89847CDE72146FFF7A7FFD4E7D0F8B032AC
-S315080044089B6823B10DF10601007C9847C0E7214651
-S31508004418FFF79AFFC7E7D0F8B032DB6823B10DF18A
-S315080044280601007C9847B3E72146FFF78DFFBAE7F0
-S31508004438D0F8B0321B6923B10DF10601007C984704
-S31508004448A6E72146FFF780FFADE7D0F8B0325B69EB
-S3150800445823B10DF10601007C984799E72146FFF735
-S3150800446873FFA0E7D0F8B0329B6923B10DF10601B6
-S31508004478007C98478CE72146FFF766FF93E72146B5
-S31508004488FFF762FF8FE7037C33B9D0F8B4325B6B6A
-S315080044980DF1060098477BE72146FFF755FF82E7A7
-S315080044A8037C43B9D0F8B4321B6B0DF10600984764
-S315080044B8072343706CE72146FFF746FF73E7214653
-S315080044C8FFF742FF6FE79A4228BF1A46ADF806205B
-S315080044D80146284600F072FA61E7284600F08BFA8A
-S315080044E861E738B504468B88F3B9CB88E3B94B88B6
-S315080044F87F2B19D803F07F0590F89C32032B0CD034
-S3150800450880F89E522946FCF7C5F8204600F073FA4B
-S3150800451835B1022384F89C3209E0FFF715FF06E057
-S31508004528012384F89C3202E02046FFF70DFF38BDC8
-S3150800453838B504460D468978284B197001290ED8CE
-S3150800454890F89C32022B0ED0032B21D02946FFF770
-S31508004558FBFE224B19782046FFF786FD02E029461E
-S31508004568FFF7F2FE38BD81B14160032380F89C321B
-S31508004578FFF76DFD022803D0204600F03CFAF1E764
-S3150800458829462046FFF7E0FEECE700F034FAE9E7AB
-S3150800459889B1436899421DD0D9B2FFF765FD0F4B1B
-S315080045A8197861602046FFF752FD02280DD020468B
-S315080045B800F021FAD6E7022380F89C324160FFF71B
-S315080045C853FD204600F017FACCE729462046FFF7A0
-S315080045D8BBFEC7E700F00FFAC4E700BF18050020BE
-S315080045E808B5CB88012B0CD190F89C325AB29AB1EF
-S315080045F8022B09D9032B0FD10122011D00F0DEF980
-S3150800460801E0FFF7A1FE08BD0146002341F8083F6F
-S31508004618012200F0D3F9F6E7FFF796FEF3E708B5A7
-S3150800462890F89C32013B022B12D8CB88022B0CD16E
-S315080046380123C360D0F8A4320BB10323C360022256
-S3150800464800F10C0100F0BAF908BDFFF77DFEFBE79B
-S31508004658FFF77AFEF8E708B590F89C32013B022B7B
-S3150800466809D84B88012B00D008BD0023C0F8A4320E
-S3150800467800F0C1F9F8E7FFF767FEF5E708B50B7824
-S3150800468803F06003202B05D0402B03D043B1FFF776
-S315080046985BFE03E0D0F8B4329B689847002008BD53
-S315080046A84B78092B1BD8DFE803F011171A141A08D8
-S315080046B8051A0E0BFFF752FEF0E7FFF712FFEDE7B4
-S315080046C8FFF736FFEAE7FFF78BFFE7E7FFF7A7FFEE
-S315080046D8E4E7FFF71BFEE1E7FFF7BDFFDEE7FFF7B5
-S315080046E833FEDBE738B505460C460B7803F060035E
-S315080046F8202B06D0402B04D01BB1FFF725FE00203F
-S3150800470838BD95F89C32013B022B16D82379012B24
-S315080047180ED8D5F8B4329B68214628469847E388C8
-S31508004728002BECD10028EAD1284600F064F9E6E720
-S3150800473821462846FFF708FEE1E721462846FFF7FF
-S3150800474803FEDCE738B504468A880B7803F060036D
-S31508004758202B08D0D0B2402B05D05BB12046FFF7F6
-S31508004768F3FD002005E0D4F8B4329B682046984744
-S31508004778002038BD202B13D04B78012B43D05DB2CF
-S31508004788002D73D0032B40F0F78094F89C32022B47
-S315080047980CD0032B21D02046FFF7D6FD0020E8E7EA
-S315080047A8D4F8B4329B6820469847E2E7B0F180030C
-S315080047B818BF0123002808BF00234BB1014620462D
-S315080047C8FBF758FF80212046FBF754FF0020D0E767
-S315080047D82046FFF7B9FD0020CBE74B884BB9B0F167
-S315080047E8800318BF0123002808BF00230BB1CB8814
-S315080047F823B1204600F0FFF80020BAE70146204614
-S31508004808FBF738FFF5E794F89C32022B06D0032B02
-S315080048181BD02046FFF798FD0020AAE7B0F18003D1
-S3150800482818BF0123002808BF00234BB101462046BC
-S31508004838FBF720FF80212046FBF71CFF002098E79E
-S315080048482046FFF781FD002093E74B88002B40F0B0
-S31508004858988010F07F0F04D1204600F0CCF800208D
-S3150800486887E701462046FBF70DFFF5E794F89C32E3
-S31508004878022B06D0032B2FD02046FFF765FD002014
-S3150800488877E7B0F1800318BF0123002808BF002383
-S315080048989BB912F0800F15D100F07F0000EB80005D
-S315080048A8830003F5A8712144043100250D6002220E
-S315080048B8204600F083F828465BE72046FFF744FDC4
-S315080048C8002056E700F07F0000EB8000830003F124
-S315080048D8100121440431E8E752B2002A24DB00F02B
-S315080048E80F0303EB83039D002544D5F858314BB3D2
-S315080048F8002A2CDB00F07F0202EB8202930003F504
-S31508004908A87525440435802814BF002301230028E8
-S3150800491808BF01232BB300232B6002222946204611
-S3150800492800F04CF8002024E700F00F0303EB83039C
-S315080049389D002544AB69002BDAD12046FFF704FD14
-S31508004948002016E72046FFF7FFFC002011E700F0D5
-S315080049587F0202EB8202930003F110052544043511
-S31508004968D1E701462046FBF731FE10B101232B603B
-S31508004978D3E700232B60D0E72046FFF7E5FC0020A5
-S31508004988F7E60020F5E6C0B170B50D4616460446AA
-S31508004998FFF7B3FC013040003080287003236B70A2
-S315080049A80223217841B101345A1CD2B2E9540233A0
-S315080049B8DBB20021A954F4E770BD704710B5134659
-S315080049C80222C0F89422C36103620A460021FBF753
-S315080049D869FE002010BD08B513460A460021FBF7F4
-S315080049E861FE002008BD08B513460A460021FBF7F4
-S315080049F861FE002008BD08B50423C0F894320023D8
-S31508004A081A461946FBF74EFE002008BD08B50523C9
-S31508004A18C0F8943200231A461946FBF74BFE0020C5
-S31508004A2808BD0000014B00225A7070471C0500207B
-S31508004A38034BFE22DA7018710222A3F84420704745
-S31508004A481C05002010B5054C00232370FFF7EAFF64
-S31508004A58FF23E3700123A4F8443010BD1C05002089
-S31508004A68064BFF22DA7000221A71597859719A7121
-S31508004A78DA711A720622A3F8442070471C0500202A
-S31508004A8808B50020FFF7D4FF08BD0000074BFF2232
-S31508004A98DA70074A9A6400221A715A719A710722BB
-S31508004AA8C3F807200822A3F8442070471C050020ED
-S31508004AB8B85D0008044BFF22DA7042689A6401223E
-S31508004AC8A3F84420704700BF1C05002008B531200C
-S31508004AD8FFF7AEFF08BD000038B5084CFF23E370A2
-S31508004AE800252571657100F00BFAA071E57125722C
-S31508004AF865720723A4F8443038BD00BF1C0500209A
-S31508004B0838B5FFF78FFF0E4C01252570FF23E37094
-S31508004B18102323710023637100F0F2F9A07100F0E5
-S31508004B2801FAE07100F0FEF9C0F3072020726572F9
-S31508004B38A5720823A4F8443000F07CFA38BD00BFF3
-S31508004B481C05002038B5054600F0DAF96A7890425F
-S31508004B580FD90A4CA16C201D00F098FCFF23E370BE
-S31508004B686A78A36C1344A3646B780133A4F84430B9
-S31508004B7838BD2220FFF75CFFFAE700BF1C050020B6
-S31508004B8838B5044600F0BCF96378984211D96168CB
-S31508004B980A4DA9646278281D00F078FCFF23EB709B
-S31508004BA86278AB6C1344AB6463780133A5F8443078
-S31508004BB838BD2220FFF73CFFFAE700BF1C05002096
-S31508004BC8F8B50546174600244E1E39B115F8013BB7
-S31508004BD81C44E4B200F0DCF93146F5E73C600120F4
-S31508004BE8F8BD000010B5084CFF23E370E21D4168C4
-S31508004BF8A06CFFF7E5FF207100236371A3710823F2
-S31508004C08A4F8443010BD00BF1C05002038B5054679
-S31508004C180D4B9C6C00F074F96A1C411E204600F086
-S31508004C280DFA60B1084CFF23E37000F069F9013802
-S31508004C38A36C0344A3640123A4F8443038BD312087
-S31508004C48FFF7F6FEFAE700BF1C05002010B5044674
-S31508004C5800F056F901386378984213DD114BFF22A4
-S31508004C68DA700122A3F84420617879B1A21C0D4BA9
-S31508004C78986C00F0E3F988B161780A4A936C0B449A
-S31508004C88936410BD2220FFF7D3FEFAE700F0E6F991
-S31508004C980028F6D13120FFF7CBFEF2E73120FFF7DF
-S31508004CA8C7FEEEE71C05002008B54168074B986C57
-S31508004CB800F0C8F930B1054BFF22DA700122A3F8D3
-S31508004CC8442008BD3120FFF7B3FEFAE71C0500208B
-S31508004CD808B500F0BBFB034BFF22DA700122A3F8E4
-S31508004CE8442008BD1C05002008B589B200F0E6F87E
-S31508004CF808BD0000054B00221A709A6483F8432001
-S31508004D08A3F844209A705A70704700BF1C05002003
-S31508004D18034B1B780BB1012070470020704700BF72
-S31508004D281C050020024B002283F84320704700BF69
-S31508004D381C05002008B50378FF2B23D0354A1278BE
-S31508004D48012A2BD1C93B352B53D8DFE803F040524B
-S31508004D58524F52524C43494652525252525252524A
-S31508004D68525252525252525252525252525252520D
-S31508004D785252525252525252312B282E52525234B1
-S31508004D8852373A3DFFF7BCFE224B93F84330012BC6
-S31508004D9833D0204BB3F94410002932DC08BDFFF79D
-S31508004DA8D1FEF1E7FFF7ECFEEEE7FFF783FEEBE748
-S31508004DB8FFF718FFE8E7FFF769FEE5E7FFF760FE84
-S31508004DC8E2E7FFF74DFEDFE7FFF73CFEDCE7FFF714
-S31508004DD81DFFD9E7FFF73AFFD6E7FFF77DFED3E7CA
-S31508004DE8FFF762FFD0E7FFF773FFCDE7FFF76EFE21
-S31508004DF8CAE72020FFF71CFEC6E71020FFF718FEB3
-S31508004E08C7E71846012380F843300330FFF76CFFDD
-S31508004E18C4E700BF1C05002010B5FFF76BFF00F0BC
-S31508004E2885FD064C0123237000F05AFE00232370E3
-S31508004E3800F0DCF90223237010BD00BFEC04002043
-S31508004E4800B583B00DF10701184800F0FDFD0128EB
-S31508004E5810D00DF10701154800F07AFE012812D086
-S31508004E680DF10701114800F041FA012814D003B0E2
-S31508004E785DF804FB0E4B01221A709DF807100B48C3
-S31508004E88FFF758FFE5E70A4B00221A709DF8071046
-S31508004E980648FFF74FFFE3E7054B02221A709DF80D
-S31508004EA807100248FFF746FFE1E700BF680500203C
-S31508004EB8EC04002008B500F0DFF908BD38B504464B
-S31508004EC80D460E4B1B78012B09D00C4B1B7853B19A
-S31508004ED80A4B1B78022B0BD0FFF724FF38BDC9B243
-S31508004EE800F080FDF1E7E9B2204600F015FEEFE78D
-S31508004EF8E9B2204600F0D0F9EEE700BFEC0400203E
-S31508004F08074B1B78022B05D0032B05D0012B05D0A0
-S31508004F18402070473F207047002070470820704798
-S31508004F28EC040020074B1B78022B05D0032B05D071
-S31508004F38012B05D0402070473F2070470020704756
-S31508004F4808207047EC04002008B5FFF7E1FE034681
-S31508004F5800B10123184608BD08B500F073FA00F039
-S31508004F6813F800F053FE00F065F8FFF755FF00F058
-S31508004F7851F808BD08B500F00BF800F05BFEFFF71E
-S31508004F885FFF00F009F808BD08B5FBF7ABFD08BDDB
-S31508004F9808B5FBF7ACFD08BD08B5FFF7D5FF01282E
-S31508004FA803D00B4B1B78012B00D008BD00F050FE30
-S31508004FB8084B1B68084A1268134403F5FA739842A3
-S31508004FC8F3D3034B00221A7000F040FAEDE700BF4E
-S31508004FD8AC050020A8050020B0050020014B186084
-S31508004FE8704700BFA8050020014B1868704700BF26
-S31508004FF8A805002008B5054B1B78012B00D008BD6D
-S3150800500800F026FE024B1860F9E700BFAC05002041
-S31508005018B005002008B5044B01221A70FFF7EAFF0D
-S31508005028FFF7BAFF08BD00BFAC05002008B5FFF7B3
-S31508005038AFFFFCE708B500F05FFB08BD08B500F050
-S3150800504867FB08BD08B500F09DFB08BD08B500F06C
-S31508005058E3FB08BD08B500F02DFC08BD08B500F04F
-S31508005068B5FB034608B9184608BD00F001FC034617
-S31508005078F9E70000094B03F11801002232B19A74C6
-S3150800508800225A61064B054A1A6070479A74596194
-S31508005098183318310132D2B2F0E700BFF405002000
-S315080050A8240600200A4B1B6883B110B45C69084AB9
-S315080050B8146019749860D86000225A741860013907
-S315080050C808445860987C5DF8044B7047FF20704781
-S315080050D82406002038B504460D4601281CD8620067
-S315080050E82244D100114B0B445A7C1B7C9A4219D096
-S315080050F80E4B0B44DA6815705A7C01325A74DA6812
-S315080051080132DA605B689A420ED9084A084651584D
-S315080051180244D160012038BD4FF4E1710448FFF715
-S3150800512885FFDCE70020F6E70120F4E7F405002010
-S31508005138C05D000808B50146024B1878FFF7CAFF94
-S3150800514808BD00BF2806002038B504460D460128C4
-S315080051581ED804EB4403DA00124B13445B7CEBB10C
-S3150800516862002244D1000F4B0B449A6812782A70C1
-S315080051785A7C013A5A749A6801329A605B689A426C
-S315080051880ED9084A0846515802449160012006E09B
-S315080051984FF4F2710448FFF749FFDAE7002038BDF3
-S315080051A80120FCE7F4050020C05D000808B50146A3
-S315080051B8024B1878FFF7C8FF08BD00BF6C06002029
-S315080051C810B50446012806D804EB4404E200054B4A
-S315080051D81344587C10BD4FF401710348FFF726FFA6
-S315080051E8F2E700BFF4050020C05D000838B5FFF7F0
-S315080051F841FF1B4C4021601CFFF754FF2070194DD6
-S315080052084021681CFFF74EFF28702378FF2B1DD016
-S31508005218FF281BD0144C002214492046FEF7E2FE4C
-S3150800522813492046FEF707FF0120FBF764FC2046D2
-S31508005238FEF708FFFCF7F6FED4F8C002FDF7BEFC39
-S31508005248FFF7D2FEB0F5FA6F05D338BD85210948B0
-S31508005258FFF7ECFEDEE74FF4FA60FFF7BFFEF4E768
-S31508005268280600206C060020B006002090040020BE
-S315080052782C040020C05D000810B5064CD4F8C002FE
-S31508005288FDF7BAFC2046FEF7C4FE0020FBF733FC00
-S3150800529810BD00BFB006002070B506460D463F296A
-S315080052A806D82846FFF746FF012806D100240FE04E
-S315080052B8BB210D48FFF7BAFEF3E7BF210A48FFF7F7
-S315080052C8B5FEF3E7C8210848FFF7B0FE0134A4B2D3
-S315080052D8ABB2A34207D9FFF75BFE305DFFF72AFF9B
-S315080052E80128F3D0EEE770BDC05D000870B5064624
-S315080052F80D461F4BD3F8C002FDF7ECF91D4B1C7879
-S315080053089CB91D48FFF752FF012801D0204670BDF9
-S31508005318194B1B78013BDBB23E2BF7D8154B0122FC
-S315080053281A70164B00221A70F0E7144B1B780133D3
-S3150800533811481844FFF73AFF0446012801D000240B
-S31508005348E4E70E4B1A780132D2B21A700A4B1B7868
-S315080053589A4201D00024D9E70949304600F096F860
-S31508005368044B00221A70054B1B782B70CEE700BF3A
-S31508005378B0060020B409002074090020B5090020E9
-S315080053887509002030B583B0144B1878FFF718FF55
-S3150800539808B30546402800D9402500240AE04FF4FA
-S315080053A8A4710F48FFF742FE9DF807200D4B1A55C2
-S315080053B80134E4B2A54208D90DF10701074B18785C
-S315080053C8FFF7C2FE0128EFD0E9E7ABB2054A81210B
-S315080053D80548FBF767F903B030BD00BF280600206B
-S315080053E8C05D0008B4050020B006002070B5044664
-S315080053F8FBF7FAFB064621460F48FBF7FEF885B287
-S31508005408002406E04FF4B5710C48FFF70FFE013487
-S31508005418A4B2AC4207D2315D094B1878FFF75AFE99
-S315080054280128F4D0EEE7FBF7DFFB4023024601210B
-S315080054380148FBF73FF970BDB0060020C05D0008BB
-S315080054486C06002008B500F010FC08BD10B5FFF77B
-S31508005458FDFD00B910BDFBF737FB0028FAD0FFF7AA
-S3150800546829FDFBF793FC00F0C9FBFFF7F3FD054B95
-S315080054780340054A9360FFF7EDFD446800F0F7FB23
-S31508005488A047E7E780FFFF1F00ED00E070B50D466F
-S315080054980446531E9EB23AB115F8013B04F8013B7F
-S315080054A8FFF776FD3246F4E770BD000038B50546C5
-S315080054B8002401E00134E4B20E2C12D8FFF768FD87
-S315080054C804EB44029300084AD358AB42F2D804EBDB
-S315080054D844029100044A0A4452681344AB42E9D983
-S315080054E800E0FF24204638BDE85D000808B5C1F38A
-S315080054F8090363B903688B4201D1012008E040F823
-S31508005508041B4FF48062FFF7C1FF012000E000206A
-S3150800551808BD2DE9F04107460068FFF7C7FFFF28D1
-S3150800552804D14FF000084046BDE8F081FCF754FC6A
-S3150800553800264FF0010805E04FF00008B8F1000F03
-S315080055481DD001361F2E1AD83D68740125443C44DF
-S315080055580434FFF71DFD224629460120FCF704FD01
-S3150800556858B900231F2BE9D8595DC9B2E25CD2B2F3
-S315080055789142E1D10133DBB2F4E74FF00008FCF7BA
-S3150800558859FCD0E770B50E460E4B984212D0054620
-S315080055980D4B994209D10B4C254624B1314628466C
-S315080055A8FFF7A4FF58B1204670BDFFF7B2FF20B138
-S315080055B82C46F2E7054C2546EFE70024EDE70024DC
-S315080055C8F1E700BFBC0D002000000208B80900205A
-S315080055D82DE9F84306460C4617461D46DFF884802B
-S315080055E801EA08080368B3F1FF3F0AD03368434560
-S315080055F80ED14FF00109B9F1010F12D04846BDE89E
-S31508005608F8834146FFF772FF81460028F3D0EDE795
-S3150800561841463046FFF7B6FF0646E8B14FF001099E
-S31508005628E9E73368E41A3444043405E017F8013B1B
-S3150800563804F8013B013DE1D0FFF7AAFC331DE31A44
-S31508005648B3F5806FF2D308F580613046FFF79AFF05
-S31508005658064620B1041DE9E74FF00009CEE74FF0EA
-S315080056680009CBE700FCFFFF70B586B004460D4677
-S3150800567800230093884203D80E2938D8012600E06B
-S31508005688002616B9304606B070BDFCF7A5FB01E042
-S315080056980134E4B2AC4227D8FFF77AFC154963000F
-S315080056A823449A008B188A585B68002B18BFB2F1F6
-S315080056B8FF3F18D000230193202305930A46630069
-S315080056C81819810008461144497A02910244137A46
-S315080056D8039301230493694601A8FEF7AFFB002844
-S315080056E8D6D0002600E00026FCF7A4FBCAE7002669
-S315080056F8C8E700BFE85D00084FF0FF33024A1360A9
-S31508005708024A1360704700BFB8090020BC0D002084
-S3150800571870B504460D4616464A1E154B1B1A9A427C
-S3150800572803D9002001280ED070BDFFF7BFFEFF2859
-S3150800573801D10020F8E728190138FFF7B7FEFF2836
-S3150800574814D00120EEE70B4B23400B4A934206D0B0
-S315080057582B46324621460948FFF73AFFE4E72B4627
-S31508005768324621460648FFF733FFDDE70020DBE728
-S31508005778FFFF1F0800FCFFFF00000208B809002009
-S31508005788BC0D002070B54A1E0F4B1B1A9A4205D944
-S31508005798FF210E460020012812D070BD05460C468A
-S315080057A8FFF784FE064660190138FFF77FFE0146B3
-S315080057B8FF2818BFFF2E01D00120ECE70020EAE7F2
-S315080057C83046FFF751FFE8E7FFFF1F08104B1B6835
-S315080057D8B3F1FF3F01D10120704700B583B00C4AE9
-S315080057E8536891680B44D1680B4411690B44516995
-S315080057F80B4491690B44D26913445B42019301AA8D
-S3150800580804210448FFF784FF03B05DF804FB00BFD2
-S31508005818BC0D0020980202080D4B1B680D4A126839
-S315080058281A440D4B1B6813440C4A126813440C4A55
-S3150800583812681A440B4B1B681A440B4B1B68134413
-S315080058480A4A1268DA4201D10120704700207047D7
-S315080058580000020804000208080002080C000208F2
-S315080058681000020814000208180002089802020824
-S3150800587808B50E4B1B68B3F1FF3F07D10C4B1B68E5
-S31508005888B3F1FF3F09D10123184608BD0748FFF7BA
-S3150800589840FE03460028F7D0F0E70548FFF739FE2B
-S315080058A803460028F0D00123EEE700BFBC0D002010
-S315080058B8B80900200048704700000208F0B4194DDE
-S315080058C82C6D24F040542C65002401E00134E4B220
-S315080058D8112C23D8144D15F8146005EB44056F7878
-S315080058E8F51905FB00054FF4FA5CBCFBF5FC05FB4E
-S315080058F80CF5B5F5FA5FE9D135463D4405FB000CCC
-S315080059084FF4FA55B5FBFCF50D80013DADB2B5F57A
-S31508005918007FDBD216701F70012000E00020F0BC63
-S31508005928704700BF00440258C45E000870B58AB0C4
-S315080059380023ADF826308DF825308DF8243009ABCC
-S315080059480DF125020DF126014FF4FA70FFF7B6FF9F
-S3150800595800283CD0204C214B23600025A560E56033
-S31508005968012626746574A574BDF826306361A66198
-S315080059789DF82530E3619DF8243023626662A662A5
-S31508005988E66226636563A663E563256404236364A0
-S31508005998A564E36426656365A565E66525666566A3
-S315080059A8A3662046FDF7CCFB0195029503960723C7
-S315080059B8049340F2676305930693079501A9204661
-S315080059C8FDF708FD2046FDF748FD0AB070BDB82169
-S315080059D80348FFF72BFBBDE7C011002000A00040D5
-S315080059E89C5E000810B58AB040F2E1730193002363
-S315080059F8029303930904049105930693079308935E
-S31508005A08522309930123024601A90E48FDF73FFDD3
-S31508005A1808B10AB010BD01210A48FDF76EFD002835
-S31508005A28F7D100F015F900F1320401210548FDF710
-S31508005A386AFE0028EDD0FFF7ABFA00F009F9A04294
-S31508005A48F3D9E6E7C011002030B58BB004460D46F9
-S31508005A5800211048FDF730FE10B900200BB030BD04
-S31508005A6823466A4600210B48FDF75AFD68B9009A8D
-S31508005A7840F267639A4201D00020EFE7019B33B9E9
-S31508005A889DF80E302B700120E8E70020E6E7002095
-S31508005A98E4E700BFC0110020054BDB6913F0200FAF
-S31508005AA804D0034B5B6A03700120704700207047D7
-S31508005AB80048004010B5094B986200F0C9F800F193
-S31508005AC80A04064BDB6913F0800F05D1FFF760FA65
-S31508005AD800F0BEF8A042F4D910BD00BF0048004047
-S31508005AE810B588B0002300934FF4614201920293DF
-S31508005AF8039304930C22059206930793054C69466B
-S31508005B082046FBF737FA236843F00103236008B0F9
-S31508005B1810BD00BF0048004070B506460D4640292E
-S31508005B280ED82846FFF7C6FF0024ABB2A3420CD905
-S31508005B38FFF72EFA305DFFF7BDFF0134A4B2F4E78C
-S31508005B4882210248FFF772FAEBE770BDE85E0008A3
-S31508005B5870B5254B1C78BCB92448FFF79DFF01286A
-S31508005B6801D0204670BD214B1B78013BDBB23F2B89
-S31508005B78F7D800F06DF81E4B18601E4B00221A70F5
-S31508005B88194B01221A70ECE706460D46194B1B7885
-S31508005B98013316481844FFF77FFF0446012815D134
-S31508005BA8144B1A780132D2B21A70104B1B789A42E3
-S31508005BB801D00024D5E710493046FFF767FC0A4BA1
-S31508005BC800221A700B4B1B782B70CAE700F040F8B6
-S31508005BD8074B1B686433984203D90024024B1C7090
-S31508005BE8BFE70024BDE700BFA1120020601200200D
-S31508005BF8A4120020A212002061120020024B0022E3
-S31508005C081A605A609A60704710E000E008B5FFF716
-S31508005C18F5FF054B054A5A6000229A600521196066
-S31508005C28034B1A6008BD00BF10E000E0FF520700EA
-S31508005C38A8120020044B1B6813F4803F03D0034ABC
-S31508005C48136801331360704710E000E0A8120020BB
-S31508005C5808B5FFF7EFFF014B186808BDA812002022
-S31508005C6808B5FFF7F5FF08BD704772B6704762B604
-S31508005C7870470A44914200F1FF3300D1704710B5C6
-S31508005C8811F8014B03F8014F9142F9D110BD0000F4
-S31508005C98F8B500BFF8BC08BC9E467047F8B500BF03
-S30D08005CA8F8BC08BC9E467047D3
-S31508005CB000000000000000000000000000000000D6
-S31508005CC000000000010000000200000003000000C0
-S31508005CD004000000000000000500000000000000AD
-S31508005CE000000000000000000600000000000000A0
-S31508005CF0000000000000000007000000000000206F
-S31508005D00757362645F636F6E662E63006D61696E9C
-S31508005D102E63000044656661756C740057696E559C
-S31508005D2053422042756C6B20496E746572666163D6
-S31508005D30650000004F70656E424C542055736572BD
-S31508005D400000000057696E5553422042756C6B205F
-S31508005D5044657669636500000100000002000000E2
-S31508005D600400000006000000080000000A00000009
-S31508005D700C00000010000000200000004000000099
-S31508005D808000000000010000000102030405060768
-S31508005D90080C10141820304000000000010203040B
-S31508005DA001020304060708090000000001020304B3
-S31508005DB001020304060708094F70656E424C540039
-S31508005DC02E2E2F2E2E2F2E2E2F536F757263652F84
-S31508005DD041524D434D375F53544D333248372F7533
-S31508005DE073622E6300000000000002080000020033
-S31508005DF00101000000000408000002000201000082
-S31508005E000000060800000200030100000000080860
-S31508005E10000002000401000000000A080000020059
-S31508005E200501000000000C08000002000601000041
-S31508005E3000000E080000020007010000000010081C
-S31508005E400000020000020000000012080000020024
-S31508005E50010200000000140800000200020200000F
-S31508005E6000001608000002000302000000001808DF
-S31508005E70000002000402000000001A0800000200E8
-S31508005E800502000000001C080000020006020000CF
-S31508005E9000001E0800000200070200002E2E2F2E0A
-S31508005EA02E2F2E2E2F536F757263652F41524D4339
-S31508005EB04D375F53544D333248372F63616E2E6327
-S31508005EC0000000000502060206030703080309038B
-S31508005ED009040A040B040C040C050D050E050F0530
-S31508005EE00F061006100710082E2E2F2E2E2F2E2ED8
-S31508005EF02F536F757263652F41524D434D375F536C
-S31508005F00544D333248372F72733233322E630000C2
-S30D08005F1021030008BD02000888
-S30908005F1899020008D4
-S31508005F1C00000000EC02002054030020BC03002003
-S31508005F2C0000000000000000000000000000000057
-S31508005F3C0000000000000000000000000000000047
-S31508005F4C0000000000000000000000000000000037
-S31508005F5C0000000000000000000000000000000027
-S31508005F6C0000000000000000000000000000000017
-S31508005F7C0000000000000000000000000000000007
-S31508005F8C00000000000000000000000000000000F7
-S31508005F9C00000000000000000000000000000000E7
-S31508005FAC00000000000000000000000000000000D7
-S31508005FBC00000000000000000100000000000000C6
-S31508005FCC0E33CDAB34126DE6ECDE05000B0000008B
-S31508005FDC00000000000000000000000000000000A7
-S31508005FEC0000000000000000000000000000000097
-S31508005FFC0000000000000000000000000000000087
-S3150800600C0000000000000000000000000000000076
-S3150800601C0000000000000000000000000000000066
-S3150800602C0000000000000000000000000000000056
-S3150800603C0000000000000000000000000000000046
-S3150800604C0000000000000000000000000000000036
-S3150800605C0000000000000000000000000000000026
-S3150800606C0000000000000000000000000000000016
-S3150800607C0000000000000000000000000000000006
-S3150800608C00000000000000000000000000000000F6
-S3150800609C00000000000000000000000000000000E6
-S315080060AC00000000000000000000000000000000D6
-S315080060BC00000000000000000000000000000000C6
-S315080060CC00000000000000000000000000000000B6
-S315080060DC00000000000000000000000000000000A6
-S315080060EC0000000000000000000000000000000096
-S315080060FC0000000000000000000000000000000086
-S3150800610C0000000000000000000000000000000075
-S3150800611C0000000000000000000000000000000065
-S3150800612C0000000000000000000000000000000055
-S3150800613C0000000000000000000000000000000045
-S3150800614C0000000000000000000000000000000035
-S3150800615C0000000000000000000000000000000025
-S3150800616C0000000000000000000000000000000015
-S3150800617C0000000000000000000000000000000005
-S3150800618C00000000000000000000000000000000F5
-S3150800619C00000000000000000000000000000000E5
-S315080061AC00000000000000000000000000000000D5
-S315080061BC00000000000000000000000000000000C5
-S315080061CC00000000000000000000000000000000B5
-S315080061DC00000000000000000000000000000000A5
-S315080061EC0000000000000000000000000000000095
-S315080061FC0000000000000000000000000000000085
-S3150800620C0000000000000000000000000000000074
-S3150800621C0000000000000000000000000000000064
-S3150800622C0000000000000000000000000000000054
-S3150800623C0000000000000000000000000000000044
-S3150800624C0000000000000000000000000000000034
-S3150800625C0000000000000000000000000000000024
-S3150800626C0000000000000000000000000000000014
-S3150800627C0000000000000000000000000000000004
-S3150800628C00000000000000000000000000000000F4
-S3150800629C00000000000000000000000000000000E4
-S315080062AC00000000000000000000000000000000D4
-S315080062BC00000000000000000000000000000000C4
-S315080062CC00000000000000000000000000000000B4
-S315080062DC00000000000000000000000000000000A4
-S315080062EC0000000000000000000000000000000094
-S315080062FC0000000000000000000000000000000084
-S3150800630C0000000000000000000000000000000073
-S3150800631C0000000000000000000000000000000063
-S3150800632C0000000000000000000000000000000053
-S3150800633C0000000000000000AC120020C10B000891
-S3150800634CA90B0008490B000800000000000000001B
-S3150800635C310B00083B0B00081D0B00080000000061
-S3150800636C0000000000000000050B000800000000FB
-S3150800637C110B000809022000010100C032090400B3
-S3150800638C0002FF000000070581024000FF07050117
-S3150800639C024000FF0A06000200000040010000004F
-S315080063ACF90B0008050C0008B50C0008910C000840
-S315080063BC7D0C0008D10C0008F50C0008120100022F
-S315080063CC00000040501DAC600002010203010000F1
-S315080063DC040309041A030000000000000000000072
-S315080063EC0000000000000000000000000000010092
-S315080063FC100000000090D0030090D00304000000A9
+S31508000428094B9A42F9D300F033FDFFF751FF04F060
+S315080004383FF8704700000220345F000800000020DB
+S31508000448F0040020F004002034190020FEE710B557
+S3150800045813460222C0F89422C36103620A460021A1
+S3150800046804F0D4FA002010BD08B513460A46002140
+S3150800047804F0CCFA002008BD08B513460A46002140
+S3150800048804F0CCFA002008BD08B50423C0F8943255
+S3150800049800231A46194604F0B9FA002008BD08B51B
+S315080004A80523C0F8943200231A46194604F0B6FA0A
+S315080004B8002008BD002302781AB10133DBB20130E7
+S315080004C8F9E71846704708B54B88012B00D008BDD0
+S315080004D8C0F8A432FFF7D8FFF9E70B7803704B7812
+S315080004E843708B78CA7803EB022343800B794A79E1
+S315080004F803EB022383808B79CA7903EB0223C38033
+S31508000508704710B50446802104F068FA0021204691
+S3150800051804F064FA10BD30B583B005460C460023CE
+S31508000528ADF806304A88130A013B062B00F2A48068
+S31508000538DFE803F004182CA2A2869300D0F8B0329C
+S315080005481B680DF10601007C9847BDF806201AB10C
+S31508000558E388002B40F09480E388002B00F09A800B
+S3150800056803B030BD037C43B9D0F8B4329B6A0DF1A9
+S315080005780600984702234370E7E7D0F8B432DB6AE7
+S315080005880DF10600984702234370DEE7D2B2052A22
+S3150800059852D8DFE802F003101D2A3744D0F8B032E3
+S315080005A85B6823B10DF10601007C9847CDE7214623
+S315080005B8FFF7A7FFD4E7D0F8B0329B6823B10DF14F
+S315080005C80601007C9847C0E72146FFF79AFFC7E768
+S315080005D8D0F8B032DB6823B10DF10601007C9847E4
+S315080005E8B3E72146FFF78DFFBAE7D0F8B0321B69A3
+S315080005F823B10DF10601007C9847A6E72146FFF7C7
+S3150800060880FFADE7D0F8B0325B6923B10DF106017A
+S31508000618007C984799E72146FFF773FFA0E7D0F8CB
+S31508000628B0329B6923B10DF10601007C98478CE727
+S315080006382146FFF766FF93E72146FFF762FF8FE734
+S31508000648037C33B9D0F8B4325B6B0DF106009847D2
+S315080006587BE72146FFF755FF82E7037C43B9D0F8C5
+S31508000668B4321B6B0DF106009847072343706CE7F5
+S315080006782146FFF746FF73E72146FFF742FF6FE774
+S315080006889A4228BF1A46ADF8062001462846FFF7BB
+S31508000698DEFE61E72846FFF7F7FE61E738B5044648
+S315080006A88B88F3B9CB88E3B94B887F2B19D803F025
+S315080006B87F0590F89C32032B0CD080F89E52294669
+S315080006C804F09CF92046FFF7DFFE35B1022384F8CB
+S315080006D89C3209E0FFF715FF06E0012384F89C32EF
+S315080006E802E02046FFF70DFF38BD000038B504467E
+S315080006F80D468978284B197001290ED890F89C322E
+S31508000708022B0ED0032B21D02946FFF7FAFE224BDF
+S315080007181978204600F072FA02E02946FFF7F1FE3A
+S3150800072838BD81B14160032380F89C3200F059FA3C
+S31508000738022803D02046FFF7A7FEF1E729462046F8
+S31508000748FFF7DFFEECE7FFF79FFEE9E789B14368A5
+S3150800075899421DD0D9B200F051FA0F4B1978616049
+S31508000768204600F03EFA02280DD02046FFF78CFEF8
+S31508000778D6E7022380F89C32416000F03FFA20460B
+S31508000788FFF782FECCE729462046FFF7BAFEC7E7F9
+S31508000798FFF77AFEC4E700BF0C05002008B5CB882A
+S315080007A8012B0CD190F89C325AB29AB1022B09D96E
+S315080007B8032B0FD10122011DFFF749FE01E0FFF7C0
+S315080007C8A0FE08BD0146002341F8083F0122FFF7AD
+S315080007D83EFEF6E7FFF795FEF3E708B590F89C3274
+S315080007E8013B022B12D8CB88022B0CD10123C360FC
+S315080007F8D0F8A4320BB10323C360022200F10C011E
+S31508000808FFF725FE08BDFFF77CFEFBE7FFF779FE35
+S31508000818F8E708B590F89C32013B022B09D84B88B3
+S31508000828012B00D008BD0023C0F8A432FFF72CFE20
+S31508000838F8E7FFF766FEF5E708B50B7803F06003F7
+S31508000848202B05D0402B03D043B1FFF75AFE03E00F
+S31508000858D0F8B4329B689847002008BD4B78092B16
+S315080008681BD8DFE803F011171A141A08051A0E0B15
+S31508000878FFF751FEF0E7FFF711FFEDE7FFF736FF41
+S31508000888EAE7FFF78BFFE7E7FFF7A7FFE4E7FFF7D6
+S315080008981AFEE1E7FFF7BDFFDEE7FFF732FEDBE703
+S315080008A838B505460C460B7803F06003202B06D0AE
+S315080008B8402B04D01BB1FFF724FE002038BD95F85D
+S315080008C89C32013B022B16D82379012B0ED8D5F872
+S315080008D8B4329B68214628469847E388002BECD112
+S315080008E80028EAD12846FFF7CFFDE6E7214628463D
+S315080008F8FFF707FEE1E721462846FFF702FEDCE791
+S3150800090838B504468A880B7803F06003202B08D08C
+S31508000918D0B2402B05D05BB12046FFF7F2FD002088
+S3150800092805E0D4F8B4329B6820469847002038BDBD
+S31508000938202B13D04B78012B43D05DB2002D73D0F2
+S31508000948032B40F0F78094F89C32022B0CD0032B2B
+S3150800095821D02046FFF7D5FD0020E8E7D4F8B432C1
+S315080009689B6820469847E2E7B0F1800318BF012341
+S31508000978002808BF00234BB10146204604F02EF88C
+S315080009888021204604F02AF80020D0E72046FFF701
+S31508000998B8FD0020CBE74B884BB9B0F1800318BFE8
+S315080009A80123002808BF00230BB1CB8823B12046B2
+S315080009B8FFF76AFD0020BAE70146204604F00EF85C
+S315080009C8F5E794F89C32022B06D0032B1BD0204659
+S315080009D8FFF797FD0020AAE7B0F1800318BF0123A7
+S315080009E8002808BF00234BB10146204603F0F6FF4E
+S315080009F88021204603F0F2FF002098E72046FFF7FB
+S31508000A0880FD002093E74B88002B40F0988010F073
+S31508000A187F0F04D12046FFF737FD002087E70146F8
+S31508000A28204603F0E3FFF5E794F89C32022B06D03C
+S31508000A38032B2FD02046FFF764FD002077E7B0F197
+S31508000A48800318BF0123002808BF00239BB912F0AA
+S31508000A58800F15D100F07F0000EB8000830003F5B6
+S31508000A68A8712144043100250D6002222046FFF7AB
+S31508000A78EEFC28465BE72046FFF743FD002056E7CD
+S31508000A8800F07F0000EB8000830003F11001214489
+S31508000A980431E8E752B2002A24DB00F00F0303EB1F
+S31508000AA883039D002544D5F858314BB3002A2CDB1F
+S31508000AB800F07F0202EB8202930003F5A87525442D
+S31508000AC80435802814BF00230123002808BF012302
+S31508000AD82BB300232B60022229462046FFF7B7FCD2
+S31508000AE8002024E700F00F0303EB83039D00254449
+S31508000AF8AB69002BDAD12046FFF703FD002016E77D
+S31508000B082046FFF7FEFC002011E700F07F0202EB03
+S31508000B188202930003F1100525440435D1E70146FE
+S31508000B28204603F007FF10B101232B60D3E7002303
+S31508000B382B60D0E72046FFF7E4FC0020F7E6002004
+S31508000B48F5E6C0B170B50D4616460446FFF7B2FC81
+S31508000B58013040003080287003236B700223217807
+S31508000B6841B101345A1CD2B2E9540233DBB200212E
+S31508000B78A954F4E770BD704798B108B50346D0F88C
+S31508000B88B40210B10020C3F8B40209B1C3F8B01210
+S31508000B981846012380F89C32027003F08FFE002065
+S31508000BA808BD0220704710B50446012380F89C3218
+S31508000BB8D0F8B4325B6801799847204603F0F3FE0B
+S31508000BC8204603F0E0FE002010BD19B1C0F8B412A3
+S31508000BD8002070470220704708B503F0DCFE0020A5
+S31508000BE808BD08B5D0F8B43233B11B68984708B9B8
+S31508000BF8002008BD0220FCE70220FAE708B5D0F86D
+S31508000C08B4325B689847002008BD38B5044600F535
+S31508000C182A752846FFF761FC0123C4F89432B4F80C
+S31508000C28AE32C4F8983294F8A81201F01F03012BC3
+S31508000C380FD05AB23AB1022B10D001F080012046E3
+S31508000C4803F0CCFE03E029462046FFF7F5FD002011
+S31508000C5838BD29462046FFF723FEF8E729462046E9
+S31508000C68FFF74EFEF3E738B50446A9BB1046D4F895
+S31508000C789432032B03D0052B25D0002038E0D4F86E
+S31508000C886031D4F8642193420DD99B1AC4F86031AF
+S31508000C989A4206D99AB201462046FFF7EDFB00208C
+S31508000CA826E092B2F7E7D4F8B4321B691BB194F878
+S31508000CB89C22032A04D02046FFF7E6FB002017E00B
+S31508000CC820469847F7E70025C4F89452294620464F
+S31508000CD803F084FE28460BE00A46D0F8B4329B692E
+S31508000CE83BB190F89C12032905D111469847002074
+S31508000CF838BD0220FCE70220FAE710B504460029A9
+S31508000D0856D11046D4F89432022B09D0002B18BFB6
+S31508000D18042B44D094F8A032012B45D0002010BDEE
+S31508000D28236A626A93421BD8E169B1FBF2F302FBB4
+S31508000D3813132BB98A4203D8D4F8983299421DD38B
+S31508000D48D4F8B432DB681BB194F89C22032A23D062
+S31508000D588021204603F042FE2046FFF7A0FBD9E78C
+S31508000D689A1A226292B201462046FFF77DFB0023B3
+S31508000D781A461946204603F051FECBE700221146CB
+S31508000D882046FFF771FB0021C4F898120B460A465D
+S31508000D98204603F043FEBDE720469847D8E780215A
+S31508000DA8204603F01BFEB5E7002084F8A002B6E744
+S31508000DB80A46D0F8B4325B693BB190F89C1203290D
+S31508000DC805D1114698470020A9E70220A7E702207F
+S31508000DD8A5E770B5044640230022114603F0EBFD4B
+S31508000DE80125C4F858514026C4F8646133460022E0
+S31508000DF88021204603F0DFFDA561666284F89C52CF
+S31508000E080023C4F894326360C4F8A432D4F8B8321C
+S31508000E182BB1D4F8B4325B680021204698470020E5
+S31508000E2870BD01740020704790F89C3280F89D3296
+S31508000E38042380F89C320020704790F89C32042BD3
+S31508000E4801D00020704790F89D3280F89C32F8E768
+S31508000E5808B590F89C32032B01D0002008BDD0F8BD
+S31508000E68B432DB69002BF8D09847F6E700207047BC
+S31508000E78002070470020704708B5012280F89C2298
+S31508000E88D0F8B422526801799047002008BD0000BE
+S31508000E98184AD2F8883043F47003C2F88830164BDB
+S31508000EA81A6842F001021A6000221A611868134982
+S31508000EB8014019609A61DA611A629A62DA621A63FB
+S31508000EC85A639A63DA631A645A64196821F48021A2
+S31508000ED819601A660A4B1A680A4B1340B3F1005F81
+S31508000EE802D2094B01221A60024B4FF000629A603F
+S31508000EF8704700BF00ED00E0004402587FEDF6EAAF
+S31508000F080010005C0000FFFF0881005110B5164B61
+S31508000F186FF00042DA670024DC674FF0FF32C3F847
+S31508000F288020C3F88040C3F88420C3F88440C3F8F7
+S31508000F388820C3F88840C3F88C20C3F88C40C3F8C7
+S31508000F489020C3F89040C3F89420C3F89440C3F897
+S31508000F589820C3F89840C3F89C20C3F89C4003F02F
+S31508000F685FFB204610BD00BF00440258104B1B7893
+S31508000F780BB90120704710B504464FF47A70B0FBD8
+S31508000F88F3F30C4A1068B0FBF3F002F095FA68B967
+S31508000F980F2C01D901200AE0002221464FF0FF3024
+S31508000FA802F058FA044B1C60002000E0012010BD2E
+S31508000FB8340400202C0400203804002010B503202F
+S31508000FC802F036FA02F06AF80F498B69C3F303236D
+S31508000FD80E4AD35C03F01F03D8408B6903F00F034E
+S31508000FE8D35C03F01F0320FA03F3094A1360094B7D
+S31508000FF818600020FFF7BAFF10B10124204610BD7B
+S31508001008044603F05DFAF9E700440258185D00083B
+S31508001018300400202C04002038B5044604F040F8B3
+S315080010280546B4F1FF3F02D0044B1B781C4404F074
+S3150800103837F8401BA042FAD338BD00BF3404002055
+S31508001048204A136843F0010313601E4B1B6813F00C
+S31508001058040FFAD01B4B00221A6119681A4A0A406B
+S315080010681A60184B1B6813F0007FFAD1154B1B68DA
+S3150800107813F0006FFAD1134B1B6813F0005FFAD10F
+S31508001088104B00229A61DA611A621049996210496E
+S31508001098D962104919635A639963DA6319645A64F9
+S315080010A8196821F4802119601A66996E40F2FF7250
+S315080010B80A439A66D3F8D02042F48032C3F8D0207F
+S315080010C8704700BF0044025845EDF6EA00020202DE
+S315080010D80000FF018002010107EE900AF8EE676A30
+S315080010E807EE901AF8EE677A86EEA77A07EE902A40
+S315080010F8F8EE677A06EE903AF8EE666A9FED096AA0
+S3150800110866EE866A77EEA67A27EE277ADDED007A06
+S31508001118F8EE677AC7EE276AFCEEE67A17EE900AC3
+S31508001128704700BF000000392DE9F04182B03E4BF8
+S315080011389B6A03F00303012B24D0BBB1022B28D0EA
+S3150800114800270023036043608360374B9E6AC6F313
+S3150800115805161A6BC2F30802551CDB6A13F0010F51
+S3150800116824D0314B5B6BC3F3CC0821E02E4B1B68AC
+S3150800117813F0040F14D02C4B1B68C3F3C1032B4F71
+S31508001188DF40DEE7284B1B6813F4807F0AD1002767
+S31508001198D7E7254B1B6813F4003F05D10027D0E78E
+S315080011A80027CEE7224FCCE7224FCAE74FF00008C0
+S315080011B8002E36D004461C4BDB6A13F4803F0CD04D
+S315080011C8194B1B6BC3F346230133009343462A4640
+S315080011D831463846FFF780FF2060134BDB6A13F465
+S315080011E8003F0CD0104B1B6BC3F306430133009327
+S315080011F843462A4631463846FFF76EFF60600A4B73
+S31508001208DB6A13F4802F0CD0074B1B6BC3F30663FA
+S315080012180133009343462A4631463846FFF75CFFB2
+S31508001228A06002B0BDE8F081004402580090D003DF
+S3150800123800093D0000127A002DE9F04182B03E4BC4
+S315080012489B6A03F00303012B24D0BBB1022B28D0D9
+S3150800125800270023036043608360374B9E6AC6F302
+S3150800126805369A6BC2F30802551CDB6A13F0100F91
+S3150800127824D0314BDB6BC3F3CC0821E02E4B1B681B
+S3150800128813F0040F14D02C4B1B68C3F3C1032B4F60
+S31508001298DF40DEE7284B1B6813F4807F0AD1002756
+S315080012A8D7E7254B1B6813F4003F05D10027D0E77D
+S315080012B80027CEE7224FCCE7224FCAE74FF00008AF
+S315080012C8002E36D004461C4BDB6A13F4002F0CD0CC
+S315080012D8194B9B6BC3F346230133009343462A46AF
+S315080012E831463846FFF7F8FE2060134BDB6A13F4DD
+S315080012F8801F0CD0104B9B6BC3F306430133009336
+S3150800130843462A4631463846FFF7E6FE60600A4BEA
+S31508001318DB6A13F4001F0CD0074B9B6BC3F30663F9
+S315080013280133009343462A4631463846FFF7D4FE2A
+S31508001338A06002B0BDE8F081004402580090D003CE
+S3150800134800093D0000127A002DE9F04182B0424BAF
+S315080013589B6A03F00303012B24D0BBB1022B28D0C8
+S31508001368002500230360436083603B4B9C6AC4F3F3
+S3150800137805541A6CC2F30802561CDB6A13F4807FFC
+S3150800138824D0354B5F6CC7F3CC0720E0324B1B687B
+S3150800139813F0040F14D0304B1B68C3F3C1032F4D49
+S315080013A8DD40DEE72C4B1B6813F4807F0AD1002545
+S315080013B8D7E7294B1B6813F4003F05D10025D0E76A
+S315080013C80025CEE7264DCCE7264DCAE700272B1C75
+S315080013D818BF0123002C08BF0023002B39D08046EC
+S315080013E81D4BDB6A13F4800F0DD01B4B1B6CC3F324
+S315080013F84623013300933B46324621462846FFF7E3
+S315080014086BFEC8F80000144BDB6A13F4000F0DD006
+S31508001418114B1B6CC3F30643013300933B46324614
+S3150800142821462846FFF758FEC8F804000A4BDB6A27
+S3150800143813F0807F0DD0084B1B6CC3F3066301338A
+S3150800144800933B46324621462846FFF745FEC8F82C
+S31508001458080002B0BDE8F081004402580090D003A5
+S3150800146800093D0000127A00154B1B6903F0380382
+S31508001478182B0ED8DFE803F00F0D0D0D0D0D0D0D09
+S31508001488210D0D0D0D0D0D0D160D0D0D0D0D0D0D59
+S315080014981800002070470A4B1B68C3F3C1030948A4
+S315080014A8D84070470848704700B585B001A8FFF7C7
+S315080014B83BFE019805B05DF804FB0448704700BF79
+S315080014C8004402580090D00300127A0000093D0033
+S315080014D8044B9B6903F00F03034AD35C03F01F030D
+S315080014E8D840704700440258285D0008044BDB6959
+S315080014F8C3F30213034AD35C03F01F03D8407047AB
+S3150800150800440258285D0008044BDB69C3F302232C
+S31508001518034AD35C03F01F03D840704700440258B7
+S31508001528285D000800B585B0C2B24F4BD358020EE5
+S31508001538C0F304218A401340CB4040EA03404B4B92
+S31508001548984228D033D8A3F58133A3F580739842F7
+S3150800155866D019D8A3F58033984251D003F540735D
+S3150800156898420FD1FFF780FF414B9B69C3F30323CA
+S31508001578404AD35C03F01F03D840FFF7A9FFFFF7DB
+S31508001588C3FF24E0002022E03B4B984248D003F5ED
+S315080015987D43984209D1364B1B6813F0005F59D032
+S315080015A801A8FFF7D1FE029811E000200FE0334B9F
+S315080015B898423FD00ED9324B984242D003F5407331
+S315080015C898423ED0A3F58033984233D0002005B020
+S315080015D85DF804FBA3F58033984203D003F54073FE
+S315080015E898420BD1224B1B6813F0040F34D0204BBA
+S315080015F81B68C3F3C1032348D840E8E70020E6E799
+S31508001608FFF732FF1A4B9B69C3F30323194AD35CC6
+S3150800161803F01F03D840FFF75BFFFFF767FFD6E71E
+S31508001628134B1B6813F0006F12D001A8FFF704FECE
+S315080016380298CCE70E4B1B6813F4807F0ED1002066
+S31508001648C5E70B4B1B6F13F0020F09D10020BEE745
+S315080016580020BCE70020BAE70020B8E70A48B6E742
+S315080016684FF40040B3E700BF4C440258080302078A
+S3150800167800440258285D0008080301070800040703
+S31508001688080005070090D00300093D0030B4446BF4
+S315080016980268D2F88410704B194041EA8401C2F8EE
+S315080016A884100268D2F8841021F47F01856B41EA18
+S315080016B80541C2F88410826B22440468D4F888105D
+S315080016C8194041EA8201C4F888100468D4F88810D9
+S315080016D821F4FE01C56B41EA0541C4F88810C16BBF
+S315080016E802EB41020468D4F8A010194041EA8201C5
+S315080016F8C4F8A0100468D4F8A01021F4FE01056CFB
+S3150800170841EA0541C4F8A010046C416C01FB0424A5
+S315080017180268D2F8B010194041EA8401C2F8B0103C
+S315080017280268D2F8B01021F4FE01856C41EA054139
+S31508001738C2F8B010826CC16C01FB02440268D2F888
+S31508001748AC10194041EA8401C2F8AC10026D416D2B
+S3150800175801FB02420468D4F8F010194041EA8201F4
+S31508001768C4F8F0100468D4F8F01021F47C11856DDB
+S3150800177841EA0541C4F8F010816D02EB410204689C
+S31508001788D4F8C0100B4043EA8202C4F8C0200268A5
+S31508001798D2F8C03023F47C13C16D43EA0143C2F87A
+S315080017A8C0300268D2F8C03023F07C53016E43EA91
+S315080017B80163C2F8C030436B284A1A449200C266CD
+S315080017C8836B02EB83030367C16B03EBC1034367B0
+S315080017D8046C416C01FB04F103EB81038367846C99
+S315080017E8C16C01FB04F103EB8103C367046D416D0A
+S315080017F801FB04F103EB8103C0F88030816D03EB2C
+S31508001808C103C0F88430C46D856E05FB04F403EB88
+S315080018188403C0F88830016E01FB05F103EB8103E8
+S31508001828C0F890300E498B4207D8D0F890309342CA
+S315080018380ED9002342F8043BF7E7D0F89C3043F06A
+S315080018482003C0F89C30032380F89830012000E074
+S31508001858002030BC704700BF0300FFFF002B0010B4
+S31508001868FCD30040F0B44C68002C2FD10E698C6864
+S3150800187826430C6846EA84460D6ACC6944EA056438
+S315080018888D692C434D692C43CD682C43D0F8847058
+S31508001898806E03FB00F307EB830547F823606C604B
+S315080018A808350020CB890E4CE35C834216D91418F8
+S315080018B8E678A3781B0443EA0663647843EA0423B4
+S315080018C8145C234345F8043B0430EBE70C698E683F
+S315080018D826430C68264346F08046CDE7F0BC704799
+S315080018E8385D00087047000030B595B004464C22AC
+S315080018F8A04901A804F0C9F9002C00F0388123682A
+S315080019089D4A934220D094F898300BB3226893697D
+S3150800191823F01003936103F0C3FB054623689A690D
+S3150800192812F0080F1AD003F0BBFB401B0A28F5D99A
+S31508001938D4F89C3043F00103C4F89C30032384F898
+S315080019489830012015B030BD03F580736360DAE777
+S3150800195884F899302046FFF7C5FFD7E79A6942F019
+S3150800196801029A6103F09CFB054623689A6912F0FE
+S31508001978010F0FD103F094FB401B0A28F5D9D4F8B8
+S315080019889C3043F00103C4F89C30032384F898304C
+S315080019980120D7E79A6942F002029A61237C012B53
+S315080019A840D02268936943F040039361637C012B16
+S315080019B83ED02268936923F480439361A37C012B64
+S315080019C83CD02268936943F48053936122689369EB
+S315080019D823F44073A1680B4393612268936923F043
+S315080019E8A40393612268136923F010031361E3685B
+S315080019F8012B29D0002B2CD0022B00F09B802268C3
+S31508001A08936943F0800393612268136943F01003CE
+S31508001A181361E368032B1CD12268936943F02003FA
+S31508001A28936116E02268936923F040039361BDE742
+S31508001A382268936943F480439361BFE722689369F0
+S31508001A4823F480539361C1E72268936943F004033A
+S31508001A589361A3695A1EE369013B1B0243EA426381
+S31508001A68226A013A13436269013A216843EA024342
+S31508001A78CB61A368B3F5407F62D0236E33B1226881
+S31508001A88D2F8C030616E0B43C2F8C030E36D226EDF
+S31508001A98D3420DD02168D1F8C83023F00703A26EC7
+S31508001AA814A800EB820252F84C2C1343C1F8C8302C
+S31508001AB8236C6BB12168D1F8BC3023F00703626C3C
+S31508001AC814A800EB820252F84C2C1343C1F8BC3018
+S31508001AD8A36C73B12168D1F8BC3023F07003E26CAB
+S31508001AE814A800EB820252F84C2C43EA0213C1F8F8
+S31508001AF8BC30236D73B12168D1F8BC3023F4E06398
+S31508001B08626D14A800EB820252F84C2C43EA0223B1
+S31508001B18C1F8BC302268184B9A4222D00023C4F870
+S31508001B289430C4F89C30012384F898302046FFF78F
+S31508001B38ADFD07E72268936943F02003936188E7B8
+S31508001B48A36A013BE26A013A43EA0223226B013A95
+S31508001B5843EA0213626A013A216843EA0243CB6000
+S31508001B688BE76268936823F003039360D6E701203E
+S31508001B78E8E600BFC85C000800A0004090F8983066
+S31508001B88013BDBB2012B07D9D0F89C3043F002039E
+S31508001B98C0F89C3001207047CB680A68D2B9072B71
+S31508001BA80ED08A68DB0643EA82730A6943EA024367
+S31508001BB84A691343C26E496842F8213000207047C3
+S31508001BC80A69CB691B0243EA02438A69134343F04D
+S31508001BD86053EFE710B40A6942EA4372072B0ED03E
+S31508001BE88C684B6943EA8473006F496800EBC10443
+S31508001BF840F83120636000205DF8044B70478B6914
+S31508001C08F2E710B490F89840E4B2012C09D0D0F85D
+S31508001C189C3043F00403C0F89C3001205DF8044B5F
+S31508001C287047920042EA011242EA43020168019BA0
+S31508001C381A43C1F880200020F0E790F89830DBB204
+S31508001C48012B07D0D0F89C3043F00403C0F89C3029
+S31508001C5801207047022380F898300268936923F0B8
+S31508001C68010393610023C0F89C301846704770B585
+S31508001C7890F89840013CE4B2012C26D893FAA3F5CB
+S31508001C88B5FA85F50668D6F8C040C4F30544A542F2
+S31508001C980BD2D6F8CC401C420FD0D0F89C3043F073
+S31508001CA84003C0F89C30012016E0D0F89C3043F079
+S31508001CB82003C0F89C3001200EE093FAA3F3B3FA88
+S31508001CC883F3FFF7CFFD002006E0D0F89C3043F0F9
+S31508001CD80203C0F89C30012070BD90F89830DBB23A
+S31508001CE8022B07D0D0F89C3043F00803C0F89C3084
+S31508001CF8012070470368C3F8D01000207047000019
+S31508001D08F0B490F89840E4B2022C40F0BA80402922
+S31508001D180CD0412930D0046D8C4253D8D0F89C3069
+S31508001D2843F02003C0F89C300120B1E00468D4F8D9
+S31508001D38A05015F4FE0F0CD0D4F8A45015F07F0F58
+S31508001D480FD1D0F89C3043F48073C0F89C3001203A
+S31508001D589EE0D0F89C3043F02003C0F89C30012060
+S31508001D6896E0D4F8A440C4F3052C446F456C0CFBE4
+S31508001D7805F504EB85042DE00468D4F8B05015F48D
+S31508001D88FE0F0CD0D4F8B45015F07F0F0FD1D0F849
+S31508001D989C3043F48073C0F89C30012078E0D0F872
+S31508001DA89C3043F02003C0F89C30012070E0D4F83A
+S31508001DB8B440C4F3052C846FC56C0CFB05F504EB1D
+S31508001DC8850407E0C46F456D01FB05F504EB85043A
+S31508001DD84FF0000C256805F080455560002D2CD17C
+S31508001DE82568C5F38A451560256805F00055956088
+S31508001DF8256805F000451561A588D561656805F467
+S31508001E087025D560656805F480155561656805F41B
+S31508001E1800159561E57905F07F0515626568ED0F8A
+S31508001E28556204F108050024D6891A4FBE5DA642F4
+S31508001E3808D92E5D1E550134F6E7256825F0604554
+S31508001E481560D1E740290AD041290DD01F290FD896
+S31508001E580268012303FA01F1C2F8981002E0036840
+S31508001E68C3F8A8C0002013E00368C3F8B8C0F9E7A8
+S31508001E7801F01F010268012303FA01F1C2F89C1058
+S31508001E88F0E7D0F89C3043F00803C0F89C300120EE
+S31508001E98F0BC7047385D00080368D3F8CC300B42AD
+S31508001EA801D00120704700207047402905D00368F3
+S31508001EB8D3F8B40000F07F0070470368D3F8A4008D
+S31508001EC800F07F007047000001F00303032B24D0BD
+S31508001ED811F0010F0BD01D4BDA6822F03002DA60D8
+S31508001EE8DA680243DA60DA6842F08802DA6011F0E2
+S31508001EF8020F11D0154BD3F80C2122F03002C3F883
+S31508001F080C21D3F80C211043C3F80C01D3F80C2183
+S31508001F1842F08802C3F80C2170470C4BDA6822F0A5
+S31508001F283002DA60D3F80C2122F03002C3F80C210B
+S31508001F38DA680243DA60D3F80C211043C3F80C01B7
+S31508001F489A6942F010029A61704700BF0020005251
+S31508001F5830B411F0010F0BD0104DEB6823F4E6638B
+S31508001F68EB60EC6842EA00231C4344F08404EC6006
+S31508001F7811F0020F0FD00949D1F80C3123F4E663A2
+S31508001F88C1F80C31D1F80C3142EA0022134343F068
+S31508001F988403C1F80C3130BC704700BF00200052DA
+S31508001FA8F8B5474B1B7D012B00F088800F46044681
+S31508001FB8434B01221A7500229A61436813F0010FF0
+S31508001FC80DD10026636813F0020F12D1CEB9236823
+S31508001FD8012B1BD04FF0FF333B60A56859E0012160
+S31508001FE84CF2503000F018FA06460028EAD00126C6
+S31508001FF8E8E702214CF2503000F00EFA0028E5D046
+S3150800200801262F4B00221A753046F8BD61682069EB
+S31508002018FFF75AFF636813F0010F12D1636813F0CC
+S31508002028020FEED002214CF2503000F0F5F900B15B
+S315080020380126244AD2F80C3123F00803C2F80C31D9
+S31508002048DFE701214CF2503000F0E6F900B101262D
+S315080020581C4AD36823F00803D360DFE701214CF252
+S31508002068503000F0D9F90646164AD168164B0B4087
+S31508002078D3601CE002214CF2503000F0CDF9064638
+S31508002088104AD2F80C11104B0B40C2F80C319EB905
+S315080020980135E368A2681344AB42B2D9226961687C
+S315080020A82846FFF755FF636813F0010FD6D1636812
+S315080020B813F0020FEBD0DDE73D60A2E70226A3E79F
+S315080020C8D012002000200052FBF8FFFF6A4B984206
+S315080020D822D06A4B98422FD0694B98423CD0694B1C
+S315080020E8984249D0684B984256D0684B984263D074
+S315080020F8674B984270D0674B98427DD0664B98429A
+S3150800210800F08A80654B984200F09680644B9842A6
+S3150800211800F0A2800120704703F58843D3F8882089
+S3150800212842F00102C3F88820D3F8882022F0010279
+S31508002138C3F888200020704703F58043D3F8882021
+S3150800214842F00202C3F88820D3F8882022F0020257
+S31508002158C3F888200020704703F57053D3F8882001
+S3150800216842F00402C3F88820D3F8882022F0040233
+S31508002178C3F888200020704703F56053D3F88820F1
+S3150800218842F00802C3F88820D3F8882022F008020B
+S31508002198C3F888200020704703F55053D3F88820E1
+S315080021A842F01002C3F88820D3F8882022F01002DB
+S315080021B8C3F888200020704703F54053D3F88820D1
+S315080021C842F02002C3F88820D3F8882022F020029B
+S315080021D8C3F888200020704703F53053D3F88820C1
+S315080021E842F04002C3F88820D3F8882022F040023B
+S315080021F8C3F888200020704703F52053D3F88820B1
+S3150800220842F08002C3F88820D3F8882022F080029A
+S31508002218C3F888200020704703F51053D3F88820A0
+S3150800222842F48072C3F88820D3F8882022F4807292
+S31508002238C3F888200020704703F50053D3F8882090
+S3150800224842F40072C3F88820D3F8882022F4007272
+S31508002258C3F888200020704703F5E053D3F8882090
+S3150800226842F48062C3F88820D3F8882022F4806272
+S31508002278C3F8882000207047000002580004025856
+S3150800228800080258000C0258001002580014025898
+S3150800229800180258001C0258002002580024025848
+S315080022A800280258F0B40C6894FAA4F4B4FA84F432
+S315080022B82BE08E68826803FB03F505EB450722EADF
+S315080022C8070205FB06F52A4382600E68CD68426850
+S315080022D822EA060205FB06F52A4342600F69C66824
+S315080022E803FB03F505EB4502D243164005FB07F742
+S315080022F83E43C6604E68022E14D04B6806683240C4
+S3150800230805FB03F31343036001340B6833FA04F23D
+S315080023182BD00122A2401340F6D04A68013A012A76
+S31508002328DCD8C6E7FF2B0ED8066A05FB03F707FBBA
+S3150800233803F3C3EB031726EA07074E6903FB06F3FD
+S315080023483B430362D9E7466A1B0A03FB03F707FB05
+S3150800235803F707FB03F3C3EB031726EA07074E69D8
+S3150800236803FB06F33B434362C7E70020F0BC70470C
+S31508002378024AD36843F08073D3607047004802580E
+S31508002388144BDB6813F0010F09D0124B124A5A6036
+S3150800239802F188325A60DB6813F0010F14D10D4B2D
+S315080023A8D3F80C3113F0010F10D00A4B0A4AC3F8B8
+S315080023B8042102F18832C3F80421D3F80C3113F04A
+S315080023C8010F05D10020704701207047002070478B
+S315080023D80120704700200052230167450D4BDA6833
+S315080023E842F00102DA60DB6813F0010F0DD0094BE1
+S315080023F8D3F80C2142F00102C3F80C21D3F80C31AA
+S3150800240813F0010F03D00020704701207047012000
+S31508002418704700BF00200052F8B505460E4602F080
+S315080024283FFE0746012E09D0364C17E002F038FE63
+S31508002438C01BA84260D88DB903204EE004240DE0DD
+S31508002448314BD3F8103124EA030333F000430CBFA9
+S31508002458012300236BB1B5F1FF3FE7D134F004033C
+S31508002468EED1294B1B6934EA03030CBF0123002369
+S31508002478F0E7012E1CD0244BD3F8103123F068431B
+S3150800248823F480135B0C5B0443F0004333F00242E9
+S3150800249817D1012E25D01C4BD3F8103113F4803FE1
+S315080024A82ED0194B4FF48032C3F81421002014E0BB
+S315080024B8154B1B6923F0684323F480135B0C5B04F4
+S315080024C8E4E712498A691A438A61002B06DA23F077
+S315080024D800430D4AC2F814310120F8BD0A4A53616F
+S315080024E8FAE7094B1B6913F4803F07D0064B4FF4EC
+S315080024F880325A610020F0E70320EEE70020ECE777
+S315080025080020EAE70400008000200052D0120020CC
+S315080025182C4B1B7D012B51D070B50C461546294B03
+S3150800252801221A7501F17841B1F5801F38D216468D
+S31508002538244B00229A6131464CF25030FFF76CFF63
+S31508002548034640BB012E2DD01F4AD2F80C3143F062
+S315080025580203C2F80C31BFF36F8FBFF34F8F0823FE
+S3150800256855F8042B44F8042B013B13F0FF03F7D165
+S31508002578BFF36F8FBFF34F8F31464CF25030FFF7DA
+S315080025884BFF0346012E13D00F49D1F80C2122F030
+S315080025980202C1F80C210B4A00211175184670BDB4
+S315080025A80226C5E7084AD36843F00203D360D2E790
+S315080025B80549CA6822F00202CA60ECE702231846EF
+S315080025C8704700BFD01200200020005200230133B4
+S315080025D80C4A934211D80269002AF8DA036943F0CB
+S315080025E80103036100230133064A934207D80269A7
+S315080025F812F0010FF7D10020704703207047032017
+S31508002608704700BF400D030084B010B5044603A800
+S3150800261880E80E00089B012B1DD1A36B23F4803399
+S31508002628A363E2681A4B1340E360E36823F4401394
+S31508002638E3600F9B012B09D02046FFF7C7FF069BCF
+S31508002648012B1BD0BDE8104004B07047E36843F47B
+S315080026588013E360F0E7E36843F04003E36020464D
+S31508002668FFF7B4FF0C9B23B9A36B43F48033A3632A
+S31508002678E5E7A36B23F48033A363E0E7A36843F095
+S315080026880603A360A36843F02003A360DAE700BF44
+S31508002698BFFFBDFF022A0AD00921C26822F4705278
+S315080026A8C260C36843EA8123C36000207047274B8A
+S315080026B80B44274A934237D9264B0B44264A93425A
+S315080026C834D9264B0B44264A934231D9254B0B4419
+S315080026D802F5C332A03293422CD9234B0B44234A22
+S315080026E8934229D9224B0B4402F5922202F57872B5
+S315080026F8934223D91F4B0B4402F5C32202F52072D5
+S3150800270893421DD91C4B0B4402F5B71202F55872B1
+S31508002718934217D9194B0B4402F5122202F5F862AF
+S31508002728934211D80721B8E70F21B6E70E21B4E777
+S315080027380D21B2E70C21B0E70B21AEE70A21ACE779
+S315080027480921AAE70821A8E70621A6E7405327FF93
+S31508002758FF340C00401E1BFF3F420F0000DC0BFF36
+S315080027687F4F1200808CF9FE60B6E5FE5FE316001F
+S3150800277800D3CEFEC05BB3FE00CA91FEE05459FEF4
+S31508002788836843F00103836000207047836823F059
+S31508002798010383600020704708B5C36823F0C04367
+S315080027A8C360012909D069B9C36843F08043C36087
+S315080027B83220FEF731FC002008BDC36843F00053F9
+S315080027C8C360F5E70120F7E7890141F020010161B7
+S315080027D800230133054A934205D8026912F0200FEF
+S315080027E8F7D1002070470320704700BF400D03004B
+S315080027F81023036100230133054A934205D8026969
+S3150800280812F0100FF7D1002070470320704700BF59
+S31508002818400D0300D0F800381943C0F80018002006
+S315080028287047000084B0F8B5044607A880E80E008B
+S31508002838254600230E2B07D803F1400204EB820233
+S31508002848002151600133F5E7119B23BBD4F80438FE
+S3150800285843F00203C4F80438A36B23F40013A363F4
+S31508002868236843F040032360236843F0800323600A
+S315080028780023C4F8003E04F50066D4F80038C4F806
+S3150800288800380C9B012B10D1099B4BB90021204617
+S31508002898FFF7C0FF0DE0A36B43F40013A363E7E754
+S315080028A801212046FFF7B6FF03E003212046FFF77C
+S315080028B8B1FF10212046FFF787FF074600B1012719
+S315080028C82046FFF795FF00B101270023336173619E
+S315080028D8F3610AE0C3B94FF00060C2F800090022A4
+S315080028E80A614FF67F328A600133079A9A4210D9ED
+S315080028F805EB431202F51061D2F800090028E9DB56
+S315080029080020C2F80009EAE74FF09040C2F800092B
+S31508002918E5E700230AE0C3B94FF00060C2F8000BE8
+S3150800292800220A614FF67F328A600133079A9A4273
+S3150800293810D905EB431202F53061D2F8000B0028CE
+S31508002948E9DB0020C2F8000BEAE74FF09040C2F82E
+S31508002958000BE5E7336923F4807333610023A36129
+S315080029686FF0804363610A9B1BB9A36943F01003A0
+S31508002978A361A2690A4B1343A3610D9B1BB1A36903
+S3150800298843F00803A361119B012B04D03846BDE820
+S31508002998F84004B07047A269024B1343A361F5E7F0
+S315080029A800383C8004000040D0F8083813F00603C5
+S315080029B805D0062B18BF022B03D10220704700202A
+S315080029C870470F207047000070B40B784A78012AC0
+S315080029D820D0D0F81C2803F00F060124B44042EA98
+S315080029E80442C0F81C2800EB4310D0F8003B13F447
+S315080029F8004F0CD1D0F8002B8B68C3F30A03C978AB
+S31508002A0843EA81431343134A1A43C0F8002B0020AC
+S31508002A1870BC7047D0F81C4803F00F06B24092B253
+S31508002A282243C0F81C2800EB4310D0F8002912F4FA
+S31508002A38004FECD1D0F800498A68C2F30A02C9786F
+S31508002A4842EA814242EA8353234302491943C0F8BA
+S31508002A580019DCE70080001070B40B784A78012A60
+S31508002A681FD0D0F83C5803F00F06012404FA06F6DE
+S31508002A7825EA0645C0F83C58D0F81C58097801F0EC
+S31508002A880F018C4025EA0444C0F81C4800EB4310A3
+S31508002A98D0F8002B124B1340C0F8003B002070BC3E
+S31508002AA87047D0F83C6803F00F0402FA04F4A4B29D
+S31508002AB826EA0404C0F83C48D0F81C48097801F00E
+S31508002AC80F018A4092B224EA0202C0F81C2800EBD9
+S31508002AD84310D0F80039034A1A40C0F80029DDE740
+S31508002AE80078F3EF007833EC70B40B784C78012C47
+S31508002AF824D000EB431000F530631D693E4C2C408A
+S31508002B081C611D693D4C2C401C614C690CB18C68D4
+S31508002B184C611C6944F400241C611C698D68C5F362
+S31508002B2812052C431C61012A61D0D0F8003B43F0FA
+S31508002B380443C0F8003B002070BC70474C695CBB76
+S31508002B4800EB4314D4F810692C4D3540C4F81059D5
+S31508002B58D4F8105945F40025C4F81059D4F8106962
+S31508002B68254D3540C4F81059012A31D000EB4313D6
+S31508002B78D3F8002942F00442C3F800294B69002B10
+S31508002B88D9D0D0F83428097801F00F040121A140DA
+S31508002B980A43C0F83428CEE700EB431404F510645A
+S31508002BA82669154D354025612669144D3540256138
+S31508002BB84E698D68AE4200D94D61256945F40025F0
+S31508002BC8256125694E69C6F3120635432561CBE7A3
+S31508002BD80A691AB100EB4311C1F8142900EB43102E
+S31508002BE8D0F8002942F00442C0F80029A3E7CA68C9
+S31508002BF8002A9AD05A6198E70000F8FFFFFF07E015
+S31508002C0870B49DF80C4064B903339E08B44208D2E0
+S31508002C1800EB023303F5805351F8045B1D60013459
+S31508002C28F4E7002070BC7047F0B583B00B784C7891
+S31508002C38012C29D000EB431303F5306426697C4D33
+S31508002C483540256126697B4D354025614D69002D3E
+S31508002C5840F0BF8025698E68C6F31206354325619C
+S31508002C68256945F400252561012A00F0C780CA7838
+S31508002C78012A00F0C980D3F8002B42F00442C3F8B1
+S31508002C88002B002003B0F0BD4C6974BB00EB43145D
+S31508002C98D4F81069674D3540C4F81059D4F8105956
+S31508002CA845F40025C4F81059D4F81069604D354024
+S31508002CB8C4F81059012A4AD000EB4313D3F800493F
+S31508002CC844F00444C3F80049CC78012C68D04B6911
+S31508002CD8002BD6D0D0F83428097801F00F04012142
+S31508002CE8A1400A43C0F83428CBE700EB4314D4F8CC
+S31508002CF810694F4D3540C4F81059D4F810694D4D30
+S31508002D083540C4F81059D4F810694D698F683D44A0
+S31508002D18013DB5FBF7F5484F07EAC5453543C4F8FD
+S31508002D281059D4F810594E69C6F312063543C4F833
+S31508002D38105904F51064CD78012DBBD1256925F005
+S31508002D48C0452561256945F000552561B2E70A6938
+S31508002D581AB100EB4314C4F81429CA78012A08D012
+S31508002D6800EB4313D3F8002942F00442C3F80029BC
+S31508002D7887E7D0F8082812F4807F08D100EB4311BA
+S31508002D88D1F8002942F00052C1F80029E8E700EB1B
+S31508002D984311D1F8002942F08052C1F80029DFE72B
+S31508002DA8D0F8084814F4807F0CD1D3F8004944F0C9
+S31508002DB80054C3F8004900928B8A0A78C968FFF755
+S31508002DC81FFF5EE7D3F8004944F08054C3F800496A
+S31508002DD8F1E78E683544013DB5FBF6F52669164FC9
+S31508002DE807EAC5473E43266127698E68ADB206FBE2
+S31508002DF805F5C5F312053D43256135E7CA68002A76
+S31508002E083FF435AF626132E7D0F8082812F4807FBC
+S31508002E1806D1D3F8002B42F00052C3F8002B2AE754
+S31508002E28D3F8002B42F08052C3F8002B23E700BFE3
+S31508002E380000F8FFFFFF07E00000F81F03329208BA
+S31508002E48002393420CD210B400F58054246841F844
+S31508002E58044B01339342F7D308465DF8044B704791
+S31508002E68084670470B784A78012A14D000EB4310B5
+S31508002E78D0F8002B002A06DB2BB1D0F8003B23F04C
+S31508002E888043C0F8003BD0F8003B43F40013C0F871
+S31508002E98003B0020704700EB4310D0F80029002AB1
+S31508002EA806DB2BB1D0F8003923F08043C0F8003987
+S31508002EB8D0F8003943F40013C0F80039E9E70B786D
+S31508002EC84A78012A0ED000EB4310D0F8003B23F4C9
+S31508002ED80013C0F8003BCB78023BDBB2012B15D9AF
+S31508002EE80020704700EB4310D0F8003923F400138C
+S31508002EF8C0F80039CB78023BDBB2012BF0D8D0F802
+S31508002F08003943F08053C0F80039E9E7D0F8003BA8
+S31508002F1843F08053C0F8003BE2E738B50546044657
+S31508002F2800220E2A09D804EB42134FF67F31C3F85C
+S31508002F380819C3F8081B0132F3E70022C5F8102858
+S31508002F48C5F81428C5F81C282846FFF751FC034677
+S31508002F5808B1184638BD10212846FFF735FC034640
+S31508002F68F7E7D0F8003823F4FE63C0F80038D0F83D
+S31508002F780038090101F4FE610B43C0F80038002047
+S31508002F88704708B5D0F8043823F00203C0F80438A7
+S31508002F980320FEF741F8002008BD08B5D0F8043824
+S31508002FA843F00203C0F804380320FEF735F800207A
+S31508002FB808BD4269806910407047D0F8183800F58E
+S31508002FC80060C0691840000C7047D0F8183800F53A
+S31508002FD80060C069184080B2704700EB4111D1F80B
+S31508002FE8082B00F5006040691040704710B4D0F807
+S31508002FF81048D0F8343801F00F02D340DB01DBB2B1
+S31508003008234300EB411000F51060806818405DF80E
+S31508003018044B7047406900F001007047D0F8002952
+S31508003028054B1340C0F80039D0F8043843F48073C8
+S31508003038C0F804380020704700F8FFFF10B4046C85
+S31508003048154B9C4203D9D0F8003B002B16DB00240D
+S31508003058C0F8104BD0F8104B44F40024C0F8104BB5
+S31508003068D0F8104B44F01804C0F8104BD0F8104BA1
+S3150800307844F0C044C0F8104B012903D000205DF87D
+S31508003088044B7047C0F8142BD0F8003B43F0802354
+S31508003098C0F8003BF2E700BF0A30544F724B1B6971
+S315080030A803F03803102B00F0DB80182B10D00BB177
+S315080030B86E4870476C4B1B6813F0200F00F0D280DF
+S315080030C8694B1868C0F3C100694B23FA00F07047CA
+S315080030D8654A916A01F00301906AC0F30510D36A3C
+S315080030E803F00103526BC2F3CC0203FB02F307EEAB
+S315080030F8903AF8EE677A002800F0B580012966D07C
+S31508003108F9B1022900F08F8007EE100AF8EE476A2F
+S315080031189FED586A86EE267A534B1B6BC3F3080352
+S3150800312806EE903AF8EE666A9FED536A67EE867A77
+S3150800313876EEA77AF7EE006A77EEA67A27EE277A6A
+S3150800314861E0494B1B6813F0200F23D046490A68EB
+S31508003158C2F3C102464BD34007EE103AF8EE476A67
+S3150800316807EE100AB8EE476A86EE867A0B6BC3F343
+S31508003178080306EE903AF8EE666A9FED3F6A67EE30
+S31508003188867A76EEA77AF7EE006A77EEA67A27EEBB
+S31508003198277A38E007EE100AF8EE476A9FED376A8D
+S315080031A886EE267A304B1B6BC3F3080306EE903A75
+S315080031B8F8EE666A9FED306A67EE867A76EEA77A43
+S315080031C8F7EE006A77EEA67A27EE277A1BE007EE6F
+S315080031D8100AF8EE476A9FED276A86EE267A224B8A
+S315080031E81B6BC3F3080306EE903AF8EE666A9FED82
+S315080031F8226A67EE867A76EEA77AF7EE006A77EE9F
+S31508003208A67A27EE277A184B1B6BC3F34623013396
+S3150800321807EE903AF8EE677AC7EE276AFCEEE67A82
+S3150800322817EE900A704707EE100AF8EE476A9FED00
+S31508003238146A86EE267A0C4B1B6BC3F3080306EE54
+S31508003248903AF8EE666A9FED0C6A67EE867A76EE2D
+S31508003258A77AF7EE006A77EEA67A27EE277AD2E7F4
+S3150800326808487047024870470044025800093D005C
+S315080032780090D0030024744A000000390024744CD6
+S315080032880024F44A00127A0008B5FFF707FF0B4A2C
+S315080032989369C3F303230A49CB5C03F01F0320FA97
+S315080032A803F3926902F00F02885C00F01F0023FA04
+S315080032B800F0044A1060044A136008BD0044025826
+S315080032C8185D0008300400202C040020014B186003
+S315080032D8704700BF2C04002038B5036813F0010FA7
+S315080032E840F08C800D4604460368454A1A408B68A8
+S315080032F809690B4369690B43E9690B43134303607F
+S31508003308EB68426822F4405213434360AB6982680B
+S3150800331822F44072134383603A4B984216D03A4BCC
+S3150800332898421CD0394B98421DD0394B98421ED02A
+S31508003338384B98421FD0384B984220D0374B984282
+S3150800334821D0374B984222D001204EE03548FEF767
+S31508003358E9F8002848D06A68EAB9012045E0324801
+S31508003368FEF7E0F8F5E73048FEF7DCF8F1E72E480F
+S31508003378FEF7D8F8EDE72C48FEF7D4F8E9E7294828
+S31508003388FEF7D0F8E5E72848FEF7CCF8E1E726483F
+S31508003398FEF7C8F8DDE72B68E9690B2B2CD8B1F5D9
+S315080033A8004F0DD0DBB2214951F82330B0FBF3F3B7
+S315080033B803EB5203B3FBF2F39BB2E360002014E07D
+S315080033C8DBB21A4951F82330B0FBF3F0530803EB84
+S315080033D84000B0FBF2F34FF6F0721A40C3F342030B
+S315080033E81343E360002000E00120E26A22F00F029E
+S315080033F82B881343E36202E00020F6E7012038BD74
+S31508003408F369FFEF001001400044004000480040FF
+S31508003418004C00400050004000140140007800406D
+S31508003428007C00400803000708000007485D0008FC
+S315080034380649CB6823F4E0631B041B0C000200F45E
+S31508003448E0600343024A1A43CA60704700ED00E089
+S315080034580000FA0530B4154BDB68C3F30223C3F141
+S315080034680704042C28BF04241D1D062D01D9033B77
+S3150800347800E000234FF0FF3505FA04F421EA0401B9
+S31508003488994005FA03F322EA03031943002805DBE2
+S315080034980901C9B2064B195430BC704700F00F0031
+S315080034A80901C9B2034B1954F6E700BF00ED00E05D
+S315080034B800E400E014ED00E00138B0F1807F0AD29C
+S315080034C8064B5860064AF02182F8231000209860B7
+S315080034D807221A6070470120704700BF10E000E015
+S315080034E800ED00E030B40468606A29B940EA024091
+S315080034F8A062002030BC70470D46A36A00EB134053
+S315080035080023691E8B4209D203F1400104EB8101AD
+S31508003518496800EB11400133DBB2F2E740EA0240A2
+S3150800352805F13F0104EB81014860E2E70368596247
+S3150800353800207047024603680121C0F8FC130020E2
+S3150800354882F8F4039A6942F000629A61596D024A50
+S315080035580A435A65704700BF0300001070472DE9F3
+S31508003568F04782B0D0F80080CA00521A9300034484
+S315080035785A6D1B6D9A4255D8C1469B1AC1EBC104B0
+S31508003588A2000244526C9A4200D31A460C460746D1
+S3150800359802F1030A4FEA9A0A15E006F1030A4FEA06
+S315080035A89A0AE3001B1B9D003D44A96C3B7C0093CB
+S315080035B8B3B2E2B24046FFF723FBAB6C3344AB64C5
+S315080035C86B6D1E446E6509EB441303F510639B691E
+S315080035D89BB2534512D3E3001B1B9A003A44516D1C
+S315080035E8136D99420AD24BB15B1AC4EBC4018A001F
+S315080035F83A44566C9E42D0D31E46CEE7E3001B1BC0
+S31508003608980007443A6D7B6D9A420FD804F00F0468
+S315080036180123A340D8F8344824EA0304C8F83448F0
+S31508003628002000E0012002B0BDE8F0870020FAE794
+S315080036387047F0B58BB0002800F0918004460568FD
+S3150800364890F8BD3323B3032384F8BD33EB6B13F427
+S31508003658807F01D1002323612068FFF797F8254664
+S3150800366855F8107B6E460FCD0FC60FCD0FC695E8D9
+S31508003678030086E80300231D0ECB3846FEF7C4FF71
+S3150800368858B1022384F8BD33012528460BB0F0BD8E
+S3150800369880F8BC33FFF7CCFFD5E700212068FFF791
+S315080036A87BF800236568AB4216D2D900C81A82008F
+S315080036B82244012082F83D0082F83C30A2F84230C4
+S315080036C8002082F83F0050649064CA1A9100214489
+S315080036D808650133DBB2E5E700239D4216D9D80011
+S315080036E8C11A8A002244002182F8FD1182F8FC31A9
+S315080036F882F8FF11C2F80412C2F80812C21A90001A
+S315080037082044C0F810120133DBB2E6E7254655F81F
+S31508003718107B6E460FCD0FC60FCD0FC695E8030072
+S3150800372886E80300231D0ECB3846FFF77BF80546C7
+S3150800373860B9002384F83830012384F8BD33636AF6
+S31508003748012B08D02068FFF728FC9EE7022384F897
+S31508003758BD33012599E72046FFF7ECFEF2E7012578
+S3150800376893E77047026890F8BC33012B19D010B557
+S31508003778012380F8BC33836A012B0AD00446006803
+S31508003788FFF7FFFB2068FEF7FBFF002084F8BC0361
+S3150800379810BD8369012BF1D0936B43F4803393638F
+S315080037A8ECE70220704738B590F8BC33012B18D0DF
+S315080037B80446012380F8BC330068FEF7E7FF206853
+S315080037C8FFF7ABFB054628B1002384F8BC3301256F
+S315080037D8284638BD2068FFF7E0FB002384F8BC3389
+S315080037E8F6E70225F4E768B110B50446032380F81E
+S315080037F8BD33FFF7D8FF2046FFF7B3FF002084F84C
+S31508003808BD0310BD0120704770B504460D46006813
+S31508003818066C00EB411303F530639A6821690129A0
+S3150800382811D037498E4254D03DB9C5EBC50293002D
+S315080038382344D3F81032002B5CD0E9B2204600F0B6
+S31508003848C1FF002070BD12F0080F09D02D498E421D
+S31508003858F7D912F4004FF4D04FF400429A60F0E713
+S3150800386812F0200F02D020229A60EAE712F0280FF9
+S31508003878E7D124498E4206D912F4004F03D04FF4F3
+S3150800388800429A60DDE7E900491B8A002244D2F81B
+S3150800389804121B69C3F31203C91AC2F81412D2F820
+S315080038A80412D2F808320B44C2F8083235B9C5EB07
+S315080038B8C50293002344D3F8103223B1E9B220464F
+S315080038C800F080FFBDE704F571720121FFF7B6FB2A
+S315080038D8F4E712F4004F03D04FF400429A60B0E7B9
+S315080038E812F0200F01D020229A60E9B2204600F093
+S315080038F869FFA6E704F571720021FFF79FFB9CE7AD
+S315080039080A31544F0A30544F38B5044603681D6CBB
+S3150800391803EB4111D1F8082B0E4B9D4207D901F547
+S31508003928306112F4004F02D04FF400438B602046F2
+S3150800393800F040FF074B9D4202D92369012B01D0AD
+S31508003948002038BD04F5717201212068FFF776FB5F
+S31508003958F6E700BF0A30544F2DE9F84F04460568C4
+S315080039682846FFF757FB08B1BDE8F88F2F460646E5
+S315080039782068FFF71EFB0028F6D02068FFF719FB1A
+S3150800398810F0020F04D02268536903F0020353614A
+S315080039982068FFF70EFB10F0100F15D02268936900
+S315080039A823F010039361D5F8208008F00F09C8F3AF
+S315080039B84343022B00F08580062B00F0A580226879
+S315080039C8936943F0100393612068FFF7F2FA10F43D
+S315080039D8002F40F0AD802068FFF7EBFA10F4802F2F
+S315080039E840F0F1802068FFF7E4FA0028C0F25F810A
+S315080039F82068FFF7DEFA10F4006F0AD0D5F8083801
+S31508003A0813F0010F40F06D812268536903F40063CF
+S31508003A1853612068FFF7CDFA10F0006F15D02268B9
+S31508003A28536903F00063536194F8F433002B40F0AC
+S31508003A385C81012184F8F41323685B6DC3F383035F
+S31508003A48C4F8F8332046FFF789FD2068FFF7B1FA6E
+S31508003A5810F4805F40F04D812068FFF7AAFA10F449
+S31508003A68005F40F0AB812068FFF7A3FA10F0080F53
+S31508003A7840F0BC812068FFF79CFA10F4801F40F0DC
+S31508003A88BE812068FFF795FA10F4001F40F0C1813F
+S31508003A982068FFF78EFA10F0804F40F0C48120683E
+S31508003AA8FFF787FA10F0040F3FF45EAF23685D68E6
+S31508003AB815F0040F40F0C081226853682B43536001
+S31508003AC852E747F6F07318EA030F3FF478AF4FEA60
+S31508003AD818184FEAC90BABEB09034FEA830AA24445
+S31508003AE8C8F30A02DAF808122846FFF7A7F9C8F34E
+S31508003AF80A08DAF808324344CAF80832DAF81432F7
+S31508003B084344CAF814325AE7082204F5717128465C
+S31508003B18FFF794F9C8F30A184FEAC903A3EB090192
+S31508003B288A002244D2F814324344C2F8143246E7CB
+S31508003B382068FFF742FA8046B14617E007EB4913B3
+S31508003B480122C3F8082B49462046FFF75DFE1DE00B
+S31508003B5807EB49130822C3F8082B49462046FFF7FE
+S31508003B68D3FE16E009F101094FEA5808B8F1000F23
+S31508003B783FF431AF18F0010FF4D05FFA89F12068E5
+S31508003B88FFF72BFA824610F0010FD7D11AF0080F63
+S31508003B98DED11AF0100F04D007EB49131022C3F828
+S31508003BA8082B1AF0200F04D007EB49132022C3F874
+S31508003BB8082B1AF4005FD5D007EB49134FF40052C7
+S31508003BC8C3F8082BCEE72068FFF7FFF98046B14609
+S31508003BD82AE05946204600F001FE1AF0080F04D0DC
+S31508003BE807EB49130822C3F808291AF0100F04D05E
+S31508003BF807EB49131022C3F808291AF0400F04D016
+S31508003C0807EB49134022C3F808291AF0020F04D013
+S31508003C1807EB49130222C3F808291AF0800F41D185
+S31508003C2809F101094FEA5808B8F1000F3FF4DAAE6E
+S31508003C3818F0010FF4D05FFA89FB59462068FFF798
+S31508003C48D5F9824610F0010FC7D009F00F030121F4
+S31508003C5801FA03F2D7F8343823EA0203C7F83438E6
+S31508003C6807EB4913C3F8081923698B42B1D14FEA00
+S31508003C78C902A2EB090293002344596C9A6C0A44B8
+S31508003C889A64B9F1000FA4D1C9EBC9029300234479
+S31508003C981B6D002B9DD104F5717201212068FFF771
+S31508003CA8CDF996E749462046FFF759FCB8E7D5F80F
+S31508003CB8043823F00103C5F8043894F8F433012BC3
+S31508003CC808D0204600F0D0FD2268536903F0004367
+S31508003CD853618DE6002184F8F4132046FFF73EFC6D
+S31508003CE8F2E7204600F0A6FD8EE6204600F0A2FD83
+S31508003CF8ABE605F50068D8F8043023F00103C8F8E0
+S31508003D08043010212068FEF75FFD20E007EB461314
+S31508003D184FF67F31C3F80819D3F8002922F40012A0
+S31508003D28C3F80029D3F8002942F00062C3F800292D
+S31508003D38C3F8081BD3F8002B22F40012C3F8002B8B
+S31508003D48D3F8002B42F00062C3F8002B01366368EB
+S31508003D58B342DBD8D8F81C3043F00113C8F81C3036
+S31508003D68236BEBB1D8F8843043F00B03C8F88430DA
+S31508003D78D8F8443043F00B03C8F84430D5F800386F
+S31508003D8823F4FE63C5F8003804F57172217C2068AF
+S31508003D98FFF754F92268536903F4805353615BE6C5
+S31508003DA8D8F8142042F22B031343C8F81430D8F86D
+S31508003DB8103043F00B03C8F81030DFE72068FFF728
+S31508003DC82DF92068FEF7F0FDE0602568FFF75CFA34
+S31508003DD8227B01462846FEF75DFC204600F010FDCA
+S31508003DE82268536903F4005353613CE6204600F001
+S31508003DF800FD2268536903F0080353613AE6002177
+S31508003E08204600F040FD2268536903F48013536185
+S31508003E1837E60021204600F030FD2268536903F48E
+S31508003E280013536134E6204600F033FD22685369CF
+S31508003E3803F08043536132E6204600F034FD3BE642
+S31508003E48026890F8BC33012B16D010B5012380F808
+S31508003E58BC33836A012B07D004460068FFF791F83C
+S31508003E68002084F8BC0310BD8369012BF4D0936B3A
+S31508003E7843F480339363EFE70220704790F8BC3326
+S31508003E88012B0BD010B50446012380F8BC33006813
+S31508003E98FFF783F8002084F8BC0310BD022070479A
+S31508003EA890F8BC33012B0DD010B50446012380F8D1
+S31508003EB8BC3380F838100068FFF753F8002084F8F8
+S31508003EC8BC0310BD02207047F8B511F0800F27D142
+S31508003ED801F00F05EE00771BBC00274604F5FC74B5
+S31508003EE8044404340744002587F8FD5101F00F01FE
+S31508003EF82170A260E370627802B1E180022B1ED0BD
+S31508003F0890F8BC33012B1DD00546012380F8BC3335
+S31508003F1821460068FEF758FD002085F8BC03F8BD61
+S31508003F2801F00F06F500AF1BBC00274638340444D9
+S31508003F3804343E460644012586F83D50D6E7002354
+S31508003F482371DDE70220EAE738B511F0800F20D1A2
+S31508003F5801F00F04E200151BAB001D4603F5FC73C0
+S31508003F68034404330544002285F8FD2101F00F01B6
+S31508003F78197090F8BC23012A1AD00446012280F841
+S31508003F88BC2319460068FEF767FD002084F8BC03C1
+S31508003F9838BD01F00F04E200151BAB001D46383387
+S31508003FA8034404332C460444012284F83D20DDE703
+S31508003FB80220EDE770B501F00F05EE00711B8C00C5
+S31508003FC804F5FC740444211D761BB4000444C4F8A3
+S31508003FD80822C4F810320023C4F8143284F8FD31D4
+S31508003FE884F8FC510369012B06D065B9DAB2006872
+S31508003FF8FEF77AFD002070BDC5EBC506B40004447B
+S31508004008C4F80C22F1E7DAB20068FEF70DFEF1E70C
+S3150800401801F00F01C1EBC1018B001844D0F8140256
+S31508004028704770B501F00F05EE00711B8C00383427
+S315080040380444211D761BB4000444A26423650023A6
+S315080040486365012384F83D3084F83C500369012BE5
+S3150800405806D05DB9DAB20068FEF746FD002070BDE5
+S31508004068C5EBC506B4000444E264F2E7DAB20068B0
+S31508004078FEF7DAFDF2E738B501F00F0543689D4209
+S3150800408836D811F0800F20D1CA00541AA3001C464E
+S3150800409803F5FC730344043322460244002182F8DC
+S315080040A8FD1101229A701D7090F8BC23012A21D0AF
+S315080040B80446012280F8BC2319460068FEF7D2FE9A
+S315080040C87DB1002084F8BC0338BDEA00511B8B007B
+S315080040D819463833034404330144012281F83D2044
+S315080040E8DFE704F57172217C2068FEF7A7FFE8E789
+S315080040F80120E9E70220E7E710B501F00F04436855
+S315080041089C422CD811F0800F1DD1E3001A1B910090
+S315080041180A4601F5FC71014404310244002382F879
+S31508004128FD3100238B700C7090F8BC33012B18D026
+S315080041380446012380F8BC330068FEF7C0FE002059
+S3150800414884F8BC0310BDE3001A1B91000A463831EF
+S31508004158014404310244012382F83D30E1E7012095
+S31508004168F0E70220EEE7000012230B8000487047AC
+S315080041785804002004230B80004870476C0400206C
+S315080041880023934216D230B40BE0373401F81340B3
+S3150800419800015C00013400250D550133DBB293425A
+S315080041A806D2040F092CF0D8303401F81340EFE78B
+S315080041B830BC70477047000038B50A4B1868043396
+S315080041C81C6804331B68C01800D138BD064D082280
+S315080041D8A91CFFF7D5FF042205F112012046FFF7AF
+S315080041E8CFFFF2E700E8F11F7004002008B51A238C
+S315080041F80B80FFF7E1FF014808BD00BF70040020E7
+S3150800420808B50A4628B905490548FCF79AFC03483B
+S3150800421808BD02490248FCF794FCF8E7EC120020AE
+S31508004228A85D000810B5044C0A4621460348FCF761
+S3150800423888FC204610BD00BFEC120020985D0008D7
+S3150800424808B50A4628B905490548FCF77AFC03481B
+S3150800425808BD02490248FCF774FCF8E7EC1200208E
+S31508004268785D000808B50A4628B905490548FCF7DF
+S3150800427868FC034808BD02490248FCF762FCF8E7EF
+S31508004288EC120020805D0008014B1880704700BFBB
+S315080042980E05002008B500F0FBFE0E4B1B68984279
+S315080042A80FD30D4B1B786BB90B4B01221A700B4BAE
+S315080042B880229A6100F0ECFE094B1B881844054BCE
+S315080042C8186008BD044B00221A70044B4FF400020C
+S315080042D89A61EFE71405002010050020000402582B
+S315080042E80E050020024B4FF400029A61704700BF82
+S315080042F80004025808B5054B1B6913F4005F03D17F
+S31508004308FFF7F0FF012008BD0020FCE70008025867
+S3150800431808B56420FFF7B8FF08BD08B5FFF7BAFF68
+S3150800432808BD70477047704708B5574A136823F0A1
+S315080043380F0343F004031360136803F00F03042BF9
+S3150800434840F09C80514AD36823F0070343F00203E0
+S31508004358D360936943F4404393614D4B1A6842F41A
+S3150800436880221A601A6842F480321A60484B1B6821
+S3150800437813F4003FFAD0464B9A6A22F0030242F039
+S3150800438802029A62DA6A42F48032DA62DA6A42F435
+S315080043980032DA62DA6A22F00C0242F00402DA62C1
+S315080043A8DA6A22F00202DA629A6A22F47C7242F027
+S315080043B840029A621A6B3749114040F2DF120A43E3
+S315080043C81A631A6B22F47E4242F400721A631A6B55
+S315080043D822F4FE0242F498121A631A6B22F0FE427D
+S315080043E842F080721A631A6842F080721A60284B83
+S315080043F81B6813F0007FFAD0254B9A6922F00F0242
+S3150800440842F008029A611A6922F0070242F003028A
+S315080044181A619A6922F470629A619A6922F00F02FF
+S3150800442842F008029A61DA6922F0700242F0400204
+S31508004438DA61DA6922F4E06242F48062DA619A693A
+S3150800444822F0700242F040029A611A6A22F070025B
+S3150800445842F040021A6210490A6822F007020A6006
+S315080044681A6D22F040521A655A6D22F4401242F427
+S3150800447880125A650948FEF729FF08BD67210848CA
+S3150800448800F0D4FA5EE700BF002000520048025840
+S315080044980044025800FEFFFF5444025800389C1C8A
+S315080044A8BC5D000808B5FCF789FDFFF73DFF08BDA8
+S315080044B808B5FFF7F7FF00F0C5FA00F0D1FAFCE7F0
+S315080044C82DE9F0418EB0514CD4F8F43043F002038C
+S315080044D8C4F8F430D4F8F43003F002030793079BC2
+S315080044E8D4F8E03043F00103C4F8E030D4F8E030FB
+S315080044F803F001030693069BD4F8E03043F0020361
+S31508004508C4F8E030D4F8E03003F002030593059BBD
+S31508004518D4F8E03043F00403C4F8E030D4F8E030C7
+S3150800452803F004030493049BD4F8E03043F008032B
+S31508004538C4F8E030D4F8E03003F008030393039B8B
+S31508004548D4F8E83043F48023C4F8E830D4F8E830DF
+S3150800455803F480230293029BD4F8EC3043F4807367
+S31508004568C4F8EC30D4F8EC3003F480730193019B5B
+S31508004578802308930123099300250A950B950C9522
+S31508004588234F08A93846FDF78DFE4FF400530893C4
+S3150800459809950C9508A91F48FDF784FE4FF440783D
+S315080045A8CDF82080022609960A950B950C950723BF
+S315080045B80D9308A91848FDF775FECDF820800996C9
+S315080045C80A960B950C9509230D9308A93846FDF705
+S315080045D869FE4FF4C0530893099603230A930B956B
+S315080045E80C950A230D9308A90C48FDF75BFED4F829
+S315080045F8D83043F00063C4F8D830D4F8D83003F07C
+S3150800460800630093009B0EB0BDE8F0810044025891
+S315080046180004025800080258000C02580000025804
+S3150800462810B5FCF70DFD214C4FF40003A361204893
+S31508004638FDF74CFD1F48FDF749FD2046FDF746FDE9
+S315080046481D48FDF743FD1D4BD3F8D82022F000621C
+S31508004658C3F8D820D3F8EC2022F48072C3F8EC20EB
+S31508004668D3F8E82022F48022C3F8E820D3F8E0201B
+S3150800467822F00802C3F8E020D3F8E02022F004026A
+S31508004688C3F8E020D3F8E02022F00202C3F8E020BD
+S31508004698D3F8E02022F00102C3F8E020D3F8F4208A
+S315080046A822F00202C3F8F42010BD00BF0004025825
+S315080046B8000C025800080258000002580044025824
+S315080046C82023038000487047C40400200A23038077
+S315080046D800487047E404002008B590F89C32032B7C
+S315080046E801D0002008BD01F04DFAFAE708B501F037
+S315080046F849FA002008BD08B5084601F077FA0020EF
+S3150800470808BD000008B50B7813F0600F06D14B7882
+S315080047180A2B14D00B2B17D0062B01D0002008BD66
+S315080047284B881B0A212B04D00B491722FBF78FFE4F
+S31508004738F4E7CA88172A28BF17220849F6E7012284
+S315080047480749FBF784FEE9E78B7813B9044A13602F
+S31508004758E4E7FBF7D6FEE1E7CD040020D6040020FF
+S315080047681805002010B50446812100F02FF901210B
+S31508004778204600F02BF9002010BD000010B50446AD
+S3150800478840230222812100F016F940230222012142
+S31508004798204600F010F94023034A0121204600F07C
+S315080047A83DF9002010BD00BFEC14002000487047F2
+S315080047B8EC14002008B500F57171D0F80404FCF76C
+S315080047C824FA08BD08B5C1EBC10293000344D3F81F
+S315080047D80822D0F80404FCF746FA08BD08B5C1EB68
+S315080047E8C102930003449A6CD0F80404FCF785FACE
+S315080047F808BD08B5D0F80404FCF72AFB08BD000074
+S3150800480810B50446C3684BB1022B01D1012106E055
+S315080048189121074800F00AF9012100E00021D4F89F
+S315080048280404FCF7FEFAD4F80404FCF7D2FA10BD1F
+S31508004838C45D000810B50446D0F80404FCF7F4FA79
+S315080048482268D2F8003E43F00103C2F8003E236A04
+S3150800485823B1044A136943F006031361FFF762FD9F
+S3150800486810BD00BF00ED00E010B50446FFF75BFD7C
+S31508004878D4F80404FCF7E1FA10BD08B5D0F8040426
+S31508004888FCF7F6FA08BD08B5D0F80404FCF7EEFA02
+S3150800489808BD10B504460120FFF743FDD4F8040403
+S315080048A8FCF7E8FA10BD10B504460020FFF739FDF5
+S315080048B8D4F80404FCF7E0FA10BD000003780BB13D
+S315080048C80020704710B503461748C0F80434C3F8E3
+S315080048D8C002164B0360092343600222C260002304
+S315080048E8036182610122C261036243628362C36211
+S315080048F80363FEF79EFE80B90B4C80212046FEF71F
+S3150800490815FE402200212046FEF7ECFD80220121F3
+S315080049182046FEF7E7FD002010BD4FF493710448C2
+S3150800492800F084F8E8E700BF2C15002000000840CE
+S31508004938C45D0008D0F8C03211F0800F08D101F024
+S315080049487F01C1EBC1018A00134493F8FE01704741
+S3150800495801F07F01C1EBC1018A00134493F83E00B8
+S31508004968704708B5D0F8C002FFF752FB08BD022801
+S3150800497807D8DFE800F00206040000207047012087
+S3150800498870470220704708B5D0F8C002FEF72BFF1B
+S31508004998FFF7EDFF08BD08B5D0F8C002FEF7E2FE3E
+S315080049A8FFF7E5FF08BD08B5D0F8C002FEF7FBFE1D
+S315080049B8FFF7DDFF08BD10B51C4613462246D0F89A
+S315080049C8C002FFF781FAFFF7D2FF10BD08B5D0F885
+S315080049D8C002FFF7B9FAFFF7CAFF08BD08B5D0F84D
+S315080049E8C002FFF748FBFFF7C2FF08BD08B5D0F8B5
+S315080049F8C002FFF781FBFFF7BAFF08BD08B5D0F874
+S31508004A08C002FFF74DFAFFF7B2FF08BD08B5D0F8A0
+S31508004A18C002FFF706FBFFF7AAFF08BD08B5D0F8DE
+S31508004A28C002FFF7C7FAFFF7A2FF08BD08B500F0EE
+S31508004A3805F8FCE708B5FFF76BFC08BD08B5FFF7EE
+S31508004A486CFC08BD08B500F0E1FEFFF7F3FF00F0BF
+S31508004A58FDFA01F0F7F800F057F800F049F808BD34
+S31508004A6808B5FFF7EBFF00F005FB00F061F800F06A
+S31508004A7801F808BD08B500F0DFF8012803D00B4B8C
+S31508004A881B78012B00D008BD00F002FB084B1B68F9
+S31508004A98084A1268134403F5FA739842F3D3034B8A
+S31508004AA800221A7000F0B6FEEDE700BF20050020C8
+S31508004AB81C05002024050020014B1860704700BF1C
+S31508004AC81C050020014B1868704700BF1C0500200C
+S31508004AD808B5054B1B78012B00D008BD00F0D8FA9D
+S31508004AE8024B1860F9E700BF2005002024050020BE
+S31508004AF808B5044B01221A70FFF7EAFFFFF7BAFF59
+S31508004B0808BD00BF2005002010B500F005FA00F022
+S31508004B18B9FB064C0123237000F0EAFA0023237038
+S31508004B2800F064FF0223237010BD00BFEE040020C6
+S31508004B3800B583B00DF10701184800F037FC0128C5
+S31508004B4810D00DF10701154800F00EFB012812D008
+S31508004B580DF10701114800F0C9FF012814D003B068
+S31508004B685DF804FB0E4B01221A709DF807100B48D6
+S31508004B7800F0F2F9E5E70A4B00221A709DF80710CB
+S31508004B88064800F0E9F9E3E7054B02221A709DF892
+S31508004B980710024800F0E0F9E1E700BF2805002001
+S31508004BA8EE04002008B500F067FF08BD38B50446CE
+S31508004BB80D460E4B1B78012B09D00C4B1B7853B1AD
+S31508004BC80A4B1B78022B0BD000F0BEF938BDC9B2C8
+S31508004BD800F0BAFBF1E7E9B2204600F0A9FAEFE7D8
+S31508004BE8E9B2204600F058FFEEE700BFEE040020C1
+S31508004BF8074B1B78022B05D0032B05D0012B05D0B4
+S31508004C08402070473F2070470020704708207047AB
+S31508004C18EE040020074B1B78022B05D0032B05D082
+S31508004C28012B05D0402070473F2070470020704769
+S31508004C3808207047EE04002008B500F07BF9034603
+S31508004C4800B10123184608BD014B00225A70704767
+S31508004C5868050020034BFE22DA7018710222A3F8B1
+S31508004C68442070476805002010B5054C00232370BA
+S31508004C78FFF7EAFFFF23E3700123A4F8443010BDC9
+S31508004C8868050020064BFF22DA7000221A71597847
+S31508004C9859719A71DA711A720622A3F84420704774
+S31508004CA86805002008B50020FFF7D4FF08BD0000F6
+S31508004CB8074BFF22DA70074A9A6400221A715A715A
+S31508004CC89A710722C3F807200822A3F844207047D8
+S31508004CD868050020D05D0008044BFF22DA70426898
+S31508004CE89A640122A3F84420704700BF680500208B
+S31508004CF808B53120FFF7AEFF08BD000038B5084CE7
+S31508004D08FF23E370002525716571FFF771FFA07110
+S31508004D18E571257265720723A4F8443038BD00BFCB
+S31508004D286805002038B5FFF78FFF0E4C012525705A
+S31508004D38FF23E3701023237100236371FFF758FFDD
+S31508004D48A071FFF767FFE071FFF764FFC0F307205C
+S31508004D5820726572A5720823A4F8443000F072FF21
+S31508004D6838BD00BF6805002038B50546FFF740FF7F
+S31508004D786A7890420FD90A4CA16C201D00F06AFD8A
+S31508004D88FF23E3706A78A36C1344A3646B78013332
+S31508004D98A4F8443038BD2220FFF75CFFFAE700BFC5
+S31508004DA86805002038B50446FFF722FF637898425D
+S31508004DB811D961680A4DA9646278281D00F04AFD70
+S31508004DC8FF23EB706278AB6C1344AB6463780133EA
+S31508004DD8A5F8443038BD2220FFF73CFFFAE700BFA4
+S31508004DE868050020F8B50546174600244E1E39B151
+S31508004DF815F8013B1C44E4B2FFF720FE3146F5E7F7
+S31508004E083C600120F8BD000010B5084CFF23E3708C
+S31508004E18E21D4168A06CFFF7E5FF20710023637166
+S31508004E28A3710823A4F8443010BD00BF6805002004
+S31508004E3838B505460D4B9C6CFFF7DAFE6A1C411E11
+S31508004E48204600F003FF60B1084CFF23E370FFF724
+S31508004E58CFFE0138A36C0344A3640123A4F84430A5
+S31508004E6838BD3120FFF7F6FEFAE700BF68050020CF
+S31508004E7810B50446FFF7BCFE01386378984213DD7F
+S31508004E88114BFF22DA700122A3F84420617879B120
+S31508004E98A21C0D4B986C00F0D9FE88B161780A4AB5
+S31508004EA8936C0B44936410BD2220FFF7D3FEFAE7F0
+S31508004EB800F0DCFE0028F6D13120FFF7CBFEF2E73A
+S31508004EC83120FFF7C7FEEEE76805002008B54168F8
+S31508004ED8074B986C00F0BEFE30B1054BFF22DA701E
+S31508004EE80122A3F8442008BD3120FFF7B3FEFAE7EC
+S31508004EF86805002008B500F08DFC034BFF22DA7020
+S31508004F080122A3F8442008BD6805002008B589B21F
+S31508004F18FFF74CFE08BD0000054B00221A709A647C
+S31508004F2883F84320A3F844209A705A70704700BF44
+S31508004F3868050020034B1B780BB101207047002039
+S31508004F48704700BF68050020024B002283F84320FB
+S31508004F58704700BF6805002008B50378FF2B23D0E3
+S31508004F68354A1278012A2BD1C93B352B53D8DFE8A5
+S31508004F7803F04052524F52524C43494652525252EB
+S31508004F8852525252525252525252525252525252EB
+S31508004F98525252525252525252525252312B282E71
+S31508004FA85252523452373A3DFFF7BCFE224B93F819
+S31508004FB84330012B33D0204BB3F94410002932DC97
+S31508004FC808BDFFF7D1FEF1E7FFF7ECFEEEE7FFF7BE
+S31508004FD883FEEBE7FFF718FFE8E7FFF769FEE5E763
+S31508004FE8FFF760FEE2E7FFF74DFEDFE7FFF73CFE57
+S31508004FF8DCE7FFF71DFFD9E7FFF73AFFD6E7FFF724
+S315080050087DFED3E7FFF762FFD0E7FFF773FFCDE72B
+S31508005018FFF76EFECAE72020FFF71CFEC6E710203A
+S31508005028FFF718FEC7E71846012380F84330033010
+S31508005038FFF76CFFC4E700BF68050020024B002293
+S315080050481A605A609A60704710E000E008B5FFF7E2
+S31508005058F5FF054B054A5A6000229A600521196032
+S31508005068034B1A6008BD00BF10E000E0FF520700B6
+S31508005078B4050020044B1B6813F4803F03D0034A89
+S31508005088136801331360704710E000E0B405002088
+S3150800509808B5FFF7EFFF014B186808BDB4050020EF
+S315080050A808B5FFF7F5FF08BD054BDB6913F0200FB8
+S315080050B804D0034B5B6A03700120704700207047D1
+S315080050C80048004010B5094B9862FFF7E1FF00F168
+S315080050D80A04064BDB6913F0800F05D1FFF7AEFC0F
+S315080050E8FFF7D6FFA042F4D910BD00BF004800401C
+S315080050F810B588B00D4C236823F0010323600023FC
+S3150800510800934FF4614201920293039304930C228D
+S3150800511805920693079369462046FEF7DDF8236845
+S3150800512843F00103236008B010BD00BF00480040E3
+S3150800513870B506460D4640290ED82846FFF7C2FF21
+S315080051480024ABB2A3420CD9FFF778FC305DFFF711
+S31508005158B9FF0134A4B2F4E784210248FFF766FCD4
+S31508005168EBE770BDD85D000870B5254B1C78BCB94F
+S315080051782448FFF799FF012801D0204670BD214B26
+S315080051881B78013BDBB23F2BF7D8FFF781FF1E4B95
+S3150800519818601E4B00221A70194B01221A70ECE788
+S315080051A806460D46194B1B78013316481844FFF76F
+S315080051B87BFF0446012815D1144B1A780132D2B25E
+S315080051C81A70104B1B789A4201D00024D5E710496B
+S315080051D8304600F03FFB0A4B00221A700B4B1B782F
+S315080051E82B70CAE7FFF754FF074B1B6864339842CE
+S315080051F803D90024024B1C70BFE70024BDE700BF93
+S31508005208F9050020B8050020FC050020FA0500204D
+S31508005218B9050020F0B4194D2C6D24F040542C65BE
+S31508005228002401E00134E4B2112C23D8144D15F8F2
+S31508005238146005EB44056F78F51905FB00054FF46E
+S31508005248FA5CBCFBF5FC05FB0CF5B5F5FA5FE9D18C
+S3150800525835463D4405FB000C4FF4FA55B5FBFCF5FD
+S315080052680D80013DADB2B5F5007FDBD216701F7013
+S31508005278012000E00020F0BC704700BF0044025837
+S31508005288285E000870B58CB00023ADF82E308DF86E
+S315080052982D308DF82C300BAB0DF12D020DF12E01AA
+S315080052A84FF4FA70FFF7B6FF002842D0234C244B78
+S315080052B823600025A560E560012626746574A57433
+S315080052C8BDF82E306361A6619DF82D30E3619DF81F
+S315080052D82C3023626662A662E66226636563A66365
+S315080052E8E563266404236364A564E3642565636546
+S315080052F8A565E66525666566A3662046FCF7F4FA9D
+S31508005308039504950596069640F2676307930893EE
+S31508005318099503A92046FCF731FC00963346022274
+S3150800532811462046FCF76DFC2046FCF786FC0CB0B7
+S3150800533870BDB8210348FFF779FBB7E700060020D8
+S3150800534800A00040005E000810B58AB040F2E1737C
+S315080053580193002302930393090404910593069382
+S3150800536807930893522309930123024601A90E4875
+S31508005378FCF77DFC08B10AB010BD01210A48FCF704
+S31508005388ACFC0028F7D1FFF783FE00F132040121AF
+S315080053980548FCF781FD0028EDD0FFF74FFBFFF71E
+S315080053A877FEA042F3D9E6E70006002030B58BB0B1
+S315080053B804460D4640211048FCF777FD10B9002031
+S315080053C80BB030BD23466A4640210B48FCF798FCCB
+S315080053D868B9009A40F267639A4201D00020EFE75D
+S315080053E8019B33B99DF80E302B700120E8E70020A1
+S315080053F8E6E70020E4E700BF0006002038B50546C2
+S31508005408002401E00134E4B20E2C12D8FFF716FB8B
+S3150800541804EB44029300084AD358AB42F2D804EB8B
+S3150800542844029100044A0A4452681344AB42E9D933
+S3150800543800E0FF24204638BD4C5E000808B5C1F3D5
+S31508005448090363B903688B4201D1012008E040F8D3
+S31508005458041B4FF4806200F0FDF9012000E00020EB
+S3150800546808BD2DE9F04107460068FFF7C7FFFF2882
+S3150800547804D14FF000084046BDE8F081FCF780FFEC
+S3150800548800264FF0010805E04FF00008B8F1000FB4
+S315080054981CD001361F2E19D83D68740125443C4492
+S315080054A80434FFF7CBFA224629460120FDF730F8DF
+S315080054B850B900231F2BE9D8595DE25CD2B2914254
+S315080054C8E2D10133DBB2F5E74FF00008FCF786FFB7
+S315080054D8D1E7000070B50E460E4B984212D0054625
+S315080054E80D4B994209D10B4C254624B1314628461D
+S315080054F8FFF7A4FF58B1204670BDFFF7B2FF20B1E9
+S315080055082C46F2E7054C2546EFE70024EDE700248C
+S31508005518F1E700BFA40A002000000208A006002040
+S315080055282DE9F84306460C4617461D46DFF88480DB
+S3150800553801EA08080368B3F1FF3F0AD03368434510
+S315080055480ED14FF00109B9F1010F12D04846BDE84E
+S31508005558F8834146FFF772FF81460028F3D0EDE746
+S3150800556841463046FFF7B6FF0646E8B14FF001094F
+S31508005578E9E73368E41A3444043405E017F8013BCC
+S3150800558804F8013B013DE1D0FFF758FA331DE31A49
+S31508005598B3F5806FF2D308F580613046FFF79AFFB6
+S315080055A8064620B1041DE9E74FF00009CEE74FF09B
+S315080055B80009CBE700FCFFFF70B586B004460D4628
+S315080055C800230093884203D80E2938D8012600E01C
+S315080055D8002616B9304606B070BDFCF7D1FE01E0C4
+S315080055E80134E4B2AC4227D8FFF728FA1549630014
+S315080055F823449A008B188A585B68002B18BFB2F1A7
+S31508005608FF3F18D000230193202305930A46630019
+S315080056181819810008461144497A02910244137AF6
+S31508005628039301230493694601A8FCF7B9FC0028EB
+S31508005638D6D0002600E00026FCF7D0FECAE70026EA
+S31508005648C8E700BF4C5E00084FF0FF33024A1360F4
+S31508005658024A1360704700BFA0060020A40A00206B
+S3150800566870B504460D4616464A1E154B1B1A9A422D
+S3150800567803D9002001280ED070BDFFF7BFFEFF280A
+S3150800568801D10020F8E728190138FFF7B7FEFF28E7
+S3150800569814D00120EEE70B4B23400B4A934206D061
+S315080056A82B46324621460948FFF73AFFE4E72B46D8
+S315080056B8324621460648FFF733FFDDE70020DBE7D9
+S315080056C8FFFF1F0800FCFFFF00000208A0060020D5
+S315080056D8A40A002070B54A1E0F4B1B1A9A4205D910
+S315080056E8FF210E460020012812D070BD05460C463B
+S315080056F8FFF784FE064660190138FFF77FFE014664
+S31508005708FF2818BFFF2E01D00120ECE70020EAE7A2
+S315080057183046FFF751FFE8E7FFFF1F08104B1B68E5
+S31508005728B3F1FF3F01D10120704700B583B00C4A99
+S31508005738536891680B44D1680B4411690B44516945
+S315080057480B4491690B44D26913445B42019301AA3D
+S3150800575804210448FFF784FF03B05DF804FB00BF83
+S31508005768A40A0020980202080D4B1B680D4A126805
+S315080057781A440D4B1B6813440C4A126813440C4A06
+S3150800578812681A440B4B1B681A440B4B1B681344C4
+S315080057980A4A1268DA4201D1012070470020704788
+S315080057A80000020804000208080002080C000208A3
+S315080057B810000208140002081800020898020208D5
+S315080057C808B50E4B1B68B3F1FF3F07D10C4B1B6896
+S315080057D8B3F1FF3F09D10123184608BD0748FFF76B
+S315080057E840FE03460028F7D0F0E70548FFF739FEDC
+S315080057F803460028F0D00123EEE700BFA40A0020DC
+S31508005808A0060020004870470000020808B500F006
+S3150800581838FA08BD10B500F021FA00B910BDFEF730
+S3150800582869FD0028FAD0FFF7BDF9FBF76FFBFFF70C
+S3150800583805FC00F017FA054B0340054A936000F08B
+S3150800584811FA446800F01FFAA047E7E780FFFF1F30
+S3150800585800ED00E070B50D460446531E9EB23AB1F7
+S3150800586815F8013B04F8013BFFF7E8F83246F4E778
+S3150800587870BD0000094B03F11801002232B19A7471
+S3150800588800225A61064B054A1A6070479A7459618C
+S31508005898183318310132D2B2F0E700BFE80E0020FB
+S315080058A8180F00200A4B1B6883B110B45C69084AB4
+S315080058B8146019749860D86000225A7418600139FF
+S315080058C808445860987C5DF8044B7047FF20704779
+S315080058D8180F002038B504460D4601281CD8620062
+S315080058E82244D100114B0B445A7C1B7C9A4219D08E
+S315080058F80E4B0B44DA6815705A7C01325A74DA680A
+S315080059080132DA605B689A420ED9084A0846515845
+S315080059180244D160012038BD4FF4E1710448FFF70D
+S3150800592885F8DCE70020F6E70120F4E7E80E002012
+S31508005938005F000808B50146024B1878FFF7CAFF4A
+S3150800594808BD00BF1C0F002038B504460D460128BF
+S315080059581ED804EB4403DA00124B13445B7CEBB104
+S3150800596862002244D1000F4B0B449A6812782A70B9
+S315080059785A7C013A5A749A6801329A605B689A4264
+S315080059880ED9084A0846515802449160012006E093
+S315080059984FF4F2710448FFF749F8DAE7002038BDF2
+S315080059A80120FCE7E80E0020005F000808B501465C
+S315080059B8024B1878FFF7C8FF08BD00BF600F002024
+S315080059C810B50446012806D804EB4404E200054B42
+S315080059D81344587C10BD4FF401710348FFF726F8A5
+S315080059E8F2E700BFE80E0020005F000838B5FFF7A9
+S315080059F841FF1B4C4021601CFFF754FF2070194DCE
+S31508005A084021681CFFF74EFF28702378FF2B1DD00E
+S31508005A18FF281BD0144C002214492046FBF7ACF883
+S31508005A2813492046FBF7D1F80120FEF77AFC2046F1
+S31508005A38FBF7D2F8FCF79CFCD4F8C002FEF700FA8C
+S31508005A48FFF740F8B0F5FA6F05D338BD8521094840
+S31508005A58FEF7ECFFDEE74FF4FA60FFF72DF8F4E7F8
+S31508005A681C0F0020600F0020A40F00203C04002013
+S31508005A788C040020005F000810B5064CD4F8C00254
+S31508005A88FEF7FCF92046FBF78EF80020FEF749FCDE
+S31508005A9810BD00BFA40F002070B506460D463F2965
+S31508005AA806D82846FFF746FF012806D100240FE046
+S31508005AB8BB210D48FEF7BAFFF3E7BF210A48FEF7F0
+S31508005AC8B5FFF3E7C8210848FEF7B0FF0134A4B2CA
+S31508005AD8ABB2A34207D9FEF7B1FF305DFFF72AFF3D
+S31508005AE80128F3D0EEE770BD005F000870B50646DA
+S31508005AF80D461F4BD3F8C002FDF72EFF1D4B1C7829
+S31508005B089CB91D48FFF752FF012801D0204670BDF1
+S31508005B18194B1B78013BDBB23E2BF7D8154B0122F4
+S31508005B281A70164B00221A70F0E7144B1B780133CB
+S31508005B3811481844FFF73AFF0446012801D0002403
+S31508005B48E4E70E4B1A780132D2B21A700A4B1B7860
+S31508005B589A4201D00024D9E709493046FFF77AFE68
+S31508005B68044B00221A70054B1B782B70CEE700BF32
+S31508005B78A40F0020A812002068120020A9120020ED
+S31508005B886912002030B583B0144B1878FFF718FF50
+S31508005B9808B30546402800D9402500240AE04FF4F2
+S31508005BA8A4710F48FEF742FF9DF807200D4B1A55BA
+S31508005BB80134E4B2A54208D90DF10701074B187854
+S31508005BC8FFF7C2FE0128EFD0E9E7ABB2054A812103
+S31508005BD80548FEF71BFF03B030BD00BF1C0F0020A9
+S31508005BE8005F0008A80E0020A40F002070B5044620
+S31508005BF8FEF7DCFD064621460F48FEF7B2FE85B2DB
+S31508005C08002406E04FF4B5710C48FEF70FFF01347F
+S31508005C18A4B2AC4207D2315D094B1878FFF75AFE91
+S31508005C280128F4D0EEE7FEF7C1FD4023024601211C
+S31508005C380148FEF7F3FE70BDA40F0020005F0008B8
+S31508005C48600F002008B5FFF7FFFC08BD08B5FFF789
+S31508005C5807FD08BD08B5FFF73DFD08BD08B5FFF700
+S31508005C6883FD08BD08B5FFF7CDFD08BD08B5FFF7E4
+S31508005C7855FD034608B9184608BDFFF7A1FD0346B2
+S31508005C88F9E772B6704762B670470A44914200F15E
+S31508005C98FF3300D1704710B511F8014B03F8014FCF
+S31508005CA89142F9D110BD0000F8B500BFF8BC08BC90
+S31508005CB89E467047F8B500BFF8BC08BC9E467047B4
+S31508005CC800000000000000000000000000000000BE
+S31508005CD800000000010000000200000003000000A8
+S31508005CE80400000000000000050000000000000095
+S31508005CF80000000000000000060000000000000088
+S31508005D080000000000000000070000000000002056
+S31508005D18000000000102030401020304060708093B
+S31508005D28000000000102030401020304060708092B
+S31508005D380001020304050607080C10141820304051
+S31508005D480100000002000000040000000600000030
+S31508005D58080000000A0000000C00000010000000FF
+S31508005D68200000004000000080000000000100003C
+S31508005D7844656661756C740057696E5553422042CE
+S31508005D88756C6B20496E7465726661636500000000
+S31508005D984F70656E424C54205573657200000000BA
+S31508005DA857696E5553422042756C6B20446576696F
+S31508005DB8636500006D61696E2E6300007573626421
+S31508005DC85F636F6E662E63004F70656E424C5400B3
+S31508005DD82E2E2F2E2E2F2E2E2F536F757263652F6C
+S31508005DE841524D434D375F53544D333248372F721E
+S31508005DF8733233322E6300002E2E2F2E2E2F2E2E80
+S31508005E082F536F757263652F41524D434D375F5354
+S31508005E18544D333248372F63616E2E6300000000F5
+S31508005E2805020602060307030803090309040A0408
+S31508005E380B040C040C050D050E050F050F061006B8
+S31508005E4810071008000002080000020001010000FF
+S31508005E58000004080000020002010000000006080D
+S31508005E680000020003010000000008080000020004
+S31508005E780401000000000A080000020005010000ED
+S31508005E8800000C08000002000601000000000E08C9
+S31508005E9800000200070100000000100800000200C8
+S31508005EA800020000000012080000020001020000BB
+S31508005EB8000014080000020002020000000016088C
+S31508005EC80000020003020000000018080000020093
+S31508005ED80402000000001A0800000200050200007B
+S31508005EE800001C08000002000602000000001E0848
+S31508005EF800000200070200002E2E2F2E2E2F2E2E0F
+S31508005F082F536F757263652F41524D434D375F5353
+S31508005F18544D333248372F7573622E6300000000DC
+S30D08005F2821030008BD02000870
+S30908005F3099020008BC
+S31508005F3400000000EC02002054030020BC030020EB
+S31508005F44000000000000000000000000000000003F
+S31508005F54000000000000000000000000000000002F
+S31508005F64000000000000000000000000000000001F
+S31508005F74000000000000000000000000000000000F
+S31508005F8400000000000000000000000000000000FF
+S31508005F9400000000000000000000000000000000EF
+S31508005FA400000000000000000000000000000000DF
+S31508005FB400000000000000000000000000000000CF
+S31508005FC400000000000000000000000000000000BF
+S31508005FD400000000000000000100000000000000AE
+S31508005FE40E33CDAB34126DE6ECDE05000B00000073
+S31508005FF4000000000000000000000000000000008F
+S31508006004000000000000000000000000000000007E
+S31508006014000000000000000000000000000000006E
+S31508006024000000000000000000000000000000005E
+S31508006034000000000000000000000000000000004E
+S31508006044000000000000000000000000000000003E
+S31508006054000000000000000000000000000000002E
+S31508006064000000000000000000000000000000001E
+S31508006074000000000000000000000000000000000E
+S3150800608400000000000000000000000000000000FE
+S3150800609400000000000000000000000000000000EE
+S315080060A400000000000000000000000000000000DE
+S315080060B400000000000000000000000000000000CE
+S315080060C400000000000000000000000000000000BE
+S315080060D400000000000000000000000000000000AE
+S315080060E4000000000000000000000000000000009E
+S315080060F4000000000000000000000000000000008E
+S31508006104000000000000000000000000000000007D
+S31508006114000000000000000000000000000000006D
+S31508006124000000000000000000000000000000005D
+S31508006134000000000000000000000000000000004D
+S31508006144000000000000000000000000000000003D
+S31508006154000000000000000000000000000000002D
+S31508006164000000000000000000000000000000001D
+S31508006174000000000000000000000000000000000D
+S3150800618400000000000000000000000000000000FD
+S3150800619400000000000000000000000000000000ED
+S315080061A400000000000000000000000000000000DD
+S315080061B400000000000000000000000000000000CD
+S315080061C400000000000000000000000000000000BD
+S315080061D400000000000000000000000000000000AD
+S315080061E4000000000000000000000000000000009D
+S315080061F4000000000000000000000000000000008D
+S31508006204000000000000000000000000000000007C
+S31508006214000000000000000000000000000000006C
+S31508006224000000000000000000000000000000005C
+S31508006234000000000000000000000000000000004C
+S31508006244000000000000000000000000000000003C
+S31508006254000000000000000000000000000000002C
+S31508006264000000000000000000000000000000001C
+S31508006274000000000000000000000000000000000C
+S3150800628400000000000000000000000000000000FC
+S3150800629400000000000000000000000000000000EC
+S315080062A400000000000000000000000000000000DC
+S315080062B400000000000000000000000000000000CC
+S315080062C400000000000000000000000000000000BC
+S315080062D400000000000000000000000000000000AC
+S315080062E4000000000000000000000000000000009C
+S315080062F4000000000000000000000000000000008C
+S31508006304000000000000000000000000000000007B
+S31508006314000000000000000000000000000000006B
+S31508006324000000000000000000000000000000005B
+S31508006334000000000000000000000000000000004B
+S31508006344000000000000000000000000000000003B
+S315080063540000000000000000AC1200200090D003EA
+S315080063640090D003010000001000000071410008ED
+S315080063747D4100082D42000809420008F54100083D
+S31508006384494200086D42000812010002000000405C
+S31508006394501DAC6000020102030100000403090455
+S315080063A41A030000000000000000000000000000BE
+S315080063B400000000000000000000000085470008F7
+S315080063C46D4700080D4700080000000000000000A3
+S315080063D4F5460008FF460008E146000800000000EC
+S315080063E40000000000000000C94600080000000084
+S315080063F4D546000809022000010100C0320904003C
+S315080064040002FF000000070581024000FF0705019E
+S31508006414024000FF0A0600020000004001000400D2
 S70508000405E9
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_GCC/Prog/bin/demoprog_stm32h743.elf b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_GCC/Prog/bin/demoprog_stm32h743.elf
index 248bbee0..49067f44 100755
Binary files a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_GCC/Prog/bin/demoprog_stm32h743.elf and b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_GCC/Prog/bin/demoprog_stm32h743.elf differ
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_GCC/Prog/bin/demoprog_stm32h743.srec b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_GCC/Prog/bin/demoprog_stm32h743.srec
index d71cd4b9..8cad5fbc 100755
--- a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_GCC/Prog/bin/demoprog_stm32h743.srec
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_GCC/Prog/bin/demoprog_stm32h743.srec
@@ -2,7 +2,7 @@ S01E000062696E2F64656D6F70726F675F73746D3332683734332E7372656323
 S3150802000000000220B10702080108020801080208D6
 S315080200100108020801080208010802080000000097
 S3150802002000000000000000000000000001080208AD
-S31508020030010802080000000001080208510D020822
+S31508020030010802080000000001080208353F02080C
 S315080200400108020801080208010802080108020854
 S315080200500108020801080208010802080108020844
 S315080200600108020801080208010802080108020834
@@ -43,8 +43,8 @@ S315080202800108020801080208010802080000000025
 S311080202900000000001080208EE11AA5541
 S315080202A010B5054C237833B9044B13B10448AFF3A0
 S315080202B000800123237010BD3C04002000000000CA
-S315080202C06444020808B5034B1BB103490348AFF35C
-S315080202D0008008BD000000004004002064440208B3
+S315080202C07844020808B5034B1BB103490348AFF348
+S315080202D0008008BD0000000040040020784402089F
 S315080202E053B94AB9002908BF00281CBF4FF0FF318D
 S315080202F04FF0FF3000F074B9ADF1080C6DE904CE89
 S3150802030000F006F8DDF804E0DDE9022304B07047E0
@@ -95,9 +95,9 @@ S315080205C095E76746D8E781467BE7384645E7ACF1C3
 S315080205D0020C2B4410E702382C4421E73746E8E69A
 S315080205E0704700BF70B50D4E0D4D761BB61006D07E
 S315080205F00024013455F8043B9847A642F9D1094E1E
-S31508020600094D761B03F02EFFB61006D000240134DE
-S3150802061055F8043B9847A642F9D170BD1845020819
-S31508020620184502082045020818450208F0B486074C
+S31508020600094D761B03F038FFB61006D000240134D4
+S3150802061055F8043B9847A642F9D170BD2C45020805
+S315080206202C450208344502082C450208F0B4860710
 S3150802063046D0541E002A3CD0CAB2034602E014F140
 S31508020640FF3436D303F8012B9D07F8D1032C29D999
 S31508020650CDB245EA05250F2C45EA054533D9A4F15D
@@ -112,7 +112,7 @@ S315080206D0024800F005B8704700000000ED0602085F
 S315080206E0002301461A46184600F01EB838B50A4CC9
 S315080206F00A4D641BA4100AD004F18043013B05EBA2
 S315080207008305013C55F804399847002CF9D1BDE810
-S31508020710384003F0ADBE00BF244502082045020852
+S31508020710384003F0B7BE00BF384502083445020820
 S31508020720704700BF704700BF2DE9F0411E4C0546D1
 S31508020730206890461F460E46FFF7F2FF1B4B1A68C3
 S31508020740D2F8483133B35A6820681F2A27DC4DB9D4
@@ -121,1059 +121,1060 @@ S31508020760BDE8F08103EB82010124C1F8888004FA0E
 S3150802077002FED3F88841022D44EA0E0CC3F888C15A
 S31508020780C1F80871E4D1D3F88C114EEA0104C3F812
 S315080207908C41DDE702F5A673C2F84831D3E7FFF7C5
-S315080207A0C1FF4FF0FF30DBE728040020C8440208E7
+S315080207A0C1FF4FF0FF30DBE728040020DC440208D3
 S315080207B0DFF834D0002103E00C4B5B584350043178
 S315080207C00B480C4B42189A42F6D30B4A02E0002316
-S315080207D042F8043B094B9A42F9D303F017FDFFF797
-S315080207E001FF00F0B9F9704700000220244502080B
+S315080207D042F8043B094B9A42F9D300F013F8FFF7A3
+S315080207E001FF03F051FC7047000002203845020859
 S315080207F0000000203C0400203C040020FC050020E8
-S31508020800FEE70000F0B4002401E00134E4B2112C42
-S3150802081020D8124D15F8147005EB440595F801C059
-S3150802082007EB0C0606FB00064FF4FA55B5FBF6F580
-S3150802083006FB05F5B5F5FA5FE7D1B5FBF6F60E80C8
-S31508020840013EB6B2B6F5007FDFD2177083F800C054
-S31508020850012000E00020F0BC704700BFCC4402082B
-S3150802086008B50948094B03604FF461434360002306
-S315080208708360C36003610C2242618361C3610362C0
-S31508020880836201F079FF08BDF804002000480040A1
-S3150802089070B58AB00025ADF826508DF825508DF82A
-S315080208A0245009AB0DF125020DF126014FF4FA7019
-S315080208B0FFF7A8FF1D4C1E4B2360A560E5600126C5
-S315080208C026746574A574BDF826306361A6619DF821
-S315080208D02530E3619DF8243023626662A662E662E9
-S315080208E026636563A663E563256404236364A564D6
-S315080208F0E36426656365A565E56525666566A3669B
-S31508020900204602F0D9FF0195029503960723049320
-S3150802091040F2676305930693079501A9204603F0FB
-S3150802092015F9204603F055F90AB070BD580400209F
-S3150802093000A0004008B5002301220146034801F041
-S315080209404DFE08B1002008BD0120FCE7F80400208E
-S3150802095008B5FFF785FFFFF79BFF08BDBFF34F8F6B
-S315080209600549CA6802F4E062044B1343CB60BFF33D
-S315080209704F8F00BFFDE700BF00ED00E00400FA0557
-S3150802098008B5214B1B78B3B92048FFF7D3FF0128D6
-S3150802099000D008BD1D4B1B78013BDBB23F2BF8D8B4
-S315080209A000F0D2F91A4B1860174B01221A70194B2C
-S315080209B000221A70EDE7174B1B78013313481844C7
-S315080209C0FFF7B8FF012813D1124A13780133DBB2B5
-S315080209D013700E4A12789342DBD10B4A002111702A
-S315080209E00A4A5278FF2AD4D1022BD2D1FFF7B6FF90
-S315080209F000F0AAF9064B1B6864339842C9D9024B20
-S31508020A0000221A70C5E700BFC5050020840500202C
-S31508020A10C8050020C605002000B58DB00021104883
-S31508020A2003F0BEF910B90DB05DF804FB6B4602AAD5
-S31508020A3000210B4803F0E8F80028F4D1029A40F2A4
-S31508020A4067639A42EFD1039B002BECD19DF81620DF
-S31508020A509DF80030FF2BE6D1022AE4D1FFF77EFF8C
-S31508020A605804002008B5FFF78BFFFFF7D5FF08BD2E
-S31508020A70014A024B9A6070470000020800ED00E046
-S31508020A8000B59DB04C22002109A8FFF7CFFD202210
-S31508020A90002101A8FFF7CAFD022002F0F5FD002396
-S31508020AA00093254B9A6942F440429A619B6903F482
-S31508020AB040430093214BDA6A42F00102DA62DB6AAA
-S31508020AC003F001030093009B1B4B9B6913F4005F21
-S31508020AD0FAD0012309934FF4A0230A93022312930F
-S31508020AE01393042214924FF4F071159116931792E8
-S31508020AF01893199200231A931B9309A802F044F833
-S31508020B0000B1FEE73F2301930323029300230393D5
-S31508020B10082304934023059306934FF480620792B1
-S31508020B20089304210DEB010002F01EFC00B1FEE75A
-S31508020B301DB05DF804FB00BF0048025800040058C7
-S31508020B4008B5FFF795FF01F069FFFFF799FF00F077
-S31508020B50E1F800F0AFF808BD08B5FFF7F1FFFFF7B7
-S31508020B60F7FE00F0B1F8FFF77DFFFAE7F0B58DB0B2
-S31508020B704D4BD3F8F42042F00202C3F8F420D3F81E
-S31508020B80F42002F002020192019AD3F8E02042F020
-S31508020B900202C3F8E020D3F8E02002F00202029231
-S31508020BA0029AD3F8E02042F00402C3F8E020D3F810
-S31508020BB0E02002F004020392039AD3F8E02042F0FE
-S31508020BC00802C3F8E020D3F8E02002F008020492F3
-S31508020BD0049AD3F8E82042F48022C3F8E820D3F82E
-S31508020BE0E82002F480220592059AD3F8EC2042F412
-S31508020BF08072C3F8EC20D3F8EC3003F480730693C2
-S31508020C00069B032001F050FF002211466FF00B00ED
-S31508020C1001F05CFF002211466FF00A0001F056FF50
-S31508020C20002211466FF0090001F050FF002211461A
-S31508020C306FF0040001F04AFF002211466FF003002C
-S31508020C4001F044FF002211466FF0010001F03EFF59
-S31508020C50002211464FF0FF3001F038FF8023079338
-S31508020C6001230893002409940A94104D07A92846DB
-S31508020C7001F0B6FD4FF440770797022608960994C5
-S31508020C800A9407230B9307A9094801F0A9FD0797B8
-S31508020C90089609940A9409230B9307A9284601F092
-S31508020CA09FFD0DB0F0BD00BF004402580004025873
-S31508020CB0000C025808B500228021024801F080FE85
-S31508020CC008BD00BF0004025810B500F03DF80E4BEF
-S31508020CD01B68C31AB3F5FA7F0CD304460B4B1B7871
-S31508020CE04BB90122094B1A708021094801F068FEA6
-S31508020CF0054B1C6010BD0022044B1A708021044863
-S31508020D0001F05EFEF4E700BFD0050020CC05002006
-S31508020D100004025808B503F0B7FA094B1868094BDC
-S31508020D20A3FB0030800901F003FF042001F016FF3F
-S31508020D30002211464FF0FF3001F0C8FE08BD00BF81
-S31508020D4034040020D34D621008B501F0A1FE08BD97
-S31508020D5008B501F091FE01F012FF08BD70470000C8
-S31508020D602DE9F04387B00446016883680269134394
-S31508020D7042691343C2691343426E13430868874A9A
-S31508020D8002401A430A602268536823F44053E16812
-S31508020D900B435360A1692268814B9A4201D0236AA8
-S31508020DA0194390687F4B03400B4393602268D36ACA
-S31508020DB023F00F03616A0B43D36223687A4A93428C
-S31508020DC01FD07A4A934259D0794A934270D0794AC7
-S31508020DD0934200F08780784A934200F09D80774AD2
-S31508020DE0934200F0B380764A934200F0F180754A46
-S31508020DF0934200F004816A4A934200F017818025E3
-S31508020E002DE1714A526D02F03802282A34D8DFE8F9
-S31508020E1012F0290033003300330033003300330065
-S31508020E203300250133003300330033003300330027
-S31508020E3033002B0033003300330033003300330012
-S31508020E4033002D0033003300330033003300330000
-S31508020E5033002F00330033003300330033003300EE
-S31508020E60330031000125FAE00825F8E01025F6E0FE
-S31508020E702025F4E04025F2E08025F0E0524A526D42
-S31508020E8002F00702052A11D8DFE812F00600370138
-S31508020E9008000A000C000E000025E0E00825DEE046
-S31508020EA01025DCE02025DAE04025D8E08025D6E0CA
-S31508020EB0454A526D02F00702052A11D8DFE812F0F8
-S31508020EC006001F0108000A000C000E000025C6E0F5
-S31508020ED00825C4E01025C2E02025C0E04025BEE072
-S31508020EE08025BCE0384A526D02F00702052A11D85D
-S31508020EF0DFE812F00600070108000A000C000E00DF
-S31508020F000025ACE00825AAE01025A8E02025A6E0E1
-S31508020F104025A4E08025A2E02B4A526D02F0070282
-S31508020F20052A11D8DFE812F00600EF0008000A00C9
-S31508020F300C000E00002592E0082590E010258EE0B0
-S31508020F4020258CE040258AE0802588E01E4A526DDD
-S31508020F5002F03802282A39D8DFE802F0153838387C
-S31508020F6038383838D7383838383838381738383873
-S31508020F703838383819383838383838381B3838381D
-S31508020F80383838381D00012569E0082567E010253C
-S31508020F9065E0202563E0402561E000BFF369FFCFE5
-S31508020FA0000C0058FFF4FF110010014000440040F5
-S31508020FB000480040004C0040005000400014014028
-S31508020FC000780040007C004000440258802546E034
-S31508020FD0A04A526D02F00702052A0ED8DFE802F08F
-S31508020FE003970507090B002539E0082537E0102580
-S31508020FF035E0202533E0402531E080252FE0954A6B
-S31508021000526D02F00702052A0ED8DFE802F00382C3
-S315080210100507090B002522E0082520E010251EE019
-S3150802102020251CE040251AE0802518E002F50E323C
-S31508021030926D02F00702052A0ED8DFE802F0036C69
-S315080210400507090B02250AE0082508E0102506E02F
-S31508021050202504E0402502E0802500E004257E4A9A
-S3150802106093425AD0E369B3F5004F00F03E85402D0E
-S3150802107001F2CB81DFE815F093070A08C909C90905
-S315080210804808C909C909C9098808C909C909C90984
-S31508021090C909C909C909C909C808C909C909C909B2
-S315080210A0C909C909C909C909C909C909C909C909A0
-S315080210B0C909C909C909C9094809C909C909C90911
-S315080210C0C909C909C909C909C909C909C909C90980
-S315080210D0C909C909C909C909C909C909C909C90970
-S315080210E0C909C909C909C909C909C909C909C90960
-S315080210F0C909C909C909C90984090425AFE7042523
-S31508021100ADE70425ABE70425A9E70425A7E70425E7
-S31508021110A5E70425A3E70425A1E7082D00F0BD806D
-S315080211200BD9202D00F04F81402D00F06A81102D39
-S3150802113000F0EC80012000F064BF022D2ED0042DB1
-S3150802114029D103A802F066FE0498636A002B00F010
-S315080211508C80012B00F08D80022B00F08C80032BF3
-S3150802116000F08B80042B00F08A80052B00F0898022
-S31508021170062B00F08880072B00F08780082B00F0EA
-S315080211808680092B00F085800A2B00F084800B2BC1
-S3150802119068D001236AE0012000F033BF02F028FE7E
-S315080211A0636AD3B1012B42D0022B42D0032B42D021
-S315080211B0042B42D0052B42D0062B42D0072B42D015
-S315080211C0082B42D0092B42D00A2B49D00B2B01D02F
-S315080211D0012303E04FF4807300E00123B0FBF3F030
-S315080211E0002801F01581666806EB4603834201F280
-S315080211F01181B0EB063F01F20F81082D00F05482EF
-S3150802120040F26C81202D00F06F83402D00F0D183CF
-S31508021210102D00F0A28201200023A3F540710F4A87
-S31508021220914201F2FB802268D36000F0EABE0223F3
-S31508021230D4E70423D2E70623D0E70823CEE70A2316
-S31508021240CCE70C23CAE71023C8E72023C6E74023C6
-S31508021250C4E700BF00440258000C0058FFFC0F0008
-S315080212608023BBE74FF4807300E00123B0FBF3F061
-S31508021270B6E70223FAE70423F8E70623F6E7082384
-S31508021280F4E70A23F2E70C23F0E71023EEE720231C
-S31508021290ECE74023EAE78023E8E7684602F0B8FE6F
-S315080212A00198636AD3B1012B1CD0022B1CD0032BE5
-S315080212B01CD0042B1CD0052B1CD0062B1CD0072BAC
-S315080212C01CD0082B1CD0092B1CD00A2B1CD00B2B8C
-S315080212D001D0012303E04FF4807300E00123B0FB41
-S315080212E0F3F07DE70223FAE70423F8E70623F6E795
-S315080212F00823F4E70A23F2E70C23F0E71023EEE7C4
-S315080213002023ECE74023EAE78023E8E7A94B1B689A
-S3150802131013F0200F3AD0A74B1B68C3F3C103A648A4
-S31508021320D840636AD3B1012B1CD0022B1CD0032BE5
-S315080213301CD0042B1CD0052B1CD0062B1CD0072B2B
-S315080213401CD0082B1CD0092B1CD00A2B1CD00B2B0B
-S3150802135001D0012303E04FF4807300E00123B0FBC0
-S31508021360F3F03DE70223FAE70423F8E70623F6E754
-S315080213700823F4E70A23F2E70C23F0E71023EEE743
-S315080213802023ECE74023EAE78023E8E7636A002B99
-S3150802139055D0012B55D0022B55D0032B55D0042BF3
-S315080213A055D0052B55D0062B55D0072B55D0082BD3
-S315080213B055D0092B55D00A2B55D00B2B01D07E4878
-S315080213C00EE77E480CE7636A002B4ED0012B4ED0FF
-S315080213D0022B4ED0032B4ED0042B4ED0052B4ED0CB
-S315080213E0062B4ED0072B4ED0082B4ED0092B4ED0AB
-S315080213F00A2B4FD00B2B01D07148F1E643F6095060
-S31508021400EEE6636A002B48D0012B49D0022B4AD05C
-S31508021410032B4BD0042B4CD0052B4DD0062B4ED08C
-S31508021420072B4FD0082B50D0092B51D00A2B52D05C
-S315080214300B2B02D04FF40040D2E68020D0E65E485D
-S31508021440CEE66048CCE66048CAE66048C8E6604828
-S31508021450C6E66048C4E66048C2E65948C0E65F4840
-S31508021460BEE65F48BCE65F48BAE65548B8E65B485A
-S31508021470B6E65B48B4E65C48B2E65A48B0E65B486C
-S31508021480AEE65B48ACE64D48AAE65A48A8E64FF2ED
-S315080214902440A5E647F61220A2E64FF400409FE64E
-S315080214A04FF480409CE64FF4005099E641F25550BD
-S315080214B096E64FF4805093E640F6CC4090E640F626
-S315080214C0AA208DE64FF400608AE64FF4806087E62C
-S315080214D04FF4007084E64FF4807081E6022D2FD017
-S315080214E0042D2AD103A802F095FC0498636A002BFE
-S315080214F000F0A480012B00F0B980022B00F0B9801D
-S31508021500032B00F0B980042B00F0B980052B00F0FC
-S31508021510B980062B00F0B980072B00F0B980082B9A
-S3150802152000F0B980092B00F0B9800A2B00F0B980C7
-S315080215300B2B7FD00122002382E0012000236CE6D8
-S3150802154002F056FC636AE3B1012B55D0022B56D042
-S31508021550032B57D0042B58D0052B59D0062B5AD01B
-S31508021560072B5BD0082B5CD0092B5DD00A2B5ED0EB
-S315080215700B2B02D00122002305E04FF480720023D0
-S3150802158001E0012200230021FEF7AAFE0F0247EA24
-S31508021590106706026268500800252B4616EB0008FB
-S315080215A047F1000940464946FEF79AFE0346284691
-S315080215B033E600BF004402580090D00390D00300DF
-S315080215C000093D000048E8010024F400AAC2A2006E
-S315080215D000127A0000A861005561510080841E003D
-S315080215E040420F0020A107002A2C0A00801A060092
-S315080215F01516050048E8010002220023C3E7042263
-S315080216000023C0E706220023BDE708220023BAE723
-S315080216100A220023B7E70C220023B4E7102200238C
-S31508021620B1E720220023AEE740220023ABE780225F
-S315080216300023A8E74FF48072002301E00122002369
-S315080216400021FEF74DFE0F0247EA1067060262689E
-S31508021650500800252B4616EB000847F100094046BC
-S315080216604946FEF73DFE03462846D6E502220023F2
-S31508021670E6E704220023E3E706220023E0E708223E
-S315080216800023DDE70A220023DAE70C220023D7E744
-S3150802169010220023D4E720220023D1E74022002388
-S315080216A0CEE780220023CBE7684602F0B1FC019818
-S315080216B0636AE3B1012B32D0022B33D0032B34D029
-S315080216C0042B35D0052B36D0062B37D0072B38D02E
-S315080216D0082B39D0092B3AD00A2B3BD00B2B02D038
-S315080216E00122002305E04FF48072002301E0012263
-S315080216F000230021FEF7F4FD0F0247EA10670602EF
-S315080217006268500800252B4616EB000847F10009C7
-S3150802171040464946FEF7E4FD034628467DE5022291
-S315080217200023E6E704220023E3E706220023E0E794
-S3150802173008220023DDE70A220023DAE70C22002327
-S31508021740D7E710220023D4E720220023D1E740223C
-S315080217500023CEE780220023CBE7C54B1B6813F094
-S31508021760200F5CD0C24B1B68C3F3C103C148D840E3
-S31508021770636AE3B1012B34D0022B35D0032B36D062
-S31508021780042B37D0052B38D0062B39D0072B3AD065
-S31508021790082B3BD0092B3CD00A2B3DD00B2B02D071
-S315080217A00122002305E04FF48072002301E00122A2
-S315080217B000230021FEF794FD4FEA012949EA106940
-S315080217C04FEA00287008002532462B4618EB000619
-S315080217D049F1000730463946FEF782FD0346284698
-S315080217E01BE502220023E4E704220023E1E706229E
-S315080217F00023DEE708220023DBE70A220023D8E7D4
-S315080218000C220023D5E710220023D2E72022002348
-S31508021810CFE740220023CCE780220023C9E7636A88
-S31508021820FBB1012B2ED0022B31D0032B34D0042B43
-S3150802183037D0052B3AD0062B3DD0072B40D0082BA4
-S3150802184043D0092B46D00A2B49D00B2B04D0DFF8FC
-S3150802185028824FF0030908E0DFF818824FF00009E2
-S3150802186003E0DFF814824FF00309770800253246B1
-S315080218702B4618EB070049F10001FEF731FD034636
-S315080218802846CAE4DFF8F4814FF00109EDE7DFF8EC
-S31508021890F0814FF00009E8E70FF2B419D9E9008997
-S315080218A0E3E7DFF8E0814FF00009DEE7DFF8D881E9
-S315080218B04FF00009D9E70FF2A019D9E90089D4E750
-S315080218C0DFF8C8814FF00009CFE7DFF8C4814FF08F
-S315080218D00009CAE7DFF8BC814FF00009C5E7DFF85F
-S315080218E0B8814FF00009C0E7636AFBB1012B2ED01D
-S315080218F0022B31D0032B34D0042B37D0052B3AD008
-S31508021900062B3DD0072B40D0082B43D0092B46D0B7
-S315080219100A2B49D00B2B04D0DFF870814FF000094F
-S3150802192008E0DFF878814FF0000903E0DFF85C8110
-S315080219304FF000097708002532462B4618EB0700B8
-S3150802194049F10001FEF7CCFC0346284665E4DFF8B8
-S3150802195040814FF00009EDE7DFF838814FF00009C2
-S31508021960E8E70FF2FC09D9E90089E3E7DFF82881FD
-S315080219704FF00009DEE7DFF828814FF00009D9E7C2
-S315080219800FF2E409D9E90089D4E7DFF8E8804FF0D5
-S315080219900009CFE7DFF80C814FF00009CAE7DFF844
-S315080219A008814FF00009C5E7DFF800814FF000090A
-S315080219B0C0E7636A03B3012B30D0022B33D0032B63
-S315080219C036D0042B39D0052B3CD0062B74D0072BE6
-S315080219D077D0082B7AD0092B7DD00A2B00F080808D
-S315080219E00B2B04D04FF400084FF0000908E04FF41F
-S315080219F000484FF0000903E04FF400084FF00009D1
-S31508021A007708002532462B4618EB070049F10001F4
-S31508021A10FEF766FC03462846FFF7FFBB4FF480082D
-S31508021A204FF00009ECE74FF400184FF00009E7E71A
-S31508021A30DFF87C804FF00009E2E74FF480184FF098
-S31508021A400009DDE7DFF86C804FF00009D8E700BF30
-S31508021A5000AAC2A200000000005561510000000061
-S31508021A60002A2C0A000000000015160500000000D6
-S31508021A70004402580090D003000090D0000048E8C5
-S31508021A80000024F40000127A0000A8610000093D53
-S31508021A900080841E0040420F0020A10700093D0075
-S31508021AA000801A060048E8010024F40000127A00B1
-S31508021AB00055150000CC0C00DFF8B0854FF0000980
-S31508021AC09EE74FF400284FF0000999E74FF4802863
-S31508021AD04FF0000994E74FF400384FF000098FE7FA
-S31508021AE04FF480384FF000098AE7402D00F25482FD
-S31508021AF0DFE815F041008F0052025202CE00520270
-S31508021B00520252020F015202520252025202520269
-S31508021B105202520250015202520252025202520218
-S31508021B205202520252025202520252025202520205
-S31508021B3052025202D1015202520252025202520277
-S31508021B4052025202520252025202520252025202E5
-S31508021B5052025202520252025202520252025202D5
-S31508021B6052025202520252025202520252025202C5
-S31508021B70520252020C0201F063FD636AD3B1012BD1
-S31508021B8033D0022B33D0032B33D0042B33D0052B7F
-S31508021B9033D0062B33D0072B33D0082B33D0092B5F
-S31508021BA033D00A2B33D00B2B01D0012303E04FF499
-S31508021BB0807300E00123B0FBF3F06268530803EB7D
-S31508021BC04003B3FBF2F39BB20020A3F110014FF6D8
-S31508021BD0EF72914200F224849AB222F00F02C3F302
-S31508021BE0420313432268D3600BE20223E3E704238A
-S31508021BF0E1E70623DFE70823DDE70A23DBE70C2311
-S31508021C00D9E71023D7E72023D5E74023D3E7802354
-S31508021C10D1E701F027FD636AD3B1012B24D0022B49
-S31508021C2024D0032B24D0042B24D0052B24D0062B16
-S31508021C3024D0072B24D0082B24D0092B24D00A2BF6
-S31508021C4024D00B2B01D0012303E04FF4807300E06C
-S31508021C500123B0FBF3F06268530803EB4003B3FBBE
-S31508021C60F2F39BB20020B0E70223F2E70423F0E77F
-S31508021C700623EEE70823ECE70A23EAE70C23E8E75C
-S31508021C801023E6E72023E4E74023E2E78023E0E7A0
-S31508021C9003A802F0BFF8049B626AD2B1012A24D0D3
-S31508021CA0022A24D0032A24D0042A24D0052A24D09E
-S31508021CB0062A24D0072A24D0082A24D0092A24D07E
-S31508021CC00A2A24D00B2A01D0012203E04FF480729B
-S31508021CD000E00122B3FBF2F261684B0803EB420310
-S31508021CE0B3FBF1F39BB200206FE70222F2E704226C
-S31508021CF0F0E70622EEE70822ECE70A22EAE70C22D8
-S31508021D00E8E71022E6E72022E4E74022E2E780221B
-S31508021D10E0E7684602F07CF9019B626AD2B1012AC1
-S31508021D2024D0022A24D0032A24D0042A24D0052A1D
-S31508021D3024D0062A24D0072A24D0082A24D0092AFD
-S31508021D4024D00A2A24D00B2A01D0012203E04FF418
-S31508021D50807200E00122B3FBF2F261684B0803EBE2
-S31508021D604203B3FBF1F39BB200202EE70222F2E70D
-S31508021D700422F0E70622EEE70822ECE70A22EAE75F
-S31508021D800C22E8E71022E6E72022E4E74022E2E70F
-S31508021D908022E0E7A34B1B6813F0200F42D0A14B29
-S31508021DA01A68C2F3C102A04BD340626AD2B1012AB1
-S31508021DB024D0022A24D0032A24D0042A24D0052A8D
-S31508021DC024D0062A24D0072A24D0082A24D0092A6D
-S31508021DD024D00A2A24D00B2A01D0012203E04FF488
-S31508021DE0807200E00122B3FBF2F261684B0803EB52
-S31508021DF04203B3FBF1F39BB20020E6E60222F2E7C6
-S31508021E000422F0E70622EEE70822ECE70A22EAE7CE
-S31508021E100C22E8E71022E6E72022E4E74022E2E77E
-S31508021E208022E0E7636ACBB1012B20D0022B20D0B7
-S31508021E30032B20D0042B20D0052B20D0062B20D014
-S31508021E40072B20D0082B20D0092B20D00A2B20D0F4
-S31508021E500B2B01D0754B02E0754B00E0734B6268A1
-S31508021E6003EB5203B3FBF2F39BB20020ADE66E4BD3
-S31508021E70F5E7704BF3E7704BF1E7704BEFE7704B02
-S31508021E80EDE7704BEBE7704BE9E7704BE7E7704B12
-S31508021E90E5E7704BE3E7636AD3B1012B21D0022B46
-S31508021EA021D0032B21D0042B21D0052B21D0062BA0
-S31508021EB021D0072B21D0082B21D0092B21D00A2B80
-S31508021EC021D00B2B01D0604B03E047F6122300E02A
-S31508021ED05D4B626803EB5203B3FBF2F39BB200203D
-S31508021EE073E65A4BF5E75A4BF3E75B4BF1E7594B67
-S31508021EF0EFE75A4BEDE75A4BEBE74D4BE9E7594B00
-S31508021F00E7E7594BE5E74FF22443E2E7636ADBB1B9
-S31508021F10012B23D0022B24D0032B25D0042B26D029
-S31508021F20052B27D0062B28D0072B29D0082B2AD0F9
-S31508021F30092B2BD00A2B2CD00B2B02D04FF4803333
-S31508021F4004E04FF4807301E04FF48033626803EBD8
-S31508021F505203B3FBF2F39BB2002036E64FF400437A
-S31508021F60F4E74FF48043F1E742F6AA23EEE74FF48B
-S31508021F700053EBE741F69813E8E741F25453E5E7D5
-S31508021F804FF48053E2E74FF40063DFE74FF48063D0
-S31508021F90DCE74FF40073D9E70120002315E601F0C8
-S31508021FA04FFB636AD3B1012B36D0022B36D0032BF3
-S31508021FB036D0042B5CD0052B5CD0062B5CD0072BC5
-S31508021FC05CD0082B5CD0092B5CD00A2B5CD00B2B7F
-S31508021FD001D0012303E04FF4807300E00123B0FB34
-S31508021FE0F3F3626803EB5203B3FBF2F39BB20020EE
-S31508021FF0A3F110014FF6EF72914200F213822268A2
-S31508022000D3600123A4F86A30A4F868300023E36693
-S31508022010236707B0BDE8F0830223E0E70423DEE77F
-S315080220200623DCE7004402580090D0030020A107EB
-S3150802203020A107000048E801548545010024F40060
-S315080220400050C300AAC2A20000127A0000093D008D
-S3150802205080841E0040420F005458140000350C00BC
-S315080220602A2C0A0090D0030048E8010000AA0A00B8
-S315080220700823B4E70A23B2E70C23B0E71023AEE736
-S315080220802023ACE74023AAE78023A8E701F0EAFA6F
-S31508022090636AD3B1012B23D0022B23D0032B23D07F
-S315080220A0042B23D0052B23D0062B23D0072B23D092
-S315080220B0082B23D0092B23D00A2B23D00B2B01D094
-S315080220C0012303E04FF4807300E00123B0FBF3F32E
-S315080220D0626803EB5203B3FBF2F39BB2002087E775
-S315080220E00223F3E70423F1E70623EFE70823EDE7E4
-S315080220F00A23EBE70C23E9E71023E7E72023E5E7C2
-S315080221004023E3E78023E1E703A801F083FE049B6B
-S31508022110626AD2B1012A23D0022A23D0032A23D003
-S31508022120042A23D0052A23D0062A23D0072A23D015
-S31508022130082A23D0092A23D00A2A23D00B2A01D017
-S31508022140012203E04FF4807200E00122B3FBF2F3AE
-S31508022150626803EB5203B3FBF2F39BB2002047E734
-S315080221600222F3E70422F1E70622EFE70822EDE767
-S315080221700A22EBE70C22E9E71022E7E72022E5E745
-S315080221804022E3E78022E1E7684601F041FF019B2E
-S31508022190626AD2B1012A23D0022A23D0032A23D083
-S315080221A0042A23D0052A23D0062A23D0072A23D095
-S315080221B0082A23D0092A23D00A2A23D00B2A01D097
-S315080221C0012203E04FF4807200E00122B3FBF2F32E
-S315080221D0626803EB5203B3FBF2F39BB2002007E7F4
-S315080221E00222F3E70422F1E70622EFE70822EDE7E7
-S315080221F00A22EBE70C22E9E71022E7E72022E5E7C5
-S315080222004022E3E78022E1E7874B1B6813F0200FA1
-S3150802221041D0854B1A68C2F3C102844BD340626A25
-S31508022220D2B1012A23D0022A23D0032A23D0042A90
-S3150802223023D0052A23D0062A23D0072A23D0082A00
-S3150802224023D0092A23D00A2A23D00B2A01D0012215
-S3150802225003E04FF4807200E00122B3FBF2F36268F6
-S3150802226003EB5203B3FBF2F39BB20020C0E6022251
-S31508022270F3E70422F1E70622EFE70822EDE70A224E
-S31508022280EBE70C22E9E71022E7E72022E5E74022FE
-S31508022290E3E78022E1E7636ACBB1012B20D0022B68
-S315080222A020D0032B20D0042B20D0052B20D0062BA0
-S315080222B020D0072B20D0082B20D0092B20D00A2B80
-S315080222C020D00B2B01D0594B02E0594B00E0574B5B
-S315080222D0626803EB5203B3FBF2F39BB2002087E674
-S315080222E0544BF5E7544BF3E7544BF1E7544BEFE7FE
-S315080222F0544BEDE7544BEBE7544BE9E7544BE7E70E
-S31508022300544BE5E7544BE3E7636AD3B1012B21D07B
-S31508022310022B21D0032B21D0042B21D0052B21D02F
-S31508022320062B21D0072B21D0082B21D0092B21D00F
-S315080223300A2B22D00B2B01D0444B03E043F6095358
-S3150802234000E0424B626803EB5203B3FBF2F39BB223
-S3150802235000204DE63E4BF5E73E4BF3E73F4BF1E7F0
-S315080223603D4BEFE73E4BEDE73E4BEBE7304BE9E7FC
-S315080223703D4BE7E74FF22443E4E747F61223E1E74A
-S31508022380636AD3B1012B22D0022B23D0032B24D08C
-S31508022390042B25D0052B26D0062B27D0072B28D091
-S315080223A0082B29D0092B2AD00A2B2BD00B2B02D08B
-S315080223B04FF4004303E0802301E04FF400436268D0
-S315080223C003EB5203B3FBF2F39BB2002010E64FF481
-S315080223D08043F4E74FF40053F1E741F25553EEE731
-S315080223E04FF48053EBE740F6CC43E8E740F6AA23DE
-S315080223F0E5E74FF40063E2E74FF48063DFE74FF463
-S315080224000073DCE74FF48073D9E701200023EFE578
-S315080224100020F6E50120F4E50120F2E50120F0E5C9
-S315080224200120EEE50120ECE5004402580090D003B5
-S3150802243090D003000048E8010024F400AAC2A200D2
-S3150802244000127A0000A861005561510000093D009A
-S3150802245080841E0040420F0020A107002A2C0A0091
-S31508022460801A06001516050048E80100836A13F06B
-S31508022470010F06D00268536823F40033C16A0B437E
-S315080224805360836A13F0020F06D00268536823F476
-S315080224908033016B0B435360836A13F0040F06D033
-S315080224A00268536823F48023416B0B435360836AA3
-S315080224B013F0080F06D00268536823F40043816BB1
-S315080224C00B435360836A13F0100F06D002689368B1
-S315080224D023F48053C16B0B439360836A13F0200F76
-S315080224E006D00268936823F40053016C0B43936089
-S315080224F0836A13F0400F0AD00268536823F48013E4
-S31508022500416C0B435360436CB3F5801F0BD0836A4F
-S3150802251013F0800F06D00268536823F40023C16CB7
-S315080225200B43536070470268536823F4C003816CF7
-S315080225300B435360EBE72DE9F04104460F46164676
-S315080225409846069D2368DB6937EA03030CBF012315
-S315080225500023B3423FD1B5F1FF3FF3D000F098FA1A
-S31508022560A0EB0800A84222D80DB323681A6812F015
-S31508022570040FE7D0DA6912F4006FE3D04FF4006271
-S315080225801A622268136823F4D07313602268936868
-S3150802259023F0010393602023C4F88030C4F8843002
-S315080225A0C4F88830002384F87C30032014E02268BB
-S315080225B0136823F4D07313602268936823F0010327
-S315080225C093602023C4F88030C4F88430002384F84A
-S315080225D07C30032000E00020BDE8F0812DE9F043BD
-S315080225E083B01E46D0F88430202B40F08280044601
-S315080225F00D469046B2FA82F35B09002908BF012309
-S31508022600002B7AD190F87C30012B78D0012380F800
-S315080226107C300023C0F888302223C0F8843000F0CA
-S3150802262037FA0746A4F85C80A4F85E80A368B3F577
-S31508022630805F06D0A3B9226972B9FF22A4F8602086
-S3150802264014E0226922B940F2FF12A4F860200DE0D4
-S31508022650FF22A4F8602009E07F22A4F8602005E0A2
-S31508022660B3F1805F0AD00022A4F86020B4F8608033
-S31508022670B3F5805F0CD04FF000091DE022691AB944
-S315080226807F22A4F86020F1E73F22A4F86020EDE754
-S31508022690236913B14FF000090EE0A94600250BE0A5
-S315080226A023685B6A08EA030329F8023BB4F85E303A
-S315080226B0013B9BB2A4F85E30B4F85E309BB28BB194
-S315080226C000963B46002220212046FFF734FFC0B978
-S315080226D0002DE5D023685A6A5FFA88F3134005F895
-S315080226E0013BE3E72023C4F88430002084F87C0009
-S315080226F000E0022003B0BDE8F0830120FAE70220D9
-S31508022700F8E70320F6E730B583B004460023C0F89D
-S31508022710883000F0BDF9054623681B6813F0080FD8
-S315080227200ED123681B6813F0040F17D12023C4F8AF
-S315080227308030C4F88430002084F87C0003B030BDB1
-S315080227406FF07E430093034600224FF400112046A1
-S31508022750FFF7F1FE0028E4D00320EFE76FF07E438F
-S3150802276000932B4600224FF480012046FFF7E3FE32
-S315080227700028DBD00320E1E778B310B50446D0F889
-S3150802278080300BB32423C4F880302268136823F000
-S31508022790010313602046FEF7E3FA012813D0A36A61
-S315080227A0BBB92268536823F490435360226893683E
-S315080227B023F02A0393602268136843F00103136027
-S315080227C02046FFF7A0FF10BD80F87C30FEF7C6FA58
-S315080227D0D8E72046FFF74AFEE3E7012070470000E4
-S315080227E0F0B583B000233AE0092400E00024B4409F
-S315080227F03C4302356E4E46F825406E4C2568D44356
-S3150802280004EA05064F6817F4803F01D042EA050636
-S31508022810684D2E606E6804EA06054F6817F4003F95
-S3150802282001D042EA0605634E75604FF0B0452D6841
-S3150802283004EA05064F6817F4801F01D042EA050626
-S315080228404FF0B0452E606D682C404E6816F4001F96
-S3150802285001D042EA05044FF0B042546001330A68D7
-S3150802286032FA03F400F0A28001249C402240F5D0FB
-S315080228704D686E1E112D18BF012E01D9122D12D1C7
-S3150802288086685F000325BD4026EA0506CD68BD4079
-S3150802289035438560466826EA04064D68C5F3001482
-S315080228A09C4034434460C6685F000325BD40EC4340
-S315080228B026408D68BD403543C5604D68122D18BF48
-S315080228C0022D13D1DE08083650F826E003F0070574
-S315080228D04FEA850C0F2505FA0CF52EEA050E0D6949
-S315080228E005FA0CF545EA0E0540F826500568254016
-S315080228F04C6804F00304BC402C4304604C6814F092
-S31508022900805FABD02C4CD4F8F45045F00205C4F8DD
-S31508022910F450D4F8F44004F002040194019C9D0892
-S31508022920AE1C234C54F8267003F00304A6000F24A9
-S31508022930B44027EA0407214CA0423FF457AF04F5F6
-S315080229408064A04222D004F58064A04220D004F517
-S315080229508064A0421ED004F58064A0421CD004F50F
-S315080229608064A0421AD004F58064A04218D004F507
-S315080229708064A04216D004F58064A04214D004F5FF
-S315080229808064A0423FF430AF0A2430E701242EE7E0
-S3150802299002242CE703242AE7042428E7052426E749
-S315080229A0062424E7072422E7082420E703B0F0BD1B
-S315080229B000040058800000580044025800000258DB
-S315080229C00AB181617047090481617047104B1B780F
-S315080229D00BB90120704710B504464FF47A70B0FB64
-S315080229E0F3F30C4A1068B0FBF3F000F0A1F868B9EB
-S315080229F00F2C01D901200AE0002221464FF0FF30B0
-S31508022A0000F064F8044B1C60002000E0012010BDB1
-S31508022A102C040020340400203004002010B50320C2
-S31508022A2000F042F800F0AAFB0F498B69C3F30323AF
-S31508022A300E4AD35C03F01F03D8408B6903F00F03D9
-S31508022A40D35C03F01F0320FA03F3094A1360094B08
-S31508022A5018600020FFF7BAFF10B10124204610BD06
-S31508022A600446FEF783F8F9E70044025800450208CF
-S31508022A703804002034040020034B1B78034A1168EB
-S31508022A800B441360704700BF2C040020F805002091
-S31508022A90014B1868704700BFF8050020014B1868FB
-S31508022AA0000C70470010005C0649CB6823F4E0630B
-S31508022AB01B041B0C000200F4E0600343024A1A439B
-S31508022AC0CA60704700ED00E00000FA0530B4154B05
-S31508022AD0DB68C3F30223C3F10704042C28BF0424CA
-S31508022AE01D1D062D01D9033B00E000234FF0FF35DB
-S31508022AF005FA04F421EA0401994005FA03F322EAE5
-S31508022B0003031943002805DB0901C9B2064B195408
-S31508022B1030BC704700F00F000901C9B2034B1954C3
-S31508022B20F6E700BF00ED00E000E400E014ED00E087
-S31508022B300138B0F1807F0AD2064B5860064AF02166
-S31508022B4082F823100020986007221A607047012035
-S31508022B50704700BF10E000E000ED00E0042805D051
-S31508022B60054A136823F0040313607047024A136880
-S31508022B7043F004031360704710E000E0704708B59D
-S31508022B80FFF7FCFF08BD0000002800F0DC8238B51C
-S31508022B900446036813F0010F25D0A94A136903F006
-S31508022BA03803926A102B15D0182B0FD06368B3F529
-S31508022BB0803F3ED0002B52D1A14B1A6822F48032B4
-S31508022BC01A601A6822F480221A6037E002F00302B9
-S31508022BD0022AEBD19A4B1B6813F4003F03D06368B1
-S31508022BE0002B00F0B282236813F0020F77D0944AC2
-S31508022BF01369926A13F038035AD0182B55D0E36832
-S31508022C00002B00F0B2808E490A6822F0190213439B
-S31508022C100B60FFF73DFF0546894B1B6813F0040F4F
-S31508022C2040F08B80FFF734FF401B0228F4D90320BB
-S31508022C3092E2834A136843F48033136063682BB3C2
-S31508022C40FFF726FF05467E4B1B6813F4003FCAD1E1
-S31508022C50FFF71EFF401B6428F5D903207CE2B3F573
-S31508022C60A02F09D0764B1A6822F480321A601A68A5
-S31508022C7022F480221A60E1E7714B1A6842F4802234
-S31508022C801A601A6842F480321A60D7E7FFF700FF23
-S31508022C9005466B4B1B6813F4003FA4D0FFF7F8FEFA
-S31508022CA0401B6428F5D9032056E212F0030FA6D179
-S31508022CB0634B1B6813F0040F03D0E368002B00F084
-S31508022CC04682FFF7EBFE41F2030398422CD85C4A90
-S31508022CD0536823F47C33216943EA0133536023683A
-S31508022CE013F0100F70D0564A136903F03803926A2C
-S31508022CF0082B52D0182B4CD0E369002B00F0A28087
-S31508022D004F4A136843F080031360FFF7C1FE054676
-S31508022D104B4B1B6813F4807F7AD1FFF7B9FE401B31
-S31508022D200228F5D9032017E2454A536823F0FE43E1
-S31508022D30216943EA01635360D1E7FFF7AFFE41F227
-S31508022D400303984208D83E4A536823F47C33216920
-S31508022D5043EA01335360C2E7394A536823F0FE4314
-S31508022D60216943EA01635360B9E7354A136823F0D8
-S31508022D7001031360FFF78CFE0546314B1B6813F0FF
-S31508022D80040FACD0FFF784FE401B0228F5D90320B6
-S31508022D90E2E102F00302012AAED1294B1B6813F4C1
-S31508022DA0807F03D0E369802B40F0D381FFF776FE5C
-S31508022DB041F20303984222D8214A536823F0F84382
-S31508022DC0216A43EA81635360236813F0080F61D0CE
-S31508022DD06369002B4AD01A4A536F43F001035367BB
-S31508022DE0FFF756FE0546164B5B6F13F0020F51D1DD
-S31508022DF0FFF74EFE401B0228F5D90320ACE1104A24
-S31508022E00D36823F07C53216A43EA0163D360DBE784
-S31508022E10FFF744FE41F20303984208D8084A53686A
-S31508022E2023F0F843216A43EA81635360CCE7044AF4
-S31508022E30D36823F07C53216A43EA0163D360C3E76C
-S31508022E4000440258A74A136823F080031360FFF769
-S31508022E501FFE0546A34B1B6813F4807FB4D0FFF709
-S31508022E6017FE401B0228F5D9032075E19D4A536FC8
-S31508022E7023F001035367FFF70BFE0546994B5B6F79
-S31508022E8013F0020F06D0FFF703FE401B0228F5D9FE
-S31508022E90032061E1236813F0200F29D0A3699BB1AF
-S31508022EA0904A136843F480531360FFF7F1FD054611
-S31508022EB08C4B1B6813F4005F1AD1FFF7E9FD401B20
-S31508022EC00228F5D9032047E1864A136823F480537A
-S31508022ED01360FFF7DDFD0546824B1B6813F4005F9E
-S31508022EE006D0FFF7D5FD401B0228F5D9032033E1AA
-S31508022EF0236813F0040F21D1636A002B00F02B819B
-S31508022F00784A126902F03802182A00F0F380022B76
-S31508022F1075D0744A136823F080731360FFF7B8FDFF
-S31508022F200446704B1B6813F0007F00F0D880FFF749
-S31508022F30AFFD001B0228F4D903200DE16A4A136883
-S31508022F4043F480731360FFF7A3FD0546664B1B68BF
-S31508022F5013F4807F06D1FFF79BFD401B6428F5D941
-S31508022F600320F9E0A368012B0AD00BBB5D4B1A6F4D
-S31508022F7022F001021A671A6F22F004021A6704E0A5
-S31508022F80584A136F43F001031367A36833B3FFF775
-S31508022F907FFD0546534B1B6F13F0020FACD1FFF7AB
-S31508022FA077FD401B41F288339842F3D90320D3E0D8
-S31508022FB0052B09D04B4B1A6F22F001021A671A6FBA
-S31508022FC022F004021A67E0E7464B1A6F42F004023F
-S31508022FD01A671A6F42F001021A67D6E7FFF758FD19
-S31508022FE00546404B1B6F13F0020F85D0FFF750FDC5
-S31508022FF0401B41F288339842F3D90320ACE0394AA0
-S31508023000136823F080731360FFF742FD0546354BBC
-S315080230101B6813F0007F06D0FFF73AFD401B022813
-S31508023020F5D9032098E02F4B996A304A0A40A16ADB
-S31508023030E06A41EA00110A439A62226B013AC2F334
-S315080230400802616B0139490289B20A43A16B013947
-S31508023050090401F4FE010A43E16B0139090601F08C
-S31508023060FE410A431A63DA6A22F00102DA62596BEE
-S315080230701F4A0A40A16C42EAC1025A63DA6A22F07E
-S315080230800C02216C0A43DA62DA6A22F00202616CE5
-S315080230900A43DA62DA6A42F48032DA62DA6A42F4B5
-S315080230A00032DA62DA6A42F48022DA62DA6A42F0D4
-S315080230B00102DA621A6842F080721A60FFF7E8FCC7
-S315080230C00446084B1B6813F0007F06D1FFF7E0FCA5
-S315080230D0001B0228F5D903203EE000203CE0002030
-S315080230E03AE000BF00440258004802580CFCFFFFB1
-S315080230F00700FFFF204A916A106B012B2DD001F0C1
-S315080231000303A26A93422AD1C1F30511E36A9942DB
-S3150802311027D1C0F30802236B013B9A4223D1C0F39D
-S315080231204622636B013B9A421FD1C0F30642A36B48
-S31508023130013B9A421BD1C0F30660E36B013B9842FE
-S3150802314017D1002008E001207047012004E0012081
-S3150802315002E0012000E0002038BD0120FCE7012042
-S31508023160FAE70120F8E70120F6E70120F4E7012053
-S31508023170F2E70120F0E700BF00440258724B1B69D0
-S3150802318003F03803102B00F0DB80182B10D00BB19C
-S315080231906E4870476C4B1B6813F0200F00F0D28004
-S315080231A0694B1868C0F3C100694B23FA00F07047EF
-S315080231B0654A916A01F00301906AC0F30510D36A61
-S315080231C003F00103526BC2F3CC0203FB02F307EED0
-S315080231D0903AF8EE677A002800F0B580012966D0A1
-S315080231E0F9B1022900F08F8007EE100AF8EE476A55
-S315080231F09FED586A86EE267A534B1B6BC3F3080378
-S3150802320006EE903AF8EE666A9FED536A67EE867A9C
-S3150802321076EEA77AF7EE006A77EEA67A27EE277A8F
-S3150802322061E0494B1B6813F0200F23D046490A6810
-S31508023230C2F3C102464BD34007EE103AF8EE476A8C
-S3150802324007EE100AB8EE476A86EE867A0B6BC3F368
-S31508023250080306EE903AF8EE666A9FED3F6A67EE55
-S31508023260867A76EEA77AF7EE006A77EEA67A27EEE0
-S31508023270277A38E007EE100AF8EE476A9FED376AB2
-S3150802328086EE267A304B1B6BC3F3080306EE903A9A
-S31508023290F8EE666A9FED306A67EE867A76EEA77A68
-S315080232A0F7EE006A77EEA67A27EE277A1BE007EE94
-S315080232B0100AF8EE476A9FED276A86EE267A224BAF
-S315080232C01B6BC3F3080306EE903AF8EE666A9FEDA7
-S315080232D0226A67EE867A76EEA77AF7EE006A77EEC4
-S315080232E0A67A27EE277A184B1B6BC3F346230133BC
-S315080232F007EE903AF8EE677AC7EE276AFCEEE67AA8
-S3150802330017EE900A704707EE100AF8EE476A9FED25
-S31508023310146A86EE267A0C4B1B6BC3F3080306EE79
-S31508023320903AF8EE666A9FED0C6A67EE867A76EE52
-S31508023330A77AF7EE006A77EEA67A27EE277AD2E719
-S3150802334008487047024870470044025800093D0081
-S315080233500090D0030024744A000000390024744CFB
-S315080233600024F44A00127A00002800F0338103464A
-S315080233709C4A126802F00F028A420BD299480268E6
-S3150802338022F00F020A430260026802F00F028A4222
-S3150802339040F0228170B51A6812F0040F0CD0186931
-S315080233A0914A926902F07002904205D98E4CA2693E
-S315080233B022F070021043A0611A6812F0080F0CD0AE
-S315080233C05869894AD26902F07002904205D9864C38
-S315080233D0E26922F070021043E0611A6812F0100FD7
-S315080233E00CD09869804AD26902F4E062904205D903
-S315080233F07D4CE26922F4E0621043E0611A6812F039
-S31508023400200F0CD0D869784A126A02F070029042EC
-S3150802341005D9754C226A22F07002104320621A6896
-S3150802342012F0020F0CD0D8686F4A926902F00F02A6
-S31508023430904205D96C4CA26922F00F021043A06192
-S315080234401C460D461B6813F0010F41D0664A936964
-S3150802345023F47063A1680B4393616368022B0AD055
-S31508023460032B27D0012B2CD05F4A126812F0040FC7
-S3150802347006D10120ADE0126812F4003F00F0AE80DA
-S3150802348059490A6922F0070213430B61FFF700FB49
-S315080234900646554B1B6903F038036268B3EBC20F45
-S315080234A016D0FFF7F5FA801B41F288339842F0D915
-S315080234B003208EE04C4A126812F0007FE0D1012008
-S315080234C087E0494A126812F4807FD9D1012080E048
-S315080234D0236813F0020F0CD0E268434B9B6903F092
-S315080234E00F039A4205D240498B6923F00F031A4308
-S315080234F08A613C4B1B6803F00F03AB420AD9394A6F
-S31508023500136823F00F032B431360136803F00F03AA
-S31508023510AB4265D1236813F0040F0CD02269324BF3
-S315080235209B6903F070039A4205D22F498B6923F0EF
-S3150802353070031A438A61236813F0080F0CD0626974
-S31508023540294BDB6903F070039A4205D22649CB69F7
-S3150802355023F070031A43CA61236813F0100F0CD0C4
-S31508023560A269214BDB6903F4E0639A4205D21E493C
-S31508023570CB6923F4E0631A43CA61236813F0200F68
-S315080235800CD0E269184B1B6A03F070039A4205D203
-S3150802359015490B6A23F070031A430A62FFF7EEFD18
-S315080235A011498B69C3F30323104AD35C03F01F0343
-S315080235B0D8408B6903F00F03D35C03F01F0320FA8C
-S315080235C003F30B4A13600B4B18600B4B1868FFF793
-S315080235D0FDF970BD01207047012070470120F8E708
-S315080235E00120F6E70020005200440258004502086E
-S315080235F038040020340400203004002008B5FFF700
-S31508023600BDFD0B4A9369C3F303230A49CB5C03F056
-S315080236101F0320FA03F3926902F00F02885C00F096
-S315080236201F0023FA00F0044A1060044A136008BD1A
-S3150802363000440258004502083804002034040020D9
-S3150802364008B5FFF7DBFF054BDB69C3F30213044A30
-S31508023650D35C03F01F03D84008BD00BF00440258DC
-S315080236600045020808B5FFF7C9FF054BDB69C3F336
-S315080236700223044AD35C03F01F03D84008BD00BFE7
-S315080236800044025800450208134BDB6813F0040F86
-S3150802369007D1114BDB6803F0070383421AD00120D6
-S315080236A0704710B50C4AD36823F007031843D06055
-S315080236B0FFF7EEF90446084B5B6813F4005F07D17F
-S315080236C0FFF7E6F9001BB0F57A7FF4D9012000E08E
-S315080236D0002010BD002070470048025830B4446BE1
-S315080236E00268D2F88410704B194041EA8401C2F884
-S315080236F084100268D2F8841021F47F01856B41EAAE
-S315080237000541C2F88410826B22440468D4F88810F2
-S31508023710194041EA8201C4F888100468D4F888106E
-S3150802372021F4FE01C56B41EA0541C4F88810C16B54
-S3150802373002EB41020468D4F8A010194041EA82015A
-S31508023740C4F8A0100468D4F8A01021F4FE01056C90
-S3150802375041EA0541C4F8A010046C416C01FB04243B
-S315080237600268D2F8B010194041EA8401C2F8B010D2
-S315080237700268D2F8B01021F4FE01856C41EA0541CF
-S31508023780C2F8B010826CC16C01FB02440268D2F81E
-S31508023790AC10194041EA8401C2F8AC10026D416DC1
-S315080237A001FB02420468D4F8F010194041EA82018A
-S315080237B0C4F8F0100468D4F8F01021F47C11856D71
-S315080237C041EA0541C4F8F010816D02EB4102046832
-S315080237D0D4F8C0100B4043EA8202C4F8C02002683B
-S315080237E0D2F8C03023F47C13C16D43EA0143C2F810
-S315080237F0C0300268D2F8C03023F07C53016E43EA27
-S315080238000163C2F8C030436B284A1A449200C26662
-S31508023810836B02EB83030367C16B03EBC103436745
-S31508023820046C416C01FB04F103EB81038367846C2E
-S31508023830C16C01FB04F103EB8103C367046D416D9F
-S3150802384001FB04F103EB8103C0F88030816D03EBC1
-S31508023850C103C0F88430C46D856E05FB04F403EB1E
-S315080238608403C0F88830016E01FB05F103EB81037E
-S31508023870C0F890300E498B4207D8D0F89030934260
-S315080238800ED9002342F8043BF7E7D0F89C3043F000
-S315080238902003C0F89C30032380F89830012000E00A
-S315080238A0002030BC704700BF0300FFFF002B00104A
-S315080238B0FCD300407047000030B595B004464C2250
-S315080238C0A04901A800F0C0FD002C00F03881236849
-S315080238D09D4A934220D094F898300BB32268936994
-S315080238E023F010039361FFF7D3F8054623689A6914
-S315080238F012F0080F1AD0FFF7CBF8401B0A28F5D9A1
-S31508023900D4F89C3043F00103C4F89C30032384F8AE
-S315080239109830012015B030BD03F580736360DAE78D
-S3150802392084F899302046FFF7C5FFD7E79A6942F02F
-S3150802393001029A61FFF7ACF8054623689A6912F004
-S31508023940010F0FD1FFF7A4F8401B0A28F5D9D4F8BE
-S315080239509C3043F00103C4F89C30032384F8983062
-S315080239600120D7E79A6942F002029A61237C012B69
-S3150802397040D02268936943F040039361637C012B2C
-S315080239803ED02268936923F480439361A37C012B7A
-S315080239903CD02268936943F4805393612268936901
-S315080239A023F44073A1680B4393612268936923F059
-S315080239B0A40393612268136923F010031361E36871
-S315080239C0012B29D0002B2CD0022B00F09B802268D9
-S315080239D0936943F0800393612268136943F01003E5
-S315080239E01361E368032B1CD12268936943F0200311
-S315080239F0936116E02268936923F040039361BDE759
-S31508023A002268936943F480439361BFE72268936906
-S31508023A1023F480539361C1E72268936943F0040350
-S31508023A209361A3695A1EE369013B1B0243EA426397
-S31508023A30226A013A13436269013A216843EA024358
-S31508023A40CB61A368B3F5407F62D0236E33B1226897
-S31508023A50D2F8C030616E0B43C2F8C030E36D226EF5
-S31508023A60D3420DD02168D1F8C83023F00703A26EDD
-S31508023A7014A800EB820252F84C2C1343C1F8C83042
-S31508023A80236C6BB12168D1F8BC3023F00703626C52
-S31508023A9014A800EB820252F84C2C1343C1F8BC302E
-S31508023AA0A36C73B12168D1F8BC3023F07003E26CC1
-S31508023AB014A800EB820252F84C2C43EA0213C1F80E
-S31508023AC0BC30236D73B12168D1F8BC3023F4E063AE
-S31508023AD0626D14A800EB820252F84C2C43EA0223C8
-S31508023AE0C1F8BC302268184B9A4222D00023C4F887
-S31508023AF09430C4F89C30012384F898302046FFF7A6
-S31508023B00EDFD07E72268936943F02003936188E78E
-S31508023B10A36A013BE26A013A43EA0223226B013AAB
-S31508023B2043EA0213626A013A216843EA0243CB6016
-S31508023B308BE76268936823F003039360D6E7012054
-S31508023B40E8E600BF7C44020800A0004090F89830DE
-S31508023B50013BDBB2012B07D9D0F89C3043F00203B4
-S31508023B60C0F89C3001207047CB680A68D2B9072B87
-S31508023B700ED08A68DB0643EA82730A6943EA02437D
-S31508023B804A691343C26E496842F8213000207047D9
-S31508023B900A69CB691B0243EA02438A69134343F063
-S31508023BA06053EFE710B40A6942EA4372072B0ED054
-S31508023BB08C684B6943EA8473006F496800EBC10459
-S31508023BC040F83120636000205DF8044B70478B692A
-S31508023BD0F2E790F89830DBB2012B07D0D0F89C3088
-S31508023BE043F00403C0F89C3001207047022380F892
-S31508023BF098300268936923F0010393610023C0F8A1
-S31508023C009C30184670470000F0B490F89840E4B229
-S31508023C10022C40F0BA8040290CD0412930D0046DDC
-S31508023C208C4253D8D0F89C3043F02003C0F89C301D
-S31508023C300120B1E00468D4F8A05015F4FE0F0CD0A8
-S31508023C40D4F8A45015F07F0F0FD1D0F89C3043F466
-S31508023C508073C0F89C3001209EE0D0F89C3043F077
-S31508023C602003C0F89C30012096E0D4F8A440C4F39F
-S31508023C70052C446F456C0CFB05F504EB85042DE019
-S31508023C800468D4F8B05015F4FE0F0CD0D4F8B4502A
-S31508023C9015F07F0F0FD1D0F89C3043F48073C0F82B
-S31508023CA09C30012078E0D0F89C3043F02003C0F81D
-S31508023CB09C30012070E0D4F8B440C4F3052C846F1C
-S31508023CC0C56C0CFB05F504EB850407E0C46F456D6E
-S31508023CD001FB05F504EB85044FF0000C256805F099
-S31508023CE080455560002D2CD12568C5F38A45156097
-S31508023CF0256805F000559560256805F000451561AB
-S31508023D00A588D561656805F47025D560656805F4EA
-S31508023D1080155561656805F400159561E57905F024
-S31508023D207F0515626568ED0F556204F108050024E2
-S31508023D30D6891A4FBE5DA64208D92E5D1E55013494
-S31508023D40F6E7256825F060451560D1E740290AD0CF
-S31508023D5041290DD01F290FD80268012303FA01F160
-S31508023D60C2F8981002E00368C3F8A8C0002013E05E
-S31508023D700368C3F8B8C0F9E701F01F010268012316
-S31508023D8003FA01F1C2F89C10F0E7D0F89C3043F030
-S31508023D900803C0F89C300120F0BC7047F0440208C2
-S31508023DA00368D3F89820D3F89C001F2903D8CA4081
-S31508023DB012F0010F17D01F2905D901F01F02D040B2
-S31508023DC010F0010F11D01F2905D8012000FA01F1C0
-S31508023DD0C3F89810704701F01F01012000FA01F19B
-S31508023DE0C3F89C10704700207047002070470000F7
-S31508023DF008B5FFF703FC054B1B6AC3F30213044A13
-S31508023E00D35C03F01F03D84008BD00BF0044025824
-S31508023E100045020810B478498C6A8A6AC2F30532E8
-S31508023E20CB6AC3F30013C96BC1F3CC0103FB01F3DD
-S31508023E30002A00F0DB8004F0030407EE903AF8EE5D
-S31508023E40677A012C66D0FCB1022C00F0B28007EE2C
-S31508023E50102AB8EE477A9FED696AC6EE076A664B7C
-S31508023E609B6BC3F3080307EE103AB8EE477A9FED49
-S31508023E70646A67EE867A77EE277AB7EE007A77EE85
-S31508023E80877A66EEA76A61E05B4B1B6813F0200F20
-S31508023E9023D0594C2168C1F3C1015A4BCB4007EED6
-S31508023EA0103AB8EE477A06EE902AB8EE666AC7EE78
-S31508023EB0066AA36BC3F3080307EE103AB8EE477A0D
-S31508023EC09FED4F6A67EE867A77EE277AB7EE007A23
-S31508023ED077EE877A66EEA76A38E007EE102AB8EE1A
-S31508023EE0477A9FED496AC6EE076A434B9B6BC3F353
-S31508023EF0080307EE103AB8EE477A9FED416A67EE75
-S31508023F00867A77EE277AB7EE007A77EE877A66EEC2
-S31508023F10A76A1BE007EE102AB8EE477A9FED376AC2
-S31508023F20C6EE076A344B9B6BC3F3080307EE103AD7
-S31508023F30B8EE477A9FED326A67EE867A77EE277A87
-S31508023F40B7EE007A77EE877A66EEA76A2A4A936B05
-S31508023F50C3F3462307EE103AB8EE477AB7EE006A7D
-S31508023F6037EE067AC6EE877AFCEEE77AC0ED007A75
-S31508023F70936BC3F3064307EE103AB8EE477A37EE69
-S31508023F80067AC6EE877AFCEEE77AC0ED017A936B7B
-S31508023F90C3F3066307EE903AF8EE677A77EE867A07
-S31508023FA086EEA77ABCEEC77A80ED027A5DF8044BF4
-S31508023FB0704707EE102AB8EE477A9FED146AC6EEE6
-S31508023FC0076A0D4B9B6BC3F3080307EE103AB8EE6C
-S31508023FD0477A9FED0B6A67EE867A77EE277AB7EE0F
-S31508023FE0007A77EE877A66EEA76AAFE70023036060
-S31508023FF043608360DAE700BF004402580024744A2B
-S31508024000000000390090D0030024744C0024F44ABE
-S3150802401010B478498C6A8A6AC2F30552CB6AC3F32A
-S315080240200023496CC1F3CC0103FB01F3002A00F01B
-S31508024030DB8004F0030407EE903AF8EE677A012C67
-S3150802404066D0FCB1022C00F0B28007EE102AB8EE58
-S31508024050477A9FED696AC6EE076A664B1B6CC3F31D
-S31508024060080307EE103AB8EE477A9FED646A67EEE0
-S31508024070867A77EE277AB7EE007A77EE877A66EE51
-S31508024080A76A61E05B4B1B6813F0200F23D0594CDB
-S315080240902168C1F3C1015A4BCB4007EE103AB8EE7C
-S315080240A0477A06EE902AB8EE666AC7EE066A236C67
-S315080240B0C3F3080307EE103AB8EE477A9FED4F6A44
-S315080240C067EE867A77EE277AB7EE007A77EE877A00
-S315080240D066EEA76A38E007EE102AB8EE477A9FED31
-S315080240E0496AC6EE076A434B1B6CC3F3080307EE1D
-S315080240F0103AB8EE477A9FED416A67EE867A77EE0E
-S31508024100277AB7EE007A77EE877A66EEA76A1BE019
-S3150802411007EE102AB8EE477A9FED376AC6EE076AA7
-S31508024120344B1B6CC3F3080307EE103AB8EE477A12
-S315080241309FED326A67EE867A77EE277AB7EE007ACD
-S3150802414077EE877A66EEA76A2A4A136CC3F3462382
-S3150802415007EE103AB8EE477AB7EE006A37EE067AF5
-S31508024160C6EE877AFCEEE77AC0ED007A136CC3F3E3
-S31508024170064307EE103AB8EE477A37EE067AC6EEE7
-S31508024180877AFCEEE77AC0ED017A136CC3F306630D
-S3150802419007EE903AF8EE677A77EE867A86EEA77A8F
-S315080241A0BCEEC77A80ED027A5DF8044B704707EEDB
-S315080241B0102AB8EE477A9FED146AC6EE076A0D4BC7
-S315080241C01B6CC3F3080307EE103AB8EE477A9FED65
-S315080241D00B6A67EE867A77EE277AB7EE007A77EE7B
-S315080241E0877A66EEA76AAFE70023036043608360B7
-S315080241F0DAE700BF004402580024744A0000003976
-S315080242000090D0030024744C0024F44A184AD2F8C9
-S31508024210883043F47003C2F88830164B1A6842F0A5
-S3150802422001021A6000221A611868134901401960CE
-S315080242309A61DA611A629A62DA621A635A639A634D
-S31508024240DA631A645A64196821F4802119601A66B5
-S315080242500A4B1A680A4B1340B3F1005F02D2094BA4
-S3150802426001221A60024B4FF000629A60704700BF43
-S3150802427000ED00E0004402587FEDF6EA0010005C0B
-S315080242800000FFFF08810051654B1B6903F03803E4
-S31508024290102B00F0C380182B1CD0A3B1614A6048CA
-S315080242A08369C3F303236049CB5CDA40836903F06D
-S315080242B00F03CB5C03F01F0322FA03F35B490B607F
-S315080242C05B4B1A607047564B1B68C3F3C103594AC6
-S315080242D0DA40E4E75249886A00F003008A6AC2F3C0
-S315080242E00512CB6A03F00103496BC1F3CC0103FB48
-S315080242F001F307EE903AF8EE677A002ACFD0012842
-S3150802430052D0F0B102286CD007EE102AF8EE476AAE
-S315080243109FED496A86EE267A414B1B6BC3F3080367
-S3150802432006EE903AF8EE666A9FED446A67EE867A7A
-S3150802433076EEA77AF7EE006A77EEA67A27EE277A5E
-S3150802434022E037480168C1F3C1013A4BCB4007EE78
-S31508024350103AF8EE476A07EE102AB8EE476A86EE72
-S31508024360867A036BC3F3080306EE903AF8EE666A9A
-S315080243709FED326A67EE867A76EEA77AF7EE006ADC
-S3150802438077EEA67A27EE277A254B1B6BC3F34623CD
-S31508024390013307EE903AF8EE677AC7EE276AFCEE23
-S315080243A0E67A17EE902A7AE707EE102AF8EE476AB7
-S315080243B09FED216A86EE267A194B1B6BC3F3080317
-S315080243C006EE903AF8EE666A9FED1C6A67EE867A02
-S315080243D076EEA77AF7EE006A77EEA67A27EE277ABE
-S315080243E0D2E707EE102AF8EE476A9FED156A86EEBF
-S315080243F0267A0B4B1B6BC3F3080306EE903AF8EECC
-S31508024400666A9FED0E6A67EE867A76EEA77AF7EE09
-S31508024410006A77EEA67A27EE277AB5E7094A3EE7D3
-S315080244200044025800093D000045020838040020ED
-S31508024430340400200090D0030024744A0000003996
-S315080244400024F44A00127A000A44914200F1FF332A
-S3150802445000D1704710B511F8014B03F8014F91428C
-S31508024460F9D110BDF8B500BFF8BC08BC9E46704726
-S31108024470F8B500BFF8BC08BC9E467047B1
-S3150802447C0000000000000000000000000000000020
-S3150802448C000000000100000002000000030000000A
-S3150802449C04000000000000000500000000000000F7
-S315080244AC00000000000000000600000000000000EA
-S315080244BC00000000000000000700000000000020B9
-S315080244CC05020602060307030803090309040A047C
-S315080244DC0B040C040C050D050E050F050F0610062C
-S315080244EC100710080001020304050607080C10142D
-S315080244FC18203040000000000102030401020304E4
-S3090802450C060708097D
-S30D0802451000BEFF7F0100000056
-S30D08024518CD060208C5020208DD
-S30908024520A1020208DA
-S3150802452400000000EC02002054030020BC03002013
-S315080245340000000000000000000000000000000067
-S315080245440000000000000000000000000000000057
-S315080245540000000000000000000000000000000047
-S315080245640000000000000000000000000000000037
-S315080245740000000000000000000000000000000027
-S315080245840000000000000000000000000000000017
-S315080245940000000000000000000000000000000007
-S315080245A400000000000000000000000000000000F7
-S315080245B400000000000000000000000000000000E7
-S315080245C400000000000000000100000000000000D6
-S315080245D40E33CDAB34126DE6ECDE05000B0000009B
-S315080245E400000000000000000000000000000000B7
-S315080245F400000000000000000000000000000000A7
-S315080246040000000000000000000000000000000096
-S315080246140000000000000000000000000000000086
-S315080246240000000000000000000000000000000076
-S315080246340000000000000000000000000000000066
-S315080246440000000000000000000000000000000056
-S315080246540000000000000000000000000000000046
-S315080246640000000000000000000000000000000036
-S315080246740000000000000000000000000000000026
-S315080246840000000000000000000000000000000016
-S315080246940000000000000000000000000000000006
-S315080246A400000000000000000000000000000000F6
-S315080246B400000000000000000000000000000000E6
-S315080246C400000000000000000000000000000000D6
-S315080246D400000000000000000000000000000000C6
-S315080246E400000000000000000000000000000000B6
-S315080246F400000000000000000000000000000000A6
-S315080247040000000000000000000000000000000095
-S315080247140000000000000000000000000000000085
-S315080247240000000000000000000000000000000075
-S315080247340000000000000000000000000000000065
-S315080247440000000000000000000000000000000055
-S315080247540000000000000000000000000000000045
-S315080247640000000000000000000000000000000035
-S315080247740000000000000000000000000000000025
-S315080247840000000000000000000000000000000015
-S315080247940000000000000000000000000000000005
-S315080247A400000000000000000000000000000000F5
-S315080247B400000000000000000000000000000000E5
-S315080247C400000000000000000000000000000000D5
-S315080247D400000000000000000000000000000000C5
-S315080247E400000000000000000000000000000000B5
-S315080247F400000000000000000000000000000000A5
-S315080248040000000000000000000000000000000094
-S315080248140000000000000000000000000000000084
-S315080248240000000000000000000000000000000074
-S315080248340000000000000000000000000000000064
-S315080248440000000000000000000000000000000054
-S315080248540000000000000000000000000000000044
-S315080248640000000000000000000000000000000034
-S315080248740000000000000000000000000000000024
-S315080248840000000000000000000000000000000014
-S315080248940000000000000000000000000000000004
-S315080248A400000000000000000000000000000000F4
-S315080248B400000000000000000000000000000000E4
-S315080248C400000000000000000000000000000000D4
-S315080248D400000000000000000000000000000000C4
-S315080248E400000000000000000000000000000000B4
-S315080248F400000000000000000000000000000000A4
-S315080249040000000000000000000000000000000093
-S315080249140000000000000000000000000000000083
-S315080249240000000000000000000000000000000073
-S315080249340000000000000000000000000000000063
-S315080249440000000000000000D40500200100000059
-S31108024954100000000090D0030090D00371
+S31508020800FEE70000184AD2F8883043F47003C2F8AB
+S315080208108830164B1A6842F001021A6000221A61E1
+S3150802082018681349014019609A61DA611A629A6274
+S31508020830DA621A635A639A63DA631A645A6419683B
+S3150802084021F4802119601A660A4B1A680A4B13406A
+S31508020850B3F1005F02D2094B01221A60024B4FF034
+S3150802086000629A60704700BF00ED00E0004402583B
+S315080208707FEDF6EA0010005C0000FFFF08810051D8
+S31508020880654B1B6903F03803102B00F0C380182B45
+S315080208901CD0A3B1614A60488369C3F30323604944
+S315080208A0CB5CDA40836903F00F03CB5C03F01F03CA
+S315080208B022FA03F35B490B605B4B1A607047564B8F
+S315080208C01B68C3F3C103594ADA40E4E75249886A06
+S315080208D000F003008A6AC2F30512CB6A03F0010329
+S315080208E0496BC1F3CC0103FB01F307EE903AF8EE2C
+S315080208F0677A002ACFD0012852D0F0B102286CD0EC
+S3150802090007EE102AF8EE476A9FED496A86EE267ABE
+S31508020910414B1B6BC3F3080306EE903AF8EE666A80
+S315080209209FED446A67EE867A76EEA77AF7EE006A54
+S3150802093077EEA67A27EE277A22E037480168C1F3CE
+S31508020940C1013A4BCB4007EE103AF8EE476A07EE7A
+S31508020950102AB8EE476A86EE867A036BC3F3080353
+S3150802096006EE903AF8EE666A9FED326A67EE867A86
+S3150802097076EEA77AF7EE006A77EEA67A27EE277A58
+S31508020980254B1B6BC3F34623013307EE903AF8EE69
+S31508020990677AC7EE276AFCEEE67A17EE902A7AE7B6
+S315080209A007EE102AF8EE476A9FED216A86EE267A46
+S315080209B0194B1B6BC3F3080306EE903AF8EE666A08
+S315080209C09FED1C6A67EE867A76EEA77AF7EE006ADC
+S315080209D077EEA67A27EE277AD2E707EE102AF8EEFE
+S315080209E0476A9FED156A86EE267A0B4B1B6BC3F395
+S315080209F0080306EE903AF8EE666A9FED0E6A67EE0F
+S31508020A00867A76EEA77AF7EE006A77EEA67A27EE68
+S31508020A10277AB5E7094A3EE70044025800093D002D
+S31508020A20E0440208300400202C0400200090D00381
+S31508020A300024744A000000390024F44A00127A009D
+S31508020A40104B1B780BB90120704710B504464FF4BA
+S31508020A507A70B0FBF3F30C4A1068B0FBF3F001F0BE
+S31508020A60E5FB68B90F2C01D901200AE000222146CC
+S31508020A704FF0FF3001F0A8FB044B1C60002000E099
+S31508020A80012010BD340400202C0400203804002064
+S31508020A9010B5032001F086FB01F0FEF80F498B69B9
+S31508020AA0C3F303230E4AD35C03F01F03D8408B69B2
+S31508020AB003F00F03D35C03F01F0320FA03F3094A7A
+S31508020AC01360094B18600020FFF7BAFF10B1012422
+S31508020AD0204610BD044603F0E1FAF9E7004402583D
+S31508020AE0E0440208300400202C040020034B1B7843
+S31508020AF0034A11680B441360704700BF3404002090
+S31508020B00F8050020014B1868704700BFF805002059
+S31508020B10014B1868000C70470010005C08B501F01C
+S31508020B20FBFA054B1B6AC3F30213044AD35C03F0B0
+S31508020B301F03D84008BD00BF00440258E04402081B
+S31508020B4010B478498C6A8A6AC2F30532CB6AC3F34F
+S31508020B500013C96BC1F3CC0103FB01F3002A00F0B1
+S31508020B60DB8004F0030407EE903AF8EE677A012C6C
+S31508020B7066D0FCB1022C00F0B28007EE102AB8EE5D
+S31508020B80477A9FED696AC6EE076A664B9B6BC3F3A3
+S31508020B90080307EE103AB8EE477A9FED646A67EEE5
+S31508020BA0867A77EE277AB7EE007A77EE877A66EE56
+S31508020BB0A76A61E05B4B1B6813F0200F23D0594CE0
+S31508020BC02168C1F3C1015A4BCB4007EE103AB8EE81
+S31508020BD0477A06EE902AB8EE666AC7EE066AA36BED
+S31508020BE0C3F3080307EE103AB8EE477A9FED4F6A49
+S31508020BF067EE867A77EE277AB7EE007A77EE877A05
+S31508020C0066EEA76A38E007EE102AB8EE477A9FED35
+S31508020C10496AC6EE076A434B9B6BC3F3080307EEA2
+S31508020C20103AB8EE477A9FED416A67EE867A77EE12
+S31508020C30277AB7EE007A77EE877A66EEA76A1BE01E
+S31508020C4007EE102AB8EE477A9FED376AC6EE076AAC
+S31508020C50344B9B6BC3F3080307EE103AB8EE477A98
+S31508020C609FED326A67EE867A77EE277AB7EE007AD2
+S31508020C7077EE877A66EEA76A2A4A936BC3F3462308
+S31508020C8007EE103AB8EE477AB7EE006A37EE067AFA
+S31508020C90C6EE877AFCEEE77AC0ED007A936BC3F369
+S31508020CA0064307EE103AB8EE477A37EE067AC6EEEC
+S31508020CB0877AFCEEE77AC0ED017A936BC3F3066393
+S31508020CC007EE903AF8EE677A77EE867A86EEA77A94
+S31508020CD0BCEEC77A80ED027A5DF8044B704707EEE0
+S31508020CE0102AB8EE477A9FED146AC6EE076A0D4BCC
+S31508020CF09B6BC3F3080307EE103AB8EE477A9FEDEB
+S31508020D000B6A67EE867A77EE277AB7EE007A77EE7F
+S31508020D10877A66EEA76AAFE70023036043608360BB
+S31508020D20DAE700BF004402580024744A000000397A
+S31508020D300090D0030024744C0024F44A10B4784975
+S31508020D408C6A8A6AC2F30552CB6AC3F30023496CDA
+S31508020D50C1F3CC0103FB01F3002A00F0DB8004F0A7
+S31508020D60030407EE903AF8EE677A012C66D0FCB1D6
+S31508020D70022C00F0B28007EE102AB8EE477A9FEDF1
+S31508020D80696AC6EE076A664B1B6CC3F3080307EE6D
+S31508020D90103AB8EE477A9FED646A67EE867A77EE7E
+S31508020DA0277AB7EE007A77EE877A66EEA76A61E067
+S31508020DB05B4B1B6813F0200F23D0594C2168C1F3F3
+S31508020DC0C1015A4BCB4007EE103AB8EE477A06EE07
+S31508020DD0902AB8EE666AC7EE066A236CC3F308035E
+S31508020DE007EE103AB8EE477A9FED4F6A67EE867AB3
+S31508020DF077EE277AB7EE007A77EE877A66EEA76AF3
+S31508020E0038E007EE102AB8EE477A9FED496AC6EE31
+S31508020E10076A434B1B6CC3F3080307EE103AB8EE96
+S31508020E20477A9FED416A67EE867A77EE277AB7EEBA
+S31508020E30007A77EE877A66EEA76A1BE007EE102A33
+S31508020E40B8EE477A9FED376AC6EE076A344B1B6CD3
+S31508020E50C3F3080307EE103AB8EE477A9FED326AF3
+S31508020E6067EE867A77EE277AB7EE007A77EE877A92
+S31508020E7066EEA76A2A4A136CC3F3462307EE103AAC
+S31508020E80B8EE477AB7EE006A37EE067AC6EE877A82
+S31508020E90FCEEE77AC0ED007A136CC3F3064307EE5D
+S31508020EA0103AB8EE477A37EE067AC6EE877AFCEE3D
+S31508020EB0E77AC0ED017A136CC3F3066307EE903A3C
+S31508020EC0F8EE677A77EE867A86EEA77ABCEEC77A66
+S31508020ED080ED027A5DF8044B704707EE102AB8EEE9
+S31508020EE0477A9FED146AC6EE076A0D4B1B6CC3F36D
+S31508020EF0080307EE103AB8EE477A9FED0B6A67EEDB
+S31508020F00867A77EE277AB7EE007A77EE877A66EEF2
+S31508020F10A76AAFE70023036043608360DAE700BF8E
+S31508020F20004402580024744A000000390090D00395
+S31508020F300024744C0024F44A30B4446B0268D2F894
+S31508020F408410704B194041EA8401C2F88410026881
+S31508020F50D2F8841021F47F01856B41EA0541C2F873
+S31508020F608410826B22440468D4F88810194041EA36
+S31508020F708201C4F888100468D4F8881021F4FE01A6
+S31508020F80C56B41EA0541C4F88810C16B02EB410200
+S31508020F900468D4F8A010194041EA8201C4F8A010E6
+S31508020FA00468D4F8A01021F4FE01056C41EA054153
+S31508020FB0C4F8A010046C416C01FB04240268D2F840
+S31508020FC0B010194041EA8401C2F8B0100268D2F89A
+S31508020FD0B01021F4FE01856C41EA0541C2F8B01051
+S31508020FE0826CC16C01FB02440268D2F8AC1019404B
+S31508020FF041EA8401C2F8AC10026D416D01FB02425E
+S315080210000468D4F8F010194041EA8201C4F8F010D5
+S315080210100468D4F8F01021F47C11856D41EA054183
+S31508021020C4F8F010816D02EB41020468D4F8C010CE
+S315080210300B4043EA8202C4F8C0200268D2F8C030E4
+S3150802104023F47C13C16D43EA0143C2F8C030026837
+S31508021050D2F8C03023F07C53016E43EA0163C2F82A
+S31508021060C030436B284A1A449200C266836B02EB6D
+S3150802107083030367C16B03EBC1034367046C416CCB
+S3150802108001FB04F103EB81038367846CC16C01FBEA
+S3150802109004F103EB8103C367046D416D01FB04F19F
+S315080210A003EB8103C0F88030816D03EBC103C0F8FE
+S315080210B08430C46D856E05FB04F403EB8403C0F823
+S315080210C08830016E01FB05F103EB8103C0F890300D
+S315080210D00E498B4207D8D0F8903093420ED9002396
+S315080210E042F8043BF7E7D0F89C3043F02003C0F8F7
+S315080210F09C30032380F89830012000E0002030BCA1
+S31508021100704700BF0300FFFF002B0010FCD300400E
+S315080211107047000030B595B004464C22A04901A894
+S3150802112003F09CF9002C00F0388123689D4A93420B
+S3150802113020D094F898300BB32268936923F01003F1
+S315080211409361FFF7DFFC054623689A6912F0080FD8
+S315080211501AD0FFF7D7FC401B0A28F5D9D4F89C30D9
+S3150802116043F00103C4F89C30032384F89830012025
+S3150802117015B030BD03F580736360DAE784F89930F9
+S315080211802046FFF7C5FFD7E79A6942F001029A613E
+S31508021190FFF7B8FC054623689A6912F0010F0FD1CA
+S315080211A0FFF7B0FC401B0A28F5D9D4F89C3043F067
+S315080211B00103C4F89C30032384F898300120D7E74A
+S315080211C09A6942F002029A61237C012B40D0226876
+S315080211D0936943F040039361637C012B3ED02268F6
+S315080211E0936923F480439361A37C012B3CD0226844
+S315080211F0936943F4805393612268936923F4407395
+S31508021200A1680B4393612268936923F0A40393614F
+S315080212102268136923F010031361E368012B29D0AE
+S31508021220002B2CD0022B00F09B802268936943F096
+S31508021230800393612268136943F010031361E3681C
+S31508021240032B1CD12268936943F02003936116E0AD
+S315080212502268936923F040039361BDE72268936984
+S3150802126043F480439361BFE72268936923F480536A
+S315080212709361C1E72268936943F004039361A36902
+S315080212805A1EE369013B1B0243EA4263226A013A98
+S3150802129013436269013A216843EA0243CB61A368B0
+S315080212A0B3F5407F62D0236E33B12268D2F8C030DC
+S315080212B0616E0B43C2F8C030E36D226ED3420DD085
+S315080212C02168D1F8C83023F00703A26E14A800EBF0
+S315080212D0820252F84C2C1343C1F8C830236C6BB106
+S315080212E02168D1F8BC3023F00703626C14A800EB1E
+S315080212F0820252F84C2C1343C1F8BC30A36C73B16A
+S315080213002168D1F8BC3023F07003E26C14A800EB14
+S31508021310820252F84C2C43EA0213C1F8BC30236D00
+S3150802132073B12168D1F8BC3023F4E063626D14A866
+S3150802133000EB820252F84C2C43EA0223C1F8BC3075
+S315080213402268184B9A4222D00023C4F89430C4F873
+S315080213509C30012384F898302046FFF7EDFD07E715
+S315080213602268936943F02003936188E7A36A013BE5
+S31508021370E26A013A43EA0223226B013A43EA02137A
+S31508021380626A013A216843EA0243CB608BE76268E4
+S31508021390936823F003039360D6E70120E8E600BFCB
+S315080213A09044020800A0004090F89830013BDBB256
+S315080213B0012B07D9D0F89C3043F00203C0F89C30C1
+S315080213C001207047CB680A68D2B9072B0ED08A6803
+S315080213D0DB0643EA82730A6943EA02434A6913430C
+S315080213E0C26E496842F82130002070470A69CB6903
+S315080213F01B0243EA02438A69134343F06053EFE749
+S3150802140010B40A6942EA4372072B0ED08C684B69FC
+S3150802141043EA8473006F496800EBC10440F831203F
+S31508021420636000205DF8044B70478B69F2E710B4DD
+S3150802143090F89840E4B2012C09D0D0F89C3043F0D9
+S315080214400403C0F89C3001205DF8044B70479200F3
+S3150802145042EA011242EA43020168019B1A43C1F8B1
+S3150802146080200020F0E790F89830DBB2012B07D0F5
+S31508021470D0F89C3043F00403C0F89C300120704732
+S31508021480022380F898300268936923F00103936176
+S315080214900023C0F89C30184670470000F0B490F854
+S315080214A09840E4B2022C40F0BA8040290CD0412977
+S315080214B030D0046D8C4253D8D0F89C3043F02003C8
+S315080214C0C0F89C300120B1E00468D4F8A05015F4A5
+S315080214D0FE0F0CD0D4F8A45015F07F0F0FD1D0F818
+S315080214E09C3043F48073C0F89C3001209EE0D0F80B
+S315080214F09C3043F02003C0F89C30012096E0D4F8D3
+S31508021500A440C4F3052C446F456C0CFB05F504EBAB
+S3150802151085042DE00468D4F8B05015F4FE0F0CD0FB
+S31508021520D4F8B45015F07F0F0FD1D0F89C3043F49D
+S315080215308073C0F89C30012078E0D0F89C3043F0E4
+S315080215402003C0F89C30012070E0D4F8B440C4F3FC
+S31508021550052C846FC56C0CFB05F504EB850407E0C6
+S31508021560C46F456D01FB05F504EB85044FF0000CCD
+S31508021570256805F080455560002D2CD12568C5F3F0
+S315080215808A451560256805F000559560256805F0B9
+S3150802159000451561A588D561656805F47025D5608D
+S315080215A0656805F480155561656805F40015956149
+S315080215B0E57905F07F0515626568ED0F556204F158
+S315080215C008050024D6891A4FBE5DA64208D92E5DA3
+S315080215D01E550134F6E7256825F060451560D1E702
+S315080215E040290AD041290DD01F290FD802680123A4
+S315080215F003FA01F1C2F8981002E00368C3F8A8C01A
+S31508021600002013E00368C3F8B8C0F9E701F01F0128
+S315080216100268012303FA01F1C2F89C10F0E7D0F838
+S315080216209C3043F00803C0F89C300120F0BC704798
+S31508021630F0440208402905D00368D3F8B40000F044
+S315080216407F0070470368D3F8A40000F07F00704754
+S31508021650134BDB6813F0040F07D1114BDB6803F059
+S31508021660070383421AD00120704710B50C4AD36883
+S3150802167023F007031843D060FFF744FA0446084BE1
+S315080216805B6813F4005F07D1FFF73CFA001BB0F55D
+S315080216907A7FF4D9012000E0002010BD00207047AF
+S315080216A000480258002800F0DC8238B50446036870
+S315080216B013F0010F25D0A94A136903F03803926A79
+S315080216C0102B15D0182B0FD06368B3F5803F3ED088
+S315080216D0002B52D1A14B1A6822F480321A601A687A
+S315080216E022F480221A6037E002F00302022AEBD1C2
+S315080216F09A4B1B6813F4003F03D06368002B00F073
+S31508021700B282236813F0020F77D0944A1369926A59
+S3150802171013F038035AD0182B55D0E368002B00F083
+S31508021720B2808E490A6822F0190213430B60FFF74A
+S31508021730E9F90546894B1B6813F0040F40F08B80C4
+S31508021740FFF7E0F9401B0228F4D9032092E2834A04
+S31508021750136843F48033136063682BB3FFF7D2F937
+S3150802176005467E4B1B6813F4003FCAD1FFF7CAF938
+S31508021770401B6428F5D903207CE2B3F5A02F09D0D3
+S31508021780764B1A6822F480321A601A6822F480228A
+S315080217901A60E1E7714B1A6842F480221A601A68E5
+S315080217A042F480321A60D7E7FFF7ACF905466B4B6D
+S315080217B01B6813F4003FA4D0FFF7A4F9401B642862
+S315080217C0F5D9032056E212F0030FA6D1634B1B6824
+S315080217D013F0040F03D0E368002B00F04682FFF7EC
+S315080217E097F941F2030398422CD85C4A536823F4CA
+S315080217F07C33216943EA01335360236813F0100FDF
+S3150802180070D0564A136903F03803926A082B52D0ED
+S31508021810182B4CD0E369002B00F0A2804F4A1368BC
+S3150802182043F080031360FFF76DF905464B4B1B68BF
+S3150802183013F4807F7AD1FFF765F9401B0228F5D9A0
+S31508021840032017E2454A536823F0FE43216943EA17
+S3150802185001635360D1E7FFF75BF941F2030398424C
+S3150802186008D83E4A536823F47C33216943EA013394
+S315080218705360C2E7394A536823F0FE43216943EAB3
+S3150802188001635360B9E7354A136823F0010313600D
+S31508021890FFF738F90546314B1B6813F0040FACD035
+S315080218A0FFF730F9401B0228F5D90320E2E102F0DE
+S315080218B00302012AAED1294B1B6813F4807F03D099
+S315080218C0E369802B40F0D381FFF722F941F2030343
+S315080218D0984222D8214A536823F0F843216A43EAF8
+S315080218E081635360236813F0080F61D06369002B84
+S315080218F04AD01A4A536F43F001035367FFF702F9B6
+S315080219000546164B5B6F13F0020F51D1FFF7FAF833
+S31508021910401B0228F5D90320ACE1104AD36823F00C
+S315080219207C53216A43EA0163D360DBE7FFF7F0F8E9
+S3150802193041F20303984208D8084A536823F0F84349
+S31508021940216A43EA81635360CCE7044AD36823F0E9
+S315080219507C53216A43EA0163D360C3E70044025811
+S31508021960A74A136823F080031360FFF7CBF80546EE
+S31508021970A34B1B6813F4807FB4D0FFF7C3F8401B50
+S315080219800228F5D9032075E19D4A536F23F0010316
+S315080219905367FFF7B7F80546994B5B6F13F0020FCB
+S315080219A006D0FFF7AFF8401B0228F5D9032061E1FC
+S315080219B0236813F0200F29D0A3699BB1904A1368B4
+S315080219C043F480531360FFF79DF805468C4B1B685A
+S315080219D013F4005F1AD1FFF795F8401B0228F5D9D0
+S315080219E0032047E1864A136823F480531360FFF7FE
+S315080219F089F80546824B1B6813F4005F06D0FFF789
+S31508021A0081F8401B0228F5D9032033E1236813F035
+S31508021A10040F21D1636A002B00F02B81784A1269E0
+S31508021A2002F03802182A00F0F380022B75D0744AA5
+S31508021A30136823F080731360FFF764F80446704B4B
+S31508021A401B6813F0007F00F0D880FFF75BF8001BD5
+S31508021A500228F4D903200DE16A4A136843F4807315
+S31508021A601360FFF74FF80546664B1B6813F4807F31
+S31508021A7006D1FFF747F8401B6428F5D90320F9E099
+S31508021A80A368012B0AD00BBB5D4B1A6F22F0010229
+S31508021A901A671A6F22F004021A6704E0584A136F8B
+S31508021AA043F001031367A36833B3FFF72BF8054620
+S31508021AB0534B1B6F13F0020FACD1FFF723F8401BF1
+S31508021AC041F288339842F3D90320D3E0052B09D093
+S31508021AD04B4B1A6F22F001021A671A6F22F00402A0
+S31508021AE01A67E0E7464B1A6F42F004021A671A6F42
+S31508021AF042F001021A67D6E7FFF704F80546404B9B
+S31508021B001B6F13F0020F85D0FEF7FCFF401B41F254
+S31508021B1088339842F3D90320ACE0394A136823F094
+S31508021B2080731360FEF7EEFF0546354B1B6813F00C
+S31508021B30007F06D0FEF7E6FF401B0228F5D90320F0
+S31508021B4098E02F4B996A304A0A40A16AE06A41EA4C
+S31508021B5000110A439A62226B013AC2F30802616BC8
+S31508021B600139490289B20A43A16B0139090401F410
+S31508021B70FE010A43E16B0139090601F0FE410A43F7
+S31508021B801A63DA6A22F00102DA62596B1F4A0A40BC
+S31508021B90A16C42EAC1025A63DA6A22F00C02216C8B
+S31508021BA00A43DA62DA6A22F00202616C0A43DA62EC
+S31508021BB0DA6A42F48032DA62DA6A42F40032DA62C5
+S31508021BC0DA6A42F48022DA62DA6A42F00102DA62F8
+S31508021BD01A6842F080721A60FEF794FF0446084BB0
+S31508021BE01B6813F0007F06D1FEF78CFF001B022844
+S31508021BF0F5D903203EE000203CE000203AE000BF91
+S31508021C0000440258004802580CFCFFFF0700FFFF79
+S31508021C10204A916A106B012B2DD001F00303A26AA8
+S31508021C2093422AD1C1F30511E36A994227D1C0F337
+S31508021C300802236B013B9A4223D1C0F34622636B07
+S31508021C40013B9A421FD1C0F30642A36B013B9A425B
+S31508021C501BD1C0F30660E36B013B984217D1002003
+S31508021C6008E001207047012004E0012002E001207B
+S31508021C7000E0002038BD0120FCE70120FAE7012038
+S31508021C80F8E70120F6E70120F4E70120F2E7012050
+S31508021C90F0E700BF00440258724B1B6903F0380391
+S31508021CA0102B00F0DB80182B10D00BB16E48704752
+S31508021CB06C4B1B6813F0200F00F0D280694B186832
+S31508021CC0C0F3C100694B23FA00F07047654A916A6E
+S31508021CD001F00301906AC0F30510D36A03F0010309
+S31508021CE0526BC2F3CC0203FB02F307EE903AF8EE0C
+S31508021CF0677A002800F0B580012966D0F9B1022971
+S31508021D0000F08F8007EE100AF8EE476A9FED586AD0
+S31508021D1086EE267A534B1B6BC3F3080306EE903AFC
+S31508021D20F8EE666A9FED536A67EE867A76EEA77ACA
+S31508021D30F7EE006A77EEA67A27EE277A61E0494B34
+S31508021D401B6813F0200F23D046490A68C2F3C10262
+S31508021D50464BD34007EE103AF8EE476A07EE100AEA
+S31508021D60B8EE476A86EE867A0B6BC3F3080306EE6D
+S31508021D70903AF8EE666A9FED3F6A67EE867A76EEE5
+S31508021D80A77AF7EE006A77EEA67A27EE277A38E080
+S31508021D9007EE100AF8EE476A9FED376A86EE267A4C
+S31508021DA0304B1B6BC3F3080306EE903AF8EE666AED
+S31508021DB09FED306A67EE867A76EEA77AF7EE006AC4
+S31508021DC077EEA67A27EE277A1BE007EE100AF8EED8
+S31508021DD0476A9FED276A86EE267A224B1B6BC3F368
+S31508021DE0080306EE903AF8EE666A9FED226A67EEF7
+S31508021DF0867A76EEA77AF7EE006A77EEA67A27EE65
+S31508021E00277A184B1B6BC3F34623013307EE903A26
+S31508021E10F8EE677AC7EE276AFCEEE67A17EE900ABC
+S31508021E20704707EE100AF8EE476A9FED146A86EEC7
+S31508021E30267A0C4B1B6BC3F3080306EE903AF8EEB0
+S31508021E40666A9FED0C6A67EE867A76EEA77AF7EEF1
+S31508021E50006A77EEA67A27EE277AD2E7084870470D
+S31508021E60024870470044025800093D000090D0031A
+S31508021E700024744A000000390024744C0024F44AF1
+S31508021E8000127A00002800F0338103469C4A126841
+S31508021E9002F00F028A420BD29948026822F00F0218
+S31508021EA00A430260026802F00F028A4240F0228167
+S31508021EB070B51A6812F0040F0CD01869914A926923
+S31508021EC002F07002904205D98E4CA26922F0700285
+S31508021ED01043A0611A6812F0080F0CD05869894A93
+S31508021EE0D26902F07002904205D9864CE26922F064
+S31508021EF070021043E0611A6812F0100F0CD098694C
+S31508021F00804AD26902F4E062904205D97D4CE269C0
+S31508021F1022F4E0621043E0611A6812F0200F0CD036
+S31508021F20D869784A126A02F07002904205D9754C4D
+S31508021F30226A22F07002104320621A6812F0020F17
+S31508021F400CD0D8686F4A926902F00F02904205D9FE
+S31508021F506C4CA26922F00F021043A0611C460D4682
+S31508021F601B6813F0010F41D0664A936923F4706324
+S31508021F70A1680B4393616368022B0AD0032B27D00F
+S31508021F80012B2CD05F4A126812F0040F06D10120E9
+S31508021F90ADE0126812F4003F00F0AE8059490A69B2
+S31508021FA022F0070213430B61FEF7ACFD0646554BBA
+S31508021FB01B6903F038036268B3EBC20F16D0FEF74B
+S31508021FC0A1FD801B41F288339842F0D903208EE0A6
+S31508021FD04C4A126812F0007FE0D1012087E0494A94
+S31508021FE0126812F4807FD9D1012080E0236813F0A9
+S31508021FF0020F0CD0E268434B9B6903F00F039A4227
+S3150802200005D240498B6923F00F031A438A613C4B78
+S315080220101B6803F00F03AB420AD9394A136823F047
+S315080220200F032B431360136803F00F03AB4265D10A
+S31508022030236813F0040F0CD02269324B9B6903F014
+S3150802204070039A4205D22F498B6923F070031A430B
+S315080220508A61236813F0080F0CD06269294BDB6981
+S3150802206003F070039A4205D22649CB6923F070031E
+S315080220701A43CA61236813F0100F0CD0A269214BC8
+S31508022080DB6903F4E0639A4205D21E49CB6923F45D
+S31508022090E0631A43CA61236813F0200F0CD0E26981
+S315080220A0184B1B6A03F070039A4205D215490B6A4C
+S315080220B023F070031A430A62FFF7EEFD11498B6992
+S315080220C0C3F30323104AD35C03F01F03D8408B697A
+S315080220D003F00F03D35C03F01F0320FA03F30B4A42
+S315080220E013600B4B18600B4B1868FEF7A9FC70BD02
+S315080220F001207047012070470120F8E70120F6E722
+S315080221000020005200440258E0440208300400202D
+S315080221102C0400203804002008B5FFF7BDFD0B4A41
+S315080221209369C3F303230A49CB5C03F01F0320FA1E
+S3150802213003F3926902F00F02885C00F01F0023FA8B
+S3150802214000F0044A1060044A136008BD00440258AD
+S31508022150E0440208300400202C04002008B5FFF7EA
+S31508022160DBFF054BDB69C3F30213044AD35C03F0B6
+S315080221701F03D84008BD00BF00440258E0440208C5
+S3150802218008B5FFF7C9FF054BDB69C3F30223044A07
+S31508022190D35C03F01F03D84008BD00BF00440258B1
+S315080221A0E04402080649CB6823F4E0631B041B0CCF
+S315080221B0000200F4E0600343024A1A43CA60704709
+S315080221C000ED00E00000FA0530B4154BDB68C3F3F6
+S315080221D00223C3F10704042C28BF04241D1D062D5F
+S315080221E001D9033B00E000234FF0FF3505FA04F45A
+S315080221F021EA0401994005FA03F322EA0303194383
+S31508022200002805DB0901C9B2064B195430BC7047D0
+S3150802221000F00F000901C9B2034B1954F6E700BFD3
+S3150802222000ED00E000E400E014ED00E00138B0F152
+S31508022230807F0AD2064B5860064AF02182F823109C
+S315080222400020986007221A6070470120704700BF75
+S3150802225010E000E000ED00E0042805D0054A136806
+S3150802226023F0040313607047024A136843F0040319
+S315080222701360704710E000E0704708B5FFF7FCFFEF
+S3150802228008BD0000F0B583B000233AE0092400E057
+S315080222900024B4403C4302356E4E46F825406E4C47
+S315080222A02568D44304EA05064F6817F4803F01D02F
+S315080222B042EA0506684D2E606E6804EA06054F680E
+S315080222C017F4003F01D042EA0605634E75604FF0E7
+S315080222D0B0452D6804EA05064F6817F4801F01D039
+S315080222E042EA05064FF0B0452E606D682C404E68EE
+S315080222F016F4001F01D042EA05044FF0B0425460BA
+S3150802230001330A6832FA03F400F0A28001249C40E1
+S315080223102240F5D04D686E1E112D18BF012E01D927
+S31508022320122D12D186685F000325BD4026EA0506EE
+S31508022330CD68BD4035438560466826EA04064D6881
+S31508022340C5F300149C4034434460C6685F00032505
+S31508022350BD40EC4326408D68BD403543C5604D6897
+S31508022360122D18BF022D13D1DE08083650F826E0C2
+S3150802237003F007054FEA850C0F2505FA0CF52EEA38
+S31508022380050E0D6905FA0CF545EA0E0540F82650C4
+S31508022390056825404C6804F00304BC402C430460DD
+S315080223A04C6814F0805FABD02C4CD4F8F45045F04E
+S315080223B00205C4F8F450D4F8F44004F00204019477
+S315080223C0019C9D08AE1C234C54F8267003F00304A6
+S315080223D0A6000F24B44027EA0407214CA0423FF482
+S315080223E057AF04F58064A04222D004F58064A04267
+S315080223F020D004F58064A0421ED004F58064A04271
+S315080224001CD004F58064A0421AD004F58064A04268
+S3150802241018D004F58064A04216D004F58064A04260
+S3150802242014D004F58064A0423FF430AF0A2430E7A2
+S3150802243001242EE702242CE703242AE7042428E7AA
+S31508022440052426E7062424E7072422E7082420E7AA
+S3150802245003B0F0BD0004005880000058004402583A
+S31508022460000002580AB18161704709048161704708
+S3150802247070470000000000002DE9F04387B00446CB
+S31508022480016883680269134342691343C2691343A5
+S31508022490426E13430868874A02401A430A60226852
+S315080224A0536823F44053E1680B435360A1692268D9
+S315080224B0814B9A4201D0236A194390687F4B0340A5
+S315080224C00B4393602268D36A23F00F03616A0B43B6
+S315080224D0D36223687A4A93421FD07A4A934259D0E2
+S315080224E0794A934270D0794A934200F08780784AB3
+S315080224F0934200F09D80774A934200F0B380764A71
+S31508022500934200F0F180754A934200F004816A4AC8
+S31508022510934200F0178180252DE1714A526D02F02F
+S315080225203802282A34D8DFE812F0290033003300AB
+S315080225303300330033003300330025013300330000
+S31508022540330033003300330033002B0033003300EB
+S31508022550330033003300330033002D0033003300D9
+S31508022560330033003300330033002F0033003300C7
+S315080225703300330033003300330031000125FAE01B
+S315080225800825F8E01025F6E02025F4E04025F2E0DB
+S315080225908025F0E0524A526D02F00702052A11D848
+S315080225A0DFE812F00600370108000A000C000E00E8
+S315080225B00025E0E00825DEE01025DCE02025DAE04B
+S315080225C04025D8E08025D6E0454A526D02F007023A
+S315080225D0052A11D8DFE812F006001F0108000A00D2
+S315080225E00C000E000025C6E00825C4E01025C2E04E
+S315080225F02025C0E04025BEE08025BCE0384A526D61
+S3150802260002F00702052A11D8DFE812F006000701D0
+S3150802261008000A000C000E000025ACE00825AAE016
+S315080226201025A8E02025A6E04025A4E08025A2E002
+S315080226302B4A526D02F00702052A11D8DFE812F07A
+S315080226400600EF0008000A000C000E00002592E0C2
+S31508022650082590E010258EE020258CE040258AE0AA
+S31508022660802588E01E4A526D02F03802282A39D897
+S31508022670DFE802F01538383838383838D738383875
+S3150802268038383838173838383838383819383838FA
+S31508022690383838381B383838383838381D00012564
+S315080226A069E0082567E0102565E0202563E04025F6
+S315080226B061E000BFF369FFCF000C0058FFF4FF1179
+S315080226C0001001400044004000480040004C004011
+S315080226D0005000400014014000780040007C004091
+S315080226E000440258802546E0A04A526D02F00702CD
+S315080226F0052A0ED8DFE802F003970507090B00251D
+S3150802270039E0082537E0102535E0202533E0402555
+S3150802271031E080252FE0954A526D02F00702052A1C
+S315080227200ED8DFE802F003820507090B002522E02E
+S31508022730082520E010251EE020251CE040251AE089
+S31508022740802518E002F50E32926D02F00702052A7C
+S315080227500ED8DFE802F0036C0507090B02250AE02A
+S31508022760082508E0102506E0202504E0402502E0B9
+S31508022770802500E004257E4A93425AD0E369B3F5E0
+S31508022780004F00F03E85402D01F2CB81DFE815F0BF
+S3150802279093070A08C909C9094808C909C909C90913
+S315080227A08808C909C909C909C909C909C909C909CB
+S315080227B0C808C909C909C909C909C909C909C9097B
+S315080227C0C909C909C909C909C909C909C909C90969
+S315080227D04809C909C909C909C909C909C909C909DA
+S315080227E0C909C909C909C909C909C909C909C90949
+S315080227F0C909C909C909C909C909C909C909C90939
+S31508022800C909C909C909C909C909C909C909C90928
+S3150802281084090425AFE70425ADE70425ABE70425BB
+S31508022820A9E70425A7E70425A5E70425A3E70425C0
+S31508022830A1E7082D00F0BD800BD9202D00F04F81AD
+S31508022840402D00F06A81102D00F0EC80012000F086
+S3150802285064BF022D2ED0042D29D103A8FEF770F9E4
+S315080228600498636A002B00F08C80012B00F08D809F
+S31508022870022B00F08C80032B00F08B80042B00F0D7
+S315080228808A80052B00F08980062B00F08880072BAA
+S3150802289000F08780082B00F08680092B00F08580DF
+S315080228A00A2B00F084800B2B68D001236AE00120F2
+S315080228B000F033BFFEF732F9636AD3B1012B42D077
+S315080228C0022B42D0032B42D0042B42D0052B42D0F6
+S315080228D0062B42D0072B42D0082B42D0092B42D0D6
+S315080228E00A2B49D00B2B01D0012303E04FF4807346
+S315080228F000E00123B0FBF3F0002801F015816668B9
+S3150802290006EB4603834201F21181B0EB063F01F260
+S315080229100F81082D00F0548240F26C81202D00F0C0
+S315080229206F83402D00F0D183102D00F0A282012082
+S315080229300023A3F540710F4A914201F2FB802268F7
+S31508022940D36000F0EABE0223D4E70423D2E70623C3
+S31508022950D0E70823CEE70A23CCE70C23CAE71023DD
+S31508022960C8E72023C6E74023C4E700BF004402584D
+S31508022970000C0058FFFC0F008023BBE74FF480735E
+S3150802298000E00123B0FBF3F0B6E70223FAE70423DB
+S31508022990F8E70623F6E70823F4E70A23F2E70C2307
+S315080229A0F0E71023EEE72023ECE74023EAE780234B
+S315080229B0E8E76846FEF7C2F90198636AD3B1012BC4
+S315080229C01CD0022B1CD0032B1CD0042B1CD0052B8D
+S315080229D01CD0062B1CD0072B1CD0082B1CD0092B6D
+S315080229E01CD00A2B1CD00B2B01D0012303E04FF479
+S315080229F0807300E00123B0FBF3F07DE70223FAE7D8
+S31508022A000423F8E70623F6E70823F4E70A23F2E79E
+S31508022A100C23F0E71023EEE72023ECE74023EAE74E
+S31508022A208023E8E7A94B1B6813F0200F3AD0A74B7F
+S31508022A301B68C3F3C103A648D840636AD3B1012B06
+S31508022A401CD0022B1CD0032B1CD0042B1CD0052B0C
+S31508022A501CD0062B1CD0072B1CD0082B1CD0092BEC
+S31508022A601CD00A2B1CD00B2B01D0012303E04FF4F8
+S31508022A70807300E00123B0FBF3F03DE70223FAE797
+S31508022A800423F8E70623F6E70823F4E70A23F2E71E
+S31508022A900C23F0E71023EEE72023ECE74023EAE7CE
+S31508022AA08023E8E7636A002B55D0012B55D0022B09
+S31508022AB055D0032B55D0042B55D0052B55D0062BB4
+S31508022AC055D0072B55D0082B55D0092B55D00A2B94
+S31508022AD055D00B2B01D07E480EE77E480CE7636A79
+S31508022AE0002B4ED0012B4ED0022B4ED0032B4ED0AC
+S31508022AF0042B4ED0052B4ED0062B4ED0072B4ED08C
+S31508022B00082B4ED0092B4ED00A2B4FD00B2B01D0B7
+S31508022B107148F1E643F60950EEE6636A002B48D09F
+S31508022B20012B49D0022B4AD0032B4BD0042B4CD075
+S31508022B30052B4DD0062B4ED0072B4FD0082B50D045
+S31508022B40092B51D00A2B52D00B2B02D04FF400403E
+S31508022B50D2E68020D0E65E48CEE66048CCE66048FB
+S31508022B60CAE66048C8E66048C6E66048C4E6604801
+S31508022B70C2E65948C0E65F48BEE65F48BCE65F481B
+S31508022B80BAE65548B8E65B48B6E65B48B4E65C483A
+S31508022B90B2E65A48B0E65B48AEE65B48ACE64D4854
+S31508022BA0AAE65A48A8E64FF22440A5E647F61220B6
+S31508022BB0A2E64FF400409FE64FF480409CE64FF4AD
+S31508022BC0005099E641F2555096E64FF4805093E646
+S31508022BD040F6CC4090E640F6AA208DE64FF4006017
+S31508022BE08AE64FF4806087E64FF4007084E64FF475
+S31508022BF0807081E6022D2FD0042D2AD103A8FDF775
+S31508022C009FFF0498636A002B00F0A480012B00F052
+S31508022C10B980022B00F0B980032B00F0B980042B8F
+S31508022C2000F0B980052B00F0B980062B00F0B980B8
+S31508022C30072B00F0B980082B00F0B980092B00F0A9
+S31508022C40B9800A2B00F0B9800B2B7FD00122002312
+S31508022C5082E0012000236CE6FDF760FF636AE3B1B8
+S31508022C60012B55D0022B56D0032B57D0042B58D004
+S31508022C70052B59D0062B5AD0072B5BD0082B5CD0D4
+S31508022C80092B5DD00A2B5ED00B2B02D00122002322
+S31508022C9005E04FF48072002301E00122002300219F
+S31508022CA0FDF71EFB0F0247EA106706026268500824
+S31508022CB000252B4616EB000847F10009404649460F
+S31508022CC0FDF70EFB0346284633E600BF00440258CA
+S31508022CD00090D00390D0030000093D000048E801A7
+S31508022CE00024F400AAC2A20000127A0000A8610019
+S31508022CF05561510080841E0040420F0020A1070042
+S31508022D002A2C0A00801A06001516050048E8010052
+S31508022D1002220023C3E704220023C0E70622002377
+S31508022D20BDE708220023BAE70A220023B7E70C22E6
+S31508022D300023B4E710220023B1E720220023AEE7DE
+S31508022D4040220023ABE780220023A8E74FF48072D3
+S31508022D50002301E0012200230021FDF7C1FA0F0238
+S31508022D6047EA106706026268500800252B4616EBEA
+S31508022D70000847F1000940464946FDF7B1FA0346FD
+S31508022D802846D6E502220023E6E704220023E3E7E3
+S31508022D9006220023E0E708220023DDE70A220023B1
+S31508022DA0DAE70C220023D7E710220023D4E72022F1
+S31508022DB00023D1E740220023CEE780220023CBE777
+S31508022DC06846FDF7BBFF0198636AE3B1012B32D06F
+S31508022DD0022B33D0032B34D0042B35D0052B36D017
+S31508022DE0062B37D0072B38D0082B39D0092B3AD0E7
+S31508022DF00A2B3BD00B2B02D00122002305E04FF40D
+S31508022E008072002301E0012200230021FDF768FAFF
+S31508022E100F0247EA106706026268500800252B4629
+S31508022E2016EB000847F1000940464946FDF758FAED
+S31508022E30034628467DE502220023E6E7042200230C
+S31508022E40E3E706220023E0E708220023DDE70A2259
+S31508022E500023DAE70C220023D7E710220023D4E75F
+S31508022E6020220023D1E740220023CEE78022002336
+S31508022E70CBE7C54B1B6813F0200F5CD0C24B1B680F
+S31508022E80C3F3C103C148D840636AE3B1012B34D006
+S31508022E90022B35D0032B36D0042B37D0052B38D04E
+S31508022EA0062B39D0072B3AD0082B3BD0092B3CD01E
+S31508022EB00A2B3DD00B2B02D00122002305E04FF44A
+S31508022EC08072002301E0012200230021FDF708FA9F
+S31508022ED04FEA012949EA10694FEA002870080025D5
+S31508022EE032462B4618EB000649F1000730463946AA
+S31508022EF0FDF7F6F9034628461BE502220023E4E716
+S31508022F0004220023E1E706220023DEE70822002343
+S31508022F10DBE70A220023D8E70C220023D5E7102292
+S31508022F200023D2E720220023CFE740220023CCE762
+S31508022F3080220023C9E7636AFBB1012B2ED0022B3C
+S31508022F4031D0032B34D0042B37D0052B3AD0062B9D
+S31508022F503DD0072B40D0082B43D0092B46D00A2B4D
+S31508022F6049D00B2B04D0DFF828824FF0030908E07A
+S31508022F70DFF818824FF0000903E0DFF814824FF0F9
+S31508022F8003097708002532462B4618EB070049F154
+S31508022F900001FDF7A5F903462846CAE4DFF8F481DD
+S31508022FA04FF00109EDE7DFF8F0814FF00009E8E795
+S31508022FB00FF2B419D9E90089E3E7DFF8E0814FF0A7
+S31508022FC00009DEE7DFF8D8814FF00009D9E70FF2EA
+S31508022FD0A019D9E90089D4E7DFF8C8814FF00009BA
+S31508022FE0CFE7DFF8C4814FF00009CAE7DFF8BC81F2
+S31508022FF04FF00009C5E7DFF8B8814FF00009C0E7CE
+S31508023000636AFBB1012B2ED0022B31D0032B34D0AD
+S31508023010042B37D0052B3AD0062B3DD0072B40D0B0
+S31508023020082B43D0092B46D00A2B49D00B2B04D0A8
+S31508023030DFF870814FF0000908E0DFF878814FF079
+S31508023040000903E0DFF85C814FF0000977080025E4
+S3150802305032462B4618EB070049F10001FDF740F905
+S315080230600346284665E4DFF840814FF00009EDE79C
+S31508023070DFF838814FF00009E8E70FF2FC09D9E9D1
+S315080230800089E3E7DFF828814FF00009DEE7DFF879
+S3150802309028814FF00009D9E70FF2E409D9E9008936
+S315080230A0D4E7DFF8E8804FF00009CFE7DFF80C81B4
+S315080230B04FF00009CAE7DFF808814FF00009C5E7B3
+S315080230C0DFF800814FF00009C0E7636A03B3012BFA
+S315080230D030D0022B33D0032B36D0042B39D0052B14
+S315080230E03CD0062B74D0072B77D0082B7AD0092B25
+S315080230F07DD00A2B00F080800B2B04D04FF40008F9
+S315080231004FF0000908E04FF400484FF0000903E0C9
+S315080231104FF400084FF000097708002532462B467F
+S3150802312018EB070049F10001FDF7DAF803462846CD
+S31508023130FFF7FFBB4FF480084FF00009ECE74FF4A6
+S3150802314000184FF00009E7E7DFF87C804FF0000926
+S31508023150E2E74FF480184FF00009DDE7DFF86C80EC
+S315080231604FF00009D8E700BF00AAC2A2000000007B
+S315080231700055615100000000002A2C0A00000000D8
+S315080231800015160500000000004402580090D003FE
+S31508023190000090D0000048E8000024F40000127AEB
+S315080231A00000A8610000093D0080841E0040420F0D
+S315080231B00020A10700093D0000801A060048E80120
+S315080231C00024F40000127A000055150000CC0C0009
+S315080231D0DFF8B0854FF000099EE74FF400284FF05C
+S315080231E0000999E74FF480284FF0000994E74FF455
+S315080231F000384FF000098FE74FF480384FF0000986
+S315080232008AE7402D00F25482DFE815F041008F006C
+S3150802321052025202CE005202520252020F015202C8
+S3150802322052025202520252025202520250015202F1
+S3150802323052025202520252025202520252025202DE
+S31508023240520252025202520252025202D101520250
+S3150802325052025202520252025202520252025202BE
+S3150802326052025202520252025202520252025202AE
+S31508023270520252025202520252025202520252029E
+S315080232805202520252025202520252020C02FEF733
+S3150802329065FF636AD3B1012B33D0022B33D0032BDC
+S315080232A033D0042B33D0052B33D0062B33D0072B40
+S315080232B033D0082B33D0092B33D00A2B33D00B2B20
+S315080232C001D0012303E04FF4807300E00123B0FB31
+S315080232D0F3F06268530803EB4003B3FBF2F39BB2C5
+S315080232E00020A3F110014FF6EF72914200F22484F6
+S315080232F09AB222F00F02C3F3420313432268D36041
+S315080233000BE20223E3E70423E1E70623DFE70823C8
+S31508023310DDE70A23DBE70C23D9E71023D7E72023C7
+S31508023320D5E74023D3E78023D1E7FEF729FF636A6F
+S31508023330D3B1012B24D0022B24D0032B24D0042B67
+S3150802334024D0052B24D0062B24D0072B24D0082BD7
+S3150802335024D0092B24D00A2B24D00B2B01D00123ED
+S3150802336003E04FF4807300E00123B0FBF3F06268D8
+S31508023370530803EB4003B3FBF2F39BB20020B0E71A
+S315080233800223F2E70423F0E70623EEE70823ECE735
+S315080233900A23EAE70C23E8E71023E6E72023E4E713
+S315080233A04023E2E78023E0E703A8FDF7C9FB049B75
+S315080233B0626AD2B1012A24D0022A24D0032A24D04E
+S315080233C0042A24D0052A24D0062A24D0072A24D05F
+S315080233D0082A24D0092A24D00A2A24D00B2A01D062
+S315080233E0012203E04FF4807200E00122B3FBF2F2FD
+S315080233F061684B0803EB4203B3FBF1F39BB200206F
+S315080234006FE70222F2E70422F0E70622EEE7082235
+S31508023410ECE70A22EAE70C22E8E71022E6E720228E
+S31508023420E4E74022E2E78022E0E76846FDF786FC09
+S31508023430019B626AD2B1012A24D0022A24D0032A25
+S3150802344024D0042A24D0052A24D0062A24D0072ADE
+S3150802345024D0082A24D0092A24D00A2A24D00B2ABE
+S3150802346001D0012203E04FF4807200E00122B3FB8F
+S31508023470F2F261684B0803EB4203B3FBF1F39BB22A
+S3150802348000202EE70222F2E70422F0E70622EEE700
+S315080234900822ECE70A22EAE70C22E8E71022E6E726
+S315080234A02022E4E74022E2E78022E0E7A34B1B68FA
+S315080234B013F0200F42D0A14B1A68C2F3C102A04BE7
+S315080234C0D340626AD2B1012A24D0022A24D0032A1E
+S315080234D024D0042A24D0052A24D0062A24D0072A4E
+S315080234E024D0082A24D0092A24D00A2A24D00B2A2E
+S315080234F001D0012203E04FF4807200E00122B3FBFF
+S31508023500F2F261684B0803EB4203B3FBF1F39BB299
+S315080235100020E6E60222F2E70422F0E70622EEE7B8
+S315080235200822ECE70A22EAE70C22E8E71022E6E795
+S315080235302022E4E74022E2E78022E0E7636ACBB191
+S31508023540012B20D0022B20D0032B20D0042B20D0F5
+S31508023550052B20D0062B20D0072B20D0082B20D0D5
+S31508023560092B20D00A2B20D00B2B01D0754B02E059
+S31508023570754B00E0734B626803EB5203B3FBF2F33D
+S315080235809BB20020ADE66E4BF5E7704BF3E7704B46
+S31508023590F1E7704BEFE7704BEDE7704BEBE7704BDB
+S315080235A0E9E7704BE7E7704BE5E7704BE3E7636AD9
+S315080235B0D3B1012B21D0022B21D0032B21D0042BEE
+S315080235C021D0052B21D0062B21D0072B21D0082B61
+S315080235D021D0092B21D00A2B21D00B2B01D0604BED
+S315080235E003E047F6122300E05D4B626803EB5203E1
+S315080235F0B3FBF2F39BB2002073E65A4BF5E75A4B3C
+S31508023600F3E75B4BF1E7594BEFE75A4BEDE75A4BBA
+S31508023610EBE74D4BE9E7594BE7E7594BE5E74FF23D
+S315080236202443E2E7636ADBB1012B23D0022B24D0C1
+S31508023630032B25D0042B26D0052B27D0062B28D0E2
+S31508023640072B29D0082B2AD0092B2BD00A2B2CD0B2
+S315080236500B2B02D04FF4803304E04FF4807301E061
+S315080236604FF48033626803EB5203B3FBF2F39BB267
+S31508023670002036E64FF40043F4E74FF48043F1E7BF
+S3150802368042F6AA23EEE74FF40053EBE741F6981306
+S31508023690E8E741F25453E5E74FF48053E2E74FF483
+S315080236A00063DFE74FF48063DCE74FF40073D9E782
+S315080236B00120002315E6FEF751FD636AD3B1012BFB
+S315080236C036D0022B36D0032B36D0042B5CD0052BF2
+S315080236D05CD0062B5CD0072B5CD0082B5CD0092B60
+S315080236E05CD00A2B5CD00B2B01D0012303E04FF4EC
+S315080236F0807300E00123B0FBF3F3626803EB520325
+S31508023700B3FBF2F39BB20020A3F110014FF6EF725E
+S31508023710914200F213822268D3600123A4F86A3028
+S31508023720A4F868300023E366236707B0BDE8F08390
+S315080237300223E0E70423DEE70623DCE70044025817
+S315080237400090D0030020A10720A107000048E80145
+S31508023750548545010024F4000050C300AAC2A20001
+S3150802376000127A0000093D0080841E0040420F00C4
+S315080237705458140000350C002A2C0A0090D0030075
+S3150802378048E8010000AA0A000823B4E70A23B2E7B8
+S315080237900C23B0E71023AEE72023ACE74023AAE7C1
+S315080237A08023A8E7FEF7ECFC636AD3B1012B23D08A
+S315080237B0022B23D0032B23D0042B23D0052B23D073
+S315080237C0062B23D0072B23D0082B23D0092B23D053
+S315080237D00A2B23D00B2B01D0012303E04FF480736D
+S315080237E000E00123B0FBF3F3626803EB5203B3FB79
+S315080237F0F2F39BB2002087E70223F3E70423F1E7FB
+S315080238000623EFE70823EDE70A23EBE70C23E9E7AC
+S315080238101023E7E72023E5E74023E3E78023E1E7F0
+S3150802382003A8FDF78DF9049B626AD2B1012A23D057
+S31508023830022A23D0032A23D0042A23D0052A23D0F6
+S31508023840062A23D0072A23D0082A23D0092A23D0D6
+S315080238500A2A23D00B2A01D0012203E04FF48072F0
+S3150802386000E00122B3FBF2F3626803EB5203B3FBF7
+S31508023870F2F39BB2002047E70222F3E70422F1E7BC
+S315080238800622EFE70822EDE70A22EBE70C22E9E730
+S315080238901022E7E72022E5E74022E3E78022E1E774
+S315080238A06846FDF74BFA019B626AD2B1012A23D018
+S315080238B0022A23D0032A23D0042A23D0052A23D076
+S315080238C0062A23D0072A23D0082A23D0092A23D056
+S315080238D00A2A23D00B2A01D0012203E04FF4807270
+S315080238E000E00122B3FBF2F3626803EB5203B3FB77
+S315080238F0F2F39BB2002007E70222F3E70422F1E77C
+S315080239000622EFE70822EDE70A22EBE70C22E9E7AF
+S315080239101022E7E72022E5E74022E3E78022E1E7F3
+S31508023920874B1B6813F0200F41D0854B1A68C2F3E8
+S31508023930C102844BD340626AD2B1012A23D0022A39
+S3150802394023D0032A23D0042A23D0052A23D0062AE1
+S3150802395023D0072A23D0082A23D0092A23D00A2AC1
+S3150802396023D00B2A01D0012203E04FF4807200E033
+S315080239700122B3FBF2F3626803EB5203B3FBF2F3E1
+S315080239809BB20020C0E60222F3E70422F1E70622F0
+S31508023990EFE70822EDE70A22EBE70C22E9E7102215
+S315080239A0E7E72022E5E74022E3E78022E1E7636AC8
+S315080239B0CBB1012B20D0022B20D0032B20D0042BF5
+S315080239C020D0052B20D0062B20D0072B20D0082B61
+S315080239D020D0092B20D00A2B20D00B2B01D0594BF3
+S315080239E002E0594B00E0574B626803EB5203B3FB04
+S315080239F0F2F39BB2002087E6544BF5E7544BF3E704
+S31508023A00544BF1E7544BEFE7544BEDE7544BEBE7D6
+S31508023A10544BE9E7544BE7E7544BE5E7544BE3E7E6
+S31508023A20636AD3B1012B21D0022B21D0032B21D0DB
+S31508023A30042B21D0052B21D0062B21D0072B21D0F0
+S31508023A40082B21D0092B21D00A2B22D00B2B01D0EF
+S31508023A50444B03E043F6095300E0424B626803EB2A
+S31508023A605203B3FBF2F39BB200204DE63E4BF5E759
+S31508023A703E4BF3E73F4BF1E73D4BEFE73E4BEDE7B6
+S31508023A803E4BEBE7304BE9E73D4BE7E74FF2244382
+S31508023A90E4E747F61223E1E7636AD3B1012B22D0A2
+S31508023AA0022B23D0032B24D0042B25D0052B26D07A
+S31508023AB0062B27D0072B28D0082B29D0092B2AD04A
+S31508023AC00A2B2BD00B2B02D04FF4004303E08023A2
+S31508023AD001E04FF40043626803EB5203B3FBF2F3CF
+S31508023AE09BB2002010E64FF48043F4E74FF40053EC
+S31508023AF0F1E741F25553EEE74FF48053EBE740F610
+S31508023B00CC43E8E740F6AA23E5E74FF40063E2E789
+S31508023B104FF48063DFE74FF40073DCE74FF48073FA
+S31508023B20D9E701200023EFE50020F6E50120F4E5B8
+S31508023B300120F2E50120F0E50120EEE50120ECE5A1
+S31508023B40004402580090D00390D003000048E801D0
+S31508023B500024F400AAC2A20000127A0000A861009A
+S31508023B605561510000093D0080841E0040420F0045
+S31508023B7020A107002A2C0A00801A0600151605003D
+S31508023B8048E80100836A13F0010F06D002685368F9
+S31508023B9023F40033C16A0B435360836A13F0020F9E
+S31508023BA006D00268536823F48033016B0B435360D3
+S31508023BB0836A13F0040F06D00268536823F480233D
+S31508023BC0416B0B435360836A13F0080F06D00268F1
+S31508023BD0536823F40043816B0B435360836A13F0E3
+S31508023BE0100F06D00268936823F48053C16B0B4307
+S31508023BF09360836A13F0200F06D00268936823F451
+S31508023C000053016C0B439360836A13F0400F0AD08A
+S31508023C100268536823F48013416C0B435360436C68
+S31508023C20B3F5801F0BD0836A13F0800F06D00268A3
+S31508023C30536823F40023C16C0B4353607047026830
+S31508023C40536823F4C003816C0B435360EBE72DE9F9
+S31508023C50F04104460F4616469846069D2368DB69D8
+S31508023C6037EA03030CBF01230023B3423FD1B5F160
+S31508023C70FF3FF3D0FCF746FFA0EB0800A84222D884
+S31508023C800DB323681A6812F0040FE7D0DA6912F442
+S31508023C90006FE3D04FF400621A622268136823F4B5
+S31508023CA0D07313602268936823F00103936020237C
+S31508023CB0C4F88030C4F88430C4F88830002384F805
+S31508023CC07C30032014E02268136823F4D07313604F
+S31508023CD02268936823F0010393602023C4F8803096
+S31508023CE0C4F88430002384F87C30032000E00020E6
+S31508023CF0BDE8F0812DE9F04383B01E46D0F8843042
+S31508023D00202B40F0828004460D469046B2FA82F392
+S31508023D105B09002908BF0123002B7AD190F87C3071
+S31508023D20012B78D0012380F87C300023C0F8883034
+S31508023D302223C0F88430FCF7E5FE0746A4F85C8027
+S31508023D40A4F85E80A368B3F5805F06D0A3B922699A
+S31508023D5072B9FF22A4F8602014E0226922B940F25F
+S31508023D60FF12A4F860200DE0FF22A4F8602009E003
+S31508023D707F22A4F8602005E0B3F1805F0AD0002212
+S31508023D80A4F86020B4F86080B3F5805F0CD04FF0D9
+S31508023D9000091DE022691AB97F22A4F86020F1E71A
+S31508023DA03F22A4F86020EDE7236913B14FF000091A
+S31508023DB00EE0A94600250BE023685B6A08EA0303BE
+S31508023DC029F8023BB4F85E30013B9BB2A4F85E3098
+S31508023DD0B4F85E309BB28BB100963B460022202196
+S31508023DE02046FFF734FFC0B9002DE5D023685A6A8A
+S31508023DF05FFA88F3134005F8013BE3E72023C4F88A
+S31508023E008430002084F87C0000E0022003B0BDE87C
+S31508023E10F0830120FAE70220F8E70320F6E730B537
+S31508023E2083B004460023C0F88830FCF76BFE0546CB
+S31508023E3023681B6813F0080F0ED123681B6813F05A
+S31508023E40040F17D12023C4F88030C4F88430002028
+S31508023E5084F87C0003B030BD6FF07E4300930346BE
+S31508023E6000224FF400112046FFF7F1FE0028E4D0A5
+S31508023E700320EFE76FF07E4300932B4600224FF4B0
+S31508023E8080012046FFF7E3FE0028DBD00320E1E7A6
+S31508023E9078B310B50446D0F880300BB32423C4F89F
+S31508023EA080302268136823F0010313602046FEF768
+S31508023EB0E3FA012813D0A36ABBB92268536823F42C
+S31508023EC0904353602268936823F02A03936022681A
+S31508023ED0136843F0010313602046FFF7A0FF10BDE5
+S31508023EE080F87C30FEF7C4FAD8E72046FFF74AFE88
+S31508023EF0E3E701207047000008B5FCF7C1FC094B4F
+S31508023F001868094BA3FB00308009FEF78FF90420D5
+S31508023F10FEF7A2F9002211464FF0FF30FEF754F9D8
+S31508023F2008BD00BF2C040020D34D621008B5FCF76B
+S31508023F30E9FD08BD08B5FCF7D9FDFEF79EF908BDEF
+S31508023F4008B5002280210248FEF78CFA08BD00BF98
+S31508023F500004025810B5FFF7E9FF0E4B1B68C31A97
+S31508023F60B3F5FA7F0CD304460B4B1B784BB90122E7
+S31508023F70094B1A7080210948FEF774FA054B1C6032
+S31508023F8010BD0022044B1A7080210448FEF76AFA13
+S31508023F90F4E700BF5C04002058040020000402581D
+S31508023FA0014A024B9A6070470000020800ED00E0E1
+S31508023FB000B59DB04C22002109A8FCF737FB202248
+S31508023FC0002101A8FCF732FB0220FDF741FB002382
+S31508023FD00093254B9A6942F440429A619B6903F41D
+S31508023FE040430093214BDA6A42F00102DA62DB6A45
+S31508023FF003F001030093009B1B4B9B6913F4005FBC
+S31508024000FAD0012309934FF4A0230A9302231293A9
+S315080240101393042214924FF4F07115911693179282
+S315080240201893199200231A931B9309A8FDF73AFBD2
+S3150802403000B1FEE73F230193032302930023039370
+S31508024040082304934023059306934FF4806207924C
+S31508024050089304210DEB0100FDF714FF00B1FEE7FA
+S315080240601DB05DF804FB00BF004802580004005862
+S3150802407008B5FFF795FFFCF70BFDFFF799FFFFF76A
+S315080240803BFFFFF75DFF08BD08B5FFF7F1FF00F03C
+S3150802409055F9FFF75FFF00F0DBF9FAE7F0B58DB0E7
+S315080240A04D4BD3F8F42042F00202C3F8F420D3F8B9
+S315080240B0F42002F002020192019AD3F8E02042F0BB
+S315080240C00202C3F8E020D3F8E02002F002020292CC
+S315080240D0029AD3F8E02042F00402C3F8E020D3F8AB
+S315080240E0E02002F004020392039AD3F8E02042F099
+S315080240F00802C3F8E020D3F8E02002F0080204928E
+S31508024100049AD3F8E82042F48022C3F8E820D3F8C8
+S31508024110E82002F480220592059AD3F8EC2042F4AC
+S315080241208072C3F8EC20D3F8EC3003F4807306935C
+S31508024130069B0320FEF736F8002211466FF00B00A5
+S31508024140FEF742F8002211466FF00A00FEF73CF825
+S31508024150002211466FF00900FEF736F800221146D2
+S315080241606FF00400FEF730F8002211466FF00300E4
+S31508024170FEF72AF8002211466FF00100FEF724F82E
+S31508024180002211464FF0FF30FEF71EF880230793F0
+S3150802419001230893002409940A94104D07A9284676
+S315080241A0FEF770F84FF440770797022608960994A7
+S315080241B00A9407230B9307A90948FEF763F807979A
+S315080241C0089609940A9409230B9307A92846FEF729
+S315080241D059F80DB0F0BD00BF004402580004025859
+S315080241E0000C0258F0B4002401E00134E4B2112CA8
+S315080241F020D8124D15F8147005EB440595F801C040
+S3150802420007EB0C0606FB00064FF4FA55B5FBF6F566
+S3150802421006FB05F5B5F5FA5FE7D1B5FBF6F60E80AE
+S31508024220013EB6B2B6F5007FDFD2177083F800C03A
+S31508024230012000E00020F0BC704700BF00450208DC
+S3150802424008B50948094B03604FF4614343600023EC
+S315080242508360C36003610C2242618361C3610362A6
+S315080242608362FFF715FE08BD0005002000480040DE
+S3150802427070B58CB00025ADF82E508DF82D508DF8FE
+S315080242802C500BAB0DF12D020DF12E014FF4FA70E5
+S31508024290FFF7A8FF204C214B2360A560E5600126A5
+S315080242A026746574A574BDF82E306361A6619DF8FF
+S315080242B02D30E3619DF82C3023626662A662E662BF
+S315080242C026636563A663E563266404236364A564BB
+S315080242D0E36425656365A565E56525666566A36682
+S315080242E02046FCF717FF039504950596069640F2B5
+S315080242F0676307930893099503A92046FDF754F8BF
+S3150802430000963346022211462046FDF790F82046CB
+S31508024310FDF7A9F80CB070BD6004002000A00040AB
+S3150802432008B50023012201460348FFF7E3FC08B15A
+S31508024330002008BD0120FCE70005002008B5FFF7AC
+S315080243407FFFFFF795FF08BDBFF34F8F0549CA6880
+S3150802435002F4E062044B1343CB60BFF34F8F00BFF6
+S31508024360FDE700BF00ED00E00400FA0508B5214BA1
+S315080243701B78B3B92048FFF7D3FF012800D008BD40
+S315080243801D4B1B78013BDBB23F2BF8D8FFF7CEFD5E
+S315080243901A4B1860174B01221A70194B00221A7011
+S315080243A0EDE7174B1B78013313481844FFF7B8FF9C
+S315080243B0012813D1124A13780133DBB213700E4A5D
+S315080243C012789342DBD10B4A002111700A4A5278BD
+S315080243D0FF2AD4D1022BD2D1FFF7B6FFFFF7A6FDEB
+S315080243E0064B1B6864339842C9D9024B00221A70DD
+S315080243F0C5E700BFCD0500208C050020D0050020AA
+S31508024400CE05002000B58DB040211048FDF712F9FF
+S3150802441010B90DB05DF804FB6B4602AA40210B48A1
+S31508024420FDF73CF80028F4D1029A40F267639A42F3
+S31508024430EFD1039B002BECD19DF816209DF8003096
+S31508024440FF2BE6D1022AE4D1FFF77EFF60040020A3
+S3150802445008B5FFF78BFFFFF7D5FF08BD0A4491425F
+S3150802446000F1FF3300D1704710B511F8014B03F87C
+S31508024470014F9142F9D110BDF8B500BFF8BC08BC8E
+S315080244809E467047F8B500BFF8BC08BC9E46704702
+S31508024490000000000000000000000000000000000C
+S315080244A000000000010000000200000003000000F6
+S315080244B004000000000000000500000000000000E3
+S315080244C000000000000000000600000000000000D6
+S315080244D000000000000000000700000000000020A5
+S315080244E0000000000102030401020304060708098A
+S315080244F00001020304050607080C101418203040B0
+S3150802450005020602060307030803090309040A0447
+S315080245100B040C040C050D050E050F050F061006F7
+S309080245201007100858
+S30D08024524ECBDFF7F0100000057
+S30D0802452CCD060208C5020208C9
+S30908024534A1020208C6
+S3150802453800000000EC02002054030020BC030020FF
+S315080245480000000000000000000000000000000053
+S315080245580000000000000000000000000000000043
+S315080245680000000000000000000000000000000033
+S315080245780000000000000000000000000000000023
+S315080245880000000000000000000000000000000013
+S315080245980000000000000000000000000000000003
+S315080245A800000000000000000000000000000000F3
+S315080245B800000000000000000000000000000000E3
+S315080245C800000000000000000000000000000000D3
+S315080245D800000000000000000100000000000000C2
+S315080245E80E33CDAB34126DE6ECDE05000B00000087
+S315080245F800000000000000000000000000000000A3
+S315080246080000000000000000000000000000000092
+S315080246180000000000000000000000000000000082
+S315080246280000000000000000000000000000000072
+S315080246380000000000000000000000000000000062
+S315080246480000000000000000000000000000000052
+S315080246580000000000000000000000000000000042
+S315080246680000000000000000000000000000000032
+S315080246780000000000000000000000000000000022
+S315080246880000000000000000000000000000000012
+S315080246980000000000000000000000000000000002
+S315080246A800000000000000000000000000000000F2
+S315080246B800000000000000000000000000000000E2
+S315080246C800000000000000000000000000000000D2
+S315080246D800000000000000000000000000000000C2
+S315080246E800000000000000000000000000000000B2
+S315080246F800000000000000000000000000000000A2
+S315080247080000000000000000000000000000000091
+S315080247180000000000000000000000000000000081
+S315080247280000000000000000000000000000000071
+S315080247380000000000000000000000000000000061
+S315080247480000000000000000000000000000000051
+S315080247580000000000000000000000000000000041
+S315080247680000000000000000000000000000000031
+S315080247780000000000000000000000000000000021
+S315080247880000000000000000000000000000000011
+S315080247980000000000000000000000000000000001
+S315080247A800000000000000000000000000000000F1
+S315080247B800000000000000000000000000000000E1
+S315080247C800000000000000000000000000000000D1
+S315080247D800000000000000000000000000000000C1
+S315080247E800000000000000000000000000000000B1
+S315080247F800000000000000000000000000000000A1
+S315080248080000000000000000000000000000000090
+S315080248180000000000000000000000000000000080
+S315080248280000000000000000000000000000000070
+S315080248380000000000000000000000000000000060
+S315080248480000000000000000000000000000000050
+S315080248580000000000000000000000000000000040
+S315080248680000000000000000000000000000000030
+S315080248780000000000000000000000000000000020
+S315080248880000000000000000000000000000000010
+S315080248980000000000000000000000000000000000
+S315080248A800000000000000000000000000000000F0
+S315080248B800000000000000000000000000000000E0
+S315080248C800000000000000000000000000000000D0
+S315080248D800000000000000000000000000000000C0
+S315080248E800000000000000000000000000000000B0
+S315080248F800000000000000000000000000000000A0
+S31508024908000000000000000000000000000000008F
+S31508024918000000000000000000000000000000007F
+S31508024928000000000000000000000000000000006F
+S31508024938000000000000000000000000000000005F
+S31508024948000000000000000000000000000000004F
+S315080249580000000000000000D40500200090D003E3
+S311080249680090D0030100000010000000BF
 S705080207B138
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_GCC/Prog/boot.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_GCC/Prog/boot.c
index 72519e2a..148acf64 100644
--- a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_GCC/Prog/boot.c
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_GCC/Prog/boot.c
@@ -376,12 +376,12 @@ static void BootComCanInit(void)
     canHandle.Init.StdFiltersNbr = 0;
     canHandle.Init.ExtFiltersNbr = 1;
   }
-  /* only one reception buffer is needed. reception FIFO 0 and 1 are not used. */
-  canHandle.Init.RxFifo0ElmtsNbr = 0;
+  /* only reception FIFO 0 is used. */
+  canHandle.Init.RxFifo0ElmtsNbr = 1;
   canHandle.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_8;
   canHandle.Init.RxFifo1ElmtsNbr = 0;
   canHandle.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_8;
-  canHandle.Init.RxBuffersNbr = 1;
+  canHandle.Init.RxBuffersNbr = 0;
   canHandle.Init.RxBufferSize = FDCAN_DATA_BYTES_8;
   /* no transmit buffer is needed. transmit FIFO is not used. */
   canHandle.Init.TxEventsNbr = 0;
@@ -411,12 +411,16 @@ static void BootComCanInit(void)
   }
   filterConfig.FilterIndex = 0;
   filterConfig.FilterType = FDCAN_FILTER_DUAL;
-  filterConfig.FilterConfig = FDCAN_FILTER_TO_RXBUFFER;
+  filterConfig.FilterConfig = FDCAN_FILTER_TO_RXFIFO0;
   filterConfig.FilterID1 = rxMsgId;
   filterConfig.FilterID2 = rxMsgId;
   filterConfig.RxBufferIndex = 0;
   (void)HAL_FDCAN_ConfigFilter(&canHandle, &filterConfig);
 
+  /* configure global filter to reject all non-matching frames. */
+  HAL_FDCAN_ConfigGlobalFilter(&canHandle, FDCAN_REJECT, FDCAN_REJECT, 
+                               FDCAN_REJECT_REMOTE, FDCAN_REJECT_REMOTE);
+  
   /* start the CAN peripheral. no need to evaluate the return value as there is nothing
    * we can do about a faulty CAN controller. */
   (void)HAL_FDCAN_Start(&canHandle);
@@ -440,10 +444,10 @@ static void BootComCanCheckActivationRequest(void)
 
 
   /* poll for received CAN messages that await processing. */
-  if (HAL_FDCAN_IsRxBufferMessageAvailable(&canHandle, FDCAN_RX_BUFFER0) > 0)
+  if (HAL_FDCAN_GetRxFifoFillLevel(&canHandle, FDCAN_RX_FIFO0) > 0)
   {
     /* attempt to read the newly received CAN message from its buffer. */
-    rxStatus = HAL_FDCAN_GetRxMessage(&canHandle, FDCAN_RX_BUFFER0, &rxMsgHeader,
+    rxStatus = HAL_FDCAN_GetRxMessage(&canHandle, FDCAN_RX_FIFO0, &rxMsgHeader,
                                       rxMsgData);
   }
 
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/bin/openblt_stm32h743.out b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/bin/openblt_stm32h743.out
new file mode 100644
index 00000000..eb469d59
Binary files /dev/null and b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/bin/openblt_stm32h743.out differ
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/bin/openblt_stm32h743.srec b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/bin/openblt_stm32h743.srec
new file mode 100644
index 00000000..1954c9b6
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/bin/openblt_stm32h743.srec
@@ -0,0 +1,1819 @@
+S01900006F70656E626C745F73746D3332683734332E73726563F9
+S31508000000C81800206D6E0008996E00089D6E0008DD
+S31508000010A16E0008A56E0008A96E00080000000081
+S31508000020000000000000000000000000AD6E00089F
+S31508000030B16E000800000000B56E0008B96E000831
+S31508000040BD6E0008C16E0008C56E0008C96E0008BE
+S31508000050CD6E0008D16E0008D56E0008D96E00086E
+S31508000060DD6E0008E16E0008E56E0008E96E00081E
+S31508000070ED6E0008F16E0008F56E0008F96E0008CE
+S31508000080FD6E0008016F0008056F0008096F00087B
+S315080000900D6F0008116F0008156F0008196F00082A
+S315080000A01D6F0008216F0008256F0008296F0008DA
+S315080000B02D6F0008316F0008356F0008396F00088A
+S315080000C03D6F0008416F0008456F0008496F00083A
+S315080000D04D6F0008516F0008556F0008596F0008EA
+S315080000E05D6F0008616F000800000000656F00087A
+S315080000F0696F00086D6F0008716F0008756F00085A
+S31508000100796F00087D6F0008816F0008856F000809
+S31508000110896F00088D6F0008916F0008956F0008B9
+S31508000120996F00089D6F0008A16F0008A56F000869
+S31508000130A96F0008AD6F0008B16F0008B56F000819
+S3150800014000000000000000000000000000000000A1
+S31508000150B96F0008BD6F0008C16F0008C56F0008B9
+S31508000160C96F0008CD6F0008D16F0008D56F000869
+S31508000170D96F0008DD6F0008E16F00080000000075
+S31508000180E56F0008E96F0008ED6F0008F16F0008D9
+S31508000190F56F0008F96F0008FD6F00080170000888
+S315080001A005700008097000080D7000081170000835
+S315080001B015700008197000081D70000821700008E5
+S315080001C025700008297000082D7000083170000895
+S315080001D035700008397000083D7000084170000845
+S315080001E045700008497000084D70000851700008F5
+S315080001F055700008597000085D70000861700008A5
+S3150800020065700008697000086D7000087170000854
+S3150800021075700008797000087D7000088170000804
+S3150800022085700008897000088D70000800000000BD
+S315080002309170000895700008000000009970000889
+S315080002409D700008A1700008A5700008A970000834
+S31508000250AD700008B1700008B5700008B9700008E4
+S31508000260BD700008C1700008C5700008C970000894
+S31508000270CD700008D1700008D57000080000000095
+S31508000280D9700008DD700008E17000080000000061
+S3150800029000000000E57000080EB418B504000898C0
+S315080002A0012817D1A06B30F48030A063E168DFF82D
+S315080002B0A4080140E160E06830F44010E0600F985F
+S315080002C0012803D1E06850F48010E060200000F0B7
+S315080002D005FF12E0E06850F04000E060200000F002
+S315080002E0FDFE0C99002904D1A16B51F48031A1635C
+S315080002F003E0A16B31F48031A1630699012907D186
+S31508000300A16851F00601A160A16851F02001A16021
+S31508000310C0B212BC5DF810FB1300DBB2022B52D13F
+S31508000320DFF834288A1ADFF834389A4201D20F21C6
+S315080003304FE0DFF82C288A1ADFF828389A4201D2CB
+S315080003400E2146E0DFF820288A1ADFF820389A427C
+S3150800035001D20D213DE0DFF818288A1ADFF8143893
+S315080003609A4201D20C2134E0DFF80C288A1ADFF809
+S315080003700C389A4201D20B212BE0DFF804288A1A9E
+S31508000380DFF800389A4201D20A2122E0DFF8F8277E
+S315080003908A1ADFF8F8379A4201D2092119E0DFF8FC
+S315080003A0F0278A1ADFF8EC379A4201D2082110E0C2
+S315080003B0DFF8E427891ADFF8E427914201D20721FA
+S315080003C007E0062105E0D2B2002A01D1092100E0A2
+S315080003D00921C26832F47052C260C268890211F4F7
+S315080003E070511143C16000207047816851F00101C6
+S315080003F081600020704781684908490081600020B3
+S31508000400704780B5C26832F0C042C2600A00D2B2F4
+S31508000410012A08D1C16851F00051C160322000F0AC
+S3150800042083FE002002BDC9B2002904D1C16851F07B
+S315080004308041C160F2E70120F4E70EB478B5040004
+S3150800044000252600002005E0002104EB8002C2F802
+S315080004500411401C0F28F7D30F98002814D116F55D
+S315080004600060406850F0020016F500614860A06B15
+S3150800047030F40010A063206850F040002060206827
+S3150800048050F08000206003E0A06B50F40010A063D9
+S31508000490002016F56061086016F50060006816F51C
+S315080004A0006108600A9801280CD10798002804D131
+S315080004B00021200000F0D5F808E00121200000F016
+S315080004C0D0F803E00321200000F0CBF8102120002B
+S315080004D000F0A7F8002800D00125200000F0B2F8A7
+S315080004E0002800D00125002016F5006108610020CB
+S315080004F016F500614861002016F50061C861002004
+S315080005001BE0002116EB401212F51062116006E09E
+S315080005105FF0904116EB401212F51062116016EB6F
+S31508000520401111F5106100220A6116EB401111F510
+S3150800053010614FF67F328A60401C0599884210D2B6
+S3150800054016EB401111F5106109680029D9D5002864
+S31508000550DED15FF0006116EB401212F510621160F1
+S31508000560DDE700201BE0002116EB401212F5306291
+S31508000570116006E05FF0904116EB401212F530620A
+S31508000580116016EB401111F5306100220A6116EB75
+S31508000590401111F530614FF67F328A60401C05998B
+S315080005A0884210D216EB401111F53061096800290E
+S315080005B0D9D50028DED15FF0006116EB401212F59E
+S315080005C030621160DDE716F50060006930F480706E
+S315080005D016F5006630610020A0617FF080406061FA
+S315080005E00898002803D1A06950F01000A061A169FD
+S315080005F0DFF81C0B0143A1610B98002803D0A06902
+S3150800060050F00800A0610F98012805D1A06940F0B4
+S31508000610804050F00400A0612800C0B272BC5DF8AA
+S3150800062010FB0022890151F020010161521CDFF8FC
+S31508000630E41A8A4204D201698906F7D40020704771
+S315080006400320FCE7002110220261491CDFF8C42AB6
+S31508000650914204D20269D206F7D4002070470320DB
+S31508000660FCE710F500621268C9B2114310F5006084
+S3150800067001600020704710F50060806810F00600E1
+S31508000680002801D1002006E0022801D0062801D161
+S31508000690022000E00F20C0B2704730B40A784B78C9
+S315080006A0012B2BD110F50063DB6901240D7815F0B9
+S315080006B00F05AC40A4B2234310F50064E36110EBC8
+S315080006C0421313F510631B681B0440D410EB421346
+S315080006D013F510631B688C686405640DC97854EAC1
+S315080006E0814454EA825444F0805454F40044234329
+S315080006F010EB421010F51060036028E010F5006357
+S31508000700DB6901240D7815F00F05AC4053EA044364
+S3150800071010F50064E36110EB421313F530631B68B0
+S315080007201B0414D410EB421313F530631B688C6852
+S315080007306405640DC97854EA814444F0805454F43D
+S315080007400044234310EB421010F53060036000208C
+S3150800075030BC704730B40A784B78012B28D1012376
+S3150800076010F50064E46B0D7815F00F0513FA05F51E
+S31508000770ADB2AC4310F50065EC6310F50064E469AE
+S31508000780097811F00F018B409BB234EA030310F588
+S315080007900061CB6110EB421111F510610B68DFF8AF
+S315080007A078190B4010EB421010F51060036026E034
+S315080007B0012310F50064E46B0D7815F00F0513FAA4
+S315080007C005F534EA054410F50065EC6310F5006498
+S315080007D0E469097811F00F018B4034EA034410F5F7
+S315080007E00061CC6110EB421111F530610B68DFF83E
+S315080007F02C190B4010EB421010F5306003600020F6
+S3150800080030BC7047F8B504000D784B78012B40F0E2
+S3150800081005814B69002B24D114EB451313F510639E
+S3150800082014EB451616F5106636696FF3DC461E613D
+S3150800083014EB451313F5106314EB451616F51066FD
+S31508000840366956F400261E6114EB451313F510633A
+S3150800085014EB451616F510663669F60CF6041E6195
+S315080008605AE014EB451313F5106314EB451616F509
+S3150800087010663669F60CF6041E6114EB451313F57B
+S31508000880106314EB451616F5106636696FF3DC46E9
+S315080008901E6114EB451616F5106614EB451313F591
+S315080008A010631F69D1F814C08B6813EB0C0CBCF1EC
+S315080008B0010C8B68BCFBF3F3DFF864C81CEAC34C75
+S315080008C05CEA0707376114EB451313F5106314EB5D
+S315080008D0451616F5106636694F697F037F0B3E434A
+S315080008E01E61CB78012B17D114EB451313F5106352
+S315080008F014EB451616F51066366936F0C0461E61C5
+S3150800090014EB451313F5106314EB451616F510662C
+S31508000910366956F000561E611300DBB2012B36D13C
+S315080009200869002805D014EB451010F510600A690F
+S315080009304261C87801281DD114F500608068C00599
+S315080009400CD414EB451010F51060006850F00050F8
+S3150800095014EB451111F5106108600BE014EB451016
+S3150800096010F51060006850F0805014EB451111F531
+S315080009701061086014EB451010F51060006850F01F
+S31508000980044014EB451414F510642060DFE014EB02
+S31508000990451313F510631B6853F0044314EB45160F
+S315080009A016F510663360CB78012B10D048690028FD
+S315080009B000F0CD8014F50060406B0122097811F033
+S315080009C00F018A40104314F500646063BFE014F514
+S315080009D000639B68DB050CD414EB451313F5106311
+S315080009E01B6853F0005314EB451414F51064236088
+S315080009F00BE014EB451313F510631B6853F0805393
+S31508000A0014EB451414F510642360D2B200924B69B6
+S31508000A109BB20A78C96800F0B1F998E014EB451062
+S31508000A2010F5306014EB451313F530631B69DB0CC6
+S31508000A30DB04036114EB451010F5306014EB451325
+S31508000A4013F530631B696FF3DC43036148690028BB
+S31508000A501AD114EB451010F5306014EB451313F555
+S31508000A6030631B698E687603760B3343036114EB98
+S31508000A70451010F5306014EB451313F530631B6908
+S31508000A8053F40023036129E04B698868C3185B1E89
+S31508000A908868B3FBF0F014EB451313F5306314EBD9
+S31508000AA0451616F5306636690700BFB2DFF870C618
+S31508000AB01CEAC74C5CEA06061E6114EB451313F5DF
+S31508000AC0306314EB451616F5306636698F6880B2C2
+S31508000AD000FB07F04003400B30431861D2B2012AED
+S31508000AE008D1C868002805D014EB451010F5306009
+S31508000AF0CA684261C87801281DD114F5006080686B
+S31508000B00C0050CD414EB451010F53060006850F0A1
+S31508000B10005014EB451111F5306108600BE014EB39
+S31508000B20451010F53060006850F0805014EB451100
+S31508000B3011F53061086014EB451010F53060006857
+S31508000B4050F0044014EB451414F53064206000207E
+S31508000B50F2BD0000BFFFBDFFC0ACD80000350C00D9
+S31508000B60C0E1E40040420F000024F400804F120068
+S31508000B708073060120D61300A0491A0160E3160007
+S31508000B80002D310140771B0040A44C01C091210083
+S31508000B9000366E012075380020ABA601E09C4100A6
+S31508000BA070B40B001C785978012940F09580596972
+S31508000BB0002924D110EB441111F5106110EB4415EE
+S31508000BC015F510652D696FF3DC450D6110EB4411C1
+S31508000BD011F5106110EB441515F510652D6955F4DE
+S31508000BE000250D6110EB441111F5106110EB441549
+S31508000BF015F510652D69ED0CED040D6137E010EB68
+S31508000C00441111F5106110EB441515F510652D69A1
+S31508000C10ED0CED040D6110EB441111F5106110EBAC
+S31508000C20441515F510652D696FF3DC450D61996856
+S31508000C305D69A94201D29968596110EB441111F511
+S31508000C40106110EB441515F510652D6955F400254E
+S31508000C500D6110EB441111F5106110EB441515F5F3
+S31508000C6010652D695E697603760B35430D61D2B240
+S31508000C70012A15D11969002905D010EB441111F57F
+S31508000C8010611A694A6110EB441111F5106109687F
+S31508000C9051F0044110EB441010F5106001606AE051
+S31508000CA010EB441111F51061096851F0044110EB7D
+S31508000CB0441212F510621160596900295BD010F5CB
+S31508000CC00061496B01221B7813F00F039A40114308
+S31508000CD010F5006041634EE010EB441111F53061E8
+S31508000CE010EB441515F530652D69ED0CED040D6115
+S31508000CF010EB441111F5306110EB441515F530650C
+S31508000D002D696FF3DC450D615969002901D0996891
+S31508000D10596110EB441111F5306110EB441515F5C6
+S31508000D2030652D6955F400250D6110EB441111F558
+S31508000D30306110EB441515F530652D699E6876030C
+S31508000D40760B35430D61D2B2012A08D1D96800293C
+S31508000D5005D010EB441111F53061DA684A6110EBE1
+S31508000D60441111F53061096851F0044110EB441043
+S31508000D7010F530600160002070BC7047F0B4049C28
+S31508000D80E4B2002C13D19BB2DB1C9B0800250CE0B7
+S31508000D900C0026681700FFB24FF4805404FB0707BF
+S31508000DA017F580573E60091D6D1C9D42F0D3002043
+S31508000DB0F0BC704730B492B2D21C9208002306E009
+S31508000DC010F5805424680D002C60091D5B1C9342A5
+S31508000DD0F6D3080030BC7047020008784978012924
+S31508000DE021D112EB401111F51061096800290DD4C3
+S31508000DF000280BD012EB401111F51061096831F08B
+S31508000E00804112EB401313F51063196012EB401181
+S31508000E1011F51061096851F4001112EB401212F530
+S31508000E201062116020E012EB401111F5306109687B
+S31508000E3000290DD400280BD012EB401111F53061B2
+S31508000E40096831F0804112EB401313F530631960DD
+S31508000E5012EB401111F53061096851F4001112EBDB
+S31508000E60401212F5306211600020704710B40A78FB
+S31508000E704B78012B1ED110EB421313F510631B6838
+S31508000E8033F4001310EB421414F510642360CB7886
+S31508000E90032B02D0C97802292AD110EB421111F589
+S31508000EA01061096851F0805110EB421010F510607E
+S31508000EB001601DE010EB421313F530631B6833F431
+S31508000EC0001310EB421414F530642360CB78032B1F
+S31508000ED002D0C97802290BD110EB421111F5306105
+S31508000EE0096851F0805110EB421010F5306001602E
+S31508000EF0002010BC704710B50400200000210CE04B
+S31508000F004FF67F3210EB411313F510639A6010EB1E
+S31508000F10411313F530639A60491C0F29F0D3002159
+S31508000F2010F500621161002110F50062516100217F
+S31508000F3010F50060C1612000FFF784FB0100C9B20B
+S31508000F40002901D0C0B20AE010212000FFF769FB92
+S31508000F500100C9B2002901D0C0B200E0C0B210BD7C
+S31508000F6010F50062126832F4FE6210F500631A602A
+S31508000F7010F500621268C9B2090111F4FE61114345
+S31508000F8010F5006001600020704780B510F500611B
+S31508000F90496831F0020110F500604160032000F055
+S31508000FA0C3F8002002BD80B510F50061496851F00C
+S31508000FB0020110F500604160032000F0B5F800203A
+S31508000FC002BD01004869896908407047010011F5AA
+S31508000FD00060806911F50061C9690840000C704716
+S31508000FE0010011F50060806911F50061C9690840C2
+S31508000FF080B270470200C9B212EB411010F530609A
+S31508001000806812F5006251690840704710B410F5FF
+S315080010100062126910F500635B6B11F00F04E34080
+S31508001020DB0113F080031A43C9B210EB411010F527
+S3150800103010608068104010BC7047406910F00100CD
+S31508001040704710F510610968C90AC90210F51062DF
+S31508001050116010F50061496851F4807110F500605F
+S3150800106041600020704710B40300006CDFF8B440FC
+S31508001070A04206D313F530600068002801D5002089
+S315080010802AE0002013F53064206113F5306000690A
+S3150800109050F4002013F53064206113F530600069C0
+S315080010A050F0180013F53064206113F530600069BC
+S315080010B050F0C04013F530642061C9B201290AD145
+S315080010C013F53060426113F53060006850F08020F7
+S315080010D013F530631860002010BC70470021491CC6
+S315080010E00C4A91420FD20369002BF8D500210369F7
+S315080010F053F001030361491C914206D20369DB07D9
+S31508001100F9D4002070470320FCE70320FAE7000023
+S3150800111000383C80410D0300007833EC0078F3EF8B
+S315080011200000F81F0B30544F38B5040000F044F89F
+S31508001130050014F1010F02D004480078241800F0C5
+S315080011403BF8401BA042FAD331BD00BFC1000020C6
+S3150800115080B500F00DF813481349086000201349BC
+S31508001160086005201249086000201249086001BD80
+S3150800117000200F49086000200B49086000200B4931
+S31508001180086070470A480068C00303D50948016823
+S31508001190491C0160704780B5FFF7F4FF05480068F1
+S315080011A002BD0000FF52070014E000E018E000E06E
+S315080011B010E000E0AC14002080B5FFF7ECFF02BD9C
+S315080011C038B58AB00400002C01D10120B6E02568A4
+S315080011D094F8BD03002805D1002084F8BC0320003C
+S315080011E000F06AFE032084F8BD03E86BC00501D44D
+S315080011F0002020612068FFF7FEF8211D83B06846AD
+S31508001200342200F077FE0EBC2068FFF745F8002868
+S3150800121004D0022084F8BD0301208FE00021206855
+S31508001220FFF7EFF8002130E01C200A00D2B2424353
+S315080012302244012382F83D300A00D2B242432244B6
+S3150800124082F83C100A00D2B2424322440B00DBB2B9
+S31508001250A2F842300A00D2B242432244002382F85E
+S315080012603F300A00D2B242432244002353640A00A4
+S31508001270D2B242432244002393640A00D2B200FB4E
+S3150800128002F0204400220265491C0800C0B26268C8
+S315080012909042C9D300212BE01C200A00D2B2424357
+S315080012A02244002382F8FD310A00D2B24243224486
+S315080012B082F8FC110A00D2B242432244002382F883
+S315080012C0FF310A00D2B2424322440023C2F8043254
+S315080012D00A00D2B2424322440023C2F808320A0066
+S315080012E0D2B200FB02F020440022C0F81022491CAA
+S315080012F00800C0B262689042CED3211D83B068460A
+S31508001300342200F0F7FD0EBC2068FFF796F8002897
+S3150800131004D0022084F8BD0301200FE0002084F8E1
+S315080013203800012084F8BD03606A012802D1200034
+S3150800133000F059FE2068FFF736FE00200BB030BDDE
+S3150800134010B50400002C01D101200CE0032084F81C
+S31508001350BD03200000F029F8200000F058FE002008
+S3150800136084F8BD03002010BD10B50400206894F869
+S31508001370BC13012901D1022016E0012184F8BC130F
+S31508001380A16A012906D1A169012903D0816B51F40B
+S31508001390803181632068FFF7F8FD2068FFF725F89C
+S315080013A0002084F8BC03002010BD10B5040094F892
+S315080013B0BC03012801D1022016E0012084F8BC03F1
+S315080013C02068FFF718F82068FFF795FD002804D075
+S315080013D0002084F8BC03012006E02068FFF7E3FD3F
+S315080013E0002084F8BC03002010BD2DE9F04106005A
+S315080013F035682F003068FFF720FE002840F0778216
+S315080014003068FFF7DEFD002800F071823068FFF7CC
+S31508001410D8FD800705D53068406910F002003168AC
+S3150800142048613068FFF7CDFDC0063FD53068806952
+S3150800143030F0100031688861D5F8208018F00F0167
+S315080014401C20414306EB010010F5FE74C8F3434027
+S31508001450022816D147F6F07018EA000F20D0C8F314
+S315080014600A1292B2E1682800FFF7A4FCE068C8F304
+S315080014700A110844E060A169C8F30A104118A1617D
+S315080014800EE0C8F3434006280AD1082216F5717102
+S315080014902800FFF78FFCA169C8F30A104118A1615B
+S315080014A03068806950F01000316888613068FFF74D
+S315080014B088FD000347D500253068FFF787FD04003F
+S315080014C03FE0E0073BD52900C9B23068FFF792FD37
+S315080014D080465FEAC87009D517EB451010F53060ED
+S315080014E0012181602900300000F017FC5FEA0870CE
+S315080014F009D517EB451010F53060082181602900E1
+S31508001500300000F0ADFC5FEAC86005D517EB451062
+S3150800151010F53060102181605FEA886005D517EB09
+S31508001520451010F53060202181605FEA884006D5B5
+S3150800153017EB451010F530604FF4005181606D1CB3
+S315080015406408002CBDD13068FFF73BFD400376D513
+S315080015503068FFF745FD040000256EE0E0076AD510
+S315080015602900C9B23068FFF751FD80465FEAC870A6
+S3150800157036D5012115F00F0011FA00F017F50061B4
+S31508001580496B31EA000017F50061486317EB45100F
+S3150800159010F5106001218160306901281BD11C20DB
+S315080015A000FB05F13144896C00FB05F23244526CAC
+S315080015B0114400FB05F232449164002D0BD100FB67
+S315080015C005F03044006D002805D116F57172012129
+S315080015D03068FFF748FD2900C9B2300000F02FFD3A
+S315080015E05FEA087005D517EB451010F5106008215D
+S315080015F081605FEAC86005D517EB451010F51060E5
+S31508001600102181605FEA486005D517EB451010F593
+S315080016101060402181605FEA887005D517EB451098
+S3150800162010F51060022181605FEA086003D5290081
+S31508001630300000F0FEFA6D1C6408002C8ED130686C
+S31508001640FFF7BFFC00281CD517F500604068400866
+S31508001650400017F50061486096F8F403012807D1A1
+S31508001660002086F8F4030021300000F0CFFC02E0E9
+S31508001670300000F02FFD3068406910F000403168F6
+S3150800168048613068FFF79DFC00050DD517F5006029
+S315080016908068C00702D5300000F001FD3068406957
+S315080016A010F40060316848613068FFF78AFC000171
+S315080016B01AD53068406910F000603168486196F8BC
+S315080016C0F40300280DD1012086F8F4033068406D34
+S315080016D0C0F38300C6F8F8030121300000F096FC39
+S315080016E002E0300000F0DBFC3068FFF76AFCC0045B
+S315080016F040F1938017F5006040684008400017F5F0
+S315080017000061486010213068FEF78BFF00203CE03E
+S315080017104FF67F3117EB401212F51062916017EB06
+S31508001720401212F51062126832F4001217EB4013D9
+S3150800173013F510631A6017EB401212F5106212685F
+S3150800174052F0006217EB401313F510631A6017EB9B
+S31508001750401212F53062916017EB401111F53061B5
+S31508001760096831F4001117EB401212F53062116066
+S3150800177017EB401111F53061096851F0006117EB5C
+S31508001780401212F530621160401C71688842BFD35E
+S3150800179017F50060C06950F0011017F50061C861BF
+S315080017A0306B002812D017F50060D0F8840050F08E
+S315080017B00B0017F50061C1F8840017F50060406C4E
+S315080017C050F00B0017F50061486411E017F500604A
+S315080017D0406940F4005050F02B0017F5006148614D
+S315080017E017F50060006950F00B0017F500610861F5
+S315080017F017F50060006830F4FE6017F5006738607A
+S3150800180016F571723169C9B23068FFF72CFC306879
+S31508001810406910F48050316848613068FFF7D1FBA1
+S31508001820800417D53068FFF70CFC3068FEF723FFF5
+S31508001830F06000F06CFE0100F268D2B23068FEF784
+S315080018406BFD300000F00FFC3068406910F4005062
+S31508001850316848613068FFF7B4FB000708D53000E7
+S3150800186000F0FBFB3068406910F0080031684861F9
+S315080018703068FFF7A6FBC0020AD50021C9B23000BE
+S3150800188000F038FC3068406910F48010316848610F
+S315080018903068FFF796FB80020AD50021C9B23000EE
+S315080018A000F021FC3068406910F400103168486186
+S315080018B03068FFF786FB400008D5300000F021FCB1
+S315080018C03068406910F08040316848613068FFF739
+S315080018D078FB40070BD530684468600702D53000AE
+S315080018E000F019FC30684068044330684460BDE87D
+S315080018F0F08110B50400206894F8BC13012901D1C1
+S31508001900022013E0012184F8BC13A16A012906D13B
+S31508001910A169012903D0816B51F480318163206864
+S31508001920FFF733FB002084F8BC03002010BD10B578
+S31508001930040094F8BC03012801D1022009E0012023
+S3150800194084F8BC032068FFF72EFB002084F8BC034C
+S31508001950002010BD10B5040094F8BC03012801D17D
+S3150800196002200CE0012084F8BC0384F83810C9B2C0
+S315080019702068FFF7F5FA002084F8BC03002010BDA4
+S3150800198070B5050000260800C0B200060CD50C008C
+S31508001990E4B214F00F041C20444305EB040010F1D4
+S315080019A03C04012060700BE00C00E4B214F00F0454
+S315080019B01C20444305EB040010F5FE7400206070FB
+S315080019C011F00F01217092B2A260E37060780028CE
+S315080019D001D02078E080DBB2022B01D100202071F3
+S315080019E095F8BC03012801D102200BE0012085F8F7
+S315080019F0BC0321002868FEF750FE002085F8BC03CA
+S31508001A003000C0B270BD10B504000800C0B20006B0
+S31508001A100BD50A00D2B212F00F021C20424304EB87
+S31508001A2002003C30012242700BE00A00D2B212F0EA
+S31508001A300F021C20424304EB020010F5FE70002240
+S31508001A40427011F00F01017094F8BC13012901D1FD
+S31508001A5002200AE0012184F8BC1301002068FEF781
+S31508001A6079FE002084F8BC03002010BD38B51C00A0
+S31508001A700D00EDB215F00F051C235D4300EB0503C1
+S31508001A8013F5FE73DA605C6100249C6100245C70C7
+S31508001A9011F00F041C700469012C00D11A6111F0B1
+S31508001AA00F0F06D10269D2B219000068FFF778F85D
+S31508001AB005E00269D2B219000068FEF7A3FE00200D
+S31508001AC032BDC9B211F00F011C2251430844D0F8A7
+S31508001AD01402704738B51C000D00EDB215F00F055D
+S31508001AE01C235D4300EB05033C33DA605C6100248C
+S31508001AF09C6101245C7011F00F041C700469012CB0
+S31508001B0000D11A6111F00F0F06D10269D2B219007D
+S31508001B100068FFF745F805E00269D2B219000068C7
+S31508001B20FEF770FE002032BD38B504000D0060686F
+S31508001B302900C9B211F00F01884201D2012039E00B
+S31508001B402800C0B200060CD52900C9B211F00F0151
+S31508001B501C20414304EB010010F13C0101204870B0
+S31508001B6009E02900C9B21C20414304EB010010F525
+S31508001B70FE71002048700120887015F00F0008706B
+S31508001B8094F8BC03012801D1022013E0012084F84F
+S31508001B90BC032068FFF720F915F00F0F06D114F5DE
+S31508001BA071722169C9B22068FFF75DFA002084F8CE
+S31508001BB0BC03002032BD10B5040060680A00D2B22A
+S31508001BC012F00F02904201D2012031E00800C0B2A3
+S31508001BD000060BD50A00D2B212F00F021C204243AF
+S31508001BE004EB02003C30012242700BE00A00D2B23C
+S31508001BF012F00F021C20424304EB020010F5FE709F
+S31508001C00002242700022827011F00F01017094F8D0
+S31508001C10BC13012901D102200AE0012184F8BC1372
+S31508001C2001002068FFF722F9002084F8BC03002091
+S31508001C3010BD2DE9FC4704000D00266837001C205E
+S31508001C4000FB05F0204410F13C08D8F81400D8F839
+S31508001C501810884201D201205DE0D8F81400D8F89F
+S31508001C601890B0EB0909D8F80800484501D2D8F809
+S31508001C70089019F103095FEA990926E0D8F81400D3
+S31508001C80D8F818A0B0EB0A0AD8F80800504501D2CF
+S31508001C90D8F808A01AF103095FEA99092069C0B2C1
+S31508001CA0009053469BB22A00D2B2D8F80C103000E6
+S31508001CB0FFF764F8D8F80C005044C8F80C00D8F8B8
+S31508001CC018001AEB000AC8F818A017EB451010F50B
+S31508001CD01060806980B2484509D3D8F81800D8F84A
+S31508001CE01410884203D2D8F814000028C6D1D8F8B0
+S31508001CF01800D8F8141088420CD3012015F00F05E7
+S31508001D0010FA05F517F50060406B30EA050517F57A
+S31508001D1000677D630020BDE8F68738B505000C002E
+S31508001D2029680800096C10EB441212F530629268B3
+S31508001D302B69012B62D113070ED55D4B9942C0F072
+S31508001D408D80110440F18A8010EB441010F5306044
+S31508001D504FF40041816081E0930606D510EB4410EC
+S31508001D6010F530602021816078E012F0280F75D1D7
+S31508001D704F4B994209D3110407D510EB441010F5BF
+S31508001D8030604FF40041816068E01C2101FB04F2D9
+S31508001D902A44D2F8042210EB441010F5306000698A
+S31508001DA04003400B121A01FB04F02844C0F8142221
+S31508001DB001FB04F02844D0F8080201FB04F22A4487
+S31508001DC0D2F80422104401FB04F22A44C2F808029D
+S31508001DD0002C0DD101FB04F105EB0100D0F810022F
+S31508001DE0002805D115F5717201212868FFF73BF91E
+S31508001DF02100C9B2280000F013F92FE02D4B9942B3
+S31508001E0017D1110407D510EB441010F530604FF4C4
+S31508001E100041816022E0910605D510EB441010F5CB
+S31508001E203060202181602100C9B2280000F0F8F84E
+S31508001E3014E0002C0DD11C2000FB04F02844D0F837
+S31508001E401002002805D115F5717200212868FFF7E0
+S31508001E500AF92100C9B2280000F0E2F8002032BDD4
+S31508001E6070B5040022681000156C10EB411212F5CB
+S31508001E70306292680E4EB54208D3120406D510EBAE
+S31508001E80411010F530604FF400418160200000F0E9
+S31508001E90BFF8B54208D32069012805D114F5717237
+S31508001EA001212068FFF7DFF8002070BD0000000060
+S31508001EB00B30544F0A31544F704730B4002513E0A5
+S31508001EC050F8042BD30744BFA9F101039A18091F38
+S31508001ED0042942F8045BFAD213468C0744BF1580DE
+S31508001EE09B1CC90748BF1D7050F8041B0029E7D181
+S31508001EF030BC7047103A07D330B4B1E83810103AFE
+S31508001F00A0E83810F9D230BC530724BFB1E808104E
+S31508001F10A0E8081044BF51F8043B40F8043BD20738
+S31508001F2024BF31F8022B20F8022B44BF0B7803702C
+S31508001F307047121F17D35B0009D151F8043B20F8EC
+S31508001F40023B1B0C121F20F8023BF6D20BE051F89D
+S31508001F50043B00F8013B1B0A20F8023B1B0C121F2E
+S31508001F6000F8013BF3D238BF121D521E24BF11F8E8
+S31508001F70013B00F8013BF8D87047000070B40368CD
+S31508001F805B6A0C00E4B2002C05D192B253EA024314
+S31508001F90006883621FE00468A46A13EB14430024F4
+S31508001FA009E005682600F6B205EB8605D5F8045162
+S31508001FB013EB1543641C2500EDB20E00F6B2761E2F
+S31508001FC0B542EED30068C9B200EB810092B253EA7B
+S31508001FD00243C0F80031002070BC704789B200681F
+S31508001FE041620020704701680122C0F8FC230022E4
+S31508001FF080F8F423886950F000608861486D40F0E5
+S31508002000805050F0030048650020704770477047BD
+S3150800201080B510F57171D0F8040400F00BFB01BD12
+S3150800202080B50B00DBB21C22534300EB0302D2F847
+S315080020300822C9B2D0F8040400F02EFB01BD80B511
+S315080020400B00DBB21C22534300EB0302926CC9B2AD
+S31508002050D0F8040400F073FB01BD80B5D0F8040481
+S3150800206000F035FC01BD38B504000125E0680028FC
+S3150800207001D1002508E0E068022801D1012503E026
+S315080020809121464800F045FC2900C9B2D4F8040459
+S3150800209000F007FCD4F8040400F0D3FB31BD10B5FA
+S315080020A00400D4F8040400F0FFFB206810F5606013
+S315080020B0006850F00100216811F560610860206A27
+S315080020C0002804D03648016851F00601016000F086
+S315080020D047FC10BD10B5040000F043FCD4F8040416
+S315080020E000F0EBFB10BD80B5C9B2D0F8040400F0CF
+S315080020F000FC01BD80B5C9B2D0F8040400F0F7FBB6
+S3150800210001BD10B50400012000F029FCD4F8040430
+S3150800211000F0F1FB10BD10B50400002000F01FFC14
+S31508002120D4F8040400F0E9FB10BD10B501780029C5
+S3150800213032D11C4CC4F80404C0F8C0421A482060C6
+S31508002140092060600220E060002020610220A06172
+S315080021500120E06100202062002060620020A06269
+S315080021600020E062002020632000FFF729F80028FD
+S3150800217004D04FF49371094800F0CBFB802120006E
+S31508002180FFF72CFF402200212000FFF7F7FE8022F0
+S3150800219001212000FFF7F2FE002010BD106B000899
+S315080021A010ED00E0C40000200000084080B50021C2
+S315080021B00021D0F8C002FFF7C3F8C0B200F09DF8BE
+S315080021C0C0B202BD80B500210021D0F8C002FFF7D9
+S315080021D0CBF8C0B200F091F8C0B202BD80B50021BC
+S315080021E00021D0F8C002FFF7E0F8C0B200F085F889
+S315080021F0C0B202BD10B51C00002300231300DBB2D9
+S31508002200220092B2C9B2D0F8C002FFF7B9FBC0B239
+S3150800221000F073F8C0B210BD80B500220022C9B222
+S31508002220D0F8C002FFF7EFFBC0B200F066F8C0B204
+S3150800223002BD80B500220022C9B2D0F8C002FFF75D
+S3150800224073FCC0B200F059F8C0B202BD80B50022D6
+S315080022500022C9B2D0F8C002FFF7ADFCC0B200F048
+S315080022604CF8C0B202BDD0F8C0220800C0B20006C1
+S3150800227009D5C9B211F07F011C20414302EB0100C8
+S3150800228090F83E0008E0C9B211F07F011C204143D6
+S3150800229002EB010090F8FE01704780B5002200228B
+S315080022A0C9B2D0F8C002FFF755FBC0B200F025F856
+S315080022B0C0B202BD10B5002400249BB2C9B2D0F842
+S315080022C0C002FFF707FCC0B200F017F8C0B210BD95
+S315080022D010B5002400249BB2C9B2D0F8C002FFF79B
+S315080022E0C5FBC0B200F009F8C0B210BD80B5C9B2CE
+S315080022F0D0F8C002FFF7E5FB02BD0021C0B20028F6
+S3150800230005D0022807D004D3032806D007E000200A
+S3150800231006E0022004E0012002E0022000E002209C
+S31508002320C0B27047DFF83002006810F038000028A5
+S3150800233006D0082813D0102814D0182815D0E4E0A1
+S31508002340DFF810120868800606D5DFF8100209685B
+S31508002350C1F3C101C84001E0DFF80002D6E0DFF8AA
+S315080023602002D3E0DFF81C02D0E0DFF800020268A2
+S3150800237012F003020068C0F30510DFF8F4110B68C9
+S3150800238013F00103DFF8F0110968C1F3CC014B43E0
+S3150800239000EE103AB8EE400A002800F0B480002A91
+S315080023A003D0022A66D048D381E0DFF8A8110A686C
+S315080023B0920625D5DFF8A4210968C1F3C101CA40F0
+S315080023C000EE902AF8EE600A01EE100AB8EE411AFD
+S315080023D0C0EE810ADFF89C010068C005C00D01EE59
+S315080023E0100AB8EE411ADFED571A80EE210A31EECF
+S315080023F0000AB7EE001A30EE010A60EE800A1BE00A
+S3150800240000EE900AF8EE600A9FED4F1AC1EE200A18
+S3150800241058480068C005C00D01EE100AB8EE411A0A
+S31508002420DFED481A80EE210A31EE000AB7EE001AEF
+S3150800243030EE010A60EE800A55E000EE900AF8EEEA
+S31508002440600A9FED421AC1EE200A4A480068C00594
+S31508002450C00D01EE100AB8EE411ADFED3A1A80EE09
+S31508002460210A31EE000AB7EE001A30EE010A60EED4
+S31508002470800A38E000EE900AF8EE600A9FED341AFA
+S31508002480C1EE200A3B480068C005C00D01EE100ADF
+S31508002490B8EE411ADFED2B1A80EE210A31EE000A5A
+S315080024A0B7EE001A30EE010A60EE800A1BE000EE75
+S315080024B0900AF8EE600A9FED251AC1EE200A2D480B
+S315080024C00068C005C00D01EE100AB8EE411ADFED2E
+S315080024D01D1A80EE210A31EE000AB7EE001A30EE18
+S315080024E0010A60EE800A23480068C0F34620401CB3
+S315080024F000EE100AB8EE400A80EE800ABCEEC00A6A
+S3150800250010EE100A00E0002000E01D48704780B574
+S31508002510FFF708FF1449194A0B68C3F30323D35C72
+S3150800252013F01F03D8400F4B096811F00F01515CD7
+S3150800253011F01F010200CA401A60094908601868AC
+S3150800254002BD0000000000460024744C0024744AB2
+S315080025500024F44A00440258104402580090D0035C
+S315080025600400002008000020184402582844025895
+S315080025702C44025830440258344402584C6E000821
+S3150800258000093D0000127A0080B5002801D102201A
+S3150800259011E0D0F8B432002B02D00023C0F8B432D0
+S315080025A0002901D0C0F8B012012180F89C120270EF
+S315080025B0FFF7BBFD002002BD10B50400012084F81A
+S315080025C09C026168C9B22000D4F8B42252689047C8
+S315080025D02000FFF703FE2000FFF7E8FD002010BDEE
+S315080025E00022002903D0C0F8B412002000E002201F
+S315080025F0C0B2704780B5FFF7E5FD002002BD002098
+S31508002600704710B50224D0F8B422002A07D0C9B200
+S31508002610D0F8B42212689047002800D10024200080
+S31508002620C0B210BD80B5C9B2D0F8B422526890477E
+S31508002630002002BD10B5040014F52A7000F01EFD36
+S315080026400120C4F89402B4F8AE02C4F8980294F8CB
+S31508002650A80210F01F00002803D002280DD006D3C8
+S3150800266011E014F52A71200000F07CF912E014F547
+S315080026702A71200000F0B3F90CE014F52A71200045
+S3150800268000F0E3F906E094F8A81211F080012000A2
+S31508002690FFF7CFFD002010BD10B5040010000A009A
+S315080026A0D2B2002A39D114F5AA72D4F894120329A1
+S315080026B027D11169D368994211D2D36811695B1A77
+S315080026C0D360D1681369994201D2D26800E01269D1
+S315080026D092B20100200000F03CFD002010BDD4F8A5
+S315080026E0B4020069002808D094F89C02032804D193
+S315080026F02000D4F8B41209698847200000F032FD9A
+S31508002700EBE7D4F894020528E7D10020C4F8940230
+S3150800271000212000FFF78DFDDFE7D4F8B4028069B9
+S3150800272000280AD094F89C02032806D1C9B22000D2
+S31508002730D4F8B42292699047CFE70220CEE710B5C5
+S31508002740040010000A00D2B2002A68D114F114025B
+S31508002750D4F8941202294AD11169D368994210D241
+S31508002760D36811695B1AD360D26892B2010020005F
+S3150800277000F0E6FC0023002200212000FFF7A8FD58
+S3150800278041E090681169B0FBF1F301FB13000028E2
+S3150800279017D190681169884213D39068D4F89812B3
+S315080027A088420ED200220021200000F0C9FC002039
+S315080027B0C4F898020023002200212000FFF788FDB4
+S315080027C021E0D4F8B402C068002808D094F89C0226
+S315080027D0032804D12000D4F8B412C9688847802198
+S315080027E02000FFF726FD200000F0C7FC0BE0D4F818
+S315080027F09402042803D0D4F89402002803D1802137
+S315080028002000FFF716FD94F8A002012805D1200044
+S31508002810FFF7F5FE002084F8A002002010BDD4F8CA
+S31508002820B402406900280AD094F89C02032806D10D
+S31508002830C9B22000D4F8B42252699047EDE70220C5
+S31508002840ECE710B504004023002200212000FFF722
+S31508002850D1FC0120C4F858014020C4F86401402383
+S31508002860002280212000FFF7C5FC0120A06140203E
+S315080028706062012084F89C020020C4F894020020BB
+S3150800288060600020C4F8A402D4F8B802002806D074
+S315080028906168C9B22000D4F8B42252689047002073
+S315080028A010BD01740020704790F89C1280F89D12A4
+S315080028B0042180F89C120020704790F89C12042985
+S315080028C003D190F89D1280F89C120020704780B5BD
+S315080028D090F89C12032908D1D0F8B412C9690029C6
+S315080028E003D0D0F8B412C9698847002002BD002079
+S315080028F07047002070470020704780B5012180F896
+S315080029009C124168C9B2D0F8B42252689047002098
+S3150800291002BD80B500F040FCFCE7000000690840F5
+S31508002920884201D1012000E00020704780B54FF4AD
+S3150800293000510548FFF7F2FF002801D0002002E009
+S3150800294000F055FC012002BD0008025880B564203D
+S3150800295000F02BFC01BD80B500F02AFC01BD7047D4
+S315080029607047704710B500240A7812F06002002AF2
+S3150800297008D0202A01D0402A2CD1D0F8B422926857
+S31508002980904729E04A78002A18D0012A1CD0032A41
+S3150800299017D0052A09D0062A04D0082A0BD0092AF6
+S315080029A006D014E000F077F913E000F074FA10E0AE
+S315080029B000F0A0FA0DE000F007FB0AE000F023FBA8
+S315080029C007E000F03FFB04E000F046FB01E000F002
+S315080029D069FB01E000F066FB2000C0B210BD38B507
+S315080029E004000D000020287810F06000002803D0AD
+S315080029F0202801D0402822D194F89C02401E0228A3
+S31508002A0018D82879022810D229002000D4F8B42230
+S31508002A10926890470100E88800280AD1C9B20029BF
+S31508002A2007D1200000F09EFB03E02900200000F0FB
+S31508002A3039FB03E02900200000F034FB03E02900FD
+S31508002A40200000F02FFB002032BD70B505000024E1
+S31508002A5088880A7812F06002002A0AD0202A02D052
+S31508002A60402A40F012812800D5F8B422926890478F
+S31508002A700EE10A7812F06002202A06D12800D5F85D
+S31508002A80B42292689047C0B204E14A78002A6CD012
+S31508002A90012A3AD0032A40F0F48095F89C22022AAB
+S31508002AA002D0032A16D02CE00200D2B2002A0DD09A
+S31508002AB00200D2B2802A09D00100C9B22800FFF765
+S31508002AC0B8FB80212800FFF7B4FB02E0280000F0DD
+S31508002AD0E9FA19E04A88002A0FD10200D2B2002A80
+S31508002AE00BD00200D2B2802A07D0C988002904D1A7
+S31508002AF00100C9B22800FFF79CFB280000F032FB52
+S31508002B0002E0280000F0CEFABEE095F89C22022AE0
+S31508002B1002D0032A16D024E00200D2B2002A0DD031
+S31508002B200200D2B2802A09D00100C9B22800FFF7F4
+S31508002B3080FB80212800FFF77CFB02E0280000F0DC
+S31508002B40B1FA11E0498800290AD110F07F0F04D0A4
+S31508002B500100C9B22800FFF779FB280000F002FB44
+S31508002B6002E0280000F09EFA8EE095F89C22022AE0
+S31508002B7002D0032A28D080E00200D2B2002A07D069
+S31508002B800200D2B2802A03D0280000F08BFA77E040
+S31508002B900100C9B2090608D5C0B210F07F00142199
+S31508002BA04843284410F1140107E0C0B210F07F0032
+S31508002BB014214843284410F5AA710020086002220F
+S31508002BC0280000F0ABFA5BE00200D2B212060ED57E
+S31508002BD00300DBB213F00F031422534305EB030281
+S31508002BE09269002A13D1280000F05CFA48E0030035
+S31508002BF0DBB213F00F031422534305EB0302D2F89A
+S31508002C005821002A03D1280000F04CFA38E00100C8
+S31508002C10C9B209060AD50200D2B212F07F021421FF
+S31508002C204A4305EB020111F1140609E00200D2B28B
+S31508002C3012F07F0214214A4305EB020111F5AA7628
+S31508002C400100C9B2002903D00100C9B2802902D106
+S31508002C50002030600BE00100C9B22800FFF703FB33
+S31508002C60002802D00120306001E0002030600222F6
+S31508002C703100280000F052FA02E0280000F012FAAB
+S31508002C8002E0280000F00EFA02E0280000F00AFA36
+S31508002C902000C0B270BDF8B505000E000020ADF8E2
+S31508002CA0000000270024708880B2000AC0B20128FC
+S31508002CB00AD0022810D0032823D0062800F0A580C1
+S31508002CC0072800F0B280C2E06946287CD5F8B02211
+S31508002CD0126890470700BFE0287C002808D168469C
+S31508002CE0D5F8B412896A884707000220787007E089
+S31508002CF06846D5F8B412C96A884707000220787072
+S31508002D00AAE0B078002808D002282CD018D30428C6
+S31508002D104FD03BD305285FD071E0D5F8B0024068A4
+S31508002D20002807D06946287CD5F8B0225268904713
+S31508002D30070004E03100280000F0B4F9641C63E0E1
+S31508002D40D5F8B0028068002807D06946287CD5F8EF
+S31508002D50B02292689047070004E03100280000F08E
+S31508002D60A1F9641C50E0D5F8B002C068002807D065
+S31508002D706946287CD5F8B022D2689047070004E057
+S31508002D803100280000F08EF9641C3DE0D5F8B00249
+S31508002D900069002807D06946287CD5F8B022126950
+S31508002DA09047070004E03100280000F07BF9641C16
+S31508002DB02AE0D5F8B0024069002807D06946287C81
+S31508002DC0D5F8B02252699047070004E03100280080
+S31508002DD000F068F9641C17E0D5F8B002806900288D
+S31508002DE007D06946287CD5F8B02292699047070033
+S31508002DF004E03100280000F055F9641C04E03100B5
+S31508002E00280000F04FF9641C26E0287C002806D12B
+S31508002E106846D5F8B412496B8847070004E03100C4
+S31508002E20280000F03FF9641C16E0287C002808D129
+S31508002E306846D5F8B412096B8847070007207870EA
+S31508002E4004E03100280000F02DF9641C04E031008C
+S31508002E50280000F027F9641CE4B2002C1AD1BDF84A
+S31508002E600000002810D0F08800280DD0BDF800001A
+S31508002E70F188884202D3F088ADF80000BDF800203A
+S31508002E803900280000F04AF9F088002802D1280005
+S31508002E9000F068F9F1BD38B505008888002825D105
+S31508002EA0C888002822D1488880281FD28C7814F038
+S31508002EB07F0495F89C02032803D1280000F0F2F855
+S31508002EC017E085F89E422100C9B22800FFF7E5F908
+S31508002ED0280000F047F9E4B2002C03D0022085F858
+S31508002EE09C0206E0012085F89C0202E0280000F01A
+S31508002EF0D9F831BD70B504000D00324E68883070BF
+S31508002F003078022804D32900200000F0CBF857E0D7
+S31508002F1094F89C02022802D003281BD048E0307897
+S31508002F20002813D030786060032084F89C0231783A
+S31508002F302000FFF766FB022804D12900200000F0D4
+S31508002F40B1F83DE0200000F00DF902E0200000F0A5
+S31508002F5009F935E0307800280CD1022084F89C0263
+S31508002F603078606031782000FFF75CFB200000F0C5
+S31508002F70F9F81CE030786168884215D06168C9B2F2
+S31508002F802000FFF74FFB3078606031782000FFF7AC
+S31508002F9038FB022804D12900200000F083F80FE04E
+S31508002FA0200000F0DFF802E0200000F0DBF807E080
+S31508002FB02900200000F076F831782000FFF732FB70
+S31508002FC070BD0000C014002080B5CA88012A02D04E
+S31508002FD000F068F816E090F89C22521E012A02D9E1
+S31508002FE0921E08D00CE000218160012210F1080130
+S31508002FF000F094F806E00122011D00F08FF801E0C8
+S3150800300000F050F801BD80B590F89C22521E022AA5
+S3150800301015D8CA88022A02D000F044F811E0012126
+S31508003020C160D0F8A412002903D0C16851F002018A
+S31508003030C160022210F10C0100F070F801E000F006
+S3150800304031F801BD80B54988012904D10121C0F8AC
+S31508003050A41200F087F801BD80B590F89C22521E94
+S31508003060022A08D84988012904D10021C0F8A412E7
+S3150800307000F078F801E000F015F801BD0A78027052
+S315080030804A7842708A78CB781B029A1842800A7965
+S315080030904B791B029A1882808A79C979090289189C
+S315080030A0C180704710B5040080212000FFF7C1F8E1
+S315080030B000212000FFF7BDF810BDF8B504000D008B
+S315080030C017000026002C1ED0200000F01DF8400036
+S315080030D0801C388038783100C9B26854761C0320C1
+S315080030E03100C9B26854761C0AE020783100C9B2AA
+S315080030F06854641C761C00203100C9B26854761CDA
+S3150800310020780028F1D1F1BD0200002001E0401C22
+S31508003110521C11780029FAD1C0B2704780B5130045
+S315080031200222C0F894221A0092B2C2611A0092B220
+S3150800313002629BB20A000021FFF7BCF8002002BD1C
+S3150800314080B513009BB20A000021FFF7B3F80020F0
+S3150800315002BD80B513009BB20A000021FFF7B8F83C
+S31508003160002002BD80B50421C0F894120023002275
+S315080031700021FFF79FF8002002BD80B50521C0F8A1
+S315080031809412002300220021FFF7A2F8002002BDB6
+S3150800319080B5FFF7DBFB01BD80B5FFF7DCFB01BDA2
+S315080031A08161704709048161704714490880704736
+S315080031B010B5FDF7F0FF124C2168884216D3114965
+S315080031C00878002806D10120087080210E48FFF7EC
+S315080031D0E7FF05E00020087080210B48FFF7E2FFB3
+S315080031E0FDF7D9FF054909884018206010BD80B54C
+S315080031F080210548FFF7D6FF01BD0000B81400205E
+S31508003200A4140020BB1400200004025878B593B01B
+S3150800321004006846DFF814164C22FEF76BFE002CF5
+S3150800322001D101205AE1DFF808562068A84203D1E7
+S31508003230206810F580706060A068B0F5407F206C4B
+S315080032400028A06C0028206D0028206E0028E06D5C
+S31508003250216E0818002894F89800002805D1002047
+S3150800326084F89900200000F049FC2068806930F055
+S31508003270100021688861FDF79FFF060020688069B5
+S3150800328000070FD5FDF798FF801B0B28F6D3D4F857
+S315080032909C0050F00100C4F89C00032084F89800B4
+S315080032A001201BE12068806950F0010021688861CF
+S315080032B0FDF782FF060020688069C0070FD4FDF776
+S315080032C07BFF801B0B28F6D3D4F89C0050F0010036
+S315080032D0C4F89C00032084F898000120FEE02068CA
+S315080032E0806950F0020021688861207C012806D197
+S315080032F02068806930F040002168886105E0206810
+S31508003300806950F0400021688861607C012806D1F8
+S315080033102068806950F480402168886105E020684B
+S31508003320806930F4804021688861A07C012806D134
+S315080033302068806930F480502168886105E020683B
+S31508003340806950F48050216888612068816931F469
+S315080033504071A0680143206881612068806930F067
+S31508003360A400216888612068006930F0100021688F
+S315080033700861E068012806D12068806950F00400D9
+S315080033802168886121E0E06800281ED0E0680228EC
+S3150800339015D02068806950F080002168886120680F
+S315080033A0006950F0100021680861E06803280CD114
+S315080033B02068806950F020002168886105E020684F
+S315080033C0806950F0200021688861A069401EE16983
+S315080033D0491E090251EA4061206A401E014360699C
+S315080033E0401E51EA00412068C161A068B0F5407FDF
+S315080033F00FD1A06A401EE16A491E50EA0120216BDE
+S31508003400491E50EA0110616A491E50EA01402168C6
+S31508003410C860206E002807D02068D0F8C010606EFB
+S3150800342001432068C0F8C010E06D216E0818002816
+S315080034300CD02068D0F8C810C908C9006846A26E22
+S3150800344050F8220001432068C0F8C810206C0028F4
+S315080034500CD02068D0F8BC10C908C9006846626C50
+S3150800346050F8220001432068C0F8BC10A06C002860
+S315080034700DD02068D0F8BC0030F070006946E26CC8
+S3150800348051F8221050EA01102168C1F8BC00206DDD
+S3150800349000280DD02068D0F8BC0030F4E0606946FA
+S315080034A0626D51F8221050EA01202168C1F8BC006B
+S315080034B02068A84205D16068806880088000616835
+S315080034C088600020C4F894000020C4F89C000120FD
+S315080034D084F89800200000F0C7F9C0B214B070BD97
+S315080034E010B490F898201300DBB2012B02D0D2B2A8
+S315080034F0022A3BD1CA68072A0A68002A1ED1CA6866
+S31508003500072ACA68072A09D10A69CB691B0253EA3E
+S3150800351002438A69134353F0605309E08A68CB680B
+S31508003520DB0653EA82730A6953EA02434A6913437C
+S31508003530C06E496810EB8100036015E0CA68072A67
+S31508003540CB680A6952EA4372CB68072B01D18B69AB
+S3150800355003E08C684B6953EA8473006F496810EB83
+S31508003560C1000260001D0360002006E0D0F89C1030
+S3150800357051F00201C0F89C10012010BC704710B42D
+S3150800358090F89840012C0BD1019C920052EA011246
+S3150800359052EA430222430068C0F88020002006E071
+S315080035A0D0F89C1051F00401C0F89C10012010BC02
+S315080035B0704790F8981001290DD1022180F89810CB
+S315080035C00168896949084900026891610021C0F8C3
+S315080035D09C10002006E0D0F89C1051F00401C0F8B9
+S315080035E09C100120704738B590F898504C68002C0C
+S315080035F0FFD02C00E4B2012C02D0EDB2022D27D167
+S3150800360093FAA3F4B4FA84F40568D5F8C050C5F360
+S315080036100545AC4207D3D0F89C1051F02001C0F8FC
+S315080036209C1001201BE00468D4F8CC401C4207D04B
+S31508003630D0F89C1051F04001C0F89C1001200EE013
+S3150800364093FAA3F3B3FA83F300F00BFA002006E02B
+S31508003650D0F89C1051F00201C0F89C10012032BD30
+S3150800366090F89820022A04D10068C0F8D0100020EB
+S3150800367006E0D0F89C1051F00801C0F89C10012013
+S315080036807047F0B4002590F89840E4B2022C40F058
+S31508003690C380402927D10468D4F8A04014F4FE0F4B
+S315080036A007D1D0F89C1051F02001C0F89C100120D9
+S315080036B0B9E00468D4F8A44014F07F0F07D1D0F815
+S315080036C09C1051F48071C0F89C100120ABE004688E
+S315080036D0D4F8A440C4F30525466F446C04FB05F4EE
+S315080036E016EB84063AE0412927D10468D4F8B0409D
+S315080036F014F4FE0F07D1D0F89C1051F02001C0F841
+S315080037009C1001208FE00468D4F8B44014F07F0FB1
+S3150800371007D1D0F89C1051F48071C0F89C10012094
+S3150800372081E00468D4F8B440C4F30525866FC46CF8
+S3150800373004FB05F416EB840610E0046DA14207D3DA
+S31508003740D0F89C1051F02001C0F89C1001206AE0C6
+S31508003750C66F446D04FB01F416EB8406346814F056
+S31508003760804454605468002C04D13468C4F38A44F5
+S31508003770146003E0346824F060441460346814F07C
+S3150800378000549460346814F000441461341D2668AB
+S31508003790B6B2D661266816F47026D660266816F480
+S315080037A080165661266816F4001696612668C6F3D2
+S315080037B0066616622668F60F5662241D002602E083
+S315080037C0A75D9F55761CDFF89C70D2F80CC05FEA9F
+S315080037D01C4C17F80C70BE42F2D3402903D100687E
+S315080037E0C0F8A85016E0412903D10068C0F8B850BF
+S315080037F010E0202906D2012212FA01F10068C0F869
+S31508003800981007E0012211F01F0112FA01F1006871
+S31508003810C0F89C10002006E0D0F89C1051F0080172
+S31508003820C0F89C100120F0BC70470000BC6B000873
+S3150800383000A000400068D0F8CC00084201D1002062
+S3150800384000E001207047402905D10068D0F8A4009F
+S3150800385010F07F0004E00068D0F8B40010F07F0094
+S31508003860704700002C6E000810B4436B9F4A01682D
+S31508003870D1F88410114051EA83010468C4F8841011
+S315080038800168D1F8841031F47F01846B51EA044150
+S315080038900468C4F88410816BCB180168D1F88810C5
+S315080038A0114051EA83010468C4F888100168D1F808
+S315080038B0881031F4FE01C46B51EA04410468C4F867
+S315080038C08810C16B13EB41030168D1F8A0101140B1
+S315080038D051EA83010468C4F8A0100168D1F8A01061
+S315080038E031F4FE01046C51EA04410468C4F8A010DE
+S315080038F0046C416C01FB04330168D1F8B010114027
+S3150800390051EA83010468C4F8B0100168D1F8B01010
+S3150800391031F4FE01846C51EA04410468C4F8B0101D
+S31508003920846CC16C01FB04330168D1F8AC101140FA
+S3150800393051EA83010468C4F8AC10046D416D01FBBB
+S3150800394004330168D1F8F010114051EA8301046884
+S31508003950C4F8F0100168D1F8F01031F47C11846DC8
+S3150800396051EA04410468C4F8F010816D13EB410371
+S315080039700168D1F8C0100A4052EA83020168C1F80A
+S31508003980C0200168D1F8C01031F47C11C26D51EA2B
+S3150800399002410268C2F8C0100168D1F8C01031F0BF
+S315080039A07C51026E51EA02610268C2F8C010416B8E
+S315080039B04F4A12EB8102C266C16E826B11EB82011D
+S315080039C00167016FC26B11EBC2014167426F036C5D
+S315080039D0416C4B4312EB83028267826F836CC16C26
+S315080039E04B4312EB8302C267C26F036D416D4B43B3
+S315080039F012EB8302C0F88020D0F88010826D11EB9C
+S31508003A00C201C0F88410D0F88420C36D816E4B4380
+S31508003A1012EB8302C0F88820D0F88820036E816EE6
+S31508003A204B4312EB8302C0F89020D0F89010314A2D
+S31508003A3091420AD3D0F89C1051F02001C0F89C108E
+S31508003A40032180F89810012009E0C16E02E00022E7
+S31508003A500A60091DD0F890209142F8D3002010BCC6
+S31508003A60704770B41C004B68002B06D10D698B6833
+S31508003A701D430B6855EA834506E00D698B681D43AF
+S31508003A800B681D4355F080450B6ACE6956EA0366F6
+S31508003A908B691E434B691E43CB681E43D0F884309E
+S31508003AA0806E444313EB84031D60181D0660031DD6
+S31508003AB0002412E002EB0400C07802EB0405AD789E
+S31508003AC02D0455EA006502EB0400407855EA002506
+S31508003AD0105D05431D601B1D241D0748CD682D0C70
+S31508003AE0405D8442E6D370BC704700000300FFFFC8
+S31508003AF000AC0040FDD300402C6E00087047000063
+S31508003B00DFF814070068400C10F001007047DFF872
+S31508003B1008070068800810F001007047DFF8F8060B
+S31508003B20006810F018007047DFF8EC060068000A15
+S31508003B3010F001007047DFF8E4060068400810F04E
+S31508003B4001007047DFF8D806006810F038007047A3
+S31508003B50DFF8D006006810F470607047DFF8C40616
+S31508003B60006810F00F007047DFF8BC06006810F018
+S31508003B7070007047DFF8B006006810F4E060704720
+S31508003B8000F0FF02DFF8A8168A1811680200120E64
+S31508003B9003001B0A13F01F039A4011400200120A81
+S31508003BA012F01F02D14050EA0140704780B5FFF776
+S31508003BB0E7FF02BDDFF87C06006810F003007047D7
+S31508003BC0DFF874060068400E10F001007047DFF851
+S31508003BD06C060068000C10F001007047DFF85C0600
+S31508003BE00068400C10F001007047DFF850060068C6
+S31508003BF0800C10F001007047DFF84006006810F0EE
+S31508003C0001007047DFF838060068C005C00D401C83
+S31508003C107047DFF820060068C0F305107047DFF824
+S31508003C2020060068C0F34620401C7047DFF81006DF
+S31508003C300068C0F30640401C7047DFF804060068B9
+S31508003C40C0F30660401C7047DFF808060068C0F33A
+S31508003C50CC007047DFF8E0050068C00E10F00100E0
+S31508003C607047DFF8D8050068C00C10F001007047EF
+S31508003C70DFF8C8050068000D10F001007047DFF88E
+S31508003C80BC050068400D10F001007047DFF8AC0570
+S31508003C900068000910F001007047DFF8BC050068ED
+S31508003CA0C005C00D401C7047DFF888050068C0F3E2
+S31508003CB005307047DFF8A0050068C0F34620401CB1
+S31508003CC07047DFF894050068C0F30640401C70474B
+S31508003CD0DFF884050068C0F30660401C7047DFF80B
+S31508003CE07C050068C0F3CC007047DFF84C05006817
+S31508003CF0400F10F001007047DFF840050068800D9E
+S31508003D0010F001007047DFF834050068C00D10F0A8
+S31508003D1001007047DFF824050068000E10F0010066
+S31508003D207047DFF818050068000A10F001007047B0
+S31508003D30DFF82C050068C005C00D401C7047DFF889
+S31508003D40F4040068C0F305507047DFF814050068EE
+S31508003D50C0F34620401C7047DFF804050068C0F32E
+S31508003D600640401C7047DFF8F8040068C0F3066098
+S31508003D70401C7047DFF8EC040068C0F3CC007047BD
+S31508003D8010B5DFF89444206850F001002060FFF772
+S31508003D90BEFE0028FBD00020DFF8841408602168E6
+S31508003DA0DFF8A00401402160FFF70AFF0028FBD1D5
+S31508003DB0FFF750FF0028FBD1FFF797FF0028FBD13C
+S31508003DC00020DFF8601408600020DFF85C14086043
+S31508003DD00020DFF858140860DFF86C04DFF8541484
+S31508003DE00860DFF86804DFF854140860DFF8600438
+S31508003DF0DFF84C1408600021DFF858241160DFF85A
+S31508003E00581408600021DFF854241160DFF85014B4
+S31508003E1008600020DFF84C140860206830F4802021
+S31508003E2020600020DFF840140860DFF840140A68B4
+S31508003E3040F2FF7002430A60DFF83404016851F467
+S31508003E408031016010BD2DE9FC41070000260025E0
+S31508003E50FFF7B0FE002803D0022813D00BD318E0D2
+S31508003E60FFF755FE002805D0DFF80864FFF756FE71
+S31508003E70C008C6400DE0FFF757FE002801D0DFF85E
+S31508003E80F86306E0FFF73CFE002801D0DFF8EC6394
+S31508003E90FFE700203860002078600020B860FFF750
+S31508003EA0B8FE0400FFF7AEFE8046FFF7A5FE002821
+S31508003EB002D0FFF7C9FE0500002C29D0FFF787FEC0
+S31508003EC0002809D0FFF7ABFE00902B0042462100E0
+S31508003ED0300000F0EFF83860FFF780FE002809D0C0
+S31508003EE0FFF7A4FE00902B0042462100300000F0A8
+S31508003EF0E1F87860FFF779FE002809D0FFF79DFE04
+S31508003F0000902B0042462100300000F0D3F8B8603C
+S31508003F10BDE8F3812DE9FC41070000260025FFF7DF
+S31508003F2049FE002803D0022813D00BD318E0FFF768
+S31508003F30EEFD002805D0DFF83C63FFF7EFFDC0086B
+S31508003F40C6400DE0FFF7F0FD002801D0DFF8286332
+S31508003F5006E0FFF7D5FD002801D0DFF82063FFE76C
+S31508003F6000203860002078600020B860FFF79CFECB
+S31508003F700400FFF792FE8046FFF788FE002802D06D
+S31508003F80FFF7ADFE0500002C29D0FFF76AFE0028D2
+S31508003F9009D0FFF78FFE00902B0042462100300023
+S31508003FA000F088F83860FFF763FE002809D0FFF7AD
+S31508003FB088FE00902B0042462100300000F07AF877
+S31508003FC07860FFF75CFE002809D0FFF781FE0090B5
+S31508003FD02B0042462100300000F06CF8B860BDE8BE
+S31508003FE0F3812DE9FC41070000240026FFF7E2FDD6
+S31508003FF0002803D0022813D00BD318E0FFF787FD5B
+S31508004000002805D0DFF86C42FFF788FDC008C440D9
+S315080040100DE0FFF789FD002801D0DFF85C4206E0D5
+S31508004020FFF76EFD002801D0DFF85042FFE70020B9
+S315080040303860002078600020B860FFF780FE050031
+S31508004040FFF776FE8046FFF76CFE002802D0FFF7E2
+S3150800405091FE0600002D2BD0002C29D0FFF74CFE30
+S31508004060002809D0FFF771FE009033004246290068
+S31508004070200000F01FF83860FFF745FE002809D039
+S31508004080FFF76AFE0090330042462900200000F040
+S3150800409011F87860FFF73EFE002809D0FFF763FEA7
+S315080040A00090330042462900200000F003F8B8606B
+S315080040B0BDE8F38100EE100A00EE901A01EE102A10
+S315080040C001EE903A9DED002AB8EE400AF8EE600A35
+S315080040D080EE200AF8EE410AB8EE611ADFED4D1AB5
+S315080040E081EE211A70EE810A20EE200AF8EE420AC5
+S315080040F080EE200ABCEEC00A10EE100A70471FB503
+S315080041000024FFF753FDDFF87811884240D0DFF826
+S315080041107411884228D0DFF8701188424CD0DFF835
+S315080041206C11884248D0DFF8681188424DD0DFF814
+S315080041306411884249D0DFF8601188424ED0DFF812
+S315080041405C1188424AD0DFF85811884251D0DFF80E
+S31508004150541188424DD0DFF85011884250D0DFF80C
+S315080041604C1188424CD052E000F0A4F80400FFF746
+S31508004170EFFCDFF83C11C0F30320085C10F01F00C9
+S31508004180C440200000F0B5F800F0CEF804003EE088
+S3150800419000F090F80400FFF7DBFCDFF81411C0F319
+S315080041A00320085C10F01F00C440200000F0A1F8AE
+S315080041B000F0ACF804002AE0FFF74CFD002803D015
+S315080041C06846FFF7A7FE019C21E0FFF78EFD002851
+S315080041D003D06846FFF705FF019C18E0FFF797FC38
+S315080041E0002805D0DFF88C40FFF798FCC008C440CB
+S315080041F00DE0FFF799FC002801D0DFF87C4006E0C7
+S31508004200FFF799FC002801D04FF40044FFE720008F
+S3150800421004B010BD0000004600440258704402581D
+S3150800422010440258184402581C44025820440258A4
+S315080042304C44025828440258004402582C44025858
+S315080042403044025845EDF6EA000202020000FF017A
+S315080042508002010134440258384402583C4402584A
+S31508004260404402584444025860440258684402587C
+S31508004270D04402580090D00300093D0000127A008D
+S3150800428008000007080300070800010708030107DC
+S3150800429008000207080302070800030708030307C4
+S315080042A008000407080304070800050708030507AC
+S315080042B03C6E00081FB50024FFF744FC002806D012
+S315080042C008280AD010280AD018280AD00EE01E4C52
+S315080042D0FFF724FCC008C44008E01A4C06E01B4C53
+S315080042E004E06846FFF7AFFD009CFFE7200004B036
+S315080042F010BD10B50400FFF731FC154910F00F008A
+S31508004300085C10F01F00C440200010BD10B5040062
+S31508004310FFF72AFC0E49C0F30210085C10F01F00D4
+S31508004320C440200010BD000010B50400FFF722FCB1
+S315080043300749C0F30220085C10F01F00C4402000A3
+S3150800434010BD000000093D000090D00300127A005D
+S315080043503C6E0008DFF8B4140A68D208D20010438D
+S3150800436008607047DFF8A8140A6832F44042104320
+S3150800437008607047DFF89C04016851F480210160E9
+S315080043807047DFF89004016851F480310160704786
+S31508004390DFF880040068400C10F001007047DFF871
+S315080043A078140A68D208D200104308607047DFF80C
+S315080043B06C140A6832F47062104308607047DFF8BC
+S315080043C05C140A6812091201104308607047DFF886
+S315080043D050140A6832F07002104308607047DFF81C
+S315080043E040140A6832F4E062104308607047DFF848
+S315080043F02C140A6832F07002104308607047DFF820
+S3150800440024140A6832F0700210430860704710B42A
+S3150800441000F0FF02DFF810148A18116803001B0E5B
+S315080044200400240A14F01F04A3409943C0F3074369
+S31508004430000A10F01F0013FA00F00843106010BCC1
+S31508004440704780B5FFF7E3FF01BDDFF8E0130A68A0
+S3150800445032F44012104308607047DFF8D4130A6834
+S3150800446032F04052104308607047DFF8C8130A68F4
+S3150800447092089200104308607047DFF898030168B5
+S3150800448051F0807101607047DFF888030068400EBC
+S3150800449010F001007047DFF8A003016851F480317D
+S315080044A001607047DFF89003016851F4003101603C
+S315080044B07047E1490A6832F0020252EA40020A608D
+S315080044C07047DD490A6832F00C0252EA80020A6037
+S315080044D07047DA490A68520A5202401E10430860B9
+S315080044E07047D4490A6832F47C7252EA00120A60AC
+S315080044F07047D2490A6832F47E42401E52EA402288
+S315080045000A607047CD490A6832F4FE02401E52EA34
+S3150800451000420A607047C9490A6832F0FE42401EE6
+S3150800452052EA00620A607047C5490A681209120110
+S31508004530104308607047C248006810F00F007047C3
+S3150800454081B0C0490A6802430A60096808400090B9
+S31508004550009801B07047BB490A6832EA0000086053
+S31508004560704781B0B8490A6802430A60096808407A
+S315080045700090009801B07047B3490A6832EA000013
+S315080045800860704781B0B1490A6802430A60096841
+S3150800459008400090009801B07047AC490A6832EAB2
+S315080045A000000860704781B0A9490A6802430A609A
+S315080045B0096808400090009801B07047A4490A6845
+S315080045C032EA00000860704781B0A2490A680243CF
+S315080045D00A60096808400090009801B070479D4934
+S315080045E00A6832EA0000086070470904816170476A
+S315080045F080B500F005F800F03DF900F049F9FCE750
+S3150800460080B500F04FF900F001F801BD80B504202F
+S31508004610FFF78AFFFFF78FFF042803D064218E482F
+S31508004620FEF777F90220FFF795FE4FF44040FFF7B3
+S3150800463099FEFFF79FFEFFF7A4FEFFF7A9FE0128E4
+S31508004640FBD10220FFF711FFFFF725FFFFF72AFF2F
+S315080046500120FFF736FF0020FFF72BFF0420FFF7A6
+S3150800466040FF4FF4F070FFF734FF0220FFF741FFD9
+S315080046701420FFF747FF0220FFF74DFFFFF7FDFE67
+S31508004680FFF702FF0128FBD10820FFF798FE032059
+S31508004690FFF785FE0020FFF78AFE0820FFF78FFE4A
+S315080046A04020FFF794FE4FF48060FFF798FE402005
+S315080046B0FFF79DFE4020FFF7A2FE6848FFF7C1FE00
+S315080046C00020FFF7CAFE5FF48010FFF7BEFE6448BD
+S315080046D000F062F901BD38B586B00220FFF774FF15
+S315080046E00120FFF73EFF0220FFF73BFF0420FFF7FC
+S315080046F038FF0820FFF735FF5FF48020FFF742FFF9
+S315080047004FF48070FFF74FFF802000900120019042
+S31508004710002002900020039000200490514C694626
+S31508004720200000F03DFA4FF4005000900020019060
+S315080047300020049069464C4800F032FA4FF4407560
+S31508004740009502200190002002900020039000208E
+S315080047500490072005906946444800F021FA009520
+S31508004760022001900220029000200390002004906D
+S31508004770092005906946200000F012FA4FF4C0504F
+S315080047800090022001900320029000200390002050
+S3150800479004900A2005906946354800F001FA5FF052
+S315080047A00060FFF7CDFE07B030BD10B5FFF7E8FA99
+S315080047B02C4C80212000FFF718FF2C4800F05DF9EB
+S315080047C0294800F05AF9200000F057F9284800F067
+S315080047D054F95FF00060FFF7BEFE4FF48070FFF7F4
+S315080047E0EDFE5FF48020FFF7D8FE0820FFF7C4FE31
+S315080047F00420FFF7C1FE0220FFF7BEFE0120FFF7E7
+S31508004800BBFE0220FFF7EBFE10BD00000C48025865
+S3150800481018480258004402581044025818440258CE
+S315080048201C440258204402584C4402585444025826
+S3150800483050440258284402582C440258304402581E
+S3150800484000200052D8440258E0440258E84402586E
+S31508004850EC440258F4440258686B00080800000744
+S3150800486000389C1C0004025800080258000C025824
+S315080048700000025880B500F0D5F9FEF789FCFCF770
+S3150800488067FC00F006FA00F023FA00F0BBFA01BD57
+S3150800489080B5FEF781FCFCF775FC00F02AFA00F0FB
+S315080048A0BAFA01BD80B5032000F03DFBFDF73AFDDD
+S315080048B0DFF8B010DFF8B0200B68C3F30323D35C2E
+S315080048C013F01F03D840096811F00F01515C11F06D
+S315080048D01F010200CA40DFF894100A60DFF8901042
+S315080048E00860002000F046FB002801D0012002E005
+S315080048F0FFF7F1FE002002BD80B5DFF878007FF0F3
+S315080049000041016000210160DFF86C105FF0FF30A4
+S31508004910086000220A60DFF86410086000220A6056
+S31508004920DFF85C10086000220A60DFF8581008609B
+S3150800493000220A60DFF85010086000220A60DFF8DB
+S315080049404C10086000220A60DFF844100860002254
+S315080049500A60DFF84010086000200860FFF725FFAE
+S31508004960002002BD184402584C6E000808000020BA
+S31508004970040000207C4402588044025884440258AB
+S31508004980884402588C440258904402589444025869
+S31508004990984402589C440258014908607047000030
+S315080049A00400002030B4046801FB01F503235D43CD
+S315080049B0AC43494351432143016030BC70474368C7
+S315080049C08B43514319434160704730B4846801FBF7
+S315080049D001F503235D43AC434943514321438160B9
+S315080049E030BC704730B4C46801FB01F503235D434E
+S315080049F0AC43494351432143C16030BC704730B48E
+S31508004A00046A01FB01F54D434D430F235D43AC4357
+S31508004A1001FB01F34B4301FB03F1514321430162BF
+S31508004A2030BC704730B4446A0D002D0A0B001B0ACF
+S31508004A305D430B001B0A5D430B001B0A5D430F23F6
+S31508004A405D43AC430D002D0A0B001B0A5D430B00AA
+S31508004A501B0A5D43090A01FB05F1514321434162E3
+S31508004A6030BC704742490A6810430860704740499D
+S31508004A700A6832EA00000860704710B500243D490C
+S31508004A80884206D10120FFF7EDFF0120FFF7EFFF6F
+S31508004A906AE03949884206D10220FFF7E3FF02207F
+S31508004AA0FFF7E5FF60E03549884206D10420FFF7A5
+S31508004AB0D9FF0420FFF7DBFF56E03149884206D1CB
+S31508004AC00820FFF7CFFF0820FFF7D1FF4CE02D495C
+S31508004AD0884206D11020FFF7C5FF1020FFF7C7FF51
+S31508004AE042E02949884206D12020FFF7BBFF202053
+S31508004AF0FFF7BDFF38E02549884206D14020FFF779
+S31508004B00B1FF4020FFF7B3FF2EE02149884206D1C6
+S31508004B108020FFF7A7FF8020FFF7A9FF24E01D49A3
+S31508004B20884208D14FF48070FFF79CFF4FF48070DD
+S31508004B30FFF79DFF18E01849884208D14FF4007026
+S31508004B40FFF790FF4FF40070FFF791FF0CE0134951
+S31508004B50884208D14FF48060FFF784FF4FF48060E5
+S31508004B60FFF785FF00E001242000C0B210BD000059
+S31508004B7088440258000002580004025800080258E7
+S31508004B80000C025800100258001402580018025867
+S31508004B90001C025800200258002402580028025817
+S31508004BA0F8B505000E00306890FAA0F0B0FA80F764
+S31508004BB031E0726921002800FFF734FF25E03468E8
+S31508004BC00120B8400440002C24D07068012802D087
+S31508004BD07068022809D1B26821002800FFF7F5FE9F
+S31508004BE0F26831682800FFF7EAFE326921002800DA
+S31508004BF0FFF7F8FE7068022807D1B4F5807FD8D28F
+S31508004C00726921002800FFF7FAFE72682100280061
+S31508004C10FFF7C8FE7F1C3068F8400028CFD1002077
+S31508004C20F2BD000080B500F0D1F901BD10B500F065
+S31508004C303CF8002816D0FDF779FE002812D000F0BF
+S31508004C4085F8FFF759FEFCF793FA00F032F80649A3
+S31508004C5008400649086000F02CF8001D046800F0BA
+S31508004C60B7F9A04710BD000080FFFF1F08ED00E060
+S31508004C7070B504000D00160005E0287820706D1C3C
+S31508004C80641CFEF789FA3000461E80B20028F4D16B
+S31508004C9070BD80B500F09EF901BD80B500F0A3F99E
+S31508004CA002BD80B500F0E6F902BD80B500F054FA01
+S31508004CB002BD80B500F096FA02BD80B500F011FA83
+S31508004CC0002801D1002001E000F06FFA02BD0000C3
+S31508004CD010B500F0EFFB00F03DFE434C01202070BC
+S31508004CE000F064FF0020207001F01EF802202070FA
+S31508004CF010BD1CB53D4C6946200000F0F4FE0128A5
+S31508004D0007D10120384908709DF80010200000F0EE
+S31508004D10F1FB6946200000F08AFF012807D1002030
+S31508004D20314908709DF80010200000F0E3FB694641
+S31508004D30200001F077F8012807D102202A490870D7
+S31508004D409DF80010200000F0D5FB13BD80B501F0DA
+S31508004D502AF801BD70B504000D00234E30780128ED
+S31508004D6004D12900C9B2200000F07BFE3078002863
+S31508004D7004D12900C9B2200000F038FF3078022893
+S31508004D8004D12900C9B2200001F01BF800F0ACFBE1
+S31508004D9070BD15480078002805D0022807D004D32E
+S31508004DA0032806D007E0402006E0082004E03F205C
+S31508004DB002E0002000E0402080B270470A480078F0
+S31508004DC0002805D0022807D004D3032806D007E018
+S31508004DD0402006E0082004E03F2002E0002000E032
+S31508004DE0402080B270470000C00000205013002009
+S31508004DF010B5002400F06FFB002800D00124200025
+S31508004E00C0B210BD80B501201749087000F022F81D
+S31508004E1000F001F801BD10B5FFF7EAFF012812D02E
+S31508004E20114C207801280ED1FCF7B5F90F490A680C
+S31508004E300F4909688A1812F5FA72904203D30020BE
+S31508004E402070FFF7F3FE10BD084908607047074851
+S31508004E500068704780B504480078012803D1FCF73C
+S31508004E609AF90349086001BDBA140020A01400206D
+S31508004E709C14002010F00700374B1A684FF6FF0104
+S31508004E800A40364951EA00210A431A6070473248F7
+S31508004E900068C0F302207047020012B2002A04D448
+S31508004EA009012F4A00B2115407E009012D4A00B240
+S31508004EB010F00F00104400F8041C704710B410F0EE
+S31508004EC00700D0F10703052B01D3042301E0D0F135
+S31508004ED00703041D072C01D2002000E0C01E012490
+S31508004EE014FA03F35B1E1940814014FA00F0401EC1
+S31508004EF01040084310BC704780B5411EB1F1807F51
+S31508004F0001D301200EE0401E174908600F215FF00B
+S31508004F10FF30FFF7C1FF0020144908600720144935
+S31508004F200860002002BD80B5FFF7A4FF01BD70B57B
+S31508004F3004000D001600FFF7AAFF32002900FFF74C
+S31508004F40BDFF0100200000B2FFF7A6FF70BD80B5C7
+S31508004F50FFF7D2FF02BD00000CED00E00000FA05E5
+S31508004F6000E400E018ED00E014E000E018E000E0DE
+S31508004F7010E000E010B5040011490878002801D1B6
+S31508004F8001201BE04FF47A700978B0FBF1F00D4967
+S31508004F900968B1FBF0F0FFF7DAFF002801D001201D
+S31508004FA00CE0102C09D2002221005FF0FF30FFF739
+S31508004FB0BEFF05480460002000E0012010BD00BFC8
+S31508004FC0C1000020040000200000002072B67047CF
+S31508004FD062B670475FF0FF30DFF8CC140860DFF880
+S31508004FE0CC14086070472DE9F04104000D00160046
+S31508004FF05FF00108DFF8B874D7F8A810D7F8AC0046
+S315080050004118491E091B681E814201D25FF000083B
+S315080050104046C0B201280CD1200000F01FFAFF2834
+S3150800502005D02819401E00F019FAFF2801D15FF0B3
+S3150800503000084046C0B2012818D12100890A4FF459
+S31508005040806041433868814208D12B003200210034
+S31508005050DFF8580400F002F9804607E02B0032001A
+S315080050602100DFF8440400F0F9F880464046C0B253
+S31508005070BDE8F081F8B504000D000126FF20070001
+S31508005080DFF82C14D1F8A820D1F8AC108A18521ED3
+S31508005090121B691E8A4200D200263100C9B20129B4
+S315080050A011D1200000F0DAF907002C19641E20003F
+S315080050B000F0D4F93900C9B2FF2903D00100C9B2FA
+S315080050C0FF2900D100263100C9B2012906D1010005
+S315080050D0C9B23800C0B200F067F906003000C0B2A5
+S315080050E0F2BD80B5012000210091DFF8C0130A68DF
+S315080050F012F1010F2ED00200D2B2012A2AD1009A4B
+S31508005100486882180092009A886882180092009A65
+S31508005110C86882180092009A086982180092009A54
+S31508005120486982180092009A886982180092009A43
+S31508005130C869821800920098C04300900098401CE5
+S3150800514000906A460421DFF86803006810F52670A7
+S31508005150FFF749FFC0B202BD01200022DFF8503335
+S31508005160196809688A181968091D09688A18196862
+S31508005170083109688A1819680C3109688A18196883
+S31508005180103109688A181968143109688A18196863
+S31508005190183109688A18196811F5267109688A1874
+S315080051A0002A00D00020C0B2704710B50124BF48BD
+S315080051B0016811F1010F04D000F0A4F8002800D10D
+S315080051C000242000C0B2012809D1B748016811F1AE
+S315080051D0010F04D000F096F8002800D10024200022
+S315080051E0C0B210BDB2480068704710B501248A05E0
+S315080051F000D000242200D2B2012A08D102688A42CD
+S3150800520005D001604FF48062001DFFF731FD2000D4
+S31508005210C0B210BD70B505000E000020A348854237
+S3150800522002D1A14D2C000EE0A1490A68964203D18D
+S3150800523005000E682C0006E02C00280000F062F835
+S31508005240002800D10024002C06D031002800FFF7E2
+S31508005250CCFF002800D10024200070BD2DE9F843BA
+S315080052600400894690461D0001274E46B60A4FF4AB
+S3150800527080604643206810F1010F06D131002000F6
+S31508005280FFF7B3FF002800D100273800C0B2012875
+S315080052900AD12068B04207D031002000FFF7BAFFD4
+S315080052A00400002C00D100273800C0B2012825D1FF
+S315080052B02068B9EB000904EB090010F10409FDF7B1
+S315080052C06BFF201DB9EB0000B0F5806F09D316F50A
+S315080052D080612000FFF79EFF0400002C0DD014F11A
+S315080052E0040998F8000089F8000019F1010918F175
+S315080052F001086D1E002DE2D100E000273800C0B27B
+S31508005300BDE8F2832DE9F84304000126202520682C
+S3150800531000F0A4F8FF2800D100263000C0B201280A
+S315080053203ED100F081FF002700E07F1C4FF480602B
+S315080053302900C9B290FBF1F087422FD22068A8460F
+S315080053405FFA88F808FB07082800C0B200FB07F0D8
+S31508005350204410F10409FDF71FFF4A464146012083
+S3150800536000F004FF002801D1002002E0002615E025
+S31508005370401C01002A00C9B2D2B291420AD20100E9
+S31508005380C9B218F801100200D2B219F802209142E7
+S31508005390EED000263000C0B20028C6D100F066FF65
+S315080053A03000C0B2BDE8F28370B586B006000C00C6
+S315080053B001250020009020003100C0B2C9B2884201
+S315080053C000D200252800C0B2012804D12000C0B2AE
+S315080053D00F2800D300252800C0B201283AD100F0D2
+S315080053E023FF1AE000200190202005903000C0B26B
+S315080053F048431044407A02903000C0B201FB00F1E5
+S3150800540002EB0100007A039001200490694601A886
+S3150800541000F0CAFF00281AD1761C20003100C0B25D
+S31508005420C9B2884214D3FDF7B7FE0C21204A3000D2
+S31508005430C0B2484313583000C0B2484310444068CD
+S3150800544013F1010F01D00028CCD1002500E000257A
+S3150800545000F00CFF2800C0B206B070BD70B504009D
+S31508005460FF25002600E0761C3000C0B20F2817D2B0
+S31508005470FDF792FE0C200E493200D2B242438A58FA
+S315080054809442F0D33200D2B242438A583300DBB298
+S3150800549000FB03F00844406882189442E3D23500C2
+S315080054A02800C0B270BD0000CC040020D00800203F
+S315080054B05C6A0008DFF8C8030021017000218164D6
+S315080054C0002180F843100021A0F8441000218170C3
+S315080054D0002141707047DFF8A8030078002801D141
+S315080054E0002000E0012070470020DFF8941381F8BF
+S315080054F04300704710B50178FF2917D100F08CF8E2
+S31508005500DFF87C4394F84300012802D1102000F00C
+S315080055107BF8B4F94400012807DB012084F843002E
+S31508005520B4F94410E01C00F053F810BDDFF850132E
+S31508005530097801294BD10178C92932D0CC293FD025
+S31508005540CF293AD0D0292FD0D12933D0D2292ED05D
+S31508005550F32917D0F4290FD0F5290AD0F6290ED049
+S31508005560FA2912D0FC2913D0FD2914D0FE2915D00A
+S3150800557029E000F0B5F8C3E700F0D1F8C0E700F07D
+S31508005580A6F8BDE700F0ECF8BAE700F08EF8B7E742
+S3150800559000F086F8B4E700F072F8B1E700F063F8B7
+S315080055A0AEE700F004F9ABE700F020F9A8E700F051
+S315080055B0E9F8A5E700F048F9A2E700F057F99FE7F0
+S315080055C000F062F99CE7202000F01EF898E7ACE7A7
+S315080055D080B589B2FFF7BEFB01BDF8B504000D0022
+S315080055E01600002704E02078C719641CFDF7D4FDCF
+S315080055F02800451E0028F6D1FFB237600120F2BD0B
+S3150800560000209F49487070479D49FE22CA7008715C
+S315080056100220A1F84400704710B5FFF7F1FF984C37
+S3150800562001202070FF20E07000202071207950F0C2
+S31508005630100020710020607160796071FFF7A9FB86
+S31508005640A071FFF7BBFBE071FFF7B8FB80B2000A59
+S315080056502072012060720120A0720820A4F844007C
+S31508005660FFF717FB10BD10B5854C00202070FFF71B
+S31508005670C7FFFF20E0700120A4F8440010BD804851
+S31508005680FF21C170002101714178417100218171AA
+S315080056900021C171002101720621A0F8441070474B
+S315080056A080B50020FFF7B0FF01BD7548FF21C17026
+S315080056B074498164002101710021417100218171C1
+S315080056C00721C0F807100821A0F8441070476C4954
+S315080056D0FF22CA70406888640120A1F84400704718
+S315080056E038B50400FFF755FB80B2401E6178884242
+S315080056F003DA2220FFF788FF10E06278604D281D44
+S3150800570092B2A96CFFF7B4FAFF20E870A86C61782A
+S315080057104018A8646078401CA5F8440031BD38B527
+S315080057200400FFF736FB80B2401E6178884203DA30
+S315080057302220FFF769FF12E0514D6068A86462787D
+S31508005740281D92B2A96CFFF793FAFF20E870A86C9F
+S3150800575061784018A8646078401CA5F8440031BDFB
+S3150800576010B5474CFF21E170E21D4168A06CFFF7B8
+S3150800577034FF2071002060710020A0710820A4F871
+S31508005780440010BD10B53E4CFF20E070002020718B
+S3150800579000206071FFF7FDFAA0710020E07100207B
+S315080057A02072002060720720A4F8440010BD38B5A6
+S315080057B00400FFF7EEFA0100314D621C89B2491E5A
+S315080057C0A86CFFF76AFA002803D13120FFF71CFFFF
+S315080057D00BE0FF20E870FFF7DCFAA96C80B2401EE8
+S315080057E04018A8640120A5F8440031BD38B5040066
+S315080057F0FFF7CFFA80B2801E6178884203DA22204A
+S31508005800FFF702FF1FE01E4DFF20E8700120A5F8F4
+S3150800581044006078002807D1FFF74FFA002802D124
+S315080058203120FFF7F1FE0EE0A21C6178A86CFFF7A5
+S3150800583034FA002803D13120FFF7E6FE03E0A86C0E
+S3150800584061784018A86431BD10B50D4C4168A06C4C
+S31508005850FFF727FA002803D13120FFF7D5FE04E029
+S31508005860FF20E0700120A4F8440010BD80B5FFF7C2
+S31508005870DDF90348FF21C1700121A0F8441001BDDC
+S3150800588038120020906E000880B53120FFF7BCFE64
+S3150800589001BD0000B3490A6832F04052104308605F
+S315080058A07047F8B504000D0016001F000020FFF72A
+S315080058B0F1FF4FF4FA51002200E0521C1000C0B26A
+S315080058C0122845D2A84B200080B294465FFA8CFC79
+S315080058D013F81CC096465FFA8EFE03EB4E0E9EF832
+S315080058E001E01EEB0C0C1CF1010C0CFB00F0B1FBEB
+S315080058F0F0FC00FB1C100028DFD1200080B2944683
+S315080059005FFA8CFC13F81CC096465FFA8EFE03EB12
+S315080059104E0E9EF801E01EEB0C0C1CF1010C0CFB64
+S3150800592000F0B1FBF0F0288028880028C5D0288828
+S3150800593040F2012C6045C0DA1000C0B213F810001E
+S315080059403070D2B203EB420040783870012000E094
+S315080059500020F2BD38B58AB00020ADF80600002058
+S315080059608DF8050000208DF8040040F2676401AB4D
+S315080059700DF105020DF106014FF4FA70FFF791FFDC
+S31508005980002803D1B8217948FCF7C3FF784D794838
+S3150800599028600020A8600020E86001202874002004
+S315080059A068740020A874BDF8060068610120A86123
+S315080059B09DF80500E8619DF80400286201206862E8
+S315080059C00120A8620120E86201202863002068639C
+S315080059D0002C04D40120A8630020E86303E000201B
+S315080059E0A8630120E8630120286404206864002075
+S315080059F0A8640420E864002028650420686500205F
+S31508005A00A8650120E865002028660020686604204D
+S31508005A10A8662800FDF7FAFB002C02D400200290A5
+S31508005A2004E05FF08040029024F0004400200390D8
+S31508005A300120049001200590069407940020089000
+S31508005A4002A92800FDF74CFD01200090012302223F
+S31508005A5002212800FDF793FD2800FDF7AAFD0BB0EB
+S31508005A6030BD30B589B0020040F2E170002803D499
+S31508005A7000900020019005E020F0004000905FF0C3
+S31508005A808040019000200290C9B2090403910020C9
+S31508005A9004900020059000200690002007905220D0
+S31508005AA00890334D012369462800FDF79CFDC0B2D6
+S31508005AB0002816D101212800FDF7D2FDC0B2002822
+S31508005AC00FD1FBF768FB0400323401212800FDF7EB
+S31508005AD0B1FE002805D0FDF75FFBFBF75CFB8442AF
+S31508005AE0F3D209B030BD2DE9F8438AB007000C009F
+S31508005AF0002540F267665FF00108DFF874904021E0
+S31508005B004846FDF7A0FE002806D03B006A4640211D
+S31508005B104846FDF7B6FD80465FFA88F8B8F1000FEB
+S31508005B201AD1002E07D40098B0420ED10198002849
+S31508005B300BD1012509E026F000460098B04204D1B1
+S31508005B400198B0F1804F00D101252800C0B2012884
+S31508005B5002D10398000C20702800C0B20BB0BDE833
+S31508005B60F083000050440258506D0008486C000845
+S31508005B709811002000A00040016851F00101016061
+S31508005B80704701684908490001607047C0694009C3
+S31508005B9010F001007047C069C00910F00100704795
+S31508005BA0406AC0B27047C9B28162704710B588B002
+S31508005BB0574C2000FFF7E5FF002000904FF46140A6
+S31508005BC001900020029000200390002004900C20F1
+S31508005BD0059000200690002007906946200000F0F6
+S31508005BE01CFD2000FFF7C8FF08B010BD70B5040003
+S31508005BF00D002800C0B2412803DB84214548FCF784
+S31508005C0088FE2800C0B200F06CF8002607E0FDF711
+S31508005C10C3FA300080B2205C00F063F8761C3000CE
+S31508005C202900C9B280B289B28842F0D370BD2DE985
+S31508005C30F04105000E00384C2078002815D1374D64
+S31508005C40280000F03DF8012837D12878002834D0FC
+S31508005C502878412831DAFBF79EFA31490860002096
+S31508005C60304908700120207027E02E4FDFF8AC80FD
+S31508005C7038784044401C00F023F8012814D13878BD
+S31508005C80401C3870387898F80010884215D13A7850
+S31508005C9092B218F101012800FEF7EAFF00202070F1
+S31508005CA038783070012009E0FBF775FA1C49096855
+S31508005CB06431814201D2002020700020BDE8F081C5
+S31508005CC070B504000025124E3000FFF75FFF00286C
+S31508005CD004D03000FFF764FF207001252800C0B209
+S31508005CE070BD38B501000A4DC9B22800FFF75BFF41
+S31508005CF0FBF751FA04000A342800FFF74CFF002886
+S31508005D0005D1FDF749FAFBF746FA8442F4D231BDCC
+S31508005D1000480040086C0008BD14002084120020CA
+S31508005D20A8140020BC14002038B500F02DF9DFF8BF
+S31508005D300C544021681C00F03EF92870DFF8004436
+S31508005D404021601C00F037F920702878FF2802D01F
+S31508005D502078FF2804D18421DFF8E803FCF7D9FD71
+S31508005D60DFF8E4430022DFF8E4132000FCF70CFC1C
+S31508005D70DFF8DC132000FCF733FC0120FCF7EFFD0D
+S31508005D802000FCF737FC00F0D3FCD4F8C002FBF780
+S31508005D90B0FDFFF75CF8B0F5FA6F03D24FF4FA607E
+S31508005DA0FFF752F831BD10B5DFF89C43D4F8C002AE
+S31508005DB0FBF7BDFD2000FCF7FFFB0020FCF7CFFD3D
+S31508005DC010BD70B505000C002000C0B2402804DBE9
+S31508005DD0BB21DFF87003FCF79CFD2000C0B200F081
+S31508005DE069F8C0B2012804D0BF21DFF85803FCF7D0
+S31508005DF090FD00260EE0FDF7CFF9300080B2285C52
+S31508005E0000F058F8C0B2012803D0C821CD48FCF7E5
+S31508005E1080FD761C30002100C9B280B289B2884262
+S31508005E20E9D370BD2DE9F04105000E00C648D0F84B
+S31508005E30C002FBF7DAFAC74C2078002813D1C64D02
+S31508005E40280000F02FF801280AD12878002807D062
+S31508005E502878402804DA012020700020BF490870FD
+S31508005E600020BDE8F081BD4FDFF8EC823878404469
+S31508005E70401C00F017F80128F2D13878401C387019
+S31508005E80387898F800108842EAD13A7892B218F130
+S31508005E9001012800FEF7ECFE0020207038783070EB
+S31508005EA00120DEE780B50100A548007800F0E8F893
+S31508005EB0C0B202BD80B50100C9B2A048007800F0A2
+S31508005EC091F8C0B202BD7CB59C4C207800F022F94E
+S31508005ED005002800C0B2002827D02800C0B24128F3
+S31508005EE000DB4025002612E06946207800F0C8F855
+S31508005EF0C0B2012804D04FF4A4719248FCF709FDFA
+S31508005F009DF8000096493200D2B28854761C3000BB
+S31508005F102900C0B2C9B28842E6D3EDB22B009BB2C3
+S31508005F208F4A81218848FCF7C5F973BDF8B5060084
+S31508005F30002000F07EFC0400834D3100C9B2280021
+S31508005F40FCF7D4F9070000260FE0300080B2215C88
+S31508005F507B48007800F046F8C0B2012804D04FF418
+S31508005F60B5717848FCF7D5FC761C3000390080B24C
+S31508005F7089B28842E9D300F05CFC02004023012183
+S31508005F802800FCF7A5F9F1BD10B4764B190013F1FA
+S31508005F901802002004E088744A6118311832401C3F
+S31508005FA00400E4B2002CF6D08874002048616E48DC
+S31508005FB0036010BC704710B46B4B1A68002A01D1F5
+S31508005FC0FF200DE01A6854691C6011749060D06057
+S31508005FD0002353741060C9B20844401E5060907C78
+S31508005FE010BC704738B505000C002800C0B202285E
+S31508005FF004DB4FF4E1715348FCF78BFC1820594930
+S315080060002A00D2B242430A44527C2B00DBB24343F5
+S315080060100B441B7C9A4201D1002030E02A00D2B200
+S3150800602042430A44D26814702A00D2B242430A4450
+S315080060302B00DBB243430B445B7C5B1C53742A0086
+S31508006040D2B242430A442B00DBB243430B44DB681B
+S315080060505B1CD3602A00D2B242430A4452682B0022
+S31508006060DBB243430B44DB689A4207D22A00D2B21A
+S3150800607042430A44EDB245434859D060012032BD37
+S3150800608038B504000D002000C0B2022804DB4FF426
+S31508006090F2712C48FCF73DFC1821324A2000C0B2A8
+S315080060A048431044407C002801D1002031E02000FC
+S315080060B0C0B2484310448068007828702000C0B2F7
+S315080060C0484310442300DBB24B4313445B7C5B1EFE
+S315080060D043742000C0B2484310442300DBB24B434C
+S315080060E013449B685B1C83602000C0B2484310447D
+S315080060F040682300DBB24B4313449B68984207D29F
+S315080061002000C0B248431044E4B24C4311598160A0
+S31508006110012032BD10B504002000C0B2022804DBFD
+S315080061204FF401710748FCF7F4FB0E49E4B2182056
+S31508006130444301EB0400407C10BD0000C812002057
+S315080061400C130020846C0008D40C0020700000207A
+S3150800615018000020BF14002090130020BE14002051
+S31508006160D013002050140020B01400202DE9F84365
+S3150800617017000D000826DFF8F441207D012801D11B
+S3150800618002204FE001202075B1F10061B1F5801FB2
+S3150800619002D25FF0010801E05FF002080020A0616A
+S315080061A04CF250394146484600F076F80100C9B22B
+S315080061B0002934D1B8F1010F06D1DFF8B40101681E
+S315080061C051F00201016005E0DFF8A801016851F00D
+S315080061D002010160BFF36F8FBFF34F8F38682860E5
+S315080061E02D1D3F1D761E3000C0B20028F6D1BFF324
+S315080061F06F8FBFF34F8F4146484600F04DF8B8F110
+S31508006200010F06D1DFF868110A6832F002020A6047
+S3150800621005E0DFF860110A6832F002020A60002120
+S315080062202175C0B2BDE8F283DFF844010168C907E9
+S315080062300CD5DFF85411DFF854210A60DFF8502135
+S315080062400A600068C00701D501200EE049480168C8
+S31508006250C90709D54F494D4A0A604D4A0A60006880
+S31508006260C00701D5012000E00020704740480168BA
+S3150800627051F0010101600068C00701D401200AE05D
+S315080062803C48016851F0010101600068C00701D46B
+S31508006290012000E000207047F8B504000D00FAF769
+S315080062A08BFF0600012D01D1042700E03A4F3B4938
+S315080062B011EA0700B84208D12F4800683840B842AA
+S315080062C001D101200DE000200BE02D480068384080
+S315080062D020F0004027F00042904201D1012000E062
+S315080062E0002000280BD014F1010FE0D0FAF764FF64
+S315080062F0801B844201D3002CD9D1032034E0012D20
+S3150800630004D11D4802682648024005E01C48026878
+S315080063102448024052F0004232F0024000280FD0D2
+S3150800632012488369134383611140914202D113488D
+S31508006330026003E022F0004212480260012013E0E6
+S31508006340012D08D10C480068C0030CD55FF48030D5
+S315080063500A49086007E00A480068C00303D55FF4E5
+S315080063608030084908600020F2BD00008014002033
+S315080063700C2000520C21005210200052142000520A
+S3150800638010210052142100520420005223016745AF
+S31508006390AB89EFCD04210052040000800F00EF1FE7
+S315080063A00000EE170000EE972DE9F0410700884639
+S315080063B00025DFF8D041207D012801D1022082E0A6
+S315080063C0012020750020A0613879C00707D5012172
+S315080063D04CF25030FFF760FF002800D001253879CD
+S315080063E0800707D502214CF25030FFF755FF0028E9
+S315080063F000D001252800C0B2002860D138680128DD
+S3150800640026D17968386900F060F83879C0070DD563
+S3150800641001214CF25030FFF73FFF002800D001253C
+S31508006420DFF86401016831F00801016038798007F6
+S3150800643045D502214CF25030FFF72EFF002800D038
+S315080064400125DFF84801016831F00801016036E0EE
+S315080064505FF0FF30C8F80000BE6800E0761CF968F7
+S31508006460B86841188E422AD23A697968300000F035
+S3150800647068F83879C0070CD501214CF25030FFF77F
+S315080064800BFF0500DFF800110A68DFF80401024077
+S315080064900A60387980070CD502214CF25030FFF794
+S315080064A0FBFE0500DFF8E4100A68DFF8E4000240A6
+S315080064B00A602800C0B20028D0D0C8F800600020C2
+S315080064C020752800C0B2BDE8F08111F00302032A46
+S315080064D018D1DFF8B4100A6832F030020A60DFF823
+S315080064E0AC20136833F0300313600B6803430B606A
+S315080064F0116808431060DFF89C00016851F010012C
+S3150800650001601DE0CA070CD5DFF87C20136833F05C
+S3150800651030031360136803431360136853F088034A
+S31508006520136089070CD5DFF864100A6832F0300268
+S315080065300A600A6810430860086850F08800086016
+S31508006540704730B4CB070CD5DFF83C301C6834F400
+S31508006550E6641C601C6852EA002555F084052C4345
+S315080065601C6089070BD509490B6833F4E6630B6091
+S315080065700B6852EA002252F084021A430A6030BCC1
+S3150800658070470000801400200C2000520C21005295
+S31508006590FBF8FFFF18200052006810F00100704752
+S315080065A0C26A1209120189B21143C1627047426870
+S315080065B032F44052114341607047826832F44072A7
+S315080065C011438160704710B40C2A24D2019CB3F59C
+S315080065D0004F14D14A4BD2B253F82220B1FBF2F144
+S315080065E02200520812EB4102B2FBF4F189B24FF6CF
+S315080065F0F0720A40C1F342010A43C2600BE0404B05
+S31508006600D2B253F82220B1FBF2F111EB5401B1FBDF
+S31508006610F4F189B2C16010BC7047F8B505000F00E7
+S31508006620012600242800FFF7B7FF002864D129684F
+S315080066303C480140B8680143386901437869014319
+S31508006640F86901432960F9682800FFF7B0FFB969BE
+S315080066502800FFF7B2FF2B48854204D13248FDF7E0
+S315080066604EFD040036E02848854204D12F48FDF740
+S3150800667046FD04002EE02548854204D12B48FDF747
+S315080066803EFD040026E02248854204D12748FDF74E
+S3150800669036FD04001EE01F48854204D12348FDF755
+S315080066A02EFD040016E01C48854204D11E48FDF75D
+S315080066B026FD04000EE01948854204D11B48FDF763
+S315080066C01EFD040006E01648854203D11748FDF76B
+S315080066D016FD0400002C0BD07868002808D0002688
+S315080066E078680090FB693A6821002800FFF76BFF7D
+S315080066F039682800FFF754FF3000C0B2F2BD000029
+S31508006700F86C0008001001400044004000480040B2
+S31508006710004C004000500040001401400078004042
+S31508006720007C0040F369FFEF080300070800000734
+S315080067300248016851F08071016070470C480258A0
+S3150800674038B5040000254023022281212000FBF7EA
+S3150800675051FD4023022201212000FBF74BFD402377
+S31508006760354A01212000FBF7B3FD2800C0B232BD2F
+S3150800677038B50400002581212000FBF74DFD0121D5
+S315080067802000FBF749FD2800C0B232BD38B50B0022
+S3150800679017222A4C14F109011D7815F0600F29D12A
+S315080067A05D78062D04D00A2D14D00B2D17D021E0C4
+S315080067B05D88ADB22D0AADB2212D07D114F11201B3
+S315080067C0DA88182A01DB172200E0DA8892B2FCF789
+S315080067D0A5FC0FE001221A49FCF7A0FC0AE059883B
+S315080067E0C9B2002903D198781549086002E0190052
+S315080067F0FCF758FC002032BD80B5FFF764FB00208B
+S3150800680002BD80B50800C0B2FFF790FB002002BDAC
+S3150800681080B590F89C02032801D1FFF754FB0020AD
+S3150800682002BD20210180054870470A2101800548DC
+S3150800683070470148704700001014002050000020DF
+S31508006840B41400200C000020122008802D48704740
+S31508006850042008802C48704780B50A00C0B200287A
+S3150800686004D12A492A48FCF728FC03E02749284886
+S31508006870FCF723FC254802BD10B50A00234C21006D
+S315080068802448FCF71AFC200010BD80B51A200880A1
+S3150800689000F022F8204802BD80B50A00C0B20028E0
+S315080068A004D11A491D48FCF708FC03E017491B48A0
+S315080068B0FCF703FC154802BD80B50A00C0B20028E3
+S315080068C004D112491648FCF7F8FB03E00F491448AF
+S315080068D0FCF7F3FB0D4802BD38B5124800681249AB
+S315080068E00C6812490968081800280AD00A4D0822B7
+S315080068F0A91C00F01DF8042215F11201200000F071
+S3150800690017F831BD8C000020A0000020980F002049
+S31508006910186E00085C6E0008A4000020886E000847
+S31508006920006E000800E8F11F04E8F11F08E8F11FEF
+S3150800693030B4002300231AE00400240F37341D0066
+S31508006940EDB201F815400AE00400240F0A2CF3D230
+S315080069500400240F30341D00EDB201F81540000183
+S3150800696000241D00EDB201EB45056C705B1C1C0094
+S315080069701500E4B2EDB2AC42E6D330BC7047000075
+S315080069802348016851F4700101602249086850F0F3
+S31508006990010008600020204A10600A681F4802406B
+S315080069A00A6000201E4A106000201E4A106000205F
+S315080069B01D4A106000201D4A106000201C4A106005
+S315080069C000201C4A106000201B4A106000201B4A49
+S315080069D0106000201A4A106000201A4A1060002031
+S315080069E0194A1060086830F48020086000201749AA
+S315080069F0086017480068000C0004B0F1005F02D276
+S31508006A000120144908605FF0006013490860704768
+S31508006A1088ED00E000440258104402587FEDF6EA7B
+S31508006A20184402581C440258204402582844025864
+S31508006A302C44025830440258344402583844025808
+S31508006A403C440258404402584444025860440258A0
+S31508006A500010005C0881005108ED00E00000020803
+S31508006A600000020001010000000004080000020006
+S31508006A7002010000000006080000020003010000F1
+S31508006A8000000808000002000401000000000A08CF
+S31508006A90000002000501000000000C0800000200CA
+S31508006AA00601000000000E080000020007010000B1
+S31508006AB00000100800000200000200000000120892
+S31508006AC00000020001020000000014080000020095
+S31508006AD0020200000000160800000200030200007F
+S31508006AE000001808000002000402000000001A084E
+S31508006AF0000002000502000000001C080000020059
+S31508006B000602000000001E0800000200070200003E
+S31508006B10433A5C576F726B5C736F66747761726524
+S31508006B205C4F70656E424C545C5461726765745C68
+S31508006B3044656D6F5C41524D434D375F53544D3339
+S31508006B403248375F4E75636C656F5F483734335A22
+S31508006B50495F4941525C426F6F745C757362645F4A
+S31508006B60636F6E662E630000433A5C576F726B5C08
+S31508006B70736F6674776172655C4F70656E424C54CC
+S31508006B805C5461726765745C44656D6F5C41524D17
+S31508006B90434D375F53544D333248375F4E75636CF8
+S31508006BA0656F5F483734335A495F4941525C426FD3
+S31508006BB06F745C6D61696E2E630000000000000052
+S31508006BC000000000000000000000000000000000B7
+S31508006BD0010000000200000003000000040000009D
+S31508006BE00000000005000000000000000000000092
+S31508006BF00000000006000000000000000000000081
+S31508006C000000000007000000433A5C576F726B5C97
+S31508006C10736F6674776172655C4F70656E424C542B
+S31508006C205C5461726765745C536F757263655C4129
+S31508006C30524D434D375F53544D333248375C727368
+S31508006C403233322E63000000433A5C576F726B5C36
+S31508006C50736F6674776172655C4F70656E424C54EB
+S31508006C605C5461726765745C536F757263655C41E9
+S31508006C70524D434D375F53544D333248375C636149
+S31508006C806E2E6300433A5C576F726B5C736F667463
+S31508006C90776172655C4F70656E424C545C546172E4
+S31508006CA06765745C536F757263655C41524D434DFD
+S31508006CB0375F53544D333248375C7573622E630021
+S31508006CC030B5016884684218416802EB5103C90768
+S31508006CD003D54C4401E0491C05D19A420AD012F961
+S31508006CE0011B12F8015B002904F8015BF3D4491E65
+S31508006CF0F7D5F2E70C3030BD0100000002000000B5
+S31508006D000400000006000000080000000A00000059
+S31508006D100C000000100000002000000040000000E9
+S31508006D20800000000001000010B5074979441831B9
+S31508006D30064C7C44163404E00A68081D114488474A
+S31508006D400146A142F8D110BD500000006C000000B9
+S31508006D5005020602060307030803090309040A04D1
+S31508006D600B040C040C050D050E050F050F06100681
+S31508006D70100710084EF68851CEF20001086840F454
+S31508006D8070000860BFF34F8FBFF36F8F4FF000702E
+S31508006D90E1EE100A7047000023B1FFFF001400005F
+S31508006DA0C40000200000000019FFFFFF3C0300009C
+S31508006DB0380100000000002000F00DF8002801D07E
+S31508006DC0FFF7B2FFAFF300800020AFF30080FDF7B6
+S31508006DD00FFC00F002F80120704700F001B800002F
+S31508006DE00746384600F002F8FBE7000080B5AFF327
+S31508006DF00080024A11001820ABBEFBE726000200FD
+S31508006E0057696E5553422042756C6B20496E7465FE
+S31508006E10726661636500000057696E5553422042E9
+S31508006E20756C6B2044657669636500000001020392
+S31508006E3004050607080C101418203040000000004E
+S31508006E400102030401020304060708090000000002
+S31508006E500102030401020304060708094F70656E60
+S31508006E60424C542055736572000000000148804763
+S31508006E7001480047816900087D6E0008AFF300806D
+S31508006E80FFF778FFFFF798FF44656661756C740035
+S31508006E904F70656E424C5400FFF7FEBFFFF7FEBF0A
+S31508006EA0FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF08
+S31508006EB0FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFF8
+S31508006EC0FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFE8
+S31508006ED0FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFD8
+S31508006EE0FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFC8
+S31508006EF0FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFB8
+S31508006F00FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFA7
+S31508006F10FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF97
+S31508006F20FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF87
+S31508006F30FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF77
+S31508006F40FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF67
+S31508006F50FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF57
+S31508006F60FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF47
+S31508006F70FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF37
+S31508006F80FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF27
+S31508006F90FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF17
+S31508006FA0FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF07
+S31508006FB0FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFF7
+S31508006FC0FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFE7
+S31508006FD0FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFD7
+S31508006FE0FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFC7
+S31508006FF0FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFB7
+S31508007000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFA6
+S31508007010FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF96
+S31508007020FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF86
+S31508007030FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF76
+S31508007040FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF66
+S31508007050FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF56
+S31508007060FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF46
+S31508007070FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF36
+S31508007080FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF26
+S31508007090FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF16
+S315080070A0FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF06
+S315080070B0FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFF6
+S315080070C0FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFE6
+S315080070D0FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFD6
+S315080070E0FFF7FEBFFFF7FEBF0010FC000A90D003B3
+S315080070F00090D0030A060002FD00014001FD000BC6
+S3150800710041670008716700088D670008F8000BF9E9
+S315080071106700080368000811680008F4000323687C
+S315080071200008FC00122B6800080902200001010073
+S31508007130C0320904000002FFFD002D070581024048
+S3150800714000FF070501024000FF4968000851680072
+S315080071500879680008596800088B6800089968006B
+S3150800716008B968000812010002FD001240501DAC63
+S31508007170600002010203010000040309041A03E681
+S3090800718000010401F7
+S70508006E7D07
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/blt_conf.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/blt_conf.h
new file mode 100644
index 00000000..b9e07941
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/blt_conf.h
@@ -0,0 +1,189 @@
+/************************************************************************************//**
+* \file         Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/blt_conf.h
+* \brief        Bootloader configuration header file.
+* \ingroup      Boot_ARMCM7_STM32H7_Nucleo_H743ZI_IAR
+* \internal
+*----------------------------------------------------------------------------------------
+*                          C O P Y R I G H T
+*----------------------------------------------------------------------------------------
+*   Copyright (c) 2020  by Feaser    http://www.feaser.com    All rights reserved
+*
+*----------------------------------------------------------------------------------------
+*                            L I C E N S E
+*----------------------------------------------------------------------------------------
+* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as published by the Free
+* Software Foundation, either version 3 of the License, or (at your option) any later
+* version.
+*
+* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+* PURPOSE. See the GNU General Public License for more details.
+*
+* You have received a copy of the GNU General Public License along with OpenBLT. It
+* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
+*
+* \endinternal
+****************************************************************************************/
+#ifndef BLT_CONF_H
+#define BLT_CONF_H
+
+/****************************************************************************************
+*   C P U   D R I V E R   C O N F I G U R A T I O N
+****************************************************************************************/
+/* To properly initialize the baudrate clocks of the communication interface, typically
+ * the speed of the crystal oscillator and/or the speed at which the system runs is
+ * needed. Set these through configurables BOOT_CPU_XTAL_SPEED_KHZ and
+ * BOOT_CPU_SYSTEM_SPEED_KHZ, respectively. To enable data exchange with the host that is
+ * not dependent on the targets architecture, the byte ordering needs to be known.
+ * Setting BOOT_CPU_BYTE_ORDER_MOTOROLA to 1 selects big endian mode and 0 selects
+ * little endian mode.
+ *
+ * Set BOOT_CPU_USER_PROGRAM_START_HOOK to 1 if you would like a hook function to be
+ * called the moment the user program is about to be started. This could be used to
+ * de-initialize application specific parts, for example to stop blinking an LED, etc.
+ */
+/** \brief Frequency of the external crystal oscillator. */
+#define BOOT_CPU_XTAL_SPEED_KHZ          (8000)
+/** \brief Desired system speed. */
+#define BOOT_CPU_SYSTEM_SPEED_KHZ        (480000)
+/** \brief Motorola or Intel style byte ordering. */
+#define BOOT_CPU_BYTE_ORDER_MOTOROLA     (0)
+/** \brief Enable/disable hook function call right before user program start. */
+#define BOOT_CPU_USER_PROGRAM_START_HOOK (1)
+
+
+/****************************************************************************************
+*   C O M M U N I C A T I O N   I N T E R F A C E   C O N F I G U R A T I O N
+****************************************************************************************/
+/* The USB communication interface is selected by setting the BOOT_COM_USB_ENABLE
+ * configurable to 1. The maximum amount of data bytes in a message for data transmission
+ * and reception is set through BOOT_COM_USB_TX_MAX_DATA and BOOT_COM_USB_RX_MAX_DATA,
+ * respectively.
+ *
+ */
+/** \brief Enable/disable USB transport layer. */
+#define BOOT_COM_USB_ENABLE             (1)
+/** \brief Configure number of bytes in the target->host data packet. */
+#define BOOT_COM_USB_TX_MAX_DATA        (63)
+/** \brief Configure number of bytes in the host->target data packet. */
+#define BOOT_COM_USB_RX_MAX_DATA        (63)
+
+/* The CAN communication interface is selected by setting the BOOT_COM_CAN_ENABLE
+ * configurable to 1. Configurable BOOT_COM_CAN_BAUDRATE selects the communication speed
+ * in bits/second. Two CAN messages are reserved for communication with the host. The
+ * message identifier for sending data from the target to the host is configured with
+ * BOOT_COM_CAN_TXMSG_ID. The one for receiving data from the host is configured with
+ * BOOT_COM_CAN_RXMSG_ID. Note that an extended 29-bit CAN identifier is configured by
+ * OR-ing with mask 0x80000000. The maximum amount of data bytes in a message for data
+ * transmission and reception is set through BOOT_COM_CAN_TX_MAX_DATA and
+ * BOOT_COM_CAN_RX_MAX_DATA, respectively. It is common for a microcontroller to have more
+ * than 1 CAN controller on board. The zero-based BOOT_COM_CAN_CHANNEL_INDEX selects the
+ * CAN controller channel.
+ *
+ */
+/** \brief Enable/disable CAN transport layer. */
+#define BOOT_COM_CAN_ENABLE             (1)
+/** \brief Configure the desired CAN baudrate. */
+#define BOOT_COM_CAN_BAUDRATE           (500000)
+/** \brief Configure CAN message ID target->host. */
+#define BOOT_COM_CAN_TX_MSG_ID          (0x7E1 /*| 0x80000000*/)
+/** \brief Configure number of bytes in the target->host CAN message. */
+#define BOOT_COM_CAN_TX_MAX_DATA        (8)
+/** \brief Configure CAN message ID host->target. */
+#define BOOT_COM_CAN_RX_MSG_ID          (0x667 /*| 0x80000000*/)
+/** \brief Configure number of bytes in the host->target CAN message. */
+#define BOOT_COM_CAN_RX_MAX_DATA        (8)
+/** \brief Select the desired CAN peripheral as a zero based index. */
+#define BOOT_COM_CAN_CHANNEL_INDEX      (0)
+
+/* The RS232 communication interface is selected by setting the BOOT_COM_RS232_ENABLE
+ * configurable to 1. Configurable BOOT_COM_RS232_BAUDRATE selects the communication speed
+ * in bits/second. The maximum amount of data bytes in a message for data transmission
+ * and reception is set through BOOT_COM_RS232_TX_MAX_DATA and BOOT_COM_RS232_RX_MAX_DATA,
+ * respectively. It is common for a microcontroller to have more than 1 UART interface
+ * on board. The zero-based BOOT_COM_RS232_CHANNEL_INDEX selects the UART interface.
+ *
+ */
+/** \brief Enable/disable UART transport layer. */
+#define BOOT_COM_RS232_ENABLE            (1)
+/** \brief Configure the desired communication speed. */
+#define BOOT_COM_RS232_BAUDRATE          (57600)
+/** \brief Configure number of bytes in the target->host data packet. */
+#define BOOT_COM_RS232_TX_MAX_DATA       (64)
+/** \brief Configure number of bytes in the host->target data packet. */
+#define BOOT_COM_RS232_RX_MAX_DATA       (64)
+/** \brief Select the desired UART peripheral as a zero based index. */
+#define BOOT_COM_RS232_CHANNEL_INDEX     (2)
+
+
+/****************************************************************************************
+*   B A C K D O O R   E N T R Y   C O N F I G U R A T I O N
+****************************************************************************************/
+/* It is possible to implement an application specific method to force the bootloader to
+ * stay active after a reset. Such a backdoor entry into the bootloader is desired in
+ * situations where the user program does not run properly and therefore cannot
+ * reactivate the bootloader. By enabling these hook functions, the application can
+ * implement the backdoor, which overrides the default backdoor entry that is programmed
+ * into the bootloader. When desired for security purposes, these hook functions can
+ * also be implemented in a way that disables the backdoor entry altogether.
+ */
+/** \brief Enable/disable the backdoor override hook functions. */
+#define BOOT_BACKDOOR_HOOKS_ENABLE      (0)
+
+
+/****************************************************************************************
+*   N O N - V O L A T I L E   M E M O R Y   D R I V E R   C O N F I G U R A T I O N
+****************************************************************************************/
+/* The NVM driver typically supports erase and program operations of the internal memory
+ * present on the microcontroller. Through these hook functions the NVM driver can be
+ * extended to support additional memory types such as external flash memory and serial
+ * eeproms. The size of the internal memory in kilobytes is specified with configurable
+ * BOOT_NVM_SIZE_KB. If desired the internal checksum writing and verification method can
+ * be overridden with a application specific method by enabling configuration switch
+ * BOOT_NVM_CHECKSUM_HOOKS_ENABLE.
+ */
+/** \brief Enable/disable the NVM hook function for supporting additional memory devices. */
+#define BOOT_NVM_HOOKS_ENABLE           (0)
+/** \brief Configure the size of the default memory device (typically flash EEPROM). */
+#define BOOT_NVM_SIZE_KB                (2048)
+/** \brief Enable/disable hooks functions to override the user program checksum handling. */
+#define BOOT_NVM_CHECKSUM_HOOKS_ENABLE  (0)
+
+
+/****************************************************************************************
+*   W A T C H D O G   D R I V E R   C O N F I G U R A T I O N
+****************************************************************************************/
+/* The COP driver cannot be configured internally in the bootloader, because its use
+ * and configuration is application specific. The bootloader does need to service the
+ * watchdog in case it is used. When the application requires the use of a watchdog,
+ * set BOOT_COP_HOOKS_ENABLE to be able to initialize and service the watchdog through
+ * hook functions.
+ */
+/** \brief Enable/disable the hook functions for controlling the watchdog. */
+#define BOOT_COP_HOOKS_ENABLE           (1)
+
+
+/****************************************************************************************
+*   S E E D / K E Y   S E C U R I T Y   C O N F I G U R A T I O N
+****************************************************************************************/
+/* A security mechanism can be enabled in the bootloader's XCP module by setting configu-
+ * rable BOOT_XCP_SEED_KEY_ENABLE to 1. Before any memory erase or programming
+ * operations can be performed, access to this resource need to be unlocked.
+ * In the Microboot settings on tab "XCP Protection" you need to specify a DLL that
+ * implements the unlocking algorithm. The demo programs are configured for the (simple)
+ * algorithm in "libseednkey.dll". The source code for this DLL is available so it can be
+ * customized to your needs.
+ * During the unlock sequence, Microboot requests a seed from the bootloader, which is in
+ * the format of a byte array. Using this seed the unlock algorithm in the DLL computes
+ * a key, which is also a byte array, and sends this back to the bootloader. The
+ * bootloader then verifies this key to determine if programming and erase operations are
+ * permitted.
+ * After enabling this feature the hook functions XcpGetSeedHook() and XcpVerifyKeyHook()
+ * are called by the bootloader to obtain the seed and to verify the key, respectively.
+ */
+#define BOOT_XCP_SEED_KEY_ENABLE        (0)
+
+
+#endif /* BLT_CONF_H */
+/*********************************** end of blt_conf.h *********************************/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/boot.dox b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/boot.dox
new file mode 100644
index 00000000..370d2665
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/boot.dox
@@ -0,0 +1,7 @@
+/**
+\defgroup   Boot_ARMCM7_STM32H7_Nucleo_H743ZI_IAR Bootloader
+\brief      Bootloader. 
+\ingroup    ARMCM7_STM32H7_Nucleo_H743ZI_IAR
+*/
+
+
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/hooks.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/hooks.c
new file mode 100644
index 00000000..a21858f0
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/hooks.c
@@ -0,0 +1,350 @@
+/************************************************************************************//**
+* \file         Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/hooks.c
+* \brief        Bootloader callback source file.
+* \ingroup      Boot_ARMCM7_STM32H7_Nucleo_H743ZI_IAR
+* \internal
+*----------------------------------------------------------------------------------------
+*                          C O P Y R I G H T
+*----------------------------------------------------------------------------------------
+*   Copyright (c) 2020  by Feaser    http://www.feaser.com    All rights reserved
+*
+*----------------------------------------------------------------------------------------
+*                            L I C E N S E
+*----------------------------------------------------------------------------------------
+* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as published by the Free
+* Software Foundation, either version 3 of the License, or (at your option) any later
+* version.
+*
+* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+* PURPOSE. See the GNU General Public License for more details.
+*
+* You have received a copy of the GNU General Public License along with OpenBLT. It
+* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
+*
+* \endinternal
+****************************************************************************************/
+
+/****************************************************************************************
+* Include files
+****************************************************************************************/
+#include "boot.h"                                /* bootloader generic header          */
+#include "led.h"                                 /* LED driver header                  */
+#include "stm32h7xx.h"                           /* STM32 CPU and HAL header           */
+#include "stm32h7xx_ll_gpio.h"                   /* STM32 LL GPIO header               */
+
+
+/****************************************************************************************
+*   C P U   D R I V E R   H O O K   F U N C T I O N S
+****************************************************************************************/
+
+#if (BOOT_CPU_USER_PROGRAM_START_HOOK > 0)
+/************************************************************************************//**
+** \brief     Callback that gets called when the bootloader is about to exit and
+**            hand over control to the user program. This is the last moment that
+**            some final checking can be performed and if necessary prevent the
+**            bootloader from activiting the user program.
+** \return    BLT_TRUE if it is okay to start the user program, BLT_FALSE to keep
+**            keep the bootloader active.
+**
+****************************************************************************************/
+blt_bool CpuUserProgramStartHook(void)
+{
+  /* additional and optional backdoor entry through the pushbutton on the board. to
+   * force the bootloader to stay active after reset, keep the pushbutton pressed while
+   * resetting the microcontroller.
+   */
+  if (LL_GPIO_IsInputPinSet(GPIOC, LL_GPIO_PIN_13) != 0)
+  {
+    /* pushbutton pressed, so do not start the user program and keep the
+     * bootloader active instead.
+     */
+    return BLT_FALSE;
+  }
+  /* clean up the LED driver */
+  LedBlinkExit();
+  /*  okay to start the user program.*/
+  return BLT_TRUE;
+} /*** end of CpuUserProgramStartHook ***/
+#endif /* BOOT_CPU_USER_PROGRAM_START_HOOK > 0 */
+
+
+/****************************************************************************************
+*   W A T C H D O G   D R I V E R   H O O K   F U N C T I O N S
+****************************************************************************************/
+
+#if (BOOT_COP_HOOKS_ENABLE > 0)
+/************************************************************************************//**
+** \brief     Callback that gets called at the end of the internal COP driver
+**            initialization routine. It can be used to configure and enable the
+**            watchdog.
+** \return    none.
+**
+****************************************************************************************/
+void CopInitHook(void)
+{
+  /* this function is called upon initialization. might as well use it to initialize
+   * the LED driver. It is kind of a visual watchdog anyways.
+   */
+  LedBlinkInit(100);
+} /*** end of CopInitHook ***/
+
+
+/************************************************************************************//**
+** \brief     Callback that gets called at the end of the internal COP driver
+**            service routine. This gets called upon initialization and during
+**            potential long lasting loops and routine. It can be used to service
+**            the watchdog to prevent a watchdog reset.
+** \return    none.
+**
+****************************************************************************************/
+void CopServiceHook(void)
+{
+  /* run the LED blink task. this is a better place to do it than in the main() program
+   * loop. certain operations such as flash erase can take a long time, which would cause
+   * a blink interval to be skipped. this function is also called during such operations,
+   * so no blink intervals will be skipped when calling the LED blink task here.
+   */
+  LedBlinkTask();
+} /*** end of CopServiceHook ***/
+#endif /* BOOT_COP_HOOKS_ENABLE > 0 */
+
+
+/****************************************************************************************
+*   U S B   C O M M U N I C A T I O N   I N T E R F A C E   H O O K   F U N C T I O N S
+****************************************************************************************/
+
+#if (BOOT_COM_USB_ENABLE > 0)
+/************************************************************************************//**
+** \brief     Callback that gets called whenever the USB device should be connected
+**            to the USB bus.
+** \param     connect BLT_TRUE to connect and BLT_FALSE to disconnect.
+** \return    none.
+**
+****************************************************************************************/
+void UsbConnectHook(blt_bool connect)
+{
+  /* Note that this is handled automatically by the OTG peripheral. */
+} /*** end of UsbConnect ***/
+
+
+/************************************************************************************//**
+** \brief     Callback that gets called whenever the USB host requests the device
+**            to enter a low power mode.
+** \return    none.
+**
+****************************************************************************************/
+void UsbEnterLowPowerModeHook(void)
+{
+  /* support to enter a low power mode can be implemented here */
+} /*** end of UsbEnterLowPowerMode ***/
+
+
+/************************************************************************************//**
+** \brief     Callback that gets called whenever the USB host requests the device to
+**            exit low power mode.
+** \return    none.
+**
+****************************************************************************************/
+void UsbLeaveLowPowerModeHook(void)
+{
+  /* support to leave a low power mode can be implemented here */
+} /*** end of UsbLeaveLowPowerMode ***/
+#endif /* BOOT_COM_USB_ENABLE > 0 */
+
+
+/****************************************************************************************
+*   B A C K D O O R   E N T R Y   H O O K   F U N C T I O N S
+****************************************************************************************/
+
+#if (BOOT_BACKDOOR_HOOKS_ENABLE > 0)
+/************************************************************************************//**
+** \brief     Initializes the backdoor entry option.
+** \return    none.
+**
+****************************************************************************************/
+void BackDoorInitHook(void)
+{
+} /*** end of BackDoorInitHook ***/
+
+
+/************************************************************************************//**
+** \brief     Checks if a backdoor entry is requested.
+** \return    BLT_TRUE if the backdoor entry is requested, BLT_FALSE otherwise.
+**
+****************************************************************************************/
+blt_bool BackDoorEntryHook(void)
+{
+  /* default implementation always activates the bootloader after a reset */
+  return BLT_TRUE;
+} /*** end of BackDoorEntryHook ***/
+#endif /* BOOT_BACKDOOR_HOOKS_ENABLE > 0 */
+
+
+/****************************************************************************************
+*   N O N - V O L A T I L E   M E M O R Y   D R I V E R   H O O K   F U N C T I O N S
+****************************************************************************************/
+
+#if (BOOT_NVM_HOOKS_ENABLE > 0)
+/************************************************************************************//**
+** \brief     Callback that gets called at the start of the internal NVM driver
+**            initialization routine.
+** \return    none.
+**
+****************************************************************************************/
+void NvmInitHook(void)
+{
+} /*** end of NvmInitHook ***/
+
+
+/************************************************************************************//**
+** \brief     Callback that gets called at the start of a firmware update to reinitialize
+**            the NVM driver.
+** \return    none.
+**
+****************************************************************************************/
+void NvmReinitHook(void)
+{
+} /*** end of NvmReinitHook ***/
+
+
+/************************************************************************************//**
+** \brief     Callback that gets called at the start of the NVM driver write
+**            routine. It allows additional memory to be operated on. If the address
+**            is not within the range of the additional memory, then
+**            BLT_NVM_NOT_IN_RANGE must be returned to indicate that the data hasn't
+**            been written yet.
+** \param     addr Start address.
+** \param     len  Length in bytes.
+** \param     data Pointer to the data buffer.
+** \return    BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is
+**            not within the supported memory range, or BLT_NVM_ERROR is the write
+**            operation failed.
+**
+****************************************************************************************/
+blt_int8u NvmWriteHook(blt_addr addr, blt_int32u len, blt_int8u *data)
+{
+  return BLT_NVM_NOT_IN_RANGE;
+} /*** end of NvmWriteHook ***/
+
+
+/************************************************************************************//**
+** \brief     Callback that gets called at the start of the NVM driver erase
+**            routine. It allows additional memory to be operated on. If the address
+**            is not within the range of the additional memory, then
+**            BLT_NVM_NOT_IN_RANGE must be returned to indicate that the memory
+**            hasn't been erased yet.
+** \param     addr Start address.
+** \param     len  Length in bytes.
+** \return    BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is
+**            not within the supported memory range, or BLT_NVM_ERROR is the erase
+**            operation failed.
+**
+****************************************************************************************/
+blt_int8u NvmEraseHook(blt_addr addr, blt_int32u len)
+{
+  return BLT_NVM_NOT_IN_RANGE;
+} /*** end of NvmEraseHook ***/
+
+
+/************************************************************************************//**
+** \brief     Callback that gets called at the end of the NVM programming session.
+** \return    BLT_TRUE is successful, BLT_FALSE otherwise.
+**
+****************************************************************************************/
+blt_bool NvmDoneHook(void)
+{
+  return BLT_TRUE;
+} /*** end of NvmDoneHook ***/
+#endif /* BOOT_NVM_HOOKS_ENABLE > 0 */
+
+
+#if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0)
+/************************************************************************************//**
+** \brief     Verifies the checksum, which indicates that a valid user program is
+**            present and can be started.
+** \return    BLT_TRUE if successful, BLT_FALSE otherwise.
+**
+****************************************************************************************/
+blt_bool NvmVerifyChecksumHook(void)
+{
+  return BLT_TRUE;
+} /*** end of NvmVerifyChecksum ***/
+
+
+/************************************************************************************//**
+** \brief     Writes a checksum of the user program to non-volatile memory. This is
+**            performed once the entire user program has been programmed. Through
+**            the checksum, the bootloader can check if a valid user programming is
+**            present and can be started.
+** \return    BLT_TRUE if successful, BLT_FALSE otherwise.
+**
+****************************************************************************************/
+blt_bool NvmWriteChecksumHook(void)
+{
+  return BLT_TRUE;
+}
+#endif /* BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0 */
+
+
+/****************************************************************************************
+*   S E E D / K E Y   S E C U R I T Y   H O O K   F U N C T I O N S
+****************************************************************************************/
+
+#if (BOOT_XCP_SEED_KEY_ENABLE > 0)
+/************************************************************************************//**
+** \brief     Provides a seed to the XCP master that will be used for the key
+**            generation when the master attempts to unlock the specified resource.
+**            Called by the GET_SEED command.
+** \param     resource  Resource that the seed if requested for (XCP_RES_XXX).
+** \param     seed      Pointer to byte buffer wher the seed will be stored.
+** \return    Length of the seed in bytes.
+**
+****************************************************************************************/
+blt_int8u XcpGetSeedHook(blt_int8u resource, blt_int8u *seed)
+{
+  /* request seed for unlocking ProGraMming resource */
+  if ((resource & XCP_RES_PGM) != 0)
+  {
+    seed[0] = 0x55;
+  }
+
+  /* return seed length */
+  return 1;
+} /*** end of XcpGetSeedHook ***/
+
+
+/************************************************************************************//**
+** \brief     Called by the UNLOCK command and checks if the key to unlock the
+**            specified resource was correct. If so, then the resource protection
+**            will be removed.
+** \param     resource  resource to unlock (XCP_RES_XXX).
+** \param     key       pointer to the byte buffer holding the key.
+** \param     len       length of the key in bytes.
+** \return    1 if the key was correct, 0 otherwise.
+**
+****************************************************************************************/
+blt_int8u XcpVerifyKeyHook(blt_int8u resource, blt_int8u *key, blt_int8u len)
+{
+  /* suppress compiler warning for unused parameter */
+  len = len;
+
+  /* the example key algorithm in "libseednkey.dll" works as follows:
+   *  - PGM will be unlocked if key = seed - 1
+   */
+
+  /* check key for unlocking ProGraMming resource */
+  if ((resource == XCP_RES_PGM) && (key[0] == (0x55-1)))
+  {
+    /* correct key received for unlocking PGM resource */
+    return 1;
+  }
+
+  /* still here so key incorrect */
+  return 0;
+} /*** end of XcpVerifyKeyHook ***/
+#endif /* BOOT_XCP_SEED_KEY_ENABLE > 0 */
+
+
+/*********************************** end of hooks.c ************************************/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/ide/stm32h743.dep b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/ide/stm32h743.dep
new file mode 100644
index 00000000..3396031b
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/ide/stm32h743.dep
@@ -0,0 +1,1603 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<project>
+    <fileVersion>4</fileVersion>
+    <fileChecksum>1705512899</fileChecksum>
+    <configuration>
+        <name>stm32h743</name>
+        <outputs>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cortex.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_cortex.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_def.h</file>
+            <file>$PROJ_DIR$\..\lib\CMSIS\Include\cmsis_version.h</file>
+            <file>$PROJ_DIR$\..\lib\CMSIS\Device\ST\STM32H7xx\Include\stm32h743xx.h</file>
+            <file>$PROJ_DIR$\..\lib\CMSIS\Device\ST\STM32H7xx\Include\stm32h7xx.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32_USB_Device_Library\Core\Inc\usbd_ctlreq.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal.h</file>
+            <file>$PROJ_DIR$\..\lib\CMSIS\Device\ST\STM32H7xx\Include\system_stm32h7xx.h</file>
+            <file>$PROJ_DIR$\..\lib\CMSIS\Include\core_cm7.h</file>
+            <file>$PROJ_DIR$\..\lib\CMSIS\Include\mpu_armv7.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32_USB_Device_Library\Core\Src\usbd_core.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32_USB_Device_Library\Core\Inc\usbd_core.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32_USB_Device_Library\Core\Src\usbd_ctlreq.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32_USB_Device_Library\Core\Inc\usbd_def.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32_USB_Device_Library\Core\Src\usbd_ioreq.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32_USB_Device_Library\Core\Inc\usbd_ioreq.h</file>
+            <file>$PROJ_DIR$\..\lib\CMSIS\Include\cmsis_iccarm.h</file>
+            <file>$PROJ_DIR$\..\lib\CMSIS\Include\cmsis_compiler.h</file>
+            <file>$PROJ_DIR$\..\obj\assert.xcl</file>
+            <file>$PROJ_DIR$\..\obj\main.o</file>
+            <file>$PROJ_DIR$\..\obj\rs232.o</file>
+            <file>$TOOLKIT_DIR$\inc\c\iar_intrinsics_common.h</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_rcc_ex.xcl</file>
+            <file>$PROJ_DIR$\..\obj\backdoor.o</file>
+            <file>$PROJ_DIR$\..\obj\flash.o</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_pwr_ex.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_ll_rcc.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_gpio.o</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_gpio.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_ll_usart.o</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_dma.o</file>
+            <file>$PROJ_DIR$\..\obj\usbd_ioreq.xcl</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_mdma.__cstat.et</file>
+            <file>$TOOLKIT_DIR$\inc\c\DLib_Product_string.h</file>
+            <file>$PROJ_DIR$\..\obj\com.xcl</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_ll_exti.o</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_ll_gpio.xcl</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_i2c.xcl</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_i2c.o</file>
+            <file>$TOOLKIT_DIR$\inc\c\string.h</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_i2c.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\usbd_ioreq.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_pcd.o</file>
+            <file>$PROJ_DIR$\..\obj\openblt_stm32h743.map</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_ll_utils.xcl</file>
+            <file>$PROJ_DIR$\..\obj\cop.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_ll_utils.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_hsem.o</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\file.o</file>
+            <file>$PROJ_DIR$\..\obj\file.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_ll_gpio.o</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_rcc.o</file>
+            <file>$PROJ_DIR$\..\obj\com.o</file>
+            <file>$PROJ_DIR$\..\obj\led.o</file>
+            <file>$TOOLKIT_DIR$\lib\shb_l.a</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_pcd_ex.o</file>
+            <file>$PROJ_DIR$\..\obj\net.xcl</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_ll_rcc.xcl</file>
+            <file>$PROJ_DIR$\..\obj\usb.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_tim.o</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_ll_usb.o</file>
+            <file>$PROJ_DIR$\..\obj\boot.o</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_flash_ex.xcl</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_mdma.o</file>
+            <file>$PROJ_DIR$\..\obj\led.xcl</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_flash.o</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_ll_usart.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_ll_exti.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_pwr_ex.o</file>
+            <file>$PROJ_DIR$\..\obj\usbd_core.xcl</file>
+            <file>$PROJ_DIR$\..\obj\can.xcl</file>
+            <file>$TOOLKIT_DIR$\inc\c\ctype.h</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_pwr.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\usbd_bulk.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\can.o</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_dma.xcl</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_pcd_ex.xcl</file>
+            <file>$PROJ_DIR$\..\obj\cpu_comp.o</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_dma_ex.o</file>
+            <file>$PROJ_DIR$\..\obj\rs232.xcl</file>
+            <file>$PROJ_DIR$\..\obj\assert.o</file>
+            <file>$PROJ_DIR$\..\obj\cpu.o</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_ll_dma.xcl</file>
+            <file>$TOOLKIT_DIR$\inc\c\ysizet.h</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_cortex.o</file>
+            <file>$PROJ_DIR$\..\obj\system_stm32h7xx.__cstat.et</file>
+            <file>$PROJ_DIR$\..\stm32h743xx_flash.icf</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_tim_ex.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_cortex.__cstat.et</file>
+            <file>$TOOLKIT_DIR$\lib\rt7M_tl.a</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_ll_usb.xcl</file>
+            <file>$TOOLKIT_DIR$\inc\c\DLib_float_setup.h</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_flash_ex.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\usbd_ctlreq.xcl</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal.o</file>
+            <file>$PROJ_DIR$\..\obj\usbd_ioreq.o</file>
+            <file>$PROJ_DIR$\..\obj\xcp.xcl</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_flash.xcl</file>
+            <file>$PROJ_DIR$\..\obj\backdoor.xcl</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_tim.xcl</file>
+            <file>$TOOLKIT_DIR$\inc\c\stdio.h</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_i2c_ex.o</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_ll_utils.o</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_mdma.xcl</file>
+            <file>$PROJ_DIR$\..\bin\openblt_stm32h743.out</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_hsem.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\flash.xcl</file>
+            <file>$PROJ_DIR$\..\obj\usb.xcl</file>
+            <file>$TOOLKIT_DIR$\lib\m7M_tlv.a</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_gpio.xcl</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_flash.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\hooks.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\net.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal.xcl</file>
+            <file>$PROJ_DIR$\..\obj\timer.o</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_tim_ex.o</file>
+            <file>$PROJ_DIR$\..\obj\cpu.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_rcc.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\can.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\flash.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\usbd_core.o</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_fdcan.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_ll_dma.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_ll_usart.xcl</file>
+            <file>$PROJ_DIR$\..\obj\com.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_hsem.xcl</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_exti.xcl</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_rcc_ex.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_tim.__cstat.et</file>
+            <file>$TOOLKIT_DIR$\inc\c\math.h</file>
+            <file>$PROJ_DIR$\..\obj\backdoor.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_ll_exti.xcl</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_fdcan.xcl</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_exti.o</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_pcd.xcl</file>
+            <file>$PROJ_DIR$\..\obj\led.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\assert.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_pwr_ex.xcl</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_ll_gpio.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_i2c_ex.xcl</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_i2c_ex.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\usbd_ctlreq.o</file>
+            <file>$PROJ_DIR$\..\obj\nvm.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\usbd_core.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\nvm.xcl</file>
+            <file>$PROJ_DIR$\..\obj\cpu.xcl</file>
+            <file>$PROJ_DIR$\..\obj\xcp.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_pwr.xcl</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_dma_ex.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\stm32h743.pbd</file>
+            <file>$PROJ_DIR$\..\obj\usbd_desc.o</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_dma.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\usbd_bulk.o</file>
+            <file>$PROJ_DIR$\..\obj\usbd_conf.__cstat.et</file>
+            <file>$TOOLKIT_DIR$\inc\c\stdlib.h</file>
+            <file>$PROJ_DIR$\..\obj\boot.xcl</file>
+            <file>$PROJ_DIR$\..\obj\timer.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\main.xcl</file>
+            <file>$PROJ_DIR$\..\bin\openblt_stm32h743.srec</file>
+            <file>$PROJ_DIR$\..\obj\usbd_bulk.xcl</file>
+            <file>$PROJ_DIR$\..\obj\usbd_ctlreq.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_rcc.xcl</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_tim_ex.xcl</file>
+            <file>$PROJ_DIR$\..\obj\xcp.o</file>
+            <file>$PROJ_DIR$\..\obj\usbd_desc.xcl</file>
+            <file>$PROJ_DIR$\..\obj\system_stm32h7xx.o</file>
+            <file>$PROJ_DIR$\..\obj\usb.o</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_rcc_ex.o</file>
+            <file>$TOOLKIT_DIR$\inc\c\intrinsics.h</file>
+            <file>$PROJ_DIR$\..\obj\usbd_desc.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\system_stm32h7xx.xcl</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_fdcan.o</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_exti.__cstat.et</file>
+            <file>$TOOLKIT_DIR$\inc\c\DLib_Product_stdlib.h</file>
+            <file>$TOOLKIT_DIR$\inc\c\yvals.h</file>
+            <file>$PROJ_DIR$\..\obj\timer.xcl</file>
+            <file>$PROJ_DIR$\..\obj\boot.__cstat.et</file>
+            <file>$TOOLKIT_DIR$\inc\c\DLib_Defaults.h</file>
+            <file>$PROJ_DIR$\..\obj\cpu_comp.xcl</file>
+            <file>$TOOLKIT_DIR$\inc\c\stdint.h</file>
+            <file>$TOOLKIT_DIR$\inc\c\ycheck.h</file>
+            <file>$PROJ_DIR$\..\obj\startup_stm32h743xx.o</file>
+            <file>$PROJ_DIR$\..\obj\hooks.xcl</file>
+            <file>$PROJ_DIR$\..\obj\cop.xcl</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_pcd_ex.__cstat.et</file>
+            <file>$TOOLKIT_DIR$\inc\c\iccarm_builtin.h</file>
+            <file>$PROJ_DIR$\..\obj\file.xcl</file>
+            <file>$PROJ_DIR$\..\obj\hooks.o</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_flash.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hsem.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dma_ex.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dma.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_flash_ex.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pcd_ex.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mdma.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_gpio_ex.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_mdma.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pwr.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr_ex.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pcd.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_i2c.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_exti.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pcd.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pwr_ex.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c_ex.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash_ex.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_gpio.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_fdcan.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_fdcan.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pcd_ex.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_i2c_ex.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_gpio.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_exti.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma_ex.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_hsem.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_usb.c</file>
+            <file>$PROJ_DIR$\..\lib\stm32h7xx_hal_conf.h</file>
+            <file>$PROJ_DIR$\..\hooks.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_bus.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_dmamux.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim_ex.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_exti.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_exti.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_gpio.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_rcc.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_system.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_usb.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_rcc_ex.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_pwr.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_utils.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc_ex.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_rcc.h</file>
+            <file>$PROJ_DIR$\..\lib\system_stm32h7xx.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_utils.c</file>
+            <file>$PROJ_DIR$\..\blt_conf.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_rcc.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_dma.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_dma.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_gpio.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_usart.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_usart.h</file>
+            <file>$PROJ_DIR$\..\..\..\..\Source\assert.h</file>
+            <file>$PROJ_DIR$\..\led.h</file>
+            <file>$PROJ_DIR$\..\..\..\..\Source\ARMCM7_STM32H7\usb.c</file>
+            <file>$PROJ_DIR$\..\..\..\..\Source\ARMCM7_STM32H7\can.c</file>
+            <file>$PROJ_DIR$\..\usbd_bulk.h</file>
+            <file>$PROJ_DIR$\..\..\..\..\Source\ARMCM7_STM32H7\cpu.c</file>
+            <file>$PROJ_DIR$\..\..\..\..\Source\ARMCM7_STM32H7\flash.c</file>
+            <file>$PROJ_DIR$\..\..\..\..\Source\boot.h</file>
+            <file>$PROJ_DIR$\..\usbd_bulk.c</file>
+            <file>$PROJ_DIR$\..\..\..\..\Source\ARMCM7_STM32H7\IAR\cpu_comp.c</file>
+            <file>$PROJ_DIR$\..\..\..\..\Source\can.h</file>
+            <file>$PROJ_DIR$\..\..\..\..\Source\com.c</file>
+            <file>$PROJ_DIR$\..\..\..\..\Source\cop.c</file>
+            <file>$PROJ_DIR$\..\..\..\..\Source\cop.h</file>
+            <file>$PROJ_DIR$\..\..\..\..\Source\com.h</file>
+            <file>$PROJ_DIR$\..\..\..\..\Source\cpu.h</file>
+            <file>$PROJ_DIR$\..\..\..\..\Source\boot.c</file>
+            <file>$PROJ_DIR$\..\main.c</file>
+            <file>$PROJ_DIR$\..\led.c</file>
+            <file>$PROJ_DIR$\..\startup_stm32h743xx.s</file>
+            <file>$PROJ_DIR$\..\usbd_conf.c</file>
+            <file>$PROJ_DIR$\..\..\..\..\Source\ARMCM7_STM32H7\nvm.c</file>
+            <file>$PROJ_DIR$\..\..\..\..\Source\ARMCM7_STM32H7\rs232.c</file>
+            <file>$PROJ_DIR$\..\usbd_conf.h</file>
+            <file>$PROJ_DIR$\..\usbd_desc.c</file>
+            <file>$PROJ_DIR$\..\..\..\..\Source\ARMCM7_STM32H7\timer.c</file>
+            <file>$PROJ_DIR$\..\..\..\..\Source\ARMCM7_STM32H7\types.h</file>
+            <file>$PROJ_DIR$\..\..\..\..\Source\backdoor.h</file>
+            <file>$PROJ_DIR$\..\..\..\..\Source\assert.c</file>
+            <file>$PROJ_DIR$\..\..\..\..\Source\backdoor.c</file>
+            <file>$PROJ_DIR$\..\..\..\..\Source\ARMCM7_STM32H7\flash.h</file>
+            <file>$PROJ_DIR$\..\usbd_desc.h</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_flash_ex.o</file>
+            <file>$PROJ_DIR$\..\..\..\..\Source\file.c</file>
+            <file>$PROJ_DIR$\..\obj\usbd_conf.xcl</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_pcd.__cstat.et</file>
+            <file>$PROJ_DIR$\..\..\..\..\Source\file.h</file>
+            <file>$PROJ_DIR$\..\..\..\..\Source\usb.h</file>
+            <file>$PROJ_DIR$\..\obj\rs232.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\usbd_conf.o</file>
+            <file>$PROJ_DIR$\..\obj\cop.o</file>
+            <file>$PROJ_DIR$\..\..\..\..\Source\timer.h</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_cortex.xcl</file>
+            <file>$PROJ_DIR$\..\..\..\..\Source\xcp.h</file>
+            <file>$PROJ_DIR$\..\obj\nvm.o</file>
+            <file>$PROJ_DIR$\..\obj\cpu_comp.__cstat.et</file>
+            <file>$PROJ_DIR$\..\..\..\..\Source\rs232.h</file>
+            <file>$TOOLKIT_DIR$\inc\c\stddef.h</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_ll_rcc.o</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_ll_usb.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\net.o</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_dma_ex.xcl</file>
+            <file>$PROJ_DIR$\..\..\..\..\Source\net.c</file>
+            <file>$TOOLKIT_DIR$\lib\dl7M_tlf.a</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_ll_dma.o</file>
+            <file>$PROJ_DIR$\..\..\..\..\Source\net.h</file>
+            <file>$TOOLKIT_DIR$\inc\c\DLib_Product.h</file>
+            <file>$PROJ_DIR$\..\..\..\..\Source\xcp.c</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_pwr.o</file>
+            <file>$PROJ_DIR$\..\..\..\..\Source\plausibility.h</file>
+            <file>$TOOLKIT_DIR$\inc\c\DLib_Config_Full.h</file>
+            <file>$PROJ_DIR$\..\obj\main.__cstat.et</file>
+            <file>$PROJ_DIR$\..\..\..\..\Source\nvm.h</file>
+        </outputs>
+        <file>
+            <name>[ROOT_NODE]</name>
+            <outputs>
+                <tool>
+                    <name>ILINK</name>
+                    <file> 108 46</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 98</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 117</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 51</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 9 225 245 4 7 6 11 183 184 178 181 311 307 5 20 19 189 12 10 0 298 87 133 95 237 219 201 195 194 202 220 3 215 192 197 222 206 218 203 210 209 236 198</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cortex.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 88</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 293</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 92</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 9 225 245 4 7 6 11 183 184 178 181 311 307 5 20 19 189 12 10 0 298 87 133 95 237 219 201 195 194 202 220 3 215 192 197 222 206 218 203 210 209 236 198</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32_USB_Device_Library\Core\Src\usbd_core.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 124</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 73</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 147</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 14 274 104 184 178 181 311 307 87 158 177 42 36 7 6 11 183 5 20 19 189 12 10 9 225 245 4 0 298 133 95 237 219 201 195 194 202 220 3 215 192 197 222 206 218 203 210 209 236 198 16 18 8</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32_USB_Device_Library\Core\Src\usbd_ctlreq.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 145</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 97</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 164</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 8 16 274 104 184 178 181 311 307 87 158 177 42 36 7 6 11 183 5 20 19 189 12 10 9 225 245 4 0 298 133 95 237 219 201 195 194 202 220 3 215 192 197 222 206 218 203 210 209 236 198 18 14</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32_USB_Device_Library\Core\Src\usbd_ioreq.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 99</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 34</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 44</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 18 16 274 104 184 178 181 311 307 87 158 177 42 36 7 6 11 183 5 20 19 189 12 10 9 225 245 4 0 298 133 95 237 219 201 195 194 202 220 3 215 192 197 222 206 218 203 210 209 236 198 14 8</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\bin\openblt_stm32h743.out</name>
+            <outputs>
+                <tool>
+                    <name>ILINK</name>
+                    <file> 46</file>
+                </tool>
+                <tool>
+                    <name>OBJCOPY</name>
+                    <file> 162</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ILINK</name>
+                    <file> 90 84 26 65 78 56 291 85 81 52 27 191 57 22 301 295 23 185 98 88 33 82 137 175 69 283 30 50 41 105 67 45 59 309 72 55 171 63 119 305 38 54 299 32 64 106 169 118 170 156 290 124 145 154 99 167 58 93 112 304</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hsem.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 50</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 129</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 109</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 9 225 245 4 7 6 11 183 184 178 181 311 307 5 20 19 189 12 10 0 298 87 133 95 237 219 201 195 194 202 220 3 215 192 197 222 206 218 203 210 209 236 198</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 41</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 40</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 43</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 9 225 245 4 7 6 11 183 184 178 181 311 307 5 20 19 189 12 10 0 298 87 133 95 237 219 201 195 194 202 220 3 215 192 197 222 206 218 203 210 209 236 198</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mdma.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 67</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 107</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 35</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 9 225 245 4 7 6 11 183 184 178 181 311 307 5 20 19 189 12 10 0 298 87 133 95 237 219 201 195 194 202 220 3 215 192 197 222 206 218 203 210 209 236 198</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 33</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 79</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 155</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 9 225 245 4 7 6 11 183 184 178 181 311 307 5 20 19 189 12 10 0 298 87 133 95 237 219 201 195 194 202 220 3 215 192 197 222 206 218 203 210 209 236 198</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr_ex.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 72</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 141</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 28</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 9 225 245 4 7 6 11 183 184 178 181 311 307 5 20 19 189 12 10 0 298 87 133 95 237 219 201 195 194 202 220 3 215 192 197 222 206 218 203 210 209 236 198</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pcd.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 45</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 138</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 286</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 9 225 245 4 7 6 11 183 184 178 181 311 307 5 20 19 189 12 10 0 298 87 133 95 237 219 201 195 194 202 220 3 215 192 197 222 206 218 203 210 209 236 198</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_exti.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 137</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 130</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 176</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 9 225 245 4 7 6 11 183 184 178 181 311 307 5 20 19 189 12 10 0 298 87 133 95 237 219 201 195 194 202 220 3 215 192 197 222 206 218 203 210 209 236 198</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 69</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 101</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 114</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 9 225 245 4 7 6 11 183 184 178 181 311 307 5 20 19 189 12 10 0 298 87 133 95 237 219 201 195 194 202 220 3 215 192 197 222 206 218 203 210 209 236 198</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c_ex.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 105</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 143</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 144</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 9 225 245 4 7 6 11 183 184 178 181 311 307 5 20 19 189 12 10 0 298 87 133 95 237 219 201 195 194 202 220 3 215 192 197 222 206 218 203 210 209 236 198</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash_ex.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 283</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 66</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 96</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 9 225 245 4 7 6 11 183 184 178 181 311 307 5 20 19 189 12 10 0 298 87 133 95 237 219 201 195 194 202 220 3 215 192 197 222 206 218 203 210 209 236 198</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_gpio.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 30</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 113</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 31</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 9 225 245 4 7 6 11 183 184 178 181 311 307 5 20 19 189 12 10 0 298 87 133 95 237 219 201 195 194 202 220 3 215 192 197 222 206 218 203 210 209 236 198</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_fdcan.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 175</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 136</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 125</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 9 225 245 4 7 6 11 183 184 178 181 311 307 5 20 19 189 12 10 0 298 87 133 95 237 219 201 195 194 202 220 3 215 192 197 222 206 218 203 210 209 236 198</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pcd_ex.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 59</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 80</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 188</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 9 225 245 4 7 6 11 183 184 178 181 311 307 5 20 19 189 12 10 0 298 87 133 95 237 219 201 195 194 202 220 3 215 192 197 222 206 218 203 210 209 236 198</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 55</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 165</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 121</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 9 225 245 4 7 6 11 183 184 178 181 311 307 5 20 19 189 12 10 0 298 87 133 95 237 219 201 195 194 202 220 3 215 192 197 222 206 218 203 210 209 236 198</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma_ex.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 82</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 302</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 152</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 9 225 245 4 7 6 11 183 184 178 181 311 307 5 20 19 189 12 10 0 298 87 133 95 237 219 201 195 194 202 220 3 215 192 197 222 206 218 203 210 209 236 198</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 309</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 151</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 76</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 9 225 245 4 7 6 11 183 184 178 181 311 307 5 20 19 189 12 10 0 298 87 133 95 237 219 201 195 194 202 220 3 215 192 197 222 206 218 203 210 209 236 198</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_usb.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 64</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 94</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 300</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 9 225 245 4 7 6 11 183 184 178 181 311 307 5 20 19 189 12 10 0 298 87 133 95 237 219 201 195 194 202 220 3 215 192 197 222 206 218 203 210 209 236 198</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\hooks.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 191</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 186</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 115</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 258 277 251 244 310 266 264 313 292 278 287 265 294 252 7 6 11 183 184 178 181 311 307 5 20 19 189 12 10 9 225 245 4 0 298 87 133 95 237 219 201 195 194 202 220 3 215 192 197 222 206 218 203 210 209 236 198 233</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 63</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 103</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 132</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 9 225 245 4 7 6 11 183 184 178 181 311 307 5 20 19 189 12 10 0 298 87 133 95 237 219 201 195 194 202 220 3 215 192 197 222 206 218 203 210 209 236 198</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim_ex.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 119</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 166</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 91</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 9 225 245 4 7 6 11 183 184 178 181 311 307 5 20 19 189 12 10 0 298 87 133 95 237 219 201 195 194 202 220 3 215 192 197 222 206 218 203 210 209 236 198</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_exti.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 38</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 135</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 71</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 232 7 6 11 183 184 178 181 311 307 5 20 19 189 12 10 9 225 245 4 0 298 87 133 95 237 219 201 195 194 202 220 3 215 192 197 222 206 218 203 210 209 236 198</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_rcc.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 299</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 61</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 29</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 241 7 6 11 183 184 178 181 311 307 5 20 19 189 12 10 9 225 245 4 0 298 87 133 95 237 219 201 195 194 202 220 3 215 192 197 222 206 218 203 210 209 236 198 227</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc_ex.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 171</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 25</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 131</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 9 225 245 4 7 6 11 183 184 178 181 311 307 5 20 19 189 12 10 0 298 87 133 95 237 219 201 195 194 202 220 3 215 192 197 222 206 218 203 210 209 236 198</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\system_stm32h7xx.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 169</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 174</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 89</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 7 6 11 183 184 178 181 311 307 5 20 19 189 12 10 9 225 245 4 0 298 87 133 95 237 219 201 195 194 202 220 3 215 192 197 222 206 218 203 210 209 236 198</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_utils.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 106</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 47</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 49</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 239 7 6 11 183 184 178 181 311 307 5 20 19 189 12 10 9 225 245 4 0 298 87 133 95 237 219 201 195 194 202 220 3 215 192 197 222 206 218 203 210 209 236 198 235 227 241 238</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_dma.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 305</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 86</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 126</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 247 7 6 11 183 184 178 181 311 307 5 20 19 189 12 10 9 225 245 4 0 298 87 133 95 237 219 201 195 194 202 220 3 215 192 197 222 206 218 203 210 209 236 198 229 227</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_gpio.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 54</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 39</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 142</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 233 7 6 11 183 184 178 181 311 307 5 20 19 189 12 10 9 225 245 4 0 298 87 133 95 237 219 201 195 194 202 220 3 215 192 197 222 206 218 203 210 209 236 198 227</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_usart.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 32</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 127</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 70</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 250 7 6 11 183 184 178 181 311 307 5 20 19 189 12 10 9 225 245 4 0 298 87 133 95 237 219 201 195 194 202 220 3 215 192 197 222 206 218 203 210 209 236 198 241 227</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\ARMCM7_STM32H7\usb.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 170</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 111</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 62</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 258 277 251 244 310 266 264 313 292 278 287 265 294 288 14 274 104 184 178 181 311 307 87 158 177 42 36 7 6 11 183 5 20 19 189 12 10 9 225 245 4 0 298 133 95 237 219 201 195 194 202 220 3 215 192 197 222 206 218 203 210 209 236 198 16 18 8 282 255</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\ARMCM7_STM32H7\can.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 78</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 74</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 122</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 258 277 251 244 310 266 264 313 292 278 287 265 294 7 6 11 183 184 178 181 311 307 5 20 19 189 12 10 9 225 245 4 0 298 87 133 95 237 219 201 195 194 202 220 3 215 192 197 222 206 218 203 210 209 236 198 241</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\ARMCM7_STM32H7\cpu.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 85</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 149</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 120</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 258 277 251 244 310 266 264 313 292 278 287 265 294 7 6 11 183 184 178 181 311 307 5 20 19 189 12 10 9 225 245 4 0 298 87 133 95 237 219 201 195 194 202 220 3 215 192 197 222 206 218 203 210 209 236 198</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\ARMCM7_STM32H7\flash.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 27</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 110</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 123</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 258 277 251 244 310 266 264 313 292 278 287 265 294 7 6 11 183 184 178 181 311 307 5 20 19 189 12 10 9 225 245 4 0 298 87 133 95 237 219 201 195 194 202 220 3 215 192 197 222 206 218 203 210 209 236 198</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\usbd_bulk.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 156</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 163</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 77</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 255 18 16 274 104 184 178 181 311 307 87 158 177 42 36 7 6 11 183 5 20 19 189 12 10 9 225 245 4 0 298 133 95 237 219 201 195 194 202 220 3 215 192 197 222 206 218 203 210 209 236 198 14 8 282</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\ARMCM7_STM32H7\IAR\cpu_comp.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 81</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 182</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 296</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 258 277 251 244 310 266 264 313 292 278 287 265 294 172 189 178 181 311 307 24</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\com.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 56</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 37</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 128</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 258 277 251 244 310 266 264 313 292 278 287 265 294 261 297 288</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\cop.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 291</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 187</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 48</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 258 277 251 244 310 266 264 313 292 278 287 265 294</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\boot.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 65</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 159</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 180</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 258 277 251 244 310 266 264 313 292 278 287 265 294</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\main.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 22</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 161</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 312</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 258 277 251 244 310 266 264 313 292 278 287 265 294 7 6 11 183 184 178 181 311 307 5 20 19 189 12 10 9 225 245 4 0 298 87 133 95 237 219 201 195 194 202 220 3 215 192 197 222 206 218 203 210 209 236 198 238 241 239 235 227 233</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\led.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 57</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 68</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 139</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 258 277 251 244 310 266 264 313 292 278 287 265 294 252 7 6 11 183 184 178 181 311 307 5 20 19 189 12 10 9 225 245 4 0 298 87 133 95 237 219 201 195 194 202 220 3 215 192 197 222 206 218 203 210 209 236 198 233</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\startup_stm32h743xx.s</name>
+            <outputs>
+                <tool>
+                    <name>AARM</name>
+                    <file> 185</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\usbd_conf.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 290</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 285</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 157</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 7 6 11 183 184 178 181 311 307 5 20 19 189 12 10 9 225 245 4 0 298 87 133 95 237 219 201 195 194 202 220 3 215 192 197 222 206 218 203 210 209 236 198 16 274 104 158 177 42 36 14 18 8 255 258 277 251 244 310 266 264 313 292 278 287 265 294 288</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\ARMCM7_STM32H7\nvm.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 295</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 148</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 146</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 258 277 251 244 310 266 264 313 292 278 287 265 294 281</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\ARMCM7_STM32H7\rs232.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 23</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 83</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 289</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 258 277 251 244 310 266 264 313 292 278 287 265 294 7 6 11 183 184 178 181 311 307 5 20 19 189 12 10 9 225 245 4 0 298 87 133 95 237 219 201 195 194 202 220 3 215 192 197 222 206 218 203 210 209 236 198 250</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\usbd_desc.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 154</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 168</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 173</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 14 274 104 184 178 181 311 307 87 158 177 42 36 7 6 11 183 5 20 19 189 12 10 9 225 245 4 0 298 133 95 237 219 201 195 194 202 220 3 215 192 197 222 206 218 203 210 209 236 198 16 18 8 282</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\ARMCM7_STM32H7\timer.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 118</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 179</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 160</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 258 277 251 244 310 266 264 313 292 278 287 265 294 7 6 11 183 184 178 181 311 307 5 20 19 189 12 10 9 225 245 4 0 298 87 133 95 237 219 201 195 194 202 220 3 215 192 197 222 206 218 203 210 209 236 198</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\assert.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 84</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 21</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 140</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 258 277 251 244 310 266 264 313 292 278 287 265 294</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\backdoor.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 26</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 102</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 134</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 258 277 251 244 310 266 264 313 292 278 287 265 294</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\file.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 52</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 190</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 53</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 258 277 251 244 310 266 264 313 292 278 287 265 294 42 184 178 181 311 307 87 36 75</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\net.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 301</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 60</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 116</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 258 277 251 244 310 266 264 313 292 278 287 265 294</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\xcp.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 167</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 100</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 150</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 258 277 251 244 310 266 264 313 292 278 287 265 294</file>
+                </tool>
+            </inputs>
+        </file>
+    </configuration>
+</project>
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/ide/stm32h743.ewd b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/ide/stm32h743.ewd
new file mode 100644
index 00000000..04d8cc97
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/ide/stm32h743.ewd
@@ -0,0 +1,1489 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<project>
+    <fileVersion>3</fileVersion>
+    <configuration>
+        <name>stm32h743</name>
+        <toolchain>
+            <name>ARM</name>
+        </toolchain>
+        <debug>1</debug>
+        <settings>
+            <name>C-SPY</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>32</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>CInput</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CEndian</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCVariant</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MacOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MacFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>MemOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MemFile</name>
+                    <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\STM32H743ZI.ddf</state>
+                </option>
+                <option>
+                    <name>RunToEnable</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RunToName</name>
+                    <state>main</state>
+                </option>
+                <option>
+                    <name>CExtraOptionsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CExtraOptions</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CFpuProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCDDFArgumentProducer</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCDownloadSuppressDownload</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCDownloadVerifyAll</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCProductVersion</name>
+                    <state>7.10.3.6927</state>
+                </option>
+                <option>
+                    <name>OCDynDriverList</name>
+                    <state>STLINK_ID</state>
+                </option>
+                <option>
+                    <name>OCLastSavedByProductVersion</name>
+                    <state>8.50.4.26131</state>
+                </option>
+                <option>
+                    <name>UseFlashLoader</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CLowLevel</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCBE8Slave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>MacFile2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CDevice</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>FlashLoadersV3</name>
+                    <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32H7xxxI.board</state>
+                </option>
+                <option>
+                    <name>OCImagesSuppressCheck1</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesPath1</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesSuppressCheck2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesPath2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesSuppressCheck3</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesPath3</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OverrideDefFlashBoard</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCImagesOffset1</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesOffset2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesOffset3</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesUse1</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesUse2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesUse3</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCDeviceConfigMacroFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCDebuggerExtraOption</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCAllMTBOptions</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCMulticoreNrOfCores</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCMulticoreWorkspace</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCMulticoreSlaveProject</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCMulticoreSlaveConfiguration</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCDownloadExtraImage</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCAttachSlave</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MassEraseBeforeFlashing</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCMulticoreNrOfCoresSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCMulticoreAMPConfigType</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCMulticoreSessionFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCTpiuBaseOption</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>ARMSIM_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>1</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCSimDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCSimEnablePSP</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCSimPspOverrideConfig</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCSimPspConfigFile</name>
+                    <state></state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>CADI_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>CCadiMemory</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>Fast Model</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCADILogFileCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCADILogFileEditB</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>CMSISDAP_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>4</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>CatchSFERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCIarProbeScriptFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CMSISDAPResetList</name>
+                    <version>1</version>
+                    <state>10</state>
+                </option>
+                <option>
+                    <name>CMSISDAPHWResetDuration</name>
+                    <state>300</state>
+                </option>
+                <option>
+                    <name>CMSISDAPHWResetDelay</name>
+                    <state>200</state>
+                </option>
+                <option>
+                    <name>CMSISDAPDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CMSISDAPInterfaceRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiTargetEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPJtagSpeedList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPRestoreBreakpointsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPUpdateBreakpointsEdit</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>RDICatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchUndef</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchData</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchPrefetch</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchMMERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchNOCPERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchCHKERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchSTATERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchBUSERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchINTERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchHARDERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiCPUEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiCPUNumber</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeCfgOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeConfig</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CMSISDAPProbeConfigRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPSelectedCPUBehaviour</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>ICpuName</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCJetEmuParams</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCCMSISDAPUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCCMSISDAPUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>GDBSERVER_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>TCPIP</name>
+                    <state>aaa.bbb.ccc.ddd</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCJTagBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJTagDoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJTagUpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>IJET_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>8</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>CatchSFERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCIarProbeScriptFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetResetList</name>
+                    <version>1</version>
+                    <state>10</state>
+                </option>
+                <option>
+                    <name>IjetHWResetDuration</name>
+                    <state>300</state>
+                </option>
+                <option>
+                    <name>IjetHWResetDelay</name>
+                    <state>200</state>
+                </option>
+                <option>
+                    <name>IjetPowerFromProbe</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetPowerRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>IjetInterfaceRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetMultiTargetEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetScanChainNonARMDevices</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetIRLength</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetJtagSpeedList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetProtocolRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetSwoPin</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetCpuClockEdit</name>
+                    <state>72.0</state>
+                </option>
+                <option>
+                    <name>IjetSwoPrescalerList</name>
+                    <version>1</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetRestoreBreakpointsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetUpdateBreakpointsEdit</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>RDICatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchUndef</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchData</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchPrefetch</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchMMERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchNOCPERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchCHKERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchSTATERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchBUSERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchINTERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchHARDERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeCfgOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeConfig</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IjetProbeConfigRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetMultiCPUEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetMultiCPUNumber</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetSelectedCPUBehaviour</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>ICpuName</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCJetEmuParams</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetPreferETB</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetTraceSettingsList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetTraceSizeList</name>
+                    <version>0</version>
+                    <state>4</state>
+                </option>
+                <option>
+                    <name>FlashBoardPathSlave</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCIjetUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCIjetUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>JLINK_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>16</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>CCCatchSFERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>JLinkSpeed</name>
+                    <state>1000</state>
+                </option>
+                <option>
+                    <name>CCJLinkDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCJLinkHWResetDelay</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>JLinkInitialSpeed</name>
+                    <state>1000</state>
+                </option>
+                <option>
+                    <name>CCDoJlinkMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCScanChainNonARMDevices</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkIRLength</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkCommRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkTCPIP</name>
+                    <state>aaa.bbb.ccc.ddd</state>
+                </option>
+                <option>
+                    <name>CCJLinkSpeedRadioV2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCUSBDevice</name>
+                    <version>1</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCRDICatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchUndef</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchData</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchPrefetch</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkDoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkUpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>CCJLinkInterfaceRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkResetList</name>
+                    <version>6</version>
+                    <state>7</state>
+                </option>
+                <option>
+                    <name>CCJLinkInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchMMERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchNOCPERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchCHRERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchSTATERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchBUSERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchINTERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchHARDERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCJLinkScriptFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCJLinkUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCTcpIpAlt</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkTcpIpSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCCpuClockEdit</name>
+                    <state>72.0</state>
+                </option>
+                <option>
+                    <name>CCSwoClockAuto</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSwoClockEdit</name>
+                    <state>2000</state>
+                </option>
+                <option>
+                    <name>OCJLinkTraceSource</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCJLinkTraceSourceDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCJLinkDeviceName</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>LMIFTDI_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>2</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>LmiftdiSpeed</name>
+                    <state>500</state>
+                </option>
+                <option>
+                    <name>CCLmiftdiDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCLmiftdiLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCLmiFtdiInterfaceRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCLmiFtdiInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>NULINK_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>PEMICRO_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>3</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCJPEMicroShowSettings</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>STLINK_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>7</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCSTLinkInterfaceRadio</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCSTLinkInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkResetList</name>
+                    <version>3</version>
+                    <state>4</state>
+                </option>
+                <option>
+                    <name>CCCpuClockEdit</name>
+                    <state>64.0</state>
+                </option>
+                <option>
+                    <name>CCSwoClockAuto</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSwoClockEdit</name>
+                    <state>2000</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCSTLinkDoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkUpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchMMERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchNOCPERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchCHRERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchSTATERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchBUSERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchINTERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchSFERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchHARDERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSTLinkUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkJtagSpeedList</name>
+                    <version>2</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkDAPNumber</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSTLinkDebugAccessPortRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkUseServerSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkProbeList</name>
+                    <version>1</version>
+                    <state>2</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>THIRDPARTY_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>CThirdPartyDriverDll</name>
+                    <state>###Uninitialized###</state>
+                </option>
+                <option>
+                    <name>CThirdPartyLogFileCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CThirdPartyLogFileEditB</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>TIFET_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>1</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCMSPFetResetList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetInterfaceRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetTargetVccTypeDefault</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetTargetVoltage</name>
+                    <state>###Uninitialized###</state>
+                </option>
+                <option>
+                    <name>CCMSPFetVCCDefault</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCMSPFetTargetSettlingtime</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetRadioJtagSpeedType</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCMSPFetConnection</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetUsbComPort</name>
+                    <state>Automatic</state>
+                </option>
+                <option>
+                    <name>CCMSPFetAllowAccessToBSL</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCMSPFetRadioEraseFlash</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>XDS100_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>8</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>TIPackageOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>TIPackage</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>BoardFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCXds100BreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100DoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100UpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchUndef</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchData</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchPrefetch</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchMMERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchNOCPERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchCHRERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchSTATERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchBUSERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchINTERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchSFERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchHARDERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCXds100SwoClockAuto</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100SwoClockEdit</name>
+                    <state>1000</state>
+                </option>
+                <option>
+                    <name>CCXds100HWResetDelay</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100ResetList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100UsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCXds100UsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100JtagSpeedList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100InterfaceRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100InterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100ProbeList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100SWOPortRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100SWOPort</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCXDSTargetVccEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXDSTargetVoltage</name>
+                    <state>###Uninitialized###</state>
+                </option>
+                <option>
+                    <name>OCXDSDigitalStatesConfigFile</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <debuggerPlugins>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\RemedyRtosViewer\RemedyRtosViewer.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8b.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8bBE.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+        </debuggerPlugins>
+    </configuration>
+</project>
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/ide/stm32h743.ewp b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/ide/stm32h743.ewp
new file mode 100644
index 00000000..5bd821f7
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/ide/stm32h743.ewp
@@ -0,0 +1,1522 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<project>
+    <fileVersion>3</fileVersion>
+    <configuration>
+        <name>stm32h743</name>
+        <toolchain>
+            <name>ARM</name>
+        </toolchain>
+        <debug>1</debug>
+        <settings>
+            <name>General</name>
+            <archiveVersion>3</archiveVersion>
+            <data>
+                <version>31</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>ExePath</name>
+                    <state>$PROJ_DIR$\..\bin</state>
+                </option>
+                <option>
+                    <name>ObjPath</name>
+                    <state>$PROJ_DIR$\..\obj</state>
+                </option>
+                <option>
+                    <name>ListPath</name>
+                    <state>$PROJ_DIR$\..\obj</state>
+                </option>
+                <option>
+                    <name>GEndianMode</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>Input description</name>
+                    <state>Full formatting, with multibyte support.</state>
+                </option>
+                <option>
+                    <name>Output description</name>
+                    <state>Full formatting, with multibyte support.</state>
+                </option>
+                <option>
+                    <name>GOutputBinary</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGCoreOrChip</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>GRuntimeLibSelect</name>
+                    <version>0</version>
+                    <state>2</state>
+                </option>
+                <option>
+                    <name>GRuntimeLibSelectSlave</name>
+                    <version>0</version>
+                    <state>2</state>
+                </option>
+                <option>
+                    <name>RTDescription</name>
+                    <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
+                </option>
+                <option>
+                    <name>OGProductVersion</name>
+                    <state>4.41A</state>
+                </option>
+                <option>
+                    <name>OGLastSavedByProductVersion</name>
+                    <state>8.50.4.26131</state>
+                </option>
+                <option>
+                    <name>GeneralEnableMisra</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GeneralMisraVerbose</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGChipSelectEditMenu</name>
+                    <state>STM32H743ZI	ST STM32H743ZI</state>
+                </option>
+                <option>
+                    <name>GenLowLevelInterface</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>GEndianModeBE</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OGBufferedTerminalOutput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenStdoutInterface</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GeneralMisraRules98</name>
+                    <version>0</version>
+                    <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+                </option>
+                <option>
+                    <name>GeneralMisraVer</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GeneralMisraRules04</name>
+                    <version>0</version>
+                    <state>011111111111111110111111111111011111111111111011110100111111111111111111111111111111111111111111101111111111111011111111111111111111111111111</state>
+                </option>
+                <option>
+                    <name>RTConfigPath2</name>
+                    <state>$TOOLKIT_DIR$\inc\c\DLib_Config_Full.h</state>
+                </option>
+                <option>
+                    <name>GBECoreSlave</name>
+                    <version>28</version>
+                    <state>41</state>
+                </option>
+                <option>
+                    <name>OGUseCmsis</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGUseCmsisDspLib</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GRuntimeLibThreads</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CoreVariant</name>
+                    <version>28</version>
+                    <state>41</state>
+                </option>
+                <option>
+                    <name>GFPUDeviceSlave</name>
+                    <state>STM32H743ZI	ST STM32H743ZI</state>
+                </option>
+                <option>
+                    <name>FPU2</name>
+                    <version>0</version>
+                    <state>7</state>
+                </option>
+                <option>
+                    <name>NrRegs</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>NEON</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GFPUCoreSlave2</name>
+                    <version>28</version>
+                    <state>41</state>
+                </option>
+                <option>
+                    <name>OGCMSISPackSelectDevice</name>
+                </option>
+                <option>
+                    <name>OgLibHeap</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGLibAdditionalLocale</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGPrintfVariant</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OGPrintfMultibyteSupport</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OGScanfVariant</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OGScanfMultibyteSupport</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>GenLocaleTags</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>GenLocaleDisplayOnly</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>DSPExtension</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>TrustZone</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>TrustZoneModes</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>ICCARM</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>36</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>CCOptimizationNoSizeConstraints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCDefines</name>
+                    <state>USE_FULL_LL_DRIVER</state>
+                    <state>USE_HAL_DRIVER</state>
+                    <state>STM32H743xx</state>
+                </option>
+                <option>
+                    <name>CCPreprocFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPreprocComments</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPreprocLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListCFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListCMnemonics</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListCMessages</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListAssFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListAssSource</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCEnableRemarks</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCDiagSuppress</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCDiagRemark</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCDiagWarning</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCDiagError</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCObjPrefix</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCAllowList</name>
+                    <version>1</version>
+                    <state>00000000</state>
+                </option>
+                <option>
+                    <name>CCDebugInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IEndianMode</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IExtraOptionsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IExtraOptions</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCLangConformance</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSignedPlainChar</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCRequirePrototypes</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCDiagWarnAreErr</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCompilerRuntimeInfo</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IFpuProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OutputFile</name>
+                    <state>$FILE_BNAME$.o</state>
+                </option>
+                <option>
+                    <name>CCLibConfigHeader</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>PreInclude</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CompilerMisraOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCIncludePath2</name>
+                    <state>$PROJ_DIR$\..</state>
+                    <state>$PROJ_DIR$\..\lib</state>
+                    <state>$PROJ_DIR$\..\lib\CMSIS\Include</state>
+                    <state>$PROJ_DIR$\..\lib\CMSIS\Device\ST\STM32H7xx\Include</state>
+                    <state>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc</state>
+                    <state>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\Legacy</state>
+                    <state>$PROJ_DIR$\..\lib\STM32_USB_Device_Library\Core\Inc</state>
+                    <state>$PROJ_DIR$\..\..\..\..\Source</state>
+                    <state>$PROJ_DIR$\..\..\..\..\Source\ARMCM7_STM32H7</state>
+                </option>
+                <option>
+                    <name>CCStdIncCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCodeSection</name>
+                    <state>.text</state>
+                </option>
+                <option>
+                    <name>IProcessorMode2</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCOptLevel</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCOptStrategy</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCOptLevelSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CompilerMisraRules98</name>
+                    <version>0</version>
+                    <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+                </option>
+                <option>
+                    <name>CompilerMisraRules04</name>
+                    <version>0</version>
+                    <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+                </option>
+                <option>
+                    <name>CCPosIndRopi</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPosIndRwpi</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPosIndNoDynInit</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccLang</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccCDialect</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IccAllowVLA</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccStaticDestr</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccCppInlineSemantics</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccCmsis</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IccFloatSemantics</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCNoLiteralPool</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCOptStrategySlave</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCGuardCalls</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCEncSource</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCEncOutput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCEncOutputBom</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCEncInput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccExceptions2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccRTTI2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OICompilerExtraOption</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCStackProtection</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>AARM</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>10</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>AObjPrefix</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AEndian</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>ACaseSensitivity</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>MacroChars</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AWarnEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AWarnWhat</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AWarnOne</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AWarnRange1</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AWarnRange2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>ADebug</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AltRegisterNames</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>ADefines</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AList</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AListHeader</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AListing</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>Includes</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MacDefs</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MacExps</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>MacExec</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OnlyAssed</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MultiLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>PageLengthCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>PageLength</name>
+                    <state>80</state>
+                </option>
+                <option>
+                    <name>TabSpacing</name>
+                    <state>8</state>
+                </option>
+                <option>
+                    <name>AXRef</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AXRefDefines</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AXRefInternal</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AXRefDual</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AFpuProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AOutputFile</name>
+                    <state>$FILE_BNAME$.o</state>
+                </option>
+                <option>
+                    <name>ALimitErrorsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>ALimitErrorsEdit</name>
+                    <state>100</state>
+                </option>
+                <option>
+                    <name>AIgnoreStdInclude</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AUserIncludes</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AExtraOptionsCheckV2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AExtraOptionsV2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AsmNoLiteralPool</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>OBJCOPY</name>
+            <archiveVersion>0</archiveVersion>
+            <data>
+                <version>1</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OOCOutputFormat</name>
+                    <version>3</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCOutputOverride</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OOCOutputFile</name>
+                    <state>openblt_stm32h743.srec</state>
+                </option>
+                <option>
+                    <name>OOCCommandLineProducer</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OOCObjCopyEnable</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>CUSTOM</name>
+            <archiveVersion>3</archiveVersion>
+            <data>
+                <extensions></extensions>
+                <cmdline></cmdline>
+                <hasPrio>0</hasPrio>
+            </data>
+        </settings>
+        <settings>
+            <name>BICOMP</name>
+            <archiveVersion>0</archiveVersion>
+            <data />
+        </settings>
+        <settings>
+            <name>BUILDACTION</name>
+            <archiveVersion>1</archiveVersion>
+            <data>
+                <prebuild></prebuild>
+                <postbuild></postbuild>
+            </data>
+        </settings>
+        <settings>
+            <name>ILINK</name>
+            <archiveVersion>0</archiveVersion>
+            <data>
+                <version>23</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>IlinkLibIOConfig</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>XLinkMisraHandler</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkInputFileSlave</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkOutputFile</name>
+                    <state>openblt_stm32h743.out</state>
+                </option>
+                <option>
+                    <name>IlinkDebugInfoEnable</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkKeepSymbols</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySymbol</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySegment</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryAlign</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkDefines</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkConfigDefines</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkMapFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkLogFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogInitialization</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogModule</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogSection</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogVeneer</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIcfOverride</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkIcfFile</name>
+                    <state>$PROJ_DIR$\..\stm32h743xx_flash.icf</state>
+                </option>
+                <option>
+                    <name>IlinkIcfFileSlave</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkEnableRemarks</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkSuppressDiags</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkTreatAsRem</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkTreatAsWarn</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkTreatAsErr</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkWarningsAreErrors</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkUseExtraOptions</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkExtraOptions</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkLowLevelInterfaceSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkAutoLibEnable</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkAdditionalLibs</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkOverrideProgramEntryLabel</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkProgramEntryLabelSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkProgramEntryLabel</name>
+                    <state>__iar_program_start</state>
+                </option>
+                <option>
+                    <name>DoFill</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>FillerByte</name>
+                    <state>0xFF</state>
+                </option>
+                <option>
+                    <name>FillerStart</name>
+                    <state>0x0</state>
+                </option>
+                <option>
+                    <name>FillerEnd</name>
+                    <state>0x0</state>
+                </option>
+                <option>
+                    <name>CrcSize</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcAlign</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcPoly</name>
+                    <state>0x11021</state>
+                </option>
+                <option>
+                    <name>CrcCompl</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CrcBitOrder</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CrcInitialValue</name>
+                    <state>0x0</state>
+                </option>
+                <option>
+                    <name>DoCrc</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkBE8Slave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkBufferedTerminalOutput</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkStdoutInterfaceSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcFullSize</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIElfToolPostProcess</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogAutoLibSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogRedirSymbols</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogUnusedFragments</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCrcReverseByteOrder</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCrcUseAsInput</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptInline</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkOptExceptionsAllow</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptExceptionsForce</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCmsis</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptMergeDuplSections</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkOptUseVfe</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptForceVfe</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkStackAnalysisEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkStackControlFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkStackCallGraphFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CrcAlgorithm</name>
+                    <version>1</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcUnitSize</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkThreadsSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkLogCallGraph</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIcfFile_AltDefault</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkEncInput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkEncOutput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkEncOutputBom</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkHeapSelect</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkLocaleSelect</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkTrustzoneImportLibraryOut</name>
+                    <state>stm32h743_import_lib.o</state>
+                </option>
+                <option>
+                    <name>OILinkExtraOption</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryFile2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySymbol2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySegment2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryAlign2</name>
+                    <state></state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>IARCHIVE</name>
+            <archiveVersion>0</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>IarchiveInputs</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IarchiveOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IarchiveOutput</name>
+                    <state>###Unitialized###</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>BILINK</name>
+            <archiveVersion>0</archiveVersion>
+            <data />
+        </settings>
+    </configuration>
+    <group>
+        <name>Boot</name>
+        <group>
+            <name>lib</name>
+            <group>
+                <name>CMSIS</name>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\cmsis_armcc.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\cmsis_armclang.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\cmsis_compiler.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\cmsis_gcc.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\cmsis_iccarm.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\cmsis_version.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_armv8mbl.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_armv8mml.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_cm0.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_cm0plus.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_cm1.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_cm23.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_cm3.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_cm33.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_cm4.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_cm7.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_sc000.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_sc300.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\mpu_armv7.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\mpu_armv8.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Device\ST\STM32H7xx\Include\stm32h743xx.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Device\ST\STM32H7xx\Include\stm32h7xx.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Device\ST\STM32H7xx\Include\system_stm32h7xx.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\tz_context.h</name>
+                </file>
+            </group>
+            <group>
+                <name>STM32_USB_Device_Library</name>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32_USB_Device_Library\Core\Src\usbd_core.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32_USB_Device_Library\Core\Inc\usbd_core.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32_USB_Device_Library\Core\Src\usbd_ctlreq.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32_USB_Device_Library\Core\Inc\usbd_ctlreq.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32_USB_Device_Library\Core\Inc\usbd_def.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32_USB_Device_Library\Core\Src\usbd_ioreq.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32_USB_Device_Library\Core\Inc\usbd_ioreq.h</name>
+                </file>
+            </group>
+            <group>
+                <name>STM32H7xx_HAL_Driver</name>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cortex.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_cortex.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_def.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dma.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma_ex.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dma_ex.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_exti.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_exti.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_fdcan.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_fdcan.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_flash.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash_ex.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_flash_ex.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_gpio.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_gpio.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_gpio_ex.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hsem.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_hsem.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_i2c.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c_ex.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_i2c_ex.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mdma.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_mdma.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pcd.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pcd.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pcd_ex.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pcd_ex.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pwr.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr_ex.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pwr_ex.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_rcc.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc_ex.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_rcc_ex.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_tim.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim_ex.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_tim_ex.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_bus.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_cortex.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_crs.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_dma.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_dma.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_dmamux.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_exti.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_exti.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_gpio.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_gpio.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_pwr.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_rcc.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_rcc.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_system.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_usart.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_usart.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_usb.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_usb.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_utils.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_utils.h</name>
+                </file>
+            </group>
+            <file>
+                <name>$PROJ_DIR$\..\lib\stm32h7xx_hal_conf.h</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\..\lib\system_stm32h7xx.c</name>
+            </file>
+        </group>
+        <file>
+            <name>$PROJ_DIR$\..\blt_conf.h</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\hooks.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\led.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\led.h</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\main.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\startup_stm32h743xx.s</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\usbd_bulk.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\usbd_bulk.h</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\usbd_conf.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\usbd_conf.h</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\usbd_desc.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\usbd_desc.h</name>
+        </file>
+    </group>
+    <group>
+        <name>Source</name>
+        <group>
+            <name>ARMCM7_STM32H7</name>
+            <group>
+                <name>IAR</name>
+                <file>
+                    <name>$PROJ_DIR$\..\..\..\..\Source\ARMCM7_STM32H7\IAR\cpu_comp.c</name>
+                </file>
+            </group>
+            <file>
+                <name>$PROJ_DIR$\..\..\..\..\Source\ARMCM7_STM32H7\can.c</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\..\..\..\..\Source\ARMCM7_STM32H7\cpu.c</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\..\..\..\..\Source\ARMCM7_STM32H7\flash.c</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\..\..\..\..\Source\ARMCM7_STM32H7\flash.h</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\..\..\..\..\Source\ARMCM7_STM32H7\nvm.c</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\..\..\..\..\Source\ARMCM7_STM32H7\rs232.c</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\..\..\..\..\Source\ARMCM7_STM32H7\timer.c</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\..\..\..\..\Source\ARMCM7_STM32H7\types.h</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\..\..\..\..\Source\ARMCM7_STM32H7\usb.c</name>
+            </file>
+        </group>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\assert.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\assert.h</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\backdoor.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\backdoor.h</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\boot.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\boot.h</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\can.h</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\com.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\com.h</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\cop.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\cop.h</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\cpu.h</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\file.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\file.h</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\net.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\net.h</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\nvm.h</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\plausibility.h</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\rs232.h</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\timer.h</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\usb.h</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\xcp.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\xcp.h</name>
+        </file>
+    </group>
+</project>
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/ide/stm32h743.ewt b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/ide/stm32h743.ewt
new file mode 100644
index 00000000..438576ab
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/ide/stm32h743.ewt
@@ -0,0 +1,1876 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<project>
+    <fileVersion>3</fileVersion>
+    <configuration>
+        <name>stm32h743</name>
+        <toolchain>
+            <name>ARM</name>
+        </toolchain>
+        <debug>1</debug>
+        <settings>
+            <name>C-STAT</name>
+            <archiveVersion>264</archiveVersion>
+            <data>
+                <version>264</version>
+                <cstatargs>
+                    <useExtraArgs>0</useExtraArgs>
+                    <extraArgs></extraArgs>
+                    <analyzeTimeoutEnabled>1</analyzeTimeoutEnabled>
+                    <analyzeTimeout>600</analyzeTimeout>
+                    <enableParallel>1</enableParallel>
+                    <parallelThreads>2</parallelThreads>
+                    <enableFalsePositives>0</enableFalsePositives>
+                    <messagesLimitEnabled>1</messagesLimitEnabled>
+                    <messagesLimit>100</messagesLimit>
+                </cstatargs>
+                <cstat_settings>
+                    <cstat_version>1.8.1</cstat_version>
+                    <checks_tree>
+                        <package enabled="true" name="STDCHECKS">
+                            <group enabled="true" name="ARR">
+                                <check enabled="true" name="ARR-inv-index-pos" />
+                                <check enabled="true" name="ARR-inv-index-ptr-pos" />
+                                <check enabled="true" name="ARR-inv-index-ptr" />
+                                <check enabled="true" name="ARR-inv-index" />
+                                <check enabled="true" name="ARR-neg-index" />
+                                <check enabled="true" name="ARR-uninit-index" />
+                            </group>
+                            <group enabled="true" name="ATH">
+                                <check enabled="true" name="ATH-cmp-float" />
+                                <check enabled="true" name="ATH-cmp-unsign-neg" />
+                                <check enabled="true" name="ATH-cmp-unsign-pos" />
+                                <check enabled="true" name="ATH-div-0-assign" />
+                                <check enabled="false" name="ATH-div-0-cmp-aft" />
+                                <check enabled="true" name="ATH-div-0-cmp-bef" />
+                                <check enabled="true" name="ATH-div-0-interval" />
+                                <check enabled="true" name="ATH-div-0-pos" />
+                                <check enabled="true" name="ATH-div-0-unchk-global" />
+                                <check enabled="true" name="ATH-div-0-unchk-local" />
+                                <check enabled="true" name="ATH-div-0-unchk-param" />
+                                <check enabled="true" name="ATH-div-0" />
+                                <check enabled="true" name="ATH-inc-bool" />
+                                <check enabled="true" name="ATH-malloc-overrun" />
+                                <check enabled="true" name="ATH-neg-check-nonneg" />
+                                <check enabled="true" name="ATH-neg-check-pos" />
+                                <check enabled="true" name="ATH-new-overrun" />
+                                <check enabled="false" name="ATH-overflow-cast" />
+                                <check enabled="true" name="ATH-overflow" />
+                                <check enabled="true" name="ATH-shift-bounds" />
+                                <check enabled="true" name="ATH-shift-neg" />
+                                <check enabled="true" name="ATH-sizeof-by-sizeof" />
+                            </group>
+                            <group enabled="true" name="CAST">
+                                <check enabled="false" name="CAST-old-style" />
+                            </group>
+                            <group enabled="true" name="CATCH">
+                                <check enabled="true" name="CATCH-object-slicing" />
+                                <check enabled="false" name="CATCH-xtor-bad-member" />
+                            </group>
+                            <group enabled="true" name="COMMA">
+                                <check enabled="false" name="COMMA-overload" />
+                            </group>
+                            <group enabled="true" name="COMMENT">
+                                <check enabled="true" name="COMMENT-nested" />
+                            </group>
+                            <group enabled="true" name="CONST">
+                                <check enabled="true" name="CONST-member-ret" />
+                            </group>
+                            <group enabled="true" name="COP">
+                                <check enabled="false" name="COP-alloc-ctor" />
+                                <check enabled="true" name="COP-assign-op-ret" />
+                                <check enabled="true" name="COP-assign-op-self" />
+                                <check enabled="true" name="COP-assign-op" />
+                                <check enabled="true" name="COP-copy-ctor" />
+                                <check enabled="false" name="COP-dealloc-dtor" />
+                                <check enabled="true" name="COP-dtor-throw" />
+                                <check enabled="true" name="COP-dtor" />
+                                <check enabled="true" name="COP-init-order" />
+                                <check enabled="true" name="COP-init-uninit" />
+                                <check enabled="true" name="COP-member-uninit" />
+                            </group>
+                            <group enabled="true" name="CPU">
+                                <check enabled="true" name="CPU-ctor-call-virt" />
+                                <check enabled="false" name="CPU-ctor-implicit" />
+                                <check enabled="true" name="CPU-delete-throw" />
+                                <check enabled="true" name="CPU-delete-void" />
+                                <check enabled="true" name="CPU-dtor-call-virt" />
+                                <check enabled="true" name="CPU-malloc-class" />
+                                <check enabled="true" name="CPU-nonvirt-dtor" />
+                                <check enabled="true" name="CPU-return-ref-to-class-data" />
+                            </group>
+                            <group enabled="true" name="DECL">
+                                <check enabled="false" name="DECL-implicit-int" />
+                            </group>
+                            <group enabled="true" name="DEFINE">
+                                <check enabled="true" name="DEFINE-hash-multiple" />
+                            </group>
+                            <group enabled="true" name="ENUM">
+                                <check enabled="false" name="ENUM-bounds" />
+                            </group>
+                            <group enabled="true" name="EXP">
+                                <check enabled="true" name="EXP-cond-assign" />
+                                <check enabled="true" name="EXP-dangling-else" />
+                                <check enabled="true" name="EXP-loop-exit" />
+                                <check enabled="false" name="EXP-main-ret-int" />
+                                <check enabled="false" name="EXP-null-stmt" />
+                                <check enabled="false" name="EXP-stray-semicolon" />
+                            </group>
+                            <group enabled="true" name="EXPR">
+                                <check enabled="true" name="EXPR-const-overflow" />
+                            </group>
+                            <group enabled="true" name="FPT">
+                                <check enabled="true" name="FPT-cmp-null" />
+                                <check enabled="false" name="FPT-literal" />
+                                <check enabled="true" name="FPT-misuse" />
+                            </group>
+                            <group enabled="true" name="FUNC">
+                                <check enabled="false" name="FUNC-implicit-decl" />
+                                <check enabled="false" name="FUNC-unprototyped-all" />
+                                <check enabled="true" name="FUNC-unprototyped-used" />
+                            </group>
+                            <group enabled="true" name="INCLUDE">
+                                <check enabled="false" name="INCLUDE-c-file" />
+                            </group>
+                            <group enabled="true" name="INT">
+                                <check enabled="false" name="INT-use-signed-as-unsigned-pos" />
+                                <check enabled="true" name="INT-use-signed-as-unsigned" />
+                            </group>
+                            <group enabled="true" name="ITR">
+                                <check enabled="true" name="ITR-end-cmp-aft" />
+                                <check enabled="true" name="ITR-end-cmp-bef" />
+                                <check enabled="true" name="ITR-invalidated" />
+                                <check enabled="false" name="ITR-mismatch-alg" />
+                                <check enabled="false" name="ITR-store" />
+                                <check enabled="true" name="ITR-uninit" />
+                            </group>
+                            <group enabled="true" name="LIB">
+                                <check enabled="false" name="LIB-bsearch-overrun-pos" />
+                                <check enabled="false" name="LIB-bsearch-overrun" />
+                                <check enabled="false" name="LIB-fn-unsafe" />
+                                <check enabled="false" name="LIB-fread-overrun-pos" />
+                                <check enabled="true" name="LIB-fread-overrun" />
+                                <check enabled="false" name="LIB-memchr-overrun-pos" />
+                                <check enabled="true" name="LIB-memchr-overrun" />
+                                <check enabled="false" name="LIB-memcpy-overrun-pos" />
+                                <check enabled="true" name="LIB-memcpy-overrun" />
+                                <check enabled="false" name="LIB-memset-overrun-pos" />
+                                <check enabled="true" name="LIB-memset-overrun" />
+                                <check enabled="false" name="LIB-putenv" />
+                                <check enabled="false" name="LIB-qsort-overrun-pos" />
+                                <check enabled="false" name="LIB-qsort-overrun" />
+                                <check enabled="true" name="LIB-return-const" />
+                                <check enabled="true" name="LIB-return-error" />
+                                <check enabled="true" name="LIB-return-leak" />
+                                <check enabled="true" name="LIB-return-neg" />
+                                <check enabled="true" name="LIB-return-null" />
+                                <check enabled="false" name="LIB-sprintf-overrun" />
+                                <check enabled="false" name="LIB-std-sort-overrun-pos" />
+                                <check enabled="true" name="LIB-std-sort-overrun" />
+                                <check enabled="false" name="LIB-strcat-overrun-pos" />
+                                <check enabled="true" name="LIB-strcat-overrun" />
+                                <check enabled="false" name="LIB-strcpy-overrun-pos" />
+                                <check enabled="true" name="LIB-strcpy-overrun" />
+                                <check enabled="false" name="LIB-strncat-overrun-pos" />
+                                <check enabled="true" name="LIB-strncat-overrun" />
+                                <check enabled="false" name="LIB-strncmp-overrun-pos" />
+                                <check enabled="true" name="LIB-strncmp-overrun" />
+                                <check enabled="false" name="LIB-strncpy-overrun-pos" />
+                                <check enabled="true" name="LIB-strncpy-overrun" />
+                            </group>
+                            <group enabled="true" name="LOGIC">
+                                <check enabled="false" name="LOGIC-overload" />
+                            </group>
+                            <group enabled="true" name="MEM">
+                                <check enabled="true" name="MEM-delete-array-op" />
+                                <check enabled="true" name="MEM-delete-op" />
+                                <check enabled="true" name="MEM-double-free-alias" />
+                                <check enabled="true" name="MEM-double-free-some" />
+                                <check enabled="true" name="MEM-double-free" />
+                                <check enabled="true" name="MEM-free-field" />
+                                <check enabled="true" name="MEM-free-fptr" />
+                                <check enabled="false" name="MEM-free-no-alloc-struct" />
+                                <check enabled="false" name="MEM-free-no-alloc" />
+                                <check enabled="true" name="MEM-free-no-use" />
+                                <check enabled="true" name="MEM-free-op" />
+                                <check enabled="true" name="MEM-free-struct-field" />
+                                <check enabled="true" name="MEM-free-variable-alias" />
+                                <check enabled="true" name="MEM-free-variable" />
+                                <check enabled="true" name="MEM-leak-alias" />
+                                <check enabled="false" name="MEM-leak" />
+                                <check enabled="false" name="MEM-malloc-arith" />
+                                <check enabled="true" name="MEM-malloc-diff-type" />
+                                <check enabled="true" name="MEM-malloc-sizeof-ptr" />
+                                <check enabled="true" name="MEM-malloc-sizeof" />
+                                <check enabled="false" name="MEM-malloc-strlen" />
+                                <check enabled="true" name="MEM-realloc-diff-type" />
+                                <check enabled="true" name="MEM-return-free" />
+                                <check enabled="true" name="MEM-return-no-assign" />
+                                <check enabled="true" name="MEM-stack-global-field" />
+                                <check enabled="true" name="MEM-stack-global" />
+                                <check enabled="true" name="MEM-stack-param-ref" />
+                                <check enabled="true" name="MEM-stack-param" />
+                                <check enabled="true" name="MEM-stack-pos" />
+                                <check enabled="true" name="MEM-stack-ref" />
+                                <check enabled="true" name="MEM-stack" />
+                                <check enabled="true" name="MEM-use-free-all" />
+                                <check enabled="true" name="MEM-use-free-some" />
+                            </group>
+                            <group enabled="true" name="PTR">
+                                <check enabled="true" name="PTR-arith-field" />
+                                <check enabled="true" name="PTR-arith-stack" />
+                                <check enabled="true" name="PTR-arith-var" />
+                                <check enabled="true" name="PTR-cmp-str-lit" />
+                                <check enabled="false" name="PTR-null-assign-fun-pos" />
+                                <check enabled="false" name="PTR-null-assign-pos" />
+                                <check enabled="true" name="PTR-null-assign" />
+                                <check enabled="true" name="PTR-null-cmp-aft" />
+                                <check enabled="true" name="PTR-null-cmp-bef-fun" />
+                                <check enabled="true" name="PTR-null-cmp-bef" />
+                                <check enabled="true" name="PTR-null-fun-pos" />
+                                <check enabled="false" name="PTR-null-literal-pos" />
+                                <check enabled="false" name="PTR-overload" />
+                                <check enabled="false" name="PTR-singleton-arith-pos" />
+                                <check enabled="true" name="PTR-singleton-arith" />
+                                <check enabled="true" name="PTR-unchk-param-some" />
+                                <check enabled="false" name="PTR-unchk-param" />
+                                <check enabled="false" name="PTR-uninit-pos" />
+                                <check enabled="true" name="PTR-uninit" />
+                            </group>
+                            <group enabled="true" name="RED">
+                                <check enabled="false" name="RED-alloc-zero-bytes" />
+                                <check enabled="false" name="RED-case-reach" />
+                                <check enabled="false" name="RED-cmp-always" />
+                                <check enabled="false" name="RED-cmp-never" />
+                                <check enabled="false" name="RED-cond-always" />
+                                <check enabled="true" name="RED-cond-const-assign" />
+                                <check enabled="false" name="RED-cond-const-expr" />
+                                <check enabled="false" name="RED-cond-const" />
+                                <check enabled="false" name="RED-cond-never" />
+                                <check enabled="true" name="RED-dead" />
+                                <check enabled="false" name="RED-expr" />
+                                <check enabled="false" name="RED-func-no-effect" />
+                                <check enabled="true" name="RED-local-hides-global" />
+                                <check enabled="false" name="RED-local-hides-local" />
+                                <check enabled="false" name="RED-local-hides-member" />
+                                <check enabled="true" name="RED-local-hides-param" />
+                                <check enabled="false" name="RED-no-effect" />
+                                <check enabled="true" name="RED-self-assign" />
+                                <check enabled="true" name="RED-unused-assign" />
+                                <check enabled="false" name="RED-unused-param" />
+                                <check enabled="false" name="RED-unused-return-val" />
+                                <check enabled="false" name="RED-unused-val" />
+                                <check enabled="true" name="RED-unused-var-all" />
+                            </group>
+                            <group enabled="true" name="RESOURCE">
+                                <check enabled="false" name="RESOURCE-deref-file" />
+                                <check enabled="true" name="RESOURCE-double-close" />
+                                <check enabled="true" name="RESOURCE-file-no-close-all" />
+                                <check enabled="false" name="RESOURCE-file-pos-neg" />
+                                <check enabled="true" name="RESOURCE-file-use-after-close" />
+                                <check enabled="false" name="RESOURCE-implicit-deref-file" />
+                                <check enabled="true" name="RESOURCE-write-ronly-file" />
+                            </group>
+                            <group enabled="true" name="SIZEOF">
+                                <check enabled="true" name="SIZEOF-side-effect" />
+                            </group>
+                            <group enabled="true" name="SPC">
+                                <check enabled="true" name="SPC-order" />
+                                <check enabled="false" name="SPC-uninit-arr-all" />
+                                <check enabled="true" name="SPC-uninit-struct-field-heap" />
+                                <check enabled="false" name="SPC-uninit-struct-field" />
+                                <check enabled="true" name="SPC-uninit-struct" />
+                                <check enabled="true" name="SPC-uninit-var-all" />
+                                <check enabled="true" name="SPC-uninit-var-some" />
+                                <check enabled="false" name="SPC-volatile-reads" />
+                                <check enabled="false" name="SPC-volatile-writes" />
+                            </group>
+                            <group enabled="true" name="STRUCT">
+                                <check enabled="false" name="STRUCT-signed-bit" />
+                            </group>
+                            <group enabled="true" name="SWITCH">
+                                <check enabled="true" name="SWITCH-fall-through" />
+                            </group>
+                            <group enabled="true" name="THROW">
+                                <check enabled="false" name="THROW-empty" />
+                                <check enabled="false" name="THROW-main" />
+                                <check enabled="true" name="THROW-null" />
+                                <check enabled="true" name="THROW-ptr" />
+                                <check enabled="true" name="THROW-static" />
+                                <check enabled="true" name="THROW-unhandled" />
+                            </group>
+                            <group enabled="true" name="UNION">
+                                <check enabled="true" name="UNION-overlap-assign" />
+                                <check enabled="true" name="UNION-type-punning" />
+                            </group>
+                        </package>
+                        <package enabled="false" name="CERT">
+                            <group enabled="true" name="CERT-ARR">
+                                <check enabled="true" name="CERT-ARR30-C_a" />
+                                <check enabled="true" name="CERT-ARR30-C_b" />
+                                <check enabled="true" name="CERT-ARR30-C_c" />
+                                <check enabled="true" name="CERT-ARR30-C_d" />
+                                <check enabled="true" name="CERT-ARR30-C_e" />
+                                <check enabled="true" name="CERT-ARR30-C_f" />
+                                <check enabled="true" name="CERT-ARR30-C_g" />
+                                <check enabled="true" name="CERT-ARR30-C_h" />
+                                <check enabled="true" name="CERT-ARR30-C_i" />
+                                <check enabled="true" name="CERT-ARR30-C_j" />
+                                <check enabled="true" name="CERT-ARR32-C" />
+                                <check enabled="true" name="CERT-ARR36-C_a" />
+                                <check enabled="true" name="CERT-ARR36-C_b" />
+                                <check enabled="true" name="CERT-ARR37-C" />
+                                <check enabled="true" name="CERT-ARR38-C_a" />
+                                <check enabled="true" name="CERT-ARR38-C_b" />
+                                <check enabled="true" name="CERT-ARR38-C_c" />
+                                <check enabled="true" name="CERT-ARR38-C_d" />
+                                <check enabled="true" name="CERT-ARR38-C_e" />
+                                <check enabled="true" name="CERT-ARR38-C_f" />
+                                <check enabled="true" name="CERT-ARR39-C" />
+                            </group>
+                            <group enabled="true" name="CERT-DCL">
+                                <check enabled="true" name="CERT-DCL30-C_a" />
+                                <check enabled="true" name="CERT-DCL30-C_b" />
+                                <check enabled="true" name="CERT-DCL30-C_c" />
+                                <check enabled="true" name="CERT-DCL30-C_d" />
+                                <check enabled="true" name="CERT-DCL30-C_e" />
+                                <check enabled="true" name="CERT-DCL31-C" />
+                                <check enabled="true" name="CERT-DCL36-C" />
+                                <check enabled="true" name="CERT-DCL37-C_a" />
+                                <check enabled="true" name="CERT-DCL37-C_b" />
+                                <check enabled="false" name="CERT-DCL37-C_c" />
+                                <check enabled="true" name="CERT-DCL38-C" />
+                                <check enabled="true" name="CERT-DCL39-C" />
+                                <check enabled="true" name="CERT-DCL40-C" />
+                                <check enabled="true" name="CERT-DCL41-C" />
+                            </group>
+                            <group enabled="true" name="CERT-ENV">
+                                <check enabled="true" name="CERT-ENV30-C" />
+                                <check enabled="true" name="CERT-ENV31-C" />
+                                <check enabled="true" name="CERT-ENV32-C" />
+                                <check enabled="true" name="CERT-ENV33-C" />
+                                <check enabled="true" name="CERT-ENV34-C" />
+                            </group>
+                            <group enabled="true" name="CERT-ERR">
+                                <check enabled="true" name="CERT-ERR30-C_a" />
+                                <check enabled="true" name="CERT-ERR30-C_b" />
+                                <check enabled="true" name="CERT-ERR30-C_c" />
+                                <check enabled="true" name="CERT-ERR30-C_d" />
+                                <check enabled="true" name="CERT-ERR32-C" />
+                                <check enabled="true" name="CERT-ERR33-C_a" />
+                                <check enabled="true" name="CERT-ERR33-C_b" />
+                                <check enabled="true" name="CERT-ERR33-C_c" />
+                                <check enabled="true" name="CERT-ERR33-C_d" />
+                                <check enabled="true" name="CERT-ERR34-C_a" />
+                                <check enabled="true" name="CERT-ERR34-C_b" />
+                            </group>
+                            <group enabled="true" name="CERT-EXP">
+                                <check enabled="true" name="CERT-EXP19-C" />
+                                <check enabled="true" name="CERT-EXP30-C_a" />
+                                <check enabled="true" name="CERT-EXP30-C_b" />
+                                <check enabled="true" name="CERT-EXP32-C" />
+                                <check enabled="true" name="CERT-EXP33-C_a" />
+                                <check enabled="true" name="CERT-EXP33-C_b" />
+                                <check enabled="true" name="CERT-EXP33-C_c" />
+                                <check enabled="true" name="CERT-EXP33-C_d" />
+                                <check enabled="true" name="CERT-EXP33-C_e" />
+                                <check enabled="true" name="CERT-EXP33-C_f" />
+                                <check enabled="true" name="CERT-EXP34-C_a" />
+                                <check enabled="true" name="CERT-EXP34-C_b" />
+                                <check enabled="true" name="CERT-EXP34-C_c" />
+                                <check enabled="true" name="CERT-EXP34-C_d" />
+                                <check enabled="true" name="CERT-EXP34-C_e" />
+                                <check enabled="true" name="CERT-EXP34-C_f" />
+                                <check enabled="true" name="CERT-EXP34-C_g" />
+                                <check enabled="true" name="CERT-EXP35-C" />
+                                <check enabled="true" name="CERT-EXP36-C_a" />
+                                <check enabled="true" name="CERT-EXP36-C_b" />
+                                <check enabled="true" name="CERT-EXP37-C_a" />
+                                <check enabled="true" name="CERT-EXP37-C_b" />
+                                <check enabled="true" name="CERT-EXP37-C_c" />
+                                <check enabled="true" name="CERT-EXP39-C_a" />
+                                <check enabled="true" name="CERT-EXP39-C_b" />
+                                <check enabled="true" name="CERT-EXP39-C_c" />
+                                <check enabled="true" name="CERT-EXP39-C_d" />
+                                <check enabled="true" name="CERT-EXP39-C_e" />
+                                <check enabled="true" name="CERT-EXP40-C_a" />
+                                <check enabled="true" name="CERT-EXP40-C_b" />
+                                <check enabled="true" name="CERT-EXP42-C" />
+                                <check enabled="true" name="CERT-EXP43-C_a" />
+                                <check enabled="true" name="CERT-EXP43-C_b" />
+                                <check enabled="true" name="CERT-EXP43-C_c" />
+                                <check enabled="true" name="CERT-EXP43-C_d" />
+                                <check enabled="true" name="CERT-EXP44-C" />
+                                <check enabled="true" name="CERT-EXP45-C" />
+                                <check enabled="true" name="CERT-EXP46-C" />
+                                <check enabled="true" name="CERT-EXP47-C_a" />
+                                <check enabled="true" name="CERT-EXP47-C_b" />
+                            </group>
+                            <group enabled="true" name="CERT-FIO">
+                                <check enabled="true" name="CERT-FIO30-C" />
+                                <check enabled="true" name="CERT-FIO32-C" />
+                                <check enabled="true" name="CERT-FIO34-C" />
+                                <check enabled="true" name="CERT-FIO37-C" />
+                                <check enabled="true" name="CERT-FIO38-C" />
+                                <check enabled="true" name="CERT-FIO39-C" />
+                                <check enabled="true" name="CERT-FIO40-C" />
+                                <check enabled="true" name="CERT-FIO41-C" />
+                                <check enabled="true" name="CERT-FIO42-C_a" />
+                                <check enabled="false" name="CERT-FIO42-C_b" />
+                                <check enabled="true" name="CERT-FIO44-C" />
+                                <check enabled="true" name="CERT-FIO45-C" />
+                                <check enabled="true" name="CERT-FIO46-C_a" />
+                                <check enabled="true" name="CERT-FIO46-C_b" />
+                                <check enabled="true" name="CERT-FIO46-C_c" />
+                                <check enabled="true" name="CERT-FIO47-C_a" />
+                                <check enabled="true" name="CERT-FIO47-C_b" />
+                                <check enabled="true" name="CERT-FIO47-C_c" />
+                            </group>
+                            <group enabled="true" name="CERT-FLP">
+                                <check enabled="true" name="CERT-FLP30-C_a" />
+                                <check enabled="true" name="CERT-FLP30-C_b" />
+                                <check enabled="true" name="CERT-FLP32-C_a" />
+                                <check enabled="true" name="CERT-FLP32-C_b" />
+                                <check enabled="true" name="CERT-FLP34-C" />
+                                <check enabled="true" name="CERT-FLP36-C" />
+                                <check enabled="true" name="CERT-FLP37-C" />
+                            </group>
+                            <group enabled="true" name="CERT-INT">
+                                <check enabled="true" name="CERT-INT30-C_a" />
+                                <check enabled="false" name="CERT-INT30-C_b" />
+                                <check enabled="true" name="CERT-INT31-C_a" />
+                                <check enabled="true" name="CERT-INT31-C_b" />
+                                <check enabled="true" name="CERT-INT31-C_c" />
+                                <check enabled="true" name="CERT-INT32-C_a" />
+                                <check enabled="false" name="CERT-INT32-C_b" />
+                                <check enabled="true" name="CERT-INT33-C_a" />
+                                <check enabled="true" name="CERT-INT33-C_b" />
+                                <check enabled="true" name="CERT-INT33-C_c" />
+                                <check enabled="true" name="CERT-INT33-C_d" />
+                                <check enabled="true" name="CERT-INT33-C_e" />
+                                <check enabled="true" name="CERT-INT33-C_f" />
+                                <check enabled="true" name="CERT-INT33-C_g" />
+                                <check enabled="true" name="CERT-INT33-C_h" />
+                                <check enabled="true" name="CERT-INT33-C_i" />
+                                <check enabled="true" name="CERT-INT34-C_a" />
+                                <check enabled="true" name="CERT-INT34-C_b" />
+                                <check enabled="true" name="CERT-INT34-C_c" />
+                                <check enabled="true" name="CERT-INT35-C" />
+                                <check enabled="true" name="CERT-INT36-C" />
+                            </group>
+                            <group enabled="true" name="CERT-MEM">
+                                <check enabled="true" name="CERT-MEM30-C_a" />
+                                <check enabled="true" name="CERT-MEM30-C_b" />
+                                <check enabled="true" name="CERT-MEM30-C_c" />
+                                <check enabled="true" name="CERT-MEM31-C" />
+                                <check enabled="true" name="CERT-MEM33-C_a" />
+                                <check enabled="true" name="CERT-MEM33-C_b" />
+                                <check enabled="true" name="CERT-MEM34-C_a" />
+                                <check enabled="true" name="CERT-MEM34-C_b" />
+                                <check enabled="true" name="CERT-MEM34-C_c" />
+                                <check enabled="true" name="CERT-MEM35-C_a" />
+                                <check enabled="true" name="CERT-MEM35-C_b" />
+                                <check enabled="true" name="CERT-MEM35-C_c" />
+                                <check enabled="true" name="CERT-MEM36-C" />
+                            </group>
+                            <group enabled="true" name="CERT-MSC">
+                                <check enabled="true" name="CERT-MSC30-C" />
+                                <check enabled="true" name="CERT-MSC32-C" />
+                                <check enabled="false" name="CERT-MSC33-C" />
+                                <check enabled="true" name="CERT-MSC37-C" />
+                                <check enabled="true" name="CERT-MSC38-C" />
+                                <check enabled="true" name="CERT-MSC39-C" />
+                                <check enabled="true" name="CERT-MSC40-C_a" />
+                                <check enabled="true" name="CERT-MSC40-C_b" />
+                                <check enabled="true" name="CERT-MSC40-C_c" />
+                                <check enabled="true" name="CERT-MSC40-C_d" />
+                                <check enabled="false" name="CERT-MSC40-C_e" />
+                                <check enabled="true" name="CERT-MSC41-C_a" />
+                                <check enabled="true" name="CERT-MSC41-C_b" />
+                                <check enabled="true" name="CERT-MSC41-C_c" />
+                            </group>
+                            <group enabled="true" name="CERT-PRE">
+                                <check enabled="true" name="CERT-PRE31-C" />
+                                <check enabled="true" name="CERT-PRE32-C_a" />
+                                <check enabled="true" name="CERT-PRE32-C_b" />
+                            </group>
+                            <group enabled="true" name="CERT-SIG">
+                                <check enabled="true" name="CERT-SIG30-C" />
+                                <check enabled="true" name="CERT-SIG31-C" />
+                                <check enabled="true" name="CERT-SIG34-C" />
+                                <check enabled="true" name="CERT-SIG35-C" />
+                            </group>
+                            <group enabled="true" name="CERT-STR">
+                                <check enabled="true" name="CERT-STR30-C" />
+                                <check enabled="true" name="CERT-STR31-C_a" />
+                                <check enabled="true" name="CERT-STR31-C_b" />
+                                <check enabled="true" name="CERT-STR31-C_c" />
+                                <check enabled="true" name="CERT-STR31-C_d" />
+                                <check enabled="true" name="CERT-STR31-C_e" />
+                                <check enabled="true" name="CERT-STR31-C_f" />
+                                <check enabled="true" name="CERT-STR31-C_g" />
+                                <check enabled="true" name="CERT-STR31-C_h" />
+                                <check enabled="true" name="CERT-STR32-C" />
+                                <check enabled="true" name="CERT-STR34-C" />
+                                <check enabled="true" name="CERT-STR37-C" />
+                            </group>
+                        </package>
+                        <package enabled="false" name="SECURITY">
+                            <group enabled="true" name="SEC-BUFFER">
+                                <check enabled="true" name="SEC-BUFFER-memory-leak-alias" />
+                                <check enabled="false" name="SEC-BUFFER-memory-leak" />
+                                <check enabled="false" name="SEC-BUFFER-memset-overrun-pos" />
+                                <check enabled="true" name="SEC-BUFFER-memset-overrun" />
+                                <check enabled="false" name="SEC-BUFFER-qsort-overrun-pos" />
+                                <check enabled="true" name="SEC-BUFFER-qsort-overrun" />
+                                <check enabled="true" name="SEC-BUFFER-sprintf-overrun" />
+                                <check enabled="false" name="SEC-BUFFER-std-sort-overrun-pos" />
+                                <check enabled="true" name="SEC-BUFFER-std-sort-overrun" />
+                                <check enabled="false" name="SEC-BUFFER-strcat-overrun-pos" />
+                                <check enabled="true" name="SEC-BUFFER-strcat-overrun" />
+                                <check enabled="false" name="SEC-BUFFER-strcpy-overrun-pos" />
+                                <check enabled="true" name="SEC-BUFFER-strcpy-overrun" />
+                                <check enabled="false" name="SEC-BUFFER-strncat-overrun-pos" />
+                                <check enabled="true" name="SEC-BUFFER-strncat-overrun" />
+                                <check enabled="false" name="SEC-BUFFER-strncmp-overrun-pos" />
+                                <check enabled="true" name="SEC-BUFFER-strncmp-overrun" />
+                                <check enabled="false" name="SEC-BUFFER-strncpy-overrun-pos" />
+                                <check enabled="true" name="SEC-BUFFER-strncpy-overrun" />
+                                <check enabled="true" name="SEC-BUFFER-tainted-alloc-size" />
+                                <check enabled="true" name="SEC-BUFFER-tainted-copy-length" />
+                                <check enabled="true" name="SEC-BUFFER-tainted-copy" />
+                                <check enabled="true" name="SEC-BUFFER-tainted-index" />
+                                <check enabled="true" name="SEC-BUFFER-tainted-offset" />
+                                <check enabled="true" name="SEC-BUFFER-use-after-free-all" />
+                                <check enabled="true" name="SEC-BUFFER-use-after-free-some" />
+                            </group>
+                            <group enabled="true" name="SEC-DIV-0">
+                                <check enabled="true" name="SEC-DIV-0-compare-after" />
+                                <check enabled="true" name="SEC-DIV-0-compare-before" />
+                                <check enabled="true" name="SEC-DIV-0-tainted" />
+                            </group>
+                            <group enabled="true" name="SEC-FILEOP">
+                                <check enabled="true" name="SEC-FILEOP-open-no-close" />
+                                <check enabled="false" name="SEC-FILEOP-path-traversal" />
+                                <check enabled="true" name="SEC-FILEOP-use-after-close" />
+                            </group>
+                            <group enabled="true" name="SEC-INJECTION">
+                                <check enabled="false" name="SEC-INJECTION-sql" />
+                                <check enabled="false" name="SEC-INJECTION-xpath" />
+                            </group>
+                            <group enabled="true" name="SEC-LOOP">
+                                <check enabled="true" name="SEC-LOOP-tainted-bound" />
+                            </group>
+                            <group enabled="true" name="SEC-NULL">
+                                <check enabled="false" name="SEC-NULL-assignment-fun-pos" />
+                                <check enabled="true" name="SEC-NULL-assignment" />
+                                <check enabled="true" name="SEC-NULL-cmp-aft" />
+                                <check enabled="true" name="SEC-NULL-cmp-bef-fun" />
+                                <check enabled="true" name="SEC-NULL-cmp-bef" />
+                                <check enabled="false" name="SEC-NULL-literal-pos" />
+                            </group>
+                            <group enabled="true" name="SEC-STRING">
+                                <check enabled="true" name="SEC-STRING-format-string" />
+                                <check enabled="false" name="SEC-STRING-hard-coded-credentials" />
+                            </group>
+                        </package>
+                        <package enabled="false" name="MISRAC2004">
+                            <group enabled="true" name="MISRAC2004-1">
+                                <check enabled="true" name="MISRAC2004-1.1" />
+                                <check enabled="true" name="MISRAC2004-1.2_a" />
+                                <check enabled="true" name="MISRAC2004-1.2_b" />
+                                <check enabled="true" name="MISRAC2004-1.2_c" />
+                                <check enabled="true" name="MISRAC2004-1.2_d" />
+                                <check enabled="true" name="MISRAC2004-1.2_e" />
+                                <check enabled="true" name="MISRAC2004-1.2_f" />
+                                <check enabled="true" name="MISRAC2004-1.2_g" />
+                                <check enabled="true" name="MISRAC2004-1.2_h" />
+                                <check enabled="true" name="MISRAC2004-1.2_i" />
+                                <check enabled="true" name="MISRAC2004-1.2_j" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-2">
+                                <check enabled="true" name="MISRAC2004-2.1" />
+                                <check enabled="true" name="MISRAC2004-2.2" />
+                                <check enabled="true" name="MISRAC2004-2.3" />
+                                <check enabled="false" name="MISRAC2004-2.4" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-5">
+                                <check enabled="true" name="MISRAC2004-5.1" />
+                                <check enabled="true" name="MISRAC2004-5.2" />
+                                <check enabled="true" name="MISRAC2004-5.3" />
+                                <check enabled="true" name="MISRAC2004-5.4" />
+                                <check enabled="false" name="MISRAC2004-5.5" />
+                                <check enabled="false" name="MISRAC2004-5.6" />
+                                <check enabled="false" name="MISRAC2004-5.7" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-6">
+                                <check enabled="true" name="MISRAC2004-6.1" />
+                                <check enabled="true" name="MISRAC2004-6.2" />
+                                <check enabled="false" name="MISRAC2004-6.3" />
+                                <check enabled="true" name="MISRAC2004-6.4" />
+                                <check enabled="true" name="MISRAC2004-6.5" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-7">
+                                <check enabled="true" name="MISRAC2004-7.1" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-8">
+                                <check enabled="true" name="MISRAC2004-8.1" />
+                                <check enabled="true" name="MISRAC2004-8.2" />
+                                <check enabled="true" name="MISRAC2004-8.3" />
+                                <check enabled="true" name="MISRAC2004-8.5_a" />
+                                <check enabled="true" name="MISRAC2004-8.5_b" />
+                                <check enabled="true" name="MISRAC2004-8.6" />
+                                <check enabled="true" name="MISRAC2004-8.7" />
+                                <check enabled="true" name="MISRAC2004-8.8_a" />
+                                <check enabled="true" name="MISRAC2004-8.8_b" />
+                                <check enabled="true" name="MISRAC2004-8.10" />
+                                <check enabled="true" name="MISRAC2004-8.12" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-9">
+                                <check enabled="true" name="MISRAC2004-9.1_a" />
+                                <check enabled="true" name="MISRAC2004-9.1_b" />
+                                <check enabled="true" name="MISRAC2004-9.1_c" />
+                                <check enabled="true" name="MISRAC2004-9.2" />
+                                <check enabled="true" name="MISRAC2004-9.3" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-10">
+                                <check enabled="true" name="MISRAC2004-10.1_a" />
+                                <check enabled="true" name="MISRAC2004-10.1_b" />
+                                <check enabled="true" name="MISRAC2004-10.1_c" />
+                                <check enabled="true" name="MISRAC2004-10.1_d" />
+                                <check enabled="true" name="MISRAC2004-10.2_a" />
+                                <check enabled="true" name="MISRAC2004-10.2_b" />
+                                <check enabled="true" name="MISRAC2004-10.2_c" />
+                                <check enabled="true" name="MISRAC2004-10.2_d" />
+                                <check enabled="true" name="MISRAC2004-10.3" />
+                                <check enabled="true" name="MISRAC2004-10.4" />
+                                <check enabled="true" name="MISRAC2004-10.5" />
+                                <check enabled="true" name="MISRAC2004-10.6" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-11">
+                                <check enabled="true" name="MISRAC2004-11.1" />
+                                <check enabled="false" name="MISRAC2004-11.3" />
+                                <check enabled="false" name="MISRAC2004-11.4" />
+                                <check enabled="true" name="MISRAC2004-11.5" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-12">
+                                <check enabled="false" name="MISRAC2004-12.1" />
+                                <check enabled="true" name="MISRAC2004-12.2_a" />
+                                <check enabled="true" name="MISRAC2004-12.2_b" />
+                                <check enabled="true" name="MISRAC2004-12.2_c" />
+                                <check enabled="true" name="MISRAC2004-12.3" />
+                                <check enabled="true" name="MISRAC2004-12.4" />
+                                <check enabled="true" name="MISRAC2004-12.5" />
+                                <check enabled="false" name="MISRAC2004-12.6_a" />
+                                <check enabled="false" name="MISRAC2004-12.6_b" />
+                                <check enabled="true" name="MISRAC2004-12.7" />
+                                <check enabled="true" name="MISRAC2004-12.8" />
+                                <check enabled="true" name="MISRAC2004-12.9" />
+                                <check enabled="true" name="MISRAC2004-12.10" />
+                                <check enabled="false" name="MISRAC2004-12.11" />
+                                <check enabled="true" name="MISRAC2004-12.12_a" />
+                                <check enabled="true" name="MISRAC2004-12.12_b" />
+                                <check enabled="false" name="MISRAC2004-12.13" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-13">
+                                <check enabled="true" name="MISRAC2004-13.1" />
+                                <check enabled="false" name="MISRAC2004-13.2_a" />
+                                <check enabled="false" name="MISRAC2004-13.2_b" />
+                                <check enabled="false" name="MISRAC2004-13.2_c" />
+                                <check enabled="false" name="MISRAC2004-13.2_d" />
+                                <check enabled="false" name="MISRAC2004-13.2_e" />
+                                <check enabled="true" name="MISRAC2004-13.3" />
+                                <check enabled="true" name="MISRAC2004-13.4" />
+                                <check enabled="true" name="MISRAC2004-13.5" />
+                                <check enabled="true" name="MISRAC2004-13.6" />
+                                <check enabled="true" name="MISRAC2004-13.7_a" />
+                                <check enabled="true" name="MISRAC2004-13.7_b" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-14">
+                                <check enabled="true" name="MISRAC2004-14.1" />
+                                <check enabled="true" name="MISRAC2004-14.2" />
+                                <check enabled="true" name="MISRAC2004-14.3" />
+                                <check enabled="true" name="MISRAC2004-14.4" />
+                                <check enabled="true" name="MISRAC2004-14.5" />
+                                <check enabled="true" name="MISRAC2004-14.6" />
+                                <check enabled="true" name="MISRAC2004-14.7" />
+                                <check enabled="true" name="MISRAC2004-14.8_a" />
+                                <check enabled="true" name="MISRAC2004-14.8_b" />
+                                <check enabled="true" name="MISRAC2004-14.8_c" />
+                                <check enabled="true" name="MISRAC2004-14.8_d" />
+                                <check enabled="true" name="MISRAC2004-14.9" />
+                                <check enabled="true" name="MISRAC2004-14.10" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-15">
+                                <check enabled="true" name="MISRAC2004-15.0" />
+                                <check enabled="true" name="MISRAC2004-15.1" />
+                                <check enabled="true" name="MISRAC2004-15.2" />
+                                <check enabled="true" name="MISRAC2004-15.3" />
+                                <check enabled="true" name="MISRAC2004-15.4" />
+                                <check enabled="true" name="MISRAC2004-15.5" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-16">
+                                <check enabled="true" name="MISRAC2004-16.1" />
+                                <check enabled="true" name="MISRAC2004-16.2_a" />
+                                <check enabled="true" name="MISRAC2004-16.2_b" />
+                                <check enabled="true" name="MISRAC2004-16.3" />
+                                <check enabled="true" name="MISRAC2004-16.4" />
+                                <check enabled="true" name="MISRAC2004-16.5" />
+                                <check enabled="true" name="MISRAC2004-16.7" />
+                                <check enabled="true" name="MISRAC2004-16.8" />
+                                <check enabled="true" name="MISRAC2004-16.9" />
+                                <check enabled="true" name="MISRAC2004-16.10" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-17">
+                                <check enabled="true" name="MISRAC2004-17.1_a" />
+                                <check enabled="true" name="MISRAC2004-17.1_b" />
+                                <check enabled="true" name="MISRAC2004-17.1_c" />
+                                <check enabled="true" name="MISRAC2004-17.2" />
+                                <check enabled="true" name="MISRAC2004-17.3" />
+                                <check enabled="true" name="MISRAC2004-17.4_a" />
+                                <check enabled="true" name="MISRAC2004-17.4_b" />
+                                <check enabled="true" name="MISRAC2004-17.5" />
+                                <check enabled="true" name="MISRAC2004-17.6_a" />
+                                <check enabled="true" name="MISRAC2004-17.6_b" />
+                                <check enabled="true" name="MISRAC2004-17.6_c" />
+                                <check enabled="true" name="MISRAC2004-17.6_d" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-18">
+                                <check enabled="true" name="MISRAC2004-18.1" />
+                                <check enabled="true" name="MISRAC2004-18.2" />
+                                <check enabled="true" name="MISRAC2004-18.4" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-19">
+                                <check enabled="false" name="MISRAC2004-19.1" />
+                                <check enabled="false" name="MISRAC2004-19.2" />
+                                <check enabled="true" name="MISRAC2004-19.4" />
+                                <check enabled="true" name="MISRAC2004-19.5" />
+                                <check enabled="true" name="MISRAC2004-19.6" />
+                                <check enabled="false" name="MISRAC2004-19.7" />
+                                <check enabled="true" name="MISRAC2004-19.10" />
+                                <check enabled="true" name="MISRAC2004-19.12" />
+                                <check enabled="false" name="MISRAC2004-19.13" />
+                                <check enabled="true" name="MISRAC2004-19.15" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-20">
+                                <check enabled="true" name="MISRAC2004-20.1" />
+                                <check enabled="true" name="MISRAC2004-20.2" />
+                                <check enabled="true" name="MISRAC2004-20.3_a" />
+                                <check enabled="true" name="MISRAC2004-20.3_b" />
+                                <check enabled="true" name="MISRAC2004-20.3_c" />
+                                <check enabled="true" name="MISRAC2004-20.3_d" />
+                                <check enabled="true" name="MISRAC2004-20.3_e" />
+                                <check enabled="true" name="MISRAC2004-20.3_f" />
+                                <check enabled="true" name="MISRAC2004-20.3_g" />
+                                <check enabled="true" name="MISRAC2004-20.3_h" />
+                                <check enabled="true" name="MISRAC2004-20.3_i" />
+                                <check enabled="true" name="MISRAC2004-20.4" />
+                                <check enabled="true" name="MISRAC2004-20.5" />
+                                <check enabled="true" name="MISRAC2004-20.6" />
+                                <check enabled="true" name="MISRAC2004-20.7" />
+                                <check enabled="true" name="MISRAC2004-20.8" />
+                                <check enabled="true" name="MISRAC2004-20.9" />
+                                <check enabled="true" name="MISRAC2004-20.10" />
+                                <check enabled="true" name="MISRAC2004-20.11" />
+                                <check enabled="true" name="MISRAC2004-20.12" />
+                            </group>
+                        </package>
+                        <package enabled="false" name="MISRAC2012">
+                            <group enabled="true" name="MISRAC2012-Dir-4">
+                                <check enabled="true" name="MISRAC2012-Dir-4.3" />
+                                <check enabled="false" name="MISRAC2012-Dir-4.4" />
+                                <check enabled="false" name="MISRAC2012-Dir-4.5" />
+                                <check enabled="false" name="MISRAC2012-Dir-4.6_a" />
+                                <check enabled="false" name="MISRAC2012-Dir-4.6_b" />
+                                <check enabled="false" name="MISRAC2012-Dir-4.7_a" />
+                                <check enabled="false" name="MISRAC2012-Dir-4.7_b" />
+                                <check enabled="false" name="MISRAC2012-Dir-4.7_c" />
+                                <check enabled="false" name="MISRAC2012-Dir-4.8" />
+                                <check enabled="false" name="MISRAC2012-Dir-4.9" />
+                                <check enabled="true" name="MISRAC2012-Dir-4.10" />
+                                <check enabled="false" name="MISRAC2012-Dir-4.11_a" />
+                                <check enabled="false" name="MISRAC2012-Dir-4.11_b" />
+                                <check enabled="false" name="MISRAC2012-Dir-4.11_c" />
+                                <check enabled="false" name="MISRAC2012-Dir-4.11_d" />
+                                <check enabled="false" name="MISRAC2012-Dir-4.11_e" />
+                                <check enabled="false" name="MISRAC2012-Dir-4.11_f" />
+                                <check enabled="false" name="MISRAC2012-Dir-4.11_g" />
+                                <check enabled="false" name="MISRAC2012-Dir-4.11_h" />
+                                <check enabled="false" name="MISRAC2012-Dir-4.11_i" />
+                                <check enabled="false" name="MISRAC2012-Dir-4.12" />
+                                <check enabled="true" name="MISRAC2012-Dir-4.13_b" />
+                                <check enabled="true" name="MISRAC2012-Dir-4.13_c" />
+                                <check enabled="true" name="MISRAC2012-Dir-4.13_d" />
+                                <check enabled="true" name="MISRAC2012-Dir-4.13_e" />
+                                <check enabled="true" name="MISRAC2012-Dir-4.13_f" />
+                                <check enabled="true" name="MISRAC2012-Dir-4.13_g" />
+                                <check enabled="false" name="MISRAC2012-Dir-4.13_h" />
+                                <check enabled="true" name="MISRAC2012-Dir-4.14_a" />
+                                <check enabled="true" name="MISRAC2012-Dir-4.14_b" />
+                                <check enabled="true" name="MISRAC2012-Dir-4.14_c" />
+                                <check enabled="true" name="MISRAC2012-Dir-4.14_d" />
+                                <check enabled="true" name="MISRAC2012-Dir-4.14_e" />
+                                <check enabled="true" name="MISRAC2012-Dir-4.14_f" />
+                                <check enabled="true" name="MISRAC2012-Dir-4.14_g" />
+                                <check enabled="true" name="MISRAC2012-Dir-4.14_h" />
+                                <check enabled="true" name="MISRAC2012-Dir-4.14_i" />
+                                <check enabled="true" name="MISRAC2012-Dir-4.14_j" />
+                                <check enabled="true" name="MISRAC2012-Dir-4.14_l" />
+                                <check enabled="true" name="MISRAC2012-Dir-4.14_m" />
+                            </group>
+                            <group enabled="true" name="MISRAC2012-Rule-1">
+                                <check enabled="true" name="MISRAC2012-Rule-1.3_a" />
+                                <check enabled="true" name="MISRAC2012-Rule-1.3_b" />
+                                <check enabled="true" name="MISRAC2012-Rule-1.3_c" />
+                                <check enabled="true" name="MISRAC2012-Rule-1.3_d" />
+                                <check enabled="true" name="MISRAC2012-Rule-1.3_e" />
+                                <check enabled="true" name="MISRAC2012-Rule-1.3_f" />
+                                <check enabled="true" name="MISRAC2012-Rule-1.3_g" />
+                                <check enabled="true" name="MISRAC2012-Rule-1.3_h" />
+                                <check enabled="true" name="MISRAC2012-Rule-1.3_i" />
+                                <check enabled="true" name="MISRAC2012-Rule-1.3_j" />
+                                <check enabled="true" name="MISRAC2012-Rule-1.3_k" />
+                                <check enabled="true" name="MISRAC2012-Rule-1.3_m" />
+                                <check enabled="true" name="MISRAC2012-Rule-1.3_n" />
+                                <check enabled="true" name="MISRAC2012-Rule-1.3_o" />
+                                <check enabled="true" name="MISRAC2012-Rule-1.3_p" />
+                                <check enabled="true" name="MISRAC2012-Rule-1.3_q" />
+                                <check enabled="true" name="MISRAC2012-Rule-1.3_r" />
+                                <check enabled="true" name="MISRAC2012-Rule-1.3_s" />
+                                <check enabled="true" name="MISRAC2012-Rule-1.3_t" />
+                                <check enabled="true" name="MISRAC2012-Rule-1.3_u" />
+                                <check enabled="true" name="MISRAC2012-Rule-1.3_v" />
+                                <check enabled="true" name="MISRAC2012-Rule-1.3_w" />
+                            </group>
+                            <group enabled="true" name="MISRAC2012-Rule-2">
+                                <check enabled="true" name="MISRAC2012-Rule-2.1_a" />
+                                <check enabled="true" name="MISRAC2012-Rule-2.1_b" />
+                                <check enabled="true" name="MISRAC2012-Rule-2.2_a" />
+                                <check enabled="true" name="MISRAC2012-Rule-2.2_b" />
+                                <check enabled="true" name="MISRAC2012-Rule-2.2_c" />
+                                <check enabled="false" name="MISRAC2012-Rule-2.3" />
+                                <check enabled="false" name="MISRAC2012-Rule-2.4" />
+                                <check enabled="false" name="MISRAC2012-Rule-2.5" />
+                                <check enabled="false" name="MISRAC2012-Rule-2.6" />
+                                <check enabled="false" name="MISRAC2012-Rule-2.7" />
+                            </group>
+                            <group enabled="true" name="MISRAC2012-Rule-3">
+                                <check enabled="true" name="MISRAC2012-Rule-3.1" />
+                                <check enabled="true" name="MISRAC2012-Rule-3.2" />
+                            </group>
+                            <group enabled="true" name="MISRAC2012-Rule-5">
+                                <check enabled="true" name="MISRAC2012-Rule-5.1" />
+                                <check enabled="true" name="MISRAC2012-Rule-5.2_c89" />
+                                <check enabled="true" name="MISRAC2012-Rule-5.2_c99" />
+                                <check enabled="true" name="MISRAC2012-Rule-5.3_c89" />
+                                <check enabled="true" name="MISRAC2012-Rule-5.3_c99" />
+                                <check enabled="true" name="MISRAC2012-Rule-5.4_c89" />
+                                <check enabled="true" name="MISRAC2012-Rule-5.4_c99" />
+                                <check enabled="true" name="MISRAC2012-Rule-5.5_c89" />
+                                <check enabled="true" name="MISRAC2012-Rule-5.5_c99" />
+                                <check enabled="true" name="MISRAC2012-Rule-5.6" />
+                                <check enabled="true" name="MISRAC2012-Rule-5.7" />
+                                <check enabled="true" name="MISRAC2012-Rule-5.8" />
+                                <check enabled="false" name="MISRAC2012-Rule-5.9" />
+                            </group>
+                            <group enabled="true" name="MISRAC2012-Rule-6">
+                                <check enabled="true" name="MISRAC2012-Rule-6.1" />
+                                <check enabled="true" name="MISRAC2012-Rule-6.2" />
+                            </group>
+                            <group enabled="true" name="MISRAC2012-Rule-7">
+                                <check enabled="true" name="MISRAC2012-Rule-7.1" />
+                                <check enabled="true" name="MISRAC2012-Rule-7.2" />
+                                <check enabled="true" name="MISRAC2012-Rule-7.3" />
+                                <check enabled="true" name="MISRAC2012-Rule-7.4_a" />
+                                <check enabled="true" name="MISRAC2012-Rule-7.4_b" />
+                            </group>
+                            <group enabled="true" name="MISRAC2012-Rule-8">
+                                <check enabled="true" name="MISRAC2012-Rule-8.1" />
+                                <check enabled="true" name="MISRAC2012-Rule-8.2_a" />
+                                <check enabled="true" name="MISRAC2012-Rule-8.2_b" />
+                                <check enabled="true" name="MISRAC2012-Rule-8.3" />
+                                <check enabled="true" name="MISRAC2012-Rule-8.4" />
+                                <check enabled="true" name="MISRAC2012-Rule-8.5_a" />
+                                <check enabled="true" name="MISRAC2012-Rule-8.5_b" />
+                                <check enabled="false" name="MISRAC2012-Rule-8.7" />
+                                <check enabled="false" name="MISRAC2012-Rule-8.9_a" />
+                                <check enabled="false" name="MISRAC2012-Rule-8.9_b" />
+                                <check enabled="true" name="MISRAC2012-Rule-8.10" />
+                                <check enabled="false" name="MISRAC2012-Rule-8.11" />
+                                <check enabled="true" name="MISRAC2012-Rule-8.12" />
+                                <check enabled="false" name="MISRAC2012-Rule-8.13" />
+                                <check enabled="true" name="MISRAC2012-Rule-8.14" />
+                            </group>
+                            <group enabled="true" name="MISRAC2012-Rule-9">
+                                <check enabled="true" name="MISRAC2012-Rule-9.1_a" />
+                                <check enabled="true" name="MISRAC2012-Rule-9.1_b" />
+                                <check enabled="true" name="MISRAC2012-Rule-9.1_c" />
+                                <check enabled="true" name="MISRAC2012-Rule-9.1_d" />
+                                <check enabled="true" name="MISRAC2012-Rule-9.1_e" />
+                                <check enabled="true" name="MISRAC2012-Rule-9.1_f" />
+                                <check enabled="true" name="MISRAC2012-Rule-9.2" />
+                                <check enabled="true" name="MISRAC2012-Rule-9.3" />
+                                <check enabled="true" name="MISRAC2012-Rule-9.4" />
+                                <check enabled="true" name="MISRAC2012-Rule-9.5_a" />
+                                <check enabled="true" name="MISRAC2012-Rule-9.5_b" />
+                            </group>
+                            <group enabled="true" name="MISRAC2012-Rule-10">
+                                <check enabled="true" name="MISRAC2012-Rule-10.1_R2" />
+                                <check enabled="true" name="MISRAC2012-Rule-10.1_R3" />
+                                <check enabled="true" name="MISRAC2012-Rule-10.1_R4" />
+                                <check enabled="true" name="MISRAC2012-Rule-10.1_R5" />
+                                <check enabled="true" name="MISRAC2012-Rule-10.1_R6" />
+                                <check enabled="true" name="MISRAC2012-Rule-10.1_R7" />
+                                <check enabled="true" name="MISRAC2012-Rule-10.1_R8" />
+                                <check enabled="true" name="MISRAC2012-Rule-10.2" />
+                                <check enabled="true" name="MISRAC2012-Rule-10.3" />
+                                <check enabled="true" name="MISRAC2012-Rule-10.4_a" />
+                                <check enabled="true" name="MISRAC2012-Rule-10.4_b" />
+                                <check enabled="false" name="MISRAC2012-Rule-10.5" />
+                                <check enabled="true" name="MISRAC2012-Rule-10.6" />
+                                <check enabled="true" name="MISRAC2012-Rule-10.7" />
+                                <check enabled="true" name="MISRAC2012-Rule-10.8" />
+                            </group>
+                            <group enabled="true" name="MISRAC2012-Rule-11">
+                                <check enabled="true" name="MISRAC2012-Rule-11.1" />
+                                <check enabled="true" name="MISRAC2012-Rule-11.2" />
+                                <check enabled="true" name="MISRAC2012-Rule-11.3" />
+                                <check enabled="false" name="MISRAC2012-Rule-11.4" />
+                                <check enabled="false" name="MISRAC2012-Rule-11.5" />
+                                <check enabled="true" name="MISRAC2012-Rule-11.6" />
+                                <check enabled="true" name="MISRAC2012-Rule-11.7" />
+                                <check enabled="true" name="MISRAC2012-Rule-11.8" />
+                                <check enabled="true" name="MISRAC2012-Rule-11.9" />
+                            </group>
+                            <group enabled="true" name="MISRAC2012-Rule-12">
+                                <check enabled="false" name="MISRAC2012-Rule-12.1" />
+                                <check enabled="true" name="MISRAC2012-Rule-12.2" />
+                                <check enabled="false" name="MISRAC2012-Rule-12.3" />
+                                <check enabled="true" name="MISRAC2012-Rule-12.5" />
+                            </group>
+                            <group enabled="true" name="MISRAC2012-Rule-13">
+                                <check enabled="true" name="MISRAC2012-Rule-13.1" />
+                                <check enabled="true" name="MISRAC2012-Rule-13.2_a" />
+                                <check enabled="true" name="MISRAC2012-Rule-13.2_b" />
+                                <check enabled="true" name="MISRAC2012-Rule-13.2_c" />
+                                <check enabled="false" name="MISRAC2012-Rule-13.3" />
+                                <check enabled="false" name="MISRAC2012-Rule-13.4_a" />
+                                <check enabled="false" name="MISRAC2012-Rule-13.4_b" />
+                                <check enabled="true" name="MISRAC2012-Rule-13.5" />
+                                <check enabled="true" name="MISRAC2012-Rule-13.6" />
+                            </group>
+                            <group enabled="true" name="MISRAC2012-Rule-14">
+                                <check enabled="true" name="MISRAC2012-Rule-14.1_a" />
+                                <check enabled="true" name="MISRAC2012-Rule-14.1_b" />
+                                <check enabled="true" name="MISRAC2012-Rule-14.2" />
+                                <check enabled="true" name="MISRAC2012-Rule-14.3_a" />
+                                <check enabled="true" name="MISRAC2012-Rule-14.3_b" />
+                                <check enabled="true" name="MISRAC2012-Rule-14.4_a" />
+                                <check enabled="true" name="MISRAC2012-Rule-14.4_b" />
+                                <check enabled="true" name="MISRAC2012-Rule-14.4_c" />
+                                <check enabled="true" name="MISRAC2012-Rule-14.4_d" />
+                            </group>
+                            <group enabled="true" name="MISRAC2012-Rule-15">
+                                <check enabled="false" name="MISRAC2012-Rule-15.1" />
+                                <check enabled="true" name="MISRAC2012-Rule-15.2" />
+                                <check enabled="true" name="MISRAC2012-Rule-15.3" />
+                                <check enabled="false" name="MISRAC2012-Rule-15.4" />
+                                <check enabled="false" name="MISRAC2012-Rule-15.5" />
+                                <check enabled="true" name="MISRAC2012-Rule-15.6_a" />
+                                <check enabled="true" name="MISRAC2012-Rule-15.6_b" />
+                                <check enabled="true" name="MISRAC2012-Rule-15.6_c" />
+                                <check enabled="true" name="MISRAC2012-Rule-15.6_d" />
+                                <check enabled="true" name="MISRAC2012-Rule-15.6_e" />
+                                <check enabled="true" name="MISRAC2012-Rule-15.7" />
+                            </group>
+                            <group enabled="true" name="MISRAC2012-Rule-16">
+                                <check enabled="true" name="MISRAC2012-Rule-16.1" />
+                                <check enabled="true" name="MISRAC2012-Rule-16.2" />
+                                <check enabled="true" name="MISRAC2012-Rule-16.3" />
+                                <check enabled="true" name="MISRAC2012-Rule-16.4" />
+                                <check enabled="true" name="MISRAC2012-Rule-16.5" />
+                                <check enabled="true" name="MISRAC2012-Rule-16.6" />
+                                <check enabled="true" name="MISRAC2012-Rule-16.7" />
+                            </group>
+                            <group enabled="true" name="MISRAC2012-Rule-17">
+                                <check enabled="true" name="MISRAC2012-Rule-17.1" />
+                                <check enabled="true" name="MISRAC2012-Rule-17.2_a" />
+                                <check enabled="true" name="MISRAC2012-Rule-17.2_b" />
+                                <check enabled="true" name="MISRAC2012-Rule-17.3" />
+                                <check enabled="true" name="MISRAC2012-Rule-17.4" />
+                                <check enabled="false" name="MISRAC2012-Rule-17.5" />
+                                <check enabled="true" name="MISRAC2012-Rule-17.6" />
+                                <check enabled="true" name="MISRAC2012-Rule-17.7" />
+                                <check enabled="false" name="MISRAC2012-Rule-17.8" />
+                            </group>
+                            <group enabled="true" name="MISRAC2012-Rule-18">
+                                <check enabled="true" name="MISRAC2012-Rule-18.1_a" />
+                                <check enabled="true" name="MISRAC2012-Rule-18.1_b" />
+                                <check enabled="true" name="MISRAC2012-Rule-18.1_c" />
+                                <check enabled="true" name="MISRAC2012-Rule-18.1_d" />
+                                <check enabled="true" name="MISRAC2012-Rule-18.2" />
+                                <check enabled="true" name="MISRAC2012-Rule-18.3" />
+                                <check enabled="true" name="MISRAC2012-Rule-18.4" />
+                                <check enabled="false" name="MISRAC2012-Rule-18.5" />
+                                <check enabled="true" name="MISRAC2012-Rule-18.6_a" />
+                                <check enabled="true" name="MISRAC2012-Rule-18.6_b" />
+                                <check enabled="true" name="MISRAC2012-Rule-18.6_c" />
+                                <check enabled="true" name="MISRAC2012-Rule-18.6_d" />
+                                <check enabled="true" name="MISRAC2012-Rule-18.7" />
+                                <check enabled="true" name="MISRAC2012-Rule-18.8" />
+                            </group>
+                            <group enabled="true" name="MISRAC2012-Rule-19">
+                                <check enabled="true" name="MISRAC2012-Rule-19.1" />
+                                <check enabled="false" name="MISRAC2012-Rule-19.2" />
+                            </group>
+                            <group enabled="true" name="MISRAC2012-Rule-20">
+                                <check enabled="false" name="MISRAC2012-Rule-20.1" />
+                                <check enabled="true" name="MISRAC2012-Rule-20.2" />
+                                <check enabled="true" name="MISRAC2012-Rule-20.4_c89" />
+                                <check enabled="true" name="MISRAC2012-Rule-20.4_c99" />
+                                <check enabled="false" name="MISRAC2012-Rule-20.5" />
+                                <check enabled="true" name="MISRAC2012-Rule-20.6_a" />
+                                <check enabled="true" name="MISRAC2012-Rule-20.6_b" />
+                                <check enabled="true" name="MISRAC2012-Rule-20.7" />
+                                <check enabled="false" name="MISRAC2012-Rule-20.10" />
+                            </group>
+                            <group enabled="true" name="MISRAC2012-Rule-21">
+                                <check enabled="true" name="MISRAC2012-Rule-21.1" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.2" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.3" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.4" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.5" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.6" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.7" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.8" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.9" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.10" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.11" />
+                                <check enabled="false" name="MISRAC2012-Rule-21.12_a" />
+                                <check enabled="false" name="MISRAC2012-Rule-21.12_b" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.13" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.14" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.15" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.16" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.17_a" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.17_b" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.17_c" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.17_d" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.17_e" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.17_f" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.18_a" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.18_b" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.19_a" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.19_b" />
+                                <check enabled="true" name="MISRAC2012-Rule-21.20" />
+                            </group>
+                            <group enabled="true" name="MISRAC2012-Rule-22">
+                                <check enabled="true" name="MISRAC2012-Rule-22.1_a" />
+                                <check enabled="true" name="MISRAC2012-Rule-22.1_b" />
+                                <check enabled="true" name="MISRAC2012-Rule-22.2_a" />
+                                <check enabled="true" name="MISRAC2012-Rule-22.2_b" />
+                                <check enabled="true" name="MISRAC2012-Rule-22.2_c" />
+                                <check enabled="true" name="MISRAC2012-Rule-22.3" />
+                                <check enabled="true" name="MISRAC2012-Rule-22.4" />
+                                <check enabled="true" name="MISRAC2012-Rule-22.5_a" />
+                                <check enabled="true" name="MISRAC2012-Rule-22.5_b" />
+                                <check enabled="true" name="MISRAC2012-Rule-22.6" />
+                                <check enabled="true" name="MISRAC2012-Rule-22.7_a" />
+                                <check enabled="true" name="MISRAC2012-Rule-22.7_b" />
+                                <check enabled="true" name="MISRAC2012-Rule-22.8" />
+                                <check enabled="true" name="MISRAC2012-Rule-22.9" />
+                                <check enabled="true" name="MISRAC2012-Rule-22.10" />
+                            </group>
+                        </package>
+                        <package enabled="false" name="MISRAC++2008">
+                            <group enabled="true" name="MISRAC++2008-0-1">
+                                <check enabled="true" name="MISRAC++2008-0-1-1" />
+                                <check enabled="true" name="MISRAC++2008-0-1-2_a" />
+                                <check enabled="true" name="MISRAC++2008-0-1-2_b" />
+                                <check enabled="true" name="MISRAC++2008-0-1-2_c" />
+                                <check enabled="true" name="MISRAC++2008-0-1-3" />
+                                <check enabled="true" name="MISRAC++2008-0-1-4_a" />
+                                <check enabled="true" name="MISRAC++2008-0-1-4_b" />
+                                <check enabled="true" name="MISRAC++2008-0-1-6" />
+                                <check enabled="true" name="MISRAC++2008-0-1-7" />
+                                <check enabled="false" name="MISRAC++2008-0-1-8" />
+                                <check enabled="true" name="MISRAC++2008-0-1-9" />
+                                <check enabled="true" name="MISRAC++2008-0-1-11" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-0-2">
+                                <check enabled="true" name="MISRAC++2008-0-2-1" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-0-3">
+                                <check enabled="true" name="MISRAC++2008-0-3-2" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-2-7">
+                                <check enabled="true" name="MISRAC++2008-2-7-1" />
+                                <check enabled="true" name="MISRAC++2008-2-7-2" />
+                                <check enabled="false" name="MISRAC++2008-2-7-3" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-2-10">
+                                <check enabled="true" name="MISRAC++2008-2-10-1" />
+                                <check enabled="true" name="MISRAC++2008-2-10-2" />
+                                <check enabled="true" name="MISRAC++2008-2-10-3" />
+                                <check enabled="true" name="MISRAC++2008-2-10-4" />
+                                <check enabled="false" name="MISRAC++2008-2-10-5" />
+                                <check enabled="true" name="MISRAC++2008-2-10-6" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-2-13">
+                                <check enabled="true" name="MISRAC++2008-2-13-2" />
+                                <check enabled="true" name="MISRAC++2008-2-13-3" />
+                                <check enabled="true" name="MISRAC++2008-2-13-4_a" />
+                                <check enabled="true" name="MISRAC++2008-2-13-4_b" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-3-1">
+                                <check enabled="true" name="MISRAC++2008-3-1-1" />
+                                <check enabled="true" name="MISRAC++2008-3-1-3" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-3-9">
+                                <check enabled="false" name="MISRAC++2008-3-9-2" />
+                                <check enabled="true" name="MISRAC++2008-3-9-3" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-4-5">
+                                <check enabled="true" name="MISRAC++2008-4-5-1" />
+                                <check enabled="true" name="MISRAC++2008-4-5-2" />
+                                <check enabled="true" name="MISRAC++2008-4-5-3" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-5-0">
+                                <check enabled="true" name="MISRAC++2008-5-0-1_a" />
+                                <check enabled="true" name="MISRAC++2008-5-0-1_b" />
+                                <check enabled="true" name="MISRAC++2008-5-0-1_c" />
+                                <check enabled="false" name="MISRAC++2008-5-0-2" />
+                                <check enabled="true" name="MISRAC++2008-5-0-3" />
+                                <check enabled="true" name="MISRAC++2008-5-0-4" />
+                                <check enabled="true" name="MISRAC++2008-5-0-5" />
+                                <check enabled="true" name="MISRAC++2008-5-0-6" />
+                                <check enabled="true" name="MISRAC++2008-5-0-7" />
+                                <check enabled="true" name="MISRAC++2008-5-0-8" />
+                                <check enabled="true" name="MISRAC++2008-5-0-9" />
+                                <check enabled="true" name="MISRAC++2008-5-0-10" />
+                                <check enabled="true" name="MISRAC++2008-5-0-13_a" />
+                                <check enabled="true" name="MISRAC++2008-5-0-13_b" />
+                                <check enabled="true" name="MISRAC++2008-5-0-13_c" />
+                                <check enabled="true" name="MISRAC++2008-5-0-13_d" />
+                                <check enabled="true" name="MISRAC++2008-5-0-14" />
+                                <check enabled="true" name="MISRAC++2008-5-0-15_a" />
+                                <check enabled="true" name="MISRAC++2008-5-0-15_b" />
+                                <check enabled="true" name="MISRAC++2008-5-0-16_a" />
+                                <check enabled="true" name="MISRAC++2008-5-0-16_b" />
+                                <check enabled="true" name="MISRAC++2008-5-0-16_c" />
+                                <check enabled="true" name="MISRAC++2008-5-0-16_d" />
+                                <check enabled="true" name="MISRAC++2008-5-0-16_e" />
+                                <check enabled="true" name="MISRAC++2008-5-0-16_f" />
+                                <check enabled="true" name="MISRAC++2008-5-0-19" />
+                                <check enabled="true" name="MISRAC++2008-5-0-21" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-5-2">
+                                <check enabled="true" name="MISRAC++2008-5-2-4" />
+                                <check enabled="true" name="MISRAC++2008-5-2-5" />
+                                <check enabled="true" name="MISRAC++2008-5-2-6" />
+                                <check enabled="true" name="MISRAC++2008-5-2-7" />
+                                <check enabled="false" name="MISRAC++2008-5-2-9" />
+                                <check enabled="false" name="MISRAC++2008-5-2-10" />
+                                <check enabled="true" name="MISRAC++2008-5-2-11_a" />
+                                <check enabled="true" name="MISRAC++2008-5-2-11_b" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-5-3">
+                                <check enabled="true" name="MISRAC++2008-5-3-1" />
+                                <check enabled="true" name="MISRAC++2008-5-3-2_a" />
+                                <check enabled="true" name="MISRAC++2008-5-3-2_b" />
+                                <check enabled="true" name="MISRAC++2008-5-3-3" />
+                                <check enabled="true" name="MISRAC++2008-5-3-4" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-5-8">
+                                <check enabled="true" name="MISRAC++2008-5-8-1" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-5-14">
+                                <check enabled="true" name="MISRAC++2008-5-14-1" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-5-18">
+                                <check enabled="true" name="MISRAC++2008-5-18-1" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-5-19">
+                                <check enabled="false" name="MISRAC++2008-5-19-1" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-6-2">
+                                <check enabled="true" name="MISRAC++2008-6-2-1" />
+                                <check enabled="true" name="MISRAC++2008-6-2-2" />
+                                <check enabled="false" name="MISRAC++2008-6-2-3" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-6-3">
+                                <check enabled="true" name="MISRAC++2008-6-3-1_a" />
+                                <check enabled="true" name="MISRAC++2008-6-3-1_b" />
+                                <check enabled="true" name="MISRAC++2008-6-3-1_c" />
+                                <check enabled="true" name="MISRAC++2008-6-3-1_d" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-6-4">
+                                <check enabled="true" name="MISRAC++2008-6-4-1" />
+                                <check enabled="true" name="MISRAC++2008-6-4-2" />
+                                <check enabled="true" name="MISRAC++2008-6-4-3" />
+                                <check enabled="true" name="MISRAC++2008-6-4-4" />
+                                <check enabled="true" name="MISRAC++2008-6-4-5" />
+                                <check enabled="true" name="MISRAC++2008-6-4-6" />
+                                <check enabled="true" name="MISRAC++2008-6-4-7" />
+                                <check enabled="true" name="MISRAC++2008-6-4-8" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-6-5">
+                                <check enabled="true" name="MISRAC++2008-6-5-1_a" />
+                                <check enabled="true" name="MISRAC++2008-6-5-1_b" />
+                                <check enabled="true" name="MISRAC++2008-6-5-2" />
+                                <check enabled="true" name="MISRAC++2008-6-5-3" />
+                                <check enabled="true" name="MISRAC++2008-6-5-4" />
+                                <check enabled="true" name="MISRAC++2008-6-5-5" />
+                                <check enabled="true" name="MISRAC++2008-6-5-6" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-6-6">
+                                <check enabled="true" name="MISRAC++2008-6-6-1" />
+                                <check enabled="true" name="MISRAC++2008-6-6-2" />
+                                <check enabled="true" name="MISRAC++2008-6-6-4" />
+                                <check enabled="true" name="MISRAC++2008-6-6-5" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-7-1">
+                                <check enabled="true" name="MISRAC++2008-7-1-1" />
+                                <check enabled="true" name="MISRAC++2008-7-1-2" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-7-2">
+                                <check enabled="true" name="MISRAC++2008-7-2-1" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-7-4">
+                                <check enabled="true" name="MISRAC++2008-7-4-3" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-7-5">
+                                <check enabled="true" name="MISRAC++2008-7-5-1_a" />
+                                <check enabled="true" name="MISRAC++2008-7-5-1_b" />
+                                <check enabled="true" name="MISRAC++2008-7-5-2_a" />
+                                <check enabled="true" name="MISRAC++2008-7-5-2_b" />
+                                <check enabled="true" name="MISRAC++2008-7-5-2_c" />
+                                <check enabled="true" name="MISRAC++2008-7-5-2_d" />
+                                <check enabled="false" name="MISRAC++2008-7-5-4_a" />
+                                <check enabled="false" name="MISRAC++2008-7-5-4_b" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-8-0">
+                                <check enabled="true" name="MISRAC++2008-8-0-1" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-8-4">
+                                <check enabled="true" name="MISRAC++2008-8-4-1" />
+                                <check enabled="true" name="MISRAC++2008-8-4-3" />
+                                <check enabled="true" name="MISRAC++2008-8-4-4" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-8-5">
+                                <check enabled="true" name="MISRAC++2008-8-5-1_a" />
+                                <check enabled="true" name="MISRAC++2008-8-5-1_b" />
+                                <check enabled="true" name="MISRAC++2008-8-5-1_c" />
+                                <check enabled="true" name="MISRAC++2008-8-5-2" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-9-3">
+                                <check enabled="true" name="MISRAC++2008-9-3-1" />
+                                <check enabled="true" name="MISRAC++2008-9-3-2" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-9-5">
+                                <check enabled="true" name="MISRAC++2008-9-5-1" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-9-6">
+                                <check enabled="true" name="MISRAC++2008-9-6-2" />
+                                <check enabled="true" name="MISRAC++2008-9-6-3" />
+                                <check enabled="true" name="MISRAC++2008-9-6-4" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-12-1">
+                                <check enabled="true" name="MISRAC++2008-12-1-1_a" />
+                                <check enabled="true" name="MISRAC++2008-12-1-1_b" />
+                                <check enabled="true" name="MISRAC++2008-12-1-3" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-15-0">
+                                <check enabled="false" name="MISRAC++2008-15-0-2" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-15-1">
+                                <check enabled="true" name="MISRAC++2008-15-1-2" />
+                                <check enabled="true" name="MISRAC++2008-15-1-3" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-15-3">
+                                <check enabled="true" name="MISRAC++2008-15-3-1" />
+                                <check enabled="false" name="MISRAC++2008-15-3-2" />
+                                <check enabled="true" name="MISRAC++2008-15-3-3" />
+                                <check enabled="true" name="MISRAC++2008-15-3-4" />
+                                <check enabled="true" name="MISRAC++2008-15-3-5" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-15-5">
+                                <check enabled="true" name="MISRAC++2008-15-5-1" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-16-0">
+                                <check enabled="true" name="MISRAC++2008-16-0-3" />
+                                <check enabled="true" name="MISRAC++2008-16-0-4" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-16-2">
+                                <check enabled="true" name="MISRAC++2008-16-2-2" />
+                                <check enabled="true" name="MISRAC++2008-16-2-3" />
+                                <check enabled="true" name="MISRAC++2008-16-2-4" />
+                                <check enabled="false" name="MISRAC++2008-16-2-5" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-16-3">
+                                <check enabled="true" name="MISRAC++2008-16-3-1" />
+                                <check enabled="false" name="MISRAC++2008-16-3-2" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-17-0">
+                                <check enabled="true" name="MISRAC++2008-17-0-1" />
+                                <check enabled="true" name="MISRAC++2008-17-0-3" />
+                                <check enabled="true" name="MISRAC++2008-17-0-5" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-18-0">
+                                <check enabled="true" name="MISRAC++2008-18-0-1" />
+                                <check enabled="true" name="MISRAC++2008-18-0-2" />
+                                <check enabled="true" name="MISRAC++2008-18-0-3" />
+                                <check enabled="true" name="MISRAC++2008-18-0-4" />
+                                <check enabled="true" name="MISRAC++2008-18-0-5" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-18-2">
+                                <check enabled="true" name="MISRAC++2008-18-2-1" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-18-4">
+                                <check enabled="true" name="MISRAC++2008-18-4-1" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-18-7">
+                                <check enabled="true" name="MISRAC++2008-18-7-1" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-19-3">
+                                <check enabled="true" name="MISRAC++2008-19-3-1" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-27-0">
+                                <check enabled="true" name="MISRAC++2008-27-0-1" />
+                            </group>
+                        </package>
+                    </checks_tree>
+                </cstat_settings>
+            </data>
+        </settings>
+        <settings>
+            <name>RuntimeChecking</name>
+            <archiveVersion>0</archiveVersion>
+            <data>
+                <version>2</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>GenRtcDebugHeap</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcEnableBoundsChecking</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcCheckPtrsNonInstrMem</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>GenRtcTrackPointerBounds</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>GenRtcCheckAccesses</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>GenRtcGenerateEntries</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcNrTrackedPointers</name>
+                    <state>1000</state>
+                </option>
+                <option>
+                    <name>GenRtcIntOverflow</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcIncUnsigned</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcIntConversion</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcInclExplicit</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcIntShiftOverflow</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcInclUnsignedShiftOverflow</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcUnhandledCase</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcDivByZero</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcCheckPtrsNonInstrFunc</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+    </configuration>
+    <group>
+        <name>Boot</name>
+        <group>
+            <name>lib</name>
+            <group>
+                <name>CMSIS</name>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\cmsis_armcc.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\cmsis_armclang.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\cmsis_compiler.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\cmsis_gcc.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\cmsis_iccarm.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\cmsis_version.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_armv8mbl.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_armv8mml.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_cm0.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_cm0plus.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_cm1.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_cm23.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_cm3.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_cm33.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_cm4.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_cm7.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_sc000.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_sc300.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\mpu_armv7.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\mpu_armv8.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Device\ST\STM32H7xx\Include\stm32h743xx.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Device\ST\STM32H7xx\Include\stm32h7xx.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Device\ST\STM32H7xx\Include\system_stm32h7xx.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\tz_context.h</name>
+                </file>
+            </group>
+            <group>
+                <name>STM32_USB_Device_Library</name>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32_USB_Device_Library\Core\Src\usbd_core.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32_USB_Device_Library\Core\Inc\usbd_core.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32_USB_Device_Library\Core\Src\usbd_ctlreq.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32_USB_Device_Library\Core\Inc\usbd_ctlreq.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32_USB_Device_Library\Core\Inc\usbd_def.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32_USB_Device_Library\Core\Src\usbd_ioreq.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32_USB_Device_Library\Core\Inc\usbd_ioreq.h</name>
+                </file>
+            </group>
+            <group>
+                <name>STM32H7xx_HAL_Driver</name>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cortex.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_cortex.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_def.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dma.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma_ex.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dma_ex.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_exti.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_exti.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_fdcan.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_fdcan.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_flash.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash_ex.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_flash_ex.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_gpio.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_gpio.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_gpio_ex.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hsem.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_hsem.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_i2c.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c_ex.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_i2c_ex.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mdma.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_mdma.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pcd.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pcd.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pcd_ex.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pcd_ex.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pwr.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr_ex.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pwr_ex.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_rcc.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc_ex.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_rcc_ex.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_tim.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim_ex.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_tim_ex.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_bus.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_cortex.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_crs.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_dma.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_dma.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_dmamux.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_exti.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_exti.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_gpio.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_gpio.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_pwr.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_rcc.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_rcc.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_system.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_usart.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_usart.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_usb.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_usb.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_utils.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_utils.h</name>
+                </file>
+            </group>
+            <file>
+                <name>$PROJ_DIR$\..\lib\stm32h7xx_hal_conf.h</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\..\lib\system_stm32h7xx.c</name>
+            </file>
+        </group>
+        <file>
+            <name>$PROJ_DIR$\..\blt_conf.h</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\hooks.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\led.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\led.h</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\main.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\startup_stm32h743xx.s</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\usbd_bulk.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\usbd_bulk.h</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\usbd_conf.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\usbd_conf.h</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\usbd_desc.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\usbd_desc.h</name>
+        </file>
+    </group>
+    <group>
+        <name>Source</name>
+        <group>
+            <name>ARMCM7_STM32H7</name>
+            <group>
+                <name>IAR</name>
+                <file>
+                    <name>$PROJ_DIR$\..\..\..\..\Source\ARMCM7_STM32H7\IAR\cpu_comp.c</name>
+                </file>
+            </group>
+            <file>
+                <name>$PROJ_DIR$\..\..\..\..\Source\ARMCM7_STM32H7\can.c</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\..\..\..\..\Source\ARMCM7_STM32H7\cpu.c</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\..\..\..\..\Source\ARMCM7_STM32H7\flash.c</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\..\..\..\..\Source\ARMCM7_STM32H7\flash.h</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\..\..\..\..\Source\ARMCM7_STM32H7\nvm.c</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\..\..\..\..\Source\ARMCM7_STM32H7\rs232.c</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\..\..\..\..\Source\ARMCM7_STM32H7\timer.c</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\..\..\..\..\Source\ARMCM7_STM32H7\types.h</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\..\..\..\..\Source\ARMCM7_STM32H7\usb.c</name>
+            </file>
+        </group>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\assert.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\assert.h</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\backdoor.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\backdoor.h</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\boot.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\boot.h</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\can.h</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\com.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\com.h</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\cop.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\cop.h</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\cpu.h</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\file.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\file.h</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\net.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\net.h</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\nvm.h</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\plausibility.h</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\rs232.h</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\timer.h</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\usb.h</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\xcp.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\..\..\..\Source\xcp.h</name>
+        </file>
+    </group>
+</project>
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/ide/stm32h743.eww b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/ide/stm32h743.eww
new file mode 100644
index 00000000..d3964b7d
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/ide/stm32h743.eww
@@ -0,0 +1,7 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<workspace>
+  <project>
+    <path>$WS_DIR$\stm32h743.ewp</path>
+  </project>
+  <batchBuild />
+</workspace>
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/led.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/led.c
new file mode 100644
index 00000000..03f498c7
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/led.c
@@ -0,0 +1,101 @@
+/************************************************************************************//**
+* \file         Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/led.c
+* \brief        LED driver source file.
+* \ingroup      Boot_ARMCM7_STM32H7_Nucleo_H743ZI_IAR
+* \internal
+*----------------------------------------------------------------------------------------
+*                          C O P Y R I G H T
+*----------------------------------------------------------------------------------------
+*   Copyright (c) 2020  by Feaser    http://www.feaser.com    All rights reserved
+*
+*----------------------------------------------------------------------------------------
+*                            L I C E N S E
+*----------------------------------------------------------------------------------------
+* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as published by the Free
+* Software Foundation, either version 3 of the License, or (at your option) any later
+* version.
+*
+* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+* PURPOSE. See the GNU General Public License for more details.
+*
+* You have received a copy of the GNU General Public License along with OpenBLT. It
+* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
+*
+* \endinternal
+****************************************************************************************/
+
+/****************************************************************************************
+* Include files
+****************************************************************************************/
+#include "boot.h"                                /* bootloader generic header          */
+#include "led.h"                                 /* module header                      */
+#include "stm32h7xx.h"                           /* STM32 CPU and HAL header           */
+#include "stm32h7xx_ll_gpio.h"                   /* STM32 LL GPIO header               */
+
+
+/****************************************************************************************
+* Local data declarations
+****************************************************************************************/
+/** \brief Holds the desired LED blink interval time. */
+static blt_int16u ledBlinkIntervalMs;
+
+
+/************************************************************************************//**
+** \brief     Initializes the LED blink driver.
+** \param     interval_ms Specifies the desired LED blink interval time in milliseconds.
+** \return    none.
+**
+****************************************************************************************/
+void LedBlinkInit(blt_int16u interval_ms)
+{
+  /* store the interval time between LED toggles */
+  ledBlinkIntervalMs = interval_ms;
+} /*** end of LedBlinkInit ***/
+
+
+/************************************************************************************//**
+** \brief     Task function for blinking the LED as a fixed timer interval.
+** \return    none.
+**
+****************************************************************************************/
+void LedBlinkTask(void)
+{
+  static blt_bool ledOn = BLT_FALSE;
+  static blt_int32u nextBlinkEvent = 0;
+
+  /* check for blink event */
+  if (TimerGet() >= nextBlinkEvent)
+  {
+    /* toggle the LED state */
+    if (ledOn == BLT_FALSE)
+    {
+      ledOn = BLT_TRUE;
+      LL_GPIO_SetOutputPin(GPIOB, LL_GPIO_PIN_7);
+    }
+    else
+    {
+      ledOn = BLT_FALSE;
+      LL_GPIO_ResetOutputPin(GPIOB, LL_GPIO_PIN_7);
+    }
+    /* schedule the next blink event */
+    nextBlinkEvent = TimerGet() + ledBlinkIntervalMs;
+  }
+} /*** end of LedBlinkTask ***/
+
+
+/************************************************************************************//**
+** \brief     Cleans up the LED blink driver. This is intended to be used upon program
+**            exit.
+** \return    none.
+**
+****************************************************************************************/
+void LedBlinkExit(void)
+{
+  /* turn the LED off */
+  LL_GPIO_ResetOutputPin(GPIOB, LL_GPIO_PIN_7);
+} /*** end of LedBlinkExit ***/
+
+
+/*********************************** end of led.c **************************************/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/led.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/led.h
new file mode 100644
index 00000000..758610ce
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/led.h
@@ -0,0 +1,40 @@
+/************************************************************************************//**
+* \file         Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/led.h
+* \brief        LED driver header file.
+* \ingroup      Boot_ARMCM7_STM32H7_Nucleo_H743ZI_IAR
+* \internal
+*----------------------------------------------------------------------------------------
+*                          C O P Y R I G H T
+*----------------------------------------------------------------------------------------
+*   Copyright (c) 2020  by Feaser    http://www.feaser.com    All rights reserved
+*
+*----------------------------------------------------------------------------------------
+*                            L I C E N S E
+*----------------------------------------------------------------------------------------
+* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as published by the Free
+* Software Foundation, either version 3 of the License, or (at your option) any later
+* version.
+*
+* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+* PURPOSE. See the GNU General Public License for more details.
+*
+* You have received a copy of the GNU General Public License along with OpenBLT. It 
+* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
+*
+* \endinternal
+****************************************************************************************/
+#ifndef LED_H
+#define LED_H
+
+/****************************************************************************************
+* Function prototypes
+****************************************************************************************/
+void LedBlinkInit(blt_int16u interval_ms);
+void LedBlinkTask(void);
+void LedBlinkExit(void);
+
+
+#endif /* LED_H */
+/*********************************** end of led.h **************************************/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h
new file mode 100644
index 00000000..cdcde7d9
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h
@@ -0,0 +1,26288 @@
+/**
+  ******************************************************************************
+  * @file    stm32h743xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32H743xx Device Peripheral Access Layer Header File.
+  *
+  *          This file contains:
+  *           - Data structures and the address mapping for all peripherals
+  *           - Peripheral's registers declarations and bits definition
+  *           - Macros to access peripheral's registers hardware
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS_Device
+  * @{
+  */
+
+/** @addtogroup stm32h743xx
+  * @{
+  */
+
+#ifndef STM32H743xx_H
+#define STM32H743xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+  * @{
+  */
+
+/**
+ * @brief STM32H7XX Interrupt Number Definition, according to the selected device
+ *        in @ref Library_configuration_section
+ */
+typedef enum
+{
+/******  Cortex-M Processor Exceptions Numbers *****************************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
+  HardFault_IRQn              = -13,    /*!< 4 Cortex-M Memory Management Interrupt                            */
+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M Memory Management Interrupt                            */
+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M Bus Fault Interrupt                                    */
+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M Usage Fault Interrupt                                  */
+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M SV Call Interrupt                                     */
+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M Debug Monitor Interrupt                               */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M Pend SV Interrupt                                     */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M System Tick Interrupt                                 */
+/******  STM32 specific Interrupt Numbers **********************************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it)                   */
+  PVD_AVD_IRQn                = 1,      /*!< PVD/AVD through EXTI Line detection Interrupt                     */
+  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
+  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
+  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
+  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
+  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
+  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
+  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
+  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
+  ADC_IRQn                    = 18,     /*!< ADC1 and  ADC2 global Interrupts                                  */
+  FDCAN1_IT0_IRQn             = 19,     /*!< FDCAN1 Interrupt line 0                                           */
+  FDCAN2_IT0_IRQn             = 20,     /*!< FDCAN2 Interrupt line 0                                           */
+  FDCAN1_IT1_IRQn             = 21,     /*!< FDCAN1 Interrupt line 1                                           */
+  FDCAN2_IT1_IRQn             = 22,     /*!< FDCAN2 Interrupt line 1                                           */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
+  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                              */
+  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                             */
+  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt                            */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
+  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
+  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
+  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
+  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
+  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
+  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */
+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
+  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
+  DMA2_Stream0_IRQn           = 56,     /*!<   DMA2 Stream 0 global Interrupt                                  */
+  DMA2_Stream1_IRQn           = 57,     /*!<   DMA2 Stream 1 global Interrupt                                  */
+  DMA2_Stream2_IRQn           = 58,     /*!<   DMA2 Stream 2 global Interrupt                                  */
+  DMA2_Stream3_IRQn           = 59,     /*!<   DMA2 Stream 3 global Interrupt                                  */
+  DMA2_Stream4_IRQn           = 60,     /*!<   DMA2 Stream 4 global Interrupt                                  */
+  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
+  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
+  FDCAN_CAL_IRQn              = 63,     /*!< FDCAN Calibration unit Interrupt                                  */
+  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
+  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
+  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
+  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
+  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
+  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
+  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
+  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
+  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
+  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
+  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
+  RNG_IRQn                    = 80,     /*!< RNG global interrupt                                              */
+  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
+  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */
+  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */
+  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
+  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */
+  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */
+  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */
+  LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                             */
+  LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                       */
+  DMA2D_IRQn                  = 90,     /*!< DMA2D global Interrupt                                            */
+  SAI2_IRQn                   = 91,     /*!< SAI2 global Interrupt                                             */
+  QUADSPI_IRQn                = 92,     /*!< Quad SPI global interrupt                                         */
+  LPTIM1_IRQn                 = 93,     /*!< LP TIM1 interrupt                                                 */
+  CEC_IRQn                    = 94,     /*!< HDMI-CEC global Interrupt                                         */
+  I2C4_EV_IRQn                = 95,     /*!< I2C4 Event Interrupt                                              */
+  I2C4_ER_IRQn                = 96,     /*!< I2C4 Error Interrupt                                              */
+  SPDIF_RX_IRQn               = 97,     /*!< SPDIF-RX global Interrupt                                         */
+  OTG_FS_EP1_OUT_IRQn         = 98,     /*!< USB OTG HS2 global interrupt                                      */
+  OTG_FS_EP1_IN_IRQn          = 99,     /*!< USB OTG HS2 End Point 1 Out global interrupt                      */
+  OTG_FS_WKUP_IRQn            = 100,    /*!< USB OTG HS2 End Point 1 In global interrupt                       */
+  OTG_FS_IRQn                 = 101,    /*!< USB OTG HS2 Wakeup through EXTI interrupt                         */
+  DMAMUX1_OVR_IRQn            = 102,    /*!<DMAMUX1 Overrun interrupt                                          */
+  HRTIM1_Master_IRQn          = 103,    /*!< HRTIM Master Timer global Interrupts                              */
+  HRTIM1_TIMA_IRQn            = 104,    /*!< HRTIM Timer A global Interrupt                                    */
+  HRTIM1_TIMB_IRQn            = 105,    /*!< HRTIM Timer B global Interrupt                                    */
+  HRTIM1_TIMC_IRQn            = 106,    /*!< HRTIM Timer C global Interrupt                                    */
+  HRTIM1_TIMD_IRQn            = 107,    /*!< HRTIM Timer D global Interrupt                                    */
+  HRTIM1_TIME_IRQn            = 108,    /*!< HRTIM Timer E global Interrupt                                    */
+  HRTIM1_FLT_IRQn             = 109,    /*!< HRTIM Fault global Interrupt                                      */
+  DFSDM1_FLT0_IRQn            = 110,    /*!<DFSDM Filter1 Interrupt                                            */
+  DFSDM1_FLT1_IRQn            = 111,    /*!<DFSDM Filter2 Interrupt                                            */
+  DFSDM1_FLT2_IRQn            = 112,    /*!<DFSDM Filter3 Interrupt                                            */
+  DFSDM1_FLT3_IRQn            = 113,    /*!<DFSDM Filter4 Interrupt                                            */
+  SAI3_IRQn                   = 114,    /*!< SAI3 global Interrupt                                             */
+  SWPMI1_IRQn                 = 115,    /*!< Serial Wire Interface 1 global interrupt                          */
+  TIM15_IRQn                  = 116,    /*!< TIM15 global Interrupt                                            */
+  TIM16_IRQn                  = 117,    /*!< TIM16 global Interrupt                                            */
+  TIM17_IRQn                  = 118,    /*!< TIM17 global Interrupt                                            */
+  MDIOS_WKUP_IRQn             = 119,    /*!< MDIOS Wakeup  Interrupt                                           */
+  MDIOS_IRQn                  = 120,    /*!< MDIOS global Interrupt                                            */
+  JPEG_IRQn                   = 121,    /*!< JPEG global Interrupt                                             */
+  MDMA_IRQn                   = 122,    /*!< MDMA global Interrupt                                             */
+  SDMMC2_IRQn                 = 124,    /*!< SDMMC2 global Interrupt                                           */
+  HSEM1_IRQn                  = 125,    /*!< HSEM1 global Interrupt                                            */
+  ADC3_IRQn                   = 127,    /*!< ADC3 global Interrupt                                             */
+  DMAMUX2_OVR_IRQn            = 128,    /*!<DMAMUX2 Overrun interrupt                                          */
+  BDMA_Channel0_IRQn          = 129,    /*!< BDMA Channel 0 global Interrupt                                   */
+  BDMA_Channel1_IRQn          = 130,    /*!< BDMA Channel 1 global Interrupt                                   */
+  BDMA_Channel2_IRQn          = 131,    /*!< BDMA Channel 2 global Interrupt                                   */
+  BDMA_Channel3_IRQn          = 132,    /*!< BDMA Channel 3 global Interrupt                                   */
+  BDMA_Channel4_IRQn          = 133,    /*!< BDMA Channel 4 global Interrupt                                   */
+  BDMA_Channel5_IRQn          = 134,    /*!< BDMA Channel 5 global Interrupt                                   */
+  BDMA_Channel6_IRQn          = 135,    /*!< BDMA Channel 6 global Interrupt                                   */
+  BDMA_Channel7_IRQn          = 136,    /*!< BDMA Channel 7 global Interrupt                                   */
+  COMP_IRQn                   = 137 ,   /*!< COMP global Interrupt                                             */
+  LPTIM2_IRQn                 = 138,    /*!< LP TIM2 global interrupt                                          */
+  LPTIM3_IRQn                 = 139,    /*!< LP TIM3 global interrupt                                          */
+  LPTIM4_IRQn                 = 140,    /*!< LP TIM4 global interrupt                                          */
+  LPTIM5_IRQn                 = 141,    /*!< LP TIM5 global interrupt                                          */
+  LPUART1_IRQn                = 142,    /*!< LP UART1 interrupt                                                */
+  CRS_IRQn                    = 144,    /*!< Clock Recovery Global Interrupt                                   */
+  ECC_IRQn                    = 145,    /*!< ECC diagnostic Global Interrupt                                   */
+  SAI4_IRQn                   = 146,    /*!< SAI4 global interrupt                                             */
+  WAKEUP_PIN_IRQn             = 149,    /*!< Interrupt for all 6 wake-up pins                                  */
+} IRQn_Type;
+
+/**
+  * @}
+  */
+
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+
+
+
+
+/**
+  * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
+   */
+#define __CM7_REV               0x0100U   /*!< Cortex-M7 revision r1p0                       */
+#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */
+#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */
+#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1       /*!< FPU present                                   */
+#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */
+#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */
+#include "core_cm7.h"                     /*!< Cortex-M7 processor and core peripherals      */
+
+/**
+  * @}
+  */
+
+
+
+
+#include "system_stm32h7xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+  * @{
+  */
+
+/**
+  * @brief Analog to Digital Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t ISR;              /*!< ADC Interrupt and Status Register,                          Address offset: 0x00 */
+  __IO uint32_t IER;              /*!< ADC Interrupt Enable Register,                              Address offset: 0x04 */
+  __IO uint32_t CR;               /*!< ADC control register,                                       Address offset: 0x08 */
+  __IO uint32_t CFGR;             /*!< ADC Configuration register,                                 Address offset: 0x0C */
+  __IO uint32_t CFGR2;            /*!< ADC Configuration register 2,                               Address offset: 0x10 */
+  __IO uint32_t SMPR1;            /*!< ADC sample time register 1,                                 Address offset: 0x14 */
+  __IO uint32_t SMPR2;            /*!< ADC sample time register 2,                                 Address offset: 0x18 */
+  __IO uint32_t PCSEL;            /*!< ADC pre-channel selection,                                  Address offset: 0x1C */
+  __IO uint32_t LTR1;             /*!< ADC watchdog Lower threshold register 1,                    Address offset: 0x20 */
+  __IO uint32_t HTR1;             /*!< ADC watchdog higher threshold register 1,                   Address offset: 0x24 */
+  uint32_t      RESERVED1;        /*!< Reserved, 0x028                                                                  */
+  uint32_t      RESERVED2;        /*!< Reserved, 0x02C                                                                  */
+  __IO uint32_t SQR1;             /*!< ADC regular sequence register 1,                            Address offset: 0x30 */
+  __IO uint32_t SQR2;             /*!< ADC regular sequence register 2,                            Address offset: 0x34 */
+  __IO uint32_t SQR3;             /*!< ADC regular sequence register 3,                            Address offset: 0x38 */
+  __IO uint32_t SQR4;             /*!< ADC regular sequence register 4,                            Address offset: 0x3C */
+  __IO uint32_t DR;               /*!< ADC regular data register,                                  Address offset: 0x40 */
+  uint32_t      RESERVED3;        /*!< Reserved, 0x044                                                                  */
+  uint32_t      RESERVED4;        /*!< Reserved, 0x048                                                                  */
+  __IO uint32_t JSQR;             /*!< ADC injected sequence register,                             Address offset: 0x4C */
+  uint32_t      RESERVED5[4];     /*!< Reserved, 0x050 - 0x05C                                                          */
+  __IO uint32_t OFR1;             /*!< ADC offset register 1,                                      Address offset: 0x60 */
+  __IO uint32_t OFR2;             /*!< ADC offset register 2,                                      Address offset: 0x64 */
+  __IO uint32_t OFR3;             /*!< ADC offset register 3,                                      Address offset: 0x68 */
+  __IO uint32_t OFR4;             /*!< ADC offset register 4,                                      Address offset: 0x6C */
+  uint32_t      RESERVED6[4];     /*!< Reserved, 0x070 - 0x07C                                                          */
+  __IO uint32_t JDR1;             /*!< ADC injected data register 1,                               Address offset: 0x80 */
+  __IO uint32_t JDR2;             /*!< ADC injected data register 2,                               Address offset: 0x84 */
+  __IO uint32_t JDR3;             /*!< ADC injected data register 3,                               Address offset: 0x88 */
+  __IO uint32_t JDR4;             /*!< ADC injected data register 4,                               Address offset: 0x8C */
+  uint32_t      RESERVED7[4];     /*!< Reserved, 0x090 - 0x09C                                                          */
+  __IO uint32_t AWD2CR;           /*!< ADC  Analog Watchdog 2 Configuration Register,              Address offset: 0xA0 */
+  __IO uint32_t AWD3CR;           /*!< ADC  Analog Watchdog 3 Configuration Register,              Address offset: 0xA4 */
+  uint32_t      RESERVED8;        /*!< Reserved, 0x0A8                                                                  */
+  uint32_t      RESERVED9;        /*!< Reserved, 0x0AC                                                                  */
+  __IO uint32_t LTR2;             /*!< ADC watchdog Lower threshold register 2,                    Address offset: 0xB0 */
+  __IO uint32_t HTR2;             /*!< ADC watchdog Higher threshold register 2,                   Address offset: 0xB4 */
+  __IO uint32_t LTR3;             /*!< ADC watchdog Lower threshold register 3,                    Address offset: 0xB8 */
+  __IO uint32_t HTR3;             /*!< ADC watchdog Higher threshold register 3,                   Address offset: 0xBC */
+  __IO uint32_t DIFSEL;           /*!< ADC  Differential Mode Selection Register,                  Address offset: 0xC0 */
+  __IO uint32_t CALFACT;          /*!< ADC  Calibration Factors,                                   Address offset: 0xC4 */
+  __IO uint32_t CALFACT2;         /*!< ADC  Linearity Calibration Factors,                         Address offset: 0xC8 */
+} ADC_TypeDef;
+
+
+typedef struct
+{
+__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
+uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
+__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
+__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */
+__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */
+
+} ADC_Common_TypeDef;
+
+
+/**
+  * @brief VREFBUF
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */
+  __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */
+} VREFBUF_TypeDef;
+
+
+/**
+  * @brief FD Controller Area Network
+  */
+
+typedef struct
+{
+  __IO uint32_t CREL;         /*!< FDCAN Core Release register,                                     Address offset: 0x000 */
+  __IO uint32_t ENDN;         /*!< FDCAN Endian register,                                           Address offset: 0x004 */
+  __IO uint32_t RESERVED1;    /*!< Reserved,                                                                        0x008 */
+  __IO uint32_t DBTP;         /*!< FDCAN Data Bit Timing & Prescaler register,                      Address offset: 0x00C */
+  __IO uint32_t TEST;         /*!< FDCAN Test register,                                             Address offset: 0x010 */
+  __IO uint32_t RWD;          /*!< FDCAN RAM Watchdog register,                                     Address offset: 0x014 */
+  __IO uint32_t CCCR;         /*!< FDCAN CC Control register,                                       Address offset: 0x018 */
+  __IO uint32_t NBTP;         /*!< FDCAN Nominal Bit Timing & Prescaler register,                   Address offset: 0x01C */
+  __IO uint32_t TSCC;         /*!< FDCAN Timestamp Counter Configuration register,                  Address offset: 0x020 */
+  __IO uint32_t TSCV;         /*!< FDCAN Timestamp Counter Value register,                          Address offset: 0x024 */
+  __IO uint32_t TOCC;         /*!< FDCAN Timeout Counter Configuration register,                    Address offset: 0x028 */
+  __IO uint32_t TOCV;         /*!< FDCAN Timeout Counter Value register,                            Address offset: 0x02C */
+  __IO uint32_t RESERVED2[4]; /*!< Reserved,                                                                0x030 - 0x03C */
+  __IO uint32_t ECR;          /*!< FDCAN Error Counter register,                                    Address offset: 0x040 */
+  __IO uint32_t PSR;          /*!< FDCAN Protocol Status register,                                  Address offset: 0x044 */
+  __IO uint32_t TDCR;         /*!< FDCAN Transmitter Delay Compensation register,                   Address offset: 0x048 */
+  __IO uint32_t RESERVED3;    /*!< Reserved,                                                                        0x04C */
+  __IO uint32_t IR;           /*!< FDCAN Interrupt register,                                        Address offset: 0x050 */
+  __IO uint32_t IE;           /*!< FDCAN Interrupt Enable register,                                 Address offset: 0x054 */
+  __IO uint32_t ILS;          /*!< FDCAN Interrupt Line Select register,                            Address offset: 0x058 */
+  __IO uint32_t ILE;          /*!< FDCAN Interrupt Line Enable register,                            Address offset: 0x05C */
+  __IO uint32_t RESERVED4[8]; /*!< Reserved,                                                                0x060 - 0x07C */
+  __IO uint32_t GFC;          /*!< FDCAN Global Filter Configuration register,                      Address offset: 0x080 */
+  __IO uint32_t SIDFC;        /*!< FDCAN Standard ID Filter Configuration register,                 Address offset: 0x084 */
+  __IO uint32_t XIDFC;        /*!< FDCAN Extended ID Filter Configuration register,                 Address offset: 0x088 */
+  __IO uint32_t RESERVED5;    /*!< Reserved,                                                                        0x08C */
+  __IO uint32_t XIDAM;        /*!< FDCAN Extended ID AND Mask register,                             Address offset: 0x090 */
+  __IO uint32_t HPMS;         /*!< FDCAN High Priority Message Status register,                     Address offset: 0x094 */
+  __IO uint32_t NDAT1;        /*!< FDCAN New Data 1 register,                                       Address offset: 0x098 */
+  __IO uint32_t NDAT2;        /*!< FDCAN New Data 2 register,                                       Address offset: 0x09C */
+  __IO uint32_t RXF0C;        /*!< FDCAN Rx FIFO 0 Configuration register,                          Address offset: 0x0A0 */
+  __IO uint32_t RXF0S;        /*!< FDCAN Rx FIFO 0 Status register,                                 Address offset: 0x0A4 */
+  __IO uint32_t RXF0A;        /*!< FDCAN Rx FIFO 0 Acknowledge register,                            Address offset: 0x0A8 */
+  __IO uint32_t RXBC;         /*!< FDCAN Rx Buffer Configuration register,                          Address offset: 0x0AC */
+  __IO uint32_t RXF1C;        /*!< FDCAN Rx FIFO 1 Configuration register,                          Address offset: 0x0B0 */
+  __IO uint32_t RXF1S;        /*!< FDCAN Rx FIFO 1 Status register,                                 Address offset: 0x0B4 */
+  __IO uint32_t RXF1A;        /*!< FDCAN Rx FIFO 1 Acknowledge register,                            Address offset: 0x0B8 */
+  __IO uint32_t RXESC;        /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register,        Address offset: 0x0BC */
+  __IO uint32_t TXBC;         /*!< FDCAN Tx Buffer Configuration register,                          Address offset: 0x0C0 */
+  __IO uint32_t TXFQS;        /*!< FDCAN Tx FIFO/Queue Status register,                             Address offset: 0x0C4 */
+  __IO uint32_t TXESC;        /*!< FDCAN Tx Buffer Element Size Configuration register,             Address offset: 0x0C8 */
+  __IO uint32_t TXBRP;        /*!< FDCAN Tx Buffer Request Pending register,                        Address offset: 0x0CC */
+  __IO uint32_t TXBAR;        /*!< FDCAN Tx Buffer Add Request register,                            Address offset: 0x0D0 */
+  __IO uint32_t TXBCR;        /*!< FDCAN Tx Buffer Cancellation Request register,                   Address offset: 0x0D4 */
+  __IO uint32_t TXBTO;        /*!< FDCAN Tx Buffer Transmission Occurred register,                  Address offset: 0x0D8 */
+  __IO uint32_t TXBCF;        /*!< FDCAN Tx Buffer Cancellation Finished register,                  Address offset: 0x0DC */
+  __IO uint32_t TXBTIE;       /*!< FDCAN Tx Buffer Transmission Interrupt Enable register,          Address offset: 0x0E0 */
+  __IO uint32_t TXBCIE;       /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */
+  __IO uint32_t RESERVED6[2]; /*!< Reserved,                                                                0x0E8 - 0x0EC */
+  __IO uint32_t TXEFC;        /*!< FDCAN Tx Event FIFO Configuration register,                      Address offset: 0x0F0 */
+  __IO uint32_t TXEFS;        /*!< FDCAN Tx Event FIFO Status register,                             Address offset: 0x0F4 */
+  __IO uint32_t TXEFA;        /*!< FDCAN Tx Event FIFO Acknowledge register,                        Address offset: 0x0F8 */
+  __IO uint32_t RESERVED7;    /*!< Reserved,                                                                        0x0FC */
+} FDCAN_GlobalTypeDef;
+
+/**
+  * @brief TTFD Controller Area Network
+  */
+
+typedef struct
+{
+  __IO uint32_t TTTMC;          /*!< TT Trigger Memory Configuration register,    Address offset: 0x100 */
+  __IO uint32_t TTRMC;          /*!< TT Reference Message Configuration register, Address offset: 0x104 */
+  __IO uint32_t TTOCF;          /*!< TT Operation Configuration register,         Address offset: 0x108 */
+  __IO uint32_t TTMLM;          /*!< TT Matrix Limits register,                   Address offset: 0x10C */
+  __IO uint32_t TURCF;          /*!< TUR Configuration register,                  Address offset: 0x110 */
+  __IO uint32_t TTOCN;          /*!< TT Operation Control register,               Address offset: 0x114 */
+  __IO uint32_t TTGTP;          /*!< TT Global Time Preset register,              Address offset: 0x118 */
+  __IO uint32_t TTTMK;          /*!< TT Time Mark register,                       Address offset: 0x11C */
+  __IO uint32_t TTIR;           /*!< TT Interrupt register,                       Address offset: 0x120 */
+  __IO uint32_t TTIE;           /*!< TT Interrupt Enable register,                Address offset: 0x124 */
+  __IO uint32_t TTILS;          /*!< TT Interrupt Line Select register,           Address offset: 0x128 */
+  __IO uint32_t TTOST;          /*!< TT Operation Status register,                Address offset: 0x12C */
+  __IO uint32_t TURNA;          /*!< TT TUR Numerator Actual register,            Address offset: 0x130 */
+  __IO uint32_t TTLGT;          /*!< TT Local and Global Time register,           Address offset: 0x134 */
+  __IO uint32_t TTCTC;          /*!< TT Cycle Time and Count register,            Address offset: 0x138 */
+  __IO uint32_t TTCPT;          /*!< TT Capture Time register,                    Address offset: 0x13C */
+  __IO uint32_t TTCSM;          /*!< TT Cycle Sync Mark register,                 Address offset: 0x140 */
+  __IO uint32_t RESERVED1[111]; /*!< Reserved,                                            0x144 - 0x2FC */
+  __IO uint32_t TTTS;           /*!< TT Trigger Select register,                  Address offset: 0x300 */
+} TTCAN_TypeDef;
+
+/**
+  * @brief FD Controller Area Network
+  */
+
+typedef struct
+{
+  __IO uint32_t CREL;  /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */
+  __IO uint32_t CCFG;  /*!< Calibration Configuration register,           Address offset: 0x04 */
+  __IO uint32_t CSTAT; /*!< Calibration Status register,                  Address offset: 0x08 */
+  __IO uint32_t CWD;   /*!< Calibration Watchdog register,                Address offset: 0x0C */
+  __IO uint32_t IR;    /*!< CCU Interrupt register,                       Address offset: 0x10 */
+  __IO uint32_t IE;    /*!< CCU Interrupt Enable register,                Address offset: 0x14 */
+} FDCAN_ClockCalibrationUnit_TypeDef;
+
+
+/**
+  * @brief Consumer Electronics Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;           /*!< CEC control register,              Address offset:0x00 */
+  __IO uint32_t CFGR;         /*!< CEC configuration register,        Address offset:0x04 */
+  __IO uint32_t TXDR;         /*!< CEC Tx data register ,             Address offset:0x08 */
+  __IO uint32_t RXDR;         /*!< CEC Rx Data Register,              Address offset:0x0C */
+  __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register, Address offset:0x10 */
+  __IO uint32_t IER;          /*!< CEC interrupt enable register,     Address offset:0x14 */
+}CEC_TypeDef;
+
+/**
+  * @brief CRC calculation unit
+  */
+
+typedef struct
+{
+  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
+  __IO uint32_t IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
+  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
+  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */
+  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
+  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
+} CRC_TypeDef;
+
+
+/**
+  * @brief Clock Recovery System
+  */
+typedef struct
+{
+__IO uint32_t CR;            /*!< CRS ccontrol register,              Address offset: 0x00 */
+__IO uint32_t CFGR;          /*!< CRS configuration register,         Address offset: 0x04 */
+__IO uint32_t ISR;           /*!< CRS interrupt and status register,  Address offset: 0x08 */
+__IO uint32_t ICR;           /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
+} CRS_TypeDef;
+
+
+/**
+  * @brief Digital to Analog Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
+  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
+  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
+  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
+  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
+  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
+  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
+  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
+  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
+  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
+  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
+  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
+  __IO uint32_t CCR;      /*!< DAC calibration control register,                        Address offset: 0x38 */
+  __IO uint32_t MCR;      /*!< DAC mode control register,                               Address offset: 0x3C */
+  __IO uint32_t SHSR1;    /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */
+  __IO uint32_t SHSR2;    /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */
+  __IO uint32_t SHHR;     /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */
+  __IO uint32_t SHRR;     /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */
+} DAC_TypeDef;
+
+/**
+  * @brief DFSDM module registers
+  */
+typedef struct
+{
+  __IO uint32_t FLTCR1;          /*!< DFSDM control register1,                          Address offset: 0x100 */
+  __IO uint32_t FLTCR2;          /*!< DFSDM control register2,                          Address offset: 0x104 */
+  __IO uint32_t FLTISR;          /*!< DFSDM interrupt and status register,              Address offset: 0x108 */
+  __IO uint32_t FLTICR;          /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */
+  __IO uint32_t FLTJCHGR;        /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */
+  __IO uint32_t FLTFCR;          /*!< DFSDM filter control register,                    Address offset: 0x114 */
+  __IO uint32_t FLTJDATAR;       /*!< DFSDM data register for injected group,           Address offset: 0x118 */
+  __IO uint32_t FLTRDATAR;       /*!< DFSDM data register for regular group,            Address offset: 0x11C */
+  __IO uint32_t FLTAWHTR;        /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */
+  __IO uint32_t FLTAWLTR;        /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */
+  __IO uint32_t FLTAWSR;         /*!< DFSDM analog watchdog status register             Address offset: 0x128 */
+  __IO uint32_t FLTAWCFR;        /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */
+  __IO uint32_t FLTEXMAX;        /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */
+  __IO uint32_t FLTEXMIN;        /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */
+  __IO uint32_t FLTCNVTIMR;      /*!< DFSDM conversion timer,                           Address offset: 0x138 */
+} DFSDM_Filter_TypeDef;
+
+/**
+  * @brief DFSDM channel configuration registers
+  */
+typedef struct
+{
+  __IO uint32_t CHCFGR1;      /*!< DFSDM channel configuration register1,            Address offset: 0x00 */
+  __IO uint32_t CHCFGR2;      /*!< DFSDM channel configuration register2,            Address offset: 0x04 */
+  __IO uint32_t CHAWSCDR;     /*!< DFSDM channel analog watchdog and
+                                   short circuit detector register,                  Address offset: 0x08 */
+  __IO uint32_t CHWDATAR;     /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */
+  __IO uint32_t CHDATINR;     /*!< DFSDM channel data input register,                Address offset: 0x10 */
+} DFSDM_Channel_TypeDef;
+
+/**
+  * @brief Debug MCU
+  */
+typedef struct
+{
+  __IO uint32_t IDCODE;        /*!< MCU device ID code,                     Address offset: 0x00 */
+  __IO uint32_t CR;            /*!< Debug MCU configuration register,       Address offset: 0x04 */
+  uint32_t RESERVED4[11];      /*!< Reserved,                             Address offset: 0x08 */
+  __IO uint32_t APB3FZ1;     /*!< Debug MCU APB3FZ1 freeze register,    Address offset: 0x34 */
+  uint32_t RESERVED5;          /*!< Reserved,                             Address offset: 0x38 */
+  __IO uint32_t APB1LFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x3C */
+  uint32_t RESERVED6;          /*!< Reserved,                             Address offset: 0x40 */
+  __IO uint32_t APB1HFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x44 */
+  uint32_t RESERVED7;          /*!< Reserved,                             Address offset: 0x48 */
+  __IO uint32_t APB2FZ1;     /*!< Debug MCU APB2FZ1 freeze register,    Address offset: 0x4C */
+  uint32_t RESERVED8;          /*!< Reserved,                             Address offset: 0x50 */
+  __IO uint32_t APB4FZ1;     /*!< Debug MCU APB4FZ1 freeze register,    Address offset: 0x54 */
+}DBGMCU_TypeDef;
+/**
+  * @brief DCMI
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
+  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
+  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
+  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
+  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
+  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
+  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
+  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
+  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
+  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
+} DCMI_TypeDef;
+
+/**
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
+  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
+  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
+  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
+  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
+  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
+  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
+  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
+  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CCR;          /*!< DMA channel x configuration register          */
+  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register         */
+  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register     */
+  __IO uint32_t CM0AR;        /*!< DMA channel x memory 0 address register       */
+  __IO uint32_t CM1AR;        /*!< DMA channel x memory 1 address register       */
+} BDMA_Channel_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
+  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
+} BDMA_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t  CCR;        /*!< DMA Multiplexer Channel x Control Register   */
+}DMAMUX_Channel_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t  CSR;      /*!< DMA Channel Status Register     */
+  __IO uint32_t  CFR;      /*!< DMA Channel Clear Flag Register */
+}DMAMUX_ChannelStatus_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t  RGCR;        /*!< DMA Request Generator x Control Register   */
+}DMAMUX_RequestGen_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t  RGSR;        /*!< DMA Request Generator Status Register       */
+  __IO uint32_t  RGCFR;       /*!< DMA Request Generator Clear Flag Register   */
+}DMAMUX_RequestGenStatus_TypeDef;
+
+/**
+  * @brief MDMA Controller
+  */
+typedef struct
+{
+  __IO uint32_t  GISR0;   /*!< MDMA Global Interrupt/Status Register 0,          Address offset: 0x00 */
+}MDMA_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t  CISR;      /*!< MDMA channel x interrupt/status register,             Address offset: 0x40 */
+  __IO uint32_t  CIFCR;     /*!< MDMA channel x interrupt flag clear register,         Address offset: 0x44 */
+  __IO uint32_t  CESR;      /*!< MDMA Channel x error status register,                 Address offset: 0x48 */
+  __IO uint32_t  CCR;       /*!< MDMA channel x control register,                      Address offset: 0x4C */
+  __IO uint32_t  CTCR;      /*!< MDMA channel x Transfer Configuration register,       Address offset: 0x50 */
+  __IO uint32_t  CBNDTR;    /*!< MDMA Channel x block number of data register,         Address offset: 0x54 */
+  __IO uint32_t  CSAR;      /*!< MDMA channel x source address register,               Address offset: 0x58 */
+  __IO uint32_t  CDAR;      /*!< MDMA channel x destination address register,          Address offset: 0x5C */
+  __IO uint32_t  CBRUR;     /*!< MDMA channel x Block Repeat address Update register,  Address offset: 0x60 */
+  __IO uint32_t  CLAR;      /*!< MDMA channel x Link Address register,                 Address offset: 0x64 */
+  __IO uint32_t  CTBR;      /*!< MDMA channel x Trigger and Bus selection Register,    Address offset: 0x68 */
+  uint32_t       RESERVED0; /*!< Reserved, 0x68                                                             */
+  __IO uint32_t  CMAR;      /*!< MDMA channel x Mask address register,                 Address offset: 0x70 */
+  __IO uint32_t  CMDR;      /*!< MDMA channel x Mask Data register,                    Address offset: 0x74 */
+}MDMA_Channel_TypeDef;
+
+/**
+  * @brief DMA2D Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */
+  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */
+  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */
+  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */
+  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */
+  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */
+  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */
+  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */
+  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */
+  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */
+  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */
+  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */
+  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */
+  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */
+  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */
+  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */
+  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */
+  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */
+  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */
+  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */
+  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
+  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */
+  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */
+} DMA2D_TypeDef;
+
+
+/**
+  * @brief Ethernet MAC
+  */
+typedef struct
+{
+  __IO uint32_t MACCR;
+  __IO uint32_t MACECR;
+  __IO uint32_t MACPFR;
+  __IO uint32_t MACWTR;
+  __IO uint32_t MACHT0R;
+  __IO uint32_t MACHT1R;
+  uint32_t      RESERVED1[14];
+  __IO uint32_t MACVTR;
+  uint32_t      RESERVED2;
+  __IO uint32_t MACVHTR;
+  uint32_t      RESERVED3;
+  __IO uint32_t MACVIR;
+  __IO uint32_t MACIVIR;
+  uint32_t      RESERVED4[2];
+  __IO uint32_t MACTFCR;
+  uint32_t      RESERVED5[7];
+  __IO uint32_t MACRFCR;
+  uint32_t      RESERVED6[7];
+  __IO uint32_t MACISR;
+  __IO uint32_t MACIER;
+  __IO uint32_t MACRXTXSR;
+  uint32_t      RESERVED7;
+  __IO uint32_t MACPCSR;
+  __IO uint32_t MACRWKPFR;
+  uint32_t      RESERVED8[2];
+  __IO uint32_t MACLCSR;
+  __IO uint32_t MACLTCR;
+  __IO uint32_t MACLETR;
+  __IO uint32_t MAC1USTCR;
+  uint32_t      RESERVED9[12];
+  __IO uint32_t MACVR;
+  __IO uint32_t MACDR;
+  uint32_t      RESERVED10;
+  __IO uint32_t MACHWF0R;
+  __IO uint32_t MACHWF1R;
+  __IO uint32_t MACHWF2R;
+  uint32_t      RESERVED11[54];
+  __IO uint32_t MACMDIOAR;
+  __IO uint32_t MACMDIODR;
+  uint32_t      RESERVED12[2];
+  __IO uint32_t MACARPAR;
+  uint32_t      RESERVED13[59];
+  __IO uint32_t MACA0HR;
+  __IO uint32_t MACA0LR;
+  __IO uint32_t MACA1HR;
+  __IO uint32_t MACA1LR;
+  __IO uint32_t MACA2HR;
+  __IO uint32_t MACA2LR;
+  __IO uint32_t MACA3HR;
+  __IO uint32_t MACA3LR;
+  uint32_t      RESERVED14[248];
+  __IO uint32_t MMCCR;
+  __IO uint32_t MMCRIR;
+  __IO uint32_t MMCTIR;
+  __IO uint32_t MMCRIMR;
+  __IO uint32_t MMCTIMR;
+  uint32_t      RESERVED15[14];
+  __IO uint32_t MMCTSCGPR;
+  __IO uint32_t MMCTMCGPR;
+  uint32_t      RESERVED16[5];
+  __IO uint32_t MMCTPCGR;
+  uint32_t      RESERVED17[10];
+  __IO uint32_t MMCRCRCEPR;
+  __IO uint32_t MMCRAEPR;
+  uint32_t      RESERVED18[10];
+  __IO uint32_t MMCRUPGR;
+  uint32_t      RESERVED19[9];
+  __IO uint32_t MMCTLPIMSTR;
+  __IO uint32_t MMCTLPITCR;
+  __IO uint32_t MMCRLPIMSTR;
+  __IO uint32_t MMCRLPITCR;
+  uint32_t      RESERVED20[65];
+  __IO uint32_t MACL3L4C0R;
+  __IO uint32_t MACL4A0R;
+  uint32_t      RESERVED21[2];
+  __IO uint32_t MACL3A0R0R;
+  __IO uint32_t MACL3A1R0R;
+  __IO uint32_t MACL3A2R0R;
+  __IO uint32_t MACL3A3R0R;
+  uint32_t      RESERVED22[4];
+  __IO uint32_t MACL3L4C1R;
+  __IO uint32_t MACL4A1R;
+  uint32_t      RESERVED23[2];
+  __IO uint32_t MACL3A0R1R;
+  __IO uint32_t MACL3A1R1R;
+  __IO uint32_t MACL3A2R1R;
+  __IO uint32_t MACL3A3R1R;
+  uint32_t      RESERVED24[108];
+  __IO uint32_t MACTSCR;
+  __IO uint32_t MACSSIR;
+  __IO uint32_t MACSTSR;
+  __IO uint32_t MACSTNR;
+  __IO uint32_t MACSTSUR;
+  __IO uint32_t MACSTNUR;
+  __IO uint32_t MACTSAR;
+  uint32_t      RESERVED25;
+  __IO uint32_t MACTSSR;
+  uint32_t      RESERVED26[3];
+  __IO uint32_t MACTTSSNR;
+  __IO uint32_t MACTTSSSR;
+  uint32_t      RESERVED27[2];
+  __IO uint32_t MACACR;
+  uint32_t      RESERVED28;
+  __IO uint32_t MACATSNR;
+  __IO uint32_t MACATSSR;
+  __IO uint32_t MACTSIACR;
+  __IO uint32_t MACTSEACR;
+  __IO uint32_t MACTSICNR;
+  __IO uint32_t MACTSECNR;
+  uint32_t      RESERVED29[4];
+  __IO uint32_t MACPPSCR;
+  uint32_t      RESERVED30[3];
+  __IO uint32_t MACPPSTTSR;
+  __IO uint32_t MACPPSTTNR;
+  __IO uint32_t MACPPSIR;
+  __IO uint32_t MACPPSWR;
+  uint32_t      RESERVED31[12];
+  __IO uint32_t MACPOCR;
+  __IO uint32_t MACSPI0R;
+  __IO uint32_t MACSPI1R;
+  __IO uint32_t MACSPI2R;
+  __IO uint32_t MACLMIR;
+  uint32_t      RESERVED32[11];
+  __IO uint32_t MTLOMR;
+  uint32_t      RESERVED33[7];
+  __IO uint32_t MTLISR;
+  uint32_t      RESERVED34[55];
+  __IO uint32_t MTLTQOMR;
+  __IO uint32_t MTLTQUR;
+  __IO uint32_t MTLTQDR;
+  uint32_t      RESERVED35[8];
+  __IO uint32_t MTLQICSR;
+  __IO uint32_t MTLRQOMR;
+  __IO uint32_t MTLRQMPOCR;
+  __IO uint32_t MTLRQDR;
+  uint32_t      RESERVED36[177];
+  __IO uint32_t DMAMR;
+  __IO uint32_t DMASBMR;
+  __IO uint32_t DMAISR;
+  __IO uint32_t DMADSR;
+  uint32_t      RESERVED37[60];
+  __IO uint32_t DMACCR;
+  __IO uint32_t DMACTCR;
+  __IO uint32_t DMACRCR;
+  uint32_t      RESERVED38[2];
+  __IO uint32_t DMACTDLAR;
+  uint32_t      RESERVED39;
+  __IO uint32_t DMACRDLAR;
+  __IO uint32_t DMACTDTPR;
+  uint32_t      RESERVED40;
+  __IO uint32_t DMACRDTPR;
+  __IO uint32_t DMACTDRLR;
+  __IO uint32_t DMACRDRLR;
+  __IO uint32_t DMACIER;
+  __IO uint32_t DMACRIWTR;
+__IO uint32_t DMACSFCSR;
+  uint32_t      RESERVED41;
+  __IO uint32_t DMACCATDR;
+  uint32_t      RESERVED42;
+  __IO uint32_t DMACCARDR;
+  uint32_t      RESERVED43;
+  __IO uint32_t DMACCATBR;
+  uint32_t      RESERVED44;
+  __IO uint32_t DMACCARBR;
+  __IO uint32_t DMACSR;
+uint32_t      RESERVED45[2];
+__IO uint32_t DMACMFCR;
+}ETH_TypeDef;
+/**
+  * @brief External Interrupt/Event Controller
+  */
+
+typedef struct
+{
+__IO uint32_t RTSR1;               /*!< EXTI Rising trigger selection register,          Address offset: 0x00 */
+__IO uint32_t FTSR1;               /*!< EXTI Falling trigger selection register,         Address offset: 0x04 */
+__IO uint32_t SWIER1;              /*!< EXTI Software interrupt event register,          Address offset: 0x08 */
+__IO uint32_t D3PMR1;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */
+__IO uint32_t D3PCR1L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L)     Address offset: 0x10 */
+__IO uint32_t D3PCR1H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H)   Address offset: 0x14 */
+uint32_t      RESERVED1[2];        /*!< Reserved,                                        0x18 to 0x1C         */
+__IO uint32_t RTSR2;               /*!< EXTI Rising trigger selection register,          Address offset: 0x20 */
+__IO uint32_t FTSR2;               /*!< EXTI Falling trigger selection register,         Address offset: 0x24 */
+__IO uint32_t SWIER2;              /*!< EXTI Software interrupt event register,          Address offset: 0x28 */
+__IO uint32_t D3PMR2;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */
+__IO uint32_t D3PCR2L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L)  Address offset: 0x30 */
+__IO uint32_t D3PCR2H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */
+uint32_t      RESERVED2[2];        /*!< Reserved,                                        0x38 to 0x3C         */
+__IO uint32_t RTSR3;               /*!< EXTI Rising trigger selection register,          Address offset: 0x40 */
+__IO uint32_t FTSR3;               /*!< EXTI Falling trigger selection register,         Address offset: 0x44 */
+__IO uint32_t SWIER3;              /*!< EXTI Software interrupt event register,          Address offset: 0x48 */
+__IO uint32_t D3PMR3;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */
+__IO uint32_t D3PCR3L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */
+__IO uint32_t D3PCR3H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */
+uint32_t      RESERVED3[10];       /*!< Reserved,                                        0x58 to 0x7C         */
+__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                    Address offset: 0x80 */
+__IO uint32_t EMR1;                /*!< EXTI Event mask register,                        Address offset: 0x84 */
+__IO uint32_t PR1;                 /*!< EXTI Pending register,                           Address offset: 0x88 */
+uint32_t      RESERVED4;           /*!< Reserved,                                        0x8C                 */
+__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                    Address offset: 0x90 */
+__IO uint32_t EMR2;                /*!< EXTI Event mask register,                        Address offset: 0x94 */
+__IO uint32_t PR2;                 /*!< EXTI Pending register,                           Address offset: 0x98 */
+uint32_t      RESERVED5;           /*!< Reserved,                                        0x9C                 */
+__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                    Address offset: 0xA0 */
+__IO uint32_t EMR3;                /*!< EXTI Event mask register,                        Address offset: 0xA4 */
+__IO uint32_t PR3;                 /*!< EXTI Pending register,                           Address offset: 0xA8 */
+}EXTI_TypeDef;
+
+typedef struct
+{
+__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                Address offset: 0x00 */
+__IO uint32_t EMR1;                /*!< EXTI Event mask register,                    Address offset: 0x04 */
+__IO uint32_t PR1;                 /*!< EXTI Pending register,                       Address offset: 0x08 */
+uint32_t      RESERVED1;           /*!< Reserved, 0x0C                                                    */
+__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                Address offset: 0x10 */
+__IO uint32_t EMR2;                /*!< EXTI Event mask register,                    Address offset: 0x14 */
+__IO uint32_t PR2;                 /*!< EXTI Pending register,                       Address offset: 0x18 */
+uint32_t      RESERVED2;           /*!< Reserved, 0x1C                                                    */
+__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                Address offset: 0x20 */
+__IO uint32_t EMR3;                /*!< EXTI Event mask register,                    Address offset: 0x24 */
+__IO uint32_t PR3;                 /*!< EXTI Pending register,                       Address offset: 0x28 */
+}EXTI_Core_TypeDef;
+
+
+/**
+  * @brief FLASH Registers
+  */
+
+typedef struct
+{
+  __IO uint32_t ACR;             /*!< FLASH access control register,                            Address offset: 0x00  */
+  __IO uint32_t KEYR1;           /*!< Flash Key Register for bank1,                             Address offset: 0x04  */
+  __IO uint32_t OPTKEYR;         /*!< Flash Option Key Register,                                Address offset: 0x08  */
+  __IO uint32_t CR1;             /*!< Flash Control Register for bank1,                         Address offset: 0x0C  */
+  __IO uint32_t SR1;             /*!< Flash Status Register for bank1,                          Address offset: 0x10  */
+  __IO uint32_t CCR1;            /*!< Flash Control Register for bank1,                         Address offset: 0x14  */
+  __IO uint32_t OPTCR;           /*!< Flash Option Control Register,                            Address offset: 0x18  */
+  __IO uint32_t OPTSR_CUR;       /*!< Flash Option Status Current Register,                     Address offset: 0x1C  */
+  __IO uint32_t OPTSR_PRG;       /*!< Flash Option Status to Program Register,                  Address offset: 0x20  */
+  __IO uint32_t OPTCCR;          /*!< Flash Option Clear Control Register,                      Address offset: 0x24  */
+  __IO uint32_t PRAR_CUR1;       /*!< Flash Current Protection Address Register for bank1,      Address offset: 0x28  */
+  __IO uint32_t PRAR_PRG1;       /*!< Flash Protection Address to Program Register for bank1,   Address offset: 0x2C  */
+  __IO uint32_t SCAR_CUR1;       /*!< Flash Current Secure Address Register for bank1,          Address offset: 0x30  */
+  __IO uint32_t SCAR_PRG1;       /*!< Flash Secure Address to Program Register for bank1,       Address offset: 0x34  */
+  __IO uint32_t WPSN_CUR1;       /*!< Flash Current Write Protection Register on bank1,         Address offset: 0x38  */
+  __IO uint32_t WPSN_PRG1;       /*!< Flash Write Protection to Program Register on bank1,      Address offset: 0x3C  */
+  __IO uint32_t BOOT_CUR;        /*!< Flash Current Boot Address for Pelican Core Register,     Address offset: 0x40  */
+  __IO uint32_t BOOT_PRG;        /*!< Flash Boot Address to Program for Pelican Core Register,  Address offset: 0x44  */
+  uint32_t      RESERVED0[2];    /*!< Reserved, 0x48 to 0x4C                                                          */
+  __IO uint32_t CRCCR1;          /*!< Flash CRC Control register For Bank1 Register ,           Address offset: 0x50  */
+  __IO uint32_t CRCSADD1;        /*!< Flash CRC Start Address Register for Bank1 ,              Address offset: 0x54  */
+  __IO uint32_t CRCEADD1;        /*!< Flash CRC End Address Register for Bank1 ,                Address offset: 0x58  */
+  __IO uint32_t CRCDATA;         /*!< Flash CRC Data Register for Bank1 ,                       Address offset: 0x5C  */
+  __IO uint32_t ECC_FA1;         /*!< Flash ECC Fail Address For Bank1 Register ,               Address offset: 0x60  */
+  uint32_t      RESERVED1[40];   /*!< Reserved, 0x64 to 0x100                                                         */
+  __IO uint32_t KEYR2;           /*!< Flash Key Register for bank2,                             Address offset: 0x104 */
+  uint32_t      RESERVED2;       /*!< Reserved, 0x108                                                                 */
+  __IO uint32_t CR2;             /*!< Flash Control Register for bank2,                         Address offset: 0x10C */
+  __IO uint32_t SR2;             /*!< Flash Status Register for bank2,                          Address offset: 0x110 */
+  __IO uint32_t CCR2;            /*!< Flash Status Register for bank2,                          Address offset: 0x114 */
+  uint32_t      RESERVED3[4];    /*!< Reserved, 0x118 to 0x124                                                        */
+  __IO uint32_t PRAR_CUR2;       /*!< Flash Current Protection Address Register for bank2,      Address offset: 0x128 */
+  __IO uint32_t PRAR_PRG2;       /*!< Flash Protection Address to Program Register for bank2,   Address offset: 0x12C */
+  __IO uint32_t SCAR_CUR2;       /*!< Flash Current Secure Address Register for bank2,          Address offset: 0x130 */
+  __IO uint32_t SCAR_PRG2;       /*!< Flash Secure Address Register for bank2,                  Address offset: 0x134 */
+  __IO uint32_t WPSN_CUR2;       /*!< Flash Current Write Protection Register on bank2,         Address offset: 0x138 */
+  __IO uint32_t WPSN_PRG2;       /*!< Flash Write Protection to Program Register on bank2,      Address offset: 0x13C */
+  uint32_t      RESERVED4[4];    /*!< Reserved, 0x140 to 0x14C                                                        */
+  __IO uint32_t CRCCR2;          /*!< Flash CRC Control register For Bank2 Register ,           Address offset: 0x150 */
+  __IO uint32_t CRCSADD2;        /*!< Flash CRC Start Address Register for Bank2 ,              Address offset: 0x154 */
+  __IO uint32_t CRCEADD2;        /*!< Flash CRC End Address Register for Bank2 ,                Address offset: 0x158 */
+  __IO uint32_t CRCDATA2;        /*!< Flash CRC Data Register for Bank2 ,                       Address offset: 0x15C */
+  __IO uint32_t ECC_FA2;         /*!< Flash ECC Fail Address For Bank2 Register ,               Address offset: 0x160 */
+} FLASH_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FMC_Bank1_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank1E
+  */
+
+typedef struct
+{
+  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank2
+  */
+
+typedef struct
+{
+  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */
+  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */
+  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */
+  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
+  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */
+  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */
+} FMC_Bank2_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank3
+  */
+
+typedef struct
+{
+  __IO uint32_t PCR;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */
+  __IO uint32_t SR;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */
+  __IO uint32_t PMEM;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */
+  __IO uint32_t PATT;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
+  uint32_t      RESERVED;  /*!< Reserved, 0x90                                                            */
+  __IO uint32_t ECCR;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */
+} FMC_Bank3_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank5 and 6
+  */
+
+
+typedef struct
+{
+  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */
+  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */
+  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */
+  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */
+  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */
+} FMC_Bank5_6_TypeDef;
+
+/**
+  * @brief General Purpose I/O
+  */
+
+typedef struct
+{
+  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
+  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
+  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
+  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
+  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
+  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
+  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset,               Address offset: 0x18      */
+  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
+  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+  * @brief Operational Amplifier (OPAMP)
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;          /*!< OPAMP control/status register,                      Address offset: 0x00 */
+  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,     Address offset: 0x04 */
+  __IO uint32_t HSOTR;        /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */
+} OPAMP_TypeDef;
+
+/**
+  * @brief System configuration controller
+  */
+
+typedef struct
+{
+ uint32_t RESERVED1;           /*!< Reserved,                                           Address offset: 0x00        */
+ __IO uint32_t PMCR;           /*!< SYSCFG peripheral mode configuration register,      Address offset: 0x04        */
+ __IO uint32_t EXTICR[4];      /*!< SYSCFG external interrupt configuration registers,  Address offset: 0x08-0x14   */
+ __IO uint32_t CFGR;           /*!< SYSCFG configuration registers,                     Address offset: 0x18        */
+ uint32_t RESERVED2;           /*!< Reserved,                                           Address offset: 0x1C        */
+ __IO uint32_t CCCSR;          /*!< SYSCFG compensation cell control/status register,   Address offset: 0x20        */
+ __IO uint32_t CCVR;           /*!< SYSCFG compensation cell value register,            Address offset: 0x24        */
+ __IO uint32_t CCCR;           /*!< SYSCFG compensation cell code register,             Address offset: 0x28        */
+ __IO uint32_t PWRCR;          /*!< PWR control register,                               Address offset: 0x2C        */
+  uint32_t     RESERVED3[61];  /*!< Reserved, 0x30-0x120                                                            */
+  __IO uint32_t PKGR;          /*!< SYSCFG package register,                            Address offset: 0x124       */
+  uint32_t     RESERVED4[118]; /*!< Reserved, 0x128-0x2FC                                                           */
+ __IO uint32_t UR0;            /*!< SYSCFG user register 0,                             Address offset: 0x300       */
+ __IO uint32_t UR1;            /*!< SYSCFG user register 1,                             Address offset: 0x304       */
+ __IO uint32_t UR2;            /*!< SYSCFG user register 2,                             Address offset: 0x308       */
+ __IO uint32_t UR3;            /*!< SYSCFG user register 3,                             Address offset: 0x30C       */
+ __IO uint32_t UR4;            /*!< SYSCFG user register 4,                             Address offset: 0x310       */
+ __IO uint32_t UR5;            /*!< SYSCFG user register 5,                             Address offset: 0x314       */
+ __IO uint32_t UR6;            /*!< SYSCFG user register 6,                             Address offset: 0x318       */
+ __IO uint32_t UR7;            /*!< SYSCFG user register 7,                             Address offset: 0x31C       */
+ __IO uint32_t UR8;            /*!< SYSCFG user register 8,                             Address offset: 0x320       */
+ __IO uint32_t UR9;            /*!< SYSCFG user register 9,                             Address offset: 0x324       */
+ __IO uint32_t UR10;           /*!< SYSCFG user register 10,                            Address offset: 0x328       */
+ __IO uint32_t UR11;           /*!< SYSCFG user register 11,                            Address offset: 0x32C       */
+ __IO uint32_t UR12;           /*!< SYSCFG user register 12,                            Address offset: 0x330       */
+ __IO uint32_t UR13;           /*!< SYSCFG user register 13,                            Address offset: 0x334       */
+ __IO uint32_t UR14;           /*!< SYSCFG user register 14,                            Address offset: 0x338       */
+ __IO uint32_t UR15;           /*!< SYSCFG user register 15,                            Address offset: 0x33C       */
+ __IO uint32_t UR16;           /*!< SYSCFG user register 16,                            Address offset: 0x340       */
+ __IO uint32_t UR17;           /*!< SYSCFG user register 17,                            Address offset: 0x344       */
+
+} SYSCFG_TypeDef;
+
+/**
+  * @brief Inter-integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
+  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
+  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
+  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
+  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
+  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
+  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
+  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
+  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
+  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
+  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
+} I2C_TypeDef;
+
+/**
+  * @brief Independent WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
+  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
+} IWDG_TypeDef;
+
+
+/**
+  * @brief JPEG Codec
+  */
+typedef struct
+{
+  __IO uint32_t CONFR0;          /*!< JPEG Codec Control Register (JPEG_CONFR0),        Address offset: 00h       */
+  __IO uint32_t CONFR1;          /*!< JPEG Codec Control Register (JPEG_CONFR1),        Address offset: 04h       */
+  __IO uint32_t CONFR2;          /*!< JPEG Codec Control Register (JPEG_CONFR2),        Address offset: 08h       */
+  __IO uint32_t CONFR3;          /*!< JPEG Codec Control Register (JPEG_CONFR3),        Address offset: 0Ch       */
+  __IO uint32_t CONFR4;          /*!< JPEG Codec Control Register (JPEG_CONFR4),        Address offset: 10h       */
+  __IO uint32_t CONFR5;          /*!< JPEG Codec Control Register (JPEG_CONFR5),        Address offset: 14h       */
+  __IO uint32_t CONFR6;          /*!< JPEG Codec Control Register (JPEG_CONFR6),        Address offset: 18h       */
+  __IO uint32_t CONFR7;          /*!< JPEG Codec Control Register (JPEG_CONFR7),        Address offset: 1Ch       */
+  uint32_t  Reserved20[4];       /* Reserved                                            Address offset: 20h-2Ch   */
+  __IO uint32_t CR;              /*!< JPEG Control Register (JPEG_CR),                  Address offset: 30h       */
+  __IO uint32_t SR;              /*!< JPEG Status Register (JPEG_SR),                   Address offset: 34h       */
+  __IO uint32_t CFR;             /*!< JPEG Clear Flag Register (JPEG_CFR),              Address offset: 38h       */
+  uint32_t  Reserved3c;          /* Reserved                                            Address offset: 3Ch       */
+  __IO uint32_t DIR;             /*!< JPEG Data Input Register (JPEG_DIR),              Address offset: 40h       */
+  __IO uint32_t DOR;             /*!< JPEG Data Output Register (JPEG_DOR),             Address offset: 44h       */
+  uint32_t  Reserved48[2];       /* Reserved                                            Address offset: 48h-4Ch   */
+  __IO uint32_t QMEM0[16];       /*!< JPEG quantization tables 0,                       Address offset: 50h-8Ch   */
+  __IO uint32_t QMEM1[16];       /*!< JPEG quantization tables 1,                       Address offset: 90h-CCh   */
+  __IO uint32_t QMEM2[16];       /*!< JPEG quantization tables 2,                       Address offset: D0h-10Ch  */
+  __IO uint32_t QMEM3[16];       /*!< JPEG quantization tables 3,                       Address offset: 110h-14Ch */
+  __IO uint32_t HUFFMIN[16];     /*!< JPEG HuffMin tables,                              Address offset: 150h-18Ch */
+  __IO uint32_t HUFFBASE[32];    /*!< JPEG HuffSymb tables,                             Address offset: 190h-20Ch */
+  __IO uint32_t HUFFSYMB[84];    /*!< JPEG HUFFSYMB tables,                             Address offset: 210h-35Ch */
+  __IO uint32_t DHTMEM[103];     /*!< JPEG DHTMem tables,                               Address offset: 360h-4F8h */
+  uint32_t  Reserved4FC;         /* Reserved                                            Address offset: 4FCh      */
+  __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0,                 Address offset: 500h-65Ch */
+  __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1,                 Address offset: 660h-7BCh */
+  __IO uint32_t HUFFENC_DC0[8];  /*!< JPEG encodor, DC Huffman table 0,                 Address offset: 7C0h-7DCh */
+  __IO uint32_t HUFFENC_DC1[8];  /*!< JPEG encodor, DC Huffman table 1,                 Address offset: 7E0h-7FCh */
+
+} JPEG_TypeDef;
+
+/**
+  * @brief LCD-TFT Display Controller
+  */
+
+typedef struct
+{
+  uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04                                                       */
+  __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */
+  __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */
+  __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */
+  __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */
+  __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */
+  uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20                                                       */
+  __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */
+  uint32_t      RESERVED2[1];  /*!< Reserved, 0x28                                                            */
+  __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */
+  uint32_t      RESERVED3[1];  /*!< Reserved, 0x30                                                            */
+  __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */
+  __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */
+  __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */
+  __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
+  __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */
+  __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                 Address offset: 0x48 */
+} LTDC_TypeDef;
+
+/**
+  * @brief LCD-TFT Display layer x Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */
+  __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
+  __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */
+  __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */
+  __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */
+  __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */
+  __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */
+  __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */
+  uint32_t      RESERVED0[2];  /*!< Reserved */
+  __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */
+  __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */
+  __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */
+  uint32_t      RESERVED1[3];  /*!< Reserved */
+  __IO uint32_t CLUTWR;         /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */
+
+} LTDC_Layer_TypeDef;
+
+/**
+  * @brief Power Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;       /*!< PWR power control register 1,            Address offset: 0x00 */
+  __IO uint32_t CSR1;      /*!< PWR power control status register 1,     Address offset: 0x04 */
+  __IO uint32_t CR2;       /*!< PWR power control register 2,            Address offset: 0x08 */
+  __IO uint32_t CR3;       /*!< PWR power control register 3,            Address offset: 0x0C */
+  __IO uint32_t CPUCR;     /*!< PWR CPU control register,                Address offset: 0x10 */
+       uint32_t RESERVED0; /*!< Reserved,                                Address offset: 0x14 */
+  __IO uint32_t D3CR;      /*!< PWR D3 domain control register,          Address offset: 0x18 */
+       uint32_t RESERVED1; /*!< Reserved,                                Address offset: 0x1C */
+  __IO uint32_t WKUPCR;    /*!< PWR wakeup clear register,               Address offset: 0x20 */
+  __IO uint32_t WKUPFR;    /*!< PWR wakeup flag register,                Address offset: 0x24 */
+  __IO uint32_t WKUPEPR;   /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */
+} PWR_TypeDef;
+
+/**
+  * @brief Reset and Clock Control
+  */
+
+typedef struct
+{
+ __IO uint32_t CR;             /*!< RCC clock control register,                                              Address offset: 0x00  */
+ __IO uint32_t HSICFGR;        /*!< HSI Clock Calibration Register,                                          Address offset: 0x04  */
+ __IO uint32_t CRRCR;          /*!< Clock Recovery RC  Register,                                             Address offset: 0x08  */
+ __IO uint32_t CSICFGR;        /*!< CSI Clock Calibration Register,                                          Address offset: 0x0C  */
+ __IO uint32_t CFGR;           /*!< RCC clock configuration register,                                        Address offset: 0x10  */
+ uint32_t     RESERVED1;       /*!< Reserved,                                                                Address offset: 0x14  */
+ __IO uint32_t D1CFGR;         /*!< RCC Domain 1 configuration register,                                     Address offset: 0x18  */
+ __IO uint32_t D2CFGR;         /*!< RCC Domain 2 configuration register,                                     Address offset: 0x1C  */
+ __IO uint32_t D3CFGR;         /*!< RCC Domain 3 configuration register,                                     Address offset: 0x20  */
+ uint32_t     RESERVED2;       /*!< Reserved,                                                                Address offset: 0x24  */
+ __IO uint32_t PLLCKSELR;      /*!< RCC PLLs Clock Source Selection Register,                                Address offset: 0x28  */
+ __IO uint32_t PLLCFGR;        /*!< RCC PLLs  Configuration Register,                                        Address offset: 0x2C  */
+ __IO uint32_t PLL1DIVR;       /*!< RCC PLL1 Dividers Configuration Register,                                Address offset: 0x30  */
+ __IO uint32_t PLL1FRACR;      /*!< RCC PLL1 Fractional Divider Configuration Register,                      Address offset: 0x34  */
+ __IO uint32_t PLL2DIVR;       /*!< RCC PLL2 Dividers Configuration Register,                                Address offset: 0x38  */
+ __IO uint32_t PLL2FRACR;      /*!< RCC PLL2 Fractional Divider Configuration Register,                      Address offset: 0x3C  */
+ __IO uint32_t PLL3DIVR;       /*!< RCC PLL3 Dividers Configuration Register,                                Address offset: 0x40  */
+ __IO uint32_t PLL3FRACR;      /*!< RCC PLL3 Fractional Divider Configuration Register,                      Address offset: 0x44  */
+ uint32_t      RESERVED3;      /*!< Reserved,                                                                Address offset: 0x48  */
+ __IO uint32_t  D1CCIPR;       /*!< RCC Domain 1 Kernel Clock Configuration Register                         Address offset: 0x4C  */
+ __IO uint32_t  D2CCIP1R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x50  */
+ __IO uint32_t  D2CCIP2R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x54  */
+ __IO uint32_t  D3CCIPR;       /*!< RCC Domain 3 Kernel Clock Configuration Register                         Address offset: 0x58  */
+ uint32_t      RESERVED4;      /*!< Reserved,                                                                Address offset: 0x5C  */
+ __IO uint32_t  CIER;          /*!< RCC Clock Source Interrupt Enable Register                               Address offset: 0x60  */
+ __IO uint32_t  CIFR;          /*!< RCC Clock Source Interrupt Flag Register                                 Address offset: 0x64  */
+ __IO uint32_t  CICR;          /*!< RCC Clock Source Interrupt Clear Register                                Address offset: 0x68  */
+ uint32_t     RESERVED5;       /*!< Reserved,                                                                Address offset: 0x6C  */
+ __IO uint32_t  BDCR;          /*!< RCC Vswitch Backup Domain Control Register,                              Address offset: 0x70  */
+ __IO uint32_t  CSR;           /*!< RCC clock control & status register,                                     Address offset: 0x74  */
+ uint32_t     RESERVED6;       /*!< Reserved,                                                                Address offset: 0x78  */
+ __IO uint32_t AHB3RSTR;       /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x7C  */
+ __IO uint32_t AHB1RSTR;       /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x80  */
+ __IO uint32_t AHB2RSTR;       /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x84  */
+ __IO uint32_t AHB4RSTR;       /*!< RCC AHB4 peripheral reset register,                                      Address offset: 0x88  */
+ __IO uint32_t APB3RSTR;       /*!< RCC APB3 peripheral reset register,                                      Address offset: 0x8C  */
+ __IO uint32_t APB1LRSTR;      /*!< RCC APB1 peripheral reset Low Word register,                             Address offset: 0x90  */
+ __IO uint32_t APB1HRSTR;      /*!< RCC APB1 peripheral reset High Word register,                            Address offset: 0x94  */
+ __IO uint32_t APB2RSTR;       /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x98  */
+ __IO uint32_t APB4RSTR;       /*!< RCC APB4 peripheral reset register,                                      Address offset: 0x9C  */
+ __IO uint32_t GCR;            /*!< RCC RCC Global Control  Register,                                        Address offset: 0xA0  */
+ uint32_t     RESERVED8;       /*!< Reserved,                                                                Address offset: 0xA4  */
+ __IO uint32_t D3AMR;          /*!< RCC Domain 3 Autonomous Mode Register,                                   Address offset: 0xA8  */
+ uint32_t     RESERVED11[9];    /*!< Reserved, 0xAC-0xCC                                                      Address offset: 0xAC  */
+ __IO uint32_t RSR;            /*!< RCC Reset status register,                                               Address offset: 0xD0  */
+ __IO uint32_t AHB3ENR;        /*!< RCC AHB3 peripheral clock  register,                                     Address offset: 0xD4  */
+ __IO uint32_t AHB1ENR;        /*!< RCC AHB1 peripheral clock  register,                                     Address offset: 0xD8  */
+ __IO uint32_t AHB2ENR;        /*!< RCC AHB2 peripheral clock  register,                                     Address offset: 0xDC  */
+ __IO uint32_t AHB4ENR;        /*!< RCC AHB4 peripheral clock  register,                                     Address offset: 0xE0  */
+ __IO uint32_t APB3ENR;        /*!< RCC APB3 peripheral clock  register,                                     Address offset: 0xE4  */
+ __IO uint32_t APB1LENR;       /*!< RCC APB1 peripheral clock  Low Word register,                            Address offset: 0xE8  */
+ __IO uint32_t APB1HENR;       /*!< RCC APB1 peripheral clock  High Word register,                           Address offset: 0xEC  */
+ __IO uint32_t APB2ENR;        /*!< RCC APB2 peripheral clock  register,                                     Address offset: 0xF0  */
+ __IO uint32_t APB4ENR;        /*!< RCC APB4 peripheral clock  register,                                     Address offset: 0xF4  */
+ uint32_t      RESERVED12;      /*!< Reserved,                                                                Address offset: 0xF8  */
+ __IO uint32_t AHB3LPENR;      /*!< RCC AHB3 peripheral sleep clock  register,                               Address offset: 0xFC  */
+ __IO uint32_t AHB1LPENR;      /*!< RCC AHB1 peripheral sleep clock  register,                               Address offset: 0x100 */
+ __IO uint32_t AHB2LPENR;      /*!< RCC AHB2 peripheral sleep clock  register,                               Address offset: 0x104 */
+ __IO uint32_t AHB4LPENR;      /*!< RCC AHB4 peripheral sleep clock  register,                               Address offset: 0x108 */
+ __IO uint32_t APB3LPENR;      /*!< RCC APB3 peripheral sleep clock  register,                               Address offset: 0x10C */
+ __IO uint32_t APB1LLPENR;     /*!< RCC APB1 peripheral sleep clock  Low Word register,                      Address offset: 0x110 */
+ __IO uint32_t APB1HLPENR;     /*!< RCC APB1 peripheral sleep clock  High Word register,                     Address offset: 0x114 */
+ __IO uint32_t APB2LPENR;      /*!< RCC APB2 peripheral sleep clock  register,                               Address offset: 0x118 */
+ __IO uint32_t APB4LPENR;      /*!< RCC APB4 peripheral sleep clock  register,                               Address offset: 0x11C */
+ uint32_t     RESERVED13[4];   /*!< Reserved, 0x120-0x12C                                                    Address offset: 0x120 */
+
+} RCC_TypeDef;
+
+
+/**
+  * @brief Real-Time Clock
+  */
+typedef struct
+{
+  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
+  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
+  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
+  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
+  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
+  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
+       uint32_t RESERVED;   /*!< Reserved,                                                  Address offset: 0x18 */
+  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
+  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
+  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
+  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
+  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
+  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
+  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
+  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
+  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
+  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */
+  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
+  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
+  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset: 0x4C */
+  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
+  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
+  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
+  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
+  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
+  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */
+  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */
+  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */
+  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */
+  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
+  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */
+  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */
+  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */
+  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */
+  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */
+  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */
+  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */
+  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */
+  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */
+  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */
+  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */
+  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */
+  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */
+  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */
+  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */
+  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */
+  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */
+  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */
+  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */
+  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */
+  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */
+  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */
+} RTC_TypeDef;
+
+/**
+  * @brief Serial Audio Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t GCR;           /*!< SAI global configuration register, Address offset: 0x00 */
+  uint32_t      RESERVED0[16]; /*!< Reserved, 0x04 - 0x43                                   */
+  __IO uint32_t PDMCR;         /*!< SAI PDM control register,          Address offset: 0x44 */
+  __IO uint32_t PDMDLY;        /*!< SAI PDM delay register,            Address offset: 0x48 */
+} SAI_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */
+  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */
+  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */
+  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */
+  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
+  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */
+  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */
+  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+/**
+  * @brief SPDIF-RX Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t   CR;           /*!< Control register,                   Address offset: 0x00 */
+  __IO uint32_t   IMR;          /*!< Interrupt mask register,            Address offset: 0x04 */
+  __IO uint32_t   SR;           /*!< Status register,                    Address offset: 0x08 */
+  __IO uint32_t   IFCR;         /*!< Interrupt Flag Clear register,      Address offset: 0x0C */
+  __IO uint32_t   DR;           /*!< Data input register,                Address offset: 0x10 */
+  __IO uint32_t   CSR;          /*!< Channel Status register,            Address offset: 0x14 */
+  __IO uint32_t   DIR;          /*!< Debug Information register,         Address offset: 0x18 */
+  uint32_t        RESERVED2;    /*!< Reserved,  0x1A                                          */
+} SPDIFRX_TypeDef;
+
+
+/**
+  * @brief Secure digital input/output Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t POWER;          /*!< SDMMC power control register,             Address offset: 0x00  */
+  __IO uint32_t CLKCR;          /*!< SDMMC clock control register,             Address offset: 0x04  */
+  __IO uint32_t ARG;            /*!< SDMMC argument register,                  Address offset: 0x08  */
+  __IO uint32_t CMD;            /*!< SDMMC command register,                   Address offset: 0x0C  */
+  __I uint32_t  RESPCMD;        /*!< SDMMC command response register,          Address offset: 0x10  */
+  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,                Address offset: 0x14  */
+  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,                Address offset: 0x18  */
+  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,                Address offset: 0x1C  */
+  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,                Address offset: 0x20  */
+  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,                Address offset: 0x24  */
+  __IO uint32_t DLEN;           /*!< SDMMC data length register,               Address offset: 0x28  */
+  __IO uint32_t DCTRL;          /*!< SDMMC data control register,              Address offset: 0x2C  */
+  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,              Address offset: 0x30  */
+  __I uint32_t  STA;            /*!< SDMMC status register,                    Address offset: 0x34  */
+  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,           Address offset: 0x38  */
+  __IO uint32_t MASK;           /*!< SDMMC mask register,                      Address offset: 0x3C  */
+  __IO uint32_t ACKTIME;        /*!< SDMMC Acknowledgement timer register,     Address offset: 0x40  */
+  uint32_t      RESERVED0[3];   /*!< Reserved, 0x44 - 0x4C - 0x4C                                    */
+  __IO uint32_t IDMACTRL;       /*!< SDMMC DMA control register,               Address offset: 0x50  */
+  __IO uint32_t IDMABSIZE;      /*!< SDMMC DMA buffer size register,           Address offset: 0x54  */
+  __IO uint32_t IDMABASE0;      /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58  */
+  __IO uint32_t IDMABASE1;      /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C  */
+  uint32_t      RESERVED1[8];   /*!< Reserved, 0x60-0x7C                                             */
+  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,                 Address offset: 0x80  */
+  uint32_t      RESERVED2[222]; /*!< Reserved, 0x84-0x3F8                                            */
+  __IO uint32_t IPVR;           /*!< SDMMC data FIFO register,                 Address offset: 0x3FC */
+} SDMMC_TypeDef;
+
+
+/**
+  * @brief Delay Block DLYB
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< DELAY BLOCK control register,  Address offset: 0x00 */
+  __IO uint32_t CFGR;        /*!< DELAY BLOCK configuration register,  Address offset: 0x04 */
+} DLYB_TypeDef;
+
+/**
+  * @brief HW Semaphore HSEM
+  */
+
+typedef struct
+{
+  __IO uint32_t R[32];      /*!< 2-step write lock and read back registers,     Address offset: 00h-7Ch  */
+  __IO uint32_t RLR[32];    /*!< 1-step read lock registers,                    Address offset: 80h-FCh  */
+  __IO uint32_t C1IER;      /*!< HSEM Interrupt enable register ,             Address offset: 100h     */
+  __IO uint32_t C1ICR;      /*!< HSEM Interrupt clear register ,              Address offset: 104h     */
+  __IO uint32_t C1ISR;      /*!< HSEM Interrupt Status register ,             Address offset: 108h     */
+  __IO uint32_t C1MISR;     /*!< HSEM Interrupt Masked Status register ,      Address offset: 10Ch     */
+  uint32_t  Reserved[12];   /* Reserved                                       Address offset: 110h-13Ch  */
+  __IO uint32_t CR;         /*!< HSEM Semaphore clear register ,                Address offset: 140h      */
+  __IO uint32_t KEYR;       /*!< HSEM Semaphore clear key register ,            Address offset: 144h      */
+
+} HSEM_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t IER;        /*!< HSEM interrupt enable register ,                Address offset:   0h     */
+  __IO uint32_t ICR;        /*!< HSEM interrupt clear register ,                 Address offset:   4h     */
+  __IO uint32_t ISR;        /*!< HSEM interrupt status register ,                Address offset:   8h     */
+  __IO uint32_t MISR;       /*!< HSEM masked interrupt status register ,         Address offset:   Ch     */
+} HSEM_Common_TypeDef;
+
+/**
+  * @brief Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;           /*!< SPI/I2S Control register 1,                      Address offset: 0x00 */
+  __IO uint32_t CR2;           /*!< SPI Control register 2,                          Address offset: 0x04 */
+  __IO uint32_t CFG1;          /*!< SPI Configuration register 1,                    Address offset: 0x08 */
+  __IO uint32_t CFG2;          /*!< SPI Configuration register 2,                    Address offset: 0x0C */
+  __IO uint32_t IER;           /*!< SPI/I2S Interrupt Enable register,               Address offset: 0x10 */
+  __IO uint32_t SR;            /*!< SPI/I2S Status register,                         Address offset: 0x14 */
+  __IO uint32_t IFCR;          /*!< SPI/I2S Interrupt/Status flags clear register,   Address offset: 0x18 */
+  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                        */
+  __IO uint32_t TXDR;          /*!< SPI/I2S Transmit data register,                  Address offset: 0x20 */
+  uint32_t      RESERVED1[3];  /*!< Reserved, 0x24-0x2C                                                   */
+  __IO uint32_t RXDR;          /*!< SPI/I2S Receive data register,                   Address offset: 0x30 */
+  uint32_t      RESERVED2[3];  /*!< Reserved, 0x34-0x3C                                                   */
+  __IO uint32_t CRCPOLY;       /*!< SPI CRC Polynomial register,                     Address offset: 0x40 */
+  __IO uint32_t TXCRC;         /*!< SPI Transmitter CRC register,                    Address offset: 0x44 */
+  __IO uint32_t RXCRC;         /*!< SPI Receiver CRC register,                       Address offset: 0x48 */
+  __IO uint32_t UDRDR;         /*!< SPI Underrun data register,                      Address offset: 0x4C */
+  __IO uint32_t I2SCFGR;       /*!< I2S Configuration register,                      Address offset: 0x50 */
+
+} SPI_TypeDef;
+/**
+  * @brief QUAD Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< QUADSPI Control register,                           Address offset: 0x00 */
+  __IO uint32_t DCR;      /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */
+  __IO uint32_t SR;       /*!< QUADSPI Status register,                            Address offset: 0x08 */
+  __IO uint32_t FCR;      /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */
+  __IO uint32_t DLR;      /*!< QUADSPI Data Length register,                       Address offset: 0x10 */
+  __IO uint32_t CCR;      /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */
+  __IO uint32_t AR;       /*!< QUADSPI Address register,                           Address offset: 0x18 */
+  __IO uint32_t ABR;      /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */
+  __IO uint32_t DR;       /*!< QUADSPI Data register,                              Address offset: 0x20 */
+  __IO uint32_t PSMKR;    /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */
+  __IO uint32_t PSMAR;    /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */
+  __IO uint32_t PIR;      /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */
+  __IO uint32_t LPTR;     /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */
+} QUADSPI_TypeDef;
+
+/**
+  * @brief TIM
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */
+  __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */
+  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */
+  __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */
+  __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */
+  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */
+  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */
+  __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */
+  __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */
+  __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */
+  __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */
+  __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */
+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */
+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */
+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */
+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */
+  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */
+  __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */
+  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */
+  uint32_t      RESERVED1;   /*!< Reserved, 0x50                                                 */
+  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */
+  __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */
+  __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */
+  __IO uint32_t AF1;         /*!< TIM alternate function option register 1, Address offset: 0x60 */
+  __IO uint32_t AF2;         /*!< TIM alternate function option register 2, Address offset: 0x64 */
+  __IO uint32_t TISEL;       /*!< TIM Input Selection register,             Address offset: 0x68 */
+} TIM_TypeDef;
+
+/**
+  * @brief LPTIMIMER
+  */
+typedef struct
+{
+  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,         Address offset: 0x00 */
+  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,              Address offset: 0x04 */
+  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,             Address offset: 0x08 */
+  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                Address offset: 0x0C */
+  __IO uint32_t CR;       /*!< LPTIM Control register,                      Address offset: 0x10 */
+  __IO uint32_t CMP;      /*!< LPTIM Compare register,                      Address offset: 0x14 */
+  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                   Address offset: 0x18 */
+  __IO uint32_t CNT;      /*!< LPTIM Counter register,                      Address offset: 0x1C */
+  uint32_t  RESERVED1;    /*!< Reserved, 0x20                                                    */
+  __IO uint32_t CFGR2;    /*!< LPTIM Configuration register,                Address offset: 0x24 */
+} LPTIM_TypeDef;
+
+/**
+  * @brief Comparator
+  */
+typedef struct
+{
+  __IO uint32_t SR;        /*!< Comparator status register,                    Address offset: 0x00 */
+  __IO uint32_t ICFR;      /*!< Comparator interrupt clear flag register,       Address offset: 0x04 */
+  __IO uint32_t OR;        /*!< Comparator option register,                  Address offset: 0x08 */
+} COMPOPT_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CFGR;      /*!< Comparator configuration register  ,           Address offset: 0x00 */
+} COMP_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CFGR;       /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
+} COMP_Common_TypeDef;
+/**
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */
+  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */
+  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
+  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */
+  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
+  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */
+  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
+  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
+  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
+  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
+  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
+  __IO uint32_t PRESC;  /*!< USART clock Prescaler register,           Address offset: 0x2C */
+} USART_TypeDef;
+
+/**
+  * @brief Single Wire Protocol Master Interface SPWMI
+  */
+typedef struct
+{
+  __IO uint32_t CR;          /*!< SWPMI Configuration/Control register,     Address offset: 0x00 */
+  __IO uint32_t BRR;         /*!< SWPMI bitrate register,                   Address offset: 0x04 */
+    uint32_t  RESERVED1;     /*!< Reserved, 0x08                                                 */
+  __IO uint32_t ISR;         /*!< SWPMI Interrupt and Status register,      Address offset: 0x0C */
+  __IO uint32_t ICR;         /*!< SWPMI Interrupt Flag Clear register,      Address offset: 0x10 */
+  __IO uint32_t IER;         /*!< SWPMI Interrupt Enable register,          Address offset: 0x14 */
+  __IO uint32_t RFL;         /*!< SWPMI Receive Frame Length register,      Address offset: 0x18 */
+  __IO uint32_t TDR;         /*!< SWPMI Transmit data register,             Address offset: 0x1C */
+  __IO uint32_t RDR;         /*!< SWPMI Receive data register,              Address offset: 0x20 */
+  __IO uint32_t OR;          /*!< SWPMI Option register,                    Address offset: 0x24 */
+} SWPMI_TypeDef;
+
+/**
+  * @brief Window WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
+} WWDG_TypeDef;
+
+
+/**
+  * @brief RAM_ECC_Specific_Registers
+  */
+typedef struct
+{
+  __IO uint32_t CR;           /*!< RAMECC monitor configuration register          */
+  __IO uint32_t SR;           /*!< RAMECC monitor status register                 */
+  __IO uint32_t FAR;          /*!< RAMECC monitor failing address register        */
+  __IO uint32_t FDRL;         /*!< RAMECC monitor failing data low register       */
+  __IO uint32_t FDRH;         /*!< RAMECC monitor failing data high register      */
+  __IO uint32_t FECR;         /*!< RAMECC monitor failing ECC error code register */
+} RAMECC_MonitorTypeDef;
+
+typedef struct
+{
+  __IO uint32_t IER;          /*!< RAMECC interrupt enable register */
+} RAMECC_TypeDef;
+/**
+  * @}
+  */
+
+
+
+/**
+  * @brief High resolution Timer (HRTIM)
+  */
+/* HRTIM master registers definition */
+typedef struct
+{
+  __IO uint32_t MCR;            /*!< HRTIM Master Timer control register,                     Address offset: 0x00 */
+  __IO uint32_t MISR;           /*!< HRTIM Master Timer interrupt status register,            Address offset: 0x04 */
+  __IO uint32_t MICR;           /*!< HRTIM Master Timer interupt clear register,              Address offset: 0x08 */
+  __IO uint32_t MDIER;          /*!< HRTIM Master Timer DMA/interrupt enable register         Address offset: 0x0C */
+  __IO uint32_t MCNTR;          /*!< HRTIM Master Timer counter register,                     Address offset: 0x10 */
+  __IO uint32_t MPER;           /*!< HRTIM Master Timer period register,                      Address offset: 0x14 */
+  __IO uint32_t MREP;           /*!< HRTIM Master Timer repetition register,                  Address offset: 0x18 */
+  __IO uint32_t MCMP1R;         /*!< HRTIM Master Timer compare 1 register,                   Address offset: 0x1C */
+  uint32_t      RESERVED0;     /*!< Reserved,                                                                 0x20 */
+  __IO uint32_t MCMP2R;         /*!< HRTIM Master Timer compare 2 register,                   Address offset: 0x24 */
+  __IO uint32_t MCMP3R;         /*!< HRTIM Master Timer compare 3 register,                   Address offset: 0x28 */
+  __IO uint32_t MCMP4R;         /*!< HRTIM Master Timer compare 4 register,                   Address offset: 0x2C */
+  uint32_t      RESERVED1[20];  /*!< Reserved,                                                          0x30..0x7C */
+}HRTIM_Master_TypeDef;
+
+/* HRTIM Timer A to E registers definition */
+typedef struct
+{
+  __IO uint32_t TIMxCR;     /*!< HRTIM Timerx control register,                              Address offset: 0x00 */
+  __IO uint32_t TIMxISR;    /*!< HRTIM Timerx interrupt status register,                     Address offset: 0x04 */
+  __IO uint32_t TIMxICR;    /*!< HRTIM Timerx interrupt clear register,                      Address offset: 0x08 */
+  __IO uint32_t TIMxDIER;   /*!< HRTIM Timerx DMA/interrupt enable register,                 Address offset: 0x0C */
+  __IO uint32_t CNTxR;      /*!< HRTIM Timerx counter register,                              Address offset: 0x10 */
+  __IO uint32_t PERxR;      /*!< HRTIM Timerx period register,                               Address offset: 0x14 */
+  __IO uint32_t REPxR;      /*!< HRTIM Timerx repetition register,                           Address offset: 0x18 */
+  __IO uint32_t CMP1xR;     /*!< HRTIM Timerx compare 1 register,                            Address offset: 0x1C */
+  __IO uint32_t CMP1CxR;    /*!< HRTIM Timerx compare 1 compound register,                   Address offset: 0x20 */
+  __IO uint32_t CMP2xR;     /*!< HRTIM Timerx compare 2 register,                            Address offset: 0x24 */
+  __IO uint32_t CMP3xR;     /*!< HRTIM Timerx compare 3 register,                            Address offset: 0x28 */
+  __IO uint32_t CMP4xR;     /*!< HRTIM Timerx compare 4 register,                            Address offset: 0x2C */
+  __IO uint32_t CPT1xR;     /*!< HRTIM Timerx capture 1 register,                            Address offset: 0x30 */
+  __IO uint32_t CPT2xR;     /*!< HRTIM Timerx capture 2 register,                            Address offset: 0x34 */
+  __IO uint32_t DTxR;       /*!< HRTIM Timerx dead time register,                            Address offset: 0x38 */
+  __IO uint32_t SETx1R;     /*!< HRTIM Timerx output 1 set register,                         Address offset: 0x3C */
+  __IO uint32_t RSTx1R;     /*!< HRTIM Timerx output 1 reset register,                       Address offset: 0x40 */
+  __IO uint32_t SETx2R;     /*!< HRTIM Timerx output 2 set register,                         Address offset: 0x44 */
+  __IO uint32_t RSTx2R;     /*!< HRTIM Timerx output 2 reset register,                       Address offset: 0x48 */
+  __IO uint32_t EEFxR1;     /*!< HRTIM Timerx external event filtering 1 register,           Address offset: 0x4C */
+  __IO uint32_t EEFxR2;     /*!< HRTIM Timerx external event filtering 2 register,           Address offset: 0x50 */
+  __IO uint32_t RSTxR;      /*!< HRTIM Timerx Reset register,                                Address offset: 0x54 */
+  __IO uint32_t CHPxR;      /*!< HRTIM Timerx Chopper register,                              Address offset: 0x58 */
+  __IO uint32_t CPT1xCR;    /*!< HRTIM Timerx Capture 1 register,                            Address offset: 0x5C */
+  __IO uint32_t CPT2xCR;    /*!< HRTIM Timerx Capture 2 register,                            Address offset: 0x60 */
+  __IO uint32_t OUTxR;      /*!< HRTIM Timerx Output register,                               Address offset: 0x64 */
+  __IO uint32_t FLTxR;      /*!< HRTIM Timerx Fault register,                                Address offset: 0x68 */
+  uint32_t      RESERVED0[5];  /*!< Reserved,                                                          0x6C..0x7C */
+}HRTIM_Timerx_TypeDef;
+
+/* HRTIM common register definition */
+typedef struct
+{
+  __IO uint32_t CR1;        /*!< HRTIM control register1,                                    Address offset: 0x00 */
+  __IO uint32_t CR2;        /*!< HRTIM control register2,                                    Address offset: 0x04 */
+  __IO uint32_t ISR;        /*!< HRTIM interrupt status register,                            Address offset: 0x08 */
+  __IO uint32_t ICR;        /*!< HRTIM interrupt clear register,                             Address offset: 0x0C */
+  __IO uint32_t IER;        /*!< HRTIM interrupt enable register,                            Address offset: 0x10 */
+  __IO uint32_t OENR;       /*!< HRTIM Output enable register,                               Address offset: 0x14 */
+  __IO uint32_t ODISR;      /*!< HRTIM Output disable register,                              Address offset: 0x18 */
+  __IO uint32_t ODSR;       /*!< HRTIM Output disable status register,                       Address offset: 0x1C */
+  __IO uint32_t BMCR;       /*!< HRTIM Burst mode control register,                          Address offset: 0x20 */
+  __IO uint32_t BMTRGR;     /*!< HRTIM Busrt mode trigger register,                          Address offset: 0x24 */
+  __IO uint32_t BMCMPR;     /*!< HRTIM Burst mode compare register,                          Address offset: 0x28 */
+  __IO uint32_t BMPER;      /*!< HRTIM Burst mode period register,                           Address offset: 0x2C */
+  __IO uint32_t EECR1;      /*!< HRTIM Timer external event control register1,               Address offset: 0x30 */
+  __IO uint32_t EECR2;      /*!< HRTIM Timer external event control register2,               Address offset: 0x34 */
+  __IO uint32_t EECR3;      /*!< HRTIM Timer external event control register3,               Address offset: 0x38 */
+  __IO uint32_t ADC1R;      /*!< HRTIM ADC Trigger 1 register,                               Address offset: 0x3C */
+  __IO uint32_t ADC2R;      /*!< HRTIM ADC Trigger 2 register,                               Address offset: 0x40 */
+  __IO uint32_t ADC3R;      /*!< HRTIM ADC Trigger 3 register,                               Address offset: 0x44 */
+  __IO uint32_t ADC4R;      /*!< HRTIM ADC Trigger 4 register,                               Address offset: 0x48 */
+  __IO uint32_t RESERVED0;  /*!< Reserved,                                                   Address offset: 0x4C */
+  __IO uint32_t FLTINR1;    /*!< HRTIM Fault input register1,                                Address offset: 0x50 */
+  __IO uint32_t FLTINR2;    /*!< HRTIM Fault input register2,                                Address offset: 0x54 */
+  __IO uint32_t BDMUPR;     /*!< HRTIM Burst DMA Master Timer update register,               Address offset: 0x58 */
+  __IO uint32_t BDTAUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x5C */
+  __IO uint32_t BDTBUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x60 */
+  __IO uint32_t BDTCUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x64 */
+  __IO uint32_t BDTDUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x68 */
+  __IO uint32_t BDTEUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x6C */
+  __IO uint32_t BDMADR;     /*!< HRTIM Burst DMA Master Data register,                       Address offset: 0x70 */
+}HRTIM_Common_TypeDef;
+
+/* HRTIM  register definition */
+typedef struct {
+  HRTIM_Master_TypeDef sMasterRegs;
+  HRTIM_Timerx_TypeDef sTimerxRegs[5];
+  uint32_t             RESERVED0[32];
+  HRTIM_Common_TypeDef sCommonRegs;
+}HRTIM_TypeDef;
+/**
+  * @brief RNG
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
+} RNG_TypeDef;
+
+/**
+  * @brief MDIOS
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;
+  __IO uint32_t WRFR;
+  __IO uint32_t CWRFR;
+  __IO uint32_t RDFR;
+  __IO uint32_t CRDFR;
+  __IO uint32_t SR;
+  __IO uint32_t CLRFR;
+  uint32_t RESERVED[57];
+  __IO uint32_t DINR0;
+  __IO uint32_t DINR1;
+  __IO uint32_t DINR2;
+  __IO uint32_t DINR3;
+  __IO uint32_t DINR4;
+  __IO uint32_t DINR5;
+  __IO uint32_t DINR6;
+  __IO uint32_t DINR7;
+  __IO uint32_t DINR8;
+  __IO uint32_t DINR9;
+  __IO uint32_t DINR10;
+  __IO uint32_t DINR11;
+  __IO uint32_t DINR12;
+  __IO uint32_t DINR13;
+  __IO uint32_t DINR14;
+  __IO uint32_t DINR15;
+  __IO uint32_t DINR16;
+  __IO uint32_t DINR17;
+  __IO uint32_t DINR18;
+  __IO uint32_t DINR19;
+  __IO uint32_t DINR20;
+  __IO uint32_t DINR21;
+  __IO uint32_t DINR22;
+  __IO uint32_t DINR23;
+  __IO uint32_t DINR24;
+  __IO uint32_t DINR25;
+  __IO uint32_t DINR26;
+  __IO uint32_t DINR27;
+  __IO uint32_t DINR28;
+  __IO uint32_t DINR29;
+  __IO uint32_t DINR30;
+  __IO uint32_t DINR31;
+  __IO uint32_t DOUTR0;
+  __IO uint32_t DOUTR1;
+  __IO uint32_t DOUTR2;
+  __IO uint32_t DOUTR3;
+  __IO uint32_t DOUTR4;
+  __IO uint32_t DOUTR5;
+  __IO uint32_t DOUTR6;
+  __IO uint32_t DOUTR7;
+  __IO uint32_t DOUTR8;
+  __IO uint32_t DOUTR9;
+  __IO uint32_t DOUTR10;
+  __IO uint32_t DOUTR11;
+  __IO uint32_t DOUTR12;
+  __IO uint32_t DOUTR13;
+  __IO uint32_t DOUTR14;
+  __IO uint32_t DOUTR15;
+  __IO uint32_t DOUTR16;
+  __IO uint32_t DOUTR17;
+  __IO uint32_t DOUTR18;
+  __IO uint32_t DOUTR19;
+  __IO uint32_t DOUTR20;
+  __IO uint32_t DOUTR21;
+  __IO uint32_t DOUTR22;
+  __IO uint32_t DOUTR23;
+  __IO uint32_t DOUTR24;
+  __IO uint32_t DOUTR25;
+  __IO uint32_t DOUTR26;
+  __IO uint32_t DOUTR27;
+  __IO uint32_t DOUTR28;
+  __IO uint32_t DOUTR29;
+  __IO uint32_t DOUTR30;
+  __IO uint32_t DOUTR31;
+} MDIOS_TypeDef;
+
+
+/**
+  * @brief USB_OTG_Core_Registers
+  */
+typedef struct
+{
+ __IO uint32_t GOTGCTL;               /*!< USB_OTG Control and Status Register          000h */
+  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */
+  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */
+  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */
+  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */
+  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */
+  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */
+  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */
+  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */
+  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */
+  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */
+  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */
+  uint32_t Reserved30[2];             /*!< Reserved                                     030h */
+  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */
+  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */
+  __IO uint32_t GSNPSID;              /* USB_OTG core ID                                040h*/
+  __IO uint32_t GHWCFG1;              /* User HW config1                                044h*/
+  __IO uint32_t GHWCFG2;              /* User HW config2                                048h*/
+  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */
+  uint32_t  Reserved6;                /*!< Reserved                                     050h */
+  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */
+  __IO uint32_t GPWRDN;               /*!< Power Down Register                          058h */
+  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */
+   __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register       60Ch */
+    uint32_t  Reserved43[39];         /*!< Reserved                                058h-0FFh */
+  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */
+  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */
+} USB_OTG_GlobalTypeDef;
+
+
+/**
+  * @brief USB_OTG_device_Registers
+  */
+typedef struct
+{
+  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */
+  __IO uint32_t DCTL;            /*!< dev Control Register         804h */
+  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */
+  uint32_t Reserved0C;           /*!< Reserved                     80Ch */
+  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */
+  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */
+  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */
+  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */
+  uint32_t  Reserved20;          /*!< Reserved                     820h */
+  uint32_t Reserved9;            /*!< Reserved                     824h */
+  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */
+  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */
+  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */
+  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */
+  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */
+  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */
+  uint32_t Reserved40;           /*!< dedicated EP mask            840h */
+  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */
+  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */
+  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */
+} USB_OTG_DeviceTypeDef;
+
+
+/**
+  * @brief USB_OTG_IN_Endpoint-Specific_Register
+  */
+typedef struct
+{
+  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */
+  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */
+  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */
+  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */
+  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */
+  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */
+  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+
+/**
+  * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+  */
+typedef struct
+{
+  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */
+  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */
+  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */
+  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */
+  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */
+  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */
+  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
+} USB_OTG_OUTEndpointTypeDef;
+
+
+/**
+  * @brief USB_OTG_Host_Mode_Register_Structures
+  */
+typedef struct
+{
+  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */
+  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */
+  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */
+  uint32_t Reserved40C;           /*!< Reserved                             40Ch */
+  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */
+  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */
+  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */
+} USB_OTG_HostTypeDef;
+
+/**
+  * @brief USB_OTG_Host_Channel_Specific_Registers
+  */
+typedef struct
+{
+  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */
+  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */
+  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */
+  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */
+  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */
+  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */
+  uint32_t Reserved[2];           /*!< Reserved                                      */
+} USB_OTG_HostChannelTypeDef;
+/**
+  * @}
+  */
+
+
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+#define D1_ITCMRAM_BASE           (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM  */
+#define D1_ITCMICP_BASE           (0x00100000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM         */
+#define D1_DTCMRAM_BASE           (0x20000000UL) /*!< Base address of : 128KB system data RAM accessible over DTCM                            */
+#define D1_AXIFLASH_BASE          (0x08000000UL) /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI                */
+#define D1_AXIICP_BASE            (0x1FF00000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI          */
+#define D1_AXISRAM_BASE           (0x24000000UL) /*!< Base address of : (up to 512KB) system data RAM accessible over over AXI                */
+
+#define D2_AXISRAM_BASE           (0x10000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI                */
+#define D2_AHBSRAM_BASE           (0x30000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI->AHB Bridge    */
+
+#define D3_BKPSRAM_BASE           (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge                                */
+#define D3_SRAM_BASE              (0x38000000UL) /*!< Base address of : Backup SRAM(64 KB) over AXI->AHB Bridge                               */
+
+#define PERIPH_BASE               (0x40000000UL) /*!< Base address of : AHB/APB Peripherals                                                   */
+#define QSPI_BASE                 (0x90000000UL) /*!< Base address of : QSPI memories  accessible over AXI                                    */
+
+#define FLASH_BANK1_BASE          (0x08000000UL) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI                          */
+#define FLASH_BANK2_BASE          (0x08100000UL) /*!< Base address of : (up to 1 MB) Flash Bank2 accessible over AXI                          */
+#define FLASH_END                 (0x081FFFFFUL) /*!< FLASH end address                                                                       */
+
+/* Legacy define */
+#define FLASH_BASE                FLASH_BANK1_BASE
+
+/*!< Device electronic signature memory map */
+#define UID_BASE                  (0x1FF1E800UL)            /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE            (0x1FF1E880UL)            /*!< FLASH Size register base address */
+
+
+/*!< Peripheral memory map */
+#define D2_APB1PERIPH_BASE        PERIPH_BASE
+#define D2_APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
+#define D2_AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
+#define D2_AHB2PERIPH_BASE       (PERIPH_BASE + 0x08020000UL)
+
+#define D1_APB1PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)
+#define D1_AHB1PERIPH_BASE       (PERIPH_BASE + 0x12000000UL)
+
+#define D3_APB1PERIPH_BASE       (PERIPH_BASE + 0x18000000UL)
+#define D3_AHB1PERIPH_BASE       (PERIPH_BASE + 0x18020000UL)
+
+/*!< Legacy Peripheral memory map */
+#define APB1PERIPH_BASE        PERIPH_BASE
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000UL)
+
+
+/*!< D1_AHB1PERIPH peripherals */
+
+#define MDMA_BASE             (D1_AHB1PERIPH_BASE + 0x0000UL)
+#define DMA2D_BASE            (D1_AHB1PERIPH_BASE + 0x1000UL)
+#define JPGDEC_BASE           (D1_AHB1PERIPH_BASE + 0x3000UL)
+#define FLASH_R_BASE          (D1_AHB1PERIPH_BASE + 0x2000UL)
+#define FMC_R_BASE            (D1_AHB1PERIPH_BASE + 0x4000UL)
+#define QSPI_R_BASE           (D1_AHB1PERIPH_BASE + 0x5000UL)
+#define DLYB_QSPI_BASE        (D1_AHB1PERIPH_BASE + 0x6000UL)
+#define SDMMC1_BASE           (D1_AHB1PERIPH_BASE + 0x7000UL)
+#define DLYB_SDMMC1_BASE      (D1_AHB1PERIPH_BASE + 0x8000UL)
+#define RAMECC1_BASE          (D1_AHB1PERIPH_BASE + 0x9000UL)
+
+/*!< D2_AHB1PERIPH peripherals */
+
+#define DMA1_BASE               (D2_AHB1PERIPH_BASE + 0x0000UL)
+#define DMA2_BASE               (D2_AHB1PERIPH_BASE + 0x0400UL)
+#define DMAMUX1_BASE            (D2_AHB1PERIPH_BASE + 0x0800UL)
+#define ADC1_BASE               (D2_AHB1PERIPH_BASE + 0x2000UL)
+#define ADC2_BASE               (D2_AHB1PERIPH_BASE + 0x2100UL)
+#define ADC12_COMMON_BASE       (D2_AHB1PERIPH_BASE + 0x2300UL)
+#define ETH_BASE                (D2_AHB1PERIPH_BASE + 0x8000UL)
+#define ETH_MAC_BASE            (ETH_BASE)
+
+/*!< USB registers base address */
+#define USB1_OTG_HS_PERIPH_BASE              (0x40040000UL)
+#define USB2_OTG_FS_PERIPH_BASE              (0x40080000UL)
+#define USB_OTG_GLOBAL_BASE                  (0x000UL)
+#define USB_OTG_DEVICE_BASE                  (0x800UL)
+#define USB_OTG_IN_ENDPOINT_BASE             (0x900UL)
+#define USB_OTG_OUT_ENDPOINT_BASE            (0xB00UL)
+#define USB_OTG_EP_REG_SIZE                  (0x20UL)
+#define USB_OTG_HOST_BASE                    (0x400UL)
+#define USB_OTG_HOST_PORT_BASE               (0x440UL)
+#define USB_OTG_HOST_CHANNEL_BASE            (0x500UL)
+#define USB_OTG_HOST_CHANNEL_SIZE            (0x20UL)
+#define USB_OTG_PCGCCTL_BASE                 (0xE00UL)
+#define USB_OTG_FIFO_BASE                    (0x1000UL)
+#define USB_OTG_FIFO_SIZE                    (0x1000UL)
+
+/*!< D2_AHB2PERIPH peripherals */
+
+#define DCMI_BASE              (D2_AHB2PERIPH_BASE + 0x0000UL)
+#define RNG_BASE               (D2_AHB2PERIPH_BASE + 0x1800UL)
+#define SDMMC2_BASE            (D2_AHB2PERIPH_BASE + 0x2400UL)
+#define DLYB_SDMMC2_BASE       (D2_AHB2PERIPH_BASE + 0x2800UL)
+#define RAMECC2_BASE           (D2_AHB2PERIPH_BASE + 0x3000UL)
+
+/*!< D3_AHB1PERIPH peripherals */
+#define GPIOA_BASE            (D3_AHB1PERIPH_BASE + 0x0000UL)
+#define GPIOB_BASE            (D3_AHB1PERIPH_BASE + 0x0400UL)
+#define GPIOC_BASE            (D3_AHB1PERIPH_BASE + 0x0800UL)
+#define GPIOD_BASE            (D3_AHB1PERIPH_BASE + 0x0C00UL)
+#define GPIOE_BASE            (D3_AHB1PERIPH_BASE + 0x1000UL)
+#define GPIOF_BASE            (D3_AHB1PERIPH_BASE + 0x1400UL)
+#define GPIOG_BASE            (D3_AHB1PERIPH_BASE + 0x1800UL)
+#define GPIOH_BASE            (D3_AHB1PERIPH_BASE + 0x1C00UL)
+#define GPIOI_BASE            (D3_AHB1PERIPH_BASE + 0x2000UL)
+#define GPIOJ_BASE            (D3_AHB1PERIPH_BASE + 0x2400UL)
+#define GPIOK_BASE            (D3_AHB1PERIPH_BASE + 0x2800UL)
+#define RCC_BASE              (D3_AHB1PERIPH_BASE + 0x4400UL)
+#define PWR_BASE              (D3_AHB1PERIPH_BASE + 0x4800UL)
+#define CRC_BASE              (D3_AHB1PERIPH_BASE + 0x4C00UL)
+#define BDMA_BASE             (D3_AHB1PERIPH_BASE + 0x5400UL)
+#define DMAMUX2_BASE          (D3_AHB1PERIPH_BASE + 0x5800UL)
+#define ADC3_BASE             (D3_AHB1PERIPH_BASE + 0x6000UL)
+#define ADC3_COMMON_BASE      (D3_AHB1PERIPH_BASE + 0x6300UL)
+#define HSEM_BASE             (D3_AHB1PERIPH_BASE + 0x6400UL)
+#define RAMECC3_BASE          (D3_AHB1PERIPH_BASE + 0x7000UL)
+
+/*!< D1_APB1PERIPH peripherals */
+#define LTDC_BASE             (D1_APB1PERIPH_BASE + 0x1000UL)
+#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84UL)
+#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104UL)
+#define WWDG1_BASE            (D1_APB1PERIPH_BASE + 0x3000UL)
+
+/*!< D2_APB1PERIPH peripherals */
+#define TIM2_BASE             (D2_APB1PERIPH_BASE + 0x0000UL)
+#define TIM3_BASE             (D2_APB1PERIPH_BASE + 0x0400UL)
+#define TIM4_BASE             (D2_APB1PERIPH_BASE + 0x0800UL)
+#define TIM5_BASE             (D2_APB1PERIPH_BASE + 0x0C00UL)
+#define TIM6_BASE             (D2_APB1PERIPH_BASE + 0x1000UL)
+#define TIM7_BASE             (D2_APB1PERIPH_BASE + 0x1400UL)
+#define TIM12_BASE            (D2_APB1PERIPH_BASE + 0x1800UL)
+#define TIM13_BASE            (D2_APB1PERIPH_BASE + 0x1C00UL)
+#define TIM14_BASE            (D2_APB1PERIPH_BASE + 0x2000UL)
+#define LPTIM1_BASE           (D2_APB1PERIPH_BASE + 0x2400UL)
+
+
+#define SPI2_BASE             (D2_APB1PERIPH_BASE + 0x3800UL)
+#define SPI3_BASE             (D2_APB1PERIPH_BASE + 0x3C00UL)
+#define SPDIFRX_BASE          (D2_APB1PERIPH_BASE + 0x4000UL)
+#define USART2_BASE           (D2_APB1PERIPH_BASE + 0x4400UL)
+#define USART3_BASE           (D2_APB1PERIPH_BASE + 0x4800UL)
+#define UART4_BASE            (D2_APB1PERIPH_BASE + 0x4C00UL)
+#define UART5_BASE            (D2_APB1PERIPH_BASE + 0x5000UL)
+#define I2C1_BASE             (D2_APB1PERIPH_BASE + 0x5400UL)
+#define I2C2_BASE             (D2_APB1PERIPH_BASE + 0x5800UL)
+#define I2C3_BASE             (D2_APB1PERIPH_BASE + 0x5C00UL)
+#define CEC_BASE              (D2_APB1PERIPH_BASE + 0x6C00UL)
+#define DAC1_BASE             (D2_APB1PERIPH_BASE + 0x7400UL)
+#define UART7_BASE            (D2_APB1PERIPH_BASE + 0x7800UL)
+#define UART8_BASE            (D2_APB1PERIPH_BASE + 0x7C00UL)
+#define CRS_BASE              (D2_APB1PERIPH_BASE + 0x8400UL)
+#define SWPMI1_BASE           (D2_APB1PERIPH_BASE + 0x8800UL)
+#define OPAMP_BASE            (D2_APB1PERIPH_BASE + 0x9000UL)
+#define OPAMP1_BASE           (D2_APB1PERIPH_BASE + 0x9000UL)
+#define OPAMP2_BASE           (D2_APB1PERIPH_BASE + 0x9010UL)
+#define MDIOS_BASE            (D2_APB1PERIPH_BASE + 0x9400UL)
+#define FDCAN1_BASE           (D2_APB1PERIPH_BASE + 0xA000UL)
+#define FDCAN2_BASE           (D2_APB1PERIPH_BASE + 0xA400UL)
+#define FDCAN_CCU_BASE        (D2_APB1PERIPH_BASE + 0xA800UL)
+#define SRAMCAN_BASE          (D2_APB1PERIPH_BASE + 0xAC00UL)
+
+/*!< D2_APB2PERIPH peripherals */
+
+#define TIM1_BASE             (D2_APB2PERIPH_BASE + 0x0000UL)
+#define TIM8_BASE             (D2_APB2PERIPH_BASE + 0x0400UL)
+#define USART1_BASE           (D2_APB2PERIPH_BASE + 0x1000UL)
+#define USART6_BASE           (D2_APB2PERIPH_BASE + 0x1400UL)
+#define SPI1_BASE             (D2_APB2PERIPH_BASE + 0x3000UL)
+#define SPI4_BASE             (D2_APB2PERIPH_BASE + 0x3400UL)
+#define TIM15_BASE            (D2_APB2PERIPH_BASE + 0x4000UL)
+#define TIM16_BASE            (D2_APB2PERIPH_BASE + 0x4400UL)
+#define TIM17_BASE            (D2_APB2PERIPH_BASE + 0x4800UL)
+#define SPI5_BASE             (D2_APB2PERIPH_BASE + 0x5000UL)
+#define SAI1_BASE             (D2_APB2PERIPH_BASE + 0x5800UL)
+#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004UL)
+#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024UL)
+#define SAI2_BASE             (D2_APB2PERIPH_BASE + 0x5C00UL)
+#define SAI2_Block_A_BASE     (SAI2_BASE + 0x004UL)
+#define SAI2_Block_B_BASE     (SAI2_BASE + 0x024UL)
+#define SAI3_BASE             (D2_APB2PERIPH_BASE + 0x6000UL)
+#define SAI3_Block_A_BASE     (SAI3_BASE + 0x004UL)
+#define SAI3_Block_B_BASE     (SAI3_BASE + 0x024UL)
+#define DFSDM1_BASE           (D2_APB2PERIPH_BASE + 0x7000UL)
+#define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x00UL)
+#define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x20UL)
+#define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x40UL)
+#define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x60UL)
+#define DFSDM1_Channel4_BASE  (DFSDM1_BASE + 0x80UL)
+#define DFSDM1_Channel5_BASE  (DFSDM1_BASE + 0xA0UL)
+#define DFSDM1_Channel6_BASE  (DFSDM1_BASE + 0xC0UL)
+#define DFSDM1_Channel7_BASE  (DFSDM1_BASE + 0xE0UL)
+#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100UL)
+#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180UL)
+#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200UL)
+#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280UL)
+#define HRTIM1_BASE           (D2_APB2PERIPH_BASE + 0x7400UL)
+#define HRTIM1_TIMA_BASE      (HRTIM1_BASE + 0x00000080UL)
+#define HRTIM1_TIMB_BASE      (HRTIM1_BASE + 0x00000100UL)
+#define HRTIM1_TIMC_BASE      (HRTIM1_BASE + 0x00000180UL)
+#define HRTIM1_TIMD_BASE      (HRTIM1_BASE + 0x00000200UL)
+#define HRTIM1_TIME_BASE      (HRTIM1_BASE + 0x00000280UL)
+#define HRTIM1_COMMON_BASE    (HRTIM1_BASE + 0x00000380UL)
+
+
+/*!< D3_APB1PERIPH peripherals */
+#define EXTI_BASE             (D3_APB1PERIPH_BASE + 0x0000UL)
+#define EXTI_D1_BASE          (EXTI_BASE + 0x0080UL)
+#define EXTI_D2_BASE          (EXTI_BASE + 0x00C0UL)
+#define SYSCFG_BASE           (D3_APB1PERIPH_BASE + 0x0400UL)
+#define LPUART1_BASE          (D3_APB1PERIPH_BASE + 0x0C00UL)
+#define SPI6_BASE             (D3_APB1PERIPH_BASE + 0x1400UL)
+#define I2C4_BASE             (D3_APB1PERIPH_BASE + 0x1C00UL)
+#define LPTIM2_BASE           (D3_APB1PERIPH_BASE + 0x2400UL)
+#define LPTIM3_BASE           (D3_APB1PERIPH_BASE + 0x2800UL)
+#define LPTIM4_BASE           (D3_APB1PERIPH_BASE + 0x2C00UL)
+#define LPTIM5_BASE           (D3_APB1PERIPH_BASE + 0x3000UL)
+#define COMP12_BASE           (D3_APB1PERIPH_BASE + 0x3800UL)
+#define COMP1_BASE            (COMP12_BASE + 0x0CUL)
+#define COMP2_BASE            (COMP12_BASE + 0x10UL)
+#define VREFBUF_BASE          (D3_APB1PERIPH_BASE + 0x3C00UL)
+#define RTC_BASE              (D3_APB1PERIPH_BASE + 0x4000UL)
+#define IWDG1_BASE            (D3_APB1PERIPH_BASE + 0x4800UL)
+
+
+#define SAI4_BASE             (D3_APB1PERIPH_BASE + 0x5400UL)
+#define SAI4_Block_A_BASE     (SAI4_BASE + 0x004UL)
+#define SAI4_Block_B_BASE     (SAI4_BASE + 0x024UL)
+
+
+
+
+#define BDMA_Channel0_BASE    (BDMA_BASE + 0x0008UL)
+#define BDMA_Channel1_BASE    (BDMA_BASE + 0x001CUL)
+#define BDMA_Channel2_BASE    (BDMA_BASE + 0x0030UL)
+#define BDMA_Channel3_BASE    (BDMA_BASE + 0x0044UL)
+#define BDMA_Channel4_BASE    (BDMA_BASE + 0x0058UL)
+#define BDMA_Channel5_BASE    (BDMA_BASE + 0x006CUL)
+#define BDMA_Channel6_BASE    (BDMA_BASE + 0x0080UL)
+#define BDMA_Channel7_BASE    (BDMA_BASE + 0x0094UL)
+
+#define DMAMUX2_Channel0_BASE    (DMAMUX2_BASE)
+#define DMAMUX2_Channel1_BASE    (DMAMUX2_BASE + 0x0004UL)
+#define DMAMUX2_Channel2_BASE    (DMAMUX2_BASE + 0x0008UL)
+#define DMAMUX2_Channel3_BASE    (DMAMUX2_BASE + 0x000CUL)
+#define DMAMUX2_Channel4_BASE    (DMAMUX2_BASE + 0x0010UL)
+#define DMAMUX2_Channel5_BASE    (DMAMUX2_BASE + 0x0014UL)
+#define DMAMUX2_Channel6_BASE    (DMAMUX2_BASE + 0x0018UL)
+#define DMAMUX2_Channel7_BASE    (DMAMUX2_BASE + 0x001CUL)
+
+#define DMAMUX2_RequestGenerator0_BASE  (DMAMUX2_BASE + 0x0100UL)
+#define DMAMUX2_RequestGenerator1_BASE  (DMAMUX2_BASE + 0x0104UL)
+#define DMAMUX2_RequestGenerator2_BASE  (DMAMUX2_BASE + 0x0108UL)
+#define DMAMUX2_RequestGenerator3_BASE  (DMAMUX2_BASE + 0x010CUL)
+#define DMAMUX2_RequestGenerator4_BASE  (DMAMUX2_BASE + 0x0110UL)
+#define DMAMUX2_RequestGenerator5_BASE  (DMAMUX2_BASE + 0x0114UL)
+#define DMAMUX2_RequestGenerator6_BASE  (DMAMUX2_BASE + 0x0118UL)
+#define DMAMUX2_RequestGenerator7_BASE  (DMAMUX2_BASE + 0x011CUL)
+
+#define DMAMUX2_ChannelStatus_BASE      (DMAMUX2_BASE + 0x0080UL)
+#define DMAMUX2_RequestGenStatus_BASE   (DMAMUX2_BASE + 0x0140UL)
+
+#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)
+#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)
+#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)
+#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)
+#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)
+#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)
+#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)
+#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)
+
+#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)
+#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)
+#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)
+#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)
+#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)
+#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)
+#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)
+#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)
+
+#define DMAMUX1_Channel0_BASE    (DMAMUX1_BASE)
+#define DMAMUX1_Channel1_BASE    (DMAMUX1_BASE + 0x0004UL)
+#define DMAMUX1_Channel2_BASE    (DMAMUX1_BASE + 0x0008UL)
+#define DMAMUX1_Channel3_BASE    (DMAMUX1_BASE + 0x000CUL)
+#define DMAMUX1_Channel4_BASE    (DMAMUX1_BASE + 0x0010UL)
+#define DMAMUX1_Channel5_BASE    (DMAMUX1_BASE + 0x0014UL)
+#define DMAMUX1_Channel6_BASE    (DMAMUX1_BASE + 0x0018UL)
+#define DMAMUX1_Channel7_BASE    (DMAMUX1_BASE + 0x001CUL)
+#define DMAMUX1_Channel8_BASE    (DMAMUX1_BASE + 0x0020UL)
+#define DMAMUX1_Channel9_BASE    (DMAMUX1_BASE + 0x0024UL)
+#define DMAMUX1_Channel10_BASE   (DMAMUX1_BASE + 0x0028UL)
+#define DMAMUX1_Channel11_BASE   (DMAMUX1_BASE + 0x002CUL)
+#define DMAMUX1_Channel12_BASE   (DMAMUX1_BASE + 0x0030UL)
+#define DMAMUX1_Channel13_BASE   (DMAMUX1_BASE + 0x0034UL)
+#define DMAMUX1_Channel14_BASE   (DMAMUX1_BASE + 0x0038UL)
+#define DMAMUX1_Channel15_BASE   (DMAMUX1_BASE + 0x003CUL)
+
+#define DMAMUX1_RequestGenerator0_BASE  (DMAMUX1_BASE + 0x0100UL)
+#define DMAMUX1_RequestGenerator1_BASE  (DMAMUX1_BASE + 0x0104UL)
+#define DMAMUX1_RequestGenerator2_BASE  (DMAMUX1_BASE + 0x0108UL)
+#define DMAMUX1_RequestGenerator3_BASE  (DMAMUX1_BASE + 0x010CUL)
+#define DMAMUX1_RequestGenerator4_BASE  (DMAMUX1_BASE + 0x0110UL)
+#define DMAMUX1_RequestGenerator5_BASE  (DMAMUX1_BASE + 0x0114UL)
+#define DMAMUX1_RequestGenerator6_BASE  (DMAMUX1_BASE + 0x0118UL)
+#define DMAMUX1_RequestGenerator7_BASE  (DMAMUX1_BASE + 0x011CUL)
+
+#define DMAMUX1_ChannelStatus_BASE      (DMAMUX1_BASE + 0x0080UL)
+#define DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x0140UL)
+
+/*!< FMC Banks registers base  address */
+#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000UL)
+#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104UL)
+#define FMC_Bank2_R_BASE      (FMC_R_BASE + 0x0060UL)
+#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080UL)
+#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140UL)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE           (0x5C001000UL)
+
+#define MDMA_Channel0_BASE    (MDMA_BASE + 0x00000040UL)
+#define MDMA_Channel1_BASE    (MDMA_BASE + 0x00000080UL)
+#define MDMA_Channel2_BASE    (MDMA_BASE + 0x000000C0UL)
+#define MDMA_Channel3_BASE    (MDMA_BASE + 0x00000100UL)
+#define MDMA_Channel4_BASE    (MDMA_BASE + 0x00000140UL)
+#define MDMA_Channel5_BASE    (MDMA_BASE + 0x00000180UL)
+#define MDMA_Channel6_BASE    (MDMA_BASE + 0x000001C0UL)
+#define MDMA_Channel7_BASE    (MDMA_BASE + 0x00000200UL)
+#define MDMA_Channel8_BASE    (MDMA_BASE + 0x00000240UL)
+#define MDMA_Channel9_BASE    (MDMA_BASE + 0x00000280UL)
+#define MDMA_Channel10_BASE   (MDMA_BASE + 0x000002C0UL)
+#define MDMA_Channel11_BASE   (MDMA_BASE + 0x00000300UL)
+#define MDMA_Channel12_BASE   (MDMA_BASE + 0x00000340UL)
+#define MDMA_Channel13_BASE   (MDMA_BASE + 0x00000380UL)
+#define MDMA_Channel14_BASE   (MDMA_BASE + 0x000003C0UL)
+#define MDMA_Channel15_BASE   (MDMA_BASE + 0x00000400UL)
+
+#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL)
+#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL)
+#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL)
+#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL)
+#define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL)
+
+#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL)
+#define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL)
+#define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL)
+#define RAMECC2_Monitor4_BASE (RAMECC2_BASE + 0x80UL)
+#define RAMECC2_Monitor5_BASE (RAMECC2_BASE + 0xA0UL)
+
+#define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL)
+#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_declaration
+  * @{
+  */
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
+#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
+#define VREFBUF             ((VREFBUF_TypeDef *) VREFBUF_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG1               ((WWDG_TypeDef *) WWDG1_BASE)
+
+
+#define IWDG1               ((IWDG_TypeDef *) IWDG1_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
+#define SPI4                ((SPI_TypeDef *) SPI4_BASE)
+#define SPI5                ((SPI_TypeDef *) SPI5_BASE)
+#define SPI6                ((SPI_TypeDef *) SPI6_BASE)
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define USART3              ((USART_TypeDef *) USART3_BASE)
+#define USART6              ((USART_TypeDef *) USART6_BASE)
+#define UART7               ((USART_TypeDef *) UART7_BASE)
+#define UART8               ((USART_TypeDef *) UART8_BASE)
+#define CRS                 ((CRS_TypeDef *) CRS_BASE)
+#define UART4               ((USART_TypeDef *) UART4_BASE)
+#define UART5               ((USART_TypeDef *) UART5_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
+#define I2C4                ((I2C_TypeDef *) I2C4_BASE)
+#define FDCAN1              ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
+#define FDCAN2              ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
+#define FDCAN_CCU           ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)
+#define CEC                 ((CEC_TypeDef *) CEC_BASE)
+#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+#define DAC1                ((DAC_TypeDef *) DAC1_BASE)
+#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
+#define SWPMI1              ((SWPMI_TypeDef *) SWPMI1_BASE)
+#define LPTIM2              ((LPTIM_TypeDef *) LPTIM2_BASE)
+#define LPTIM3              ((LPTIM_TypeDef *) LPTIM3_BASE)
+#define LPTIM4              ((LPTIM_TypeDef *) LPTIM4_BASE)
+#define LPTIM5              ((LPTIM_TypeDef *) LPTIM5_BASE)
+
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define COMP12              ((COMPOPT_TypeDef *) COMP12_BASE)
+#define COMP1               ((COMP_TypeDef *) COMP1_BASE)
+#define COMP2               ((COMP_TypeDef *) COMP2_BASE)
+#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP2_BASE)
+#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
+#define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)
+#define OPAMP2              ((OPAMP_TypeDef *) OPAMP2_BASE)
+
+
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define EXTI_D1             ((EXTI_Core_TypeDef *) EXTI_D1_BASE)
+#define EXTI_D2             ((EXTI_Core_TypeDef *) EXTI_D2_BASE)
+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17               ((TIM_TypeDef *) TIM17_BASE)
+#define HRTIM1              ((HRTIM_TypeDef *) HRTIM1_BASE)
+#define HRTIM1_TIMA         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE)
+#define HRTIM1_TIMB         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE)
+#define HRTIM1_TIMC         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE)
+#define HRTIM1_TIMD         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE)
+#define HRTIM1_TIME         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE)
+#define HRTIM1_COMMON       ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)
+#define SAI1                ((SAI_TypeDef *) SAI1_BASE)
+#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
+#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+#define SAI2                ((SAI_TypeDef *) SAI2_BASE)
+#define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
+#define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
+#define SAI3                ((SAI_TypeDef *) SAI3_BASE)
+#define SAI3_Block_A        ((SAI_Block_TypeDef *)SAI3_Block_A_BASE)
+#define SAI3_Block_B        ((SAI_Block_TypeDef *)SAI3_Block_B_BASE)
+#define SAI4                ((SAI_TypeDef *) SAI4_BASE)
+#define SAI4_Block_A        ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)
+#define SAI4_Block_B        ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)
+
+#define SPDIFRX             ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
+#define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
+#define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
+#define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
+#define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
+#define DFSDM1_Channel4     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
+#define DFSDM1_Channel5     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
+#define DFSDM1_Channel6     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
+#define DFSDM1_Channel7     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
+#define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
+#define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
+#define DFSDM1_Filter2      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
+#define DFSDM1_Filter3      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
+#define DMA2D               ((DMA2D_TypeDef *) DMA2D_BASE)
+#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
+#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)
+#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)
+
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
+#define ADC3_COMMON         ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)
+#define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
+
+#define RNG                 ((RNG_TypeDef *) RNG_BASE)
+#define SDMMC2              ((SDMMC_TypeDef *) SDMMC2_BASE)
+#define DLYB_SDMMC2         ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)
+
+#define BDMA                ((BDMA_TypeDef *) BDMA_BASE)
+#define BDMA_Channel0       ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)
+#define BDMA_Channel1       ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)
+#define BDMA_Channel2       ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)
+#define BDMA_Channel3       ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)
+#define BDMA_Channel4       ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)
+#define BDMA_Channel5       ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)
+#define BDMA_Channel6       ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)
+#define BDMA_Channel7       ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)
+
+#define RAMECC1              ((RAMECC_TypeDef *)RAMECC1_BASE)
+#define RAMECC1_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)
+#define RAMECC1_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)
+#define RAMECC1_Monitor3     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)
+#define RAMECC1_Monitor4     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)
+#define RAMECC1_Monitor5     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)
+
+#define RAMECC2              ((RAMECC_TypeDef *)RAMECC2_BASE)
+#define RAMECC2_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)
+#define RAMECC2_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)
+#define RAMECC2_Monitor3     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)
+#define RAMECC2_Monitor4     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor4_BASE)
+#define RAMECC2_Monitor5     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor5_BASE)
+
+#define RAMECC3              ((RAMECC_TypeDef *)RAMECC3_BASE)
+#define RAMECC3_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)
+#define RAMECC3_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)
+
+#define DMAMUX2                ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)
+#define DMAMUX2_Channel0       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)
+#define DMAMUX2_Channel1       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)
+#define DMAMUX2_Channel2       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)
+#define DMAMUX2_Channel3       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)
+#define DMAMUX2_Channel4       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)
+#define DMAMUX2_Channel5       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)
+#define DMAMUX2_Channel6       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)
+#define DMAMUX2_Channel7       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)
+
+
+#define DMAMUX2_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)
+#define DMAMUX2_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)
+#define DMAMUX2_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)
+#define DMAMUX2_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)
+#define DMAMUX2_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)
+#define DMAMUX2_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)
+#define DMAMUX2_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)
+#define DMAMUX2_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)
+
+#define DMAMUX2_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)
+#define DMAMUX2_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)
+
+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+
+
+#define DMAMUX1              ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
+#define DMAMUX1_Channel0     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
+#define DMAMUX1_Channel1     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
+#define DMAMUX1_Channel2     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
+#define DMAMUX1_Channel3     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
+#define DMAMUX1_Channel4     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
+#define DMAMUX1_Channel5     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
+#define DMAMUX1_Channel6     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
+#define DMAMUX1_Channel7     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
+#define DMAMUX1_Channel8     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
+#define DMAMUX1_Channel9     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
+#define DMAMUX1_Channel10    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
+#define DMAMUX1_Channel11    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
+#define DMAMUX1_Channel12    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
+#define DMAMUX1_Channel13    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
+#define DMAMUX1_Channel14    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
+#define DMAMUX1_Channel15    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
+
+#define DMAMUX1_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
+#define DMAMUX1_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
+#define DMAMUX1_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
+#define DMAMUX1_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
+#define DMAMUX1_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)
+#define DMAMUX1_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)
+#define DMAMUX1_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)
+#define DMAMUX1_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)
+
+#define DMAMUX1_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *)    DMAMUX1_ChannelStatus_BASE)
+#define DMAMUX1_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
+
+
+#define FMC_Bank1_R           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
+#define FMC_Bank1E_R          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
+#define FMC_Bank2_R           ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)
+#define FMC_Bank3_R           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
+#define FMC_Bank5_6_R         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
+
+
+#define QUADSPI               ((QUADSPI_TypeDef *) QSPI_R_BASE)
+#define DLYB_QUADSPI          ((DLYB_TypeDef *) DLYB_QSPI_BASE)
+#define SDMMC1                ((SDMMC_TypeDef *) SDMMC1_BASE)
+#define DLYB_SDMMC1           ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)
+
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define JPEG                ((JPEG_TypeDef *) JPGDEC_BASE)
+#define HSEM                ((HSEM_TypeDef *) HSEM_BASE)
+#define HSEM_COMMON         ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))
+
+#define LTDC                ((LTDC_TypeDef *)LTDC_BASE)
+#define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
+#define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
+
+#define MDIOS               ((MDIOS_TypeDef *) MDIOS_BASE)
+
+#define ETH                 ((ETH_TypeDef *)ETH_BASE)
+#define MDMA                ((MDMA_TypeDef *)MDMA_BASE)
+#define MDMA_Channel0       ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)
+#define MDMA_Channel1       ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)
+#define MDMA_Channel2       ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)
+#define MDMA_Channel3       ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)
+#define MDMA_Channel4       ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)
+#define MDMA_Channel5       ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)
+#define MDMA_Channel6       ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)
+#define MDMA_Channel7       ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)
+#define MDMA_Channel8       ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)
+#define MDMA_Channel9       ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)
+#define MDMA_Channel10      ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)
+#define MDMA_Channel11      ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)
+#define MDMA_Channel12      ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)
+#define MDMA_Channel13      ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)
+#define MDMA_Channel14      ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)
+#define MDMA_Channel15      ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)
+
+
+#define USB1_OTG_HS         ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)
+#define USB2_OTG_FS         ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE)
+
+/* Legacy defines */
+#define USB_OTG_HS                   USB1_OTG_HS
+#define USB_OTG_HS_PERIPH_BASE       USB1_OTG_HS_PERIPH_BASE
+#define USB_OTG_FS                   USB2_OTG_FS
+#define USB_OTG_FS_PERIPH_BASE       USB2_OTG_FS_PERIPH_BASE
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+
+  /** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+
+/******************************************************************************/
+/*                         Peripheral Registers_Bits_Definition               */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Analog to Digital Converter                         */
+/*                                                                            */
+/******************************************************************************/
+/*******************************  ADC VERSION  ********************************/
+#define ADC_VER_V5_X
+/********************  Bit definition for ADC_ISR register  ********************/
+#define ADC_ISR_ADRDY_Pos                 (0U)
+#define ADC_ISR_ADRDY_Msk                 (0x1UL << ADC_ISR_ADRDY_Pos)         /*!< 0x00000001 */
+#define ADC_ISR_ADRDY                     ADC_ISR_ADRDY_Msk                    /*!< ADC Ready (ADRDY) flag  */
+#define ADC_ISR_EOSMP_Pos                 (1U)
+#define ADC_ISR_EOSMP_Msk                 (0x1UL << ADC_ISR_EOSMP_Pos)         /*!< 0x00000002 */
+#define ADC_ISR_EOSMP                     ADC_ISR_EOSMP_Msk                    /*!< ADC End of Sampling flag */
+#define ADC_ISR_EOC_Pos                   (2U)
+#define ADC_ISR_EOC_Msk                   (0x1UL << ADC_ISR_EOC_Pos)           /*!< 0x00000004 */
+#define ADC_ISR_EOC                       ADC_ISR_EOC_Msk                      /*!< ADC End of Regular Conversion flag */
+#define ADC_ISR_EOS_Pos                   (3U)
+#define ADC_ISR_EOS_Msk                   (0x1UL << ADC_ISR_EOS_Pos)           /*!< 0x00000008 */
+#define ADC_ISR_EOS                       ADC_ISR_EOS_Msk                      /*!< ADC End of Regular sequence of Conversions flag */
+#define ADC_ISR_OVR_Pos                   (4U)
+#define ADC_ISR_OVR_Msk                   (0x1UL << ADC_ISR_OVR_Pos)           /*!< 0x00000010 */
+#define ADC_ISR_OVR                       ADC_ISR_OVR_Msk                      /*!< ADC overrun flag */
+#define ADC_ISR_JEOC_Pos                  (5U)
+#define ADC_ISR_JEOC_Msk                  (0x1UL << ADC_ISR_JEOC_Pos)          /*!< 0x00000020 */
+#define ADC_ISR_JEOC                      ADC_ISR_JEOC_Msk                     /*!< ADC End of Injected Conversion flag */
+#define ADC_ISR_JEOS_Pos                  (6U)
+#define ADC_ISR_JEOS_Msk                  (0x1UL << ADC_ISR_JEOS_Pos)          /*!< 0x00000040 */
+#define ADC_ISR_JEOS                      ADC_ISR_JEOS_Msk                     /*!< ADC End of Injected sequence of Conversions flag */
+#define ADC_ISR_AWD1_Pos                  (7U)
+#define ADC_ISR_AWD1_Msk                  (0x1UL << ADC_ISR_AWD1_Pos)          /*!< 0x00000080 */
+#define ADC_ISR_AWD1                      ADC_ISR_AWD1_Msk                     /*!< ADC Analog watchdog 1 flag */
+#define ADC_ISR_AWD2_Pos                  (8U)
+#define ADC_ISR_AWD2_Msk                  (0x1UL << ADC_ISR_AWD2_Pos)          /*!< 0x00000100 */
+#define ADC_ISR_AWD2                      ADC_ISR_AWD2_Msk                     /*!< ADC Analog watchdog 2 flag */
+#define ADC_ISR_AWD3_Pos                  (9U)
+#define ADC_ISR_AWD3_Msk                  (0x1UL << ADC_ISR_AWD3_Pos)          /*!< 0x00000200 */
+#define ADC_ISR_AWD3                      ADC_ISR_AWD3_Msk                     /*!< ADC Analog watchdog 3 flag */
+#define ADC_ISR_JQOVF_Pos                 (10U)
+#define ADC_ISR_JQOVF_Msk                 (0x1UL << ADC_ISR_JQOVF_Pos)         /*!< 0x00000400 */
+#define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                    /*!< ADC Injected Context Queue Overflow flag */
+
+/********************  Bit definition for ADC_IER register  ********************/
+#define ADC_IER_ADRDYIE_Pos               (0U)
+#define ADC_IER_ADRDYIE_Msk               (0x1UL << ADC_IER_ADRDYIE_Pos)       /*!< 0x00000001 */
+#define ADC_IER_ADRDYIE                   ADC_IER_ADRDYIE_Msk                  /*!< ADC Ready (ADRDY) interrupt source */
+#define ADC_IER_EOSMPIE_Pos               (1U)
+#define ADC_IER_EOSMPIE_Msk               (0x1UL << ADC_IER_EOSMPIE_Pos)       /*!< 0x00000002 */
+#define ADC_IER_EOSMPIE                   ADC_IER_EOSMPIE_Msk                  /*!< ADC End of Sampling interrupt source */
+#define ADC_IER_EOCIE_Pos                 (2U)
+#define ADC_IER_EOCIE_Msk                 (0x1UL << ADC_IER_EOCIE_Pos)         /*!< 0x00000004 */
+#define ADC_IER_EOCIE                     ADC_IER_EOCIE_Msk                    /*!< ADC End of Regular Conversion interrupt source */
+#define ADC_IER_EOSIE_Pos                 (3U)
+#define ADC_IER_EOSIE_Msk                 (0x1UL << ADC_IER_EOSIE_Pos)         /*!< 0x00000008 */
+#define ADC_IER_EOSIE                     ADC_IER_EOSIE_Msk                    /*!< ADC End of Regular sequence of Conversions interrupt source */
+#define ADC_IER_OVRIE_Pos                 (4U)
+#define ADC_IER_OVRIE_Msk                 (0x1UL << ADC_IER_OVRIE_Pos)         /*!< 0x00000010 */
+#define ADC_IER_OVRIE                     ADC_IER_OVRIE_Msk                    /*!< ADC overrun interrupt source */
+#define ADC_IER_JEOCIE_Pos                (5U)
+#define ADC_IER_JEOCIE_Msk                (0x1UL << ADC_IER_JEOCIE_Pos)        /*!< 0x00000020 */
+#define ADC_IER_JEOCIE                    ADC_IER_JEOCIE_Msk                   /*!< ADC End of Injected Conversion interrupt source */
+#define ADC_IER_JEOSIE_Pos                (6U)
+#define ADC_IER_JEOSIE_Msk                (0x1UL << ADC_IER_JEOSIE_Pos)        /*!< 0x00000040 */
+#define ADC_IER_JEOSIE                    ADC_IER_JEOSIE_Msk                   /*!< ADC End of Injected sequence of Conversions interrupt source */
+#define ADC_IER_AWD1IE_Pos                (7U)
+#define ADC_IER_AWD1IE_Msk                (0x1UL << ADC_IER_AWD1IE_Pos)        /*!< 0x00000080 */
+#define ADC_IER_AWD1IE                    ADC_IER_AWD1IE_Msk                   /*!< ADC Analog watchdog 1 interrupt source */
+#define ADC_IER_AWD2IE_Pos                (8U)
+#define ADC_IER_AWD2IE_Msk                (0x1UL << ADC_IER_AWD2IE_Pos)        /*!< 0x00000100 */
+#define ADC_IER_AWD2IE                    ADC_IER_AWD2IE_Msk                   /*!< ADC Analog watchdog 2 interrupt source */
+#define ADC_IER_AWD3IE_Pos                (9U)
+#define ADC_IER_AWD3IE_Msk                (0x1UL << ADC_IER_AWD3IE_Pos)        /*!< 0x00000200 */
+#define ADC_IER_AWD3IE                    ADC_IER_AWD3IE_Msk                   /*!< ADC Analog watchdog 3 interrupt source */
+#define ADC_IER_JQOVFIE_Pos               (10U)
+#define ADC_IER_JQOVFIE_Msk               (0x1UL << ADC_IER_JQOVFIE_Pos)       /*!< 0x00000400 */
+#define ADC_IER_JQOVFIE                   ADC_IER_JQOVFIE_Msk                  /*!< ADC Injected Context Queue Overflow interrupt source */
+
+/********************  Bit definition for ADC_CR register  ********************/
+#define ADC_CR_ADEN_Pos                   (0U)
+#define ADC_CR_ADEN_Msk                   (0x1UL << ADC_CR_ADEN_Pos)           /*!< 0x00000001 */
+#define ADC_CR_ADEN                       ADC_CR_ADEN_Msk                      /*!< ADC Enable control */
+#define ADC_CR_ADDIS_Pos                  (1U)
+#define ADC_CR_ADDIS_Msk                  (0x1UL << ADC_CR_ADDIS_Pos)          /*!< 0x00000002 */
+#define ADC_CR_ADDIS                      ADC_CR_ADDIS_Msk                     /*!< ADC Disable command */
+#define ADC_CR_ADSTART_Pos                (2U)
+#define ADC_CR_ADSTART_Msk                (0x1UL << ADC_CR_ADSTART_Pos)        /*!< 0x00000004 */
+#define ADC_CR_ADSTART                    ADC_CR_ADSTART_Msk                   /*!< ADC Start of Regular conversion */
+#define ADC_CR_JADSTART_Pos               (3U)
+#define ADC_CR_JADSTART_Msk               (0x1UL << ADC_CR_JADSTART_Pos)       /*!< 0x00000008 */
+#define ADC_CR_JADSTART                   ADC_CR_JADSTART_Msk                  /*!< ADC Start of injected conversion */
+#define ADC_CR_ADSTP_Pos                  (4U)
+#define ADC_CR_ADSTP_Msk                  (0x1UL << ADC_CR_ADSTP_Pos)          /*!< 0x00000010 */
+#define ADC_CR_ADSTP                      ADC_CR_ADSTP_Msk                     /*!< ADC Stop of Regular conversion */
+#define ADC_CR_JADSTP_Pos                 (5U)
+#define ADC_CR_JADSTP_Msk                 (0x1UL << ADC_CR_JADSTP_Pos)         /*!< 0x00000020 */
+#define ADC_CR_JADSTP                     ADC_CR_JADSTP_Msk                    /*!< ADC Stop of injected conversion */
+#define ADC_CR_BOOST_Pos                  (8U)
+#define ADC_CR_BOOST_Msk                  (0x3UL << ADC_CR_BOOST_Pos)          /*!< 0x00000300 */
+#define ADC_CR_BOOST                      ADC_CR_BOOST_Msk                     /*!< ADC Boost Mode configuration */
+#define ADC_CR_BOOST_0                    (0x1UL << ADC_CR_BOOST_Pos)           /*!< 0x00000100 */
+#define ADC_CR_BOOST_1                    (0x2UL << ADC_CR_BOOST_Pos)           /*!< 0x00000200 */
+#define ADC_CR_ADCALLIN_Pos               (16U)
+#define ADC_CR_ADCALLIN_Msk               (0x1UL << ADC_CR_ADCALLIN_Pos)       /*!< 0x00010000 */
+#define ADC_CR_ADCALLIN                   ADC_CR_ADCALLIN_Msk                  /*!< ADC Linearity calibration */
+#define ADC_CR_LINCALRDYW1_Pos            (22U)
+#define ADC_CR_LINCALRDYW1_Msk            (0x1UL << ADC_CR_LINCALRDYW1_Pos)    /*!< 0x00400000 */
+#define ADC_CR_LINCALRDYW1                ADC_CR_LINCALRDYW1_Msk               /*!< ADC Linearity calibration ready Word 1 */
+#define ADC_CR_LINCALRDYW2_Pos            (23U)
+#define ADC_CR_LINCALRDYW2_Msk            (0x1UL << ADC_CR_LINCALRDYW2_Pos)    /*!< 0x00800000 */
+#define ADC_CR_LINCALRDYW2                ADC_CR_LINCALRDYW2_Msk               /*!< ADC Linearity calibration ready Word 2 */
+#define ADC_CR_LINCALRDYW3_Pos            (24U)
+#define ADC_CR_LINCALRDYW3_Msk            (0x1UL << ADC_CR_LINCALRDYW3_Pos)    /*!< 0x01000000 */
+#define ADC_CR_LINCALRDYW3                ADC_CR_LINCALRDYW3_Msk               /*!< ADC Linearity calibration ready Word 3 */
+#define ADC_CR_LINCALRDYW4_Pos            (25U)
+#define ADC_CR_LINCALRDYW4_Msk            (0x1UL << ADC_CR_LINCALRDYW4_Pos)    /*!< 0x02000000 */
+#define ADC_CR_LINCALRDYW4                ADC_CR_LINCALRDYW4_Msk               /*!< ADC Linearity calibration ready Word 4 */
+#define ADC_CR_LINCALRDYW5_Pos            (26U)
+#define ADC_CR_LINCALRDYW5_Msk            (0x1UL << ADC_CR_LINCALRDYW5_Pos)    /*!< 0x04000000 */
+#define ADC_CR_LINCALRDYW5                ADC_CR_LINCALRDYW5_Msk               /*!< ADC Linearity calibration ready Word 5 */
+#define ADC_CR_LINCALRDYW6_Pos            (27U)
+#define ADC_CR_LINCALRDYW6_Msk            (0x1UL << ADC_CR_LINCALRDYW6_Pos)    /*!< 0x08000000 */
+#define ADC_CR_LINCALRDYW6                ADC_CR_LINCALRDYW6_Msk               /*!< ADC Linearity calibration ready Word 6 */
+#define ADC_CR_ADVREGEN_Pos               (28U)
+#define ADC_CR_ADVREGEN_Msk               (0x1UL << ADC_CR_ADVREGEN_Pos)       /*!< 0x10000000 */
+#define ADC_CR_ADVREGEN                   ADC_CR_ADVREGEN_Msk                  /*!< ADC Voltage regulator Enable */
+#define ADC_CR_DEEPPWD_Pos                (29U)
+#define ADC_CR_DEEPPWD_Msk                (0x1UL << ADC_CR_DEEPPWD_Pos)        /*!< 0x20000000 */
+#define ADC_CR_DEEPPWD                    ADC_CR_DEEPPWD_Msk                   /*!< ADC Deep power down Enable */
+#define ADC_CR_ADCALDIF_Pos               (30U)
+#define ADC_CR_ADCALDIF_Msk               (0x1UL << ADC_CR_ADCALDIF_Pos)       /*!< 0x40000000 */
+#define ADC_CR_ADCALDIF                   ADC_CR_ADCALDIF_Msk                  /*!< ADC Differential Mode for calibration */
+#define ADC_CR_ADCAL_Pos                  (31U)
+#define ADC_CR_ADCAL_Msk                  (0x1UL << ADC_CR_ADCAL_Pos)          /*!< 0x80000000 */
+#define ADC_CR_ADCAL                      ADC_CR_ADCAL_Msk                     /*!< ADC Calibration */
+
+/********************  Bit definition for ADC_CFGR register  ********************/
+#define ADC_CFGR_DMNGT_Pos                (0U)
+#define ADC_CFGR_DMNGT_Msk                (0x3UL << ADC_CFGR_DMNGT_Pos)        /*!< 0x00000003 */
+#define ADC_CFGR_DMNGT                    ADC_CFGR_DMNGT_Msk                   /*!< ADC Data Management configuration */
+#define ADC_CFGR_DMNGT_0                  (0x1UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000001 */
+#define ADC_CFGR_DMNGT_1                  (0x2UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000002 */
+
+#define ADC_CFGR_RES_Pos                  (2U)
+#define ADC_CFGR_RES_Msk                  (0x7UL << ADC_CFGR_RES_Pos)          /*!< 0x0000001C */
+#define ADC_CFGR_RES                      ADC_CFGR_RES_Msk                     /*!< ADC Data resolution */
+#define ADC_CFGR_RES_0                    (0x1UL << ADC_CFGR_RES_Pos)           /*!< 0x00000004 */
+#define ADC_CFGR_RES_1                    (0x2UL << ADC_CFGR_RES_Pos)           /*!< 0x00000008 */
+#define ADC_CFGR_RES_2                    (0x4UL << ADC_CFGR_RES_Pos)           /*!< 0x00000010 */
+
+#define ADC_CFGR_EXTSEL_Pos               (5U)
+#define ADC_CFGR_EXTSEL_Msk               (0x1FUL << ADC_CFGR_EXTSEL_Pos)      /*!< 0x000003E0 */
+#define ADC_CFGR_EXTSEL                   ADC_CFGR_EXTSEL_Msk                  /*!< ADC External trigger selection for regular group */
+#define ADC_CFGR_EXTSEL_0                 (0x01UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000020 */
+#define ADC_CFGR_EXTSEL_1                 (0x02UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000040 */
+#define ADC_CFGR_EXTSEL_2                 (0x04UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000080 */
+#define ADC_CFGR_EXTSEL_3                 (0x08UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000100 */
+#define ADC_CFGR_EXTSEL_4                 (0x10UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000200 */
+
+#define ADC_CFGR_EXTEN_Pos                (10U)
+#define ADC_CFGR_EXTEN_Msk                (0x3UL << ADC_CFGR_EXTEN_Pos)        /*!< 0x00000C00 */
+#define ADC_CFGR_EXTEN                    ADC_CFGR_EXTEN_Msk                   /*!< ADC External trigger enable and polarity selection for regular channels */
+#define ADC_CFGR_EXTEN_0                  (0x1UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000400 */
+#define ADC_CFGR_EXTEN_1                  (0x2UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000800 */
+
+#define ADC_CFGR_OVRMOD_Pos               (12U)
+#define ADC_CFGR_OVRMOD_Msk               (0x1UL << ADC_CFGR_OVRMOD_Pos)       /*!< 0x00001000 */
+#define ADC_CFGR_OVRMOD                   ADC_CFGR_OVRMOD_Msk                  /*!< ADC overrun mode */
+#define ADC_CFGR_CONT_Pos                 (13U)
+#define ADC_CFGR_CONT_Msk                 (0x1UL << ADC_CFGR_CONT_Pos)         /*!< 0x00002000 */
+#define ADC_CFGR_CONT                     ADC_CFGR_CONT_Msk                    /*!< ADC Single/continuous conversion mode for regular conversion */
+#define ADC_CFGR_AUTDLY_Pos               (14U)
+#define ADC_CFGR_AUTDLY_Msk               (0x1UL << ADC_CFGR_AUTDLY_Pos)       /*!< 0x00004000 */
+#define ADC_CFGR_AUTDLY                   ADC_CFGR_AUTDLY_Msk                  /*!< ADC Delayed conversion mode */
+
+#define ADC_CFGR_DISCEN_Pos               (16U)
+#define ADC_CFGR_DISCEN_Msk               (0x1UL << ADC_CFGR_DISCEN_Pos)       /*!< 0x00010000 */
+#define ADC_CFGR_DISCEN                   ADC_CFGR_DISCEN_Msk                  /*!< ADC Discontinuous mode for regular channels */
+
+#define ADC_CFGR_DISCNUM_Pos              (17U)
+#define ADC_CFGR_DISCNUM_Msk              (0x7UL << ADC_CFGR_DISCNUM_Pos)      /*!< 0x000E0000 */
+#define ADC_CFGR_DISCNUM                  ADC_CFGR_DISCNUM_Msk                 /*!< ADC Discontinuous mode channel count */
+#define ADC_CFGR_DISCNUM_0                (0x1UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00020000 */
+#define ADC_CFGR_DISCNUM_1                (0x2UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00040000 */
+#define ADC_CFGR_DISCNUM_2                (0x4UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00080000 */
+
+#define ADC_CFGR_JDISCEN_Pos              (20U)
+#define ADC_CFGR_JDISCEN_Msk              (0x1UL << ADC_CFGR_JDISCEN_Pos)      /*!< 0x00100000 */
+#define ADC_CFGR_JDISCEN                  ADC_CFGR_JDISCEN_Msk                 /*!< ADC Discontinuous mode on injected channels */
+#define ADC_CFGR_JQM_Pos                  (21U)
+#define ADC_CFGR_JQM_Msk                  (0x1UL << ADC_CFGR_JQM_Pos)          /*!< 0x00200000 */
+#define ADC_CFGR_JQM                      ADC_CFGR_JQM_Msk                     /*!< ADC JSQR Queue mode */
+#define ADC_CFGR_AWD1SGL_Pos              (22U)
+#define ADC_CFGR_AWD1SGL_Msk              (0x1UL << ADC_CFGR_AWD1SGL_Pos)      /*!< 0x00400000 */
+#define ADC_CFGR_AWD1SGL                  ADC_CFGR_AWD1SGL_Msk                 /*!< Enable the watchdog 1 on a single channel or on all channels */
+#define ADC_CFGR_AWD1EN_Pos               (23U)
+#define ADC_CFGR_AWD1EN_Msk               (0x1UL << ADC_CFGR_AWD1EN_Pos)       /*!< 0x00800000 */
+#define ADC_CFGR_AWD1EN                   ADC_CFGR_AWD1EN_Msk                  /*!< ADC Analog watchdog 1 enable on regular Channels */
+#define ADC_CFGR_JAWD1EN_Pos              (24U)
+#define ADC_CFGR_JAWD1EN_Msk              (0x1UL << ADC_CFGR_JAWD1EN_Pos)      /*!< 0x01000000 */
+#define ADC_CFGR_JAWD1EN                  ADC_CFGR_JAWD1EN_Msk                 /*!< ADC Analog watchdog 1 enable on injected Channels */
+#define ADC_CFGR_JAUTO_Pos                (25U)
+#define ADC_CFGR_JAUTO_Msk                (0x1UL << ADC_CFGR_JAUTO_Pos)        /*!< 0x02000000 */
+#define ADC_CFGR_JAUTO                    ADC_CFGR_JAUTO_Msk                   /*!< ADC Automatic injected group conversion */
+
+#define ADC_CFGR_AWD1CH_Pos               (26U)
+#define ADC_CFGR_AWD1CH_Msk               (0x1FUL << ADC_CFGR_AWD1CH_Pos)      /*!< 0x7C000000 */
+#define ADC_CFGR_AWD1CH                   ADC_CFGR_AWD1CH_Msk                  /*!< ADC Analog watchdog 1 Channel selection */
+#define ADC_CFGR_AWD1CH_0                 (0x01UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x04000000 */
+#define ADC_CFGR_AWD1CH_1                 (0x02UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x08000000 */
+#define ADC_CFGR_AWD1CH_2                 (0x04UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x10000000 */
+#define ADC_CFGR_AWD1CH_3                 (0x08UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x20000000 */
+#define ADC_CFGR_AWD1CH_4                 (0x10UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x40000000 */
+
+#define ADC_CFGR_JQDIS_Pos                (31U)
+#define ADC_CFGR_JQDIS_Msk                (0x1UL << ADC_CFGR_JQDIS_Pos)        /*!< 0x80000000 */
+#define ADC_CFGR_JQDIS                    ADC_CFGR_JQDIS_Msk                   /*!< ADC Injected queue disable */
+
+/********************  Bit definition for ADC_CFGR2 register  ********************/
+#define ADC_CFGR2_ROVSE_Pos               (0U)
+#define ADC_CFGR2_ROVSE_Msk               (0x1UL << ADC_CFGR2_ROVSE_Pos)       /*!< 0x00000001 */
+#define ADC_CFGR2_ROVSE                   ADC_CFGR2_ROVSE_Msk                  /*!< ADC Regular group oversampler enable */
+#define ADC_CFGR2_JOVSE_Pos               (1U)
+#define ADC_CFGR2_JOVSE_Msk               (0x1UL << ADC_CFGR2_JOVSE_Pos)       /*!< 0x00000002 */
+#define ADC_CFGR2_JOVSE                   ADC_CFGR2_JOVSE_Msk                  /*!< ADC Injected group oversampler enable */
+
+#define ADC_CFGR2_OVSS_Pos                (5U)
+#define ADC_CFGR2_OVSS_Msk                (0xFUL << ADC_CFGR2_OVSS_Pos)        /*!< 0x000001E0 */
+#define ADC_CFGR2_OVSS                    ADC_CFGR2_OVSS_Msk                   /*!< ADC Regular Oversampling shift */
+#define ADC_CFGR2_OVSS_0                  (0x1UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000020 */
+#define ADC_CFGR2_OVSS_1                  (0x2UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000040 */
+#define ADC_CFGR2_OVSS_2                  (0x4UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000080 */
+#define ADC_CFGR2_OVSS_3                  (0x8UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000100 */
+
+#define ADC_CFGR2_TROVS_Pos               (9U)
+#define ADC_CFGR2_TROVS_Msk               (0x1UL << ADC_CFGR2_TROVS_Pos)       /*!< 0x00000200 */
+#define ADC_CFGR2_TROVS                   ADC_CFGR2_TROVS_Msk                  /*!< ADC Triggered regular Oversampling */
+#define ADC_CFGR2_ROVSM_Pos               (10U)
+#define ADC_CFGR2_ROVSM_Msk               (0x1UL << ADC_CFGR2_ROVSM_Pos)       /*!< 0x00000400 */
+#define ADC_CFGR2_ROVSM                   ADC_CFGR2_ROVSM_Msk                  /*!< ADC Regular oversampling mode */
+
+#define ADC_CFGR2_RSHIFT1_Pos             (11U)
+#define ADC_CFGR2_RSHIFT1_Msk             (0x1UL << ADC_CFGR2_RSHIFT1_Pos)     /*!< 0x00000800 */
+#define ADC_CFGR2_RSHIFT1                 ADC_CFGR2_RSHIFT1_Msk                /*!< ADC Right-shift data after Offset 1 correction */
+#define ADC_CFGR2_RSHIFT2_Pos             (12U)
+#define ADC_CFGR2_RSHIFT2_Msk             (0x1UL << ADC_CFGR2_RSHIFT2_Pos)     /*!< 0x00001000 */
+#define ADC_CFGR2_RSHIFT2                 ADC_CFGR2_RSHIFT2_Msk                /*!< ADC Right-shift data after Offset 2 correction */
+#define ADC_CFGR2_RSHIFT3_Pos             (13U)
+#define ADC_CFGR2_RSHIFT3_Msk             (0x1UL << ADC_CFGR2_RSHIFT3_Pos)     /*!< 0x00002000 */
+#define ADC_CFGR2_RSHIFT3                 ADC_CFGR2_RSHIFT3_Msk                /*!< ADC Right-shift data after Offset 3 correction */
+#define ADC_CFGR2_RSHIFT4_Pos             (14U)
+#define ADC_CFGR2_RSHIFT4_Msk             (0x1UL << ADC_CFGR2_RSHIFT4_Pos)     /*!< 0x00004000 */
+#define ADC_CFGR2_RSHIFT4                 ADC_CFGR2_RSHIFT4_Msk                /*!< ADC Right-shift data after Offset 4 correction */
+
+#define ADC_CFGR2_OVSR_Pos                (16U)
+#define ADC_CFGR2_OVSR_Msk                (0x3FFUL << ADC_CFGR2_OVSR_Pos)      /*!< 0x03FF0000 */
+#define ADC_CFGR2_OVSR                    ADC_CFGR2_OVSR_Msk                   /*!< ADC oversampling Ratio */
+#define ADC_CFGR2_OVSR_0                  (0x001UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00010000 */
+#define ADC_CFGR2_OVSR_1                  (0x002UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00020000 */
+#define ADC_CFGR2_OVSR_2                  (0x004UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00040000 */
+#define ADC_CFGR2_OVSR_3                  (0x008UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00080000 */
+#define ADC_CFGR2_OVSR_4                  (0x010UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00100000 */
+#define ADC_CFGR2_OVSR_5                  (0x020UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00200000 */
+#define ADC_CFGR2_OVSR_6                  (0x040UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00400000 */
+#define ADC_CFGR2_OVSR_7                  (0x080UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00800000 */
+#define ADC_CFGR2_OVSR_8                  (0x100UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x01000000 */
+#define ADC_CFGR2_OVSR_9                  (0x200UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x02000000 */
+
+#define ADC_CFGR2_LSHIFT_Pos              (28U)
+#define ADC_CFGR2_LSHIFT_Msk              (0xFUL << ADC_CFGR2_LSHIFT_Pos)      /*!< 0xF0000000 */
+#define ADC_CFGR2_LSHIFT                  ADC_CFGR2_LSHIFT_Msk                 /*!< ADC Left shift factor */
+#define ADC_CFGR2_LSHIFT_0                (0x1UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x10000000 */
+#define ADC_CFGR2_LSHIFT_1                (0x2UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x20000000 */
+#define ADC_CFGR2_LSHIFT_2                (0x4UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x40000000 */
+#define ADC_CFGR2_LSHIFT_3                (0x8UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_SMPR1 register  ********************/
+#define ADC_SMPR1_SMP0_Pos                (0U)
+#define ADC_SMPR1_SMP0_Msk                (0x7UL << ADC_SMPR1_SMP0_Pos)        /*!< 0x00000007 */
+#define ADC_SMPR1_SMP0                    ADC_SMPR1_SMP0_Msk                   /*!< ADC Channel 0 Sampling time selection  */
+#define ADC_SMPR1_SMP0_0                  (0x1UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000001 */
+#define ADC_SMPR1_SMP0_1                  (0x2UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000002 */
+#define ADC_SMPR1_SMP0_2                  (0x4UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000004 */
+
+#define ADC_SMPR1_SMP1_Pos                (3U)
+#define ADC_SMPR1_SMP1_Msk                (0x7UL << ADC_SMPR1_SMP1_Pos)        /*!< 0x00000038 */
+#define ADC_SMPR1_SMP1                    ADC_SMPR1_SMP1_Msk                   /*!< ADC Channel 1 Sampling time selection  */
+#define ADC_SMPR1_SMP1_0                  (0x1UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000008 */
+#define ADC_SMPR1_SMP1_1                  (0x2UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000010 */
+#define ADC_SMPR1_SMP1_2                  (0x4UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000020 */
+
+#define ADC_SMPR1_SMP2_Pos                (6U)
+#define ADC_SMPR1_SMP2_Msk                (0x7UL << ADC_SMPR1_SMP2_Pos)        /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP2                    ADC_SMPR1_SMP2_Msk                   /*!< ADC Channel 2 Sampling time selection  */
+#define ADC_SMPR1_SMP2_0                  (0x1UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000040 */
+#define ADC_SMPR1_SMP2_1                  (0x2UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000080 */
+#define ADC_SMPR1_SMP2_2                  (0x4UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000100 */
+
+#define ADC_SMPR1_SMP3_Pos                (9U)
+#define ADC_SMPR1_SMP3_Msk                (0x7UL << ADC_SMPR1_SMP3_Pos)        /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP3                    ADC_SMPR1_SMP3_Msk                   /*!< ADC Channel 3 Sampling time selection  */
+#define ADC_SMPR1_SMP3_0                  (0x1UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000200 */
+#define ADC_SMPR1_SMP3_1                  (0x2UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000400 */
+#define ADC_SMPR1_SMP3_2                  (0x4UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000800 */
+
+#define ADC_SMPR1_SMP4_Pos                (12U)
+#define ADC_SMPR1_SMP4_Msk                (0x7UL << ADC_SMPR1_SMP4_Pos)        /*!< 0x00007000 */
+#define ADC_SMPR1_SMP4                    ADC_SMPR1_SMP4_Msk                   /*!< ADC Channel 4 Sampling time selection  */
+#define ADC_SMPR1_SMP4_0                  (0x1UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00001000 */
+#define ADC_SMPR1_SMP4_1                  (0x2UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00002000 */
+#define ADC_SMPR1_SMP4_2                  (0x4UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00004000 */
+
+#define ADC_SMPR1_SMP5_Pos                (15U)
+#define ADC_SMPR1_SMP5_Msk                (0x7UL << ADC_SMPR1_SMP5_Pos)        /*!< 0x00038000 */
+#define ADC_SMPR1_SMP5                    ADC_SMPR1_SMP5_Msk                   /*!< ADC Channel 5 Sampling time selection  */
+#define ADC_SMPR1_SMP5_0                  (0x1UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00008000 */
+#define ADC_SMPR1_SMP5_1                  (0x2UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00010000 */
+#define ADC_SMPR1_SMP5_2                  (0x4UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00020000 */
+
+#define ADC_SMPR1_SMP6_Pos                (18U)
+#define ADC_SMPR1_SMP6_Msk                (0x7UL << ADC_SMPR1_SMP6_Pos)        /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP6                    ADC_SMPR1_SMP6_Msk                   /*!< ADC Channel 6 Sampling time selection  */
+#define ADC_SMPR1_SMP6_0                  (0x1UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00040000 */
+#define ADC_SMPR1_SMP6_1                  (0x2UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00080000 */
+#define ADC_SMPR1_SMP6_2                  (0x4UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00100000 */
+
+#define ADC_SMPR1_SMP7_Pos                (21U)
+#define ADC_SMPR1_SMP7_Msk                (0x7UL << ADC_SMPR1_SMP7_Pos)        /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP7                    ADC_SMPR1_SMP7_Msk                   /*!< ADC Channel 7 Sampling time selection  */
+#define ADC_SMPR1_SMP7_0                  (0x1UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00200000 */
+#define ADC_SMPR1_SMP7_1                  (0x2UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00400000 */
+#define ADC_SMPR1_SMP7_2                  (0x4UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00800000 */
+
+#define ADC_SMPR1_SMP8_Pos                (24U)
+#define ADC_SMPR1_SMP8_Msk                (0x7UL << ADC_SMPR1_SMP8_Pos)        /*!< 0x07000000 */
+#define ADC_SMPR1_SMP8                    ADC_SMPR1_SMP8_Msk                   /*!< ADC Channel 8 Sampling time selection  */
+#define ADC_SMPR1_SMP8_0                  (0x1UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x01000000 */
+#define ADC_SMPR1_SMP8_1                  (0x2UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x02000000 */
+#define ADC_SMPR1_SMP8_2                  (0x4UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x04000000 */
+
+#define ADC_SMPR1_SMP9_Pos                (27U)
+#define ADC_SMPR1_SMP9_Msk                (0x7UL << ADC_SMPR1_SMP9_Pos)        /*!< 0x38000000 */
+#define ADC_SMPR1_SMP9                    ADC_SMPR1_SMP9_Msk                   /*!< ADC Channel 9 Sampling time selection  */
+#define ADC_SMPR1_SMP9_0                  (0x1UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x08000000 */
+#define ADC_SMPR1_SMP9_1                  (0x2UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x10000000 */
+#define ADC_SMPR1_SMP9_2                  (0x4UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x20000000 */
+
+/********************  Bit definition for ADC_SMPR2 register  ********************/
+#define ADC_SMPR2_SMP10_Pos               (0U)
+#define ADC_SMPR2_SMP10_Msk               (0x7UL << ADC_SMPR2_SMP10_Pos)       /*!< 0x00000007 */
+#define ADC_SMPR2_SMP10                   ADC_SMPR2_SMP10_Msk                  /*!< ADC Channel 10 Sampling time selection  */
+#define ADC_SMPR2_SMP10_0                 (0x1UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000001 */
+#define ADC_SMPR2_SMP10_1                 (0x2UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000002 */
+#define ADC_SMPR2_SMP10_2                 (0x4UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000004 */
+
+#define ADC_SMPR2_SMP11_Pos               (3U)
+#define ADC_SMPR2_SMP11_Msk               (0x7UL << ADC_SMPR2_SMP11_Pos)       /*!< 0x00000038 */
+#define ADC_SMPR2_SMP11                   ADC_SMPR2_SMP11_Msk                  /*!< ADC Channel 11 Sampling time selection  */
+#define ADC_SMPR2_SMP11_0                 (0x1UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000008 */
+#define ADC_SMPR2_SMP11_1                 (0x2UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000010 */
+#define ADC_SMPR2_SMP11_2                 (0x4UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000020 */
+
+#define ADC_SMPR2_SMP12_Pos               (6U)
+#define ADC_SMPR2_SMP12_Msk               (0x7UL << ADC_SMPR2_SMP12_Pos)       /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP12                   ADC_SMPR2_SMP12_Msk                  /*!< ADC Channel 12 Sampling time selection  */
+#define ADC_SMPR2_SMP12_0                 (0x1UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000040 */
+#define ADC_SMPR2_SMP12_1                 (0x2UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000080 */
+#define ADC_SMPR2_SMP12_2                 (0x4UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000100 */
+
+#define ADC_SMPR2_SMP13_Pos               (9U)
+#define ADC_SMPR2_SMP13_Msk               (0x7UL << ADC_SMPR2_SMP13_Pos)       /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP13                   ADC_SMPR2_SMP13_Msk                  /*!< ADC Channel 13 Sampling time selection  */
+#define ADC_SMPR2_SMP13_0                 (0x1UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000200 */
+#define ADC_SMPR2_SMP13_1                 (0x2UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000400 */
+#define ADC_SMPR2_SMP13_2                 (0x4UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000800 */
+
+#define ADC_SMPR2_SMP14_Pos               (12U)
+#define ADC_SMPR2_SMP14_Msk               (0x7UL << ADC_SMPR2_SMP14_Pos)       /*!< 0x00007000 */
+#define ADC_SMPR2_SMP14                   ADC_SMPR2_SMP14_Msk                  /*!< ADC Channel 14 Sampling time selection  */
+#define ADC_SMPR2_SMP14_0                 (0x1UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00001000 */
+#define ADC_SMPR2_SMP14_1                 (0x2UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00002000 */
+#define ADC_SMPR2_SMP14_2                 (0x4UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00004000 */
+
+#define ADC_SMPR2_SMP15_Pos               (15U)
+#define ADC_SMPR2_SMP15_Msk               (0x7UL << ADC_SMPR2_SMP15_Pos)       /*!< 0x00038000 */
+#define ADC_SMPR2_SMP15                   ADC_SMPR2_SMP15_Msk                  /*!< ADC Channel 15 Sampling time selection  */
+#define ADC_SMPR2_SMP15_0                 (0x1UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00008000 */
+#define ADC_SMPR2_SMP15_1                 (0x2UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00010000 */
+#define ADC_SMPR2_SMP15_2                 (0x4UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00020000 */
+
+#define ADC_SMPR2_SMP16_Pos               (18U)
+#define ADC_SMPR2_SMP16_Msk               (0x7UL << ADC_SMPR2_SMP16_Pos)       /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP16                   ADC_SMPR2_SMP16_Msk                  /*!< ADC Channel 16 Sampling time selection  */
+#define ADC_SMPR2_SMP16_0                 (0x1UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00040000 */
+#define ADC_SMPR2_SMP16_1                 (0x2UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00080000 */
+#define ADC_SMPR2_SMP16_2                 (0x4UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00100000 */
+
+#define ADC_SMPR2_SMP17_Pos               (21U)
+#define ADC_SMPR2_SMP17_Msk               (0x7UL << ADC_SMPR2_SMP17_Pos)       /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP17                   ADC_SMPR2_SMP17_Msk                  /*!< ADC Channel 17 Sampling time selection  */
+#define ADC_SMPR2_SMP17_0                 (0x1UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00200000 */
+#define ADC_SMPR2_SMP17_1                 (0x2UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00400000 */
+#define ADC_SMPR2_SMP17_2                 (0x4UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00800000 */
+
+#define ADC_SMPR2_SMP18_Pos               (24U)
+#define ADC_SMPR2_SMP18_Msk               (0x7UL << ADC_SMPR2_SMP18_Pos)       /*!< 0x07000000 */
+#define ADC_SMPR2_SMP18                   ADC_SMPR2_SMP18_Msk                  /*!< ADC Channel 18 Sampling time selection  */
+#define ADC_SMPR2_SMP18_0                 (0x1UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x01000000 */
+#define ADC_SMPR2_SMP18_1                 (0x2UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x02000000 */
+#define ADC_SMPR2_SMP18_2                 (0x4UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x04000000 */
+
+#define ADC_SMPR2_SMP19_Pos               (27U)
+#define ADC_SMPR2_SMP19_Msk               (0x7UL << ADC_SMPR2_SMP19_Pos)       /*!< 0x38000000 */
+#define ADC_SMPR2_SMP19                   ADC_SMPR2_SMP19_Msk                  /*!< ADC Channel 19 Sampling time selection  */
+#define ADC_SMPR2_SMP19_0                 (0x1UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x08000000 */
+#define ADC_SMPR2_SMP19_1                 (0x2UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x10000000 */
+#define ADC_SMPR2_SMP19_2                 (0x4UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x20000000 */
+
+/********************  Bit definition for ADC_PCSEL register  ********************/
+#define ADC_PCSEL_PCSEL_Pos               (0U)
+#define ADC_PCSEL_PCSEL_Msk               (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos)   /*!< 0x000FFFFF */
+#define ADC_PCSEL_PCSEL                   ADC_PCSEL_PCSEL_Msk                  /*!< ADC pre channel selection */
+#define ADC_PCSEL_PCSEL_0                 (0x00001UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000001 */
+#define ADC_PCSEL_PCSEL_1                 (0x00002UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000002 */
+#define ADC_PCSEL_PCSEL_2                 (0x00004UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000004 */
+#define ADC_PCSEL_PCSEL_3                 (0x00008UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000008 */
+#define ADC_PCSEL_PCSEL_4                 (0x00010UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000010 */
+#define ADC_PCSEL_PCSEL_5                 (0x00020UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000020 */
+#define ADC_PCSEL_PCSEL_6                 (0x00040UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000040 */
+#define ADC_PCSEL_PCSEL_7                 (0x00080UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000080 */
+#define ADC_PCSEL_PCSEL_8                 (0x00100UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000100 */
+#define ADC_PCSEL_PCSEL_9                 (0x00200UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000200 */
+#define ADC_PCSEL_PCSEL_10                (0x00400UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000400 */
+#define ADC_PCSEL_PCSEL_11                (0x00800UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000800 */
+#define ADC_PCSEL_PCSEL_12                (0x01000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00001000 */
+#define ADC_PCSEL_PCSEL_13                (0x02000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00002000 */
+#define ADC_PCSEL_PCSEL_14                (0x04000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00004000 */
+#define ADC_PCSEL_PCSEL_15                (0x08000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00008000 */
+#define ADC_PCSEL_PCSEL_16                (0x10000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00010000 */
+#define ADC_PCSEL_PCSEL_17                (0x20000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00020000 */
+#define ADC_PCSEL_PCSEL_18                (0x40000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00040000 */
+#define ADC_PCSEL_PCSEL_19                (0x80000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00080000 */
+
+/*****************  Bit definition for ADC_LTR1, 2, 3 registers *****************/
+#define ADC_LTR_LT_Pos                    (0U)
+#define ADC_LTR_LT_Msk                    (0x3FFFFFFUL << ADC_LTR_LT_Pos)      /*!< 0x03FFFFFF */
+#define ADC_LTR_LT                        ADC_LTR_LT_Msk                       /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */
+
+/*****************  Bit definition for ADC_HTR1, 2, 3 registers  ****************/
+#define ADC_HTR_HT_Pos                    (0U)
+#define ADC_HTR_HT_Msk                    (0x3FFFFFFUL << ADC_HTR_HT_Pos)      /*!< 0x03FFFFFF */
+#define ADC_HTR_HT                        ADC_HTR_HT_Msk                       /*!< ADC Analog watchdog 1,2 and 3 higher threshold */
+
+
+/********************  Bit definition for ADC_SQR1 register  ********************/
+#define ADC_SQR1_L_Pos                    (0U)
+#define ADC_SQR1_L_Msk                    (0xFUL << ADC_SQR1_L_Pos)            /*!< 0x0000000F */
+#define ADC_SQR1_L                        ADC_SQR1_L_Msk                       /*!< ADC regular channel sequence lenght */
+#define ADC_SQR1_L_0                      (0x1UL << ADC_SQR1_L_Pos)             /*!< 0x00000001 */
+#define ADC_SQR1_L_1                      (0x2UL << ADC_SQR1_L_Pos)             /*!< 0x00000002 */
+#define ADC_SQR1_L_2                      (0x4UL << ADC_SQR1_L_Pos)             /*!< 0x00000004 */
+#define ADC_SQR1_L_3                      (0x8UL << ADC_SQR1_L_Pos)             /*!< 0x00000008 */
+
+#define ADC_SQR1_SQ1_Pos                  (6U)
+#define ADC_SQR1_SQ1_Msk                  (0x1FUL << ADC_SQR1_SQ1_Pos)         /*!< 0x000007C0 */
+#define ADC_SQR1_SQ1                      ADC_SQR1_SQ1_Msk                     /*!< ADC 1st conversion in regular sequence */
+#define ADC_SQR1_SQ1_0                    (0x01UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000040 */
+#define ADC_SQR1_SQ1_1                    (0x02UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000080 */
+#define ADC_SQR1_SQ1_2                    (0x04UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000100 */
+#define ADC_SQR1_SQ1_3                    (0x08UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000200 */
+#define ADC_SQR1_SQ1_4                    (0x10UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000400 */
+
+#define ADC_SQR1_SQ2_Pos                  (12U)
+#define ADC_SQR1_SQ2_Msk                  (0x1FUL << ADC_SQR1_SQ2_Pos)         /*!< 0x0001F000 */
+#define ADC_SQR1_SQ2                      ADC_SQR1_SQ2_Msk                     /*!< ADC 2nd conversion in regular sequence */
+#define ADC_SQR1_SQ2_0                    (0x01UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00001000 */
+#define ADC_SQR1_SQ2_1                    (0x02UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00002000 */
+#define ADC_SQR1_SQ2_2                    (0x04UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00004000 */
+#define ADC_SQR1_SQ2_3                    (0x08UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00008000 */
+#define ADC_SQR1_SQ2_4                    (0x10UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00010000 */
+
+#define ADC_SQR1_SQ3_Pos                  (18U)
+#define ADC_SQR1_SQ3_Msk                  (0x1FUL << ADC_SQR1_SQ3_Pos)         /*!< 0x007C0000 */
+#define ADC_SQR1_SQ3                      ADC_SQR1_SQ3_Msk                     /*!< ADC 3rd conversion in regular sequence */
+#define ADC_SQR1_SQ3_0                    (0x01UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00040000 */
+#define ADC_SQR1_SQ3_1                    (0x02UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00080000 */
+#define ADC_SQR1_SQ3_2                    (0x04UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00100000 */
+#define ADC_SQR1_SQ3_3                    (0x08UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00200000 */
+#define ADC_SQR1_SQ3_4                    (0x10UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00400000 */
+
+#define ADC_SQR1_SQ4_Pos                  (24U)
+#define ADC_SQR1_SQ4_Msk                  (0x1FUL << ADC_SQR1_SQ4_Pos)         /*!< 0x1F000000 */
+#define ADC_SQR1_SQ4                      ADC_SQR1_SQ4_Msk                     /*!< ADC 4th conversion in regular sequence */
+#define ADC_SQR1_SQ4_0                    (0x01UL << ADC_SQR1_SQ4_Pos)          /*!< 0x01000000 */
+#define ADC_SQR1_SQ4_1                    (0x02UL << ADC_SQR1_SQ4_Pos)          /*!< 0x02000000 */
+#define ADC_SQR1_SQ4_2                    (0x04UL << ADC_SQR1_SQ4_Pos)          /*!< 0x04000000 */
+#define ADC_SQR1_SQ4_3                    (0x08UL << ADC_SQR1_SQ4_Pos)          /*!< 0x08000000 */
+#define ADC_SQR1_SQ4_4                    (0x10UL << ADC_SQR1_SQ4_Pos)          /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR2 register  ********************/
+#define ADC_SQR2_SQ5_Pos                  (0U)
+#define ADC_SQR2_SQ5_Msk                  (0x1FUL << ADC_SQR2_SQ5_Pos)         /*!< 0x0000001F */
+#define ADC_SQR2_SQ5                      ADC_SQR2_SQ5_Msk                     /*!< ADC 5th conversion in regular sequence */
+#define ADC_SQR2_SQ5_0                    (0x01UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000001 */
+#define ADC_SQR2_SQ5_1                    (0x02UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000002 */
+#define ADC_SQR2_SQ5_2                    (0x04UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000004 */
+#define ADC_SQR2_SQ5_3                    (0x08UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000008 */
+#define ADC_SQR2_SQ5_4                    (0x10UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000010 */
+
+#define ADC_SQR2_SQ6_Pos                  (6U)
+#define ADC_SQR2_SQ6_Msk                  (0x1FUL << ADC_SQR2_SQ6_Pos)         /*!< 0x000007C0 */
+#define ADC_SQR2_SQ6                      ADC_SQR2_SQ6_Msk                     /*!< ADC 6th conversion in regular sequence */
+#define ADC_SQR2_SQ6_0                    (0x01UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000040 */
+#define ADC_SQR2_SQ6_1                    (0x02UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000080 */
+#define ADC_SQR2_SQ6_2                    (0x04UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000100 */
+#define ADC_SQR2_SQ6_3                    (0x08UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000200 */
+#define ADC_SQR2_SQ6_4                    (0x10UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000400 */
+
+#define ADC_SQR2_SQ7_Pos                  (12U)
+#define ADC_SQR2_SQ7_Msk                  (0x1FUL << ADC_SQR2_SQ7_Pos)         /*!< 0x0001F000 */
+#define ADC_SQR2_SQ7                      ADC_SQR2_SQ7_Msk                     /*!< ADC 7th conversion in regular sequence */
+#define ADC_SQR2_SQ7_0                    (0x01UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00001000 */
+#define ADC_SQR2_SQ7_1                    (0x02UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00002000 */
+#define ADC_SQR2_SQ7_2                    (0x04UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00004000 */
+#define ADC_SQR2_SQ7_3                    (0x08UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00008000 */
+#define ADC_SQR2_SQ7_4                    (0x10UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00010000 */
+
+#define ADC_SQR2_SQ8_Pos                  (18U)
+#define ADC_SQR2_SQ8_Msk                  (0x1FUL << ADC_SQR2_SQ8_Pos)         /*!< 0x007C0000 */
+#define ADC_SQR2_SQ8                      ADC_SQR2_SQ8_Msk                     /*!< ADC 8th conversion in regular sequence */
+#define ADC_SQR2_SQ8_0                    (0x01UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00040000 */
+#define ADC_SQR2_SQ8_1                    (0x02UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00080000 */
+#define ADC_SQR2_SQ8_2                    (0x04UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00100000 */
+#define ADC_SQR2_SQ8_3                    (0x08UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00200000 */
+#define ADC_SQR2_SQ8_4                    (0x10UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00400000 */
+
+#define ADC_SQR2_SQ9_Pos                  (24U)
+#define ADC_SQR2_SQ9_Msk                  (0x1FUL << ADC_SQR2_SQ9_Pos)         /*!< 0x1F000000 */
+#define ADC_SQR2_SQ9                      ADC_SQR2_SQ9_Msk                     /*!< ADC 9th conversion in regular sequence */
+#define ADC_SQR2_SQ9_0                    (0x01UL << ADC_SQR2_SQ9_Pos)          /*!< 0x01000000 */
+#define ADC_SQR2_SQ9_1                    (0x02UL << ADC_SQR2_SQ9_Pos)          /*!< 0x02000000 */
+#define ADC_SQR2_SQ9_2                    (0x04UL << ADC_SQR2_SQ9_Pos)          /*!< 0x04000000 */
+#define ADC_SQR2_SQ9_3                    (0x08UL << ADC_SQR2_SQ9_Pos)          /*!< 0x08000000 */
+#define ADC_SQR2_SQ9_4                    (0x10UL << ADC_SQR2_SQ9_Pos)          /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR3 register  ********************/
+#define ADC_SQR3_SQ10_Pos                 (0U)
+#define ADC_SQR3_SQ10_Msk                 (0x1FUL << ADC_SQR3_SQ10_Pos)        /*!< 0x0000001F */
+#define ADC_SQR3_SQ10                     ADC_SQR3_SQ10_Msk                    /*!< ADC 10th conversion in regular sequence */
+#define ADC_SQR3_SQ10_0                   (0x01UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000001 */
+#define ADC_SQR3_SQ10_1                   (0x02UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000002 */
+#define ADC_SQR3_SQ10_2                   (0x04UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000004 */
+#define ADC_SQR3_SQ10_3                   (0x08UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000008 */
+#define ADC_SQR3_SQ10_4                   (0x10UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000010 */
+
+#define ADC_SQR3_SQ11_Pos                 (6U)
+#define ADC_SQR3_SQ11_Msk                 (0x1FUL << ADC_SQR3_SQ11_Pos)        /*!< 0x000007C0 */
+#define ADC_SQR3_SQ11                     ADC_SQR3_SQ11_Msk                    /*!< ADC 11th conversion in regular sequence */
+#define ADC_SQR3_SQ11_0                   (0x01UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000040 */
+#define ADC_SQR3_SQ11_1                   (0x02UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000080 */
+#define ADC_SQR3_SQ11_2                   (0x04UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000100 */
+#define ADC_SQR3_SQ11_3                   (0x08UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000200 */
+#define ADC_SQR3_SQ11_4                   (0x10UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000400 */
+
+#define ADC_SQR3_SQ12_Pos                 (12U)
+#define ADC_SQR3_SQ12_Msk                 (0x1FUL << ADC_SQR3_SQ12_Pos)        /*!< 0x0001F000 */
+#define ADC_SQR3_SQ12                     ADC_SQR3_SQ12_Msk                    /*!< ADC 12th conversion in regular sequence */
+#define ADC_SQR3_SQ12_0                   (0x01UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00001000 */
+#define ADC_SQR3_SQ12_1                   (0x02UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00002000 */
+#define ADC_SQR3_SQ12_2                   (0x04UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00004000 */
+#define ADC_SQR3_SQ12_3                   (0x08UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00008000 */
+#define ADC_SQR3_SQ12_4                   (0x10UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00010000 */
+
+#define ADC_SQR3_SQ13_Pos                 (18U)
+#define ADC_SQR3_SQ13_Msk                 (0x1FUL << ADC_SQR3_SQ13_Pos)        /*!< 0x007C0000 */
+#define ADC_SQR3_SQ13                     ADC_SQR3_SQ13_Msk                    /*!< ADC 13th conversion in regular sequence */
+#define ADC_SQR3_SQ13_0                   (0x01UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00040000 */
+#define ADC_SQR3_SQ13_1                   (0x02UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00080000 */
+#define ADC_SQR3_SQ13_2                   (0x04UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00100000 */
+#define ADC_SQR3_SQ13_3                   (0x08UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00200000 */
+#define ADC_SQR3_SQ13_4                   (0x10UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00400000 */
+
+#define ADC_SQR3_SQ14_Pos                 (24U)
+#define ADC_SQR3_SQ14_Msk                 (0x1FUL << ADC_SQR3_SQ14_Pos)        /*!< 0x1F000000 */
+#define ADC_SQR3_SQ14                     ADC_SQR3_SQ14_Msk                    /*!< ADC 14th conversion in regular sequence */
+#define ADC_SQR3_SQ14_0                   (0x01UL << ADC_SQR3_SQ14_Pos)         /*!< 0x01000000 */
+#define ADC_SQR3_SQ14_1                   (0x02UL << ADC_SQR3_SQ14_Pos)         /*!< 0x02000000 */
+#define ADC_SQR3_SQ14_2                   (0x04UL << ADC_SQR3_SQ14_Pos)         /*!< 0x04000000 */
+#define ADC_SQR3_SQ14_3                   (0x08UL << ADC_SQR3_SQ14_Pos)         /*!< 0x08000000 */
+#define ADC_SQR3_SQ14_4                   (0x10UL << ADC_SQR3_SQ14_Pos)         /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR4 register  ********************/
+#define ADC_SQR4_SQ15_Pos                 (0U)
+#define ADC_SQR4_SQ15_Msk                 (0x1FUL << ADC_SQR4_SQ15_Pos)        /*!< 0x0000001F */
+#define ADC_SQR4_SQ15                     ADC_SQR4_SQ15_Msk                    /*!< ADC 15th conversion in regular sequence */
+#define ADC_SQR4_SQ15_0                   (0x01UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000001 */
+#define ADC_SQR4_SQ15_1                   (0x02UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000002 */
+#define ADC_SQR4_SQ15_2                   (0x04UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000004 */
+#define ADC_SQR4_SQ15_3                   (0x08UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000008 */
+#define ADC_SQR4_SQ15_4                   (0x10UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000010 */
+
+#define ADC_SQR4_SQ16_Pos                 (6U)
+#define ADC_SQR4_SQ16_Msk                 (0x1FUL << ADC_SQR4_SQ16_Pos)        /*!< 0x000007C0 */
+#define ADC_SQR4_SQ16                     ADC_SQR4_SQ16_Msk                    /*!< ADC 16th conversion in regular sequence */
+#define ADC_SQR4_SQ16_0                   (0x01UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000040 */
+#define ADC_SQR4_SQ16_1                   (0x02UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000080 */
+#define ADC_SQR4_SQ16_2                   (0x04UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000100 */
+#define ADC_SQR4_SQ16_3                   (0x08UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000200 */
+#define ADC_SQR4_SQ16_4                   (0x10UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000400 */
+/********************  Bit definition for ADC_DR register  ********************/
+#define ADC_DR_RDATA_Pos                  (0U)
+#define ADC_DR_RDATA_Msk                  (0xFFFFFFFFUL << ADC_DR_RDATA_Pos)   /*!< 0xFFFFFFFF */
+#define ADC_DR_RDATA                      ADC_DR_RDATA_Msk                     /*!< ADC regular Data converted */
+
+/********************  Bit definition for ADC_JSQR register  ********************/
+#define ADC_JSQR_JL_Pos                   (0U)
+#define ADC_JSQR_JL_Msk                   (0x3UL << ADC_JSQR_JL_Pos)           /*!< 0x00000003 */
+#define ADC_JSQR_JL                       ADC_JSQR_JL_Msk                      /*!< ADC injected channel sequence length */
+#define ADC_JSQR_JL_0                     (0x1UL << ADC_JSQR_JL_Pos)           /*!< 0x00000001 */
+#define ADC_JSQR_JL_1                     (0x2UL << ADC_JSQR_JL_Pos)           /*!< 0x00000002 */
+
+#define ADC_JSQR_JEXTSEL_Pos              (2U)
+#define ADC_JSQR_JEXTSEL_Msk              (0x1FUL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x0000007C */
+#define ADC_JSQR_JEXTSEL                  ADC_JSQR_JEXTSEL_Msk                 /*!< ADC external trigger selection for injected group */
+#define ADC_JSQR_JEXTSEL_0                (0x01UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000004 */
+#define ADC_JSQR_JEXTSEL_1                (0x02UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000008 */
+#define ADC_JSQR_JEXTSEL_2                (0x04UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000010 */
+#define ADC_JSQR_JEXTSEL_3                (0x08UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000020 */
+#define ADC_JSQR_JEXTSEL_4                (0x10UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000040 */
+
+#define ADC_JSQR_JEXTEN_Pos               (7U)
+#define ADC_JSQR_JEXTEN_Msk               (0x3UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000180 */
+#define ADC_JSQR_JEXTEN                   ADC_JSQR_JEXTEN_Msk                  /*!< ADC external trigger enable and polarity selection for injected channels */
+#define ADC_JSQR_JEXTEN_0                 (0x1UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000080 */
+#define ADC_JSQR_JEXTEN_1                 (0x2UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000100 */
+
+#define ADC_JSQR_JSQ1_Pos                 (9U)
+#define ADC_JSQR_JSQ1_Msk                 (0x1FUL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00003E00 */
+#define ADC_JSQR_JSQ1                     ADC_JSQR_JSQ1_Msk                    /*!< ADC 1st conversion in injected sequence */
+#define ADC_JSQR_JSQ1_0                   (0x01UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000200 */
+#define ADC_JSQR_JSQ1_1                   (0x02UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000400 */
+#define ADC_JSQR_JSQ1_2                   (0x04UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000800 */
+#define ADC_JSQR_JSQ1_3                   (0x08UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00001000 */
+#define ADC_JSQR_JSQ1_4                   (0x10UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00002000 */
+
+#define ADC_JSQR_JSQ2_Pos                 (15U)
+#define ADC_JSQR_JSQ2_Msk                 (0x1FUL << ADC_JSQR_JSQ2_Pos)        /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ2                     ADC_JSQR_JSQ2_Msk                    /*!< ADC 2nd conversion in injected sequence */
+#define ADC_JSQR_JSQ2_0                   (0x01UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00008000 */
+#define ADC_JSQR_JSQ2_1                   (0x02UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00010000 */
+#define ADC_JSQR_JSQ2_2                   (0x04UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00020000 */
+#define ADC_JSQR_JSQ2_3                   (0x08UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00040000 */
+#define ADC_JSQR_JSQ2_4                   (0x10UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00080000 */
+
+#define ADC_JSQR_JSQ3_Pos                 (21U)
+#define ADC_JSQR_JSQ3_Msk                 (0x1FUL << ADC_JSQR_JSQ3_Pos)        /*!< 0x03E00000 */
+#define ADC_JSQR_JSQ3                     ADC_JSQR_JSQ3_Msk                    /*!< ADC 3rd conversion in injected sequence */
+#define ADC_JSQR_JSQ3_0                   (0x01UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00200000 */
+#define ADC_JSQR_JSQ3_1                   (0x02UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00400000 */
+#define ADC_JSQR_JSQ3_2                   (0x04UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00800000 */
+#define ADC_JSQR_JSQ3_3                   (0x08UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x01000000 */
+#define ADC_JSQR_JSQ3_4                   (0x10UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x02000000 */
+
+#define ADC_JSQR_JSQ4_Pos                 (27U)
+#define ADC_JSQR_JSQ4_Msk                 (0x1FUL << ADC_JSQR_JSQ4_Pos)        /*!< 0xF8000000 */
+#define ADC_JSQR_JSQ4                     ADC_JSQR_JSQ4_Msk                    /*!< ADC 4th conversion in injected sequence */
+#define ADC_JSQR_JSQ4_0                   (0x01UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x08000000 */
+#define ADC_JSQR_JSQ4_1                   (0x02UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x10000000 */
+#define ADC_JSQR_JSQ4_2                   (0x04UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x20000000 */
+#define ADC_JSQR_JSQ4_3                   (0x08UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x40000000 */
+#define ADC_JSQR_JSQ4_4                   (0x10UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_OFR1 register  ********************/
+#define ADC_OFR1_OFFSET1_Pos              (0U)
+#define ADC_OFR1_OFFSET1_Msk              (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */
+#define ADC_OFR1_OFFSET1                  ADC_OFR1_OFFSET1_Msk                  /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
+#define ADC_OFR1_OFFSET1_0                (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
+#define ADC_OFR1_OFFSET1_1                (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
+#define ADC_OFR1_OFFSET1_2                (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
+#define ADC_OFR1_OFFSET1_3                (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
+#define ADC_OFR1_OFFSET1_4                (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
+#define ADC_OFR1_OFFSET1_5                (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
+#define ADC_OFR1_OFFSET1_6                (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
+#define ADC_OFR1_OFFSET1_7                (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
+#define ADC_OFR1_OFFSET1_8                (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
+#define ADC_OFR1_OFFSET1_9                (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
+#define ADC_OFR1_OFFSET1_10               (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
+#define ADC_OFR1_OFFSET1_11               (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
+#define ADC_OFR1_OFFSET1_12               (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */
+#define ADC_OFR1_OFFSET1_13               (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */
+#define ADC_OFR1_OFFSET1_14               (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */
+#define ADC_OFR1_OFFSET1_15               (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */
+#define ADC_OFR1_OFFSET1_16               (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */
+#define ADC_OFR1_OFFSET1_17               (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */
+#define ADC_OFR1_OFFSET1_18               (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */
+#define ADC_OFR1_OFFSET1_19               (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */
+#define ADC_OFR1_OFFSET1_20               (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */
+#define ADC_OFR1_OFFSET1_21               (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */
+#define ADC_OFR1_OFFSET1_22               (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */
+#define ADC_OFR1_OFFSET1_23               (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */
+#define ADC_OFR1_OFFSET1_24               (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */
+#define ADC_OFR1_OFFSET1_25               (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */
+
+#define ADC_OFR1_OFFSET1_CH_Pos           (26U)
+#define ADC_OFR1_OFFSET1_CH_Msk           (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x7C000000 */
+#define ADC_OFR1_OFFSET1_CH               ADC_OFR1_OFFSET1_CH_Msk               /*!< ADC Channel selection for the data offset 1 */
+#define ADC_OFR1_OFFSET1_CH_0             (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x04000000 */
+#define ADC_OFR1_OFFSET1_CH_1             (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x08000000 */
+#define ADC_OFR1_OFFSET1_CH_2             (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x10000000 */
+#define ADC_OFR1_OFFSET1_CH_3             (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x20000000 */
+#define ADC_OFR1_OFFSET1_CH_4             (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x40000000 */
+
+#define ADC_OFR1_SSATE_Pos                (31U)
+#define ADC_OFR1_SSATE_Msk                (0x1UL << ADC_OFR1_SSATE_Pos)         /*!< 0x80000000 */
+#define ADC_OFR1_SSATE                    ADC_OFR1_SSATE_Msk                    /*!< ADC Signed saturation Enable */
+
+
+/********************  Bit definition for ADC_OFR2 register  ********************/
+#define ADC_OFR2_OFFSET2_Pos              (0U)
+#define ADC_OFR2_OFFSET2_Msk              (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */
+#define ADC_OFR2_OFFSET2                  ADC_OFR2_OFFSET2_Msk                  /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
+#define ADC_OFR2_OFFSET2_0                (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
+#define ADC_OFR2_OFFSET2_1                (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
+#define ADC_OFR2_OFFSET2_2                (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
+#define ADC_OFR2_OFFSET2_3                (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
+#define ADC_OFR2_OFFSET2_4                (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
+#define ADC_OFR2_OFFSET2_5                (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
+#define ADC_OFR2_OFFSET2_6                (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
+#define ADC_OFR2_OFFSET2_7                (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
+#define ADC_OFR2_OFFSET2_8                (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
+#define ADC_OFR2_OFFSET2_9                (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
+#define ADC_OFR2_OFFSET2_10               (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
+#define ADC_OFR2_OFFSET2_11               (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
+#define ADC_OFR2_OFFSET2_12               (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */
+#define ADC_OFR2_OFFSET2_13               (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */
+#define ADC_OFR2_OFFSET2_14               (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */
+#define ADC_OFR2_OFFSET2_15               (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */
+#define ADC_OFR2_OFFSET2_16               (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */
+#define ADC_OFR2_OFFSET2_17               (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */
+#define ADC_OFR2_OFFSET2_18               (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */
+#define ADC_OFR2_OFFSET2_19               (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */
+#define ADC_OFR2_OFFSET2_20               (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */
+#define ADC_OFR2_OFFSET2_21               (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */
+#define ADC_OFR2_OFFSET2_22               (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */
+#define ADC_OFR2_OFFSET2_23               (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */
+#define ADC_OFR2_OFFSET2_24               (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */
+#define ADC_OFR2_OFFSET2_25               (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */
+
+#define ADC_OFR2_OFFSET2_CH_Pos           (26U)
+#define ADC_OFR2_OFFSET2_CH_Msk           (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x7C000000 */
+#define ADC_OFR2_OFFSET2_CH               ADC_OFR2_OFFSET2_CH_Msk               /*!< ADC Channel selection for the data offset 2 */
+#define ADC_OFR2_OFFSET2_CH_0             (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x04000000 */
+#define ADC_OFR2_OFFSET2_CH_1             (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x08000000 */
+#define ADC_OFR2_OFFSET2_CH_2             (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x10000000 */
+#define ADC_OFR2_OFFSET2_CH_3             (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x20000000 */
+#define ADC_OFR2_OFFSET2_CH_4             (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x40000000 */
+
+#define ADC_OFR2_SSATE_Pos                (31U)
+#define ADC_OFR2_SSATE_Msk                (0x1UL << ADC_OFR2_SSATE_Pos)         /*!< 0x80000000 */
+#define ADC_OFR2_SSATE                    ADC_OFR2_SSATE_Msk                    /*!< ADC Signed saturation Enable */
+
+
+/********************  Bit definition for ADC_OFR3 register  ********************/
+#define ADC_OFR3_OFFSET3_Pos              (0U)
+#define ADC_OFR3_OFFSET3_Msk              (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */
+#define ADC_OFR3_OFFSET3                  ADC_OFR3_OFFSET3_Msk                  /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
+#define ADC_OFR3_OFFSET3_0                (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
+#define ADC_OFR3_OFFSET3_1                (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
+#define ADC_OFR3_OFFSET3_2                (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
+#define ADC_OFR3_OFFSET3_3                (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
+#define ADC_OFR3_OFFSET3_4                (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
+#define ADC_OFR3_OFFSET3_5                (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
+#define ADC_OFR3_OFFSET3_6                (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
+#define ADC_OFR3_OFFSET3_7                (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
+#define ADC_OFR3_OFFSET3_8                (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
+#define ADC_OFR3_OFFSET3_9                (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
+#define ADC_OFR3_OFFSET3_10               (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
+#define ADC_OFR3_OFFSET3_11               (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
+#define ADC_OFR3_OFFSET3_12               (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */
+#define ADC_OFR3_OFFSET3_13               (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */
+#define ADC_OFR3_OFFSET3_14               (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */
+#define ADC_OFR3_OFFSET3_15               (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */
+#define ADC_OFR3_OFFSET3_16               (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */
+#define ADC_OFR3_OFFSET3_17               (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */
+#define ADC_OFR3_OFFSET3_18               (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */
+#define ADC_OFR3_OFFSET3_19               (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */
+#define ADC_OFR3_OFFSET3_20               (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */
+#define ADC_OFR3_OFFSET3_21               (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */
+#define ADC_OFR3_OFFSET3_22               (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */
+#define ADC_OFR3_OFFSET3_23               (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */
+#define ADC_OFR3_OFFSET3_24               (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */
+#define ADC_OFR3_OFFSET3_25               (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */
+
+#define ADC_OFR3_OFFSET3_CH_Pos           (26U)
+#define ADC_OFR3_OFFSET3_CH_Msk           (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x7C000000 */
+#define ADC_OFR3_OFFSET3_CH               ADC_OFR3_OFFSET3_CH_Msk               /*!< ADC Channel selection for the data offset 3 */
+#define ADC_OFR3_OFFSET3_CH_0             (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x04000000 */
+#define ADC_OFR3_OFFSET3_CH_1             (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x08000000 */
+#define ADC_OFR3_OFFSET3_CH_2             (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x10000000 */
+#define ADC_OFR3_OFFSET3_CH_3             (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x20000000 */
+#define ADC_OFR3_OFFSET3_CH_4             (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x40000000 */
+
+#define ADC_OFR3_SSATE_Pos                (31U)
+#define ADC_OFR3_SSATE_Msk                (0x1UL << ADC_OFR3_SSATE_Pos)         /*!< 0x80000000 */
+#define ADC_OFR3_SSATE                    ADC_OFR3_SSATE_Msk                    /*!< ADC Signed saturation Enable */
+
+
+/********************  Bit definition for ADC_OFR4 register  ********************/
+#define ADC_OFR4_OFFSET4_Pos              (0U)
+#define ADC_OFR4_OFFSET4_Msk              (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */
+#define ADC_OFR4_OFFSET4                  ADC_OFR4_OFFSET4_Msk                  /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
+#define ADC_OFR4_OFFSET4_0                (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
+#define ADC_OFR4_OFFSET4_1                (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
+#define ADC_OFR4_OFFSET4_2                (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
+#define ADC_OFR4_OFFSET4_3                (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
+#define ADC_OFR4_OFFSET4_4                (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
+#define ADC_OFR4_OFFSET4_5                (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
+#define ADC_OFR4_OFFSET4_6                (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
+#define ADC_OFR4_OFFSET4_7                (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
+#define ADC_OFR4_OFFSET4_8                (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
+#define ADC_OFR4_OFFSET4_9                (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
+#define ADC_OFR4_OFFSET4_10               (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
+#define ADC_OFR4_OFFSET4_11               (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
+#define ADC_OFR4_OFFSET4_12               (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */
+#define ADC_OFR4_OFFSET4_13               (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */
+#define ADC_OFR4_OFFSET4_14               (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */
+#define ADC_OFR4_OFFSET4_15               (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */
+#define ADC_OFR4_OFFSET4_16               (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */
+#define ADC_OFR4_OFFSET4_17               (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */
+#define ADC_OFR4_OFFSET4_18               (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */
+#define ADC_OFR4_OFFSET4_19               (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */
+#define ADC_OFR4_OFFSET4_20               (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */
+#define ADC_OFR4_OFFSET4_21               (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */
+#define ADC_OFR4_OFFSET4_22               (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */
+#define ADC_OFR4_OFFSET4_23               (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */
+#define ADC_OFR4_OFFSET4_24               (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */
+#define ADC_OFR4_OFFSET4_25               (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */
+
+#define ADC_OFR4_OFFSET4_CH_Pos           (26U)
+#define ADC_OFR4_OFFSET4_CH_Msk           (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x7C000000 */
+#define ADC_OFR4_OFFSET4_CH               ADC_OFR4_OFFSET4_CH_Msk               /*!< ADC Channel selection for the data offset 4 */
+#define ADC_OFR4_OFFSET4_CH_0             (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x04000000 */
+#define ADC_OFR4_OFFSET4_CH_1             (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x08000000 */
+#define ADC_OFR4_OFFSET4_CH_2             (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x10000000 */
+#define ADC_OFR4_OFFSET4_CH_3             (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x20000000 */
+#define ADC_OFR4_OFFSET4_CH_4             (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x40000000 */
+
+#define ADC_OFR4_SSATE_Pos                (31U)
+#define ADC_OFR4_SSATE_Msk                (0x1UL << ADC_OFR4_SSATE_Pos)         /*!< 0x80000000 */
+#define ADC_OFR4_SSATE                    ADC_OFR4_SSATE_Msk                    /*!< ADC Signed saturation Enable */
+
+
+/********************  Bit definition for ADC_JDR1 register  ********************/
+#define ADC_JDR1_JDATA_Pos                (0U)
+#define ADC_JDR1_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos)  /*!< 0xFFFFFFFF */
+#define ADC_JDR1_JDATA                    ADC_JDR1_JDATA_Msk                    /*!< ADC Injected DATA */
+#define ADC_JDR1_JDATA_0                  (0x00000001UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000001 */
+#define ADC_JDR1_JDATA_1                  (0x00000002UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000002 */
+#define ADC_JDR1_JDATA_2                  (0x00000004UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000004 */
+#define ADC_JDR1_JDATA_3                  (0x00000008UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000008 */
+#define ADC_JDR1_JDATA_4                  (0x00000010UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000010 */
+#define ADC_JDR1_JDATA_5                  (0x00000020UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000020 */
+#define ADC_JDR1_JDATA_6                  (0x00000040UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000040 */
+#define ADC_JDR1_JDATA_7                  (0x00000080UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000080 */
+#define ADC_JDR1_JDATA_8                  (0x00000100UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000100 */
+#define ADC_JDR1_JDATA_9                  (0x00000200UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000200 */
+#define ADC_JDR1_JDATA_10                 (0x00000400UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000400 */
+#define ADC_JDR1_JDATA_11                 (0x00000800UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000800 */
+#define ADC_JDR1_JDATA_12                 (0x00001000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00001000 */
+#define ADC_JDR1_JDATA_13                 (0x00002000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00002000 */
+#define ADC_JDR1_JDATA_14                 (0x00004000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00004000 */
+#define ADC_JDR1_JDATA_15                 (0x00008000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00008000 */
+#define ADC_JDR1_JDATA_16                 (0x00010000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00010000 */
+#define ADC_JDR1_JDATA_17                 (0x00020000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00020000 */
+#define ADC_JDR1_JDATA_18                 (0x00040000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00040000 */
+#define ADC_JDR1_JDATA_19                 (0x00080000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00080000 */
+#define ADC_JDR1_JDATA_20                 (0x00100000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00100000 */
+#define ADC_JDR1_JDATA_21                 (0x00200000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00200000 */
+#define ADC_JDR1_JDATA_22                 (0x00400000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00400000 */
+#define ADC_JDR1_JDATA_23                 (0x00800000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00800000 */
+#define ADC_JDR1_JDATA_24                 (0x01000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x01000000 */
+#define ADC_JDR1_JDATA_25                 (0x02000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x02000000 */
+#define ADC_JDR1_JDATA_26                 (0x04000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x04000000 */
+#define ADC_JDR1_JDATA_27                 (0x08000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x08000000 */
+#define ADC_JDR1_JDATA_28                 (0x10000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x10000000 */
+#define ADC_JDR1_JDATA_29                 (0x20000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x20000000 */
+#define ADC_JDR1_JDATA_30                 (0x40000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x40000000 */
+#define ADC_JDR1_JDATA_31                 (0x80000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_JDR2 register  ********************/
+#define ADC_JDR2_JDATA_Pos                (0U)
+#define ADC_JDR2_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos)  /*!< 0xFFFFFFFF */
+#define ADC_JDR2_JDATA                    ADC_JDR2_JDATA_Msk                    /*!< ADC Injected DATA */
+#define ADC_JDR2_JDATA_0                  (0x00000001UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000001 */
+#define ADC_JDR2_JDATA_1                  (0x00000002UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000002 */
+#define ADC_JDR2_JDATA_2                  (0x00000004UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000004 */
+#define ADC_JDR2_JDATA_3                  (0x00000008UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000008 */
+#define ADC_JDR2_JDATA_4                  (0x00000010UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000010 */
+#define ADC_JDR2_JDATA_5                  (0x00000020UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000020 */
+#define ADC_JDR2_JDATA_6                  (0x00000040UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000040 */
+#define ADC_JDR2_JDATA_7                  (0x00000080UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000080 */
+#define ADC_JDR2_JDATA_8                  (0x00000100UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000100 */
+#define ADC_JDR2_JDATA_9                  (0x00000200UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000200 */
+#define ADC_JDR2_JDATA_10                 (0x00000400UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000400 */
+#define ADC_JDR2_JDATA_11                 (0x00000800UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000800 */
+#define ADC_JDR2_JDATA_12                 (0x00001000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00001000 */
+#define ADC_JDR2_JDATA_13                 (0x00002000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00002000 */
+#define ADC_JDR2_JDATA_14                 (0x00004000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00004000 */
+#define ADC_JDR2_JDATA_15                 (0x00008000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00008000 */
+#define ADC_JDR2_JDATA_16                 (0x00010000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00010000 */
+#define ADC_JDR2_JDATA_17                 (0x00020000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00020000 */
+#define ADC_JDR2_JDATA_18                 (0x00040000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00040000 */
+#define ADC_JDR2_JDATA_19                 (0x00080000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00080000 */
+#define ADC_JDR2_JDATA_20                 (0x00100000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00100000 */
+#define ADC_JDR2_JDATA_21                 (0x00200000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00200000 */
+#define ADC_JDR2_JDATA_22                 (0x00400000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00400000 */
+#define ADC_JDR2_JDATA_23                 (0x00800000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00800000 */
+#define ADC_JDR2_JDATA_24                 (0x01000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x01000000 */
+#define ADC_JDR2_JDATA_25                 (0x02000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x02000000 */
+#define ADC_JDR2_JDATA_26                 (0x04000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x04000000 */
+#define ADC_JDR2_JDATA_27                 (0x08000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x08000000 */
+#define ADC_JDR2_JDATA_28                 (0x10000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x10000000 */
+#define ADC_JDR2_JDATA_29                 (0x20000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x20000000 */
+#define ADC_JDR2_JDATA_30                 (0x40000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x40000000 */
+#define ADC_JDR2_JDATA_31                 (0x80000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_JDR3 register  ********************/
+#define ADC_JDR3_JDATA_Pos                (0U)
+#define ADC_JDR3_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos)  /*!< 0xFFFFFFFF */
+#define ADC_JDR3_JDATA                    ADC_JDR3_JDATA_Msk                    /*!< ADC Injected DATA */
+#define ADC_JDR3_JDATA_0                  (0x00000001UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000001 */
+#define ADC_JDR3_JDATA_1                  (0x00000002UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000002 */
+#define ADC_JDR3_JDATA_2                  (0x00000004UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000004 */
+#define ADC_JDR3_JDATA_3                  (0x00000008UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000008 */
+#define ADC_JDR3_JDATA_4                  (0x00000010UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000010 */
+#define ADC_JDR3_JDATA_5                  (0x00000020UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000020 */
+#define ADC_JDR3_JDATA_6                  (0x00000040UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000040 */
+#define ADC_JDR3_JDATA_7                  (0x00000080UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000080 */
+#define ADC_JDR3_JDATA_8                  (0x00000100UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000100 */
+#define ADC_JDR3_JDATA_9                  (0x00000200UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000200 */
+#define ADC_JDR3_JDATA_10                 (0x00000400UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000400 */
+#define ADC_JDR3_JDATA_11                 (0x00000800UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000800 */
+#define ADC_JDR3_JDATA_12                 (0x00001000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00001000 */
+#define ADC_JDR3_JDATA_13                 (0x00002000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00002000 */
+#define ADC_JDR3_JDATA_14                 (0x00004000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00004000 */
+#define ADC_JDR3_JDATA_15                 (0x00008000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00008000 */
+#define ADC_JDR3_JDATA_16                 (0x00010000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00010000 */
+#define ADC_JDR3_JDATA_17                 (0x00020000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00020000 */
+#define ADC_JDR3_JDATA_18                 (0x00040000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00040000 */
+#define ADC_JDR3_JDATA_19                 (0x00080000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00080000 */
+#define ADC_JDR3_JDATA_20                 (0x00100000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00100000 */
+#define ADC_JDR3_JDATA_21                 (0x00200000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00200000 */
+#define ADC_JDR3_JDATA_22                 (0x00400000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00400000 */
+#define ADC_JDR3_JDATA_23                 (0x00800000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00800000 */
+#define ADC_JDR3_JDATA_24                 (0x01000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x01000000 */
+#define ADC_JDR3_JDATA_25                 (0x02000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x02000000 */
+#define ADC_JDR3_JDATA_26                 (0x04000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x04000000 */
+#define ADC_JDR3_JDATA_27                 (0x08000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x08000000 */
+#define ADC_JDR3_JDATA_28                 (0x10000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x10000000 */
+#define ADC_JDR3_JDATA_29                 (0x20000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x20000000 */
+#define ADC_JDR3_JDATA_30                 (0x40000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x40000000 */
+#define ADC_JDR3_JDATA_31                 (0x80000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_JDR4 register  ********************/
+#define ADC_JDR4_JDATA_Pos                (0U)
+#define ADC_JDR4_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos)  /*!< 0xFFFFFFFF */
+#define ADC_JDR4_JDATA                    ADC_JDR4_JDATA_Msk                    /*!< ADC Injected DATA */
+#define ADC_JDR4_JDATA_0                  (0x00000001UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000001 */
+#define ADC_JDR4_JDATA_1                  (0x00000002UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000002 */
+#define ADC_JDR4_JDATA_2                  (0x00000004UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000004 */
+#define ADC_JDR4_JDATA_3                  (0x00000008UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000008 */
+#define ADC_JDR4_JDATA_4                  (0x00000010UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000010 */
+#define ADC_JDR4_JDATA_5                  (0x00000020UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000020 */
+#define ADC_JDR4_JDATA_6                  (0x00000040UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000040 */
+#define ADC_JDR4_JDATA_7                  (0x00000080UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000080 */
+#define ADC_JDR4_JDATA_8                  (0x00000100UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000100 */
+#define ADC_JDR4_JDATA_9                  (0x00000200UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000200 */
+#define ADC_JDR4_JDATA_10                 (0x00000400UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000400 */
+#define ADC_JDR4_JDATA_11                 (0x00000800UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000800 */
+#define ADC_JDR4_JDATA_12                 (0x00001000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00001000 */
+#define ADC_JDR4_JDATA_13                 (0x00002000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00002000 */
+#define ADC_JDR4_JDATA_14                 (0x00004000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00004000 */
+#define ADC_JDR4_JDATA_15                 (0x00008000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00008000 */
+#define ADC_JDR4_JDATA_16                 (0x00010000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00010000 */
+#define ADC_JDR4_JDATA_17                 (0x00020000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00020000 */
+#define ADC_JDR4_JDATA_18                 (0x00040000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00040000 */
+#define ADC_JDR4_JDATA_19                 (0x00080000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00080000 */
+#define ADC_JDR4_JDATA_20                 (0x00100000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00100000 */
+#define ADC_JDR4_JDATA_21                 (0x00200000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00200000 */
+#define ADC_JDR4_JDATA_22                 (0x00400000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00400000 */
+#define ADC_JDR4_JDATA_23                 (0x00800000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00800000 */
+#define ADC_JDR4_JDATA_24                 (0x01000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x01000000 */
+#define ADC_JDR4_JDATA_25                 (0x02000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x02000000 */
+#define ADC_JDR4_JDATA_26                 (0x04000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x04000000 */
+#define ADC_JDR4_JDATA_27                 (0x08000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x08000000 */
+#define ADC_JDR4_JDATA_28                 (0x10000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x10000000 */
+#define ADC_JDR4_JDATA_29                 (0x20000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x20000000 */
+#define ADC_JDR4_JDATA_30                 (0x40000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x40000000 */
+#define ADC_JDR4_JDATA_31                 (0x80000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_AWD2CR register  ********************/
+#define ADC_AWD2CR_AWD2CH_Pos             (0U)
+#define ADC_AWD2CR_AWD2CH_Msk             (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x000FFFFF */
+#define ADC_AWD2CR_AWD2CH                 ADC_AWD2CR_AWD2CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */
+#define ADC_AWD2CR_AWD2CH_0               (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000001 */
+#define ADC_AWD2CR_AWD2CH_1               (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000002 */
+#define ADC_AWD2CR_AWD2CH_2               (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000004 */
+#define ADC_AWD2CR_AWD2CH_3               (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000008 */
+#define ADC_AWD2CR_AWD2CH_4               (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000010 */
+#define ADC_AWD2CR_AWD2CH_5               (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000020 */
+#define ADC_AWD2CR_AWD2CH_6               (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000040 */
+#define ADC_AWD2CR_AWD2CH_7               (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000080 */
+#define ADC_AWD2CR_AWD2CH_8               (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000100 */
+#define ADC_AWD2CR_AWD2CH_9               (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000200 */
+#define ADC_AWD2CR_AWD2CH_10              (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000400 */
+#define ADC_AWD2CR_AWD2CH_11              (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000800 */
+#define ADC_AWD2CR_AWD2CH_12              (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00001000 */
+#define ADC_AWD2CR_AWD2CH_13              (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00002000 */
+#define ADC_AWD2CR_AWD2CH_14              (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00004000 */
+#define ADC_AWD2CR_AWD2CH_15              (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00008000 */
+#define ADC_AWD2CR_AWD2CH_16              (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00010000 */
+#define ADC_AWD2CR_AWD2CH_17              (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00020000 */
+#define ADC_AWD2CR_AWD2CH_18              (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00040000 */
+#define ADC_AWD2CR_AWD2CH_19              (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00080000 */
+
+/********************  Bit definition for ADC_AWD3CR register  ********************/
+#define ADC_AWD3CR_AWD3CH_Pos             (0U)
+#define ADC_AWD3CR_AWD3CH_Msk             (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x000FFFFF */
+#define ADC_AWD3CR_AWD3CH                 ADC_AWD3CR_AWD3CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */
+#define ADC_AWD3CR_AWD3CH_0               (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000001 */
+#define ADC_AWD3CR_AWD3CH_1               (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000002 */
+#define ADC_AWD3CR_AWD3CH_2               (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000004 */
+#define ADC_AWD3CR_AWD3CH_3               (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000008 */
+#define ADC_AWD3CR_AWD3CH_4               (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000010 */
+#define ADC_AWD3CR_AWD3CH_5               (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000020 */
+#define ADC_AWD3CR_AWD3CH_6               (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000040 */
+#define ADC_AWD3CR_AWD3CH_7               (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000080 */
+#define ADC_AWD3CR_AWD3CH_8               (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000100 */
+#define ADC_AWD3CR_AWD3CH_9               (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000200 */
+#define ADC_AWD3CR_AWD3CH_10              (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000400 */
+#define ADC_AWD3CR_AWD3CH_11              (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000800 */
+#define ADC_AWD3CR_AWD3CH_12              (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00001000 */
+#define ADC_AWD3CR_AWD3CH_13              (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00002000 */
+#define ADC_AWD3CR_AWD3CH_14              (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00004000 */
+#define ADC_AWD3CR_AWD3CH_15              (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00008000 */
+#define ADC_AWD3CR_AWD3CH_16              (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00010000 */
+#define ADC_AWD3CR_AWD3CH_17              (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00020000 */
+#define ADC_AWD3CR_AWD3CH_18              (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00040000 */
+#define ADC_AWD3CR_AWD3CH_19              (0x80000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00080000 */
+
+/********************  Bit definition for ADC_DIFSEL register  ********************/
+#define ADC_DIFSEL_DIFSEL_Pos             (0U)
+#define ADC_DIFSEL_DIFSEL_Msk             (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x000FFFFF */
+#define ADC_DIFSEL_DIFSEL                 ADC_DIFSEL_DIFSEL_Msk                 /*!< ADC differential modes for channels 1 to 18 */
+#define ADC_DIFSEL_DIFSEL_0               (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000001 */
+#define ADC_DIFSEL_DIFSEL_1               (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000002 */
+#define ADC_DIFSEL_DIFSEL_2               (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000004 */
+#define ADC_DIFSEL_DIFSEL_3               (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000008 */
+#define ADC_DIFSEL_DIFSEL_4               (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000010 */
+#define ADC_DIFSEL_DIFSEL_5               (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000020 */
+#define ADC_DIFSEL_DIFSEL_6               (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000040 */
+#define ADC_DIFSEL_DIFSEL_7               (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000080 */
+#define ADC_DIFSEL_DIFSEL_8               (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000100 */
+#define ADC_DIFSEL_DIFSEL_9               (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000200 */
+#define ADC_DIFSEL_DIFSEL_10              (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000400 */
+#define ADC_DIFSEL_DIFSEL_11              (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000800 */
+#define ADC_DIFSEL_DIFSEL_12              (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00001000 */
+#define ADC_DIFSEL_DIFSEL_13              (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00002000 */
+#define ADC_DIFSEL_DIFSEL_14              (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00004000 */
+#define ADC_DIFSEL_DIFSEL_15              (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00008000 */
+#define ADC_DIFSEL_DIFSEL_16              (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00010000 */
+#define ADC_DIFSEL_DIFSEL_17              (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00020000 */
+#define ADC_DIFSEL_DIFSEL_18              (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00040000 */
+#define ADC_DIFSEL_DIFSEL_19              (0x80000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00080000 */
+
+/********************  Bit definition for ADC_CALFACT register  ********************/
+#define ADC_CALFACT_CALFACT_S_Pos         (0U)
+#define ADC_CALFACT_CALFACT_S_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */
+#define ADC_CALFACT_CALFACT_S             ADC_CALFACT_CALFACT_S_Msk              /*!< ADC calibration factors in single-ended mode */
+#define ADC_CALFACT_CALFACT_S_0           (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
+#define ADC_CALFACT_CALFACT_S_1           (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
+#define ADC_CALFACT_CALFACT_S_2           (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
+#define ADC_CALFACT_CALFACT_S_3           (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
+#define ADC_CALFACT_CALFACT_S_4           (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
+#define ADC_CALFACT_CALFACT_S_5           (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
+#define ADC_CALFACT_CALFACT_S_6           (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
+#define ADC_CALFACT_CALFACT_S_7           (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */
+#define ADC_CALFACT_CALFACT_S_8           (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */
+#define ADC_CALFACT_CALFACT_S_9           (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */
+#define ADC_CALFACT_CALFACT_S_10          (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */
+#define ADC_CALFACT_CALFACT_D_Pos         (16U)
+#define ADC_CALFACT_CALFACT_D_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */
+#define ADC_CALFACT_CALFACT_D             ADC_CALFACT_CALFACT_D_Msk              /*!< ADC calibration factors in differential mode */
+#define ADC_CALFACT_CALFACT_D_0           (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
+#define ADC_CALFACT_CALFACT_D_1           (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
+#define ADC_CALFACT_CALFACT_D_2           (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
+#define ADC_CALFACT_CALFACT_D_3           (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
+#define ADC_CALFACT_CALFACT_D_4           (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
+#define ADC_CALFACT_CALFACT_D_5           (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
+#define ADC_CALFACT_CALFACT_D_6           (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
+#define ADC_CALFACT_CALFACT_D_7           (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */
+#define ADC_CALFACT_CALFACT_D_8           (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */
+#define ADC_CALFACT_CALFACT_D_9           (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */
+#define ADC_CALFACT_CALFACT_D_10          (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */
+
+/********************  Bit definition for ADC_CALFACT2 register  ********************/
+#define ADC_CALFACT2_LINCALFACT_Pos       (0U)
+#define ADC_CALFACT2_LINCALFACT_Msk       (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */
+#define ADC_CALFACT2_LINCALFACT           ADC_CALFACT2_LINCALFACT_Msk                   /*!< ADC Linearity calibration factors */
+#define ADC_CALFACT2_LINCALFACT_0         (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */
+#define ADC_CALFACT2_LINCALFACT_1         (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */
+#define ADC_CALFACT2_LINCALFACT_2         (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */
+#define ADC_CALFACT2_LINCALFACT_3         (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */
+#define ADC_CALFACT2_LINCALFACT_4         (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */
+#define ADC_CALFACT2_LINCALFACT_5         (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */
+#define ADC_CALFACT2_LINCALFACT_6         (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */
+#define ADC_CALFACT2_LINCALFACT_7         (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */
+#define ADC_CALFACT2_LINCALFACT_8         (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */
+#define ADC_CALFACT2_LINCALFACT_9         (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */
+#define ADC_CALFACT2_LINCALFACT_10        (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */
+#define ADC_CALFACT2_LINCALFACT_11        (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */
+#define ADC_CALFACT2_LINCALFACT_12        (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */
+#define ADC_CALFACT2_LINCALFACT_13        (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */
+#define ADC_CALFACT2_LINCALFACT_14        (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */
+#define ADC_CALFACT2_LINCALFACT_15        (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */
+#define ADC_CALFACT2_LINCALFACT_16        (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */
+#define ADC_CALFACT2_LINCALFACT_17        (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */
+#define ADC_CALFACT2_LINCALFACT_18        (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */
+#define ADC_CALFACT2_LINCALFACT_19        (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */
+#define ADC_CALFACT2_LINCALFACT_20        (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */
+#define ADC_CALFACT2_LINCALFACT_21        (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */
+#define ADC_CALFACT2_LINCALFACT_22        (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */
+#define ADC_CALFACT2_LINCALFACT_23        (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */
+#define ADC_CALFACT2_LINCALFACT_24        (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */
+#define ADC_CALFACT2_LINCALFACT_25        (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */
+#define ADC_CALFACT2_LINCALFACT_26        (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */
+#define ADC_CALFACT2_LINCALFACT_27        (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */
+#define ADC_CALFACT2_LINCALFACT_28        (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */
+#define ADC_CALFACT2_LINCALFACT_29        (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */
+
+/*************************  ADC Common registers  *****************************/
+/********************  Bit definition for ADC_CSR register  ********************/
+#define ADC_CSR_ADRDY_MST_Pos             (0U)
+#define ADC_CSR_ADRDY_MST_Msk             (0x1UL << ADC_CSR_ADRDY_MST_Pos)     /*!< 0x00000001 */
+#define ADC_CSR_ADRDY_MST                 ADC_CSR_ADRDY_MST_Msk                /*!< Master ADC ready */
+#define ADC_CSR_EOSMP_MST_Pos             (1U)
+#define ADC_CSR_EOSMP_MST_Msk             (0x1UL << ADC_CSR_EOSMP_MST_Pos)     /*!< 0x00000002 */
+#define ADC_CSR_EOSMP_MST                 ADC_CSR_EOSMP_MST_Msk                /*!< End of sampling phase flag of the master ADC */
+#define ADC_CSR_EOC_MST_Pos               (2U)
+#define ADC_CSR_EOC_MST_Msk               (0x1UL << ADC_CSR_EOC_MST_Pos)       /*!< 0x00000004 */
+#define ADC_CSR_EOC_MST                   ADC_CSR_EOC_MST_Msk                  /*!< End of regular conversion of the master ADC */
+#define ADC_CSR_EOS_MST_Pos               (3U)
+#define ADC_CSR_EOS_MST_Msk               (0x1UL << ADC_CSR_EOS_MST_Pos)       /*!< 0x00000008 */
+#define ADC_CSR_EOS_MST                   ADC_CSR_EOS_MST_Msk                  /*!< End of regular sequence flag of the master ADC */
+#define ADC_CSR_OVR_MST_Pos               (4U)
+#define ADC_CSR_OVR_MST_Msk               (0x1UL << ADC_CSR_OVR_MST_Pos)       /*!< 0x00000010 */
+#define ADC_CSR_OVR_MST                   ADC_CSR_OVR_MST_Msk                  /*!< Overrun flag of the master ADC */
+#define ADC_CSR_JEOC_MST_Pos              (5U)
+#define ADC_CSR_JEOC_MST_Msk              (0x1UL << ADC_CSR_JEOC_MST_Pos)      /*!< 0x00000020 */
+#define ADC_CSR_JEOC_MST                  ADC_CSR_JEOC_MST_Msk                 /*!< End of injected conversion of the master ADC */
+#define ADC_CSR_JEOS_MST_Pos              (6U)
+#define ADC_CSR_JEOS_MST_Msk              (0x1UL << ADC_CSR_JEOS_MST_Pos)      /*!< 0x00000040 */
+#define ADC_CSR_JEOS_MST                  ADC_CSR_JEOS_MST_Msk                 /*!< End of injected sequence flag of the master ADC */
+#define ADC_CSR_AWD1_MST_Pos              (7U)
+#define ADC_CSR_AWD1_MST_Msk              (0x1UL << ADC_CSR_AWD1_MST_Pos)      /*!< 0x00000080 */
+#define ADC_CSR_AWD1_MST                  ADC_CSR_AWD1_MST_Msk                 /*!< Analog watchdog 1 flag of the master ADC */
+#define ADC_CSR_AWD2_MST_Pos              (8U)
+#define ADC_CSR_AWD2_MST_Msk              (0x1UL << ADC_CSR_AWD2_MST_Pos)      /*!< 0x00000100 */
+#define ADC_CSR_AWD2_MST                  ADC_CSR_AWD2_MST_Msk                 /*!< Analog watchdog 2 flag of the master ADC */
+#define ADC_CSR_AWD3_MST_Pos              (9U)
+#define ADC_CSR_AWD3_MST_Msk              (0x1UL << ADC_CSR_AWD3_MST_Pos)      /*!< 0x00000200 */
+#define ADC_CSR_AWD3_MST                  ADC_CSR_AWD3_MST_Msk                 /*!< Analog watchdog 3 flag of the master ADC */
+#define ADC_CSR_JQOVF_MST_Pos             (10U)
+#define ADC_CSR_JQOVF_MST_Msk             (0x1UL << ADC_CSR_JQOVF_MST_Pos)     /*!< 0x00000400 */
+#define ADC_CSR_JQOVF_MST                 ADC_CSR_JQOVF_MST_Msk                /*!< Injected context queue overflow flag of the master ADC */
+#define ADC_CSR_ADRDY_SLV_Pos             (16U)
+#define ADC_CSR_ADRDY_SLV_Msk             (0x1UL << ADC_CSR_ADRDY_SLV_Pos)     /*!< 0x00010000 */
+#define ADC_CSR_ADRDY_SLV                 ADC_CSR_ADRDY_SLV_Msk                /*!< Slave ADC ready */
+#define ADC_CSR_EOSMP_SLV_Pos             (17U)
+#define ADC_CSR_EOSMP_SLV_Msk             (0x1UL << ADC_CSR_EOSMP_SLV_Pos)     /*!< 0x00020000 */
+#define ADC_CSR_EOSMP_SLV                 ADC_CSR_EOSMP_SLV_Msk                /*!< End of sampling phase flag of the slave ADC */
+#define ADC_CSR_EOC_SLV_Pos               (18U)
+#define ADC_CSR_EOC_SLV_Msk               (0x1UL << ADC_CSR_EOC_SLV_Pos)       /*!< 0x00040000 */
+#define ADC_CSR_EOC_SLV                   ADC_CSR_EOC_SLV_Msk                  /*!< End of regular conversion of the slave ADC */
+#define ADC_CSR_EOS_SLV_Pos               (19U)
+#define ADC_CSR_EOS_SLV_Msk               (0x1UL << ADC_CSR_EOS_SLV_Pos)       /*!< 0x00080000 */
+#define ADC_CSR_EOS_SLV                   ADC_CSR_EOS_SLV_Msk                  /*!< End of regular sequence flag of the slave ADC */
+#define ADC_CSR_OVR_SLV_Pos               (20U)
+#define ADC_CSR_OVR_SLV_Msk               (0x1UL << ADC_CSR_OVR_SLV_Pos)       /*!< 0x00100000 */
+#define ADC_CSR_OVR_SLV                   ADC_CSR_OVR_SLV_Msk                  /*!< Overrun flag of the slave ADC */
+#define ADC_CSR_JEOC_SLV_Pos              (21U)
+#define ADC_CSR_JEOC_SLV_Msk              (0x1UL << ADC_CSR_JEOC_SLV_Pos)      /*!< 0x00200000 */
+#define ADC_CSR_JEOC_SLV                  ADC_CSR_JEOC_SLV_Msk                 /*!< End of injected conversion of the slave ADC */
+#define ADC_CSR_JEOS_SLV_Pos              (22U)
+#define ADC_CSR_JEOS_SLV_Msk              (0x1UL << ADC_CSR_JEOS_SLV_Pos)      /*!< 0x00400000 */
+#define ADC_CSR_JEOS_SLV                  ADC_CSR_JEOS_SLV_Msk                 /*!< End of injected sequence flag of the slave ADC */
+#define ADC_CSR_AWD1_SLV_Pos              (23U)
+#define ADC_CSR_AWD1_SLV_Msk              (0x1UL << ADC_CSR_AWD1_SLV_Pos)      /*!< 0x00800000 */
+#define ADC_CSR_AWD1_SLV                  ADC_CSR_AWD1_SLV_Msk                 /*!< Analog watchdog 1 flag of the slave ADC */
+#define ADC_CSR_AWD2_SLV_Pos              (24U)
+#define ADC_CSR_AWD2_SLV_Msk              (0x1UL << ADC_CSR_AWD2_SLV_Pos)      /*!< 0x01000000 */
+#define ADC_CSR_AWD2_SLV                  ADC_CSR_AWD2_SLV_Msk                 /*!< Analog watchdog 2 flag of the slave ADC */
+#define ADC_CSR_AWD3_SLV_Pos              (25U)
+#define ADC_CSR_AWD3_SLV_Msk              (0x1UL << ADC_CSR_AWD3_SLV_Pos)      /*!< 0x02000000 */
+#define ADC_CSR_AWD3_SLV                  ADC_CSR_AWD3_SLV_Msk                 /*!< Analog watchdog 3 flag of the slave ADC */
+#define ADC_CSR_JQOVF_SLV_Pos             (26U)
+#define ADC_CSR_JQOVF_SLV_Msk             (0x1UL << ADC_CSR_JQOVF_SLV_Pos)     /*!< 0x04000000 */
+#define ADC_CSR_JQOVF_SLV                 ADC_CSR_JQOVF_SLV_Msk                /*!< Injected context queue overflow flag of the slave ADC */
+
+/********************  Bit definition for ADC_CCR register  ********************/
+#define ADC_CCR_DUAL_Pos                  (0U)
+#define ADC_CCR_DUAL_Msk                  (0x1FUL << ADC_CCR_DUAL_Pos)          /*!< 0x0000001F */
+#define ADC_CCR_DUAL                      ADC_CCR_DUAL_Msk                      /*!< Dual ADC mode selection */
+#define ADC_CCR_DUAL_0                    (0x01UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000001 */
+#define ADC_CCR_DUAL_1                    (0x02UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000002 */
+#define ADC_CCR_DUAL_2                    (0x04UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000004 */
+#define ADC_CCR_DUAL_3                    (0x08UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000008 */
+#define ADC_CCR_DUAL_4                    (0x10UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000010 */
+
+#define ADC_CCR_DELAY_Pos                 (8U)
+#define ADC_CCR_DELAY_Msk                 (0xFUL << ADC_CCR_DELAY_Pos)          /*!< 0x00000F00 */
+#define ADC_CCR_DELAY                     ADC_CCR_DELAY_Msk                     /*!< Delay between 2 sampling phases */
+#define ADC_CCR_DELAY_0                   (0x1UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000100 */
+#define ADC_CCR_DELAY_1                   (0x2UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000200 */
+#define ADC_CCR_DELAY_2                   (0x4UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000400 */
+#define ADC_CCR_DELAY_3                   (0x8UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000800 */
+
+
+#define ADC_CCR_DAMDF_Pos                 (14U)
+#define ADC_CCR_DAMDF_Msk                 (0x3UL << ADC_CCR_DAMDF_Pos)          /*!< 0x0000C000 */
+#define ADC_CCR_DAMDF                     ADC_CCR_DAMDF_Msk                     /*!< Dual ADC mode Data format */
+#define ADC_CCR_DAMDF_0                   (0x1UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00004000 */
+#define ADC_CCR_DAMDF_1                   (0x2UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00008000 */
+
+#define ADC_CCR_CKMODE_Pos                (16U)
+#define ADC_CCR_CKMODE_Msk                (0x3UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00030000 */
+#define ADC_CCR_CKMODE                    ADC_CCR_CKMODE_Msk                    /*!< ADC clock mode */
+#define ADC_CCR_CKMODE_0                  (0x1UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00010000 */
+#define ADC_CCR_CKMODE_1                  (0x2UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00020000 */
+
+#define ADC_CCR_PRESC_Pos                 (18U)
+#define ADC_CCR_PRESC_Msk                 (0xFUL << ADC_CCR_PRESC_Pos)          /*!< 0x003C0000 */
+#define ADC_CCR_PRESC                     ADC_CCR_PRESC_Msk                     /*!< ADC prescaler */
+#define ADC_CCR_PRESC_0                   (0x1UL << ADC_CCR_PRESC_Pos)          /*!< 0x00040000 */
+#define ADC_CCR_PRESC_1                   (0x2UL << ADC_CCR_PRESC_Pos)          /*!< 0x00080000 */
+#define ADC_CCR_PRESC_2                   (0x4UL << ADC_CCR_PRESC_Pos)          /*!< 0x00100000 */
+#define ADC_CCR_PRESC_3                   (0x8UL << ADC_CCR_PRESC_Pos)          /*!< 0x00200000 */
+
+#define ADC_CCR_VREFEN_Pos                (22U)
+#define ADC_CCR_VREFEN_Msk                (0x1UL << ADC_CCR_VREFEN_Pos)         /*!< 0x00400000 */
+#define ADC_CCR_VREFEN                    ADC_CCR_VREFEN_Msk                    /*!< VREFINT enable */
+#define ADC_CCR_TSEN_Pos                  (23U)
+#define ADC_CCR_TSEN_Msk                  (0x1UL << ADC_CCR_TSEN_Pos)           /*!< 0x00800000 */
+#define ADC_CCR_TSEN                      ADC_CCR_TSEN_Msk                      /*!< Temperature sensor enable */
+#define ADC_CCR_VBATEN_Pos                (24U)
+#define ADC_CCR_VBATEN_Msk                (0x1UL << ADC_CCR_VBATEN_Pos)         /*!< 0x01000000 */
+#define ADC_CCR_VBATEN                    ADC_CCR_VBATEN_Msk                    /*!< VBAT enable */
+
+/********************  Bit definition for ADC_CDR register  *******************/
+#define ADC_CDR_RDATA_MST_Pos             (0U)
+#define ADC_CDR_RDATA_MST_Msk             (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)   /*!< 0x0000FFFF */
+#define ADC_CDR_RDATA_MST                 ADC_CDR_RDATA_MST_Msk                 /*!< ADC multimode master group regular conversion data */
+
+#define ADC_CDR_RDATA_SLV_Pos             (16U)
+#define ADC_CDR_RDATA_SLV_Msk             (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)   /*!< 0xFFFF0000 */
+#define ADC_CDR_RDATA_SLV                 ADC_CDR_RDATA_SLV_Msk                 /*!< ADC multimode slave group regular conversion data */
+
+/********************  Bit definition for ADC_CDR2 register  ******************/
+#define ADC_CDR2_RDATA_ALT_Pos            (0U)
+#define ADC_CDR2_RDATA_ALT_Msk            (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */
+#define ADC_CDR2_RDATA_ALT                ADC_CDR2_RDATA_ALT_Msk                   /*!< Regular data of the master/slave alternated ADCs */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                   VREFBUF                                  */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for VREFBUF_CSR register  ****************/
+#define VREFBUF_CSR_ENVR_Pos        (0U)
+#define VREFBUF_CSR_ENVR_Msk        (0x1UL << VREFBUF_CSR_ENVR_Pos)            /*!< 0x00000001 */
+#define VREFBUF_CSR_ENVR            VREFBUF_CSR_ENVR_Msk                       /*!<Voltage reference buffer enable */
+#define VREFBUF_CSR_HIZ_Pos         (1U)
+#define VREFBUF_CSR_HIZ_Msk         (0x1UL << VREFBUF_CSR_HIZ_Pos)             /*!< 0x00000002 */
+#define VREFBUF_CSR_HIZ             VREFBUF_CSR_HIZ_Msk                        /*!<High impedance mode             */
+#define VREFBUF_CSR_VRR_Pos         (3U)
+#define VREFBUF_CSR_VRR_Msk         (0x1UL << VREFBUF_CSR_VRR_Pos)             /*!< 0x00000008 */
+#define VREFBUF_CSR_VRR             VREFBUF_CSR_VRR_Msk                        /*!<Voltage reference buffer ready  */
+#define VREFBUF_CSR_VRS_Pos         (4U)
+#define VREFBUF_CSR_VRS_Msk         (0x7UL << VREFBUF_CSR_VRS_Pos)             /*!< 0x00000070 */
+#define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */
+
+#define VREFBUF_CSR_VRS_OUT1        ((uint32_t)0x00000000)                     /*!<Voltage reference VREF_OUT1     */
+#define VREFBUF_CSR_VRS_OUT2_Pos    (4U)
+#define VREFBUF_CSR_VRS_OUT2_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)        /*!< 0x00000010 */
+#define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */
+#define VREFBUF_CSR_VRS_OUT3_Pos    (5U)
+#define VREFBUF_CSR_VRS_OUT3_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT3_Pos)        /*!< 0x00000020 */
+#define VREFBUF_CSR_VRS_OUT3        VREFBUF_CSR_VRS_OUT3_Msk                   /*!<Voltage reference VREF_OUT3     */
+#define VREFBUF_CSR_VRS_OUT4_Pos    (4U)
+#define VREFBUF_CSR_VRS_OUT4_Msk    (0x3UL << VREFBUF_CSR_VRS_OUT4_Pos)        /*!< 0x00000030 */
+#define VREFBUF_CSR_VRS_OUT4        VREFBUF_CSR_VRS_OUT4_Msk                   /*!<Voltage reference VREF_OUT4     */
+
+/*******************  Bit definition for VREFBUF_CCR register  ****************/
+#define VREFBUF_CCR_TRIM_Pos        (0U)
+#define VREFBUF_CCR_TRIM_Msk        (0x3FUL << VREFBUF_CCR_TRIM_Pos)           /*!< 0x0000003F */
+#define VREFBUF_CCR_TRIM            VREFBUF_CCR_TRIM_Msk                       /*!<TRIM[5:0] bits (Trimming code)  */
+
+/******************************************************************************/
+/*                                                                            */
+/*                 Flexible Datarate Controller Area Network                  */
+/*                                                                            */
+/******************************************************************************/
+/*!<FDCAN control and status registers */
+/*****************  Bit definition for FDCAN_CREL register  *******************/
+#define FDCAN_CREL_DAY_Pos        (0U)
+#define FDCAN_CREL_DAY_Msk        (0xFFUL << FDCAN_CREL_DAY_Pos)               /*!< 0x000000FF */
+#define FDCAN_CREL_DAY            FDCAN_CREL_DAY_Msk                           /*!<Timestamp Day                           */
+#define FDCAN_CREL_MON_Pos        (8U)
+#define FDCAN_CREL_MON_Msk        (0xFFUL << FDCAN_CREL_MON_Pos)               /*!< 0x0000FF00 */
+#define FDCAN_CREL_MON            FDCAN_CREL_MON_Msk                           /*!<Timestamp Month                         */
+#define FDCAN_CREL_YEAR_Pos       (16U)
+#define FDCAN_CREL_YEAR_Msk       (0xFUL << FDCAN_CREL_YEAR_Pos)               /*!< 0x000F0000 */
+#define FDCAN_CREL_YEAR           FDCAN_CREL_YEAR_Msk                          /*!<Timestamp Year                          */
+#define FDCAN_CREL_SUBSTEP_Pos    (20U)
+#define FDCAN_CREL_SUBSTEP_Msk    (0xFUL << FDCAN_CREL_SUBSTEP_Pos)            /*!< 0x00F00000 */
+#define FDCAN_CREL_SUBSTEP        FDCAN_CREL_SUBSTEP_Msk                       /*!<Sub-step of Core release                */
+#define FDCAN_CREL_STEP_Pos       (24U)
+#define FDCAN_CREL_STEP_Msk       (0xFUL << FDCAN_CREL_STEP_Pos)               /*!< 0x0F000000 */
+#define FDCAN_CREL_STEP           FDCAN_CREL_STEP_Msk                          /*!<Step of Core release                    */
+#define FDCAN_CREL_REL_Pos        (28U)
+#define FDCAN_CREL_REL_Msk        (0xFUL << FDCAN_CREL_REL_Pos)                /*!< 0xF0000000 */
+#define FDCAN_CREL_REL            FDCAN_CREL_REL_Msk                           /*!<Core release                            */
+
+/*****************  Bit definition for FDCAN_ENDN register  *******************/
+#define FDCAN_ENDN_ETV_Pos        (0U)
+#define FDCAN_ENDN_ETV_Msk        (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)         /*!< 0xFFFFFFFF */
+#define FDCAN_ENDN_ETV            FDCAN_ENDN_ETV_Msk                           /*!<Endiannes Test Value                    */
+
+/*****************  Bit definition for FDCAN_DBTP register  *******************/
+#define FDCAN_DBTP_DSJW_Pos       (0U)
+#define FDCAN_DBTP_DSJW_Msk       (0xFUL << FDCAN_DBTP_DSJW_Pos)               /*!< 0x0000000F */
+#define FDCAN_DBTP_DSJW           FDCAN_DBTP_DSJW_Msk                          /*!<Synchronization Jump Width              */
+#define FDCAN_DBTP_DTSEG2_Pos     (4U)
+#define FDCAN_DBTP_DTSEG2_Msk     (0xFUL << FDCAN_DBTP_DTSEG2_Pos)             /*!< 0x000000F0 */
+#define FDCAN_DBTP_DTSEG2         FDCAN_DBTP_DTSEG2_Msk                        /*!<Data time segment after sample point    */
+#define FDCAN_DBTP_DTSEG1_Pos     (8U)
+#define FDCAN_DBTP_DTSEG1_Msk     (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)            /*!< 0x00001F00 */
+#define FDCAN_DBTP_DTSEG1         FDCAN_DBTP_DTSEG1_Msk                        /*!<Data time segment before sample point   */
+#define FDCAN_DBTP_DBRP_Pos       (16U)
+#define FDCAN_DBTP_DBRP_Msk       (0x1FUL << FDCAN_DBTP_DBRP_Pos)              /*!< 0x001F0000 */
+#define FDCAN_DBTP_DBRP           FDCAN_DBTP_DBRP_Msk                          /*!<Data BIt Rate Prescaler                 */
+#define FDCAN_DBTP_TDC_Pos        (23U)
+#define FDCAN_DBTP_TDC_Msk        (0x1UL << FDCAN_DBTP_TDC_Pos)                /*!< 0x00800000 */
+#define FDCAN_DBTP_TDC            FDCAN_DBTP_TDC_Msk                           /*!<Transceiver Delay Compensation          */
+
+/*****************  Bit definition for FDCAN_TEST register  *******************/
+#define FDCAN_TEST_LBCK_Pos       (4U)
+#define FDCAN_TEST_LBCK_Msk       (0x1UL << FDCAN_TEST_LBCK_Pos)               /*!< 0x00000010 */
+#define FDCAN_TEST_LBCK           FDCAN_TEST_LBCK_Msk                          /*!<Loop Back mode                           */
+#define FDCAN_TEST_TX_Pos         (5U)
+#define FDCAN_TEST_TX_Msk         (0x3UL << FDCAN_TEST_TX_Pos)                 /*!< 0x00000060 */
+#define FDCAN_TEST_TX             FDCAN_TEST_TX_Msk                            /*!<Control of Transmit Pin                  */
+#define FDCAN_TEST_RX_Pos         (7U)
+#define FDCAN_TEST_RX_Msk         (0x1UL << FDCAN_TEST_RX_Pos)                 /*!< 0x00000080 */
+#define FDCAN_TEST_RX             FDCAN_TEST_RX_Msk                            /*!<Receive Pin                              */
+
+/*****************  Bit definition for FDCAN_RWD register  ********************/
+#define FDCAN_RWD_WDC_Pos         (0U)
+#define FDCAN_RWD_WDC_Msk         (0xFFUL << FDCAN_RWD_WDC_Pos)                /*!< 0x000000FF */
+#define FDCAN_RWD_WDC             FDCAN_RWD_WDC_Msk                            /*!<Watchdog configuration                   */
+#define FDCAN_RWD_WDV_Pos         (8U)
+#define FDCAN_RWD_WDV_Msk         (0xFFUL << FDCAN_RWD_WDV_Pos)                /*!< 0x0000FF00 */
+#define FDCAN_RWD_WDV             FDCAN_RWD_WDV_Msk                            /*!<Watchdog value                           */
+
+/*****************  Bit definition for FDCAN_CCCR register  ********************/
+#define FDCAN_CCCR_INIT_Pos       (0U)
+#define FDCAN_CCCR_INIT_Msk       (0x1UL << FDCAN_CCCR_INIT_Pos)               /*!< 0x00000001 */
+#define FDCAN_CCCR_INIT           FDCAN_CCCR_INIT_Msk                          /*!<Initialization                           */
+#define FDCAN_CCCR_CCE_Pos        (1U)
+#define FDCAN_CCCR_CCE_Msk        (0x1UL << FDCAN_CCCR_CCE_Pos)                /*!< 0x00000002 */
+#define FDCAN_CCCR_CCE            FDCAN_CCCR_CCE_Msk                           /*!<Configuration Change Enable              */
+#define FDCAN_CCCR_ASM_Pos        (2U)
+#define FDCAN_CCCR_ASM_Msk        (0x1UL << FDCAN_CCCR_ASM_Pos)                /*!< 0x00000004 */
+#define FDCAN_CCCR_ASM            FDCAN_CCCR_ASM_Msk                           /*!<ASM Restricted Operation Mode            */
+#define FDCAN_CCCR_CSA_Pos        (3U)
+#define FDCAN_CCCR_CSA_Msk        (0x1UL << FDCAN_CCCR_CSA_Pos)                /*!< 0x00000008 */
+#define FDCAN_CCCR_CSA            FDCAN_CCCR_CSA_Msk                           /*!<Clock Stop Acknowledge                   */
+#define FDCAN_CCCR_CSR_Pos        (4U)
+#define FDCAN_CCCR_CSR_Msk        (0x1UL << FDCAN_CCCR_CSR_Pos)                /*!< 0x00000010 */
+#define FDCAN_CCCR_CSR            FDCAN_CCCR_CSR_Msk                           /*!<Clock Stop Request                       */
+#define FDCAN_CCCR_MON_Pos        (5U)
+#define FDCAN_CCCR_MON_Msk        (0x1UL << FDCAN_CCCR_MON_Pos)                /*!< 0x00000020 */
+#define FDCAN_CCCR_MON            FDCAN_CCCR_MON_Msk                           /*!<Bus Monitoring Mode                      */
+#define FDCAN_CCCR_DAR_Pos        (6U)
+#define FDCAN_CCCR_DAR_Msk        (0x1UL << FDCAN_CCCR_DAR_Pos)                /*!< 0x00000040 */
+#define FDCAN_CCCR_DAR            FDCAN_CCCR_DAR_Msk                           /*!<Disable Automatic Retransmission         */
+#define FDCAN_CCCR_TEST_Pos       (7U)
+#define FDCAN_CCCR_TEST_Msk       (0x1UL << FDCAN_CCCR_TEST_Pos)               /*!< 0x00000080 */
+#define FDCAN_CCCR_TEST           FDCAN_CCCR_TEST_Msk                          /*!<Test Mode Enable                         */
+#define FDCAN_CCCR_FDOE_Pos       (8U)
+#define FDCAN_CCCR_FDOE_Msk       (0x1UL << FDCAN_CCCR_FDOE_Pos)               /*!< 0x00000100 */
+#define FDCAN_CCCR_FDOE           FDCAN_CCCR_FDOE_Msk                          /*!<FD Operation Enable                      */
+#define FDCAN_CCCR_BRSE_Pos       (9U)
+#define FDCAN_CCCR_BRSE_Msk       (0x1UL << FDCAN_CCCR_BRSE_Pos)               /*!< 0x00000200 */
+#define FDCAN_CCCR_BRSE           FDCAN_CCCR_BRSE_Msk                          /*!<FDCAN Bit Rate Switching                 */
+#define FDCAN_CCCR_PXHD_Pos       (12U)
+#define FDCAN_CCCR_PXHD_Msk       (0x1UL << FDCAN_CCCR_PXHD_Pos)               /*!< 0x00001000 */
+#define FDCAN_CCCR_PXHD           FDCAN_CCCR_PXHD_Msk                          /*!<Protocol Exception Handling Disable      */
+#define FDCAN_CCCR_EFBI_Pos       (13U)
+#define FDCAN_CCCR_EFBI_Msk       (0x1UL << FDCAN_CCCR_EFBI_Pos)               /*!< 0x00002000 */
+#define FDCAN_CCCR_EFBI           FDCAN_CCCR_EFBI_Msk                          /*!<Edge Filtering during Bus Integration    */
+#define FDCAN_CCCR_TXP_Pos        (14U)
+#define FDCAN_CCCR_TXP_Msk        (0x1UL << FDCAN_CCCR_TXP_Pos)                /*!< 0x00004000 */
+#define FDCAN_CCCR_TXP            FDCAN_CCCR_TXP_Msk                           /*!<Two CAN bit times Pause                  */
+#define FDCAN_CCCR_NISO_Pos       (15U)
+#define FDCAN_CCCR_NISO_Msk       (0x1UL << FDCAN_CCCR_NISO_Pos)               /*!< 0x00008000 */
+#define FDCAN_CCCR_NISO           FDCAN_CCCR_NISO_Msk                          /*!<Non ISO Operation                        */
+
+/*****************  Bit definition for FDCAN_NBTP register  ********************/
+#define FDCAN_NBTP_NTSEG2_Pos     (0U)
+#define FDCAN_NBTP_NTSEG2_Msk     (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)            /*!< 0x0000007F */
+#define FDCAN_NBTP_NTSEG2         FDCAN_NBTP_NTSEG2_Msk                        /*!<Nominal Time segment after sample point  */
+#define FDCAN_NBTP_NTSEG1_Pos     (8U)
+#define FDCAN_NBTP_NTSEG1_Msk     (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)            /*!< 0x0000FF00 */
+#define FDCAN_NBTP_NTSEG1         FDCAN_NBTP_NTSEG1_Msk                        /*!<Nominal Time segment before sample point */
+#define FDCAN_NBTP_NBRP_Pos       (16U)
+#define FDCAN_NBTP_NBRP_Msk       (0x1FFUL << FDCAN_NBTP_NBRP_Pos)             /*!< 0x01FF0000 */
+#define FDCAN_NBTP_NBRP           FDCAN_NBTP_NBRP_Msk                          /*!<Bit Rate Prescaler                       */
+#define FDCAN_NBTP_NSJW_Pos       (25U)
+#define FDCAN_NBTP_NSJW_Msk       (0x7FUL << FDCAN_NBTP_NSJW_Pos)              /*!< 0xFE000000 */
+#define FDCAN_NBTP_NSJW           FDCAN_NBTP_NSJW_Msk                          /*!<Nominal (Re)Synchronization Jump Width   */
+
+/*****************  Bit definition for FDCAN_TSCC register  ********************/
+#define FDCAN_TSCC_TSS_Pos        (0U)
+#define FDCAN_TSCC_TSS_Msk        (0x3UL << FDCAN_TSCC_TSS_Pos)                /*!< 0x00000003 */
+#define FDCAN_TSCC_TSS            FDCAN_TSCC_TSS_Msk                           /*!<Timestamp Select                         */
+#define FDCAN_TSCC_TCP_Pos        (16U)
+#define FDCAN_TSCC_TCP_Msk        (0xFUL << FDCAN_TSCC_TCP_Pos)                /*!< 0x000F0000 */
+#define FDCAN_TSCC_TCP            FDCAN_TSCC_TCP_Msk                           /*!<Timestamp Counter Prescaler              */
+
+/*****************  Bit definition for FDCAN_TSCV register  ********************/
+#define FDCAN_TSCV_TSC_Pos        (0U)
+#define FDCAN_TSCV_TSC_Msk        (0xFFFFUL << FDCAN_TSCV_TSC_Pos)             /*!< 0x0000FFFF */
+#define FDCAN_TSCV_TSC            FDCAN_TSCV_TSC_Msk                           /*!<Timestamp Counter                        */
+
+/*****************  Bit definition for FDCAN_TOCC register  ********************/
+#define FDCAN_TOCC_ETOC_Pos       (0U)
+#define FDCAN_TOCC_ETOC_Msk       (0x1UL << FDCAN_TOCC_ETOC_Pos)               /*!< 0x00000001 */
+#define FDCAN_TOCC_ETOC           FDCAN_TOCC_ETOC_Msk                          /*!<Enable Timeout Counter                   */
+#define FDCAN_TOCC_TOS_Pos        (1U)
+#define FDCAN_TOCC_TOS_Msk        (0x3UL << FDCAN_TOCC_TOS_Pos)                /*!< 0x00000006 */
+#define FDCAN_TOCC_TOS            FDCAN_TOCC_TOS_Msk                           /*!<Timeout Select                           */
+#define FDCAN_TOCC_TOP_Pos        (16U)
+#define FDCAN_TOCC_TOP_Msk        (0xFFFFUL << FDCAN_TOCC_TOP_Pos)             /*!< 0xFFFF0000 */
+#define FDCAN_TOCC_TOP            FDCAN_TOCC_TOP_Msk                           /*!<Timeout Period                           */
+
+/*****************  Bit definition for FDCAN_TOCV register  ********************/
+#define FDCAN_TOCV_TOC_Pos        (0U)
+#define FDCAN_TOCV_TOC_Msk        (0xFFFFUL << FDCAN_TOCV_TOC_Pos)             /*!< 0x0000FFFF */
+#define FDCAN_TOCV_TOC            FDCAN_TOCV_TOC_Msk                           /*!<Timeout Counter                          */
+
+/*****************  Bit definition for FDCAN_ECR register  *********************/
+#define FDCAN_ECR_TEC_Pos         (0U)
+#define FDCAN_ECR_TEC_Msk         (0xFUL << FDCAN_ECR_TEC_Pos)                 /*!< 0x0000000F */
+#define FDCAN_ECR_TEC             FDCAN_ECR_TEC_Msk                            /*!<Transmit Error Counter                   */
+#define FDCAN_ECR_REC_Pos         (8U)
+#define FDCAN_ECR_REC_Msk         (0x7FUL << FDCAN_ECR_REC_Pos)                /*!< 0x00007F00 */
+#define FDCAN_ECR_REC             FDCAN_ECR_REC_Msk                            /*!<Receive Error Counter                    */
+#define FDCAN_ECR_RP_Pos          (15U)
+#define FDCAN_ECR_RP_Msk          (0x1UL << FDCAN_ECR_RP_Pos)                  /*!< 0x00008000 */
+#define FDCAN_ECR_RP              FDCAN_ECR_RP_Msk                             /*!<Receive Error Passive                    */
+#define FDCAN_ECR_CEL_Pos         (16U)
+#define FDCAN_ECR_CEL_Msk         (0xFFUL << FDCAN_ECR_CEL_Pos)                /*!< 0x00FF0000 */
+#define FDCAN_ECR_CEL             FDCAN_ECR_CEL_Msk                            /*!<CAN Error Logging                        */
+
+/*****************  Bit definition for FDCAN_PSR register  *********************/
+#define FDCAN_PSR_LEC_Pos         (0U)
+#define FDCAN_PSR_LEC_Msk         (0x7UL << FDCAN_PSR_LEC_Pos)                 /*!< 0x00000007 */
+#define FDCAN_PSR_LEC             FDCAN_PSR_LEC_Msk                            /*!<Last Error Code                          */
+#define FDCAN_PSR_ACT_Pos         (3U)
+#define FDCAN_PSR_ACT_Msk         (0x3UL << FDCAN_PSR_ACT_Pos)                 /*!< 0x00000018 */
+#define FDCAN_PSR_ACT             FDCAN_PSR_ACT_Msk                            /*!<Activity                                 */
+#define FDCAN_PSR_EP_Pos          (5U)
+#define FDCAN_PSR_EP_Msk          (0x1UL << FDCAN_PSR_EP_Pos)                  /*!< 0x00000020 */
+#define FDCAN_PSR_EP              FDCAN_PSR_EP_Msk                             /*!<Error Passive                            */
+#define FDCAN_PSR_EW_Pos          (6U)
+#define FDCAN_PSR_EW_Msk          (0x1UL << FDCAN_PSR_EW_Pos)                  /*!< 0x00000040 */
+#define FDCAN_PSR_EW              FDCAN_PSR_EW_Msk                             /*!<Warning Status                           */
+#define FDCAN_PSR_BO_Pos          (7U)
+#define FDCAN_PSR_BO_Msk          (0x1UL << FDCAN_PSR_BO_Pos)                  /*!< 0x00000080 */
+#define FDCAN_PSR_BO              FDCAN_PSR_BO_Msk                             /*!<Bus_Off Status                           */
+#define FDCAN_PSR_DLEC_Pos        (8U)
+#define FDCAN_PSR_DLEC_Msk        (0x7UL << FDCAN_PSR_DLEC_Pos)                /*!< 0x00000700 */
+#define FDCAN_PSR_DLEC            FDCAN_PSR_DLEC_Msk                           /*!<Data Last Error Code                     */
+#define FDCAN_PSR_RESI_Pos        (11U)
+#define FDCAN_PSR_RESI_Msk        (0x1UL << FDCAN_PSR_RESI_Pos)                /*!< 0x00000800 */
+#define FDCAN_PSR_RESI            FDCAN_PSR_RESI_Msk                           /*!<ESI flag of last received FDCAN Message  */
+#define FDCAN_PSR_RBRS_Pos        (12U)
+#define FDCAN_PSR_RBRS_Msk        (0x1UL << FDCAN_PSR_RBRS_Pos)                /*!< 0x00001000 */
+#define FDCAN_PSR_RBRS            FDCAN_PSR_RBRS_Msk                           /*!<BRS flag of last received FDCAN Message  */
+#define FDCAN_PSR_REDL_Pos        (13U)
+#define FDCAN_PSR_REDL_Msk        (0x1UL << FDCAN_PSR_REDL_Pos)                /*!< 0x00002000 */
+#define FDCAN_PSR_REDL            FDCAN_PSR_REDL_Msk                           /*!<Received FDCAN Message                   */
+#define FDCAN_PSR_PXE_Pos         (14U)
+#define FDCAN_PSR_PXE_Msk         (0x1UL << FDCAN_PSR_PXE_Pos)                 /*!< 0x00004000 */
+#define FDCAN_PSR_PXE             FDCAN_PSR_PXE_Msk                            /*!<Protocol Exception Event                 */
+#define FDCAN_PSR_TDCV_Pos        (16U)
+#define FDCAN_PSR_TDCV_Msk        (0x7FUL << FDCAN_PSR_TDCV_Pos)               /*!< 0x007F0000 */
+#define FDCAN_PSR_TDCV            FDCAN_PSR_TDCV_Msk                           /*!<Transmitter Delay Compensation Value     */
+
+/*****************  Bit definition for FDCAN_TDCR register  ********************/
+#define FDCAN_TDCR_TDCF_Pos       (0U)
+#define FDCAN_TDCR_TDCF_Msk       (0x7FUL << FDCAN_TDCR_TDCF_Pos)              /*!< 0x0000007F */
+#define FDCAN_TDCR_TDCF           FDCAN_TDCR_TDCF_Msk                          /*!<Transmitter Delay Compensation Filter    */
+#define FDCAN_TDCR_TDCO_Pos       (8U)
+#define FDCAN_TDCR_TDCO_Msk       (0x7FUL << FDCAN_TDCR_TDCO_Pos)              /*!< 0x00007F00 */
+#define FDCAN_TDCR_TDCO           FDCAN_TDCR_TDCO_Msk                          /*!<Transmitter Delay Compensation Offset    */
+
+/*****************  Bit definition for FDCAN_IR register  **********************/
+#define FDCAN_IR_RF0N_Pos         (0U)
+#define FDCAN_IR_RF0N_Msk         (0x1UL << FDCAN_IR_RF0N_Pos)                 /*!< 0x00000001 */
+#define FDCAN_IR_RF0N             FDCAN_IR_RF0N_Msk                            /*!<Rx FIFO 0 New Message                    */
+#define FDCAN_IR_RF0W_Pos         (1U)
+#define FDCAN_IR_RF0W_Msk         (0x1UL << FDCAN_IR_RF0W_Pos)                 /*!< 0x00000002 */
+#define FDCAN_IR_RF0W             FDCAN_IR_RF0W_Msk                            /*!<Rx FIFO 0 Watermark Reached              */
+#define FDCAN_IR_RF0F_Pos         (2U)
+#define FDCAN_IR_RF0F_Msk         (0x1UL << FDCAN_IR_RF0F_Pos)                 /*!< 0x00000004 */
+#define FDCAN_IR_RF0F             FDCAN_IR_RF0F_Msk                            /*!<Rx FIFO 0 Full                           */
+#define FDCAN_IR_RF0L_Pos         (3U)
+#define FDCAN_IR_RF0L_Msk         (0x1UL << FDCAN_IR_RF0L_Pos)                 /*!< 0x00000008 */
+#define FDCAN_IR_RF0L             FDCAN_IR_RF0L_Msk                            /*!<Rx FIFO 0 Message Lost                   */
+#define FDCAN_IR_RF1N_Pos         (4U)
+#define FDCAN_IR_RF1N_Msk         (0x1UL << FDCAN_IR_RF1N_Pos)                 /*!< 0x00000010 */
+#define FDCAN_IR_RF1N             FDCAN_IR_RF1N_Msk                            /*!<Rx FIFO 1 New Message                    */
+#define FDCAN_IR_RF1W_Pos         (5U)
+#define FDCAN_IR_RF1W_Msk         (0x1UL << FDCAN_IR_RF1W_Pos)                 /*!< 0x00000020 */
+#define FDCAN_IR_RF1W             FDCAN_IR_RF1W_Msk                            /*!<Rx FIFO 1 Watermark Reached              */
+#define FDCAN_IR_RF1F_Pos         (6U)
+#define FDCAN_IR_RF1F_Msk         (0x1UL << FDCAN_IR_RF1F_Pos)                 /*!< 0x00000040 */
+#define FDCAN_IR_RF1F             FDCAN_IR_RF1F_Msk                            /*!<Rx FIFO 1 Full                           */
+#define FDCAN_IR_RF1L_Pos         (7U)
+#define FDCAN_IR_RF1L_Msk         (0x1UL << FDCAN_IR_RF1L_Pos)                 /*!< 0x00000080 */
+#define FDCAN_IR_RF1L             FDCAN_IR_RF1L_Msk                            /*!<Rx FIFO 1 Message Lost                   */
+#define FDCAN_IR_HPM_Pos          (8U)
+#define FDCAN_IR_HPM_Msk          (0x1UL << FDCAN_IR_HPM_Pos)                  /*!< 0x00000100 */
+#define FDCAN_IR_HPM              FDCAN_IR_HPM_Msk                             /*!<High Priority Message                    */
+#define FDCAN_IR_TC_Pos           (9U)
+#define FDCAN_IR_TC_Msk           (0x1UL << FDCAN_IR_TC_Pos)                   /*!< 0x00000200 */
+#define FDCAN_IR_TC               FDCAN_IR_TC_Msk                              /*!<Transmission Completed                   */
+#define FDCAN_IR_TCF_Pos          (10U)
+#define FDCAN_IR_TCF_Msk          (0x1UL << FDCAN_IR_TCF_Pos)                  /*!< 0x00000400 */
+#define FDCAN_IR_TCF              FDCAN_IR_TCF_Msk                             /*!<Transmission Cancellation Finished       */
+#define FDCAN_IR_TFE_Pos          (11U)
+#define FDCAN_IR_TFE_Msk          (0x1UL << FDCAN_IR_TFE_Pos)                  /*!< 0x00000800 */
+#define FDCAN_IR_TFE              FDCAN_IR_TFE_Msk                             /*!<Tx FIFO Empty                            */
+#define FDCAN_IR_TEFN_Pos         (12U)
+#define FDCAN_IR_TEFN_Msk         (0x1UL << FDCAN_IR_TEFN_Pos)                 /*!< 0x00001000 */
+#define FDCAN_IR_TEFN             FDCAN_IR_TEFN_Msk                            /*!<Tx Event FIFO New Entry                  */
+#define FDCAN_IR_TEFW_Pos         (13U)
+#define FDCAN_IR_TEFW_Msk         (0x1UL << FDCAN_IR_TEFW_Pos)                 /*!< 0x00002000 */
+#define FDCAN_IR_TEFW             FDCAN_IR_TEFW_Msk                            /*!<Tx Event FIFO Watermark Reached          */
+#define FDCAN_IR_TEFF_Pos         (14U)
+#define FDCAN_IR_TEFF_Msk         (0x1UL << FDCAN_IR_TEFF_Pos)                 /*!< 0x00004000 */
+#define FDCAN_IR_TEFF             FDCAN_IR_TEFF_Msk                            /*!<Tx Event FIFO Full                       */
+#define FDCAN_IR_TEFL_Pos         (15U)
+#define FDCAN_IR_TEFL_Msk         (0x1UL << FDCAN_IR_TEFL_Pos)                 /*!< 0x00008000 */
+#define FDCAN_IR_TEFL             FDCAN_IR_TEFL_Msk                            /*!<Tx Event FIFO Element Lost               */
+#define FDCAN_IR_TSW_Pos          (16U)
+#define FDCAN_IR_TSW_Msk          (0x1UL << FDCAN_IR_TSW_Pos)                  /*!< 0x00010000 */
+#define FDCAN_IR_TSW              FDCAN_IR_TSW_Msk                             /*!<Timestamp Wraparound                     */
+#define FDCAN_IR_MRAF_Pos         (17U)
+#define FDCAN_IR_MRAF_Msk         (0x1UL << FDCAN_IR_MRAF_Pos)                 /*!< 0x00020000 */
+#define FDCAN_IR_MRAF             FDCAN_IR_MRAF_Msk                            /*!<Message RAM Access Failure               */
+#define FDCAN_IR_TOO_Pos          (18U)
+#define FDCAN_IR_TOO_Msk          (0x1UL << FDCAN_IR_TOO_Pos)                  /*!< 0x00040000 */
+#define FDCAN_IR_TOO              FDCAN_IR_TOO_Msk                             /*!<Timeout Occurred                         */
+#define FDCAN_IR_DRX_Pos          (19U)
+#define FDCAN_IR_DRX_Msk          (0x1UL << FDCAN_IR_DRX_Pos)                  /*!< 0x00080000 */
+#define FDCAN_IR_DRX              FDCAN_IR_DRX_Msk                             /*!<Message stored to Dedicated Rx Buffer    */
+#define FDCAN_IR_ELO_Pos          (22U)
+#define FDCAN_IR_ELO_Msk          (0x1UL << FDCAN_IR_ELO_Pos)                  /*!< 0x00400000 */
+#define FDCAN_IR_ELO              FDCAN_IR_ELO_Msk                             /*!<Error Logging Overflow                   */
+#define FDCAN_IR_EP_Pos           (23U)
+#define FDCAN_IR_EP_Msk           (0x1UL << FDCAN_IR_EP_Pos)                   /*!< 0x00800000 */
+#define FDCAN_IR_EP               FDCAN_IR_EP_Msk                              /*!<Error Passive                            */
+#define FDCAN_IR_EW_Pos           (24U)
+#define FDCAN_IR_EW_Msk           (0x1UL << FDCAN_IR_EW_Pos)                   /*!< 0x01000000 */
+#define FDCAN_IR_EW               FDCAN_IR_EW_Msk                              /*!<Warning Status                           */
+#define FDCAN_IR_BO_Pos           (25U)
+#define FDCAN_IR_BO_Msk           (0x1UL << FDCAN_IR_BO_Pos)                   /*!< 0x02000000 */
+#define FDCAN_IR_BO               FDCAN_IR_BO_Msk                              /*!<Bus_Off Status                           */
+#define FDCAN_IR_WDI_Pos          (26U)
+#define FDCAN_IR_WDI_Msk          (0x1UL << FDCAN_IR_WDI_Pos)                  /*!< 0x04000000 */
+#define FDCAN_IR_WDI              FDCAN_IR_WDI_Msk                             /*!<Watchdog Interrupt                       */
+#define FDCAN_IR_PEA_Pos          (27U)
+#define FDCAN_IR_PEA_Msk          (0x1UL << FDCAN_IR_PEA_Pos)                  /*!< 0x08000000 */
+#define FDCAN_IR_PEA              FDCAN_IR_PEA_Msk                             /*!<Protocol Error in Arbitration Phase      */
+#define FDCAN_IR_PED_Pos          (28U)
+#define FDCAN_IR_PED_Msk          (0x1UL << FDCAN_IR_PED_Pos)                  /*!< 0x10000000 */
+#define FDCAN_IR_PED              FDCAN_IR_PED_Msk                             /*!<Protocol Error in Data Phase             */
+#define FDCAN_IR_ARA_Pos          (29U)
+#define FDCAN_IR_ARA_Msk          (0x1UL << FDCAN_IR_ARA_Pos)                  /*!< 0x20000000 */
+#define FDCAN_IR_ARA              FDCAN_IR_ARA_Msk                             /*!<Access to Reserved Address               */
+
+/*****************  Bit definition for FDCAN_IE register  **********************/
+#define FDCAN_IE_RF0NE_Pos        (0U)
+#define FDCAN_IE_RF0NE_Msk        (0x1UL << FDCAN_IE_RF0NE_Pos)                /*!< 0x00000001 */
+#define FDCAN_IE_RF0NE            FDCAN_IE_RF0NE_Msk                           /*!<Rx FIFO 0 New Message Enable                 */
+#define FDCAN_IE_RF0WE_Pos        (1U)
+#define FDCAN_IE_RF0WE_Msk        (0x1UL << FDCAN_IE_RF0WE_Pos)                /*!< 0x00000002 */
+#define FDCAN_IE_RF0WE            FDCAN_IE_RF0WE_Msk                           /*!<Rx FIFO 0 Watermark Reached Enable           */
+#define FDCAN_IE_RF0FE_Pos        (2U)
+#define FDCAN_IE_RF0FE_Msk        (0x1UL << FDCAN_IE_RF0FE_Pos)                /*!< 0x00000004 */
+#define FDCAN_IE_RF0FE            FDCAN_IE_RF0FE_Msk                           /*!<Rx FIFO 0 Full Enable                        */
+#define FDCAN_IE_RF0LE_Pos        (3U)
+#define FDCAN_IE_RF0LE_Msk        (0x1UL << FDCAN_IE_RF0LE_Pos)                /*!< 0x00000008 */
+#define FDCAN_IE_RF0LE            FDCAN_IE_RF0LE_Msk                           /*!<Rx FIFO 0 Message Lost Enable                */
+#define FDCAN_IE_RF1NE_Pos        (4U)
+#define FDCAN_IE_RF1NE_Msk        (0x1UL << FDCAN_IE_RF1NE_Pos)                /*!< 0x00000010 */
+#define FDCAN_IE_RF1NE            FDCAN_IE_RF1NE_Msk                           /*!<Rx FIFO 1 New Message Enable                 */
+#define FDCAN_IE_RF1WE_Pos        (5U)
+#define FDCAN_IE_RF1WE_Msk        (0x1UL << FDCAN_IE_RF1WE_Pos)                /*!< 0x00000020 */
+#define FDCAN_IE_RF1WE            FDCAN_IE_RF1WE_Msk                           /*!<Rx FIFO 1 Watermark Reached Enable           */
+#define FDCAN_IE_RF1FE_Pos        (6U)
+#define FDCAN_IE_RF1FE_Msk        (0x1UL << FDCAN_IE_RF1FE_Pos)                /*!< 0x00000040 */
+#define FDCAN_IE_RF1FE            FDCAN_IE_RF1FE_Msk                           /*!<Rx FIFO 1 Full Enable                        */
+#define FDCAN_IE_RF1LE_Pos        (7U)
+#define FDCAN_IE_RF1LE_Msk        (0x1UL << FDCAN_IE_RF1LE_Pos)                /*!< 0x00000080 */
+#define FDCAN_IE_RF1LE            FDCAN_IE_RF1LE_Msk                           /*!<Rx FIFO 1 Message Lost Enable                */
+#define FDCAN_IE_HPME_Pos         (8U)
+#define FDCAN_IE_HPME_Msk         (0x1UL << FDCAN_IE_HPME_Pos)                 /*!< 0x00000100 */
+#define FDCAN_IE_HPME             FDCAN_IE_HPME_Msk                            /*!<High Priority Message Enable                 */
+#define FDCAN_IE_TCE_Pos          (9U)
+#define FDCAN_IE_TCE_Msk          (0x1UL << FDCAN_IE_TCE_Pos)                  /*!< 0x00000200 */
+#define FDCAN_IE_TCE              FDCAN_IE_TCE_Msk                             /*!<Transmission Completed Enable                */
+#define FDCAN_IE_TCFE_Pos         (10U)
+#define FDCAN_IE_TCFE_Msk         (0x1UL << FDCAN_IE_TCFE_Pos)                 /*!< 0x00000400 */
+#define FDCAN_IE_TCFE             FDCAN_IE_TCFE_Msk                            /*!<Transmission Cancellation Finished Enable    */
+#define FDCAN_IE_TFEE_Pos         (11U)
+#define FDCAN_IE_TFEE_Msk         (0x1UL << FDCAN_IE_TFEE_Pos)                 /*!< 0x00000800 */
+#define FDCAN_IE_TFEE             FDCAN_IE_TFEE_Msk                            /*!<Tx FIFO Empty Enable                         */
+#define FDCAN_IE_TEFNE_Pos        (12U)
+#define FDCAN_IE_TEFNE_Msk        (0x1UL << FDCAN_IE_TEFNE_Pos)                /*!< 0x00001000 */
+#define FDCAN_IE_TEFNE            FDCAN_IE_TEFNE_Msk                           /*!<Tx Event FIFO New Entry Enable               */
+#define FDCAN_IE_TEFWE_Pos        (13U)
+#define FDCAN_IE_TEFWE_Msk        (0x1UL << FDCAN_IE_TEFWE_Pos)                /*!< 0x00002000 */
+#define FDCAN_IE_TEFWE            FDCAN_IE_TEFWE_Msk                           /*!<Tx Event FIFO Watermark Reached Enable       */
+#define FDCAN_IE_TEFFE_Pos        (14U)
+#define FDCAN_IE_TEFFE_Msk        (0x1UL << FDCAN_IE_TEFFE_Pos)                /*!< 0x00004000 */
+#define FDCAN_IE_TEFFE            FDCAN_IE_TEFFE_Msk                           /*!<Tx Event FIFO Full Enable                    */
+#define FDCAN_IE_TEFLE_Pos        (15U)
+#define FDCAN_IE_TEFLE_Msk        (0x1UL << FDCAN_IE_TEFLE_Pos)                /*!< 0x00008000 */
+#define FDCAN_IE_TEFLE            FDCAN_IE_TEFLE_Msk                           /*!<Tx Event FIFO Element Lost Enable            */
+#define FDCAN_IE_TSWE_Pos         (16U)
+#define FDCAN_IE_TSWE_Msk         (0x1UL << FDCAN_IE_TSWE_Pos)                 /*!< 0x00010000 */
+#define FDCAN_IE_TSWE             FDCAN_IE_TSWE_Msk                            /*!<Timestamp Wraparound Enable                  */
+#define FDCAN_IE_MRAFE_Pos        (17U)
+#define FDCAN_IE_MRAFE_Msk        (0x1UL << FDCAN_IE_MRAFE_Pos)                /*!< 0x00020000 */
+#define FDCAN_IE_MRAFE            FDCAN_IE_MRAFE_Msk                           /*!<Message RAM Access Failure Enable            */
+#define FDCAN_IE_TOOE_Pos         (18U)
+#define FDCAN_IE_TOOE_Msk         (0x1UL << FDCAN_IE_TOOE_Pos)                 /*!< 0x00040000 */
+#define FDCAN_IE_TOOE             FDCAN_IE_TOOE_Msk                            /*!<Timeout Occurred Enable                      */
+#define FDCAN_IE_DRXE_Pos         (19U)
+#define FDCAN_IE_DRXE_Msk         (0x1UL << FDCAN_IE_DRXE_Pos)                 /*!< 0x00080000 */
+#define FDCAN_IE_DRXE             FDCAN_IE_DRXE_Msk                            /*!<Message stored to Dedicated Rx Buffer Enable */
+#define FDCAN_IE_BECE_Pos         (20U)
+#define FDCAN_IE_BECE_Msk         (0x1UL << FDCAN_IE_BECE_Pos)                 /*!< 0x00100000 */
+#define FDCAN_IE_BECE             FDCAN_IE_BECE_Msk                            /*!<Bit Error Corrected Interrupt Enable         */
+#define FDCAN_IE_BEUE_Pos         (21U)
+#define FDCAN_IE_BEUE_Msk         (0x1UL << FDCAN_IE_BEUE_Pos)                 /*!< 0x00200000 */
+#define FDCAN_IE_BEUE             FDCAN_IE_BEUE_Msk                            /*!<Bit Error Uncorrected Interrupt Enable       */
+#define FDCAN_IE_ELOE_Pos         (22U)
+#define FDCAN_IE_ELOE_Msk         (0x1UL << FDCAN_IE_ELOE_Pos)                 /*!< 0x00400000 */
+#define FDCAN_IE_ELOE             FDCAN_IE_ELOE_Msk                            /*!<Error Logging Overflow Enable                */
+#define FDCAN_IE_EPE_Pos          (23U)
+#define FDCAN_IE_EPE_Msk          (0x1UL << FDCAN_IE_EPE_Pos)                  /*!< 0x00800000 */
+#define FDCAN_IE_EPE              FDCAN_IE_EPE_Msk                             /*!<Error Passive Enable                         */
+#define FDCAN_IE_EWE_Pos          (24U)
+#define FDCAN_IE_EWE_Msk          (0x1UL << FDCAN_IE_EWE_Pos)                  /*!< 0x01000000 */
+#define FDCAN_IE_EWE              FDCAN_IE_EWE_Msk                             /*!<Warning Status Enable                        */
+#define FDCAN_IE_BOE_Pos          (25U)
+#define FDCAN_IE_BOE_Msk          (0x1UL << FDCAN_IE_BOE_Pos)                  /*!< 0x02000000 */
+#define FDCAN_IE_BOE              FDCAN_IE_BOE_Msk                             /*!<Bus_Off Status Enable                        */
+#define FDCAN_IE_WDIE_Pos         (26U)
+#define FDCAN_IE_WDIE_Msk         (0x1UL << FDCAN_IE_WDIE_Pos)                 /*!< 0x04000000 */
+#define FDCAN_IE_WDIE             FDCAN_IE_WDIE_Msk                            /*!<Watchdog Interrupt Enable                    */
+#define FDCAN_IE_PEAE_Pos         (27U)
+#define FDCAN_IE_PEAE_Msk         (0x1UL << FDCAN_IE_PEAE_Pos)                 /*!< 0x08000000 */
+#define FDCAN_IE_PEAE             FDCAN_IE_PEAE_Msk                            /*!<Protocol Error in Arbitration Phase Enable   */
+#define FDCAN_IE_PEDE_Pos         (28U)
+#define FDCAN_IE_PEDE_Msk         (0x1UL << FDCAN_IE_PEDE_Pos)                 /*!< 0x10000000 */
+#define FDCAN_IE_PEDE             FDCAN_IE_PEDE_Msk                            /*!<Protocol Error in Data Phase Enable          */
+#define FDCAN_IE_ARAE_Pos         (29U)
+#define FDCAN_IE_ARAE_Msk         (0x1UL << FDCAN_IE_ARAE_Pos)                 /*!< 0x20000000 */
+#define FDCAN_IE_ARAE             FDCAN_IE_ARAE_Msk                            /*!<Access to Reserved Address Enable            */
+
+/*****************  Bit definition for FDCAN_ILS register  **********************/
+#define FDCAN_ILS_RF0NL_Pos       (0U)
+#define FDCAN_ILS_RF0NL_Msk       (0x1UL << FDCAN_ILS_RF0NL_Pos)               /*!< 0x00000001 */
+#define FDCAN_ILS_RF0NL           FDCAN_ILS_RF0NL_Msk                          /*!<Rx FIFO 0 New Message Line                  */
+#define FDCAN_ILS_RF0WL_Pos       (1U)
+#define FDCAN_ILS_RF0WL_Msk       (0x1UL << FDCAN_ILS_RF0WL_Pos)               /*!< 0x00000002 */
+#define FDCAN_ILS_RF0WL           FDCAN_ILS_RF0WL_Msk                          /*!<Rx FIFO 0 Watermark Reached Line            */
+#define FDCAN_ILS_RF0FL_Pos       (2U)
+#define FDCAN_ILS_RF0FL_Msk       (0x1UL << FDCAN_ILS_RF0FL_Pos)               /*!< 0x00000004 */
+#define FDCAN_ILS_RF0FL           FDCAN_ILS_RF0FL_Msk                          /*!<Rx FIFO 0 Full Line                         */
+#define FDCAN_ILS_RF0LL_Pos       (3U)
+#define FDCAN_ILS_RF0LL_Msk       (0x1UL << FDCAN_ILS_RF0LL_Pos)               /*!< 0x00000008 */
+#define FDCAN_ILS_RF0LL           FDCAN_ILS_RF0LL_Msk                          /*!<Rx FIFO 0 Message Lost Line                 */
+#define FDCAN_ILS_RF1NL_Pos       (4U)
+#define FDCAN_ILS_RF1NL_Msk       (0x1UL << FDCAN_ILS_RF1NL_Pos)               /*!< 0x00000010 */
+#define FDCAN_ILS_RF1NL           FDCAN_ILS_RF1NL_Msk                          /*!<Rx FIFO 1 New Message Line                  */
+#define FDCAN_ILS_RF1WL_Pos       (5U)
+#define FDCAN_ILS_RF1WL_Msk       (0x1UL << FDCAN_ILS_RF1WL_Pos)               /*!< 0x00000020 */
+#define FDCAN_ILS_RF1WL           FDCAN_ILS_RF1WL_Msk                          /*!<Rx FIFO 1 Watermark Reached Line            */
+#define FDCAN_ILS_RF1FL_Pos       (6U)
+#define FDCAN_ILS_RF1FL_Msk       (0x1UL << FDCAN_ILS_RF1FL_Pos)               /*!< 0x00000040 */
+#define FDCAN_ILS_RF1FL           FDCAN_ILS_RF1FL_Msk                          /*!<Rx FIFO 1 Full Line                         */
+#define FDCAN_ILS_RF1LL_Pos       (7U)
+#define FDCAN_ILS_RF1LL_Msk       (0x1UL << FDCAN_ILS_RF1LL_Pos)               /*!< 0x00000080 */
+#define FDCAN_ILS_RF1LL           FDCAN_ILS_RF1LL_Msk                          /*!<Rx FIFO 1 Message Lost Line                 */
+#define FDCAN_ILS_HPML_Pos        (8U)
+#define FDCAN_ILS_HPML_Msk        (0x1UL << FDCAN_ILS_HPML_Pos)                /*!< 0x00000100 */
+#define FDCAN_ILS_HPML            FDCAN_ILS_HPML_Msk                           /*!<High Priority Message Line                  */
+#define FDCAN_ILS_TCL_Pos         (9U)
+#define FDCAN_ILS_TCL_Msk         (0x1UL << FDCAN_ILS_TCL_Pos)                 /*!< 0x00000200 */
+#define FDCAN_ILS_TCL             FDCAN_ILS_TCL_Msk                            /*!<Transmission Completed Line                 */
+#define FDCAN_ILS_TCFL_Pos        (10U)
+#define FDCAN_ILS_TCFL_Msk        (0x1UL << FDCAN_ILS_TCFL_Pos)                /*!< 0x00000400 */
+#define FDCAN_ILS_TCFL            FDCAN_ILS_TCFL_Msk                           /*!<Transmission Cancellation Finished Line     */
+#define FDCAN_ILS_TFEL_Pos        (11U)
+#define FDCAN_ILS_TFEL_Msk        (0x1UL << FDCAN_ILS_TFEL_Pos)                /*!< 0x00000800 */
+#define FDCAN_ILS_TFEL            FDCAN_ILS_TFEL_Msk                           /*!<Tx FIFO Empty Line                          */
+#define FDCAN_ILS_TEFNL_Pos       (12U)
+#define FDCAN_ILS_TEFNL_Msk       (0x1UL << FDCAN_ILS_TEFNL_Pos)               /*!< 0x00001000 */
+#define FDCAN_ILS_TEFNL           FDCAN_ILS_TEFNL_Msk                          /*!<Tx Event FIFO New Entry Line                */
+#define FDCAN_ILS_TEFWL_Pos       (13U)
+#define FDCAN_ILS_TEFWL_Msk       (0x1UL << FDCAN_ILS_TEFWL_Pos)               /*!< 0x00002000 */
+#define FDCAN_ILS_TEFWL           FDCAN_ILS_TEFWL_Msk                          /*!<Tx Event FIFO Watermark Reached Line        */
+#define FDCAN_ILS_TEFFL_Pos       (14U)
+#define FDCAN_ILS_TEFFL_Msk       (0x1UL << FDCAN_ILS_TEFFL_Pos)               /*!< 0x00004000 */
+#define FDCAN_ILS_TEFFL           FDCAN_ILS_TEFFL_Msk                          /*!<Tx Event FIFO Full Line                     */
+#define FDCAN_ILS_TEFLL_Pos       (15U)
+#define FDCAN_ILS_TEFLL_Msk       (0x1UL << FDCAN_ILS_TEFLL_Pos)               /*!< 0x00008000 */
+#define FDCAN_ILS_TEFLL           FDCAN_ILS_TEFLL_Msk                          /*!<Tx Event FIFO Element Lost Line             */
+#define FDCAN_ILS_TSWL_Pos        (16U)
+#define FDCAN_ILS_TSWL_Msk        (0x1UL << FDCAN_ILS_TSWL_Pos)                /*!< 0x00010000 */
+#define FDCAN_ILS_TSWL            FDCAN_ILS_TSWL_Msk                           /*!<Timestamp Wraparound Line                   */
+#define FDCAN_ILS_MRAFE_Pos       (17U)
+#define FDCAN_ILS_MRAFE_Msk       (0x1UL << FDCAN_ILS_MRAFE_Pos)               /*!< 0x00020000 */
+#define FDCAN_ILS_MRAFE           FDCAN_ILS_MRAFE_Msk                          /*!<Message RAM Access Failure Line             */
+#define FDCAN_ILS_TOOE_Pos        (18U)
+#define FDCAN_ILS_TOOE_Msk        (0x1UL << FDCAN_ILS_TOOE_Pos)                /*!< 0x00040000 */
+#define FDCAN_ILS_TOOE            FDCAN_ILS_TOOE_Msk                           /*!<Timeout Occurred Line                       */
+#define FDCAN_ILS_DRXE_Pos        (19U)
+#define FDCAN_ILS_DRXE_Msk        (0x1UL << FDCAN_ILS_DRXE_Pos)                /*!< 0x00080000 */
+#define FDCAN_ILS_DRXE            FDCAN_ILS_DRXE_Msk                           /*!<Message stored to Dedicated Rx Buffer Line  */
+#define FDCAN_ILS_BECE_Pos        (20U)
+#define FDCAN_ILS_BECE_Msk        (0x1UL << FDCAN_ILS_BECE_Pos)                /*!< 0x00100000 */
+#define FDCAN_ILS_BECE            FDCAN_ILS_BECE_Msk                           /*!<Bit Error Corrected Interrupt Line          */
+#define FDCAN_ILS_BEUE_Pos        (21U)
+#define FDCAN_ILS_BEUE_Msk        (0x1UL << FDCAN_ILS_BEUE_Pos)                /*!< 0x00200000 */
+#define FDCAN_ILS_BEUE            FDCAN_ILS_BEUE_Msk                           /*!<Bit Error Uncorrected Interrupt Line        */
+#define FDCAN_ILS_ELOE_Pos        (22U)
+#define FDCAN_ILS_ELOE_Msk        (0x1UL << FDCAN_ILS_ELOE_Pos)                /*!< 0x00400000 */
+#define FDCAN_ILS_ELOE            FDCAN_ILS_ELOE_Msk                           /*!<Error Logging Overflow Line                 */
+#define FDCAN_ILS_EPE_Pos         (23U)
+#define FDCAN_ILS_EPE_Msk         (0x1UL << FDCAN_ILS_EPE_Pos)                 /*!< 0x00800000 */
+#define FDCAN_ILS_EPE             FDCAN_ILS_EPE_Msk                            /*!<Error Passive Line                          */
+#define FDCAN_ILS_EWE_Pos         (24U)
+#define FDCAN_ILS_EWE_Msk         (0x1UL << FDCAN_ILS_EWE_Pos)                 /*!< 0x01000000 */
+#define FDCAN_ILS_EWE             FDCAN_ILS_EWE_Msk                            /*!<Warning Status Line                         */
+#define FDCAN_ILS_BOE_Pos         (25U)
+#define FDCAN_ILS_BOE_Msk         (0x1UL << FDCAN_ILS_BOE_Pos)                 /*!< 0x02000000 */
+#define FDCAN_ILS_BOE             FDCAN_ILS_BOE_Msk                            /*!<Bus_Off Status Line                         */
+#define FDCAN_ILS_WDIE_Pos        (26U)
+#define FDCAN_ILS_WDIE_Msk        (0x1UL << FDCAN_ILS_WDIE_Pos)                /*!< 0x04000000 */
+#define FDCAN_ILS_WDIE            FDCAN_ILS_WDIE_Msk                           /*!<Watchdog Interrupt Line                     */
+#define FDCAN_ILS_PEAE_Pos        (27U)
+#define FDCAN_ILS_PEAE_Msk        (0x1UL << FDCAN_ILS_PEAE_Pos)                /*!< 0x08000000 */
+#define FDCAN_ILS_PEAE            FDCAN_ILS_PEAE_Msk                           /*!<Protocol Error in Arbitration Phase Line    */
+#define FDCAN_ILS_PEDE_Pos        (28U)
+#define FDCAN_ILS_PEDE_Msk        (0x1UL << FDCAN_ILS_PEDE_Pos)                /*!< 0x10000000 */
+#define FDCAN_ILS_PEDE            FDCAN_ILS_PEDE_Msk                           /*!<Protocol Error in Data Phase Line           */
+#define FDCAN_ILS_ARAE_Pos        (29U)
+#define FDCAN_ILS_ARAE_Msk        (0x1UL << FDCAN_ILS_ARAE_Pos)                /*!< 0x20000000 */
+#define FDCAN_ILS_ARAE            FDCAN_ILS_ARAE_Msk                           /*!<Access to Reserved Address Line             */
+
+/*****************  Bit definition for FDCAN_ILE register  **********************/
+#define FDCAN_ILE_EINT0_Pos       (0U)
+#define FDCAN_ILE_EINT0_Msk       (0x1UL << FDCAN_ILE_EINT0_Pos)               /*!< 0x00000001 */
+#define FDCAN_ILE_EINT0           FDCAN_ILE_EINT0_Msk                          /*!<Enable Interrupt Line 0                   */
+#define FDCAN_ILE_EINT1_Pos       (1U)
+#define FDCAN_ILE_EINT1_Msk       (0x1UL << FDCAN_ILE_EINT1_Pos)               /*!< 0x00000002 */
+#define FDCAN_ILE_EINT1           FDCAN_ILE_EINT1_Msk                          /*!<Enable Interrupt Line 1                   */
+
+/*****************  Bit definition for FDCAN_GFC register  **********************/
+#define FDCAN_GFC_RRFE_Pos        (0U)
+#define FDCAN_GFC_RRFE_Msk        (0x1UL << FDCAN_GFC_RRFE_Pos)                /*!< 0x00000001 */
+#define FDCAN_GFC_RRFE            FDCAN_GFC_RRFE_Msk                           /*!<Reject Remote Frames Extended             */
+#define FDCAN_GFC_RRFS_Pos        (1U)
+#define FDCAN_GFC_RRFS_Msk        (0x1UL << FDCAN_GFC_RRFS_Pos)                /*!< 0x00000002 */
+#define FDCAN_GFC_RRFS            FDCAN_GFC_RRFS_Msk                           /*!<Reject Remote Frames Standard             */
+#define FDCAN_GFC_ANFE_Pos        (2U)
+#define FDCAN_GFC_ANFE_Msk        (0x3UL << FDCAN_GFC_ANFE_Pos)                /*!< 0x0000000C */
+#define FDCAN_GFC_ANFE            FDCAN_GFC_ANFE_Msk                           /*!<Accept Non-matching Frames Extended       */
+#define FDCAN_GFC_ANFS_Pos        (4U)
+#define FDCAN_GFC_ANFS_Msk        (0x3UL << FDCAN_GFC_ANFS_Pos)                /*!< 0x00000030 */
+#define FDCAN_GFC_ANFS            FDCAN_GFC_ANFS_Msk                           /*!<Accept Non-matching Frames Standard       */
+
+/*****************  Bit definition for FDCAN_SIDFC register  ********************/
+#define FDCAN_SIDFC_FLSSA_Pos     (2U)
+#define FDCAN_SIDFC_FLSSA_Msk     (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos)          /*!< 0x0000FFFC */
+#define FDCAN_SIDFC_FLSSA         FDCAN_SIDFC_FLSSA_Msk                        /*!<Filter List Standard Start Address        */
+#define FDCAN_SIDFC_LSS_Pos       (16U)
+#define FDCAN_SIDFC_LSS_Msk       (0xFFUL << FDCAN_SIDFC_LSS_Pos)              /*!< 0x00FF0000 */
+#define FDCAN_SIDFC_LSS           FDCAN_SIDFC_LSS_Msk                          /*!<List Size Standard                        */
+
+/*****************  Bit definition for FDCAN_XIDFC register  ********************/
+#define FDCAN_XIDFC_FLESA_Pos     (2U)
+#define FDCAN_XIDFC_FLESA_Msk     (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos)          /*!< 0x0000FFFC */
+#define FDCAN_XIDFC_FLESA         FDCAN_XIDFC_FLESA_Msk                        /*!<Filter List Standard Start Address        */
+#define FDCAN_XIDFC_LSE_Pos       (16U)
+#define FDCAN_XIDFC_LSE_Msk       (0x7FUL << FDCAN_XIDFC_LSE_Pos)              /*!< 0x007F0000 */
+#define FDCAN_XIDFC_LSE           FDCAN_XIDFC_LSE_Msk                          /*!<List Size Extended                        */
+
+/*****************  Bit definition for FDCAN_XIDAM register  ********************/
+#define FDCAN_XIDAM_EIDM_Pos      (0U)
+#define FDCAN_XIDAM_EIDM_Msk      (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)       /*!< 0x1FFFFFFF */
+#define FDCAN_XIDAM_EIDM          FDCAN_XIDAM_EIDM_Msk                         /*!<Extended ID Mask                          */
+
+/*****************  Bit definition for FDCAN_HPMS register  *********************/
+#define FDCAN_HPMS_BIDX_Pos       (0U)
+#define FDCAN_HPMS_BIDX_Msk       (0x3FUL << FDCAN_HPMS_BIDX_Pos)              /*!< 0x0000003F */
+#define FDCAN_HPMS_BIDX           FDCAN_HPMS_BIDX_Msk                          /*!<Buffer Index                              */
+#define FDCAN_HPMS_MSI_Pos        (6U)
+#define FDCAN_HPMS_MSI_Msk        (0x3UL << FDCAN_HPMS_MSI_Pos)                /*!< 0x000000C0 */
+#define FDCAN_HPMS_MSI            FDCAN_HPMS_MSI_Msk                           /*!<Message Storage Indicator                 */
+#define FDCAN_HPMS_FIDX_Pos       (8U)
+#define FDCAN_HPMS_FIDX_Msk       (0x7FUL << FDCAN_HPMS_FIDX_Pos)              /*!< 0x00007F00 */
+#define FDCAN_HPMS_FIDX           FDCAN_HPMS_FIDX_Msk                          /*!<Filter Index                              */
+#define FDCAN_HPMS_FLST_Pos       (15U)
+#define FDCAN_HPMS_FLST_Msk       (0x1UL << FDCAN_HPMS_FLST_Pos)               /*!< 0x00008000 */
+#define FDCAN_HPMS_FLST           FDCAN_HPMS_FLST_Msk                          /*!<Filter List                               */
+
+/*****************  Bit definition for FDCAN_NDAT1 register  ********************/
+#define FDCAN_NDAT1_ND0_Pos       (0U)
+#define FDCAN_NDAT1_ND0_Msk       (0x1UL << FDCAN_NDAT1_ND0_Pos)               /*!< 0x00000001 */
+#define FDCAN_NDAT1_ND0           FDCAN_NDAT1_ND0_Msk                          /*!<New Data flag of Rx Buffer 0              */
+#define FDCAN_NDAT1_ND1_Pos       (1U)
+#define FDCAN_NDAT1_ND1_Msk       (0x1UL << FDCAN_NDAT1_ND1_Pos)               /*!< 0x00000002 */
+#define FDCAN_NDAT1_ND1           FDCAN_NDAT1_ND1_Msk                          /*!<New Data flag of Rx Buffer 1              */
+#define FDCAN_NDAT1_ND2_Pos       (2U)
+#define FDCAN_NDAT1_ND2_Msk       (0x1UL << FDCAN_NDAT1_ND2_Pos)               /*!< 0x00000004 */
+#define FDCAN_NDAT1_ND2           FDCAN_NDAT1_ND2_Msk                          /*!<New Data flag of Rx Buffer 2              */
+#define FDCAN_NDAT1_ND3_Pos       (3U)
+#define FDCAN_NDAT1_ND3_Msk       (0x1UL << FDCAN_NDAT1_ND3_Pos)               /*!< 0x00000008 */
+#define FDCAN_NDAT1_ND3           FDCAN_NDAT1_ND3_Msk                          /*!<New Data flag of Rx Buffer 3              */
+#define FDCAN_NDAT1_ND4_Pos       (4U)
+#define FDCAN_NDAT1_ND4_Msk       (0x1UL << FDCAN_NDAT1_ND4_Pos)               /*!< 0x00000010 */
+#define FDCAN_NDAT1_ND4           FDCAN_NDAT1_ND4_Msk                          /*!<New Data flag of Rx Buffer 4              */
+#define FDCAN_NDAT1_ND5_Pos       (5U)
+#define FDCAN_NDAT1_ND5_Msk       (0x1UL << FDCAN_NDAT1_ND5_Pos)               /*!< 0x00000020 */
+#define FDCAN_NDAT1_ND5           FDCAN_NDAT1_ND5_Msk                          /*!<New Data flag of Rx Buffer 5              */
+#define FDCAN_NDAT1_ND6_Pos       (6U)
+#define FDCAN_NDAT1_ND6_Msk       (0x1UL << FDCAN_NDAT1_ND6_Pos)               /*!< 0x00000040 */
+#define FDCAN_NDAT1_ND6           FDCAN_NDAT1_ND6_Msk                          /*!<New Data flag of Rx Buffer 6              */
+#define FDCAN_NDAT1_ND7_Pos       (7U)
+#define FDCAN_NDAT1_ND7_Msk       (0x1UL << FDCAN_NDAT1_ND7_Pos)               /*!< 0x00000080 */
+#define FDCAN_NDAT1_ND7           FDCAN_NDAT1_ND7_Msk                          /*!<New Data flag of Rx Buffer 7              */
+#define FDCAN_NDAT1_ND8_Pos       (8U)
+#define FDCAN_NDAT1_ND8_Msk       (0x1UL << FDCAN_NDAT1_ND8_Pos)               /*!< 0x00000100 */
+#define FDCAN_NDAT1_ND8           FDCAN_NDAT1_ND8_Msk                          /*!<New Data flag of Rx Buffer 8              */
+#define FDCAN_NDAT1_ND9_Pos       (9U)
+#define FDCAN_NDAT1_ND9_Msk       (0x1UL << FDCAN_NDAT1_ND9_Pos)               /*!< 0x00000200 */
+#define FDCAN_NDAT1_ND9           FDCAN_NDAT1_ND9_Msk                          /*!<New Data flag of Rx Buffer 9              */
+#define FDCAN_NDAT1_ND10_Pos      (10U)
+#define FDCAN_NDAT1_ND10_Msk      (0x1UL << FDCAN_NDAT1_ND10_Pos)              /*!< 0x00000400 */
+#define FDCAN_NDAT1_ND10          FDCAN_NDAT1_ND10_Msk                         /*!<New Data flag of Rx Buffer 10             */
+#define FDCAN_NDAT1_ND11_Pos      (11U)
+#define FDCAN_NDAT1_ND11_Msk      (0x1UL << FDCAN_NDAT1_ND11_Pos)              /*!< 0x00000800 */
+#define FDCAN_NDAT1_ND11          FDCAN_NDAT1_ND11_Msk                         /*!<New Data flag of Rx Buffer 11             */
+#define FDCAN_NDAT1_ND12_Pos      (12U)
+#define FDCAN_NDAT1_ND12_Msk      (0x1UL << FDCAN_NDAT1_ND12_Pos)              /*!< 0x00001000 */
+#define FDCAN_NDAT1_ND12          FDCAN_NDAT1_ND12_Msk                         /*!<New Data flag of Rx Buffer 12             */
+#define FDCAN_NDAT1_ND13_Pos      (13U)
+#define FDCAN_NDAT1_ND13_Msk      (0x1UL << FDCAN_NDAT1_ND13_Pos)              /*!< 0x00002000 */
+#define FDCAN_NDAT1_ND13          FDCAN_NDAT1_ND13_Msk                         /*!<New Data flag of Rx Buffer 13             */
+#define FDCAN_NDAT1_ND14_Pos      (14U)
+#define FDCAN_NDAT1_ND14_Msk      (0x1UL << FDCAN_NDAT1_ND14_Pos)              /*!< 0x00004000 */
+#define FDCAN_NDAT1_ND14          FDCAN_NDAT1_ND14_Msk                         /*!<New Data flag of Rx Buffer 14             */
+#define FDCAN_NDAT1_ND15_Pos      (15U)
+#define FDCAN_NDAT1_ND15_Msk      (0x1UL << FDCAN_NDAT1_ND15_Pos)              /*!< 0x00008000 */
+#define FDCAN_NDAT1_ND15          FDCAN_NDAT1_ND15_Msk                         /*!<New Data flag of Rx Buffer 15             */
+#define FDCAN_NDAT1_ND16_Pos      (16U)
+#define FDCAN_NDAT1_ND16_Msk      (0x1UL << FDCAN_NDAT1_ND16_Pos)              /*!< 0x00010000 */
+#define FDCAN_NDAT1_ND16          FDCAN_NDAT1_ND16_Msk                         /*!<New Data flag of Rx Buffer 16             */
+#define FDCAN_NDAT1_ND17_Pos      (17U)
+#define FDCAN_NDAT1_ND17_Msk      (0x1UL << FDCAN_NDAT1_ND17_Pos)              /*!< 0x00020000 */
+#define FDCAN_NDAT1_ND17          FDCAN_NDAT1_ND17_Msk                         /*!<New Data flag of Rx Buffer 17             */
+#define FDCAN_NDAT1_ND18_Pos      (18U)
+#define FDCAN_NDAT1_ND18_Msk      (0x1UL << FDCAN_NDAT1_ND18_Pos)              /*!< 0x00040000 */
+#define FDCAN_NDAT1_ND18          FDCAN_NDAT1_ND18_Msk                         /*!<New Data flag of Rx Buffer 18             */
+#define FDCAN_NDAT1_ND19_Pos      (19U)
+#define FDCAN_NDAT1_ND19_Msk      (0x1UL << FDCAN_NDAT1_ND19_Pos)              /*!< 0x00080000 */
+#define FDCAN_NDAT1_ND19          FDCAN_NDAT1_ND19_Msk                         /*!<New Data flag of Rx Buffer 19             */
+#define FDCAN_NDAT1_ND20_Pos      (20U)
+#define FDCAN_NDAT1_ND20_Msk      (0x1UL << FDCAN_NDAT1_ND20_Pos)              /*!< 0x00100000 */
+#define FDCAN_NDAT1_ND20          FDCAN_NDAT1_ND20_Msk                         /*!<New Data flag of Rx Buffer 20             */
+#define FDCAN_NDAT1_ND21_Pos      (21U)
+#define FDCAN_NDAT1_ND21_Msk      (0x1UL << FDCAN_NDAT1_ND21_Pos)              /*!< 0x00200000 */
+#define FDCAN_NDAT1_ND21          FDCAN_NDAT1_ND21_Msk                         /*!<New Data flag of Rx Buffer 21             */
+#define FDCAN_NDAT1_ND22_Pos      (22U)
+#define FDCAN_NDAT1_ND22_Msk      (0x1UL << FDCAN_NDAT1_ND22_Pos)              /*!< 0x00400000 */
+#define FDCAN_NDAT1_ND22          FDCAN_NDAT1_ND22_Msk                         /*!<New Data flag of Rx Buffer 22             */
+#define FDCAN_NDAT1_ND23_Pos      (23U)
+#define FDCAN_NDAT1_ND23_Msk      (0x1UL << FDCAN_NDAT1_ND23_Pos)              /*!< 0x00800000 */
+#define FDCAN_NDAT1_ND23          FDCAN_NDAT1_ND23_Msk                         /*!<New Data flag of Rx Buffer 23             */
+#define FDCAN_NDAT1_ND24_Pos      (24U)
+#define FDCAN_NDAT1_ND24_Msk      (0x1UL << FDCAN_NDAT1_ND24_Pos)              /*!< 0x01000000 */
+#define FDCAN_NDAT1_ND24          FDCAN_NDAT1_ND24_Msk                         /*!<New Data flag of Rx Buffer 24             */
+#define FDCAN_NDAT1_ND25_Pos      (25U)
+#define FDCAN_NDAT1_ND25_Msk      (0x1UL << FDCAN_NDAT1_ND25_Pos)              /*!< 0x02000000 */
+#define FDCAN_NDAT1_ND25          FDCAN_NDAT1_ND25_Msk                         /*!<New Data flag of Rx Buffer 25             */
+#define FDCAN_NDAT1_ND26_Pos      (26U)
+#define FDCAN_NDAT1_ND26_Msk      (0x1UL << FDCAN_NDAT1_ND26_Pos)              /*!< 0x04000000 */
+#define FDCAN_NDAT1_ND26          FDCAN_NDAT1_ND26_Msk                         /*!<New Data flag of Rx Buffer 26             */
+#define FDCAN_NDAT1_ND27_Pos      (27U)
+#define FDCAN_NDAT1_ND27_Msk      (0x1UL << FDCAN_NDAT1_ND27_Pos)              /*!< 0x08000000 */
+#define FDCAN_NDAT1_ND27          FDCAN_NDAT1_ND27_Msk                         /*!<New Data flag of Rx Buffer 27             */
+#define FDCAN_NDAT1_ND28_Pos      (28U)
+#define FDCAN_NDAT1_ND28_Msk      (0x1UL << FDCAN_NDAT1_ND28_Pos)              /*!< 0x10000000 */
+#define FDCAN_NDAT1_ND28          FDCAN_NDAT1_ND28_Msk                         /*!<New Data flag of Rx Buffer 28             */
+#define FDCAN_NDAT1_ND29_Pos      (29U)
+#define FDCAN_NDAT1_ND29_Msk      (0x1UL << FDCAN_NDAT1_ND29_Pos)              /*!< 0x20000000 */
+#define FDCAN_NDAT1_ND29          FDCAN_NDAT1_ND29_Msk                         /*!<New Data flag of Rx Buffer 29             */
+#define FDCAN_NDAT1_ND30_Pos      (30U)
+#define FDCAN_NDAT1_ND30_Msk      (0x1UL << FDCAN_NDAT1_ND30_Pos)              /*!< 0x40000000 */
+#define FDCAN_NDAT1_ND30          FDCAN_NDAT1_ND30_Msk                         /*!<New Data flag of Rx Buffer 30             */
+#define FDCAN_NDAT1_ND31_Pos      (31U)
+#define FDCAN_NDAT1_ND31_Msk      (0x1UL << FDCAN_NDAT1_ND31_Pos)              /*!< 0x80000000 */
+#define FDCAN_NDAT1_ND31          FDCAN_NDAT1_ND31_Msk                         /*!<New Data flag of Rx Buffer 31             */
+
+/*****************  Bit definition for FDCAN_NDAT2 register  ********************/
+#define FDCAN_NDAT2_ND32_Pos      (0U)
+#define FDCAN_NDAT2_ND32_Msk      (0x1UL << FDCAN_NDAT2_ND32_Pos)              /*!< 0x00000001 */
+#define FDCAN_NDAT2_ND32          FDCAN_NDAT2_ND32_Msk                         /*!<New Data flag of Rx Buffer 32             */
+#define FDCAN_NDAT2_ND33_Pos      (1U)
+#define FDCAN_NDAT2_ND33_Msk      (0x1UL << FDCAN_NDAT2_ND33_Pos)              /*!< 0x00000002 */
+#define FDCAN_NDAT2_ND33          FDCAN_NDAT2_ND33_Msk                         /*!<New Data flag of Rx Buffer 33             */
+#define FDCAN_NDAT2_ND34_Pos      (2U)
+#define FDCAN_NDAT2_ND34_Msk      (0x1UL << FDCAN_NDAT2_ND34_Pos)              /*!< 0x00000004 */
+#define FDCAN_NDAT2_ND34          FDCAN_NDAT2_ND34_Msk                         /*!<New Data flag of Rx Buffer 34             */
+#define FDCAN_NDAT2_ND35_Pos      (3U)
+#define FDCAN_NDAT2_ND35_Msk      (0x1UL << FDCAN_NDAT2_ND35_Pos)              /*!< 0x00000008 */
+#define FDCAN_NDAT2_ND35          FDCAN_NDAT2_ND35_Msk                         /*!<New Data flag of Rx Buffer 35             */
+#define FDCAN_NDAT2_ND36_Pos      (4U)
+#define FDCAN_NDAT2_ND36_Msk      (0x1UL << FDCAN_NDAT2_ND36_Pos)              /*!< 0x00000010 */
+#define FDCAN_NDAT2_ND36          FDCAN_NDAT2_ND36_Msk                         /*!<New Data flag of Rx Buffer 36             */
+#define FDCAN_NDAT2_ND37_Pos      (5U)
+#define FDCAN_NDAT2_ND37_Msk      (0x1UL << FDCAN_NDAT2_ND37_Pos)              /*!< 0x00000020 */
+#define FDCAN_NDAT2_ND37          FDCAN_NDAT2_ND37_Msk                         /*!<New Data flag of Rx Buffer 37             */
+#define FDCAN_NDAT2_ND38_Pos      (6U)
+#define FDCAN_NDAT2_ND38_Msk      (0x1UL << FDCAN_NDAT2_ND38_Pos)              /*!< 0x00000040 */
+#define FDCAN_NDAT2_ND38          FDCAN_NDAT2_ND38_Msk                         /*!<New Data flag of Rx Buffer 38             */
+#define FDCAN_NDAT2_ND39_Pos      (7U)
+#define FDCAN_NDAT2_ND39_Msk      (0x1UL << FDCAN_NDAT2_ND39_Pos)              /*!< 0x00000080 */
+#define FDCAN_NDAT2_ND39          FDCAN_NDAT2_ND39_Msk                         /*!<New Data flag of Rx Buffer 39             */
+#define FDCAN_NDAT2_ND40_Pos      (8U)
+#define FDCAN_NDAT2_ND40_Msk      (0x1UL << FDCAN_NDAT2_ND40_Pos)              /*!< 0x00000100 */
+#define FDCAN_NDAT2_ND40          FDCAN_NDAT2_ND40_Msk                         /*!<New Data flag of Rx Buffer 40             */
+#define FDCAN_NDAT2_ND41_Pos      (9U)
+#define FDCAN_NDAT2_ND41_Msk      (0x1UL << FDCAN_NDAT2_ND41_Pos)              /*!< 0x00000200 */
+#define FDCAN_NDAT2_ND41          FDCAN_NDAT2_ND41_Msk                         /*!<New Data flag of Rx Buffer 41             */
+#define FDCAN_NDAT2_ND42_Pos      (10U)
+#define FDCAN_NDAT2_ND42_Msk      (0x1UL << FDCAN_NDAT2_ND42_Pos)              /*!< 0x00000400 */
+#define FDCAN_NDAT2_ND42          FDCAN_NDAT2_ND42_Msk                         /*!<New Data flag of Rx Buffer 42             */
+#define FDCAN_NDAT2_ND43_Pos      (11U)
+#define FDCAN_NDAT2_ND43_Msk      (0x1UL << FDCAN_NDAT2_ND43_Pos)              /*!< 0x00000800 */
+#define FDCAN_NDAT2_ND43          FDCAN_NDAT2_ND43_Msk                         /*!<New Data flag of Rx Buffer 43             */
+#define FDCAN_NDAT2_ND44_Pos      (12U)
+#define FDCAN_NDAT2_ND44_Msk      (0x1UL << FDCAN_NDAT2_ND44_Pos)              /*!< 0x00001000 */
+#define FDCAN_NDAT2_ND44          FDCAN_NDAT2_ND44_Msk                         /*!<New Data flag of Rx Buffer 44             */
+#define FDCAN_NDAT2_ND45_Pos      (13U)
+#define FDCAN_NDAT2_ND45_Msk      (0x1UL << FDCAN_NDAT2_ND45_Pos)              /*!< 0x00002000 */
+#define FDCAN_NDAT2_ND45          FDCAN_NDAT2_ND45_Msk                         /*!<New Data flag of Rx Buffer 45             */
+#define FDCAN_NDAT2_ND46_Pos      (14U)
+#define FDCAN_NDAT2_ND46_Msk      (0x1UL << FDCAN_NDAT2_ND46_Pos)              /*!< 0x00004000 */
+#define FDCAN_NDAT2_ND46          FDCAN_NDAT2_ND46_Msk                         /*!<New Data flag of Rx Buffer 46             */
+#define FDCAN_NDAT2_ND47_Pos      (15U)
+#define FDCAN_NDAT2_ND47_Msk      (0x1UL << FDCAN_NDAT2_ND47_Pos)              /*!< 0x00008000 */
+#define FDCAN_NDAT2_ND47          FDCAN_NDAT2_ND47_Msk                         /*!<New Data flag of Rx Buffer 47             */
+#define FDCAN_NDAT2_ND48_Pos      (16U)
+#define FDCAN_NDAT2_ND48_Msk      (0x1UL << FDCAN_NDAT2_ND48_Pos)              /*!< 0x00010000 */
+#define FDCAN_NDAT2_ND48          FDCAN_NDAT2_ND48_Msk                         /*!<New Data flag of Rx Buffer 48             */
+#define FDCAN_NDAT2_ND49_Pos      (17U)
+#define FDCAN_NDAT2_ND49_Msk      (0x1UL << FDCAN_NDAT2_ND49_Pos)              /*!< 0x00020000 */
+#define FDCAN_NDAT2_ND49          FDCAN_NDAT2_ND49_Msk                         /*!<New Data flag of Rx Buffer 49             */
+#define FDCAN_NDAT2_ND50_Pos      (18U)
+#define FDCAN_NDAT2_ND50_Msk      (0x1UL << FDCAN_NDAT2_ND50_Pos)              /*!< 0x00040000 */
+#define FDCAN_NDAT2_ND50          FDCAN_NDAT2_ND50_Msk                         /*!<New Data flag of Rx Buffer 50             */
+#define FDCAN_NDAT2_ND51_Pos      (19U)
+#define FDCAN_NDAT2_ND51_Msk      (0x1UL << FDCAN_NDAT2_ND51_Pos)              /*!< 0x00080000 */
+#define FDCAN_NDAT2_ND51          FDCAN_NDAT2_ND51_Msk                         /*!<New Data flag of Rx Buffer 51             */
+#define FDCAN_NDAT2_ND52_Pos      (20U)
+#define FDCAN_NDAT2_ND52_Msk      (0x1UL << FDCAN_NDAT2_ND52_Pos)              /*!< 0x00100000 */
+#define FDCAN_NDAT2_ND52          FDCAN_NDAT2_ND52_Msk                         /*!<New Data flag of Rx Buffer 52             */
+#define FDCAN_NDAT2_ND53_Pos      (21U)
+#define FDCAN_NDAT2_ND53_Msk      (0x1UL << FDCAN_NDAT2_ND53_Pos)              /*!< 0x00200000 */
+#define FDCAN_NDAT2_ND53          FDCAN_NDAT2_ND53_Msk                         /*!<New Data flag of Rx Buffer 53             */
+#define FDCAN_NDAT2_ND54_Pos      (22U)
+#define FDCAN_NDAT2_ND54_Msk      (0x1UL << FDCAN_NDAT2_ND54_Pos)              /*!< 0x00400000 */
+#define FDCAN_NDAT2_ND54          FDCAN_NDAT2_ND54_Msk                         /*!<New Data flag of Rx Buffer 54             */
+#define FDCAN_NDAT2_ND55_Pos      (23U)
+#define FDCAN_NDAT2_ND55_Msk      (0x1UL << FDCAN_NDAT2_ND55_Pos)              /*!< 0x00800000 */
+#define FDCAN_NDAT2_ND55          FDCAN_NDAT2_ND55_Msk                         /*!<New Data flag of Rx Buffer 55             */
+#define FDCAN_NDAT2_ND56_Pos      (24U)
+#define FDCAN_NDAT2_ND56_Msk      (0x1UL << FDCAN_NDAT2_ND56_Pos)              /*!< 0x01000000 */
+#define FDCAN_NDAT2_ND56          FDCAN_NDAT2_ND56_Msk                         /*!<New Data flag of Rx Buffer 56             */
+#define FDCAN_NDAT2_ND57_Pos      (25U)
+#define FDCAN_NDAT2_ND57_Msk      (0x1UL << FDCAN_NDAT2_ND57_Pos)              /*!< 0x02000000 */
+#define FDCAN_NDAT2_ND57          FDCAN_NDAT2_ND57_Msk                         /*!<New Data flag of Rx Buffer 57             */
+#define FDCAN_NDAT2_ND58_Pos      (26U)
+#define FDCAN_NDAT2_ND58_Msk      (0x1UL << FDCAN_NDAT2_ND58_Pos)              /*!< 0x04000000 */
+#define FDCAN_NDAT2_ND58          FDCAN_NDAT2_ND58_Msk                         /*!<New Data flag of Rx Buffer 58             */
+#define FDCAN_NDAT2_ND59_Pos      (27U)
+#define FDCAN_NDAT2_ND59_Msk      (0x1UL << FDCAN_NDAT2_ND59_Pos)              /*!< 0x08000000 */
+#define FDCAN_NDAT2_ND59          FDCAN_NDAT2_ND59_Msk                         /*!<New Data flag of Rx Buffer 59             */
+#define FDCAN_NDAT2_ND60_Pos      (28U)
+#define FDCAN_NDAT2_ND60_Msk      (0x1UL << FDCAN_NDAT2_ND60_Pos)              /*!< 0x10000000 */
+#define FDCAN_NDAT2_ND60          FDCAN_NDAT2_ND60_Msk                         /*!<New Data flag of Rx Buffer 60             */
+#define FDCAN_NDAT2_ND61_Pos      (29U)
+#define FDCAN_NDAT2_ND61_Msk      (0x1UL << FDCAN_NDAT2_ND61_Pos)              /*!< 0x20000000 */
+#define FDCAN_NDAT2_ND61          FDCAN_NDAT2_ND61_Msk                         /*!<New Data flag of Rx Buffer 61             */
+#define FDCAN_NDAT2_ND62_Pos      (30U)
+#define FDCAN_NDAT2_ND62_Msk      (0x1UL << FDCAN_NDAT2_ND62_Pos)              /*!< 0x40000000 */
+#define FDCAN_NDAT2_ND62          FDCAN_NDAT2_ND62_Msk                         /*!<New Data flag of Rx Buffer 62             */
+#define FDCAN_NDAT2_ND63_Pos      (31U)
+#define FDCAN_NDAT2_ND63_Msk      (0x1UL << FDCAN_NDAT2_ND63_Pos)              /*!< 0x80000000 */
+#define FDCAN_NDAT2_ND63          FDCAN_NDAT2_ND63_Msk                         /*!<New Data flag of Rx Buffer 63             */
+
+/*****************  Bit definition for FDCAN_RXF0C register  ********************/
+#define FDCAN_RXF0C_F0SA_Pos      (2U)
+#define FDCAN_RXF0C_F0SA_Msk      (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos)           /*!< 0x0000FFFC */
+#define FDCAN_RXF0C_F0SA          FDCAN_RXF0C_F0SA_Msk                         /*!<Rx FIFO 0 Start Address                   */
+#define FDCAN_RXF0C_F0S_Pos       (16U)
+#define FDCAN_RXF0C_F0S_Msk       (0x7FUL << FDCAN_RXF0C_F0S_Pos)              /*!< 0x007F0000 */
+#define FDCAN_RXF0C_F0S           FDCAN_RXF0C_F0S_Msk                          /*!<Number of Rx FIFO 0 elements              */
+#define FDCAN_RXF0C_F0WM_Pos      (24U)
+#define FDCAN_RXF0C_F0WM_Msk      (0x7FUL << FDCAN_RXF0C_F0WM_Pos)             /*!< 0x7F000000 */
+#define FDCAN_RXF0C_F0WM          FDCAN_RXF0C_F0WM_Msk                         /*!<FIFO 0 Watermark                          */
+#define FDCAN_RXF0C_F0OM_Pos      (31U)
+#define FDCAN_RXF0C_F0OM_Msk      (0x1UL << FDCAN_RXF0C_F0OM_Pos)              /*!< 0x80000000 */
+#define FDCAN_RXF0C_F0OM          FDCAN_RXF0C_F0OM_Msk                         /*!<FIFO 0 Operation Mode                     */
+
+/*****************  Bit definition for FDCAN_RXF0S register  ********************/
+#define FDCAN_RXF0S_F0FL_Pos      (0U)
+#define FDCAN_RXF0S_F0FL_Msk      (0x7FUL << FDCAN_RXF0S_F0FL_Pos)             /*!< 0x0000007F */
+#define FDCAN_RXF0S_F0FL          FDCAN_RXF0S_F0FL_Msk                         /*!<Rx FIFO 0 Fill Level                      */
+#define FDCAN_RXF0S_F0GI_Pos      (8U)
+#define FDCAN_RXF0S_F0GI_Msk      (0x3FUL << FDCAN_RXF0S_F0GI_Pos)             /*!< 0x00003F00 */
+#define FDCAN_RXF0S_F0GI          FDCAN_RXF0S_F0GI_Msk                         /*!<Rx FIFO 0 Get Index                       */
+#define FDCAN_RXF0S_F0PI_Pos      (16U)
+#define FDCAN_RXF0S_F0PI_Msk      (0x3FUL << FDCAN_RXF0S_F0PI_Pos)             /*!< 0x003F0000 */
+#define FDCAN_RXF0S_F0PI          FDCAN_RXF0S_F0PI_Msk                         /*!<Rx FIFO 0 Put Index                       */
+#define FDCAN_RXF0S_F0F_Pos       (24U)
+#define FDCAN_RXF0S_F0F_Msk       (0x1UL << FDCAN_RXF0S_F0F_Pos)               /*!< 0x01000000 */
+#define FDCAN_RXF0S_F0F           FDCAN_RXF0S_F0F_Msk                          /*!<Rx FIFO 0 Full                            */
+#define FDCAN_RXF0S_RF0L_Pos      (25U)
+#define FDCAN_RXF0S_RF0L_Msk      (0x1UL << FDCAN_RXF0S_RF0L_Pos)              /*!< 0x02000000 */
+#define FDCAN_RXF0S_RF0L          FDCAN_RXF0S_RF0L_Msk                         /*!<Rx FIFO 0 Message Lost                    */
+
+/*****************  Bit definition for FDCAN_RXF0A register  ********************/
+#define FDCAN_RXF0A_F0AI_Pos      (0U)
+#define FDCAN_RXF0A_F0AI_Msk      (0x3FUL << FDCAN_RXF0A_F0AI_Pos)             /*!< 0x0000003F */
+#define FDCAN_RXF0A_F0AI          FDCAN_RXF0A_F0AI_Msk                         /*!<Rx FIFO 0 Acknowledge Index               */
+
+/*****************  Bit definition for FDCAN_RXBC register  ********************/
+#define FDCAN_RXBC_RBSA_Pos       (2U)
+#define FDCAN_RXBC_RBSA_Msk       (0x3FFFUL << FDCAN_RXBC_RBSA_Pos)            /*!< 0x0000FFFC */
+#define FDCAN_RXBC_RBSA           FDCAN_RXBC_RBSA_Msk                          /*!<Rx Buffer Start Address                   */
+
+/*****************  Bit definition for FDCAN_RXF1C register  ********************/
+#define FDCAN_RXF1C_F1SA_Pos      (2U)
+#define FDCAN_RXF1C_F1SA_Msk      (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos)           /*!< 0x0000FFFC */
+#define FDCAN_RXF1C_F1SA          FDCAN_RXF1C_F1SA_Msk                         /*!<Rx FIFO 1 Start Address                   */
+#define FDCAN_RXF1C_F1S_Pos       (16U)
+#define FDCAN_RXF1C_F1S_Msk       (0x7FUL << FDCAN_RXF1C_F1S_Pos)              /*!< 0x007F0000 */
+#define FDCAN_RXF1C_F1S           FDCAN_RXF1C_F1S_Msk                          /*!<Number of Rx FIFO 1 elements              */
+#define FDCAN_RXF1C_F1WM_Pos      (24U)
+#define FDCAN_RXF1C_F1WM_Msk      (0x7FUL << FDCAN_RXF1C_F1WM_Pos)             /*!< 0x7F000000 */
+#define FDCAN_RXF1C_F1WM          FDCAN_RXF1C_F1WM_Msk                         /*!<Rx FIFO 1 Watermark                       */
+#define FDCAN_RXF1C_F1OM_Pos      (31U)
+#define FDCAN_RXF1C_F1OM_Msk      (0x1UL << FDCAN_RXF1C_F1OM_Pos)              /*!< 0x80000000 */
+#define FDCAN_RXF1C_F1OM          FDCAN_RXF1C_F1OM_Msk                         /*!<FIFO 1 Operation Mode                     */
+
+/*****************  Bit definition for FDCAN_RXF1S register  ********************/
+#define FDCAN_RXF1S_F1FL_Pos      (0U)
+#define FDCAN_RXF1S_F1FL_Msk      (0x7FUL << FDCAN_RXF1S_F1FL_Pos)             /*!< 0x0000007F */
+#define FDCAN_RXF1S_F1FL          FDCAN_RXF1S_F1FL_Msk                         /*!<Rx FIFO 1 Fill Level                      */
+#define FDCAN_RXF1S_F1GI_Pos      (8U)
+#define FDCAN_RXF1S_F1GI_Msk      (0x3FUL << FDCAN_RXF1S_F1GI_Pos)             /*!< 0x00003F00 */
+#define FDCAN_RXF1S_F1GI          FDCAN_RXF1S_F1GI_Msk                         /*!<Rx FIFO 1 Get Index                       */
+#define FDCAN_RXF1S_F1PI_Pos      (16U)
+#define FDCAN_RXF1S_F1PI_Msk      (0x3FUL << FDCAN_RXF1S_F1PI_Pos)             /*!< 0x003F0000 */
+#define FDCAN_RXF1S_F1PI          FDCAN_RXF1S_F1PI_Msk                         /*!<Rx FIFO 1 Put Index                       */
+#define FDCAN_RXF1S_F1F_Pos       (24U)
+#define FDCAN_RXF1S_F1F_Msk       (0x1UL << FDCAN_RXF1S_F1F_Pos)               /*!< 0x01000000 */
+#define FDCAN_RXF1S_F1F           FDCAN_RXF1S_F1F_Msk                          /*!<Rx FIFO 1 Full                            */
+#define FDCAN_RXF1S_RF1L_Pos      (25U)
+#define FDCAN_RXF1S_RF1L_Msk      (0x1UL << FDCAN_RXF1S_RF1L_Pos)              /*!< 0x02000000 */
+#define FDCAN_RXF1S_RF1L          FDCAN_RXF1S_RF1L_Msk                         /*!<Rx FIFO 1 Message Lost                    */
+
+/*****************  Bit definition for FDCAN_RXF1A register  ********************/
+#define FDCAN_RXF1A_F1AI_Pos      (0U)
+#define FDCAN_RXF1A_F1AI_Msk      (0x3FUL << FDCAN_RXF1A_F1AI_Pos)             /*!< 0x0000003F */
+#define FDCAN_RXF1A_F1AI          FDCAN_RXF1A_F1AI_Msk                         /*!<Rx FIFO 1 Acknowledge Index               */
+
+/*****************  Bit definition for FDCAN_RXESC register  ********************/
+#define FDCAN_RXESC_F0DS_Pos      (0U)
+#define FDCAN_RXESC_F0DS_Msk      (0x7UL << FDCAN_RXESC_F0DS_Pos)              /*!< 0x00000007 */
+#define FDCAN_RXESC_F0DS          FDCAN_RXESC_F0DS_Msk                         /*!<Rx FIFO 1 Data Field Size                 */
+#define FDCAN_RXESC_F1DS_Pos      (4U)
+#define FDCAN_RXESC_F1DS_Msk      (0x7UL << FDCAN_RXESC_F1DS_Pos)              /*!< 0x00000070 */
+#define FDCAN_RXESC_F1DS          FDCAN_RXESC_F1DS_Msk                         /*!<Rx FIFO 0 Data Field Size                 */
+#define FDCAN_RXESC_RBDS_Pos      (8U)
+#define FDCAN_RXESC_RBDS_Msk      (0x7UL << FDCAN_RXESC_RBDS_Pos)              /*!< 0x00000700 */
+#define FDCAN_RXESC_RBDS          FDCAN_RXESC_RBDS_Msk                         /*!<Rx Buffer Data Field Size                 */
+
+/*****************  Bit definition for FDCAN_TXBC register  *********************/
+#define FDCAN_TXBC_TBSA_Pos       (2U)
+#define FDCAN_TXBC_TBSA_Msk       (0x3FFFUL << FDCAN_TXBC_TBSA_Pos)            /*!< 0x0000FFFC */
+#define FDCAN_TXBC_TBSA           FDCAN_TXBC_TBSA_Msk                          /*!<Tx Buffers Start Address                  */
+#define FDCAN_TXBC_NDTB_Pos       (16U)
+#define FDCAN_TXBC_NDTB_Msk       (0x3FUL << FDCAN_TXBC_NDTB_Pos)              /*!< 0x003F0000 */
+#define FDCAN_TXBC_NDTB           FDCAN_TXBC_NDTB_Msk                          /*!<Number of Dedicated Transmit Buffers      */
+#define FDCAN_TXBC_TFQS_Pos       (24U)
+#define FDCAN_TXBC_TFQS_Msk       (0x3FUL << FDCAN_TXBC_TFQS_Pos)              /*!< 0x3F000000 */
+#define FDCAN_TXBC_TFQS           FDCAN_TXBC_TFQS_Msk                          /*!<Transmit FIFO/Queue Size                  */
+#define FDCAN_TXBC_TFQM_Pos       (30U)
+#define FDCAN_TXBC_TFQM_Msk       (0x1UL << FDCAN_TXBC_TFQM_Pos)               /*!< 0x40000000 */
+#define FDCAN_TXBC_TFQM           FDCAN_TXBC_TFQM_Msk                          /*!<Tx FIFO/Queue Mode                        */
+
+/*****************  Bit definition for FDCAN_TXFQS register  *********************/
+#define FDCAN_TXFQS_TFFL_Pos      (0U)
+#define FDCAN_TXFQS_TFFL_Msk      (0x3FUL << FDCAN_TXFQS_TFFL_Pos)             /*!< 0x0000003F */
+#define FDCAN_TXFQS_TFFL          FDCAN_TXFQS_TFFL_Msk                         /*!<Tx FIFO Free Level                        */
+#define FDCAN_TXFQS_TFGI_Pos      (8U)
+#define FDCAN_TXFQS_TFGI_Msk      (0x1FUL << FDCAN_TXFQS_TFGI_Pos)             /*!< 0x00001F00 */
+#define FDCAN_TXFQS_TFGI          FDCAN_TXFQS_TFGI_Msk                         /*!<Tx FIFO Get Index                         */
+#define FDCAN_TXFQS_TFQPI_Pos     (16U)
+#define FDCAN_TXFQS_TFQPI_Msk     (0x1FUL << FDCAN_TXFQS_TFQPI_Pos)            /*!< 0x001F0000 */
+#define FDCAN_TXFQS_TFQPI         FDCAN_TXFQS_TFQPI_Msk                        /*!<Tx FIFO/Queue Put Index                   */
+#define FDCAN_TXFQS_TFQF_Pos      (21U)
+#define FDCAN_TXFQS_TFQF_Msk      (0x1UL << FDCAN_TXFQS_TFQF_Pos)              /*!< 0x00200000 */
+#define FDCAN_TXFQS_TFQF          FDCAN_TXFQS_TFQF_Msk                         /*!<Tx FIFO/Queue Full                        */
+
+/*****************  Bit definition for FDCAN_TXESC register  *********************/
+#define FDCAN_TXESC_TBDS_Pos      (0U)
+#define FDCAN_TXESC_TBDS_Msk      (0x7UL << FDCAN_TXESC_TBDS_Pos)              /*!< 0x00000007 */
+#define FDCAN_TXESC_TBDS          FDCAN_TXESC_TBDS_Msk                         /*!<Tx Buffer Data Field Size                 */
+
+/*****************  Bit definition for FDCAN_TXBRP register  *********************/
+#define FDCAN_TXBRP_TRP_Pos       (0U)
+#define FDCAN_TXBRP_TRP_Msk       (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos)        /*!< 0xFFFFFFFF */
+#define FDCAN_TXBRP_TRP           FDCAN_TXBRP_TRP_Msk                          /*!<Transmission Request Pending              */
+
+/*****************  Bit definition for FDCAN_TXBAR register  *********************/
+#define FDCAN_TXBAR_AR_Pos        (0U)
+#define FDCAN_TXBAR_AR_Msk        (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos)         /*!< 0xFFFFFFFF */
+#define FDCAN_TXBAR_AR            FDCAN_TXBAR_AR_Msk                           /*!<Add Request                               */
+
+/*****************  Bit definition for FDCAN_TXBCR register  *********************/
+#define FDCAN_TXBCR_CR_Pos        (0U)
+#define FDCAN_TXBCR_CR_Msk        (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos)         /*!< 0xFFFFFFFF */
+#define FDCAN_TXBCR_CR            FDCAN_TXBCR_CR_Msk                           /*!<Cancellation Request                      */
+
+/*****************  Bit definition for FDCAN_TXBTO register  *********************/
+#define FDCAN_TXBTO_TO_Pos        (0U)
+#define FDCAN_TXBTO_TO_Msk        (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos)         /*!< 0xFFFFFFFF */
+#define FDCAN_TXBTO_TO            FDCAN_TXBTO_TO_Msk                           /*!<Transmission Occurred                     */
+
+/*****************  Bit definition for FDCAN_TXBCF register  *********************/
+#define FDCAN_TXBCF_CF_Pos        (0U)
+#define FDCAN_TXBCF_CF_Msk        (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos)         /*!< 0xFFFFFFFF */
+#define FDCAN_TXBCF_CF            FDCAN_TXBCF_CF_Msk                           /*!<Cancellation Finished                     */
+
+/*****************  Bit definition for FDCAN_TXBTIE register  ********************/
+#define FDCAN_TXBTIE_TIE_Pos      (0U)
+#define FDCAN_TXBTIE_TIE_Msk      (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos)       /*!< 0xFFFFFFFF */
+#define FDCAN_TXBTIE_TIE          FDCAN_TXBTIE_TIE_Msk                         /*!<Transmission Interrupt Enable             */
+
+/*****************  Bit definition for FDCAN_ TXBCIE register  *******************/
+#define FDCAN_TXBCIE_CFIE_Pos     (0U)
+#define FDCAN_TXBCIE_CFIE_Msk     (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos)      /*!< 0xFFFFFFFF */
+#define FDCAN_TXBCIE_CFIE         FDCAN_TXBCIE_CFIE_Msk                        /*!<Cancellation Finished Interrupt Enable    */
+
+/*****************  Bit definition for FDCAN_TXEFC register  *********************/
+#define FDCAN_TXEFC_EFSA_Pos      (2U)
+#define FDCAN_TXEFC_EFSA_Msk      (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos)           /*!< 0x0000FFFC */
+#define FDCAN_TXEFC_EFSA          FDCAN_TXEFC_EFSA_Msk                         /*!<Event FIFO Start Address                  */
+#define FDCAN_TXEFC_EFS_Pos       (16U)
+#define FDCAN_TXEFC_EFS_Msk       (0x3FUL << FDCAN_TXEFC_EFS_Pos)              /*!< 0x003F0000 */
+#define FDCAN_TXEFC_EFS           FDCAN_TXEFC_EFS_Msk                          /*!<Event FIFO Size                           */
+#define FDCAN_TXEFC_EFWM_Pos      (24U)
+#define FDCAN_TXEFC_EFWM_Msk      (0x3FUL << FDCAN_TXEFC_EFWM_Pos)             /*!< 0x3F000000 */
+#define FDCAN_TXEFC_EFWM          FDCAN_TXEFC_EFWM_Msk                         /*!<Event FIFO Watermark                      */
+
+/*****************  Bit definition for FDCAN_TXEFS register  *********************/
+#define FDCAN_TXEFS_EFFL_Pos      (0U)
+#define FDCAN_TXEFS_EFFL_Msk      (0x3FUL << FDCAN_TXEFS_EFFL_Pos)             /*!< 0x0000003F */
+#define FDCAN_TXEFS_EFFL          FDCAN_TXEFS_EFFL_Msk                         /*!<Event FIFO Fill Level                     */
+#define FDCAN_TXEFS_EFGI_Pos      (8U)
+#define FDCAN_TXEFS_EFGI_Msk      (0x1FUL << FDCAN_TXEFS_EFGI_Pos)             /*!< 0x00001F00 */
+#define FDCAN_TXEFS_EFGI          FDCAN_TXEFS_EFGI_Msk                         /*!<Event FIFO Get Index                      */
+#define FDCAN_TXEFS_EFPI_Pos      (16U)
+#define FDCAN_TXEFS_EFPI_Msk      (0x1FUL << FDCAN_TXEFS_EFPI_Pos)             /*!< 0x001F0000 */
+#define FDCAN_TXEFS_EFPI          FDCAN_TXEFS_EFPI_Msk                         /*!<Event FIFO Put Index                      */
+#define FDCAN_TXEFS_EFF_Pos       (24U)
+#define FDCAN_TXEFS_EFF_Msk       (0x1UL << FDCAN_TXEFS_EFF_Pos)               /*!< 0x01000000 */
+#define FDCAN_TXEFS_EFF           FDCAN_TXEFS_EFF_Msk                          /*!<Event FIFO Full                           */
+#define FDCAN_TXEFS_TEFL_Pos      (25U)
+#define FDCAN_TXEFS_TEFL_Msk      (0x1UL << FDCAN_TXEFS_TEFL_Pos)              /*!< 0x02000000 */
+#define FDCAN_TXEFS_TEFL          FDCAN_TXEFS_TEFL_Msk                         /*!<Tx Event FIFO Element Lost                */
+
+/*****************  Bit definition for FDCAN_TXEFA register  *********************/
+#define FDCAN_TXEFA_EFAI_Pos      (0U)
+#define FDCAN_TXEFA_EFAI_Msk      (0x1FUL << FDCAN_TXEFA_EFAI_Pos)             /*!< 0x0000001F */
+#define FDCAN_TXEFA_EFAI          FDCAN_TXEFA_EFAI_Msk                         /*!<Event FIFO Acknowledge Index              */
+
+/*****************  Bit definition for FDCAN_TTTMC register  *********************/
+#define FDCAN_TTTMC_TMSA_Pos      (2U)
+#define FDCAN_TTTMC_TMSA_Msk      (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos)           /*!< 0x0000FFFC */
+#define FDCAN_TTTMC_TMSA          FDCAN_TTTMC_TMSA_Msk                         /*!<Trigger Memory Start Address              */
+#define FDCAN_TTTMC_TME_Pos       (16U)
+#define FDCAN_TTTMC_TME_Msk       (0x7FUL << FDCAN_TTTMC_TME_Pos)              /*!< 0x007F0000 */
+#define FDCAN_TTTMC_TME           FDCAN_TTTMC_TME_Msk                          /*!<Trigger Memory Elements                   */
+
+/*****************  Bit definition for FDCAN_TTRMC register  *********************/
+#define FDCAN_TTRMC_RID_Pos       (0U)
+#define FDCAN_TTRMC_RID_Msk       (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos)        /*!< 0x1FFFFFFF */
+#define FDCAN_TTRMC_RID           FDCAN_TTRMC_RID_Msk                          /*!<Reference Identifier                      */
+#define FDCAN_TTRMC_XTD_Pos       (30U)
+#define FDCAN_TTRMC_XTD_Msk       (0x1UL << FDCAN_TTRMC_XTD_Pos)               /*!< 0x40000000 */
+#define FDCAN_TTRMC_XTD           FDCAN_TTRMC_XTD_Msk                          /*!< Extended Identifier                      */
+#define FDCAN_TTRMC_RMPS_Pos      (31U)
+#define FDCAN_TTRMC_RMPS_Msk      (0x1UL << FDCAN_TTRMC_RMPS_Pos)              /*!< 0x80000000 */
+#define FDCAN_TTRMC_RMPS          FDCAN_TTRMC_RMPS_Msk                         /*!<Reference Message Payload Select          */
+
+/*****************  Bit definition for FDCAN_TTOCF register  *********************/
+#define FDCAN_TTOCF_OM_Pos        (0U)
+#define FDCAN_TTOCF_OM_Msk        (0x3UL << FDCAN_TTOCF_OM_Pos)                /*!< 0x00000003 */
+#define FDCAN_TTOCF_OM            FDCAN_TTOCF_OM_Msk                           /*!<Operation Mode                            */
+#define FDCAN_TTOCF_GEN_Pos       (3U)
+#define FDCAN_TTOCF_GEN_Msk       (0x1UL << FDCAN_TTOCF_GEN_Pos)               /*!< 0x00000008 */
+#define FDCAN_TTOCF_GEN           FDCAN_TTOCF_GEN_Msk                          /*!<Gap Enable                                */
+#define FDCAN_TTOCF_TM_Pos        (4U)
+#define FDCAN_TTOCF_TM_Msk        (0x1UL << FDCAN_TTOCF_TM_Pos)                /*!< 0x00000010 */
+#define FDCAN_TTOCF_TM            FDCAN_TTOCF_TM_Msk                           /*!<Time Master                               */
+#define FDCAN_TTOCF_LDSDL_Pos     (5U)
+#define FDCAN_TTOCF_LDSDL_Msk     (0x7UL << FDCAN_TTOCF_LDSDL_Pos)             /*!< 0x000000E0 */
+#define FDCAN_TTOCF_LDSDL         FDCAN_TTOCF_LDSDL_Msk                        /*!<LD of Synchronization Deviation Limit     */
+#define FDCAN_TTOCF_IRTO_Pos      (8U)
+#define FDCAN_TTOCF_IRTO_Msk      (0x7FUL << FDCAN_TTOCF_IRTO_Pos)             /*!< 0x00007F00 */
+#define FDCAN_TTOCF_IRTO          FDCAN_TTOCF_IRTO_Msk                         /*!<Initial Reference Trigger Offset          */
+#define FDCAN_TTOCF_EECS_Pos      (15U)
+#define FDCAN_TTOCF_EECS_Msk      (0x1UL << FDCAN_TTOCF_EECS_Pos)              /*!< 0x00008000 */
+#define FDCAN_TTOCF_EECS          FDCAN_TTOCF_EECS_Msk                         /*!<Enable External Clock Synchronization     */
+#define FDCAN_TTOCF_AWL_Pos       (16U)
+#define FDCAN_TTOCF_AWL_Msk       (0xFFUL << FDCAN_TTOCF_AWL_Pos)              /*!< 0x00FF0000 */
+#define FDCAN_TTOCF_AWL           FDCAN_TTOCF_AWL_Msk                          /*!<Application Watchdog Limit                */
+#define FDCAN_TTOCF_EGTF_Pos      (24U)
+#define FDCAN_TTOCF_EGTF_Msk      (0x1UL << FDCAN_TTOCF_EGTF_Pos)              /*!< 0x01000000 */
+#define FDCAN_TTOCF_EGTF          FDCAN_TTOCF_EGTF_Msk                         /*!<Enable Global Time Filtering              */
+#define FDCAN_TTOCF_ECC_Pos       (25U)
+#define FDCAN_TTOCF_ECC_Msk       (0x1UL << FDCAN_TTOCF_ECC_Pos)               /*!< 0x02000000 */
+#define FDCAN_TTOCF_ECC           FDCAN_TTOCF_ECC_Msk                          /*!<Enable Clock Calibration                  */
+#define FDCAN_TTOCF_EVTP_Pos      (26U)
+#define FDCAN_TTOCF_EVTP_Msk      (0x1UL << FDCAN_TTOCF_EVTP_Pos)              /*!< 0x04000000 */
+#define FDCAN_TTOCF_EVTP          FDCAN_TTOCF_EVTP_Msk                         /*!<Event Trigger Polarity                    */
+
+/*****************  Bit definition for FDCAN_TTMLM register  *********************/
+#define FDCAN_TTMLM_CCM_Pos       (0U)
+#define FDCAN_TTMLM_CCM_Msk       (0x3FUL << FDCAN_TTMLM_CCM_Pos)              /*!< 0x0000003F */
+#define FDCAN_TTMLM_CCM           FDCAN_TTMLM_CCM_Msk                          /*!<Cycle Count Max                           */
+#define FDCAN_TTMLM_CSS_Pos       (6U)
+#define FDCAN_TTMLM_CSS_Msk       (0x3UL << FDCAN_TTMLM_CSS_Pos)               /*!< 0x000000C0 */
+#define FDCAN_TTMLM_CSS           FDCAN_TTMLM_CSS_Msk                          /*!<Cycle Start Synchronization               */
+#define FDCAN_TTMLM_TXEW_Pos      (8U)
+#define FDCAN_TTMLM_TXEW_Msk      (0xFUL << FDCAN_TTMLM_TXEW_Pos)              /*!< 0x00000F00 */
+#define FDCAN_TTMLM_TXEW          FDCAN_TTMLM_TXEW_Msk                         /*!<Tx Enable Window                          */
+#define FDCAN_TTMLM_ENTT_Pos      (16U)
+#define FDCAN_TTMLM_ENTT_Msk      (0xFFFUL << FDCAN_TTMLM_ENTT_Pos)            /*!< 0x0FFF0000 */
+#define FDCAN_TTMLM_ENTT          FDCAN_TTMLM_ENTT_Msk                         /*!<Expected Number of Tx Triggers            */
+
+/*****************  Bit definition for FDCAN_TURCF register  *********************/
+#define FDCAN_TURCF_NCL_Pos       (0U)
+#define FDCAN_TURCF_NCL_Msk       (0xFFFFUL << FDCAN_TURCF_NCL_Pos)            /*!< 0x0000FFFF */
+#define FDCAN_TURCF_NCL           FDCAN_TURCF_NCL_Msk                          /*!<Numerator Configuration Low               */
+#define FDCAN_TURCF_DC_Pos        (16U)
+#define FDCAN_TURCF_DC_Msk        (0x3FFFUL << FDCAN_TURCF_DC_Pos)             /*!< 0x3FFF0000 */
+#define FDCAN_TURCF_DC            FDCAN_TURCF_DC_Msk                           /*!<Denominator Configuration                 */
+#define FDCAN_TURCF_ELT_Pos       (31U)
+#define FDCAN_TURCF_ELT_Msk       (0x1UL << FDCAN_TURCF_ELT_Pos)               /*!< 0x80000000 */
+#define FDCAN_TURCF_ELT           FDCAN_TURCF_ELT_Msk                          /*!<Enable Local Time                         */
+
+/*****************  Bit definition for FDCAN_TTOCN register  ********************/
+#define FDCAN_TTOCN_SGT_Pos       (0U)
+#define FDCAN_TTOCN_SGT_Msk       (0x1UL << FDCAN_TTOCN_SGT_Pos)               /*!< 0x00000001 */
+#define FDCAN_TTOCN_SGT           FDCAN_TTOCN_SGT_Msk                          /*!<Set Global time                           */
+#define FDCAN_TTOCN_ECS_Pos       (1U)
+#define FDCAN_TTOCN_ECS_Msk       (0x1UL << FDCAN_TTOCN_ECS_Pos)               /*!< 0x00000002 */
+#define FDCAN_TTOCN_ECS           FDCAN_TTOCN_ECS_Msk                          /*!<External Clock Synchronization            */
+#define FDCAN_TTOCN_SWP_Pos       (2U)
+#define FDCAN_TTOCN_SWP_Msk       (0x1UL << FDCAN_TTOCN_SWP_Pos)               /*!< 0x00000004 */
+#define FDCAN_TTOCN_SWP           FDCAN_TTOCN_SWP_Msk                          /*!<Stop Watch Polarity                       */
+#define FDCAN_TTOCN_SWS_Pos       (3U)
+#define FDCAN_TTOCN_SWS_Msk       (0x3UL << FDCAN_TTOCN_SWS_Pos)               /*!< 0x00000018 */
+#define FDCAN_TTOCN_SWS           FDCAN_TTOCN_SWS_Msk                          /*!<Stop Watch Source                         */
+#define FDCAN_TTOCN_RTIE_Pos      (5U)
+#define FDCAN_TTOCN_RTIE_Msk      (0x1UL << FDCAN_TTOCN_RTIE_Pos)              /*!< 0x00000020 */
+#define FDCAN_TTOCN_RTIE          FDCAN_TTOCN_RTIE_Msk                         /*!<Register Time Mark Interrupt Pulse Enable */
+#define FDCAN_TTOCN_TMC_Pos       (6U)
+#define FDCAN_TTOCN_TMC_Msk       (0x3UL << FDCAN_TTOCN_TMC_Pos)               /*!< 0x000000C0 */
+#define FDCAN_TTOCN_TMC           FDCAN_TTOCN_TMC_Msk                          /*!<Register Time Mark Compare                */
+#define FDCAN_TTOCN_TTIE_Pos      (8U)
+#define FDCAN_TTOCN_TTIE_Msk      (0x1UL << FDCAN_TTOCN_TTIE_Pos)              /*!< 0x00000100 */
+#define FDCAN_TTOCN_TTIE          FDCAN_TTOCN_TTIE_Msk                         /*!<Trigger Time Mark Interrupt Pulse Enable  */
+#define FDCAN_TTOCN_GCS_Pos       (9U)
+#define FDCAN_TTOCN_GCS_Msk       (0x1UL << FDCAN_TTOCN_GCS_Pos)               /*!< 0x00000200 */
+#define FDCAN_TTOCN_GCS           FDCAN_TTOCN_GCS_Msk                          /*!<Gap Control Select                        */
+#define FDCAN_TTOCN_FGP_Pos       (10U)
+#define FDCAN_TTOCN_FGP_Msk       (0x1UL << FDCAN_TTOCN_FGP_Pos)               /*!< 0x00000400 */
+#define FDCAN_TTOCN_FGP           FDCAN_TTOCN_FGP_Msk                          /*!<Finish Gap                                */
+#define FDCAN_TTOCN_TMG_Pos       (11U)
+#define FDCAN_TTOCN_TMG_Msk       (0x1UL << FDCAN_TTOCN_TMG_Pos)               /*!< 0x00000800 */
+#define FDCAN_TTOCN_TMG           FDCAN_TTOCN_TMG_Msk                          /*!<Time Mark Gap                             */
+#define FDCAN_TTOCN_NIG_Pos       (12U)
+#define FDCAN_TTOCN_NIG_Msk       (0x1UL << FDCAN_TTOCN_NIG_Pos)               /*!< 0x00001000 */
+#define FDCAN_TTOCN_NIG           FDCAN_TTOCN_NIG_Msk                          /*!<Next is Gap                               */
+#define FDCAN_TTOCN_ESCN_Pos      (13U)
+#define FDCAN_TTOCN_ESCN_Msk      (0x1UL << FDCAN_TTOCN_ESCN_Pos)              /*!< 0x00002000 */
+#define FDCAN_TTOCN_ESCN          FDCAN_TTOCN_ESCN_Msk                         /*!<External Synchronization Control          */
+#define FDCAN_TTOCN_LCKC_Pos      (15U)
+#define FDCAN_TTOCN_LCKC_Msk      (0x1UL << FDCAN_TTOCN_LCKC_Pos)              /*!< 0x00008000 */
+#define FDCAN_TTOCN_LCKC          FDCAN_TTOCN_LCKC_Msk                         /*!<TT Operation Control Register Locked      */
+
+/*****************  Bit definition for FDCAN_TTGTP register  ********************/
+#define FDCAN_TTGTP_TP_Pos        (0U)
+#define FDCAN_TTGTP_TP_Msk        (0xFFFFUL << FDCAN_TTGTP_TP_Pos)             /*!< 0x0000FFFF */
+#define FDCAN_TTGTP_TP            FDCAN_TTGTP_TP_Msk                           /*!<Time Preset                               */
+#define FDCAN_TTGTP_CTP_Pos       (16U)
+#define FDCAN_TTGTP_CTP_Msk       (0xFFFFUL << FDCAN_TTGTP_CTP_Pos)            /*!< 0xFFFF0000 */
+#define FDCAN_TTGTP_CTP           FDCAN_TTGTP_CTP_Msk                          /*!<Cycle Time Target Phase                   */
+
+/*****************  Bit definition for FDCAN_TTTMK register  ********************/
+#define FDCAN_TTTMK_TM_Pos        (0U)
+#define FDCAN_TTTMK_TM_Msk        (0xFFFFUL << FDCAN_TTTMK_TM_Pos)             /*!< 0x0000FFFF */
+#define FDCAN_TTTMK_TM            FDCAN_TTTMK_TM_Msk                           /*!<Time Mark                                 */
+#define FDCAN_TTTMK_TICC_Pos      (16U)
+#define FDCAN_TTTMK_TICC_Msk      (0x7FUL << FDCAN_TTTMK_TICC_Pos)             /*!< 0x007F0000 */
+#define FDCAN_TTTMK_TICC          FDCAN_TTTMK_TICC_Msk                         /*!<Time Mark Cycle Code                      */
+#define FDCAN_TTTMK_LCKM_Pos      (31U)
+#define FDCAN_TTTMK_LCKM_Msk      (0x1UL << FDCAN_TTTMK_LCKM_Pos)              /*!< 0x80000000 */
+#define FDCAN_TTTMK_LCKM          FDCAN_TTTMK_LCKM_Msk                         /*!<TT Time Mark Register Locked              */
+
+/*****************  Bit definition for FDCAN_TTIR register  ********************/
+#define FDCAN_TTIR_SBC_Pos        (0U)
+#define FDCAN_TTIR_SBC_Msk        (0x1UL << FDCAN_TTIR_SBC_Pos)                /*!< 0x00000001 */
+#define FDCAN_TTIR_SBC            FDCAN_TTIR_SBC_Msk                           /*!<Start of Basic Cycle                      */
+#define FDCAN_TTIR_SMC_Pos        (1U)
+#define FDCAN_TTIR_SMC_Msk        (0x1UL << FDCAN_TTIR_SMC_Pos)                /*!< 0x00000002 */
+#define FDCAN_TTIR_SMC            FDCAN_TTIR_SMC_Msk                           /*!<Start of Matrix Cycle                     */
+#define FDCAN_TTIR_CSM_Pos        (2U)
+#define FDCAN_TTIR_CSM_Msk        (0x1UL << FDCAN_TTIR_CSM_Pos)                /*!< 0x00000004 */
+#define FDCAN_TTIR_CSM            FDCAN_TTIR_CSM_Msk                           /*!<Change of Synchronization Mode            */
+#define FDCAN_TTIR_SOG_Pos        (3U)
+#define FDCAN_TTIR_SOG_Msk        (0x1UL << FDCAN_TTIR_SOG_Pos)                /*!< 0x00000008 */
+#define FDCAN_TTIR_SOG            FDCAN_TTIR_SOG_Msk                           /*!<Start of Gap                              */
+#define FDCAN_TTIR_RTMI_Pos       (4U)
+#define FDCAN_TTIR_RTMI_Msk       (0x1UL << FDCAN_TTIR_RTMI_Pos)               /*!< 0x00000010 */
+#define FDCAN_TTIR_RTMI           FDCAN_TTIR_RTMI_Msk                          /*!<Register Time Mark Interrupt              */
+#define FDCAN_TTIR_TTMI_Pos       (5U)
+#define FDCAN_TTIR_TTMI_Msk       (0x1UL << FDCAN_TTIR_TTMI_Pos)               /*!< 0x00000020 */
+#define FDCAN_TTIR_TTMI           FDCAN_TTIR_TTMI_Msk                          /*!<Trigger Time Mark Event Internal          */
+#define FDCAN_TTIR_SWE_Pos        (6U)
+#define FDCAN_TTIR_SWE_Msk        (0x1UL << FDCAN_TTIR_SWE_Pos)                /*!< 0x00000040 */
+#define FDCAN_TTIR_SWE            FDCAN_TTIR_SWE_Msk                           /*!<Stop Watch Event                          */
+#define FDCAN_TTIR_GTW_Pos        (7U)
+#define FDCAN_TTIR_GTW_Msk        (0x1UL << FDCAN_TTIR_GTW_Pos)                /*!< 0x00000080 */
+#define FDCAN_TTIR_GTW            FDCAN_TTIR_GTW_Msk                           /*!<Global Time Wrap                          */
+#define FDCAN_TTIR_GTD_Pos        (8U)
+#define FDCAN_TTIR_GTD_Msk        (0x1UL << FDCAN_TTIR_GTD_Pos)                /*!< 0x00000100 */
+#define FDCAN_TTIR_GTD            FDCAN_TTIR_GTD_Msk                           /*!<Global Time Discontinuity                 */
+#define FDCAN_TTIR_GTE_Pos        (9U)
+#define FDCAN_TTIR_GTE_Msk        (0x1UL << FDCAN_TTIR_GTE_Pos)                /*!< 0x00000200 */
+#define FDCAN_TTIR_GTE            FDCAN_TTIR_GTE_Msk                           /*!<Global Time Error                         */
+#define FDCAN_TTIR_TXU_Pos        (10U)
+#define FDCAN_TTIR_TXU_Msk        (0x1UL << FDCAN_TTIR_TXU_Pos)                /*!< 0x00000400 */
+#define FDCAN_TTIR_TXU            FDCAN_TTIR_TXU_Msk                           /*!<Tx Count Underflow                        */
+#define FDCAN_TTIR_TXO_Pos        (11U)
+#define FDCAN_TTIR_TXO_Msk        (0x1UL << FDCAN_TTIR_TXO_Pos)                /*!< 0x00000800 */
+#define FDCAN_TTIR_TXO            FDCAN_TTIR_TXO_Msk                           /*!<Tx Count Overflow                         */
+#define FDCAN_TTIR_SE1_Pos        (12U)
+#define FDCAN_TTIR_SE1_Msk        (0x1UL << FDCAN_TTIR_SE1_Pos)                /*!< 0x00001000 */
+#define FDCAN_TTIR_SE1            FDCAN_TTIR_SE1_Msk                           /*!<Scheduling Error 1                        */
+#define FDCAN_TTIR_SE2_Pos        (13U)
+#define FDCAN_TTIR_SE2_Msk        (0x1UL << FDCAN_TTIR_SE2_Pos)                /*!< 0x00002000 */
+#define FDCAN_TTIR_SE2            FDCAN_TTIR_SE2_Msk                           /*!<Scheduling Error 2                        */
+#define FDCAN_TTIR_ELC_Pos        (14U)
+#define FDCAN_TTIR_ELC_Msk        (0x1UL << FDCAN_TTIR_ELC_Pos)                /*!< 0x00004000 */
+#define FDCAN_TTIR_ELC            FDCAN_TTIR_ELC_Msk                           /*!<Error Level Changed                       */
+#define FDCAN_TTIR_IWT_Pos        (15U)
+#define FDCAN_TTIR_IWT_Msk        (0x1UL << FDCAN_TTIR_IWT_Pos)                /*!< 0x00008000 */
+#define FDCAN_TTIR_IWT            FDCAN_TTIR_IWT_Msk                           /*!<Initialization Watch Trigger              */
+#define FDCAN_TTIR_WT_Pos         (16U)
+#define FDCAN_TTIR_WT_Msk         (0x1UL << FDCAN_TTIR_WT_Pos)                 /*!< 0x00010000 */
+#define FDCAN_TTIR_WT             FDCAN_TTIR_WT_Msk                            /*!<Watch Trigger                             */
+#define FDCAN_TTIR_AW_Pos         (17U)
+#define FDCAN_TTIR_AW_Msk         (0x1UL << FDCAN_TTIR_AW_Pos)                 /*!< 0x00020000 */
+#define FDCAN_TTIR_AW             FDCAN_TTIR_AW_Msk                            /*!<Application Watchdog                      */
+#define FDCAN_TTIR_CER_Pos        (18U)
+#define FDCAN_TTIR_CER_Msk        (0x1UL << FDCAN_TTIR_CER_Pos)                /*!< 0x00040000 */
+#define FDCAN_TTIR_CER            FDCAN_TTIR_CER_Msk                           /*!<Configuration Error                       */
+
+/*****************  Bit definition for FDCAN_TTIE register  ********************/
+#define FDCAN_TTIE_SBCE_Pos       (0U)
+#define FDCAN_TTIE_SBCE_Msk       (0x1UL << FDCAN_TTIE_SBCE_Pos)               /*!< 0x00000001 */
+#define FDCAN_TTIE_SBCE           FDCAN_TTIE_SBCE_Msk                          /*!<Start of Basic Cycle Interrupt Enable             */
+#define FDCAN_TTIE_SMCE_Pos       (1U)
+#define FDCAN_TTIE_SMCE_Msk       (0x1UL << FDCAN_TTIE_SMCE_Pos)               /*!< 0x00000002 */
+#define FDCAN_TTIE_SMCE           FDCAN_TTIE_SMCE_Msk                          /*!<Start of Matrix Cycle Interrupt Enable            */
+#define FDCAN_TTIE_CSME_Pos       (2U)
+#define FDCAN_TTIE_CSME_Msk       (0x1UL << FDCAN_TTIE_CSME_Pos)               /*!< 0x00000004 */
+#define FDCAN_TTIE_CSME           FDCAN_TTIE_CSME_Msk                          /*!<Change of Synchronization Mode Interrupt Enable   */
+#define FDCAN_TTIE_SOGE_Pos       (3U)
+#define FDCAN_TTIE_SOGE_Msk       (0x1UL << FDCAN_TTIE_SOGE_Pos)               /*!< 0x00000008 */
+#define FDCAN_TTIE_SOGE           FDCAN_TTIE_SOGE_Msk                          /*!<Start of Gap Interrupt Enable                     */
+#define FDCAN_TTIE_RTMIE_Pos      (4U)
+#define FDCAN_TTIE_RTMIE_Msk      (0x1UL << FDCAN_TTIE_RTMIE_Pos)              /*!< 0x00000010 */
+#define FDCAN_TTIE_RTMIE          FDCAN_TTIE_RTMIE_Msk                         /*!<Register Time Mark Interrupt Interrupt Enable     */
+#define FDCAN_TTIE_TTMIE_Pos      (5U)
+#define FDCAN_TTIE_TTMIE_Msk      (0x1UL << FDCAN_TTIE_TTMIE_Pos)              /*!< 0x00000020 */
+#define FDCAN_TTIE_TTMIE          FDCAN_TTIE_TTMIE_Msk                         /*!<Trigger Time Mark Event Internal Interrupt Enable */
+#define FDCAN_TTIE_SWEE_Pos       (6U)
+#define FDCAN_TTIE_SWEE_Msk       (0x1UL << FDCAN_TTIE_SWEE_Pos)               /*!< 0x00000040 */
+#define FDCAN_TTIE_SWEE           FDCAN_TTIE_SWEE_Msk                          /*!<Stop Watch Event Interrupt Enable                 */
+#define FDCAN_TTIE_GTWE_Pos       (7U)
+#define FDCAN_TTIE_GTWE_Msk       (0x1UL << FDCAN_TTIE_GTWE_Pos)               /*!< 0x00000080 */
+#define FDCAN_TTIE_GTWE           FDCAN_TTIE_GTWE_Msk                          /*!<Global Time Wrap Interrupt Enable                 */
+#define FDCAN_TTIE_GTDE_Pos       (8U)
+#define FDCAN_TTIE_GTDE_Msk       (0x1UL << FDCAN_TTIE_GTDE_Pos)               /*!< 0x00000100 */
+#define FDCAN_TTIE_GTDE           FDCAN_TTIE_GTDE_Msk                          /*!<Global Time Discontinuity Interrupt Enable        */
+#define FDCAN_TTIE_GTEE_Pos       (9U)
+#define FDCAN_TTIE_GTEE_Msk       (0x1UL << FDCAN_TTIE_GTEE_Pos)               /*!< 0x00000200 */
+#define FDCAN_TTIE_GTEE           FDCAN_TTIE_GTEE_Msk                          /*!<Global Time Error Interrupt Enable                */
+#define FDCAN_TTIE_TXUE_Pos       (10U)
+#define FDCAN_TTIE_TXUE_Msk       (0x1UL << FDCAN_TTIE_TXUE_Pos)               /*!< 0x00000400 */
+#define FDCAN_TTIE_TXUE           FDCAN_TTIE_TXUE_Msk                          /*!<Tx Count Underflow Interrupt Enable               */
+#define FDCAN_TTIE_TXOE_Pos       (11U)
+#define FDCAN_TTIE_TXOE_Msk       (0x1UL << FDCAN_TTIE_TXOE_Pos)               /*!< 0x00000800 */
+#define FDCAN_TTIE_TXOE           FDCAN_TTIE_TXOE_Msk                          /*!<Tx Count Overflow Interrupt Enable                */
+#define FDCAN_TTIE_SE1E_Pos       (12U)
+#define FDCAN_TTIE_SE1E_Msk       (0x1UL << FDCAN_TTIE_SE1E_Pos)               /*!< 0x00001000 */
+#define FDCAN_TTIE_SE1E           FDCAN_TTIE_SE1E_Msk                          /*!<Scheduling Error 1 Interrupt Enable               */
+#define FDCAN_TTIE_SE2E_Pos       (13U)
+#define FDCAN_TTIE_SE2E_Msk       (0x1UL << FDCAN_TTIE_SE2E_Pos)               /*!< 0x00002000 */
+#define FDCAN_TTIE_SE2E           FDCAN_TTIE_SE2E_Msk                          /*!<Scheduling Error 2 Interrupt Enable               */
+#define FDCAN_TTIE_ELCE_Pos       (14U)
+#define FDCAN_TTIE_ELCE_Msk       (0x1UL << FDCAN_TTIE_ELCE_Pos)               /*!< 0x00004000 */
+#define FDCAN_TTIE_ELCE           FDCAN_TTIE_ELCE_Msk                          /*!<Error Level Changed Interrupt Enable              */
+#define FDCAN_TTIE_IWTE_Pos       (15U)
+#define FDCAN_TTIE_IWTE_Msk       (0x1UL << FDCAN_TTIE_IWTE_Pos)               /*!< 0x00008000 */
+#define FDCAN_TTIE_IWTE           FDCAN_TTIE_IWTE_Msk                          /*!<Initialization Watch Trigger Interrupt Enable     */
+#define FDCAN_TTIE_WTE_Pos        (16U)
+#define FDCAN_TTIE_WTE_Msk        (0x1UL << FDCAN_TTIE_WTE_Pos)                /*!< 0x00010000 */
+#define FDCAN_TTIE_WTE            FDCAN_TTIE_WTE_Msk                           /*!<Watch Trigger Interrupt Enable                    */
+#define FDCAN_TTIE_AWE_Pos        (17U)
+#define FDCAN_TTIE_AWE_Msk        (0x1UL << FDCAN_TTIE_AWE_Pos)                /*!< 0x00020000 */
+#define FDCAN_TTIE_AWE            FDCAN_TTIE_AWE_Msk                           /*!<Application Watchdog Interrupt Enable             */
+#define FDCAN_TTIE_CERE_Pos       (18U)
+#define FDCAN_TTIE_CERE_Msk       (0x1UL << FDCAN_TTIE_CERE_Pos)               /*!< 0x00040000 */
+#define FDCAN_TTIE_CERE           FDCAN_TTIE_CERE_Msk                          /*!<Configuration Error Interrupt Enable              */
+
+/*****************  Bit definition for FDCAN_TTILS register  ********************/
+#define FDCAN_TTILS_SBCS_Pos      (0U)
+#define FDCAN_TTILS_SBCS_Msk      (0x1UL << FDCAN_TTILS_SBCS_Pos)              /*!< 0x00000001 */
+#define FDCAN_TTILS_SBCS          FDCAN_TTILS_SBCS_Msk                         /*!<Start of Basic Cycle Interrupt Line               */
+#define FDCAN_TTILS_SMCS_Pos      (1U)
+#define FDCAN_TTILS_SMCS_Msk      (0x1UL << FDCAN_TTILS_SMCS_Pos)              /*!< 0x00000002 */
+#define FDCAN_TTILS_SMCS          FDCAN_TTILS_SMCS_Msk                         /*!<Start of Matrix Cycle Interrupt Line              */
+#define FDCAN_TTILS_CSMS_Pos      (2U)
+#define FDCAN_TTILS_CSMS_Msk      (0x1UL << FDCAN_TTILS_CSMS_Pos)              /*!< 0x00000004 */
+#define FDCAN_TTILS_CSMS          FDCAN_TTILS_CSMS_Msk                         /*!<Change of Synchronization Mode Interrupt Line     */
+#define FDCAN_TTILS_SOGS_Pos      (3U)
+#define FDCAN_TTILS_SOGS_Msk      (0x1UL << FDCAN_TTILS_SOGS_Pos)              /*!< 0x00000008 */
+#define FDCAN_TTILS_SOGS          FDCAN_TTILS_SOGS_Msk                         /*!<Start of Gap Interrupt Line                       */
+#define FDCAN_TTILS_RTMIS_Pos     (4U)
+#define FDCAN_TTILS_RTMIS_Msk     (0x1UL << FDCAN_TTILS_RTMIS_Pos)             /*!< 0x00000010 */
+#define FDCAN_TTILS_RTMIS         FDCAN_TTILS_RTMIS_Msk                        /*!<Register Time Mark Interrupt Interrupt Line       */
+#define FDCAN_TTILS_TTMIS_Pos     (5U)
+#define FDCAN_TTILS_TTMIS_Msk     (0x1UL << FDCAN_TTILS_TTMIS_Pos)             /*!< 0x00000020 */
+#define FDCAN_TTILS_TTMIS         FDCAN_TTILS_TTMIS_Msk                        /*!<Trigger Time Mark Event Internal Interrupt Line   */
+#define FDCAN_TTILS_SWES_Pos      (6U)
+#define FDCAN_TTILS_SWES_Msk      (0x1UL << FDCAN_TTILS_SWES_Pos)              /*!< 0x00000040 */
+#define FDCAN_TTILS_SWES          FDCAN_TTILS_SWES_Msk                         /*!<Stop Watch Event Interrupt Line                   */
+#define FDCAN_TTILS_GTWS_Pos      (7U)
+#define FDCAN_TTILS_GTWS_Msk      (0x1UL << FDCAN_TTILS_GTWS_Pos)              /*!< 0x00000080 */
+#define FDCAN_TTILS_GTWS          FDCAN_TTILS_GTWS_Msk                         /*!<Global Time Wrap Interrupt Line                   */
+#define FDCAN_TTILS_GTDS_Pos      (8U)
+#define FDCAN_TTILS_GTDS_Msk      (0x1UL << FDCAN_TTILS_GTDS_Pos)              /*!< 0x00000100 */
+#define FDCAN_TTILS_GTDS          FDCAN_TTILS_GTDS_Msk                         /*!<Global Time Discontinuity Interrupt Line          */
+#define FDCAN_TTILS_GTES_Pos      (9U)
+#define FDCAN_TTILS_GTES_Msk      (0x1UL << FDCAN_TTILS_GTES_Pos)              /*!< 0x00000200 */
+#define FDCAN_TTILS_GTES          FDCAN_TTILS_GTES_Msk                         /*!<Global Time Error Interrupt Line                  */
+#define FDCAN_TTILS_TXUS_Pos      (10U)
+#define FDCAN_TTILS_TXUS_Msk      (0x1UL << FDCAN_TTILS_TXUS_Pos)              /*!< 0x00000400 */
+#define FDCAN_TTILS_TXUS          FDCAN_TTILS_TXUS_Msk                         /*!<Tx Count Underflow Interrupt Line                 */
+#define FDCAN_TTILS_TXOS_Pos      (11U)
+#define FDCAN_TTILS_TXOS_Msk      (0x1UL << FDCAN_TTILS_TXOS_Pos)              /*!< 0x00000800 */
+#define FDCAN_TTILS_TXOS          FDCAN_TTILS_TXOS_Msk                         /*!<Tx Count Overflow Interrupt Line                  */
+#define FDCAN_TTILS_SE1S_Pos      (12U)
+#define FDCAN_TTILS_SE1S_Msk      (0x1UL << FDCAN_TTILS_SE1S_Pos)              /*!< 0x00001000 */
+#define FDCAN_TTILS_SE1S          FDCAN_TTILS_SE1S_Msk                         /*!<Scheduling Error 1 Interrupt Line                 */
+#define FDCAN_TTILS_SE2S_Pos      (13U)
+#define FDCAN_TTILS_SE2S_Msk      (0x1UL << FDCAN_TTILS_SE2S_Pos)              /*!< 0x00002000 */
+#define FDCAN_TTILS_SE2S          FDCAN_TTILS_SE2S_Msk                         /*!<Scheduling Error 2 Interrupt Line                 */
+#define FDCAN_TTILS_ELCS_Pos      (14U)
+#define FDCAN_TTILS_ELCS_Msk      (0x1UL << FDCAN_TTILS_ELCS_Pos)              /*!< 0x00004000 */
+#define FDCAN_TTILS_ELCS          FDCAN_TTILS_ELCS_Msk                         /*!<Error Level Changed Interrupt Line                */
+#define FDCAN_TTILS_IWTS_Pos      (15U)
+#define FDCAN_TTILS_IWTS_Msk      (0x1UL << FDCAN_TTILS_IWTS_Pos)              /*!< 0x00008000 */
+#define FDCAN_TTILS_IWTS          FDCAN_TTILS_IWTS_Msk                         /*!<Initialization Watch Trigger Interrupt Line       */
+#define FDCAN_TTILS_WTS_Pos       (16U)
+#define FDCAN_TTILS_WTS_Msk       (0x1UL << FDCAN_TTILS_WTS_Pos)               /*!< 0x00010000 */
+#define FDCAN_TTILS_WTS           FDCAN_TTILS_WTS_Msk                          /*!<Watch Trigger Interrupt Line                      */
+#define FDCAN_TTILS_AWS_Pos       (17U)
+#define FDCAN_TTILS_AWS_Msk       (0x1UL << FDCAN_TTILS_AWS_Pos)               /*!< 0x00020000 */
+#define FDCAN_TTILS_AWS           FDCAN_TTILS_AWS_Msk                          /*!<Application Watchdog Interrupt Line               */
+#define FDCAN_TTILS_CERS_Pos      (18U)
+#define FDCAN_TTILS_CERS_Msk      (0x1UL << FDCAN_TTILS_CERS_Pos)              /*!< 0x00040000 */
+#define FDCAN_TTILS_CERS          FDCAN_TTILS_CERS_Msk                         /*!<Configuration Error Interrupt Line                */
+
+/*****************  Bit definition for FDCAN_TTOST register  ********************/
+#define FDCAN_TTOST_EL_Pos        (0U)
+#define FDCAN_TTOST_EL_Msk        (0x3UL << FDCAN_TTOST_EL_Pos)                /*!< 0x00000003 */
+#define FDCAN_TTOST_EL            FDCAN_TTOST_EL_Msk                           /*!<Error Level                              */
+#define FDCAN_TTOST_MS_Pos        (2U)
+#define FDCAN_TTOST_MS_Msk        (0x3UL << FDCAN_TTOST_MS_Pos)                /*!< 0x0000000C */
+#define FDCAN_TTOST_MS            FDCAN_TTOST_MS_Msk                           /*!<Master State                             */
+#define FDCAN_TTOST_SYS_Pos       (4U)
+#define FDCAN_TTOST_SYS_Msk       (0x3UL << FDCAN_TTOST_SYS_Pos)               /*!< 0x00000030 */
+#define FDCAN_TTOST_SYS           FDCAN_TTOST_SYS_Msk                          /*!<Synchronization State                    */
+#define FDCAN_TTOST_QGTP_Pos      (6U)
+#define FDCAN_TTOST_QGTP_Msk      (0x1UL << FDCAN_TTOST_QGTP_Pos)              /*!< 0x00000040 */
+#define FDCAN_TTOST_QGTP          FDCAN_TTOST_QGTP_Msk                         /*!<Quality of Global Time Phase             */
+#define FDCAN_TTOST_QCS_Pos       (7U)
+#define FDCAN_TTOST_QCS_Msk       (0x1UL << FDCAN_TTOST_QCS_Pos)               /*!< 0x00000080 */
+#define FDCAN_TTOST_QCS           FDCAN_TTOST_QCS_Msk                          /*!<Quality of Clock Speed                   */
+#define FDCAN_TTOST_RTO_Pos       (8U)
+#define FDCAN_TTOST_RTO_Msk       (0xFFUL << FDCAN_TTOST_RTO_Pos)              /*!< 0x0000FF00 */
+#define FDCAN_TTOST_RTO           FDCAN_TTOST_RTO_Msk                          /*!<Reference Trigger Offset                 */
+#define FDCAN_TTOST_WGTD_Pos      (22U)
+#define FDCAN_TTOST_WGTD_Msk      (0x1UL << FDCAN_TTOST_WGTD_Pos)              /*!< 0x00400000 */
+#define FDCAN_TTOST_WGTD          FDCAN_TTOST_WGTD_Msk                         /*!<Wait for Global Time Discontinuity       */
+#define FDCAN_TTOST_GFI_Pos       (23U)
+#define FDCAN_TTOST_GFI_Msk       (0x1UL << FDCAN_TTOST_GFI_Pos)               /*!< 0x00800000 */
+#define FDCAN_TTOST_GFI           FDCAN_TTOST_GFI_Msk                          /*!<Gap Finished Indicator                   */
+#define FDCAN_TTOST_TMP_Pos       (24U)
+#define FDCAN_TTOST_TMP_Msk       (0x7UL << FDCAN_TTOST_TMP_Pos)               /*!< 0x07000000 */
+#define FDCAN_TTOST_TMP           FDCAN_TTOST_TMP_Msk                          /*!<Time Master Priority                     */
+#define FDCAN_TTOST_GSI_Pos       (27U)
+#define FDCAN_TTOST_GSI_Msk       (0x1UL << FDCAN_TTOST_GSI_Pos)               /*!< 0x08000000 */
+#define FDCAN_TTOST_GSI           FDCAN_TTOST_GSI_Msk                          /*!<Gap Started Indicator                    */
+#define FDCAN_TTOST_WFE_Pos       (28U)
+#define FDCAN_TTOST_WFE_Msk       (0x1UL << FDCAN_TTOST_WFE_Pos)               /*!< 0x10000000 */
+#define FDCAN_TTOST_WFE           FDCAN_TTOST_WFE_Msk                          /*!<Wait for Event                           */
+#define FDCAN_TTOST_AWE_Pos       (29U)
+#define FDCAN_TTOST_AWE_Msk       (0x1UL << FDCAN_TTOST_AWE_Pos)               /*!< 0x20000000 */
+#define FDCAN_TTOST_AWE           FDCAN_TTOST_AWE_Msk                          /*!<Application Watchdog Event               */
+#define FDCAN_TTOST_WECS_Pos      (30U)
+#define FDCAN_TTOST_WECS_Msk      (0x1UL << FDCAN_TTOST_WECS_Pos)              /*!< 0x40000000 */
+#define FDCAN_TTOST_WECS          FDCAN_TTOST_WECS_Msk                         /*!<Wait for External Clock Synchronization  */
+#define FDCAN_TTOST_SPL_Pos       (31U)
+#define FDCAN_TTOST_SPL_Msk       (0x1UL << FDCAN_TTOST_SPL_Pos)               /*!< 0x80000000 */
+#define FDCAN_TTOST_SPL           FDCAN_TTOST_SPL_Msk                          /*!<Schedule Phase Lock                      */
+
+/*****************  Bit definition for FDCAN_TURNA register  ********************/
+#define FDCAN_TURNA_NAV_Pos       (0U)
+#define FDCAN_TURNA_NAV_Msk       (0x3FFFFUL << FDCAN_TURNA_NAV_Pos)           /*!< 0x0003FFFF */
+#define FDCAN_TURNA_NAV           FDCAN_TURNA_NAV_Msk                          /*!<Numerator Actual Value                   */
+
+/*****************  Bit definition for FDCAN_TTLGT register  ********************/
+#define FDCAN_TTLGT_LT_Pos        (0U)
+#define FDCAN_TTLGT_LT_Msk        (0xFFFFUL << FDCAN_TTLGT_LT_Pos)             /*!< 0x0000FFFF */
+#define FDCAN_TTLGT_LT            FDCAN_TTLGT_LT_Msk                           /*!<Local Time                               */
+#define FDCAN_TTLGT_GT_Pos        (16U)
+#define FDCAN_TTLGT_GT_Msk        (0xFFFFUL << FDCAN_TTLGT_GT_Pos)             /*!< 0xFFFF0000 */
+#define FDCAN_TTLGT_GT            FDCAN_TTLGT_GT_Msk                           /*!<Global Time                              */
+
+/*****************  Bit definition for FDCAN_TTCTC register  ********************/
+#define FDCAN_TTCTC_CT_Pos        (0U)
+#define FDCAN_TTCTC_CT_Msk        (0xFFFFUL << FDCAN_TTCTC_CT_Pos)             /*!< 0x0000FFFF */
+#define FDCAN_TTCTC_CT            FDCAN_TTCTC_CT_Msk                           /*!<Cycle Time                               */
+#define FDCAN_TTCTC_CC_Pos        (16U)
+#define FDCAN_TTCTC_CC_Msk        (0x3FUL << FDCAN_TTCTC_CC_Pos)               /*!< 0x003F0000 */
+#define FDCAN_TTCTC_CC            FDCAN_TTCTC_CC_Msk                           /*!<Cycle Count                              */
+
+/*****************  Bit definition for FDCAN_TTCPT register  ********************/
+#define FDCAN_TTCPT_CCV_Pos       (0U)
+#define FDCAN_TTCPT_CCV_Msk       (0x3FUL << FDCAN_TTCPT_CCV_Pos)              /*!< 0x0000003F */
+#define FDCAN_TTCPT_CCV           FDCAN_TTCPT_CCV_Msk                          /*!<Cycle Count Value                        */
+#define FDCAN_TTCPT_SWV_Pos       (16U)
+#define FDCAN_TTCPT_SWV_Msk       (0xFFFFUL << FDCAN_TTCPT_SWV_Pos)            /*!< 0xFFFF0000 */
+#define FDCAN_TTCPT_SWV           FDCAN_TTCPT_SWV_Msk                          /*!<Stop Watch Value                         */
+
+/*****************  Bit definition for FDCAN_TTCSM register  ********************/
+#define FDCAN_TTCSM_CSM_Pos       (0U)
+#define FDCAN_TTCSM_CSM_Msk       (0xFFFFUL << FDCAN_TTCSM_CSM_Pos)            /*!< 0x0000FFFF */
+#define FDCAN_TTCSM_CSM           FDCAN_TTCSM_CSM_Msk                          /*!<Cycle Sync Mark                          */
+
+/*****************  Bit definition for FDCAN_TTTS register  *********************/
+#define FDCAN_TTTS_SWTSEL_Pos     (0U)
+#define FDCAN_TTTS_SWTSEL_Msk     (0x3UL << FDCAN_TTTS_SWTSEL_Pos)             /*!< 0x00000003 */
+#define FDCAN_TTTS_SWTSEL         FDCAN_TTTS_SWTSEL_Msk                        /*!<Stop watch trigger input selection       */
+#define FDCAN_TTTS_EVTSEL_Pos     (4U)
+#define FDCAN_TTTS_EVTSEL_Msk     (0x3UL << FDCAN_TTTS_EVTSEL_Pos)             /*!< 0x00000030 */
+#define FDCAN_TTTS_EVTSEL         FDCAN_TTTS_EVTSEL_Msk                        /*!<Event trigger input selection            */
+
+/********************************************************************************/
+/*                                                                              */
+/*                      FDCANCCU (Clock Calibration unit)                       */
+/*                                                                              */
+/********************************************************************************/
+
+/*****************  Bit definition for FDCANCCU_CREL register  ******************/
+#define FDCANCCU_CREL_DAY_Pos        (0U)
+#define FDCANCCU_CREL_DAY_Msk        (0xFFUL << FDCANCCU_CREL_DAY_Pos)         /*!< 0x000000FF */
+#define FDCANCCU_CREL_DAY            FDCANCCU_CREL_DAY_Msk                     /*!<Timestamp Day                           */
+#define FDCANCCU_CREL_MON_Pos        (8U)
+#define FDCANCCU_CREL_MON_Msk        (0xFFUL << FDCANCCU_CREL_MON_Pos)         /*!< 0x0000FF00 */
+#define FDCANCCU_CREL_MON            FDCANCCU_CREL_MON_Msk                     /*!<Timestamp Month                         */
+#define FDCANCCU_CREL_YEAR_Pos       (16U)
+#define FDCANCCU_CREL_YEAR_Msk       (0xFUL << FDCANCCU_CREL_YEAR_Pos)         /*!< 0x000F0000 */
+#define FDCANCCU_CREL_YEAR           FDCANCCU_CREL_YEAR_Msk                    /*!<Timestamp Year                          */
+#define FDCANCCU_CREL_SUBSTEP_Pos    (20U)
+#define FDCANCCU_CREL_SUBSTEP_Msk    (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos)      /*!< 0x00F00000 */
+#define FDCANCCU_CREL_SUBSTEP        FDCANCCU_CREL_SUBSTEP_Msk                 /*!<Sub-step of Core release                */
+#define FDCANCCU_CREL_STEP_Pos       (24U)
+#define FDCANCCU_CREL_STEP_Msk       (0xFUL << FDCANCCU_CREL_STEP_Pos)         /*!< 0x0F000000 */
+#define FDCANCCU_CREL_STEP           FDCANCCU_CREL_STEP_Msk                    /*!<Step of Core release                    */
+#define FDCANCCU_CREL_REL_Pos        (28U)
+#define FDCANCCU_CREL_REL_Msk        (0xFUL << FDCANCCU_CREL_REL_Pos)          /*!< 0xF0000000 */
+#define FDCANCCU_CREL_REL            FDCANCCU_CREL_REL_Msk                     /*!<Core release                            */
+
+/*****************  Bit definition for FDCANCCU_CCFG register  ******************/
+#define FDCANCCU_CCFG_TQBT_Pos       (0U)
+#define FDCANCCU_CCFG_TQBT_Msk       (0x1FUL << FDCANCCU_CCFG_TQBT_Pos)        /*!< 0x0000001F */
+#define FDCANCCU_CCFG_TQBT           FDCANCCU_CCFG_TQBT_Msk                    /*!<Time Quanta per Bit Time                */
+#define FDCANCCU_CCFG_BCC_Pos        (6U)
+#define FDCANCCU_CCFG_BCC_Msk        (0x1UL << FDCANCCU_CCFG_BCC_Pos)          /*!< 0x00000040 */
+#define FDCANCCU_CCFG_BCC            FDCANCCU_CCFG_BCC_Msk                     /*!<Bypass Clock Calibration                */
+#define FDCANCCU_CCFG_CFL_Pos        (7U)
+#define FDCANCCU_CCFG_CFL_Msk        (0x1UL << FDCANCCU_CCFG_CFL_Pos)          /*!< 0x00000080 */
+#define FDCANCCU_CCFG_CFL            FDCANCCU_CCFG_CFL_Msk                     /*!<Calibration Field Length                */
+#define FDCANCCU_CCFG_OCPM_Pos       (8U)
+#define FDCANCCU_CCFG_OCPM_Msk       (0xFFUL << FDCANCCU_CCFG_OCPM_Pos)        /*!< 0x0000FF00 */
+#define FDCANCCU_CCFG_OCPM           FDCANCCU_CCFG_OCPM_Msk                    /*!<Oscillator Clock Periods Minimum        */
+#define FDCANCCU_CCFG_CDIV_Pos       (16U)
+#define FDCANCCU_CCFG_CDIV_Msk       (0xFUL << FDCANCCU_CCFG_CDIV_Pos)         /*!< 0x000F0000 */
+#define FDCANCCU_CCFG_CDIV           FDCANCCU_CCFG_CDIV_Msk                    /*!<Clock Divider                           */
+#define FDCANCCU_CCFG_SWR_Pos        (31U)
+#define FDCANCCU_CCFG_SWR_Msk        (0x1UL << FDCANCCU_CCFG_SWR_Pos)          /*!< 0x80000000 */
+#define FDCANCCU_CCFG_SWR            FDCANCCU_CCFG_SWR_Msk                     /*!<Software Reset                          */
+
+/*****************  Bit definition for FDCANCCU_CSTAT register  *****************/
+#define FDCANCCU_CSTAT_OCPC_Pos      (0U)
+#define FDCANCCU_CSTAT_OCPC_Msk      (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos)    /*!< 0x0003FFFF */
+#define FDCANCCU_CSTAT_OCPC          FDCANCCU_CSTAT_OCPC_Msk                   /*!<Oscillator Clock Period Counter        */
+#define FDCANCCU_CSTAT_TQC_Pos       (18U)
+#define FDCANCCU_CSTAT_TQC_Msk       (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos)       /*!< 0x1FFC0000 */
+#define FDCANCCU_CSTAT_TQC           FDCANCCU_CSTAT_TQC_Msk                    /*!<Time Quanta Counter                    */
+#define FDCANCCU_CSTAT_CALS_Pos      (30U)
+#define FDCANCCU_CSTAT_CALS_Msk      (0x3UL << FDCANCCU_CSTAT_CALS_Pos)        /*!< 0xC0000000 */
+#define FDCANCCU_CSTAT_CALS          FDCANCCU_CSTAT_CALS_Msk                   /*!<Calibration State                      */
+
+/******************  Bit definition for FDCANCCU_CWD register  ******************/
+#define FDCANCCU_CWD_WDC_Pos         (0U)
+#define FDCANCCU_CWD_WDC_Msk         (0xFFFFUL << FDCANCCU_CWD_WDC_Pos)        /*!< 0x0000FFFF */
+#define FDCANCCU_CWD_WDC             FDCANCCU_CWD_WDC_Msk                      /*!<Watchdog Configuration                 */
+#define FDCANCCU_CWD_WDV_Pos         (16U)
+#define FDCANCCU_CWD_WDV_Msk         (0xFFFFUL << FDCANCCU_CWD_WDV_Pos)        /*!< 0xFFFF0000 */
+#define FDCANCCU_CWD_WDV             FDCANCCU_CWD_WDV_Msk                      /*!<Watchdog Value                         */
+
+/******************  Bit definition for FDCANCCU_IR register  *******************/
+#define FDCANCCU_IR_CWE_Pos          (0U)
+#define FDCANCCU_IR_CWE_Msk          (0x1UL << FDCANCCU_IR_CWE_Pos)            /*!< 0x00000001 */
+#define FDCANCCU_IR_CWE              FDCANCCU_IR_CWE_Msk                       /*!<Calibration Watchdog Event             */
+#define FDCANCCU_IR_CSC_Pos          (1U)
+#define FDCANCCU_IR_CSC_Msk          (0x1UL << FDCANCCU_IR_CSC_Pos)            /*!< 0x00000002 */
+#define FDCANCCU_IR_CSC              FDCANCCU_IR_CSC_Msk                       /*!<Calibration State Changed              */
+
+/******************  Bit definition for FDCANCCU_IE register  *******************/
+#define FDCANCCU_IE_CWEE_Pos         (0U)
+#define FDCANCCU_IE_CWEE_Msk         (0x1UL << FDCANCCU_IE_CWEE_Pos)           /*!< 0x00000001 */
+#define FDCANCCU_IE_CWEE             FDCANCCU_IE_CWEE_Msk                      /*!<Calibration Watchdog Event Enable      */
+#define FDCANCCU_IE_CSCE_Pos         (1U)
+#define FDCANCCU_IE_CSCE_Msk         (0x1UL << FDCANCCU_IE_CSCE_Pos)           /*!< 0x00000002 */
+#define FDCANCCU_IE_CSCE             FDCANCCU_IE_CSCE_Msk                      /*!<Calibration State Changed Enable       */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          HDMI-CEC (CEC)                                    */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for CEC_CR register  *********************/
+#define CEC_CR_CECEN_Pos         (0U)
+#define CEC_CR_CECEN_Msk         (0x1UL << CEC_CR_CECEN_Pos)                   /*!< 0x00000001 */
+#define CEC_CR_CECEN             CEC_CR_CECEN_Msk                              /*!< CEC Enable                                */
+#define CEC_CR_TXSOM_Pos         (1U)
+#define CEC_CR_TXSOM_Msk         (0x1UL << CEC_CR_TXSOM_Pos)                   /*!< 0x00000002 */
+#define CEC_CR_TXSOM             CEC_CR_TXSOM_Msk                              /*!< CEC Tx Start Of Message                   */
+#define CEC_CR_TXEOM_Pos         (2U)
+#define CEC_CR_TXEOM_Msk         (0x1UL << CEC_CR_TXEOM_Pos)                   /*!< 0x00000004 */
+#define CEC_CR_TXEOM             CEC_CR_TXEOM_Msk                              /*!< CEC Tx End Of Message                     */
+
+/*******************  Bit definition for CEC_CFGR register  *******************/
+#define CEC_CFGR_SFT_Pos         (0U)
+#define CEC_CFGR_SFT_Msk         (0x7UL << CEC_CFGR_SFT_Pos)                   /*!< 0x00000007 */
+#define CEC_CFGR_SFT             CEC_CFGR_SFT_Msk                              /*!< CEC Signal Free Time                      */
+#define CEC_CFGR_RXTOL_Pos       (3U)
+#define CEC_CFGR_RXTOL_Msk       (0x1UL << CEC_CFGR_RXTOL_Pos)                 /*!< 0x00000008 */
+#define CEC_CFGR_RXTOL           CEC_CFGR_RXTOL_Msk                            /*!< CEC Tolerance                             */
+#define CEC_CFGR_BRESTP_Pos      (4U)
+#define CEC_CFGR_BRESTP_Msk      (0x1UL << CEC_CFGR_BRESTP_Pos)                /*!< 0x00000010 */
+#define CEC_CFGR_BRESTP          CEC_CFGR_BRESTP_Msk                           /*!< CEC Rx Stop                               */
+#define CEC_CFGR_BREGEN_Pos      (5U)
+#define CEC_CFGR_BREGEN_Msk      (0x1UL << CEC_CFGR_BREGEN_Pos)                /*!< 0x00000020 */
+#define CEC_CFGR_BREGEN          CEC_CFGR_BREGEN_Msk                           /*!< CEC Bit Rising Error generation           */
+#define CEC_CFGR_LBPEGEN_Pos     (6U)
+#define CEC_CFGR_LBPEGEN_Msk     (0x1UL << CEC_CFGR_LBPEGEN_Pos)               /*!< 0x00000040 */
+#define CEC_CFGR_LBPEGEN         CEC_CFGR_LBPEGEN_Msk                          /*!< CEC Long Bit Period Error generation      */
+#define CEC_CFGR_SFTOPT_Pos      (8U)
+#define CEC_CFGR_SFTOPT_Msk      (0x1UL << CEC_CFGR_SFTOPT_Pos)                /*!< 0x00000100 */
+#define CEC_CFGR_SFTOPT          CEC_CFGR_SFTOPT_Msk                           /*!< CEC Signal Free Time optional             */
+#define CEC_CFGR_BRDNOGEN_Pos    (7U)
+#define CEC_CFGR_BRDNOGEN_Msk    (0x1UL << CEC_CFGR_BRDNOGEN_Pos)              /*!< 0x00000080 */
+#define CEC_CFGR_BRDNOGEN        CEC_CFGR_BRDNOGEN_Msk                         /*!< CEC Broadcast No error generation         */
+#define CEC_CFGR_OAR_Pos         (16U)
+#define CEC_CFGR_OAR_Msk         (0x7FFFUL << CEC_CFGR_OAR_Pos)                /*!< 0x7FFF0000 */
+#define CEC_CFGR_OAR             CEC_CFGR_OAR_Msk                              /*!< CEC Own Address                           */
+#define CEC_CFGR_LSTN_Pos        (31U)
+#define CEC_CFGR_LSTN_Msk        (0x1UL << CEC_CFGR_LSTN_Pos)                  /*!< 0x80000000 */
+#define CEC_CFGR_LSTN            CEC_CFGR_LSTN_Msk                             /*!< CEC Listen mode                           */
+
+/*******************  Bit definition for CEC_TXDR register  *******************/
+#define CEC_TXDR_TXD_Pos         (0U)
+#define CEC_TXDR_TXD_Msk         (0xFFUL << CEC_TXDR_TXD_Pos)                  /*!< 0x000000FF */
+#define CEC_TXDR_TXD             CEC_TXDR_TXD_Msk                              /*!< CEC Tx Data                               */
+
+/*******************  Bit definition for CEC_RXDR register  *******************/
+#define CEC_RXDR_RXD_Pos         (0U)
+#define CEC_RXDR_RXD_Msk         (0xFFUL << CEC_RXDR_RXD_Pos)                  /*!< 0x000000FF */
+#define CEC_RXDR_RXD             CEC_RXDR_RXD_Msk                              /*!< CEC Rx Data                               */
+
+/*******************  Bit definition for CEC_ISR register  ********************/
+#define CEC_ISR_RXBR_Pos         (0U)
+#define CEC_ISR_RXBR_Msk         (0x1UL << CEC_ISR_RXBR_Pos)                   /*!< 0x00000001 */
+#define CEC_ISR_RXBR             CEC_ISR_RXBR_Msk                              /*!< CEC Rx-Byte Received                      */
+#define CEC_ISR_RXEND_Pos        (1U)
+#define CEC_ISR_RXEND_Msk        (0x1UL << CEC_ISR_RXEND_Pos)                  /*!< 0x00000002 */
+#define CEC_ISR_RXEND            CEC_ISR_RXEND_Msk                             /*!< CEC End Of Reception                      */
+#define CEC_ISR_RXOVR_Pos        (2U)
+#define CEC_ISR_RXOVR_Msk        (0x1UL << CEC_ISR_RXOVR_Pos)                  /*!< 0x00000004 */
+#define CEC_ISR_RXOVR            CEC_ISR_RXOVR_Msk                             /*!< CEC Rx-Overrun                            */
+#define CEC_ISR_BRE_Pos          (3U)
+#define CEC_ISR_BRE_Msk          (0x1UL << CEC_ISR_BRE_Pos)                    /*!< 0x00000008 */
+#define CEC_ISR_BRE              CEC_ISR_BRE_Msk                               /*!< CEC Rx Bit Rising Error                   */
+#define CEC_ISR_SBPE_Pos         (4U)
+#define CEC_ISR_SBPE_Msk         (0x1UL << CEC_ISR_SBPE_Pos)                   /*!< 0x00000010 */
+#define CEC_ISR_SBPE             CEC_ISR_SBPE_Msk                              /*!< CEC Rx Short Bit period Error             */
+#define CEC_ISR_LBPE_Pos         (5U)
+#define CEC_ISR_LBPE_Msk         (0x1UL << CEC_ISR_LBPE_Pos)                   /*!< 0x00000020 */
+#define CEC_ISR_LBPE             CEC_ISR_LBPE_Msk                              /*!< CEC Rx Long Bit period Error              */
+#define CEC_ISR_RXACKE_Pos       (6U)
+#define CEC_ISR_RXACKE_Msk       (0x1UL << CEC_ISR_RXACKE_Pos)                 /*!< 0x00000040 */
+#define CEC_ISR_RXACKE           CEC_ISR_RXACKE_Msk                            /*!< CEC Rx Missing Acknowledge                */
+#define CEC_ISR_ARBLST_Pos       (7U)
+#define CEC_ISR_ARBLST_Msk       (0x1UL << CEC_ISR_ARBLST_Pos)                 /*!< 0x00000080 */
+#define CEC_ISR_ARBLST           CEC_ISR_ARBLST_Msk                            /*!< CEC Arbitration Lost                      */
+#define CEC_ISR_TXBR_Pos         (8U)
+#define CEC_ISR_TXBR_Msk         (0x1UL << CEC_ISR_TXBR_Pos)                   /*!< 0x00000100 */
+#define CEC_ISR_TXBR             CEC_ISR_TXBR_Msk                              /*!< CEC Tx Byte Request                       */
+#define CEC_ISR_TXEND_Pos        (9U)
+#define CEC_ISR_TXEND_Msk        (0x1UL << CEC_ISR_TXEND_Pos)                  /*!< 0x00000200 */
+#define CEC_ISR_TXEND            CEC_ISR_TXEND_Msk                             /*!< CEC End of Transmission                   */
+#define CEC_ISR_TXUDR_Pos        (10U)
+#define CEC_ISR_TXUDR_Msk        (0x1UL << CEC_ISR_TXUDR_Pos)                  /*!< 0x00000400 */
+#define CEC_ISR_TXUDR            CEC_ISR_TXUDR_Msk                             /*!< CEC Tx-Buffer Underrun                    */
+#define CEC_ISR_TXERR_Pos        (11U)
+#define CEC_ISR_TXERR_Msk        (0x1UL << CEC_ISR_TXERR_Pos)                  /*!< 0x00000800 */
+#define CEC_ISR_TXERR            CEC_ISR_TXERR_Msk                             /*!< CEC Tx-Error                              */
+#define CEC_ISR_TXACKE_Pos       (12U)
+#define CEC_ISR_TXACKE_Msk       (0x1UL << CEC_ISR_TXACKE_Pos)                 /*!< 0x00001000 */
+#define CEC_ISR_TXACKE           CEC_ISR_TXACKE_Msk                            /*!< CEC Tx Missing Acknowledge                */
+
+/*******************  Bit definition for CEC_IER register  ********************/
+#define CEC_IER_RXBRIE_Pos       (0U)
+#define CEC_IER_RXBRIE_Msk       (0x1UL << CEC_IER_RXBRIE_Pos)                 /*!< 0x00000001 */
+#define CEC_IER_RXBRIE           CEC_IER_RXBRIE_Msk                            /*!< CEC Rx-Byte Received IT Enable            */
+#define CEC_IER_RXENDIE_Pos      (1U)
+#define CEC_IER_RXENDIE_Msk      (0x1UL << CEC_IER_RXENDIE_Pos)                /*!< 0x00000002 */
+#define CEC_IER_RXENDIE          CEC_IER_RXENDIE_Msk                           /*!< CEC End Of Reception IT Enable            */
+#define CEC_IER_RXOVRIE_Pos      (2U)
+#define CEC_IER_RXOVRIE_Msk      (0x1UL << CEC_IER_RXOVRIE_Pos)                /*!< 0x00000004 */
+#define CEC_IER_RXOVRIE          CEC_IER_RXOVRIE_Msk                           /*!< CEC Rx-Overrun IT Enable                  */
+#define CEC_IER_BREIE_Pos        (3U)
+#define CEC_IER_BREIE_Msk        (0x1UL << CEC_IER_BREIE_Pos)                  /*!< 0x00000008 */
+#define CEC_IER_BREIE            CEC_IER_BREIE_Msk                             /*!< CEC Rx Bit Rising Error IT Enable         */
+#define CEC_IER_SBPEIE_Pos       (4U)
+#define CEC_IER_SBPEIE_Msk       (0x1UL << CEC_IER_SBPEIE_Pos)                 /*!< 0x00000010 */
+#define CEC_IER_SBPEIE           CEC_IER_SBPEIE_Msk                            /*!< CEC Rx Short Bit period Error IT Enable   */
+#define CEC_IER_LBPEIE_Pos       (5U)
+#define CEC_IER_LBPEIE_Msk       (0x1UL << CEC_IER_LBPEIE_Pos)                 /*!< 0x00000020 */
+#define CEC_IER_LBPEIE           CEC_IER_LBPEIE_Msk                            /*!< CEC Rx Long Bit period Error IT Enable    */
+#define CEC_IER_RXACKEIE_Pos     (6U)
+#define CEC_IER_RXACKEIE_Msk     (0x1UL << CEC_IER_RXACKEIE_Pos)               /*!< 0x00000040 */
+#define CEC_IER_RXACKEIE         CEC_IER_RXACKEIE_Msk                          /*!< CEC Rx Missing Acknowledge IT Enable      */
+#define CEC_IER_ARBLSTIE_Pos     (7U)
+#define CEC_IER_ARBLSTIE_Msk     (0x1UL << CEC_IER_ARBLSTIE_Pos)               /*!< 0x00000080 */
+#define CEC_IER_ARBLSTIE         CEC_IER_ARBLSTIE_Msk                          /*!< CEC Arbitration Lost IT Enable            */
+#define CEC_IER_TXBRIE_Pos       (8U)
+#define CEC_IER_TXBRIE_Msk       (0x1UL << CEC_IER_TXBRIE_Pos)                 /*!< 0x00000100 */
+#define CEC_IER_TXBRIE           CEC_IER_TXBRIE_Msk                            /*!< CEC Tx Byte Request  IT Enable            */
+#define CEC_IER_TXENDIE_Pos      (9U)
+#define CEC_IER_TXENDIE_Msk      (0x1UL << CEC_IER_TXENDIE_Pos)                /*!< 0x00000200 */
+#define CEC_IER_TXENDIE          CEC_IER_TXENDIE_Msk                           /*!< CEC End of Transmission IT Enable         */
+#define CEC_IER_TXUDRIE_Pos      (10U)
+#define CEC_IER_TXUDRIE_Msk      (0x1UL << CEC_IER_TXUDRIE_Pos)                /*!< 0x00000400 */
+#define CEC_IER_TXUDRIE          CEC_IER_TXUDRIE_Msk                           /*!< CEC Tx-Buffer Underrun IT Enable          */
+#define CEC_IER_TXERRIE_Pos      (11U)
+#define CEC_IER_TXERRIE_Msk      (0x1UL << CEC_IER_TXERRIE_Pos)                /*!< 0x00000800 */
+#define CEC_IER_TXERRIE          CEC_IER_TXERRIE_Msk                           /*!< CEC Tx-Error IT Enable                    */
+#define CEC_IER_TXACKEIE_Pos     (12U)
+#define CEC_IER_TXACKEIE_Msk     (0x1UL << CEC_IER_TXACKEIE_Pos)               /*!< 0x00001000 */
+#define CEC_IER_TXACKEIE         CEC_IER_TXACKEIE_Msk                          /*!< CEC Tx Missing Acknowledge IT Enable      */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRC calculation unit                              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CRC_DR register  *********************/
+#define CRC_DR_DR_Pos            (0U)
+#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)               /*!< 0xFFFFFFFF */
+#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define CRC_IDR_IDR_Pos          (0U)
+#define CRC_IDR_IDR_Msk          (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)             /*!< 0xFFFFFFFF */
+#define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 32-bit data register bits */
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define CRC_CR_RESET_Pos         (0U)
+#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                   /*!< 0x00000001 */
+#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE_Pos      (3U)
+#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000018 */
+#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
+#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
+#define CRC_CR_REV_IN_Pos        (5U)
+#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000060 */
+#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
+#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
+#define CRC_CR_REV_OUT_Pos       (7U)
+#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                 /*!< 0x00000080 */
+#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
+
+/*******************  Bit definition for CRC_INIT register  *******************/
+#define CRC_INIT_INIT_Pos        (0U)
+#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)           /*!< 0xFFFFFFFF */
+#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
+
+/*******************  Bit definition for CRC_POL register  ********************/
+#define CRC_POL_POL_Pos          (0U)
+#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)             /*!< 0xFFFFFFFF */
+#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRS Clock Recovery System                         */
+/******************************************************************************/
+
+/*******************  Bit definition for CRS_CR register  *********************/
+#define CRS_CR_SYNCOKIE_Pos       (0U)
+#define CRS_CR_SYNCOKIE_Msk       (0x1UL << CRS_CR_SYNCOKIE_Pos)               /*!< 0x00000001 */
+#define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /*!< SYNC event OK interrupt enable */
+#define CRS_CR_SYNCWARNIE_Pos     (1U)
+#define CRS_CR_SYNCWARNIE_Msk     (0x1UL << CRS_CR_SYNCWARNIE_Pos)             /*!< 0x00000002 */
+#define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /*!< SYNC warning interrupt enable */
+#define CRS_CR_ERRIE_Pos          (2U)
+#define CRS_CR_ERRIE_Msk          (0x1UL << CRS_CR_ERRIE_Pos)                  /*!< 0x00000004 */
+#define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /*!< SYNC error or trimming error interrupt enable */
+#define CRS_CR_ESYNCIE_Pos        (3U)
+#define CRS_CR_ESYNCIE_Msk        (0x1UL << CRS_CR_ESYNCIE_Pos)                /*!< 0x00000008 */
+#define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /*!< Expected SYNC interrupt enable */
+#define CRS_CR_CEN_Pos            (5U)
+#define CRS_CR_CEN_Msk            (0x1UL << CRS_CR_CEN_Pos)                    /*!< 0x00000020 */
+#define CRS_CR_CEN                CRS_CR_CEN_Msk                               /*!< Frequency error counter enable */
+#define CRS_CR_AUTOTRIMEN_Pos     (6U)
+#define CRS_CR_AUTOTRIMEN_Msk     (0x1UL << CRS_CR_AUTOTRIMEN_Pos)             /*!< 0x00000040 */
+#define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /*!< Automatic trimming enable */
+#define CRS_CR_SWSYNC_Pos         (7U)
+#define CRS_CR_SWSYNC_Msk         (0x1UL << CRS_CR_SWSYNC_Pos)                 /*!< 0x00000080 */
+#define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /*!< Generate software SYNC event */
+#define CRS_CR_TRIM_Pos           (8U)
+#define CRS_CR_TRIM_Msk           (0x3FUL << CRS_CR_TRIM_Pos)                  /*!< 0x00003F00 */
+#define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /*!< HSI48 oscillator smooth trimming */
+
+/*******************  Bit definition for CRS_CFGR register  *********************/
+#define CRS_CFGR_RELOAD_Pos       (0U)
+#define CRS_CFGR_RELOAD_Msk       (0xFFFFUL << CRS_CFGR_RELOAD_Pos)            /*!< 0x0000FFFF */
+#define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /*!< Counter reload value */
+#define CRS_CFGR_FELIM_Pos        (16U)
+#define CRS_CFGR_FELIM_Msk        (0xFFUL << CRS_CFGR_FELIM_Pos)               /*!< 0x00FF0000 */
+#define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /*!< Frequency error limit */
+
+#define CRS_CFGR_SYNCDIV_Pos      (24U)
+#define CRS_CFGR_SYNCDIV_Msk      (0x7UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x07000000 */
+#define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /*!< SYNC divider */
+#define CRS_CFGR_SYNCDIV_0        (0x1UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */
+#define CRS_CFGR_SYNCDIV_1        (0x2UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */
+#define CRS_CFGR_SYNCDIV_2        (0x4UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */
+
+#define CRS_CFGR_SYNCSRC_Pos      (28U)
+#define CRS_CFGR_SYNCSRC_Msk      (0x3UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x30000000 */
+#define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /*!< SYNC signal source selection */
+#define CRS_CFGR_SYNCSRC_0        (0x1UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */
+#define CRS_CFGR_SYNCSRC_1        (0x2UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */
+
+#define CRS_CFGR_SYNCPOL_Pos      (31U)
+#define CRS_CFGR_SYNCPOL_Msk      (0x1UL << CRS_CFGR_SYNCPOL_Pos)              /*!< 0x80000000 */
+#define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /*!< SYNC polarity selection */
+
+/*******************  Bit definition for CRS_ISR register  *********************/
+#define CRS_ISR_SYNCOKF_Pos       (0U)
+#define CRS_ISR_SYNCOKF_Msk       (0x1UL << CRS_ISR_SYNCOKF_Pos)               /*!< 0x00000001 */
+#define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /*!< SYNC event OK flag */
+#define CRS_ISR_SYNCWARNF_Pos     (1U)
+#define CRS_ISR_SYNCWARNF_Msk     (0x1UL << CRS_ISR_SYNCWARNF_Pos)             /*!< 0x00000002 */
+#define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /*!< SYNC warning flag */
+#define CRS_ISR_ERRF_Pos          (2U)
+#define CRS_ISR_ERRF_Msk          (0x1UL << CRS_ISR_ERRF_Pos)                  /*!< 0x00000004 */
+#define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /*!< Error flag */
+#define CRS_ISR_ESYNCF_Pos        (3U)
+#define CRS_ISR_ESYNCF_Msk        (0x1UL << CRS_ISR_ESYNCF_Pos)                /*!< 0x00000008 */
+#define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /*!< Expected SYNC flag */
+#define CRS_ISR_SYNCERR_Pos       (8U)
+#define CRS_ISR_SYNCERR_Msk       (0x1UL << CRS_ISR_SYNCERR_Pos)               /*!< 0x00000100 */
+#define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /*!< SYNC error */
+#define CRS_ISR_SYNCMISS_Pos      (9U)
+#define CRS_ISR_SYNCMISS_Msk      (0x1UL << CRS_ISR_SYNCMISS_Pos)              /*!< 0x00000200 */
+#define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /*!< SYNC missed */
+#define CRS_ISR_TRIMOVF_Pos       (10U)
+#define CRS_ISR_TRIMOVF_Msk       (0x1UL << CRS_ISR_TRIMOVF_Pos)               /*!< 0x00000400 */
+#define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /*!< Trimming overflow or underflow */
+#define CRS_ISR_FEDIR_Pos         (15U)
+#define CRS_ISR_FEDIR_Msk         (0x1UL << CRS_ISR_FEDIR_Pos)                 /*!< 0x00008000 */
+#define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /*!< Frequency error direction */
+#define CRS_ISR_FECAP_Pos         (16U)
+#define CRS_ISR_FECAP_Msk         (0xFFFFUL << CRS_ISR_FECAP_Pos)              /*!< 0xFFFF0000 */
+#define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /*!< Frequency error capture */
+
+/*******************  Bit definition for CRS_ICR register  *********************/
+#define CRS_ICR_SYNCOKC_Pos       (0U)
+#define CRS_ICR_SYNCOKC_Msk       (0x1UL << CRS_ICR_SYNCOKC_Pos)               /*!< 0x00000001 */
+#define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /*!< SYNC event OK clear flag */
+#define CRS_ICR_SYNCWARNC_Pos     (1U)
+#define CRS_ICR_SYNCWARNC_Msk     (0x1UL << CRS_ICR_SYNCWARNC_Pos)             /*!< 0x00000002 */
+#define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /*!< SYNC warning clear flag */
+#define CRS_ICR_ERRC_Pos          (2U)
+#define CRS_ICR_ERRC_Msk          (0x1UL << CRS_ICR_ERRC_Pos)                  /*!< 0x00000004 */
+#define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /*!< Error clear flag */
+#define CRS_ICR_ESYNCC_Pos        (3U)
+#define CRS_ICR_ESYNCC_Msk        (0x1UL << CRS_ICR_ESYNCC_Pos)                /*!< 0x00000008 */
+#define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /*!< Expected SYNC clear flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Digital to Analog Converter                           */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DAC_CR register  ********************/
+#define DAC_CR_EN1_Pos              (0U)
+#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                  /*!< 0x00000001 */
+#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */
+#define DAC_CR_TEN1_Pos             (1U)
+#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                 /*!< 0x00000002 */
+#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos            (2U)
+#define DAC_CR_TSEL1_Msk            (0xFUL << DAC_CR_TSEL1_Pos)                /*!< 0x0000003C */
+#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000004 */
+#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
+#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
+#define DAC_CR_TSEL1_3              (0x8UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
+
+
+#define DAC_CR_WAVE1_Pos            (6U)
+#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                /*!< 0x000000C0 */
+#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos            (8U)
+#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                /*!< 0x00000F00 */
+#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos           (12U)
+#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)               /*!< 0x00001000 */
+#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1_Pos        (13U)
+#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)            /*!< 0x00002000 */
+#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/
+#define DAC_CR_CEN1_Pos             (14U)
+#define DAC_CR_CEN1_Msk             (0x1UL << DAC_CR_CEN1_Pos)                 /*!< 0x00004000 */
+#define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/
+
+#define DAC_CR_EN2_Pos              (16U)
+#define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                  /*!< 0x00010000 */
+#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */
+#define DAC_CR_TEN2_Pos             (17U)
+#define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                 /*!< 0x00020000 */
+#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2_Pos            (18U)
+#define DAC_CR_TSEL2_Msk            (0xFUL << DAC_CR_TSEL2_Pos)                /*!< 0x003C0000 */
+#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00040000 */
+#define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */
+#define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */
+#define DAC_CR_TSEL2_3              (0x8UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */
+
+
+#define DAC_CR_WAVE2_Pos            (22U)
+#define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                /*!< 0x00C00000 */
+#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */
+#define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */
+
+#define DAC_CR_MAMP2_Pos            (24U)
+#define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                /*!< 0x0F000000 */
+#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */
+#define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */
+#define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */
+#define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */
+
+#define DAC_CR_DMAEN2_Pos           (28U)
+#define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)               /*!< 0x10000000 */
+#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2_Pos        (29U)
+#define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)            /*!< 0x20000000 */
+#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/
+#define DAC_CR_CEN2_Pos             (30U)
+#define DAC_CR_CEN2_Msk             (0x1UL << DAC_CR_CEN2_Pos)                 /*!< 0x40000000 */
+#define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/
+
+/*****************  Bit definition for DAC_SWTRIGR register  ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)
+#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)         /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)
+#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)         /*!< 0x00000002 */
+#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */
+
+/*****************  Bit definition for DAC_DHR12R1 register  ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos    (0U)
+#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)      /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L1 register  ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos    (4U)
+#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)      /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R1 register  ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos     (0U)
+#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)        /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12R2 register  ******************/
+#define DAC_DHR12R2_DACC2DHR_Pos    (0U)
+#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)      /*!< 0x00000FFF */
+#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L2 register  ******************/
+#define DAC_DHR12L2_DACC2DHR_Pos    (4U)
+#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)      /*!< 0x0000FFF0 */
+#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R2 register  ******************/
+#define DAC_DHR8R2_DACC2DHR_Pos     (0U)
+#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)        /*!< 0x000000FF */
+#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12RD register  ******************/
+#define DAC_DHR12RD_DACC1DHR_Pos    (0U)
+#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)      /*!< 0x00000FFF */
+#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR_Pos    (16U)
+#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)      /*!< 0x0FFF0000 */
+#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12LD register  ******************/
+#define DAC_DHR12LD_DACC1DHR_Pos    (4U)
+#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)      /*!< 0x0000FFF0 */
+#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR_Pos    (20U)
+#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)      /*!< 0xFFF00000 */
+#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8RD register  ******************/
+#define DAC_DHR8RD_DACC1DHR_Pos     (0U)
+#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)        /*!< 0x000000FF */
+#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR_Pos     (8U)
+#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)        /*!< 0x0000FF00 */
+#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
+
+/*******************  Bit definition for DAC_DOR1 register  *******************/
+#define DAC_DOR1_DACC1DOR_Pos       (0U)
+#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)         /*!< 0x00000FFF */
+#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */
+
+/*******************  Bit definition for DAC_DOR2 register  *******************/
+#define DAC_DOR2_DACC2DOR_Pos       (0U)
+#define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)         /*!< 0x00000FFF */
+#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */
+
+/********************  Bit definition for DAC_SR register  ********************/
+#define DAC_SR_DMAUDR1_Pos          (13U)
+#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)              /*!< 0x00002000 */
+#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_CAL_FLAG1_Pos        (14U)
+#define DAC_SR_CAL_FLAG1_Msk        (0x1UL << DAC_SR_CAL_FLAG1_Pos)            /*!< 0x00004000 */
+#define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */
+#define DAC_SR_BWST1_Pos            (15U)
+#define DAC_SR_BWST1_Msk            (0x4001UL << DAC_SR_BWST1_Pos)             /*!< 0x20008000 */
+#define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */
+
+#define DAC_SR_DMAUDR2_Pos          (29U)
+#define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)              /*!< 0x20000000 */
+#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */
+#define DAC_SR_CAL_FLAG2_Pos        (30U)
+#define DAC_SR_CAL_FLAG2_Msk        (0x1UL << DAC_SR_CAL_FLAG2_Pos)            /*!< 0x40000000 */
+#define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */
+#define DAC_SR_BWST2_Pos            (31U)
+#define DAC_SR_BWST2_Msk            (0x1UL << DAC_SR_BWST2_Pos)                /*!< 0x80000000 */
+#define DAC_SR_BWST2                DAC_SR_BWST2_Msk                           /*!<DAC channel2 busy writing sample time flag */
+
+/*******************  Bit definition for DAC_CCR register  ********************/
+#define DAC_CCR_OTRIM1_Pos          (0U)
+#define DAC_CCR_OTRIM1_Msk          (0x1FUL << DAC_CCR_OTRIM1_Pos)             /*!< 0x0000001F */
+#define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */
+#define DAC_CCR_OTRIM2_Pos          (16U)
+#define DAC_CCR_OTRIM2_Msk          (0x1FUL << DAC_CCR_OTRIM2_Pos)             /*!< 0x001F0000 */
+#define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */
+
+/*******************  Bit definition for DAC_MCR register  *******************/
+#define DAC_MCR_MODE1_Pos           (0U)
+#define DAC_MCR_MODE1_Msk           (0x7UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000007 */
+#define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */
+#define DAC_MCR_MODE1_0             (0x1UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000001 */
+#define DAC_MCR_MODE1_1             (0x2UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000002 */
+#define DAC_MCR_MODE1_2             (0x4UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000004 */
+
+#define DAC_MCR_MODE2_Pos           (16U)
+#define DAC_MCR_MODE2_Msk           (0x7UL << DAC_MCR_MODE2_Pos)               /*!< 0x00070000 */
+#define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */
+#define DAC_MCR_MODE2_0             (0x1UL << DAC_MCR_MODE2_Pos)                /*!< 0x00010000 */
+#define DAC_MCR_MODE2_1             (0x2UL << DAC_MCR_MODE2_Pos)                /*!< 0x00020000 */
+#define DAC_MCR_MODE2_2             (0x4UL << DAC_MCR_MODE2_Pos)                /*!< 0x00040000 */
+
+/******************  Bit definition for DAC_SHSR1 register  ******************/
+#define DAC_SHSR1_TSAMPLE1_Pos      (0U)
+#define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)        /*!< 0x000003FF */
+#define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */
+
+/******************  Bit definition for DAC_SHSR2 register  ******************/
+#define DAC_SHSR2_TSAMPLE2_Pos      (0U)
+#define DAC_SHSR2_TSAMPLE2_Msk      (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)        /*!< 0x000003FF */
+#define DAC_SHSR2_TSAMPLE2          DAC_SHSR2_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */
+
+/******************  Bit definition for DAC_SHHR register  ******************/
+#define DAC_SHHR_THOLD1_Pos         (0U)
+#define DAC_SHHR_THOLD1_Msk         (0x3FFUL << DAC_SHHR_THOLD1_Pos)           /*!< 0x000003FF */
+#define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */
+#define DAC_SHHR_THOLD2_Pos         (16U)
+#define DAC_SHHR_THOLD2_Msk         (0x3FFUL << DAC_SHHR_THOLD2_Pos)           /*!< 0x03FF0000 */
+#define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */
+
+/******************  Bit definition for DAC_SHRR register  ******************/
+#define DAC_SHRR_TREFRESH1_Pos      (0U)
+#define DAC_SHRR_TREFRESH1_Msk      (0xFFUL << DAC_SHRR_TREFRESH1_Pos)         /*!< 0x000000FF */
+#define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */
+#define DAC_SHRR_TREFRESH2_Pos      (16U)
+#define DAC_SHRR_TREFRESH2_Msk      (0xFFUL << DAC_SHRR_TREFRESH2_Pos)         /*!< 0x00FF0000 */
+#define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    DCMI                                    */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for DCMI_CR register  ******************/
+#define DCMI_CR_CAPTURE_Pos        (0U)
+#define DCMI_CR_CAPTURE_Msk        (0x1UL << DCMI_CR_CAPTURE_Pos)              /*!< 0x00000001 */
+#define DCMI_CR_CAPTURE            DCMI_CR_CAPTURE_Msk
+#define DCMI_CR_CM_Pos             (1U)
+#define DCMI_CR_CM_Msk             (0x1UL << DCMI_CR_CM_Pos)                   /*!< 0x00000002 */
+#define DCMI_CR_CM                 DCMI_CR_CM_Msk
+#define DCMI_CR_CROP_Pos           (2U)
+#define DCMI_CR_CROP_Msk           (0x1UL << DCMI_CR_CROP_Pos)                 /*!< 0x00000004 */
+#define DCMI_CR_CROP               DCMI_CR_CROP_Msk
+#define DCMI_CR_JPEG_Pos           (3U)
+#define DCMI_CR_JPEG_Msk           (0x1UL << DCMI_CR_JPEG_Pos)                 /*!< 0x00000008 */
+#define DCMI_CR_JPEG               DCMI_CR_JPEG_Msk
+#define DCMI_CR_ESS_Pos            (4U)
+#define DCMI_CR_ESS_Msk            (0x1UL << DCMI_CR_ESS_Pos)                  /*!< 0x00000010 */
+#define DCMI_CR_ESS                DCMI_CR_ESS_Msk
+#define DCMI_CR_PCKPOL_Pos         (5U)
+#define DCMI_CR_PCKPOL_Msk         (0x1UL << DCMI_CR_PCKPOL_Pos)               /*!< 0x00000020 */
+#define DCMI_CR_PCKPOL             DCMI_CR_PCKPOL_Msk
+#define DCMI_CR_HSPOL_Pos          (6U)
+#define DCMI_CR_HSPOL_Msk          (0x1UL << DCMI_CR_HSPOL_Pos)                /*!< 0x00000040 */
+#define DCMI_CR_HSPOL              DCMI_CR_HSPOL_Msk
+#define DCMI_CR_VSPOL_Pos          (7U)
+#define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                /*!< 0x00000080 */
+#define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk
+#define DCMI_CR_FCRC_0             ((uint32_t)0x00000100U)
+#define DCMI_CR_FCRC_1             ((uint32_t)0x00000200U)
+#define DCMI_CR_EDM_0              ((uint32_t)0x00000400U)
+#define DCMI_CR_EDM_1              ((uint32_t)0x00000800U)
+#define DCMI_CR_CRE_Pos            (12U)
+#define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                  /*!< 0x00001000 */
+#define DCMI_CR_CRE                DCMI_CR_CRE_Msk
+#define DCMI_CR_ENABLE_Pos         (14U)
+#define DCMI_CR_ENABLE_Msk         (0x1UL << DCMI_CR_ENABLE_Pos)               /*!< 0x00004000 */
+#define DCMI_CR_ENABLE             DCMI_CR_ENABLE_Msk
+#define DCMI_CR_BSM_Pos            (16U)
+#define DCMI_CR_BSM_Msk            (0x3UL << DCMI_CR_BSM_Pos)                  /*!< 0x00030000 */
+#define DCMI_CR_BSM                DCMI_CR_BSM_Msk
+#define DCMI_CR_BSM_0              (0x1UL << DCMI_CR_BSM_Pos)                   /*!< 0x00010000 */
+#define DCMI_CR_BSM_1              (0x2UL << DCMI_CR_BSM_Pos)                   /*!< 0x00020000 */
+#define DCMI_CR_OEBS_Pos           (18U)
+#define DCMI_CR_OEBS_Msk           (0x1UL << DCMI_CR_OEBS_Pos)                 /*!< 0x00040000 */
+#define DCMI_CR_OEBS               DCMI_CR_OEBS_Msk
+#define DCMI_CR_LSM_Pos            (19U)
+#define DCMI_CR_LSM_Msk            (0x1UL << DCMI_CR_LSM_Pos)                  /*!< 0x00080000 */
+#define DCMI_CR_LSM                DCMI_CR_LSM_Msk
+#define DCMI_CR_OELS_Pos           (20U)
+#define DCMI_CR_OELS_Msk           (0x1UL << DCMI_CR_OELS_Pos)                 /*!< 0x00100000 */
+#define DCMI_CR_OELS               DCMI_CR_OELS_Msk
+
+/********************  Bits definition for DCMI_SR register  ******************/
+#define DCMI_SR_HSYNC_Pos          (0U)
+#define DCMI_SR_HSYNC_Msk          (0x1UL << DCMI_SR_HSYNC_Pos)                /*!< 0x00000001 */
+#define DCMI_SR_HSYNC              DCMI_SR_HSYNC_Msk
+#define DCMI_SR_VSYNC_Pos          (1U)
+#define DCMI_SR_VSYNC_Msk          (0x1UL << DCMI_SR_VSYNC_Pos)                /*!< 0x00000002 */
+#define DCMI_SR_VSYNC              DCMI_SR_VSYNC_Msk
+#define DCMI_SR_FNE_Pos            (2U)
+#define DCMI_SR_FNE_Msk            (0x1UL << DCMI_SR_FNE_Pos)                  /*!< 0x00000004 */
+#define DCMI_SR_FNE                DCMI_SR_FNE_Msk
+
+/********************  Bits definition for DCMI_RIS register   ****************/
+#define DCMI_RIS_FRAME_RIS_Pos     (0U)
+#define DCMI_RIS_FRAME_RIS_Msk     (0x1UL << DCMI_RIS_FRAME_RIS_Pos)           /*!< 0x00000001 */
+#define DCMI_RIS_FRAME_RIS         DCMI_RIS_FRAME_RIS_Msk
+#define DCMI_RIS_OVR_RIS_Pos       (1U)
+#define DCMI_RIS_OVR_RIS_Msk       (0x1UL << DCMI_RIS_OVR_RIS_Pos)             /*!< 0x00000002 */
+#define DCMI_RIS_OVR_RIS           DCMI_RIS_OVR_RIS_Msk
+#define DCMI_RIS_ERR_RIS_Pos       (2U)
+#define DCMI_RIS_ERR_RIS_Msk       (0x1UL << DCMI_RIS_ERR_RIS_Pos)             /*!< 0x00000004 */
+#define DCMI_RIS_ERR_RIS           DCMI_RIS_ERR_RIS_Msk
+#define DCMI_RIS_VSYNC_RIS_Pos     (3U)
+#define DCMI_RIS_VSYNC_RIS_Msk     (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)           /*!< 0x00000008 */
+#define DCMI_RIS_VSYNC_RIS         DCMI_RIS_VSYNC_RIS_Msk
+#define DCMI_RIS_LINE_RIS_Pos      (4U)
+#define DCMI_RIS_LINE_RIS_Msk      (0x1UL << DCMI_RIS_LINE_RIS_Pos)            /*!< 0x00000010 */
+#define DCMI_RIS_LINE_RIS          DCMI_RIS_LINE_RIS_Msk
+
+/********************  Bits definition for DCMI_IER register  *****************/
+#define DCMI_IER_FRAME_IE_Pos      (0U)
+#define DCMI_IER_FRAME_IE_Msk      (0x1UL << DCMI_IER_FRAME_IE_Pos)            /*!< 0x00000001 */
+#define DCMI_IER_FRAME_IE          DCMI_IER_FRAME_IE_Msk
+#define DCMI_IER_OVR_IE_Pos        (1U)
+#define DCMI_IER_OVR_IE_Msk        (0x1UL << DCMI_IER_OVR_IE_Pos)              /*!< 0x00000002 */
+#define DCMI_IER_OVR_IE            DCMI_IER_OVR_IE_Msk
+#define DCMI_IER_ERR_IE_Pos        (2U)
+#define DCMI_IER_ERR_IE_Msk        (0x1UL << DCMI_IER_ERR_IE_Pos)              /*!< 0x00000004 */
+#define DCMI_IER_ERR_IE            DCMI_IER_ERR_IE_Msk
+#define DCMI_IER_VSYNC_IE_Pos      (3U)
+#define DCMI_IER_VSYNC_IE_Msk      (0x1UL << DCMI_IER_VSYNC_IE_Pos)            /*!< 0x00000008 */
+#define DCMI_IER_VSYNC_IE          DCMI_IER_VSYNC_IE_Msk
+#define DCMI_IER_LINE_IE_Pos       (4U)
+#define DCMI_IER_LINE_IE_Msk       (0x1UL << DCMI_IER_LINE_IE_Pos)             /*!< 0x00000010 */
+#define DCMI_IER_LINE_IE           DCMI_IER_LINE_IE_Msk
+
+
+/********************  Bits definition for DCMI_MIS register  *****************/
+#define DCMI_MIS_FRAME_MIS_Pos     (0U)
+#define DCMI_MIS_FRAME_MIS_Msk     (0x1UL << DCMI_MIS_FRAME_MIS_Pos)           /*!< 0x00000001 */
+#define DCMI_MIS_FRAME_MIS         DCMI_MIS_FRAME_MIS_Msk
+#define DCMI_MIS_OVR_MIS_Pos       (1U)
+#define DCMI_MIS_OVR_MIS_Msk       (0x1UL << DCMI_MIS_OVR_MIS_Pos)             /*!< 0x00000002 */
+#define DCMI_MIS_OVR_MIS           DCMI_MIS_OVR_MIS_Msk
+#define DCMI_MIS_ERR_MIS_Pos       (2U)
+#define DCMI_MIS_ERR_MIS_Msk       (0x1UL << DCMI_MIS_ERR_MIS_Pos)             /*!< 0x00000004 */
+#define DCMI_MIS_ERR_MIS           DCMI_MIS_ERR_MIS_Msk
+#define DCMI_MIS_VSYNC_MIS_Pos     (3U)
+#define DCMI_MIS_VSYNC_MIS_Msk     (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)           /*!< 0x00000008 */
+#define DCMI_MIS_VSYNC_MIS         DCMI_MIS_VSYNC_MIS_Msk
+#define DCMI_MIS_LINE_MIS_Pos      (4U)
+#define DCMI_MIS_LINE_MIS_Msk      (0x1UL << DCMI_MIS_LINE_MIS_Pos)            /*!< 0x00000010 */
+#define DCMI_MIS_LINE_MIS          DCMI_MIS_LINE_MIS_Msk
+
+
+/********************  Bits definition for DCMI_ICR register  *****************/
+#define DCMI_ICR_FRAME_ISC_Pos     (0U)
+#define DCMI_ICR_FRAME_ISC_Msk     (0x1UL << DCMI_ICR_FRAME_ISC_Pos)           /*!< 0x00000001 */
+#define DCMI_ICR_FRAME_ISC         DCMI_ICR_FRAME_ISC_Msk
+#define DCMI_ICR_OVR_ISC_Pos       (1U)
+#define DCMI_ICR_OVR_ISC_Msk       (0x1UL << DCMI_ICR_OVR_ISC_Pos)             /*!< 0x00000002 */
+#define DCMI_ICR_OVR_ISC           DCMI_ICR_OVR_ISC_Msk
+#define DCMI_ICR_ERR_ISC_Pos       (2U)
+#define DCMI_ICR_ERR_ISC_Msk       (0x1UL << DCMI_ICR_ERR_ISC_Pos)             /*!< 0x00000004 */
+#define DCMI_ICR_ERR_ISC           DCMI_ICR_ERR_ISC_Msk
+#define DCMI_ICR_VSYNC_ISC_Pos     (3U)
+#define DCMI_ICR_VSYNC_ISC_Msk     (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)           /*!< 0x00000008 */
+#define DCMI_ICR_VSYNC_ISC         DCMI_ICR_VSYNC_ISC_Msk
+#define DCMI_ICR_LINE_ISC_Pos      (4U)
+#define DCMI_ICR_LINE_ISC_Msk      (0x1UL << DCMI_ICR_LINE_ISC_Pos)            /*!< 0x00000010 */
+#define DCMI_ICR_LINE_ISC          DCMI_ICR_LINE_ISC_Msk
+
+
+/********************  Bits definition for DCMI_ESCR register  ******************/
+#define DCMI_ESCR_FSC_Pos          (0U)
+#define DCMI_ESCR_FSC_Msk          (0xFFUL << DCMI_ESCR_FSC_Pos)               /*!< 0x000000FF */
+#define DCMI_ESCR_FSC              DCMI_ESCR_FSC_Msk
+#define DCMI_ESCR_LSC_Pos          (8U)
+#define DCMI_ESCR_LSC_Msk          (0xFFUL << DCMI_ESCR_LSC_Pos)               /*!< 0x0000FF00 */
+#define DCMI_ESCR_LSC              DCMI_ESCR_LSC_Msk
+#define DCMI_ESCR_LEC_Pos          (16U)
+#define DCMI_ESCR_LEC_Msk          (0xFFUL << DCMI_ESCR_LEC_Pos)               /*!< 0x00FF0000 */
+#define DCMI_ESCR_LEC              DCMI_ESCR_LEC_Msk
+#define DCMI_ESCR_FEC_Pos          (24U)
+#define DCMI_ESCR_FEC_Msk          (0xFFUL << DCMI_ESCR_FEC_Pos)               /*!< 0xFF000000 */
+#define DCMI_ESCR_FEC              DCMI_ESCR_FEC_Msk
+
+/********************  Bits definition for DCMI_ESUR register  ******************/
+#define DCMI_ESUR_FSU_Pos          (0U)
+#define DCMI_ESUR_FSU_Msk          (0xFFUL << DCMI_ESUR_FSU_Pos)               /*!< 0x000000FF */
+#define DCMI_ESUR_FSU              DCMI_ESUR_FSU_Msk
+#define DCMI_ESUR_LSU_Pos          (8U)
+#define DCMI_ESUR_LSU_Msk          (0xFFUL << DCMI_ESUR_LSU_Pos)               /*!< 0x0000FF00 */
+#define DCMI_ESUR_LSU              DCMI_ESUR_LSU_Msk
+#define DCMI_ESUR_LEU_Pos          (16U)
+#define DCMI_ESUR_LEU_Msk          (0xFFUL << DCMI_ESUR_LEU_Pos)               /*!< 0x00FF0000 */
+#define DCMI_ESUR_LEU              DCMI_ESUR_LEU_Msk
+#define DCMI_ESUR_FEU_Pos          (24U)
+#define DCMI_ESUR_FEU_Msk          (0xFFUL << DCMI_ESUR_FEU_Pos)               /*!< 0xFF000000 */
+#define DCMI_ESUR_FEU              DCMI_ESUR_FEU_Msk
+
+/********************  Bits definition for DCMI_CWSTRT register  ******************/
+#define DCMI_CWSTRT_HOFFCNT_Pos    (0U)
+#define DCMI_CWSTRT_HOFFCNT_Msk    (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)       /*!< 0x00003FFF */
+#define DCMI_CWSTRT_HOFFCNT        DCMI_CWSTRT_HOFFCNT_Msk
+#define DCMI_CWSTRT_VST_Pos        (16U)
+#define DCMI_CWSTRT_VST_Msk        (0x1FFFUL << DCMI_CWSTRT_VST_Pos)           /*!< 0x1FFF0000 */
+#define DCMI_CWSTRT_VST            DCMI_CWSTRT_VST_Msk
+
+/********************  Bits definition for DCMI_CWSIZE register  ******************/
+#define DCMI_CWSIZE_CAPCNT_Pos     (0U)
+#define DCMI_CWSIZE_CAPCNT_Msk     (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)        /*!< 0x00003FFF */
+#define DCMI_CWSIZE_CAPCNT         DCMI_CWSIZE_CAPCNT_Msk
+#define DCMI_CWSIZE_VLINE_Pos      (16U)
+#define DCMI_CWSIZE_VLINE_Msk      (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)         /*!< 0x3FFF0000 */
+#define DCMI_CWSIZE_VLINE          DCMI_CWSIZE_VLINE_Msk
+
+/********************  Bits definition for DCMI_DR register  ******************/
+#define DCMI_DR_BYTE0_Pos          (0U)
+#define DCMI_DR_BYTE0_Msk          (0xFFUL << DCMI_DR_BYTE0_Pos)               /*!< 0x000000FF */
+#define DCMI_DR_BYTE0              DCMI_DR_BYTE0_Msk
+#define DCMI_DR_BYTE1_Pos          (8U)
+#define DCMI_DR_BYTE1_Msk          (0xFFUL << DCMI_DR_BYTE1_Pos)               /*!< 0x0000FF00 */
+#define DCMI_DR_BYTE1              DCMI_DR_BYTE1_Msk
+#define DCMI_DR_BYTE2_Pos          (16U)
+#define DCMI_DR_BYTE2_Msk          (0xFFUL << DCMI_DR_BYTE2_Pos)               /*!< 0x00FF0000 */
+#define DCMI_DR_BYTE2              DCMI_DR_BYTE2_Msk
+#define DCMI_DR_BYTE3_Pos          (24U)
+#define DCMI_DR_BYTE3_Msk          (0xFFUL << DCMI_DR_BYTE3_Pos)               /*!< 0xFF000000 */
+#define DCMI_DR_BYTE3              DCMI_DR_BYTE3_Msk
+
+/******************************************************************************/
+/*                                                                            */
+/*                 Digital Filter for Sigma Delta Modulators                  */
+/*                                                                            */
+/******************************************************************************/
+
+/****************   DFSDM channel configuration registers  ********************/
+
+/***************  Bit definition for DFSDM_CHCFGR1 register  ******************/
+#define DFSDM_CHCFGR1_DFSDMEN_Pos       (31U)
+#define DFSDM_CHCFGR1_DFSDMEN_Msk       (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos)   /*!< 0x80000000 */
+#define DFSDM_CHCFGR1_DFSDMEN           DFSDM_CHCFGR1_DFSDMEN_Msk              /*!< Global enable for DFSDM interface */
+#define DFSDM_CHCFGR1_CKOUTSRC_Pos      (30U)
+#define DFSDM_CHCFGR1_CKOUTSRC_Msk      (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos)  /*!< 0x40000000 */
+#define DFSDM_CHCFGR1_CKOUTSRC          DFSDM_CHCFGR1_CKOUTSRC_Msk             /*!< Output serial clock source selection */
+#define DFSDM_CHCFGR1_CKOUTDIV_Pos      (16U)
+#define DFSDM_CHCFGR1_CKOUTDIV_Msk      (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */
+#define DFSDM_CHCFGR1_CKOUTDIV          DFSDM_CHCFGR1_CKOUTDIV_Msk             /*!< CKOUTDIV[7:0] output serial clock divider */
+#define DFSDM_CHCFGR1_DATPACK_Pos       (14U)
+#define DFSDM_CHCFGR1_DATPACK_Msk       (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos)   /*!< 0x0000C000 */
+#define DFSDM_CHCFGR1_DATPACK           DFSDM_CHCFGR1_DATPACK_Msk              /*!< DATPACK[1:0] Data packing mode */
+#define DFSDM_CHCFGR1_DATPACK_1         (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00008000 */
+#define DFSDM_CHCFGR1_DATPACK_0         (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00004000 */
+#define DFSDM_CHCFGR1_DATMPX_Pos        (12U)
+#define DFSDM_CHCFGR1_DATMPX_Msk        (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos)    /*!< 0x00003000 */
+#define DFSDM_CHCFGR1_DATMPX            DFSDM_CHCFGR1_DATMPX_Msk               /*!< DATMPX[1:0] Input data multiplexer for channel y */
+#define DFSDM_CHCFGR1_DATMPX_1          (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00002000 */
+#define DFSDM_CHCFGR1_DATMPX_0          (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00001000 */
+#define DFSDM_CHCFGR1_CHINSEL_Pos       (8U)
+#define DFSDM_CHCFGR1_CHINSEL_Msk       (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos)   /*!< 0x00000100 */
+#define DFSDM_CHCFGR1_CHINSEL           DFSDM_CHCFGR1_CHINSEL_Msk              /*!< Serial inputs selection for channel y */
+#define DFSDM_CHCFGR1_CHEN_Pos          (7U)
+#define DFSDM_CHCFGR1_CHEN_Msk          (0x1UL << DFSDM_CHCFGR1_CHEN_Pos)      /*!< 0x00000080 */
+#define DFSDM_CHCFGR1_CHEN              DFSDM_CHCFGR1_CHEN_Msk                 /*!< Channel y enable */
+#define DFSDM_CHCFGR1_CKABEN_Pos        (6U)
+#define DFSDM_CHCFGR1_CKABEN_Msk        (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos)    /*!< 0x00000040 */
+#define DFSDM_CHCFGR1_CKABEN            DFSDM_CHCFGR1_CKABEN_Msk               /*!< Clock absence detector enable on channel y */
+#define DFSDM_CHCFGR1_SCDEN_Pos         (5U)
+#define DFSDM_CHCFGR1_SCDEN_Msk         (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos)     /*!< 0x00000020 */
+#define DFSDM_CHCFGR1_SCDEN             DFSDM_CHCFGR1_SCDEN_Msk                /*!< Short circuit detector enable on channel y */
+#define DFSDM_CHCFGR1_SPICKSEL_Pos      (2U)
+#define DFSDM_CHCFGR1_SPICKSEL_Msk      (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos)  /*!< 0x0000000C */
+#define DFSDM_CHCFGR1_SPICKSEL          DFSDM_CHCFGR1_SPICKSEL_Msk             /*!< SPICKSEL[1:0] SPI clock select for channel y */
+#define DFSDM_CHCFGR1_SPICKSEL_1        (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000008 */
+#define DFSDM_CHCFGR1_SPICKSEL_0        (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000004 */
+#define DFSDM_CHCFGR1_SITP_Pos          (0U)
+#define DFSDM_CHCFGR1_SITP_Msk          (0x3UL << DFSDM_CHCFGR1_SITP_Pos)      /*!< 0x00000003 */
+#define DFSDM_CHCFGR1_SITP              DFSDM_CHCFGR1_SITP_Msk                 /*!< SITP[1:0] Serial interface type for channel y */
+#define DFSDM_CHCFGR1_SITP_1            (0x2UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000002 */
+#define DFSDM_CHCFGR1_SITP_0            (0x1UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000001 */
+
+/***************  Bit definition for DFSDM_CHCFGR2 register  ******************/
+#define DFSDM_CHCFGR2_OFFSET_Pos        (8U)
+#define DFSDM_CHCFGR2_OFFSET_Msk        (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_CHCFGR2_OFFSET            DFSDM_CHCFGR2_OFFSET_Msk               /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
+#define DFSDM_CHCFGR2_DTRBS_Pos         (3U)
+#define DFSDM_CHCFGR2_DTRBS_Msk         (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos)    /*!< 0x000000F8 */
+#define DFSDM_CHCFGR2_DTRBS             DFSDM_CHCFGR2_DTRBS_Msk                /*!< DTRBS[4:0] Data right bit-shift for channel y */
+
+/******************  Bit definition for DFSDM_CHAWSCDR register *****************/
+#define DFSDM_CHAWSCDR_AWFORD_Pos       (22U)
+#define DFSDM_CHAWSCDR_AWFORD_Msk       (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos)   /*!< 0x00C00000 */
+#define DFSDM_CHAWSCDR_AWFORD           DFSDM_CHAWSCDR_AWFORD_Msk              /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
+#define DFSDM_CHAWSCDR_AWFORD_1         (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00800000 */
+#define DFSDM_CHAWSCDR_AWFORD_0         (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00400000 */
+#define DFSDM_CHAWSCDR_AWFOSR_Pos       (16U)
+#define DFSDM_CHAWSCDR_AWFOSR_Msk       (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos)  /*!< 0x001F0000 */
+#define DFSDM_CHAWSCDR_AWFOSR           DFSDM_CHAWSCDR_AWFOSR_Msk              /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
+#define DFSDM_CHAWSCDR_BKSCD_Pos        (12U)
+#define DFSDM_CHAWSCDR_BKSCD_Msk        (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos)    /*!< 0x0000F000 */
+#define DFSDM_CHAWSCDR_BKSCD            DFSDM_CHAWSCDR_BKSCD_Msk               /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
+#define DFSDM_CHAWSCDR_SCDT_Pos         (0U)
+#define DFSDM_CHAWSCDR_SCDT_Msk         (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos)    /*!< 0x000000FF */
+#define DFSDM_CHAWSCDR_SCDT             DFSDM_CHAWSCDR_SCDT_Msk                /*!< SCDT[7:0] Short circuit detector threshold for channel y */
+
+/****************  Bit definition for DFSDM_CHWDATR register *******************/
+#define DFSDM_CHWDATR_WDATA_Pos         (0U)
+#define DFSDM_CHWDATR_WDATA_Msk         (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos)  /*!< 0x0000FFFF */
+#define DFSDM_CHWDATR_WDATA             DFSDM_CHWDATR_WDATA_Msk                /*!< WDATA[15:0] Input channel y watchdog data */
+
+/****************  Bit definition for DFSDM_CHDATINR register *****************/
+#define DFSDM_CHDATINR_INDAT0_Pos       (0U)
+#define DFSDM_CHDATINR_INDAT0_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */
+#define DFSDM_CHDATINR_INDAT0           DFSDM_CHDATINR_INDAT0_Msk              /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
+#define DFSDM_CHDATINR_INDAT1_Pos       (16U)
+#define DFSDM_CHDATINR_INDAT1_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */
+#define DFSDM_CHDATINR_INDAT1           DFSDM_CHDATINR_INDAT1_Msk              /*!< INDAT0[15:0] Input data for channel y */
+
+/************************   DFSDM module registers  ****************************/
+
+/********************  Bit definition for DFSDM_FLTCR1 register *******************/
+#define DFSDM_FLTCR1_AWFSEL_Pos         (30U)
+#define DFSDM_FLTCR1_AWFSEL_Msk         (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos)     /*!< 0x40000000 */
+#define DFSDM_FLTCR1_AWFSEL             DFSDM_FLTCR1_AWFSEL_Msk                /*!< Analog watchdog fast mode select */
+#define DFSDM_FLTCR1_FAST_Pos           (29U)
+#define DFSDM_FLTCR1_FAST_Msk           (0x1UL << DFSDM_FLTCR1_FAST_Pos)       /*!< 0x20000000 */
+#define DFSDM_FLTCR1_FAST               DFSDM_FLTCR1_FAST_Msk                  /*!< Fast conversion mode selection */
+#define DFSDM_FLTCR1_RCH_Pos            (24U)
+#define DFSDM_FLTCR1_RCH_Msk            (0x7UL << DFSDM_FLTCR1_RCH_Pos)        /*!< 0x07000000 */
+#define DFSDM_FLTCR1_RCH                DFSDM_FLTCR1_RCH_Msk                   /*!< RCH[2:0] Regular channel selection */
+#define DFSDM_FLTCR1_RDMAEN_Pos         (21U)
+#define DFSDM_FLTCR1_RDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos)     /*!< 0x00200000 */
+#define DFSDM_FLTCR1_RDMAEN             DFSDM_FLTCR1_RDMAEN_Msk                /*!< DMA channel enabled to read data for the regular conversion */
+#define DFSDM_FLTCR1_RSYNC_Pos          (19U)
+#define DFSDM_FLTCR1_RSYNC_Msk          (0x1UL << DFSDM_FLTCR1_RSYNC_Pos)      /*!< 0x00080000 */
+#define DFSDM_FLTCR1_RSYNC              DFSDM_FLTCR1_RSYNC_Msk                 /*!< Launch regular conversion synchronously with DFSDMx */
+#define DFSDM_FLTCR1_RCONT_Pos          (18U)
+#define DFSDM_FLTCR1_RCONT_Msk          (0x1UL << DFSDM_FLTCR1_RCONT_Pos)      /*!< 0x00040000 */
+#define DFSDM_FLTCR1_RCONT              DFSDM_FLTCR1_RCONT_Msk                 /*!< Continuous mode selection for regular conversions */
+#define DFSDM_FLTCR1_RSWSTART_Pos       (17U)
+#define DFSDM_FLTCR1_RSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos)   /*!< 0x00020000 */
+#define DFSDM_FLTCR1_RSWSTART           DFSDM_FLTCR1_RSWSTART_Msk              /*!< Software start of a conversion on the regular channel */
+#define DFSDM_FLTCR1_JEXTEN_Pos         (13U)
+#define DFSDM_FLTCR1_JEXTEN_Msk         (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos)     /*!< 0x00006000 */
+#define DFSDM_FLTCR1_JEXTEN             DFSDM_FLTCR1_JEXTEN_Msk                /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
+#define DFSDM_FLTCR1_JEXTEN_1           (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00004000 */
+#define DFSDM_FLTCR1_JEXTEN_0           (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00002000 */
+#define DFSDM_FLTCR1_JEXTSEL_Pos        (8U)
+#define DFSDM_FLTCR1_JEXTSEL_Msk        (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos)   /*!< 0x00001F00 */
+#define DFSDM_FLTCR1_JEXTSEL            DFSDM_FLTCR1_JEXTSEL_Msk               /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */
+#define DFSDM_FLTCR1_JEXTSEL_0          (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000100 */
+#define DFSDM_FLTCR1_JEXTSEL_1          (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000200 */
+#define DFSDM_FLTCR1_JEXTSEL_2          (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000400 */
+#define DFSDM_FLTCR1_JEXTSEL_3          (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000800 */
+#define DFSDM_FLTCR1_JEXTSEL_4          (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00001000 */
+
+#define DFSDM_FLTCR1_JDMAEN_Pos         (5U)
+#define DFSDM_FLTCR1_JDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos)     /*!< 0x00000020 */
+#define DFSDM_FLTCR1_JDMAEN             DFSDM_FLTCR1_JDMAEN_Msk                /*!< DMA channel enabled to read data for the injected channel group */
+#define DFSDM_FLTCR1_JSCAN_Pos          (4U)
+#define DFSDM_FLTCR1_JSCAN_Msk          (0x1UL << DFSDM_FLTCR1_JSCAN_Pos)      /*!< 0x00000010 */
+#define DFSDM_FLTCR1_JSCAN              DFSDM_FLTCR1_JSCAN_Msk                 /*!< Scanning conversion in continuous mode selection for injected conversions */
+#define DFSDM_FLTCR1_JSYNC_Pos          (3U)
+#define DFSDM_FLTCR1_JSYNC_Msk          (0x1UL << DFSDM_FLTCR1_JSYNC_Pos)      /*!< 0x00000008 */
+#define DFSDM_FLTCR1_JSYNC              DFSDM_FLTCR1_JSYNC_Msk                 /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */
+#define DFSDM_FLTCR1_JSWSTART_Pos       (1U)
+#define DFSDM_FLTCR1_JSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos)   /*!< 0x00000002 */
+#define DFSDM_FLTCR1_JSWSTART           DFSDM_FLTCR1_JSWSTART_Msk              /*!< Start the conversion of the injected group of channels */
+#define DFSDM_FLTCR1_DFEN_Pos           (0U)
+#define DFSDM_FLTCR1_DFEN_Msk           (0x1UL << DFSDM_FLTCR1_DFEN_Pos)       /*!< 0x00000001 */
+#define DFSDM_FLTCR1_DFEN               DFSDM_FLTCR1_DFEN_Msk                  /*!< DFSDM enable */
+
+/********************  Bit definition for DFSDM_FLTCR2 register *******************/
+#define DFSDM_FLTCR2_AWDCH_Pos          (16U)
+#define DFSDM_FLTCR2_AWDCH_Msk          (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos)     /*!< 0x00FF0000 */
+#define DFSDM_FLTCR2_AWDCH              DFSDM_FLTCR2_AWDCH_Msk                 /*!< AWDCH[7:0] Analog watchdog channel selection */
+#define DFSDM_FLTCR2_EXCH_Pos           (8U)
+#define DFSDM_FLTCR2_EXCH_Msk           (0xFFUL << DFSDM_FLTCR2_EXCH_Pos)      /*!< 0x0000FF00 */
+#define DFSDM_FLTCR2_EXCH               DFSDM_FLTCR2_EXCH_Msk                  /*!< EXCH[7:0] Extreme detector channel selection */
+#define DFSDM_FLTCR2_CKABIE_Pos         (6U)
+#define DFSDM_FLTCR2_CKABIE_Msk         (0x1UL << DFSDM_FLTCR2_CKABIE_Pos)     /*!< 0x00000040 */
+#define DFSDM_FLTCR2_CKABIE             DFSDM_FLTCR2_CKABIE_Msk                /*!< Clock absence interrupt enable */
+#define DFSDM_FLTCR2_SCDIE_Pos          (5U)
+#define DFSDM_FLTCR2_SCDIE_Msk          (0x1UL << DFSDM_FLTCR2_SCDIE_Pos)      /*!< 0x00000020 */
+#define DFSDM_FLTCR2_SCDIE              DFSDM_FLTCR2_SCDIE_Msk                 /*!< Short circuit detector interrupt enable */
+#define DFSDM_FLTCR2_AWDIE_Pos          (4U)
+#define DFSDM_FLTCR2_AWDIE_Msk          (0x1UL << DFSDM_FLTCR2_AWDIE_Pos)      /*!< 0x00000010 */
+#define DFSDM_FLTCR2_AWDIE              DFSDM_FLTCR2_AWDIE_Msk                 /*!< Analog watchdog interrupt enable */
+#define DFSDM_FLTCR2_ROVRIE_Pos         (3U)
+#define DFSDM_FLTCR2_ROVRIE_Msk         (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos)     /*!< 0x00000008 */
+#define DFSDM_FLTCR2_ROVRIE             DFSDM_FLTCR2_ROVRIE_Msk                /*!< Regular data overrun interrupt enable */
+#define DFSDM_FLTCR2_JOVRIE_Pos         (2U)
+#define DFSDM_FLTCR2_JOVRIE_Msk         (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos)     /*!< 0x00000004 */
+#define DFSDM_FLTCR2_JOVRIE             DFSDM_FLTCR2_JOVRIE_Msk                /*!< Injected data overrun interrupt enable */
+#define DFSDM_FLTCR2_REOCIE_Pos         (1U)
+#define DFSDM_FLTCR2_REOCIE_Msk         (0x1UL << DFSDM_FLTCR2_REOCIE_Pos)     /*!< 0x00000002 */
+#define DFSDM_FLTCR2_REOCIE             DFSDM_FLTCR2_REOCIE_Msk                /*!< Regular end of conversion interrupt enable */
+#define DFSDM_FLTCR2_JEOCIE_Pos         (0U)
+#define DFSDM_FLTCR2_JEOCIE_Msk         (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos)     /*!< 0x00000001 */
+#define DFSDM_FLTCR2_JEOCIE             DFSDM_FLTCR2_JEOCIE_Msk                /*!< Injected end of conversion interrupt enable */
+
+/********************  Bit definition for DFSDM_FLTISR register *******************/
+#define DFSDM_FLTISR_SCDF_Pos           (24U)
+#define DFSDM_FLTISR_SCDF_Msk           (0xFFUL << DFSDM_FLTISR_SCDF_Pos)      /*!< 0xFF000000 */
+#define DFSDM_FLTISR_SCDF               DFSDM_FLTISR_SCDF_Msk                  /*!< SCDF[7:0] Short circuit detector flag */
+#define DFSDM_FLTISR_CKABF_Pos          (16U)
+#define DFSDM_FLTISR_CKABF_Msk          (0xFFUL << DFSDM_FLTISR_CKABF_Pos)     /*!< 0x00FF0000 */
+#define DFSDM_FLTISR_CKABF              DFSDM_FLTISR_CKABF_Msk                 /*!< CKABF[7:0] Clock absence flag */
+#define DFSDM_FLTISR_RCIP_Pos           (14U)
+#define DFSDM_FLTISR_RCIP_Msk           (0x1UL << DFSDM_FLTISR_RCIP_Pos)       /*!< 0x00004000 */
+#define DFSDM_FLTISR_RCIP               DFSDM_FLTISR_RCIP_Msk                  /*!< Regular conversion in progress status */
+#define DFSDM_FLTISR_JCIP_Pos           (13U)
+#define DFSDM_FLTISR_JCIP_Msk           (0x1UL << DFSDM_FLTISR_JCIP_Pos)       /*!< 0x00002000 */
+#define DFSDM_FLTISR_JCIP               DFSDM_FLTISR_JCIP_Msk                  /*!< Injected conversion in progress status */
+#define DFSDM_FLTISR_AWDF_Pos           (4U)
+#define DFSDM_FLTISR_AWDF_Msk           (0x1UL << DFSDM_FLTISR_AWDF_Pos)       /*!< 0x00000010 */
+#define DFSDM_FLTISR_AWDF               DFSDM_FLTISR_AWDF_Msk                  /*!< Analog watchdog */
+#define DFSDM_FLTISR_ROVRF_Pos          (3U)
+#define DFSDM_FLTISR_ROVRF_Msk          (0x1UL << DFSDM_FLTISR_ROVRF_Pos)      /*!< 0x00000008 */
+#define DFSDM_FLTISR_ROVRF              DFSDM_FLTISR_ROVRF_Msk                 /*!< Regular conversion overrun flag */
+#define DFSDM_FLTISR_JOVRF_Pos          (2U)
+#define DFSDM_FLTISR_JOVRF_Msk          (0x1UL << DFSDM_FLTISR_JOVRF_Pos)      /*!< 0x00000004 */
+#define DFSDM_FLTISR_JOVRF              DFSDM_FLTISR_JOVRF_Msk                 /*!< Injected conversion overrun flag */
+#define DFSDM_FLTISR_REOCF_Pos          (1U)
+#define DFSDM_FLTISR_REOCF_Msk          (0x1UL << DFSDM_FLTISR_REOCF_Pos)      /*!< 0x00000002 */
+#define DFSDM_FLTISR_REOCF              DFSDM_FLTISR_REOCF_Msk                 /*!< End of regular conversion flag */
+#define DFSDM_FLTISR_JEOCF_Pos          (0U)
+#define DFSDM_FLTISR_JEOCF_Msk          (0x1UL << DFSDM_FLTISR_JEOCF_Pos)      /*!< 0x00000001 */
+#define DFSDM_FLTISR_JEOCF              DFSDM_FLTISR_JEOCF_Msk                 /*!< End of injected conversion flag */
+
+/********************  Bit definition for DFSDM_FLTICR register *******************/
+#define DFSDM_FLTICR_CLRSCDF_Pos        (24U)
+#define DFSDM_FLTICR_CLRSCDF_Msk        (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos)   /*!< 0xFF000000 */
+#define DFSDM_FLTICR_CLRSCDF            DFSDM_FLTICR_CLRSCDF_Msk               /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
+#define DFSDM_FLTICR_CLRCKABF_Pos       (16U)
+#define DFSDM_FLTICR_CLRCKABF_Msk       (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos)  /*!< 0x00FF0000 */
+#define DFSDM_FLTICR_CLRCKABF           DFSDM_FLTICR_CLRCKABF_Msk              /*!< CLRCKABF[7:0] Clear the clock absence flag */
+#define DFSDM_FLTICR_CLRROVRF_Pos       (3U)
+#define DFSDM_FLTICR_CLRROVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos)   /*!< 0x00000008 */
+#define DFSDM_FLTICR_CLRROVRF           DFSDM_FLTICR_CLRROVRF_Msk              /*!< Clear the regular conversion overrun flag */
+#define DFSDM_FLTICR_CLRJOVRF_Pos       (2U)
+#define DFSDM_FLTICR_CLRJOVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos)   /*!< 0x00000004 */
+#define DFSDM_FLTICR_CLRJOVRF           DFSDM_FLTICR_CLRJOVRF_Msk              /*!< Clear the injected conversion overrun flag */
+
+/*******************  Bit definition for DFSDM_FLTJCHGR register ******************/
+#define DFSDM_FLTJCHGR_JCHG_Pos         (0U)
+#define DFSDM_FLTJCHGR_JCHG_Msk         (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos)    /*!< 0x000000FF */
+#define DFSDM_FLTJCHGR_JCHG             DFSDM_FLTJCHGR_JCHG_Msk                /*!< JCHG[7:0] Injected channel group selection */
+
+/********************  Bit definition for DFSDM_FLTFCR register *******************/
+#define DFSDM_FLTFCR_FORD_Pos           (29U)
+#define DFSDM_FLTFCR_FORD_Msk           (0x7UL << DFSDM_FLTFCR_FORD_Pos)       /*!< 0xE0000000 */
+#define DFSDM_FLTFCR_FORD               DFSDM_FLTFCR_FORD_Msk                  /*!< FORD[2:0] Sinc filter order */
+#define DFSDM_FLTFCR_FORD_2             (0x4UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x80000000 */
+#define DFSDM_FLTFCR_FORD_1             (0x2UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x40000000 */
+#define DFSDM_FLTFCR_FORD_0             (0x1UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x20000000 */
+#define DFSDM_FLTFCR_FOSR_Pos           (16U)
+#define DFSDM_FLTFCR_FOSR_Msk           (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos)     /*!< 0x03FF0000 */
+#define DFSDM_FLTFCR_FOSR               DFSDM_FLTFCR_FOSR_Msk                  /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
+#define DFSDM_FLTFCR_IOSR_Pos           (0U)
+#define DFSDM_FLTFCR_IOSR_Msk           (0xFFUL << DFSDM_FLTFCR_IOSR_Pos)      /*!< 0x000000FF */
+#define DFSDM_FLTFCR_IOSR               DFSDM_FLTFCR_IOSR_Msk                  /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
+
+/******************  Bit definition for DFSDM_FLTJDATAR register *****************/
+#define DFSDM_FLTJDATAR_JDATA_Pos       (8U)
+#define DFSDM_FLTJDATAR_JDATA_Msk       (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTJDATAR_JDATA           DFSDM_FLTJDATAR_JDATA_Msk              /*!< JDATA[23:0] Injected group conversion data */
+#define DFSDM_FLTJDATAR_JDATACH_Pos     (0U)
+#define DFSDM_FLTJDATAR_JDATACH_Msk     (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */
+#define DFSDM_FLTJDATAR_JDATACH         DFSDM_FLTJDATAR_JDATACH_Msk            /*!< JDATACH[2:0] Injected channel most recently converted */
+
+/******************  Bit definition for DFSDM_FLTRDATAR register *****************/
+#define DFSDM_FLTRDATAR_RDATA_Pos       (8U)
+#define DFSDM_FLTRDATAR_RDATA_Msk       (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTRDATAR_RDATA           DFSDM_FLTRDATAR_RDATA_Msk              /*!< RDATA[23:0] Regular channel conversion data */
+#define DFSDM_FLTRDATAR_RPEND_Pos       (4U)
+#define DFSDM_FLTRDATAR_RPEND_Msk       (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos)   /*!< 0x00000010 */
+#define DFSDM_FLTRDATAR_RPEND           DFSDM_FLTRDATAR_RPEND_Msk              /*!< RPEND Regular channel pending data */
+#define DFSDM_FLTRDATAR_RDATACH_Pos     (0U)
+#define DFSDM_FLTRDATAR_RDATACH_Msk     (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */
+#define DFSDM_FLTRDATAR_RDATACH         DFSDM_FLTRDATAR_RDATACH_Msk            /*!< RDATACH[2:0] Regular channel most recently converted */
+
+/******************  Bit definition for DFSDM_FLTAWHTR register ******************/
+#define DFSDM_FLTAWHTR_AWHT_Pos         (8U)
+#define DFSDM_FLTAWHTR_AWHT_Msk         (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTAWHTR_AWHT             DFSDM_FLTAWHTR_AWHT_Msk                /*!< AWHT[23:0] Analog watchdog high threshold */
+#define DFSDM_FLTAWHTR_BKAWH_Pos        (0U)
+#define DFSDM_FLTAWHTR_BKAWH_Msk        (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)    /*!< 0x0000000F */
+#define DFSDM_FLTAWHTR_BKAWH            DFSDM_FLTAWHTR_BKAWH_Msk               /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
+
+/******************  Bit definition for DFSDM_FLTAWLTR register ******************/
+#define DFSDM_FLTAWLTR_AWLT_Pos         (8U)
+#define DFSDM_FLTAWLTR_AWLT_Msk         (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTAWLTR_AWLT             DFSDM_FLTAWLTR_AWLT_Msk                /*!< AWHT[23:0] Analog watchdog low threshold */
+#define DFSDM_FLTAWLTR_BKAWL_Pos        (0U)
+#define DFSDM_FLTAWLTR_BKAWL_Msk        (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos)    /*!< 0x0000000F */
+#define DFSDM_FLTAWLTR_BKAWL            DFSDM_FLTAWLTR_BKAWL_Msk               /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
+
+/******************  Bit definition for DFSDM_FLTAWSR register ******************/
+#define DFSDM_FLTAWSR_AWHTF_Pos         (8U)
+#define DFSDM_FLTAWSR_AWHTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos)    /*!< 0x0000FF00 */
+#define DFSDM_FLTAWSR_AWHTF             DFSDM_FLTAWSR_AWHTF_Msk                /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
+#define DFSDM_FLTAWSR_AWLTF_Pos         (0U)
+#define DFSDM_FLTAWSR_AWLTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos)    /*!< 0x000000FF */
+#define DFSDM_FLTAWSR_AWLTF             DFSDM_FLTAWSR_AWLTF_Msk                /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
+
+/******************  Bit definition for DFSDM_FLTAWCFR) register *****************/
+#define DFSDM_FLTAWCFR_CLRAWHTF_Pos     (8U)
+#define DFSDM_FLTAWCFR_CLRAWHTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */
+#define DFSDM_FLTAWCFR_CLRAWHTF         DFSDM_FLTAWCFR_CLRAWHTF_Msk            /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
+#define DFSDM_FLTAWCFR_CLRAWLTF_Pos     (0U)
+#define DFSDM_FLTAWCFR_CLRAWLTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */
+#define DFSDM_FLTAWCFR_CLRAWLTF         DFSDM_FLTAWCFR_CLRAWLTF_Msk            /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
+
+/******************  Bit definition for DFSDM_FLTEXMAX register ******************/
+#define DFSDM_FLTEXMAX_EXMAX_Pos        (8U)
+#define DFSDM_FLTEXMAX_EXMAX_Msk        (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTEXMAX_EXMAX            DFSDM_FLTEXMAX_EXMAX_Msk               /*!< EXMAX[23:0] Extreme detector maximum value */
+#define DFSDM_FLTEXMAX_EXMAXCH_Pos      (0U)
+#define DFSDM_FLTEXMAX_EXMAXCH_Msk      (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos)  /*!< 0x00000007 */
+#define DFSDM_FLTEXMAX_EXMAXCH          DFSDM_FLTEXMAX_EXMAXCH_Msk             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
+
+/******************  Bit definition for DFSDM_FLTEXMIN register ******************/
+#define DFSDM_FLTEXMIN_EXMIN_Pos        (8U)
+#define DFSDM_FLTEXMIN_EXMIN_Msk        (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTEXMIN_EXMIN            DFSDM_FLTEXMIN_EXMIN_Msk               /*!< EXMIN[23:0] Extreme detector minimum value */
+#define DFSDM_FLTEXMIN_EXMINCH_Pos      (0U)
+#define DFSDM_FLTEXMIN_EXMINCH_Msk      (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos)  /*!< 0x00000007 */
+#define DFSDM_FLTEXMIN_EXMINCH          DFSDM_FLTEXMIN_EXMINCH_Msk             /*!< EXMINCH[2:0] Extreme detector minimum data channel */
+
+/******************  Bit definition for DFSDM_FLTCNVTIMR register ******************/
+#define DFSDM_FLTCNVTIMR_CNVCNT_Pos     (4U)
+#define DFSDM_FLTCNVTIMR_CNVCNT_Msk     (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */
+#define DFSDM_FLTCNVTIMR_CNVCNT         DFSDM_FLTCNVTIMR_CNVCNT_Msk            /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           BDMA Controller                                  */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for BDMA_ISR register  ********************/
+#define BDMA_ISR_GIF0_Pos       (0U)
+#define BDMA_ISR_GIF0_Msk       (0x1UL << BDMA_ISR_GIF0_Pos)                   /*!< 0x00000001 */
+#define BDMA_ISR_GIF0           BDMA_ISR_GIF0_Msk                              /*!< Channel 0 Global interrupt flag */
+#define BDMA_ISR_TCIF0_Pos      (1U)
+#define BDMA_ISR_TCIF0_Msk      (0x1UL << BDMA_ISR_TCIF0_Pos)                  /*!< 0x00000002 */
+#define BDMA_ISR_TCIF0          BDMA_ISR_TCIF0_Msk                             /*!< Channel 0 Transfer Complete flag */
+#define BDMA_ISR_HTIF0_Pos      (2U)
+#define BDMA_ISR_HTIF0_Msk      (0x1UL << BDMA_ISR_HTIF0_Pos)                  /*!< 0x00000004 */
+#define BDMA_ISR_HTIF0          BDMA_ISR_HTIF0_Msk                             /*!< Channel 0 Half Transfer flag */
+#define BDMA_ISR_TEIF0_Pos      (3U)
+#define BDMA_ISR_TEIF0_Msk      (0x1UL << BDMA_ISR_TEIF0_Pos)                  /*!< 0x00000008 */
+#define BDMA_ISR_TEIF0          BDMA_ISR_TEIF0_Msk                             /*!< Channel 0 Transfer Error flag */
+#define BDMA_ISR_GIF1_Pos       (4U)
+#define BDMA_ISR_GIF1_Msk       (0x1UL << BDMA_ISR_GIF1_Pos)                   /*!< 0x00000010 */
+#define BDMA_ISR_GIF1           BDMA_ISR_GIF1_Msk                              /*!< Channel 1 Global interrupt flag */
+#define BDMA_ISR_TCIF1_Pos      (5U)
+#define BDMA_ISR_TCIF1_Msk      (0x1UL << BDMA_ISR_TCIF1_Pos)                  /*!< 0x00000020 */
+#define BDMA_ISR_TCIF1          BDMA_ISR_TCIF1_Msk                             /*!< Channel 1 Transfer Complete flag */
+#define BDMA_ISR_HTIF1_Pos      (6U)
+#define BDMA_ISR_HTIF1_Msk      (0x1UL << BDMA_ISR_HTIF1_Pos)                  /*!< 0x00000040 */
+#define BDMA_ISR_HTIF1          BDMA_ISR_HTIF1_Msk                             /*!< Channel 1 Half Transfer flag */
+#define BDMA_ISR_TEIF1_Pos      (7U)
+#define BDMA_ISR_TEIF1_Msk      (0x1UL << BDMA_ISR_TEIF1_Pos)                  /*!< 0x00000080 */
+#define BDMA_ISR_TEIF1          BDMA_ISR_TEIF1_Msk                             /*!< Channel 1 Transfer Error flag */
+#define BDMA_ISR_GIF2_Pos       (8U)
+#define BDMA_ISR_GIF2_Msk       (0x1UL << BDMA_ISR_GIF2_Pos)                   /*!< 0x00000100 */
+#define BDMA_ISR_GIF2           BDMA_ISR_GIF2_Msk                              /*!< Channel 2 Global interrupt flag */
+#define BDMA_ISR_TCIF2_Pos      (9U)
+#define BDMA_ISR_TCIF2_Msk      (0x1UL << BDMA_ISR_TCIF2_Pos)                  /*!< 0x00000200 */
+#define BDMA_ISR_TCIF2          BDMA_ISR_TCIF2_Msk                             /*!< Channel 2 Transfer Complete flag */
+#define BDMA_ISR_HTIF2_Pos      (10U)
+#define BDMA_ISR_HTIF2_Msk      (0x1UL << BDMA_ISR_HTIF2_Pos)                  /*!< 0x00000400 */
+#define BDMA_ISR_HTIF2          BDMA_ISR_HTIF2_Msk                             /*!< Channel 2 Half Transfer flag */
+#define BDMA_ISR_TEIF2_Pos      (11U)
+#define BDMA_ISR_TEIF2_Msk      (0x1UL << BDMA_ISR_TEIF2_Pos)                  /*!< 0x00000800 */
+#define BDMA_ISR_TEIF2          BDMA_ISR_TEIF2_Msk                             /*!< Channel 2 Transfer Error flag */
+#define BDMA_ISR_GIF3_Pos       (12U)
+#define BDMA_ISR_GIF3_Msk       (0x1UL << BDMA_ISR_GIF3_Pos)                   /*!< 0x00001000 */
+#define BDMA_ISR_GIF3           BDMA_ISR_GIF3_Msk                              /*!< Channel 3 Global interrupt flag */
+#define BDMA_ISR_TCIF3_Pos      (13U)
+#define BDMA_ISR_TCIF3_Msk      (0x1UL << BDMA_ISR_TCIF3_Pos)                  /*!< 0x00002000 */
+#define BDMA_ISR_TCIF3          BDMA_ISR_TCIF3_Msk                             /*!< Channel 3 Transfer Complete flag */
+#define BDMA_ISR_HTIF3_Pos      (14U)
+#define BDMA_ISR_HTIF3_Msk      (0x1UL << BDMA_ISR_HTIF3_Pos)                  /*!< 0x00004000 */
+#define BDMA_ISR_HTIF3          BDMA_ISR_HTIF3_Msk                             /*!< Channel 3 Half Transfer flag */
+#define BDMA_ISR_TEIF3_Pos      (15U)
+#define BDMA_ISR_TEIF3_Msk      (0x1UL << BDMA_ISR_TEIF3_Pos)                  /*!< 0x00008000 */
+#define BDMA_ISR_TEIF3          BDMA_ISR_TEIF3_Msk                             /*!< Channel 3 Transfer Error flag */
+#define BDMA_ISR_GIF4_Pos       (16U)
+#define BDMA_ISR_GIF4_Msk       (0x1UL << BDMA_ISR_GIF4_Pos)                   /*!< 0x00010000 */
+#define BDMA_ISR_GIF4           BDMA_ISR_GIF4_Msk                              /*!< Channel 4 Global interrupt flag */
+#define BDMA_ISR_TCIF4_Pos      (17U)
+#define BDMA_ISR_TCIF4_Msk      (0x1UL << BDMA_ISR_TCIF4_Pos)                  /*!< 0x00020000 */
+#define BDMA_ISR_TCIF4          BDMA_ISR_TCIF4_Msk                             /*!< Channel 4 Transfer Complete flag */
+#define BDMA_ISR_HTIF4_Pos      (18U)
+#define BDMA_ISR_HTIF4_Msk      (0x1UL << BDMA_ISR_HTIF4_Pos)                  /*!< 0x00040000 */
+#define BDMA_ISR_HTIF4          BDMA_ISR_HTIF4_Msk                             /*!< Channel 4 Half Transfer flag */
+#define BDMA_ISR_TEIF4_Pos      (19U)
+#define BDMA_ISR_TEIF4_Msk      (0x1UL << BDMA_ISR_TEIF4_Pos)                  /*!< 0x00080000 */
+#define BDMA_ISR_TEIF4          BDMA_ISR_TEIF4_Msk                             /*!< Channel 4 Transfer Error flag */
+#define BDMA_ISR_GIF5_Pos       (20U)
+#define BDMA_ISR_GIF5_Msk       (0x1UL << BDMA_ISR_GIF5_Pos)                   /*!< 0x00100000 */
+#define BDMA_ISR_GIF5           BDMA_ISR_GIF5_Msk                              /*!< Channel 5 Global interrupt flag */
+#define BDMA_ISR_TCIF5_Pos      (21U)
+#define BDMA_ISR_TCIF5_Msk      (0x1UL << BDMA_ISR_TCIF5_Pos)                  /*!< 0x00200000 */
+#define BDMA_ISR_TCIF5          BDMA_ISR_TCIF5_Msk                             /*!< Channel 5 Transfer Complete flag */
+#define BDMA_ISR_HTIF5_Pos      (22U)
+#define BDMA_ISR_HTIF5_Msk      (0x1UL << BDMA_ISR_HTIF5_Pos)                  /*!< 0x00400000 */
+#define BDMA_ISR_HTIF5          BDMA_ISR_HTIF5_Msk                             /*!< Channel 5 Half Transfer flag */
+#define BDMA_ISR_TEIF5_Pos      (23U)
+#define BDMA_ISR_TEIF5_Msk      (0x1UL << BDMA_ISR_TEIF5_Pos)                  /*!< 0x00800000 */
+#define BDMA_ISR_TEIF5          BDMA_ISR_TEIF5_Msk                             /*!< Channel 5 Transfer Error flag */
+#define BDMA_ISR_GIF6_Pos       (24U)
+#define BDMA_ISR_GIF6_Msk       (0x1UL << BDMA_ISR_GIF6_Pos)                   /*!< 0x01000000 */
+#define BDMA_ISR_GIF6           BDMA_ISR_GIF6_Msk                              /*!< Channel 6 Global interrupt flag */
+#define BDMA_ISR_TCIF6_Pos      (25U)
+#define BDMA_ISR_TCIF6_Msk      (0x1UL << BDMA_ISR_TCIF6_Pos)                  /*!< 0x02000000 */
+#define BDMA_ISR_TCIF6          BDMA_ISR_TCIF6_Msk                             /*!< Channel 6 Transfer Complete flag */
+#define BDMA_ISR_HTIF6_Pos      (26U)
+#define BDMA_ISR_HTIF6_Msk      (0x1UL << BDMA_ISR_HTIF6_Pos)                  /*!< 0x04000000 */
+#define BDMA_ISR_HTIF6          BDMA_ISR_HTIF6_Msk                             /*!< Channel 6 Half Transfer flag */
+#define BDMA_ISR_TEIF6_Pos      (27U)
+#define BDMA_ISR_TEIF6_Msk      (0x1UL << BDMA_ISR_TEIF6_Pos)                  /*!< 0x08000000 */
+#define BDMA_ISR_TEIF6          BDMA_ISR_TEIF6_Msk                             /*!< Channel 6 Transfer Error flag */
+#define BDMA_ISR_GIF7_Pos       (28U)
+#define BDMA_ISR_GIF7_Msk       (0x1UL << BDMA_ISR_GIF7_Pos)                   /*!< 0x10000000 */
+#define BDMA_ISR_GIF7           BDMA_ISR_GIF7_Msk                              /*!< Channel 7 Global interrupt flag */
+#define BDMA_ISR_TCIF7_Pos      (29U)
+#define BDMA_ISR_TCIF7_Msk      (0x1UL << BDMA_ISR_TCIF7_Pos)                  /*!< 0x20000000 */
+#define BDMA_ISR_TCIF7          BDMA_ISR_TCIF7_Msk                             /*!< Channel 7 Transfer Complete flag */
+#define BDMA_ISR_HTIF7_Pos      (30U)
+#define BDMA_ISR_HTIF7_Msk      (0x1UL << BDMA_ISR_HTIF7_Pos)                  /*!< 0x40000000 */
+#define BDMA_ISR_HTIF7          BDMA_ISR_HTIF7_Msk                             /*!< Channel 7 Half Transfer flag */
+#define BDMA_ISR_TEIF7_Pos      (31U)
+#define BDMA_ISR_TEIF7_Msk      (0x1UL << BDMA_ISR_TEIF7_Pos)                  /*!< 0x80000000 */
+#define BDMA_ISR_TEIF7          BDMA_ISR_TEIF7_Msk                             /*!< Channel 7 Transfer Error flag */
+
+/*******************  Bit definition for BDMA_IFCR register  *******************/
+#define BDMA_IFCR_CGIF0_Pos     (0U)
+#define BDMA_IFCR_CGIF0_Msk     (0x1UL << BDMA_IFCR_CGIF0_Pos)                 /*!< 0x00000001 */
+#define BDMA_IFCR_CGIF0         BDMA_IFCR_CGIF0_Msk                            /*!< Channel 0 Global interrupt clearr */
+#define BDMA_IFCR_CTCIF0_Pos    (1U)
+#define BDMA_IFCR_CTCIF0_Msk    (0x1UL << BDMA_IFCR_CTCIF0_Pos)                /*!< 0x00000002 */
+#define BDMA_IFCR_CTCIF0        BDMA_IFCR_CTCIF0_Msk                           /*!< Channel 0 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF0_Pos    (2U)
+#define BDMA_IFCR_CHTIF0_Msk    (0x1UL << BDMA_IFCR_CHTIF0_Pos)                /*!< 0x00000004 */
+#define BDMA_IFCR_CHTIF0        BDMA_IFCR_CHTIF0_Msk                           /*!< Channel 0 Half Transfer clear */
+#define BDMA_IFCR_CTEIF0_Pos    (3U)
+#define BDMA_IFCR_CTEIF0_Msk    (0x1UL << BDMA_IFCR_CTEIF0_Pos)                /*!< 0x00000008 */
+#define BDMA_IFCR_CTEIF0        BDMA_IFCR_CTEIF0_Msk                           /*!< Channel 0 Transfer Error clear */
+#define BDMA_IFCR_CGIF1_Pos     (4U)
+#define BDMA_IFCR_CGIF1_Msk     (0x1UL << BDMA_IFCR_CGIF1_Pos)                 /*!< 0x00000010 */
+#define BDMA_IFCR_CGIF1         BDMA_IFCR_CGIF1_Msk                            /*!< Channel 1 Global interrupt clear */
+#define BDMA_IFCR_CTCIF1_Pos    (5U)
+#define BDMA_IFCR_CTCIF1_Msk    (0x1UL << BDMA_IFCR_CTCIF1_Pos)                /*!< 0x00000020 */
+#define BDMA_IFCR_CTCIF1        BDMA_IFCR_CTCIF1_Msk                           /*!< Channel 1 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF1_Pos    (6U)
+#define BDMA_IFCR_CHTIF1_Msk    (0x1UL << BDMA_IFCR_CHTIF1_Pos)                /*!< 0x00000040 */
+#define BDMA_IFCR_CHTIF1        BDMA_IFCR_CHTIF1_Msk                           /*!< Channel 1 Half Transfer clear */
+#define BDMA_IFCR_CTEIF1_Pos    (7U)
+#define BDMA_IFCR_CTEIF1_Msk    (0x1UL << BDMA_IFCR_CTEIF1_Pos)                /*!< 0x00000080 */
+#define BDMA_IFCR_CTEIF1        BDMA_IFCR_CTEIF1_Msk                           /*!< Channel 1 Transfer Error clear */
+#define BDMA_IFCR_CGIF2_Pos     (8U)
+#define BDMA_IFCR_CGIF2_Msk     (0x1UL << BDMA_IFCR_CGIF2_Pos)                 /*!< 0x00000100 */
+#define BDMA_IFCR_CGIF2         BDMA_IFCR_CGIF2_Msk                            /*!< Channel 2 Global interrupt clear */
+#define BDMA_IFCR_CTCIF2_Pos    (9U)
+#define BDMA_IFCR_CTCIF2_Msk    (0x1UL << BDMA_IFCR_CTCIF2_Pos)                /*!< 0x00000200 */
+#define BDMA_IFCR_CTCIF2        BDMA_IFCR_CTCIF2_Msk                           /*!< Channel 2 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF2_Pos    (10U)
+#define BDMA_IFCR_CHTIF2_Msk    (0x1UL << BDMA_IFCR_CHTIF2_Pos)                /*!< 0x00000400 */
+#define BDMA_IFCR_CHTIF2        BDMA_IFCR_CHTIF2_Msk                           /*!< Channel 2 Half Transfer clear */
+#define BDMA_IFCR_CTEIF2_Pos    (11U)
+#define BDMA_IFCR_CTEIF2_Msk    (0x1UL << BDMA_IFCR_CTEIF2_Pos)                /*!< 0x00000800 */
+#define BDMA_IFCR_CTEIF2        BDMA_IFCR_CTEIF2_Msk                           /*!< Channel 2 Transfer Error clear */
+#define BDMA_IFCR_CGIF3_Pos     (12U)
+#define BDMA_IFCR_CGIF3_Msk     (0x1UL << BDMA_IFCR_CGIF3_Pos)                 /*!< 0x00001000 */
+#define BDMA_IFCR_CGIF3         BDMA_IFCR_CGIF3_Msk                            /*!< Channel 3 Global interrupt clear */
+#define BDMA_IFCR_CTCIF3_Pos    (13U)
+#define BDMA_IFCR_CTCIF3_Msk    (0x1UL << BDMA_IFCR_CTCIF3_Pos)                /*!< 0x00002000 */
+#define BDMA_IFCR_CTCIF3        BDMA_IFCR_CTCIF3_Msk                           /*!< Channel 3 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF3_Pos    (14U)
+#define BDMA_IFCR_CHTIF3_Msk    (0x1UL << BDMA_IFCR_CHTIF3_Pos)                /*!< 0x00004000 */
+#define BDMA_IFCR_CHTIF3        BDMA_IFCR_CHTIF3_Msk                           /*!< Channel 3 Half Transfer clear */
+#define BDMA_IFCR_CTEIF3_Pos    (15U)
+#define BDMA_IFCR_CTEIF3_Msk    (0x1UL << BDMA_IFCR_CTEIF3_Pos)                /*!< 0x00008000 */
+#define BDMA_IFCR_CTEIF3        BDMA_IFCR_CTEIF3_Msk                           /*!< Channel 3 Transfer Error clear */
+#define BDMA_IFCR_CGIF4_Pos     (16U)
+#define BDMA_IFCR_CGIF4_Msk     (0x1UL << BDMA_IFCR_CGIF4_Pos)                 /*!< 0x00010000 */
+#define BDMA_IFCR_CGIF4         BDMA_IFCR_CGIF4_Msk                            /*!< Channel 4 Global interrupt clear */
+#define BDMA_IFCR_CTCIF4_Pos    (17U)
+#define BDMA_IFCR_CTCIF4_Msk    (0x1UL << BDMA_IFCR_CTCIF4_Pos)                /*!< 0x00020000 */
+#define BDMA_IFCR_CTCIF4        BDMA_IFCR_CTCIF4_Msk                           /*!< Channel 4 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF4_Pos    (18U)
+#define BDMA_IFCR_CHTIF4_Msk    (0x1UL << BDMA_IFCR_CHTIF4_Pos)                /*!< 0x00040000 */
+#define BDMA_IFCR_CHTIF4        BDMA_IFCR_CHTIF4_Msk                           /*!< Channel 4 Half Transfer clear */
+#define BDMA_IFCR_CTEIF4_Pos    (19U)
+#define BDMA_IFCR_CTEIF4_Msk    (0x1UL << BDMA_IFCR_CTEIF4_Pos)                /*!< 0x00080000 */
+#define BDMA_IFCR_CTEIF4        BDMA_IFCR_CTEIF4_Msk                           /*!< Channel 4 Transfer Error clear */
+#define BDMA_IFCR_CGIF5_Pos     (20U)
+#define BDMA_IFCR_CGIF5_Msk     (0x1UL << BDMA_IFCR_CGIF5_Pos)                 /*!< 0x00100000 */
+#define BDMA_IFCR_CGIF5         BDMA_IFCR_CGIF5_Msk                            /*!< Channel 5 Global interrupt clear */
+#define BDMA_IFCR_CTCIF5_Pos    (21U)
+#define BDMA_IFCR_CTCIF5_Msk    (0x1UL << BDMA_IFCR_CTCIF5_Pos)                /*!< 0x00200000 */
+#define BDMA_IFCR_CTCIF5        BDMA_IFCR_CTCIF5_Msk                           /*!< Channel 5 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF5_Pos    (22U)
+#define BDMA_IFCR_CHTIF5_Msk    (0x1UL << BDMA_IFCR_CHTIF5_Pos)                /*!< 0x00400000 */
+#define BDMA_IFCR_CHTIF5        BDMA_IFCR_CHTIF5_Msk                           /*!< Channel 5 Half Transfer clear */
+#define BDMA_IFCR_CTEIF5_Pos    (23U)
+#define BDMA_IFCR_CTEIF5_Msk    (0x1UL << BDMA_IFCR_CTEIF5_Pos)                /*!< 0x00800000 */
+#define BDMA_IFCR_CTEIF5        BDMA_IFCR_CTEIF5_Msk                           /*!< Channel 5 Transfer Error clear */
+#define BDMA_IFCR_CGIF6_Pos     (24U)
+#define BDMA_IFCR_CGIF6_Msk     (0x1UL << BDMA_IFCR_CGIF6_Pos)                 /*!< 0x01000000 */
+#define BDMA_IFCR_CGIF6         BDMA_IFCR_CGIF6_Msk                            /*!< Channel 6 Global interrupt clear */
+#define BDMA_IFCR_CTCIF6_Pos    (25U)
+#define BDMA_IFCR_CTCIF6_Msk    (0x1UL << BDMA_IFCR_CTCIF6_Pos)                /*!< 0x02000000 */
+#define BDMA_IFCR_CTCIF6        BDMA_IFCR_CTCIF6_Msk                           /*!< Channel 6 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF6_Pos    (26U)
+#define BDMA_IFCR_CHTIF6_Msk    (0x1UL << BDMA_IFCR_CHTIF6_Pos)                /*!< 0x04000000 */
+#define BDMA_IFCR_CHTIF6        BDMA_IFCR_CHTIF6_Msk                           /*!< Channel 6 Half Transfer clear */
+#define BDMA_IFCR_CTEIF6_Pos    (27U)
+#define BDMA_IFCR_CTEIF6_Msk    (0x1UL << BDMA_IFCR_CTEIF6_Pos)                /*!< 0x08000000 */
+#define BDMA_IFCR_CTEIF6        BDMA_IFCR_CTEIF6_Msk                           /*!< Channel 6 Transfer Error clear */
+#define BDMA_IFCR_CGIF7_Pos     (28U)
+#define BDMA_IFCR_CGIF7_Msk     (0x1UL << BDMA_IFCR_CGIF7_Pos)                 /*!< 0x10000000 */
+#define BDMA_IFCR_CGIF7         BDMA_IFCR_CGIF7_Msk                            /*!< Channel 7 Global interrupt clear */
+#define BDMA_IFCR_CTCIF7_Pos    (29U)
+#define BDMA_IFCR_CTCIF7_Msk    (0x1UL << BDMA_IFCR_CTCIF7_Pos)                /*!< 0x20000000 */
+#define BDMA_IFCR_CTCIF7        BDMA_IFCR_CTCIF7_Msk                           /*!< Channel 7 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF7_Pos    (30U)
+#define BDMA_IFCR_CHTIF7_Msk    (0x1UL << BDMA_IFCR_CHTIF7_Pos)                /*!< 0x40000000 */
+#define BDMA_IFCR_CHTIF7        BDMA_IFCR_CHTIF7_Msk                           /*!< Channel 7 Half Transfer clear */
+#define BDMA_IFCR_CTEIF7_Pos    (31U)
+#define BDMA_IFCR_CTEIF7_Msk    (0x1UL << BDMA_IFCR_CTEIF7_Pos)                /*!< 0x80000000 */
+#define BDMA_IFCR_CTEIF7        BDMA_IFCR_CTEIF7_Msk                           /*!< Channel 7 Transfer Error clear */
+
+/*******************  Bit definition for BDMA_CCR register  ********************/
+#define BDMA_CCR_EN_Pos         (0U)
+#define BDMA_CCR_EN_Msk         (0x1UL << BDMA_CCR_EN_Pos)                     /*!< 0x00000001 */
+#define BDMA_CCR_EN             BDMA_CCR_EN_Msk                                /*!< Channel enable                      */
+#define BDMA_CCR_TCIE_Pos       (1U)
+#define BDMA_CCR_TCIE_Msk       (0x1UL << BDMA_CCR_TCIE_Pos)                   /*!< 0x00000002 */
+#define BDMA_CCR_TCIE           BDMA_CCR_TCIE_Msk                              /*!< Transfer complete interrupt enable  */
+#define BDMA_CCR_HTIE_Pos       (2U)
+#define BDMA_CCR_HTIE_Msk       (0x1UL << BDMA_CCR_HTIE_Pos)                   /*!< 0x00000004 */
+#define BDMA_CCR_HTIE           BDMA_CCR_HTIE_Msk                              /*!< Half Transfer interrupt enable      */
+#define BDMA_CCR_TEIE_Pos       (3U)
+#define BDMA_CCR_TEIE_Msk       (0x1UL << BDMA_CCR_TEIE_Pos)                   /*!< 0x00000008 */
+#define BDMA_CCR_TEIE           BDMA_CCR_TEIE_Msk                              /*!< Transfer error interrupt enable     */
+#define BDMA_CCR_DIR_Pos        (4U)
+#define BDMA_CCR_DIR_Msk        (0x1UL << BDMA_CCR_DIR_Pos)                    /*!< 0x00000010 */
+#define BDMA_CCR_DIR            BDMA_CCR_DIR_Msk                               /*!< Data transfer direction             */
+#define BDMA_CCR_CIRC_Pos       (5U)
+#define BDMA_CCR_CIRC_Msk       (0x1UL << BDMA_CCR_CIRC_Pos)                   /*!< 0x00000020 */
+#define BDMA_CCR_CIRC           BDMA_CCR_CIRC_Msk                              /*!< Circular mode                       */
+#define BDMA_CCR_PINC_Pos       (6U)
+#define BDMA_CCR_PINC_Msk       (0x1UL << BDMA_CCR_PINC_Pos)                   /*!< 0x00000040 */
+#define BDMA_CCR_PINC           BDMA_CCR_PINC_Msk                              /*!< Peripheral increment mode           */
+#define BDMA_CCR_MINC_Pos       (7U)
+#define BDMA_CCR_MINC_Msk       (0x1UL << BDMA_CCR_MINC_Pos)                   /*!< 0x00000080 */
+#define BDMA_CCR_MINC           BDMA_CCR_MINC_Msk                              /*!< Memory increment mode               */
+
+#define BDMA_CCR_PSIZE_Pos      (8U)
+#define BDMA_CCR_PSIZE_Msk      (0x3UL << BDMA_CCR_PSIZE_Pos)                  /*!< 0x00000300 */
+#define BDMA_CCR_PSIZE          BDMA_CCR_PSIZE_Msk                             /*!< PSIZE[1:0] bits (Peripheral size)   */
+#define BDMA_CCR_PSIZE_0        (0x1UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000100 */
+#define BDMA_CCR_PSIZE_1        (0x2UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000200 */
+
+#define BDMA_CCR_MSIZE_Pos      (10U)
+#define BDMA_CCR_MSIZE_Msk      (0x3UL << BDMA_CCR_MSIZE_Pos)                  /*!< 0x00000C00 */
+#define BDMA_CCR_MSIZE          BDMA_CCR_MSIZE_Msk                             /*!< MSIZE[1:0] bits (Memory size)       */
+#define BDMA_CCR_MSIZE_0        (0x1UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000400 */
+#define BDMA_CCR_MSIZE_1        (0x2UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000800 */
+
+#define BDMA_CCR_PL_Pos         (12U)
+#define BDMA_CCR_PL_Msk         (0x3UL << BDMA_CCR_PL_Pos)                     /*!< 0x00003000 */
+#define BDMA_CCR_PL             BDMA_CCR_PL_Msk                                /*!< PL[1:0] bits(Channel Priority level)*/
+#define BDMA_CCR_PL_0           (0x1UL << BDMA_CCR_PL_Pos)                      /*!< 0x00001000 */
+#define BDMA_CCR_PL_1           (0x2UL << BDMA_CCR_PL_Pos)                      /*!< 0x00002000 */
+
+#define BDMA_CCR_MEM2MEM_Pos    (14U)
+#define BDMA_CCR_MEM2MEM_Msk    (0x1UL << BDMA_CCR_MEM2MEM_Pos)                /*!< 0x00004000 */
+#define BDMA_CCR_MEM2MEM        BDMA_CCR_MEM2MEM_Msk                           /*!< Memory to memory mode               */
+#define BDMA_CCR_DBM_Pos        (15U)
+#define BDMA_CCR_DBM_Msk        (0x1UL << BDMA_CCR_DBM_Pos)                    /*!< 0x0000A000 */
+#define BDMA_CCR_DBM            BDMA_CCR_DBM_Msk                               /*!< Memory to memory mode               */
+#define BDMA_CCR_CT_Pos         (16U)
+#define BDMA_CCR_CT_Msk         (0x1UL << BDMA_CCR_CT_Pos)                     /*!< 0x00010000 */
+#define BDMA_CCR_CT             BDMA_CCR_CT_Msk                                /*!< Memory to memory mode               */
+
+/******************  Bit definition for BDMA_CNDTR register  *******************/
+#define BDMA_CNDTR_NDT_Pos      (0U)
+#define BDMA_CNDTR_NDT_Msk      (0xFFFFUL << BDMA_CNDTR_NDT_Pos)               /*!< 0x0000FFFF */
+#define BDMA_CNDTR_NDT          BDMA_CNDTR_NDT_Msk                             /*!< Number of data to Transfer          */
+
+/******************  Bit definition for BDMA_CPAR register  ********************/
+#define BDMA_CPAR_PA_Pos        (0U)
+#define BDMA_CPAR_PA_Msk        (0xFFFFFFFFUL << BDMA_CPAR_PA_Pos)             /*!< 0xFFFFFFFF */
+#define BDMA_CPAR_PA            BDMA_CPAR_PA_Msk                               /*!< Peripheral Address                  */
+
+/******************  Bit definition for BDMA_CM0AR register  ********************/
+#define BDMA_CM0AR_MA_Pos        (0U)
+#define BDMA_CM0AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM0AR_MA_Pos)             /*!< 0xFFFFFFFF */
+#define BDMA_CM0AR_MA            BDMA_CM0AR_MA_Msk                               /*!< Memory Address                      */
+
+/******************  Bit definition for BDMA_CM1AR register  ********************/
+#define BDMA_CM1AR_MA_Pos        (0U)
+#define BDMA_CM1AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM1AR_MA_Pos)             /*!< 0xFFFFFFFF */
+#define BDMA_CM1AR_MA            BDMA_CM1AR_MA_Msk                               /*!< Memory Address                      */
+
+/******************************************************************************/
+/*                                                                            */
+/*                Ethernet MAC Registers bits definitions                     */
+/*                                                                            */
+/******************************************************************************/
+/* Bit definition for Ethernet MAC Configuration Register register */
+#define ETH_MACCR_ARP_Pos                             (31U)
+#define ETH_MACCR_ARP_Msk                             (0x1UL << ETH_MACCR_ARP_Pos) /*!< 0x80000000 */
+#define ETH_MACCR_ARP                                 ETH_MACCR_ARP_Msk        /* ARP Offload Enable */
+#define ETH_MACCR_SARC_Pos                            (28U)
+#define ETH_MACCR_SARC_Msk                            (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
+#define ETH_MACCR_SARC                                ETH_MACCR_SARC_Msk       /* Source Address Insertion or Replacement Control */
+#define ETH_MACCR_SARC_MTIATI                         ((uint32_t)0x00000000)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
+#define ETH_MACCR_SARC_INSADDR0_Pos                   (29U)
+#define ETH_MACCR_SARC_INSADDR0_Msk                   (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
+#define ETH_MACCR_SARC_INSADDR0                       ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
+#define ETH_MACCR_SARC_INSADDR1_Pos                   (29U)
+#define ETH_MACCR_SARC_INSADDR1_Msk                   (0x3UL << ETH_MACCR_SARC_INSADDR1_Pos) /*!< 0x60000000 */
+#define ETH_MACCR_SARC_INSADDR1                       ETH_MACCR_SARC_INSADDR1_Msk /* Insert MAC Address1 in the SA field of all transmitted packets. */
+#define ETH_MACCR_SARC_REPADDR0_Pos                   (28U)
+#define ETH_MACCR_SARC_REPADDR0_Msk                   (0x3UL << ETH_MACCR_SARC_REPADDR0_Pos) /*!< 0x30000000 */
+#define ETH_MACCR_SARC_REPADDR0                       ETH_MACCR_SARC_REPADDR0_Msk /* Replace MAC Address0 in the SA field of all transmitted packets. */
+#define ETH_MACCR_SARC_REPADDR1_Pos                   (28U)
+#define ETH_MACCR_SARC_REPADDR1_Msk                   (0x7UL << ETH_MACCR_SARC_REPADDR1_Pos) /*!< 0x70000000 */
+#define ETH_MACCR_SARC_REPADDR1                       ETH_MACCR_SARC_REPADDR1_Msk /* Replace MAC Address1 in the SA field of all transmitted packets. */
+#define ETH_MACCR_IPC_Pos                             (27U)
+#define ETH_MACCR_IPC_Msk                             (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */
+#define ETH_MACCR_IPC                                 ETH_MACCR_IPC_Msk        /* Checksum Offload */
+#define ETH_MACCR_IPG_Pos                             (24U)
+#define ETH_MACCR_IPG_Msk                             (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
+#define ETH_MACCR_IPG                                 ETH_MACCR_IPG_Msk        /* Inter-Packet Gap */
+#define ETH_MACCR_IPG_96BIT                           ((uint32_t)0x00000000)   /* Minimum IFG between Packets during transmission is 96Bit */
+#define ETH_MACCR_IPG_88BIT                           ((uint32_t)0x01000000)   /* Minimum IFG between Packets during transmission is 88Bit */
+#define ETH_MACCR_IPG_80BIT                           ((uint32_t)0x02000000)   /* Minimum IFG between Packets during transmission is 80Bit */
+#define ETH_MACCR_IPG_72BIT                           ((uint32_t)0x03000000)   /* Minimum IFG between Packets during transmission is 72Bit */
+#define ETH_MACCR_IPG_64BIT                           ((uint32_t)0x04000000)   /* Minimum IFG between Packets during transmission is 64Bit */
+#define ETH_MACCR_IPG_56BIT                           ((uint32_t)0x05000000)   /* Minimum IFG between Packets during transmission is 56Bit */
+#define ETH_MACCR_IPG_48BIT                           ((uint32_t)0x06000000)   /* Minimum IFG between Packets during transmission is 48Bit */
+#define ETH_MACCR_IPG_40BIT                           ((uint32_t)0x07000000)   /* Minimum IFG between Packets during transmission is 40Bit */
+#define ETH_MACCR_GPSLCE_Pos                          (23U)
+#define ETH_MACCR_GPSLCE_Msk                          (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
+#define ETH_MACCR_GPSLCE                              ETH_MACCR_GPSLCE_Msk     /* Giant Packet Size Limit Control Enable */
+#define ETH_MACCR_S2KP_Pos                            (22U)
+#define ETH_MACCR_S2KP_Msk                            (0x1UL << ETH_MACCR_S2KP_Pos) /*!< 0x00400000 */
+#define ETH_MACCR_S2KP                                ETH_MACCR_S2KP_Msk       /* IEEE 802.3as Support for 2K Packets */
+#define ETH_MACCR_CST_Pos                             (21U)
+#define ETH_MACCR_CST_Msk                             (0x1UL << ETH_MACCR_CST_Pos) /*!< 0x00200000 */
+#define ETH_MACCR_CST                                 ETH_MACCR_CST_Msk        /* CRC stripping for Type packets */
+#define ETH_MACCR_ACS_Pos                             (20U)
+#define ETH_MACCR_ACS_Msk                             (0x1UL << ETH_MACCR_ACS_Pos) /*!< 0x00100000 */
+#define ETH_MACCR_ACS                                 ETH_MACCR_ACS_Msk        /* Automatic Pad or CRC Stripping */
+#define ETH_MACCR_WD_Pos                              (19U)
+#define ETH_MACCR_WD_Msk                              (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00080000 */
+#define ETH_MACCR_WD                                  ETH_MACCR_WD_Msk         /* Watchdog disable */
+#define ETH_MACCR_JD_Pos                              (17U)
+#define ETH_MACCR_JD_Msk                              (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00020000 */
+#define ETH_MACCR_JD                                  ETH_MACCR_JD_Msk         /* Jabber disable */
+#define ETH_MACCR_JE_Pos                              (16U)
+#define ETH_MACCR_JE_Msk                              (0x1UL << ETH_MACCR_JE_Pos) /*!< 0x00010000 */
+#define ETH_MACCR_JE                                  ETH_MACCR_JE_Msk         /* Jumbo Packet Enable */
+#define ETH_MACCR_FES_Pos                             (14U)
+#define ETH_MACCR_FES_Msk                             (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
+#define ETH_MACCR_FES                                 ETH_MACCR_FES_Msk        /* Fast ethernet speed */
+#define ETH_MACCR_DM_Pos                              (13U)
+#define ETH_MACCR_DM_Msk                              (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00002000 */
+#define ETH_MACCR_DM                                  ETH_MACCR_DM_Msk         /* Duplex mode */
+#define ETH_MACCR_LM_Pos                              (12U)
+#define ETH_MACCR_LM_Msk                              (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
+#define ETH_MACCR_LM                                  ETH_MACCR_LM_Msk         /* loopback mode */
+#define ETH_MACCR_ECRSFD_Pos                          (11U)
+#define ETH_MACCR_ECRSFD_Msk                          (0x1UL << ETH_MACCR_ECRSFD_Pos) /*!< 0x00000800 */
+#define ETH_MACCR_ECRSFD                              ETH_MACCR_ECRSFD_Msk     /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */
+#define ETH_MACCR_DO_Pos                              (10U)
+#define ETH_MACCR_DO_Msk                              (0x1UL << ETH_MACCR_DO_Pos) /*!< 0x00000400 */
+#define ETH_MACCR_DO                                  ETH_MACCR_DO_Msk         /* Disable Receive own  */
+#define ETH_MACCR_DCRS_Pos                            (9U)
+#define ETH_MACCR_DCRS_Msk                            (0x1UL << ETH_MACCR_DCRS_Pos) /*!< 0x00000200 */
+#define ETH_MACCR_DCRS                                ETH_MACCR_DCRS_Msk       /* Disable Carrier Sense During Transmission */
+#define ETH_MACCR_DR_Pos                              (8U)
+#define ETH_MACCR_DR_Msk                              (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */
+#define ETH_MACCR_DR                                  ETH_MACCR_DR_Msk         /* Disable Retry */
+#define ETH_MACCR_BL_Pos                              (5U)
+#define ETH_MACCR_BL_Msk                              (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
+#define ETH_MACCR_BL                                  ETH_MACCR_BL_Msk         /* Back-off limit mask */
+#define ETH_MACCR_BL_10                               (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */
+#define ETH_MACCR_BL_8                                (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */
+#define ETH_MACCR_BL_4                                (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */
+#define ETH_MACCR_BL_1                                (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
+#define ETH_MACCR_DC_Pos                              (4U)
+#define ETH_MACCR_DC_Msk                              (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
+#define ETH_MACCR_DC                                  ETH_MACCR_DC_Msk         /* Defferal check */
+#define ETH_MACCR_PRELEN_Pos                          (2U)
+#define ETH_MACCR_PRELEN_Msk                          (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */
+#define ETH_MACCR_PRELEN                              ETH_MACCR_PRELEN_Msk     /* Preamble Length for Transmit packets */
+#define ETH_MACCR_PRELEN_7                            (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */
+#define ETH_MACCR_PRELEN_5                            (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */
+#define ETH_MACCR_PRELEN_3                            (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */
+#define ETH_MACCR_TE_Pos                              (1U)
+#define ETH_MACCR_TE_Msk                              (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000002 */
+#define ETH_MACCR_TE                                  ETH_MACCR_TE_Msk         /* Transmitter enable */
+#define ETH_MACCR_RE_Pos                              (0U)
+#define ETH_MACCR_RE_Msk                              (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000001 */
+#define ETH_MACCR_RE                                  ETH_MACCR_RE_Msk         /* Receiver enable */
+
+/* Bit definition for Ethernet MAC Extended Configuration Register register */
+#define ETH_MACECR_EIPG_Pos                           (25U)
+#define ETH_MACECR_EIPG_Msk                           (0x1FUL << ETH_MACECR_EIPG_Pos) /*!< 0x3E000000 */
+#define ETH_MACECR_EIPG                               ETH_MACECR_EIPG_Msk      /* Extended Inter-Packet Gap */
+#define ETH_MACECR_EIPGEN_Pos                         (24U)
+#define ETH_MACECR_EIPGEN_Msk                         (0x1UL << ETH_MACECR_EIPGEN_Pos) /*!< 0x01000000 */
+#define ETH_MACECR_EIPGEN                             ETH_MACECR_EIPGEN_Msk    /* Extended Inter-Packet Gap Enable */
+#define ETH_MACECR_USP_Pos                            (18U)
+#define ETH_MACECR_USP_Msk                            (0x1UL << ETH_MACECR_USP_Pos) /*!< 0x00040000 */
+#define ETH_MACECR_USP                                ETH_MACECR_USP_Msk       /* Unicast Slow Protocol Packet Detect */
+#define ETH_MACECR_SPEN_Pos                           (17U)
+#define ETH_MACECR_SPEN_Msk                           (0x1UL << ETH_MACECR_SPEN_Pos) /*!< 0x00020000 */
+#define ETH_MACECR_SPEN                               ETH_MACECR_SPEN_Msk      /* Slow Protocol Detection Enable */
+#define ETH_MACECR_DCRCC_Pos                          (16U)
+#define ETH_MACECR_DCRCC_Msk                          (0x1UL << ETH_MACECR_DCRCC_Pos) /*!< 0x00010000 */
+#define ETH_MACECR_DCRCC                              ETH_MACECR_DCRCC_Msk     /* Disable CRC Checking for Received Packets */
+#define ETH_MACECR_GPSL_Pos                           (0U)
+#define ETH_MACECR_GPSL_Msk                           (0x3FFFUL << ETH_MACECR_GPSL_Pos) /*!< 0x00003FFF */
+#define ETH_MACECR_GPSL                               ETH_MACECR_GPSL_Msk      /* Giant Packet Size Limit */
+
+/* Bit definition for Ethernet MAC Packet Filter Register */
+#define ETH_MACPFR_RA_Pos                             (31U)
+#define ETH_MACPFR_RA_Msk                             (0x1UL << ETH_MACPFR_RA_Pos) /*!< 0x80000000 */
+#define ETH_MACPFR_RA                                 ETH_MACPFR_RA_Msk        /* Receive all */
+#define ETH_MACPFR_DNTU_Pos                           (21U)
+#define ETH_MACPFR_DNTU_Msk                           (0x1UL << ETH_MACPFR_DNTU_Pos) /*!< 0x00200000 */
+#define ETH_MACPFR_DNTU                               ETH_MACPFR_DNTU_Msk      /* Drop Non-TCP/UDP over IP Packets */
+#define ETH_MACPFR_IPFE_Pos                           (20U)
+#define ETH_MACPFR_IPFE_Msk                           (0x1UL << ETH_MACPFR_IPFE_Pos) /*!< 0x00100000 */
+#define ETH_MACPFR_IPFE                               ETH_MACPFR_IPFE_Msk      /* Layer 3 and Layer 4 Filter Enable */
+#define ETH_MACPFR_VTFE_Pos                           (16U)
+#define ETH_MACPFR_VTFE_Msk                           (0x1UL << ETH_MACPFR_VTFE_Pos) /*!< 0x00010000 */
+#define ETH_MACPFR_VTFE                               ETH_MACPFR_VTFE_Msk      /* VLAN Tag Filter Enable */
+#define ETH_MACPFR_HPF_Pos                            (10U)
+#define ETH_MACPFR_HPF_Msk                            (0x1UL << ETH_MACPFR_HPF_Pos) /*!< 0x00000400 */
+#define ETH_MACPFR_HPF                                ETH_MACPFR_HPF_Msk       /* Hash or perfect filter */
+#define ETH_MACPFR_SAF_Pos                            (9U)
+#define ETH_MACPFR_SAF_Msk                            (0x1UL << ETH_MACPFR_SAF_Pos) /*!< 0x00000200 */
+#define ETH_MACPFR_SAF                                ETH_MACPFR_SAF_Msk       /* Source address filter enable */
+#define ETH_MACPFR_SAIF_Pos                           (8U)
+#define ETH_MACPFR_SAIF_Msk                           (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */
+#define ETH_MACPFR_SAIF                               ETH_MACPFR_SAIF_Msk      /* SA inverse filtering */
+#define ETH_MACPFR_PCF_Pos                            (6U)
+#define ETH_MACPFR_PCF_Msk                            (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
+#define ETH_MACPFR_PCF                                ETH_MACPFR_PCF_Msk       /* Pass control frames: 4 cases */
+#define ETH_MACPFR_PCF_BLOCKALL                       ((uint32_t)0x00000000)   /* MAC filters all control frames from reaching the application */
+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos         (6U)
+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk         (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA             ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
+#define ETH_MACPFR_PCF_FORWARDALL_Pos                 (7U)
+#define ETH_MACPFR_PCF_FORWARDALL_Msk                 (0x1UL << ETH_MACPFR_PCF_FORWARDALL_Pos) /*!< 0x00000080 */
+#define ETH_MACPFR_PCF_FORWARDALL                     ETH_MACPFR_PCF_FORWARDALL_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos    (6U)
+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk    (0x3UL << ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos) /*!< 0x000000C0 */
+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER        ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk /* MAC forwards control frames that pass the Address Filter. */
+#define ETH_MACPFR_DBF_Pos                            (5U)
+#define ETH_MACPFR_DBF_Msk                            (0x1UL << ETH_MACPFR_DBF_Pos) /*!< 0x00000020 */
+#define ETH_MACPFR_DBF                                ETH_MACPFR_DBF_Msk       /* Disable Broadcast Packets */
+#define ETH_MACPFR_PM_Pos                             (4U)
+#define ETH_MACPFR_PM_Msk                             (0x1UL << ETH_MACPFR_PM_Pos) /*!< 0x00000010 */
+#define ETH_MACPFR_PM                                 ETH_MACPFR_PM_Msk        /* Pass all mutlicast */
+#define ETH_MACPFR_DAIF_Pos                           (3U)
+#define ETH_MACPFR_DAIF_Msk                           (0x1UL << ETH_MACPFR_DAIF_Pos) /*!< 0x00000008 */
+#define ETH_MACPFR_DAIF                               ETH_MACPFR_DAIF_Msk      /* DA Inverse filtering */
+#define ETH_MACPFR_HMC_Pos                            (2U)
+#define ETH_MACPFR_HMC_Msk                            (0x1UL << ETH_MACPFR_HMC_Pos) /*!< 0x00000004 */
+#define ETH_MACPFR_HMC                                ETH_MACPFR_HMC_Msk       /* Hash multicast */
+#define ETH_MACPFR_HUC_Pos                            (1U)
+#define ETH_MACPFR_HUC_Msk                            (0x1UL << ETH_MACPFR_HUC_Pos) /*!< 0x00000002 */
+#define ETH_MACPFR_HUC                                ETH_MACPFR_HUC_Msk       /* Hash unicast */
+#define ETH_MACPFR_PR_Pos                             (0U)
+#define ETH_MACPFR_PR_Msk                             (0x1UL << ETH_MACPFR_PR_Pos) /*!< 0x00000001 */
+#define ETH_MACPFR_PR                                 ETH_MACPFR_PR_Msk        /* Promiscuous mode */
+
+/* Bit definition for Ethernet MAC Watchdog Timeout Register */
+#define ETH_MACWTR_PWE_Pos                            (8U)
+#define ETH_MACWTR_PWE_Msk                            (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */
+#define ETH_MACWTR_PWE                                ETH_MACWTR_PWE_Msk       /* Programmable Watchdog Enable */
+#define ETH_MACWTR_WTO_Pos                            (0U)
+#define ETH_MACWTR_WTO_Msk                            (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
+#define ETH_MACWTR_WTO                                ETH_MACWTR_WTO_Msk       /* Watchdog Timeout */
+#define ETH_MACWTR_WTO_2KB                            ((uint32_t)0x00000000)   /* Maximum received packet length 2KB*/
+#define ETH_MACWTR_WTO_3KB                            ((uint32_t)0x00000001)   /* Maximum received packet length 3KB */
+#define ETH_MACWTR_WTO_4KB                            ((uint32_t)0x00000002)   /* Maximum received packet length 4KB */
+#define ETH_MACWTR_WTO_5KB                            ((uint32_t)0x00000003)   /* Maximum received packet length 5KB */
+#define ETH_MACWTR_WTO_6KB                            ((uint32_t)0x00000004)   /* Maximum received packet length 6KB */
+#define ETH_MACWTR_WTO_7KB                            ((uint32_t)0x00000005)   /* Maximum received packet length 7KB */
+#define ETH_MACWTR_WTO_8KB                            ((uint32_t)0x00000006)   /* Maximum received packet length 8KB */
+#define ETH_MACWTR_WTO_9KB                            ((uint32_t)0x00000007)   /* Maximum received packet length 9KB */
+#define ETH_MACWTR_WTO_10KB                           ((uint32_t)0x00000008)   /* Maximum received packet length 10KB */
+#define ETH_MACWTR_WTO_11KB                           ((uint32_t)0x00000009)   /* Maximum received packet length 11KB */
+#define ETH_MACWTR_WTO_12KB                           ((uint32_t)0x0000000A)   /* Maximum received packet length 12KB */
+#define ETH_MACWTR_WTO_13KB                           ((uint32_t)0x0000000B)   /* Maximum received packet length 13KB */
+#define ETH_MACWTR_WTO_14KB                           ((uint32_t)0x0000000C)   /* Maximum received packet length 14KB */
+#define ETH_MACWTR_WTO_15KB                           ((uint32_t)0x0000000D)   /* Maximum received packet length 15KB */
+#define ETH_MACWTR_WTO_16KB                           ((uint32_t)0x0000000E)   /* Maximum received packet length 16KB */
+
+/* Bit definition for Ethernet MAC Hash Table High Register */
+#define ETH_MACHTHR_HTH_Pos                           (0U)
+#define ETH_MACHTHR_HTH_Msk                           (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACHTHR_HTH                               ETH_MACHTHR_HTH_Msk      /* Hash table high */
+
+/* Bit definition for Ethernet MAC Hash Table Low Register */
+#define ETH_MACHTLR_HTL_Pos                           (0U)
+#define ETH_MACHTLR_HTL_Msk                           (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACHTLR_HTL                               ETH_MACHTLR_HTL_Msk      /* Hash table low */
+
+/* Bit definition for Ethernet MAC VLAN Tag Register */
+#define ETH_MACVTR_EIVLRXS_Pos                        (31U)
+#define ETH_MACVTR_EIVLRXS_Msk                        (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */
+#define ETH_MACVTR_EIVLRXS                            ETH_MACVTR_EIVLRXS_Msk   /* Enable Inner VLAN Tag in Rx Status */
+#define ETH_MACVTR_EIVLS_Pos                          (28U)
+#define ETH_MACVTR_EIVLS_Msk                          (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
+#define ETH_MACVTR_EIVLS                              ETH_MACVTR_EIVLS_Msk     /* Enable Inner VLAN Tag Stripping on Receive */
+#define ETH_MACVTR_EIVLS_DONOTSTRIP                   ((uint32_t)0x00000000)   /* Do not strip */
+#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos              (28U)
+#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk              (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
+#define ETH_MACVTR_EIVLS_STRIPIFPASS                  ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
+#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos             (29U)
+#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk             (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */
+#define ETH_MACVTR_EIVLS_STRIPIFFAILS                 ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
+#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos              (28U)
+#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk              (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */
+#define ETH_MACVTR_EIVLS_ALWAYSSTRIP                  ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */
+#define ETH_MACVTR_ERIVLT_Pos                         (27U)
+#define ETH_MACVTR_ERIVLT_Msk                         (0x1UL << ETH_MACVTR_ERIVLT_Pos) /*!< 0x08000000 */
+#define ETH_MACVTR_ERIVLT                             ETH_MACVTR_ERIVLT_Msk    /* Enable Inner VLAN Tag */
+#define ETH_MACVTR_EDVLP_Pos                          (26U)
+#define ETH_MACVTR_EDVLP_Msk                          (0x1UL << ETH_MACVTR_EDVLP_Pos) /*!< 0x04000000 */
+#define ETH_MACVTR_EDVLP                              ETH_MACVTR_EDVLP_Msk     /* Enable Double VLAN Processing */
+#define ETH_MACVTR_VTHM_Pos                           (25U)
+#define ETH_MACVTR_VTHM_Msk                           (0x1UL << ETH_MACVTR_VTHM_Pos) /*!< 0x02000000 */
+#define ETH_MACVTR_VTHM                               ETH_MACVTR_VTHM_Msk      /* VLAN Tag Hash Table Match Enable */
+#define ETH_MACVTR_EVLRXS_Pos                         (24U)
+#define ETH_MACVTR_EVLRXS_Msk                         (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */
+#define ETH_MACVTR_EVLRXS                             ETH_MACVTR_EVLRXS_Msk    /* Enable VLAN Tag in Rx status */
+#define ETH_MACVTR_EVLS_Pos                           (21U)
+#define ETH_MACVTR_EVLS_Msk                           (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
+#define ETH_MACVTR_EVLS                               ETH_MACVTR_EVLS_Msk      /* Enable VLAN Tag Stripping on Receive */
+#define ETH_MACVTR_EVLS_DONOTSTRIP                    ((uint32_t)0x00000000)   /* Do not strip */
+#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos               (21U)
+#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk               (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
+#define ETH_MACVTR_EVLS_STRIPIFPASS                   ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
+#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos              (22U)
+#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk              (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */
+#define ETH_MACVTR_EVLS_STRIPIFFAILS                  ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
+#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos               (21U)
+#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk               (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */
+#define ETH_MACVTR_EVLS_ALWAYSSTRIP                   ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */
+#define ETH_MACVTR_DOVLTC_Pos                         (20U)
+#define ETH_MACVTR_DOVLTC_Msk                         (0x1UL << ETH_MACVTR_DOVLTC_Pos) /*!< 0x00100000 */
+#define ETH_MACVTR_DOVLTC                             ETH_MACVTR_DOVLTC_Msk    /* Disable VLAN Type Check */
+#define ETH_MACVTR_ERSVLM_Pos                         (19U)
+#define ETH_MACVTR_ERSVLM_Msk                         (0x1UL << ETH_MACVTR_ERSVLM_Pos) /*!< 0x00080000 */
+#define ETH_MACVTR_ERSVLM                             ETH_MACVTR_ERSVLM_Msk    /* Enable Receive S-VLAN Match */
+#define ETH_MACVTR_ESVL_Pos                           (18U)
+#define ETH_MACVTR_ESVL_Msk                           (0x1UL << ETH_MACVTR_ESVL_Pos) /*!< 0x00040000 */
+#define ETH_MACVTR_ESVL                               ETH_MACVTR_ESVL_Msk      /* Enable S-VLAN */
+#define ETH_MACVTR_VTIM_Pos                           (17U)
+#define ETH_MACVTR_VTIM_Msk                           (0x1UL << ETH_MACVTR_VTIM_Pos) /*!< 0x00020000 */
+#define ETH_MACVTR_VTIM                               ETH_MACVTR_VTIM_Msk      /* VLAN Tag Inverse Match Enable */
+#define ETH_MACVTR_ETV_Pos                            (16U)
+#define ETH_MACVTR_ETV_Msk                            (0x1UL << ETH_MACVTR_ETV_Pos) /*!< 0x00010000 */
+#define ETH_MACVTR_ETV                                ETH_MACVTR_ETV_Msk       /* Enable 12-Bit VLAN Tag Comparison */
+#define ETH_MACVTR_VL_Pos                             (0U)
+#define ETH_MACVTR_VL_Msk                             (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */
+#define ETH_MACVTR_VL                                 ETH_MACVTR_VL_Msk        /* VLAN Tag Identifier for Receive Packets */
+#define ETH_MACVTR_VL_UP_Pos                          (13U)
+#define ETH_MACVTR_VL_UP_Msk                          (0x7UL << ETH_MACVTR_VL_UP_Pos) /*!< 0x0000E000 */
+#define ETH_MACVTR_VL_UP                              ETH_MACVTR_VL_UP_Msk     /* User Priority */
+#define ETH_MACVTR_VL_CFIDEI_Pos                      (12U)
+#define ETH_MACVTR_VL_CFIDEI_Msk                      (0x1UL << ETH_MACVTR_VL_CFIDEI_Pos) /*!< 0x00001000 */
+#define ETH_MACVTR_VL_CFIDEI                          ETH_MACVTR_VL_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
+#define ETH_MACVTR_VL_VID_Pos                         (0U)
+#define ETH_MACVTR_VL_VID_Msk                         (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */
+#define ETH_MACVTR_VL_VID                             ETH_MACVTR_VL_VID_Msk    /* VLAN Identifier field of VLAN tag */
+
+/* Bit definition for Ethernet MAC VLAN Hash Table Register */
+#define ETH_MACVHTR_VLHT_Pos                          (0U)
+#define ETH_MACVHTR_VLHT_Msk                          (0xFFFFUL << ETH_MACVHTR_VLHT_Pos) /*!< 0x0000FFFF */
+#define ETH_MACVHTR_VLHT                              ETH_MACVHTR_VLHT_Msk     /* VLAN Hash Table */
+
+/* Bit definition for Ethernet MAC VLAN Incl Register */
+#define ETH_MACVIR_VLTI_Pos                           (20U)
+#define ETH_MACVIR_VLTI_Msk                           (0x1UL << ETH_MACVIR_VLTI_Pos) /*!< 0x00100000 */
+#define ETH_MACVIR_VLTI                               ETH_MACVIR_VLTI_Msk      /* VLAN Tag Input */
+#define ETH_MACVIR_CSVL_Pos                           (19U)
+#define ETH_MACVIR_CSVL_Msk                           (0x1UL << ETH_MACVIR_CSVL_Pos) /*!< 0x00080000 */
+#define ETH_MACVIR_CSVL                               ETH_MACVIR_CSVL_Msk      /* C-VLAN or S-VLAN */
+#define ETH_MACVIR_VLP_Pos                            (18U)
+#define ETH_MACVIR_VLP_Msk                            (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */
+#define ETH_MACVIR_VLP                                ETH_MACVIR_VLP_Msk       /* VLAN Priority Control */
+#define ETH_MACVIR_VLC_Pos                            (16U)
+#define ETH_MACVIR_VLC_Msk                            (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
+#define ETH_MACVIR_VLC                                ETH_MACVIR_VLC_Msk       /* VLAN Tag Control in Transmit Packets */
+#define ETH_MACVIR_VLC_NOVLANTAG                      ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos              (16U)
+#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
+#define ETH_MACVIR_VLC_VLANTAGDELETE                  ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
+#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos              (17U)
+#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */
+#define ETH_MACVIR_VLC_VLANTAGINSERT                  ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
+#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos             (16U)
+#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk             (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */
+#define ETH_MACVIR_VLC_VLANTAGREPLACE                 ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
+#define ETH_MACVIR_VLT_Pos                            (0U)
+#define ETH_MACVIR_VLT_Msk                            (0xFFFFUL << ETH_MACVIR_VLT_Pos) /*!< 0x0000FFFF */
+#define ETH_MACVIR_VLT                                ETH_MACVIR_VLT_Msk       /* VLAN Tag for Transmit Packets */
+#define ETH_MACVIR_VLT_UP_Pos                         (13U)
+#define ETH_MACVIR_VLT_UP_Msk                         (0x7UL << ETH_MACVIR_VLT_UP_Pos) /*!< 0x0000E000 */
+#define ETH_MACVIR_VLT_UP                             ETH_MACVIR_VLT_UP_Msk    /* User Priority */
+#define ETH_MACVIR_VLT_CFIDEI_Pos                     (12U)
+#define ETH_MACVIR_VLT_CFIDEI_Msk                     (0x1UL << ETH_MACVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */
+#define ETH_MACVIR_VLT_CFIDEI                         ETH_MACVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
+#define ETH_MACVIR_VLT_VID_Pos                        (0U)
+#define ETH_MACVIR_VLT_VID_Msk                        (0xFFFUL << ETH_MACVIR_VLT_VID_Pos) /*!< 0x00000FFF */
+#define ETH_MACVIR_VLT_VID                            ETH_MACVIR_VLT_VID_Msk   /* VLAN Identifier field of VLAN tag */
+
+/* Bit definition for Ethernet MAC Inner_VLAN Incl Register */
+#define ETH_MACIVIR_VLTI_Pos                          (20U)
+#define ETH_MACIVIR_VLTI_Msk                          (0x1UL << ETH_MACIVIR_VLTI_Pos) /*!< 0x00100000 */
+#define ETH_MACIVIR_VLTI                              ETH_MACIVIR_VLTI_Msk     /* VLAN Tag Input */
+#define ETH_MACIVIR_CSVL_Pos                          (19U)
+#define ETH_MACIVIR_CSVL_Msk                          (0x1UL << ETH_MACIVIR_CSVL_Pos) /*!< 0x00080000 */
+#define ETH_MACIVIR_CSVL                              ETH_MACIVIR_CSVL_Msk     /* C-VLAN or S-VLAN */
+#define ETH_MACIVIR_VLP_Pos                           (18U)
+#define ETH_MACIVIR_VLP_Msk                           (0x1UL << ETH_MACIVIR_VLP_Pos) /*!< 0x00040000 */
+#define ETH_MACIVIR_VLP                               ETH_MACIVIR_VLP_Msk      /* VLAN Priority Control */
+#define ETH_MACIVIR_VLC_Pos                           (16U)
+#define ETH_MACIVIR_VLC_Msk                           (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
+#define ETH_MACIVIR_VLC                               ETH_MACIVIR_VLC_Msk      /* VLAN Tag Control in Transmit Packets */
+#define ETH_MACIVIR_VLC_NOVLANTAG                     ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos             (16U)
+#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
+#define ETH_MACIVIR_VLC_VLANTAGDELETE                 ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
+#define ETH_MACIVIR_VLC_VLANTAGINSERT_Pos             (17U)
+#define ETH_MACIVIR_VLC_VLANTAGINSERT_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */
+#define ETH_MACIVIR_VLC_VLANTAGINSERT                 ETH_MACIVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
+#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos            (16U)
+#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk            (0x3UL << ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */
+#define ETH_MACIVIR_VLC_VLANTAGREPLACE                ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
+#define ETH_MACIVIR_VLT_Pos                           (0U)
+#define ETH_MACIVIR_VLT_Msk                           (0xFFFFUL << ETH_MACIVIR_VLT_Pos) /*!< 0x0000FFFF */
+#define ETH_MACIVIR_VLT                               ETH_MACIVIR_VLT_Msk      /* VLAN Tag for Transmit Packets */
+#define ETH_MACIVIR_VLT_UP_Pos                        (13U)
+#define ETH_MACIVIR_VLT_UP_Msk                        (0x7UL << ETH_MACIVIR_VLT_UP_Pos) /*!< 0x0000E000 */
+#define ETH_MACIVIR_VLT_UP                            ETH_MACIVIR_VLT_UP_Msk   /* User Priority */
+#define ETH_MACIVIR_VLT_CFIDEI_Pos                    (12U)
+#define ETH_MACIVIR_VLT_CFIDEI_Msk                    (0x1UL << ETH_MACIVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */
+#define ETH_MACIVIR_VLT_CFIDEI                        ETH_MACIVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
+#define ETH_MACIVIR_VLT_VID_Pos                       (0U)
+#define ETH_MACIVIR_VLT_VID_Msk                       (0xFFFUL << ETH_MACIVIR_VLT_VID_Pos) /*!< 0x00000FFF */
+#define ETH_MACIVIR_VLT_VID                           ETH_MACIVIR_VLT_VID_Msk  /* VLAN Identifier field of VLAN tag */
+
+/* Bit definition for Ethernet MAC Tx Flow Ctrl Register */
+#define ETH_MACTFCR_PT_Pos                            (16U)
+#define ETH_MACTFCR_PT_Msk                            (0xFFFFUL << ETH_MACTFCR_PT_Pos) /*!< 0xFFFF0000 */
+#define ETH_MACTFCR_PT                                ETH_MACTFCR_PT_Msk       /* Pause Time */
+#define ETH_MACTFCR_DZPQ_Pos                          (7U)
+#define ETH_MACTFCR_DZPQ_Msk                          (0x1UL << ETH_MACTFCR_DZPQ_Pos) /*!< 0x00000080 */
+#define ETH_MACTFCR_DZPQ                              ETH_MACTFCR_DZPQ_Msk     /* Disable Zero-Quanta Pause */
+#define ETH_MACTFCR_PLT_Pos                           (4U)
+#define ETH_MACTFCR_PLT_Msk                           (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */
+#define ETH_MACTFCR_PLT                               ETH_MACTFCR_PLT_Msk      /* Pause Low Threshold */
+#define ETH_MACTFCR_PLT_MINUS4                        ((uint32_t)0x00000000)   /* Pause time minus 4 slot times */
+#define ETH_MACTFCR_PLT_MINUS28_Pos                   (4U)
+#define ETH_MACTFCR_PLT_MINUS28_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
+#define ETH_MACTFCR_PLT_MINUS28                       ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
+#define ETH_MACTFCR_PLT_MINUS36_Pos                   (5U)
+#define ETH_MACTFCR_PLT_MINUS36_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS36_Pos) /*!< 0x00000020 */
+#define ETH_MACTFCR_PLT_MINUS36                       ETH_MACTFCR_PLT_MINUS36_Msk /* Pause time minus 36 slot times */
+#define ETH_MACTFCR_PLT_MINUS144_Pos                  (4U)
+#define ETH_MACTFCR_PLT_MINUS144_Msk                  (0x3UL << ETH_MACTFCR_PLT_MINUS144_Pos) /*!< 0x00000030 */
+#define ETH_MACTFCR_PLT_MINUS144                      ETH_MACTFCR_PLT_MINUS144_Msk /* Pause time minus 144 slot times */
+#define ETH_MACTFCR_PLT_MINUS256_Pos                  (6U)
+#define ETH_MACTFCR_PLT_MINUS256_Msk                  (0x1UL << ETH_MACTFCR_PLT_MINUS256_Pos) /*!< 0x00000040 */
+#define ETH_MACTFCR_PLT_MINUS256                      ETH_MACTFCR_PLT_MINUS256_Msk /* Pause time minus 256 slot times */
+#define ETH_MACTFCR_PLT_MINUS512_Pos                  (4U)
+#define ETH_MACTFCR_PLT_MINUS512_Msk                  (0x5UL << ETH_MACTFCR_PLT_MINUS512_Pos) /*!< 0x00000050 */
+#define ETH_MACTFCR_PLT_MINUS512                      ETH_MACTFCR_PLT_MINUS512_Msk /* Pause time minus 512 slot times */
+#define ETH_MACTFCR_TFE_Pos                           (1U)
+#define ETH_MACTFCR_TFE_Msk                           (0x1UL << ETH_MACTFCR_TFE_Pos) /*!< 0x00000002 */
+#define ETH_MACTFCR_TFE                               ETH_MACTFCR_TFE_Msk      /* Transmit Flow Control Enable */
+#define ETH_MACTFCR_FCB_Pos                           (0U)
+#define ETH_MACTFCR_FCB_Msk                           (0x1UL << ETH_MACTFCR_FCB_Pos) /*!< 0x00000001 */
+#define ETH_MACTFCR_FCB                               ETH_MACTFCR_FCB_Msk      /* Flow Control Busy or Backpressure Activate */
+
+/* Bit definition for Ethernet MAC Rx Flow Ctrl Register */
+#define ETH_MACRFCR_UP_Pos                            (1U)
+#define ETH_MACRFCR_UP_Msk                            (0x1UL << ETH_MACRFCR_UP_Pos) /*!< 0x00000002 */
+#define ETH_MACRFCR_UP                                ETH_MACRFCR_UP_Msk       /* Unicast Pause Packet Detect */
+#define ETH_MACRFCR_RFE_Pos                           (0U)
+#define ETH_MACRFCR_RFE_Msk                           (0x1UL << ETH_MACRFCR_RFE_Pos) /*!< 0x00000001 */
+#define ETH_MACRFCR_RFE                               ETH_MACRFCR_RFE_Msk      /* Receive Flow Control Enable */
+
+/* Bit definition for Ethernet MAC Interrupt Status Register */
+#define ETH_MACISR_RXSTSIS_Pos                        (14U)
+#define ETH_MACISR_RXSTSIS_Msk                        (0x1UL << ETH_MACISR_RXSTSIS_Pos) /*!< 0x00004000 */
+#define ETH_MACISR_RXSTSIS                            ETH_MACISR_RXSTSIS_Msk   /* Receive Status Interrupt */
+#define ETH_MACISR_TXSTSIS_Pos                        (13U)
+#define ETH_MACISR_TXSTSIS_Msk                        (0x1UL << ETH_MACISR_TXSTSIS_Pos) /*!< 0x00002000 */
+#define ETH_MACISR_TXSTSIS                            ETH_MACISR_TXSTSIS_Msk   /* Transmit Status Interrupt */
+#define ETH_MACISR_TSIS_Pos                           (12U)
+#define ETH_MACISR_TSIS_Msk                           (0x1UL << ETH_MACISR_TSIS_Pos) /*!< 0x00001000 */
+#define ETH_MACISR_TSIS                               ETH_MACISR_TSIS_Msk      /* Timestamp Interrupt Status */
+#define ETH_MACISR_MMCTXIS_Pos                        (10U)
+#define ETH_MACISR_MMCTXIS_Msk                        (0x1UL << ETH_MACISR_MMCTXIS_Pos) /*!< 0x00000400 */
+#define ETH_MACISR_MMCTXIS                            ETH_MACISR_MMCTXIS_Msk   /* MMC Transmit Interrupt Status */
+#define ETH_MACISR_MMCRXIS_Pos                        (9U)
+#define ETH_MACISR_MMCRXIS_Msk                        (0x1UL << ETH_MACISR_MMCRXIS_Pos) /*!< 0x00000200 */
+#define ETH_MACISR_MMCRXIS                            ETH_MACISR_MMCRXIS_Msk   /* MMC Receive Interrupt Status */
+#define ETH_MACISR_MMCIS_Pos                          (8U)
+#define ETH_MACISR_MMCIS_Msk                          (0x1UL << ETH_MACISR_MMCIS_Pos) /*!< 0x00000100 */
+#define ETH_MACISR_MMCIS                              ETH_MACISR_MMCIS_Msk     /* MMC Interrupt Status */
+#define ETH_MACISR_LPIIS_Pos                          (5U)
+#define ETH_MACISR_LPIIS_Msk                          (0x1UL << ETH_MACISR_LPIIS_Pos) /*!< 0x00000020 */
+#define ETH_MACISR_LPIIS                              ETH_MACISR_LPIIS_Msk     /* LPI Interrupt Status */
+#define ETH_MACISR_PMTIS_Pos                          (4U)
+#define ETH_MACISR_PMTIS_Msk                          (0x1UL << ETH_MACISR_PMTIS_Pos) /*!< 0x00000010 */
+#define ETH_MACISR_PMTIS                              ETH_MACISR_PMTIS_Msk     /* PMT Interrupt Status */
+#define ETH_MACISR_PHYIS_Pos                          (3U)
+#define ETH_MACISR_PHYIS_Msk                          (0x1UL << ETH_MACISR_PHYIS_Pos) /*!< 0x00000008 */
+#define ETH_MACISR_PHYIS                              ETH_MACISR_PHYIS_Msk     /* PHY Interrupt */
+
+/* Bit definition for Ethernet MAC Interrupt Enable Register */
+#define ETH_MACIER_RXSTSIE_Pos                        (14U)
+#define ETH_MACIER_RXSTSIE_Msk                        (0x1UL << ETH_MACIER_RXSTSIE_Pos) /*!< 0x00004000 */
+#define ETH_MACIER_RXSTSIE                            ETH_MACIER_RXSTSIE_Msk   /* Receive Status Interrupt Enable */
+#define ETH_MACIER_TXSTSIE_Pos                        (13U)
+#define ETH_MACIER_TXSTSIE_Msk                        (0x1UL << ETH_MACIER_TXSTSIE_Pos) /*!< 0x00002000 */
+#define ETH_MACIER_TXSTSIE                            ETH_MACIER_TXSTSIE_Msk   /* Transmit Status Interrupt Enable */
+#define ETH_MACIER_TSIE_Pos                           (12U)
+#define ETH_MACIER_TSIE_Msk                           (0x1UL << ETH_MACIER_TSIE_Pos) /*!< 0x00001000 */
+#define ETH_MACIER_TSIE                               ETH_MACIER_TSIE_Msk      /* Timestamp Interrupt Enable */
+#define ETH_MACIER_LPIIE_Pos                          (5U)
+#define ETH_MACIER_LPIIE_Msk                          (0x1UL << ETH_MACIER_LPIIE_Pos) /*!< 0x00000020 */
+#define ETH_MACIER_LPIIE                              ETH_MACIER_LPIIE_Msk     /* LPI Interrupt Enable */
+#define ETH_MACIER_PMTIE_Pos                          (4U)
+#define ETH_MACIER_PMTIE_Msk                          (0x1UL << ETH_MACIER_PMTIE_Pos) /*!< 0x00000010 */
+#define ETH_MACIER_PMTIE                              ETH_MACIER_PMTIE_Msk     /* PMT Interrupt Enable */
+#define ETH_MACIER_PHYIE_Pos                          (3U)
+#define ETH_MACIER_PHYIE_Msk                          (0x1UL << ETH_MACIER_PHYIE_Pos) /*!< 0x00000008 */
+#define ETH_MACIER_PHYIE                              ETH_MACIER_PHYIE_Msk     /* PHY Interrupt Enable */
+
+/* Bit definition for Ethernet MAC Rx Tx Status Register */
+#define ETH_MACRXTXSR_RWT_Pos                         (8U)
+#define ETH_MACRXTXSR_RWT_Msk                         (0x1UL << ETH_MACRXTXSR_RWT_Pos) /*!< 0x00000100 */
+#define ETH_MACRXTXSR_RWT                             ETH_MACRXTXSR_RWT_Msk    /* Receive Watchdog Timeout */
+#define ETH_MACRXTXSR_EXCOL_Pos                       (5U)
+#define ETH_MACRXTXSR_EXCOL_Msk                       (0x1UL << ETH_MACRXTXSR_EXCOL_Pos) /*!< 0x00000020 */
+#define ETH_MACRXTXSR_EXCOL                           ETH_MACRXTXSR_EXCOL_Msk  /* Excessive Collisions */
+#define ETH_MACRXTXSR_LCOL_Pos                        (4U)
+#define ETH_MACRXTXSR_LCOL_Msk                        (0x1UL << ETH_MACRXTXSR_LCOL_Pos) /*!< 0x00000010 */
+#define ETH_MACRXTXSR_LCOL                            ETH_MACRXTXSR_LCOL_Msk   /* Late Collision */
+#define ETH_MACRXTXSR_EXDEF_Pos                       (3U)
+#define ETH_MACRXTXSR_EXDEF_Msk                       (0x1UL << ETH_MACRXTXSR_EXDEF_Pos) /*!< 0x00000008 */
+#define ETH_MACRXTXSR_EXDEF                           ETH_MACRXTXSR_EXDEF_Msk  /* Excessive Deferral */
+#define ETH_MACRXTXSR_LCARR_Pos                       (2U)
+#define ETH_MACRXTXSR_LCARR_Msk                       (0x1UL << ETH_MACRXTXSR_LCARR_Pos) /*!< 0x00000004 */
+#define ETH_MACRXTXSR_LCARR                           ETH_MACRXTXSR_LCARR_Msk  /* Loss of Carrier */
+#define ETH_MACRXTXSR_NCARR_Pos                       (1U)
+#define ETH_MACRXTXSR_NCARR_Msk                       (0x1UL << ETH_MACRXTXSR_NCARR_Pos) /*!< 0x00000002 */
+#define ETH_MACRXTXSR_NCARR                           ETH_MACRXTXSR_NCARR_Msk  /* No Carrier */
+#define ETH_MACRXTXSR_TJT_Pos                         (0U)
+#define ETH_MACRXTXSR_TJT_Msk                         (0x1UL << ETH_MACRXTXSR_TJT_Pos) /*!< 0x00000001 */
+#define ETH_MACRXTXSR_TJT                             ETH_MACRXTXSR_TJT_Msk    /* Transmit Jabber Timeout */
+
+/* Bit definition for Ethernet MAC PMT Control Status Register */
+#define ETH_MACPCSR_RWKFILTRST_Pos                    (31U)
+#define ETH_MACPCSR_RWKFILTRST_Msk                    (0x1UL << ETH_MACPCSR_RWKFILTRST_Pos) /*!< 0x80000000 */
+#define ETH_MACPCSR_RWKFILTRST                        ETH_MACPCSR_RWKFILTRST_Msk /* Remote Wake-Up Packet Filter Register Pointer Reset */
+#define ETH_MACPCSR_RWKPTR_Pos                        (24U)
+#define ETH_MACPCSR_RWKPTR_Msk                        (0x1FUL << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x1F000000 */
+#define ETH_MACPCSR_RWKPTR                            ETH_MACPCSR_RWKPTR_Msk   /* Remote Wake-up FIFO Pointer */
+#define ETH_MACPCSR_RWKPFE_Pos                        (10U)
+#define ETH_MACPCSR_RWKPFE_Msk                        (0x1UL << ETH_MACPCSR_RWKPFE_Pos) /*!< 0x00000400 */
+#define ETH_MACPCSR_RWKPFE                            ETH_MACPCSR_RWKPFE_Msk   /* Remote Wake-up Packet Forwarding Enable */
+#define ETH_MACPCSR_GLBLUCAST_Pos                     (9U)
+#define ETH_MACPCSR_GLBLUCAST_Msk                     (0x1UL << ETH_MACPCSR_GLBLUCAST_Pos) /*!< 0x00000200 */
+#define ETH_MACPCSR_GLBLUCAST                         ETH_MACPCSR_GLBLUCAST_Msk /* Global Unicast */
+#define ETH_MACPCSR_RWKPRCVD_Pos                      (6U)
+#define ETH_MACPCSR_RWKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_RWKPRCVD_Pos) /*!< 0x00000040 */
+#define ETH_MACPCSR_RWKPRCVD                          ETH_MACPCSR_RWKPRCVD_Msk /* Remote Wake-Up Packet Received */
+#define ETH_MACPCSR_MGKPRCVD_Pos                      (5U)
+#define ETH_MACPCSR_MGKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_MGKPRCVD_Pos) /*!< 0x00000020 */
+#define ETH_MACPCSR_MGKPRCVD                          ETH_MACPCSR_MGKPRCVD_Msk /* Magic Packet Received */
+#define ETH_MACPCSR_RWKPKTEN_Pos                      (2U)
+#define ETH_MACPCSR_RWKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_RWKPKTEN_Pos) /*!< 0x00000004 */
+#define ETH_MACPCSR_RWKPKTEN                          ETH_MACPCSR_RWKPKTEN_Msk /* Remote Wake-Up Packet Enable */
+#define ETH_MACPCSR_MGKPKTEN_Pos                      (1U)
+#define ETH_MACPCSR_MGKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_MGKPKTEN_Pos) /*!< 0x00000002 */
+#define ETH_MACPCSR_MGKPKTEN                          ETH_MACPCSR_MGKPKTEN_Msk /* Magic Packet Enable */
+#define ETH_MACPCSR_PWRDWN_Pos                        (0U)
+#define ETH_MACPCSR_PWRDWN_Msk                        (0x1UL << ETH_MACPCSR_PWRDWN_Pos) /*!< 0x00000001 */
+#define ETH_MACPCSR_PWRDWN                            ETH_MACPCSR_PWRDWN_Msk   /* Power Down */
+
+/* Bit definition for Ethernet MAC Remote Wake-Up Packet Filter Register */
+#define ETH_MACRWUPFR_D_Pos                           (0U)
+#define ETH_MACRWUPFR_D_Msk                           (0xFFFFFFFFUL << ETH_MACRWUPFR_D_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACRWUPFR_D                               ETH_MACRWUPFR_D_Msk      /* Wake-up Packet filter register data */
+
+/* Bit definition for Ethernet MAC LPI Control Status Register */
+#define ETH_MACLCSR_LPITCSE_Pos                       (21U)
+#define ETH_MACLCSR_LPITCSE_Msk                       (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */
+#define ETH_MACLCSR_LPITCSE                           ETH_MACLCSR_LPITCSE_Msk  /* LPI Tx Clock Stop Enable */
+#define ETH_MACLCSR_LPITE_Pos                         (20U)
+#define ETH_MACLCSR_LPITE_Msk                         (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */
+#define ETH_MACLCSR_LPITE                             ETH_MACLCSR_LPITE_Msk    /* LPI Timer Enable */
+#define ETH_MACLCSR_LPITXA_Pos                        (19U)
+#define ETH_MACLCSR_LPITXA_Msk                        (0x1UL << ETH_MACLCSR_LPITXA_Pos) /*!< 0x00080000 */
+#define ETH_MACLCSR_LPITXA                            ETH_MACLCSR_LPITXA_Msk   /* LPI Tx Automate */
+#define ETH_MACLCSR_PLS_Pos                           (17U)
+#define ETH_MACLCSR_PLS_Msk                           (0x1UL << ETH_MACLCSR_PLS_Pos) /*!< 0x00020000 */
+#define ETH_MACLCSR_PLS                               ETH_MACLCSR_PLS_Msk      /* PHY Link Status */
+#define ETH_MACLCSR_LPIEN_Pos                         (16U)
+#define ETH_MACLCSR_LPIEN_Msk                         (0x1UL << ETH_MACLCSR_LPIEN_Pos) /*!< 0x00010000 */
+#define ETH_MACLCSR_LPIEN                             ETH_MACLCSR_LPIEN_Msk    /* LPI Enable */
+#define ETH_MACLCSR_RLPIST_Pos                        (9U)
+#define ETH_MACLCSR_RLPIST_Msk                        (0x1UL << ETH_MACLCSR_RLPIST_Pos) /*!< 0x00000200 */
+#define ETH_MACLCSR_RLPIST                            ETH_MACLCSR_RLPIST_Msk   /* Receive LPI State */
+#define ETH_MACLCSR_TLPIST_Pos                        (8U)
+#define ETH_MACLCSR_TLPIST_Msk                        (0x1UL << ETH_MACLCSR_TLPIST_Pos) /*!< 0x00000100 */
+#define ETH_MACLCSR_TLPIST                            ETH_MACLCSR_TLPIST_Msk   /* Transmit LPI State */
+#define ETH_MACLCSR_RLPIEX_Pos                        (3U)
+#define ETH_MACLCSR_RLPIEX_Msk                        (0x1UL << ETH_MACLCSR_RLPIEX_Pos) /*!< 0x00000008 */
+#define ETH_MACLCSR_RLPIEX                            ETH_MACLCSR_RLPIEX_Msk   /* Receive LPI Exit */
+#define ETH_MACLCSR_RLPIEN_Pos                        (2U)
+#define ETH_MACLCSR_RLPIEN_Msk                        (0x1UL << ETH_MACLCSR_RLPIEN_Pos) /*!< 0x00000004 */
+#define ETH_MACLCSR_RLPIEN                            ETH_MACLCSR_RLPIEN_Msk   /* Receive LPI Entry */
+#define ETH_MACLCSR_TLPIEX_Pos                        (1U)
+#define ETH_MACLCSR_TLPIEX_Msk                        (0x1UL << ETH_MACLCSR_TLPIEX_Pos) /*!< 0x00000002 */
+#define ETH_MACLCSR_TLPIEX                            ETH_MACLCSR_TLPIEX_Msk   /* Transmit LPI Exit */
+#define ETH_MACLCSR_TLPIEN_Pos                        (0U)
+#define ETH_MACLCSR_TLPIEN_Msk                        (0x1UL << ETH_MACLCSR_TLPIEN_Pos) /*!< 0x00000001 */
+#define ETH_MACLCSR_TLPIEN                            ETH_MACLCSR_TLPIEN_Msk   /* Transmit LPI Entry */
+
+/* Bit definition for Ethernet MAC LPI Timers Control Register */
+#define ETH_MACLTCR_LST_Pos                           (16U)
+#define ETH_MACLTCR_LST_Msk                           (0x3FFUL << ETH_MACLTCR_LST_Pos) /*!< 0x03FF0000 */
+#define ETH_MACLTCR_LST                               ETH_MACLTCR_LST_Msk      /* LPI LS TIMER */
+#define ETH_MACLTCR_TWT_Pos                           (0U)
+#define ETH_MACLTCR_TWT_Msk                           (0xFFFFUL << ETH_MACLTCR_TWT_Pos) /*!< 0x0000FFFF */
+#define ETH_MACLTCR_TWT                               ETH_MACLTCR_TWT_Msk      /* LPI TW TIMER */
+
+/* Bit definition for Ethernet MAC LPI Entry Timer Register */
+#define ETH_MACLETR_LPIET_Pos                         (0U)
+#define ETH_MACLETR_LPIET_Msk                         (0xFFFFFUL << ETH_MACLETR_LPIET_Pos) /*!< 0x000FFFFF */
+#define ETH_MACLETR_LPIET                             ETH_MACLETR_LPIET_Msk    /* LPI Entry Timer */
+
+/* Bit definition for Ethernet MAC 1US Tic Counter Register */
+#define ETH_MAC1USTCR_TIC1USCNTR_Pos                  (0U)
+#define ETH_MAC1USTCR_TIC1USCNTR_Msk                  (0xFFFUL << ETH_MAC1USTCR_TIC1USCNTR_Pos) /*!< 0x00000FFF */
+#define ETH_MAC1USTCR_TIC1USCNTR                      ETH_MAC1USTCR_TIC1USCNTR_Msk /* 1US TIC Counter */
+
+/* Bit definition for Ethernet MAC Version Register */
+#define ETH_MACVR_USERVER_Pos                         (8U)
+#define ETH_MACVR_USERVER_Msk                         (0xFFUL << ETH_MACVR_USERVER_Pos) /*!< 0x0000FF00 */
+#define ETH_MACVR_USERVER                             ETH_MACVR_USERVER_Msk    /* User-defined Version */
+#define ETH_MACVR_SNPSVER_Pos                         (0U)
+#define ETH_MACVR_SNPSVER_Msk                         (0xFFUL << ETH_MACVR_SNPSVER_Pos) /*!< 0x000000FF */
+#define ETH_MACVR_SNPSVER                             ETH_MACVR_SNPSVER_Msk    /* Synopsys-defined Version */
+
+/* Bit definition for Ethernet MAC Debug Register */
+#define ETH_MACDR_TFCSTS_Pos                          (17U)
+#define ETH_MACDR_TFCSTS_Msk                          (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
+#define ETH_MACDR_TFCSTS                              ETH_MACDR_TFCSTS_Msk     /* MAC Transmit Packet Controller Status */
+#define ETH_MACDR_TFCSTS_IDLE                         ((uint32_t)0x00000000)   /* Idle state */
+#define ETH_MACDR_TFCSTS_WAIT_Pos                     (17U)
+#define ETH_MACDR_TFCSTS_WAIT_Msk                     (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
+#define ETH_MACDR_TFCSTS_WAIT                         ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
+#define ETH_MACDR_TFCSTS_GENERATEPCP_Pos              (18U)
+#define ETH_MACDR_TFCSTS_GENERATEPCP_Msk              (0x1UL << ETH_MACDR_TFCSTS_GENERATEPCP_Pos) /*!< 0x00040000 */
+#define ETH_MACDR_TFCSTS_GENERATEPCP                  ETH_MACDR_TFCSTS_GENERATEPCP_Msk /* Generating and transmitting a Pause control packet */
+#define ETH_MACDR_TFCSTS_TRASFERIP_Pos                (17U)
+#define ETH_MACDR_TFCSTS_TRASFERIP_Msk                (0x3UL << ETH_MACDR_TFCSTS_TRASFERIP_Pos) /*!< 0x00060000 */
+#define ETH_MACDR_TFCSTS_TRASFERIP                    ETH_MACDR_TFCSTS_TRASFERIP_Msk /* Transferring input packet for transmission */
+#define ETH_MACDR_TPESTS_Pos                          (16U)
+#define ETH_MACDR_TPESTS_Msk                          (0x1UL << ETH_MACDR_TPESTS_Pos) /*!< 0x00010000 */
+#define ETH_MACDR_TPESTS                              ETH_MACDR_TPESTS_Msk     /* MAC Receive Packet Controller FIFO Status */
+#define ETH_MACDR_RFCFCSTS_Pos                        (1U)
+#define ETH_MACDR_RFCFCSTS_Msk                        (0x3UL << ETH_MACDR_RFCFCSTS_Pos) /*!< 0x00000006 */
+#define ETH_MACDR_RFCFCSTS                            ETH_MACDR_RFCFCSTS_Msk   /* MAC MII Transmit Protocol Engine Status */
+#define ETH_MACDR_RPESTS_Pos                          (0U)
+#define ETH_MACDR_RPESTS_Msk                          (0x1UL << ETH_MACDR_RPESTS_Pos) /*!< 0x00000001 */
+#define ETH_MACDR_RPESTS                              ETH_MACDR_RPESTS_Msk     /* MAC MII Receive Protocol Engine Status */
+
+/* Bit definition for Ethernet MAC HW Feature0 Register */
+#define ETH_MACHWF0R_ACTPHYSEL_Pos                    (28U)
+#define ETH_MACHWF0R_ACTPHYSEL_Msk                    (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
+#define ETH_MACHWF0R_ACTPHYSEL                        ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
+#define ETH_MACHWF0R_ACTPHYSEL_MII                    ((uint32_t)0x00000000)   /* MII */
+#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos               (30U)
+#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk               (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
+#define ETH_MACHWF0R_ACTPHYSEL_RMII                   ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
+#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos             (28U)
+#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk             (0x7UL << ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos) /*!< 0x70000000 */
+#define ETH_MACHWF0R_ACTPHYSEL_REVMII                 ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk /* RevMII */
+#define ETH_MACHWF0R_SAVLANINS_Pos                    (27U)
+#define ETH_MACHWF0R_SAVLANINS_Msk                    (0x1UL << ETH_MACHWF0R_SAVLANINS_Pos) /*!< 0x08000000 */
+#define ETH_MACHWF0R_SAVLANINS                        ETH_MACHWF0R_SAVLANINS_Msk /* Source Address or VLAN Insertion Enable */
+#define ETH_MACHWF0R_TSSTSSEL_Pos                     (25U)
+#define ETH_MACHWF0R_TSSTSSEL_Msk                     (0x3UL << ETH_MACHWF0R_TSSTSSEL_Pos) /*!< 0x06000000 */
+#define ETH_MACHWF0R_TSSTSSEL                         ETH_MACHWF0R_TSSTSSEL_Msk /* Timestamp System Time Source */
+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos            (25U)
+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos) /*!< 0x02000000 */
+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL                ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk /* Timestamp System Time Source: Internal */
+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos            (26U)
+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos) /*!< 0x04000000 */
+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL                ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk /* Timestamp System Time Source: External */
+#define ETH_MACHWF0R_TSSTSSEL_BOTH_Pos                (25U)
+#define ETH_MACHWF0R_TSSTSSEL_BOTH_Msk                (0x3UL << ETH_MACHWF0R_TSSTSSEL_BOTH_Pos) /*!< 0x06000000 */
+#define ETH_MACHWF0R_TSSTSSEL_BOTH                    ETH_MACHWF0R_TSSTSSEL_BOTH_Msk /* Timestamp System Time Source: Internal & External */
+#define ETH_MACHWF0R_MACADR64SEL_Pos                  (24U)
+#define ETH_MACHWF0R_MACADR64SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR64SEL_Pos) /*!< 0x01000000 */
+#define ETH_MACHWF0R_MACADR64SEL                      ETH_MACHWF0R_MACADR64SEL_Msk /* MAC Addresses 64-127 Selected */
+#define ETH_MACHWF0R_MACADR32SEL_Pos                  (23U)
+#define ETH_MACHWF0R_MACADR32SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR32SEL_Pos) /*!< 0x00800000 */
+#define ETH_MACHWF0R_MACADR32SEL                      ETH_MACHWF0R_MACADR32SEL_Msk /* MAC Addresses 32-63 Selected */
+#define ETH_MACHWF0R_ADDMACADRSEL_Pos                 (18U)
+#define ETH_MACHWF0R_ADDMACADRSEL_Msk                 (0x1FUL << ETH_MACHWF0R_ADDMACADRSEL_Pos) /*!< 0x007C0000 */
+#define ETH_MACHWF0R_ADDMACADRSEL                     ETH_MACHWF0R_ADDMACADRSEL_Msk /* MAC Addresses 1- 31 Selected */
+#define ETH_MACHWF0R_RXCOESEL_Pos                     (16U)
+#define ETH_MACHWF0R_RXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_RXCOESEL_Pos) /*!< 0x00010000 */
+#define ETH_MACHWF0R_RXCOESEL                         ETH_MACHWF0R_RXCOESEL_Msk /* Receive Checksum Offload Enabled */
+#define ETH_MACHWF0R_TXCOESEL_Pos                     (14U)
+#define ETH_MACHWF0R_TXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_TXCOESEL_Pos) /*!< 0x00004000 */
+#define ETH_MACHWF0R_TXCOESEL                         ETH_MACHWF0R_TXCOESEL_Msk /* Transmit Checksum Offload Enabled */
+#define ETH_MACHWF0R_EEESEL_Pos                       (13U)
+#define ETH_MACHWF0R_EEESEL_Msk                       (0x1UL << ETH_MACHWF0R_EEESEL_Pos) /*!< 0x00002000 */
+#define ETH_MACHWF0R_EEESEL                           ETH_MACHWF0R_EEESEL_Msk  /* Energy Efficient Ethernet Enabled */
+#define ETH_MACHWF0R_TSSEL_Pos                        (12U)
+#define ETH_MACHWF0R_TSSEL_Msk                        (0x1UL << ETH_MACHWF0R_TSSEL_Pos) /*!< 0x00001000 */
+#define ETH_MACHWF0R_TSSEL                            ETH_MACHWF0R_TSSEL_Msk   /* IEEE 1588-2008 Timestamp Enabled */
+#define ETH_MACHWF0R_ARPOFFSEL_Pos                    (9U)
+#define ETH_MACHWF0R_ARPOFFSEL_Msk                    (0x1UL << ETH_MACHWF0R_ARPOFFSEL_Pos) /*!< 0x00000200 */
+#define ETH_MACHWF0R_ARPOFFSEL                        ETH_MACHWF0R_ARPOFFSEL_Msk /* ARP Offload Enabled */
+#define ETH_MACHWF0R_MMCSEL_Pos                       (8U)
+#define ETH_MACHWF0R_MMCSEL_Msk                       (0x1UL << ETH_MACHWF0R_MMCSEL_Pos) /*!< 0x00000100 */
+#define ETH_MACHWF0R_MMCSEL                           ETH_MACHWF0R_MMCSEL_Msk  /* RMON Module Enable */
+#define ETH_MACHWF0R_MGKSEL_Pos                       (7U)
+#define ETH_MACHWF0R_MGKSEL_Msk                       (0x1UL << ETH_MACHWF0R_MGKSEL_Pos) /*!< 0x00000080 */
+#define ETH_MACHWF0R_MGKSEL                           ETH_MACHWF0R_MGKSEL_Msk  /* PMT Magic Packet Enable */
+#define ETH_MACHWF0R_RWKSEL_Pos                       (6U)
+#define ETH_MACHWF0R_RWKSEL_Msk                       (0x1UL << ETH_MACHWF0R_RWKSEL_Pos) /*!< 0x00000040 */
+#define ETH_MACHWF0R_RWKSEL                           ETH_MACHWF0R_RWKSEL_Msk  /* PMT Remote Wake-up Packet Enable */
+#define ETH_MACHWF0R_SMASEL_Pos                       (5U)
+#define ETH_MACHWF0R_SMASEL_Msk                       (0x1UL << ETH_MACHWF0R_SMASEL_Pos) /*!< 0x00000020 */
+#define ETH_MACHWF0R_SMASEL                           ETH_MACHWF0R_SMASEL_Msk  /* SMA (MDIO) Interface */
+#define ETH_MACHWF0R_VLHASH_Pos                       (4U)
+#define ETH_MACHWF0R_VLHASH_Msk                       (0x1UL << ETH_MACHWF0R_VLHASH_Pos) /*!< 0x00000010 */
+#define ETH_MACHWF0R_VLHASH                           ETH_MACHWF0R_VLHASH_Msk  /* VLAN Hash Filter Selected */
+#define ETH_MACHWF0R_PCSSEL_Pos                       (3U)
+#define ETH_MACHWF0R_PCSSEL_Msk                       (0x1UL << ETH_MACHWF0R_PCSSEL_Pos) /*!< 0x00000008 */
+#define ETH_MACHWF0R_PCSSEL                           ETH_MACHWF0R_PCSSEL_Msk  /* PCS Registers (TBI, SGMII, or RTBI PHY interface) */
+#define ETH_MACHWF0R_HDSEL_Pos                        (2U)
+#define ETH_MACHWF0R_HDSEL_Msk                        (0x1UL << ETH_MACHWF0R_HDSEL_Pos) /*!< 0x00000004 */
+#define ETH_MACHWF0R_HDSEL                            ETH_MACHWF0R_HDSEL_Msk   /* Half-duplex Support */
+#define ETH_MACHWF0R_GMIISEL_Pos                      (1U)
+#define ETH_MACHWF0R_GMIISEL_Msk                      (0x1UL << ETH_MACHWF0R_GMIISEL_Pos) /*!< 0x00000002 */
+#define ETH_MACHWF0R_GMIISEL                          ETH_MACHWF0R_GMIISEL_Msk /* 1000 Mbps Support */
+#define ETH_MACHWF0R_MIISEL_Pos                       (0U)
+#define ETH_MACHWF0R_MIISEL_Msk                       (0x1UL << ETH_MACHWF0R_MIISEL_Pos) /*!< 0x00000001 */
+#define ETH_MACHWF0R_MIISEL                           ETH_MACHWF0R_MIISEL_Msk  /* 10 or 100 Mbps Support */
+
+/* Bit definition for Ethernet MAC HW Feature1 Register */
+#define ETH_MACHWF1R_L3L4FNUM_Pos                     (27U)
+#define ETH_MACHWF1R_L3L4FNUM_Msk                     (0xFUL << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x78000000 */
+#define ETH_MACHWF1R_L3L4FNUM                         ETH_MACHWF1R_L3L4FNUM_Msk /* Total number of L3 or L4 Filters */
+#define ETH_MACHWF1R_HASHTBLSZ_Pos                    (24U)
+#define ETH_MACHWF1R_HASHTBLSZ_Msk                    (0x3UL << ETH_MACHWF1R_HASHTBLSZ_Pos) /*!< 0x03000000 */
+#define ETH_MACHWF1R_HASHTBLSZ                        ETH_MACHWF1R_HASHTBLSZ_Msk /* Hash Table Size */
+#define ETH_MACHWF1R_AVSEL_Pos                        (20U)
+#define ETH_MACHWF1R_AVSEL_Msk                        (0x1UL << ETH_MACHWF1R_AVSEL_Pos) /*!< 0x00100000 */
+#define ETH_MACHWF1R_AVSEL                            ETH_MACHWF1R_AVSEL_Msk   /* AV Feature Enabled */
+#define ETH_MACHWF1R_DBGMEMA_Pos                      (19U)
+#define ETH_MACHWF1R_DBGMEMA_Msk                      (0x1UL << ETH_MACHWF1R_DBGMEMA_Pos) /*!< 0x00080000 */
+#define ETH_MACHWF1R_DBGMEMA                          ETH_MACHWF1R_DBGMEMA_Msk /* Debug Memory Interface Enabled */
+#define ETH_MACHWF1R_TSOEN_Pos                        (18U)
+#define ETH_MACHWF1R_TSOEN_Msk                        (0x1UL << ETH_MACHWF1R_TSOEN_Pos) /*!< 0x00040000 */
+#define ETH_MACHWF1R_TSOEN                            ETH_MACHWF1R_TSOEN_Msk   /* TCP Segmentation Offload Enable */
+#define ETH_MACHWF1R_SPHEN_Pos                        (17U)
+#define ETH_MACHWF1R_SPHEN_Msk                        (0x1UL << ETH_MACHWF1R_SPHEN_Pos) /*!< 0x00020000 */
+#define ETH_MACHWF1R_SPHEN                            ETH_MACHWF1R_SPHEN_Msk   /* Split Header Feature Enable */
+#define ETH_MACHWF1R_DCBEN_Pos                        (16U)
+#define ETH_MACHWF1R_DCBEN_Msk                        (0x1UL << ETH_MACHWF1R_DCBEN_Pos) /*!< 0x00010000 */
+#define ETH_MACHWF1R_DCBEN                            ETH_MACHWF1R_DCBEN_Msk   /* DCB Feature Enable */
+#define ETH_MACHWF1R_ADDR64_Pos                       (14U)
+#define ETH_MACHWF1R_ADDR64_Msk                       (0x3UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x0000C000 */
+#define ETH_MACHWF1R_ADDR64                           ETH_MACHWF1R_ADDR64_Msk  /* Address Width */
+#define ETH_MACHWF1R_ADDR64_32                        (0x0UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00000000 */
+#define ETH_MACHWF1R_ADDR64_40                        (0x1UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00004000 */
+#define ETH_MACHWF1R_ADDR64_48                        (0x2UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00008000 */
+#define ETH_MACHWF1R_ADVTHWORD_Pos                    (13U)
+#define ETH_MACHWF1R_ADVTHWORD_Msk                    (0x1UL << ETH_MACHWF1R_ADVTHWORD_Pos) /*!< 0x00002000 */
+#define ETH_MACHWF1R_ADVTHWORD                        ETH_MACHWF1R_ADVTHWORD_Msk /* IEEE 1588 High Word Register Enable */
+#define ETH_MACHWF1R_PTOEN_Pos                        (12U)
+#define ETH_MACHWF1R_PTOEN_Msk                        (0x1UL << ETH_MACHWF1R_PTOEN_Pos) /*!< 0x00001000 */
+#define ETH_MACHWF1R_PTOEN                            ETH_MACHWF1R_PTOEN_Msk   /* PTP Offload Enable */
+#define ETH_MACHWF1R_OSTEN_Pos                        (11U)
+#define ETH_MACHWF1R_OSTEN_Msk                        (0x1UL << ETH_MACHWF1R_OSTEN_Pos) /*!< 0x00000800 */
+#define ETH_MACHWF1R_OSTEN                            ETH_MACHWF1R_OSTEN_Msk   /* One-Step Timestamping Enable */
+#define ETH_MACHWF1R_TXFIFOSIZE_Pos                   (6U)
+#define ETH_MACHWF1R_TXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x000007C0 */
+#define ETH_MACHWF1R_TXFIFOSIZE                       ETH_MACHWF1R_TXFIFOSIZE_Msk /* MTL Transmit FIFO Size */
+#define ETH_MACHWF1R_RXFIFOSIZE_Pos                   (0U)
+#define ETH_MACHWF1R_RXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x0000001F */
+#define ETH_MACHWF1R_RXFIFOSIZE                       ETH_MACHWF1R_RXFIFOSIZE_Msk /* MTL Receive FIFO Size */
+
+/* Bit definition for Ethernet MAC HW Feature2 Register */
+#define ETH_MACHWF2R_AUXSNAPNUM_Pos                   (28U)
+#define ETH_MACHWF2R_AUXSNAPNUM_Msk                   (0x7UL << ETH_MACHWF2R_AUXSNAPNUM_Pos) /*!< 0x70000000 */
+#define ETH_MACHWF2R_AUXSNAPNUM                       ETH_MACHWF2R_AUXSNAPNUM_Msk /* Number of Auxiliary Snapshot Inputs */
+#define ETH_MACHWF2R_PPSOUTNUM_Pos                    (24U)
+#define ETH_MACHWF2R_PPSOUTNUM_Msk                    (0x7UL << ETH_MACHWF2R_PPSOUTNUM_Pos) /*!< 0x07000000 */
+#define ETH_MACHWF2R_PPSOUTNUM                        ETH_MACHWF2R_PPSOUTNUM_Msk /*  Number of PPS Outputs */
+#define ETH_MACHWF2R_TXCHCNT_Pos                      (18U)
+#define ETH_MACHWF2R_TXCHCNT_Msk                      (0xFUL << ETH_MACHWF2R_TXCHCNT_Pos) /*!< 0x003C0000 */
+#define ETH_MACHWF2R_TXCHCNT                          ETH_MACHWF2R_TXCHCNT_Msk /* Number of DMA Transmit Channels */
+#define ETH_MACHWF2R_RXCHCNT_Pos                      (13U)
+#define ETH_MACHWF2R_RXCHCNT_Msk                      (0x7UL << ETH_MACHWF2R_RXCHCNT_Pos) /*!< 0x0000E000 */
+#define ETH_MACHWF2R_RXCHCNT                          ETH_MACHWF2R_RXCHCNT_Msk /* Number of DMA Receive Channels */
+#define ETH_MACHWF2R_TXQCNT_Pos                       (6U)
+#define ETH_MACHWF2R_TXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_TXQCNT_Pos) /*!< 0x000003C0 */
+#define ETH_MACHWF2R_TXQCNT                           ETH_MACHWF2R_TXQCNT_Msk  /* Number of MTL Transmit Queues */
+#define ETH_MACHWF2R_RXQCNT_Pos                       (0U)
+#define ETH_MACHWF2R_RXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_RXQCNT_Pos) /*!< 0x0000000F */
+#define ETH_MACHWF2R_RXQCNT                           ETH_MACHWF2R_RXQCNT_Msk  /* Number of MTL Receive Queues */
+
+/* Bit definition for Ethernet MAC MDIO Address Register */
+#define ETH_MACMDIOAR_PSE_Pos                         (27U)
+#define ETH_MACMDIOAR_PSE_Msk                         (0x1UL << ETH_MACMDIOAR_PSE_Pos) /*!< 0x08000000 */
+#define ETH_MACMDIOAR_PSE                             ETH_MACMDIOAR_PSE_Msk    /* Preamble Suppression Enable */
+#define ETH_MACMDIOAR_BTB_Pos                         (26U)
+#define ETH_MACMDIOAR_BTB_Msk                         (0x1UL << ETH_MACMDIOAR_BTB_Pos) /*!< 0x04000000 */
+#define ETH_MACMDIOAR_BTB                             ETH_MACMDIOAR_BTB_Msk    /* Back to Back transactions */
+#define ETH_MACMDIOAR_PA_Pos                          (21U)
+#define ETH_MACMDIOAR_PA_Msk                          (0x1FUL << ETH_MACMDIOAR_PA_Pos) /*!< 0x03E00000 */
+#define ETH_MACMDIOAR_PA                              ETH_MACMDIOAR_PA_Msk     /* Physical Layer Address */
+#define ETH_MACMDIOAR_RDA_Pos                         (16U)
+#define ETH_MACMDIOAR_RDA_Msk                         (0x1FUL << ETH_MACMDIOAR_RDA_Pos) /*!< 0x001F0000 */
+#define ETH_MACMDIOAR_RDA                             ETH_MACMDIOAR_RDA_Msk    /* Register/Device Address */
+#define ETH_MACMDIOAR_NTC_Pos                         (12U)
+#define ETH_MACMDIOAR_NTC_Msk                         (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */
+#define ETH_MACMDIOAR_NTC                             ETH_MACMDIOAR_NTC_Msk    /* Number of Trailing Clocks */
+#define ETH_MACMDIOAR_CR_Pos                          (8U)
+#define ETH_MACMDIOAR_CR_Msk                          (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
+#define ETH_MACMDIOAR_CR                              ETH_MACMDIOAR_CR_Msk     /* CSR Clock Range */
+#define ETH_MACMDIOAR_CR_DIV42                        ((uint32_t)0x00000000)   /* CSR clock/42 */
+#define ETH_MACMDIOAR_CR_DIV62_Pos                    (8U)
+#define ETH_MACMDIOAR_CR_DIV62_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
+#define ETH_MACMDIOAR_CR_DIV62                        ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
+#define ETH_MACMDIOAR_CR_DIV16_Pos                    (9U)
+#define ETH_MACMDIOAR_CR_DIV16_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV16_Pos) /*!< 0x00000200 */
+#define ETH_MACMDIOAR_CR_DIV16                        ETH_MACMDIOAR_CR_DIV16_Msk /* CSR clock/16 */
+#define ETH_MACMDIOAR_CR_DIV26_Pos                    (8U)
+#define ETH_MACMDIOAR_CR_DIV26_Msk                    (0x3UL << ETH_MACMDIOAR_CR_DIV26_Pos) /*!< 0x00000300 */
+#define ETH_MACMDIOAR_CR_DIV26                        ETH_MACMDIOAR_CR_DIV26_Msk /* CSR clock/26 */
+#define ETH_MACMDIOAR_CR_DIV102_Pos                   (10U)
+#define ETH_MACMDIOAR_CR_DIV102_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV102_Pos) /*!< 0x00000400 */
+#define ETH_MACMDIOAR_CR_DIV102                       ETH_MACMDIOAR_CR_DIV102_Msk /* CSR clock/102 */
+#define ETH_MACMDIOAR_CR_DIV124_Pos                   (8U)
+#define ETH_MACMDIOAR_CR_DIV124_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV124_Pos) /*!< 0x00000500 */
+#define ETH_MACMDIOAR_CR_DIV124                       ETH_MACMDIOAR_CR_DIV124_Msk /* CSR clock/124 */
+#define ETH_MACMDIOAR_CR_DIV4AR_Pos                   (11U)
+#define ETH_MACMDIOAR_CR_DIV4AR_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV4AR_Pos) /*!< 0x00000800 */
+#define ETH_MACMDIOAR_CR_DIV4AR                       ETH_MACMDIOAR_CR_DIV4AR_Msk /* CSR clock/4: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV6AR_Pos                   (8U)
+#define ETH_MACMDIOAR_CR_DIV6AR_Msk                   (0x9UL << ETH_MACMDIOAR_CR_DIV6AR_Pos) /*!< 0x00000900 */
+#define ETH_MACMDIOAR_CR_DIV6AR                       ETH_MACMDIOAR_CR_DIV6AR_Msk /* CSR clock/6: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV8AR_Pos                   (9U)
+#define ETH_MACMDIOAR_CR_DIV8AR_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV8AR_Pos) /*!< 0x00000A00 */
+#define ETH_MACMDIOAR_CR_DIV8AR                       ETH_MACMDIOAR_CR_DIV8AR_Msk /* CSR clock/8: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV10AR_Pos                  (8U)
+#define ETH_MACMDIOAR_CR_DIV10AR_Msk                  (0xBUL << ETH_MACMDIOAR_CR_DIV10AR_Pos) /*!< 0x00000B00 */
+#define ETH_MACMDIOAR_CR_DIV10AR                      ETH_MACMDIOAR_CR_DIV10AR_Msk /* CSR clock/10: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV12AR_Pos                  (10U)
+#define ETH_MACMDIOAR_CR_DIV12AR_Msk                  (0x3UL << ETH_MACMDIOAR_CR_DIV12AR_Pos) /*!< 0x00000C00 */
+#define ETH_MACMDIOAR_CR_DIV12AR                      ETH_MACMDIOAR_CR_DIV12AR_Msk /* CSR clock/12: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV14AR_Pos                  (8U)
+#define ETH_MACMDIOAR_CR_DIV14AR_Msk                  (0xDUL << ETH_MACMDIOAR_CR_DIV14AR_Pos) /*!< 0x00000D00 */
+#define ETH_MACMDIOAR_CR_DIV14AR                      ETH_MACMDIOAR_CR_DIV14AR_Msk /* CSR clock/14: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV16AR_Pos                  (9U)
+#define ETH_MACMDIOAR_CR_DIV16AR_Msk                  (0x7UL << ETH_MACMDIOAR_CR_DIV16AR_Pos) /*!< 0x00000E00 */
+#define ETH_MACMDIOAR_CR_DIV16AR                      ETH_MACMDIOAR_CR_DIV16AR_Msk /* CSR clock/16: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV18AR_Pos                  (8U)
+#define ETH_MACMDIOAR_CR_DIV18AR_Msk                  (0xFUL << ETH_MACMDIOAR_CR_DIV18AR_Pos) /*!< 0x00000F00 */
+#define ETH_MACMDIOAR_CR_DIV18AR                      ETH_MACMDIOAR_CR_DIV18AR_Msk /* CSR clock/18: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_SKAP_Pos                        (4U)
+#define ETH_MACMDIOAR_SKAP_Msk                        (0x1UL << ETH_MACMDIOAR_SKAP_Pos) /*!< 0x00000010 */
+#define ETH_MACMDIOAR_SKAP                            ETH_MACMDIOAR_SKAP_Msk   /* Skip Address Packet */
+#define ETH_MACMDIOAR_MOC_Pos                         (2U)
+#define ETH_MACMDIOAR_MOC_Msk                         (0x3UL << ETH_MACMDIOAR_MOC_Pos) /*!< 0x0000000C */
+#define ETH_MACMDIOAR_MOC                             ETH_MACMDIOAR_MOC_Msk    /* MII Operation Command */
+#define ETH_MACMDIOAR_MOC_WR_Pos                      (2U)
+#define ETH_MACMDIOAR_MOC_WR_Msk                      (0x1UL << ETH_MACMDIOAR_MOC_WR_Pos) /*!< 0x00000004 */
+#define ETH_MACMDIOAR_MOC_WR                          ETH_MACMDIOAR_MOC_WR_Msk /* Write */
+#define ETH_MACMDIOAR_MOC_PRDIA_Pos                   (3U)
+#define ETH_MACMDIOAR_MOC_PRDIA_Msk                   (0x1UL << ETH_MACMDIOAR_MOC_PRDIA_Pos) /*!< 0x00000008 */
+#define ETH_MACMDIOAR_MOC_PRDIA                       ETH_MACMDIOAR_MOC_PRDIA_Msk /* Post Read Increment Address for Clause 45 PHY */
+#define ETH_MACMDIOAR_MOC_RD_Pos                      (2U)
+#define ETH_MACMDIOAR_MOC_RD_Msk                      (0x3UL << ETH_MACMDIOAR_MOC_RD_Pos) /*!< 0x0000000C */
+#define ETH_MACMDIOAR_MOC_RD                          ETH_MACMDIOAR_MOC_RD_Msk /* Read */
+#define ETH_MACMDIOAR_C45E_Pos                        (1U)
+#define ETH_MACMDIOAR_C45E_Msk                        (0x1UL << ETH_MACMDIOAR_C45E_Pos) /*!< 0x00000002 */
+#define ETH_MACMDIOAR_C45E                            ETH_MACMDIOAR_C45E_Msk   /* Clause 45 PHY Enable */
+#define ETH_MACMDIOAR_MB_Pos                          (0U)
+#define ETH_MACMDIOAR_MB_Msk                          (0x1UL << ETH_MACMDIOAR_MB_Pos) /*!< 0x00000001 */
+#define ETH_MACMDIOAR_MB                              ETH_MACMDIOAR_MB_Msk     /* MII Busy */
+
+/* Bit definition for Ethernet MAC MDIO Data Register */
+#define ETH_MACMDIODR_RA_Pos                          (16U)
+#define ETH_MACMDIODR_RA_Msk                          (0xFFFFUL << ETH_MACMDIODR_RA_Pos) /*!< 0xFFFF0000 */
+#define ETH_MACMDIODR_RA                              ETH_MACMDIODR_RA_Msk     /* Register Address */
+#define ETH_MACMDIODR_MD_Pos                          (0U)
+#define ETH_MACMDIODR_MD_Msk                          (0xFFFFUL << ETH_MACMDIODR_MD_Pos) /*!< 0x0000FFFF */
+#define ETH_MACMDIODR_MD                              ETH_MACMDIODR_MD_Msk     /* MII Data */
+
+/* Bit definition for Ethernet ARP Address Register */
+#define ETH_MACARPAR_ARPPA_Pos                         (0U)
+#define ETH_MACARPAR_ARPPA_Msk                         (0xFFFFFFFFUL << ETH_MACARPAR_ARPPA_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACARPAR_ARPPA                             ETH_MACARPAR_ARPPA_Msk     /* ARP Protocol Address */
+
+/* Bit definition for Ethernet MAC Address 0 High Register */
+#define ETH_MACA0HR_AE_Pos                            (31U)
+#define ETH_MACA0HR_AE_Msk                            (0x1UL << ETH_MACA0HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA0HR_AE                                ETH_MACA0HR_AE_Msk /* Address Enable*/
+#define ETH_MACA0HR_ADDRHI_Pos                        (0U)
+#define ETH_MACA0HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA0HR_ADDRHI                            ETH_MACA0HR_ADDRHI_Msk   /* MAC Address 0*/
+
+/* Bit definition for Ethernet MAC Address 0 Low Register */
+#define ETH_MACA0LR_ADDRLO_Pos                        (0U)
+#define ETH_MACA0LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA0LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA0LR_ADDRLO                            ETH_MACA0LR_ADDRLO_Msk   /* MAC Address 0*/
+
+/* Bit definition for Ethernet MAC Address 1 High Register */
+#define ETH_MACA1HR_AE_Pos                            (31U)
+#define ETH_MACA1HR_AE_Msk                            (0x1UL << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA1HR_AE                                ETH_MACA1HR_AE_Msk /* Address Enable*/
+#define ETH_MACA1HR_SA_Pos                            (30U)
+#define ETH_MACA1HR_SA_Msk                            (0x1UL << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA1HR_SA                                ETH_MACA1HR_SA_Msk /* Source Address */
+#define ETH_MACA1HR_MBC_Pos                           (24U)
+#define ETH_MACA1HR_MBC_Msk                           (0x3FUL << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA1HR_MBC                               ETH_MACA1HR_MBC_Msk /* Mask Byte Control */
+#define ETH_MACA1HR_ADDRHI_Pos                        (0U)
+#define ETH_MACA1HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA1HR_ADDRHI                            ETH_MACA1HR_ADDRHI_Msk   /* MAC Address 1*/
+
+/* Bit definition for Ethernet MAC Address 1 Low Register */
+#define ETH_MACA1LR_ADDRLO_Pos                        (0U)
+#define ETH_MACA1LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA1LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA1LR_ADDRLO                            ETH_MACA1LR_ADDRLO_Msk   /* MAC Address 1*/
+
+/* Bit definition for Ethernet MAC Address 2 High Register */
+#define ETH_MACA2HR_AE_Pos                            (31U)
+#define ETH_MACA2HR_AE_Msk                            (0x1UL << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA2HR_AE                                ETH_MACA2HR_AE_Msk /* Address Enable*/
+#define ETH_MACA2HR_SA_Pos                            (30U)
+#define ETH_MACA2HR_SA_Msk                            (0x1UL << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA2HR_SA                                ETH_MACA2HR_SA_Msk /* Source Address */
+#define ETH_MACA2HR_MBC_Pos                           (24U)
+#define ETH_MACA2HR_MBC_Msk                           (0x3FUL << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA2HR_MBC                               ETH_MACA2HR_MBC_Msk /* Mask Byte Control */
+#define ETH_MACA2HR_ADDRHI_Pos                        (0U)
+#define ETH_MACA2HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA2HR_ADDRHI                            ETH_MACA2HR_ADDRHI_Msk   /* MAC Address 1*/
+
+/* Bit definition for Ethernet MAC Address 2 Low Register */
+#define ETH_MACA2LR_ADDRLO_Pos                        (0U)
+#define ETH_MACA2LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA2LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA2LR_ADDRLO                            ETH_MACA2LR_ADDRLO_Msk   /* MAC Address 2*/
+
+/* Bit definition for Ethernet MAC Address 3 High Register */
+#define ETH_MACA3HR_AE_Pos                            (31U)
+#define ETH_MACA3HR_AE_Msk                            (0x1UL << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA3HR_AE                                ETH_MACA3HR_AE_Msk /* Address Enable*/
+#define ETH_MACA3HR_SA_Pos                            (30U)
+#define ETH_MACA3HR_SA_Msk                            (0x1UL << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA3HR_SA                                ETH_MACA3HR_SA_Msk /* Source Address */
+#define ETH_MACA3HR_MBC_Pos                           (24U)
+#define ETH_MACA3HR_MBC_Msk                           (0x3FUL << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA3HR_MBC                               ETH_MACA3HR_MBC_Msk /* Mask Byte Control */
+#define ETH_MACA3HR_ADDRHI_Pos                        (0U)
+#define ETH_MACA3HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA3HR_ADDRHI                            ETH_MACA3HR_ADDRHI_Msk   /* MAC Address 1*/
+
+/* Bit definition for Ethernet MAC Address 3 Low Register */
+#define ETH_MACA3LR_ADDRLO_Pos                        (0U)
+#define ETH_MACA3LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA3LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA3LR_ADDRLO                            ETH_MACA3LR_ADDRLO_Msk   /* MAC Address 3*/
+
+/* Bit definition for Ethernet MAC Address High Register */
+#define ETH_MACAHR_AE_Pos                             (31U)
+#define ETH_MACAHR_AE_Msk                             (0x1UL << ETH_MACAHR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACAHR_AE                                 ETH_MACAHR_AE_Msk        /* Address enable */
+#define ETH_MACAHR_SA_Pos                             (30U)
+#define ETH_MACAHR_SA_Msk                             (0x1UL << ETH_MACAHR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACAHR_SA                                 ETH_MACAHR_SA_Msk        /* Source address */
+#define ETH_MACAHR_MBC_Pos                            (24U)
+#define ETH_MACAHR_MBC_Msk                            (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACAHR_MBC                                ETH_MACAHR_MBC_Msk       /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+#define ETH_MACAHR_MBC_HBITS15_8                      ((uint32_t)0x20000000)   /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACAHR_MBC_HBITS7_0                       ((uint32_t)0x10000000)   /* Mask MAC Address high reg bits [7:0] */
+#define ETH_MACAHR_MBC_LBITS31_24                     ((uint32_t)0x08000000)   /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACAHR_MBC_LBITS23_16                     ((uint32_t)0x04000000)   /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACAHR_MBC_LBITS15_8                      ((uint32_t)0x02000000)   /* Mask MAC Address low reg bits [15:8] */
+#define ETH_MACAHR_MBC_LBITS7_0                       ((uint32_t)0x01000000)   /* Mask MAC Address low reg bits [7:0] */
+#define ETH_MACAHR_MACAH_Pos                          (0U)
+#define ETH_MACAHR_MACAH_Msk                          (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */
+#define ETH_MACAHR_MACAH                              ETH_MACAHR_MACAH_Msk     /* MAC address high */
+
+/* Bit definition for Ethernet MAC Address Low Register */
+#define ETH_MACALR_MACAL_Pos                          (0U)
+#define ETH_MACALR_MACAL_Msk                          (0xFFFFFFFFUL << ETH_MACALR_MACAL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACALR_MACAL                              ETH_MACALR_MACAL_Msk     /* MAC address low */
+
+/* Bit definition for Ethernet MMC Control Register */
+#define ETH_MMCCR_UCDBC_Pos                           (8U)
+#define ETH_MMCCR_UCDBC_Msk                           (0x1UL << ETH_MMCCR_UCDBC_Pos) /*!< 0x00000100 */
+#define ETH_MMCCR_UCDBC                               ETH_MMCCR_UCDBC_Msk  /* Update MMC Counters for Dropped Broadcast Packets */
+#define ETH_MMCCR_CNTPRSTLVL_Pos                      (5U)
+#define ETH_MMCCR_CNTPRSTLVL_Msk                      (0x1UL << ETH_MMCCR_CNTPRSTLVL_Pos) /*!< 0x00000020 */
+#define ETH_MMCCR_CNTPRSTLVL                          ETH_MMCCR_CNTPRSTLVL_Msk  /* Full-Half Preset */
+#define ETH_MMCCR_CNTPRST_Pos                         (4U)
+#define ETH_MMCCR_CNTPRST_Msk                         (0x1UL << ETH_MMCCR_CNTPRST_Pos) /*!< 0x00000010 */
+#define ETH_MMCCR_CNTPRST                             ETH_MMCCR_CNTPRST_Msk  /* Counters Reset */
+#define ETH_MMCCR_CNTFREEZ_Pos                        (3U)
+#define ETH_MMCCR_CNTFREEZ_Msk                        (0x1UL << ETH_MMCCR_CNTFREEZ_Pos) /*!< 0x00000008 */
+#define ETH_MMCCR_CNTFREEZ                            ETH_MMCCR_CNTFREEZ_Msk  /* MMC Counter Freeze */
+#define ETH_MMCCR_RSTONRD_Pos                         (2U)
+#define ETH_MMCCR_RSTONRD_Msk                         (0x1UL << ETH_MMCCR_RSTONRD_Pos) /*!< 0x00000004 */
+#define ETH_MMCCR_RSTONRD                             ETH_MMCCR_RSTONRD_Msk  /* Reset On Read */
+#define ETH_MMCCR_CNTSTOPRO_Pos                       (1U)
+#define ETH_MMCCR_CNTSTOPRO_Msk                       (0x1UL << ETH_MMCCR_CNTSTOPRO_Pos) /*!< 0x00000002 */
+#define ETH_MMCCR_CNTSTOPRO                           ETH_MMCCR_CNTSTOPRO_Msk  /* Counter Stop Rollover */
+#define ETH_MMCCR_CNTRST_Pos                          (0U)
+#define ETH_MMCCR_CNTRST_Msk                          (0x1UL << ETH_MMCCR_CNTRST_Pos) /*!< 0x00000001 */
+#define ETH_MMCCR_CNTRST                              ETH_MMCCR_CNTRST_Msk  /* Counters Reset */
+
+/* Bit definition for Ethernet MMC Rx Interrupt Register */
+#define ETH_MMCRIR_RXLPITRCIS_Pos                     (27U)
+#define ETH_MMCRIR_RXLPITRCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPITRCIS_Pos) /*!< 0x08000000 */
+#define ETH_MMCRIR_RXLPITRCIS                         ETH_MMCRIR_RXLPITRCIS_Msk  /* MMC Receive LPI transition counter interrupt status */
+#define ETH_MMCRIR_RXLPIUSCIS_Pos                     (26U)
+#define ETH_MMCRIR_RXLPIUSCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPIUSCIS_Pos) /*!< 0x04000000 */
+#define ETH_MMCRIR_RXLPIUSCIS                         ETH_MMCRIR_RXLPIUSCIS_Msk  /* MMC Receive LPI microsecond counter interrupt status */
+#define ETH_MMCRIR_RXUCGPIS_Pos                       (17U)
+#define ETH_MMCRIR_RXUCGPIS_Msk                       (0x1UL << ETH_MMCRIR_RXUCGPIS_Pos) /*!< 0x00020000 */
+#define ETH_MMCRIR_RXUCGPIS                           ETH_MMCRIR_RXUCGPIS_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Status */
+#define ETH_MMCRIR_RXALGNERPIS_Pos                    (6U)
+#define ETH_MMCRIR_RXALGNERPIS_Msk                    (0x1UL << ETH_MMCRIR_RXALGNERPIS_Pos) /*!< 0x00000040 */
+#define ETH_MMCRIR_RXALGNERPIS                        ETH_MMCRIR_RXALGNERPIS_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Status */
+#define ETH_MMCRIR_RXCRCERPIS_Pos                     (5U)
+#define ETH_MMCRIR_RXCRCERPIS_Msk                     (0x1UL << ETH_MMCRIR_RXCRCERPIS_Pos) /*!< 0x00000020 */
+#define ETH_MMCRIR_RXCRCERPIS                         ETH_MMCRIR_RXCRCERPIS_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Status */
+
+/* Bit definition for Ethernet MMC Tx Interrupt Register */
+#define ETH_MMCTIR_TXLPITRCIS_Pos                     (27U)
+#define ETH_MMCTIR_TXLPITRCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPITRCIS_Pos) /*!< 0x08000000 */
+#define ETH_MMCTIR_TXLPITRCIS                         ETH_MMCTIR_TXLPITRCIS_Msk  /* MMC Transmit LPI transition counter interrupt status */
+#define ETH_MMCTIR_TXLPIUSCIS_Pos                     (26U)
+#define ETH_MMCTIR_TXLPIUSCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPIUSCIS_Pos) /*!< 0x04000000 */
+#define ETH_MMCTIR_TXLPIUSCIS                         ETH_MMCTIR_TXLPIUSCIS_Msk  /* MMC Transmit LPI microsecond counter interrupt status */
+#define ETH_MMCTIR_TXGPKTIS_Pos                       (21U)
+#define ETH_MMCTIR_TXGPKTIS_Msk                       (0x1UL << ETH_MMCTIR_TXGPKTIS_Pos) /*!< 0x00200000 */
+#define ETH_MMCTIR_TXGPKTIS                           ETH_MMCTIR_TXGPKTIS_Msk  /* MMC Transmit Good Packet Counter Interrupt Status */
+#define ETH_MMCTIR_TXMCOLGPIS_Pos                     (15U)
+#define ETH_MMCTIR_TXMCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXMCOLGPIS_Pos) /*!< 0x00008000 */
+#define ETH_MMCTIR_TXMCOLGPIS                         ETH_MMCTIR_TXMCOLGPIS_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Status */
+#define ETH_MMCTIR_TXSCOLGPIS_Pos                     (14U)
+#define ETH_MMCTIR_TXSCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXSCOLGPIS_Pos) /*!< 0x00004000 */
+#define ETH_MMCTIR_TXSCOLGPIS                         ETH_MMCTIR_TXSCOLGPIS_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Status */
+
+/* Bit definition for Ethernet MMC Rx interrupt Mask register */
+#define ETH_MMCRIMR_RXLPITRCIM_Pos                    (27U)
+#define ETH_MMCRIMR_RXLPITRCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPITRCIM_Pos) /*!< 0x08000000 */
+#define ETH_MMCRIMR_RXLPITRCIM                        ETH_MMCRIMR_RXLPITRCIM_Msk  /* MMC Receive LPI transition counter interrupt Mask */
+#define ETH_MMCRIMR_RXLPIUSCIM_Pos                    (26U)
+#define ETH_MMCRIMR_RXLPIUSCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPIUSCIM_Pos) /*!< 0x04000000 */
+#define ETH_MMCRIMR_RXLPIUSCIM                        ETH_MMCRIMR_RXLPIUSCIM_Msk  /* MMC Receive LPI microsecond counter interrupt Mask */
+#define ETH_MMCRIMR_RXUCGPIM_Pos                      (17U)
+#define ETH_MMCRIMR_RXUCGPIM_Msk                      (0x1UL << ETH_MMCRIMR_RXUCGPIM_Pos) /*!< 0x00020000 */
+#define ETH_MMCRIMR_RXUCGPIM                          ETH_MMCRIMR_RXUCGPIM_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Mask */
+#define ETH_MMCRIMR_RXALGNERPIM_Pos                   (6U)
+#define ETH_MMCRIMR_RXALGNERPIM_Msk                   (0x1UL << ETH_MMCRIMR_RXALGNERPIM_Pos) /*!< 0x00000040 */
+#define ETH_MMCRIMR_RXALGNERPIM                       ETH_MMCRIMR_RXALGNERPIM_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Mask */
+#define ETH_MMCRIMR_RXCRCERPIM_Pos                    (5U)
+#define ETH_MMCRIMR_RXCRCERPIM_Msk                    (0x1UL << ETH_MMCRIMR_RXCRCERPIM_Pos) /*!< 0x00000020 */
+#define ETH_MMCRIMR_RXCRCERPIM                        ETH_MMCRIMR_RXCRCERPIM_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Mask */
+
+/* Bit definition for Ethernet MMC Tx Interrupt Mask Register */
+#define ETH_MMCTIMR_TXLPITRCIM_Pos                    (27U)
+#define ETH_MMCTIMR_TXLPITRCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */
+#define ETH_MMCTIMR_TXLPITRCIM                        ETH_MMCTIMR_TXLPITRCIM_Msk  /* MMC Transmit LPI transition counter interrupt Mask*/
+#define ETH_MMCTIMR_TXLPIUSCIM_Pos                    (26U)
+#define ETH_MMCTIMR_TXLPIUSCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPIUSCIM_Pos) /*!< 0x04000000 */
+#define ETH_MMCTIMR_TXLPIUSCIM                        ETH_MMCTIMR_TXLPIUSCIM_Msk  /* MMC Transmit LPI microsecond counter interrupt Mask*/
+#define ETH_MMCTIMR_TXGPKTIM_Pos                      (21U)
+#define ETH_MMCTIMR_TXGPKTIM_Msk                      (0x1UL << ETH_MMCTIMR_TXGPKTIM_Pos) /*!< 0x00200000 */
+#define ETH_MMCTIMR_TXGPKTIM                          ETH_MMCTIMR_TXGPKTIM_Msk  /* MMC Transmit Good Packet Counter Interrupt Mask*/
+#define ETH_MMCTIMR_TXMCOLGPIM_Pos                    (15U)
+#define ETH_MMCTIMR_TXMCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXMCOLGPIM_Pos) /*!< 0x00008000 */
+#define ETH_MMCTIMR_TXMCOLGPIM                        ETH_MMCTIMR_TXMCOLGPIM_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask */
+#define ETH_MMCTIMR_TXSCOLGPIM_Pos                    (14U)
+#define ETH_MMCTIMR_TXSCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXSCOLGPIM_Pos) /*!< 0x00004000 */
+#define ETH_MMCTIMR_TXSCOLGPIM                        ETH_MMCTIMR_TXSCOLGPIM_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Mask */
+
+/* Bit definition for Ethernet MMC Tx Single Collision Good Packets Register */
+#define ETH_MMCTSCGPR_TXSNGLCOLG_Pos                  (0U)
+#define ETH_MMCTSCGPR_TXSNGLCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTSCGPR_TXSNGLCOLG_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTSCGPR_TXSNGLCOLG                      ETH_MMCTSCGPR_TXSNGLCOLG_msk /* Tx Single Collision Good Packets */
+
+/* Bit definition for Ethernet MMC Tx Multiple Collision Good Packets Register */
+#define ETH_MMCTMCGPR_TXMULTCOLG_Pos                  (0U)
+#define ETH_MMCTMCGPR_TXMULTCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTMCGPR_TXMULTCOLG_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTMCGPR_TXMULTCOLG                      ETH_MMCTMCGPR_TXMULTCOLG_msk /* Tx Multiple Collision Good Packets */
+
+/* Bit definition for Ethernet MMC Tx Packet Count Good Register */
+#define ETH_MMCTPCGR_TXPKTG_Pos                       (0U)
+#define ETH_MMCTPCGR_TXPKTG_msk                       (0xFFFFFFFFUL <<  ETH_MMCTPCGR_TXPKTG_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTPCGR_TXPKTG                           ETH_MMCTPCGR_TXPKTG_msk /* Tx Packet Count Good */
+
+/* Bit definition for Ethernet MMC Rx CRC Error Packets Register */
+#define ETH_MMCRCRCEPR_RXCRCERR_Pos                   (0U)
+#define ETH_MMCRCRCEPR_RXCRCERR_msk                   (0xFFFFFFFFUL <<  ETH_MMCRCRCEPR_RXCRCERR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRCRCEPR_RXCRCERR                       ETH_MMCRCRCEPR_RXCRCERR_msk /* Rx CRC Error Packets */
+
+/* Bit definition for Ethernet MMC Rx alignment error packets register */
+#define ETH_MMCRAEPR_RXALGNERR_Pos                    (0U)
+#define ETH_MMCRAEPR_RXALGNERR_msk                    (0xFFFFFFFFUL <<  ETH_MMCRAEPR_RXALGNERR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRAEPR_RXALGNERR                        ETH_MMCRAEPR_RXALGNERR_msk /* Rx Alignment Error Packets */
+
+/* Bit definition for Ethernet MMC Rx Unicast Packets Good Register */
+#define ETH_MMCRUPGR_RXUCASTG_Pos                     (0U)
+#define ETH_MMCRUPGR_RXUCASTG_msk                     (0xFFFFFFFFUL <<  ETH_MMCRUPGR_RXUCASTG_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRUPGR_RXUCASTG                         ETH_MMCRUPGR_RXUCASTG_msk /* Rx Unicast Packets Good */
+
+/* Bit definition for Ethernet MMC Tx LPI Microsecond Timer Register */
+#define ETH_MMCTLPIMSTR_TXLPIUSC_Pos                  (0U)
+#define ETH_MMCTLPIMSTR_TXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCTLPIMSTR_TXLPIUSC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTLPIMSTR_TXLPIUSC                      ETH_MMCTLPIMSTR_TXLPIUSC_msk /* Tx LPI Microseconds Counter */
+
+/* Bit definition for Ethernet MMC Tx LPI Transition Counter Register */
+#define ETH_MMCTLPITCR_TXLPITRC_Pos                   (0U)
+#define ETH_MMCTLPITCR_TXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCTLPITCR_TXLPITRC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTLPITCR_TXLPITRC                       ETH_MMCTLPITCR_TXLPITRC_msk /* Tx LPI Transition counter */
+
+/* Bit definition for Ethernet MMC Rx LPI Microsecond Counter Register */
+#define ETH_MMCRLPIMSTR_RXLPIUSC_Pos                  (0U)
+#define ETH_MMCRLPIMSTR_RXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCRLPIMSTR_RXLPIUSC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRLPIMSTR_RXLPIUSC                      ETH_MMCRLPIMSTR_RXLPIUSC_msk /* Rx LPI Microseconds Counter */
+
+/* Bit definition for Ethernet MMC Rx LPI Transition Counter Register */
+#define ETH_MMCRLPITCR_RXLPITRC_Pos                   (0U)
+#define ETH_MMCRLPITCR_RXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCRLPITCR_RXLPITRC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRLPITCR_RXLPITRC                       ETH_MMCRLPITCR_RXLPITRC_msk /* Rx LPI Transition counter */
+
+/* Bit definition for Ethernet MAC L3 L4 Control Register */
+#define ETH_MACL3L4CR_L4DPIM_Pos                      (21U)
+#define ETH_MACL3L4CR_L4DPIM_Msk                      (0x1UL << ETH_MACL3L4CR_L4DPIM_Pos) /*!< 0x00200000 */
+#define ETH_MACL3L4CR_L4DPIM                          ETH_MACL3L4CR_L4DPIM_Msk /* Layer 4 Destination Port Inverse Match Enable */
+#define ETH_MACL3L4CR_L4DPM_Pos                       (20U)
+#define ETH_MACL3L4CR_L4DPM_Msk                       (0x1UL << ETH_MACL3L4CR_L4DPM_Pos) /*!< 0x00100000 */
+#define ETH_MACL3L4CR_L4DPM                           ETH_MACL3L4CR_L4DPM_Msk  /* Layer 4 Destination Port Match Enable */
+#define ETH_MACL3L4CR_L4SPIM_Pos                      (19U)
+#define ETH_MACL3L4CR_L4SPIM_Msk                      (0x1UL << ETH_MACL3L4CR_L4SPIM_Pos) /*!< 0x00080000 */
+#define ETH_MACL3L4CR_L4SPIM                          ETH_MACL3L4CR_L4SPIM_Msk /* Layer 4 Source Port Inverse Match Enable */
+#define ETH_MACL3L4CR_L4SPM_Pos                       (18U)
+#define ETH_MACL3L4CR_L4SPM_Msk                       (0x1UL << ETH_MACL3L4CR_L4SPM_Pos) /*!< 0x00040000 */
+#define ETH_MACL3L4CR_L4SPM                           ETH_MACL3L4CR_L4SPM_Msk  /* Layer 4 Source Port Match Enable */
+#define ETH_MACL3L4CR_L4PEN_Pos                       (16U)
+#define ETH_MACL3L4CR_L4PEN_Msk                       (0x1UL << ETH_MACL3L4CR_L4PEN_Pos) /*!< 0x00010000 */
+#define ETH_MACL3L4CR_L4PEN                           ETH_MACL3L4CR_L4PEN_Msk  /* Layer 4 Protocol Enable */
+#define ETH_MACL3L4CR_L3HDBM_Pos                      (11U)
+#define ETH_MACL3L4CR_L3HDBM_Msk                      (0x1FUL << ETH_MACL3L4CR_L3HDBM_Pos) /*!< 0x0000F800 */
+#define ETH_MACL3L4CR_L3HDBM                          ETH_MACL3L4CR_L3HDBM_Msk /* Layer 3 IP DA Higher Bits Match */
+#define ETH_MACL3L4CR_L3HSBM_Pos                      (6U)
+#define ETH_MACL3L4CR_L3HSBM_Msk                      (0x1FUL << ETH_MACL3L4CR_L3HSBM_Pos) /*!< 0x000007C0 */
+#define ETH_MACL3L4CR_L3HSBM                          ETH_MACL3L4CR_L3HSBM_Msk /* Layer 3 IP SA Higher Bits Match */
+#define ETH_MACL3L4CR_L3DAIM_Pos                      (5U)
+#define ETH_MACL3L4CR_L3DAIM_Msk                      (0x1UL << ETH_MACL3L4CR_L3DAIM_Pos) /*!< 0x00000020 */
+#define ETH_MACL3L4CR_L3DAIM                          ETH_MACL3L4CR_L3DAIM_Msk /* Layer 3 IP DA Inverse Match Enable */
+#define ETH_MACL3L4CR_L3DAM_Pos                       (4U)
+#define ETH_MACL3L4CR_L3DAM_Msk                       (0x1UL << ETH_MACL3L4CR_L3DAM_Pos) /*!< 0x00000010 */
+#define ETH_MACL3L4CR_L3DAM                           ETH_MACL3L4CR_L3DAM_Msk  /* Layer 3 IP DA Match Enable */
+#define ETH_MACL3L4CR_L3SAIM_Pos                      (3U)
+#define ETH_MACL3L4CR_L3SAIM_Msk                      (0x1UL << ETH_MACL3L4CR_L3SAIM_Pos) /*!< 0x00000008 */
+#define ETH_MACL3L4CR_L3SAIM                          ETH_MACL3L4CR_L3SAIM_Msk /* Layer 3 IP SA Inverse Match Enable */
+#define ETH_MACL3L4CR_L3SAM_Pos                       (2U)
+#define ETH_MACL3L4CR_L3SAM_Msk                       (0x1UL << ETH_MACL3L4CR_L3SAM_Pos) /*!< 0x00000004 */
+#define ETH_MACL3L4CR_L3SAM                           ETH_MACL3L4CR_L3SAM_Msk  /* Layer 3 IP SA Match Enable*/
+#define ETH_MACL3L4CR_L3PEN_Pos                       (0U)
+#define ETH_MACL3L4CR_L3PEN_Msk                       (0x1UL << ETH_MACL3L4CR_L3PEN_Pos) /*!< 0x00000001 */
+#define ETH_MACL3L4CR_L3PEN                           ETH_MACL3L4CR_L3PEN_Msk  /* Layer 3 Protocol Enable */
+
+/* Bit definition for Ethernet MAC L4 Address Register */
+#define ETH_MACL4AR_L4DP_Pos                          (16U)
+#define ETH_MACL4AR_L4DP_Msk                          (0xFFFFUL << ETH_MACL4AR_L4DP_Pos) /*!< 0xFFFF0000 */
+#define ETH_MACL4AR_L4DP                              ETH_MACL4AR_L4DP_Msk     /* Layer 4 Destination Port Number Field */
+#define ETH_MACL4AR_L4SP_Pos                          (0U)
+#define ETH_MACL4AR_L4SP_Msk                          (0xFFFFUL << ETH_MACL4AR_L4SP_Pos) /*!< 0x0000FFFF */
+#define ETH_MACL4AR_L4SP                              ETH_MACL4AR_L4SP_Msk     /* Layer 4 Source Port Number Field */
+
+/* Bit definition for Ethernet MAC L3 Address0 Register */
+#define ETH_MACL3A0R_L3A0_Pos                         (0U)
+#define ETH_MACL3A0R_L3A0_Msk                         (0xFFFFFFFFUL << ETH_MACL3A0R_L3A0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A0R_L3A0                             ETH_MACL3A0R_L3A0_Msk    /* Layer 3 Address 0 Field */
+
+/* Bit definition for Ethernet MAC L4 Address1 Register */
+#define ETH_MACL3A1R_L3A1_Pos                         (0U)
+#define ETH_MACL3A1R_L3A1_Msk                         (0xFFFFFFFFUL << ETH_MACL3A1R_L3A1_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A1R_L3A1                             ETH_MACL3A1R_L3A1_Msk    /* Layer 3 Address 1 Field */
+
+/* Bit definition for Ethernet MAC L4 Address2 Register */
+#define ETH_MACL3A2R_L3A2_Pos                         (0U)
+#define ETH_MACL3A2R_L3A2_Msk                         (0xFFFFFFFFUL << ETH_MACL3A2R_L3A2_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A2R_L3A2                             ETH_MACL3A2R_L3A2_Msk    /* Layer 3 Address 2 Field */
+
+/* Bit definition for Ethernet MAC L4 Address3 Register */
+#define ETH_MACL3A3R_L3A3_Pos                         (0U)
+#define ETH_MACL3A3R_L3A3_Msk                         (0xFFFFFFFFUL << ETH_MACL3A3R_L3A3_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A3R_L3A3                             ETH_MACL3A3R_L3A3_Msk    /* Layer 3 Address 3 Field */
+
+/* Bit definition for Ethernet MAC Timestamp Control Register */
+#define ETH_MACTSCR_TXTSSTSM_Pos                      (24U)
+#define ETH_MACTSCR_TXTSSTSM_Msk                      (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */
+#define ETH_MACTSCR_TXTSSTSM                          ETH_MACTSCR_TXTSSTSM_Msk  /* Transmit Timestamp Status Mode */
+#define ETH_MACTSCR_CSC_Pos                           (19U)
+#define ETH_MACTSCR_CSC_Msk                           (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */
+#define ETH_MACTSCR_CSC                               ETH_MACTSCR_CSC_Msk  /* Enable checksum correction during OST for PTP over UDP/IPv4 packets */
+#define ETH_MACTSCR_TSENMACADDR_Pos                   (18U)
+#define ETH_MACTSCR_TSENMACADDR_Msk                   (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */
+#define ETH_MACTSCR_TSENMACADDR                       ETH_MACTSCR_TSENMACADDR_Msk  /* Enable MAC Address for PTP Packet Filtering */
+#define ETH_MACTSCR_SNAPTYPSEL_Pos                    (16U)
+#define ETH_MACTSCR_SNAPTYPSEL_Msk                    (0x3UL << ETH_MACTSCR_SNAPTYPSEL_Pos) /*!< 0x00030000 */
+#define ETH_MACTSCR_SNAPTYPSEL                        ETH_MACTSCR_SNAPTYPSEL_Msk  /* Select PTP packets for Taking Snapshots */
+#define ETH_MACTSCR_TSMSTRENA_Pos                     (15U)
+#define ETH_MACTSCR_TSMSTRENA_Msk                     (0x1UL << ETH_MACTSCR_TSMSTRENA_Pos) /*!< 0x00008000 */
+#define ETH_MACTSCR_TSMSTRENA                         ETH_MACTSCR_TSMSTRENA_Msk  /* Enable Snapshot for Messages Relevant to Master */
+#define ETH_MACTSCR_TSEVNTENA_Pos                     (14U)
+#define ETH_MACTSCR_TSEVNTENA_Msk                     (0x1UL << ETH_MACTSCR_TSEVNTENA_Pos) /*!< 0x00004000 */
+#define ETH_MACTSCR_TSEVNTENA                         ETH_MACTSCR_TSEVNTENA_Msk  /* Enable Timestamp Snapshot for Event Messages */
+#define ETH_MACTSCR_TSIPV4ENA_Pos                     (13U)
+#define ETH_MACTSCR_TSIPV4ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV4ENA_Pos) /*!< 0x00002000 */
+#define ETH_MACTSCR_TSIPV4ENA                         ETH_MACTSCR_TSIPV4ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv4-UDP */
+#define ETH_MACTSCR_TSIPV6ENA_Pos                     (12U)
+#define ETH_MACTSCR_TSIPV6ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV6ENA_Pos) /*!< 0x00001000 */
+#define ETH_MACTSCR_TSIPV6ENA                         ETH_MACTSCR_TSIPV6ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv6-UDP */
+#define ETH_MACTSCR_TSIPENA_Pos                       (11U)
+#define ETH_MACTSCR_TSIPENA_Msk                       (0x1UL << ETH_MACTSCR_TSIPENA_Pos) /*!< 0x00000800 */
+#define ETH_MACTSCR_TSIPENA                           ETH_MACTSCR_TSIPENA_Msk  /* Enable Processing of PTP over Ethernet Packets */
+#define ETH_MACTSCR_TSVER2ENA_Pos                     (10U)
+#define ETH_MACTSCR_TSVER2ENA_Msk                     (0x1UL << ETH_MACTSCR_TSVER2ENA_Pos) /*!< 0x00000400 */
+#define ETH_MACTSCR_TSVER2ENA                         ETH_MACTSCR_TSVER2ENA_Msk  /* Enable PTP Packet Processing for Version 2 Format */
+#define ETH_MACTSCR_TSCTRLSSR_Pos                     (9U)
+#define ETH_MACTSCR_TSCTRLSSR_Msk                     (0x1UL << ETH_MACTSCR_TSCTRLSSR_Pos) /*!< 0x00000200 */
+#define ETH_MACTSCR_TSCTRLSSR                         ETH_MACTSCR_TSCTRLSSR_Msk  /* Timestamp Digital or Binary Rollover Control */
+#define ETH_MACTSCR_TSENALL_Pos                       (8U)
+#define ETH_MACTSCR_TSENALL_Msk                       (0x1UL << ETH_MACTSCR_TSENALL_Pos) /*!< 0x00000100 */
+#define ETH_MACTSCR_TSENALL                           ETH_MACTSCR_TSENALL_Msk  /* Enable Timestamp for All Packets */
+#define ETH_MACTSCR_TSADDREG_Pos                      (5U)
+#define ETH_MACTSCR_TSADDREG_Msk                      (0x1UL << ETH_MACTSCR_TSADDREG_Pos) /*!< 0x00000020 */
+#define ETH_MACTSCR_TSADDREG                          ETH_MACTSCR_TSADDREG_Msk  /* Update Addend Register */
+#define ETH_MACTSCR_TSUPDT_Pos                        (3U)
+#define ETH_MACTSCR_TSUPDT_Msk                        (0x1UL << ETH_MACTSCR_TSUPDT_Pos) /*!< 0x00000008 */
+#define ETH_MACTSCR_TSUPDT                            ETH_MACTSCR_TSUPDT_Msk  /* Update Timestamp */
+#define ETH_MACTSCR_TSINIT_Pos                        (2U)
+#define ETH_MACTSCR_TSINIT_Msk                        (0x1UL << ETH_MACTSCR_TSINIT_Pos) /*!< 0x00000004 */
+#define ETH_MACTSCR_TSINIT                             ETH_MACTSCR_TSINIT_Msk  /* Initialize Timestamp */
+#define ETH_MACTSCR_TSCFUPDT_Pos                      (1U)
+#define ETH_MACTSCR_TSCFUPDT_Msk                      (0x1UL << ETH_MACTSCR_TSCFUPDT_Pos) /*!< 0x00000002 */
+#define ETH_MACTSCR_TSCFUPDT                          ETH_MACTSCR_TSCFUPDT_Msk  /* Fine or Coarse Timestamp Update*/
+#define ETH_MACTSCR_TSENA_Pos                         (0U)
+#define ETH_MACTSCR_TSENA_Msk                         (0x1UL << ETH_MACTSCR_TSENA_Pos) /*!< 0x00000001 */
+#define ETH_MACTSCR_TSENA                             ETH_MACTSCR_TSENA_Msk  /* Enable Timestamp */
+
+/* Bit definition for Ethernet MAC Sub-second Increment Register */
+#define ETH_MACMACSSIR_SSINC_Pos                      (16U)
+#define ETH_MACMACSSIR_SSINC_Msk                      (0xFFUL << ETH_MACMACSSIR_SSINC_Pos) /*!< 0x0000FF00 */
+#define ETH_MACMACSSIR_SSINC                          ETH_MACMACSSIR_SSINC_Msk  /* Sub-second Increment Value */
+#define ETH_MACMACSSIR_SNSINC_Pos                     (8U)
+#define ETH_MACMACSSIR_SNSINC_Msk                     (0xFFUL << ETH_MACMACSSIR_SNSINC_Pos) /*!< 0x000000FF */
+#define ETH_MACMACSSIR_SNSINC                         ETH_MACMACSSIR_SNSINC_Msk  /* Sub-nanosecond Increment Value */
+
+/* Bit definition for Ethernet MAC System Time Seconds Register */
+#define ETH_MACSTSR_TSS_Pos                           (0U)
+#define ETH_MACSTSR_TSS_Msk                           (0xFFFFFFFFUL << ETH_MACSTSR_TSS_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACSTSR_TSS                               ETH_MACSTSR_TSS_Msk  /* Timestamp Second */
+
+/* Bit definition for Ethernet MAC System Time Nanoseconds Register */
+#define ETH_MACSTNR_TSSS_Pos                          (0U)
+#define ETH_MACSTNR_TSSS_Msk                          (0x7FFFFFFFUL << ETH_MACSTNR_TSSS_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACSTNR_TSSS                              ETH_MACSTNR_TSSS_Msk  /* Timestamp Sub-seconds */
+
+/* Bit definition for Ethernet MAC System Time Seconds Update Register */
+#define ETH_MACSTSUR_TSS_Pos                          (0U)
+#define ETH_MACSTSUR_TSS_Msk                          (0xFFFFFFFFUL << ETH_MACSTSUR_TSS_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACSTSUR_TSS                              ETH_MACSTSUR_TSS_Msk  /* Timestamp Seconds */
+
+/* Bit definition for Ethernet MAC System Time Nanoseconds Update Register */
+#define ETH_MACSTNUR_ADDSUB_Pos                       (31U)
+#define ETH_MACSTNUR_ADDSUB_Msk                       (0x1UL << ETH_MACSTNUR_ADDSUB_Pos) /*!< 0x80000000 */
+#define ETH_MACSTNUR_ADDSUB                           ETH_MACSTNUR_ADDSUB_Msk  /* Add or Subtract Time */
+#define ETH_MACSTNUR_TSSS_Pos                         (0U)
+#define ETH_MACSTNUR_TSSS_Msk                         (0x7FFFFFFFUL << ETH_MACSTNUR_TSSS_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACSTNUR_TSSS                             ETH_MACSTNUR_TSSS_Msk  /* Timestamp Sub-seconds */
+
+/* Bit definition for Ethernet MAC Timestamp Addend Register */
+#define ETH_MACTSAR_TSAR_Pos                          (0U)
+#define ETH_MACTSAR_TSAR_Msk                          (0xFFFFFFFFUL << ETH_MACTSAR_TSAR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSAR_TSAR                              ETH_MACTSAR_TSAR_Msk  /* Timestamp Addend Register */
+
+/* Bit definition for Ethernet MAC Timestamp Status Register */
+#define ETH_MACTSSR_ATSNS_Pos                         (25U)
+#define ETH_MACTSSR_ATSNS_Msk                         (0x1FUL << ETH_MACTSSR_ATSNS_Pos) /*!< 0x3E000000 */
+#define ETH_MACTSSR_ATSNS                             ETH_MACTSSR_ATSNS_Msk  /* Number of Auxiliary Timestamp Snapshots */
+#define ETH_MACTSSR_ATSSTM_Pos                        (24U)
+#define ETH_MACTSSR_ATSSTM_Msk                        (0x1UL << ETH_MACTSSR_ATSSTM_Pos) /*!< 0x01000000 */
+#define ETH_MACTSSR_ATSSTM                            ETH_MACTSSR_ATSSTM_Msk  /* Auxiliary Timestamp Snapshot Trigger Missed */
+#define ETH_MACTSSR_ATSSTN_Pos                        (16U)
+#define ETH_MACTSSR_ATSSTN_Msk                        (0xFUL << ETH_MACTSSR_ATSSTN_Pos) /*!< 0x000F0000 */
+#define ETH_MACTSSR_ATSSTN                            ETH_MACTSSR_ATSSTN_Msk  /* Auxiliary Timestamp Snapshot Trigger Identifier */
+#define ETH_MACTSSR_TXTSSIS_Pos                       (15U)
+#define ETH_MACTSSR_TXTSSIS_Msk                       (0x1UL << ETH_MACTSSR_TXTSSIS_Pos) /*!< 0x00008000 */
+#define ETH_MACTSSR_TXTSSIS                           ETH_MACTSSR_TXTSSIS_Msk  /* Tx Timestamp Status Interrupt Status */
+#define ETH_MACTSSR_TSTRGTERR0_Pos                    (3U)
+#define ETH_MACTSSR_TSTRGTERR0_Msk                    (0x1UL << ETH_MACTSSR_TSTRGTERR0_Pos) /*!< 0x00000008 */
+#define ETH_MACTSSR_TSTRGTERR0                        ETH_MACTSSR_TSTRGTERR0_Msk  /* Timestamp Target Time Error */
+#define ETH_MACTSSR_AUXTSTRIG_Pos                     (2U)
+#define ETH_MACTSSR_AUXTSTRIG_Msk                     (0x1UL << ETH_MACTSSR_AUXTSTRIG_Pos) /*!< 0x00000004 */
+#define ETH_MACTSSR_AUXTSTRIG                         ETH_MACTSSR_AUXTSTRIG_Msk  /* Auxiliary Timestamp Trigger Snapshot*/
+#define ETH_MACTSSR_TSTARGT0_Pos                      (1U)
+#define ETH_MACTSSR_TSTARGT0_Msk                      (0x1UL << ETH_MACTSSR_TSTARGT0_Pos) /*!< 0x00000002 */
+#define ETH_MACTSSR_TSTARGT0                          ETH_MACTSSR_TSTARGT0_Msk  /* Timestamp Target Time Reached */
+#define ETH_MACTSSR_TSSOVF_Pos                        (0U)
+#define ETH_MACTSSR_TSSOVF_Msk                        (0x1UL << ETH_MACTSSR_TSSOVF_Pos) /*!< 0x00000001 */
+#define ETH_MACTSSR_TSSOVF                            ETH_MACTSSR_TSSOVF_Msk  /* Timestamp Seconds Overflow */
+
+/* Bit definition for Ethernet MAC Tx Timestamp Status Nanoseconds Register */
+#define ETH_MACTTSSNR_TXTSSMIS_Pos                    (31U)
+#define ETH_MACTTSSNR_TXTSSMIS_Msk                    (0x1UL << ETH_MACTTSSNR_TXTSSMIS_Pos) /*!< 0x80000000 */
+#define ETH_MACTTSSNR_TXTSSMIS                        ETH_MACTTSSNR_TXTSSMIS_Msk  /* Transmit Timestamp Status Missed */
+#define ETH_MACTTSSNR_TXTSSLO_Pos                     (0U)
+#define ETH_MACTTSSNR_TXTSSLO_Msk                     (0x7FFFFFFFUL << ETH_MACTTSSNR_TXTSSLO_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACTTSSNR_TXTSSLO                         ETH_MACTTSSNR_TXTSSLO_Msk  /* Transmit Timestamp Status Low */
+
+/* Bit definition for Ethernet MAC Tx Timestamp Status Seconds Register */
+#define ETH_MACTTSSSR_TXTSSHI_Pos                     (0U)
+#define ETH_MACTTSSSR_TXTSSHI_Msk                     (0xFFFFFFFFUL << ETH_MACTTSSSR_TXTSSHI_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTTSSSR_TXTSSHI                         ETH_MACTTSSSR_TXTSSHI_Msk  /* Transmit Timestamp Status High */
+
+/* Bit definition for Ethernet MAC Auxiliary Control Register*/
+#define ETH_MACACR_ATSEN3_Pos                         (7U)
+#define ETH_MACACR_ATSEN3_Msk                         (0x1UL << ETH_MACACR_ATSEN3_Pos) /*!< 0x00000080 */
+#define ETH_MACACR_ATSEN3                             ETH_MACACR_ATSEN3_Msk  /* Auxiliary Snapshot 3 Enable */
+#define ETH_MACACR_ATSEN2_Pos                         (6U)
+#define ETH_MACACR_ATSEN2_Msk                         (0x1UL << ETH_MACACR_ATSEN2_Pos) /*!< 0x00000040 */
+#define ETH_MACACR_ATSEN2                             ETH_MACACR_ATSEN2_Msk  /* Auxiliary Snapshot 2 Enable */
+#define ETH_MACACR_ATSEN1_Pos                         (5U)
+#define ETH_MACACR_ATSEN1_Msk                         (0x1UL << ETH_MACACR_ATSEN1_Pos) /*!< 0x00000020 */
+#define ETH_MACACR_ATSEN1                             ETH_MACACR_ATSEN1_Msk  /* Auxiliary Snapshot 1 Enable */
+#define ETH_MACACR_ATSEN0_Pos                         (4U)
+#define ETH_MACACR_ATSEN0_Msk                         (0x1UL << ETH_MACACR_ATSEN0_Pos) /*!< 0x00000010 */
+#define ETH_MACACR_ATSEN0                             ETH_MACACR_ATSEN0_Msk  /* Auxiliary Snapshot 0 Enable */
+#define ETH_MACACR_ATSFC_Pos                          (0U)
+#define ETH_MACACR_ATSFC_Msk                          (0x1UL << ETH_MACACR_ATSFC_Pos) /*!< 0x00000001 */
+#define ETH_MACACR_ATSFC                              ETH_MACACR_ATSFC_Msk  /* Auxiliary Snapshot FIFO Clear */
+
+/* Bit definition for Ethernet MAC Auxiliary Timestamp Nanoseconds Register */
+#define ETH_MACATSNR_AUXTSLO_Pos                      (0U)
+#define ETH_MACATSNR_AUXTSLO_Msk                      (0x7FFFFFFFUL << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACATSNR_AUXTSLO                          ETH_MACATSNR_AUXTSLO_Msk  /* Auxiliary Timestamp */
+
+/* Bit definition for Ethernet MAC Auxiliary Timestamp Seconds Register */
+#define ETH_MACATSSR_AUXTSHI_Pos                      (0U)
+#define ETH_MACATSSR_AUXTSHI_Msk                      (0xFFFFFFFFUL << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACATSSR_AUXTSHI                          ETH_MACATSSR_AUXTSHI_Msk  /* Auxiliary Timestamp */
+
+/* Bit definition for Ethernet MAC Timestamp Ingress Asymmetric Correction Register */
+#define ETH_MACTSIACR_OSTIAC_Pos                      (0U)
+#define ETH_MACTSIACR_OSTIAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSIACR_OSTIAC                          ETH_MACTSIACR_OSTIAC_Msk  /* One-Step Timestamp Ingress Asymmetry Correction */
+
+/* Bit definition for Ethernet MAC Timestamp Egress Asymmetric Correction Register */
+#define ETH_MACTSEACR_OSTEAC_Pos                      (0U)
+#define ETH_MACTSEACR_OSTEAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSEACR_OSTEAC                          ETH_MACTSEACR_OSTEAC_Msk  /* One-Step Timestamp Egress Asymmetry Correction */
+
+/* Bit definition for Ethernet MAC Timestamp Ingress Correction Nanosecond Register */
+#define ETH_MACTSICNR_TSIC_Pos                        (0U)
+#define ETH_MACTSICNR_TSIC_Msk                        (0xFFFFFFFFUL << ETH_MACTSICNR_TSIC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSICNR_TSIC                            ETH_MACTSICNR_TSIC_Msk  /* Timestamp Ingress Correction */
+
+/* Bit definition for Ethernet MAC Timestamp Egress correction Nanosecond Register */
+#define ETH_MACTSECNR_TSEC_Pos                        (0U)
+#define ETH_MACTSECNR_TSEC_Msk                        (0xFFFFFFFFUL << ETH_MACTSECNR_TSEC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSECNR_TSEC                            ETH_MACTSECNR_TSEC_Msk  /* Timestamp Egress Correction */
+
+/* Bit definition for Ethernet MAC PPS Control Register */
+#define ETH_MACPPSCR_TRGTMODSEL0_Pos                  (5U)
+#define ETH_MACPPSCR_TRGTMODSEL0_Msk                  (0x3UL << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000060 */
+#define ETH_MACPPSCR_TRGTMODSEL0                      ETH_MACPPSCR_TRGTMODSEL0_Msk  /* Target Time Register Mode for PPS Output */
+#define ETH_MACPPSCR_PPSEN0_Pos                       (4U)
+#define ETH_MACPPSCR_PPSEN0_Msk                       (0x1UL << ETH_MACPPSCR_PPSEN0_Pos) /*!< 0x00000010 */
+#define ETH_MACPPSCR_PPSEN0                           ETH_MACPPSCR_PPSEN0_Msk  /* Flexible PPS Output Mode Enable */
+#define ETH_MACPPSCR_PPSCTRL_Pos                      (0U)
+#define ETH_MACPPSCR_PPSCTRL_Msk                      (0xFUL << ETH_MACPPSCR_PPSCTRL_Pos) /*!< 0x0000000F */
+#define ETH_MACPPSCR_PPSCTRL                          ETH_MACPPSCR_PPSCTRL_Msk  /* PPS Output Frequency Control */
+
+/* Bit definition for Ethernet MAC PPS Target Time Seconds Register */
+#define ETH_MACPPSTTSR_TSTRH0_Pos                     (0U)
+#define ETH_MACPPSTTSR_TSTRH0_Msk                     (0xFFFFFFFFUL << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACPPSTTSR_TSTRH0                         ETH_MACPPSTTSR_TSTRH0_Msk  /* PPS Target Time Seconds Register */
+
+/* Bit definition for Ethernet MAC PPS Target Time Nanoseconds Register */
+#define ETH_MACPPSTTNR_TRGTBUSY0_Pos                  (31U)
+#define ETH_MACPPSTTNR_TRGTBUSY0_Msk                  (0x1UL << ETH_MACPPSTTNR_TRGTBUSY0_Pos) /*!< 0x80000000 */
+#define ETH_MACPPSTTNR_TRGTBUSY0                      ETH_MACPPSTTNR_TRGTBUSY0_Msk  /* PPS Target Time Register Busy */
+#define ETH_MACPPSTTNR_TTSL0_Pos                      (0U)
+#define ETH_MACPPSTTNR_TTSL0_Msk                      (0x7FFFFFFFUL << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACPPSTTNR_TTSL0                          ETH_MACPPSTTNR_TTSL0_Msk  /* Target Time Low for PPS Register */
+
+/* Bit definition for Ethernet MAC PPS Interval Register */
+#define ETH_MACPPSIR_PPSINT0_Pos                      (0U)
+#define ETH_MACPPSIR_PPSINT0_Msk                      (0xFFFFFFFFUL << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACPPSIR_PPSINT0                          ETH_MACPPSIR_PPSINT0_Msk  /* PPS Output Signal Interval */
+
+/* Bit definition for Ethernet MAC PPS Width Register */
+#define ETH_MACPPSWR_PPSWIDTH0_Pos                    (0U)
+#define ETH_MACPPSWR_PPSWIDTH0_Msk                    (0xFFFFFFFFUL << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACPPSWR_PPSWIDTH0                        ETH_MACPPSWR_PPSWIDTH0_Msk  /* PPS Output Signal Width */
+
+/* Bit definition for Ethernet MAC PTP Offload Control Register */
+#define ETH_MACPOCR_DN_Pos                            (8U)
+#define ETH_MACPOCR_DN_Msk                            (0xFFUL << ETH_MACPOCR_DN_Pos) /*!< 0x0000FF00 */
+#define ETH_MACPOCR_DN                                ETH_MACPOCR_DN_Msk  /* Domain Number */
+#define ETH_MACPOCR_DRRDIS_Pos                        (6U)
+#define ETH_MACPOCR_DRRDIS_Msk                        (0x1UL << ETH_MACPOCR_DRRDIS_Pos) /*!< 0x00000040 */
+#define ETH_MACPOCR_DRRDIS                            ETH_MACPOCR_DRRDIS_Msk  /* Disable PTO Delay Request/Response response generation */
+#define ETH_MACPOCR_APDREQTRIG_Pos                    (5U)
+#define ETH_MACPOCR_APDREQTRIG_Msk                    (0x1UL << ETH_MACPOCR_APDREQTRIG_Pos) /*!< 0x00000020 */
+#define ETH_MACPOCR_APDREQTRIG                        ETH_MACPOCR_APDREQTRIG_Msk  /* Automatic PTP Pdelay_Req message Trigger */
+#define ETH_MACPOCR_ASYNCTRIG_Pos                     (4U)
+#define ETH_MACPOCR_ASYNCTRIG_Msk                     (0x1UL << ETH_MACPOCR_ASYNCTRIG_Pos) /*!< 0x00000010 */
+#define ETH_MACPOCR_ASYNCTRIG                         ETH_MACPOCR_ASYNCTRIG_Msk  /* Automatic PTP SYNC message Trigger */
+#define ETH_MACPOCR_APDREQEN_Pos                      (2U)
+#define ETH_MACPOCR_APDREQEN_Msk                      (0x1UL << ETH_MACPOCR_APDREQEN_Pos) /*!< 0x00000004 */
+#define ETH_MACPOCR_APDREQEN                          ETH_MACPOCR_APDREQEN_Msk  /* Automatic PTP Pdelay_Req message Enable */
+#define ETH_MACPOCR_ASYNCEN_Pos                       (1U)
+#define ETH_MACPOCR_ASYNCEN_Msk                       (0x1UL << ETH_MACPOCR_ASYNCEN_Pos) /*!< 0x00000002 */
+#define ETH_MACPOCR_ASYNCEN                           ETH_MACPOCR_ASYNCEN_Msk  /* Automatic PTP SYNC message Enable */
+#define ETH_MACPOCR_PTOEN_Pos                         (0U)
+#define ETH_MACPOCR_PTOEN_Msk                         (0x1UL << ETH_MACPOCR_PTOEN_Pos) /*!< 0x00000001 */
+#define ETH_MACPOCR_PTOEN                             ETH_MACPOCR_PTOEN_Msk  /* PTP Offload Enable */
+
+/* Bit definition for Ethernet MAC PTP Source Port Identity 0 Register */
+#define ETH_MACSPI0R_SPI0_Pos                         (0U)
+#define ETH_MACSPI0R_SPI0_Msk                         (0xFFFFFFFFUL << ETH_MACSPI0R_SPI0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACSPI0R_SPI0                             ETH_MACSPI0R_SPI0_Msk  /* Source Port Identity 0 */
+
+/* Bit definition for Ethernet MAC PTP Source Port Identity 1 Register */
+#define ETH_MACSPI1R_SPI1_Pos                         (0U)
+#define ETH_MACSPI1R_SPI1_Msk                         (0xFFFFFFFFUL << ETH_MACSPI1R_SPI1_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACSPI1R_SPI1                             ETH_MACSPI1R_SPI1_Msk  /* Source Port Identity 1 */
+
+/* Bit definition for Ethernet MAC PTP Source Port Identity 2 Register */
+#define ETH_MACSPI2R_SPI2_Pos                         (0U)
+#define ETH_MACSPI2R_SPI2_Msk                         (0xFFFFUL << ETH_MACSPI2R_SPI2_Pos) /*!< 0x0000FFFF */
+#define ETH_MACSPI2R_SPI2                             ETH_MACSPI2R_SPI2_Msk  /* Source Port Identity 2 */
+
+/* Bit definition for Ethernet MAC Log Message Interval Register */
+#define ETH_MACLMIR_LMPDRI_Pos                        (24U)
+#define ETH_MACLMIR_LMPDRI_Msk                        (0xFFUL << ETH_MACLMIR_LMPDRI_Pos) /*!< 0xFF000000 */
+#define ETH_MACLMIR_LMPDRI                             ETH_MACLMIR_LMPDRI_Msk  /* Log Min Pdelay_Req Interval */
+#define ETH_MACLMIR_DRSYNCR_Pos                       (8U)
+#define ETH_MACLMIR_DRSYNCR_Msk                       (0x7UL << ETH_MACLMIR_DRSYNCR_Pos) /*!< 0x00000700 */
+#define ETH_MACLMIR_DRSYNCR                           ETH_MACLMIR_DRSYNCR_Msk  /* Delay_Req to SYNC Ratio */
+#define ETH_MACLMIR_LSI_Pos                           (0U)
+#define ETH_MACLMIR_LSI_Msk                           (0xFFUL << ETH_MACLMIR_LSI_Pos) /*!< 0x000000FF */
+#define ETH_MACLMIR_LSI                               ETH_MACLMIR_LSI_Msk  /* Log Sync Interval */
+
+/* Bit definition for Ethernet MTL Operation Mode Register */
+#define ETH_MTLOMR_CNTCLR_Pos                         (9U)
+#define ETH_MTLOMR_CNTCLR_Msk                         (0x1UL << ETH_MTLOMR_CNTCLR_Pos) /*!< 0x00000200 */
+#define ETH_MTLOMR_CNTCLR                             ETH_MTLOMR_CNTCLR_Msk    /* Counters Reset */
+#define ETH_MTLOMR_CNTPRST_Pos                        (8U)
+#define ETH_MTLOMR_CNTPRST_Msk                        (0x1UL << ETH_MTLOMR_CNTPRST_Pos) /*!< 0x00000100 */
+#define ETH_MTLOMR_CNTPRST                            ETH_MTLOMR_CNTPRST_Msk   /* Counters Preset */
+#define ETH_MTLOMR_DTXSTS_Pos                         (1U)
+#define ETH_MTLOMR_DTXSTS_Msk                         (0x1UL << ETH_MTLOMR_DTXSTS_Pos) /*!< 0x00000002 */
+#define ETH_MTLOMR_DTXSTS                             ETH_MTLOMR_DTXSTS_Msk  /* Drop Transmit Status */
+
+/* Bit definition for Ethernet MTL Interrupt Status Register */
+#define ETH_MTLISR_MACIS_Pos                          (16U)
+#define ETH_MTLISR_MACIS_Msk                          (0x1UL << ETH_MTLISR_MACIS_Pos) /*!< 0x00010000 */
+#define ETH_MTLISR_MACIS                              ETH_MTLISR_MACIS_Msk     /* MAC Interrupt Status */
+#define ETH_MTLISR_QIS_Pos                            (0U)
+#define ETH_MTLISR_QIS_Msk                            (0x1UL << ETH_MTLISR_QIS_Pos) /*!< 0x00000001 */
+#define ETH_MTLISR_QIS                                ETH_MTLISR_QIS_Msk       /* Queue Interrupt status */
+
+/* Bit definition for Ethernet MTL Tx Queue Operation Mode Register */
+#define ETH_MTLTQOMR_TTC_Pos                          (4U)
+#define ETH_MTLTQOMR_TTC_Msk                          (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */
+#define ETH_MTLTQOMR_TTC                              ETH_MTLTQOMR_TTC_Msk     /* Transmit Threshold Control */
+#define ETH_MTLTQOMR_TTC_32BITS                       ((uint32_t)0x00000000)   /* 32 bits Threshold */
+#define ETH_MTLTQOMR_TTC_64BITS                       ((uint32_t)0x00000010)   /* 64  bits Threshold */
+#define ETH_MTLTQOMR_TTC_96BITS                       ((uint32_t)0x00000020)   /* 96 bits Threshold */
+#define ETH_MTLTQOMR_TTC_128BITS                      ((uint32_t)0x00000030)   /* 128 bits Threshold */
+#define ETH_MTLTQOMR_TTC_192BITS                      ((uint32_t)0x00000040)   /* 192 bits Threshold */
+#define ETH_MTLTQOMR_TTC_256BITS                      ((uint32_t)0x00000050)   /* 256 bits Threshold */
+#define ETH_MTLTQOMR_TTC_384BITS                      ((uint32_t)0x00000060)   /* 384 bits Threshold */
+#define ETH_MTLTQOMR_TTC_512BITS                      ((uint32_t)0x00000070)   /* 512 bits Threshold */
+#define ETH_MTLTQOMR_TSF_Pos                          (1U)
+#define ETH_MTLTQOMR_TSF_Msk                          (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */
+#define ETH_MTLTQOMR_TSF                              ETH_MTLTQOMR_TSF_Msk     /* Transmit Store and Forward */
+#define ETH_MTLTQOMR_FTQ_Pos                          (0U)
+#define ETH_MTLTQOMR_FTQ_Msk                          (0x1UL << ETH_MTLTQOMR_FTQ_Pos) /*!< 0x00000001 */
+#define ETH_MTLTQOMR_FTQ                              ETH_MTLTQOMR_FTQ_Msk     /* Flush Transmit Queue */
+
+/* Bit definition for Ethernet MTL Tx Queue Underflow Register */
+#define ETH_MTLTQUR_UFCNTOVF_Pos                      (11U)
+#define ETH_MTLTQUR_UFCNTOVF_Msk                      (0x1UL << ETH_MTLTQUR_UFCNTOVF_Pos) /*!< 0x00000800 */
+#define ETH_MTLTQUR_UFCNTOVF                          ETH_MTLTQUR_UFCNTOVF_Msk /* Overflow Bit for Underflow Packet Counter */
+#define ETH_MTLTQUR_UFPKTCNT_Pos                      (0U)
+#define ETH_MTLTQUR_UFPKTCNT_Msk                      (0x7FFUL << ETH_MTLTQUR_UFPKTCNT_Pos) /*!< 0x000007FF */
+#define ETH_MTLTQUR_UFPKTCNT                          ETH_MTLTQUR_UFPKTCNT_Msk /* Underflow Packet Counter */
+
+/* Bit definition for Ethernet MTL Tx Queue Debug Register */
+#define ETH_MTLTQDR_STXSTSF_Pos                       (20U)
+#define ETH_MTLTQDR_STXSTSF_Msk                       (0x7UL << ETH_MTLTQDR_STXSTSF_Pos) /*!< 0x00700000 */
+#define ETH_MTLTQDR_STXSTSF                           ETH_MTLTQDR_STXSTSF_Msk  /* Number of Status Words in the Tx Status FIFO of Queue */
+#define ETH_MTLTQDR_PTXQ_Pos                          (16U)
+#define ETH_MTLTQDR_PTXQ_Msk                          (0x7UL << ETH_MTLTQDR_PTXQ_Pos) /*!< 0x00070000 */
+#define ETH_MTLTQDR_PTXQ                              ETH_MTLTQDR_PTXQ_Msk     /* Number of Packets in the Transmit Queue */
+#define ETH_MTLTQDR_TXSTSFSTS_Pos                     (5U)
+#define ETH_MTLTQDR_TXSTSFSTS_Msk                     (0x1UL << ETH_MTLTQDR_TXSTSFSTS_Pos) /*!< 0x00000020 */
+#define ETH_MTLTQDR_TXSTSFSTS                         ETH_MTLTQDR_TXSTSFSTS_Msk /* MTL Tx Status FIFO Full Status */
+#define ETH_MTLTQDR_TXQSTS_Pos                        (4U)
+#define ETH_MTLTQDR_TXQSTS_Msk                        (0x1UL << ETH_MTLTQDR_TXQSTS_Pos) /*!< 0x00000010 */
+#define ETH_MTLTQDR_TXQSTS                            ETH_MTLTQDR_TXQSTS_Msk   /* MTL Tx Queue Not Empty Status */
+#define ETH_MTLTQDR_TWCSTS_Pos                        (3U)
+#define ETH_MTLTQDR_TWCSTS_Msk                        (0x1UL << ETH_MTLTQDR_TWCSTS_Pos) /*!< 0x00000008 */
+#define ETH_MTLTQDR_TWCSTS                            ETH_MTLTQDR_TWCSTS_Msk   /* MTL Tx Queue Write Controller Status */
+#define ETH_MTLTQDR_TRCSTS_Pos                        (1U)
+#define ETH_MTLTQDR_TRCSTS_Msk                        (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */
+#define ETH_MTLTQDR_TRCSTS                            ETH_MTLTQDR_TRCSTS_Msk  /* MTL Tx Queue Read Controller Status */
+#define ETH_MTLTQDR_TRCSTS_IDLE                       ((uint32_t)0x00000000)  /* Idle state */
+#define ETH_MTLTQDR_TRCSTS_READ                       ((uint32_t)0x00000002)  /* Read state (transferring data to the MAC transmitter) */
+#define ETH_MTLTQDR_TRCSTS_WAITING                    ((uint32_t)0x00000004)  /* Waiting for pending Tx Status from the MAC transmitter */
+#define ETH_MTLTQDR_TRCSTS_FLUSHING                   ((uint32_t)0x00000006)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */
+#define ETH_MTLTQDR_TXQPAUSED_Pos                     (0U)
+#define ETH_MTLTQDR_TXQPAUSED_Msk                     (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */
+#define ETH_MTLTQDR_TXQPAUSED                         ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
+
+/* Bit definition for Ethernet MTL Queue Interrupt Control Status Register */
+#define ETH_MTLQICSR_RXOIE_Pos                        (24U)
+#define ETH_MTLQICSR_RXOIE_Msk                        (0x1UL << ETH_MTLQICSR_RXOIE_Pos) /*!< 0x01000000 */
+#define ETH_MTLQICSR_RXOIE                            ETH_MTLQICSR_RXOIE_Msk   /* Receive Queue Overflow Interrupt Enable */
+#define ETH_MTLQICSR_RXOVFIS_Pos                      (16U)
+#define ETH_MTLQICSR_RXOVFIS_Msk                      (0x1UL << ETH_MTLQICSR_RXOVFIS_Pos) /*!< 0x00010000 */
+#define ETH_MTLQICSR_RXOVFIS                          ETH_MTLQICSR_RXOVFIS_Msk /* Receive Queue Overflow Interrupt Status */
+#define ETH_MTLQICSR_TXUIE_Pos                        (8U)
+#define ETH_MTLQICSR_TXUIE_Msk                        (0x1UL << ETH_MTLQICSR_TXUIE_Pos) /*!< 0x00000100 */
+#define ETH_MTLQICSR_TXUIE                            ETH_MTLQICSR_TXUIE_Msk   /* Transmit Queue Underflow Interrupt Enable */
+#define ETH_MTLQICSR_TXUNFIS_Pos                      (0U)
+#define ETH_MTLQICSR_TXUNFIS_Msk                      (0x1UL << ETH_MTLQICSR_TXUNFIS_Pos) /*!< 0x00000001 */
+#define ETH_MTLQICSR_TXUNFIS                          ETH_MTLQICSR_TXUNFIS_Msk /* Transmit Queue Underflow Interrupt Status */
+
+/* Bit definition for Ethernet MTL Rx Queue Operation Mode Register */
+#define ETH_MTLRQOMR_RQS_Pos                          (20U)
+#define ETH_MTLRQOMR_RQS_Msk                          (0x7UL << ETH_MTLRQOMR_RQS_Pos) /*!< 0x00700000 */
+#define ETH_MTLRQOMR_RQS                              ETH_MTLRQOMR_RQS_Msk /* Receive Queue Size */
+#define ETH_MTLRQOMR_RFD_Pos                          (14U)
+#define ETH_MTLRQOMR_RFD_Msk                          (0x7UL << ETH_MTLRQOMR_RFD_Pos) /*!< 0x0001C000 */
+#define ETH_MTLRQOMR_RFD                              ETH_MTLRQOMR_RFD_Msk /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */
+#define ETH_MTLRQOMR_RFA_Pos                          (8U)
+#define ETH_MTLRQOMR_RFA_Msk                          (0x7UL << ETH_MTLRQOMR_RFA_Pos) /*!< 0x00000700 */
+#define ETH_MTLRQOMR_RFA                              ETH_MTLRQOMR_RFA_Msk /* Threshold for Activating Flow Control (in half-duplex and full-duplex */
+#define ETH_MTLRQOMR_EHFC_Pos                         (7U)
+#define ETH_MTLRQOMR_EHFC_Msk                         (0x1UL << ETH_MTLRQOMR_EHFC_Pos) /*!< 0x00000080 */
+#define ETH_MTLRQOMR_EHFC                             ETH_MTLRQOMR_EHFC_Msk /* DEnable Hardware Flow Control */
+#define ETH_MTLRQOMR_DISTCPEF_Pos                     (6U)
+#define ETH_MTLRQOMR_DISTCPEF_Msk                     (0x1UL << ETH_MTLRQOMR_DISTCPEF_Pos) /*!< 0x00000040 */
+#define ETH_MTLRQOMR_DISTCPEF                         ETH_MTLRQOMR_DISTCPEF_Msk /* Disable Dropping of TCP/IP Checksum Error Packets */
+#define ETH_MTLRQOMR_RSF_Pos                          (5U)
+#define ETH_MTLRQOMR_RSF_Msk                          (0x1UL << ETH_MTLRQOMR_RSF_Pos) /*!< 0x00000020 */
+#define ETH_MTLRQOMR_RSF                              ETH_MTLRQOMR_RSF_Msk     /* Receive Queue Store and Forward */
+#define ETH_MTLRQOMR_FEP_Pos                          (4U)
+#define ETH_MTLRQOMR_FEP_Msk                          (0x1UL << ETH_MTLRQOMR_FEP_Pos) /*!< 0x00000010 */
+#define ETH_MTLRQOMR_FEP                              ETH_MTLRQOMR_FEP_Msk     /* Forward Error Packets */
+#define ETH_MTLRQOMR_FUP_Pos                          (3U)
+#define ETH_MTLRQOMR_FUP_Msk                          (0x1UL << ETH_MTLRQOMR_FUP_Pos) /*!< 0x00000008 */
+#define ETH_MTLRQOMR_FUP                              ETH_MTLRQOMR_FUP_Msk     /* Forward Undersized Good Packets */
+#define ETH_MTLRQOMR_RTC_Pos                          (0U)
+#define ETH_MTLRQOMR_RTC_Msk                          (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */
+#define ETH_MTLRQOMR_RTC                              ETH_MTLRQOMR_RTC_Msk     /* Receive Queue Threshold Control */
+#define ETH_MTLRQOMR_RTC_64BITS                       ((uint32_t)0x00000000)   /* 64 bits Threshold */
+#define ETH_MTLRQOMR_RTC_32BITS                       ((uint32_t)0x00000001)   /* 32 bits Threshold */
+#define ETH_MTLRQOMR_RTC_96BITS                       ((uint32_t)0x00000002)   /* 96 bits Threshold */
+#define ETH_MTLRQOMR_RTC_128BITS                      ((uint32_t)0x00000003)   /* 128 bits Threshold */
+
+/* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
+#define ETH_MTLRQMPOCR_MISCNTOVF_Pos                  (27U)
+#define ETH_MTLRQMPOCR_MISCNTOVF_Msk                  (0x1UL << ETH_MTLRQMPOCR_MISCNTOVF_Pos) /*!< 0x08000000 */
+#define ETH_MTLRQMPOCR_MISCNTOVF                      ETH_MTLRQMPOCR_MISCNTOVF_Msk /* Missed Packet Counter Overflow Bit */
+#define ETH_MTLRQMPOCR_MISPKTCNT_Pos                  (16U)
+#define ETH_MTLRQMPOCR_MISPKTCNT_Msk                  (0x7FFUL << ETH_MTLRQMPOCR_MISPKTCNT_Pos) /*!< 0x07FF0000 */
+#define ETH_MTLRQMPOCR_MISPKTCNT                      ETH_MTLRQMPOCR_MISPKTCNT_Msk /* Missed Packet Counter */
+#define ETH_MTLRQMPOCR_OVFCNTOVF_Pos                  (11U)
+#define ETH_MTLRQMPOCR_OVFCNTOVF_Msk                  (0x1UL << ETH_MTLRQMPOCR_OVFCNTOVF_Pos) /*!< 0x00000800 */
+#define ETH_MTLRQMPOCR_OVFCNTOVF                      ETH_MTLRQMPOCR_OVFCNTOVF_Msk /* Overflow Counter Overflow Bit */
+#define ETH_MTLRQMPOCR_OVFPKTCNT_Pos                  (0U)
+#define ETH_MTLRQMPOCR_OVFPKTCNT_Msk                  (0x7FFUL << ETH_MTLRQMPOCR_OVFPKTCNT_Pos) /*!< 0x000007FF */
+#define ETH_MTLRQMPOCR_OVFPKTCNT                      ETH_MTLRQMPOCR_OVFPKTCNT_Msk /* Overflow Packet Counter */
+
+/* Bit definition for Ethernet MTL Rx Queue Debug Register */
+#define ETH_MTLRQDR_PRXQ_Pos                          (16U)
+#define ETH_MTLRQDR_PRXQ_Msk                          (0x3FFFUL << ETH_MTLRQDR_PRXQ_Pos) /*!< 0x3FFF0000 */
+#define ETH_MTLRQDR_PRXQ                              ETH_MTLRQDR_PRXQ_Msk     /* Number of Packets in Receive Queue */
+#define ETH_MTLRQDR_RXQSTS_Pos                        (4U)
+#define ETH_MTLRQDR_RXQSTS_Msk                        (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */
+#define ETH_MTLRQDR_RXQSTS                            ETH_MTLRQDR_RXQSTS_Msk   /* MTL Rx Queue Fill-Level Status */
+#define ETH_MTLRQDR_RXQSTS_EMPTY                      ((uint32_t)0x00000000)   /* Rx Queue empty */
+#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos         (4U)
+#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
+#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD             ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
+#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos         (5U)
+#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos) /*!< 0x00000020 */
+#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD             ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk /* Rx Queue fill-level above flow-control activate threshold */
+#define ETH_MTLRQDR_RXQSTS_FULL_Pos                   (4U)
+#define ETH_MTLRQDR_RXQSTS_FULL_Msk                   (0x3UL << ETH_MTLRQDR_RXQSTS_FULL_Pos) /*!< 0x00000030 */
+#define ETH_MTLRQDR_RXQSTS_FULL                       ETH_MTLRQDR_RXQSTS_FULL_Msk /* Rx Queue full */
+#define ETH_MTLRQDR_RRCSTS_Pos                        (1U)
+#define ETH_MTLRQDR_RRCSTS_Msk                        (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */
+#define ETH_MTLRQDR_RRCSTS                            ETH_MTLRQDR_RRCSTS_Msk   /* MTL Rx Queue Read Controller State */
+#define ETH_MTLRQDR_RRCSTS_IDLE                       ((uint32_t)0x00000000)   /* Idle state */
+#define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos            (1U)
+#define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk            (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
+#define ETH_MTLRQDR_RRCSTS_READINGDATA                ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
+#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos          (2U)
+#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk          (0x1UL << ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos) /*!< 0x00000004 */
+#define ETH_MTLRQDR_RRCSTS_READINGSTATUS              ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk /* Reading packet status (or timestamp) */
+#define ETH_MTLRQDR_RRCSTS_FLUSHING_Pos               (1U)
+#define ETH_MTLRQDR_RRCSTS_FLUSHING_Msk               (0x3UL << ETH_MTLRQDR_RRCSTS_FLUSHING_Pos) /*!< 0x00000006 */
+#define ETH_MTLRQDR_RRCSTS_FLUSHING                   ETH_MTLRQDR_RRCSTS_FLUSHING_Msk /* Flushing the packet data and status */
+#define ETH_MTLRQDR_RWCSTS_Pos                        (0U)
+#define ETH_MTLRQDR_RWCSTS_Msk                        (0x1UL << ETH_MTLRQDR_RWCSTS_Pos) /*!< 0x00000001 */
+#define ETH_MTLRQDR_RWCSTS                            ETH_MTLRQDR_RWCSTS_Msk   /* MTL Rx Queue Write Controller Active Status */
+
+/* Bit definition for Ethernet MTL Rx Queue Control Register */
+#define ETH_MTLRQCR_RQPA_Pos                          (3U)
+#define ETH_MTLRQCR_RQPA_Msk                          (0x1UL << ETH_MTLRQCR_RQPA_Pos) /*!< 0x00000008 */
+#define ETH_MTLRQCR_RQPA                              ETH_MTLRQCR_RQPA_Msk     /* Receive Queue Packet Arbitration */
+#define ETH_MTLRQCR_RQW_Pos                           (0U)
+#define ETH_MTLRQCR_RQW_Msk                           (0x7UL << ETH_MTLRQCR_RQW_Pos) /*!< 0x00000007 */
+#define ETH_MTLRQCR_RQW                               ETH_MTLRQCR_RQW_Msk      /* Receive Queue Weight */
+
+/* Bit definition for Ethernet DMA Mode Register */
+#define ETH_DMAMR_INTM_Pos                            (16U)
+#define ETH_DMAMR_INTM_Msk                            (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */
+#define ETH_DMAMR_INTM                                ETH_DMAMR_INTM_Msk       /* This field defines the interrupt mode */
+#define ETH_DMAMR_INTM_0                              (0x0UL << ETH_DMAMR_INTM_Pos) /*!< 0x00000000 */
+#define ETH_DMAMR_INTM_1                              (0x1UL << ETH_DMAMR_INTM_Pos) /*!< 0x00010000 */
+#define ETH_DMAMR_INTM_2                              (0x2UL << ETH_DMAMR_INTM_Pos) /*!< 0x00020000 */
+#define ETH_DMAMR_PR_Pos                              (12U)
+#define ETH_DMAMR_PR_Msk                              (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
+#define ETH_DMAMR_PR                                  ETH_DMAMR_PR_Msk         /* Priority Ratio */
+#define ETH_DMAMR_PR_1_1                              ((uint32_t)0x00000000)   /* The priority ratio is 1:1 */
+#define ETH_DMAMR_PR_2_1                              ((uint32_t)0x00001000)   /* The priority ratio is 2:1 */
+#define ETH_DMAMR_PR_3_1                              ((uint32_t)0x00002000)   /* The priority ratio is 3:1 */
+#define ETH_DMAMR_PR_4_1                              ((uint32_t)0x00003000)   /* The priority ratio is 4:1 */
+#define ETH_DMAMR_PR_5_1                              ((uint32_t)0x00004000)   /* The priority ratio is 5:1 */
+#define ETH_DMAMR_PR_6_1                              ((uint32_t)0x00005000)   /* The priority ratio is 6:1 */
+#define ETH_DMAMR_PR_7_1                              ((uint32_t)0x00006000)   /* The priority ratio is 7:1 */
+#define ETH_DMAMR_PR_8_1                              ((uint32_t)0x00007000)   /* The priority ratio is 8:1 */
+#define ETH_DMAMR_TXPR_Pos                            (11U)
+#define ETH_DMAMR_TXPR_Msk                            (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
+#define ETH_DMAMR_TXPR                                ETH_DMAMR_TXPR_Msk       /* Transmit Priority */
+#define ETH_DMAMR_DA_Pos                              (1U)
+#define ETH_DMAMR_DA_Msk                              (0x1UL << ETH_DMAMR_DA_Pos) /*!< 0x00000002 */
+#define ETH_DMAMR_DA                                  ETH_DMAMR_DA_Msk         /* DMA Tx or Rx Arbitration Scheme */
+#define ETH_DMAMR_SWR_Pos                             (0U)
+#define ETH_DMAMR_SWR_Msk                             (0x1UL << ETH_DMAMR_SWR_Pos) /*!< 0x00000001 */
+#define ETH_DMAMR_SWR                                 ETH_DMAMR_SWR_Msk        /* Software Reset */
+
+/* Bit definition for Ethernet DMA SysBus Mode Register */
+#define ETH_DMASBMR_RB_Pos                            (15U)
+#define ETH_DMASBMR_RB_Msk                            (0x1UL << ETH_DMASBMR_RB_Pos) /*!< 0x00008000 */
+#define ETH_DMASBMR_RB                                ETH_DMASBMR_RB_Msk       /* Rebuild INCRx Burst */
+#define ETH_DMASBMR_MB_Pos                            (14U)
+#define ETH_DMASBMR_MB_Msk                            (0x1UL << ETH_DMASBMR_MB_Pos) /*!< 0x00004000 */
+#define ETH_DMASBMR_MB                                ETH_DMASBMR_MB_Msk       /* Mixed Burst */
+#define ETH_DMASBMR_AAL_Pos                           (12U)
+#define ETH_DMASBMR_AAL_Msk                           (0x1UL << ETH_DMASBMR_AAL_Pos) /*!< 0x00001000 */
+#define ETH_DMASBMR_AAL                               ETH_DMASBMR_AAL_Msk      /* Address-Aligned Beats */
+#define ETH_DMASBMR_FB_Pos                            (0U)
+#define ETH_DMASBMR_FB_Msk                            (0x1UL << ETH_DMASBMR_FB_Pos) /*!< 0x00000001 */
+#define ETH_DMASBMR_FB                                ETH_DMASBMR_FB_Msk       /* Fixed Burst Length */
+
+/* Bit definition for Ethernet DMA Interrupt Status Register */
+#define ETH_DMAISR_MACIS_Pos                          (17U)
+#define ETH_DMAISR_MACIS_Msk                          (0x1UL << ETH_DMAISR_MACIS_Pos) /*!< 0x00020000 */
+#define ETH_DMAISR_MACIS                              ETH_DMAISR_MACIS_Msk     /* MAC Interrupt Status */
+#define ETH_DMAISR_MTLIS_Pos                          (16U)
+#define ETH_DMAISR_MTLIS_Msk                          (0x1UL << ETH_DMAISR_MTLIS_Pos) /*!< 0x00010000 */
+#define ETH_DMAISR_MTLIS                              ETH_DMAISR_MTLIS_Msk     /* MAC Interrupt Status */
+#define ETH_DMAISR_DMACIS_Pos                         (0U)
+#define ETH_DMAISR_DMACIS_Msk                         (0x1UL << ETH_DMAISR_DMACIS_Pos) /*!< 0x00000001 */
+#define ETH_DMAISR_DMACIS                             ETH_DMAISR_DMACIS_Msk    /* DMA Channel Interrupt Status */
+
+/* Bit definition for Ethernet DMA Debug Status Register */
+#define ETH_DMADSR_TPS_Pos                            (12U)
+#define ETH_DMADSR_TPS_Msk                            (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */
+#define ETH_DMADSR_TPS                                ETH_DMADSR_TPS_Msk       /* DMA Channel Transmit Process State */
+#define ETH_DMADSR_TPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Transmit Command issued) */
+#define ETH_DMADSR_TPS_FETCHING_Pos                   (12U)
+#define ETH_DMADSR_TPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */
+#define ETH_DMADSR_TPS_FETCHING                       ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
+#define ETH_DMADSR_TPS_WAITING_Pos                    (13U)
+#define ETH_DMADSR_TPS_WAITING_Msk                    (0x1UL << ETH_DMADSR_TPS_WAITING_Pos) /*!< 0x00002000 */
+#define ETH_DMADSR_TPS_WAITING                        ETH_DMADSR_TPS_WAITING_Msk /* Running (Waiting for status) */
+#define ETH_DMADSR_TPS_READING_Pos                    (12U)
+#define ETH_DMADSR_TPS_READING_Msk                    (0x3UL << ETH_DMADSR_TPS_READING_Pos) /*!< 0x00003000 */
+#define ETH_DMADSR_TPS_READING                        ETH_DMADSR_TPS_READING_Msk /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */
+#define ETH_DMADSR_TPS_TIMESTAMP_WR_Pos               (14U)
+#define ETH_DMADSR_TPS_TIMESTAMP_WR_Msk               (0x1UL << ETH_DMADSR_TPS_TIMESTAMP_WR_Pos) /*!< 0x00004000 */
+#define ETH_DMADSR_TPS_TIMESTAMP_WR                   ETH_DMADSR_TPS_TIMESTAMP_WR_Msk /* Timestamp write state */
+#define ETH_DMADSR_TPS_SUSPENDED_Pos                  (13U)
+#define ETH_DMADSR_TPS_SUSPENDED_Msk                  (0x3UL << ETH_DMADSR_TPS_SUSPENDED_Pos) /*!< 0x00006000 */
+#define ETH_DMADSR_TPS_SUSPENDED                      ETH_DMADSR_TPS_SUSPENDED_Msk /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */
+#define ETH_DMADSR_TPS_CLOSING_Pos                    (12U)
+#define ETH_DMADSR_TPS_CLOSING_Msk                    (0x7UL << ETH_DMADSR_TPS_CLOSING_Pos) /*!< 0x00007000 */
+#define ETH_DMADSR_TPS_CLOSING                        ETH_DMADSR_TPS_CLOSING_Msk /* Running (Closing Tx Descriptor) */
+#define ETH_DMADSR_RPS_Pos                            (8U)
+#define ETH_DMADSR_RPS_Msk                            (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */
+#define ETH_DMADSR_RPS                                ETH_DMADSR_RPS_Msk       /* DMA Channel Receive Process State */
+#define ETH_DMADSR_RPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Receive Command issued) */
+#define ETH_DMADSR_RPS_FETCHING_Pos                   (12U)
+#define ETH_DMADSR_RPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */
+#define ETH_DMADSR_RPS_FETCHING                       ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
+#define ETH_DMADSR_RPS_WAITING_Pos                    (12U)
+#define ETH_DMADSR_RPS_WAITING_Msk                    (0x3UL << ETH_DMADSR_RPS_WAITING_Pos) /*!< 0x00003000 */
+#define ETH_DMADSR_RPS_WAITING                        ETH_DMADSR_RPS_WAITING_Msk /* Running (Waiting for status) */
+#define ETH_DMADSR_RPS_SUSPENDED_Pos                  (14U)
+#define ETH_DMADSR_RPS_SUSPENDED_Msk                  (0x1UL << ETH_DMADSR_RPS_SUSPENDED_Pos) /*!< 0x00004000 */
+#define ETH_DMADSR_RPS_SUSPENDED                      ETH_DMADSR_RPS_SUSPENDED_Msk /* Suspended (Rx Descriptor Unavailable) */
+#define ETH_DMADSR_RPS_CLOSING_Pos                    (12U)
+#define ETH_DMADSR_RPS_CLOSING_Msk                    (0x5UL << ETH_DMADSR_RPS_CLOSING_Pos) /*!< 0x00005000 */
+#define ETH_DMADSR_RPS_CLOSING                        ETH_DMADSR_RPS_CLOSING_Msk /* Running (Closing the Rx Descriptor) */
+#define ETH_DMADSR_RPS_TIMESTAMP_WR_Pos               (13U)
+#define ETH_DMADSR_RPS_TIMESTAMP_WR_Msk               (0x3UL << ETH_DMADSR_RPS_TIMESTAMP_WR_Pos) /*!< 0x00006000 */
+#define ETH_DMADSR_RPS_TIMESTAMP_WR                   ETH_DMADSR_RPS_TIMESTAMP_WR_Msk /* Timestamp write state */
+#define ETH_DMADSR_RPS_TRANSFERRING_Pos               (12U)
+#define ETH_DMADSR_RPS_TRANSFERRING_Msk               (0x7UL << ETH_DMADSR_RPS_TRANSFERRING_Pos) /*!< 0x00007000 */
+#define ETH_DMADSR_RPS_TRANSFERRING                   ETH_DMADSR_RPS_TRANSFERRING_Msk /* Running (Transferring the received packet data from the Rx buffer to the system memory) */
+
+/* Bit definition for Ethernet DMA Channel Control Register */
+#define ETH_DMACCR_DSL_Pos                            (18U)
+#define ETH_DMACCR_DSL_Msk                            (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */
+#define ETH_DMACCR_DSL                                ETH_DMACCR_DSL_Msk       /* Descriptor Skip Length */
+#define ETH_DMACCR_DSL_0BIT                           ((uint32_t)0x00000000)
+#define ETH_DMACCR_DSL_32BIT                          ((uint32_t)0x00040000)
+#define ETH_DMACCR_DSL_64BIT                          ((uint32_t)0x00080000)
+#define ETH_DMACCR_DSL_128BIT                         ((uint32_t)0x00100000)
+#define ETH_DMACCR_8PBL                               ((uint32_t)0x00010000)   /* 8xPBL mode */
+#define ETH_DMACCR_MSS_Pos                            (0U)
+#define ETH_DMACCR_MSS_Msk                            (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */
+#define ETH_DMACCR_MSS                                ETH_DMACCR_MSS_Msk       /* Maximum Segment Size */
+
+/* Bit definition for Ethernet DMA Channel Tx Control Register */
+#define ETH_DMACTCR_TPBL_Pos                          (16U)
+#define ETH_DMACTCR_TPBL_Msk                          (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */
+#define ETH_DMACTCR_TPBL                              ETH_DMACTCR_TPBL_Msk     /* Transmit Programmable Burst Length */
+#define ETH_DMACTCR_TPBL_1PBL                         ((uint32_t)0x00010000)   /* Transmit Programmable Burst Length 1 */
+#define ETH_DMACTCR_TPBL_2PBL                         ((uint32_t)0x00020000)   /* Transmit Programmable Burst Length 2 */
+#define ETH_DMACTCR_TPBL_4PBL                         ((uint32_t)0x00040000)   /* Transmit Programmable Burst Length 4 */
+#define ETH_DMACTCR_TPBL_8PBL                         ((uint32_t)0x00080000)   /* Transmit Programmable Burst Length 8 */
+#define ETH_DMACTCR_TPBL_16PBL                        ((uint32_t)0x00100000)   /* Transmit Programmable Burst Length 16 */
+#define ETH_DMACTCR_TPBL_32PBL                        ((uint32_t)0x00200000)   /* Transmit Programmable Burst Length 32 */
+#define ETH_DMACTCR_TSE_Pos                           (12U)
+#define ETH_DMACTCR_TSE_Msk                           (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */
+#define ETH_DMACTCR_TSE                               ETH_DMACTCR_TSE_Msk      /* TCP Segmentation Enabled */
+#define ETH_DMACTCR_OSP_Pos                           (4U)
+#define ETH_DMACTCR_OSP_Msk                           (0x1UL << ETH_DMACTCR_OSP_Pos) /*!< 0x00000010 */
+#define ETH_DMACTCR_OSP                               ETH_DMACTCR_OSP_Msk      /* Operate on Second Packet */
+#define ETH_DMACTCR_ST_Pos                            (0U)
+#define ETH_DMACTCR_ST_Msk                            (0x1UL << ETH_DMACTCR_ST_Pos) /*!< 0x00000001 */
+#define ETH_DMACTCR_ST                                ETH_DMACTCR_ST_Msk       /* Start or Stop Transmission Command */
+
+/* Bit definition for Ethernet DMA Channel Rx Control Register */
+#define ETH_DMACRCR_RPF_Pos                           (31U)
+#define ETH_DMACRCR_RPF_Msk                           (0x1UL << ETH_DMACRCR_RPF_Pos) /*!< 0x80000000 */
+#define ETH_DMACRCR_RPF                               ETH_DMACRCR_RPF_Msk      /* Rx Packet Flush */
+#define ETH_DMACRCR_RPBL_Pos                          (16U)
+#define ETH_DMACRCR_RPBL_Msk                          (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */
+#define ETH_DMACRCR_RPBL                              ETH_DMACRCR_RPBL_Msk     /* Receive Programmable Burst Length */
+#define ETH_DMACRCR_RPBL_1PBL                         ((uint32_t)0x00010000)   /* Receive Programmable Burst Length 1 */
+#define ETH_DMACRCR_RPBL_2PBL                         ((uint32_t)0x00020000)   /* Receive Programmable Burst Length 2 */
+#define ETH_DMACRCR_RPBL_4PBL                         ((uint32_t)0x00040000)   /* Receive Programmable Burst Length 4 */
+#define ETH_DMACRCR_RPBL_8PBL                         ((uint32_t)0x00080000)   /* Receive Programmable Burst Length 8 */
+#define ETH_DMACRCR_RPBL_16PBL                        ((uint32_t)0x00100000)   /* Receive Programmable Burst Length 16 */
+#define ETH_DMACRCR_RPBL_32PBL                        ((uint32_t)0x00200000)   /* Receive Programmable Burst Length 32 */
+#define ETH_DMACRCR_RBSZ_Pos                          (1U)
+#define ETH_DMACRCR_RBSZ_Msk                          (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */
+#define ETH_DMACRCR_RBSZ                              ETH_DMACRCR_RBSZ_Msk     /* Receive Buffer size */
+#define ETH_DMACRCR_SR_Pos                            (0U)
+#define ETH_DMACRCR_SR_Msk                            (0x1UL << ETH_DMACRCR_SR_Pos) /*!< 0x00000001 */
+#define ETH_DMACRCR_SR                                ETH_DMACRCR_SR_Msk       /* Start or Stop Receive */
+
+/* Bit definition for Ethernet DMA CH Tx Desc List Address Register */
+#define ETH_DMACTDLAR_TDESLA_Pos                      (2U)
+#define ETH_DMACTDLAR_TDESLA_Msk                      (0x3FFFFFFFUL << ETH_DMACTDLAR_TDESLA_Pos) /*!< 0xFFFFFFFC */
+#define ETH_DMACTDLAR_TDESLA                          ETH_DMACTDLAR_TDESLA_Msk /* Start of Transmit List */
+
+/* Bit definition for Ethernet DMA CH Rx Desc List Address Register */
+#define ETH_DMACRDLAR_RDESLA_Pos                      (2U)
+#define ETH_DMACRDLAR_RDESLA_Msk                      (0x3FFFFFFFUL << ETH_DMACRDLAR_RDESLA_Pos) /*!< 0xFFFFFFFC */
+#define ETH_DMACRDLAR_RDESLA                          ETH_DMACRDLAR_RDESLA_Msk /* Start of Receive List */
+
+/* Bit definition for Ethernet DMA CH Tx Desc Tail Pointer Register */
+#define ETH_DMACTDTPR_TDT_Pos                         (2U)
+#define ETH_DMACTDTPR_TDT_Msk                         (0x3FFFFFFFUL << ETH_DMACTDTPR_TDT_Pos) /*!< 0xFFFFFFFC */
+#define ETH_DMACTDTPR_TDT                             ETH_DMACTDTPR_TDT_Msk    /* Transmit Descriptor Tail Pointer */
+
+/* Bit definition for Ethernet DMA CH Rx Desc Tail Pointer Register */
+#define ETH_DMACRDTPR_RDT_Pos                         (2U)
+#define ETH_DMACRDTPR_RDT_Msk                         (0x3FFFFFFFUL << ETH_DMACRDTPR_RDT_Pos) /*!< 0xFFFFFFFC */
+#define ETH_DMACRDTPR_RDT                             ETH_DMACRDTPR_RDT_Msk    /* Receive Descriptor Tail Pointer */
+
+/* Bit definition for Ethernet DMA CH Tx Desc Ring Length Register */
+#define ETH_DMACTDRLR_TDRL_Pos                        (0U)
+#define ETH_DMACTDRLR_TDRL_Msk                        (0x3FFUL << ETH_DMACTDRLR_TDRL_Pos) /*!< 0x000003FF */
+#define ETH_DMACTDRLR_TDRL                            ETH_DMACTDRLR_TDRL_Msk   /* Transmit Descriptor Ring Length */
+
+/* Bit definition for Ethernet DMA CH Rx Desc Ring Length Register */
+#define ETH_DMACRDRLR_RDRL_Pos                        (0U)
+#define ETH_DMACRDRLR_RDRL_Msk                        (0x3FFUL << ETH_DMACRDRLR_RDRL_Pos) /*!< 0x000003FF */
+#define ETH_DMACRDRLR_RDRL                            ETH_DMACRDRLR_RDRL_Msk   /* Receive Descriptor Ring Length */
+
+/* Bit definition for Ethernet DMA Channel Interrupt Enable Register */
+#define ETH_DMACIER_NIE_Pos                           (15U)
+#define ETH_DMACIER_NIE_Msk                           (0x1UL << ETH_DMACIER_NIE_Pos) /*!< 0x00008000 */
+#define ETH_DMACIER_NIE                               ETH_DMACIER_NIE_Msk      /* Normal Interrupt Summary Enable */
+#define ETH_DMACIER_AIE_Pos                           (14U)
+#define ETH_DMACIER_AIE_Msk                           (0x1UL << ETH_DMACIER_AIE_Pos) /*!< 0x00004000 */
+#define ETH_DMACIER_AIE                               ETH_DMACIER_AIE_Msk      /* Abnormal Interrupt Summary Enable */
+#define ETH_DMACIER_CDEE_Pos                          (13U)
+#define ETH_DMACIER_CDEE_Msk                          (0x1UL << ETH_DMACIER_CDEE_Pos) /*!< 0x00002000 */
+#define ETH_DMACIER_CDEE                              ETH_DMACIER_CDEE_Msk     /* Context Descriptor Error Enable */
+#define ETH_DMACIER_FBEE_Pos                          (12U)
+#define ETH_DMACIER_FBEE_Msk                          (0x1UL << ETH_DMACIER_FBEE_Pos) /*!< 0x00001000 */
+#define ETH_DMACIER_FBEE                              ETH_DMACIER_FBEE_Msk     /* Fatal Bus Error Enable */
+#define ETH_DMACIER_ERIE_Pos                          (11U)
+#define ETH_DMACIER_ERIE_Msk                          (0x1UL << ETH_DMACIER_ERIE_Pos) /*!< 0x00000800 */
+#define ETH_DMACIER_ERIE                              ETH_DMACIER_ERIE_Msk     /* Early Receive Interrupt Enable */
+#define ETH_DMACIER_ETIE_Pos                          (10U)
+#define ETH_DMACIER_ETIE_Msk                          (0x1UL << ETH_DMACIER_ETIE_Pos) /*!< 0x00000400 */
+#define ETH_DMACIER_ETIE                              ETH_DMACIER_ETIE_Msk     /* Early Transmit Interrupt Enable */
+#define ETH_DMACIER_RWTE_Pos                          (9U)
+#define ETH_DMACIER_RWTE_Msk                          (0x1UL << ETH_DMACIER_RWTE_Pos) /*!< 0x00000200 */
+#define ETH_DMACIER_RWTE                              ETH_DMACIER_RWTE_Msk     /* Receive Watchdog Timeout Enable */
+#define ETH_DMACIER_RSE_Pos                           (8U)
+#define ETH_DMACIER_RSE_Msk                           (0x1UL << ETH_DMACIER_RSE_Pos) /*!< 0x00000100 */
+#define ETH_DMACIER_RSE                               ETH_DMACIER_RSE_Msk      /* Receive Stopped Enable */
+#define ETH_DMACIER_RBUE_Pos                          (7U)
+#define ETH_DMACIER_RBUE_Msk                          (0x1UL << ETH_DMACIER_RBUE_Pos) /*!< 0x00000080 */
+#define ETH_DMACIER_RBUE                              ETH_DMACIER_RBUE_Msk     /* Receive Buffer Unavailable Enable */
+#define ETH_DMACIER_RIE_Pos                           (6U)
+#define ETH_DMACIER_RIE_Msk                           (0x1UL << ETH_DMACIER_RIE_Pos) /*!< 0x00000040 */
+#define ETH_DMACIER_RIE                               ETH_DMACIER_RIE_Msk      /* Receive Interrupt Enable */
+#define ETH_DMACIER_TBUE_Pos                          (2U)
+#define ETH_DMACIER_TBUE_Msk                          (0x1UL << ETH_DMACIER_TBUE_Pos) /*!< 0x00000004 */
+#define ETH_DMACIER_TBUE                              ETH_DMACIER_TBUE_Msk     /* Transmit Buffer Unavailable Enable */
+#define ETH_DMACIER_TXSE_Pos                          (1U)
+#define ETH_DMACIER_TXSE_Msk                          (0x1UL << ETH_DMACIER_TXSE_Pos) /*!< 0x00000002 */
+#define ETH_DMACIER_TXSE                              ETH_DMACIER_TXSE_Msk     /* Transmit Stopped Enable */
+#define ETH_DMACIER_TIE_Pos                           (0U)
+#define ETH_DMACIER_TIE_Msk                           (0x1UL << ETH_DMACIER_TIE_Pos) /*!< 0x00000001 */
+#define ETH_DMACIER_TIE                               ETH_DMACIER_TIE_Msk      /* Transmit Interrupt Enable */
+
+/* Bit definition for Ethernet DMA Channel Rx Interrupt Watchdog Timer Register */
+#define ETH_DMACRIWTR_RWT_Pos                         (0U)
+#define ETH_DMACRIWTR_RWT_Msk                         (0xFFUL << ETH_DMACRIWTR_RWT_Pos) /*!< 0x000000FF */
+#define ETH_DMACRIWTR_RWT                             ETH_DMACRIWTR_RWT_Msk    /* Receive Interrupt Watchdog Timer Count */
+
+/* Bit definition for Ethernet DMA Channel Current App Tx Desc Register */
+#define ETH_DMACCATDR_CURTDESAPTR_Pos                 (0U)
+#define ETH_DMACCATDR_CURTDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCATDR_CURTDESAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACCATDR_CURTDESAPTR                     ETH_DMACCATDR_CURTDESAPTR_Msk /* Application Transmit Descriptor Address Pointer */
+
+/* Bit definition for Ethernet DMA Channel Current App Rx Desc Register */
+#define ETH_DMACCARDR_CURRDESAPTR_Pos                 (0U)
+#define ETH_DMACCARDR_CURRDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCARDR_CURRDESAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACCARDR_CURRDESAPTR                     ETH_DMACCARDR_CURRDESAPTR_Msk /* Application Receive Descriptor Address Pointer */
+
+/* Bit definition for Ethernet DMA Channel Current App Tx Buffer Register */
+#define ETH_DMACCATBR_CURTBUFAPTR_Pos                 (0U)
+#define ETH_DMACCATBR_CURTBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCATBR_CURTBUFAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACCATBR_CURTBUFAPTR                     ETH_DMACCATBR_CURTBUFAPTR_Msk /* Application Transmit Buffer Address Pointer */
+
+/* Bit definition for Ethernet DMA Channel Current App Rx Buffer Register */
+#define ETH_DMACCARBR_CURRBUFAPTR_Pos                 (0U)
+#define ETH_DMACCARBR_CURRBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCARBR_CURRBUFAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACCARBR_CURRBUFAPTR                     ETH_DMACCARBR_CURRBUFAPTR_Msk /* Application Receive Buffer Address Pointer */
+
+/* Bit definition for Ethernet DMA Channel Status Register */
+#define ETH_DMACSR_REB_Pos                            (19U)
+#define ETH_DMACSR_REB_Msk                            (0x7UL << ETH_DMACSR_REB_Pos) /*!< 0x00380000 */
+#define ETH_DMACSR_REB                                ETH_DMACSR_REB_Msk       /* Rx DMA Error Bits */
+#define ETH_DMACSR_TEB_Pos                            (16U)
+#define ETH_DMACSR_TEB_Msk                            (0x7UL << ETH_DMACSR_TEB_Pos) /*!< 0x00070000 */
+#define ETH_DMACSR_TEB                                ETH_DMACSR_TEB_Msk       /* Tx DMA Error Bits */
+#define ETH_DMACSR_NIS_Pos                            (15U)
+#define ETH_DMACSR_NIS_Msk                            (0x1UL << ETH_DMACSR_NIS_Pos) /*!< 0x00008000 */
+#define ETH_DMACSR_NIS                                ETH_DMACSR_NIS_Msk       /* Normal Interrupt Summary */
+#define ETH_DMACSR_AIS_Pos                            (14U)
+#define ETH_DMACSR_AIS_Msk                            (0x1UL << ETH_DMACSR_AIS_Pos) /*!< 0x00004000 */
+#define ETH_DMACSR_AIS                                ETH_DMACSR_AIS_Msk       /* Abnormal Interrupt Summary */
+#define ETH_DMACSR_CDE_Pos                            (13U)
+#define ETH_DMACSR_CDE_Msk                            (0x1UL << ETH_DMACSR_CDE_Pos) /*!< 0x00002000 */
+#define ETH_DMACSR_CDE                                ETH_DMACSR_CDE_Msk       /* Context Descriptor Error */
+#define ETH_DMACSR_FBE_Pos                            (12U)
+#define ETH_DMACSR_FBE_Msk                            (0x1UL << ETH_DMACSR_FBE_Pos) /*!< 0x00001000 */
+#define ETH_DMACSR_FBE                                ETH_DMACSR_FBE_Msk       /* Fatal Bus Error */
+#define ETH_DMACSR_ERI_Pos                            (11U)
+#define ETH_DMACSR_ERI_Msk                            (0x1UL << ETH_DMACSR_ERI_Pos) /*!< 0x00000800 */
+#define ETH_DMACSR_ERI                                ETH_DMACSR_ERI_Msk       /* Early Receive Interrupt */
+#define ETH_DMACSR_ETI_Pos                            (10U)
+#define ETH_DMACSR_ETI_Msk                            (0x1UL << ETH_DMACSR_ETI_Pos) /*!< 0x00000400 */
+#define ETH_DMACSR_ETI                                ETH_DMACSR_ETI_Msk       /* Early Transmit Interrupt */
+#define ETH_DMACSR_RWT_Pos                            (9U)
+#define ETH_DMACSR_RWT_Msk                            (0x1UL << ETH_DMACSR_RWT_Pos) /*!< 0x00000200 */
+#define ETH_DMACSR_RWT                                ETH_DMACSR_RWT_Msk       /* Receive Watchdog Timeout */
+#define ETH_DMACSR_RPS_Pos                            (8U)
+#define ETH_DMACSR_RPS_Msk                            (0x1UL << ETH_DMACSR_RPS_Pos) /*!< 0x00000100 */
+#define ETH_DMACSR_RPS                                ETH_DMACSR_RPS_Msk       /* Receive Process Stopped */
+#define ETH_DMACSR_RBU_Pos                            (7U)
+#define ETH_DMACSR_RBU_Msk                            (0x1UL << ETH_DMACSR_RBU_Pos) /*!< 0x00000080 */
+#define ETH_DMACSR_RBU                                ETH_DMACSR_RBU_Msk       /* Receive Buffer Unavailable */
+#define ETH_DMACSR_RI_Pos                             (6U)
+#define ETH_DMACSR_RI_Msk                             (0x1UL << ETH_DMACSR_RI_Pos) /*!< 0x00000040 */
+#define ETH_DMACSR_RI                                 ETH_DMACSR_RI_Msk        /* Receive Interrupt */
+#define ETH_DMACSR_TBU_Pos                            (2U)
+#define ETH_DMACSR_TBU_Msk                            (0x1UL << ETH_DMACSR_TBU_Pos) /*!< 0x00000004 */
+#define ETH_DMACSR_TBU                                ETH_DMACSR_TBU_Msk       /* Transmit Buffer Unavailable */
+#define ETH_DMACSR_TPS_Pos                            (1U)
+#define ETH_DMACSR_TPS_Msk                            (0x1UL << ETH_DMACSR_TPS_Pos) /*!< 0x00000002 */
+#define ETH_DMACSR_TPS                                ETH_DMACSR_TPS_Msk       /* Transmit Process Stopped */
+#define ETH_DMACSR_TI_Pos                             (0U)
+#define ETH_DMACSR_TI_Msk                             (0x1UL << ETH_DMACSR_TI_Pos) /*!< 0x00000001 */
+#define ETH_DMACSR_TI                                 ETH_DMACSR_TI_Msk        /* Transmit Interrupt */
+
+/* Bit definition for Ethernet DMA Channel missed frame count register */
+#define ETH_DMACMFCR_MFCO_Pos                         (15U)
+#define ETH_DMACMFCR_MFCO_Msk                         (0x1UL << ETH_DMACMFCR_MFCO_Pos) /*!< 0x00008000 */
+#define ETH_DMACMFCR_MFCO                             ETH_DMACMFCR_MFCO_Msk    /* Overflow status of the MFC Counter */
+#define ETH_DMACMFCR_MFC_Pos                          (0U)
+#define ETH_DMACMFCR_MFC_Msk                          (0x7FFUL << ETH_DMACMFCR_MFC_Pos) /*!< 0x000007FF */
+#define ETH_DMACMFCR_MFC                              ETH_DMACMFCR_MFC_Msk     /* The number of packet counters dropped by the DMA */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             DMA Controller                                 */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for DMA_SxCR register  *****************/
+#define DMA_SxCR_MBURST_Pos      (23U)
+#define DMA_SxCR_MBURST_Msk      (0x3UL << DMA_SxCR_MBURST_Pos)                /*!< 0x01800000 */
+#define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk                           /*!< Memory burst transfer configuration */
+#define DMA_SxCR_MBURST_0        (0x1UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */
+#define DMA_SxCR_MBURST_1        (0x2UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */
+#define DMA_SxCR_PBURST_Pos      (21U)
+#define DMA_SxCR_PBURST_Msk      (0x3UL << DMA_SxCR_PBURST_Pos)                /*!< 0x00600000 */
+#define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk                           /*!< Peripheral burst transfer configuration */
+#define DMA_SxCR_PBURST_0        (0x1UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */
+#define DMA_SxCR_PBURST_1        (0x2UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */
+#define DMA_SxCR_TRBUFF_Pos      (20U)
+#define DMA_SxCR_TRBUFF_Msk      (0x1UL << DMA_SxCR_TRBUFF_Pos)                 /*!< 0x00100000 */
+#define DMA_SxCR_TRBUFF          DMA_SxCR_TRBUFF_Msk                            /*!< bufferable transfers enabled/disable */
+#define DMA_SxCR_CT_Pos          (19U)
+#define DMA_SxCR_CT_Msk          (0x1UL << DMA_SxCR_CT_Pos)                    /*!< 0x00080000 */
+#define DMA_SxCR_CT              DMA_SxCR_CT_Msk                               /*!< Current target (only in double buffer mode) */
+#define DMA_SxCR_DBM_Pos         (18U)
+#define DMA_SxCR_DBM_Msk         (0x1UL << DMA_SxCR_DBM_Pos)                   /*!< 0x00040000 */
+#define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk                              /*!< Double buffer mode */
+#define DMA_SxCR_PL_Pos          (16U)
+#define DMA_SxCR_PL_Msk          (0x3UL << DMA_SxCR_PL_Pos)                    /*!< 0x00030000 */
+#define DMA_SxCR_PL              DMA_SxCR_PL_Msk                               /*!< Priority level */
+#define DMA_SxCR_PL_0            (0x1UL << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */
+#define DMA_SxCR_PL_1            (0x2UL << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */
+#define DMA_SxCR_PINCOS_Pos      (15U)
+#define DMA_SxCR_PINCOS_Msk      (0x1UL << DMA_SxCR_PINCOS_Pos)                /*!< 0x00008000 */
+#define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk                           /*!< Peripheral increment offset size */
+#define DMA_SxCR_MSIZE_Pos       (13U)
+#define DMA_SxCR_MSIZE_Msk       (0x3UL << DMA_SxCR_MSIZE_Pos)                 /*!< 0x00006000 */
+#define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk                            /*!< Memory data size */
+#define DMA_SxCR_MSIZE_0         (0x1UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */
+#define DMA_SxCR_MSIZE_1         (0x2UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */
+#define DMA_SxCR_PSIZE_Pos       (11U)
+#define DMA_SxCR_PSIZE_Msk       (0x3UL << DMA_SxCR_PSIZE_Pos)                 /*!< 0x00001800 */
+#define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk                            /*< Peripheral data size */
+#define DMA_SxCR_PSIZE_0         (0x1UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */
+#define DMA_SxCR_PSIZE_1         (0x2UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */
+#define DMA_SxCR_MINC_Pos        (10U)
+#define DMA_SxCR_MINC_Msk        (0x1UL << DMA_SxCR_MINC_Pos)                  /*!< 0x00000400 */
+#define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk                             /*!< Memory increment mode */
+#define DMA_SxCR_PINC_Pos        (9U)
+#define DMA_SxCR_PINC_Msk        (0x1UL << DMA_SxCR_PINC_Pos)                  /*!< 0x00000200 */
+#define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk                             /*!< Peripheral increment mode */
+#define DMA_SxCR_CIRC_Pos        (8U)
+#define DMA_SxCR_CIRC_Msk        (0x1UL << DMA_SxCR_CIRC_Pos)                  /*!< 0x00000100 */
+#define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk                             /*!< Circular mode */
+#define DMA_SxCR_DIR_Pos         (6U)
+#define DMA_SxCR_DIR_Msk         (0x3UL << DMA_SxCR_DIR_Pos)                   /*!< 0x000000C0 */
+#define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk                              /*!< Data transfer direction */
+#define DMA_SxCR_DIR_0           (0x1UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */
+#define DMA_SxCR_DIR_1           (0x2UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */
+#define DMA_SxCR_PFCTRL_Pos      (5U)
+#define DMA_SxCR_PFCTRL_Msk      (0x1UL << DMA_SxCR_PFCTRL_Pos)                /*!< 0x00000020 */
+#define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk                           /*!< Peripheral flow controller */
+#define DMA_SxCR_TCIE_Pos        (4U)
+#define DMA_SxCR_TCIE_Msk        (0x1UL << DMA_SxCR_TCIE_Pos)                  /*!< 0x00000010 */
+#define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk                             /*!< Transfer complete interrupt enable */
+#define DMA_SxCR_HTIE_Pos        (3U)
+#define DMA_SxCR_HTIE_Msk        (0x1UL << DMA_SxCR_HTIE_Pos)                  /*!< 0x00000008 */
+#define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk                             /*!< Half transfer interrupt enable */
+#define DMA_SxCR_TEIE_Pos        (2U)
+#define DMA_SxCR_TEIE_Msk        (0x1UL << DMA_SxCR_TEIE_Pos)                  /*!< 0x00000004 */
+#define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk                             /*!< Transfer error interrupt enable */
+#define DMA_SxCR_DMEIE_Pos       (1U)
+#define DMA_SxCR_DMEIE_Msk       (0x1UL << DMA_SxCR_DMEIE_Pos)                 /*!< 0x00000002 */
+#define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk                            /*!< Direct mode error interrupt enable */
+#define DMA_SxCR_EN_Pos          (0U)
+#define DMA_SxCR_EN_Msk          (0x1UL << DMA_SxCR_EN_Pos)                    /*!< 0x00000001 */
+#define DMA_SxCR_EN              DMA_SxCR_EN_Msk                               /*!< Stream enable / flag stream ready when read low */
+
+/********************  Bits definition for DMA_SxCNDTR register  **************/
+#define DMA_SxNDT_Pos            (0U)
+#define DMA_SxNDT_Msk            (0xFFFFUL << DMA_SxNDT_Pos)                   /*!< 0x0000FFFF */
+#define DMA_SxNDT                DMA_SxNDT_Msk                                 /*!< Number of data items to transfer */
+#define DMA_SxNDT_0              (0x0001UL << DMA_SxNDT_Pos)                    /*!< 0x00000001 */
+#define DMA_SxNDT_1              (0x0002UL << DMA_SxNDT_Pos)                    /*!< 0x00000002 */
+#define DMA_SxNDT_2              (0x0004UL << DMA_SxNDT_Pos)                    /*!< 0x00000004 */
+#define DMA_SxNDT_3              (0x0008UL << DMA_SxNDT_Pos)                    /*!< 0x00000008 */
+#define DMA_SxNDT_4              (0x0010UL << DMA_SxNDT_Pos)                    /*!< 0x00000010 */
+#define DMA_SxNDT_5              (0x0020UL << DMA_SxNDT_Pos)                    /*!< 0x00000020 */
+#define DMA_SxNDT_6              (0x0040UL << DMA_SxNDT_Pos)                    /*!< 0x00000040 */
+#define DMA_SxNDT_7              (0x0080UL << DMA_SxNDT_Pos)                    /*!< 0x00000080 */
+#define DMA_SxNDT_8              (0x0100UL << DMA_SxNDT_Pos)                    /*!< 0x00000100 */
+#define DMA_SxNDT_9              (0x0200UL << DMA_SxNDT_Pos)                    /*!< 0x00000200 */
+#define DMA_SxNDT_10             (0x0400UL << DMA_SxNDT_Pos)                    /*!< 0x00000400 */
+#define DMA_SxNDT_11             (0x0800UL << DMA_SxNDT_Pos)                    /*!< 0x00000800 */
+#define DMA_SxNDT_12             (0x1000UL << DMA_SxNDT_Pos)                    /*!< 0x00001000 */
+#define DMA_SxNDT_13             (0x2000UL << DMA_SxNDT_Pos)                    /*!< 0x00002000 */
+#define DMA_SxNDT_14             (0x4000UL << DMA_SxNDT_Pos)                    /*!< 0x00004000 */
+#define DMA_SxNDT_15             (0x8000UL << DMA_SxNDT_Pos)                    /*!< 0x00008000 */
+
+/********************  Bits definition for DMA_SxFCR register  ****************/
+#define DMA_SxFCR_FEIE_Pos       (7U)
+#define DMA_SxFCR_FEIE_Msk       (0x1UL << DMA_SxFCR_FEIE_Pos)                 /*!< 0x00000080 */
+#define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk                            /*!< FIFO error interrupt enable */
+#define DMA_SxFCR_FS_Pos         (3U)
+#define DMA_SxFCR_FS_Msk         (0x7UL << DMA_SxFCR_FS_Pos)                   /*!< 0x00000038 */
+#define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk                              /*!< FIFO status */
+#define DMA_SxFCR_FS_0           (0x1UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */
+#define DMA_SxFCR_FS_1           (0x2UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */
+#define DMA_SxFCR_FS_2           (0x4UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */
+#define DMA_SxFCR_DMDIS_Pos      (2U)
+#define DMA_SxFCR_DMDIS_Msk      (0x1UL << DMA_SxFCR_DMDIS_Pos)                /*!< 0x00000004 */
+#define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk                           /*!< Direct mode disable */
+#define DMA_SxFCR_FTH_Pos        (0U)
+#define DMA_SxFCR_FTH_Msk        (0x3UL << DMA_SxFCR_FTH_Pos)                  /*!< 0x00000003 */
+#define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk                             /*!< FIFO threshold selection */
+#define DMA_SxFCR_FTH_0          (0x1UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */
+#define DMA_SxFCR_FTH_1          (0x2UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */
+
+/********************  Bits definition for DMA_LISR register  *****************/
+#define DMA_LISR_TCIF3_Pos       (27U)
+#define DMA_LISR_TCIF3_Msk       (0x1UL << DMA_LISR_TCIF3_Pos)                 /*!< 0x08000000 */
+#define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk                            /*!<  Stream 3 transfer complete interrupt flag */
+#define DMA_LISR_HTIF3_Pos       (26U)
+#define DMA_LISR_HTIF3_Msk       (0x1UL << DMA_LISR_HTIF3_Pos)                 /*!< 0x04000000 */
+#define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk                            /*!<  Stream 3 half transfer interrupt flag */
+#define DMA_LISR_TEIF3_Pos       (25U)
+#define DMA_LISR_TEIF3_Msk       (0x1UL << DMA_LISR_TEIF3_Pos)                 /*!< 0x02000000 */
+#define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk                            /*!<  Stream 3 transfer error interrupt flag */
+#define DMA_LISR_DMEIF3_Pos      (24U)
+#define DMA_LISR_DMEIF3_Msk      (0x1UL << DMA_LISR_DMEIF3_Pos)                /*!< 0x01000000 */
+#define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk                           /*!<  Stream 3 direct mode error interrupt flag */
+#define DMA_LISR_FEIF3_Pos       (22U)
+#define DMA_LISR_FEIF3_Msk       (0x1UL << DMA_LISR_FEIF3_Pos)                 /*!< 0x00400000 */
+#define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk                            /*!<  Stream 3 FIFO error interrupt flag */
+#define DMA_LISR_TCIF2_Pos       (21U)
+#define DMA_LISR_TCIF2_Msk       (0x1UL << DMA_LISR_TCIF2_Pos)                 /*!< 0x00200000 */
+#define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk                            /*!<  Stream 2 transfer complete interrupt flag */
+#define DMA_LISR_HTIF2_Pos       (20U)
+#define DMA_LISR_HTIF2_Msk       (0x1UL << DMA_LISR_HTIF2_Pos)                 /*!< 0x00100000 */
+#define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk                            /*!<  Stream 2 half transfer interrupt flag */
+#define DMA_LISR_TEIF2_Pos       (19U)
+#define DMA_LISR_TEIF2_Msk       (0x1UL << DMA_LISR_TEIF2_Pos)                 /*!< 0x00080000 */
+#define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk                            /*!<  Stream 2 transfer error interrupt flag */
+#define DMA_LISR_DMEIF2_Pos      (18U)
+#define DMA_LISR_DMEIF2_Msk      (0x1UL << DMA_LISR_DMEIF2_Pos)                /*!< 0x00040000 */
+#define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk                           /*!<  Stream 2 direct mode error interrupt flag */
+#define DMA_LISR_FEIF2_Pos       (16U)
+#define DMA_LISR_FEIF2_Msk       (0x1UL << DMA_LISR_FEIF2_Pos)                 /*!< 0x00010000 */
+#define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk                            /*!<  Stream 2 FIFO error interrupt flag */
+#define DMA_LISR_TCIF1_Pos       (11U)
+#define DMA_LISR_TCIF1_Msk       (0x1UL << DMA_LISR_TCIF1_Pos)                 /*!< 0x00000800 */
+#define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk                            /*!<  Stream 1 transfer complete interrupt flag */
+#define DMA_LISR_HTIF1_Pos       (10U)
+#define DMA_LISR_HTIF1_Msk       (0x1UL << DMA_LISR_HTIF1_Pos)                 /*!< 0x00000400 */
+#define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk                            /*!<  Stream 1 half transfer interrupt flag */
+#define DMA_LISR_TEIF1_Pos       (9U)
+#define DMA_LISR_TEIF1_Msk       (0x1UL << DMA_LISR_TEIF1_Pos)                 /*!< 0x00000200 */
+#define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk                            /*!<  Stream 1 transfer error interrupt flag */
+#define DMA_LISR_DMEIF1_Pos      (8U)
+#define DMA_LISR_DMEIF1_Msk      (0x1UL << DMA_LISR_DMEIF1_Pos)                /*!< 0x00000100 */
+#define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk                           /*!<  Stream 1 direct mode error interrupt flag */
+#define DMA_LISR_FEIF1_Pos       (6U)
+#define DMA_LISR_FEIF1_Msk       (0x1UL << DMA_LISR_FEIF1_Pos)                 /*!< 0x00000040 */
+#define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk                            /*!<  Stream 1 FIFO error interrupt flag */
+#define DMA_LISR_TCIF0_Pos       (5U)
+#define DMA_LISR_TCIF0_Msk       (0x1UL << DMA_LISR_TCIF0_Pos)                 /*!< 0x00000020 */
+#define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk                            /*!<  Stream 0 transfer complete interrupt flag */
+#define DMA_LISR_HTIF0_Pos       (4U)
+#define DMA_LISR_HTIF0_Msk       (0x1UL << DMA_LISR_HTIF0_Pos)                 /*!< 0x00000010 */
+#define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk                            /*!<  Stream 0 half transfer interrupt flag */
+#define DMA_LISR_TEIF0_Pos       (3U)
+#define DMA_LISR_TEIF0_Msk       (0x1UL << DMA_LISR_TEIF0_Pos)                 /*!< 0x00000008 */
+#define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk                            /*!<  Stream 0 transfer error interrupt flag */
+#define DMA_LISR_DMEIF0_Pos      (2U)
+#define DMA_LISR_DMEIF0_Msk      (0x1UL << DMA_LISR_DMEIF0_Pos)                /*!< 0x00000004 */
+#define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk                           /*!<  Stream 0 direct mode error interrupt flag */
+#define DMA_LISR_FEIF0_Pos       (0U)
+#define DMA_LISR_FEIF0_Msk       (0x1UL << DMA_LISR_FEIF0_Pos)                 /*!< 0x00000001 */
+#define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk                            /*!<  Stream 0 FIFO error interrupt flag */
+
+/********************  Bits definition for DMA_HISR register  *****************/
+#define DMA_HISR_TCIF7_Pos       (27U)
+#define DMA_HISR_TCIF7_Msk       (0x1UL << DMA_HISR_TCIF7_Pos)                 /*!< 0x08000000 */
+#define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk                            /*!<  Stream 7 transfer complete interrupt flag */
+#define DMA_HISR_HTIF7_Pos       (26U)
+#define DMA_HISR_HTIF7_Msk       (0x1UL << DMA_HISR_HTIF7_Pos)                 /*!< 0x04000000 */
+#define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk                            /*!<  Stream 7 half transfer interrupt flag */
+#define DMA_HISR_TEIF7_Pos       (25U)
+#define DMA_HISR_TEIF7_Msk       (0x1UL << DMA_HISR_TEIF7_Pos)                 /*!< 0x02000000 */
+#define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk                            /*!<  Stream 7 transfer error interrupt flag */
+#define DMA_HISR_DMEIF7_Pos      (24U)
+#define DMA_HISR_DMEIF7_Msk      (0x1UL << DMA_HISR_DMEIF7_Pos)                /*!< 0x01000000 */
+#define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk                           /*!<  Stream 7 direct mode error interrupt flag */
+#define DMA_HISR_FEIF7_Pos       (22U)
+#define DMA_HISR_FEIF7_Msk       (0x1UL << DMA_HISR_FEIF7_Pos)                 /*!< 0x00400000 */
+#define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk                            /*!<  Stream 7 FIFO error interrupt flag */
+#define DMA_HISR_TCIF6_Pos       (21U)
+#define DMA_HISR_TCIF6_Msk       (0x1UL << DMA_HISR_TCIF6_Pos)                 /*!< 0x00200000 */
+#define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk                            /*!<  Stream 6 transfer complete interrupt flag */
+#define DMA_HISR_HTIF6_Pos       (20U)
+#define DMA_HISR_HTIF6_Msk       (0x1UL << DMA_HISR_HTIF6_Pos)                 /*!< 0x00100000 */
+#define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk                            /*!<  Stream 6 half transfer interrupt flag */
+#define DMA_HISR_TEIF6_Pos       (19U)
+#define DMA_HISR_TEIF6_Msk       (0x1UL << DMA_HISR_TEIF6_Pos)                 /*!< 0x00080000 */
+#define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk                            /*!<  Stream 6 transfer error interrupt flag */
+#define DMA_HISR_DMEIF6_Pos      (18U)
+#define DMA_HISR_DMEIF6_Msk      (0x1UL << DMA_HISR_DMEIF6_Pos)                /*!< 0x00040000 */
+#define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk                           /*!<  Stream 6 direct mode error interrupt flag */
+#define DMA_HISR_FEIF6_Pos       (16U)
+#define DMA_HISR_FEIF6_Msk       (0x1UL << DMA_HISR_FEIF6_Pos)                 /*!< 0x00010000 */
+#define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk                            /*!<  Stream 6 FIFO error interrupt flag */
+#define DMA_HISR_TCIF5_Pos       (11U)
+#define DMA_HISR_TCIF5_Msk       (0x1UL << DMA_HISR_TCIF5_Pos)                 /*!< 0x00000800 */
+#define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk                            /*!<  Stream 5 transfer complete interrupt flag */
+#define DMA_HISR_HTIF5_Pos       (10U)
+#define DMA_HISR_HTIF5_Msk       (0x1UL << DMA_HISR_HTIF5_Pos)                 /*!< 0x00000400 */
+#define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk                            /*!<  Stream 5 half transfer interrupt flag */
+#define DMA_HISR_TEIF5_Pos       (9U)
+#define DMA_HISR_TEIF5_Msk       (0x1UL << DMA_HISR_TEIF5_Pos)                 /*!< 0x00000200 */
+#define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk                            /*!<  Stream 5 transfer error interrupt flag */
+#define DMA_HISR_DMEIF5_Pos      (8U)
+#define DMA_HISR_DMEIF5_Msk      (0x1UL << DMA_HISR_DMEIF5_Pos)                /*!< 0x00000100 */
+#define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk                           /*!<  Stream 5 direct mode error interrupt flag */
+#define DMA_HISR_FEIF5_Pos       (6U)
+#define DMA_HISR_FEIF5_Msk       (0x1UL << DMA_HISR_FEIF5_Pos)                 /*!< 0x00000040 */
+#define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk                            /*!<  Stream 5 FIFO error interrupt flag */
+#define DMA_HISR_TCIF4_Pos       (5U)
+#define DMA_HISR_TCIF4_Msk       (0x1UL << DMA_HISR_TCIF4_Pos)                 /*!< 0x00000020 */
+#define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk                            /*!<  Stream 4 transfer complete interrupt flag */
+#define DMA_HISR_HTIF4_Pos       (4U)
+#define DMA_HISR_HTIF4_Msk       (0x1UL << DMA_HISR_HTIF4_Pos)                 /*!< 0x00000010 */
+#define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk                            /*!<  Stream 4 half transfer interrupt flag */
+#define DMA_HISR_TEIF4_Pos       (3U)
+#define DMA_HISR_TEIF4_Msk       (0x1UL << DMA_HISR_TEIF4_Pos)                 /*!< 0x00000008 */
+#define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk                            /*!<  Stream 4 transfer error interrupt flag */
+#define DMA_HISR_DMEIF4_Pos      (2U)
+#define DMA_HISR_DMEIF4_Msk      (0x1UL << DMA_HISR_DMEIF4_Pos)                /*!< 0x00000004 */
+#define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk                           /*!<  Stream 4 direct mode error interrupt flag */
+#define DMA_HISR_FEIF4_Pos       (0U)
+#define DMA_HISR_FEIF4_Msk       (0x1UL << DMA_HISR_FEIF4_Pos)                 /*!< 0x00000001 */
+#define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk                            /*!<  Stream 4 FIFO error interrupt flag */
+
+/********************  Bits definition for DMA_LIFCR register  ****************/
+#define DMA_LIFCR_CTCIF3_Pos     (27U)
+#define DMA_LIFCR_CTCIF3_Msk     (0x1UL << DMA_LIFCR_CTCIF3_Pos)               /*!< 0x08000000 */
+#define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk                          /*!<  Stream 3 clear transfer complete interrupt flag */
+#define DMA_LIFCR_CHTIF3_Pos     (26U)
+#define DMA_LIFCR_CHTIF3_Msk     (0x1UL << DMA_LIFCR_CHTIF3_Pos)               /*!< 0x04000000 */
+#define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk                          /*!<  Stream 3 clear half transfer interrupt flag */
+#define DMA_LIFCR_CTEIF3_Pos     (25U)
+#define DMA_LIFCR_CTEIF3_Msk     (0x1UL << DMA_LIFCR_CTEIF3_Pos)               /*!< 0x02000000 */
+#define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk                          /*!<  Stream 3 clear transfer error interrupt flag */
+#define DMA_LIFCR_CDMEIF3_Pos    (24U)
+#define DMA_LIFCR_CDMEIF3_Msk    (0x1UL << DMA_LIFCR_CDMEIF3_Pos)              /*!< 0x01000000 */
+#define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk                         /*!<  Stream 3 clear direct mode error interrupt flag */
+#define DMA_LIFCR_CFEIF3_Pos     (22U)
+#define DMA_LIFCR_CFEIF3_Msk     (0x1UL << DMA_LIFCR_CFEIF3_Pos)               /*!< 0x00400000 */
+#define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk                          /*!<  Stream 3 clear FIFO error interrupt flag */
+#define DMA_LIFCR_CTCIF2_Pos     (21U)
+#define DMA_LIFCR_CTCIF2_Msk     (0x1UL << DMA_LIFCR_CTCIF2_Pos)               /*!< 0x00200000 */
+#define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk                          /*!<  Stream 2 clear transfer complete interrupt flag */
+#define DMA_LIFCR_CHTIF2_Pos     (20U)
+#define DMA_LIFCR_CHTIF2_Msk     (0x1UL << DMA_LIFCR_CHTIF2_Pos)               /*!< 0x00100000 */
+#define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk                          /*!<  Stream 2 clear half transfer interrupt flag */
+#define DMA_LIFCR_CTEIF2_Pos     (19U)
+#define DMA_LIFCR_CTEIF2_Msk     (0x1UL << DMA_LIFCR_CTEIF2_Pos)               /*!< 0x00080000 */
+#define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk                          /*!<  Stream 2 clear transfer error interrupt flag */
+#define DMA_LIFCR_CDMEIF2_Pos    (18U)
+#define DMA_LIFCR_CDMEIF2_Msk    (0x1UL << DMA_LIFCR_CDMEIF2_Pos)              /*!< 0x00040000 */
+#define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk                         /*!<  Stream 2 clear direct mode error interrupt flag */
+#define DMA_LIFCR_CFEIF2_Pos     (16U)
+#define DMA_LIFCR_CFEIF2_Msk     (0x1UL << DMA_LIFCR_CFEIF2_Pos)               /*!< 0x00010000 */
+#define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk                          /*!<  Stream 2 clear FIFO error interrupt flag */
+#define DMA_LIFCR_CTCIF1_Pos     (11U)
+#define DMA_LIFCR_CTCIF1_Msk     (0x1UL << DMA_LIFCR_CTCIF1_Pos)               /*!< 0x00000800 */
+#define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk                          /*!<  Stream 1 clear transfer complete interrupt flag */
+#define DMA_LIFCR_CHTIF1_Pos     (10U)
+#define DMA_LIFCR_CHTIF1_Msk     (0x1UL << DMA_LIFCR_CHTIF1_Pos)               /*!< 0x00000400 */
+#define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk                          /*!<  Stream 1 clear half transfer interrupt flag */
+#define DMA_LIFCR_CTEIF1_Pos     (9U)
+#define DMA_LIFCR_CTEIF1_Msk     (0x1UL << DMA_LIFCR_CTEIF1_Pos)               /*!< 0x00000200 */
+#define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk                          /*!<  Stream 1 clear transfer error interrupt flag */
+#define DMA_LIFCR_CDMEIF1_Pos    (8U)
+#define DMA_LIFCR_CDMEIF1_Msk    (0x1UL << DMA_LIFCR_CDMEIF1_Pos)              /*!< 0x00000100 */
+#define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk                         /*!<  Stream 1 clear direct mode error interrupt flag */
+#define DMA_LIFCR_CFEIF1_Pos     (6U)
+#define DMA_LIFCR_CFEIF1_Msk     (0x1UL << DMA_LIFCR_CFEIF1_Pos)               /*!< 0x00000040 */
+#define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk                          /*!<  Stream 1 clear FIFO error interrupt flag */
+#define DMA_LIFCR_CTCIF0_Pos     (5U)
+#define DMA_LIFCR_CTCIF0_Msk     (0x1UL << DMA_LIFCR_CTCIF0_Pos)               /*!< 0x00000020 */
+#define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk                          /*!<  Stream 0 clear transfer complete interrupt flag */
+#define DMA_LIFCR_CHTIF0_Pos     (4U)
+#define DMA_LIFCR_CHTIF0_Msk     (0x1UL << DMA_LIFCR_CHTIF0_Pos)               /*!< 0x00000010 */
+#define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk                          /*!<  Stream 0 clear half transfer interrupt flag */
+#define DMA_LIFCR_CTEIF0_Pos     (3U)
+#define DMA_LIFCR_CTEIF0_Msk     (0x1UL << DMA_LIFCR_CTEIF0_Pos)               /*!< 0x00000008 */
+#define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk                          /*!<  Stream 0 clear transfer error interrupt flag */
+#define DMA_LIFCR_CDMEIF0_Pos    (2U)
+#define DMA_LIFCR_CDMEIF0_Msk    (0x1UL << DMA_LIFCR_CDMEIF0_Pos)              /*!< 0x00000004 */
+#define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk                         /*!<  Stream 0 clear direct mode error interrupt flag */
+#define DMA_LIFCR_CFEIF0_Pos     (0U)
+#define DMA_LIFCR_CFEIF0_Msk     (0x1UL << DMA_LIFCR_CFEIF0_Pos)               /*!< 0x00000001 */
+#define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk                          /*!<  Stream 0 clear FIFO error interrupt flag */
+
+/********************  Bits definition for DMA_HIFCR  register  ****************/
+#define DMA_HIFCR_CTCIF7_Pos     (27U)
+#define DMA_HIFCR_CTCIF7_Msk     (0x1UL << DMA_HIFCR_CTCIF7_Pos)               /*!< 0x08000000 */
+#define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk                          /*!<  Stream 7 clear transfer complete interrupt flag */
+#define DMA_HIFCR_CHTIF7_Pos     (26U)
+#define DMA_HIFCR_CHTIF7_Msk     (0x1UL << DMA_HIFCR_CHTIF7_Pos)               /*!< 0x04000000 */
+#define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk                          /*!<  Stream 7 clear half transfer interrupt flag */
+#define DMA_HIFCR_CTEIF7_Pos     (25U)
+#define DMA_HIFCR_CTEIF7_Msk     (0x1UL << DMA_HIFCR_CTEIF7_Pos)               /*!< 0x02000000 */
+#define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk                          /*!<  Stream 7 clear transfer error interrupt flag */
+#define DMA_HIFCR_CDMEIF7_Pos    (24U)
+#define DMA_HIFCR_CDMEIF7_Msk    (0x1UL << DMA_HIFCR_CDMEIF7_Pos)              /*!< 0x01000000 */
+#define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk                         /*!<  Stream 7 clear direct mode error interrupt flag */
+#define DMA_HIFCR_CFEIF7_Pos     (22U)
+#define DMA_HIFCR_CFEIF7_Msk     (0x1UL << DMA_HIFCR_CFEIF7_Pos)               /*!< 0x00400000 */
+#define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk                          /*!<  Stream 7 clear FIFO error interrupt flag */
+#define DMA_HIFCR_CTCIF6_Pos     (21U)
+#define DMA_HIFCR_CTCIF6_Msk     (0x1UL << DMA_HIFCR_CTCIF6_Pos)               /*!< 0x00200000 */
+#define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk                          /*!<  Stream 6 clear transfer complete interrupt flag */
+#define DMA_HIFCR_CHTIF6_Pos     (20U)
+#define DMA_HIFCR_CHTIF6_Msk     (0x1UL << DMA_HIFCR_CHTIF6_Pos)               /*!< 0x00100000 */
+#define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk                          /*!<  Stream 6 clear half transfer interrupt flag */
+#define DMA_HIFCR_CTEIF6_Pos     (19U)
+#define DMA_HIFCR_CTEIF6_Msk     (0x1UL << DMA_HIFCR_CTEIF6_Pos)               /*!< 0x00080000 */
+#define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk                          /*!<  Stream 6 clear transfer error interrupt flag */
+#define DMA_HIFCR_CDMEIF6_Pos    (18U)
+#define DMA_HIFCR_CDMEIF6_Msk    (0x1UL << DMA_HIFCR_CDMEIF6_Pos)              /*!< 0x00040000 */
+#define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk                         /*!<  Stream 6 clear direct mode error interrupt flag */
+#define DMA_HIFCR_CFEIF6_Pos     (16U)
+#define DMA_HIFCR_CFEIF6_Msk     (0x1UL << DMA_HIFCR_CFEIF6_Pos)               /*!< 0x00010000 */
+#define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk                          /*!<  Stream 6 clear FIFO error interrupt flag */
+#define DMA_HIFCR_CTCIF5_Pos     (11U)
+#define DMA_HIFCR_CTCIF5_Msk     (0x1UL << DMA_HIFCR_CTCIF5_Pos)               /*!< 0x00000800 */
+#define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk                          /*!<  Stream 5 clear transfer complete interrupt flag */
+#define DMA_HIFCR_CHTIF5_Pos     (10U)
+#define DMA_HIFCR_CHTIF5_Msk     (0x1UL << DMA_HIFCR_CHTIF5_Pos)               /*!< 0x00000400 */
+#define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk                          /*!<  Stream 5 clear half transfer interrupt flag */
+#define DMA_HIFCR_CTEIF5_Pos     (9U)
+#define DMA_HIFCR_CTEIF5_Msk     (0x1UL << DMA_HIFCR_CTEIF5_Pos)               /*!< 0x00000200 */
+#define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk                          /*!<  Stream 5 clear transfer error interrupt flag */
+#define DMA_HIFCR_CDMEIF5_Pos    (8U)
+#define DMA_HIFCR_CDMEIF5_Msk    (0x1UL << DMA_HIFCR_CDMEIF5_Pos)              /*!< 0x00000100 */
+#define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk                         /*!<  Stream 5 clear direct mode error interrupt flag */
+#define DMA_HIFCR_CFEIF5_Pos     (6U)
+#define DMA_HIFCR_CFEIF5_Msk     (0x1UL << DMA_HIFCR_CFEIF5_Pos)               /*!< 0x00000040 */
+#define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk                          /*!<  Stream 5 clear FIFO error interrupt flag */
+#define DMA_HIFCR_CTCIF4_Pos     (5U)
+#define DMA_HIFCR_CTCIF4_Msk     (0x1UL << DMA_HIFCR_CTCIF4_Pos)               /*!< 0x00000020 */
+#define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk                          /*!<  Stream 4 clear transfer complete interrupt flag */
+#define DMA_HIFCR_CHTIF4_Pos     (4U)
+#define DMA_HIFCR_CHTIF4_Msk     (0x1UL << DMA_HIFCR_CHTIF4_Pos)               /*!< 0x00000010 */
+#define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk                          /*!<  Stream 4 clear half transfer interrupt flag */
+#define DMA_HIFCR_CTEIF4_Pos     (3U)
+#define DMA_HIFCR_CTEIF4_Msk     (0x1UL << DMA_HIFCR_CTEIF4_Pos)               /*!< 0x00000008 */
+#define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk                          /*!<  Stream 4 clear transfer error interrupt flag */
+#define DMA_HIFCR_CDMEIF4_Pos    (2U)
+#define DMA_HIFCR_CDMEIF4_Msk    (0x1UL << DMA_HIFCR_CDMEIF4_Pos)              /*!< 0x00000004 */
+#define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk                         /*!<  Stream 4 clear direct mode error interrupt flag */
+#define DMA_HIFCR_CFEIF4_Pos     (0U)
+#define DMA_HIFCR_CFEIF4_Msk     (0x1UL << DMA_HIFCR_CFEIF4_Pos)               /*!< 0x00000001 */
+#define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk                          /*!<  Stream 4 clear FIFO error interrupt flag */
+
+/******************  Bit definition for DMA_SxPAR register  ********************/
+#define DMA_SxPAR_PA_Pos         (0U)
+#define DMA_SxPAR_PA_Msk         (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)            /*!< 0xFFFFFFFF */
+#define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_SxM0AR register  ********************/
+#define DMA_SxM0AR_M0A_Pos       (0U)
+#define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)          /*!< 0xFFFFFFFF */
+#define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory 0 Address */
+
+/******************  Bit definition for DMA_SxM1AR register  ********************/
+#define DMA_SxM1AR_M1A_Pos       (0U)
+#define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)          /*!< 0xFFFFFFFF */
+#define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory 1 Address */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             DMAMUX Controller                              */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for DMAMUX_CxCR register  **************/
+#define DMAMUX_CxCR_DMAREQ_ID_Pos      (0U)
+#define DMAMUX_CxCR_DMAREQ_ID_Msk      (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)   /*!< 0x000000FF */
+#define DMAMUX_CxCR_DMAREQ_ID          DMAMUX_CxCR_DMAREQ_ID_Msk               /*!<  DMA request identification */
+#define DMAMUX_CxCR_DMAREQ_ID_0        (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000001 */
+#define DMAMUX_CxCR_DMAREQ_ID_1        (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000002 */
+#define DMAMUX_CxCR_DMAREQ_ID_2        (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000004 */
+#define DMAMUX_CxCR_DMAREQ_ID_3        (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000008 */
+#define DMAMUX_CxCR_DMAREQ_ID_4        (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000010 */
+#define DMAMUX_CxCR_DMAREQ_ID_5        (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000020 */
+#define DMAMUX_CxCR_DMAREQ_ID_6        (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000040 */
+#define DMAMUX_CxCR_DMAREQ_ID_7        (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000080 */
+#define DMAMUX_CxCR_SOIE_Pos           (8U)
+#define DMAMUX_CxCR_SOIE_Msk           (0x1UL << DMAMUX_CxCR_SOIE_Pos)         /*!< 0x00000100 */
+#define DMAMUX_CxCR_SOIE               DMAMUX_CxCR_SOIE_Msk                    /*!<  Synchronization overrun interrupt enable */
+#define DMAMUX_CxCR_EGE_Pos            (9U)
+#define DMAMUX_CxCR_EGE_Msk            (0x1UL << DMAMUX_CxCR_EGE_Pos)          /*!< 0x00000200 */
+#define DMAMUX_CxCR_EGE                DMAMUX_CxCR_EGE_Msk                     /*!<  Event generation enable */
+#define DMAMUX_CxCR_SE_Pos             (16U)
+#define DMAMUX_CxCR_SE_Msk             (0x1UL << DMAMUX_CxCR_SE_Pos)           /*!< 0x00010000 */
+#define DMAMUX_CxCR_SE                 DMAMUX_CxCR_SE_Msk                      /*!<  Synchronization enable */
+#define DMAMUX_CxCR_SPOL_Pos           (17U)
+#define DMAMUX_CxCR_SPOL_Msk           (0x3UL << DMAMUX_CxCR_SPOL_Pos)         /*!< 0x00060000 */
+#define DMAMUX_CxCR_SPOL               DMAMUX_CxCR_SPOL_Msk                    /*!<  Synchronization polarity */
+#define DMAMUX_CxCR_SPOL_0             (0x1UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00020000 */
+#define DMAMUX_CxCR_SPOL_1             (0x2UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00040000 */
+#define DMAMUX_CxCR_NBREQ_Pos          (19U)
+#define DMAMUX_CxCR_NBREQ_Msk          (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)       /*!< 0x00F80000 */
+#define DMAMUX_CxCR_NBREQ              DMAMUX_CxCR_NBREQ_Msk                   /*!<  Number of DMA requests minus 1 to forward */
+#define DMAMUX_CxCR_NBREQ_0            (0x01UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00080000 */
+#define DMAMUX_CxCR_NBREQ_1            (0x02UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00100000 */
+#define DMAMUX_CxCR_NBREQ_2            (0x04UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00200000 */
+#define DMAMUX_CxCR_NBREQ_3            (0x08UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00400000 */
+#define DMAMUX_CxCR_NBREQ_4            (0x10UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00800000 */
+#define DMAMUX_CxCR_SYNC_ID_Pos        (24U)
+#define DMAMUX_CxCR_SYNC_ID_Msk        (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)     /*!< 0x1F000000 */
+#define DMAMUX_CxCR_SYNC_ID            DMAMUX_CxCR_SYNC_ID_Msk                 /*!<  Synchronization identification */
+#define DMAMUX_CxCR_SYNC_ID_0          (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x01000000 */
+#define DMAMUX_CxCR_SYNC_ID_1          (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x02000000 */
+#define DMAMUX_CxCR_SYNC_ID_2          (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x04000000 */
+#define DMAMUX_CxCR_SYNC_ID_3          (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x08000000 */
+#define DMAMUX_CxCR_SYNC_ID_4          (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x10000000 */
+
+/********************  Bits definition for DMAMUX_CSR register  **************/
+#define DMAMUX_CSR_SOF0_Pos            (0U)
+#define DMAMUX_CSR_SOF0_Msk            (0x1UL << DMAMUX_CSR_SOF0_Pos)          /*!< 0x00000001 */
+#define DMAMUX_CSR_SOF0                DMAMUX_CSR_SOF0_Msk                     /*!< Channel 0 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF1_Pos            (1U)
+#define DMAMUX_CSR_SOF1_Msk            (0x1UL << DMAMUX_CSR_SOF1_Pos)          /*!< 0x00000002 */
+#define DMAMUX_CSR_SOF1                DMAMUX_CSR_SOF1_Msk                     /*!< Channel 1 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF2_Pos            (2U)
+#define DMAMUX_CSR_SOF2_Msk            (0x1UL << DMAMUX_CSR_SOF2_Pos)          /*!< 0x00000004 */
+#define DMAMUX_CSR_SOF2                DMAMUX_CSR_SOF2_Msk                     /*!< Channel 2 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF3_Pos            (3U)
+#define DMAMUX_CSR_SOF3_Msk            (0x1UL << DMAMUX_CSR_SOF3_Pos)          /*!< 0x00000008 */
+#define DMAMUX_CSR_SOF3                DMAMUX_CSR_SOF3_Msk                     /*!< Channel 3 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF4_Pos            (4U)
+#define DMAMUX_CSR_SOF4_Msk            (0x1UL << DMAMUX_CSR_SOF4_Pos)          /*!< 0x00000010 */
+#define DMAMUX_CSR_SOF4                DMAMUX_CSR_SOF4_Msk                     /*!< Channel 4 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF5_Pos            (5U)
+#define DMAMUX_CSR_SOF5_Msk            (0x1UL << DMAMUX_CSR_SOF5_Pos)          /*!< 0x00000020 */
+#define DMAMUX_CSR_SOF5                DMAMUX_CSR_SOF5_Msk                     /*!< Channel 5 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF6_Pos            (6U)
+#define DMAMUX_CSR_SOF6_Msk            (0x1UL << DMAMUX_CSR_SOF6_Pos)          /*!< 0x00000040 */
+#define DMAMUX_CSR_SOF6                DMAMUX_CSR_SOF6_Msk                     /*!< Channel 6 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF7_Pos            (7U)
+#define DMAMUX_CSR_SOF7_Msk            (0x1UL << DMAMUX_CSR_SOF7_Pos)          /*!< 0x00000080 */
+#define DMAMUX_CSR_SOF7                DMAMUX_CSR_SOF7_Msk                     /*!< Channel 7 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF8_Pos            (8U)
+#define DMAMUX_CSR_SOF8_Msk            (0x1UL << DMAMUX_CSR_SOF8_Pos)          /*!< 0x00000100 */
+#define DMAMUX_CSR_SOF8                DMAMUX_CSR_SOF8_Msk                     /*!< Channel 8 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF9_Pos            (9U)
+#define DMAMUX_CSR_SOF9_Msk            (0x1UL << DMAMUX_CSR_SOF9_Pos)          /*!< 0x00000200 */
+#define DMAMUX_CSR_SOF9                DMAMUX_CSR_SOF9_Msk                     /*!< Channel 9 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF10_Pos           (10U)
+#define DMAMUX_CSR_SOF10_Msk           (0x1UL << DMAMUX_CSR_SOF10_Pos)         /*!< 0x00000400 */
+#define DMAMUX_CSR_SOF10               DMAMUX_CSR_SOF10_Msk                    /*!< Channel 10 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF11_Pos           (11U)
+#define DMAMUX_CSR_SOF11_Msk           (0x1UL << DMAMUX_CSR_SOF11_Pos)         /*!< 0x00000800 */
+#define DMAMUX_CSR_SOF11               DMAMUX_CSR_SOF11_Msk                    /*!< Channel 11 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF12_Pos           (12U)
+#define DMAMUX_CSR_SOF12_Msk           (0x1UL << DMAMUX_CSR_SOF12_Pos)         /*!< 0x00001000 */
+#define DMAMUX_CSR_SOF12               DMAMUX_CSR_SOF12_Msk                    /*!< Channel 12 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF13_Pos           (13U)
+#define DMAMUX_CSR_SOF13_Msk           (0x1UL << DMAMUX_CSR_SOF13_Pos)         /*!< 0x00002000 */
+#define DMAMUX_CSR_SOF13               DMAMUX_CSR_SOF13_Msk                    /*!< Channel 13 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF14_Pos           (14U)
+#define DMAMUX_CSR_SOF14_Msk           (0x1UL << DMAMUX_CSR_SOF14_Pos)         /*!< 0x00004000 */
+#define DMAMUX_CSR_SOF14               DMAMUX_CSR_SOF14_Msk                    /*!< Channel 14 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF15_Pos           (15U)
+#define DMAMUX_CSR_SOF15_Msk           (0x1UL << DMAMUX_CSR_SOF15_Pos)         /*!< 0x00008000 */
+#define DMAMUX_CSR_SOF15               DMAMUX_CSR_SOF15_Msk                    /*!< Channel 15 Synchronization overrun event flag */
+
+/********************  Bits definition for DMAMUX_CFR register  **************/
+#define DMAMUX_CFR_CSOF0_Pos           (0U)
+#define DMAMUX_CFR_CSOF0_Msk           (0x1UL << DMAMUX_CFR_CSOF0_Pos)         /*!< 0x00000001 */
+#define DMAMUX_CFR_CSOF0               DMAMUX_CFR_CSOF0_Msk                    /*!< Channel 0 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF1_Pos           (1U)
+#define DMAMUX_CFR_CSOF1_Msk           (0x1UL << DMAMUX_CFR_CSOF1_Pos)         /*!< 0x00000002 */
+#define DMAMUX_CFR_CSOF1               DMAMUX_CFR_CSOF1_Msk                    /*!< Channel 1 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF2_Pos           (2U)
+#define DMAMUX_CFR_CSOF2_Msk           (0x1UL << DMAMUX_CFR_CSOF2_Pos)         /*!< 0x00000004 */
+#define DMAMUX_CFR_CSOF2               DMAMUX_CFR_CSOF2_Msk                    /*!< Channel 2 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF3_Pos           (3U)
+#define DMAMUX_CFR_CSOF3_Msk           (0x1UL << DMAMUX_CFR_CSOF3_Pos)         /*!< 0x00000008 */
+#define DMAMUX_CFR_CSOF3               DMAMUX_CFR_CSOF3_Msk                    /*!< Channel 3 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF4_Pos           (4U)
+#define DMAMUX_CFR_CSOF4_Msk           (0x1UL << DMAMUX_CFR_CSOF4_Pos)         /*!< 0x00000010 */
+#define DMAMUX_CFR_CSOF4               DMAMUX_CFR_CSOF4_Msk                    /*!< Channel 4 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF5_Pos           (5U)
+#define DMAMUX_CFR_CSOF5_Msk           (0x1UL << DMAMUX_CFR_CSOF5_Pos)         /*!< 0x00000020 */
+#define DMAMUX_CFR_CSOF5               DMAMUX_CFR_CSOF5_Msk                    /*!< Channel 5 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF6_Pos           (6U)
+#define DMAMUX_CFR_CSOF6_Msk           (0x1UL << DMAMUX_CFR_CSOF6_Pos)         /*!< 0x00000040 */
+#define DMAMUX_CFR_CSOF6               DMAMUX_CFR_CSOF6_Msk                    /*!< Channel 6 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF7_Pos           (7U)
+#define DMAMUX_CFR_CSOF7_Msk           (0x1UL << DMAMUX_CFR_CSOF7_Pos)         /*!< 0x00000080 */
+#define DMAMUX_CFR_CSOF7               DMAMUX_CFR_CSOF7_Msk                    /*!< Channel 7 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF8_Pos           (8U)
+#define DMAMUX_CFR_CSOF8_Msk           (0x1UL << DMAMUX_CFR_CSOF8_Pos)         /*!< 0x00000100 */
+#define DMAMUX_CFR_CSOF8               DMAMUX_CFR_CSOF8_Msk                    /*!< Channel 8 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF9_Pos           (9U)
+#define DMAMUX_CFR_CSOF9_Msk           (0x1UL << DMAMUX_CFR_CSOF9_Pos)         /*!< 0x00000200 */
+#define DMAMUX_CFR_CSOF9               DMAMUX_CFR_CSOF9_Msk                    /*!< Channel 9 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF10_Pos          (10U)
+#define DMAMUX_CFR_CSOF10_Msk          (0x1UL << DMAMUX_CFR_CSOF10_Pos)        /*!< 0x00000400 */
+#define DMAMUX_CFR_CSOF10              DMAMUX_CFR_CSOF10_Msk                   /*!< Channel 10 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF11_Pos          (11U)
+#define DMAMUX_CFR_CSOF11_Msk          (0x1UL << DMAMUX_CFR_CSOF11_Pos)        /*!< 0x00000800 */
+#define DMAMUX_CFR_CSOF11              DMAMUX_CFR_CSOF11_Msk                   /*!< Channel 11 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF12_Pos          (12U)
+#define DMAMUX_CFR_CSOF12_Msk          (0x1UL << DMAMUX_CFR_CSOF12_Pos)        /*!< 0x00001000 */
+#define DMAMUX_CFR_CSOF12              DMAMUX_CFR_CSOF12_Msk                   /*!< Channel 12 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF13_Pos          (13U)
+#define DMAMUX_CFR_CSOF13_Msk          (0x1UL << DMAMUX_CFR_CSOF13_Pos)        /*!< 0x00002000 */
+#define DMAMUX_CFR_CSOF13              DMAMUX_CFR_CSOF13_Msk                   /*!< Channel 13 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF14_Pos          (14U)
+#define DMAMUX_CFR_CSOF14_Msk          (0x1UL << DMAMUX_CFR_CSOF14_Pos)        /*!< 0x00004000 */
+#define DMAMUX_CFR_CSOF14              DMAMUX_CFR_CSOF14_Msk                   /*!< Channel 14 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF15_Pos          (15U)
+#define DMAMUX_CFR_CSOF15_Msk          (0x1UL << DMAMUX_CFR_CSOF15_Pos)        /*!< 0x00008000 */
+#define DMAMUX_CFR_CSOF15              DMAMUX_CFR_CSOF15_Msk                   /*!< Channel 15 Clear synchronization overrun event flag */
+
+/********************  Bits definition for DMAMUX_RGxCR register  ************/
+#define DMAMUX_RGxCR_SIG_ID_Pos        (0U)
+#define DMAMUX_RGxCR_SIG_ID_Msk        (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)     /*!< 0x0000001F */
+#define DMAMUX_RGxCR_SIG_ID            DMAMUX_RGxCR_SIG_ID_Msk                 /*!< Signal identification */
+#define DMAMUX_RGxCR_SIG_ID_0          (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000001 */
+#define DMAMUX_RGxCR_SIG_ID_1          (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000002 */
+#define DMAMUX_RGxCR_SIG_ID_2          (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000004 */
+#define DMAMUX_RGxCR_SIG_ID_3          (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000008 */
+#define DMAMUX_RGxCR_SIG_ID_4          (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000010 */
+#define DMAMUX_RGxCR_OIE_Pos           (8U)
+#define DMAMUX_RGxCR_OIE_Msk           (0x1UL << DMAMUX_RGxCR_OIE_Pos)         /*!< 0x00000100 */
+#define DMAMUX_RGxCR_OIE               DMAMUX_RGxCR_OIE_Msk                    /*!< Trigger overrun interrupt enable */
+#define DMAMUX_RGxCR_GE_Pos            (16U)
+#define DMAMUX_RGxCR_GE_Msk            (0x1UL << DMAMUX_RGxCR_GE_Pos)          /*!< 0x00010000 */
+#define DMAMUX_RGxCR_GE                DMAMUX_RGxCR_GE_Msk                     /*!< DMA request generator enable */
+#define DMAMUX_RGxCR_GPOL_Pos          (17U)
+#define DMAMUX_RGxCR_GPOL_Msk          (0x3UL << DMAMUX_RGxCR_GPOL_Pos)        /*!< 0x00060000 */
+#define DMAMUX_RGxCR_GPOL              DMAMUX_RGxCR_GPOL_Msk                   /*!< DMA request generator trigger polarity */
+#define DMAMUX_RGxCR_GPOL_0            (0x1UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00020000 */
+#define DMAMUX_RGxCR_GPOL_1            (0x2UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00040000 */
+#define DMAMUX_RGxCR_GNBREQ_Pos        (19U)
+#define DMAMUX_RGxCR_GNBREQ_Msk        (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)     /*!< 0x00F80000 */
+#define DMAMUX_RGxCR_GNBREQ            DMAMUX_RGxCR_GNBREQ_Msk                 /*!< Number of DMA requests to be generated */
+#define DMAMUX_RGxCR_GNBREQ_0          (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00080000 */
+#define DMAMUX_RGxCR_GNBREQ_1          (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00100000 */
+#define DMAMUX_RGxCR_GNBREQ_2          (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00200000 */
+#define DMAMUX_RGxCR_GNBREQ_3          (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00400000 */
+#define DMAMUX_RGxCR_GNBREQ_4          (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00800000 */
+
+/********************  Bits definition for DMAMUX_RGSR register  **************/
+#define DMAMUX_RGSR_OF0_Pos            (0U)
+#define DMAMUX_RGSR_OF0_Msk            (0x1UL << DMAMUX_RGSR_OF0_Pos)          /*!< 0x00000001 */
+#define DMAMUX_RGSR_OF0                DMAMUX_RGSR_OF0_Msk                     /*!< Request generator channel 0 Trigger overrun event flag */
+#define DMAMUX_RGSR_OF1_Pos            (1U)
+#define DMAMUX_RGSR_OF1_Msk            (0x1UL << DMAMUX_RGSR_OF1_Pos)          /*!< 0x00000002 */
+#define DMAMUX_RGSR_OF1                DMAMUX_RGSR_OF1_Msk                     /*!< Request generator channel 1 Trigger overrun event flag */
+#define DMAMUX_RGSR_OF2_Pos            (2U)
+#define DMAMUX_RGSR_OF2_Msk            (0x1UL << DMAMUX_RGSR_OF2_Pos)          /*!< 0x00000004 */
+#define DMAMUX_RGSR_OF2                DMAMUX_RGSR_OF2_Msk                     /*!< Request generator channel 2 Trigger overrun event flag */
+#define DMAMUX_RGSR_OF3_Pos            (3U)
+#define DMAMUX_RGSR_OF3_Msk            (0x1UL << DMAMUX_RGSR_OF3_Pos)          /*!< 0x00000008 */
+#define DMAMUX_RGSR_OF3                DMAMUX_RGSR_OF3_Msk                     /*!< Request generator channel 3 Trigger overrun event flag */
+#define DMAMUX_RGSR_OF4_Pos            (4U)
+#define DMAMUX_RGSR_OF4_Msk            (0x1UL << DMAMUX_RGSR_OF4_Pos)          /*!< 0x00000010 */
+#define DMAMUX_RGSR_OF4                DMAMUX_RGSR_OF4_Msk                     /*!< Request generator channel 4 Trigger overrun event flag */
+#define DMAMUX_RGSR_OF5_Pos            (5U)
+#define DMAMUX_RGSR_OF5_Msk            (0x1UL << DMAMUX_RGSR_OF5_Pos)          /*!< 0x00000020 */
+#define DMAMUX_RGSR_OF5                DMAMUX_RGSR_OF5_Msk                     /*!< Request generator channel 5 Trigger overrun event flag */
+#define DMAMUX_RGSR_OF6_Pos            (6U)
+#define DMAMUX_RGSR_OF6_Msk            (0x1UL << DMAMUX_RGSR_OF6_Pos)          /*!< 0x00000040 */
+#define DMAMUX_RGSR_OF6                DMAMUX_RGSR_OF6_Msk                     /*!< Request generator channel 6 Trigger overrun event flag */
+#define DMAMUX_RGSR_OF7_Pos            (7U)
+#define DMAMUX_RGSR_OF7_Msk            (0x1UL << DMAMUX_RGSR_OF7_Pos)          /*!< 0x00000080 */
+#define DMAMUX_RGSR_OF7                DMAMUX_RGSR_OF7_Msk                     /*!< Request generator channel 7 Trigger overrun event flag */
+
+/********************  Bits definition for DMAMUX_RGCFR register  **************/
+#define DMAMUX_RGCFR_COF0_Pos          (0U)
+#define DMAMUX_RGCFR_COF0_Msk          (0x1UL << DMAMUX_RGCFR_COF0_Pos)        /*!< 0x00000001 */
+#define DMAMUX_RGCFR_COF0              DMAMUX_RGCFR_COF0_Msk                   /*!< Request generator channel 0 Clear trigger overrun event flag */
+#define DMAMUX_RGCFR_COF1_Pos          (1U)
+#define DMAMUX_RGCFR_COF1_Msk          (0x1UL << DMAMUX_RGCFR_COF1_Pos)        /*!< 0x00000002 */
+#define DMAMUX_RGCFR_COF1              DMAMUX_RGCFR_COF1_Msk                   /*!< Request generator channel 1 Clear trigger overrun event flag */
+#define DMAMUX_RGCFR_COF2_Pos          (2U)
+#define DMAMUX_RGCFR_COF2_Msk          (0x1UL << DMAMUX_RGCFR_COF2_Pos)        /*!< 0x00000004 */
+#define DMAMUX_RGCFR_COF2              DMAMUX_RGCFR_COF2_Msk                   /*!< Request generator channel 2 Clear trigger overrun event flag */
+#define DMAMUX_RGCFR_COF3_Pos          (3U)
+#define DMAMUX_RGCFR_COF3_Msk          (0x1UL << DMAMUX_RGCFR_COF3_Pos)        /*!< 0x00000008 */
+#define DMAMUX_RGCFR_COF3              DMAMUX_RGCFR_COF3_Msk                   /*!< Request generator channel 3 Clear trigger overrun event flag */
+#define DMAMUX_RGCFR_COF4_Pos          (4U)
+#define DMAMUX_RGCFR_COF4_Msk          (0x1UL << DMAMUX_RGCFR_COF4_Pos)        /*!< 0x00000010 */
+#define DMAMUX_RGCFR_COF4              DMAMUX_RGCFR_COF4_Msk                   /*!< Request generator channel 4 Clear trigger overrun event flag */
+#define DMAMUX_RGCFR_COF5_Pos          (5U)
+#define DMAMUX_RGCFR_COF5_Msk          (0x1UL << DMAMUX_RGCFR_COF5_Pos)        /*!< 0x00000020 */
+#define DMAMUX_RGCFR_COF5              DMAMUX_RGCFR_COF5_Msk                   /*!< Request generator channel 5 Clear trigger overrun event flag */
+#define DMAMUX_RGCFR_COF6_Pos          (6U)
+#define DMAMUX_RGCFR_COF6_Msk          (0x1UL << DMAMUX_RGCFR_COF6_Pos)        /*!< 0x00000040 */
+#define DMAMUX_RGCFR_COF6              DMAMUX_RGCFR_COF6_Msk                   /*!< Request generator channel 6 Clear trigger overrun event flag */
+#define DMAMUX_RGCFR_COF7_Pos          (7U)
+#define DMAMUX_RGCFR_COF7_Msk          (0x1UL << DMAMUX_RGCFR_COF7_Pos)        /*!< 0x00000080 */
+#define DMAMUX_RGCFR_COF7              DMAMUX_RGCFR_COF7_Msk                   /*!< Request generator channel 7 Clear trigger overrun event flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         AHB Master DMA2D Controller (DMA2D)                */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for DMA2D_CR register  ******************/
+
+#define DMA2D_CR_START_Pos         (0U)
+#define DMA2D_CR_START_Msk         (0x1UL << DMA2D_CR_START_Pos)               /*!< 0x00000001 */
+#define DMA2D_CR_START             DMA2D_CR_START_Msk                          /*!< Start transfer                          */
+#define DMA2D_CR_SUSP_Pos          (1U)
+#define DMA2D_CR_SUSP_Msk          (0x1UL << DMA2D_CR_SUSP_Pos)                /*!< 0x00000002 */
+#define DMA2D_CR_SUSP              DMA2D_CR_SUSP_Msk                           /*!< Suspend transfer                        */
+#define DMA2D_CR_ABORT_Pos         (2U)
+#define DMA2D_CR_ABORT_Msk         (0x1UL << DMA2D_CR_ABORT_Pos)               /*!< 0x00000004 */
+#define DMA2D_CR_ABORT             DMA2D_CR_ABORT_Msk                          /*!< Abort transfer                          */
+#define DMA2D_CR_LOM_Pos           (6U)
+#define DMA2D_CR_LOM_Msk           (0x1UL << DMA2D_CR_LOM_Pos)                 /*!< 0x00000040 */
+#define DMA2D_CR_LOM               DMA2D_CR_LOM_Msk                            /*!< Line Offset Mode                         */
+#define DMA2D_CR_TEIE_Pos          (8U)
+#define DMA2D_CR_TEIE_Msk          (0x1UL << DMA2D_CR_TEIE_Pos)                /*!< 0x00000100 */
+#define DMA2D_CR_TEIE              DMA2D_CR_TEIE_Msk                           /*!< Transfer Error Interrupt Enable         */
+#define DMA2D_CR_TCIE_Pos          (9U)
+#define DMA2D_CR_TCIE_Msk          (0x1UL << DMA2D_CR_TCIE_Pos)                /*!< 0x00000200 */
+#define DMA2D_CR_TCIE              DMA2D_CR_TCIE_Msk                           /*!< Transfer Complete Interrupt Enable      */
+#define DMA2D_CR_TWIE_Pos          (10U)
+#define DMA2D_CR_TWIE_Msk          (0x1UL << DMA2D_CR_TWIE_Pos)                /*!< 0x00000400 */
+#define DMA2D_CR_TWIE              DMA2D_CR_TWIE_Msk                           /*!< Transfer Watermark Interrupt Enable     */
+#define DMA2D_CR_CAEIE_Pos         (11U)
+#define DMA2D_CR_CAEIE_Msk         (0x1UL << DMA2D_CR_CAEIE_Pos)               /*!< 0x00000800 */
+#define DMA2D_CR_CAEIE             DMA2D_CR_CAEIE_Msk                          /*!< CLUT Access Error Interrupt Enable      */
+#define DMA2D_CR_CTCIE_Pos         (12U)
+#define DMA2D_CR_CTCIE_Msk         (0x1UL << DMA2D_CR_CTCIE_Pos)               /*!< 0x00001000 */
+#define DMA2D_CR_CTCIE             DMA2D_CR_CTCIE_Msk                          /*!< CLUT Transfer Complete Interrupt Enable */
+#define DMA2D_CR_CEIE_Pos          (13U)
+#define DMA2D_CR_CEIE_Msk          (0x1UL << DMA2D_CR_CEIE_Pos)                /*!< 0x00002000 */
+#define DMA2D_CR_CEIE              DMA2D_CR_CEIE_Msk                           /*!< Configuration Error Interrupt Enable    */
+#define DMA2D_CR_MODE_Pos          (16U)
+#define DMA2D_CR_MODE_Msk          (0x7UL << DMA2D_CR_MODE_Pos)                /*!< 0x00070000 */
+#define DMA2D_CR_MODE              DMA2D_CR_MODE_Msk                           /*!< DMA2D Mode[2:0]                         */
+#define DMA2D_CR_MODE_0            (0x1UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00010000 */
+#define DMA2D_CR_MODE_1            (0x2UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00020000 */
+#define DMA2D_CR_MODE_2            (0x4UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00040000 */
+
+/********************  Bit definition for DMA2D_ISR register  *****************/
+
+#define DMA2D_ISR_TEIF_Pos         (0U)
+#define DMA2D_ISR_TEIF_Msk         (0x1UL << DMA2D_ISR_TEIF_Pos)               /*!< 0x00000001 */
+#define DMA2D_ISR_TEIF             DMA2D_ISR_TEIF_Msk                          /*!< Transfer Error Interrupt Flag         */
+#define DMA2D_ISR_TCIF_Pos         (1U)
+#define DMA2D_ISR_TCIF_Msk         (0x1UL << DMA2D_ISR_TCIF_Pos)               /*!< 0x00000002 */
+#define DMA2D_ISR_TCIF             DMA2D_ISR_TCIF_Msk                          /*!< Transfer Complete Interrupt Flag      */
+#define DMA2D_ISR_TWIF_Pos         (2U)
+#define DMA2D_ISR_TWIF_Msk         (0x1UL << DMA2D_ISR_TWIF_Pos)               /*!< 0x00000004 */
+#define DMA2D_ISR_TWIF             DMA2D_ISR_TWIF_Msk                          /*!< Transfer Watermark Interrupt Flag     */
+#define DMA2D_ISR_CAEIF_Pos        (3U)
+#define DMA2D_ISR_CAEIF_Msk        (0x1UL << DMA2D_ISR_CAEIF_Pos)              /*!< 0x00000008 */
+#define DMA2D_ISR_CAEIF            DMA2D_ISR_CAEIF_Msk                         /*!< CLUT Access Error Interrupt Flag      */
+#define DMA2D_ISR_CTCIF_Pos        (4U)
+#define DMA2D_ISR_CTCIF_Msk        (0x1UL << DMA2D_ISR_CTCIF_Pos)              /*!< 0x00000010 */
+#define DMA2D_ISR_CTCIF            DMA2D_ISR_CTCIF_Msk                         /*!< CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_CEIF_Pos         (5U)
+#define DMA2D_ISR_CEIF_Msk         (0x1UL << DMA2D_ISR_CEIF_Pos)               /*!< 0x00000020 */
+#define DMA2D_ISR_CEIF             DMA2D_ISR_CEIF_Msk                          /*!< Configuration Error Interrupt Flag    */
+
+/********************  Bit definition for DMA2D_IFCR register  ****************/
+
+#define DMA2D_IFCR_CTEIF_Pos       (0U)
+#define DMA2D_IFCR_CTEIF_Msk       (0x1UL << DMA2D_IFCR_CTEIF_Pos)             /*!< 0x00000001 */
+#define DMA2D_IFCR_CTEIF           DMA2D_IFCR_CTEIF_Msk                        /*!< Clears Transfer Error Interrupt Flag         */
+#define DMA2D_IFCR_CTCIF_Pos       (1U)
+#define DMA2D_IFCR_CTCIF_Msk       (0x1UL << DMA2D_IFCR_CTCIF_Pos)             /*!< 0x00000002 */
+#define DMA2D_IFCR_CTCIF           DMA2D_IFCR_CTCIF_Msk                        /*!< Clears Transfer Complete Interrupt Flag      */
+#define DMA2D_IFCR_CTWIF_Pos       (2U)
+#define DMA2D_IFCR_CTWIF_Msk       (0x1UL << DMA2D_IFCR_CTWIF_Pos)             /*!< 0x00000004 */
+#define DMA2D_IFCR_CTWIF           DMA2D_IFCR_CTWIF_Msk                        /*!< Clears Transfer Watermark Interrupt Flag     */
+#define DMA2D_IFCR_CAECIF_Pos      (3U)
+#define DMA2D_IFCR_CAECIF_Msk      (0x1UL << DMA2D_IFCR_CAECIF_Pos)            /*!< 0x00000008 */
+#define DMA2D_IFCR_CAECIF          DMA2D_IFCR_CAECIF_Msk                       /*!< Clears CLUT Access Error Interrupt Flag      */
+#define DMA2D_IFCR_CCTCIF_Pos      (4U)
+#define DMA2D_IFCR_CCTCIF_Msk      (0x1UL << DMA2D_IFCR_CCTCIF_Pos)            /*!< 0x00000010 */
+#define DMA2D_IFCR_CCTCIF          DMA2D_IFCR_CCTCIF_Msk                       /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CCEIF_Pos       (5U)
+#define DMA2D_IFCR_CCEIF_Msk       (0x1UL << DMA2D_IFCR_CCEIF_Pos)             /*!< 0x00000020 */
+#define DMA2D_IFCR_CCEIF           DMA2D_IFCR_CCEIF_Msk                        /*!< Clears Configuration Error Interrupt Flag    */
+
+/********************  Bit definition for DMA2D_FGMAR register  ***************/
+
+#define DMA2D_FGMAR_MA_Pos         (0U)
+#define DMA2D_FGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)        /*!< 0xFFFFFFFF */
+#define DMA2D_FGMAR_MA             DMA2D_FGMAR_MA_Msk                          /*!< Foreground Memory Address */
+
+/********************  Bit definition for DMA2D_FGOR register  ****************/
+
+#define DMA2D_FGOR_LO_Pos          (0U)
+#define DMA2D_FGOR_LO_Msk          (0xFFFFUL << DMA2D_FGOR_LO_Pos)             /*!< 0x0000FFFF */
+#define DMA2D_FGOR_LO              DMA2D_FGOR_LO_Msk                           /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_BGMAR register  ***************/
+
+#define DMA2D_BGMAR_MA_Pos         (0U)
+#define DMA2D_BGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)        /*!< 0xFFFFFFFF */
+#define DMA2D_BGMAR_MA             DMA2D_BGMAR_MA_Msk                          /*!< Background Memory Address */
+
+/********************  Bit definition for DMA2D_BGOR register  ****************/
+
+#define DMA2D_BGOR_LO_Pos          (0U)
+#define DMA2D_BGOR_LO_Msk          (0xFFFFUL << DMA2D_BGOR_LO_Pos)             /*!< 0x0000FFFF */
+#define DMA2D_BGOR_LO              DMA2D_BGOR_LO_Msk                           /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_FGPFCCR register  *************/
+
+#define DMA2D_FGPFCCR_CM_Pos       (0U)
+#define DMA2D_FGPFCCR_CM_Msk       (0xFUL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x0000000F */
+#define DMA2D_FGPFCCR_CM           DMA2D_FGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */
+#define DMA2D_FGPFCCR_CM_0         (0x1UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000001 */
+#define DMA2D_FGPFCCR_CM_1         (0x2UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000002 */
+#define DMA2D_FGPFCCR_CM_2         (0x4UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000004 */
+#define DMA2D_FGPFCCR_CM_3         (0x8UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000008 */
+#define DMA2D_FGPFCCR_CCM_Pos      (4U)
+#define DMA2D_FGPFCCR_CCM_Msk      (0x1UL << DMA2D_FGPFCCR_CCM_Pos)            /*!< 0x00000010 */
+#define DMA2D_FGPFCCR_CCM          DMA2D_FGPFCCR_CCM_Msk                       /*!< CLUT Color mode */
+#define DMA2D_FGPFCCR_START_Pos    (5U)
+#define DMA2D_FGPFCCR_START_Msk    (0x1UL << DMA2D_FGPFCCR_START_Pos)          /*!< 0x00000020 */
+#define DMA2D_FGPFCCR_START        DMA2D_FGPFCCR_START_Msk                     /*!< Start */
+#define DMA2D_FGPFCCR_CS_Pos       (8U)
+#define DMA2D_FGPFCCR_CS_Msk       (0xFFUL << DMA2D_FGPFCCR_CS_Pos)            /*!< 0x0000FF00 */
+#define DMA2D_FGPFCCR_CS           DMA2D_FGPFCCR_CS_Msk                        /*!< CLUT size */
+#define DMA2D_FGPFCCR_AM_Pos       (16U)
+#define DMA2D_FGPFCCR_AM_Msk       (0x3UL << DMA2D_FGPFCCR_AM_Pos)             /*!< 0x00030000 */
+#define DMA2D_FGPFCCR_AM           DMA2D_FGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */
+#define DMA2D_FGPFCCR_AM_0         (0x1UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00010000 */
+#define DMA2D_FGPFCCR_AM_1         (0x2UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00020000 */
+#define DMA2D_FGPFCCR_CSS_Pos      (18U)
+#define DMA2D_FGPFCCR_CSS_Msk      (0x3UL << DMA2D_FGPFCCR_CSS_Pos)            /*!< 0x000C0000 */
+#define DMA2D_FGPFCCR_CSS          DMA2D_FGPFCCR_CSS_Msk                       /* !< Chroma Sub-Sampling */
+#define DMA2D_FGPFCCR_CSS_0        (0x1UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00040000 */
+#define DMA2D_FGPFCCR_CSS_1        (0x2UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00080000 */
+#define DMA2D_FGPFCCR_AI_Pos       (20U)
+#define DMA2D_FGPFCCR_AI_Msk       (0x1UL << DMA2D_FGPFCCR_AI_Pos)             /*!< 0x00100000 */
+#define DMA2D_FGPFCCR_AI           DMA2D_FGPFCCR_AI_Msk                        /*!< Foreground Input Alpha Inverted */
+#define DMA2D_FGPFCCR_RBS_Pos      (21U)
+#define DMA2D_FGPFCCR_RBS_Msk      (0x1UL << DMA2D_FGPFCCR_RBS_Pos)            /*!< 0x00200000 */
+#define DMA2D_FGPFCCR_RBS          DMA2D_FGPFCCR_RBS_Msk                       /*!< Foreground Input Red Blue Swap */
+#define DMA2D_FGPFCCR_ALPHA_Pos    (24U)
+#define DMA2D_FGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */
+#define DMA2D_FGPFCCR_ALPHA        DMA2D_FGPFCCR_ALPHA_Msk                     /*!< Alpha value */
+
+/********************  Bit definition for DMA2D_FGCOLR register  **************/
+
+#define DMA2D_FGCOLR_BLUE_Pos      (0U)
+#define DMA2D_FGCOLR_BLUE_Msk      (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)           /*!< 0x000000FF */
+#define DMA2D_FGCOLR_BLUE          DMA2D_FGCOLR_BLUE_Msk                       /*!< Foreground Blue Value */
+#define DMA2D_FGCOLR_GREEN_Pos     (8U)
+#define DMA2D_FGCOLR_GREEN_Msk     (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */
+#define DMA2D_FGCOLR_GREEN         DMA2D_FGCOLR_GREEN_Msk                      /*!< Foreground Green Value */
+#define DMA2D_FGCOLR_RED_Pos       (16U)
+#define DMA2D_FGCOLR_RED_Msk       (0xFFUL << DMA2D_FGCOLR_RED_Pos)            /*!< 0x00FF0000 */
+#define DMA2D_FGCOLR_RED           DMA2D_FGCOLR_RED_Msk                        /*!< Foreground Red Value */
+
+/********************  Bit definition for DMA2D_BGPFCCR register  *************/
+
+#define DMA2D_BGPFCCR_CM_Pos       (0U)
+#define DMA2D_BGPFCCR_CM_Msk       (0xFUL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x0000000F */
+#define DMA2D_BGPFCCR_CM           DMA2D_BGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */
+#define DMA2D_BGPFCCR_CM_0         (0x1UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000001 */
+#define DMA2D_BGPFCCR_CM_1         (0x2UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000002 */
+#define DMA2D_BGPFCCR_CM_2         (0x4UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000004 */
+#define DMA2D_BGPFCCR_CM_3         (0x8UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000008 */
+#define DMA2D_BGPFCCR_CCM_Pos      (4U)
+#define DMA2D_BGPFCCR_CCM_Msk      (0x1UL << DMA2D_BGPFCCR_CCM_Pos)            /*!< 0x00000010 */
+#define DMA2D_BGPFCCR_CCM          DMA2D_BGPFCCR_CCM_Msk                       /*!< CLUT Color mode */
+#define DMA2D_BGPFCCR_START_Pos    (5U)
+#define DMA2D_BGPFCCR_START_Msk    (0x1UL << DMA2D_BGPFCCR_START_Pos)          /*!< 0x00000020 */
+#define DMA2D_BGPFCCR_START        DMA2D_BGPFCCR_START_Msk                     /*!< Start */
+#define DMA2D_BGPFCCR_CS_Pos       (8U)
+#define DMA2D_BGPFCCR_CS_Msk       (0xFFUL << DMA2D_BGPFCCR_CS_Pos)            /*!< 0x0000FF00 */
+#define DMA2D_BGPFCCR_CS           DMA2D_BGPFCCR_CS_Msk                        /*!< CLUT size */
+#define DMA2D_BGPFCCR_AM_Pos       (16U)
+#define DMA2D_BGPFCCR_AM_Msk       (0x3UL << DMA2D_BGPFCCR_AM_Pos)             /*!< 0x00030000 */
+#define DMA2D_BGPFCCR_AM           DMA2D_BGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */
+#define DMA2D_BGPFCCR_AM_0         (0x1UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00010000 */
+#define DMA2D_BGPFCCR_AM_1         (0x2UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00020000 */
+#define DMA2D_BGPFCCR_AI_Pos       (20U)
+#define DMA2D_BGPFCCR_AI_Msk       (0x1UL << DMA2D_BGPFCCR_AI_Pos)             /*!< 0x00100000 */
+#define DMA2D_BGPFCCR_AI           DMA2D_BGPFCCR_AI_Msk                        /*!< background Input Alpha Inverted */
+#define DMA2D_BGPFCCR_RBS_Pos      (21U)
+#define DMA2D_BGPFCCR_RBS_Msk      (0x1UL << DMA2D_BGPFCCR_RBS_Pos)            /*!< 0x00200000 */
+#define DMA2D_BGPFCCR_RBS          DMA2D_BGPFCCR_RBS_Msk                       /*!< Background Input Red Blue Swap */
+#define DMA2D_BGPFCCR_ALPHA_Pos    (24U)
+#define DMA2D_BGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */
+#define DMA2D_BGPFCCR_ALPHA        DMA2D_BGPFCCR_ALPHA_Msk                     /*!< background Input Alpha value */
+
+/********************  Bit definition for DMA2D_BGCOLR register  **************/
+
+#define DMA2D_BGCOLR_BLUE_Pos      (0U)
+#define DMA2D_BGCOLR_BLUE_Msk      (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)           /*!< 0x000000FF */
+#define DMA2D_BGCOLR_BLUE          DMA2D_BGCOLR_BLUE_Msk                       /*!< Background Blue Value */
+#define DMA2D_BGCOLR_GREEN_Pos     (8U)
+#define DMA2D_BGCOLR_GREEN_Msk     (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */
+#define DMA2D_BGCOLR_GREEN         DMA2D_BGCOLR_GREEN_Msk                      /*!< Background Green Value */
+#define DMA2D_BGCOLR_RED_Pos       (16U)
+#define DMA2D_BGCOLR_RED_Msk       (0xFFUL << DMA2D_BGCOLR_RED_Pos)            /*!< 0x00FF0000 */
+#define DMA2D_BGCOLR_RED           DMA2D_BGCOLR_RED_Msk                        /*!< Background Red Value */
+
+/********************  Bit definition for DMA2D_FGCMAR register  **************/
+
+#define DMA2D_FGCMAR_MA_Pos        (0U)
+#define DMA2D_FGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */
+#define DMA2D_FGCMAR_MA            DMA2D_FGCMAR_MA_Msk                         /*!< Foreground CLUT Memory Address */
+
+/********************  Bit definition for DMA2D_BGCMAR register  **************/
+
+#define DMA2D_BGCMAR_MA_Pos        (0U)
+#define DMA2D_BGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */
+#define DMA2D_BGCMAR_MA            DMA2D_BGCMAR_MA_Msk                         /*!< Background CLUT Memory Address */
+
+/********************  Bit definition for DMA2D_OPFCCR register  **************/
+
+#define DMA2D_OPFCCR_CM_Pos        (0U)
+#define DMA2D_OPFCCR_CM_Msk        (0x7UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000007 */
+#define DMA2D_OPFCCR_CM            DMA2D_OPFCCR_CM_Msk                         /*!< Output Color mode CM[2:0] */
+#define DMA2D_OPFCCR_CM_0          (0x1UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000001 */
+#define DMA2D_OPFCCR_CM_1          (0x2UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000002 */
+#define DMA2D_OPFCCR_CM_2          (0x4UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000004 */
+#define DMA2D_OPFCCR_SB_Pos        (8U)
+#define DMA2D_OPFCCR_SB_Msk        (0x1UL << DMA2D_OPFCCR_SB_Pos)              /*!< 0x00000100 */
+#define DMA2D_OPFCCR_SB            DMA2D_OPFCCR_SB_Msk                         /*!< Swap Bytes */
+#define DMA2D_OPFCCR_AI_Pos        (20U)
+#define DMA2D_OPFCCR_AI_Msk        (0x1UL << DMA2D_OPFCCR_AI_Pos)              /*!< 0x00100000 */
+#define DMA2D_OPFCCR_AI            DMA2D_OPFCCR_AI_Msk                         /*!< Output Alpha Inverted */
+#define DMA2D_OPFCCR_RBS_Pos       (21U)
+#define DMA2D_OPFCCR_RBS_Msk       (0x1UL << DMA2D_OPFCCR_RBS_Pos)             /*!< 0x00200000 */
+#define DMA2D_OPFCCR_RBS           DMA2D_OPFCCR_RBS_Msk                        /*!< Output Red Blue Swap */
+
+/********************  Bit definition for DMA2D_OCOLR register  ***************/
+
+/*!<Mode_ARGB8888/RGB888 */
+
+#define DMA2D_OCOLR_BLUE_1_Pos     (0U)
+#define DMA2D_OCOLR_BLUE_1_Msk     (0xFFUL <<DMA2D_OCOLR_BLUE_1_Pos)            /*0x000000FFU*/
+#define DMA2D_OCOLR_BLUE_1         DMA2D_OCOLR_BLUE_1_Msk                      /*!< Output BLUE Value */
+#define DMA2D_OCOLR_GREEN_1_Pos    (8U)
+#define DMA2D_OCOLR_GREEN_1_Msk    (0xFFUL<<DMA2D_OCOLR_GREEN_1_Pos)            /*0x0000FF00U)*/
+#define DMA2D_OCOLR_GREEN_1        DMA2D_OCOLR_GREEN_1_Msk                     /*!< Output GREEN Value  */
+#define DMA2D_OCOLR_RED_1_Pos      (16U)
+#define DMA2D_OCOLR_RED_1_Msk      (0xFFUL << DMA2D_OCOLR_RED_1_Pos)            /*0x00FF0000U */
+#define DMA2D_OCOLR_RED_1          DMA2D_OCOLR_RED_1_Msk                       /*!< Output Red Value */
+#define DMA2D_OCOLR_ALPHA_1_Pos    (24U)
+#define DMA2D_OCOLR_ALPHA_1_Msk    (0xFFUL << DMA2D_OCOLR_ALPHA_1_Pos)          /*0xFF000000U*/
+#define DMA2D_OCOLR_ALPHA_1        DMA2D_OCOLR_ALPHA_1_Msk                     /*!< Output Alpha Channel Value */
+
+/*!<Mode_RGB565 */
+#define DMA2D_OCOLR_BLUE_2_Pos     (0U)
+#define DMA2D_OCOLR_BLUE_2_Msk     (0x1FUL <<DMA2D_OCOLR_BLUE_2_Pos)            /*0x0000001FU*/
+#define DMA2D_OCOLR_BLUE_2         DMA2D_OCOLR_BLUE_2_Msk                      /*!< Output BLUE Value */
+#define DMA2D_OCOLR_GREEN_2_Pos    (5U)
+#define DMA2D_OCOLR_GREEN_2_Msk    (0x7EUL << DMA2D_OCOLR_GREEN_2_Pos)          /* 0x000007E0U */
+#define DMA2D_OCOLR_GREEN_2        DMA2D_OCOLR_GREEN_2_Msk                     /*!< Output GREEN Value  */
+#define DMA2D_OCOLR_RED_2_Pos      (11U)
+#define DMA2D_OCOLR_RED_2_Msk      (0xF8UL<<DMA2D_OCOLR_RED_2_Pos)              /*0x0000F800U*/
+#define DMA2D_OCOLR_RED_2          DMA2D_OCOLR_RED_2_Msk                       /*!< Output Red Value */
+
+/*!<Mode_ARGB1555 */
+#define DMA2D_OCOLR_BLUE_3_Pos     (0U)
+#define DMA2D_OCOLR_BLUE_3_Msk     (0x1FUL << DMA2D_OCOLR_BLUE_3_Pos)           /*0x0000001FU*/
+#define DMA2D_OCOLR_BLUE_3         DMA2D_OCOLR_BLUE_3_Msk                      /*!< Output BLUE Value */
+#define DMA2D_OCOLR_GREEN_3_Pos    (5U)
+#define DMA2D_OCOLR_GREEN_3_Msk    (0x3EUL << DMA2D_OCOLR_GREEN_3_Pos)          /*0x000003E0U*/
+#define DMA2D_OCOLR_GREEN_3        DMA2D_OCOLR_GREEN_3_Msk                     /*!< Output GREEN Value  */
+#define DMA2D_OCOLR_RED_3_Pos      (10U)
+#define DMA2D_OCOLR_RED_3_Msk      (0x7CUL << DMA2D_OCOLR_RED_3_Pos)            /* 0x00007C00U*/
+#define DMA2D_OCOLR_RED_3          DMA2D_OCOLR_RED_3_Msk                       /*!< Output Red Value */
+#define DMA2D_OCOLR_ALPHA_3_Pos    (15U)
+#define DMA2D_OCOLR_ALPHA_3_Msk    (0x1UL << DMA2D_OCOLR_ALPHA_3_Pos)           /*0x00008000U*/
+#define DMA2D_OCOLR_ALPHA_3        DMA2D_OCOLR_ALPHA_3_Msk                     /*!< Output Alpha Channel Value */
+
+/*!<Mode_ARGB4444 */
+#define DMA2D_OCOLR_BLUE_4_Pos     (0U)
+#define DMA2D_OCOLR_BLUE_4_Msk     (0xFUL << DMA2D_OCOLR_BLUE_4_Pos)            /*0x0000000FU*/
+#define DMA2D_OCOLR_BLUE_4         DMA2D_OCOLR_BLUE_4_Msk                      /*!< Output BLUE Value */
+#define DMA2D_OCOLR_GREEN_4_Pos    (4U)
+#define DMA2D_OCOLR_GREEN_4_Msk    (0xFUL << DMA2D_OCOLR_GREEN_4_Pos)           /*0x000000F0U*/
+#define DMA2D_OCOLR_GREEN_4        DMA2D_OCOLR_GREEN_4_Msk                     /*!< Output GREEN Value  */
+#define DMA2D_OCOLR_RED_4_Pos      (8U)
+#define DMA2D_OCOLR_RED_4_Msk      (0xFUL << DMA2D_OCOLR_RED_4_Pos)             /*0x00000F00U*/
+#define DMA2D_OCOLR_RED_4          DMA2D_OCOLR_RED_4_Msk                       /*!< Output Red Value */
+#define DMA2D_OCOLR_ALPHA_4_Pos    (12U)
+#define DMA2D_OCOLR_ALPHA_4_Msk    (0xFUL << DMA2D_OCOLR_ALPHA_4_Pos)            /*0x0000F000U*/
+#define DMA2D_OCOLR_ALPHA_4        DMA2D_OCOLR_ALPHA_4_Msk                     /*!< Output Alpha Channel Value */
+
+/********************  Bit definition for DMA2D_OMAR register  ****************/
+
+#define DMA2D_OMAR_MA_Pos          (0U)
+#define DMA2D_OMAR_MA_Msk          (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)         /*!< 0xFFFFFFFF */
+#define DMA2D_OMAR_MA              DMA2D_OMAR_MA_Msk                           /*!< Output Memory Address */
+
+/********************  Bit definition for DMA2D_OOR register  *****************/
+
+#define DMA2D_OOR_LO_Pos           (0U)
+#define DMA2D_OOR_LO_Msk           (0xFFFFUL << DMA2D_OOR_LO_Pos)              /*!< 0x0000FFFF */
+#define DMA2D_OOR_LO               DMA2D_OOR_LO_Msk                            /*!< Output Line Offset */
+
+/********************  Bit definition for DMA2D_NLR register  *****************/
+
+#define DMA2D_NLR_NL_Pos           (0U)
+#define DMA2D_NLR_NL_Msk           (0xFFFFUL << DMA2D_NLR_NL_Pos)              /*!< 0x0000FFFF */
+#define DMA2D_NLR_NL               DMA2D_NLR_NL_Msk                            /*!< Number of Lines */
+#define DMA2D_NLR_PL_Pos           (16U)
+#define DMA2D_NLR_PL_Msk           (0x3FFFUL << DMA2D_NLR_PL_Pos)              /*!< 0x3FFF0000 */
+#define DMA2D_NLR_PL               DMA2D_NLR_PL_Msk                            /*!< Pixel per Lines */
+
+/********************  Bit definition for DMA2D_LWR register  *****************/
+
+#define DMA2D_LWR_LW_Pos           (0U)
+#define DMA2D_LWR_LW_Msk           (0xFFFFUL << DMA2D_LWR_LW_Pos)              /*!< 0x0000FFFF */
+#define DMA2D_LWR_LW               DMA2D_LWR_LW_Msk                            /*!< Line Watermark */
+
+/********************  Bit definition for DMA2D_AMTCR register  ***************/
+
+#define DMA2D_AMTCR_EN_Pos         (0U)
+#define DMA2D_AMTCR_EN_Msk         (0x1UL << DMA2D_AMTCR_EN_Pos)               /*!< 0x00000001 */
+#define DMA2D_AMTCR_EN             DMA2D_AMTCR_EN_Msk                          /*!< Enable */
+#define DMA2D_AMTCR_DT_Pos         (8U)
+#define DMA2D_AMTCR_DT_Msk         (0xFFUL << DMA2D_AMTCR_DT_Pos)              /*!< 0x0000FF00 */
+#define DMA2D_AMTCR_DT             DMA2D_AMTCR_DT_Msk                          /*!< Dead Time */
+
+
+/********************  Bit definition for DMA2D_FGCLUT register  **************/
+
+/********************  Bit definition for DMA2D_BGCLUT register  **************/
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                    External Interrupt/Event Controller                     */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for EXTI_RTSR1 register  *******************/
+#define EXTI_RTSR1_TR_Pos          (0U)
+#define EXTI_RTSR1_TR_Msk          (0x3FFFFFUL << EXTI_RTSR1_TR_Pos)           /*!< 0x003FFFFF */
+#define EXTI_RTSR1_TR              EXTI_RTSR1_TR_Msk                           /*!< Rising trigger event configuration bit */
+#define EXTI_RTSR1_TR0_Pos         (0U)
+#define EXTI_RTSR1_TR0_Msk         (0x1UL << EXTI_RTSR1_TR0_Pos)               /*!< 0x00000001 */
+#define EXTI_RTSR1_TR0             EXTI_RTSR1_TR0_Msk                          /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR1_TR1_Pos         (1U)
+#define EXTI_RTSR1_TR1_Msk         (0x1UL << EXTI_RTSR1_TR1_Pos)               /*!< 0x00000002 */
+#define EXTI_RTSR1_TR1             EXTI_RTSR1_TR1_Msk                          /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR1_TR2_Pos         (2U)
+#define EXTI_RTSR1_TR2_Msk         (0x1UL << EXTI_RTSR1_TR2_Pos)               /*!< 0x00000004 */
+#define EXTI_RTSR1_TR2             EXTI_RTSR1_TR2_Msk                          /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR1_TR3_Pos         (3U)
+#define EXTI_RTSR1_TR3_Msk         (0x1UL << EXTI_RTSR1_TR3_Pos)               /*!< 0x00000008 */
+#define EXTI_RTSR1_TR3             EXTI_RTSR1_TR3_Msk                          /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR1_TR4_Pos         (4U)
+#define EXTI_RTSR1_TR4_Msk         (0x1UL << EXTI_RTSR1_TR4_Pos)               /*!< 0x00000010 */
+#define EXTI_RTSR1_TR4             EXTI_RTSR1_TR4_Msk                          /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR1_TR5_Pos         (5U)
+#define EXTI_RTSR1_TR5_Msk         (0x1UL << EXTI_RTSR1_TR5_Pos)               /*!< 0x00000020 */
+#define EXTI_RTSR1_TR5             EXTI_RTSR1_TR5_Msk                          /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR1_TR6_Pos         (6U)
+#define EXTI_RTSR1_TR6_Msk         (0x1UL << EXTI_RTSR1_TR6_Pos)               /*!< 0x00000040 */
+#define EXTI_RTSR1_TR6             EXTI_RTSR1_TR6_Msk                          /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR1_TR7_Pos         (7U)
+#define EXTI_RTSR1_TR7_Msk         (0x1UL << EXTI_RTSR1_TR7_Pos)               /*!< 0x00000080 */
+#define EXTI_RTSR1_TR7             EXTI_RTSR1_TR7_Msk                          /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR1_TR8_Pos         (8U)
+#define EXTI_RTSR1_TR8_Msk         (0x1UL << EXTI_RTSR1_TR8_Pos)               /*!< 0x00000100 */
+#define EXTI_RTSR1_TR8             EXTI_RTSR1_TR8_Msk                          /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR1_TR9_Pos         (9U)
+#define EXTI_RTSR1_TR9_Msk         (0x1UL << EXTI_RTSR1_TR9_Pos)               /*!< 0x00000200 */
+#define EXTI_RTSR1_TR9             EXTI_RTSR1_TR9_Msk                          /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR1_TR10_Pos        (10U)
+#define EXTI_RTSR1_TR10_Msk        (0x1UL << EXTI_RTSR1_TR10_Pos)              /*!< 0x00000400 */
+#define EXTI_RTSR1_TR10            EXTI_RTSR1_TR10_Msk                         /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR1_TR11_Pos        (11U)
+#define EXTI_RTSR1_TR11_Msk        (0x1UL << EXTI_RTSR1_TR11_Pos)              /*!< 0x00000800 */
+#define EXTI_RTSR1_TR11            EXTI_RTSR1_TR11_Msk                         /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR1_TR12_Pos        (12U)
+#define EXTI_RTSR1_TR12_Msk        (0x1UL << EXTI_RTSR1_TR12_Pos)              /*!< 0x00001000 */
+#define EXTI_RTSR1_TR12            EXTI_RTSR1_TR12_Msk                         /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR1_TR13_Pos        (13U)
+#define EXTI_RTSR1_TR13_Msk        (0x1UL << EXTI_RTSR1_TR13_Pos)              /*!< 0x00002000 */
+#define EXTI_RTSR1_TR13            EXTI_RTSR1_TR13_Msk                         /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR1_TR14_Pos        (14U)
+#define EXTI_RTSR1_TR14_Msk        (0x1UL << EXTI_RTSR1_TR14_Pos)              /*!< 0x00004000 */
+#define EXTI_RTSR1_TR14            EXTI_RTSR1_TR14_Msk                         /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR1_TR15_Pos        (15U)
+#define EXTI_RTSR1_TR15_Msk        (0x1UL << EXTI_RTSR1_TR15_Pos)              /*!< 0x00008000 */
+#define EXTI_RTSR1_TR15            EXTI_RTSR1_TR15_Msk                         /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR1_TR16_Pos        (16U)
+#define EXTI_RTSR1_TR16_Msk        (0x1UL << EXTI_RTSR1_TR16_Pos)              /*!< 0x00010000 */
+#define EXTI_RTSR1_TR16            EXTI_RTSR1_TR16_Msk                         /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR1_TR17_Pos        (17U)
+#define EXTI_RTSR1_TR17_Msk        (0x1UL << EXTI_RTSR1_TR17_Pos)              /*!< 0x00020000 */
+#define EXTI_RTSR1_TR17            EXTI_RTSR1_TR17_Msk                         /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR1_TR18_Pos        (18U)
+#define EXTI_RTSR1_TR18_Msk        (0x1UL << EXTI_RTSR1_TR18_Pos)              /*!< 0x00040000 */
+#define EXTI_RTSR1_TR18            EXTI_RTSR1_TR18_Msk                         /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR1_TR19_Pos        (19U)
+#define EXTI_RTSR1_TR19_Msk        (0x1UL << EXTI_RTSR1_TR19_Pos)              /*!< 0x00080000 */
+#define EXTI_RTSR1_TR19            EXTI_RTSR1_TR19_Msk                         /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR1_TR20_Pos        (20U)
+#define EXTI_RTSR1_TR20_Msk        (0x1UL << EXTI_RTSR1_TR20_Pos)              /*!< 0x00100000 */
+#define EXTI_RTSR1_TR20            EXTI_RTSR1_TR20_Msk                         /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR1_TR21_Pos        (21U)
+#define EXTI_RTSR1_TR21_Msk        (0x1UL << EXTI_RTSR1_TR21_Pos)              /*!< 0x00200000 */
+#define EXTI_RTSR1_TR21            EXTI_RTSR1_TR21_Msk                         /*!< Rising trigger event configuration bit of line 21 */
+
+/******************  Bit definition for EXTI_FTSR1 register  *******************/
+#define EXTI_FTSR1_TR_Pos          (0U)
+#define EXTI_FTSR1_TR_Msk          (0x3FFFFFUL << EXTI_FTSR1_TR_Pos)           /*!< 0x003FFFFF */
+#define EXTI_FTSR1_TR              EXTI_FTSR1_TR_Msk                           /*!< Falling trigger event configuration bit */
+#define EXTI_FTSR1_TR0_Pos         (0U)
+#define EXTI_FTSR1_TR0_Msk         (0x1UL << EXTI_FTSR1_TR0_Pos)               /*!< 0x00000001 */
+#define EXTI_FTSR1_TR0             EXTI_FTSR1_TR0_Msk                          /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR1_TR1_Pos         (1U)
+#define EXTI_FTSR1_TR1_Msk         (0x1UL << EXTI_FTSR1_TR1_Pos)               /*!< 0x00000002 */
+#define EXTI_FTSR1_TR1             EXTI_FTSR1_TR1_Msk                          /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR1_TR2_Pos         (2U)
+#define EXTI_FTSR1_TR2_Msk         (0x1UL << EXTI_FTSR1_TR2_Pos)               /*!< 0x00000004 */
+#define EXTI_FTSR1_TR2             EXTI_FTSR1_TR2_Msk                          /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR1_TR3_Pos         (3U)
+#define EXTI_FTSR1_TR3_Msk         (0x1UL << EXTI_FTSR1_TR3_Pos)               /*!< 0x00000008 */
+#define EXTI_FTSR1_TR3             EXTI_FTSR1_TR3_Msk                          /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR1_TR4_Pos         (4U)
+#define EXTI_FTSR1_TR4_Msk         (0x1UL << EXTI_FTSR1_TR4_Pos)               /*!< 0x00000010 */
+#define EXTI_FTSR1_TR4             EXTI_FTSR1_TR4_Msk                          /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR1_TR5_Pos         (5U)
+#define EXTI_FTSR1_TR5_Msk         (0x1UL << EXTI_FTSR1_TR5_Pos)               /*!< 0x00000020 */
+#define EXTI_FTSR1_TR5             EXTI_FTSR1_TR5_Msk                          /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR1_TR6_Pos         (6U)
+#define EXTI_FTSR1_TR6_Msk         (0x1UL << EXTI_FTSR1_TR6_Pos)               /*!< 0x00000040 */
+#define EXTI_FTSR1_TR6             EXTI_FTSR1_TR6_Msk                          /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR1_TR7_Pos         (7U)
+#define EXTI_FTSR1_TR7_Msk         (0x1UL << EXTI_FTSR1_TR7_Pos)               /*!< 0x00000080 */
+#define EXTI_FTSR1_TR7             EXTI_FTSR1_TR7_Msk                          /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR1_TR8_Pos         (8U)
+#define EXTI_FTSR1_TR8_Msk         (0x1UL << EXTI_FTSR1_TR8_Pos)               /*!< 0x00000100 */
+#define EXTI_FTSR1_TR8             EXTI_FTSR1_TR8_Msk                          /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR1_TR9_Pos         (9U)
+#define EXTI_FTSR1_TR9_Msk         (0x1UL << EXTI_FTSR1_TR9_Pos)               /*!< 0x00000200 */
+#define EXTI_FTSR1_TR9             EXTI_FTSR1_TR9_Msk                          /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR1_TR10_Pos        (10U)
+#define EXTI_FTSR1_TR10_Msk        (0x1UL << EXTI_FTSR1_TR10_Pos)              /*!< 0x00000400 */
+#define EXTI_FTSR1_TR10            EXTI_FTSR1_TR10_Msk                         /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR1_TR11_Pos        (11U)
+#define EXTI_FTSR1_TR11_Msk        (0x1UL << EXTI_FTSR1_TR11_Pos)              /*!< 0x00000800 */
+#define EXTI_FTSR1_TR11            EXTI_FTSR1_TR11_Msk                         /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR1_TR12_Pos        (12U)
+#define EXTI_FTSR1_TR12_Msk        (0x1UL << EXTI_FTSR1_TR12_Pos)              /*!< 0x00001000 */
+#define EXTI_FTSR1_TR12            EXTI_FTSR1_TR12_Msk                         /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR1_TR13_Pos        (13U)
+#define EXTI_FTSR1_TR13_Msk        (0x1UL << EXTI_FTSR1_TR13_Pos)              /*!< 0x00002000 */
+#define EXTI_FTSR1_TR13            EXTI_FTSR1_TR13_Msk                         /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR1_TR14_Pos        (14U)
+#define EXTI_FTSR1_TR14_Msk        (0x1UL << EXTI_FTSR1_TR14_Pos)              /*!< 0x00004000 */
+#define EXTI_FTSR1_TR14            EXTI_FTSR1_TR14_Msk                         /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR1_TR15_Pos        (15U)
+#define EXTI_FTSR1_TR15_Msk        (0x1UL << EXTI_FTSR1_TR15_Pos)              /*!< 0x00008000 */
+#define EXTI_FTSR1_TR15            EXTI_FTSR1_TR15_Msk                         /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR1_TR16_Pos        (16U)
+#define EXTI_FTSR1_TR16_Msk        (0x1UL << EXTI_FTSR1_TR16_Pos)              /*!< 0x00010000 */
+#define EXTI_FTSR1_TR16            EXTI_FTSR1_TR16_Msk                         /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR1_TR17_Pos        (17U)
+#define EXTI_FTSR1_TR17_Msk        (0x1UL << EXTI_FTSR1_TR17_Pos)              /*!< 0x00020000 */
+#define EXTI_FTSR1_TR17            EXTI_FTSR1_TR17_Msk                         /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR1_TR18_Pos        (18U)
+#define EXTI_FTSR1_TR18_Msk        (0x1UL << EXTI_FTSR1_TR18_Pos)              /*!< 0x00040000 */
+#define EXTI_FTSR1_TR18            EXTI_FTSR1_TR18_Msk                         /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR1_TR19_Pos        (19U)
+#define EXTI_FTSR1_TR19_Msk        (0x1UL << EXTI_FTSR1_TR19_Pos)              /*!< 0x00080000 */
+#define EXTI_FTSR1_TR19            EXTI_FTSR1_TR19_Msk                         /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR1_TR20_Pos        (20U)
+#define EXTI_FTSR1_TR20_Msk        (0x1UL << EXTI_FTSR1_TR20_Pos)              /*!< 0x00100000 */
+#define EXTI_FTSR1_TR20            EXTI_FTSR1_TR20_Msk                         /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR1_TR21_Pos        (21U)
+#define EXTI_FTSR1_TR21_Msk        (0x1UL << EXTI_FTSR1_TR21_Pos)              /*!< 0x00200000 */
+#define EXTI_FTSR1_TR21            EXTI_FTSR1_TR21_Msk                         /*!< Falling trigger event configuration bit of line 21 */
+
+/******************  Bit definition for EXTI_SWIER1 register  ******************/
+#define EXTI_SWIER1_SWIER0_Pos     (0U)
+#define EXTI_SWIER1_SWIER0_Msk     (0x1UL << EXTI_SWIER1_SWIER0_Pos)           /*!< 0x00000001 */
+#define EXTI_SWIER1_SWIER0         EXTI_SWIER1_SWIER0_Msk                      /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER1_SWIER1_Pos     (1U)
+#define EXTI_SWIER1_SWIER1_Msk     (0x1UL << EXTI_SWIER1_SWIER1_Pos)           /*!< 0x00000002 */
+#define EXTI_SWIER1_SWIER1         EXTI_SWIER1_SWIER1_Msk                      /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER1_SWIER2_Pos     (2U)
+#define EXTI_SWIER1_SWIER2_Msk     (0x1UL << EXTI_SWIER1_SWIER2_Pos)           /*!< 0x00000004 */
+#define EXTI_SWIER1_SWIER2         EXTI_SWIER1_SWIER2_Msk                      /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER1_SWIER3_Pos     (3U)
+#define EXTI_SWIER1_SWIER3_Msk     (0x1UL << EXTI_SWIER1_SWIER3_Pos)           /*!< 0x00000008 */
+#define EXTI_SWIER1_SWIER3         EXTI_SWIER1_SWIER3_Msk                      /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER1_SWIER4_Pos     (4U)
+#define EXTI_SWIER1_SWIER4_Msk     (0x1UL << EXTI_SWIER1_SWIER4_Pos)           /*!< 0x00000010 */
+#define EXTI_SWIER1_SWIER4         EXTI_SWIER1_SWIER4_Msk                      /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER1_SWIER5_Pos     (5U)
+#define EXTI_SWIER1_SWIER5_Msk     (0x1UL << EXTI_SWIER1_SWIER5_Pos)           /*!< 0x00000020 */
+#define EXTI_SWIER1_SWIER5         EXTI_SWIER1_SWIER5_Msk                      /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER1_SWIER6_Pos     (6U)
+#define EXTI_SWIER1_SWIER6_Msk     (0x1UL << EXTI_SWIER1_SWIER6_Pos)           /*!< 0x00000040 */
+#define EXTI_SWIER1_SWIER6         EXTI_SWIER1_SWIER6_Msk                      /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER1_SWIER7_Pos     (7U)
+#define EXTI_SWIER1_SWIER7_Msk     (0x1UL << EXTI_SWIER1_SWIER7_Pos)           /*!< 0x00000080 */
+#define EXTI_SWIER1_SWIER7         EXTI_SWIER1_SWIER7_Msk                      /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER1_SWIER8_Pos     (8U)
+#define EXTI_SWIER1_SWIER8_Msk     (0x1UL << EXTI_SWIER1_SWIER8_Pos)           /*!< 0x00000100 */
+#define EXTI_SWIER1_SWIER8         EXTI_SWIER1_SWIER8_Msk                      /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER1_SWIER9_Pos     (9U)
+#define EXTI_SWIER1_SWIER9_Msk     (0x1UL << EXTI_SWIER1_SWIER9_Pos)           /*!< 0x00000200 */
+#define EXTI_SWIER1_SWIER9         EXTI_SWIER1_SWIER9_Msk                      /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER1_SWIER10_Pos    (10U)
+#define EXTI_SWIER1_SWIER10_Msk    (0x1UL << EXTI_SWIER1_SWIER10_Pos)          /*!< 0x00000400 */
+#define EXTI_SWIER1_SWIER10        EXTI_SWIER1_SWIER10_Msk                     /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER1_SWIER11_Pos    (11U)
+#define EXTI_SWIER1_SWIER11_Msk    (0x1UL << EXTI_SWIER1_SWIER11_Pos)          /*!< 0x00000800 */
+#define EXTI_SWIER1_SWIER11        EXTI_SWIER1_SWIER11_Msk                     /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER1_SWIER12_Pos    (12U)
+#define EXTI_SWIER1_SWIER12_Msk    (0x1UL << EXTI_SWIER1_SWIER12_Pos)          /*!< 0x00001000 */
+#define EXTI_SWIER1_SWIER12        EXTI_SWIER1_SWIER12_Msk                     /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER1_SWIER13_Pos    (13U)
+#define EXTI_SWIER1_SWIER13_Msk    (0x1UL << EXTI_SWIER1_SWIER13_Pos)          /*!< 0x00002000 */
+#define EXTI_SWIER1_SWIER13        EXTI_SWIER1_SWIER13_Msk                     /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER1_SWIER14_Pos    (14U)
+#define EXTI_SWIER1_SWIER14_Msk    (0x1UL << EXTI_SWIER1_SWIER14_Pos)          /*!< 0x00004000 */
+#define EXTI_SWIER1_SWIER14        EXTI_SWIER1_SWIER14_Msk                     /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER1_SWIER15_Pos    (15U)
+#define EXTI_SWIER1_SWIER15_Msk    (0x1UL << EXTI_SWIER1_SWIER15_Pos)          /*!< 0x00008000 */
+#define EXTI_SWIER1_SWIER15        EXTI_SWIER1_SWIER15_Msk                     /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER1_SWIER16_Pos    (16U)
+#define EXTI_SWIER1_SWIER16_Msk    (0x1UL << EXTI_SWIER1_SWIER16_Pos)          /*!< 0x00010000 */
+#define EXTI_SWIER1_SWIER16        EXTI_SWIER1_SWIER16_Msk                     /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER1_SWIER17_Pos    (17U)
+#define EXTI_SWIER1_SWIER17_Msk    (0x1UL << EXTI_SWIER1_SWIER17_Pos)          /*!< 0x00020000 */
+#define EXTI_SWIER1_SWIER17        EXTI_SWIER1_SWIER17_Msk                     /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER1_SWIER18_Pos    (18U)
+#define EXTI_SWIER1_SWIER18_Msk    (0x1UL << EXTI_SWIER1_SWIER18_Pos)          /*!< 0x00040000 */
+#define EXTI_SWIER1_SWIER18        EXTI_SWIER1_SWIER18_Msk                     /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER1_SWIER19_Pos    (19U)
+#define EXTI_SWIER1_SWIER19_Msk    (0x1UL << EXTI_SWIER1_SWIER19_Pos)          /*!< 0x00080000 */
+#define EXTI_SWIER1_SWIER19        EXTI_SWIER1_SWIER19_Msk                     /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER1_SWIER20_Pos    (20U)
+#define EXTI_SWIER1_SWIER20_Msk    (0x1UL << EXTI_SWIER1_SWIER20_Pos)          /*!< 0x00100000 */
+#define EXTI_SWIER1_SWIER20        EXTI_SWIER1_SWIER20_Msk                     /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER1_SWIER21_Pos    (21U)
+#define EXTI_SWIER1_SWIER21_Msk    (0x1UL << EXTI_SWIER1_SWIER21_Pos)          /*!< 0x00200000 */
+#define EXTI_SWIER1_SWIER21        EXTI_SWIER1_SWIER21_Msk                     /*!< Software Interrupt on line 21 */
+
+/******************  Bit definition for EXTI_D3PMR1 register  ******************/
+#define EXTI_D3PMR1_MR0_Pos        (0U)
+#define EXTI_D3PMR1_MR0_Msk        (0x1UL << EXTI_D3PMR1_MR0_Pos)              /*!< 0x00000001 */
+#define EXTI_D3PMR1_MR0            EXTI_D3PMR1_MR0_Msk                         /*!< Pending Mask Event for line 0  */
+#define EXTI_D3PMR1_MR1_Pos        (1U)
+#define EXTI_D3PMR1_MR1_Msk        (0x1UL << EXTI_D3PMR1_MR1_Pos)              /*!< 0x00000002 */
+#define EXTI_D3PMR1_MR1            EXTI_D3PMR1_MR1_Msk                         /*!< Pending Mask Event for line 1  */
+#define EXTI_D3PMR1_MR2_Pos        (2U)
+#define EXTI_D3PMR1_MR2_Msk        (0x1UL << EXTI_D3PMR1_MR2_Pos)              /*!< 0x00000004 */
+#define EXTI_D3PMR1_MR2            EXTI_D3PMR1_MR2_Msk                         /*!< Pending Mask Event for line 2  */
+#define EXTI_D3PMR1_MR3_Pos        (3U)
+#define EXTI_D3PMR1_MR3_Msk        (0x1UL << EXTI_D3PMR1_MR3_Pos)              /*!< 0x00000008 */
+#define EXTI_D3PMR1_MR3            EXTI_D3PMR1_MR3_Msk                         /*!< Pending Mask Event for line 3  */
+#define EXTI_D3PMR1_MR4_Pos        (4U)
+#define EXTI_D3PMR1_MR4_Msk        (0x1UL << EXTI_D3PMR1_MR4_Pos)              /*!< 0x00000010 */
+#define EXTI_D3PMR1_MR4            EXTI_D3PMR1_MR4_Msk                         /*!< Pending Mask Event for line 4  */
+#define EXTI_D3PMR1_MR5_Pos        (5U)
+#define EXTI_D3PMR1_MR5_Msk        (0x1UL << EXTI_D3PMR1_MR5_Pos)              /*!< 0x00000020 */
+#define EXTI_D3PMR1_MR5            EXTI_D3PMR1_MR5_Msk                         /*!< Pending Mask Event for line 5  */
+#define EXTI_D3PMR1_MR6_Pos        (6U)
+#define EXTI_D3PMR1_MR6_Msk        (0x1UL << EXTI_D3PMR1_MR6_Pos)              /*!< 0x00000040 */
+#define EXTI_D3PMR1_MR6            EXTI_D3PMR1_MR6_Msk                         /*!< Pending Mask Event for line 6  */
+#define EXTI_D3PMR1_MR7_Pos        (7U)
+#define EXTI_D3PMR1_MR7_Msk        (0x1UL << EXTI_D3PMR1_MR7_Pos)              /*!< 0x00000080 */
+#define EXTI_D3PMR1_MR7            EXTI_D3PMR1_MR7_Msk                         /*!< Pending Mask Event for line 7  */
+#define EXTI_D3PMR1_MR8_Pos        (8U)
+#define EXTI_D3PMR1_MR8_Msk        (0x1UL << EXTI_D3PMR1_MR8_Pos)              /*!< 0x00000100 */
+#define EXTI_D3PMR1_MR8            EXTI_D3PMR1_MR8_Msk                         /*!< Pending Mask Event for line 8  */
+#define EXTI_D3PMR1_MR9_Pos        (9U)
+#define EXTI_D3PMR1_MR9_Msk        (0x1UL << EXTI_D3PMR1_MR9_Pos)              /*!< 0x00000200 */
+#define EXTI_D3PMR1_MR9            EXTI_D3PMR1_MR9_Msk                         /*!< Pending Mask Event for line 9  */
+#define EXTI_D3PMR1_MR10_Pos       (10U)
+#define EXTI_D3PMR1_MR10_Msk       (0x1UL << EXTI_D3PMR1_MR10_Pos)             /*!< 0x00000400 */
+#define EXTI_D3PMR1_MR10           EXTI_D3PMR1_MR10_Msk                        /*!< Pending Mask Event for line 10 */
+#define EXTI_D3PMR1_MR11_Pos       (11U)
+#define EXTI_D3PMR1_MR11_Msk       (0x1UL << EXTI_D3PMR1_MR11_Pos)             /*!< 0x00000800 */
+#define EXTI_D3PMR1_MR11           EXTI_D3PMR1_MR11_Msk                        /*!< Pending Mask Event for line 11 */
+#define EXTI_D3PMR1_MR12_Pos       (12U)
+#define EXTI_D3PMR1_MR12_Msk       (0x1UL << EXTI_D3PMR1_MR12_Pos)             /*!< 0x00001000 */
+#define EXTI_D3PMR1_MR12           EXTI_D3PMR1_MR12_Msk                        /*!< Pending Mask Event for line 12 */
+#define EXTI_D3PMR1_MR13_Pos       (13U)
+#define EXTI_D3PMR1_MR13_Msk       (0x1UL << EXTI_D3PMR1_MR13_Pos)             /*!< 0x00002000 */
+#define EXTI_D3PMR1_MR13           EXTI_D3PMR1_MR13_Msk                        /*!< Pending Mask Event for line 13 */
+#define EXTI_D3PMR1_MR14_Pos       (14U)
+#define EXTI_D3PMR1_MR14_Msk       (0x1UL << EXTI_D3PMR1_MR14_Pos)             /*!< 0x00004000 */
+#define EXTI_D3PMR1_MR14           EXTI_D3PMR1_MR14_Msk                        /*!< Pending Mask Event for line 14 */
+#define EXTI_D3PMR1_MR15_Pos       (15U)
+#define EXTI_D3PMR1_MR15_Msk       (0x1UL << EXTI_D3PMR1_MR15_Pos)             /*!< 0x00008000 */
+#define EXTI_D3PMR1_MR15           EXTI_D3PMR1_MR15_Msk                        /*!< Pending Mask Event for line 15 */
+#define EXTI_D3PMR1_MR19_Pos       (19U)
+#define EXTI_D3PMR1_MR19_Msk       (0x1UL << EXTI_D3PMR1_MR19_Pos)             /*!< 0x00080000 */
+#define EXTI_D3PMR1_MR19           EXTI_D3PMR1_MR19_Msk                        /*!< Pending Mask Event for line 19 */
+#define EXTI_D3PMR1_MR20_Pos       (20U)
+#define EXTI_D3PMR1_MR20_Msk       (0x1UL << EXTI_D3PMR1_MR20_Pos)             /*!< 0x00100000 */
+#define EXTI_D3PMR1_MR20           EXTI_D3PMR1_MR20_Msk                        /*!< Pending Mask Event for line 20 */
+#define EXTI_D3PMR1_MR21_Pos       (21U)
+#define EXTI_D3PMR1_MR21_Msk       (0x1UL << EXTI_D3PMR1_MR21_Pos)             /*!< 0x00200000 */
+#define EXTI_D3PMR1_MR21           EXTI_D3PMR1_MR21_Msk                        /*!< Pending Mask Event for line 21 */
+#define EXTI_D3PMR1_MR25_Pos       (24U)
+#define EXTI_D3PMR1_MR25_Msk       (0x1UL << EXTI_D3PMR1_MR25_Pos)             /*!< 0x01000000 */
+#define EXTI_D3PMR1_MR25           EXTI_D3PMR1_MR25_Msk                        /*!< Pending Mask Event for line 25 */
+
+/*******************  Bit definition for EXTI_D3PCR1L register  ****************/
+#define EXTI_D3PCR1L_PCS0_Pos       (0U)
+#define EXTI_D3PCR1L_PCS0_Msk       (0x3UL << EXTI_D3PCR1L_PCS0_Pos)           /*!< 0x00000003 */
+#define EXTI_D3PCR1L_PCS0           EXTI_D3PCR1L_PCS0_Msk                      /*!< D3 Pending request clear input signal selection on line 0 */
+#define EXTI_D3PCR1L_PCS1_Pos       (2U)
+#define EXTI_D3PCR1L_PCS1_Msk       (0x3UL << EXTI_D3PCR1L_PCS1_Pos)           /*!< 0x000000C0 */
+#define EXTI_D3PCR1L_PCS1           EXTI_D3PCR1L_PCS1_Msk                      /*!< D3 Pending request clear input signal selection on line 1 */
+#define EXTI_D3PCR1L_PCS2_Pos       (4U)
+#define EXTI_D3PCR1L_PCS2_Msk       (0x3UL << EXTI_D3PCR1L_PCS2_Pos)           /*!< 0x00000030 */
+#define EXTI_D3PCR1L_PCS2           EXTI_D3PCR1L_PCS2_Msk                      /*!< D3 Pending request clear input signal selection on line 2 */
+#define EXTI_D3PCR1L_PCS3_Pos       (6U)
+#define EXTI_D3PCR1L_PCS3_Msk       (0x3UL << EXTI_D3PCR1L_PCS3_Pos)           /*!< 0x000000C0 */
+#define EXTI_D3PCR1L_PCS3           EXTI_D3PCR1L_PCS3_Msk                      /*!< D3 Pending request clear input signal selection on line 3 */
+#define EXTI_D3PCR1L_PCS4_Pos       (8U)
+#define EXTI_D3PCR1L_PCS4_Msk       (0x3UL << EXTI_D3PCR1L_PCS4_Pos)           /*!< 0x00000300 */
+#define EXTI_D3PCR1L_PCS4           EXTI_D3PCR1L_PCS4_Msk                      /*!< D3 Pending request clear input signal selection on line 4 */
+#define EXTI_D3PCR1L_PCS5_Pos       (10U)
+#define EXTI_D3PCR1L_PCS5_Msk       (0x3UL << EXTI_D3PCR1L_PCS5_Pos)           /*!< 0x00000C00 */
+#define EXTI_D3PCR1L_PCS5           EXTI_D3PCR1L_PCS5_Msk                      /*!< D3 Pending request clear input signal selection on line 5 */
+#define EXTI_D3PCR1L_PCS6_Pos       (12U)
+#define EXTI_D3PCR1L_PCS6_Msk       (0x3UL << EXTI_D3PCR1L_PCS6_Pos)           /*!< 0x00003000 */
+#define EXTI_D3PCR1L_PCS6           EXTI_D3PCR1L_PCS6_Msk                      /*!< D3 Pending request clear input signal selection on line 6 */
+#define EXTI_D3PCR1L_PCS7_Pos       (14U)
+#define EXTI_D3PCR1L_PCS7_Msk       (0x3UL << EXTI_D3PCR1L_PCS7_Pos)           /*!< 0x0000C000 */
+#define EXTI_D3PCR1L_PCS7           EXTI_D3PCR1L_PCS7_Msk                      /*!< D3 Pending request clear input signal selection on line 7 */
+#define EXTI_D3PCR1L_PCS8_Pos       (16U)
+#define EXTI_D3PCR1L_PCS8_Msk       (0x3UL << EXTI_D3PCR1L_PCS8_Pos)           /*!< 0x00030000 */
+#define EXTI_D3PCR1L_PCS8           EXTI_D3PCR1L_PCS8_Msk                      /*!< D3 Pending request clear input signal selection on line 8 */
+#define EXTI_D3PCR1L_PCS9_Pos       (18U)
+#define EXTI_D3PCR1L_PCS9_Msk       (0x3UL << EXTI_D3PCR1L_PCS9_Pos)           /*!< 0x000C0000 */
+#define EXTI_D3PCR1L_PCS9           EXTI_D3PCR1L_PCS9_Msk                      /*!< D3 Pending request clear input signal selection on line 9 */
+#define EXTI_D3PCR1L_PCS10_Pos      (20U)
+#define EXTI_D3PCR1L_PCS10_Msk      (0x3UL << EXTI_D3PCR1L_PCS10_Pos)          /*!< 0x00300000 */
+#define EXTI_D3PCR1L_PCS10          EXTI_D3PCR1L_PCS10_Msk                     /*!< D3 Pending request clear input signal selection on line 10*/
+#define EXTI_D3PCR1L_PCS11_Pos      (22U)
+#define EXTI_D3PCR1L_PCS11_Msk      (0x3UL << EXTI_D3PCR1L_PCS11_Pos)          /*!< 0x00C00000 */
+#define EXTI_D3PCR1L_PCS11          EXTI_D3PCR1L_PCS11_Msk                     /*!< D3 Pending request clear input signal selection on line 11*/
+#define EXTI_D3PCR1L_PCS12_Pos      (24U)
+#define EXTI_D3PCR1L_PCS12_Msk      (0x3UL << EXTI_D3PCR1L_PCS12_Pos)          /*!< 0x03000000 */
+#define EXTI_D3PCR1L_PCS12          EXTI_D3PCR1L_PCS12_Msk                     /*!< D3 Pending request clear input signal selection on line 12*/
+#define EXTI_D3PCR1L_PCS13_Pos      (26U)
+#define EXTI_D3PCR1L_PCS13_Msk      (0x3UL << EXTI_D3PCR1L_PCS13_Pos)          /*!< 0x0C000000 */
+#define EXTI_D3PCR1L_PCS13          EXTI_D3PCR1L_PCS13_Msk                     /*!< D3 Pending request clear input signal selection on line 13*/
+#define EXTI_D3PCR1L_PCS14_Pos      (28U)
+#define EXTI_D3PCR1L_PCS14_Msk      (0x3UL << EXTI_D3PCR1L_PCS14_Pos)          /*!< 0x30000000 */
+#define EXTI_D3PCR1L_PCS14          EXTI_D3PCR1L_PCS14_Msk                     /*!< D3 Pending request clear input signal selection on line 14*/
+#define EXTI_D3PCR1L_PCS15_Pos      (30U)
+#define EXTI_D3PCR1L_PCS15_Msk      (0x3UL << EXTI_D3PCR1L_PCS15_Pos)          /*!< 0xC0000000 */
+#define EXTI_D3PCR1L_PCS15          EXTI_D3PCR1L_PCS15_Msk                     /*!< D3 Pending request clear input signal selection on line 15*/
+
+/*******************  Bit definition for EXTI_D3PCR1H register  ****************/
+#define EXTI_D3PCR1H_PCS19_Pos       (6U)
+#define EXTI_D3PCR1H_PCS19_Msk       (0x3UL << EXTI_D3PCR1H_PCS19_Pos)         /*!< 0x000000C0 */
+#define EXTI_D3PCR1H_PCS19           EXTI_D3PCR1H_PCS19_Msk                    /*!< D3 Pending request clear input signal selection on line 19 */
+#define EXTI_D3PCR1H_PCS20_Pos       (8U)
+#define EXTI_D3PCR1H_PCS20_Msk       (0x3UL << EXTI_D3PCR1H_PCS20_Pos)         /*!< 0x00000300 */
+#define EXTI_D3PCR1H_PCS20           EXTI_D3PCR1H_PCS20_Msk                    /*!< D3 Pending request clear input signal selection on line 20 */
+#define EXTI_D3PCR1H_PCS21_Pos       (10U)
+#define EXTI_D3PCR1H_PCS21_Msk       (0x3UL << EXTI_D3PCR1H_PCS21_Pos)         /*!< 0x00000C00 */
+#define EXTI_D3PCR1H_PCS21           EXTI_D3PCR1H_PCS21_Msk                    /*!< D3 Pending request clear input signal selection on line 21 */
+#define EXTI_D3PCR1H_PCS25_Pos       (18U)
+#define EXTI_D3PCR1H_PCS25_Msk       (0x3UL << EXTI_D3PCR1H_PCS25_Pos)         /*!< 0x000C0000 */
+#define EXTI_D3PCR1H_PCS25           EXTI_D3PCR1H_PCS25_Msk                    /*!< D3 Pending request clear input signal selection on line 25 */
+
+/******************  Bit definition for EXTI_RTSR2 register  *******************/
+#define EXTI_RTSR2_TR_Pos          (17U)
+#define EXTI_RTSR2_TR_Msk          (0x5UL << EXTI_RTSR2_TR_Pos)                /*!< 0x000A0000 */
+#define EXTI_RTSR2_TR              EXTI_RTSR2_TR_Msk                           /*!< Rising trigger event configuration bit */
+#define EXTI_RTSR2_TR49_Pos        (17U)
+#define EXTI_RTSR2_TR49_Msk        (0x1UL << EXTI_RTSR2_TR49_Pos)              /*!< 0x00020000 */
+#define EXTI_RTSR2_TR49            EXTI_RTSR2_TR49_Msk                         /*!< Rising trigger event configuration bit of line 49 */
+#define EXTI_RTSR2_TR51_Pos        (19U)
+#define EXTI_RTSR2_TR51_Msk        (0x1UL << EXTI_RTSR2_TR51_Pos)              /*!< 0x00080000 */
+#define EXTI_RTSR2_TR51            EXTI_RTSR2_TR51_Msk                         /*!< Rising trigger event configuration bit of line 51 */
+
+/******************  Bit definition for EXTI_FTSR2 register  *******************/
+#define EXTI_FTSR2_TR_Pos          (17U)
+#define EXTI_FTSR2_TR_Msk          (0x5UL << EXTI_FTSR2_TR_Pos)                /*!< 0x000A0000 */
+#define EXTI_FTSR2_TR              EXTI_FTSR2_TR_Msk                           /*!< Falling trigger event configuration bit */
+#define EXTI_FTSR2_TR49_Pos        (17U)
+#define EXTI_FTSR2_TR49_Msk        (0x1UL << EXTI_FTSR2_TR49_Pos)              /*!< 0x00020000 */
+#define EXTI_FTSR2_TR49            EXTI_FTSR2_TR49_Msk                         /*!< Falling trigger event configuration bit of line 49 */
+#define EXTI_FTSR2_TR51_Pos        (19U)
+#define EXTI_FTSR2_TR51_Msk        (0x1UL << EXTI_FTSR2_TR51_Pos)              /*!< 0x00080000 */
+#define EXTI_FTSR2_TR51            EXTI_FTSR2_TR51_Msk                         /*!< Falling trigger event configuration bit of line 51 */
+
+/******************  Bit definition for EXTI_SWIER2 register  ******************/
+#define EXTI_SWIER2_SWIER49_Pos    (17U)
+#define EXTI_SWIER2_SWIER49_Msk    (0x1UL << EXTI_SWIER2_SWIER49_Pos)          /*!< 0x00020000 */
+#define EXTI_SWIER2_SWIER49        EXTI_SWIER2_SWIER49_Msk                     /*!< Software Interrupt on line 49 */
+#define EXTI_SWIER2_SWIER51_Pos    (19U)
+#define EXTI_SWIER2_SWIER51_Msk    (0x1UL << EXTI_SWIER2_SWIER51_Pos)          /*!< 0x00080000 */
+#define EXTI_SWIER2_SWIER51        EXTI_SWIER2_SWIER51_Msk                     /*!< Software Interrupt on line 51 */
+
+/******************  Bit definition for EXTI_D3PMR2 register  ******************/
+#define EXTI_D3PMR2_MR34_Pos       (2U)
+#define EXTI_D3PMR2_MR34_Msk       (0x1UL << EXTI_D3PMR2_MR34_Pos)             /*!< 0x00000004 */
+#define EXTI_D3PMR2_MR34           EXTI_D3PMR2_MR34_Msk                        /*!< Pending Mask Event for line 34  */
+#define EXTI_D3PMR2_MR35_Pos       (3U)
+#define EXTI_D3PMR2_MR35_Msk       (0x1UL << EXTI_D3PMR2_MR35_Pos)             /*!< 0x00000008 */
+#define EXTI_D3PMR2_MR35           EXTI_D3PMR2_MR35_Msk                        /*!< Pending Mask Event for line 35  */
+#define EXTI_D3PMR2_MR41_Pos       (9U)
+#define EXTI_D3PMR2_MR41_Msk       (0x1UL << EXTI_D3PMR2_MR41_Pos)             /*!< 0x00000200 */
+#define EXTI_D3PMR2_MR41           EXTI_D3PMR2_MR41_Msk                        /*!< Pending Mask Event for line 41  */
+#define EXTI_D3PMR2_MR48_Pos       (16U)
+#define EXTI_D3PMR2_MR48_Msk       (0x1UL << EXTI_D3PMR2_MR48_Pos)             /*!< 0x00010000 */
+#define EXTI_D3PMR2_MR48           EXTI_D3PMR2_MR48_Msk                        /*!< Pending Mask Event for line 48  */
+#define EXTI_D3PMR2_MR49_Pos       (17U)
+#define EXTI_D3PMR2_MR49_Msk       (0x1UL << EXTI_D3PMR2_MR49_Pos)             /*!< 0x00020000 */
+#define EXTI_D3PMR2_MR49           EXTI_D3PMR2_MR49_Msk                        /*!< Pending Mask Event for line 49  */
+#define EXTI_D3PMR2_MR50_Pos       (18U)
+#define EXTI_D3PMR2_MR50_Msk       (0x1UL << EXTI_D3PMR2_MR50_Pos)             /*!< 0x00040000 */
+#define EXTI_D3PMR2_MR50           EXTI_D3PMR2_MR50_Msk                        /*!< Pending Mask Event for line 50  */
+#define EXTI_D3PMR2_MR51_Pos       (19U)
+#define EXTI_D3PMR2_MR51_Msk       (0x1UL << EXTI_D3PMR2_MR51_Pos)             /*!< 0x00080000 */
+#define EXTI_D3PMR2_MR51           EXTI_D3PMR2_MR51_Msk                        /*!< Pending Mask Event for line 51  */
+#define EXTI_D3PMR2_MR52_Pos       (20U)
+#define EXTI_D3PMR2_MR52_Msk       (0x1UL << EXTI_D3PMR2_MR52_Pos)             /*!< 0x00100000 */
+#define EXTI_D3PMR2_MR52           EXTI_D3PMR2_MR52_Msk                        /*!< Pending Mask Event for line 52  */
+#define EXTI_D3PMR2_MR53_Pos       (21U)
+#define EXTI_D3PMR2_MR53_Msk       (0x1UL << EXTI_D3PMR2_MR53_Pos)             /*!< 0x00200000 */
+#define EXTI_D3PMR2_MR53           EXTI_D3PMR2_MR53_Msk                        /*!< Pending Mask Event for line 53  */
+/*******************  Bit definition for EXTI_D3PCR2L register  ****************/
+#define EXTI_D3PCR2L_PCS34_Pos       (4U)
+#define EXTI_D3PCR2L_PCS34_Msk       (0x3UL << EXTI_D3PCR2L_PCS34_Pos)         /*!< 0x00000030 */
+#define EXTI_D3PCR2L_PCS34           EXTI_D3PCR2L_PCS34_Msk                    /*!< D3 Pending request clear input signal selection on line 34 */
+#define EXTI_D3PCR2L_PCS35_Pos       (6U)
+#define EXTI_D3PCR2L_PCS35_Msk       (0x3UL << EXTI_D3PCR2L_PCS35_Pos)         /*!< 0x000000C0 */
+#define EXTI_D3PCR2L_PCS35           EXTI_D3PCR2L_PCS35_Msk                    /*!< D3 Pending request clear input signal selection on line 35 */
+#define EXTI_D3PCR2L_PCS41_Pos       (18U)
+#define EXTI_D3PCR2L_PCS41_Msk       (0x3UL << EXTI_D3PCR2L_PCS41_Pos)         /*!< 0x000C0000 */
+#define EXTI_D3PCR2L_PCS41           EXTI_D3PCR2L_PCS41_Msk                    /*!< D3 Pending request clear input signal selection on line 41 */
+
+
+/*******************  Bit definition for EXTI_D3PCR2H register  ****************/
+#define EXTI_D3PCR2H_PCS48_Pos       (0U)
+#define EXTI_D3PCR2H_PCS48_Msk       (0x3UL << EXTI_D3PCR2H_PCS48_Pos)         /*!< 0x00000003 */
+#define EXTI_D3PCR2H_PCS48           EXTI_D3PCR2H_PCS48_Msk                    /*!< D3 Pending request clear input signal selection on line 48 */
+#define EXTI_D3PCR2H_PCS49_Pos       (2U)
+#define EXTI_D3PCR2H_PCS49_Msk       (0x3UL << EXTI_D3PCR2H_PCS49_Pos)         /*!< 0x0000000C */
+#define EXTI_D3PCR2H_PCS49           EXTI_D3PCR2H_PCS49_Msk                    /*!< D3 Pending request clear input signal selection on line 49 */
+#define EXTI_D3PCR2H_PCS50_Pos       (4U)
+#define EXTI_D3PCR2H_PCS50_Msk       (0x3UL << EXTI_D3PCR2H_PCS50_Pos)         /*!< 0x00000030 */
+#define EXTI_D3PCR2H_PCS50           EXTI_D3PCR2H_PCS50_Msk                    /*!< D3 Pending request clear input signal selection on line 50 */
+#define EXTI_D3PCR2H_PCS51_Pos       (6U)
+#define EXTI_D3PCR2H_PCS51_Msk       (0x3UL << EXTI_D3PCR2H_PCS51_Pos)         /*!< 0x000000C0 */
+#define EXTI_D3PCR2H_PCS51           EXTI_D3PCR2H_PCS51_Msk                    /*!< D3 Pending request clear input signal selection on line 51 */
+#define EXTI_D3PCR2H_PCS52_Pos       (8U)
+#define EXTI_D3PCR2H_PCS52_Msk       (0x3UL << EXTI_D3PCR2H_PCS52_Pos)         /*!< 0x00000300 */
+#define EXTI_D3PCR2H_PCS52           EXTI_D3PCR2H_PCS52_Msk                    /*!< D3 Pending request clear input signal selection on line 52 */
+#define EXTI_D3PCR2H_PCS53_Pos       (10U)
+#define EXTI_D3PCR2H_PCS53_Msk       (0x3UL << EXTI_D3PCR2H_PCS53_Pos)         /*!< 0x00000C00 */
+#define EXTI_D3PCR2H_PCS53           EXTI_D3PCR2H_PCS53_Msk                    /*!< D3 Pending request clear input signal selection on line 53 */
+/******************  Bit definition for EXTI_RTSR3 register  *******************/
+#define EXTI_RTSR3_TR_Pos          (18U)
+#define EXTI_RTSR3_TR_Msk          (0x1DUL << EXTI_RTSR3_TR_Pos)               /*!< 0x00740000 */
+#define EXTI_RTSR3_TR              EXTI_RTSR3_TR_Msk                           /*!< Rising trigger event configuration bit */
+#define EXTI_RTSR3_TR82_Pos        (18U)
+#define EXTI_RTSR3_TR82_Msk        (0x1UL << EXTI_RTSR3_TR82_Pos)              /*!< 0x00040000 */
+#define EXTI_RTSR3_TR82            EXTI_RTSR3_TR82_Msk                         /*!< Rising trigger event configuration bit of line 82 */
+#define EXTI_RTSR3_TR84_Pos        (20U)
+#define EXTI_RTSR3_TR84_Msk        (0x1UL << EXTI_RTSR3_TR84_Pos)              /*!< 0x00100000 */
+#define EXTI_RTSR3_TR84            EXTI_RTSR3_TR84_Msk                         /*!< Rising trigger event configuration bit of line 84 */
+#define EXTI_RTSR3_TR85_Pos        (21U)
+#define EXTI_RTSR3_TR85_Msk        (0x1UL << EXTI_RTSR3_TR85_Pos)              /*!< 0x00200000 */
+#define EXTI_RTSR3_TR85            EXTI_RTSR3_TR85_Msk                         /*!< Rising trigger event configuration bit of line 85 */
+#define EXTI_RTSR3_TR86_Pos        (22U)
+#define EXTI_RTSR3_TR86_Msk        (0x1UL << EXTI_RTSR3_TR86_Pos)              /*!< 0x00400000 */
+#define EXTI_RTSR3_TR86            EXTI_RTSR3_TR86_Msk                         /*!< Rising trigger event configuration bit of line 86 */
+
+/******************  Bit definition for EXTI_FTSR3 register  *******************/
+#define EXTI_FTSR3_TR_Pos          (18U)
+#define EXTI_FTSR3_TR_Msk          (0x1DUL << EXTI_FTSR3_TR_Pos)               /*!< 0x00740000 */
+#define EXTI_FTSR3_TR              EXTI_FTSR3_TR_Msk                           /*!< Falling trigger event configuration bit */
+#define EXTI_FTSR3_TR82_Pos        (18U)
+#define EXTI_FTSR3_TR82_Msk        (0x1UL << EXTI_FTSR3_TR82_Pos)              /*!< 0x00040000 */
+#define EXTI_FTSR3_TR82            EXTI_FTSR3_TR82_Msk                         /*!< Falling trigger event configuration bit of line 82 */
+#define EXTI_FTSR3_TR84_Pos        (20U)
+#define EXTI_FTSR3_TR84_Msk        (0x1UL << EXTI_FTSR3_TR84_Pos)              /*!< 0x00100000 */
+#define EXTI_FTSR3_TR84            EXTI_FTSR3_TR84_Msk                         /*!< Falling trigger event configuration bit of line 84 */
+#define EXTI_FTSR3_TR85_Pos        (21U)
+#define EXTI_FTSR3_TR85_Msk        (0x1UL << EXTI_FTSR3_TR85_Pos)              /*!< 0x00200000 */
+#define EXTI_FTSR3_TR85            EXTI_FTSR3_TR85_Msk                         /*!< Falling trigger event configuration bit of line 85 */
+#define EXTI_FTSR3_TR86_Pos        (22U)
+#define EXTI_FTSR3_TR86_Msk        (0x1UL << EXTI_FTSR3_TR86_Pos)              /*!< 0x00400000 */
+#define EXTI_FTSR3_TR86            EXTI_FTSR3_TR86_Msk                         /*!< Falling trigger event configuration bit of line 86 */
+
+/******************  Bit definition for EXTI_SWIER3 register  ******************/
+#define EXTI_SWIER3_SWI_Pos        (18U)
+#define EXTI_SWIER3_SWI_Msk        (0x1DUL << EXTI_SWIER3_SWI_Pos)             /*!< 0x00740000 */
+#define EXTI_SWIER3_SWI            EXTI_SWIER3_SWI_Msk                         /*!< Software Interrupt event bit */
+#define EXTI_SWIER3_SWIER82_Pos    (18U)
+#define EXTI_SWIER3_SWIER82_Msk    (0x1UL << EXTI_SWIER3_SWIER82_Pos)          /*!< 0x00040000 */
+#define EXTI_SWIER3_SWIER82        EXTI_SWIER3_SWIER82_Msk                     /*!< Software Interrupt on line 82 */
+#define EXTI_SWIER3_SWIER84_Pos    (20U)
+#define EXTI_SWIER3_SWIER84_Msk    (0x1UL << EXTI_SWIER3_SWIER84_Pos)          /*!< 0x00100000 */
+#define EXTI_SWIER3_SWIER84        EXTI_SWIER3_SWIER84_Msk                     /*!< Software Interrupt on line 84 */
+#define EXTI_SWIER3_SWIER85_Pos    (21U)
+#define EXTI_SWIER3_SWIER85_Msk    (0x1UL << EXTI_SWIER3_SWIER85_Pos)          /*!< 0x00200000 */
+#define EXTI_SWIER3_SWIER85        EXTI_SWIER3_SWIER85_Msk                     /*!< Software Interrupt on line 85 */
+#define EXTI_SWIER3_SWIER86_Pos    (22U)
+#define EXTI_SWIER3_SWIER86_Msk    (0x1UL << EXTI_SWIER3_SWIER86_Pos)          /*!< 0x00400000 */
+#define EXTI_SWIER3_SWIER86        EXTI_SWIER3_SWIER86_Msk                     /*!< Software Interrupt on line 86 */
+
+/*******************  Bit definition for EXTI_IMR1 register  *******************/
+#define EXTI_IMR1_IM_Pos           (0U)
+#define EXTI_IMR1_IM_Msk           (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos)          /*!< 0xFFFFFFFF */
+#define EXTI_IMR1_IM               EXTI_IMR1_IM_Msk                            /*!< Interrupt Mask */
+#define EXTI_IMR1_IM0_Pos          (0U)
+#define EXTI_IMR1_IM0_Msk          (0x1UL << EXTI_IMR1_IM0_Pos)                /*!< 0x00000001 */
+#define EXTI_IMR1_IM0              EXTI_IMR1_IM0_Msk                           /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR1_IM1_Pos          (1U)
+#define EXTI_IMR1_IM1_Msk          (0x1UL << EXTI_IMR1_IM1_Pos)                /*!< 0x00000002 */
+#define EXTI_IMR1_IM1              EXTI_IMR1_IM1_Msk                           /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR1_IM2_Pos          (2U)
+#define EXTI_IMR1_IM2_Msk          (0x1UL << EXTI_IMR1_IM2_Pos)                /*!< 0x00000004 */
+#define EXTI_IMR1_IM2              EXTI_IMR1_IM2_Msk                           /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR1_IM3_Pos          (3U)
+#define EXTI_IMR1_IM3_Msk          (0x1UL << EXTI_IMR1_IM3_Pos)                /*!< 0x00000008 */
+#define EXTI_IMR1_IM3              EXTI_IMR1_IM3_Msk                           /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR1_IM4_Pos          (4U)
+#define EXTI_IMR1_IM4_Msk          (0x1UL << EXTI_IMR1_IM4_Pos)                /*!< 0x00000010 */
+#define EXTI_IMR1_IM4              EXTI_IMR1_IM4_Msk                           /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR1_IM5_Pos          (5U)
+#define EXTI_IMR1_IM5_Msk          (0x1UL << EXTI_IMR1_IM5_Pos)                /*!< 0x00000020 */
+#define EXTI_IMR1_IM5              EXTI_IMR1_IM5_Msk                           /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR1_IM6_Pos          (6U)
+#define EXTI_IMR1_IM6_Msk          (0x1UL << EXTI_IMR1_IM6_Pos)                /*!< 0x00000040 */
+#define EXTI_IMR1_IM6              EXTI_IMR1_IM6_Msk                           /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR1_IM7_Pos          (7U)
+#define EXTI_IMR1_IM7_Msk          (0x1UL << EXTI_IMR1_IM7_Pos)                /*!< 0x00000080 */
+#define EXTI_IMR1_IM7              EXTI_IMR1_IM7_Msk                           /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR1_IM8_Pos          (8U)
+#define EXTI_IMR1_IM8_Msk          (0x1UL << EXTI_IMR1_IM8_Pos)                /*!< 0x00000100 */
+#define EXTI_IMR1_IM8              EXTI_IMR1_IM8_Msk                           /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR1_IM9_Pos          (9U)
+#define EXTI_IMR1_IM9_Msk          (0x1UL << EXTI_IMR1_IM9_Pos)                /*!< 0x00000200 */
+#define EXTI_IMR1_IM9              EXTI_IMR1_IM9_Msk                           /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR1_IM10_Pos         (10U)
+#define EXTI_IMR1_IM10_Msk         (0x1UL << EXTI_IMR1_IM10_Pos)               /*!< 0x00000400 */
+#define EXTI_IMR1_IM10             EXTI_IMR1_IM10_Msk                          /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR1_IM11_Pos         (11U)
+#define EXTI_IMR1_IM11_Msk         (0x1UL << EXTI_IMR1_IM11_Pos)               /*!< 0x00000800 */
+#define EXTI_IMR1_IM11             EXTI_IMR1_IM11_Msk                          /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR1_IM12_Pos         (12U)
+#define EXTI_IMR1_IM12_Msk         (0x1UL << EXTI_IMR1_IM12_Pos)               /*!< 0x00001000 */
+#define EXTI_IMR1_IM12             EXTI_IMR1_IM12_Msk                          /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR1_IM13_Pos         (13U)
+#define EXTI_IMR1_IM13_Msk         (0x1UL << EXTI_IMR1_IM13_Pos)               /*!< 0x00002000 */
+#define EXTI_IMR1_IM13             EXTI_IMR1_IM13_Msk                          /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR1_IM14_Pos         (14U)
+#define EXTI_IMR1_IM14_Msk         (0x1UL << EXTI_IMR1_IM14_Pos)               /*!< 0x00004000 */
+#define EXTI_IMR1_IM14             EXTI_IMR1_IM14_Msk                          /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR1_IM15_Pos         (15U)
+#define EXTI_IMR1_IM15_Msk         (0x1UL << EXTI_IMR1_IM15_Pos)               /*!< 0x00008000 */
+#define EXTI_IMR1_IM15             EXTI_IMR1_IM15_Msk                          /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR1_IM16_Pos         (16U)
+#define EXTI_IMR1_IM16_Msk         (0x1UL << EXTI_IMR1_IM16_Pos)               /*!< 0x00010000 */
+#define EXTI_IMR1_IM16             EXTI_IMR1_IM16_Msk                          /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR1_IM17_Pos         (17U)
+#define EXTI_IMR1_IM17_Msk         (0x1UL << EXTI_IMR1_IM17_Pos)               /*!< 0x00020000 */
+#define EXTI_IMR1_IM17             EXTI_IMR1_IM17_Msk                          /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR1_IM18_Pos         (18U)
+#define EXTI_IMR1_IM18_Msk         (0x1UL << EXTI_IMR1_IM18_Pos)               /*!< 0x00040000 */
+#define EXTI_IMR1_IM18             EXTI_IMR1_IM18_Msk                          /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR1_IM19_Pos         (19U)
+#define EXTI_IMR1_IM19_Msk         (0x1UL << EXTI_IMR1_IM19_Pos)               /*!< 0x00080000 */
+#define EXTI_IMR1_IM19             EXTI_IMR1_IM19_Msk                          /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR1_IM20_Pos         (20U)
+#define EXTI_IMR1_IM20_Msk         (0x1UL << EXTI_IMR1_IM20_Pos)               /*!< 0x00100000 */
+#define EXTI_IMR1_IM20             EXTI_IMR1_IM20_Msk                          /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR1_IM21_Pos         (21U)
+#define EXTI_IMR1_IM21_Msk         (0x1UL << EXTI_IMR1_IM21_Pos)               /*!< 0x00200000 */
+#define EXTI_IMR1_IM21             EXTI_IMR1_IM21_Msk                          /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR1_IM22_Pos         (22U)
+#define EXTI_IMR1_IM22_Msk         (0x1UL << EXTI_IMR1_IM22_Pos)               /*!< 0x00400000 */
+#define EXTI_IMR1_IM22             EXTI_IMR1_IM22_Msk                          /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR1_IM23_Pos         (23U)
+#define EXTI_IMR1_IM23_Msk         (0x1UL << EXTI_IMR1_IM23_Pos)               /*!< 0x00800000 */
+#define EXTI_IMR1_IM23             EXTI_IMR1_IM23_Msk                          /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR1_IM24_Pos         (24U)
+#define EXTI_IMR1_IM24_Msk         (0x1UL << EXTI_IMR1_IM24_Pos)               /*!< 0x01000000 */
+#define EXTI_IMR1_IM24             EXTI_IMR1_IM24_Msk                          /*!< Interrupt Mask on line 24 */
+#define EXTI_IMR1_IM25_Pos         (25U)
+#define EXTI_IMR1_IM25_Msk         (0x1UL << EXTI_IMR1_IM25_Pos)               /*!< 0x02000000 */
+#define EXTI_IMR1_IM25             EXTI_IMR1_IM25_Msk                          /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR1_IM26_Pos         (26U)
+#define EXTI_IMR1_IM26_Msk         (0x1UL << EXTI_IMR1_IM26_Pos)               /*!< 0x04000000 */
+#define EXTI_IMR1_IM26             EXTI_IMR1_IM26_Msk                          /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR1_IM27_Pos         (27U)
+#define EXTI_IMR1_IM27_Msk         (0x1UL << EXTI_IMR1_IM27_Pos)               /*!< 0x08000000 */
+#define EXTI_IMR1_IM27             EXTI_IMR1_IM27_Msk                          /*!< Interrupt Mask on line 27 */
+#define EXTI_IMR1_IM28_Pos         (28U)
+#define EXTI_IMR1_IM28_Msk         (0x1UL << EXTI_IMR1_IM28_Pos)               /*!< 0x10000000 */
+#define EXTI_IMR1_IM28             EXTI_IMR1_IM28_Msk                          /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR1_IM29_Pos         (29U)
+#define EXTI_IMR1_IM29_Msk         (0x1UL << EXTI_IMR1_IM29_Pos)               /*!< 0x20000000 */
+#define EXTI_IMR1_IM29             EXTI_IMR1_IM29_Msk                          /*!< Interrupt Mask on line 29 */
+#define EXTI_IMR1_IM30_Pos         (30U)
+#define EXTI_IMR1_IM30_Msk         (0x1UL << EXTI_IMR1_IM30_Pos)               /*!< 0x40000000 */
+#define EXTI_IMR1_IM30             EXTI_IMR1_IM30_Msk                          /*!< Interrupt Mask on line 30 */
+#define EXTI_IMR1_IM31_Pos         (31U)
+#define EXTI_IMR1_IM31_Msk         (0x1UL << EXTI_IMR1_IM31_Pos)               /*!< 0x80000000 */
+#define EXTI_IMR1_IM31             EXTI_IMR1_IM31_Msk                          /*!< Interrupt Mask on line 31 */
+
+/*******************  Bit definition for EXTI_EMR1 register  *******************/
+#define EXTI_EMR1_EM_Pos           (0U)
+#define EXTI_EMR1_EM_Msk           (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos)          /*!< 0xFFFFFFFF */
+#define EXTI_EMR1_EM               EXTI_EMR1_EM_Msk                            /*!< Event Mask */
+#define EXTI_EMR1_EM0_Pos          (0U)
+#define EXTI_EMR1_EM0_Msk          (0x1UL << EXTI_EMR1_EM0_Pos)                /*!< 0x00000001 */
+#define EXTI_EMR1_EM0              EXTI_EMR1_EM0_Msk                           /*!< Event Mask on line 0 */
+#define EXTI_EMR1_EM1_Pos          (1U)
+#define EXTI_EMR1_EM1_Msk          (0x1UL << EXTI_EMR1_EM1_Pos)                /*!< 0x00000002 */
+#define EXTI_EMR1_EM1              EXTI_EMR1_EM1_Msk                           /*!< Event Mask on line 1 */
+#define EXTI_EMR1_EM2_Pos          (2U)
+#define EXTI_EMR1_EM2_Msk          (0x1UL << EXTI_EMR1_EM2_Pos)                /*!< 0x00000004 */
+#define EXTI_EMR1_EM2              EXTI_EMR1_EM2_Msk                           /*!< Event Mask on line 2 */
+#define EXTI_EMR1_EM3_Pos          (3U)
+#define EXTI_EMR1_EM3_Msk          (0x1UL << EXTI_EMR1_EM3_Pos)                /*!< 0x00000008 */
+#define EXTI_EMR1_EM3              EXTI_EMR1_EM3_Msk                           /*!< Event Mask on line 3 */
+#define EXTI_EMR1_EM4_Pos          (4U)
+#define EXTI_EMR1_EM4_Msk          (0x1UL << EXTI_EMR1_EM4_Pos)                /*!< 0x00000010 */
+#define EXTI_EMR1_EM4              EXTI_EMR1_EM4_Msk                           /*!< Event Mask on line 4 */
+#define EXTI_EMR1_EM5_Pos          (5U)
+#define EXTI_EMR1_EM5_Msk          (0x1UL << EXTI_EMR1_EM5_Pos)                /*!< 0x00000020 */
+#define EXTI_EMR1_EM5              EXTI_EMR1_EM5_Msk                           /*!< Event Mask on line 5 */
+#define EXTI_EMR1_EM6_Pos          (6U)
+#define EXTI_EMR1_EM6_Msk          (0x1UL << EXTI_EMR1_EM6_Pos)                /*!< 0x00000040 */
+#define EXTI_EMR1_EM6              EXTI_EMR1_EM6_Msk                           /*!< Event Mask on line 6 */
+#define EXTI_EMR1_EM7_Pos          (7U)
+#define EXTI_EMR1_EM7_Msk          (0x1UL << EXTI_EMR1_EM7_Pos)                /*!< 0x00000080 */
+#define EXTI_EMR1_EM7              EXTI_EMR1_EM7_Msk                           /*!< Event Mask on line 7 */
+#define EXTI_EMR1_EM8_Pos          (8U)
+#define EXTI_EMR1_EM8_Msk          (0x1UL << EXTI_EMR1_EM8_Pos)                /*!< 0x00000100 */
+#define EXTI_EMR1_EM8              EXTI_EMR1_EM8_Msk                           /*!< Event Mask on line 8 */
+#define EXTI_EMR1_EM9_Pos          (9U)
+#define EXTI_EMR1_EM9_Msk          (0x1UL << EXTI_EMR1_EM9_Pos)                /*!< 0x00000200 */
+#define EXTI_EMR1_EM9              EXTI_EMR1_EM9_Msk                           /*!< Event Mask on line 9 */
+#define EXTI_EMR1_EM10_Pos         (10U)
+#define EXTI_EMR1_EM10_Msk         (0x1UL << EXTI_EMR1_EM10_Pos)               /*!< 0x00000400 */
+#define EXTI_EMR1_EM10             EXTI_EMR1_EM10_Msk                          /*!< Event Mask on line 10 */
+#define EXTI_EMR1_EM11_Pos         (11U)
+#define EXTI_EMR1_EM11_Msk         (0x1UL << EXTI_EMR1_EM11_Pos)               /*!< 0x00000800 */
+#define EXTI_EMR1_EM11             EXTI_EMR1_EM11_Msk                          /*!< Event Mask on line 11 */
+#define EXTI_EMR1_EM12_Pos         (12U)
+#define EXTI_EMR1_EM12_Msk         (0x1UL << EXTI_EMR1_EM12_Pos)               /*!< 0x00001000 */
+#define EXTI_EMR1_EM12             EXTI_EMR1_EM12_Msk                          /*!< Event Mask on line 12 */
+#define EXTI_EMR1_EM13_Pos         (13U)
+#define EXTI_EMR1_EM13_Msk         (0x1UL << EXTI_EMR1_EM13_Pos)               /*!< 0x00002000 */
+#define EXTI_EMR1_EM13             EXTI_EMR1_EM13_Msk                          /*!< Event Mask on line 13 */
+#define EXTI_EMR1_EM14_Pos         (14U)
+#define EXTI_EMR1_EM14_Msk         (0x1UL << EXTI_EMR1_EM14_Pos)               /*!< 0x00004000 */
+#define EXTI_EMR1_EM14             EXTI_EMR1_EM14_Msk                          /*!< Event Mask on line 14 */
+#define EXTI_EMR1_EM15_Pos         (15U)
+#define EXTI_EMR1_EM15_Msk         (0x1UL << EXTI_EMR1_EM15_Pos)               /*!< 0x00008000 */
+#define EXTI_EMR1_EM15             EXTI_EMR1_EM15_Msk                          /*!< Event Mask on line 15 */
+#define EXTI_EMR1_EM16_Pos         (16U)
+#define EXTI_EMR1_EM16_Msk         (0x1UL << EXTI_EMR1_EM16_Pos)               /*!< 0x00010000 */
+#define EXTI_EMR1_EM16             EXTI_EMR1_EM16_Msk                          /*!< Event Mask on line 16 */
+#define EXTI_EMR1_EM17_Pos         (17U)
+#define EXTI_EMR1_EM17_Msk         (0x1UL << EXTI_EMR1_EM17_Pos)               /*!< 0x00020000 */
+#define EXTI_EMR1_EM17             EXTI_EMR1_EM17_Msk                          /*!< Event Mask on line 17 */
+#define EXTI_EMR1_EM18_Pos         (18U)
+#define EXTI_EMR1_EM18_Msk         (0x1UL << EXTI_EMR1_EM18_Pos)               /*!< 0x00040000 */
+#define EXTI_EMR1_EM18             EXTI_EMR1_EM18_Msk                          /*!< Event Mask on line 18 */
+#define EXTI_EMR1_EM20_Pos         (20U)
+#define EXTI_EMR1_EM20_Msk         (0x1UL << EXTI_EMR1_EM20_Pos)               /*!< 0x00100000 */
+#define EXTI_EMR1_EM20             EXTI_EMR1_EM20_Msk                          /*!< Event Mask on line 20 */
+#define EXTI_EMR1_EM21_Pos         (21U)
+#define EXTI_EMR1_EM21_Msk         (0x1UL << EXTI_EMR1_EM21_Pos)               /*!< 0x00200000 */
+#define EXTI_EMR1_EM21             EXTI_EMR1_EM21_Msk                          /*!< Event Mask on line 21 */
+#define EXTI_EMR1_EM22_Pos         (22U)
+#define EXTI_EMR1_EM22_Msk         (0x1UL << EXTI_EMR1_EM22_Pos)               /*!< 0x00400000 */
+#define EXTI_EMR1_EM22             EXTI_EMR1_EM22_Msk                          /*!< Event Mask on line 22 */
+#define EXTI_EMR1_EM23_Pos         (23U)
+#define EXTI_EMR1_EM23_Msk         (0x1UL << EXTI_EMR1_EM23_Pos)               /*!< 0x00800000 */
+#define EXTI_EMR1_EM23             EXTI_EMR1_EM23_Msk                          /*!< Event Mask on line 23 */
+#define EXTI_EMR1_EM24_Pos         (24U)
+#define EXTI_EMR1_EM24_Msk         (0x1UL << EXTI_EMR1_EM24_Pos)               /*!< 0x01000000 */
+#define EXTI_EMR1_EM24             EXTI_EMR1_EM24_Msk                          /*!< Event Mask on line 24 */
+#define EXTI_EMR1_EM25_Pos         (25U)
+#define EXTI_EMR1_EM25_Msk         (0x1UL << EXTI_EMR1_EM25_Pos)               /*!< 0x02000000 */
+#define EXTI_EMR1_EM25             EXTI_EMR1_EM25_Msk                          /*!< Event Mask on line 25 */
+#define EXTI_EMR1_EM26_Pos         (26U)
+#define EXTI_EMR1_EM26_Msk         (0x1UL << EXTI_EMR1_EM26_Pos)               /*!< 0x04000000 */
+#define EXTI_EMR1_EM26             EXTI_EMR1_EM26_Msk                          /*!< Event Mask on line 26 */
+#define EXTI_EMR1_EM27_Pos         (27U)
+#define EXTI_EMR1_EM27_Msk         (0x1UL << EXTI_EMR1_EM27_Pos)               /*!< 0x08000000 */
+#define EXTI_EMR1_EM27             EXTI_EMR1_EM27_Msk                          /*!< Event Mask on line 27 */
+#define EXTI_EMR1_EM28_Pos         (28U)
+#define EXTI_EMR1_EM28_Msk         (0x1UL << EXTI_EMR1_EM28_Pos)               /*!< 0x10000000 */
+#define EXTI_EMR1_EM28             EXTI_EMR1_EM28_Msk                          /*!< Event Mask on line 28 */
+#define EXTI_EMR1_EM29_Pos         (29U)
+#define EXTI_EMR1_EM29_Msk         (0x1UL << EXTI_EMR1_EM29_Pos)               /*!< 0x20000000 */
+#define EXTI_EMR1_EM29             EXTI_EMR1_EM29_Msk                          /*!< Event Mask on line 29 */
+#define EXTI_EMR1_EM30_Pos         (30U)
+#define EXTI_EMR1_EM30_Msk         (0x1UL << EXTI_EMR1_EM30_Pos)               /*!< 0x40000000 */
+#define EXTI_EMR1_EM30             EXTI_EMR1_EM30_Msk                          /*!< Event Mask on line 30 */
+#define EXTI_EMR1_EM31_Pos         (31U)
+#define EXTI_EMR1_EM31_Msk         (0x1UL << EXTI_EMR1_EM31_Pos)               /*!< 0x80000000 */
+#define EXTI_EMR1_EM31             EXTI_EMR1_EM31_Msk                          /*!< Event Mask on line 31 */
+
+/*******************  Bit definition for EXTI_PR1 register  ********************/
+#define EXTI_PR1_PR_Pos            (0U)
+#define EXTI_PR1_PR_Msk            (0x3FFFFFUL << EXTI_PR1_PR_Pos)             /*!< 0x003FFFFF */
+#define EXTI_PR1_PR                EXTI_PR1_PR_Msk                             /*!< Pending bit */
+#define EXTI_PR1_PR0_Pos           (0U)
+#define EXTI_PR1_PR0_Msk           (0x1UL << EXTI_PR1_PR0_Pos)                 /*!< 0x00000001 */
+#define EXTI_PR1_PR0               EXTI_PR1_PR0_Msk                            /*!< Pending bit for line 0 */
+#define EXTI_PR1_PR1_Pos           (1U)
+#define EXTI_PR1_PR1_Msk           (0x1UL << EXTI_PR1_PR1_Pos)                 /*!< 0x00000002 */
+#define EXTI_PR1_PR1               EXTI_PR1_PR1_Msk                            /*!< Pending bit for line 1 */
+#define EXTI_PR1_PR2_Pos           (2U)
+#define EXTI_PR1_PR2_Msk           (0x1UL << EXTI_PR1_PR2_Pos)                 /*!< 0x00000004 */
+#define EXTI_PR1_PR2               EXTI_PR1_PR2_Msk                            /*!< Pending bit for line 2 */
+#define EXTI_PR1_PR3_Pos           (3U)
+#define EXTI_PR1_PR3_Msk           (0x1UL << EXTI_PR1_PR3_Pos)                 /*!< 0x00000008 */
+#define EXTI_PR1_PR3               EXTI_PR1_PR3_Msk                            /*!< Pending bit for line 3 */
+#define EXTI_PR1_PR4_Pos           (4U)
+#define EXTI_PR1_PR4_Msk           (0x1UL << EXTI_PR1_PR4_Pos)                 /*!< 0x00000010 */
+#define EXTI_PR1_PR4               EXTI_PR1_PR4_Msk                            /*!< Pending bit for line 4 */
+#define EXTI_PR1_PR5_Pos           (5U)
+#define EXTI_PR1_PR5_Msk           (0x1UL << EXTI_PR1_PR5_Pos)                 /*!< 0x00000020 */
+#define EXTI_PR1_PR5               EXTI_PR1_PR5_Msk                            /*!< Pending bit for line 5 */
+#define EXTI_PR1_PR6_Pos           (6U)
+#define EXTI_PR1_PR6_Msk           (0x1UL << EXTI_PR1_PR6_Pos)                 /*!< 0x00000040 */
+#define EXTI_PR1_PR6               EXTI_PR1_PR6_Msk                            /*!< Pending bit for line 6 */
+#define EXTI_PR1_PR7_Pos           (7U)
+#define EXTI_PR1_PR7_Msk           (0x1UL << EXTI_PR1_PR7_Pos)                 /*!< 0x00000080 */
+#define EXTI_PR1_PR7               EXTI_PR1_PR7_Msk                            /*!< Pending bit for line 7 */
+#define EXTI_PR1_PR8_Pos           (8U)
+#define EXTI_PR1_PR8_Msk           (0x1UL << EXTI_PR1_PR8_Pos)                 /*!< 0x00000100 */
+#define EXTI_PR1_PR8               EXTI_PR1_PR8_Msk                            /*!< Pending bit for line 8 */
+#define EXTI_PR1_PR9_Pos           (9U)
+#define EXTI_PR1_PR9_Msk           (0x1UL << EXTI_PR1_PR9_Pos)                 /*!< 0x00000200 */
+#define EXTI_PR1_PR9               EXTI_PR1_PR9_Msk                            /*!< Pending bit for line 9 */
+#define EXTI_PR1_PR10_Pos          (10U)
+#define EXTI_PR1_PR10_Msk          (0x1UL << EXTI_PR1_PR10_Pos)                /*!< 0x00000400 */
+#define EXTI_PR1_PR10              EXTI_PR1_PR10_Msk                           /*!< Pending bit for line 10 */
+#define EXTI_PR1_PR11_Pos          (11U)
+#define EXTI_PR1_PR11_Msk          (0x1UL << EXTI_PR1_PR11_Pos)                /*!< 0x00000800 */
+#define EXTI_PR1_PR11              EXTI_PR1_PR11_Msk                           /*!< Pending bit for line 11 */
+#define EXTI_PR1_PR12_Pos          (12U)
+#define EXTI_PR1_PR12_Msk          (0x1UL << EXTI_PR1_PR12_Pos)                /*!< 0x00001000 */
+#define EXTI_PR1_PR12              EXTI_PR1_PR12_Msk                           /*!< Pending bit for line 12 */
+#define EXTI_PR1_PR13_Pos          (13U)
+#define EXTI_PR1_PR13_Msk          (0x1UL << EXTI_PR1_PR13_Pos)                /*!< 0x00002000 */
+#define EXTI_PR1_PR13              EXTI_PR1_PR13_Msk                           /*!< Pending bit for line 13 */
+#define EXTI_PR1_PR14_Pos          (14U)
+#define EXTI_PR1_PR14_Msk          (0x1UL << EXTI_PR1_PR14_Pos)                /*!< 0x00004000 */
+#define EXTI_PR1_PR14              EXTI_PR1_PR14_Msk                           /*!< Pending bit for line 14 */
+#define EXTI_PR1_PR15_Pos          (15U)
+#define EXTI_PR1_PR15_Msk          (0x1UL << EXTI_PR1_PR15_Pos)                /*!< 0x00008000 */
+#define EXTI_PR1_PR15              EXTI_PR1_PR15_Msk                           /*!< Pending bit for line 15 */
+#define EXTI_PR1_PR16_Pos          (16U)
+#define EXTI_PR1_PR16_Msk          (0x1UL << EXTI_PR1_PR16_Pos)                /*!< 0x00010000 */
+#define EXTI_PR1_PR16              EXTI_PR1_PR16_Msk                           /*!< Pending bit for line 16 */
+#define EXTI_PR1_PR17_Pos          (17U)
+#define EXTI_PR1_PR17_Msk          (0x1UL << EXTI_PR1_PR17_Pos)                /*!< 0x00020000 */
+#define EXTI_PR1_PR17              EXTI_PR1_PR17_Msk                           /*!< Pending bit for line 17 */
+#define EXTI_PR1_PR18_Pos          (18U)
+#define EXTI_PR1_PR18_Msk          (0x1UL << EXTI_PR1_PR18_Pos)                /*!< 0x00040000 */
+#define EXTI_PR1_PR18              EXTI_PR1_PR18_Msk                           /*!< Pending bit for line 18 */
+#define EXTI_PR1_PR19_Pos          (19U)
+#define EXTI_PR1_PR19_Msk          (0x1UL << EXTI_PR1_PR19_Pos)                /*!< 0x00080000 */
+#define EXTI_PR1_PR19              EXTI_PR1_PR19_Msk                           /*!< Pending bit for line 19 */
+#define EXTI_PR1_PR20_Pos          (20U)
+#define EXTI_PR1_PR20_Msk          (0x1UL << EXTI_PR1_PR20_Pos)                /*!< 0x00100000 */
+#define EXTI_PR1_PR20              EXTI_PR1_PR20_Msk                           /*!< Pending bit for line 20 */
+#define EXTI_PR1_PR21_Pos          (21U)
+#define EXTI_PR1_PR21_Msk          (0x1UL << EXTI_PR1_PR21_Pos)                /*!< 0x00200000 */
+#define EXTI_PR1_PR21              EXTI_PR1_PR21_Msk                           /*!< Pending bit for line 21 */
+
+/*******************  Bit definition for EXTI_IMR2 register  *******************/
+#define EXTI_IMR2_IM_Pos           (0U)
+#define EXTI_IMR2_IM_Msk           (0xFFFFDFFFUL << EXTI_IMR2_IM_Pos)          /*!< 0xFFFFDFFF */
+#define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            /*!< Interrupt Mask */
+#define EXTI_IMR2_IM32_Pos         (0U)
+#define EXTI_IMR2_IM32_Msk         (0x1UL << EXTI_IMR2_IM32_Pos)               /*!< 0x00000001 */
+#define EXTI_IMR2_IM32             EXTI_IMR2_IM32_Msk                          /*!< Interrupt Mask on line 32 */
+#define EXTI_IMR2_IM33_Pos         (1U)
+#define EXTI_IMR2_IM33_Msk         (0x1UL << EXTI_IMR2_IM33_Pos)               /*!< 0x00000002 */
+#define EXTI_IMR2_IM33             EXTI_IMR2_IM33_Msk                          /*!< Interrupt Mask on line 33 */
+#define EXTI_IMR2_IM34_Pos         (2U)
+#define EXTI_IMR2_IM34_Msk         (0x1UL << EXTI_IMR2_IM34_Pos)               /*!< 0x00000004 */
+#define EXTI_IMR2_IM34             EXTI_IMR2_IM34_Msk                          /*!< Interrupt Mask on line 34 */
+#define EXTI_IMR2_IM35_Pos         (3U)
+#define EXTI_IMR2_IM35_Msk         (0x1UL << EXTI_IMR2_IM35_Pos)               /*!< 0x00000008 */
+#define EXTI_IMR2_IM35             EXTI_IMR2_IM35_Msk                          /*!< Interrupt Mask on line 35 */
+#define EXTI_IMR2_IM36_Pos         (4U)
+#define EXTI_IMR2_IM36_Msk         (0x1UL << EXTI_IMR2_IM36_Pos)               /*!< 0x00000010 */
+#define EXTI_IMR2_IM36             EXTI_IMR2_IM36_Msk                          /*!< Interrupt Mask on line 36 */
+#define EXTI_IMR2_IM37_Pos         (5U)
+#define EXTI_IMR2_IM37_Msk         (0x1UL << EXTI_IMR2_IM37_Pos)               /*!< 0x00000020 */
+#define EXTI_IMR2_IM37             EXTI_IMR2_IM37_Msk                          /*!< Interrupt Mask on line 37 */
+#define EXTI_IMR2_IM38_Pos         (6U)
+#define EXTI_IMR2_IM38_Msk         (0x1UL << EXTI_IMR2_IM38_Pos)               /*!< 0x00000040 */
+#define EXTI_IMR2_IM38             EXTI_IMR2_IM38_Msk                          /*!< Interrupt Mask on line 38 */
+#define EXTI_IMR2_IM39_Pos         (7U)
+#define EXTI_IMR2_IM39_Msk         (0x1UL << EXTI_IMR2_IM39_Pos)               /*!< 0x00000080 */
+#define EXTI_IMR2_IM39             EXTI_IMR2_IM39_Msk                          /*!< Interrupt Mask on line 39 */
+#define EXTI_IMR2_IM40_Pos         (8U)
+#define EXTI_IMR2_IM40_Msk         (0x1UL << EXTI_IMR2_IM40_Pos)               /*!< 0x00000100 */
+#define EXTI_IMR2_IM40             EXTI_IMR2_IM40_Msk                          /*!< Interrupt Mask on line 40 */
+#define EXTI_IMR2_IM41_Pos         (9U)
+#define EXTI_IMR2_IM41_Msk         (0x1UL << EXTI_IMR2_IM41_Pos)               /*!< 0x00000200 */
+#define EXTI_IMR2_IM41             EXTI_IMR2_IM41_Msk                          /*!< Interrupt Mask on line 41 */
+#define EXTI_IMR2_IM42_Pos         (10U)
+#define EXTI_IMR2_IM42_Msk         (0x1UL << EXTI_IMR2_IM42_Pos)               /*!< 0x00000400 */
+#define EXTI_IMR2_IM42             EXTI_IMR2_IM42_Msk                          /*!< Interrupt Mask on line 42 */
+#define EXTI_IMR2_IM43_Pos         (11U)
+#define EXTI_IMR2_IM43_Msk         (0x1UL << EXTI_IMR2_IM43_Pos)               /*!< 0x00000800 */
+#define EXTI_IMR2_IM43             EXTI_IMR2_IM43_Msk                          /*!< Interrupt Mask on line 43 */
+#define EXTI_IMR2_IM44_Pos         (12U)
+#define EXTI_IMR2_IM44_Msk         (0x1UL << EXTI_IMR2_IM44_Pos)               /*!< 0x00001000 */
+#define EXTI_IMR2_IM44             EXTI_IMR2_IM44_Msk                          /*!< Interrupt Mask on line 44 */
+#define EXTI_IMR2_IM46_Pos         (14U)
+#define EXTI_IMR2_IM46_Msk         (0x1UL << EXTI_IMR2_IM46_Pos)               /*!< 0x00004000 */
+#define EXTI_IMR2_IM46             EXTI_IMR2_IM46_Msk                          /*!< Interrupt Mask on line 46 */
+#define EXTI_IMR2_IM47_Pos         (15U)
+#define EXTI_IMR2_IM47_Msk         (0x1UL << EXTI_IMR2_IM47_Pos)               /*!< 0x00008000 */
+#define EXTI_IMR2_IM47             EXTI_IMR2_IM47_Msk                          /*!< Interrupt Mask on line 47 */
+#define EXTI_IMR2_IM48_Pos         (16U)
+#define EXTI_IMR2_IM48_Msk         (0x1UL << EXTI_IMR2_IM48_Pos)               /*!< 0x00010000 */
+#define EXTI_IMR2_IM48             EXTI_IMR2_IM48_Msk                          /*!< Interrupt Mask on line 48 */
+#define EXTI_IMR2_IM49_Pos         (17U)
+#define EXTI_IMR2_IM49_Msk         (0x1UL << EXTI_IMR2_IM49_Pos)               /*!< 0x00020000 */
+#define EXTI_IMR2_IM49             EXTI_IMR2_IM49_Msk                          /*!< Interrupt Mask on line 49 */
+#define EXTI_IMR2_IM50_Pos         (18U)
+#define EXTI_IMR2_IM50_Msk         (0x1UL << EXTI_IMR2_IM50_Pos)               /*!< 0x00040000 */
+#define EXTI_IMR2_IM50             EXTI_IMR2_IM50_Msk                          /*!< Interrupt Mask on line 50 */
+#define EXTI_IMR2_IM51_Pos         (19U)
+#define EXTI_IMR2_IM51_Msk         (0x1UL << EXTI_IMR2_IM51_Pos)               /*!< 0x00080000 */
+#define EXTI_IMR2_IM51             EXTI_IMR2_IM51_Msk                          /*!< Interrupt Mask on line 51 */
+#define EXTI_IMR2_IM52_Pos         (20U)
+#define EXTI_IMR2_IM52_Msk         (0x1UL << EXTI_IMR2_IM52_Pos)               /*!< 0x00100000 */
+#define EXTI_IMR2_IM52             EXTI_IMR2_IM52_Msk                          /*!< Interrupt Mask on line 52 */
+#define EXTI_IMR2_IM53_Pos         (21U)
+#define EXTI_IMR2_IM53_Msk         (0x1UL << EXTI_IMR2_IM53_Pos)               /*!< 0x00200000 */
+#define EXTI_IMR2_IM53             EXTI_IMR2_IM53_Msk                          /*!< Interrupt Mask on line 53 */
+#define EXTI_IMR2_IM54_Pos         (22U)
+#define EXTI_IMR2_IM54_Msk         (0x1UL << EXTI_IMR2_IM54_Pos)               /*!< 0x00400000 */
+#define EXTI_IMR2_IM54             EXTI_IMR2_IM54_Msk                          /*!< Interrupt Mask on line 54 */
+#define EXTI_IMR2_IM55_Pos         (23U)
+#define EXTI_IMR2_IM55_Msk         (0x1UL << EXTI_IMR2_IM55_Pos)               /*!< 0x00800000 */
+#define EXTI_IMR2_IM55             EXTI_IMR2_IM55_Msk                          /*!< Interrupt Mask on line 55 */
+#define EXTI_IMR2_IM56_Pos         (24U)
+#define EXTI_IMR2_IM56_Msk         (0x1UL << EXTI_IMR2_IM56_Pos)               /*!< 0x01000000 */
+#define EXTI_IMR2_IM56             EXTI_IMR2_IM56_Msk                          /*!< Interrupt Mask on line 56 */
+#define EXTI_IMR2_IM57_Pos         (25U)
+#define EXTI_IMR2_IM57_Msk         (0x1UL << EXTI_IMR2_IM57_Pos)               /*!< 0x02000000 */
+#define EXTI_IMR2_IM57             EXTI_IMR2_IM57_Msk                          /*!< Interrupt Mask on line 57 */
+#define EXTI_IMR2_IM58_Pos         (26U)
+#define EXTI_IMR2_IM58_Msk         (0x1UL << EXTI_IMR2_IM58_Pos)               /*!< 0x04000000 */
+#define EXTI_IMR2_IM58             EXTI_IMR2_IM58_Msk                          /*!< Interrupt Mask on line 58 */
+#define EXTI_IMR2_IM59_Pos         (27U)
+#define EXTI_IMR2_IM59_Msk         (0x1UL << EXTI_IMR2_IM59_Pos)               /*!< 0x08000000 */
+#define EXTI_IMR2_IM59             EXTI_IMR2_IM59_Msk                          /*!< Interrupt Mask on line 59 */
+#define EXTI_IMR2_IM60_Pos         (28U)
+#define EXTI_IMR2_IM60_Msk         (0x1UL << EXTI_IMR2_IM60_Pos)               /*!< 0x10000000 */
+#define EXTI_IMR2_IM60             EXTI_IMR2_IM60_Msk                          /*!< Interrupt Mask on line 60 */
+#define EXTI_IMR2_IM61_Pos         (29U)
+#define EXTI_IMR2_IM61_Msk         (0x1UL << EXTI_IMR2_IM61_Pos)               /*!< 0x20000000 */
+#define EXTI_IMR2_IM61             EXTI_IMR2_IM61_Msk                          /*!< Interrupt Mask on line 61 */
+#define EXTI_IMR2_IM62_Pos         (30U)
+#define EXTI_IMR2_IM62_Msk         (0x1UL << EXTI_IMR2_IM62_Pos)               /*!< 0x40000000 */
+#define EXTI_IMR2_IM62             EXTI_IMR2_IM62_Msk                          /*!< Interrupt Mask on line 62 */
+#define EXTI_IMR2_IM63_Pos         (31U)
+#define EXTI_IMR2_IM63_Msk         (0x1UL << EXTI_IMR2_IM63_Pos)               /*!< 0x80000000 */
+#define EXTI_IMR2_IM63             EXTI_IMR2_IM63_Msk                          /*!< Interrupt Mask on line 63 */
+
+/*******************  Bit definition for EXTI_EMR2 register  *******************/
+#define EXTI_EMR2_EM_Pos           (0U)
+#define EXTI_EMR2_EM_Msk           (0xFFFFDFFFUL << EXTI_EMR2_EM_Pos)          /*!< 0xFFFFDFFF */
+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            /*!< Event Mask */
+#define EXTI_EMR2_EM32_Pos         (0U)
+#define EXTI_EMR2_EM32_Msk         (0x1UL << EXTI_EMR2_EM32_Pos)               /*!< 0x00000001 */
+#define EXTI_EMR2_EM32             EXTI_EMR2_EM32_Msk                          /*!< Event Mask on line 32*/
+#define EXTI_EMR2_EM33_Pos         (1U)
+#define EXTI_EMR2_EM33_Msk         (0x1UL << EXTI_EMR2_EM33_Pos)               /*!< 0x00000002 */
+#define EXTI_EMR2_EM33             EXTI_EMR2_EM33_Msk                          /*!< Event Mask on line 33*/
+#define EXTI_EMR2_EM34_Pos         (2U)
+#define EXTI_EMR2_EM34_Msk         (0x1UL << EXTI_EMR2_EM34_Pos)               /*!< 0x00000004 */
+#define EXTI_EMR2_EM34             EXTI_EMR2_EM34_Msk                          /*!< Event Mask on line 34*/
+#define EXTI_EMR2_EM35_Pos         (3U)
+#define EXTI_EMR2_EM35_Msk         (0x1UL << EXTI_EMR2_EM35_Pos)               /*!< 0x00000008 */
+#define EXTI_EMR2_EM35             EXTI_EMR2_EM35_Msk                          /*!< Event Mask on line 35*/
+#define EXTI_EMR2_EM36_Pos         (4U)
+#define EXTI_EMR2_EM36_Msk         (0x1UL << EXTI_EMR2_EM36_Pos)               /*!< 0x00000010 */
+#define EXTI_EMR2_EM36             EXTI_EMR2_EM36_Msk                          /*!< Event Mask on line 36*/
+#define EXTI_EMR2_EM37_Pos         (5U)
+#define EXTI_EMR2_EM37_Msk         (0x1UL << EXTI_EMR2_EM37_Pos)               /*!< 0x00000020 */
+#define EXTI_EMR2_EM37             EXTI_EMR2_EM37_Msk                          /*!< Event Mask on line 37*/
+#define EXTI_EMR2_EM38_Pos         (6U)
+#define EXTI_EMR2_EM38_Msk         (0x1UL << EXTI_EMR2_EM38_Pos)               /*!< 0x00000040 */
+#define EXTI_EMR2_EM38             EXTI_EMR2_EM38_Msk                          /*!< Event Mask on line 38*/
+#define EXTI_EMR2_EM39_Pos         (7U)
+#define EXTI_EMR2_EM39_Msk         (0x1UL << EXTI_EMR2_EM39_Pos)               /*!< 0x00000080 */
+#define EXTI_EMR2_EM39             EXTI_EMR2_EM39_Msk                          /*!< Event Mask on line 39*/
+#define EXTI_EMR2_EM40_Pos         (8U)
+#define EXTI_EMR2_EM40_Msk         (0x1UL << EXTI_EMR2_EM40_Pos)               /*!< 0x00000100 */
+#define EXTI_EMR2_EM40             EXTI_EMR2_EM40_Msk                          /*!< Event Mask on line 40*/
+#define EXTI_EMR2_EM41_Pos         (9U)
+#define EXTI_EMR2_EM41_Msk         (0x1UL << EXTI_EMR2_EM41_Pos)               /*!< 0x00000200 */
+#define EXTI_EMR2_EM41             EXTI_EMR2_EM41_Msk                          /*!< Event Mask on line 41*/
+#define EXTI_EMR2_EM42_Pos         (10U)
+#define EXTI_EMR2_EM42_Msk         (0x1UL << EXTI_EMR2_EM42_Pos)               /*!< 0x00000400 */
+#define EXTI_EMR2_EM42             EXTI_EMR2_EM42_Msk                          /*!< Event Mask on line 42 */
+#define EXTI_EMR2_EM43_Pos         (11U)
+#define EXTI_EMR2_EM43_Msk         (0x1UL << EXTI_EMR2_EM43_Pos)               /*!< 0x00000800 */
+#define EXTI_EMR2_EM43             EXTI_EMR2_EM43_Msk                          /*!< Event Mask on line 43 */
+#define EXTI_EMR2_EM44_Pos         (12U)
+#define EXTI_EMR2_EM44_Msk         (0x1UL << EXTI_EMR2_EM44_Pos)               /*!< 0x00001000 */
+#define EXTI_EMR2_EM44             EXTI_EMR2_EM44_Msk                          /*!< Event Mask on line 44 */
+#define EXTI_EMR2_EM46_Pos         (14U)
+#define EXTI_EMR2_EM46_Msk         (0x1UL << EXTI_EMR2_EM46_Pos)               /*!< 0x00004000 */
+#define EXTI_EMR2_EM46             EXTI_EMR2_EM46_Msk                          /*!< Event Mask on line 46 */
+#define EXTI_EMR2_EM47_Pos         (15U)
+#define EXTI_EMR2_EM47_Msk         (0x1UL << EXTI_EMR2_EM47_Pos)               /*!< 0x00008000 */
+#define EXTI_EMR2_EM47             EXTI_EMR2_EM47_Msk                          /*!< Event Mask on line 47 */
+#define EXTI_EMR2_EM48_Pos         (16U)
+#define EXTI_EMR2_EM48_Msk         (0x1UL << EXTI_EMR2_EM48_Pos)               /*!< 0x00010000 */
+#define EXTI_EMR2_EM48             EXTI_EMR2_EM48_Msk                          /*!< Event Mask on line 48 */
+#define EXTI_EMR2_EM49_Pos         (17U)
+#define EXTI_EMR2_EM49_Msk         (0x1UL << EXTI_EMR2_EM49_Pos)               /*!< 0x00020000 */
+#define EXTI_EMR2_EM49             EXTI_EMR2_EM49_Msk                          /*!< Event Mask on line 49 */
+#define EXTI_EMR2_EM50_Pos         (18U)
+#define EXTI_EMR2_EM50_Msk         (0x1UL << EXTI_EMR2_EM50_Pos)               /*!< 0x00040000 */
+#define EXTI_EMR2_EM50             EXTI_EMR2_EM50_Msk                          /*!< Event Mask on line 50 */
+#define EXTI_EMR2_EM51_Pos         (19U)
+#define EXTI_EMR2_EM51_Msk         (0x1UL << EXTI_EMR2_EM51_Pos)               /*!< 0x00080000 */
+#define EXTI_EMR2_EM51             EXTI_EMR2_EM51_Msk                          /*!< Event Mask on line 51 */
+#define EXTI_EMR2_EM52_Pos         (20U)
+#define EXTI_EMR2_EM52_Msk         (0x1UL << EXTI_EMR2_EM52_Pos)               /*!< 0x00100000 */
+#define EXTI_EMR2_EM52             EXTI_EMR2_EM52_Msk                          /*!< Event Mask on line 52 */
+#define EXTI_EMR2_EM53_Pos         (21U)
+#define EXTI_EMR2_EM53_Msk         (0x1UL << EXTI_EMR2_EM53_Pos)               /*!< 0x00200000 */
+#define EXTI_EMR2_EM53             EXTI_EMR2_EM53_Msk                          /*!< Event Mask on line 53 */
+#define EXTI_EMR2_EM54_Pos         (22U)
+#define EXTI_EMR2_EM54_Msk         (0x1UL << EXTI_EMR2_EM54_Pos)               /*!< 0x00400000 */
+#define EXTI_EMR2_EM54             EXTI_EMR2_EM54_Msk                          /*!< Event Mask on line 54 */
+#define EXTI_EMR2_EM55_Pos         (23U)
+#define EXTI_EMR2_EM55_Msk         (0x1UL << EXTI_EMR2_EM55_Pos)               /*!< 0x00800000 */
+#define EXTI_EMR2_EM55             EXTI_EMR2_EM55_Msk                          /*!< Event Mask on line 55 */
+#define EXTI_EMR2_EM56_Pos         (24U)
+#define EXTI_EMR2_EM56_Msk         (0x1UL << EXTI_EMR2_EM56_Pos)               /*!< 0x01000000 */
+#define EXTI_EMR2_EM56             EXTI_EMR2_EM56_Msk                          /*!< Event Mask on line 56 */
+#define EXTI_EMR2_EM57_Pos         (25U)
+#define EXTI_EMR2_EM57_Msk         (0x1UL << EXTI_EMR2_EM57_Pos)               /*!< 0x02000000 */
+#define EXTI_EMR2_EM57             EXTI_EMR2_EM57_Msk                          /*!< Event Mask on line 57 */
+#define EXTI_EMR2_EM58_Pos         (26U)
+#define EXTI_EMR2_EM58_Msk         (0x1UL << EXTI_EMR2_EM58_Pos)               /*!< 0x04000000 */
+#define EXTI_EMR2_EM58             EXTI_EMR2_EM58_Msk                          /*!< Event Mask on line 58 */
+#define EXTI_EMR2_EM59_Pos         (27U)
+#define EXTI_EMR2_EM59_Msk         (0x1UL << EXTI_EMR2_EM59_Pos)               /*!< 0x08000000 */
+#define EXTI_EMR2_EM59             EXTI_EMR2_EM59_Msk                          /*!< Event Mask on line 59 */
+#define EXTI_EMR2_EM60_Pos         (28U)
+#define EXTI_EMR2_EM60_Msk         (0x1UL << EXTI_EMR2_EM60_Pos)               /*!< 0x10000000 */
+#define EXTI_EMR2_EM60             EXTI_EMR2_EM60_Msk                          /*!< Event Mask on line 60 */
+#define EXTI_EMR2_EM61_Pos         (29U)
+#define EXTI_EMR2_EM61_Msk         (0x1UL << EXTI_EMR2_EM61_Pos)               /*!< 0x20000000 */
+#define EXTI_EMR2_EM61             EXTI_EMR2_EM61_Msk                          /*!< Event Mask on line 61 */
+#define EXTI_EMR2_EM62_Pos         (30U)
+#define EXTI_EMR2_EM62_Msk         (0x1UL << EXTI_EMR2_EM62_Pos)               /*!< 0x40000000 */
+#define EXTI_EMR2_EM62             EXTI_EMR2_EM62_Msk                          /*!< Event Mask on line 62 */
+#define EXTI_EMR2_EM63_Pos         (31U)
+#define EXTI_EMR2_EM63_Msk         (0x1UL << EXTI_EMR2_EM63_Pos)               /*!< 0x80000000 */
+#define EXTI_EMR2_EM63             EXTI_EMR2_EM63_Msk                          /*!< Event Mask on line 63 */
+
+/*******************  Bit definition for EXTI_PR2 register  ********************/
+#define EXTI_PR2_PR_Pos            (17U)
+#define EXTI_PR2_PR_Msk            (0x5UL << EXTI_PR2_PR_Pos)                  /*!< 0x000A0000 */
+#define EXTI_PR2_PR                EXTI_PR2_PR_Msk                             /*!< Pending bit */
+#define EXTI_PR2_PR49_Pos          (17U)
+#define EXTI_PR2_PR49_Msk          (0x1UL << EXTI_PR2_PR49_Pos)                /*!< 0x00020000 */
+#define EXTI_PR2_PR49              EXTI_PR2_PR49_Msk                           /*!< Pending bit for line 49 */
+#define EXTI_PR2_PR51_Pos          (19U)
+#define EXTI_PR2_PR51_Msk          (0x1UL << EXTI_PR2_PR51_Pos)                /*!< 0x00080000 */
+#define EXTI_PR2_PR51              EXTI_PR2_PR51_Msk                           /*!< Pending bit for line 51 */
+
+/*******************  Bit definition for EXTI_IMR3 register  *******************/
+#define EXTI_IMR3_IM_Pos           (0U)
+#define EXTI_IMR3_IM_Msk           (0x00F5FFFFUL << EXTI_IMR3_IM_Pos)          /*!< 0x00F5FFFF */
+#define EXTI_IMR3_IM               EXTI_IMR3_IM_Msk                            /*!< Interrupt Mask */
+#define EXTI_IMR3_IM64_Pos         (0U)
+#define EXTI_IMR3_IM64_Msk         (0x1UL << EXTI_IMR3_IM64_Pos)               /*!< 0x00000001 */
+#define EXTI_IMR3_IM64             EXTI_IMR3_IM64_Msk                          /*!< Interrupt Mask on line 64 */
+#define EXTI_IMR3_IM65_Pos         (1U)
+#define EXTI_IMR3_IM65_Msk         (0x1UL << EXTI_IMR3_IM65_Pos)               /*!< 0x00000002 */
+#define EXTI_IMR3_IM65             EXTI_IMR3_IM65_Msk                          /*!< Interrupt Mask on line 65 */
+#define EXTI_IMR3_IM66_Pos         (2U)
+#define EXTI_IMR3_IM66_Msk         (0x1UL << EXTI_IMR3_IM66_Pos)               /*!< 0x00000004 */
+#define EXTI_IMR3_IM66             EXTI_IMR3_IM66_Msk                          /*!< Interrupt Mask on line 66 */
+#define EXTI_IMR3_IM67_Pos         (3U)
+#define EXTI_IMR3_IM67_Msk         (0x1UL << EXTI_IMR3_IM67_Pos)               /*!< 0x00000008 */
+#define EXTI_IMR3_IM67             EXTI_IMR3_IM67_Msk                          /*!< Interrupt Mask on line 67 */
+#define EXTI_IMR3_IM68_Pos         (4U)
+#define EXTI_IMR3_IM68_Msk         (0x1UL << EXTI_IMR3_IM68_Pos)               /*!< 0x00000010 */
+#define EXTI_IMR3_IM68             EXTI_IMR3_IM68_Msk                          /*!< Interrupt Mask on line 68 */
+#define EXTI_IMR3_IM69_Pos         (5U)
+#define EXTI_IMR3_IM69_Msk         (0x1UL << EXTI_IMR3_IM69_Pos)               /*!< 0x00000020 */
+#define EXTI_IMR3_IM69             EXTI_IMR3_IM69_Msk                          /*!< Interrupt Mask on line 69 */
+#define EXTI_IMR3_IM70_Pos         (6U)
+#define EXTI_IMR3_IM70_Msk         (0x1UL << EXTI_IMR3_IM70_Pos)               /*!< 0x00000040 */
+#define EXTI_IMR3_IM70             EXTI_IMR3_IM70_Msk                          /*!< Interrupt Mask on line 70 */
+#define EXTI_IMR3_IM71_Pos         (7U)
+#define EXTI_IMR3_IM71_Msk         (0x1UL << EXTI_IMR3_IM71_Pos)               /*!< 0x00000080 */
+#define EXTI_IMR3_IM71             EXTI_IMR3_IM71_Msk                          /*!< Interrupt Mask on line 71 */
+#define EXTI_IMR3_IM72_Pos         (8U)
+#define EXTI_IMR3_IM72_Msk         (0x1UL << EXTI_IMR3_IM72_Pos)               /*!< 0x00000100 */
+#define EXTI_IMR3_IM72             EXTI_IMR3_IM72_Msk                          /*!< Interrupt Mask on line 72 */
+#define EXTI_IMR3_IM73_Pos         (9U)
+#define EXTI_IMR3_IM73_Msk         (0x1UL << EXTI_IMR3_IM73_Pos)               /*!< 0x00000200 */
+#define EXTI_IMR3_IM73             EXTI_IMR3_IM73_Msk                          /*!< Interrupt Mask on line 73 */
+#define EXTI_IMR3_IM74_Pos         (10U)
+#define EXTI_IMR3_IM74_Msk         (0x1UL << EXTI_IMR3_IM74_Pos)               /*!< 0x00000400 */
+#define EXTI_IMR3_IM74             EXTI_IMR3_IM74_Msk                          /*!< Interrupt Mask on line 74 */
+#define EXTI_IMR3_IM75_Pos         (11U)
+#define EXTI_IMR3_IM75_Msk         (0x1UL << EXTI_IMR3_IM75_Pos)               /*!< 0x00000800 */
+#define EXTI_IMR3_IM75             EXTI_IMR3_IM75_Msk                          /*!< Interrupt Mask on line 75 */
+#define EXTI_IMR3_IM76_Pos         (12U)
+#define EXTI_IMR3_IM76_Msk         (0x1UL << EXTI_IMR3_IM76_Pos)               /*!< 0x00001000 */
+#define EXTI_IMR3_IM76             EXTI_IMR3_IM76_Msk                          /*!< Interrupt Mask on line 76 */
+#define EXTI_IMR3_IM77_Pos         (13U)
+#define EXTI_IMR3_IM77_Msk         (0x1UL << EXTI_IMR3_IM77_Pos)               /*!< 0x00002000 */
+#define EXTI_IMR3_IM77             EXTI_IMR3_IM77_Msk                          /*!< Interrupt Mask on line 77 */
+#define EXTI_IMR3_IM78_Pos         (14U)
+#define EXTI_IMR3_IM78_Msk         (0x1UL << EXTI_IMR3_IM78_Pos)               /*!< 0x00004000 */
+#define EXTI_IMR3_IM78             EXTI_IMR3_IM78_Msk                          /*!< Interrupt Mask on line 78 */
+#define EXTI_IMR3_IM79_Pos         (15U)
+#define EXTI_IMR3_IM79_Msk         (0x1UL << EXTI_IMR3_IM79_Pos)               /*!< 0x00008000 */
+#define EXTI_IMR3_IM79             EXTI_IMR3_IM79_Msk                          /*!< Interrupt Mask on line 79 */
+#define EXTI_IMR3_IM80_Pos         (16U)
+#define EXTI_IMR3_IM80_Msk         (0x1UL << EXTI_IMR3_IM80_Pos)               /*!< 0x00010000 */
+#define EXTI_IMR3_IM80             EXTI_IMR3_IM80_Msk                          /*!< Interrupt Mask on line 80 */
+#define EXTI_IMR3_IM82_Pos         (18U)
+#define EXTI_IMR3_IM82_Msk         (0x1UL << EXTI_IMR3_IM82_Pos)               /*!< 0x00040000 */
+#define EXTI_IMR3_IM82             EXTI_IMR3_IM82_Msk                          /*!< Interrupt Mask on line 82 */
+#define EXTI_IMR3_IM84_Pos         (20U)
+#define EXTI_IMR3_IM84_Msk         (0x1UL << EXTI_IMR3_IM84_Pos)               /*!< 0x00100000 */
+#define EXTI_IMR3_IM84             EXTI_IMR3_IM84_Msk                          /*!< Interrupt Mask on line 84 */
+#define EXTI_IMR3_IM85_Pos         (21U)
+#define EXTI_IMR3_IM85_Msk         (0x1UL << EXTI_IMR3_IM85_Pos)               /*!< 0x00200000 */
+#define EXTI_IMR3_IM85             EXTI_IMR3_IM85_Msk                          /*!< Interrupt Mask on line 85 */
+#define EXTI_IMR3_IM86_Pos         (22U)
+#define EXTI_IMR3_IM86_Msk         (0x1UL << EXTI_IMR3_IM86_Pos)               /*!< 0x00400000 */
+#define EXTI_IMR3_IM86             EXTI_IMR3_IM86_Msk                          /*!< Interrupt Mask on line 86 */
+#define EXTI_IMR3_IM87_Pos         (23U)
+#define EXTI_IMR3_IM87_Msk         (0x1UL << EXTI_IMR3_IM87_Pos)               /*!< 0x00800000 */
+#define EXTI_IMR3_IM87             EXTI_IMR3_IM87_Msk                          /*!< Interrupt Mask on line 87 */
+
+
+/*******************  Bit definition for EXTI_EMR3 register  *******************/
+#define EXTI_EMR3_EM_Pos           (0U)
+#define EXTI_EMR3_EM_Msk           (0x00F5FFFFUL << EXTI_EMR3_EM_Pos)          /*!< 0x00F5FFFF */
+#define EXTI_EMR3_EM               EXTI_EMR3_EM_Msk                            /*!< Event Mask           */
+#define EXTI_EMR3_EM64_Pos         (0U)
+#define EXTI_EMR3_EM64_Msk         (0x1UL << EXTI_EMR3_EM64_Pos)               /*!< 0x00000001 */
+#define EXTI_EMR3_EM64             EXTI_EMR3_EM64_Msk                          /*!< Event Mask on line 64*/
+#define EXTI_EMR3_EM65_Pos         (1U)
+#define EXTI_EMR3_EM65_Msk         (0x1UL << EXTI_EMR3_EM65_Pos)               /*!< 0x00000002 */
+#define EXTI_EMR3_EM65             EXTI_EMR3_EM65_Msk                          /*!< Event Mask on line 65*/
+#define EXTI_EMR3_EM66_Pos         (2U)
+#define EXTI_EMR3_EM66_Msk         (0x1UL << EXTI_EMR3_EM66_Pos)               /*!< 0x00000004 */
+#define EXTI_EMR3_EM66             EXTI_EMR3_EM66_Msk                          /*!< Event Mask on line 66*/
+#define EXTI_EMR3_EM67_Pos         (3U)
+#define EXTI_EMR3_EM67_Msk         (0x1UL << EXTI_EMR3_EM67_Pos)               /*!< 0x00000008 */
+#define EXTI_EMR3_EM67             EXTI_EMR3_EM67_Msk                          /*!< Event Mask on line 67*/
+#define EXTI_EMR3_EM68_Pos         (4U)
+#define EXTI_EMR3_EM68_Msk         (0x1UL << EXTI_EMR3_EM68_Pos)               /*!< 0x00000010 */
+#define EXTI_EMR3_EM68             EXTI_EMR3_EM68_Msk                          /*!< Event Mask on line 68*/
+#define EXTI_EMR3_EM69_Pos         (5U)
+#define EXTI_EMR3_EM69_Msk         (0x1UL << EXTI_EMR3_EM69_Pos)               /*!< 0x00000020 */
+#define EXTI_EMR3_EM69             EXTI_EMR3_EM69_Msk                          /*!< Event Mask on line 69*/
+#define EXTI_EMR3_EM70_Pos         (6U)
+#define EXTI_EMR3_EM70_Msk         (0x1UL << EXTI_EMR3_EM70_Pos)               /*!< 0x00000040 */
+#define EXTI_EMR3_EM70             EXTI_EMR3_EM70_Msk                          /*!< Event Mask on line 70*/
+#define EXTI_EMR3_EM71_Pos         (7U)
+#define EXTI_EMR3_EM71_Msk         (0x1UL << EXTI_EMR3_EM71_Pos)               /*!< 0x00000080 */
+#define EXTI_EMR3_EM71             EXTI_EMR3_EM71_Msk                          /*!< Event Mask on line 71*/
+#define EXTI_EMR3_EM72_Pos         (8U)
+#define EXTI_EMR3_EM72_Msk         (0x1UL << EXTI_EMR3_EM72_Pos)               /*!< 0x00000100 */
+#define EXTI_EMR3_EM72             EXTI_EMR3_EM72_Msk                          /*!< Event Mask on line 72*/
+#define EXTI_EMR3_EM73_Pos         (9U)
+#define EXTI_EMR3_EM73_Msk         (0x1UL << EXTI_EMR3_EM73_Pos)               /*!< 0x00000200 */
+#define EXTI_EMR3_EM73             EXTI_EMR3_EM73_Msk                          /*!< Event Mask on line 73*/
+#define EXTI_EMR3_EM74_Pos         (10U)
+#define EXTI_EMR3_EM74_Msk         (0x1UL << EXTI_EMR3_EM74_Pos)               /*!< 0x00000400 */
+#define EXTI_EMR3_EM74             EXTI_EMR3_EM74_Msk                          /*!< Event Mask on line 74 */
+#define EXTI_EMR3_EM75_Pos         (11U)
+#define EXTI_EMR3_EM75_Msk         (0x1UL << EXTI_EMR3_EM75_Pos)               /*!< 0x00000800 */
+#define EXTI_EMR3_EM75             EXTI_EMR3_EM75_Msk                          /*!< Event Mask on line 75 */
+#define EXTI_EMR3_EM76_Pos         (12U)
+#define EXTI_EMR3_EM76_Msk         (0x1UL << EXTI_EMR3_EM76_Pos)               /*!< 0x00001000 */
+#define EXTI_EMR3_EM76             EXTI_EMR3_EM76_Msk                          /*!< Event Mask on line 76 */
+#define EXTI_EMR3_EM77_Pos         (13U)
+#define EXTI_EMR3_EM77_Msk         (0x1UL << EXTI_EMR3_EM77_Pos)               /*!< 0x00002000 */
+#define EXTI_EMR3_EM77             EXTI_EMR3_EM77_Msk                          /*!< Event Mask on line 77 */
+#define EXTI_EMR3_EM78_Pos         (14U)
+#define EXTI_EMR3_EM78_Msk         (0x1UL << EXTI_EMR3_EM78_Pos)               /*!< 0x00004000 */
+#define EXTI_EMR3_EM78             EXTI_EMR3_EM78_Msk                          /*!< Event Mask on line 78 */
+#define EXTI_EMR3_EM79_Pos         (15U)
+#define EXTI_EMR3_EM79_Msk         (0x1UL << EXTI_EMR3_EM79_Pos)               /*!< 0x00008000 */
+#define EXTI_EMR3_EM79             EXTI_EMR3_EM79_Msk                          /*!< Event Mask on line 79 */
+#define EXTI_EMR3_EM80_Pos         (16U)
+#define EXTI_EMR3_EM80_Msk         (0x1UL << EXTI_EMR3_EM80_Pos)               /*!< 0x00010000 */
+#define EXTI_EMR3_EM80             EXTI_EMR3_EM80_Msk                          /*!< Event Mask on line 80 */
+#define EXTI_EMR3_EM81_Pos         (17U)
+#define EXTI_EMR3_EM81_Msk         (0x1UL << EXTI_EMR3_EM81_Pos)               /*!< 0x00020000 */
+#define EXTI_EMR3_EM81             EXTI_EMR3_EM81_Msk                          /*!< Event Mask on line 81 */
+#define EXTI_EMR3_EM82_Pos         (18U)
+#define EXTI_EMR3_EM82_Msk         (0x1UL << EXTI_EMR3_EM82_Pos)               /*!< 0x00040000 */
+#define EXTI_EMR3_EM82             EXTI_EMR3_EM82_Msk                          /*!< Event Mask on line 82 */
+#define EXTI_EMR3_EM84_Pos         (20U)
+#define EXTI_EMR3_EM84_Msk         (0x1UL << EXTI_EMR3_EM84_Pos)               /*!< 0x00100000 */
+#define EXTI_EMR3_EM84             EXTI_EMR3_EM84_Msk                          /*!< Event Mask on line 84 */
+#define EXTI_EMR3_EM85_Pos         (21U)
+#define EXTI_EMR3_EM85_Msk         (0x1UL << EXTI_EMR3_EM85_Pos)               /*!< 0x00200000 */
+#define EXTI_EMR3_EM85             EXTI_EMR3_EM85_Msk                          /*!< Event Mask on line 85 */
+#define EXTI_EMR3_EM86_Pos         (22U)
+#define EXTI_EMR3_EM86_Msk         (0x1UL << EXTI_EMR3_EM86_Pos)               /*!< 0x00400000 */
+#define EXTI_EMR3_EM86             EXTI_EMR3_EM86_Msk                          /*!< Event Mask on line 86 */
+#define EXTI_EMR3_EM87_Pos         (23U)
+#define EXTI_EMR3_EM87_Msk         (0x1UL << EXTI_EMR3_EM87_Pos)               /*!< 0x00800000 */
+#define EXTI_EMR3_EM87             EXTI_EMR3_EM87_Msk                          /*!< Event Mask on line 87 */
+
+/*******************  Bit definition for EXTI_PR3 register  ********************/
+#define EXTI_PR3_PR_Pos            (18U)
+#define EXTI_PR3_PR_Msk            (0x1DUL << EXTI_PR3_PR_Pos)                 /*!< 0x00740000 */
+#define EXTI_PR3_PR                EXTI_PR3_PR_Msk                             /*!< Pending bit */
+#define EXTI_PR3_PR82_Pos          (18U)
+#define EXTI_PR3_PR82_Msk          (0x1UL << EXTI_PR3_PR82_Pos)                /*!< 0x00040000 */
+#define EXTI_PR3_PR82              EXTI_PR3_PR82_Msk                           /*!< Pending bit for line 82 */
+#define EXTI_PR3_PR84_Pos          (20U)
+#define EXTI_PR3_PR84_Msk          (0x1UL << EXTI_PR3_PR84_Pos)                /*!< 0x00100000 */
+#define EXTI_PR3_PR84              EXTI_PR3_PR84_Msk                           /*!< Pending bit for line 84 */
+#define EXTI_PR3_PR85_Pos          (21U)
+#define EXTI_PR3_PR85_Msk          (0x1UL << EXTI_PR3_PR85_Pos)                /*!< 0x00200000 */
+#define EXTI_PR3_PR85              EXTI_PR3_PR85_Msk                           /*!< Pending bit for line 85 */
+#define EXTI_PR3_PR86_Pos          (22U)
+#define EXTI_PR3_PR86_Msk          (0x1UL << EXTI_PR3_PR86_Pos)                /*!< 0x00400000 */
+#define EXTI_PR3_PR86              EXTI_PR3_PR86_Msk                           /*!< Pending bit for line 86 */
+/******************************************************************************/
+/*                                                                            */
+/*                                    FLASH                                   */
+/*                                                                            */
+/******************************************************************************/
+/*
+* @brief FLASH Global Defines
+*/
+#define FLASH_SECTOR_TOTAL                   8U                    /* 8 sectors */
+#define FLASH_SIZE                           0x200000UL            /* 2 MB   */
+#define FLASH_BANK_SIZE                      (FLASH_SIZE >> 1)     /* 1 MB   */
+#define FLASH_SECTOR_SIZE                    0x00020000UL          /* 128 KB */
+#define FLASH_LATENCY_DEFAULT                FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */
+#define FLASH_NB_32BITWORD_IN_FLASHWORD      8U                    /* 256 bits */
+#define DUAL_BANK                                                  /* Dual-bank Flash */
+
+/*******************  Bits definition for FLASH_ACR register  **********************/
+#define FLASH_ACR_LATENCY_Pos                (0U)
+#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Read Latency */
+#define FLASH_ACR_LATENCY_0WS                (0x00000000UL)
+#define FLASH_ACR_LATENCY_1WS                (0x00000001UL)
+#define FLASH_ACR_LATENCY_2WS                (0x00000002UL)
+#define FLASH_ACR_LATENCY_3WS                (0x00000003UL)
+#define FLASH_ACR_LATENCY_4WS                (0x00000004UL)
+#define FLASH_ACR_LATENCY_5WS                (0x00000005UL)
+#define FLASH_ACR_LATENCY_6WS                (0x00000006UL)
+#define FLASH_ACR_LATENCY_7WS                (0x00000007UL)
+#define FLASH_ACR_LATENCY_8WS                (0x00000008UL)
+#define FLASH_ACR_LATENCY_9WS                (0x00000009UL)
+#define FLASH_ACR_LATENCY_10WS               (0x0000000AUL)
+#define FLASH_ACR_LATENCY_11WS               (0x0000000BUL)
+#define FLASH_ACR_LATENCY_12WS               (0x0000000CUL)
+#define FLASH_ACR_LATENCY_13WS               (0x0000000DUL)
+#define FLASH_ACR_LATENCY_14WS               (0x0000000EUL)
+#define FLASH_ACR_LATENCY_15WS               (0x0000000FUL)
+#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
+#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
+#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
+#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
+#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
+
+/*******************  Bits definition for FLASH_CR register  ***********************/
+#define FLASH_CR_LOCK_Pos                    (0U)
+#define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)      /*!< 0x00000001 */
+#define FLASH_CR_LOCK                        FLASH_CR_LOCK_Msk                 /*!< Configuration lock bit */
+#define FLASH_CR_PG_Pos                      (1U)
+#define FLASH_CR_PG_Msk                      (0x1UL << FLASH_CR_PG_Pos)        /*!< 0x00000002 */
+#define FLASH_CR_PG                          FLASH_CR_PG_Msk                   /*!< Internal buffer control bit */
+#define FLASH_CR_SER_Pos                     (2U)
+#define FLASH_CR_SER_Msk                     (0x1UL << FLASH_CR_SER_Pos)       /*!< 0x00000004 */
+#define FLASH_CR_SER                         FLASH_CR_SER_Msk                  /*!< Sector erase request */
+#define FLASH_CR_BER_Pos                     (3U)
+#define FLASH_CR_BER_Msk                     (0x1UL << FLASH_CR_BER_Pos)       /*!< 0x00000008 */
+#define FLASH_CR_BER                         FLASH_CR_BER_Msk                  /*!< Bank erase request */
+#define FLASH_CR_PSIZE_Pos                   (4U)
+#define FLASH_CR_PSIZE_Msk                   (0x3UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000030 */
+#define FLASH_CR_PSIZE                       FLASH_CR_PSIZE_Msk                /*!< Program size */
+#define FLASH_CR_PSIZE_0                     (0x1UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000010 */
+#define FLASH_CR_PSIZE_1                     (0x2UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000020 */
+#define FLASH_CR_FW_Pos                      (6U)
+#define FLASH_CR_FW_Msk                      (0x1UL << FLASH_CR_FW_Pos)        /*!< 0x00000040 */
+#define FLASH_CR_FW                          FLASH_CR_FW_Msk                   /*!< Write forcing control bit */
+#define FLASH_CR_START_Pos                   (7U)
+#define FLASH_CR_START_Msk                   (0x1UL << FLASH_CR_START_Pos)     /*!< 0x00000080 */
+#define FLASH_CR_START                       FLASH_CR_START_Msk                /*!< Erase start control bit */
+#define FLASH_CR_SNB_Pos                     (8U)
+#define FLASH_CR_SNB_Msk                     (0x7UL << FLASH_CR_SNB_Pos)       /*!< 0x00000700 */
+#define FLASH_CR_SNB                         FLASH_CR_SNB_Msk                  /*!< Sector erase selection number */
+#define FLASH_CR_SNB_0                       (0x1UL << FLASH_CR_SNB_Pos)       /*!< 0x00000100 */
+#define FLASH_CR_SNB_1                       (0x2UL << FLASH_CR_SNB_Pos)       /*!< 0x00000200 */
+#define FLASH_CR_SNB_2                       (0x4UL << FLASH_CR_SNB_Pos)       /*!< 0x00000400 */
+#define FLASH_CR_CRC_EN_Pos                  (15U)
+#define FLASH_CR_CRC_EN_Msk                  (0x1UL << FLASH_CR_CRC_EN_Pos)    /*!< 0x00008000 */
+#define FLASH_CR_CRC_EN                      FLASH_CR_CRC_EN_Msk               /*!< CRC control bit */
+#define FLASH_CR_EOPIE_Pos                   (16U)
+#define FLASH_CR_EOPIE_Msk                   (0x1UL << FLASH_CR_EOPIE_Pos)     /*!< 0x00010000 */
+#define FLASH_CR_EOPIE                       FLASH_CR_EOPIE_Msk                /*!< End-of-program interrupt control bit */
+#define FLASH_CR_WRPERRIE_Pos                (17U)
+#define FLASH_CR_WRPERRIE_Msk                (0x1UL << FLASH_CR_WRPERRIE_Pos)  /*!< 0x00020000 */
+#define FLASH_CR_WRPERRIE                    FLASH_CR_WRPERRIE_Msk             /*!< Write protection error interrupt enable bit */
+#define FLASH_CR_PGSERRIE_Pos                (18U)
+#define FLASH_CR_PGSERRIE_Msk                (0x1UL << FLASH_CR_PGSERRIE_Pos)  /*!< 0x00040000 */
+#define FLASH_CR_PGSERRIE                    FLASH_CR_PGSERRIE_Msk             /*!< Programming sequence error interrupt enable bit */
+#define FLASH_CR_STRBERRIE_Pos               (19U)
+#define FLASH_CR_STRBERRIE_Msk               (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */
+#define FLASH_CR_STRBERRIE                   FLASH_CR_STRBERRIE_Msk            /*!< Strobe error interrupt enable bit */
+#define FLASH_CR_INCERRIE_Pos                (21U)
+#define FLASH_CR_INCERRIE_Msk                (0x1UL << FLASH_CR_INCERRIE_Pos)  /*!< 0x00200000 */
+#define FLASH_CR_INCERRIE                    FLASH_CR_INCERRIE_Msk             /*!< Inconsistency error interrupt enable bit */
+#define FLASH_CR_OPERRIE_Pos                 (22U)
+#define FLASH_CR_OPERRIE_Msk                 (0x1UL << FLASH_CR_OPERRIE_Pos)   /*!< 0x00400000 */
+#define FLASH_CR_OPERRIE                     FLASH_CR_OPERRIE_Msk              /*!< Write/erase error interrupt enable bit */
+#define FLASH_CR_RDPERRIE_Pos                (23U)
+#define FLASH_CR_RDPERRIE_Msk                (0x1UL << FLASH_CR_RDPERRIE_Pos)  /*!< 0x00800000 */
+#define FLASH_CR_RDPERRIE                    FLASH_CR_RDPERRIE_Msk             /*!< Read protection error interrupt enable bit */
+#define FLASH_CR_RDSERRIE_Pos                (24U)
+#define FLASH_CR_RDSERRIE_Msk                (0x1UL << FLASH_CR_RDSERRIE_Pos)  /*!< 0x01000000 */
+#define FLASH_CR_RDSERRIE                    FLASH_CR_RDSERRIE_Msk             /*!< Secure error interrupt enable bit */
+#define FLASH_CR_SNECCERRIE_Pos              (25U)
+#define FLASH_CR_SNECCERRIE_Msk              (0x1UL << FLASH_CR_SNECCERRIE_Pos) /*!< 0x02000000 */
+#define FLASH_CR_SNECCERRIE                  FLASH_CR_SNECCERRIE_Msk            /*!< ECC single correction error interrupt enable bit */
+#define FLASH_CR_DBECCERRIE_Pos              (26U)
+#define FLASH_CR_DBECCERRIE_Msk              (0x1UL << FLASH_CR_DBECCERRIE_Pos) /*!< 0x04000000 */
+#define FLASH_CR_DBECCERRIE                  FLASH_CR_DBECCERRIE_Msk            /*!< ECC double detection error interrupt enable bit */
+#define FLASH_CR_CRCENDIE_Pos                (27U)
+#define FLASH_CR_CRCENDIE_Msk                (0x1UL << FLASH_CR_CRCENDIE_Pos)  /*!< 0x08000000 */
+#define FLASH_CR_CRCENDIE                    FLASH_CR_CRCENDIE_Msk             /*!< CRC end of calculation interrupt enable bit */
+#define FLASH_CR_CRCRDERRIE_Pos              (28U)
+#define FLASH_CR_CRCRDERRIE_Msk              (0x1UL << FLASH_CR_CRCRDERRIE_Pos) /*!< 0x10000000 */
+#define FLASH_CR_CRCRDERRIE                  FLASH_CR_CRCRDERRIE_Msk            /*!< CRC read error interrupt enable bit */
+
+/*******************  Bits definition for FLASH_SR register  ***********************/
+#define FLASH_SR_BSY_Pos                     (0U)
+#define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)       /*!< 0x00000001 */
+#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy flag */
+#define FLASH_SR_WBNE_Pos                    (1U)
+#define FLASH_SR_WBNE_Msk                    (0x1UL << FLASH_SR_WBNE_Pos)      /*!< 0x00000002 */
+#define FLASH_SR_WBNE                        FLASH_SR_WBNE_Msk                 /*!< Write buffer not empty flag */
+#define FLASH_SR_QW_Pos                      (2U)
+#define FLASH_SR_QW_Msk                      (0x1UL << FLASH_SR_QW_Pos)        /*!< 0x00000004 */
+#define FLASH_SR_QW                          FLASH_SR_QW_Msk                   /*!< Wait queue flag */
+#define FLASH_SR_CRC_BUSY_Pos                (3U)
+#define FLASH_SR_CRC_BUSY_Msk                (0x1UL << FLASH_SR_CRC_BUSY_Pos)  /*!< 0x00000008 */
+#define FLASH_SR_CRC_BUSY                    FLASH_SR_CRC_BUSY_Msk             /*!< CRC busy flag */
+#define FLASH_SR_EOP_Pos                     (16U)
+#define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)       /*!< 0x00010000 */
+#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End-of-program flag */
+#define FLASH_SR_WRPERR_Pos                  (17U)
+#define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)    /*!< 0x00020000 */
+#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protection error flag */
+#define FLASH_SR_PGSERR_Pos                  (18U)
+#define FLASH_SR_PGSERR_Msk                  (0x1UL << FLASH_SR_PGSERR_Pos)    /*!< 0x00040000 */
+#define FLASH_SR_PGSERR                      FLASH_SR_PGSERR_Msk               /*!< Programming sequence error flag */
+#define FLASH_SR_STRBERR_Pos                 (19U)
+#define FLASH_SR_STRBERR_Msk                 (0x1UL << FLASH_SR_STRBERR_Pos)   /*!< 0x00080000 */
+#define FLASH_SR_STRBERR                     FLASH_SR_STRBERR_Msk              /*!< Strobe error flag */
+#define FLASH_SR_INCERR_Pos                  (21U)
+#define FLASH_SR_INCERR_Msk                  (0x1UL << FLASH_SR_INCERR_Pos)    /*!< 0x00200000 */
+#define FLASH_SR_INCERR                      FLASH_SR_INCERR_Msk               /*!< Inconsistency error flag */
+#define FLASH_SR_OPERR_Pos                   (22U)
+#define FLASH_SR_OPERR_Msk                   (0x1UL << FLASH_SR_OPERR_Pos)     /*!< 0x00400000 */
+#define FLASH_SR_OPERR                       FLASH_SR_OPERR_Msk                /*!< Write/erase error flag */
+#define FLASH_SR_RDPERR_Pos                  (23U)
+#define FLASH_SR_RDPERR_Msk                  (0x1UL << FLASH_SR_RDPERR_Pos)    /*!< 0x00800000 */
+#define FLASH_SR_RDPERR                      FLASH_SR_RDPERR_Msk               /*!< Read protection error flag */
+#define FLASH_SR_RDSERR_Pos                  (24U)
+#define FLASH_SR_RDSERR_Msk                  (0x1UL << FLASH_SR_RDSERR_Pos)    /*!< 0x01000000 */
+#define FLASH_SR_RDSERR                      FLASH_SR_RDSERR_Msk               /*!< Secure error flag */
+#define FLASH_SR_SNECCERR_Pos                (25U)
+#define FLASH_SR_SNECCERR_Msk                (0x1UL << FLASH_SR_SNECCERR_Pos)  /*!< 0x02000000 */
+#define FLASH_SR_SNECCERR                    FLASH_SR_SNECCERR_Msk             /*!< Single correction error flag */
+#define FLASH_SR_DBECCERR_Pos                (26U)
+#define FLASH_SR_DBECCERR_Msk                (0x1UL << FLASH_SR_DBECCERR_Pos)  /*!< 0x04000000 */
+#define FLASH_SR_DBECCERR                    FLASH_SR_DBECCERR_Msk             /*!< ECC double detection error flag */
+#define FLASH_SR_CRCEND_Pos                  (27U)
+#define FLASH_SR_CRCEND_Msk                  (0x1UL << FLASH_SR_CRCEND_Pos)    /*!< 0x08000000 */
+#define FLASH_SR_CRCEND                      FLASH_SR_CRCEND_Msk               /*!< CRC end of calculation flag */
+#define FLASH_SR_CRCRDERR_Pos                (28U)
+#define FLASH_SR_CRCRDERR_Msk                (0x1UL << FLASH_SR_CRCRDERR_Pos)  /*!< 0x10000000 */
+#define FLASH_SR_CRCRDERR                    FLASH_SR_CRCRDERR_Msk             /*!< CRC read error flag */
+
+/*******************  Bits definition for FLASH_CCR register  *******************/
+#define FLASH_CCR_CLR_EOP_Pos                (16U)
+#define FLASH_CCR_CLR_EOP_Msk                (0x1UL << FLASH_CCR_CLR_EOP_Pos)  /*!< 0x00010000 */
+#define FLASH_CCR_CLR_EOP                    FLASH_CCR_CLR_EOP_Msk             /*!< EOP flag clear bit */
+#define FLASH_CCR_CLR_WRPERR_Pos             (17U)
+#define FLASH_CCR_CLR_WRPERR_Msk             (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */
+#define FLASH_CCR_CLR_WRPERR                 FLASH_CCR_CLR_WRPERR_Msk            /*!< WRPERR flag clear bit */
+#define FLASH_CCR_CLR_PGSERR_Pos             (18U)
+#define FLASH_CCR_CLR_PGSERR_Msk             (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */
+#define FLASH_CCR_CLR_PGSERR                 FLASH_CCR_CLR_PGSERR_Msk            /*!< PGSERR flag clear bit */
+#define FLASH_CCR_CLR_STRBERR_Pos            (19U)
+#define FLASH_CCR_CLR_STRBERR_Msk            (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */
+#define FLASH_CCR_CLR_STRBERR                FLASH_CCR_CLR_STRBERR_Msk            /*!< STRBERR flag clear bit */
+#define FLASH_CCR_CLR_INCERR_Pos             (21U)
+#define FLASH_CCR_CLR_INCERR_Msk             (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00200000 */
+#define FLASH_CCR_CLR_INCERR                 FLASH_CCR_CLR_INCERR_Msk            /*!< INCERR flag clear bit */
+#define FLASH_CCR_CLR_OPERR_Pos              (22U)
+#define FLASH_CCR_CLR_OPERR_Msk              (0x1UL << FLASH_CCR_CLR_OPERR_Pos) /*!< 0x00400000 */
+#define FLASH_CCR_CLR_OPERR                  FLASH_CCR_CLR_OPERR_Msk            /*!< OPERR flag clear bit */
+#define FLASH_CCR_CLR_RDPERR_Pos             (23U)
+#define FLASH_CCR_CLR_RDPERR_Msk             (0x1UL << FLASH_CCR_CLR_RDPERR_Pos) /*!< 0x00800000 */
+#define FLASH_CCR_CLR_RDPERR                 FLASH_CCR_CLR_RDPERR_Msk            /*!< RDPERR flag clear bit */
+#define FLASH_CCR_CLR_RDSERR_Pos             (24U)
+#define FLASH_CCR_CLR_RDSERR_Msk             (0x1UL << FLASH_CCR_CLR_RDSERR_Pos) /*!< 0x01000000 */
+#define FLASH_CCR_CLR_RDSERR                 FLASH_CCR_CLR_RDSERR_Msk            /*!< RDSERR flag clear bit */
+#define FLASH_CCR_CLR_SNECCERR_Pos           (25U)
+#define FLASH_CCR_CLR_SNECCERR_Msk           (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos) /*!< 0x02000000 */
+#define FLASH_CCR_CLR_SNECCERR               FLASH_CCR_CLR_SNECCERR_Msk            /*!< SNECCERR flag clear bit */
+#define FLASH_CCR_CLR_DBECCERR_Pos           (26U)
+#define FLASH_CCR_CLR_DBECCERR_Msk           (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos) /*!< 0x04000000 */
+#define FLASH_CCR_CLR_DBECCERR               FLASH_CCR_CLR_DBECCERR_Msk            /*!< DBECCERR flag clear bit */
+#define FLASH_CCR_CLR_CRCEND_Pos             (27U)
+#define FLASH_CCR_CLR_CRCEND_Msk             (0x1UL << FLASH_CCR_CLR_CRCEND_Pos) /*!< 0x08000000 */
+#define FLASH_CCR_CLR_CRCEND                 FLASH_CCR_CLR_CRCEND_Msk            /*!< CRCEND flag clear bit */
+#define FLASH_CCR_CLR_CRCRDERR_Pos           (28U)
+#define FLASH_CCR_CLR_CRCRDERR_Msk           (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos) /*!< 0x10000000 */
+#define FLASH_CCR_CLR_CRCRDERR               FLASH_CCR_CLR_CRCRDERR_Msk            /*!< CRCRDERR flag clear bit */
+
+/*******************  Bits definition for FLASH_OPTCR register  *******************/
+#define FLASH_OPTCR_OPTLOCK_Pos              (0U)
+#define FLASH_OPTCR_OPTLOCK_Msk              (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)  /*!< 0x00000001 */
+#define FLASH_OPTCR_OPTLOCK                  FLASH_OPTCR_OPTLOCK_Msk             /*!< FLASH_OPTCR lock option configuration bit */
+#define FLASH_OPTCR_OPTSTART_Pos             (1U)
+#define FLASH_OPTCR_OPTSTART_Msk             (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */
+#define FLASH_OPTCR_OPTSTART                 FLASH_OPTCR_OPTSTART_Msk            /*!< Option byte start change option configuration bit */
+#define FLASH_OPTCR_MER_Pos                  (4U)
+#define FLASH_OPTCR_MER_Msk                  (0x1UL << FLASH_OPTCR_MER_Pos)      /*!< 0x00000010 */
+#define FLASH_OPTCR_MER                      FLASH_OPTCR_MER_Msk                 /*!< Mass erase request */
+#define FLASH_OPTCR_OPTCHANGEERRIE_Pos       (30U)
+#define FLASH_OPTCR_OPTCHANGEERRIE_Msk       (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) /*!< 0x40000000 */
+#define FLASH_OPTCR_OPTCHANGEERRIE           FLASH_OPTCR_OPTCHANGEERRIE_Msk            /*!< Option byte change error interrupt enable bit */
+#define FLASH_OPTCR_SWAP_BANK_Pos            (31U)
+#define FLASH_OPTCR_SWAP_BANK_Msk            (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */
+#define FLASH_OPTCR_SWAP_BANK                FLASH_OPTCR_SWAP_BANK_Msk            /*!< Bank swapping option configuration bit */
+
+/*******************  Bits definition for FLASH_OPTSR register  ***************/
+#define FLASH_OPTSR_OPT_BUSY_Pos             (0U)
+#define FLASH_OPTSR_OPT_BUSY_Msk             (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos) /*!< 0x00000001 */
+#define FLASH_OPTSR_OPT_BUSY                 FLASH_OPTSR_OPT_BUSY_Msk            /*!< Option byte change ongoing flag */
+#define FLASH_OPTSR_BOR_LEV_Pos              (2U)
+#define FLASH_OPTSR_BOR_LEV_Msk              (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x0000000C */
+#define FLASH_OPTSR_BOR_LEV                  FLASH_OPTSR_BOR_LEV_Msk            /*!< Brownout level option status bit */
+#define FLASH_OPTSR_BOR_LEV_0                (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000004 */
+#define FLASH_OPTSR_BOR_LEV_1                (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000008 */
+#define FLASH_OPTSR_IWDG1_SW_Pos             (4U)
+#define FLASH_OPTSR_IWDG1_SW_Msk             (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos) /*!< 0x00000010 */
+#define FLASH_OPTSR_IWDG1_SW                 FLASH_OPTSR_IWDG1_SW_Msk            /*!< IWDG1 control mode option status bit */
+#define FLASH_OPTSR_NRST_STOP_D1_Pos         (6U)
+#define FLASH_OPTSR_NRST_STOP_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos) /*!< 0x00000040 */
+#define FLASH_OPTSR_NRST_STOP_D1             FLASH_OPTSR_NRST_STOP_D1_Msk            /*!< D1 domain DStop entry reset option status bit */
+#define FLASH_OPTSR_NRST_STBY_D1_Pos         (7U)
+#define FLASH_OPTSR_NRST_STBY_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos) /*!< 0x00000080 */
+#define FLASH_OPTSR_NRST_STBY_D1             FLASH_OPTSR_NRST_STBY_D1_Msk            /*!< D1 domain DStandby entry reset option status bit */
+#define FLASH_OPTSR_RDP_Pos                  (8U)
+#define FLASH_OPTSR_RDP_Msk                  (0xFFUL << FLASH_OPTSR_RDP_Pos)   /*!< 0x0000FF00 */
+#define FLASH_OPTSR_RDP                      FLASH_OPTSR_RDP_Msk               /*!< Readout protection level option status byte */
+#define FLASH_OPTSR_FZ_IWDG_STOP_Pos         (17U)
+#define FLASH_OPTSR_FZ_IWDG_STOP_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos) /*!< 0x00020000 */
+#define FLASH_OPTSR_FZ_IWDG_STOP             FLASH_OPTSR_FZ_IWDG_STOP_Msk            /*!< IWDG Stop mode freeze option status bit */
+#define FLASH_OPTSR_FZ_IWDG_SDBY_Pos         (18U)
+#define FLASH_OPTSR_FZ_IWDG_SDBY_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos) /*!< 0x00040000 */
+#define FLASH_OPTSR_FZ_IWDG_SDBY             FLASH_OPTSR_FZ_IWDG_SDBY_Msk            /*!< IWDG Standby mode freeze option status bit */
+#define FLASH_OPTSR_ST_RAM_SIZE_Pos          (19U)
+#define FLASH_OPTSR_ST_RAM_SIZE_Msk          (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00180000 */
+#define FLASH_OPTSR_ST_RAM_SIZE              FLASH_OPTSR_ST_RAM_SIZE_Msk            /*!< ST RAM size option status */
+#define FLASH_OPTSR_ST_RAM_SIZE_0            (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00080000 */
+#define FLASH_OPTSR_ST_RAM_SIZE_1            (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00100000 */
+#define FLASH_OPTSR_SECURITY_Pos             (21U)
+#define FLASH_OPTSR_SECURITY_Msk             (0x1UL << FLASH_OPTSR_SECURITY_Pos) /*!< 0x00200000 */
+#define FLASH_OPTSR_SECURITY                 FLASH_OPTSR_SECURITY_Msk            /*!< Security enable option status bit */
+#define FLASH_OPTSR_IO_HSLV_Pos              (29U)
+#define FLASH_OPTSR_IO_HSLV_Msk              (0x1UL << FLASH_OPTSR_IO_HSLV_Pos) /*!< 0x20000000 */
+#define FLASH_OPTSR_IO_HSLV                  FLASH_OPTSR_IO_HSLV_Msk            /*!< I/O high-speed at low-voltage status bit */
+#define FLASH_OPTSR_OPTCHANGEERR_Pos         (30U)
+#define FLASH_OPTSR_OPTCHANGEERR_Msk         (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) /*!< 0x40000000 */
+#define FLASH_OPTSR_OPTCHANGEERR             FLASH_OPTSR_OPTCHANGEERR_Msk            /*!< Option byte change error flag */
+#define FLASH_OPTSR_SWAP_BANK_OPT_Pos        (31U)
+#define FLASH_OPTSR_SWAP_BANK_OPT_Msk        (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos) /*!< 0x80000000 */
+#define FLASH_OPTSR_SWAP_BANK_OPT            FLASH_OPTSR_SWAP_BANK_OPT_Msk            /*!< Bank swapping option status bit */
+
+/*******************  Bits definition for FLASH_OPTCCR register  *******************/
+#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos    (30U)
+#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk    (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos) /*!< 0x40000000 */
+#define FLASH_OPTCCR_CLR_OPTCHANGEERR        FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk            /*!< OPTCHANGEERR reset bit */
+
+/*******************  Bits definition for FLASH_PRAR register  *********************/
+#define FLASH_PRAR_PROT_AREA_START_Pos       (0U)
+#define FLASH_PRAR_PROT_AREA_START_Msk       (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos) /*!< 0x00000FFF */
+#define FLASH_PRAR_PROT_AREA_START           FLASH_PRAR_PROT_AREA_START_Msk              /*!< PCROP area start status bits */
+#define FLASH_PRAR_PROT_AREA_END_Pos         (16U)
+#define FLASH_PRAR_PROT_AREA_END_Msk         (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos) /*!< 0x0FFF0000 */
+#define FLASH_PRAR_PROT_AREA_END             FLASH_PRAR_PROT_AREA_END_Msk              /*!< PCROP area end status bits */
+#define FLASH_PRAR_DMEP_Pos                  (31U)
+#define FLASH_PRAR_DMEP_Msk                  (0x1UL << FLASH_PRAR_DMEP_Pos)    /*!< 0x80000000 */
+#define FLASH_PRAR_DMEP                      FLASH_PRAR_DMEP_Msk               /*!< PCROP protected erase enable option status bit */
+
+/*******************  Bits definition for FLASH_SCAR register  *********************/
+#define FLASH_SCAR_SEC_AREA_START_Pos        (0U)
+#define FLASH_SCAR_SEC_AREA_START_Msk        (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos) /*!< 0x00000FFF */
+#define FLASH_SCAR_SEC_AREA_START            FLASH_SCAR_SEC_AREA_START_Msk              /*!< Secure-only area start status bits */
+#define FLASH_SCAR_SEC_AREA_END_Pos          (16U)
+#define FLASH_SCAR_SEC_AREA_END_Msk          (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos) /*!< 0x0FFF0000 */
+#define FLASH_SCAR_SEC_AREA_END              FLASH_SCAR_SEC_AREA_END_Msk              /*!< Secure-only area end status bits */
+#define FLASH_SCAR_DMES_Pos                  (31U)
+#define FLASH_SCAR_DMES_Msk                  (0x1UL << FLASH_SCAR_DMES_Pos)    /*!< 0x80000000 */
+#define FLASH_SCAR_DMES                      FLASH_SCAR_DMES_Msk               /*!< Secure access protected erase enable option status bit */
+
+/*******************  Bits definition for FLASH_WPSN register  *********************/
+#define FLASH_WPSN_WRPSN_Pos                 (0U)
+#define FLASH_WPSN_WRPSN_Msk                 (0xFFUL << FLASH_WPSN_WRPSN_Pos)  /*!< 0x000000FF */
+#define FLASH_WPSN_WRPSN                     FLASH_WPSN_WRPSN_Msk              /*!< Sector write protection option status byte */
+
+/*******************  Bits definition for FLASH_BOOT_CUR register  ****************/
+#define FLASH_BOOT_ADD0_Pos                  (0U)
+#define FLASH_BOOT_ADD0_Msk                  (0xFFFFUL << FLASH_BOOT_ADD0_Pos) /*!< 0x0000FFFF */
+#define FLASH_BOOT_ADD0                      FLASH_BOOT_ADD0_Msk               /*!< Arm Cortex-M7 boot address 0 */
+#define FLASH_BOOT_ADD1_Pos                  (16U)
+#define FLASH_BOOT_ADD1_Msk                  (0xFFFFUL << FLASH_BOOT_ADD1_Pos) /*!< 0xFFFF0000 */
+#define FLASH_BOOT_ADD1                      FLASH_BOOT_ADD1_Msk               /*!< Arm Cortex-M7 boot address 1 */
+
+
+/*******************  Bits definition for FLASH_CRCCR register  ********************/
+#define FLASH_CRCCR_CRC_SECT_Pos             (0U)
+#define FLASH_CRCCR_CRC_SECT_Msk             (0x7UL << FLASH_CRCCR_CRC_SECT_Pos) /*!< 0x00000007 */
+#define FLASH_CRCCR_CRC_SECT                 FLASH_CRCCR_CRC_SECT_Msk            /*!< CRC sector number */
+#define FLASH_CRCCR_CRC_BY_SECT_Pos          (8U)
+#define FLASH_CRCCR_CRC_BY_SECT_Msk          (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos) /*!< 0x00000100 */
+#define FLASH_CRCCR_CRC_BY_SECT              FLASH_CRCCR_CRC_BY_SECT_Msk            /*!< CRC sector mode select bit */
+#define FLASH_CRCCR_ADD_SECT_Pos             (9U)
+#define FLASH_CRCCR_ADD_SECT_Msk             (0x1UL << FLASH_CRCCR_ADD_SECT_Pos) /*!< 0x00000200 */
+#define FLASH_CRCCR_ADD_SECT                 FLASH_CRCCR_ADD_SECT_Msk            /*!< CRC sector select bit */
+#define FLASH_CRCCR_CLEAN_SECT_Pos           (10U)
+#define FLASH_CRCCR_CLEAN_SECT_Msk           (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos) /*!< 0x00000400 */
+#define FLASH_CRCCR_CLEAN_SECT               FLASH_CRCCR_CLEAN_SECT_Msk            /*!< CRC sector list clear bit */
+#define FLASH_CRCCR_START_CRC_Pos            (16U)
+#define FLASH_CRCCR_START_CRC_Msk            (0x1UL << FLASH_CRCCR_START_CRC_Pos) /*!< 0x00010000 */
+#define FLASH_CRCCR_START_CRC                FLASH_CRCCR_START_CRC_Msk            /*!< CRC start bit */
+#define FLASH_CRCCR_CLEAN_CRC_Pos            (17U)
+#define FLASH_CRCCR_CLEAN_CRC_Msk            (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos) /*!< 0x00020000 */
+#define FLASH_CRCCR_CLEAN_CRC                FLASH_CRCCR_CLEAN_CRC_Msk            /*!< CRC clear bit */
+#define FLASH_CRCCR_CRC_BURST_Pos            (20U)
+#define FLASH_CRCCR_CRC_BURST_Msk            (0x3UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00300000 */
+#define FLASH_CRCCR_CRC_BURST                FLASH_CRCCR_CRC_BURST_Msk            /*!< CRC burst size */
+#define FLASH_CRCCR_CRC_BURST_0              (0x1UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00100000 */
+#define FLASH_CRCCR_CRC_BURST_1              (0x2UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00200000 */
+#define FLASH_CRCCR_ALL_BANK_Pos             (22U)
+#define FLASH_CRCCR_ALL_BANK_Msk             (0x1UL << FLASH_CRCCR_ALL_BANK_Pos) /*!< 0x00400000 */
+#define FLASH_CRCCR_ALL_BANK                 FLASH_CRCCR_ALL_BANK_Msk            /*!< CRC select bit */
+
+/*******************  Bits definition for FLASH_CRCSADD register  ****************/
+#define FLASH_CRCSADD_CRC_START_ADDR_Pos     (0U)
+#define FLASH_CRCSADD_CRC_START_ADDR_Msk     (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_CRCSADD_CRC_START_ADDR         FLASH_CRCSADD_CRC_START_ADDR_Msk                   /*!< CRC start address */
+
+/*******************  Bits definition for FLASH_CRCEADD register  ****************/
+#define FLASH_CRCEADD_CRC_END_ADDR_Pos       (0U)
+#define FLASH_CRCEADD_CRC_END_ADDR_Msk       (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_CRCEADD_CRC_END_ADDR           FLASH_CRCEADD_CRC_END_ADDR_Msk                   /*!< CRC end address */
+
+/*******************  Bits definition for FLASH_CRCDATA register  ***************/
+#define FLASH_CRCDATA_CRC_DATA_Pos           (0U)
+#define FLASH_CRCDATA_CRC_DATA_Msk           (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_CRCDATA_CRC_DATA               FLASH_CRCDATA_CRC_DATA_Msk                   /*!< CRC result */
+
+/*******************  Bits definition for FLASH_ECC_FA register  *******************/
+#define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos       (0U)
+#define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk       (0x7FFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos) /*!< 0x00007FFF */
+#define FLASH_ECC_FA_FAIL_ECC_ADDR           FLASH_ECC_FA_FAIL_ECC_ADDR_Msk               /*!< ECC error address */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Flexible Memory Controller                        */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for FMC_BCR1 register  *******************/
+#define FMC_BCR1_CCLKEN_Pos        (20U)
+#define FMC_BCR1_CCLKEN_Msk        (0x1UL << FMC_BCR1_CCLKEN_Pos)              /*!< 0x00100000 */
+#define FMC_BCR1_CCLKEN            FMC_BCR1_CCLKEN_Msk                         /*!<Continous clock enable     */
+#define FMC_BCR1_WFDIS_Pos         (21U)
+#define FMC_BCR1_WFDIS_Msk         (0x1UL << FMC_BCR1_WFDIS_Pos)               /*!< 0x00200000 */
+#define FMC_BCR1_WFDIS             FMC_BCR1_WFDIS_Msk                          /*!<Write FIFO Disable         */
+
+#define FMC_BCR1_BMAP_Pos          (24U)
+#define FMC_BCR1_BMAP_Msk          (0x3UL << FMC_BCR1_BMAP_Pos)                /*!< 0x03000000 */
+#define FMC_BCR1_BMAP              FMC_BCR1_BMAP_Msk                           /*!<BMAP[1:0] FMC bank mapping */
+#define FMC_BCR1_BMAP_0            (0x1UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x01000000 */
+#define FMC_BCR1_BMAP_1            (0x2UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x02000000 */
+
+#define FMC_BCR1_FMCEN_Pos         (31U)
+#define FMC_BCR1_FMCEN_Msk         (0x1UL << FMC_BCR1_FMCEN_Pos)               /*!< 0x80000000 */
+#define FMC_BCR1_FMCEN             FMC_BCR1_FMCEN_Msk                          /*!<FMC controller Enable */
+/******************  Bit definition for FMC_BCRx registers (x=1..4)  *********/
+#define FMC_BCRx_MBKEN_Pos         (0U)
+#define FMC_BCRx_MBKEN_Msk         (0x1UL << FMC_BCRx_MBKEN_Pos)               /*!< 0x00000001 */
+#define FMC_BCRx_MBKEN             FMC_BCRx_MBKEN_Msk                          /*!<Memory bank enable bit                 */
+#define FMC_BCRx_MUXEN_Pos         (1U)
+#define FMC_BCRx_MUXEN_Msk         (0x1UL << FMC_BCRx_MUXEN_Pos)               /*!< 0x00000002 */
+#define FMC_BCRx_MUXEN             FMC_BCRx_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */
+
+#define FMC_BCRx_MTYP_Pos          (2U)
+#define FMC_BCRx_MTYP_Msk          (0x3UL << FMC_BCRx_MTYP_Pos)                /*!< 0x0000000C */
+#define FMC_BCRx_MTYP              FMC_BCRx_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */
+#define FMC_BCRx_MTYP_0            (0x1UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000004 */
+#define FMC_BCRx_MTYP_1            (0x2UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000008 */
+
+#define FMC_BCRx_MWID_Pos          (4U)
+#define FMC_BCRx_MWID_Msk          (0x3UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000030 */
+#define FMC_BCRx_MWID              FMC_BCRx_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCRx_MWID_0            (0x1UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000010 */
+#define FMC_BCRx_MWID_1            (0x2UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000020 */
+
+#define FMC_BCRx_FACCEN_Pos        (6U)
+#define FMC_BCRx_FACCEN_Msk        (0x1UL << FMC_BCRx_FACCEN_Pos)              /*!< 0x00000040 */
+#define FMC_BCRx_FACCEN            FMC_BCRx_FACCEN_Msk                         /*!<Flash access enable        */
+#define FMC_BCRx_BURSTEN_Pos       (8U)
+#define FMC_BCRx_BURSTEN_Msk       (0x1UL << FMC_BCRx_BURSTEN_Pos)             /*!< 0x00000100 */
+#define FMC_BCRx_BURSTEN           FMC_BCRx_BURSTEN_Msk                        /*!<Burst enable bit           */
+#define FMC_BCRx_WAITPOL_Pos       (9U)
+#define FMC_BCRx_WAITPOL_Msk       (0x1UL << FMC_BCRx_WAITPOL_Pos)             /*!< 0x00000200 */
+#define FMC_BCRx_WAITPOL           FMC_BCRx_WAITPOL_Msk                        /*!<Wait signal polarity bit   */
+#define FMC_BCRx_WAITCFG_Pos       (11U)
+#define FMC_BCRx_WAITCFG_Msk       (0x1UL << FMC_BCRx_WAITCFG_Pos)             /*!< 0x00000800 */
+#define FMC_BCRx_WAITCFG           FMC_BCRx_WAITCFG_Msk                        /*!<Wait timing configuration  */
+#define FMC_BCRx_WREN_Pos          (12U)
+#define FMC_BCRx_WREN_Msk          (0x1UL << FMC_BCRx_WREN_Pos)                /*!< 0x00001000 */
+#define FMC_BCRx_WREN              FMC_BCRx_WREN_Msk                           /*!<Write enable bit           */
+#define FMC_BCRx_WAITEN_Pos        (13U)
+#define FMC_BCRx_WAITEN_Msk        (0x1UL << FMC_BCRx_WAITEN_Pos)              /*!< 0x00002000 */
+#define FMC_BCRx_WAITEN            FMC_BCRx_WAITEN_Msk                         /*!<Wait enable bit            */
+#define FMC_BCRx_EXTMOD_Pos        (14U)
+#define FMC_BCRx_EXTMOD_Msk        (0x1UL << FMC_BCRx_EXTMOD_Pos)              /*!< 0x00004000 */
+#define FMC_BCRx_EXTMOD            FMC_BCRx_EXTMOD_Msk                         /*!<Extended mode enable       */
+#define FMC_BCRx_ASYNCWAIT_Pos     (15U)
+#define FMC_BCRx_ASYNCWAIT_Msk     (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)           /*!< 0x00008000 */
+#define FMC_BCRx_ASYNCWAIT         FMC_BCRx_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */
+
+#define FMC_BCRx_CPSIZE_Pos        (16U)
+#define FMC_BCRx_CPSIZE_Msk        (0x7UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00070000 */
+#define FMC_BCRx_CPSIZE            FMC_BCRx_CPSIZE_Msk                         /*!<PSIZE[2:0] bits CRAM Page Size */
+#define FMC_BCRx_CPSIZE_0          (0x1UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00010000 */
+#define FMC_BCRx_CPSIZE_1          (0x2UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00020000 */
+#define FMC_BCRx_CPSIZE_2          (0x4UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00040000 */
+
+#define FMC_BCRx_CBURSTRW_Pos      (19U)
+#define FMC_BCRx_CBURSTRW_Msk      (0x1UL << FMC_BCRx_CBURSTRW_Pos)            /*!< 0x00080000 */
+#define FMC_BCRx_CBURSTRW          FMC_BCRx_CBURSTRW_Msk                       /*!<Write burst enable         */
+
+/******************  Bit definition for FMC_BTRx registers (x=1..4)  *********/
+#define FMC_BTRx_ADDSET_Pos        (0U)
+#define FMC_BTRx_ADDSET_Msk        (0xFUL << FMC_BTRx_ADDSET_Pos)              /*!< 0x0000000F */
+#define FMC_BTRx_ADDSET            FMC_BTRx_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTRx_ADDSET_0          (0x1UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000001 */
+#define FMC_BTRx_ADDSET_1          (0x2UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000002 */
+#define FMC_BTRx_ADDSET_2          (0x4UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000004 */
+#define FMC_BTRx_ADDSET_3          (0x8UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000008 */
+
+#define FMC_BTRx_ADDHLD_Pos        (4U)
+#define FMC_BTRx_ADDHLD_Msk        (0xFUL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x000000F0 */
+#define FMC_BTRx_ADDHLD            FMC_BTRx_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
+#define FMC_BTRx_ADDHLD_0          (0x1UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000010 */
+#define FMC_BTRx_ADDHLD_1          (0x2UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000020 */
+#define FMC_BTRx_ADDHLD_2          (0x4UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000040 */
+#define FMC_BTRx_ADDHLD_3          (0x8UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000080 */
+
+#define FMC_BTRx_DATAST_Pos        (8U)
+#define FMC_BTRx_DATAST_Msk        (0xFFUL << FMC_BTRx_DATAST_Pos)             /*!< 0x0000FF00 */
+#define FMC_BTRx_DATAST            FMC_BTRx_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTRx_DATAST_0          (0x01UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000100 */
+#define FMC_BTRx_DATAST_1          (0x02UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000200 */
+#define FMC_BTRx_DATAST_2          (0x04UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000400 */
+#define FMC_BTRx_DATAST_3          (0x08UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000800 */
+#define FMC_BTRx_DATAST_4          (0x10UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00001000 */
+#define FMC_BTRx_DATAST_5          (0x20UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00002000 */
+#define FMC_BTRx_DATAST_6          (0x40UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00004000 */
+#define FMC_BTRx_DATAST_7          (0x80UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00008000 */
+
+#define FMC_BTRx_BUSTURN_Pos       (16U)
+#define FMC_BTRx_BUSTURN_Msk       (0xFUL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x000F0000 */
+#define FMC_BTRx_BUSTURN           FMC_BTRx_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTRx_BUSTURN_0         (0x1UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00010000 */
+#define FMC_BTRx_BUSTURN_1         (0x2UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00020000 */
+#define FMC_BTRx_BUSTURN_2         (0x4UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00040000 */
+#define FMC_BTRx_BUSTURN_3         (0x8UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00080000 */
+
+#define FMC_BTRx_CLKDIV_Pos        (20U)
+#define FMC_BTRx_CLKDIV_Msk        (0xFUL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00F00000 */
+#define FMC_BTRx_CLKDIV            FMC_BTRx_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTRx_CLKDIV_0          (0x1UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00100000 */
+#define FMC_BTRx_CLKDIV_1          (0x2UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00200000 */
+#define FMC_BTRx_CLKDIV_2          (0x4UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00400000 */
+#define FMC_BTRx_CLKDIV_3          (0x8UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00800000 */
+
+#define FMC_BTRx_DATLAT_Pos        (24U)
+#define FMC_BTRx_DATLAT_Msk        (0xFUL << FMC_BTRx_DATLAT_Pos)              /*!< 0x0F000000 */
+#define FMC_BTRx_DATLAT            FMC_BTRx_DATLAT_Msk                         /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTRx_DATLAT_0          (0x1UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x01000000 */
+#define FMC_BTRx_DATLAT_1          (0x2UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x02000000 */
+#define FMC_BTRx_DATLAT_2          (0x4UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x04000000 */
+#define FMC_BTRx_DATLAT_3          (0x8UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x08000000 */
+
+#define FMC_BTRx_ACCMOD_Pos        (28U)
+#define FMC_BTRx_ACCMOD_Msk        (0x3UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x30000000 */
+#define FMC_BTRx_ACCMOD            FMC_BTRx_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTRx_ACCMOD_0          (0x1UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x10000000 */
+#define FMC_BTRx_ACCMOD_1          (0x2UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x20000000 */
+
+/******************  Bit definition for FMC_BWTRx registers (x=1..4)  *********/
+#define FMC_BWTRx_ADDSET_Pos       (0U)
+#define FMC_BWTRx_ADDSET_Msk       (0xFUL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x0000000F */
+#define FMC_BWTRx_ADDSET           FMC_BWTRx_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTRx_ADDSET_0         (0x1UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000001 */
+#define FMC_BWTRx_ADDSET_1         (0x2UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000002 */
+#define FMC_BWTRx_ADDSET_2         (0x4UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000004 */
+#define FMC_BWTRx_ADDSET_3         (0x8UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000008 */
+
+#define FMC_BWTRx_ADDHLD_Pos       (4U)
+#define FMC_BWTRx_ADDHLD_Msk       (0xFUL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x000000F0 */
+#define FMC_BWTRx_ADDHLD           FMC_BWTRx_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTRx_ADDHLD_0         (0x1UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000010 */
+#define FMC_BWTRx_ADDHLD_1         (0x2UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000020 */
+#define FMC_BWTRx_ADDHLD_2         (0x4UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000040 */
+#define FMC_BWTRx_ADDHLD_3         (0x8UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000080 */
+
+#define FMC_BWTRx_DATAST_Pos       (8U)
+#define FMC_BWTRx_DATAST_Msk       (0xFFUL << FMC_BWTRx_DATAST_Pos)            /*!< 0x0000FF00 */
+#define FMC_BWTRx_DATAST           FMC_BWTRx_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTRx_DATAST_0         (0x01UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000100 */
+#define FMC_BWTRx_DATAST_1         (0x02UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000200 */
+#define FMC_BWTRx_DATAST_2         (0x04UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000400 */
+#define FMC_BWTRx_DATAST_3         (0x08UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000800 */
+#define FMC_BWTRx_DATAST_4         (0x10UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00001000 */
+#define FMC_BWTRx_DATAST_5         (0x20UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00002000 */
+#define FMC_BWTRx_DATAST_6         (0x40UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00004000 */
+#define FMC_BWTRx_DATAST_7         (0x80UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00008000 */
+
+#define FMC_BWTRx_BUSTURN_Pos      (16U)
+#define FMC_BWTRx_BUSTURN_Msk      (0xFUL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x000F0000 */
+#define FMC_BWTRx_BUSTURN          FMC_BWTRx_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BWTRx_BUSTURN_0        (0x1UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00010000 */
+#define FMC_BWTRx_BUSTURN_1        (0x2UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00020000 */
+#define FMC_BWTRx_BUSTURN_2        (0x4UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00040000 */
+#define FMC_BWTRx_BUSTURN_3        (0x8UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00080000 */
+
+#define FMC_BWTRx_ACCMOD_Pos       (28U)
+#define FMC_BWTRx_ACCMOD_Msk       (0x3UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x30000000 */
+#define FMC_BWTRx_ACCMOD           FMC_BWTRx_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTRx_ACCMOD_0         (0x1UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x10000000 */
+#define FMC_BWTRx_ACCMOD_1         (0x2UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x20000000 */
+
+/******************  Bit definition for FMC_PCR register  *******************/
+#define FMC_PCR_PWAITEN_Pos        (1U)
+#define FMC_PCR_PWAITEN_Msk        (0x1UL << FMC_PCR_PWAITEN_Pos)              /*!< 0x00000002 */
+#define FMC_PCR_PWAITEN            FMC_PCR_PWAITEN_Msk                         /*!<Wait feature enable bit                   */
+#define FMC_PCR_PBKEN_Pos          (2U)
+#define FMC_PCR_PBKEN_Msk          (0x1UL << FMC_PCR_PBKEN_Pos)                /*!< 0x00000004 */
+#define FMC_PCR_PBKEN              FMC_PCR_PBKEN_Msk                           /*!<NAND Flash memory bank enable bit */
+
+#define FMC_PCR_PWID_Pos           (4U)
+#define FMC_PCR_PWID_Msk           (0x3UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000030 */
+#define FMC_PCR_PWID               FMC_PCR_PWID_Msk                            /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR_PWID_0             (0x1UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000010 */
+#define FMC_PCR_PWID_1             (0x2UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000020 */
+
+#define FMC_PCR_ECCEN_Pos          (6U)
+#define FMC_PCR_ECCEN_Msk          (0x1UL << FMC_PCR_ECCEN_Pos)                /*!< 0x00000040 */
+#define FMC_PCR_ECCEN              FMC_PCR_ECCEN_Msk                           /*!<ECC computation logic enable bit          */
+
+#define FMC_PCR_TCLR_Pos           (9U)
+#define FMC_PCR_TCLR_Msk           (0xFUL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001E00 */
+#define FMC_PCR_TCLR               FMC_PCR_TCLR_Msk                            /*!<TCLR[3:0] bits (CLE to RE delay)          */
+#define FMC_PCR_TCLR_0             (0x1UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000200 */
+#define FMC_PCR_TCLR_1             (0x2UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000400 */
+#define FMC_PCR_TCLR_2             (0x4UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000800 */
+#define FMC_PCR_TCLR_3             (0x8UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00001000 */
+
+#define FMC_PCR_TAR_Pos            (13U)
+#define FMC_PCR_TAR_Msk            (0xFUL << FMC_PCR_TAR_Pos)                  /*!< 0x0001E000 */
+#define FMC_PCR_TAR                FMC_PCR_TAR_Msk                             /*!<TAR[3:0] bits (ALE to RE delay)           */
+#define FMC_PCR_TAR_0              (0x1UL << FMC_PCR_TAR_Pos)                   /*!< 0x00002000 */
+#define FMC_PCR_TAR_1              (0x2UL << FMC_PCR_TAR_Pos)                   /*!< 0x00004000 */
+#define FMC_PCR_TAR_2              (0x4UL << FMC_PCR_TAR_Pos)                   /*!< 0x00008000 */
+#define FMC_PCR_TAR_3              (0x8UL << FMC_PCR_TAR_Pos)                   /*!< 0x00010000 */
+
+#define FMC_PCR_ECCPS_Pos          (17U)
+#define FMC_PCR_ECCPS_Msk          (0x7UL << FMC_PCR_ECCPS_Pos)                /*!< 0x000E0000 */
+#define FMC_PCR_ECCPS              FMC_PCR_ECCPS_Msk                           /*!<ECCPS[1:0] bits (ECC page size)           */
+#define FMC_PCR_ECCPS_0            (0x1UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00020000 */
+#define FMC_PCR_ECCPS_1            (0x2UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00040000 */
+#define FMC_PCR_ECCPS_2            (0x4UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00080000 */
+
+/*******************  Bit definition for FMC_SR register  *******************/
+#define FMC_SR_IRS_Pos             (0U)
+#define FMC_SR_IRS_Msk             (0x1UL << FMC_SR_IRS_Pos)                   /*!< 0x00000001 */
+#define FMC_SR_IRS                 FMC_SR_IRS_Msk                              /*!<Interrupt Rising Edge status                */
+#define FMC_SR_ILS_Pos             (1U)
+#define FMC_SR_ILS_Msk             (0x1UL << FMC_SR_ILS_Pos)                   /*!< 0x00000002 */
+#define FMC_SR_ILS                 FMC_SR_ILS_Msk                              /*!<Interrupt Level status                      */
+#define FMC_SR_IFS_Pos             (2U)
+#define FMC_SR_IFS_Msk             (0x1UL << FMC_SR_IFS_Pos)                   /*!< 0x00000004 */
+#define FMC_SR_IFS                 FMC_SR_IFS_Msk                              /*!<Interrupt Falling Edge status               */
+#define FMC_SR_IREN_Pos            (3U)
+#define FMC_SR_IREN_Msk            (0x1UL << FMC_SR_IREN_Pos)                  /*!< 0x00000008 */
+#define FMC_SR_IREN                FMC_SR_IREN_Msk                             /*!<Interrupt Rising Edge detection Enable bit  */
+#define FMC_SR_ILEN_Pos            (4U)
+#define FMC_SR_ILEN_Msk            (0x1UL << FMC_SR_ILEN_Pos)                  /*!< 0x00000010 */
+#define FMC_SR_ILEN                FMC_SR_ILEN_Msk                             /*!<Interrupt Level detection Enable bit        */
+#define FMC_SR_IFEN_Pos            (5U)
+#define FMC_SR_IFEN_Msk            (0x1UL << FMC_SR_IFEN_Pos)                  /*!< 0x00000020 */
+#define FMC_SR_IFEN                FMC_SR_IFEN_Msk                             /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR_FEMPT_Pos           (6U)
+#define FMC_SR_FEMPT_Msk           (0x1UL << FMC_SR_FEMPT_Pos)                 /*!< 0x00000040 */
+#define FMC_SR_FEMPT               FMC_SR_FEMPT_Msk                            /*!<FIFO empty                                  */
+
+/******************  Bit definition for FMC_PMEM register  ******************/
+#define FMC_PMEM_MEMSET_Pos       (0U)
+#define FMC_PMEM_MEMSET_Msk       (0xFFUL << FMC_PMEM_MEMSET_Pos)            /*!< 0x000000FF */
+#define FMC_PMEM_MEMSET           FMC_PMEM_MEMSET_Msk                        /*!<MEMSET[7:0] bits (Common memory setup time) */
+#define FMC_PMEM_MEMSET_0         (0x01UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000001 */
+#define FMC_PMEM_MEMSET_1         (0x02UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000002 */
+#define FMC_PMEM_MEMSET_2         (0x04UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000004 */
+#define FMC_PMEM_MEMSET_3         (0x08UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000008 */
+#define FMC_PMEM_MEMSET_4         (0x10UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000010 */
+#define FMC_PMEM_MEMSET_5         (0x20UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000020 */
+#define FMC_PMEM_MEMSET_6         (0x40UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000040 */
+#define FMC_PMEM_MEMSET_7         (0x80UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000080 */
+
+#define FMC_PMEM_MEMWAIT_Pos      (8U)
+#define FMC_PMEM_MEMWAIT_Msk      (0xFFUL << FMC_PMEM_MEMWAIT_Pos)           /*!< 0x0000FF00 */
+#define FMC_PMEM_MEMWAIT          FMC_PMEM_MEMWAIT_Msk                       /*!<MEMWAIT[7:0] bits (Common memory wait time) */
+#define FMC_PMEM_MEMWAIT_0        (0x01UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000100 */
+#define FMC_PMEM_MEMWAIT_1        (0x02UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000200 */
+#define FMC_PMEM_MEMWAIT_2        (0x04UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000400 */
+#define FMC_PMEM_MEMWAIT_3        (0x08UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000800 */
+#define FMC_PMEM_MEMWAIT_4        (0x10UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00001000 */
+#define FMC_PMEM_MEMWAIT_5        (0x20UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00002000 */
+#define FMC_PMEM_MEMWAIT_6        (0x40UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00004000 */
+#define FMC_PMEM_MEMWAIT_7        (0x80UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00008000 */
+
+#define FMC_PMEM_MEMHOLD_Pos      (16U)
+#define FMC_PMEM_MEMHOLD_Msk      (0xFFUL << FMC_PMEM_MEMHOLD_Pos)           /*!< 0x00FF0000 */
+#define FMC_PMEM_MEMHOLD          FMC_PMEM_MEMHOLD_Msk                       /*!<MEMHOLD[7:0] bits (Common memory hold time) */
+#define FMC_PMEM_MEMHOLD_0        (0x01UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00010000 */
+#define FMC_PMEM_MEMHOLD_1        (0x02UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00020000 */
+#define FMC_PMEM_MEMHOLD_2        (0x04UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00040000 */
+#define FMC_PMEM_MEMHOLD_3        (0x08UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00080000 */
+#define FMC_PMEM_MEMHOLD_4        (0x10UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00100000 */
+#define FMC_PMEM_MEMHOLD_5        (0x20UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00200000 */
+#define FMC_PMEM_MEMHOLD_6        (0x40UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00400000 */
+#define FMC_PMEM_MEMHOLD_7        (0x80UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00800000 */
+
+#define FMC_PMEM_MEMHIZ_Pos       (24U)
+#define FMC_PMEM_MEMHIZ_Msk       (0xFFUL << FMC_PMEM_MEMHIZ_Pos)            /*!< 0xFF000000 */
+#define FMC_PMEM_MEMHIZ           FMC_PMEM_MEMHIZ_Msk                        /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */
+#define FMC_PMEM_MEMHIZ_0         (0x01UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x01000000 */
+#define FMC_PMEM_MEMHIZ_1         (0x02UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x02000000 */
+#define FMC_PMEM_MEMHIZ_2         (0x04UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x04000000 */
+#define FMC_PMEM_MEMHIZ_3         (0x08UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x08000000 */
+#define FMC_PMEM_MEMHIZ_4         (0x10UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x10000000 */
+#define FMC_PMEM_MEMHIZ_5         (0x20UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x20000000 */
+#define FMC_PMEM_MEMHIZ_6         (0x40UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x40000000 */
+#define FMC_PMEM_MEMHIZ_7         (0x80UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_PATT register  ******************/
+#define FMC_PATT_ATTSET_Pos       (0U)
+#define FMC_PATT_ATTSET_Msk       (0xFFUL << FMC_PATT_ATTSET_Pos)            /*!< 0x000000FF */
+#define FMC_PATT_ATTSET           FMC_PATT_ATTSET_Msk                        /*!<ATTSET[7:0] bits (Attribute memory setup time) */
+#define FMC_PATT_ATTSET_0         (0x01UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000001 */
+#define FMC_PATT_ATTSET_1         (0x02UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000002 */
+#define FMC_PATT_ATTSET_2         (0x04UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000004 */
+#define FMC_PATT_ATTSET_3         (0x08UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000008 */
+#define FMC_PATT_ATTSET_4         (0x10UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000010 */
+#define FMC_PATT_ATTSET_5         (0x20UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000020 */
+#define FMC_PATT_ATTSET_6         (0x40UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000040 */
+#define FMC_PATT_ATTSET_7         (0x80UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000080 */
+
+#define FMC_PATT_ATTWAIT_Pos      (8U)
+#define FMC_PATT_ATTWAIT_Msk      (0xFFUL << FMC_PATT_ATTWAIT_Pos)           /*!< 0x0000FF00 */
+#define FMC_PATT_ATTWAIT          FMC_PATT_ATTWAIT_Msk                       /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */
+#define FMC_PATT_ATTWAIT_0        (0x01UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000100 */
+#define FMC_PATT_ATTWAIT_1        (0x02UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000200 */
+#define FMC_PATT_ATTWAIT_2        (0x04UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000400 */
+#define FMC_PATT_ATTWAIT_3        (0x08UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000800 */
+#define FMC_PATT_ATTWAIT_4        (0x10UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00001000 */
+#define FMC_PATT_ATTWAIT_5        (0x20UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00002000 */
+#define FMC_PATT_ATTWAIT_6        (0x40UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00004000 */
+#define FMC_PATT_ATTWAIT_7        (0x80UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00008000 */
+
+#define FMC_PATT_ATTHOLD_Pos      (16U)
+#define FMC_PATT_ATTHOLD_Msk      (0xFFUL << FMC_PATT_ATTHOLD_Pos)           /*!< 0x00FF0000 */
+#define FMC_PATT_ATTHOLD          FMC_PATT_ATTHOLD_Msk                       /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */
+#define FMC_PATT_ATTHOLD_0        (0x01UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00010000 */
+#define FMC_PATT_ATTHOLD_1        (0x02UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00020000 */
+#define FMC_PATT_ATTHOLD_2        (0x04UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00040000 */
+#define FMC_PATT_ATTHOLD_3        (0x08UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00080000 */
+#define FMC_PATT_ATTHOLD_4        (0x10UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00100000 */
+#define FMC_PATT_ATTHOLD_5        (0x20UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00200000 */
+#define FMC_PATT_ATTHOLD_6        (0x40UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00400000 */
+#define FMC_PATT_ATTHOLD_7        (0x80UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00800000 */
+
+#define FMC_PATT_ATTHIZ_Pos       (24U)
+#define FMC_PATT_ATTHIZ_Msk       (0xFFUL << FMC_PATT_ATTHIZ_Pos)            /*!< 0xFF000000 */
+#define FMC_PATT_ATTHIZ           FMC_PATT_ATTHIZ_Msk                        /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */
+#define FMC_PATT_ATTHIZ_0         (0x01UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x01000000 */
+#define FMC_PATT_ATTHIZ_1         (0x02UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x02000000 */
+#define FMC_PATT_ATTHIZ_2         (0x04UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x04000000 */
+#define FMC_PATT_ATTHIZ_3         (0x08UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x08000000 */
+#define FMC_PATT_ATTHIZ_4         (0x10UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x10000000 */
+#define FMC_PATT_ATTHIZ_5         (0x20UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x20000000 */
+#define FMC_PATT_ATTHIZ_6         (0x40UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x40000000 */
+#define FMC_PATT_ATTHIZ_7         (0x80UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_ECCR3 register  ******************/
+#define FMC_ECCR3_ECC3_Pos         (0U)
+#define FMC_ECCR3_ECC3_Msk         (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos)        /*!< 0xFFFFFFFF */
+#define FMC_ECCR3_ECC3             FMC_ECCR3_ECC3_Msk                          /*!<ECC result */
+
+/******************  Bit definition for FMC_SDCRx registers (x=1..4)  *********/
+#define FMC_SDCRx_NC_Pos           (0U)
+#define FMC_SDCRx_NC_Msk           (0x3UL << FMC_SDCRx_NC_Pos)                 /*!< 0x00000003 */
+#define FMC_SDCRx_NC               FMC_SDCRx_NC_Msk                            /*!<NC[1:0] bits (Number of column bits) */
+#define FMC_SDCRx_NC_0             (0x1UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000001 */
+#define FMC_SDCRx_NC_1             (0x2UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000002 */
+
+#define FMC_SDCRx_NR_Pos           (2U)
+#define FMC_SDCRx_NR_Msk           (0x3UL << FMC_SDCRx_NR_Pos)                 /*!< 0x0000000C */
+#define FMC_SDCRx_NR               FMC_SDCRx_NR_Msk                            /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCRx_NR_0             (0x1UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000004 */
+#define FMC_SDCRx_NR_1             (0x2UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000008 */
+
+#define FMC_SDCRx_MWID_Pos         (4U)
+#define FMC_SDCRx_MWID_Msk         (0x3UL << FMC_SDCRx_MWID_Pos)               /*!< 0x00000030 */
+#define FMC_SDCRx_MWID             FMC_SDCRx_MWID_Msk                          /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCRx_MWID_0           (0x1UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000010 */
+#define FMC_SDCRx_MWID_1           (0x2UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000020 */
+
+#define FMC_SDCRx_NB_Pos           (6U)
+#define FMC_SDCRx_NB_Msk           (0x1UL << FMC_SDCRx_NB_Pos)                 /*!< 0x00000040 */
+#define FMC_SDCRx_NB               FMC_SDCRx_NB_Msk                            /*!<Number of internal bank */
+
+#define FMC_SDCRx_CAS_Pos          (7U)
+#define FMC_SDCRx_CAS_Msk          (0x3UL << FMC_SDCRx_CAS_Pos)                /*!< 0x00000180 */
+#define FMC_SDCRx_CAS              FMC_SDCRx_CAS_Msk                           /*!<CAS[1:0] bits (CAS latency) */
+#define FMC_SDCRx_CAS_0            (0x1UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000080 */
+#define FMC_SDCRx_CAS_1            (0x2UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000100 */
+
+#define FMC_SDCRx_WP_Pos           (9U)
+#define FMC_SDCRx_WP_Msk           (0x1UL << FMC_SDCRx_WP_Pos)                 /*!< 0x00000200 */
+#define FMC_SDCRx_WP               FMC_SDCRx_WP_Msk                            /*!<Write protection */
+
+#define FMC_SDCRx_SDCLK_Pos        (10U)
+#define FMC_SDCRx_SDCLK_Msk        (0x3UL << FMC_SDCRx_SDCLK_Pos)              /*!< 0x00000C00 */
+#define FMC_SDCRx_SDCLK            FMC_SDCRx_SDCLK_Msk                         /*!<SDRAM clock configuration */
+#define FMC_SDCRx_SDCLK_0          (0x1UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000400 */
+#define FMC_SDCRx_SDCLK_1          (0x2UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000800 */
+
+#define FMC_SDCRx_RBURST_Pos       (12U)
+#define FMC_SDCRx_RBURST_Msk       (0x1UL << FMC_SDCRx_RBURST_Pos)             /*!< 0x00001000 */
+#define FMC_SDCRx_RBURST           FMC_SDCRx_RBURST_Msk                        /*!<Read burst */
+
+#define FMC_SDCRx_RPIPE_Pos        (13U)
+#define FMC_SDCRx_RPIPE_Msk        (0x3UL << FMC_SDCRx_RPIPE_Pos)              /*!< 0x00006000 */
+#define FMC_SDCRx_RPIPE            FMC_SDCRx_RPIPE_Msk                         /*!<Write protection */
+#define FMC_SDCRx_RPIPE_0          (0x1UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00002000 */
+#define FMC_SDCRx_RPIPE_1          (0x2UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00004000 */
+
+/******************  Bit definition for FMC_SDTRx(1,2) register  ******************/
+#define FMC_SDTRx_TMRD_Pos         (0U)
+#define FMC_SDTRx_TMRD_Msk         (0xFUL << FMC_SDTRx_TMRD_Pos)               /*!< 0x0000000F */
+#define FMC_SDTRx_TMRD             FMC_SDTRx_TMRD_Msk                          /*!<TMRD[3:0] bits (Load mode register to active) */
+#define FMC_SDTRx_TMRD_0           (0x1UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000001 */
+#define FMC_SDTRx_TMRD_1           (0x2UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000002 */
+#define FMC_SDTRx_TMRD_2           (0x4UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000004 */
+#define FMC_SDTRx_TMRD_3           (0x8UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000008 */
+
+#define FMC_SDTRx_TXSR_Pos         (4U)
+#define FMC_SDTRx_TXSR_Msk         (0xFUL << FMC_SDTRx_TXSR_Pos)               /*!< 0x000000F0 */
+#define FMC_SDTRx_TXSR             FMC_SDTRx_TXSR_Msk                          /*!<TXSR[3:0] bits (Exit self refresh) */
+#define FMC_SDTRx_TXSR_0           (0x1UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000010 */
+#define FMC_SDTRx_TXSR_1           (0x2UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000020 */
+#define FMC_SDTRx_TXSR_2           (0x4UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000040 */
+#define FMC_SDTRx_TXSR_3           (0x8UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000080 */
+
+#define FMC_SDTRx_TRAS_Pos         (8U)
+#define FMC_SDTRx_TRAS_Msk         (0xFUL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000F00 */
+#define FMC_SDTRx_TRAS             FMC_SDTRx_TRAS_Msk                          /*!<TRAS[3:0] bits (Self refresh time) */
+#define FMC_SDTRx_TRAS_0           (0x1UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000100 */
+#define FMC_SDTRx_TRAS_1           (0x2UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000200 */
+#define FMC_SDTRx_TRAS_2           (0x4UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000400 */
+#define FMC_SDTRx_TRAS_3           (0x8UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000800 */
+
+#define FMC_SDTRx_TRC_Pos          (12U)
+#define FMC_SDTRx_TRC_Msk          (0xFUL << FMC_SDTRx_TRC_Pos)                /*!< 0x0000F000 */
+#define FMC_SDTRx_TRC              FMC_SDTRx_TRC_Msk                           /*!<TRC[2:0] bits (Row cycle delay) */
+#define FMC_SDTRx_TRC_0            (0x1UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00001000 */
+#define FMC_SDTRx_TRC_1            (0x2UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00002000 */
+#define FMC_SDTRx_TRC_2            (0x4UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00004000 */
+
+#define FMC_SDTRx_TWR_Pos          (16U)
+#define FMC_SDTRx_TWR_Msk          (0xFUL << FMC_SDTRx_TWR_Pos)                /*!< 0x000F0000 */
+#define FMC_SDTRx_TWR              FMC_SDTRx_TWR_Msk                           /*!<TRC[2:0] bits (Write recovery delay) */
+#define FMC_SDTRx_TWR_0            (0x1UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00010000 */
+#define FMC_SDTRx_TWR_1            (0x2UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00020000 */
+#define FMC_SDTRx_TWR_2            (0x4UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00040000 */
+
+#define FMC_SDTRx_TRP_Pos          (20U)
+#define FMC_SDTRx_TRP_Msk          (0xFUL << FMC_SDTRx_TRP_Pos)                /*!< 0x00F00000 */
+#define FMC_SDTRx_TRP              FMC_SDTRx_TRP_Msk                           /*!<TRP[2:0] bits (Row precharge delay) */
+#define FMC_SDTRx_TRP_0            (0x1UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00100000 */
+#define FMC_SDTRx_TRP_1            (0x2UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00200000 */
+#define FMC_SDTRx_TRP_2            (0x4UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00400000 */
+
+#define FMC_SDTRx_TRCD_Pos         (24U)
+#define FMC_SDTRx_TRCD_Msk         (0xFUL << FMC_SDTRx_TRCD_Pos)               /*!< 0x0F000000 */
+#define FMC_SDTRx_TRCD             FMC_SDTRx_TRCD_Msk                          /*!<TRP[2:0] bits (Row to column delay) */
+#define FMC_SDTRx_TRCD_0           (0x1UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x01000000 */
+#define FMC_SDTRx_TRCD_1           (0x2UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x02000000 */
+#define FMC_SDTRx_TRCD_2           (0x4UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x04000000 */
+
+/******************  Bit definition for FMC_SDCMR register  ******************/
+#define FMC_SDCMR_MODE_Pos         (0U)
+#define FMC_SDCMR_MODE_Msk         (0x7UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000007 */
+#define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */
+#define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */
+#define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */
+#define FMC_SDCMR_MODE_2           (0x3UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000003 */
+
+#define FMC_SDCMR_CTB2_Pos         (3U)
+#define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */
+#define FMC_SDCMR_CTB2             FMC_SDCMR_CTB2_Msk                          /*!<Command target 2 */
+
+#define FMC_SDCMR_CTB1_Pos         (4U)
+#define FMC_SDCMR_CTB1_Msk         (0x1UL << FMC_SDCMR_CTB1_Pos)               /*!< 0x00000010 */
+#define FMC_SDCMR_CTB1             FMC_SDCMR_CTB1_Msk                          /*!<Command target 1 */
+
+#define FMC_SDCMR_NRFS_Pos         (5U)
+#define FMC_SDCMR_NRFS_Msk         (0xFUL << FMC_SDCMR_NRFS_Pos)               /*!< 0x000001E0 */
+#define FMC_SDCMR_NRFS             FMC_SDCMR_NRFS_Msk                          /*!<NRFS[3:0] bits (Number of auto-refresh) */
+#define FMC_SDCMR_NRFS_0           (0x1UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000020 */
+#define FMC_SDCMR_NRFS_1           (0x2UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000040 */
+#define FMC_SDCMR_NRFS_2           (0x4UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000080 */
+#define FMC_SDCMR_NRFS_3           (0x8UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000100 */
+
+#define FMC_SDCMR_MRD_Pos          (9U)
+#define FMC_SDCMR_MRD_Msk          (0x1FFFUL << FMC_SDCMR_MRD_Pos)             /*!< 0x003FFE00 */
+#define FMC_SDCMR_MRD              FMC_SDCMR_MRD_Msk                           /*!<MRD[12:0] bits (Mode register definition) */
+
+/******************  Bit definition for FMC_SDRTR register  ******************/
+#define FMC_SDRTR_CRE_Pos          (0U)
+#define FMC_SDRTR_CRE_Msk          (0x1UL << FMC_SDRTR_CRE_Pos)                /*!< 0x00000001 */
+#define FMC_SDRTR_CRE              FMC_SDRTR_CRE_Msk                           /*!<Clear refresh error flag */
+
+#define FMC_SDRTR_COUNT_Pos        (1U)
+#define FMC_SDRTR_COUNT_Msk        (0x1FFFUL << FMC_SDRTR_COUNT_Pos)           /*!< 0x00003FFE */
+#define FMC_SDRTR_COUNT            FMC_SDRTR_COUNT_Msk                         /*!<COUNT[12:0] bits (Refresh timer count) */
+
+#define FMC_SDRTR_REIE_Pos         (14U)
+#define FMC_SDRTR_REIE_Msk         (0x1UL << FMC_SDRTR_REIE_Pos)               /*!< 0x00004000 */
+#define FMC_SDRTR_REIE             FMC_SDRTR_REIE_Msk                          /*!<RES interupt enable */
+
+/******************  Bit definition for FMC_SDSR register  ******************/
+#define FMC_SDSR_RE_Pos            (0U)
+#define FMC_SDSR_RE_Msk            (0x1UL << FMC_SDSR_RE_Pos)                  /*!< 0x00000001 */
+#define FMC_SDSR_RE                FMC_SDSR_RE_Msk                             /*!<Refresh error flag */
+
+#define FMC_SDSR_MODES1_Pos        (1U)
+#define FMC_SDSR_MODES1_Msk        (0x3UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000006 */
+#define FMC_SDSR_MODES1            FMC_SDSR_MODES1_Msk                         /*!<MODES1[1:0]bits (Status mode for bank 1) */
+#define FMC_SDSR_MODES1_0          (0x1UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000002 */
+#define FMC_SDSR_MODES1_1          (0x2UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000004 */
+
+#define FMC_SDSR_MODES2_Pos        (3U)
+#define FMC_SDSR_MODES2_Msk        (0x3UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000018 */
+#define FMC_SDSR_MODES2            FMC_SDSR_MODES2_Msk                         /*!<MODES2[1:0]bits (Status mode for bank 2) */
+#define FMC_SDSR_MODES2_0          (0x1UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000008 */
+#define FMC_SDSR_MODES2_1          (0x2UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000010 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            General Purpose I/O                             */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bits definition for GPIO_MODER register  *****************/
+#define GPIO_MODER_MODE0_Pos           (0U)
+#define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
+#define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000002 */
+
+#define GPIO_MODER_MODE1_Pos           (2U)
+#define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
+#define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000008 */
+
+#define GPIO_MODER_MODE2_Pos           (4U)
+#define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
+#define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000020 */
+
+#define GPIO_MODER_MODE3_Pos           (6U)
+#define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000080 */
+
+#define GPIO_MODER_MODE4_Pos           (8U)
+#define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
+#define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000200 */
+
+#define GPIO_MODER_MODE5_Pos           (10U)
+#define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000800 */
+
+#define GPIO_MODER_MODE6_Pos           (12U)
+#define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
+#define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00002000 */
+
+#define GPIO_MODER_MODE7_Pos           (14U)
+#define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00008000 */
+
+#define GPIO_MODER_MODE8_Pos           (16U)
+#define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
+#define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00020000 */
+
+#define GPIO_MODER_MODE9_Pos           (18U)
+#define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00080000 */
+
+#define GPIO_MODER_MODE10_Pos          (20U)
+#define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
+#define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00200000 */
+
+#define GPIO_MODER_MODE11_Pos          (22U)
+#define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00800000 */
+
+#define GPIO_MODER_MODE12_Pos          (24U)
+#define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
+#define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)         /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)         /*!< 0x02000000 */
+
+#define GPIO_MODER_MODE13_Pos          (26U)
+#define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)         /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)         /*!< 0x08000000 */
+
+#define GPIO_MODER_MODE14_Pos          (28U)
+#define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
+#define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)         /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)         /*!< 0x20000000 */
+
+#define GPIO_MODER_MODE15_Pos          (30U)
+#define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)         /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)         /*!< 0x80000000 */
+
+/******************  Bits definition for GPIO_OTYPER register  ****************/
+#define GPIO_OTYPER_OT0_Pos            (0U)
+#define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */
+#define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk
+#define GPIO_OTYPER_OT1_Pos            (1U)
+#define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */
+#define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk
+#define GPIO_OTYPER_OT2_Pos            (2U)
+#define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */
+#define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk
+#define GPIO_OTYPER_OT3_Pos            (3U)
+#define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */
+#define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk
+#define GPIO_OTYPER_OT4_Pos            (4U)
+#define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */
+#define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk
+#define GPIO_OTYPER_OT5_Pos            (5U)
+#define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */
+#define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk
+#define GPIO_OTYPER_OT6_Pos            (6U)
+#define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */
+#define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk
+#define GPIO_OTYPER_OT7_Pos            (7U)
+#define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */
+#define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk
+#define GPIO_OTYPER_OT8_Pos            (8U)
+#define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */
+#define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk
+#define GPIO_OTYPER_OT9_Pos            (9U)
+#define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */
+#define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk
+#define GPIO_OTYPER_OT10_Pos           (10U)
+#define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */
+#define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk
+#define GPIO_OTYPER_OT11_Pos           (11U)
+#define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */
+#define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk
+#define GPIO_OTYPER_OT12_Pos           (12U)
+#define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */
+#define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk
+#define GPIO_OTYPER_OT13_Pos           (13U)
+#define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */
+#define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk
+#define GPIO_OTYPER_OT14_Pos           (14U)
+#define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */
+#define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk
+#define GPIO_OTYPER_OT15_Pos           (15U)
+#define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */
+#define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk
+
+/******************  Bits definition for GPIO_OSPEEDR register  ***************/
+#define GPIO_OSPEEDR_OSPEED0_Pos       (0U)
+#define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */
+#define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk
+#define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000001 */
+#define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000002 */
+
+#define GPIO_OSPEEDR_OSPEED1_Pos       (2U)
+#define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */
+#define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk
+#define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000004 */
+#define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000008 */
+
+#define GPIO_OSPEEDR_OSPEED2_Pos       (4U)
+#define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */
+#define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk
+#define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000010 */
+#define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000020 */
+
+#define GPIO_OSPEEDR_OSPEED3_Pos       (6U)
+#define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */
+#define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk
+#define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000040 */
+#define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000080 */
+
+#define GPIO_OSPEEDR_OSPEED4_Pos       (8U)
+#define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */
+#define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk
+#define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000100 */
+#define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000200 */
+
+#define GPIO_OSPEEDR_OSPEED5_Pos       (10U)
+#define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */
+#define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk
+#define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000400 */
+#define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000800 */
+
+#define GPIO_OSPEEDR_OSPEED6_Pos       (12U)
+#define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */
+#define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk
+#define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00001000 */
+#define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00002000 */
+
+#define GPIO_OSPEEDR_OSPEED7_Pos       (14U)
+#define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */
+#define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk
+#define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00004000 */
+#define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00008000 */
+
+#define GPIO_OSPEEDR_OSPEED8_Pos       (16U)
+#define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */
+#define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk
+#define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00010000 */
+#define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00020000 */
+
+#define GPIO_OSPEEDR_OSPEED9_Pos       (18U)
+#define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */
+#define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk
+#define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00040000 */
+#define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00080000 */
+
+#define GPIO_OSPEEDR_OSPEED10_Pos      (20U)
+#define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */
+#define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk
+#define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00100000 */
+#define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00200000 */
+
+#define GPIO_OSPEEDR_OSPEED11_Pos      (22U)
+#define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */
+#define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk
+#define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00400000 */
+#define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00800000 */
+
+#define GPIO_OSPEEDR_OSPEED12_Pos      (24U)
+#define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */
+#define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk
+#define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x01000000 */
+#define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x02000000 */
+
+#define GPIO_OSPEEDR_OSPEED13_Pos      (26U)
+#define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */
+#define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk
+#define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x04000000 */
+#define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x08000000 */
+
+#define GPIO_OSPEEDR_OSPEED14_Pos      (28U)
+#define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */
+#define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk
+#define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x10000000 */
+#define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x20000000 */
+
+#define GPIO_OSPEEDR_OSPEED15_Pos      (30U)
+#define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */
+#define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk
+#define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x40000000 */
+#define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x80000000 */
+
+/******************  Bits definition for GPIO_PUPDR register  *****************/
+#define GPIO_PUPDR_PUPD0_Pos           (0U)
+#define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000002 */
+
+#define GPIO_PUPDR_PUPD1_Pos           (2U)
+#define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000008 */
+
+#define GPIO_PUPDR_PUPD2_Pos           (4U)
+#define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000020 */
+
+#define GPIO_PUPDR_PUPD3_Pos           (6U)
+#define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000080 */
+
+#define GPIO_PUPDR_PUPD4_Pos           (8U)
+#define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000200 */
+
+#define GPIO_PUPDR_PUPD5_Pos           (10U)
+#define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000800 */
+
+#define GPIO_PUPDR_PUPD6_Pos           (12U)
+#define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00002000 */
+
+#define GPIO_PUPDR_PUPD7_Pos           (14U)
+#define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00008000 */
+
+#define GPIO_PUPDR_PUPD8_Pos           (16U)
+#define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00020000 */
+
+#define GPIO_PUPDR_PUPD9_Pos           (18U)
+#define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00080000 */
+
+#define GPIO_PUPDR_PUPD10_Pos          (20U)
+#define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00200000 */
+
+#define GPIO_PUPDR_PUPD11_Pos          (22U)
+#define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00800000 */
+
+#define GPIO_PUPDR_PUPD12_Pos          (24U)
+#define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x02000000 */
+
+#define GPIO_PUPDR_PUPD13_Pos          (26U)
+#define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x08000000 */
+
+#define GPIO_PUPDR_PUPD14_Pos          (28U)
+#define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x20000000 */
+
+#define GPIO_PUPDR_PUPD15_Pos          (30U)
+#define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x80000000 */
+
+/******************  Bits definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_ID0_Pos               (0U)
+#define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
+#define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos               (1U)
+#define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
+#define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos               (2U)
+#define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
+#define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos               (3U)
+#define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
+#define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos               (4U)
+#define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
+#define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos               (5U)
+#define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
+#define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos               (6U)
+#define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
+#define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos               (7U)
+#define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
+#define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos               (8U)
+#define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
+#define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos               (9U)
+#define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
+#define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos              (10U)
+#define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
+#define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos              (11U)
+#define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
+#define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos              (12U)
+#define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
+#define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos              (13U)
+#define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
+#define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos              (14U)
+#define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
+#define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos              (15U)
+#define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
+#define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk
+
+/******************  Bits definition for GPIO_ODR register  *******************/
+#define GPIO_ODR_OD0_Pos               (0U)
+#define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
+#define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos               (1U)
+#define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
+#define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos               (2U)
+#define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
+#define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos               (3U)
+#define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
+#define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos               (4U)
+#define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
+#define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos               (5U)
+#define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
+#define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos               (6U)
+#define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
+#define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos               (7U)
+#define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
+#define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos               (8U)
+#define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
+#define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos               (9U)
+#define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
+#define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos              (10U)
+#define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
+#define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos              (11U)
+#define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
+#define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos              (12U)
+#define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
+#define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos              (13U)
+#define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
+#define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos              (14U)
+#define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
+#define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos              (15U)
+#define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
+#define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk
+
+/******************  Bits definition for GPIO_BSRR register  ******************/
+#define GPIO_BSRR_BS0_Pos              (0U)
+#define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */
+#define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk
+#define GPIO_BSRR_BS1_Pos              (1U)
+#define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */
+#define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk
+#define GPIO_BSRR_BS2_Pos              (2U)
+#define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */
+#define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk
+#define GPIO_BSRR_BS3_Pos              (3U)
+#define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */
+#define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk
+#define GPIO_BSRR_BS4_Pos              (4U)
+#define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */
+#define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk
+#define GPIO_BSRR_BS5_Pos              (5U)
+#define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */
+#define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk
+#define GPIO_BSRR_BS6_Pos              (6U)
+#define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */
+#define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk
+#define GPIO_BSRR_BS7_Pos              (7U)
+#define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */
+#define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk
+#define GPIO_BSRR_BS8_Pos              (8U)
+#define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */
+#define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk
+#define GPIO_BSRR_BS9_Pos              (9U)
+#define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */
+#define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk
+#define GPIO_BSRR_BS10_Pos             (10U)
+#define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */
+#define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk
+#define GPIO_BSRR_BS11_Pos             (11U)
+#define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */
+#define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk
+#define GPIO_BSRR_BS12_Pos             (12U)
+#define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */
+#define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk
+#define GPIO_BSRR_BS13_Pos             (13U)
+#define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */
+#define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk
+#define GPIO_BSRR_BS14_Pos             (14U)
+#define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */
+#define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk
+#define GPIO_BSRR_BS15_Pos             (15U)
+#define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */
+#define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk
+#define GPIO_BSRR_BR0_Pos              (16U)
+#define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */
+#define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk
+#define GPIO_BSRR_BR1_Pos              (17U)
+#define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */
+#define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk
+#define GPIO_BSRR_BR2_Pos              (18U)
+#define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */
+#define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk
+#define GPIO_BSRR_BR3_Pos              (19U)
+#define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */
+#define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk
+#define GPIO_BSRR_BR4_Pos              (20U)
+#define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */
+#define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk
+#define GPIO_BSRR_BR5_Pos              (21U)
+#define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */
+#define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk
+#define GPIO_BSRR_BR6_Pos              (22U)
+#define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */
+#define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk
+#define GPIO_BSRR_BR7_Pos              (23U)
+#define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */
+#define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk
+#define GPIO_BSRR_BR8_Pos              (24U)
+#define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */
+#define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk
+#define GPIO_BSRR_BR9_Pos              (25U)
+#define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */
+#define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk
+#define GPIO_BSRR_BR10_Pos             (26U)
+#define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */
+#define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk
+#define GPIO_BSRR_BR11_Pos             (27U)
+#define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */
+#define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk
+#define GPIO_BSRR_BR12_Pos             (28U)
+#define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */
+#define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk
+#define GPIO_BSRR_BR13_Pos             (29U)
+#define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */
+#define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk
+#define GPIO_BSRR_BR14_Pos             (30U)
+#define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */
+#define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk
+#define GPIO_BSRR_BR15_Pos             (31U)
+#define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */
+#define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0_Pos             (0U)
+#define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos             (1U)
+#define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos             (2U)
+#define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos             (3U)
+#define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos             (4U)
+#define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos             (5U)
+#define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos             (6U)
+#define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos             (7U)
+#define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos             (8U)
+#define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos             (9U)
+#define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos            (10U)
+#define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos            (11U)
+#define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos            (12U)
+#define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos            (13U)
+#define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos            (14U)
+#define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos            (15U)
+#define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos             (16U)
+#define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk
+
+/****************** Bit definition for GPIO_AFRL register  ********************/
+#define GPIO_AFRL_AFSEL0_Pos           (0U)
+#define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000001 */
+#define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000002 */
+#define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000004 */
+#define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000008 */
+#define GPIO_AFRL_AFSEL1_Pos           (4U)
+#define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000010 */
+#define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000020 */
+#define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000040 */
+#define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000080 */
+#define GPIO_AFRL_AFSEL2_Pos           (8U)
+#define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000100 */
+#define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000200 */
+#define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000400 */
+#define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000800 */
+#define GPIO_AFRL_AFSEL3_Pos           (12U)
+#define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00001000 */
+#define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00002000 */
+#define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00004000 */
+#define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00008000 */
+#define GPIO_AFRL_AFSEL4_Pos           (16U)
+#define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00010000 */
+#define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00020000 */
+#define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00040000 */
+#define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00080000 */
+#define GPIO_AFRL_AFSEL5_Pos           (20U)
+#define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00100000 */
+#define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00200000 */
+#define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00400000 */
+#define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00800000 */
+#define GPIO_AFRL_AFSEL6_Pos           (24U)
+#define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x01000000 */
+#define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x02000000 */
+#define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x04000000 */
+#define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x08000000 */
+#define GPIO_AFRL_AFSEL7_Pos           (28U)
+#define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk
+#define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x10000000 */
+#define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x20000000 */
+#define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x40000000 */
+#define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0
+#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1
+#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2
+#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3
+#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4
+#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5
+#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6
+#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7
+
+/****************** Bit definition for GPIO_AFRH register  ********************/
+#define GPIO_AFRH_AFSEL8_Pos           (0U)
+#define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000001 */
+#define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000002 */
+#define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000004 */
+#define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000008 */
+#define GPIO_AFRH_AFSEL9_Pos           (4U)
+#define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000010 */
+#define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000020 */
+#define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000040 */
+#define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000080 */
+#define GPIO_AFRH_AFSEL10_Pos          (8U)
+#define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000100 */
+#define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000200 */
+#define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000400 */
+#define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000800 */
+#define GPIO_AFRH_AFSEL11_Pos          (12U)
+#define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00001000 */
+#define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00002000 */
+#define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00004000 */
+#define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00008000 */
+#define GPIO_AFRH_AFSEL12_Pos          (16U)
+#define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00010000 */
+#define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00020000 */
+#define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00040000 */
+#define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00080000 */
+#define GPIO_AFRH_AFSEL13_Pos          (20U)
+#define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00100000 */
+#define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00200000 */
+#define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00400000 */
+#define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00800000 */
+#define GPIO_AFRH_AFSEL14_Pos          (24U)
+#define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x01000000 */
+#define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x02000000 */
+#define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x04000000 */
+#define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x08000000 */
+#define GPIO_AFRH_AFSEL15_Pos          (28U)
+#define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk
+#define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x10000000 */
+#define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x20000000 */
+#define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x40000000 */
+#define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8
+#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9
+#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10
+#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11
+#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12
+#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13
+#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14
+#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15
+
+/******************************************************************************/
+/*                                                                            */
+/*                        HSEM HW Semaphore                                   */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for HSEM_R register  ********************/
+#define HSEM_R_PROCID_Pos         (0U)
+#define HSEM_R_PROCID_Msk         (0xFFUL << HSEM_R_PROCID_Pos)                /*!< 0x000000FF */
+#define HSEM_R_PROCID             HSEM_R_PROCID_Msk                            /*!<Semaphore ProcessID */
+#define HSEM_R_COREID_Pos         (8U)
+#define HSEM_R_COREID_Msk         (0xFFUL << HSEM_R_COREID_Pos)                /*!< 0x0000FF00 */
+#define HSEM_R_COREID             HSEM_R_COREID_Msk                            /*!<Semaphore CoreID.   */
+#define HSEM_R_LOCK_Pos           (31U)
+#define HSEM_R_LOCK_Msk           (0x1UL << HSEM_R_LOCK_Pos)                   /*!< 0x80000000 */
+#define HSEM_R_LOCK               HSEM_R_LOCK_Msk                              /*!<Lock indication.    */
+
+/********************  Bit definition for HSEM_RLR register  ******************/
+#define HSEM_RLR_PROCID_Pos       (0U)
+#define HSEM_RLR_PROCID_Msk       (0xFFUL << HSEM_RLR_PROCID_Pos)              /*!< 0x000000FF */
+#define HSEM_RLR_PROCID           HSEM_RLR_PROCID_Msk                          /*!<Semaphore ProcessID */
+#define HSEM_RLR_COREID_Pos       (8U)
+#define HSEM_RLR_COREID_Msk       (0xFFUL << HSEM_RLR_COREID_Pos)              /*!< 0x0000FF00 */
+#define HSEM_RLR_COREID           HSEM_RLR_COREID_Msk                          /*!<Semaphore CoreID.   */
+#define HSEM_RLR_LOCK_Pos         (31U)
+#define HSEM_RLR_LOCK_Msk         (0x1UL << HSEM_RLR_LOCK_Pos)                 /*!< 0x80000000 */
+#define HSEM_RLR_LOCK             HSEM_RLR_LOCK_Msk                            /*!<Lock indication.    */
+
+/********************  Bit definition for HSEM_C1IER register  *****************/
+#define HSEM_C1IER_ISE0_Pos       (0U)
+#define HSEM_C1IER_ISE0_Msk       (0x1UL << HSEM_C1IER_ISE0_Pos)               /*!< 0x00000001 */
+#define HSEM_C1IER_ISE0           HSEM_C1IER_ISE0_Msk                          /*!<semaphore 0 , interrupt 0 enable bit.  */
+#define HSEM_C1IER_ISE1_Pos       (1U)
+#define HSEM_C1IER_ISE1_Msk       (0x1UL << HSEM_C1IER_ISE1_Pos)               /*!< 0x00000002 */
+#define HSEM_C1IER_ISE1           HSEM_C1IER_ISE1_Msk                          /*!<semaphore 1 , interrupt 0 enable bit.  */
+#define HSEM_C1IER_ISE2_Pos       (2U)
+#define HSEM_C1IER_ISE2_Msk       (0x1UL << HSEM_C1IER_ISE2_Pos)               /*!< 0x00000004 */
+#define HSEM_C1IER_ISE2           HSEM_C1IER_ISE2_Msk                          /*!<semaphore 2 , interrupt 0 enable bit.  */
+#define HSEM_C1IER_ISE3_Pos       (3U)
+#define HSEM_C1IER_ISE3_Msk       (0x1UL << HSEM_C1IER_ISE3_Pos)               /*!< 0x00000008 */
+#define HSEM_C1IER_ISE3           HSEM_C1IER_ISE3_Msk                          /*!<semaphore 3 , interrupt 0 enable bit.  */
+#define HSEM_C1IER_ISE4_Pos       (4U)
+#define HSEM_C1IER_ISE4_Msk       (0x1UL << HSEM_C1IER_ISE4_Pos)               /*!< 0x00000010 */
+#define HSEM_C1IER_ISE4           HSEM_C1IER_ISE4_Msk                          /*!<semaphore 4 , interrupt 0 enable bit.  */
+#define HSEM_C1IER_ISE5_Pos       (5U)
+#define HSEM_C1IER_ISE5_Msk       (0x1UL << HSEM_C1IER_ISE5_Pos)               /*!< 0x00000020 */
+#define HSEM_C1IER_ISE5           HSEM_C1IER_ISE5_Msk                          /*!<semaphore 5 interrupt 0 enable bit.    */
+#define HSEM_C1IER_ISE6_Pos       (6U)
+#define HSEM_C1IER_ISE6_Msk       (0x1UL << HSEM_C1IER_ISE6_Pos)               /*!< 0x00000040 */
+#define HSEM_C1IER_ISE6           HSEM_C1IER_ISE6_Msk                          /*!<semaphore 6 interrupt 0 enable bit.    */
+#define HSEM_C1IER_ISE7_Pos       (7U)
+#define HSEM_C1IER_ISE7_Msk       (0x1UL << HSEM_C1IER_ISE7_Pos)               /*!< 0x00000080 */
+#define HSEM_C1IER_ISE7           HSEM_C1IER_ISE7_Msk                          /*!<semaphore 7 interrupt 0 enable bit.    */
+#define HSEM_C1IER_ISE8_Pos       (8U)
+#define HSEM_C1IER_ISE8_Msk       (0x1UL << HSEM_C1IER_ISE8_Pos)               /*!< 0x00000100 */
+#define HSEM_C1IER_ISE8           HSEM_C1IER_ISE8_Msk                          /*!<semaphore 8 interrupt 0 enable bit.    */
+#define HSEM_C1IER_ISE9_Pos       (9U)
+#define HSEM_C1IER_ISE9_Msk       (0x1UL << HSEM_C1IER_ISE9_Pos)               /*!< 0x00000200 */
+#define HSEM_C1IER_ISE9           HSEM_C1IER_ISE9_Msk                          /*!<semaphore 9 interrupt 0 enable bit.    */
+#define HSEM_C1IER_ISE10_Pos      (10U)
+#define HSEM_C1IER_ISE10_Msk      (0x1UL << HSEM_C1IER_ISE10_Pos)              /*!< 0x00000400 */
+#define HSEM_C1IER_ISE10          HSEM_C1IER_ISE10_Msk                         /*!<semaphore 10 interrupt 0 enable bit.   */
+#define HSEM_C1IER_ISE11_Pos      (11U)
+#define HSEM_C1IER_ISE11_Msk      (0x1UL << HSEM_C1IER_ISE11_Pos)              /*!< 0x00000800 */
+#define HSEM_C1IER_ISE11          HSEM_C1IER_ISE11_Msk                         /*!<semaphore 11 interrupt 0 enable bit.   */
+#define HSEM_C1IER_ISE12_Pos      (12U)
+#define HSEM_C1IER_ISE12_Msk      (0x1UL << HSEM_C1IER_ISE12_Pos)              /*!< 0x00001000 */
+#define HSEM_C1IER_ISE12          HSEM_C1IER_ISE12_Msk                         /*!<semaphore 12 interrupt 0 enable bit.   */
+#define HSEM_C1IER_ISE13_Pos      (13U)
+#define HSEM_C1IER_ISE13_Msk      (0x1UL << HSEM_C1IER_ISE13_Pos)              /*!< 0x00002000 */
+#define HSEM_C1IER_ISE13          HSEM_C1IER_ISE13_Msk                         /*!<semaphore 13 interrupt 0 enable bit.   */
+#define HSEM_C1IER_ISE14_Pos      (14U)
+#define HSEM_C1IER_ISE14_Msk      (0x1UL << HSEM_C1IER_ISE14_Pos)              /*!< 0x00004000 */
+#define HSEM_C1IER_ISE14          HSEM_C1IER_ISE14_Msk                         /*!<semaphore 14 interrupt 0 enable bit.   */
+#define HSEM_C1IER_ISE15_Pos      (15U)
+#define HSEM_C1IER_ISE15_Msk      (0x1UL << HSEM_C1IER_ISE15_Pos)              /*!< 0x00008000 */
+#define HSEM_C1IER_ISE15          HSEM_C1IER_ISE15_Msk                         /*!<semaphore 15 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE16_Pos      (16U)
+#define HSEM_C1IER_ISE16_Msk      (0x1UL << HSEM_C1IER_ISE16_Pos)              /*!< 0x00010000 */
+#define HSEM_C1IER_ISE16          HSEM_C1IER_ISE16_Msk                         /*!<semaphore 16 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE17_Pos      (17U)
+#define HSEM_C1IER_ISE17_Msk      (0x1UL << HSEM_C1IER_ISE17_Pos)              /*!< 0x00020000 */
+#define HSEM_C1IER_ISE17          HSEM_C1IER_ISE17_Msk                         /*!<semaphore 17 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE18_Pos      (18U)
+#define HSEM_C1IER_ISE18_Msk      (0x1UL << HSEM_C1IER_ISE18_Pos)              /*!< 0x00040000 */
+#define HSEM_C1IER_ISE18          HSEM_C1IER_ISE18_Msk                         /*!<semaphore 18 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE19_Pos      (19U)
+#define HSEM_C1IER_ISE19_Msk      (0x1UL << HSEM_C1IER_ISE19_Pos)              /*!< 0x00080000 */
+#define HSEM_C1IER_ISE19          HSEM_C1IER_ISE19_Msk                         /*!<semaphore 19 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE20_Pos      (20U)
+#define HSEM_C1IER_ISE20_Msk      (0x1UL << HSEM_C1IER_ISE20_Pos)              /*!< 0x00100000 */
+#define HSEM_C1IER_ISE20          HSEM_C1IER_ISE20_Msk                         /*!<semaphore 20 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE21_Pos      (21U)
+#define HSEM_C1IER_ISE21_Msk      (0x1UL << HSEM_C1IER_ISE21_Pos)              /*!< 0x00200000 */
+#define HSEM_C1IER_ISE21          HSEM_C1IER_ISE21_Msk                         /*!<semaphore 21 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE22_Pos      (22U)
+#define HSEM_C1IER_ISE22_Msk      (0x1UL << HSEM_C1IER_ISE22_Pos)              /*!< 0x00400000 */
+#define HSEM_C1IER_ISE22          HSEM_C1IER_ISE22_Msk                         /*!<semaphore 22 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE23_Pos      (23U)
+#define HSEM_C1IER_ISE23_Msk      (0x1UL << HSEM_C1IER_ISE23_Pos)              /*!< 0x00800000 */
+#define HSEM_C1IER_ISE23          HSEM_C1IER_ISE23_Msk                         /*!<semaphore 23 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE24_Pos      (24U)
+#define HSEM_C1IER_ISE24_Msk      (0x1UL << HSEM_C1IER_ISE24_Pos)              /*!< 0x01000000 */
+#define HSEM_C1IER_ISE24          HSEM_C1IER_ISE24_Msk                         /*!<semaphore 24 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE25_Pos      (25U)
+#define HSEM_C1IER_ISE25_Msk      (0x1UL << HSEM_C1IER_ISE25_Pos)              /*!< 0x02000000 */
+#define HSEM_C1IER_ISE25          HSEM_C1IER_ISE25_Msk                         /*!<semaphore 25 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE26_Pos      (26U)
+#define HSEM_C1IER_ISE26_Msk      (0x1UL << HSEM_C1IER_ISE26_Pos)              /*!< 0x04000000 */
+#define HSEM_C1IER_ISE26          HSEM_C1IER_ISE26_Msk                         /*!<semaphore 26 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE27_Pos      (27U)
+#define HSEM_C1IER_ISE27_Msk      (0x1UL << HSEM_C1IER_ISE27_Pos)              /*!< 0x08000000 */
+#define HSEM_C1IER_ISE27          HSEM_C1IER_ISE27_Msk                         /*!<semaphore 27 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE28_Pos      (28U)
+#define HSEM_C1IER_ISE28_Msk      (0x1UL << HSEM_C1IER_ISE28_Pos)              /*!< 0x10000000 */
+#define HSEM_C1IER_ISE28          HSEM_C1IER_ISE28_Msk                         /*!<semaphore 28 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE29_Pos      (29U)
+#define HSEM_C1IER_ISE29_Msk      (0x1UL << HSEM_C1IER_ISE29_Pos)              /*!< 0x20000000 */
+#define HSEM_C1IER_ISE29          HSEM_C1IER_ISE29_Msk                         /*!<semaphore 29 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE30_Pos      (30U)
+#define HSEM_C1IER_ISE30_Msk      (0x1UL << HSEM_C1IER_ISE30_Pos)              /*!< 0x40000000 */
+#define HSEM_C1IER_ISE30          HSEM_C1IER_ISE30_Msk                         /*!<semaphore 30 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE31_Pos      (31U)
+#define HSEM_C1IER_ISE31_Msk      (0x1UL << HSEM_C1IER_ISE31_Pos)              /*!< 0x80000000 */
+#define HSEM_C1IER_ISE31          HSEM_C1IER_ISE31_Msk                         /*!<semaphore 31 interrupt 0 enable bit. */
+
+/********************  Bit definition for HSEM_C1ICR register  *****************/
+#define HSEM_C1ICR_ISC0_Pos       (0U)
+#define HSEM_C1ICR_ISC0_Msk       (0x1UL << HSEM_C1ICR_ISC0_Pos)               /*!< 0x00000001 */
+#define HSEM_C1ICR_ISC0           HSEM_C1ICR_ISC0_Msk                          /*!<semaphore 0 , interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC1_Pos       (1U)
+#define HSEM_C1ICR_ISC1_Msk       (0x1UL << HSEM_C1ICR_ISC1_Pos)               /*!< 0x00000002 */
+#define HSEM_C1ICR_ISC1           HSEM_C1ICR_ISC1_Msk                          /*!<semaphore 1 , interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC2_Pos       (2U)
+#define HSEM_C1ICR_ISC2_Msk       (0x1UL << HSEM_C1ICR_ISC2_Pos)               /*!< 0x00000004 */
+#define HSEM_C1ICR_ISC2           HSEM_C1ICR_ISC2_Msk                          /*!<semaphore 2 , interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC3_Pos       (3U)
+#define HSEM_C1ICR_ISC3_Msk       (0x1UL << HSEM_C1ICR_ISC3_Pos)               /*!< 0x00000008 */
+#define HSEM_C1ICR_ISC3           HSEM_C1ICR_ISC3_Msk                          /*!<semaphore 3 , interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC4_Pos       (4U)
+#define HSEM_C1ICR_ISC4_Msk       (0x1UL << HSEM_C1ICR_ISC4_Pos)               /*!< 0x00000010 */
+#define HSEM_C1ICR_ISC4           HSEM_C1ICR_ISC4_Msk                          /*!<semaphore 4 , interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC5_Pos       (5U)
+#define HSEM_C1ICR_ISC5_Msk       (0x1UL << HSEM_C1ICR_ISC5_Pos)               /*!< 0x00000020 */
+#define HSEM_C1ICR_ISC5           HSEM_C1ICR_ISC5_Msk                          /*!<semaphore 5 interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC6_Pos       (6U)
+#define HSEM_C1ICR_ISC6_Msk       (0x1UL << HSEM_C1ICR_ISC6_Pos)               /*!< 0x00000040 */
+#define HSEM_C1ICR_ISC6           HSEM_C1ICR_ISC6_Msk                          /*!<semaphore 6 interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC7_Pos       (7U)
+#define HSEM_C1ICR_ISC7_Msk       (0x1UL << HSEM_C1ICR_ISC7_Pos)               /*!< 0x00000080 */
+#define HSEM_C1ICR_ISC7           HSEM_C1ICR_ISC7_Msk                          /*!<semaphore 7 interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC8_Pos       (8U)
+#define HSEM_C1ICR_ISC8_Msk       (0x1UL << HSEM_C1ICR_ISC8_Pos)               /*!< 0x00000100 */
+#define HSEM_C1ICR_ISC8           HSEM_C1ICR_ISC8_Msk                          /*!<semaphore 8 interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC9_Pos       (9U)
+#define HSEM_C1ICR_ISC9_Msk       (0x1UL << HSEM_C1ICR_ISC9_Pos)               /*!< 0x00000200 */
+#define HSEM_C1ICR_ISC9           HSEM_C1ICR_ISC9_Msk                          /*!<semaphore 9 interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC10_Pos      (10U)
+#define HSEM_C1ICR_ISC10_Msk      (0x1UL << HSEM_C1ICR_ISC10_Pos)              /*!< 0x00000400 */
+#define HSEM_C1ICR_ISC10          HSEM_C1ICR_ISC10_Msk                         /*!<semaphore 10 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC11_Pos      (11U)
+#define HSEM_C1ICR_ISC11_Msk      (0x1UL << HSEM_C1ICR_ISC11_Pos)              /*!< 0x00000800 */
+#define HSEM_C1ICR_ISC11          HSEM_C1ICR_ISC11_Msk                         /*!<semaphore 11 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC12_Pos      (12U)
+#define HSEM_C1ICR_ISC12_Msk      (0x1UL << HSEM_C1ICR_ISC12_Pos)              /*!< 0x00001000 */
+#define HSEM_C1ICR_ISC12          HSEM_C1ICR_ISC12_Msk                         /*!<semaphore 12 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC13_Pos      (13U)
+#define HSEM_C1ICR_ISC13_Msk      (0x1UL << HSEM_C1ICR_ISC13_Pos)              /*!< 0x00002000 */
+#define HSEM_C1ICR_ISC13          HSEM_C1ICR_ISC13_Msk                         /*!<semaphore 13 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC14_Pos      (14U)
+#define HSEM_C1ICR_ISC14_Msk      (0x1UL << HSEM_C1ICR_ISC14_Pos)              /*!< 0x00004000 */
+#define HSEM_C1ICR_ISC14          HSEM_C1ICR_ISC14_Msk                         /*!<semaphore 14 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC15_Pos      (15U)
+#define HSEM_C1ICR_ISC15_Msk      (0x1UL << HSEM_C1ICR_ISC15_Pos)              /*!< 0x00008000 */
+#define HSEM_C1ICR_ISC15          HSEM_C1ICR_ISC15_Msk                         /*!<semaphore 15 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC16_Pos      (16U)
+#define HSEM_C1ICR_ISC16_Msk      (0x1UL << HSEM_C1ICR_ISC16_Pos)              /*!< 0x00010000 */
+#define HSEM_C1ICR_ISC16          HSEM_C1ICR_ISC16_Msk                         /*!<semaphore 16 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC17_Pos      (17U)
+#define HSEM_C1ICR_ISC17_Msk      (0x1UL << HSEM_C1ICR_ISC17_Pos)              /*!< 0x00020000 */
+#define HSEM_C1ICR_ISC17          HSEM_C1ICR_ISC17_Msk                         /*!<semaphore 17 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC18_Pos      (18U)
+#define HSEM_C1ICR_ISC18_Msk      (0x1UL << HSEM_C1ICR_ISC18_Pos)              /*!< 0x00040000 */
+#define HSEM_C1ICR_ISC18          HSEM_C1ICR_ISC18_Msk                         /*!<semaphore 18 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC19_Pos      (19U)
+#define HSEM_C1ICR_ISC19_Msk      (0x1UL << HSEM_C1ICR_ISC19_Pos)              /*!< 0x00080000 */
+#define HSEM_C1ICR_ISC19          HSEM_C1ICR_ISC19_Msk                         /*!<semaphore 19 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC20_Pos      (20U)
+#define HSEM_C1ICR_ISC20_Msk      (0x1UL << HSEM_C1ICR_ISC20_Pos)              /*!< 0x00100000 */
+#define HSEM_C1ICR_ISC20          HSEM_C1ICR_ISC20_Msk                         /*!<semaphore 20 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC21_Pos      (21U)
+#define HSEM_C1ICR_ISC21_Msk      (0x1UL << HSEM_C1ICR_ISC21_Pos)              /*!< 0x00200000 */
+#define HSEM_C1ICR_ISC21          HSEM_C1ICR_ISC21_Msk                         /*!<semaphore 21 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC22_Pos      (22U)
+#define HSEM_C1ICR_ISC22_Msk      (0x1UL << HSEM_C1ICR_ISC22_Pos)              /*!< 0x00400000 */
+#define HSEM_C1ICR_ISC22          HSEM_C1ICR_ISC22_Msk                         /*!<semaphore 22 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC23_Pos      (23U)
+#define HSEM_C1ICR_ISC23_Msk      (0x1UL << HSEM_C1ICR_ISC23_Pos)              /*!< 0x00800000 */
+#define HSEM_C1ICR_ISC23          HSEM_C1ICR_ISC23_Msk                         /*!<semaphore 23 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC24_Pos      (24U)
+#define HSEM_C1ICR_ISC24_Msk      (0x1UL << HSEM_C1ICR_ISC24_Pos)              /*!< 0x01000000 */
+#define HSEM_C1ICR_ISC24          HSEM_C1ICR_ISC24_Msk                         /*!<semaphore 24 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC25_Pos      (25U)
+#define HSEM_C1ICR_ISC25_Msk      (0x1UL << HSEM_C1ICR_ISC25_Pos)              /*!< 0x02000000 */
+#define HSEM_C1ICR_ISC25          HSEM_C1ICR_ISC25_Msk                         /*!<semaphore 25 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC26_Pos      (26U)
+#define HSEM_C1ICR_ISC26_Msk      (0x1UL << HSEM_C1ICR_ISC26_Pos)              /*!< 0x04000000 */
+#define HSEM_C1ICR_ISC26          HSEM_C1ICR_ISC26_Msk                         /*!<semaphore 26 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC27_Pos      (27U)
+#define HSEM_C1ICR_ISC27_Msk      (0x1UL << HSEM_C1ICR_ISC27_Pos)              /*!< 0x08000000 */
+#define HSEM_C1ICR_ISC27          HSEM_C1ICR_ISC27_Msk                         /*!<semaphore 27 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC28_Pos      (28U)
+#define HSEM_C1ICR_ISC28_Msk      (0x1UL << HSEM_C1ICR_ISC28_Pos)              /*!< 0x10000000 */
+#define HSEM_C1ICR_ISC28          HSEM_C1ICR_ISC28_Msk                         /*!<semaphore 28 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC29_Pos      (29U)
+#define HSEM_C1ICR_ISC29_Msk      (0x1UL << HSEM_C1ICR_ISC29_Pos)              /*!< 0x20000000 */
+#define HSEM_C1ICR_ISC29          HSEM_C1ICR_ISC29_Msk                         /*!<semaphore 29 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC30_Pos      (30U)
+#define HSEM_C1ICR_ISC30_Msk      (0x1UL << HSEM_C1ICR_ISC30_Pos)              /*!< 0x40000000 */
+#define HSEM_C1ICR_ISC30          HSEM_C1ICR_ISC30_Msk                         /*!<semaphore 30 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC31_Pos      (31U)
+#define HSEM_C1ICR_ISC31_Msk      (0x1UL << HSEM_C1ICR_ISC31_Pos)              /*!< 0x80000000 */
+#define HSEM_C1ICR_ISC31          HSEM_C1ICR_ISC31_Msk                         /*!<semaphore 31 interrupt 0 clear bit. */
+
+/********************  Bit definition for HSEM_C1ISR register  *****************/
+#define HSEM_C1ISR_ISF0_Pos       (0U)
+#define HSEM_C1ISR_ISF0_Msk       (0x1UL << HSEM_C1ISR_ISF0_Pos)               /*!< 0x00000001 */
+#define HSEM_C1ISR_ISF0           HSEM_C1ISR_ISF0_Msk                          /*!<semaphore 0 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF1_Pos       (1U)
+#define HSEM_C1ISR_ISF1_Msk       (0x1UL << HSEM_C1ISR_ISF1_Pos)               /*!< 0x00000002 */
+#define HSEM_C1ISR_ISF1           HSEM_C1ISR_ISF1_Msk                          /*!<semaphore 1 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF2_Pos       (2U)
+#define HSEM_C1ISR_ISF2_Msk       (0x1UL << HSEM_C1ISR_ISF2_Pos)               /*!< 0x00000004 */
+#define HSEM_C1ISR_ISF2           HSEM_C1ISR_ISF2_Msk                          /*!<semaphore 2 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF3_Pos       (3U)
+#define HSEM_C1ISR_ISF3_Msk       (0x1UL << HSEM_C1ISR_ISF3_Pos)               /*!< 0x00000008 */
+#define HSEM_C1ISR_ISF3           HSEM_C1ISR_ISF3_Msk                          /*!<semaphore 3 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF4_Pos       (4U)
+#define HSEM_C1ISR_ISF4_Msk       (0x1UL << HSEM_C1ISR_ISF4_Pos)               /*!< 0x00000010 */
+#define HSEM_C1ISR_ISF4           HSEM_C1ISR_ISF4_Msk                          /*!<semaphore 4 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF5_Pos       (5U)
+#define HSEM_C1ISR_ISF5_Msk       (0x1UL << HSEM_C1ISR_ISF5_Pos)               /*!< 0x00000020 */
+#define HSEM_C1ISR_ISF5           HSEM_C1ISR_ISF5_Msk                          /*!<semaphore 5 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF6_Pos       (6U)
+#define HSEM_C1ISR_ISF6_Msk       (0x1UL << HSEM_C1ISR_ISF6_Pos)               /*!< 0x00000040 */
+#define HSEM_C1ISR_ISF6           HSEM_C1ISR_ISF6_Msk                          /*!<semaphore 6 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF7_Pos       (7U)
+#define HSEM_C1ISR_ISF7_Msk       (0x1UL << HSEM_C1ISR_ISF7_Pos)               /*!< 0x00000080 */
+#define HSEM_C1ISR_ISF7           HSEM_C1ISR_ISF7_Msk                          /*!<semaphore 7 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF8_Pos       (8U)
+#define HSEM_C1ISR_ISF8_Msk       (0x1UL << HSEM_C1ISR_ISF8_Pos)               /*!< 0x00000100 */
+#define HSEM_C1ISR_ISF8           HSEM_C1ISR_ISF8_Msk                          /*!<semaphore 8 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF9_Pos       (9U)
+#define HSEM_C1ISR_ISF9_Msk       (0x1UL << HSEM_C1ISR_ISF9_Pos)               /*!< 0x00000200 */
+#define HSEM_C1ISR_ISF9           HSEM_C1ISR_ISF9_Msk                          /*!<semaphore 9 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF10_Pos      (10U)
+#define HSEM_C1ISR_ISF10_Msk      (0x1UL << HSEM_C1ISR_ISF10_Pos)              /*!< 0x00000400 */
+#define HSEM_C1ISR_ISF10          HSEM_C1ISR_ISF10_Msk                         /*!<semaphore 10 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF11_Pos      (11U)
+#define HSEM_C1ISR_ISF11_Msk      (0x1UL << HSEM_C1ISR_ISF11_Pos)              /*!< 0x00000800 */
+#define HSEM_C1ISR_ISF11          HSEM_C1ISR_ISF11_Msk                         /*!<semaphore 11 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF12_Pos      (12U)
+#define HSEM_C1ISR_ISF12_Msk      (0x1UL << HSEM_C1ISR_ISF12_Pos)              /*!< 0x00001000 */
+#define HSEM_C1ISR_ISF12          HSEM_C1ISR_ISF12_Msk                         /*!<semaphore 12 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF13_Pos      (13U)
+#define HSEM_C1ISR_ISF13_Msk      (0x1UL << HSEM_C1ISR_ISF13_Pos)              /*!< 0x00002000 */
+#define HSEM_C1ISR_ISF13          HSEM_C1ISR_ISF13_Msk                         /*!<semaphore 13 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF14_Pos      (14U)
+#define HSEM_C1ISR_ISF14_Msk      (0x1UL << HSEM_C1ISR_ISF14_Pos)              /*!< 0x00004000 */
+#define HSEM_C1ISR_ISF14          HSEM_C1ISR_ISF14_Msk                         /*!<semaphore 14 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF15_Pos      (15U)
+#define HSEM_C1ISR_ISF15_Msk      (0x1UL << HSEM_C1ISR_ISF15_Pos)              /*!< 0x00008000 */
+#define HSEM_C1ISR_ISF15          HSEM_C1ISR_ISF15_Msk                         /*!<semaphore 15 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF16_Pos      (16U)
+#define HSEM_C1ISR_ISF16_Msk      (0x1UL << HSEM_C1ISR_ISF16_Pos)              /*!< 0x00010000 */
+#define HSEM_C1ISR_ISF16          HSEM_C1ISR_ISF16_Msk                         /*!<semaphore 16 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF17_Pos      (17U)
+#define HSEM_C1ISR_ISF17_Msk      (0x1UL << HSEM_C1ISR_ISF17_Pos)              /*!< 0x00020000 */
+#define HSEM_C1ISR_ISF17          HSEM_C1ISR_ISF17_Msk                         /*!<semaphore 17 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF18_Pos      (18U)
+#define HSEM_C1ISR_ISF18_Msk      (0x1UL << HSEM_C1ISR_ISF18_Pos)              /*!< 0x00040000 */
+#define HSEM_C1ISR_ISF18          HSEM_C1ISR_ISF18_Msk                         /*!<semaphore 18 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF19_Pos      (19U)
+#define HSEM_C1ISR_ISF19_Msk      (0x1UL << HSEM_C1ISR_ISF19_Pos)              /*!< 0x00080000 */
+#define HSEM_C1ISR_ISF19          HSEM_C1ISR_ISF19_Msk                         /*!<semaphore 19 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF20_Pos      (20U)
+#define HSEM_C1ISR_ISF20_Msk      (0x1UL << HSEM_C1ISR_ISF20_Pos)              /*!< 0x00100000 */
+#define HSEM_C1ISR_ISF20          HSEM_C1ISR_ISF20_Msk                         /*!<semaphore 20 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF21_Pos      (21U)
+#define HSEM_C1ISR_ISF21_Msk      (0x1UL << HSEM_C1ISR_ISF21_Pos)              /*!< 0x00200000 */
+#define HSEM_C1ISR_ISF21          HSEM_C1ISR_ISF21_Msk                         /*!<semaphore 21 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF22_Pos      (22U)
+#define HSEM_C1ISR_ISF22_Msk      (0x1UL << HSEM_C1ISR_ISF22_Pos)              /*!< 0x00400000 */
+#define HSEM_C1ISR_ISF22          HSEM_C1ISR_ISF22_Msk                         /*!<semaphore 22 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF23_Pos      (23U)
+#define HSEM_C1ISR_ISF23_Msk      (0x1UL << HSEM_C1ISR_ISF23_Pos)              /*!< 0x00800000 */
+#define HSEM_C1ISR_ISF23          HSEM_C1ISR_ISF23_Msk                         /*!<semaphore 23 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF24_Pos      (24U)
+#define HSEM_C1ISR_ISF24_Msk      (0x1UL << HSEM_C1ISR_ISF24_Pos)              /*!< 0x01000000 */
+#define HSEM_C1ISR_ISF24          HSEM_C1ISR_ISF24_Msk                         /*!<semaphore 24 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF25_Pos      (25U)
+#define HSEM_C1ISR_ISF25_Msk      (0x1UL << HSEM_C1ISR_ISF25_Pos)              /*!< 0x02000000 */
+#define HSEM_C1ISR_ISF25          HSEM_C1ISR_ISF25_Msk                         /*!<semaphore 25 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF26_Pos      (26U)
+#define HSEM_C1ISR_ISF26_Msk      (0x1UL << HSEM_C1ISR_ISF26_Pos)              /*!< 0x04000000 */
+#define HSEM_C1ISR_ISF26          HSEM_C1ISR_ISF26_Msk                         /*!<semaphore 26 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF27_Pos      (27U)
+#define HSEM_C1ISR_ISF27_Msk      (0x1UL << HSEM_C1ISR_ISF27_Pos)              /*!< 0x08000000 */
+#define HSEM_C1ISR_ISF27          HSEM_C1ISR_ISF27_Msk                         /*!<semaphore 27 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF28_Pos      (28U)
+#define HSEM_C1ISR_ISF28_Msk      (0x1UL << HSEM_C1ISR_ISF28_Pos)              /*!< 0x10000000 */
+#define HSEM_C1ISR_ISF28          HSEM_C1ISR_ISF28_Msk                         /*!<semaphore 28 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF29_Pos      (29U)
+#define HSEM_C1ISR_ISF29_Msk      (0x1UL << HSEM_C1ISR_ISF29_Pos)              /*!< 0x20000000 */
+#define HSEM_C1ISR_ISF29          HSEM_C1ISR_ISF29_Msk                         /*!<semaphore 29 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF30_Pos      (30U)
+#define HSEM_C1ISR_ISF30_Msk      (0x1UL << HSEM_C1ISR_ISF30_Pos)              /*!< 0x40000000 */
+#define HSEM_C1ISR_ISF30          HSEM_C1ISR_ISF30_Msk                         /*!<semaphore 30 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF31_Pos      (31U)
+#define HSEM_C1ISR_ISF31_Msk      (0x1UL << HSEM_C1ISR_ISF31_Pos)              /*!< 0x80000000 */
+#define HSEM_C1ISR_ISF31          HSEM_C1ISR_ISF31_Msk                         /*!<semaphore 31 interrupt 0 status bit. */
+
+/********************  Bit definition for HSEM_C1MISR register  *****************/
+#define HSEM_C1MISR_MISF0_Pos     (0U)
+#define HSEM_C1MISR_MISF0_Msk     (0x1UL << HSEM_C1MISR_MISF0_Pos)             /*!< 0x00000001 */
+#define HSEM_C1MISR_MISF0         HSEM_C1MISR_MISF0_Msk                        /*!<semaphore 0 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF1_Pos     (1U)
+#define HSEM_C1MISR_MISF1_Msk     (0x1UL << HSEM_C1MISR_MISF1_Pos)             /*!< 0x00000002 */
+#define HSEM_C1MISR_MISF1         HSEM_C1MISR_MISF1_Msk                        /*!<semaphore 1 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF2_Pos     (2U)
+#define HSEM_C1MISR_MISF2_Msk     (0x1UL << HSEM_C1MISR_MISF2_Pos)             /*!< 0x00000004 */
+#define HSEM_C1MISR_MISF2         HSEM_C1MISR_MISF2_Msk                        /*!<semaphore 2 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF3_Pos     (3U)
+#define HSEM_C1MISR_MISF3_Msk     (0x1UL << HSEM_C1MISR_MISF3_Pos)             /*!< 0x00000008 */
+#define HSEM_C1MISR_MISF3         HSEM_C1MISR_MISF3_Msk                        /*!<semaphore 3 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF4_Pos     (4U)
+#define HSEM_C1MISR_MISF4_Msk     (0x1UL << HSEM_C1MISR_MISF4_Pos)             /*!< 0x00000010 */
+#define HSEM_C1MISR_MISF4         HSEM_C1MISR_MISF4_Msk                        /*!<semaphore 4 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF5_Pos     (5U)
+#define HSEM_C1MISR_MISF5_Msk     (0x1UL << HSEM_C1MISR_MISF5_Pos)             /*!< 0x00000020 */
+#define HSEM_C1MISR_MISF5         HSEM_C1MISR_MISF5_Msk                        /*!<semaphore 5 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF6_Pos     (6U)
+#define HSEM_C1MISR_MISF6_Msk     (0x1UL << HSEM_C1MISR_MISF6_Pos)             /*!< 0x00000040 */
+#define HSEM_C1MISR_MISF6         HSEM_C1MISR_MISF6_Msk                        /*!<semaphore 6 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF7_Pos     (7U)
+#define HSEM_C1MISR_MISF7_Msk     (0x1UL << HSEM_C1MISR_MISF7_Pos)             /*!< 0x00000080 */
+#define HSEM_C1MISR_MISF7         HSEM_C1MISR_MISF7_Msk                        /*!<semaphore 7 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF8_Pos     (8U)
+#define HSEM_C1MISR_MISF8_Msk     (0x1UL << HSEM_C1MISR_MISF8_Pos)             /*!< 0x00000100 */
+#define HSEM_C1MISR_MISF8         HSEM_C1MISR_MISF8_Msk                        /*!<semaphore 8 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF9_Pos     (9U)
+#define HSEM_C1MISR_MISF9_Msk     (0x1UL << HSEM_C1MISR_MISF9_Pos)             /*!< 0x00000200 */
+#define HSEM_C1MISR_MISF9         HSEM_C1MISR_MISF9_Msk                        /*!<semaphore 9 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF10_Pos    (10U)
+#define HSEM_C1MISR_MISF10_Msk    (0x1UL << HSEM_C1MISR_MISF10_Pos)            /*!< 0x00000400 */
+#define HSEM_C1MISR_MISF10        HSEM_C1MISR_MISF10_Msk                       /*!<semaphore 10 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF11_Pos    (11U)
+#define HSEM_C1MISR_MISF11_Msk    (0x1UL << HSEM_C1MISR_MISF11_Pos)            /*!< 0x00000800 */
+#define HSEM_C1MISR_MISF11        HSEM_C1MISR_MISF11_Msk                       /*!<semaphore 11 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF12_Pos    (12U)
+#define HSEM_C1MISR_MISF12_Msk    (0x1UL << HSEM_C1MISR_MISF12_Pos)            /*!< 0x00001000 */
+#define HSEM_C1MISR_MISF12        HSEM_C1MISR_MISF12_Msk                       /*!<semaphore 12 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF13_Pos    (13U)
+#define HSEM_C1MISR_MISF13_Msk    (0x1UL << HSEM_C1MISR_MISF13_Pos)            /*!< 0x00002000 */
+#define HSEM_C1MISR_MISF13        HSEM_C1MISR_MISF13_Msk                       /*!<semaphore 13 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF14_Pos    (14U)
+#define HSEM_C1MISR_MISF14_Msk    (0x1UL << HSEM_C1MISR_MISF14_Pos)            /*!< 0x00004000 */
+#define HSEM_C1MISR_MISF14        HSEM_C1MISR_MISF14_Msk                       /*!<semaphore 14 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF15_Pos    (15U)
+#define HSEM_C1MISR_MISF15_Msk    (0x1UL << HSEM_C1MISR_MISF15_Pos)            /*!< 0x00008000 */
+#define HSEM_C1MISR_MISF15        HSEM_C1MISR_MISF15_Msk                       /*!<semaphore 15 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF16_Pos    (16U)
+#define HSEM_C1MISR_MISF16_Msk    (0x1UL << HSEM_C1MISR_MISF16_Pos)            /*!< 0x00010000 */
+#define HSEM_C1MISR_MISF16        HSEM_C1MISR_MISF16_Msk                       /*!<semaphore 16 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF17_Pos    (17U)
+#define HSEM_C1MISR_MISF17_Msk    (0x1UL << HSEM_C1MISR_MISF17_Pos)            /*!< 0x00020000 */
+#define HSEM_C1MISR_MISF17        HSEM_C1MISR_MISF17_Msk                       /*!<semaphore 17 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF18_Pos    (18U)
+#define HSEM_C1MISR_MISF18_Msk    (0x1UL << HSEM_C1MISR_MISF18_Pos)            /*!< 0x00040000 */
+#define HSEM_C1MISR_MISF18        HSEM_C1MISR_MISF18_Msk                       /*!<semaphore 18 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF19_Pos    (19U)
+#define HSEM_C1MISR_MISF19_Msk    (0x1UL << HSEM_C1MISR_MISF19_Pos)            /*!< 0x00080000 */
+#define HSEM_C1MISR_MISF19        HSEM_C1MISR_MISF19_Msk                       /*!<semaphore 19 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF20_Pos    (20U)
+#define HSEM_C1MISR_MISF20_Msk    (0x1UL << HSEM_C1MISR_MISF20_Pos)            /*!< 0x00100000 */
+#define HSEM_C1MISR_MISF20        HSEM_C1MISR_MISF20_Msk                       /*!<semaphore 20 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF21_Pos    (21U)
+#define HSEM_C1MISR_MISF21_Msk    (0x1UL << HSEM_C1MISR_MISF21_Pos)            /*!< 0x00200000 */
+#define HSEM_C1MISR_MISF21        HSEM_C1MISR_MISF21_Msk                       /*!<semaphore 21 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF22_Pos    (22U)
+#define HSEM_C1MISR_MISF22_Msk    (0x1UL << HSEM_C1MISR_MISF22_Pos)            /*!< 0x00400000 */
+#define HSEM_C1MISR_MISF22        HSEM_C1MISR_MISF22_Msk                       /*!<semaphore 22 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF23_Pos    (23U)
+#define HSEM_C1MISR_MISF23_Msk    (0x1UL << HSEM_C1MISR_MISF23_Pos)            /*!< 0x00800000 */
+#define HSEM_C1MISR_MISF23        HSEM_C1MISR_MISF23_Msk                       /*!<semaphore 23 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF24_Pos    (24U)
+#define HSEM_C1MISR_MISF24_Msk    (0x1UL << HSEM_C1MISR_MISF24_Pos)            /*!< 0x01000000 */
+#define HSEM_C1MISR_MISF24        HSEM_C1MISR_MISF24_Msk                       /*!<semaphore 24 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF25_Pos    (25U)
+#define HSEM_C1MISR_MISF25_Msk    (0x1UL << HSEM_C1MISR_MISF25_Pos)            /*!< 0x02000000 */
+#define HSEM_C1MISR_MISF25        HSEM_C1MISR_MISF25_Msk                       /*!<semaphore 25 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF26_Pos    (26U)
+#define HSEM_C1MISR_MISF26_Msk    (0x1UL << HSEM_C1MISR_MISF26_Pos)            /*!< 0x04000000 */
+#define HSEM_C1MISR_MISF26        HSEM_C1MISR_MISF26_Msk                       /*!<semaphore 26 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF27_Pos    (27U)
+#define HSEM_C1MISR_MISF27_Msk    (0x1UL << HSEM_C1MISR_MISF27_Pos)            /*!< 0x08000000 */
+#define HSEM_C1MISR_MISF27        HSEM_C1MISR_MISF27_Msk                       /*!<semaphore 27 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF28_Pos    (28U)
+#define HSEM_C1MISR_MISF28_Msk    (0x1UL << HSEM_C1MISR_MISF28_Pos)            /*!< 0x10000000 */
+#define HSEM_C1MISR_MISF28        HSEM_C1MISR_MISF28_Msk                       /*!<semaphore 28 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF29_Pos    (29U)
+#define HSEM_C1MISR_MISF29_Msk    (0x1UL << HSEM_C1MISR_MISF29_Pos)            /*!< 0x20000000 */
+#define HSEM_C1MISR_MISF29        HSEM_C1MISR_MISF29_Msk                       /*!<semaphore 29 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF30_Pos    (30U)
+#define HSEM_C1MISR_MISF30_Msk    (0x1UL << HSEM_C1MISR_MISF30_Pos)            /*!< 0x40000000 */
+#define HSEM_C1MISR_MISF30        HSEM_C1MISR_MISF30_Msk                       /*!<semaphore 30 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF31_Pos    (31U)
+#define HSEM_C1MISR_MISF31_Msk    (0x1UL << HSEM_C1MISR_MISF31_Pos)            /*!< 0x80000000 */
+#define HSEM_C1MISR_MISF31        HSEM_C1MISR_MISF31_Msk                       /*!<semaphore 31 interrupt 0 masked status bit. */
+
+/********************  Bit definition for HSEM_CR register  *****************/
+#define HSEM_CR_COREID_Pos        (8U)
+#define HSEM_CR_COREID_Msk        (0xFFUL << HSEM_CR_COREID_Pos)               /*!< 0x0000FF00 */
+#define HSEM_CR_COREID            HSEM_CR_COREID_Msk                           /*!<CoreID of semaphores to be cleared. */
+#define HSEM_CR_KEY_Pos           (16U)
+#define HSEM_CR_KEY_Msk           (0xFFFFUL << HSEM_CR_KEY_Pos)                /*!< 0xFFFF0000 */
+#define HSEM_CR_KEY               HSEM_CR_KEY_Msk                              /*!<semaphores clear key. */
+
+/********************  Bit definition for HSEM_KEYR register  *****************/
+#define HSEM_KEYR_KEY_Pos         (16U)
+#define HSEM_KEYR_KEY_Msk         (0xFFFFUL << HSEM_KEYR_KEY_Pos)              /*!< 0xFFFF0000 */
+#define HSEM_KEYR_KEY             HSEM_KEYR_KEY_Msk                            /*!<semaphores clear key. */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Inter-integrated Circuit Interface (I2C)              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for I2C_CR1 register  *******************/
+#define I2C_CR1_PE_Pos               (0U)
+#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                 /*!< 0x00000001 */
+#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */
+#define I2C_CR1_TXIE_Pos             (1U)
+#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)               /*!< 0x00000002 */
+#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */
+#define I2C_CR1_RXIE_Pos             (2U)
+#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)               /*!< 0x00000004 */
+#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE_Pos           (3U)
+#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)             /*!< 0x00000008 */
+#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE_Pos           (4U)
+#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)             /*!< 0x00000010 */
+#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE_Pos           (5U)
+#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)             /*!< 0x00000020 */
+#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE_Pos             (6U)
+#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)               /*!< 0x00000040 */
+#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE_Pos            (7U)
+#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)              /*!< 0x00000080 */
+#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */
+#define I2C_CR1_DNF_Pos              (8U)
+#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                /*!< 0x00000F00 */
+#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF_Pos           (12U)
+#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)             /*!< 0x00001000 */
+#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */
+#define I2C_CR1_TXDMAEN_Pos          (14U)
+#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)            /*!< 0x00004000 */
+#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN_Pos          (15U)
+#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)            /*!< 0x00008000 */
+#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */
+#define I2C_CR1_SBC_Pos              (16U)
+#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                /*!< 0x00010000 */
+#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH_Pos        (17U)
+#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)          /*!< 0x00020000 */
+#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN_Pos            (18U)
+#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)              /*!< 0x00040000 */
+#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN_Pos             (19U)
+#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)               /*!< 0x00080000 */
+#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */
+#define I2C_CR1_SMBHEN_Pos           (20U)
+#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)             /*!< 0x00100000 */
+#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN_Pos           (21U)
+#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)             /*!< 0x00200000 */
+#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN_Pos          (22U)
+#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)            /*!< 0x00400000 */
+#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */
+#define I2C_CR1_PECEN_Pos            (23U)
+#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)              /*!< 0x00800000 */
+#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */
+
+/******************  Bit definition for I2C_CR2 register  ********************/
+#define I2C_CR2_SADD_Pos             (0U)
+#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)             /*!< 0x000003FF */
+#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN_Pos           (10U)
+#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)             /*!< 0x00000400 */
+#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10_Pos            (11U)
+#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)              /*!< 0x00000800 */
+#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R_Pos          (12U)
+#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)            /*!< 0x00001000 */
+#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START_Pos            (13U)
+#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)              /*!< 0x00002000 */
+#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */
+#define I2C_CR2_STOP_Pos             (14U)
+#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)               /*!< 0x00004000 */
+#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK_Pos             (15U)
+#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)               /*!< 0x00008000 */
+#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES_Pos           (16U)
+#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)            /*!< 0x00FF0000 */
+#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */
+#define I2C_CR2_RELOAD_Pos           (24U)
+#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)             /*!< 0x01000000 */
+#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND_Pos          (25U)
+#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)            /*!< 0x02000000 */
+#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE_Pos          (26U)
+#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)            /*!< 0x04000000 */
+#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */
+
+/*******************  Bit definition for I2C_OAR1 register  ******************/
+#define I2C_OAR1_OA1_Pos             (0U)
+#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)             /*!< 0x000003FF */
+#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE_Pos         (10U)
+#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)           /*!< 0x00000400 */
+#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN_Pos           (15U)
+#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)             /*!< 0x00008000 */
+#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */
+
+/*******************  Bit definition for I2C_OAR2 register  ******************/
+#define I2C_OAR2_OA2_Pos             (1U)
+#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)              /*!< 0x000000FE */
+#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK_Pos          (8U)
+#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)            /*!< 0x00000700 */
+#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK           0x00000000UL                              /*!< No mask */
+#define I2C_OAR2_OA2MASK01_Pos       (8U)
+#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)         /*!< 0x00000100 */
+#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02_Pos       (9U)
+#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)         /*!< 0x00000200 */
+#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03_Pos       (8U)
+#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)         /*!< 0x00000300 */
+#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04_Pos       (10U)
+#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)         /*!< 0x00000400 */
+#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05_Pos       (8U)
+#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)         /*!< 0x00000500 */
+#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06_Pos       (9U)
+#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)         /*!< 0x00000600 */
+#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07_Pos       (8U)
+#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)         /*!< 0x00000700 */
+#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN_Pos           (15U)
+#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)             /*!< 0x00008000 */
+#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable */
+
+/*******************  Bit definition for I2C_TIMINGR register *******************/
+#define I2C_TIMINGR_SCLL_Pos         (0U)
+#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)          /*!< 0x000000FF */
+#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH_Pos         (8U)
+#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)          /*!< 0x0000FF00 */
+#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL_Pos       (16U)
+#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)         /*!< 0x000F0000 */
+#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL_Pos       (20U)
+#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)         /*!< 0x00F00000 */
+#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */
+#define I2C_TIMINGR_PRESC_Pos        (28U)
+#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)          /*!< 0xF0000000 */
+#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)
+#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)    /*!< 0x00000FFF */
+#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE_Pos       (12U)
+#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)         /*!< 0x00001000 */
+#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)
+#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)      /*!< 0x00008000 */
+#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)
+#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)    /*!< 0x0FFF0000 */
+#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)
+#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)        /*!< 0x80000000 */
+#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
+
+/******************  Bit definition for I2C_ISR register  *********************/
+#define I2C_ISR_TXE_Pos              (0U)
+#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                /*!< 0x00000001 */
+#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */
+#define I2C_ISR_TXIS_Pos             (1U)
+#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)               /*!< 0x00000002 */
+#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE_Pos             (2U)
+#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)               /*!< 0x00000004 */
+#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
+#define I2C_ISR_ADDR_Pos             (3U)
+#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)               /*!< 0x00000008 */
+#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF_Pos            (4U)
+#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)              /*!< 0x00000010 */
+#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */
+#define I2C_ISR_STOPF_Pos            (5U)
+#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)              /*!< 0x00000020 */
+#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */
+#define I2C_ISR_TC_Pos               (6U)
+#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                 /*!< 0x00000040 */
+#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR_Pos              (7U)
+#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                /*!< 0x00000080 */
+#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */
+#define I2C_ISR_BERR_Pos             (8U)
+#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)               /*!< 0x00000100 */
+#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */
+#define I2C_ISR_ARLO_Pos             (9U)
+#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)               /*!< 0x00000200 */
+#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */
+#define I2C_ISR_OVR_Pos              (10U)
+#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                /*!< 0x00000400 */
+#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR_Pos           (11U)
+#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)             /*!< 0x00000800 */
+#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT_Pos          (12U)
+#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)            /*!< 0x00001000 */
+#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT_Pos            (13U)
+#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)              /*!< 0x00002000 */
+#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */
+#define I2C_ISR_BUSY_Pos             (15U)
+#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)               /*!< 0x00008000 */
+#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */
+#define I2C_ISR_DIR_Pos              (16U)
+#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                /*!< 0x00010000 */
+#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE_Pos          (17U)
+#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)           /*!< 0x00FE0000 */
+#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
+
+/******************  Bit definition for I2C_ICR register  *********************/
+#define I2C_ICR_ADDRCF_Pos           (3U)
+#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)             /*!< 0x00000008 */
+#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF_Pos           (4U)
+#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)             /*!< 0x00000010 */
+#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */
+#define I2C_ICR_STOPCF_Pos           (5U)
+#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)             /*!< 0x00000020 */
+#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF_Pos           (8U)
+#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)             /*!< 0x00000100 */
+#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF_Pos           (9U)
+#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)             /*!< 0x00000200 */
+#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF_Pos            (10U)
+#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)              /*!< 0x00000400 */
+#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF_Pos            (11U)
+#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)              /*!< 0x00000800 */
+#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF_Pos         (12U)
+#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)           /*!< 0x00001000 */
+#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF_Pos          (13U)
+#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)            /*!< 0x00002000 */
+#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */
+
+/******************  Bit definition for I2C_PECR register  *********************/
+#define I2C_PECR_PEC_Pos             (0U)
+#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)              /*!< 0x000000FF */
+#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
+
+/******************  Bit definition for I2C_RXDR register  *********************/
+#define I2C_RXDR_RXDATA_Pos          (0U)
+#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)           /*!< 0x000000FF */
+#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
+
+/******************  Bit definition for I2C_TXDR register  *********************/
+#define I2C_TXDR_TXDATA_Pos          (0U)
+#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)           /*!< 0x000000FF */
+#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Independent WATCHDOG                             */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define IWDG_KR_KEY_Pos      (0U)
+#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                     /*!< 0x0000FFFF */
+#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define IWDG_PR_PR_Pos       (0U)
+#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                         /*!< 0x00000007 */
+#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */
+#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */
+#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */
+#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define IWDG_RLR_RL_Pos      (0U)
+#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                      /*!< 0x00000FFF */
+#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define IWDG_SR_PVU_Pos      (0U)
+#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                        /*!< 0x00000001 */
+#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos      (1U)
+#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                        /*!< 0x00000002 */
+#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU_Pos      (2U)
+#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                        /*!< 0x00000004 */
+#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
+
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define IWDG_WINR_WIN_Pos    (0U)
+#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                    /*!< 0x00000FFF */
+#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        JPEG Encoder/Decoder                                */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for CONFR0 register  ********************/
+#define JPEG_CONFR0_START_Pos           (0U)
+#define JPEG_CONFR0_START_Msk           (0x1UL << JPEG_CONFR0_START_Pos)       /*!< 0x00000001 */
+#define JPEG_CONFR0_START               JPEG_CONFR0_START_Msk                  /*!<Start/Stop bit */
+
+/********************  Bit definition for CONFR1 register  ********************/
+#define JPEG_CONFR1_NF_Pos              (0U)
+#define JPEG_CONFR1_NF_Msk              (0x3UL << JPEG_CONFR1_NF_Pos)          /*!< 0x00000003 */
+#define JPEG_CONFR1_NF                  JPEG_CONFR1_NF_Msk                     /*!<Number of color components */
+#define JPEG_CONFR1_NF_0                (0x1UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000001 */
+#define JPEG_CONFR1_NF_1                (0x2UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000002 */
+#define JPEG_CONFR1_DE_Pos              (3U)
+#define JPEG_CONFR1_DE_Msk              (0x1UL << JPEG_CONFR1_DE_Pos)          /*!< 0x00000008 */
+#define JPEG_CONFR1_DE                  JPEG_CONFR1_DE_Msk                     /*!<Decoding Enable */
+#define JPEG_CONFR1_COLORSPACE_Pos      (4U)
+#define JPEG_CONFR1_COLORSPACE_Msk      (0x3UL << JPEG_CONFR1_COLORSPACE_Pos)  /*!< 0x00000030 */
+#define JPEG_CONFR1_COLORSPACE          JPEG_CONFR1_COLORSPACE_Msk             /*!<Color Space */
+#define JPEG_CONFR1_COLORSPACE_0        (0x1UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000010 */
+#define JPEG_CONFR1_COLORSPACE_1        (0x2UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000020 */
+#define JPEG_CONFR1_NS_Pos              (6U)
+#define JPEG_CONFR1_NS_Msk              (0x3UL << JPEG_CONFR1_NS_Pos)          /*!< 0x000000C0 */
+#define JPEG_CONFR1_NS                  JPEG_CONFR1_NS_Msk                     /*!<Number of components for Scan */
+#define JPEG_CONFR1_NS_0                (0x1UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000040 */
+#define JPEG_CONFR1_NS_1                (0x2UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000080 */
+#define JPEG_CONFR1_HDR_Pos             (8U)
+#define JPEG_CONFR1_HDR_Msk             (0x1UL << JPEG_CONFR1_HDR_Pos)         /*!< 0x00000100 */
+#define JPEG_CONFR1_HDR                 JPEG_CONFR1_HDR_Msk                    /*!<Header Processing On/Off */
+#define JPEG_CONFR1_YSIZE_Pos           (16U)
+#define JPEG_CONFR1_YSIZE_Msk           (0xFFFFUL << JPEG_CONFR1_YSIZE_Pos)    /*!< 0xFFFF0000 */
+#define JPEG_CONFR1_YSIZE               JPEG_CONFR1_YSIZE_Msk                  /*!<Number of lines in source image */
+
+/********************  Bit definition for CONFR2 register  ********************/
+#define JPEG_CONFR2_NMCU_Pos            (0U)
+#define JPEG_CONFR2_NMCU_Msk            (0x3FFFFFFUL << JPEG_CONFR2_NMCU_Pos)  /*!< 0x03FFFFFF */
+#define JPEG_CONFR2_NMCU                JPEG_CONFR2_NMCU_Msk                   /*!<Number of MCU units minus 1 to encode */
+
+/********************  Bit definition for CONFR3 register  ********************/
+#define JPEG_CONFR3_XSIZE_Pos           (16U)
+#define JPEG_CONFR3_XSIZE_Msk           (0xFFFFUL << JPEG_CONFR3_XSIZE_Pos)    /*!< 0xFFFF0000 */
+#define JPEG_CONFR3_XSIZE               JPEG_CONFR3_XSIZE_Msk                  /*!<Number of pixels per line */
+
+/********************  Bit definition for CONFR4 register  ********************/
+#define JPEG_CONFR4_HD_Pos              (0U)
+#define JPEG_CONFR4_HD_Msk              (0x1UL << JPEG_CONFR4_HD_Pos)          /*!< 0x00000001 */
+#define JPEG_CONFR4_HD                  JPEG_CONFR4_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */
+#define JPEG_CONFR4_HA_Pos              (1U)
+#define JPEG_CONFR4_HA_Msk              (0x1UL << JPEG_CONFR4_HA_Pos)          /*!< 0x00000002 */
+#define JPEG_CONFR4_HA                  JPEG_CONFR4_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */
+#define JPEG_CONFR4_QT_Pos              (2U)
+#define JPEG_CONFR4_QT_Msk              (0x3UL << JPEG_CONFR4_QT_Pos)          /*!< 0x0000000C */
+#define JPEG_CONFR4_QT                  JPEG_CONFR4_QT_Msk                     /*!<Selects quantization table associated with a color component */
+#define JPEG_CONFR4_QT_0                (0x1UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000004 */
+#define JPEG_CONFR4_QT_1                (0x2UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000008 */
+#define JPEG_CONFR4_NB_Pos              (4U)
+#define JPEG_CONFR4_NB_Msk              (0xFUL << JPEG_CONFR4_NB_Pos)          /*!< 0x000000F0 */
+#define JPEG_CONFR4_NB                  JPEG_CONFR4_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */
+#define JPEG_CONFR4_NB_0                (0x1UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000010 */
+#define JPEG_CONFR4_NB_1                (0x2UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000020 */
+#define JPEG_CONFR4_NB_2                (0x4UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000040 */
+#define JPEG_CONFR4_NB_3                (0x8UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000080 */
+#define JPEG_CONFR4_VSF_Pos             (8U)
+#define JPEG_CONFR4_VSF_Msk             (0xFUL << JPEG_CONFR4_VSF_Pos)         /*!< 0x00000F00 */
+#define JPEG_CONFR4_VSF                 JPEG_CONFR4_VSF_Msk                    /*!<Vertical sampling factor for component 1 */
+#define JPEG_CONFR4_VSF_0               (0x1UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000100 */
+#define JPEG_CONFR4_VSF_1               (0x2UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000200 */
+#define JPEG_CONFR4_VSF_2               (0x4UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000400 */
+#define JPEG_CONFR4_VSF_3               (0x8UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000800 */
+#define JPEG_CONFR4_HSF_Pos             (12U)
+#define JPEG_CONFR4_HSF_Msk             (0xFUL << JPEG_CONFR4_HSF_Pos)         /*!< 0x0000F000 */
+#define JPEG_CONFR4_HSF                 JPEG_CONFR4_HSF_Msk                    /*!<Horizontal sampling factor for component 1 */
+#define JPEG_CONFR4_HSF_0               (0x1UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00001000 */
+#define JPEG_CONFR4_HSF_1               (0x2UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00002000 */
+#define JPEG_CONFR4_HSF_2               (0x4UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00004000 */
+#define JPEG_CONFR4_HSF_3               (0x8UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00008000 */
+
+/********************  Bit definition for CONFR5 register  ********************/
+#define JPEG_CONFR5_HD_Pos              (0U)
+#define JPEG_CONFR5_HD_Msk              (0x1UL << JPEG_CONFR5_HD_Pos)          /*!< 0x00000001 */
+#define JPEG_CONFR5_HD                  JPEG_CONFR5_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */
+#define JPEG_CONFR5_HA_Pos              (1U)
+#define JPEG_CONFR5_HA_Msk              (0x1UL << JPEG_CONFR5_HA_Pos)          /*!< 0x00000002 */
+#define JPEG_CONFR5_HA                  JPEG_CONFR5_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */
+#define JPEG_CONFR5_QT_Pos              (2U)
+#define JPEG_CONFR5_QT_Msk              (0x3UL << JPEG_CONFR5_QT_Pos)          /*!< 0x0000000C */
+#define JPEG_CONFR5_QT                  JPEG_CONFR5_QT_Msk                     /*!<Selects quantization table associated with a color component */
+#define JPEG_CONFR5_QT_0                (0x1UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000004 */
+#define JPEG_CONFR5_QT_1                (0x2UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000008 */
+#define JPEG_CONFR5_NB_Pos              (4U)
+#define JPEG_CONFR5_NB_Msk              (0xFUL << JPEG_CONFR5_NB_Pos)          /*!< 0x000000F0 */
+#define JPEG_CONFR5_NB                  JPEG_CONFR5_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */
+#define JPEG_CONFR5_NB_0                (0x1UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000010 */
+#define JPEG_CONFR5_NB_1                (0x2UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000020 */
+#define JPEG_CONFR5_NB_2                (0x4UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000040 */
+#define JPEG_CONFR5_NB_3                (0x8UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000080 */
+#define JPEG_CONFR5_VSF_Pos             (8U)
+#define JPEG_CONFR5_VSF_Msk             (0xFUL << JPEG_CONFR5_VSF_Pos)         /*!< 0x00000F00 */
+#define JPEG_CONFR5_VSF                 JPEG_CONFR5_VSF_Msk                    /*!<Vertical sampling factor for component 2 */
+#define JPEG_CONFR5_VSF_0               (0x1UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000100 */
+#define JPEG_CONFR5_VSF_1               (0x2UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000200 */
+#define JPEG_CONFR5_VSF_2               (0x4UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000400 */
+#define JPEG_CONFR5_VSF_3               (0x8UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000800 */
+#define JPEG_CONFR5_HSF_Pos             (12U)
+#define JPEG_CONFR5_HSF_Msk             (0xFUL << JPEG_CONFR5_HSF_Pos)         /*!< 0x0000F000 */
+#define JPEG_CONFR5_HSF                 JPEG_CONFR5_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */
+#define JPEG_CONFR5_HSF_0               (0x1UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00001000 */
+#define JPEG_CONFR5_HSF_1               (0x2UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00002000 */
+#define JPEG_CONFR5_HSF_2               (0x4UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00004000 */
+#define JPEG_CONFR5_HSF_3               (0x8UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00008000 */
+
+/********************  Bit definition for CONFR6 register  ********************/
+#define JPEG_CONFR6_HD_Pos              (0U)
+#define JPEG_CONFR6_HD_Msk              (0x1UL << JPEG_CONFR6_HD_Pos)          /*!< 0x00000001 */
+#define JPEG_CONFR6_HD                  JPEG_CONFR6_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */
+#define JPEG_CONFR6_HA_Pos              (1U)
+#define JPEG_CONFR6_HA_Msk              (0x1UL << JPEG_CONFR6_HA_Pos)          /*!< 0x00000002 */
+#define JPEG_CONFR6_HA                  JPEG_CONFR6_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */
+#define JPEG_CONFR6_QT_Pos              (2U)
+#define JPEG_CONFR6_QT_Msk              (0x3UL << JPEG_CONFR6_QT_Pos)          /*!< 0x0000000C */
+#define JPEG_CONFR6_QT                  JPEG_CONFR6_QT_Msk                     /*!<Selects quantization table associated with a color component */
+#define JPEG_CONFR6_QT_0                (0x1UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000004 */
+#define JPEG_CONFR6_QT_1                (0x2UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000008 */
+#define JPEG_CONFR6_NB_Pos              (4U)
+#define JPEG_CONFR6_NB_Msk              (0xFUL << JPEG_CONFR6_NB_Pos)          /*!< 0x000000F0 */
+#define JPEG_CONFR6_NB                  JPEG_CONFR6_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */
+#define JPEG_CONFR6_NB_0                (0x1UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000010 */
+#define JPEG_CONFR6_NB_1                (0x2UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000020 */
+#define JPEG_CONFR6_NB_2                (0x4UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000040 */
+#define JPEG_CONFR6_NB_3                (0x8UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000080 */
+#define JPEG_CONFR6_VSF_Pos             (8U)
+#define JPEG_CONFR6_VSF_Msk             (0xFUL << JPEG_CONFR6_VSF_Pos)         /*!< 0x00000F00 */
+#define JPEG_CONFR6_VSF                 JPEG_CONFR6_VSF_Msk                    /*!<Vertical sampling factor for component 2 */
+#define JPEG_CONFR6_VSF_0               (0x1UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000100 */
+#define JPEG_CONFR6_VSF_1               (0x2UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000200 */
+#define JPEG_CONFR6_VSF_2               (0x4UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000400 */
+#define JPEG_CONFR6_VSF_3               (0x8UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000800 */
+#define JPEG_CONFR6_HSF_Pos             (12U)
+#define JPEG_CONFR6_HSF_Msk             (0xFUL << JPEG_CONFR6_HSF_Pos)         /*!< 0x0000F000 */
+#define JPEG_CONFR6_HSF                 JPEG_CONFR6_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */
+#define JPEG_CONFR6_HSF_0               (0x1UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00001000 */
+#define JPEG_CONFR6_HSF_1               (0x2UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00002000 */
+#define JPEG_CONFR6_HSF_2               (0x4UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00004000 */
+#define JPEG_CONFR6_HSF_3               (0x8UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00008000 */
+
+/********************  Bit definition for CONFR7 register  ********************/
+#define JPEG_CONFR7_HD_Pos              (0U)
+#define JPEG_CONFR7_HD_Msk              (0x1UL << JPEG_CONFR7_HD_Pos)          /*!< 0x00000001 */
+#define JPEG_CONFR7_HD                  JPEG_CONFR7_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */
+#define JPEG_CONFR7_HA_Pos              (1U)
+#define JPEG_CONFR7_HA_Msk              (0x1UL << JPEG_CONFR7_HA_Pos)          /*!< 0x00000002 */
+#define JPEG_CONFR7_HA                  JPEG_CONFR7_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */
+#define JPEG_CONFR7_QT_Pos              (2U)
+#define JPEG_CONFR7_QT_Msk              (0x3UL << JPEG_CONFR7_QT_Pos)          /*!< 0x0000000C */
+#define JPEG_CONFR7_QT                  JPEG_CONFR7_QT_Msk                     /*!<Selects quantization table associated with a color component */
+#define JPEG_CONFR7_QT_0                (0x1UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000004 */
+#define JPEG_CONFR7_QT_1                (0x2UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000008 */
+#define JPEG_CONFR7_NB_Pos              (4U)
+#define JPEG_CONFR7_NB_Msk              (0xFUL << JPEG_CONFR7_NB_Pos)          /*!< 0x000000F0 */
+#define JPEG_CONFR7_NB                  JPEG_CONFR7_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */
+#define JPEG_CONFR7_NB_0                (0x1UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000010 */
+#define JPEG_CONFR7_NB_1                (0x2UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000020 */
+#define JPEG_CONFR7_NB_2                (0x4UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000040 */
+#define JPEG_CONFR7_NB_3                (0x8UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000080 */
+#define JPEG_CONFR7_VSF_Pos             (8U)
+#define JPEG_CONFR7_VSF_Msk             (0xFUL << JPEG_CONFR7_VSF_Pos)         /*!< 0x00000F00 */
+#define JPEG_CONFR7_VSF                 JPEG_CONFR7_VSF_Msk                    /*!<Vertical sampling factor for component 2 */
+#define JPEG_CONFR7_VSF_0               (0x1UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000100 */
+#define JPEG_CONFR7_VSF_1               (0x2UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000200 */
+#define JPEG_CONFR7_VSF_2               (0x4UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000400 */
+#define JPEG_CONFR7_VSF_3               (0x8UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000800 */
+#define JPEG_CONFR7_HSF_Pos             (12U)
+#define JPEG_CONFR7_HSF_Msk             (0xFUL << JPEG_CONFR7_HSF_Pos)         /*!< 0x0000F000 */
+#define JPEG_CONFR7_HSF                 JPEG_CONFR7_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */
+#define JPEG_CONFR7_HSF_0               (0x1UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00001000 */
+#define JPEG_CONFR7_HSF_1               (0x2UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00002000 */
+#define JPEG_CONFR7_HSF_2               (0x4UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00004000 */
+#define JPEG_CONFR7_HSF_3               (0x8UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00008000 */
+
+/********************  Bit definition for CR register  ********************/
+#define JPEG_CR_JCEN_Pos                (0U)
+#define JPEG_CR_JCEN_Msk                (0x1UL << JPEG_CR_JCEN_Pos)            /*!< 0x00000001 */
+#define JPEG_CR_JCEN                    JPEG_CR_JCEN_Msk                       /*!<Enable the JPEG Codec Core */
+#define JPEG_CR_IFTIE_Pos               (1U)
+#define JPEG_CR_IFTIE_Msk               (0x1UL << JPEG_CR_IFTIE_Pos)           /*!< 0x00000002 */
+#define JPEG_CR_IFTIE                   JPEG_CR_IFTIE_Msk                      /*!<Input FIFO Threshold Interrupt Enable */
+#define JPEG_CR_IFNFIE_Pos              (2U)
+#define JPEG_CR_IFNFIE_Msk              (0x1UL << JPEG_CR_IFNFIE_Pos)          /*!< 0x00000004 */
+#define JPEG_CR_IFNFIE                  JPEG_CR_IFNFIE_Msk                     /*!<Input FIFO Not Full Interrupt Enable */
+#define JPEG_CR_OFTIE_Pos               (3U)
+#define JPEG_CR_OFTIE_Msk               (0x1UL << JPEG_CR_OFTIE_Pos)           /*!< 0x00000008 */
+#define JPEG_CR_OFTIE                   JPEG_CR_OFTIE_Msk                      /*!<Output FIFO Threshold Interrupt Enable */
+#define JPEG_CR_OFNEIE_Pos              (4U)
+#define JPEG_CR_OFNEIE_Msk              (0x1UL << JPEG_CR_OFNEIE_Pos)          /*!< 0x00000010 */
+#define JPEG_CR_OFNEIE                  JPEG_CR_OFNEIE_Msk                     /*!<Output FIFO Not Empty Interrupt Enable */
+#define JPEG_CR_EOCIE_Pos               (5U)
+#define JPEG_CR_EOCIE_Msk               (0x1UL << JPEG_CR_EOCIE_Pos)           /*!< 0x00000020 */
+#define JPEG_CR_EOCIE                   JPEG_CR_EOCIE_Msk                      /*!<End of Conversion Interrupt Enable */
+#define JPEG_CR_HPDIE_Pos               (6U)
+#define JPEG_CR_HPDIE_Msk               (0x1UL << JPEG_CR_HPDIE_Pos)           /*!< 0x00000040 */
+#define JPEG_CR_HPDIE                   JPEG_CR_HPDIE_Msk                      /*!<Header Parsing Done Interrupt Enable */
+#define JPEG_CR_IFF_Pos                 (13U)
+#define JPEG_CR_IFF_Msk                 (0x1UL << JPEG_CR_IFF_Pos)             /*!< 0x00002000 */
+#define JPEG_CR_IFF                     JPEG_CR_IFF_Msk                        /*!<Flush the input FIFO */
+#define JPEG_CR_OFF_Pos                 (14U)
+#define JPEG_CR_OFF_Msk                 (0x1UL << JPEG_CR_OFF_Pos)             /*!< 0x00004000 */
+#define JPEG_CR_OFF                     JPEG_CR_OFF_Msk                        /*!<Flush the output FIFO */
+
+/********************  Bit definition for SR register  ********************/
+#define JPEG_SR_IFTF_Pos                (1U)
+#define JPEG_SR_IFTF_Msk                (0x1UL << JPEG_SR_IFTF_Pos)            /*!< 0x00000002 */
+#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is bellow its threshold flag */
+#define JPEG_SR_IFNFF_Pos               (2U)
+#define JPEG_SR_IFNFF_Msk               (0x1UL << JPEG_SR_IFNFF_Pos)           /*!< 0x00000004 */
+#define JPEG_SR_IFNFF                   JPEG_SR_IFNFF_Msk                      /*!<Input FIFO Not Full Flag, a data can be written */
+#define JPEG_SR_OFTF_Pos                (3U)
+#define JPEG_SR_OFTF_Msk                (0x1UL << JPEG_SR_OFTF_Pos)            /*!< 0x00000008 */
+#define JPEG_SR_OFTF                    JPEG_SR_OFTF_Msk                       /*!<Output FIFO is not empty and has reach its threshold */
+#define JPEG_SR_OFNEF_Pos               (4U)
+#define JPEG_SR_OFNEF_Msk               (0x1UL << JPEG_SR_OFNEF_Pos)           /*!< 0x00000010 */
+#define JPEG_SR_OFNEF                   JPEG_SR_OFNEF_Msk                      /*!<Output FIFO is not empty, a data is available */
+#define JPEG_SR_EOCF_Pos                (5U)
+#define JPEG_SR_EOCF_Msk                (0x1UL << JPEG_SR_EOCF_Pos)            /*!< 0x00000020 */
+#define JPEG_SR_EOCF                    JPEG_SR_EOCF_Msk                       /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */
+#define JPEG_SR_HPDF_Pos                (6U)
+#define JPEG_SR_HPDF_Msk                (0x1UL << JPEG_SR_HPDF_Pos)            /*!< 0x00000040 */
+#define JPEG_SR_HPDF                    JPEG_SR_HPDF_Msk                       /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */
+#define JPEG_SR_COF_Pos                 (7U)
+#define JPEG_SR_COF_Msk                 (0x1UL << JPEG_SR_COF_Pos)             /*!< 0x00000080 */
+#define JPEG_SR_COF                     JPEG_SR_COF_Msk                        /*!<JPEG Codec operation on going flag */
+
+/********************  Bit definition for CFR register  ********************/
+#define JPEG_CFR_CEOCF_Pos              (4U)
+#define JPEG_CFR_CEOCF_Msk              (0x1UL << JPEG_CFR_CEOCF_Pos)          /*!< 0x00000010 */
+#define JPEG_CFR_CEOCF                  JPEG_CFR_CEOCF_Msk                     /*!<Clear End of Conversion Flag */
+#define JPEG_CFR_CHPDF_Pos              (5U)
+#define JPEG_CFR_CHPDF_Msk              (0x1UL << JPEG_CFR_CHPDF_Pos)          /*!< 0x00000020 */
+#define JPEG_CFR_CHPDF                  JPEG_CFR_CHPDF_Msk                     /*!<Clear Header Parsing Done Flag */
+
+/********************  Bit definition for DIR register  ********************/
+#define JPEG_DIR_DATAIN_Pos             (0U)
+#define JPEG_DIR_DATAIN_Msk             (0xFFFFFFFFUL << JPEG_DIR_DATAIN_Pos)  /*!< 0xFFFFFFFF */
+#define JPEG_DIR_DATAIN                 JPEG_DIR_DATAIN_Msk                    /*!<Data Input FIFO */
+
+/********************  Bit definition for DOR register  ********************/
+#define JPEG_DOR_DATAOUT_Pos            (0U)
+#define JPEG_DOR_DATAOUT_Msk            (0xFFFFFFFFUL << JPEG_DOR_DATAOUT_Pos) /*!< 0xFFFFFFFF */
+#define JPEG_DOR_DATAOUT                JPEG_DOR_DATAOUT_Msk                   /*!<Data Output FIFO */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      LCD-TFT Display Controller (LTDC)                     */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for LTDC_SSCR register  *****************/
+
+#define LTDC_SSCR_VSH_Pos            (0U)
+#define LTDC_SSCR_VSH_Msk            (0x7FFUL << LTDC_SSCR_VSH_Pos)            /*!< 0x000007FF */
+#define LTDC_SSCR_VSH                LTDC_SSCR_VSH_Msk                         /*!< Vertical Synchronization Height  */
+#define LTDC_SSCR_HSW_Pos            (16U)
+#define LTDC_SSCR_HSW_Msk            (0xFFFUL << LTDC_SSCR_HSW_Pos)            /*!< 0x0FFF0000 */
+#define LTDC_SSCR_HSW                LTDC_SSCR_HSW_Msk                         /*!< Horizontal Synchronization Width */
+
+/********************  Bit definition for LTDC_BPCR register  *****************/
+
+#define LTDC_BPCR_AVBP_Pos           (0U)
+#define LTDC_BPCR_AVBP_Msk           (0x7FFUL << LTDC_BPCR_AVBP_Pos)           /*!< 0x000007FF */
+#define LTDC_BPCR_AVBP               LTDC_BPCR_AVBP_Msk                        /*!< Accumulated Vertical Back Porch   */
+#define LTDC_BPCR_AHBP_Pos           (16U)
+#define LTDC_BPCR_AHBP_Msk           (0xFFFUL << LTDC_BPCR_AHBP_Pos)           /*!< 0x0FFF0000 */
+#define LTDC_BPCR_AHBP               LTDC_BPCR_AHBP_Msk                        /*!< Accumulated Horizontal Back Porch */
+
+/********************  Bit definition for LTDC_AWCR register  *****************/
+
+#define LTDC_AWCR_AAH_Pos            (0U)
+#define LTDC_AWCR_AAH_Msk            (0x7FFUL << LTDC_AWCR_AAH_Pos)            /*!< 0x000007FF */
+#define LTDC_AWCR_AAH                LTDC_AWCR_AAH_Msk                         /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAW_Pos            (16U)
+#define LTDC_AWCR_AAW_Msk            (0xFFFUL << LTDC_AWCR_AAW_Pos)            /*!< 0x0FFF0000 */
+#define LTDC_AWCR_AAW                LTDC_AWCR_AAW_Msk                         /*!< Accumulated Active Width */
+
+/********************  Bit definition for LTDC_TWCR register  *****************/
+
+#define LTDC_TWCR_TOTALH_Pos         (0U)
+#define LTDC_TWCR_TOTALH_Msk         (0x7FFUL << LTDC_TWCR_TOTALH_Pos)         /*!< 0x000007FF */
+#define LTDC_TWCR_TOTALH             LTDC_TWCR_TOTALH_Msk                      /*!< Total Heigh */
+#define LTDC_TWCR_TOTALW_Pos         (16U)
+#define LTDC_TWCR_TOTALW_Msk         (0xFFFUL << LTDC_TWCR_TOTALW_Pos)         /*!< 0x0FFF0000 */
+#define LTDC_TWCR_TOTALW             LTDC_TWCR_TOTALW_Msk                      /*!< Total Width */
+
+/********************  Bit definition for LTDC_GCR register  ******************/
+
+#define LTDC_GCR_LTDCEN_Pos          (0U)
+#define LTDC_GCR_LTDCEN_Msk          (0x1UL << LTDC_GCR_LTDCEN_Pos)            /*!< 0x00000001 */
+#define LTDC_GCR_LTDCEN              LTDC_GCR_LTDCEN_Msk                       /*!< LCD-TFT controller enable bit       */
+#define LTDC_GCR_DBW_Pos             (4U)
+#define LTDC_GCR_DBW_Msk             (0x7UL << LTDC_GCR_DBW_Pos)               /*!< 0x00000070 */
+#define LTDC_GCR_DBW                 LTDC_GCR_DBW_Msk                          /*!< Dither Blue Width                   */
+#define LTDC_GCR_DGW_Pos             (8U)
+#define LTDC_GCR_DGW_Msk             (0x7UL << LTDC_GCR_DGW_Pos)               /*!< 0x00000700 */
+#define LTDC_GCR_DGW                 LTDC_GCR_DGW_Msk                          /*!< Dither Green Width                  */
+#define LTDC_GCR_DRW_Pos             (12U)
+#define LTDC_GCR_DRW_Msk             (0x7UL << LTDC_GCR_DRW_Pos)               /*!< 0x00007000 */
+#define LTDC_GCR_DRW                 LTDC_GCR_DRW_Msk                          /*!< Dither Red Width                    */
+#define LTDC_GCR_DEN_Pos             (16U)
+#define LTDC_GCR_DEN_Msk             (0x1UL << LTDC_GCR_DEN_Pos)               /*!< 0x00010000 */
+#define LTDC_GCR_DEN                 LTDC_GCR_DEN_Msk                          /*!< Dither Enable                       */
+#define LTDC_GCR_PCPOL_Pos           (28U)
+#define LTDC_GCR_PCPOL_Msk           (0x1UL << LTDC_GCR_PCPOL_Pos)             /*!< 0x10000000 */
+#define LTDC_GCR_PCPOL               LTDC_GCR_PCPOL_Msk                        /*!< Pixel Clock Polarity                */
+#define LTDC_GCR_DEPOL_Pos           (29U)
+#define LTDC_GCR_DEPOL_Msk           (0x1UL << LTDC_GCR_DEPOL_Pos)             /*!< 0x20000000 */
+#define LTDC_GCR_DEPOL               LTDC_GCR_DEPOL_Msk                        /*!< Data Enable Polarity                */
+#define LTDC_GCR_VSPOL_Pos           (30U)
+#define LTDC_GCR_VSPOL_Msk           (0x1UL << LTDC_GCR_VSPOL_Pos)             /*!< 0x40000000 */
+#define LTDC_GCR_VSPOL               LTDC_GCR_VSPOL_Msk                        /*!< Vertical Synchronization Polarity   */
+#define LTDC_GCR_HSPOL_Pos           (31U)
+#define LTDC_GCR_HSPOL_Msk           (0x1UL << LTDC_GCR_HSPOL_Pos)             /*!< 0x80000000 */
+#define LTDC_GCR_HSPOL               LTDC_GCR_HSPOL_Msk                        /*!< Horizontal Synchronization Polarity */
+
+
+/********************  Bit definition for LTDC_SRCR register  *****************/
+
+#define LTDC_SRCR_IMR_Pos            (0U)
+#define LTDC_SRCR_IMR_Msk            (0x1UL << LTDC_SRCR_IMR_Pos)              /*!< 0x00000001 */
+#define LTDC_SRCR_IMR                LTDC_SRCR_IMR_Msk                         /*!< Immediate Reload         */
+#define LTDC_SRCR_VBR_Pos            (1U)
+#define LTDC_SRCR_VBR_Msk            (0x1UL << LTDC_SRCR_VBR_Pos)              /*!< 0x00000002 */
+#define LTDC_SRCR_VBR                LTDC_SRCR_VBR_Msk                         /*!< Vertical Blanking Reload */
+
+/********************  Bit definition for LTDC_BCCR register  *****************/
+
+#define LTDC_BCCR_BCBLUE_Pos         (0U)
+#define LTDC_BCCR_BCBLUE_Msk         (0xFFUL << LTDC_BCCR_BCBLUE_Pos)          /*!< 0x000000FF */
+#define LTDC_BCCR_BCBLUE             LTDC_BCCR_BCBLUE_Msk                      /*!< Background Blue value  */
+#define LTDC_BCCR_BCGREEN_Pos        (8U)
+#define LTDC_BCCR_BCGREEN_Msk        (0xFFUL << LTDC_BCCR_BCGREEN_Pos)         /*!< 0x0000FF00 */
+#define LTDC_BCCR_BCGREEN            LTDC_BCCR_BCGREEN_Msk                     /*!< Background Green value */
+#define LTDC_BCCR_BCRED_Pos          (16U)
+#define LTDC_BCCR_BCRED_Msk          (0xFFUL << LTDC_BCCR_BCRED_Pos)           /*!< 0x00FF0000 */
+#define LTDC_BCCR_BCRED              LTDC_BCCR_BCRED_Msk                       /*!< Background Red value   */
+
+/********************  Bit definition for LTDC_IER register  ******************/
+
+#define LTDC_IER_LIE_Pos             (0U)
+#define LTDC_IER_LIE_Msk             (0x1UL << LTDC_IER_LIE_Pos)               /*!< 0x00000001 */
+#define LTDC_IER_LIE                 LTDC_IER_LIE_Msk                          /*!< Line Interrupt Enable            */
+#define LTDC_IER_FUIE_Pos            (1U)
+#define LTDC_IER_FUIE_Msk            (0x1UL << LTDC_IER_FUIE_Pos)              /*!< 0x00000002 */
+#define LTDC_IER_FUIE                LTDC_IER_FUIE_Msk                         /*!< FIFO Underrun Interrupt Enable   */
+#define LTDC_IER_TERRIE_Pos          (2U)
+#define LTDC_IER_TERRIE_Msk          (0x1UL << LTDC_IER_TERRIE_Pos)            /*!< 0x00000004 */
+#define LTDC_IER_TERRIE              LTDC_IER_TERRIE_Msk                       /*!< Transfer Error Interrupt Enable  */
+#define LTDC_IER_RRIE_Pos            (3U)
+#define LTDC_IER_RRIE_Msk            (0x1UL << LTDC_IER_RRIE_Pos)              /*!< 0x00000008 */
+#define LTDC_IER_RRIE                LTDC_IER_RRIE_Msk                         /*!< Register Reload interrupt enable */
+
+/********************  Bit definition for LTDC_ISR register  ******************/
+
+#define LTDC_ISR_LIF_Pos             (0U)
+#define LTDC_ISR_LIF_Msk             (0x1UL << LTDC_ISR_LIF_Pos)               /*!< 0x00000001 */
+#define LTDC_ISR_LIF                 LTDC_ISR_LIF_Msk                          /*!< Line Interrupt Flag */
+#define LTDC_ISR_FUIF_Pos            (1U)
+#define LTDC_ISR_FUIF_Msk            (0x1UL << LTDC_ISR_FUIF_Pos)              /*!< 0x00000002 */
+#define LTDC_ISR_FUIF                LTDC_ISR_FUIF_Msk                         /*!< FIFO Underrun Interrupt Flag */
+#define LTDC_ISR_TERRIF_Pos          (2U)
+#define LTDC_ISR_TERRIF_Msk          (0x1UL << LTDC_ISR_TERRIF_Pos)            /*!< 0x00000004 */
+#define LTDC_ISR_TERRIF              LTDC_ISR_TERRIF_Msk                       /*!< Transfer Error Interrupt Flag */
+#define LTDC_ISR_RRIF_Pos            (3U)
+#define LTDC_ISR_RRIF_Msk            (0x1UL << LTDC_ISR_RRIF_Pos)              /*!< 0x00000008 */
+#define LTDC_ISR_RRIF                LTDC_ISR_RRIF_Msk                         /*!< Register Reload interrupt Flag */
+
+/********************  Bit definition for LTDC_ICR register  ******************/
+
+#define LTDC_ICR_CLIF_Pos            (0U)
+#define LTDC_ICR_CLIF_Msk            (0x1UL << LTDC_ICR_CLIF_Pos)              /*!< 0x00000001 */
+#define LTDC_ICR_CLIF                LTDC_ICR_CLIF_Msk                         /*!< Clears the Line Interrupt Flag */
+#define LTDC_ICR_CFUIF_Pos           (1U)
+#define LTDC_ICR_CFUIF_Msk           (0x1UL << LTDC_ICR_CFUIF_Pos)             /*!< 0x00000002 */
+#define LTDC_ICR_CFUIF               LTDC_ICR_CFUIF_Msk                        /*!< Clears the FIFO Underrun Interrupt Flag */
+#define LTDC_ICR_CTERRIF_Pos         (2U)
+#define LTDC_ICR_CTERRIF_Msk         (0x1UL << LTDC_ICR_CTERRIF_Pos)           /*!< 0x00000004 */
+#define LTDC_ICR_CTERRIF             LTDC_ICR_CTERRIF_Msk                      /*!< Clears the Transfer Error Interrupt Flag */
+#define LTDC_ICR_CRRIF_Pos           (3U)
+#define LTDC_ICR_CRRIF_Msk           (0x1UL << LTDC_ICR_CRRIF_Pos)             /*!< 0x00000008 */
+#define LTDC_ICR_CRRIF               LTDC_ICR_CRRIF_Msk                        /*!< Clears Register Reload interrupt Flag */
+
+/********************  Bit definition for LTDC_LIPCR register  ****************/
+
+#define LTDC_LIPCR_LIPOS_Pos         (0U)
+#define LTDC_LIPCR_LIPOS_Msk         (0x7FFUL << LTDC_LIPCR_LIPOS_Pos)         /*!< 0x000007FF */
+#define LTDC_LIPCR_LIPOS             LTDC_LIPCR_LIPOS_Msk                      /*!< Line Interrupt Position */
+
+/********************  Bit definition for LTDC_CPSR register  *****************/
+
+#define LTDC_CPSR_CYPOS_Pos          (0U)
+#define LTDC_CPSR_CYPOS_Msk          (0xFFFFUL << LTDC_CPSR_CYPOS_Pos)         /*!< 0x0000FFFF */
+#define LTDC_CPSR_CYPOS              LTDC_CPSR_CYPOS_Msk                       /*!< Current Y Position */
+#define LTDC_CPSR_CXPOS_Pos          (16U)
+#define LTDC_CPSR_CXPOS_Msk          (0xFFFFUL << LTDC_CPSR_CXPOS_Pos)         /*!< 0xFFFF0000 */
+#define LTDC_CPSR_CXPOS              LTDC_CPSR_CXPOS_Msk                       /*!< Current X Position */
+
+/********************  Bit definition for LTDC_CDSR register  *****************/
+
+#define LTDC_CDSR_VDES_Pos           (0U)
+#define LTDC_CDSR_VDES_Msk           (0x1UL << LTDC_CDSR_VDES_Pos)             /*!< 0x00000001 */
+#define LTDC_CDSR_VDES               LTDC_CDSR_VDES_Msk                        /*!< Vertical Data Enable Status       */
+#define LTDC_CDSR_HDES_Pos           (1U)
+#define LTDC_CDSR_HDES_Msk           (0x1UL << LTDC_CDSR_HDES_Pos)             /*!< 0x00000002 */
+#define LTDC_CDSR_HDES               LTDC_CDSR_HDES_Msk                        /*!< Horizontal Data Enable Status     */
+#define LTDC_CDSR_VSYNCS_Pos         (2U)
+#define LTDC_CDSR_VSYNCS_Msk         (0x1UL << LTDC_CDSR_VSYNCS_Pos)           /*!< 0x00000004 */
+#define LTDC_CDSR_VSYNCS             LTDC_CDSR_VSYNCS_Msk                      /*!< Vertical Synchronization Status   */
+#define LTDC_CDSR_HSYNCS_Pos         (3U)
+#define LTDC_CDSR_HSYNCS_Msk         (0x1UL << LTDC_CDSR_HSYNCS_Pos)           /*!< 0x00000008 */
+#define LTDC_CDSR_HSYNCS             LTDC_CDSR_HSYNCS_Msk                      /*!< Horizontal Synchronization Status */
+
+/********************  Bit definition for LTDC_LxCR register  *****************/
+
+#define LTDC_LxCR_LEN_Pos            (0U)
+#define LTDC_LxCR_LEN_Msk            (0x1UL << LTDC_LxCR_LEN_Pos)              /*!< 0x00000001 */
+#define LTDC_LxCR_LEN                LTDC_LxCR_LEN_Msk                         /*!< Layer Enable              */
+#define LTDC_LxCR_COLKEN_Pos         (1U)
+#define LTDC_LxCR_COLKEN_Msk         (0x1UL << LTDC_LxCR_COLKEN_Pos)           /*!< 0x00000002 */
+#define LTDC_LxCR_COLKEN             LTDC_LxCR_COLKEN_Msk                      /*!< Color Keying Enable       */
+#define LTDC_LxCR_CLUTEN_Pos         (4U)
+#define LTDC_LxCR_CLUTEN_Msk         (0x1UL << LTDC_LxCR_CLUTEN_Pos)           /*!< 0x00000010 */
+#define LTDC_LxCR_CLUTEN             LTDC_LxCR_CLUTEN_Msk                      /*!< Color Lockup Table Enable */
+
+/********************  Bit definition for LTDC_LxWHPCR register  **************/
+
+#define LTDC_LxWHPCR_WHSTPOS_Pos     (0U)
+#define LTDC_LxWHPCR_WHSTPOS_Msk     (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos)     /*!< 0x00000FFF */
+#define LTDC_LxWHPCR_WHSTPOS         LTDC_LxWHPCR_WHSTPOS_Msk                  /*!< Window Horizontal Start Position */
+#define LTDC_LxWHPCR_WHSPPOS_Pos     (16U)
+#define LTDC_LxWHPCR_WHSPPOS_Msk     (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos)    /*!< 0xFFFF0000 */
+#define LTDC_LxWHPCR_WHSPPOS         LTDC_LxWHPCR_WHSPPOS_Msk                  /*!< Window Horizontal Stop Position  */
+
+/********************  Bit definition for LTDC_LxWVPCR register  **************/
+
+#define LTDC_LxWVPCR_WVSTPOS_Pos     (0U)
+#define LTDC_LxWVPCR_WVSTPOS_Msk     (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos)     /*!< 0x00000FFF */
+#define LTDC_LxWVPCR_WVSTPOS         LTDC_LxWVPCR_WVSTPOS_Msk                  /*!< Window Vertical Start Position */
+#define LTDC_LxWVPCR_WVSPPOS_Pos     (16U)
+#define LTDC_LxWVPCR_WVSPPOS_Msk     (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos)    /*!< 0xFFFF0000 */
+#define LTDC_LxWVPCR_WVSPPOS         LTDC_LxWVPCR_WVSPPOS_Msk                  /*!< Window Vertical Stop Position  */
+
+/********************  Bit definition for LTDC_LxCKCR register  ***************/
+
+#define LTDC_LxCKCR_CKBLUE_Pos       (0U)
+#define LTDC_LxCKCR_CKBLUE_Msk       (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos)        /*!< 0x000000FF */
+#define LTDC_LxCKCR_CKBLUE           LTDC_LxCKCR_CKBLUE_Msk                    /*!< Color Key Blue value  */
+#define LTDC_LxCKCR_CKGREEN_Pos      (8U)
+#define LTDC_LxCKCR_CKGREEN_Msk      (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos)       /*!< 0x0000FF00 */
+#define LTDC_LxCKCR_CKGREEN          LTDC_LxCKCR_CKGREEN_Msk                   /*!< Color Key Green value */
+#define LTDC_LxCKCR_CKRED_Pos        (16U)
+#define LTDC_LxCKCR_CKRED_Msk        (0xFFUL << LTDC_LxCKCR_CKRED_Pos)         /*!< 0x00FF0000 */
+#define LTDC_LxCKCR_CKRED            LTDC_LxCKCR_CKRED_Msk                     /*!< Color Key Red value   */
+
+/********************  Bit definition for LTDC_LxPFCR register  ***************/
+
+#define LTDC_LxPFCR_PF_Pos           (0U)
+#define LTDC_LxPFCR_PF_Msk           (0x7UL << LTDC_LxPFCR_PF_Pos)             /*!< 0x00000007 */
+#define LTDC_LxPFCR_PF               LTDC_LxPFCR_PF_Msk                        /*!< Pixel Format */
+
+/********************  Bit definition for LTDC_LxCACR register  ***************/
+
+#define LTDC_LxCACR_CONSTA_Pos       (0U)
+#define LTDC_LxCACR_CONSTA_Msk       (0xFFUL << LTDC_LxCACR_CONSTA_Pos)        /*!< 0x000000FF */
+#define LTDC_LxCACR_CONSTA           LTDC_LxCACR_CONSTA_Msk                    /*!< Constant Alpha */
+
+/********************  Bit definition for LTDC_LxDCCR register  ***************/
+
+#define LTDC_LxDCCR_DCBLUE_Pos       (0U)
+#define LTDC_LxDCCR_DCBLUE_Msk       (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos)        /*!< 0x000000FF */
+#define LTDC_LxDCCR_DCBLUE           LTDC_LxDCCR_DCBLUE_Msk                    /*!< Default Color Blue  */
+#define LTDC_LxDCCR_DCGREEN_Pos      (8U)
+#define LTDC_LxDCCR_DCGREEN_Msk      (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos)       /*!< 0x0000FF00 */
+#define LTDC_LxDCCR_DCGREEN          LTDC_LxDCCR_DCGREEN_Msk                   /*!< Default Color Green */
+#define LTDC_LxDCCR_DCRED_Pos        (16U)
+#define LTDC_LxDCCR_DCRED_Msk        (0xFFUL << LTDC_LxDCCR_DCRED_Pos)         /*!< 0x00FF0000 */
+#define LTDC_LxDCCR_DCRED            LTDC_LxDCCR_DCRED_Msk                     /*!< Default Color Red   */
+#define LTDC_LxDCCR_DCALPHA_Pos      (24U)
+#define LTDC_LxDCCR_DCALPHA_Msk      (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos)       /*!< 0xFF000000 */
+#define LTDC_LxDCCR_DCALPHA          LTDC_LxDCCR_DCALPHA_Msk                   /*!< Default Color Alpha */
+
+/********************  Bit definition for LTDC_LxBFCR register  ***************/
+
+#define LTDC_LxBFCR_BF2_Pos          (0U)
+#define LTDC_LxBFCR_BF2_Msk          (0x7UL << LTDC_LxBFCR_BF2_Pos)            /*!< 0x00000007 */
+#define LTDC_LxBFCR_BF2              LTDC_LxBFCR_BF2_Msk                       /*!< Blending Factor 2 */
+#define LTDC_LxBFCR_BF1_Pos          (8U)
+#define LTDC_LxBFCR_BF1_Msk          (0x7UL << LTDC_LxBFCR_BF1_Pos)            /*!< 0x00000700 */
+#define LTDC_LxBFCR_BF1              LTDC_LxBFCR_BF1_Msk                       /*!< Blending Factor 1 */
+
+/********************  Bit definition for LTDC_LxCFBAR register  **************/
+
+#define LTDC_LxCFBAR_CFBADD_Pos      (0U)
+#define LTDC_LxCFBAR_CFBADD_Msk      (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */
+#define LTDC_LxCFBAR_CFBADD          LTDC_LxCFBAR_CFBADD_Msk                   /*!< Color Frame Buffer Start Address */
+
+/********************  Bit definition for LTDC_LxCFBLR register  **************/
+
+#define LTDC_LxCFBLR_CFBLL_Pos       (0U)
+#define LTDC_LxCFBLR_CFBLL_Msk       (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos)      /*!< 0x00001FFF */
+#define LTDC_LxCFBLR_CFBLL           LTDC_LxCFBLR_CFBLL_Msk                    /*!< Color Frame Buffer Line Length    */
+#define LTDC_LxCFBLR_CFBP_Pos        (16U)
+#define LTDC_LxCFBLR_CFBP_Msk        (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos)       /*!< 0x1FFF0000 */
+#define LTDC_LxCFBLR_CFBP            LTDC_LxCFBLR_CFBP_Msk                     /*!< Color Frame Buffer Pitch in bytes */
+
+/********************  Bit definition for LTDC_LxCFBLNR register  *************/
+
+#define LTDC_LxCFBLNR_CFBLNBR_Pos    (0U)
+#define LTDC_LxCFBLNR_CFBLNBR_Msk    (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos)    /*!< 0x000007FF */
+#define LTDC_LxCFBLNR_CFBLNBR        LTDC_LxCFBLNR_CFBLNBR_Msk                 /*!< Frame Buffer Line Number */
+
+/********************  Bit definition for LTDC_LxCLUTWR register  *************/
+
+#define LTDC_LxCLUTWR_BLUE_Pos       (0U)
+#define LTDC_LxCLUTWR_BLUE_Msk       (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos)        /*!< 0x000000FF */
+#define LTDC_LxCLUTWR_BLUE           LTDC_LxCLUTWR_BLUE_Msk                    /*!< Blue value   */
+#define LTDC_LxCLUTWR_GREEN_Pos      (8U)
+#define LTDC_LxCLUTWR_GREEN_Msk      (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos)       /*!< 0x0000FF00 */
+#define LTDC_LxCLUTWR_GREEN          LTDC_LxCLUTWR_GREEN_Msk                   /*!< Green value  */
+#define LTDC_LxCLUTWR_RED_Pos        (16U)
+#define LTDC_LxCLUTWR_RED_Msk        (0xFFUL << LTDC_LxCLUTWR_RED_Pos)         /*!< 0x00FF0000 */
+#define LTDC_LxCLUTWR_RED            LTDC_LxCLUTWR_RED_Msk                     /*!< Red value    */
+#define LTDC_LxCLUTWR_CLUTADD_Pos    (24U)
+#define LTDC_LxCLUTWR_CLUTADD_Msk    (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos)     /*!< 0xFF000000 */
+#define LTDC_LxCLUTWR_CLUTADD        LTDC_LxCLUTWR_CLUTADD_Msk                 /*!< CLUT address */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                     MDMA                                   */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for MDMA_GISR0 register  ****************/
+#define MDMA_GISR0_GIF0_Pos       (0U)
+#define MDMA_GISR0_GIF0_Msk       (0x1UL << MDMA_GISR0_GIF0_Pos)               /*!< 0x00000001 */
+#define MDMA_GISR0_GIF0           MDMA_GISR0_GIF0_Msk                          /*!< Channel 0 global interrupt flag */
+#define MDMA_GISR0_GIF1_Pos       (1U)
+#define MDMA_GISR0_GIF1_Msk       (0x1UL << MDMA_GISR0_GIF1_Pos)               /*!< 0x00000002 */
+#define MDMA_GISR0_GIF1           MDMA_GISR0_GIF1_Msk                          /*!< Channel 1 global interrupt flag */
+#define MDMA_GISR0_GIF2_Pos       (2U)
+#define MDMA_GISR0_GIF2_Msk       (0x1UL << MDMA_GISR0_GIF2_Pos)               /*!< 0x00000004 */
+#define MDMA_GISR0_GIF2           MDMA_GISR0_GIF2_Msk                          /*!< Channel 2 global interrupt flag */
+#define MDMA_GISR0_GIF3_Pos       (3U)
+#define MDMA_GISR0_GIF3_Msk       (0x1UL << MDMA_GISR0_GIF3_Pos)               /*!< 0x00000008 */
+#define MDMA_GISR0_GIF3           MDMA_GISR0_GIF3_Msk                          /*!< Channel 3 global interrupt flag */
+#define MDMA_GISR0_GIF4_Pos       (4U)
+#define MDMA_GISR0_GIF4_Msk       (0x1UL << MDMA_GISR0_GIF4_Pos)               /*!< 0x00000010 */
+#define MDMA_GISR0_GIF4           MDMA_GISR0_GIF4_Msk                          /*!< Channel 4 global interrupt flag */
+#define MDMA_GISR0_GIF5_Pos       (5U)
+#define MDMA_GISR0_GIF5_Msk       (0x1UL << MDMA_GISR0_GIF5_Pos)               /*!< 0x00000020 */
+#define MDMA_GISR0_GIF5           MDMA_GISR0_GIF5_Msk                          /*!< Channel 5 global interrupt flag */
+#define MDMA_GISR0_GIF6_Pos       (6U)
+#define MDMA_GISR0_GIF6_Msk       (0x1UL << MDMA_GISR0_GIF6_Pos)               /*!< 0x00000040 */
+#define MDMA_GISR0_GIF6           MDMA_GISR0_GIF6_Msk                          /*!< Channel 6 global interrupt flag */
+#define MDMA_GISR0_GIF7_Pos       (7U)
+#define MDMA_GISR0_GIF7_Msk       (0x1UL << MDMA_GISR0_GIF7_Pos)               /*!< 0x00000080 */
+#define MDMA_GISR0_GIF7           MDMA_GISR0_GIF7_Msk                          /*!< Channel 7 global interrupt flag */
+#define MDMA_GISR0_GIF8_Pos       (8U)
+#define MDMA_GISR0_GIF8_Msk       (0x1UL << MDMA_GISR0_GIF8_Pos)               /*!< 0x00000100 */
+#define MDMA_GISR0_GIF8           MDMA_GISR0_GIF8_Msk                          /*!< Channel 8 global interrupt flag */
+#define MDMA_GISR0_GIF9_Pos       (9U)
+#define MDMA_GISR0_GIF9_Msk       (0x1UL << MDMA_GISR0_GIF9_Pos)               /*!< 0x00000200 */
+#define MDMA_GISR0_GIF9           MDMA_GISR0_GIF9_Msk                          /*!< Channel 9 global interrupt flag */
+#define MDMA_GISR0_GIF10_Pos      (10U)
+#define MDMA_GISR0_GIF10_Msk      (0x1UL << MDMA_GISR0_GIF10_Pos)              /*!< 0x00000400 */
+#define MDMA_GISR0_GIF10          MDMA_GISR0_GIF10_Msk                         /*!< Channel 10 global interrupt flag */
+#define MDMA_GISR0_GIF11_Pos      (11U)
+#define MDMA_GISR0_GIF11_Msk      (0x1UL << MDMA_GISR0_GIF11_Pos)              /*!< 0x00000800 */
+#define MDMA_GISR0_GIF11          MDMA_GISR0_GIF11_Msk                         /*!< Channel 11 global interrupt flag */
+#define MDMA_GISR0_GIF12_Pos      (12U)
+#define MDMA_GISR0_GIF12_Msk      (0x1UL << MDMA_GISR0_GIF12_Pos)              /*!< 0x00001000 */
+#define MDMA_GISR0_GIF12          MDMA_GISR0_GIF12_Msk                         /*!< Channel 12 global interrupt flag */
+#define MDMA_GISR0_GIF13_Pos      (13U)
+#define MDMA_GISR0_GIF13_Msk      (0x1UL << MDMA_GISR0_GIF13_Pos)              /*!< 0x00002000 */
+#define MDMA_GISR0_GIF13          MDMA_GISR0_GIF13_Msk                         /*!< Channel 13 global interrupt flag */
+#define MDMA_GISR0_GIF14_Pos      (14U)
+#define MDMA_GISR0_GIF14_Msk      (0x1UL << MDMA_GISR0_GIF14_Pos)              /*!< 0x00004000 */
+#define MDMA_GISR0_GIF14          MDMA_GISR0_GIF14_Msk                         /*!< Channel 14 global interrupt flag */
+#define MDMA_GISR0_GIF15_Pos      (15U)
+#define MDMA_GISR0_GIF15_Msk      (0x1UL << MDMA_GISR0_GIF15_Pos)              /*!< 0x00008000 */
+#define MDMA_GISR0_GIF15          MDMA_GISR0_GIF15_Msk                         /*!< Channel 15 global interrupt flag */
+
+/********************  Bit definition for MDMA_CxISR register  ****************/
+#define MDMA_CISR_TEIF_Pos        (0U)
+#define MDMA_CISR_TEIF_Msk        (0x1UL << MDMA_CISR_TEIF_Pos)                /*!< 0x00000001 */
+#define MDMA_CISR_TEIF            MDMA_CISR_TEIF_Msk                           /*!< Channel x transfer error interrupt flag */
+#define MDMA_CISR_CTCIF_Pos       (1U)
+#define MDMA_CISR_CTCIF_Msk       (0x1UL << MDMA_CISR_CTCIF_Pos)               /*!< 0x00000002 */
+#define MDMA_CISR_CTCIF           MDMA_CISR_CTCIF_Msk                          /*!< Channel x Channel Transfer Complete interrupt flag */
+#define MDMA_CISR_BRTIF_Pos       (2U)
+#define MDMA_CISR_BRTIF_Msk       (0x1UL << MDMA_CISR_BRTIF_Pos)               /*!< 0x00000004 */
+#define MDMA_CISR_BRTIF           MDMA_CISR_BRTIF_Msk                          /*!< Channel x block repeat transfer complete interrupt flag */
+#define MDMA_CISR_BTIF_Pos        (3U)
+#define MDMA_CISR_BTIF_Msk        (0x1UL << MDMA_CISR_BTIF_Pos)                /*!< 0x00000008 */
+#define MDMA_CISR_BTIF            MDMA_CISR_BTIF_Msk                           /*!< Channel x block transfer complete interrupt flag */
+#define MDMA_CISR_TCIF_Pos        (4U)
+#define MDMA_CISR_TCIF_Msk        (0x1UL << MDMA_CISR_TCIF_Pos)                /*!< 0x00000010 */
+#define MDMA_CISR_TCIF            MDMA_CISR_TCIF_Msk                           /*!< Channel x buffer transfer complete interrupt flag */
+#define MDMA_CISR_CRQA_Pos        (16U)
+#define MDMA_CISR_CRQA_Msk        (0x1UL << MDMA_CISR_CRQA_Pos)                /*!< 0x00010000 */
+#define MDMA_CISR_CRQA            MDMA_CISR_CRQA_Msk                           /*!< Channel x ReQest Active flag */
+
+/********************  Bit definition for MDMA_CxIFCR register  ****************/
+#define MDMA_CIFCR_CTEIF_Pos      (0U)
+#define MDMA_CIFCR_CTEIF_Msk      (0x1UL << MDMA_CIFCR_CTEIF_Pos)              /*!< 0x00000001 */
+#define MDMA_CIFCR_CTEIF          MDMA_CIFCR_CTEIF_Msk                         /*!< Channel x clear transfer error interrupt flag */
+#define MDMA_CIFCR_CCTCIF_Pos     (1U)
+#define MDMA_CIFCR_CCTCIF_Msk     (0x1UL << MDMA_CIFCR_CCTCIF_Pos)             /*!< 0x00000002 */
+#define MDMA_CIFCR_CCTCIF         MDMA_CIFCR_CCTCIF_Msk                        /*!< Clear Channel transfer complete interrupt flag for channel x */
+#define MDMA_CIFCR_CBRTIF_Pos     (2U)
+#define MDMA_CIFCR_CBRTIF_Msk     (0x1UL << MDMA_CIFCR_CBRTIF_Pos)             /*!< 0x00000004 */
+#define MDMA_CIFCR_CBRTIF         MDMA_CIFCR_CBRTIF_Msk                        /*!< Channel x clear block repeat transfer complete interrupt flag */
+#define MDMA_CIFCR_CBTIF_Pos      (3U)
+#define MDMA_CIFCR_CBTIF_Msk      (0x1UL << MDMA_CIFCR_CBTIF_Pos)              /*!< 0x00000008 */
+#define MDMA_CIFCR_CBTIF          MDMA_CIFCR_CBTIF_Msk                         /*!< Channel x Clear block transfer complete interrupt flag */
+#define MDMA_CIFCR_CLTCIF_Pos     (4U)
+#define MDMA_CIFCR_CLTCIF_Msk     (0x1UL << MDMA_CIFCR_CLTCIF_Pos)             /*!< 0x00000010 */
+#define MDMA_CIFCR_CLTCIF         MDMA_CIFCR_CLTCIF_Msk                        /*!< CLear Transfer buffer Complete Interrupt Flag for channel */
+
+/********************  Bit definition for MDMA_CxESR register  ****************/
+#define MDMA_CESR_TEA_Pos         (0U)
+#define MDMA_CESR_TEA_Msk         (0x7FUL << MDMA_CESR_TEA_Pos)                /*!< 0x0000007F */
+#define MDMA_CESR_TEA             MDMA_CESR_TEA_Msk                            /*!< Transfer Error Address */
+#define MDMA_CESR_TED_Pos         (7U)
+#define MDMA_CESR_TED_Msk         (0x1UL << MDMA_CESR_TED_Pos)                 /*!< 0x00000080 */
+#define MDMA_CESR_TED             MDMA_CESR_TED_Msk                            /*!< Transfer Error Direction */
+#define MDMA_CESR_TELD_Pos        (8U)
+#define MDMA_CESR_TELD_Msk        (0x1UL << MDMA_CESR_TELD_Pos)                /*!< 0x00000100 */
+#define MDMA_CESR_TELD            MDMA_CESR_TELD_Msk                           /*!< Transfer Error Link Data */
+#define MDMA_CESR_TEMD_Pos        (9U)
+#define MDMA_CESR_TEMD_Msk        (0x1UL << MDMA_CESR_TEMD_Pos)                /*!< 0x00000200 */
+#define MDMA_CESR_TEMD            MDMA_CESR_TEMD_Msk                           /*!< Transfer Error Mask Data */
+#define MDMA_CESR_ASE_Pos         (10U)
+#define MDMA_CESR_ASE_Msk         (0x1UL << MDMA_CESR_ASE_Pos)                 /*!< 0x00000400 */
+#define MDMA_CESR_ASE             MDMA_CESR_ASE_Msk                            /*!< Address/Size Error       */
+#define MDMA_CESR_BSE_Pos         (11U)
+#define MDMA_CESR_BSE_Msk         (0x1UL << MDMA_CESR_BSE_Pos)                 /*!< 0x00000800 */
+#define MDMA_CESR_BSE             MDMA_CESR_BSE_Msk                            /*!< Block Size Error         */
+
+/********************  Bit definition for MDMA_CxCR register  ****************/
+#define MDMA_CCR_EN_Pos           (0U)
+#define MDMA_CCR_EN_Msk           (0x1UL << MDMA_CCR_EN_Pos)                   /*!< 0x00000001 */
+#define MDMA_CCR_EN               MDMA_CCR_EN_Msk                              /*!< Channel enable / flag channel ready when read low */
+#define MDMA_CCR_TEIE_Pos         (1U)
+#define MDMA_CCR_TEIE_Msk         (0x1UL << MDMA_CCR_TEIE_Pos)                 /*!< 0x00000002 */
+#define MDMA_CCR_TEIE             MDMA_CCR_TEIE_Msk                            /*!< Transfer error interrupt enable */
+#define MDMA_CCR_CTCIE_Pos        (2U)
+#define MDMA_CCR_CTCIE_Msk        (0x1UL << MDMA_CCR_CTCIE_Pos)                /*!< 0x00000004 */
+#define MDMA_CCR_CTCIE            MDMA_CCR_CTCIE_Msk                           /*!< Channel Transfer Complete interrupt enable */
+#define MDMA_CCR_BRTIE_Pos        (3U)
+#define MDMA_CCR_BRTIE_Msk        (0x1UL << MDMA_CCR_BRTIE_Pos)                /*!< 0x00000008 */
+#define MDMA_CCR_BRTIE            MDMA_CCR_BRTIE_Msk                           /*!< Block Repeat transfer interrupt enable */
+#define MDMA_CCR_BTIE_Pos         (4U)
+#define MDMA_CCR_BTIE_Msk         (0x1UL << MDMA_CCR_BTIE_Pos)                 /*!< 0x00000010 */
+#define MDMA_CCR_BTIE             MDMA_CCR_BTIE_Msk                            /*!< Block Transfer interrupt enable */
+#define MDMA_CCR_TCIE_Pos         (5U)
+#define MDMA_CCR_TCIE_Msk         (0x1UL << MDMA_CCR_TCIE_Pos)                 /*!< 0x00000020 */
+#define MDMA_CCR_TCIE             MDMA_CCR_TCIE_Msk                            /*!< buffer Transfer Complete interrupt enable */
+#define MDMA_CCR_PL_Pos           (6U)
+#define MDMA_CCR_PL_Msk           (0x3UL << MDMA_CCR_PL_Pos)                   /*!< 0x000000C0 */
+#define MDMA_CCR_PL               MDMA_CCR_PL_Msk                              /*!< Priority level */
+#define MDMA_CCR_PL_0             (0x1UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000040 */
+#define MDMA_CCR_PL_1             (0x2UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000080 */
+#define MDMA_CCR_BEX_Pos          (12U)
+#define MDMA_CCR_BEX_Msk          (0x1UL << MDMA_CCR_BEX_Pos)                  /*!< 0x00001000 */
+#define MDMA_CCR_BEX              MDMA_CCR_BEX_Msk                             /*!< Byte Endianess eXchange */
+#define MDMA_CCR_HEX_Pos          (13U)
+#define MDMA_CCR_HEX_Msk          (0x1UL << MDMA_CCR_HEX_Pos)                  /*!< 0x00002000 */
+#define MDMA_CCR_HEX              MDMA_CCR_HEX_Msk                             /*!< Half word Endianess eXchange */
+#define MDMA_CCR_WEX_Pos          (14U)
+#define MDMA_CCR_WEX_Msk          (0x1UL << MDMA_CCR_WEX_Pos)                  /*!< 0x00004000 */
+#define MDMA_CCR_WEX              MDMA_CCR_WEX_Msk                             /*!< Word Endianess eXchange */
+#define MDMA_CCR_SWRQ_Pos         (16U)
+#define MDMA_CCR_SWRQ_Msk         (0x1UL << MDMA_CCR_SWRQ_Pos)                 /*!< 0x00010000 */
+#define MDMA_CCR_SWRQ             MDMA_CCR_SWRQ_Msk                            /*!< SW ReQuest */
+
+/********************  Bit definition for MDMA_CxTCR register  ****************/
+#define MDMA_CTCR_SINC_Pos        (0U)
+#define MDMA_CTCR_SINC_Msk        (0x3UL << MDMA_CTCR_SINC_Pos)                /*!< 0x00000003 */
+#define MDMA_CTCR_SINC            MDMA_CTCR_SINC_Msk                           /*!< Source increment mode */
+#define MDMA_CTCR_SINC_0          (0x1UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000001 */
+#define MDMA_CTCR_SINC_1          (0x2UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000002 */
+#define MDMA_CTCR_DINC_Pos        (2U)
+#define MDMA_CTCR_DINC_Msk        (0x3UL << MDMA_CTCR_DINC_Pos)                /*!< 0x0000000C */
+#define MDMA_CTCR_DINC            MDMA_CTCR_DINC_Msk                           /*!< Source increment mode */
+#define MDMA_CTCR_DINC_0          (0x1UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000004 */
+#define MDMA_CTCR_DINC_1          (0x2UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000008 */
+#define MDMA_CTCR_SSIZE_Pos       (4U)
+#define MDMA_CTCR_SSIZE_Msk       (0x3UL << MDMA_CTCR_SSIZE_Pos)               /*!< 0x00000030 */
+#define MDMA_CTCR_SSIZE           MDMA_CTCR_SSIZE_Msk                          /*!< Source data size */
+#define MDMA_CTCR_SSIZE_0         (0x1UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000010 */
+#define MDMA_CTCR_SSIZE_1         (0x2UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000020 */
+#define MDMA_CTCR_DSIZE_Pos       (6U)
+#define MDMA_CTCR_DSIZE_Msk       (0x3UL << MDMA_CTCR_DSIZE_Pos)               /*!< 0x000000C0 */
+#define MDMA_CTCR_DSIZE           MDMA_CTCR_DSIZE_Msk                          /*!< Destination data size */
+#define MDMA_CTCR_DSIZE_0         (0x1UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000040 */
+#define MDMA_CTCR_DSIZE_1         (0x2UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000080 */
+#define MDMA_CTCR_SINCOS_Pos      (8U)
+#define MDMA_CTCR_SINCOS_Msk      (0x3UL << MDMA_CTCR_SINCOS_Pos)              /*!< 0x00000300 */
+#define MDMA_CTCR_SINCOS          MDMA_CTCR_SINCOS_Msk                         /*!< Source increment offset size */
+#define MDMA_CTCR_SINCOS_0        (0x1UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000100 */
+#define MDMA_CTCR_SINCOS_1        (0x2UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000200 */
+#define MDMA_CTCR_DINCOS_Pos      (10U)
+#define MDMA_CTCR_DINCOS_Msk      (0x3UL << MDMA_CTCR_DINCOS_Pos)              /*!< 0x00000C00 */
+#define MDMA_CTCR_DINCOS          MDMA_CTCR_DINCOS_Msk                         /*!< Destination increment offset size */
+#define MDMA_CTCR_DINCOS_0        (0x1UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000400 */
+#define MDMA_CTCR_DINCOS_1        (0x2UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000800 */
+#define MDMA_CTCR_SBURST_Pos      (12U)
+#define MDMA_CTCR_SBURST_Msk      (0x7UL << MDMA_CTCR_SBURST_Pos)              /*!< 0x00007000 */
+#define MDMA_CTCR_SBURST          MDMA_CTCR_SBURST_Msk                         /*!< Source burst transfer configuration */
+#define MDMA_CTCR_SBURST_0        (0x1UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00001000 */
+#define MDMA_CTCR_SBURST_1        (0x2UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00002000 */
+#define MDMA_CTCR_SBURST_2        (0x4UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00004000 */
+#define MDMA_CTCR_DBURST_Pos      (15U)
+#define MDMA_CTCR_DBURST_Msk      (0x7UL << MDMA_CTCR_DBURST_Pos)              /*!< 0x00038000 */
+#define MDMA_CTCR_DBURST          MDMA_CTCR_DBURST_Msk                         /*!< Destination burst transfer configuration */
+#define MDMA_CTCR_DBURST_0        (0x1UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00008000 */
+#define MDMA_CTCR_DBURST_1        (0x2UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00010000 */
+#define MDMA_CTCR_DBURST_2        (0x4UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00020000 */
+#define MDMA_CTCR_TLEN_Pos        (18U)
+#define MDMA_CTCR_TLEN_Msk        (0x7FUL << MDMA_CTCR_TLEN_Pos)               /*!< 0x01FC0000 */
+#define MDMA_CTCR_TLEN            MDMA_CTCR_TLEN_Msk                           /*!< buffer Transfer Length (number of bytes - 1) */
+#define MDMA_CTCR_PKE_Pos         (25U)
+#define MDMA_CTCR_PKE_Msk         (0x1UL << MDMA_CTCR_PKE_Pos)                 /*!< 0x02000000 */
+#define MDMA_CTCR_PKE             MDMA_CTCR_PKE_Msk                            /*!< PacK Enable */
+#define MDMA_CTCR_PAM_Pos         (26U)
+#define MDMA_CTCR_PAM_Msk         (0x3UL << MDMA_CTCR_PAM_Pos)                 /*!< 0x0C000000 */
+#define MDMA_CTCR_PAM             MDMA_CTCR_PAM_Msk                            /*!< Padding/Alignement Mode */
+#define MDMA_CTCR_PAM_0           (0x1UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x4000000 */
+#define MDMA_CTCR_PAM_1           (0x2UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x8000000 */
+#define MDMA_CTCR_TRGM_Pos        (28U)
+#define MDMA_CTCR_TRGM_Msk        (0x3UL << MDMA_CTCR_TRGM_Pos)                /*!< 0x30000000 */
+#define MDMA_CTCR_TRGM            MDMA_CTCR_TRGM_Msk                           /*!< Trigger Mode */
+#define MDMA_CTCR_TRGM_0          (0x1UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x10000000 */
+#define MDMA_CTCR_TRGM_1          (0x2UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x20000000 */
+#define MDMA_CTCR_SWRM_Pos        (30U)
+#define MDMA_CTCR_SWRM_Msk        (0x1UL << MDMA_CTCR_SWRM_Pos)                /*!< 0x40000000 */
+#define MDMA_CTCR_SWRM            MDMA_CTCR_SWRM_Msk                           /*!< SW Request Mode */
+#define MDMA_CTCR_BWM_Pos         (31U)
+#define MDMA_CTCR_BWM_Msk         (0x1UL << MDMA_CTCR_BWM_Pos)                 /*!< 0x80000000 */
+#define MDMA_CTCR_BWM             MDMA_CTCR_BWM_Msk                            /*!< Bufferable Write Mode */
+
+/********************  Bit definition for MDMA_CxBNDTR register  ****************/
+#define MDMA_CBNDTR_BNDT_Pos      (0U)
+#define MDMA_CBNDTR_BNDT_Msk      (0x1FFFFUL << MDMA_CBNDTR_BNDT_Pos)          /*!< 0x0001FFFF */
+#define MDMA_CBNDTR_BNDT          MDMA_CBNDTR_BNDT_Msk                         /*!< Block Number of data bytes to transfer */
+#define MDMA_CBNDTR_BRSUM_Pos     (18U)
+#define MDMA_CBNDTR_BRSUM_Msk     (0x1UL << MDMA_CBNDTR_BRSUM_Pos)             /*!< 0x00040000 */
+#define MDMA_CBNDTR_BRSUM         MDMA_CBNDTR_BRSUM_Msk                        /*!< Block Repeat Source address Update Mode */
+#define MDMA_CBNDTR_BRDUM_Pos     (19U)
+#define MDMA_CBNDTR_BRDUM_Msk     (0x1UL << MDMA_CBNDTR_BRDUM_Pos)             /*!< 0x00080000 */
+#define MDMA_CBNDTR_BRDUM         MDMA_CBNDTR_BRDUM_Msk                        /*!< Block Repeat Destination address Update Mode */
+#define MDMA_CBNDTR_BRC_Pos       (20U)
+#define MDMA_CBNDTR_BRC_Msk       (0xFFFUL << MDMA_CBNDTR_BRC_Pos)             /*!< 0xFFF00000 */
+#define MDMA_CBNDTR_BRC           MDMA_CBNDTR_BRC_Msk                          /*!< Block Repeat Count */
+
+/********************  Bit definition for MDMA_CxSAR register  ****************/
+#define MDMA_CSAR_SAR_Pos         (0U)
+#define MDMA_CSAR_SAR_Msk         (0xFFFFFFFFUL << MDMA_CSAR_SAR_Pos)          /*!< 0xFFFFFFFF */
+#define MDMA_CSAR_SAR             MDMA_CSAR_SAR_Msk                            /*!< Source address */
+
+/********************  Bit definition for MDMA_CxDAR register  ****************/
+#define MDMA_CDAR_DAR_Pos         (0U)
+#define MDMA_CDAR_DAR_Msk         (0xFFFFFFFFUL << MDMA_CDAR_DAR_Pos)          /*!< 0xFFFFFFFF */
+#define MDMA_CDAR_DAR             MDMA_CDAR_DAR_Msk                            /*!< Destination address */
+
+/********************  Bit definition for MDMA_CxBRUR  ************************/
+#define MDMA_CBRUR_SUV_Pos        (0U)
+#define MDMA_CBRUR_SUV_Msk        (0xFFFFUL << MDMA_CBRUR_SUV_Pos)             /*!< 0x0000FFFF */
+#define MDMA_CBRUR_SUV            MDMA_CBRUR_SUV_Msk                           /*!< Source address Update Value */
+#define MDMA_CBRUR_DUV_Pos        (16U)
+#define MDMA_CBRUR_DUV_Msk        (0xFFFFUL << MDMA_CBRUR_DUV_Pos)             /*!< 0xFFFF0000 */
+#define MDMA_CBRUR_DUV            MDMA_CBRUR_DUV_Msk                           /*!< Destination address Update Value */
+
+/********************  Bit definition for MDMA_CxLAR  *************************/
+#define MDMA_CLAR_LAR_Pos         (0U)
+#define MDMA_CLAR_LAR_Msk         (0xFFFFFFFFUL << MDMA_CLAR_LAR_Pos)          /*!< 0xFFFFFFFF */
+#define MDMA_CLAR_LAR             MDMA_CLAR_LAR_Msk                            /*!< Link Address Register */
+
+/********************  Bit definition for MDMA_CxTBR)  ************************/
+#define MDMA_CTBR_TSEL_Pos        (0U)
+#define MDMA_CTBR_TSEL_Msk        (0xFFUL << MDMA_CTBR_TSEL_Pos)               /*!< 0x000000FF */
+#define MDMA_CTBR_TSEL            MDMA_CTBR_TSEL_Msk                           /*!< Trigger SELection */
+#define MDMA_CTBR_SBUS_Pos        (16U)
+#define MDMA_CTBR_SBUS_Msk        (0x1UL << MDMA_CTBR_SBUS_Pos)                /*!< 0x00010000 */
+#define MDMA_CTBR_SBUS            MDMA_CTBR_SBUS_Msk                           /*!< Source BUS select */
+#define MDMA_CTBR_DBUS_Pos        (17U)
+#define MDMA_CTBR_DBUS_Msk        (0x1UL << MDMA_CTBR_DBUS_Pos)                /*!< 0x00020000 */
+#define MDMA_CTBR_DBUS            MDMA_CTBR_DBUS_Msk                           /*!< Destination BUS select */
+
+/********************  Bit definition for MDMA_CxMAR)  ************************/
+#define MDMA_CMAR_MAR_Pos         (0U)
+#define MDMA_CMAR_MAR_Msk         (0xFFFFFFFFUL << MDMA_CMAR_MAR_Pos)          /*!< 0xFFFFFFFF */
+#define MDMA_CMAR_MAR             MDMA_CMAR_MAR_Msk                            /*!< Mask address */
+
+/********************  Bit definition for MDMA_CxMDR)  ************************/
+#define MDMA_CMDR_MDR_Pos         (0U)
+#define MDMA_CMDR_MDR_Msk         (0xFFFFFFFFUL << MDMA_CMDR_MDR_Pos)          /*!< 0xFFFFFFFF */
+#define MDMA_CMDR_MDR             MDMA_CMDR_MDR_Msk                            /*!< Mask Data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Operational Amplifier (OPAMP)                      */
+/*                                                                            */
+/******************************************************************************/
+/*********************  Bit definition for OPAMPx_CSR register  ***************/
+#define OPAMP_CSR_OPAMPxEN_Pos           (0U)
+#define OPAMP_CSR_OPAMPxEN_Msk           (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)     /*!< 0x00000001 */
+#define OPAMP_CSR_OPAMPxEN               OPAMP_CSR_OPAMPxEN_Msk                /*!< OPAMP enable */
+#define OPAMP_CSR_FORCEVP_Pos            (1U)
+#define OPAMP_CSR_FORCEVP_Msk            (0x1UL << OPAMP_CSR_FORCEVP_Pos)      /*!< 0x00000002 */
+#define OPAMP_CSR_FORCEVP                OPAMP_CSR_FORCEVP_Msk                 /*!< Force internal reference on VP */
+
+#define OPAMP_CSR_VPSEL_Pos              (2U)
+#define OPAMP_CSR_VPSEL_Msk              (0x3UL << OPAMP_CSR_VPSEL_Pos)        /*!< 0x0000000C */
+#define OPAMP_CSR_VPSEL                  OPAMP_CSR_VPSEL_Msk                   /*!< Non inverted input selection */
+#define OPAMP_CSR_VPSEL_0                (0x1UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000004 */
+#define OPAMP_CSR_VPSEL_1                (0x2UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000008 */
+
+#define OPAMP_CSR_VMSEL_Pos              (5U)
+#define OPAMP_CSR_VMSEL_Msk              (0x3UL << OPAMP_CSR_VMSEL_Pos)        /*!< 0x00000060 */
+#define OPAMP_CSR_VMSEL                  OPAMP_CSR_VMSEL_Msk                   /*!< Inverting input selection */
+#define OPAMP_CSR_VMSEL_0                (0x1UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000020 */
+#define OPAMP_CSR_VMSEL_1                (0x2UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000040 */
+
+#define OPAMP_CSR_OPAHSM_Pos             (8U)
+#define OPAMP_CSR_OPAHSM_Msk             (0x1UL << OPAMP_CSR_OPAHSM_Pos)       /*!< 0x00000100 */
+#define OPAMP_CSR_OPAHSM                 OPAMP_CSR_OPAHSM_Msk                  /*!< Operational amplifier high speed mode */
+#define OPAMP_CSR_CALON_Pos              (11U)
+#define OPAMP_CSR_CALON_Msk              (0x1UL << OPAMP_CSR_CALON_Pos)        /*!< 0x00000800 */
+#define OPAMP_CSR_CALON                  OPAMP_CSR_CALON_Msk                   /*!< Calibration mode enable */
+
+#define OPAMP_CSR_CALSEL_Pos             (12U)
+#define OPAMP_CSR_CALSEL_Msk             (0x3UL << OPAMP_CSR_CALSEL_Pos)       /*!< 0x00003000 */
+#define OPAMP_CSR_CALSEL                 OPAMP_CSR_CALSEL_Msk                  /*!< Calibration selection */
+#define OPAMP_CSR_CALSEL_0               (0x1UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00001000 */
+#define OPAMP_CSR_CALSEL_1               (0x2UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00002000 */
+
+#define OPAMP_CSR_PGGAIN_Pos             (14U)
+#define OPAMP_CSR_PGGAIN_Msk             (0xFUL << OPAMP_CSR_PGGAIN_Pos)       /*!< 0x0003C000 */
+#define OPAMP_CSR_PGGAIN                 OPAMP_CSR_PGGAIN_Msk                  /*!< Operational amplifier Programmable amplifier gain value */
+#define OPAMP_CSR_PGGAIN_0               (0x1UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00004000 */
+#define OPAMP_CSR_PGGAIN_1               (0x2UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00008000 */
+#define OPAMP_CSR_PGGAIN_2               (0x4UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00010000 */
+#define OPAMP_CSR_PGGAIN_3               (0x8UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00020000 */
+
+#define OPAMP_CSR_USERTRIM_Pos           (18U)
+#define OPAMP_CSR_USERTRIM_Msk           (0x1UL << OPAMP_CSR_USERTRIM_Pos)     /*!< 0x00040000 */
+#define OPAMP_CSR_USERTRIM               OPAMP_CSR_USERTRIM_Msk                /*!< User trimming enable */
+#define OPAMP_CSR_TSTREF_Pos             (29U)
+#define OPAMP_CSR_TSTREF_Msk             (0x1UL << OPAMP_CSR_TSTREF_Pos)       /*!< 0x20000000 */
+#define OPAMP_CSR_TSTREF                 OPAMP_CSR_TSTREF_Msk                  /*!< OpAmp calibration reference voltage output control */
+#define OPAMP_CSR_CALOUT_Pos             (30U)
+#define OPAMP_CSR_CALOUT_Msk             (0x1UL << OPAMP_CSR_CALOUT_Pos)       /*!< 0x40000000 */
+#define OPAMP_CSR_CALOUT                 OPAMP_CSR_CALOUT_Msk                  /*!< Operational amplifier calibration output */
+
+/*********************  Bit definition for OPAMP1_CSR register  ***************/
+#define OPAMP1_CSR_OPAEN_Pos              (0U)
+#define OPAMP1_CSR_OPAEN_Msk              (0x1UL << OPAMP1_CSR_OPAEN_Pos)      /*!< 0x00000001 */
+#define OPAMP1_CSR_OPAEN                  OPAMP1_CSR_OPAEN_Msk                 /*!< Operational amplifier1 Enable */
+#define OPAMP1_CSR_FORCEVP_Pos            (1U)
+#define OPAMP1_CSR_FORCEVP_Msk            (0x1UL << OPAMP1_CSR_FORCEVP_Pos)    /*!< 0x00000002 */
+#define OPAMP1_CSR_FORCEVP                OPAMP1_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */
+
+#define OPAMP1_CSR_VPSEL_Pos              (2U)
+#define OPAMP1_CSR_VPSEL_Msk              (0x3UL << OPAMP1_CSR_VPSEL_Pos)      /*!< 0x0000000C */
+#define OPAMP1_CSR_VPSEL                  OPAMP1_CSR_VPSEL_Msk                 /*!< Non inverted input selection */
+#define OPAMP1_CSR_VPSEL_0                (0x1UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000004 */
+#define OPAMP1_CSR_VPSEL_1                (0x2UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000008 */
+
+#define OPAMP1_CSR_VMSEL_Pos              (5U)
+#define OPAMP1_CSR_VMSEL_Msk              (0x3UL << OPAMP1_CSR_VMSEL_Pos)      /*!< 0x00000060 */
+#define OPAMP1_CSR_VMSEL                  OPAMP1_CSR_VMSEL_Msk                 /*!< Inverting input selection */
+#define OPAMP1_CSR_VMSEL_0                (0x1UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000020 */
+#define OPAMP1_CSR_VMSEL_1                (0x2UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000040 */
+
+#define OPAMP1_CSR_OPAHSM_Pos             (8U)
+#define OPAMP1_CSR_OPAHSM_Msk             (0x1UL << OPAMP1_CSR_OPAHSM_Pos)     /*!< 0x00000100 */
+#define OPAMP1_CSR_OPAHSM                 OPAMP1_CSR_OPAHSM_Msk                /*!< Operational amplifier1 high speed mode */
+#define OPAMP1_CSR_CALON_Pos              (11U)
+#define OPAMP1_CSR_CALON_Msk              (0x1UL << OPAMP1_CSR_CALON_Pos)      /*!< 0x00000800 */
+#define OPAMP1_CSR_CALON                  OPAMP1_CSR_CALON_Msk                 /*!< Calibration mode enable */
+
+#define OPAMP1_CSR_CALSEL_Pos             (12U)
+#define OPAMP1_CSR_CALSEL_Msk             (0x3UL << OPAMP1_CSR_CALSEL_Pos)     /*!< 0x00003000 */
+#define OPAMP1_CSR_CALSEL                 OPAMP1_CSR_CALSEL_Msk                /*!< Calibration selection */
+#define OPAMP1_CSR_CALSEL_0               (0x1UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00001000 */
+#define OPAMP1_CSR_CALSEL_1               (0x2UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00002000 */
+
+#define OPAMP1_CSR_PGGAIN_Pos             (14U)
+#define OPAMP1_CSR_PGGAIN_Msk             (0xFUL << OPAMP1_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */
+#define OPAMP1_CSR_PGGAIN                 OPAMP1_CSR_PGGAIN_Msk                /*!< Operational amplifier1 Programmable amplifier gain value */
+#define OPAMP1_CSR_PGGAIN_0               (0x1UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00004000 */
+#define OPAMP1_CSR_PGGAIN_1               (0x2UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00008000 */
+#define OPAMP1_CSR_PGGAIN_2               (0x4UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00010000 */
+#define OPAMP1_CSR_PGGAIN_3               (0x8UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00020000 */
+
+#define OPAMP1_CSR_USERTRIM_Pos           (18U)
+#define OPAMP1_CSR_USERTRIM_Msk           (0x1UL << OPAMP1_CSR_USERTRIM_Pos)   /*!< 0x00040000 */
+#define OPAMP1_CSR_USERTRIM               OPAMP1_CSR_USERTRIM_Msk              /*!< User trimming enable */
+#define OPAMP1_CSR_TSTREF_Pos             (29U)
+#define OPAMP1_CSR_TSTREF_Msk             (0x1UL << OPAMP1_CSR_TSTREF_Pos)     /*!< 0x20000000 */
+#define OPAMP1_CSR_TSTREF                 OPAMP1_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */
+#define OPAMP1_CSR_CALOUT_Pos             (30U)
+#define OPAMP1_CSR_CALOUT_Msk             (0x1UL << OPAMP1_CSR_CALOUT_Pos)     /*!< 0x40000000 */
+#define OPAMP1_CSR_CALOUT                 OPAMP1_CSR_CALOUT_Msk                /*!< Operational amplifier1 calibration output */
+
+/*********************  Bit definition for OPAMP2_CSR register  ***************/
+#define OPAMP2_CSR_OPAEN_Pos              (0U)
+#define OPAMP2_CSR_OPAEN_Msk              (0x1UL << OPAMP2_CSR_OPAEN_Pos)      /*!< 0x00000001 */
+#define OPAMP2_CSR_OPAEN                  OPAMP2_CSR_OPAEN_Msk                 /*!< Operational amplifier2 Enable */
+#define OPAMP2_CSR_FORCEVP_Pos            (1U)
+#define OPAMP2_CSR_FORCEVP_Msk            (0x1UL << OPAMP2_CSR_FORCEVP_Pos)    /*!< 0x00000002 */
+#define OPAMP2_CSR_FORCEVP                OPAMP2_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */
+
+#define OPAMP2_CSR_VPSEL_Pos              (2U)
+#define OPAMP2_CSR_VPSEL_Msk              (0x3UL << OPAMP2_CSR_VPSEL_Pos)      /*!< 0x0000000C */
+#define OPAMP2_CSR_VPSEL                  OPAMP2_CSR_VPSEL_Msk                 /*!< Non inverted input selection */
+#define OPAMP2_CSR_VPSEL_0                (0x1UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000004 */
+#define OPAMP2_CSR_VPSEL_1                (0x2UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000008 */
+
+#define OPAMP2_CSR_VMSEL_Pos              (5U)
+#define OPAMP2_CSR_VMSEL_Msk              (0x3UL << OPAMP2_CSR_VMSEL_Pos)      /*!< 0x00000060 */
+#define OPAMP2_CSR_VMSEL                  OPAMP2_CSR_VMSEL_Msk                 /*!< Inverting input selection */
+#define OPAMP2_CSR_VMSEL_0                (0x1UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000020 */
+#define OPAMP2_CSR_VMSEL_1                (0x2UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000040 */
+
+#define OPAMP2_CSR_OPAHSM_Pos             (8U)
+#define OPAMP2_CSR_OPAHSM_Msk             (0x1UL << OPAMP2_CSR_OPAHSM_Pos)     /*!< 0x00000100 */
+#define OPAMP2_CSR_OPAHSM                 OPAMP2_CSR_OPAHSM_Msk                /*!< Operational amplifier2 high speed mode */
+#define OPAMP2_CSR_CALON_Pos              (11U)
+#define OPAMP2_CSR_CALON_Msk              (0x1UL << OPAMP2_CSR_CALON_Pos)      /*!< 0x00000800 */
+#define OPAMP2_CSR_CALON                  OPAMP2_CSR_CALON_Msk                 /*!< Calibration mode enable */
+
+#define OPAMP2_CSR_CALSEL_Pos             (12U)
+#define OPAMP2_CSR_CALSEL_Msk             (0x3UL << OPAMP2_CSR_CALSEL_Pos)     /*!< 0x00003000 */
+#define OPAMP2_CSR_CALSEL                 OPAMP2_CSR_CALSEL_Msk                /*!< Calibration selection */
+#define OPAMP2_CSR_CALSEL_0               (0x1UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00001000 */
+#define OPAMP2_CSR_CALSEL_1               (0x2UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00002000 */
+
+#define OPAMP2_CSR_PGGAIN_Pos             (14U)
+#define OPAMP2_CSR_PGGAIN_Msk             (0xFUL << OPAMP2_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */
+#define OPAMP2_CSR_PGGAIN                 OPAMP2_CSR_PGGAIN_Msk                /*!< Operational amplifier2 Programmable amplifier gain value */
+#define OPAMP2_CSR_PGGAIN_0               (0x1UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00004000 */
+#define OPAMP2_CSR_PGGAIN_1               (0x2UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00008000 */
+#define OPAMP2_CSR_PGGAIN_2               (0x4UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00010000 */
+#define OPAMP2_CSR_PGGAIN_3               (0x8UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00020000 */
+
+#define OPAMP2_CSR_USERTRIM_Pos           (18U)
+#define OPAMP2_CSR_USERTRIM_Msk           (0x1UL << OPAMP2_CSR_USERTRIM_Pos)   /*!< 0x00040000 */
+#define OPAMP2_CSR_USERTRIM               OPAMP2_CSR_USERTRIM_Msk              /*!< User trimming enable */
+#define OPAMP2_CSR_TSTREF_Pos             (29U)
+#define OPAMP2_CSR_TSTREF_Msk             (0x1UL << OPAMP2_CSR_TSTREF_Pos)     /*!< 0x20000000 */
+#define OPAMP2_CSR_TSTREF                 OPAMP2_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */
+#define OPAMP2_CSR_CALOUT_Pos             (30U)
+#define OPAMP2_CSR_CALOUT_Msk             (0x1UL << OPAMP2_CSR_CALOUT_Pos)     /*!< 0x40000000 */
+#define OPAMP2_CSR_CALOUT                 OPAMP2_CSR_CALOUT_Msk                /*!< Operational amplifier2 calibration output */
+
+/*******************  Bit definition for OPAMP_OTR register  ******************/
+#define OPAMP_OTR_TRIMOFFSETN_Pos        (0U)
+#define OPAMP_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP_OTR_TRIMOFFSETN            OPAMP_OTR_TRIMOFFSETN_Msk             /*!< Trim for NMOS differential pairs */
+#define OPAMP_OTR_TRIMOFFSETP_Pos        (8U)
+#define OPAMP_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP_OTR_TRIMOFFSETP            OPAMP_OTR_TRIMOFFSETP_Msk             /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP1_OTR register  ******************/
+#define OPAMP1_OTR_TRIMOFFSETN_Pos        (0U)
+#define OPAMP1_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP1_OTR_TRIMOFFSETN            OPAMP1_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */
+#define OPAMP1_OTR_TRIMOFFSETP_Pos        (8U)
+#define OPAMP1_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP1_OTR_TRIMOFFSETP            OPAMP1_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP2_OTR register  ******************/
+#define OPAMP2_OTR_TRIMOFFSETN_Pos        (0U)
+#define OPAMP2_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP2_OTR_TRIMOFFSETN            OPAMP2_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */
+#define OPAMP2_OTR_TRIMOFFSETP_Pos        (8U)
+#define OPAMP2_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP2_OTR_TRIMOFFSETP            OPAMP2_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP_HSOTR register  ****************/
+#define OPAMP_HSOTR_TRIMHSOFFSETN_Pos    (0U)
+#define OPAMP_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP_HSOTR_TRIMHSOFFSETN        OPAMP_HSOTR_TRIMHSOFFSETN_Msk         /*!< Trim for NMOS differential pairs */
+#define OPAMP_HSOTR_TRIMHSOFFSETP_Pos    (8U)
+#define OPAMP_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP_HSOTR_TRIMHSOFFSETP        OPAMP_HSOTR_TRIMHSOFFSETP_Msk         /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP1_HSOTR register  ****************/
+#define OPAMP1_HSOTR_TRIMHSOFFSETN_Pos    (0U)
+#define OPAMP1_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP1_HSOTR_TRIMHSOFFSETN        OPAMP1_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */
+#define OPAMP1_HSOTR_TRIMHSOFFSETP_Pos    (8U)
+#define OPAMP1_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP1_HSOTR_TRIMHSOFFSETP        OPAMP1_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP2_HSOTR register  ****************/
+#define OPAMP2_HSOTR_TRIMHSOFFSETN_Pos    (0U)
+#define OPAMP2_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP2_HSOTR_TRIMHSOFFSETN        OPAMP2_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */
+#define OPAMP2_HSOTR_TRIMHSOFFSETP_Pos    (8U)
+#define OPAMP2_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP2_HSOTR_TRIMHSOFFSETP        OPAMP2_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             Power Control                                  */
+/*                                                                            */
+/******************************************************************************/
+/*************************  NUMBER OF POWER DOMAINS  **************************/
+#define POWER_DOMAINS_NUMBER           3U                                      /*!< 3 Domains */
+
+/********************  Bit definition for PWR_CR1 register  *******************/
+#define PWR_CR1_ALS_Pos                (17U)
+#define PWR_CR1_ALS_Msk                (0x3UL << PWR_CR1_ALS_Pos)              /*!< 0x00060000 */
+#define PWR_CR1_ALS                    PWR_CR1_ALS_Msk                         /*!< Analog Voltage Detector level selection */
+#define PWR_CR1_ALS_0                  (0x1UL << PWR_CR1_ALS_Pos)              /*!< 0x00020000 */
+#define PWR_CR1_ALS_1                  (0x2UL << PWR_CR1_ALS_Pos)              /*!< 0x00040000 */
+#define PWR_CR1_AVDEN_Pos              (16U)
+#define PWR_CR1_AVDEN_Msk              (0x1UL << PWR_CR1_AVDEN_Pos)            /*!< 0x00010000 */
+#define PWR_CR1_AVDEN                  PWR_CR1_AVDEN_Msk                       /*!< Analog Voltage Detector Enable */
+#define PWR_CR1_SVOS_Pos               (14U)
+#define PWR_CR1_SVOS_Msk               (0x3UL << PWR_CR1_SVOS_Pos)             /*!< 0x0000C000 */
+#define PWR_CR1_SVOS                   PWR_CR1_SVOS_Msk                        /*!< System STOP mode Voltage Scaling selection */
+#define PWR_CR1_SVOS_0                 (0x1UL << PWR_CR1_SVOS_Pos)             /*!< 0x00004000 */
+#define PWR_CR1_SVOS_1                 (0x2UL << PWR_CR1_SVOS_Pos)             /*!< 0x00008000 */
+#define PWR_CR1_FLPS_Pos               (9U)
+#define PWR_CR1_FLPS_Msk               (0x1UL << PWR_CR1_FLPS_Pos)             /*!< 0x00000200 */
+#define PWR_CR1_FLPS                   PWR_CR1_FLPS_Msk                        /*!< Flash low power mode in DSTOP */
+#define PWR_CR1_DBP_Pos                (8U)
+#define PWR_CR1_DBP_Msk                (0x1UL << PWR_CR1_DBP_Pos)              /*!< 0x00000100 */
+#define PWR_CR1_DBP                    PWR_CR1_DBP_Msk                         /*!< Disable Back-up domain Protection */
+#define PWR_CR1_PLS_Pos                (5U)
+#define PWR_CR1_PLS_Msk                (0x7UL << PWR_CR1_PLS_Pos)              /*!< 0x000000E0 */
+#define PWR_CR1_PLS                    PWR_CR1_PLS_Msk                         /*!< Programmable Voltage Detector level selection */
+#define PWR_CR1_PLS_0                  (0x1UL << PWR_CR1_PLS_Pos)              /*!< 0x00000020 */
+#define PWR_CR1_PLS_1                  (0x2UL << PWR_CR1_PLS_Pos)              /*!< 0x00000040 */
+#define PWR_CR1_PLS_2                  (0x4UL << PWR_CR1_PLS_Pos)              /*!< 0x00000080 */
+#define PWR_CR1_PVDEN_Pos              (4U)
+#define PWR_CR1_PVDEN_Msk              (0x1UL << PWR_CR1_PVDEN_Pos)            /*!< 0x00000010 */
+#define PWR_CR1_PVDEN                  PWR_CR1_PVDEN_Msk                       /*!< Programmable Voltage detector enable */
+#define PWR_CR1_LPDS_Pos               (0U)
+#define PWR_CR1_LPDS_Msk               (0x1UL << PWR_CR1_LPDS_Pos)             /*!< 0x00000001 */
+#define PWR_CR1_LPDS                   PWR_CR1_LPDS_Msk                        /*!< Low Power Deepsleep with SVOS3 */
+
+/*!< PVD level configuration */
+#define PWR_CR1_PLS_LEV0               (0UL)                                   /*!< PVD level 0 */
+#define PWR_CR1_PLS_LEV1_Pos           (5U)
+#define PWR_CR1_PLS_LEV1_Msk           (0x1UL << PWR_CR1_PLS_LEV1_Pos)         /*!< 0x00000020 */
+#define PWR_CR1_PLS_LEV1               PWR_CR1_PLS_LEV1_Msk                    /*!< PVD level 1 */
+#define PWR_CR1_PLS_LEV2_Pos           (6U)
+#define PWR_CR1_PLS_LEV2_Msk           (0x1UL << PWR_CR1_PLS_LEV2_Pos)         /*!< 0x00000040 */
+#define PWR_CR1_PLS_LEV2               PWR_CR1_PLS_LEV2_Msk                    /*!< PVD level 2 */
+#define PWR_CR1_PLS_LEV3_Pos           (5U)
+#define PWR_CR1_PLS_LEV3_Msk           (0x3UL << PWR_CR1_PLS_LEV3_Pos)         /*!< 0x00000060 */
+#define PWR_CR1_PLS_LEV3               PWR_CR1_PLS_LEV3_Msk                    /*!< PVD level 3 */
+#define PWR_CR1_PLS_LEV4_Pos           (7U)
+#define PWR_CR1_PLS_LEV4_Msk           (0x1UL << PWR_CR1_PLS_LEV4_Pos)         /*!< 0x00000080 */
+#define PWR_CR1_PLS_LEV4               PWR_CR1_PLS_LEV4_Msk                    /*!< PVD level 4 */
+#define PWR_CR1_PLS_LEV5_Pos           (5U)
+#define PWR_CR1_PLS_LEV5_Msk           (0x5UL << PWR_CR1_PLS_LEV5_Pos)         /*!< 0x000000A0 */
+#define PWR_CR1_PLS_LEV5               PWR_CR1_PLS_LEV5_Msk                    /*!< PVD level 5 */
+#define PWR_CR1_PLS_LEV6_Pos           (6U)
+#define PWR_CR1_PLS_LEV6_Msk           (0x3UL << PWR_CR1_PLS_LEV6_Pos)         /*!< 0x000000C0 */
+#define PWR_CR1_PLS_LEV6               PWR_CR1_PLS_LEV6_Msk                    /*!< PVD level 6 */
+#define PWR_CR1_PLS_LEV7_Pos           (5U)
+#define PWR_CR1_PLS_LEV7_Msk           (0x7UL << PWR_CR1_PLS_LEV7_Pos)         /*!< 0x000000E0 */
+#define PWR_CR1_PLS_LEV7               PWR_CR1_PLS_LEV7_Msk                    /*!< PVD level 7 */
+
+/*!< AVD level configuration */
+#define PWR_CR1_ALS_LEV0               (0UL)                                   /*!< AVD level 0 */
+#define PWR_CR1_ALS_LEV1_Pos           (17U)
+#define PWR_CR1_ALS_LEV1_Msk           (0x1UL << PWR_CR1_ALS_LEV1_Pos)         /*!< 0x00020000 */
+#define PWR_CR1_ALS_LEV1               PWR_CR1_ALS_LEV1_Msk                    /*!< AVD level 1 */
+#define PWR_CR1_ALS_LEV2_Pos           (18U)
+#define PWR_CR1_ALS_LEV2_Msk           (0x1UL << PWR_CR1_ALS_LEV2_Pos)         /*!< 0x00040000 */
+#define PWR_CR1_ALS_LEV2               PWR_CR1_ALS_LEV2_Msk                    /*!< AVD level 2 */
+#define PWR_CR1_ALS_LEV3_Pos           (17U)
+#define PWR_CR1_ALS_LEV3_Msk           (0x3UL << PWR_CR1_ALS_LEV3_Pos)         /*!< 0x00060000 */
+#define PWR_CR1_ALS_LEV3               PWR_CR1_ALS_LEV3_Msk                    /*!< AVD level 3 */
+
+/********************  Bit definition for PWR_CSR1 register  ******************/
+#define PWR_CSR1_AVDO_Pos              (16U)
+#define PWR_CSR1_AVDO_Msk              (0x1UL << PWR_CSR1_AVDO_Pos)            /*!< 0x00010000 */
+#define PWR_CSR1_AVDO                  PWR_CSR1_AVDO_Msk                       /*!< Analog Voltage Detect Output */
+#define PWR_CSR1_ACTVOS_Pos            (14U)
+#define PWR_CSR1_ACTVOS_Msk            (0x3UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x0000C000 */
+#define PWR_CSR1_ACTVOS                PWR_CSR1_ACTVOS_Msk                     /*!< Current actual used VOS for VDD11 Voltage Scaling */
+#define PWR_CSR1_ACTVOS_0              (0x1UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00004000 */
+#define PWR_CSR1_ACTVOS_1              (0x2UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00008000 */
+#define PWR_CSR1_ACTVOSRDY_Pos         (13U)
+#define PWR_CSR1_ACTVOSRDY_Msk         (0x1UL << PWR_CSR1_ACTVOSRDY_Pos)       /*!< 0x00002000 */
+#define PWR_CSR1_ACTVOSRDY             PWR_CSR1_ACTVOSRDY_Msk                  /*!< Ready bit for current actual used VOS for VDD11 Voltage Scaling  */
+#define PWR_CSR1_PVDO_Pos              (4U)
+#define PWR_CSR1_PVDO_Msk              (0x1UL << PWR_CSR1_PVDO_Pos)            /*!< 0x00000010 */
+#define PWR_CSR1_PVDO                  PWR_CSR1_PVDO_Msk                       /*!< Programmable Voltage Detect Output */
+
+/********************  Bit definition for PWR_CR2 register  *******************/
+#define PWR_CR2_TEMPH_Pos              (23U)
+#define PWR_CR2_TEMPH_Msk              (0x1UL << PWR_CR2_TEMPH_Pos)            /*!< 0x00800000 */
+#define PWR_CR2_TEMPH                  PWR_CR2_TEMPH_Msk                       /*!< Monitored temperature level above high threshold */
+#define PWR_CR2_TEMPL_Pos              (22U)
+#define PWR_CR2_TEMPL_Msk              (0x1UL << PWR_CR2_TEMPL_Pos)            /*!< 0x00400000 */
+#define PWR_CR2_TEMPL                  PWR_CR2_TEMPL_Msk                       /*!< Monitored temperature level above low threshold */
+#define PWR_CR2_VBATH_Pos              (21U)
+#define PWR_CR2_VBATH_Msk              (0x1UL << PWR_CR2_VBATH_Pos)            /*!< 0x00200000 */
+#define PWR_CR2_VBATH                  PWR_CR2_VBATH_Msk                       /*!< Monitored VBAT level above high threshold */
+#define PWR_CR2_VBATL_Pos              (20U)
+#define PWR_CR2_VBATL_Msk              (0x1UL << PWR_CR2_VBATL_Pos)            /*!< 0x00100000 */
+#define PWR_CR2_VBATL                  PWR_CR2_VBATL_Msk                       /*!< Monitored VBAT level above low threshold */
+#define PWR_CR2_BRRDY_Pos              (16U)
+#define PWR_CR2_BRRDY_Msk              (0x1UL << PWR_CR2_BRRDY_Pos)            /*!< 0x00010000 */
+#define PWR_CR2_BRRDY                  PWR_CR2_BRRDY_Msk                       /*!< Backup regulator ready */
+#define PWR_CR2_MONEN_Pos              (4U)
+#define PWR_CR2_MONEN_Msk              (0x1UL << PWR_CR2_MONEN_Pos)            /*!< 0x00000010 */
+#define PWR_CR2_MONEN                  PWR_CR2_MONEN_Msk                       /*!< VBAT and temperature monitoring enable */
+#define PWR_CR2_BREN_Pos               (0U)
+#define PWR_CR2_BREN_Msk               (0x1UL << PWR_CR2_BREN_Pos)             /*!< 0x00000001 */
+#define PWR_CR2_BREN                   PWR_CR2_BREN_Msk                        /*!< Backup regulator enable */
+
+/********************  Bit definition for PWR_CR3 register  *******************/
+#define PWR_CR3_USB33RDY_Pos           (26U)
+#define PWR_CR3_USB33RDY_Msk           (0x1UL << PWR_CR3_USB33RDY_Pos)         /*!< 0x04000000 */
+#define PWR_CR3_USB33RDY               PWR_CR3_USB33RDY_Msk                    /*!< USB supply ready */
+#define PWR_CR3_USBREGEN_Pos           (25U)
+#define PWR_CR3_USBREGEN_Msk           (0x1UL << PWR_CR3_USBREGEN_Pos)         /*!< 0x02000000 */
+#define PWR_CR3_USBREGEN               PWR_CR3_USBREGEN_Msk                    /*!< USB regulator enable */
+#define PWR_CR3_USB33DEN_Pos           (24U)
+#define PWR_CR3_USB33DEN_Msk           (0x1UL << PWR_CR3_USB33DEN_Pos)         /*!< 0x01000000 */
+#define PWR_CR3_USB33DEN               PWR_CR3_USB33DEN_Msk                    /*!< VDD33_USB voltage level detector enable */
+#define PWR_CR3_VBRS_Pos               (9U)
+#define PWR_CR3_VBRS_Msk               (0x1UL << PWR_CR3_VBRS_Pos)             /*!< 0x00000200 */
+#define PWR_CR3_VBRS                   PWR_CR3_VBRS_Msk                        /*!< VBAT charging resistor selection */
+#define PWR_CR3_VBE_Pos                (8U)
+#define PWR_CR3_VBE_Msk                (0x1UL << PWR_CR3_VBE_Pos)              /*!< 0x00000100 */
+#define PWR_CR3_VBE                    PWR_CR3_VBE_Msk                         /*!< VBAT charging enable */
+#define PWR_CR3_SCUEN_Pos              (2U)
+#define PWR_CR3_SCUEN_Msk              (0x1UL << PWR_CR3_SCUEN_Pos)            /*!< 0x00000004 */
+#define PWR_CR3_SCUEN                  PWR_CR3_SCUEN_Msk                       /*!< Supply configuration update enable */
+#define PWR_CR3_LDOEN_Pos              (1U)
+#define PWR_CR3_LDOEN_Msk              (0x1UL << PWR_CR3_LDOEN_Pos)            /*!< 0x00000002 */
+#define PWR_CR3_LDOEN                  PWR_CR3_LDOEN_Msk                       /*!< Low Drop Output regulator enable */
+#define PWR_CR3_BYPASS_Pos             (0U)
+#define PWR_CR3_BYPASS_Msk             (0x1UL << PWR_CR3_BYPASS_Pos)           /*!< 0x00000001 */
+#define PWR_CR3_BYPASS                 PWR_CR3_BYPASS_Msk                      /*!< Power Management Unit bypass */
+
+/********************  Bit definition for PWR_CPUCR register  *****************/
+#define PWR_CPUCR_RUN_D3_Pos           (11U)
+#define PWR_CPUCR_RUN_D3_Msk           (0x1UL << PWR_CPUCR_RUN_D3_Pos)         /*!< 0x00000800 */
+#define PWR_CPUCR_RUN_D3               PWR_CPUCR_RUN_D3_Msk                    /*!< Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes */
+#define PWR_CPUCR_CSSF_Pos             (9U)
+#define PWR_CPUCR_CSSF_Msk             (0x1UL << PWR_CPUCR_CSSF_Pos)           /*!< 0x00000200 */
+#define PWR_CPUCR_CSSF                 PWR_CPUCR_CSSF_Msk                      /*!< Clear D1 domain CPU1 STANDBY, STOP and HOLD flags */
+#define PWR_CPUCR_SBF_D2_Pos           (8U)
+#define PWR_CPUCR_SBF_D2_Msk           (0x1UL << PWR_CPUCR_SBF_D2_Pos)         /*!< 0x00000100 */
+#define PWR_CPUCR_SBF_D2               PWR_CPUCR_SBF_D2_Msk                    /*!< D2 domain DSTANDBY Flag */
+#define PWR_CPUCR_SBF_D1_Pos           (7U)
+#define PWR_CPUCR_SBF_D1_Msk           (0x1UL << PWR_CPUCR_SBF_D1_Pos)         /*!< 0x00000080 */
+#define PWR_CPUCR_SBF_D1               PWR_CPUCR_SBF_D1_Msk                    /*!< D1 domain DSTANDBY Flag */
+#define PWR_CPUCR_SBF_Pos              (6U)
+#define PWR_CPUCR_SBF_Msk              (0x1UL << PWR_CPUCR_SBF_Pos)            /*!< 0x00000040 */
+#define PWR_CPUCR_SBF                  PWR_CPUCR_SBF_Msk                       /*!< System STANDBY Flag */
+#define PWR_CPUCR_STOPF_Pos            (5U)
+#define PWR_CPUCR_STOPF_Msk            (0x1UL << PWR_CPUCR_STOPF_Pos)          /*!< 0x00000020 */
+#define PWR_CPUCR_STOPF                PWR_CPUCR_STOPF_Msk                     /*!< STOP Flag */
+#define PWR_CPUCR_PDDS_D3_Pos          (2U)
+#define PWR_CPUCR_PDDS_D3_Msk          (0x1UL << PWR_CPUCR_PDDS_D3_Pos)        /*!< 0x00000004 */
+#define PWR_CPUCR_PDDS_D3              PWR_CPUCR_PDDS_D3_Msk                   /*!< System D3 domain Power Down Deepsleep */
+#define PWR_CPUCR_PDDS_D2_Pos          (1U)
+#define PWR_CPUCR_PDDS_D2_Msk          (0x1UL << PWR_CPUCR_PDDS_D2_Pos)        /*!< 0x00000002 */
+#define PWR_CPUCR_PDDS_D2              PWR_CPUCR_PDDS_D2_Msk                   /*!< D2 domain Power Down Deepsleep */
+#define PWR_CPUCR_PDDS_D1_Pos          (0U)
+#define PWR_CPUCR_PDDS_D1_Msk          (0x1UL << PWR_CPUCR_PDDS_D1_Pos)        /*!< 0x00000001 */
+#define PWR_CPUCR_PDDS_D1              PWR_CPUCR_PDDS_D1_Msk                   /*!< D1 domain Power Down Deepsleep selection */
+
+
+/********************  Bit definition for PWR_D3CR register  ******************/
+#define PWR_D3CR_VOS_Pos               (14U)
+#define PWR_D3CR_VOS_Msk               (0x3UL << PWR_D3CR_VOS_Pos)             /*!< 0x0000C000 */
+#define PWR_D3CR_VOS                   PWR_D3CR_VOS_Msk                        /*!< Voltage Scaling selection according performance */
+#define PWR_D3CR_VOS_0                 (0x1UL << PWR_D3CR_VOS_Pos)             /*!< 0x00004000 */
+#define PWR_D3CR_VOS_1                 (0x2UL << PWR_D3CR_VOS_Pos)             /*!< 0x00008000 */
+#define PWR_D3CR_VOSRDY_Pos            (13U)
+#define PWR_D3CR_VOSRDY_Msk            (0x1UL << PWR_D3CR_VOSRDY_Pos)          /*!< 0x00002000 */
+#define PWR_D3CR_VOSRDY                PWR_D3CR_VOSRDY_Msk                     /*!< VOS Ready bit for VDD11 Voltage Scaling output selection */
+
+/******************  Bit definition for PWR_WKUPCR register  ******************/
+#define PWR_WKUPCR_WKUPC6_Pos          (5U)
+#define PWR_WKUPCR_WKUPC6_Msk          (0x1UL << PWR_WKUPCR_WKUPC6_Pos)        /*!< 0x00000020 */
+#define PWR_WKUPCR_WKUPC6              PWR_WKUPCR_WKUPC6_Msk                   /*!< Clear Wakeup Pin Flag 6 */
+#define PWR_WKUPCR_WKUPC5_Pos          (4U)
+#define PWR_WKUPCR_WKUPC5_Msk          (0x1UL << PWR_WKUPCR_WKUPC5_Pos)        /*!< 0x00000010 */
+#define PWR_WKUPCR_WKUPC5              PWR_WKUPCR_WKUPC5_Msk                   /*!< Clear Wakeup Pin Flag 5 */
+#define PWR_WKUPCR_WKUPC4_Pos          (3U)
+#define PWR_WKUPCR_WKUPC4_Msk          (0x1UL << PWR_WKUPCR_WKUPC4_Pos)        /*!< 0x00000008 */
+#define PWR_WKUPCR_WKUPC4              PWR_WKUPCR_WKUPC4_Msk                   /*!< Clear Wakeup Pin Flag 4 */
+#define PWR_WKUPCR_WKUPC3_Pos          (2U)
+#define PWR_WKUPCR_WKUPC3_Msk          (0x1UL << PWR_WKUPCR_WKUPC3_Pos)        /*!< 0x00000004 */
+#define PWR_WKUPCR_WKUPC3              PWR_WKUPCR_WKUPC3_Msk                   /*!< Clear Wakeup Pin Flag 3 */
+#define PWR_WKUPCR_WKUPC2_Pos          (1U)
+#define PWR_WKUPCR_WKUPC2_Msk          (0x1UL << PWR_WKUPCR_WKUPC2_Pos)        /*!< 0x00000002 */
+#define PWR_WKUPCR_WKUPC2              PWR_WKUPCR_WKUPC2_Msk                   /*!< Clear Wakeup Pin Flag 2 */
+#define PWR_WKUPCR_WKUPC1_Pos          (0U)
+#define PWR_WKUPCR_WKUPC1_Msk          (0x1UL << PWR_WKUPCR_WKUPC1_Pos)        /*!< 0x00000001 */
+#define PWR_WKUPCR_WKUPC1              PWR_WKUPCR_WKUPC1_Msk                   /*!< Clear Wakeup Pin Flag 1 */
+
+/********************  Bit definition for PWR_WKUPFR register  ****************/
+#define PWR_WKUPFR_WKUPF6_Pos          (5U)
+#define PWR_WKUPFR_WKUPF6_Msk          (0x1UL << PWR_WKUPFR_WKUPF6_Pos)        /*!< 0x00000020 */
+#define PWR_WKUPFR_WKUPF6              PWR_WKUPFR_WKUPF6_Msk                   /*!< Wakeup Pin Flag 6 */
+#define PWR_WKUPFR_WKUPF5_Pos          (4U)
+#define PWR_WKUPFR_WKUPF5_Msk          (0x1UL << PWR_WKUPFR_WKUPF5_Pos)        /*!< 0x00000010 */
+#define PWR_WKUPFR_WKUPF5              PWR_WKUPFR_WKUPF5_Msk                   /*!< Wakeup Pin Flag 5 */
+#define PWR_WKUPFR_WKUPF4_Pos          (3U)
+#define PWR_WKUPFR_WKUPF4_Msk          (0x1UL << PWR_WKUPFR_WKUPF4_Pos)        /*!< 0x00000008 */
+#define PWR_WKUPFR_WKUPF4              PWR_WKUPFR_WKUPF4_Msk                   /*!< Wakeup Pin Flag 4 */
+#define PWR_WKUPFR_WKUPF3_Pos          (2U)
+#define PWR_WKUPFR_WKUPF3_Msk          (0x1UL << PWR_WKUPFR_WKUPF3_Pos)        /*!< 0x00000004 */
+#define PWR_WKUPFR_WKUPF3              PWR_WKUPFR_WKUPF3_Msk                   /*!< Wakeup Pin Flag 3 */
+#define PWR_WKUPFR_WKUPF2_Pos          (1U)
+#define PWR_WKUPFR_WKUPF2_Msk          (0x1UL << PWR_WKUPFR_WKUPF2_Pos)        /*!< 0x00000002 */
+#define PWR_WKUPFR_WKUPF2              PWR_WKUPFR_WKUPF2_Msk                   /*!< Wakeup Pin Flag 2 */
+#define PWR_WKUPFR_WKUPF1_Pos          (0U)
+#define PWR_WKUPFR_WKUPF1_Msk          (0x1UL << PWR_WKUPFR_WKUPF1_Pos)        /*!< 0x00000001 */
+#define PWR_WKUPFR_WKUPF1              PWR_WKUPFR_WKUPF1_Msk                   /*!< Wakeup Pin Flag 1 */
+
+/******************  Bit definition for PWR_WKUPEPR register  *****************/
+#define PWR_WKUPEPR_WKUPPUPD6_Pos      (26U)
+#define PWR_WKUPEPR_WKUPPUPD6_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x0C000000 */
+#define PWR_WKUPEPR_WKUPPUPD6          PWR_WKUPEPR_WKUPPUPD6_Msk               /*!< Wakeup Pin pull configuration for WKUP6 */
+#define PWR_WKUPEPR_WKUPPUPD6_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x04000000 */
+#define PWR_WKUPEPR_WKUPPUPD6_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x08000000 */
+#define PWR_WKUPEPR_WKUPPUPD5_Pos      (24U)
+#define PWR_WKUPEPR_WKUPPUPD5_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x03000000 */
+#define PWR_WKUPEPR_WKUPPUPD5          PWR_WKUPEPR_WKUPPUPD5_Msk               /*!< Wakeup Pin pull configuration for WKUP5 */
+#define PWR_WKUPEPR_WKUPPUPD5_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x01000000 */
+#define PWR_WKUPEPR_WKUPPUPD5_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x02000000 */
+#define PWR_WKUPEPR_WKUPPUPD4_Pos      (22U)
+#define PWR_WKUPEPR_WKUPPUPD4_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00C00000 */
+#define PWR_WKUPEPR_WKUPPUPD4          PWR_WKUPEPR_WKUPPUPD4_Msk               /*!< Wakeup Pin pull configuration for WKUP4 */
+#define PWR_WKUPEPR_WKUPPUPD4_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00400000 */
+#define PWR_WKUPEPR_WKUPPUPD4_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00800000 */
+#define PWR_WKUPEPR_WKUPPUPD3_Pos      (20U)
+#define PWR_WKUPEPR_WKUPPUPD3_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00300000 */
+#define PWR_WKUPEPR_WKUPPUPD3          PWR_WKUPEPR_WKUPPUPD3_Msk               /*!< Wakeup Pin pull configuration for WKUP3 */
+#define PWR_WKUPEPR_WKUPPUPD3_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00100000 */
+#define PWR_WKUPEPR_WKUPPUPD3_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00200000 */
+#define PWR_WKUPEPR_WKUPPUPD2_Pos      (18U)
+#define PWR_WKUPEPR_WKUPPUPD2_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x000C0000 */
+#define PWR_WKUPEPR_WKUPPUPD2          PWR_WKUPEPR_WKUPPUPD2_Msk               /*!< Wakeup Pin pull configuration for WKUP2 */
+#define PWR_WKUPEPR_WKUPPUPD2_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00040000 */
+#define PWR_WKUPEPR_WKUPPUPD2_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00080000 */
+#define PWR_WKUPEPR_WKUPPUPD1_Pos      (16U)
+#define PWR_WKUPEPR_WKUPPUPD1_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00030000 */
+#define PWR_WKUPEPR_WKUPPUPD1          PWR_WKUPEPR_WKUPPUPD1_Msk               /*!< Wakeup Pin pull configuration for WKUP1 */
+#define PWR_WKUPEPR_WKUPPUPD1_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00010000 */
+#define PWR_WKUPEPR_WKUPPUPD1_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00020000 */
+#define PWR_WKUPEPR_WKUPP6_Pos         (13U)
+#define PWR_WKUPEPR_WKUPP6_Msk         (0x1UL << PWR_WKUPEPR_WKUPP6_Pos)       /*!< 0x00002000 */
+#define PWR_WKUPEPR_WKUPP6             PWR_WKUPEPR_WKUPP6_Msk                  /*!< Wakeup Pin Polarity for WKUP6 */
+#define PWR_WKUPEPR_WKUPP5_Pos         (12U)
+#define PWR_WKUPEPR_WKUPP5_Msk         (0x1UL << PWR_WKUPEPR_WKUPP5_Pos)       /*!< 0x00001000 */
+#define PWR_WKUPEPR_WKUPP5             PWR_WKUPEPR_WKUPP5_Msk                  /*!< Wakeup Pin Polarity for WKUP5 */
+#define PWR_WKUPEPR_WKUPP4_Pos         (11U)
+#define PWR_WKUPEPR_WKUPP4_Msk         (0x1UL << PWR_WKUPEPR_WKUPP4_Pos)       /*!< 0x00000800 */
+#define PWR_WKUPEPR_WKUPP4             PWR_WKUPEPR_WKUPP4_Msk                  /*!< Wakeup Pin Polarity for WKUP4 */
+#define PWR_WKUPEPR_WKUPP3_Pos         (10U)
+#define PWR_WKUPEPR_WKUPP3_Msk         (0x1UL << PWR_WKUPEPR_WKUPP3_Pos)       /*!< 0x00000400 */
+#define PWR_WKUPEPR_WKUPP3             PWR_WKUPEPR_WKUPP3_Msk                  /*!< Wakeup Pin Polarity for WKUP3 */
+#define PWR_WKUPEPR_WKUPP2_Pos         (9U)
+#define PWR_WKUPEPR_WKUPP2_Msk         (0x1UL << PWR_WKUPEPR_WKUPP2_Pos)       /*!< 0x00000200 */
+#define PWR_WKUPEPR_WKUPP2             PWR_WKUPEPR_WKUPP2_Msk                  /*!< Wakeup Pin Polarity for WKUP2 */
+#define PWR_WKUPEPR_WKUPP1_Pos         (8U)
+#define PWR_WKUPEPR_WKUPP1_Msk         (0x1UL << PWR_WKUPEPR_WKUPP1_Pos)       /*!< 0x00000100 */
+#define PWR_WKUPEPR_WKUPP1             PWR_WKUPEPR_WKUPP1_Msk                  /*!< Wakeup Pin Polarity for WKUP1 */
+#define PWR_WKUPEPR_WKUPEN6_Pos        (5U)
+#define PWR_WKUPEPR_WKUPEN6_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN6_Pos)      /*!< 0x00000020 */
+#define PWR_WKUPEPR_WKUPEN6            PWR_WKUPEPR_WKUPEN6_Msk                 /*!< Enable Wakeup Pin WKUP6 */
+#define PWR_WKUPEPR_WKUPEN5_Pos        (4U)
+#define PWR_WKUPEPR_WKUPEN5_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN5_Pos)      /*!< 0x00000010 */
+#define PWR_WKUPEPR_WKUPEN5            PWR_WKUPEPR_WKUPEN5_Msk                 /*!< Enable Wakeup Pin WKUP5 */
+#define PWR_WKUPEPR_WKUPEN4_Pos        (3U)
+#define PWR_WKUPEPR_WKUPEN4_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos)      /*!< 0x00000008 */
+#define PWR_WKUPEPR_WKUPEN4            PWR_WKUPEPR_WKUPEN4_Msk                 /*!< Enable Wakeup Pin WKUP4 */
+#define PWR_WKUPEPR_WKUPEN3_Pos        (2U)
+#define PWR_WKUPEPR_WKUPEN3_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos)      /*!< 0x00000004 */
+#define PWR_WKUPEPR_WKUPEN3            PWR_WKUPEPR_WKUPEN3_Msk                 /*!< Enable Wakeup Pin WKUP3 */
+#define PWR_WKUPEPR_WKUPEN2_Pos        (1U)
+#define PWR_WKUPEPR_WKUPEN2_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos)      /*!< 0x00000002 */
+#define PWR_WKUPEPR_WKUPEN2            PWR_WKUPEPR_WKUPEN2_Msk                 /*!< Enable Wakeup Pin WKUP2 */
+#define PWR_WKUPEPR_WKUPEN1_Pos        (0U)
+#define PWR_WKUPEPR_WKUPEN1_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos)      /*!< 0x00000001 */
+#define PWR_WKUPEPR_WKUPEN1            PWR_WKUPEPR_WKUPEN1_Msk                 /*!< Enable Wakeup Pin WKUP1 */
+#define PWR_WKUPEPR_WKUPEN_Pos         (0U)
+#define PWR_WKUPEPR_WKUPEN_Msk         (0x3FUL << PWR_WKUPEPR_WKUPEN_Pos)      /*!< 0x0000003F */
+#define PWR_WKUPEPR_WKUPEN             PWR_WKUPEPR_WKUPEN_Msk                  /*!< Enable all Wakeup Pin */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Reset and Clock Control                            */
+/*                                                                            */
+/******************************************************************************/
+/*******************************  RCC VERSION  ********************************/
+#define RCC_VER_X
+
+/********************  Bit definition for RCC_CR register  ********************/
+#define RCC_CR_HSION_Pos                       (0U)
+#define RCC_CR_HSION_Msk                       (0x1UL << RCC_CR_HSION_Pos)     /*!< 0x00000001 */
+#define RCC_CR_HSION                           RCC_CR_HSION_Msk                /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIKERON_Pos                    (1U)
+#define RCC_CR_HSIKERON_Msk                    (0x1UL << RCC_CR_HSIKERON_Pos)  /*!< 0x00000002 */
+#define RCC_CR_HSIKERON                        RCC_CR_HSIKERON_Msk             /*!< Internal High Speed clock enable for some IPs Kernel */
+#define RCC_CR_HSIRDY_Pos                      (2U)
+#define RCC_CR_HSIRDY_Msk                      (0x1UL << RCC_CR_HSIRDY_Pos)    /*!< 0x00000004 */
+#define RCC_CR_HSIRDY                          RCC_CR_HSIRDY_Msk               /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSIDIV_Pos                      (3U)
+#define RCC_CR_HSIDIV_Msk                      (0x3UL << RCC_CR_HSIDIV_Pos)    /*!< 0x00000018 */
+#define RCC_CR_HSIDIV                          RCC_CR_HSIDIV_Msk               /*!< Internal High Speed clock divider selection */
+#define RCC_CR_HSIDIV_1                        (0x0UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000000 */
+#define RCC_CR_HSIDIV_2                        (0x1UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000008 */
+#define RCC_CR_HSIDIV_4                        (0x2UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000010 */
+#define RCC_CR_HSIDIV_8                        (0x3UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000018 */
+
+#define RCC_CR_HSIDIVF_Pos                     (5U)
+#define RCC_CR_HSIDIVF_Msk                     (0x1UL << RCC_CR_HSIDIVF_Pos)   /*!< 0x00000020 */
+#define RCC_CR_HSIDIVF                         RCC_CR_HSIDIVF_Msk              /*!< HSI Divider flag */
+#define RCC_CR_CSION_Pos                       (7U)
+#define RCC_CR_CSION_Msk                       (0x1UL << RCC_CR_CSION_Pos)     /*!< 0x00000080 */
+#define RCC_CR_CSION                           RCC_CR_CSION_Msk                /*!< The Internal RC 4MHz oscillator clock enable */
+#define RCC_CR_CSIRDY_Pos                      (8U)
+#define RCC_CR_CSIRDY_Msk                      (0x1UL << RCC_CR_CSIRDY_Pos)    /*!< 0x00000100 */
+#define RCC_CR_CSIRDY                          RCC_CR_CSIRDY_Msk               /*!< The Internal RC 4MHz oscillator clock ready */
+#define RCC_CR_CSIKERON_Pos                    (9U)
+#define RCC_CR_CSIKERON_Msk                    (0x1UL << RCC_CR_CSIKERON_Pos)  /*!< 0x00000200 */
+#define RCC_CR_CSIKERON                        RCC_CR_CSIKERON_Msk             /*!< Internal RC 4MHz oscillator clock enable for some IPs Kernel */
+#define RCC_CR_HSI48ON_Pos                     (12U)
+#define RCC_CR_HSI48ON_Msk                     (0x1UL << RCC_CR_HSI48ON_Pos)   /*!< 0x00001000 */
+#define RCC_CR_HSI48ON                         RCC_CR_HSI48ON_Msk              /*!< HSI48 clock enable clock enable  */
+#define RCC_CR_HSI48RDY_Pos                    (13U)
+#define RCC_CR_HSI48RDY_Msk                    (0x1UL << RCC_CR_HSI48RDY_Pos)  /*!< 0x00002000 */
+#define RCC_CR_HSI48RDY                        RCC_CR_HSI48RDY_Msk             /*!< HSI48 clock ready */
+
+#define RCC_CR_D1CKRDY_Pos                     (14U)
+#define RCC_CR_D1CKRDY_Msk                     (0x1UL << RCC_CR_D1CKRDY_Pos)   /*!< 0x00004000 */
+#define RCC_CR_D1CKRDY                         RCC_CR_D1CKRDY_Msk              /*!< D1 domain clocks ready flag  */
+#define RCC_CR_D2CKRDY_Pos                     (15U)
+#define RCC_CR_D2CKRDY_Msk                     (0x1UL << RCC_CR_D2CKRDY_Pos)   /*!< 0x00008000 */
+#define RCC_CR_D2CKRDY                         RCC_CR_D2CKRDY_Msk              /*!< D2 domain clocks ready flag */
+
+#define RCC_CR_HSEON_Pos                       (16U)
+#define RCC_CR_HSEON_Msk                       (0x1UL << RCC_CR_HSEON_Pos)     /*!< 0x00010000 */
+#define RCC_CR_HSEON                           RCC_CR_HSEON_Msk                /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY_Pos                      (17U)
+#define RCC_CR_HSERDY_Msk                      (0x1UL << RCC_CR_HSERDY_Pos)    /*!< 0x00020000 */
+#define RCC_CR_HSERDY                          RCC_CR_HSERDY_Msk               /*!< External High Speed clock ready */
+#define RCC_CR_HSEBYP_Pos                      (18U)
+#define RCC_CR_HSEBYP_Msk                      (0x1UL << RCC_CR_HSEBYP_Pos)    /*!< 0x00040000 */
+#define RCC_CR_HSEBYP                          RCC_CR_HSEBYP_Msk               /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSHSEON_Pos                    (19U)
+#define RCC_CR_CSSHSEON_Msk                    (0x1UL << RCC_CR_CSSHSEON_Pos)  /*!< 0x00080000 */
+#define RCC_CR_CSSHSEON                        RCC_CR_CSSHSEON_Msk             /*!< HSE Clock security System enable */
+
+
+#define RCC_CR_PLL1ON_Pos                      (24U)
+#define RCC_CR_PLL1ON_Msk                      (0x1UL << RCC_CR_PLL1ON_Pos)    /*!< 0x01000000 */
+#define RCC_CR_PLL1ON                          RCC_CR_PLL1ON_Msk               /*!< System PLL1 clock enable */
+#define RCC_CR_PLL1RDY_Pos                     (25U)
+#define RCC_CR_PLL1RDY_Msk                     (0x1UL << RCC_CR_PLL1RDY_Pos)   /*!< 0x02000000 */
+#define RCC_CR_PLL1RDY                         RCC_CR_PLL1RDY_Msk              /*!< System PLL1 clock ready */
+#define RCC_CR_PLL2ON_Pos                      (26U)
+#define RCC_CR_PLL2ON_Msk                      (0x1UL << RCC_CR_PLL2ON_Pos)    /*!< 0x04000000 */
+#define RCC_CR_PLL2ON                          RCC_CR_PLL2ON_Msk               /*!< System PLL2 clock enable */
+#define RCC_CR_PLL2RDY_Pos                     (27U)
+#define RCC_CR_PLL2RDY_Msk                     (0x1UL << RCC_CR_PLL2RDY_Pos)   /*!< 0x08000000 */
+#define RCC_CR_PLL2RDY                         RCC_CR_PLL2RDY_Msk              /*!< System PLL2 clock ready */
+#define RCC_CR_PLL3ON_Pos                      (28U)
+#define RCC_CR_PLL3ON_Msk                      (0x1UL << RCC_CR_PLL3ON_Pos)    /*!< 0x10000000 */
+#define RCC_CR_PLL3ON                          RCC_CR_PLL3ON_Msk               /*!< System PLL3 clock enable */
+#define RCC_CR_PLL3RDY_Pos                     (29U)
+#define RCC_CR_PLL3RDY_Msk                     (0x1UL << RCC_CR_PLL3RDY_Pos)   /*!< 0x20000000 */
+#define RCC_CR_PLL3RDY                         RCC_CR_PLL3RDY_Msk              /*!< System PLL3 clock ready */
+
+/*Legacy */
+#define RCC_CR_PLLON_Pos                       (24U)
+#define RCC_CR_PLLON_Msk                       (0x1UL << RCC_CR_PLLON_Pos)     /*!< 0x01000000 */
+#define RCC_CR_PLLON                           RCC_CR_PLLON_Msk                /*!< System PLL clock enable */
+#define RCC_CR_PLLRDY_Pos                      (25U)
+#define RCC_CR_PLLRDY_Msk                      (0x1UL << RCC_CR_PLLRDY_Pos)    /*!< 0x02000000 */
+#define RCC_CR_PLLRDY                          RCC_CR_PLLRDY_Msk               /*!< System PLL clock ready */
+
+/********************  Bit definition for RCC_HSICFGR register  ***************/
+/*!< HSICAL configuration */
+#define RCC_HSICFGR_HSICAL_Pos                 (0U)
+#define RCC_HSICFGR_HSICAL_Msk                 (0xFFFUL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000FFF */
+#define RCC_HSICFGR_HSICAL                     RCC_HSICFGR_HSICAL_Msk          /*!< HSICAL[11:0] bits */
+#define RCC_HSICFGR_HSICAL_0                   (0x001UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000001 */
+#define RCC_HSICFGR_HSICAL_1                   (0x002UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000002 */
+#define RCC_HSICFGR_HSICAL_2                   (0x004UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000004 */
+#define RCC_HSICFGR_HSICAL_3                   (0x008UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000008 */
+#define RCC_HSICFGR_HSICAL_4                   (0x010UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000010 */
+#define RCC_HSICFGR_HSICAL_5                   (0x020UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000020 */
+#define RCC_HSICFGR_HSICAL_6                   (0x040UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000040 */
+#define RCC_HSICFGR_HSICAL_7                   (0x080UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000080 */
+#define RCC_HSICFGR_HSICAL_8                   (0x100UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000100 */
+#define RCC_HSICFGR_HSICAL_9                   (0x200UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000200 */
+#define RCC_HSICFGR_HSICAL_10                  (0x400UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000400 */
+#define RCC_HSICFGR_HSICAL_11                  (0x800UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000800 */
+
+/*!< HSITRIM configuration */
+#define RCC_HSICFGR_HSITRIM_Pos                (24U)
+#define RCC_HSICFGR_HSITRIM_Msk                (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x7F000000 */
+#define RCC_HSICFGR_HSITRIM                    RCC_HSICFGR_HSITRIM_Msk         /*!< HSITRIM[6:0] bits */
+#define RCC_HSICFGR_HSITRIM_0                  (0x01UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x01000000 */
+#define RCC_HSICFGR_HSITRIM_1                  (0x02UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x02000000 */
+#define RCC_HSICFGR_HSITRIM_2                  (0x04UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x04000000 */
+#define RCC_HSICFGR_HSITRIM_3                  (0x08UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x08000000 */
+#define RCC_HSICFGR_HSITRIM_4                  (0x10UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x10000000 */
+#define RCC_HSICFGR_HSITRIM_5                  (0x20UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x20000000 */
+#define RCC_HSICFGR_HSITRIM_6                  (0x40UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x40000000 */
+
+
+/********************  Bit definition for RCC_CRRCR register  *****************/
+
+/*!< HSI48CAL configuration */
+#define RCC_CRRCR_HSI48CAL_Pos                 (0U)
+#define RCC_CRRCR_HSI48CAL_Msk                 (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x000003FF */
+#define RCC_CRRCR_HSI48CAL                     RCC_CRRCR_HSI48CAL_Msk          /*!< HSI48CAL[9:0] bits */
+#define RCC_CRRCR_HSI48CAL_0                   (0x001UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000001 */
+#define RCC_CRRCR_HSI48CAL_1                   (0x002UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000002 */
+#define RCC_CRRCR_HSI48CAL_2                   (0x004UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000004 */
+#define RCC_CRRCR_HSI48CAL_3                   (0x008UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000008 */
+#define RCC_CRRCR_HSI48CAL_4                   (0x010UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000010 */
+#define RCC_CRRCR_HSI48CAL_5                   (0x020UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000020 */
+#define RCC_CRRCR_HSI48CAL_6                   (0x040UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000040 */
+#define RCC_CRRCR_HSI48CAL_7                   (0x080UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */
+#define RCC_CRRCR_HSI48CAL_8                   (0x100UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */
+#define RCC_CRRCR_HSI48CAL_9                   (0x200UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */
+
+
+/********************  Bit definition for RCC_CSICFGR register  *****************/
+/*!< CSICAL configuration */
+#define RCC_CSICFGR_CSICAL_Pos                 (0U)
+#define RCC_CSICFGR_CSICAL_Msk                 (0xFFUL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x000000FF */
+#define RCC_CSICFGR_CSICAL                     RCC_CSICFGR_CSICAL_Msk          /*!< CSICAL[7:0] bits */
+#define RCC_CSICFGR_CSICAL_0                   (0x01UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000001 */
+#define RCC_CSICFGR_CSICAL_1                   (0x02UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000002 */
+#define RCC_CSICFGR_CSICAL_2                   (0x04UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000004 */
+#define RCC_CSICFGR_CSICAL_3                   (0x08UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000008 */
+#define RCC_CSICFGR_CSICAL_4                   (0x10UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000010 */
+#define RCC_CSICFGR_CSICAL_5                   (0x20UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000020 */
+#define RCC_CSICFGR_CSICAL_6                   (0x40UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000040 */
+#define RCC_CSICFGR_CSICAL_7                   (0x80UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000080 */
+
+/*!< CSITRIM configuration */
+#define RCC_CSICFGR_CSITRIM_Pos                (24U)
+#define RCC_CSICFGR_CSITRIM_Msk                (0x3FUL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x3F000000 */
+#define RCC_CSICFGR_CSITRIM                    RCC_CSICFGR_CSITRIM_Msk         /*!< CSITRIM[5:0] bits */
+#define RCC_CSICFGR_CSITRIM_0                  (0x01UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x01000000 */
+#define RCC_CSICFGR_CSITRIM_1                  (0x02UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x02000000 */
+#define RCC_CSICFGR_CSITRIM_2                  (0x04UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x04000000 */
+#define RCC_CSICFGR_CSITRIM_3                  (0x08UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x08000000 */
+#define RCC_CSICFGR_CSITRIM_4                  (0x10UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x10000000 */
+#define RCC_CSICFGR_CSITRIM_5                  (0x20UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x20000000 */
+
+/********************  Bit definition for RCC_CFGR register  ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos                        (0U)
+#define RCC_CFGR_SW_Msk                        (0x7UL << RCC_CFGR_SW_Pos)           /*!< 0x00000007 */
+#define RCC_CFGR_SW                            RCC_CFGR_SW_Msk                     /*!< SW[2:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0                          (0x1UL << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */
+#define RCC_CFGR_SW_1                          (0x2UL << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */
+#define RCC_CFGR_SW_2                          (0x4UL << RCC_CFGR_SW_Pos)           /*!< 0x00000004 */
+
+#define RCC_CFGR_SW_HSI                        (0x00000000UL)                       /*!< HSI selection as system clock */
+#define RCC_CFGR_SW_CSI                        (0x00000001UL)                       /*!< CSI selection as system clock */
+#define RCC_CFGR_SW_HSE                        (0x00000002UL)                       /*!< HSE selection as system clock */
+#define RCC_CFGR_SW_PLL1                       (0x00000003UL)                       /*!< PLL1 selection as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos                       (3U)
+#define RCC_CFGR_SWS_Msk                       (0x7UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000038 */
+#define RCC_CFGR_SWS                           RCC_CFGR_SWS_Msk                    /*!< SWS[2:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0                         (0x1UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */
+#define RCC_CFGR_SWS_1                         (0x2UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000010 */
+#define RCC_CFGR_SWS_2                         (0x4UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000020 */
+
+#define RCC_CFGR_SWS_HSI                       (0x00000000UL)                       /*!< HSI used as system clock */
+#define RCC_CFGR_SWS_CSI                       (0x00000008UL)                       /*!< CSI used as system clock */
+#define RCC_CFGR_SWS_HSE                       (0x00000010UL)                       /*!< HSE used as system clock */
+#define RCC_CFGR_SWS_PLL1                      (0x00000018UL)                       /*!< PLL1 used as system clock */
+
+#define RCC_CFGR_STOPWUCK_Pos                  (6U)
+#define RCC_CFGR_STOPWUCK_Msk                  (0x1UL << RCC_CFGR_STOPWUCK_Pos)     /*!< 0x00000040 */
+#define RCC_CFGR_STOPWUCK                      RCC_CFGR_STOPWUCK_Msk                /*!< Wake Up from stop and CSS backup clock selection */
+
+#define RCC_CFGR_STOPKERWUCK_Pos               (7U)
+#define RCC_CFGR_STOPKERWUCK_Msk               (0x1UL << RCC_CFGR_STOPKERWUCK_Pos)  /*!< 0x00000080 */
+#define RCC_CFGR_STOPKERWUCK                   RCC_CFGR_STOPKERWUCK_Msk             /*!< Kernel Clock Selection after a Wake Up from STOP */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE_Pos                    (8U)
+#define RCC_CFGR_RTCPRE_Msk                    (0x3FUL << RCC_CFGR_RTCPRE_Pos)
+#define RCC_CFGR_RTCPRE                        RCC_CFGR_RTCPRE_Msk                  /*!< 0x00003F00 */
+#define RCC_CFGR_RTCPRE_0                      (0x1UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000100 */
+#define RCC_CFGR_RTCPRE_1                      (0x2UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000200 */
+#define RCC_CFGR_RTCPRE_2                      (0x4UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000400 */
+#define RCC_CFGR_RTCPRE_3                      (0x8UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000800 */
+#define RCC_CFGR_RTCPRE_4                      (0x10UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00001000 */
+#define RCC_CFGR_RTCPRE_5                      (0x20UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00002000 */
+
+/*!< HRTIMSEL configuration */
+#define RCC_CFGR_HRTIMSEL_Pos                  (14U)
+#define RCC_CFGR_HRTIMSEL_Msk                  (0x1UL << RCC_CFGR_HRTIMSEL_Pos)
+#define RCC_CFGR_HRTIMSEL                      RCC_CFGR_HRTIMSEL_Msk                /*!< 0x00004000 */
+
+/*!< TIMPRE configuration */
+#define RCC_CFGR_TIMPRE_Pos                    (15U)
+#define RCC_CFGR_TIMPRE_Msk                    (0x1UL << RCC_CFGR_TIMPRE_Pos)
+#define RCC_CFGR_TIMPRE                        RCC_CFGR_TIMPRE_Msk                  /*!< 0x00008000 */
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1_Pos                      (22U)
+#define RCC_CFGR_MCO1_Msk                      (0x7UL << RCC_CFGR_MCO1_Pos)
+#define RCC_CFGR_MCO1                          RCC_CFGR_MCO1_Msk                       /*!< 0x01C00000 */
+#define RCC_CFGR_MCO1_0                        (0x1UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00400000 */
+#define RCC_CFGR_MCO1_1                        (0x2UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00800000 */
+#define RCC_CFGR_MCO1_2                        (0x4UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x01000000 */
+
+#define RCC_CFGR_MCO1PRE_Pos                   (18U)
+#define RCC_CFGR_MCO1PRE_Msk                   (0xFUL << RCC_CFGR_MCO1PRE_Pos)
+#define RCC_CFGR_MCO1PRE                       RCC_CFGR_MCO1PRE_Msk                    /*!< 0x003C0000 */
+#define RCC_CFGR_MCO1PRE_0                     (0x1UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00040000 */
+#define RCC_CFGR_MCO1PRE_1                     (0x2UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00080000 */
+#define RCC_CFGR_MCO1PRE_2                     (0x4UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00100000 */
+#define RCC_CFGR_MCO1PRE_3                     (0x8UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00200000 */
+
+#define RCC_CFGR_MCO2PRE_Pos                   (25U)
+#define RCC_CFGR_MCO2PRE_Msk                   (0xFUL << RCC_CFGR_MCO2PRE_Pos)
+#define RCC_CFGR_MCO2PRE                       RCC_CFGR_MCO2PRE_Msk                    /*!< 0x1E000000 */
+#define RCC_CFGR_MCO2PRE_0                     (0x1UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x02000000 */
+#define RCC_CFGR_MCO2PRE_1                     (0x2UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x04000000 */
+#define RCC_CFGR_MCO2PRE_2                     (0x4UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x08000000 */
+#define RCC_CFGR_MCO2PRE_3                     (0x8UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x10000000 */
+
+#define RCC_CFGR_MCO2_Pos                      (29U)
+#define RCC_CFGR_MCO2_Msk                      (0x7UL << RCC_CFGR_MCO2_Pos)
+#define RCC_CFGR_MCO2                          RCC_CFGR_MCO2_Msk                       /*!< 0xE0000000 */
+#define RCC_CFGR_MCO2_0                        (0x1UL << RCC_CFGR_MCO2_Pos)             /*!< 0x20000000 */
+#define RCC_CFGR_MCO2_1                        (0x2UL << RCC_CFGR_MCO2_Pos)             /*!< 0x40000000 */
+#define RCC_CFGR_MCO2_2                        (0x4UL << RCC_CFGR_MCO2_Pos)             /*!< 0x80000000 */
+
+/********************  Bit definition for RCC_D1CFGR register  ******************/
+/*!< D1HPRE configuration */
+#define RCC_D1CFGR_HPRE_Pos                    (0U)
+#define RCC_D1CFGR_HPRE_Msk                    (0xFUL << RCC_D1CFGR_HPRE_Pos)  /*!< 0x0000000F */
+#define RCC_D1CFGR_HPRE                        RCC_D1CFGR_HPRE_Msk             /*!< HPRE[3:0] bits (AHB3 prescaler) */
+#define RCC_D1CFGR_HPRE_0                      (0x1UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000001 */
+#define RCC_D1CFGR_HPRE_1                      (0x2UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000002 */
+#define RCC_D1CFGR_HPRE_2                      (0x4UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000004 */
+#define RCC_D1CFGR_HPRE_3                      (0x8UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000008 */
+
+
+#define RCC_D1CFGR_HPRE_DIV1                   ((uint32_t)0x00000000)          /*!< AHB3 Clock not divided */
+#define RCC_D1CFGR_HPRE_DIV2_Pos               (3U)
+#define RCC_D1CFGR_HPRE_DIV2_Msk               (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */
+#define RCC_D1CFGR_HPRE_DIV2                   RCC_D1CFGR_HPRE_DIV2_Msk        /*!< AHB3 Clock divided by 2 */
+#define RCC_D1CFGR_HPRE_DIV4_Pos               (0U)
+#define RCC_D1CFGR_HPRE_DIV4_Msk               (0x9UL << RCC_D1CFGR_HPRE_DIV4_Pos) /*!< 0x00000009 */
+#define RCC_D1CFGR_HPRE_DIV4                   RCC_D1CFGR_HPRE_DIV4_Msk        /*!< AHB3 Clock divided by 4 */
+#define RCC_D1CFGR_HPRE_DIV8_Pos               (1U)
+#define RCC_D1CFGR_HPRE_DIV8_Msk               (0x5UL << RCC_D1CFGR_HPRE_DIV8_Pos) /*!< 0x0000000A */
+#define RCC_D1CFGR_HPRE_DIV8                   RCC_D1CFGR_HPRE_DIV8_Msk        /*!< AHB3 Clock divided by 8 */
+#define RCC_D1CFGR_HPRE_DIV16_Pos              (0U)
+#define RCC_D1CFGR_HPRE_DIV16_Msk              (0xBUL << RCC_D1CFGR_HPRE_DIV16_Pos) /*!< 0x0000000B */
+#define RCC_D1CFGR_HPRE_DIV16                  RCC_D1CFGR_HPRE_DIV16_Msk       /*!< AHB3 Clock divided by 16 */
+#define RCC_D1CFGR_HPRE_DIV64_Pos              (2U)
+#define RCC_D1CFGR_HPRE_DIV64_Msk              (0x3UL << RCC_D1CFGR_HPRE_DIV64_Pos) /*!< 0x0000000C */
+#define RCC_D1CFGR_HPRE_DIV64                  RCC_D1CFGR_HPRE_DIV64_Msk       /*!< AHB3 Clock divided by 64 */
+#define RCC_D1CFGR_HPRE_DIV128_Pos             (0U)
+#define RCC_D1CFGR_HPRE_DIV128_Msk             (0xDUL << RCC_D1CFGR_HPRE_DIV128_Pos) /*!< 0x0000000D */
+#define RCC_D1CFGR_HPRE_DIV128                 RCC_D1CFGR_HPRE_DIV128_Msk      /*!< AHB3 Clock divided by 128 */
+#define RCC_D1CFGR_HPRE_DIV256_Pos             (1U)
+#define RCC_D1CFGR_HPRE_DIV256_Msk             (0x7UL << RCC_D1CFGR_HPRE_DIV256_Pos) /*!< 0x0000000E */
+#define RCC_D1CFGR_HPRE_DIV256                 RCC_D1CFGR_HPRE_DIV256_Msk      /*!< AHB3 Clock divided by 256 */
+#define RCC_D1CFGR_HPRE_DIV512_Pos             (0U)
+#define RCC_D1CFGR_HPRE_DIV512_Msk             (0xFUL << RCC_D1CFGR_HPRE_DIV512_Pos) /*!< 0x0000000F */
+#define RCC_D1CFGR_HPRE_DIV512                 RCC_D1CFGR_HPRE_DIV512_Msk      /*!< AHB3 Clock divided by 512 */
+
+/*!< D1PPRE configuration */
+#define RCC_D1CFGR_D1PPRE_Pos                  (4U)
+#define RCC_D1CFGR_D1PPRE_Msk                  (0x7UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000070 */
+#define RCC_D1CFGR_D1PPRE                      RCC_D1CFGR_D1PPRE_Msk           /*!< D1PRE[2:0] bits (APB3 prescaler) */
+#define RCC_D1CFGR_D1PPRE_0                    (0x1UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000010 */
+#define RCC_D1CFGR_D1PPRE_1                    (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */
+#define RCC_D1CFGR_D1PPRE_2                    (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */
+
+#define RCC_D1CFGR_D1PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB3 clock not divided */
+#define RCC_D1CFGR_D1PPRE_DIV2_Pos             (6U)
+#define RCC_D1CFGR_D1PPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */
+#define RCC_D1CFGR_D1PPRE_DIV2                 RCC_D1CFGR_D1PPRE_DIV2_Msk      /*!< APB3 clock divided by 2 */
+#define RCC_D1CFGR_D1PPRE_DIV4_Pos             (4U)
+#define RCC_D1CFGR_D1PPRE_DIV4_Msk             (0x5UL << RCC_D1CFGR_D1PPRE_DIV4_Pos) /*!< 0x00000050 */
+#define RCC_D1CFGR_D1PPRE_DIV4                 RCC_D1CFGR_D1PPRE_DIV4_Msk      /*!< APB3 clock divided by 4 */
+#define RCC_D1CFGR_D1PPRE_DIV8_Pos             (5U)
+#define RCC_D1CFGR_D1PPRE_DIV8_Msk             (0x3UL << RCC_D1CFGR_D1PPRE_DIV8_Pos) /*!< 0x00000060 */
+#define RCC_D1CFGR_D1PPRE_DIV8                 RCC_D1CFGR_D1PPRE_DIV8_Msk      /*!< APB3 clock divided by 8 */
+#define RCC_D1CFGR_D1PPRE_DIV16_Pos            (4U)
+#define RCC_D1CFGR_D1PPRE_DIV16_Msk            (0x7UL << RCC_D1CFGR_D1PPRE_DIV16_Pos) /*!< 0x00000070 */
+#define RCC_D1CFGR_D1PPRE_DIV16                RCC_D1CFGR_D1PPRE_DIV16_Msk     /*!< APB3 clock divided by 16 */
+
+#define RCC_D1CFGR_D1CPRE_Pos                  (8U)
+#define RCC_D1CFGR_D1CPRE_Msk                  (0xFUL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000F00 */
+#define RCC_D1CFGR_D1CPRE                      RCC_D1CFGR_D1CPRE_Msk           /*!< D1CPRE[2:0] bits (Domain 1 Core prescaler) */
+#define RCC_D1CFGR_D1CPRE_0                    (0x1UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000100 */
+#define RCC_D1CFGR_D1CPRE_1                    (0x2UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000200 */
+#define RCC_D1CFGR_D1CPRE_2                    (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */
+#define RCC_D1CFGR_D1CPRE_3                    (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */
+
+#define RCC_D1CFGR_D1CPRE_DIV1                 ((uint32_t)0x00000000)          /*!< Domain 1 Core clock not divided */
+#define RCC_D1CFGR_D1CPRE_DIV2_Pos             (11U)
+#define RCC_D1CFGR_D1CPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */
+#define RCC_D1CFGR_D1CPRE_DIV2                 RCC_D1CFGR_D1CPRE_DIV2_Msk      /*!< Domain 1 Core clock divided by 2 */
+#define RCC_D1CFGR_D1CPRE_DIV4_Pos             (8U)
+#define RCC_D1CFGR_D1CPRE_DIV4_Msk             (0x9UL << RCC_D1CFGR_D1CPRE_DIV4_Pos) /*!< 0x00000900 */
+#define RCC_D1CFGR_D1CPRE_DIV4                 RCC_D1CFGR_D1CPRE_DIV4_Msk      /*!< Domain 1 Core clock divided by 4 */
+#define RCC_D1CFGR_D1CPRE_DIV8_Pos             (9U)
+#define RCC_D1CFGR_D1CPRE_DIV8_Msk             (0x5UL << RCC_D1CFGR_D1CPRE_DIV8_Pos) /*!< 0x00000A00 */
+#define RCC_D1CFGR_D1CPRE_DIV8                 RCC_D1CFGR_D1CPRE_DIV8_Msk      /*!< Domain 1 Core clock divided by 8 */
+#define RCC_D1CFGR_D1CPRE_DIV16_Pos            (8U)
+#define RCC_D1CFGR_D1CPRE_DIV16_Msk            (0xBUL << RCC_D1CFGR_D1CPRE_DIV16_Pos) /*!< 0x00000B00 */
+#define RCC_D1CFGR_D1CPRE_DIV16                RCC_D1CFGR_D1CPRE_DIV16_Msk     /*!< Domain 1 Core clock divided by 16 */
+#define RCC_D1CFGR_D1CPRE_DIV64_Pos            (10U)
+#define RCC_D1CFGR_D1CPRE_DIV64_Msk            (0x3UL << RCC_D1CFGR_D1CPRE_DIV64_Pos) /*!< 0x00000C00 */
+#define RCC_D1CFGR_D1CPRE_DIV64                RCC_D1CFGR_D1CPRE_DIV64_Msk     /*!< Domain 1 Core clock divided by 64 */
+#define RCC_D1CFGR_D1CPRE_DIV128_Pos           (8U)
+#define RCC_D1CFGR_D1CPRE_DIV128_Msk           (0xDUL << RCC_D1CFGR_D1CPRE_DIV128_Pos) /*!< 0x00000D00 */
+#define RCC_D1CFGR_D1CPRE_DIV128               RCC_D1CFGR_D1CPRE_DIV128_Msk    /*!< Domain 1 Core clock divided by 128 */
+#define RCC_D1CFGR_D1CPRE_DIV256_Pos           (9U)
+#define RCC_D1CFGR_D1CPRE_DIV256_Msk           (0x7UL << RCC_D1CFGR_D1CPRE_DIV256_Pos) /*!< 0x00000E00 */
+#define RCC_D1CFGR_D1CPRE_DIV256               RCC_D1CFGR_D1CPRE_DIV256_Msk    /*!< Domain 1 Core clock divided by 256 */
+#define RCC_D1CFGR_D1CPRE_DIV512_Pos           (8U)
+#define RCC_D1CFGR_D1CPRE_DIV512_Msk           (0xFUL << RCC_D1CFGR_D1CPRE_DIV512_Pos) /*!< 0x00000F00 */
+#define RCC_D1CFGR_D1CPRE_DIV512               RCC_D1CFGR_D1CPRE_DIV512_Msk    /*!< Domain 1 Core clock divided by 512 */
+
+/********************  Bit definition for RCC_D2CFGR register  ******************/
+/*!< D2PPRE1 configuration */
+#define RCC_D2CFGR_D2PPRE1_Pos                 (4U)
+#define RCC_D2CFGR_D2PPRE1_Msk                 (0x7UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000070 */
+#define RCC_D2CFGR_D2PPRE1                     RCC_D2CFGR_D2PPRE1_Msk          /*!< D1PPRE1[2:0] bits (APB1 prescaler) */
+#define RCC_D2CFGR_D2PPRE1_0                   (0x1UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000010 */
+#define RCC_D2CFGR_D2PPRE1_1                   (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */
+#define RCC_D2CFGR_D2PPRE1_2                   (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */
+
+#define RCC_D2CFGR_D2PPRE1_DIV1                ((uint32_t)0x00000000)          /*!< APB1 clock not divided */
+#define RCC_D2CFGR_D2PPRE1_DIV2_Pos            (6U)
+#define RCC_D2CFGR_D2PPRE1_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */
+#define RCC_D2CFGR_D2PPRE1_DIV2                RCC_D2CFGR_D2PPRE1_DIV2_Msk     /*!< APB1 clock divided by 2 */
+#define RCC_D2CFGR_D2PPRE1_DIV4_Pos            (4U)
+#define RCC_D2CFGR_D2PPRE1_DIV4_Msk            (0x5UL << RCC_D2CFGR_D2PPRE1_DIV4_Pos) /*!< 0x00000050 */
+#define RCC_D2CFGR_D2PPRE1_DIV4                RCC_D2CFGR_D2PPRE1_DIV4_Msk     /*!< APB1 clock divided by 4 */
+#define RCC_D2CFGR_D2PPRE1_DIV8_Pos            (5U)
+#define RCC_D2CFGR_D2PPRE1_DIV8_Msk            (0x3UL << RCC_D2CFGR_D2PPRE1_DIV8_Pos) /*!< 0x00000060 */
+#define RCC_D2CFGR_D2PPRE1_DIV8                RCC_D2CFGR_D2PPRE1_DIV8_Msk     /*!< APB1 clock divided by 8 */
+#define RCC_D2CFGR_D2PPRE1_DIV16_Pos           (4U)
+#define RCC_D2CFGR_D2PPRE1_DIV16_Msk           (0x7UL << RCC_D2CFGR_D2PPRE1_DIV16_Pos) /*!< 0x00000070 */
+#define RCC_D2CFGR_D2PPRE1_DIV16               RCC_D2CFGR_D2PPRE1_DIV16_Msk    /*!< APB1 clock divided by 16 */
+
+/*!< D2PPRE2 configuration */
+#define RCC_D2CFGR_D2PPRE2_Pos                 (8U)
+#define RCC_D2CFGR_D2PPRE2_Msk                 (0x7UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000700 */
+#define RCC_D2CFGR_D2PPRE2                     RCC_D2CFGR_D2PPRE2_Msk          /*!< D2PPRE2[2:0] bits (APB2 prescaler) */
+#define RCC_D2CFGR_D2PPRE2_0                   (0x1UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000100 */
+#define RCC_D2CFGR_D2PPRE2_1                   (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */
+#define RCC_D2CFGR_D2PPRE2_2                   (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */
+
+#define RCC_D2CFGR_D2PPRE2_DIV1                ((uint32_t)0x00000000)          /*!< APB2 clock not divided */
+#define RCC_D2CFGR_D2PPRE2_DIV2_Pos            (10U)
+#define RCC_D2CFGR_D2PPRE2_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */
+#define RCC_D2CFGR_D2PPRE2_DIV2                RCC_D2CFGR_D2PPRE2_DIV2_Msk     /*!< APB2 clock divided by 2 */
+#define RCC_D2CFGR_D2PPRE2_DIV4_Pos            (8U)
+#define RCC_D2CFGR_D2PPRE2_DIV4_Msk            (0x5UL << RCC_D2CFGR_D2PPRE2_DIV4_Pos) /*!< 0x00000500 */
+#define RCC_D2CFGR_D2PPRE2_DIV4                RCC_D2CFGR_D2PPRE2_DIV4_Msk     /*!< APB2 clock divided by 4 */
+#define RCC_D2CFGR_D2PPRE2_DIV8_Pos            (9U)
+#define RCC_D2CFGR_D2PPRE2_DIV8_Msk            (0x3UL << RCC_D2CFGR_D2PPRE2_DIV8_Pos) /*!< 0x00000600 */
+#define RCC_D2CFGR_D2PPRE2_DIV8                RCC_D2CFGR_D2PPRE2_DIV8_Msk     /*!< APB2 clock divided by 8 */
+#define RCC_D2CFGR_D2PPRE2_DIV16_Pos           (8U)
+#define RCC_D2CFGR_D2PPRE2_DIV16_Msk           (0x7UL << RCC_D2CFGR_D2PPRE2_DIV16_Pos) /*!< 0x00000700 */
+#define RCC_D2CFGR_D2PPRE2_DIV16               RCC_D2CFGR_D2PPRE2_DIV16_Msk    /*!< APB2 clock divided by 16 */
+
+/********************  Bit definition for RCC_D3CFGR register  ******************/
+/*!< D3PPRE configuration */
+#define RCC_D3CFGR_D3PPRE_Pos                  (4U)
+#define RCC_D3CFGR_D3PPRE_Msk                  (0x7UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000070 */
+#define RCC_D3CFGR_D3PPRE                      RCC_D3CFGR_D3PPRE_Msk           /*!< D3PPRE1[2:0] bits (APB4 prescaler) */
+#define RCC_D3CFGR_D3PPRE_0                    (0x1UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000010 */
+#define RCC_D3CFGR_D3PPRE_1                    (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */
+#define RCC_D3CFGR_D3PPRE_2                    (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */
+
+#define RCC_D3CFGR_D3PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB4 clock not divided */
+#define RCC_D3CFGR_D3PPRE_DIV2_Pos             (6U)
+#define RCC_D3CFGR_D3PPRE_DIV2_Msk             (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */
+#define RCC_D3CFGR_D3PPRE_DIV2                 RCC_D3CFGR_D3PPRE_DIV2_Msk      /*!< APB4 clock divided by 2 */
+#define RCC_D3CFGR_D3PPRE_DIV4_Pos             (4U)
+#define RCC_D3CFGR_D3PPRE_DIV4_Msk             (0x5UL << RCC_D3CFGR_D3PPRE_DIV4_Pos) /*!< 0x00000050 */
+#define RCC_D3CFGR_D3PPRE_DIV4                 RCC_D3CFGR_D3PPRE_DIV4_Msk      /*!< APB4 clock divided by 4 */
+#define RCC_D3CFGR_D3PPRE_DIV8_Pos             (5U)
+#define RCC_D3CFGR_D3PPRE_DIV8_Msk             (0x3UL << RCC_D3CFGR_D3PPRE_DIV8_Pos) /*!< 0x00000060 */
+#define RCC_D3CFGR_D3PPRE_DIV8                 RCC_D3CFGR_D3PPRE_DIV8_Msk      /*!< APB4 clock divided by 8 */
+#define RCC_D3CFGR_D3PPRE_DIV16_Pos            (4U)
+#define RCC_D3CFGR_D3PPRE_DIV16_Msk            (0x7UL << RCC_D3CFGR_D3PPRE_DIV16_Pos) /*!< 0x00000070 */
+#define RCC_D3CFGR_D3PPRE_DIV16                RCC_D3CFGR_D3PPRE_DIV16_Msk     /*!< APB4 clock divided by 16 */
+
+/********************  Bit definition for RCC_PLLCKSELR register  *************/
+
+#define RCC_PLLCKSELR_PLLSRC_Pos               (0U)
+#define RCC_PLLCKSELR_PLLSRC_Msk               (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
+#define RCC_PLLCKSELR_PLLSRC                   RCC_PLLCKSELR_PLLSRC_Msk
+
+#define RCC_PLLCKSELR_PLLSRC_HSI               ((uint32_t)0x00000000)          /*!< HSI source clock selected */
+#define RCC_PLLCKSELR_PLLSRC_CSI_Pos           (0U)
+#define RCC_PLLCKSELR_PLLSRC_CSI_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
+#define RCC_PLLCKSELR_PLLSRC_CSI               RCC_PLLCKSELR_PLLSRC_CSI_Msk    /*!< CSI source clock selected */
+#define RCC_PLLCKSELR_PLLSRC_HSE_Pos           (1U)
+#define RCC_PLLCKSELR_PLLSRC_HSE_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_HSE_Pos) /*!< 0x00000002 */
+#define RCC_PLLCKSELR_PLLSRC_HSE               RCC_PLLCKSELR_PLLSRC_HSE_Msk    /*!< HSE source clock selected */
+#define RCC_PLLCKSELR_PLLSRC_NONE_Pos          (0U)
+#define RCC_PLLCKSELR_PLLSRC_NONE_Msk          (0x3UL << RCC_PLLCKSELR_PLLSRC_NONE_Pos) /*!< 0x00000003 */
+#define RCC_PLLCKSELR_PLLSRC_NONE              RCC_PLLCKSELR_PLLSRC_NONE_Msk   /*!< No source clock selected  */
+
+#define RCC_PLLCKSELR_DIVM1_Pos                (4U)
+#define RCC_PLLCKSELR_DIVM1_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x000003F0 */
+#define RCC_PLLCKSELR_DIVM1                    RCC_PLLCKSELR_DIVM1_Msk
+#define RCC_PLLCKSELR_DIVM1_0                  (0x01UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000010 */
+#define RCC_PLLCKSELR_DIVM1_1                  (0x02UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000020 */
+#define RCC_PLLCKSELR_DIVM1_2                  (0x04UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000040 */
+#define RCC_PLLCKSELR_DIVM1_3                  (0x08UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000080 */
+#define RCC_PLLCKSELR_DIVM1_4                  (0x10UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000100 */
+#define RCC_PLLCKSELR_DIVM1_5                  (0x20UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000200 */
+
+#define RCC_PLLCKSELR_DIVM2_Pos                (12U)
+#define RCC_PLLCKSELR_DIVM2_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x0003F000 */
+#define RCC_PLLCKSELR_DIVM2                    RCC_PLLCKSELR_DIVM2_Msk
+#define RCC_PLLCKSELR_DIVM2_0                  (0x01UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00001000 */
+#define RCC_PLLCKSELR_DIVM2_1                  (0x02UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00002000 */
+#define RCC_PLLCKSELR_DIVM2_2                  (0x04UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00004000 */
+#define RCC_PLLCKSELR_DIVM2_3                  (0x08UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00008000 */
+#define RCC_PLLCKSELR_DIVM2_4                  (0x10UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00010000 */
+#define RCC_PLLCKSELR_DIVM2_5                  (0x20UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00020000 */
+
+#define RCC_PLLCKSELR_DIVM3_Pos                (20U)
+#define RCC_PLLCKSELR_DIVM3_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x03F00000 */
+#define RCC_PLLCKSELR_DIVM3                    RCC_PLLCKSELR_DIVM3_Msk
+#define RCC_PLLCKSELR_DIVM3_0                  (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00100000 */
+#define RCC_PLLCKSELR_DIVM3_1                  (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00200000 */
+#define RCC_PLLCKSELR_DIVM3_2                  (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00400000 */
+#define RCC_PLLCKSELR_DIVM3_3                  (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00800000 */
+#define RCC_PLLCKSELR_DIVM3_4                  (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x01000000 */
+#define RCC_PLLCKSELR_DIVM3_5                  (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 */
+
+/********************  Bit definition for RCC_PLLCFGR register  ***************/
+
+#define RCC_PLLCFGR_PLL1FRACEN_Pos             (0U)
+#define RCC_PLLCFGR_PLL1FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos) /*!< 0x00000001 */
+#define RCC_PLLCFGR_PLL1FRACEN                 RCC_PLLCFGR_PLL1FRACEN_Msk
+#define RCC_PLLCFGR_PLL1VCOSEL_Pos             (1U)
+#define RCC_PLLCFGR_PLL1VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos) /*!< 0x00000002 */
+#define RCC_PLLCFGR_PLL1VCOSEL                 RCC_PLLCFGR_PLL1VCOSEL_Msk
+#define RCC_PLLCFGR_PLL1RGE_Pos                (2U)
+#define RCC_PLLCFGR_PLL1RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
+#define RCC_PLLCFGR_PLL1RGE                    RCC_PLLCFGR_PLL1RGE_Msk
+#define RCC_PLLCFGR_PLL1RGE_0                  (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */
+#define RCC_PLLCFGR_PLL1RGE_1                  (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */
+#define RCC_PLLCFGR_PLL1RGE_2                  (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */
+#define RCC_PLLCFGR_PLL1RGE_3                  (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
+
+#define RCC_PLLCFGR_PLL2FRACEN_Pos             (4U)
+#define RCC_PLLCFGR_PLL2FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos) /*!< 0x00000010 */
+#define RCC_PLLCFGR_PLL2FRACEN                 RCC_PLLCFGR_PLL2FRACEN_Msk
+#define RCC_PLLCFGR_PLL2VCOSEL_Pos             (5U)
+#define RCC_PLLCFGR_PLL2VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos) /*!< 0x00000020 */
+#define RCC_PLLCFGR_PLL2VCOSEL                 RCC_PLLCFGR_PLL2VCOSEL_Msk
+#define RCC_PLLCFGR_PLL2RGE_Pos                (6U)
+#define RCC_PLLCFGR_PLL2RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */
+#define RCC_PLLCFGR_PLL2RGE                    RCC_PLLCFGR_PLL2RGE_Msk
+#define RCC_PLLCFGR_PLL2RGE_0                  (0x0UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000000 */
+#define RCC_PLLCFGR_PLL2RGE_1                  (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000040 */
+#define RCC_PLLCFGR_PLL2RGE_2                  (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000080 */
+#define RCC_PLLCFGR_PLL2RGE_3                  (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */
+
+#define RCC_PLLCFGR_PLL3FRACEN_Pos             (8U)
+#define RCC_PLLCFGR_PLL3FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos) /*!< 0x00000100 */
+#define RCC_PLLCFGR_PLL3FRACEN                 RCC_PLLCFGR_PLL3FRACEN_Msk
+#define RCC_PLLCFGR_PLL3VCOSEL_Pos             (9U)
+#define RCC_PLLCFGR_PLL3VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos) /*!< 0x00000200 */
+#define RCC_PLLCFGR_PLL3VCOSEL                 RCC_PLLCFGR_PLL3VCOSEL_Msk
+#define RCC_PLLCFGR_PLL3RGE_Pos                (10U)
+#define RCC_PLLCFGR_PLL3RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */
+#define RCC_PLLCFGR_PLL3RGE                    RCC_PLLCFGR_PLL3RGE_Msk
+#define RCC_PLLCFGR_PLL3RGE_0                  (0x0UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000000 */
+#define RCC_PLLCFGR_PLL3RGE_1                  (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000400 */
+#define RCC_PLLCFGR_PLL3RGE_2                  (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000800 */
+#define RCC_PLLCFGR_PLL3RGE_3                  (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */
+
+#define RCC_PLLCFGR_DIVP1EN_Pos                (16U)
+#define RCC_PLLCFGR_DIVP1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP1EN_Pos) /*!< 0x00010000 */
+#define RCC_PLLCFGR_DIVP1EN                    RCC_PLLCFGR_DIVP1EN_Msk
+#define RCC_PLLCFGR_DIVQ1EN_Pos                (17U)
+#define RCC_PLLCFGR_DIVQ1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ1EN_Pos) /*!< 0x00020000 */
+#define RCC_PLLCFGR_DIVQ1EN                    RCC_PLLCFGR_DIVQ1EN_Msk
+#define RCC_PLLCFGR_DIVR1EN_Pos                (18U)
+#define RCC_PLLCFGR_DIVR1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR1EN_Pos) /*!< 0x00040000 */
+#define RCC_PLLCFGR_DIVR1EN                    RCC_PLLCFGR_DIVR1EN_Msk
+
+#define RCC_PLLCFGR_DIVP2EN_Pos                (19U)
+#define RCC_PLLCFGR_DIVP2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP2EN_Pos) /*!< 0x00080000 */
+#define RCC_PLLCFGR_DIVP2EN                    RCC_PLLCFGR_DIVP2EN_Msk
+#define RCC_PLLCFGR_DIVQ2EN_Pos                (20U)
+#define RCC_PLLCFGR_DIVQ2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ2EN_Pos) /*!< 0x00100000 */
+#define RCC_PLLCFGR_DIVQ2EN                    RCC_PLLCFGR_DIVQ2EN_Msk
+#define RCC_PLLCFGR_DIVR2EN_Pos                (21U)
+#define RCC_PLLCFGR_DIVR2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR2EN_Pos) /*!< 0x00200000 */
+#define RCC_PLLCFGR_DIVR2EN                    RCC_PLLCFGR_DIVR2EN_Msk
+
+#define RCC_PLLCFGR_DIVP3EN_Pos                (22U)
+#define RCC_PLLCFGR_DIVP3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP3EN_Pos) /*!< 0x00400000 */
+#define RCC_PLLCFGR_DIVP3EN                    RCC_PLLCFGR_DIVP3EN_Msk
+#define RCC_PLLCFGR_DIVQ3EN_Pos                (23U)
+#define RCC_PLLCFGR_DIVQ3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ3EN_Pos) /*!< 0x00800000 */
+#define RCC_PLLCFGR_DIVQ3EN                    RCC_PLLCFGR_DIVQ3EN_Msk
+#define RCC_PLLCFGR_DIVR3EN_Pos                (24U)
+#define RCC_PLLCFGR_DIVR3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR3EN_Pos) /*!< 0x01000000 */
+#define RCC_PLLCFGR_DIVR3EN                    RCC_PLLCFGR_DIVR3EN_Msk
+
+
+/********************  Bit definition for RCC_PLL1DIVR register  ***************/
+#define RCC_PLL1DIVR_N1_Pos                    (0U)
+#define RCC_PLL1DIVR_N1_Msk                    (0x1FFUL << RCC_PLL1DIVR_N1_Pos) /*!< 0x000001FF */
+#define RCC_PLL1DIVR_N1                        RCC_PLL1DIVR_N1_Msk
+#define RCC_PLL1DIVR_P1_Pos                    (9U)
+#define RCC_PLL1DIVR_P1_Msk                    (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */
+#define RCC_PLL1DIVR_P1                        RCC_PLL1DIVR_P1_Msk
+#define RCC_PLL1DIVR_Q1_Pos                    (16U)
+#define RCC_PLL1DIVR_Q1_Msk                    (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */
+#define RCC_PLL1DIVR_Q1                        RCC_PLL1DIVR_Q1_Msk
+#define RCC_PLL1DIVR_R1_Pos                    (24U)
+#define RCC_PLL1DIVR_R1_Msk                    (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
+#define RCC_PLL1DIVR_R1                        RCC_PLL1DIVR_R1_Msk
+
+/********************  Bit definition for RCC_PLL1FRACR register  ***************/
+#define RCC_PLL1FRACR_FRACN1_Pos               (3U)
+#define RCC_PLL1FRACR_FRACN1_Msk               (0x1FFFUL << RCC_PLL1FRACR_FRACN1_Pos) /*!< 0x0000FFF8 */
+#define RCC_PLL1FRACR_FRACN1                   RCC_PLL1FRACR_FRACN1_Msk
+
+/********************  Bit definition for RCC_PLL2DIVR register  ***************/
+#define RCC_PLL2DIVR_N2_Pos                    (0U)
+#define RCC_PLL2DIVR_N2_Msk                    (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */
+#define RCC_PLL2DIVR_N2                        RCC_PLL2DIVR_N2_Msk
+#define RCC_PLL2DIVR_P2_Pos                    (9U)
+#define RCC_PLL2DIVR_P2_Msk                    (0x7FUL << RCC_PLL2DIVR_P2_Pos) /*!< 0x0000FE00 */
+#define RCC_PLL2DIVR_P2                        RCC_PLL2DIVR_P2_Msk
+#define RCC_PLL2DIVR_Q2_Pos                    (16U)
+#define RCC_PLL2DIVR_Q2_Msk                    (0x7FUL << RCC_PLL2DIVR_Q2_Pos) /*!< 0x007F0000 */
+#define RCC_PLL2DIVR_Q2                        RCC_PLL2DIVR_Q2_Msk
+#define RCC_PLL2DIVR_R2_Pos                    (24U)
+#define RCC_PLL2DIVR_R2_Msk                    (0x7FUL << RCC_PLL2DIVR_R2_Pos) /*!< 0x7F000000 */
+#define RCC_PLL2DIVR_R2                        RCC_PLL2DIVR_R2_Msk
+
+/********************  Bit definition for RCC_PLL2FRACR register  ***************/
+#define RCC_PLL2FRACR_FRACN2_Pos               (3U)
+#define RCC_PLL2FRACR_FRACN2_Msk               (0x1FFFUL << RCC_PLL2FRACR_FRACN2_Pos) /*!< 0x0000FFF8 */
+#define RCC_PLL2FRACR_FRACN2                   RCC_PLL2FRACR_FRACN2_Msk
+
+/********************  Bit definition for RCC_PLL3DIVR register  ***************/
+#define RCC_PLL3DIVR_N3_Pos                    (0U)
+#define RCC_PLL3DIVR_N3_Msk                    (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */
+#define RCC_PLL3DIVR_N3                        RCC_PLL3DIVR_N3_Msk
+#define RCC_PLL3DIVR_P3_Pos                    (9U)
+#define RCC_PLL3DIVR_P3_Msk                    (0x7FUL << RCC_PLL3DIVR_P3_Pos) /*!< 0x0000FE00 */
+#define RCC_PLL3DIVR_P3                        RCC_PLL3DIVR_P3_Msk
+#define RCC_PLL3DIVR_Q3_Pos                    (16U)
+#define RCC_PLL3DIVR_Q3_Msk                    (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */
+#define RCC_PLL3DIVR_Q3                        RCC_PLL3DIVR_Q3_Msk
+#define RCC_PLL3DIVR_R3_Pos                    (24U)
+#define RCC_PLL3DIVR_R3_Msk                    (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */
+#define RCC_PLL3DIVR_R3                        RCC_PLL3DIVR_R3_Msk
+
+/********************  Bit definition for RCC_PLL3FRACR register  ***************/
+#define RCC_PLL3FRACR_FRACN3_Pos               (3U)
+#define RCC_PLL3FRACR_FRACN3_Msk               (0x1FFFUL << RCC_PLL3FRACR_FRACN3_Pos) /*!< 0x0000FFF8 */
+#define RCC_PLL3FRACR_FRACN3                   RCC_PLL3FRACR_FRACN3_Msk
+
+/********************  Bit definition for RCC_D1CCIPR register  ***************/
+#define RCC_D1CCIPR_FMCSEL_Pos                 (0U)
+#define RCC_D1CCIPR_FMCSEL_Msk                 (0x3UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000003 */
+#define RCC_D1CCIPR_FMCSEL                     RCC_D1CCIPR_FMCSEL_Msk
+#define RCC_D1CCIPR_FMCSEL_0                   (0x1UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000001 */
+#define RCC_D1CCIPR_FMCSEL_1                   (0x2UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000002 */
+#define RCC_D1CCIPR_QSPISEL_Pos                (4U)
+#define RCC_D1CCIPR_QSPISEL_Msk                (0x3UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000030 */
+#define RCC_D1CCIPR_QSPISEL                    RCC_D1CCIPR_QSPISEL_Msk
+#define RCC_D1CCIPR_QSPISEL_0                  (0x1UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000010 */
+#define RCC_D1CCIPR_QSPISEL_1                  (0x2UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000020 */
+#define RCC_D1CCIPR_SDMMCSEL_Pos               (16U)
+#define RCC_D1CCIPR_SDMMCSEL_Msk               (0x1UL << RCC_D1CCIPR_SDMMCSEL_Pos) /*!< 0x00010000 */
+#define RCC_D1CCIPR_SDMMCSEL                   RCC_D1CCIPR_SDMMCSEL_Msk
+#define RCC_D1CCIPR_CKPERSEL_Pos               (28U)
+#define RCC_D1CCIPR_CKPERSEL_Msk               (0x3UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x30000000 */
+#define RCC_D1CCIPR_CKPERSEL                   RCC_D1CCIPR_CKPERSEL_Msk
+#define RCC_D1CCIPR_CKPERSEL_0                 (0x1UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x10000000 */
+#define RCC_D1CCIPR_CKPERSEL_1                 (0x2UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x20000000 */
+
+/********************  Bit definition for RCC_D2CCIP1R register  ***************/
+#define RCC_D2CCIP1R_SAI1SEL_Pos               (0U)
+#define RCC_D2CCIP1R_SAI1SEL_Msk               (0x7UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000007 */
+#define RCC_D2CCIP1R_SAI1SEL                   RCC_D2CCIP1R_SAI1SEL_Msk
+#define RCC_D2CCIP1R_SAI1SEL_0                 (0x1UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000001 */
+#define RCC_D2CCIP1R_SAI1SEL_1                 (0x2UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000002 */
+#define RCC_D2CCIP1R_SAI1SEL_2                 (0x4UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000004 */
+
+#define RCC_D2CCIP1R_SAI23SEL_Pos              (6U)
+#define RCC_D2CCIP1R_SAI23SEL_Msk              (0x7UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x000001C0 */
+#define RCC_D2CCIP1R_SAI23SEL                  RCC_D2CCIP1R_SAI23SEL_Msk
+#define RCC_D2CCIP1R_SAI23SEL_0                (0x1UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000040 */
+#define RCC_D2CCIP1R_SAI23SEL_1                (0x2UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000080 */
+#define RCC_D2CCIP1R_SAI23SEL_2                (0x4UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000100 */
+
+#define RCC_D2CCIP1R_SPI123SEL_Pos             (12U)
+#define RCC_D2CCIP1R_SPI123SEL_Msk             (0x7UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00007000 */
+#define RCC_D2CCIP1R_SPI123SEL                 RCC_D2CCIP1R_SPI123SEL_Msk
+#define RCC_D2CCIP1R_SPI123SEL_0               (0x1UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00001000 */
+#define RCC_D2CCIP1R_SPI123SEL_1               (0x2UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00002000 */
+#define RCC_D2CCIP1R_SPI123SEL_2               (0x4UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00004000 */
+
+#define RCC_D2CCIP1R_SPI45SEL_Pos              (16U)
+#define RCC_D2CCIP1R_SPI45SEL_Msk              (0x7UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00070000 */
+#define RCC_D2CCIP1R_SPI45SEL                  RCC_D2CCIP1R_SPI45SEL_Msk
+#define RCC_D2CCIP1R_SPI45SEL_0                (0x1UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00010000 */
+#define RCC_D2CCIP1R_SPI45SEL_1                (0x2UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00020000 */
+#define RCC_D2CCIP1R_SPI45SEL_2                (0x4UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00040000 */
+
+#define RCC_D2CCIP1R_SPDIFSEL_Pos              (20U)
+#define RCC_D2CCIP1R_SPDIFSEL_Msk              (0x3UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00300000 */
+#define RCC_D2CCIP1R_SPDIFSEL                  RCC_D2CCIP1R_SPDIFSEL_Msk
+#define RCC_D2CCIP1R_SPDIFSEL_0                (0x1UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00100000 */
+#define RCC_D2CCIP1R_SPDIFSEL_1                (0x2UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00200000 */
+
+#define RCC_D2CCIP1R_DFSDM1SEL_Pos             (24U)
+#define RCC_D2CCIP1R_DFSDM1SEL_Msk             (0x1UL << RCC_D2CCIP1R_DFSDM1SEL_Pos) /*!< 0x01000000 */
+#define RCC_D2CCIP1R_DFSDM1SEL                 RCC_D2CCIP1R_DFSDM1SEL_Msk
+
+#define RCC_D2CCIP1R_FDCANSEL_Pos              (28U)
+#define RCC_D2CCIP1R_FDCANSEL_Msk              (0x3UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x30000000 */
+#define RCC_D2CCIP1R_FDCANSEL                  RCC_D2CCIP1R_FDCANSEL_Msk
+#define RCC_D2CCIP1R_FDCANSEL_0                (0x1UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x10000000 */
+#define RCC_D2CCIP1R_FDCANSEL_1                (0x2UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x20000000 */
+
+#define RCC_D2CCIP1R_SWPSEL_Pos                (31U)
+#define RCC_D2CCIP1R_SWPSEL_Msk                (0x1UL << RCC_D2CCIP1R_SWPSEL_Pos) /*!< 0x80000000 */
+#define RCC_D2CCIP1R_SWPSEL                    RCC_D2CCIP1R_SWPSEL_Msk
+
+/********************  Bit definition for RCC_D2CCIP2R register  ***************/
+#define RCC_D2CCIP2R_USART16SEL_Pos            (3U)
+#define RCC_D2CCIP2R_USART16SEL_Msk            (0x7UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000038 */
+#define RCC_D2CCIP2R_USART16SEL                RCC_D2CCIP2R_USART16SEL_Msk
+#define RCC_D2CCIP2R_USART16SEL_0              (0x1UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000008 */
+#define RCC_D2CCIP2R_USART16SEL_1              (0x2UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000010 */
+#define RCC_D2CCIP2R_USART16SEL_2              (0x4UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000020 */
+
+#define RCC_D2CCIP2R_USART28SEL_Pos            (0U)
+#define RCC_D2CCIP2R_USART28SEL_Msk            (0x7UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000007 */
+#define RCC_D2CCIP2R_USART28SEL                RCC_D2CCIP2R_USART28SEL_Msk
+#define RCC_D2CCIP2R_USART28SEL_0              (0x1UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000001 */
+#define RCC_D2CCIP2R_USART28SEL_1              (0x2UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000002 */
+#define RCC_D2CCIP2R_USART28SEL_2              (0x4UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000004 */
+
+#define RCC_D2CCIP2R_RNGSEL_Pos                (8U)
+#define RCC_D2CCIP2R_RNGSEL_Msk                (0x3UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000300 */
+#define RCC_D2CCIP2R_RNGSEL                    RCC_D2CCIP2R_RNGSEL_Msk
+#define RCC_D2CCIP2R_RNGSEL_0                  (0x1UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000100 */
+#define RCC_D2CCIP2R_RNGSEL_1                  (0x2UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000200 */
+
+#define RCC_D2CCIP2R_I2C123SEL_Pos             (12U)
+#define RCC_D2CCIP2R_I2C123SEL_Msk             (0x3UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00003000 */
+#define RCC_D2CCIP2R_I2C123SEL                 RCC_D2CCIP2R_I2C123SEL_Msk
+#define RCC_D2CCIP2R_I2C123SEL_0               (0x1UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00001000 */
+#define RCC_D2CCIP2R_I2C123SEL_1               (0x2UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00002000 */
+
+#define RCC_D2CCIP2R_USBSEL_Pos                (20U)
+#define RCC_D2CCIP2R_USBSEL_Msk                (0x3UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00300000 */
+#define RCC_D2CCIP2R_USBSEL                    RCC_D2CCIP2R_USBSEL_Msk
+#define RCC_D2CCIP2R_USBSEL_0                  (0x1UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00100000 */
+#define RCC_D2CCIP2R_USBSEL_1                  (0x2UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00200000 */
+
+#define RCC_D2CCIP2R_CECSEL_Pos                (22U)
+#define RCC_D2CCIP2R_CECSEL_Msk                (0x3UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00C00000 */
+#define RCC_D2CCIP2R_CECSEL                    RCC_D2CCIP2R_CECSEL_Msk
+#define RCC_D2CCIP2R_CECSEL_0                  (0x1UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00400000 */
+#define RCC_D2CCIP2R_CECSEL_1                  (0x2UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00800000 */
+
+#define RCC_D2CCIP2R_LPTIM1SEL_Pos             (28U)
+#define RCC_D2CCIP2R_LPTIM1SEL_Msk             (0x7UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x70000000 */
+#define RCC_D2CCIP2R_LPTIM1SEL                 RCC_D2CCIP2R_LPTIM1SEL_Msk
+#define RCC_D2CCIP2R_LPTIM1SEL_0               (0x1UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x10000000 */
+#define RCC_D2CCIP2R_LPTIM1SEL_1               (0x2UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x20000000 */
+#define RCC_D2CCIP2R_LPTIM1SEL_2               (0x4UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for RCC_D3CCIPR register  ***************/
+#define RCC_D3CCIPR_LPUART1SEL_Pos             (0U)
+#define RCC_D3CCIPR_LPUART1SEL_Msk             (0x7UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000007 */
+#define RCC_D3CCIPR_LPUART1SEL                 RCC_D3CCIPR_LPUART1SEL_Msk
+#define RCC_D3CCIPR_LPUART1SEL_0               (0x1UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000001 */
+#define RCC_D3CCIPR_LPUART1SEL_1               (0x2UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000002 */
+#define RCC_D3CCIPR_LPUART1SEL_2               (0x4UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000004 */
+
+#define RCC_D3CCIPR_I2C4SEL_Pos                (8U)
+#define RCC_D3CCIPR_I2C4SEL_Msk                (0x3UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000300 */
+#define RCC_D3CCIPR_I2C4SEL                    RCC_D3CCIPR_I2C4SEL_Msk
+#define RCC_D3CCIPR_I2C4SEL_0                  (0x1UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000100 */
+#define RCC_D3CCIPR_I2C4SEL_1                  (0x2UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000200 */
+
+#define RCC_D3CCIPR_LPTIM2SEL_Pos              (10U)
+#define RCC_D3CCIPR_LPTIM2SEL_Msk              (0x7UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001C00 */
+#define RCC_D3CCIPR_LPTIM2SEL                  RCC_D3CCIPR_LPTIM2SEL_Msk
+#define RCC_D3CCIPR_LPTIM2SEL_0                (0x1UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000400 */
+#define RCC_D3CCIPR_LPTIM2SEL_1                (0x2UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000800 */
+#define RCC_D3CCIPR_LPTIM2SEL_2                (0x4UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001000 */
+
+#define RCC_D3CCIPR_LPTIM345SEL_Pos            (13U)
+#define RCC_D3CCIPR_LPTIM345SEL_Msk            (0x7UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x0000E000 */
+#define RCC_D3CCIPR_LPTIM345SEL                RCC_D3CCIPR_LPTIM345SEL_Msk
+#define RCC_D3CCIPR_LPTIM345SEL_0              (0x1UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00002000 */
+#define RCC_D3CCIPR_LPTIM345SEL_1              (0x2UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00004000 */
+#define RCC_D3CCIPR_LPTIM345SEL_2              (0x4UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00008000 */
+
+#define RCC_D3CCIPR_SAI4ASEL_Pos               (21U)
+#define RCC_D3CCIPR_SAI4ASEL_Msk               (0x7UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00E00000 */
+#define RCC_D3CCIPR_SAI4ASEL                   RCC_D3CCIPR_SAI4ASEL_Msk
+#define RCC_D3CCIPR_SAI4ASEL_0                 (0x1UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00200000 */
+#define RCC_D3CCIPR_SAI4ASEL_1                 (0x2UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00400000 */
+#define RCC_D3CCIPR_SAI4ASEL_2                 (0x4UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00800000 */
+
+#define RCC_D3CCIPR_SAI4BSEL_Pos               (24U)
+#define RCC_D3CCIPR_SAI4BSEL_Msk               (0x7UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x07000000 */
+#define RCC_D3CCIPR_SAI4BSEL                   RCC_D3CCIPR_SAI4BSEL_Msk
+#define RCC_D3CCIPR_SAI4BSEL_0                 (0x1UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x01000000 */
+#define RCC_D3CCIPR_SAI4BSEL_1                 (0x2UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x02000000 */
+#define RCC_D3CCIPR_SAI4BSEL_2                 (0x4UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x04000000 */
+
+#define RCC_D3CCIPR_ADCSEL_Pos                 (16U)
+#define RCC_D3CCIPR_ADCSEL_Msk                 (0x3UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00030000 */
+#define RCC_D3CCIPR_ADCSEL                     RCC_D3CCIPR_ADCSEL_Msk
+#define RCC_D3CCIPR_ADCSEL_0                   (0x1UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00010000 */
+#define RCC_D3CCIPR_ADCSEL_1                   (0x2UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00020000 */
+
+#define RCC_D3CCIPR_SPI6SEL_Pos                (28U)
+#define RCC_D3CCIPR_SPI6SEL_Msk                (0x7UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x70000000 */
+#define RCC_D3CCIPR_SPI6SEL                    RCC_D3CCIPR_SPI6SEL_Msk
+#define RCC_D3CCIPR_SPI6SEL_0                  (0x1UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x10000000 */
+#define RCC_D3CCIPR_SPI6SEL_1                  (0x2UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x20000000 */
+#define RCC_D3CCIPR_SPI6SEL_2                  (0x4UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x40000000 */
+/********************  Bit definition for RCC_CIER register  ******************/
+#define RCC_CIER_LSIRDYIE_Pos                  (0U)
+#define RCC_CIER_LSIRDYIE_Msk                  (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
+#define RCC_CIER_LSIRDYIE                      RCC_CIER_LSIRDYIE_Msk
+#define RCC_CIER_LSERDYIE_Pos                  (1U)
+#define RCC_CIER_LSERDYIE_Msk                  (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
+#define RCC_CIER_LSERDYIE                      RCC_CIER_LSERDYIE_Msk
+#define RCC_CIER_HSIRDYIE_Pos                  (2U)
+#define RCC_CIER_HSIRDYIE_Msk                  (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
+#define RCC_CIER_HSIRDYIE                      RCC_CIER_HSIRDYIE_Msk
+#define RCC_CIER_HSERDYIE_Pos                  (3U)
+#define RCC_CIER_HSERDYIE_Msk                  (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
+#define RCC_CIER_HSERDYIE                      RCC_CIER_HSERDYIE_Msk
+#define RCC_CIER_CSIRDYIE_Pos                  (4U)
+#define RCC_CIER_CSIRDYIE_Msk                  (0x1UL << RCC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */
+#define RCC_CIER_CSIRDYIE                      RCC_CIER_CSIRDYIE_Msk
+#define RCC_CIER_HSI48RDYIE_Pos                (5U)
+#define RCC_CIER_HSI48RDYIE_Msk                (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000020 */
+#define RCC_CIER_HSI48RDYIE                    RCC_CIER_HSI48RDYIE_Msk
+#define RCC_CIER_PLL1RDYIE_Pos                 (6U)
+#define RCC_CIER_PLL1RDYIE_Msk                 (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000040 */
+#define RCC_CIER_PLL1RDYIE                     RCC_CIER_PLL1RDYIE_Msk
+#define RCC_CIER_PLL2RDYIE_Pos                 (7U)
+#define RCC_CIER_PLL2RDYIE_Msk                 (0x1UL << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000080 */
+#define RCC_CIER_PLL2RDYIE                     RCC_CIER_PLL2RDYIE_Msk
+#define RCC_CIER_PLL3RDYIE_Pos                 (8U)
+#define RCC_CIER_PLL3RDYIE_Msk                 (0x1UL << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000100 */
+#define RCC_CIER_PLL3RDYIE                     RCC_CIER_PLL3RDYIE_Msk
+#define RCC_CIER_LSECSSIE_Pos                  (9U)
+#define RCC_CIER_LSECSSIE_Msk                  (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */
+#define RCC_CIER_LSECSSIE                      RCC_CIER_LSECSSIE_Msk
+
+/********************  Bit definition for RCC_CIFR register  ******************/
+#define RCC_CIFR_LSIRDYF_Pos                   (0U)
+#define RCC_CIFR_LSIRDYF_Msk                   (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIFR_LSIRDYF                       RCC_CIFR_LSIRDYF_Msk
+#define RCC_CIFR_LSERDYF_Pos                   (1U)
+#define RCC_CIFR_LSERDYF_Msk                   (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIFR_LSERDYF                       RCC_CIFR_LSERDYF_Msk
+#define RCC_CIFR_HSIRDYF_Pos                   (2U)
+#define RCC_CIFR_HSIRDYF_Msk                   (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIFR_HSIRDYF                       RCC_CIFR_HSIRDYF_Msk
+#define RCC_CIFR_HSERDYF_Pos                   (3U)
+#define RCC_CIFR_HSERDYF_Msk                   (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIFR_HSERDYF                       RCC_CIFR_HSERDYF_Msk
+#define RCC_CIFR_CSIRDYF_Pos                   (4U)
+#define RCC_CIFR_CSIRDYF_Msk                   (0x1UL << RCC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIFR_CSIRDYF                       RCC_CIFR_CSIRDYF_Msk
+#define RCC_CIFR_HSI48RDYF_Pos                 (5U)
+#define RCC_CIFR_HSI48RDYF_Msk                 (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000020 */
+#define RCC_CIFR_HSI48RDYF                     RCC_CIFR_HSI48RDYF_Msk
+#define RCC_CIFR_PLLRDYF_Pos                   (6U)
+#define RCC_CIFR_PLLRDYF_Msk                   (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000040 */
+#define RCC_CIFR_PLLRDYF                       RCC_CIFR_PLLRDYF_Msk
+#define RCC_CIFR_PLL2RDYF_Pos                  (7U)
+#define RCC_CIFR_PLL2RDYF_Msk                  (0x1UL << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000080 */
+#define RCC_CIFR_PLL2RDYF                      RCC_CIFR_PLL2RDYF_Msk
+#define RCC_CIFR_PLL3RDYF_Pos                  (8U)
+#define RCC_CIFR_PLL3RDYF_Msk                  (0x1UL << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000100 */
+#define RCC_CIFR_PLL3RDYF                      RCC_CIFR_PLL3RDYF_Msk
+#define RCC_CIFR_LSECSSF_Pos                   (9U)
+#define RCC_CIFR_LSECSSF_Msk                   (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */
+#define RCC_CIFR_LSECSSF                       RCC_CIFR_LSECSSF_Msk
+#define RCC_CIFR_HSECSSF_Pos                   (10U)
+#define RCC_CIFR_HSECSSF_Msk                   (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */
+#define RCC_CIFR_HSECSSF                       RCC_CIFR_HSECSSF_Msk
+
+/********************  Bit definition for RCC_CICR register  ******************/
+#define RCC_CICR_LSIRDYC_Pos                   (0U)
+#define RCC_CICR_LSIRDYC_Msk                   (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
+#define RCC_CICR_LSIRDYC                       RCC_CICR_LSIRDYC_Msk
+#define RCC_CICR_LSERDYC_Pos                   (1U)
+#define RCC_CICR_LSERDYC_Msk                   (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
+#define RCC_CICR_LSERDYC                       RCC_CICR_LSERDYC_Msk
+#define RCC_CICR_HSIRDYC_Pos                   (2U)
+#define RCC_CICR_HSIRDYC_Msk                   (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */
+#define RCC_CICR_HSIRDYC                       RCC_CICR_HSIRDYC_Msk
+#define RCC_CICR_HSERDYC_Pos                   (3U)
+#define RCC_CICR_HSERDYC_Msk                   (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */
+#define RCC_CICR_HSERDYC                       RCC_CICR_HSERDYC_Msk
+#define RCC_CICR_CSIRDYC_Pos                   (4U)
+#define RCC_CICR_CSIRDYC_Msk                   (0x1UL << RCC_CICR_CSIRDYC_Pos) /*!< 0x00000010 */
+#define RCC_CICR_CSIRDYC                       RCC_CICR_CSIRDYC_Msk
+#define RCC_CICR_HSI48RDYC_Pos                 (5U)
+#define RCC_CICR_HSI48RDYC_Msk                 (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000020 */
+#define RCC_CICR_HSI48RDYC                     RCC_CICR_HSI48RDYC_Msk
+#define RCC_CICR_PLLRDYC_Pos                   (6U)
+#define RCC_CICR_PLLRDYC_Msk                   (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000040 */
+#define RCC_CICR_PLLRDYC                       RCC_CICR_PLLRDYC_Msk
+#define RCC_CICR_PLL2RDYC_Pos                  (7U)
+#define RCC_CICR_PLL2RDYC_Msk                  (0x1UL << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000080 */
+#define RCC_CICR_PLL2RDYC                      RCC_CICR_PLL2RDYC_Msk
+#define RCC_CICR_PLL3RDYC_Pos                  (8U)
+#define RCC_CICR_PLL3RDYC_Msk                  (0x1UL << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000100 */
+#define RCC_CICR_PLL3RDYC                      RCC_CICR_PLL3RDYC_Msk
+#define RCC_CICR_LSECSSC_Pos                   (9U)
+#define RCC_CICR_LSECSSC_Msk                   (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */
+#define RCC_CICR_LSECSSC                       RCC_CICR_LSECSSC_Msk
+#define RCC_CICR_HSECSSC_Pos                   (10U)
+#define RCC_CICR_HSECSSC_Msk                   (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */
+#define RCC_CICR_HSECSSC                       RCC_CICR_HSECSSC_Msk
+
+/********************  Bit definition for RCC_BDCR register  ******************/
+#define RCC_BDCR_LSEON_Pos                     (0U)
+#define RCC_BDCR_LSEON_Msk                     (0x1UL << RCC_BDCR_LSEON_Pos)   /*!< 0x00000001 */
+#define RCC_BDCR_LSEON                         RCC_BDCR_LSEON_Msk
+#define RCC_BDCR_LSERDY_Pos                    (1U)
+#define RCC_BDCR_LSERDY_Msk                    (0x1UL << RCC_BDCR_LSERDY_Pos)  /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY                        RCC_BDCR_LSERDY_Msk
+#define RCC_BDCR_LSEBYP_Pos                    (2U)
+#define RCC_BDCR_LSEBYP_Msk                    (0x1UL << RCC_BDCR_LSEBYP_Pos)  /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP                        RCC_BDCR_LSEBYP_Msk
+
+#define RCC_BDCR_LSEDRV_Pos                    (3U)
+#define RCC_BDCR_LSEDRV_Msk                    (0x3UL << RCC_BDCR_LSEDRV_Pos)  /*!< 0x00000018 */
+#define RCC_BDCR_LSEDRV                        RCC_BDCR_LSEDRV_Msk
+#define RCC_BDCR_LSEDRV_0                      (0x1UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000008 */
+#define RCC_BDCR_LSEDRV_1                      (0x2UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000010 */
+
+#define RCC_BDCR_LSECSSON_Pos                  (5U)
+#define RCC_BDCR_LSECSSON_Msk                  (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */
+#define RCC_BDCR_LSECSSON                      RCC_BDCR_LSECSSON_Msk
+#define RCC_BDCR_LSECSSD_Pos                   (6U)
+#define RCC_BDCR_LSECSSD_Msk                   (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */
+#define RCC_BDCR_LSECSSD                       RCC_BDCR_LSECSSD_Msk
+
+#define RCC_BDCR_RTCSEL_Pos                    (8U)
+#define RCC_BDCR_RTCSEL_Msk                    (0x3UL << RCC_BDCR_RTCSEL_Pos)  /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL                        RCC_BDCR_RTCSEL_Msk
+#define RCC_BDCR_RTCSEL_0                      (0x1UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1                      (0x2UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000200 */
+
+#define RCC_BDCR_RTCEN_Pos                     (15U)
+#define RCC_BDCR_RTCEN_Msk                     (0x1UL << RCC_BDCR_RTCEN_Pos)   /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN                         RCC_BDCR_RTCEN_Msk
+#define RCC_BDCR_BDRST_Pos                     (16U)
+#define RCC_BDCR_BDRST_Msk                     (0x1UL << RCC_BDCR_BDRST_Pos)   /*!< 0x00010000 */
+#define RCC_BDCR_BDRST                         RCC_BDCR_BDRST_Msk
+/********************  Bit definition for RCC_CSR register  *******************/
+#define RCC_CSR_LSION_Pos                      (0U)
+#define RCC_CSR_LSION_Msk                      (0x1UL << RCC_CSR_LSION_Pos)    /*!< 0x00000001 */
+#define RCC_CSR_LSION                          RCC_CSR_LSION_Msk
+#define RCC_CSR_LSIRDY_Pos                     (1U)
+#define RCC_CSR_LSIRDY_Msk                     (0x1UL << RCC_CSR_LSIRDY_Pos)   /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY                         RCC_CSR_LSIRDY_Msk
+
+
+/********************  Bit definition for RCC_AHB3ENR register  **************/
+#define RCC_AHB3ENR_MDMAEN_Pos                 (0U)
+#define RCC_AHB3ENR_MDMAEN_Msk                 (0x1UL << RCC_AHB3ENR_MDMAEN_Pos)       /*!< 0x00000001 */
+#define RCC_AHB3ENR_MDMAEN                     RCC_AHB3ENR_MDMAEN_Msk
+#define RCC_AHB3ENR_DMA2DEN_Pos                (4U)
+#define RCC_AHB3ENR_DMA2DEN_Msk                (0x1UL << RCC_AHB3ENR_DMA2DEN_Pos)      /*!< 0x00000010 */
+#define RCC_AHB3ENR_DMA2DEN                    RCC_AHB3ENR_DMA2DEN_Msk
+#define RCC_AHB3ENR_JPGDECEN_Pos               (5U)
+#define RCC_AHB3ENR_JPGDECEN_Msk               (0x1UL << RCC_AHB3ENR_JPGDECEN_Pos)     /*!< 0x00000020 */
+#define RCC_AHB3ENR_JPGDECEN                   RCC_AHB3ENR_JPGDECEN_Msk
+#define RCC_AHB3ENR_FMCEN_Pos                  (12U)
+#define RCC_AHB3ENR_FMCEN_Msk                  (0x1UL << RCC_AHB3ENR_FMCEN_Pos)        /*!< 0x00001000 */
+#define RCC_AHB3ENR_FMCEN                      RCC_AHB3ENR_FMCEN_Msk
+#define RCC_AHB3ENR_QSPIEN_Pos                 (14U)
+#define RCC_AHB3ENR_QSPIEN_Msk                 (0x1UL << RCC_AHB3ENR_QSPIEN_Pos)       /*!< 0x00004000 */
+#define RCC_AHB3ENR_QSPIEN                     RCC_AHB3ENR_QSPIEN_Msk
+#define RCC_AHB3ENR_SDMMC1EN_Pos               (16U)
+#define RCC_AHB3ENR_SDMMC1EN_Msk               (0x1UL << RCC_AHB3ENR_SDMMC1EN_Pos)     /*!< 0x00010000 */
+#define RCC_AHB3ENR_SDMMC1EN                   RCC_AHB3ENR_SDMMC1EN_Msk
+
+/********************  Bit definition for RCC_AHB1ENR register  ***************/
+#define RCC_AHB1ENR_DMA1EN_Pos                 (0U)
+#define RCC_AHB1ENR_DMA1EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)          /*!< 0x00000001 */
+#define RCC_AHB1ENR_DMA1EN                     RCC_AHB1ENR_DMA1EN_Msk
+#define RCC_AHB1ENR_DMA2EN_Pos                 (1U)
+#define RCC_AHB1ENR_DMA2EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)          /*!< 0x00000002 */
+#define RCC_AHB1ENR_DMA2EN                     RCC_AHB1ENR_DMA2EN_Msk
+#define RCC_AHB1ENR_ADC12EN_Pos                (5U)
+#define RCC_AHB1ENR_ADC12EN_Msk                (0x1UL << RCC_AHB1ENR_ADC12EN_Pos)         /*!< 0x00000020 */
+#define RCC_AHB1ENR_ADC12EN                    RCC_AHB1ENR_ADC12EN_Msk
+#define RCC_AHB1ENR_ETH1MACEN_Pos              (15U)
+#define RCC_AHB1ENR_ETH1MACEN_Msk              (0x1UL << RCC_AHB1ENR_ETH1MACEN_Pos)       /*!< 0x00008000 */
+#define RCC_AHB1ENR_ETH1MACEN                  RCC_AHB1ENR_ETH1MACEN_Msk
+#define RCC_AHB1ENR_ETH1TXEN_Pos               (16U)
+#define RCC_AHB1ENR_ETH1TXEN_Msk               (0x1UL << RCC_AHB1ENR_ETH1TXEN_Pos)        /*!< 0x00010000 */
+#define RCC_AHB1ENR_ETH1TXEN                   RCC_AHB1ENR_ETH1TXEN_Msk
+#define RCC_AHB1ENR_ETH1RXEN_Pos               (17U)
+#define RCC_AHB1ENR_ETH1RXEN_Msk               (0x1UL << RCC_AHB1ENR_ETH1RXEN_Pos)        /*!< 0x00020000 */
+#define RCC_AHB1ENR_ETH1RXEN                   RCC_AHB1ENR_ETH1RXEN_Msk
+#define RCC_AHB1ENR_USB1OTGHSEN_Pos            (25U)
+#define RCC_AHB1ENR_USB1OTGHSEN_Msk            (0x1UL << RCC_AHB1ENR_USB1OTGHSEN_Pos)     /*!< 0x02000000 */
+#define RCC_AHB1ENR_USB1OTGHSEN                RCC_AHB1ENR_USB1OTGHSEN_Msk
+#define RCC_AHB1ENR_USB1OTGHSULPIEN_Pos        (26U)
+#define RCC_AHB1ENR_USB1OTGHSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_USB1OTGHSULPIEN_Pos) /*!< 0x04000000 */
+#define RCC_AHB1ENR_USB1OTGHSULPIEN            RCC_AHB1ENR_USB1OTGHSULPIEN_Msk
+#define RCC_AHB1ENR_USB2OTGFSEN_Pos            (27U)
+#define RCC_AHB1ENR_USB2OTGFSEN_Msk            (0x1UL << RCC_AHB1ENR_USB2OTGFSEN_Pos)     /*!< 0x08000000 */
+#define RCC_AHB1ENR_USB2OTGFSEN                RCC_AHB1ENR_USB2OTGFSEN_Msk
+#define RCC_AHB1ENR_USB2OTGFSULPIEN_Pos        (28U)
+#define RCC_AHB1ENR_USB2OTGFSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_USB2OTGFSULPIEN_Pos) /*!< 0x10000000 */
+#define RCC_AHB1ENR_USB2OTGFSULPIEN            RCC_AHB1ENR_USB2OTGFSULPIEN_Msk
+
+/* Legacy define */
+#define RCC_AHB1ENR_USB2OTGHSEN_Pos            RCC_AHB1ENR_USB2OTGFSEN_Pos
+#define RCC_AHB1ENR_USB2OTGHSEN_Msk            RCC_AHB1ENR_USB2OTGFSEN_Msk
+#define RCC_AHB1ENR_USB2OTGHSEN                RCC_AHB1ENR_USB2OTGFSEN
+#define RCC_AHB1ENR_USB2OTGHSULPIEN_Pos        RCC_AHB1ENR_USB2OTGFSULPIEN_Pos
+#define RCC_AHB1ENR_USB2OTGHSULPIEN_Msk        RCC_AHB1ENR_USB2OTGFSULPIEN_Msk
+#define RCC_AHB1ENR_USB2OTGHSULPIEN            RCC_AHB1ENR_USB2OTGFSULPIEN
+
+
+/********************  Bit definition for RCC_AHB2ENR register  ***************/
+#define RCC_AHB2ENR_DCMIEN_Pos                 (0U)
+#define RCC_AHB2ENR_DCMIEN_Msk                 (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)          /*!< 0x00000001 */
+#define RCC_AHB2ENR_DCMIEN                     RCC_AHB2ENR_DCMIEN_Msk
+#define RCC_AHB2ENR_RNGEN_Pos                  (6U)
+#define RCC_AHB2ENR_RNGEN_Msk                  (0x1UL << RCC_AHB2ENR_RNGEN_Pos)           /*!< 0x00000040 */
+#define RCC_AHB2ENR_RNGEN                      RCC_AHB2ENR_RNGEN_Msk
+#define RCC_AHB2ENR_SDMMC2EN_Pos               (9U)
+#define RCC_AHB2ENR_SDMMC2EN_Msk               (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos)        /*!< 0x00000200 */
+#define RCC_AHB2ENR_SDMMC2EN                   RCC_AHB2ENR_SDMMC2EN_Msk
+#define RCC_AHB2ENR_SRAM1EN_Pos                (29U)
+#define RCC_AHB2ENR_SRAM1EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM1EN_Pos)       /*!< 0x20000000 */
+#define RCC_AHB2ENR_SRAM1EN                    RCC_AHB2ENR_SRAM1EN_Msk
+#define RCC_AHB2ENR_SRAM2EN_Pos                (30U)
+#define RCC_AHB2ENR_SRAM2EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos)       /*!< 0x40000000 */
+#define RCC_AHB2ENR_SRAM2EN                    RCC_AHB2ENR_SRAM2EN_Msk
+#define RCC_AHB2ENR_SRAM3EN_Pos                (31U)
+#define RCC_AHB2ENR_SRAM3EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM3EN_Pos)       /*!< 0x80000000 */
+#define RCC_AHB2ENR_SRAM3EN                    RCC_AHB2ENR_SRAM3EN_Msk
+
+/* Legacy define */
+#define RCC_AHB2ENR_D2SRAM1EN_Pos              RCC_AHB2ENR_SRAM1EN_Pos
+#define RCC_AHB2ENR_D2SRAM1EN_Msk              RCC_AHB2ENR_SRAM1EN_Msk
+#define RCC_AHB2ENR_D2SRAM1EN                  RCC_AHB2ENR_SRAM1EN
+#define RCC_AHB2ENR_D2SRAM2EN_Pos              RCC_AHB2ENR_SRAM2EN_Pos
+#define RCC_AHB2ENR_D2SRAM2EN_Msk              RCC_AHB2ENR_SRAM2EN_Msk
+#define RCC_AHB2ENR_D2SRAM2EN                  RCC_AHB2ENR_SRAM2EN
+#define RCC_AHB2ENR_D2SRAM3EN_Pos              RCC_AHB2ENR_SRAM3EN_Pos
+#define RCC_AHB2ENR_D2SRAM3EN_Msk              RCC_AHB2ENR_SRAM3EN_Msk
+#define RCC_AHB2ENR_D2SRAM3EN                  RCC_AHB2ENR_SRAM3EN
+
+/********************  Bit definition for RCC_AHB4ENR register  ******************/
+#define RCC_AHB4ENR_GPIOAEN_Pos                (0U)
+#define RCC_AHB4ENR_GPIOAEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos)         /*!< 0x00000001 */
+#define RCC_AHB4ENR_GPIOAEN                    RCC_AHB4ENR_GPIOAEN_Msk
+#define RCC_AHB4ENR_GPIOBEN_Pos                (1U)
+#define RCC_AHB4ENR_GPIOBEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos)         /*!< 0x00000002 */
+#define RCC_AHB4ENR_GPIOBEN                    RCC_AHB4ENR_GPIOBEN_Msk
+#define RCC_AHB4ENR_GPIOCEN_Pos                (2U)
+#define RCC_AHB4ENR_GPIOCEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos)         /*!< 0x00000004 */
+#define RCC_AHB4ENR_GPIOCEN                    RCC_AHB4ENR_GPIOCEN_Msk
+#define RCC_AHB4ENR_GPIODEN_Pos                (3U)
+#define RCC_AHB4ENR_GPIODEN_Msk                (0x1UL << RCC_AHB4ENR_GPIODEN_Pos)         /*!< 0x00000008 */
+#define RCC_AHB4ENR_GPIODEN                    RCC_AHB4ENR_GPIODEN_Msk
+#define RCC_AHB4ENR_GPIOEEN_Pos                (4U)
+#define RCC_AHB4ENR_GPIOEEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos)         /*!< 0x00000010 */
+#define RCC_AHB4ENR_GPIOEEN                    RCC_AHB4ENR_GPIOEEN_Msk
+#define RCC_AHB4ENR_GPIOFEN_Pos                (5U)
+#define RCC_AHB4ENR_GPIOFEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos)         /*!< 0x00000020 */
+#define RCC_AHB4ENR_GPIOFEN                    RCC_AHB4ENR_GPIOFEN_Msk
+#define RCC_AHB4ENR_GPIOGEN_Pos                (6U)
+#define RCC_AHB4ENR_GPIOGEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos)         /*!< 0x00000040 */
+#define RCC_AHB4ENR_GPIOGEN                    RCC_AHB4ENR_GPIOGEN_Msk
+#define RCC_AHB4ENR_GPIOHEN_Pos                (7U)
+#define RCC_AHB4ENR_GPIOHEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos)         /*!< 0x00000080 */
+#define RCC_AHB4ENR_GPIOHEN                    RCC_AHB4ENR_GPIOHEN_Msk
+#define RCC_AHB4ENR_GPIOIEN_Pos                (8U)
+#define RCC_AHB4ENR_GPIOIEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOIEN_Pos)         /*!< 0x00000100 */
+#define RCC_AHB4ENR_GPIOIEN                    RCC_AHB4ENR_GPIOIEN_Msk
+#define RCC_AHB4ENR_GPIOJEN_Pos                (9U)
+#define RCC_AHB4ENR_GPIOJEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOJEN_Pos)         /*!< 0x00000200 */
+#define RCC_AHB4ENR_GPIOJEN                    RCC_AHB4ENR_GPIOJEN_Msk
+#define RCC_AHB4ENR_GPIOKEN_Pos                (10U)
+#define RCC_AHB4ENR_GPIOKEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOKEN_Pos)         /*!< 0x00000400 */
+#define RCC_AHB4ENR_GPIOKEN                    RCC_AHB4ENR_GPIOKEN_Msk
+#define RCC_AHB4ENR_CRCEN_Pos                  (19U)
+#define RCC_AHB4ENR_CRCEN_Msk                  (0x1UL << RCC_AHB4ENR_CRCEN_Pos)           /*!< 0x00080000 */
+#define RCC_AHB4ENR_CRCEN                      RCC_AHB4ENR_CRCEN_Msk
+#define RCC_AHB4ENR_BDMAEN_Pos                 (21U)
+#define RCC_AHB4ENR_BDMAEN_Msk                 (0x1UL << RCC_AHB4ENR_BDMAEN_Pos)          /*!< 0x00200000 */
+#define RCC_AHB4ENR_BDMAEN                     RCC_AHB4ENR_BDMAEN_Msk
+#define RCC_AHB4ENR_ADC3EN_Pos                 (24U)
+#define RCC_AHB4ENR_ADC3EN_Msk                 (0x1UL << RCC_AHB4ENR_ADC3EN_Pos)          /*!< 0x01000000 */
+#define RCC_AHB4ENR_ADC3EN                     RCC_AHB4ENR_ADC3EN_Msk
+#define RCC_AHB4ENR_HSEMEN_Pos                 (25U)
+#define RCC_AHB4ENR_HSEMEN_Msk                 (0x1UL << RCC_AHB4ENR_HSEMEN_Pos)          /*!< 0x02000000 */
+#define RCC_AHB4ENR_HSEMEN                     RCC_AHB4ENR_HSEMEN_Msk
+#define RCC_AHB4ENR_BKPRAMEN_Pos               (28U)
+#define RCC_AHB4ENR_BKPRAMEN_Msk               (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos)        /*!< 0x10000000 */
+#define RCC_AHB4ENR_BKPRAMEN                   RCC_AHB4ENR_BKPRAMEN_Msk
+
+/********************  Bit definition for RCC_APB3ENR register  ******************/
+#define RCC_APB3ENR_LTDCEN_Pos                 (3U)
+#define RCC_APB3ENR_LTDCEN_Msk                 (0x1UL << RCC_APB3ENR_LTDCEN_Pos) /*!< 0x00000008 */
+#define RCC_APB3ENR_LTDCEN                     RCC_APB3ENR_LTDCEN_Msk
+#define RCC_APB3ENR_WWDG1EN_Pos                (6U)
+#define RCC_APB3ENR_WWDG1EN_Msk                (0x1UL << RCC_APB3ENR_WWDG1EN_Pos) /*!< 0x00000040 */
+#define RCC_APB3ENR_WWDG1EN                    RCC_APB3ENR_WWDG1EN_Msk
+
+/********************  Bit definition for RCC_APB1LENR register  ******************/
+
+#define RCC_APB1LENR_TIM2EN_Pos                (0U)
+#define RCC_APB1LENR_TIM2EN_Msk                (0x1UL << RCC_APB1LENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1LENR_TIM2EN                    RCC_APB1LENR_TIM2EN_Msk
+#define RCC_APB1LENR_TIM3EN_Pos                (1U)
+#define RCC_APB1LENR_TIM3EN_Msk                (0x1UL << RCC_APB1LENR_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1LENR_TIM3EN                    RCC_APB1LENR_TIM3EN_Msk
+#define RCC_APB1LENR_TIM4EN_Pos                (2U)
+#define RCC_APB1LENR_TIM4EN_Msk                (0x1UL << RCC_APB1LENR_TIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1LENR_TIM4EN                    RCC_APB1LENR_TIM4EN_Msk
+#define RCC_APB1LENR_TIM5EN_Pos                (3U)
+#define RCC_APB1LENR_TIM5EN_Msk                (0x1UL << RCC_APB1LENR_TIM5EN_Pos) /*!< 0x00000008 */
+#define RCC_APB1LENR_TIM5EN                    RCC_APB1LENR_TIM5EN_Msk
+#define RCC_APB1LENR_TIM6EN_Pos                (4U)
+#define RCC_APB1LENR_TIM6EN_Msk                (0x1UL << RCC_APB1LENR_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_APB1LENR_TIM6EN                    RCC_APB1LENR_TIM6EN_Msk
+#define RCC_APB1LENR_TIM7EN_Pos                (5U)
+#define RCC_APB1LENR_TIM7EN_Msk                (0x1UL << RCC_APB1LENR_TIM7EN_Pos) /*!< 0x00000020 */
+#define RCC_APB1LENR_TIM7EN                    RCC_APB1LENR_TIM7EN_Msk
+#define RCC_APB1LENR_TIM12EN_Pos               (6U)
+#define RCC_APB1LENR_TIM12EN_Msk               (0x1UL << RCC_APB1LENR_TIM12EN_Pos) /*!< 0x00000040 */
+#define RCC_APB1LENR_TIM12EN                   RCC_APB1LENR_TIM12EN_Msk
+#define RCC_APB1LENR_TIM13EN_Pos               (7U)
+#define RCC_APB1LENR_TIM13EN_Msk               (0x1UL << RCC_APB1LENR_TIM13EN_Pos) /*!< 0x00000080 */
+#define RCC_APB1LENR_TIM13EN                   RCC_APB1LENR_TIM13EN_Msk
+#define RCC_APB1LENR_TIM14EN_Pos               (8U)
+#define RCC_APB1LENR_TIM14EN_Msk               (0x1UL << RCC_APB1LENR_TIM14EN_Pos) /*!< 0x00000100 */
+#define RCC_APB1LENR_TIM14EN                   RCC_APB1LENR_TIM14EN_Msk
+#define RCC_APB1LENR_LPTIM1EN_Pos              (9U)
+#define RCC_APB1LENR_LPTIM1EN_Msk              (0x1UL << RCC_APB1LENR_LPTIM1EN_Pos) /*!< 0x00000200 */
+#define RCC_APB1LENR_LPTIM1EN                  RCC_APB1LENR_LPTIM1EN_Msk
+
+
+#define RCC_APB1LENR_SPI2EN_Pos                (14U)
+#define RCC_APB1LENR_SPI2EN_Msk                (0x1UL << RCC_APB1LENR_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1LENR_SPI2EN                    RCC_APB1LENR_SPI2EN_Msk
+#define RCC_APB1LENR_SPI3EN_Pos                (15U)
+#define RCC_APB1LENR_SPI3EN_Msk                (0x1UL << RCC_APB1LENR_SPI3EN_Pos) /*!< 0x00008000 */
+#define RCC_APB1LENR_SPI3EN                    RCC_APB1LENR_SPI3EN_Msk
+#define RCC_APB1LENR_SPDIFRXEN_Pos             (16U)
+#define RCC_APB1LENR_SPDIFRXEN_Msk             (0x1UL << RCC_APB1LENR_SPDIFRXEN_Pos) /*!< 0x00010000 */
+#define RCC_APB1LENR_SPDIFRXEN                 RCC_APB1LENR_SPDIFRXEN_Msk
+#define RCC_APB1LENR_USART2EN_Pos              (17U)
+#define RCC_APB1LENR_USART2EN_Msk              (0x1UL << RCC_APB1LENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1LENR_USART2EN                  RCC_APB1LENR_USART2EN_Msk
+#define RCC_APB1LENR_USART3EN_Pos              (18U)
+#define RCC_APB1LENR_USART3EN_Msk              (0x1UL << RCC_APB1LENR_USART3EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1LENR_USART3EN                  RCC_APB1LENR_USART3EN_Msk
+#define RCC_APB1LENR_UART4EN_Pos               (19U)
+#define RCC_APB1LENR_UART4EN_Msk               (0x1UL << RCC_APB1LENR_UART4EN_Pos) /*!< 0x00080000 */
+#define RCC_APB1LENR_UART4EN                   RCC_APB1LENR_UART4EN_Msk
+#define RCC_APB1LENR_UART5EN_Pos               (20U)
+#define RCC_APB1LENR_UART5EN_Msk               (0x1UL << RCC_APB1LENR_UART5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB1LENR_UART5EN                   RCC_APB1LENR_UART5EN_Msk
+#define RCC_APB1LENR_I2C1EN_Pos                (21U)
+#define RCC_APB1LENR_I2C1EN_Msk                (0x1UL << RCC_APB1LENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1LENR_I2C1EN                    RCC_APB1LENR_I2C1EN_Msk
+#define RCC_APB1LENR_I2C2EN_Pos                (22U)
+#define RCC_APB1LENR_I2C2EN_Msk                (0x1UL << RCC_APB1LENR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1LENR_I2C2EN                    RCC_APB1LENR_I2C2EN_Msk
+#define RCC_APB1LENR_I2C3EN_Pos                (23U)
+#define RCC_APB1LENR_I2C3EN_Msk                (0x1UL << RCC_APB1LENR_I2C3EN_Pos) /*!< 0x00800000 */
+#define RCC_APB1LENR_I2C3EN                    RCC_APB1LENR_I2C3EN_Msk
+#define RCC_APB1LENR_CECEN_Pos                 (27U)
+#define RCC_APB1LENR_CECEN_Msk                 (0x1UL << RCC_APB1LENR_CECEN_Pos) /*!< 0x08000000 */
+#define RCC_APB1LENR_CECEN                     RCC_APB1LENR_CECEN_Msk
+#define RCC_APB1LENR_DAC12EN_Pos               (29U)
+#define RCC_APB1LENR_DAC12EN_Msk               (0x1UL << RCC_APB1LENR_DAC12EN_Pos) /*!< 0x20000000 */
+#define RCC_APB1LENR_DAC12EN                   RCC_APB1LENR_DAC12EN_Msk
+#define RCC_APB1LENR_UART7EN_Pos               (30U)
+#define RCC_APB1LENR_UART7EN_Msk               (0x1UL << RCC_APB1LENR_UART7EN_Pos) /*!< 0x40000000 */
+#define RCC_APB1LENR_UART7EN                   RCC_APB1LENR_UART7EN_Msk
+#define RCC_APB1LENR_UART8EN_Pos               (31U)
+#define RCC_APB1LENR_UART8EN_Msk               (0x1UL << RCC_APB1LENR_UART8EN_Pos) /*!< 0x80000000 */
+#define RCC_APB1LENR_UART8EN                   RCC_APB1LENR_UART8EN_Msk
+
+/* Legacy define */
+#define RCC_APB1LENR_HDMICECEN_Pos             RCC_APB1LENR_CECEN_Pos
+#define RCC_APB1LENR_HDMICECEN_Msk             RCC_APB1LENR_CECEN_Msk
+#define RCC_APB1LENR_HDMICECEN                 RCC_APB1LENR_CECEN
+/********************  Bit definition for RCC_APB1HENR register  ******************/
+#define RCC_APB1HENR_CRSEN_Pos                 (1U)
+#define RCC_APB1HENR_CRSEN_Msk                 (0x1UL << RCC_APB1HENR_CRSEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1HENR_CRSEN                     RCC_APB1HENR_CRSEN_Msk
+#define RCC_APB1HENR_SWPMIEN_Pos               (2U)
+#define RCC_APB1HENR_SWPMIEN_Msk               (0x1UL << RCC_APB1HENR_SWPMIEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1HENR_SWPMIEN                   RCC_APB1HENR_SWPMIEN_Msk
+#define RCC_APB1HENR_OPAMPEN_Pos               (4U)
+#define RCC_APB1HENR_OPAMPEN_Msk               (0x1UL << RCC_APB1HENR_OPAMPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1HENR_OPAMPEN                   RCC_APB1HENR_OPAMPEN_Msk
+#define RCC_APB1HENR_MDIOSEN_Pos               (5U)
+#define RCC_APB1HENR_MDIOSEN_Msk               (0x1UL << RCC_APB1HENR_MDIOSEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1HENR_MDIOSEN                   RCC_APB1HENR_MDIOSEN_Msk
+#define RCC_APB1HENR_FDCANEN_Pos               (8U)
+#define RCC_APB1HENR_FDCANEN_Msk               (0x1UL << RCC_APB1HENR_FDCANEN_Pos) /*!< 0x00000100 */
+#define RCC_APB1HENR_FDCANEN                   RCC_APB1HENR_FDCANEN_Msk
+
+/********************  Bit definition for RCC_APB2ENR register  ******************/
+#define RCC_APB2ENR_TIM1EN_Pos                 (0U)
+#define RCC_APB2ENR_TIM1EN_Msk                 (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_TIM1EN                     RCC_APB2ENR_TIM1EN_Msk
+#define RCC_APB2ENR_TIM8EN_Pos                 (1U)
+#define RCC_APB2ENR_TIM8EN_Msk                 (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
+#define RCC_APB2ENR_TIM8EN                     RCC_APB2ENR_TIM8EN_Msk
+#define RCC_APB2ENR_USART1EN_Pos               (4U)
+#define RCC_APB2ENR_USART1EN_Msk               (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
+#define RCC_APB2ENR_USART1EN                   RCC_APB2ENR_USART1EN_Msk
+#define RCC_APB2ENR_USART6EN_Pos               (5U)
+#define RCC_APB2ENR_USART6EN_Msk               (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_USART6EN                   RCC_APB2ENR_USART6EN_Msk
+#define RCC_APB2ENR_SPI1EN_Pos                 (12U)
+#define RCC_APB2ENR_SPI1EN_Msk                 (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN                     RCC_APB2ENR_SPI1EN_Msk
+#define RCC_APB2ENR_SPI4EN_Pos                 (13U)
+#define RCC_APB2ENR_SPI4EN_Msk                 (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
+#define RCC_APB2ENR_SPI4EN                     RCC_APB2ENR_SPI4EN_Msk
+#define RCC_APB2ENR_TIM15EN_Pos                (16U)
+#define RCC_APB2ENR_TIM15EN_Msk                (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
+#define RCC_APB2ENR_TIM15EN                    RCC_APB2ENR_TIM15EN_Msk
+#define RCC_APB2ENR_TIM16EN_Pos                (17U)
+#define RCC_APB2ENR_TIM16EN_Msk                (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
+#define RCC_APB2ENR_TIM16EN                    RCC_APB2ENR_TIM16EN_Msk
+#define RCC_APB2ENR_TIM17EN_Pos                (18U)
+#define RCC_APB2ENR_TIM17EN_Msk                (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
+#define RCC_APB2ENR_TIM17EN                    RCC_APB2ENR_TIM17EN_Msk
+#define RCC_APB2ENR_SPI5EN_Pos                 (20U)
+#define RCC_APB2ENR_SPI5EN_Msk                 (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB2ENR_SPI5EN                     RCC_APB2ENR_SPI5EN_Msk
+#define RCC_APB2ENR_SAI1EN_Pos                 (22U)
+#define RCC_APB2ENR_SAI1EN_Msk                 (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */
+#define RCC_APB2ENR_SAI1EN                     RCC_APB2ENR_SAI1EN_Msk
+#define RCC_APB2ENR_SAI2EN_Pos                 (23U)
+#define RCC_APB2ENR_SAI2EN_Msk                 (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */
+#define RCC_APB2ENR_SAI2EN                     RCC_APB2ENR_SAI2EN_Msk
+#define RCC_APB2ENR_SAI3EN_Pos                 (24U)
+#define RCC_APB2ENR_SAI3EN_Msk                 (0x1UL << RCC_APB2ENR_SAI3EN_Pos) /*!< 0x01000000 */
+#define RCC_APB2ENR_SAI3EN                     RCC_APB2ENR_SAI3EN_Msk
+#define RCC_APB2ENR_DFSDM1EN_Pos               (28U)
+#define RCC_APB2ENR_DFSDM1EN_Msk               (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x10000000 */
+#define RCC_APB2ENR_DFSDM1EN                   RCC_APB2ENR_DFSDM1EN_Msk
+#define RCC_APB2ENR_HRTIMEN_Pos                (29U)
+#define RCC_APB2ENR_HRTIMEN_Msk                (0x1UL << RCC_APB2ENR_HRTIMEN_Pos) /*!< 0x20000000 */
+#define RCC_APB2ENR_HRTIMEN                    RCC_APB2ENR_HRTIMEN_Msk
+
+/********************  Bit definition for RCC_APB4ENR register  ******************/
+#define RCC_APB4ENR_SYSCFGEN_Pos               (1U)
+#define RCC_APB4ENR_SYSCFGEN_Msk               (0x1UL << RCC_APB4ENR_SYSCFGEN_Pos) /*!< 0x00000002 */
+#define RCC_APB4ENR_SYSCFGEN                   RCC_APB4ENR_SYSCFGEN_Msk
+#define RCC_APB4ENR_LPUART1EN_Pos              (3U)
+#define RCC_APB4ENR_LPUART1EN_Msk              (0x1UL << RCC_APB4ENR_LPUART1EN_Pos) /*!< 0x00000008 */
+#define RCC_APB4ENR_LPUART1EN                  RCC_APB4ENR_LPUART1EN_Msk
+#define RCC_APB4ENR_SPI6EN_Pos                 (5U)
+#define RCC_APB4ENR_SPI6EN_Msk                 (0x1UL << RCC_APB4ENR_SPI6EN_Pos) /*!< 0x00000020 */
+#define RCC_APB4ENR_SPI6EN                     RCC_APB4ENR_SPI6EN_Msk
+#define RCC_APB4ENR_I2C4EN_Pos                 (7U)
+#define RCC_APB4ENR_I2C4EN_Msk                 (0x1UL << RCC_APB4ENR_I2C4EN_Pos) /*!< 0x00000080 */
+#define RCC_APB4ENR_I2C4EN                     RCC_APB4ENR_I2C4EN_Msk
+#define RCC_APB4ENR_LPTIM2EN_Pos               (9U)
+#define RCC_APB4ENR_LPTIM2EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos) /*!< 0x00000200 */
+#define RCC_APB4ENR_LPTIM2EN                   RCC_APB4ENR_LPTIM2EN_Msk
+#define RCC_APB4ENR_LPTIM3EN_Pos               (10U)
+#define RCC_APB4ENR_LPTIM3EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos) /*!< 0x00000400 */
+#define RCC_APB4ENR_LPTIM3EN                   RCC_APB4ENR_LPTIM3EN_Msk
+#define RCC_APB4ENR_LPTIM4EN_Pos               (11U)
+#define RCC_APB4ENR_LPTIM4EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM4EN_Pos) /*!< 0x00000800 */
+#define RCC_APB4ENR_LPTIM4EN                   RCC_APB4ENR_LPTIM4EN_Msk
+#define RCC_APB4ENR_LPTIM5EN_Pos               (12U)
+#define RCC_APB4ENR_LPTIM5EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM5EN_Pos) /*!< 0x00001000 */
+#define RCC_APB4ENR_LPTIM5EN                   RCC_APB4ENR_LPTIM5EN_Msk
+#define RCC_APB4ENR_COMP12EN_Pos               (14U)
+#define RCC_APB4ENR_COMP12EN_Msk               (0x1UL << RCC_APB4ENR_COMP12EN_Pos) /*!< 0x00004000 */
+#define RCC_APB4ENR_COMP12EN                   RCC_APB4ENR_COMP12EN_Msk
+#define RCC_APB4ENR_VREFEN_Pos                 (15U)
+#define RCC_APB4ENR_VREFEN_Msk                 (0x1UL << RCC_APB4ENR_VREFEN_Pos) /*!< 0x00008000 */
+#define RCC_APB4ENR_VREFEN                     RCC_APB4ENR_VREFEN_Msk
+#define RCC_APB4ENR_RTCAPBEN_Pos               (16U)
+#define RCC_APB4ENR_RTCAPBEN_Msk               (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos) /*!< 0x00010000 */
+#define RCC_APB4ENR_RTCAPBEN                   RCC_APB4ENR_RTCAPBEN_Msk
+#define RCC_APB4ENR_SAI4EN_Pos                 (21U)
+#define RCC_APB4ENR_SAI4EN_Msk                 (0x1UL << RCC_APB4ENR_SAI4EN_Pos) /*!< 0x00200000 */
+#define RCC_APB4ENR_SAI4EN                     RCC_APB4ENR_SAI4EN_Msk
+
+
+/********************  Bit definition for RCC_AHB3RSTR register  ***************/
+#define RCC_AHB3RSTR_MDMARST_Pos               (0U)
+#define RCC_AHB3RSTR_MDMARST_Msk               (0x1UL << RCC_AHB3RSTR_MDMARST_Pos)      /*!< 0x00000001 */
+#define RCC_AHB3RSTR_MDMARST                   RCC_AHB3RSTR_MDMARST_Msk
+#define RCC_AHB3RSTR_DMA2DRST_Pos              (4U)
+#define RCC_AHB3RSTR_DMA2DRST_Msk              (0x1UL << RCC_AHB3RSTR_DMA2DRST_Pos)     /*!< 0x00000010 */
+#define RCC_AHB3RSTR_DMA2DRST                  RCC_AHB3RSTR_DMA2DRST_Msk
+#define RCC_AHB3RSTR_JPGDECRST_Pos             (5U)
+#define RCC_AHB3RSTR_JPGDECRST_Msk             (0x1UL << RCC_AHB3RSTR_JPGDECRST_Pos)    /*!< 0x00000020 */
+#define RCC_AHB3RSTR_JPGDECRST                 RCC_AHB3RSTR_JPGDECRST_Msk
+#define RCC_AHB3RSTR_FMCRST_Pos                (12U)
+#define RCC_AHB3RSTR_FMCRST_Msk                (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)      /*!< 0x00001000 */
+#define RCC_AHB3RSTR_FMCRST                    RCC_AHB3RSTR_FMCRST_Msk
+#define RCC_AHB3RSTR_QSPIRST_Pos               (14U)
+#define RCC_AHB3RSTR_QSPIRST_Msk               (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)     /*!< 0x00004000 */
+#define RCC_AHB3RSTR_QSPIRST                   RCC_AHB3RSTR_QSPIRST_Msk
+#define RCC_AHB3RSTR_SDMMC1RST_Pos             (16U)
+#define RCC_AHB3RSTR_SDMMC1RST_Msk             (0x1UL << RCC_AHB3RSTR_SDMMC1RST_Pos)   /*!< 0x00010000 */
+#define RCC_AHB3RSTR_SDMMC1RST                 RCC_AHB3RSTR_SDMMC1RST_Msk
+
+
+/********************  Bit definition for RCC_AHB1RSTR register  ***************/
+#define RCC_AHB1RSTR_DMA1RST_Pos               (0U)
+#define RCC_AHB1RSTR_DMA1RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)      /*!< 0x00000001 */
+#define RCC_AHB1RSTR_DMA1RST                   RCC_AHB1RSTR_DMA1RST_Msk
+#define RCC_AHB1RSTR_DMA2RST_Pos               (1U)
+#define RCC_AHB1RSTR_DMA2RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)      /*!< 0x00000002 */
+#define RCC_AHB1RSTR_DMA2RST                   RCC_AHB1RSTR_DMA2RST_Msk
+#define RCC_AHB1RSTR_ADC12RST_Pos              (5U)
+#define RCC_AHB1RSTR_ADC12RST_Msk              (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos)     /*!< 0x00000020 */
+#define RCC_AHB1RSTR_ADC12RST                  RCC_AHB1RSTR_ADC12RST_Msk
+#define RCC_AHB1RSTR_ETH1MACRST_Pos            (15U)
+#define RCC_AHB1RSTR_ETH1MACRST_Msk            (0x1UL << RCC_AHB1RSTR_ETH1MACRST_Pos)   /*!< 0x00008000 */
+#define RCC_AHB1RSTR_ETH1MACRST                RCC_AHB1RSTR_ETH1MACRST_Msk
+#define RCC_AHB1RSTR_USB1OTGHSRST_Pos          (25U)
+#define RCC_AHB1RSTR_USB1OTGHSRST_Msk          (0x1UL << RCC_AHB1RSTR_USB1OTGHSRST_Pos) /*!< 0x02000000 */
+#define RCC_AHB1RSTR_USB1OTGHSRST              RCC_AHB1RSTR_USB1OTGHSRST_Msk
+#define RCC_AHB1RSTR_USB2OTGFSRST_Pos          (27U)
+#define RCC_AHB1RSTR_USB2OTGFSRST_Msk          (0x1UL << RCC_AHB1RSTR_USB2OTGFSRST_Pos) /*!< 0x08000000 */
+#define RCC_AHB1RSTR_USB2OTGFSRST              RCC_AHB1RSTR_USB2OTGFSRST_Msk
+
+/* Legacy define */
+#define RCC_AHB1RSTR_USB2OTGHSRST_Pos          RCC_AHB1RSTR_USB2OTGFSRST_Pos
+#define RCC_AHB1RSTR_USB2OTGHSRST_Msk          RCC_AHB1RSTR_USB2OTGFSRST_Msk
+#define RCC_AHB1RSTR_USB2OTGHSRST              RCC_AHB1RSTR_USB2OTGFSRST
+
+/********************  Bit definition for RCC_AHB2RSTR register  ***************/
+#define RCC_AHB2RSTR_DCMIRST_Pos               (0U)
+#define RCC_AHB2RSTR_DCMIRST_Msk               (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)       /*!< 0x00000001 */
+#define RCC_AHB2RSTR_DCMIRST                   RCC_AHB2RSTR_DCMIRST_Msk
+#define RCC_AHB2RSTR_RNGRST_Pos                (6U)
+#define RCC_AHB2RSTR_RNGRST_Msk                (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)        /*!< 0x00000040 */
+#define RCC_AHB2RSTR_RNGRST                    RCC_AHB2RSTR_RNGRST_Msk
+#define RCC_AHB2RSTR_SDMMC2RST_Pos             (9U)
+#define RCC_AHB2RSTR_SDMMC2RST_Msk             (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos)     /*!< 0x00000200 */
+#define RCC_AHB2RSTR_SDMMC2RST                 RCC_AHB2RSTR_SDMMC2RST_Msk
+
+/********************  Bit definition for RCC_AHB4RSTR register  ******************/
+#define RCC_AHB4RSTR_GPIOARST_Pos              (0U)
+#define RCC_AHB4RSTR_GPIOARST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos)      /*!< 0x00000001 */
+#define RCC_AHB4RSTR_GPIOARST                  RCC_AHB4RSTR_GPIOARST_Msk
+#define RCC_AHB4RSTR_GPIOBRST_Pos              (1U)
+#define RCC_AHB4RSTR_GPIOBRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos)      /*!< 0x00000002 */
+#define RCC_AHB4RSTR_GPIOBRST                  RCC_AHB4RSTR_GPIOBRST_Msk
+#define RCC_AHB4RSTR_GPIOCRST_Pos              (2U)
+#define RCC_AHB4RSTR_GPIOCRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos)      /*!< 0x00000004 */
+#define RCC_AHB4RSTR_GPIOCRST                  RCC_AHB4RSTR_GPIOCRST_Msk
+#define RCC_AHB4RSTR_GPIODRST_Pos              (3U)
+#define RCC_AHB4RSTR_GPIODRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos)      /*!< 0x00000008 */
+#define RCC_AHB4RSTR_GPIODRST                  RCC_AHB4RSTR_GPIODRST_Msk
+#define RCC_AHB4RSTR_GPIOERST_Pos              (4U)
+#define RCC_AHB4RSTR_GPIOERST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos)      /*!< 0x00000010 */
+#define RCC_AHB4RSTR_GPIOERST                  RCC_AHB4RSTR_GPIOERST_Msk
+#define RCC_AHB4RSTR_GPIOFRST_Pos              (5U)
+#define RCC_AHB4RSTR_GPIOFRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos)       /*!< 0x00000020 */
+#define RCC_AHB4RSTR_GPIOFRST                  RCC_AHB4RSTR_GPIOFRST_Msk
+#define RCC_AHB4RSTR_GPIOGRST_Pos              (6U)
+#define RCC_AHB4RSTR_GPIOGRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos)       /*!< 0x00000040 */
+#define RCC_AHB4RSTR_GPIOGRST                  RCC_AHB4RSTR_GPIOGRST_Msk
+#define RCC_AHB4RSTR_GPIOHRST_Pos              (7U)
+#define RCC_AHB4RSTR_GPIOHRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos)       /*!< 0x00000080 */
+#define RCC_AHB4RSTR_GPIOHRST                  RCC_AHB4RSTR_GPIOHRST_Msk
+#define RCC_AHB4RSTR_GPIOIRST_Pos              (8U)
+#define RCC_AHB4RSTR_GPIOIRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOIRST_Pos)       /*!< 0x00000100 */
+#define RCC_AHB4RSTR_GPIOIRST                  RCC_AHB4RSTR_GPIOIRST_Msk
+#define RCC_AHB4RSTR_GPIOJRST_Pos              (9U)
+#define RCC_AHB4RSTR_GPIOJRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOJRST_Pos)       /*!< 0x00000200 */
+#define RCC_AHB4RSTR_GPIOJRST                  RCC_AHB4RSTR_GPIOJRST_Msk
+#define RCC_AHB4RSTR_GPIOKRST_Pos              (10U)
+#define RCC_AHB4RSTR_GPIOKRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOKRST_Pos)       /*!< 0x00000400 */
+#define RCC_AHB4RSTR_GPIOKRST                  RCC_AHB4RSTR_GPIOKRST_Msk
+#define RCC_AHB4RSTR_CRCRST_Pos                (19U)
+#define RCC_AHB4RSTR_CRCRST_Msk                (0x1UL << RCC_AHB4RSTR_CRCRST_Pos)         /*!< 0x00080000 */
+#define RCC_AHB4RSTR_CRCRST                    RCC_AHB4RSTR_CRCRST_Msk
+#define RCC_AHB4RSTR_BDMARST_Pos               (21U)
+#define RCC_AHB4RSTR_BDMARST_Msk               (0x1UL << RCC_AHB4RSTR_BDMARST_Pos)        /*!< 0x00200000 */
+#define RCC_AHB4RSTR_BDMARST                   RCC_AHB4RSTR_BDMARST_Msk
+#define RCC_AHB4RSTR_ADC3RST_Pos               (24U)
+#define RCC_AHB4RSTR_ADC3RST_Msk               (0x1UL << RCC_AHB4RSTR_ADC3RST_Pos)        /*!< 0x01000000 */
+#define RCC_AHB4RSTR_ADC3RST                   RCC_AHB4RSTR_ADC3RST_Msk
+#define RCC_AHB4RSTR_HSEMRST_Pos               (25U)
+#define RCC_AHB4RSTR_HSEMRST_Msk               (0x1UL << RCC_AHB4RSTR_HSEMRST_Pos)        /*!< 0x02000000 */
+#define RCC_AHB4RSTR_HSEMRST                   RCC_AHB4RSTR_HSEMRST_Msk
+
+
+/********************  Bit definition for RCC_APB3RSTR register  ******************/
+#define RCC_APB3RSTR_LTDCRST_Pos               (3U)
+#define RCC_APB3RSTR_LTDCRST_Msk               (0x1UL << RCC_APB3RSTR_LTDCRST_Pos) /*!< 0x00000008 */
+#define RCC_APB3RSTR_LTDCRST                   RCC_APB3RSTR_LTDCRST_Msk
+
+/********************  Bit definition for RCC_APB1LRSTR register  ******************/
+
+#define RCC_APB1LRSTR_TIM2RST_Pos              (0U)
+#define RCC_APB1LRSTR_TIM2RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1LRSTR_TIM2RST                  RCC_APB1LRSTR_TIM2RST_Msk
+#define RCC_APB1LRSTR_TIM3RST_Pos              (1U)
+#define RCC_APB1LRSTR_TIM3RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1LRSTR_TIM3RST                  RCC_APB1LRSTR_TIM3RST_Msk
+#define RCC_APB1LRSTR_TIM4RST_Pos              (2U)
+#define RCC_APB1LRSTR_TIM4RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1LRSTR_TIM4RST                  RCC_APB1LRSTR_TIM4RST_Msk
+#define RCC_APB1LRSTR_TIM5RST_Pos              (3U)
+#define RCC_APB1LRSTR_TIM5RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos) /*!< 0x00000008 */
+#define RCC_APB1LRSTR_TIM5RST                  RCC_APB1LRSTR_TIM5RST_Msk
+#define RCC_APB1LRSTR_TIM6RST_Pos              (4U)
+#define RCC_APB1LRSTR_TIM6RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1LRSTR_TIM6RST                  RCC_APB1LRSTR_TIM6RST_Msk
+#define RCC_APB1LRSTR_TIM7RST_Pos              (5U)
+#define RCC_APB1LRSTR_TIM7RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1LRSTR_TIM7RST                  RCC_APB1LRSTR_TIM7RST_Msk
+#define RCC_APB1LRSTR_TIM12RST_Pos             (6U)
+#define RCC_APB1LRSTR_TIM12RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos) /*!< 0x00000040 */
+#define RCC_APB1LRSTR_TIM12RST                 RCC_APB1LRSTR_TIM12RST_Msk
+#define RCC_APB1LRSTR_TIM13RST_Pos             (7U)
+#define RCC_APB1LRSTR_TIM13RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM13RST_Pos) /*!< 0x00000080 */
+#define RCC_APB1LRSTR_TIM13RST                 RCC_APB1LRSTR_TIM13RST_Msk
+#define RCC_APB1LRSTR_TIM14RST_Pos             (8U)
+#define RCC_APB1LRSTR_TIM14RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM14RST_Pos) /*!< 0x00000100 */
+#define RCC_APB1LRSTR_TIM14RST                 RCC_APB1LRSTR_TIM14RST_Msk
+#define RCC_APB1LRSTR_LPTIM1RST_Pos            (9U)
+#define RCC_APB1LRSTR_LPTIM1RST_Msk            (0x1UL << RCC_APB1LRSTR_LPTIM1RST_Pos) /*!< 0x00000200 */
+#define RCC_APB1LRSTR_LPTIM1RST                RCC_APB1LRSTR_LPTIM1RST_Msk
+#define RCC_APB1LRSTR_SPI2RST_Pos              (14U)
+#define RCC_APB1LRSTR_SPI2RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1LRSTR_SPI2RST                  RCC_APB1LRSTR_SPI2RST_Msk
+#define RCC_APB1LRSTR_SPI3RST_Pos              (15U)
+#define RCC_APB1LRSTR_SPI3RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos) /*!< 0x00008000 */
+#define RCC_APB1LRSTR_SPI3RST                  RCC_APB1LRSTR_SPI3RST_Msk
+#define RCC_APB1LRSTR_SPDIFRXRST_Pos           (16U)
+#define RCC_APB1LRSTR_SPDIFRXRST_Msk           (0x1UL << RCC_APB1LRSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */
+#define RCC_APB1LRSTR_SPDIFRXRST               RCC_APB1LRSTR_SPDIFRXRST_Msk
+#define RCC_APB1LRSTR_USART2RST_Pos            (17U)
+#define RCC_APB1LRSTR_USART2RST_Msk            (0x1UL << RCC_APB1LRSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1LRSTR_USART2RST                RCC_APB1LRSTR_USART2RST_Msk
+#define RCC_APB1LRSTR_USART3RST_Pos            (18U)
+#define RCC_APB1LRSTR_USART3RST_Msk            (0x1UL << RCC_APB1LRSTR_USART3RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1LRSTR_USART3RST                RCC_APB1LRSTR_USART3RST_Msk
+#define RCC_APB1LRSTR_UART4RST_Pos             (19U)
+#define RCC_APB1LRSTR_UART4RST_Msk             (0x1UL << RCC_APB1LRSTR_UART4RST_Pos) /*!< 0x00080000 */
+#define RCC_APB1LRSTR_UART4RST                 RCC_APB1LRSTR_UART4RST_Msk
+#define RCC_APB1LRSTR_UART5RST_Pos             (20U)
+#define RCC_APB1LRSTR_UART5RST_Msk             (0x1UL << RCC_APB1LRSTR_UART5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB1LRSTR_UART5RST                 RCC_APB1LRSTR_UART5RST_Msk
+#define RCC_APB1LRSTR_I2C1RST_Pos              (21U)
+#define RCC_APB1LRSTR_I2C1RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1LRSTR_I2C1RST                  RCC_APB1LRSTR_I2C1RST_Msk
+#define RCC_APB1LRSTR_I2C2RST_Pos              (22U)
+#define RCC_APB1LRSTR_I2C2RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1LRSTR_I2C2RST                  RCC_APB1LRSTR_I2C2RST_Msk
+#define RCC_APB1LRSTR_I2C3RST_Pos              (23U)
+#define RCC_APB1LRSTR_I2C3RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C3RST_Pos) /*!< 0x00800000 */
+#define RCC_APB1LRSTR_I2C3RST                  RCC_APB1LRSTR_I2C3RST_Msk
+#define RCC_APB1LRSTR_CECRST_Pos               (27U)
+#define RCC_APB1LRSTR_CECRST_Msk               (0x1UL << RCC_APB1LRSTR_CECRST_Pos) /*!< 0x08000000 */
+#define RCC_APB1LRSTR_CECRST                   RCC_APB1LRSTR_CECRST_Msk
+#define RCC_APB1LRSTR_DAC12RST_Pos             (29U)
+#define RCC_APB1LRSTR_DAC12RST_Msk             (0x1UL << RCC_APB1LRSTR_DAC12RST_Pos) /*!< 0x20000000 */
+#define RCC_APB1LRSTR_DAC12RST                 RCC_APB1LRSTR_DAC12RST_Msk
+#define RCC_APB1LRSTR_UART7RST_Pos             (30U)
+#define RCC_APB1LRSTR_UART7RST_Msk             (0x1UL << RCC_APB1LRSTR_UART7RST_Pos) /*!< 0x40000000 */
+#define RCC_APB1LRSTR_UART7RST                 RCC_APB1LRSTR_UART7RST_Msk
+#define RCC_APB1LRSTR_UART8RST_Pos             (31U)
+#define RCC_APB1LRSTR_UART8RST_Msk             (0x1UL << RCC_APB1LRSTR_UART8RST_Pos) /*!< 0x80000000 */
+#define RCC_APB1LRSTR_UART8RST                 RCC_APB1LRSTR_UART8RST_Msk
+
+/* Legacy define */
+#define RCC_APB1LRSTR_HDMICECRST_Pos           RCC_APB1LRSTR_CECRST_Pos
+#define RCC_APB1LRSTR_HDMICECRST_Msk           RCC_APB1LRSTR_CECRST_Msk
+#define RCC_APB1LRSTR_HDMICECRST               RCC_APB1LRSTR_CECRST
+/********************  Bit definition for RCC_APB1HRSTR register  ******************/
+#define RCC_APB1HRSTR_CRSRST_Pos               (1U)
+#define RCC_APB1HRSTR_CRSRST_Msk               (0x1UL << RCC_APB1HRSTR_CRSRST_Pos) /*!< 0x00000002 */
+#define RCC_APB1HRSTR_CRSRST                   RCC_APB1HRSTR_CRSRST_Msk
+#define RCC_APB1HRSTR_SWPMIRST_Pos             (2U)
+#define RCC_APB1HRSTR_SWPMIRST_Msk             (0x1UL << RCC_APB1HRSTR_SWPMIRST_Pos) /*!< 0x00000004 */
+#define RCC_APB1HRSTR_SWPMIRST                 RCC_APB1HRSTR_SWPMIRST_Msk
+#define RCC_APB1HRSTR_OPAMPRST_Pos             (4U)
+#define RCC_APB1HRSTR_OPAMPRST_Msk             (0x1UL << RCC_APB1HRSTR_OPAMPRST_Pos) /*!< 0x00000010 */
+#define RCC_APB1HRSTR_OPAMPRST                 RCC_APB1HRSTR_OPAMPRST_Msk
+#define RCC_APB1HRSTR_MDIOSRST_Pos             (5U)
+#define RCC_APB1HRSTR_MDIOSRST_Msk             (0x1UL << RCC_APB1HRSTR_MDIOSRST_Pos) /*!< 0x00000020 */
+#define RCC_APB1HRSTR_MDIOSRST                 RCC_APB1HRSTR_MDIOSRST_Msk
+#define RCC_APB1HRSTR_FDCANRST_Pos             (8U)
+#define RCC_APB1HRSTR_FDCANRST_Msk             (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos) /*!< 0x00000100 */
+#define RCC_APB1HRSTR_FDCANRST                 RCC_APB1HRSTR_FDCANRST_Msk
+
+/********************  Bit definition for RCC_APB2RSTR register  ******************/
+#define RCC_APB2RSTR_TIM1RST_Pos               (0U)
+#define RCC_APB2RSTR_TIM1RST_Msk               (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_TIM1RST                   RCC_APB2RSTR_TIM1RST_Msk
+#define RCC_APB2RSTR_TIM8RST_Pos               (1U)
+#define RCC_APB2RSTR_TIM8RST_Msk               (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
+#define RCC_APB2RSTR_TIM8RST                   RCC_APB2RSTR_TIM8RST_Msk
+#define RCC_APB2RSTR_USART1RST_Pos             (4U)
+#define RCC_APB2RSTR_USART1RST_Msk             (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTR_USART1RST                 RCC_APB2RSTR_USART1RST_Msk
+#define RCC_APB2RSTR_USART6RST_Pos             (5U)
+#define RCC_APB2RSTR_USART6RST_Msk             (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_USART6RST                 RCC_APB2RSTR_USART6RST_Msk
+#define RCC_APB2RSTR_SPI1RST_Pos               (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk               (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST                   RCC_APB2RSTR_SPI1RST_Msk
+#define RCC_APB2RSTR_SPI4RST_Pos               (13U)
+#define RCC_APB2RSTR_SPI4RST_Msk               (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
+#define RCC_APB2RSTR_SPI4RST                   RCC_APB2RSTR_SPI4RST_Msk
+#define RCC_APB2RSTR_TIM15RST_Pos              (16U)
+#define RCC_APB2RSTR_TIM15RST_Msk              (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
+#define RCC_APB2RSTR_TIM15RST                  RCC_APB2RSTR_TIM15RST_Msk
+#define RCC_APB2RSTR_TIM16RST_Pos              (17U)
+#define RCC_APB2RSTR_TIM16RST_Msk              (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
+#define RCC_APB2RSTR_TIM16RST                  RCC_APB2RSTR_TIM16RST_Msk
+#define RCC_APB2RSTR_TIM17RST_Pos              (18U)
+#define RCC_APB2RSTR_TIM17RST_Msk              (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
+#define RCC_APB2RSTR_TIM17RST                  RCC_APB2RSTR_TIM17RST_Msk
+#define RCC_APB2RSTR_SPI5RST_Pos               (20U)
+#define RCC_APB2RSTR_SPI5RST_Msk               (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB2RSTR_SPI5RST                   RCC_APB2RSTR_SPI5RST_Msk
+#define RCC_APB2RSTR_SAI1RST_Pos               (22U)
+#define RCC_APB2RSTR_SAI1RST_Msk               (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */
+#define RCC_APB2RSTR_SAI1RST                   RCC_APB2RSTR_SAI1RST_Msk
+#define RCC_APB2RSTR_SAI2RST_Pos               (23U)
+#define RCC_APB2RSTR_SAI2RST_Msk               (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */
+#define RCC_APB2RSTR_SAI2RST                   RCC_APB2RSTR_SAI2RST_Msk
+#define RCC_APB2RSTR_SAI3RST_Pos               (24U)
+#define RCC_APB2RSTR_SAI3RST_Msk               (0x1UL << RCC_APB2RSTR_SAI3RST_Pos) /*!< 0x01000000 */
+#define RCC_APB2RSTR_SAI3RST                   RCC_APB2RSTR_SAI3RST_Msk
+#define RCC_APB2RSTR_DFSDM1RST_Pos             (28U)
+#define RCC_APB2RSTR_DFSDM1RST_Msk             (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x10000000 */
+#define RCC_APB2RSTR_DFSDM1RST                 RCC_APB2RSTR_DFSDM1RST_Msk
+#define RCC_APB2RSTR_HRTIMRST_Pos              (29U)
+#define RCC_APB2RSTR_HRTIMRST_Msk              (0x1UL << RCC_APB2RSTR_HRTIMRST_Pos) /*!< 0x20000000 */
+#define RCC_APB2RSTR_HRTIMRST                  RCC_APB2RSTR_HRTIMRST_Msk
+
+/********************  Bit definition for RCC_APB4RSTR register  ******************/
+#define RCC_APB4RSTR_SYSCFGRST_Pos             (1U)
+#define RCC_APB4RSTR_SYSCFGRST_Msk             (0x1UL << RCC_APB4RSTR_SYSCFGRST_Pos) /*!< 0x00000002 */
+#define RCC_APB4RSTR_SYSCFGRST                 RCC_APB4RSTR_SYSCFGRST_Msk
+#define RCC_APB4RSTR_LPUART1RST_Pos            (3U)
+#define RCC_APB4RSTR_LPUART1RST_Msk            (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos) /*!< 0x00000008 */
+#define RCC_APB4RSTR_LPUART1RST                RCC_APB4RSTR_LPUART1RST_Msk
+#define RCC_APB4RSTR_SPI6RST_Pos               (5U)
+#define RCC_APB4RSTR_SPI6RST_Msk               (0x1UL << RCC_APB4RSTR_SPI6RST_Pos) /*!< 0x00000020 */
+#define RCC_APB4RSTR_SPI6RST                   RCC_APB4RSTR_SPI6RST_Msk
+#define RCC_APB4RSTR_I2C4RST_Pos               (7U)
+#define RCC_APB4RSTR_I2C4RST_Msk               (0x1UL << RCC_APB4RSTR_I2C4RST_Pos) /*!< 0x00000080 */
+#define RCC_APB4RSTR_I2C4RST                   RCC_APB4RSTR_I2C4RST_Msk
+#define RCC_APB4RSTR_LPTIM2RST_Pos             (9U)
+#define RCC_APB4RSTR_LPTIM2RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos) /*!< 0x00000200 */
+#define RCC_APB4RSTR_LPTIM2RST                 RCC_APB4RSTR_LPTIM2RST_Msk
+#define RCC_APB4RSTR_LPTIM3RST_Pos             (10U)
+#define RCC_APB4RSTR_LPTIM3RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos) /*!< 0x00000400 */
+#define RCC_APB4RSTR_LPTIM3RST                 RCC_APB4RSTR_LPTIM3RST_Msk
+#define RCC_APB4RSTR_LPTIM4RST_Pos             (11U)
+#define RCC_APB4RSTR_LPTIM4RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM4RST_Pos) /*!< 0x00000800 */
+#define RCC_APB4RSTR_LPTIM4RST                 RCC_APB4RSTR_LPTIM4RST_Msk
+#define RCC_APB4RSTR_LPTIM5RST_Pos             (12U)
+#define RCC_APB4RSTR_LPTIM5RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM5RST_Pos) /*!< 0x00001000 */
+#define RCC_APB4RSTR_LPTIM5RST                 RCC_APB4RSTR_LPTIM5RST_Msk
+#define RCC_APB4RSTR_COMP12RST_Pos             (14U)
+#define RCC_APB4RSTR_COMP12RST_Msk             (0x1UL << RCC_APB4RSTR_COMP12RST_Pos) /*!< 0x00004000 */
+#define RCC_APB4RSTR_COMP12RST                 RCC_APB4RSTR_COMP12RST_Msk
+#define RCC_APB4RSTR_VREFRST_Pos               (15U)
+#define RCC_APB4RSTR_VREFRST_Msk               (0x1UL << RCC_APB4RSTR_VREFRST_Pos) /*!< 0x00008000 */
+#define RCC_APB4RSTR_VREFRST                   RCC_APB4RSTR_VREFRST_Msk
+#define RCC_APB4RSTR_SAI4RST_Pos               (21U)
+#define RCC_APB4RSTR_SAI4RST_Msk               (0x1UL << RCC_APB4RSTR_SAI4RST_Pos) /*!< 0x00200000 */
+#define RCC_APB4RSTR_SAI4RST                   RCC_APB4RSTR_SAI4RST_Msk
+
+
+/********************  Bit definition for RCC_GCR register  ********************/
+#define RCC_GCR_WW1RSC_Pos                     (0U)
+#define RCC_GCR_WW1RSC_Msk                     (0x1UL << RCC_GCR_WW1RSC_Pos)   /*!< 0x00000001 */
+#define RCC_GCR_WW1RSC                         RCC_GCR_WW1RSC_Msk
+
+/********************  Bit definition for RCC_D3AMR register  ********************/
+#define RCC_D3AMR_BDMAAMEN_Pos                 (0U)
+#define RCC_D3AMR_BDMAAMEN_Msk                 (0x1UL << RCC_D3AMR_BDMAAMEN_Pos) /*!< 0x00000001 */
+#define RCC_D3AMR_BDMAAMEN                     RCC_D3AMR_BDMAAMEN_Msk
+#define RCC_D3AMR_LPUART1AMEN_Pos              (3U)
+#define RCC_D3AMR_LPUART1AMEN_Msk              (0x1UL << RCC_D3AMR_LPUART1AMEN_Pos) /*!< 0x00000008 */
+#define RCC_D3AMR_LPUART1AMEN                  RCC_D3AMR_LPUART1AMEN_Msk
+#define RCC_D3AMR_SPI6AMEN_Pos                 (5U)
+#define RCC_D3AMR_SPI6AMEN_Msk                 (0x1UL << RCC_D3AMR_SPI6AMEN_Pos) /*!< 0x00000020 */
+#define RCC_D3AMR_SPI6AMEN                     RCC_D3AMR_SPI6AMEN_Msk
+#define RCC_D3AMR_I2C4AMEN_Pos                 (7U)
+#define RCC_D3AMR_I2C4AMEN_Msk                 (0x1UL << RCC_D3AMR_I2C4AMEN_Pos) /*!< 0x00000080 */
+#define RCC_D3AMR_I2C4AMEN                     RCC_D3AMR_I2C4AMEN_Msk
+#define RCC_D3AMR_LPTIM2AMEN_Pos               (9U)
+#define RCC_D3AMR_LPTIM2AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM2AMEN_Pos) /*!< 0x00000200 */
+#define RCC_D3AMR_LPTIM2AMEN                   RCC_D3AMR_LPTIM2AMEN_Msk
+#define RCC_D3AMR_LPTIM3AMEN_Pos               (10U)
+#define RCC_D3AMR_LPTIM3AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM3AMEN_Pos) /*!< 0x00000400 */
+#define RCC_D3AMR_LPTIM3AMEN                   RCC_D3AMR_LPTIM3AMEN_Msk
+#define RCC_D3AMR_LPTIM4AMEN_Pos               (11U)
+#define RCC_D3AMR_LPTIM4AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM4AMEN_Pos) /*!< 0x00000800 */
+#define RCC_D3AMR_LPTIM4AMEN                   RCC_D3AMR_LPTIM4AMEN_Msk
+#define RCC_D3AMR_LPTIM5AMEN_Pos               (12U)
+#define RCC_D3AMR_LPTIM5AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM5AMEN_Pos) /*!< 0x00001000 */
+#define RCC_D3AMR_LPTIM5AMEN                   RCC_D3AMR_LPTIM5AMEN_Msk
+#define RCC_D3AMR_COMP12AMEN_Pos               (14U)
+#define RCC_D3AMR_COMP12AMEN_Msk               (0x1UL << RCC_D3AMR_COMP12AMEN_Pos) /*!< 0x00004000 */
+#define RCC_D3AMR_COMP12AMEN                   RCC_D3AMR_COMP12AMEN_Msk
+#define RCC_D3AMR_VREFAMEN_Pos                 (15U)
+#define RCC_D3AMR_VREFAMEN_Msk                 (0x1UL << RCC_D3AMR_VREFAMEN_Pos) /*!< 0x00008000 */
+#define RCC_D3AMR_VREFAMEN                     RCC_D3AMR_VREFAMEN_Msk
+#define RCC_D3AMR_RTCAMEN_Pos                  (16U)
+#define RCC_D3AMR_RTCAMEN_Msk                  (0x1UL << RCC_D3AMR_RTCAMEN_Pos) /*!< 0x00010000 */
+#define RCC_D3AMR_RTCAMEN                      RCC_D3AMR_RTCAMEN_Msk
+#define RCC_D3AMR_CRCAMEN_Pos                  (19U)
+#define RCC_D3AMR_CRCAMEN_Msk                  (0x1UL << RCC_D3AMR_CRCAMEN_Pos) /*!< 0x00080000 */
+#define RCC_D3AMR_CRCAMEN                      RCC_D3AMR_CRCAMEN_Msk
+#define RCC_D3AMR_SAI4AMEN_Pos                 (21U)
+#define RCC_D3AMR_SAI4AMEN_Msk                 (0x1UL << RCC_D3AMR_SAI4AMEN_Pos) /*!< 0x00200000 */
+#define RCC_D3AMR_SAI4AMEN                     RCC_D3AMR_SAI4AMEN_Msk
+#define RCC_D3AMR_ADC3AMEN_Pos                 (24U)
+#define RCC_D3AMR_ADC3AMEN_Msk                 (0x1UL << RCC_D3AMR_ADC3AMEN_Pos) /*!< 0x01000000 */
+#define RCC_D3AMR_ADC3AMEN                     RCC_D3AMR_ADC3AMEN_Msk
+
+
+#define RCC_D3AMR_BKPRAMAMEN_Pos               (28U)
+#define RCC_D3AMR_BKPRAMAMEN_Msk               (0x1UL << RCC_D3AMR_BKPRAMAMEN_Pos) /*!< 0x10000000 */
+#define RCC_D3AMR_BKPRAMAMEN                   RCC_D3AMR_BKPRAMAMEN_Msk
+#define RCC_D3AMR_SRAM4AMEN_Pos                (29U)
+#define RCC_D3AMR_SRAM4AMEN_Msk                (0x1UL << RCC_D3AMR_SRAM4AMEN_Pos) /*!< 0x20000000 */
+#define RCC_D3AMR_SRAM4AMEN                    RCC_D3AMR_SRAM4AMEN_Msk
+/********************  Bit definition for RCC_AHB3LPENR register  **************/
+#define RCC_AHB3LPENR_MDMALPEN_Pos             (0U)
+#define RCC_AHB3LPENR_MDMALPEN_Msk             (0x1UL << RCC_AHB3LPENR_MDMALPEN_Pos)         /*!< 0x00000001 */
+#define RCC_AHB3LPENR_MDMALPEN                 RCC_AHB3LPENR_MDMALPEN_Msk
+#define RCC_AHB3LPENR_DMA2DLPEN_Pos            (4U)
+#define RCC_AHB3LPENR_DMA2DLPEN_Msk            (0x1UL << RCC_AHB3LPENR_DMA2DLPEN_Pos)        /*!< 0x00000010 */
+#define RCC_AHB3LPENR_DMA2DLPEN                RCC_AHB3LPENR_DMA2DLPEN_Msk
+#define RCC_AHB3LPENR_JPGDECLPEN_Pos           (5U)
+#define RCC_AHB3LPENR_JPGDECLPEN_Msk           (0x1UL << RCC_AHB3LPENR_JPGDECLPEN_Pos)       /*!< 0x00000020 */
+#define RCC_AHB3LPENR_JPGDECLPEN               RCC_AHB3LPENR_JPGDECLPEN_Msk
+#define RCC_AHB3LPENR_FLASHLPEN_Pos            (8U)
+#define RCC_AHB3LPENR_FLASHLPEN_Msk            (0x1UL << RCC_AHB3LPENR_FLASHLPEN_Pos)        /*!< 0x00000100 */
+#define RCC_AHB3LPENR_FLASHLPEN                RCC_AHB3LPENR_FLASHLPEN_Msk
+#define RCC_AHB3LPENR_FMCLPEN_Pos              (12U)
+#define RCC_AHB3LPENR_FMCLPEN_Msk              (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos)          /*!< 0x00001000 */
+#define RCC_AHB3LPENR_FMCLPEN                  RCC_AHB3LPENR_FMCLPEN_Msk
+#define RCC_AHB3LPENR_QSPILPEN_Pos             (14U)
+#define RCC_AHB3LPENR_QSPILPEN_Msk             (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos)         /*!< 0x00004000 */
+#define RCC_AHB3LPENR_QSPILPEN                 RCC_AHB3LPENR_QSPILPEN_Msk
+#define RCC_AHB3LPENR_SDMMC1LPEN_Pos           (16U)
+#define RCC_AHB3LPENR_SDMMC1LPEN_Msk           (0x1UL << RCC_AHB3LPENR_SDMMC1LPEN_Pos)       /*!< 0x00010000 */
+#define RCC_AHB3LPENR_SDMMC1LPEN               RCC_AHB3LPENR_SDMMC1LPEN_Msk
+#define RCC_AHB3LPENR_DTCM1LPEN_Pos            (28U)
+#define RCC_AHB3LPENR_DTCM1LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM1LPEN_Pos)        /*!< 0x10000000 */
+#define RCC_AHB3LPENR_DTCM1LPEN                RCC_AHB3LPENR_DTCM1LPEN_Msk
+#define RCC_AHB3LPENR_DTCM2LPEN_Pos            (29U)
+#define RCC_AHB3LPENR_DTCM2LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM2LPEN_Pos)        /*!< 0x20000000 */
+#define RCC_AHB3LPENR_DTCM2LPEN                RCC_AHB3LPENR_DTCM2LPEN_Msk
+#define RCC_AHB3LPENR_ITCMLPEN_Pos             (30U)
+#define RCC_AHB3LPENR_ITCMLPEN_Msk             (0x1UL << RCC_AHB3LPENR_ITCMLPEN_Pos)         /*!< 0x40000000 */
+#define RCC_AHB3LPENR_ITCMLPEN                 RCC_AHB3LPENR_ITCMLPEN_Msk
+#define RCC_AHB3LPENR_AXISRAMLPEN_Pos          (31U)
+#define RCC_AHB3LPENR_AXISRAMLPEN_Msk          (0x1UL << RCC_AHB3LPENR_AXISRAMLPEN_Pos)      /*!< 0x80000000 */
+#define RCC_AHB3LPENR_AXISRAMLPEN              RCC_AHB3LPENR_AXISRAMLPEN_Msk
+
+
+/********************  Bit definition for RCC_AHB1LPENR register  ***************/
+#define RCC_AHB1LPENR_DMA1LPEN_Pos             (0U)
+#define RCC_AHB1LPENR_DMA1LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1LPENR_DMA1LPEN                 RCC_AHB1LPENR_DMA1LPEN_Msk
+#define RCC_AHB1LPENR_DMA2LPEN_Pos             (1U)
+#define RCC_AHB1LPENR_DMA2LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1LPENR_DMA2LPEN                 RCC_AHB1LPENR_DMA2LPEN_Msk
+#define RCC_AHB1LPENR_ADC12LPEN_Pos            (5U)
+#define RCC_AHB1LPENR_ADC12LPEN_Msk            (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB1LPENR_ADC12LPEN                RCC_AHB1LPENR_ADC12LPEN_Msk
+#define RCC_AHB1LPENR_ETH1MACLPEN_Pos          (15U)
+#define RCC_AHB1LPENR_ETH1MACLPEN_Msk          (0x1UL << RCC_AHB1LPENR_ETH1MACLPEN_Pos) /*!< 0x00008000 */
+#define RCC_AHB1LPENR_ETH1MACLPEN              RCC_AHB1LPENR_ETH1MACLPEN_Msk
+#define RCC_AHB1LPENR_ETH1TXLPEN_Pos           (16U)
+#define RCC_AHB1LPENR_ETH1TXLPEN_Msk           (0x1UL << RCC_AHB1LPENR_ETH1TXLPEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB1LPENR_ETH1TXLPEN               RCC_AHB1LPENR_ETH1TXLPEN_Msk
+#define RCC_AHB1LPENR_ETH1RXLPEN_Pos           (17U)
+#define RCC_AHB1LPENR_ETH1RXLPEN_Msk           (0x1UL << RCC_AHB1LPENR_ETH1RXLPEN_Pos) /*!< 0x00020000 */
+#define RCC_AHB1LPENR_ETH1RXLPEN               RCC_AHB1LPENR_ETH1RXLPEN_Msk
+#define RCC_AHB1LPENR_USB1OTGHSLPEN_Pos        (25U)
+#define RCC_AHB1LPENR_USB1OTGHSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_USB1OTGHSLPEN_Pos) /*!< 0x02000000 */
+#define RCC_AHB1LPENR_USB1OTGHSLPEN            RCC_AHB1LPENR_USB1OTGHSLPEN_Msk
+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos    (26U)
+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos) /*!< 0x04000000 */
+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN        RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk
+#define RCC_AHB1LPENR_USB2OTGFSLPEN_Pos        (27U)
+#define RCC_AHB1LPENR_USB2OTGFSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_USB2OTGFSLPEN_Pos) /*!< 0x08000000 */
+#define RCC_AHB1LPENR_USB2OTGFSLPEN            RCC_AHB1LPENR_USB2OTGFSLPEN_Msk
+#define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos    (28U)
+#define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos) /*!< 0x10000000 */
+#define RCC_AHB1LPENR_USB2OTGFSULPILPEN        RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk
+
+/* Legacy define */
+#define RCC_AHB1LPENR_USB2OTGHSLPEN_Pos        RCC_AHB1LPENR_USB2OTGFSLPEN_Pos
+#define RCC_AHB1LPENR_USB2OTGHSLPEN_Msk        RCC_AHB1LPENR_USB2OTGFSLPEN_Msk
+#define RCC_AHB1LPENR_USB2OTGHSLPEN            RCC_AHB1LPENR_USB2OTGFSLPEN
+#define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Pos    RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos
+#define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Msk    RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk
+#define RCC_AHB1LPENR_USB2OTGHSULPILPEN        RCC_AHB1LPENR_USB2OTGFSULPILPEN
+
+/********************  Bit definition for RCC_AHB2LPENR register  ***************/
+#define RCC_AHB2LPENR_DCMILPEN_Pos             (0U)
+#define RCC_AHB2LPENR_DCMILPEN_Msk             (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB2LPENR_DCMILPEN                 RCC_AHB2LPENR_DCMILPEN_Msk
+#define RCC_AHB2LPENR_RNGLPEN_Pos              (6U)
+#define RCC_AHB2LPENR_RNGLPEN_Msk              (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB2LPENR_RNGLPEN                  RCC_AHB2LPENR_RNGLPEN_Msk
+#define RCC_AHB2LPENR_SDMMC2LPEN_Pos           (9U)
+#define RCC_AHB2LPENR_SDMMC2LPEN_Msk           (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000200 */
+#define RCC_AHB2LPENR_SDMMC2LPEN               RCC_AHB2LPENR_SDMMC2LPEN_Msk
+#define RCC_AHB2LPENR_SRAM1LPEN_Pos          (29U)
+#define RCC_AHB2LPENR_SRAM1LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM1LPEN_Pos) /*!< 0x20000000 */
+#define RCC_AHB2LPENR_SRAM1LPEN              RCC_AHB2LPENR_SRAM1LPEN_Msk
+#define RCC_AHB2LPENR_SRAM2LPEN_Pos          (30U)
+#define RCC_AHB2LPENR_SRAM2LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM2LPEN_Pos) /*!< 0x40000000 */
+#define RCC_AHB2LPENR_SRAM2LPEN              RCC_AHB2LPENR_SRAM2LPEN_Msk
+#define RCC_AHB2LPENR_SRAM3LPEN_Pos          (31U)
+#define RCC_AHB2LPENR_SRAM3LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM3LPEN_Pos) /*!< 0x80000000 */
+#define RCC_AHB2LPENR_SRAM3LPEN              RCC_AHB2LPENR_SRAM3LPEN_Msk
+
+/* Legacy define */
+#define RCC_AHB2LPENR_D2SRAM1LPEN_Pos          RCC_AHB2LPENR_SRAM1LPEN_Pos
+#define RCC_AHB2LPENR_D2SRAM1LPEN_Msk          RCC_AHB2LPENR_SRAM1LPEN_Msk
+#define RCC_AHB2LPENR_D2SRAM1LPEN              RCC_AHB2LPENR_SRAM1LPEN
+#define RCC_AHB2LPENR_D2SRAM2LPEN_Pos          RCC_AHB2LPENR_SRAM2LPEN_Pos
+#define RCC_AHB2LPENR_D2SRAM2LPEN_Msk          RCC_AHB2LPENR_SRAM2LPEN_Msk
+#define RCC_AHB2LPENR_D2SRAM2LPEN              RCC_AHB2LPENR_SRAM2LPEN
+#define RCC_AHB2LPENR_D2SRAM3LPEN_Pos          RCC_AHB2LPENR_SRAM3LPEN_Pos
+#define RCC_AHB2LPENR_D2SRAM3LPEN_Msk          RCC_AHB2LPENR_SRAM3LPEN_Msk
+#define RCC_AHB2LPENR_D2SRAM3LPEN              RCC_AHB2LPENR_SRAM3LPEN
+
+/********************  Bit definition for RCC_AHB4LPENR register  ******************/
+#define RCC_AHB4LPENR_GPIOALPEN_Pos            (0U)
+#define RCC_AHB4LPENR_GPIOALPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB4LPENR_GPIOALPEN                RCC_AHB4LPENR_GPIOALPEN_Msk
+#define RCC_AHB4LPENR_GPIOBLPEN_Pos            (1U)
+#define RCC_AHB4LPENR_GPIOBLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB4LPENR_GPIOBLPEN                RCC_AHB4LPENR_GPIOBLPEN_Msk
+#define RCC_AHB4LPENR_GPIOCLPEN_Pos            (2U)
+#define RCC_AHB4LPENR_GPIOCLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB4LPENR_GPIOCLPEN                RCC_AHB4LPENR_GPIOCLPEN_Msk
+#define RCC_AHB4LPENR_GPIODLPEN_Pos            (3U)
+#define RCC_AHB4LPENR_GPIODLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB4LPENR_GPIODLPEN                RCC_AHB4LPENR_GPIODLPEN_Msk
+#define RCC_AHB4LPENR_GPIOELPEN_Pos            (4U)
+#define RCC_AHB4LPENR_GPIOELPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB4LPENR_GPIOELPEN                RCC_AHB4LPENR_GPIOELPEN_Msk
+#define RCC_AHB4LPENR_GPIOFLPEN_Pos            (5U)
+#define RCC_AHB4LPENR_GPIOFLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB4LPENR_GPIOFLPEN                RCC_AHB4LPENR_GPIOFLPEN_Msk
+#define RCC_AHB4LPENR_GPIOGLPEN_Pos            (6U)
+#define RCC_AHB4LPENR_GPIOGLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB4LPENR_GPIOGLPEN                RCC_AHB4LPENR_GPIOGLPEN_Msk
+#define RCC_AHB4LPENR_GPIOHLPEN_Pos            (7U)
+#define RCC_AHB4LPENR_GPIOHLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB4LPENR_GPIOHLPEN                RCC_AHB4LPENR_GPIOHLPEN_Msk
+#define RCC_AHB4LPENR_GPIOILPEN_Pos            (8U)
+#define RCC_AHB4LPENR_GPIOILPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB4LPENR_GPIOILPEN                RCC_AHB4LPENR_GPIOILPEN_Msk
+#define RCC_AHB4LPENR_GPIOJLPEN_Pos            (9U)
+#define RCC_AHB4LPENR_GPIOJLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */
+#define RCC_AHB4LPENR_GPIOJLPEN                RCC_AHB4LPENR_GPIOJLPEN_Msk
+#define RCC_AHB4LPENR_GPIOKLPEN_Pos            (10U)
+#define RCC_AHB4LPENR_GPIOKLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */
+#define RCC_AHB4LPENR_GPIOKLPEN                RCC_AHB4LPENR_GPIOKLPEN_Msk
+#define RCC_AHB4LPENR_CRCLPEN_Pos              (19U)
+#define RCC_AHB4LPENR_CRCLPEN_Msk              (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos) /*!< 0x00080000 */
+#define RCC_AHB4LPENR_CRCLPEN                  RCC_AHB4LPENR_CRCLPEN_Msk
+#define RCC_AHB4LPENR_BDMALPEN_Pos             (21U)
+#define RCC_AHB4LPENR_BDMALPEN_Msk             (0x1UL << RCC_AHB4LPENR_BDMALPEN_Pos) /*!< 0x00200000 */
+#define RCC_AHB4LPENR_BDMALPEN                 RCC_AHB4LPENR_BDMALPEN_Msk
+#define RCC_AHB4LPENR_ADC3LPEN_Pos             (24U)
+#define RCC_AHB4LPENR_ADC3LPEN_Msk             (0x1UL << RCC_AHB4LPENR_ADC3LPEN_Pos) /*!< 0x01000000 */
+#define RCC_AHB4LPENR_ADC3LPEN                 RCC_AHB4LPENR_ADC3LPEN_Msk
+#define RCC_AHB4LPENR_BKPRAMLPEN_Pos           (28U)
+#define RCC_AHB4LPENR_BKPRAMLPEN_Msk           (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos) /*!< 0x10000000 */
+#define RCC_AHB4LPENR_BKPRAMLPEN               RCC_AHB4LPENR_BKPRAMLPEN_Msk
+#define RCC_AHB4LPENR_SRAM4LPEN_Pos            (29U)
+#define RCC_AHB4LPENR_SRAM4LPEN_Msk            (0x1UL << RCC_AHB4LPENR_SRAM4LPEN_Pos) /*!< 0x20000000 */
+#define RCC_AHB4LPENR_SRAM4LPEN                RCC_AHB4LPENR_SRAM4LPEN_Msk
+
+/* Legacy define */
+#define RCC_AHB4LPENR_D3SRAM1LPEN_Pos          RCC_AHB4LPENR_SRAM4LPEN_Pos
+#define RCC_AHB4LPENR_D3SRAM1LPEN_Msk          RCC_AHB4LPENR_SRAM4LPEN_Msk
+#define RCC_AHB4LPENR_D3SRAM1LPEN              RCC_AHB4LPENR_SRAM4LPEN
+/********************  Bit definition for RCC_APB3LPENR register  ******************/
+#define RCC_APB3LPENR_LTDCLPEN_Pos             (3U)
+#define RCC_APB3LPENR_LTDCLPEN_Msk             (0x1UL << RCC_APB3LPENR_LTDCLPEN_Pos) /*!< 0x00000008 */
+#define RCC_APB3LPENR_LTDCLPEN                 RCC_APB3LPENR_LTDCLPEN_Msk
+#define RCC_APB3LPENR_WWDG1LPEN_Pos            (6U)
+#define RCC_APB3LPENR_WWDG1LPEN_Msk            (0x1UL << RCC_APB3LPENR_WWDG1LPEN_Pos) /*!< 0x00000040 */
+#define RCC_APB3LPENR_WWDG1LPEN                RCC_APB3LPENR_WWDG1LPEN_Msk
+
+/********************  Bit definition for RCC_APB1LLPENR register  ******************/
+
+#define RCC_APB1LLPENR_TIM2LPEN_Pos            (0U)
+#define RCC_APB1LLPENR_TIM2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1LLPENR_TIM2LPEN                RCC_APB1LLPENR_TIM2LPEN_Msk
+#define RCC_APB1LLPENR_TIM3LPEN_Pos            (1U)
+#define RCC_APB1LLPENR_TIM3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1LLPENR_TIM3LPEN                RCC_APB1LLPENR_TIM3LPEN_Msk
+#define RCC_APB1LLPENR_TIM4LPEN_Pos            (2U)
+#define RCC_APB1LLPENR_TIM4LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1LLPENR_TIM4LPEN                RCC_APB1LLPENR_TIM4LPEN_Msk
+#define RCC_APB1LLPENR_TIM5LPEN_Pos            (3U)
+#define RCC_APB1LLPENR_TIM5LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
+#define RCC_APB1LLPENR_TIM5LPEN                RCC_APB1LLPENR_TIM5LPEN_Msk
+#define RCC_APB1LLPENR_TIM6LPEN_Pos            (4U)
+#define RCC_APB1LLPENR_TIM6LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1LLPENR_TIM6LPEN                RCC_APB1LLPENR_TIM6LPEN_Msk
+#define RCC_APB1LLPENR_TIM7LPEN_Pos            (5U)
+#define RCC_APB1LLPENR_TIM7LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1LLPENR_TIM7LPEN                RCC_APB1LLPENR_TIM7LPEN_Msk
+#define RCC_APB1LLPENR_TIM12LPEN_Pos           (6U)
+#define RCC_APB1LLPENR_TIM12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
+#define RCC_APB1LLPENR_TIM12LPEN               RCC_APB1LLPENR_TIM12LPEN_Msk
+#define RCC_APB1LLPENR_TIM13LPEN_Pos           (7U)
+#define RCC_APB1LLPENR_TIM13LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
+#define RCC_APB1LLPENR_TIM13LPEN               RCC_APB1LLPENR_TIM13LPEN_Msk
+#define RCC_APB1LLPENR_TIM14LPEN_Pos           (8U)
+#define RCC_APB1LLPENR_TIM14LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB1LLPENR_TIM14LPEN               RCC_APB1LLPENR_TIM14LPEN_Msk
+#define RCC_APB1LLPENR_LPTIM1LPEN_Pos          (9U)
+#define RCC_APB1LLPENR_LPTIM1LPEN_Msk          (0x1UL << RCC_APB1LLPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */
+#define RCC_APB1LLPENR_LPTIM1LPEN              RCC_APB1LLPENR_LPTIM1LPEN_Msk
+
+
+#define RCC_APB1LLPENR_SPI2LPEN_Pos            (14U)
+#define RCC_APB1LLPENR_SPI2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB1LLPENR_SPI2LPEN                RCC_APB1LLPENR_SPI2LPEN_Msk
+#define RCC_APB1LLPENR_SPI3LPEN_Pos            (15U)
+#define RCC_APB1LLPENR_SPI3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
+#define RCC_APB1LLPENR_SPI3LPEN                RCC_APB1LLPENR_SPI3LPEN_Msk
+#define RCC_APB1LLPENR_SPDIFRXLPEN_Pos         (16U)
+#define RCC_APB1LLPENR_SPDIFRXLPEN_Msk         (0x1UL << RCC_APB1LLPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */
+#define RCC_APB1LLPENR_SPDIFRXLPEN             RCC_APB1LLPENR_SPDIFRXLPEN_Msk
+#define RCC_APB1LLPENR_USART2LPEN_Pos          (17U)
+#define RCC_APB1LLPENR_USART2LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1LLPENR_USART2LPEN              RCC_APB1LLPENR_USART2LPEN_Msk
+#define RCC_APB1LLPENR_USART3LPEN_Pos          (18U)
+#define RCC_APB1LLPENR_USART3LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1LLPENR_USART3LPEN              RCC_APB1LLPENR_USART3LPEN_Msk
+#define RCC_APB1LLPENR_UART4LPEN_Pos           (19U)
+#define RCC_APB1LLPENR_UART4LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos) /*!< 0x00080000 */
+#define RCC_APB1LLPENR_UART4LPEN               RCC_APB1LLPENR_UART4LPEN_Msk
+#define RCC_APB1LLPENR_UART5LPEN_Pos           (20U)
+#define RCC_APB1LLPENR_UART5LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos) /*!< 0x00100000 */
+#define RCC_APB1LLPENR_UART5LPEN               RCC_APB1LLPENR_UART5LPEN_Msk
+#define RCC_APB1LLPENR_I2C1LPEN_Pos            (21U)
+#define RCC_APB1LLPENR_I2C1LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1LLPENR_I2C1LPEN                RCC_APB1LLPENR_I2C1LPEN_Msk
+#define RCC_APB1LLPENR_I2C2LPEN_Pos            (22U)
+#define RCC_APB1LLPENR_I2C2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_APB1LLPENR_I2C2LPEN                RCC_APB1LLPENR_I2C2LPEN_Msk
+#define RCC_APB1LLPENR_I2C3LPEN_Pos            (23U)
+#define RCC_APB1LLPENR_I2C3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1LLPENR_I2C3LPEN                RCC_APB1LLPENR_I2C3LPEN_Msk
+#define RCC_APB1LLPENR_CECLPEN_Pos             (27U)
+#define RCC_APB1LLPENR_CECLPEN_Msk             (0x1UL << RCC_APB1LLPENR_CECLPEN_Pos) /*!< 0x08000000 */
+#define RCC_APB1LLPENR_CECLPEN                 RCC_APB1LLPENR_CECLPEN_Msk
+#define RCC_APB1LLPENR_DAC12LPEN_Pos           (29U)
+#define RCC_APB1LLPENR_DAC12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_DAC12LPEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1LLPENR_DAC12LPEN               RCC_APB1LLPENR_DAC12LPEN_Msk
+#define RCC_APB1LLPENR_UART7LPEN_Pos           (30U)
+#define RCC_APB1LLPENR_UART7LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART7LPEN_Pos) /*!< 0x40000000 */
+#define RCC_APB1LLPENR_UART7LPEN               RCC_APB1LLPENR_UART7LPEN_Msk
+#define RCC_APB1LLPENR_UART8LPEN_Pos           (31U)
+#define RCC_APB1LLPENR_UART8LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART8LPEN_Pos) /*!< 0x80000000 */
+#define RCC_APB1LLPENR_UART8LPEN               RCC_APB1LLPENR_UART8LPEN_Msk
+
+/* Legacy define */
+#define RCC_APB1LLPENR_HDMICECEN_Pos           RCC_APB1LLPENR_CECLPEN_Pos
+#define RCC_APB1LLPENR_HDMICECEN_Msk           RCC_APB1LLPENR_CECLPEN_Msk
+#define RCC_APB1LLPENR_HDMICECEN               RCC_APB1LLPENR_CECLPEN
+/********************  Bit definition for RCC_APB1HLPENR register  ******************/
+#define RCC_APB1HLPENR_CRSLPEN_Pos             (1U)
+#define RCC_APB1HLPENR_CRSLPEN_Msk             (0x1UL << RCC_APB1HLPENR_CRSLPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1HLPENR_CRSLPEN                 RCC_APB1HLPENR_CRSLPEN_Msk
+#define RCC_APB1HLPENR_SWPMILPEN_Pos           (2U)
+#define RCC_APB1HLPENR_SWPMILPEN_Msk           (0x1UL << RCC_APB1HLPENR_SWPMILPEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1HLPENR_SWPMILPEN               RCC_APB1HLPENR_SWPMILPEN_Msk
+#define RCC_APB1HLPENR_OPAMPLPEN_Pos           (4U)
+#define RCC_APB1HLPENR_OPAMPLPEN_Msk           (0x1UL << RCC_APB1HLPENR_OPAMPLPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1HLPENR_OPAMPLPEN               RCC_APB1HLPENR_OPAMPLPEN_Msk
+#define RCC_APB1HLPENR_MDIOSLPEN_Pos           (5U)
+#define RCC_APB1HLPENR_MDIOSLPEN_Msk           (0x1UL << RCC_APB1HLPENR_MDIOSLPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1HLPENR_MDIOSLPEN               RCC_APB1HLPENR_MDIOSLPEN_Msk
+#define RCC_APB1HLPENR_FDCANLPEN_Pos           (8U)
+#define RCC_APB1HLPENR_FDCANLPEN_Msk           (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB1HLPENR_FDCANLPEN               RCC_APB1HLPENR_FDCANLPEN_Msk
+
+/********************  Bit definition for RCC_APB2LPENR register  ******************/
+#define RCC_APB2LPENR_TIM1LPEN_Pos             (0U)
+#define RCC_APB2LPENR_TIM1LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2LPENR_TIM1LPEN                 RCC_APB2LPENR_TIM1LPEN_Msk
+#define RCC_APB2LPENR_TIM8LPEN_Pos             (1U)
+#define RCC_APB2LPENR_TIM8LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB2LPENR_TIM8LPEN                 RCC_APB2LPENR_TIM8LPEN_Msk
+#define RCC_APB2LPENR_USART1LPEN_Pos           (4U)
+#define RCC_APB2LPENR_USART1LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB2LPENR_USART1LPEN               RCC_APB2LPENR_USART1LPEN_Msk
+#define RCC_APB2LPENR_USART6LPEN_Pos           (5U)
+#define RCC_APB2LPENR_USART6LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2LPENR_USART6LPEN               RCC_APB2LPENR_USART6LPEN_Msk
+#define RCC_APB2LPENR_SPI1LPEN_Pos             (12U)
+#define RCC_APB2LPENR_SPI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2LPENR_SPI1LPEN                 RCC_APB2LPENR_SPI1LPEN_Msk
+#define RCC_APB2LPENR_SPI4LPEN_Pos             (13U)
+#define RCC_APB2LPENR_SPI4LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
+#define RCC_APB2LPENR_SPI4LPEN                 RCC_APB2LPENR_SPI4LPEN_Msk
+#define RCC_APB2LPENR_TIM15LPEN_Pos            (16U)
+#define RCC_APB2LPENR_TIM15LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */
+#define RCC_APB2LPENR_TIM15LPEN                RCC_APB2LPENR_TIM15LPEN_Msk
+#define RCC_APB2LPENR_TIM16LPEN_Pos            (17U)
+#define RCC_APB2LPENR_TIM16LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB2LPENR_TIM16LPEN                RCC_APB2LPENR_TIM16LPEN_Msk
+#define RCC_APB2LPENR_TIM17LPEN_Pos            (18U)
+#define RCC_APB2LPENR_TIM17LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB2LPENR_TIM17LPEN                RCC_APB2LPENR_TIM17LPEN_Msk
+#define RCC_APB2LPENR_SPI5LPEN_Pos             (20U)
+#define RCC_APB2LPENR_SPI5LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
+#define RCC_APB2LPENR_SPI5LPEN                 RCC_APB2LPENR_SPI5LPEN_Msk
+#define RCC_APB2LPENR_SAI1LPEN_Pos             (22U)
+#define RCC_APB2LPENR_SAI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2LPENR_SAI1LPEN                 RCC_APB2LPENR_SAI1LPEN_Msk
+#define RCC_APB2LPENR_SAI2LPEN_Pos             (23U)
+#define RCC_APB2LPENR_SAI2LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */
+#define RCC_APB2LPENR_SAI2LPEN                 RCC_APB2LPENR_SAI2LPEN_Msk
+#define RCC_APB2LPENR_SAI3LPEN_Pos             (24U)
+#define RCC_APB2LPENR_SAI3LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI3LPEN_Pos) /*!< 0x01000000 */
+#define RCC_APB2LPENR_SAI3LPEN                 RCC_APB2LPENR_SAI3LPEN_Msk
+#define RCC_APB2LPENR_DFSDM1LPEN_Pos           (28U)
+#define RCC_APB2LPENR_DFSDM1LPEN_Msk           (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x10000000 */
+#define RCC_APB2LPENR_DFSDM1LPEN               RCC_APB2LPENR_DFSDM1LPEN_Msk
+#define RCC_APB2LPENR_HRTIMLPEN_Pos            (29U)
+#define RCC_APB2LPENR_HRTIMLPEN_Msk            (0x1UL << RCC_APB2LPENR_HRTIMLPEN_Pos) /*!< 0x20000000 */
+#define RCC_APB2LPENR_HRTIMLPEN                RCC_APB2LPENR_HRTIMLPEN_Msk
+
+/********************  Bit definition for RCC_APB4LPENR register  ******************/
+#define RCC_APB4LPENR_SYSCFGLPEN_Pos           (1U)
+#define RCC_APB4LPENR_SYSCFGLPEN_Msk           (0x1UL << RCC_APB4LPENR_SYSCFGLPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB4LPENR_SYSCFGLPEN               RCC_APB4LPENR_SYSCFGLPEN_Msk
+#define RCC_APB4LPENR_LPUART1LPEN_Pos          (3U)
+#define RCC_APB4LPENR_LPUART1LPEN_Msk          (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos) /*!< 0x00000008 */
+#define RCC_APB4LPENR_LPUART1LPEN              RCC_APB4LPENR_LPUART1LPEN_Msk
+#define RCC_APB4LPENR_SPI6LPEN_Pos             (5U)
+#define RCC_APB4LPENR_SPI6LPEN_Msk             (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB4LPENR_SPI6LPEN                 RCC_APB4LPENR_SPI6LPEN_Msk
+#define RCC_APB4LPENR_I2C4LPEN_Pos             (7U)
+#define RCC_APB4LPENR_I2C4LPEN_Msk             (0x1UL << RCC_APB4LPENR_I2C4LPEN_Pos) /*!< 0x00000080 */
+#define RCC_APB4LPENR_I2C4LPEN                 RCC_APB4LPENR_I2C4LPEN_Msk
+#define RCC_APB4LPENR_LPTIM2LPEN_Pos           (9U)
+#define RCC_APB4LPENR_LPTIM2LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos) /*!< 0x00000200 */
+#define RCC_APB4LPENR_LPTIM2LPEN               RCC_APB4LPENR_LPTIM2LPEN_Msk
+#define RCC_APB4LPENR_LPTIM3LPEN_Pos           (10U)
+#define RCC_APB4LPENR_LPTIM3LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos) /*!< 0x00000400 */
+#define RCC_APB4LPENR_LPTIM3LPEN               RCC_APB4LPENR_LPTIM3LPEN_Msk
+#define RCC_APB4LPENR_LPTIM4LPEN_Pos           (11U)
+#define RCC_APB4LPENR_LPTIM4LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM4LPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB4LPENR_LPTIM4LPEN               RCC_APB4LPENR_LPTIM4LPEN_Msk
+#define RCC_APB4LPENR_LPTIM5LPEN_Pos           (12U)
+#define RCC_APB4LPENR_LPTIM5LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM5LPEN_Pos) /*!< 0x00001000 */
+#define RCC_APB4LPENR_LPTIM5LPEN               RCC_APB4LPENR_LPTIM5LPEN_Msk
+#define RCC_APB4LPENR_COMP12LPEN_Pos           (14U)
+#define RCC_APB4LPENR_COMP12LPEN_Msk           (0x1UL << RCC_APB4LPENR_COMP12LPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB4LPENR_COMP12LPEN               RCC_APB4LPENR_COMP12LPEN_Msk
+#define RCC_APB4LPENR_VREFLPEN_Pos             (15U)
+#define RCC_APB4LPENR_VREFLPEN_Msk             (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos) /*!< 0x00008000 */
+#define RCC_APB4LPENR_VREFLPEN                 RCC_APB4LPENR_VREFLPEN_Msk
+#define RCC_APB4LPENR_RTCAPBLPEN_Pos           (16U)
+#define RCC_APB4LPENR_RTCAPBLPEN_Msk           (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos) /*!< 0x00010000 */
+#define RCC_APB4LPENR_RTCAPBLPEN               RCC_APB4LPENR_RTCAPBLPEN_Msk
+#define RCC_APB4LPENR_SAI4LPEN_Pos             (21U)
+#define RCC_APB4LPENR_SAI4LPEN_Msk             (0x1UL << RCC_APB4LPENR_SAI4LPEN_Pos) /*!< 0x00200000 */
+#define RCC_APB4LPENR_SAI4LPEN                 RCC_APB4LPENR_SAI4LPEN_Msk
+
+
+/********************  Bit definition for RCC_RSR register  *******************/
+#define RCC_RSR_RMVF_Pos                       (16U)
+#define RCC_RSR_RMVF_Msk                       (0x1UL << RCC_RSR_RMVF_Pos)     /*!< 0x00010000 */
+#define RCC_RSR_RMVF                           RCC_RSR_RMVF_Msk
+#define RCC_RSR_CPURSTF_Pos                    (17U)
+#define RCC_RSR_CPURSTF_Msk                    (0x1UL << RCC_RSR_CPURSTF_Pos)  /*!< 0x00020000 */
+#define RCC_RSR_CPURSTF                        RCC_RSR_CPURSTF_Msk
+#define RCC_RSR_D1RSTF_Pos                     (19U)
+#define RCC_RSR_D1RSTF_Msk                     (0x1UL << RCC_RSR_D1RSTF_Pos)   /*!< 0x00080000 */
+#define RCC_RSR_D1RSTF                         RCC_RSR_D1RSTF_Msk
+#define RCC_RSR_D2RSTF_Pos                     (20U)
+#define RCC_RSR_D2RSTF_Msk                     (0x1UL << RCC_RSR_D2RSTF_Pos)   /*!< 0x00100000 */
+#define RCC_RSR_D2RSTF                         RCC_RSR_D2RSTF_Msk
+#define RCC_RSR_BORRSTF_Pos                    (21U)
+#define RCC_RSR_BORRSTF_Msk                    (0x1UL << RCC_RSR_BORRSTF_Pos)  /*!< 0x00200000 */
+#define RCC_RSR_BORRSTF                        RCC_RSR_BORRSTF_Msk
+#define RCC_RSR_PINRSTF_Pos                    (22U)
+#define RCC_RSR_PINRSTF_Msk                    (0x1UL << RCC_RSR_PINRSTF_Pos)  /*!< 0x00400000 */
+#define RCC_RSR_PINRSTF                        RCC_RSR_PINRSTF_Msk
+#define RCC_RSR_PORRSTF_Pos                    (23U)
+#define RCC_RSR_PORRSTF_Msk                    (0x1UL << RCC_RSR_PORRSTF_Pos)  /*!< 0x00800000 */
+#define RCC_RSR_PORRSTF                        RCC_RSR_PORRSTF_Msk
+#define RCC_RSR_SFTRSTF_Pos                    (24U)
+#define RCC_RSR_SFTRSTF_Msk                    (0x1UL << RCC_RSR_SFTRSTF_Pos)  /*!< 0x01000000 */
+#define RCC_RSR_SFTRSTF                        RCC_RSR_SFTRSTF_Msk
+#define RCC_RSR_IWDG1RSTF_Pos                  (26U)
+#define RCC_RSR_IWDG1RSTF_Msk                  (0x1UL << RCC_RSR_IWDG1RSTF_Pos) /*!< 0x04000000 */
+#define RCC_RSR_IWDG1RSTF                      RCC_RSR_IWDG1RSTF_Msk
+#define RCC_RSR_WWDG1RSTF_Pos                  (28U)
+#define RCC_RSR_WWDG1RSTF_Msk                  (0x1UL << RCC_RSR_WWDG1RSTF_Pos) /*!< 0x10000000 */
+#define RCC_RSR_WWDG1RSTF                      RCC_RSR_WWDG1RSTF_Msk
+
+#define RCC_RSR_LPWRRSTF_Pos                   (30U)
+#define RCC_RSR_LPWRRSTF_Msk                   (0x1UL << RCC_RSR_LPWRRSTF_Pos) /*!< 0x40000000 */
+#define RCC_RSR_LPWRRSTF                       RCC_RSR_LPWRRSTF_Msk
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    RNG                                     */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RNG_CR register  *******************/
+#define RNG_CR_RNGEN_Pos    (2U)
+#define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                        /*!< 0x00000004 */
+#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk
+#define RNG_CR_IE_Pos       (3U)
+#define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                           /*!< 0x00000008 */
+#define RNG_CR_IE           RNG_CR_IE_Msk
+#define RNG_CR_CED_Pos      (5U)
+#define RNG_CR_CED_Msk      (0x1UL << RNG_CR_CED_Pos)                          /*!< 0x00000020 */
+#define RNG_CR_CED          RNG_CR_CED_Msk
+
+/********************  Bits definition for RNG_SR register  *******************/
+#define RNG_SR_DRDY_Pos     (0U)
+#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                         /*!< 0x00000001 */
+#define RNG_SR_DRDY         RNG_SR_DRDY_Msk
+#define RNG_SR_CECS_Pos     (1U)
+#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                         /*!< 0x00000002 */
+#define RNG_SR_CECS         RNG_SR_CECS_Msk
+#define RNG_SR_SECS_Pos     (2U)
+#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                         /*!< 0x00000004 */
+#define RNG_SR_SECS         RNG_SR_SECS_Msk
+#define RNG_SR_CEIS_Pos     (5U)
+#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                         /*!< 0x00000020 */
+#define RNG_SR_CEIS         RNG_SR_CEIS_Msk
+#define RNG_SR_SEIS_Pos     (6U)
+#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                         /*!< 0x00000040 */
+#define RNG_SR_SEIS         RNG_SR_SEIS_Msk
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RTC_TR register  *******************/
+#define RTC_TR_PM_Pos                  (22U)
+#define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                /*!< 0x00400000 */
+#define RTC_TR_PM                      RTC_TR_PM_Msk
+#define RTC_TR_HT_Pos                  (20U)
+#define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                /*!< 0x00300000 */
+#define RTC_TR_HT                      RTC_TR_HT_Msk
+#define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                 /*!< 0x00100000 */
+#define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                 /*!< 0x00200000 */
+#define RTC_TR_HU_Pos                  (16U)
+#define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                /*!< 0x000F0000 */
+#define RTC_TR_HU                      RTC_TR_HU_Msk
+#define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                 /*!< 0x00010000 */
+#define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                 /*!< 0x00020000 */
+#define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                 /*!< 0x00040000 */
+#define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                 /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos                 (12U)
+#define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)               /*!< 0x00007000 */
+#define RTC_TR_MNT                     RTC_TR_MNT_Msk
+#define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)                /*!< 0x00001000 */
+#define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)                /*!< 0x00002000 */
+#define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)                /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos                 (8U)
+#define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)               /*!< 0x00000F00 */
+#define RTC_TR_MNU                     RTC_TR_MNU_Msk
+#define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)                /*!< 0x00000100 */
+#define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)                /*!< 0x00000200 */
+#define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)                /*!< 0x00000400 */
+#define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)                /*!< 0x00000800 */
+#define RTC_TR_ST_Pos                  (4U)
+#define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                /*!< 0x00000070 */
+#define RTC_TR_ST                      RTC_TR_ST_Msk
+#define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                 /*!< 0x00000010 */
+#define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                 /*!< 0x00000020 */
+#define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                 /*!< 0x00000040 */
+#define RTC_TR_SU_Pos                  (0U)
+#define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                /*!< 0x0000000F */
+#define RTC_TR_SU                      RTC_TR_SU_Msk
+#define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                 /*!< 0x00000001 */
+#define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                 /*!< 0x00000002 */
+#define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                 /*!< 0x00000004 */
+#define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                 /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_DR register  *******************/
+#define RTC_DR_YT_Pos                  (20U)
+#define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                /*!< 0x00F00000 */
+#define RTC_DR_YT                      RTC_DR_YT_Msk
+#define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                 /*!< 0x00100000 */
+#define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                 /*!< 0x00200000 */
+#define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                 /*!< 0x00400000 */
+#define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                 /*!< 0x00800000 */
+#define RTC_DR_YU_Pos                  (16U)
+#define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                /*!< 0x000F0000 */
+#define RTC_DR_YU                      RTC_DR_YU_Msk
+#define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                 /*!< 0x00010000 */
+#define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                 /*!< 0x00020000 */
+#define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                 /*!< 0x00040000 */
+#define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                 /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos                 (13U)
+#define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)               /*!< 0x0000E000 */
+#define RTC_DR_WDU                     RTC_DR_WDU_Msk
+#define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)                /*!< 0x00002000 */
+#define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)                /*!< 0x00004000 */
+#define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)                /*!< 0x00008000 */
+#define RTC_DR_MT_Pos                  (12U)
+#define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                /*!< 0x00001000 */
+#define RTC_DR_MT                      RTC_DR_MT_Msk
+#define RTC_DR_MU_Pos                  (8U)
+#define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                /*!< 0x00000F00 */
+#define RTC_DR_MU                      RTC_DR_MU_Msk
+#define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                 /*!< 0x00000100 */
+#define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                 /*!< 0x00000200 */
+#define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                 /*!< 0x00000400 */
+#define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                 /*!< 0x00000800 */
+#define RTC_DR_DT_Pos                  (4U)
+#define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                /*!< 0x00000030 */
+#define RTC_DR_DT                      RTC_DR_DT_Msk
+#define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                 /*!< 0x00000010 */
+#define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                 /*!< 0x00000020 */
+#define RTC_DR_DU_Pos                  (0U)
+#define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                /*!< 0x0000000F */
+#define RTC_DR_DU                      RTC_DR_DU_Msk
+#define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                 /*!< 0x00000001 */
+#define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                 /*!< 0x00000002 */
+#define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                 /*!< 0x00000004 */
+#define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                 /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_CR register  *******************/
+#define RTC_CR_ITSE_Pos                (24U)
+#define RTC_CR_ITSE_Msk                (0x1UL << RTC_CR_ITSE_Pos)              /*!< 0x01000000 */
+#define RTC_CR_ITSE                    RTC_CR_ITSE_Msk
+#define RTC_CR_COE_Pos                 (23U)
+#define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)               /*!< 0x00800000 */
+#define RTC_CR_COE                     RTC_CR_COE_Msk
+#define RTC_CR_OSEL_Pos                (21U)
+#define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)              /*!< 0x00600000 */
+#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk
+#define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */
+#define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */
+#define RTC_CR_POL_Pos                 (20U)
+#define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)               /*!< 0x00100000 */
+#define RTC_CR_POL                     RTC_CR_POL_Msk
+#define RTC_CR_COSEL_Pos               (19U)
+#define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)             /*!< 0x00080000 */
+#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk
+#define RTC_CR_BKP_Pos                 (18U)
+#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)               /*!< 0x00040000 */
+#define RTC_CR_BKP                     RTC_CR_BKP_Msk
+#define RTC_CR_SUB1H_Pos               (17U)
+#define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)             /*!< 0x00020000 */
+#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk
+#define RTC_CR_ADD1H_Pos               (16U)
+#define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)             /*!< 0x00010000 */
+#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk
+#define RTC_CR_TSIE_Pos                (15U)
+#define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)              /*!< 0x00008000 */
+#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk
+#define RTC_CR_WUTIE_Pos               (14U)
+#define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)             /*!< 0x00004000 */
+#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk
+#define RTC_CR_ALRBIE_Pos              (13U)
+#define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)            /*!< 0x00002000 */
+#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk
+#define RTC_CR_ALRAIE_Pos              (12U)
+#define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)            /*!< 0x00001000 */
+#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk
+#define RTC_CR_TSE_Pos                 (11U)
+#define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)               /*!< 0x00000800 */
+#define RTC_CR_TSE                     RTC_CR_TSE_Msk
+#define RTC_CR_WUTE_Pos                (10U)
+#define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)              /*!< 0x00000400 */
+#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk
+#define RTC_CR_ALRBE_Pos               (9U)
+#define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)             /*!< 0x00000200 */
+#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk
+#define RTC_CR_ALRAE_Pos               (8U)
+#define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)             /*!< 0x00000100 */
+#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk
+#define RTC_CR_FMT_Pos                 (6U)
+#define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)               /*!< 0x00000040 */
+#define RTC_CR_FMT                     RTC_CR_FMT_Msk
+#define RTC_CR_BYPSHAD_Pos             (5U)
+#define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)           /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk
+#define RTC_CR_REFCKON_Pos             (4U)
+#define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)           /*!< 0x00000010 */
+#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk
+#define RTC_CR_TSEDGE_Pos              (3U)
+#define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)            /*!< 0x00000008 */
+#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk
+#define RTC_CR_WUCKSEL_Pos             (0U)
+#define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk
+#define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */
+
+/********************  Bits definition for RTC_ISR register  ******************/
+#define RTC_ISR_ITSF_Pos               (17U)
+#define RTC_ISR_ITSF_Msk               (0x1UL << RTC_ISR_ITSF_Pos)             /*!< 0x00020000 */
+#define RTC_ISR_ITSF                   RTC_ISR_ITSF_Msk
+#define RTC_ISR_RECALPF_Pos            (16U)
+#define RTC_ISR_RECALPF_Msk            (0x1UL << RTC_ISR_RECALPF_Pos)          /*!< 0x00010000 */
+#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk
+#define RTC_ISR_TAMP3F_Pos             (15U)
+#define RTC_ISR_TAMP3F_Msk             (0x1UL << RTC_ISR_TAMP3F_Pos)           /*!< 0x00008000 */
+#define RTC_ISR_TAMP3F                 RTC_ISR_TAMP3F_Msk
+#define RTC_ISR_TAMP2F_Pos             (14U)
+#define RTC_ISR_TAMP2F_Msk             (0x1UL << RTC_ISR_TAMP2F_Pos)           /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk
+#define RTC_ISR_TAMP1F_Pos             (13U)
+#define RTC_ISR_TAMP1F_Msk             (0x1UL << RTC_ISR_TAMP1F_Pos)           /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk
+#define RTC_ISR_TSOVF_Pos              (12U)
+#define RTC_ISR_TSOVF_Msk              (0x1UL << RTC_ISR_TSOVF_Pos)            /*!< 0x00001000 */
+#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk
+#define RTC_ISR_TSF_Pos                (11U)
+#define RTC_ISR_TSF_Msk                (0x1UL << RTC_ISR_TSF_Pos)              /*!< 0x00000800 */
+#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk
+#define RTC_ISR_WUTF_Pos               (10U)
+#define RTC_ISR_WUTF_Msk               (0x1UL << RTC_ISR_WUTF_Pos)             /*!< 0x00000400 */
+#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk
+#define RTC_ISR_ALRBF_Pos              (9U)
+#define RTC_ISR_ALRBF_Msk              (0x1UL << RTC_ISR_ALRBF_Pos)            /*!< 0x00000200 */
+#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk
+#define RTC_ISR_ALRAF_Pos              (8U)
+#define RTC_ISR_ALRAF_Msk              (0x1UL << RTC_ISR_ALRAF_Pos)            /*!< 0x00000100 */
+#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk
+#define RTC_ISR_INIT_Pos               (7U)
+#define RTC_ISR_INIT_Msk               (0x1UL << RTC_ISR_INIT_Pos)             /*!< 0x00000080 */
+#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk
+#define RTC_ISR_INITF_Pos              (6U)
+#define RTC_ISR_INITF_Msk              (0x1UL << RTC_ISR_INITF_Pos)            /*!< 0x00000040 */
+#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk
+#define RTC_ISR_RSF_Pos                (5U)
+#define RTC_ISR_RSF_Msk                (0x1UL << RTC_ISR_RSF_Pos)              /*!< 0x00000020 */
+#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk
+#define RTC_ISR_INITS_Pos              (4U)
+#define RTC_ISR_INITS_Msk              (0x1UL << RTC_ISR_INITS_Pos)            /*!< 0x00000010 */
+#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk
+#define RTC_ISR_SHPF_Pos               (3U)
+#define RTC_ISR_SHPF_Msk               (0x1UL << RTC_ISR_SHPF_Pos)             /*!< 0x00000008 */
+#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk
+#define RTC_ISR_WUTWF_Pos              (2U)
+#define RTC_ISR_WUTWF_Msk              (0x1UL << RTC_ISR_WUTWF_Pos)            /*!< 0x00000004 */
+#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk
+#define RTC_ISR_ALRBWF_Pos             (1U)
+#define RTC_ISR_ALRBWF_Msk             (0x1UL << RTC_ISR_ALRBWF_Pos)           /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk
+#define RTC_ISR_ALRAWF_Pos             (0U)
+#define RTC_ISR_ALRAWF_Msk             (0x1UL << RTC_ISR_ALRAWF_Pos)           /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk
+
+/********************  Bits definition for RTC_PRER register  *****************/
+#define RTC_PRER_PREDIV_A_Pos          (16U)
+#define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)       /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk
+#define RTC_PRER_PREDIV_S_Pos          (0U)
+#define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)     /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk
+
+/********************  Bits definition for RTC_WUTR register  *****************/
+#define RTC_WUTR_WUT_Pos               (0U)
+#define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)          /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk
+
+/********************  Bits definition for RTC_ALRMAR register  ***************/
+#define RTC_ALRMAR_MSK4_Pos            (31U)
+#define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)          /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk
+#define RTC_ALRMAR_WDSEL_Pos           (30U)
+#define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)         /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk
+#define RTC_ALRMAR_DT_Pos              (28U)
+#define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)            /*!< 0x30000000 */
+#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk
+#define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos              (24U)
+#define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)            /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk
+#define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos            (23U)
+#define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)          /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk
+#define RTC_ALRMAR_PM_Pos              (22U)
+#define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)            /*!< 0x00400000 */
+#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk
+#define RTC_ALRMAR_HT_Pos              (20U)
+#define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00300000 */
+#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk
+#define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos              (16U)
+#define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)            /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk
+#define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos            (15U)
+#define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)          /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk
+#define RTC_ALRMAR_MNT_Pos             (12U)
+#define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk
+#define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos             (8U)
+#define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk
+#define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos            (7U)
+#define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)          /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk
+#define RTC_ALRMAR_ST_Pos              (4U)
+#define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000070 */
+#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk
+#define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos              (0U)
+#define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)            /*!< 0x0000000F */
+#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk
+#define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_ALRMBR register  ***************/
+#define RTC_ALRMBR_MSK4_Pos            (31U)
+#define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)          /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk
+#define RTC_ALRMBR_WDSEL_Pos           (30U)
+#define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)         /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk
+#define RTC_ALRMBR_DT_Pos              (28U)
+#define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)            /*!< 0x30000000 */
+#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk
+#define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos              (24U)
+#define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)            /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk
+#define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos            (23U)
+#define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)          /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk
+#define RTC_ALRMBR_PM_Pos              (22U)
+#define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)            /*!< 0x00400000 */
+#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk
+#define RTC_ALRMBR_HT_Pos              (20U)
+#define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00300000 */
+#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk
+#define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos              (16U)
+#define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)            /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk
+#define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos            (15U)
+#define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)          /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk
+#define RTC_ALRMBR_MNT_Pos             (12U)
+#define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk
+#define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos             (8U)
+#define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk
+#define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos            (7U)
+#define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)          /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk
+#define RTC_ALRMBR_ST_Pos              (4U)
+#define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000070 */
+#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk
+#define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos              (0U)
+#define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)            /*!< 0x0000000F */
+#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk
+#define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_WPR register  ******************/
+#define RTC_WPR_KEY_Pos                (0U)
+#define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)             /*!< 0x000000FF */
+#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk
+
+/********************  Bits definition for RTC_SSR register  ******************/
+#define RTC_SSR_SS_Pos                 (0U)
+#define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)            /*!< 0x0000FFFF */
+#define RTC_SSR_SS                     RTC_SSR_SS_Msk
+
+/********************  Bits definition for RTC_SHIFTR register  ***************/
+#define RTC_SHIFTR_SUBFS_Pos           (0U)
+#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)      /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk
+#define RTC_SHIFTR_ADD1S_Pos           (31U)
+#define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)         /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk
+
+/********************  Bits definition for RTC_TSTR register  *****************/
+#define RTC_TSTR_PM_Pos                (22U)
+#define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)              /*!< 0x00400000 */
+#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk
+#define RTC_TSTR_HT_Pos                (20U)
+#define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)              /*!< 0x00300000 */
+#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk
+#define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */
+#define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos                (16U)
+#define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)              /*!< 0x000F0000 */
+#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk
+#define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */
+#define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */
+#define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */
+#define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos               (12U)
+#define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)             /*!< 0x00007000 */
+#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk
+#define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos               (8U)
+#define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)             /*!< 0x00000F00 */
+#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk
+#define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos                (4U)
+#define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)              /*!< 0x00000070 */
+#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk
+#define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */
+#define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */
+#define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos                (0U)
+#define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)              /*!< 0x0000000F */
+#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk
+#define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */
+#define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */
+#define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */
+#define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_TSDR register  *****************/
+#define RTC_TSDR_WDU_Pos               (13U)
+#define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)             /*!< 0x0000E000 */
+#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk
+#define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos                (12U)
+#define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)              /*!< 0x00001000 */
+#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk
+#define RTC_TSDR_MU_Pos                (8U)
+#define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)              /*!< 0x00000F00 */
+#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk
+#define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */
+#define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */
+#define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */
+#define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos                (4U)
+#define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)              /*!< 0x00000030 */
+#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk
+#define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */
+#define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos                (0U)
+#define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)              /*!< 0x0000000F */
+#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk
+#define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */
+#define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */
+#define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */
+#define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_TSSSR register  ****************/
+#define RTC_TSSSR_SS_Pos               (0U)
+#define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)          /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk
+
+/********************  Bits definition for RTC_CALR register  *****************/
+#define RTC_CALR_CALP_Pos              (15U)
+#define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)            /*!< 0x00008000 */
+#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk
+#define RTC_CALR_CALW8_Pos             (14U)
+#define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)           /*!< 0x00004000 */
+#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk
+#define RTC_CALR_CALW16_Pos            (13U)
+#define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)          /*!< 0x00002000 */
+#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk
+#define RTC_CALR_CALM_Pos              (0U)
+#define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)          /*!< 0x000001FF */
+#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk
+#define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */
+#define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */
+#define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */
+#define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */
+#define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */
+#define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */
+#define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */
+#define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */
+#define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */
+
+/********************  Bits definition for RTC_TAMPCR register  ***************/
+#define RTC_TAMPCR_TAMP3MF_Pos         (24U)
+#define RTC_TAMPCR_TAMP3MF_Msk         (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)       /*!< 0x01000000 */
+#define RTC_TAMPCR_TAMP3MF             RTC_TAMPCR_TAMP3MF_Msk
+#define RTC_TAMPCR_TAMP3NOERASE_Pos    (23U)
+#define RTC_TAMPCR_TAMP3NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)  /*!< 0x00800000 */
+#define RTC_TAMPCR_TAMP3NOERASE        RTC_TAMPCR_TAMP3NOERASE_Msk
+#define RTC_TAMPCR_TAMP3IE_Pos         (22U)
+#define RTC_TAMPCR_TAMP3IE_Msk         (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)       /*!< 0x00400000 */
+#define RTC_TAMPCR_TAMP3IE             RTC_TAMPCR_TAMP3IE_Msk
+#define RTC_TAMPCR_TAMP2MF_Pos         (21U)
+#define RTC_TAMPCR_TAMP2MF_Msk         (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)       /*!< 0x00200000 */
+#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk
+#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)
+#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)  /*!< 0x00100000 */
+#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk
+#define RTC_TAMPCR_TAMP2IE_Pos         (19U)
+#define RTC_TAMPCR_TAMP2IE_Msk         (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)       /*!< 0x00080000 */
+#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk
+#define RTC_TAMPCR_TAMP1MF_Pos         (18U)
+#define RTC_TAMPCR_TAMP1MF_Msk         (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)       /*!< 0x00040000 */
+#define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk
+#define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)
+#define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)  /*!< 0x00020000 */
+#define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk
+#define RTC_TAMPCR_TAMP1IE_Pos         (16U)
+#define RTC_TAMPCR_TAMP1IE_Msk         (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)       /*!< 0x00010000 */
+#define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk
+#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)
+#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)     /*!< 0x00008000 */
+#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk
+#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)
+#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)      /*!< 0x00006000 */
+#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk
+#define RTC_TAMPCR_TAMPPRCH_0          (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */
+#define RTC_TAMPCR_TAMPPRCH_1          (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */
+#define RTC_TAMPCR_TAMPFLT_Pos         (11U)
+#define RTC_TAMPCR_TAMPFLT_Msk         (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)       /*!< 0x00001800 */
+#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk
+#define RTC_TAMPCR_TAMPFLT_0           (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */
+#define RTC_TAMPCR_TAMPFLT_1           (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */
+#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)
+#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)      /*!< 0x00000700 */
+#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk
+#define RTC_TAMPCR_TAMPFREQ_0          (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */
+#define RTC_TAMPCR_TAMPFREQ_1          (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */
+#define RTC_TAMPCR_TAMPFREQ_2          (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */
+#define RTC_TAMPCR_TAMPTS_Pos          (7U)
+#define RTC_TAMPCR_TAMPTS_Msk          (0x1UL << RTC_TAMPCR_TAMPTS_Pos)        /*!< 0x00000080 */
+#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk
+#define RTC_TAMPCR_TAMP3TRG_Pos        (6U)
+#define RTC_TAMPCR_TAMP3TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)      /*!< 0x00000040 */
+#define RTC_TAMPCR_TAMP3TRG            RTC_TAMPCR_TAMP3TRG_Msk
+#define RTC_TAMPCR_TAMP3E_Pos          (5U)
+#define RTC_TAMPCR_TAMP3E_Msk          (0x1UL << RTC_TAMPCR_TAMP3E_Pos)        /*!< 0x00000020 */
+#define RTC_TAMPCR_TAMP3E              RTC_TAMPCR_TAMP3E_Msk
+#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)
+#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)      /*!< 0x00000010 */
+#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk
+#define RTC_TAMPCR_TAMP2E_Pos          (3U)
+#define RTC_TAMPCR_TAMP2E_Msk          (0x1UL << RTC_TAMPCR_TAMP2E_Pos)        /*!< 0x00000008 */
+#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk
+#define RTC_TAMPCR_TAMPIE_Pos          (2U)
+#define RTC_TAMPCR_TAMPIE_Msk          (0x1UL << RTC_TAMPCR_TAMPIE_Pos)        /*!< 0x00000004 */
+#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk
+#define RTC_TAMPCR_TAMP1TRG_Pos        (1U)
+#define RTC_TAMPCR_TAMP1TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)      /*!< 0x00000002 */
+#define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk
+#define RTC_TAMPCR_TAMP1E_Pos          (0U)
+#define RTC_TAMPCR_TAMP1E_Msk          (0x1UL << RTC_TAMPCR_TAMP1E_Pos)        /*!< 0x00000001 */
+#define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk
+
+/********************  Bits definition for RTC_ALRMASSR register  *************/
+#define RTC_ALRMASSR_MASKSS_Pos        (24U)
+#define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos            (0U)
+#define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)       /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk
+
+/********************  Bits definition for RTC_ALRMBSSR register  *************/
+#define RTC_ALRMBSSR_MASKSS_Pos        (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos            (0U)
+#define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)       /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk
+
+/********************  Bits definition for RTC_OR register  *******************/
+#define RTC_OR_OUT_RMP_Pos             (1U)
+#define RTC_OR_OUT_RMP_Msk             (0x1UL << RTC_OR_OUT_RMP_Pos)           /*!< 0x00000002 */
+#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk
+#define RTC_OR_ALARMOUTTYPE_Pos        (0U)
+#define RTC_OR_ALARMOUTTYPE_Msk        (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)      /*!< 0x00000001 */
+#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk
+
+/********************  Bits definition for RTC_BKP0R register  ****************/
+#define RTC_BKP0R_Pos                  (0U)
+#define RTC_BKP0R_Msk                  (0xFFFFFFFFUL << RTC_BKP0R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP0R                      RTC_BKP0R_Msk
+
+/********************  Bits definition for RTC_BKP1R register  ****************/
+#define RTC_BKP1R_Pos                  (0U)
+#define RTC_BKP1R_Msk                  (0xFFFFFFFFUL << RTC_BKP1R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP1R                      RTC_BKP1R_Msk
+
+/********************  Bits definition for RTC_BKP2R register  ****************/
+#define RTC_BKP2R_Pos                  (0U)
+#define RTC_BKP2R_Msk                  (0xFFFFFFFFUL << RTC_BKP2R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP2R                      RTC_BKP2R_Msk
+
+/********************  Bits definition for RTC_BKP3R register  ****************/
+#define RTC_BKP3R_Pos                  (0U)
+#define RTC_BKP3R_Msk                  (0xFFFFFFFFUL << RTC_BKP3R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP3R                      RTC_BKP3R_Msk
+
+/********************  Bits definition for RTC_BKP4R register  ****************/
+#define RTC_BKP4R_Pos                  (0U)
+#define RTC_BKP4R_Msk                  (0xFFFFFFFFUL << RTC_BKP4R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP4R                      RTC_BKP4R_Msk
+
+/********************  Bits definition for RTC_BKP5R register  ****************/
+#define RTC_BKP5R_Pos                  (0U)
+#define RTC_BKP5R_Msk                  (0xFFFFFFFFUL << RTC_BKP5R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP5R                      RTC_BKP5R_Msk
+
+/********************  Bits definition for RTC_BKP6R register  ****************/
+#define RTC_BKP6R_Pos                  (0U)
+#define RTC_BKP6R_Msk                  (0xFFFFFFFFUL << RTC_BKP6R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP6R                      RTC_BKP6R_Msk
+
+/********************  Bits definition for RTC_BKP7R register  ****************/
+#define RTC_BKP7R_Pos                  (0U)
+#define RTC_BKP7R_Msk                  (0xFFFFFFFFUL << RTC_BKP7R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP7R                      RTC_BKP7R_Msk
+
+/********************  Bits definition for RTC_BKP8R register  ****************/
+#define RTC_BKP8R_Pos                  (0U)
+#define RTC_BKP8R_Msk                  (0xFFFFFFFFUL << RTC_BKP8R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP8R                      RTC_BKP8R_Msk
+
+/********************  Bits definition for RTC_BKP9R register  ****************/
+#define RTC_BKP9R_Pos                  (0U)
+#define RTC_BKP9R_Msk                  (0xFFFFFFFFUL << RTC_BKP9R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP9R                      RTC_BKP9R_Msk
+
+/********************  Bits definition for RTC_BKP10R register  ***************/
+#define RTC_BKP10R_Pos                 (0U)
+#define RTC_BKP10R_Msk                 (0xFFFFFFFFUL << RTC_BKP10R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP10R                     RTC_BKP10R_Msk
+
+/********************  Bits definition for RTC_BKP11R register  ***************/
+#define RTC_BKP11R_Pos                 (0U)
+#define RTC_BKP11R_Msk                 (0xFFFFFFFFUL << RTC_BKP11R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP11R                     RTC_BKP11R_Msk
+
+/********************  Bits definition for RTC_BKP12R register  ***************/
+#define RTC_BKP12R_Pos                 (0U)
+#define RTC_BKP12R_Msk                 (0xFFFFFFFFUL << RTC_BKP12R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP12R                     RTC_BKP12R_Msk
+
+/********************  Bits definition for RTC_BKP13R register  ***************/
+#define RTC_BKP13R_Pos                 (0U)
+#define RTC_BKP13R_Msk                 (0xFFFFFFFFUL << RTC_BKP13R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP13R                     RTC_BKP13R_Msk
+
+/********************  Bits definition for RTC_BKP14R register  ***************/
+#define RTC_BKP14R_Pos                 (0U)
+#define RTC_BKP14R_Msk                 (0xFFFFFFFFUL << RTC_BKP14R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP14R                     RTC_BKP14R_Msk
+
+/********************  Bits definition for RTC_BKP15R register  ***************/
+#define RTC_BKP15R_Pos                 (0U)
+#define RTC_BKP15R_Msk                 (0xFFFFFFFFUL << RTC_BKP15R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP15R                     RTC_BKP15R_Msk
+
+/********************  Bits definition for RTC_BKP16R register  ***************/
+#define RTC_BKP16R_Pos                 (0U)
+#define RTC_BKP16R_Msk                 (0xFFFFFFFFUL << RTC_BKP16R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP16R                     RTC_BKP16R_Msk
+
+/********************  Bits definition for RTC_BKP17R register  ***************/
+#define RTC_BKP17R_Pos                 (0U)
+#define RTC_BKP17R_Msk                 (0xFFFFFFFFUL << RTC_BKP17R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP17R                     RTC_BKP17R_Msk
+
+/********************  Bits definition for RTC_BKP18R register  ***************/
+#define RTC_BKP18R_Pos                 (0U)
+#define RTC_BKP18R_Msk                 (0xFFFFFFFFUL << RTC_BKP18R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP18R                     RTC_BKP18R_Msk
+
+/********************  Bits definition for RTC_BKP19R register  ***************/
+#define RTC_BKP19R_Pos                 (0U)
+#define RTC_BKP19R_Msk                 (0xFFFFFFFFUL << RTC_BKP19R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP19R                     RTC_BKP19R_Msk
+
+/********************  Bits definition for RTC_BKP20R register  ***************/
+#define RTC_BKP20R_Pos                 (0U)
+#define RTC_BKP20R_Msk                 (0xFFFFFFFFUL << RTC_BKP20R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP20R                     RTC_BKP20R_Msk
+
+/********************  Bits definition for RTC_BKP21R register  ***************/
+#define RTC_BKP21R_Pos                 (0U)
+#define RTC_BKP21R_Msk                 (0xFFFFFFFFUL << RTC_BKP21R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP21R                     RTC_BKP21R_Msk
+
+/********************  Bits definition for RTC_BKP22R register  ***************/
+#define RTC_BKP22R_Pos                 (0U)
+#define RTC_BKP22R_Msk                 (0xFFFFFFFFUL << RTC_BKP22R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP22R                     RTC_BKP22R_Msk
+
+/********************  Bits definition for RTC_BKP23R register  ***************/
+#define RTC_BKP23R_Pos                 (0U)
+#define RTC_BKP23R_Msk                 (0xFFFFFFFFUL << RTC_BKP23R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP23R                     RTC_BKP23R_Msk
+
+/********************  Bits definition for RTC_BKP24R register  ***************/
+#define RTC_BKP24R_Pos                 (0U)
+#define RTC_BKP24R_Msk                 (0xFFFFFFFFUL << RTC_BKP24R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP24R                     RTC_BKP24R_Msk
+
+/********************  Bits definition for RTC_BKP25R register  ***************/
+#define RTC_BKP25R_Pos                 (0U)
+#define RTC_BKP25R_Msk                 (0xFFFFFFFFUL << RTC_BKP25R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP25R                     RTC_BKP25R_Msk
+
+/********************  Bits definition for RTC_BKP26R register  ***************/
+#define RTC_BKP26R_Pos                 (0U)
+#define RTC_BKP26R_Msk                 (0xFFFFFFFFUL << RTC_BKP26R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP26R                     RTC_BKP26R_Msk
+
+/********************  Bits definition for RTC_BKP27R register  ***************/
+#define RTC_BKP27R_Pos                 (0U)
+#define RTC_BKP27R_Msk                 (0xFFFFFFFFUL << RTC_BKP27R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP27R                     RTC_BKP27R_Msk
+
+/********************  Bits definition for RTC_BKP28R register  ***************/
+#define RTC_BKP28R_Pos                 (0U)
+#define RTC_BKP28R_Msk                 (0xFFFFFFFFUL << RTC_BKP28R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP28R                     RTC_BKP28R_Msk
+
+/********************  Bits definition for RTC_BKP29R register  ***************/
+#define RTC_BKP29R_Pos                 (0U)
+#define RTC_BKP29R_Msk                 (0xFFFFFFFFUL << RTC_BKP29R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP29R                     RTC_BKP29R_Msk
+
+/********************  Bits definition for RTC_BKP30R register  ***************/
+#define RTC_BKP30R_Pos                 (0U)
+#define RTC_BKP30R_Msk                 (0xFFFFFFFFUL << RTC_BKP30R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP30R                     RTC_BKP30R_Msk
+
+/********************  Bits definition for RTC_BKP31R register  ***************/
+#define RTC_BKP31R_Pos                 (0U)
+#define RTC_BKP31R_Msk                 (0xFFFFFFFFUL << RTC_BKP31R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP31R                     RTC_BKP31R_Msk
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER_Pos             (5U)
+#define RTC_BKP_NUMBER_Msk             (0x1UL << RTC_BKP_NUMBER_Pos)           /*!< 0x00000020 */
+#define RTC_BKP_NUMBER                 RTC_BKP_NUMBER_Msk
+
+/******************************************************************************/
+/*                                                                            */
+/*                              SPDIF-RX Interface                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for SPDIF_CR register  ******************/
+#define SPDIFRX_CR_SPDIFEN_Pos      (0U)
+#define SPDIFRX_CR_SPDIFEN_Msk      (0x3UL << SPDIFRX_CR_SPDIFEN_Pos)          /*!< 0x00000003 */
+#define SPDIFRX_CR_SPDIFEN          SPDIFRX_CR_SPDIFEN_Msk                     /*!<Peripheral Block Enable                      */
+#define SPDIFRX_CR_RXDMAEN_Pos      (2U)
+#define SPDIFRX_CR_RXDMAEN_Msk      (0x1UL << SPDIFRX_CR_RXDMAEN_Pos)          /*!< 0x00000004 */
+#define SPDIFRX_CR_RXDMAEN          SPDIFRX_CR_RXDMAEN_Msk                     /*!<Receiver DMA Enable for data flow            */
+#define SPDIFRX_CR_RXSTEO_Pos       (3U)
+#define SPDIFRX_CR_RXSTEO_Msk       (0x1UL << SPDIFRX_CR_RXSTEO_Pos)           /*!< 0x00000008 */
+#define SPDIFRX_CR_RXSTEO           SPDIFRX_CR_RXSTEO_Msk                      /*!<Stereo Mode                                  */
+#define SPDIFRX_CR_DRFMT_Pos        (4U)
+#define SPDIFRX_CR_DRFMT_Msk        (0x3UL << SPDIFRX_CR_DRFMT_Pos)            /*!< 0x00000030 */
+#define SPDIFRX_CR_DRFMT            SPDIFRX_CR_DRFMT_Msk                       /*!<RX Data format                               */
+#define SPDIFRX_CR_PMSK_Pos         (6U)
+#define SPDIFRX_CR_PMSK_Msk         (0x1UL << SPDIFRX_CR_PMSK_Pos)             /*!< 0x00000040 */
+#define SPDIFRX_CR_PMSK             SPDIFRX_CR_PMSK_Msk                        /*!<Mask Parity error bit                        */
+#define SPDIFRX_CR_VMSK_Pos         (7U)
+#define SPDIFRX_CR_VMSK_Msk         (0x1UL << SPDIFRX_CR_VMSK_Pos)             /*!< 0x00000080 */
+#define SPDIFRX_CR_VMSK             SPDIFRX_CR_VMSK_Msk                        /*!<Mask of Validity bit                         */
+#define SPDIFRX_CR_CUMSK_Pos        (8U)
+#define SPDIFRX_CR_CUMSK_Msk        (0x1UL << SPDIFRX_CR_CUMSK_Pos)            /*!< 0x00000100 */
+#define SPDIFRX_CR_CUMSK            SPDIFRX_CR_CUMSK_Msk                       /*!<Mask of channel status and user bits         */
+#define SPDIFRX_CR_PTMSK_Pos        (9U)
+#define SPDIFRX_CR_PTMSK_Msk        (0x1UL << SPDIFRX_CR_PTMSK_Pos)            /*!< 0x00000200 */
+#define SPDIFRX_CR_PTMSK            SPDIFRX_CR_PTMSK_Msk                       /*!<Mask of Preamble Type bits                   */
+#define SPDIFRX_CR_CBDMAEN_Pos      (10U)
+#define SPDIFRX_CR_CBDMAEN_Msk      (0x1UL << SPDIFRX_CR_CBDMAEN_Pos)          /*!< 0x00000400 */
+#define SPDIFRX_CR_CBDMAEN          SPDIFRX_CR_CBDMAEN_Msk                     /*!<Control Buffer DMA ENable for control flow   */
+#define SPDIFRX_CR_CHSEL_Pos        (11U)
+#define SPDIFRX_CR_CHSEL_Msk        (0x1UL << SPDIFRX_CR_CHSEL_Pos)            /*!< 0x00000800 */
+#define SPDIFRX_CR_CHSEL            SPDIFRX_CR_CHSEL_Msk                       /*!<Channel Selection                            */
+#define SPDIFRX_CR_NBTR_Pos         (12U)
+#define SPDIFRX_CR_NBTR_Msk         (0x3UL << SPDIFRX_CR_NBTR_Pos)             /*!< 0x00003000 */
+#define SPDIFRX_CR_NBTR             SPDIFRX_CR_NBTR_Msk                        /*!<Maximum allowed re-tries during synchronization phase */
+#define SPDIFRX_CR_WFA_Pos          (14U)
+#define SPDIFRX_CR_WFA_Msk          (0x1UL << SPDIFRX_CR_WFA_Pos)              /*!< 0x00004000 */
+#define SPDIFRX_CR_WFA              SPDIFRX_CR_WFA_Msk                         /*!<Wait For Activity     */
+#define SPDIFRX_CR_INSEL_Pos        (16U)
+#define SPDIFRX_CR_INSEL_Msk        (0x7UL << SPDIFRX_CR_INSEL_Pos)            /*!< 0x00070000 */
+#define SPDIFRX_CR_INSEL            SPDIFRX_CR_INSEL_Msk                       /*!<SPDIF input selection */
+#define SPDIFRX_CR_CKSEN_Pos        (20U)
+#define SPDIFRX_CR_CKSEN_Msk        (0x1UL << SPDIFRX_CR_CKSEN_Pos)            /*!< 0x00100000 */
+#define SPDIFRX_CR_CKSEN            SPDIFRX_CR_CKSEN_Msk                       /*!<Symbol Clock Enable */
+#define SPDIFRX_CR_CKSBKPEN_Pos     (21U)
+#define SPDIFRX_CR_CKSBKPEN_Msk     (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos)         /*!< 0x00200000 */
+#define SPDIFRX_CR_CKSBKPEN         SPDIFRX_CR_CKSBKPEN_Msk                    /*!<Backup Symbol Clock Enable */
+
+/*******************  Bit definition for SPDIFRX_IMR register  *******************/
+#define SPDIFRX_IMR_RXNEIE_Pos      (0U)
+#define SPDIFRX_IMR_RXNEIE_Msk      (0x1UL << SPDIFRX_IMR_RXNEIE_Pos)          /*!< 0x00000001 */
+#define SPDIFRX_IMR_RXNEIE          SPDIFRX_IMR_RXNEIE_Msk                     /*!<RXNE interrupt enable                              */
+#define SPDIFRX_IMR_CSRNEIE_Pos     (1U)
+#define SPDIFRX_IMR_CSRNEIE_Msk     (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos)         /*!< 0x00000002 */
+#define SPDIFRX_IMR_CSRNEIE         SPDIFRX_IMR_CSRNEIE_Msk                    /*!<Control Buffer Ready Interrupt Enable              */
+#define SPDIFRX_IMR_PERRIE_Pos      (2U)
+#define SPDIFRX_IMR_PERRIE_Msk      (0x1UL << SPDIFRX_IMR_PERRIE_Pos)          /*!< 0x00000004 */
+#define SPDIFRX_IMR_PERRIE          SPDIFRX_IMR_PERRIE_Msk                     /*!<Parity error interrupt enable                      */
+#define SPDIFRX_IMR_OVRIE_Pos       (3U)
+#define SPDIFRX_IMR_OVRIE_Msk       (0x1UL << SPDIFRX_IMR_OVRIE_Pos)           /*!< 0x00000008 */
+#define SPDIFRX_IMR_OVRIE           SPDIFRX_IMR_OVRIE_Msk                      /*!<Overrun error Interrupt Enable                     */
+#define SPDIFRX_IMR_SBLKIE_Pos      (4U)
+#define SPDIFRX_IMR_SBLKIE_Msk      (0x1UL << SPDIFRX_IMR_SBLKIE_Pos)          /*!< 0x00000010 */
+#define SPDIFRX_IMR_SBLKIE          SPDIFRX_IMR_SBLKIE_Msk                     /*!<Synchronization Block Detected Interrupt Enable    */
+#define SPDIFRX_IMR_SYNCDIE_Pos     (5U)
+#define SPDIFRX_IMR_SYNCDIE_Msk     (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos)         /*!< 0x00000020 */
+#define SPDIFRX_IMR_SYNCDIE         SPDIFRX_IMR_SYNCDIE_Msk                    /*!<Synchronization Done                               */
+#define SPDIFRX_IMR_IFEIE_Pos       (6U)
+#define SPDIFRX_IMR_IFEIE_Msk       (0x1UL << SPDIFRX_IMR_IFEIE_Pos)           /*!< 0x00000040 */
+#define SPDIFRX_IMR_IFEIE           SPDIFRX_IMR_IFEIE_Msk                      /*!<Serial Interface Error Interrupt Enable            */
+
+/*******************  Bit definition for SPDIFRX_SR register  *******************/
+#define SPDIFRX_SR_RXNE_Pos         (0U)
+#define SPDIFRX_SR_RXNE_Msk         (0x1UL << SPDIFRX_SR_RXNE_Pos)             /*!< 0x00000001 */
+#define SPDIFRX_SR_RXNE             SPDIFRX_SR_RXNE_Msk                        /*!<Read data register not empty                          */
+#define SPDIFRX_SR_CSRNE_Pos        (1U)
+#define SPDIFRX_SR_CSRNE_Msk        (0x1UL << SPDIFRX_SR_CSRNE_Pos)            /*!< 0x00000002 */
+#define SPDIFRX_SR_CSRNE            SPDIFRX_SR_CSRNE_Msk                       /*!<The Control Buffer register is not empty              */
+#define SPDIFRX_SR_PERR_Pos         (2U)
+#define SPDIFRX_SR_PERR_Msk         (0x1UL << SPDIFRX_SR_PERR_Pos)             /*!< 0x00000004 */
+#define SPDIFRX_SR_PERR             SPDIFRX_SR_PERR_Msk                        /*!<Parity error                                          */
+#define SPDIFRX_SR_OVR_Pos          (3U)
+#define SPDIFRX_SR_OVR_Msk          (0x1UL << SPDIFRX_SR_OVR_Pos)              /*!< 0x00000008 */
+#define SPDIFRX_SR_OVR              SPDIFRX_SR_OVR_Msk                         /*!<Overrun error                                         */
+#define SPDIFRX_SR_SBD_Pos          (4U)
+#define SPDIFRX_SR_SBD_Msk          (0x1UL << SPDIFRX_SR_SBD_Pos)              /*!< 0x00000010 */
+#define SPDIFRX_SR_SBD              SPDIFRX_SR_SBD_Msk                         /*!<Synchronization Block Detected                        */
+#define SPDIFRX_SR_SYNCD_Pos        (5U)
+#define SPDIFRX_SR_SYNCD_Msk        (0x1UL << SPDIFRX_SR_SYNCD_Pos)            /*!< 0x00000020 */
+#define SPDIFRX_SR_SYNCD            SPDIFRX_SR_SYNCD_Msk                       /*!<Synchronization Done                                  */
+#define SPDIFRX_SR_FERR_Pos         (6U)
+#define SPDIFRX_SR_FERR_Msk         (0x1UL << SPDIFRX_SR_FERR_Pos)             /*!< 0x00000040 */
+#define SPDIFRX_SR_FERR             SPDIFRX_SR_FERR_Msk                        /*!<Framing error                                         */
+#define SPDIFRX_SR_SERR_Pos         (7U)
+#define SPDIFRX_SR_SERR_Msk         (0x1UL << SPDIFRX_SR_SERR_Pos)             /*!< 0x00000080 */
+#define SPDIFRX_SR_SERR             SPDIFRX_SR_SERR_Msk                        /*!<Synchronization error                                 */
+#define SPDIFRX_SR_TERR_Pos         (8U)
+#define SPDIFRX_SR_TERR_Msk         (0x1UL << SPDIFRX_SR_TERR_Pos)             /*!< 0x00000100 */
+#define SPDIFRX_SR_TERR             SPDIFRX_SR_TERR_Msk                        /*!<Time-out error                                        */
+#define SPDIFRX_SR_WIDTH5_Pos       (16U)
+#define SPDIFRX_SR_WIDTH5_Msk       (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos)        /*!< 0x7FFF0000 */
+#define SPDIFRX_SR_WIDTH5           SPDIFRX_SR_WIDTH5_Msk                      /*!<Duration of 5 symbols counted with spdif_clk          */
+
+/*******************  Bit definition for SPDIFRX_IFCR register  *******************/
+#define SPDIFRX_IFCR_PERRCF_Pos     (2U)
+#define SPDIFRX_IFCR_PERRCF_Msk     (0x1UL << SPDIFRX_IFCR_PERRCF_Pos)         /*!< 0x00000004 */
+#define SPDIFRX_IFCR_PERRCF         SPDIFRX_IFCR_PERRCF_Msk                    /*!<Clears the Parity error flag                         */
+#define SPDIFRX_IFCR_OVRCF_Pos      (3U)
+#define SPDIFRX_IFCR_OVRCF_Msk      (0x1UL << SPDIFRX_IFCR_OVRCF_Pos)          /*!< 0x00000008 */
+#define SPDIFRX_IFCR_OVRCF          SPDIFRX_IFCR_OVRCF_Msk                     /*!<Clears the Overrun error flag                        */
+#define SPDIFRX_IFCR_SBDCF_Pos      (4U)
+#define SPDIFRX_IFCR_SBDCF_Msk      (0x1UL << SPDIFRX_IFCR_SBDCF_Pos)          /*!< 0x00000010 */
+#define SPDIFRX_IFCR_SBDCF          SPDIFRX_IFCR_SBDCF_Msk                     /*!<Clears the Synchronization Block Detected flag       */
+#define SPDIFRX_IFCR_SYNCDCF_Pos    (5U)
+#define SPDIFRX_IFCR_SYNCDCF_Msk    (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos)        /*!< 0x00000020 */
+#define SPDIFRX_IFCR_SYNCDCF        SPDIFRX_IFCR_SYNCDCF_Msk                   /*!<Clears the Synchronization Done flag                 */
+
+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b00 case) *******************/
+#define SPDIFRX_DR0_DR_Pos          (0U)
+#define SPDIFRX_DR0_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos)         /*!< 0x00FFFFFF */
+#define SPDIFRX_DR0_DR              SPDIFRX_DR0_DR_Msk                         /*!<Data value            */
+#define SPDIFRX_DR0_PE_Pos          (24U)
+#define SPDIFRX_DR0_PE_Msk          (0x1UL << SPDIFRX_DR0_PE_Pos)              /*!< 0x01000000 */
+#define SPDIFRX_DR0_PE              SPDIFRX_DR0_PE_Msk                         /*!<Parity Error bit      */
+#define SPDIFRX_DR0_V_Pos           (25U)
+#define SPDIFRX_DR0_V_Msk           (0x1UL << SPDIFRX_DR0_V_Pos)               /*!< 0x02000000 */
+#define SPDIFRX_DR0_V               SPDIFRX_DR0_V_Msk                          /*!<Validity bit          */
+#define SPDIFRX_DR0_U_Pos           (26U)
+#define SPDIFRX_DR0_U_Msk           (0x1UL << SPDIFRX_DR0_U_Pos)               /*!< 0x04000000 */
+#define SPDIFRX_DR0_U               SPDIFRX_DR0_U_Msk                          /*!<User bit              */
+#define SPDIFRX_DR0_C_Pos           (27U)
+#define SPDIFRX_DR0_C_Msk           (0x1UL << SPDIFRX_DR0_C_Pos)               /*!< 0x08000000 */
+#define SPDIFRX_DR0_C               SPDIFRX_DR0_C_Msk                          /*!<Channel Status bit    */
+#define SPDIFRX_DR0_PT_Pos          (28U)
+#define SPDIFRX_DR0_PT_Msk          (0x3UL << SPDIFRX_DR0_PT_Pos)              /*!< 0x30000000 */
+#define SPDIFRX_DR0_PT              SPDIFRX_DR0_PT_Msk                         /*!<Preamble Type         */
+
+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b01 case) *******************/
+#define SPDIFRX_DR1_DR_Pos          (8U)
+#define SPDIFRX_DR1_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos)         /*!< 0xFFFFFF00 */
+#define SPDIFRX_DR1_DR              SPDIFRX_DR1_DR_Msk                         /*!<Data value            */
+#define SPDIFRX_DR1_PT_Pos          (4U)
+#define SPDIFRX_DR1_PT_Msk          (0x3UL << SPDIFRX_DR1_PT_Pos)              /*!< 0x00000030 */
+#define SPDIFRX_DR1_PT              SPDIFRX_DR1_PT_Msk                         /*!<Preamble Type         */
+#define SPDIFRX_DR1_C_Pos           (3U)
+#define SPDIFRX_DR1_C_Msk           (0x1UL << SPDIFRX_DR1_C_Pos)               /*!< 0x00000008 */
+#define SPDIFRX_DR1_C               SPDIFRX_DR1_C_Msk                          /*!<Channel Status bit    */
+#define SPDIFRX_DR1_U_Pos           (2U)
+#define SPDIFRX_DR1_U_Msk           (0x1UL << SPDIFRX_DR1_U_Pos)               /*!< 0x00000004 */
+#define SPDIFRX_DR1_U               SPDIFRX_DR1_U_Msk                          /*!<User bit              */
+#define SPDIFRX_DR1_V_Pos           (1U)
+#define SPDIFRX_DR1_V_Msk           (0x1UL << SPDIFRX_DR1_V_Pos)               /*!< 0x00000002 */
+#define SPDIFRX_DR1_V               SPDIFRX_DR1_V_Msk                          /*!<Validity bit          */
+#define SPDIFRX_DR1_PE_Pos          (0U)
+#define SPDIFRX_DR1_PE_Msk          (0x1UL << SPDIFRX_DR1_PE_Pos)              /*!< 0x00000001 */
+#define SPDIFRX_DR1_PE              SPDIFRX_DR1_PE_Msk                         /*!<Parity Error bit      */
+
+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b10 case) *******************/
+#define SPDIFRX_DR1_DRNL1_Pos       (16U)
+#define SPDIFRX_DR1_DRNL1_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos)        /*!< 0xFFFF0000 */
+#define SPDIFRX_DR1_DRNL1           SPDIFRX_DR1_DRNL1_Msk                      /*!<Data value Channel B      */
+#define SPDIFRX_DR1_DRNL2_Pos       (0U)
+#define SPDIFRX_DR1_DRNL2_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos)        /*!< 0x0000FFFF */
+#define SPDIFRX_DR1_DRNL2           SPDIFRX_DR1_DRNL2_Msk                      /*!<Data value Channel A      */
+
+/*******************  Bit definition for SPDIFRX_CSR register   *******************/
+#define SPDIFRX_CSR_USR_Pos         (0U)
+#define SPDIFRX_CSR_USR_Msk         (0xFFFFUL << SPDIFRX_CSR_USR_Pos)          /*!< 0x0000FFFF */
+#define SPDIFRX_CSR_USR             SPDIFRX_CSR_USR_Msk                        /*!<User data information           */
+#define SPDIFRX_CSR_CS_Pos          (16U)
+#define SPDIFRX_CSR_CS_Msk          (0xFFUL << SPDIFRX_CSR_CS_Pos)             /*!< 0x00FF0000 */
+#define SPDIFRX_CSR_CS              SPDIFRX_CSR_CS_Msk                         /*!<Channel A status information    */
+#define SPDIFRX_CSR_SOB_Pos         (24U)
+#define SPDIFRX_CSR_SOB_Msk         (0x1UL << SPDIFRX_CSR_SOB_Pos)             /*!< 0x01000000 */
+#define SPDIFRX_CSR_SOB             SPDIFRX_CSR_SOB_Msk                        /*!<Start Of Block                  */
+
+/*******************  Bit definition for SPDIFRX_DIR register    *******************/
+#define SPDIFRX_DIR_THI_Pos         (0U)
+#define SPDIFRX_DIR_THI_Msk         (0x1FFFUL << SPDIFRX_DIR_THI_Pos)          /*!< 0x00001FFF */
+#define SPDIFRX_DIR_THI             SPDIFRX_DIR_THI_Msk                        /*!<Threshold LOW      */
+#define SPDIFRX_DIR_TLO_Pos         (16U)
+#define SPDIFRX_DIR_TLO_Msk         (0x1FFFUL << SPDIFRX_DIR_TLO_Pos)          /*!< 0x1FFF0000 */
+#define SPDIFRX_DIR_TLO             SPDIFRX_DIR_TLO_Msk                        /*!<Threshold HIGH     */
+
+/*******************  Bit definition for SPDIFRX_VERR register    *******************/
+#define SPDIFRX_VERR_MINREV_Pos     (0U)
+#define SPDIFRX_VERR_MINREV_Msk     (0xFUL << SPDIFRX_VERR_MINREV_Pos)         /*!< 0x0000000F */
+#define SPDIFRX_VERR_MINREV         SPDIFRX_VERR_MINREV_Msk                    /*!<SPDIFRX Minor revision     */
+#define SPDIFRX_VERR_MAJREV_Pos     (4U)
+#define SPDIFRX_VERR_MAJREV_Msk     (0xFUL << SPDIFRX_VERR_MAJREV_Pos)         /*!< 0x000000F0 */
+#define SPDIFRX_VERR_MAJREV         SPDIFRX_VERR_MAJREV_Msk                    /*!<SPDIFRX Major revision     */
+
+/*******************  Bit definition for SPDIFRX_IDR register    *******************/
+#define SPDIFRX_IDR_ID_Pos          (0U)
+#define SPDIFRX_IDR_ID_Msk          (0xFFFFFFFFUL << SPDIFRX_IDR_ID_Pos)       /*!< 0xFFFFFFFF */
+#define SPDIFRX_IDR_ID              SPDIFRX_IDR_ID_Msk                         /*!<SPDIFRX identifier     */
+
+/*******************  Bit definition for SPDIFRX_SIDR register    *******************/
+#define SPDIFRX_SIDR_SID_Pos        (0U)
+#define SPDIFRX_SIDR_SID_Msk        (0xFFFFFFFFUL << SPDIFRX_SIDR_SID_Pos)     /*!< 0xFFFFFFFF */
+#define SPDIFRX_SIDR_SID            SPDIFRX_SIDR_SID_Msk                       /*!<Size of the memory region allocated to SPDIFRX registers */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Serial Audio Interface                            */
+/*                                                                            */
+/******************************************************************************/
+/*******************************  SAI VERSION  ********************************/
+#define SAI_VER_V2_X
+
+/********************  Bit definition for SAI_GCR register  *******************/
+#define SAI_GCR_SYNCIN_Pos         (0U)
+#define SAI_GCR_SYNCIN_Msk         (0x3UL << SAI_GCR_SYNCIN_Pos)               /*!< 0x00000003 */
+#define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
+#define SAI_GCR_SYNCIN_0           (0x1UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */
+#define SAI_GCR_SYNCIN_1           (0x2UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */
+
+#define SAI_GCR_SYNCOUT_Pos        (4U)
+#define SAI_GCR_SYNCOUT_Msk        (0x3UL << SAI_GCR_SYNCOUT_Pos)              /*!< 0x00000030 */
+#define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define SAI_GCR_SYNCOUT_0          (0x1UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */
+#define SAI_GCR_SYNCOUT_1          (0x2UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */
+
+/*******************  Bit definition for SAI_xCR1 register  *******************/
+#define SAI_xCR1_MODE_Pos          (0U)
+#define SAI_xCR1_MODE_Msk          (0x3UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000003 */
+#define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */
+#define SAI_xCR1_MODE_0            (0x1UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */
+#define SAI_xCR1_MODE_1            (0x2UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */
+
+#define SAI_xCR1_PRTCFG_Pos        (2U)
+#define SAI_xCR1_PRTCFG_Msk        (0x3UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x0000000C */
+#define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
+#define SAI_xCR1_PRTCFG_0          (0x1UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */
+#define SAI_xCR1_PRTCFG_1          (0x2UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */
+
+#define SAI_xCR1_DS_Pos            (5U)
+#define SAI_xCR1_DS_Msk            (0x7UL << SAI_xCR1_DS_Pos)                  /*!< 0x000000E0 */
+#define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */
+#define SAI_xCR1_DS_0              (0x1UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */
+#define SAI_xCR1_DS_1              (0x2UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */
+#define SAI_xCR1_DS_2              (0x4UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */
+
+#define SAI_xCR1_LSBFIRST_Pos      (8U)
+#define SAI_xCR1_LSBFIRST_Msk      (0x1UL << SAI_xCR1_LSBFIRST_Pos)            /*!< 0x00000100 */
+#define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */
+#define SAI_xCR1_CKSTR_Pos         (9U)
+#define SAI_xCR1_CKSTR_Msk         (0x1UL << SAI_xCR1_CKSTR_Pos)               /*!< 0x00000200 */
+#define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */
+
+#define SAI_xCR1_SYNCEN_Pos        (10U)
+#define SAI_xCR1_SYNCEN_Msk        (0x3UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000C00 */
+#define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define SAI_xCR1_SYNCEN_0          (0x1UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */
+#define SAI_xCR1_SYNCEN_1          (0x2UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */
+
+#define SAI_xCR1_MONO_Pos          (12U)
+#define SAI_xCR1_MONO_Msk          (0x1UL << SAI_xCR1_MONO_Pos)                /*!< 0x00001000 */
+#define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */
+#define SAI_xCR1_OUTDRIV_Pos       (13U)
+#define SAI_xCR1_OUTDRIV_Msk       (0x1UL << SAI_xCR1_OUTDRIV_Pos)             /*!< 0x00002000 */
+#define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */
+#define SAI_xCR1_SAIEN_Pos         (16U)
+#define SAI_xCR1_SAIEN_Msk         (0x1UL << SAI_xCR1_SAIEN_Pos)               /*!< 0x00010000 */
+#define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */
+#define SAI_xCR1_DMAEN_Pos         (17U)
+#define SAI_xCR1_DMAEN_Msk         (0x1UL << SAI_xCR1_DMAEN_Pos)               /*!< 0x00020000 */
+#define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */
+#define SAI_xCR1_NODIV_Pos         (19U)
+#define SAI_xCR1_NODIV_Msk         (0x1UL << SAI_xCR1_NODIV_Pos)               /*!< 0x00080000 */
+#define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */
+
+#define SAI_xCR1_MCKDIV_Pos        (20U)
+#define SAI_xCR1_MCKDIV_Msk        (0x3FUL << SAI_xCR1_MCKDIV_Pos)             /*!< 0x03F00000 */
+#define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[5:0] (Master ClocK Divider)  */
+#define SAI_xCR1_MCKDIV_0          (0x01UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00100000 */
+#define SAI_xCR1_MCKDIV_1          (0x02UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00200000 */
+#define SAI_xCR1_MCKDIV_2          (0x04UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00400000 */
+#define SAI_xCR1_MCKDIV_3          (0x08UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00800000 */
+#define SAI_xCR1_MCKDIV_4          (0x10UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x01000000 */
+#define SAI_xCR1_MCKDIV_5          (0x20UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x02000000 */
+
+#define SAI_xCR1_MCKEN_Pos         (27U)
+#define SAI_xCR1_MCKEN_Msk         (0x1UL << SAI_xCR1_MCKEN_Pos)               /*!< 0x08000000 */
+#define SAI_xCR1_MCKEN             SAI_xCR1_MCKEN_Msk                          /*!<Master ClocK enable */
+
+#define SAI_xCR1_OSR_Pos           (26U)
+#define SAI_xCR1_OSR_Msk           (0x1UL << SAI_xCR1_OSR_Pos)                 /*!< 0x04000000 */
+#define SAI_xCR1_OSR               SAI_xCR1_OSR_Msk                            /*!<OverSampling Ratio for master clock  */
+
+/* Legacy define */
+#define  SAI_xCR1_NOMCK               SAI_xCR1_NODIV
+
+/*******************  Bit definition for SAI_xCR2 register  *******************/
+#define SAI_xCR2_FTH_Pos           (0U)
+#define SAI_xCR2_FTH_Msk           (0x7UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000007 */
+#define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */
+#define SAI_xCR2_FTH_0             (0x1UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */
+#define SAI_xCR2_FTH_1             (0x2UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */
+#define SAI_xCR2_FTH_2             (0x4UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */
+
+#define SAI_xCR2_FFLUSH_Pos        (3U)
+#define SAI_xCR2_FFLUSH_Msk        (0x1UL << SAI_xCR2_FFLUSH_Pos)              /*!< 0x00000008 */
+#define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */
+#define SAI_xCR2_TRIS_Pos          (4U)
+#define SAI_xCR2_TRIS_Msk          (0x1UL << SAI_xCR2_TRIS_Pos)                /*!< 0x00000010 */
+#define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */
+#define SAI_xCR2_MUTE_Pos          (5U)
+#define SAI_xCR2_MUTE_Msk          (0x1UL << SAI_xCR2_MUTE_Pos)                /*!< 0x00000020 */
+#define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */
+#define SAI_xCR2_MUTEVAL_Pos       (6U)
+#define SAI_xCR2_MUTEVAL_Msk       (0x1UL << SAI_xCR2_MUTEVAL_Pos)             /*!< 0x00000040 */
+#define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */
+
+#define SAI_xCR2_MUTECNT_Pos       (7U)
+#define SAI_xCR2_MUTECNT_Msk       (0x3FUL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00001F80 */
+#define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */
+#define SAI_xCR2_MUTECNT_0         (0x01UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */
+#define SAI_xCR2_MUTECNT_1         (0x02UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */
+#define SAI_xCR2_MUTECNT_2         (0x04UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */
+#define SAI_xCR2_MUTECNT_3         (0x08UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */
+#define SAI_xCR2_MUTECNT_4         (0x10UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */
+#define SAI_xCR2_MUTECNT_5         (0x20UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */
+
+#define SAI_xCR2_CPL_Pos           (13U)
+#define SAI_xCR2_CPL_Msk           (0x1UL << SAI_xCR2_CPL_Pos)                 /*!< 0x00002000 */
+#define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!< Complement Bit             */
+
+#define SAI_xCR2_COMP_Pos          (14U)
+#define SAI_xCR2_COMP_Msk          (0x3UL << SAI_xCR2_COMP_Pos)                /*!< 0x0000C000 */
+#define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */
+#define SAI_xCR2_COMP_0            (0x1UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */
+#define SAI_xCR2_COMP_1            (0x2UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */
+
+/******************  Bit definition for SAI_xFRCR register  *******************/
+#define SAI_xFRCR_FRL_Pos          (0U)
+#define SAI_xFRCR_FRL_Msk          (0xFFUL << SAI_xFRCR_FRL_Pos)               /*!< 0x000000FF */
+#define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](FRame Length)  */
+#define SAI_xFRCR_FRL_0            (0x01UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */
+#define SAI_xFRCR_FRL_1            (0x02UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */
+#define SAI_xFRCR_FRL_2            (0x04UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */
+#define SAI_xFRCR_FRL_3            (0x08UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */
+#define SAI_xFRCR_FRL_4            (0x10UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */
+#define SAI_xFRCR_FRL_5            (0x20UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */
+#define SAI_xFRCR_FRL_6            (0x40UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */
+#define SAI_xFRCR_FRL_7            (0x80UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */
+
+#define SAI_xFRCR_FSALL_Pos        (8U)
+#define SAI_xFRCR_FSALL_Msk        (0x7FUL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00007F00 */
+#define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FSALL[6:0] (Frame Synchronization Active Level Length)  */
+#define SAI_xFRCR_FSALL_0          (0x01UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */
+#define SAI_xFRCR_FSALL_1          (0x02UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */
+#define SAI_xFRCR_FSALL_2          (0x04UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */
+#define SAI_xFRCR_FSALL_3          (0x08UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */
+#define SAI_xFRCR_FSALL_4          (0x10UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */
+#define SAI_xFRCR_FSALL_5          (0x20UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */
+#define SAI_xFRCR_FSALL_6          (0x40UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */
+
+#define SAI_xFRCR_FSDEF_Pos        (16U)
+#define SAI_xFRCR_FSDEF_Msk        (0x1UL << SAI_xFRCR_FSDEF_Pos)              /*!< 0x00010000 */
+#define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!<Frame Synchronization Definition  */
+#define SAI_xFRCR_FSPOL_Pos        (17U)
+#define SAI_xFRCR_FSPOL_Msk        (0x1UL << SAI_xFRCR_FSPOL_Pos)              /*!< 0x00020000 */
+#define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */
+#define SAI_xFRCR_FSOFF_Pos        (18U)
+#define SAI_xFRCR_FSOFF_Msk        (0x1UL << SAI_xFRCR_FSOFF_Pos)              /*!< 0x00040000 */
+#define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */
+
+/* Legacy define */
+#define  SAI_xFRCR_FSPO                      SAI_xFRCR_FSPOL
+
+/******************  Bit definition for SAI_xSLOTR register  *******************/
+#define SAI_xSLOTR_FBOFF_Pos       (0U)
+#define SAI_xSLOTR_FBOFF_Msk       (0x1FUL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x0000001F */
+#define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FBOFF[4:0](First Bit Offset)  */
+#define SAI_xSLOTR_FBOFF_0         (0x01UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */
+#define SAI_xSLOTR_FBOFF_1         (0x02UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */
+#define SAI_xSLOTR_FBOFF_2         (0x04UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */
+#define SAI_xSLOTR_FBOFF_3         (0x08UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */
+#define SAI_xSLOTR_FBOFF_4         (0x10UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */
+
+#define SAI_xSLOTR_SLOTSZ_Pos      (6U)
+#define SAI_xSLOTR_SLOTSZ_Msk      (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x000000C0 */
+#define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */
+#define SAI_xSLOTR_SLOTSZ_0        (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */
+#define SAI_xSLOTR_SLOTSZ_1        (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */
+
+#define SAI_xSLOTR_NBSLOT_Pos      (8U)
+#define SAI_xSLOTR_NBSLOT_Msk      (0xFUL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000F00 */
+#define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
+#define SAI_xSLOTR_NBSLOT_0        (0x1UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */
+#define SAI_xSLOTR_NBSLOT_1        (0x2UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */
+#define SAI_xSLOTR_NBSLOT_2        (0x4UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */
+#define SAI_xSLOTR_NBSLOT_3        (0x8UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */
+
+#define SAI_xSLOTR_SLOTEN_Pos      (16U)
+#define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)         /*!< 0xFFFF0000 */
+#define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */
+
+/*******************  Bit definition for SAI_xIMR register  *******************/
+#define SAI_xIMR_OVRUDRIE_Pos      (0U)
+#define SAI_xIMR_OVRUDRIE_Msk      (0x1UL << SAI_xIMR_OVRUDRIE_Pos)            /*!< 0x00000001 */
+#define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */
+#define SAI_xIMR_MUTEDETIE_Pos     (1U)
+#define SAI_xIMR_MUTEDETIE_Msk     (0x1UL << SAI_xIMR_MUTEDETIE_Pos)           /*!< 0x00000002 */
+#define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */
+#define SAI_xIMR_WCKCFGIE_Pos      (2U)
+#define SAI_xIMR_WCKCFGIE_Msk      (0x1UL << SAI_xIMR_WCKCFGIE_Pos)            /*!< 0x00000004 */
+#define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */
+#define SAI_xIMR_FREQIE_Pos        (3U)
+#define SAI_xIMR_FREQIE_Msk        (0x1UL << SAI_xIMR_FREQIE_Pos)              /*!< 0x00000008 */
+#define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */
+#define SAI_xIMR_CNRDYIE_Pos       (4U)
+#define SAI_xIMR_CNRDYIE_Msk       (0x1UL << SAI_xIMR_CNRDYIE_Pos)             /*!< 0x00000010 */
+#define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */
+#define SAI_xIMR_AFSDETIE_Pos      (5U)
+#define SAI_xIMR_AFSDETIE_Msk      (0x1UL << SAI_xIMR_AFSDETIE_Pos)            /*!< 0x00000020 */
+#define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */
+#define SAI_xIMR_LFSDETIE_Pos      (6U)
+#define SAI_xIMR_LFSDETIE_Msk      (0x1UL << SAI_xIMR_LFSDETIE_Pos)            /*!< 0x00000040 */
+#define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */
+
+/********************  Bit definition for SAI_xSR register  *******************/
+#define SAI_xSR_OVRUDR_Pos         (0U)
+#define SAI_xSR_OVRUDR_Msk         (0x1UL << SAI_xSR_OVRUDR_Pos)               /*!< 0x00000001 */
+#define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */
+#define SAI_xSR_MUTEDET_Pos        (1U)
+#define SAI_xSR_MUTEDET_Msk        (0x1UL << SAI_xSR_MUTEDET_Pos)              /*!< 0x00000002 */
+#define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */
+#define SAI_xSR_WCKCFG_Pos         (2U)
+#define SAI_xSR_WCKCFG_Msk         (0x1UL << SAI_xSR_WCKCFG_Pos)               /*!< 0x00000004 */
+#define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */
+#define SAI_xSR_FREQ_Pos           (3U)
+#define SAI_xSR_FREQ_Msk           (0x1UL << SAI_xSR_FREQ_Pos)                 /*!< 0x00000008 */
+#define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */
+#define SAI_xSR_CNRDY_Pos          (4U)
+#define SAI_xSR_CNRDY_Msk          (0x1UL << SAI_xSR_CNRDY_Pos)                /*!< 0x00000010 */
+#define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */
+#define SAI_xSR_AFSDET_Pos         (5U)
+#define SAI_xSR_AFSDET_Msk         (0x1UL << SAI_xSR_AFSDET_Pos)               /*!< 0x00000020 */
+#define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */
+#define SAI_xSR_LFSDET_Pos         (6U)
+#define SAI_xSR_LFSDET_Msk         (0x1UL << SAI_xSR_LFSDET_Pos)               /*!< 0x00000040 */
+#define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */
+
+#define SAI_xSR_FLVL_Pos           (16U)
+#define SAI_xSR_FLVL_Msk           (0x7UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00070000 */
+#define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */
+#define SAI_xSR_FLVL_0             (0x1UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */
+#define SAI_xSR_FLVL_1             (0x2UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */
+#define SAI_xSR_FLVL_2             (0x4UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */
+
+/******************  Bit definition for SAI_xCLRFR register  ******************/
+#define SAI_xCLRFR_COVRUDR_Pos     (0U)
+#define SAI_xCLRFR_COVRUDR_Msk     (0x1UL << SAI_xCLRFR_COVRUDR_Pos)           /*!< 0x00000001 */
+#define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */
+#define SAI_xCLRFR_CMUTEDET_Pos    (1U)
+#define SAI_xCLRFR_CMUTEDET_Msk    (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)          /*!< 0x00000002 */
+#define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */
+#define SAI_xCLRFR_CWCKCFG_Pos     (2U)
+#define SAI_xCLRFR_CWCKCFG_Msk     (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)           /*!< 0x00000004 */
+#define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */
+#define SAI_xCLRFR_CFREQ_Pos       (3U)
+#define SAI_xCLRFR_CFREQ_Msk       (0x1UL << SAI_xCLRFR_CFREQ_Pos)             /*!< 0x00000008 */
+#define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */
+#define SAI_xCLRFR_CCNRDY_Pos      (4U)
+#define SAI_xCLRFR_CCNRDY_Msk      (0x1UL << SAI_xCLRFR_CCNRDY_Pos)            /*!< 0x00000010 */
+#define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */
+#define SAI_xCLRFR_CAFSDET_Pos     (5U)
+#define SAI_xCLRFR_CAFSDET_Msk     (0x1UL << SAI_xCLRFR_CAFSDET_Pos)           /*!< 0x00000020 */
+#define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */
+#define SAI_xCLRFR_CLFSDET_Pos     (6U)
+#define SAI_xCLRFR_CLFSDET_Msk     (0x1UL << SAI_xCLRFR_CLFSDET_Pos)           /*!< 0x00000040 */
+#define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */
+
+/******************  Bit definition for SAI_xDR register  *********************/
+#define SAI_xDR_DATA_Pos           (0U)
+#define SAI_xDR_DATA_Msk           (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)          /*!< 0xFFFFFFFF */
+#define SAI_xDR_DATA               SAI_xDR_DATA_Msk
+
+/*******************  Bit definition for SAI_PDMCR register  ******************/
+#define SAI_PDMCR_PDMEN_Pos        (0U)
+#define SAI_PDMCR_PDMEN_Msk        (0x1UL << SAI_PDMCR_PDMEN_Pos)              /*!< 0x00000001 */
+#define SAI_PDMCR_PDMEN            SAI_PDMCR_PDMEN_Msk                         /*!<PDM Enable                                          */
+
+#define SAI_PDMCR_MICNBR_Pos       (4U)
+#define SAI_PDMCR_MICNBR_Msk       (0x3UL << SAI_PDMCR_MICNBR_Pos)             /*!< 0x00000030 */
+#define SAI_PDMCR_MICNBR           SAI_PDMCR_MICNBR_Msk                        /*!<Number of microphones                               */
+#define SAI_PDMCR_MICNBR_0         (0x1UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000010 */
+#define SAI_PDMCR_MICNBR_1         (0x2UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000020 */
+
+#define SAI_PDMCR_CKEN1_Pos        (8U)
+#define SAI_PDMCR_CKEN1_Msk        (0x1UL << SAI_PDMCR_CKEN1_Pos)              /*!< 0x00000100 */
+#define SAI_PDMCR_CKEN1            SAI_PDMCR_CKEN1_Msk                         /*!<Clock enable of bitstream clock number 1            */
+#define SAI_PDMCR_CKEN2_Pos        (9U)
+#define SAI_PDMCR_CKEN2_Msk        (0x1UL << SAI_PDMCR_CKEN2_Pos)              /*!< 0x00000200 */
+#define SAI_PDMCR_CKEN2            SAI_PDMCR_CKEN2_Msk                         /*!<Clock enable of bitstream clock number 2            */
+#define SAI_PDMCR_CKEN3_Pos        (10U)
+#define SAI_PDMCR_CKEN3_Msk        (0x1UL << SAI_PDMCR_CKEN3_Pos)              /*!< 0x00000400 */
+#define SAI_PDMCR_CKEN3            SAI_PDMCR_CKEN3_Msk                         /*!<Clock enable of bitstream clock number 3            */
+#define SAI_PDMCR_CKEN4_Pos        (11U)
+#define SAI_PDMCR_CKEN4_Msk        (0x1UL << SAI_PDMCR_CKEN4_Pos)              /*!< 0x00000800 */
+#define SAI_PDMCR_CKEN4            SAI_PDMCR_CKEN4_Msk                         /*!<Clock enable of bitstream clock number 4            */
+
+/******************  Bit definition for SAI_PDMDLY register  ******************/
+#define SAI_PDMDLY_DLYM1L_Pos      (0U)
+#define SAI_PDMDLY_DLYM1L_Msk      (0x7UL << SAI_PDMDLY_DLYM1L_Pos)            /*!< 0x00000007 */
+#define SAI_PDMDLY_DLYM1L          SAI_PDMDLY_DLYM1L_Msk                       /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */
+#define SAI_PDMDLY_DLYM1L_0        (0x1UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000001 */
+#define SAI_PDMDLY_DLYM1L_1        (0x2UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000002 */
+#define SAI_PDMDLY_DLYM1L_2        (0x4UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000004 */
+
+#define SAI_PDMDLY_DLYM1R_Pos      (4U)
+#define SAI_PDMDLY_DLYM1R_Msk      (0x7UL << SAI_PDMDLY_DLYM1R_Pos)            /*!< 0x00000070 */
+#define SAI_PDMDLY_DLYM1R          SAI_PDMDLY_DLYM1R_Msk                       /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */
+#define SAI_PDMDLY_DLYM1R_0        (0x1UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000010 */
+#define SAI_PDMDLY_DLYM1R_1        (0x2UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000020 */
+#define SAI_PDMDLY_DLYM1R_2        (0x4UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000040 */
+
+#define SAI_PDMDLY_DLYM2L_Pos      (8U)
+#define SAI_PDMDLY_DLYM2L_Msk      (0x7UL << SAI_PDMDLY_DLYM2L_Pos)            /*!< 0x00000700 */
+#define SAI_PDMDLY_DLYM2L          SAI_PDMDLY_DLYM2L_Msk                       /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */
+#define SAI_PDMDLY_DLYM2L_0        (0x1UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000100 */
+#define SAI_PDMDLY_DLYM2L_1        (0x2UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000200 */
+#define SAI_PDMDLY_DLYM2L_2        (0x4UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000400 */
+
+#define SAI_PDMDLY_DLYM2R_Pos      (12U)
+#define SAI_PDMDLY_DLYM2R_Msk      (0x7UL << SAI_PDMDLY_DLYM2R_Pos)            /*!< 0x00007000 */
+#define SAI_PDMDLY_DLYM2R          SAI_PDMDLY_DLYM2R_Msk                       /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2)*/
+#define SAI_PDMDLY_DLYM2R_0        (0x1UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00001000 */
+#define SAI_PDMDLY_DLYM2R_1        (0x2UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00002000 */
+#define SAI_PDMDLY_DLYM2R_2        (0x4UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00004000 */
+
+#define SAI_PDMDLY_DLYM3L_Pos      (16U)
+#define SAI_PDMDLY_DLYM3L_Msk      (0x7UL << SAI_PDMDLY_DLYM3L_Pos)            /*!< 0x00070000 */
+#define SAI_PDMDLY_DLYM3L          SAI_PDMDLY_DLYM3L_Msk                       /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3)*/
+#define SAI_PDMDLY_DLYM3L_0        (0x1UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00010000 */
+#define SAI_PDMDLY_DLYM3L_1        (0x2UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00020000 */
+#define SAI_PDMDLY_DLYM3L_2        (0x4UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00040000 */
+
+#define SAI_PDMDLY_DLYM3R_Pos      (20U)
+#define SAI_PDMDLY_DLYM3R_Msk      (0x7UL << SAI_PDMDLY_DLYM3R_Pos)            /*!< 0x00700000 */
+#define SAI_PDMDLY_DLYM3R          SAI_PDMDLY_DLYM3R_Msk                       /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3)*/
+#define SAI_PDMDLY_DLYM3R_0        (0x1UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00100000 */
+#define SAI_PDMDLY_DLYM3R_1        (0x2UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00200000 */
+#define SAI_PDMDLY_DLYM3R_2        (0x4UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00400000 */
+
+#define SAI_PDMDLY_DLYM4L_Pos      (24U)
+#define SAI_PDMDLY_DLYM4L_Msk      (0x7UL << SAI_PDMDLY_DLYM4L_Pos)            /*!< 0x07000000 */
+#define SAI_PDMDLY_DLYM4L          SAI_PDMDLY_DLYM4L_Msk                       /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4)*/
+#define SAI_PDMDLY_DLYM4L_0        (0x1UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x01000000 */
+#define SAI_PDMDLY_DLYM4L_1        (0x2UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x02000000 */
+#define SAI_PDMDLY_DLYM4L_2        (0x4UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x04000000 */
+
+#define SAI_PDMDLY_DLYM4R_Pos      (28U)
+#define SAI_PDMDLY_DLYM4R_Msk      (0x7UL << SAI_PDMDLY_DLYM4R_Pos)            /*!< 0x70000000 */
+#define SAI_PDMDLY_DLYM4R          SAI_PDMDLY_DLYM4R_Msk                       /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4)*/
+#define SAI_PDMDLY_DLYM4R_0        (0x1UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x10000000 */
+#define SAI_PDMDLY_DLYM4R_1        (0x2UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x20000000 */
+#define SAI_PDMDLY_DLYM4R_2        (0x4UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x40000000 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           SDMMC Interface                                  */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SDMMC_POWER register  ******************/
+#define SDMMC_POWER_PWRCTRL_Pos          (0U)
+#define SDMMC_POWER_PWRCTRL_Msk          (0x3UL << SDMMC_POWER_PWRCTRL_Pos)    /*!< 0x00000003 */
+#define SDMMC_POWER_PWRCTRL              SDMMC_POWER_PWRCTRL_Msk               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDMMC_POWER_PWRCTRL_0            (0x1UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000001 */
+#define SDMMC_POWER_PWRCTRL_1            (0x2UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000002 */
+#define SDMMC_POWER_VSWITCH_Pos          (2U)
+#define SDMMC_POWER_VSWITCH_Msk          (0x1UL << SDMMC_POWER_VSWITCH_Pos)    /*!< 0x00000004 */
+#define SDMMC_POWER_VSWITCH              SDMMC_POWER_VSWITCH_Msk               /*!<Voltage switch sequence start */
+#define SDMMC_POWER_VSWITCHEN_Pos        (3U)
+#define SDMMC_POWER_VSWITCHEN_Msk        (0x1UL << SDMMC_POWER_VSWITCHEN_Pos)  /*!< 0x00000008 */
+#define SDMMC_POWER_VSWITCHEN            SDMMC_POWER_VSWITCHEN_Msk             /*!<Voltage switch procedure enable */
+#define SDMMC_POWER_DIRPOL_Pos           (4U)
+#define SDMMC_POWER_DIRPOL_Msk           (0x1UL << SDMMC_POWER_DIRPOL_Pos)     /*!< 0x00000010 */
+#define SDMMC_POWER_DIRPOL               SDMMC_POWER_DIRPOL_Msk                /*!<Data and Command direction signals polarity selection */
+
+/******************  Bit definition for SDMMC_CLKCR register  ******************/
+#define SDMMC_CLKCR_CLKDIV_Pos           (0U)
+#define SDMMC_CLKCR_CLKDIV_Msk           (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos)   /*!< 0x000003FF */
+#define SDMMC_CLKCR_CLKDIV               SDMMC_CLKCR_CLKDIV_Msk                /*!<Clock divide factor             */
+#define SDMMC_CLKCR_PWRSAV_Pos           (12U)
+#define SDMMC_CLKCR_PWRSAV_Msk           (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)     /*!< 0x00001000 */
+#define SDMMC_CLKCR_PWRSAV               SDMMC_CLKCR_PWRSAV_Msk                /*!<Power saving configuration bit  */
+
+#define SDMMC_CLKCR_WIDBUS_Pos           (14U)
+#define SDMMC_CLKCR_WIDBUS_Msk           (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)     /*!< 0x0000C000 */
+#define SDMMC_CLKCR_WIDBUS               SDMMC_CLKCR_WIDBUS_Msk                /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDMMC_CLKCR_WIDBUS_0             (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00004000 */
+#define SDMMC_CLKCR_WIDBUS_1             (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00008000 */
+
+#define SDMMC_CLKCR_NEGEDGE_Pos          (16U)
+#define SDMMC_CLKCR_NEGEDGE_Msk          (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)    /*!< 0x00010000 */
+#define SDMMC_CLKCR_NEGEDGE              SDMMC_CLKCR_NEGEDGE_Msk               /*!<SDMMC_CK dephasing selection bit */
+#define SDMMC_CLKCR_HWFC_EN_Pos          (17U)
+#define SDMMC_CLKCR_HWFC_EN_Msk          (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)    /*!< 0x00020000 */
+#define SDMMC_CLKCR_HWFC_EN              SDMMC_CLKCR_HWFC_EN_Msk               /*!<HW Flow Control enable           */
+#define SDMMC_CLKCR_DDR_Pos              (18U)
+#define SDMMC_CLKCR_DDR_Msk              (0x1UL << SDMMC_CLKCR_DDR_Pos)        /*!< 0x00040000 */
+#define SDMMC_CLKCR_DDR                  SDMMC_CLKCR_DDR_Msk                   /*!<Data rate signaling selection    */
+#define SDMMC_CLKCR_BUSSPEED_Pos         (19U)
+#define SDMMC_CLKCR_BUSSPEED_Msk         (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos)   /*!< 0x00080000 */
+#define SDMMC_CLKCR_BUSSPEED             SDMMC_CLKCR_BUSSPEED_Msk              /*!<Bus speed mode selection         */
+#define SDMMC_CLKCR_SELCLKRX_Pos         (20U)
+#define SDMMC_CLKCR_SELCLKRX_Msk         (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos)   /*!< 0x00300000 */
+#define SDMMC_CLKCR_SELCLKRX             SDMMC_CLKCR_SELCLKRX_Msk              /*!<SELCLKRX[1:0] bits (Receive clock selection) */
+#define SDMMC_CLKCR_SELCLKRX_0           (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00100000 */
+#define SDMMC_CLKCR_SELCLKRX_1           (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00200000 */
+
+/*******************  Bit definition for SDMMC_ARG register  *******************/
+#define SDMMC_ARG_CMDARG_Pos             (0U)
+#define SDMMC_ARG_CMDARG_Msk             (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_ARG_CMDARG                 SDMMC_ARG_CMDARG_Msk                  /*!<Command argument */
+
+/*******************  Bit definition for SDMMC_CMD register  *******************/
+#define SDMMC_CMD_CMDINDEX_Pos           (0U)
+#define SDMMC_CMD_CMDINDEX_Msk           (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)    /*!< 0x0000003F */
+#define SDMMC_CMD_CMDINDEX               SDMMC_CMD_CMDINDEX_Msk                /*!<Command Index                               */
+#define SDMMC_CMD_CMDTRANS_Pos           (6U)
+#define SDMMC_CMD_CMDTRANS_Msk           (0x1UL << SDMMC_CMD_CMDTRANS_Pos)     /*!< 0x00000040 */
+#define SDMMC_CMD_CMDTRANS               SDMMC_CMD_CMDTRANS_Msk                /*!<CPSM Treats command as a Data Transfer      */
+#define SDMMC_CMD_CMDSTOP_Pos            (7U)
+#define SDMMC_CMD_CMDSTOP_Msk            (0x1UL << SDMMC_CMD_CMDSTOP_Pos)      /*!< 0x00000080 */
+#define SDMMC_CMD_CMDSTOP                SDMMC_CMD_CMDSTOP_Msk                 /*!<CPSM Treats command as a Stop               */
+
+#define SDMMC_CMD_WAITRESP_Pos           (8U)
+#define SDMMC_CMD_WAITRESP_Msk           (0x3UL << SDMMC_CMD_WAITRESP_Pos)     /*!< 0x00000300 */
+#define SDMMC_CMD_WAITRESP               SDMMC_CMD_WAITRESP_Msk                /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDMMC_CMD_WAITRESP_0             (0x1UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000100 */
+#define SDMMC_CMD_WAITRESP_1             (0x2UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000200 */
+
+#define SDMMC_CMD_WAITINT_Pos            (10U)
+#define SDMMC_CMD_WAITINT_Msk            (0x1UL << SDMMC_CMD_WAITINT_Pos)      /*!< 0x00000400 */
+#define SDMMC_CMD_WAITINT                SDMMC_CMD_WAITINT_Msk                 /*!<CPSM Waits for Interrupt Request                               */
+#define SDMMC_CMD_WAITPEND_Pos           (11U)
+#define SDMMC_CMD_WAITPEND_Msk           (0x1UL << SDMMC_CMD_WAITPEND_Pos)     /*!< 0x00000800 */
+#define SDMMC_CMD_WAITPEND               SDMMC_CMD_WAITPEND_Msk                /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDMMC_CMD_CPSMEN_Pos             (12U)
+#define SDMMC_CMD_CPSMEN_Msk             (0x1UL << SDMMC_CMD_CPSMEN_Pos)       /*!< 0x00001000 */
+#define SDMMC_CMD_CPSMEN                 SDMMC_CMD_CPSMEN_Msk                  /*!<Command path state machine (CPSM) Enable bit                   */
+#define SDMMC_CMD_DTHOLD_Pos             (13U)
+#define SDMMC_CMD_DTHOLD_Msk             (0x1UL << SDMMC_CMD_DTHOLD_Pos)       /*!< 0x00002000 */
+#define SDMMC_CMD_DTHOLD                 SDMMC_CMD_DTHOLD_Msk                  /*!<Hold new data block transmission and reception in the DPSM     */
+#define SDMMC_CMD_BOOTMODE_Pos           (14U)
+#define SDMMC_CMD_BOOTMODE_Msk           (0x1UL << SDMMC_CMD_BOOTMODE_Pos)     /*!< 0x00004000 */
+#define SDMMC_CMD_BOOTMODE               SDMMC_CMD_BOOTMODE_Msk                /*!<Boot mode                                                      */
+#define SDMMC_CMD_BOOTEN_Pos             (15U)
+#define SDMMC_CMD_BOOTEN_Msk             (0x1UL << SDMMC_CMD_BOOTEN_Pos)       /*!< 0x00008000 */
+#define SDMMC_CMD_BOOTEN                 SDMMC_CMD_BOOTEN_Msk                  /*!<Enable Boot mode procedure                                     */
+#define SDMMC_CMD_CMDSUSPEND_Pos         (16U)
+#define SDMMC_CMD_CMDSUSPEND_Msk         (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos)   /*!< 0x00010000 */
+#define SDMMC_CMD_CMDSUSPEND             SDMMC_CMD_CMDSUSPEND_Msk              /*!<CPSM Treats command as a Suspend or Resume command             */
+
+/*****************  Bit definition for SDMMC_RESPCMD register  *****************/
+#define SDMMC_RESPCMD_RESPCMD_Pos        (0U)
+#define SDMMC_RESPCMD_RESPCMD_Msk        (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
+#define SDMMC_RESPCMD_RESPCMD            SDMMC_RESPCMD_RESPCMD_Msk             /*!<Response command index */
+
+/******************  Bit definition for SDMMC_RESP0 register  ******************/
+#define SDMMC_RESP0_CARDSTATUS0_Pos      (0U)
+#define SDMMC_RESP0_CARDSTATUS0_Msk      (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP0_CARDSTATUS0          SDMMC_RESP0_CARDSTATUS0_Msk           /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP1 register  ******************/
+#define SDMMC_RESP1_CARDSTATUS1_Pos      (0U)
+#define SDMMC_RESP1_CARDSTATUS1_Msk      (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP1_CARDSTATUS1          SDMMC_RESP1_CARDSTATUS1_Msk           /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP2 register  ******************/
+#define SDMMC_RESP2_CARDSTATUS2_Pos      (0U)
+#define SDMMC_RESP2_CARDSTATUS2_Msk      (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP2_CARDSTATUS2          SDMMC_RESP2_CARDSTATUS2_Msk           /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP3 register  ******************/
+#define SDMMC_RESP3_CARDSTATUS3_Pos      (0U)
+#define SDMMC_RESP3_CARDSTATUS3_Msk      (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP3_CARDSTATUS3          SDMMC_RESP3_CARDSTATUS3_Msk           /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP4 register  ******************/
+#define SDMMC_RESP4_CARDSTATUS4_Pos      (0U)
+#define SDMMC_RESP4_CARDSTATUS4_Msk      (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP4_CARDSTATUS4          SDMMC_RESP4_CARDSTATUS4_Msk           /*!<Card Status */
+
+/******************  Bit definition for SDMMC_DTIMER register  *****************/
+#define SDMMC_DTIMER_DATATIME_Pos        (0U)
+#define SDMMC_DTIMER_DATATIME_Msk        (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_DTIMER_DATATIME            SDMMC_DTIMER_DATATIME_Msk             /*!<Data timeout period. */
+
+/******************  Bit definition for SDMMC_DLEN register  *******************/
+#define SDMMC_DLEN_DATALENGTH_Pos        (0U)
+#define SDMMC_DLEN_DATALENGTH_Msk        (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_DLEN_DATALENGTH            SDMMC_DLEN_DATALENGTH_Msk             /*!<Data length value    */
+
+/******************  Bit definition for SDMMC_DCTRL register  ******************/
+#define SDMMC_DCTRL_DTEN_Pos             (0U)
+#define SDMMC_DCTRL_DTEN_Msk             (0x1UL << SDMMC_DCTRL_DTEN_Pos)       /*!< 0x00000001 */
+#define SDMMC_DCTRL_DTEN                 SDMMC_DCTRL_DTEN_Msk                  /*!<Data transfer enabled bit                */
+#define SDMMC_DCTRL_DTDIR_Pos            (1U)
+#define SDMMC_DCTRL_DTDIR_Msk            (0x1UL << SDMMC_DCTRL_DTDIR_Pos)      /*!< 0x00000002 */
+#define SDMMC_DCTRL_DTDIR                SDMMC_DCTRL_DTDIR_Msk                 /*!<Data transfer direction selection        */
+#define SDMMC_DCTRL_DTMODE_Pos           (2U)
+#define SDMMC_DCTRL_DTMODE_Msk           (0x3UL << SDMMC_DCTRL_DTMODE_Pos)     /*!< 0x0000000C */
+#define SDMMC_DCTRL_DTMODE               SDMMC_DCTRL_DTMODE_Msk                /*!<DTMODE[1:0] Data transfer mode selection */
+#define SDMMC_DCTRL_DTMODE_0             (0x1UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000004 */
+#define SDMMC_DCTRL_DTMODE_1             (0x2UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000008 */
+
+#define SDMMC_DCTRL_DBLOCKSIZE_Pos       (4U)
+#define SDMMC_DCTRL_DBLOCKSIZE_Msk       (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
+#define SDMMC_DCTRL_DBLOCKSIZE           SDMMC_DCTRL_DBLOCKSIZE_Msk            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDMMC_DCTRL_DBLOCKSIZE_0         (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000010 */
+#define SDMMC_DCTRL_DBLOCKSIZE_1         (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000020 */
+#define SDMMC_DCTRL_DBLOCKSIZE_2         (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000040 */
+#define SDMMC_DCTRL_DBLOCKSIZE_3         (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000080 */
+
+#define SDMMC_DCTRL_RWSTART_Pos          (8U)
+#define SDMMC_DCTRL_RWSTART_Msk          (0x1UL << SDMMC_DCTRL_RWSTART_Pos)    /*!< 0x00000100 */
+#define SDMMC_DCTRL_RWSTART              SDMMC_DCTRL_RWSTART_Msk               /*!<Read wait start                                 */
+#define SDMMC_DCTRL_RWSTOP_Pos           (9U)
+#define SDMMC_DCTRL_RWSTOP_Msk           (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)     /*!< 0x00000200 */
+#define SDMMC_DCTRL_RWSTOP               SDMMC_DCTRL_RWSTOP_Msk                /*!<Read wait stop                                  */
+#define SDMMC_DCTRL_RWMOD_Pos            (10U)
+#define SDMMC_DCTRL_RWMOD_Msk            (0x1UL << SDMMC_DCTRL_RWMOD_Pos)      /*!< 0x00000400 */
+#define SDMMC_DCTRL_RWMOD                SDMMC_DCTRL_RWMOD_Msk                 /*!<Read wait mode                                  */
+#define SDMMC_DCTRL_SDIOEN_Pos           (11U)
+#define SDMMC_DCTRL_SDIOEN_Msk           (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)     /*!< 0x00000800 */
+#define SDMMC_DCTRL_SDIOEN               SDMMC_DCTRL_SDIOEN_Msk                /*!<SD I/O enable functions                         */
+#define SDMMC_DCTRL_BOOTACKEN_Pos        (12U)
+#define SDMMC_DCTRL_BOOTACKEN_Msk        (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos)  /*!< 0x00001000 */
+#define SDMMC_DCTRL_BOOTACKEN            SDMMC_DCTRL_BOOTACKEN_Msk             /*!<Enable the reception of the Boot Acknowledgment */
+#define SDMMC_DCTRL_FIFORST_Pos          (13U)
+#define SDMMC_DCTRL_FIFORST_Msk          (0x1UL << SDMMC_DCTRL_FIFORST_Pos)    /*!< 0x00002000 */
+#define SDMMC_DCTRL_FIFORST              SDMMC_DCTRL_FIFORST_Msk               /*!<FIFO reset                                      */
+
+/******************  Bit definition for SDMMC_DCOUNT register  *****************/
+#define SDMMC_DCOUNT_DATACOUNT_Pos       (0U)
+#define SDMMC_DCOUNT_DATACOUNT_Msk       (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_DCOUNT_DATACOUNT           SDMMC_DCOUNT_DATACOUNT_Msk            /*!<Data count value */
+
+/******************  Bit definition for SDMMC_STA register  ********************/
+#define SDMMC_STA_CCRCFAIL_Pos           (0U)
+#define SDMMC_STA_CCRCFAIL_Msk           (0x1UL << SDMMC_STA_CCRCFAIL_Pos)     /*!< 0x00000001 */
+#define SDMMC_STA_CCRCFAIL               SDMMC_STA_CCRCFAIL_Msk                /*!<Command response received (CRC check failed)  */
+#define SDMMC_STA_DCRCFAIL_Pos           (1U)
+#define SDMMC_STA_DCRCFAIL_Msk           (0x1UL << SDMMC_STA_DCRCFAIL_Pos)     /*!< 0x00000002 */
+#define SDMMC_STA_DCRCFAIL               SDMMC_STA_DCRCFAIL_Msk                /*!<Data block sent/received (CRC check failed)   */
+#define SDMMC_STA_CTIMEOUT_Pos           (2U)
+#define SDMMC_STA_CTIMEOUT_Msk           (0x1UL << SDMMC_STA_CTIMEOUT_Pos)     /*!< 0x00000004 */
+#define SDMMC_STA_CTIMEOUT               SDMMC_STA_CTIMEOUT_Msk                /*!<Command response timeout                      */
+#define SDMMC_STA_DTIMEOUT_Pos           (3U)
+#define SDMMC_STA_DTIMEOUT_Msk           (0x1UL << SDMMC_STA_DTIMEOUT_Pos)     /*!< 0x00000008 */
+#define SDMMC_STA_DTIMEOUT               SDMMC_STA_DTIMEOUT_Msk                /*!<Data timeout                                  */
+#define SDMMC_STA_TXUNDERR_Pos           (4U)
+#define SDMMC_STA_TXUNDERR_Msk           (0x1UL << SDMMC_STA_TXUNDERR_Pos)     /*!< 0x00000010 */
+#define SDMMC_STA_TXUNDERR               SDMMC_STA_TXUNDERR_Msk                /*!<Transmit FIFO underrun error                  */
+#define SDMMC_STA_RXOVERR_Pos            (5U)
+#define SDMMC_STA_RXOVERR_Msk            (0x1UL << SDMMC_STA_RXOVERR_Pos)      /*!< 0x00000020 */
+#define SDMMC_STA_RXOVERR                SDMMC_STA_RXOVERR_Msk                 /*!<Received FIFO overrun error                   */
+#define SDMMC_STA_CMDREND_Pos            (6U)
+#define SDMMC_STA_CMDREND_Msk            (0x1UL << SDMMC_STA_CMDREND_Pos)      /*!< 0x00000040 */
+#define SDMMC_STA_CMDREND                SDMMC_STA_CMDREND_Msk                 /*!<Command response received (CRC check passed)  */
+#define SDMMC_STA_CMDSENT_Pos            (7U)
+#define SDMMC_STA_CMDSENT_Msk            (0x1UL << SDMMC_STA_CMDSENT_Pos)      /*!< 0x00000080 */
+#define SDMMC_STA_CMDSENT                SDMMC_STA_CMDSENT_Msk                 /*!<Command sent (no response required)           */
+#define SDMMC_STA_DATAEND_Pos            (8U)
+#define SDMMC_STA_DATAEND_Msk            (0x1UL << SDMMC_STA_DATAEND_Pos)      /*!< 0x00000100 */
+#define SDMMC_STA_DATAEND                SDMMC_STA_DATAEND_Msk                 /*!<Data end (data counter, SDIDCOUNT, is zero)   */
+#define SDMMC_STA_DHOLD_Pos              (9U)
+#define SDMMC_STA_DHOLD_Msk              (0x1UL << SDMMC_STA_DHOLD_Pos)        /*!< 0x00000200 */
+#define SDMMC_STA_DHOLD                  SDMMC_STA_DHOLD_Msk                   /*!<Data transfer Hold                                                      */
+#define SDMMC_STA_DBCKEND_Pos            (10U)
+#define SDMMC_STA_DBCKEND_Msk            (0x1UL << SDMMC_STA_DBCKEND_Pos)      /*!< 0x00000400 */
+#define SDMMC_STA_DBCKEND                SDMMC_STA_DBCKEND_Msk                 /*!<Data block sent/received (CRC check passed)   */
+#define SDMMC_STA_DABORT_Pos             (11U)
+#define SDMMC_STA_DABORT_Msk             (0x1UL << SDMMC_STA_DABORT_Pos)       /*!< 0x00000800 */
+#define SDMMC_STA_DABORT                 SDMMC_STA_DABORT_Msk                  /*!<Data transfer aborted by CMD12                                          */
+#define SDMMC_STA_DPSMACT_Pos            (12U)
+#define SDMMC_STA_DPSMACT_Msk            (0x1UL << SDMMC_STA_DPSMACT_Pos)      /*!< 0x00001000 */
+#define SDMMC_STA_DPSMACT                SDMMC_STA_DPSMACT_Msk                 /*!<Data path state machine active                                       */
+#define SDMMC_STA_CPSMACT_Pos            (13U)
+#define SDMMC_STA_CPSMACT_Msk            (0x1UL << SDMMC_STA_CPSMACT_Pos)      /*!< 0x00002000 */
+#define SDMMC_STA_CPSMACT                SDMMC_STA_CPSMACT_Msk                 /*!<Command path state machine active                                          */
+#define SDMMC_STA_TXFIFOHE_Pos           (14U)
+#define SDMMC_STA_TXFIFOHE_Msk           (0x1UL << SDMMC_STA_TXFIFOHE_Pos)     /*!< 0x00004000 */
+#define SDMMC_STA_TXFIFOHE               SDMMC_STA_TXFIFOHE_Msk                /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDMMC_STA_RXFIFOHF_Pos           (15U)
+#define SDMMC_STA_RXFIFOHF_Msk           (0x1UL << SDMMC_STA_RXFIFOHF_Pos)     /*!< 0x00008000 */
+#define SDMMC_STA_RXFIFOHF               SDMMC_STA_RXFIFOHF_Msk                /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDMMC_STA_TXFIFOF_Pos            (16U)
+#define SDMMC_STA_TXFIFOF_Msk            (0x1UL << SDMMC_STA_TXFIFOF_Pos)      /*!< 0x00010000 */
+#define SDMMC_STA_TXFIFOF                SDMMC_STA_TXFIFOF_Msk                 /*!<Transmit FIFO full                            */
+#define SDMMC_STA_RXFIFOF_Pos            (17U)
+#define SDMMC_STA_RXFIFOF_Msk            (0x1UL << SDMMC_STA_RXFIFOF_Pos)      /*!< 0x00020000 */
+#define SDMMC_STA_RXFIFOF                SDMMC_STA_RXFIFOF_Msk                 /*!<Receive FIFO full                             */
+#define SDMMC_STA_TXFIFOE_Pos            (18U)
+#define SDMMC_STA_TXFIFOE_Msk            (0x1UL << SDMMC_STA_TXFIFOE_Pos)      /*!< 0x00040000 */
+#define SDMMC_STA_TXFIFOE                SDMMC_STA_TXFIFOE_Msk                 /*!<Transmit FIFO empty                           */
+#define SDMMC_STA_RXFIFOE_Pos            (19U)
+#define SDMMC_STA_RXFIFOE_Msk            (0x1UL << SDMMC_STA_RXFIFOE_Pos)      /*!< 0x00080000 */
+#define SDMMC_STA_RXFIFOE                SDMMC_STA_RXFIFOE_Msk                 /*!<Receive FIFO empty                            */
+#define SDMMC_STA_BUSYD0_Pos             (20U)
+#define SDMMC_STA_BUSYD0_Msk             (0x1UL << SDMMC_STA_BUSYD0_Pos)       /*!< 0x00100000 */
+#define SDMMC_STA_BUSYD0                 SDMMC_STA_BUSYD0_Msk                  /*!<Inverted value of SDMMC_D0 line (Busy)                                  */
+#define SDMMC_STA_BUSYD0END_Pos          (21U)
+#define SDMMC_STA_BUSYD0END_Msk          (0x1UL << SDMMC_STA_BUSYD0END_Pos)    /*!< 0x00200000 */
+#define SDMMC_STA_BUSYD0END              SDMMC_STA_BUSYD0END_Msk               /*!<End of SDMMC_D0 Busy following a CMD response detected                  */
+#define SDMMC_STA_SDIOIT_Pos             (22U)
+#define SDMMC_STA_SDIOIT_Msk             (0x1UL << SDMMC_STA_SDIOIT_Pos)       /*!< 0x00400000 */
+#define SDMMC_STA_SDIOIT                 SDMMC_STA_SDIOIT_Msk                  /*!<SDIO interrupt received                                                 */
+#define SDMMC_STA_ACKFAIL_Pos            (23U)
+#define SDMMC_STA_ACKFAIL_Msk            (0x1UL << SDMMC_STA_ACKFAIL_Pos)      /*!< 0x00800000 */
+#define SDMMC_STA_ACKFAIL                SDMMC_STA_ACKFAIL_Msk                 /*!<Boot Acknowledgment received (BootAck check fail)                       */
+#define SDMMC_STA_ACKTIMEOUT_Pos         (24U)
+#define SDMMC_STA_ACKTIMEOUT_Msk         (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos)   /*!< 0x01000000 */
+#define SDMMC_STA_ACKTIMEOUT             SDMMC_STA_ACKTIMEOUT_Msk              /*!<Boot Acknowledgment timeout                                             */
+#define SDMMC_STA_VSWEND_Pos             (25U)
+#define SDMMC_STA_VSWEND_Msk             (0x1UL << SDMMC_STA_VSWEND_Pos)       /*!< 0x02000000 */
+#define SDMMC_STA_VSWEND                 SDMMC_STA_VSWEND_Msk                  /*!<Voltage switch critical timing section completion                       */
+#define SDMMC_STA_CKSTOP_Pos             (26U)
+#define SDMMC_STA_CKSTOP_Msk             (0x1UL << SDMMC_STA_CKSTOP_Pos)       /*!< 0x04000000 */
+#define SDMMC_STA_CKSTOP                 SDMMC_STA_CKSTOP_Msk                  /*!<SDMMC_CK stopped in Voltage switch procedure                            */
+#define SDMMC_STA_IDMATE_Pos             (27U)
+#define SDMMC_STA_IDMATE_Msk             (0x1UL << SDMMC_STA_IDMATE_Pos)       /*!< 0x08000000 */
+#define SDMMC_STA_IDMATE                 SDMMC_STA_IDMATE_Msk                  /*!<IDMA transfer error                                                     */
+#define SDMMC_STA_IDMABTC_Pos            (28U)
+#define SDMMC_STA_IDMABTC_Msk            (0x1UL << SDMMC_STA_IDMABTC_Pos)      /*!< 0x10000000 */
+#define SDMMC_STA_IDMABTC                SDMMC_STA_IDMABTC_Msk                 /*!<IDMA buffer transfer complete                                           */
+
+/*******************  Bit definition for SDMMC_ICR register  *******************/
+#define SDMMC_ICR_CCRCFAILC_Pos          (0U)
+#define SDMMC_ICR_CCRCFAILC_Msk          (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)    /*!< 0x00000001 */
+#define SDMMC_ICR_CCRCFAILC              SDMMC_ICR_CCRCFAILC_Msk               /*!<CCRCFAIL flag clear bit */
+#define SDMMC_ICR_DCRCFAILC_Pos          (1U)
+#define SDMMC_ICR_DCRCFAILC_Msk          (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)    /*!< 0x00000002 */
+#define SDMMC_ICR_DCRCFAILC              SDMMC_ICR_DCRCFAILC_Msk               /*!<DCRCFAIL flag clear bit */
+#define SDMMC_ICR_CTIMEOUTC_Pos          (2U)
+#define SDMMC_ICR_CTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)    /*!< 0x00000004 */
+#define SDMMC_ICR_CTIMEOUTC              SDMMC_ICR_CTIMEOUTC_Msk               /*!<CTIMEOUT flag clear bit */
+#define SDMMC_ICR_DTIMEOUTC_Pos          (3U)
+#define SDMMC_ICR_DTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)    /*!< 0x00000008 */
+#define SDMMC_ICR_DTIMEOUTC              SDMMC_ICR_DTIMEOUTC_Msk               /*!<DTIMEOUT flag clear bit */
+#define SDMMC_ICR_TXUNDERRC_Pos          (4U)
+#define SDMMC_ICR_TXUNDERRC_Msk          (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)    /*!< 0x00000010 */
+#define SDMMC_ICR_TXUNDERRC              SDMMC_ICR_TXUNDERRC_Msk               /*!<TXUNDERR flag clear bit */
+#define SDMMC_ICR_RXOVERRC_Pos           (5U)
+#define SDMMC_ICR_RXOVERRC_Msk           (0x1UL << SDMMC_ICR_RXOVERRC_Pos)     /*!< 0x00000020 */
+#define SDMMC_ICR_RXOVERRC               SDMMC_ICR_RXOVERRC_Msk                /*!<RXOVERR flag clear bit  */
+#define SDMMC_ICR_CMDRENDC_Pos           (6U)
+#define SDMMC_ICR_CMDRENDC_Msk           (0x1UL << SDMMC_ICR_CMDRENDC_Pos)     /*!< 0x00000040 */
+#define SDMMC_ICR_CMDRENDC               SDMMC_ICR_CMDRENDC_Msk                /*!<CMDREND flag clear bit  */
+#define SDMMC_ICR_CMDSENTC_Pos           (7U)
+#define SDMMC_ICR_CMDSENTC_Msk           (0x1UL << SDMMC_ICR_CMDSENTC_Pos)     /*!< 0x00000080 */
+#define SDMMC_ICR_CMDSENTC               SDMMC_ICR_CMDSENTC_Msk                /*!<CMDSENT flag clear bit  */
+#define SDMMC_ICR_DATAENDC_Pos           (8U)
+#define SDMMC_ICR_DATAENDC_Msk           (0x1UL << SDMMC_ICR_DATAENDC_Pos)     /*!< 0x00000100 */
+#define SDMMC_ICR_DATAENDC               SDMMC_ICR_DATAENDC_Msk                /*!<DATAEND flag clear bit  */
+#define SDMMC_ICR_DHOLDC_Pos             (9U)
+#define SDMMC_ICR_DHOLDC_Msk             (0x1UL << SDMMC_ICR_DHOLDC_Pos)       /*!< 0x00000200 */
+#define SDMMC_ICR_DHOLDC                 SDMMC_ICR_DHOLDC_Msk                  /*!<DHOLD flag clear bit       */
+#define SDMMC_ICR_DBCKENDC_Pos           (10U)
+#define SDMMC_ICR_DBCKENDC_Msk           (0x1UL << SDMMC_ICR_DBCKENDC_Pos)     /*!< 0x00000400 */
+#define SDMMC_ICR_DBCKENDC               SDMMC_ICR_DBCKENDC_Msk                /*!<DBCKEND flag clear bit  */
+#define SDMMC_ICR_DABORTC_Pos            (11U)
+#define SDMMC_ICR_DABORTC_Msk            (0x1UL << SDMMC_ICR_DABORTC_Pos)      /*!< 0x00000800 */
+#define SDMMC_ICR_DABORTC                SDMMC_ICR_DABORTC_Msk                 /*!<DABORTC flag clear bit     */
+#define SDMMC_ICR_BUSYD0ENDC_Pos         (21U)
+#define SDMMC_ICR_BUSYD0ENDC_Msk         (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos)   /*!< 0x00200000 */
+#define SDMMC_ICR_BUSYD0ENDC             SDMMC_ICR_BUSYD0ENDC_Msk              /*!<BUSYD0ENDC flag clear bit  */
+#define SDMMC_ICR_SDIOITC_Pos            (22U)
+#define SDMMC_ICR_SDIOITC_Msk            (0x1UL << SDMMC_ICR_SDIOITC_Pos)      /*!< 0x00400000 */
+#define SDMMC_ICR_SDIOITC                SDMMC_ICR_SDIOITC_Msk                 /*!<SDIOIT flag clear bit      */
+#define SDMMC_ICR_ACKFAILC_Pos           (23U)
+#define SDMMC_ICR_ACKFAILC_Msk           (0x1UL << SDMMC_ICR_ACKFAILC_Pos)     /*!< 0x00800000 */
+#define SDMMC_ICR_ACKFAILC               SDMMC_ICR_ACKFAILC_Msk                /*!<ACKFAILC flag clear bit    */
+#define SDMMC_ICR_ACKTIMEOUTC_Pos        (24U)
+#define SDMMC_ICR_ACKTIMEOUTC_Msk        (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos)  /*!< 0x01000000 */
+#define SDMMC_ICR_ACKTIMEOUTC            SDMMC_ICR_ACKTIMEOUTC_Msk             /*!<ACKTIMEOUTC flag clear bit */
+#define SDMMC_ICR_VSWENDC_Pos            (25U)
+#define SDMMC_ICR_VSWENDC_Msk            (0x1UL << SDMMC_ICR_VSWENDC_Pos)      /*!< 0x02000000 */
+#define SDMMC_ICR_VSWENDC                SDMMC_ICR_VSWENDC_Msk                 /*!<VSWENDC flag clear bit     */
+#define SDMMC_ICR_CKSTOPC_Pos            (26U)
+#define SDMMC_ICR_CKSTOPC_Msk            (0x1UL << SDMMC_ICR_CKSTOPC_Pos)      /*!< 0x04000000 */
+#define SDMMC_ICR_CKSTOPC                SDMMC_ICR_CKSTOPC_Msk                 /*!<CKSTOPC flag clear bit     */
+#define SDMMC_ICR_IDMATEC_Pos            (27U)
+#define SDMMC_ICR_IDMATEC_Msk            (0x1UL << SDMMC_ICR_IDMATEC_Pos)      /*!< 0x08000000 */
+#define SDMMC_ICR_IDMATEC                SDMMC_ICR_IDMATEC_Msk                 /*!<IDMATEC flag clear bit     */
+#define SDMMC_ICR_IDMABTCC_Pos           (28U)
+#define SDMMC_ICR_IDMABTCC_Msk           (0x1UL << SDMMC_ICR_IDMABTCC_Pos)     /*!< 0x10000000 */
+#define SDMMC_ICR_IDMABTCC               SDMMC_ICR_IDMABTCC_Msk                /*!<IDMABTCC flag clear bit    */
+
+/******************  Bit definition for SDMMC_MASK register  *******************/
+#define SDMMC_MASK_CCRCFAILIE_Pos        (0U)
+#define SDMMC_MASK_CCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)  /*!< 0x00000001 */
+#define SDMMC_MASK_CCRCFAILIE            SDMMC_MASK_CCRCFAILIE_Msk             /*!<Command CRC Fail Interrupt Enable          */
+#define SDMMC_MASK_DCRCFAILIE_Pos        (1U)
+#define SDMMC_MASK_DCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)  /*!< 0x00000002 */
+#define SDMMC_MASK_DCRCFAILIE            SDMMC_MASK_DCRCFAILIE_Msk             /*!<Data CRC Fail Interrupt Enable             */
+#define SDMMC_MASK_CTIMEOUTIE_Pos        (2U)
+#define SDMMC_MASK_CTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)  /*!< 0x00000004 */
+#define SDMMC_MASK_CTIMEOUTIE            SDMMC_MASK_CTIMEOUTIE_Msk             /*!<Command TimeOut Interrupt Enable           */
+#define SDMMC_MASK_DTIMEOUTIE_Pos        (3U)
+#define SDMMC_MASK_DTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)  /*!< 0x00000008 */
+#define SDMMC_MASK_DTIMEOUTIE            SDMMC_MASK_DTIMEOUTIE_Msk             /*!<Data TimeOut Interrupt Enable              */
+#define SDMMC_MASK_TXUNDERRIE_Pos        (4U)
+#define SDMMC_MASK_TXUNDERRIE_Msk        (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)  /*!< 0x00000010 */
+#define SDMMC_MASK_TXUNDERRIE            SDMMC_MASK_TXUNDERRIE_Msk             /*!<Tx FIFO UnderRun Error Interrupt Enable    */
+#define SDMMC_MASK_RXOVERRIE_Pos         (5U)
+#define SDMMC_MASK_RXOVERRIE_Msk         (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)   /*!< 0x00000020 */
+#define SDMMC_MASK_RXOVERRIE             SDMMC_MASK_RXOVERRIE_Msk              /*!<Rx FIFO OverRun Error Interrupt Enable     */
+#define SDMMC_MASK_CMDRENDIE_Pos         (6U)
+#define SDMMC_MASK_CMDRENDIE_Msk         (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)   /*!< 0x00000040 */
+#define SDMMC_MASK_CMDRENDIE             SDMMC_MASK_CMDRENDIE_Msk              /*!<Command Response Received Interrupt Enable */
+#define SDMMC_MASK_CMDSENTIE_Pos         (7U)
+#define SDMMC_MASK_CMDSENTIE_Msk         (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)   /*!< 0x00000080 */
+#define SDMMC_MASK_CMDSENTIE             SDMMC_MASK_CMDSENTIE_Msk              /*!<Command Sent Interrupt Enable              */
+#define SDMMC_MASK_DATAENDIE_Pos         (8U)
+#define SDMMC_MASK_DATAENDIE_Msk         (0x1UL << SDMMC_MASK_DATAENDIE_Pos)   /*!< 0x00000100 */
+#define SDMMC_MASK_DATAENDIE             SDMMC_MASK_DATAENDIE_Msk              /*!<Data End Interrupt Enable                  */
+#define SDMMC_MASK_DHOLDIE_Pos           (9U)
+#define SDMMC_MASK_DHOLDIE_Msk           (0x1UL << SDMMC_MASK_DHOLDIE_Pos)     /*!< 0x00000200 */
+#define SDMMC_MASK_DHOLDIE               SDMMC_MASK_DHOLDIE_Msk                /*!<Data Hold Interrupt Enable                 */
+#define SDMMC_MASK_DBCKENDIE_Pos         (10U)
+#define SDMMC_MASK_DBCKENDIE_Msk         (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)   /*!< 0x00000400 */
+#define SDMMC_MASK_DBCKENDIE             SDMMC_MASK_DBCKENDIE_Msk              /*!<Data Block End Interrupt Enable            */
+#define SDMMC_MASK_DABORTIE_Pos          (11U)
+#define SDMMC_MASK_DABORTIE_Msk          (0x1UL << SDMMC_MASK_DABORTIE_Pos)    /*!< 0x00000800 */
+#define SDMMC_MASK_DABORTIE              SDMMC_MASK_DABORTIE_Msk               /*!<Data transfer aborted interrupt enable     */
+
+#define SDMMC_MASK_TXFIFOHEIE_Pos        (14U)
+#define SDMMC_MASK_TXFIFOHEIE_Msk        (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)  /*!< 0x00004000 */
+#define SDMMC_MASK_TXFIFOHEIE            SDMMC_MASK_TXFIFOHEIE_Msk             /*!<Tx FIFO Half Empty interrupt Enable        */
+#define SDMMC_MASK_RXFIFOHFIE_Pos        (15U)
+#define SDMMC_MASK_RXFIFOHFIE_Msk        (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)  /*!< 0x00008000 */
+#define SDMMC_MASK_RXFIFOHFIE            SDMMC_MASK_RXFIFOHFIE_Msk             /*!<Rx FIFO Half Full interrupt Enable         */
+
+#define SDMMC_MASK_RXFIFOFIE_Pos         (17U)
+#define SDMMC_MASK_RXFIFOFIE_Msk         (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)   /*!< 0x00020000 */
+#define SDMMC_MASK_RXFIFOFIE             SDMMC_MASK_RXFIFOFIE_Msk              /*!<Rx FIFO Full interrupt Enable              */
+#define SDMMC_MASK_TXFIFOEIE_Pos         (18U)
+#define SDMMC_MASK_TXFIFOEIE_Msk         (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)   /*!< 0x00040000 */
+#define SDMMC_MASK_TXFIFOEIE             SDMMC_MASK_TXFIFOEIE_Msk              /*!<Tx FIFO Empty interrupt Enable             */
+
+#define SDMMC_MASK_BUSYD0ENDIE_Pos       (21U)
+#define SDMMC_MASK_BUSYD0ENDIE_Msk       (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */
+#define SDMMC_MASK_BUSYD0ENDIE           SDMMC_MASK_BUSYD0ENDIE_Msk            /*!<BUSYD0ENDIE interrupt Enable */
+#define SDMMC_MASK_SDIOITIE_Pos           (22U)
+#define SDMMC_MASK_SDIOITIE_Msk           (0x1UL << SDMMC_MASK_SDIOITIE_Pos)     /*!< 0x00400000 */
+#define SDMMC_MASK_SDIOITIE               SDMMC_MASK_SDIOITIE_Msk                /*!<SDMMC Mode Interrupt Received interrupt Enable */
+#define SDMMC_MASK_ACKFAILIE_Pos         (23U)
+#define SDMMC_MASK_ACKFAILIE_Msk         (0x1UL << SDMMC_MASK_ACKFAILIE_Pos)   /*!< 0x00800000 */
+#define SDMMC_MASK_ACKFAILIE             SDMMC_MASK_ACKFAILIE_Msk              /*!<Acknowledgment Fail Interrupt Enable */
+#define SDMMC_MASK_ACKTIMEOUTIE_Pos      (24U)
+#define SDMMC_MASK_ACKTIMEOUTIE_Msk      (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */
+#define SDMMC_MASK_ACKTIMEOUTIE          SDMMC_MASK_ACKTIMEOUTIE_Msk           /*!<Acknowledgment timeout Interrupt Enable */
+#define SDMMC_MASK_VSWENDIE_Pos          (25U)
+#define SDMMC_MASK_VSWENDIE_Msk          (0x1UL << SDMMC_MASK_VSWENDIE_Pos)    /*!< 0x02000000 */
+#define SDMMC_MASK_VSWENDIE              SDMMC_MASK_VSWENDIE_Msk               /*!<Voltage switch critical timing section completion Interrupt Enable */
+#define SDMMC_MASK_CKSTOPIE_Pos          (26U)
+#define SDMMC_MASK_CKSTOPIE_Msk          (0x1UL << SDMMC_MASK_CKSTOPIE_Pos)    /*!< 0x04000000 */
+#define SDMMC_MASK_CKSTOPIE              SDMMC_MASK_CKSTOPIE_Msk               /*!<Voltage Switch clock stopped Interrupt Enable */
+#define SDMMC_MASK_IDMABTCIE_Pos         (28U)
+#define SDMMC_MASK_IDMABTCIE_Msk         (0x1UL << SDMMC_MASK_IDMABTCIE_Pos)   /*!< 0x10000000 */
+#define SDMMC_MASK_IDMABTCIE             SDMMC_MASK_IDMABTCIE_Msk              /*!<IDMA buffer transfer complete Interrupt Enable */
+
+/*****************  Bit definition for SDMMC_ACKTIME register  *****************/
+#define SDMMC_ACKTIME_ACKTIME_Pos        (0U)
+#define SDMMC_ACKTIME_ACKTIME_Msk        (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_ACKTIME_ACKTIME            SDMMC_ACKTIME_ACKTIME_Msk             /*!<Boot acknowledgment timeout period */
+
+/******************  Bit definition for SDMMC_FIFO register  *******************/
+#define SDMMC_FIFO_FIFODATA_Pos          (0U)
+#define SDMMC_FIFO_FIFODATA_Msk          (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_FIFO_FIFODATA              SDMMC_FIFO_FIFODATA_Msk               /*!<Receive and transmit FIFO data */
+
+/******************  Bit definition for SDMMC_IDMACTRL register ****************/
+#define SDMMC_IDMA_IDMAEN_Pos            (0U)
+#define SDMMC_IDMA_IDMAEN_Msk            (0x1UL << SDMMC_IDMA_IDMAEN_Pos)      /*!< 0x00000001 */
+#define SDMMC_IDMA_IDMAEN                SDMMC_IDMA_IDMAEN_Msk                 /*!< Enable the internal DMA of the SDMMC peripheral */
+#define SDMMC_IDMA_IDMABMODE_Pos         (1U)
+#define SDMMC_IDMA_IDMABMODE_Msk         (0x1UL << SDMMC_IDMA_IDMABMODE_Pos)   /*!< 0x00000002 */
+#define SDMMC_IDMA_IDMABMODE             SDMMC_IDMA_IDMABMODE_Msk              /*!< Enable double buffer mode for IDMA */
+#define SDMMC_IDMA_IDMABACT_Pos          (2U)
+#define SDMMC_IDMA_IDMABACT_Msk          (0x1UL << SDMMC_IDMA_IDMABACT_Pos)    /*!< 0x00000004 */
+#define SDMMC_IDMA_IDMABACT              SDMMC_IDMA_IDMABACT_Msk               /*!< Uses buffer 1 when double buffer mode is selected */
+
+/*****************  Bit definition for SDMMC_IDMABSIZE register  ***************/
+#define SDMMC_IDMABSIZE_IDMABNDT_Pos     (5U)
+#define SDMMC_IDMABSIZE_IDMABNDT_Msk     (0xFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos) /*!< 0x00001FE0 */
+#define SDMMC_IDMABSIZE_IDMABNDT         SDMMC_IDMABSIZE_IDMABNDT_Msk          /*!< Number of transfers per buffer */
+
+/*****************  Bit definition for SDMMC_IDMABASE0 register  ***************/
+#define SDMMC_IDMABASE0_IDMABASE0        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 0 memory base address */
+
+/*****************  Bit definition for SDMMC_IDMABASE1 register  ***************/
+#define SDMMC_IDMABASE1_IDMABASE1        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 1 memory base address */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Delay Block Interface (DLYB)                        */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for DLYB_CR register  ********************/
+#define DLYB_CR_DEN_Pos         (0U)
+#define DLYB_CR_DEN_Msk         (0x1UL << DLYB_CR_DEN_Pos)                     /*!< 0x00000001 */
+#define DLYB_CR_DEN             DLYB_CR_DEN_Msk                                /*!<Delay Block enable */
+#define DLYB_CR_SEN_Pos         (1U)
+#define DLYB_CR_SEN_Msk         (0x1UL << DLYB_CR_SEN_Pos)                     /*!< 0x00000002 */
+#define DLYB_CR_SEN             DLYB_CR_SEN_Msk                                /*!<Sampler length enable */
+
+
+/*******************  Bit definition for DLYB_CFGR register  ********************/
+#define DLYB_CFGR_SEL_Pos       (0U)
+#define DLYB_CFGR_SEL_Msk       (0xFUL << DLYB_CFGR_SEL_Pos)                   /*!< 0x0000000F */
+#define DLYB_CFGR_SEL           DLYB_CFGR_SEL_Msk                              /*!<Select the phase for the Output clock[3:0] */
+#define DLYB_CFGR_SEL_0         (0x1UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000001 */
+#define DLYB_CFGR_SEL_1         (0x2UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000002 */
+#define DLYB_CFGR_SEL_2         (0x3UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000003 */
+#define DLYB_CFGR_SEL_3         (0x8UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000008 */
+
+#define DLYB_CFGR_UNIT_Pos      (8U)
+#define DLYB_CFGR_UNIT_Msk      (0x7FUL << DLYB_CFGR_UNIT_Pos)                 /*!< 0x00007F00 */
+#define DLYB_CFGR_UNIT          DLYB_CFGR_UNIT_Msk                             /*!<Delay Defines the delay of a Unit delay cell[6:0] */
+#define DLYB_CFGR_UNIT_0        (0x01UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000100 */
+#define DLYB_CFGR_UNIT_1        (0x02UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000200 */
+#define DLYB_CFGR_UNIT_2        (0x04UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000400 */
+#define DLYB_CFGR_UNIT_3        (0x08UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000800 */
+#define DLYB_CFGR_UNIT_4        (0x10UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00001000 */
+#define DLYB_CFGR_UNIT_5        (0x20UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00002000 */
+#define DLYB_CFGR_UNIT_6        (0x40UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00004000 */
+
+#define DLYB_CFGR_LNG_Pos       (16U)
+#define DLYB_CFGR_LNG_Msk       (0xFFFUL << DLYB_CFGR_LNG_Pos)                 /*!< 0x0FFF0000 */
+#define DLYB_CFGR_LNG           DLYB_CFGR_LNG_Msk                              /*!<Delay line length value[11:0] */
+#define DLYB_CFGR_LNG_0         (0x001UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00010000 */
+#define DLYB_CFGR_LNG_1         (0x002UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00020000 */
+#define DLYB_CFGR_LNG_2         (0x004UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00040000 */
+#define DLYB_CFGR_LNG_3         (0x008UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00080000 */
+#define DLYB_CFGR_LNG_4         (0x010UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00100000 */
+#define DLYB_CFGR_LNG_5         (0x020UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00200000 */
+#define DLYB_CFGR_LNG_6         (0x040UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00400000 */
+#define DLYB_CFGR_LNG_7         (0x080UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00800000 */
+#define DLYB_CFGR_LNG_8         (0x100UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x01000000 */
+#define DLYB_CFGR_LNG_9         (0x200UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x02000000 */
+#define DLYB_CFGR_LNG_10        (0x400UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x04000000 */
+#define DLYB_CFGR_LNG_11        (0x800UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x08000000 */
+
+#define DLYB_CFGR_LNGF_Pos      (31U)
+#define DLYB_CFGR_LNGF_Msk      (0x1UL << DLYB_CFGR_LNGF_Pos)                  /*!< 0x80000000 */
+#define DLYB_CFGR_LNGF          DLYB_CFGR_LNGF_Msk                             /*!<Length valid flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                   Serial Peripheral Interface (SPI/I2S)                    */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define SPI_CR1_SPE_Pos             (0U)
+#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000001 */
+#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<Serial Peripheral Enable                         */
+#define SPI_CR1_MASRX_Pos           (8U)
+#define SPI_CR1_MASRX_Msk           (0x1UL << SPI_CR1_MASRX_Pos)               /*!< 0x00000100 */
+#define SPI_CR1_MASRX               SPI_CR1_MASRX_Msk                          /*!<Master automatic SUSP in Receive mode            */
+#define SPI_CR1_CSTART_Pos          (9U)
+#define SPI_CR1_CSTART_Msk          (0x1UL << SPI_CR1_CSTART_Pos)              /*!< 0x00000200 */
+#define SPI_CR1_CSTART              SPI_CR1_CSTART_Msk                         /*!<Master transfer start                            */
+#define SPI_CR1_CSUSP_Pos           (10U)
+#define SPI_CR1_CSUSP_Msk           (0x1UL << SPI_CR1_CSUSP_Pos)               /*!< 0x00000400 */
+#define SPI_CR1_CSUSP               SPI_CR1_CSUSP_Msk                          /*!<Master SUSPend request                           */
+#define SPI_CR1_HDDIR_Pos           (11U)
+#define SPI_CR1_HDDIR_Msk           (0x1UL << SPI_CR1_HDDIR_Pos)               /*!< 0x00000800 */
+#define SPI_CR1_HDDIR               SPI_CR1_HDDIR_Msk                          /*!<Rx/Tx direction at Half-duplex mode              */
+#define SPI_CR1_SSI_Pos             (12U)
+#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                 /*!< 0x00001000 */
+#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal SS signal input level                   */
+#define SPI_CR1_CRC33_17_Pos        (13U)
+#define SPI_CR1_CRC33_17_Msk        (0x1UL << SPI_CR1_CRC33_17_Pos)            /*!< 0x00002000 */
+#define SPI_CR1_CRC33_17             SPI_CR1_CRC33_17_Msk                      /*!<32-bit CRC polynomial configuration              */
+#define SPI_CR1_RCRCINI_Pos         (14U)
+#define SPI_CR1_RCRCINI_Msk         (0x1UL << SPI_CR1_RCRCINI_Pos)             /*!< 0x00004000 */
+#define SPI_CR1_RCRCINI             SPI_CR1_RCRCINI_Msk                        /*!<CRC init pattern control for receiver            */
+#define SPI_CR1_TCRCINI_Pos         (15U)
+#define SPI_CR1_TCRCINI_Msk         (0x1UL << SPI_CR1_TCRCINI_Pos)             /*!< 0x00008000 */
+#define SPI_CR1_TCRCINI             SPI_CR1_TCRCINI_Msk                        /*!<CRC init pattern control for transmitter         */
+#define SPI_CR1_IOLOCK_Pos          (16U)
+#define SPI_CR1_IOLOCK_Msk          (0x1UL << SPI_CR1_IOLOCK_Pos)              /*!< 0x00010000 */
+#define SPI_CR1_IOLOCK              SPI_CR1_IOLOCK_Msk                         /*!<Locking the AF configuration of associated IOs   */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define SPI_CR2_TSER_Pos            (16U)
+#define SPI_CR2_TSER_Msk            (0xFFFFUL << SPI_CR2_TSER_Pos)             /*!< 0xFFFF0000 */
+#define SPI_CR2_TSER                SPI_CR2_TSER_Msk                           /*!<Number of data transfer extension                */
+#define SPI_CR2_TSIZE_Pos           (0U)
+#define SPI_CR2_TSIZE_Msk           (0xFFFFUL << SPI_CR2_TSIZE_Pos)            /*!< 0x0000FFFF */
+#define SPI_CR2_TSIZE               SPI_CR2_TSIZE_Msk                          /*!<Number of data at current transfer               */
+
+/*******************  Bit definition for SPI_CFG1 register  ********************/
+#define SPI_CFG1_DSIZE_Pos          (0U)
+#define SPI_CFG1_DSIZE_Msk          (0x1FUL << SPI_CFG1_DSIZE_Pos)             /*!< 0x0000001F */
+#define SPI_CFG1_DSIZE              SPI_CFG1_DSIZE_Msk                         /*!<DSIZE[4:0]: Bits number in single SPI data frame */
+#define SPI_CFG1_DSIZE_0            (0x01UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000001 */
+#define SPI_CFG1_DSIZE_1            (0x02UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000002 */
+#define SPI_CFG1_DSIZE_2            (0x04UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000004 */
+#define SPI_CFG1_DSIZE_3            (0x08UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000008 */
+#define SPI_CFG1_DSIZE_4            (0x10UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000010 */
+
+#define SPI_CFG1_FTHLV_Pos          (5U)
+#define SPI_CFG1_FTHLV_Msk          (0xFUL << SPI_CFG1_FTHLV_Pos)              /*!< 0x000001E0 */
+#define SPI_CFG1_FTHLV              SPI_CFG1_FTHLV_Msk                         /*!<FTHVL [3:0]: FIFO threshold level*/
+#define SPI_CFG1_FTHLV_0            (0x1UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000020 */
+#define SPI_CFG1_FTHLV_1            (0x2UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000040 */
+#define SPI_CFG1_FTHLV_2            (0x4UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000080 */
+#define SPI_CFG1_FTHLV_3            (0x8UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000100 */
+
+#define SPI_CFG1_UDRCFG_Pos         (9U)
+#define SPI_CFG1_UDRCFG_Msk         (0x3UL << SPI_CFG1_UDRCFG_Pos)             /*!< 0x00000600 */
+#define SPI_CFG1_UDRCFG             SPI_CFG1_UDRCFG_Msk                        /*!<UDRCFG[1:0]: Behavior of transmitter at underrun */
+#define SPI_CFG1_UDRCFG_0           (0x1UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000200 */
+#define SPI_CFG1_UDRCFG_1           (0x2UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000400 */
+
+
+#define SPI_CFG1_UDRDET_Pos         (11U)
+#define SPI_CFG1_UDRDET_Msk         (0x3UL << SPI_CFG1_UDRDET_Pos)             /*!< 0x00001800 */
+#define SPI_CFG1_UDRDET             SPI_CFG1_UDRDET_Msk                        /*!<UDRDET[1:0]: Detection of underrun condition     */
+#define SPI_CFG1_UDRDET_0           (0x1UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00000800 */
+#define SPI_CFG1_UDRDET_1           (0x2UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00001000 */
+
+#define SPI_CFG1_RXDMAEN_Pos        (14U)
+#define SPI_CFG1_RXDMAEN_Msk        (0x1UL << SPI_CFG1_RXDMAEN_Pos)            /*!< 0x00004000 */
+#define SPI_CFG1_RXDMAEN            SPI_CFG1_RXDMAEN_Msk                       /*!<Rx DMA stream enable                */
+#define SPI_CFG1_TXDMAEN_Pos        (15U)
+#define SPI_CFG1_TXDMAEN_Msk        (0x1UL << SPI_CFG1_TXDMAEN_Pos)            /*!< 0x00008000 */
+#define SPI_CFG1_TXDMAEN            SPI_CFG1_TXDMAEN_Msk                       /*!<Tx DMA stream enable                */
+
+#define SPI_CFG1_CRCSIZE_Pos        (16U)
+#define SPI_CFG1_CRCSIZE_Msk        (0x1FUL << SPI_CFG1_CRCSIZE_Pos)           /*!< 0x001F0000 */
+#define SPI_CFG1_CRCSIZE            SPI_CFG1_CRCSIZE_Msk                       /*!<CRCSIZE [4:0]: Length of CRC frame*/
+#define SPI_CFG1_CRCSIZE_0          (0x01UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00010000 */
+#define SPI_CFG1_CRCSIZE_1          (0x02UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00020000 */
+#define SPI_CFG1_CRCSIZE_2          (0x04UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00040000 */
+#define SPI_CFG1_CRCSIZE_3          (0x08UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00080000 */
+#define SPI_CFG1_CRCSIZE_4          (0x10UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00100000 */
+
+#define SPI_CFG1_CRCEN_Pos          (22U)
+#define SPI_CFG1_CRCEN_Msk          (0x1UL << SPI_CFG1_CRCEN_Pos)              /*!< 0x00400000 */
+#define SPI_CFG1_CRCEN              SPI_CFG1_CRCEN_Msk                         /*!<Hardware CRC computation enable */
+
+#define SPI_CFG1_MBR_Pos            (28U)
+#define SPI_CFG1_MBR_Msk            (0x7UL << SPI_CFG1_MBR_Pos)                /*!< 0x70000000 */
+#define SPI_CFG1_MBR                SPI_CFG1_MBR_Msk                           /*!<Master baud rate                */
+#define SPI_CFG1_MBR_0              (0x1UL << SPI_CFG1_MBR_Pos)                 /*!< 0x10000000 */
+#define SPI_CFG1_MBR_1              (0x2UL << SPI_CFG1_MBR_Pos)                 /*!< 0x20000000 */
+#define SPI_CFG1_MBR_2              (0x4UL << SPI_CFG1_MBR_Pos)                 /*!< 0x40000000 */
+
+/*******************  Bit definition for SPI_CFG2 register  ********************/
+#define SPI_CFG2_MSSI_Pos           (0U)
+#define SPI_CFG2_MSSI_Msk           (0xFUL << SPI_CFG2_MSSI_Pos)               /*!< 0x0000000F */
+#define SPI_CFG2_MSSI               SPI_CFG2_MSSI_Msk                          /*!<Master SS Idleness */
+#define SPI_CFG2_MSSI_0             (0x1UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000001 */
+#define SPI_CFG2_MSSI_1             (0x2UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000002 */
+#define SPI_CFG2_MSSI_2             (0x4UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000004 */
+#define SPI_CFG2_MSSI_3             (0x8UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000008 */
+
+#define SPI_CFG2_MIDI_Pos           (4U)
+#define SPI_CFG2_MIDI_Msk           (0xFUL << SPI_CFG2_MIDI_Pos)               /*!< 0x000000F0 */
+#define SPI_CFG2_MIDI               SPI_CFG2_MIDI_Msk                          /*!<Master Inter-Data Idleness */
+#define SPI_CFG2_MIDI_0             (0x1UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000010 */
+#define SPI_CFG2_MIDI_1             (0x2UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000020 */
+#define SPI_CFG2_MIDI_2             (0x4UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000040 */
+#define SPI_CFG2_MIDI_3             (0x8UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000080 */
+
+#define SPI_CFG2_IOSWP_Pos          (15U)
+#define SPI_CFG2_IOSWP_Msk          (0x1UL << SPI_CFG2_IOSWP_Pos)              /*!< 0x00008000 */
+#define SPI_CFG2_IOSWP              SPI_CFG2_IOSWP_Msk                         /*!<Swap functionality of MISO and MOSI pins */
+
+#define SPI_CFG2_COMM_Pos           (17U)
+#define SPI_CFG2_COMM_Msk           (0x3UL << SPI_CFG2_COMM_Pos)               /*!< 0x00060000 */
+#define SPI_CFG2_COMM               SPI_CFG2_COMM_Msk                          /*!<COMM [1:0]: SPI Communication Mode*/
+#define SPI_CFG2_COMM_0             (0x1UL << SPI_CFG2_COMM_Pos)                /*!< 0x00020000 */
+#define SPI_CFG2_COMM_1             (0x2UL << SPI_CFG2_COMM_Pos)                /*!< 0x00040000 */
+
+#define SPI_CFG2_SP_Pos             (19U)
+#define SPI_CFG2_SP_Msk             (0x7UL << SPI_CFG2_SP_Pos)                 /*!< 0x00380000 */
+#define SPI_CFG2_SP                 SPI_CFG2_SP_Msk                            /*!<SP[2:0]: Serial Protocol */
+#define SPI_CFG2_SP_0               (0x1UL << SPI_CFG2_SP_Pos)                  /*!< 0x00080000 */
+#define SPI_CFG2_SP_1               (0x2UL << SPI_CFG2_SP_Pos)                  /*!< 0x00100000 */
+#define SPI_CFG2_SP_2               (0x4UL << SPI_CFG2_SP_Pos)                  /*!< 0x00200000 */
+
+#define SPI_CFG2_MASTER_Pos         (22U)
+#define SPI_CFG2_MASTER_Msk         (0x1UL << SPI_CFG2_MASTER_Pos)             /*!< 0x00400000 */
+#define SPI_CFG2_MASTER             SPI_CFG2_MASTER_Msk                        /*!<SPI Master           */
+#define SPI_CFG2_LSBFRST_Pos        (23U)
+#define SPI_CFG2_LSBFRST_Msk        (0x1UL << SPI_CFG2_LSBFRST_Pos)            /*!< 0x00800000 */
+#define SPI_CFG2_LSBFRST            SPI_CFG2_LSBFRST_Msk                       /*!<Data frame format               */
+#define SPI_CFG2_CPHA_Pos           (24U)
+#define SPI_CFG2_CPHA_Msk           (0x1UL << SPI_CFG2_CPHA_Pos)               /*!< 0x01000000 */
+#define SPI_CFG2_CPHA               SPI_CFG2_CPHA_Msk                          /*!<Clock Phase      */
+#define SPI_CFG2_CPOL_Pos           (25U)
+#define SPI_CFG2_CPOL_Msk           (0x1UL << SPI_CFG2_CPOL_Pos)               /*!< 0x02000000 */
+#define SPI_CFG2_CPOL               SPI_CFG2_CPOL_Msk                          /*!<Clock Polarity   */
+#define SPI_CFG2_SSM_Pos            (26U)
+#define SPI_CFG2_SSM_Msk            (0x1UL << SPI_CFG2_SSM_Pos)                /*!< 0x04000000 */
+#define SPI_CFG2_SSM                SPI_CFG2_SSM_Msk                           /*!<Software slave management */
+
+#define SPI_CFG2_SSIOP_Pos          (28U)
+#define SPI_CFG2_SSIOP_Msk          (0x1UL << SPI_CFG2_SSIOP_Pos)              /*!< 0x10000000 */
+#define SPI_CFG2_SSIOP              SPI_CFG2_SSIOP_Msk                         /*!<SS input/output polarity */
+#define SPI_CFG2_SSOE_Pos           (29U)
+#define SPI_CFG2_SSOE_Msk           (0x1UL << SPI_CFG2_SSOE_Pos)               /*!< 0x20000000 */
+#define SPI_CFG2_SSOE               SPI_CFG2_SSOE_Msk                          /*!<SS output enable */
+#define SPI_CFG2_SSOM_Pos           (30U)
+#define SPI_CFG2_SSOM_Msk           (0x1UL << SPI_CFG2_SSOM_Pos)               /*!< 0x40000000 */
+#define SPI_CFG2_SSOM               SPI_CFG2_SSOM_Msk                          /*!<SS output management in master mode */
+
+#define SPI_CFG2_AFCNTR_Pos         (31U)
+#define SPI_CFG2_AFCNTR_Msk         (0x1UL << SPI_CFG2_AFCNTR_Pos)             /*!< 0x80000000 */
+#define SPI_CFG2_AFCNTR             SPI_CFG2_AFCNTR_Msk                        /*!<Alternate function GPIOs control */
+
+/*******************  Bit definition for SPI_IER register  ********************/
+#define SPI_IER_RXPIE_Pos           (0U)
+#define SPI_IER_RXPIE_Msk           (0x1UL << SPI_IER_RXPIE_Pos)               /*!< 0x00000001 */
+#define SPI_IER_RXPIE               SPI_IER_RXPIE_Msk                          /*!<RXP Interrupt Enable            */
+#define SPI_IER_TXPIE_Pos           (1U)
+#define SPI_IER_TXPIE_Msk           (0x1UL << SPI_IER_TXPIE_Pos)               /*!< 0x00000002 */
+#define SPI_IER_TXPIE               SPI_IER_TXPIE_Msk                          /*!<TXP interrupt enable            */
+#define SPI_IER_DXPIE_Pos           (2U)
+#define SPI_IER_DXPIE_Msk           (0x1UL << SPI_IER_DXPIE_Pos)               /*!< 0x00000004 */
+#define SPI_IER_DXPIE               SPI_IER_DXPIE_Msk                          /*!<DXP interrupt enable            */
+#define SPI_IER_EOTIE_Pos           (3U)
+#define SPI_IER_EOTIE_Msk           (0x1UL << SPI_IER_EOTIE_Pos)               /*!< 0x00000008 */
+#define SPI_IER_EOTIE               SPI_IER_EOTIE_Msk                          /*!<EOT/SUSP/TXC interrupt enable   */
+#define SPI_IER_TXTFIE_Pos          (4U)
+#define SPI_IER_TXTFIE_Msk          (0x1UL << SPI_IER_TXTFIE_Pos)              /*!< 0x00000010 */
+#define SPI_IER_TXTFIE              SPI_IER_TXTFIE_Msk                         /*!<TXTF interrupt enable           */
+#define SPI_IER_UDRIE_Pos           (5U)
+#define SPI_IER_UDRIE_Msk           (0x1UL << SPI_IER_UDRIE_Pos)               /*!< 0x00000020 */
+#define SPI_IER_UDRIE               SPI_IER_UDRIE_Msk                          /*!<UDR interrupt enable            */
+#define SPI_IER_OVRIE_Pos           (6U)
+#define SPI_IER_OVRIE_Msk           (0x1UL << SPI_IER_OVRIE_Pos)               /*!< 0x00000040 */
+#define SPI_IER_OVRIE               SPI_IER_OVRIE_Msk                          /*!<OVR interrupt enable            */
+#define SPI_IER_CRCEIE_Pos          (7U)
+#define SPI_IER_CRCEIE_Msk          (0x1UL << SPI_IER_CRCEIE_Pos)               /*!< 0x00000080 */
+#define SPI_IER_CRCEIE              SPI_IER_CRCEIE_Msk                          /*!<CRCE interrupt enable           */
+#define SPI_IER_TIFREIE_Pos         (8U)
+#define SPI_IER_TIFREIE_Msk         (0x1UL << SPI_IER_TIFREIE_Pos)             /*!< 0x00000100 */
+#define SPI_IER_TIFREIE             SPI_IER_TIFREIE_Msk                        /*!<TI Frame Error interrupt enable */
+#define SPI_IER_MODFIE_Pos          (9U)
+#define SPI_IER_MODFIE_Msk          (0x1UL << SPI_IER_MODFIE_Pos)              /*!< 0x00000200 */
+#define SPI_IER_MODFIE              SPI_IER_MODFIE_Msk                         /*!<MODF interrupt enable           */
+#define SPI_IER_TSERFIE_Pos         (10U)
+#define SPI_IER_TSERFIE_Msk         (0x1UL << SPI_IER_TSERFIE_Pos)              /*!< 0x00000400 */
+#define SPI_IER_TSERFIE             SPI_IER_TSERFIE_Msk                        /*!<TSERF interrupt enable          */
+
+/*******************  Bit definition for SPI_SR register  ********************/
+#define SPI_SR_RXP_Pos              (0U)
+#define SPI_SR_RXP_Msk              (0x1UL << SPI_SR_RXP_Pos)                  /*!< 0x00000001 */
+#define SPI_SR_RXP                  SPI_SR_RXP_Msk                             /*!<Rx-Packet available             */
+#define SPI_SR_TXP_Pos              (1U)
+#define SPI_SR_TXP_Msk              (0x1UL << SPI_SR_TXP_Pos)                  /*!< 0x00000002 */
+#define SPI_SR_TXP                  SPI_SR_TXP_Msk                             /*!<Tx-Packet space available       */
+#define SPI_SR_DXP_Pos              (2U)
+#define SPI_SR_DXP_Msk              (0x1UL << SPI_SR_DXP_Pos)                  /*!< 0x00000004 */
+#define SPI_SR_DXP                  SPI_SR_DXP_Msk                             /*!<Duplex Packet available         */
+#define SPI_SR_EOT_Pos              (3U)
+#define SPI_SR_EOT_Msk              (0x1UL << SPI_SR_EOT_Pos)                  /*!< 0x00000008 */
+#define SPI_SR_EOT                  SPI_SR_EOT_Msk                             /*!<Duplex Packet available         */
+#define SPI_SR_TXTF_Pos             (4U)
+#define SPI_SR_TXTF_Msk             (0x1UL << SPI_SR_TXTF_Pos)                 /*!< 0x00000010 */
+#define SPI_SR_TXTF                 SPI_SR_TXTF_Msk                            /*!<Transmission Transfer Filled    */
+#define SPI_SR_UDR_Pos              (5U)
+#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                  /*!< 0x00000020 */
+#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<UDR at Slave transmission       */
+#define SPI_SR_OVR_Pos              (6U)
+#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                  /*!< 0x00000040 */
+#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Rx-Packet available             */
+#define SPI_SR_CRCE_Pos             (7U)
+#define SPI_SR_CRCE_Msk             (0x1UL << SPI_SR_CRCE_Pos)                 /*!< 0x00000080 */
+#define SPI_SR_CRCE                 SPI_SR_CRCE_Msk                            /*!<CRC Error Detected              */
+#define SPI_SR_TIFRE_Pos            (8U)
+#define SPI_SR_TIFRE_Msk            (0x1UL << SPI_SR_TIFRE_Pos)                /*!< 0x00000100 */
+#define SPI_SR_TIFRE                SPI_SR_TIFRE_Msk                           /*!<TI frame format error Detected  */
+#define SPI_SR_MODF_Pos             (9U)
+#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                 /*!< 0x00000200 */
+#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode Fault Detected             */
+#define SPI_SR_TSERF_Pos            (10U)
+#define SPI_SR_TSERF_Msk            (0x1UL << SPI_SR_TSERF_Pos)                /*!< 0x00000400 */
+#define SPI_SR_TSERF                SPI_SR_TSERF_Msk                           /*!<Number of SPI data to be transacted reloaded     */
+#define SPI_SR_SUSP_Pos             (11U)
+#define SPI_SR_SUSP_Msk             (0x1UL << SPI_SR_SUSP_Pos)                 /*!< 0x00000800 */
+#define SPI_SR_SUSP                 SPI_SR_SUSP_Msk                            /*!<SUSP is set by hardware  */
+#define SPI_SR_TXC_Pos              (12U)
+#define SPI_SR_TXC_Msk              (0x1UL << SPI_SR_TXC_Pos)                  /*!< 0x00001000 */
+#define SPI_SR_TXC                  SPI_SR_TXC_Msk                             /*!<TxFIFO transmission complete */
+#define SPI_SR_RXPLVL_Pos           (13U)
+#define SPI_SR_RXPLVL_Msk           (0x3UL << SPI_SR_RXPLVL_Pos)               /*!< 0x00006000 */
+#define SPI_SR_RXPLVL               SPI_SR_RXPLVL_Msk                          /*!<RxFIFO Packing Level                             */
+#define SPI_SR_RXPLVL_0             (0x1UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00002000 */
+#define SPI_SR_RXPLVL_1             (0x2UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00004000 */
+#define SPI_SR_RXWNE_Pos            (15U)
+#define SPI_SR_RXWNE_Msk            (0x1UL << SPI_SR_RXWNE_Pos)                /*!< 0x00008000 */
+#define SPI_SR_RXWNE                SPI_SR_RXWNE_Msk                           /*!<Rx FIFO Word Not Empty                           */
+#define SPI_SR_CTSIZE_Pos           (16U)
+#define SPI_SR_CTSIZE_Msk           (0xFFFFUL << SPI_SR_CTSIZE_Pos)            /*!< 0xFFFF0000 */
+#define SPI_SR_CTSIZE               SPI_SR_CTSIZE_Msk                          /*!<Number of data frames remaining in TSIZE         */
+
+/*******************  Bit definition for SPI_IFCR register  ********************/
+#define SPI_IFCR_EOTC_Pos           (3U)
+#define SPI_IFCR_EOTC_Msk           (0x1UL << SPI_IFCR_EOTC_Pos)               /*!< 0x00000008 */
+#define SPI_IFCR_EOTC               SPI_IFCR_EOTC_Msk                          /*!<End Of Transfer flag clear              */
+#define SPI_IFCR_TXTFC_Pos          (4U)
+#define SPI_IFCR_TXTFC_Msk          (0x1UL << SPI_IFCR_TXTFC_Pos)              /*!< 0x00000010 */
+#define SPI_IFCR_TXTFC              SPI_IFCR_TXTFC_Msk                         /*!<Transmission Transfer Filled flag clear */
+#define SPI_IFCR_UDRC_Pos           (5U)
+#define SPI_IFCR_UDRC_Msk           (0x1UL << SPI_IFCR_UDRC_Pos)               /*!< 0x00000020 */
+#define SPI_IFCR_UDRC               SPI_IFCR_UDRC_Msk                          /*!<Underrun flag clear                     */
+#define SPI_IFCR_OVRC_Pos           (6U)
+#define SPI_IFCR_OVRC_Msk           (0x1UL << SPI_IFCR_OVRC_Pos)               /*!< 0x00000040 */
+#define SPI_IFCR_OVRC               SPI_IFCR_OVRC_Msk                          /*!<Overrun flag clear                      */
+#define SPI_IFCR_CRCEC_Pos          (7U)
+#define SPI_IFCR_CRCEC_Msk          (0x1UL << SPI_IFCR_CRCEC_Pos)              /*!< 0x00000080 */
+#define SPI_IFCR_CRCEC              SPI_IFCR_CRCEC_Msk                         /*!<CRC Error flag clear                    */
+#define SPI_IFCR_TIFREC_Pos         (8U)
+#define SPI_IFCR_TIFREC_Msk         (0x1UL << SPI_IFCR_TIFREC_Pos)             /*!< 0x00000100 */
+#define SPI_IFCR_TIFREC             SPI_IFCR_TIFREC_Msk                        /*!<TI frame format error flag clear        */
+#define SPI_IFCR_MODFC_Pos          (9U)
+#define SPI_IFCR_MODFC_Msk          (0x1UL << SPI_IFCR_MODFC_Pos)              /*!< 0x00000200 */
+#define SPI_IFCR_MODFC              SPI_IFCR_MODFC_Msk                         /*!<Mode Fault flag clear                   */
+#define SPI_IFCR_TSERFC_Pos         (10U)
+#define SPI_IFCR_TSERFC_Msk         (0x1UL << SPI_IFCR_TSERFC_Pos)             /*!< 0x00000400 */
+#define SPI_IFCR_TSERFC             SPI_IFCR_TSERFC_Msk                        /*!<TSERFC flag clear                       */
+#define SPI_IFCR_SUSPC_Pos          (11U)
+#define SPI_IFCR_SUSPC_Msk          (0x1UL << SPI_IFCR_SUSPC_Pos)              /*!< 0x00000800 */
+#define SPI_IFCR_SUSPC              SPI_IFCR_SUSPC_Msk                         /*!<SUSPend flag clear                      */
+
+/*******************  Bit definition for SPI_TXDR register  ********************/
+#define SPI_TXDR_TXDR_Pos           (0U)
+#define SPI_TXDR_TXDR_Msk           (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos)        /*!< 0xFFFFFFFF */
+#define SPI_TXDR_TXDR               SPI_TXDR_TXDR_Msk                          /* Transmit Data Register */
+
+/*******************  Bit definition for SPI_RXDR register  ********************/
+#define SPI_RXDR_RXDR_Pos           (0U)
+#define SPI_RXDR_RXDR_Msk           (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos)        /*!< 0xFFFFFFFF */
+#define SPI_RXDR_RXDR               SPI_RXDR_RXDR_Msk                          /* Receive Data Register  */
+
+/*******************  Bit definition for SPI_CRCPOLY register  ********************/
+#define SPI_CRCPOLY_CRCPOLY_Pos     (0U)
+#define SPI_CRCPOLY_CRCPOLY_Msk     (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos)  /*!< 0xFFFFFFFF */
+#define SPI_CRCPOLY_CRCPOLY         SPI_CRCPOLY_CRCPOLY_Msk                    /* CRC Polynomial register  */
+
+/*******************  Bit definition for SPI_TXCRC register  ********************/
+#define SPI_TXCRC_TXCRC_Pos         (0U)
+#define SPI_TXCRC_TXCRC_Msk         (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos)      /*!< 0xFFFFFFFF */
+#define SPI_TXCRC_TXCRC             SPI_TXCRC_TXCRC_Msk                        /* CRCRegister for transmitter */
+
+/*******************  Bit definition for SPI_RXCRC register  ********************/
+#define SPI_RXCRC_RXCRC_Pos         (0U)
+#define SPI_RXCRC_RXCRC_Msk         (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos)      /*!< 0xFFFFFFFF */
+#define SPI_RXCRC_RXCRC             SPI_RXCRC_RXCRC_Msk                        /* CRCRegister for receiver */
+
+/*******************  Bit definition for SPI_UDRDR register  ********************/
+#define SPI_UDRDR_UDRDR_Pos         (0U)
+#define SPI_UDRDR_UDRDR_Msk         (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos)      /*!< 0xFFFFFFFF */
+#define SPI_UDRDR_UDRDR             SPI_UDRDR_UDRDR_Msk                        /* Data at slave underrun condition */
+
+/******************  Bit definition for SPI_I2SCFGR register  *****************/
+#define SPI_I2SCFGR_I2SMOD_Pos      (0U)
+#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)          /*!< 0x00000001 */
+#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
+#define SPI_I2SCFGR_I2SCFG_Pos      (1U)
+#define SPI_I2SCFGR_I2SCFG_Msk      (0x7UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x0000000E */
+#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[2:0] I2S configuration mode                */
+#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000002 */
+#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000004 */
+#define SPI_I2SCFGR_I2SCFG_2        (0x4UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000008 */
+#define SPI_I2SCFGR_I2SSTD_Pos      (4U)
+#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] I2S standard selection                */
+#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */
+#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)
+#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)         /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                         */
+#define SPI_I2SCFGR_DATLEN_Pos      (8U)
+#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000300 */
+#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] Data length to be transferred         */
+#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000100 */
+#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000200 */
+#define SPI_I2SCFGR_CHLEN_Pos       (10U)
+#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)           /*!< 0x00000400 */
+#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
+#define SPI_I2SCFGR_CKPOL_Pos       (11U)
+#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)           /*!< 0x00000800 */
+#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<Steady state clock polarity                       */
+#define SPI_I2SCFGR_FIXCH_Pos       (12U)
+#define SPI_I2SCFGR_FIXCH_Msk       (0x1UL << SPI_I2SCFGR_FIXCH_Pos)           /*!< 0x00001000 */
+#define SPI_I2SCFGR_FIXCH           SPI_I2SCFGR_FIXCH_Msk                      /*!<Fixed channel length in SLAVE                     */
+#define SPI_I2SCFGR_WSINV_Pos       (13U)
+#define SPI_I2SCFGR_WSINV_Msk       (0x1UL << SPI_I2SCFGR_WSINV_Pos)           /*!< 0x00002000 */
+#define SPI_I2SCFGR_WSINV           SPI_I2SCFGR_WSINV_Msk                      /*!<Word select inversion                             */
+#define SPI_I2SCFGR_DATFMT_Pos      (14U)
+#define SPI_I2SCFGR_DATFMT_Msk      (0x1UL << SPI_I2SCFGR_DATFMT_Pos)          /*!< 0x00004000 */
+#define SPI_I2SCFGR_DATFMT          SPI_I2SCFGR_DATFMT_Msk                     /*!<Data format                                       */
+#define SPI_I2SCFGR_I2SDIV_Pos      (16U)
+#define SPI_I2SCFGR_I2SDIV_Msk      (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos)         /*!< 0x00FF0000 */
+#define SPI_I2SCFGR_I2SDIV          SPI_I2SCFGR_I2SDIV_Msk                     /*!<I2S Linear prescaler */
+#define SPI_I2SCFGR_ODD_Pos         (24U)
+#define SPI_I2SCFGR_ODD_Msk         (0x1UL << SPI_I2SCFGR_ODD_Pos)             /*!< 0x01000000 */
+#define SPI_I2SCFGR_ODD             SPI_I2SCFGR_ODD_Msk                        /*!<Odd factor for the prescaler */
+#define SPI_I2SCFGR_MCKOE_Pos       (25U)
+#define SPI_I2SCFGR_MCKOE_Msk       (0x1UL << SPI_I2SCFGR_MCKOE_Pos)           /*!< 0x02000000 */
+#define SPI_I2SCFGR_MCKOE           SPI_I2SCFGR_MCKOE_Msk                      /*!<Master Clock Output Enable */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    QUADSPI                                 */
+/*                                                                            */
+/******************************************************************************/
+/*****************  Bit definition for QUADSPI_CR register  *******************/
+#define QUADSPI_CR_EN_Pos                (0U)
+#define QUADSPI_CR_EN_Msk                (0x1UL << QUADSPI_CR_EN_Pos)          /*!< 0x00000001 */
+#define QUADSPI_CR_EN                    QUADSPI_CR_EN_Msk                     /*!< Enable */
+#define QUADSPI_CR_ABORT_Pos             (1U)
+#define QUADSPI_CR_ABORT_Msk             (0x1UL << QUADSPI_CR_ABORT_Pos)       /*!< 0x00000002 */
+#define QUADSPI_CR_ABORT                 QUADSPI_CR_ABORT_Msk                  /*!< Abort request */
+#define QUADSPI_CR_DMAEN_Pos             (2U)
+#define QUADSPI_CR_DMAEN_Msk             (0x1UL << QUADSPI_CR_DMAEN_Pos)       /*!< 0x00000004 */
+#define QUADSPI_CR_DMAEN                 QUADSPI_CR_DMAEN_Msk                  /*!< DMA Enable */
+#define QUADSPI_CR_TCEN_Pos              (3U)
+#define QUADSPI_CR_TCEN_Msk              (0x1UL << QUADSPI_CR_TCEN_Pos)        /*!< 0x00000008 */
+#define QUADSPI_CR_TCEN                  QUADSPI_CR_TCEN_Msk                   /*!< Timeout Counter Enable */
+#define QUADSPI_CR_SSHIFT_Pos            (4U)
+#define QUADSPI_CR_SSHIFT_Msk            (0x1UL << QUADSPI_CR_SSHIFT_Pos)      /*!< 0x00000010 */
+#define QUADSPI_CR_SSHIFT                QUADSPI_CR_SSHIFT_Msk                 /*!< SSHIFT Sample Shift */
+#define QUADSPI_CR_DFM_Pos               (6U)
+#define QUADSPI_CR_DFM_Msk               (0x1UL << QUADSPI_CR_DFM_Pos)         /*!< 0x00000040 */
+#define QUADSPI_CR_DFM                   QUADSPI_CR_DFM_Msk                    /*!< Dual Flash Mode */
+#define QUADSPI_CR_FSEL_Pos              (7U)
+#define QUADSPI_CR_FSEL_Msk              (0x1UL << QUADSPI_CR_FSEL_Pos)        /*!< 0x00000080 */
+#define QUADSPI_CR_FSEL                  QUADSPI_CR_FSEL_Msk                   /*!< Flash Select */
+#define QUADSPI_CR_FTHRES_Pos            (8U)
+#define QUADSPI_CR_FTHRES_Msk            (0xFUL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000F00 */
+#define QUADSPI_CR_FTHRES                QUADSPI_CR_FTHRES_Msk                 /*!< FTHRES[3:0] FIFO Level */
+#define QUADSPI_CR_FTHRES_0              (0x1UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000100 */
+#define QUADSPI_CR_FTHRES_1              (0x2UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000200 */
+#define QUADSPI_CR_FTHRES_2              (0x4UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000400 */
+#define QUADSPI_CR_FTHRES_3              (0x8UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000800 */
+#define QUADSPI_CR_TEIE_Pos              (16U)
+#define QUADSPI_CR_TEIE_Msk              (0x1UL << QUADSPI_CR_TEIE_Pos)        /*!< 0x00010000 */
+#define QUADSPI_CR_TEIE                  QUADSPI_CR_TEIE_Msk                   /*!< Transfer Error Interrupt Enable */
+#define QUADSPI_CR_TCIE_Pos              (17U)
+#define QUADSPI_CR_TCIE_Msk              (0x1UL << QUADSPI_CR_TCIE_Pos)        /*!< 0x00020000 */
+#define QUADSPI_CR_TCIE                  QUADSPI_CR_TCIE_Msk                   /*!< Transfer Complete Interrupt Enable */
+#define QUADSPI_CR_FTIE_Pos              (18U)
+#define QUADSPI_CR_FTIE_Msk              (0x1UL << QUADSPI_CR_FTIE_Pos)        /*!< 0x00040000 */
+#define QUADSPI_CR_FTIE                  QUADSPI_CR_FTIE_Msk                   /*!< FIFO Threshold Interrupt Enable */
+#define QUADSPI_CR_SMIE_Pos              (19U)
+#define QUADSPI_CR_SMIE_Msk              (0x1UL << QUADSPI_CR_SMIE_Pos)        /*!< 0x00080000 */
+#define QUADSPI_CR_SMIE                  QUADSPI_CR_SMIE_Msk                   /*!< Status Match Interrupt Enable */
+#define QUADSPI_CR_TOIE_Pos              (20U)
+#define QUADSPI_CR_TOIE_Msk              (0x1UL << QUADSPI_CR_TOIE_Pos)        /*!< 0x00100000 */
+#define QUADSPI_CR_TOIE                  QUADSPI_CR_TOIE_Msk                   /*!< TimeOut Interrupt Enable */
+#define QUADSPI_CR_APMS_Pos              (22U)
+#define QUADSPI_CR_APMS_Msk              (0x1UL << QUADSPI_CR_APMS_Pos)        /*!< 0x00400000 */
+#define QUADSPI_CR_APMS                  QUADSPI_CR_APMS_Msk                   /*!< Bit 1 */
+#define QUADSPI_CR_PMM_Pos               (23U)
+#define QUADSPI_CR_PMM_Msk               (0x1UL << QUADSPI_CR_PMM_Pos)         /*!< 0x00800000 */
+#define QUADSPI_CR_PMM                   QUADSPI_CR_PMM_Msk                    /*!< Polling Match Mode */
+#define QUADSPI_CR_PRESCALER_Pos         (24U)
+#define QUADSPI_CR_PRESCALER_Msk         (0xFFUL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0xFF000000 */
+#define QUADSPI_CR_PRESCALER             QUADSPI_CR_PRESCALER_Msk              /*!< PRESCALER[7:0] Clock prescaler */
+#define QUADSPI_CR_PRESCALER_0           (0x01UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x01000000 */
+#define QUADSPI_CR_PRESCALER_1           (0x02UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x02000000 */
+#define QUADSPI_CR_PRESCALER_2           (0x04UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x04000000 */
+#define QUADSPI_CR_PRESCALER_3           (0x08UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x08000000 */
+#define QUADSPI_CR_PRESCALER_4           (0x10UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x10000000 */
+#define QUADSPI_CR_PRESCALER_5           (0x20UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x20000000 */
+#define QUADSPI_CR_PRESCALER_6           (0x40UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x40000000 */
+#define QUADSPI_CR_PRESCALER_7           (0x80UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x80000000 */
+
+/*****************  Bit definition for QUADSPI_DCR register  ******************/
+#define QUADSPI_DCR_CKMODE_Pos           (0U)
+#define QUADSPI_DCR_CKMODE_Msk           (0x1UL << QUADSPI_DCR_CKMODE_Pos)     /*!< 0x00000001 */
+#define QUADSPI_DCR_CKMODE               QUADSPI_DCR_CKMODE_Msk                /*!< Mode 0 / Mode 3 */
+#define QUADSPI_DCR_CSHT_Pos             (8U)
+#define QUADSPI_DCR_CSHT_Msk             (0x7UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000700 */
+#define QUADSPI_DCR_CSHT                 QUADSPI_DCR_CSHT_Msk                  /*!< CSHT[2:0]: ChipSelect High Time */
+#define QUADSPI_DCR_CSHT_0               (0x1UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000100 */
+#define QUADSPI_DCR_CSHT_1               (0x2UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000200 */
+#define QUADSPI_DCR_CSHT_2               (0x4UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000400 */
+#define QUADSPI_DCR_FSIZE_Pos            (16U)
+#define QUADSPI_DCR_FSIZE_Msk            (0x1FUL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x001F0000 */
+#define QUADSPI_DCR_FSIZE                QUADSPI_DCR_FSIZE_Msk                 /*!< FSIZE[4:0]: Flash Size */
+#define QUADSPI_DCR_FSIZE_0              (0x01UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00010000 */
+#define QUADSPI_DCR_FSIZE_1              (0x02UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00020000 */
+#define QUADSPI_DCR_FSIZE_2              (0x04UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00040000 */
+#define QUADSPI_DCR_FSIZE_3              (0x08UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00080000 */
+#define QUADSPI_DCR_FSIZE_4              (0x10UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00100000 */
+
+/******************  Bit definition for QUADSPI_SR register  *******************/
+#define QUADSPI_SR_TEF_Pos               (0U)
+#define QUADSPI_SR_TEF_Msk               (0x1UL << QUADSPI_SR_TEF_Pos)         /*!< 0x00000001 */
+#define QUADSPI_SR_TEF                   QUADSPI_SR_TEF_Msk                    /*!< Transfer Error Flag */
+#define QUADSPI_SR_TCF_Pos               (1U)
+#define QUADSPI_SR_TCF_Msk               (0x1UL << QUADSPI_SR_TCF_Pos)         /*!< 0x00000002 */
+#define QUADSPI_SR_TCF                   QUADSPI_SR_TCF_Msk                    /*!< Transfer Complete Flag */
+#define QUADSPI_SR_FTF_Pos               (2U)
+#define QUADSPI_SR_FTF_Msk               (0x1UL << QUADSPI_SR_FTF_Pos)         /*!< 0x00000004 */
+#define QUADSPI_SR_FTF                   QUADSPI_SR_FTF_Msk                    /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_SMF_Pos               (3U)
+#define QUADSPI_SR_SMF_Msk               (0x1UL << QUADSPI_SR_SMF_Pos)         /*!< 0x00000008 */
+#define QUADSPI_SR_SMF                   QUADSPI_SR_SMF_Msk                    /*!< Status Match Flag */
+#define QUADSPI_SR_TOF_Pos               (4U)
+#define QUADSPI_SR_TOF_Msk               (0x1UL << QUADSPI_SR_TOF_Pos)         /*!< 0x00000010 */
+#define QUADSPI_SR_TOF                   QUADSPI_SR_TOF_Msk                    /*!< Timeout Flag */
+#define QUADSPI_SR_BUSY_Pos              (5U)
+#define QUADSPI_SR_BUSY_Msk              (0x1UL << QUADSPI_SR_BUSY_Pos)        /*!< 0x00000020 */
+#define QUADSPI_SR_BUSY                  QUADSPI_SR_BUSY_Msk                   /*!< Busy */
+#define QUADSPI_SR_FLEVEL_Pos            (8U)
+#define QUADSPI_SR_FLEVEL_Msk            (0x3FUL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00003F00 */
+#define QUADSPI_SR_FLEVEL                QUADSPI_SR_FLEVEL_Msk                 /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_FLEVEL_0              (0x01UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000100 */
+#define QUADSPI_SR_FLEVEL_1              (0x02UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000200 */
+#define QUADSPI_SR_FLEVEL_2              (0x04UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000400 */
+#define QUADSPI_SR_FLEVEL_3              (0x08UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000800 */
+#define QUADSPI_SR_FLEVEL_4              (0x10UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00001000 */
+#define QUADSPI_SR_FLEVEL_5              (0x20UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00002000 */
+
+/******************  Bit definition for QUADSPI_FCR register  ******************/
+#define QUADSPI_FCR_CTEF_Pos             (0U)
+#define QUADSPI_FCR_CTEF_Msk             (0x1UL << QUADSPI_FCR_CTEF_Pos)       /*!< 0x00000001 */
+#define QUADSPI_FCR_CTEF                 QUADSPI_FCR_CTEF_Msk                  /*!< Clear Transfer Error Flag */
+#define QUADSPI_FCR_CTCF_Pos             (1U)
+#define QUADSPI_FCR_CTCF_Msk             (0x1UL << QUADSPI_FCR_CTCF_Pos)       /*!< 0x00000002 */
+#define QUADSPI_FCR_CTCF                 QUADSPI_FCR_CTCF_Msk                  /*!< Clear Transfer Complete Flag */
+#define QUADSPI_FCR_CSMF_Pos             (3U)
+#define QUADSPI_FCR_CSMF_Msk             (0x1UL << QUADSPI_FCR_CSMF_Pos)       /*!< 0x00000008 */
+#define QUADSPI_FCR_CSMF                 QUADSPI_FCR_CSMF_Msk                  /*!< Clear Status Match Flag */
+#define QUADSPI_FCR_CTOF_Pos             (4U)
+#define QUADSPI_FCR_CTOF_Msk             (0x1UL << QUADSPI_FCR_CTOF_Pos)       /*!< 0x00000010 */
+#define QUADSPI_FCR_CTOF                 QUADSPI_FCR_CTOF_Msk                  /*!< Clear Timeout Flag */
+
+/******************  Bit definition for QUADSPI_DLR register  ******************/
+#define QUADSPI_DLR_DL_Pos               (0U)
+#define QUADSPI_DLR_DL_Msk               (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)  /*!< 0xFFFFFFFF */
+#define QUADSPI_DLR_DL                   QUADSPI_DLR_DL_Msk                    /*!< DL[31:0]: Data Length */
+
+/******************  Bit definition for QUADSPI_CCR register  ******************/
+#define QUADSPI_CCR_INSTRUCTION_Pos      (0U)
+#define QUADSPI_CCR_INSTRUCTION_Msk      (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
+#define QUADSPI_CCR_INSTRUCTION          QUADSPI_CCR_INSTRUCTION_Msk             /*!< INSTRUCTION[7:0]: Instruction */
+#define QUADSPI_CCR_INSTRUCTION_0        (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */
+#define QUADSPI_CCR_INSTRUCTION_1        (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */
+#define QUADSPI_CCR_INSTRUCTION_2        (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */
+#define QUADSPI_CCR_INSTRUCTION_3        (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */
+#define QUADSPI_CCR_INSTRUCTION_4        (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */
+#define QUADSPI_CCR_INSTRUCTION_5        (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */
+#define QUADSPI_CCR_INSTRUCTION_6        (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */
+#define QUADSPI_CCR_INSTRUCTION_7        (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */
+#define QUADSPI_CCR_IMODE_Pos            (8U)
+#define QUADSPI_CCR_IMODE_Msk            (0x3UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000300 */
+#define QUADSPI_CCR_IMODE                QUADSPI_CCR_IMODE_Msk                   /*!< IMODE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_IMODE_0              (0x1UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000100 */
+#define QUADSPI_CCR_IMODE_1              (0x2UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000200 */
+#define QUADSPI_CCR_ADMODE_Pos           (10U)
+#define QUADSPI_CCR_ADMODE_Msk           (0x3UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000C00 */
+#define QUADSPI_CCR_ADMODE               QUADSPI_CCR_ADMODE_Msk                  /*!< ADMODE[1:0]: Address Mode */
+#define QUADSPI_CCR_ADMODE_0             (0x1UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000400 */
+#define QUADSPI_CCR_ADMODE_1             (0x2UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000800 */
+#define QUADSPI_CCR_ADSIZE_Pos           (12U)
+#define QUADSPI_CCR_ADSIZE_Msk           (0x3UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00003000 */
+#define QUADSPI_CCR_ADSIZE               QUADSPI_CCR_ADSIZE_Msk                  /*!< ADSIZE[1:0]: Address Size */
+#define QUADSPI_CCR_ADSIZE_0             (0x1UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00001000 */
+#define QUADSPI_CCR_ADSIZE_1             (0x2UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00002000 */
+#define QUADSPI_CCR_ABMODE_Pos           (14U)
+#define QUADSPI_CCR_ABMODE_Msk           (0x3UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x0000C000 */
+#define QUADSPI_CCR_ABMODE               QUADSPI_CCR_ABMODE_Msk                  /*!< ABMODE[1:0]: Alternate Bytes Mode */
+#define QUADSPI_CCR_ABMODE_0             (0x1UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00004000 */
+#define QUADSPI_CCR_ABMODE_1             (0x2UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00008000 */
+#define QUADSPI_CCR_ABSIZE_Pos           (16U)
+#define QUADSPI_CCR_ABSIZE_Msk           (0x3UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00030000 */
+#define QUADSPI_CCR_ABSIZE               QUADSPI_CCR_ABSIZE_Msk                  /*!< ABSIZE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_ABSIZE_0             (0x1UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00010000 */
+#define QUADSPI_CCR_ABSIZE_1             (0x2UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00020000 */
+#define QUADSPI_CCR_DCYC_Pos             (18U)
+#define QUADSPI_CCR_DCYC_Msk             (0x1FUL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x007C0000 */
+#define QUADSPI_CCR_DCYC                 QUADSPI_CCR_DCYC_Msk                    /*!< DCYC[4:0]: Dummy Cycles */
+#define QUADSPI_CCR_DCYC_0               (0x01UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00040000 */
+#define QUADSPI_CCR_DCYC_1               (0x02UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00080000 */
+#define QUADSPI_CCR_DCYC_2               (0x04UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00100000 */
+#define QUADSPI_CCR_DCYC_3               (0x08UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00200000 */
+#define QUADSPI_CCR_DCYC_4               (0x10UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00400000 */
+#define QUADSPI_CCR_DMODE_Pos            (24U)
+#define QUADSPI_CCR_DMODE_Msk            (0x3UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x03000000 */
+#define QUADSPI_CCR_DMODE                QUADSPI_CCR_DMODE_Msk                   /*!< DMODE[1:0]: Data Mode */
+#define QUADSPI_CCR_DMODE_0              (0x1UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x01000000 */
+#define QUADSPI_CCR_DMODE_1              (0x2UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x02000000 */
+#define QUADSPI_CCR_FMODE_Pos            (26U)
+#define QUADSPI_CCR_FMODE_Msk            (0x3UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x0C000000 */
+#define QUADSPI_CCR_FMODE                QUADSPI_CCR_FMODE_Msk                   /*!< FMODE[1:0]: Functional Mode */
+#define QUADSPI_CCR_FMODE_0              (0x1UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x04000000 */
+#define QUADSPI_CCR_FMODE_1              (0x2UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x08000000 */
+#define QUADSPI_CCR_SIOO_Pos             (28U)
+#define QUADSPI_CCR_SIOO_Msk             (0x1UL << QUADSPI_CCR_SIOO_Pos)         /*!< 0x10000000 */
+#define QUADSPI_CCR_SIOO                 QUADSPI_CCR_SIOO_Msk                    /*!< SIOO: Send Instruction Only Once Mode */
+#define QUADSPI_CCR_DHHC_Pos             (30U)
+#define QUADSPI_CCR_DHHC_Msk             (0x1UL << QUADSPI_CCR_DHHC_Pos)         /*!< 0x40000000 */
+#define QUADSPI_CCR_DHHC                 QUADSPI_CCR_DHHC_Msk                    /*!< DHHC: DDR hold half cycle */
+#define QUADSPI_CCR_DDRM_Pos             (31U)
+#define QUADSPI_CCR_DDRM_Msk             (0x1UL << QUADSPI_CCR_DDRM_Pos)         /*!< 0x80000000 */
+#define QUADSPI_CCR_DDRM                 QUADSPI_CCR_DDRM_Msk                    /*!< DDRM: Double Data Rate Mode */
+
+/******************  Bit definition for QUADSPI_AR register  *******************/
+#define QUADSPI_AR_ADDRESS_Pos           (0U)
+#define QUADSPI_AR_ADDRESS_Msk           (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_AR_ADDRESS               QUADSPI_AR_ADDRESS_Msk                /*!< ADDRESS[31:0]: Address */
+
+/******************  Bit definition for QUADSPI_ABR register  ******************/
+#define QUADSPI_ABR_ALTERNATE_Pos        (0U)
+#define QUADSPI_ABR_ALTERNATE_Msk        (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_ABR_ALTERNATE            QUADSPI_ABR_ALTERNATE_Msk             /*!< ALTERNATE[31:0]: Alternate Bytes */
+
+/******************  Bit definition for QUADSPI_DR register  *******************/
+#define QUADSPI_DR_DATA_Pos              (0U)
+#define QUADSPI_DR_DATA_Msk              (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_DR_DATA                  QUADSPI_DR_DATA_Msk                   /*!< DATA[31:0]: Data */
+
+/******************  Bit definition for QUADSPI_PSMKR register  ****************/
+#define QUADSPI_PSMKR_MASK_Pos           (0U)
+#define QUADSPI_PSMKR_MASK_Msk           (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_PSMKR_MASK               QUADSPI_PSMKR_MASK_Msk                /*!< MASK[31:0]: Status Mask */
+
+/******************  Bit definition for QUADSPI_PSMAR register  ****************/
+#define QUADSPI_PSMAR_MATCH_Pos          (0U)
+#define QUADSPI_PSMAR_MATCH_Msk          (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_PSMAR_MATCH              QUADSPI_PSMAR_MATCH_Msk               /*!< MATCH[31:0]: Status Match */
+
+/******************  Bit definition for QUADSPI_PIR register  *****************/
+#define QUADSPI_PIR_INTERVAL_Pos         (0U)
+#define QUADSPI_PIR_INTERVAL_Msk         (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
+#define QUADSPI_PIR_INTERVAL             QUADSPI_PIR_INTERVAL_Msk              /*!< INTERVAL[15:0]: Polling Interval */
+
+/******************  Bit definition for QUADSPI_LPTR register  *****************/
+#define QUADSPI_LPTR_TIMEOUT_Pos         (0U)
+#define QUADSPI_LPTR_TIMEOUT_Msk         (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
+#define QUADSPI_LPTR_TIMEOUT             QUADSPI_LPTR_TIMEOUT_Msk              /*!< TIMEOUT[15:0]: Timeout period */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 SYSCFG                                     */
+/*                                                                            */
+/******************************************************************************/
+
+/******************  Bit definition for SYSCFG_PMCR register  ******************/
+#define SYSCFG_PMCR_I2C1_FMP_Pos        (0U)
+#define SYSCFG_PMCR_I2C1_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C1_FMP_Pos)    /*!< 0x00000001 */
+#define SYSCFG_PMCR_I2C1_FMP            SYSCFG_PMCR_I2C1_FMP_Msk               /*!< I2C1 Fast mode plus */
+#define SYSCFG_PMCR_I2C2_FMP_Pos        (1U)
+#define SYSCFG_PMCR_I2C2_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C2_FMP_Pos)    /*!< 0x00000002 */
+#define SYSCFG_PMCR_I2C2_FMP            SYSCFG_PMCR_I2C2_FMP_Msk               /*!< I2C2 Fast mode plus */
+#define SYSCFG_PMCR_I2C3_FMP_Pos        (2U)
+#define SYSCFG_PMCR_I2C3_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C3_FMP_Pos)    /*!< 0x00000004 */
+#define SYSCFG_PMCR_I2C3_FMP            SYSCFG_PMCR_I2C3_FMP_Msk               /*!< I2C3 Fast mode plus */
+#define SYSCFG_PMCR_I2C4_FMP_Pos        (3U)
+#define SYSCFG_PMCR_I2C4_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C4_FMP_Pos)    /*!< 0x00000008 */
+#define SYSCFG_PMCR_I2C4_FMP            SYSCFG_PMCR_I2C4_FMP_Msk               /*!< I2C4 Fast mode plus */
+#define SYSCFG_PMCR_I2C_PB6_FMP_Pos     (4U)
+#define SYSCFG_PMCR_I2C_PB6_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB6_FMP_Pos) /*!< 0x00000010 */
+#define SYSCFG_PMCR_I2C_PB6_FMP         SYSCFG_PMCR_I2C_PB6_FMP_Msk            /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_PMCR_I2C_PB7_FMP_Pos     (5U)
+#define SYSCFG_PMCR_I2C_PB7_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB7_FMP_Pos) /*!< 0x00000020 */
+#define SYSCFG_PMCR_I2C_PB7_FMP         SYSCFG_PMCR_I2C_PB7_FMP_Msk            /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_PMCR_I2C_PB8_FMP_Pos     (6U)
+#define SYSCFG_PMCR_I2C_PB8_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB8_FMP_Pos) /*!< 0x00000040 */
+#define SYSCFG_PMCR_I2C_PB8_FMP         SYSCFG_PMCR_I2C_PB8_FMP_Msk            /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_PMCR_I2C_PB9_FMP_Pos     (7U)
+#define SYSCFG_PMCR_I2C_PB9_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB9_FMP_Pos) /*!< 0x00000080 */
+#define SYSCFG_PMCR_I2C_PB9_FMP         SYSCFG_PMCR_I2C_PB9_FMP_Msk            /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_PMCR_BOOSTEN_Pos         (8U)
+#define SYSCFG_PMCR_BOOSTEN_Msk         (0x1UL << SYSCFG_PMCR_BOOSTEN_Pos)     /*!< 0x00000100 */
+#define SYSCFG_PMCR_BOOSTEN             SYSCFG_PMCR_BOOSTEN_Msk                /*!< I/O analog switch voltage booster enable */
+
+#define SYSCFG_PMCR_BOOSTVDDSEL_Pos     (9U)
+#define SYSCFG_PMCR_BOOSTVDDSEL_Msk     (0x1UL << SYSCFG_PMCR_BOOSTVDDSEL_Pos) /*!< 0x00000200 */
+#define SYSCFG_PMCR_BOOSTVDDSEL         SYSCFG_PMCR_BOOSTVDDSEL_Msk            /*!< Analog switch supply source selection : VDD/VDDA */
+
+#define SYSCFG_PMCR_EPIS_SEL_Pos        (21U)
+#define SYSCFG_PMCR_EPIS_SEL_Msk        (0x7UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00E00000 */
+#define SYSCFG_PMCR_EPIS_SEL            SYSCFG_PMCR_EPIS_SEL_Msk               /*!< Ethernet PHY Interface Selection */
+#define SYSCFG_PMCR_EPIS_SEL_0          (0x1UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00200000 */
+#define SYSCFG_PMCR_EPIS_SEL_1          (0x2UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00400000 */
+#define SYSCFG_PMCR_EPIS_SEL_2          (0x4UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00800000 */
+#define SYSCFG_PMCR_PA0SO_Pos           (24U)
+#define SYSCFG_PMCR_PA0SO_Msk           (0x1UL << SYSCFG_PMCR_PA0SO_Pos)       /*!< 0x01000000 */
+#define SYSCFG_PMCR_PA0SO               SYSCFG_PMCR_PA0SO_Msk                  /*!< PA0 Switch Open */
+#define SYSCFG_PMCR_PA1SO_Pos           (25U)
+#define SYSCFG_PMCR_PA1SO_Msk           (0x1UL << SYSCFG_PMCR_PA1SO_Pos)       /*!< 0x02000000 */
+#define SYSCFG_PMCR_PA1SO               SYSCFG_PMCR_PA1SO_Msk                  /*!< PA1 Switch Open */
+#define SYSCFG_PMCR_PC2SO_Pos           (26U)
+#define SYSCFG_PMCR_PC2SO_Msk           (0x1UL << SYSCFG_PMCR_PC2SO_Pos)       /*!< 0x04000000 */
+#define SYSCFG_PMCR_PC2SO               SYSCFG_PMCR_PC2SO_Msk                  /*!< PC2 Switch Open */
+#define SYSCFG_PMCR_PC3SO_Pos           (27U)
+#define SYSCFG_PMCR_PC3SO_Msk           (0x1UL << SYSCFG_PMCR_PC3SO_Pos)       /*!< 0x08000000 */
+#define SYSCFG_PMCR_PC3SO               SYSCFG_PMCR_PC3SO_Msk                  /*!< PC3 Switch Open */
+
+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)
+#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)    /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)
+#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)    /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)
+#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)    /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)
+#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)    /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */
+/**
+  * @brief   EXTI0 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000)                 /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001)                 /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002)                 /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003)                 /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004)                 /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x00000005)                 /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x00000006)                 /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000007)                 /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI         ((uint32_t)0x00000008)                 /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x00000009)                 /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x0000000A)                 /*!<PK[0] pin */
+
+/**
+  * @brief   EXTI1 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000)                 /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010)                 /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020)                 /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030)                 /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040)                 /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x00000050)                 /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x00000060)                 /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000070)                 /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI         ((uint32_t)0x00000080)                 /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x00000090)                 /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x000000A0)                 /*!<PK[1] pin */
+/**
+  * @brief   EXTI2 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000)                 /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100)                 /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200)                 /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300)                 /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400)                 /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x00000500)                 /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x00000600)                 /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x00000700)                 /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI         ((uint32_t)0x00000800)                 /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x00000900)                 /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x00000A00)                 /*!<PK[2] pin */
+
+/**
+  * @brief   EXTI3 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000)                 /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000)                 /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000)                 /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000)                 /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000)                 /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x00005000)                 /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x00006000)                 /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x00007000)                 /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI         ((uint32_t)0x00008000)                 /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x00009000)                 /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0x0000A000)                 /*!<PK[3] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
+#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)
+#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)    /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)
+#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)    /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)
+#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)    /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)
+#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)    /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */
+/**
+  * @brief   EXTI4 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000)                 /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001)                 /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002)                 /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003)                 /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004)                 /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x00000005)                 /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x00000006)                 /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x00000007)                 /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI         ((uint32_t)0x00000008)                 /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x00000009)                 /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x0000000A)                 /*!<PK[4] pin */
+/**
+  * @brief   EXTI5 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000)                 /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010)                 /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020)                 /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030)                 /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040)                 /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x00000050)                 /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x00000060)                 /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x00000070)                 /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI         ((uint32_t)0x00000080)                 /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x00000090)                 /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x000000A0)                 /*!<PK[5] pin */
+/**
+  * @brief   EXTI6 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000)                 /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100)                 /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200)                 /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300)                 /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400)                 /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x00000500)                 /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x00000600)                 /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x00000700)                 /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI         ((uint32_t)0x00000800)                 /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x00000900)                 /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x00000A00)                 /*!<PK[6] pin */
+
+/**
+  * @brief   EXTI7 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000)                 /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000)                 /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000)                 /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000)                 /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000)                 /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x00005000)                 /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x00006000)                 /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x00007000)                 /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI         ((uint32_t)0x00008000)                 /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x00009000)                 /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0x0000A000)                 /*!<PK[7] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
+#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)
+#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)    /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)
+#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)    /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)
+#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)   /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)
+#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)   /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */
+
+/**
+  * @brief   EXTI8 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000)                 /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001)                 /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002)                 /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003)                 /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004)                 /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x00000005)                 /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x00000006)                 /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x00000007)                 /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI         ((uint32_t)0x00000008)                 /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x00000009)                 /*!<PJ[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PK         ((uint32_t)0x0000000A)                 /*!<PK[8] pin */
+
+/**
+  * @brief   EXTI9 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000)                 /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010)                 /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020)                 /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030)                 /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040)                 /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x00000050)                 /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x00000060)                 /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x00000070)                 /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI         ((uint32_t)0x00000080)                 /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x00000090)                 /*!<PJ[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PK         ((uint32_t)0x000000A0)                 /*!<PK[9] pin */
+
+/**
+  * @brief   EXTI10 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000)                 /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100)                 /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200)                 /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300)                 /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400)                 /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x00000500)                 /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x00000600)                 /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x00000700)                 /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI        ((uint32_t)0x00000800)                 /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x00000900)                 /*!<PJ[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PK        ((uint32_t)0x00000A00)                 /*!<PK[10] pin */
+
+/**
+  * @brief   EXTI11 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000)                 /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000)                 /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000)                 /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000)                 /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000)                 /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x00005000)                 /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x00006000)                 /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x00007000)                 /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI        ((uint32_t)0x00008000)                 /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x00009000)                 /*!<PJ[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PK        ((uint32_t)0x0000A000)                 /*!<PK[11] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
+#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)
+#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)   /*!< 0x0000000F */
+#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)
+#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)   /*!< 0x000000F0 */
+#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)
+#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)   /*!< 0x00000F00 */
+#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)
+#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)   /*!< 0x0000F000 */
+#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */
+/**
+  * @brief   EXTI12 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000)                 /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001)                 /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002)                 /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003)                 /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004)                 /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x00000005)                 /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x00000006)                 /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x00000007)                 /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI        ((uint32_t)0x00000008)                 /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x00000009)                 /*!<PJ[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PK        ((uint32_t)0x0000000A)                 /*!<PK[12] pin */
+/**
+  * @brief   EXTI13 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000)                 /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010)                 /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020)                 /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030)                 /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040)                 /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x00000050)                 /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x00000060)                 /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x00000070)                 /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI        ((uint32_t)0x00000080)                 /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x00000090)                 /*!<PJ[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PK        ((uint32_t)0x000000A0)                 /*!<PK[13] pin */
+/**
+  * @brief   EXTI14 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000)                 /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100)                 /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200)                 /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300)                 /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400)                 /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x00000500)                 /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x00000600)                 /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x00000700)                 /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI        ((uint32_t)0x00000800)                 /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x00000900)                 /*!<PJ[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PK        ((uint32_t)0x00000A00)                 /*!<PK[14] pin */
+/**
+  * @brief   EXTI15 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000)                 /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000)                 /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000)                 /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000)                 /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000)                 /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x00005000)                 /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x00006000)                 /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x00007000)                 /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI        ((uint32_t)0x00008000)                 /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x00009000)                 /*!<PJ[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PK        ((uint32_t)0x0000A000)                 /*!<PK[15] pin */
+
+/******************  Bit definition for SYSCFG_CFGR register  ******************/
+#define SYSCFG_CFGR_PVDL_Pos            (2U)
+#define SYSCFG_CFGR_PVDL_Msk            (0x1UL << SYSCFG_CFGR_PVDL_Pos)        /*!< 0x00000004 */
+#define SYSCFG_CFGR_PVDL                SYSCFG_CFGR_PVDL_Msk                   /*!<PVD lock enable bit */
+#define SYSCFG_CFGR_FLASHL_Pos          (3U)
+#define SYSCFG_CFGR_FLASHL_Msk          (0x1UL << SYSCFG_CFGR_FLASHL_Pos)      /*!< 0x00000008 */
+#define SYSCFG_CFGR_FLASHL              SYSCFG_CFGR_FLASHL_Msk                 /*!<FLASH double ECC error lock bit */
+#define SYSCFG_CFGR_CM7L_Pos            (6U)
+#define SYSCFG_CFGR_CM7L_Msk            (0x1UL << SYSCFG_CFGR_CM7L_Pos)        /*!< 0x00000040 */
+#define SYSCFG_CFGR_CM7L                SYSCFG_CFGR_CM7L_Msk                   /*!<Cortex-M7 LOCKUP (Hardfault) output enable bit */
+#define SYSCFG_CFGR_BKRAML_Pos          (7U)
+#define SYSCFG_CFGR_BKRAML_Msk          (0x1UL << SYSCFG_CFGR_BKRAML_Pos)      /*!< 0x00000080 */
+#define SYSCFG_CFGR_BKRAML              SYSCFG_CFGR_BKRAML_Msk                 /*!<Backup SRAM double ECC error lock bit */
+#define SYSCFG_CFGR_SRAM4L_Pos          (9U)
+#define SYSCFG_CFGR_SRAM4L_Msk          (0x1UL << SYSCFG_CFGR_SRAM4L_Pos)      /*!< 0x00000200 */
+#define SYSCFG_CFGR_SRAM4L              SYSCFG_CFGR_SRAM4L_Msk                 /*!<SRAM4 double ECC error lock bit */
+#define SYSCFG_CFGR_SRAM3L_Pos          (10U)
+#define SYSCFG_CFGR_SRAM3L_Msk          (0x1UL << SYSCFG_CFGR_SRAM3L_Pos)      /*!< 0x00000400 */
+#define SYSCFG_CFGR_SRAM3L              SYSCFG_CFGR_SRAM3L_Msk                 /*!<SRAM3 double ECC error lock bit */
+#define SYSCFG_CFGR_SRAM2L_Pos          (11U)
+#define SYSCFG_CFGR_SRAM2L_Msk          (0x1UL << SYSCFG_CFGR_SRAM2L_Pos)      /*!< 0x00000800 */
+#define SYSCFG_CFGR_SRAM2L              SYSCFG_CFGR_SRAM2L_Msk                 /*!<SRAM2 double ECC error lock bit */
+#define SYSCFG_CFGR_SRAM1L_Pos          (12U)
+#define SYSCFG_CFGR_SRAM1L_Msk          (0x1UL << SYSCFG_CFGR_SRAM1L_Pos)      /*!< 0x00001000 */
+#define SYSCFG_CFGR_SRAM1L              SYSCFG_CFGR_SRAM1L_Msk                 /*!<SRAM1 double ECC error lock bit */
+#define SYSCFG_CFGR_DTCML_Pos           (13U)
+#define SYSCFG_CFGR_DTCML_Msk           (0x1UL << SYSCFG_CFGR_DTCML_Pos)       /*!< 0x00002000 */
+#define SYSCFG_CFGR_DTCML               SYSCFG_CFGR_DTCML_Msk                  /*!<DTCM double ECC error lock bit */
+#define SYSCFG_CFGR_ITCML_Pos           (14U)
+#define SYSCFG_CFGR_ITCML_Msk           (0x1UL << SYSCFG_CFGR_ITCML_Pos)       /*!< 0x00004000 */
+#define SYSCFG_CFGR_ITCML               SYSCFG_CFGR_ITCML_Msk                  /*!<ITCM double ECC error lock bit */
+#define SYSCFG_CFGR_AXISRAML_Pos        (15U)
+#define SYSCFG_CFGR_AXISRAML_Msk        (0x1UL << SYSCFG_CFGR_AXISRAML_Pos)    /*!< 0x00008000 */
+#define SYSCFG_CFGR_AXISRAML            SYSCFG_CFGR_AXISRAML_Msk               /*!<AXISRAM double ECC error lock bit */
+
+/******************  Bit definition for SYSCFG_CCCSR register  ******************/
+#define SYSCFG_CCCSR_EN_Pos             (0U)
+#define SYSCFG_CCCSR_EN_Msk             (0x1UL << SYSCFG_CCCSR_EN_Pos)         /*!< 0x00000001 */
+#define SYSCFG_CCCSR_EN                 SYSCFG_CCCSR_EN_Msk                    /*!< I/O compensation cell enable */
+#define SYSCFG_CCCSR_CS_Pos             (1U)
+#define SYSCFG_CCCSR_CS_Msk             (0x1UL << SYSCFG_CCCSR_CS_Pos)         /*!< 0x00000002 */
+#define SYSCFG_CCCSR_CS                 SYSCFG_CCCSR_CS_Msk                    /*!< I/O compensation cell code selection */
+#define SYSCFG_CCCSR_READY_Pos          (8U)
+#define SYSCFG_CCCSR_READY_Msk          (0x1UL << SYSCFG_CCCSR_READY_Pos)      /*!< 0x00000100 */
+#define SYSCFG_CCCSR_READY              SYSCFG_CCCSR_READY_Msk                 /*!< I/O compensation cell ready flag */
+#define SYSCFG_CCCSR_HSLV_Pos           (16U)
+#define SYSCFG_CCCSR_HSLV_Msk           (0x1UL << SYSCFG_CCCSR_HSLV_Pos)       /*!< 0x00010000 */
+#define SYSCFG_CCCSR_HSLV               SYSCFG_CCCSR_HSLV_Msk                  /*!< High-speed at low-voltage */
+
+/******************  Bit definition for SYSCFG_CCVR register  *******************/
+#define SYSCFG_CCVR_NCV_Pos             (0U)
+#define SYSCFG_CCVR_NCV_Msk             (0xFUL << SYSCFG_CCVR_NCV_Pos)         /*!< 0x0000000F */
+#define SYSCFG_CCVR_NCV                 SYSCFG_CCVR_NCV_Msk                    /*!< NMOS compensation value */
+#define SYSCFG_CCVR_PCV_Pos             (4U)
+#define SYSCFG_CCVR_PCV_Msk             (0xFUL << SYSCFG_CCVR_PCV_Pos)         /*!< 0x000000F0 */
+#define SYSCFG_CCVR_PCV                 SYSCFG_CCVR_PCV_Msk                    /*!< PMOS compensation value */
+
+/******************  Bit definition for SYSCFG_CCCR register  *******************/
+#define SYSCFG_CCCR_NCC_Pos             (0U)
+#define SYSCFG_CCCR_NCC_Msk             (0xFUL << SYSCFG_CCCR_NCC_Pos)         /*!< 0x0000000F */
+#define SYSCFG_CCCR_NCC                 SYSCFG_CCCR_NCC_Msk                    /*!< NMOS compensation code */
+#define SYSCFG_CCCR_PCC_Pos             (4U)
+#define SYSCFG_CCCR_PCC_Msk             (0xFUL << SYSCFG_CCCR_PCC_Pos)         /*!< 0x000000F0 */
+#define SYSCFG_CCCR_PCC                 SYSCFG_CCCR_PCC_Msk                    /*!< PMOS compensation code */
+/******************  Bit definition for SYSCFG_PWRCR register  *******************/
+#define SYSCFG_PWRCR_ODEN_Pos           (0U)
+#define SYSCFG_PWRCR_ODEN_Msk           (0x1UL << SYSCFG_PWRCR_ODEN_Pos)         /*!< 0x00000001 */
+#define SYSCFG_PWRCR_ODEN               SYSCFG_PWRCR_ODEN_Msk                    /*!< PWR overdrive enable */
+
+/******************  Bit definition for SYSCFG_PKGR register  *******************/
+#define SYSCFG_PKGR_PKG_Pos             (0U)
+#define SYSCFG_PKGR_PKG_Msk             (0xFUL << SYSCFG_PKGR_PKG_Pos)         /*!< 0x0000000F */
+#define SYSCFG_PKGR_PKG                 SYSCFG_PKGR_PKG_Msk                    /*!< Package type */
+
+/******************  Bit definition for SYSCFG_UR0 register  *******************/
+#define SYSCFG_UR0_BKS_Pos              (0U)
+#define SYSCFG_UR0_BKS_Msk              (0x1UL << SYSCFG_UR0_BKS_Pos)          /*!< 0x00000001 */
+#define SYSCFG_UR0_BKS                  SYSCFG_UR0_BKS_Msk                     /*!< Bank Swap */
+#define SYSCFG_UR0_RDP_Pos              (16U)
+#define SYSCFG_UR0_RDP_Msk              (0xFFUL << SYSCFG_UR0_RDP_Pos)         /*!< 0x00FF0000 */
+#define SYSCFG_UR0_RDP                  SYSCFG_UR0_RDP_Msk                     /*!< Readout protection */
+
+/******************  Bit definition for SYSCFG_UR2 register  *******************/
+#define SYSCFG_UR2_BORH_Pos             (0U)
+#define SYSCFG_UR2_BORH_Msk             (0x3UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000003 */
+#define SYSCFG_UR2_BORH                 SYSCFG_UR2_BORH_Msk                    /*!< Brown Out Reset High level */
+#define SYSCFG_UR2_BORH_0               (0x1UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000001 */
+#define SYSCFG_UR2_BORH_1               (0x2UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000002 */
+#define SYSCFG_UR2_BOOT_ADD0_Pos        (16U)
+#define SYSCFG_UR2_BOOT_ADD0_Msk        (0xFFFFUL << SYSCFG_UR2_BOOT_ADD0_Pos) /*!< 0xFFFF0000 */
+#define SYSCFG_UR2_BOOT_ADD0            SYSCFG_UR2_BOOT_ADD0_Msk               /*!< Core Boot Address 0 */
+/******************  Bit definition for SYSCFG_UR3 register  *******************/
+#define SYSCFG_UR3_BOOT_ADD1_Pos        (0U)
+#define SYSCFG_UR3_BOOT_ADD1_Msk        (0xFFFFUL << SYSCFG_UR3_BOOT_ADD1_Pos) /*!< 0x0000FFFF */
+#define SYSCFG_UR3_BOOT_ADD1            SYSCFG_UR3_BOOT_ADD1_Msk               /*!< Core Boot Address 1 */
+
+  /******************  Bit definition for SYSCFG_UR4 register  *******************/
+
+#define SYSCFG_UR4_MEPAD_BANK1_Pos      (16U)
+#define SYSCFG_UR4_MEPAD_BANK1_Msk      (0x1UL << SYSCFG_UR4_MEPAD_BANK1_Pos)  /*!< 0x00010000 */
+#define SYSCFG_UR4_MEPAD_BANK1          SYSCFG_UR4_MEPAD_BANK1_Msk             /*!< Mass Erase Protected Area Disabled for bank 1 */
+
+/******************  Bit definition for SYSCFG_UR5 register  *******************/
+#define SYSCFG_UR5_MESAD_BANK1_Pos      (0U)
+#define SYSCFG_UR5_MESAD_BANK1_Msk      (0x1UL << SYSCFG_UR5_MESAD_BANK1_Pos)  /*!< 0x00000001 */
+#define SYSCFG_UR5_MESAD_BANK1          SYSCFG_UR5_MESAD_BANK1_Msk             /*!< Mass erase secured area disabled for bank 1 */
+#define SYSCFG_UR5_WRPN_BANK1_Pos       (16U)
+#define SYSCFG_UR5_WRPN_BANK1_Msk       (0xFFUL << SYSCFG_UR5_WRPN_BANK1_Pos)  /*!< 0x00FF0000 */
+#define SYSCFG_UR5_WRPN_BANK1           SYSCFG_UR5_WRPN_BANK1_Msk              /*!< Write protection for flash bank 1 */
+
+/******************  Bit definition for SYSCFG_UR6 register  *******************/
+#define SYSCFG_UR6_PABEG_BANK1_Pos      (0U)
+#define SYSCFG_UR6_PABEG_BANK1_Msk      (0xFFFUL << SYSCFG_UR6_PABEG_BANK1_Pos) /*!< 0x00000FFF */
+#define SYSCFG_UR6_PABEG_BANK1          SYSCFG_UR6_PABEG_BANK1_Msk             /*!< Protected area start address for bank 1 */
+#define SYSCFG_UR6_PAEND_BANK1_Pos      (16U)
+#define SYSCFG_UR6_PAEND_BANK1_Msk      (0xFFFUL << SYSCFG_UR6_PAEND_BANK1_Pos) /*!< 0x0FFF0000 */
+#define SYSCFG_UR6_PAEND_BANK1          SYSCFG_UR6_PAEND_BANK1_Msk             /*!< Protected area end address for bank 1 */
+
+/******************  Bit definition for SYSCFG_UR7 register  *******************/
+#define SYSCFG_UR7_SABEG_BANK1_Pos      (0U)
+#define SYSCFG_UR7_SABEG_BANK1_Msk      (0xFFFUL << SYSCFG_UR7_SABEG_BANK1_Pos) /*!< 0x00000FFF */
+#define SYSCFG_UR7_SABEG_BANK1          SYSCFG_UR7_SABEG_BANK1_Msk             /*!< Secured area start address for bank 1 */
+#define SYSCFG_UR7_SAEND_BANK1_Pos      (16U)
+#define SYSCFG_UR7_SAEND_BANK1_Msk      (0xFFFUL << SYSCFG_UR7_SAEND_BANK1_Pos) /*!< 0x0FFF0000 */
+#define SYSCFG_UR7_SAEND_BANK1          SYSCFG_UR7_SAEND_BANK1_Msk             /*!< Secured area end address for bank 1 */
+
+/******************  Bit definition for SYSCFG_UR8 register  *******************/
+#define SYSCFG_UR8_MEPAD_BANK2_Pos      (0U)
+#define SYSCFG_UR8_MEPAD_BANK2_Msk      (0x1UL << SYSCFG_UR8_MEPAD_BANK2_Pos)  /*!< 0x00000001 */
+#define SYSCFG_UR8_MEPAD_BANK2          SYSCFG_UR8_MEPAD_BANK2_Msk             /*!< Mass erase Protected area disabled for bank 2 */
+#define SYSCFG_UR8_MESAD_BANK2_Pos      (16U)
+#define SYSCFG_UR8_MESAD_BANK2_Msk      (0x1UL << SYSCFG_UR8_MESAD_BANK2_Pos)  /*!< 0x00010000 */
+#define SYSCFG_UR8_MESAD_BANK2          SYSCFG_UR8_MESAD_BANK2_Msk             /*!< Mass Erase Secured Area Disabled for bank 2 */
+
+/******************  Bit definition for SYSCFG_UR9 register  *******************/
+#define SYSCFG_UR9_WRPN_BANK2_Pos       (0U)
+#define SYSCFG_UR9_WRPN_BANK2_Msk       (0xFFUL << SYSCFG_UR9_WRPN_BANK2_Pos)  /*!< 0x000000FF */
+#define SYSCFG_UR9_WRPN_BANK2           SYSCFG_UR9_WRPN_BANK2_Msk              /*!< Write protection for flash bank 2 */
+#define SYSCFG_UR9_PABEG_BANK2_Pos      (16U)
+#define SYSCFG_UR9_PABEG_BANK2_Msk      (0xFFFUL << SYSCFG_UR9_PABEG_BANK2_Pos) /*!< 0x0FFF0000 */
+#define SYSCFG_UR9_PABEG_BANK2          SYSCFG_UR9_PABEG_BANK2_Msk             /*!< Protected area start address for bank 2 */
+
+/******************  Bit definition for SYSCFG_UR10 register  *******************/
+#define SYSCFG_UR10_PAEND_BANK2_Pos     (0U)
+#define SYSCFG_UR10_PAEND_BANK2_Msk     (0xFFFUL << SYSCFG_UR10_PAEND_BANK2_Pos) /*!< 0x00000FFF */
+#define SYSCFG_UR10_PAEND_BANK2         SYSCFG_UR10_PAEND_BANK2_Msk            /*!< Protected area end address for bank 2 */
+#define SYSCFG_UR10_SABEG_BANK2_Pos     (16U)
+#define SYSCFG_UR10_SABEG_BANK2_Msk     (0xFFFUL << SYSCFG_UR10_SABEG_BANK2_Pos) /*!< 0x0FFF0000 */
+#define SYSCFG_UR10_SABEG_BANK2         SYSCFG_UR10_SABEG_BANK2_Msk            /*!< Secured area start address for bank 2 */
+
+/******************  Bit definition for SYSCFG_UR11 register  *******************/
+#define SYSCFG_UR11_SAEND_BANK2_Pos     (0U)
+#define SYSCFG_UR11_SAEND_BANK2_Msk     (0xFFFUL << SYSCFG_UR11_SAEND_BANK2_Pos) /*!< 0x00000FFF */
+#define SYSCFG_UR11_SAEND_BANK2         SYSCFG_UR11_SAEND_BANK2_Msk            /*!< Secured area end address for bank 2 */
+#define SYSCFG_UR11_IWDG1M_Pos          (16U)
+#define SYSCFG_UR11_IWDG1M_Msk          (0x1UL << SYSCFG_UR11_IWDG1M_Pos)      /*!< 0x00010000 */
+#define SYSCFG_UR11_IWDG1M              SYSCFG_UR11_IWDG1M_Msk                 /*!< Independent Watchdog 1 mode (SW or HW) */
+
+/******************  Bit definition for SYSCFG_UR12 register  *******************/
+
+#define SYSCFG_UR12_SECURE_Pos          (16U)
+#define SYSCFG_UR12_SECURE_Msk          (0x1UL << SYSCFG_UR12_SECURE_Pos)      /*!< 0x00010000 */
+#define SYSCFG_UR12_SECURE              SYSCFG_UR12_SECURE_Msk                 /*!< Secure mode status */
+
+/******************  Bit definition for SYSCFG_UR13 register  *******************/
+#define SYSCFG_UR13_SDRS_Pos            (0U)
+#define SYSCFG_UR13_SDRS_Msk            (0x3UL << SYSCFG_UR13_SDRS_Pos)        /*!< 0x00000003 */
+#define SYSCFG_UR13_SDRS                SYSCFG_UR13_SDRS_Msk                   /*!< Secured DTCM RAM Size */
+#define SYSCFG_UR13_D1SBRST_Pos         (16U)
+#define SYSCFG_UR13_D1SBRST_Msk         (0x1UL << SYSCFG_UR13_D1SBRST_Pos)     /*!< 0x00010000 */
+#define SYSCFG_UR13_D1SBRST             SYSCFG_UR13_D1SBRST_Msk                /*!< D1 Standby reset */
+
+/******************  Bit definition for SYSCFG_UR14 register  *******************/
+#define SYSCFG_UR14_D1STPRST_Pos        (0U)
+#define SYSCFG_UR14_D1STPRST_Msk        (0x1UL << SYSCFG_UR14_D1STPRST_Pos)    /*!< 0x00000001 */
+#define SYSCFG_UR14_D1STPRST            SYSCFG_UR14_D1STPRST_Msk               /*!< D1 Stop Reset */
+
+/******************  Bit definition for SYSCFG_UR15 register  *******************/
+#define SYSCFG_UR15_FZIWDGSTB_Pos       (16U)
+#define SYSCFG_UR15_FZIWDGSTB_Msk       (0x1UL << SYSCFG_UR15_FZIWDGSTB_Pos)   /*!< 0x00010000 */
+#define SYSCFG_UR15_FZIWDGSTB           SYSCFG_UR15_FZIWDGSTB_Msk              /*!< Freeze independent watchdogs in Standby mode */
+
+/******************  Bit definition for SYSCFG_UR16 register  *******************/
+#define SYSCFG_UR16_FZIWDGSTP_Pos       (0U)
+#define SYSCFG_UR16_FZIWDGSTP_Msk       (0x1UL << SYSCFG_UR16_FZIWDGSTP_Pos)   /*!< 0x00000001 */
+#define SYSCFG_UR16_FZIWDGSTP           SYSCFG_UR16_FZIWDGSTP_Msk              /*!< Freeze independent watchdogs in Stop mode */
+#define SYSCFG_UR16_PKP_Pos             (16U)
+#define SYSCFG_UR16_PKP_Msk             (0x1UL << SYSCFG_UR16_PKP_Pos)         /*!< 0x00010000 */
+#define SYSCFG_UR16_PKP                 SYSCFG_UR16_PKP_Msk                    /*!< Private key programmed */
+
+/******************  Bit definition for SYSCFG_UR17 register  *******************/
+#define SYSCFG_UR17_IOHSLV_Pos          (0U)
+#define SYSCFG_UR17_IOHSLV_Msk          (0x1UL << SYSCFG_UR17_IOHSLV_Pos)      /*!< 0x00000001 */
+#define SYSCFG_UR17_IOHSLV              SYSCFG_UR17_IOHSLV_Msk                 /*!< I/O high speed / low voltage */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    TIM                                     */
+/*                                                                            */
+/******************************************************************************/
+#define TIM_BREAK_INPUT_SUPPORT             /*!<TIM Break input feature */
+
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define TIM_CR1_CEN_Pos           (0U)
+#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */
+#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos          (1U)
+#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */
+#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
+#define TIM_CR1_URS_Pos           (2U)
+#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */
+#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
+#define TIM_CR1_OPM_Pos           (3U)
+#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */
+#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos           (4U)
+#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */
+#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
+
+#define TIM_CR1_CMS_Pos           (5U)
+#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */
+#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
+#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos          (7U)
+#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */
+#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos           (8U)
+#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */
+#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
+#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
+
+#define TIM_CR1_UIFREMAP_Pos      (11U)
+#define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */
+#define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define TIM_CR2_CCPC_Pos          (0U)
+#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */
+#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos          (2U)
+#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */
+#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos          (3U)
+#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */
+#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos           (4U)
+#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000070 */
+#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
+#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
+#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos          (7U)
+#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */
+#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos          (8U)
+#define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */
+#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos         (9U)
+#define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */
+#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos          (10U)
+#define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */
+#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos         (11U)
+#define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */
+#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos          (12U)
+#define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */
+#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos         (13U)
+#define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */
+#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos          (14U)
+#define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */
+#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
+#define TIM_CR2_OIS5_Pos          (16U)
+#define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
+#define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */
+#define TIM_CR2_OIS6_Pos          (17U)
+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00020000 */
+#define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */
+
+#define TIM_CR2_MMS2_Pos          (20U)
+#define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */
+#define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00100000 */
+#define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00200000 */
+#define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00400000 */
+#define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00800000 */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define TIM_SMCR_SMS_Pos          (0U)
+#define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */
+#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000004 */
+#define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)               /*!< 0x00010000 */
+
+#define TIM_SMCR_TS_Pos           (4U)
+#define TIM_SMCR_TS_Msk           (0x30007UL << TIM_SMCR_TS_Pos)               /*!< 0x00300070 */
+#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[4:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0             (0x00001UL << TIM_SMCR_TS_Pos)                /*!< 0x00000010 */
+#define TIM_SMCR_TS_1             (0x00002UL << TIM_SMCR_TS_Pos)                /*!< 0x00000020 */
+#define TIM_SMCR_TS_2             (0x00004UL << TIM_SMCR_TS_Pos)                /*!< 0x00000040 */
+#define TIM_SMCR_TS_3             (0x10000UL << TIM_SMCR_TS_Pos)                /*!< 0x00100000 */
+#define TIM_SMCR_TS_4             (0x20000UL << TIM_SMCR_TS_Pos)                /*!< 0x00200000 */
+
+#define TIM_SMCR_MSM_Pos          (7U)
+#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */
+#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos          (8U)
+#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */
+#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos         (12U)
+#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */
+#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos          (14U)
+#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */
+#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos          (15U)
+#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */
+#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define TIM_DIER_UIE_Pos          (0U)
+#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */
+#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos        (1U)
+#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */
+#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos        (2U)
+#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */
+#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos        (3U)
+#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */
+#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos        (4U)
+#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */
+#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos        (5U)
+#define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */
+#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos          (6U)
+#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */
+#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos          (7U)
+#define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */
+#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos          (8U)
+#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */
+#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos        (9U)
+#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */
+#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos        (10U)
+#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */
+#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos        (11U)
+#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */
+#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos        (12U)
+#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */
+#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos        (13U)
+#define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */
+#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos          (14U)
+#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */
+#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define TIM_SR_UIF_Pos            (0U)
+#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */
+#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos          (1U)
+#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */
+#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos          (2U)
+#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */
+#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos          (3U)
+#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */
+#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos          (4U)
+#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */
+#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos          (5U)
+#define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */
+#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos            (6U)
+#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */
+#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos            (7U)
+#define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */
+#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
+#define TIM_SR_B2IF_Pos           (8U)
+#define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */
+#define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break2 interrupt Flag */
+#define TIM_SR_CC1OF_Pos          (9U)
+#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */
+#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos          (10U)
+#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */
+#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos          (11U)
+#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */
+#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos          (12U)
+#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */
+#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
+#define TIM_SR_CC5IF_Pos          (16U)
+#define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */
+#define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */
+#define TIM_SR_CC6IF_Pos          (17U)
+#define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */
+#define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */
+#define TIM_SR_SBIF_Pos           (13U)
+#define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */
+#define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!< System Break Flag */
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define TIM_EGR_UG_Pos            (0U)
+#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */
+#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos          (1U)
+#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */
+#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos          (2U)
+#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */
+#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos          (3U)
+#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */
+#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos          (4U)
+#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */
+#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos          (5U)
+#define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */
+#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos            (6U)
+#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */
+#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos            (7U)
+#define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */
+#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */
+#define TIM_EGR_B2G_Pos           (8U)
+#define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */
+#define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break Generation */
+
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define TIM_CCMR1_CC1S_Pos        (0U)
+#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos       (2U)
+#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos       (3U)
+#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos        (4U)
+#define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */
+#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000040 */
+#define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010000 */
+
+#define TIM_CCMR1_OC1CE_Pos       (7U)
+#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos        (8U)
+#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos       (10U)
+#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos       (11U)
+#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos        (12U)
+#define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */
+#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00004000 */
+#define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x01000000 */
+
+#define TIM_CCMR1_OC2CE_Pos       (15U)
+#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos      (2U)
+#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos        (4U)
+#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos      (10U)
+#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos        (12U)
+#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define TIM_CCMR2_CC3S_Pos        (0U)
+#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos       (2U)
+#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos       (3U)
+#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos        (4U)
+#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
+#define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010000 */
+
+#define TIM_CCMR2_OC3CE_Pos       (7U)
+#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos        (8U)
+#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos       (10U)
+#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos       (11U)
+#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos        (12U)
+#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
+#define TIM_CCMR2_OC4M_3          (0x100UL << TIM_CCMR2_OC4M_Pos)               /*!< 0x00100000 */
+
+#define TIM_CCMR2_OC4CE_Pos       (15U)
+#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos      (2U)
+#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos        (4U)
+#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos      (10U)
+#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos        (12U)
+#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define TIM_CCER_CC1E_Pos         (0U)
+#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */
+#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos         (1U)
+#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */
+#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos        (2U)
+#define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */
+#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos        (3U)
+#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */
+#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos         (4U)
+#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */
+#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos         (5U)
+#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */
+#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos        (6U)
+#define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */
+#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos        (7U)
+#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */
+#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos         (8U)
+#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */
+#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos         (9U)
+#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */
+#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos        (10U)
+#define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */
+#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos        (11U)
+#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */
+#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos         (12U)
+#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */
+#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos         (13U)
+#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */
+#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos        (15U)
+#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */
+#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
+#define TIM_CCER_CC5E_Pos         (16U)
+#define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */
+#define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */
+#define TIM_CCER_CC5P_Pos         (17U)
+#define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */
+#define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */
+#define TIM_CCER_CC6E_Pos         (20U)
+#define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */
+#define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */
+#define TIM_CCER_CC6P_Pos         (21U)
+#define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */
+#define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define TIM_CNT_CNT_Pos           (0U)
+#define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
+#define TIM_CNT_UIFCPY_Pos        (31U)
+#define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */
+#define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy */
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define TIM_PSC_PSC_Pos           (0U)
+#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */
+#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define TIM_ARR_ARR_Pos           (0U)
+#define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RCR register  ********************/
+#define TIM_RCR_REP_Pos           (0U)
+#define TIM_RCR_REP_Msk           (0xFFUL << TIM_RCR_REP_Pos)                  /*!< 0x000000FF */
+#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define TIM_CCR1_CCR1_Pos         (0U)
+#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)              /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define TIM_CCR2_CCR2_Pos         (0U)
+#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)              /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define TIM_CCR3_CCR3_Pos         (0U)
+#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)              /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define TIM_CCR4_CCR4_Pos         (0U)
+#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)              /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_CCR5 register  *******************/
+#define TIM_CCR5_CCR5_Pos         (0U)
+#define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)          /*!< 0xFFFFFFFF */
+#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */
+#define TIM_CCR5_GC5C1_Pos        (29U)
+#define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */
+#define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */
+#define TIM_CCR5_GC5C2_Pos        (30U)
+#define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */
+#define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */
+#define TIM_CCR5_GC5C3_Pos        (31U)
+#define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */
+#define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */
+
+/*******************  Bit definition for TIM_CCR6 register  *******************/
+#define TIM_CCR6_CCR6_Pos         (0U)
+#define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */
+#define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define TIM_BDTR_DTG_Pos          (0U)
+#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */
+#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000001 */
+#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000002 */
+#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000004 */
+#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000008 */
+#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000010 */
+#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000020 */
+#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000040 */
+#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000080 */
+
+#define TIM_BDTR_LOCK_Pos         (8U)
+#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */
+#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000100 */
+#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000200 */
+
+#define TIM_BDTR_OSSI_Pos         (10U)
+#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */
+#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos         (11U)
+#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */
+#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos          (12U)
+#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */
+#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break1 */
+#define TIM_BDTR_BKP_Pos          (13U)
+#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */
+#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break1 */
+#define TIM_BDTR_AOE_Pos          (14U)
+#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */
+#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos          (15U)
+#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */
+#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
+
+#define TIM_BDTR_BKF_Pos          (16U)
+#define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */
+#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break1 */
+#define TIM_BDTR_BK2F_Pos         (20U)
+#define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */
+#define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break2 */
+
+#define TIM_BDTR_BK2E_Pos         (24U)
+#define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */
+#define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break2 */
+#define TIM_BDTR_BK2P_Pos         (25U)
+#define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */
+#define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break2 */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define TIM_DCR_DBA_Pos           (0U)
+#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */
+#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
+#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
+#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
+#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
+#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos           (8U)
+#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */
+#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
+#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
+#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
+#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
+#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define TIM_DMAR_DMAB_Pos         (0U)
+#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)              /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
+
+/******************  Bit definition for TIM_CCMR3 register  *******************/
+#define TIM_CCMR3_OC5FE_Pos       (2U)
+#define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */
+#define TIM_CCMR3_OC5PE_Pos       (3U)
+#define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */
+#define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
+
+#define TIM_CCMR3_OC5M_Pos        (4U)
+#define TIM_CCMR3_OC5M_Msk        (0x7UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00000070 */
+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_0          (0x1UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000010 */
+#define TIM_CCMR3_OC5M_1          (0x2UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000020 */
+#define TIM_CCMR3_OC5M_2          (0x4UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000040 */
+#define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010000 */
+
+#define TIM_CCMR3_OC5CE_Pos       (7U)
+#define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */
+#define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */
+
+#define TIM_CCMR3_OC6FE_Pos       (10U)
+#define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR3_OC6PE_Pos       (11U)
+#define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */
+#define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR3_OC6M_Pos        (12U)
+#define TIM_CCMR3_OC6M_Msk        (0x7UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x00007000 */
+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR3_OC6M_0          (0x1UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00001000 */
+#define TIM_CCMR3_OC6M_1          (0x2UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00002000 */
+#define TIM_CCMR3_OC6M_2          (0x4UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00004000 */
+#define TIM_CCMR3_OC6M_3          (0x100UL << TIM_CCMR3_OC6M_Pos)               /*!< 0x00100000 */
+
+#define TIM_CCMR3_OC6CE_Pos       (15U)
+#define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
+#define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 4 Clear Enable */
+/*******************  Bit definition for TIM1_AF1 register  *********************/
+#define TIM1_AF1_BKINE_Pos        (0U)
+#define TIM1_AF1_BKINE_Msk        (0x1UL << TIM1_AF1_BKINE_Pos)                /*!< 0x00000001 */
+#define TIM1_AF1_BKINE            TIM1_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */
+#define TIM1_AF1_BKCMP1E_Pos      (1U)
+#define TIM1_AF1_BKCMP1E_Msk      (0x1UL << TIM1_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */
+#define TIM1_AF1_BKCMP1E          TIM1_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */
+#define TIM1_AF1_BKCMP2E_Pos      (2U)
+#define TIM1_AF1_BKCMP2E_Msk      (0x1UL << TIM1_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */
+#define TIM1_AF1_BKCMP2E          TIM1_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit */
+#define TIM1_AF1_BKDF1BK0E_Pos    (8U)
+#define TIM1_AF1_BKDF1BK0E_Msk    (0x1UL << TIM1_AF1_BKDF1BK0E_Pos)            /*!< 0x00000100 */
+#define TIM1_AF1_BKDF1BK0E        TIM1_AF1_BKDF1BK0E_Msk                       /*!<BKDF1BK0E Break input DFSDM Break 0 */
+#define TIM1_AF1_BKINP_Pos        (9U)
+#define TIM1_AF1_BKINP_Msk        (0x1UL << TIM1_AF1_BKINP_Pos)                /*!< 0x00000200 */
+#define TIM1_AF1_BKINP            TIM1_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */
+#define TIM1_AF1_BKCMP1P_Pos      (10U)
+#define TIM1_AF1_BKCMP1P_Msk      (0x1UL << TIM1_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */
+#define TIM1_AF1_BKCMP1P          TIM1_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */
+#define TIM1_AF1_BKCMP2P_Pos      (11U)
+#define TIM1_AF1_BKCMP2P_Msk      (0x1UL << TIM1_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */
+#define TIM1_AF1_BKCMP2P          TIM1_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */
+
+#define TIM1_AF1_ETRSEL_Pos       (14U)
+#define TIM1_AF1_ETRSEL_Msk       (0xFUL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */
+#define TIM1_AF1_ETRSEL           TIM1_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM1 ETRSEL) */
+#define TIM1_AF1_ETRSEL_0         (0x1UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00004000 */
+#define TIM1_AF1_ETRSEL_1         (0x2UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00008000 */
+#define TIM1_AF1_ETRSEL_2         (0x4UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00010000 */
+#define TIM1_AF1_ETRSEL_3         (0x8UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00020000 */
+
+/*******************  Bit definition for TIM1_AF2 register  *********************/
+#define TIM1_AF2_BK2INE_Pos       (0U)
+#define TIM1_AF2_BK2INE_Msk       (0x1UL << TIM1_AF2_BK2INE_Pos)               /*!< 0x00000001 */
+#define TIM1_AF2_BK2INE           TIM1_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */
+#define TIM1_AF2_BK2CMP1E_Pos     (1U)
+#define TIM1_AF2_BK2CMP1E_Msk     (0x1UL << TIM1_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */
+#define TIM1_AF2_BK2CMP1E         TIM1_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */
+#define TIM1_AF2_BK2CMP2E_Pos     (2U)
+#define TIM1_AF2_BK2CMP2E_Msk     (0x1UL << TIM1_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */
+#define TIM1_AF2_BK2CMP2E         TIM1_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */
+#define TIM1_AF2_BK2DFBK1E_Pos    (8U)
+#define TIM1_AF2_BK2DFBK1E_Msk    (0x1UL << TIM1_AF2_BK2DFBK1E_Pos)            /*!< 0x00000100 */
+#define TIM1_AF2_BK2DFBK1E        TIM1_AF2_BK2DFBK1E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 1 */
+#define TIM1_AF2_BK2INP_Pos       (9U)
+#define TIM1_AF2_BK2INP_Msk       (0x1UL << TIM1_AF2_BK2INP_Pos)               /*!< 0x00000200 */
+#define TIM1_AF2_BK2INP           TIM1_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */
+#define TIM1_AF2_BK2CMP1P_Pos     (10U)
+#define TIM1_AF2_BK2CMP1P_Msk     (0x1UL << TIM1_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */
+#define TIM1_AF2_BK2CMP1P         TIM1_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */
+#define TIM1_AF2_BK2CMP2P_Pos     (11U)
+#define TIM1_AF2_BK2CMP2P_Msk     (0x1UL << TIM1_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */
+#define TIM1_AF2_BK2CMP2P         TIM1_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */
+
+/*******************  Bit definition for TIM_TISEL register  *********************/
+#define TIM_TISEL_TI1SEL_Pos      (0U)
+#define TIM_TISEL_TI1SEL_Msk      (0xFUL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x0000000F */
+#define TIM_TISEL_TI1SEL          TIM_TISEL_TI1SEL_Msk                         /*!<TI1SEL[3:0] bits (TIM TI1 SEL)*/
+#define TIM_TISEL_TI1SEL_0        (0x1UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000001 */
+#define TIM_TISEL_TI1SEL_1        (0x2UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000002 */
+#define TIM_TISEL_TI1SEL_2        (0x4UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000004 */
+#define TIM_TISEL_TI1SEL_3        (0x8UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000008 */
+
+#define TIM_TISEL_TI2SEL_Pos      (8U)
+#define TIM_TISEL_TI2SEL_Msk      (0xFUL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000F00 */
+#define TIM_TISEL_TI2SEL          TIM_TISEL_TI2SEL_Msk                         /*!<TI2SEL[3:0] bits (TIM TI2 SEL)*/
+#define TIM_TISEL_TI2SEL_0        (0x1UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000100 */
+#define TIM_TISEL_TI2SEL_1        (0x2UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000200 */
+#define TIM_TISEL_TI2SEL_2        (0x4UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000400 */
+#define TIM_TISEL_TI2SEL_3        (0x8UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000800 */
+
+#define TIM_TISEL_TI3SEL_Pos      (16U)
+#define TIM_TISEL_TI3SEL_Msk      (0xFUL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x000F0000 */
+#define TIM_TISEL_TI3SEL          TIM_TISEL_TI3SEL_Msk                         /*!<TI3SEL[3:0] bits (TIM TI3 SEL)*/
+#define TIM_TISEL_TI3SEL_0        (0x1UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00010000 */
+#define TIM_TISEL_TI3SEL_1        (0x2UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00020000 */
+#define TIM_TISEL_TI3SEL_2        (0x4UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00040000 */
+#define TIM_TISEL_TI3SEL_3        (0x8UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00080000 */
+
+#define TIM_TISEL_TI4SEL_Pos      (24U)
+#define TIM_TISEL_TI4SEL_Msk      (0xFUL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x0F000000 */
+#define TIM_TISEL_TI4SEL          TIM_TISEL_TI4SEL_Msk                         /*!<TI4SEL[3:0] bits (TIM TI4 SEL)*/
+#define TIM_TISEL_TI4SEL_0        (0x1UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x01000000 */
+#define TIM_TISEL_TI4SEL_1        (0x2UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x02000000 */
+#define TIM_TISEL_TI4SEL_2        (0x4UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x04000000 */
+#define TIM_TISEL_TI4SEL_3        (0x8UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x08000000 */
+
+/*******************  Bit definition for TIM8_AF1 register  *********************/
+#define TIM8_AF1_BKINE_Pos        (0U)
+#define TIM8_AF1_BKINE_Msk        (0x1UL << TIM8_AF1_BKINE_Pos)                /*!< 0x00000001 */
+#define TIM8_AF1_BKINE            TIM8_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */
+#define TIM8_AF1_BKCMP1E_Pos      (1U)
+#define TIM8_AF1_BKCMP1E_Msk      (0x1UL << TIM8_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */
+#define TIM8_AF1_BKCMP1E          TIM8_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */
+#define TIM8_AF1_BKCMP2E_Pos      (2U)
+#define TIM8_AF1_BKCMP2E_Msk      (0x1UL << TIM8_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */
+#define TIM8_AF1_BKCMP2E          TIM8_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit  */
+#define TIM8_AF1_BKDFBK2E_Pos     (8U)
+#define TIM8_AF1_BKDFBK2E_Msk     (0x1UL << TIM8_AF1_BKDFBK2E_Pos)             /*!< 0x00000100 */
+#define TIM8_AF1_BKDFBK2E         TIM8_AF1_BKDFBK2E_Msk                        /*!<BKDFBK2E Break input DFSDM Break 2 */
+#define TIM8_AF1_BKINP_Pos        (9U)
+#define TIM8_AF1_BKINP_Msk        (0x1UL << TIM8_AF1_BKINP_Pos)                /*!< 0x00000200 */
+#define TIM8_AF1_BKINP            TIM8_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */
+#define TIM8_AF1_BKCMP1P_Pos      (10U)
+#define TIM8_AF1_BKCMP1P_Msk      (0x1UL << TIM8_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */
+#define TIM8_AF1_BKCMP1P          TIM8_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */
+#define TIM8_AF1_BKCMP2P_Pos      (11U)
+#define TIM8_AF1_BKCMP2P_Msk      (0x1UL << TIM8_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */
+#define TIM8_AF1_BKCMP2P          TIM8_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */
+
+#define TIM8_AF1_ETRSEL_Pos       (14U)
+#define TIM8_AF1_ETRSEL_Msk       (0xFUL << TIM8_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */
+#define TIM8_AF1_ETRSEL           TIM8_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM8 ETRSEL) */
+#define TIM8_AF1_ETRSEL_0         (0x1UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00004000 */
+#define TIM8_AF1_ETRSEL_1         (0x2UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00008000 */
+#define TIM8_AF1_ETRSEL_2         (0x4UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00010000 */
+#define TIM8_AF1_ETRSEL_3         (0x8UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00020000 */
+/*******************  Bit definition for TIM8_AF2 register  *********************/
+#define TIM8_AF2_BK2INE_Pos       (0U)
+#define TIM8_AF2_BK2INE_Msk       (0x1UL << TIM8_AF2_BK2INE_Pos)               /*!< 0x00000001 */
+#define TIM8_AF2_BK2INE           TIM8_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */
+#define TIM8_AF2_BK2CMP1E_Pos     (1U)
+#define TIM8_AF2_BK2CMP1E_Msk     (0x1UL << TIM8_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */
+#define TIM8_AF2_BK2CMP1E         TIM8_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */
+#define TIM8_AF2_BK2CMP2E_Pos     (2U)
+#define TIM8_AF2_BK2CMP2E_Msk     (0x1UL << TIM8_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */
+#define TIM8_AF2_BK2CMP2E         TIM8_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */
+#define TIM8_AF2_BK2DFBK3E_Pos    (8U)
+#define TIM8_AF2_BK2DFBK3E_Msk    (0x1UL << TIM8_AF2_BK2DFBK3E_Pos)            /*!< 0x00000100 */
+#define TIM8_AF2_BK2DFBK3E        TIM8_AF2_BK2DFBK3E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 3 */
+#define TIM8_AF2_BK2INP_Pos       (9U)
+#define TIM8_AF2_BK2INP_Msk       (0x1UL << TIM8_AF2_BK2INP_Pos)               /*!< 0x00000200 */
+#define TIM8_AF2_BK2INP           TIM8_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */
+#define TIM8_AF2_BK2CMP1P_Pos     (10U)
+#define TIM8_AF2_BK2CMP1P_Msk     (0x1UL << TIM8_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */
+#define TIM8_AF2_BK2CMP1P         TIM8_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */
+#define TIM8_AF2_BK2CMP2P_Pos     (11U)
+#define TIM8_AF2_BK2CMP2P_Msk     (0x1UL << TIM8_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */
+#define TIM8_AF2_BK2CMP2P         TIM8_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */
+
+/*******************  Bit definition for TIM2_AF1 register  *********************/
+#define TIM2_AF1_ETRSEL_Pos      (14U)
+#define TIM2_AF1_ETRSEL_Msk      (0xFUL << TIM2_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */
+#define TIM2_AF1_ETRSEL          TIM2_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM2 ETRSEL) */
+#define TIM2_AF1_ETRSEL_0        (0x1UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */
+#define TIM2_AF1_ETRSEL_1        (0x2UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */
+#define TIM2_AF1_ETRSEL_2        (0x4UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */
+#define TIM2_AF1_ETRSEL_3        (0x8UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */
+
+/*******************  Bit definition for TIM3_AF1 register  *********************/
+#define TIM3_AF1_ETRSEL_Pos      (14U)
+#define TIM3_AF1_ETRSEL_Msk      (0xFUL << TIM3_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */
+#define TIM3_AF1_ETRSEL          TIM3_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM3 ETRSEL) */
+#define TIM3_AF1_ETRSEL_0        (0x1UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */
+#define TIM3_AF1_ETRSEL_1        (0x2UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */
+#define TIM3_AF1_ETRSEL_2        (0x4UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */
+#define TIM3_AF1_ETRSEL_3        (0x8UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */
+
+/*******************  Bit definition for TIM5_AF1 register  *********************/
+#define TIM5_AF1_ETRSEL_Pos      (14U)
+#define TIM5_AF1_ETRSEL_Msk      (0xFUL << TIM5_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */
+#define TIM5_AF1_ETRSEL          TIM5_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM5 ETRSEL) */
+#define TIM5_AF1_ETRSEL_0        (0x1UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */
+#define TIM5_AF1_ETRSEL_1        (0x2UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */
+#define TIM5_AF1_ETRSEL_2        (0x4UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */
+#define TIM5_AF1_ETRSEL_3        (0x8UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */
+
+/*******************  Bit definition for TIM15_AF1 register  *********************/
+#define TIM15_AF1_BKINE_Pos        (0U)
+#define TIM15_AF1_BKINE_Msk        (0x1UL << TIM15_AF1_BKINE_Pos)              /*!< 0x00000001 */
+#define TIM15_AF1_BKINE            TIM15_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */
+#define TIM15_AF1_BKCMP1E_Pos      (1U)
+#define TIM15_AF1_BKCMP1E_Msk      (0x1UL << TIM15_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */
+#define TIM15_AF1_BKCMP1E          TIM15_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */
+#define TIM15_AF1_BKCMP2E_Pos      (2U)
+#define TIM15_AF1_BKCMP2E_Msk      (0x1UL << TIM15_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */
+#define TIM15_AF1_BKCMP2E          TIM15_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */
+#define TIM15_AF1_BKDF1BK2E_Pos    (8U)
+#define TIM15_AF1_BKDF1BK2E_Msk    (0x1UL << TIM15_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */
+#define TIM15_AF1_BKDF1BK2E        TIM15_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[0] enable */
+#define TIM15_AF1_BKINP_Pos        (9U)
+#define TIM15_AF1_BKINP_Msk        (0x1UL << TIM15_AF1_BKINP_Pos)              /*!< 0x00000200 */
+#define TIM15_AF1_BKINP            TIM15_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */
+#define TIM15_AF1_BKCMP1P_Pos      (10U)
+#define TIM15_AF1_BKCMP1P_Msk      (0x1UL << TIM15_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */
+#define TIM15_AF1_BKCMP1P          TIM15_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */
+#define TIM15_AF1_BKCMP2P_Pos      (11U)
+#define TIM15_AF1_BKCMP2P_Msk      (0x1UL << TIM15_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */
+#define TIM15_AF1_BKCMP2P          TIM15_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */
+
+/*******************  Bit definition for TIM16_ register  *********************/
+#define TIM16_AF1_BKINE_Pos        (0U)
+#define TIM16_AF1_BKINE_Msk        (0x1UL << TIM16_AF1_BKINE_Pos)              /*!< 0x00000001 */
+#define TIM16_AF1_BKINE            TIM16_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */
+#define TIM16_AF1_BKCMP1E_Pos      (1U)
+#define TIM16_AF1_BKCMP1E_Msk      (0x1UL << TIM16_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */
+#define TIM16_AF1_BKCMP1E          TIM16_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */
+#define TIM16_AF1_BKCMP2E_Pos      (2U)
+#define TIM16_AF1_BKCMP2E_Msk      (0x1UL << TIM16_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */
+#define TIM16_AF1_BKCMP2E          TIM16_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */
+#define TIM16_AF1_BKDF1BK2E_Pos    (8U)
+#define TIM16_AF1_BKDF1BK2E_Msk    (0x1UL << TIM16_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */
+#define TIM16_AF1_BKDF1BK2E        TIM16_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[1] enable */
+#define TIM16_AF1_BKINP_Pos        (9U)
+#define TIM16_AF1_BKINP_Msk        (0x1UL << TIM16_AF1_BKINP_Pos)              /*!< 0x00000200 */
+#define TIM16_AF1_BKINP            TIM16_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */
+#define TIM16_AF1_BKCMP1P_Pos      (10U)
+#define TIM16_AF1_BKCMP1P_Msk      (0x1UL << TIM16_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */
+#define TIM16_AF1_BKCMP1P          TIM16_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */
+#define TIM16_AF1_BKCMP2P_Pos      (11U)
+#define TIM16_AF1_BKCMP2P_Msk      (0x1UL << TIM16_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */
+#define TIM16_AF1_BKCMP2P          TIM16_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */
+
+/*******************  Bit definition for TIM17_AF1 register  *********************/
+#define TIM17_AF1_BKINE_Pos        (0U)
+#define TIM17_AF1_BKINE_Msk        (0x1UL << TIM17_AF1_BKINE_Pos)              /*!< 0x00000001 */
+#define TIM17_AF1_BKINE            TIM17_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */
+#define TIM17_AF1_BKCMP1E_Pos      (1U)
+#define TIM17_AF1_BKCMP1E_Msk      (0x1UL << TIM17_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */
+#define TIM17_AF1_BKCMP1E          TIM17_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */
+#define TIM17_AF1_BKCMP2E_Pos      (2U)
+#define TIM17_AF1_BKCMP2E_Msk      (0x1UL << TIM17_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */
+#define TIM17_AF1_BKCMP2E          TIM17_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */
+#define TIM17_AF1_BKDF1BK2E_Pos    (8U)
+#define TIM17_AF1_BKDF1BK2E_Msk    (0x1UL << TIM17_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */
+#define TIM17_AF1_BKDF1BK2E        TIM17_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[2] enable */
+#define TIM17_AF1_BKINP_Pos        (9U)
+#define TIM17_AF1_BKINP_Msk        (0x1UL << TIM17_AF1_BKINP_Pos)              /*!< 0x00000200 */
+#define TIM17_AF1_BKINP            TIM17_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */
+#define TIM17_AF1_BKCMP1P_Pos      (10U)
+#define TIM17_AF1_BKCMP1P_Msk      (0x1UL << TIM17_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */
+#define TIM17_AF1_BKCMP1P          TIM17_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */
+#define TIM17_AF1_BKCMP2P_Pos      (11U)
+#define TIM17_AF1_BKCMP2P_Msk      (0x1UL << TIM17_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */
+#define TIM17_AF1_BKCMP2P          TIM17_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Low Power Timer (LPTTIM)                           */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for LPTIM_ISR register  *******************/
+#define LPTIM_ISR_CMPM_Pos          (0U)
+#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)              /*!< 0x00000001 */
+#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
+#define LPTIM_ISR_ARRM_Pos          (1U)
+#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */
+#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG_Pos       (2U)
+#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */
+#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK_Pos         (3U)
+#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)             /*!< 0x00000008 */
+#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK_Pos         (4U)
+#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */
+#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP_Pos            (5U)
+#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */
+#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN_Pos          (6U)
+#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */
+#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
+
+/******************  Bit definition for LPTIM_ICR register  *******************/
+#define LPTIM_ICR_CMPMCF_Pos        (0U)
+#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)            /*!< 0x00000001 */
+#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF_Pos        (1U)
+#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */
+#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)
+#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */
+#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF_Pos       (3U)
+#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)           /*!< 0x00000008 */
+#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF_Pos       (4U)
+#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */
+#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF_Pos          (5U)
+#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */
+#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF_Pos        (6U)
+#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */
+#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
+
+/******************  Bit definition for LPTIM_IER register ********************/
+#define LPTIM_IER_CMPMIE_Pos        (0U)
+#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)            /*!< 0x00000001 */
+#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE_Pos        (1U)
+#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)            /*!< 0x00000002 */
+#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE_Pos     (2U)
+#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)         /*!< 0x00000004 */
+#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE_Pos       (3U)
+#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)           /*!< 0x00000008 */
+#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE_Pos       (4U)
+#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)           /*!< 0x00000010 */
+#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE_Pos          (5U)
+#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)              /*!< 0x00000020 */
+#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE_Pos        (6U)
+#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)            /*!< 0x00000040 */
+#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
+
+/******************  Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL_Pos        (0U)
+#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */
+#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL_Pos        (1U)
+#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */
+#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */
+#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */
+
+#define LPTIM_CFGR_CKFLT_Pos        (3U)
+#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */
+#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */
+#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */
+
+#define LPTIM_CFGR_TRGFLT_Pos       (6U)
+#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */
+#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */
+#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */
+
+#define LPTIM_CFGR_PRESC_Pos        (9U)
+#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */
+#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */
+#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */
+#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */
+
+#define LPTIM_CFGR_TRIGSEL_Pos      (13U)
+#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x0000E000 */
+#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */
+#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */
+#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */
+
+#define LPTIM_CFGR_TRIGEN_Pos       (17U)
+#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */
+#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */
+#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */
+
+#define LPTIM_CFGR_TIMOUT_Pos       (19U)
+#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */
+#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
+#define LPTIM_CFGR_WAVE_Pos         (20U)
+#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */
+#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL_Pos       (21U)
+#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */
+#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD_Pos      (22U)
+#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */
+#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE_Pos    (23U)
+#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */
+#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC_Pos          (24U)
+#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */
+#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
+
+/******************  Bit definition for LPTIM_CR register  ********************/
+#define LPTIM_CR_ENABLE_Pos         (0U)
+#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */
+#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT_Pos        (1U)
+#define LPTIM_CR_SNGSTRT_Msk        (0x40001UL << LPTIM_CR_SNGSTRT_Pos)        /*!< 0x00080002 */
+#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT_Pos        (2U)
+#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */
+#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
+#define LPTIM_CR_COUNTRST_Pos       (3U)
+#define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */
+#define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Timer Counter reset in synchronous mode*/
+#define LPTIM_CR_RSTARE_Pos         (4U)
+#define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */
+#define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Timer Counter reset after read enable (asynchronously)*/
+
+
+/******************  Bit definition for LPTIM_CMP register  *******************/
+#define LPTIM_CMP_CMP_Pos           (0U)
+#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)            /*!< 0x0000FFFF */
+#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
+
+/******************  Bit definition for LPTIM_ARR register  *******************/
+#define LPTIM_ARR_ARR_Pos           (0U)
+#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */
+#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
+
+/******************  Bit definition for LPTIM_CNT register  *******************/
+#define LPTIM_CNT_CNT_Pos           (0U)
+#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */
+#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
+
+/******************  Bit definition for LPTIM_CFGR2 register  *****************/
+#define LPTIM_CFGR2_IN1SEL_Pos      (0U)
+#define LPTIM_CFGR2_IN1SEL_Msk      (0x3UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000003 */
+#define LPTIM_CFGR2_IN1SEL          LPTIM_CFGR2_IN1SEL_Msk                     /*!< IN1SEL[1:0] bits (Remap selection) */
+#define LPTIM_CFGR2_IN1SEL_0        (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000001 */
+#define LPTIM_CFGR2_IN1SEL_1        (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000002 */
+#define LPTIM_CFGR2_IN2SEL_Pos      (4U)
+#define LPTIM_CFGR2_IN2SEL_Msk      (0x3UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000030 */
+#define LPTIM_CFGR2_IN2SEL          LPTIM_CFGR2_IN2SEL_Msk                     /*!< IN2SEL[5:4] bits (Remap selection) */
+#define LPTIM_CFGR2_IN2SEL_0        (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000010 */
+#define LPTIM_CFGR2_IN2SEL_1        (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000020 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Analog Comparators (COMP)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for COMP_SR register  ********************/
+#define COMP_SR_C1VAL_Pos            (0U)
+#define COMP_SR_C1VAL_Msk            (0x1UL << COMP_SR_C1VAL_Pos)              /*!< 0x00000001 */
+#define COMP_SR_C1VAL                COMP_SR_C1VAL_Msk
+#define COMP_SR_C2VAL_Pos            (1U)
+#define COMP_SR_C2VAL_Msk            (0x1UL << COMP_SR_C2VAL_Pos)              /*!< 0x00000002 */
+#define COMP_SR_C2VAL                COMP_SR_C2VAL_Msk
+#define COMP_SR_C1IF_Pos             (16U)
+#define COMP_SR_C1IF_Msk             (0x1UL << COMP_SR_C1IF_Pos)               /*!< 0x00010000 */
+#define COMP_SR_C1IF                 COMP_SR_C1IF_Msk
+#define COMP_SR_C2IF_Pos             (17U)
+#define COMP_SR_C2IF_Msk             (0x1UL << COMP_SR_C2IF_Pos)               /*!< 0x00020000 */
+#define COMP_SR_C2IF                 COMP_SR_C2IF_Msk
+/*******************  Bit definition for COMP_ICFR register  ********************/
+#define COMP_ICFR_C1IF_Pos           (16U)
+#define COMP_ICFR_C1IF_Msk           (0x1UL << COMP_ICFR_C1IF_Pos)             /*!< 0x00010000 */
+#define COMP_ICFR_C1IF               COMP_ICFR_C1IF_Msk
+#define COMP_ICFR_C2IF_Pos           (17U)
+#define COMP_ICFR_C2IF_Msk           (0x1UL << COMP_ICFR_C2IF_Pos)             /*!< 0x00020000 */
+#define COMP_ICFR_C2IF               COMP_ICFR_C2IF_Msk
+/*******************  Bit definition for COMP_OR register  ********************/
+#define COMP_OR_AFOPA6_Pos           (0U)
+#define COMP_OR_AFOPA6_Msk           (0x1UL << COMP_OR_AFOPA6_Pos)             /*!< 0x00000001 */
+#define COMP_OR_AFOPA6               COMP_OR_AFOPA6_Msk
+#define COMP_OR_AFOPA8_Pos           (1U)
+#define COMP_OR_AFOPA8_Msk           (0x1UL << COMP_OR_AFOPA8_Pos)             /*!< 0x00000002 */
+#define COMP_OR_AFOPA8               COMP_OR_AFOPA8_Msk
+#define COMP_OR_AFOPB12_Pos          (2U)
+#define COMP_OR_AFOPB12_Msk          (0x1UL << COMP_OR_AFOPB12_Pos)            /*!< 0x00000004 */
+#define COMP_OR_AFOPB12              COMP_OR_AFOPB12_Msk
+#define COMP_OR_AFOPE6_Pos           (3U)
+#define COMP_OR_AFOPE6_Msk           (0x1UL << COMP_OR_AFOPE6_Pos)             /*!< 0x00000008 */
+#define COMP_OR_AFOPE6               COMP_OR_AFOPE6_Msk
+#define COMP_OR_AFOPE15_Pos          (4U)
+#define COMP_OR_AFOPE15_Msk          (0x1UL << COMP_OR_AFOPE15_Pos)            /*!< 0x00000010 */
+#define COMP_OR_AFOPE15              COMP_OR_AFOPE15_Msk
+#define COMP_OR_AFOPG2_Pos           (5U)
+#define COMP_OR_AFOPG2_Msk           (0x1UL << COMP_OR_AFOPG2_Pos)             /*!< 0x00000020 */
+#define COMP_OR_AFOPG2               COMP_OR_AFOPG2_Msk
+#define COMP_OR_AFOPG3_Pos           (6U)
+#define COMP_OR_AFOPG3_Msk           (0x1UL << COMP_OR_AFOPG3_Pos)             /*!< 0x00000040 */
+#define COMP_OR_AFOPG3               COMP_OR_AFOPG3_Msk
+#define COMP_OR_AFOPG4_Pos           (7U)
+#define COMP_OR_AFOPG4_Msk           (0x1UL << COMP_OR_AFOPG4_Pos)             /*!< 0x00000080 */
+#define COMP_OR_AFOPG4               COMP_OR_AFOPG4_Msk
+#define COMP_OR_AFOPI1_Pos           (8U)
+#define COMP_OR_AFOPI1_Msk           (0x1UL << COMP_OR_AFOPI1_Pos)             /*!< 0x00000100 */
+#define COMP_OR_AFOPI1               COMP_OR_AFOPI1_Msk
+#define COMP_OR_AFOPI4_Pos           (9U)
+#define COMP_OR_AFOPI4_Msk           (0x1UL << COMP_OR_AFOPI4_Pos)             /*!< 0x00000200 */
+#define COMP_OR_AFOPI4               COMP_OR_AFOPI4_Msk
+#define COMP_OR_AFOPK2_Pos           (10U)
+#define COMP_OR_AFOPK2_Msk           (0x1UL << COMP_OR_AFOPK2_Pos)             /*!< 0x00000400 */
+#define COMP_OR_AFOPK2               COMP_OR_AFOPK2_Msk
+
+/*!< ******************  Bit definition for COMP_CFGRx register  ********************/
+#define COMP_CFGRx_EN_Pos            (0U)
+#define COMP_CFGRx_EN_Msk            (0x1UL << COMP_CFGRx_EN_Pos)              /*!< 0x00000001 */
+#define COMP_CFGRx_EN                COMP_CFGRx_EN_Msk                         /*!< COMPx enable bit                     */
+#define COMP_CFGRx_BRGEN_Pos         (1U)
+#define COMP_CFGRx_BRGEN_Msk         (0x1UL << COMP_CFGRx_BRGEN_Pos)           /*!< 0x00000002 */
+#define COMP_CFGRx_BRGEN             COMP_CFGRx_BRGEN_Msk                      /*!< COMPx Scaler bridge enable           */
+#define COMP_CFGRx_SCALEN_Pos        (2U)
+#define COMP_CFGRx_SCALEN_Msk        (0x1UL << COMP_CFGRx_SCALEN_Pos)          /*!< 0x00000004 */
+#define COMP_CFGRx_SCALEN            COMP_CFGRx_SCALEN_Msk                     /*!< COMPx Voltage scaler enable bit      */
+#define COMP_CFGRx_POLARITY_Pos      (3U)
+#define COMP_CFGRx_POLARITY_Msk      (0x1UL << COMP_CFGRx_POLARITY_Pos)        /*!< 0x00000008 */
+#define COMP_CFGRx_POLARITY          COMP_CFGRx_POLARITY_Msk                   /*!< COMPx  polarity selection bit        */
+#define COMP_CFGRx_WINMODE_Pos       (4U)
+#define COMP_CFGRx_WINMODE_Msk       (0x1UL << COMP_CFGRx_WINMODE_Pos)         /*!< 0x00000010 */
+#define COMP_CFGRx_WINMODE           COMP_CFGRx_WINMODE_Msk                    /*!< COMPx Windows mode selection bit     */
+#define COMP_CFGRx_ITEN_Pos          (6U)
+#define COMP_CFGRx_ITEN_Msk          (0x1UL << COMP_CFGRx_ITEN_Pos)            /*!< 0x00000040 */
+#define COMP_CFGRx_ITEN              COMP_CFGRx_ITEN_Msk                       /*!< COMPx  interrupt enable              */
+#define COMP_CFGRx_HYST_Pos          (8U)
+#define COMP_CFGRx_HYST_Msk          (0x3UL << COMP_CFGRx_HYST_Pos)            /*!< 0x00000300 */
+#define COMP_CFGRx_HYST              COMP_CFGRx_HYST_Msk                       /*!< COMPx  hysteresis selection bits     */
+#define COMP_CFGRx_HYST_0            (0x1UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000100 */
+#define COMP_CFGRx_HYST_1            (0x2UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000200 */
+#define COMP_CFGRx_PWRMODE_Pos       (12U)
+#define COMP_CFGRx_PWRMODE_Msk       (0x3UL << COMP_CFGRx_PWRMODE_Pos)         /*!< 0x00003000 */
+#define COMP_CFGRx_PWRMODE           COMP_CFGRx_PWRMODE_Msk                    /*!< COMPx Power Mode of the comparator   */
+#define COMP_CFGRx_PWRMODE_0         (0x1UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00001000 */
+#define COMP_CFGRx_PWRMODE_1         (0x2UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00002000 */
+#define COMP_CFGRx_INMSEL_Pos        (16U)
+#define COMP_CFGRx_INMSEL_Msk        (0x7UL << COMP_CFGRx_INMSEL_Pos)          /*!< 0x00070000 */
+#define COMP_CFGRx_INMSEL            COMP_CFGRx_INMSEL_Msk                     /*!< COMPx  input minus selection bit  */
+#define COMP_CFGRx_INMSEL_0          (0x1UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00010000 */
+#define COMP_CFGRx_INMSEL_1          (0x2UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00020000 */
+#define COMP_CFGRx_INMSEL_2          (0x4UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00040000 */
+#define COMP_CFGRx_INPSEL_Pos        (20U)
+#define COMP_CFGRx_INPSEL_Msk        (0x1UL << COMP_CFGRx_INPSEL_Pos)          /*!< 0x00100000 */
+#define COMP_CFGRx_INPSEL            COMP_CFGRx_INPSEL_Msk                     /*!< COMPx  input plus selection bit       */
+#define COMP_CFGRx_BLANKING_Pos      (24U)
+#define COMP_CFGRx_BLANKING_Msk      (0xFUL << COMP_CFGRx_BLANKING_Pos)        /*!< 0x0F000000 */
+#define COMP_CFGRx_BLANKING          COMP_CFGRx_BLANKING_Msk                   /*!< COMPx  blanking source selection bits */
+#define COMP_CFGRx_BLANKING_0        (0x1UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x01000000 */
+#define COMP_CFGRx_BLANKING_1        (0x2UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x02000000 */
+#define COMP_CFGRx_BLANKING_2        (0x4UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x04000000 */
+#define COMP_CFGRx_LOCK_Pos          (31U)
+#define COMP_CFGRx_LOCK_Msk          (0x1UL << COMP_CFGRx_LOCK_Pos)            /*!< 0x80000000 */
+#define COMP_CFGRx_LOCK              COMP_CFGRx_LOCK_Msk                       /*!< COMPx Lock Bit                        */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for USART_CR1 register  *******************/
+#define USART_CR1_UE_Pos                (0U)
+#define USART_CR1_UE_Msk                (0x1UL << USART_CR1_UE_Pos)            /*!< 0x00000001 */
+#define USART_CR1_UE                    USART_CR1_UE_Msk                       /*!< USART Enable */
+#define USART_CR1_UESM_Pos              (1U)
+#define USART_CR1_UESM_Msk              (0x1UL << USART_CR1_UESM_Pos)          /*!< 0x00000002 */
+#define USART_CR1_UESM                  USART_CR1_UESM_Msk                     /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE_Pos                (2U)
+#define USART_CR1_RE_Msk                (0x1UL << USART_CR1_RE_Pos)            /*!< 0x00000004 */
+#define USART_CR1_RE                    USART_CR1_RE_Msk                       /*!< Receiver Enable */
+#define USART_CR1_TE_Pos                (3U)
+#define USART_CR1_TE_Msk                (0x1UL << USART_CR1_TE_Pos)            /*!< 0x00000008 */
+#define USART_CR1_TE                    USART_CR1_TE_Msk                       /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos            (4U)
+#define USART_CR1_IDLEIE_Msk            (0x1UL << USART_CR1_IDLEIE_Pos)        /*!< 0x00000010 */
+#define USART_CR1_IDLEIE                USART_CR1_IDLEIE_Msk                   /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_RXFNEIE_Pos    (5U)
+#define USART_CR1_RXNEIE_RXFNEIE_Msk    (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE_RXFNEIE        USART_CR1_RXNEIE_RXFNEIE_Msk           /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
+#define USART_CR1_TCIE_Pos              (6U)
+#define USART_CR1_TCIE_Msk              (0x1UL << USART_CR1_TCIE_Pos)          /*!< 0x00000040 */
+#define USART_CR1_TCIE                  USART_CR1_TCIE_Msk                     /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_TXFNFIE_Pos     (7U)
+#define USART_CR1_TXEIE_TXFNFIE_Msk     (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE_TXFNFIE         USART_CR1_TXEIE_TXFNFIE_Msk            /*!< TXE and TX FIFO Not Full Interrupt Enable */
+#define USART_CR1_PEIE_Pos              (8U)
+#define USART_CR1_PEIE_Msk              (0x1UL << USART_CR1_PEIE_Pos)          /*!< 0x00000100 */
+#define USART_CR1_PEIE                  USART_CR1_PEIE_Msk                     /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos                (9U)
+#define USART_CR1_PS_Msk                (0x1UL << USART_CR1_PS_Pos)            /*!< 0x00000200 */
+#define USART_CR1_PS                    USART_CR1_PS_Msk                       /*!< Parity Selection */
+#define USART_CR1_PCE_Pos               (10U)
+#define USART_CR1_PCE_Msk               (0x1UL << USART_CR1_PCE_Pos)           /*!< 0x00000400 */
+#define USART_CR1_PCE                   USART_CR1_PCE_Msk                      /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos              (11U)
+#define USART_CR1_WAKE_Msk              (0x1UL << USART_CR1_WAKE_Pos)          /*!< 0x00000800 */
+#define USART_CR1_WAKE                  USART_CR1_WAKE_Msk                     /*!< Receiver Wakeup method */
+#define USART_CR1_M_Pos                 (12U)
+#define USART_CR1_M_Msk                 (0x10001UL << USART_CR1_M_Pos)         /*!< 0x10001000 */
+#define USART_CR1_M                     USART_CR1_M_Msk                        /*!< Word length */
+#define USART_CR1_M0_Pos                (12U)
+#define USART_CR1_M0_Msk                (0x1UL << USART_CR1_M0_Pos)            /*!< 0x00001000 */
+#define USART_CR1_M0                    USART_CR1_M0_Msk                       /*!< Word length - Bit 0 */
+#define USART_CR1_MME_Pos               (13U)
+#define USART_CR1_MME_Msk               (0x1UL << USART_CR1_MME_Pos)           /*!< 0x00002000 */
+#define USART_CR1_MME                   USART_CR1_MME_Msk                      /*!< Mute Mode Enable */
+#define USART_CR1_CMIE_Pos              (14U)
+#define USART_CR1_CMIE_Msk              (0x1UL << USART_CR1_CMIE_Pos)          /*!< 0x00004000 */
+#define USART_CR1_CMIE                  USART_CR1_CMIE_Msk                     /*!< Character match interrupt enable */
+#define USART_CR1_OVER8_Pos             (15U)
+#define USART_CR1_OVER8_Msk             (0x1UL << USART_CR1_OVER8_Pos)         /*!< 0x00008000 */
+#define USART_CR1_OVER8                 USART_CR1_OVER8_Msk                    /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT_Pos              (16U)
+#define USART_CR1_DEDT_Msk              (0x1FUL << USART_CR1_DEDT_Pos)         /*!< 0x001F0000 */
+#define USART_CR1_DEDT                  USART_CR1_DEDT_Msk                     /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0                (0x01UL << USART_CR1_DEDT_Pos)          /*!< 0x00010000 */
+#define USART_CR1_DEDT_1                (0x02UL << USART_CR1_DEDT_Pos)          /*!< 0x00020000 */
+#define USART_CR1_DEDT_2                (0x04UL << USART_CR1_DEDT_Pos)          /*!< 0x00040000 */
+#define USART_CR1_DEDT_3                (0x08UL << USART_CR1_DEDT_Pos)          /*!< 0x00080000 */
+#define USART_CR1_DEDT_4                (0x10UL << USART_CR1_DEDT_Pos)          /*!< 0x00100000 */
+#define USART_CR1_DEAT_Pos              (21U)
+#define USART_CR1_DEAT_Msk              (0x1FUL << USART_CR1_DEAT_Pos)         /*!< 0x03E00000 */
+#define USART_CR1_DEAT                  USART_CR1_DEAT_Msk                     /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0                (0x01UL << USART_CR1_DEAT_Pos)          /*!< 0x00200000 */
+#define USART_CR1_DEAT_1                (0x02UL << USART_CR1_DEAT_Pos)          /*!< 0x00400000 */
+#define USART_CR1_DEAT_2                (0x04UL << USART_CR1_DEAT_Pos)          /*!< 0x00800000 */
+#define USART_CR1_DEAT_3                (0x08UL << USART_CR1_DEAT_Pos)          /*!< 0x01000000 */
+#define USART_CR1_DEAT_4                (0x10UL << USART_CR1_DEAT_Pos)          /*!< 0x02000000 */
+#define USART_CR1_RTOIE_Pos             (26U)
+#define USART_CR1_RTOIE_Msk             (0x1UL << USART_CR1_RTOIE_Pos)         /*!< 0x04000000 */
+#define USART_CR1_RTOIE                 USART_CR1_RTOIE_Msk                    /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE_Pos             (27U)
+#define USART_CR1_EOBIE_Msk             (0x1UL << USART_CR1_EOBIE_Pos)         /*!< 0x08000000 */
+#define USART_CR1_EOBIE                 USART_CR1_EOBIE_Msk                    /*!< End of Block interrupt enable */
+#define USART_CR1_M1_Pos                (28U)
+#define USART_CR1_M1_Msk                (0x1UL << USART_CR1_M1_Pos)            /*!< 0x10000000 */
+#define USART_CR1_M1                    USART_CR1_M1_Msk                       /*!< Word length - Bit 1 */
+#define USART_CR1_FIFOEN_Pos            (29U)
+#define USART_CR1_FIFOEN_Msk            (0x1UL << USART_CR1_FIFOEN_Pos)        /*!< 0x20000000 */
+#define USART_CR1_FIFOEN                USART_CR1_FIFOEN_Msk                   /*!< FIFO mode enable */
+#define USART_CR1_TXFEIE_Pos            (30U)
+#define USART_CR1_TXFEIE_Msk            (0x1UL << USART_CR1_TXFEIE_Pos)        /*!< 0x40000000 */
+#define USART_CR1_TXFEIE                USART_CR1_TXFEIE_Msk                   /*!< TXFIFO empty interrupt enable */
+#define USART_CR1_RXFFIE_Pos            (31U)
+#define USART_CR1_RXFFIE_Msk            (0x1UL << USART_CR1_RXFFIE_Pos)        /*!< 0x80000000 */
+#define USART_CR1_RXFFIE                USART_CR1_RXFFIE_Msk                   /*!< RXFIFO Full interrupt enable */
+
+/* Legacy define */
+#define  USART_CR1_RXNEIE  USART_CR1_RXNEIE_RXFNEIE
+#define  USART_CR1_TXEIE   USART_CR1_TXEIE_TXFNFIE
+
+/******************  Bit definition for USART_CR2 register  *******************/
+#define USART_CR2_SLVEN_Pos             (0U)
+#define USART_CR2_SLVEN_Msk             (0x1UL << USART_CR2_SLVEN_Pos)         /*!< 0x00000001 */
+#define USART_CR2_SLVEN                 USART_CR2_SLVEN_Msk                    /*!< Synchronous Slave mode Enable */
+#define USART_CR2_DIS_NSS_Pos           (3U)
+#define USART_CR2_DIS_NSS_Msk           (0x1UL << USART_CR2_DIS_NSS_Pos)       /*!< 0x00000008 */
+#define USART_CR2_DIS_NSS               USART_CR2_DIS_NSS_Msk                  /*!< Negative Slave Select (NSS) pin management */
+#define USART_CR2_ADDM7_Pos             (4U)
+#define USART_CR2_ADDM7_Msk             (0x1UL << USART_CR2_ADDM7_Pos)         /*!< 0x00000010 */
+#define USART_CR2_ADDM7                 USART_CR2_ADDM7_Msk                    /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL_Pos              (5U)
+#define USART_CR2_LBDL_Msk              (0x1UL << USART_CR2_LBDL_Pos)          /*!< 0x00000020 */
+#define USART_CR2_LBDL                  USART_CR2_LBDL_Msk                     /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos             (6U)
+#define USART_CR2_LBDIE_Msk             (0x1UL << USART_CR2_LBDIE_Pos)         /*!< 0x00000040 */
+#define USART_CR2_LBDIE                 USART_CR2_LBDIE_Msk                    /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos              (8U)
+#define USART_CR2_LBCL_Msk              (0x1UL << USART_CR2_LBCL_Pos)          /*!< 0x00000100 */
+#define USART_CR2_LBCL                  USART_CR2_LBCL_Msk                     /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos              (9U)
+#define USART_CR2_CPHA_Msk              (0x1UL << USART_CR2_CPHA_Pos)          /*!< 0x00000200 */
+#define USART_CR2_CPHA                  USART_CR2_CPHA_Msk                     /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos              (10U)
+#define USART_CR2_CPOL_Msk              (0x1UL << USART_CR2_CPOL_Pos)          /*!< 0x00000400 */
+#define USART_CR2_CPOL                  USART_CR2_CPOL_Msk                     /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos             (11U)
+#define USART_CR2_CLKEN_Msk             (0x1UL << USART_CR2_CLKEN_Pos)         /*!< 0x00000800 */
+#define USART_CR2_CLKEN                 USART_CR2_CLKEN_Msk                    /*!< Clock Enable */
+#define USART_CR2_STOP_Pos              (12U)
+#define USART_CR2_STOP_Msk              (0x3UL << USART_CR2_STOP_Pos)          /*!< 0x00003000 */
+#define USART_CR2_STOP                  USART_CR2_STOP_Msk                     /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0                (0x1UL << USART_CR2_STOP_Pos)           /*!< 0x00001000 */
+#define USART_CR2_STOP_1                (0x2UL << USART_CR2_STOP_Pos)           /*!< 0x00002000 */
+#define USART_CR2_LINEN_Pos             (14U)
+#define USART_CR2_LINEN_Msk             (0x1UL << USART_CR2_LINEN_Pos)         /*!< 0x00004000 */
+#define USART_CR2_LINEN                 USART_CR2_LINEN_Msk                    /*!< LIN mode enable */
+#define USART_CR2_SWAP_Pos              (15U)
+#define USART_CR2_SWAP_Msk              (0x1UL << USART_CR2_SWAP_Pos)          /*!< 0x00008000 */
+#define USART_CR2_SWAP                  USART_CR2_SWAP_Msk                     /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV_Pos             (16U)
+#define USART_CR2_RXINV_Msk             (0x1UL << USART_CR2_RXINV_Pos)         /*!< 0x00010000 */
+#define USART_CR2_RXINV                 USART_CR2_RXINV_Msk                    /*!< RX pin active level inversion */
+#define USART_CR2_TXINV_Pos             (17U)
+#define USART_CR2_TXINV_Msk             (0x1UL << USART_CR2_TXINV_Pos)         /*!< 0x00020000 */
+#define USART_CR2_TXINV                 USART_CR2_TXINV_Msk                    /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV_Pos           (18U)
+#define USART_CR2_DATAINV_Msk           (0x1UL << USART_CR2_DATAINV_Pos)       /*!< 0x00040000 */
+#define USART_CR2_DATAINV               USART_CR2_DATAINV_Msk                  /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST_Pos          (19U)
+#define USART_CR2_MSBFIRST_Msk          (0x1UL << USART_CR2_MSBFIRST_Pos)      /*!< 0x00080000 */
+#define USART_CR2_MSBFIRST              USART_CR2_MSBFIRST_Msk                 /*!< Most Significant Bit First */
+#define USART_CR2_ABREN_Pos             (20U)
+#define USART_CR2_ABREN_Msk             (0x1UL << USART_CR2_ABREN_Pos)         /*!< 0x00100000 */
+#define USART_CR2_ABREN                 USART_CR2_ABREN_Msk                    /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE_Pos           (21U)
+#define USART_CR2_ABRMODE_Msk           (0x3UL << USART_CR2_ABRMODE_Pos)       /*!< 0x00600000 */
+#define USART_CR2_ABRMODE               USART_CR2_ABRMODE_Msk                  /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0             (0x1UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00200000 */
+#define USART_CR2_ABRMODE_1             (0x2UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00400000 */
+#define USART_CR2_RTOEN_Pos             (23U)
+#define USART_CR2_RTOEN_Msk             (0x1UL << USART_CR2_RTOEN_Pos)         /*!< 0x00800000 */
+#define USART_CR2_RTOEN                 USART_CR2_RTOEN_Msk                    /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD_Pos               (24U)
+#define USART_CR2_ADD_Msk               (0xFFUL << USART_CR2_ADD_Pos)          /*!< 0xFF000000 */
+#define USART_CR2_ADD                   USART_CR2_ADD_Msk                      /*!< Address of the USART node */
+
+/******************  Bit definition for USART_CR3 register  *******************/
+#define USART_CR3_EIE_Pos               (0U)
+#define USART_CR3_EIE_Msk               (0x1UL << USART_CR3_EIE_Pos)           /*!< 0x00000001 */
+#define USART_CR3_EIE                   USART_CR3_EIE_Msk                      /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos              (1U)
+#define USART_CR3_IREN_Msk              (0x1UL << USART_CR3_IREN_Pos)          /*!< 0x00000002 */
+#define USART_CR3_IREN                  USART_CR3_IREN_Msk                     /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos              (2U)
+#define USART_CR3_IRLP_Msk              (0x1UL << USART_CR3_IRLP_Pos)          /*!< 0x00000004 */
+#define USART_CR3_IRLP                  USART_CR3_IRLP_Msk                     /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos             (3U)
+#define USART_CR3_HDSEL_Msk             (0x1UL << USART_CR3_HDSEL_Pos)         /*!< 0x00000008 */
+#define USART_CR3_HDSEL                 USART_CR3_HDSEL_Msk                    /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos              (4U)
+#define USART_CR3_NACK_Msk              (0x1UL << USART_CR3_NACK_Pos)          /*!< 0x00000010 */
+#define USART_CR3_NACK                  USART_CR3_NACK_Msk                     /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN_Pos              (5U)
+#define USART_CR3_SCEN_Msk              (0x1UL << USART_CR3_SCEN_Pos)          /*!< 0x00000020 */
+#define USART_CR3_SCEN                  USART_CR3_SCEN_Msk                     /*!< SmartCard mode enable */
+#define USART_CR3_DMAR_Pos              (6U)
+#define USART_CR3_DMAR_Msk              (0x1UL << USART_CR3_DMAR_Pos)          /*!< 0x00000040 */
+#define USART_CR3_DMAR                  USART_CR3_DMAR_Msk                     /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos              (7U)
+#define USART_CR3_DMAT_Msk              (0x1UL << USART_CR3_DMAT_Pos)          /*!< 0x00000080 */
+#define USART_CR3_DMAT                  USART_CR3_DMAT_Msk                     /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos              (8U)
+#define USART_CR3_RTSE_Msk              (0x1UL << USART_CR3_RTSE_Pos)          /*!< 0x00000100 */
+#define USART_CR3_RTSE                  USART_CR3_RTSE_Msk                     /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos              (9U)
+#define USART_CR3_CTSE_Msk              (0x1UL << USART_CR3_CTSE_Pos)          /*!< 0x00000200 */
+#define USART_CR3_CTSE                  USART_CR3_CTSE_Msk                     /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos             (10U)
+#define USART_CR3_CTSIE_Msk             (0x1UL << USART_CR3_CTSIE_Pos)         /*!< 0x00000400 */
+#define USART_CR3_CTSIE                 USART_CR3_CTSIE_Msk                    /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos            (11U)
+#define USART_CR3_ONEBIT_Msk            (0x1UL << USART_CR3_ONEBIT_Pos)        /*!< 0x00000800 */
+#define USART_CR3_ONEBIT                USART_CR3_ONEBIT_Msk                   /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS_Pos            (12U)
+#define USART_CR3_OVRDIS_Msk            (0x1UL << USART_CR3_OVRDIS_Pos)        /*!< 0x00001000 */
+#define USART_CR3_OVRDIS                USART_CR3_OVRDIS_Msk                   /*!< Overrun Disable */
+#define USART_CR3_DDRE_Pos              (13U)
+#define USART_CR3_DDRE_Msk              (0x1UL << USART_CR3_DDRE_Pos)          /*!< 0x00002000 */
+#define USART_CR3_DDRE                  USART_CR3_DDRE_Msk                     /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM_Pos               (14U)
+#define USART_CR3_DEM_Msk               (0x1UL << USART_CR3_DEM_Pos)           /*!< 0x00004000 */
+#define USART_CR3_DEM                   USART_CR3_DEM_Msk                      /*!< Driver Enable Mode */
+#define USART_CR3_DEP_Pos               (15U)
+#define USART_CR3_DEP_Msk               (0x1UL << USART_CR3_DEP_Pos)           /*!< 0x00008000 */
+#define USART_CR3_DEP                   USART_CR3_DEP_Msk                      /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT_Pos           (17U)
+#define USART_CR3_SCARCNT_Msk           (0x7UL << USART_CR3_SCARCNT_Pos)       /*!< 0x000E0000 */
+#define USART_CR3_SCARCNT               USART_CR3_SCARCNT_Msk                  /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0             (0x1UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00020000 */
+#define USART_CR3_SCARCNT_1             (0x2UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00040000 */
+#define USART_CR3_SCARCNT_2             (0x4UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00080000 */
+#define USART_CR3_WUS_Pos               (20U)
+#define USART_CR3_WUS_Msk               (0x3UL << USART_CR3_WUS_Pos)           /*!< 0x00300000 */
+#define USART_CR3_WUS                   USART_CR3_WUS_Msk                      /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0                 (0x1UL << USART_CR3_WUS_Pos)            /*!< 0x00100000 */
+#define USART_CR3_WUS_1                 (0x2UL << USART_CR3_WUS_Pos)            /*!< 0x00200000 */
+#define USART_CR3_WUFIE_Pos             (22U)
+#define USART_CR3_WUFIE_Msk             (0x1UL << USART_CR3_WUFIE_Pos)         /*!< 0x00400000 */
+#define USART_CR3_WUFIE                 USART_CR3_WUFIE_Msk                    /*!< Wake Up Interrupt Enable */
+#define USART_CR3_TXFTIE_Pos            (23U)
+#define USART_CR3_TXFTIE_Msk            (0x1UL << USART_CR3_TXFTIE_Pos)        /*!< 0x00800000 */
+#define USART_CR3_TXFTIE                USART_CR3_TXFTIE_Msk                   /*!< TXFIFO threshold interrupt enable */
+#define USART_CR3_TCBGTIE_Pos           (24U)
+#define USART_CR3_TCBGTIE_Msk           (0x1UL << USART_CR3_TCBGTIE_Pos)       /*!< 0x01000000 */
+#define USART_CR3_TCBGTIE               USART_CR3_TCBGTIE_Msk                  /*!< Transmission Complete before guard time, interrupt enable */
+#define USART_CR3_RXFTCFG_Pos           (25U)
+#define USART_CR3_RXFTCFG_Msk           (0x7UL << USART_CR3_RXFTCFG_Pos)       /*!< 0x0E000000 */
+#define USART_CR3_RXFTCFG               USART_CR3_RXFTCFG_Msk                  /*!< RXFTCFG [2:0]Receive FIFO threshold configuration */
+#define USART_CR3_RXFTCFG_0             (0x1UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x02000000 */
+#define USART_CR3_RXFTCFG_1             (0x2UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x04000000 */
+#define USART_CR3_RXFTCFG_2             (0x4UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x08000000 */
+#define USART_CR3_RXFTIE_Pos            (28U)
+#define USART_CR3_RXFTIE_Msk            (0x1UL << USART_CR3_RXFTIE_Pos)        /*!< 0x10000000 */
+#define USART_CR3_RXFTIE                USART_CR3_RXFTIE_Msk                   /*!< RXFIFO threshold interrupt enable */
+#define USART_CR3_TXFTCFG_Pos           (29U)
+#define USART_CR3_TXFTCFG_Msk           (0x7UL << USART_CR3_TXFTCFG_Pos)       /*!< 0xE0000000 */
+#define USART_CR3_TXFTCFG               USART_CR3_TXFTCFG_Msk                  /*!< TXFIFO [2:0] threshold configuration */
+#define USART_CR3_TXFTCFG_0             (0x1UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x20000000 */
+#define USART_CR3_TXFTCFG_1             (0x2UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x40000000 */
+#define USART_CR3_TXFTCFG_2             (0x4UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x80000000 */
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define USART_BRR_DIV_FRACTION_Pos      (0U)
+#define USART_BRR_DIV_FRACTION_Msk      (0xFUL << USART_BRR_DIV_FRACTION_Pos)  /*!< 0x0000000F */
+#define USART_BRR_DIV_FRACTION          USART_BRR_DIV_FRACTION_Msk             /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA_Pos      (4U)
+#define USART_BRR_DIV_MANTISSA_Msk      (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_MANTISSA          USART_BRR_DIV_MANTISSA_Msk             /*!< Mantissa of USARTDIV */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define USART_GTPR_PSC_Pos              (0U)
+#define USART_GTPR_PSC_Msk              (0xFFUL << USART_GTPR_PSC_Pos)         /*!< 0x000000FF */
+#define USART_GTPR_PSC                  USART_GTPR_PSC_Msk                     /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT_Pos               (8U)
+#define USART_GTPR_GT_Msk               (0xFFUL << USART_GTPR_GT_Pos)          /*!< 0x0000FF00 */
+#define USART_GTPR_GT                   USART_GTPR_GT_Msk                      /*!< GT[7:0] bits (Guard time value) */
+
+/*******************  Bit definition for USART_RTOR register  *****************/
+#define USART_RTOR_RTO_Pos              (0U)
+#define USART_RTOR_RTO_Msk              (0xFFFFFFUL << USART_RTOR_RTO_Pos)     /*!< 0x00FFFFFF */
+#define USART_RTOR_RTO                  USART_RTOR_RTO_Msk                     /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN_Pos             (24U)
+#define USART_RTOR_BLEN_Msk             (0xFFUL << USART_RTOR_BLEN_Pos)        /*!< 0xFF000000 */
+#define USART_RTOR_BLEN                 USART_RTOR_BLEN_Msk                    /*!< Block Length */
+
+/*******************  Bit definition for USART_RQR register  ******************/
+#define USART_RQR_ABRRQ_Pos             (0U)
+#define USART_RQR_ABRRQ_Msk             (0x1UL << USART_RQR_ABRRQ_Pos)         /*!< 0x00000001 */
+#define USART_RQR_ABRRQ                 USART_RQR_ABRRQ_Msk                    /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ_Pos             (1U)
+#define USART_RQR_SBKRQ_Msk             (0x1UL << USART_RQR_SBKRQ_Pos)         /*!< 0x00000002 */
+#define USART_RQR_SBKRQ                 USART_RQR_SBKRQ_Msk                    /*!< Send Break Request */
+#define USART_RQR_MMRQ_Pos              (2U)
+#define USART_RQR_MMRQ_Msk              (0x1UL << USART_RQR_MMRQ_Pos)          /*!< 0x00000004 */
+#define USART_RQR_MMRQ                  USART_RQR_MMRQ_Msk                     /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ_Pos             (3U)
+#define USART_RQR_RXFRQ_Msk             (0x1UL << USART_RQR_RXFRQ_Pos)         /*!< 0x00000008 */
+#define USART_RQR_RXFRQ                 USART_RQR_RXFRQ_Msk                    /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ_Pos             (4U)
+#define USART_RQR_TXFRQ_Msk             (0x1UL << USART_RQR_TXFRQ_Pos)         /*!< 0x00000010 */
+#define USART_RQR_TXFRQ                 USART_RQR_TXFRQ_Msk                    /*!< Transmit data flush Request */
+
+/*******************  Bit definition for USART_ISR register  ******************/
+#define USART_ISR_PE_Pos                (0U)
+#define USART_ISR_PE_Msk                (0x1UL << USART_ISR_PE_Pos)            /*!< 0x00000001 */
+#define USART_ISR_PE                    USART_ISR_PE_Msk                       /*!< Parity Error */
+#define USART_ISR_FE_Pos                (1U)
+#define USART_ISR_FE_Msk                (0x1UL << USART_ISR_FE_Pos)            /*!< 0x00000002 */
+#define USART_ISR_FE                    USART_ISR_FE_Msk                       /*!< Framing Error */
+#define USART_ISR_NE_Pos                (2U)
+#define USART_ISR_NE_Msk                (0x1UL << USART_ISR_NE_Pos)            /*!< 0x00000004 */
+#define USART_ISR_NE                    USART_ISR_NE_Msk                       /*!< Noise detected Flag */
+#define USART_ISR_ORE_Pos               (3U)
+#define USART_ISR_ORE_Msk               (0x1UL << USART_ISR_ORE_Pos)           /*!< 0x00000008 */
+#define USART_ISR_ORE                   USART_ISR_ORE_Msk                      /*!< OverRun Error */
+#define USART_ISR_IDLE_Pos              (4U)
+#define USART_ISR_IDLE_Msk              (0x1UL << USART_ISR_IDLE_Pos)          /*!< 0x00000010 */
+#define USART_ISR_IDLE                  USART_ISR_IDLE_Msk                     /*!< IDLE line detected */
+#define USART_ISR_RXNE_RXFNE_Pos        (5U)
+#define USART_ISR_RXNE_RXFNE_Msk        (0x1UL << USART_ISR_RXNE_RXFNE_Pos)    /*!< 0x00000020 */
+#define USART_ISR_RXNE_RXFNE            USART_ISR_RXNE_RXFNE_Msk               /*!< Read Data Register or RX FIFO Not Empty */
+#define USART_ISR_TC_Pos                (6U)
+#define USART_ISR_TC_Msk                (0x1UL << USART_ISR_TC_Pos)            /*!< 0x00000040 */
+#define USART_ISR_TC                    USART_ISR_TC_Msk                       /*!< Transmission Complete */
+#define USART_ISR_TXE_TXFNF_Pos         (7U)
+#define USART_ISR_TXE_TXFNF_Msk         (0x1UL << USART_ISR_TXE_TXFNF_Pos)     /*!< 0x00000080 */
+#define USART_ISR_TXE_TXFNF             USART_ISR_TXE_TXFNF_Msk                /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
+#define USART_ISR_LBDF_Pos              (8U)
+#define USART_ISR_LBDF_Msk              (0x1UL << USART_ISR_LBDF_Pos)          /*!< 0x00000100 */
+#define USART_ISR_LBDF                  USART_ISR_LBDF_Msk                     /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF_Pos             (9U)
+#define USART_ISR_CTSIF_Msk             (0x1UL << USART_ISR_CTSIF_Pos)         /*!< 0x00000200 */
+#define USART_ISR_CTSIF                 USART_ISR_CTSIF_Msk                    /*!< CTS interrupt flag */
+#define USART_ISR_CTS_Pos               (10U)
+#define USART_ISR_CTS_Msk               (0x1UL << USART_ISR_CTS_Pos)           /*!< 0x00000400 */
+#define USART_ISR_CTS                   USART_ISR_CTS_Msk                      /*!< CTS flag */
+#define USART_ISR_RTOF_Pos              (11U)
+#define USART_ISR_RTOF_Msk              (0x1UL << USART_ISR_RTOF_Pos)          /*!< 0x00000800 */
+#define USART_ISR_RTOF                  USART_ISR_RTOF_Msk                     /*!< Receiver Time Out */
+#define USART_ISR_EOBF_Pos              (12U)
+#define USART_ISR_EOBF_Msk              (0x1UL << USART_ISR_EOBF_Pos)          /*!< 0x00001000 */
+#define USART_ISR_EOBF                  USART_ISR_EOBF_Msk                     /*!< End Of Block Flag */
+#define USART_ISR_UDR_Pos               (13U)
+#define USART_ISR_UDR_Msk               (0x1UL << USART_ISR_UDR_Pos)           /*!< 0x00002000 */
+#define USART_ISR_UDR                   USART_ISR_UDR_Msk                      /*!< SPI slave underrun error flag */
+#define USART_ISR_ABRE_Pos              (14U)
+#define USART_ISR_ABRE_Msk              (0x1UL << USART_ISR_ABRE_Pos)          /*!< 0x00004000 */
+#define USART_ISR_ABRE                  USART_ISR_ABRE_Msk                     /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF_Pos              (15U)
+#define USART_ISR_ABRF_Msk              (0x1UL << USART_ISR_ABRF_Pos)          /*!< 0x00008000 */
+#define USART_ISR_ABRF                  USART_ISR_ABRF_Msk                     /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY_Pos              (16U)
+#define USART_ISR_BUSY_Msk              (0x1UL << USART_ISR_BUSY_Pos)          /*!< 0x00010000 */
+#define USART_ISR_BUSY                  USART_ISR_BUSY_Msk                     /*!< Busy Flag */
+#define USART_ISR_CMF_Pos               (17U)
+#define USART_ISR_CMF_Msk               (0x1UL << USART_ISR_CMF_Pos)           /*!< 0x00020000 */
+#define USART_ISR_CMF                   USART_ISR_CMF_Msk                      /*!< Character Match Flag */
+#define USART_ISR_SBKF_Pos              (18U)
+#define USART_ISR_SBKF_Msk              (0x1UL << USART_ISR_SBKF_Pos)          /*!< 0x00040000 */
+#define USART_ISR_SBKF                  USART_ISR_SBKF_Msk                     /*!< Send Break Flag */
+#define USART_ISR_RWU_Pos               (19U)
+#define USART_ISR_RWU_Msk               (0x1UL << USART_ISR_RWU_Pos)           /*!< 0x00080000 */
+#define USART_ISR_RWU                   USART_ISR_RWU_Msk                      /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF_Pos               (20U)
+#define USART_ISR_WUF_Msk               (0x1UL << USART_ISR_WUF_Pos)           /*!< 0x00100000 */
+#define USART_ISR_WUF                   USART_ISR_WUF_Msk                      /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK_Pos             (21U)
+#define USART_ISR_TEACK_Msk             (0x1UL << USART_ISR_TEACK_Pos)         /*!< 0x00200000 */
+#define USART_ISR_TEACK                 USART_ISR_TEACK_Msk                    /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK_Pos             (22U)
+#define USART_ISR_REACK_Msk             (0x1UL << USART_ISR_REACK_Pos)         /*!< 0x00400000 */
+#define USART_ISR_REACK                 USART_ISR_REACK_Msk                    /*!< Receive Enable Acknowledge Flag */
+#define USART_ISR_TXFE_Pos              (23U)
+#define USART_ISR_TXFE_Msk              (0x1UL << USART_ISR_TXFE_Pos)          /*!< 0x00800000 */
+#define USART_ISR_TXFE                  USART_ISR_TXFE_Msk                     /*!< TXFIFO Empty */
+#define USART_ISR_RXFF_Pos              (24U)
+#define USART_ISR_RXFF_Msk              (0x1UL << USART_ISR_RXFF_Pos)          /*!< 0x01000000 */
+#define USART_ISR_RXFF                  USART_ISR_RXFF_Msk                     /*!< RXFIFO Full Flag */
+#define USART_ISR_TCBGT_Pos             (25U)
+#define USART_ISR_TCBGT_Msk             (0x1UL << USART_ISR_TCBGT_Pos)         /*!< 0x02000000 */
+#define USART_ISR_TCBGT                 USART_ISR_TCBGT_Msk                    /*!< Transmission complete before guard time Flag */
+#define USART_ISR_RXFT_Pos              (26U)
+#define USART_ISR_RXFT_Msk              (0x1UL << USART_ISR_RXFT_Pos)          /*!< 0x04000000 */
+#define USART_ISR_RXFT                  USART_ISR_RXFT_Msk                     /*!< RXFIFO threshold Flag */
+#define USART_ISR_TXFT_Pos              (27U)
+#define USART_ISR_TXFT_Msk              (0x1UL << USART_ISR_TXFT_Pos)          /*!< 0x08000000 */
+#define USART_ISR_TXFT                  USART_ISR_TXFT_Msk                     /*!< TXFIFO threshold Flag */
+
+/*******************  Bit definition for USART_ICR register  ******************/
+#define USART_ICR_PECF_Pos              (0U)
+#define USART_ICR_PECF_Msk              (0x1UL << USART_ICR_PECF_Pos)          /*!< 0x00000001 */
+#define USART_ICR_PECF                  USART_ICR_PECF_Msk                     /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF_Pos              (1U)
+#define USART_ICR_FECF_Msk              (0x1UL << USART_ICR_FECF_Pos)          /*!< 0x00000002 */
+#define USART_ICR_FECF                  USART_ICR_FECF_Msk                     /*!< Framing Error Clear Flag */
+#define USART_ICR_NECF_Pos              (2U)
+#define USART_ICR_NECF_Msk              (0x1UL << USART_ICR_NECF_Pos)          /*!< 0x00000004 */
+#define USART_ICR_NECF                  USART_ICR_NECF_Msk                     /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF_Pos             (3U)
+#define USART_ICR_ORECF_Msk             (0x1UL << USART_ICR_ORECF_Pos)         /*!< 0x00000008 */
+#define USART_ICR_ORECF                 USART_ICR_ORECF_Msk                    /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF_Pos            (4U)
+#define USART_ICR_IDLECF_Msk            (0x1UL << USART_ICR_IDLECF_Pos)        /*!< 0x00000010 */
+#define USART_ICR_IDLECF                USART_ICR_IDLECF_Msk                   /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TXFECF_Pos            (5U)
+#define USART_ICR_TXFECF_Msk            (0x1UL << USART_ICR_TXFECF_Pos)        /*!< 0x00000020 */
+#define USART_ICR_TXFECF                USART_ICR_TXFECF_Msk                   /*!< TXFIFO empty clear flag */
+#define USART_ICR_TCCF_Pos              (6U)
+#define USART_ICR_TCCF_Msk              (0x1UL << USART_ICR_TCCF_Pos)          /*!< 0x00000040 */
+#define USART_ICR_TCCF                  USART_ICR_TCCF_Msk                     /*!< Transmission Complete Clear Flag */
+#define USART_ICR_TCBGTCF_Pos           (7U)
+#define USART_ICR_TCBGTCF_Msk           (0x1UL << USART_ICR_TCBGTCF_Pos)       /*!< 0x00000080 */
+#define USART_ICR_TCBGTCF               USART_ICR_TCBGTCF_Msk                  /*!< Transmission complete before guard time Clear Flag */
+#define USART_ICR_LBDCF_Pos             (8U)
+#define USART_ICR_LBDCF_Msk             (0x1UL << USART_ICR_LBDCF_Pos)         /*!< 0x00000100 */
+#define USART_ICR_LBDCF                 USART_ICR_LBDCF_Msk                    /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF_Pos             (9U)
+#define USART_ICR_CTSCF_Msk             (0x1UL << USART_ICR_CTSCF_Pos)         /*!< 0x00000200 */
+#define USART_ICR_CTSCF                 USART_ICR_CTSCF_Msk                    /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF_Pos             (11U)
+#define USART_ICR_RTOCF_Msk             (0x1UL << USART_ICR_RTOCF_Pos)         /*!< 0x00000800 */
+#define USART_ICR_RTOCF                 USART_ICR_RTOCF_Msk                    /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF_Pos             (12U)
+#define USART_ICR_EOBCF_Msk             (0x1UL << USART_ICR_EOBCF_Pos)         /*!< 0x00001000 */
+#define USART_ICR_EOBCF                 USART_ICR_EOBCF_Msk                    /*!< End Of Block Clear Flag */
+#define USART_ICR_UDRCF_Pos             (13U)
+#define USART_ICR_UDRCF_Msk             (0x1UL << USART_ICR_UDRCF_Pos)         /*!< 0x00002000 */
+#define USART_ICR_UDRCF                 USART_ICR_UDRCF_Msk                    /*!< SPI slave underrun clear flag */
+#define USART_ICR_CMCF_Pos              (17U)
+#define USART_ICR_CMCF_Msk              (0x1UL << USART_ICR_CMCF_Pos)          /*!< 0x00020000 */
+#define USART_ICR_CMCF                  USART_ICR_CMCF_Msk                     /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF_Pos              (20U)
+#define USART_ICR_WUCF_Msk              (0x1UL << USART_ICR_WUCF_Pos)          /*!< 0x00100000 */
+#define USART_ICR_WUCF                  USART_ICR_WUCF_Msk                     /*!< Wake Up from stop mode Clear Flag */
+
+/*******************  Bit definition for USART_RDR register  ******************/
+#define USART_RDR_RDR_Pos               (0U)
+#define USART_RDR_RDR_Msk               (0x1FFUL << USART_RDR_RDR_Pos)         /*!< 0x000001FF */
+#define USART_RDR_RDR                   USART_RDR_RDR_Msk                      /*!< RDR[8:0] bits (Receive Data value) */
+
+/*******************  Bit definition for USART_TDR register  ******************/
+#define USART_TDR_TDR_Pos               (0U)
+#define USART_TDR_TDR_Msk               (0x1FFUL << USART_TDR_TDR_Pos)         /*!< 0x000001FF */
+#define USART_TDR_TDR                   USART_TDR_TDR_Msk                      /*!< TDR[8:0] bits (Transmit Data value) */
+
+/*******************  Bit definition for USART_PRESC register  ******************/
+#define USART_PRESC_PRESCALER_Pos       (0U)
+#define USART_PRESC_PRESCALER_Msk       (0xFUL << USART_PRESC_PRESCALER_Pos)   /*!< 0x0000000F */
+#define USART_PRESC_PRESCALER           USART_PRESC_PRESCALER_Msk              /*!< PRESCALER[3:0] bits (Clock prescaler) */
+#define USART_PRESC_PRESCALER_0         (0x1UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000001 */
+#define USART_PRESC_PRESCALER_1         (0x2UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000002 */
+#define USART_PRESC_PRESCALER_2         (0x4UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000004 */
+#define USART_PRESC_PRESCALER_3         (0x8UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000008 */
+
+/******************************************************************************/
+/*                                                                            */
+/*           Single Wire Protocol Master Interface (SWPMI)                    */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for SWPMI_CR register   ********************/
+#define SWPMI_CR_RXDMA_Pos       (0U)
+#define SWPMI_CR_RXDMA_Msk       (0x1UL << SWPMI_CR_RXDMA_Pos)                 /*!< 0x00000001 */
+#define SWPMI_CR_RXDMA           SWPMI_CR_RXDMA_Msk                            /*!<Reception DMA enable                                 */
+#define SWPMI_CR_TXDMA_Pos       (1U)
+#define SWPMI_CR_TXDMA_Msk       (0x1UL << SWPMI_CR_TXDMA_Pos)                 /*!< 0x00000002 */
+#define SWPMI_CR_TXDMA           SWPMI_CR_TXDMA_Msk                            /*!<Transmission DMA enable                              */
+#define SWPMI_CR_RXMODE_Pos      (2U)
+#define SWPMI_CR_RXMODE_Msk      (0x1UL << SWPMI_CR_RXMODE_Pos)                /*!< 0x00000004 */
+#define SWPMI_CR_RXMODE          SWPMI_CR_RXMODE_Msk                           /*!<Reception buffering mode                             */
+#define SWPMI_CR_TXMODE_Pos      (3U)
+#define SWPMI_CR_TXMODE_Msk      (0x1UL << SWPMI_CR_TXMODE_Pos)                /*!< 0x00000008 */
+#define SWPMI_CR_TXMODE          SWPMI_CR_TXMODE_Msk                           /*!<Transmission buffering mode                          */
+#define SWPMI_CR_LPBK_Pos        (4U)
+#define SWPMI_CR_LPBK_Msk        (0x1UL << SWPMI_CR_LPBK_Pos)                  /*!< 0x00000010 */
+#define SWPMI_CR_LPBK            SWPMI_CR_LPBK_Msk                             /*!<Loopback mode enable                                 */
+#define SWPMI_CR_SWPACT_Pos      (5U)
+#define SWPMI_CR_SWPACT_Msk      (0x1UL << SWPMI_CR_SWPACT_Pos)                /*!< 0x00000020 */
+#define SWPMI_CR_SWPACT          SWPMI_CR_SWPACT_Msk                           /*!<Single wire protocol master interface activate       */
+#define SWPMI_CR_DEACT_Pos       (10U)
+#define SWPMI_CR_DEACT_Msk       (0x1UL << SWPMI_CR_DEACT_Pos)                 /*!< 0x00000400 */
+#define SWPMI_CR_DEACT           SWPMI_CR_DEACT_Msk                            /*!<Single wire protocol master interface deactivate     */
+#define SWPMI_CR_SWPEN_Pos       (11U)
+#define SWPMI_CR_SWPEN_Msk       (0x1UL << SWPMI_CR_SWPEN_Pos)                 /*!< 0x00000800 */
+#define SWPMI_CR_SWPEN           SWPMI_CR_SWPEN_Msk                            /*!<Single wire protocol master transceiver enable       */
+
+/*******************  Bit definition for SWPMI_BRR register  ********************/
+#define SWPMI_BRR_BR_Pos         (0U)
+#define SWPMI_BRR_BR_Msk         (0xFFUL << SWPMI_BRR_BR_Pos)                  /*!< 0x000000FF */
+#define SWPMI_BRR_BR             SWPMI_BRR_BR_Msk                              /*!<BR[7:0] bits (Bitrate prescaler) */
+
+/*******************  Bit definition for SWPMI_ISR register  ********************/
+#define SWPMI_ISR_RXBFF_Pos      (0U)
+#define SWPMI_ISR_RXBFF_Msk      (0x1UL << SWPMI_ISR_RXBFF_Pos)                /*!< 0x00000001 */
+#define SWPMI_ISR_RXBFF          SWPMI_ISR_RXBFF_Msk                           /*!<Receive buffer full flag        */
+#define SWPMI_ISR_TXBEF_Pos      (1U)
+#define SWPMI_ISR_TXBEF_Msk      (0x1UL << SWPMI_ISR_TXBEF_Pos)                /*!< 0x00000002 */
+#define SWPMI_ISR_TXBEF          SWPMI_ISR_TXBEF_Msk                           /*!<Transmit buffer empty flag      */
+#define SWPMI_ISR_RXBERF_Pos     (2U)
+#define SWPMI_ISR_RXBERF_Msk     (0x1UL << SWPMI_ISR_RXBERF_Pos)               /*!< 0x00000004 */
+#define SWPMI_ISR_RXBERF         SWPMI_ISR_RXBERF_Msk                          /*!<Receive CRC error flag          */
+#define SWPMI_ISR_RXOVRF_Pos     (3U)
+#define SWPMI_ISR_RXOVRF_Msk     (0x1UL << SWPMI_ISR_RXOVRF_Pos)               /*!< 0x00000008 */
+#define SWPMI_ISR_RXOVRF         SWPMI_ISR_RXOVRF_Msk                          /*!<Receive overrun error flag      */
+#define SWPMI_ISR_TXUNRF_Pos     (4U)
+#define SWPMI_ISR_TXUNRF_Msk     (0x1UL << SWPMI_ISR_TXUNRF_Pos)               /*!< 0x00000010 */
+#define SWPMI_ISR_TXUNRF         SWPMI_ISR_TXUNRF_Msk                          /*!<Transmit underrun error flag    */
+#define SWPMI_ISR_RXNE_Pos       (5U)
+#define SWPMI_ISR_RXNE_Msk       (0x1UL << SWPMI_ISR_RXNE_Pos)                 /*!< 0x00000020 */
+#define SWPMI_ISR_RXNE           SWPMI_ISR_RXNE_Msk                            /*!<Receive data register not empty */
+#define SWPMI_ISR_TXE_Pos        (6U)
+#define SWPMI_ISR_TXE_Msk        (0x1UL << SWPMI_ISR_TXE_Pos)                  /*!< 0x00000040 */
+#define SWPMI_ISR_TXE            SWPMI_ISR_TXE_Msk                             /*!<Transmit data register empty    */
+#define SWPMI_ISR_TCF_Pos        (7U)
+#define SWPMI_ISR_TCF_Msk        (0x1UL << SWPMI_ISR_TCF_Pos)                  /*!< 0x00000080 */
+#define SWPMI_ISR_TCF            SWPMI_ISR_TCF_Msk                             /*!<Transfer complete flag          */
+#define SWPMI_ISR_SRF_Pos        (8U)
+#define SWPMI_ISR_SRF_Msk        (0x1UL << SWPMI_ISR_SRF_Pos)                  /*!< 0x00000100 */
+#define SWPMI_ISR_SRF            SWPMI_ISR_SRF_Msk                             /*!<Slave resume flag               */
+#define SWPMI_ISR_SUSP_Pos       (9U)
+#define SWPMI_ISR_SUSP_Msk       (0x1UL << SWPMI_ISR_SUSP_Pos)                 /*!< 0x00000200 */
+#define SWPMI_ISR_SUSP           SWPMI_ISR_SUSP_Msk                            /*!<SUSPEND flag                    */
+#define SWPMI_ISR_DEACTF_Pos     (10U)
+#define SWPMI_ISR_DEACTF_Msk     (0x1UL << SWPMI_ISR_DEACTF_Pos)               /*!< 0x00000400 */
+#define SWPMI_ISR_DEACTF         SWPMI_ISR_DEACTF_Msk                          /*!<DEACTIVATED flag                */
+#define SWPMI_ISR_RDYF_Pos       (11U)
+#define SWPMI_ISR_RDYF_Msk       (0x1UL << SWPMI_ISR_RDYF_Pos)                 /*!< 0x00000800 */
+#define SWPMI_ISR_RDYF           SWPMI_ISR_RDYF_Msk                            /*!<Transceiver ready flag          */
+
+/*******************  Bit definition for SWPMI_ICR register  ********************/
+#define SWPMI_ICR_CRXBFF_Pos     (0U)
+#define SWPMI_ICR_CRXBFF_Msk     (0x1UL << SWPMI_ICR_CRXBFF_Pos)               /*!< 0x00000001 */
+#define SWPMI_ICR_CRXBFF         SWPMI_ICR_CRXBFF_Msk                          /*!<Clear receive buffer full flag       */
+#define SWPMI_ICR_CTXBEF_Pos     (1U)
+#define SWPMI_ICR_CTXBEF_Msk     (0x1UL << SWPMI_ICR_CTXBEF_Pos)               /*!< 0x00000002 */
+#define SWPMI_ICR_CTXBEF         SWPMI_ICR_CTXBEF_Msk                          /*!<Clear transmit buffer empty flag     */
+#define SWPMI_ICR_CRXBERF_Pos    (2U)
+#define SWPMI_ICR_CRXBERF_Msk    (0x1UL << SWPMI_ICR_CRXBERF_Pos)              /*!< 0x00000004 */
+#define SWPMI_ICR_CRXBERF        SWPMI_ICR_CRXBERF_Msk                         /*!<Clear receive CRC error flag         */
+#define SWPMI_ICR_CRXOVRF_Pos    (3U)
+#define SWPMI_ICR_CRXOVRF_Msk    (0x1UL << SWPMI_ICR_CRXOVRF_Pos)              /*!< 0x00000008 */
+#define SWPMI_ICR_CRXOVRF        SWPMI_ICR_CRXOVRF_Msk                         /*!<Clear receive overrun error flag     */
+#define SWPMI_ICR_CTXUNRF_Pos    (4U)
+#define SWPMI_ICR_CTXUNRF_Msk    (0x1UL << SWPMI_ICR_CTXUNRF_Pos)              /*!< 0x00000010 */
+#define SWPMI_ICR_CTXUNRF        SWPMI_ICR_CTXUNRF_Msk                         /*!<Clear transmit underrun error flag   */
+#define SWPMI_ICR_CTCF_Pos       (7U)
+#define SWPMI_ICR_CTCF_Msk       (0x1UL << SWPMI_ICR_CTCF_Pos)                 /*!< 0x00000080 */
+#define SWPMI_ICR_CTCF           SWPMI_ICR_CTCF_Msk                            /*!<Clear transfer complete flag         */
+#define SWPMI_ICR_CSRF_Pos       (8U)
+#define SWPMI_ICR_CSRF_Msk       (0x1UL << SWPMI_ICR_CSRF_Pos)                 /*!< 0x00000100 */
+#define SWPMI_ICR_CSRF           SWPMI_ICR_CSRF_Msk                            /*!<Clear slave resume flag              */
+#define SWPMI_ICR_CRDYF_Pos      (11U)
+#define SWPMI_ICR_CRDYF_Msk      (0x1UL << SWPMI_ICR_CRDYF_Pos)                /*!< 0x00000800 */
+#define SWPMI_ICR_CRDYF          SWPMI_ICR_CRDYF_Msk                           /*!<Clear transceiver ready flag         */
+
+/*******************  Bit definition for SWPMI_IER register  ********************/
+#define SWPMI_IER_RXBFIE_Pos     (0U)
+#define SWPMI_IER_RXBFIE_Msk     (0x1UL << SWPMI_IER_RXBFIE_Pos)               /*!< 0x00000001 */
+#define SWPMI_IER_RXBFIE         SWPMI_IER_RXBFIE_Msk                          /*!<Receive buffer full interrupt enable        */
+#define SWPMI_IER_TXBEIE_Pos     (1U)
+#define SWPMI_IER_TXBEIE_Msk     (0x1UL << SWPMI_IER_TXBEIE_Pos)               /*!< 0x00000002 */
+#define SWPMI_IER_TXBEIE         SWPMI_IER_TXBEIE_Msk                          /*!<Transmit buffer empty interrupt enable      */
+#define SWPMI_IER_RXBERIE_Pos    (2U)
+#define SWPMI_IER_RXBERIE_Msk    (0x1UL << SWPMI_IER_RXBERIE_Pos)              /*!< 0x00000004 */
+#define SWPMI_IER_RXBERIE        SWPMI_IER_RXBERIE_Msk                         /*!<Receive CRC error interrupt enable          */
+#define SWPMI_IER_RXOVRIE_Pos    (3U)
+#define SWPMI_IER_RXOVRIE_Msk    (0x1UL << SWPMI_IER_RXOVRIE_Pos)              /*!< 0x00000008 */
+#define SWPMI_IER_RXOVRIE        SWPMI_IER_RXOVRIE_Msk                         /*!<Receive overrun error interrupt enable      */
+#define SWPMI_IER_TXUNRIE_Pos    (4U)
+#define SWPMI_IER_TXUNRIE_Msk    (0x1UL << SWPMI_IER_TXUNRIE_Pos)              /*!< 0x00000010 */
+#define SWPMI_IER_TXUNRIE        SWPMI_IER_TXUNRIE_Msk                         /*!<Transmit underrun error interrupt enable    */
+#define SWPMI_IER_RIE_Pos        (5U)
+#define SWPMI_IER_RIE_Msk        (0x1UL << SWPMI_IER_RIE_Pos)                  /*!< 0x00000020 */
+#define SWPMI_IER_RIE            SWPMI_IER_RIE_Msk                             /*!<Receive interrupt enable                    */
+#define SWPMI_IER_TIE_Pos        (6U)
+#define SWPMI_IER_TIE_Msk        (0x1UL << SWPMI_IER_TIE_Pos)                  /*!< 0x00000040 */
+#define SWPMI_IER_TIE            SWPMI_IER_TIE_Msk                             /*!<Transmit interrupt enable                   */
+#define SWPMI_IER_TCIE_Pos       (7U)
+#define SWPMI_IER_TCIE_Msk       (0x1UL << SWPMI_IER_TCIE_Pos)                 /*!< 0x00000080 */
+#define SWPMI_IER_TCIE           SWPMI_IER_TCIE_Msk                            /*!<Transmit complete interrupt enable          */
+#define SWPMI_IER_SRIE_Pos       (8U)
+#define SWPMI_IER_SRIE_Msk       (0x1UL << SWPMI_IER_SRIE_Pos)                 /*!< 0x00000100 */
+#define SWPMI_IER_SRIE           SWPMI_IER_SRIE_Msk                            /*!<Slave resume interrupt enable               */
+#define SWPMI_IER_RDYIE_Pos      (11U)
+#define SWPMI_IER_RDYIE_Msk      (0x1UL << SWPMI_IER_RDYIE_Pos)                /*!< 0x00000800 */
+#define SWPMI_IER_RDYIE          SWPMI_IER_RDYIE_Msk                           /*!<Transceiver ready interrupt enable          */
+
+/*******************  Bit definition for SWPMI_RFL register  ********************/
+#define SWPMI_RFL_RFL_Pos        (0U)
+#define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */
+#define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */
+#define SWPMI_RFL_RFL_0_1        ((uint32_t)0x00000003)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
+
+/*******************  Bit definition for SWPMI_TDR register  ********************/
+#define SWPMI_TDR_TD_Pos         (0U)
+#define SWPMI_TDR_TD_Msk         (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos)            /*!< 0xFFFFFFFF */
+#define SWPMI_TDR_TD             SWPMI_TDR_TD_Msk                              /*!<Transmit Data Register         */
+
+/*******************  Bit definition for SWPMI_RDR register  ********************/
+#define SWPMI_RDR_RD_Pos         (0U)
+#define SWPMI_RDR_RD_Msk         (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos)            /*!< 0xFFFFFFFF */
+#define SWPMI_RDR_RD             SWPMI_RDR_RD_Msk                              /*!<Recive Data Register           */
+
+
+/*******************  Bit definition for SWPMI_OR register  ********************/
+#define SWPMI_OR_TBYP_Pos        (0U)
+#define SWPMI_OR_TBYP_Msk        (0x1UL << SWPMI_OR_TBYP_Pos)                  /*!< 0x00000001 */
+#define SWPMI_OR_TBYP            SWPMI_OR_TBYP_Msk                             /*!<SWP Transceiver Bypass */
+#define SWPMI_OR_CLASS_Pos       (1U)
+#define SWPMI_OR_CLASS_Msk       (0x1UL << SWPMI_OR_CLASS_Pos)                 /*!< 0x00000002 */
+#define SWPMI_OR_CLASS           SWPMI_OR_CLASS_Msk                            /*!<SWP CLASS selection */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Window WATCHDOG                                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define WWDG_CR_T_Pos           (0U)
+#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                      /*!< 0x0000007F */
+#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
+#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
+#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
+#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
+#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
+#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
+#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
+
+#define WWDG_CR_WDGA_Pos        (7U)
+#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                    /*!< 0x00000080 */
+#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define WWDG_CFR_W_Pos          (0U)
+#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                     /*!< 0x0000007F */
+#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
+#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
+#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
+#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
+#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
+#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
+#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
+
+#define WWDG_CFR_EWI_Pos        (9U)
+#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                    /*!< 0x00000200 */
+#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
+
+#define WWDG_CFR_WDGTB_Pos      (11U)
+#define WWDG_CFR_WDGTB_Msk      (0x7UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00003800 */
+#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[2:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000800 */
+#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00001000 */
+#define WWDG_CFR_WDGTB_2        (0x4UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00002000 */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define WWDG_SR_EWIF_Pos        (0U)
+#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                    /*!< 0x00000001 */
+#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                DBG                                         */
+/*                                                                            */
+/******************************************************************************/
+/*********************************  DEVICE ID  ********************************/
+#define STM32H7_DEV_ID           0x450UL
+
+/********************  Bit definition for DBGMCU_IDCODE register  *************/
+#define DBGMCU_IDCODE_DEV_ID_Pos          (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk          (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID              DBGMCU_IDCODE_DEV_ID_Msk
+#define DBGMCU_IDCODE_REV_ID_Pos          (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk          (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID              DBGMCU_IDCODE_REV_ID_Msk
+
+/********************  Bit definition for DBGMCU_CR register  *****************/
+#define DBGMCU_CR_DBG_SLEEPD1_Pos         (0U)
+#define DBGMCU_CR_DBG_SLEEPD1_Msk         (0x1UL << DBGMCU_CR_DBG_SLEEPD1_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEPD1             DBGMCU_CR_DBG_SLEEPD1_Msk
+#define DBGMCU_CR_DBG_STOPD1_Pos          (1U)
+#define DBGMCU_CR_DBG_STOPD1_Msk          (0x1UL << DBGMCU_CR_DBG_STOPD1_Pos)  /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOPD1              DBGMCU_CR_DBG_STOPD1_Msk
+#define DBGMCU_CR_DBG_STANDBYD1_Pos       (2U)
+#define DBGMCU_CR_DBG_STANDBYD1_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYD1_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBYD1           DBGMCU_CR_DBG_STANDBYD1_Msk
+#define DBGMCU_CR_DBG_STOPD3_Pos          (7U)
+#define DBGMCU_CR_DBG_STOPD3_Msk          (0x1UL << DBGMCU_CR_DBG_STOPD3_Pos)  /*!< 0x00000080 */
+#define DBGMCU_CR_DBG_STOPD3              DBGMCU_CR_DBG_STOPD3_Msk
+#define DBGMCU_CR_DBG_STANDBYD3_Pos       (8U)
+#define DBGMCU_CR_DBG_STANDBYD3_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYD3_Pos) /*!< 0x00000100 */
+#define DBGMCU_CR_DBG_STANDBYD3           DBGMCU_CR_DBG_STANDBYD3_Msk
+#define DBGMCU_CR_DBG_TRACECKEN_Pos       (20U)
+#define DBGMCU_CR_DBG_TRACECKEN_Msk       (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos) /*!< 0x00100000 */
+#define DBGMCU_CR_DBG_TRACECKEN           DBGMCU_CR_DBG_TRACECKEN_Msk
+#define DBGMCU_CR_DBG_CKD1EN_Pos          (21U)
+#define DBGMCU_CR_DBG_CKD1EN_Msk          (0x1UL << DBGMCU_CR_DBG_CKD1EN_Pos)  /*!< 0x00200000 */
+#define DBGMCU_CR_DBG_CKD1EN              DBGMCU_CR_DBG_CKD1EN_Msk
+#define DBGMCU_CR_DBG_CKD3EN_Pos          (22U)
+#define DBGMCU_CR_DBG_CKD3EN_Msk          (0x1UL << DBGMCU_CR_DBG_CKD3EN_Pos)  /*!< 0x00400000 */
+#define DBGMCU_CR_DBG_CKD3EN              DBGMCU_CR_DBG_CKD3EN_Msk
+#define DBGMCU_CR_DBG_TRGOEN_Pos          (28U)
+#define DBGMCU_CR_DBG_TRGOEN_Msk          (0x1UL << DBGMCU_CR_DBG_TRGOEN_Pos)  /*!< 0x10000000 */
+#define DBGMCU_CR_DBG_TRGOEN              DBGMCU_CR_DBG_TRGOEN_Msk
+
+/********************  Bit definition for APB3FZ1 register  ************/
+#define DBGMCU_APB3FZ1_DBG_WWDG1_Pos      (6U)
+#define DBGMCU_APB3FZ1_DBG_WWDG1_Msk      (0x1UL << DBGMCU_APB3FZ1_DBG_WWDG1_Pos) /*!< 0x00000040 */
+#define DBGMCU_APB3FZ1_DBG_WWDG1          DBGMCU_APB3FZ1_DBG_WWDG1_Msk
+/********************  Bit definition for APB1LFZ1 register  ************/
+#define DBGMCU_APB1LFZ1_DBG_TIM2_Pos      (0U)
+#define DBGMCU_APB1LFZ1_DBG_TIM2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1LFZ1_DBG_TIM2          DBGMCU_APB1LFZ1_DBG_TIM2_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM3_Pos      (1U)
+#define DBGMCU_APB1LFZ1_DBG_TIM3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB1LFZ1_DBG_TIM3          DBGMCU_APB1LFZ1_DBG_TIM3_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM4_Pos      (2U)
+#define DBGMCU_APB1LFZ1_DBG_TIM4_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB1LFZ1_DBG_TIM4          DBGMCU_APB1LFZ1_DBG_TIM4_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM5_Pos      (3U)
+#define DBGMCU_APB1LFZ1_DBG_TIM5_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_Pos) /*!< 0x00000008 */
+#define DBGMCU_APB1LFZ1_DBG_TIM5          DBGMCU_APB1LFZ1_DBG_TIM5_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM6_Pos      (4U)
+#define DBGMCU_APB1LFZ1_DBG_TIM6_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB1LFZ1_DBG_TIM6          DBGMCU_APB1LFZ1_DBG_TIM6_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM7_Pos      (5U)
+#define DBGMCU_APB1LFZ1_DBG_TIM7_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB1LFZ1_DBG_TIM7          DBGMCU_APB1LFZ1_DBG_TIM7_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM12_Pos     (6U)
+#define DBGMCU_APB1LFZ1_DBG_TIM12_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_Pos) /*!< 0x00000040 */
+#define DBGMCU_APB1LFZ1_DBG_TIM12         DBGMCU_APB1LFZ1_DBG_TIM12_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM13_Pos     (7U)
+#define DBGMCU_APB1LFZ1_DBG_TIM13_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_Pos) /*!< 0x00000080 */
+#define DBGMCU_APB1LFZ1_DBG_TIM13         DBGMCU_APB1LFZ1_DBG_TIM13_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM14_Pos     (8U)
+#define DBGMCU_APB1LFZ1_DBG_TIM14_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_Pos) /*!< 0x00000100 */
+#define DBGMCU_APB1LFZ1_DBG_TIM14         DBGMCU_APB1LFZ1_DBG_TIM14_Msk
+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos    (9U)
+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos) /*!< 0x00000200 */
+#define DBGMCU_APB1LFZ1_DBG_LPTIM1        DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk
+#define DBGMCU_APB1LFZ1_DBG_I2C1_Pos      (21U)
+#define DBGMCU_APB1LFZ1_DBG_I2C1_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1LFZ1_DBG_I2C1          DBGMCU_APB1LFZ1_DBG_I2C1_Msk
+#define DBGMCU_APB1LFZ1_DBG_I2C2_Pos      (22U)
+#define DBGMCU_APB1LFZ1_DBG_I2C2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1LFZ1_DBG_I2C2          DBGMCU_APB1LFZ1_DBG_I2C2_Msk
+#define DBGMCU_APB1LFZ1_DBG_I2C3_Pos      (23U)
+#define DBGMCU_APB1LFZ1_DBG_I2C3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_Pos) /*!< 0x00800000 */
+#define DBGMCU_APB1LFZ1_DBG_I2C3          DBGMCU_APB1LFZ1_DBG_I2C3_Msk
+
+/********************  Bit definition for APB1HFZ1 register  ************/
+#define DBGMCU_APB1HFZ1_DBG_FDCAN_Pos     (8U)
+#define DBGMCU_APB1HFZ1_DBG_FDCAN_Msk     (0x1UL << DBGMCU_APB1HFZ1_DBG_FDCAN_Pos) /*!< 0x00000100 */
+#define DBGMCU_APB1HFZ1_DBG_FDCAN         DBGMCU_APB1HFZ1_DBG_FDCAN_Msk
+/********************  Bit definition for APB2FZ1 register  ************/
+#define DBGMCU_APB2FZ1_DBG_TIM1_Pos       (0U)
+#define DBGMCU_APB2FZ1_DBG_TIM1_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB2FZ1_DBG_TIM1           DBGMCU_APB2FZ1_DBG_TIM1_Msk
+#define DBGMCU_APB2FZ1_DBG_TIM8_Pos       (1U)
+#define DBGMCU_APB2FZ1_DBG_TIM8_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB2FZ1_DBG_TIM8           DBGMCU_APB2FZ1_DBG_TIM8_Msk
+#define DBGMCU_APB2FZ1_DBG_TIM15_Pos      (16U)
+#define DBGMCU_APB2FZ1_DBG_TIM15_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_Pos) /*!< 0x00010000 */
+#define DBGMCU_APB2FZ1_DBG_TIM15          DBGMCU_APB2FZ1_DBG_TIM15_Msk
+#define DBGMCU_APB2FZ1_DBG_TIM16_Pos      (17U)
+#define DBGMCU_APB2FZ1_DBG_TIM16_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_Pos) /*!< 0x00020000 */
+#define DBGMCU_APB2FZ1_DBG_TIM16          DBGMCU_APB2FZ1_DBG_TIM16_Msk
+#define DBGMCU_APB2FZ1_DBG_TIM17_Pos      (18U)
+#define DBGMCU_APB2FZ1_DBG_TIM17_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_Pos) /*!< 0x00040000 */
+#define DBGMCU_APB2FZ1_DBG_TIM17          DBGMCU_APB2FZ1_DBG_TIM17_Msk
+#define DBGMCU_APB2FZ1_DBG_HRTIM_Pos      (29U)
+#define DBGMCU_APB2FZ1_DBG_HRTIM_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_HRTIM_Pos) /*!< 0x20000000 */
+#define DBGMCU_APB2FZ1_DBG_HRTIM          DBGMCU_APB2FZ1_DBG_HRTIM_Msk
+
+/********************  Bit definition for APB4FZ1 register  ************/
+#define DBGMCU_APB4FZ1_DBG_I2C4_Pos       (7U)
+#define DBGMCU_APB4FZ1_DBG_I2C4_Msk       (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_Pos) /*!< 0x00000080 */
+#define DBGMCU_APB4FZ1_DBG_I2C4           DBGMCU_APB4FZ1_DBG_I2C4_Msk
+#define DBGMCU_APB4FZ1_DBG_LPTIM2_Pos     (9U)
+#define DBGMCU_APB4FZ1_DBG_LPTIM2_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_Pos) /*!< 0x00000200 */
+#define DBGMCU_APB4FZ1_DBG_LPTIM2         DBGMCU_APB4FZ1_DBG_LPTIM2_Msk
+#define DBGMCU_APB4FZ1_DBG_LPTIM3_Pos     (10U)
+#define DBGMCU_APB4FZ1_DBG_LPTIM3_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB4FZ1_DBG_LPTIM3         DBGMCU_APB4FZ1_DBG_LPTIM3_Msk
+#define DBGMCU_APB4FZ1_DBG_LPTIM4_Pos     (11U)
+#define DBGMCU_APB4FZ1_DBG_LPTIM4_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM4_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB4FZ1_DBG_LPTIM4         DBGMCU_APB4FZ1_DBG_LPTIM4_Msk
+#define DBGMCU_APB4FZ1_DBG_LPTIM5_Pos     (12U)
+#define DBGMCU_APB4FZ1_DBG_LPTIM5_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM5_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB4FZ1_DBG_LPTIM5         DBGMCU_APB4FZ1_DBG_LPTIM5_Msk
+#define DBGMCU_APB4FZ1_DBG_RTC_Pos        (16U)
+#define DBGMCU_APB4FZ1_DBG_RTC_Msk        (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_Pos) /*!< 0x00010000 */
+#define DBGMCU_APB4FZ1_DBG_RTC            DBGMCU_APB4FZ1_DBG_RTC_Msk
+#define DBGMCU_APB4FZ1_DBG_IWDG1_Pos      (18U)
+#define DBGMCU_APB4FZ1_DBG_IWDG1_Msk      (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG1_Pos) /*!< 0x00040000 */
+#define DBGMCU_APB4FZ1_DBG_IWDG1          DBGMCU_APB4FZ1_DBG_IWDG1_Msk
+/******************************************************************************/
+/*                                                                            */
+/*                        High Resolution Timer (HRTIM)                       */
+/*                                                                            */
+/******************************************************************************/
+/******************** Master Timer control register ***************************/
+#define HRTIM_MCR_CK_PSC_Pos          (0U)
+#define HRTIM_MCR_CK_PSC_Msk          (0x7UL << HRTIM_MCR_CK_PSC_Pos)          /*!< 0x00000007 */
+#define HRTIM_MCR_CK_PSC              HRTIM_MCR_CK_PSC_Msk                     /*!< Prescaler mask */
+#define HRTIM_MCR_CK_PSC_0            (0x1UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000001 */
+#define HRTIM_MCR_CK_PSC_1            (0x2UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000002 */
+#define HRTIM_MCR_CK_PSC_2            (0x4UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000004 */
+
+#define HRTIM_MCR_CONT_Pos            (3U)
+#define HRTIM_MCR_CONT_Msk            (0x1UL << HRTIM_MCR_CONT_Pos)            /*!< 0x00000008 */
+#define HRTIM_MCR_CONT                HRTIM_MCR_CONT_Msk                       /*!< Continuous mode */
+#define HRTIM_MCR_RETRIG_Pos          (4U)
+#define HRTIM_MCR_RETRIG_Msk          (0x1UL << HRTIM_MCR_RETRIG_Pos)          /*!< 0x00000010 */
+#define HRTIM_MCR_RETRIG              HRTIM_MCR_RETRIG_Msk                     /*!< Rettrigreable mode */
+#define HRTIM_MCR_HALF_Pos            (5U)
+#define HRTIM_MCR_HALF_Msk            (0x1UL << HRTIM_MCR_HALF_Pos)            /*!< 0x00000020 */
+#define HRTIM_MCR_HALF                HRTIM_MCR_HALF_Msk                       /*!< Half mode */
+
+#define HRTIM_MCR_SYNC_IN_Pos         (8U)
+#define HRTIM_MCR_SYNC_IN_Msk         (0x3UL << HRTIM_MCR_SYNC_IN_Pos)         /*!< 0x00000300 */
+#define HRTIM_MCR_SYNC_IN             HRTIM_MCR_SYNC_IN_Msk                    /*!< Synchronization input master */
+#define HRTIM_MCR_SYNC_IN_0           (0x1UL << HRTIM_MCR_SYNC_IN_Pos)          /*!< 0x00000100 */
+#define HRTIM_MCR_SYNC_IN_1           (0x2UL << HRTIM_MCR_SYNC_IN_Pos)          /*!< 0x00000200 */
+#define HRTIM_MCR_SYNCRSTM_Pos        (10U)
+#define HRTIM_MCR_SYNCRSTM_Msk        (0x1UL << HRTIM_MCR_SYNCRSTM_Pos)        /*!< 0x00000400 */
+#define HRTIM_MCR_SYNCRSTM            HRTIM_MCR_SYNCRSTM_Msk                   /*!< Synchronization reset master */
+#define HRTIM_MCR_SYNCSTRTM_Pos       (11U)
+#define HRTIM_MCR_SYNCSTRTM_Msk       (0x1UL << HRTIM_MCR_SYNCSTRTM_Pos)       /*!< 0x00000800 */
+#define HRTIM_MCR_SYNCSTRTM           HRTIM_MCR_SYNCSTRTM_Msk                  /*!< Synchronization start master */
+#define HRTIM_MCR_SYNC_OUT_Pos        (12U)
+#define HRTIM_MCR_SYNC_OUT_Msk        (0x3UL << HRTIM_MCR_SYNC_OUT_Pos)        /*!< 0x00003000 */
+#define HRTIM_MCR_SYNC_OUT            HRTIM_MCR_SYNC_OUT_Msk                   /*!< Synchronization output master */
+#define HRTIM_MCR_SYNC_OUT_0          (0x1UL << HRTIM_MCR_SYNC_OUT_Pos)         /*!< 0x00001000 */
+#define HRTIM_MCR_SYNC_OUT_1          (0x2UL << HRTIM_MCR_SYNC_OUT_Pos)         /*!< 0x00002000 */
+#define HRTIM_MCR_SYNC_SRC_Pos        (14U)
+#define HRTIM_MCR_SYNC_SRC_Msk        (0x3UL << HRTIM_MCR_SYNC_SRC_Pos)        /*!< 0x0000C000 */
+#define HRTIM_MCR_SYNC_SRC            HRTIM_MCR_SYNC_SRC_Msk                   /*!< Synchronization source */
+#define HRTIM_MCR_SYNC_SRC_0          (0x1UL << HRTIM_MCR_SYNC_SRC_Pos)         /*!< 0x00004000 */
+#define HRTIM_MCR_SYNC_SRC_1          (0x2UL << HRTIM_MCR_SYNC_SRC_Pos)         /*!< 0x00008000 */
+
+#define HRTIM_MCR_MCEN_Pos            (16U)
+#define HRTIM_MCR_MCEN_Msk            (0x1UL << HRTIM_MCR_MCEN_Pos)            /*!< 0x00010000 */
+#define HRTIM_MCR_MCEN                HRTIM_MCR_MCEN_Msk                       /*!< Master counter enable */
+#define HRTIM_MCR_TACEN_Pos           (17U)
+#define HRTIM_MCR_TACEN_Msk           (0x1UL << HRTIM_MCR_TACEN_Pos)           /*!< 0x00020000 */
+#define HRTIM_MCR_TACEN               HRTIM_MCR_TACEN_Msk                      /*!< Timer A counter enable */
+#define HRTIM_MCR_TBCEN_Pos           (18U)
+#define HRTIM_MCR_TBCEN_Msk           (0x1UL << HRTIM_MCR_TBCEN_Pos)           /*!< 0x00040000 */
+#define HRTIM_MCR_TBCEN               HRTIM_MCR_TBCEN_Msk                      /*!< Timer B counter enable */
+#define HRTIM_MCR_TCCEN_Pos           (19U)
+#define HRTIM_MCR_TCCEN_Msk           (0x1UL << HRTIM_MCR_TCCEN_Pos)           /*!< 0x00080000 */
+#define HRTIM_MCR_TCCEN               HRTIM_MCR_TCCEN_Msk                      /*!< Timer C counter enable */
+#define HRTIM_MCR_TDCEN_Pos           (20U)
+#define HRTIM_MCR_TDCEN_Msk           (0x1UL << HRTIM_MCR_TDCEN_Pos)           /*!< 0x00100000 */
+#define HRTIM_MCR_TDCEN               HRTIM_MCR_TDCEN_Msk                      /*!< Timer D counter enable */
+#define HRTIM_MCR_TECEN_Pos           (21U)
+#define HRTIM_MCR_TECEN_Msk           (0x1UL << HRTIM_MCR_TECEN_Pos)           /*!< 0x00200000 */
+#define HRTIM_MCR_TECEN               HRTIM_MCR_TECEN_Msk                      /*!< Timer E counter enable */
+
+#define HRTIM_MCR_DACSYNC_Pos         (25U)
+#define HRTIM_MCR_DACSYNC_Msk         (0x3UL << HRTIM_MCR_DACSYNC_Pos)         /*!< 0x06000000 */
+#define HRTIM_MCR_DACSYNC             HRTIM_MCR_DACSYNC_Msk                    /*!< DAC sychronization mask */
+#define HRTIM_MCR_DACSYNC_0           (0x1UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x02000000 */
+#define HRTIM_MCR_DACSYNC_1           (0x2UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x04000000 */
+
+#define HRTIM_MCR_PREEN_Pos           (27U)
+#define HRTIM_MCR_PREEN_Msk           (0x1UL << HRTIM_MCR_PREEN_Pos)           /*!< 0x08000000 */
+#define HRTIM_MCR_PREEN               HRTIM_MCR_PREEN_Msk                      /*!< Master preload enable */
+#define HRTIM_MCR_MREPU_Pos           (29U)
+#define HRTIM_MCR_MREPU_Msk           (0x1UL << HRTIM_MCR_MREPU_Pos)           /*!< 0x20000000 */
+#define HRTIM_MCR_MREPU               HRTIM_MCR_MREPU_Msk                      /*!< Master repetition update */
+
+#define HRTIM_MCR_BRSTDMA_Pos         (30U)
+#define HRTIM_MCR_BRSTDMA_Msk         (0x3UL << HRTIM_MCR_BRSTDMA_Pos)         /*!< 0xC0000000 */
+#define HRTIM_MCR_BRSTDMA             HRTIM_MCR_BRSTDMA_Msk                    /*!< Burst DMA update */
+#define HRTIM_MCR_BRSTDMA_0           (0x1UL << HRTIM_MCR_BRSTDMA_Pos)          /*!< 0x40000000 */
+#define HRTIM_MCR_BRSTDMA_1           (0x2UL << HRTIM_MCR_BRSTDMA_Pos)          /*!< 0x80000000 */
+
+/******************** Master Timer Interrupt status register ******************/
+#define HRTIM_MISR_MCMP1_Pos          (0U)
+#define HRTIM_MISR_MCMP1_Msk          (0x1UL << HRTIM_MISR_MCMP1_Pos)          /*!< 0x00000001 */
+#define HRTIM_MISR_MCMP1              HRTIM_MISR_MCMP1_Msk                     /*!< Master compare 1 interrupt flag */
+#define HRTIM_MISR_MCMP2_Pos          (1U)
+#define HRTIM_MISR_MCMP2_Msk          (0x1UL << HRTIM_MISR_MCMP2_Pos)          /*!< 0x00000002 */
+#define HRTIM_MISR_MCMP2              HRTIM_MISR_MCMP2_Msk                     /*!< Master compare 2 interrupt flag */
+#define HRTIM_MISR_MCMP3_Pos          (2U)
+#define HRTIM_MISR_MCMP3_Msk          (0x1UL << HRTIM_MISR_MCMP3_Pos)          /*!< 0x00000004 */
+#define HRTIM_MISR_MCMP3              HRTIM_MISR_MCMP3_Msk                     /*!< Master compare 3 interrupt flag */
+#define HRTIM_MISR_MCMP4_Pos          (3U)
+#define HRTIM_MISR_MCMP4_Msk          (0x1UL << HRTIM_MISR_MCMP4_Pos)          /*!< 0x00000008 */
+#define HRTIM_MISR_MCMP4              HRTIM_MISR_MCMP4_Msk                     /*!< Master compare 4 interrupt flag */
+#define HRTIM_MISR_MREP_Pos           (4U)
+#define HRTIM_MISR_MREP_Msk           (0x1UL << HRTIM_MISR_MREP_Pos)           /*!< 0x00000010 */
+#define HRTIM_MISR_MREP               HRTIM_MISR_MREP_Msk                      /*!< Master Repetition interrupt flag */
+#define HRTIM_MISR_SYNC_Pos           (5U)
+#define HRTIM_MISR_SYNC_Msk           (0x1UL << HRTIM_MISR_SYNC_Pos)           /*!< 0x00000020 */
+#define HRTIM_MISR_SYNC               HRTIM_MISR_SYNC_Msk                      /*!< Synchronization input interrupt flag */
+#define HRTIM_MISR_MUPD_Pos           (6U)
+#define HRTIM_MISR_MUPD_Msk           (0x1UL << HRTIM_MISR_MUPD_Pos)           /*!< 0x00000040 */
+#define HRTIM_MISR_MUPD               HRTIM_MISR_MUPD_Msk                      /*!< Master update interrupt flag */
+
+/******************** Master Timer Interrupt clear register *******************/
+#define HRTIM_MICR_MCMP1_Pos          (0U)
+#define HRTIM_MICR_MCMP1_Msk          (0x1UL << HRTIM_MICR_MCMP1_Pos)          /*!< 0x00000001 */
+#define HRTIM_MICR_MCMP1              HRTIM_MICR_MCMP1_Msk                     /*!< Master compare 1 interrupt flag clear */
+#define HRTIM_MICR_MCMP2_Pos          (1U)
+#define HRTIM_MICR_MCMP2_Msk          (0x1UL << HRTIM_MICR_MCMP2_Pos)          /*!< 0x00000002 */
+#define HRTIM_MICR_MCMP2              HRTIM_MICR_MCMP2_Msk                     /*!< Master compare 2 interrupt flag clear */
+#define HRTIM_MICR_MCMP3_Pos          (2U)
+#define HRTIM_MICR_MCMP3_Msk          (0x1UL << HRTIM_MICR_MCMP3_Pos)          /*!< 0x00000004 */
+#define HRTIM_MICR_MCMP3              HRTIM_MICR_MCMP3_Msk                     /*!< Master compare 3 interrupt flag clear */
+#define HRTIM_MICR_MCMP4_Pos          (3U)
+#define HRTIM_MICR_MCMP4_Msk          (0x1UL << HRTIM_MICR_MCMP4_Pos)          /*!< 0x00000008 */
+#define HRTIM_MICR_MCMP4              HRTIM_MICR_MCMP4_Msk                     /*!< Master compare 4 interrupt flag clear */
+#define HRTIM_MICR_MREP_Pos           (4U)
+#define HRTIM_MICR_MREP_Msk           (0x1UL << HRTIM_MICR_MREP_Pos)           /*!< 0x00000010 */
+#define HRTIM_MICR_MREP               HRTIM_MICR_MREP_Msk                      /*!< Master Repetition interrupt flag clear */
+#define HRTIM_MICR_SYNC_Pos           (5U)
+#define HRTIM_MICR_SYNC_Msk           (0x1UL << HRTIM_MICR_SYNC_Pos)           /*!< 0x00000020 */
+#define HRTIM_MICR_SYNC               HRTIM_MICR_SYNC_Msk                      /*!< Synchronization input interrupt flag clear */
+#define HRTIM_MICR_MUPD_Pos           (6U)
+#define HRTIM_MICR_MUPD_Msk           (0x1UL << HRTIM_MICR_MUPD_Pos)           /*!< 0x00000040 */
+#define HRTIM_MICR_MUPD               HRTIM_MICR_MUPD_Msk                      /*!< Master update interrupt flag clear */
+
+/******************** Master Timer DMA/Interrupt enable register **************/
+#define HRTIM_MDIER_MCMP1IE_Pos       (0U)
+#define HRTIM_MDIER_MCMP1IE_Msk       (0x1UL << HRTIM_MDIER_MCMP1IE_Pos)       /*!< 0x00000001 */
+#define HRTIM_MDIER_MCMP1IE           HRTIM_MDIER_MCMP1IE_Msk                  /*!< Master compare 1 interrupt enable */
+#define HRTIM_MDIER_MCMP2IE_Pos       (1U)
+#define HRTIM_MDIER_MCMP2IE_Msk       (0x1UL << HRTIM_MDIER_MCMP2IE_Pos)       /*!< 0x00000002 */
+#define HRTIM_MDIER_MCMP2IE           HRTIM_MDIER_MCMP2IE_Msk                  /*!< Master compare 2 interrupt enable */
+#define HRTIM_MDIER_MCMP3IE_Pos       (2U)
+#define HRTIM_MDIER_MCMP3IE_Msk       (0x1UL << HRTIM_MDIER_MCMP3IE_Pos)       /*!< 0x00000004 */
+#define HRTIM_MDIER_MCMP3IE           HRTIM_MDIER_MCMP3IE_Msk                  /*!< Master compare 3 interrupt enable */
+#define HRTIM_MDIER_MCMP4IE_Pos       (3U)
+#define HRTIM_MDIER_MCMP4IE_Msk       (0x1UL << HRTIM_MDIER_MCMP4IE_Pos)       /*!< 0x00000008 */
+#define HRTIM_MDIER_MCMP4IE           HRTIM_MDIER_MCMP4IE_Msk                  /*!< Master compare 4 interrupt enable */
+#define HRTIM_MDIER_MREPIE_Pos        (4U)
+#define HRTIM_MDIER_MREPIE_Msk        (0x1UL << HRTIM_MDIER_MREPIE_Pos)        /*!< 0x00000010 */
+#define HRTIM_MDIER_MREPIE            HRTIM_MDIER_MREPIE_Msk                   /*!< Master Repetition interrupt enable */
+#define HRTIM_MDIER_SYNCIE_Pos        (5U)
+#define HRTIM_MDIER_SYNCIE_Msk        (0x1UL << HRTIM_MDIER_SYNCIE_Pos)        /*!< 0x00000020 */
+#define HRTIM_MDIER_SYNCIE            HRTIM_MDIER_SYNCIE_Msk                   /*!< Synchronization input interrupt enable */
+#define HRTIM_MDIER_MUPDIE_Pos        (6U)
+#define HRTIM_MDIER_MUPDIE_Msk        (0x1UL << HRTIM_MDIER_MUPDIE_Pos)        /*!< 0x00000040 */
+#define HRTIM_MDIER_MUPDIE            HRTIM_MDIER_MUPDIE_Msk                   /*!< Master update interrupt enable */
+
+#define HRTIM_MDIER_MCMP1DE_Pos       (16U)
+#define HRTIM_MDIER_MCMP1DE_Msk       (0x1UL << HRTIM_MDIER_MCMP1DE_Pos)       /*!< 0x00010000 */
+#define HRTIM_MDIER_MCMP1DE           HRTIM_MDIER_MCMP1DE_Msk                  /*!< Master compare 1 DMA enable */
+#define HRTIM_MDIER_MCMP2DE_Pos       (17U)
+#define HRTIM_MDIER_MCMP2DE_Msk       (0x1UL << HRTIM_MDIER_MCMP2DE_Pos)       /*!< 0x00020000 */
+#define HRTIM_MDIER_MCMP2DE           HRTIM_MDIER_MCMP2DE_Msk                  /*!< Master compare 2 DMA enable */
+#define HRTIM_MDIER_MCMP3DE_Pos       (18U)
+#define HRTIM_MDIER_MCMP3DE_Msk       (0x1UL << HRTIM_MDIER_MCMP3DE_Pos)       /*!< 0x00040000 */
+#define HRTIM_MDIER_MCMP3DE           HRTIM_MDIER_MCMP3DE_Msk                  /*!< Master compare 3 DMA enable */
+#define HRTIM_MDIER_MCMP4DE_Pos       (19U)
+#define HRTIM_MDIER_MCMP4DE_Msk       (0x1UL << HRTIM_MDIER_MCMP4DE_Pos)       /*!< 0x00080000 */
+#define HRTIM_MDIER_MCMP4DE           HRTIM_MDIER_MCMP4DE_Msk                  /*!< Master compare 4 DMA enable */
+#define HRTIM_MDIER_MREPDE_Pos        (20U)
+#define HRTIM_MDIER_MREPDE_Msk        (0x1UL << HRTIM_MDIER_MREPDE_Pos)        /*!< 0x00100000 */
+#define HRTIM_MDIER_MREPDE            HRTIM_MDIER_MREPDE_Msk                   /*!< Master Repetition DMA enable */
+#define HRTIM_MDIER_SYNCDE_Pos        (21U)
+#define HRTIM_MDIER_SYNCDE_Msk        (0x1UL << HRTIM_MDIER_SYNCDE_Pos)        /*!< 0x00200000 */
+#define HRTIM_MDIER_SYNCDE            HRTIM_MDIER_SYNCDE_Msk                   /*!< Synchronization input DMA enable */
+#define HRTIM_MDIER_MUPDDE_Pos        (22U)
+#define HRTIM_MDIER_MUPDDE_Msk        (0x1UL << HRTIM_MDIER_MUPDDE_Pos)        /*!< 0x00400000 */
+#define HRTIM_MDIER_MUPDDE            HRTIM_MDIER_MUPDDE_Msk                   /*!< Master update DMA enable */
+
+/*******************  Bit definition for HRTIM_MCNTR register  ****************/
+#define HRTIM_MCNTR_MCNTR_Pos         (0U)
+#define HRTIM_MCNTR_MCNTR_Msk         (0xFFFFUL << HRTIM_MCNTR_MCNTR_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_MCNTR_MCNTR             HRTIM_MCNTR_MCNTR_Msk                    /*!<Counter Value */
+
+/*******************  Bit definition for HRTIM_MPER register  *****************/
+#define HRTIM_MPER_MPER_Pos           (0U)
+#define HRTIM_MPER_MPER_Msk           (0xFFFFUL << HRTIM_MPER_MPER_Pos)        /*!< 0x0000FFFF */
+#define HRTIM_MPER_MPER               HRTIM_MPER_MPER_Msk                      /*!< Period Value */
+
+/*******************  Bit definition for HRTIM_MREP register  *****************/
+#define HRTIM_MREP_MREP_Pos           (0U)
+#define HRTIM_MREP_MREP_Msk           (0xFFUL << HRTIM_MREP_MREP_Pos)          /*!< 0x000000FF */
+#define HRTIM_MREP_MREP               HRTIM_MREP_MREP_Msk                      /*!<Repetition Value */
+
+/*******************  Bit definition for HRTIM_MCMP1R register  *****************/
+#define HRTIM_MCMP1R_MCMP1R_Pos       (0U)
+#define HRTIM_MCMP1R_MCMP1R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP1R_Pos)    /*!< 0x0000FFFF */
+#define HRTIM_MCMP1R_MCMP1R           HRTIM_MCMP1R_MCMP1R_Msk                  /*!<Compare Value */
+
+/*******************  Bit definition for HRTIM_MCMP2R register  *****************/
+#define HRTIM_MCMP1R_MCMP2R_Pos       (0U)
+#define HRTIM_MCMP1R_MCMP2R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP2R_Pos)    /*!< 0x0000FFFF */
+#define HRTIM_MCMP1R_MCMP2R           HRTIM_MCMP1R_MCMP2R_Msk                  /*!<Compare Value */
+
+/*******************  Bit definition for HRTIM_MCMP3R register  *****************/
+#define HRTIM_MCMP1R_MCMP3R_Pos       (0U)
+#define HRTIM_MCMP1R_MCMP3R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP3R_Pos)    /*!< 0x0000FFFF */
+#define HRTIM_MCMP1R_MCMP3R           HRTIM_MCMP1R_MCMP3R_Msk                  /*!<Compare Value */
+
+/*******************  Bit definition for HRTIM_MCMP4R register  *****************/
+#define HRTIM_MCMP1R_MCMP4R_Pos       (0U)
+#define HRTIM_MCMP1R_MCMP4R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP4R_Pos)    /*!< 0x0000FFFF */
+#define HRTIM_MCMP1R_MCMP4R           HRTIM_MCMP1R_MCMP4R_Msk                  /*!<Compare Value */
+
+/******************** Slave control register **********************************/
+#define HRTIM_TIMCR_CK_PSC_Pos        (0U)
+#define HRTIM_TIMCR_CK_PSC_Msk        (0x7UL << HRTIM_TIMCR_CK_PSC_Pos)        /*!< 0x00000007 */
+#define HRTIM_TIMCR_CK_PSC            HRTIM_TIMCR_CK_PSC_Msk                   /*!< Slave prescaler mask*/
+#define HRTIM_TIMCR_CK_PSC_0          (0x1UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000001 */
+#define HRTIM_TIMCR_CK_PSC_1          (0x2UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000002 */
+#define HRTIM_TIMCR_CK_PSC_2          (0x4UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000004 */
+
+#define HRTIM_TIMCR_CONT_Pos          (3U)
+#define HRTIM_TIMCR_CONT_Msk          (0x1UL << HRTIM_TIMCR_CONT_Pos)          /*!< 0x00000008 */
+#define HRTIM_TIMCR_CONT              HRTIM_TIMCR_CONT_Msk                     /*!< Slave continuous mode */
+#define HRTIM_TIMCR_RETRIG_Pos        (4U)
+#define HRTIM_TIMCR_RETRIG_Msk        (0x1UL << HRTIM_TIMCR_RETRIG_Pos)        /*!< 0x00000010 */
+#define HRTIM_TIMCR_RETRIG            HRTIM_TIMCR_RETRIG_Msk                   /*!< Slave Retrigreable mode */
+#define HRTIM_TIMCR_HALF_Pos          (5U)
+#define HRTIM_TIMCR_HALF_Msk          (0x1UL << HRTIM_TIMCR_HALF_Pos)          /*!< 0x00000020 */
+#define HRTIM_TIMCR_HALF              HRTIM_TIMCR_HALF_Msk                     /*!< Slave Half mode */
+#define HRTIM_TIMCR_PSHPLL_Pos        (6U)
+#define HRTIM_TIMCR_PSHPLL_Msk        (0x1UL << HRTIM_TIMCR_PSHPLL_Pos)        /*!< 0x00000040 */
+#define HRTIM_TIMCR_PSHPLL            HRTIM_TIMCR_PSHPLL_Msk                   /*!< Slave push-pull mode */
+
+#define HRTIM_TIMCR_SYNCRST_Pos       (10U)
+#define HRTIM_TIMCR_SYNCRST_Msk       (0x1UL << HRTIM_TIMCR_SYNCRST_Pos)       /*!< 0x00000400 */
+#define HRTIM_TIMCR_SYNCRST           HRTIM_TIMCR_SYNCRST_Msk                  /*!< Slave synchronization resets */
+#define HRTIM_TIMCR_SYNCSTRT_Pos      (11U)
+#define HRTIM_TIMCR_SYNCSTRT_Msk      (0x1UL << HRTIM_TIMCR_SYNCSTRT_Pos)      /*!< 0x00000800 */
+#define HRTIM_TIMCR_SYNCSTRT          HRTIM_TIMCR_SYNCSTRT_Msk                 /*!< Slave synchronization starts */
+
+#define HRTIM_TIMCR_DELCMP2_Pos       (12U)
+#define HRTIM_TIMCR_DELCMP2_Msk       (0x3UL << HRTIM_TIMCR_DELCMP2_Pos)       /*!< 0x00003000 */
+#define HRTIM_TIMCR_DELCMP2           HRTIM_TIMCR_DELCMP2_Msk                  /*!< Slave delayed compartor 2 mode mask */
+#define HRTIM_TIMCR_DELCMP2_0         (0x1UL << HRTIM_TIMCR_DELCMP2_Pos)        /*!< 0x00001000 */
+#define HRTIM_TIMCR_DELCMP2_1         (0x2UL << HRTIM_TIMCR_DELCMP2_Pos)        /*!< 0x00002000 */
+#define HRTIM_TIMCR_DELCMP4_Pos       (14U)
+#define HRTIM_TIMCR_DELCMP4_Msk       (0x3UL << HRTIM_TIMCR_DELCMP4_Pos)       /*!< 0x0000C000 */
+#define HRTIM_TIMCR_DELCMP4           HRTIM_TIMCR_DELCMP4_Msk                  /*!< Slave delayed compartor 4 mode mask */
+#define HRTIM_TIMCR_DELCMP4_0         (0x1UL << HRTIM_TIMCR_DELCMP4_Pos)        /*!< 0x00004000 */
+#define HRTIM_TIMCR_DELCMP4_1         (0x2UL << HRTIM_TIMCR_DELCMP4_Pos)        /*!< 0x00008000 */
+
+#define HRTIM_TIMCR_TREPU_Pos         (17U)
+#define HRTIM_TIMCR_TREPU_Msk         (0x1UL << HRTIM_TIMCR_TREPU_Pos)         /*!< 0x00020000 */
+#define HRTIM_TIMCR_TREPU             HRTIM_TIMCR_TREPU_Msk                    /*!< Slave repetition update */
+#define HRTIM_TIMCR_TRSTU_Pos         (18U)
+#define HRTIM_TIMCR_TRSTU_Msk         (0x1UL << HRTIM_TIMCR_TRSTU_Pos)         /*!< 0x00040000 */
+#define HRTIM_TIMCR_TRSTU             HRTIM_TIMCR_TRSTU_Msk                    /*!< Slave reset update */
+#define HRTIM_TIMCR_TAU_Pos           (19U)
+#define HRTIM_TIMCR_TAU_Msk           (0x1UL << HRTIM_TIMCR_TAU_Pos)           /*!< 0x00080000 */
+#define HRTIM_TIMCR_TAU               HRTIM_TIMCR_TAU_Msk                      /*!< Slave Timer A update reserved for TIM A */
+#define HRTIM_TIMCR_TBU_Pos           (20U)
+#define HRTIM_TIMCR_TBU_Msk           (0x1UL << HRTIM_TIMCR_TBU_Pos)           /*!< 0x00100000 */
+#define HRTIM_TIMCR_TBU               HRTIM_TIMCR_TBU_Msk                      /*!< Slave Timer B update reserved for TIM B */
+#define HRTIM_TIMCR_TCU_Pos           (21U)
+#define HRTIM_TIMCR_TCU_Msk           (0x1UL << HRTIM_TIMCR_TCU_Pos)           /*!< 0x00200000 */
+#define HRTIM_TIMCR_TCU               HRTIM_TIMCR_TCU_Msk                      /*!< Slave Timer C update reserved for TIM C */
+#define HRTIM_TIMCR_TDU_Pos           (22U)
+#define HRTIM_TIMCR_TDU_Msk           (0x1UL << HRTIM_TIMCR_TDU_Pos)           /*!< 0x00400000 */
+#define HRTIM_TIMCR_TDU               HRTIM_TIMCR_TDU_Msk                      /*!< Slave Timer D update reserved for TIM D */
+#define HRTIM_TIMCR_TEU_Pos           (23U)
+#define HRTIM_TIMCR_TEU_Msk           (0x1UL << HRTIM_TIMCR_TEU_Pos)           /*!< 0x00800000 */
+#define HRTIM_TIMCR_TEU               HRTIM_TIMCR_TEU_Msk                      /*!< Slave Timer E update reserved for TIM E */
+#define HRTIM_TIMCR_MSTU_Pos          (24U)
+#define HRTIM_TIMCR_MSTU_Msk          (0x1UL << HRTIM_TIMCR_MSTU_Pos)          /*!< 0x01000000 */
+#define HRTIM_TIMCR_MSTU              HRTIM_TIMCR_MSTU_Msk                     /*!< Master Update */
+
+#define HRTIM_TIMCR_DACSYNC_Pos       (25U)
+#define HRTIM_TIMCR_DACSYNC_Msk       (0x3UL << HRTIM_TIMCR_DACSYNC_Pos)       /*!< 0x06000000 */
+#define HRTIM_TIMCR_DACSYNC           HRTIM_TIMCR_DACSYNC_Msk                  /*!< DAC sychronization mask */
+#define HRTIM_TIMCR_DACSYNC_0         (0x1UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x02000000 */
+#define HRTIM_TIMCR_DACSYNC_1         (0x2UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x04000000 */
+#define HRTIM_TIMCR_PREEN_Pos         (27U)
+#define HRTIM_TIMCR_PREEN_Msk         (0x1UL << HRTIM_TIMCR_PREEN_Pos)         /*!< 0x08000000 */
+#define HRTIM_TIMCR_PREEN             HRTIM_TIMCR_PREEN_Msk                    /*!< Slave preload enable */
+
+#define HRTIM_TIMCR_UPDGAT_Pos        (28U)
+#define HRTIM_TIMCR_UPDGAT_Msk        (0xFUL << HRTIM_TIMCR_UPDGAT_Pos)        /*!< 0xF0000000 */
+#define HRTIM_TIMCR_UPDGAT            HRTIM_TIMCR_UPDGAT_Msk                   /*!< Slave update gating mask */
+#define HRTIM_TIMCR_UPDGAT_0          (0x1UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x10000000 */
+#define HRTIM_TIMCR_UPDGAT_1          (0x2UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x20000000 */
+#define HRTIM_TIMCR_UPDGAT_2          (0x4UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x40000000 */
+#define HRTIM_TIMCR_UPDGAT_3          (0x8UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x80000000 */
+
+/******************** Slave Interrupt status register **************************/
+#define HRTIM_TIMISR_CMP1_Pos         (0U)
+#define HRTIM_TIMISR_CMP1_Msk         (0x1UL << HRTIM_TIMISR_CMP1_Pos)         /*!< 0x00000001 */
+#define HRTIM_TIMISR_CMP1             HRTIM_TIMISR_CMP1_Msk                    /*!< Slave compare 1 interrupt flag */
+#define HRTIM_TIMISR_CMP2_Pos         (1U)
+#define HRTIM_TIMISR_CMP2_Msk         (0x1UL << HRTIM_TIMISR_CMP2_Pos)         /*!< 0x00000002 */
+#define HRTIM_TIMISR_CMP2             HRTIM_TIMISR_CMP2_Msk                    /*!< Slave compare 2 interrupt flag */
+#define HRTIM_TIMISR_CMP3_Pos         (2U)
+#define HRTIM_TIMISR_CMP3_Msk         (0x1UL << HRTIM_TIMISR_CMP3_Pos)         /*!< 0x00000004 */
+#define HRTIM_TIMISR_CMP3             HRTIM_TIMISR_CMP3_Msk                    /*!< Slave compare 3 interrupt flag */
+#define HRTIM_TIMISR_CMP4_Pos         (3U)
+#define HRTIM_TIMISR_CMP4_Msk         (0x1UL << HRTIM_TIMISR_CMP4_Pos)         /*!< 0x00000008 */
+#define HRTIM_TIMISR_CMP4             HRTIM_TIMISR_CMP4_Msk                    /*!< Slave compare 4 interrupt flag */
+#define HRTIM_TIMISR_REP_Pos          (4U)
+#define HRTIM_TIMISR_REP_Msk          (0x1UL << HRTIM_TIMISR_REP_Pos)          /*!< 0x00000010 */
+#define HRTIM_TIMISR_REP              HRTIM_TIMISR_REP_Msk                     /*!< Slave repetition interrupt flag */
+#define HRTIM_TIMISR_UPD_Pos          (6U)
+#define HRTIM_TIMISR_UPD_Msk          (0x1UL << HRTIM_TIMISR_UPD_Pos)          /*!< 0x00000040 */
+#define HRTIM_TIMISR_UPD              HRTIM_TIMISR_UPD_Msk                     /*!< Slave update interrupt flag */
+#define HRTIM_TIMISR_CPT1_Pos         (7U)
+#define HRTIM_TIMISR_CPT1_Msk         (0x1UL << HRTIM_TIMISR_CPT1_Pos)         /*!< 0x00000080 */
+#define HRTIM_TIMISR_CPT1             HRTIM_TIMISR_CPT1_Msk                    /*!< Slave capture 1 interrupt flag */
+#define HRTIM_TIMISR_CPT2_Pos         (8U)
+#define HRTIM_TIMISR_CPT2_Msk         (0x1UL << HRTIM_TIMISR_CPT2_Pos)         /*!< 0x00000100 */
+#define HRTIM_TIMISR_CPT2             HRTIM_TIMISR_CPT2_Msk                    /*!< Slave capture 2 interrupt flag */
+#define HRTIM_TIMISR_SET1_Pos         (9U)
+#define HRTIM_TIMISR_SET1_Msk         (0x1UL << HRTIM_TIMISR_SET1_Pos)         /*!< 0x00000200 */
+#define HRTIM_TIMISR_SET1             HRTIM_TIMISR_SET1_Msk                    /*!< Slave output 1 set interrupt flag */
+#define HRTIM_TIMISR_RST1_Pos         (10U)
+#define HRTIM_TIMISR_RST1_Msk         (0x1UL << HRTIM_TIMISR_RST1_Pos)         /*!< 0x00000400 */
+#define HRTIM_TIMISR_RST1             HRTIM_TIMISR_RST1_Msk                    /*!< Slave output 1 reset interrupt flag */
+#define HRTIM_TIMISR_SET2_Pos         (11U)
+#define HRTIM_TIMISR_SET2_Msk         (0x1UL << HRTIM_TIMISR_SET2_Pos)         /*!< 0x00000800 */
+#define HRTIM_TIMISR_SET2             HRTIM_TIMISR_SET2_Msk                    /*!< Slave output 2 set interrupt flag */
+#define HRTIM_TIMISR_RST2_Pos         (12U)
+#define HRTIM_TIMISR_RST2_Msk         (0x1UL << HRTIM_TIMISR_RST2_Pos)         /*!< 0x00001000 */
+#define HRTIM_TIMISR_RST2             HRTIM_TIMISR_RST2_Msk                    /*!< Slave output 2 reset interrupt flag */
+#define HRTIM_TIMISR_RST_Pos          (13U)
+#define HRTIM_TIMISR_RST_Msk          (0x1UL << HRTIM_TIMISR_RST_Pos)          /*!< 0x00002000 */
+#define HRTIM_TIMISR_RST              HRTIM_TIMISR_RST_Msk                     /*!< Slave reset interrupt flag */
+#define HRTIM_TIMISR_DLYPRT_Pos       (14U)
+#define HRTIM_TIMISR_DLYPRT_Msk       (0x1UL << HRTIM_TIMISR_DLYPRT_Pos)       /*!< 0x00004000 */
+#define HRTIM_TIMISR_DLYPRT           HRTIM_TIMISR_DLYPRT_Msk                  /*!< Slave output 1 delay protection interrupt flag */
+#define HRTIM_TIMISR_CPPSTAT_Pos      (16U)
+#define HRTIM_TIMISR_CPPSTAT_Msk      (0x1UL << HRTIM_TIMISR_CPPSTAT_Pos)      /*!< 0x00010000 */
+#define HRTIM_TIMISR_CPPSTAT          HRTIM_TIMISR_CPPSTAT_Msk                 /*!< Slave current push-pull flag */
+#define HRTIM_TIMISR_IPPSTAT_Pos      (17U)
+#define HRTIM_TIMISR_IPPSTAT_Msk      (0x1UL << HRTIM_TIMISR_IPPSTAT_Pos)      /*!< 0x00020000 */
+#define HRTIM_TIMISR_IPPSTAT          HRTIM_TIMISR_IPPSTAT_Msk                 /*!< Slave idle push-pull flag */
+#define HRTIM_TIMISR_O1STAT_Pos       (18U)
+#define HRTIM_TIMISR_O1STAT_Msk       (0x1UL << HRTIM_TIMISR_O1STAT_Pos)       /*!< 0x00040000 */
+#define HRTIM_TIMISR_O1STAT           HRTIM_TIMISR_O1STAT_Msk                  /*!< Slave output 1 state flag */
+#define HRTIM_TIMISR_O2STAT_Pos       (19U)
+#define HRTIM_TIMISR_O2STAT_Msk       (0x1UL << HRTIM_TIMISR_O2STAT_Pos)       /*!< 0x00080000 */
+#define HRTIM_TIMISR_O2STAT           HRTIM_TIMISR_O2STAT_Msk                  /*!< Slave output 2 state flag */
+#define HRTIM_TIMISR_O1CPY_Pos        (20U)
+#define HRTIM_TIMISR_O1CPY_Msk        (0x1UL << HRTIM_TIMISR_O1CPY_Pos)        /*!< 0x00100000 */
+#define HRTIM_TIMISR_O1CPY            HRTIM_TIMISR_O1CPY_Msk                   /*!< Slave output 1 copy flag */
+#define HRTIM_TIMISR_O2CPY_Pos        (21U)
+#define HRTIM_TIMISR_O2CPY_Msk        (0x1UL << HRTIM_TIMISR_O2CPY_Pos)        /*!< 0x00200000 */
+#define HRTIM_TIMISR_O2CPY            HRTIM_TIMISR_O2CPY_Msk                   /*!< Slave output 2 copy flag */
+
+/******************** Slave Interrupt clear register **************************/
+#define HRTIM_TIMICR_CMP1C_Pos        (0U)
+#define HRTIM_TIMICR_CMP1C_Msk        (0x1UL << HRTIM_TIMICR_CMP1C_Pos)        /*!< 0x00000001 */
+#define HRTIM_TIMICR_CMP1C            HRTIM_TIMICR_CMP1C_Msk                   /*!< Slave compare 1 clear flag */
+#define HRTIM_TIMICR_CMP2C_Pos        (1U)
+#define HRTIM_TIMICR_CMP2C_Msk        (0x1UL << HRTIM_TIMICR_CMP2C_Pos)        /*!< 0x00000002 */
+#define HRTIM_TIMICR_CMP2C            HRTIM_TIMICR_CMP2C_Msk                   /*!< Slave compare 2 clear flag */
+#define HRTIM_TIMICR_CMP3C_Pos        (2U)
+#define HRTIM_TIMICR_CMP3C_Msk        (0x1UL << HRTIM_TIMICR_CMP3C_Pos)        /*!< 0x00000004 */
+#define HRTIM_TIMICR_CMP3C            HRTIM_TIMICR_CMP3C_Msk                   /*!< Slave compare 3 clear flag */
+#define HRTIM_TIMICR_CMP4C_Pos        (3U)
+#define HRTIM_TIMICR_CMP4C_Msk        (0x1UL << HRTIM_TIMICR_CMP4C_Pos)        /*!< 0x00000008 */
+#define HRTIM_TIMICR_CMP4C            HRTIM_TIMICR_CMP4C_Msk                   /*!< Slave compare 4 clear flag */
+#define HRTIM_TIMICR_REPC_Pos         (4U)
+#define HRTIM_TIMICR_REPC_Msk         (0x1UL << HRTIM_TIMICR_REPC_Pos)         /*!< 0x00000010 */
+#define HRTIM_TIMICR_REPC             HRTIM_TIMICR_REPC_Msk                    /*!< Slave repetition clear flag */
+#define HRTIM_TIMICR_UPDC_Pos         (6U)
+#define HRTIM_TIMICR_UPDC_Msk         (0x1UL << HRTIM_TIMICR_UPDC_Pos)         /*!< 0x00000040 */
+#define HRTIM_TIMICR_UPDC             HRTIM_TIMICR_UPDC_Msk                    /*!< Slave update clear flag */
+#define HRTIM_TIMICR_CPT1C_Pos        (7U)
+#define HRTIM_TIMICR_CPT1C_Msk        (0x1UL << HRTIM_TIMICR_CPT1C_Pos)        /*!< 0x00000080 */
+#define HRTIM_TIMICR_CPT1C            HRTIM_TIMICR_CPT1C_Msk                   /*!< Slave capture 1 clear flag */
+#define HRTIM_TIMICR_CPT2C_Pos        (8U)
+#define HRTIM_TIMICR_CPT2C_Msk        (0x1UL << HRTIM_TIMICR_CPT2C_Pos)        /*!< 0x00000100 */
+#define HRTIM_TIMICR_CPT2C            HRTIM_TIMICR_CPT2C_Msk                   /*!< Slave capture 2 clear flag */
+#define HRTIM_TIMICR_SET1C_Pos        (9U)
+#define HRTIM_TIMICR_SET1C_Msk        (0x1UL << HRTIM_TIMICR_SET1C_Pos)        /*!< 0x00000200 */
+#define HRTIM_TIMICR_SET1C            HRTIM_TIMICR_SET1C_Msk                   /*!< Slave output 1 set clear flag */
+#define HRTIM_TIMICR_RST1C_Pos        (10U)
+#define HRTIM_TIMICR_RST1C_Msk        (0x1UL << HRTIM_TIMICR_RST1C_Pos)        /*!< 0x00000400 */
+#define HRTIM_TIMICR_RST1C            HRTIM_TIMICR_RST1C_Msk                   /*!< Slave output 1 reset clear flag */
+#define HRTIM_TIMICR_SET2C_Pos        (11U)
+#define HRTIM_TIMICR_SET2C_Msk        (0x1UL << HRTIM_TIMICR_SET2C_Pos)        /*!< 0x00000800 */
+#define HRTIM_TIMICR_SET2C            HRTIM_TIMICR_SET2C_Msk                   /*!< Slave output 2 set clear flag */
+#define HRTIM_TIMICR_RST2C_Pos        (12U)
+#define HRTIM_TIMICR_RST2C_Msk        (0x1UL << HRTIM_TIMICR_RST2C_Pos)        /*!< 0x00001000 */
+#define HRTIM_TIMICR_RST2C            HRTIM_TIMICR_RST2C_Msk                   /*!< Slave output 2 reset clear flag */
+#define HRTIM_TIMICR_RSTC_Pos         (13U)
+#define HRTIM_TIMICR_RSTC_Msk         (0x1UL << HRTIM_TIMICR_RSTC_Pos)         /*!< 0x00002000 */
+#define HRTIM_TIMICR_RSTC             HRTIM_TIMICR_RSTC_Msk                    /*!< Slave reset clear flag */
+#define HRTIM_TIMICR_DLYPRTC_Pos      (14U)
+#define HRTIM_TIMICR_DLYPRTC_Msk      (0x1UL << HRTIM_TIMICR_DLYPRTC_Pos)      /*!< 0x00004000 */
+#define HRTIM_TIMICR_DLYPRTC          HRTIM_TIMICR_DLYPRTC_Msk                 /*!< Slave output 1 delay protection clear flag */
+
+/******************** Slave DMA/Interrupt enable register *********************/
+#define HRTIM_TIMDIER_CMP1IE_Pos      (0U)
+#define HRTIM_TIMDIER_CMP1IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP1IE_Pos)      /*!< 0x00000001 */
+#define HRTIM_TIMDIER_CMP1IE          HRTIM_TIMDIER_CMP1IE_Msk                 /*!< Slave compare 1 interrupt enable */
+#define HRTIM_TIMDIER_CMP2IE_Pos      (1U)
+#define HRTIM_TIMDIER_CMP2IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP2IE_Pos)      /*!< 0x00000002 */
+#define HRTIM_TIMDIER_CMP2IE          HRTIM_TIMDIER_CMP2IE_Msk                 /*!< Slave compare 2 interrupt enable */
+#define HRTIM_TIMDIER_CMP3IE_Pos      (2U)
+#define HRTIM_TIMDIER_CMP3IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP3IE_Pos)      /*!< 0x00000004 */
+#define HRTIM_TIMDIER_CMP3IE          HRTIM_TIMDIER_CMP3IE_Msk                 /*!< Slave compare 3 interrupt enable */
+#define HRTIM_TIMDIER_CMP4IE_Pos      (3U)
+#define HRTIM_TIMDIER_CMP4IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP4IE_Pos)      /*!< 0x00000008 */
+#define HRTIM_TIMDIER_CMP4IE          HRTIM_TIMDIER_CMP4IE_Msk                 /*!< Slave compare 4 interrupt enable */
+#define HRTIM_TIMDIER_REPIE_Pos       (4U)
+#define HRTIM_TIMDIER_REPIE_Msk       (0x1UL << HRTIM_TIMDIER_REPIE_Pos)       /*!< 0x00000010 */
+#define HRTIM_TIMDIER_REPIE           HRTIM_TIMDIER_REPIE_Msk                  /*!< Slave repetition interrupt enable */
+#define HRTIM_TIMDIER_UPDIE_Pos       (6U)
+#define HRTIM_TIMDIER_UPDIE_Msk       (0x1UL << HRTIM_TIMDIER_UPDIE_Pos)       /*!< 0x00000040 */
+#define HRTIM_TIMDIER_UPDIE           HRTIM_TIMDIER_UPDIE_Msk                  /*!< Slave update interrupt enable */
+#define HRTIM_TIMDIER_CPT1IE_Pos      (7U)
+#define HRTIM_TIMDIER_CPT1IE_Msk      (0x1UL << HRTIM_TIMDIER_CPT1IE_Pos)      /*!< 0x00000080 */
+#define HRTIM_TIMDIER_CPT1IE          HRTIM_TIMDIER_CPT1IE_Msk                 /*!< Slave capture 1 interrupt enable */
+#define HRTIM_TIMDIER_CPT2IE_Pos      (8U)
+#define HRTIM_TIMDIER_CPT2IE_Msk      (0x1UL << HRTIM_TIMDIER_CPT2IE_Pos)      /*!< 0x00000100 */
+#define HRTIM_TIMDIER_CPT2IE          HRTIM_TIMDIER_CPT2IE_Msk                 /*!< Slave capture 2 interrupt enable */
+#define HRTIM_TIMDIER_SET1IE_Pos      (9U)
+#define HRTIM_TIMDIER_SET1IE_Msk      (0x1UL << HRTIM_TIMDIER_SET1IE_Pos)      /*!< 0x00000200 */
+#define HRTIM_TIMDIER_SET1IE          HRTIM_TIMDIER_SET1IE_Msk                 /*!< Slave output 1 set interrupt enable */
+#define HRTIM_TIMDIER_RST1IE_Pos      (10U)
+#define HRTIM_TIMDIER_RST1IE_Msk      (0x1UL << HRTIM_TIMDIER_RST1IE_Pos)      /*!< 0x00000400 */
+#define HRTIM_TIMDIER_RST1IE          HRTIM_TIMDIER_RST1IE_Msk                 /*!< Slave output 1 reset interrupt enable */
+#define HRTIM_TIMDIER_SET2IE_Pos      (11U)
+#define HRTIM_TIMDIER_SET2IE_Msk      (0x1UL << HRTIM_TIMDIER_SET2IE_Pos)      /*!< 0x00000800 */
+#define HRTIM_TIMDIER_SET2IE          HRTIM_TIMDIER_SET2IE_Msk                 /*!< Slave output 2 set interrupt enable */
+#define HRTIM_TIMDIER_RST2IE_Pos      (12U)
+#define HRTIM_TIMDIER_RST2IE_Msk      (0x1UL << HRTIM_TIMDIER_RST2IE_Pos)      /*!< 0x00001000 */
+#define HRTIM_TIMDIER_RST2IE          HRTIM_TIMDIER_RST2IE_Msk                 /*!< Slave output 2 reset interrupt enable */
+#define HRTIM_TIMDIER_RSTIE_Pos       (13U)
+#define HRTIM_TIMDIER_RSTIE_Msk       (0x1UL << HRTIM_TIMDIER_RSTIE_Pos)       /*!< 0x00002000 */
+#define HRTIM_TIMDIER_RSTIE           HRTIM_TIMDIER_RSTIE_Msk                  /*!< Slave reset interrupt enable */
+#define HRTIM_TIMDIER_DLYPRTIE_Pos    (14U)
+#define HRTIM_TIMDIER_DLYPRTIE_Msk    (0x1UL << HRTIM_TIMDIER_DLYPRTIE_Pos)    /*!< 0x00004000 */
+#define HRTIM_TIMDIER_DLYPRTIE        HRTIM_TIMDIER_DLYPRTIE_Msk               /*!< Slave delay protection interrupt enable */
+
+#define HRTIM_TIMDIER_CMP1DE_Pos      (16U)
+#define HRTIM_TIMDIER_CMP1DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP1DE_Pos)      /*!< 0x00010000 */
+#define HRTIM_TIMDIER_CMP1DE          HRTIM_TIMDIER_CMP1DE_Msk                 /*!< Slave compare 1 request enable */
+#define HRTIM_TIMDIER_CMP2DE_Pos      (17U)
+#define HRTIM_TIMDIER_CMP2DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP2DE_Pos)      /*!< 0x00020000 */
+#define HRTIM_TIMDIER_CMP2DE          HRTIM_TIMDIER_CMP2DE_Msk                 /*!< Slave compare 2 request enable */
+#define HRTIM_TIMDIER_CMP3DE_Pos      (18U)
+#define HRTIM_TIMDIER_CMP3DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP3DE_Pos)      /*!< 0x00040000 */
+#define HRTIM_TIMDIER_CMP3DE          HRTIM_TIMDIER_CMP3DE_Msk                 /*!< Slave compare 3 request enable */
+#define HRTIM_TIMDIER_CMP4DE_Pos      (19U)
+#define HRTIM_TIMDIER_CMP4DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP4DE_Pos)      /*!< 0x00080000 */
+#define HRTIM_TIMDIER_CMP4DE          HRTIM_TIMDIER_CMP4DE_Msk                 /*!< Slave compare 4 request enable */
+#define HRTIM_TIMDIER_REPDE_Pos       (20U)
+#define HRTIM_TIMDIER_REPDE_Msk       (0x1UL << HRTIM_TIMDIER_REPDE_Pos)       /*!< 0x00100000 */
+#define HRTIM_TIMDIER_REPDE           HRTIM_TIMDIER_REPDE_Msk                  /*!< Slave repetition request enable */
+#define HRTIM_TIMDIER_UPDDE_Pos       (22U)
+#define HRTIM_TIMDIER_UPDDE_Msk       (0x1UL << HRTIM_TIMDIER_UPDDE_Pos)       /*!< 0x00400000 */
+#define HRTIM_TIMDIER_UPDDE           HRTIM_TIMDIER_UPDDE_Msk                  /*!< Slave update request enable */
+#define HRTIM_TIMDIER_CPT1DE_Pos      (23U)
+#define HRTIM_TIMDIER_CPT1DE_Msk      (0x1UL << HRTIM_TIMDIER_CPT1DE_Pos)      /*!< 0x00800000 */
+#define HRTIM_TIMDIER_CPT1DE          HRTIM_TIMDIER_CPT1DE_Msk                 /*!< Slave capture 1 request enable */
+#define HRTIM_TIMDIER_CPT2DE_Pos      (24U)
+#define HRTIM_TIMDIER_CPT2DE_Msk      (0x1UL << HRTIM_TIMDIER_CPT2DE_Pos)      /*!< 0x01000000 */
+#define HRTIM_TIMDIER_CPT2DE          HRTIM_TIMDIER_CPT2DE_Msk                 /*!< Slave capture 2 request enable */
+#define HRTIM_TIMDIER_SET1DE_Pos      (25U)
+#define HRTIM_TIMDIER_SET1DE_Msk      (0x1UL << HRTIM_TIMDIER_SET1DE_Pos)      /*!< 0x02000000 */
+#define HRTIM_TIMDIER_SET1DE          HRTIM_TIMDIER_SET1DE_Msk                 /*!< Slave output 1 set request enable */
+#define HRTIM_TIMDIER_RST1DE_Pos      (26U)
+#define HRTIM_TIMDIER_RST1DE_Msk      (0x1UL << HRTIM_TIMDIER_RST1DE_Pos)      /*!< 0x04000000 */
+#define HRTIM_TIMDIER_RST1DE          HRTIM_TIMDIER_RST1DE_Msk                 /*!< Slave output 1 reset request enable */
+#define HRTIM_TIMDIER_SET2DE_Pos      (27U)
+#define HRTIM_TIMDIER_SET2DE_Msk      (0x1UL << HRTIM_TIMDIER_SET2DE_Pos)      /*!< 0x08000000 */
+#define HRTIM_TIMDIER_SET2DE          HRTIM_TIMDIER_SET2DE_Msk                 /*!< Slave output 2 set request enable */
+#define HRTIM_TIMDIER_RST2DE_Pos      (28U)
+#define HRTIM_TIMDIER_RST2DE_Msk      (0x1UL << HRTIM_TIMDIER_RST2DE_Pos)      /*!< 0x10000000 */
+#define HRTIM_TIMDIER_RST2DE          HRTIM_TIMDIER_RST2DE_Msk                 /*!< Slave output 2 reset request enable */
+#define HRTIM_TIMDIER_RSTDE_Pos       (29U)
+#define HRTIM_TIMDIER_RSTDE_Msk       (0x1UL << HRTIM_TIMDIER_RSTDE_Pos)       /*!< 0x20000000 */
+#define HRTIM_TIMDIER_RSTDE           HRTIM_TIMDIER_RSTDE_Msk                  /*!< Slave reset request enable */
+#define HRTIM_TIMDIER_DLYPRTDE_Pos    (30U)
+#define HRTIM_TIMDIER_DLYPRTDE_Msk    (0x1UL << HRTIM_TIMDIER_DLYPRTDE_Pos)    /*!< 0x40000000 */
+#define HRTIM_TIMDIER_DLYPRTDE        HRTIM_TIMDIER_DLYPRTDE_Msk               /*!< Slavedelay protection request enable */
+
+/******************  Bit definition for HRTIM_CNTR register  ****************/
+#define HRTIM_CNTR_CNTR_Pos           (0U)
+#define HRTIM_CNTR_CNTR_Msk           (0xFFFFUL << HRTIM_CNTR_CNTR_Pos)        /*!< 0x0000FFFF */
+#define HRTIM_CNTR_CNTR               HRTIM_CNTR_CNTR_Msk                      /*!< Counter Value */
+
+/*******************  Bit definition for HRTIM_PER register  *****************/
+#define HRTIM_PER_PER_Pos             (0U)
+#define HRTIM_PER_PER_Msk             (0xFFFFUL << HRTIM_PER_PER_Pos)          /*!< 0x0000FFFF */
+#define HRTIM_PER_PER                 HRTIM_PER_PER_Msk                        /*!< Period Value */
+
+/*******************  Bit definition for HRTIM_REP register  *****************/
+#define HRTIM_REP_REP_Pos             (0U)
+#define HRTIM_REP_REP_Msk             (0xFFUL << HRTIM_REP_REP_Pos)            /*!< 0x000000FF */
+#define HRTIM_REP_REP                 HRTIM_REP_REP_Msk                        /*!< Repetition Value */
+
+/*******************  Bit definition for HRTIM_CMP1R register  *****************/
+#define HRTIM_CMP1R_CMP1R_Pos         (0U)
+#define HRTIM_CMP1R_CMP1R_Msk         (0xFFFFUL << HRTIM_CMP1R_CMP1R_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_CMP1R_CMP1R             HRTIM_CMP1R_CMP1R_Msk                    /*!< Compare Value */
+
+/*******************  Bit definition for HRTIM_CMP1CR register  *****************/
+#define HRTIM_CMP1CR_CMP1CR_Pos       (0U)
+#define HRTIM_CMP1CR_CMP1CR_Msk       (0xFFFFFFFFUL << HRTIM_CMP1CR_CMP1CR_Pos) /*!< 0xFFFFFFFF */
+#define HRTIM_CMP1CR_CMP1CR           HRTIM_CMP1CR_CMP1CR_Msk                  /*!< Compare Value */
+
+/*******************  Bit definition for HRTIM_CMP2R register  *****************/
+#define HRTIM_CMP2R_CMP2R_Pos         (0U)
+#define HRTIM_CMP2R_CMP2R_Msk         (0xFFFFUL << HRTIM_CMP2R_CMP2R_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_CMP2R_CMP2R             HRTIM_CMP2R_CMP2R_Msk                    /*!< Compare Value */
+
+/*******************  Bit definition for HRTIM_CMP3R register  *****************/
+#define HRTIM_CMP3R_CMP3R_Pos         (0U)
+#define HRTIM_CMP3R_CMP3R_Msk         (0xFFFFUL << HRTIM_CMP3R_CMP3R_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_CMP3R_CMP3R             HRTIM_CMP3R_CMP3R_Msk                    /*!< Compare Value */
+
+/*******************  Bit definition for HRTIM_CMP4R register  *****************/
+#define HRTIM_CMP4R_CMP4R_Pos         (0U)
+#define HRTIM_CMP4R_CMP4R_Msk         (0xFFFFUL << HRTIM_CMP4R_CMP4R_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_CMP4R_CMP4R             HRTIM_CMP4R_CMP4R_Msk                    /*!< Compare Value */
+
+/*******************  Bit definition for HRTIM_CPT1R register  ****************/
+#define HRTIM_CPT1R_CPT1R_Pos         (0U)
+#define HRTIM_CPT1R_CPT1R_Msk         (0xFFFFUL << HRTIM_CPT1R_CPT1R_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_CPT1R_CPT1R             HRTIM_CPT1R_CPT1R_Msk                    /*!< Capture Value */
+
+/*******************  Bit definition for HRTIM_CPT2R register  ****************/
+#define HRTIM_CPT2R_CPT2R_Pos         (0U)
+#define HRTIM_CPT2R_CPT2R_Msk         (0xFFFFUL << HRTIM_CPT2R_CPT2R_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_CPT2R_CPT2R             HRTIM_CPT2R_CPT2R_Msk                    /*!< Capture Value */
+
+/******************** Bit definition for Slave Deadtime register **************/
+#define HRTIM_DTR_DTR_Pos             (0U)
+#define HRTIM_DTR_DTR_Msk             (0x1FFUL << HRTIM_DTR_DTR_Pos)           /*!< 0x000001FF */
+#define HRTIM_DTR_DTR                 HRTIM_DTR_DTR_Msk                        /*!< Dead time rising value */
+#define HRTIM_DTR_DTR_0               (0x001UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000001 */
+#define HRTIM_DTR_DTR_1               (0x002UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000002 */
+#define HRTIM_DTR_DTR_2               (0x004UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000004 */
+#define HRTIM_DTR_DTR_3               (0x008UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000008 */
+#define HRTIM_DTR_DTR_4               (0x010UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000010 */
+#define HRTIM_DTR_DTR_5               (0x020UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000020 */
+#define HRTIM_DTR_DTR_6               (0x040UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000040 */
+#define HRTIM_DTR_DTR_7               (0x080UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000080 */
+#define HRTIM_DTR_DTR_8               (0x100UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000100 */
+#define HRTIM_DTR_SDTR_Pos            (9U)
+#define HRTIM_DTR_SDTR_Msk            (0x1UL << HRTIM_DTR_SDTR_Pos)            /*!< 0x00000200 */
+#define HRTIM_DTR_SDTR                HRTIM_DTR_SDTR_Msk                       /*!< Sign dead time rising value */
+#define HRTIM_DTR_DTPRSC_Pos          (10U)
+#define HRTIM_DTR_DTPRSC_Msk          (0x7UL << HRTIM_DTR_DTPRSC_Pos)          /*!< 0x00001C00 */
+#define HRTIM_DTR_DTPRSC              HRTIM_DTR_DTPRSC_Msk                     /*!< Dead time prescaler */
+#define HRTIM_DTR_DTPRSC_0            (0x1UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00000400 */
+#define HRTIM_DTR_DTPRSC_1            (0x2UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00000800 */
+#define HRTIM_DTR_DTPRSC_2            (0x4UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00001000 */
+#define HRTIM_DTR_DTRSLK_Pos          (14U)
+#define HRTIM_DTR_DTRSLK_Msk          (0x1UL << HRTIM_DTR_DTRSLK_Pos)          /*!< 0x00004000 */
+#define HRTIM_DTR_DTRSLK              HRTIM_DTR_DTRSLK_Msk                     /*!< Dead time rising sign lock */
+#define HRTIM_DTR_DTRLK_Pos           (15U)
+#define HRTIM_DTR_DTRLK_Msk           (0x1UL << HRTIM_DTR_DTRLK_Pos)           /*!< 0x00008000 */
+#define HRTIM_DTR_DTRLK               HRTIM_DTR_DTRLK_Msk                      /*!< Dead time rising lock */
+#define HRTIM_DTR_DTF_Pos             (16U)
+#define HRTIM_DTR_DTF_Msk             (0x1FFUL << HRTIM_DTR_DTF_Pos)           /*!< 0x01FF0000 */
+#define HRTIM_DTR_DTF                 HRTIM_DTR_DTF_Msk                        /*!< Dead time falling value */
+#define HRTIM_DTR_DTF_0               (0x001UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00010000 */
+#define HRTIM_DTR_DTF_1               (0x002UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00020000 */
+#define HRTIM_DTR_DTF_2               (0x004UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00040000 */
+#define HRTIM_DTR_DTF_3               (0x008UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00080000 */
+#define HRTIM_DTR_DTF_4               (0x010UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00100000 */
+#define HRTIM_DTR_DTF_5               (0x020UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00200000 */
+#define HRTIM_DTR_DTF_6               (0x040UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00400000 */
+#define HRTIM_DTR_DTF_7               (0x080UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00800000 */
+#define HRTIM_DTR_DTF_8               (0x100UL << HRTIM_DTR_DTF_Pos)            /*!< 0x01000000 */
+#define HRTIM_DTR_SDTF_Pos            (25U)
+#define HRTIM_DTR_SDTF_Msk            (0x1UL << HRTIM_DTR_SDTF_Pos)            /*!< 0x02000000 */
+#define HRTIM_DTR_SDTF                HRTIM_DTR_SDTF_Msk                       /*!< Sign dead time falling value */
+#define HRTIM_DTR_DTFSLK_Pos          (30U)
+#define HRTIM_DTR_DTFSLK_Msk          (0x1UL << HRTIM_DTR_DTFSLK_Pos)          /*!< 0x40000000 */
+#define HRTIM_DTR_DTFSLK              HRTIM_DTR_DTFSLK_Msk                     /*!< Dead time falling sign lock */
+#define HRTIM_DTR_DTFLK_Pos           (31U)
+#define HRTIM_DTR_DTFLK_Msk           (0x1UL << HRTIM_DTR_DTFLK_Pos)           /*!< 0x80000000 */
+#define HRTIM_DTR_DTFLK               HRTIM_DTR_DTFLK_Msk                      /*!< Dead time falling lock */
+
+/**** Bit definition for Slave Output 1 set register **************************/
+#define HRTIM_SET1R_SST_Pos           (0U)
+#define HRTIM_SET1R_SST_Msk           (0x1UL << HRTIM_SET1R_SST_Pos)           /*!< 0x00000001 */
+#define HRTIM_SET1R_SST               HRTIM_SET1R_SST_Msk                      /*!< software set trigger */
+#define HRTIM_SET1R_RESYNC_Pos        (1U)
+#define HRTIM_SET1R_RESYNC_Msk        (0x1UL << HRTIM_SET1R_RESYNC_Pos)        /*!< 0x00000002 */
+#define HRTIM_SET1R_RESYNC            HRTIM_SET1R_RESYNC_Msk                   /*!< Timer A resynchronization */
+#define HRTIM_SET1R_PER_Pos           (2U)
+#define HRTIM_SET1R_PER_Msk           (0x1UL << HRTIM_SET1R_PER_Pos)           /*!< 0x00000004 */
+#define HRTIM_SET1R_PER               HRTIM_SET1R_PER_Msk                      /*!< Timer A period */
+#define HRTIM_SET1R_CMP1_Pos          (3U)
+#define HRTIM_SET1R_CMP1_Msk          (0x1UL << HRTIM_SET1R_CMP1_Pos)          /*!< 0x00000008 */
+#define HRTIM_SET1R_CMP1              HRTIM_SET1R_CMP1_Msk                     /*!< Timer A compare 1 */
+#define HRTIM_SET1R_CMP2_Pos          (4U)
+#define HRTIM_SET1R_CMP2_Msk          (0x1UL << HRTIM_SET1R_CMP2_Pos)          /*!< 0x00000010 */
+#define HRTIM_SET1R_CMP2              HRTIM_SET1R_CMP2_Msk                     /*!< Timer A compare 2 */
+#define HRTIM_SET1R_CMP3_Pos          (5U)
+#define HRTIM_SET1R_CMP3_Msk          (0x1UL << HRTIM_SET1R_CMP3_Pos)          /*!< 0x00000020 */
+#define HRTIM_SET1R_CMP3              HRTIM_SET1R_CMP3_Msk                     /*!< Timer A compare 3 */
+#define HRTIM_SET1R_CMP4_Pos          (6U)
+#define HRTIM_SET1R_CMP4_Msk          (0x1UL << HRTIM_SET1R_CMP4_Pos)          /*!< 0x00000040 */
+#define HRTIM_SET1R_CMP4              HRTIM_SET1R_CMP4_Msk                     /*!< Timer A compare 4 */
+
+#define HRTIM_SET1R_MSTPER_Pos        (7U)
+#define HRTIM_SET1R_MSTPER_Msk        (0x1UL << HRTIM_SET1R_MSTPER_Pos)        /*!< 0x00000080 */
+#define HRTIM_SET1R_MSTPER            HRTIM_SET1R_MSTPER_Msk                   /*!< Master period */
+#define HRTIM_SET1R_MSTCMP1_Pos       (8U)
+#define HRTIM_SET1R_MSTCMP1_Msk       (0x1UL << HRTIM_SET1R_MSTCMP1_Pos)       /*!< 0x00000100 */
+#define HRTIM_SET1R_MSTCMP1           HRTIM_SET1R_MSTCMP1_Msk                  /*!< Master compare 1 */
+#define HRTIM_SET1R_MSTCMP2_Pos       (9U)
+#define HRTIM_SET1R_MSTCMP2_Msk       (0x1UL << HRTIM_SET1R_MSTCMP2_Pos)       /*!< 0x00000200 */
+#define HRTIM_SET1R_MSTCMP2           HRTIM_SET1R_MSTCMP2_Msk                  /*!< Master compare 2 */
+#define HRTIM_SET1R_MSTCMP3_Pos       (10U)
+#define HRTIM_SET1R_MSTCMP3_Msk       (0x1UL << HRTIM_SET1R_MSTCMP3_Pos)       /*!< 0x00000400 */
+#define HRTIM_SET1R_MSTCMP3           HRTIM_SET1R_MSTCMP3_Msk                  /*!< Master compare 3 */
+#define HRTIM_SET1R_MSTCMP4_Pos       (11U)
+#define HRTIM_SET1R_MSTCMP4_Msk       (0x1UL << HRTIM_SET1R_MSTCMP4_Pos)       /*!< 0x00000800 */
+#define HRTIM_SET1R_MSTCMP4           HRTIM_SET1R_MSTCMP4_Msk                  /*!< Master compare 4 */
+
+#define HRTIM_SET1R_TIMEVNT1_Pos      (12U)
+#define HRTIM_SET1R_TIMEVNT1_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT1_Pos)      /*!< 0x00001000 */
+#define HRTIM_SET1R_TIMEVNT1          HRTIM_SET1R_TIMEVNT1_Msk                 /*!< Timer event 1 */
+#define HRTIM_SET1R_TIMEVNT2_Pos      (13U)
+#define HRTIM_SET1R_TIMEVNT2_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT2_Pos)      /*!< 0x00002000 */
+#define HRTIM_SET1R_TIMEVNT2          HRTIM_SET1R_TIMEVNT2_Msk                 /*!< Timer event 2 */
+#define HRTIM_SET1R_TIMEVNT3_Pos      (14U)
+#define HRTIM_SET1R_TIMEVNT3_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT3_Pos)      /*!< 0x00004000 */
+#define HRTIM_SET1R_TIMEVNT3          HRTIM_SET1R_TIMEVNT3_Msk                 /*!< Timer event 3 */
+#define HRTIM_SET1R_TIMEVNT4_Pos      (15U)
+#define HRTIM_SET1R_TIMEVNT4_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT4_Pos)      /*!< 0x00008000 */
+#define HRTIM_SET1R_TIMEVNT4          HRTIM_SET1R_TIMEVNT4_Msk                 /*!< Timer event 4 */
+#define HRTIM_SET1R_TIMEVNT5_Pos      (16U)
+#define HRTIM_SET1R_TIMEVNT5_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT5_Pos)      /*!< 0x00010000 */
+#define HRTIM_SET1R_TIMEVNT5          HRTIM_SET1R_TIMEVNT5_Msk                 /*!< Timer event 5 */
+#define HRTIM_SET1R_TIMEVNT6_Pos      (17U)
+#define HRTIM_SET1R_TIMEVNT6_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT6_Pos)      /*!< 0x00020000 */
+#define HRTIM_SET1R_TIMEVNT6          HRTIM_SET1R_TIMEVNT6_Msk                 /*!< Timer event 6 */
+#define HRTIM_SET1R_TIMEVNT7_Pos      (18U)
+#define HRTIM_SET1R_TIMEVNT7_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT7_Pos)      /*!< 0x00040000 */
+#define HRTIM_SET1R_TIMEVNT7          HRTIM_SET1R_TIMEVNT7_Msk                 /*!< Timer event 7 */
+#define HRTIM_SET1R_TIMEVNT8_Pos      (19U)
+#define HRTIM_SET1R_TIMEVNT8_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT8_Pos)      /*!< 0x00080000 */
+#define HRTIM_SET1R_TIMEVNT8          HRTIM_SET1R_TIMEVNT8_Msk                 /*!< Timer event 8 */
+#define HRTIM_SET1R_TIMEVNT9_Pos      (20U)
+#define HRTIM_SET1R_TIMEVNT9_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT9_Pos)      /*!< 0x00100000 */
+#define HRTIM_SET1R_TIMEVNT9          HRTIM_SET1R_TIMEVNT9_Msk                 /*!< Timer event 9 */
+
+#define HRTIM_SET1R_EXTVNT1_Pos       (21U)
+#define HRTIM_SET1R_EXTVNT1_Msk       (0x1UL << HRTIM_SET1R_EXTVNT1_Pos)       /*!< 0x00200000 */
+#define HRTIM_SET1R_EXTVNT1           HRTIM_SET1R_EXTVNT1_Msk                  /*!< External event 1 */
+#define HRTIM_SET1R_EXTVNT2_Pos       (22U)
+#define HRTIM_SET1R_EXTVNT2_Msk       (0x1UL << HRTIM_SET1R_EXTVNT2_Pos)       /*!< 0x00400000 */
+#define HRTIM_SET1R_EXTVNT2           HRTIM_SET1R_EXTVNT2_Msk                  /*!< External event 2 */
+#define HRTIM_SET1R_EXTVNT3_Pos       (23U)
+#define HRTIM_SET1R_EXTVNT3_Msk       (0x1UL << HRTIM_SET1R_EXTVNT3_Pos)       /*!< 0x00800000 */
+#define HRTIM_SET1R_EXTVNT3           HRTIM_SET1R_EXTVNT3_Msk                  /*!< External event 3 */
+#define HRTIM_SET1R_EXTVNT4_Pos       (24U)
+#define HRTIM_SET1R_EXTVNT4_Msk       (0x1UL << HRTIM_SET1R_EXTVNT4_Pos)       /*!< 0x01000000 */
+#define HRTIM_SET1R_EXTVNT4           HRTIM_SET1R_EXTVNT4_Msk                  /*!< External event 4 */
+#define HRTIM_SET1R_EXTVNT5_Pos       (25U)
+#define HRTIM_SET1R_EXTVNT5_Msk       (0x1UL << HRTIM_SET1R_EXTVNT5_Pos)       /*!< 0x02000000 */
+#define HRTIM_SET1R_EXTVNT5           HRTIM_SET1R_EXTVNT5_Msk                  /*!< External event 5 */
+#define HRTIM_SET1R_EXTVNT6_Pos       (26U)
+#define HRTIM_SET1R_EXTVNT6_Msk       (0x1UL << HRTIM_SET1R_EXTVNT6_Pos)       /*!< 0x04000000 */
+#define HRTIM_SET1R_EXTVNT6           HRTIM_SET1R_EXTVNT6_Msk                  /*!< External event 6 */
+#define HRTIM_SET1R_EXTVNT7_Pos       (27U)
+#define HRTIM_SET1R_EXTVNT7_Msk       (0x1UL << HRTIM_SET1R_EXTVNT7_Pos)       /*!< 0x08000000 */
+#define HRTIM_SET1R_EXTVNT7           HRTIM_SET1R_EXTVNT7_Msk                  /*!< External event 7 */
+#define HRTIM_SET1R_EXTVNT8_Pos       (28U)
+#define HRTIM_SET1R_EXTVNT8_Msk       (0x1UL << HRTIM_SET1R_EXTVNT8_Pos)       /*!< 0x10000000 */
+#define HRTIM_SET1R_EXTVNT8           HRTIM_SET1R_EXTVNT8_Msk                  /*!< External event 8 */
+#define HRTIM_SET1R_EXTVNT9_Pos       (29U)
+#define HRTIM_SET1R_EXTVNT9_Msk       (0x1UL << HRTIM_SET1R_EXTVNT9_Pos)       /*!< 0x20000000 */
+#define HRTIM_SET1R_EXTVNT9           HRTIM_SET1R_EXTVNT9_Msk                  /*!< External event 9 */
+#define HRTIM_SET1R_EXTVNT10_Pos      (30U)
+#define HRTIM_SET1R_EXTVNT10_Msk      (0x1UL << HRTIM_SET1R_EXTVNT10_Pos)      /*!< 0x40000000 */
+#define HRTIM_SET1R_EXTVNT10          HRTIM_SET1R_EXTVNT10_Msk                 /*!< External event 10 */
+
+#define HRTIM_SET1R_UPDATE_Pos        (31U)
+#define HRTIM_SET1R_UPDATE_Msk        (0x1UL << HRTIM_SET1R_UPDATE_Pos)        /*!< 0x80000000 */
+#define HRTIM_SET1R_UPDATE            HRTIM_SET1R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */
+
+/**** Bit definition for Slave Output 1 reset register ************************/
+#define HRTIM_RST1R_SRT_Pos           (0U)
+#define HRTIM_RST1R_SRT_Msk           (0x1UL << HRTIM_RST1R_SRT_Pos)           /*!< 0x00000001 */
+#define HRTIM_RST1R_SRT               HRTIM_RST1R_SRT_Msk                      /*!< software reset trigger */
+#define HRTIM_RST1R_RESYNC_Pos        (1U)
+#define HRTIM_RST1R_RESYNC_Msk        (0x1UL << HRTIM_RST1R_RESYNC_Pos)        /*!< 0x00000002 */
+#define HRTIM_RST1R_RESYNC            HRTIM_RST1R_RESYNC_Msk                   /*!< Timer A resynchronization */
+#define HRTIM_RST1R_PER_Pos           (2U)
+#define HRTIM_RST1R_PER_Msk           (0x1UL << HRTIM_RST1R_PER_Pos)           /*!< 0x00000004 */
+#define HRTIM_RST1R_PER               HRTIM_RST1R_PER_Msk                      /*!< Timer A period */
+#define HRTIM_RST1R_CMP1_Pos          (3U)
+#define HRTIM_RST1R_CMP1_Msk          (0x1UL << HRTIM_RST1R_CMP1_Pos)          /*!< 0x00000008 */
+#define HRTIM_RST1R_CMP1              HRTIM_RST1R_CMP1_Msk                     /*!< Timer A compare 1 */
+#define HRTIM_RST1R_CMP2_Pos          (4U)
+#define HRTIM_RST1R_CMP2_Msk          (0x1UL << HRTIM_RST1R_CMP2_Pos)          /*!< 0x00000010 */
+#define HRTIM_RST1R_CMP2              HRTIM_RST1R_CMP2_Msk                     /*!< Timer A compare 2 */
+#define HRTIM_RST1R_CMP3_Pos          (5U)
+#define HRTIM_RST1R_CMP3_Msk          (0x1UL << HRTIM_RST1R_CMP3_Pos)          /*!< 0x00000020 */
+#define HRTIM_RST1R_CMP3              HRTIM_RST1R_CMP3_Msk                     /*!< Timer A compare 3 */
+#define HRTIM_RST1R_CMP4_Pos          (6U)
+#define HRTIM_RST1R_CMP4_Msk          (0x1UL << HRTIM_RST1R_CMP4_Pos)          /*!< 0x00000040 */
+#define HRTIM_RST1R_CMP4              HRTIM_RST1R_CMP4_Msk                     /*!< Timer A compare 4 */
+
+#define HRTIM_RST1R_MSTPER_Pos        (7U)
+#define HRTIM_RST1R_MSTPER_Msk        (0x1UL << HRTIM_RST1R_MSTPER_Pos)        /*!< 0x00000080 */
+#define HRTIM_RST1R_MSTPER            HRTIM_RST1R_MSTPER_Msk                   /*!< Master period */
+#define HRTIM_RST1R_MSTCMP1_Pos       (8U)
+#define HRTIM_RST1R_MSTCMP1_Msk       (0x1UL << HRTIM_RST1R_MSTCMP1_Pos)       /*!< 0x00000100 */
+#define HRTIM_RST1R_MSTCMP1           HRTIM_RST1R_MSTCMP1_Msk                  /*!< Master compare 1 */
+#define HRTIM_RST1R_MSTCMP2_Pos       (9U)
+#define HRTIM_RST1R_MSTCMP2_Msk       (0x1UL << HRTIM_RST1R_MSTCMP2_Pos)       /*!< 0x00000200 */
+#define HRTIM_RST1R_MSTCMP2           HRTIM_RST1R_MSTCMP2_Msk                  /*!< Master compare 2 */
+#define HRTIM_RST1R_MSTCMP3_Pos       (10U)
+#define HRTIM_RST1R_MSTCMP3_Msk       (0x1UL << HRTIM_RST1R_MSTCMP3_Pos)       /*!< 0x00000400 */
+#define HRTIM_RST1R_MSTCMP3           HRTIM_RST1R_MSTCMP3_Msk                  /*!< Master compare 3 */
+#define HRTIM_RST1R_MSTCMP4_Pos       (11U)
+#define HRTIM_RST1R_MSTCMP4_Msk       (0x1UL << HRTIM_RST1R_MSTCMP4_Pos)       /*!< 0x00000800 */
+#define HRTIM_RST1R_MSTCMP4           HRTIM_RST1R_MSTCMP4_Msk                  /*!< Master compare 4 */
+
+#define HRTIM_RST1R_TIMEVNT1_Pos      (12U)
+#define HRTIM_RST1R_TIMEVNT1_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT1_Pos)      /*!< 0x00001000 */
+#define HRTIM_RST1R_TIMEVNT1          HRTIM_RST1R_TIMEVNT1_Msk                 /*!< Timer event 1 */
+#define HRTIM_RST1R_TIMEVNT2_Pos      (13U)
+#define HRTIM_RST1R_TIMEVNT2_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT2_Pos)      /*!< 0x00002000 */
+#define HRTIM_RST1R_TIMEVNT2          HRTIM_RST1R_TIMEVNT2_Msk                 /*!< Timer event 2 */
+#define HRTIM_RST1R_TIMEVNT3_Pos      (14U)
+#define HRTIM_RST1R_TIMEVNT3_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT3_Pos)      /*!< 0x00004000 */
+#define HRTIM_RST1R_TIMEVNT3          HRTIM_RST1R_TIMEVNT3_Msk                 /*!< Timer event 3 */
+#define HRTIM_RST1R_TIMEVNT4_Pos      (15U)
+#define HRTIM_RST1R_TIMEVNT4_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT4_Pos)      /*!< 0x00008000 */
+#define HRTIM_RST1R_TIMEVNT4          HRTIM_RST1R_TIMEVNT4_Msk                 /*!< Timer event 4 */
+#define HRTIM_RST1R_TIMEVNT5_Pos      (16U)
+#define HRTIM_RST1R_TIMEVNT5_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT5_Pos)      /*!< 0x00010000 */
+#define HRTIM_RST1R_TIMEVNT5          HRTIM_RST1R_TIMEVNT5_Msk                 /*!< Timer event 5 */
+#define HRTIM_RST1R_TIMEVNT6_Pos      (17U)
+#define HRTIM_RST1R_TIMEVNT6_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT6_Pos)      /*!< 0x00020000 */
+#define HRTIM_RST1R_TIMEVNT6          HRTIM_RST1R_TIMEVNT6_Msk                 /*!< Timer event 6 */
+#define HRTIM_RST1R_TIMEVNT7_Pos      (18U)
+#define HRTIM_RST1R_TIMEVNT7_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT7_Pos)      /*!< 0x00040000 */
+#define HRTIM_RST1R_TIMEVNT7          HRTIM_RST1R_TIMEVNT7_Msk                 /*!< Timer event 7 */
+#define HRTIM_RST1R_TIMEVNT8_Pos      (19U)
+#define HRTIM_RST1R_TIMEVNT8_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT8_Pos)      /*!< 0x00080000 */
+#define HRTIM_RST1R_TIMEVNT8          HRTIM_RST1R_TIMEVNT8_Msk                 /*!< Timer event 8 */
+#define HRTIM_RST1R_TIMEVNT9_Pos      (20U)
+#define HRTIM_RST1R_TIMEVNT9_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT9_Pos)      /*!< 0x00100000 */
+#define HRTIM_RST1R_TIMEVNT9          HRTIM_RST1R_TIMEVNT9_Msk                 /*!< Timer event 9 */
+
+#define HRTIM_RST1R_EXTVNT1_Pos       (21U)
+#define HRTIM_RST1R_EXTVNT1_Msk       (0x1UL << HRTIM_RST1R_EXTVNT1_Pos)       /*!< 0x00200000 */
+#define HRTIM_RST1R_EXTVNT1           HRTIM_RST1R_EXTVNT1_Msk                  /*!< External event 1 */
+#define HRTIM_RST1R_EXTVNT2_Pos       (22U)
+#define HRTIM_RST1R_EXTVNT2_Msk       (0x1UL << HRTIM_RST1R_EXTVNT2_Pos)       /*!< 0x00400000 */
+#define HRTIM_RST1R_EXTVNT2           HRTIM_RST1R_EXTVNT2_Msk                  /*!< External event 2 */
+#define HRTIM_RST1R_EXTVNT3_Pos       (23U)
+#define HRTIM_RST1R_EXTVNT3_Msk       (0x1UL << HRTIM_RST1R_EXTVNT3_Pos)       /*!< 0x00800000 */
+#define HRTIM_RST1R_EXTVNT3           HRTIM_RST1R_EXTVNT3_Msk                  /*!< External event 3 */
+#define HRTIM_RST1R_EXTVNT4_Pos       (24U)
+#define HRTIM_RST1R_EXTVNT4_Msk       (0x1UL << HRTIM_RST1R_EXTVNT4_Pos)       /*!< 0x01000000 */
+#define HRTIM_RST1R_EXTVNT4           HRTIM_RST1R_EXTVNT4_Msk                  /*!< External event 4 */
+#define HRTIM_RST1R_EXTVNT5_Pos       (25U)
+#define HRTIM_RST1R_EXTVNT5_Msk       (0x1UL << HRTIM_RST1R_EXTVNT5_Pos)       /*!< 0x02000000 */
+#define HRTIM_RST1R_EXTVNT5           HRTIM_RST1R_EXTVNT5_Msk                  /*!< External event 5 */
+#define HRTIM_RST1R_EXTVNT6_Pos       (26U)
+#define HRTIM_RST1R_EXTVNT6_Msk       (0x1UL << HRTIM_RST1R_EXTVNT6_Pos)       /*!< 0x04000000 */
+#define HRTIM_RST1R_EXTVNT6           HRTIM_RST1R_EXTVNT6_Msk                  /*!< External event 6 */
+#define HRTIM_RST1R_EXTVNT7_Pos       (27U)
+#define HRTIM_RST1R_EXTVNT7_Msk       (0x1UL << HRTIM_RST1R_EXTVNT7_Pos)       /*!< 0x08000000 */
+#define HRTIM_RST1R_EXTVNT7           HRTIM_RST1R_EXTVNT7_Msk                  /*!< External event 7 */
+#define HRTIM_RST1R_EXTVNT8_Pos       (28U)
+#define HRTIM_RST1R_EXTVNT8_Msk       (0x1UL << HRTIM_RST1R_EXTVNT8_Pos)       /*!< 0x10000000 */
+#define HRTIM_RST1R_EXTVNT8           HRTIM_RST1R_EXTVNT8_Msk                  /*!< External event 8 */
+#define HRTIM_RST1R_EXTVNT9_Pos       (29U)
+#define HRTIM_RST1R_EXTVNT9_Msk       (0x1UL << HRTIM_RST1R_EXTVNT9_Pos)       /*!< 0x20000000 */
+#define HRTIM_RST1R_EXTVNT9           HRTIM_RST1R_EXTVNT9_Msk                  /*!< External event 9 */
+#define HRTIM_RST1R_EXTVNT10_Pos      (30U)
+#define HRTIM_RST1R_EXTVNT10_Msk      (0x1UL << HRTIM_RST1R_EXTVNT10_Pos)      /*!< 0x40000000 */
+#define HRTIM_RST1R_EXTVNT10          HRTIM_RST1R_EXTVNT10_Msk                 /*!< External event 10 */
+
+#define HRTIM_RST1R_UPDATE_Pos        (31U)
+#define HRTIM_RST1R_UPDATE_Msk        (0x1UL << HRTIM_RST1R_UPDATE_Pos)        /*!< 0x80000000 */
+#define HRTIM_RST1R_UPDATE            HRTIM_RST1R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */
+
+
+/**** Bit definition for Slave Output 2 set register **************************/
+#define HRTIM_SET2R_SST_Pos           (0U)
+#define HRTIM_SET2R_SST_Msk           (0x1UL << HRTIM_SET2R_SST_Pos)           /*!< 0x00000001 */
+#define HRTIM_SET2R_SST               HRTIM_SET2R_SST_Msk                      /*!< software set trigger */
+#define HRTIM_SET2R_RESYNC_Pos        (1U)
+#define HRTIM_SET2R_RESYNC_Msk        (0x1UL << HRTIM_SET2R_RESYNC_Pos)        /*!< 0x00000002 */
+#define HRTIM_SET2R_RESYNC            HRTIM_SET2R_RESYNC_Msk                   /*!< Timer A resynchronization */
+#define HRTIM_SET2R_PER_Pos           (2U)
+#define HRTIM_SET2R_PER_Msk           (0x1UL << HRTIM_SET2R_PER_Pos)           /*!< 0x00000004 */
+#define HRTIM_SET2R_PER               HRTIM_SET2R_PER_Msk                      /*!< Timer A period */
+#define HRTIM_SET2R_CMP1_Pos          (3U)
+#define HRTIM_SET2R_CMP1_Msk          (0x1UL << HRTIM_SET2R_CMP1_Pos)          /*!< 0x00000008 */
+#define HRTIM_SET2R_CMP1              HRTIM_SET2R_CMP1_Msk                     /*!< Timer A compare 1 */
+#define HRTIM_SET2R_CMP2_Pos          (4U)
+#define HRTIM_SET2R_CMP2_Msk          (0x1UL << HRTIM_SET2R_CMP2_Pos)          /*!< 0x00000010 */
+#define HRTIM_SET2R_CMP2              HRTIM_SET2R_CMP2_Msk                     /*!< Timer A compare 2 */
+#define HRTIM_SET2R_CMP3_Pos          (5U)
+#define HRTIM_SET2R_CMP3_Msk          (0x1UL << HRTIM_SET2R_CMP3_Pos)          /*!< 0x00000020 */
+#define HRTIM_SET2R_CMP3              HRTIM_SET2R_CMP3_Msk                     /*!< Timer A compare 3 */
+#define HRTIM_SET2R_CMP4_Pos          (6U)
+#define HRTIM_SET2R_CMP4_Msk          (0x1UL << HRTIM_SET2R_CMP4_Pos)          /*!< 0x00000040 */
+#define HRTIM_SET2R_CMP4              HRTIM_SET2R_CMP4_Msk                     /*!< Timer A compare 4 */
+
+#define HRTIM_SET2R_MSTPER_Pos        (7U)
+#define HRTIM_SET2R_MSTPER_Msk        (0x1UL << HRTIM_SET2R_MSTPER_Pos)        /*!< 0x00000080 */
+#define HRTIM_SET2R_MSTPER            HRTIM_SET2R_MSTPER_Msk                   /*!< Master period */
+#define HRTIM_SET2R_MSTCMP1_Pos       (8U)
+#define HRTIM_SET2R_MSTCMP1_Msk       (0x1UL << HRTIM_SET2R_MSTCMP1_Pos)       /*!< 0x00000100 */
+#define HRTIM_SET2R_MSTCMP1           HRTIM_SET2R_MSTCMP1_Msk                  /*!< Master compare 1 */
+#define HRTIM_SET2R_MSTCMP2_Pos       (9U)
+#define HRTIM_SET2R_MSTCMP2_Msk       (0x1UL << HRTIM_SET2R_MSTCMP2_Pos)       /*!< 0x00000200 */
+#define HRTIM_SET2R_MSTCMP2           HRTIM_SET2R_MSTCMP2_Msk                  /*!< Master compare 2 */
+#define HRTIM_SET2R_MSTCMP3_Pos       (10U)
+#define HRTIM_SET2R_MSTCMP3_Msk       (0x1UL << HRTIM_SET2R_MSTCMP3_Pos)       /*!< 0x00000400 */
+#define HRTIM_SET2R_MSTCMP3           HRTIM_SET2R_MSTCMP3_Msk                  /*!< Master compare 3 */
+#define HRTIM_SET2R_MSTCMP4_Pos       (11U)
+#define HRTIM_SET2R_MSTCMP4_Msk       (0x1UL << HRTIM_SET2R_MSTCMP4_Pos)       /*!< 0x00000800 */
+#define HRTIM_SET2R_MSTCMP4           HRTIM_SET2R_MSTCMP4_Msk                  /*!< Master compare 4 */
+
+#define HRTIM_SET2R_TIMEVNT1_Pos      (12U)
+#define HRTIM_SET2R_TIMEVNT1_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT1_Pos)      /*!< 0x00001000 */
+#define HRTIM_SET2R_TIMEVNT1          HRTIM_SET2R_TIMEVNT1_Msk                 /*!< Timer event 1 */
+#define HRTIM_SET2R_TIMEVNT2_Pos      (13U)
+#define HRTIM_SET2R_TIMEVNT2_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT2_Pos)      /*!< 0x00002000 */
+#define HRTIM_SET2R_TIMEVNT2          HRTIM_SET2R_TIMEVNT2_Msk                 /*!< Timer event 2 */
+#define HRTIM_SET2R_TIMEVNT3_Pos      (14U)
+#define HRTIM_SET2R_TIMEVNT3_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT3_Pos)      /*!< 0x00004000 */
+#define HRTIM_SET2R_TIMEVNT3          HRTIM_SET2R_TIMEVNT3_Msk                 /*!< Timer event 3 */
+#define HRTIM_SET2R_TIMEVNT4_Pos      (15U)
+#define HRTIM_SET2R_TIMEVNT4_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT4_Pos)      /*!< 0x00008000 */
+#define HRTIM_SET2R_TIMEVNT4          HRTIM_SET2R_TIMEVNT4_Msk                 /*!< Timer event 4 */
+#define HRTIM_SET2R_TIMEVNT5_Pos      (16U)
+#define HRTIM_SET2R_TIMEVNT5_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT5_Pos)      /*!< 0x00010000 */
+#define HRTIM_SET2R_TIMEVNT5          HRTIM_SET2R_TIMEVNT5_Msk                 /*!< Timer event 5 */
+#define HRTIM_SET2R_TIMEVNT6_Pos      (17U)
+#define HRTIM_SET2R_TIMEVNT6_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT6_Pos)      /*!< 0x00020000 */
+#define HRTIM_SET2R_TIMEVNT6          HRTIM_SET2R_TIMEVNT6_Msk                 /*!< Timer event 6 */
+#define HRTIM_SET2R_TIMEVNT7_Pos      (18U)
+#define HRTIM_SET2R_TIMEVNT7_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT7_Pos)      /*!< 0x00040000 */
+#define HRTIM_SET2R_TIMEVNT7          HRTIM_SET2R_TIMEVNT7_Msk                 /*!< Timer event 7 */
+#define HRTIM_SET2R_TIMEVNT8_Pos      (19U)
+#define HRTIM_SET2R_TIMEVNT8_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT8_Pos)      /*!< 0x00080000 */
+#define HRTIM_SET2R_TIMEVNT8          HRTIM_SET2R_TIMEVNT8_Msk                 /*!< Timer event 8 */
+#define HRTIM_SET2R_TIMEVNT9_Pos      (20U)
+#define HRTIM_SET2R_TIMEVNT9_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT9_Pos)      /*!< 0x00100000 */
+#define HRTIM_SET2R_TIMEVNT9          HRTIM_SET2R_TIMEVNT9_Msk                 /*!< Timer event 9 */
+
+#define HRTIM_SET2R_EXTVNT1_Pos       (21U)
+#define HRTIM_SET2R_EXTVNT1_Msk       (0x1UL << HRTIM_SET2R_EXTVNT1_Pos)       /*!< 0x00200000 */
+#define HRTIM_SET2R_EXTVNT1           HRTIM_SET2R_EXTVNT1_Msk                  /*!< External event 1 */
+#define HRTIM_SET2R_EXTVNT2_Pos       (22U)
+#define HRTIM_SET2R_EXTVNT2_Msk       (0x1UL << HRTIM_SET2R_EXTVNT2_Pos)       /*!< 0x00400000 */
+#define HRTIM_SET2R_EXTVNT2           HRTIM_SET2R_EXTVNT2_Msk                  /*!< External event 2 */
+#define HRTIM_SET2R_EXTVNT3_Pos       (23U)
+#define HRTIM_SET2R_EXTVNT3_Msk       (0x1UL << HRTIM_SET2R_EXTVNT3_Pos)       /*!< 0x00800000 */
+#define HRTIM_SET2R_EXTVNT3           HRTIM_SET2R_EXTVNT3_Msk                  /*!< External event 3 */
+#define HRTIM_SET2R_EXTVNT4_Pos       (24U)
+#define HRTIM_SET2R_EXTVNT4_Msk       (0x1UL << HRTIM_SET2R_EXTVNT4_Pos)       /*!< 0x01000000 */
+#define HRTIM_SET2R_EXTVNT4           HRTIM_SET2R_EXTVNT4_Msk                  /*!< External event 4 */
+#define HRTIM_SET2R_EXTVNT5_Pos       (25U)
+#define HRTIM_SET2R_EXTVNT5_Msk       (0x1UL << HRTIM_SET2R_EXTVNT5_Pos)       /*!< 0x02000000 */
+#define HRTIM_SET2R_EXTVNT5           HRTIM_SET2R_EXTVNT5_Msk                  /*!< External event 5 */
+#define HRTIM_SET2R_EXTVNT6_Pos       (26U)
+#define HRTIM_SET2R_EXTVNT6_Msk       (0x1UL << HRTIM_SET2R_EXTVNT6_Pos)       /*!< 0x04000000 */
+#define HRTIM_SET2R_EXTVNT6           HRTIM_SET2R_EXTVNT6_Msk                  /*!< External event 6 */
+#define HRTIM_SET2R_EXTVNT7_Pos       (27U)
+#define HRTIM_SET2R_EXTVNT7_Msk       (0x1UL << HRTIM_SET2R_EXTVNT7_Pos)       /*!< 0x08000000 */
+#define HRTIM_SET2R_EXTVNT7           HRTIM_SET2R_EXTVNT7_Msk                  /*!< External event 7 */
+#define HRTIM_SET2R_EXTVNT8_Pos       (28U)
+#define HRTIM_SET2R_EXTVNT8_Msk       (0x1UL << HRTIM_SET2R_EXTVNT8_Pos)       /*!< 0x10000000 */
+#define HRTIM_SET2R_EXTVNT8           HRTIM_SET2R_EXTVNT8_Msk                  /*!< External event 8 */
+#define HRTIM_SET2R_EXTVNT9_Pos       (29U)
+#define HRTIM_SET2R_EXTVNT9_Msk       (0x1UL << HRTIM_SET2R_EXTVNT9_Pos)       /*!< 0x20000000 */
+#define HRTIM_SET2R_EXTVNT9           HRTIM_SET2R_EXTVNT9_Msk                  /*!< External event 9 */
+#define HRTIM_SET2R_EXTVNT10_Pos      (30U)
+#define HRTIM_SET2R_EXTVNT10_Msk      (0x1UL << HRTIM_SET2R_EXTVNT10_Pos)      /*!< 0x40000000 */
+#define HRTIM_SET2R_EXTVNT10          HRTIM_SET2R_EXTVNT10_Msk                 /*!< External event 10 */
+
+#define HRTIM_SET2R_UPDATE_Pos        (31U)
+#define HRTIM_SET2R_UPDATE_Msk        (0x1UL << HRTIM_SET2R_UPDATE_Pos)        /*!< 0x80000000 */
+#define HRTIM_SET2R_UPDATE            HRTIM_SET2R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */
+
+/**** Bit definition for Slave Output 2 reset register ************************/
+#define HRTIM_RST2R_SRT_Pos           (0U)
+#define HRTIM_RST2R_SRT_Msk           (0x1UL << HRTIM_RST2R_SRT_Pos)           /*!< 0x00000001 */
+#define HRTIM_RST2R_SRT               HRTIM_RST2R_SRT_Msk                      /*!< software reset trigger */
+#define HRTIM_RST2R_RESYNC_Pos        (1U)
+#define HRTIM_RST2R_RESYNC_Msk        (0x1UL << HRTIM_RST2R_RESYNC_Pos)        /*!< 0x00000002 */
+#define HRTIM_RST2R_RESYNC            HRTIM_RST2R_RESYNC_Msk                   /*!< Timer A resynchronization */
+#define HRTIM_RST2R_PER_Pos           (2U)
+#define HRTIM_RST2R_PER_Msk           (0x1UL << HRTIM_RST2R_PER_Pos)           /*!< 0x00000004 */
+#define HRTIM_RST2R_PER               HRTIM_RST2R_PER_Msk                      /*!< Timer A period */
+#define HRTIM_RST2R_CMP1_Pos          (3U)
+#define HRTIM_RST2R_CMP1_Msk          (0x1UL << HRTIM_RST2R_CMP1_Pos)          /*!< 0x00000008 */
+#define HRTIM_RST2R_CMP1              HRTIM_RST2R_CMP1_Msk                     /*!< Timer A compare 1 */
+#define HRTIM_RST2R_CMP2_Pos          (4U)
+#define HRTIM_RST2R_CMP2_Msk          (0x1UL << HRTIM_RST2R_CMP2_Pos)          /*!< 0x00000010 */
+#define HRTIM_RST2R_CMP2              HRTIM_RST2R_CMP2_Msk                     /*!< Timer A compare 2 */
+#define HRTIM_RST2R_CMP3_Pos          (5U)
+#define HRTIM_RST2R_CMP3_Msk          (0x1UL << HRTIM_RST2R_CMP3_Pos)          /*!< 0x00000020 */
+#define HRTIM_RST2R_CMP3              HRTIM_RST2R_CMP3_Msk                     /*!< Timer A compare 3 */
+#define HRTIM_RST2R_CMP4_Pos          (6U)
+#define HRTIM_RST2R_CMP4_Msk          (0x1UL << HRTIM_RST2R_CMP4_Pos)          /*!< 0x00000040 */
+#define HRTIM_RST2R_CMP4              HRTIM_RST2R_CMP4_Msk                     /*!< Timer A compare 4 */
+
+#define HRTIM_RST2R_MSTPER_Pos        (7U)
+#define HRTIM_RST2R_MSTPER_Msk        (0x1UL << HRTIM_RST2R_MSTPER_Pos)        /*!< 0x00000080 */
+#define HRTIM_RST2R_MSTPER            HRTIM_RST2R_MSTPER_Msk                   /*!< Master period */
+#define HRTIM_RST2R_MSTCMP1_Pos       (8U)
+#define HRTIM_RST2R_MSTCMP1_Msk       (0x1UL << HRTIM_RST2R_MSTCMP1_Pos)       /*!< 0x00000100 */
+#define HRTIM_RST2R_MSTCMP1           HRTIM_RST2R_MSTCMP1_Msk                  /*!< Master compare 1 */
+#define HRTIM_RST2R_MSTCMP2_Pos       (9U)
+#define HRTIM_RST2R_MSTCMP2_Msk       (0x1UL << HRTIM_RST2R_MSTCMP2_Pos)       /*!< 0x00000200 */
+#define HRTIM_RST2R_MSTCMP2           HRTIM_RST2R_MSTCMP2_Msk                  /*!< Master compare 2 */
+#define HRTIM_RST2R_MSTCMP3_Pos       (10U)
+#define HRTIM_RST2R_MSTCMP3_Msk       (0x1UL << HRTIM_RST2R_MSTCMP3_Pos)       /*!< 0x00000400 */
+#define HRTIM_RST2R_MSTCMP3           HRTIM_RST2R_MSTCMP3_Msk                  /*!< Master compare 3 */
+#define HRTIM_RST2R_MSTCMP4_Pos       (11U)
+#define HRTIM_RST2R_MSTCMP4_Msk       (0x1UL << HRTIM_RST2R_MSTCMP4_Pos)       /*!< 0x00000800 */
+#define HRTIM_RST2R_MSTCMP4           HRTIM_RST2R_MSTCMP4_Msk                  /*!< Master compare 4 */
+
+#define HRTIM_RST2R_TIMEVNT1_Pos      (12U)
+#define HRTIM_RST2R_TIMEVNT1_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT1_Pos)      /*!< 0x00001000 */
+#define HRTIM_RST2R_TIMEVNT1          HRTIM_RST2R_TIMEVNT1_Msk                 /*!< Timer event 1 */
+#define HRTIM_RST2R_TIMEVNT2_Pos      (13U)
+#define HRTIM_RST2R_TIMEVNT2_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT2_Pos)      /*!< 0x00002000 */
+#define HRTIM_RST2R_TIMEVNT2          HRTIM_RST2R_TIMEVNT2_Msk                 /*!< Timer event 2 */
+#define HRTIM_RST2R_TIMEVNT3_Pos      (14U)
+#define HRTIM_RST2R_TIMEVNT3_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT3_Pos)      /*!< 0x00004000 */
+#define HRTIM_RST2R_TIMEVNT3          HRTIM_RST2R_TIMEVNT3_Msk                 /*!< Timer event 3 */
+#define HRTIM_RST2R_TIMEVNT4_Pos      (15U)
+#define HRTIM_RST2R_TIMEVNT4_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT4_Pos)      /*!< 0x00008000 */
+#define HRTIM_RST2R_TIMEVNT4          HRTIM_RST2R_TIMEVNT4_Msk                 /*!< Timer event 4 */
+#define HRTIM_RST2R_TIMEVNT5_Pos      (16U)
+#define HRTIM_RST2R_TIMEVNT5_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT5_Pos)      /*!< 0x00010000 */
+#define HRTIM_RST2R_TIMEVNT5          HRTIM_RST2R_TIMEVNT5_Msk                 /*!< Timer event 5 */
+#define HRTIM_RST2R_TIMEVNT6_Pos      (17U)
+#define HRTIM_RST2R_TIMEVNT6_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT6_Pos)      /*!< 0x00020000 */
+#define HRTIM_RST2R_TIMEVNT6          HRTIM_RST2R_TIMEVNT6_Msk                 /*!< Timer event 6 */
+#define HRTIM_RST2R_TIMEVNT7_Pos      (18U)
+#define HRTIM_RST2R_TIMEVNT7_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT7_Pos)      /*!< 0x00040000 */
+#define HRTIM_RST2R_TIMEVNT7          HRTIM_RST2R_TIMEVNT7_Msk                 /*!< Timer event 7 */
+#define HRTIM_RST2R_TIMEVNT8_Pos      (19U)
+#define HRTIM_RST2R_TIMEVNT8_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT8_Pos)      /*!< 0x00080000 */
+#define HRTIM_RST2R_TIMEVNT8          HRTIM_RST2R_TIMEVNT8_Msk                 /*!< Timer event 8 */
+#define HRTIM_RST2R_TIMEVNT9_Pos      (20U)
+#define HRTIM_RST2R_TIMEVNT9_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT9_Pos)      /*!< 0x00100000 */
+#define HRTIM_RST2R_TIMEVNT9          HRTIM_RST2R_TIMEVNT9_Msk                 /*!< Timer event 9 */
+
+#define HRTIM_RST2R_EXTVNT1_Pos       (21U)
+#define HRTIM_RST2R_EXTVNT1_Msk       (0x1UL << HRTIM_RST2R_EXTVNT1_Pos)       /*!< 0x00200000 */
+#define HRTIM_RST2R_EXTVNT1           HRTIM_RST2R_EXTVNT1_Msk                  /*!< External event 1 */
+#define HRTIM_RST2R_EXTVNT2_Pos       (22U)
+#define HRTIM_RST2R_EXTVNT2_Msk       (0x1UL << HRTIM_RST2R_EXTVNT2_Pos)       /*!< 0x00400000 */
+#define HRTIM_RST2R_EXTVNT2           HRTIM_RST2R_EXTVNT2_Msk                  /*!< External event 2 */
+#define HRTIM_RST2R_EXTVNT3_Pos       (23U)
+#define HRTIM_RST2R_EXTVNT3_Msk       (0x1UL << HRTIM_RST2R_EXTVNT3_Pos)       /*!< 0x00800000 */
+#define HRTIM_RST2R_EXTVNT3           HRTIM_RST2R_EXTVNT3_Msk                  /*!< External event 3 */
+#define HRTIM_RST2R_EXTVNT4_Pos       (24U)
+#define HRTIM_RST2R_EXTVNT4_Msk       (0x1UL << HRTIM_RST2R_EXTVNT4_Pos)       /*!< 0x01000000 */
+#define HRTIM_RST2R_EXTVNT4           HRTIM_RST2R_EXTVNT4_Msk                  /*!< External event 4 */
+#define HRTIM_RST2R_EXTVNT5_Pos       (25U)
+#define HRTIM_RST2R_EXTVNT5_Msk       (0x1UL << HRTIM_RST2R_EXTVNT5_Pos)       /*!< 0x02000000 */
+#define HRTIM_RST2R_EXTVNT5           HRTIM_RST2R_EXTVNT5_Msk                  /*!< External event 5 */
+#define HRTIM_RST2R_EXTVNT6_Pos       (26U)
+#define HRTIM_RST2R_EXTVNT6_Msk       (0x1UL << HRTIM_RST2R_EXTVNT6_Pos)       /*!< 0x04000000 */
+#define HRTIM_RST2R_EXTVNT6           HRTIM_RST2R_EXTVNT6_Msk                  /*!< External event 6 */
+#define HRTIM_RST2R_EXTVNT7_Pos       (27U)
+#define HRTIM_RST2R_EXTVNT7_Msk       (0x1UL << HRTIM_RST2R_EXTVNT7_Pos)       /*!< 0x08000000 */
+#define HRTIM_RST2R_EXTVNT7           HRTIM_RST2R_EXTVNT7_Msk                  /*!< External event 7 */
+#define HRTIM_RST2R_EXTVNT8_Pos       (28U)
+#define HRTIM_RST2R_EXTVNT8_Msk       (0x1UL << HRTIM_RST2R_EXTVNT8_Pos)       /*!< 0x10000000 */
+#define HRTIM_RST2R_EXTVNT8           HRTIM_RST2R_EXTVNT8_Msk                  /*!< External event 8 */
+#define HRTIM_RST2R_EXTVNT9_Pos       (29U)
+#define HRTIM_RST2R_EXTVNT9_Msk       (0x1UL << HRTIM_RST2R_EXTVNT9_Pos)       /*!< 0x20000000 */
+#define HRTIM_RST2R_EXTVNT9           HRTIM_RST2R_EXTVNT9_Msk                  /*!< External event 9 */
+#define HRTIM_RST2R_EXTVNT10_Pos      (30U)
+#define HRTIM_RST2R_EXTVNT10_Msk      (0x1UL << HRTIM_RST2R_EXTVNT10_Pos)      /*!< 0x40000000 */
+#define HRTIM_RST2R_EXTVNT10          HRTIM_RST2R_EXTVNT10_Msk                 /*!< External event 10 */
+
+#define HRTIM_RST2R_UPDATE_Pos        (31U)
+#define HRTIM_RST2R_UPDATE_Msk        (0x1UL << HRTIM_RST2R_UPDATE_Pos)        /*!< 0x80000000 */
+#define HRTIM_RST2R_UPDATE            HRTIM_RST2R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */
+
+/**** Bit definition for Slave external event filtering  register 1 ***********/
+#define HRTIM_EEFR1_EE1LTCH_Pos       (0U)
+#define HRTIM_EEFR1_EE1LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE1LTCH_Pos)       /*!< 0x00000001 */
+#define HRTIM_EEFR1_EE1LTCH           HRTIM_EEFR1_EE1LTCH_Msk                  /*!< External Event 1 latch */
+#define HRTIM_EEFR1_EE1FLTR_Pos       (1U)
+#define HRTIM_EEFR1_EE1FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE1FLTR_Pos)       /*!< 0x0000001E */
+#define HRTIM_EEFR1_EE1FLTR           HRTIM_EEFR1_EE1FLTR_Msk                  /*!< External Event 1 filter mask */
+#define HRTIM_EEFR1_EE1FLTR_0         (0x1UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000002 */
+#define HRTIM_EEFR1_EE1FLTR_1         (0x2UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000004 */
+#define HRTIM_EEFR1_EE1FLTR_2         (0x4UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000008 */
+#define HRTIM_EEFR1_EE1FLTR_3         (0x8UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000010 */
+
+#define HRTIM_EEFR1_EE2LTCH_Pos       (6U)
+#define HRTIM_EEFR1_EE2LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE2LTCH_Pos)       /*!< 0x00000040 */
+#define HRTIM_EEFR1_EE2LTCH           HRTIM_EEFR1_EE2LTCH_Msk                  /*!< External Event 2 latch */
+#define HRTIM_EEFR1_EE2FLTR_Pos       (7U)
+#define HRTIM_EEFR1_EE2FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE2FLTR_Pos)       /*!< 0x00000780 */
+#define HRTIM_EEFR1_EE2FLTR           HRTIM_EEFR1_EE2FLTR_Msk                  /*!< External Event 2 filter mask */
+#define HRTIM_EEFR1_EE2FLTR_0         (0x1UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000080 */
+#define HRTIM_EEFR1_EE2FLTR_1         (0x2UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000100 */
+#define HRTIM_EEFR1_EE2FLTR_2         (0x4UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000200 */
+#define HRTIM_EEFR1_EE2FLTR_3         (0x8UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000400 */
+
+#define HRTIM_EEFR1_EE3LTCH_Pos       (12U)
+#define HRTIM_EEFR1_EE3LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE3LTCH_Pos)       /*!< 0x00001000 */
+#define HRTIM_EEFR1_EE3LTCH           HRTIM_EEFR1_EE3LTCH_Msk                  /*!< External Event 3 latch */
+#define HRTIM_EEFR1_EE3FLTR_Pos       (13U)
+#define HRTIM_EEFR1_EE3FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE3FLTR_Pos)       /*!< 0x0001E000 */
+#define HRTIM_EEFR1_EE3FLTR           HRTIM_EEFR1_EE3FLTR_Msk                  /*!< External Event 3 filter mask */
+#define HRTIM_EEFR1_EE3FLTR_0         (0x1UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00002000 */
+#define HRTIM_EEFR1_EE3FLTR_1         (0x2UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00004000 */
+#define HRTIM_EEFR1_EE3FLTR_2         (0x4UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00008000 */
+#define HRTIM_EEFR1_EE3FLTR_3         (0x8UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00010000 */
+
+#define HRTIM_EEFR1_EE4LTCH_Pos       (18U)
+#define HRTIM_EEFR1_EE4LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE4LTCH_Pos)       /*!< 0x00040000 */
+#define HRTIM_EEFR1_EE4LTCH           HRTIM_EEFR1_EE4LTCH_Msk                  /*!< External Event 4 latch */
+#define HRTIM_EEFR1_EE4FLTR_Pos       (19U)
+#define HRTIM_EEFR1_EE4FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE4FLTR_Pos)       /*!< 0x00780000 */
+#define HRTIM_EEFR1_EE4FLTR           HRTIM_EEFR1_EE4FLTR_Msk                  /*!< External Event 4 filter mask */
+#define HRTIM_EEFR1_EE4FLTR_0         (0x1UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00080000 */
+#define HRTIM_EEFR1_EE4FLTR_1         (0x2UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00100000 */
+#define HRTIM_EEFR1_EE4FLTR_2         (0x4UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00200000 */
+#define HRTIM_EEFR1_EE4FLTR_3         (0x8UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00400000 */
+
+#define HRTIM_EEFR1_EE5LTCH_Pos       (24U)
+#define HRTIM_EEFR1_EE5LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE5LTCH_Pos)       /*!< 0x01000000 */
+#define HRTIM_EEFR1_EE5LTCH           HRTIM_EEFR1_EE5LTCH_Msk                  /*!< External Event 5 latch */
+#define HRTIM_EEFR1_EE5FLTR_Pos       (25U)
+#define HRTIM_EEFR1_EE5FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE5FLTR_Pos)       /*!< 0x1E000000 */
+#define HRTIM_EEFR1_EE5FLTR           HRTIM_EEFR1_EE5FLTR_Msk                  /*!< External Event 5 filter mask */
+#define HRTIM_EEFR1_EE5FLTR_0         (0x1UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x02000000 */
+#define HRTIM_EEFR1_EE5FLTR_1         (0x2UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x04000000 */
+#define HRTIM_EEFR1_EE5FLTR_2         (0x4UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x08000000 */
+#define HRTIM_EEFR1_EE5FLTR_3         (0x8UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x10000000 */
+
+/**** Bit definition for Slave external event filtering  register 2 ***********/
+#define HRTIM_EEFR2_EE6LTCH_Pos       (0U)
+#define HRTIM_EEFR2_EE6LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE6LTCH_Pos)       /*!< 0x00000001 */
+#define HRTIM_EEFR2_EE6LTCH           HRTIM_EEFR2_EE6LTCH_Msk                  /*!< External Event 6 latch */
+#define HRTIM_EEFR2_EE6FLTR_Pos       (1U)
+#define HRTIM_EEFR2_EE6FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE6FLTR_Pos)       /*!< 0x0000001E */
+#define HRTIM_EEFR2_EE6FLTR           HRTIM_EEFR2_EE6FLTR_Msk                  /*!< External Event 6 filter mask */
+#define HRTIM_EEFR2_EE6FLTR_0         (0x1UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000002 */
+#define HRTIM_EEFR2_EE6FLTR_1         (0x2UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000004 */
+#define HRTIM_EEFR2_EE6FLTR_2         (0x4UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000008 */
+#define HRTIM_EEFR2_EE6FLTR_3         (0x8UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000010 */
+
+#define HRTIM_EEFR2_EE7LTCH_Pos       (6U)
+#define HRTIM_EEFR2_EE7LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE7LTCH_Pos)       /*!< 0x00000040 */
+#define HRTIM_EEFR2_EE7LTCH           HRTIM_EEFR2_EE7LTCH_Msk                  /*!< External Event 7 latch */
+#define HRTIM_EEFR2_EE7FLTR_Pos       (7U)
+#define HRTIM_EEFR2_EE7FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE7FLTR_Pos)       /*!< 0x00000780 */
+#define HRTIM_EEFR2_EE7FLTR           HRTIM_EEFR2_EE7FLTR_Msk                  /*!< External Event 7 filter mask */
+#define HRTIM_EEFR2_EE7FLTR_0         (0x1UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000080 */
+#define HRTIM_EEFR2_EE7FLTR_1         (0x2UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000100 */
+#define HRTIM_EEFR2_EE7FLTR_2         (0x4UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000200 */
+#define HRTIM_EEFR2_EE7FLTR_3         (0x8UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000400 */
+
+#define HRTIM_EEFR2_EE8LTCH_Pos       (12U)
+#define HRTIM_EEFR2_EE8LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE8LTCH_Pos)       /*!< 0x00001000 */
+#define HRTIM_EEFR2_EE8LTCH           HRTIM_EEFR2_EE8LTCH_Msk                  /*!< External Event 8 latch */
+#define HRTIM_EEFR2_EE8FLTR_Pos       (13U)
+#define HRTIM_EEFR2_EE8FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE8FLTR_Pos)       /*!< 0x0001E000 */
+#define HRTIM_EEFR2_EE8FLTR           HRTIM_EEFR2_EE8FLTR_Msk                  /*!< External Event 8 filter mask */
+#define HRTIM_EEFR2_EE8FLTR_0         (0x1UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00002000 */
+#define HRTIM_EEFR2_EE8FLTR_1         (0x2UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00004000 */
+#define HRTIM_EEFR2_EE8FLTR_2         (0x4UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00008000 */
+#define HRTIM_EEFR2_EE8FLTR_3         (0x8UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00010000 */
+
+#define HRTIM_EEFR2_EE9LTCH_Pos       (18U)
+#define HRTIM_EEFR2_EE9LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE9LTCH_Pos)       /*!< 0x00040000 */
+#define HRTIM_EEFR2_EE9LTCH           HRTIM_EEFR2_EE9LTCH_Msk                  /*!< External Event 9 latch */
+#define HRTIM_EEFR2_EE9FLTR_Pos       (19U)
+#define HRTIM_EEFR2_EE9FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE9FLTR_Pos)       /*!< 0x00780000 */
+#define HRTIM_EEFR2_EE9FLTR           HRTIM_EEFR2_EE9FLTR_Msk                  /*!< External Event 9 filter mask */
+#define HRTIM_EEFR2_EE9FLTR_0         (0x1UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00080000 */
+#define HRTIM_EEFR2_EE9FLTR_1         (0x2UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00100000 */
+#define HRTIM_EEFR2_EE9FLTR_2         (0x4UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00200000 */
+#define HRTIM_EEFR2_EE9FLTR_3         (0x8UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00400000 */
+
+#define HRTIM_EEFR2_EE10LTCH_Pos      (24U)
+#define HRTIM_EEFR2_EE10LTCH_Msk      (0x1UL << HRTIM_EEFR2_EE10LTCH_Pos)      /*!< 0x01000000 */
+#define HRTIM_EEFR2_EE10LTCH          HRTIM_EEFR2_EE10LTCH_Msk                 /*!< External Event 10 latch */
+#define HRTIM_EEFR2_EE10FLTR_Pos      (25U)
+#define HRTIM_EEFR2_EE10FLTR_Msk      (0xFUL << HRTIM_EEFR2_EE10FLTR_Pos)      /*!< 0x1E000000 */
+#define HRTIM_EEFR2_EE10FLTR          HRTIM_EEFR2_EE10FLTR_Msk                 /*!< External Event 10 filter mask */
+#define HRTIM_EEFR2_EE10FLTR_0        (0x1UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x02000000 */
+#define HRTIM_EEFR2_EE10FLTR_1        (0x2UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x04000000 */
+#define HRTIM_EEFR2_EE10FLTR_2        (0x4UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x08000000 */
+#define HRTIM_EEFR2_EE10FLTR_3        (0x8UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x10000000 */
+
+/**** Bit definition for Slave Timer reset register ***************************/
+#define HRTIM_RSTR_UPDATE_Pos         (1U)
+#define HRTIM_RSTR_UPDATE_Msk         (0x1UL << HRTIM_RSTR_UPDATE_Pos)         /*!< 0x00000002 */
+#define HRTIM_RSTR_UPDATE             HRTIM_RSTR_UPDATE_Msk                    /*!< Timer update */
+#define HRTIM_RSTR_CMP2_Pos           (2U)
+#define HRTIM_RSTR_CMP2_Msk           (0x1UL << HRTIM_RSTR_CMP2_Pos)           /*!< 0x00000004 */
+#define HRTIM_RSTR_CMP2               HRTIM_RSTR_CMP2_Msk                      /*!< Timer compare2 */
+#define HRTIM_RSTR_CMP4_Pos           (3U)
+#define HRTIM_RSTR_CMP4_Msk           (0x1UL << HRTIM_RSTR_CMP4_Pos)           /*!< 0x00000008 */
+#define HRTIM_RSTR_CMP4               HRTIM_RSTR_CMP4_Msk                      /*!< Timer compare4 */
+
+#define HRTIM_RSTR_MSTPER_Pos         (4U)
+#define HRTIM_RSTR_MSTPER_Msk         (0x1UL << HRTIM_RSTR_MSTPER_Pos)         /*!< 0x00000010 */
+#define HRTIM_RSTR_MSTPER             HRTIM_RSTR_MSTPER_Msk                    /*!< Master period */
+#define HRTIM_RSTR_MSTCMP1_Pos        (5U)
+#define HRTIM_RSTR_MSTCMP1_Msk        (0x1UL << HRTIM_RSTR_MSTCMP1_Pos)        /*!< 0x00000020 */
+#define HRTIM_RSTR_MSTCMP1            HRTIM_RSTR_MSTCMP1_Msk                   /*!< Master compare1 */
+#define HRTIM_RSTR_MSTCMP2_Pos        (6U)
+#define HRTIM_RSTR_MSTCMP2_Msk        (0x1UL << HRTIM_RSTR_MSTCMP2_Pos)        /*!< 0x00000040 */
+#define HRTIM_RSTR_MSTCMP2            HRTIM_RSTR_MSTCMP2_Msk                   /*!< Master compare2 */
+#define HRTIM_RSTR_MSTCMP3_Pos        (7U)
+#define HRTIM_RSTR_MSTCMP3_Msk        (0x1UL << HRTIM_RSTR_MSTCMP3_Pos)        /*!< 0x00000080 */
+#define HRTIM_RSTR_MSTCMP3            HRTIM_RSTR_MSTCMP3_Msk                   /*!< Master compare3 */
+#define HRTIM_RSTR_MSTCMP4_Pos        (8U)
+#define HRTIM_RSTR_MSTCMP4_Msk        (0x1UL << HRTIM_RSTR_MSTCMP4_Pos)        /*!< 0x00000100 */
+#define HRTIM_RSTR_MSTCMP4            HRTIM_RSTR_MSTCMP4_Msk                   /*!< Master compare4 */
+
+#define HRTIM_RSTR_EXTEVNT1_Pos       (9U)
+#define HRTIM_RSTR_EXTEVNT1_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT1_Pos)       /*!< 0x00000200 */
+#define HRTIM_RSTR_EXTEVNT1           HRTIM_RSTR_EXTEVNT1_Msk                  /*!< External event 1 */
+#define HRTIM_RSTR_EXTEVNT2_Pos       (10U)
+#define HRTIM_RSTR_EXTEVNT2_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT2_Pos)       /*!< 0x00000400 */
+#define HRTIM_RSTR_EXTEVNT2           HRTIM_RSTR_EXTEVNT2_Msk                  /*!< External event 2 */
+#define HRTIM_RSTR_EXTEVNT3_Pos       (11U)
+#define HRTIM_RSTR_EXTEVNT3_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT3_Pos)       /*!< 0x00000800 */
+#define HRTIM_RSTR_EXTEVNT3           HRTIM_RSTR_EXTEVNT3_Msk                  /*!< External event 3 */
+#define HRTIM_RSTR_EXTEVNT4_Pos       (12U)
+#define HRTIM_RSTR_EXTEVNT4_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT4_Pos)       /*!< 0x00001000 */
+#define HRTIM_RSTR_EXTEVNT4           HRTIM_RSTR_EXTEVNT4_Msk                  /*!< External event 4 */
+#define HRTIM_RSTR_EXTEVNT5_Pos       (13U)
+#define HRTIM_RSTR_EXTEVNT5_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT5_Pos)       /*!< 0x00002000 */
+#define HRTIM_RSTR_EXTEVNT5           HRTIM_RSTR_EXTEVNT5_Msk                  /*!< External event 5 */
+#define HRTIM_RSTR_EXTEVNT6_Pos       (14U)
+#define HRTIM_RSTR_EXTEVNT6_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT6_Pos)       /*!< 0x00004000 */
+#define HRTIM_RSTR_EXTEVNT6           HRTIM_RSTR_EXTEVNT6_Msk                  /*!< External event 6 */
+#define HRTIM_RSTR_EXTEVNT7_Pos       (15U)
+#define HRTIM_RSTR_EXTEVNT7_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT7_Pos)       /*!< 0x00008000 */
+#define HRTIM_RSTR_EXTEVNT7           HRTIM_RSTR_EXTEVNT7_Msk                  /*!< External event 7 */
+#define HRTIM_RSTR_EXTEVNT8_Pos       (16U)
+#define HRTIM_RSTR_EXTEVNT8_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT8_Pos)       /*!< 0x00010000 */
+#define HRTIM_RSTR_EXTEVNT8           HRTIM_RSTR_EXTEVNT8_Msk                  /*!< External event 8 */
+#define HRTIM_RSTR_EXTEVNT9_Pos       (17U)
+#define HRTIM_RSTR_EXTEVNT9_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT9_Pos)       /*!< 0x00020000 */
+#define HRTIM_RSTR_EXTEVNT9           HRTIM_RSTR_EXTEVNT9_Msk                  /*!< External event 9 */
+#define HRTIM_RSTR_EXTEVNT10_Pos      (18U)
+#define HRTIM_RSTR_EXTEVNT10_Msk      (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos)      /*!< 0x00040000 */
+#define HRTIM_RSTR_EXTEVNT10          HRTIM_RSTR_EXTEVNT10_Msk                 /*!< External event 10 */
+
+#define HRTIM_RSTR_TIMBCMP1_Pos       (19U)
+#define HRTIM_RSTR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos)       /*!< 0x00080000 */
+#define HRTIM_RSTR_TIMBCMP1           HRTIM_RSTR_TIMBCMP1_Msk                  /*!< Timer B compare 1 */
+#define HRTIM_RSTR_TIMBCMP2_Pos       (20U)
+#define HRTIM_RSTR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP2_Pos)       /*!< 0x00100000 */
+#define HRTIM_RSTR_TIMBCMP2           HRTIM_RSTR_TIMBCMP2_Msk                  /*!< Timer B compare 2 */
+#define HRTIM_RSTR_TIMBCMP4_Pos       (21U)
+#define HRTIM_RSTR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP4_Pos)       /*!< 0x00200000 */
+#define HRTIM_RSTR_TIMBCMP4           HRTIM_RSTR_TIMBCMP4_Msk                  /*!< Timer B compare 4 */
+
+#define HRTIM_RSTR_TIMCCMP1_Pos       (22U)
+#define HRTIM_RSTR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP1_Pos)       /*!< 0x00400000 */
+#define HRTIM_RSTR_TIMCCMP1           HRTIM_RSTR_TIMCCMP1_Msk                  /*!< Timer C compare 1 */
+#define HRTIM_RSTR_TIMCCMP2_Pos       (23U)
+#define HRTIM_RSTR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP2_Pos)       /*!< 0x00800000 */
+#define HRTIM_RSTR_TIMCCMP2           HRTIM_RSTR_TIMCCMP2_Msk                  /*!< Timer C compare 2 */
+#define HRTIM_RSTR_TIMCCMP4_Pos       (24U)
+#define HRTIM_RSTR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP4_Pos)       /*!< 0x01000000 */
+#define HRTIM_RSTR_TIMCCMP4           HRTIM_RSTR_TIMCCMP4_Msk                  /*!< Timer C compare 4 */
+
+#define HRTIM_RSTR_TIMDCMP1_Pos       (25U)
+#define HRTIM_RSTR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP1_Pos)       /*!< 0x02000000 */
+#define HRTIM_RSTR_TIMDCMP1           HRTIM_RSTR_TIMDCMP1_Msk                  /*!< Timer D compare 1 */
+#define HRTIM_RSTR_TIMDCMP2_Pos       (26U)
+#define HRTIM_RSTR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP2_Pos)       /*!< 0x04000000 */
+#define HRTIM_RSTR_TIMDCMP2           HRTIM_RSTR_TIMDCMP2_Msk                  /*!< Timer D compare 2 */
+#define HRTIM_RSTR_TIMDCMP4_Pos       (27U)
+#define HRTIM_RSTR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP4_Pos)       /*!< 0x08000000 */
+#define HRTIM_RSTR_TIMDCMP4           HRTIM_RSTR_TIMDCMP4_Msk                  /*!< Timer D compare 4 */
+
+#define HRTIM_RSTR_TIMECMP1_Pos       (28U)
+#define HRTIM_RSTR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTR_TIMECMP1_Pos)       /*!< 0x10000000 */
+#define HRTIM_RSTR_TIMECMP1           HRTIM_RSTR_TIMECMP1_Msk                  /*!< Timer E compare 1 */
+#define HRTIM_RSTR_TIMECMP2_Pos       (29U)
+#define HRTIM_RSTR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTR_TIMECMP2_Pos)       /*!< 0x20000000 */
+#define HRTIM_RSTR_TIMECMP2           HRTIM_RSTR_TIMECMP2_Msk                  /*!< Timer E compare 2 */
+#define HRTIM_RSTR_TIMECMP4_Pos       (30U)
+#define HRTIM_RSTR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTR_TIMECMP4_Pos)       /*!< 0x40000000 */
+#define HRTIM_RSTR_TIMECMP4           HRTIM_RSTR_TIMECMP4_Msk                  /*!< Timer E compare 4 */
+
+/**** Bit definition for Slave Timer Chopper register *************************/
+#define HRTIM_CHPR_CARFRQ_Pos         (0U)
+#define HRTIM_CHPR_CARFRQ_Msk         (0xFUL << HRTIM_CHPR_CARFRQ_Pos)         /*!< 0x0000000F */
+#define HRTIM_CHPR_CARFRQ             HRTIM_CHPR_CARFRQ_Msk                    /*!< Timer carrier frequency value */
+#define HRTIM_CHPR_CARFRQ_0           (0x1UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000001 */
+#define HRTIM_CHPR_CARFRQ_1           (0x2UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000002 */
+#define HRTIM_CHPR_CARFRQ_2           (0x4UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000004 */
+#define HRTIM_CHPR_CARFRQ_3           (0x8UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000008 */
+
+#define HRTIM_CHPR_CARDTY_Pos         (4U)
+#define HRTIM_CHPR_CARDTY_Msk         (0x7UL << HRTIM_CHPR_CARDTY_Pos)         /*!< 0x00000070 */
+#define HRTIM_CHPR_CARDTY             HRTIM_CHPR_CARDTY_Msk                    /*!< Timer chopper duty cycle value */
+#define HRTIM_CHPR_CARDTY_0           (0x1UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000010 */
+#define HRTIM_CHPR_CARDTY_1           (0x2UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000020 */
+#define HRTIM_CHPR_CARDTY_2           (0x4UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000040 */
+
+#define HRTIM_CHPR_STRPW_Pos          (7U)
+#define HRTIM_CHPR_STRPW_Msk          (0xFUL << HRTIM_CHPR_STRPW_Pos)          /*!< 0x00000780 */
+#define HRTIM_CHPR_STRPW              HRTIM_CHPR_STRPW_Msk                     /*!< Timer start pulse width value */
+#define HRTIM_CHPR_STRPW_0            (0x1UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000080 */
+#define HRTIM_CHPR_STRPW_1            (0x2UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000100 */
+#define HRTIM_CHPR_STRPW_2            (0x4UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000200 */
+#define HRTIM_CHPR_STRPW_3            (0x8UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000400 */
+
+/**** Bit definition for Slave Timer Capture 1 control register ***************/
+#define HRTIM_CPT1CR_SWCPT_Pos        (0U)
+#define HRTIM_CPT1CR_SWCPT_Msk        (0x1UL << HRTIM_CPT1CR_SWCPT_Pos)        /*!< 0x00000001 */
+#define HRTIM_CPT1CR_SWCPT            HRTIM_CPT1CR_SWCPT_Msk                   /*!< Software capture */
+#define HRTIM_CPT1CR_UPDCPT_Pos       (1U)
+#define HRTIM_CPT1CR_UPDCPT_Msk       (0x1UL << HRTIM_CPT1CR_UPDCPT_Pos)       /*!< 0x00000002 */
+#define HRTIM_CPT1CR_UPDCPT           HRTIM_CPT1CR_UPDCPT_Msk                  /*!< Update capture */
+#define HRTIM_CPT1CR_EXEV1CPT_Pos     (2U)
+#define HRTIM_CPT1CR_EXEV1CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV1CPT_Pos)     /*!< 0x00000004 */
+#define HRTIM_CPT1CR_EXEV1CPT         HRTIM_CPT1CR_EXEV1CPT_Msk                /*!< External event 1 capture */
+#define HRTIM_CPT1CR_EXEV2CPT_Pos     (3U)
+#define HRTIM_CPT1CR_EXEV2CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV2CPT_Pos)     /*!< 0x00000008 */
+#define HRTIM_CPT1CR_EXEV2CPT         HRTIM_CPT1CR_EXEV2CPT_Msk                /*!< External event 2 capture */
+#define HRTIM_CPT1CR_EXEV3CPT_Pos     (4U)
+#define HRTIM_CPT1CR_EXEV3CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV3CPT_Pos)     /*!< 0x00000010 */
+#define HRTIM_CPT1CR_EXEV3CPT         HRTIM_CPT1CR_EXEV3CPT_Msk                /*!< External event 3 capture */
+#define HRTIM_CPT1CR_EXEV4CPT_Pos     (5U)
+#define HRTIM_CPT1CR_EXEV4CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV4CPT_Pos)     /*!< 0x00000020 */
+#define HRTIM_CPT1CR_EXEV4CPT         HRTIM_CPT1CR_EXEV4CPT_Msk                /*!< External event 4 capture */
+#define HRTIM_CPT1CR_EXEV5CPT_Pos     (6U)
+#define HRTIM_CPT1CR_EXEV5CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV5CPT_Pos)     /*!< 0x00000040 */
+#define HRTIM_CPT1CR_EXEV5CPT         HRTIM_CPT1CR_EXEV5CPT_Msk                /*!< External event 5 capture */
+#define HRTIM_CPT1CR_EXEV6CPT_Pos     (7U)
+#define HRTIM_CPT1CR_EXEV6CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV6CPT_Pos)     /*!< 0x00000080 */
+#define HRTIM_CPT1CR_EXEV6CPT         HRTIM_CPT1CR_EXEV6CPT_Msk                /*!< External event 6 capture */
+#define HRTIM_CPT1CR_EXEV7CPT_Pos     (8U)
+#define HRTIM_CPT1CR_EXEV7CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV7CPT_Pos)     /*!< 0x00000100 */
+#define HRTIM_CPT1CR_EXEV7CPT         HRTIM_CPT1CR_EXEV7CPT_Msk                /*!< External event 7 capture */
+#define HRTIM_CPT1CR_EXEV8CPT_Pos     (9U)
+#define HRTIM_CPT1CR_EXEV8CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV8CPT_Pos)     /*!< 0x00000200 */
+#define HRTIM_CPT1CR_EXEV8CPT         HRTIM_CPT1CR_EXEV8CPT_Msk                /*!< External event 8 capture */
+#define HRTIM_CPT1CR_EXEV9CPT_Pos     (10U)
+#define HRTIM_CPT1CR_EXEV9CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV9CPT_Pos)     /*!< 0x00000400 */
+#define HRTIM_CPT1CR_EXEV9CPT         HRTIM_CPT1CR_EXEV9CPT_Msk                /*!< External event 9 capture */
+#define HRTIM_CPT1CR_EXEV10CPT_Pos    (11U)
+#define HRTIM_CPT1CR_EXEV10CPT_Msk    (0x1UL << HRTIM_CPT1CR_EXEV10CPT_Pos)    /*!< 0x00000800 */
+#define HRTIM_CPT1CR_EXEV10CPT        HRTIM_CPT1CR_EXEV10CPT_Msk               /*!< External event 10 capture */
+
+#define HRTIM_CPT1CR_TA1SET_Pos       (12U)
+#define HRTIM_CPT1CR_TA1SET_Msk       (0x1UL << HRTIM_CPT1CR_TA1SET_Pos)       /*!< 0x00001000 */
+#define HRTIM_CPT1CR_TA1SET           HRTIM_CPT1CR_TA1SET_Msk                  /*!< Timer A output 1 set */
+#define HRTIM_CPT1CR_TA1RST_Pos       (13U)
+#define HRTIM_CPT1CR_TA1RST_Msk       (0x1UL << HRTIM_CPT1CR_TA1RST_Pos)       /*!< 0x00002000 */
+#define HRTIM_CPT1CR_TA1RST           HRTIM_CPT1CR_TA1RST_Msk                  /*!< Timer A output 1 reset */
+#define HRTIM_CPT1CR_TIMACMP1_Pos     (14U)
+#define HRTIM_CPT1CR_TIMACMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMACMP1_Pos)     /*!< 0x00004000 */
+#define HRTIM_CPT1CR_TIMACMP1         HRTIM_CPT1CR_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_CPT1CR_TIMACMP2_Pos     (15U)
+#define HRTIM_CPT1CR_TIMACMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMACMP2_Pos)     /*!< 0x00008000 */
+#define HRTIM_CPT1CR_TIMACMP2         HRTIM_CPT1CR_TIMACMP2_Msk                /*!< Timer A compare 2 */
+
+#define HRTIM_CPT1CR_TB1SET_Pos       (16U)
+#define HRTIM_CPT1CR_TB1SET_Msk       (0x1UL << HRTIM_CPT1CR_TB1SET_Pos)       /*!< 0x00010000 */
+#define HRTIM_CPT1CR_TB1SET           HRTIM_CPT1CR_TB1SET_Msk                  /*!< Timer B output 1 set */
+#define HRTIM_CPT1CR_TB1RST_Pos       (17U)
+#define HRTIM_CPT1CR_TB1RST_Msk       (0x1UL << HRTIM_CPT1CR_TB1RST_Pos)       /*!< 0x00020000 */
+#define HRTIM_CPT1CR_TB1RST           HRTIM_CPT1CR_TB1RST_Msk                  /*!< Timer B output 1 reset */
+#define HRTIM_CPT1CR_TIMBCMP1_Pos     (18U)
+#define HRTIM_CPT1CR_TIMBCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMBCMP1_Pos)     /*!< 0x00040000 */
+#define HRTIM_CPT1CR_TIMBCMP1         HRTIM_CPT1CR_TIMBCMP1_Msk                /*!< Timer B compare 1 */
+#define HRTIM_CPT1CR_TIMBCMP2_Pos     (19U)
+#define HRTIM_CPT1CR_TIMBCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMBCMP2_Pos)     /*!< 0x00080000 */
+#define HRTIM_CPT1CR_TIMBCMP2         HRTIM_CPT1CR_TIMBCMP2_Msk                /*!< Timer B compare 2 */
+
+#define HRTIM_CPT1CR_TC1SET_Pos       (20U)
+#define HRTIM_CPT1CR_TC1SET_Msk       (0x1UL << HRTIM_CPT1CR_TC1SET_Pos)       /*!< 0x00100000 */
+#define HRTIM_CPT1CR_TC1SET           HRTIM_CPT1CR_TC1SET_Msk                  /*!< Timer C output 1 set */
+#define HRTIM_CPT1CR_TC1RST_Pos       (21U)
+#define HRTIM_CPT1CR_TC1RST_Msk       (0x1UL << HRTIM_CPT1CR_TC1RST_Pos)       /*!< 0x00200000 */
+#define HRTIM_CPT1CR_TC1RST           HRTIM_CPT1CR_TC1RST_Msk                  /*!< Timer C output 1 reset */
+#define HRTIM_CPT1CR_TIMCCMP1_Pos     (22U)
+#define HRTIM_CPT1CR_TIMCCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMCCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_CPT1CR_TIMCCMP1         HRTIM_CPT1CR_TIMCCMP1_Msk                /*!< Timer C compare 1 */
+#define HRTIM_CPT1CR_TIMCCMP2_Pos     (23U)
+#define HRTIM_CPT1CR_TIMCCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMCCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_CPT1CR_TIMCCMP2         HRTIM_CPT1CR_TIMCCMP2_Msk                /*!< Timer C compare 2 */
+
+#define HRTIM_CPT1CR_TD1SET_Pos       (24U)
+#define HRTIM_CPT1CR_TD1SET_Msk       (0x1UL << HRTIM_CPT1CR_TD1SET_Pos)       /*!< 0x01000000 */
+#define HRTIM_CPT1CR_TD1SET           HRTIM_CPT1CR_TD1SET_Msk                  /*!< Timer D output 1 set */
+#define HRTIM_CPT1CR_TD1RST_Pos       (25U)
+#define HRTIM_CPT1CR_TD1RST_Msk       (0x1UL << HRTIM_CPT1CR_TD1RST_Pos)       /*!< 0x02000000 */
+#define HRTIM_CPT1CR_TD1RST           HRTIM_CPT1CR_TD1RST_Msk                  /*!< Timer D output 1 reset */
+#define HRTIM_CPT1CR_TIMDCMP1_Pos     (26U)
+#define HRTIM_CPT1CR_TIMDCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMDCMP1_Pos)     /*!< 0x04000000 */
+#define HRTIM_CPT1CR_TIMDCMP1         HRTIM_CPT1CR_TIMDCMP1_Msk                /*!< Timer D compare 1 */
+#define HRTIM_CPT1CR_TIMDCMP2_Pos     (27U)
+#define HRTIM_CPT1CR_TIMDCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMDCMP2_Pos)     /*!< 0x08000000 */
+#define HRTIM_CPT1CR_TIMDCMP2         HRTIM_CPT1CR_TIMDCMP2_Msk                /*!< Timer D compare 2 */
+
+#define HRTIM_CPT1CR_TE1SET_Pos       (28U)
+#define HRTIM_CPT1CR_TE1SET_Msk       (0x1UL << HRTIM_CPT1CR_TE1SET_Pos)       /*!< 0x10000000 */
+#define HRTIM_CPT1CR_TE1SET           HRTIM_CPT1CR_TE1SET_Msk                  /*!< Timer E output 1 set */
+#define HRTIM_CPT1CR_TE1RST_Pos       (29U)
+#define HRTIM_CPT1CR_TE1RST_Msk       (0x1UL << HRTIM_CPT1CR_TE1RST_Pos)       /*!< 0x20000000 */
+#define HRTIM_CPT1CR_TE1RST           HRTIM_CPT1CR_TE1RST_Msk                  /*!< Timer E output 1 reset */
+#define HRTIM_CPT1CR_TIMECMP1_Pos     (30U)
+#define HRTIM_CPT1CR_TIMECMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMECMP1_Pos)     /*!< 0x40000000 */
+#define HRTIM_CPT1CR_TIMECMP1         HRTIM_CPT1CR_TIMECMP1_Msk                /*!< Timer E compare 1 */
+#define HRTIM_CPT1CR_TIMECMP2_Pos     (31U)
+#define HRTIM_CPT1CR_TIMECMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMECMP2_Pos)     /*!< 0x80000000 */
+#define HRTIM_CPT1CR_TIMECMP2         HRTIM_CPT1CR_TIMECMP2_Msk                /*!< Timer E compare 2 */
+
+/**** Bit definition for Slave Timer Capture 2 control register ***************/
+#define HRTIM_CPT2CR_SWCPT_Pos        (0U)
+#define HRTIM_CPT2CR_SWCPT_Msk        (0x1UL << HRTIM_CPT2CR_SWCPT_Pos)        /*!< 0x00000001 */
+#define HRTIM_CPT2CR_SWCPT            HRTIM_CPT2CR_SWCPT_Msk                   /*!< Software capture */
+#define HRTIM_CPT2CR_UPDCPT_Pos       (1U)
+#define HRTIM_CPT2CR_UPDCPT_Msk       (0x1UL << HRTIM_CPT2CR_UPDCPT_Pos)       /*!< 0x00000002 */
+#define HRTIM_CPT2CR_UPDCPT           HRTIM_CPT2CR_UPDCPT_Msk                  /*!< Update capture */
+#define HRTIM_CPT2CR_EXEV1CPT_Pos     (2U)
+#define HRTIM_CPT2CR_EXEV1CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV1CPT_Pos)     /*!< 0x00000004 */
+#define HRTIM_CPT2CR_EXEV1CPT         HRTIM_CPT2CR_EXEV1CPT_Msk                /*!< External event 1 capture */
+#define HRTIM_CPT2CR_EXEV2CPT_Pos     (3U)
+#define HRTIM_CPT2CR_EXEV2CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV2CPT_Pos)     /*!< 0x00000008 */
+#define HRTIM_CPT2CR_EXEV2CPT         HRTIM_CPT2CR_EXEV2CPT_Msk                /*!< External event 2 capture */
+#define HRTIM_CPT2CR_EXEV3CPT_Pos     (4U)
+#define HRTIM_CPT2CR_EXEV3CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV3CPT_Pos)     /*!< 0x00000010 */
+#define HRTIM_CPT2CR_EXEV3CPT         HRTIM_CPT2CR_EXEV3CPT_Msk                /*!< External event 3 capture */
+#define HRTIM_CPT2CR_EXEV4CPT_Pos     (5U)
+#define HRTIM_CPT2CR_EXEV4CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV4CPT_Pos)     /*!< 0x00000020 */
+#define HRTIM_CPT2CR_EXEV4CPT         HRTIM_CPT2CR_EXEV4CPT_Msk                /*!< External event 4 capture */
+#define HRTIM_CPT2CR_EXEV5CPT_Pos     (6U)
+#define HRTIM_CPT2CR_EXEV5CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV5CPT_Pos)     /*!< 0x00000040 */
+#define HRTIM_CPT2CR_EXEV5CPT         HRTIM_CPT2CR_EXEV5CPT_Msk                /*!< External event 5 capture */
+#define HRTIM_CPT2CR_EXEV6CPT_Pos     (7U)
+#define HRTIM_CPT2CR_EXEV6CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV6CPT_Pos)     /*!< 0x00000080 */
+#define HRTIM_CPT2CR_EXEV6CPT         HRTIM_CPT2CR_EXEV6CPT_Msk                /*!< External event 6 capture */
+#define HRTIM_CPT2CR_EXEV7CPT_Pos     (8U)
+#define HRTIM_CPT2CR_EXEV7CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV7CPT_Pos)     /*!< 0x00000100 */
+#define HRTIM_CPT2CR_EXEV7CPT         HRTIM_CPT2CR_EXEV7CPT_Msk                /*!< External event 7 capture */
+#define HRTIM_CPT2CR_EXEV8CPT_Pos     (9U)
+#define HRTIM_CPT2CR_EXEV8CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV8CPT_Pos)     /*!< 0x00000200 */
+#define HRTIM_CPT2CR_EXEV8CPT         HRTIM_CPT2CR_EXEV8CPT_Msk                /*!< External event 8 capture */
+#define HRTIM_CPT2CR_EXEV9CPT_Pos     (10U)
+#define HRTIM_CPT2CR_EXEV9CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV9CPT_Pos)     /*!< 0x00000400 */
+#define HRTIM_CPT2CR_EXEV9CPT         HRTIM_CPT2CR_EXEV9CPT_Msk                /*!< External event 9 capture */
+#define HRTIM_CPT2CR_EXEV10CPT_Pos    (11U)
+#define HRTIM_CPT2CR_EXEV10CPT_Msk    (0x1UL << HRTIM_CPT2CR_EXEV10CPT_Pos)    /*!< 0x00000800 */
+#define HRTIM_CPT2CR_EXEV10CPT        HRTIM_CPT2CR_EXEV10CPT_Msk               /*!< External event 10 capture */
+
+#define HRTIM_CPT2CR_TA1SET_Pos       (12U)
+#define HRTIM_CPT2CR_TA1SET_Msk       (0x1UL << HRTIM_CPT2CR_TA1SET_Pos)       /*!< 0x00001000 */
+#define HRTIM_CPT2CR_TA1SET           HRTIM_CPT2CR_TA1SET_Msk                  /*!< Timer A output 1 set */
+#define HRTIM_CPT2CR_TA1RST_Pos       (13U)
+#define HRTIM_CPT2CR_TA1RST_Msk       (0x1UL << HRTIM_CPT2CR_TA1RST_Pos)       /*!< 0x00002000 */
+#define HRTIM_CPT2CR_TA1RST           HRTIM_CPT2CR_TA1RST_Msk                  /*!< Timer A output 1 reset */
+#define HRTIM_CPT2CR_TIMACMP1_Pos     (14U)
+#define HRTIM_CPT2CR_TIMACMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMACMP1_Pos)     /*!< 0x00004000 */
+#define HRTIM_CPT2CR_TIMACMP1         HRTIM_CPT2CR_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_CPT2CR_TIMACMP2_Pos     (15U)
+#define HRTIM_CPT2CR_TIMACMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMACMP2_Pos)     /*!< 0x00008000 */
+#define HRTIM_CPT2CR_TIMACMP2         HRTIM_CPT2CR_TIMACMP2_Msk                /*!< Timer A compare 2 */
+
+#define HRTIM_CPT2CR_TB1SET_Pos       (16U)
+#define HRTIM_CPT2CR_TB1SET_Msk       (0x1UL << HRTIM_CPT2CR_TB1SET_Pos)       /*!< 0x00010000 */
+#define HRTIM_CPT2CR_TB1SET           HRTIM_CPT2CR_TB1SET_Msk                  /*!< Timer B output 1 set */
+#define HRTIM_CPT2CR_TB1RST_Pos       (17U)
+#define HRTIM_CPT2CR_TB1RST_Msk       (0x1UL << HRTIM_CPT2CR_TB1RST_Pos)       /*!< 0x00020000 */
+#define HRTIM_CPT2CR_TB1RST           HRTIM_CPT2CR_TB1RST_Msk                  /*!< Timer B output 1 reset */
+#define HRTIM_CPT2CR_TIMBCMP1_Pos     (18U)
+#define HRTIM_CPT2CR_TIMBCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMBCMP1_Pos)     /*!< 0x00040000 */
+#define HRTIM_CPT2CR_TIMBCMP1         HRTIM_CPT2CR_TIMBCMP1_Msk                /*!< Timer B compare 1 */
+#define HRTIM_CPT2CR_TIMBCMP2_Pos     (19U)
+#define HRTIM_CPT2CR_TIMBCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMBCMP2_Pos)     /*!< 0x00080000 */
+#define HRTIM_CPT2CR_TIMBCMP2         HRTIM_CPT2CR_TIMBCMP2_Msk                /*!< Timer B compare 2 */
+
+#define HRTIM_CPT2CR_TC1SET_Pos       (20U)
+#define HRTIM_CPT2CR_TC1SET_Msk       (0x1UL << HRTIM_CPT2CR_TC1SET_Pos)       /*!< 0x00100000 */
+#define HRTIM_CPT2CR_TC1SET           HRTIM_CPT2CR_TC1SET_Msk                  /*!< Timer C output 1 set */
+#define HRTIM_CPT2CR_TC1RST_Pos       (21U)
+#define HRTIM_CPT2CR_TC1RST_Msk       (0x1UL << HRTIM_CPT2CR_TC1RST_Pos)       /*!< 0x00200000 */
+#define HRTIM_CPT2CR_TC1RST           HRTIM_CPT2CR_TC1RST_Msk                  /*!< Timer C output 1 reset */
+#define HRTIM_CPT2CR_TIMCCMP1_Pos     (22U)
+#define HRTIM_CPT2CR_TIMCCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMCCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_CPT2CR_TIMCCMP1         HRTIM_CPT2CR_TIMCCMP1_Msk                /*!< Timer C compare 1 */
+#define HRTIM_CPT2CR_TIMCCMP2_Pos     (23U)
+#define HRTIM_CPT2CR_TIMCCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMCCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_CPT2CR_TIMCCMP2         HRTIM_CPT2CR_TIMCCMP2_Msk                /*!< Timer C compare 2 */
+
+#define HRTIM_CPT2CR_TD1SET_Pos       (24U)
+#define HRTIM_CPT2CR_TD1SET_Msk       (0x1UL << HRTIM_CPT2CR_TD1SET_Pos)       /*!< 0x01000000 */
+#define HRTIM_CPT2CR_TD1SET           HRTIM_CPT2CR_TD1SET_Msk                  /*!< Timer D output 1 set */
+#define HRTIM_CPT2CR_TD1RST_Pos       (25U)
+#define HRTIM_CPT2CR_TD1RST_Msk       (0x1UL << HRTIM_CPT2CR_TD1RST_Pos)       /*!< 0x02000000 */
+#define HRTIM_CPT2CR_TD1RST           HRTIM_CPT2CR_TD1RST_Msk                  /*!< Timer D output 1 reset */
+#define HRTIM_CPT2CR_TIMDCMP1_Pos     (26U)
+#define HRTIM_CPT2CR_TIMDCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMDCMP1_Pos)     /*!< 0x04000000 */
+#define HRTIM_CPT2CR_TIMDCMP1         HRTIM_CPT2CR_TIMDCMP1_Msk                /*!< Timer D compare 1 */
+#define HRTIM_CPT2CR_TIMDCMP2_Pos     (27U)
+#define HRTIM_CPT2CR_TIMDCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMDCMP2_Pos)     /*!< 0x08000000 */
+#define HRTIM_CPT2CR_TIMDCMP2         HRTIM_CPT2CR_TIMDCMP2_Msk                /*!< Timer D compare 2 */
+
+#define HRTIM_CPT2CR_TE1SET_Pos       (28U)
+#define HRTIM_CPT2CR_TE1SET_Msk       (0x1UL << HRTIM_CPT2CR_TE1SET_Pos)       /*!< 0x10000000 */
+#define HRTIM_CPT2CR_TE1SET           HRTIM_CPT2CR_TE1SET_Msk                  /*!< Timer E output 1 set */
+#define HRTIM_CPT2CR_TE1RST_Pos       (29U)
+#define HRTIM_CPT2CR_TE1RST_Msk       (0x1UL << HRTIM_CPT2CR_TE1RST_Pos)       /*!< 0x20000000 */
+#define HRTIM_CPT2CR_TE1RST           HRTIM_CPT2CR_TE1RST_Msk                  /*!< Timer E output 1 reset */
+#define HRTIM_CPT2CR_TIMECMP1_Pos     (30U)
+#define HRTIM_CPT2CR_TIMECMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMECMP1_Pos)     /*!< 0x40000000 */
+#define HRTIM_CPT2CR_TIMECMP1         HRTIM_CPT2CR_TIMECMP1_Msk                /*!< Timer E compare 1 */
+#define HRTIM_CPT2CR_TIMECMP2_Pos     (31U)
+#define HRTIM_CPT2CR_TIMECMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMECMP2_Pos)     /*!< 0x80000000 */
+#define HRTIM_CPT2CR_TIMECMP2         HRTIM_CPT2CR_TIMECMP2_Msk                /*!< Timer E compare 2 */
+
+/**** Bit definition for Slave Timer Output register **************************/
+#define HRTIM_OUTR_POL1_Pos           (1U)
+#define HRTIM_OUTR_POL1_Msk           (0x1UL << HRTIM_OUTR_POL1_Pos)           /*!< 0x00000002 */
+#define HRTIM_OUTR_POL1               HRTIM_OUTR_POL1_Msk                      /*!< Slave output 1 polarity */
+#define HRTIM_OUTR_IDLM1_Pos          (2U)
+#define HRTIM_OUTR_IDLM1_Msk          (0x1UL << HRTIM_OUTR_IDLM1_Pos)          /*!< 0x00000004 */
+#define HRTIM_OUTR_IDLM1              HRTIM_OUTR_IDLM1_Msk                     /*!< Slave output 1 idle mode */
+#define HRTIM_OUTR_IDLES1_Pos         (3U)
+#define HRTIM_OUTR_IDLES1_Msk         (0x1UL << HRTIM_OUTR_IDLES1_Pos)         /*!< 0x00000008 */
+#define HRTIM_OUTR_IDLES1             HRTIM_OUTR_IDLES1_Msk                    /*!< Slave output 1 idle state */
+#define HRTIM_OUTR_FAULT1_Pos         (4U)
+#define HRTIM_OUTR_FAULT1_Msk         (0x3UL << HRTIM_OUTR_FAULT1_Pos)         /*!< 0x00000030 */
+#define HRTIM_OUTR_FAULT1             HRTIM_OUTR_FAULT1_Msk                    /*!< Slave output 1 fault state */
+#define HRTIM_OUTR_FAULT1_0           (0x1UL << HRTIM_OUTR_FAULT1_Pos)          /*!< 0x00000010 */
+#define HRTIM_OUTR_FAULT1_1           (0x2UL << HRTIM_OUTR_FAULT1_Pos)          /*!< 0x00000020 */
+#define HRTIM_OUTR_CHP1_Pos           (6U)
+#define HRTIM_OUTR_CHP1_Msk           (0x1UL << HRTIM_OUTR_CHP1_Pos)           /*!< 0x00000040 */
+#define HRTIM_OUTR_CHP1               HRTIM_OUTR_CHP1_Msk                      /*!< Slave output 1 chopper enable */
+#define HRTIM_OUTR_DIDL1_Pos          (7U)
+#define HRTIM_OUTR_DIDL1_Msk          (0x1UL << HRTIM_OUTR_DIDL1_Pos)          /*!< 0x00000080 */
+#define HRTIM_OUTR_DIDL1              HRTIM_OUTR_DIDL1_Msk                     /*!< Slave output 1 dead time idle */
+
+#define HRTIM_OUTR_DTEN_Pos           (8U)
+#define HRTIM_OUTR_DTEN_Msk           (0x1UL << HRTIM_OUTR_DTEN_Pos)           /*!< 0x00000100 */
+#define HRTIM_OUTR_DTEN               HRTIM_OUTR_DTEN_Msk                      /*!< Slave output deadtime enable */
+#define HRTIM_OUTR_DLYPRTEN_Pos       (9U)
+#define HRTIM_OUTR_DLYPRTEN_Msk       (0x1UL << HRTIM_OUTR_DLYPRTEN_Pos)       /*!< 0x00000200 */
+#define HRTIM_OUTR_DLYPRTEN           HRTIM_OUTR_DLYPRTEN_Msk                  /*!< Slave output delay protection enable */
+#define HRTIM_OUTR_DLYPRT_Pos         (10U)
+#define HRTIM_OUTR_DLYPRT_Msk         (0x7UL << HRTIM_OUTR_DLYPRT_Pos)         /*!< 0x00001C00 */
+#define HRTIM_OUTR_DLYPRT             HRTIM_OUTR_DLYPRT_Msk                    /*!< Slave output delay protection */
+#define HRTIM_OUTR_DLYPRT_0           (0x1UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00000400 */
+#define HRTIM_OUTR_DLYPRT_1           (0x2UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00000800 */
+#define HRTIM_OUTR_DLYPRT_2           (0x4UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00001000 */
+
+#define HRTIM_OUTR_POL2_Pos           (17U)
+#define HRTIM_OUTR_POL2_Msk           (0x1UL << HRTIM_OUTR_POL2_Pos)           /*!< 0x00020000 */
+#define HRTIM_OUTR_POL2               HRTIM_OUTR_POL2_Msk                      /*!< Slave output 2 polarity */
+#define HRTIM_OUTR_IDLM2_Pos          (18U)
+#define HRTIM_OUTR_IDLM2_Msk          (0x1UL << HRTIM_OUTR_IDLM2_Pos)          /*!< 0x00040000 */
+#define HRTIM_OUTR_IDLM2              HRTIM_OUTR_IDLM2_Msk                     /*!< Slave output 2 idle mode */
+#define HRTIM_OUTR_IDLES2_Pos         (19U)
+#define HRTIM_OUTR_IDLES2_Msk         (0x1UL << HRTIM_OUTR_IDLES2_Pos)         /*!< 0x00080000 */
+#define HRTIM_OUTR_IDLES2             HRTIM_OUTR_IDLES2_Msk                    /*!< Slave output 2 idle state */
+#define HRTIM_OUTR_FAULT2_Pos         (20U)
+#define HRTIM_OUTR_FAULT2_Msk         (0x3UL << HRTIM_OUTR_FAULT2_Pos)         /*!< 0x00300000 */
+#define HRTIM_OUTR_FAULT2             HRTIM_OUTR_FAULT2_Msk                    /*!< Slave output 2 fault state */
+#define HRTIM_OUTR_FAULT2_0           (0x1UL << HRTIM_OUTR_FAULT2_Pos)          /*!< 0x00100000 */
+#define HRTIM_OUTR_FAULT2_1           (0x2UL << HRTIM_OUTR_FAULT2_Pos)          /*!< 0x00200000 */
+#define HRTIM_OUTR_CHP2_Pos           (22U)
+#define HRTIM_OUTR_CHP2_Msk           (0x1UL << HRTIM_OUTR_CHP2_Pos)           /*!< 0x00400000 */
+#define HRTIM_OUTR_CHP2               HRTIM_OUTR_CHP2_Msk                      /*!< Slave output 2 chopper enable */
+#define HRTIM_OUTR_DIDL2_Pos          (23U)
+#define HRTIM_OUTR_DIDL2_Msk          (0x1UL << HRTIM_OUTR_DIDL2_Pos)          /*!< 0x00800000 */
+#define HRTIM_OUTR_DIDL2              HRTIM_OUTR_DIDL2_Msk                     /*!< Slave output 2 dead time idle */
+
+/**** Bit definition for Slave Timer Fault register ***************************/
+#define HRTIM_FLTR_FLT1EN_Pos         (0U)
+#define HRTIM_FLTR_FLT1EN_Msk         (0x1UL << HRTIM_FLTR_FLT1EN_Pos)         /*!< 0x00000001 */
+#define HRTIM_FLTR_FLT1EN             HRTIM_FLTR_FLT1EN_Msk                    /*!< Fault 1 enable */
+#define HRTIM_FLTR_FLT2EN_Pos         (1U)
+#define HRTIM_FLTR_FLT2EN_Msk         (0x1UL << HRTIM_FLTR_FLT2EN_Pos)         /*!< 0x00000002 */
+#define HRTIM_FLTR_FLT2EN             HRTIM_FLTR_FLT2EN_Msk                    /*!< Fault 2 enable */
+#define HRTIM_FLTR_FLT3EN_Pos         (2U)
+#define HRTIM_FLTR_FLT3EN_Msk         (0x1UL << HRTIM_FLTR_FLT3EN_Pos)         /*!< 0x00000004 */
+#define HRTIM_FLTR_FLT3EN             HRTIM_FLTR_FLT3EN_Msk                    /*!< Fault 3 enable */
+#define HRTIM_FLTR_FLT4EN_Pos         (3U)
+#define HRTIM_FLTR_FLT4EN_Msk         (0x1UL << HRTIM_FLTR_FLT4EN_Pos)         /*!< 0x00000008 */
+#define HRTIM_FLTR_FLT4EN             HRTIM_FLTR_FLT4EN_Msk                    /*!< Fault 4 enable */
+#define HRTIM_FLTR_FLT5EN_Pos         (4U)
+#define HRTIM_FLTR_FLT5EN_Msk         (0x1UL << HRTIM_FLTR_FLT5EN_Pos)         /*!< 0x00000010 */
+#define HRTIM_FLTR_FLT5EN             HRTIM_FLTR_FLT5EN_Msk                    /*!< Fault 5 enable */
+#define HRTIM_FLTR_FLTLCK_Pos         (31U)
+#define HRTIM_FLTR_FLTLCK_Msk         (0x1UL << HRTIM_FLTR_FLTLCK_Pos)         /*!< 0x80000000 */
+#define HRTIM_FLTR_FLTLCK             HRTIM_FLTR_FLTLCK_Msk                    /*!< Fault sources lock */
+
+/**** Bit definition for Common HRTIM Timer control register 1 ****************/
+#define HRTIM_CR1_MUDIS_Pos           (0U)
+#define HRTIM_CR1_MUDIS_Msk           (0x1UL << HRTIM_CR1_MUDIS_Pos)           /*!< 0x00000001 */
+#define HRTIM_CR1_MUDIS               HRTIM_CR1_MUDIS_Msk                      /*!< Master update disable*/
+#define HRTIM_CR1_TAUDIS_Pos          (1U)
+#define HRTIM_CR1_TAUDIS_Msk          (0x1UL << HRTIM_CR1_TAUDIS_Pos)          /*!< 0x00000002 */
+#define HRTIM_CR1_TAUDIS              HRTIM_CR1_TAUDIS_Msk                     /*!< Timer A update disable*/
+#define HRTIM_CR1_TBUDIS_Pos          (2U)
+#define HRTIM_CR1_TBUDIS_Msk          (0x1UL << HRTIM_CR1_TBUDIS_Pos)          /*!< 0x00000004 */
+#define HRTIM_CR1_TBUDIS              HRTIM_CR1_TBUDIS_Msk                     /*!< Timer B update disable*/
+#define HRTIM_CR1_TCUDIS_Pos          (3U)
+#define HRTIM_CR1_TCUDIS_Msk          (0x1UL << HRTIM_CR1_TCUDIS_Pos)          /*!< 0x00000008 */
+#define HRTIM_CR1_TCUDIS              HRTIM_CR1_TCUDIS_Msk                     /*!< Timer C update disable*/
+#define HRTIM_CR1_TDUDIS_Pos          (4U)
+#define HRTIM_CR1_TDUDIS_Msk          (0x1UL << HRTIM_CR1_TDUDIS_Pos)          /*!< 0x00000010 */
+#define HRTIM_CR1_TDUDIS              HRTIM_CR1_TDUDIS_Msk                     /*!< Timer D update disable*/
+#define HRTIM_CR1_TEUDIS_Pos          (5U)
+#define HRTIM_CR1_TEUDIS_Msk          (0x1UL << HRTIM_CR1_TEUDIS_Pos)          /*!< 0x00000020 */
+#define HRTIM_CR1_TEUDIS              HRTIM_CR1_TEUDIS_Msk                     /*!< Timer E update disable*/
+#define HRTIM_CR1_ADC1USRC_Pos        (16U)
+#define HRTIM_CR1_ADC1USRC_Msk        (0x7UL << HRTIM_CR1_ADC1USRC_Pos)        /*!< 0x00070000 */
+#define HRTIM_CR1_ADC1USRC            HRTIM_CR1_ADC1USRC_Msk                   /*!< ADC Trigger 1 update source */
+#define HRTIM_CR1_ADC1USRC_0          (0x1UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00010000 */
+#define HRTIM_CR1_ADC1USRC_1          (0x2UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00020000 */
+#define HRTIM_CR1_ADC1USRC_2          (0x4UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00040000 */
+#define HRTIM_CR1_ADC2USRC_Pos        (19U)
+#define HRTIM_CR1_ADC2USRC_Msk        (0x7UL << HRTIM_CR1_ADC2USRC_Pos)        /*!< 0x00380000 */
+#define HRTIM_CR1_ADC2USRC            HRTIM_CR1_ADC2USRC_Msk                   /*!< ADC Trigger 2 update source */
+#define HRTIM_CR1_ADC2USRC_0          (0x1UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00080000 */
+#define HRTIM_CR1_ADC2USRC_1          (0x2UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00100000 */
+#define HRTIM_CR1_ADC2USRC_2          (0x4UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00200000 */
+#define HRTIM_CR1_ADC3USRC_Pos        (22U)
+#define HRTIM_CR1_ADC3USRC_Msk        (0x7UL << HRTIM_CR1_ADC3USRC_Pos)        /*!< 0x01C00000 */
+#define HRTIM_CR1_ADC3USRC            HRTIM_CR1_ADC3USRC_Msk                   /*!< ADC Trigger 3 update source */
+#define HRTIM_CR1_ADC3USRC_0          (0x1UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x00400000 */
+#define HRTIM_CR1_ADC3USRC_1          (0x2UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x00800000 */
+#define HRTIM_CR1_ADC3USRC_2          (0x4UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x01000000 */
+#define HRTIM_CR1_ADC4USRC_Pos        (25U)
+#define HRTIM_CR1_ADC4USRC_Msk        (0x7UL << HRTIM_CR1_ADC4USRC_Pos)        /*!< 0x0E000000 */
+#define HRTIM_CR1_ADC4USRC            HRTIM_CR1_ADC4USRC_Msk                   /*!< ADC Trigger 4 update source */
+#define HRTIM_CR1_ADC4USRC_0          (0x1UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x02000000 */
+#define HRTIM_CR1_ADC4USRC_1          (0x2UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x04000000 */
+#define HRTIM_CR1_ADC4USRC_2          (0x0UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x0800000 */
+
+/**** Bit definition for Common HRTIM Timer control register 2 ****************/
+#define HRTIM_CR2_MSWU_Pos            (0U)
+#define HRTIM_CR2_MSWU_Msk            (0x1UL << HRTIM_CR2_MSWU_Pos)            /*!< 0x00000001 */
+#define HRTIM_CR2_MSWU                HRTIM_CR2_MSWU_Msk                       /*!< Master software update */
+#define HRTIM_CR2_TASWU_Pos           (1U)
+#define HRTIM_CR2_TASWU_Msk           (0x1UL << HRTIM_CR2_TASWU_Pos)           /*!< 0x00000002 */
+#define HRTIM_CR2_TASWU               HRTIM_CR2_TASWU_Msk                      /*!< Timer A software update */
+#define HRTIM_CR2_TBSWU_Pos           (2U)
+#define HRTIM_CR2_TBSWU_Msk           (0x1UL << HRTIM_CR2_TBSWU_Pos)           /*!< 0x00000004 */
+#define HRTIM_CR2_TBSWU               HRTIM_CR2_TBSWU_Msk                      /*!< Timer B software update */
+#define HRTIM_CR2_TCSWU_Pos           (3U)
+#define HRTIM_CR2_TCSWU_Msk           (0x1UL << HRTIM_CR2_TCSWU_Pos)           /*!< 0x00000008 */
+#define HRTIM_CR2_TCSWU               HRTIM_CR2_TCSWU_Msk                      /*!< Timer C software update */
+#define HRTIM_CR2_TDSWU_Pos           (4U)
+#define HRTIM_CR2_TDSWU_Msk           (0x1UL << HRTIM_CR2_TDSWU_Pos)           /*!< 0x00000010 */
+#define HRTIM_CR2_TDSWU               HRTIM_CR2_TDSWU_Msk                      /*!< Timer D software update */
+#define HRTIM_CR2_TESWU_Pos           (5U)
+#define HRTIM_CR2_TESWU_Msk           (0x1UL << HRTIM_CR2_TESWU_Pos)           /*!< 0x00000020 */
+#define HRTIM_CR2_TESWU               HRTIM_CR2_TESWU_Msk                      /*!< Timer E software update */
+#define HRTIM_CR2_MRST_Pos            (8U)
+#define HRTIM_CR2_MRST_Msk            (0x1UL << HRTIM_CR2_MRST_Pos)            /*!< 0x00000100 */
+#define HRTIM_CR2_MRST                HRTIM_CR2_MRST_Msk                       /*!< Master count software reset */
+#define HRTIM_CR2_TARST_Pos           (9U)
+#define HRTIM_CR2_TARST_Msk           (0x1UL << HRTIM_CR2_TARST_Pos)           /*!< 0x00000200 */
+#define HRTIM_CR2_TARST               HRTIM_CR2_TARST_Msk                      /*!< Timer A count software reset */
+#define HRTIM_CR2_TBRST_Pos           (10U)
+#define HRTIM_CR2_TBRST_Msk           (0x1UL << HRTIM_CR2_TBRST_Pos)           /*!< 0x00000400 */
+#define HRTIM_CR2_TBRST               HRTIM_CR2_TBRST_Msk                      /*!< Timer B count software reset */
+#define HRTIM_CR2_TCRST_Pos           (11U)
+#define HRTIM_CR2_TCRST_Msk           (0x1UL << HRTIM_CR2_TCRST_Pos)           /*!< 0x00000800 */
+#define HRTIM_CR2_TCRST               HRTIM_CR2_TCRST_Msk                      /*!< Timer C count software reset */
+#define HRTIM_CR2_TDRST_Pos           (12U)
+#define HRTIM_CR2_TDRST_Msk           (0x1UL << HRTIM_CR2_TDRST_Pos)           /*!< 0x00001000 */
+#define HRTIM_CR2_TDRST               HRTIM_CR2_TDRST_Msk                      /*!< Timer D count software reset */
+#define HRTIM_CR2_TERST_Pos           (13U)
+#define HRTIM_CR2_TERST_Msk           (0x1UL << HRTIM_CR2_TERST_Pos)           /*!< 0x00002000 */
+#define HRTIM_CR2_TERST               HRTIM_CR2_TERST_Msk                      /*!< Timer E count software reset */
+
+/**** Bit definition for Common HRTIM Timer interrupt status register *********/
+#define HRTIM_ISR_FLT1_Pos            (0U)
+#define HRTIM_ISR_FLT1_Msk            (0x1UL << HRTIM_ISR_FLT1_Pos)            /*!< 0x00000001 */
+#define HRTIM_ISR_FLT1                HRTIM_ISR_FLT1_Msk                       /*!< Fault 1 interrupt flag */
+#define HRTIM_ISR_FLT2_Pos            (1U)
+#define HRTIM_ISR_FLT2_Msk            (0x1UL << HRTIM_ISR_FLT2_Pos)            /*!< 0x00000002 */
+#define HRTIM_ISR_FLT2                HRTIM_ISR_FLT2_Msk                       /*!< Fault 2 interrupt flag */
+#define HRTIM_ISR_FLT3_Pos            (2U)
+#define HRTIM_ISR_FLT3_Msk            (0x1UL << HRTIM_ISR_FLT3_Pos)            /*!< 0x00000004 */
+#define HRTIM_ISR_FLT3                HRTIM_ISR_FLT3_Msk                       /*!< Fault 3 interrupt flag */
+#define HRTIM_ISR_FLT4_Pos            (3U)
+#define HRTIM_ISR_FLT4_Msk            (0x1UL << HRTIM_ISR_FLT4_Pos)            /*!< 0x00000008 */
+#define HRTIM_ISR_FLT4                HRTIM_ISR_FLT4_Msk                       /*!< Fault 4 interrupt flag */
+#define HRTIM_ISR_FLT5_Pos            (4U)
+#define HRTIM_ISR_FLT5_Msk            (0x1UL << HRTIM_ISR_FLT5_Pos)            /*!< 0x00000010 */
+#define HRTIM_ISR_FLT5                HRTIM_ISR_FLT5_Msk                       /*!< Fault 5 interrupt flag */
+#define HRTIM_ISR_SYSFLT_Pos          (5U)
+#define HRTIM_ISR_SYSFLT_Msk          (0x1UL << HRTIM_ISR_SYSFLT_Pos)          /*!< 0x00000020 */
+#define HRTIM_ISR_SYSFLT              HRTIM_ISR_SYSFLT_Msk                     /*!< System Fault interrupt flag */
+#define HRTIM_ISR_BMPER_Pos           (17U)
+#define HRTIM_ISR_BMPER_Msk           (0x1UL << HRTIM_ISR_BMPER_Pos)           /*!< 0x00020000 */
+#define HRTIM_ISR_BMPER               HRTIM_ISR_BMPER_Msk                      /*!<  Burst mode period interrupt flag */
+
+/**** Bit definition for Common HRTIM Timer interrupt clear register **********/
+#define HRTIM_ICR_FLT1C_Pos           (0U)
+#define HRTIM_ICR_FLT1C_Msk           (0x1UL << HRTIM_ICR_FLT1C_Pos)           /*!< 0x00000001 */
+#define HRTIM_ICR_FLT1C               HRTIM_ICR_FLT1C_Msk                      /*!< Fault 1 interrupt flag clear */
+#define HRTIM_ICR_FLT2C_Pos           (1U)
+#define HRTIM_ICR_FLT2C_Msk           (0x1UL << HRTIM_ICR_FLT2C_Pos)           /*!< 0x00000002 */
+#define HRTIM_ICR_FLT2C               HRTIM_ICR_FLT2C_Msk                      /*!< Fault 2 interrupt flag clear */
+#define HRTIM_ICR_FLT3C_Pos           (2U)
+#define HRTIM_ICR_FLT3C_Msk           (0x1UL << HRTIM_ICR_FLT3C_Pos)           /*!< 0x00000004 */
+#define HRTIM_ICR_FLT3C               HRTIM_ICR_FLT3C_Msk                      /*!< Fault 3 interrupt flag clear */
+#define HRTIM_ICR_FLT4C_Pos           (3U)
+#define HRTIM_ICR_FLT4C_Msk           (0x1UL << HRTIM_ICR_FLT4C_Pos)           /*!< 0x00000008 */
+#define HRTIM_ICR_FLT4C               HRTIM_ICR_FLT4C_Msk                      /*!< Fault 4 interrupt flag clear */
+#define HRTIM_ICR_FLT5C_Pos           (4U)
+#define HRTIM_ICR_FLT5C_Msk           (0x1UL << HRTIM_ICR_FLT5C_Pos)           /*!< 0x00000010 */
+#define HRTIM_ICR_FLT5C               HRTIM_ICR_FLT5C_Msk                      /*!< Fault 5 interrupt flag clear */
+#define HRTIM_ICR_SYSFLTC_Pos         (5U)
+#define HRTIM_ICR_SYSFLTC_Msk         (0x1UL << HRTIM_ICR_SYSFLTC_Pos)         /*!< 0x00000020 */
+#define HRTIM_ICR_SYSFLTC             HRTIM_ICR_SYSFLTC_Msk                    /*!< System Fault interrupt flag clear */
+#define HRTIM_ICR_BMPERC_Pos          (17U)
+#define HRTIM_ICR_BMPERC_Msk          (0x1UL << HRTIM_ICR_BMPERC_Pos)          /*!< 0x00020000 */
+#define HRTIM_ICR_BMPERC              HRTIM_ICR_BMPERC_Msk                     /*!<  Burst mode period interrupt flag clear */
+
+/**** Bit definition for Common HRTIM Timer interrupt enable register *********/
+#define HRTIM_IER_FLT1_Pos            (0U)
+#define HRTIM_IER_FLT1_Msk            (0x1UL << HRTIM_IER_FLT1_Pos)            /*!< 0x00000001 */
+#define HRTIM_IER_FLT1                HRTIM_IER_FLT1_Msk                       /*!< Fault 1 interrupt enable */
+#define HRTIM_IER_FLT2_Pos            (1U)
+#define HRTIM_IER_FLT2_Msk            (0x1UL << HRTIM_IER_FLT2_Pos)            /*!< 0x00000002 */
+#define HRTIM_IER_FLT2                HRTIM_IER_FLT2_Msk                       /*!< Fault 2 interrupt enable */
+#define HRTIM_IER_FLT3_Pos            (2U)
+#define HRTIM_IER_FLT3_Msk            (0x1UL << HRTIM_IER_FLT3_Pos)            /*!< 0x00000004 */
+#define HRTIM_IER_FLT3                HRTIM_IER_FLT3_Msk                       /*!< Fault 3 interrupt enable */
+#define HRTIM_IER_FLT4_Pos            (3U)
+#define HRTIM_IER_FLT4_Msk            (0x1UL << HRTIM_IER_FLT4_Pos)            /*!< 0x00000008 */
+#define HRTIM_IER_FLT4                HRTIM_IER_FLT4_Msk                       /*!< Fault 4 interrupt enable */
+#define HRTIM_IER_FLT5_Pos            (4U)
+#define HRTIM_IER_FLT5_Msk            (0x1UL << HRTIM_IER_FLT5_Pos)            /*!< 0x00000010 */
+#define HRTIM_IER_FLT5                HRTIM_IER_FLT5_Msk                       /*!< Fault 5 interrupt enable */
+#define HRTIM_IER_SYSFLT_Pos          (5U)
+#define HRTIM_IER_SYSFLT_Msk          (0x1UL << HRTIM_IER_SYSFLT_Pos)          /*!< 0x00000020 */
+#define HRTIM_IER_SYSFLT              HRTIM_IER_SYSFLT_Msk                     /*!< System Fault interrupt enable */
+#define HRTIM_IER_BMPER_Pos           (17U)
+#define HRTIM_IER_BMPER_Msk           (0x1UL << HRTIM_IER_BMPER_Pos)           /*!< 0x00020000 */
+#define HRTIM_IER_BMPER               HRTIM_IER_BMPER_Msk                      /*!<  Burst mode period interrupt enable */
+
+/**** Bit definition for Common HRTIM Timer output enable register ************/
+#define HRTIM_OENR_TA1OEN_Pos         (0U)
+#define HRTIM_OENR_TA1OEN_Msk         (0x1UL << HRTIM_OENR_TA1OEN_Pos)         /*!< 0x00000001 */
+#define HRTIM_OENR_TA1OEN             HRTIM_OENR_TA1OEN_Msk                    /*!< Timer A Output 1 enable */
+#define HRTIM_OENR_TA2OEN_Pos         (1U)
+#define HRTIM_OENR_TA2OEN_Msk         (0x1UL << HRTIM_OENR_TA2OEN_Pos)         /*!< 0x00000002 */
+#define HRTIM_OENR_TA2OEN             HRTIM_OENR_TA2OEN_Msk                    /*!< Timer A Output 2 enable */
+#define HRTIM_OENR_TB1OEN_Pos         (2U)
+#define HRTIM_OENR_TB1OEN_Msk         (0x1UL << HRTIM_OENR_TB1OEN_Pos)         /*!< 0x00000004 */
+#define HRTIM_OENR_TB1OEN             HRTIM_OENR_TB1OEN_Msk                    /*!< Timer B Output 1 enable */
+#define HRTIM_OENR_TB2OEN_Pos         (3U)
+#define HRTIM_OENR_TB2OEN_Msk         (0x1UL << HRTIM_OENR_TB2OEN_Pos)         /*!< 0x00000008 */
+#define HRTIM_OENR_TB2OEN             HRTIM_OENR_TB2OEN_Msk                    /*!< Timer B Output 2 enable */
+#define HRTIM_OENR_TC1OEN_Pos         (4U)
+#define HRTIM_OENR_TC1OEN_Msk         (0x1UL << HRTIM_OENR_TC1OEN_Pos)         /*!< 0x00000010 */
+#define HRTIM_OENR_TC1OEN             HRTIM_OENR_TC1OEN_Msk                    /*!< Timer C Output 1 enable */
+#define HRTIM_OENR_TC2OEN_Pos         (5U)
+#define HRTIM_OENR_TC2OEN_Msk         (0x1UL << HRTIM_OENR_TC2OEN_Pos)         /*!< 0x00000020 */
+#define HRTIM_OENR_TC2OEN             HRTIM_OENR_TC2OEN_Msk                    /*!< Timer C Output 2 enable */
+#define HRTIM_OENR_TD1OEN_Pos         (6U)
+#define HRTIM_OENR_TD1OEN_Msk         (0x1UL << HRTIM_OENR_TD1OEN_Pos)         /*!< 0x00000040 */
+#define HRTIM_OENR_TD1OEN             HRTIM_OENR_TD1OEN_Msk                    /*!< Timer D Output 1 enable */
+#define HRTIM_OENR_TD2OEN_Pos         (7U)
+#define HRTIM_OENR_TD2OEN_Msk         (0x1UL << HRTIM_OENR_TD2OEN_Pos)         /*!< 0x00000080 */
+#define HRTIM_OENR_TD2OEN             HRTIM_OENR_TD2OEN_Msk                    /*!< Timer D Output 2 enable */
+#define HRTIM_OENR_TE1OEN_Pos         (8U)
+#define HRTIM_OENR_TE1OEN_Msk         (0x1UL << HRTIM_OENR_TE1OEN_Pos)         /*!< 0x00000100 */
+#define HRTIM_OENR_TE1OEN             HRTIM_OENR_TE1OEN_Msk                    /*!< Timer E Output 1 enable */
+#define HRTIM_OENR_TE2OEN_Pos         (9U)
+#define HRTIM_OENR_TE2OEN_Msk         (0x1UL << HRTIM_OENR_TE2OEN_Pos)         /*!< 0x00000200 */
+#define HRTIM_OENR_TE2OEN             HRTIM_OENR_TE2OEN_Msk                    /*!< Timer E Output 2 enable */
+
+/**** Bit definition for Common HRTIM Timer output disable register ***********/
+#define HRTIM_ODISR_TA1ODIS_Pos       (0U)
+#define HRTIM_ODISR_TA1ODIS_Msk       (0x1UL << HRTIM_ODISR_TA1ODIS_Pos)       /*!< 0x00000001 */
+#define HRTIM_ODISR_TA1ODIS           HRTIM_ODISR_TA1ODIS_Msk                  /*!< Timer A Output 1 disable */
+#define HRTIM_ODISR_TA2ODIS_Pos       (1U)
+#define HRTIM_ODISR_TA2ODIS_Msk       (0x1UL << HRTIM_ODISR_TA2ODIS_Pos)       /*!< 0x00000002 */
+#define HRTIM_ODISR_TA2ODIS           HRTIM_ODISR_TA2ODIS_Msk                  /*!< Timer A Output 2 disable */
+#define HRTIM_ODISR_TB1ODIS_Pos       (2U)
+#define HRTIM_ODISR_TB1ODIS_Msk       (0x1UL << HRTIM_ODISR_TB1ODIS_Pos)       /*!< 0x00000004 */
+#define HRTIM_ODISR_TB1ODIS           HRTIM_ODISR_TB1ODIS_Msk                  /*!< Timer B Output 1 disable */
+#define HRTIM_ODISR_TB2ODIS_Pos       (3U)
+#define HRTIM_ODISR_TB2ODIS_Msk       (0x1UL << HRTIM_ODISR_TB2ODIS_Pos)       /*!< 0x00000008 */
+#define HRTIM_ODISR_TB2ODIS           HRTIM_ODISR_TB2ODIS_Msk                  /*!< Timer B Output 2 disable */
+#define HRTIM_ODISR_TC1ODIS_Pos       (4U)
+#define HRTIM_ODISR_TC1ODIS_Msk       (0x1UL << HRTIM_ODISR_TC1ODIS_Pos)       /*!< 0x00000010 */
+#define HRTIM_ODISR_TC1ODIS           HRTIM_ODISR_TC1ODIS_Msk                  /*!< Timer C Output 1 disable */
+#define HRTIM_ODISR_TC2ODIS_Pos       (5U)
+#define HRTIM_ODISR_TC2ODIS_Msk       (0x1UL << HRTIM_ODISR_TC2ODIS_Pos)       /*!< 0x00000020 */
+#define HRTIM_ODISR_TC2ODIS           HRTIM_ODISR_TC2ODIS_Msk                  /*!< Timer C Output 2 disable */
+#define HRTIM_ODISR_TD1ODIS_Pos       (6U)
+#define HRTIM_ODISR_TD1ODIS_Msk       (0x1UL << HRTIM_ODISR_TD1ODIS_Pos)       /*!< 0x00000040 */
+#define HRTIM_ODISR_TD1ODIS           HRTIM_ODISR_TD1ODIS_Msk                  /*!< Timer D Output 1 disable */
+#define HRTIM_ODISR_TD2ODIS_Pos       (7U)
+#define HRTIM_ODISR_TD2ODIS_Msk       (0x1UL << HRTIM_ODISR_TD2ODIS_Pos)       /*!< 0x00000080 */
+#define HRTIM_ODISR_TD2ODIS           HRTIM_ODISR_TD2ODIS_Msk                  /*!< Timer D Output 2 disable */
+#define HRTIM_ODISR_TE1ODIS_Pos       (8U)
+#define HRTIM_ODISR_TE1ODIS_Msk       (0x1UL << HRTIM_ODISR_TE1ODIS_Pos)       /*!< 0x00000100 */
+#define HRTIM_ODISR_TE1ODIS           HRTIM_ODISR_TE1ODIS_Msk                  /*!< Timer E Output 1 disable */
+#define HRTIM_ODISR_TE2ODIS_Pos       (9U)
+#define HRTIM_ODISR_TE2ODIS_Msk       (0x1UL << HRTIM_ODISR_TE2ODIS_Pos)       /*!< 0x00000200 */
+#define HRTIM_ODISR_TE2ODIS           HRTIM_ODISR_TE2ODIS_Msk                  /*!< Timer E Output 2 disable */
+
+/**** Bit definition for Common HRTIM Timer output disable status register *****/
+#define HRTIM_ODSR_TA1ODS_Pos         (0U)
+#define HRTIM_ODSR_TA1ODS_Msk         (0x1UL << HRTIM_ODSR_TA1ODS_Pos)         /*!< 0x00000001 */
+#define HRTIM_ODSR_TA1ODS             HRTIM_ODSR_TA1ODS_Msk                    /*!< Timer A Output 1 disable status */
+#define HRTIM_ODSR_TA2ODS_Pos         (1U)
+#define HRTIM_ODSR_TA2ODS_Msk         (0x1UL << HRTIM_ODSR_TA2ODS_Pos)         /*!< 0x00000002 */
+#define HRTIM_ODSR_TA2ODS             HRTIM_ODSR_TA2ODS_Msk                    /*!< Timer A Output 2 disable status */
+#define HRTIM_ODSR_TB1ODS_Pos         (2U)
+#define HRTIM_ODSR_TB1ODS_Msk         (0x1UL << HRTIM_ODSR_TB1ODS_Pos)         /*!< 0x00000004 */
+#define HRTIM_ODSR_TB1ODS             HRTIM_ODSR_TB1ODS_Msk                    /*!< Timer B Output 1 disable status */
+#define HRTIM_ODSR_TB2ODS_Pos         (3U)
+#define HRTIM_ODSR_TB2ODS_Msk         (0x1UL << HRTIM_ODSR_TB2ODS_Pos)         /*!< 0x00000008 */
+#define HRTIM_ODSR_TB2ODS             HRTIM_ODSR_TB2ODS_Msk                    /*!< Timer B Output 2 disable status */
+#define HRTIM_ODSR_TC1ODS_Pos         (4U)
+#define HRTIM_ODSR_TC1ODS_Msk         (0x1UL << HRTIM_ODSR_TC1ODS_Pos)         /*!< 0x00000010 */
+#define HRTIM_ODSR_TC1ODS             HRTIM_ODSR_TC1ODS_Msk                    /*!< Timer C Output 1 disable status */
+#define HRTIM_ODSR_TC2ODS_Pos         (5U)
+#define HRTIM_ODSR_TC2ODS_Msk         (0x1UL << HRTIM_ODSR_TC2ODS_Pos)         /*!< 0x00000020 */
+#define HRTIM_ODSR_TC2ODS             HRTIM_ODSR_TC2ODS_Msk                    /*!< Timer C Output 2 disable status */
+#define HRTIM_ODSR_TD1ODS_Pos         (6U)
+#define HRTIM_ODSR_TD1ODS_Msk         (0x1UL << HRTIM_ODSR_TD1ODS_Pos)         /*!< 0x00000040 */
+#define HRTIM_ODSR_TD1ODS             HRTIM_ODSR_TD1ODS_Msk                    /*!< Timer D Output 1 disable status */
+#define HRTIM_ODSR_TD2ODS_Pos         (7U)
+#define HRTIM_ODSR_TD2ODS_Msk         (0x1UL << HRTIM_ODSR_TD2ODS_Pos)         /*!< 0x00000080 */
+#define HRTIM_ODSR_TD2ODS             HRTIM_ODSR_TD2ODS_Msk                    /*!< Timer D Output 2 disable status */
+#define HRTIM_ODSR_TE1ODS_Pos         (8U)
+#define HRTIM_ODSR_TE1ODS_Msk         (0x1UL << HRTIM_ODSR_TE1ODS_Pos)         /*!< 0x00000100 */
+#define HRTIM_ODSR_TE1ODS             HRTIM_ODSR_TE1ODS_Msk                    /*!< Timer E Output 1 disable status */
+#define HRTIM_ODSR_TE2ODS_Pos         (9U)
+#define HRTIM_ODSR_TE2ODS_Msk         (0x1UL << HRTIM_ODSR_TE2ODS_Pos)         /*!< 0x00000200 */
+#define HRTIM_ODSR_TE2ODS             HRTIM_ODSR_TE2ODS_Msk                    /*!< Timer E Output 2 disable status */
+
+/**** Bit definition for Common HRTIM Timer Burst mode control register ********/
+#define HRTIM_BMCR_BME_Pos            (0U)
+#define HRTIM_BMCR_BME_Msk            (0x1UL << HRTIM_BMCR_BME_Pos)            /*!< 0x00000001 */
+#define HRTIM_BMCR_BME                HRTIM_BMCR_BME_Msk                       /*!< Burst mode enbale */
+#define HRTIM_BMCR_BMOM_Pos           (1U)
+#define HRTIM_BMCR_BMOM_Msk           (0x1UL << HRTIM_BMCR_BMOM_Pos)           /*!< 0x00000002 */
+#define HRTIM_BMCR_BMOM               HRTIM_BMCR_BMOM_Msk                      /*!< Burst mode operating mode */
+#define HRTIM_BMCR_BMCLK_Pos          (2U)
+#define HRTIM_BMCR_BMCLK_Msk          (0xFUL << HRTIM_BMCR_BMCLK_Pos)          /*!< 0x0000003C */
+#define HRTIM_BMCR_BMCLK              HRTIM_BMCR_BMCLK_Msk                     /*!< Burst mode clock source */
+#define HRTIM_BMCR_BMCLK_0            (0x1UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000004 */
+#define HRTIM_BMCR_BMCLK_1            (0x2UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000008 */
+#define HRTIM_BMCR_BMCLK_2            (0x4UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000010 */
+#define HRTIM_BMCR_BMCLK_3            (0x8UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000020 */
+#define HRTIM_BMCR_BMPRSC_Pos         (6U)
+#define HRTIM_BMCR_BMPRSC_Msk         (0xFUL << HRTIM_BMCR_BMPRSC_Pos)         /*!< 0x000003C0 */
+#define HRTIM_BMCR_BMPRSC             HRTIM_BMCR_BMPRSC_Msk                    /*!< Burst mode prescaler */
+#define HRTIM_BMCR_BMPRSC_0           (0x1UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000040 */
+#define HRTIM_BMCR_BMPRSC_1           (0x2UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000080 */
+#define HRTIM_BMCR_BMPRSC_2           (0x4UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000100 */
+#define HRTIM_BMCR_BMPRSC_3           (0x8UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000200 */
+#define HRTIM_BMCR_BMPREN_Pos         (10U)
+#define HRTIM_BMCR_BMPREN_Msk         (0x1UL << HRTIM_BMCR_BMPREN_Pos)         /*!< 0x00000400 */
+#define HRTIM_BMCR_BMPREN             HRTIM_BMCR_BMPREN_Msk                    /*!< Burst mode Preload bit */
+#define HRTIM_BMCR_MTBM_Pos           (16U)
+#define HRTIM_BMCR_MTBM_Msk           (0x1UL << HRTIM_BMCR_MTBM_Pos)           /*!< 0x00010000 */
+#define HRTIM_BMCR_MTBM               HRTIM_BMCR_MTBM_Msk                      /*!< Master Timer Burst mode */
+#define HRTIM_BMCR_TABM_Pos           (17U)
+#define HRTIM_BMCR_TABM_Msk           (0x1UL << HRTIM_BMCR_TABM_Pos)           /*!< 0x00020000 */
+#define HRTIM_BMCR_TABM               HRTIM_BMCR_TABM_Msk                      /*!< Timer A Burst mode */
+#define HRTIM_BMCR_TBBM_Pos           (18U)
+#define HRTIM_BMCR_TBBM_Msk           (0x1UL << HRTIM_BMCR_TBBM_Pos)           /*!< 0x00040000 */
+#define HRTIM_BMCR_TBBM               HRTIM_BMCR_TBBM_Msk                      /*!< Timer B Burst mode */
+#define HRTIM_BMCR_TCBM_Pos           (19U)
+#define HRTIM_BMCR_TCBM_Msk           (0x1UL << HRTIM_BMCR_TCBM_Pos)           /*!< 0x00080000 */
+#define HRTIM_BMCR_TCBM               HRTIM_BMCR_TCBM_Msk                      /*!< Timer C Burst mode */
+#define HRTIM_BMCR_TDBM_Pos           (20U)
+#define HRTIM_BMCR_TDBM_Msk           (0x1UL << HRTIM_BMCR_TDBM_Pos)           /*!< 0x00100000 */
+#define HRTIM_BMCR_TDBM               HRTIM_BMCR_TDBM_Msk                      /*!< Timer D Burst mode */
+#define HRTIM_BMCR_TEBM_Pos           (21U)
+#define HRTIM_BMCR_TEBM_Msk           (0x1UL << HRTIM_BMCR_TEBM_Pos)           /*!< 0x00200000 */
+#define HRTIM_BMCR_TEBM               HRTIM_BMCR_TEBM_Msk                      /*!< Timer E Burst mode */
+#define HRTIM_BMCR_BMSTAT_Pos         (31U)
+#define HRTIM_BMCR_BMSTAT_Msk         (0x1UL << HRTIM_BMCR_BMSTAT_Pos)         /*!< 0x80000000 */
+#define HRTIM_BMCR_BMSTAT             HRTIM_BMCR_BMSTAT_Msk                    /*!< Burst mode status */
+
+/**** Bit definition for Common HRTIM Timer Burst mode Trigger register *******/
+#define HRTIM_BMTRGR_SW_Pos           (0U)
+#define HRTIM_BMTRGR_SW_Msk           (0x1UL << HRTIM_BMTRGR_SW_Pos)           /*!< 0x00000001 */
+#define HRTIM_BMTRGR_SW               HRTIM_BMTRGR_SW_Msk                      /*!< Software start */
+#define HRTIM_BMTRGR_MSTRST_Pos       (1U)
+#define HRTIM_BMTRGR_MSTRST_Msk       (0x1UL << HRTIM_BMTRGR_MSTRST_Pos)       /*!< 0x00000002 */
+#define HRTIM_BMTRGR_MSTRST           HRTIM_BMTRGR_MSTRST_Msk                  /*!<  Master reset */
+#define HRTIM_BMTRGR_MSTREP_Pos       (2U)
+#define HRTIM_BMTRGR_MSTREP_Msk       (0x1UL << HRTIM_BMTRGR_MSTREP_Pos)       /*!< 0x00000004 */
+#define HRTIM_BMTRGR_MSTREP           HRTIM_BMTRGR_MSTREP_Msk                  /*!<  Master repetition */
+#define HRTIM_BMTRGR_MSTCMP1_Pos      (3U)
+#define HRTIM_BMTRGR_MSTCMP1_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP1_Pos)      /*!< 0x00000008 */
+#define HRTIM_BMTRGR_MSTCMP1          HRTIM_BMTRGR_MSTCMP1_Msk                 /*!<  Master compare 1 */
+#define HRTIM_BMTRGR_MSTCMP2_Pos      (4U)
+#define HRTIM_BMTRGR_MSTCMP2_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP2_Pos)      /*!< 0x00000010 */
+#define HRTIM_BMTRGR_MSTCMP2          HRTIM_BMTRGR_MSTCMP2_Msk                 /*!< Master compare 2  */
+#define HRTIM_BMTRGR_MSTCMP3_Pos      (5U)
+#define HRTIM_BMTRGR_MSTCMP3_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP3_Pos)      /*!< 0x00000020 */
+#define HRTIM_BMTRGR_MSTCMP3          HRTIM_BMTRGR_MSTCMP3_Msk                 /*!< Master compare 3 */
+#define HRTIM_BMTRGR_MSTCMP4_Pos      (6U)
+#define HRTIM_BMTRGR_MSTCMP4_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP4_Pos)      /*!< 0x00000040 */
+#define HRTIM_BMTRGR_MSTCMP4          HRTIM_BMTRGR_MSTCMP4_Msk                 /*!< Master compare 4 */
+#define HRTIM_BMTRGR_TARST_Pos        (7U)
+#define HRTIM_BMTRGR_TARST_Msk        (0x1UL << HRTIM_BMTRGR_TARST_Pos)        /*!< 0x00000080 */
+#define HRTIM_BMTRGR_TARST            HRTIM_BMTRGR_TARST_Msk                   /*!< Timer A reset  */
+#define HRTIM_BMTRGR_TAREP_Pos        (8U)
+#define HRTIM_BMTRGR_TAREP_Msk        (0x1UL << HRTIM_BMTRGR_TAREP_Pos)        /*!< 0x00000100 */
+#define HRTIM_BMTRGR_TAREP            HRTIM_BMTRGR_TAREP_Msk                   /*!< Timer A repetition  */
+#define HRTIM_BMTRGR_TACMP1_Pos       (9U)
+#define HRTIM_BMTRGR_TACMP1_Msk       (0x1UL << HRTIM_BMTRGR_TACMP1_Pos)       /*!< 0x00000200 */
+#define HRTIM_BMTRGR_TACMP1           HRTIM_BMTRGR_TACMP1_Msk                  /*!< Timer A compare 1  */
+#define HRTIM_BMTRGR_TACMP2_Pos       (10U)
+#define HRTIM_BMTRGR_TACMP2_Msk       (0x1UL << HRTIM_BMTRGR_TACMP2_Pos)       /*!< 0x00000400 */
+#define HRTIM_BMTRGR_TACMP2           HRTIM_BMTRGR_TACMP2_Msk                  /*!< Timer A compare 2  */
+#define HRTIM_BMTRGR_TBRST_Pos        (11U)
+#define HRTIM_BMTRGR_TBRST_Msk        (0x1UL << HRTIM_BMTRGR_TBRST_Pos)        /*!< 0x00000800 */
+#define HRTIM_BMTRGR_TBRST            HRTIM_BMTRGR_TBRST_Msk                   /*!< Timer B reset  */
+#define HRTIM_BMTRGR_TBREP_Pos        (12U)
+#define HRTIM_BMTRGR_TBREP_Msk        (0x1UL << HRTIM_BMTRGR_TBREP_Pos)        /*!< 0x00001000 */
+#define HRTIM_BMTRGR_TBREP            HRTIM_BMTRGR_TBREP_Msk                   /*!< Timer B repetition  */
+#define HRTIM_BMTRGR_TBCMP1_Pos       (13U)
+#define HRTIM_BMTRGR_TBCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TBCMP1_Pos)       /*!< 0x00002000 */
+#define HRTIM_BMTRGR_TBCMP1           HRTIM_BMTRGR_TBCMP1_Msk                  /*!< Timer B compare 1 */
+#define HRTIM_BMTRGR_TBCMP2_Pos       (14U)
+#define HRTIM_BMTRGR_TBCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TBCMP2_Pos)       /*!< 0x00004000 */
+#define HRTIM_BMTRGR_TBCMP2           HRTIM_BMTRGR_TBCMP2_Msk                  /*!< Timer B compare 2 */
+#define HRTIM_BMTRGR_TCRST_Pos        (15U)
+#define HRTIM_BMTRGR_TCRST_Msk        (0x1UL << HRTIM_BMTRGR_TCRST_Pos)        /*!< 0x00008000 */
+#define HRTIM_BMTRGR_TCRST            HRTIM_BMTRGR_TCRST_Msk                   /*!< Timer C reset  */
+#define HRTIM_BMTRGR_TCREP_Pos        (16U)
+#define HRTIM_BMTRGR_TCREP_Msk        (0x1UL << HRTIM_BMTRGR_TCREP_Pos)        /*!< 0x00010000 */
+#define HRTIM_BMTRGR_TCREP            HRTIM_BMTRGR_TCREP_Msk                   /*!< Timer C repetition */
+#define HRTIM_BMTRGR_TCCMP1_Pos       (17U)
+#define HRTIM_BMTRGR_TCCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TCCMP1_Pos)       /*!< 0x00020000 */
+#define HRTIM_BMTRGR_TCCMP1           HRTIM_BMTRGR_TCCMP1_Msk                  /*!< Timer C compare 1 */
+#define HRTIM_BMTRGR_TCCMP2_Pos       (18U)
+#define HRTIM_BMTRGR_TCCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TCCMP2_Pos)       /*!< 0x00040000 */
+#define HRTIM_BMTRGR_TCCMP2           HRTIM_BMTRGR_TCCMP2_Msk                  /*!< Timer C compare 2 */
+#define HRTIM_BMTRGR_TDRST_Pos        (19U)
+#define HRTIM_BMTRGR_TDRST_Msk        (0x1UL << HRTIM_BMTRGR_TDRST_Pos)        /*!< 0x00080000 */
+#define HRTIM_BMTRGR_TDRST            HRTIM_BMTRGR_TDRST_Msk                   /*!< Timer D reset  */
+#define HRTIM_BMTRGR_TDREP_Pos        (20U)
+#define HRTIM_BMTRGR_TDREP_Msk        (0x1UL << HRTIM_BMTRGR_TDREP_Pos)        /*!< 0x00100000 */
+#define HRTIM_BMTRGR_TDREP            HRTIM_BMTRGR_TDREP_Msk                   /*!< Timer D repetition  */
+#define HRTIM_BMTRGR_TDCMP1_Pos       (21U)
+#define HRTIM_BMTRGR_TDCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TDCMP1_Pos)       /*!< 0x00200000 */
+#define HRTIM_BMTRGR_TDCMP1           HRTIM_BMTRGR_TDCMP1_Msk                  /*!< Timer D compare 1 */
+#define HRTIM_BMTRGR_TDCMP2_Pos       (22U)
+#define HRTIM_BMTRGR_TDCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TDCMP2_Pos)       /*!< 0x00400000 */
+#define HRTIM_BMTRGR_TDCMP2           HRTIM_BMTRGR_TDCMP2_Msk                  /*!< Timer D compare 2 */
+#define HRTIM_BMTRGR_TERST_Pos        (23U)
+#define HRTIM_BMTRGR_TERST_Msk        (0x1UL << HRTIM_BMTRGR_TERST_Pos)        /*!< 0x00800000 */
+#define HRTIM_BMTRGR_TERST            HRTIM_BMTRGR_TERST_Msk                   /*!< Timer E reset  */
+#define HRTIM_BMTRGR_TEREP_Pos        (24U)
+#define HRTIM_BMTRGR_TEREP_Msk        (0x1UL << HRTIM_BMTRGR_TEREP_Pos)        /*!< 0x01000000 */
+#define HRTIM_BMTRGR_TEREP            HRTIM_BMTRGR_TEREP_Msk                   /*!< Timer E repetition  */
+#define HRTIM_BMTRGR_TECMP1_Pos       (25U)
+#define HRTIM_BMTRGR_TECMP1_Msk       (0x1UL << HRTIM_BMTRGR_TECMP1_Pos)       /*!< 0x02000000 */
+#define HRTIM_BMTRGR_TECMP1           HRTIM_BMTRGR_TECMP1_Msk                  /*!< Timer E compare 1 */
+#define HRTIM_BMTRGR_TECMP2_Pos       (26U)
+#define HRTIM_BMTRGR_TECMP2_Msk       (0x1UL << HRTIM_BMTRGR_TECMP2_Pos)       /*!< 0x04000000 */
+#define HRTIM_BMTRGR_TECMP2           HRTIM_BMTRGR_TECMP2_Msk                  /*!< Timer E compare 2 */
+#define HRTIM_BMTRGR_TAEEV7_Pos       (27U)
+#define HRTIM_BMTRGR_TAEEV7_Msk       (0x1UL << HRTIM_BMTRGR_TAEEV7_Pos)       /*!< 0x08000000 */
+#define HRTIM_BMTRGR_TAEEV7           HRTIM_BMTRGR_TAEEV7_Msk                  /*!< Timer A period following External Event7  */
+#define HRTIM_BMTRGR_TDEEV8_Pos       (28U)
+#define HRTIM_BMTRGR_TDEEV8_Msk       (0x1UL << HRTIM_BMTRGR_TDEEV8_Pos)       /*!< 0x10000000 */
+#define HRTIM_BMTRGR_TDEEV8           HRTIM_BMTRGR_TDEEV8_Msk                  /*!< Timer D period following External Event8  */
+#define HRTIM_BMTRGR_EEV7_Pos         (29U)
+#define HRTIM_BMTRGR_EEV7_Msk         (0x1UL << HRTIM_BMTRGR_EEV7_Pos)         /*!< 0x20000000 */
+#define HRTIM_BMTRGR_EEV7             HRTIM_BMTRGR_EEV7_Msk                    /*!< External Event 7 */
+#define HRTIM_BMTRGR_EEV8_Pos         (30U)
+#define HRTIM_BMTRGR_EEV8_Msk         (0x1UL << HRTIM_BMTRGR_EEV8_Pos)         /*!< 0x40000000 */
+#define HRTIM_BMTRGR_EEV8             HRTIM_BMTRGR_EEV8_Msk                    /*!< External Event 8 */
+#define HRTIM_BMTRGR_OCHPEV_Pos       (31U)
+#define HRTIM_BMTRGR_OCHPEV_Msk       (0x1UL << HRTIM_BMTRGR_OCHPEV_Pos)       /*!< 0x80000000 */
+#define HRTIM_BMTRGR_OCHPEV           HRTIM_BMTRGR_OCHPEV_Msk                  /*!< on-chip Event */
+
+/*******************  Bit definition for HRTIM_BMCMPR register  ***************/
+#define HRTIM_BMCMPR_BMCMPR_Pos       (0U)
+#define HRTIM_BMCMPR_BMCMPR_Msk       (0xFFFFUL << HRTIM_BMCMPR_BMCMPR_Pos)    /*!< 0x0000FFFF */
+#define HRTIM_BMCMPR_BMCMPR           HRTIM_BMCMPR_BMCMPR_Msk                  /*!<!<Burst Compare Value */
+
+/*******************  Bit definition for HRTIM_BMPER register  ****************/
+#define HRTIM_BMPER_BMPER_Pos         (0U)
+#define HRTIM_BMPER_BMPER_Msk         (0xFFFFUL << HRTIM_BMPER_BMPER_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_BMPER_BMPER             HRTIM_BMPER_BMPER_Msk                    /*!<!<Burst period Value */
+
+/*******************  Bit definition for HRTIM_EECR1 register  ****************/
+#define HRTIM_EECR1_EE1SRC_Pos        (0U)
+#define HRTIM_EECR1_EE1SRC_Msk        (0x3UL << HRTIM_EECR1_EE1SRC_Pos)        /*!< 0x00000003 */
+#define HRTIM_EECR1_EE1SRC            HRTIM_EECR1_EE1SRC_Msk                   /*!< External event 1 source */
+#define HRTIM_EECR1_EE1SRC_0          (0x1UL << HRTIM_EECR1_EE1SRC_Pos)         /*!< 0x00000001 */
+#define HRTIM_EECR1_EE1SRC_1          (0x2UL << HRTIM_EECR1_EE1SRC_Pos)         /*!< 0x00000002 */
+#define HRTIM_EECR1_EE1POL_Pos        (2U)
+#define HRTIM_EECR1_EE1POL_Msk        (0x1UL << HRTIM_EECR1_EE1POL_Pos)        /*!< 0x00000004 */
+#define HRTIM_EECR1_EE1POL            HRTIM_EECR1_EE1POL_Msk                   /*!< External event 1 Polarity */
+#define HRTIM_EECR1_EE1SNS_Pos        (3U)
+#define HRTIM_EECR1_EE1SNS_Msk        (0x3UL << HRTIM_EECR1_EE1SNS_Pos)        /*!< 0x00000018 */
+#define HRTIM_EECR1_EE1SNS            HRTIM_EECR1_EE1SNS_Msk                   /*!< External event 1 sensitivity */
+#define HRTIM_EECR1_EE1SNS_0          (0x1UL << HRTIM_EECR1_EE1SNS_Pos)         /*!< 0x00000008 */
+#define HRTIM_EECR1_EE1SNS_1          (0x2UL << HRTIM_EECR1_EE1SNS_Pos)         /*!< 0x00000010 */
+#define HRTIM_EECR1_EE1FAST_Pos       (5U)
+#define HRTIM_EECR1_EE1FAST_Msk       (0x1UL << HRTIM_EECR1_EE1FAST_Pos)       /*!< 0x00000020 */
+#define HRTIM_EECR1_EE1FAST           HRTIM_EECR1_EE1FAST_Msk                  /*!< External event 1 Fast mode */
+
+#define HRTIM_EECR1_EE2SRC_Pos        (6U)
+#define HRTIM_EECR1_EE2SRC_Msk        (0x3UL << HRTIM_EECR1_EE2SRC_Pos)        /*!< 0x000000C0 */
+#define HRTIM_EECR1_EE2SRC            HRTIM_EECR1_EE2SRC_Msk                   /*!< External event 2 source */
+#define HRTIM_EECR1_EE2SRC_0          (0x1UL << HRTIM_EECR1_EE2SRC_Pos)         /*!< 0x00000040 */
+#define HRTIM_EECR1_EE2SRC_1          (0x2UL << HRTIM_EECR1_EE2SRC_Pos)         /*!< 0x00000080 */
+#define HRTIM_EECR1_EE2POL_Pos        (8U)
+#define HRTIM_EECR1_EE2POL_Msk        (0x1UL << HRTIM_EECR1_EE2POL_Pos)        /*!< 0x00000100 */
+#define HRTIM_EECR1_EE2POL            HRTIM_EECR1_EE2POL_Msk                   /*!< External event 2 Polarity */
+#define HRTIM_EECR1_EE2SNS_Pos        (9U)
+#define HRTIM_EECR1_EE2SNS_Msk        (0x3UL << HRTIM_EECR1_EE2SNS_Pos)        /*!< 0x00000600 */
+#define HRTIM_EECR1_EE2SNS            HRTIM_EECR1_EE2SNS_Msk                   /*!< External event 2 sensitivity */
+#define HRTIM_EECR1_EE2SNS_0          (0x1UL << HRTIM_EECR1_EE2SNS_Pos)         /*!< 0x00000200 */
+#define HRTIM_EECR1_EE2SNS_1          (0x2UL << HRTIM_EECR1_EE2SNS_Pos)         /*!< 0x00000400 */
+#define HRTIM_EECR1_EE2FAST_Pos       (11U)
+#define HRTIM_EECR1_EE2FAST_Msk       (0x1UL << HRTIM_EECR1_EE2FAST_Pos)       /*!< 0x00000800 */
+#define HRTIM_EECR1_EE2FAST           HRTIM_EECR1_EE2FAST_Msk                  /*!< External event 2 Fast mode */
+
+#define HRTIM_EECR1_EE3SRC_Pos        (12U)
+#define HRTIM_EECR1_EE3SRC_Msk        (0x3UL << HRTIM_EECR1_EE3SRC_Pos)        /*!< 0x00003000 */
+#define HRTIM_EECR1_EE3SRC            HRTIM_EECR1_EE3SRC_Msk                   /*!< External event 3 source */
+#define HRTIM_EECR1_EE3SRC_0          (0x1UL << HRTIM_EECR1_EE3SRC_Pos)         /*!< 0x00001000 */
+#define HRTIM_EECR1_EE3SRC_1          (0x2UL << HRTIM_EECR1_EE3SRC_Pos)         /*!< 0x00002000 */
+#define HRTIM_EECR1_EE3POL_Pos        (14U)
+#define HRTIM_EECR1_EE3POL_Msk        (0x1UL << HRTIM_EECR1_EE3POL_Pos)        /*!< 0x00004000 */
+#define HRTIM_EECR1_EE3POL            HRTIM_EECR1_EE3POL_Msk                   /*!< External event 3 Polarity */
+#define HRTIM_EECR1_EE3SNS_Pos        (15U)
+#define HRTIM_EECR1_EE3SNS_Msk        (0x3UL << HRTIM_EECR1_EE3SNS_Pos)        /*!< 0x00018000 */
+#define HRTIM_EECR1_EE3SNS            HRTIM_EECR1_EE3SNS_Msk                   /*!< External event 3 sensitivity */
+#define HRTIM_EECR1_EE3SNS_0          (0x1UL << HRTIM_EECR1_EE3SNS_Pos)         /*!< 0x00008000 */
+#define HRTIM_EECR1_EE3SNS_1          (0x2UL << HRTIM_EECR1_EE3SNS_Pos)         /*!< 0x00010000 */
+#define HRTIM_EECR1_EE3FAST_Pos       (17U)
+#define HRTIM_EECR1_EE3FAST_Msk       (0x1UL << HRTIM_EECR1_EE3FAST_Pos)       /*!< 0x00020000 */
+#define HRTIM_EECR1_EE3FAST           HRTIM_EECR1_EE3FAST_Msk                  /*!< External event 3 Fast mode */
+
+#define HRTIM_EECR1_EE4SRC_Pos        (18U)
+#define HRTIM_EECR1_EE4SRC_Msk        (0x3UL << HRTIM_EECR1_EE4SRC_Pos)        /*!< 0x000C0000 */
+#define HRTIM_EECR1_EE4SRC            HRTIM_EECR1_EE4SRC_Msk                   /*!< External event 4 source */
+#define HRTIM_EECR1_EE4SRC_0          (0x1UL << HRTIM_EECR1_EE4SRC_Pos)         /*!< 0x00040000 */
+#define HRTIM_EECR1_EE4SRC_1          (0x2UL << HRTIM_EECR1_EE4SRC_Pos)         /*!< 0x00080000 */
+#define HRTIM_EECR1_EE4POL_Pos        (20U)
+#define HRTIM_EECR1_EE4POL_Msk        (0x1UL << HRTIM_EECR1_EE4POL_Pos)        /*!< 0x00100000 */
+#define HRTIM_EECR1_EE4POL            HRTIM_EECR1_EE4POL_Msk                   /*!< External event 4 Polarity */
+#define HRTIM_EECR1_EE4SNS_Pos        (21U)
+#define HRTIM_EECR1_EE4SNS_Msk        (0x3UL << HRTIM_EECR1_EE4SNS_Pos)        /*!< 0x00600000 */
+#define HRTIM_EECR1_EE4SNS            HRTIM_EECR1_EE4SNS_Msk                   /*!< External event 4 sensitivity */
+#define HRTIM_EECR1_EE4SNS_0          (0x1UL << HRTIM_EECR1_EE4SNS_Pos)         /*!< 0x00200000 */
+#define HRTIM_EECR1_EE4SNS_1          (0x2UL << HRTIM_EECR1_EE4SNS_Pos)         /*!< 0x00400000 */
+#define HRTIM_EECR1_EE4FAST_Pos       (23U)
+#define HRTIM_EECR1_EE4FAST_Msk       (0x1UL << HRTIM_EECR1_EE4FAST_Pos)       /*!< 0x00800000 */
+#define HRTIM_EECR1_EE4FAST           HRTIM_EECR1_EE4FAST_Msk                  /*!< External event 4 Fast mode */
+
+#define HRTIM_EECR1_EE5SRC_Pos        (24U)
+#define HRTIM_EECR1_EE5SRC_Msk        (0x3UL << HRTIM_EECR1_EE5SRC_Pos)        /*!< 0x03000000 */
+#define HRTIM_EECR1_EE5SRC            HRTIM_EECR1_EE5SRC_Msk                   /*!< External event 5 source */
+#define HRTIM_EECR1_EE5SRC_0          (0x1UL << HRTIM_EECR1_EE5SRC_Pos)         /*!< 0x01000000 */
+#define HRTIM_EECR1_EE5SRC_1          (0x2UL << HRTIM_EECR1_EE5SRC_Pos)         /*!< 0x02000000 */
+#define HRTIM_EECR1_EE5POL_Pos        (26U)
+#define HRTIM_EECR1_EE5POL_Msk        (0x1UL << HRTIM_EECR1_EE5POL_Pos)        /*!< 0x04000000 */
+#define HRTIM_EECR1_EE5POL            HRTIM_EECR1_EE5POL_Msk                   /*!< External event 5 Polarity */
+#define HRTIM_EECR1_EE5SNS_Pos        (27U)
+#define HRTIM_EECR1_EE5SNS_Msk        (0x3UL << HRTIM_EECR1_EE5SNS_Pos)        /*!< 0x18000000 */
+#define HRTIM_EECR1_EE5SNS            HRTIM_EECR1_EE5SNS_Msk                   /*!< External event 5 sensitivity */
+#define HRTIM_EECR1_EE5SNS_0          (0x1UL << HRTIM_EECR1_EE5SNS_Pos)         /*!< 0x08000000 */
+#define HRTIM_EECR1_EE5SNS_1          (0x2UL << HRTIM_EECR1_EE5SNS_Pos)         /*!< 0x10000000 */
+#define HRTIM_EECR1_EE5FAST_Pos       (29U)
+#define HRTIM_EECR1_EE5FAST_Msk       (0x1UL << HRTIM_EECR1_EE5FAST_Pos)       /*!< 0x20000000 */
+#define HRTIM_EECR1_EE5FAST           HRTIM_EECR1_EE5FAST_Msk                  /*!< External event 5 Fast mode */
+
+/*******************  Bit definition for HRTIM_EECR2 register  ****************/
+#define HRTIM_EECR2_EE6SRC_Pos        (0U)
+#define HRTIM_EECR2_EE6SRC_Msk        (0x3UL << HRTIM_EECR2_EE6SRC_Pos)        /*!< 0x00000003 */
+#define HRTIM_EECR2_EE6SRC            HRTIM_EECR2_EE6SRC_Msk                   /*!< External event 6 source */
+#define HRTIM_EECR2_EE6SRC_0          (0x1UL << HRTIM_EECR2_EE6SRC_Pos)         /*!< 0x00000001 */
+#define HRTIM_EECR2_EE6SRC_1          (0x2UL << HRTIM_EECR2_EE6SRC_Pos)         /*!< 0x00000002 */
+#define HRTIM_EECR2_EE6POL_Pos        (2U)
+#define HRTIM_EECR2_EE6POL_Msk        (0x1UL << HRTIM_EECR2_EE6POL_Pos)        /*!< 0x00000004 */
+#define HRTIM_EECR2_EE6POL            HRTIM_EECR2_EE6POL_Msk                   /*!< External event 6 Polarity */
+#define HRTIM_EECR2_EE6SNS_Pos        (3U)
+#define HRTIM_EECR2_EE6SNS_Msk        (0x3UL << HRTIM_EECR2_EE6SNS_Pos)        /*!< 0x00000018 */
+#define HRTIM_EECR2_EE6SNS            HRTIM_EECR2_EE6SNS_Msk                   /*!< External event 6 sensitivity */
+#define HRTIM_EECR2_EE6SNS_0          (0x1UL << HRTIM_EECR2_EE6SNS_Pos)         /*!< 0x00000008 */
+#define HRTIM_EECR2_EE6SNS_1          (0x2UL << HRTIM_EECR2_EE6SNS_Pos)         /*!< 0x00000010 */
+
+#define HRTIM_EECR2_EE7SRC_Pos        (6U)
+#define HRTIM_EECR2_EE7SRC_Msk        (0x3UL << HRTIM_EECR2_EE7SRC_Pos)        /*!< 0x000000C0 */
+#define HRTIM_EECR2_EE7SRC            HRTIM_EECR2_EE7SRC_Msk                   /*!< External event 7 source */
+#define HRTIM_EECR2_EE7SRC_0          (0x1UL << HRTIM_EECR2_EE7SRC_Pos)         /*!< 0x00000040 */
+#define HRTIM_EECR2_EE7SRC_1          (0x2UL << HRTIM_EECR2_EE7SRC_Pos)         /*!< 0x00000080 */
+#define HRTIM_EECR2_EE7POL_Pos        (8U)
+#define HRTIM_EECR2_EE7POL_Msk        (0x1UL << HRTIM_EECR2_EE7POL_Pos)        /*!< 0x00000100 */
+#define HRTIM_EECR2_EE7POL            HRTIM_EECR2_EE7POL_Msk                   /*!< External event 7 Polarity */
+#define HRTIM_EECR2_EE7SNS_Pos        (9U)
+#define HRTIM_EECR2_EE7SNS_Msk        (0x3UL << HRTIM_EECR2_EE7SNS_Pos)        /*!< 0x00000600 */
+#define HRTIM_EECR2_EE7SNS            HRTIM_EECR2_EE7SNS_Msk                   /*!< External event 7 sensitivity */
+#define HRTIM_EECR2_EE7SNS_0          (0x1UL << HRTIM_EECR2_EE7SNS_Pos)         /*!< 0x00000200 */
+#define HRTIM_EECR2_EE7SNS_1          (0x2UL << HRTIM_EECR2_EE7SNS_Pos)         /*!< 0x00000400 */
+
+#define HRTIM_EECR2_EE8SRC_Pos        (12U)
+#define HRTIM_EECR2_EE8SRC_Msk        (0x3UL << HRTIM_EECR2_EE8SRC_Pos)        /*!< 0x00003000 */
+#define HRTIM_EECR2_EE8SRC            HRTIM_EECR2_EE8SRC_Msk                   /*!< External event 8 source */
+#define HRTIM_EECR2_EE8SRC_0          (0x1UL << HRTIM_EECR2_EE8SRC_Pos)         /*!< 0x00001000 */
+#define HRTIM_EECR2_EE8SRC_1          (0x2UL << HRTIM_EECR2_EE8SRC_Pos)         /*!< 0x00002000 */
+#define HRTIM_EECR2_EE8POL_Pos        (14U)
+#define HRTIM_EECR2_EE8POL_Msk        (0x1UL << HRTIM_EECR2_EE8POL_Pos)        /*!< 0x00004000 */
+#define HRTIM_EECR2_EE8POL            HRTIM_EECR2_EE8POL_Msk                   /*!< External event 8 Polarity */
+#define HRTIM_EECR2_EE8SNS_Pos        (15U)
+#define HRTIM_EECR2_EE8SNS_Msk        (0x3UL << HRTIM_EECR2_EE8SNS_Pos)        /*!< 0x00018000 */
+#define HRTIM_EECR2_EE8SNS            HRTIM_EECR2_EE8SNS_Msk                   /*!< External event 8 sensitivity */
+#define HRTIM_EECR2_EE8SNS_0          (0x1UL << HRTIM_EECR2_EE8SNS_Pos)         /*!< 0x00008000 */
+#define HRTIM_EECR2_EE8SNS_1          (0x2UL << HRTIM_EECR2_EE8SNS_Pos)         /*!< 0x00010000 */
+
+#define HRTIM_EECR2_EE9SRC_Pos        (18U)
+#define HRTIM_EECR2_EE9SRC_Msk        (0x3UL << HRTIM_EECR2_EE9SRC_Pos)        /*!< 0x000C0000 */
+#define HRTIM_EECR2_EE9SRC            HRTIM_EECR2_EE9SRC_Msk                   /*!< External event 9 source */
+#define HRTIM_EECR2_EE9SRC_0          (0x1UL << HRTIM_EECR2_EE9SRC_Pos)         /*!< 0x00040000 */
+#define HRTIM_EECR2_EE9SRC_1          (0x2UL << HRTIM_EECR2_EE9SRC_Pos)         /*!< 0x00080000 */
+#define HRTIM_EECR2_EE9POL_Pos        (20U)
+#define HRTIM_EECR2_EE9POL_Msk        (0x1UL << HRTIM_EECR2_EE9POL_Pos)        /*!< 0x00100000 */
+#define HRTIM_EECR2_EE9POL            HRTIM_EECR2_EE9POL_Msk                   /*!< External event 9 Polarity */
+#define HRTIM_EECR2_EE9SNS_Pos        (21U)
+#define HRTIM_EECR2_EE9SNS_Msk        (0x3UL << HRTIM_EECR2_EE9SNS_Pos)        /*!< 0x00600000 */
+#define HRTIM_EECR2_EE9SNS            HRTIM_EECR2_EE9SNS_Msk                   /*!< External event 9 sensitivity */
+#define HRTIM_EECR2_EE9SNS_0          (0x1UL << HRTIM_EECR2_EE9SNS_Pos)         /*!< 0x00200000 */
+#define HRTIM_EECR2_EE9SNS_1          (0x2UL << HRTIM_EECR2_EE9SNS_Pos)         /*!< 0x00400000 */
+
+#define HRTIM_EECR2_EE10SRC_Pos       (24U)
+#define HRTIM_EECR2_EE10SRC_Msk       (0x3UL << HRTIM_EECR2_EE10SRC_Pos)       /*!< 0x03000000 */
+#define HRTIM_EECR2_EE10SRC           HRTIM_EECR2_EE10SRC_Msk                  /*!< External event 10 source */
+#define HRTIM_EECR2_EE10SRC_0         (0x1UL << HRTIM_EECR2_EE10SRC_Pos)        /*!< 0x01000000 */
+#define HRTIM_EECR2_EE10SRC_1         (0x2UL << HRTIM_EECR2_EE10SRC_Pos)        /*!< 0x02000000 */
+#define HRTIM_EECR2_EE10POL_Pos       (26U)
+#define HRTIM_EECR2_EE10POL_Msk       (0x1UL << HRTIM_EECR2_EE10POL_Pos)       /*!< 0x04000000 */
+#define HRTIM_EECR2_EE10POL           HRTIM_EECR2_EE10POL_Msk                  /*!< External event 10 Polarity */
+#define HRTIM_EECR2_EE10SNS_Pos       (27U)
+#define HRTIM_EECR2_EE10SNS_Msk       (0x3UL << HRTIM_EECR2_EE10SNS_Pos)       /*!< 0x18000000 */
+#define HRTIM_EECR2_EE10SNS           HRTIM_EECR2_EE10SNS_Msk                  /*!< External event 10 sensitivity */
+#define HRTIM_EECR2_EE10SNS_0         (0x1UL << HRTIM_EECR2_EE10SNS_Pos)        /*!< 0x08000000 */
+#define HRTIM_EECR2_EE10SNS_1         (0x2UL << HRTIM_EECR2_EE10SNS_Pos)        /*!< 0x10000000 */
+
+/*******************  Bit definition for HRTIM_EECR3 register  ****************/
+#define HRTIM_EECR3_EE6F_Pos          (0U)
+#define HRTIM_EECR3_EE6F_Msk          (0xFUL << HRTIM_EECR3_EE6F_Pos)          /*!< 0x0000000F */
+#define HRTIM_EECR3_EE6F              HRTIM_EECR3_EE6F_Msk                     /*!< External event 6 filter */
+#define HRTIM_EECR3_EE6F_0            (0x1UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000001 */
+#define HRTIM_EECR3_EE6F_1            (0x2UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000002 */
+#define HRTIM_EECR3_EE6F_2            (0x4UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000004 */
+#define HRTIM_EECR3_EE6F_3            (0x8UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000008 */
+#define HRTIM_EECR3_EE7F_Pos          (6U)
+#define HRTIM_EECR3_EE7F_Msk          (0xFUL << HRTIM_EECR3_EE7F_Pos)          /*!< 0x000003C0 */
+#define HRTIM_EECR3_EE7F              HRTIM_EECR3_EE7F_Msk                     /*!< External event 7 filter */
+#define HRTIM_EECR3_EE7F_0            (0x1UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000040 */
+#define HRTIM_EECR3_EE7F_1            (0x2UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000080 */
+#define HRTIM_EECR3_EE7F_2            (0x4UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000100 */
+#define HRTIM_EECR3_EE7F_3            (0x8UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000200 */
+#define HRTIM_EECR3_EE8F_Pos          (12U)
+#define HRTIM_EECR3_EE8F_Msk          (0xFUL << HRTIM_EECR3_EE8F_Pos)          /*!< 0x0000F000 */
+#define HRTIM_EECR3_EE8F              HRTIM_EECR3_EE8F_Msk                     /*!< External event 8 filter */
+#define HRTIM_EECR3_EE8F_0            (0x1UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00001000 */
+#define HRTIM_EECR3_EE8F_1            (0x2UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00002000 */
+#define HRTIM_EECR3_EE8F_2            (0x4UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00004000 */
+#define HRTIM_EECR3_EE8F_3            (0x8UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00008000 */
+#define HRTIM_EECR3_EE9F_Pos          (18U)
+#define HRTIM_EECR3_EE9F_Msk          (0xFUL << HRTIM_EECR3_EE9F_Pos)          /*!< 0x003C0000 */
+#define HRTIM_EECR3_EE9F              HRTIM_EECR3_EE9F_Msk                     /*!< External event 9 filter */
+#define HRTIM_EECR3_EE9F_0            (0x1UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00040000 */
+#define HRTIM_EECR3_EE9F_1            (0x2UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00080000 */
+#define HRTIM_EECR3_EE9F_2            (0x4UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00100000 */
+#define HRTIM_EECR3_EE9F_3            (0x8UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00200000 */
+#define HRTIM_EECR3_EE10F_Pos         (24U)
+#define HRTIM_EECR3_EE10F_Msk         (0xFUL << HRTIM_EECR3_EE10F_Pos)         /*!< 0x0F000000 */
+#define HRTIM_EECR3_EE10F             HRTIM_EECR3_EE10F_Msk                    /*!< External event 10 filter */
+#define HRTIM_EECR3_EE10F_0           (0x1UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x01000000 */
+#define HRTIM_EECR3_EE10F_1           (0x2UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x02000000 */
+#define HRTIM_EECR3_EE10F_2           (0x4UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x04000000 */
+#define HRTIM_EECR3_EE10F_3           (0x8UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x08000000 */
+#define HRTIM_EECR3_EEVSD_Pos         (30U)
+#define HRTIM_EECR3_EEVSD_Msk         (0x3UL << HRTIM_EECR3_EEVSD_Pos)         /*!< 0xC0000000 */
+#define HRTIM_EECR3_EEVSD             HRTIM_EECR3_EEVSD_Msk                    /*!< External event sampling clock division */
+#define HRTIM_EECR3_EEVSD_0           (0x1UL << HRTIM_EECR3_EEVSD_Pos)          /*!< 0x40000000 */
+#define HRTIM_EECR3_EEVSD_1           (0x2UL << HRTIM_EECR3_EEVSD_Pos)          /*!< 0x80000000 */
+
+/*******************  Bit definition for HRTIM_ADC1R register  ****************/
+#define HRTIM_ADC1R_AD1MC1_Pos        (0U)
+#define HRTIM_ADC1R_AD1MC1_Msk        (0x1UL << HRTIM_ADC1R_AD1MC1_Pos)        /*!< 0x00000001 */
+#define HRTIM_ADC1R_AD1MC1            HRTIM_ADC1R_AD1MC1_Msk                   /*!< ADC Trigger 1 on master compare 1 */
+#define HRTIM_ADC1R_AD1MC2_Pos        (1U)
+#define HRTIM_ADC1R_AD1MC2_Msk        (0x1UL << HRTIM_ADC1R_AD1MC2_Pos)        /*!< 0x00000002 */
+#define HRTIM_ADC1R_AD1MC2            HRTIM_ADC1R_AD1MC2_Msk                   /*!< ADC Trigger 1 on master compare 2 */
+#define HRTIM_ADC1R_AD1MC3_Pos        (2U)
+#define HRTIM_ADC1R_AD1MC3_Msk        (0x1UL << HRTIM_ADC1R_AD1MC3_Pos)        /*!< 0x00000004 */
+#define HRTIM_ADC1R_AD1MC3            HRTIM_ADC1R_AD1MC3_Msk                   /*!< ADC Trigger 1 on master compare 3 */
+#define HRTIM_ADC1R_AD1MC4_Pos        (3U)
+#define HRTIM_ADC1R_AD1MC4_Msk        (0x1UL << HRTIM_ADC1R_AD1MC4_Pos)        /*!< 0x00000008 */
+#define HRTIM_ADC1R_AD1MC4            HRTIM_ADC1R_AD1MC4_Msk                   /*!< ADC Trigger 1 on master compare 4 */
+#define HRTIM_ADC1R_AD1MPER_Pos       (4U)
+#define HRTIM_ADC1R_AD1MPER_Msk       (0x1UL << HRTIM_ADC1R_AD1MPER_Pos)       /*!< 0x00000010 */
+#define HRTIM_ADC1R_AD1MPER           HRTIM_ADC1R_AD1MPER_Msk                  /*!< ADC Trigger 1 on master period */
+#define HRTIM_ADC1R_AD1EEV1_Pos       (5U)
+#define HRTIM_ADC1R_AD1EEV1_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV1_Pos)       /*!< 0x00000020 */
+#define HRTIM_ADC1R_AD1EEV1           HRTIM_ADC1R_AD1EEV1_Msk                  /*!< ADC Trigger 1 on external event 1 */
+#define HRTIM_ADC1R_AD1EEV2_Pos       (6U)
+#define HRTIM_ADC1R_AD1EEV2_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV2_Pos)       /*!< 0x00000040 */
+#define HRTIM_ADC1R_AD1EEV2           HRTIM_ADC1R_AD1EEV2_Msk                  /*!< ADC Trigger 1 on external event 2 */
+#define HRTIM_ADC1R_AD1EEV3_Pos       (7U)
+#define HRTIM_ADC1R_AD1EEV3_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV3_Pos)       /*!< 0x00000080 */
+#define HRTIM_ADC1R_AD1EEV3           HRTIM_ADC1R_AD1EEV3_Msk                  /*!< ADC Trigger 1 on external event 3 */
+#define HRTIM_ADC1R_AD1EEV4_Pos       (8U)
+#define HRTIM_ADC1R_AD1EEV4_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV4_Pos)       /*!< 0x00000100 */
+#define HRTIM_ADC1R_AD1EEV4           HRTIM_ADC1R_AD1EEV4_Msk                  /*!< ADC Trigger 1 on external event 4 */
+#define HRTIM_ADC1R_AD1EEV5_Pos       (9U)
+#define HRTIM_ADC1R_AD1EEV5_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV5_Pos)       /*!< 0x00000200 */
+#define HRTIM_ADC1R_AD1EEV5           HRTIM_ADC1R_AD1EEV5_Msk                  /*!< ADC Trigger 1 on external event 5 */
+#define HRTIM_ADC1R_AD1TAC2_Pos       (10U)
+#define HRTIM_ADC1R_AD1TAC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC2_Pos)       /*!< 0x00000400 */
+#define HRTIM_ADC1R_AD1TAC2           HRTIM_ADC1R_AD1TAC2_Msk                  /*!< ADC Trigger 1 on Timer A compare 2 */
+#define HRTIM_ADC1R_AD1TAC3_Pos       (11U)
+#define HRTIM_ADC1R_AD1TAC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC3_Pos)       /*!< 0x00000800 */
+#define HRTIM_ADC1R_AD1TAC3           HRTIM_ADC1R_AD1TAC3_Msk                  /*!< ADC Trigger 1 on Timer A compare 3 */
+#define HRTIM_ADC1R_AD1TAC4_Pos       (12U)
+#define HRTIM_ADC1R_AD1TAC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC4_Pos)       /*!< 0x00001000 */
+#define HRTIM_ADC1R_AD1TAC4           HRTIM_ADC1R_AD1TAC4_Msk                  /*!< ADC Trigger 1 on Timer A compare 4 */
+#define HRTIM_ADC1R_AD1TAPER_Pos      (13U)
+#define HRTIM_ADC1R_AD1TAPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TAPER_Pos)      /*!< 0x00002000 */
+#define HRTIM_ADC1R_AD1TAPER          HRTIM_ADC1R_AD1TAPER_Msk                 /*!< ADC Trigger 1 on Timer A period */
+#define HRTIM_ADC1R_AD1TARST_Pos      (14U)
+#define HRTIM_ADC1R_AD1TARST_Msk      (0x1UL << HRTIM_ADC1R_AD1TARST_Pos)      /*!< 0x00004000 */
+#define HRTIM_ADC1R_AD1TARST          HRTIM_ADC1R_AD1TARST_Msk                 /*!< ADC Trigger 1 on Timer A reset */
+#define HRTIM_ADC1R_AD1TBC2_Pos       (15U)
+#define HRTIM_ADC1R_AD1TBC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC2_Pos)       /*!< 0x00008000 */
+#define HRTIM_ADC1R_AD1TBC2           HRTIM_ADC1R_AD1TBC2_Msk                  /*!< ADC Trigger 1 on Timer B compare 2 */
+#define HRTIM_ADC1R_AD1TBC3_Pos       (16U)
+#define HRTIM_ADC1R_AD1TBC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC3_Pos)       /*!< 0x00010000 */
+#define HRTIM_ADC1R_AD1TBC3           HRTIM_ADC1R_AD1TBC3_Msk                  /*!< ADC Trigger 1 on Timer B compare 3 */
+#define HRTIM_ADC1R_AD1TBC4_Pos       (17U)
+#define HRTIM_ADC1R_AD1TBC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC4_Pos)       /*!< 0x00020000 */
+#define HRTIM_ADC1R_AD1TBC4           HRTIM_ADC1R_AD1TBC4_Msk                  /*!< ADC Trigger 1 on Timer B compare 4 */
+#define HRTIM_ADC1R_AD1TBPER_Pos      (18U)
+#define HRTIM_ADC1R_AD1TBPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TBPER_Pos)      /*!< 0x00040000 */
+#define HRTIM_ADC1R_AD1TBPER          HRTIM_ADC1R_AD1TBPER_Msk                 /*!< ADC Trigger 1 on Timer B period */
+#define HRTIM_ADC1R_AD1TBRST_Pos      (19U)
+#define HRTIM_ADC1R_AD1TBRST_Msk      (0x1UL << HRTIM_ADC1R_AD1TBRST_Pos)      /*!< 0x00080000 */
+#define HRTIM_ADC1R_AD1TBRST          HRTIM_ADC1R_AD1TBRST_Msk                 /*!< ADC Trigger 1 on Timer B reset */
+#define HRTIM_ADC1R_AD1TCC2_Pos       (20U)
+#define HRTIM_ADC1R_AD1TCC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC2_Pos)       /*!< 0x00100000 */
+#define HRTIM_ADC1R_AD1TCC2           HRTIM_ADC1R_AD1TCC2_Msk                  /*!< ADC Trigger 1 on Timer C compare 2 */
+#define HRTIM_ADC1R_AD1TCC3_Pos       (21U)
+#define HRTIM_ADC1R_AD1TCC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC3_Pos)       /*!< 0x00200000 */
+#define HRTIM_ADC1R_AD1TCC3           HRTIM_ADC1R_AD1TCC3_Msk                  /*!< ADC Trigger 1 on Timer C compare 3 */
+#define HRTIM_ADC1R_AD1TCC4_Pos       (22U)
+#define HRTIM_ADC1R_AD1TCC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC4_Pos)       /*!< 0x00400000 */
+#define HRTIM_ADC1R_AD1TCC4           HRTIM_ADC1R_AD1TCC4_Msk                  /*!< ADC Trigger 1 on Timer C compare 4 */
+#define HRTIM_ADC1R_AD1TCPER_Pos      (23U)
+#define HRTIM_ADC1R_AD1TCPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TCPER_Pos)      /*!< 0x00800000 */
+#define HRTIM_ADC1R_AD1TCPER          HRTIM_ADC1R_AD1TCPER_Msk                 /*!< ADC Trigger 1 on Timer C period */
+#define HRTIM_ADC1R_AD1TDC2_Pos       (24U)
+#define HRTIM_ADC1R_AD1TDC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC2_Pos)       /*!< 0x01000000 */
+#define HRTIM_ADC1R_AD1TDC2           HRTIM_ADC1R_AD1TDC2_Msk                  /*!< ADC Trigger 1 on Timer D compare 2 */
+#define HRTIM_ADC1R_AD1TDC3_Pos       (25U)
+#define HRTIM_ADC1R_AD1TDC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC3_Pos)       /*!< 0x02000000 */
+#define HRTIM_ADC1R_AD1TDC3           HRTIM_ADC1R_AD1TDC3_Msk                  /*!< ADC Trigger 1 on Timer D compare 3 */
+#define HRTIM_ADC1R_AD1TDC4_Pos       (26U)
+#define HRTIM_ADC1R_AD1TDC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC4_Pos)       /*!< 0x04000000 */
+#define HRTIM_ADC1R_AD1TDC4           HRTIM_ADC1R_AD1TDC4_Msk                  /*!< ADC Trigger 1 on Timer D compare 4 */
+#define HRTIM_ADC1R_AD1TDPER_Pos      (27U)
+#define HRTIM_ADC1R_AD1TDPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TDPER_Pos)      /*!< 0x08000000 */
+#define HRTIM_ADC1R_AD1TDPER          HRTIM_ADC1R_AD1TDPER_Msk                 /*!< ADC Trigger 1 on Timer D period */
+#define HRTIM_ADC1R_AD1TEC2_Pos       (28U)
+#define HRTIM_ADC1R_AD1TEC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC2_Pos)       /*!< 0x10000000 */
+#define HRTIM_ADC1R_AD1TEC2           HRTIM_ADC1R_AD1TEC2_Msk                  /*!< ADC Trigger 1 on Timer E compare 2 */
+#define HRTIM_ADC1R_AD1TEC3_Pos       (29U)
+#define HRTIM_ADC1R_AD1TEC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC3_Pos)       /*!< 0x20000000 */
+#define HRTIM_ADC1R_AD1TEC3           HRTIM_ADC1R_AD1TEC3_Msk                  /*!< ADC Trigger 1 on Timer E compare 3 */
+#define HRTIM_ADC1R_AD1TEC4_Pos       (30U)
+#define HRTIM_ADC1R_AD1TEC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC4_Pos)       /*!< 0x40000000 */
+#define HRTIM_ADC1R_AD1TEC4           HRTIM_ADC1R_AD1TEC4_Msk                  /*!< ADC Trigger 1 on Timer E compare 4 */
+#define HRTIM_ADC1R_AD1TEPER_Pos      (31U)
+#define HRTIM_ADC1R_AD1TEPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TEPER_Pos)      /*!< 0x80000000 */
+#define HRTIM_ADC1R_AD1TEPER          HRTIM_ADC1R_AD1TEPER_Msk                 /*!< ADC Trigger 1 on Timer E period */
+
+/*******************  Bit definition for HRTIM_ADC2R register  ****************/
+#define HRTIM_ADC2R_AD2MC1_Pos        (0U)
+#define HRTIM_ADC2R_AD2MC1_Msk        (0x1UL << HRTIM_ADC2R_AD2MC1_Pos)        /*!< 0x00000001 */
+#define HRTIM_ADC2R_AD2MC1            HRTIM_ADC2R_AD2MC1_Msk                   /*!< ADC Trigger 2 on master compare 1 */
+#define HRTIM_ADC2R_AD2MC2_Pos        (1U)
+#define HRTIM_ADC2R_AD2MC2_Msk        (0x1UL << HRTIM_ADC2R_AD2MC2_Pos)        /*!< 0x00000002 */
+#define HRTIM_ADC2R_AD2MC2            HRTIM_ADC2R_AD2MC2_Msk                   /*!< ADC Trigger 2 on master compare 2 */
+#define HRTIM_ADC2R_AD2MC3_Pos        (2U)
+#define HRTIM_ADC2R_AD2MC3_Msk        (0x1UL << HRTIM_ADC2R_AD2MC3_Pos)        /*!< 0x00000004 */
+#define HRTIM_ADC2R_AD2MC3            HRTIM_ADC2R_AD2MC3_Msk                   /*!< ADC Trigger 2 on master compare 3 */
+#define HRTIM_ADC2R_AD2MC4_Pos        (3U)
+#define HRTIM_ADC2R_AD2MC4_Msk        (0x1UL << HRTIM_ADC2R_AD2MC4_Pos)        /*!< 0x00000008 */
+#define HRTIM_ADC2R_AD2MC4            HRTIM_ADC2R_AD2MC4_Msk                   /*!< ADC Trigger 2 on master compare 4 */
+#define HRTIM_ADC2R_AD2MPER_Pos       (4U)
+#define HRTIM_ADC2R_AD2MPER_Msk       (0x1UL << HRTIM_ADC2R_AD2MPER_Pos)       /*!< 0x00000010 */
+#define HRTIM_ADC2R_AD2MPER           HRTIM_ADC2R_AD2MPER_Msk                  /*!< ADC Trigger 2 on master period */
+#define HRTIM_ADC2R_AD2EEV6_Pos       (5U)
+#define HRTIM_ADC2R_AD2EEV6_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV6_Pos)       /*!< 0x00000020 */
+#define HRTIM_ADC2R_AD2EEV6           HRTIM_ADC2R_AD2EEV6_Msk                  /*!< ADC Trigger 2 on external event 6 */
+#define HRTIM_ADC2R_AD2EEV7_Pos       (6U)
+#define HRTIM_ADC2R_AD2EEV7_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV7_Pos)       /*!< 0x00000040 */
+#define HRTIM_ADC2R_AD2EEV7           HRTIM_ADC2R_AD2EEV7_Msk                  /*!< ADC Trigger 2 on external event 7 */
+#define HRTIM_ADC2R_AD2EEV8_Pos       (7U)
+#define HRTIM_ADC2R_AD2EEV8_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV8_Pos)       /*!< 0x00000080 */
+#define HRTIM_ADC2R_AD2EEV8           HRTIM_ADC2R_AD2EEV8_Msk                  /*!< ADC Trigger 2 on external event 8 */
+#define HRTIM_ADC2R_AD2EEV9_Pos       (8U)
+#define HRTIM_ADC2R_AD2EEV9_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV9_Pos)       /*!< 0x00000100 */
+#define HRTIM_ADC2R_AD2EEV9           HRTIM_ADC2R_AD2EEV9_Msk                  /*!< ADC Trigger 2 on external event 9 */
+#define HRTIM_ADC2R_AD2EEV10_Pos      (9U)
+#define HRTIM_ADC2R_AD2EEV10_Msk      (0x1UL << HRTIM_ADC2R_AD2EEV10_Pos)      /*!< 0x00000200 */
+#define HRTIM_ADC2R_AD2EEV10          HRTIM_ADC2R_AD2EEV10_Msk                 /*!< ADC Trigger 2 on external event 10 */
+#define HRTIM_ADC2R_AD2TAC2_Pos       (10U)
+#define HRTIM_ADC2R_AD2TAC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC2_Pos)       /*!< 0x00000400 */
+#define HRTIM_ADC2R_AD2TAC2           HRTIM_ADC2R_AD2TAC2_Msk                  /*!< ADC Trigger 2 on Timer A compare 2 */
+#define HRTIM_ADC2R_AD2TAC3_Pos       (11U)
+#define HRTIM_ADC2R_AD2TAC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC3_Pos)       /*!< 0x00000800 */
+#define HRTIM_ADC2R_AD2TAC3           HRTIM_ADC2R_AD2TAC3_Msk                  /*!< ADC Trigger 2 on Timer A compare 3 */
+#define HRTIM_ADC2R_AD2TAC4_Pos       (12U)
+#define HRTIM_ADC2R_AD2TAC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC4_Pos)       /*!< 0x00001000 */
+#define HRTIM_ADC2R_AD2TAC4           HRTIM_ADC2R_AD2TAC4_Msk                  /*!< ADC Trigger 2 on Timer A compare 4*/
+#define HRTIM_ADC2R_AD2TAPER_Pos      (13U)
+#define HRTIM_ADC2R_AD2TAPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TAPER_Pos)      /*!< 0x00002000 */
+#define HRTIM_ADC2R_AD2TAPER          HRTIM_ADC2R_AD2TAPER_Msk                 /*!< ADC Trigger 2 on Timer A period */
+#define HRTIM_ADC2R_AD2TBC2_Pos       (14U)
+#define HRTIM_ADC2R_AD2TBC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC2_Pos)       /*!< 0x00004000 */
+#define HRTIM_ADC2R_AD2TBC2           HRTIM_ADC2R_AD2TBC2_Msk                  /*!< ADC Trigger 2 on Timer B compare 2 */
+#define HRTIM_ADC2R_AD2TBC3_Pos       (15U)
+#define HRTIM_ADC2R_AD2TBC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC3_Pos)       /*!< 0x00008000 */
+#define HRTIM_ADC2R_AD2TBC3           HRTIM_ADC2R_AD2TBC3_Msk                  /*!< ADC Trigger 2 on Timer B compare 3 */
+#define HRTIM_ADC2R_AD2TBC4_Pos       (16U)
+#define HRTIM_ADC2R_AD2TBC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC4_Pos)       /*!< 0x00010000 */
+#define HRTIM_ADC2R_AD2TBC4           HRTIM_ADC2R_AD2TBC4_Msk                  /*!< ADC Trigger 2 on Timer B compare 4 */
+#define HRTIM_ADC2R_AD2TBPER_Pos      (17U)
+#define HRTIM_ADC2R_AD2TBPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TBPER_Pos)      /*!< 0x00020000 */
+#define HRTIM_ADC2R_AD2TBPER          HRTIM_ADC2R_AD2TBPER_Msk                 /*!< ADC Trigger 2 on Timer B period */
+#define HRTIM_ADC2R_AD2TCC2_Pos       (18U)
+#define HRTIM_ADC2R_AD2TCC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC2_Pos)       /*!< 0x00040000 */
+#define HRTIM_ADC2R_AD2TCC2           HRTIM_ADC2R_AD2TCC2_Msk                  /*!< ADC Trigger 2 on Timer C compare 2 */
+#define HRTIM_ADC2R_AD2TCC3_Pos       (19U)
+#define HRTIM_ADC2R_AD2TCC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC3_Pos)       /*!< 0x00080000 */
+#define HRTIM_ADC2R_AD2TCC3           HRTIM_ADC2R_AD2TCC3_Msk                  /*!< ADC Trigger 2 on Timer C compare 3 */
+#define HRTIM_ADC2R_AD2TCC4_Pos       (20U)
+#define HRTIM_ADC2R_AD2TCC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC4_Pos)       /*!< 0x00100000 */
+#define HRTIM_ADC2R_AD2TCC4           HRTIM_ADC2R_AD2TCC4_Msk                  /*!< ADC Trigger 2 on Timer C compare 4 */
+#define HRTIM_ADC2R_AD2TCPER_Pos      (21U)
+#define HRTIM_ADC2R_AD2TCPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TCPER_Pos)      /*!< 0x00200000 */
+#define HRTIM_ADC2R_AD2TCPER          HRTIM_ADC2R_AD2TCPER_Msk                 /*!< ADC Trigger 2 on Timer C period */
+#define HRTIM_ADC2R_AD2TCRST_Pos      (22U)
+#define HRTIM_ADC2R_AD2TCRST_Msk      (0x1UL << HRTIM_ADC2R_AD2TCRST_Pos)      /*!< 0x00400000 */
+#define HRTIM_ADC2R_AD2TCRST          HRTIM_ADC2R_AD2TCRST_Msk                 /*!< ADC Trigger 2 on Timer C reset */
+#define HRTIM_ADC2R_AD2TDC2_Pos       (23U)
+#define HRTIM_ADC2R_AD2TDC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC2_Pos)       /*!< 0x00800000 */
+#define HRTIM_ADC2R_AD2TDC2           HRTIM_ADC2R_AD2TDC2_Msk                  /*!< ADC Trigger 2 on Timer D compare 2 */
+#define HRTIM_ADC2R_AD2TDC3_Pos       (24U)
+#define HRTIM_ADC2R_AD2TDC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC3_Pos)       /*!< 0x01000000 */
+#define HRTIM_ADC2R_AD2TDC3           HRTIM_ADC2R_AD2TDC3_Msk                  /*!< ADC Trigger 2 on Timer D compare 3 */
+#define HRTIM_ADC2R_AD2TDC4_Pos       (25U)
+#define HRTIM_ADC2R_AD2TDC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC4_Pos)       /*!< 0x02000000 */
+#define HRTIM_ADC2R_AD2TDC4           HRTIM_ADC2R_AD2TDC4_Msk                  /*!< ADC Trigger 2 on Timer D compare 4*/
+#define HRTIM_ADC2R_AD2TDPER_Pos      (26U)
+#define HRTIM_ADC2R_AD2TDPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TDPER_Pos)      /*!< 0x04000000 */
+#define HRTIM_ADC2R_AD2TDPER          HRTIM_ADC2R_AD2TDPER_Msk                 /*!< ADC Trigger 2 on Timer D period */
+#define HRTIM_ADC2R_AD2TDRST_Pos      (27U)
+#define HRTIM_ADC2R_AD2TDRST_Msk      (0x1UL << HRTIM_ADC2R_AD2TDRST_Pos)      /*!< 0x08000000 */
+#define HRTIM_ADC2R_AD2TDRST          HRTIM_ADC2R_AD2TDRST_Msk                 /*!< ADC Trigger 2 on Timer D reset */
+#define HRTIM_ADC2R_AD2TEC2_Pos       (28U)
+#define HRTIM_ADC2R_AD2TEC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC2_Pos)       /*!< 0x10000000 */
+#define HRTIM_ADC2R_AD2TEC2           HRTIM_ADC2R_AD2TEC2_Msk                  /*!< ADC Trigger 2 on Timer E compare 2 */
+#define HRTIM_ADC2R_AD2TEC3_Pos       (29U)
+#define HRTIM_ADC2R_AD2TEC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC3_Pos)       /*!< 0x20000000 */
+#define HRTIM_ADC2R_AD2TEC3           HRTIM_ADC2R_AD2TEC3_Msk                  /*!< ADC Trigger 2 on Timer E compare 3 */
+#define HRTIM_ADC2R_AD2TEC4_Pos       (30U)
+#define HRTIM_ADC2R_AD2TEC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC4_Pos)       /*!< 0x40000000 */
+#define HRTIM_ADC2R_AD2TEC4           HRTIM_ADC2R_AD2TEC4_Msk                  /*!< ADC Trigger 2 on Timer E compare 4 */
+#define HRTIM_ADC2R_AD2TERST_Pos      (31U)
+#define HRTIM_ADC2R_AD2TERST_Msk      (0x1UL << HRTIM_ADC2R_AD2TERST_Pos)      /*!< 0x80000000 */
+#define HRTIM_ADC2R_AD2TERST          HRTIM_ADC2R_AD2TERST_Msk                 /*!< ADC Trigger 2 on Timer E reset */
+
+/*******************  Bit definition for HRTIM_ADC3R register  ****************/
+#define HRTIM_ADC3R_AD3MC1_Pos        (0U)
+#define HRTIM_ADC3R_AD3MC1_Msk        (0x1UL << HRTIM_ADC3R_AD3MC1_Pos)        /*!< 0x00000001 */
+#define HRTIM_ADC3R_AD3MC1            HRTIM_ADC3R_AD3MC1_Msk                   /*!< ADC Trigger 3 on master compare 1 */
+#define HRTIM_ADC3R_AD3MC2_Pos        (1U)
+#define HRTIM_ADC3R_AD3MC2_Msk        (0x1UL << HRTIM_ADC3R_AD3MC2_Pos)        /*!< 0x00000002 */
+#define HRTIM_ADC3R_AD3MC2            HRTIM_ADC3R_AD3MC2_Msk                   /*!< ADC Trigger 3 on master compare 2 */
+#define HRTIM_ADC3R_AD3MC3_Pos        (2U)
+#define HRTIM_ADC3R_AD3MC3_Msk        (0x1UL << HRTIM_ADC3R_AD3MC3_Pos)        /*!< 0x00000004 */
+#define HRTIM_ADC3R_AD3MC3            HRTIM_ADC3R_AD3MC3_Msk                   /*!< ADC Trigger 3 on master compare 3 */
+#define HRTIM_ADC3R_AD3MC4_Pos        (3U)
+#define HRTIM_ADC3R_AD3MC4_Msk        (0x1UL << HRTIM_ADC3R_AD3MC4_Pos)        /*!< 0x00000008 */
+#define HRTIM_ADC3R_AD3MC4            HRTIM_ADC3R_AD3MC4_Msk                   /*!< ADC Trigger 3 on master compare 4 */
+#define HRTIM_ADC3R_AD3MPER_Pos       (4U)
+#define HRTIM_ADC3R_AD3MPER_Msk       (0x1UL << HRTIM_ADC3R_AD3MPER_Pos)       /*!< 0x00000010 */
+#define HRTIM_ADC3R_AD3MPER           HRTIM_ADC3R_AD3MPER_Msk                  /*!< ADC Trigger 3 on master period */
+#define HRTIM_ADC3R_AD3EEV1_Pos       (5U)
+#define HRTIM_ADC3R_AD3EEV1_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV1_Pos)       /*!< 0x00000020 */
+#define HRTIM_ADC3R_AD3EEV1           HRTIM_ADC3R_AD3EEV1_Msk                  /*!< ADC Trigger 3 on external event 1 */
+#define HRTIM_ADC3R_AD3EEV2_Pos       (6U)
+#define HRTIM_ADC3R_AD3EEV2_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV2_Pos)       /*!< 0x00000040 */
+#define HRTIM_ADC3R_AD3EEV2           HRTIM_ADC3R_AD3EEV2_Msk                  /*!< ADC Trigger 3 on external event 2 */
+#define HRTIM_ADC3R_AD3EEV3_Pos       (7U)
+#define HRTIM_ADC3R_AD3EEV3_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV3_Pos)       /*!< 0x00000080 */
+#define HRTIM_ADC3R_AD3EEV3           HRTIM_ADC3R_AD3EEV3_Msk                  /*!< ADC Trigger 3 on external event 3 */
+#define HRTIM_ADC3R_AD3EEV4_Pos       (8U)
+#define HRTIM_ADC3R_AD3EEV4_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV4_Pos)       /*!< 0x00000100 */
+#define HRTIM_ADC3R_AD3EEV4           HRTIM_ADC3R_AD3EEV4_Msk                  /*!< ADC Trigger 3 on external event 4 */
+#define HRTIM_ADC3R_AD3EEV5_Pos       (9U)
+#define HRTIM_ADC3R_AD3EEV5_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV5_Pos)       /*!< 0x00000200 */
+#define HRTIM_ADC3R_AD3EEV5           HRTIM_ADC3R_AD3EEV5_Msk                  /*!< ADC Trigger 3 on external event 5 */
+#define HRTIM_ADC3R_AD3TAC2_Pos       (10U)
+#define HRTIM_ADC3R_AD3TAC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC2_Pos)       /*!< 0x00000400 */
+#define HRTIM_ADC3R_AD3TAC2           HRTIM_ADC3R_AD3TAC2_Msk                  /*!< ADC Trigger 3 on Timer A compare 2 */
+#define HRTIM_ADC3R_AD3TAC3_Pos       (11U)
+#define HRTIM_ADC3R_AD3TAC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC3_Pos)       /*!< 0x00000800 */
+#define HRTIM_ADC3R_AD3TAC3           HRTIM_ADC3R_AD3TAC3_Msk                  /*!< ADC Trigger 3 on Timer A compare 3 */
+#define HRTIM_ADC3R_AD3TAC4_Pos       (12U)
+#define HRTIM_ADC3R_AD3TAC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC4_Pos)       /*!< 0x00001000 */
+#define HRTIM_ADC3R_AD3TAC4           HRTIM_ADC3R_AD3TAC4_Msk                  /*!< ADC Trigger 3 on Timer A compare 4 */
+#define HRTIM_ADC3R_AD3TAPER_Pos      (13U)
+#define HRTIM_ADC3R_AD3TAPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TAPER_Pos)      /*!< 0x00002000 */
+#define HRTIM_ADC3R_AD3TAPER          HRTIM_ADC3R_AD3TAPER_Msk                 /*!< ADC Trigger 3 on Timer A period */
+#define HRTIM_ADC3R_AD3TARST_Pos      (14U)
+#define HRTIM_ADC3R_AD3TARST_Msk      (0x1UL << HRTIM_ADC3R_AD3TARST_Pos)      /*!< 0x00004000 */
+#define HRTIM_ADC3R_AD3TARST          HRTIM_ADC3R_AD3TARST_Msk                 /*!< ADC Trigger 3 on Timer A reset */
+#define HRTIM_ADC3R_AD3TBC2_Pos       (15U)
+#define HRTIM_ADC3R_AD3TBC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC2_Pos)       /*!< 0x00008000 */
+#define HRTIM_ADC3R_AD3TBC2           HRTIM_ADC3R_AD3TBC2_Msk                  /*!< ADC Trigger 3 on Timer B compare 2 */
+#define HRTIM_ADC3R_AD3TBC3_Pos       (16U)
+#define HRTIM_ADC3R_AD3TBC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC3_Pos)       /*!< 0x00010000 */
+#define HRTIM_ADC3R_AD3TBC3           HRTIM_ADC3R_AD3TBC3_Msk                  /*!< ADC Trigger 3 on Timer B compare 3 */
+#define HRTIM_ADC3R_AD3TBC4_Pos       (17U)
+#define HRTIM_ADC3R_AD3TBC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC4_Pos)       /*!< 0x00020000 */
+#define HRTIM_ADC3R_AD3TBC4           HRTIM_ADC3R_AD3TBC4_Msk                  /*!< ADC Trigger 3 on Timer B compare 4 */
+#define HRTIM_ADC3R_AD3TBPER_Pos      (18U)
+#define HRTIM_ADC3R_AD3TBPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TBPER_Pos)      /*!< 0x00040000 */
+#define HRTIM_ADC3R_AD3TBPER          HRTIM_ADC3R_AD3TBPER_Msk                 /*!< ADC Trigger 3 on Timer B period */
+#define HRTIM_ADC3R_AD3TBRST_Pos      (19U)
+#define HRTIM_ADC3R_AD3TBRST_Msk      (0x1UL << HRTIM_ADC3R_AD3TBRST_Pos)      /*!< 0x00080000 */
+#define HRTIM_ADC3R_AD3TBRST          HRTIM_ADC3R_AD3TBRST_Msk                 /*!< ADC Trigger 3 on Timer B reset */
+#define HRTIM_ADC3R_AD3TCC2_Pos       (20U)
+#define HRTIM_ADC3R_AD3TCC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC2_Pos)       /*!< 0x00100000 */
+#define HRTIM_ADC3R_AD3TCC2           HRTIM_ADC3R_AD3TCC2_Msk                  /*!< ADC Trigger 3 on Timer C compare 2 */
+#define HRTIM_ADC3R_AD3TCC3_Pos       (21U)
+#define HRTIM_ADC3R_AD3TCC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC3_Pos)       /*!< 0x00200000 */
+#define HRTIM_ADC3R_AD3TCC3           HRTIM_ADC3R_AD3TCC3_Msk                  /*!< ADC Trigger 3 on Timer C compare 3 */
+#define HRTIM_ADC3R_AD3TCC4_Pos       (22U)
+#define HRTIM_ADC3R_AD3TCC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC4_Pos)       /*!< 0x00400000 */
+#define HRTIM_ADC3R_AD3TCC4           HRTIM_ADC3R_AD3TCC4_Msk                  /*!< ADC Trigger 3 on Timer C compare 4 */
+#define HRTIM_ADC3R_AD3TCPER_Pos      (23U)
+#define HRTIM_ADC3R_AD3TCPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TCPER_Pos)      /*!< 0x00800000 */
+#define HRTIM_ADC3R_AD3TCPER          HRTIM_ADC3R_AD3TCPER_Msk                 /*!< ADC Trigger 3 on Timer C period */
+#define HRTIM_ADC3R_AD3TDC2_Pos       (24U)
+#define HRTIM_ADC3R_AD3TDC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC2_Pos)       /*!< 0x01000000 */
+#define HRTIM_ADC3R_AD3TDC2           HRTIM_ADC3R_AD3TDC2_Msk                  /*!< ADC Trigger 3 on Timer D compare 2 */
+#define HRTIM_ADC3R_AD3TDC3_Pos       (25U)
+#define HRTIM_ADC3R_AD3TDC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC3_Pos)       /*!< 0x02000000 */
+#define HRTIM_ADC3R_AD3TDC3           HRTIM_ADC3R_AD3TDC3_Msk                  /*!< ADC Trigger 3 on Timer D compare 3 */
+#define HRTIM_ADC3R_AD3TDC4_Pos       (26U)
+#define HRTIM_ADC3R_AD3TDC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC4_Pos)       /*!< 0x04000000 */
+#define HRTIM_ADC3R_AD3TDC4           HRTIM_ADC3R_AD3TDC4_Msk                  /*!< ADC Trigger 3 on Timer D compare 4 */
+#define HRTIM_ADC3R_AD3TDPER_Pos      (27U)
+#define HRTIM_ADC3R_AD3TDPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TDPER_Pos)      /*!< 0x08000000 */
+#define HRTIM_ADC3R_AD3TDPER          HRTIM_ADC3R_AD3TDPER_Msk                 /*!< ADC Trigger 3 on Timer D period */
+#define HRTIM_ADC3R_AD3TEC2_Pos       (28U)
+#define HRTIM_ADC3R_AD3TEC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC2_Pos)       /*!< 0x10000000 */
+#define HRTIM_ADC3R_AD3TEC2           HRTIM_ADC3R_AD3TEC2_Msk                  /*!< ADC Trigger 3 on Timer E compare 2 */
+#define HRTIM_ADC3R_AD3TEC3_Pos       (29U)
+#define HRTIM_ADC3R_AD3TEC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC3_Pos)       /*!< 0x20000000 */
+#define HRTIM_ADC3R_AD3TEC3           HRTIM_ADC3R_AD3TEC3_Msk                  /*!< ADC Trigger 3 on Timer E compare 3 */
+#define HRTIM_ADC3R_AD3TEC4_Pos       (30U)
+#define HRTIM_ADC3R_AD3TEC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC4_Pos)       /*!< 0x40000000 */
+#define HRTIM_ADC3R_AD3TEC4           HRTIM_ADC3R_AD3TEC4_Msk                  /*!< ADC Trigger 3 on Timer E compare 4 */
+#define HRTIM_ADC3R_AD3TEPER_Pos      (31U)
+#define HRTIM_ADC3R_AD3TEPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TEPER_Pos)      /*!< 0x80000000 */
+#define HRTIM_ADC3R_AD3TEPER          HRTIM_ADC3R_AD3TEPER_Msk                 /*!< ADC Trigger 3 on Timer E period */
+
+/*******************  Bit definition for HRTIM_ADC4R register  ****************/
+#define HRTIM_ADC4R_AD4MC1_Pos        (0U)
+#define HRTIM_ADC4R_AD4MC1_Msk        (0x1UL << HRTIM_ADC4R_AD4MC1_Pos)        /*!< 0x00000001 */
+#define HRTIM_ADC4R_AD4MC1            HRTIM_ADC4R_AD4MC1_Msk                   /*!< ADC Trigger 4 on master compare 1 */
+#define HRTIM_ADC4R_AD4MC2_Pos        (1U)
+#define HRTIM_ADC4R_AD4MC2_Msk        (0x1UL << HRTIM_ADC4R_AD4MC2_Pos)        /*!< 0x00000002 */
+#define HRTIM_ADC4R_AD4MC2            HRTIM_ADC4R_AD4MC2_Msk                   /*!< ADC Trigger 4 on master compare 2 */
+#define HRTIM_ADC4R_AD4MC3_Pos        (2U)
+#define HRTIM_ADC4R_AD4MC3_Msk        (0x1UL << HRTIM_ADC4R_AD4MC3_Pos)        /*!< 0x00000004 */
+#define HRTIM_ADC4R_AD4MC3            HRTIM_ADC4R_AD4MC3_Msk                   /*!< ADC Trigger 4 on master compare 3 */
+#define HRTIM_ADC4R_AD4MC4_Pos        (3U)
+#define HRTIM_ADC4R_AD4MC4_Msk        (0x1UL << HRTIM_ADC4R_AD4MC4_Pos)        /*!< 0x00000008 */
+#define HRTIM_ADC4R_AD4MC4            HRTIM_ADC4R_AD4MC4_Msk                   /*!< ADC Trigger 4 on master compare 4 */
+#define HRTIM_ADC4R_AD4MPER_Pos       (4U)
+#define HRTIM_ADC4R_AD4MPER_Msk       (0x1UL << HRTIM_ADC4R_AD4MPER_Pos)       /*!< 0x00000010 */
+#define HRTIM_ADC4R_AD4MPER           HRTIM_ADC4R_AD4MPER_Msk                  /*!< ADC Trigger 4 on master period */
+#define HRTIM_ADC4R_AD4EEV6_Pos       (5U)
+#define HRTIM_ADC4R_AD4EEV6_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV6_Pos)       /*!< 0x00000020 */
+#define HRTIM_ADC4R_AD4EEV6           HRTIM_ADC4R_AD4EEV6_Msk                  /*!< ADC Trigger 4 on external event 6 */
+#define HRTIM_ADC4R_AD4EEV7_Pos       (6U)
+#define HRTIM_ADC4R_AD4EEV7_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV7_Pos)       /*!< 0x00000040 */
+#define HRTIM_ADC4R_AD4EEV7           HRTIM_ADC4R_AD4EEV7_Msk                  /*!< ADC Trigger 4 on external event 7 */
+#define HRTIM_ADC4R_AD4EEV8_Pos       (7U)
+#define HRTIM_ADC4R_AD4EEV8_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV8_Pos)       /*!< 0x00000080 */
+#define HRTIM_ADC4R_AD4EEV8           HRTIM_ADC4R_AD4EEV8_Msk                  /*!< ADC Trigger 4 on external event 8 */
+#define HRTIM_ADC4R_AD4EEV9_Pos       (8U)
+#define HRTIM_ADC4R_AD4EEV9_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV9_Pos)       /*!< 0x00000100 */
+#define HRTIM_ADC4R_AD4EEV9           HRTIM_ADC4R_AD4EEV9_Msk                  /*!< ADC Trigger 4 on external event 9 */
+#define HRTIM_ADC4R_AD4EEV10_Pos      (9U)
+#define HRTIM_ADC4R_AD4EEV10_Msk      (0x1UL << HRTIM_ADC4R_AD4EEV10_Pos)      /*!< 0x00000200 */
+#define HRTIM_ADC4R_AD4EEV10          HRTIM_ADC4R_AD4EEV10_Msk                 /*!< ADC Trigger 4 on external event 10 */
+#define HRTIM_ADC4R_AD4TAC2_Pos       (10U)
+#define HRTIM_ADC4R_AD4TAC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC2_Pos)       /*!< 0x00000400 */
+#define HRTIM_ADC4R_AD4TAC2           HRTIM_ADC4R_AD4TAC2_Msk                  /*!< ADC Trigger 4 on Timer A compare 2 */
+#define HRTIM_ADC4R_AD4TAC3_Pos       (11U)
+#define HRTIM_ADC4R_AD4TAC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC3_Pos)       /*!< 0x00000800 */
+#define HRTIM_ADC4R_AD4TAC3           HRTIM_ADC4R_AD4TAC3_Msk                  /*!< ADC Trigger 4 on Timer A compare 3 */
+#define HRTIM_ADC4R_AD4TAC4_Pos       (12U)
+#define HRTIM_ADC4R_AD4TAC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC4_Pos)       /*!< 0x00001000 */
+#define HRTIM_ADC4R_AD4TAC4           HRTIM_ADC4R_AD4TAC4_Msk                  /*!< ADC Trigger 4 on Timer A compare 4*/
+#define HRTIM_ADC4R_AD4TAPER_Pos      (13U)
+#define HRTIM_ADC4R_AD4TAPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TAPER_Pos)      /*!< 0x00002000 */
+#define HRTIM_ADC4R_AD4TAPER          HRTIM_ADC4R_AD4TAPER_Msk                 /*!< ADC Trigger 4 on Timer A period */
+#define HRTIM_ADC4R_AD4TBC2_Pos       (14U)
+#define HRTIM_ADC4R_AD4TBC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC2_Pos)       /*!< 0x00004000 */
+#define HRTIM_ADC4R_AD4TBC2           HRTIM_ADC4R_AD4TBC2_Msk                  /*!< ADC Trigger 4 on Timer B compare 2 */
+#define HRTIM_ADC4R_AD4TBC3_Pos       (15U)
+#define HRTIM_ADC4R_AD4TBC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC3_Pos)       /*!< 0x00008000 */
+#define HRTIM_ADC4R_AD4TBC3           HRTIM_ADC4R_AD4TBC3_Msk                  /*!< ADC Trigger 4 on Timer B compare 3 */
+#define HRTIM_ADC4R_AD4TBC4_Pos       (16U)
+#define HRTIM_ADC4R_AD4TBC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC4_Pos)       /*!< 0x00010000 */
+#define HRTIM_ADC4R_AD4TBC4           HRTIM_ADC4R_AD4TBC4_Msk                  /*!< ADC Trigger 4 on Timer B compare 4 */
+#define HRTIM_ADC4R_AD4TBPER_Pos      (17U)
+#define HRTIM_ADC4R_AD4TBPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TBPER_Pos)      /*!< 0x00020000 */
+#define HRTIM_ADC4R_AD4TBPER          HRTIM_ADC4R_AD4TBPER_Msk                 /*!< ADC Trigger 4 on Timer B period */
+#define HRTIM_ADC4R_AD4TCC2_Pos       (18U)
+#define HRTIM_ADC4R_AD4TCC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC2_Pos)       /*!< 0x00040000 */
+#define HRTIM_ADC4R_AD4TCC2           HRTIM_ADC4R_AD4TCC2_Msk                  /*!< ADC Trigger 4 on Timer C compare 2 */
+#define HRTIM_ADC4R_AD4TCC3_Pos       (19U)
+#define HRTIM_ADC4R_AD4TCC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC3_Pos)       /*!< 0x00080000 */
+#define HRTIM_ADC4R_AD4TCC3           HRTIM_ADC4R_AD4TCC3_Msk                  /*!< ADC Trigger 4 on Timer C compare 3 */
+#define HRTIM_ADC4R_AD4TCC4_Pos       (20U)
+#define HRTIM_ADC4R_AD4TCC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC4_Pos)       /*!< 0x00100000 */
+#define HRTIM_ADC4R_AD4TCC4           HRTIM_ADC4R_AD4TCC4_Msk                  /*!< ADC Trigger 4 on Timer C compare 4 */
+#define HRTIM_ADC4R_AD4TCPER_Pos      (21U)
+#define HRTIM_ADC4R_AD4TCPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TCPER_Pos)      /*!< 0x00200000 */
+#define HRTIM_ADC4R_AD4TCPER          HRTIM_ADC4R_AD4TCPER_Msk                 /*!< ADC Trigger 4 on Timer C period */
+#define HRTIM_ADC4R_AD4TCRST_Pos      (22U)
+#define HRTIM_ADC4R_AD4TCRST_Msk      (0x1UL << HRTIM_ADC4R_AD4TCRST_Pos)      /*!< 0x00400000 */
+#define HRTIM_ADC4R_AD4TCRST          HRTIM_ADC4R_AD4TCRST_Msk                 /*!< ADC Trigger 4 on Timer C reset */
+#define HRTIM_ADC4R_AD4TDC2_Pos       (23U)
+#define HRTIM_ADC4R_AD4TDC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC2_Pos)       /*!< 0x00800000 */
+#define HRTIM_ADC4R_AD4TDC2           HRTIM_ADC4R_AD4TDC2_Msk                  /*!< ADC Trigger 4 on Timer D compare 2 */
+#define HRTIM_ADC4R_AD4TDC3_Pos       (24U)
+#define HRTIM_ADC4R_AD4TDC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC3_Pos)       /*!< 0x01000000 */
+#define HRTIM_ADC4R_AD4TDC3           HRTIM_ADC4R_AD4TDC3_Msk                  /*!< ADC Trigger 4 on Timer D compare 3 */
+#define HRTIM_ADC4R_AD4TDC4_Pos       (25U)
+#define HRTIM_ADC4R_AD4TDC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC4_Pos)       /*!< 0x02000000 */
+#define HRTIM_ADC4R_AD4TDC4           HRTIM_ADC4R_AD4TDC4_Msk                  /*!< ADC Trigger 4 on Timer D compare 4*/
+#define HRTIM_ADC4R_AD4TDPER_Pos      (26U)
+#define HRTIM_ADC4R_AD4TDPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TDPER_Pos)      /*!< 0x04000000 */
+#define HRTIM_ADC4R_AD4TDPER          HRTIM_ADC4R_AD4TDPER_Msk                 /*!< ADC Trigger 4 on Timer D period */
+#define HRTIM_ADC4R_AD4TDRST_Pos      (27U)
+#define HRTIM_ADC4R_AD4TDRST_Msk      (0x1UL << HRTIM_ADC4R_AD4TDRST_Pos)      /*!< 0x08000000 */
+#define HRTIM_ADC4R_AD4TDRST          HRTIM_ADC4R_AD4TDRST_Msk                 /*!< ADC Trigger 4 on Timer D reset */
+#define HRTIM_ADC4R_AD4TEC2_Pos       (28U)
+#define HRTIM_ADC4R_AD4TEC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC2_Pos)       /*!< 0x10000000 */
+#define HRTIM_ADC4R_AD4TEC2           HRTIM_ADC4R_AD4TEC2_Msk                  /*!< ADC Trigger 4 on Timer E compare 2 */
+#define HRTIM_ADC4R_AD4TEC3_Pos       (29U)
+#define HRTIM_ADC4R_AD4TEC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC3_Pos)       /*!< 0x20000000 */
+#define HRTIM_ADC4R_AD4TEC3           HRTIM_ADC4R_AD4TEC3_Msk                  /*!< ADC Trigger 4 on Timer E compare 3 */
+#define HRTIM_ADC4R_AD4TEC4_Pos       (30U)
+#define HRTIM_ADC4R_AD4TEC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC4_Pos)       /*!< 0x40000000 */
+#define HRTIM_ADC4R_AD4TEC4           HRTIM_ADC4R_AD4TEC4_Msk                  /*!< ADC Trigger 4 on Timer E compare 4 */
+#define HRTIM_ADC4R_AD4TERST_Pos      (31U)
+#define HRTIM_ADC4R_AD4TERST_Msk      (0x1UL << HRTIM_ADC4R_AD4TERST_Pos)      /*!< 0x80000000 */
+#define HRTIM_ADC4R_AD4TERST          HRTIM_ADC4R_AD4TERST_Msk                 /*!< ADC Trigger 4 on Timer E reset */
+
+/*******************  Bit definition for HRTIM_FLTINR1 register  ***************/
+#define HRTIM_FLTINR1_FLT1E_Pos       (0U)
+#define HRTIM_FLTINR1_FLT1E_Msk       (0x1UL << HRTIM_FLTINR1_FLT1E_Pos)       /*!< 0x00000001 */
+#define HRTIM_FLTINR1_FLT1E           HRTIM_FLTINR1_FLT1E_Msk                  /*!< Fault 1 enable */
+#define HRTIM_FLTINR1_FLT1P_Pos       (1U)
+#define HRTIM_FLTINR1_FLT1P_Msk       (0x1UL << HRTIM_FLTINR1_FLT1P_Pos)       /*!< 0x00000002 */
+#define HRTIM_FLTINR1_FLT1P           HRTIM_FLTINR1_FLT1P_Msk                  /*!< Fault 1 polarity */
+#define HRTIM_FLTINR1_FLT1SRC_Pos     (2U)
+#define HRTIM_FLTINR1_FLT1SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT1SRC_Pos)     /*!< 0x00000004 */
+#define HRTIM_FLTINR1_FLT1SRC         HRTIM_FLTINR1_FLT1SRC_Msk                /*!< Fault 1 source */
+#define HRTIM_FLTINR1_FLT1F_Pos       (3U)
+#define HRTIM_FLTINR1_FLT1F_Msk       (0xFUL << HRTIM_FLTINR1_FLT1F_Pos)       /*!< 0x00000078 */
+#define HRTIM_FLTINR1_FLT1F           HRTIM_FLTINR1_FLT1F_Msk                  /*!< Fault 1 filter */
+#define HRTIM_FLTINR1_FLT1F_0         (0x1UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000008 */
+#define HRTIM_FLTINR1_FLT1F_1         (0x2UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000010 */
+#define HRTIM_FLTINR1_FLT1F_2         (0x4UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000020 */
+#define HRTIM_FLTINR1_FLT1F_3         (0x8UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000040 */
+#define HRTIM_FLTINR1_FLT1LCK_Pos     (7U)
+#define HRTIM_FLTINR1_FLT1LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT1LCK_Pos)     /*!< 0x00000080 */
+#define HRTIM_FLTINR1_FLT1LCK         HRTIM_FLTINR1_FLT1LCK_Msk                /*!< Fault 1 lock */
+
+#define HRTIM_FLTINR1_FLT2E_Pos       (8U)
+#define HRTIM_FLTINR1_FLT2E_Msk       (0x1UL << HRTIM_FLTINR1_FLT2E_Pos)       /*!< 0x00000100 */
+#define HRTIM_FLTINR1_FLT2E           HRTIM_FLTINR1_FLT2E_Msk                  /*!< Fault 2 enable */
+#define HRTIM_FLTINR1_FLT2P_Pos       (9U)
+#define HRTIM_FLTINR1_FLT2P_Msk       (0x1UL << HRTIM_FLTINR1_FLT2P_Pos)       /*!< 0x00000200 */
+#define HRTIM_FLTINR1_FLT2P           HRTIM_FLTINR1_FLT2P_Msk                  /*!< Fault 2 polarity */
+#define HRTIM_FLTINR1_FLT2SRC_Pos     (10U)
+#define HRTIM_FLTINR1_FLT2SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT2SRC_Pos)     /*!< 0x00000400 */
+#define HRTIM_FLTINR1_FLT2SRC         HRTIM_FLTINR1_FLT2SRC_Msk                /*!< Fault 2 source */
+#define HRTIM_FLTINR1_FLT2F_Pos       (11U)
+#define HRTIM_FLTINR1_FLT2F_Msk       (0xFUL << HRTIM_FLTINR1_FLT2F_Pos)       /*!< 0x00007800 */
+#define HRTIM_FLTINR1_FLT2F           HRTIM_FLTINR1_FLT2F_Msk                  /*!< Fault 2 filter */
+#define HRTIM_FLTINR1_FLT2F_0         (0x1UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00000800 */
+#define HRTIM_FLTINR1_FLT2F_1         (0x2UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00001000 */
+#define HRTIM_FLTINR1_FLT2F_2         (0x4UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00002000 */
+#define HRTIM_FLTINR1_FLT2F_3         (0x8UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00004000 */
+#define HRTIM_FLTINR1_FLT2LCK_Pos     (15U)
+#define HRTIM_FLTINR1_FLT2LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT2LCK_Pos)     /*!< 0x00008000 */
+#define HRTIM_FLTINR1_FLT2LCK         HRTIM_FLTINR1_FLT2LCK_Msk                /*!< Fault 2 lock */
+
+#define HRTIM_FLTINR1_FLT3E_Pos       (16U)
+#define HRTIM_FLTINR1_FLT3E_Msk       (0x1UL << HRTIM_FLTINR1_FLT3E_Pos)       /*!< 0x00010000 */
+#define HRTIM_FLTINR1_FLT3E           HRTIM_FLTINR1_FLT3E_Msk                  /*!< Fault 3 enable */
+#define HRTIM_FLTINR1_FLT3P_Pos       (17U)
+#define HRTIM_FLTINR1_FLT3P_Msk       (0x1UL << HRTIM_FLTINR1_FLT3P_Pos)       /*!< 0x00020000 */
+#define HRTIM_FLTINR1_FLT3P           HRTIM_FLTINR1_FLT3P_Msk                  /*!< Fault 3 polarity */
+#define HRTIM_FLTINR1_FLT3SRC_Pos     (18U)
+#define HRTIM_FLTINR1_FLT3SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT3SRC_Pos)     /*!< 0x00040000 */
+#define HRTIM_FLTINR1_FLT3SRC         HRTIM_FLTINR1_FLT3SRC_Msk                /*!< Fault 3 source */
+#define HRTIM_FLTINR1_FLT3F_Pos       (19U)
+#define HRTIM_FLTINR1_FLT3F_Msk       (0xFUL << HRTIM_FLTINR1_FLT3F_Pos)       /*!< 0x00780000 */
+#define HRTIM_FLTINR1_FLT3F           HRTIM_FLTINR1_FLT3F_Msk                  /*!< Fault 3 filter */
+#define HRTIM_FLTINR1_FLT3F_0         (0x1UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00080000 */
+#define HRTIM_FLTINR1_FLT3F_1         (0x2UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00100000 */
+#define HRTIM_FLTINR1_FLT3F_2         (0x4UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00200000 */
+#define HRTIM_FLTINR1_FLT3F_3         (0x8UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00400000 */
+#define HRTIM_FLTINR1_FLT3LCK_Pos     (23U)
+#define HRTIM_FLTINR1_FLT3LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT3LCK_Pos)     /*!< 0x00800000 */
+#define HRTIM_FLTINR1_FLT3LCK         HRTIM_FLTINR1_FLT3LCK_Msk                /*!< Fault 3 lock */
+
+#define HRTIM_FLTINR1_FLT4E_Pos       (24U)
+#define HRTIM_FLTINR1_FLT4E_Msk       (0x1UL << HRTIM_FLTINR1_FLT4E_Pos)       /*!< 0x01000000 */
+#define HRTIM_FLTINR1_FLT4E           HRTIM_FLTINR1_FLT4E_Msk                  /*!< Fault 4 enable */
+#define HRTIM_FLTINR1_FLT4P_Pos       (25U)
+#define HRTIM_FLTINR1_FLT4P_Msk       (0x1UL << HRTIM_FLTINR1_FLT4P_Pos)       /*!< 0x02000000 */
+#define HRTIM_FLTINR1_FLT4P           HRTIM_FLTINR1_FLT4P_Msk                  /*!< Fault 4 polarity */
+#define HRTIM_FLTINR1_FLT4SRC_Pos     (26U)
+#define HRTIM_FLTINR1_FLT4SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT4SRC_Pos)     /*!< 0x04000000 */
+#define HRTIM_FLTINR1_FLT4SRC         HRTIM_FLTINR1_FLT4SRC_Msk                /*!< Fault 4 source */
+#define HRTIM_FLTINR1_FLT4F_Pos       (27U)
+#define HRTIM_FLTINR1_FLT4F_Msk       (0xFUL << HRTIM_FLTINR1_FLT4F_Pos)       /*!< 0x78000000 */
+#define HRTIM_FLTINR1_FLT4F           HRTIM_FLTINR1_FLT4F_Msk                  /*!< Fault 4 filter */
+#define HRTIM_FLTINR1_FLT4F_0         (0x1UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x08000000 */
+#define HRTIM_FLTINR1_FLT4F_1         (0x2UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x10000000 */
+#define HRTIM_FLTINR1_FLT4F_2         (0x4UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x20000000 */
+#define HRTIM_FLTINR1_FLT4F_3         (0x8UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x40000000 */
+#define HRTIM_FLTINR1_FLT4LCK_Pos     (31U)
+#define HRTIM_FLTINR1_FLT4LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT4LCK_Pos)     /*!< 0x80000000 */
+#define HRTIM_FLTINR1_FLT4LCK         HRTIM_FLTINR1_FLT4LCK_Msk                /*!< Fault 4 lock */
+
+/*******************  Bit definition for HRTIM_FLTINR2 register  ***************/
+#define HRTIM_FLTINR2_FLT5E_Pos       (0U)
+#define HRTIM_FLTINR2_FLT5E_Msk       (0x1UL << HRTIM_FLTINR2_FLT5E_Pos)       /*!< 0x00000001 */
+#define HRTIM_FLTINR2_FLT5E           HRTIM_FLTINR2_FLT5E_Msk                  /*!< Fault 5 enable */
+#define HRTIM_FLTINR2_FLT5P_Pos       (1U)
+#define HRTIM_FLTINR2_FLT5P_Msk       (0x1UL << HRTIM_FLTINR2_FLT5P_Pos)       /*!< 0x00000002 */
+#define HRTIM_FLTINR2_FLT5P           HRTIM_FLTINR2_FLT5P_Msk                  /*!< Fault 5 polarity */
+#define HRTIM_FLTINR2_FLT5SRC_Pos     (2U)
+#define HRTIM_FLTINR2_FLT5SRC_Msk     (0x1UL << HRTIM_FLTINR2_FLT5SRC_Pos)     /*!< 0x00000004 */
+#define HRTIM_FLTINR2_FLT5SRC         HRTIM_FLTINR2_FLT5SRC_Msk                /*!< Fault 5 source */
+#define HRTIM_FLTINR2_FLT5F_Pos       (3U)
+#define HRTIM_FLTINR2_FLT5F_Msk       (0xFUL << HRTIM_FLTINR2_FLT5F_Pos)       /*!< 0x00000078 */
+#define HRTIM_FLTINR2_FLT5F           HRTIM_FLTINR2_FLT5F_Msk                  /*!< Fault 5 filter */
+#define HRTIM_FLTINR2_FLT5F_0         (0x1UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000008 */
+#define HRTIM_FLTINR2_FLT5F_1         (0x2UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000010 */
+#define HRTIM_FLTINR2_FLT5F_2         (0x4UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000020 */
+#define HRTIM_FLTINR2_FLT5F_3         (0x8UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000040 */
+#define HRTIM_FLTINR2_FLT5LCK_Pos     (7U)
+#define HRTIM_FLTINR2_FLT5LCK_Msk     (0x1UL << HRTIM_FLTINR2_FLT5LCK_Pos)     /*!< 0x00000080 */
+#define HRTIM_FLTINR2_FLT5LCK         HRTIM_FLTINR2_FLT5LCK_Msk                /*!< Fault 5 lock */
+#define HRTIM_FLTINR2_FLTSD_Pos       (24U)
+#define HRTIM_FLTINR2_FLTSD_Msk       (0x3UL << HRTIM_FLTINR2_FLTSD_Pos)       /*!< 0x03000000 */
+#define HRTIM_FLTINR2_FLTSD           HRTIM_FLTINR2_FLTSD_Msk                  /*!< Fault sampling clock division */
+#define HRTIM_FLTINR2_FLTSD_0         (0x1UL << HRTIM_FLTINR2_FLTSD_Pos)        /*!< 0x01000000 */
+#define HRTIM_FLTINR2_FLTSD_1         (0x2UL << HRTIM_FLTINR2_FLTSD_Pos)        /*!< 0x02000000 */
+
+/*******************  Bit definition for HRTIM_BDMUPR register  ***************/
+#define HRTIM_BDMUPR_MCR_Pos          (0U)
+#define HRTIM_BDMUPR_MCR_Msk          (0x1UL << HRTIM_BDMUPR_MCR_Pos)          /*!< 0x00000001 */
+#define HRTIM_BDMUPR_MCR              HRTIM_BDMUPR_MCR_Msk                     /*!< MCR register update enable */
+#define HRTIM_BDMUPR_MICR_Pos         (1U)
+#define HRTIM_BDMUPR_MICR_Msk         (0x1UL << HRTIM_BDMUPR_MICR_Pos)         /*!< 0x00000002 */
+#define HRTIM_BDMUPR_MICR             HRTIM_BDMUPR_MICR_Msk                    /*!< MICR register update enable */
+#define HRTIM_BDMUPR_MDIER_Pos        (2U)
+#define HRTIM_BDMUPR_MDIER_Msk        (0x1UL << HRTIM_BDMUPR_MDIER_Pos)        /*!< 0x00000004 */
+#define HRTIM_BDMUPR_MDIER            HRTIM_BDMUPR_MDIER_Msk                   /*!< MDIER register update enable */
+#define HRTIM_BDMUPR_MCNT_Pos         (3U)
+#define HRTIM_BDMUPR_MCNT_Msk         (0x1UL << HRTIM_BDMUPR_MCNT_Pos)         /*!< 0x00000008 */
+#define HRTIM_BDMUPR_MCNT             HRTIM_BDMUPR_MCNT_Msk                    /*!< MCNT register update enable */
+#define HRTIM_BDMUPR_MPER_Pos         (4U)
+#define HRTIM_BDMUPR_MPER_Msk         (0x1UL << HRTIM_BDMUPR_MPER_Pos)         /*!< 0x00000010 */
+#define HRTIM_BDMUPR_MPER             HRTIM_BDMUPR_MPER_Msk                    /*!< MPER register update enable */
+#define HRTIM_BDMUPR_MREP_Pos         (5U)
+#define HRTIM_BDMUPR_MREP_Msk         (0x1UL << HRTIM_BDMUPR_MREP_Pos)         /*!< 0x00000020 */
+#define HRTIM_BDMUPR_MREP             HRTIM_BDMUPR_MREP_Msk                    /*!< MREP register update enable */
+#define HRTIM_BDMUPR_MCMP1_Pos        (6U)
+#define HRTIM_BDMUPR_MCMP1_Msk        (0x1UL << HRTIM_BDMUPR_MCMP1_Pos)        /*!< 0x00000040 */
+#define HRTIM_BDMUPR_MCMP1            HRTIM_BDMUPR_MCMP1_Msk                   /*!< MCMP1 register update enable */
+#define HRTIM_BDMUPR_MCMP2_Pos        (7U)
+#define HRTIM_BDMUPR_MCMP2_Msk        (0x1UL << HRTIM_BDMUPR_MCMP2_Pos)        /*!< 0x00000080 */
+#define HRTIM_BDMUPR_MCMP2            HRTIM_BDMUPR_MCMP2_Msk                   /*!< MCMP2 register update enable */
+#define HRTIM_BDMUPR_MCMP3_Pos        (8U)
+#define HRTIM_BDMUPR_MCMP3_Msk        (0x1UL << HRTIM_BDMUPR_MCMP3_Pos)        /*!< 0x00000100 */
+#define HRTIM_BDMUPR_MCMP3            HRTIM_BDMUPR_MCMP3_Msk                   /*!< MCMP3 register update enable */
+#define HRTIM_BDMUPR_MCMP4_Pos        (9U)
+#define HRTIM_BDMUPR_MCMP4_Msk        (0x1UL << HRTIM_BDMUPR_MCMP4_Pos)        /*!< 0x00000200 */
+#define HRTIM_BDMUPR_MCMP4            HRTIM_BDMUPR_MCMP4_Msk                   /*!< MPCMP4 register update enable */
+
+/*******************  Bit definition for HRTIM_BDTUPR register  ***************/
+#define HRTIM_BDTUPR_TIMCR_Pos        (0U)
+#define HRTIM_BDTUPR_TIMCR_Msk        (0x1UL << HRTIM_BDTUPR_TIMCR_Pos)        /*!< 0x00000001 */
+#define HRTIM_BDTUPR_TIMCR            HRTIM_BDTUPR_TIMCR_Msk                   /*!<  TIMCR register update enable */
+#define HRTIM_BDTUPR_TIMICR_Pos       (1U)
+#define HRTIM_BDTUPR_TIMICR_Msk       (0x1UL << HRTIM_BDTUPR_TIMICR_Pos)       /*!< 0x00000002 */
+#define HRTIM_BDTUPR_TIMICR           HRTIM_BDTUPR_TIMICR_Msk                  /*!<  TIMICR register update enable */
+#define HRTIM_BDTUPR_TIMDIER_Pos      (2U)
+#define HRTIM_BDTUPR_TIMDIER_Msk      (0x1UL << HRTIM_BDTUPR_TIMDIER_Pos)      /*!< 0x00000004 */
+#define HRTIM_BDTUPR_TIMDIER          HRTIM_BDTUPR_TIMDIER_Msk                 /*!<  TIMDIER register update enable */
+#define HRTIM_BDTUPR_TIMCNT_Pos       (3U)
+#define HRTIM_BDTUPR_TIMCNT_Msk       (0x1UL << HRTIM_BDTUPR_TIMCNT_Pos)       /*!< 0x00000008 */
+#define HRTIM_BDTUPR_TIMCNT           HRTIM_BDTUPR_TIMCNT_Msk                  /*!<  TIMCNT register update enable */
+#define HRTIM_BDTUPR_TIMPER_Pos       (4U)
+#define HRTIM_BDTUPR_TIMPER_Msk       (0x1UL << HRTIM_BDTUPR_TIMPER_Pos)       /*!< 0x00000010 */
+#define HRTIM_BDTUPR_TIMPER           HRTIM_BDTUPR_TIMPER_Msk                  /*!<  TIMPER register update enable */
+#define HRTIM_BDTUPR_TIMREP_Pos       (5U)
+#define HRTIM_BDTUPR_TIMREP_Msk       (0x1UL << HRTIM_BDTUPR_TIMREP_Pos)       /*!< 0x00000020 */
+#define HRTIM_BDTUPR_TIMREP           HRTIM_BDTUPR_TIMREP_Msk                  /*!<  TIMREP register update enable */
+#define HRTIM_BDTUPR_TIMCMP1_Pos      (6U)
+#define HRTIM_BDTUPR_TIMCMP1_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP1_Pos)      /*!< 0x00000040 */
+#define HRTIM_BDTUPR_TIMCMP1          HRTIM_BDTUPR_TIMCMP1_Msk                 /*!<  TIMCMP1 register update enable */
+#define HRTIM_BDTUPR_TIMCMP2_Pos      (7U)
+#define HRTIM_BDTUPR_TIMCMP2_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP2_Pos)      /*!< 0x00000080 */
+#define HRTIM_BDTUPR_TIMCMP2          HRTIM_BDTUPR_TIMCMP2_Msk                 /*!<  TIMCMP2 register update enable */
+#define HRTIM_BDTUPR_TIMCMP3_Pos      (8U)
+#define HRTIM_BDTUPR_TIMCMP3_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP3_Pos)      /*!< 0x00000100 */
+#define HRTIM_BDTUPR_TIMCMP3          HRTIM_BDTUPR_TIMCMP3_Msk                 /*!<  TIMCMP3 register update enable */
+#define HRTIM_BDTUPR_TIMCMP4_Pos      (9U)
+#define HRTIM_BDTUPR_TIMCMP4_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP4_Pos)      /*!< 0x00000200 */
+#define HRTIM_BDTUPR_TIMCMP4          HRTIM_BDTUPR_TIMCMP4_Msk                 /*!<  TIMCMP4 register update enable */
+#define HRTIM_BDTUPR_TIMDTR_Pos       (10U)
+#define HRTIM_BDTUPR_TIMDTR_Msk       (0x1UL << HRTIM_BDTUPR_TIMDTR_Pos)       /*!< 0x00000400 */
+#define HRTIM_BDTUPR_TIMDTR           HRTIM_BDTUPR_TIMDTR_Msk                  /*!<  TIMDTR register update enable */
+#define HRTIM_BDTUPR_TIMSET1R_Pos     (11U)
+#define HRTIM_BDTUPR_TIMSET1R_Msk     (0x1UL << HRTIM_BDTUPR_TIMSET1R_Pos)     /*!< 0x00000800 */
+#define HRTIM_BDTUPR_TIMSET1R         HRTIM_BDTUPR_TIMSET1R_Msk                /*!<  TIMSET1R register update enable */
+#define HRTIM_BDTUPR_TIMRST1R_Pos     (12U)
+#define HRTIM_BDTUPR_TIMRST1R_Msk     (0x1UL << HRTIM_BDTUPR_TIMRST1R_Pos)     /*!< 0x00001000 */
+#define HRTIM_BDTUPR_TIMRST1R         HRTIM_BDTUPR_TIMRST1R_Msk                /*!<  TIMRST1R register update enable */
+#define HRTIM_BDTUPR_TIMSET2R_Pos     (13U)
+#define HRTIM_BDTUPR_TIMSET2R_Msk     (0x1UL << HRTIM_BDTUPR_TIMSET2R_Pos)     /*!< 0x00002000 */
+#define HRTIM_BDTUPR_TIMSET2R         HRTIM_BDTUPR_TIMSET2R_Msk                /*!<  TIMSET2R register update enable */
+#define HRTIM_BDTUPR_TIMRST2R_Pos     (14U)
+#define HRTIM_BDTUPR_TIMRST2R_Msk     (0x1UL << HRTIM_BDTUPR_TIMRST2R_Pos)     /*!< 0x00004000 */
+#define HRTIM_BDTUPR_TIMRST2R         HRTIM_BDTUPR_TIMRST2R_Msk                /*!<  TIMRST2R register update enable */
+#define HRTIM_BDTUPR_TIMEEFR1_Pos     (15U)
+#define HRTIM_BDTUPR_TIMEEFR1_Msk     (0x1UL << HRTIM_BDTUPR_TIMEEFR1_Pos)     /*!< 0x00008000 */
+#define HRTIM_BDTUPR_TIMEEFR1         HRTIM_BDTUPR_TIMEEFR1_Msk                /*!<  TIMEEFR1 register update enable */
+#define HRTIM_BDTUPR_TIMEEFR2_Pos     (16U)
+#define HRTIM_BDTUPR_TIMEEFR2_Msk     (0x1UL << HRTIM_BDTUPR_TIMEEFR2_Pos)     /*!< 0x00010000 */
+#define HRTIM_BDTUPR_TIMEEFR2         HRTIM_BDTUPR_TIMEEFR2_Msk                /*!<  TIMEEFR2 register update enable */
+#define HRTIM_BDTUPR_TIMRSTR_Pos      (17U)
+#define HRTIM_BDTUPR_TIMRSTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMRSTR_Pos)      /*!< 0x00020000 */
+#define HRTIM_BDTUPR_TIMRSTR          HRTIM_BDTUPR_TIMRSTR_Msk                 /*!<  TIMRSTR register update enable */
+#define HRTIM_BDTUPR_TIMCHPR_Pos      (18U)
+#define HRTIM_BDTUPR_TIMCHPR_Msk      (0x1UL << HRTIM_BDTUPR_TIMCHPR_Pos)      /*!< 0x00040000 */
+#define HRTIM_BDTUPR_TIMCHPR          HRTIM_BDTUPR_TIMCHPR_Msk                 /*!<  TIMCHPR register update enable */
+#define HRTIM_BDTUPR_TIMOUTR_Pos      (19U)
+#define HRTIM_BDTUPR_TIMOUTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMOUTR_Pos)      /*!< 0x00080000 */
+#define HRTIM_BDTUPR_TIMOUTR          HRTIM_BDTUPR_TIMOUTR_Msk                 /*!<  TIMOUTR register update enable */
+#define HRTIM_BDTUPR_TIMFLTR_Pos      (20U)
+#define HRTIM_BDTUPR_TIMFLTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMFLTR_Pos)      /*!< 0x00100000 */
+#define HRTIM_BDTUPR_TIMFLTR          HRTIM_BDTUPR_TIMFLTR_Msk                 /*!<  TIMFLTR register update enable */
+
+/*******************  Bit definition for HRTIM_BDMADR register  ***************/
+#define HRTIM_BDMADR_BDMADR_Pos       (0U)
+#define HRTIM_BDMADR_BDMADR_Msk       (0xFFFFFFFFUL << HRTIM_BDMADR_BDMADR_Pos) /*!< 0xFFFFFFFF */
+#define HRTIM_BDMADR_BDMADR           HRTIM_BDMADR_BDMADR_Msk                  /*!<  Burst DMA Data register */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             RAM ECC monitoring                             */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for RAMECC_IER register  ******************/
+#define RAMECC_IER_GECCDEBWIE_Pos         (3U)
+#define RAMECC_IER_GECCDEBWIE_Msk         (0x1UL << RAMECC_IER_GECCDEBWIE_Pos)  /*!< 0x00000008 */
+#define RAMECC_IER_GECCDEBWIE             RAMECC_IER_GECCDEBWIE_Msk             /*!< Global ECC double error on byte write (BW) interrupt enable */
+#define RAMECC_IER_GECCDEIE_Pos           (2U)
+#define RAMECC_IER_GECCDEIE_Msk           (0x1UL << RAMECC_IER_GECCDEIE_Pos)    /*!< 0x00000004 */
+#define RAMECC_IER_GECCDEIE               RAMECC_IER_GECCDEIE_Msk               /*!< Global ECC double error interrupt enable */
+#define RAMECC_IER_GECCSEIE_Pos           (1U)
+#define RAMECC_IER_GECCSEIE_Msk           (0x1UL << RAMECC_IER_GECCSEIE_Pos)    /*!< 0x00000002 */
+#define RAMECC_IER_GECCSEIE               RAMECC_IER_GECCSEIE_Msk               /*!< Global ECC single error interrupt enable */
+#define RAMECC_IER_GIE_Pos                (0U)
+#define RAMECC_IER_GIE_Msk                (0x1UL << RAMECC_IER_GIE_Pos)         /*!< 0x00000001 */
+#define RAMECC_IER_GIE                    RAMECC_IER_GIE_Msk                    /*!< Global interrupt enable */
+
+/*******************  Bit definition for RAMECC_CR register  ******************/
+#define RAMECC_CR_ECCELEN_Pos             (5U)
+#define RAMECC_CR_ECCELEN_Msk             (0x1UL << RAMECC_CR_ECCELEN_Pos)      /*!< 0x00000020 */
+#define RAMECC_CR_ECCELEN                 RAMECC_CR_ECCELEN_Msk                 /*!< ECC error latching enable */
+#define RAMECC_CR_ECCDEBWIE_Pos           (4U)
+#define RAMECC_CR_ECCDEBWIE_Msk           (0x1UL << RAMECC_CR_ECCDEBWIE_Pos)    /*!< 0x00000010 */
+#define RAMECC_CR_ECCDEBWIE               RAMECC_CR_ECCDEBWIE_Msk               /*!< ECC double error on byte write (BW) interrupt enable */
+#define RAMECC_CR_ECCDEIE_Pos             (3U)
+#define RAMECC_CR_ECCDEIE_Msk             (0x1UL << RAMECC_CR_ECCDEIE_Pos)      /*!< 0x00000008 */
+#define RAMECC_CR_ECCDEIE                 RAMECC_CR_ECCDEIE_Msk                 /*!< ECC double error interrupt enable */
+#define RAMECC_CR_ECCSEIE_Pos             (2U)
+#define RAMECC_CR_ECCSEIE_Msk             (0x1UL << RAMECC_CR_ECCSEIE_Pos)      /*!< 0x00000004 */
+#define RAMECC_CR_ECCSEIE                 RAMECC_CR_ECCSEIE_Msk                 /*!< ECC single error interrupt enable */
+
+/*******************  Bit definition for RAMECC_SR register  ******************/
+#define RAMECC_SR_DEBWDF_Pos             (2U)
+#define RAMECC_SR_DEBWDF_Msk             (0x1UL << RAMECC_SR_DEBWDF_Pos)        /*!< 0x00000004 */
+#define RAMECC_SR_DEBWDF                 RAMECC_SR_DEBWDF_Msk                   /*!< ECC double error on byte write (BW) detected flag */
+#define RAMECC_SR_DEDF_Pos               (1U)
+#define RAMECC_SR_DEDF_Msk               (0x1UL << RAMECC_SR_DEDF_Pos)          /*!< 0x00000002 */
+#define RAMECC_SR_DEDF                   RAMECC_SR_DEDF_Msk                     /*!< ECC double error detected flag */
+#define RAMECC_SR_SEDCF_Pos              (0U)
+#define RAMECC_SR_SEDCF_Msk              (0x1UL << RAMECC_SR_SEDCF_Pos)         /*!< 0x00000001 */
+#define RAMECC_SR_SEDCF                  RAMECC_SR_SEDCF_Msk                    /*!< ECC single error detected and corrected flag */
+
+/******************  Bit definition for RAMECC_FAR register  ******************/
+#define RAMECC_FAR_FADD_Pos              (0U)
+#define RAMECC_FAR_FADD_Msk              (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos)  /*!< 0xFFFFFFFF */
+#define RAMECC_FAR_FADD                  RAMECC_FAR_FADD_Msk                    /*!< ECC error failing address */
+
+/******************  Bit definition for RAMECC_FDRL register  *****************/
+#define RAMECC_FAR_FDATAL_Pos            (0U)
+#define RAMECC_FAR_FDATAL_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAL_Pos)/*!< 0xFFFFFFFF */
+#define RAMECC_FAR_FDATAL                RAMECC_FAR_FDATAL_Msk                  /*!< ECC error failing address */
+
+/******************  Bit definition for RAMECC_FDRH register  *****************/
+#define RAMECC_FAR_FDATAH_Pos            (0U)
+#define RAMECC_FAR_FDATAH_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAH_Pos)/*!< 0xFFFFFFFF */
+#define RAMECC_FAR_FDATAH                RAMECC_FAR_FDATAH_Msk                  /* Failing data high (64-bit memory) */
+
+/*****************  Bit definition for RAMECC_FECR register  ******************/
+#define RAMECC_FECR_FEC_Pos              (0U)
+#define RAMECC_FECR_FEC_Msk              (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos)  /*!< 0xFFFFFFFF */
+#define RAMECC_FECR_FEC                  RAMECC_FECR_FEC_Msk                    /*!< Failing error code */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                MDIOS                                        */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for MDIOS_CR register  *******************/
+#define MDIOS_CR_EN_Pos                (0U)
+#define MDIOS_CR_EN_Msk                (0x1UL << MDIOS_CR_EN_Pos)              /*!< 0x00000001 */
+#define MDIOS_CR_EN                    MDIOS_CR_EN_Msk                         /*!<  MDIOS slave peripheral enable */
+#define MDIOS_CR_WRIE_Pos              (1U)
+#define MDIOS_CR_WRIE_Msk              (0x1UL << MDIOS_CR_WRIE_Pos)            /*!< 0x00000002 */
+#define MDIOS_CR_WRIE                  MDIOS_CR_WRIE_Msk                       /*!<  MDIOS slave register write interrupt enable. */
+#define MDIOS_CR_RDIE_Pos              (2U)
+#define MDIOS_CR_RDIE_Msk              (0x1UL << MDIOS_CR_RDIE_Pos)            /*!< 0x00000004 */
+#define MDIOS_CR_RDIE                  MDIOS_CR_RDIE_Msk                       /*!<  MDIOS slave register read interrupt enable. */
+#define MDIOS_CR_EIE_Pos               (3U)
+#define MDIOS_CR_EIE_Msk               (0x1UL << MDIOS_CR_EIE_Pos)             /*!< 0x00000008 */
+#define MDIOS_CR_EIE                   MDIOS_CR_EIE_Msk                        /*!<  MDIOS slave register error interrupt enable. */
+#define MDIOS_CR_DPC_Pos               (7U)
+#define MDIOS_CR_DPC_Msk               (0x1UL << MDIOS_CR_DPC_Pos)             /*!< 0x00000080 */
+#define MDIOS_CR_DPC                   MDIOS_CR_DPC_Msk                        /*!<  MDIOS slave disable preamble check. */
+#define MDIOS_CR_PORT_ADDRESS_Pos      (8U)
+#define MDIOS_CR_PORT_ADDRESS_Msk      (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos)   /*!< 0x00001F00 */
+#define MDIOS_CR_PORT_ADDRESS          MDIOS_CR_PORT_ADDRESS_Msk               /*!<  MDIOS slave port address mask. */
+#define MDIOS_CR_PORT_ADDRESS_0        (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000100 */
+#define MDIOS_CR_PORT_ADDRESS_1        (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000200 */
+#define MDIOS_CR_PORT_ADDRESS_2        (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000400 */
+#define MDIOS_CR_PORT_ADDRESS_3        (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000800 */
+#define MDIOS_CR_PORT_ADDRESS_4        (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00001000 */
+
+/********************  Bit definition for MDIOS_SR register  *******************/
+#define MDIOS_SR_PERF_Pos              (0U)
+#define MDIOS_SR_PERF_Msk              (0x1UL << MDIOS_SR_PERF_Pos)            /*!< 0x00000001 */
+#define MDIOS_SR_PERF                  MDIOS_SR_PERF_Msk                       /*!<  MDIOS slave turnaround error flag*/
+#define MDIOS_SR_SERF_Pos              (1U)
+#define MDIOS_SR_SERF_Msk              (0x1UL << MDIOS_SR_SERF_Pos)            /*!< 0x00000002 */
+#define MDIOS_SR_SERF                  MDIOS_SR_SERF_Msk                       /*!<  MDIOS slave start error flag */
+#define MDIOS_SR_TERF_Pos              (2U)
+#define MDIOS_SR_TERF_Msk              (0x1UL << MDIOS_SR_TERF_Pos)            /*!< 0x00000004 */
+#define MDIOS_SR_TERF                  MDIOS_SR_TERF_Msk                       /*!<  MDIOS slave preamble error flag */
+
+/********************  Bit definition for MDIOS_CLRFR register  *******************/
+#define MDIOS_SR_CPERF_Pos             (0U)
+#define MDIOS_SR_CPERF_Msk             (0x1UL << MDIOS_SR_CPERF_Pos)           /*!< 0x00000001 */
+#define MDIOS_SR_CPERF                 MDIOS_SR_CPERF_Msk                      /*!<  MDIOS slave Clear the turnaround error flag */
+#define MDIOS_SR_CSERF_Pos             (1U)
+#define MDIOS_SR_CSERF_Msk             (0x1UL << MDIOS_SR_CSERF_Pos)           /*!< 0x00000002 */
+#define MDIOS_SR_CSERF                 MDIOS_SR_CSERF_Msk                      /*!<  MDIOS slave Clear the start error flag */
+#define MDIOS_SR_CTERF_Pos             (2U)
+#define MDIOS_SR_CTERF_Msk             (0x1UL << MDIOS_SR_CTERF_Pos)           /*!< 0x00000004 */
+#define MDIOS_SR_CTERF                 MDIOS_SR_CTERF_Msk                      /*!<  MDIOS slave Clear the preamble error flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                       USB_OTG                              */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/
+#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)
+#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)
+#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
+#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */
+#define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)
+#define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */
+#define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)
+#define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
+#define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
+#define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)
+#define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)
+#define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
+#define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)
+#define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)
+#define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */
+#define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)
+#define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)
+#define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)
+#define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)
+#define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
+#define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_EHEN_Pos                 (12U)
+#define USB_OTG_GOTGCTL_EHEN_Msk                 (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
+#define USB_OTG_GOTGCTL_EHEN                     USB_OTG_GOTGCTL_EHEN_Msk      /*!< Embedded host enable */
+#define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)
+#define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
+#define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)
+#define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)
+#define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */
+#define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)
+#define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!< B-session valid */
+#define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)
+#define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
+#define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */
+
+/********************  Bit definition forUSB_OTG_HCFG register  ********************/
+
+#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)
+#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
+#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */
+#define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCFG_FSLSS_Pos                   (2U)
+#define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */
+
+/********************  Bit definition forUSB_OTG_DCFG register  ********************/
+
+#define USB_OTG_DCFG_DSPD_Pos                    (0U)
+#define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
+#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)
+#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD_Pos                     (4U)
+#define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */
+#define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
+
+#define USB_OTG_DCFG_PFIVL_Pos                   (11U)
+#define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
+
+#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)
+#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
+#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
+
+/********************  Bit definition forUSB_OTG_PCGCR register  ********************/
+#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)
+#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)
+#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)
+#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */
+
+/********************  Bit definition forUSB_OTG_GOTGINT register  ********************/
+#define USB_OTG_GOTGINT_SEDET_Pos                (2U)
+#define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */
+#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)
+#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */
+#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)
+#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)
+#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */
+#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)
+#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */
+#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)
+#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */
+
+/********************  Bit definition forUSB_OTG_DCTL register  ********************/
+#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)
+#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS_Pos                    (1U)
+#define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */
+#define USB_OTG_DCTL_GINSTS_Pos                  (2U)
+#define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */
+#define USB_OTG_DCTL_GONSTS_Pos                  (3U)
+#define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
+#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */
+
+#define USB_OTG_DCTL_TCTL_Pos                    (4U)
+#define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
+#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCTL_SGINAK_Pos                  (7U)
+#define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */
+#define USB_OTG_DCTL_CGINAK_Pos                  (8U)
+#define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */
+#define USB_OTG_DCTL_SGONAK_Pos                  (9U)
+#define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */
+#define USB_OTG_DCTL_CGONAK_Pos                  (10U)
+#define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */
+#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)
+#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
+
+/********************  Bit definition forUSB_OTG_HFIR register  ********************/
+#define USB_OTG_HFIR_FRIVL_Pos                   (0U)
+#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */
+
+/********************  Bit definition forUSB_OTG_HFNUM register  ********************/
+#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)
+#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */
+#define USB_OTG_HFNUM_FTREM_Pos                  (16U)
+#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */
+
+/********************  Bit definition forUSB_OTG_DSTS register  ********************/
+#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)
+#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */
+
+#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)
+#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
+#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
+#define USB_OTG_DSTS_EERR_Pos                    (3U)
+#define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
+#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */
+#define USB_OTG_DSTS_FNSOF_Pos                   (8U)
+#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
+#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */
+
+/********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/
+#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)
+#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
+#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */
+
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)
+#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
+#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
+#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
+#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
+#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
+#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)
+#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)
+#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)
+#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
+#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */
+
+/********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)
+#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
+#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
+#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
+#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
+#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)
+#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
+#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)
+#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
+#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)
+#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
+#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */
+
+#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)
+#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
+#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
+#define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
+#define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
+#define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)
+#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)
+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
+#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */
+#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)
+#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
+#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */
+#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)
+#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
+#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */
+#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)
+#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
+#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)
+#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
+#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */
+#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)
+#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
+#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)
+#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
+#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */
+#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)
+#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
+#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */
+#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)
+#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
+#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */
+#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)
+#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */
+
+/********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
+#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)
+#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
+#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */
+#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)
+#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
+#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */
+#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)
+#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
+#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)
+#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
+#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)
+#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
+#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */
+
+#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)
+#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
+#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
+#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
+#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)
+#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
+#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)
+#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
+#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */
+
+/********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/
+#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)
+#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */
+#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)
+#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */
+#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)
+#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
+#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)
+#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */
+#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)
+#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */
+#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)
+#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */
+#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)
+#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */
+
+/********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)
+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */
+
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)
+#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)
+#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
+
+/********************  Bit definition forUSB_OTG_HAINT register  ********************/
+#define USB_OTG_HAINT_HAINT_Pos                  (0U)
+#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */
+
+/********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/
+#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)
+#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)
+#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */
+#define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)
+#define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
+#define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk      /*!< OUT transaction AHB Error interrupt mask               */
+#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)
+#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */
+#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)
+#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)
+#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)
+#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */
+#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)
+#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */
+#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)
+#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */
+#define USB_OTG_DOEPMSK_BERRM_Pos                (12U)
+#define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask               */
+#define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)
+#define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask               */
+#define USB_OTG_DOEPMSK_NYETM_Pos                (14U)
+#define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk      /*!< NYET interrupt mask                */
+
+/********************  Bit definition forUSB_OTG_GINTSTS register  ********************/
+#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)
+#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
+#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */
+#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)
+#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */
+#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)
+#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */
+#define USB_OTG_GINTSTS_SOF_Pos                  (3U)
+#define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */
+#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)
+#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */
+#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)
+#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */
+#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)
+#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */
+#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)
+#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */
+#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)
+#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */
+#define USB_OTG_GINTSTS_USBRST_Pos               (12U)
+#define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */
+#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)
+#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */
+#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)
+#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */
+#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)
+#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */
+#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)
+#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */
+#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)
+#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */
+#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)
+#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)
+#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */
+#define USB_OTG_GINTSTS_RSTDET_Pos               (23U)
+#define USB_OTG_GINTSTS_RSTDET_Msk               (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
+#define USB_OTG_GINTSTS_RSTDET                   USB_OTG_GINTSTS_RSTDET_Msk    /*!< Reset detected interrupt                       */
+#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)
+#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */
+#define USB_OTG_GINTSTS_HCINT_Pos                (25U)
+#define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */
+#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)
+#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */
+#define USB_OTG_GINTSTS_LPMINT_Pos               (27U)
+#define USB_OTG_GINTSTS_LPMINT_Msk               (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt                                  */
+#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)
+#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */
+#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)
+#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */
+#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)
+#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)
+#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */
+
+/********************  Bit definition forUSB_OTG_GINTMSK register  ********************/
+#define USB_OTG_GINTMSK_MMISM_Pos                (1U)
+#define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */
+#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)
+#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */
+#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)
+#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */
+#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)
+#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */
+#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)
+#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)
+#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)
+#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */
+#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)
+#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */
+#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)
+#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */
+#define USB_OTG_GINTMSK_USBRST_Pos               (12U)
+#define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)
+#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */
+#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)
+#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */
+#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)
+#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */
+#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)
+#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
+#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */
+#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)
+#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */
+#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)
+#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)
+#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */
+#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)
+#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */
+#define USB_OTG_GINTMSK_RSTDEM_Pos               (23U)
+#define USB_OTG_GINTMSK_RSTDEM_Msk               (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */
+#define USB_OTG_GINTMSK_RSTDEM                   USB_OTG_GINTMSK_RSTDEM_Msk    /*!< Reset detected interrupt mask                      */
+#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)
+#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */
+#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)
+#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */
+#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)
+#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */
+#define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)
+#define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask                                  */
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)
+#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */
+#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)
+#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */
+#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)
+#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)
+#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */
+
+/********************  Bit definition forUSB_OTG_DAINT register  ********************/
+#define USB_OTG_DAINT_IEPINT_Pos                 (0U)
+#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */
+#define USB_OTG_DAINT_OEPINT_Pos                 (16U)
+#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */
+
+/********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/
+#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)
+#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */
+
+/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
+#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)
+#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */
+#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)
+#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)
+#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)
+#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/
+#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)
+#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)
+#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition for OTG register  ********************/
+
+#define USB_OTG_CHNUM_Pos                        (0U)
+#define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)  /*!< 0x0000000F */
+#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */
+#define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos                         (4U)
+#define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */
+
+#define USB_OTG_DPID_Pos                         (15U)
+#define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)   /*!< 0x00018000 */
+#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */
+#define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */
+#define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */
+
+#define USB_OTG_PKTSTS_Pos                       (17U)
+#define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */
+
+#define USB_OTG_EPNUM_Pos                        (0U)
+#define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)  /*!< 0x0000000F */
+#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */
+
+#define USB_OTG_FRMNUM_Pos                       (21U)
+#define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */
+
+/********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/
+#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)
+#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */
+
+/********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)
+#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */
+
+/********************  Bit definition for OTG register  ********************/
+#define USB_OTG_NPTXFSA_Pos                      (0U)
+#define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD_Pos                       (16U)
+#define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */
+#define USB_OTG_TX0FSA_Pos                       (0U)
+#define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */
+#define USB_OTG_TX0FD_Pos                        (16U)
+#define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */
+
+/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)
+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
+#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
+
+/********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
+#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
+#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)
+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
+#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)
+#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
+#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)
+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
+#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)
+#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
+#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */
+
+/********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/********************  Bit definition forUSB_OTG_DEACHINT register  ********************/
+#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)
+#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */
+#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)
+#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */
+
+/********************  Bit definition forUSB_OTG_GCCFG register  ********************/
+#define USB_OTG_GCCFG_DCDET_Pos                  (0U)
+#define USB_OTG_GCCFG_DCDET_Msk                  (0x1UL << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */
+#define USB_OTG_GCCFG_DCDET                      USB_OTG_GCCFG_DCDET_Msk       /*!< Data contact detection (DCD) status */
+#define USB_OTG_GCCFG_PDET_Pos                   (1U)
+#define USB_OTG_GCCFG_PDET_Msk                   (0x1UL << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_GCCFG_PDET                       USB_OTG_GCCFG_PDET_Msk        /*!< Primary detection (PD) status */
+#define USB_OTG_GCCFG_SDET_Pos                   (2U)
+#define USB_OTG_GCCFG_SDET_Msk                   (0x1UL << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GCCFG_SDET                       USB_OTG_GCCFG_SDET_Msk        /*!< Secondary detection (SD) status */
+#define USB_OTG_GCCFG_PS2DET_Pos                 (3U)
+#define USB_OTG_GCCFG_PS2DET_Msk                 (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */
+#define USB_OTG_GCCFG_PS2DET                     USB_OTG_GCCFG_PS2DET_Msk      /*!< DM pull-up detection status */
+#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)
+#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
+#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */
+#define USB_OTG_GCCFG_BCDEN_Pos                  (17U)
+#define USB_OTG_GCCFG_BCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_GCCFG_BCDEN                      USB_OTG_GCCFG_BCDEN_Msk       /*!< Battery charging detector (BCD) enable */
+#define USB_OTG_GCCFG_DCDEN_Pos                  (18U)
+#define USB_OTG_GCCFG_DCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_GCCFG_DCDEN                      USB_OTG_GCCFG_DCDEN_Msk       /*!< Data contact detection (DCD) mode enable*/
+#define USB_OTG_GCCFG_PDEN_Pos                   (19U)
+#define USB_OTG_GCCFG_PDEN_Msk                   (0x1UL << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_GCCFG_PDEN                       USB_OTG_GCCFG_PDEN_Msk        /*!< Primary detection (PD) mode enable*/
+#define USB_OTG_GCCFG_SDEN_Pos                   (20U)
+#define USB_OTG_GCCFG_SDEN_Msk                   (0x1UL << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_GCCFG_SDEN                       USB_OTG_GCCFG_SDEN_Msk        /*!< Secondary detection (SD) mode enable */
+#define USB_OTG_GCCFG_VBDEN_Pos                  (21U)
+#define USB_OTG_GCCFG_VBDEN_Msk                  (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk       /*!< Secondary detection (SD) mode enable */
+
+/********************  Bit definition forUSB_OTG_GPWRDN) register  ********************/
+#define USB_OTG_GPWRDN_ADPMEN_Pos                (0U)
+#define USB_OTG_GPWRDN_ADPMEN_Msk                (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */
+#define USB_OTG_GPWRDN_ADPMEN                    USB_OTG_GPWRDN_ADPMEN_Msk     /*!< ADP module enable */
+#define USB_OTG_GPWRDN_ADPIF_Pos                 (23U)
+#define USB_OTG_GPWRDN_ADPIF_Msk                 (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */
+#define USB_OTG_GPWRDN_ADPIF                     USB_OTG_GPWRDN_ADPIF_Msk      /*!< ADP Interrupt flag */
+
+/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
+
+/********************  Bit definition forUSB_OTG_CID register  ********************/
+#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)
+#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */
+
+/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/
+#define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)
+#define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
+#define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /*!< LPM support enable                                     */
+#define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)
+#define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
+#define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /*!< LPM Token acknowledge enable                           */
+#define USB_OTG_GLPMCFG_BESL_Pos                 (2U)
+#define USB_OTG_GLPMCFG_BESL_Msk                 (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
+#define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /*!< BESL value received with last ACKed LPM Token          */
+#define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)
+#define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
+#define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /*!< bRemoteWake value received with last ACKed LPM Token   */
+#define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)
+#define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /*!< L1 shallow sleep enable                                */
+#define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)
+#define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
+#define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /*!< BESL threshold                                         */
+#define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)
+#define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
+#define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /*!< L1 deep sleep enable                                   */
+#define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)
+#define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
+#define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /*!< LPM response                                           */
+#define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)
+#define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /*!< Port sleep status                                      */
+#define USB_OTG_GLPMCFG_L1RSMOK_Pos              (16U)
+#define USB_OTG_GLPMCFG_L1RSMOK_Msk              (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
+#define USB_OTG_GLPMCFG_L1RSMOK                  USB_OTG_GLPMCFG_L1RSMOK_Msk   /*!< Sleep State Resume OK                                  */
+#define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)
+#define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /*!< LPM Channel Index                                      */
+#define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)
+#define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
+#define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /*!< LPM retry count                                        */
+#define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)
+#define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /*!< Send LPM transaction                                   */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status                                 */
+#define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)
+#define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
+#define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /*!< Enable best effort service latency                     */
+
+/********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)
+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)
+#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)
+#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)
+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+
+/********************  Bit definition forUSB_OTG_HPRT register  ********************/
+#define USB_OTG_HPRT_PCSTS_Pos                   (0U)
+#define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */
+#define USB_OTG_HPRT_PCDET_Pos                   (1U)
+#define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */
+#define USB_OTG_HPRT_PENA_Pos                    (2U)
+#define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
+#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */
+#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)
+#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
+#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA_Pos                    (4U)
+#define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
+#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */
+#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)
+#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
+#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */
+#define USB_OTG_HPRT_PRES_Pos                    (6U)
+#define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
+#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume   */
+#define USB_OTG_HPRT_PSUSP_Pos                   (7U)
+#define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
+#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend  */
+#define USB_OTG_HPRT_PRST_Pos                    (8U)
+#define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
+#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset    */
+
+#define USB_OTG_HPRT_PLSTS_Pos                   (10U)
+#define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
+#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
+#define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_HPRT_PPWR_Pos                    (12U)
+#define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL_Pos                   (13U)
+#define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
+#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
+#define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
+#define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
+#define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_HPRT_PSPD_Pos                    (17U)
+#define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
+#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
+
+/********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)
+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)
+#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)
+#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)
+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)
+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)
+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
+
+/********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)
+#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)
+#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth */
+
+/********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/
+#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)
+#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)
+#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)
+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)
+#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)
+#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DIEPCTL_STALL_Pos                (21U)
+#define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)
+#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
+#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
+#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
+#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)
+#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)
+#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)
+#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)
+#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)
+#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable */
+
+/********************  Bit definition forUSB_OTG_HCCHAR register  ********************/
+#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)
+#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)
+#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
+#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
+#define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)
+#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)
+#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)
+#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
+
+#define USB_OTG_HCCHAR_MC_Pos                    (20U)
+#define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
+#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
+#define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
+
+#define USB_OTG_HCCHAR_DAD_Pos                   (22U)
+#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
+#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
+#define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
+#define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
+#define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
+#define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
+#define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
+#define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
+#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)
+#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)
+#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)
+#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */
+
+/********************  Bit definition forUSB_OTG_HCSPLT register  ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)
+#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
+#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
+
+#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)
+#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
+#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
+
+#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)
+#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
+#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)
+#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
+#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)
+#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */
+
+/********************  Bit definition forUSB_OTG_HCINT register  ********************/
+#define USB_OTG_HCINT_XFRC_Pos                   (0U)
+#define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH_Pos                    (1U)
+#define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR_Pos                 (2U)
+#define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */
+#define USB_OTG_HCINT_STALL_Pos                  (3U)
+#define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK_Pos                    (4U)
+#define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK_Pos                    (5U)
+#define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET_Pos                   (6U)
+#define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR_Pos                  (7U)
+#define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR_Pos                  (8U)
+#define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR_Pos                  (9U)
+#define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR_Pos                  (10U)
+#define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */
+
+/********************  Bit definition forUSB_OTG_DIEPINT register  ********************/
+#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)
+#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)
+#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_AHBERR_Pos               (2U)
+#define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */
+#define USB_OTG_DIEPINT_TOC_Pos                  (3U)
+#define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)
+#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNM_Pos               (5U)
+#define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */
+#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)
+#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)
+#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
+#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA_Pos                  (9U)
+#define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)
+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR_Pos                 (12U)
+#define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK_Pos                  (13U)
+#define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */
+
+/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/
+#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)
+#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)
+#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)
+#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)
+#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)
+#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)
+#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET_Pos                (6U)
+#define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)
+#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)
+#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)
+#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)
+#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */
+
+/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)
+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)
+#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */
+/********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)
+#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)
+#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)
+#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)
+#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
+#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/
+#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)
+#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */
+
+/********************  Bit definition forUSB_OTG_HCDMA register  ********************/
+#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)
+#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */
+
+/********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)
+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
+
+/********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)
+#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)
+#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */
+
+/********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)
+#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)
+#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)
+#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)
+#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)
+#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)
+#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
+#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL_Pos                (21U)
+#define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)
+#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)
+#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)
+#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)
+#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */
+
+/********************  Bit definition forUSB_OTG_DOEPINT register  ********************/
+#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)
+#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)
+#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_AHBERR_Pos               (2U)
+#define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */
+#define USB_OTG_DOEPINT_STUP_Pos                 (3U)
+#define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)
+#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)
+#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< OUT Status Phase Received interrupt */
+#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)
+#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)
+#define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */
+#define USB_OTG_DOEPINT_BERR_Pos                 (12U)
+#define USB_OTG_DOEPINT_BERR_Msk                 (0x1UL << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPINT_BERR                      USB_OTG_DOEPINT_BERR_Msk   /*!< Babble error interrupt */
+#define USB_OTG_DOEPINT_NAK_Pos                  (13U)
+#define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */
+#define USB_OTG_DOEPINT_NYET_Pos                 (14U)
+#define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */
+#define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)
+#define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */
+
+/********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)
+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for PCGCCTL register  ********************/
+#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)
+#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)
+#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)
+#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+                                       ((INSTANCE) == ADC2) || \
+                                       ((INSTANCE) == ADC3))
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON) ||\
+                                          ((INSTANCE) == ADC3_COMMON))
+
+/******************************** COMP Instances ******************************/
+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
+                                       ((INSTANCE) == COMP2))
+
+#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
+/******************** COMP Instances with window mode capability **************/
+#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
+
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
+/******************************* DCMI Instances *******************************/
+#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
+
+/******************************* DELAYBLOCK Instances *******************************/
+#define IS_DLYB_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DLYB_SDMMC1) || \
+                                         ((INSTANCE) == DLYB_SDMMC2) || \
+                                         ((INSTANCE) == DLYB_QUADSPI))
+/****************************** DFSDM Instances *******************************/
+#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
+                                               ((INSTANCE) == DFSDM1_Filter1) || \
+                                               ((INSTANCE) == DFSDM1_Filter2) || \
+                                               ((INSTANCE) == DFSDM1_Filter3))
+
+#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
+                                                 ((INSTANCE) == DFSDM1_Channel1) || \
+                                                 ((INSTANCE) == DFSDM1_Channel2) || \
+                                                 ((INSTANCE) == DFSDM1_Channel3) || \
+                                                 ((INSTANCE) == DFSDM1_Channel4) || \
+                                                 ((INSTANCE) == DFSDM1_Channel5) || \
+                                                 ((INSTANCE) == DFSDM1_Channel6) || \
+                                                 ((INSTANCE) == DFSDM1_Channel7))
+/****************************** RAMECC Instances ******************************/
+#define IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMECC1_Monitor1)   || \
+                                                  ((INSTANCE) == RAMECC1_Monitor2)   || \
+                                                  ((INSTANCE) == RAMECC1_Monitor3)   || \
+                                                  ((INSTANCE) == RAMECC1_Monitor4)   || \
+                                                  ((INSTANCE) == RAMECC1_Monitor5)   || \
+                                                  ((INSTANCE) == RAMECC2_Monitor1)   || \
+                                                  ((INSTANCE) == RAMECC2_Monitor2)   || \
+                                                  ((INSTANCE) == RAMECC2_Monitor3)   || \
+                                                  ((INSTANCE) == RAMECC2_Monitor4)   || \
+                                                  ((INSTANCE) == RAMECC2_Monitor5)   || \
+                                                  ((INSTANCE) == RAMECC3_Monitor1)   || \
+                                                  ((INSTANCE) == RAMECC3_Monitor2))
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \
+                                       ((INSTANCE) == DMA1_Stream1)   || \
+                                       ((INSTANCE) == DMA1_Stream2)   || \
+                                       ((INSTANCE) == DMA1_Stream3)   || \
+                                       ((INSTANCE) == DMA1_Stream4)   || \
+                                       ((INSTANCE) == DMA1_Stream5)   || \
+                                       ((INSTANCE) == DMA1_Stream6)   || \
+                                       ((INSTANCE) == DMA1_Stream7)   || \
+                                       ((INSTANCE) == DMA2_Stream0)   || \
+                                       ((INSTANCE) == DMA2_Stream1)   || \
+                                       ((INSTANCE) == DMA2_Stream2)   || \
+                                       ((INSTANCE) == DMA2_Stream3)   || \
+                                       ((INSTANCE) == DMA2_Stream4)   || \
+                                       ((INSTANCE) == DMA2_Stream5)   || \
+                                       ((INSTANCE) == DMA2_Stream6)   || \
+                                       ((INSTANCE) == DMA2_Stream7)   || \
+                                       ((INSTANCE) == BDMA_Channel0) || \
+                                       ((INSTANCE) == BDMA_Channel1) || \
+                                       ((INSTANCE) == BDMA_Channel2) || \
+                                       ((INSTANCE) == BDMA_Channel3) || \
+                                       ((INSTANCE) == BDMA_Channel4) || \
+                                       ((INSTANCE) == BDMA_Channel5) || \
+                                       ((INSTANCE) == BDMA_Channel6) || \
+                                       ((INSTANCE) == BDMA_Channel7))
+
+/****************************** BDMA CHANNEL Instances ***************************/
+#define IS_BDMA_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == BDMA_Channel0) || \
+                                            ((INSTANCE) == BDMA_Channel1) || \
+                                            ((INSTANCE) == BDMA_Channel2) || \
+                                            ((INSTANCE) == BDMA_Channel3) || \
+                                            ((INSTANCE) == BDMA_Channel4) || \
+                                            ((INSTANCE) == BDMA_Channel5) || \
+                                            ((INSTANCE) == BDMA_Channel6) || \
+                                            ((INSTANCE) == BDMA_Channel7))
+
+/****************************** DMA DMAMUX ALL Instances ***************************/
+#define IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)    || \
+                                               ((INSTANCE) == DMA1_Stream1)    || \
+                                               ((INSTANCE) == DMA1_Stream2)    || \
+                                               ((INSTANCE) == DMA1_Stream3)    || \
+                                               ((INSTANCE) == DMA1_Stream4)    || \
+                                               ((INSTANCE) == DMA1_Stream5)    || \
+                                               ((INSTANCE) == DMA1_Stream6)    || \
+                                               ((INSTANCE) == DMA1_Stream7)    || \
+                                               ((INSTANCE) == DMA2_Stream0)    || \
+                                               ((INSTANCE) == DMA2_Stream1)    || \
+                                               ((INSTANCE) == DMA2_Stream2)    || \
+                                               ((INSTANCE) == DMA2_Stream3)    || \
+                                               ((INSTANCE) == DMA2_Stream4)    || \
+                                               ((INSTANCE) == DMA2_Stream5)    || \
+                                               ((INSTANCE) == DMA2_Stream6)    || \
+                                               ((INSTANCE) == DMA2_Stream7)    || \
+                                               ((INSTANCE) == BDMA_Channel0)   || \
+                                               ((INSTANCE) == BDMA_Channel1)   || \
+                                               ((INSTANCE) == BDMA_Channel2)   || \
+                                               ((INSTANCE) == BDMA_Channel3)   || \
+                                               ((INSTANCE) == BDMA_Channel4)   || \
+                                               ((INSTANCE) == BDMA_Channel5)   || \
+                                               ((INSTANCE) == BDMA_Channel6)   || \
+                                               ((INSTANCE) == BDMA_Channel7))
+
+/****************************** BDMA DMAMUX Instances ***************************/
+#define IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == BDMA_Channel0) || \
+                                                    ((INSTANCE) == BDMA_Channel1) || \
+                                                    ((INSTANCE) == BDMA_Channel2) || \
+                                                    ((INSTANCE) == BDMA_Channel3) || \
+                                                    ((INSTANCE) == BDMA_Channel4) || \
+                                                    ((INSTANCE) == BDMA_Channel5) || \
+                                                    ((INSTANCE) == BDMA_Channel6) || \
+                                                    ((INSTANCE) == BDMA_Channel7))
+
+/****************************** DMA STREAM Instances ***************************/
+#define IS_DMA_STREAM_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \
+                                          ((INSTANCE) == DMA1_Stream1)   || \
+                                          ((INSTANCE) == DMA1_Stream2)   || \
+                                          ((INSTANCE) == DMA1_Stream3)   || \
+                                          ((INSTANCE) == DMA1_Stream4)   || \
+                                          ((INSTANCE) == DMA1_Stream5)   || \
+                                          ((INSTANCE) == DMA1_Stream6)   || \
+                                          ((INSTANCE) == DMA1_Stream7)   || \
+                                          ((INSTANCE) == DMA2_Stream0)   || \
+                                          ((INSTANCE) == DMA2_Stream1)   || \
+                                          ((INSTANCE) == DMA2_Stream2)   || \
+                                          ((INSTANCE) == DMA2_Stream3)   || \
+                                          ((INSTANCE) == DMA2_Stream4)   || \
+                                          ((INSTANCE) == DMA2_Stream5)   || \
+                                          ((INSTANCE) == DMA2_Stream6)   || \
+                                          ((INSTANCE) == DMA2_Stream7))
+
+/****************************** DMA DMAMUX Instances ***************************/
+#define IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)   || \
+                                                  ((INSTANCE) == DMA1_Stream1)   || \
+                                                  ((INSTANCE) == DMA1_Stream2)   || \
+                                                  ((INSTANCE) == DMA1_Stream3)   || \
+                                                  ((INSTANCE) == DMA1_Stream4)   || \
+                                                  ((INSTANCE) == DMA1_Stream5)   || \
+                                                  ((INSTANCE) == DMA1_Stream6)   || \
+                                                  ((INSTANCE) == DMA1_Stream7)   || \
+                                                  ((INSTANCE) == DMA2_Stream0)   || \
+                                                  ((INSTANCE) == DMA2_Stream1)   || \
+                                                  ((INSTANCE) == DMA2_Stream2)   || \
+                                                  ((INSTANCE) == DMA2_Stream3)   || \
+                                                  ((INSTANCE) == DMA2_Stream4)   || \
+                                                  ((INSTANCE) == DMA2_Stream5)   || \
+                                                  ((INSTANCE) == DMA2_Stream6)   || \
+                                                  ((INSTANCE) == DMA2_Stream7))
+
+/******************************** DMA Request Generator Instances **************/
+#define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator1) || \
+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator2) || \
+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator3) || \
+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator4) || \
+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator5) || \
+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator6) || \
+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator7) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator0) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator1) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator2) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator3) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator4) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator5) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator6) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator7))
+
+/******************************* DMA2D Instances *******************************/
+#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
+
+/******************************** MDMA Request Generator Instances **************/
+#define IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDMA_Channel0)  || \
+                                               ((INSTANCE) == MDMA_Channel1)  || \
+                                               ((INSTANCE) == MDMA_Channel2)  || \
+                                               ((INSTANCE) == MDMA_Channel3)  || \
+                                               ((INSTANCE) == MDMA_Channel4)  || \
+                                               ((INSTANCE) == MDMA_Channel5)  || \
+                                               ((INSTANCE) == MDMA_Channel6)  || \
+                                               ((INSTANCE) == MDMA_Channel7)  || \
+                                               ((INSTANCE) == MDMA_Channel8)  || \
+                                               ((INSTANCE) == MDMA_Channel9)  || \
+                                               ((INSTANCE) == MDMA_Channel10) || \
+                                               ((INSTANCE) == MDMA_Channel11) || \
+                                               ((INSTANCE) == MDMA_Channel12) || \
+                                               ((INSTANCE) == MDMA_Channel13) || \
+                                               ((INSTANCE) == MDMA_Channel14) || \
+                                               ((INSTANCE) == MDMA_Channel15))
+
+/******************************* QUADSPI Instances *******************************/
+#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
+
+/******************************* FDCAN Instances ******************************/
+#define IS_FDCAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == FDCAN1) || \
+                                             ((__INSTANCE__) == FDCAN2))
+
+#define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1)
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+                                        ((INSTANCE) == GPIOB) || \
+                                        ((INSTANCE) == GPIOC) || \
+                                        ((INSTANCE) == GPIOD) || \
+                                        ((INSTANCE) == GPIOE) || \
+                                        ((INSTANCE) == GPIOF) || \
+                                        ((INSTANCE) == GPIOG) || \
+                                        ((INSTANCE) == GPIOH) || \
+                                        ((INSTANCE) == GPIOI) || \
+                                        ((INSTANCE) == GPIOJ) || \
+                                        ((INSTANCE) == GPIOK))
+
+/******************************* GPIO AF Instances ****************************/
+#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/**************************** GPIO Lock Instances *****************************/
+/* On H7, all GPIO Bank support the Lock mechanism */
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/******************************** HSEM Instances *******************************/
+#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)
+#define HSEM_CPU1_COREID         (0x00000003U) /* Semaphore Core CM7 ID */
+#define HSEM_CR_COREID_CPU1      (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
+#define HSEM_CR_COREID_CURRENT   (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
+
+#define HSEM_SEMID_MIN     (0U)       /* HSEM ID Min*/
+#define HSEM_SEMID_MAX     (31U)      /* HSEM ID Max */
+
+#define HSEM_PROCESSID_MIN (0U)       /* HSEM Process ID Min */
+#define HSEM_PROCESSID_MAX (255U)     /* HSEM Process ID Max */
+
+#define HSEM_CLEAR_KEY_MIN (0U)       /* HSEM clear Key Min value */
+#define HSEM_CLEAR_KEY_MAX (0xFFFFU)  /* HSEM clear Key Max value */
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+                                       ((INSTANCE) == I2C2) || \
+                                       ((INSTANCE) == I2C3) || \
+                                       ((INSTANCE) == I2C4))
+/************** I2C Instances : wakeup capability from stop modes *************/
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
+
+/****************************** SMBUS Instances *******************************/
+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+                                         ((INSTANCE) == I2C2) || \
+                                         ((INSTANCE) == I2C3) || \
+                                         ((INSTANCE) == I2C4))
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE)   (((INSTANCE) == SPI1) || \
+                                         ((INSTANCE) == SPI2) || \
+                                         ((INSTANCE) == SPI3))
+
+/****************************** LTDC Instances ********************************/
+#define IS_LTDC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == LTDC)
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
+
+/****************************** SDMMC Instances *********************************/
+#define IS_SDMMC_ALL_INSTANCE(_INSTANCE_) (((_INSTANCE_) == SDMMC1) || \
+                                           ((_INSTANCE_) == SDMMC2))
+
+/******************************** SMBUS Instances *****************************/
+#define IS_SMBUS_INSTANCE(INSTANCE)  ((INSTANCE) == I2C1)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+                                       ((INSTANCE) == SPI2) || \
+                                       ((INSTANCE) == SPI3) || \
+                                       ((INSTANCE) == SPI4) || \
+                                       ((INSTANCE) == SPI5) || \
+                                       ((INSTANCE) == SPI6))
+
+#define IS_SPI_HIGHEND_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+                                           ((INSTANCE) == SPI2) || \
+                                           ((INSTANCE) == SPI3))
+
+/******************************** SWPMI Instances *****************************/
+#define IS_SWPMI_INSTANCE(INSTANCE)  ((INSTANCE) == SWPMI1)
+
+/****************** LPTIM Instances : All supported instances *****************/
+#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \
+                                         ((INSTANCE) == LPTIM2) || \
+                                         ((INSTANCE) == LPTIM3) || \
+                                         ((INSTANCE) == LPTIM4) || \
+                                         ((INSTANCE) == LPTIM5))
+
+/****************** LPTIM Instances : supporting encoder interface **************/
+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \
+                                                           ((INSTANCE) == LPTIM2))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM6)   || \
+                                         ((INSTANCE) == TIM7)   || \
+                                         ((INSTANCE) == TIM8)   || \
+                                         ((INSTANCE) == TIM12)  || \
+                                         ((INSTANCE) == TIM13)  || \
+                                         ((INSTANCE) == TIM14)  || \
+                                         ((INSTANCE) == TIM15)  || \
+                                         ((INSTANCE) == TIM16)  || \
+                                         ((INSTANCE) == TIM17))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8)   || \
+                                         ((INSTANCE) == TIM12)  || \
+                                         ((INSTANCE) == TIM13)  || \
+                                         ((INSTANCE) == TIM14)  || \
+                                         ((INSTANCE) == TIM15)  || \
+                                         ((INSTANCE) == TIM16)  || \
+                                         ((INSTANCE) == TIM17))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8)   || \
+                                         ((INSTANCE) == TIM12)  || \
+                                         ((INSTANCE) == TIM15))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 5 capture/compare channels *************/
+#define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM8))
+/************ TIM Instances : at least 6 capture/compare channels *************/
+#define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
+                                                ((__INSTANCE__) == TIM8))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8)   || \
+                                         ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \
+                                           ((INSTANCE) == TIM2)   || \
+                                           ((INSTANCE) == TIM3)   || \
+                                           ((INSTANCE) == TIM4)   || \
+                                           ((INSTANCE) == TIM5)   || \
+                                           ((INSTANCE) == TIM6)   || \
+                                           ((INSTANCE) == TIM7)   || \
+                                           ((INSTANCE) == TIM8)   || \
+                                           ((INSTANCE) == TIM15)  || \
+                                           ((INSTANCE) == TIM16)  || \
+                                           ((INSTANCE) == TIM17))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM5)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15)  || \
+                                            ((INSTANCE) == TIM16)  || \
+                                            ((INSTANCE) == TIM17))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM5)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM5)   || \
+                                            ((INSTANCE) == TIM8))
+
+/*************** TIM Instances : external trigger reamp input available *******/
+#define IS_TIM_ETR_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \
+                                           ((INSTANCE) == TIM2)   || \
+                                           ((INSTANCE) == TIM3)   || \
+                                           ((INSTANCE) == TIM4)   || \
+                                           ((INSTANCE) == TIM5)   || \
+                                           ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
+                                          ((INSTANCE) == TIM2)  || \
+                                          ((INSTANCE) == TIM3)  || \
+                                          ((INSTANCE) == TIM5)  || \
+                                          ((INSTANCE) == TIM8)  || \
+                                          ((INSTANCE) == TIM16) || \
+                                          ((INSTANCE) == TIM17))
+
+/*************** TIM Instances : external trigger reamp input available *******/
+#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \
+                                              ((INSTANCE) == TIM2)   || \
+                                              ((INSTANCE) == TIM3)   || \
+                                              ((INSTANCE) == TIM5)   || \
+                                              ((INSTANCE) == TIM8))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM5)   || \
+                                            ((INSTANCE) == TIM6)   || \
+                                            ((INSTANCE) == TIM7)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15))
+
+/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                           ((INSTANCE) == TIM2)   || \
+                                           ((INSTANCE) == TIM3)   || \
+                                           ((INSTANCE) == TIM4)   || \
+                                           ((INSTANCE) == TIM5)   || \
+                                           ((INSTANCE) == TIM8)   || \
+                                           ((INSTANCE) == TIM12))
+
+/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
+#define IS_TIM_TRGO2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                           ((INSTANCE) == TIM8))
+
+/****** TIM Instances : TISEL available (TIMx_TISEL available )*********/
+#define IS_TIM_TISEL_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)   || \
+                                          ((INSTANCE) == TIM2)   || \
+                                          ((INSTANCE) == TIM3)   || \
+                                          ((INSTANCE) == TIM4)   || \
+                                          ((INSTANCE) == TIM5)   || \
+                                          ((INSTANCE) == TIM8)   || \
+                                          ((INSTANCE) == TIM15)  || \
+                                          ((INSTANCE) == TIM16)  || \
+                                          ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting commutation event *************/
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)    || \
+                                                     ((INSTANCE) == TIM8)    || \
+                                                     ((INSTANCE) == TIM15)   || \
+                                                     ((INSTANCE) == TIM16)   || \
+                                                     ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1)  || \
+                                                      ((__INSTANCE__) == TIM2)      || \
+                                                      ((__INSTANCE__) == TIM3)      || \
+                                                      ((__INSTANCE__) == TIM4)      || \
+                                                      ((__INSTANCE__) == TIM5)      || \
+                                                      ((__INSTANCE__) == TIM8))
+
+/****** TIM Instances : TIM_CCR5_GC5C available (TIMx_CCR5.GC5C available )*********/
+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                                       ((INSTANCE) == TIM8))
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+    ((((INSTANCE) == TIM1) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4) ||          \
+      ((CHANNEL) == TIM_CHANNEL_5) ||          \
+      ((CHANNEL) == TIM_CHANNEL_6)))           \
+     ||                                        \
+     (((INSTANCE) == TIM2) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+  ||                                           \
+      (((INSTANCE) == TIM3) &&                 \
+      (((CHANNEL) == TIM_CHANNEL_1)||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+  ||                                           \
+      (((INSTANCE) == TIM4) &&                 \
+      (((CHANNEL) == TIM_CHANNEL_1) ||         \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+  ||                                           \
+      (((INSTANCE) == TIM5) &&                 \
+      (((CHANNEL) == TIM_CHANNEL_1) ||         \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+  ||                                           \
+      (((INSTANCE) == TIM8) &&                 \
+      (((CHANNEL) == TIM_CHANNEL_1) ||         \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4) ||          \
+      ((CHANNEL) == TIM_CHANNEL_5) ||          \
+      ((CHANNEL) == TIM_CHANNEL_6)))           \
+  ||                                           \
+     (((INSTANCE) == TIM12) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2)))           \
+  ||                                           \
+     (((INSTANCE) == TIM13) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+  ||                                           \
+     (((INSTANCE) == TIM14) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+  ||                                           \
+     (((INSTANCE) == TIM15) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+     ((CHANNEL) == TIM_CHANNEL_2)))            \
+  ||                                           \
+     (((INSTANCE) == TIM16) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+  ||                                           \
+     (((INSTANCE) == TIM17) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1))))
+
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
+      (((INSTANCE) == TIM1)    || \
+      ((INSTANCE) == TIM8)     || \
+       ((INSTANCE) == TIM15)   || \
+       ((INSTANCE) == TIM16)   || \
+       ((INSTANCE) == TIM17))
+
+/************** TIM Instances : supporting Break source selection *************/
+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                               ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting complementary output(s) ********/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+   ((((INSTANCE) == TIM1) &&                    \
+     (((CHANNEL) == TIM_CHANNEL_1) ||           \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3)))            \
+ ||                                             \
+      (((INSTANCE) == TIM8) &&                  \
+      (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3)))            \
+    ||                                          \
+    (((INSTANCE) == TIM15) &&                   \
+      ((CHANNEL) == TIM_CHANNEL_1))             \
+    ||                                          \
+    (((INSTANCE) == TIM16) &&                   \
+     ((CHANNEL) == TIM_CHANNEL_1))              \
+    ||                                          \
+    (((INSTANCE) == TIM17) &&                   \
+     ((CHANNEL) == TIM_CHANNEL_1)))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM5)    || \
+   ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM15)   || \
+   ((INSTANCE) == TIM16)   || \
+   ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting synchronization ****************/
+#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
+    (((__INSTANCE__) == TIM1)    || \
+     ((__INSTANCE__) == TIM2)    || \
+     ((__INSTANCE__) == TIM3)    || \
+     ((__INSTANCE__) == TIM4)    || \
+     ((__INSTANCE__) == TIM5)    || \
+     ((__INSTANCE__) == TIM6)    || \
+     ((__INSTANCE__) == TIM8)    || \
+     ((__INSTANCE__) == TIM12)   || \
+     ((__INSTANCE__) == TIM15))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM5)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM15)   || \
+   ((INSTANCE) == TIM16)   || \
+   ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting external clock mode 1 for ETRF input */
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM5)    || \
+   ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting external clock mode 2 **********/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1)     || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM5)    || \
+   ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM5)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM5)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3))
+
+/****************** TIM Instances : TIM_32B_COUNTER ***************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : TIM_BKIN2 ***************************/
+#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting Hall sensor interface **********/
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1)  || \
+                                                             ((__INSTANCE__) == TIM2)  || \
+                                                             ((__INSTANCE__) == TIM3)  || \
+                                                             ((__INSTANCE__) == TIM4)  || \
+                                                             ((__INSTANCE__) == TIM5)  || \
+                                                             ((__INSTANCE__) == TIM15) || \
+                                                             ((__INSTANCE__) == TIM8))
+
+/****************************** HRTIM Instances *******************************/
+#define IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                     ((INSTANCE) == USART2) || \
+                                     ((INSTANCE) == USART3) || \
+                                     ((INSTANCE) == USART6))
+
+/******************** USART Instances : SPI slave mode ************************/
+#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                              ((INSTANCE) == USART2) || \
+                                              ((INSTANCE) == USART3) || \
+                                              ((INSTANCE) == USART6))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                    ((INSTANCE) == USART2) || \
+                                    ((INSTANCE) == USART3) || \
+                                    ((INSTANCE) == UART4)  || \
+                                    ((INSTANCE) == UART5)  || \
+                                    ((INSTANCE) == USART6) || \
+                                    ((INSTANCE) == UART7)  || \
+                                    ((INSTANCE) == UART8))
+
+/******************** UART Instances : FIFO mode.******************************/
+#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                         ((INSTANCE) == USART2) || \
+                                         ((INSTANCE) == USART3) || \
+                                         ((INSTANCE) == UART4)  || \
+                                         ((INSTANCE) == UART5)  || \
+                                         ((INSTANCE) == USART6) || \
+                                         ((INSTANCE) == UART7)  || \
+                                         ((INSTANCE) == UART8))
+
+/****************** UART Instances : Auto Baud Rate detection *****************/
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                                            ((INSTANCE) == USART2) || \
+                                                            ((INSTANCE) == USART3) || \
+                                                            ((INSTANCE) == UART4)  || \
+                                                            ((INSTANCE) == UART5)  || \
+                                                            ((INSTANCE) == USART6) || \
+                                                            ((INSTANCE) == UART7)  || \
+                                                            ((INSTANCE) == UART8))
+
+/*********************** UART Instances : Driver Enable ***********************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                                  ((INSTANCE) == USART2) || \
+                                                  ((INSTANCE) == USART3) || \
+                                                  ((INSTANCE) == UART4)  || \
+                                                  ((INSTANCE) == UART5)  || \
+                                                  ((INSTANCE) == USART6) || \
+                                                  ((INSTANCE) == UART7)  || \
+                                                  ((INSTANCE) == UART8)  || \
+                                                  ((INSTANCE) == LPUART1))
+
+/********************* UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                               ((INSTANCE) == USART2) || \
+                                               ((INSTANCE) == USART3) || \
+                                               ((INSTANCE) == UART4)  || \
+                                               ((INSTANCE) == UART5)  || \
+                                               ((INSTANCE) == USART6) || \
+                                               ((INSTANCE) == UART7)  || \
+                                               ((INSTANCE) == UART8)  || \
+                                               ((INSTANCE) == LPUART1))
+
+/******************* UART Instances : Hardware Flow control *******************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                           ((INSTANCE) == USART2) || \
+                                           ((INSTANCE) == USART3) || \
+                                           ((INSTANCE) == UART4)  || \
+                                           ((INSTANCE) == UART5)  || \
+                                           ((INSTANCE) == USART6) || \
+                                           ((INSTANCE) == UART7)  || \
+                                           ((INSTANCE) == UART8)  || \
+                                           ((INSTANCE) == LPUART1))
+
+/************************* UART Instances : LIN mode **************************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                        ((INSTANCE) == USART2) || \
+                                        ((INSTANCE) == USART3) || \
+                                        ((INSTANCE) == UART4)  || \
+                                        ((INSTANCE) == UART5)  || \
+                                        ((INSTANCE) == USART6) || \
+                                        ((INSTANCE) == UART7)  || \
+                                        ((INSTANCE) == UART8))
+
+/****************** UART Instances : Wake-up from Stop mode *******************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                                    ((INSTANCE) == USART2) || \
+                                                    ((INSTANCE) == USART3) || \
+                                                    ((INSTANCE) == UART4)  || \
+                                                    ((INSTANCE) == UART5)  || \
+                                                    ((INSTANCE) == USART6) || \
+                                                    ((INSTANCE) == UART7)  || \
+                                                    ((INSTANCE) == UART8)  || \
+                                                    ((INSTANCE) == LPUART1))
+
+/************************* UART Instances : IRDA mode *************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                    ((INSTANCE) == USART2) || \
+                                    ((INSTANCE) == USART3) || \
+                                    ((INSTANCE) == UART4)  || \
+                                    ((INSTANCE) == UART5)  || \
+                                    ((INSTANCE) == USART6) || \
+                                    ((INSTANCE) == UART7)  || \
+                                    ((INSTANCE) == UART8))
+
+/********************* USART Instances : Smard card mode **********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                         ((INSTANCE) == USART2) || \
+                                         ((INSTANCE) == USART3) || \
+                                         ((INSTANCE) == USART6))
+
+/****************************** LPUART Instance *******************************/
+#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG1)
+/****************************** USB Instances ********************************/
+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG1)
+/****************************** MDIOS Instances ********************************/
+#define IS_MDIOS_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == MDIOS)
+
+/****************************** CEC Instances *********************************/
+#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
+
+/****************************** SAI Instances ********************************/
+#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
+                    ((INSTANCE) == SAI1_Block_B) || \
+                     ((INSTANCE) == SAI2_Block_A) || \
+                     ((INSTANCE) == SAI2_Block_B) || \
+                     ((INSTANCE) == SAI3_Block_A) || \
+                     ((INSTANCE) == SAI3_Block_B) || \
+                     ((INSTANCE) == SAI4_Block_A) || \
+                     ((INSTANCE) == SAI4_Block_B))
+
+/****************************** SPDIFRX Instances ********************************/
+#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)
+
+/****************************** OPAMP Instances *******************************/
+#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
+                                         ((INSTANCE) == OPAMP2))
+
+#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
+
+/*********************** USB OTG PCD Instances ********************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+                                        ((INSTANCE) == USB_OTG_HS))
+
+/*********************** USB OTG HCD Instances ********************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+                                       ((INSTANCE) == USB_OTG_HS))
+
+/******************************************************************************/
+/*  For a painless codes migration between the STM32H7xx device product       */
+/*  lines, or with STM32F7xx devices the aliases defined below are put        */
+/*   in place to overcome the differences in the interrupt handlers and IRQn  */
+/*   definitions. No need to update developed interrupt code when moving      */
+/*  across product lines within the same STM32H7 Family                       */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define  HASH_RNG_IRQn                  RNG_IRQn
+#define  TIM1_BRK_TIM9_IRQn             TIM1_BRK_IRQn
+#define  TIM1_UP_TIM10_IRQn             TIM1_UP_IRQn
+#define  TIM1_TRG_COM_TIM11_IRQn        TIM1_TRG_COM_IRQn
+#define  PVD_IRQn                       PVD_AVD_IRQn
+
+
+
+/* Aliases for __IRQHandler */
+#define  HASH_RNG_IRQHandler           RNG_IRQHandler
+#define TIM1_BRK_TIM9_IRQHandler       TIM1_BRK_IRQHandler
+#define TIM1_UP_TIM9_IRQHandler        TIM1_UP_IRQHandler
+#define TIM1_TRG_COM_TIM11_IRQHandler  TIM1_TRG_COM_IRQHandler
+#define PVD_IRQHandler                 PVD_AVD_IRQHandler
+
+/* Aliases for COMP __IRQHandler */
+#define COMP_IRQHandler                COMP1_IRQHandler
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* STM32H743xx_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h
new file mode 100644
index 00000000..f6296181
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h
@@ -0,0 +1,224 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32H7xx Device Peripheral Access Layer Header File.
+  *
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The STM32H7xx device used in the target application
+  *              - To use or not the peripheral�s drivers in application code(i.e.
+  *                code will be based on direct access to peripheral�s registers
+  *                rather than drivers API), this option is controlled by
+  *                "#define USE_HAL_DRIVER"
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32h7xx
+  * @{
+  */
+
+#ifndef STM32H7xx_H
+#define STM32H7xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+
+/**
+  * @brief STM32 Family
+  */
+#if !defined  (STM32H7)
+#define STM32H7
+#endif /* STM32H7 */
+
+
+/* Uncomment the line below according to the target STM32H7 device used in your
+   application
+  */
+
+#if !defined (STM32H743xx) && !defined (STM32H753xx)  && !defined (STM32H750xx) && !defined (STM32H742xx) && \
+    !defined (STM32H745xx) && !defined (STM32H755xx)  && !defined (STM32H747xx) && !defined (STM32H757xx) && \
+    !defined (STM32H7A3xx) && !defined (STM32H7A3xxQ) && !defined (STM32H7B3xx) && !defined (STM32H7B3xxQ) && !defined (STM32H7B0xx)  && !defined (STM32H7B0xxQ)
+  /* #define STM32H742xx */   /*!< STM32H742VI, STM32H742ZI, STM32H742AI, STM32H742II, STM32H742BI, STM32H742XI Devices */
+  /* #define STM32H743xx */   /*!< STM32H743VI, STM32H743ZI, STM32H743AI, STM32H743II, STM32H743BI, STM32H743XI Devices */
+  /* #define STM32H753xx */   /*!< STM32H753VI, STM32H753ZI, STM32H753AI, STM32H753II, STM32H753BI, STM32H753XI Devices */
+  /* #define STM32H750xx */   /*!< STM32H750V, STM32H750I, STM32H750X Devices */
+  /* #define STM32H747xx */   /*!< STM32H747ZI, STM32H747AI, STM32H747II, STM32H747BI, STM32H747XI Devices */
+  /* #define STM32H757xx */   /*!< STM32H757ZI, STM32H757AI, STM32H757II, STM32H757BI, STM32H757XI Devices */
+  /* #define STM32H745xx */   /*!< STM32H745ZI, STM32H745II, STM32H745BI, STM32H745XI Devices  */
+  /* #define STM32H755xx */   /*!< STM32H755ZI, STM32H755II, STM32H755BI, STM32H755XI Devices  */
+  /* #define STM32H7B0xx */   /*!< STM32H7B0ABIxQ, STM32H7B0IBTx, STM32H7B0RBTx, STM32H7B0VBTx, STM32H7B0ZBTx, STM32H7B0IBKxQ */
+  /* #define STM32H7A3xx */   /*!< STM32H7A3IIK6, STM32H7A3IIT6, STM32H7A3NIH6, STM32H7A3RIT6, STM32H7A3VIH6, STM32H7A3VIT6, STM32H7A3ZIT6 */
+  /* #define STM32H7A3xxQ */  /*!< STM32H7A3QIY6Q, STM32H7A3IIK6Q, STM32H7A3IIT6Q, STM32H7A3LIH6Q, STM32H7A3VIH6Q, STM32H7A3VIT6Q, STM32H7A3AII6Q, STM32H7A3ZIT6Q */
+  /* #define STM32H7B3xx */   /*!< STM32H7B3IIK6, STM32H7B3IIT6, STM32H7B3NIH6, STM32H7B3RIT6, STM32H7B3VIH6, STM32H7B3VIT6, STM32H7B3ZIT6 */
+  /* #define STM32H7B3xxQ */  /*!< STM32H7B3QIY6Q, STM32H7B3IIK6Q, STM32H7B3IIT6Q, STM32H7B3LIH6Q, STM32H7B3VIH6Q, STM32H7B3VIT6Q, STM32H7B3AII6Q, STM32H7B3ZIT6Q */
+#endif
+
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+
+#if defined(DUAL_CORE) && !defined(CORE_CM4) && !defined(CORE_CM7)
+ #error "Dual core device, please select CORE_CM4 or CORE_CM7"
+#endif
+
+#if !defined  (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will
+   be based on direct access to peripherals registers
+   */
+  /*#define USE_HAL_DRIVER */
+#endif /* USE_HAL_DRIVER */
+
+/**
+  * @brief CMSIS Device version number V1.8.0
+  */
+#define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN   (0x01) /*!< [31:24] main version */
+#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1   (0x08) /*!< [23:16] sub1 version */
+#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __STM32H7xx_CMSIS_DEVICE_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
+#define __STM32H7xx_CMSIS_DEVICE_VERSION        ((__CMSIS_DEVICE_VERSION_MAIN     << 24)\
+                                      |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
+                                      |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
+                                      |(__CMSIS_DEVICE_HAL_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Device_Included
+  * @{
+  */
+
+#if defined(STM32H743xx)
+  #include "stm32h743xx.h"
+#elif defined(STM32H753xx)
+  #include "stm32h753xx.h"
+#elif defined(STM32H750xx)
+  #include "stm32h750xx.h"
+#elif defined(STM32H742xx)
+  #include "stm32h742xx.h"
+#elif defined(STM32H745xx)
+  #include "stm32h745xx.h"
+#elif defined(STM32H755xx)
+  #include "stm32h755xx.h"
+#elif defined(STM32H747xx)
+  #include "stm32h747xx.h"
+#elif defined(STM32H757xx)
+  #include "stm32h757xx.h"
+#elif defined(STM32H7B0xx)
+  #include "stm32h7b0xx.h"
+#elif defined(STM32H7B0xxQ)
+  #include "stm32h7b0xxq.h"
+#elif defined(STM32H7A3xx)
+  #include "stm32h7a3xx.h"
+#elif defined(STM32H7B3xx)
+  #include "stm32h7b3xx.h"
+#elif defined(STM32H7A3xxQ)
+  #include "stm32h7a3xxq.h"
+#elif defined(STM32H7B3xxQ)
+  #include "stm32h7b3xxq.h"
+#else
+ #error "Please select first the target STM32H7xx device used in your application (in stm32h7xx.h file)"
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_types
+  * @{
+  */
+typedef enum
+{
+  RESET = 0,
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+  DISABLE = 0,
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+  SUCCESS = 0,
+  ERROR = !SUCCESS
+} ErrorStatus;
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL)))
+
+
+/**
+  * @}
+  */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32h7xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* STM32H7xx_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h
new file mode 100644
index 00000000..dd75af67
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h
@@ -0,0 +1,105 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32h7xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-Mx Device System Source File for STM32H7xx devices.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32h7xx_system
+  * @{
+  */
+
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef SYSTEM_STM32H7XX_H
+#define SYSTEM_STM32H7XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32H7xx_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32H7xx_System_Exported_types
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+extern uint32_t SystemCoreClock;             /*!< System Domain1 Clock Frequency  */
+extern uint32_t SystemD2Clock;               /*!< System Domain2 Clock Frequency  */
+extern const  uint8_t D1CorePrescTable[16] ; /*!< D1CorePrescTable prescalers table values */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Exported_Functions
+  * @{
+  */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_STM32H7XX_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/cmsis_armcc.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/cmsis_armcc.h
new file mode 100644
index 00000000..7d751fb3
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/cmsis_armcc.h
@@ -0,0 +1,865 @@
+/**************************************************************************//**
+ * @file     cmsis_armcc.h
+ * @brief    CMSIS compiler ARMCC (Arm Compiler 5) header file
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+  #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \
+     (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )
+  #define __ARM_ARCH_6M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))
+  #define __ARM_ARCH_7M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+  #define __ARM_ARCH_7EM__          1
+#endif
+
+  /* __ARM_ARCH_8M_BASE__  not applicable */
+  /* __ARM_ARCH_8M_MAIN__  not applicable */
+
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE                 
+  #define __STATIC_FORCEINLINE                   static __forceinline
+#endif           
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __declspec(noreturn)
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        __packed struct
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         __packed union
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #define __UNALIGNED_UINT32(x)                  (*((__packed uint32_t *)(x)))
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();     */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();    */
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  register uint32_t __regBasePriMax      __ASM("basepri_max");
+  __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#else
+  (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB() do {\
+                   __schedule_barrier();\
+                   __isb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+                   __schedule_barrier();\
+                   __dsb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+                   __schedule_barrier();\
+                   __dmb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+                  
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+  #define __RBIT                          __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value != 0U; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+  return result;
+}
+#endif
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
+#else
+  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
+#else
+  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
+#else
+  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXB(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX                           __clrex
+
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#else  /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/cmsis_armclang.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/cmsis_armclang.h
new file mode 100644
index 00000000..d8031b03
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/cmsis_armclang.h
@@ -0,0 +1,1869 @@
+/**************************************************************************//**
+ * @file     cmsis_armclang.h
+ * @brief    CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header   /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include <arm_compat.h>    /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE                 
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline
+#endif                                           
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+  
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+  
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+  return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#define __get_FPSCR      (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR()      ((uint32_t)0U)
+#endif
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#define __set_FPSCR      __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x)      ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP          __builtin_arm_nop
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI          __builtin_arm_wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE          __builtin_arm_wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV          __builtin_arm_sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB()        __builtin_arm_isb(0xF);
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()        __builtin_arm_dsb(0xF);
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB()        __builtin_arm_dmb(0xF);
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV(value)   __builtin_bswap32(value)
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U)
+  {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)     __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __RBIT            __builtin_arm_rbit
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ             (uint8_t)__builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB        (uint8_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH        (uint16_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW        (uint32_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXB        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXH        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXW        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX             __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT             __builtin_arm_ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT             __builtin_arm_usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXB                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXH                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEX                  (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+  int32_t result;
+
+  __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/cmsis_compiler.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/cmsis_compiler.h
new file mode 100644
index 00000000..79a2cac3
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/cmsis_compiler.h
@@ -0,0 +1,266 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/cmsis_gcc.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/cmsis_gcc.h
new file mode 100644
index 00000000..1bd41a49
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/cmsis_gcc.h
@@ -0,0 +1,2085 @@
+/**************************************************************************//**
+ * @file     cmsis_gcc.h
+ * @brief    CMSIS compiler GCC header file
+ * @version  V5.0.4
+ * @date     09. April 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+  #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static inline
+#endif
+#ifndef   __STATIC_FORCEINLINE                 
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
+#endif                                           
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+  
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+  
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+  return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_get_fpscr) 
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+  return __builtin_arm_get_fpscr();
+#else
+  uint32_t result;
+
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  return(result);
+#endif
+#else
+  return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_set_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+  __builtin_arm_set_fpscr(fpscr);
+#else
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#endif
+#else
+  (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP()                             __ASM volatile ("nop")
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI()                             __ASM volatile ("wfi")
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE()                             __ASM volatile ("wfe")
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV()                             __ASM volatile ("sev")
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE void __ISB(void)
+{
+  __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+  __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+  __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (int16_t)__builtin_bswap16(value);
+#else
+  int16_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U)
+  {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value != 0U; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+#endif
+  return result;
+}
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ             (uint8_t)__builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  ARG1  Value to be saturated
+  \param [in]  ARG2  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+__extension__ \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  ARG1  Value to be saturated
+  \param [in]  ARG2  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+ __extension__ \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/cmsis_iccarm.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/cmsis_iccarm.h
new file mode 100644
index 00000000..3c90a2cd
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/cmsis_iccarm.h
@@ -0,0 +1,935 @@
+/**************************************************************************//**
+ * @file     cmsis_iccarm.h
+ * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version  V5.0.7
+ * @date     19. June 2018
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2018 IAR Systems
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+  #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+  #define __ICCARM_V8 1
+#else
+  #define __ICCARM_V8 0
+#endif
+
+#ifndef __ALIGNED
+  #if __ICCARM_V8
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #elif (__VER__ >= 7080000)
+    /* Needs IAR language extensions */
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #else
+    #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
+/* Macros already defined */
+#else
+  #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
+    #if __ARM_ARCH == 6
+      #define __ARM_ARCH_6M__ 1
+    #elif __ARM_ARCH == 7
+      #if __ARM_FEATURE_DSP
+        #define __ARM_ARCH_7EM__ 1
+      #else
+        #define __ARM_ARCH_7M__ 1
+      #endif
+    #endif /* __ARM_ARCH */
+  #endif /* __ARM_ARCH_PROFILE == 'M' */
+#endif
+
+/* Alternativ core deduction for older ICCARM's */
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
+    !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
+  #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
+    #define __ARM_ARCH_6M__ 1
+  #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
+    #define __ARM_ARCH_7M__ 1
+  #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
+    #define __ARM_ARCH_7EM__  1
+  #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #else
+    #error "Unknown target."
+  #endif
+#endif
+
+
+
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
+  #define __IAR_M0_FAMILY  1
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
+  #define __IAR_M0_FAMILY  1
+#else
+  #define __IAR_M0_FAMILY  0
+#endif
+
+
+#ifndef __ASM
+  #define __ASM __asm
+#endif
+
+#ifndef __INLINE
+  #define __INLINE inline
+#endif
+
+#ifndef   __NO_RETURN
+  #if __ICCARM_V8
+    #define __NO_RETURN __attribute__((__noreturn__))
+  #else
+    #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+  #endif
+#endif
+
+#ifndef   __PACKED
+  #if __ICCARM_V8
+    #define __PACKED __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED __packed
+  #endif
+#endif
+
+#ifndef   __PACKED_STRUCT
+  #if __ICCARM_V8
+    #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_STRUCT __packed struct
+  #endif
+#endif
+
+#ifndef   __PACKED_UNION
+  #if __ICCARM_V8
+    #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_UNION __packed union
+  #endif
+#endif
+
+#ifndef   __RESTRICT
+  #define __RESTRICT            __restrict
+#endif
+
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE       static inline
+#endif
+
+#ifndef   __FORCEINLINE
+  #define __FORCEINLINE         _Pragma("inline=forced")
+#endif
+
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE  __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+{
+  return *(__packed uint16_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+{
+  *(__packed uint16_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+{
+  return *(__packed uint32_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+{
+  *(__packed uint32_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32   /* deprecated */
+#pragma language=save
+#pragma language=extended
+__packed struct  __iar_u32 { uint32_t v; };
+#pragma language=restore
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+
+#ifndef   __USED
+  #if __ICCARM_V8
+    #define __USED __attribute__((used))
+  #else
+    #define __USED _Pragma("__root")
+  #endif
+#endif
+
+#ifndef   __WEAK
+  #if __ICCARM_V8
+    #define __WEAK __attribute__((weak))
+  #else
+    #define __WEAK _Pragma("__weak")
+  #endif
+#endif
+
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+  #define __ICCARM_INTRINSICS_VERSION__  0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+  #if defined(__CLZ)
+    #undef __CLZ
+  #endif
+  #if defined(__REVSH)
+    #undef __REVSH
+  #endif
+  #if defined(__RBIT)
+    #undef __RBIT
+  #endif
+  #if defined(__SSAT)
+    #undef __SSAT
+  #endif
+  #if defined(__USAT)
+    #undef __USAT
+  #endif
+
+  #include "iccarm_builtin.h"
+
+  #define __disable_fault_irq __iar_builtin_disable_fiq
+  #define __disable_irq       __iar_builtin_disable_interrupt
+  #define __enable_fault_irq  __iar_builtin_enable_fiq
+  #define __enable_irq        __iar_builtin_enable_interrupt
+  #define __arm_rsr           __iar_builtin_rsr
+  #define __arm_wsr           __iar_builtin_wsr
+
+
+  #define __get_APSR()                (__arm_rsr("APSR"))
+  #define __get_BASEPRI()             (__arm_rsr("BASEPRI"))
+  #define __get_CONTROL()             (__arm_rsr("CONTROL"))
+  #define __get_FAULTMASK()           (__arm_rsr("FAULTMASK"))
+
+  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+    #define __get_FPSCR()             (__arm_rsr("FPSCR"))
+    #define __set_FPSCR(VALUE)        (__arm_wsr("FPSCR", (VALUE)))
+  #else
+    #define __get_FPSCR()             ( 0 )
+    #define __set_FPSCR(VALUE)        ((void)VALUE)
+  #endif
+
+  #define __get_IPSR()                (__arm_rsr("IPSR"))
+  #define __get_MSP()                 (__arm_rsr("MSP"))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __get_MSPLIM()            (0U)
+  #else
+    #define __get_MSPLIM()            (__arm_rsr("MSPLIM"))
+  #endif
+  #define __get_PRIMASK()             (__arm_rsr("PRIMASK"))
+  #define __get_PSP()                 (__arm_rsr("PSP"))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __get_PSPLIM()            (0U)
+  #else
+    #define __get_PSPLIM()            (__arm_rsr("PSPLIM"))
+  #endif
+
+  #define __get_xPSR()                (__arm_rsr("xPSR"))
+
+  #define __set_BASEPRI(VALUE)        (__arm_wsr("BASEPRI", (VALUE)))
+  #define __set_BASEPRI_MAX(VALUE)    (__arm_wsr("BASEPRI_MAX", (VALUE)))
+  #define __set_CONTROL(VALUE)        (__arm_wsr("CONTROL", (VALUE)))
+  #define __set_FAULTMASK(VALUE)      (__arm_wsr("FAULTMASK", (VALUE)))
+  #define __set_MSP(VALUE)            (__arm_wsr("MSP", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __set_MSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_MSPLIM(VALUE)       (__arm_wsr("MSPLIM", (VALUE)))
+  #endif
+  #define __set_PRIMASK(VALUE)        (__arm_wsr("PRIMASK", (VALUE)))
+  #define __set_PSP(VALUE)            (__arm_wsr("PSP", (VALUE)))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __set_PSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_PSPLIM(VALUE)       (__arm_wsr("PSPLIM", (VALUE)))
+  #endif
+
+  #define __TZ_get_CONTROL_NS()       (__arm_rsr("CONTROL_NS"))
+  #define __TZ_set_CONTROL_NS(VALUE)  (__arm_wsr("CONTROL_NS", (VALUE)))
+  #define __TZ_get_PSP_NS()           (__arm_rsr("PSP_NS"))
+  #define __TZ_set_PSP_NS(VALUE)      (__arm_wsr("PSP_NS", (VALUE)))
+  #define __TZ_get_MSP_NS()           (__arm_rsr("MSP_NS"))
+  #define __TZ_set_MSP_NS(VALUE)      (__arm_wsr("MSP_NS", (VALUE)))
+  #define __TZ_get_SP_NS()            (__arm_rsr("SP_NS"))
+  #define __TZ_set_SP_NS(VALUE)       (__arm_wsr("SP_NS", (VALUE)))
+  #define __TZ_get_PRIMASK_NS()       (__arm_rsr("PRIMASK_NS"))
+  #define __TZ_set_PRIMASK_NS(VALUE)  (__arm_wsr("PRIMASK_NS", (VALUE)))
+  #define __TZ_get_BASEPRI_NS()       (__arm_rsr("BASEPRI_NS"))
+  #define __TZ_set_BASEPRI_NS(VALUE)  (__arm_wsr("BASEPRI_NS", (VALUE)))
+  #define __TZ_get_FAULTMASK_NS()     (__arm_rsr("FAULTMASK_NS"))
+  #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __TZ_get_PSPLIM_NS()      (0U)
+    #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+  #else
+    #define __TZ_get_PSPLIM_NS()      (__arm_rsr("PSPLIM_NS"))
+    #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+  #endif
+
+  #define __TZ_get_MSPLIM_NS()        (__arm_rsr("MSPLIM_NS"))
+  #define __TZ_set_MSPLIM_NS(VALUE)   (__arm_wsr("MSPLIM_NS", (VALUE)))
+
+  #define __NOP     __iar_builtin_no_operation
+
+  #define __CLZ     __iar_builtin_CLZ
+  #define __CLREX   __iar_builtin_CLREX
+
+  #define __DMB     __iar_builtin_DMB
+  #define __DSB     __iar_builtin_DSB
+  #define __ISB     __iar_builtin_ISB
+
+  #define __LDREXB  __iar_builtin_LDREXB
+  #define __LDREXH  __iar_builtin_LDREXH
+  #define __LDREXW  __iar_builtin_LDREX
+
+  #define __RBIT    __iar_builtin_RBIT
+  #define __REV     __iar_builtin_REV
+  #define __REV16   __iar_builtin_REV16
+
+  __IAR_FT int16_t __REVSH(int16_t val)
+  {
+    return (int16_t) __iar_builtin_REVSH(val);
+  }
+
+  #define __ROR     __iar_builtin_ROR
+  #define __RRX     __iar_builtin_RRX
+
+  #define __SEV     __iar_builtin_SEV
+
+  #if !__IAR_M0_FAMILY
+    #define __SSAT    __iar_builtin_SSAT
+  #endif
+
+  #define __STREXB  __iar_builtin_STREXB
+  #define __STREXH  __iar_builtin_STREXH
+  #define __STREXW  __iar_builtin_STREX
+
+  #if !__IAR_M0_FAMILY
+    #define __USAT    __iar_builtin_USAT
+  #endif
+
+  #define __WFE     __iar_builtin_WFE
+  #define __WFI     __iar_builtin_WFI
+
+  #if __ARM_MEDIA__
+    #define __SADD8   __iar_builtin_SADD8
+    #define __QADD8   __iar_builtin_QADD8
+    #define __SHADD8  __iar_builtin_SHADD8
+    #define __UADD8   __iar_builtin_UADD8
+    #define __UQADD8  __iar_builtin_UQADD8
+    #define __UHADD8  __iar_builtin_UHADD8
+    #define __SSUB8   __iar_builtin_SSUB8
+    #define __QSUB8   __iar_builtin_QSUB8
+    #define __SHSUB8  __iar_builtin_SHSUB8
+    #define __USUB8   __iar_builtin_USUB8
+    #define __UQSUB8  __iar_builtin_UQSUB8
+    #define __UHSUB8  __iar_builtin_UHSUB8
+    #define __SADD16  __iar_builtin_SADD16
+    #define __QADD16  __iar_builtin_QADD16
+    #define __SHADD16 __iar_builtin_SHADD16
+    #define __UADD16  __iar_builtin_UADD16
+    #define __UQADD16 __iar_builtin_UQADD16
+    #define __UHADD16 __iar_builtin_UHADD16
+    #define __SSUB16  __iar_builtin_SSUB16
+    #define __QSUB16  __iar_builtin_QSUB16
+    #define __SHSUB16 __iar_builtin_SHSUB16
+    #define __USUB16  __iar_builtin_USUB16
+    #define __UQSUB16 __iar_builtin_UQSUB16
+    #define __UHSUB16 __iar_builtin_UHSUB16
+    #define __SASX    __iar_builtin_SASX
+    #define __QASX    __iar_builtin_QASX
+    #define __SHASX   __iar_builtin_SHASX
+    #define __UASX    __iar_builtin_UASX
+    #define __UQASX   __iar_builtin_UQASX
+    #define __UHASX   __iar_builtin_UHASX
+    #define __SSAX    __iar_builtin_SSAX
+    #define __QSAX    __iar_builtin_QSAX
+    #define __SHSAX   __iar_builtin_SHSAX
+    #define __USAX    __iar_builtin_USAX
+    #define __UQSAX   __iar_builtin_UQSAX
+    #define __UHSAX   __iar_builtin_UHSAX
+    #define __USAD8   __iar_builtin_USAD8
+    #define __USADA8  __iar_builtin_USADA8
+    #define __SSAT16  __iar_builtin_SSAT16
+    #define __USAT16  __iar_builtin_USAT16
+    #define __UXTB16  __iar_builtin_UXTB16
+    #define __UXTAB16 __iar_builtin_UXTAB16
+    #define __SXTB16  __iar_builtin_SXTB16
+    #define __SXTAB16 __iar_builtin_SXTAB16
+    #define __SMUAD   __iar_builtin_SMUAD
+    #define __SMUADX  __iar_builtin_SMUADX
+    #define __SMMLA   __iar_builtin_SMMLA
+    #define __SMLAD   __iar_builtin_SMLAD
+    #define __SMLADX  __iar_builtin_SMLADX
+    #define __SMLALD  __iar_builtin_SMLALD
+    #define __SMLALDX __iar_builtin_SMLALDX
+    #define __SMUSD   __iar_builtin_SMUSD
+    #define __SMUSDX  __iar_builtin_SMUSDX
+    #define __SMLSD   __iar_builtin_SMLSD
+    #define __SMLSDX  __iar_builtin_SMLSDX
+    #define __SMLSLD  __iar_builtin_SMLSLD
+    #define __SMLSLDX __iar_builtin_SMLSLDX
+    #define __SEL     __iar_builtin_SEL
+    #define __QADD    __iar_builtin_QADD
+    #define __QSUB    __iar_builtin_QSUB
+    #define __PKHBT   __iar_builtin_PKHBT
+    #define __PKHTB   __iar_builtin_PKHTB
+  #endif
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #define __CLZ  __cmsis_iar_clz_not_active
+    #define __SSAT __cmsis_iar_ssat_not_active
+    #define __USAT __cmsis_iar_usat_not_active
+    #define __RBIT __cmsis_iar_rbit_not_active
+    #define __get_APSR  __cmsis_iar_get_APSR_not_active
+  #endif
+
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+    #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
+  #endif
+
+  #ifdef __INTRINSICS_INCLUDED
+  #error intrinsics.h is already included previously!
+  #endif
+
+  #include <intrinsics.h>
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #undef __CLZ
+    #undef __SSAT
+    #undef __USAT
+    #undef __RBIT
+    #undef __get_APSR
+
+    __STATIC_INLINE uint8_t __CLZ(uint32_t data)
+    {
+      if (data == 0U) { return 32U; }
+
+      uint32_t count = 0U;
+      uint32_t mask = 0x80000000U;
+
+      while ((data & mask) == 0U)
+      {
+        count += 1U;
+        mask = mask >> 1U;
+      }
+      return count;
+    }
+
+    __STATIC_INLINE uint32_t __RBIT(uint32_t v)
+    {
+      uint8_t sc = 31U;
+      uint32_t r = v;
+      for (v >>= 1U; v; v >>= 1U)
+      {
+        r <<= 1U;
+        r |= v & 1U;
+        sc--;
+      }
+      return (r << sc);
+    }
+
+    __STATIC_INLINE  uint32_t __get_APSR(void)
+    {
+      uint32_t res;
+      __asm("MRS      %0,APSR" : "=r" (res));
+      return res;
+    }
+
+  #endif
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #undef __get_FPSCR
+    #undef __set_FPSCR
+    #define __get_FPSCR()       (0)
+    #define __set_FPSCR(VALUE)  ((void)VALUE)
+  #endif
+
+  #pragma diag_suppress=Pe940
+  #pragma diag_suppress=Pe177
+
+  #define __enable_irq    __enable_interrupt
+  #define __disable_irq   __disable_interrupt
+  #define __NOP           __no_operation
+
+  #define __get_xPSR      __get_PSR
+
+  #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
+
+    __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+    {
+      return __LDREX((unsigned long *)ptr);
+    }
+
+    __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+    {
+      return __STREX(value, (unsigned long *)ptr);
+    }
+  #endif
+
+
+  /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+  #if (__CORTEX_M >= 0x03)
+
+    __IAR_FT uint32_t __RRX(uint32_t value)
+    {
+      uint32_t result;
+      __ASM("RRX      %0, %1" : "=r"(result) : "r" (value) : "cc");
+      return(result);
+    }
+
+    __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_MAX,%0"::"r" (value));
+    }
+
+
+    #define __enable_fault_irq  __enable_fiq
+    #define __disable_fault_irq __disable_fiq
+
+
+  #endif /* (__CORTEX_M >= 0x03) */
+
+  __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+  {
+    return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+  }
+
+  #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+       (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+   __IAR_FT uint32_t __get_MSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,MSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_MSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      MSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __get_PSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,PSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_PSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      PSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,CONTROL_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_CONTROL_NS(uint32_t value)
+    {
+      __asm volatile("MSR      CONTROL_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_SP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,SP_NS" : "=r" (res));
+      return res;
+    }
+    __IAR_FT void   __TZ_set_SP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      SP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PRIMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PRIMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PRIMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PRIMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_BASEPRI_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,BASEPRI_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_BASEPRI_NS(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_FAULTMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,FAULTMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_FAULTMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      FAULTMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSPLIM_NS(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,PSPLIM_NS" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PSPLIM_NS(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      PSPLIM_NS,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSPLIM_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSPLIM_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSPLIM_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSPLIM_NS,%0" :: "r" (value));
+    }
+
+  #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#endif   /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value)    __asm volatile ("BKPT     %0" : : "i"(value))
+
+#if __IAR_M0_FAMILY
+  __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+  {
+    if ((sat >= 1U) && (sat <= 32U))
+    {
+      const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+      const int32_t min = -1 - max ;
+      if (val > max)
+      {
+        return max;
+      }
+      else if (val < min)
+      {
+        return min;
+      }
+    }
+    return val;
+  }
+
+  __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+  {
+    if (sat <= 31U)
+    {
+      const uint32_t max = ((1U << sat) - 1U);
+      if (val > (int32_t)max)
+      {
+        return max;
+      }
+      else if (val < 0)
+      {
+        return 0U;
+      }
+    }
+    return (uint32_t)val;
+  }
+#endif
+
+#if (__CORTEX_M >= 0x03)   /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+  __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
+  {
+    __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
+  {
+    __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
+  {
+    __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+  }
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+
+  __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
+  {
+    __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
+  {
+    __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
+  {
+    __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#undef __IAR_FT
+#undef __IAR_M0_FAMILY
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#endif /* __CMSIS_ICCARM_H__ */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/cmsis_version.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/cmsis_version.h
new file mode 100644
index 00000000..ae3f2e33
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/cmsis_version.h
@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 1U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/core_armv8mbl.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/core_armv8mbl.h
new file mode 100644
index 00000000..ec76ab21
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/core_armv8mbl.h
@@ -0,0 +1,1918 @@
+/**************************************************************************//**
+ * @file     core_armv8mbl.h
+ * @brief    CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File
+ * @version  V5.0.7
+ * @date     22. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MBL_H_GENERIC
+#define __CORE_ARMV8MBL_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_ARMv8MBL
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS definitions */
+#define __ARMv8MBL_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __ARMv8MBL_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __ARMv8MBL_CMSIS_VERSION       ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
+                                         __ARMv8MBL_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                     ( 2U)                                            /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MBL_H_DEPENDANT
+#define __CORE_ARMV8MBL_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __ARMv8MBL_REV
+    #define __ARMv8MBL_REV               0x0000U
+    #warning "__ARMv8MBL_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ETM_PRESENT
+    #define __ETM_PRESENT             0U
+    #warning "__ETM_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MTB_PRESENT
+    #define __MTB_PRESENT             0U
+    #warning "__MTB_PRESENT not defined in device header file; using default!"
+  #endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MBL */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+        uint32_t RESERVED0[6U];
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Sizes Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Sizes Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
+        uint32_t RESERVED3[809U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  Software Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  Software Lock Status Register */
+        uint32_t RESERVED4[4U];
+  __IM  uint32_t TYPE;                   /*!< Offset: 0xFC8 (R/ )  Device Identifier Register */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos              0U                                         /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk             (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)    /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos                0U                                         /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk               (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)        /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos                     1U                                         /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk                    (0x1UL << TPI_LSR_nTT_Pos)                  /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos                     1U                                         /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk                    (0x1UL << TPI_LSR_SLK_Pos)                  /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos                     0U                                         /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk                    (0x1UL /*<< TPI_LSR_SLI_Pos*/)              /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+        uint32_t RESERVED0[7U];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
+#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
+#else
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
+#endif
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/core_armv8mml.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/core_armv8mml.h
new file mode 100644
index 00000000..2d0f1067
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/core_armv8mml.h
@@ -0,0 +1,2927 @@
+/**************************************************************************//**
+ * @file     core_armv8mml.h
+ * @brief    CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File
+ * @version  V5.0.7
+ * @date     06. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MML_H_GENERIC
+#define __CORE_ARMV8MML_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_ARMv8MML
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS Armv8MML definitions */
+#define __ARMv8MML_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __ARMv8MML_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __ARMv8MML_CMSIS_VERSION       ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
+                                         __ARMv8MML_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                     (81U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MML_H_DEPENDANT
+#define __CORE_ARMV8MML_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __ARMv8MML_REV
+    #define __ARMv8MML_REV               0x0000U
+    #warning "__ARMv8MML_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DSP_PRESENT
+    #define __DSP_PRESENT             0U
+    #warning "__DSP_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MML */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */
+    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */
+    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED6[580U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
+        uint32_t RESERVED3[92U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+        uint32_t RESERVED7[6U];
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
+        uint32_t RESERVED6[4U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+        uint32_t RESERVED32[934U];
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+        uint32_t RESERVED33[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Sizes Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Sizes Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
+        uint32_t RESERVED3[809U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  Software Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  Software Lock Status Register */
+        uint32_t RESERVED4[4U];
+  __IM  uint32_t TYPE;                   /*!< Offset: 0xFC8 (R/ )  Device Identifier Register */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos              0U                                         /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk             (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)    /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos                0U                                         /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk               (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)        /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos                     1U                                         /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk                    (0x1UL << TPI_LSR_nTT_Pos)                  /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos                     1U                                         /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk                    (0x1UL << TPI_LSR_SLK_Pos)                  /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos                     0U                                         /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk                    (0x1UL /*<< TPI_LSR_SLI_Pos*/)              /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
+  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
+  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
+  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
+        uint32_t RESERVED0[1];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#else
+        uint32_t RESERVED0[3];
+#endif
+  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
+  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
+  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
+  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
+#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
+#else
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
+#endif
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Priority Grouping (non-secure)
+  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB_NS->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB_NS->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping (non-secure)
+  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/core_cm0.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/core_cm0.h
new file mode 100644
index 00000000..6f82227c
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/core_cm0.h
@@ -0,0 +1,949 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V5.0.5
+ * @date     28. May 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M0
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM0_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (0U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000U
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+        uint32_t RESERVED0;
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           Address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/core_cm0plus.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/core_cm0plus.h
new file mode 100644
index 00000000..b9377e8c
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/core_cm0plus.h
@@ -0,0 +1,1083 @@
+/**************************************************************************//**
+ * @file     core_cm0plus.h
+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version  V5.0.6
+ * @date     28. May 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex-M0+
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM0+ definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB  (__CM_CMSIS_VERSION_SUB)                   /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
+                                       __CM0PLUS_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                   (0U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0PLUS_REV
+    #define __CM0PLUS_REV             0x0000U
+    #warning "__CM0PLUS_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 8U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0+ header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0+ */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+    uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/core_cm1.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/core_cm1.h
new file mode 100644
index 00000000..fd1c4077
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/core_cm1.h
@@ -0,0 +1,976 @@
+/**************************************************************************//**
+ * @file     core_cm1.h
+ * @brief    CMSIS Cortex-M1 Core Peripheral Access Layer Header File
+ * @version  V1.0.0
+ * @date     23. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM1_H_GENERIC
+#define __CORE_CM1_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M1
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM1 definitions */
+#define __CM1_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM1_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM1_CMSIS_VERSION       ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM1_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (1U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM1_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM1_H_DEPENDANT
+#define __CORE_CM1_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM1_REV
+    #define __CM1_REV               0x0100U
+    #warning "__CM1_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M1 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+        uint32_t RESERVED0;
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_ITCMUAEN_Pos            4U                                        /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMUAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos)         /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
+
+#define SCnSCB_ACTLR_ITCMLAEN_Pos            3U                                        /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMLAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos)         /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M1 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M1 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           Address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM1_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/core_cm23.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/core_cm23.h
new file mode 100644
index 00000000..8202a8dd
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/core_cm23.h
@@ -0,0 +1,1993 @@
+/**************************************************************************//**
+ * @file     core_cm23.h
+ * @brief    CMSIS Cortex-M23 Core Peripheral Access Layer Header File
+ * @version  V5.0.7
+ * @date     22. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM23_H_GENERIC
+#define __CORE_CM23_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M23
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS definitions */
+#define __CM23_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM23_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM23_CMSIS_VERSION       ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
+                                     __CM23_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                 (23U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM23_H_DEPENDANT
+#define __CORE_CM23_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM23_REV
+    #define __CM23_REV                0x0000U
+    #warning "__CM23_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ETM_PRESENT
+    #define __ETM_PRESENT             0U
+    #warning "__ETM_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MTB_PRESENT
+    #define __MTB_PRESENT             0U
+    #warning "__MTB_PRESENT not defined in device header file; using default!"
+  #endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M23 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+        uint32_t RESERVED0[6U];
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t ITFTTD0;                /*!< Offset: 0xEEC (R/ )  Integration Test FIFO Test Data 0 Register */
+  __IOM uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/W)  Integration Test ATB Control Register 2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  Integration Test ATB Control Register 0 */
+  __IM  uint32_t ITFTTD1;                /*!< Offset: 0xEFC (R/ )  Integration Test FIFO Test Data 1 Register */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  Device Configuration Register */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos      16U                                         /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos       8U                                         /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos       0U                                          /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk      (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)      /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)      /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos      16U                                         /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos       8U                                         /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos       0U                                          /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk      (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)      /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)      /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+        uint32_t RESERVED0[7U];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M23 */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M23 */
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */ 
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
+#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
+#else 
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
+#endif
+
+	
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/core_cm3.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/core_cm3.h
new file mode 100644
index 00000000..b0dfbd3d
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/core_cm3.h
@@ -0,0 +1,1941 @@
+/**************************************************************************//**
+ * @file     core_cm3.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version  V5.0.8
+ * @date     04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M3
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM3_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (3U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM3_REV
+    #define __CM3_REV               0x0200U
+    #warning "__CM3_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if defined (__CM3_REV) && (__CM3_REV < 0x0201U)                   /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+#else
+        uint32_t RESERVED1[1U];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) );               /* Insert write key and priority group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/core_cm33.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/core_cm33.h
new file mode 100644
index 00000000..02f82e29
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/core_cm33.h
@@ -0,0 +1,3002 @@
+/**************************************************************************//**
+ * @file     core_cm33.h
+ * @brief    CMSIS Cortex-M33 Core Peripheral Access Layer Header File
+ * @version  V5.0.9
+ * @date     06. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM33_H_GENERIC
+#define __CORE_CM33_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M33
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS CM33 definitions */
+#define __CM33_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM33_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM33_CMSIS_VERSION       ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
+                                     __CM33_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                 (33U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined (__TARGET_FPU_VFP)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined (__ARM_PCS_VFP)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined (__ARMVFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined (__TI_VFP_SUPPORT__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined (__FPU_VFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM33_H_DEPENDANT
+#define __CORE_CM33_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM33_REV
+    #define __CM33_REV                0x0000U
+    #warning "__CM33_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DSP_PRESENT
+    #define __DSP_PRESENT             0U
+    #warning "__DSP_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M33 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */
+    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */
+    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED6[580U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
+        uint32_t RESERVED3[92U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+        uint32_t RESERVED7[6U];
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
+        uint32_t RESERVED6[4U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+        uint32_t RESERVED32[934U];
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+        uint32_t RESERVED33[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t ITFTTD0;                /*!< Offset: 0xEEC (R/ )  Integration Test FIFO Test Data 0 Register */
+  __IOM uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/W)  Integration Test ATB Control Register 2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  Integration Test ATB Control Register 0 */
+  __IM  uint32_t ITFTTD1;                /*!< Offset: 0xEFC (R/ )  Integration Test FIFO Test Data 1 Register */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  Device Configuration Register */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos      16U                                         /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos       8U                                         /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos       0U                                          /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk      (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)      /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)      /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos      16U                                         /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos       8U                                         /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos       0U                                          /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk      (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)      /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)      /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
+  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
+  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
+  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
+        uint32_t RESERVED0[1];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#else
+        uint32_t RESERVED0[3];
+#endif
+  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
+  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
+  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
+  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */ 
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
+#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
+#else 
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
+#endif
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priority group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Priority Grouping (non-secure)
+  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB_NS->AIRCR;                                                /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
+  SCB_NS->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping (non-secure)
+  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/core_cm4.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/core_cm4.h
new file mode 100644
index 00000000..308b8681
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/core_cm4.h
@@ -0,0 +1,2129 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V5.0.8
+ * @date     04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M4
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM4_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (4U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000U
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
+#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+#define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after return, restore floating-point state  */
+#define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after return, restore floating-point state  */
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/core_cm7.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/core_cm7.h
new file mode 100644
index 00000000..ada6c2a5
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/core_cm7.h
@@ -0,0 +1,2671 @@
+/**************************************************************************//**
+ * @file     core_cm7.h
+ * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File
+ * @version  V5.0.8
+ * @date     04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM7_H_GENERIC
+#define __CORE_CM7_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M7
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM7 definitions */
+#define __CM7_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM7_CMSIS_VERSION_SUB   ( __CM_CMSIS_VERSION_SUB)                  /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM7_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (7U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM7_H_DEPENDANT
+#define __CORE_CM7_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM7_REV
+    #define __CM7_REV               0x0000U
+    #warning "__CM7_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ICACHE_PRESENT
+    #define __ICACHE_PRESENT          0U
+    #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DCACHE_PRESENT
+    #define __DCACHE_PRESENT          0U
+    #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DTCM_PRESENT
+    #define __DTCM_PRESENT            0U
+    #warning "__DTCM_PRESENT        not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M7 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MFR[4U];             /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[5U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+        uint32_t RESERVED3[93U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+        uint32_t RESERVED7[6U];
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                      18U                                           /*!< SCB CCR: Branch prediction enable bit Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: Branch prediction enable bit Mask */
+
+#define SCB_CCR_IC_Pos                      17U                                           /*!< SCB CCR: Instruction cache enable bit Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: Instruction cache enable bit Mask */
+
+#define SCB_CCR_DC_Pos                      16U                                           /*!< SCB CCR: Cache enable bit Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: Cache enable bit Mask */
+
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12U                                         /*!< ACTLR: DISITMATBFLUSH Position */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define SCnSCB_ACTLR_DISRAMODE_Pos         11U                                         /*!< ACTLR: DISRAMODE Position */
+#define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: DISRAMODE Mask */
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos         10U                                         /*!< ACTLR: FPEXCODIS Position */
+#define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: FPEXCODIS Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED3[981U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 (  W)  Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
+#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+#define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after return, restore floating-point state  */
+#define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after return, restore floating-point state  */
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)IRQn)]                = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]                >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = SCB->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################  Cache functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_CacheFunctions Cache Functions
+  \brief    Functions that configure Instruction and Data cache.
+  @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )
+
+
+/**
+  \brief   Enable I-Cache
+  \details Turns on I-Cache
+  */
+__STATIC_INLINE void SCB_EnableICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+    __DSB();
+    __ISB();
+    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Disable I-Cache
+  \details Turns off I-Cache
+  */
+__STATIC_INLINE void SCB_DisableICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  /* disable I-Cache */
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Invalidate I-Cache
+  \details Invalidates I-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Enable D-Cache
+  \details Turns on D-Cache
+  */
+__STATIC_INLINE void SCB_EnableDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+    __DSB();
+
+    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Disable D-Cache
+  \details Turns off D-Cache
+  */
+__STATIC_INLINE void SCB_DisableDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  /* disable D-Cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean & invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Invalidate D-Cache
+  \details Invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Clean D-Cache
+  \details Cleans D-Cache
+  */
+__STATIC_INLINE void SCB_CleanDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+     SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+   __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
+                      ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Clean & Invalidate D-Cache
+  \details Cleans and Invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean & invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Invalidate by address
+  \details Invalidates D-Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+     int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t)addr;
+     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCIMVAC = op_addr;
+      op_addr += (uint32_t)linesize;
+      op_size -=           linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Clean by address
+  \details Cleans D-Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+     int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t) addr;
+     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCCMVAC = op_addr;
+      op_addr += (uint32_t)linesize;
+      op_size -=           linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Clean and Invalidate by address
+  \details Cleans and invalidates D_Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+     int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t) addr;
+     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCCIMVAC = op_addr;
+      op_addr += (uint32_t)linesize;
+      op_size -=           linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/core_sc000.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/core_sc000.h
new file mode 100644
index 00000000..9086c642
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/core_sc000.h
@@ -0,0 +1,1022 @@
+/**************************************************************************//**
+ * @file     core_sc000.h
+ * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version  V5.0.5
+ * @date     28. May 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup SC000
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                 /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
+                                      __SC000_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_SC                 (000U)                                   /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC000_REV
+    #define __SC000_REV             0x0000U
+    #warning "__SC000_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+        uint32_t RESERVED1[154U];
+  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the SC000 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for SC000 */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for SC000 */
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for SC000 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/core_sc300.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/core_sc300.h
new file mode 100644
index 00000000..665822da
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/core_sc300.h
@@ -0,0 +1,1915 @@
+/**************************************************************************//**
+ * @file     core_sc300.h
+ * @brief    CMSIS SC300 Core Peripheral Access Layer Header File
+ * @version  V5.0.6
+ * @date     04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup SC3000
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                 /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
+                                      __SC300_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_SC                 (300U)                                   /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC300_H_DEPENDANT
+#define __CORE_SC300_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC300_REV
+    #define __SC300_REV               0x0000U
+    #warning "__SC300_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+        uint32_t RESERVED1[129U];
+  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+        uint32_t RESERVED1[1U];
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/mpu_armv7.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/mpu_armv7.h
new file mode 100644
index 00000000..7d4b600c
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/mpu_armv7.h
@@ -0,0 +1,270 @@
+/******************************************************************************
+ * @file     mpu_armv7.h
+ * @brief    CMSIS MPU API for Armv7-M MPU
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+ 
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
+#define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
+#define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
+#define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
+#define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
+#define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
+#define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
+#define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
+#define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
+#define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
+#define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
+#define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
+#define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
+#define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
+#define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
+#define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
+#define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
+#define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
+#define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
+#define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
+#define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
+#define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
+#define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
+#define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
+#define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
+#define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
+#define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
+#define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
+
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
+#define ARM_MPU_AP_URO  2U ///!< MPU Access Permission unprivileged access read-only
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
+#define ARM_MPU_AP_PRO  5U ///!< MPU Access Permission privileged access read-only
+#define ARM_MPU_AP_RO   6U ///!< MPU Access Permission read-only access
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+  (((BaseAddress) & MPU_RBAR_ADDR_Msk) |  \
+   ((Region) & MPU_RBAR_REGION_Msk)    |  \
+   (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Memory Access Attributes
+* 
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+*/  
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)   \
+  ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk)                 | \
+   (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk)                      | \
+   (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk)                      | \
+   (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param AccessAttributes  Memory access attribution, see \ref ARM_MPU_ACCESS_.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)      \
+  ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk)                                          | \
+   (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)                                      | \
+   (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
+  
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/                         
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+  ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
+
+/**
+* MPU Memory Access Attribute for strongly ordered memory.
+*  - TEX: 000b
+*  - Shareable
+*  - Non-cacheable
+*  - Non-bufferable
+*/ 
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
+
+/**
+* MPU Memory Access Attribute for device memory.
+*  - TEX: 000b (if non-shareable) or 010b (if shareable)
+*  - Shareable or non-shareable
+*  - Non-cacheable
+*  - Bufferable (if shareable) or non-bufferable (if non-shareable)
+*
+* \param IsShareable Configures the device memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
+
+/**
+* MPU Memory Access Attribute for normal memory.
+*  - TEX: 1BBb (reflecting outer cacheability rules)
+*  - Shareable or non-shareable
+*  - Cacheable or non-cacheable (reflecting inner cacheability rules)
+*  - Bufferable or non-bufferable (reflecting inner cacheability rules)
+*
+* \param OuterCp Configures the outer cache policy.
+* \param InnerCp Configures the inner cache policy.
+* \param IsShareable Configures the memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
+
+/**
+* MPU Memory Access Attribute non-cacheable policy.
+*/
+#define ARM_MPU_CACHEP_NOCACHE 0U
+
+/**
+* MPU Memory Access Attribute write-back, write and read allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_WRA 1U
+
+/**
+* MPU Memory Access Attribute write-through, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WT_NWA 2U
+
+/**
+* MPU Memory Access Attribute write-back, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_NWA 3U
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR; //!< The region base address register value (RBAR)
+  uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  MPU->RNR = rnr;
+  MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+  MPU->RNR = rnr;
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  while (cnt > MPU_TYPE_RALIASES) {
+    orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+    table += MPU_TYPE_RALIASES;
+    cnt -= MPU_TYPE_RALIASES;
+  }
+  orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/mpu_armv8.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/mpu_armv8.h
new file mode 100644
index 00000000..99ee9f99
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/mpu_armv8.h
@@ -0,0 +1,333 @@
+/******************************************************************************
+ * @file     mpu_armv8.h
+ * @brief    CMSIS MPU API for Armv8-M MPU
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV8_H
+#define ARM_MPU_ARMV8_H
+
+/** \brief Attribute for device memory (outer only) */
+#define ARM_MPU_ATTR_DEVICE                           ( 0U )
+
+/** \brief Attribute for non-cacheable, normal memory */
+#define ARM_MPU_ATTR_NON_CACHEABLE                    ( 4U )
+
+/** \brief Attribute for normal memory (outer and inner)
+* \param NT Non-Transient: Set to 1 for non-transient data.
+* \param WB Write-Back: Set to 1 to use write-back update policy.
+* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
+* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
+*/
+#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
+  (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
+
+/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
+
+/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRE  (1U)
+
+/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGRE   (2U)
+
+/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_GRE    (3U)
+
+/** \brief Memory Attribute
+* \param O Outer memory attributes
+* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
+*/
+#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
+
+/** \brief Normal memory non-shareable  */
+#define ARM_MPU_SH_NON   (0U)
+
+/** \brief Normal memory outer shareable  */
+#define ARM_MPU_SH_OUTER (2U)
+
+/** \brief Normal memory inner shareable  */
+#define ARM_MPU_SH_INNER (3U)
+
+/** \brief Memory access permissions
+* \param RO Read-Only: Set to 1 for read-only memory.
+* \param NP Non-Privileged: Set to 1 for non-privileged memory.
+*/
+#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
+
+/** \brief Region Base Address Register value
+* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
+* \param SH Defines the Shareability domain for this memory region.
+* \param RO Read-Only: Set to 1 for a read-only memory region.
+* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
+* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
+*/
+#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
+  ((BASE & MPU_RBAR_BASE_Msk) | \
+  ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
+  ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
+  ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
+
+/** \brief Region Limit Address Register value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR(LIMIT, IDX) \
+  ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
+  ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+  (MPU_RLAR_EN_Msk))
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR;                   /*!< Region Base Address Register value */
+  uint32_t RLAR;                   /*!< Region Limit Address Register value */
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+#ifdef MPU_NS
+/** Enable the Non-secure MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the Non-secure MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable_NS(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU_NS->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+#endif
+
+/** Set the memory attribute encoding to the given MPU.
+* \param mpu Pointer to the MPU to be configured.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
+{
+  const uint8_t reg = idx / 4U;
+  const uint32_t pos = ((idx % 4U) * 8U);
+  const uint32_t mask = 0xFFU << pos;
+  
+  if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
+    return; // invalid index
+  }
+  
+  mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
+}
+
+/** Set the memory attribute encoding.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU, idx, attr);
+}
+
+#ifdef MPU_NS
+/** Set the memory attribute encoding to the Non-secure MPU.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
+}
+#endif
+
+/** Clear and disable the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
+{
+  mpu->RNR = rnr;
+  mpu->RLAR = 0U;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  ARM_MPU_ClrRegionEx(MPU, rnr);
+}
+
+#ifdef MPU_NS
+/** Clear and disable the given Non-secure MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
+{  
+  ARM_MPU_ClrRegionEx(MPU_NS, rnr);
+}
+#endif
+
+/** Configure the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  mpu->RNR = rnr;
+  mpu->RBAR = rbar;
+  mpu->RLAR = rlar;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
+}
+
+#ifdef MPU_NS
+/** Configure the given Non-secure MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);  
+}
+#endif
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table to the given MPU.
+* \param mpu Pointer to the MPU registers to be used.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  if (cnt == 1U) {
+    mpu->RNR = rnr;
+    orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
+  } else {
+    uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);
+    uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
+    
+    mpu->RNR = rnrBase;
+    while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
+      uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
+      orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
+      table += c;
+      cnt -= c;
+      rnrOffset = 0U;
+      rnrBase += MPU_TYPE_RALIASES;
+      mpu->RNR = rnrBase;
+    }
+    
+    orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU, rnr, table, cnt);
+}
+
+#ifdef MPU_NS
+/** Load the given number of MPU regions from a table to the Non-secure MPU.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
+}
+#endif
+
+#endif
+
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/tz_context.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/tz_context.h
new file mode 100644
index 00000000..d4c1474f
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/CMSIS/Include/tz_context.h
@@ -0,0 +1,70 @@
+/******************************************************************************
+ * @file     tz_context.h
+ * @brief    Context Management for Armv8-M TrustZone
+ * @version  V1.0.1
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef TZ_CONTEXT_H
+#define TZ_CONTEXT_H
+ 
+#include <stdint.h>
+ 
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+ 
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+  
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+ 
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in]  module   identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0    no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+ 
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+ 
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+ 
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+ 
+#endif  // TZ_CONTEXT_H
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
new file mode 100644
index 00000000..7b859e37
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
@@ -0,0 +1,3775 @@
+/**
+  ******************************************************************************
+  * @file    stm32_hal_legacy.h
+  * @author  MCD Application Team
+  * @brief   This file contains aliases definition for the STM32Cube HAL constants
+  *          macros and functions maintained for legacy purpose.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32_HAL_LEGACY
+#define STM32_HAL_LEGACY
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define AES_FLAG_RDERR                  CRYP_FLAG_RDERR
+#define AES_FLAG_WRERR                  CRYP_FLAG_WRERR
+#define AES_CLEARFLAG_CCF               CRYP_CLEARFLAG_CCF
+#define AES_CLEARFLAG_RDERR             CRYP_CLEARFLAG_RDERR
+#define AES_CLEARFLAG_WRERR             CRYP_CLEARFLAG_WRERR
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define ADC_RESOLUTION12b               ADC_RESOLUTION_12B
+#define ADC_RESOLUTION10b               ADC_RESOLUTION_10B
+#define ADC_RESOLUTION8b                ADC_RESOLUTION_8B
+#define ADC_RESOLUTION6b                ADC_RESOLUTION_6B
+#define OVR_DATA_OVERWRITTEN            ADC_OVR_DATA_OVERWRITTEN
+#define OVR_DATA_PRESERVED              ADC_OVR_DATA_PRESERVED
+#define EOC_SINGLE_CONV                 ADC_EOC_SINGLE_CONV
+#define EOC_SEQ_CONV                    ADC_EOC_SEQ_CONV
+#define EOC_SINGLE_SEQ_CONV             ADC_EOC_SINGLE_SEQ_CONV
+#define REGULAR_GROUP                   ADC_REGULAR_GROUP
+#define INJECTED_GROUP                  ADC_INJECTED_GROUP
+#define REGULAR_INJECTED_GROUP          ADC_REGULAR_INJECTED_GROUP
+#define AWD_EVENT                       ADC_AWD_EVENT
+#define AWD1_EVENT                      ADC_AWD1_EVENT
+#define AWD2_EVENT                      ADC_AWD2_EVENT
+#define AWD3_EVENT                      ADC_AWD3_EVENT
+#define OVR_EVENT                       ADC_OVR_EVENT
+#define JQOVF_EVENT                     ADC_JQOVF_EVENT
+#define ALL_CHANNELS                    ADC_ALL_CHANNELS
+#define REGULAR_CHANNELS                ADC_REGULAR_CHANNELS
+#define INJECTED_CHANNELS               ADC_INJECTED_CHANNELS
+#define SYSCFG_FLAG_SENSOR_ADC          ADC_FLAG_SENSOR
+#define SYSCFG_FLAG_VREF_ADC            ADC_FLAG_VREFINT
+#define ADC_CLOCKPRESCALER_PCLK_DIV1    ADC_CLOCK_SYNC_PCLK_DIV1
+#define ADC_CLOCKPRESCALER_PCLK_DIV2    ADC_CLOCK_SYNC_PCLK_DIV2
+#define ADC_CLOCKPRESCALER_PCLK_DIV4    ADC_CLOCK_SYNC_PCLK_DIV4
+#define ADC_CLOCKPRESCALER_PCLK_DIV6    ADC_CLOCK_SYNC_PCLK_DIV6
+#define ADC_CLOCKPRESCALER_PCLK_DIV8    ADC_CLOCK_SYNC_PCLK_DIV8
+#define ADC_EXTERNALTRIG0_T6_TRGO       ADC_EXTERNALTRIGCONV_T6_TRGO
+#define ADC_EXTERNALTRIG1_T21_CC2       ADC_EXTERNALTRIGCONV_T21_CC2
+#define ADC_EXTERNALTRIG2_T2_TRGO       ADC_EXTERNALTRIGCONV_T2_TRGO
+#define ADC_EXTERNALTRIG3_T2_CC4        ADC_EXTERNALTRIGCONV_T2_CC4
+#define ADC_EXTERNALTRIG4_T22_TRGO      ADC_EXTERNALTRIGCONV_T22_TRGO
+#define ADC_EXTERNALTRIG7_EXT_IT11      ADC_EXTERNALTRIGCONV_EXT_IT11
+#define ADC_CLOCK_ASYNC                 ADC_CLOCK_ASYNC_DIV1
+#define ADC_EXTERNALTRIG_EDGE_NONE      ADC_EXTERNALTRIGCONVEDGE_NONE
+#define ADC_EXTERNALTRIG_EDGE_RISING    ADC_EXTERNALTRIGCONVEDGE_RISING
+#define ADC_EXTERNALTRIG_EDGE_FALLING   ADC_EXTERNALTRIGCONVEDGE_FALLING
+#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
+#define ADC_SAMPLETIME_2CYCLE_5         ADC_SAMPLETIME_2CYCLES_5
+
+#define HAL_ADC_STATE_BUSY_REG          HAL_ADC_STATE_REG_BUSY
+#define HAL_ADC_STATE_BUSY_INJ          HAL_ADC_STATE_INJ_BUSY
+#define HAL_ADC_STATE_EOC_REG           HAL_ADC_STATE_REG_EOC
+#define HAL_ADC_STATE_EOC_INJ           HAL_ADC_STATE_INJ_EOC
+#define HAL_ADC_STATE_ERROR             HAL_ADC_STATE_ERROR_INTERNAL
+#define HAL_ADC_STATE_BUSY              HAL_ADC_STATE_BUSY_INTERNAL
+#define HAL_ADC_STATE_AWD               HAL_ADC_STATE_AWD1
+
+#if defined(STM32H7)
+#define ADC_CHANNEL_VBAT_DIV4           ADC_CHANNEL_VBAT
+#endif /* STM32H7 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define COMP_WINDOWMODE_DISABLED       COMP_WINDOWMODE_DISABLE
+#define COMP_WINDOWMODE_ENABLED        COMP_WINDOWMODE_ENABLE
+#define COMP_EXTI_LINE_COMP1_EVENT     COMP_EXTI_LINE_COMP1
+#define COMP_EXTI_LINE_COMP2_EVENT     COMP_EXTI_LINE_COMP2
+#define COMP_EXTI_LINE_COMP3_EVENT     COMP_EXTI_LINE_COMP3
+#define COMP_EXTI_LINE_COMP4_EVENT     COMP_EXTI_LINE_COMP4
+#define COMP_EXTI_LINE_COMP5_EVENT     COMP_EXTI_LINE_COMP5
+#define COMP_EXTI_LINE_COMP6_EVENT     COMP_EXTI_LINE_COMP6
+#define COMP_EXTI_LINE_COMP7_EVENT     COMP_EXTI_LINE_COMP7
+#if defined(STM32L0)
+#define COMP_LPTIMCONNECTION_ENABLED   ((uint32_t)0x00000003U)    /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
+#endif
+#define COMP_OUTPUT_COMP6TIM2OCREFCLR  COMP_OUTPUT_COMP6_TIM2OCREFCLR
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define COMP_OUTPUT_TIM3IC1            COMP_OUTPUT_COMP1_TIM3IC1
+#define COMP_OUTPUT_TIM3OCREFCLR       COMP_OUTPUT_COMP1_TIM3OCREFCLR
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32L0) || defined(STM32L4)
+#define COMP_WINDOWMODE_ENABLE         COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
+
+#define COMP_NONINVERTINGINPUT_IO1      COMP_INPUT_PLUS_IO1
+#define COMP_NONINVERTINGINPUT_IO2      COMP_INPUT_PLUS_IO2
+#define COMP_NONINVERTINGINPUT_IO3      COMP_INPUT_PLUS_IO3
+#define COMP_NONINVERTINGINPUT_IO4      COMP_INPUT_PLUS_IO4
+#define COMP_NONINVERTINGINPUT_IO5      COMP_INPUT_PLUS_IO5
+#define COMP_NONINVERTINGINPUT_IO6      COMP_INPUT_PLUS_IO6
+
+#define COMP_INVERTINGINPUT_1_4VREFINT  COMP_INPUT_MINUS_1_4VREFINT
+#define COMP_INVERTINGINPUT_1_2VREFINT  COMP_INPUT_MINUS_1_2VREFINT
+#define COMP_INVERTINGINPUT_3_4VREFINT  COMP_INPUT_MINUS_3_4VREFINT
+#define COMP_INVERTINGINPUT_VREFINT     COMP_INPUT_MINUS_VREFINT
+#define COMP_INVERTINGINPUT_DAC1_CH1    COMP_INPUT_MINUS_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC1_CH2    COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_DAC1        COMP_INPUT_MINUS_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC2        COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_IO1         COMP_INPUT_MINUS_IO1
+#if defined(STM32L0)
+/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2),     */
+/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding   */
+/* to the second dedicated IO (only for COMP2).                               */
+#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO2
+#else
+#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_IO2
+#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO3
+#endif
+#define COMP_INVERTINGINPUT_IO4         COMP_INPUT_MINUS_IO4
+#define COMP_INVERTINGINPUT_IO5         COMP_INPUT_MINUS_IO5
+
+#define COMP_OUTPUTLEVEL_LOW            COMP_OUTPUT_LEVEL_LOW
+#define COMP_OUTPUTLEVEL_HIGH           COMP_OUTPUT_LEVEL_HIGH
+
+/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose.                    */
+/*       To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()".        */
+#if defined(COMP_CSR_LOCK)
+#define COMP_FLAG_LOCK                 COMP_CSR_LOCK
+#elif defined(COMP_CSR_COMP1LOCK)
+#define COMP_FLAG_LOCK                 COMP_CSR_COMP1LOCK
+#elif defined(COMP_CSR_COMPxLOCK)
+#define COMP_FLAG_LOCK                 COMP_CSR_COMPxLOCK
+#endif
+
+#if defined(STM32L4)
+#define COMP_BLANKINGSRCE_TIM1OC5        COMP_BLANKINGSRC_TIM1_OC5_COMP1
+#define COMP_BLANKINGSRCE_TIM2OC3        COMP_BLANKINGSRC_TIM2_OC3_COMP1
+#define COMP_BLANKINGSRCE_TIM3OC3        COMP_BLANKINGSRC_TIM3_OC3_COMP1
+#define COMP_BLANKINGSRCE_TIM3OC4        COMP_BLANKINGSRC_TIM3_OC4_COMP2
+#define COMP_BLANKINGSRCE_TIM8OC5        COMP_BLANKINGSRC_TIM8_OC5_COMP2
+#define COMP_BLANKINGSRCE_TIM15OC1       COMP_BLANKINGSRC_TIM15_OC1_COMP2
+#define COMP_BLANKINGSRCE_NONE           COMP_BLANKINGSRC_NONE
+#endif
+
+#if defined(STM32L0)
+#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_MEDIUMSPEED
+#define COMP_MODE_LOWSPEED               COMP_POWERMODE_ULTRALOWPOWER
+#else
+#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_HIGHSPEED
+#define COMP_MODE_MEDIUMSPEED            COMP_POWERMODE_MEDIUMSPEED
+#define COMP_MODE_LOWPOWER               COMP_POWERMODE_LOWPOWER
+#define COMP_MODE_ULTRALOWPOWER          COMP_POWERMODE_ULTRALOWPOWER
+#endif
+
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
+/**
+  * @}
+  */
+
+/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define CRC_OUTPUTDATA_INVERSION_DISABLED    CRC_OUTPUTDATA_INVERSION_DISABLE
+#define CRC_OUTPUTDATA_INVERSION_ENABLED     CRC_OUTPUTDATA_INVERSION_ENABLE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define DAC1_CHANNEL_1                                  DAC_CHANNEL_1
+#define DAC1_CHANNEL_2                                  DAC_CHANNEL_2
+#define DAC2_CHANNEL_1                                  DAC_CHANNEL_1
+#define DAC_WAVE_NONE                                   0x00000000U
+#define DAC_WAVE_NOISE                                  DAC_CR_WAVE1_0
+#define DAC_WAVE_TRIANGLE                               DAC_CR_WAVE1_1
+#define DAC_WAVEGENERATION_NONE                         DAC_WAVE_NONE
+#define DAC_WAVEGENERATION_NOISE                        DAC_WAVE_NOISE
+#define DAC_WAVEGENERATION_TRIANGLE                     DAC_WAVE_TRIANGLE
+
+#if defined(STM32G4) || defined(STM32H7)
+#define DAC_CHIPCONNECT_DISABLE       DAC_CHIPCONNECT_EXTERNAL
+#define DAC_CHIPCONNECT_ENABLE        DAC_CHIPCONNECT_INTERNAL
+#endif
+
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
+#define HAL_DAC_MSP_INIT_CB_ID       HAL_DAC_MSPINIT_CB_ID
+#define HAL_DAC_MSP_DEINIT_CB_ID     HAL_DAC_MSPDEINIT_CB_ID
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define HAL_REMAPDMA_ADC_DMA_CH2                DMA_REMAP_ADC_DMA_CH2
+#define HAL_REMAPDMA_USART1_TX_DMA_CH4          DMA_REMAP_USART1_TX_DMA_CH4
+#define HAL_REMAPDMA_USART1_RX_DMA_CH5          DMA_REMAP_USART1_RX_DMA_CH5
+#define HAL_REMAPDMA_TIM16_DMA_CH4              DMA_REMAP_TIM16_DMA_CH4
+#define HAL_REMAPDMA_TIM17_DMA_CH2              DMA_REMAP_TIM17_DMA_CH2
+#define HAL_REMAPDMA_USART3_DMA_CH32            DMA_REMAP_USART3_DMA_CH32
+#define HAL_REMAPDMA_TIM16_DMA_CH6              DMA_REMAP_TIM16_DMA_CH6
+#define HAL_REMAPDMA_TIM17_DMA_CH7              DMA_REMAP_TIM17_DMA_CH7
+#define HAL_REMAPDMA_SPI2_DMA_CH67              DMA_REMAP_SPI2_DMA_CH67
+#define HAL_REMAPDMA_USART2_DMA_CH67            DMA_REMAP_USART2_DMA_CH67
+#define HAL_REMAPDMA_I2C1_DMA_CH76              DMA_REMAP_I2C1_DMA_CH76
+#define HAL_REMAPDMA_TIM1_DMA_CH6               DMA_REMAP_TIM1_DMA_CH6
+#define HAL_REMAPDMA_TIM2_DMA_CH7               DMA_REMAP_TIM2_DMA_CH7
+#define HAL_REMAPDMA_TIM3_DMA_CH6               DMA_REMAP_TIM3_DMA_CH6
+
+#define IS_HAL_REMAPDMA                          IS_DMA_REMAP
+#define __HAL_REMAPDMA_CHANNEL_ENABLE            __HAL_DMA_REMAP_CHANNEL_ENABLE
+#define __HAL_REMAPDMA_CHANNEL_DISABLE           __HAL_DMA_REMAP_CHANNEL_DISABLE
+
+#if defined(STM32L4)
+
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI0            HAL_DMAMUX1_REQ_GEN_EXTI0
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI1            HAL_DMAMUX1_REQ_GEN_EXTI1
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI2            HAL_DMAMUX1_REQ_GEN_EXTI2
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI3            HAL_DMAMUX1_REQ_GEN_EXTI3
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI4            HAL_DMAMUX1_REQ_GEN_EXTI4
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI5            HAL_DMAMUX1_REQ_GEN_EXTI5
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI6            HAL_DMAMUX1_REQ_GEN_EXTI6
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI7            HAL_DMAMUX1_REQ_GEN_EXTI7
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI8            HAL_DMAMUX1_REQ_GEN_EXTI8
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI9            HAL_DMAMUX1_REQ_GEN_EXTI9
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI10           HAL_DMAMUX1_REQ_GEN_EXTI10
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI11           HAL_DMAMUX1_REQ_GEN_EXTI11
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI12           HAL_DMAMUX1_REQ_GEN_EXTI12
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI13           HAL_DMAMUX1_REQ_GEN_EXTI13
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI14           HAL_DMAMUX1_REQ_GEN_EXTI14
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI15           HAL_DMAMUX1_REQ_GEN_EXTI15
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT       HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT       HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE           HAL_DMAMUX1_REQ_GEN_DSI_TE
+#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT          HAL_DMAMUX1_REQ_GEN_DSI_EOT
+#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT        HAL_DMAMUX1_REQ_GEN_DMA2D_EOT
+#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT          HAL_DMAMUX1_REQ_GEN_LTDC_IT
+
+#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT          HAL_DMAMUX_REQ_GEN_NO_EVENT
+#define HAL_DMAMUX_REQUEST_GEN_RISING            HAL_DMAMUX_REQ_GEN_RISING
+#define HAL_DMAMUX_REQUEST_GEN_FALLING           HAL_DMAMUX_REQ_GEN_FALLING
+#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING    HAL_DMAMUX_REQ_GEN_RISING_FALLING
+
+#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+#define DMA_REQUEST_DCMI_PSSI                    DMA_REQUEST_DCMI
+#endif
+
+#endif /* STM32L4 */
+
+#if defined(STM32G0)
+#define DMA_REQUEST_DAC1_CHANNEL1                DMA_REQUEST_DAC1_CH1
+#define DMA_REQUEST_DAC1_CHANNEL2                DMA_REQUEST_DAC1_CH2
+#endif
+
+#if defined(STM32H7)
+
+#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
+#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
+
+#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
+#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
+
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI0              HAL_DMAMUX1_REQ_GEN_EXTI0
+#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO         HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
+
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP          HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP          HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT          HAL_DMAMUX2_REQ_GEN_COMP1_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT          HAL_DMAMUX2_REQ_GEN_COMP2_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP           HAL_DMAMUX2_REQ_GEN_RTC_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_EXTI0              HAL_DMAMUX2_REQ_GEN_EXTI0
+#define HAL_DMAMUX2_REQUEST_GEN_EXTI2              HAL_DMAMUX2_REQ_GEN_EXTI2
+#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT        HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT            HAL_DMAMUX2_REQ_GEN_SPI6_IT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
+#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT            HAL_DMAMUX2_REQ_GEN_ADC3_IT
+#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT      HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
+#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
+
+#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT            HAL_DMAMUX_REQ_GEN_NO_EVENT
+#define HAL_DMAMUX_REQUEST_GEN_RISING              HAL_DMAMUX_REQ_GEN_RISING
+#define HAL_DMAMUX_REQUEST_GEN_FALLING             HAL_DMAMUX_REQ_GEN_FALLING
+#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING      HAL_DMAMUX_REQ_GEN_RISING_FALLING
+
+#define DFSDM_FILTER_EXT_TRIG_LPTIM1               DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT
+#define DFSDM_FILTER_EXT_TRIG_LPTIM2               DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
+#define DFSDM_FILTER_EXT_TRIG_LPTIM3               DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
+
+#define DAC_TRIGGER_LP1_OUT                        DAC_TRIGGER_LPTIM1_OUT
+#define DAC_TRIGGER_LP2_OUT                        DAC_TRIGGER_LPTIM2_OUT
+
+#endif /* STM32H7 */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define TYPEPROGRAM_BYTE              FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_HALFWORD          FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_WORD              FLASH_TYPEPROGRAM_WORD
+#define TYPEPROGRAM_DOUBLEWORD        FLASH_TYPEPROGRAM_DOUBLEWORD
+#define TYPEERASE_SECTORS             FLASH_TYPEERASE_SECTORS
+#define TYPEERASE_PAGES               FLASH_TYPEERASE_PAGES
+#define TYPEERASE_PAGEERASE           FLASH_TYPEERASE_PAGES
+#define TYPEERASE_MASSERASE           FLASH_TYPEERASE_MASSERASE
+#define WRPSTATE_DISABLE              OB_WRPSTATE_DISABLE
+#define WRPSTATE_ENABLE               OB_WRPSTATE_ENABLE
+#define HAL_FLASH_TIMEOUT_VALUE       FLASH_TIMEOUT_VALUE
+#define OBEX_PCROP                    OPTIONBYTE_PCROP
+#define OBEX_BOOTCONFIG               OPTIONBYTE_BOOTCONFIG
+#define PCROPSTATE_DISABLE            OB_PCROP_STATE_DISABLE
+#define PCROPSTATE_ENABLE             OB_PCROP_STATE_ENABLE
+#define TYPEERASEDATA_BYTE            FLASH_TYPEERASEDATA_BYTE
+#define TYPEERASEDATA_HALFWORD        FLASH_TYPEERASEDATA_HALFWORD
+#define TYPEERASEDATA_WORD            FLASH_TYPEERASEDATA_WORD
+#define TYPEPROGRAMDATA_BYTE          FLASH_TYPEPROGRAMDATA_BYTE
+#define TYPEPROGRAMDATA_HALFWORD      FLASH_TYPEPROGRAMDATA_HALFWORD
+#define TYPEPROGRAMDATA_WORD          FLASH_TYPEPROGRAMDATA_WORD
+#define TYPEPROGRAMDATA_FASTBYTE      FLASH_TYPEPROGRAMDATA_FASTBYTE
+#define TYPEPROGRAMDATA_FASTHALFWORD  FLASH_TYPEPROGRAMDATA_FASTHALFWORD
+#define TYPEPROGRAMDATA_FASTWORD      FLASH_TYPEPROGRAMDATA_FASTWORD
+#define PAGESIZE                      FLASH_PAGE_SIZE
+#define TYPEPROGRAM_FASTBYTE          FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_FASTHALFWORD      FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_FASTWORD          FLASH_TYPEPROGRAM_WORD
+#define VOLTAGE_RANGE_1               FLASH_VOLTAGE_RANGE_1
+#define VOLTAGE_RANGE_2               FLASH_VOLTAGE_RANGE_2
+#define VOLTAGE_RANGE_3               FLASH_VOLTAGE_RANGE_3
+#define VOLTAGE_RANGE_4               FLASH_VOLTAGE_RANGE_4
+#define TYPEPROGRAM_FAST              FLASH_TYPEPROGRAM_FAST
+#define TYPEPROGRAM_FAST_AND_LAST     FLASH_TYPEPROGRAM_FAST_AND_LAST
+#define WRPAREA_BANK1_AREAA           OB_WRPAREA_BANK1_AREAA
+#define WRPAREA_BANK1_AREAB           OB_WRPAREA_BANK1_AREAB
+#define WRPAREA_BANK2_AREAA           OB_WRPAREA_BANK2_AREAA
+#define WRPAREA_BANK2_AREAB           OB_WRPAREA_BANK2_AREAB
+#define IWDG_STDBY_FREEZE             OB_IWDG_STDBY_FREEZE
+#define IWDG_STDBY_ACTIVE             OB_IWDG_STDBY_RUN
+#define IWDG_STOP_FREEZE              OB_IWDG_STOP_FREEZE
+#define IWDG_STOP_ACTIVE              OB_IWDG_STOP_RUN
+#define FLASH_ERROR_NONE              HAL_FLASH_ERROR_NONE
+#define FLASH_ERROR_RD                HAL_FLASH_ERROR_RD
+#define FLASH_ERROR_PG                HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_PGP               HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_WRP               HAL_FLASH_ERROR_WRP
+#define FLASH_ERROR_OPTV              HAL_FLASH_ERROR_OPTV
+#define FLASH_ERROR_OPTVUSR           HAL_FLASH_ERROR_OPTVUSR
+#define FLASH_ERROR_PROG              HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_OP                HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_PGA               HAL_FLASH_ERROR_PGA
+#define FLASH_ERROR_SIZE              HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_SIZ               HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_PGS               HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_MIS               HAL_FLASH_ERROR_MIS
+#define FLASH_ERROR_FAST              HAL_FLASH_ERROR_FAST
+#define FLASH_ERROR_FWWERR            HAL_FLASH_ERROR_FWWERR
+#define FLASH_ERROR_NOTZERO           HAL_FLASH_ERROR_NOTZERO
+#define FLASH_ERROR_OPERATION         HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_ERS               HAL_FLASH_ERROR_ERS
+#define OB_WDG_SW                     OB_IWDG_SW
+#define OB_WDG_HW                     OB_IWDG_HW
+#define OB_SDADC12_VDD_MONITOR_SET    OB_SDACD_VDD_MONITOR_SET
+#define OB_SDADC12_VDD_MONITOR_RESET  OB_SDACD_VDD_MONITOR_RESET
+#define OB_RAM_PARITY_CHECK_SET       OB_SRAM_PARITY_SET
+#define OB_RAM_PARITY_CHECK_RESET     OB_SRAM_PARITY_RESET
+#define IS_OB_SDADC12_VDD_MONITOR     IS_OB_SDACD_VDD_MONITOR
+#define OB_RDP_LEVEL0                 OB_RDP_LEVEL_0
+#define OB_RDP_LEVEL1                 OB_RDP_LEVEL_1
+#define OB_RDP_LEVEL2                 OB_RDP_LEVEL_2
+#if defined(STM32G0)
+#define OB_BOOT_LOCK_DISABLE          OB_BOOT_ENTRY_FORCED_NONE
+#define OB_BOOT_LOCK_ENABLE           OB_BOOT_ENTRY_FORCED_FLASH
+#else
+#define OB_BOOT_ENTRY_FORCED_NONE     OB_BOOT_LOCK_DISABLE
+#define OB_BOOT_ENTRY_FORCED_FLASH    OB_BOOT_LOCK_ENABLE
+#endif
+#if defined(STM32H7)
+#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1
+#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1
+#define FLASH_FLAG_STRBER_BANK1R  FLASH_FLAG_STRBERR_BANK1
+#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
+#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
+#define FLASH_FLAG_STRBER_BANK2R  FLASH_FLAG_STRBERR_BANK2
+#define FLASH_FLAG_WDW            FLASH_FLAG_WBNE
+#define OB_WRP_SECTOR_All         OB_WRP_SECTOR_ALL
+#endif /* STM32H7 */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#if defined(STM32H7)
+#define __HAL_RCC_JPEG_CLK_ENABLE               __HAL_RCC_JPGDECEN_CLK_ENABLE
+#define __HAL_RCC_JPEG_CLK_DISABLE              __HAL_RCC_JPGDECEN_CLK_DISABLE
+#define __HAL_RCC_JPEG_FORCE_RESET              __HAL_RCC_JPGDECRST_FORCE_RESET
+#define __HAL_RCC_JPEG_RELEASE_RESET            __HAL_RCC_JPGDECRST_RELEASE_RESET
+#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE         __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
+#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE        __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
+#endif /* STM32H7 */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9    I2C_FASTMODEPLUS_PA9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10   I2C_FASTMODEPLUS_PA10
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6    I2C_FASTMODEPLUS_PB6
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7    I2C_FASTMODEPLUS_PB7
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8    I2C_FASTMODEPLUS_PB8
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9    I2C_FASTMODEPLUS_PB9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C1       I2C_FASTMODEPLUS_I2C1
+#define HAL_SYSCFG_FASTMODEPLUS_I2C2       I2C_FASTMODEPLUS_I2C2
+#define HAL_SYSCFG_FASTMODEPLUS_I2C3       I2C_FASTMODEPLUS_I2C3
+#if defined(STM32G4)
+
+#define HAL_SYSCFG_EnableIOAnalogSwitchBooster    HAL_SYSCFG_EnableIOSwitchBooster
+#define HAL_SYSCFG_DisableIOAnalogSwitchBooster   HAL_SYSCFG_DisableIOSwitchBooster
+#define HAL_SYSCFG_EnableIOAnalogSwitchVDD        HAL_SYSCFG_EnableIOSwitchVDD
+#define HAL_SYSCFG_DisableIOAnalogSwitchVDD       HAL_SYSCFG_DisableIOSwitchVDD
+#endif /* STM32G4 */
+/**
+  * @}
+  */
+
+
+/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
+  * @{
+  */
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
+#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE       FMC_NAND_WAIT_FEATURE_DISABLE
+#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE        FMC_NAND_WAIT_FEATURE_ENABLE
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_8            FMC_NAND_MEM_BUS_WIDTH_8
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_16           FMC_NAND_MEM_BUS_WIDTH_16
+#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4)
+#define FMC_NAND_WAIT_FEATURE_DISABLE           FMC_NAND_PCC_WAIT_FEATURE_DISABLE
+#define FMC_NAND_WAIT_FEATURE_ENABLE            FMC_NAND_PCC_WAIT_FEATURE_ENABLE
+#define FMC_NAND_MEM_BUS_WIDTH_8                FMC_NAND_PCC_MEM_BUS_WIDTH_8
+#define FMC_NAND_MEM_BUS_WIDTH_16               FMC_NAND_PCC_MEM_BUS_WIDTH_16
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define FSMC_NORSRAM_TYPEDEF                      FSMC_NORSRAM_TypeDef
+#define FSMC_NORSRAM_EXTENDED_TYPEDEF             FSMC_NORSRAM_EXTENDED_TypeDef
+/**
+  * @}
+  */
+
+/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define GET_GPIO_SOURCE                           GPIO_GET_INDEX
+#define GET_GPIO_INDEX                            GPIO_GET_INDEX
+
+#if defined(STM32F4)
+#define GPIO_AF12_SDMMC                           GPIO_AF12_SDIO
+#define GPIO_AF12_SDMMC1                          GPIO_AF12_SDIO
+#endif
+
+#if defined(STM32F7)
+#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1
+#endif
+
+#if defined(STM32L4)
+#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1
+#endif
+
+#if defined(STM32H7)
+#define GPIO_AF7_SDIO1                            GPIO_AF7_SDMMC1
+#define GPIO_AF8_SDIO1                            GPIO_AF8_SDMMC1
+#define GPIO_AF12_SDIO1                           GPIO_AF12_SDMMC1
+#define GPIO_AF9_SDIO2                            GPIO_AF9_SDMMC2
+#define GPIO_AF10_SDIO2                           GPIO_AF10_SDMMC2
+#define GPIO_AF11_SDIO2                           GPIO_AF11_SDMMC2
+
+#if defined (STM32H743xx) || defined (STM32H753xx)  || defined (STM32H750xx) || defined (STM32H742xx) || \
+    defined (STM32H745xx) || defined (STM32H755xx)  || defined (STM32H747xx) || defined (STM32H757xx)
+#define GPIO_AF10_OTG2_HS  GPIO_AF10_OTG2_FS
+#define GPIO_AF10_OTG1_FS  GPIO_AF10_OTG1_HS
+#define GPIO_AF12_OTG2_FS  GPIO_AF12_OTG1_FS
+#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
+#endif /* STM32H7 */
+
+#define GPIO_AF0_LPTIM                            GPIO_AF0_LPTIM1
+#define GPIO_AF1_LPTIM                            GPIO_AF1_LPTIM1
+#define GPIO_AF2_LPTIM                            GPIO_AF2_LPTIM1
+
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7)
+#define  GPIO_SPEED_LOW                           GPIO_SPEED_FREQ_LOW
+#define  GPIO_SPEED_MEDIUM                        GPIO_SPEED_FREQ_MEDIUM
+#define  GPIO_SPEED_FAST                          GPIO_SPEED_FREQ_HIGH
+#define  GPIO_SPEED_HIGH                          GPIO_SPEED_FREQ_VERY_HIGH
+#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/
+
+#if defined(STM32L1)
+ #define  GPIO_SPEED_VERY_LOW    GPIO_SPEED_FREQ_LOW
+ #define  GPIO_SPEED_LOW         GPIO_SPEED_FREQ_MEDIUM
+ #define  GPIO_SPEED_MEDIUM      GPIO_SPEED_FREQ_HIGH
+ #define  GPIO_SPEED_HIGH        GPIO_SPEED_FREQ_VERY_HIGH
+#endif /* STM32L1 */
+
+#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
+ #define  GPIO_SPEED_LOW    GPIO_SPEED_FREQ_LOW
+ #define  GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
+ #define  GPIO_SPEED_HIGH   GPIO_SPEED_FREQ_HIGH
+#endif /* STM32F0 || STM32F3 || STM32F1 */
+
+#define GPIO_AF6_DFSDM                            GPIO_AF6_DFSDM1
+/**
+  * @}
+  */
+
+/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define HRTIM_TIMDELAYEDPROTECTION_DISABLED           HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
+
+#define __HAL_HRTIM_SetCounter        __HAL_HRTIM_SETCOUNTER
+#define __HAL_HRTIM_GetCounter        __HAL_HRTIM_GETCOUNTER
+#define __HAL_HRTIM_SetPeriod         __HAL_HRTIM_SETPERIOD
+#define __HAL_HRTIM_GetPeriod         __HAL_HRTIM_GETPERIOD
+#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
+#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
+#define __HAL_HRTIM_SetCompare        __HAL_HRTIM_SETCOMPARE
+#define __HAL_HRTIM_GetCompare        __HAL_HRTIM_GETCOMPARE
+
+#if defined(STM32G4)
+#define HAL_HRTIM_ExternalEventCounterConfig    HAL_HRTIM_ExtEventCounterConfig
+#define HAL_HRTIM_ExternalEventCounterEnable    HAL_HRTIM_ExtEventCounterEnable
+#define HAL_HRTIM_ExternalEventCounterDisable   HAL_HRTIM_ExtEventCounterDisable
+#define HAL_HRTIM_ExternalEventCounterReset     HAL_HRTIM_ExtEventCounterReset
+#endif /* STM32G4 */
+
+#if defined(STM32H7)
+#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
+
+#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
+#endif /* STM32H7 */
+
+#if defined(STM32F3)
+/** @brief Constants defining available sources associated to external events.
+  */
+#define HRTIM_EVENTSRC_1              (0x00000000U)
+#define HRTIM_EVENTSRC_2              (HRTIM_EECR1_EE1SRC_0)
+#define HRTIM_EVENTSRC_3              (HRTIM_EECR1_EE1SRC_1)
+#define HRTIM_EVENTSRC_4              (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
+
+/** @brief Constants defining the events that can be selected to configure the
+  *        set/reset crossbar of a timer output
+  */
+#define HRTIM_OUTPUTSET_TIMEV_1       (HRTIM_SET1R_TIMEVNT1)
+#define HRTIM_OUTPUTSET_TIMEV_2       (HRTIM_SET1R_TIMEVNT2)
+#define HRTIM_OUTPUTSET_TIMEV_3       (HRTIM_SET1R_TIMEVNT3)
+#define HRTIM_OUTPUTSET_TIMEV_4       (HRTIM_SET1R_TIMEVNT4)
+#define HRTIM_OUTPUTSET_TIMEV_5       (HRTIM_SET1R_TIMEVNT5)
+#define HRTIM_OUTPUTSET_TIMEV_6       (HRTIM_SET1R_TIMEVNT6)
+#define HRTIM_OUTPUTSET_TIMEV_7       (HRTIM_SET1R_TIMEVNT7)
+#define HRTIM_OUTPUTSET_TIMEV_8       (HRTIM_SET1R_TIMEVNT8)
+#define HRTIM_OUTPUTSET_TIMEV_9       (HRTIM_SET1R_TIMEVNT9)
+
+#define HRTIM_OUTPUTRESET_TIMEV_1     (HRTIM_RST1R_TIMEVNT1)
+#define HRTIM_OUTPUTRESET_TIMEV_2     (HRTIM_RST1R_TIMEVNT2)
+#define HRTIM_OUTPUTRESET_TIMEV_3     (HRTIM_RST1R_TIMEVNT3)
+#define HRTIM_OUTPUTRESET_TIMEV_4     (HRTIM_RST1R_TIMEVNT4)
+#define HRTIM_OUTPUTRESET_TIMEV_5     (HRTIM_RST1R_TIMEVNT5)
+#define HRTIM_OUTPUTRESET_TIMEV_6     (HRTIM_RST1R_TIMEVNT6)
+#define HRTIM_OUTPUTRESET_TIMEV_7     (HRTIM_RST1R_TIMEVNT7)
+#define HRTIM_OUTPUTRESET_TIMEV_8     (HRTIM_RST1R_TIMEVNT8)
+#define HRTIM_OUTPUTRESET_TIMEV_9     (HRTIM_RST1R_TIMEVNT9)
+
+/** @brief Constants defining the event filtering applied to external events
+  *        by a timer
+  */
+#define HRTIM_TIMEVENTFILTER_NONE             (0x00000000U)
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1     (HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2     (HRTIM_EEFR1_EE1FLTR_1)
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3     (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4     (HRTIM_EEFR1_EE1FLTR_2)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4    (HRTIM_EEFR1_EE1FLTR_3)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)
+#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
+#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM     (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
+
+/** @brief Constants defining the DLL calibration periods (in micro seconds)
+  */
+#define HRTIM_CALIBRATIONRATE_7300             0x00000000U
+#define HRTIM_CALIBRATIONRATE_910              (HRTIM_DLLCR_CALRTE_0)
+#define HRTIM_CALIBRATIONRATE_114              (HRTIM_DLLCR_CALRTE_1)
+#define HRTIM_CALIBRATIONRATE_14               (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
+
+#endif /* STM32F3 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define I2C_DUALADDRESS_DISABLED                I2C_DUALADDRESS_DISABLE
+#define I2C_DUALADDRESS_ENABLED                 I2C_DUALADDRESS_ENABLE
+#define I2C_GENERALCALL_DISABLED                I2C_GENERALCALL_DISABLE
+#define I2C_GENERALCALL_ENABLED                 I2C_GENERALCALL_ENABLE
+#define I2C_NOSTRETCH_DISABLED                  I2C_NOSTRETCH_DISABLE
+#define I2C_NOSTRETCH_ENABLED                   I2C_NOSTRETCH_ENABLE
+#define I2C_ANALOGFILTER_ENABLED                I2C_ANALOGFILTER_ENABLE
+#define I2C_ANALOGFILTER_DISABLED               I2C_ANALOGFILTER_DISABLE
+#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
+#define HAL_I2C_STATE_MEM_BUSY_TX               HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_MEM_BUSY_RX               HAL_I2C_STATE_BUSY_RX
+#define HAL_I2C_STATE_MASTER_BUSY_TX            HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_MASTER_BUSY_RX            HAL_I2C_STATE_BUSY_RX
+#define HAL_I2C_STATE_SLAVE_BUSY_TX             HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_SLAVE_BUSY_RX             HAL_I2C_STATE_BUSY_RX
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define IRDA_ONE_BIT_SAMPLE_DISABLED            IRDA_ONE_BIT_SAMPLE_DISABLE
+#define IRDA_ONE_BIT_SAMPLE_ENABLED             IRDA_ONE_BIT_SAMPLE_ENABLE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define KR_KEY_RELOAD                   IWDG_KEY_RELOAD
+#define KR_KEY_ENABLE                   IWDG_KEY_ENABLE
+#define KR_KEY_EWA                      IWDG_KEY_WRITE_ACCESS_ENABLE
+#define KR_KEY_DWA                      IWDG_KEY_WRITE_ACCESS_DISABLE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
+
+#define LPTIM_CLOCKPOLARITY_RISINGEDGE          LPTIM_CLOCKPOLARITY_RISING
+#define LPTIM_CLOCKPOLARITY_FALLINGEDGE         LPTIM_CLOCKPOLARITY_FALLING
+#define LPTIM_CLOCKPOLARITY_BOTHEDGES           LPTIM_CLOCKPOLARITY_RISING_FALLING
+
+#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION  LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS      LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS      LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS      LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+/* The following 3 definition have also been present in a temporary version of lptim.h */
+/* They need to be renamed also to the right name, just in case */
+#define LPTIM_TRIGSAMPLETIME_2TRANSITION        LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSITION        LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSITION        LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define HAL_NAND_Read_Page              HAL_NAND_Read_Page_8b
+#define HAL_NAND_Write_Page             HAL_NAND_Write_Page_8b
+#define HAL_NAND_Read_SpareArea         HAL_NAND_Read_SpareArea_8b
+#define HAL_NAND_Write_SpareArea        HAL_NAND_Write_SpareArea_8b
+
+#define NAND_AddressTypedef             NAND_AddressTypeDef
+
+#define __ARRAY_ADDRESS                 ARRAY_ADDRESS
+#define __ADDR_1st_CYCLE                ADDR_1ST_CYCLE
+#define __ADDR_2nd_CYCLE                ADDR_2ND_CYCLE
+#define __ADDR_3rd_CYCLE                ADDR_3RD_CYCLE
+#define __ADDR_4th_CYCLE                ADDR_4TH_CYCLE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define NOR_StatusTypedef              HAL_NOR_StatusTypeDef
+#define NOR_SUCCESS                    HAL_NOR_STATUS_SUCCESS
+#define NOR_ONGOING                    HAL_NOR_STATUS_ONGOING
+#define NOR_ERROR                      HAL_NOR_STATUS_ERROR
+#define NOR_TIMEOUT                    HAL_NOR_STATUS_TIMEOUT
+
+#define __NOR_WRITE                    NOR_WRITE
+#define __NOR_ADDR_SHIFT               NOR_ADDR_SHIFT
+/**
+  * @}
+  */
+
+/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define OPAMP_NONINVERTINGINPUT_VP0           OPAMP_NONINVERTINGINPUT_IO0
+#define OPAMP_NONINVERTINGINPUT_VP1           OPAMP_NONINVERTINGINPUT_IO1
+#define OPAMP_NONINVERTINGINPUT_VP2           OPAMP_NONINVERTINGINPUT_IO2
+#define OPAMP_NONINVERTINGINPUT_VP3           OPAMP_NONINVERTINGINPUT_IO3
+
+#define OPAMP_SEC_NONINVERTINGINPUT_VP0       OPAMP_SEC_NONINVERTINGINPUT_IO0
+#define OPAMP_SEC_NONINVERTINGINPUT_VP1       OPAMP_SEC_NONINVERTINGINPUT_IO1
+#define OPAMP_SEC_NONINVERTINGINPUT_VP2       OPAMP_SEC_NONINVERTINGINPUT_IO2
+#define OPAMP_SEC_NONINVERTINGINPUT_VP3       OPAMP_SEC_NONINVERTINGINPUT_IO3
+
+#define OPAMP_INVERTINGINPUT_VM0              OPAMP_INVERTINGINPUT_IO0
+#define OPAMP_INVERTINGINPUT_VM1              OPAMP_INVERTINGINPUT_IO1
+
+#define IOPAMP_INVERTINGINPUT_VM0             OPAMP_INVERTINGINPUT_IO0
+#define IOPAMP_INVERTINGINPUT_VM1             OPAMP_INVERTINGINPUT_IO1
+
+#define OPAMP_SEC_INVERTINGINPUT_VM0          OPAMP_SEC_INVERTINGINPUT_IO0
+#define OPAMP_SEC_INVERTINGINPUT_VM1          OPAMP_SEC_INVERTINGINPUT_IO1
+
+#define OPAMP_INVERTINGINPUT_VINM             OPAMP_SEC_INVERTINGINPUT_IO1
+
+#define OPAMP_PGACONNECT_NO                   OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
+#define OPAMP_PGACONNECT_VM0                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
+#define OPAMP_PGACONNECT_VM1                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
+
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
+#define HAL_OPAMP_MSP_INIT_CB_ID       HAL_OPAMP_MSPINIT_CB_ID
+#define HAL_OPAMP_MSP_DEINIT_CB_ID     HAL_OPAMP_MSPDEINIT_CB_ID
+#endif
+
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define I2S_STANDARD_PHILLIPS      I2S_STANDARD_PHILIPS
+
+#if defined(STM32H7)
+  #define I2S_IT_TXE               I2S_IT_TXP
+  #define I2S_IT_RXNE              I2S_IT_RXP
+
+  #define I2S_FLAG_TXE             I2S_FLAG_TXP
+  #define I2S_FLAG_RXNE            I2S_FLAG_RXP
+#endif
+
+#if defined(STM32F7)
+  #define I2S_CLOCK_SYSCLK           I2S_CLOCK_PLL
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+/* Compact Flash-ATA registers description */
+#define CF_DATA                       ATA_DATA
+#define CF_SECTOR_COUNT               ATA_SECTOR_COUNT
+#define CF_SECTOR_NUMBER              ATA_SECTOR_NUMBER
+#define CF_CYLINDER_LOW               ATA_CYLINDER_LOW
+#define CF_CYLINDER_HIGH              ATA_CYLINDER_HIGH
+#define CF_CARD_HEAD                  ATA_CARD_HEAD
+#define CF_STATUS_CMD                 ATA_STATUS_CMD
+#define CF_STATUS_CMD_ALTERNATE       ATA_STATUS_CMD_ALTERNATE
+#define CF_COMMON_DATA_AREA           ATA_COMMON_DATA_AREA
+
+/* Compact Flash-ATA commands */
+#define CF_READ_SECTOR_CMD            ATA_READ_SECTOR_CMD
+#define CF_WRITE_SECTOR_CMD           ATA_WRITE_SECTOR_CMD
+#define CF_ERASE_SECTOR_CMD           ATA_ERASE_SECTOR_CMD
+#define CF_IDENTIFY_CMD               ATA_IDENTIFY_CMD
+
+#define PCCARD_StatusTypedef          HAL_PCCARD_StatusTypeDef
+#define PCCARD_SUCCESS                HAL_PCCARD_STATUS_SUCCESS
+#define PCCARD_ONGOING                HAL_PCCARD_STATUS_ONGOING
+#define PCCARD_ERROR                  HAL_PCCARD_STATUS_ERROR
+#define PCCARD_TIMEOUT                HAL_PCCARD_STATUS_TIMEOUT
+/**
+  * @}
+  */
+  
+/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define FORMAT_BIN                  RTC_FORMAT_BIN
+#define FORMAT_BCD                  RTC_FORMAT_BCD
+
+#define RTC_ALARMSUBSECONDMASK_None     RTC_ALARMSUBSECONDMASK_NONE
+#define RTC_TAMPERERASEBACKUP_DISABLED  RTC_TAMPER_ERASE_BACKUP_DISABLE
+#define RTC_TAMPERMASK_FLAG_DISABLED    RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_TAMPERMASK_FLAG_ENABLED     RTC_TAMPERMASK_FLAG_ENABLE
+
+#define RTC_MASKTAMPERFLAG_DISABLED     RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE
+#define RTC_TAMPERERASEBACKUP_ENABLED   RTC_TAMPER_ERASE_BACKUP_ENABLE
+#define RTC_TAMPER1_2_INTERRUPT         RTC_ALL_TAMPER_INTERRUPT
+#define RTC_TAMPER1_2_3_INTERRUPT       RTC_ALL_TAMPER_INTERRUPT
+
+#define RTC_TIMESTAMPPIN_PC13  RTC_TIMESTAMPPIN_DEFAULT
+#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PC1   RTC_TIMESTAMPPIN_POS2
+
+#define RTC_OUTPUT_REMAP_PC13  RTC_OUTPUT_REMAP_NONE
+#define RTC_OUTPUT_REMAP_PB14  RTC_OUTPUT_REMAP_POS1
+#define RTC_OUTPUT_REMAP_PB2   RTC_OUTPUT_REMAP_POS1
+
+#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
+#define RTC_TAMPERPIN_PA0  RTC_TAMPERPIN_POS1
+#define RTC_TAMPERPIN_PI8  RTC_TAMPERPIN_POS1
+
+#if defined(STM32H7)
+#define RTC_TAMPCR_TAMPXE          RTC_TAMPER_X
+#define RTC_TAMPCR_TAMPXIE         RTC_TAMPER_X_INTERRUPT
+
+#define RTC_TAMPER1_INTERRUPT      RTC_IT_TAMP1
+#define RTC_TAMPER2_INTERRUPT      RTC_IT_TAMP2
+#define RTC_TAMPER3_INTERRUPT      RTC_IT_TAMP3
+#define RTC_ALL_TAMPER_INTERRUPT   RTC_IT_TAMPALL
+#endif /* STM32H7 */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define SMARTCARD_NACK_ENABLED                  SMARTCARD_NACK_ENABLE
+#define SMARTCARD_NACK_DISABLED                 SMARTCARD_NACK_DISABLE
+
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLED      SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLED       SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLE       SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLE        SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+
+#define SMARTCARD_TIMEOUT_DISABLED              SMARTCARD_TIMEOUT_DISABLE
+#define SMARTCARD_TIMEOUT_ENABLED               SMARTCARD_TIMEOUT_ENABLE
+
+#define SMARTCARD_LASTBIT_DISABLED              SMARTCARD_LASTBIT_DISABLE
+#define SMARTCARD_LASTBIT_ENABLED               SMARTCARD_LASTBIT_ENABLE
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define SMBUS_DUALADDRESS_DISABLED      SMBUS_DUALADDRESS_DISABLE
+#define SMBUS_DUALADDRESS_ENABLED       SMBUS_DUALADDRESS_ENABLE
+#define SMBUS_GENERALCALL_DISABLED      SMBUS_GENERALCALL_DISABLE
+#define SMBUS_GENERALCALL_ENABLED       SMBUS_GENERALCALL_ENABLE
+#define SMBUS_NOSTRETCH_DISABLED        SMBUS_NOSTRETCH_DISABLE
+#define SMBUS_NOSTRETCH_ENABLED         SMBUS_NOSTRETCH_ENABLE
+#define SMBUS_ANALOGFILTER_ENABLED      SMBUS_ANALOGFILTER_ENABLE
+#define SMBUS_ANALOGFILTER_DISABLED     SMBUS_ANALOGFILTER_DISABLE
+#define SMBUS_PEC_DISABLED              SMBUS_PEC_DISABLE
+#define SMBUS_PEC_ENABLED               SMBUS_PEC_ENABLE
+#define HAL_SMBUS_STATE_SLAVE_LISTEN    HAL_SMBUS_STATE_LISTEN
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define SPI_TIMODE_DISABLED             SPI_TIMODE_DISABLE
+#define SPI_TIMODE_ENABLED              SPI_TIMODE_ENABLE
+
+#define SPI_CRCCALCULATION_DISABLED     SPI_CRCCALCULATION_DISABLE
+#define SPI_CRCCALCULATION_ENABLED      SPI_CRCCALCULATION_ENABLE
+
+#define SPI_NSS_PULSE_DISABLED          SPI_NSS_PULSE_DISABLE
+#define SPI_NSS_PULSE_ENABLED           SPI_NSS_PULSE_ENABLE
+
+#if defined(STM32H7)
+
+ #define SPI_FLAG_TXE                    SPI_FLAG_TXP
+ #define SPI_FLAG_RXNE                   SPI_FLAG_RXP
+
+ #define SPI_IT_TXE                      SPI_IT_TXP
+ #define SPI_IT_RXNE                     SPI_IT_RXP
+
+ #define SPI_FRLVL_EMPTY                 SPI_RX_FIFO_0PACKET
+ #define SPI_FRLVL_QUARTER_FULL          SPI_RX_FIFO_1PACKET
+ #define SPI_FRLVL_HALF_FULL             SPI_RX_FIFO_2PACKET
+ #define SPI_FRLVL_FULL                  SPI_RX_FIFO_3PACKET
+
+#endif /* STM32H7 */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define CCER_CCxE_MASK                   TIM_CCER_CCxE_MASK
+#define CCER_CCxNE_MASK                  TIM_CCER_CCxNE_MASK
+
+#define TIM_DMABase_CR1                  TIM_DMABASE_CR1
+#define TIM_DMABase_CR2                  TIM_DMABASE_CR2
+#define TIM_DMABase_SMCR                 TIM_DMABASE_SMCR
+#define TIM_DMABase_DIER                 TIM_DMABASE_DIER
+#define TIM_DMABase_SR                   TIM_DMABASE_SR
+#define TIM_DMABase_EGR                  TIM_DMABASE_EGR
+#define TIM_DMABase_CCMR1                TIM_DMABASE_CCMR1
+#define TIM_DMABase_CCMR2                TIM_DMABASE_CCMR2
+#define TIM_DMABase_CCER                 TIM_DMABASE_CCER
+#define TIM_DMABase_CNT                  TIM_DMABASE_CNT
+#define TIM_DMABase_PSC                  TIM_DMABASE_PSC
+#define TIM_DMABase_ARR                  TIM_DMABASE_ARR
+#define TIM_DMABase_RCR                  TIM_DMABASE_RCR
+#define TIM_DMABase_CCR1                 TIM_DMABASE_CCR1
+#define TIM_DMABase_CCR2                 TIM_DMABASE_CCR2
+#define TIM_DMABase_CCR3                 TIM_DMABASE_CCR3
+#define TIM_DMABase_CCR4                 TIM_DMABASE_CCR4
+#define TIM_DMABase_BDTR                 TIM_DMABASE_BDTR
+#define TIM_DMABase_DCR                  TIM_DMABASE_DCR
+#define TIM_DMABase_DMAR                 TIM_DMABASE_DMAR
+#define TIM_DMABase_OR1                  TIM_DMABASE_OR1
+#define TIM_DMABase_CCMR3                TIM_DMABASE_CCMR3
+#define TIM_DMABase_CCR5                 TIM_DMABASE_CCR5
+#define TIM_DMABase_CCR6                 TIM_DMABASE_CCR6
+#define TIM_DMABase_OR2                  TIM_DMABASE_OR2
+#define TIM_DMABase_OR3                  TIM_DMABASE_OR3
+#define TIM_DMABase_OR                   TIM_DMABASE_OR
+
+#define TIM_EventSource_Update           TIM_EVENTSOURCE_UPDATE
+#define TIM_EventSource_CC1              TIM_EVENTSOURCE_CC1
+#define TIM_EventSource_CC2              TIM_EVENTSOURCE_CC2
+#define TIM_EventSource_CC3              TIM_EVENTSOURCE_CC3
+#define TIM_EventSource_CC4              TIM_EVENTSOURCE_CC4
+#define TIM_EventSource_COM              TIM_EVENTSOURCE_COM
+#define TIM_EventSource_Trigger          TIM_EVENTSOURCE_TRIGGER
+#define TIM_EventSource_Break            TIM_EVENTSOURCE_BREAK
+#define TIM_EventSource_Break2           TIM_EVENTSOURCE_BREAK2
+
+#define TIM_DMABurstLength_1Transfer     TIM_DMABURSTLENGTH_1TRANSFER
+#define TIM_DMABurstLength_2Transfers    TIM_DMABURSTLENGTH_2TRANSFERS
+#define TIM_DMABurstLength_3Transfers    TIM_DMABURSTLENGTH_3TRANSFERS
+#define TIM_DMABurstLength_4Transfers    TIM_DMABURSTLENGTH_4TRANSFERS
+#define TIM_DMABurstLength_5Transfers    TIM_DMABURSTLENGTH_5TRANSFERS
+#define TIM_DMABurstLength_6Transfers    TIM_DMABURSTLENGTH_6TRANSFERS
+#define TIM_DMABurstLength_7Transfers    TIM_DMABURSTLENGTH_7TRANSFERS
+#define TIM_DMABurstLength_8Transfers    TIM_DMABURSTLENGTH_8TRANSFERS
+#define TIM_DMABurstLength_9Transfers    TIM_DMABURSTLENGTH_9TRANSFERS
+#define TIM_DMABurstLength_10Transfers   TIM_DMABURSTLENGTH_10TRANSFERS
+#define TIM_DMABurstLength_11Transfers   TIM_DMABURSTLENGTH_11TRANSFERS
+#define TIM_DMABurstLength_12Transfers   TIM_DMABURSTLENGTH_12TRANSFERS
+#define TIM_DMABurstLength_13Transfers   TIM_DMABURSTLENGTH_13TRANSFERS
+#define TIM_DMABurstLength_14Transfers   TIM_DMABURSTLENGTH_14TRANSFERS
+#define TIM_DMABurstLength_15Transfers   TIM_DMABURSTLENGTH_15TRANSFERS
+#define TIM_DMABurstLength_16Transfers   TIM_DMABURSTLENGTH_16TRANSFERS
+#define TIM_DMABurstLength_17Transfers   TIM_DMABURSTLENGTH_17TRANSFERS
+#define TIM_DMABurstLength_18Transfers   TIM_DMABURSTLENGTH_18TRANSFERS
+
+#if defined(STM32L0)
+#define TIM22_TI1_GPIO1   TIM22_TI1_GPIO
+#define TIM22_TI1_GPIO2   TIM22_TI1_GPIO
+#endif
+
+#if defined(STM32F3)
+#define IS_TIM_HALL_INTERFACE_INSTANCE   IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
+#endif
+
+#if defined(STM32H7)
+#define TIM_TIM1_ETR_COMP1_OUT        TIM_TIM1_ETR_COMP1
+#define TIM_TIM1_ETR_COMP2_OUT        TIM_TIM1_ETR_COMP2
+#define TIM_TIM8_ETR_COMP1_OUT        TIM_TIM8_ETR_COMP1
+#define TIM_TIM8_ETR_COMP2_OUT        TIM_TIM8_ETR_COMP2
+#define TIM_TIM2_ETR_COMP1_OUT        TIM_TIM2_ETR_COMP1
+#define TIM_TIM2_ETR_COMP2_OUT        TIM_TIM2_ETR_COMP2
+#define TIM_TIM3_ETR_COMP1_OUT        TIM_TIM3_ETR_COMP1
+#define TIM_TIM1_TI1_COMP1_OUT        TIM_TIM1_TI1_COMP1
+#define TIM_TIM8_TI1_COMP2_OUT        TIM_TIM8_TI1_COMP2
+#define TIM_TIM2_TI4_COMP1_OUT        TIM_TIM2_TI4_COMP1
+#define TIM_TIM2_TI4_COMP2_OUT        TIM_TIM2_TI4_COMP2
+#define TIM_TIM2_TI4_COMP1COMP2_OUT   TIM_TIM2_TI4_COMP1_COMP2
+#define TIM_TIM3_TI1_COMP1_OUT        TIM_TIM3_TI1_COMP1
+#define TIM_TIM3_TI1_COMP2_OUT        TIM_TIM3_TI1_COMP2
+#define TIM_TIM3_TI1_COMP1COMP2_OUT   TIM_TIM3_TI1_COMP1_COMP2
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define TSC_SYNC_POL_FALL        TSC_SYNC_POLARITY_FALLING
+#define TSC_SYNC_POL_RISE_HIGH   TSC_SYNC_POLARITY_RISING
+/**
+  * @}
+  */
+
+/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define UART_ONEBIT_SAMPLING_DISABLED   UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONEBIT_SAMPLING_ENABLED    UART_ONE_BIT_SAMPLE_ENABLE
+#define UART_ONE_BIT_SAMPLE_DISABLED    UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONE_BIT_SAMPLE_ENABLED     UART_ONE_BIT_SAMPLE_ENABLE
+
+#define __HAL_UART_ONEBIT_ENABLE        __HAL_UART_ONE_BIT_SAMPLE_ENABLE
+#define __HAL_UART_ONEBIT_DISABLE       __HAL_UART_ONE_BIT_SAMPLE_DISABLE
+
+#define __DIV_SAMPLING16                UART_DIV_SAMPLING16
+#define __DIVMANT_SAMPLING16            UART_DIVMANT_SAMPLING16
+#define __DIVFRAQ_SAMPLING16            UART_DIVFRAQ_SAMPLING16
+#define __UART_BRR_SAMPLING16           UART_BRR_SAMPLING16
+
+#define __DIV_SAMPLING8                 UART_DIV_SAMPLING8
+#define __DIVMANT_SAMPLING8             UART_DIVMANT_SAMPLING8
+#define __DIVFRAQ_SAMPLING8             UART_DIVFRAQ_SAMPLING8
+#define __UART_BRR_SAMPLING8            UART_BRR_SAMPLING8
+
+#define __DIV_LPUART                    UART_DIV_LPUART
+
+#define UART_WAKEUPMETHODE_IDLELINE     UART_WAKEUPMETHOD_IDLELINE
+#define UART_WAKEUPMETHODE_ADDRESSMARK  UART_WAKEUPMETHOD_ADDRESSMARK
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define USART_CLOCK_DISABLED            USART_CLOCK_DISABLE
+#define USART_CLOCK_ENABLED             USART_CLOCK_ENABLE
+
+#define USARTNACK_ENABLED               USART_NACK_ENABLE
+#define USARTNACK_DISABLED              USART_NACK_DISABLE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define CFR_BASE                    WWDG_CFR_BASE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define CAN_FilterFIFO0             CAN_FILTER_FIFO0
+#define CAN_FilterFIFO1             CAN_FILTER_FIFO1
+#define CAN_IT_RQCP0                CAN_IT_TME
+#define CAN_IT_RQCP1                CAN_IT_TME
+#define CAN_IT_RQCP2                CAN_IT_TME
+#define INAK_TIMEOUT                CAN_TIMEOUT_VALUE
+#define SLAK_TIMEOUT                CAN_TIMEOUT_VALUE
+#define CAN_TXSTATUS_FAILED         ((uint8_t)0x00U)
+#define CAN_TXSTATUS_OK             ((uint8_t)0x01U)
+#define CAN_TXSTATUS_PENDING        ((uint8_t)0x02U)
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define VLAN_TAG                ETH_VLAN_TAG
+#define MIN_ETH_PAYLOAD         ETH_MIN_ETH_PAYLOAD
+#define MAX_ETH_PAYLOAD         ETH_MAX_ETH_PAYLOAD
+#define JUMBO_FRAME_PAYLOAD     ETH_JUMBO_FRAME_PAYLOAD
+#define MACMIIAR_CR_MASK        ETH_MACMIIAR_CR_MASK
+#define MACCR_CLEAR_MASK        ETH_MACCR_CLEAR_MASK
+#define MACFCR_CLEAR_MASK       ETH_MACFCR_CLEAR_MASK
+#define DMAOMR_CLEAR_MASK       ETH_DMAOMR_CLEAR_MASK
+
+#define ETH_MMCCR              0x00000100U
+#define ETH_MMCRIR             0x00000104U
+#define ETH_MMCTIR             0x00000108U
+#define ETH_MMCRIMR            0x0000010CU
+#define ETH_MMCTIMR            0x00000110U
+#define ETH_MMCTGFSCCR         0x0000014CU
+#define ETH_MMCTGFMSCCR        0x00000150U
+#define ETH_MMCTGFCR           0x00000168U
+#define ETH_MMCRFCECR          0x00000194U
+#define ETH_MMCRFAECR          0x00000198U
+#define ETH_MMCRGUFCR          0x000001C4U
+
+#define ETH_MAC_TXFIFO_FULL                             0x02000000U  /* Tx FIFO full */
+#define ETH_MAC_TXFIFONOT_EMPTY                         0x01000000U  /* Tx FIFO not empty */
+#define ETH_MAC_TXFIFO_WRITE_ACTIVE                     0x00400000U  /* Tx FIFO write active */
+#define ETH_MAC_TXFIFO_IDLE                             0x00000000U  /* Tx FIFO read status: Idle */
+#define ETH_MAC_TXFIFO_READ                             0x00100000U  /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
+#define ETH_MAC_TXFIFO_WAITING                          0x00200000U  /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
+#define ETH_MAC_TXFIFO_WRITING                          0x00300000U  /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
+#define ETH_MAC_TRANSMISSION_PAUSE                      0x00080000U  /* MAC transmitter in pause */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE            0x00000000U  /* MAC transmit frame controller: Idle */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING         0x00020000U  /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF   0x00040000U  /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING    0x00060000U  /* MAC transmit frame controller: Transferring input frame for transmission */
+#define ETH_MAC_MII_TRANSMIT_ACTIVE           0x00010000U  /* MAC MII transmit engine active */
+#define ETH_MAC_RXFIFO_EMPTY                  0x00000000U  /* Rx FIFO fill level: empty */
+#define ETH_MAC_RXFIFO_BELOW_THRESHOLD        0x00000100U  /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
+#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD        0x00000200U  /* Rx FIFO fill level: fill-level above flow-control activate threshold */
+#define ETH_MAC_RXFIFO_FULL                   0x00000300U  /* Rx FIFO fill level: full */
+#if defined(STM32F1)
+#else
+#define ETH_MAC_READCONTROLLER_IDLE           0x00000000U  /* Rx FIFO read controller IDLE state */
+#define ETH_MAC_READCONTROLLER_READING_DATA   0x00000020U  /* Rx FIFO read controller Reading frame data */
+#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U  /* Rx FIFO read controller Reading frame status (or time-stamp) */
+#endif
+#define ETH_MAC_READCONTROLLER_FLUSHING       0x00000060U  /* Rx FIFO read controller Flushing the frame data and status */
+#define ETH_MAC_RXFIFO_WRITE_ACTIVE           0x00000010U  /* Rx FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_NOTACTIVE          0x00000000U  /* MAC small FIFO read / write controllers not active */
+#define ETH_MAC_SMALL_FIFO_READ_ACTIVE        0x00000002U  /* MAC small FIFO read controller active */
+#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE       0x00000004U  /* MAC small FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_RW_ACTIVE          0x00000006U  /* MAC small FIFO read / write controllers active */
+#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE   0x00000001U  /* MAC MII receive protocol engine active */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define HAL_DCMI_ERROR_OVF      HAL_DCMI_ERROR_OVR
+#define DCMI_IT_OVF             DCMI_IT_OVR
+#define DCMI_FLAG_OVFRI         DCMI_FLAG_OVRRI
+#define DCMI_FLAG_OVFMI         DCMI_FLAG_OVRMI
+
+#define HAL_DCMI_ConfigCROP     HAL_DCMI_ConfigCrop
+#define HAL_DCMI_EnableCROP     HAL_DCMI_EnableCrop
+#define HAL_DCMI_DisableCROP    HAL_DCMI_DisableCrop
+
+/**
+  * @}
+  */
+
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
+  || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
+  || defined(STM32H7)
+/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define DMA2D_ARGB8888          DMA2D_OUTPUT_ARGB8888
+#define DMA2D_RGB888            DMA2D_OUTPUT_RGB888
+#define DMA2D_RGB565            DMA2D_OUTPUT_RGB565
+#define DMA2D_ARGB1555          DMA2D_OUTPUT_ARGB1555
+#define DMA2D_ARGB4444          DMA2D_OUTPUT_ARGB4444
+
+#define CM_ARGB8888             DMA2D_INPUT_ARGB8888
+#define CM_RGB888               DMA2D_INPUT_RGB888
+#define CM_RGB565               DMA2D_INPUT_RGB565
+#define CM_ARGB1555             DMA2D_INPUT_ARGB1555
+#define CM_ARGB4444             DMA2D_INPUT_ARGB4444
+#define CM_L8                   DMA2D_INPUT_L8
+#define CM_AL44                 DMA2D_INPUT_AL44
+#define CM_AL88                 DMA2D_INPUT_AL88
+#define CM_L4                   DMA2D_INPUT_L4
+#define CM_A8                   DMA2D_INPUT_A8
+#define CM_A4                   DMA2D_INPUT_A4
+/**
+  * @}
+  */
+#endif  /* STM32L4 ||  STM32F7 ||  STM32F4 ||  STM32H7 */
+
+/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_CRYP_ComputationCpltCallback     HAL_CRYPEx_ComputationCpltCallback
+/**
+  * @}
+  */
+
+/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_HASH_STATETypeDef        HAL_HASH_StateTypeDef
+#define HAL_HASHPhaseTypeDef         HAL_HASH_PhaseTypeDef
+#define HAL_HMAC_MD5_Finish          HAL_HASH_MD5_Finish
+#define HAL_HMAC_SHA1_Finish         HAL_HASH_SHA1_Finish
+#define HAL_HMAC_SHA224_Finish       HAL_HASH_SHA224_Finish
+#define HAL_HMAC_SHA256_Finish       HAL_HASH_SHA256_Finish
+
+/*HASH Algorithm Selection*/
+
+#define HASH_AlgoSelection_SHA1      HASH_ALGOSELECTION_SHA1
+#define HASH_AlgoSelection_SHA224    HASH_ALGOSELECTION_SHA224
+#define HASH_AlgoSelection_SHA256    HASH_ALGOSELECTION_SHA256
+#define HASH_AlgoSelection_MD5       HASH_ALGOSELECTION_MD5
+
+#define HASH_AlgoMode_HASH         HASH_ALGOMODE_HASH
+#define HASH_AlgoMode_HMAC         HASH_ALGOMODE_HMAC
+
+#define HASH_HMACKeyType_ShortKey  HASH_HMAC_KEYTYPE_SHORTKEY
+#define HASH_HMACKeyType_LongKey   HASH_HMAC_KEYTYPE_LONGKEY
+
+#if defined(STM32L4) || defined(STM32L5) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
+
+#define HAL_HASH_MD5_Accumulate                HAL_HASH_MD5_Accmlt
+#define HAL_HASH_MD5_Accumulate_End            HAL_HASH_MD5_Accmlt_End
+#define HAL_HASH_MD5_Accumulate_IT             HAL_HASH_MD5_Accmlt_IT
+#define HAL_HASH_MD5_Accumulate_End_IT         HAL_HASH_MD5_Accmlt_End_IT
+
+#define HAL_HASH_SHA1_Accumulate               HAL_HASH_SHA1_Accmlt
+#define HAL_HASH_SHA1_Accumulate_End           HAL_HASH_SHA1_Accmlt_End
+#define HAL_HASH_SHA1_Accumulate_IT            HAL_HASH_SHA1_Accmlt_IT
+#define HAL_HASH_SHA1_Accumulate_End_IT        HAL_HASH_SHA1_Accmlt_End_IT
+
+#define HAL_HASHEx_SHA224_Accumulate           HAL_HASHEx_SHA224_Accmlt
+#define HAL_HASHEx_SHA224_Accumulate_End       HAL_HASHEx_SHA224_Accmlt_End
+#define HAL_HASHEx_SHA224_Accumulate_IT        HAL_HASHEx_SHA224_Accmlt_IT
+#define HAL_HASHEx_SHA224_Accumulate_End_IT    HAL_HASHEx_SHA224_Accmlt_End_IT
+
+#define HAL_HASHEx_SHA256_Accumulate           HAL_HASHEx_SHA256_Accmlt
+#define HAL_HASHEx_SHA256_Accumulate_End       HAL_HASHEx_SHA256_Accmlt_End
+#define HAL_HASHEx_SHA256_Accumulate_IT        HAL_HASHEx_SHA256_Accmlt_IT
+#define HAL_HASHEx_SHA256_Accumulate_End_IT    HAL_HASHEx_SHA256_Accmlt_End_IT
+
+#endif  /* STM32L4 || STM32L5 || STM32F4 || STM32F7 || STM32H7 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
+#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
+#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
+#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
+#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
+#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
+#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
+#define HAL_VREFINT_OutputSelect  HAL_SYSCFG_VREFINT_OutputSelect
+#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
+#if defined(STM32L0)
+#else
+#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
+#endif
+#define HAL_ADC_EnableBuffer_Cmd(cmd)  (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
+#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ?  HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
+#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
+#define HAL_EnableSRDomainDBGStopMode      HAL_EnableDomain3DBGStopMode
+#define HAL_DisableSRDomainDBGStopMode     HAL_DisableDomain3DBGStopMode
+#define HAL_EnableSRDomainDBGStandbyMode   HAL_EnableDomain3DBGStandbyMode
+#define HAL_DisableSRDomainDBGStandbyMode  HAL_DisableDomain3DBGStandbyMode
+#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ  || STM32H7B0xxQ */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define FLASH_HalfPageProgram      HAL_FLASHEx_HalfPageProgram
+#define FLASH_EnableRunPowerDown   HAL_FLASHEx_EnableRunPowerDown
+#define FLASH_DisableRunPowerDown  HAL_FLASHEx_DisableRunPowerDown
+#define HAL_DATA_EEPROMEx_Unlock   HAL_FLASHEx_DATAEEPROM_Unlock
+#define HAL_DATA_EEPROMEx_Lock     HAL_FLASHEx_DATAEEPROM_Lock
+#define HAL_DATA_EEPROMEx_Erase    HAL_FLASHEx_DATAEEPROM_Erase
+#define HAL_DATA_EEPROMEx_Program  HAL_FLASHEx_DATAEEPROM_Program
+
+ /**
+  * @}
+  */
+
+/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_I2CEx_AnalogFilter_Config         HAL_I2CEx_ConfigAnalogFilter
+#define HAL_I2CEx_DigitalFilter_Config        HAL_I2CEx_ConfigDigitalFilter
+#define HAL_FMPI2CEx_AnalogFilter_Config      HAL_FMPI2CEx_ConfigAnalogFilter
+#define HAL_FMPI2CEx_DigitalFilter_Config     HAL_FMPI2CEx_ConfigDigitalFilter
+
+#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
+
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)
+#define HAL_I2C_Master_Sequential_Transmit_IT  HAL_I2C_Master_Seq_Transmit_IT
+#define HAL_I2C_Master_Sequential_Receive_IT   HAL_I2C_Master_Seq_Receive_IT
+#define HAL_I2C_Slave_Sequential_Transmit_IT   HAL_I2C_Slave_Seq_Transmit_IT
+#define HAL_I2C_Slave_Sequential_Receive_IT    HAL_I2C_Slave_Seq_Receive_IT
+#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)
+#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
+#define HAL_I2C_Master_Sequential_Receive_DMA  HAL_I2C_Master_Seq_Receive_DMA
+#define HAL_I2C_Slave_Sequential_Transmit_DMA  HAL_I2C_Slave_Seq_Transmit_DMA
+#define HAL_I2C_Slave_Sequential_Receive_DMA   HAL_I2C_Slave_Seq_Receive_DMA
+#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */
+
+#if defined(STM32F4)
+#define HAL_FMPI2C_Master_Sequential_Transmit_IT  HAL_FMPI2C_Master_Seq_Transmit_IT
+#define HAL_FMPI2C_Master_Sequential_Receive_IT   HAL_FMPI2C_Master_Seq_Receive_IT
+#define HAL_FMPI2C_Slave_Sequential_Transmit_IT   HAL_FMPI2C_Slave_Seq_Transmit_IT
+#define HAL_FMPI2C_Slave_Sequential_Receive_IT    HAL_FMPI2C_Slave_Seq_Receive_IT
+#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA
+#define HAL_FMPI2C_Master_Sequential_Receive_DMA  HAL_FMPI2C_Master_Seq_Receive_DMA
+#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA  HAL_FMPI2C_Slave_Seq_Transmit_DMA
+#define HAL_FMPI2C_Slave_Sequential_Receive_DMA   HAL_FMPI2C_Slave_Seq_Receive_DMA
+#endif /* STM32F4 */
+ /**
+  * @}
+  */
+
+/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
+  * @{
+  */
+
+#if defined(STM32G0)
+#define HAL_PWR_ConfigPVD                             HAL_PWREx_ConfigPVD
+#define HAL_PWR_EnablePVD                             HAL_PWREx_EnablePVD
+#define HAL_PWR_DisablePVD                            HAL_PWREx_DisablePVD
+#define HAL_PWR_PVD_IRQHandler                        HAL_PWREx_PVD_IRQHandler
+#endif
+#define HAL_PWR_PVDConfig                             HAL_PWR_ConfigPVD
+#define HAL_PWR_DisableBkUpReg                        HAL_PWREx_DisableBkUpReg
+#define HAL_PWR_DisableFlashPowerDown                 HAL_PWREx_DisableFlashPowerDown
+#define HAL_PWR_DisableVddio2Monitor                  HAL_PWREx_DisableVddio2Monitor
+#define HAL_PWR_EnableBkUpReg                         HAL_PWREx_EnableBkUpReg
+#define HAL_PWR_EnableFlashPowerDown                  HAL_PWREx_EnableFlashPowerDown
+#define HAL_PWR_EnableVddio2Monitor                   HAL_PWREx_EnableVddio2Monitor
+#define HAL_PWR_PVD_PVM_IRQHandler                    HAL_PWREx_PVD_PVM_IRQHandler
+#define HAL_PWR_PVDLevelConfig                        HAL_PWR_ConfigPVD
+#define HAL_PWR_Vddio2Monitor_IRQHandler              HAL_PWREx_Vddio2Monitor_IRQHandler
+#define HAL_PWR_Vddio2MonitorCallback                 HAL_PWREx_Vddio2MonitorCallback
+#define HAL_PWREx_ActivateOverDrive                   HAL_PWREx_EnableOverDrive
+#define HAL_PWREx_DeactivateOverDrive                 HAL_PWREx_DisableOverDrive
+#define HAL_PWREx_DisableSDADCAnalog                  HAL_PWREx_DisableSDADC
+#define HAL_PWREx_EnableSDADCAnalog                   HAL_PWREx_EnableSDADC
+#define HAL_PWREx_PVMConfig                           HAL_PWREx_ConfigPVM
+
+#define PWR_MODE_NORMAL                               PWR_PVD_MODE_NORMAL
+#define PWR_MODE_IT_RISING                            PWR_PVD_MODE_IT_RISING
+#define PWR_MODE_IT_FALLING                           PWR_PVD_MODE_IT_FALLING
+#define PWR_MODE_IT_RISING_FALLING                    PWR_PVD_MODE_IT_RISING_FALLING
+#define PWR_MODE_EVENT_RISING                         PWR_PVD_MODE_EVENT_RISING
+#define PWR_MODE_EVENT_FALLING                        PWR_PVD_MODE_EVENT_FALLING
+#define PWR_MODE_EVENT_RISING_FALLING                 PWR_PVD_MODE_EVENT_RISING_FALLING
+
+#define CR_OFFSET_BB                                  PWR_CR_OFFSET_BB
+#define CSR_OFFSET_BB                                 PWR_CSR_OFFSET_BB
+#define PMODE_BIT_NUMBER                              VOS_BIT_NUMBER
+#define CR_PMODE_BB                                   CR_VOS_BB
+
+#define DBP_BitNumber                                 DBP_BIT_NUMBER
+#define PVDE_BitNumber                                PVDE_BIT_NUMBER
+#define PMODE_BitNumber                               PMODE_BIT_NUMBER
+#define EWUP_BitNumber                                EWUP_BIT_NUMBER
+#define FPDS_BitNumber                                FPDS_BIT_NUMBER
+#define ODEN_BitNumber                                ODEN_BIT_NUMBER
+#define ODSWEN_BitNumber                              ODSWEN_BIT_NUMBER
+#define MRLVDS_BitNumber                              MRLVDS_BIT_NUMBER
+#define LPLVDS_BitNumber                              LPLVDS_BIT_NUMBER
+#define BRE_BitNumber                                 BRE_BIT_NUMBER
+
+#define PWR_MODE_EVT                                  PWR_PVD_MODE_NORMAL
+
+ /**
+  * @}
+  */
+
+/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_SMBUS_Slave_Listen_IT          HAL_SMBUS_EnableListen_IT
+#define HAL_SMBUS_SlaveAddrCallback        HAL_SMBUS_AddrCallback
+#define HAL_SMBUS_SlaveListenCpltCallback  HAL_SMBUS_ListenCpltCallback
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_SPI_FlushRxFifo                HAL_SPIEx_FlushRxFifo
+/**
+  * @}
+  */
+
+/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_TIM_DMADelayPulseCplt                       TIM_DMADelayPulseCplt
+#define HAL_TIM_DMAError                                TIM_DMAError
+#define HAL_TIM_DMACaptureCplt                          TIM_DMACaptureCplt
+#define HAL_TIMEx_DMACommutationCplt                    TIMEx_DMACommutationCplt
+#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
+#define HAL_TIM_SlaveConfigSynchronization              HAL_TIM_SlaveConfigSynchro
+#define HAL_TIM_SlaveConfigSynchronization_IT           HAL_TIM_SlaveConfigSynchro_IT
+#define HAL_TIMEx_CommutationCallback                   HAL_TIMEx_CommutCallback
+#define HAL_TIMEx_ConfigCommutationEvent                HAL_TIMEx_ConfigCommutEvent
+#define HAL_TIMEx_ConfigCommutationEvent_IT             HAL_TIMEx_ConfigCommutEvent_IT
+#define HAL_TIMEx_ConfigCommutationEvent_DMA            HAL_TIMEx_ConfigCommutEvent_DMA
+#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
+/**
+  * @}
+  */
+
+/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
+#define HAL_LTDC_Relaod           HAL_LTDC_Reload
+#define HAL_LTDC_StructInitFromVideoConfig  HAL_LTDCEx_StructInitFromVideoConfig
+#define HAL_LTDC_StructInitFromAdaptedCommandConfig  HAL_LTDCEx_StructInitFromAdaptedCommandConfig
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros ------------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define AES_IT_CC                      CRYP_IT_CC
+#define AES_IT_ERR                     CRYP_IT_ERR
+#define AES_FLAG_CCF                   CRYP_FLAG_CCF
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_GET_BOOT_MODE                   __HAL_SYSCFG_GET_BOOT_MODE
+#define __HAL_REMAPMEMORY_FLASH               __HAL_SYSCFG_REMAPMEMORY_FLASH
+#define __HAL_REMAPMEMORY_SYSTEMFLASH         __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
+#define __HAL_REMAPMEMORY_SRAM                __HAL_SYSCFG_REMAPMEMORY_SRAM
+#define __HAL_REMAPMEMORY_FMC                 __HAL_SYSCFG_REMAPMEMORY_FMC
+#define __HAL_REMAPMEMORY_FMC_SDRAM           __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
+#define __HAL_REMAPMEMORY_FSMC                __HAL_SYSCFG_REMAPMEMORY_FSMC
+#define __HAL_REMAPMEMORY_QUADSPI             __HAL_SYSCFG_REMAPMEMORY_QUADSPI
+#define __HAL_FMC_BANK                        __HAL_SYSCFG_FMC_BANK
+#define __HAL_GET_FLAG                        __HAL_SYSCFG_GET_FLAG
+#define __HAL_CLEAR_FLAG                      __HAL_SYSCFG_CLEAR_FLAG
+#define __HAL_VREFINT_OUT_ENABLE              __HAL_SYSCFG_VREFINT_OUT_ENABLE
+#define __HAL_VREFINT_OUT_DISABLE             __HAL_SYSCFG_VREFINT_OUT_DISABLE
+#define __HAL_SYSCFG_SRAM2_WRP_ENABLE         __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
+
+#define SYSCFG_FLAG_VREF_READY                SYSCFG_FLAG_VREFINT_READY
+#define SYSCFG_FLAG_RC48                      RCC_FLAG_HSI48
+#define IS_SYSCFG_FASTMODEPLUS_CONFIG         IS_I2C_FASTMODEPLUS
+#define UFB_MODE_BitNumber                    UFB_MODE_BIT_NUMBER
+#define CMP_PD_BitNumber                      CMP_PD_BIT_NUMBER
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __ADC_ENABLE                                     __HAL_ADC_ENABLE
+#define __ADC_DISABLE                                    __HAL_ADC_DISABLE
+#define __HAL_ADC_ENABLING_CONDITIONS                    ADC_ENABLING_CONDITIONS
+#define __HAL_ADC_DISABLING_CONDITIONS                   ADC_DISABLING_CONDITIONS
+#define __HAL_ADC_IS_ENABLED                             ADC_IS_ENABLE
+#define __ADC_IS_ENABLED                                 ADC_IS_ENABLE
+#define __HAL_ADC_IS_SOFTWARE_START_REGULAR              ADC_IS_SOFTWARE_START_REGULAR
+#define __HAL_ADC_IS_SOFTWARE_START_INJECTED             ADC_IS_SOFTWARE_START_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR          ADC_IS_CONVERSION_ONGOING_REGULAR
+#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED         ADC_IS_CONVERSION_ONGOING_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING                  ADC_IS_CONVERSION_ONGOING
+#define __HAL_ADC_CLEAR_ERRORCODE                        ADC_CLEAR_ERRORCODE
+
+#define __HAL_ADC_GET_RESOLUTION                         ADC_GET_RESOLUTION
+#define __HAL_ADC_JSQR_RK                                ADC_JSQR_RK
+#define __HAL_ADC_CFGR_AWD1CH                            ADC_CFGR_AWD1CH_SHIFT
+#define __HAL_ADC_CFGR_AWD23CR                           ADC_CFGR_AWD23CR
+#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION            ADC_CFGR_INJECT_AUTO_CONVERSION
+#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE              ADC_CFGR_INJECT_CONTEXT_QUEUE
+#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS             ADC_CFGR_INJECT_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS                ADC_CFGR_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM                 ADC_CFGR_DISCONTINUOUS_NUM
+#define __HAL_ADC_CFGR_AUTOWAIT                          ADC_CFGR_AUTOWAIT
+#define __HAL_ADC_CFGR_CONTINUOUS                        ADC_CFGR_CONTINUOUS
+#define __HAL_ADC_CFGR_OVERRUN                           ADC_CFGR_OVERRUN
+#define __HAL_ADC_CFGR_DMACONTREQ                        ADC_CFGR_DMACONTREQ
+#define __HAL_ADC_CFGR_EXTSEL                            ADC_CFGR_EXTSEL_SET
+#define __HAL_ADC_JSQR_JEXTSEL                           ADC_JSQR_JEXTSEL_SET
+#define __HAL_ADC_OFR_CHANNEL                            ADC_OFR_CHANNEL
+#define __HAL_ADC_DIFSEL_CHANNEL                         ADC_DIFSEL_CHANNEL
+#define __HAL_ADC_CALFACT_DIFF_SET                       ADC_CALFACT_DIFF_SET
+#define __HAL_ADC_CALFACT_DIFF_GET                       ADC_CALFACT_DIFF_GET
+#define __HAL_ADC_TRX_HIGHTHRESHOLD                      ADC_TRX_HIGHTHRESHOLD
+
+#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION                ADC_OFFSET_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION         ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION        ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_COMMON_REGISTER                        ADC_COMMON_REGISTER
+#define __HAL_ADC_COMMON_CCR_MULTI                       ADC_COMMON_CCR_MULTI
+#define __HAL_ADC_MULTIMODE_IS_ENABLED                   ADC_MULTIMODE_IS_ENABLE
+#define __ADC_MULTIMODE_IS_ENABLED                       ADC_MULTIMODE_IS_ENABLE
+#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER        ADC_NONMULTIMODE_OR_MULTIMODEMASTER
+#define __HAL_ADC_COMMON_ADC_OTHER                       ADC_COMMON_ADC_OTHER
+#define __HAL_ADC_MULTI_SLAVE                            ADC_MULTI_SLAVE
+
+#define __HAL_ADC_SQR1_L                                 ADC_SQR1_L_SHIFT
+#define __HAL_ADC_JSQR_JL                                ADC_JSQR_JL_SHIFT
+#define __HAL_ADC_JSQR_RK_JL                             ADC_JSQR_RK_JL
+#define __HAL_ADC_CR1_DISCONTINUOUS_NUM                  ADC_CR1_DISCONTINUOUS_NUM
+#define __HAL_ADC_CR1_SCAN                               ADC_CR1_SCAN_SET
+#define __HAL_ADC_CONVCYCLES_MAX_RANGE                   ADC_CONVCYCLES_MAX_RANGE
+#define __HAL_ADC_CLOCK_PRESCALER_RANGE                  ADC_CLOCK_PRESCALER_RANGE
+#define __HAL_ADC_GET_CLOCK_PRESCALER                    ADC_GET_CLOCK_PRESCALER
+
+#define __HAL_ADC_SQR1                                   ADC_SQR1
+#define __HAL_ADC_SMPR1                                  ADC_SMPR1
+#define __HAL_ADC_SMPR2                                  ADC_SMPR2
+#define __HAL_ADC_SQR3_RK                                ADC_SQR3_RK
+#define __HAL_ADC_SQR2_RK                                ADC_SQR2_RK
+#define __HAL_ADC_SQR1_RK                                ADC_SQR1_RK
+#define __HAL_ADC_CR2_CONTINUOUS                         ADC_CR2_CONTINUOUS
+#define __HAL_ADC_CR1_DISCONTINUOUS                      ADC_CR1_DISCONTINUOUS
+#define __HAL_ADC_CR1_SCANCONV                           ADC_CR1_SCANCONV
+#define __HAL_ADC_CR2_EOCSelection                       ADC_CR2_EOCSelection
+#define __HAL_ADC_CR2_DMAContReq                         ADC_CR2_DMAContReq
+#define __HAL_ADC_JSQR                                   ADC_JSQR
+
+#define __HAL_ADC_CHSELR_CHANNEL                         ADC_CHSELR_CHANNEL
+#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS               ADC_CFGR1_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR1_AUTOOFF                          ADC_CFGR1_AUTOOFF
+#define __HAL_ADC_CFGR1_AUTOWAIT                         ADC_CFGR1_AUTOWAIT
+#define __HAL_ADC_CFGR1_CONTINUOUS                       ADC_CFGR1_CONTINUOUS
+#define __HAL_ADC_CFGR1_OVERRUN                          ADC_CFGR1_OVERRUN
+#define __HAL_ADC_CFGR1_SCANDIR                          ADC_CFGR1_SCANDIR
+#define __HAL_ADC_CFGR1_DMACONTREQ                       ADC_CFGR1_DMACONTREQ
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_DHR12R1_ALIGNEMENT                        DAC_DHR12R1_ALIGNMENT
+#define __HAL_DHR12R2_ALIGNEMENT                        DAC_DHR12R2_ALIGNMENT
+#define __HAL_DHR12RD_ALIGNEMENT                        DAC_DHR12RD_ALIGNMENT
+#define IS_DAC_GENERATE_WAVE                            IS_DAC_WAVE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
+#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
+#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
+#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
+#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
+#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
+#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
+#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
+#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
+#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
+#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
+#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
+#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
+#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
+#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
+#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
+
+#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
+#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
+#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
+#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
+#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
+#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
+#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
+#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
+#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
+#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
+#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
+#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
+#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
+#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
+
+
+#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
+#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
+#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
+#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
+#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
+#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
+#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
+#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
+#if defined(STM32H7)
+  #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
+  #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
+  #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
+  #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
+#else
+  #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
+  #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
+  #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
+  #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
+#endif /* STM32H7 */
+#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
+#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
+#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
+#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
+#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
+#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
+#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
+#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
+#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
+#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
+#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
+#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#if defined(STM32F3)
+#define COMP_START                                       __HAL_COMP_ENABLE
+#define COMP_STOP                                        __HAL_COMP_DISABLE
+#define COMP_LOCK                                        __HAL_COMP_LOCK
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F302xE) || defined(STM32F302xC)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP7_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP7_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP7_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F373xC) ||defined(STM32F378xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+# endif
+#else
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+#endif
+
+#define __HAL_COMP_GET_EXTI_LINE  COMP_GET_EXTI_LINE
+
+#if defined(STM32L0) || defined(STM32L4)
+/* Note: On these STM32 families, the only argument of this macro             */
+/*       is COMP_FLAG_LOCK.                                                   */
+/*       This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle  */
+/*       argument.                                                            */
+#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__)  (__HAL_COMP_IS_LOCKED(__HANDLE__))
+#endif
+/**
+  * @}
+  */
+
+#if defined(STM32L0) || defined(STM32L4)
+/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_COMP_Start_IT       HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
+#define HAL_COMP_Stop_IT        HAL_COMP_Stop  /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
+/**
+  * @}
+  */
+#endif
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
+                          ((WAVE) == DAC_WAVE_NOISE)|| \
+                          ((WAVE) == DAC_WAVE_TRIANGLE))
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define IS_WRPAREA          IS_OB_WRPAREA
+#define IS_TYPEPROGRAM      IS_FLASH_TYPEPROGRAM
+#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
+#define IS_TYPEERASE        IS_FLASH_TYPEERASE
+#define IS_NBSECTORS        IS_FLASH_NBSECTORS
+#define IS_OB_WDG_SOURCE    IS_OB_IWDG_SOURCE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_I2C_RESET_CR2             I2C_RESET_CR2
+#define __HAL_I2C_GENERATE_START        I2C_GENERATE_START
+#if defined(STM32F1)
+#define __HAL_I2C_FREQ_RANGE            I2C_FREQRANGE
+#else
+#define __HAL_I2C_FREQ_RANGE            I2C_FREQ_RANGE
+#endif /* STM32F1 */
+#define __HAL_I2C_RISE_TIME             I2C_RISE_TIME
+#define __HAL_I2C_SPEED_STANDARD        I2C_SPEED_STANDARD
+#define __HAL_I2C_SPEED_FAST            I2C_SPEED_FAST
+#define __HAL_I2C_SPEED                 I2C_SPEED
+#define __HAL_I2C_7BIT_ADD_WRITE        I2C_7BIT_ADD_WRITE
+#define __HAL_I2C_7BIT_ADD_READ         I2C_7BIT_ADD_READ
+#define __HAL_I2C_10BIT_ADDRESS         I2C_10BIT_ADDRESS
+#define __HAL_I2C_10BIT_HEADER_WRITE    I2C_10BIT_HEADER_WRITE
+#define __HAL_I2C_10BIT_HEADER_READ     I2C_10BIT_HEADER_READ
+#define __HAL_I2C_MEM_ADD_MSB           I2C_MEM_ADD_MSB
+#define __HAL_I2C_MEM_ADD_LSB           I2C_MEM_ADD_LSB
+#define __HAL_I2C_FREQRANGE             I2C_FREQRANGE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define IS_I2S_INSTANCE                 IS_I2S_ALL_INSTANCE
+#define IS_I2S_INSTANCE_EXT             IS_I2S_ALL_INSTANCE_EXT
+
+#if defined(STM32H7)
+  #define __HAL_I2S_CLEAR_FREFLAG       __HAL_I2S_CLEAR_TIFREFLAG
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __IRDA_DISABLE                  __HAL_IRDA_DISABLE
+#define __IRDA_ENABLE                   __HAL_IRDA_ENABLE
+
+#define __HAL_IRDA_GETCLOCKSOURCE       IRDA_GETCLOCKSOURCE
+#define __HAL_IRDA_MASK_COMPUTATION     IRDA_MASK_COMPUTATION
+#define __IRDA_GETCLOCKSOURCE           IRDA_GETCLOCKSOURCE
+#define __IRDA_MASK_COMPUTATION         IRDA_MASK_COMPUTATION
+
+#define IS_IRDA_ONEBIT_SAMPLE           IS_IRDA_ONE_BIT_SAMPLE
+
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_IWDG_ENABLE_WRITE_ACCESS  IWDG_ENABLE_WRITE_ACCESS
+#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_LPTIM_ENABLE_INTERRUPT    __HAL_LPTIM_ENABLE_IT
+#define __HAL_LPTIM_DISABLE_INTERRUPT   __HAL_LPTIM_DISABLE_IT
+#define __HAL_LPTIM_GET_ITSTATUS        __HAL_LPTIM_GET_IT_SOURCE
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __OPAMP_CSR_OPAXPD                OPAMP_CSR_OPAXPD
+#define __OPAMP_CSR_S3SELX                OPAMP_CSR_S3SELX
+#define __OPAMP_CSR_S4SELX                OPAMP_CSR_S4SELX
+#define __OPAMP_CSR_S5SELX                OPAMP_CSR_S5SELX
+#define __OPAMP_CSR_S6SELX                OPAMP_CSR_S6SELX
+#define __OPAMP_CSR_OPAXCAL_L             OPAMP_CSR_OPAXCAL_L
+#define __OPAMP_CSR_OPAXCAL_H             OPAMP_CSR_OPAXCAL_H
+#define __OPAMP_CSR_OPAXLPM               OPAMP_CSR_OPAXLPM
+#define __OPAMP_CSR_ALL_SWITCHES          OPAMP_CSR_ALL_SWITCHES
+#define __OPAMP_CSR_ANAWSELX              OPAMP_CSR_ANAWSELX
+#define __OPAMP_CSR_OPAXCALOUT            OPAMP_CSR_OPAXCALOUT
+#define __OPAMP_OFFSET_TRIM_BITSPOSITION  OPAMP_OFFSET_TRIM_BITSPOSITION
+#define __OPAMP_OFFSET_TRIM_SET           OPAMP_OFFSET_TRIM_SET
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_PVD_EVENT_DISABLE                                  __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PVD_EVENT_ENABLE                                   __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PVM_EVENT_DISABLE                                  __HAL_PWR_PVM_EVENT_DISABLE
+#define __HAL_PVM_EVENT_ENABLE                                   __HAL_PWR_PVM_EVENT_ENABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
+#define __HAL_PWR_INTERNALWAKEUP_DISABLE                         HAL_PWREx_DisableInternalWakeUpLine
+#define __HAL_PWR_INTERNALWAKEUP_ENABLE                          HAL_PWREx_EnableInternalWakeUpLine
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE                    HAL_PWREx_DisablePullUpPullDownConfig
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE                     HAL_PWREx_EnablePullUpPullDownConfig
+#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER()                  do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
+#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE                         __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE                          __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE                __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE                 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE                 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE                  __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER              __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER               __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVM_DISABLE()                                  do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
+#define __HAL_PWR_PVM_ENABLE()                                   do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE                  HAL_PWREx_DisableSRAM2ContentRetention
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE                   HAL_PWREx_EnableSRAM2ContentRetention
+#define __HAL_PWR_VDDIO2_DISABLE                                 HAL_PWREx_DisableVddIO2
+#define __HAL_PWR_VDDIO2_ENABLE                                  HAL_PWREx_EnableVddIO2
+#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER                 __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER           __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_VDDUSB_DISABLE                                 HAL_PWREx_DisableVddUSB
+#define __HAL_PWR_VDDUSB_ENABLE                                  HAL_PWREx_EnableVddUSB
+
+#if defined (STM32F4)
+#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD)         __HAL_PWR_PVD_EXTI_ENABLE_IT()
+#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_DISABLE_IT()
+#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD)          __HAL_PWR_PVD_EXTI_GET_FLAG()
+#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
+#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD)     __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
+#else
+#define __HAL_PVD_EXTI_CLEAR_FLAG                                __HAL_PWR_PVD_EXTI_CLEAR_FLAG
+#define __HAL_PVD_EXTI_DISABLE_IT                                __HAL_PWR_PVD_EXTI_DISABLE_IT
+#define __HAL_PVD_EXTI_ENABLE_IT                                 __HAL_PWR_PVD_EXTI_ENABLE_IT
+#define __HAL_PVD_EXTI_GENERATE_SWIT                             __HAL_PWR_PVD_EXTI_GENERATE_SWIT
+#define __HAL_PVD_EXTI_GET_FLAG                                  __HAL_PWR_PVD_EXTI_GET_FLAG
+#endif /* STM32F4 */
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
+  * @{
+  */
+
+#define RCC_StopWakeUpClock_MSI     RCC_STOP_WAKEUPCLOCK_MSI
+#define RCC_StopWakeUpClock_HSI     RCC_STOP_WAKEUPCLOCK_HSI
+
+#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
+#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
+
+#define __ADC_CLK_DISABLE          __HAL_RCC_ADC_CLK_DISABLE
+#define __ADC_CLK_ENABLE           __HAL_RCC_ADC_CLK_ENABLE
+#define __ADC_CLK_SLEEP_DISABLE    __HAL_RCC_ADC_CLK_SLEEP_DISABLE
+#define __ADC_CLK_SLEEP_ENABLE     __HAL_RCC_ADC_CLK_SLEEP_ENABLE
+#define __ADC_FORCE_RESET          __HAL_RCC_ADC_FORCE_RESET
+#define __ADC_RELEASE_RESET        __HAL_RCC_ADC_RELEASE_RESET
+#define __ADC1_CLK_DISABLE         __HAL_RCC_ADC1_CLK_DISABLE
+#define __ADC1_CLK_ENABLE          __HAL_RCC_ADC1_CLK_ENABLE
+#define __ADC1_FORCE_RESET         __HAL_RCC_ADC1_FORCE_RESET
+#define __ADC1_RELEASE_RESET       __HAL_RCC_ADC1_RELEASE_RESET
+#define __ADC1_CLK_SLEEP_ENABLE    __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
+#define __ADC1_CLK_SLEEP_DISABLE   __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_DISABLE         __HAL_RCC_ADC2_CLK_DISABLE
+#define __ADC2_CLK_ENABLE          __HAL_RCC_ADC2_CLK_ENABLE
+#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
+#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
+#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
+#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
+#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
+#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
+#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
+#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
+#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
+#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
+#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
+#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
+#define __CRYP_CLK_SLEEP_ENABLE      __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
+#define __CRYP_CLK_SLEEP_DISABLE  __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
+#define __CRYP_CLK_ENABLE  __HAL_RCC_CRYP_CLK_ENABLE
+#define __CRYP_CLK_DISABLE  __HAL_RCC_CRYP_CLK_DISABLE
+#define __CRYP_FORCE_RESET       __HAL_RCC_CRYP_FORCE_RESET
+#define __CRYP_RELEASE_RESET  __HAL_RCC_CRYP_RELEASE_RESET
+#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
+#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
+#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
+#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
+#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
+#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
+#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
+#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
+#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
+#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
+#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
+#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
+#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
+#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
+#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
+#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
+#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
+#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
+#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
+#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
+#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
+#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
+#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN_CLK_DISABLE         __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN_CLK_ENABLE          __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN_FORCE_RESET         __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN_RELEASE_RESET       __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
+#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
+#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
+#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
+#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
+#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
+#define __COMP_CLK_DISABLE        __HAL_RCC_COMP_CLK_DISABLE
+#define __COMP_CLK_ENABLE         __HAL_RCC_COMP_CLK_ENABLE
+#define __COMP_FORCE_RESET        __HAL_RCC_COMP_FORCE_RESET
+#define __COMP_RELEASE_RESET      __HAL_RCC_COMP_RELEASE_RESET
+#define __COMP_CLK_SLEEP_ENABLE   __HAL_RCC_COMP_CLK_SLEEP_ENABLE
+#define __COMP_CLK_SLEEP_DISABLE  __HAL_RCC_COMP_CLK_SLEEP_DISABLE
+#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
+#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
+#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
+#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
+#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
+#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
+#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
+#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
+#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
+#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
+#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
+#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
+#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
+#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
+#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
+#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
+#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
+#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
+#define __DBGMCU_CLK_ENABLE     __HAL_RCC_DBGMCU_CLK_ENABLE
+#define __DBGMCU_CLK_DISABLE     __HAL_RCC_DBGMCU_CLK_DISABLE
+#define __DBGMCU_FORCE_RESET    __HAL_RCC_DBGMCU_FORCE_RESET
+#define __DBGMCU_RELEASE_RESET  __HAL_RCC_DBGMCU_RELEASE_RESET
+#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
+#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
+#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
+#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
+#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
+#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
+#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
+#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
+#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
+#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
+#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
+#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
+#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
+#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
+#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
+#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
+#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
+#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
+#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
+#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
+#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
+#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
+#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
+#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
+#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
+#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
+#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
+#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
+#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
+#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
+#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
+#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
+#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
+#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
+#define __FLITF_CLK_DISABLE       __HAL_RCC_FLITF_CLK_DISABLE
+#define __FLITF_CLK_ENABLE        __HAL_RCC_FLITF_CLK_ENABLE
+#define __FLITF_FORCE_RESET       __HAL_RCC_FLITF_FORCE_RESET
+#define __FLITF_RELEASE_RESET     __HAL_RCC_FLITF_RELEASE_RESET
+#define __FLITF_CLK_SLEEP_ENABLE  __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
+#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
+#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
+#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
+#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
+#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
+#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
+#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
+#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
+#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
+#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
+#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
+#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
+#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
+#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
+#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
+#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
+#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
+#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
+#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
+#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
+#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
+#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
+#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
+#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
+#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
+#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
+#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
+#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
+#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
+#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
+#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
+#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
+#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
+#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
+#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
+#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
+#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
+#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
+#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
+#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
+#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
+#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
+#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
+#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
+#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
+#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
+#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
+#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
+#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
+#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
+#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
+#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
+#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
+#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
+#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
+#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
+#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
+#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
+#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
+#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
+#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
+#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
+#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
+#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
+#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
+#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
+#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
+#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
+#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
+#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
+#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
+#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
+#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
+#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
+#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
+#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
+#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
+#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
+#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
+#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
+#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
+#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
+#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
+#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
+#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
+#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
+#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
+#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
+#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
+#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
+#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
+#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
+#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
+#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
+#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
+#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
+#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
+#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
+#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
+#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
+#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
+#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
+#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
+#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
+#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
+#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
+#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
+#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
+#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
+#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
+#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
+#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
+#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
+#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
+#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
+#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
+#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
+#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
+#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
+#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
+#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
+#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
+#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
+
+#if defined(STM32WB)
+#define __HAL_RCC_QSPI_CLK_DISABLE            __HAL_RCC_QUADSPI_CLK_DISABLE
+#define __HAL_RCC_QSPI_CLK_ENABLE             __HAL_RCC_QUADSPI_CLK_ENABLE
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE      __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE       __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_QSPI_FORCE_RESET            __HAL_RCC_QUADSPI_FORCE_RESET
+#define __HAL_RCC_QSPI_RELEASE_RESET          __HAL_RCC_QUADSPI_RELEASE_RESET
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED         __HAL_RCC_QUADSPI_IS_CLK_ENABLED
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED        __HAL_RCC_QUADSPI_IS_CLK_DISABLED
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED   __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED  __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED
+#define QSPI_IRQHandler QUADSPI_IRQHandler
+#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */
+
+#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
+#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
+#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
+#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
+#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
+#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
+#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
+#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
+#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
+#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
+#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
+#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
+#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
+#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
+#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
+#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
+#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
+#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
+#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
+#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
+#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
+#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
+#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
+#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
+#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
+#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
+#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
+#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
+#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
+#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
+#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
+#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
+#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
+#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
+#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
+#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
+#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
+#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
+#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
+#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
+#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
+#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
+#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
+#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
+#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
+#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
+#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
+#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
+#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
+#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
+#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
+#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
+#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
+#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
+#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
+#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
+#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
+#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
+#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
+#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
+#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
+#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
+#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
+#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
+#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
+#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
+#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
+#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
+#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
+#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
+#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
+#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
+#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
+#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
+#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
+#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
+#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
+#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
+#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
+#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
+#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
+#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
+#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
+#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
+#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
+#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
+#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
+#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
+#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
+#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
+#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
+#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
+#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
+#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
+#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
+#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
+#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
+#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
+#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
+#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
+#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
+#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
+#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
+#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
+#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
+#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
+#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
+#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
+#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
+#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
+#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
+#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
+#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
+#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
+#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
+#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
+#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
+#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
+#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
+#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
+#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
+#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
+#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
+#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
+#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
+#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
+#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
+#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
+#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
+#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
+#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
+#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
+#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
+#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
+#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
+#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
+#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
+#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
+#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
+#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
+#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
+#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
+#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
+#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
+#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
+#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
+#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
+#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
+#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
+#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
+#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
+#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
+#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
+#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
+#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
+#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
+#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
+#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
+#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
+#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
+#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
+#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
+#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
+#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
+#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
+#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
+#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
+#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
+#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
+#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
+#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
+#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
+#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
+#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
+#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
+#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
+#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
+#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
+#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
+#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
+#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
+#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
+#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
+#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
+#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
+#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
+#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
+#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
+#define __USART4_CLK_DISABLE        __HAL_RCC_UART4_CLK_DISABLE
+#define __USART4_CLK_ENABLE         __HAL_RCC_UART4_CLK_ENABLE
+#define __USART4_CLK_SLEEP_ENABLE   __HAL_RCC_UART4_CLK_SLEEP_ENABLE
+#define __USART4_CLK_SLEEP_DISABLE  __HAL_RCC_UART4_CLK_SLEEP_DISABLE
+#define __USART4_FORCE_RESET        __HAL_RCC_UART4_FORCE_RESET
+#define __USART4_RELEASE_RESET      __HAL_RCC_UART4_RELEASE_RESET
+#define __USART5_CLK_DISABLE        __HAL_RCC_UART5_CLK_DISABLE
+#define __USART5_CLK_ENABLE         __HAL_RCC_UART5_CLK_ENABLE
+#define __USART5_CLK_SLEEP_ENABLE   __HAL_RCC_UART5_CLK_SLEEP_ENABLE
+#define __USART5_CLK_SLEEP_DISABLE  __HAL_RCC_UART5_CLK_SLEEP_DISABLE
+#define __USART5_FORCE_RESET        __HAL_RCC_UART5_FORCE_RESET
+#define __USART5_RELEASE_RESET      __HAL_RCC_UART5_RELEASE_RESET
+#define __USART7_CLK_DISABLE        __HAL_RCC_UART7_CLK_DISABLE
+#define __USART7_CLK_ENABLE         __HAL_RCC_UART7_CLK_ENABLE
+#define __USART7_FORCE_RESET        __HAL_RCC_UART7_FORCE_RESET
+#define __USART7_RELEASE_RESET      __HAL_RCC_UART7_RELEASE_RESET
+#define __USART8_CLK_DISABLE        __HAL_RCC_UART8_CLK_DISABLE
+#define __USART8_CLK_ENABLE         __HAL_RCC_UART8_CLK_ENABLE
+#define __USART8_FORCE_RESET        __HAL_RCC_UART8_FORCE_RESET
+#define __USART8_RELEASE_RESET      __HAL_RCC_UART8_RELEASE_RESET
+#define __USB_CLK_DISABLE         __HAL_RCC_USB_CLK_DISABLE
+#define __USB_CLK_ENABLE          __HAL_RCC_USB_CLK_ENABLE
+#define __USB_FORCE_RESET         __HAL_RCC_USB_FORCE_RESET
+#define __USB_CLK_SLEEP_ENABLE    __HAL_RCC_USB_CLK_SLEEP_ENABLE
+#define __USB_CLK_SLEEP_DISABLE   __HAL_RCC_USB_CLK_SLEEP_DISABLE
+#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
+#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
+#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
+
+#if defined(STM32H7)
+#define __HAL_RCC_WWDG_CLK_DISABLE   __HAL_RCC_WWDG1_CLK_DISABLE
+#define __HAL_RCC_WWDG_CLK_ENABLE   __HAL_RCC_WWDG1_CLK_ENABLE
+#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE  __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE  __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE
+
+#define __HAL_RCC_WWDG_FORCE_RESET    ((void)0U)  /* Not available on the STM32H7*/
+#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/
+
+
+#define  __HAL_RCC_WWDG_IS_CLK_ENABLED    __HAL_RCC_WWDG1_IS_CLK_ENABLED
+#define  __HAL_RCC_WWDG_IS_CLK_DISABLED  __HAL_RCC_WWDG1_IS_CLK_DISABLED
+#endif
+
+#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
+#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
+#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
+#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
+#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
+#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
+
+#define __TIM21_CLK_ENABLE   __HAL_RCC_TIM21_CLK_ENABLE
+#define __TIM21_CLK_DISABLE   __HAL_RCC_TIM21_CLK_DISABLE
+#define __TIM21_FORCE_RESET   __HAL_RCC_TIM21_FORCE_RESET
+#define __TIM21_RELEASE_RESET  __HAL_RCC_TIM21_RELEASE_RESET
+#define __TIM21_CLK_SLEEP_ENABLE   __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
+#define __TIM21_CLK_SLEEP_DISABLE   __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
+#define __TIM22_CLK_ENABLE   __HAL_RCC_TIM22_CLK_ENABLE
+#define __TIM22_CLK_DISABLE   __HAL_RCC_TIM22_CLK_DISABLE
+#define __TIM22_FORCE_RESET   __HAL_RCC_TIM22_FORCE_RESET
+#define __TIM22_RELEASE_RESET  __HAL_RCC_TIM22_RELEASE_RESET
+#define __TIM22_CLK_SLEEP_ENABLE   __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
+#define __TIM22_CLK_SLEEP_DISABLE   __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
+#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
+#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
+#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
+#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
+#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
+#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
+#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
+#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
+
+#define __USB_OTG_FS_FORCE_RESET  __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __USB_OTG_FS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+#define __USB_OTG_FS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
+#define __USB_OTG_FS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
+#define __USB_OTG_HS_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_DISABLE
+#define __USB_OTG_HS_CLK_ENABLE          __HAL_RCC_USB_OTG_HS_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
+#define __TIM9_CLK_SLEEP_ENABLE          __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
+#define __TIM9_CLK_SLEEP_DISABLE  __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
+#define __TIM10_CLK_SLEEP_ENABLE  __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
+#define __TIM10_CLK_SLEEP_DISABLE  __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
+#define __TIM11_CLK_SLEEP_ENABLE  __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
+#define __TIM11_CLK_SLEEP_DISABLE  __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
+#define __ETHMACPTP_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
+#define __ETHMACPTP_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
+#define __ETHMACPTP_CLK_ENABLE          __HAL_RCC_ETHMACPTP_CLK_ENABLE
+#define __ETHMACPTP_CLK_DISABLE          __HAL_RCC_ETHMACPTP_CLK_DISABLE
+#define __HASH_CLK_ENABLE          __HAL_RCC_HASH_CLK_ENABLE
+#define __HASH_FORCE_RESET          __HAL_RCC_HASH_FORCE_RESET
+#define __HASH_RELEASE_RESET          __HAL_RCC_HASH_RELEASE_RESET
+#define __HASH_CLK_SLEEP_ENABLE          __HAL_RCC_HASH_CLK_SLEEP_ENABLE
+#define __HASH_CLK_SLEEP_DISABLE  __HAL_RCC_HASH_CLK_SLEEP_DISABLE
+#define __HASH_CLK_DISABLE            __HAL_RCC_HASH_CLK_DISABLE
+#define __SPI5_CLK_ENABLE          __HAL_RCC_SPI5_CLK_ENABLE
+#define __SPI5_CLK_DISABLE              __HAL_RCC_SPI5_CLK_DISABLE
+#define __SPI5_FORCE_RESET          __HAL_RCC_SPI5_FORCE_RESET
+#define __SPI5_RELEASE_RESET          __HAL_RCC_SPI5_RELEASE_RESET
+#define __SPI5_CLK_SLEEP_ENABLE          __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
+#define __SPI5_CLK_SLEEP_DISABLE  __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
+#define __SPI6_CLK_ENABLE          __HAL_RCC_SPI6_CLK_ENABLE
+#define __SPI6_CLK_DISABLE          __HAL_RCC_SPI6_CLK_DISABLE
+#define __SPI6_FORCE_RESET          __HAL_RCC_SPI6_FORCE_RESET
+#define __SPI6_RELEASE_RESET         __HAL_RCC_SPI6_RELEASE_RESET
+#define __SPI6_CLK_SLEEP_ENABLE          __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
+#define __SPI6_CLK_SLEEP_DISABLE  __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
+#define __LTDC_CLK_ENABLE          __HAL_RCC_LTDC_CLK_ENABLE
+#define __LTDC_CLK_DISABLE          __HAL_RCC_LTDC_CLK_DISABLE
+#define __LTDC_FORCE_RESET          __HAL_RCC_LTDC_FORCE_RESET
+#define __LTDC_RELEASE_RESET          __HAL_RCC_LTDC_RELEASE_RESET
+#define __LTDC_CLK_SLEEP_ENABLE          __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
+#define __ETHMAC_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
+#define __ETHMAC_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
+#define __ETHMACTX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
+#define __ETHMACTX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
+#define __ETHMACRX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
+#define __ETHMACRX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
+#define __TIM12_CLK_SLEEP_ENABLE  __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
+#define __TIM12_CLK_SLEEP_DISABLE  __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
+#define __TIM13_CLK_SLEEP_ENABLE  __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
+#define __TIM13_CLK_SLEEP_DISABLE  __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
+#define __TIM14_CLK_SLEEP_ENABLE  __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
+#define __TIM14_CLK_SLEEP_DISABLE  __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
+#define __BKPSRAM_CLK_ENABLE          __HAL_RCC_BKPSRAM_CLK_ENABLE
+#define __BKPSRAM_CLK_DISABLE          __HAL_RCC_BKPSRAM_CLK_DISABLE
+#define __BKPSRAM_CLK_SLEEP_ENABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
+#define __BKPSRAM_CLK_SLEEP_DISABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
+#define __CCMDATARAMEN_CLK_ENABLE  __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
+#define __CCMDATARAMEN_CLK_DISABLE  __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
+#define __USART6_CLK_ENABLE          __HAL_RCC_USART6_CLK_ENABLE
+#define __USART6_CLK_DISABLE          __HAL_RCC_USART6_CLK_DISABLE
+#define __USART6_FORCE_RESET        __HAL_RCC_USART6_FORCE_RESET
+#define __USART6_RELEASE_RESET        __HAL_RCC_USART6_RELEASE_RESET
+#define __USART6_CLK_SLEEP_ENABLE  __HAL_RCC_USART6_CLK_SLEEP_ENABLE
+#define __USART6_CLK_SLEEP_DISABLE  __HAL_RCC_USART6_CLK_SLEEP_DISABLE
+#define __SPI4_CLK_ENABLE          __HAL_RCC_SPI4_CLK_ENABLE
+#define __SPI4_CLK_DISABLE          __HAL_RCC_SPI4_CLK_DISABLE
+#define __SPI4_FORCE_RESET          __HAL_RCC_SPI4_FORCE_RESET
+#define __SPI4_RELEASE_RESET        __HAL_RCC_SPI4_RELEASE_RESET
+#define __SPI4_CLK_SLEEP_ENABLE   __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
+#define __SPI4_CLK_SLEEP_DISABLE  __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
+#define __GPIOI_CLK_ENABLE          __HAL_RCC_GPIOI_CLK_ENABLE
+#define __GPIOI_CLK_DISABLE          __HAL_RCC_GPIOI_CLK_DISABLE
+#define __GPIOI_FORCE_RESET          __HAL_RCC_GPIOI_FORCE_RESET
+#define __GPIOI_RELEASE_RESET          __HAL_RCC_GPIOI_RELEASE_RESET
+#define __GPIOI_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
+#define __GPIOI_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
+#define __GPIOJ_CLK_ENABLE          __HAL_RCC_GPIOJ_CLK_ENABLE
+#define __GPIOJ_CLK_DISABLE          __HAL_RCC_GPIOJ_CLK_DISABLE
+#define __GPIOJ_FORCE_RESET         __HAL_RCC_GPIOJ_FORCE_RESET
+#define __GPIOJ_RELEASE_RESET          __HAL_RCC_GPIOJ_RELEASE_RESET
+#define __GPIOJ_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
+#define __GPIOJ_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
+#define __GPIOK_CLK_ENABLE          __HAL_RCC_GPIOK_CLK_ENABLE
+#define __GPIOK_CLK_DISABLE          __HAL_RCC_GPIOK_CLK_DISABLE
+#define __GPIOK_RELEASE_RESET          __HAL_RCC_GPIOK_RELEASE_RESET
+#define __GPIOK_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
+#define __GPIOK_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
+#define __ETH_CLK_ENABLE          __HAL_RCC_ETH_CLK_ENABLE
+#define __ETH_CLK_DISABLE          __HAL_RCC_ETH_CLK_DISABLE
+#define __DCMI_CLK_ENABLE          __HAL_RCC_DCMI_CLK_ENABLE
+#define __DCMI_CLK_DISABLE          __HAL_RCC_DCMI_CLK_DISABLE
+#define __DCMI_FORCE_RESET          __HAL_RCC_DCMI_FORCE_RESET
+#define __DCMI_RELEASE_RESET          __HAL_RCC_DCMI_RELEASE_RESET
+#define __DCMI_CLK_SLEEP_ENABLE   __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
+#define __DCMI_CLK_SLEEP_DISABLE  __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
+#define __UART7_CLK_ENABLE          __HAL_RCC_UART7_CLK_ENABLE
+#define __UART7_CLK_DISABLE          __HAL_RCC_UART7_CLK_DISABLE
+#define __UART7_RELEASE_RESET       __HAL_RCC_UART7_RELEASE_RESET
+#define __UART7_FORCE_RESET       __HAL_RCC_UART7_FORCE_RESET
+#define __UART7_CLK_SLEEP_ENABLE  __HAL_RCC_UART7_CLK_SLEEP_ENABLE
+#define __UART7_CLK_SLEEP_DISABLE  __HAL_RCC_UART7_CLK_SLEEP_DISABLE
+#define __UART8_CLK_ENABLE          __HAL_RCC_UART8_CLK_ENABLE
+#define __UART8_CLK_DISABLE          __HAL_RCC_UART8_CLK_DISABLE
+#define __UART8_FORCE_RESET          __HAL_RCC_UART8_FORCE_RESET
+#define __UART8_RELEASE_RESET          __HAL_RCC_UART8_RELEASE_RESET
+#define __UART8_CLK_SLEEP_ENABLE  __HAL_RCC_UART8_CLK_SLEEP_ENABLE
+#define __UART8_CLK_SLEEP_DISABLE  __HAL_RCC_UART8_CLK_SLEEP_DISABLE
+#define __OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __OTGHSULPI_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __OTGHSULPI_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
+#define __HAL_RCC_OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __HAL_RCC_OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE      __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE     __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED  __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
+#define __SRAM3_CLK_SLEEP_ENABLE       __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_ENABLE        __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_DISABLE       __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
+#define __DAC_CLK_SLEEP_ENABLE         __HAL_RCC_DAC_CLK_SLEEP_ENABLE
+#define __DAC_CLK_SLEEP_DISABLE        __HAL_RCC_DAC_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_SLEEP_ENABLE        __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
+#define __ADC2_CLK_SLEEP_DISABLE       __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
+#define __ADC3_CLK_SLEEP_ENABLE        __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
+#define __ADC3_CLK_SLEEP_DISABLE       __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
+#define __FSMC_FORCE_RESET             __HAL_RCC_FSMC_FORCE_RESET
+#define __FSMC_RELEASE_RESET           __HAL_RCC_FSMC_RELEASE_RESET
+#define __FSMC_CLK_SLEEP_ENABLE        __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
+#define __FSMC_CLK_SLEEP_DISABLE       __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
+#define __SDIO_FORCE_RESET             __HAL_RCC_SDIO_FORCE_RESET
+#define __SDIO_RELEASE_RESET           __HAL_RCC_SDIO_RELEASE_RESET
+#define __SDIO_CLK_SLEEP_DISABLE       __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __SDIO_CLK_SLEEP_ENABLE        __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_ENABLE             __HAL_RCC_DMA2D_CLK_ENABLE
+#define __DMA2D_CLK_DISABLE            __HAL_RCC_DMA2D_CLK_DISABLE
+#define __DMA2D_FORCE_RESET            __HAL_RCC_DMA2D_FORCE_RESET
+#define __DMA2D_RELEASE_RESET          __HAL_RCC_DMA2D_RELEASE_RESET
+#define __DMA2D_CLK_SLEEP_ENABLE       __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_SLEEP_DISABLE      __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
+
+/* alias define maintained for legacy */
+#define __HAL_RCC_OTGFS_FORCE_RESET    __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __HAL_RCC_OTGFS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+
+#define __ADC12_CLK_ENABLE          __HAL_RCC_ADC12_CLK_ENABLE
+#define __ADC12_CLK_DISABLE         __HAL_RCC_ADC12_CLK_DISABLE
+#define __ADC34_CLK_ENABLE          __HAL_RCC_ADC34_CLK_ENABLE
+#define __ADC34_CLK_DISABLE         __HAL_RCC_ADC34_CLK_DISABLE
+#define __DAC2_CLK_ENABLE           __HAL_RCC_DAC2_CLK_ENABLE
+#define __DAC2_CLK_DISABLE          __HAL_RCC_DAC2_CLK_DISABLE
+#define __TIM18_CLK_ENABLE          __HAL_RCC_TIM18_CLK_ENABLE
+#define __TIM18_CLK_DISABLE         __HAL_RCC_TIM18_CLK_DISABLE
+#define __TIM19_CLK_ENABLE          __HAL_RCC_TIM19_CLK_ENABLE
+#define __TIM19_CLK_DISABLE         __HAL_RCC_TIM19_CLK_DISABLE
+#define __TIM20_CLK_ENABLE          __HAL_RCC_TIM20_CLK_ENABLE
+#define __TIM20_CLK_DISABLE         __HAL_RCC_TIM20_CLK_DISABLE
+#define __HRTIM1_CLK_ENABLE         __HAL_RCC_HRTIM1_CLK_ENABLE
+#define __HRTIM1_CLK_DISABLE        __HAL_RCC_HRTIM1_CLK_DISABLE
+#define __SDADC1_CLK_ENABLE         __HAL_RCC_SDADC1_CLK_ENABLE
+#define __SDADC2_CLK_ENABLE         __HAL_RCC_SDADC2_CLK_ENABLE
+#define __SDADC3_CLK_ENABLE         __HAL_RCC_SDADC3_CLK_ENABLE
+#define __SDADC1_CLK_DISABLE        __HAL_RCC_SDADC1_CLK_DISABLE
+#define __SDADC2_CLK_DISABLE        __HAL_RCC_SDADC2_CLK_DISABLE
+#define __SDADC3_CLK_DISABLE        __HAL_RCC_SDADC3_CLK_DISABLE
+
+#define __ADC12_FORCE_RESET         __HAL_RCC_ADC12_FORCE_RESET
+#define __ADC12_RELEASE_RESET       __HAL_RCC_ADC12_RELEASE_RESET
+#define __ADC34_FORCE_RESET         __HAL_RCC_ADC34_FORCE_RESET
+#define __ADC34_RELEASE_RESET       __HAL_RCC_ADC34_RELEASE_RESET
+#define __DAC2_FORCE_RESET          __HAL_RCC_DAC2_FORCE_RESET
+#define __DAC2_RELEASE_RESET        __HAL_RCC_DAC2_RELEASE_RESET
+#define __TIM18_FORCE_RESET         __HAL_RCC_TIM18_FORCE_RESET
+#define __TIM18_RELEASE_RESET       __HAL_RCC_TIM18_RELEASE_RESET
+#define __TIM19_FORCE_RESET         __HAL_RCC_TIM19_FORCE_RESET
+#define __TIM19_RELEASE_RESET       __HAL_RCC_TIM19_RELEASE_RESET
+#define __TIM20_FORCE_RESET         __HAL_RCC_TIM20_FORCE_RESET
+#define __TIM20_RELEASE_RESET       __HAL_RCC_TIM20_RELEASE_RESET
+#define __HRTIM1_FORCE_RESET        __HAL_RCC_HRTIM1_FORCE_RESET
+#define __HRTIM1_RELEASE_RESET      __HAL_RCC_HRTIM1_RELEASE_RESET
+#define __SDADC1_FORCE_RESET        __HAL_RCC_SDADC1_FORCE_RESET
+#define __SDADC2_FORCE_RESET        __HAL_RCC_SDADC2_FORCE_RESET
+#define __SDADC3_FORCE_RESET        __HAL_RCC_SDADC3_FORCE_RESET
+#define __SDADC1_RELEASE_RESET      __HAL_RCC_SDADC1_RELEASE_RESET
+#define __SDADC2_RELEASE_RESET      __HAL_RCC_SDADC2_RELEASE_RESET
+#define __SDADC3_RELEASE_RESET      __HAL_RCC_SDADC3_RELEASE_RESET
+
+#define __ADC1_IS_CLK_ENABLED       __HAL_RCC_ADC1_IS_CLK_ENABLED
+#define __ADC1_IS_CLK_DISABLED      __HAL_RCC_ADC1_IS_CLK_DISABLED
+#define __ADC12_IS_CLK_ENABLED      __HAL_RCC_ADC12_IS_CLK_ENABLED
+#define __ADC12_IS_CLK_DISABLED     __HAL_RCC_ADC12_IS_CLK_DISABLED
+#define __ADC34_IS_CLK_ENABLED      __HAL_RCC_ADC34_IS_CLK_ENABLED
+#define __ADC34_IS_CLK_DISABLED     __HAL_RCC_ADC34_IS_CLK_DISABLED
+#define __CEC_IS_CLK_ENABLED        __HAL_RCC_CEC_IS_CLK_ENABLED
+#define __CEC_IS_CLK_DISABLED       __HAL_RCC_CEC_IS_CLK_DISABLED
+#define __CRC_IS_CLK_ENABLED        __HAL_RCC_CRC_IS_CLK_ENABLED
+#define __CRC_IS_CLK_DISABLED       __HAL_RCC_CRC_IS_CLK_DISABLED
+#define __DAC1_IS_CLK_ENABLED       __HAL_RCC_DAC1_IS_CLK_ENABLED
+#define __DAC1_IS_CLK_DISABLED      __HAL_RCC_DAC1_IS_CLK_DISABLED
+#define __DAC2_IS_CLK_ENABLED       __HAL_RCC_DAC2_IS_CLK_ENABLED
+#define __DAC2_IS_CLK_DISABLED      __HAL_RCC_DAC2_IS_CLK_DISABLED
+#define __DMA1_IS_CLK_ENABLED       __HAL_RCC_DMA1_IS_CLK_ENABLED
+#define __DMA1_IS_CLK_DISABLED      __HAL_RCC_DMA1_IS_CLK_DISABLED
+#define __DMA2_IS_CLK_ENABLED       __HAL_RCC_DMA2_IS_CLK_ENABLED
+#define __DMA2_IS_CLK_DISABLED      __HAL_RCC_DMA2_IS_CLK_DISABLED
+#define __FLITF_IS_CLK_ENABLED      __HAL_RCC_FLITF_IS_CLK_ENABLED
+#define __FLITF_IS_CLK_DISABLED     __HAL_RCC_FLITF_IS_CLK_DISABLED
+#define __FMC_IS_CLK_ENABLED        __HAL_RCC_FMC_IS_CLK_ENABLED
+#define __FMC_IS_CLK_DISABLED       __HAL_RCC_FMC_IS_CLK_DISABLED
+#define __GPIOA_IS_CLK_ENABLED      __HAL_RCC_GPIOA_IS_CLK_ENABLED
+#define __GPIOA_IS_CLK_DISABLED     __HAL_RCC_GPIOA_IS_CLK_DISABLED
+#define __GPIOB_IS_CLK_ENABLED      __HAL_RCC_GPIOB_IS_CLK_ENABLED
+#define __GPIOB_IS_CLK_DISABLED     __HAL_RCC_GPIOB_IS_CLK_DISABLED
+#define __GPIOC_IS_CLK_ENABLED      __HAL_RCC_GPIOC_IS_CLK_ENABLED
+#define __GPIOC_IS_CLK_DISABLED     __HAL_RCC_GPIOC_IS_CLK_DISABLED
+#define __GPIOD_IS_CLK_ENABLED      __HAL_RCC_GPIOD_IS_CLK_ENABLED
+#define __GPIOD_IS_CLK_DISABLED     __HAL_RCC_GPIOD_IS_CLK_DISABLED
+#define __GPIOE_IS_CLK_ENABLED      __HAL_RCC_GPIOE_IS_CLK_ENABLED
+#define __GPIOE_IS_CLK_DISABLED     __HAL_RCC_GPIOE_IS_CLK_DISABLED
+#define __GPIOF_IS_CLK_ENABLED      __HAL_RCC_GPIOF_IS_CLK_ENABLED
+#define __GPIOF_IS_CLK_DISABLED     __HAL_RCC_GPIOF_IS_CLK_DISABLED
+#define __GPIOG_IS_CLK_ENABLED      __HAL_RCC_GPIOG_IS_CLK_ENABLED
+#define __GPIOG_IS_CLK_DISABLED     __HAL_RCC_GPIOG_IS_CLK_DISABLED
+#define __GPIOH_IS_CLK_ENABLED      __HAL_RCC_GPIOH_IS_CLK_ENABLED
+#define __GPIOH_IS_CLK_DISABLED     __HAL_RCC_GPIOH_IS_CLK_DISABLED
+#define __HRTIM1_IS_CLK_ENABLED     __HAL_RCC_HRTIM1_IS_CLK_ENABLED
+#define __HRTIM1_IS_CLK_DISABLED    __HAL_RCC_HRTIM1_IS_CLK_DISABLED
+#define __I2C1_IS_CLK_ENABLED       __HAL_RCC_I2C1_IS_CLK_ENABLED
+#define __I2C1_IS_CLK_DISABLED      __HAL_RCC_I2C1_IS_CLK_DISABLED
+#define __I2C2_IS_CLK_ENABLED       __HAL_RCC_I2C2_IS_CLK_ENABLED
+#define __I2C2_IS_CLK_DISABLED      __HAL_RCC_I2C2_IS_CLK_DISABLED
+#define __I2C3_IS_CLK_ENABLED       __HAL_RCC_I2C3_IS_CLK_ENABLED
+#define __I2C3_IS_CLK_DISABLED      __HAL_RCC_I2C3_IS_CLK_DISABLED
+#define __PWR_IS_CLK_ENABLED        __HAL_RCC_PWR_IS_CLK_ENABLED
+#define __PWR_IS_CLK_DISABLED       __HAL_RCC_PWR_IS_CLK_DISABLED
+#define __SYSCFG_IS_CLK_ENABLED     __HAL_RCC_SYSCFG_IS_CLK_ENABLED
+#define __SYSCFG_IS_CLK_DISABLED    __HAL_RCC_SYSCFG_IS_CLK_DISABLED
+#define __SPI1_IS_CLK_ENABLED       __HAL_RCC_SPI1_IS_CLK_ENABLED
+#define __SPI1_IS_CLK_DISABLED      __HAL_RCC_SPI1_IS_CLK_DISABLED
+#define __SPI2_IS_CLK_ENABLED       __HAL_RCC_SPI2_IS_CLK_ENABLED
+#define __SPI2_IS_CLK_DISABLED      __HAL_RCC_SPI2_IS_CLK_DISABLED
+#define __SPI3_IS_CLK_ENABLED       __HAL_RCC_SPI3_IS_CLK_ENABLED
+#define __SPI3_IS_CLK_DISABLED      __HAL_RCC_SPI3_IS_CLK_DISABLED
+#define __SPI4_IS_CLK_ENABLED       __HAL_RCC_SPI4_IS_CLK_ENABLED
+#define __SPI4_IS_CLK_DISABLED      __HAL_RCC_SPI4_IS_CLK_DISABLED
+#define __SDADC1_IS_CLK_ENABLED     __HAL_RCC_SDADC1_IS_CLK_ENABLED
+#define __SDADC1_IS_CLK_DISABLED    __HAL_RCC_SDADC1_IS_CLK_DISABLED
+#define __SDADC2_IS_CLK_ENABLED     __HAL_RCC_SDADC2_IS_CLK_ENABLED
+#define __SDADC2_IS_CLK_DISABLED    __HAL_RCC_SDADC2_IS_CLK_DISABLED
+#define __SDADC3_IS_CLK_ENABLED     __HAL_RCC_SDADC3_IS_CLK_ENABLED
+#define __SDADC3_IS_CLK_DISABLED    __HAL_RCC_SDADC3_IS_CLK_DISABLED
+#define __SRAM_IS_CLK_ENABLED       __HAL_RCC_SRAM_IS_CLK_ENABLED
+#define __SRAM_IS_CLK_DISABLED      __HAL_RCC_SRAM_IS_CLK_DISABLED
+#define __TIM1_IS_CLK_ENABLED       __HAL_RCC_TIM1_IS_CLK_ENABLED
+#define __TIM1_IS_CLK_DISABLED      __HAL_RCC_TIM1_IS_CLK_DISABLED
+#define __TIM2_IS_CLK_ENABLED       __HAL_RCC_TIM2_IS_CLK_ENABLED
+#define __TIM2_IS_CLK_DISABLED      __HAL_RCC_TIM2_IS_CLK_DISABLED
+#define __TIM3_IS_CLK_ENABLED       __HAL_RCC_TIM3_IS_CLK_ENABLED
+#define __TIM3_IS_CLK_DISABLED      __HAL_RCC_TIM3_IS_CLK_DISABLED
+#define __TIM4_IS_CLK_ENABLED       __HAL_RCC_TIM4_IS_CLK_ENABLED
+#define __TIM4_IS_CLK_DISABLED      __HAL_RCC_TIM4_IS_CLK_DISABLED
+#define __TIM5_IS_CLK_ENABLED       __HAL_RCC_TIM5_IS_CLK_ENABLED
+#define __TIM5_IS_CLK_DISABLED      __HAL_RCC_TIM5_IS_CLK_DISABLED
+#define __TIM6_IS_CLK_ENABLED       __HAL_RCC_TIM6_IS_CLK_ENABLED
+#define __TIM6_IS_CLK_DISABLED      __HAL_RCC_TIM6_IS_CLK_DISABLED
+#define __TIM7_IS_CLK_ENABLED       __HAL_RCC_TIM7_IS_CLK_ENABLED
+#define __TIM7_IS_CLK_DISABLED      __HAL_RCC_TIM7_IS_CLK_DISABLED
+#define __TIM8_IS_CLK_ENABLED       __HAL_RCC_TIM8_IS_CLK_ENABLED
+#define __TIM8_IS_CLK_DISABLED      __HAL_RCC_TIM8_IS_CLK_DISABLED
+#define __TIM12_IS_CLK_ENABLED      __HAL_RCC_TIM12_IS_CLK_ENABLED
+#define __TIM12_IS_CLK_DISABLED     __HAL_RCC_TIM12_IS_CLK_DISABLED
+#define __TIM13_IS_CLK_ENABLED      __HAL_RCC_TIM13_IS_CLK_ENABLED
+#define __TIM13_IS_CLK_DISABLED     __HAL_RCC_TIM13_IS_CLK_DISABLED
+#define __TIM14_IS_CLK_ENABLED      __HAL_RCC_TIM14_IS_CLK_ENABLED
+#define __TIM14_IS_CLK_DISABLED     __HAL_RCC_TIM14_IS_CLK_DISABLED
+#define __TIM15_IS_CLK_ENABLED      __HAL_RCC_TIM15_IS_CLK_ENABLED
+#define __TIM15_IS_CLK_DISABLED     __HAL_RCC_TIM15_IS_CLK_DISABLED
+#define __TIM16_IS_CLK_ENABLED      __HAL_RCC_TIM16_IS_CLK_ENABLED
+#define __TIM16_IS_CLK_DISABLED     __HAL_RCC_TIM16_IS_CLK_DISABLED
+#define __TIM17_IS_CLK_ENABLED      __HAL_RCC_TIM17_IS_CLK_ENABLED
+#define __TIM17_IS_CLK_DISABLED     __HAL_RCC_TIM17_IS_CLK_DISABLED
+#define __TIM18_IS_CLK_ENABLED      __HAL_RCC_TIM18_IS_CLK_ENABLED
+#define __TIM18_IS_CLK_DISABLED     __HAL_RCC_TIM18_IS_CLK_DISABLED
+#define __TIM19_IS_CLK_ENABLED      __HAL_RCC_TIM19_IS_CLK_ENABLED
+#define __TIM19_IS_CLK_DISABLED     __HAL_RCC_TIM19_IS_CLK_DISABLED
+#define __TIM20_IS_CLK_ENABLED      __HAL_RCC_TIM20_IS_CLK_ENABLED
+#define __TIM20_IS_CLK_DISABLED     __HAL_RCC_TIM20_IS_CLK_DISABLED
+#define __TSC_IS_CLK_ENABLED        __HAL_RCC_TSC_IS_CLK_ENABLED
+#define __TSC_IS_CLK_DISABLED       __HAL_RCC_TSC_IS_CLK_DISABLED
+#define __UART4_IS_CLK_ENABLED      __HAL_RCC_UART4_IS_CLK_ENABLED
+#define __UART4_IS_CLK_DISABLED     __HAL_RCC_UART4_IS_CLK_DISABLED
+#define __UART5_IS_CLK_ENABLED      __HAL_RCC_UART5_IS_CLK_ENABLED
+#define __UART5_IS_CLK_DISABLED     __HAL_RCC_UART5_IS_CLK_DISABLED
+#define __USART1_IS_CLK_ENABLED     __HAL_RCC_USART1_IS_CLK_ENABLED
+#define __USART1_IS_CLK_DISABLED    __HAL_RCC_USART1_IS_CLK_DISABLED
+#define __USART2_IS_CLK_ENABLED     __HAL_RCC_USART2_IS_CLK_ENABLED
+#define __USART2_IS_CLK_DISABLED    __HAL_RCC_USART2_IS_CLK_DISABLED
+#define __USART3_IS_CLK_ENABLED     __HAL_RCC_USART3_IS_CLK_ENABLED
+#define __USART3_IS_CLK_DISABLED    __HAL_RCC_USART3_IS_CLK_DISABLED
+#define __USB_IS_CLK_ENABLED        __HAL_RCC_USB_IS_CLK_ENABLED
+#define __USB_IS_CLK_DISABLED       __HAL_RCC_USB_IS_CLK_DISABLED
+#define __WWDG_IS_CLK_ENABLED       __HAL_RCC_WWDG_IS_CLK_ENABLED
+#define __WWDG_IS_CLK_DISABLED      __HAL_RCC_WWDG_IS_CLK_DISABLED
+
+#if defined(STM32L1)
+#define __HAL_RCC_CRYP_CLK_DISABLE         __HAL_RCC_AES_CLK_DISABLE
+#define __HAL_RCC_CRYP_CLK_ENABLE          __HAL_RCC_AES_CLK_ENABLE
+#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE   __HAL_RCC_AES_CLK_SLEEP_DISABLE
+#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE    __HAL_RCC_AES_CLK_SLEEP_ENABLE
+#define __HAL_RCC_CRYP_FORCE_RESET         __HAL_RCC_AES_FORCE_RESET
+#define __HAL_RCC_CRYP_RELEASE_RESET       __HAL_RCC_AES_RELEASE_RESET
+#endif /* STM32L1 */
+
+#if defined(STM32F4)
+#define __HAL_RCC_SDMMC1_FORCE_RESET       __HAL_RCC_SDIO_FORCE_RESET
+#define __HAL_RCC_SDMMC1_RELEASE_RESET     __HAL_RCC_SDIO_RELEASE_RESET
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE  __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDMMC1_CLK_ENABLE        __HAL_RCC_SDIO_CLK_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_DISABLE       __HAL_RCC_SDIO_CLK_DISABLE
+#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED    __HAL_RCC_SDIO_IS_CLK_ENABLED
+#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED   __HAL_RCC_SDIO_IS_CLK_DISABLED
+#define Sdmmc1ClockSelection               SdioClockSelection
+#define RCC_PERIPHCLK_SDMMC1               RCC_PERIPHCLK_SDIO
+#define RCC_SDMMC1CLKSOURCE_CLK48          RCC_SDIOCLKSOURCE_CK48
+#define RCC_SDMMC1CLKSOURCE_SYSCLK         RCC_SDIOCLKSOURCE_SYSCLK
+#define __HAL_RCC_SDMMC1_CONFIG            __HAL_RCC_SDIO_CONFIG
+#define __HAL_RCC_GET_SDMMC1_SOURCE        __HAL_RCC_GET_SDIO_SOURCE
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define __HAL_RCC_SDIO_FORCE_RESET         __HAL_RCC_SDMMC1_FORCE_RESET
+#define __HAL_RCC_SDIO_RELEASE_RESET       __HAL_RCC_SDMMC1_RELEASE_RESET
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE    __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE   __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDIO_CLK_ENABLE          __HAL_RCC_SDMMC1_CLK_ENABLE
+#define __HAL_RCC_SDIO_CLK_DISABLE         __HAL_RCC_SDMMC1_CLK_DISABLE
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED      __HAL_RCC_SDMMC1_IS_CLK_ENABLED
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED     __HAL_RCC_SDMMC1_IS_CLK_DISABLED
+#define SdioClockSelection                 Sdmmc1ClockSelection
+#define RCC_PERIPHCLK_SDIO                 RCC_PERIPHCLK_SDMMC1
+#define __HAL_RCC_SDIO_CONFIG              __HAL_RCC_SDMMC1_CONFIG
+#define __HAL_RCC_GET_SDIO_SOURCE          __HAL_RCC_GET_SDMMC1_SOURCE
+#endif
+
+#if defined(STM32F7)
+#define RCC_SDIOCLKSOURCE_CLK48             RCC_SDMMC1CLKSOURCE_CLK48
+#define RCC_SDIOCLKSOURCE_SYSCLK           RCC_SDMMC1CLKSOURCE_SYSCLK
+#endif
+
+#if defined(STM32H7)
+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()              __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()         __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()             __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE()        __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET()             __HAL_RCC_USB1_OTG_HS_FORCE_RESET()
+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()           __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()        __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()   __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()       __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE()  __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
+
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()             __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE()        __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE()            __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE()       __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()            __HAL_RCC_USB2_OTG_FS_FORCE_RESET()
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET()          __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()       __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE()  __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE()      __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()
+#endif
+
+#define __HAL_RCC_I2SCLK            __HAL_RCC_I2S_CONFIG
+#define __HAL_RCC_I2SCLK_CONFIG     __HAL_RCC_I2S_CONFIG
+
+#define __RCC_PLLSRC                RCC_GET_PLL_OSCSOURCE
+
+#define IS_RCC_MSIRANGE             IS_RCC_MSI_CLOCK_RANGE
+#define IS_RCC_RTCCLK_SOURCE        IS_RCC_RTCCLKSOURCE
+#define IS_RCC_SYSCLK_DIV           IS_RCC_HCLK
+#define IS_RCC_HCLK_DIV             IS_RCC_PCLK
+#define IS_RCC_PERIPHCLK            IS_RCC_PERIPHCLOCK
+
+#define RCC_IT_HSI14                RCC_IT_HSI14RDY
+
+#define RCC_IT_CSSLSE               RCC_IT_LSECSS
+#define RCC_IT_CSSHSE               RCC_IT_CSS
+
+#define RCC_PLLMUL_3                RCC_PLL_MUL3
+#define RCC_PLLMUL_4                RCC_PLL_MUL4
+#define RCC_PLLMUL_6                RCC_PLL_MUL6
+#define RCC_PLLMUL_8                RCC_PLL_MUL8
+#define RCC_PLLMUL_12               RCC_PLL_MUL12
+#define RCC_PLLMUL_16               RCC_PLL_MUL16
+#define RCC_PLLMUL_24               RCC_PLL_MUL24
+#define RCC_PLLMUL_32               RCC_PLL_MUL32
+#define RCC_PLLMUL_48               RCC_PLL_MUL48
+
+#define RCC_PLLDIV_2                RCC_PLL_DIV2
+#define RCC_PLLDIV_3                RCC_PLL_DIV3
+#define RCC_PLLDIV_4                RCC_PLL_DIV4
+
+#define IS_RCC_MCOSOURCE            IS_RCC_MCO1SOURCE
+#define __HAL_RCC_MCO_CONFIG        __HAL_RCC_MCO1_CONFIG
+#define RCC_MCO_NODIV               RCC_MCODIV_1
+#define RCC_MCO_DIV1                RCC_MCODIV_1
+#define RCC_MCO_DIV2                RCC_MCODIV_2
+#define RCC_MCO_DIV4                RCC_MCODIV_4
+#define RCC_MCO_DIV8                RCC_MCODIV_8
+#define RCC_MCO_DIV16               RCC_MCODIV_16
+#define RCC_MCO_DIV32               RCC_MCODIV_32
+#define RCC_MCO_DIV64               RCC_MCODIV_64
+#define RCC_MCO_DIV128              RCC_MCODIV_128
+#define RCC_MCOSOURCE_NONE          RCC_MCO1SOURCE_NOCLOCK
+#define RCC_MCOSOURCE_LSI           RCC_MCO1SOURCE_LSI
+#define RCC_MCOSOURCE_LSE           RCC_MCO1SOURCE_LSE
+#define RCC_MCOSOURCE_SYSCLK        RCC_MCO1SOURCE_SYSCLK
+#define RCC_MCOSOURCE_HSI           RCC_MCO1SOURCE_HSI
+#define RCC_MCOSOURCE_HSI14         RCC_MCO1SOURCE_HSI14
+#define RCC_MCOSOURCE_HSI48         RCC_MCO1SOURCE_HSI48
+#define RCC_MCOSOURCE_HSE           RCC_MCO1SOURCE_HSE
+#define RCC_MCOSOURCE_PLLCLK_DIV1   RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_NODIV  RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_DIV2   RCC_MCO1SOURCE_PLLCLK_DIV2
+
+#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
+#define RCC_RTCCLKSOURCE_NO_CLK     RCC_RTCCLKSOURCE_NONE
+#else
+#define RCC_RTCCLKSOURCE_NONE       RCC_RTCCLKSOURCE_NO_CLK
+#endif
+
+#define RCC_USBCLK_PLLSAI1          RCC_USBCLKSOURCE_PLLSAI1
+#define RCC_USBCLK_PLL              RCC_USBCLKSOURCE_PLL
+#define RCC_USBCLK_MSI              RCC_USBCLKSOURCE_MSI
+#define RCC_USBCLKSOURCE_PLLCLK     RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1          RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1_5        RCC_USBCLKSOURCE_PLL_DIV1_5
+#define RCC_USBPLLCLK_DIV2          RCC_USBCLKSOURCE_PLL_DIV2
+#define RCC_USBPLLCLK_DIV3          RCC_USBCLKSOURCE_PLL_DIV3
+
+#define HSION_BitNumber        RCC_HSION_BIT_NUMBER
+#define HSION_BITNUMBER        RCC_HSION_BIT_NUMBER
+#define HSEON_BitNumber        RCC_HSEON_BIT_NUMBER
+#define HSEON_BITNUMBER        RCC_HSEON_BIT_NUMBER
+#define MSION_BITNUMBER        RCC_MSION_BIT_NUMBER
+#define CSSON_BitNumber        RCC_CSSON_BIT_NUMBER
+#define CSSON_BITNUMBER        RCC_CSSON_BIT_NUMBER
+#define PLLON_BitNumber        RCC_PLLON_BIT_NUMBER
+#define PLLON_BITNUMBER        RCC_PLLON_BIT_NUMBER
+#define PLLI2SON_BitNumber     RCC_PLLI2SON_BIT_NUMBER
+#define I2SSRC_BitNumber       RCC_I2SSRC_BIT_NUMBER
+#define RTCEN_BitNumber        RCC_RTCEN_BIT_NUMBER
+#define RTCEN_BITNUMBER        RCC_RTCEN_BIT_NUMBER
+#define BDRST_BitNumber        RCC_BDRST_BIT_NUMBER
+#define BDRST_BITNUMBER        RCC_BDRST_BIT_NUMBER
+#define RTCRST_BITNUMBER       RCC_RTCRST_BIT_NUMBER
+#define LSION_BitNumber        RCC_LSION_BIT_NUMBER
+#define LSION_BITNUMBER        RCC_LSION_BIT_NUMBER
+#define LSEON_BitNumber        RCC_LSEON_BIT_NUMBER
+#define LSEON_BITNUMBER        RCC_LSEON_BIT_NUMBER
+#define LSEBYP_BITNUMBER       RCC_LSEBYP_BIT_NUMBER
+#define PLLSAION_BitNumber     RCC_PLLSAION_BIT_NUMBER
+#define TIMPRE_BitNumber       RCC_TIMPRE_BIT_NUMBER
+#define RMVF_BitNumber         RCC_RMVF_BIT_NUMBER
+#define RMVF_BITNUMBER         RCC_RMVF_BIT_NUMBER
+#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
+#define CR_BYTE2_ADDRESS       RCC_CR_BYTE2_ADDRESS
+#define CIR_BYTE1_ADDRESS      RCC_CIR_BYTE1_ADDRESS
+#define CIR_BYTE2_ADDRESS      RCC_CIR_BYTE2_ADDRESS
+#define BDCR_BYTE0_ADDRESS     RCC_BDCR_BYTE0_ADDRESS
+#define DBP_TIMEOUT_VALUE      RCC_DBP_TIMEOUT_VALUE
+#define LSE_TIMEOUT_VALUE      RCC_LSE_TIMEOUT_VALUE
+
+#define CR_HSION_BB            RCC_CR_HSION_BB
+#define CR_CSSON_BB            RCC_CR_CSSON_BB
+#define CR_PLLON_BB            RCC_CR_PLLON_BB
+#define CR_PLLI2SON_BB         RCC_CR_PLLI2SON_BB
+#define CR_MSION_BB            RCC_CR_MSION_BB
+#define CSR_LSION_BB           RCC_CSR_LSION_BB
+#define CSR_LSEON_BB           RCC_CSR_LSEON_BB
+#define CSR_LSEBYP_BB          RCC_CSR_LSEBYP_BB
+#define CSR_RTCEN_BB           RCC_CSR_RTCEN_BB
+#define CSR_RTCRST_BB          RCC_CSR_RTCRST_BB
+#define CFGR_I2SSRC_BB         RCC_CFGR_I2SSRC_BB
+#define BDCR_RTCEN_BB          RCC_BDCR_RTCEN_BB
+#define BDCR_BDRST_BB          RCC_BDCR_BDRST_BB
+#define CR_HSEON_BB            RCC_CR_HSEON_BB
+#define CSR_RMVF_BB            RCC_CSR_RMVF_BB
+#define CR_PLLSAION_BB         RCC_CR_PLLSAION_BB
+#define DCKCFGR_TIMPRE_BB      RCC_DCKCFGR_TIMPRE_BB
+
+#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER     __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
+#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER    __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
+#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB        __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
+#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB       __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
+#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE         __HAL_RCC_CRS_RELOADVALUE_CALCULATE
+
+#define __HAL_RCC_GET_IT_SOURCE                     __HAL_RCC_GET_IT
+
+#define RCC_CRS_SYNCWARM       RCC_CRS_SYNCWARN
+#define RCC_CRS_TRIMOV         RCC_CRS_TRIMOVF
+
+#define RCC_PERIPHCLK_CK48               RCC_PERIPHCLK_CLK48
+#define RCC_CK48CLKSOURCE_PLLQ           RCC_CLK48CLKSOURCE_PLLQ
+#define RCC_CK48CLKSOURCE_PLLSAIP        RCC_CLK48CLKSOURCE_PLLSAIP
+#define RCC_CK48CLKSOURCE_PLLI2SQ        RCC_CLK48CLKSOURCE_PLLI2SQ
+#define IS_RCC_CK48CLKSOURCE             IS_RCC_CLK48CLKSOURCE
+#define RCC_SDIOCLKSOURCE_CK48           RCC_SDIOCLKSOURCE_CLK48
+
+#define __HAL_RCC_DFSDM_CLK_ENABLE             __HAL_RCC_DFSDM1_CLK_ENABLE
+#define __HAL_RCC_DFSDM_CLK_DISABLE            __HAL_RCC_DFSDM1_CLK_DISABLE
+#define __HAL_RCC_DFSDM_IS_CLK_ENABLED         __HAL_RCC_DFSDM1_IS_CLK_ENABLED
+#define __HAL_RCC_DFSDM_IS_CLK_DISABLED        __HAL_RCC_DFSDM1_IS_CLK_DISABLED
+#define __HAL_RCC_DFSDM_FORCE_RESET            __HAL_RCC_DFSDM1_FORCE_RESET
+#define __HAL_RCC_DFSDM_RELEASE_RESET          __HAL_RCC_DFSDM1_RELEASE_RESET
+#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE       __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
+#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE      __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED   __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED  __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
+#define DfsdmClockSelection         Dfsdm1ClockSelection
+#define RCC_PERIPHCLK_DFSDM         RCC_PERIPHCLK_DFSDM1
+#define RCC_DFSDMCLKSOURCE_PCLK     RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_DFSDMCLKSOURCE_SYSCLK   RCC_DFSDM1CLKSOURCE_SYSCLK
+#define __HAL_RCC_DFSDM_CONFIG      __HAL_RCC_DFSDM1_CONFIG
+#define __HAL_RCC_GET_DFSDM_SOURCE  __HAL_RCC_GET_DFSDM1_SOURCE
+#define RCC_DFSDM1CLKSOURCE_PCLK    RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_SWPMI1CLKSOURCE_PCLK    RCC_SWPMI1CLKSOURCE_PCLK1
+#define RCC_LPTIM1CLKSOURCE_PCLK    RCC_LPTIM1CLKSOURCE_PCLK1
+#define RCC_LPTIM2CLKSOURCE_PCLK    RCC_LPTIM2CLKSOURCE_PCLK1
+
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM1AUDIOCLKSOURCE_I2S1
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM1AUDIOCLKSOURCE_I2S2
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM2AUDIOCLKSOURCE_I2S1
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM2AUDIOCLKSOURCE_I2S2
+#define RCC_DFSDM1CLKSOURCE_APB2            RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_DFSDM2CLKSOURCE_APB2            RCC_DFSDM2CLKSOURCE_PCLK2
+#define RCC_FMPI2C1CLKSOURCE_APB            RCC_FMPI2C1CLKSOURCE_PCLK1
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define  HAL_RNG_ReadyCallback(__HANDLE__)  HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4)
+#else
+#define __HAL_RTC_CLEAR_FLAG                      __HAL_RTC_EXTI_CLEAR_FLAG
+#endif
+#define __HAL_RTC_DISABLE_IT                      __HAL_RTC_EXTI_DISABLE_IT
+#define __HAL_RTC_ENABLE_IT                       __HAL_RTC_EXTI_ENABLE_IT
+
+#if defined (STM32F1)
+#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
+
+#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_ENABLE_IT()
+
+#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_DISABLE_IT()
+
+#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT)    __HAL_RTC_ALARM_EXTI_GET_FLAG()
+
+#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
+#else
+#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
+                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
+                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
+#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__)   (((__EXTI_LINE__)  == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
+                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
+                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
+#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
+                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
+                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
+#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__)    (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
+                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
+                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
+#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__)   (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
+                                                      (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() :  \
+                                                          __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
+#endif   /* STM32F1 */
+
+#define IS_ALARM                                  IS_RTC_ALARM
+#define IS_ALARM_MASK                             IS_RTC_ALARM_MASK
+#define IS_TAMPER                                 IS_RTC_TAMPER
+#define IS_TAMPER_ERASE_MODE                      IS_RTC_TAMPER_ERASE_MODE
+#define IS_TAMPER_FILTER                          IS_RTC_TAMPER_FILTER
+#define IS_TAMPER_INTERRUPT                       IS_RTC_TAMPER_INTERRUPT
+#define IS_TAMPER_MASKFLAG_STATE                  IS_RTC_TAMPER_MASKFLAG_STATE
+#define IS_TAMPER_PRECHARGE_DURATION              IS_RTC_TAMPER_PRECHARGE_DURATION
+#define IS_TAMPER_PULLUP_STATE                    IS_RTC_TAMPER_PULLUP_STATE
+#define IS_TAMPER_SAMPLING_FREQ                   IS_RTC_TAMPER_SAMPLING_FREQ
+#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION     IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
+#define IS_TAMPER_TRIGGER                         IS_RTC_TAMPER_TRIGGER
+#define IS_WAKEUP_CLOCK                           IS_RTC_WAKEUP_CLOCK
+#define IS_WAKEUP_COUNTER                         IS_RTC_WAKEUP_COUNTER
+
+#define __RTC_WRITEPROTECTION_ENABLE  __HAL_RTC_WRITEPROTECTION_ENABLE
+#define __RTC_WRITEPROTECTION_DISABLE  __HAL_RTC_WRITEPROTECTION_DISABLE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define SD_OCR_CID_CSD_OVERWRIETE   SD_OCR_CID_CSD_OVERWRITE
+#define SD_CMD_SD_APP_STAUS         SD_CMD_SD_APP_STATUS
+
+#if defined(STM32F4) || defined(STM32F2)
+#define  SD_SDMMC_DISABLED          SD_SDIO_DISABLED
+#define  SD_SDMMC_FUNCTION_BUSY     SD_SDIO_FUNCTION_BUSY
+#define  SD_SDMMC_FUNCTION_FAILED   SD_SDIO_FUNCTION_FAILED
+#define  SD_SDMMC_UNKNOWN_FUNCTION  SD_SDIO_UNKNOWN_FUNCTION
+#define  SD_CMD_SDMMC_SEN_OP_COND   SD_CMD_SDIO_SEN_OP_COND
+#define  SD_CMD_SDMMC_RW_DIRECT     SD_CMD_SDIO_RW_DIRECT
+#define  SD_CMD_SDMMC_RW_EXTENDED   SD_CMD_SDIO_RW_EXTENDED
+#define  __HAL_SD_SDMMC_ENABLE      __HAL_SD_SDIO_ENABLE
+#define  __HAL_SD_SDMMC_DISABLE     __HAL_SD_SDIO_DISABLE
+#define  __HAL_SD_SDMMC_DMA_ENABLE  __HAL_SD_SDIO_DMA_ENABLE
+#define  __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
+#define  __HAL_SD_SDMMC_ENABLE_IT   __HAL_SD_SDIO_ENABLE_IT
+#define  __HAL_SD_SDMMC_DISABLE_IT  __HAL_SD_SDIO_DISABLE_IT
+#define  __HAL_SD_SDMMC_GET_FLAG    __HAL_SD_SDIO_GET_FLAG
+#define  __HAL_SD_SDMMC_CLEAR_FLAG  __HAL_SD_SDIO_CLEAR_FLAG
+#define  __HAL_SD_SDMMC_GET_IT      __HAL_SD_SDIO_GET_IT
+#define  __HAL_SD_SDMMC_CLEAR_IT    __HAL_SD_SDIO_CLEAR_IT
+#define  SDMMC_STATIC_FLAGS         SDIO_STATIC_FLAGS
+#define  SDMMC_CMD0TIMEOUT          SDIO_CMD0TIMEOUT
+#define  SD_SDMMC_SEND_IF_COND      SD_SDIO_SEND_IF_COND
+/* alias CMSIS */
+#define  SDMMC1_IRQn                SDIO_IRQn
+#define  SDMMC1_IRQHandler          SDIO_IRQHandler
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define  SD_SDIO_DISABLED           SD_SDMMC_DISABLED
+#define  SD_SDIO_FUNCTION_BUSY      SD_SDMMC_FUNCTION_BUSY
+#define  SD_SDIO_FUNCTION_FAILED    SD_SDMMC_FUNCTION_FAILED
+#define  SD_SDIO_UNKNOWN_FUNCTION   SD_SDMMC_UNKNOWN_FUNCTION
+#define  SD_CMD_SDIO_SEN_OP_COND    SD_CMD_SDMMC_SEN_OP_COND
+#define  SD_CMD_SDIO_RW_DIRECT      SD_CMD_SDMMC_RW_DIRECT
+#define  SD_CMD_SDIO_RW_EXTENDED    SD_CMD_SDMMC_RW_EXTENDED
+#define  __HAL_SD_SDIO_ENABLE       __HAL_SD_SDMMC_ENABLE
+#define  __HAL_SD_SDIO_DISABLE      __HAL_SD_SDMMC_DISABLE
+#define  __HAL_SD_SDIO_DMA_ENABLE   __HAL_SD_SDMMC_DMA_ENABLE
+#define  __HAL_SD_SDIO_DMA_DISABL   __HAL_SD_SDMMC_DMA_DISABLE
+#define  __HAL_SD_SDIO_ENABLE_IT    __HAL_SD_SDMMC_ENABLE_IT
+#define  __HAL_SD_SDIO_DISABLE_IT   __HAL_SD_SDMMC_DISABLE_IT
+#define  __HAL_SD_SDIO_GET_FLAG     __HAL_SD_SDMMC_GET_FLAG
+#define  __HAL_SD_SDIO_CLEAR_FLAG   __HAL_SD_SDMMC_CLEAR_FLAG
+#define  __HAL_SD_SDIO_GET_IT       __HAL_SD_SDMMC_GET_IT
+#define  __HAL_SD_SDIO_CLEAR_IT     __HAL_SD_SDMMC_CLEAR_IT
+#define  SDIO_STATIC_FLAGS          SDMMC_STATIC_FLAGS
+#define  SDIO_CMD0TIMEOUT           SDMMC_CMD0TIMEOUT
+#define  SD_SDIO_SEND_IF_COND       SD_SDMMC_SEND_IF_COND
+/* alias CMSIS for compatibilities */
+#define  SDIO_IRQn                  SDMMC1_IRQn
+#define  SDIO_IRQHandler            SDMMC1_IRQHandler
+#endif
+
+#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7)
+#define  HAL_SD_CardCIDTypedef       HAL_SD_CardCIDTypeDef
+#define  HAL_SD_CardCSDTypedef       HAL_SD_CardCSDTypeDef
+#define  HAL_SD_CardStatusTypedef    HAL_SD_CardStatusTypeDef
+#define  HAL_SD_CardStateTypedef     HAL_SD_CardStateTypeDef
+#endif
+
+#if defined(STM32H7) || defined(STM32L5)
+#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback   HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
+#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback   HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
+#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback  HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
+#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback  HAL_MMCEx_Write_DMADoubleBuf1CpltCallback
+#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback    HAL_SDEx_Read_DMADoubleBuf0CpltCallback
+#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback    HAL_SDEx_Read_DMADoubleBuf1CpltCallback
+#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback   HAL_SDEx_Write_DMADoubleBuf0CpltCallback
+#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback   HAL_SDEx_Write_DMADoubleBuf1CpltCallback
+#define HAL_SD_DriveTransciver_1_8V_Callback          HAL_SD_DriveTransceiver_1_8V_Callback
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __SMARTCARD_ENABLE_IT           __HAL_SMARTCARD_ENABLE_IT
+#define __SMARTCARD_DISABLE_IT          __HAL_SMARTCARD_DISABLE_IT
+#define __SMARTCARD_ENABLE              __HAL_SMARTCARD_ENABLE
+#define __SMARTCARD_DISABLE             __HAL_SMARTCARD_DISABLE
+#define __SMARTCARD_DMA_REQUEST_ENABLE  __HAL_SMARTCARD_DMA_REQUEST_ENABLE
+#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
+
+#define __HAL_SMARTCARD_GETCLOCKSOURCE  SMARTCARD_GETCLOCKSOURCE
+#define __SMARTCARD_GETCLOCKSOURCE      SMARTCARD_GETCLOCKSOURCE
+
+#define IS_SMARTCARD_ONEBIT_SAMPLING    IS_SMARTCARD_ONE_BIT_SAMPLE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_SMBUS_RESET_CR1           SMBUS_RESET_CR1
+#define __HAL_SMBUS_RESET_CR2           SMBUS_RESET_CR2
+#define __HAL_SMBUS_GENERATE_START      SMBUS_GENERATE_START
+#define __HAL_SMBUS_GET_ADDR_MATCH      SMBUS_GET_ADDR_MATCH
+#define __HAL_SMBUS_GET_DIR             SMBUS_GET_DIR
+#define __HAL_SMBUS_GET_STOP_MODE       SMBUS_GET_STOP_MODE
+#define __HAL_SMBUS_GET_PEC_MODE        SMBUS_GET_PEC_MODE
+#define __HAL_SMBUS_GET_ALERT_ENABLED   SMBUS_GET_ALERT_ENABLED
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_SPI_1LINE_TX              SPI_1LINE_TX
+#define __HAL_SPI_1LINE_RX              SPI_1LINE_RX
+#define __HAL_SPI_RESET_CRC             SPI_RESET_CRC
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_UART_GETCLOCKSOURCE       UART_GETCLOCKSOURCE
+#define __HAL_UART_MASK_COMPUTATION     UART_MASK_COMPUTATION
+#define __UART_GETCLOCKSOURCE           UART_GETCLOCKSOURCE
+#define __UART_MASK_COMPUTATION         UART_MASK_COMPUTATION
+
+#define IS_UART_WAKEUPMETHODE           IS_UART_WAKEUPMETHOD
+
+#define IS_UART_ONEBIT_SAMPLE           IS_UART_ONE_BIT_SAMPLE
+#define IS_UART_ONEBIT_SAMPLING         IS_UART_ONE_BIT_SAMPLE
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __USART_ENABLE_IT               __HAL_USART_ENABLE_IT
+#define __USART_DISABLE_IT              __HAL_USART_DISABLE_IT
+#define __USART_ENABLE                  __HAL_USART_ENABLE
+#define __USART_DISABLE                 __HAL_USART_DISABLE
+
+#define __HAL_USART_GETCLOCKSOURCE      USART_GETCLOCKSOURCE
+#define __USART_GETCLOCKSOURCE          USART_GETCLOCKSOURCE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define USB_EXTI_LINE_WAKEUP                               USB_WAKEUP_EXTI_LINE
+
+#define USB_FS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
+#define USB_FS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_FS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_FS_EXTI_LINE_WAKEUP                            USB_OTG_FS_WAKEUP_EXTI_LINE
+
+#define USB_HS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
+#define USB_HS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_HS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_HS_EXTI_LINE_WAKEUP                            USB_OTG_HS_WAKEUP_EXTI_LINE
+
+#define __HAL_USB_EXTI_ENABLE_IT                           __HAL_USB_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_EXTI_DISABLE_IT                          __HAL_USB_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_EXTI_GET_FLAG                            __HAL_USB_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_EXTI_CLEAR_FLAG                          __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER             __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER            __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER           __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+
+#define __HAL_USB_FS_EXTI_ENABLE_IT                        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_FS_EXTI_DISABLE_IT                       __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_FS_EXTI_GET_FLAG                         __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_FS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define __HAL_USB_HS_EXTI_ENABLE_IT                        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_HS_EXTI_DISABLE_IT                       __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_HS_EXTI_GET_FLAG                         __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_HS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define HAL_PCD_ActiveRemoteWakeup                         HAL_PCD_ActivateRemoteWakeup
+#define HAL_PCD_DeActiveRemoteWakeup                       HAL_PCD_DeActivateRemoteWakeup
+
+#define HAL_PCD_SetTxFiFo                                  HAL_PCDEx_SetTxFiFo
+#define HAL_PCD_SetRxFiFo                                  HAL_PCDEx_SetRxFiFo
+/**
+  * @}
+  */
+
+/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_TIM_SetICPrescalerValue   TIM_SET_ICPRESCALERVALUE
+#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
+
+#define TIM_GET_ITSTATUS                __HAL_TIM_GET_IT_SOURCE
+#define TIM_GET_CLEAR_IT                __HAL_TIM_CLEAR_IT
+
+#define __HAL_TIM_GET_ITSTATUS          __HAL_TIM_GET_IT_SOURCE
+
+#define __HAL_TIM_DIRECTION_STATUS      __HAL_TIM_IS_TIM_COUNTING_DOWN
+#define __HAL_TIM_PRESCALER             __HAL_TIM_SET_PRESCALER
+#define __HAL_TIM_SetCounter            __HAL_TIM_SET_COUNTER
+#define __HAL_TIM_GetCounter            __HAL_TIM_GET_COUNTER
+#define __HAL_TIM_SetAutoreload         __HAL_TIM_SET_AUTORELOAD
+#define __HAL_TIM_GetAutoreload         __HAL_TIM_GET_AUTORELOAD
+#define __HAL_TIM_SetClockDivision      __HAL_TIM_SET_CLOCKDIVISION
+#define __HAL_TIM_GetClockDivision      __HAL_TIM_GET_CLOCKDIVISION
+#define __HAL_TIM_SetICPrescaler        __HAL_TIM_SET_ICPRESCALER
+#define __HAL_TIM_GetICPrescaler        __HAL_TIM_GET_ICPRESCALER
+#define __HAL_TIM_SetCompare            __HAL_TIM_SET_COMPARE
+#define __HAL_TIM_GetCompare            __HAL_TIM_GET_COMPARE
+
+#define TIM_BREAKINPUTSOURCE_DFSDM  TIM_BREAKINPUTSOURCE_DFSDM1
+/**
+  * @}
+  */
+
+/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_ETH_EXTI_ENABLE_IT                   __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_ETH_EXTI_DISABLE_IT                  __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_ETH_EXTI_GET_FLAG                    __HAL_ETH_WAKEUP_EXTI_GET_FLAG
+#define __HAL_ETH_EXTI_CLEAR_FLAG                  __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER     __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER    __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER   __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
+
+#define ETH_PROMISCIOUSMODE_ENABLE   ETH_PROMISCUOUS_MODE_ENABLE
+#define ETH_PROMISCIOUSMODE_DISABLE  ETH_PROMISCUOUS_MODE_DISABLE
+#define IS_ETH_PROMISCIOUS_MODE      IS_ETH_PROMISCUOUS_MODE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_LTDC_LAYER LTDC_LAYER
+#define __HAL_LTDC_RELOAD_CONFIG  __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define SAI_OUTPUTDRIVE_DISABLED          SAI_OUTPUTDRIVE_DISABLE
+#define SAI_OUTPUTDRIVE_ENABLED           SAI_OUTPUTDRIVE_ENABLE
+#define SAI_MASTERDIVIDER_ENABLED         SAI_MASTERDIVIDER_ENABLE
+#define SAI_MASTERDIVIDER_DISABLED        SAI_MASTERDIVIDER_DISABLE
+#define SAI_STREOMODE                     SAI_STEREOMODE
+#define SAI_FIFOStatus_Empty              SAI_FIFOSTATUS_EMPTY
+#define SAI_FIFOStatus_Less1QuarterFull   SAI_FIFOSTATUS_LESS1QUARTERFULL
+#define SAI_FIFOStatus_1QuarterFull       SAI_FIFOSTATUS_1QUARTERFULL
+#define SAI_FIFOStatus_HalfFull           SAI_FIFOSTATUS_HALFFULL
+#define SAI_FIFOStatus_3QuartersFull      SAI_FIFOSTATUS_3QUARTERFULL
+#define SAI_FIFOStatus_Full               SAI_FIFOSTATUS_FULL
+#define IS_SAI_BLOCK_MONO_STREO_MODE      IS_SAI_BLOCK_MONO_STEREO_MODE
+#define SAI_SYNCHRONOUS_EXT               SAI_SYNCHRONOUS_EXT_SAI1
+#define SAI_SYNCEXT_IN_ENABLE             SAI_SYNCEXT_OUTBLOCKA_ENABLE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#if defined(STM32H7)
+#define HAL_SPDIFRX_ReceiveControlFlow      HAL_SPDIFRX_ReceiveCtrlFlow
+#define HAL_SPDIFRX_ReceiveControlFlow_IT   HAL_SPDIFRX_ReceiveCtrlFlow_IT
+#define HAL_SPDIFRX_ReceiveControlFlow_DMA  HAL_SPDIFRX_ReceiveCtrlFlow_DMA
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
+#define HAL_HRTIM_WaveformCounterStart_IT      HAL_HRTIM_WaveformCountStart_IT
+#define HAL_HRTIM_WaveformCounterStart_DMA     HAL_HRTIM_WaveformCountStart_DMA
+#define HAL_HRTIM_WaveformCounterStart         HAL_HRTIM_WaveformCountStart
+#define HAL_HRTIM_WaveformCounterStop_IT       HAL_HRTIM_WaveformCountStop_IT
+#define HAL_HRTIM_WaveformCounterStop_DMA      HAL_HRTIM_WaveformCountStop_DMA
+#define HAL_HRTIM_WaveformCounterStop          HAL_HRTIM_WaveformCountStop
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)
+#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
+#endif /* STM32L4 || STM32F4 || STM32F7 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32_HAL_LEGACY */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h
new file mode 100644
index 00000000..2ee957c3
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h
@@ -0,0 +1,1078 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal.h
+  * @author  MCD Application Team
+  * @brief   This file contains all the functions prototypes for the HAL
+  *          module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_H
+#define STM32H7xx_HAL_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_conf.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup HAL
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup HAL_TICK_FREQ Tick Frequency
+  * @{
+  */
+typedef enum
+{
+  HAL_TICK_FREQ_10HZ         = 100U,
+  HAL_TICK_FREQ_100HZ        = 10U,
+  HAL_TICK_FREQ_1KHZ         = 1U,
+  HAL_TICK_FREQ_DEFAULT      = HAL_TICK_FREQ_1KHZ
+} HAL_TickFreqTypeDef;
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup REV_ID device revision ID
+  * @{
+  */
+#define REV_ID_Y ((uint32_t)0x1003)  /*!< STM32H7 rev.Y */
+#define REV_ID_B ((uint32_t)0x2000)  /*!< STM32H7 rev.B */
+#define REV_ID_X ((uint32_t)0x2001)  /*!< STM32H7 rev.X */
+#define REV_ID_V ((uint32_t)0x2003)  /*!< STM32H7 rev.V */
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
+  * @{
+  */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE0   VREFBUF_CSR_VRS_OUT2   /*!< Voltage reference scale 0 (VREF_OUT2) */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE1   VREFBUF_CSR_VRS_OUT1   /*!< Voltage reference scale 1 (VREF_OUT1) */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE2   VREFBUF_CSR_VRS_OUT4   /*!< Voltage reference scale 2 (VREF_OUT4) */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE3   VREFBUF_CSR_VRS_OUT3   /*!< Voltage reference scale 3 (VREF_OUT3) */
+
+
+#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__)  (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
+                                                     ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1) || \
+                                                     ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE2) || \
+                                                     ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE3))
+
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance
+  * @{
+  */
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE  ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to Voltage reference buffer output */
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE   VREFBUF_CSR_HIZ        /*!< VREF_plus pin is high impedance */
+
+#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__)  (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
+                                                      ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
+
+#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__)  (((__VALUE__) > 0UL) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
+
+/**
+  * @}
+  */
+
+#if !defined(SYSCFG_PMCR_BOOSTEN)
+/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
+  * @{
+  */
+
+/** @brief  Fast-mode Plus driving capability on a specific GPIO
+  */
+#define SYSCFG_FASTMODEPLUS_PB6        SYSCFG_PMCR_I2C_PB6_FMP  /*!< Enable Fast-mode Plus on PB6 */
+#define SYSCFG_FASTMODEPLUS_PB7        SYSCFG_PMCR_I2C_PB7_FMP  /*!< Enable Fast-mode Plus on PB7 */
+#define SYSCFG_FASTMODEPLUS_PB8        SYSCFG_PMCR_I2C_PB8_FMP  /*!< Enable Fast-mode Plus on PB8 */
+#define SYSCFG_FASTMODEPLUS_PB9        SYSCFG_PMCR_I2C_PB9_FMP  /*!< Enable Fast-mode Plus on PB9 */
+
+#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
+
+#endif /* ! SYSCFG_PMCR_BOOSTEN */
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_Ethernet_Config  Ethernet Config
+  * @{
+  */
+#define SYSCFG_ETH_MII                      ((uint32_t)0x00000000)  /*!< Select the Media Independent Interface */
+#define SYSCFG_ETH_RMII                     SYSCFG_PMCR_EPIS_SEL_2  /*!< Select the Reduced Media Independent Interface */
+
+#define IS_SYSCFG_ETHERNET_CONFIG(CONFIG) (((CONFIG) == SYSCFG_ETH_MII)        || \
+                                          ((CONFIG) == SYSCFG_ETH_RMII))
+
+/**
+  * @}
+  */
+
+
+/** @defgroup SYSCFG_Analog_Switch_Config  Analog Switch Config
+  * @{
+  */
+#define SYSCFG_SWITCH_PA0                       SYSCFG_PMCR_PA0SO  /*!< Select PA0 analog switch */
+#define SYSCFG_SWITCH_PA1                       SYSCFG_PMCR_PA1SO  /*!< Select PA1 analog switch */
+#define SYSCFG_SWITCH_PC2                       SYSCFG_PMCR_PC2SO  /*!< Select PC2 analog switch */
+#define SYSCFG_SWITCH_PC3                       SYSCFG_PMCR_PC3SO  /*!< Select PC3 analog switch */
+
+
+#define IS_SYSCFG_ANALOG_SWITCH(SWITCH)    ((((SWITCH) & SYSCFG_SWITCH_PA0) == SYSCFG_SWITCH_PA0)|| \
+                                           (((SWITCH) & SYSCFG_SWITCH_PA1) == SYSCFG_SWITCH_PA1) || \
+                                           (((SWITCH) & SYSCFG_SWITCH_PC2) == SYSCFG_SWITCH_PC2) || \
+                                           (((SWITCH) & SYSCFG_SWITCH_PC3) == SYSCFG_SWITCH_PC3))
+
+
+#define SYSCFG_SWITCH_PA0_OPEN                       SYSCFG_PMCR_PA0SO       /*!< PA0 analog switch opened */
+#define SYSCFG_SWITCH_PA0_CLOSE                      ((uint32_t)0x00000000)  /*!< PA0 analog switch closed */
+#define SYSCFG_SWITCH_PA1_OPEN                       SYSCFG_PMCR_PA1SO       /*!< PA1 analog switch opened */
+#define SYSCFG_SWITCH_PA1_CLOSE                      ((uint32_t)0x00000000)  /*!< PA1 analog switch closed*/
+#define SYSCFG_SWITCH_PC2_OPEN                       SYSCFG_PMCR_PC2SO       /*!< PC2 analog switch opened */
+#define SYSCFG_SWITCH_PC2_CLOSE                      ((uint32_t)0x00000000)  /*!< PC2 analog switch closed */
+#define SYSCFG_SWITCH_PC3_OPEN                       SYSCFG_PMCR_PC3SO       /*!< PC3 analog switch opened */
+#define SYSCFG_SWITCH_PC3_CLOSE                      ((uint32_t)0x00000000)  /*!< PC3 analog switch closed */
+
+#define IS_SYSCFG_SWITCH_STATE(STATE)      ((((STATE) & SYSCFG_SWITCH_PA0_OPEN) == SYSCFG_SWITCH_PA0_OPEN)    || \
+                                           (((STATE) & SYSCFG_SWITCH_PA0_CLOSE) == SYSCFG_SWITCH_PA0_CLOSE)   || \
+                                           (((STATE) & SYSCFG_SWITCH_PA1_OPEN) == SYSCFG_SWITCH_PA1_OPEN)     || \
+                                           (((STATE) & SYSCFG_SWITCH_PA1_CLOSE) == SYSCFG_SWITCH_PA1_CLOSE)   || \
+                                           (((STATE) & SYSCFG_SWITCH_PC2_OPEN) == SYSCFG_SWITCH_PC2_OPEN)     || \
+                                           (((STATE) & SYSCFG_SWITCH_PC2_CLOSE) == SYSCFG_SWITCH_PC2_CLOSE)   || \
+                                           (((STATE) & SYSCFG_SWITCH_PC3_OPEN) == SYSCFG_SWITCH_PC3_OPEN)     || \
+                                           (((STATE) & SYSCFG_SWITCH_PC3_CLOSE) == SYSCFG_SWITCH_PC3_CLOSE))
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_Boot_Config  Boot Config
+  * @{
+  */
+#define SYSCFG_BOOT_ADDR0                    ((uint32_t)0x00000000)  /*!< Select Boot address0 */
+#define SYSCFG_BOOT_ADDR1                    ((uint32_t)0x00000001)  /*!< Select Boot address1 */
+
+#define IS_SYSCFG_BOOT_REGISTER(REGISTER) (((REGISTER) == SYSCFG_BOOT_ADDR0)|| \
+                                          ((REGISTER) == SYSCFG_BOOT_ADDR1))
+
+#define IS_SYSCFG_BOOT_ADDRESS(ADDRESS) ((ADDRESS) < PERIPH_BASE)
+
+/**
+  * @}
+  */
+
+
+/** @defgroup SYSCFG_IOCompenstionCell_Config  IOCompenstionCell Config
+  * @{
+  */
+#define SYSCFG_CELL_CODE                    ((uint32_t)0x00000000)  /*!< Select Code from the cell */
+#define SYSCFG_REGISTER_CODE                 SYSCFG_CCCSR_CS        /*!< Code from the SYSCFG compensation cell code register */
+
+#define IS_SYSCFG_CODE_SELECT(SELECT) (((SELECT) == SYSCFG_CELL_CODE)|| \
+                                        ((SELECT) == SYSCFG_REGISTER_CODE))
+
+#define IS_SYSCFG_CODE_CONFIG(CONFIG) ((CONFIG) < (0x10UL))
+
+/**
+  * @}
+  */
+
+
+
+
+/** @defgroup EXTI_Event_Input_Config  Event Input Config
+  * @{
+  */
+
+#define EXTI_MODE_IT          ((uint32_t)0x00010000)
+#define EXTI_MODE_EVT         ((uint32_t)0x00020000)
+#define EXTI_RISING_EDGE      ((uint32_t)0x00100000)
+#define EXTI_FALLING_EDGE     ((uint32_t)0x00200000)
+
+#define IS_EXTI_EDGE_LINE(EDGE) (((EDGE) == EXTI_RISING_EDGE) || ((EDGE) == EXTI_FALLING_EDGE))
+#define IS_EXTI_MODE_LINE(MODE) (((MODE) == EXTI_MODE_IT) || ((MODE) == EXTI_MODE_EVT))
+
+#define EXTI_LINE0       ((uint32_t)0x00)  /*!< External interrupt LINE 0  */
+#define EXTI_LINE1       ((uint32_t)0x01)  /*!< External interrupt LINE 1  */
+#define EXTI_LINE2       ((uint32_t)0x02)  /*!< External interrupt LINE 2  */
+#define EXTI_LINE3       ((uint32_t)0x03)  /*!< External interrupt LINE 3  */
+#define EXTI_LINE4       ((uint32_t)0x04)  /*!< External interrupt LINE 4  */
+#define EXTI_LINE5       ((uint32_t)0x05)  /*!< External interrupt LINE 5  */
+#define EXTI_LINE6       ((uint32_t)0x06)  /*!< External interrupt LINE 6  */
+#define EXTI_LINE7       ((uint32_t)0x07)  /*!< External interrupt LINE 7  */
+#define EXTI_LINE8       ((uint32_t)0x08)  /*!< External interrupt LINE 8  */
+#define EXTI_LINE9       ((uint32_t)0x09)  /*!< External interrupt LINE 9  */
+#define EXTI_LINE10      ((uint32_t)0x0A)  /*!< External interrupt LINE 10 */
+#define EXTI_LINE11      ((uint32_t)0x0B)  /*!< External interrupt LINE 11 */
+#define EXTI_LINE12      ((uint32_t)0x0C)  /*!< External interrupt LINE 12 */
+#define EXTI_LINE13      ((uint32_t)0x0D)  /*!< External interrupt LINE 13 */
+#define EXTI_LINE14      ((uint32_t)0x0E)  /*!< External interrupt LINE 14 */
+#define EXTI_LINE15      ((uint32_t)0x0F)  /*!< External interrupt LINE 15 */
+#define EXTI_LINE16      ((uint32_t)0x10)
+#define EXTI_LINE17      ((uint32_t)0x11)
+#define EXTI_LINE18      ((uint32_t)0x12)
+#define EXTI_LINE19      ((uint32_t)0x13)
+#define EXTI_LINE20      ((uint32_t)0x14)
+#define EXTI_LINE21      ((uint32_t)0x15)
+#define EXTI_LINE22      ((uint32_t)0x16)
+#define EXTI_LINE23      ((uint32_t)0x17)
+#define EXTI_LINE24      ((uint32_t)0x18)
+#define EXTI_LINE25      ((uint32_t)0x19)
+#define EXTI_LINE26      ((uint32_t)0x1A)
+#define EXTI_LINE27      ((uint32_t)0x1B)
+#define EXTI_LINE28      ((uint32_t)0x1C)
+#define EXTI_LINE29      ((uint32_t)0x1D)
+#define EXTI_LINE30      ((uint32_t)0x1E)
+#define EXTI_LINE31      ((uint32_t)0x1F)
+#define EXTI_LINE32      ((uint32_t)0x20)
+#define EXTI_LINE33      ((uint32_t)0x21)
+#define EXTI_LINE34      ((uint32_t)0x22)
+#define EXTI_LINE35      ((uint32_t)0x23)
+#define EXTI_LINE36      ((uint32_t)0x24)
+#define EXTI_LINE37      ((uint32_t)0x25)
+#define EXTI_LINE38      ((uint32_t)0x26)
+#define EXTI_LINE39      ((uint32_t)0x27)
+
+#define EXTI_LINE40      ((uint32_t)0x28)
+#define EXTI_LINE41      ((uint32_t)0x29)
+#define EXTI_LINE42      ((uint32_t)0x2A)
+#define EXTI_LINE43      ((uint32_t)0x2B)
+#define EXTI_LINE44      ((uint32_t)0x2C)  /* Not available in all family lines */
+/* EXTI_LINE45 Reserved */
+#if defined(DUAL_CORE)
+#define EXTI_LINE46      ((uint32_t)0x2E)
+#else
+/* EXTI_LINE46 Reserved */
+#endif /* DUAL_CORE */
+#define EXTI_LINE47      ((uint32_t)0x2F)
+#define EXTI_LINE48      ((uint32_t)0x30)
+#define EXTI_LINE49      ((uint32_t)0x31)
+#define EXTI_LINE50      ((uint32_t)0x32)
+#define EXTI_LINE51      ((uint32_t)0x33)
+#define EXTI_LINE52      ((uint32_t)0x34)
+#define EXTI_LINE53      ((uint32_t)0x35)
+#define EXTI_LINE54      ((uint32_t)0x36)
+#define EXTI_LINE55      ((uint32_t)0x37)
+#define EXTI_LINE56      ((uint32_t)0x38)
+#define EXTI_LINE57      ((uint32_t)0x39)
+#define EXTI_LINE58      ((uint32_t)0x3A)
+#define EXTI_LINE59      ((uint32_t)0x3B)
+#define EXTI_LINE60      ((uint32_t)0x3C)
+#define EXTI_LINE61      ((uint32_t)0x3D)
+#define EXTI_LINE62      ((uint32_t)0x3E)
+#define EXTI_LINE63      ((uint32_t)0x3F)
+#define EXTI_LINE64      ((uint32_t)0x40)
+#define EXTI_LINE65      ((uint32_t)0x41)
+#define EXTI_LINE66      ((uint32_t)0x42)
+#define EXTI_LINE67      ((uint32_t)0x43)
+#define EXTI_LINE68      ((uint32_t)0x44)
+#define EXTI_LINE69      ((uint32_t)0x45)
+#define EXTI_LINE70      ((uint32_t)0x46)
+#define EXTI_LINE71      ((uint32_t)0x47)
+#define EXTI_LINE72      ((uint32_t)0x48)
+#define EXTI_LINE73      ((uint32_t)0x49)
+#define EXTI_LINE74      ((uint32_t)0x4A)
+#define EXTI_LINE75      ((uint32_t)0x4B)  /* Not available in all family lines */
+#define EXTI_LINE76      ((uint32_t)0x4C)  /* Not available in all family lines */
+#if defined(DUAL_CORE)
+#define EXTI_LINE77      ((uint32_t)0x4D)
+#define EXTI_LINE78      ((uint32_t)0x4E)
+#define EXTI_LINE79      ((uint32_t)0x4F)
+#define EXTI_LINE80      ((uint32_t)0x50)
+#else
+/* EXTI_LINE77 Reserved */
+/* EXTI_LINE78 Reserved */
+/* EXTI_LINE79 Reserved */
+/* EXTI_LINE80 Reserved */
+#endif /* DUAL_CORE */
+/* EXTI_LINE81   Reserved */
+#if defined(DUAL_CORE)
+#define EXTI_LINE82      ((uint32_t)0x52)
+#else
+/* EXTI_LINE82 Reserved */
+#endif /* DUAL_CORE */
+/* EXTI_LINE83   Reserved */
+#if defined(DUAL_CORE)
+#define EXTI_LINE84      ((uint32_t)0x54)
+#else
+/* EXTI_LINE84 Reserved */
+#endif /* DUAL_CORE */
+#define EXTI_LINE85      ((uint32_t)0x55)
+#define EXTI_LINE86      ((uint32_t)0x56)  /* Not available in all family lines */
+#define EXTI_LINE87      ((uint32_t)0x57)
+#define EXTI_LINE88      ((uint32_t)0x58)  /* Not available in all family lines */
+
+#if defined(DUAL_CORE)
+#define IS_HAL_EXTI_CONFIG_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \
+                                ((LINE) == EXTI_LINE2)  || ((LINE) == EXTI_LINE3)   || \
+                                ((LINE) == EXTI_LINE4)  || ((LINE) == EXTI_LINE5)   || \
+                                ((LINE) == EXTI_LINE6)  || ((LINE) == EXTI_LINE7)   || \
+                                ((LINE) == EXTI_LINE8)  || ((LINE) == EXTI_LINE9)   || \
+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11)  || \
+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13)  || \
+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15)  || \
+                                ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17)  || \
+                                ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19)  || \
+                                ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21)  || \
+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE51)  || \
+                                ((LINE) == EXTI_LINE82) || ((LINE) == EXTI_LINE84)  || \
+                                ((LINE) == EXTI_LINE85) || ((LINE) == EXTI_LINE86))
+#else
+#define IS_HAL_EXTI_CONFIG_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1)|| \
+                                ((LINE) == EXTI_LINE2)  || ((LINE) == EXTI_LINE3)   || \
+                                ((LINE) == EXTI_LINE4)  || ((LINE) == EXTI_LINE5)   || \
+                                ((LINE) == EXTI_LINE6)  || ((LINE) == EXTI_LINE7)   || \
+                                ((LINE) == EXTI_LINE8)  || ((LINE) == EXTI_LINE9)   || \
+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
+                                ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
+                                ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
+                                ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE51) || \
+                                ((LINE) == EXTI_LINE85) || ((LINE) == EXTI_LINE86))
+#endif /* DUAL_CORE */
+
+#if defined(DUAL_CORE)
+#define IS_EXTI_ALL_LINE(LINE) (((LINE) == EXTI_LINE0)  || ((LINE) == EXTI_LINE1)  || \
+                                ((LINE) == EXTI_LINE2)  || ((LINE) == EXTI_LINE3)  || \
+                                ((LINE) == EXTI_LINE4)  || ((LINE) == EXTI_LINE5)  || \
+                                ((LINE) == EXTI_LINE6)  || ((LINE) == EXTI_LINE7)  || \
+                                ((LINE) == EXTI_LINE8)  || ((LINE) == EXTI_LINE9)  || \
+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
+                                ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
+                                ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
+                                ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
+                                ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \
+                                ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \
+                                ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \
+                                ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \
+                                ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \
+                                ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \
+                                ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
+                                ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \
+                                ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \
+                                ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \
+                                ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \
+                                ((LINE) == EXTI_LINE44) || ((LINE) == EXTI_LINE46) || \
+                                ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \
+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
+                                ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
+                                ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \
+                                ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \
+                                ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \
+                                ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \
+                                ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \
+                                ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \
+                                ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \
+                                ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \
+                                ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \
+                                ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \
+                                ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \
+                                ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
+                                ((LINE) == EXTI_LINE77) || ((LINE) == EXTI_LINE79) || \
+                                ((LINE) == EXTI_LINE84) || ((LINE) == EXTI_LINE85) || \
+                                ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87) || \
+                                ((LINE) == EXTI_LINE78) || \
+                                ((LINE) == EXTI_LINE80) || ((LINE) == EXTI_LINE82))
+#else
+#define IS_EXTI_ALL_LINE(LINE) (((LINE) == EXTI_LINE0)  || ((LINE) == EXTI_LINE1)  || \
+                                ((LINE) == EXTI_LINE2)  || ((LINE) == EXTI_LINE3)  || \
+                                ((LINE) == EXTI_LINE4)  || ((LINE) == EXTI_LINE5)  || \
+                                ((LINE) == EXTI_LINE6)  || ((LINE) == EXTI_LINE7)  || \
+                                ((LINE) == EXTI_LINE8)  || ((LINE) == EXTI_LINE9)  || \
+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
+                                ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
+                                ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
+                                ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
+                                ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \
+                                ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \
+                                ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \
+                                ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \
+                                ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \
+                                ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \
+                                ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
+                                ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \
+                                ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \
+                                ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \
+                                ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \
+                                ((LINE) == EXTI_LINE44) || \
+                                ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \
+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
+                                ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
+                                ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \
+                                ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \
+                                ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \
+                                ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \
+                                ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \
+                                ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \
+                                ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \
+                                ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \
+                                ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \
+                                ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \
+                                ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \
+                                ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
+                                ((LINE) == EXTI_LINE85) || \
+                                ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87) || \
+                                ((LINE) == EXTI_LINE88))
+#endif /*DUAL_CORE*/
+
+#if defined(DUAL_CORE)
+#define IS_EXTI_D1_LINE(LINE) (((LINE) == EXTI_LINE0)  || ((LINE) == EXTI_LINE1)  || \
+                                ((LINE) == EXTI_LINE2)  || ((LINE) == EXTI_LINE3)  || \
+                                ((LINE) == EXTI_LINE4)  || ((LINE) == EXTI_LINE5)  || \
+                                ((LINE) == EXTI_LINE6)  || ((LINE) == EXTI_LINE7)  || \
+                                ((LINE) == EXTI_LINE8)  || ((LINE) == EXTI_LINE9)  || \
+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
+                                ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
+                                ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
+                                ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
+                                ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \
+                                ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \
+                                ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \
+                                ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \
+                                ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \
+                                ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \
+                                ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
+                                ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \
+                                ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \
+                                ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \
+                                ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \
+                                ((LINE) == EXTI_LINE44) || ((LINE) == EXTI_LINE46) || \
+                                ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \
+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
+                                ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
+                                ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \
+                                ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \
+                                ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \
+                                ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \
+                                ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \
+                                ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \
+                                ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \
+                                ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \
+                                ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \
+                                ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \
+                                ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \
+                                ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
+                                ((LINE) == EXTI_LINE77) || ((LINE) == EXTI_LINE79) || \
+                                ((LINE) == EXTI_LINE84) || ((LINE) == EXTI_LINE85) || \
+                                ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87))
+#else
+#define IS_EXTI_D1_LINE(LINE) (((LINE) == EXTI_LINE0)  || ((LINE) == EXTI_LINE1)  || \
+                                ((LINE) == EXTI_LINE2)  || ((LINE) == EXTI_LINE3)  || \
+                                ((LINE) == EXTI_LINE4)  || ((LINE) == EXTI_LINE5)  || \
+                                ((LINE) == EXTI_LINE6)  || ((LINE) == EXTI_LINE7)  || \
+                                ((LINE) == EXTI_LINE8)  || ((LINE) == EXTI_LINE9)  || \
+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
+                                ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
+                                ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
+                                ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
+                                ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \
+                                ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \
+                                ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \
+                                ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \
+                                ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \
+                                ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \
+                                ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
+                                ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \
+                                ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \
+                                ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \
+                                ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \
+                                ((LINE) == EXTI_LINE44) || \
+                                ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \
+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
+                                ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
+                                ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \
+                                ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \
+                                ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \
+                                ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \
+                                ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \
+                                ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \
+                                ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \
+                                ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \
+                                ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \
+                                ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \
+                                ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \
+                                ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
+                                ((LINE) == EXTI_LINE85) || \
+                                ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87) || \
+                                ((LINE) == EXTI_LINE88))
+#endif /*DUAL_CORE*/
+
+#if defined(DUAL_CORE)
+#define IS_EXTI_D2_LINE(LINE) (((LINE) == EXTI_LINE0)  || ((LINE) == EXTI_LINE1)    || \
+                                ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3)   || \
+                                ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5)   || \
+                                ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7)   || \
+                                ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9)   || \
+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
+                                ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
+                                ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
+                                ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
+                                ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \
+                                ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \
+                                ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \
+                                ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \
+                                ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \
+                                ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \
+                                ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
+                                ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \
+                                ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \
+                                ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \
+                                ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \
+                                ((LINE) == EXTI_LINE44) || ((LINE) == EXTI_LINE46) || \
+                                ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \
+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
+                                ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
+                                ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \
+                                ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \
+                                ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \
+                                ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \
+                                ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \
+                                ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \
+                                ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \
+                                ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \
+                                ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \
+                                ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \
+                                ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \
+                                ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
+                                ((LINE) == EXTI_LINE78) || ((LINE) == EXTI_LINE80) || \
+                                ((LINE) == EXTI_LINE82) || ((LINE) == EXTI_LINE85) || \
+                                ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87))
+#endif /*DUAL_CORE*/
+
+#if defined(DUAL_CORE)
+#define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1)    || \
+                                ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3)   || \
+                                ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5)   || \
+                                ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7)   || \
+                                ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9)   || \
+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
+                                ((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || \
+                                ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE25) || \
+                                ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
+                                ((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || \
+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
+                                ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
+                                ((LINE) == EXTI_LINE53))
+#elif (POWER_DOMAINS_NUMBER == 3U)
+#define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1)    || \
+                                ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3)   || \
+                                ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5)   || \
+                                ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7)   || \
+                                ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9)   || \
+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
+                                ((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || \
+                                ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE25) || \
+                                ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
+                                ((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || \
+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
+                                ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
+                                ((LINE) == EXTI_LINE53))
+#else
+#define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1)    || \
+                                ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3)   || \
+                                ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5)   || \
+                                ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7)   || \
+                                ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9)   || \
+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
+                                ((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || \
+                                ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE25) || \
+                                ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
+                                ((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || \
+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
+                                ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE88))
+#endif /*DUAL_CORE*/
+
+
+#define  BDMA_CH6_CLEAR           ((uint32_t)0x00000000)   /*!< BDMA ch6 event selected as D3 domain pendclear source*/
+#define  BDMA_CH7_CLEAR           ((uint32_t)0x00000001)   /*!< BDMA ch7 event selected as D3 domain pendclear source*/
+#if defined (LPTIM4)
+#define  LPTIM4_OUT_CLEAR         ((uint32_t)0x00000002)   /*!< LPTIM4 out selected as D3 domain pendclear source*/
+#else
+#define  LPTIM2_OUT_CLEAR         ((uint32_t)0x00000002)   /*!< LPTIM2 out selected as D3 domain pendclear source*/
+#endif /* LPTIM4 */
+#if defined (LPTIM5)
+#define  LPTIM5_OUT_CLEAR         ((uint32_t)0x00000003)   /*!< LPTIM5 out selected as D3 domain pendclear source*/
+#else
+#define  LPTIM3_OUT_CLEAR         ((uint32_t)0x00000003)   /*!< LPTIM3 out selected as D3 domain pendclear source*/
+#endif /* LPTIM5 */
+#if defined (LPTIM4) && defined (LPTIM5)
+#define IS_EXTI_D3_CLEAR(SOURCE) (((SOURCE) == BDMA_CH6_CLEAR) || ((SOURCE) == BDMA_CH7_CLEAR)    || \
+                                 ((SOURCE) == LPTIM4_OUT_CLEAR) || ((SOURCE) == LPTIM5_OUT_CLEAR))
+#else
+#define IS_EXTI_D3_CLEAR(SOURCE) (((SOURCE) == BDMA_CH6_CLEAR) || ((SOURCE) == BDMA_CH7_CLEAR)    || \
+                                 ((SOURCE) == LPTIM2_OUT_CLEAR) || ((SOURCE) == LPTIM3_OUT_CLEAR))
+#endif /* LPTIM4 LPTIM5 */
+/**
+  * @}
+  */
+
+
+/** @defgroup FMC_SwapBankMapping_Config  SwapBankMapping Config
+  * @{
+  */
+#define FMC_SWAPBMAP_DISABLE             (0x00000000U)
+#define FMC_SWAPBMAP_SDRAM_SRAM          FMC_BCR1_BMAP_0
+#define FMC_SWAPBMAP_SDRAMB2             FMC_BCR1_BMAP_1
+
+#define IS_FMC_SWAPBMAP_MODE(__MODE__) (((__MODE__) == FMC_SWAPBMAP_DISABLE)    || \
+                                        ((__MODE__) == FMC_SWAPBMAP_SDRAM_SRAM) || \
+                                        ((__MODE__) == FMC_SWAPBMAP_SDRAMB2))
+/**
+  * @}
+  */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup ART_Exported_Macros ART Exported Macros
+  * @{
+  */
+#if defined(DUAL_CORE)
+
+/** @brief  ART Enable Macro.
+  *         Enable the Cortex-M4 ART cache.
+  */
+#define __HAL_ART_ENABLE()   SET_BIT(ART->CTR, ART_CTR_EN)
+
+/** @brief  ART Disable Macro.
+  *         Disable the Cortex-M4 ART cache.
+  */
+#define __HAL_ART_DISABLE()   CLEAR_BIT(ART->CTR, ART_CTR_EN)
+
+/** @brief  ART Cache BaseAddress Config.
+  *         Configure the Cortex-M4 ART cache Base Address.
+  */
+#define __HAL_ART_CONFIG_BASE_ADDRESS(__BASE_ADDRESS__)   MODIFY_REG(ART->CTR, ART_CTR_PCACHEADDR, (((__BASE_ADDRESS__) >> 12U) & 0x000FFF00UL))
+
+#endif /* DUAL_CORE */
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
+  * @{
+  */
+
+/** @brief  SYSCFG Break AXIRAM double ECC lock.
+  *         Enable and lock the connection of AXIRAM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_AXISRAM_DBL_ECC_LOCK()     SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML)
+
+/** @brief  SYSCFG Break ITCM double ECC lock.
+  *         Enable and lock the connection of ITCM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_ITCM_DBL_ECC_LOCK()        SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_ITCML)
+
+/** @brief  SYSCFG Break DTCM double ECC lock.
+  *         Enable and lock the connection of DTCM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_DTCM_DBL_ECC_LOCK()        SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_DTCML)
+
+/** @brief  SYSCFG Break SRAM1 double ECC lock.
+  *         Enable and lock the connection of SRAM1 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_SRAM1_DBL_ECC_LOCK()       SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM1L)
+
+/** @brief  SYSCFG Break SRAM2 double ECC lock.
+  *         Enable and lock the connection of SRAM2 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_SRAM2_DBL_ECC_LOCK()       SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM2L)
+
+/** @brief  SYSCFG Break SRAM3 double ECC lock.
+  *         Enable and lock the connection of SRAM3 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_SRAM3_DBL_ECC_LOCK()       SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM3L)
+
+/** @brief  SYSCFG Break SRAM4 double ECC lock.
+  *         Enable and lock the connection of SRAM4 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_SRAM4_DBL_ECC_LOCK()       SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM4L)
+
+/** @brief  SYSCFG Break Backup SRAM double ECC lock.
+  *         Enable and lock the connection of Backup SRAM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_BKRAM_DBL_ECC_LOCK()       SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_BKRAML)
+
+/** @brief  SYSCFG Break Cortex-M7 Lockup lock.
+  *         Enable and lock the connection of Cortex-M7 LOCKUP output to TIM1/8/15/16/17 and HRTIMER Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_CM7_LOCKUP_LOCK()          SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_CM7L)
+
+/** @brief  SYSCFG Break FLASH double ECC lock.
+  *         Enable and lock the connection of Flash double ECC error connection to TIM1/8/15/16/17 and HRTIMER Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_FLASH_DBL_ECC_LOCK()       SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_FLASHL)
+
+/** @brief  SYSCFG Break PVD lock.
+  *         Enable and lock the PVD connection to Timer1/8/15/16/17 and HRTIMER Break input, as well as the PVDE and PLS[2:0] in the PWR_CR1 register.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_PVD_LOCK()                 SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_PVDL)
+
+#if defined(DUAL_CORE)
+/** @brief  SYSCFG Break Cortex-M4 Lockup lock.
+  *         Enable and lock the connection of Cortex-M4 LOCKUP output to TIM1/8/15/16/17 and HRTIMER Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_CM4_LOCKUP_LOCK()          SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_CM4L)
+#endif /* DUAL_CORE */
+
+#if !defined(SYSCFG_PMCR_BOOSTEN)
+/** @brief  Fast-mode Plus driving capability enable/disable macros
+  * @param __FASTMODEPLUS__  This parameter can be a value of :
+  *     @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6
+  *     @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7
+  *     @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8
+  *     @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9
+  */
+#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)  do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
+                                                                SET_BIT(SYSCFG->PMCR, (__FASTMODEPLUS__));\
+                                                               }while(0)
+
+#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
+                                                                CLEAR_BIT(SYSCFG->PMCR, (__FASTMODEPLUS__));\
+                                                               }while(0)
+
+#endif /* !SYSCFG_PMCR_BOOSTEN */
+/**
+  * @}
+  */
+
+/** @brief  Freeze/Unfreeze Peripherals in Debug mode
+  */
+#define __HAL_DBGMCU_FREEZE_WWDG1()          (DBGMCU->APB3FZ1 |= (DBGMCU_APB3FZ1_DBG_WWDG1))
+
+#define __HAL_DBGMCU_FREEZE_TIM2()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM2))
+#define __HAL_DBGMCU_FREEZE_TIM3()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM3))
+#define __HAL_DBGMCU_FREEZE_TIM4()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM4))
+#define __HAL_DBGMCU_FREEZE_TIM5()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM5))
+#define __HAL_DBGMCU_FREEZE_TIM6()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM6))
+#define __HAL_DBGMCU_FREEZE_TIM7()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM7))
+#define __HAL_DBGMCU_FREEZE_TIM12()          (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM12))
+#define __HAL_DBGMCU_FREEZE_TIM13()          (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM13))
+#define __HAL_DBGMCU_FREEZE_TIM14()          (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM14))
+#define __HAL_DBGMCU_FREEZE_LPTIM1()         (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_LPTIM1))
+#define __HAL_DBGMCU_FREEZE_I2C1()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C1))
+#define __HAL_DBGMCU_FREEZE_I2C2()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C2))
+#define __HAL_DBGMCU_FREEZE_I2C3()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C3))
+#define __HAL_DBGMCU_FREEZE_FDCAN()          (DBGMCU->APB1HFZ1 |= (DBGMCU_APB1HFZ1_DBG_FDCAN))
+
+
+#define __HAL_DBGMCU_FREEZE_TIM1()           (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM1))
+#define __HAL_DBGMCU_FREEZE_TIM8()           (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM8))
+#define __HAL_DBGMCU_FREEZE_TIM15()          (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM15))
+#define __HAL_DBGMCU_FREEZE_TIM16()          (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM16))
+#define __HAL_DBGMCU_FREEZE_TIM17()          (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM17))
+#define __HAL_DBGMCU_FREEZE_HRTIM()          (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_HRTIM))
+
+#define __HAL_DBGMCU_FREEZE_I2C4()           (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_I2C4))
+#define __HAL_DBGMCU_FREEZE_LPTIM2()         (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM2))
+#define __HAL_DBGMCU_FREEZE_LPTIM3()         (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM3))
+#define __HAL_DBGMCU_FREEZE_LPTIM4()         (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM4))
+#define __HAL_DBGMCU_FREEZE_LPTIM5()         (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM5))
+#define __HAL_DBGMCU_FREEZE_RTC()            (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_RTC))
+#define __HAL_DBGMCU_FREEZE_IWDG1()          (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_IWDG1))
+
+
+#define __HAL_DBGMCU_UnFreeze_WWDG1()          (DBGMCU->APB3FZ1  &= ~ (DBGMCU_APB3FZ1_DBG_WWDG1))
+
+#define __HAL_DBGMCU_UnFreeze_TIM2()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM2))
+#define __HAL_DBGMCU_UnFreeze_TIM3()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM3))
+#define __HAL_DBGMCU_UnFreeze_TIM4()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM4))
+#define __HAL_DBGMCU_UnFreeze_TIM5()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM5))
+#define __HAL_DBGMCU_UnFreeze_TIM6()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM6))
+#define __HAL_DBGMCU_UnFreeze_TIM7()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM7))
+#define __HAL_DBGMCU_UnFreeze_TIM12()          (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM12))
+#define __HAL_DBGMCU_UnFreeze_TIM13()          (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM13))
+#define __HAL_DBGMCU_UnFreeze_TIM14()          (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM14))
+#define __HAL_DBGMCU_UnFreeze_LPTIM1()         (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_LPTIM1))
+#define __HAL_DBGMCU_UnFreeze_I2C1()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_I2C1))
+#define __HAL_DBGMCU_UnFreeze_I2C2()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_I2C2))
+#define __HAL_DBGMCU_UnFreeze_I2C3()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_I2C3))
+#define __HAL_DBGMCU_UnFreeze_FDCAN()          (DBGMCU->APB1HFZ1  &= ~ (DBGMCU_APB1HFZ1_DBG_FDCAN))
+
+
+#define __HAL_DBGMCU_UnFreeze_TIM1()           (DBGMCU->APB2FZ1  &= ~ (DBGMCU_APB2FZ1_DBG_TIM1))
+#define __HAL_DBGMCU_UnFreeze_TIM8()           (DBGMCU->APB2FZ1  &= ~ (DBGMCU_APB2FZ1_DBG_TIM8))
+#define __HAL_DBGMCU_UnFreeze_TIM15()          (DBGMCU->APB2FZ1  &= ~ (DBGMCU_APB2FZ1_DBG_TIM15))
+#define __HAL_DBGMCU_UnFreeze_TIM16()          (DBGMCU->APB2FZ1  &= ~ (DBGMCU_APB2FZ1_DBG_TIM16))
+#define __HAL_DBGMCU_UnFreeze_TIM17()          (DBGMCU->APB2FZ1  &= ~ (DBGMCU_APB2FZ1_DBG_TIM17))
+#define __HAL_DBGMCU_UnFreeze_HRTIM()          (DBGMCU->APB2FZ1  &= ~ (DBGMCU_APB2FZ1_DBG_HRTIM))
+
+#define __HAL_DBGMCU_UnFreeze_I2C4()           (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_I2C4))
+#define __HAL_DBGMCU_UnFreeze_LPTIM2()         (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM2))
+#define __HAL_DBGMCU_UnFreeze_LPTIM3()         (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM3))
+#define __HAL_DBGMCU_UnFreeze_LPTIM4()         (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM4))
+#define __HAL_DBGMCU_UnFreeze_LPTIM5()         (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM5))
+#define __HAL_DBGMCU_UnFreeze_RTC()            (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_RTC))
+#define __HAL_DBGMCU_UnFreeze_IWDG1()          (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_IWDG1))
+
+
+#if defined(DUAL_CORE)
+#define __HAL_DBGMCU_FREEZE2_IWDG2()          (DBGMCU->APB4FZ2  |= (DBGMCU_APB4FZ2_DBG_IWDG2))
+#define __HAL_DBGMCU_FREEZE2_WWDG2()          (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_WWDG2))
+
+#define __HAL_DBGMCU_UnFreeze2_IWDG2()        (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_IWDG2))
+#define __HAL_DBGMCU_UnFreeze2_WWDG2()        (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_WWDG2))
+
+
+#define __HAL_DBGMCU_FREEZE2_WWDG1()          (DBGMCU->APB3FZ2 |= (DBGMCU_APB3FZ2_DBG_WWDG1))
+
+#define __HAL_DBGMCU_FREEZE2_TIM2()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM2))
+#define __HAL_DBGMCU_FREEZE2_TIM3()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM3))
+#define __HAL_DBGMCU_FREEZE2_TIM4()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM4))
+#define __HAL_DBGMCU_FREEZE2_TIM5()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM5))
+#define __HAL_DBGMCU_FREEZE2_TIM6()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM6))
+#define __HAL_DBGMCU_FREEZE2_TIM7()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM7))
+#define __HAL_DBGMCU_FREEZE2_TIM12()          (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM12))
+#define __HAL_DBGMCU_FREEZE2_TIM13()          (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM13))
+#define __HAL_DBGMCU_FREEZE2_TIM14()          (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM14))
+#define __HAL_DBGMCU_FREEZE2_LPTIM1()         (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_LPTIM1))
+#define __HAL_DBGMCU_FREEZE2_I2C1()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_I2C1))
+#define __HAL_DBGMCU_FREEZE2_I2C2()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_I2C2))
+#define __HAL_DBGMCU_FREEZE2_I2C3()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_I2C3))
+#define __HAL_DBGMCU_FREEZE2_FDCAN()          (DBGMCU->APB1HFZ2 |= (DBGMCU_APB1HFZ2_DBG_FDCAN))
+
+
+#define __HAL_DBGMCU_FREEZE2_TIM1()           (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM1))
+#define __HAL_DBGMCU_FREEZE2_TIM8()           (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM8))
+#define __HAL_DBGMCU_FREEZE2_TIM15()          (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM15))
+#define __HAL_DBGMCU_FREEZE2_TIM16()          (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM16))
+#define __HAL_DBGMCU_FREEZE2_TIM17()          (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM17))
+#define __HAL_DBGMCU_FREEZE2_HRTIM()          (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_HRTIM))
+
+#define __HAL_DBGMCU_FREEZE2_I2C4()           (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_I2C4))
+#define __HAL_DBGMCU_FREEZE2_LPTIM2()         (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM2))
+#define __HAL_DBGMCU_FREEZE2_LPTIM3()         (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM3))
+#define __HAL_DBGMCU_FREEZE2_LPTIM4()         (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM4))
+#define __HAL_DBGMCU_FREEZE2_LPTIM5()         (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM5))
+#define __HAL_DBGMCU_FREEZE2_RTC()            (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_RTC))
+#define __HAL_DBGMCU_FREEZE2_IWDG1()          (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_IWDG1))
+
+#define __HAL_DBGMCU_UnFreeze2_WWDG1()          (DBGMCU->APB3FZ2  &= ~ (DBGMCU_APB3FZ2_DBG_WWDG1))
+
+#define __HAL_DBGMCU_UnFreeze2_TIM2()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM2))
+#define __HAL_DBGMCU_UnFreeze2_TIM3()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM3))
+#define __HAL_DBGMCU_UnFreeze2_TIM4()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM4))
+#define __HAL_DBGMCU_UnFreeze2_TIM5()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM5))
+#define __HAL_DBGMCU_UnFreeze2_TIM6()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM6))
+#define __HAL_DBGMCU_UnFreeze2_TIM7()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM7))
+#define __HAL_DBGMCU_UnFreeze2_TIM12()          (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM12))
+#define __HAL_DBGMCU_UnFreeze2_TIM13()          (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM13))
+#define __HAL_DBGMCU_UnFreeze2_TIM14()          (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM14))
+#define __HAL_DBGMCU_UnFreeze2_LPTIM1()         (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_LPTIM1))
+#define __HAL_DBGMCU_UnFreeze2_I2C1()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_I2C1))
+#define __HAL_DBGMCU_UnFreeze2_I2C2()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_I2C2))
+#define __HAL_DBGMCU_UnFreeze2_I2C3()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_I2C3))
+#define __HAL_DBGMCU_UnFreeze2_FDCAN()          (DBGMCU->APB1HFZ2  &= ~ (DBGMCU_APB1HFZ2_DBG_FDCAN))
+
+
+#define __HAL_DBGMCU_UnFreeze2_TIM1()           (DBGMCU->APB2FZ2  &= ~ (DBGMCU_APB2FZ2_DBG_TIM1))
+#define __HAL_DBGMCU_UnFreeze2_TIM8()           (DBGMCU->APB2FZ2  &= ~ (DBGMCU_APB2FZ2_DBG_TIM8))
+#define __HAL_DBGMCU_UnFreeze2_TIM15()          (DBGMCU->APB2FZ2  &= ~ (DBGMCU_APB2FZ2_DBG_TIM15))
+#define __HAL_DBGMCU_UnFreeze2_TIM16()          (DBGMCU->APB2FZ2  &= ~ (DBGMCU_APB2FZ2_DBG_TIM16))
+#define __HAL_DBGMCU_UnFreeze2_TIM17()          (DBGMCU->APB2FZ2  &= ~ (DBGMCU_APB2FZ2_DBG_TIM17))
+#define __HAL_DBGMCU_UnFreeze2_HRTIM()          (DBGMCU->APB2FZ2  &= ~ (DBGMCU_APB2FZ2_DBG_HRTIM))
+
+#define __HAL_DBGMCU_UnFreeze2_I2C4()           (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_I2C4))
+#define __HAL_DBGMCU_UnFreeze2_LPTIM2()         (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM2))
+#define __HAL_DBGMCU_UnFreeze2_LPTIM3()         (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM3))
+#define __HAL_DBGMCU_UnFreeze2_LPTIM4()         (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM4))
+#define __HAL_DBGMCU_UnFreeze2_LPTIM5()         (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM5))
+#define __HAL_DBGMCU_UnFreeze2_RTC()            (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_RTC))
+#define __HAL_DBGMCU_UnFreeze2_IWDG1()          (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_IWDG1))
+
+#endif /*DUAL_CORE*/
+
+/** @defgroup HAL_Private_Macros HAL Private Macros
+  * @{
+  */
+#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ)  || \
+                           ((FREQ) == HAL_TICK_FREQ_100HZ) || \
+                           ((FREQ) == HAL_TICK_FREQ_1KHZ))
+/**
+  * @}
+  */
+
+/* Exported variables --------------------------------------------------------*/
+
+/** @addtogroup HAL_Exported_Variables
+  * @{
+  */
+extern __IO uint32_t uwTick;
+extern uint32_t uwTickPrio;
+extern HAL_TickFreqTypeDef uwTickFreq;
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization and de-initialization functions  ******************************/
+HAL_StatusTypeDef HAL_Init(void);
+HAL_StatusTypeDef HAL_DeInit(void);
+void HAL_MspInit(void);
+void HAL_MspDeInit(void);
+HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
+
+/* Peripheral Control functions  ************************************************/
+void HAL_IncTick(void);
+void HAL_Delay(uint32_t Delay);
+uint32_t HAL_GetTick(void);
+uint32_t HAL_GetTickPrio(void);
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
+HAL_TickFreqTypeDef HAL_GetTickFreq(void);
+void HAL_SuspendTick(void);
+void HAL_ResumeTick(void);
+uint32_t HAL_GetHalVersion(void);
+uint32_t HAL_GetREVID(void);
+uint32_t HAL_GetDEVID(void);
+uint32_t HAL_GetUIDw0(void);
+uint32_t HAL_GetUIDw1(void);
+uint32_t HAL_GetUIDw2(void);
+#if defined(SYSCFG_PMCR_EPIS_SEL)
+void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface);
+#endif /* SYSCFG_PMCR_EPIS_SEL */
+void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState );
+#if defined(SYSCFG_PMCR_BOOSTEN)
+void HAL_SYSCFG_EnableBOOST(void);
+void HAL_SYSCFG_DisableBOOST(void);
+#endif /* SYSCFG_PMCR_BOOSTEN */
+
+#if defined (SYSCFG_UR2_BOOT_ADD0) ||  defined (SYSCFG_UR2_BCM7_ADD0)
+void HAL_SYSCFG_CM7BootAddConfig(uint32_t BootRegister, uint32_t BootAddress);
+#endif /* SYSCFG_UR2_BOOT_ADD0 || SYSCFG_UR2_BCM7_ADD0*/
+
+#if defined(DUAL_CORE)
+void HAL_SYSCFG_CM4BootAddConfig(uint32_t BootRegister, uint32_t BootAddress);
+void HAL_SYSCFG_EnableCM7BOOT(void);
+void HAL_SYSCFG_DisableCM7BOOT(void);
+void HAL_SYSCFG_EnableCM4BOOT(void);
+void HAL_SYSCFG_DisableCM4BOOT(void);
+#endif /*DUAL_CORE*/
+void HAL_EnableCompensationCell(void);
+void HAL_DisableCompensationCell(void);
+void HAL_SYSCFG_EnableIOSpeedOptimize(void);
+void HAL_SYSCFG_DisableIOSpeedOptimize(void);
+void HAL_SYSCFG_CompensationCodeSelect(uint32_t SYSCFG_CompCode);
+void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode);
+#if defined(SYSCFG_CCCR_NCC_MMC)
+void HAL_SYSCFG_VDDMMC_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode);
+#endif /* SYSCFG_CCCR_NCC_MMC */
+void HAL_EnableDBGSleepMode(void);
+void HAL_DisableDBGSleepMode(void);
+void HAL_EnableDBGStopMode(void);
+void HAL_DisableDBGStopMode(void);
+void HAL_EnableDBGStandbyMode(void);
+void HAL_DisableDBGStandbyMode(void);
+#if defined(DUAL_CORE)
+void HAL_EnableDomain2DBGSleepMode(void);
+void HAL_DisableDomain2DBGSleepMode(void);
+void HAL_EnableDomain2DBGStopMode(void);
+void HAL_DisableDomain2DBGStopMode(void);
+void HAL_EnableDomain2DBGStandbyMode(void);
+void HAL_DisableDomain2DBGStandbyMode(void);
+#endif /*DUAL_CORE*/
+void HAL_EnableDomain3DBGStopMode(void);
+void HAL_DisableDomain3DBGStopMode(void);
+void HAL_EnableDomain3DBGStandbyMode(void);
+void HAL_DisableDomain3DBGStandbyMode(void);
+void HAL_EXTI_EdgeConfig(uint32_t EXTI_Line , uint32_t EXTI_Edge );
+void HAL_EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
+#if defined(DUAL_CORE)
+void HAL_EXTI_D2_ClearFlag(uint32_t EXTI_Line);
+#endif /*DUAL_CORE*/
+void HAL_EXTI_D1_ClearFlag(uint32_t EXTI_Line);
+void HAL_EXTI_D1_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode,  uint32_t EXTI_LineCmd);
+#if defined(DUAL_CORE)
+void HAL_EXTI_D2_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode,  uint32_t EXTI_LineCmd);
+#endif /*DUAL_CORE*/
+void HAL_EXTI_D3_EventInputConfig(uint32_t EXTI_Line, uint32_t EXTI_LineCmd , uint32_t EXTI_ClearSrc);
+void HAL_SetFMCMemorySwappingConfig(uint32_t BankMapConfig);
+uint32_t HAL_GetFMCMemorySwappingConfig(void);
+void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
+void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
+void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
+HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
+void HAL_SYSCFG_DisableVREFBUF(void);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h
new file mode 100644
index 00000000..4eca4390
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h
@@ -0,0 +1,461 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_cortex.h
+  * @author  MCD Application Team
+  * @brief   Header file of CORTEX HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_CORTEX_H
+#define STM32H7xx_HAL_CORTEX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup CORTEX
+  * @{
+  */
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Types Cortex Exported Types
+  * @{
+  */
+
+#if (__MPU_PRESENT == 1)
+/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
+  * @brief  MPU Region initialization structure
+  * @{
+  */
+typedef struct
+{
+  uint8_t                Enable;                /*!< Specifies the status of the region.
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */
+  uint8_t                Number;                /*!< Specifies the number of the region to protect.
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */
+  uint32_t               BaseAddress;           /*!< Specifies the base address of the region to protect.                           */
+  uint8_t                Size;                  /*!< Specifies the size of the region to protect.
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Size                   */
+  uint8_t                SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable.
+                                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */
+  uint8_t                TypeExtField;          /*!< Specifies the TEX field level.
+                                                     This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                    */
+  uint8_t                AccessPermission;      /*!< Specifies the region access permission type.
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */
+  uint8_t                DisableExec;           /*!< Specifies the instruction access status.
+                                                     This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */
+  uint8_t                IsShareable;           /*!< Specifies the shareability status of the protected region.
+                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */
+  uint8_t                IsCacheable;           /*!< Specifies the cacheable status of the region protected.
+                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable              */
+  uint8_t                IsBufferable;          /*!< Specifies the bufferable status of the protected region.
+                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable             */
+}MPU_Region_InitTypeDef;
+/**
+  * @}
+  */
+#endif /* __MPU_PRESENT */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
+  * @{
+  */
+
+/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
+  * @{
+  */
+#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority
+                                                                 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority
+                                                                 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority
+                                                                 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority
+                                                                 1 bits for subpriority */
+#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority
+                                                                 0 bits for subpriority */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
+  * @{
+  */
+#define SYSTICK_CLKSOURCE_HCLK_DIV8    ((uint32_t)0x00000000)
+#define SYSTICK_CLKSOURCE_HCLK         ((uint32_t)0x00000004)
+
+/**
+  * @}
+  */
+
+#if (__MPU_PRESENT == 1)
+/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
+  * @{
+  */
+#define  MPU_HFNMI_PRIVDEF_NONE      ((uint32_t)0x00000000)
+#define  MPU_HARDFAULT_NMI           ((uint32_t)0x00000002)
+#define  MPU_PRIVILEGED_DEFAULT      ((uint32_t)0x00000004)
+#define  MPU_HFNMI_PRIVDEF           ((uint32_t)0x00000006)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
+  * @{
+  */
+#define  MPU_REGION_ENABLE     ((uint8_t)0x01)
+#define  MPU_REGION_DISABLE    ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
+  * @{
+  */
+#define  MPU_INSTRUCTION_ACCESS_ENABLE      ((uint8_t)0x00)
+#define  MPU_INSTRUCTION_ACCESS_DISABLE     ((uint8_t)0x01)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
+  * @{
+  */
+#define  MPU_ACCESS_SHAREABLE        ((uint8_t)0x01)
+#define  MPU_ACCESS_NOT_SHAREABLE    ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
+  * @{
+  */
+#define  MPU_ACCESS_CACHEABLE         ((uint8_t)0x01)
+#define  MPU_ACCESS_NOT_CACHEABLE     ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
+  * @{
+  */
+#define  MPU_ACCESS_BUFFERABLE         ((uint8_t)0x01)
+#define  MPU_ACCESS_NOT_BUFFERABLE     ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
+  * @{
+  */
+#define  MPU_TEX_LEVEL0    ((uint8_t)0x00)
+#define  MPU_TEX_LEVEL1    ((uint8_t)0x01)
+#define  MPU_TEX_LEVEL2    ((uint8_t)0x02)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
+  * @{
+  */
+#define   MPU_REGION_SIZE_32B      ((uint8_t)0x04)
+#define   MPU_REGION_SIZE_64B      ((uint8_t)0x05)
+#define   MPU_REGION_SIZE_128B     ((uint8_t)0x06)
+#define   MPU_REGION_SIZE_256B     ((uint8_t)0x07)
+#define   MPU_REGION_SIZE_512B     ((uint8_t)0x08)
+#define   MPU_REGION_SIZE_1KB      ((uint8_t)0x09)
+#define   MPU_REGION_SIZE_2KB      ((uint8_t)0x0A)
+#define   MPU_REGION_SIZE_4KB      ((uint8_t)0x0B)
+#define   MPU_REGION_SIZE_8KB      ((uint8_t)0x0C)
+#define   MPU_REGION_SIZE_16KB     ((uint8_t)0x0D)
+#define   MPU_REGION_SIZE_32KB     ((uint8_t)0x0E)
+#define   MPU_REGION_SIZE_64KB     ((uint8_t)0x0F)
+#define   MPU_REGION_SIZE_128KB    ((uint8_t)0x10)
+#define   MPU_REGION_SIZE_256KB    ((uint8_t)0x11)
+#define   MPU_REGION_SIZE_512KB    ((uint8_t)0x12)
+#define   MPU_REGION_SIZE_1MB      ((uint8_t)0x13)
+#define   MPU_REGION_SIZE_2MB      ((uint8_t)0x14)
+#define   MPU_REGION_SIZE_4MB      ((uint8_t)0x15)
+#define   MPU_REGION_SIZE_8MB      ((uint8_t)0x16)
+#define   MPU_REGION_SIZE_16MB     ((uint8_t)0x17)
+#define   MPU_REGION_SIZE_32MB     ((uint8_t)0x18)
+#define   MPU_REGION_SIZE_64MB     ((uint8_t)0x19)
+#define   MPU_REGION_SIZE_128MB    ((uint8_t)0x1A)
+#define   MPU_REGION_SIZE_256MB    ((uint8_t)0x1B)
+#define   MPU_REGION_SIZE_512MB    ((uint8_t)0x1C)
+#define   MPU_REGION_SIZE_1GB      ((uint8_t)0x1D)
+#define   MPU_REGION_SIZE_2GB      ((uint8_t)0x1E)
+#define   MPU_REGION_SIZE_4GB      ((uint8_t)0x1F)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
+  * @{
+  */
+#define  MPU_REGION_NO_ACCESS      ((uint8_t)0x00)
+#define  MPU_REGION_PRIV_RW        ((uint8_t)0x01)
+#define  MPU_REGION_PRIV_RW_URO    ((uint8_t)0x02)
+#define  MPU_REGION_FULL_ACCESS    ((uint8_t)0x03)
+#define  MPU_REGION_PRIV_RO        ((uint8_t)0x05)
+#define  MPU_REGION_PRIV_RO_URO    ((uint8_t)0x06)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
+  * @{
+  */
+#define  MPU_REGION_NUMBER0    ((uint8_t)0x00)
+#define  MPU_REGION_NUMBER1    ((uint8_t)0x01)
+#define  MPU_REGION_NUMBER2    ((uint8_t)0x02)
+#define  MPU_REGION_NUMBER3    ((uint8_t)0x03)
+#define  MPU_REGION_NUMBER4    ((uint8_t)0x04)
+#define  MPU_REGION_NUMBER5    ((uint8_t)0x05)
+#define  MPU_REGION_NUMBER6    ((uint8_t)0x06)
+#define  MPU_REGION_NUMBER7    ((uint8_t)0x07)
+#if !defined(CORE_CM4)
+#define  MPU_REGION_NUMBER8    ((uint8_t)0x08)
+#define  MPU_REGION_NUMBER9    ((uint8_t)0x09)
+#define  MPU_REGION_NUMBER10   ((uint8_t)0x0A)
+#define  MPU_REGION_NUMBER11   ((uint8_t)0x0B)
+#define  MPU_REGION_NUMBER12   ((uint8_t)0x0C)
+#define  MPU_REGION_NUMBER13   ((uint8_t)0x0D)
+#define  MPU_REGION_NUMBER14   ((uint8_t)0x0E)
+#define  MPU_REGION_NUMBER15   ((uint8_t)0x0F)
+#endif /* !defined(CORE_CM4) */
+
+/**
+  * @}
+  */
+#endif /* __MPU_PRESENT */
+
+/**
+  * @}
+  */
+
+
+/* Exported Macros -----------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+
+/** @defgroup CORTEX_CPU_Identifier CORTEX_CPU_Identifier
+  * @{
+  */
+#define CM7_CPUID        ((uint32_t)0x00000003)
+
+#if defined(DUAL_CORE)
+#define CM4_CPUID        ((uint32_t)0x00000001)
+#endif /*DUAL_CORE*/
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CORTEX_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup CORTEX_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SystemReset(void);
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
+/**
+  * @}
+  */
+
+/** @addtogroup CORTEX_Exported_Functions_Group2
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+#if (__MPU_PRESENT == 1)
+void HAL_MPU_Enable(uint32_t MPU_Control);
+void HAL_MPU_Disable(void);
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
+#endif /* __MPU_PRESENT */
+uint32_t HAL_NVIC_GetPriorityGrouping(void);
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
+void HAL_SYSTICK_IRQHandler(void);
+void HAL_SYSTICK_Callback(void);
+uint32_t HAL_GetCurrentCPUID(void);
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
+  * @{
+  */
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_1) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_2) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_3) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10UL)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY)         ((PRIORITY) < 0x10UL)
+
+#define IS_NVIC_DEVICE_IRQ(IRQ)                (((int32_t)IRQ) >= 0x00)
+
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
+                                       ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
+
+#if (__MPU_PRESENT == 1)
+#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
+                                     ((STATE) == MPU_REGION_DISABLE))
+
+#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
+                                          ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
+
+#define IS_MPU_ACCESS_SHAREABLE(STATE)   (((STATE) == MPU_ACCESS_SHAREABLE) || \
+                                          ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
+
+#define IS_MPU_ACCESS_CACHEABLE(STATE)   (((STATE) == MPU_ACCESS_CACHEABLE) || \
+                                          ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
+
+#define IS_MPU_ACCESS_BUFFERABLE(STATE)   (((STATE) == MPU_ACCESS_BUFFERABLE) || \
+                                          ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
+
+#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0)  || \
+                                ((TYPE) == MPU_TEX_LEVEL1)  || \
+                                ((TYPE) == MPU_TEX_LEVEL2))
+
+#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS)   || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RW)     || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
+                                                  ((TYPE) == MPU_REGION_FULL_ACCESS) || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RO)     || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RO_URO))
+
+#if !defined(CORE_CM4)
+#define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER1)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER2)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER3)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER4)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER5)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER6)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER7)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER8)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER9)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER10) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER11) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER12) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER13) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER14) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER15))
+#else
+#define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER1)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER2)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER3)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER4)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER5)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER6)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER7))
+#endif /* !defined(CORE_CM4) */
+
+#define IS_MPU_REGION_SIZE(SIZE)    (((SIZE) == MPU_REGION_SIZE_32B)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_64B)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_128B)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_256B)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_512B)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_1KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_2KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_4KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_8KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_16KB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_32KB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_64KB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_128KB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_256KB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_512KB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_1MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_2MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_4MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_8MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_16MB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_32MB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_64MB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_128MB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_256MB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_512MB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_1GB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_2GB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_4GB))
+
+#define IS_MPU_SUB_REGION_DISABLE(SUBREGION)  ((SUBREGION) < (uint16_t)0x00FF)
+#endif /* __MPU_PRESENT */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_CORTEX_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h
new file mode 100644
index 00000000..fce605de
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h
@@ -0,0 +1,188 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_def.h
+  * @author  MCD Application Team
+  * @brief   This file contains HAL common defines, enumeration, macros and
+  *          structures definitions.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_DEF
+#define STM32H7xx_HAL_DEF
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+#include "Legacy/stm32_hal_legacy.h"
+#include <stddef.h>
+#include <math.h>
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+  * @brief  HAL Status structures definition
+  */
+typedef enum
+{
+  HAL_OK       = 0x00,
+  HAL_ERROR    = 0x01,
+  HAL_BUSY     = 0x02,
+  HAL_TIMEOUT  = 0x03
+} HAL_StatusTypeDef;
+
+/**
+  * @brief  HAL Lock structures definition
+  */
+typedef enum
+{
+  HAL_UNLOCKED = 0x00,
+  HAL_LOCKED   = 0x01
+} HAL_LockTypeDef;
+
+/* Exported macro ------------------------------------------------------------*/
+
+#define HAL_MAX_DELAY      0xFFFFFFFFU
+
+#define HAL_IS_BIT_SET(REG, BIT)         (((REG) & (BIT)) == (BIT))
+#define HAL_IS_BIT_CLR(REG, BIT)         (((REG) & (BIT)) == 0U)
+
+#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__)               \
+                        do{                                                      \
+                              (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
+                              (__DMA_HANDLE__).Parent = (__HANDLE__);             \
+                          } while(0)
+
+#define UNUSED(x) ((void)(x))
+
+/** @brief Reset the Handle's State field.
+  * @param __HANDLE__: specifies the Peripheral Handle.
+  * @note  This macro can be used for the following purpose: 
+  *          - When the Handle is declared as local variable; before passing it as parameter
+  *            to HAL_PPP_Init() for the first time, it is mandatory to use this macro 
+  *            to set to 0 the Handle's "State" field.
+  *            Otherwise, "State" field may have any random value and the first time the function 
+  *            HAL_PPP_Init() is called, the low level hardware initialization will be missed
+  *            (i.e. HAL_PPP_MspInit() will not be executed).
+  *          - When there is a need to reconfigure the low level hardware: instead of calling
+  *            HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
+  *            In this later function, when the Handle's "State" field is set to 0, it will execute the function
+  *            HAL_PPP_MspInit() which will reconfigure the low level hardware.
+  * @retval None
+  */
+#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
+
+#if (USE_RTOS == 1)
+  #error " USE_RTOS should be 0 in the current HAL release "
+#else
+  #define __HAL_LOCK(__HANDLE__)                                           \
+                                do{                                        \
+                                    if((__HANDLE__)->Lock == HAL_LOCKED)   \
+                                    {                                      \
+                                       return HAL_BUSY;                    \
+                                    }                                      \
+                                    else                                   \
+                                    {                                      \
+                                       (__HANDLE__)->Lock = HAL_LOCKED;    \
+                                    }                                      \
+                                  }while (0)
+
+  #define __HAL_UNLOCK(__HANDLE__)                                          \
+                                  do{                                       \
+                                      (__HANDLE__)->Lock = HAL_UNLOCKED;    \
+                                    }while (0)
+#endif /* USE_RTOS */
+
+#if  defined ( __GNUC__ )
+  #ifndef __weak
+    #define __weak   __attribute__((weak))
+  #endif /* __weak */
+  #ifndef __packed
+    #define __packed __attribute__((__packed__))
+  #endif /* __packed */
+#endif /* __GNUC__ */
+
+
+/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
+#if defined   (__GNUC__)        /* GNU Compiler */
+  #ifndef __ALIGN_END
+    #define __ALIGN_END    __attribute__ ((aligned (4)))
+  #endif /* __ALIGN_END */
+  #ifndef __ALIGN_BEGIN
+    #define __ALIGN_BEGIN
+  #endif /* __ALIGN_BEGIN */
+#else
+  #ifndef __ALIGN_END
+    #define __ALIGN_END
+  #endif /* __ALIGN_END */
+  #ifndef __ALIGN_BEGIN
+    #if defined   (__CC_ARM)      /* ARM Compiler */
+      #define __ALIGN_BEGIN    __align(4)
+    #elif defined (__ICCARM__)    /* IAR Compiler */
+      #define __ALIGN_BEGIN
+    #endif /* __CC_ARM */
+  #endif /* __ALIGN_BEGIN */
+#endif /* __GNUC__ */
+
+/* Macro to get variable aligned on 32-bytes,needed for cache maintenance purpose */
+#if defined   (__GNUC__)        /* GNU Compiler */
+  #define ALIGN_32BYTES(buf)  buf __attribute__ ((aligned (32)))                                    
+#elif defined (__ICCARM__)    /* IAR Compiler */
+  #define ALIGN_32BYTES(buf) _Pragma("data_alignment=32") buf  
+#elif defined   (__CC_ARM)      /* ARM Compiler */
+  #define ALIGN_32BYTES(buf) __align(32) buf  
+#endif
+
+/**
+  * @brief  __RAM_FUNC definition
+  */
+#if defined ( __CC_ARM   )
+/* ARM Compiler
+   ------------
+   RAM functions are defined using the toolchain options.
+   Functions that are executed in RAM should reside in a separate source module.
+   Using the 'Options for File' dialog you can simply change the 'Code / Const'
+   area of a module to a memory space in physical RAM.
+   Available memory areas are declared in the 'Target' tab of the 'Options for Target'
+   dialog.
+*/
+#define __RAM_FUNC
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+   ---------------
+   RAM functions are defined using a specific toolchain keyword "__ramfunc".
+*/
+#define __RAM_FUNC __ramfunc
+
+#elif defined   (  __GNUC__  )
+/* GNU Compiler
+   ------------
+  RAM functions are defined using a specific toolchain attribute
+   "__attribute__((section(".RamFunc")))".
+*/
+#define __RAM_FUNC __attribute__((section(".RamFunc")))
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_DEF */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h
new file mode 100644
index 00000000..36d553b0
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h
@@ -0,0 +1,1290 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_dma.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMA HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_DMA_H
+#define STM32H7xx_HAL_DMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DMA
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Types DMA Exported Types
+  * @brief    DMA Exported Types
+  * @{
+  */
+
+/**
+  * @brief  DMA Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t Request;               /*!< Specifies the request selected for the specified stream.
+                                           This parameter can be a value of @ref DMA_Request_selection              */
+
+  uint32_t Direction;            /*!< Specifies if the data will be transferred from memory to peripheral,
+                                      from memory to memory or from peripheral to memory.
+                                      This parameter can be a value of @ref DMA_Data_transfer_direction              */
+
+  uint32_t PeriphInc;            /*!< Specifies whether the Peripheral address register should be incremented or not.
+                                      This parameter can be a value of @ref DMA_Peripheral_incremented_mode          */
+
+  uint32_t MemInc;               /*!< Specifies whether the memory address register should be incremented or not.
+                                      This parameter can be a value of @ref DMA_Memory_incremented_mode              */
+
+  uint32_t PeriphDataAlignment;  /*!< Specifies the Peripheral data width.
+                                      This parameter can be a value of @ref DMA_Peripheral_data_size                 */
+
+  uint32_t MemDataAlignment;     /*!< Specifies the Memory data width.
+                                      This parameter can be a value of @ref DMA_Memory_data_size                     */
+
+  uint32_t Mode;                 /*!< Specifies the operation mode of the DMAy Streamx.
+                                      This parameter can be a value of @ref DMA_mode
+                                      @note The circular buffer mode cannot be used if the memory-to-memory
+                                            data transfer is configured on the selected Stream                        */
+
+  uint32_t Priority;             /*!< Specifies the software priority for the DMAy Streamx.
+                                      This parameter can be a value of @ref DMA_Priority_level                        */
+
+  uint32_t FIFOMode;             /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
+                                      This parameter can be a value of @ref DMA_FIFO_direct_mode
+                                      @note The Direct mode (FIFO mode disabled) cannot be used if the
+                                            memory-to-memory data transfer is configured on the selected stream       */
+
+  uint32_t FIFOThreshold;        /*!< Specifies the FIFO threshold level.
+                                      This parameter can be a value of @ref DMA_FIFO_threshold_level                  */
+
+  uint32_t MemBurst;             /*!< Specifies the Burst transfer configuration for the memory transfers.
+                                      It specifies the amount of data to be transferred in a single non interruptible
+                                      transaction.
+                                      This parameter can be a value of @ref DMA_Memory_burst
+                                      @note The burst mode is possible only if the address Increment mode is enabled. */
+
+  uint32_t PeriphBurst;          /*!< Specifies the Burst transfer configuration for the peripheral transfers.
+                                      It specifies the amount of data to be transferred in a single non interruptible
+                                      transaction.
+                                      This parameter can be a value of @ref DMA_Peripheral_burst
+                                      @note The burst mode is possible only if the address Increment mode is enabled. */
+}DMA_InitTypeDef;
+
+/**
+  * @brief  HAL DMA State structures definition
+  */
+typedef enum
+{
+  HAL_DMA_STATE_RESET             = 0x00U,  /*!< DMA not yet initialized or disabled */
+  HAL_DMA_STATE_READY             = 0x01U,  /*!< DMA initialized and ready for use   */
+  HAL_DMA_STATE_BUSY              = 0x02U,  /*!< DMA process is ongoing              */
+  HAL_DMA_STATE_ERROR             = 0x03U,  /*!< DMA error state                     */
+  HAL_DMA_STATE_ABORT             = 0x04U,  /*!< DMA Abort state                     */
+}HAL_DMA_StateTypeDef;
+
+/**
+  * @brief  HAL DMA Transfer complete level structure definition
+  */
+typedef enum
+{
+  HAL_DMA_FULL_TRANSFER      = 0x00U,    /*!< Full transfer     */
+  HAL_DMA_HALF_TRANSFER      = 0x01U,    /*!< Half Transfer     */
+}HAL_DMA_LevelCompleteTypeDef;
+
+/**
+  * @brief  HAL DMA Callbacks IDs structure definition
+  */
+typedef enum
+{
+  HAL_DMA_XFER_CPLT_CB_ID          = 0x00U,    /*!< Full transfer     */
+  HAL_DMA_XFER_HALFCPLT_CB_ID      = 0x01U,    /*!< Half Transfer     */
+  HAL_DMA_XFER_M1CPLT_CB_ID        = 0x02U,    /*!< M1 Full Transfer  */
+  HAL_DMA_XFER_M1HALFCPLT_CB_ID    = 0x03U,    /*!< M1 Half Transfer  */
+  HAL_DMA_XFER_ERROR_CB_ID         = 0x04U,    /*!< Error             */
+  HAL_DMA_XFER_ABORT_CB_ID         = 0x05U,    /*!< Abort             */
+  HAL_DMA_XFER_ALL_CB_ID           = 0x06U     /*!< All               */
+}HAL_DMA_CallbackIDTypeDef;
+
+/**
+  * @brief  DMA handle Structure definition
+  */
+typedef struct __DMA_HandleTypeDef
+{
+  void                            *Instance;                                                        /*!< Register base address                         */
+
+  DMA_InitTypeDef                 Init;                                                             /*!< DMA communication parameters                  */
+
+  HAL_LockTypeDef                 Lock;                                                             /*!< DMA locking object                            */
+
+  __IO HAL_DMA_StateTypeDef       State;                                                            /*!< DMA transfer state                            */
+
+  void                            *Parent;                                                          /*!< Parent object state                           */
+
+  void                            (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);         /*!< DMA transfer complete callback                */
+
+  void                            (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);     /*!< DMA Half transfer complete callback           */
+
+  void                            (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma);       /*!< DMA transfer complete Memory1 callback        */
+
+  void                            (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);   /*!< DMA transfer Half complete Memory1 callback   */
+
+  void                            (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);        /*!< DMA transfer error callback                   */
+
+  void                            (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma);        /*!< DMA transfer Abort callback                   */
+
+ __IO uint32_t                    ErrorCode;                                                        /*!< DMA Error code                                */
+
+ uint32_t                         StreamBaseAddress;                                                /*!< DMA Stream Base Address                       */
+
+ uint32_t                         StreamIndex;                                                      /*!< DMA Stream Index                              */
+
+ DMAMUX_Channel_TypeDef           *DMAmuxChannel;                                                   /*!< DMAMUX Channel Base Address                   */
+
+ DMAMUX_ChannelStatus_TypeDef     *DMAmuxChannelStatus;                                             /*!< DMAMUX Channels Status Base Address           */
+
+ uint32_t                         DMAmuxChannelStatusMask;                                          /*!< DMAMUX Channel Status Mask                    */
+
+
+ DMAMUX_RequestGen_TypeDef        *DMAmuxRequestGen;                                                /*!< DMAMUX request generator Base Address         */
+
+ DMAMUX_RequestGenStatus_TypeDef  *DMAmuxRequestGenStatus;                                          /*!< DMAMUX request generator Status Address       */
+
+ uint32_t                         DMAmuxRequestGenStatusMask;                                       /*!< DMAMUX request generator Status mask          */
+
+}DMA_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Constants DMA Exported Constants
+  * @brief    DMA Exported constants
+  * @{
+  */
+
+/** @defgroup DMA_Error_Code DMA Error Code
+  * @brief    DMA Error Code
+  * @{
+  */
+#define HAL_DMA_ERROR_NONE            (0x00000000U)    /*!< No error                                */
+#define HAL_DMA_ERROR_TE              (0x00000001U)    /*!< Transfer error                          */
+#define HAL_DMA_ERROR_FE              (0x00000002U)    /*!< FIFO error                              */
+#define HAL_DMA_ERROR_DME             (0x00000004U)    /*!< Direct Mode error                       */
+#define HAL_DMA_ERROR_TIMEOUT         (0x00000020U)    /*!< Timeout error                           */
+#define HAL_DMA_ERROR_PARAM           (0x00000040U)    /*!< Parameter error                         */
+#define HAL_DMA_ERROR_NO_XFER         (0x00000080U)    /*!< Abort requested with no Xfer ongoing    */
+#define HAL_DMA_ERROR_NOT_SUPPORTED   (0x00000100U)    /*!< Not supported mode                      */
+#define HAL_DMA_ERROR_SYNC            (0x00000200U)    /*!< DMAMUX sync overrun  error              */
+#define HAL_DMA_ERROR_REQGEN          (0x00000400U)    /*!< DMAMUX request generator overrun  error */
+#define HAL_DMA_ERROR_BUSY            (0x00000800U)    /*!< DMA Busy                          error */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Request_selection DMA Request selection
+  * @brief    DMA Request selection
+  * @{
+  */
+/* DMAMUX1 requests */
+#define DMA_REQUEST_MEM2MEM          0U  /*!< memory to memory transfer   */
+
+#define DMA_REQUEST_GENERATOR0       1U  /*!< DMAMUX1 request generator 0 */
+#define DMA_REQUEST_GENERATOR1       2U  /*!< DMAMUX1 request generator 1 */
+#define DMA_REQUEST_GENERATOR2       3U  /*!< DMAMUX1 request generator 2 */
+#define DMA_REQUEST_GENERATOR3       4U  /*!< DMAMUX1 request generator 3 */
+#define DMA_REQUEST_GENERATOR4       5U  /*!< DMAMUX1 request generator 4 */
+#define DMA_REQUEST_GENERATOR5       6U  /*!< DMAMUX1 request generator 5 */
+#define DMA_REQUEST_GENERATOR6       7U  /*!< DMAMUX1 request generator 6 */
+#define DMA_REQUEST_GENERATOR7       8U  /*!< DMAMUX1 request generator 7 */
+
+#define DMA_REQUEST_ADC1             9U  /*!< DMAMUX1 ADC1 request */
+#define DMA_REQUEST_ADC2             10U /*!< DMAMUX1 ADC2 request */
+
+#define DMA_REQUEST_TIM1_CH1         11U  /*!< DMAMUX1 TIM1 CH1 request  */
+#define DMA_REQUEST_TIM1_CH2         12U  /*!< DMAMUX1 TIM1 CH2 request  */
+#define DMA_REQUEST_TIM1_CH3         13U  /*!< DMAMUX1 TIM1 CH3 request  */
+#define DMA_REQUEST_TIM1_CH4         14U  /*!< DMAMUX1 TIM1 CH4 request  */
+#define DMA_REQUEST_TIM1_UP          15U  /*!< DMAMUX1 TIM1 UP request   */
+#define DMA_REQUEST_TIM1_TRIG        16U  /*!< DMAMUX1 TIM1 TRIG request */
+#define DMA_REQUEST_TIM1_COM         17U  /*!< DMAMUX1 TIM1 COM request  */
+
+#define DMA_REQUEST_TIM2_CH1         18U  /*!< DMAMUX1 TIM2 CH1 request  */
+#define DMA_REQUEST_TIM2_CH2         19U  /*!< DMAMUX1 TIM2 CH2 request  */
+#define DMA_REQUEST_TIM2_CH3         20U  /*!< DMAMUX1 TIM2 CH3 request  */
+#define DMA_REQUEST_TIM2_CH4         21U  /*!< DMAMUX1 TIM2 CH4 request  */
+#define DMA_REQUEST_TIM2_UP          22U  /*!< DMAMUX1 TIM2 UP request   */
+
+#define DMA_REQUEST_TIM3_CH1         23U  /*!< DMAMUX1 TIM3 CH1 request  */
+#define DMA_REQUEST_TIM3_CH2         24U  /*!< DMAMUX1 TIM3 CH2 request  */
+#define DMA_REQUEST_TIM3_CH3         25U  /*!< DMAMUX1 TIM3 CH3 request  */
+#define DMA_REQUEST_TIM3_CH4         26U  /*!< DMAMUX1 TIM3 CH4 request  */
+#define DMA_REQUEST_TIM3_UP          27U  /*!< DMAMUX1 TIM3 UP request   */
+#define DMA_REQUEST_TIM3_TRIG        28U  /*!< DMAMUX1 TIM3 TRIG request */
+
+#define DMA_REQUEST_TIM4_CH1         29U  /*!< DMAMUX1 TIM4 CH1 request  */
+#define DMA_REQUEST_TIM4_CH2         30U  /*!< DMAMUX1 TIM4 CH2 request  */
+#define DMA_REQUEST_TIM4_CH3         31U  /*!< DMAMUX1 TIM4 CH3 request  */
+#define DMA_REQUEST_TIM4_UP          32U  /*!< DMAMUX1 TIM4 UP request   */
+
+#define DMA_REQUEST_I2C1_RX          33U  /*!< DMAMUX1 I2C1 RX request   */
+#define DMA_REQUEST_I2C1_TX          34U  /*!< DMAMUX1 I2C1 TX request   */
+#define DMA_REQUEST_I2C2_RX          35U  /*!< DMAMUX1 I2C2 RX request   */
+#define DMA_REQUEST_I2C2_TX          36U  /*!< DMAMUX1 I2C2 TX request   */
+
+#define DMA_REQUEST_SPI1_RX          37U  /*!< DMAMUX1 SPI1 RX request   */
+#define DMA_REQUEST_SPI1_TX          38U  /*!< DMAMUX1 SPI1 TX request   */
+#define DMA_REQUEST_SPI2_RX          39U  /*!< DMAMUX1 SPI2 RX request   */
+#define DMA_REQUEST_SPI2_TX          40U  /*!< DMAMUX1 SPI2 TX request   */
+
+#define DMA_REQUEST_USART1_RX        41U  /*!< DMAMUX1 USART1 RX request */
+#define DMA_REQUEST_USART1_TX        42U  /*!< DMAMUX1 USART1 TX request */
+#define DMA_REQUEST_USART2_RX        43U  /*!< DMAMUX1 USART2 RX request */
+#define DMA_REQUEST_USART2_TX        44U  /*!< DMAMUX1 USART2 TX request */
+#define DMA_REQUEST_USART3_RX        45U  /*!< DMAMUX1 USART3 RX request */
+#define DMA_REQUEST_USART3_TX        46U  /*!< DMAMUX1 USART3 TX request */
+
+#define DMA_REQUEST_TIM8_CH1         47U  /*!< DMAMUX1 TIM8 CH1 request  */
+#define DMA_REQUEST_TIM8_CH2         48U  /*!< DMAMUX1 TIM8 CH2 request  */
+#define DMA_REQUEST_TIM8_CH3         49U  /*!< DMAMUX1 TIM8 CH3 request  */
+#define DMA_REQUEST_TIM8_CH4         50U  /*!< DMAMUX1 TIM8 CH4 request  */
+#define DMA_REQUEST_TIM8_UP          51U  /*!< DMAMUX1 TIM8 UP request   */
+#define DMA_REQUEST_TIM8_TRIG        52U  /*!< DMAMUX1 TIM8 TRIG request */
+#define DMA_REQUEST_TIM8_COM         53U  /*!< DMAMUX1 TIM8 COM request  */
+
+#define DMA_REQUEST_TIM5_CH1         55U  /*!< DMAMUX1 TIM5 CH1 request  */
+#define DMA_REQUEST_TIM5_CH2         56U  /*!< DMAMUX1 TIM5 CH2 request  */
+#define DMA_REQUEST_TIM5_CH3         57U  /*!< DMAMUX1 TIM5 CH3 request  */
+#define DMA_REQUEST_TIM5_CH4         58U  /*!< DMAMUX1 TIM5 CH4 request  */
+#define DMA_REQUEST_TIM5_UP          59U  /*!< DMAMUX1 TIM5 UP request   */
+#define DMA_REQUEST_TIM5_TRIG        60U  /*!< DMAMUX1 TIM5 TRIG request */
+
+#define DMA_REQUEST_SPI3_RX          61U  /*!< DMAMUX1 SPI3 RX request   */
+#define DMA_REQUEST_SPI3_TX          62U  /*!< DMAMUX1 SPI3 TX request   */
+
+#define DMA_REQUEST_UART4_RX         63U  /*!< DMAMUX1 UART4 RX request */
+#define DMA_REQUEST_UART4_TX         64U  /*!< DMAMUX1 UART4 TX request */
+#define DMA_REQUEST_UART5_RX         65U  /*!< DMAMUX1 UART5 RX request */
+#define DMA_REQUEST_UART5_TX         66U  /*!< DMAMUX1 UART5 TX request */
+
+#define DMA_REQUEST_DAC1_CH1         67U  /*!< DMAMUX1 DAC1 Channel 1 request */
+#define DMA_REQUEST_DAC1_CH2         68U  /*!< DMAMUX1 DAC1 Channel 2 request */
+
+#define DMA_REQUEST_TIM6_UP          69U  /*!< DMAMUX1 TIM6 UP request   */
+#define DMA_REQUEST_TIM7_UP          70U  /*!< DMAMUX1 TIM7 UP request   */
+
+#define DMA_REQUEST_USART6_RX        71U  /*!< DMAMUX1 USART6 RX request */
+#define DMA_REQUEST_USART6_TX        72U  /*!< DMAMUX1 USART6 TX request */
+
+#define DMA_REQUEST_I2C3_RX          73U  /*!< DMAMUX1 I2C3 RX request   */
+#define DMA_REQUEST_I2C3_TX          74U  /*!< DMAMUX1 I2C3 TX request   */
+
+#if defined (PSSI)
+#define DMA_REQUEST_DCMI_PSSI        75U  /*!< DMAMUX1 DCMI/PSSI request    */
+#define DMA_REQUEST_DCMI             DMA_REQUEST_DCMI_PSSI /* Legacy define */
+#else
+#define DMA_REQUEST_DCMI             75U  /*!< DMAMUX1 DCMI request         */
+#endif /* PSSI */
+
+#define DMA_REQUEST_CRYP_IN          76U  /*!< DMAMUX1 CRYP IN request   */
+#define DMA_REQUEST_CRYP_OUT         77U  /*!< DMAMUX1 CRYP OUT request  */
+
+#define DMA_REQUEST_HASH_IN          78U  /*!< DMAMUX1 HASH IN request   */
+
+#define DMA_REQUEST_UART7_RX         79U  /*!< DMAMUX1 UART7 RX request  */
+#define DMA_REQUEST_UART7_TX         80U  /*!< DMAMUX1 UART7 TX request  */
+#define DMA_REQUEST_UART8_RX         81U  /*!< DMAMUX1 UART8 RX request  */
+#define DMA_REQUEST_UART8_TX         82U  /*!< DMAMUX1 UART8 TX request  */
+
+#define DMA_REQUEST_SPI4_RX          83U  /*!< DMAMUX1 SPI4 RX request   */
+#define DMA_REQUEST_SPI4_TX          84U  /*!< DMAMUX1 SPI4 TX request   */
+#define DMA_REQUEST_SPI5_RX          85U  /*!< DMAMUX1 SPI5 RX request   */
+#define DMA_REQUEST_SPI5_TX          86U  /*!< DMAMUX1 SPI5 TX request   */
+
+#define DMA_REQUEST_SAI1_A           87U  /*!< DMAMUX1 SAI1 A request    */
+#define DMA_REQUEST_SAI1_B           88U  /*!< DMAMUX1 SAI1 B request    */
+#define DMA_REQUEST_SAI2_A           89U  /*!< DMAMUX1 SAI2 A request    */
+#define DMA_REQUEST_SAI2_B           90U  /*!< DMAMUX1 SAI2 B request    */
+
+#define DMA_REQUEST_SWPMI_RX         91U  /*!< DMAMUX1 SWPMI RX request  */
+#define DMA_REQUEST_SWPMI_TX         92U  /*!< DMAMUX1 SWPMI TX request  */
+
+#define DMA_REQUEST_SPDIF_RX_DT      93U  /*!< DMAMUX1 SPDIF RXDT request*/
+#define DMA_REQUEST_SPDIF_RX_CS      94U  /*!< DMAMUX1 SPDIF RXCS request*/
+
+#if defined(HRTIM1)
+#define DMA_REQUEST_HRTIM_MASTER     95U  /*!< DMAMUX1 HRTIM1 Master request 1 */
+#define DMA_REQUEST_HRTIM_TIMER_A    96U  /*!< DMAMUX1 HRTIM1 TimerA request 2 */
+#define DMA_REQUEST_HRTIM_TIMER_B    97U  /*!< DMAMUX1 HRTIM1 TimerB request 3 */
+#define DMA_REQUEST_HRTIM_TIMER_C    98U  /*!< DMAMUX1 HRTIM1 TimerC request 4 */
+#define DMA_REQUEST_HRTIM_TIMER_D    99U  /*!< DMAMUX1 HRTIM1 TimerD request 5 */
+#define DMA_REQUEST_HRTIM_TIMER_E   100U  /*!< DMAMUX1 HRTIM1 TimerE request 6 */
+#endif /* HRTIM1 */
+
+#define DMA_REQUEST_DFSDM1_FLT0     101U  /*!< DMAMUX1 DFSDM Filter0 request */
+#define DMA_REQUEST_DFSDM1_FLT1     102U  /*!< DMAMUX1 DFSDM Filter1 request */
+#define DMA_REQUEST_DFSDM1_FLT2     103U  /*!< DMAMUX1 DFSDM Filter2 request */
+#define DMA_REQUEST_DFSDM1_FLT3     104U  /*!< DMAMUX1 DFSDM Filter3 request */
+
+#define DMA_REQUEST_TIM15_CH1       105U  /*!< DMAMUX1 TIM15 CH1 request  */
+#define DMA_REQUEST_TIM15_UP        106U  /*!< DMAMUX1 TIM15 UP request   */
+#define DMA_REQUEST_TIM15_TRIG      107U  /*!< DMAMUX1 TIM15 TRIG request */
+#define DMA_REQUEST_TIM15_COM       108U  /*!< DMAMUX1 TIM15 COM request  */
+
+#define DMA_REQUEST_TIM16_CH1       109U  /*!< DMAMUX1 TIM16 CH1 request  */
+#define DMA_REQUEST_TIM16_UP        110U  /*!< DMAMUX1 TIM16 UP request   */
+
+#define DMA_REQUEST_TIM17_CH1       111U  /*!< DMAMUX1 TIM17 CH1 request  */
+#define DMA_REQUEST_TIM17_UP        112U  /*!< DMAMUX1 TIM17 UP request   */
+
+#if defined(SAI3)
+#define DMA_REQUEST_SAI3_A          113U  /*!< DMAMUX1 SAI3 A request  */
+#define DMA_REQUEST_SAI3_B          114U  /*!< DMAMUX1 SAI3 B request  */
+#endif /* SAI3 */
+
+#if defined(ADC3)
+#define DMA_REQUEST_ADC3            115U  /*!< DMAMUX1 ADC3 request  */
+#endif /* ADC3 */
+
+#if defined(UART9)
+#define DMA_REQUEST_UART9_RX        116U  /*!< DMAMUX1 UART9 request  */
+#define DMA_REQUEST_UART9_TX        117U  /*!< DMAMUX1 UART9 request  */
+#endif /* UART9 */
+
+#if defined(USART10)
+#define DMA_REQUEST_USART10_RX      118U  /*!< DMAMUX1 USART10 request  */
+#define DMA_REQUEST_USART10_TX      119U  /*!< DMAMUX1 USART10 request  */
+#endif /* USART10 */
+
+
+/* DMAMUX2 requests */
+#define BDMA_REQUEST_MEM2MEM          0U  /*!< memory to memory transfer   */
+#define BDMA_REQUEST_GENERATOR0       1U  /*!< DMAMUX2 request generator 0 */
+#define BDMA_REQUEST_GENERATOR1       2U  /*!< DMAMUX2 request generator 1 */
+#define BDMA_REQUEST_GENERATOR2       3U  /*!< DMAMUX2 request generator 2 */
+#define BDMA_REQUEST_GENERATOR3       4U  /*!< DMAMUX2 request generator 3 */
+#define BDMA_REQUEST_GENERATOR4       5U  /*!< DMAMUX2 request generator 4 */
+#define BDMA_REQUEST_GENERATOR5       6U  /*!< DMAMUX2 request generator 5 */
+#define BDMA_REQUEST_GENERATOR6       7U  /*!< DMAMUX2 request generator 6 */
+#define BDMA_REQUEST_GENERATOR7       8U  /*!< DMAMUX2 request generator 7 */
+#define BDMA_REQUEST_LPUART1_RX       9U  /*!< DMAMUX2 LP_UART1_RX request */
+#define BDMA_REQUEST_LPUART1_TX      10U  /*!< DMAMUX2 LP_UART1_TX request */
+#define BDMA_REQUEST_SPI6_RX         11U  /*!< DMAMUX2 SPI6 RX request     */
+#define BDMA_REQUEST_SPI6_TX         12U  /*!< DMAMUX2 SPI6 TX request     */
+#define BDMA_REQUEST_I2C4_RX         13U  /*!< DMAMUX2 I2C4 RX request     */
+#define BDMA_REQUEST_I2C4_TX         14U  /*!< DMAMUX2 I2C4 TX request     */
+#if defined(SAI4)
+#define BDMA_REQUEST_SAI4_A          15U  /*!< DMAMUX2 SAI4 A request      */
+#define BDMA_REQUEST_SAI4_B          16U  /*!< DMAMUX2 SAI4 B request      */
+#endif /* SAI4 */
+#if defined(ADC3)
+#define BDMA_REQUEST_ADC3            17U  /*!< DMAMUX2 ADC3 request        */
+#endif /* ADC3 */
+#if defined(DAC2)
+#define BDMA_REQUEST_DAC2_CH1        17U  /*!< DMAMUX2 DAC2 CH1 request    */
+#endif /* DAC2 */
+#if defined(DFSDM2_Channel0)
+#define BDMA_REQUEST_DFSDM2_FLT0     18U  /*!< DMAMUX2 DFSDM2 request      */
+#endif /* DFSDM1_Channel0 */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
+  * @brief    DMA data transfer direction
+  * @{
+  */
+#define DMA_PERIPH_TO_MEMORY         ((uint32_t)0x00000000U)      /*!< Peripheral to memory direction */
+#define DMA_MEMORY_TO_PERIPH         ((uint32_t)DMA_SxCR_DIR_0)  /*!< Memory to peripheral direction */
+#define DMA_MEMORY_TO_MEMORY         ((uint32_t)DMA_SxCR_DIR_1)  /*!< Memory to memory direction     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
+  * @brief    DMA peripheral incremented mode
+  * @{
+  */
+#define DMA_PINC_ENABLE        ((uint32_t)DMA_SxCR_PINC)  /*!< Peripheral increment mode enable  */
+#define DMA_PINC_DISABLE       ((uint32_t)0x00000000U)     /*!< Peripheral increment mode disable */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
+  * @brief    DMA memory incremented mode
+  * @{
+  */
+#define DMA_MINC_ENABLE         ((uint32_t)DMA_SxCR_MINC)  /*!< Memory increment mode enable  */
+#define DMA_MINC_DISABLE        ((uint32_t)0x00000000U)     /*!< Memory increment mode disable */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
+  * @brief    DMA peripheral data size
+  * @{
+  */
+#define DMA_PDATAALIGN_BYTE          ((uint32_t)0x00000000U)       /*!< Peripheral data alignment: Byte      */
+#define DMA_PDATAALIGN_HALFWORD      ((uint32_t)DMA_SxCR_PSIZE_0)  /*!< Peripheral data alignment: HalfWord  */
+#define DMA_PDATAALIGN_WORD          ((uint32_t)DMA_SxCR_PSIZE_1)  /*!< Peripheral data alignment: Word      */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Memory_data_size DMA Memory data size
+  * @brief    DMA memory data size
+  * @{
+  */
+#define DMA_MDATAALIGN_BYTE          ((uint32_t)0x00000000U)       /*!< Memory data alignment: Byte     */
+#define DMA_MDATAALIGN_HALFWORD      ((uint32_t)DMA_SxCR_MSIZE_0)  /*!< Memory data alignment: HalfWord */
+#define DMA_MDATAALIGN_WORD          ((uint32_t)DMA_SxCR_MSIZE_1)  /*!< Memory data alignment: Word     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_mode DMA mode
+  * @brief    DMA mode
+  * @{
+  */
+#define DMA_NORMAL              ((uint32_t)0x00000000U)                  /*!< Normal mode                                    */
+#define DMA_CIRCULAR            ((uint32_t)DMA_SxCR_CIRC)                /*!< Circular mode                                  */
+#define DMA_PFCTRL              ((uint32_t)DMA_SxCR_PFCTRL)              /*!< Peripheral flow control mode                   */
+#define DMA_DOUBLE_BUFFER_M0    ((uint32_t)DMA_SxCR_DBM)                 /*!< Double buffer mode with first target memory M0 */
+#define DMA_DOUBLE_BUFFER_M1    ((uint32_t)(DMA_SxCR_DBM | DMA_SxCR_CT)) /*!< Double buffer mode with first target memory M1 */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Priority_level DMA Priority level
+  * @brief    DMA priority levels
+  * @{
+  */
+#define DMA_PRIORITY_LOW             ((uint32_t)0x00000000U)    /*!< Priority level: Low       */
+#define DMA_PRIORITY_MEDIUM          ((uint32_t)DMA_SxCR_PL_0)  /*!< Priority level: Medium    */
+#define DMA_PRIORITY_HIGH            ((uint32_t)DMA_SxCR_PL_1)  /*!< Priority level: High      */
+#define DMA_PRIORITY_VERY_HIGH       ((uint32_t)DMA_SxCR_PL)    /*!< Priority level: Very High */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
+  * @brief    DMA FIFO direct mode
+  * @{
+  */
+#define DMA_FIFOMODE_DISABLE        ((uint32_t)0x00000000U)       /*!< FIFO mode disable */
+#define DMA_FIFOMODE_ENABLE         ((uint32_t)DMA_SxFCR_DMDIS)  /*!< FIFO mode enable  */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
+  * @brief    DMA FIFO level
+  * @{
+  */
+#define DMA_FIFO_THRESHOLD_1QUARTERFULL       ((uint32_t)0x00000000U)       /*!< FIFO threshold 1 quart full configuration  */
+#define DMA_FIFO_THRESHOLD_HALFFULL           ((uint32_t)DMA_SxFCR_FTH_0)  /*!< FIFO threshold half full configuration     */
+#define DMA_FIFO_THRESHOLD_3QUARTERSFULL      ((uint32_t)DMA_SxFCR_FTH_1)  /*!< FIFO threshold 3 quarts full configuration */
+#define DMA_FIFO_THRESHOLD_FULL               ((uint32_t)DMA_SxFCR_FTH)    /*!< FIFO threshold full configuration          */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Memory_burst DMA Memory burst
+  * @brief    DMA memory burst
+  * @{
+  */
+#define DMA_MBURST_SINGLE       ((uint32_t)0x00000000U)
+#define DMA_MBURST_INC4         ((uint32_t)DMA_SxCR_MBURST_0)
+#define DMA_MBURST_INC8         ((uint32_t)DMA_SxCR_MBURST_1)
+#define DMA_MBURST_INC16        ((uint32_t)DMA_SxCR_MBURST)
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Peripheral_burst DMA Peripheral burst
+  * @brief    DMA peripheral burst
+  * @{
+  */
+#define DMA_PBURST_SINGLE       ((uint32_t)0x00000000U)
+#define DMA_PBURST_INC4         ((uint32_t)DMA_SxCR_PBURST_0)
+#define DMA_PBURST_INC8         ((uint32_t)DMA_SxCR_PBURST_1)
+#define DMA_PBURST_INC16        ((uint32_t)DMA_SxCR_PBURST)
+/**
+  * @}
+  */
+
+/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
+  * @brief    DMA interrupts definition
+  * @{
+  */
+#define DMA_IT_TC                         ((uint32_t)DMA_SxCR_TCIE)
+#define DMA_IT_HT                         ((uint32_t)DMA_SxCR_HTIE)
+#define DMA_IT_TE                         ((uint32_t)DMA_SxCR_TEIE)
+#define DMA_IT_DME                        ((uint32_t)DMA_SxCR_DMEIE)
+#define DMA_IT_FE                         ((uint32_t)0x00000080U)
+/**
+  * @}
+  */
+
+/** @defgroup DMA_flag_definitions DMA flag definitions
+  * @brief    DMA flag definitions
+  * @{
+  */
+#define DMA_FLAG_FEIF0_4                    ((uint32_t)0x00000001U)
+#define DMA_FLAG_DMEIF0_4                   ((uint32_t)0x00000004U)
+#define DMA_FLAG_TEIF0_4                    ((uint32_t)0x00000008U)
+#define DMA_FLAG_HTIF0_4                    ((uint32_t)0x00000010U)
+#define DMA_FLAG_TCIF0_4                    ((uint32_t)0x00000020U)
+#define DMA_FLAG_FEIF1_5                    ((uint32_t)0x00000040U)
+#define DMA_FLAG_DMEIF1_5                   ((uint32_t)0x00000100U)
+#define DMA_FLAG_TEIF1_5                    ((uint32_t)0x00000200U)
+#define DMA_FLAG_HTIF1_5                    ((uint32_t)0x00000400U)
+#define DMA_FLAG_TCIF1_5                    ((uint32_t)0x00000800U)
+#define DMA_FLAG_FEIF2_6                    ((uint32_t)0x00010000U)
+#define DMA_FLAG_DMEIF2_6                   ((uint32_t)0x00040000U)
+#define DMA_FLAG_TEIF2_6                    ((uint32_t)0x00080000U)
+#define DMA_FLAG_HTIF2_6                    ((uint32_t)0x00100000U)
+#define DMA_FLAG_TCIF2_6                    ((uint32_t)0x00200000U)
+#define DMA_FLAG_FEIF3_7                    ((uint32_t)0x00400000U)
+#define DMA_FLAG_DMEIF3_7                   ((uint32_t)0x01000000U)
+#define DMA_FLAG_TEIF3_7                    ((uint32_t)0x02000000U)
+#define DMA_FLAG_HTIF3_7                    ((uint32_t)0x04000000U)
+#define DMA_FLAG_TCIF3_7                    ((uint32_t)0x08000000U)
+/**
+  * @}
+  */
+
+/** @defgroup BDMA_flag_definitions BDMA flag definitions
+  * @brief    BDMA flag definitions
+  * @{
+  */
+#define BDMA_FLAG_GL0                      ((uint32_t)0x00000001)
+#define BDMA_FLAG_TC0                      ((uint32_t)0x00000002)
+#define BDMA_FLAG_HT0                      ((uint32_t)0x00000004)
+#define BDMA_FLAG_TE0                      ((uint32_t)0x00000008)
+#define BDMA_FLAG_GL1                      ((uint32_t)0x00000010)
+#define BDMA_FLAG_TC1                      ((uint32_t)0x00000020)
+#define BDMA_FLAG_HT1                      ((uint32_t)0x00000040)
+#define BDMA_FLAG_TE1                      ((uint32_t)0x00000080)
+#define BDMA_FLAG_GL2                      ((uint32_t)0x00000100)
+#define BDMA_FLAG_TC2                      ((uint32_t)0x00000200)
+#define BDMA_FLAG_HT2                      ((uint32_t)0x00000400)
+#define BDMA_FLAG_TE2                      ((uint32_t)0x00000800)
+#define BDMA_FLAG_GL3                      ((uint32_t)0x00001000)
+#define BDMA_FLAG_TC3                      ((uint32_t)0x00002000)
+#define BDMA_FLAG_HT3                      ((uint32_t)0x00004000)
+#define BDMA_FLAG_TE3                      ((uint32_t)0x00008000)
+#define BDMA_FLAG_GL4                      ((uint32_t)0x00010000)
+#define BDMA_FLAG_TC4                      ((uint32_t)0x00020000)
+#define BDMA_FLAG_HT4                      ((uint32_t)0x00040000)
+#define BDMA_FLAG_TE4                      ((uint32_t)0x00080000)
+#define BDMA_FLAG_GL5                      ((uint32_t)0x00100000)
+#define BDMA_FLAG_TC5                      ((uint32_t)0x00200000)
+#define BDMA_FLAG_HT5                      ((uint32_t)0x00400000)
+#define BDMA_FLAG_TE5                      ((uint32_t)0x00800000)
+#define BDMA_FLAG_GL6                      ((uint32_t)0x01000000)
+#define BDMA_FLAG_TC6                      ((uint32_t)0x02000000)
+#define BDMA_FLAG_HT6                      ((uint32_t)0x04000000)
+#define BDMA_FLAG_TE6                      ((uint32_t)0x08000000)
+#define BDMA_FLAG_GL7                      ((uint32_t)0x10000000)
+#define BDMA_FLAG_TC7                      ((uint32_t)0x20000000)
+#define BDMA_FLAG_HT7                      ((uint32_t)0x40000000)
+#define BDMA_FLAG_TE7                      ((uint32_t)0x80000000)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DMA_Exported_Macros DMA Exported Macros
+  * @{
+  */
+
+/** @brief Reset DMA handle state
+  * @param  __HANDLE__: specifies the DMA handle.
+  * @retval None
+  */
+#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
+
+/**
+  * @brief  Return the current DMA Stream FIFO filled level.
+  * @param  __HANDLE__: DMA handle
+  * @retval The FIFO filling state.
+  *           - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
+  *                                              and not empty.
+  *           - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
+  *           - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
+  *           - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
+  *           - DMA_FIFOStatus_Empty: when FIFO is empty
+  *           - DMA_FIFOStatus_Full: when FIFO is full
+  */
+#define __HAL_DMA_GET_FS(__HANDLE__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (DMA_SxFCR_FS)) : 0)
+
+/**
+  * @brief  Enable the specified DMA Stream.
+  * @param  __HANDLE__: DMA handle
+  * @retval None
+  */
+#define __HAL_DMA_ENABLE(__HANDLE__) \
+((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |=  DMA_SxCR_EN) : \
+(((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |=  BDMA_CCR_EN))
+
+/**
+  * @brief  Disable the specified DMA Stream.
+  * @param  __HANDLE__: DMA handle
+  * @retval None
+  */
+#define __HAL_DMA_DISABLE(__HANDLE__) \
+((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &=  ~DMA_SxCR_EN) : \
+(((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &=  ~BDMA_CCR_EN))
+
+/* Interrupt & Flag management */
+
+/**
+  * @brief  Return the current DMA Stream transfer complete flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified transfer complete flag index.
+  */
+#if defined(BDMA1)
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TCIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TCIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TCIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TCIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_TC0  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_TC0  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_TC1  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_TC1  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_TC2  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_TC2  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_TC3  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_TC3  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_TC4  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_TC4  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_TC5  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_TC5  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_TC6  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_TC6  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_TC7  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_TC7  :\
+ (uint32_t)0x00000000)
+#else
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TCIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TCIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TCIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TCIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_TC0   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_TC1   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_TC2   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_TC3   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_TC4   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_TC5   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TC6   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TC7   :\
+ (uint32_t)0x00000000)
+#endif /* BDMA1 */
+
+/**
+  * @brief  Return the current DMA Stream half transfer complete flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified half transfer complete flag index.
+  */
+#if defined(BDMA1)
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_HTIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_HTIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_HTIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_HTIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_HT0  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_HT0  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_HT1  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_HT1  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_HT2  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_HT2  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_HT3  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_HT3  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_HT4  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_HT4  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_HT5  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_HT5  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_HT6  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_HT6  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_HT7  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_HT7  :\
+ (uint32_t)0x00000000)
+#else
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_HTIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_HTIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_HTIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_HTIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_HT0   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_HT1   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_HT2   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_HT3   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_HT4   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_HT5   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_HT6   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_HT7   :\
+ (uint32_t)0x00000000)
+#endif /* BDMA1 */
+
+/**
+  * @brief  Return the current DMA Stream transfer error flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified transfer error flag index.
+  */
+#if defined(BDMA1)
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_TE0  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_TE0  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_TE1  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_TE1  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_TE2  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_TE2  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_TE3  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_TE3  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_TE4  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_TE4  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_TE5  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_TE5  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_TE6  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_TE6  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_TE7  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_TE7  :\
+ (uint32_t)0x00000000)
+#else
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_TE0   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_TE1   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_TE2   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_TE3   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_TE4   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_TE5   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TE6   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TE7   :\
+ (uint32_t)0x00000000)
+#endif /* BDMA1 */
+
+/**
+  * @brief  Return the current DMA Stream FIFO error flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified FIFO error flag index.
+  */
+#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_FEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_FEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_FEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_FEIF3_7 :\
+  (uint32_t)0x00000000)
+
+/**
+  * @brief  Return the current DMA Stream direct mode error flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified direct mode error flag index.
+  */
+#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_DMEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_DMEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_DMEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_DMEIF3_7 :\
+  (uint32_t)0x00000000)
+
+/**
+  * @brief  Returns the current BDMA Channel Global interrupt flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified transfer error flag index.
+  */
+#if defined(BDMA1)
+#define __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_ISR_GIF0 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_ISR_GIF0 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_ISR_GIF1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_ISR_GIF1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_ISR_GIF2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_ISR_GIF2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_ISR_GIF3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_ISR_GIF3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_ISR_GIF4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_ISR_GIF4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_ISR_GIF5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_ISR_GIF5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_ISR_GIF6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_ISR_GIF6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_ISR_GIF7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_ISR_GIF7 :\
+ (uint32_t)0x00000000)
+#else
+#define __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_ISR_GIF0 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_ISR_GIF1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_ISR_GIF2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_ISR_GIF3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_ISR_GIF4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_ISR_GIF5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_ISR_GIF6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_ISR_GIF7 :\
+  (uint32_t)0x00000000)
+#endif /* BDMA1 */
+
+/**
+  * @brief  Get the DMA Stream pending flags.
+  * @param  __HANDLE__: DMA handle
+  * @param  __FLAG__: Get the specified flag.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
+  *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
+  *            @arg DMA_FLAG_TEIFx: Transfer error flag.
+  *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.
+  *            @arg DMA_FLAG_FEIFx: FIFO error flag.
+  *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
+  * @retval The state of FLAG (SET or RESET).
+  */
+#if defined(BDMA1)
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)BDMA1_Channel7)?  (BDMA2->ISR & (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7  )?  (BDMA1->ISR & (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3  )?  (DMA2->HISR & (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7  )?  (DMA2->LISR & (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3  )?  (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
+#else
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->ISR & (__FLAG__))  :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
+#endif /* BDMA1 */
+
+/**
+  * @brief  Clear the DMA Stream pending flags.
+  * @param  __HANDLE__: DMA handle
+  * @param  __FLAG__: specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
+  *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
+  *            @arg DMA_FLAG_TEIFx: Transfer error flag.
+  *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.
+  *            @arg DMA_FLAG_FEIFx: FIFO error flag.
+  *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
+  * @retval None
+  */
+#if defined(BDMA1)
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)BDMA1_Channel7)? (BDMA2->IFCR = (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)?  (BDMA1->IFCR = (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)?  (DMA2->HIFCR = (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)?  (DMA2->LIFCR = (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)?  (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
+#else
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->IFCR = (__FLAG__))  :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
+#endif /* BDMA1 */
+
+#define DMA_TO_BDMA_IT(__DMA_IT__) \
+((((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE |BDMA_CCR_TEIE) :\
+ (((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT)) == (DMA_IT_TC | DMA_IT_HT)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE) :\
+ (((__DMA_IT__) & (DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_HTIE |BDMA_CCR_TEIE)  :\
+ (((__DMA_IT__) & (DMA_IT_TC | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_TE)) ? (BDMA_CCR_TCIE |BDMA_CCR_TEIE)  :\
+ ((__DMA_IT__) == DMA_IT_TC) ? BDMA_CCR_TCIE :\
+ ((__DMA_IT__) == DMA_IT_HT) ? BDMA_CCR_HTIE :\
+ ((__DMA_IT__) == DMA_IT_TE) ? BDMA_CCR_TEIE :\
+ (uint32_t)0x00000000)
+
+
+#define __HAL_BDMA_CHANNEL_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
+(((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |= (DMA_TO_BDMA_IT(__INTERRUPT__)))
+
+#define __HAL_DMA_STREAM_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((__INTERRUPT__) != DMA_IT_FE)? \
+(((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |= (__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR |= (__INTERRUPT__)))
+
+/**
+  * @brief  Enable the specified DMA Stream interrupts.
+  * @param  __HANDLE__: DMA handle
+  * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+  *        This parameter can be one of the following values:
+  *           @arg DMA_IT_TC: Transfer complete interrupt mask.
+  *           @arg DMA_IT_HT: Half transfer complete interrupt mask.
+  *           @arg DMA_IT_TE: Transfer error interrupt mask.
+  *           @arg DMA_IT_FE: FIFO error interrupt mask.
+  *           @arg DMA_IT_DME: Direct mode error interrupt.
+  * @retval None
+  */
+#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))?\
+                                                        (__HAL_DMA_STREAM_ENABLE_IT((__HANDLE__), (__INTERRUPT__))) :\
+                                                        (__HAL_BDMA_CHANNEL_ENABLE_IT((__HANDLE__), (__INTERRUPT__))))
+
+
+#define __HAL_BDMA_CHANNEL_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &= ~(DMA_TO_BDMA_IT(__INTERRUPT__)))
+
+#define __HAL_DMA_STREAM_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \
+(((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &= ~(__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR &= ~(__INTERRUPT__)))
+
+/**
+  * @brief  Disable the specified DMA Stream interrupts.
+  * @param  __HANDLE__: DMA handle
+  * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+  *         This parameter can be one of the following values:
+  *            @arg DMA_IT_TC: Transfer complete interrupt mask.
+  *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
+  *            @arg DMA_IT_TE: Transfer error interrupt mask.
+  *            @arg DMA_IT_FE: FIFO error interrupt mask.
+  *            @arg DMA_IT_DME: Direct mode error interrupt.
+  * @retval None
+  */
+#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))?\
+                                                         (__HAL_DMA_STREAM_DISABLE_IT((__HANDLE__), (__INTERRUPT__))) :\
+                                                         (__HAL_BDMA_CHANNEL_DISABLE_IT((__HANDLE__), (__INTERRUPT__))))
+
+
+#define __HAL_BDMA_CHANNEL_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  ((((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR & (DMA_TO_BDMA_IT(__INTERRUPT__))))
+
+#define __HAL_DMA_STREAM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \
+                                                        (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR & (__INTERRUPT__)) : \
+                                                        (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (__INTERRUPT__)))
+
+/**
+  * @brief  Check whether the specified DMA Stream interrupt is enabled or not.
+  * @param  __HANDLE__: DMA handle
+  * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
+  *         This parameter can be one of the following values:
+  *            @arg DMA_IT_TC: Transfer complete interrupt mask.
+  *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
+  *            @arg DMA_IT_TE: Transfer error interrupt mask.
+  *            @arg DMA_IT_FE: FIFO error interrupt mask.
+  *            @arg DMA_IT_DME: Direct mode error interrupt.
+  * @retval The state of DMA_IT.
+  */
+#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \
+                                                            (__HAL_DMA_STREAM_GET_IT_SOURCE((__HANDLE__), (__INTERRUPT__))) :\
+                                                            (__HAL_BDMA_CHANNEL_GET_IT_SOURCE((__HANDLE__), (__INTERRUPT__))))
+
+/**
+  * @brief  Writes the number of data units to be transferred on the DMA Stream.
+  * @param  __HANDLE__: DMA handle
+  * @param  __COUNTER__: Number of data units to be transferred (from 0 to 65535)
+  *          Number of data items depends only on the Peripheral data format.
+  *
+  * @note   If Peripheral data format is Bytes: number of data units is equal
+  *         to total number of bytes to be transferred.
+  *
+  * @note   If Peripheral data format is Half-Word: number of data units is
+  *         equal to total number of bytes to be transferred / 2.
+  *
+  * @note   If Peripheral data format is Word: number of data units is equal
+  *         to total  number of bytes to be transferred / 4.
+  *
+  * @retval The number of remaining data units in the current DMAy Streamx transfer.
+  */
+#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \
+                                                        (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR = (uint16_t)(__COUNTER__)) :\
+                                                        (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CNDTR = (uint16_t)(__COUNTER__)))
+
+/**
+  * @brief  Returns the number of remaining data units in the current DMAy Streamx transfer.
+  * @param  __HANDLE__: DMA handle
+  *
+  * @retval The number of remaining data units in the current DMA Stream transfer.
+  */
+#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \
+                                           (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR) :\
+                                           (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CNDTR))
+
+/**
+  * @}
+  */
+
+/* Include DMA HAL Extension module */
+#include "stm32h7xx_hal_dma_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Functions DMA Exported Functions
+  * @brief    DMA Exported functions
+  * @{
+  */
+
+/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief   Initialization and de-initialization functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
+  * @brief   I/O operation functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
+void              HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
+  * @brief    Peripheral State functions
+  * @{
+  */
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
+uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+/* Private Constants -------------------------------------------------------------*/
+/** @defgroup DMA_Private_Constants DMA Private Constants
+  * @brief    DMA private defines and constants
+  * @{
+  */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DMA_Private_Macros DMA Private Macros
+  * @brief    DMA private macros
+  * @{
+  */
+
+#if defined(ADC3)
+#define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_ADC3))
+#else
+#define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_USART10_TX))
+#endif /* ADC3 */
+
+#if defined(ADC3)
+#define IS_BDMA_REQUEST(REQUEST) (((REQUEST) <= BDMA_REQUEST_ADC3))
+#else
+#define IS_BDMA_REQUEST(REQUEST) (((REQUEST) <= BDMA_REQUEST_DFSDM2_FLT0))
+#endif /* ADC3 */
+
+#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
+                                     ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
+                                     ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
+
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
+
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
+                                            ((STATE) == DMA_PINC_DISABLE))
+
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
+                                        ((STATE) == DMA_MINC_DISABLE))
+
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
+                                           ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
+                                           ((SIZE) == DMA_PDATAALIGN_WORD))
+
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
+                                       ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
+                                       ((SIZE) == DMA_MDATAALIGN_WORD ))
+
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )           || \
+                           ((MODE) == DMA_CIRCULAR)          || \
+                           ((MODE) == DMA_PFCTRL)            || \
+                           ((MODE) == DMA_DOUBLE_BUFFER_M0)  || \
+                           ((MODE) == DMA_DOUBLE_BUFFER_M1))
+
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
+                                   ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
+                                   ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
+                                   ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
+
+#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
+                                       ((STATE) == DMA_FIFOMODE_ENABLE))
+
+#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
+                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL)      || \
+                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
+                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
+
+#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
+                                    ((BURST) == DMA_MBURST_INC4)   || \
+                                    ((BURST) == DMA_MBURST_INC8)   || \
+                                    ((BURST) == DMA_MBURST_INC16))
+
+#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
+                                        ((BURST) == DMA_PBURST_INC4)   || \
+                                        ((BURST) == DMA_PBURST_INC8)   || \
+                                        ((BURST) == DMA_PBURST_INC16))
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DMA_Private_Functions DMA Private Functions
+  * @brief    DMA private  functions
+  * @{
+  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h
new file mode 100644
index 00000000..4125ae7e
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h
@@ -0,0 +1,312 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_dma_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMA HAL extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_DMA_EX_H
+#define STM32H7xx_HAL_DMA_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DMAEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DMAEx_Exported_Types DMAEx Exported Types
+  * @brief DMAEx Exported types
+  * @{
+  */
+
+/**
+  * @brief  HAL DMA Memory definition
+  */
+typedef enum
+{
+  MEMORY0      = 0x00U,    /*!< Memory 0     */
+  MEMORY1      = 0x01U,    /*!< Memory 1     */
+
+}HAL_DMA_MemoryTypeDef;
+
+/**
+  * @brief  HAL DMAMUX Synchronization configuration structure definition
+  */
+typedef struct
+{
+  uint32_t SyncSignalID;  /*!< Specifies the synchronization signal gating the DMA request in periodic mode.
+                              This parameter can be a value of @ref DMAEx_MUX_SyncSignalID_selection */
+
+  uint32_t SyncPolarity;  /*!< Specifies the polarity of the signal on which the DMA request is synchronized.
+                              This parameter can be a value of @ref DMAEx_MUX_SyncPolarity_selection */
+
+  FunctionalState SyncEnable;  /*!< Specifies if the synchronization shall be enabled or disabled
+                                    This parameter can take the value ENABLE or DISABLE*/
+
+
+  FunctionalState EventEnable;    /*!< Specifies if an event shall be generated once the RequestNumber is reached.
+                                       This parameter can take the value ENABLE or DISABLE */
+
+  uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be authorized after a sync event.
+                               This parameters can be in the range 1 to 32 */
+
+}HAL_DMA_MuxSyncConfigTypeDef;
+
+
+/**
+  * @brief  HAL DMAMUX request generator parameters structure definition
+  */
+typedef struct
+{
+ uint32_t SignalID;      /*!< Specifies the ID of the signal used for DMAMUX request generator
+                              This parameter can be a value of @ref DMAEx_MUX_SignalGeneratorID_selection */
+
+  uint32_t Polarity;       /*!< Specifies the polarity of the signal on which the request is generated.
+                             This parameter can be a value of @ref DMAEx_MUX_RequestGeneneratorPolarity_selection */
+
+  uint32_t RequestNumber;  /*!< Specifies the number of DMA request that will be generated after a signal event.
+                                This parameters can be in the range 1 to 32 */
+
+}HAL_DMA_MuxRequestGeneratorConfigTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMAEx_Exported_Constants DMA Exported Constants
+  * @brief    DMAEx Exported constants
+  * @{
+  */
+
+/** @defgroup DMAEx_MUX_SyncSignalID_selection DMAEx MUX SyncSignalID selection
+  * @brief    DMAEx MUX SyncSignalID selection
+  * @{
+  */
+#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT   0U   /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel0 Event */
+#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT   1U   /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel1 Event */
+#define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT   2U   /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel2 Event */
+#define HAL_DMAMUX1_SYNC_LPTIM1_OUT        3U   /*!< DMAMUX1 synchronization Signal is LPTIM1 OUT             */
+#define HAL_DMAMUX1_SYNC_LPTIM2_OUT        4U   /*!< DMAMUX1 synchronization Signal is LPTIM2 OUT             */
+#define HAL_DMAMUX1_SYNC_LPTIM3_OUT        5U   /*!< DMAMUX1 synchronization Signal is LPTIM3 OUT             */
+#define HAL_DMAMUX1_SYNC_EXTI0             6U   /*!< DMAMUX1 synchronization Signal is EXTI0 IT               */
+#define HAL_DMAMUX1_SYNC_TIM12_TRGO        7U   /*!< DMAMUX1 synchronization Signal is TIM12 TRGO             */
+
+#define HAL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT   0U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel0 Event */
+#define HAL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT   1U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel1 Event */
+#define HAL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT   2U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel2 Event */
+#define HAL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT   3U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel3 Event */
+#define HAL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT   4U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel4 Event */
+#define HAL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT   5U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel5 Event */
+#define HAL_DMAMUX2_SYNC_LPUART1_RX_WKUP   6U   /*!< DMAMUX2 synchronization Signal is LPUART1 RX Wakeup      */
+#define HAL_DMAMUX2_SYNC_LPUART1_TX_WKUP   7U   /*!< DMAMUX2 synchronization Signal is LPUART1 TX Wakeup      */
+#define HAL_DMAMUX2_SYNC_LPTIM2_OUT        8U   /*!< DMAMUX2 synchronization Signal is LPTIM2 output          */
+#define HAL_DMAMUX2_SYNC_LPTIM3_OUT        9U   /*!< DMAMUX2 synchronization Signal is LPTIM3 output          */
+#define HAL_DMAMUX2_SYNC_I2C4_WKUP        10U   /*!< DMAMUX2 synchronization Signal is I2C4 Wakeup            */
+#define HAL_DMAMUX2_SYNC_SPI6_WKUP        11U   /*!< DMAMUX2 synchronization Signal is SPI6 Wakeup            */
+#define HAL_DMAMUX2_SYNC_COMP1_OUT        12U   /*!< DMAMUX2 synchronization Signal is Comparator 1 output    */
+#define HAL_DMAMUX2_SYNC_RTC_WKUP         13U   /*!< DMAMUX2 synchronization Signal is RTC Wakeup             */
+#define HAL_DMAMUX2_SYNC_EXTI0            14U   /*!< DMAMUX2 synchronization Signal is EXTI0 IT               */
+#define HAL_DMAMUX2_SYNC_EXTI2            15U   /*!< DMAMUX2 synchronization Signal is EXTI2 IT               */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMAEx_MUX_SyncPolarity_selection DMAEx MUX SyncPolarity selection
+  * @brief    DMAEx MUX SyncPolarity selection
+  * @{
+  */
+#define HAL_DMAMUX_SYNC_NO_EVENT        0x00000000U             /*!< block synchronization events                    */
+#define HAL_DMAMUX_SYNC_RISING          DMAMUX_CxCR_SPOL_0      /*!< synchronize with rising edge events             */
+#define HAL_DMAMUX_SYNC_FALLING         DMAMUX_CxCR_SPOL_1      /*!< synchronize with falling edge events            */
+#define HAL_DMAMUX_SYNC_RISING_FALLING  DMAMUX_CxCR_SPOL        /*!< synchronize with rising and falling edge events */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup DMAEx_MUX_SignalGeneratorID_selection DMAEx MUX SignalGeneratorID selection
+  * @brief    DMAEx MUX SignalGeneratorID selection
+  * @{
+  */
+#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT   0U   /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel0 Event */
+#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT   1U   /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel1 Event */
+#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT   2U   /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel2 Event */
+#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT        3U   /*!< DMAMUX1 Request generator Signal is LPTIM1 OUT             */
+#define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT        4U   /*!< DMAMUX1 Request generator Signal is LPTIM2 OUT             */
+#define HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT        5U   /*!< DMAMUX1 Request generator Signal is LPTIM3 OUT             */
+#define HAL_DMAMUX1_REQ_GEN_EXTI0             6U   /*!< DMAMUX1 Request generator Signal is EXTI0 IT               */
+#define HAL_DMAMUX1_REQ_GEN_TIM12_TRGO        7U   /*!< DMAMUX1 Request generator Signal is TIM12 TRGO             */
+
+#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT   0U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel0 Event */
+#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT   1U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel1 Event */
+#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT   2U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel2 Event */
+#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT   3U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel3 Event */
+#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT   4U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel4 Event */
+#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT   5U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel5 Event */
+#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT   6U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel6 Event */
+#define HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP   7U   /*!< DMAMUX2 Request generator Signal is LPUART1 RX Wakeup      */
+#define HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP   8U   /*!< DMAMUX2 Request generator Signal is LPUART1 TX Wakeup      */
+#define HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP       9U   /*!< DMAMUX2 Request generator Signal is LPTIM2 Wakeup          */
+#define HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT       10U   /*!< DMAMUX2 Request generator Signal is LPTIM2 OUT             */
+#define HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP      11U   /*!< DMAMUX2 Request generator Signal is LPTIM3 Wakeup          */
+#define HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT       12U   /*!< DMAMUX2 Request generator Signal is LPTIM3 OUT             */
+#if defined(LPTIM4)
+#define HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP      13U   /*!< DMAMUX2 Request generator Signal is LPTIM4 Wakeup          */
+#endif /* LPTIM4 */
+#if defined(LPTIM5)
+#define HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP      14U   /*!< DMAMUX2 Request generator Signal is LPTIM5 Wakeup          */
+#endif /* LPTIM5 */
+#define HAL_DMAMUX2_REQ_GEN_I2C4_WKUP        15U   /*!< DMAMUX2 Request generator Signal is I2C4 Wakeup            */
+#define HAL_DMAMUX2_REQ_GEN_SPI6_WKUP        16U   /*!< DMAMUX2 Request generator Signal is SPI6 Wakeup            */
+#define HAL_DMAMUX2_REQ_GEN_COMP1_OUT        17U   /*!< DMAMUX2 Request generator Signal is Comparator 1 output    */
+#define HAL_DMAMUX2_REQ_GEN_COMP2_OUT        18U   /*!< DMAMUX2 Request generator Signal is Comparator 2 output    */
+#define HAL_DMAMUX2_REQ_GEN_RTC_WKUP         19U   /*!< DMAMUX2 Request generator Signal is RTC Wakeup             */
+#define HAL_DMAMUX2_REQ_GEN_EXTI0            20U   /*!< DMAMUX2 Request generator Signal is EXTI0                  */
+#define HAL_DMAMUX2_REQ_GEN_EXTI2            21U   /*!< DMAMUX2 Request generator Signal is EXTI2                  */
+#define HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT      22U   /*!< DMAMUX2 Request generator Signal is I2C4 IT Event          */
+#define HAL_DMAMUX2_REQ_GEN_SPI6_IT          23U   /*!< DMAMUX2 Request generator Signal is SPI6 IT                */
+#define HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT    24U   /*!< DMAMUX2 Request generator Signal is LPUART1 Tx IT          */
+#define HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT    25U   /*!< DMAMUX2 Request generator Signal is LPUART1 Rx IT          */
+#if defined(ADC3)
+#define HAL_DMAMUX2_REQ_GEN_ADC3_IT          26U   /*!< DMAMUX2 Request generator Signal is ADC3 IT                */
+#define HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT    27U   /*!< DMAMUX2 Request generator Signal is ADC3 Analog Watchdog 1 output */
+#endif /* ADC3 */
+#define HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT      28U   /*!< DMAMUX2 Request generator Signal is BDMA Channel 0 IT      */
+#define HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT      29U   /*!< DMAMUX2 Request generator Signal is BDMA Channel 1 IT      */
+
+
+/**
+  * @}
+  */
+
+/** @defgroup DMAEx_MUX_RequestGeneneratorPolarity_selection DMAEx MUX RequestGeneneratorPolarity selection
+  * @brief    DMAEx MUX RequestGeneneratorPolarity selection
+  * @{
+  */
+#define HAL_DMAMUX_REQ_GEN_NO_EVENT        0x00000000U           /*!< block request generator events                     */
+#define HAL_DMAMUX_REQ_GEN_RISING          DMAMUX_RGxCR_GPOL_0  /*!< generate request on rising edge events             */
+#define HAL_DMAMUX_REQ_GEN_FALLING         DMAMUX_RGxCR_GPOL_1  /*!< generate request on falling edge events            */
+#define HAL_DMAMUX_REQ_GEN_RISING_FALLING  DMAMUX_RGxCR_GPOL    /*!< generate request on rising and falling edge events */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
+  * @brief   DMAEx Exported functions
+  * @{
+  */
+
+/** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions
+  * @brief   Extended features functions
+  * @{
+  */
+
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory);
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig);
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig);
+HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma);
+
+void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DMAEx_Private_Macros DMA Private Macros
+  * @brief    DMAEx private macros
+  * @{
+  */
+
+#define IS_DMA_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_TIM12_TRGO)
+#define IS_BDMA_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX2_SYNC_EXTI2)
+
+#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
+
+#define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT)    || \
+                                           ((POLARITY) == HAL_DMAMUX_SYNC_RISING)   || \
+                                           ((POLARITY) == HAL_DMAMUX_SYNC_FALLING)  || \
+                                           ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING))
+
+#define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE)   || ((SYNC) == ENABLE))
+
+#define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE)   || \
+                                     ((EVENT) == ENABLE))
+
+#define IS_DMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_TIM12_TRGO)
+#define IS_BDMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT)
+
+#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
+
+#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT) || \
+                                                  ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING)   || \
+                                                  ((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING)   || \
+                                                  ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING))
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DMAEx_Private_Functions DMAEx Private Functions
+  * @brief DMAEx Private functions
+  * @{
+  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h
new file mode 100644
index 00000000..6273f3c3
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h
@@ -0,0 +1,507 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_exti.h
+  * @author  MCD Application Team
+  * @brief   Header file of EXTI HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_EXTI_H
+#define STM32H7xx_HAL_EXTI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup EXTI EXTI
+  * @brief EXTI HAL module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup EXTI_Exported_Types EXTI Exported Types
+  * @{
+  */
+typedef enum
+{
+  HAL_EXTI_COMMON_CB_ID          = 0x00U,
+} EXTI_CallbackIDTypeDef;
+
+
+/**
+  * @brief  EXTI Handle structure definition
+  */
+typedef struct
+{
+  uint32_t Line;                    /*!<  Exti line number */
+  void (* PendingCallback)(void);   /*!<  Exti pending callback */
+} EXTI_HandleTypeDef;
+
+/**
+  * @brief  EXTI Configuration structure definition
+  */
+typedef struct
+{
+  uint32_t Line;           /*!< The Exti line to be configured. This parameter
+                                can be a value of @ref EXTI_Line */
+  uint32_t Mode;           /*!< The Exit Mode to be configured for a core.
+                                This parameter can be a combination of @ref EXTI_Mode */
+  uint32_t Trigger;        /*!< The Exti Trigger to be configured. This parameter
+                                can be a value of @ref EXTI_Trigger */
+  uint32_t GPIOSel;        /*!< The Exti GPIO multiplexer selection to be configured.
+                                This parameter is only possible for line 0 to 15. It
+                                can be a value of @ref EXTI_GPIOSel */
+
+  uint32_t PendClearSource; /*!< Specifies the event pending clear source for D3/SRD
+                                 domain. This parameter can be a value of @ref
+                                 EXTI_PendClear_Source */
+
+} EXTI_ConfigTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
+  * @{
+  */
+
+/** @defgroup EXTI_Line  EXTI Line
+  * @{
+  */
+#define EXTI_LINE_0                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x00U)
+#define EXTI_LINE_1                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x01U)
+#define EXTI_LINE_2                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x02U)
+#define EXTI_LINE_3                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x03U)
+#define EXTI_LINE_4                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x04U)
+#define EXTI_LINE_5                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x05U)
+#define EXTI_LINE_6                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x06U)
+#define EXTI_LINE_7                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x07U)
+#define EXTI_LINE_8                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x08U)
+#define EXTI_LINE_9                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x09U)
+#define EXTI_LINE_10                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x0AU)
+#define EXTI_LINE_11                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x0BU)
+#define EXTI_LINE_12                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x0CU)
+#define EXTI_LINE_13                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x0DU)
+#define EXTI_LINE_14                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x0EU)
+#define EXTI_LINE_15                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x0FU)
+#define EXTI_LINE_16                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x10U)
+#define EXTI_LINE_17                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x11U)
+#define EXTI_LINE_18                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x12U)
+#define EXTI_LINE_19                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x13U)
+#define EXTI_LINE_20                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x14U)
+#define EXTI_LINE_21                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x15U)
+#define EXTI_LINE_22                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x16U)
+#define EXTI_LINE_23                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x17U)
+#define EXTI_LINE_24                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x18U)
+#define EXTI_LINE_25                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x19U)
+#define EXTI_LINE_26                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1AU)
+#define EXTI_LINE_27                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1BU)
+#define EXTI_LINE_28                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1CU)
+#define EXTI_LINE_29                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1DU)
+#define EXTI_LINE_30                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1EU)
+#define EXTI_LINE_31                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1FU)
+#define EXTI_LINE_32                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x00U)
+#define EXTI_LINE_33                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x01U)
+#define EXTI_LINE_34                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x02U)
+#define EXTI_LINE_35                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x03U)
+#define EXTI_LINE_36                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x04U)
+#define EXTI_LINE_37                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x05U)
+#define EXTI_LINE_38                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x06U)
+#define EXTI_LINE_39                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x07U)
+#define EXTI_LINE_40                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x08U)
+#define EXTI_LINE_41                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x09U)
+#define EXTI_LINE_42                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0AU)
+#define EXTI_LINE_43                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0BU)
+#if !defined(USB2_OTG_FS)
+#define EXTI_LINE_44                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE    | 0x0CU)
+#else
+#define EXTI_LINE_44                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0CU)
+#endif /* USB2_OTG_FS */
+#define EXTI_LINE_45                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE    | 0x0DU)
+#if defined(DSI)
+#define EXTI_LINE_46                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0EU)
+#else
+#define EXTI_LINE_46                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE    | 0x0EU)
+#endif /* DSI */
+#define EXTI_LINE_47                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0FU)
+#define EXTI_LINE_48                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x10U)
+#define EXTI_LINE_49                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x11U)
+#define EXTI_LINE_50                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x12U)
+#define EXTI_LINE_51                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x13U)
+#if !defined(UART9)
+#define EXTI_LINE_52                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x14U)
+#else
+#define EXTI_LINE_52                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x14U)
+#endif /* UART9 */
+#if !defined(USART10)
+#define EXTI_LINE_53                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x15U)
+#else
+#define EXTI_LINE_53                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x15U)
+#endif /* USART10 */
+#define EXTI_LINE_54                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x16U)
+#define EXTI_LINE_55                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x17U)
+#define EXTI_LINE_56                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x18U)
+#define EXTI_LINE_57                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x19U)
+#define EXTI_LINE_58                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1AU)
+#define EXTI_LINE_59                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1BU)
+#define EXTI_LINE_60                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1CU)
+#define EXTI_LINE_61                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1DU)
+#define EXTI_LINE_62                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1EU)
+#define EXTI_LINE_63                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1FU)
+#define EXTI_LINE_64                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x00U)
+#define EXTI_LINE_65                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x01U)
+#define EXTI_LINE_66                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x02U)
+#define EXTI_LINE_67                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x03U)
+#define EXTI_LINE_68                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x04U)
+#define EXTI_LINE_69                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x05U)
+#define EXTI_LINE_70                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x06U)
+#define EXTI_LINE_71                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x07U)
+#define EXTI_LINE_72                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x08U)
+#define EXTI_LINE_73                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x09U)
+#define EXTI_LINE_74                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0AU)
+#if defined(ADC3)
+#define EXTI_LINE_75                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0BU)
+#else
+#define EXTI_LINE_75                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 |  EXTI_TARGET_MSK_NONE   | 0x0BU)
+#endif /* ADC3 */
+#if defined(SAI4)
+#define EXTI_LINE_76                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0CU)
+#else
+#define EXTI_LINE_76                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 |  EXTI_TARGET_MSK_NONE   | 0x0CU)
+#endif /* SAI4 */
+#if defined (DUAL_CORE)
+#define EXTI_LINE_77                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x0DU)
+#define EXTI_LINE_78                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU2| 0x0EU)
+#define EXTI_LINE_79                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x0FU)
+#define EXTI_LINE_80                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU2| 0x10U)
+#else
+#define EXTI_LINE_77                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0DU)
+#define EXTI_LINE_78                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0EU)
+#define EXTI_LINE_79                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0FU)
+#define EXTI_LINE_80                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x10U)
+#endif /* DUAL_CORE */
+
+#define EXTI_LINE_81                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x11U)
+
+#if defined (DUAL_CORE)
+#define EXTI_LINE_82                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU2| 0x12U)
+#else
+#define EXTI_LINE_82                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x12U)
+#endif /* DUAL_CORE */
+
+#define EXTI_LINE_83                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x13U)
+#if defined (DUAL_CORE)
+#define EXTI_LINE_84                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x14U)
+#else
+#define EXTI_LINE_84                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x14U)
+#endif /* DUAL_CORE */
+#define EXTI_LINE_85                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x15U)
+#if defined(ETH)
+#define EXTI_LINE_86                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x16U)
+#else
+#define EXTI_LINE_86                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x16U)
+#endif /* ETH */
+#define EXTI_LINE_87                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x17U)
+#if defined(DTS)
+#define EXTI_LINE_88                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL | 0x18U)
+#endif /* DTS */
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Mode  EXTI Mode
+  * @{
+  */
+#define EXTI_MODE_NONE                      0x00000000U
+#define EXTI_MODE_INTERRUPT                 0x00000001U
+#define EXTI_MODE_EVENT                     0x00000002U
+#if defined(DUAL_CORE)
+#define EXTI_MODE_CORE1_INTERRUPT           EXTI_MODE_INTERRUPT
+#define EXTI_MODE_CORE1_EVENT               EXTI_MODE_EVENT
+#define EXTI_MODE_CORE2_INTERRUPT           0x00000010U
+#define EXTI_MODE_CORE2_EVENT               0x00000020U
+#endif /* DUAL_CORE */
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Trigger  EXTI Trigger
+  * @{
+  */
+#define EXTI_TRIGGER_NONE                   0x00000000U
+#define EXTI_TRIGGER_RISING                 0x00000001U
+#define EXTI_TRIGGER_FALLING                0x00000002U
+#define EXTI_TRIGGER_RISING_FALLING         (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_GPIOSel  EXTI GPIOSel
+  * @brief
+  * @{
+  */
+#define EXTI_GPIOA                          0x00000000U
+#define EXTI_GPIOB                          0x00000001U
+#define EXTI_GPIOC                          0x00000002U
+#define EXTI_GPIOD                          0x00000003U
+#define EXTI_GPIOE                          0x00000004U
+#define EXTI_GPIOF                          0x00000005U
+#define EXTI_GPIOG                          0x00000006U
+#define EXTI_GPIOH                          0x00000007U
+#define EXTI_GPIOI                          0x00000008U
+#define EXTI_GPIOJ                          0x00000009U
+#define EXTI_GPIOK                          0x0000000AU
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_PendClear_Source  EXTI PendClear Source
+  * @brief
+  * @{
+  */
+#define EXTI_D3_PENDCLR_SRC_NONE       0x00000000U /*!< No D3 domain pendclear source , PMRx register to be set to zero  */
+#define EXTI_D3_PENDCLR_SRC_DMACH6     0x00000001U /*!< DMA ch6 event selected as D3 domain pendclear source, PMRx register to be set to 1 */
+#define EXTI_D3_PENDCLR_SRC_DMACH7     0x00000002U /*!< DMA ch7 event selected as D3 domain pendclear source, PMRx register to be set to 1*/
+#if defined (LPTIM4)
+#define EXTI_D3_PENDCLR_SRC_LPTIM4     0x00000003U /*!< LPTIM4 out selected as D3 domain pendclear source, PMRx register to be set to 1    */
+#else
+#define EXTI_D3_PENDCLR_SRC_LPTIM2     0x00000003U /*!< LPTIM2 out selected as D3 domain pendclear source, PMRx register to be set to 1    */
+#endif
+#if defined (LPTIM5)
+#define EXTI_D3_PENDCLR_SRC_LPTIM5     0x00000004U /*!< LPTIM5 out selected as D3 domain pendclear source, PMRx register to be set to 1    */
+#else
+#define EXTI_D3_PENDCLR_SRC_LPTIM3     0x00000004U /*!< LPTIM3 out selected as D3 domain pendclear source, PMRx register to be set to 1    */
+#endif
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants --------------------------------------------------------*/
+/** @defgroup EXTI_Private_Constants EXTI Private Constants
+  * @{
+  */
+/**
+  * @brief  EXTI Line property definition
+  */
+#define EXTI_PROPERTY_SHIFT                 24U
+#define EXTI_DIRECT                         (0x01UL << EXTI_PROPERTY_SHIFT)
+#define EXTI_CONFIG                         (0x02UL << EXTI_PROPERTY_SHIFT)
+#define EXTI_GPIO                           ((0x04UL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
+#define EXTI_RESERVED                       (0x08UL << EXTI_PROPERTY_SHIFT)
+#define EXTI_PROPERTY_MASK                  (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
+
+/**
+  * @brief  EXTI Event presence definition
+  */
+#define EXTI_EVENT_PRESENCE_SHIFT           28U
+#define EXTI_EVENT                          (0x01UL << EXTI_EVENT_PRESENCE_SHIFT)
+#define EXTI_EVENT_PRESENCE_MASK            (EXTI_EVENT)
+
+/**
+  * @brief  EXTI Register and bit usage
+  */
+#define EXTI_REG_SHIFT                      16U
+#define EXTI_REG1                           (0x00UL << EXTI_REG_SHIFT)
+#define EXTI_REG2                           (0x01UL << EXTI_REG_SHIFT)
+#define EXTI_REG3                           (0x02UL << EXTI_REG_SHIFT)
+#define EXTI_REG_MASK                       (EXTI_REG1 | EXTI_REG2 | EXTI_REG3)
+#define EXTI_PIN_MASK                       0x0000001FUL
+
+/**
+  * @brief  EXTI Target and bit usage
+  */
+#define EXTI_TARGET_SHIFT                   20U
+#define EXTI_TARGET_MSK_NONE                (0x00UL << EXTI_TARGET_SHIFT)
+#define EXTI_TARGET_MSK_D3SRD               (0x01UL << EXTI_TARGET_SHIFT)
+#define EXTI_TARGET_MSK_CPU1                (0x02UL << EXTI_TARGET_SHIFT)
+#if defined (DUAL_CORE)
+#define EXTI_TARGET_MSK_CPU2                (0x04UL << EXTI_TARGET_SHIFT)
+#define EXTI_TARGET_MASK                    (EXTI_TARGET_MSK_D3SRD | EXTI_TARGET_MSK_CPU1 | EXTI_TARGET_MSK_CPU2)
+#define EXTI_TARGET_MSK_ALL_CPU             (EXTI_TARGET_MSK_CPU1 | EXTI_TARGET_MSK_CPU2)
+#else
+#define EXTI_TARGET_MASK                    (EXTI_TARGET_MSK_D3SRD | EXTI_TARGET_MSK_CPU1)
+#define EXTI_TARGET_MSK_ALL_CPU              EXTI_TARGET_MSK_CPU1
+#endif /* DUAL_CORE */
+#define EXTI_TARGET_MSK_ALL                  EXTI_TARGET_MASK
+
+/**
+  * @brief  EXTI Mask for interrupt & event mode
+  */
+#if defined (DUAL_CORE)
+#define EXTI_MODE_MASK                      (EXTI_MODE_CORE1_EVENT | EXTI_MODE_CORE1_INTERRUPT | EXTI_MODE_CORE2_INTERRUPT | EXTI_MODE_CORE2_EVENT)
+#else
+#define EXTI_MODE_MASK                      (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
+#endif /* DUAL_CORE */
+
+/**
+  * @brief  EXTI Mask for trigger possibilities
+  */
+#define EXTI_TRIGGER_MASK                   (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
+
+/**
+  * @brief  EXTI Line number
+  */
+#if defined (EXTI_LINE_88)
+#define EXTI_LINE_NB                        89UL
+#else
+#define EXTI_LINE_NB                        88UL
+#endif /* EXTI_LINE_88 */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup EXTI_Private_Macros EXTI Private Macros
+  * @{
+  */
+#define IS_EXTI_PROPERTY(__LINE__)      ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
+                                         (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG)          || \
+                                         (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO))
+#if defined (DUAL_CORE)
+#define IS_EXTI_TARGET(__LINE__)        ((((__LINE__) & EXTI_TARGET_MASK)   == EXTI_TARGET_MSK_CPU1)      || \
+                                         (((__LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_CPU2)    || \
+                                         (((__LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL_CPU) || \
+                                         (((__LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL))
+#else
+#define IS_EXTI_TARGET(__LINE__)        ((((__LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_CPU1)   || \
+                                         (((__LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL))
+#endif
+
+#define IS_EXTI_LINE(__LINE__)          ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_EVENT_PRESENCE_MASK | EXTI_REG_MASK | EXTI_PIN_MASK | EXTI_TARGET_MASK)) == 0x00UL) && \
+                                         IS_EXTI_PROPERTY(__LINE__) && IS_EXTI_TARGET(__LINE__) && \
+                                         (((__LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK))      < \
+                                         (((EXTI_LINE_NB / 32UL) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32UL))))
+
+#define IS_EXTI_MODE(__MODE__)          (((__MODE__) & ~EXTI_MODE_MASK) == 0x00UL)
+
+#define IS_EXTI_TRIGGER(__LINE__)       (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00UL)
+
+#define IS_EXTI_PENDING_EDGE(__LINE__)  (((__LINE__) == EXTI_TRIGGER_RISING) || \
+                                         ((__LINE__) == EXTI_TRIGGER_FALLING)|| \
+                                         ((__LINE__) == EXTI_TRIGGER_RISING_FALLING))
+
+#define IS_EXTI_CONFIG_LINE(__LINE__)   (((__LINE__) & EXTI_CONFIG) != 0x00UL)
+
+#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \
+                                         ((__PORT__) == EXTI_GPIOB) || \
+                                         ((__PORT__) == EXTI_GPIOC) || \
+                                         ((__PORT__) == EXTI_GPIOD) || \
+                                         ((__PORT__) == EXTI_GPIOE) || \
+                                         ((__PORT__) == EXTI_GPIOF) || \
+                                         ((__PORT__) == EXTI_GPIOG) || \
+                                         ((__PORT__) == EXTI_GPIOH) || \
+                                         ((__PORT__) == EXTI_GPIOI) || \
+                                         ((__PORT__) == EXTI_GPIOJ) || \
+                                         ((__PORT__) == EXTI_GPIOK))
+
+#define IS_EXTI_GPIO_PIN(__PIN__)       ((__PIN__) < 16UL)
+#if defined (LPTIM4) && defined (LPTIM5)
+#define IS_EXTI_D3_PENDCLR_SRC(__SRC__) (((__SRC__) == EXTI_D3_PENDCLR_SRC_NONE) || \
+                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH6) || \
+                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH7) || \
+                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM4) || \
+                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM5))
+#else
+#define IS_EXTI_D3_PENDCLR_SRC(__SRC__) (((__SRC__) == EXTI_D3_PENDCLR_SRC_NONE) || \
+                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH6) || \
+                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH7) || \
+                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM2) || \
+                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM3))
+#endif /* LPTIM4 && LPTIM5 */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
+  * @brief    EXTI Exported Functions
+  * @{
+  */
+
+/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
+  * @brief    Configuration functions
+  * @{
+  */
+/* Configuration functions ****************************************************/
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
+HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
+HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
+HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
+HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
+  * @brief    IO operation functions
+  * @{
+  */
+/* IO operation functions *****************************************************/
+void              HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
+uint32_t          HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
+void              HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
+void              HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_EXTI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h
new file mode 100644
index 00000000..cfe58cf7
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h
@@ -0,0 +1,2414 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_fdcan.h
+  * @author  MCD Application Team
+  * @brief   Header file of FDCAN HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_FDCAN_H
+#define STM32H7xx_HAL_FDCAN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FDCAN
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FDCAN_Exported_Types FDCAN Exported Types
+  * @{
+  */
+
+/**
+  * @brief HAL State structures definition
+  */
+typedef enum
+{
+  HAL_FDCAN_STATE_RESET      = 0x00U, /*!< FDCAN not yet initialized or disabled */
+  HAL_FDCAN_STATE_READY      = 0x01U, /*!< FDCAN initialized and ready for use   */
+  HAL_FDCAN_STATE_BUSY       = 0x02U, /*!< FDCAN process is ongoing              */
+  HAL_FDCAN_STATE_ERROR      = 0x03U  /*!< FDCAN error state                     */
+} HAL_FDCAN_StateTypeDef;
+
+/**
+  * @brief FDCAN Init structure definition
+  */
+typedef struct
+{
+  uint32_t FrameFormat;                  /*!< Specifies the FDCAN frame format.
+                                              This parameter can be a value of @ref FDCAN_frame_format     */
+
+  uint32_t Mode;                         /*!< Specifies the FDCAN mode.
+                                              This parameter can be a value of @ref FDCAN_operating_mode   */
+
+  FunctionalState AutoRetransmission;    /*!< Enable or disable the automatic retransmission mode.
+                                              This parameter can be set to ENABLE or DISABLE               */
+
+  FunctionalState TransmitPause;         /*!< Enable or disable the Transmit Pause feature.
+                                              This parameter can be set to ENABLE or DISABLE               */
+
+  FunctionalState ProtocolException;      /*!< Enable or disable the Protocol Exception Handling.
+                                              This parameter can be set to ENABLE or DISABLE               */
+
+  uint32_t NominalPrescaler;             /*!< Specifies the value by which the oscillator frequency is
+                                              divided for generating the nominal bit time quanta.
+                                              This parameter must be a number between 1 and 512            */
+
+  uint32_t NominalSyncJumpWidth;         /*!< Specifies the maximum number of time quanta the FDCAN
+                                              hardware is allowed to lengthen or shorten a bit to perform
+                                              resynchronization.
+                                              This parameter must be a number between 1 and 128            */
+
+  uint32_t NominalTimeSeg1;              /*!< Specifies the number of time quanta in Bit Segment 1.
+                                              This parameter must be a number between 2 and 256            */
+
+  uint32_t NominalTimeSeg2;              /*!< Specifies the number of time quanta in Bit Segment 2.
+                                              This parameter must be a number between 2 and 128            */
+
+  uint32_t DataPrescaler;                /*!< Specifies the value by which the oscillator frequency is
+                                              divided for generating the data bit time quanta.
+                                              This parameter must be a number between 1 and 32             */
+
+  uint32_t DataSyncJumpWidth;            /*!< Specifies the maximum number of time quanta the FDCAN
+                                              hardware is allowed to lengthen or shorten a data bit to
+                                              perform resynchronization.
+                                              This parameter must be a number between 1 and 16             */
+
+  uint32_t DataTimeSeg1;                 /*!< Specifies the number of time quanta in Data Bit Segment 1.
+                                              This parameter must be a number between 1 and 32             */
+
+  uint32_t DataTimeSeg2;                 /*!< Specifies the number of time quanta in Data Bit Segment 2.
+                                              This parameter must be a number between 1 and 16             */
+
+  uint32_t MessageRAMOffset;             /*!< Specifies the message RAM start address.
+                                              This parameter must be a number between 0 and 2560           */
+
+  uint32_t StdFiltersNbr;                /*!< Specifies the number of standard Message ID filters.
+                                              This parameter must be a number between 0 and 128            */
+
+  uint32_t ExtFiltersNbr;                /*!< Specifies the number of extended Message ID filters.
+                                              This parameter must be a number between 0 and 64             */
+
+  uint32_t RxFifo0ElmtsNbr;              /*!< Specifies the number of Rx FIFO0 Elements.
+                                              This parameter must be a number between 0 and 64             */
+
+  uint32_t RxFifo0ElmtSize;              /*!< Specifies the Data Field Size in an Rx FIFO 0 element.
+                                              This parameter can be a value of @ref FDCAN_data_field_size  */
+
+  uint32_t RxFifo1ElmtsNbr;              /*!< Specifies the number of Rx FIFO 1 Elements.
+                                              This parameter must be a number between 0 and 64             */
+
+  uint32_t RxFifo1ElmtSize;              /*!< Specifies the Data Field Size in an Rx FIFO 1 element.
+                                              This parameter can be a value of @ref FDCAN_data_field_size  */
+
+  uint32_t RxBuffersNbr;                 /*!< Specifies the number of Dedicated Rx Buffer elements.
+                                              This parameter must be a number between 0 and 64             */
+
+  uint32_t RxBufferSize;                 /*!< Specifies the Data Field Size in an Rx Buffer element.
+                                              This parameter can be a value of @ref FDCAN_data_field_size  */
+
+  uint32_t TxEventsNbr;                  /*!< Specifies the number of Tx Event FIFO elements.
+                                              This parameter must be a number between 0 and 32             */
+
+  uint32_t TxBuffersNbr;                 /*!< Specifies the number of Dedicated Tx Buffers.
+                                              This parameter must be a number between 0 and 32             */
+
+  uint32_t TxFifoQueueElmtsNbr;          /*!< Specifies the number of Tx Buffers used for Tx FIFO/Queue.
+                                              This parameter must be a number between 0 and 32             */
+
+  uint32_t TxFifoQueueMode;              /*!< Tx FIFO/Queue Mode selection.
+                                              This parameter can be a value of @ref FDCAN_txFifoQueue_Mode */
+
+  uint32_t TxElmtSize;                   /*!< Specifies the Data Field Size in a Tx Element.
+                                              This parameter can be a value of @ref FDCAN_data_field_size  */
+
+} FDCAN_InitTypeDef;
+
+/**
+  * @brief  FDCAN clock calibration unit structure definition
+  */
+typedef struct
+{
+  uint32_t ClockCalibration;     /*!< Enable or disable the clock calibration.
+                                      This parameter can be a value of @ref FDCAN_clock_calibration.       */
+
+  uint32_t ClockDivider;         /*!< Specifies the FDCAN kernel clock divider when the clock calibration
+                                      is bypassed.
+                                      This parameter can be a value of @ref FDCAN_clock_divider            */
+
+  uint32_t MinOscClkPeriods;     /*!< Configures the minimum number of periods in two CAN bit times. The
+                                      actual configured number of periods is MinOscClkPeriods x 32.
+                                      This parameter must be a number between 0x00 and 0xFF                */
+
+  uint32_t CalFieldLength;       /*!< Specifies the calibration field length.
+                                      This parameter can be a value of @ref FDCAN_calibration_field_length */
+
+  uint32_t TimeQuantaPerBitTime; /*!< Configures the number of time quanta per bit time.
+                                      This parameter must be a number between 4 and 25                     */
+
+  uint32_t WatchdogStartValue;   /*!< Start value of the Calibration Watchdog Counter.
+                                      If set to zero the counter is disabled.
+                                      This parameter must be a number between 0x0000 and 0xFFFF            */
+
+} FDCAN_ClkCalUnitTypeDef;
+
+/**
+  * @brief  FDCAN filter structure definition
+  */
+typedef struct
+{
+  uint32_t IdType;           /*!< Specifies the identifier type.
+                                  This parameter can be a value of @ref FDCAN_id_type       */
+
+  uint32_t FilterIndex;      /*!< Specifies the filter which will be initialized.
+                                  This parameter must be a number between:
+                                   - 0 and 127, if IdType is FDCAN_STANDARD_ID
+                                   - 0 and 63, if IdType is FDCAN_EXTENDED_ID               */
+
+  uint32_t FilterType;       /*!< Specifies the filter type.
+                                  This parameter can be a value of @ref FDCAN_filter_type.
+                                  The value FDCAN_EXT_FILTER_RANGE_NO_EIDM is permitted
+                                  only when IdType is FDCAN_EXTENDED_ID.
+                                  This parameter is ignored if FilterConfig is set to
+                                  FDCAN_FILTER_TO_RXBUFFER                                  */
+
+  uint32_t FilterConfig;     /*!< Specifies the filter configuration.
+                                  This parameter can be a value of @ref FDCAN_filter_config */
+
+  uint32_t FilterID1;        /*!< Specifies the filter identification 1.
+                                  This parameter must be a number between:
+                                   - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+                                   - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID       */
+
+  uint32_t FilterID2;        /*!< Specifies the filter identification 2.
+                                  This parameter is ignored if FilterConfig is set to
+                                  FDCAN_FILTER_TO_RXBUFFER.
+                                  This parameter must be a number between:
+                                   - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+                                   - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID       */
+
+  uint32_t RxBufferIndex;    /*!< Contains the index of the Rx buffer in which the
+                                  matching message will be stored.
+                                  This parameter must be a number between 0 and 63.
+                                  This parameter is ignored if FilterConfig is different
+                                  from FDCAN_FILTER_TO_RXBUFFER                             */
+
+  uint32_t IsCalibrationMsg; /*!< Specifies whether the filter is configured for
+                                  calibration messages.
+                                  This parameter is ignored if FilterConfig is different
+                                  from FDCAN_FILTER_TO_RXBUFFER.
+                                  This parameter can be:
+                                   - 0 : ordinary message
+                                   - 1 : calibration message                                */
+
+} FDCAN_FilterTypeDef;
+
+/**
+  * @brief  FDCAN Tx header structure definition
+  */
+typedef struct
+{
+  uint32_t Identifier;          /*!< Specifies the identifier.
+                                     This parameter must be a number between:
+                                      - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+                                      - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID               */
+
+  uint32_t IdType;              /*!< Specifies the identifier type for the message that will be
+                                     transmitted.
+                                     This parameter can be a value of @ref FDCAN_id_type               */
+
+  uint32_t TxFrameType;         /*!< Specifies the frame type of the message that will be transmitted.
+                                     This parameter can be a value of @ref FDCAN_frame_type            */
+
+  uint32_t DataLength;          /*!< Specifies the length of the frame that will be transmitted.
+                                      This parameter can be a value of @ref FDCAN_data_length_code     */
+
+  uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
+                                     This parameter can be a value of @ref FDCAN_error_state_indicator */
+
+  uint32_t BitRateSwitch;       /*!< Specifies whether the Tx frame will be transmitted with or without
+                                     bit rate switching.
+                                     This parameter can be a value of @ref FDCAN_bit_rate_switching    */
+
+  uint32_t FDFormat;            /*!< Specifies whether the Tx frame will be transmitted in classic or
+                                     FD format.
+                                     This parameter can be a value of @ref FDCAN_format                */
+
+  uint32_t TxEventFifoControl;  /*!< Specifies the event FIFO control.
+                                     This parameter can be a value of @ref FDCAN_EFC                   */
+
+  uint32_t MessageMarker;       /*!< Specifies the message marker to be copied into Tx Event FIFO
+                                     element for identification of Tx message status.
+                                     This parameter must be a number between 0 and 0xFF                */
+
+} FDCAN_TxHeaderTypeDef;
+
+/**
+  * @brief  FDCAN Rx header structure definition
+  */
+typedef struct
+{
+  uint32_t Identifier;            /*!< Specifies the identifier.
+                                       This parameter must be a number between:
+                                        - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+                                        - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID               */
+
+  uint32_t IdType;                /*!< Specifies the identifier type of the received message.
+                                       This parameter can be a value of @ref FDCAN_id_type               */
+
+  uint32_t RxFrameType;           /*!< Specifies the the received message frame type.
+                                       This parameter can be a value of @ref FDCAN_frame_type            */
+
+  uint32_t DataLength;            /*!< Specifies the received frame length.
+                                        This parameter can be a value of @ref FDCAN_data_length_code     */
+
+  uint32_t ErrorStateIndicator;   /*!< Specifies the error state indicator.
+                                       This parameter can be a value of @ref FDCAN_error_state_indicator */
+
+  uint32_t BitRateSwitch;         /*!< Specifies whether the Rx frame is received with or without bit
+                                       rate switching.
+                                       This parameter can be a value of @ref FDCAN_bit_rate_switching    */
+
+  uint32_t FDFormat;              /*!< Specifies whether the Rx frame is received in classic or FD
+                                       format.
+                                       This parameter can be a value of @ref FDCAN_format                */
+
+  uint32_t RxTimestamp;           /*!< Specifies the timestamp counter value captured on start of frame
+                                       reception.
+                                       This parameter must be a number between 0 and 0xFFFF              */
+
+  uint32_t FilterIndex;           /*!< Specifies the index of matching Rx acceptance filter element.
+                                       This parameter must be a number between:
+                                        - 0 and 127, if IdType is FDCAN_STANDARD_ID
+                                        - 0 and 63, if IdType is FDCAN_EXTENDED_ID                       */
+
+  uint32_t IsFilterMatchingFrame; /*!< Specifies whether the accepted frame did not match any Rx filter.
+                                         Acceptance of non-matching frames may be enabled via
+                                         HAL_FDCAN_ConfigGlobalFilter().
+                                         This parameter can be 0 or 1                                    */
+
+} FDCAN_RxHeaderTypeDef;
+
+/**
+  * @brief  FDCAN Tx event FIFO structure definition
+  */
+typedef struct
+{
+  uint32_t Identifier;          /*!< Specifies the identifier.
+                                     This parameter must be a number between:
+                                      - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+                                      - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID               */
+
+  uint32_t IdType;              /*!< Specifies the identifier type for the transmitted message.
+                                     This parameter can be a value of @ref FDCAN_id_type               */
+
+  uint32_t TxFrameType;         /*!< Specifies the frame type of the transmitted message.
+                                     This parameter can be a value of @ref FDCAN_frame_type            */
+
+  uint32_t DataLength;          /*!< Specifies the length of the transmitted frame.
+                                     This parameter can be a value of @ref FDCAN_data_length_code      */
+
+  uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
+                                     This parameter can be a value of @ref FDCAN_error_state_indicator */
+
+  uint32_t BitRateSwitch;       /*!< Specifies whether the Tx frame is transmitted with or without bit
+                                     rate switching.
+                                     This parameter can be a value of @ref FDCAN_bit_rate_switching    */
+
+  uint32_t FDFormat;            /*!< Specifies whether the Tx frame is transmitted in classic or FD
+                                     format.
+                                     This parameter can be a value of @ref FDCAN_format                */
+
+  uint32_t TxTimestamp;         /*!< Specifies the timestamp counter value captured on start of frame
+                                     transmission.
+                                     This parameter must be a number between 0 and 0xFFFF              */
+
+  uint32_t MessageMarker;       /*!< Specifies the message marker copied into Tx Event FIFO element
+                                     for identification of Tx message status.
+                                     This parameter must be a number between 0 and 0xFF                */
+
+  uint32_t EventType;           /*!< Specifies the event type.
+                                     This parameter can be a value of @ref FDCAN_event_type            */
+
+} FDCAN_TxEventFifoTypeDef;
+
+/**
+  * @brief  FDCAN High Priority Message Status structure definition
+  */
+typedef struct
+{
+  uint32_t FilterList;     /*!< Specifies the filter list of the matching filter element.
+                                This parameter can be:
+                                 - 0 : Standard Filter List
+                                 - 1 : Extended Filter List                                */
+
+  uint32_t FilterIndex;    /*!< Specifies the index of matching filter element.
+                                This parameter can be a number between:
+                                - 0 and 127, if FilterList is 0 (Standard)
+                                - 0 and 63, if FilterList is 1 (Extended)                  */
+
+  uint32_t MessageStorage; /*!< Specifies the HP Message Storage.
+                                This parameter can be a value of @ref FDCAN_hp_msg_storage */
+
+  uint32_t MessageIndex;   /*!< Specifies the Index of Rx FIFO element to which the
+                                message was stored.
+                                This parameter is valid only when MessageStorage is:
+                                  FDCAN_HP_STORAGE_RXFIFO0
+                                 or
+                                  FDCAN_HP_STORAGE_RXFIFO1                                 */
+
+} FDCAN_HpMsgStatusTypeDef;
+
+/**
+  * @brief FDCAN Protocol Status structure definition
+  */
+typedef struct
+{
+  uint32_t LastErrorCode;     /*!< Specifies the type of the last error that occurred on the FDCAN bus.
+                                   This parameter can be a value of @ref FDCAN_protocol_error_code                           */
+
+  uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase of a CAN FD format
+                                   frame with its BRS flag set.
+                                   This parameter can be a value of @ref FDCAN_protocol_error_code                           */
+
+  uint32_t Activity;          /*!< Specifies the FDCAN module communication state.
+                                   This parameter can be a value of @ref FDCAN_communication_state                           */
+
+  uint32_t ErrorPassive;      /*!< Specifies the FDCAN module error status.
+                                   This parameter can be:
+                                    - 0 : The FDCAN is in Error_Active state
+                                    - 1 : The FDCAN is in Error_Passive state                                                */
+
+  uint32_t Warning;           /*!< Specifies the FDCAN module warning status.
+                                   This parameter can be:
+                                    - 0 : error counters (RxErrorCnt and TxErrorCnt) are below the Error_Warning limit of 96
+                                    - 1 : at least one of error counters has reached the Error_Warning limit of 96           */
+
+  uint32_t BusOff;            /*!< Specifies the FDCAN module Bus_Off status.
+                                   This parameter can be:
+                                    - 0 : The FDCAN is not in Bus_Off state
+                                    - 1 : The FDCAN is in Bus_Off state                                                      */
+
+  uint32_t RxESIflag;         /*!< Specifies ESI flag of last received CAN FD message.
+                                   This parameter can be:
+                                    - 0 : Last received CAN FD message did not have its ESI flag set
+                                    - 1 : Last received CAN FD message had its ESI flag set                                  */
+
+  uint32_t RxBRSflag;         /*!< Specifies BRS flag of last received CAN FD message.
+                                   This parameter can be:
+                                    - 0 : Last received CAN FD message did not have its BRS flag set
+                                    - 1 : Last received CAN FD message had its BRS flag set                                  */
+
+  uint32_t RxFDFflag;         /*!< Specifies if CAN FD message (FDF flag set) has been received since last protocol status.
+                                   This parameter can be:
+                                    - 0 : no CAN FD message received
+                                    - 1 : CAN FD message received                                                            */
+
+  uint32_t ProtocolException; /*!< Specifies the FDCAN module Protocol Exception status.
+                                   This parameter can be:
+                                    - 0 : No protocol exception event occurred since last read access
+                                    - 1 : Protocol exception event occurred                                                  */
+
+  uint32_t TDCvalue;          /*!< Specifies the Transmitter Delay Compensation Value.
+                                   This parameter can be a number between 0 and 127                                          */
+
+} FDCAN_ProtocolStatusTypeDef;
+
+/**
+  * @brief FDCAN Error Counters structure definition
+  */
+typedef struct
+{
+  uint32_t TxErrorCnt;     /*!< Specifies the Transmit Error Counter Value.
+                                This parameter can be a number between 0 and 255                                         */
+
+  uint32_t RxErrorCnt;     /*!< Specifies the Receive Error Counter Value.
+                                This parameter can be a number between 0 and 127                                         */
+
+  uint32_t RxErrorPassive; /*!< Specifies the Receive Error Passive status.
+                                This parameter can be:
+                                 - 0 : The Receive Error Counter (RxErrorCnt) is below the error passive level of 128
+                                 - 1 : The Receive Error Counter (RxErrorCnt) has reached the error passive level of 128 */
+
+  uint32_t ErrorLogging;   /*!< Specifies the Transmit/Receive error logging counter value.
+                                This parameter can be a number between 0 and 255.
+                                This counter is incremented each time when a FDCAN protocol error causes the TxErrorCnt
+                                or the RxErrorCnt to be incremented. The counter stops at 255; the next increment of
+                                TxErrorCnt or RxErrorCnt sets interrupt flag FDCAN_FLAG_ERROR_LOGGING_OVERFLOW           */
+
+} FDCAN_ErrorCountersTypeDef;
+
+/**
+  * @brief FDCAN TT Init structure definition
+  */
+typedef struct
+{
+  uint32_t OperationMode;     /*!< Specifies the FDCAN Operation Mode.
+                                   This parameter can be a value of @ref FDCAN_operation_mode               */
+
+  uint32_t GapEnable;         /*!< Specifies the FDCAN TT Operation.
+                                   This parameter can be a value of @ref FDCAN_TT_operation.
+                                   This parameter is ignored if OperationMode is set to
+                                   FDCAN_TT_COMMUNICATION_LEVEL0                                            */
+
+  uint32_t TimeMaster;        /*!< Specifies whether the instance is a slave or a potential master.
+                                   This parameter can be a value of @ref FDCAN_TT_time_master               */
+
+  uint32_t SyncDevLimit;      /*!< Specifies the Synchronization Deviation Limit SDL of the TUR
+                                   numerator : TUR = (Numerator � SDL) / Denominator.
+                                   With : SDL = 2^(SyncDevLimit+5).
+                                   This parameter must be a number between 0 and 7                          */
+
+  uint32_t InitRefTrigOffset; /*!< Specifies the Initial Reference Trigger Offset.
+                                   This parameter must be a number between 0 and 127                        */
+
+  uint32_t ExternalClkSync;   /*!< Enable or disable External Clock Synchronization.
+                                   This parameter can be a value of @ref FDCAN_TT_external_clk_sync.
+                                   This parameter is ignored if OperationMode is set to
+                                   FDCAN_TT_COMMUNICATION_LEVEL1                                            */
+
+  uint32_t AppWdgLimit;       /*!< Specifies the Application Watchdog Limit : maximum time after
+                                   which the application has to serve the application watchdog.
+                                   The application watchdog is incremented once each 256 NTUs.
+                                   The application watchdog can be disabled by setting AppWdgLimit to 0.
+                                   This parameter must be a number between 0 and 255.
+                                   This parameter is ignored if OperationMode is set to
+                                   FDCAN_TT_COMMUNICATION_LEVEL0                                            */
+
+  uint32_t GlobalTimeFilter;  /*!< Enable or disable Global Time Filtering.
+                                   This parameter can be a value of @ref FDCAN_TT_global_time_filtering.
+                                   This parameter is ignored if OperationMode is set to
+                                   FDCAN_TT_COMMUNICATION_LEVEL1                                            */
+
+  uint32_t ClockCalibration;  /*!< Enable or disable Automatic Clock Calibration.
+                                   This parameter can be a value of @ref FDCAN_TT_auto_clk_calibration.
+                                   This parameter is ignored if OperationMode is set to
+                                   FDCAN_TT_COMMUNICATION_LEVEL1                                            */
+
+  uint32_t EvtTrigPolarity;   /*!< Specifies the Event Trigger Polarity.
+                                   This parameter can be a value of @ref FDCAN_TT_event_trig_polarity.
+                                   This parameter is ignored if OperationMode is set to
+                                   FDCAN_TT_COMMUNICATION_LEVEL0                                            */
+
+  uint32_t BasicCyclesNbr;    /*!< Specifies the nubmer of basic cycles in the system matrix.
+                                   This parameter can be a value of @ref FDCAN_TT_basic_cycle_number        */
+
+  uint32_t CycleStartSync;    /*!< Enable or disable synchronization pulse output at pin fdcan1_soc.
+                                   This parameter can be a value of @ref FDCAN_TT_cycle_start_sync          */
+
+  uint32_t TxEnableWindow;    /*!< Specifies the length of Tx enable window in NTUs.
+                                   This parameter must be a number between 1 and 16                         */
+
+  uint32_t ExpTxTrigNbr;      /*!< Specifies the number of expected Tx_Triggers in the system matrix.
+                                   This is the sum of Tx_Triggers for exclusive, single arbitrating and
+                                   merged arbitrating windows.
+                                   This parameter must be a number between 0 and 4095                       */
+
+  uint32_t TURNumerator;      /*!< Specifies the TUR (Time Unit Ratio) numerator.
+                                   It is adviced to set this parameter to the largest applicable value.
+                                   This parameter must be a number between 0x10000 and 0x1FFFF              */
+
+  uint32_t TURDenominator;    /*!< Specifies the TUR (Time Unit Ratio) denominator.
+                                   This parameter must be a number between 0x0001 and 0x3FFF                */
+
+  uint32_t TriggerMemoryNbr;  /*!< Specifies the number of trigger memory elements.
+                                   This parameter must be a number between 0 and 64                         */
+
+  uint32_t StopWatchTrigSel;  /*!< Specifies the input to be used as stop watch trigger.
+                                   This parameter can be a value of @ref FDCAN_TT_stop_watch_trig_selection */
+
+  uint32_t EventTrigSel;      /*!< Specifies the input to be used as event trigger.
+                                   This parameter can be a value of @ref FDCAN_TT_event_trig_selection      */
+
+} FDCAN_TT_ConfigTypeDef;
+
+/**
+  * @brief  FDCAN Trigger structure definition
+  */
+typedef struct
+{
+  uint32_t TriggerIndex;  /*!< Specifies the trigger which will be configured.
+                               This parameter must be a number between 0 and 63                                 */
+
+  uint32_t TimeMark;      /*!< Specifies the cycle time for which the trigger becomes active.
+                               This parameter must be a number between 0 and 0xFFFF                             */
+
+  uint32_t RepeatFactor;  /*!< Specifies the trigger repeat factor.
+                               This parameter can be a value of @ref FDCAN_TT_Repeat_Factor                     */
+
+  uint32_t StartCycle;    /*!< Specifies the index of the first cycle in which the trigger becomes active.
+                               This parameter is ignored if RepeatFactor is set to FDCAN_TT_REPEAT_EVERY_CYCLE.
+                               This parameter must be a number between 0 and RepeatFactor                       */
+
+  uint32_t TmEventInt;    /*!< Enable or disable the internal time mark event.
+                               If enabled, FDCAN_TT_FLAG_TRIG_TIME_MARK flag is set when trigger memory element
+                               becomes active.
+                               This parameter can be a value of @ref FDCAN_TT_Time_Mark_Event_Internal          */
+
+  uint32_t TmEventExt;    /*!< Enable or disable the external time mark event.
+                               If enabled, and if TTOCN.TTIE is set, a pulse is generated at fdcan1_tmp when
+                               trigger memory element becomes active.
+                               This parameter can be a value of @ref FDCAN_TT_Time_Mark_Event_External          */
+
+  uint32_t TriggerType;   /*!< Specifies the trigger type.
+                               This parameter can be a value of @ref FDCAN_TT_Trigger_Type                      */
+
+  uint32_t FilterType;    /*!< Specifies the filter identifier type.
+                               This parameter can be a value of @ref FDCAN_id_type                              */
+
+  uint32_t TxBufferIndex; /*!< Specifies the index of the Tx buffer for which the trigger is valid.
+                               This parameter can be a value of @ref FDCAN_Tx_location.
+                               This parameter is taken in consideration only if the trigger is configured for
+                               transmission.                                                                    */
+
+  uint32_t FilterIndex;   /*!< Specifies the filter for which the trigger is valid.
+                               This parameter is taken in consideration only if the trigger is configured for
+                               reception.
+                               This parameter must be a number between:
+                                - 0 and 127, if FilterType is FDCAN_STANDARD_ID
+                                - 0 and 63, if FilterType is FDCAN_EXTENDED_ID                                  */
+
+} FDCAN_TriggerTypeDef;
+
+/**
+  * @brief  FDCAN TT Operation Status structure definition
+  */
+typedef struct
+{
+  uint32_t ErrorLevel;       /*!< Specifies the type of the TT operation error level.
+                                  This parameter can be a value of @ref FDCAN_TT_error_level                    */
+
+  uint32_t MasterState;      /*!< Specifies the type of the TT master state.
+                                  This parameter can be a value of @ref FDCAN_TT_master_state                   */
+
+  uint32_t SyncState;        /*!< Specifies the type of the TT synchronization state.
+                                  This parameter can be a value of @ref FDCAN_TT_sync_state                     */
+
+  uint32_t GTimeQuality;     /*!< Specifies the Quality of Global Time Phase.
+                                  This parameter is only relevant in Level 0 and Level 2, otherwise fixed to 0.
+                                  This parameter can be:
+                                   - 0 : Global time not valid
+                                   - 1 : Global time in phase with Time Master                                  */
+
+  uint32_t ClockQuality;     /*!< Specifies the Quality of Clock Speed.
+                                  This parameter is only relevant in Level 0 and Level 2, otherwise fixed to 1.
+                                  This parameter can be:
+                                   - 0 : Local clock speed not synchronized to Time Master clock speed
+                                   - 1 : Synchronization Deviation = SDL                                        */
+
+  uint32_t RefTrigOffset;    /*!< Specifies the Actual Reference Trigger Offset Value.
+                                  This parameter can be a number between 0 and 0xFF                             */
+
+  uint32_t GTimeDiscPending; /*!< Specifies the Global Time Discontinuity State.
+                                  This parameter can be:
+                                   - 0 : No global time preset pending
+                                   - 1 : Node waits for the global time preset to take effect                   */
+
+  uint32_t GapFinished;      /*!< Specifies whether a Gap is finished.
+                                  This parameter can be:
+                                   - 0 : Reset at the end of each reference message
+                                   - 1 : Gap finished                                                           */
+
+  uint32_t MasterPriority;   /*!< Specifies the Priority of actual Time Master.
+                                  This parameter can be a number between 0 and 0x7                              */
+
+  uint32_t GapStarted;       /*!< Specifies whether a Gap is started.
+                                  This parameter can be:
+                                   - 0 : No Gap in schedule
+                                   - 1 : Gap time after Basic Cycle has started                                 */
+
+  uint32_t WaitForEvt;       /*!< Specifies whether a Gap is annouced.
+                                  This parameter can be:
+                                   - 0 : No Gap announced, reset by a reference message with Next_is_Gap = 0
+                                   - 1 : Reference message with Next_is_Gap = 1 received                        */
+
+  uint32_t AppWdgEvt;        /*!< Specifies the Application Watchdog State.
+                                  This parameter can be:
+                                   - 0 : Application Watchdog served in time
+                                   - 1 : Failed to serve Application Watchdog in time                           */
+
+  uint32_t ECSPending;       /*!< Specifies the External Clock Synchronization State.
+                                  This parameter can be:
+                                   - 0 : No external clock synchronization pending
+                                   - 1 : Node waits for external clock synchronization to take effect           */
+
+  uint32_t PhaseLock;        /*!< Specifies the Phase Lock State.
+                                  This parameter can be:
+                                   - 0 : Phase outside range
+                                   - 1 : Phase inside range                                                     */
+
+} FDCAN_TTOperationStatusTypeDef;
+
+/**
+  * @brief  FDCAN Message RAM blocks
+  */
+typedef struct
+{
+  uint32_t StandardFilterSA; /*!< Specifies the Standard Filter List Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t ExtendedFilterSA; /*!< Specifies the Extended Filter List Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t RxFIFO0SA;        /*!< Specifies the Rx FIFO 0 Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t RxFIFO1SA;        /*!< Specifies the Rx FIFO 1 Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t RxBufferSA;       /*!< Specifies the Rx Buffer Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t TxEventFIFOSA;    /*!< Specifies the Tx Event FIFO Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t TxBufferSA;       /*!< Specifies the Tx Buffers Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t TxFIFOQSA;        /*!< Specifies the Tx FIFO/Queue Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t TTMemorySA;       /*!< Specifies the Trigger Memory Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t EndAddress;       /*!< Specifies the End Address of the allocated RAM.
+                                  This parameter must be a 32-bit word address      */
+
+} FDCAN_MsgRamAddressTypeDef;
+
+/**
+  * @brief  FDCAN handle structure definition
+  */
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+typedef struct __FDCAN_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+{
+  FDCAN_GlobalTypeDef         *Instance;        /*!< Register base address     */
+
+  TTCAN_TypeDef               *ttcan;           /*!< TT register base address  */
+
+  FDCAN_InitTypeDef           Init;             /*!< FDCAN required parameters */
+
+  FDCAN_MsgRamAddressTypeDef  msgRam;           /*!< FDCAN Message RAM blocks  */
+
+  uint32_t                    LatestTxFifoQRequest; /*!< FDCAN Tx buffer index
+                                               of latest Tx FIFO/Queue request */
+
+  __IO HAL_FDCAN_StateTypeDef State;            /*!< FDCAN communication state */
+
+  HAL_LockTypeDef             Lock;             /*!< FDCAN locking object      */
+
+  __IO uint32_t               ErrorCode;        /*!< FDCAN Error code          */
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+  void (* ClockCalibrationCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs);         /*!< FDCAN Clock Calibration callback          */
+  void (* TxEventFifoCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs);                 /*!< FDCAN Tx Event Fifo callback              */
+  void (* RxFifo0Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs);                         /*!< FDCAN Rx Fifo 0 callback                  */
+  void (* RxFifo1Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs);                         /*!< FDCAN Rx Fifo 1 callback                  */
+  void (* TxFifoEmptyCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                          /*!< FDCAN Tx Fifo Empty callback              */
+  void (* TxBufferCompleteCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);             /*!< FDCAN Tx Buffer complete callback         */
+  void (* TxBufferAbortCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);                /*!< FDCAN Tx Buffer abort callback            */
+  void (* RxBufferNewMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                   /*!< FDCAN Rx Buffer New Message callback      */
+  void (* HighPriorityMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                  /*!< FDCAN High priority message callback      */
+  void (* TimestampWraparoundCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                  /*!< FDCAN Timestamp wraparound callback       */
+  void (* TimeoutOccurredCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                      /*!< FDCAN Timeout occurred callback           */
+  void (* ErrorCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                                /*!< FDCAN Error callback                      */
+  void (* ErrorStatusCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs);                 /*!< FDCAN Error status callback               */
+  void (* TT_ScheduleSyncCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs);             /*!< FDCAN T Schedule Synchronization callback */
+  void (* TT_TimeMarkCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs);                  /*!< FDCAN TT Time Mark callback               */
+  void (* TT_StopWatchCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount); /*!< FDCAN TT Stop Watch callback              */
+  void (* TT_GlobalTimeCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs);                /*!< FDCAN TT Global Time callback             */
+
+  void (* MspInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                              /*!< FDCAN Msp Init callback                   */
+  void (* MspDeInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                            /*!< FDCAN Msp DeInit callback                 */
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+} FDCAN_HandleTypeDef;
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+/**
+  * @brief  HAL FDCAN common Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_FDCAN_TX_FIFO_EMPTY_CB_ID        = 0x00U, /*!< FDCAN Tx Fifo Empty callback ID         */
+  HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID    = 0x01U, /*!< FDCAN Rx buffer new message callback ID */
+  HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID    = 0x02U, /*!< FDCAN High priority message callback ID */
+  HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID = 0x03U, /*!< FDCAN Timestamp wraparound callback ID  */
+  HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID     = 0x04U, /*!< FDCAN Timeout occurred callback ID      */
+  HAL_FDCAN_ERROR_CALLBACK_CB_ID       = 0x05U, /*!< FDCAN Error callback ID                 */
+
+  HAL_FDCAN_MSPINIT_CB_ID              = 0x06U, /*!< FDCAN MspInit callback ID               */
+  HAL_FDCAN_MSPDEINIT_CB_ID            = 0x07U, /*!< FDCAN MspDeInit callback ID             */
+
+} HAL_FDCAN_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL FDCAN Callback pointer definition
+  */
+typedef  void (*pFDCAN_CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan);                                                     /*!< pointer to a common FDCAN callback function                    */
+typedef  void (*pFDCAN_ClockCalibrationCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs);         /*!< pointer to Clock Calibration FDCAN callback function           */
+typedef  void (*pFDCAN_TxEventFifoCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs);                 /*!< pointer to Tx event Fifo FDCAN callback function               */
+typedef  void (*pFDCAN_RxFifo0CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs);                         /*!< pointer to Rx Fifo 0 FDCAN callback function                   */
+typedef  void (*pFDCAN_RxFifo1CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs);                         /*!< pointer to Rx Fifo 1 FDCAN callback function                   */
+typedef  void (*pFDCAN_TxBufferCompleteCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);             /*!< pointer to Tx Buffer complete FDCAN callback function          */
+typedef  void (*pFDCAN_TxBufferAbortCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);                /*!< pointer to Tx Buffer abort FDCAN callback function             */
+typedef  void (*pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs);                 /*!< pointer to Error Status callback function                      */
+typedef  void (*pFDCAN_TT_ScheduleSyncCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs);             /*!< pointer to TT Schedule Synchronization FDCAN callback function */
+typedef  void (*pFDCAN_TT_TimeMarkCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs);                  /*!< pointer to TT Time Mark FDCAN callback function                */
+typedef  void (*pFDCAN_TT_StopWatchCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount); /*!< pointer to TT Stop Watch FDCAN callback function               */
+typedef  void (*pFDCAN_TT_GlobalTimeCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs);                /*!< pointer to TT Global Time FDCAN callback function              */
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FDCAN_Exported_Constants FDCAN Exported Constants
+  * @{
+  */
+
+/** @defgroup HAL_FDCAN_Error_Code HAL FDCAN Error Code
+  * @{
+  */
+#define HAL_FDCAN_ERROR_NONE            ((uint32_t)0x00000000U) /*!< No error                                                               */
+#define HAL_FDCAN_ERROR_TIMEOUT         ((uint32_t)0x00000001U) /*!< Timeout error                                                          */
+#define HAL_FDCAN_ERROR_NOT_INITIALIZED ((uint32_t)0x00000002U) /*!< Peripheral not initialized                                             */
+#define HAL_FDCAN_ERROR_NOT_READY       ((uint32_t)0x00000004U) /*!< Peripheral not ready                                                   */
+#define HAL_FDCAN_ERROR_NOT_STARTED     ((uint32_t)0x00000008U) /*!< Peripheral not started                                                 */
+#define HAL_FDCAN_ERROR_NOT_SUPPORTED   ((uint32_t)0x00000010U) /*!< Mode not supported                                                     */
+#define HAL_FDCAN_ERROR_PARAM           ((uint32_t)0x00000020U) /*!< Parameter error                                                        */
+#define HAL_FDCAN_ERROR_PENDING         ((uint32_t)0x00000040U) /*!< Pending operation                                                      */
+#define HAL_FDCAN_ERROR_RAM_ACCESS      ((uint32_t)0x00000080U) /*!< Message RAM Access Failure                                             */
+#define HAL_FDCAN_ERROR_FIFO_EMPTY      ((uint32_t)0x00000100U) /*!< Put element in full FIFO                                               */
+#define HAL_FDCAN_ERROR_FIFO_FULL       ((uint32_t)0x00000200U) /*!< Get element from empty FIFO                                            */
+#define HAL_FDCAN_ERROR_LOG_OVERFLOW    FDCAN_IR_ELO            /*!< Overflow of CAN Error Logging Counter                                  */
+#define HAL_FDCAN_ERROR_RAM_WDG         FDCAN_IR_WDI            /*!< Message RAM Watchdog event occurred                                    */
+#define HAL_FDCAN_ERROR_PROTOCOL_ARBT   FDCAN_IR_PEA            /*!< Protocol Error in Arbitration Phase (Nominal Bit Time is used)         */
+#define HAL_FDCAN_ERROR_PROTOCOL_DATA   FDCAN_IR_PED            /*!< Protocol Error in Data Phase (Data Bit Time is used)                   */
+#define HAL_FDCAN_ERROR_RESERVED_AREA   FDCAN_IR_ARA            /*!< Access to Reserved Address                                             */
+#define HAL_FDCAN_ERROR_TT_GLOBAL_TIME  FDCAN_TTIR_GTE          /*!< Global Time Error : Synchronization deviation exceeded limit           */
+#define HAL_FDCAN_ERROR_TT_TX_UNDERFLOW FDCAN_TTIR_TXU          /*!< Tx Count Underflow : Less Tx trigger than expected in one matrix cycle */
+#define HAL_FDCAN_ERROR_TT_TX_OVERFLOW  FDCAN_TTIR_TXO          /*!< Tx Count Overflow : More Tx trigger than expected in one matrix cycle  */
+#define HAL_FDCAN_ERROR_TT_SCHEDULE1    FDCAN_TTIR_SE1          /*!< Scheduling error 1                                                     */
+#define HAL_FDCAN_ERROR_TT_SCHEDULE2    FDCAN_TTIR_SE2          /*!< Scheduling error 2                                                     */
+#define HAL_FDCAN_ERROR_TT_NO_INIT_REF  FDCAN_TTIR_IWT          /*!< No system startup due to missing reference message                     */
+#define HAL_FDCAN_ERROR_TT_NO_REF       FDCAN_TTIR_WT           /*!< Missing reference message                                              */
+#define HAL_FDCAN_ERROR_TT_APPL_WDG     FDCAN_TTIR_AW           /*!< Application watchdog not served in time                                */
+#define HAL_FDCAN_ERROR_TT_CONFIG       FDCAN_TTIR_CER          /*!< Error found in trigger list                                            */
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+#define HAL_FDCAN_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100U) /*!< Invalid Callback error                                                */
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_frame_format FDCAN Frame Format
+  * @{
+  */
+#define FDCAN_FRAME_CLASSIC   ((uint32_t)0x00000000U)                         /*!< Classic mode                      */
+#define FDCAN_FRAME_FD_NO_BRS ((uint32_t)FDCAN_CCCR_FDOE)                     /*!< FD mode without BitRate Switching */
+#define FDCAN_FRAME_FD_BRS    ((uint32_t)(FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE)) /*!< FD mode with BitRate Switching    */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_operating_mode FDCAN Operating Mode
+  * @{
+  */
+#define FDCAN_MODE_NORMAL               ((uint32_t)0x00000000U) /*!< Normal mode               */
+#define FDCAN_MODE_RESTRICTED_OPERATION ((uint32_t)0x00000001U) /*!< Restricted Operation mode */
+#define FDCAN_MODE_BUS_MONITORING       ((uint32_t)0x00000002U) /*!< Bus Monitoring mode       */
+#define FDCAN_MODE_INTERNAL_LOOPBACK    ((uint32_t)0x00000003U) /*!< Internal LoopBack mode    */
+#define FDCAN_MODE_EXTERNAL_LOOPBACK    ((uint32_t)0x00000004U) /*!< External LoopBack mode    */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_clock_calibration FDCAN Clock Calibration
+  * @{
+  */
+#define FDCAN_CLOCK_CALIBRATION_DISABLE ((uint32_t)0x00000000U) /*!< Disable Clock Calibration */
+#define FDCAN_CLOCK_CALIBRATION_ENABLE  ((uint32_t)0x00000001U) /*!< Enable Clock Calibration  */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_clock_divider FDCAN Clock Divider
+  * @{
+  */
+#define FDCAN_CLOCK_DIV1  ((uint32_t)0x00000000U) /*!< Divide kernel clock by 1  */
+#define FDCAN_CLOCK_DIV2  ((uint32_t)0x00010000U) /*!< Divide kernel clock by 2  */
+#define FDCAN_CLOCK_DIV4  ((uint32_t)0x00020000U) /*!< Divide kernel clock by 4  */
+#define FDCAN_CLOCK_DIV6  ((uint32_t)0x00030000U) /*!< Divide kernel clock by 6  */
+#define FDCAN_CLOCK_DIV8  ((uint32_t)0x00040000U) /*!< Divide kernel clock by 8  */
+#define FDCAN_CLOCK_DIV10 ((uint32_t)0x00050000U) /*!< Divide kernel clock by 10 */
+#define FDCAN_CLOCK_DIV12 ((uint32_t)0x00060000U) /*!< Divide kernel clock by 12 */
+#define FDCAN_CLOCK_DIV14 ((uint32_t)0x00070000U) /*!< Divide kernel clock by 14 */
+#define FDCAN_CLOCK_DIV16 ((uint32_t)0x00080000U) /*!< Divide kernel clock by 16 */
+#define FDCAN_CLOCK_DIV18 ((uint32_t)0x00090000U) /*!< Divide kernel clock by 18 */
+#define FDCAN_CLOCK_DIV20 ((uint32_t)0x000A0000U) /*!< Divide kernel clock by 20 */
+#define FDCAN_CLOCK_DIV22 ((uint32_t)0x000B0000U) /*!< Divide kernel clock by 22 */
+#define FDCAN_CLOCK_DIV24 ((uint32_t)0x000C0000U) /*!< Divide kernel clock by 24 */
+#define FDCAN_CLOCK_DIV26 ((uint32_t)0x000D0000U) /*!< Divide kernel clock by 26 */
+#define FDCAN_CLOCK_DIV28 ((uint32_t)0x000E0000U) /*!< Divide kernel clock by 28 */
+#define FDCAN_CLOCK_DIV30 ((uint32_t)0x000F0000U) /*!< Divide kernel clock by 30 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_calibration_field_length FDCAN Calibration Field Length
+  * @{
+  */
+#define FDCAN_CALIB_FIELD_LENGTH_32 ((uint32_t)0x00000000U)       /*!< Calibration field length is 32 bits */
+#define FDCAN_CALIB_FIELD_LENGTH_64 ((uint32_t)FDCANCCU_CCFG_CFL) /*!< Calibration field length is 64 bits */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_calibration_state FDCAN Calibration State
+  * @{
+  */
+#define FDCAN_CLOCK_NOT_CALIBRATED       ((uint32_t)0x00000000U) /*!< Clock not calibrated       */
+#define FDCAN_CLOCK_BASIC_CALIBRATED     ((uint32_t)0x40000000U) /*!< Clock basic calibrated     */
+#define FDCAN_CLOCK_PRECISION_CALIBRATED ((uint32_t)0x80000000U) /*!< Clock precision calibrated */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_calibration_counter FDCAN Calibration Counter
+  * @{
+  */
+#define FDCAN_CALIB_TIME_QUANTA_COUNTER  ((uint32_t)0x00000000U) /*!< Time Quanta Counter             */
+#define FDCAN_CALIB_CLOCK_PERIOD_COUNTER ((uint32_t)0x00000001U) /*!< Oscillator Clock Period Counter */
+#define FDCAN_CALIB_WATCHDOG_COUNTER     ((uint32_t)0x00000002U) /*!< Calibration Watchdog Counter    */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_data_field_size FDCAN Data Field Size
+  * @{
+  */
+#define FDCAN_DATA_BYTES_8  ((uint32_t)0x00000004U) /*!< 8 bytes data field  */
+#define FDCAN_DATA_BYTES_12 ((uint32_t)0x00000005U) /*!< 12 bytes data field */
+#define FDCAN_DATA_BYTES_16 ((uint32_t)0x00000006U) /*!< 16 bytes data field */
+#define FDCAN_DATA_BYTES_20 ((uint32_t)0x00000007U) /*!< 20 bytes data field */
+#define FDCAN_DATA_BYTES_24 ((uint32_t)0x00000008U) /*!< 24 bytes data field */
+#define FDCAN_DATA_BYTES_32 ((uint32_t)0x0000000AU) /*!< 32 bytes data field */
+#define FDCAN_DATA_BYTES_48 ((uint32_t)0x0000000EU) /*!< 48 bytes data field */
+#define FDCAN_DATA_BYTES_64 ((uint32_t)0x00000012U) /*!< 64 bytes data field */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_txFifoQueue_Mode FDCAN Tx FIFO/Queue Mode
+  * @{
+  */
+#define FDCAN_TX_FIFO_OPERATION  ((uint32_t)0x00000000U)     /*!< FIFO mode  */
+#define FDCAN_TX_QUEUE_OPERATION ((uint32_t)FDCAN_TXBC_TFQM) /*!< Queue mode */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_id_type FDCAN ID Type
+  * @{
+  */
+#define FDCAN_STANDARD_ID ((uint32_t)0x00000000U) /*!< Standard ID element */
+#define FDCAN_EXTENDED_ID ((uint32_t)0x40000000U) /*!< Extended ID element */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_frame_type FDCAN Frame Type
+  * @{
+  */
+#define FDCAN_DATA_FRAME   ((uint32_t)0x00000000U)  /*!< Data frame   */
+#define FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U)  /*!< Remote frame */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_data_length_code FDCAN Data Length Code
+  * @{
+  */
+#define FDCAN_DLC_BYTES_0  ((uint32_t)0x00000000U) /*!< 0 bytes data field  */
+#define FDCAN_DLC_BYTES_1  ((uint32_t)0x00010000U) /*!< 1 bytes data field  */
+#define FDCAN_DLC_BYTES_2  ((uint32_t)0x00020000U) /*!< 2 bytes data field  */
+#define FDCAN_DLC_BYTES_3  ((uint32_t)0x00030000U) /*!< 3 bytes data field  */
+#define FDCAN_DLC_BYTES_4  ((uint32_t)0x00040000U) /*!< 4 bytes data field  */
+#define FDCAN_DLC_BYTES_5  ((uint32_t)0x00050000U) /*!< 5 bytes data field  */
+#define FDCAN_DLC_BYTES_6  ((uint32_t)0x00060000U) /*!< 6 bytes data field  */
+#define FDCAN_DLC_BYTES_7  ((uint32_t)0x00070000U) /*!< 7 bytes data field  */
+#define FDCAN_DLC_BYTES_8  ((uint32_t)0x00080000U) /*!< 8 bytes data field  */
+#define FDCAN_DLC_BYTES_12 ((uint32_t)0x00090000U) /*!< 12 bytes data field */
+#define FDCAN_DLC_BYTES_16 ((uint32_t)0x000A0000U) /*!< 16 bytes data field */
+#define FDCAN_DLC_BYTES_20 ((uint32_t)0x000B0000U) /*!< 20 bytes data field */
+#define FDCAN_DLC_BYTES_24 ((uint32_t)0x000C0000U) /*!< 24 bytes data field */
+#define FDCAN_DLC_BYTES_32 ((uint32_t)0x000D0000U) /*!< 32 bytes data field */
+#define FDCAN_DLC_BYTES_48 ((uint32_t)0x000E0000U) /*!< 48 bytes data field */
+#define FDCAN_DLC_BYTES_64 ((uint32_t)0x000F0000U) /*!< 64 bytes data field */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_error_state_indicator FDCAN Error State Indicator
+  * @{
+  */
+#define FDCAN_ESI_ACTIVE  ((uint32_t)0x00000000U) /*!< Transmitting node is error active  */
+#define FDCAN_ESI_PASSIVE ((uint32_t)0x80000000U) /*!< Transmitting node is error passive */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_bit_rate_switching FDCAN Bit Rate Switching
+  * @{
+  */
+#define FDCAN_BRS_OFF ((uint32_t)0x00000000U) /*!< FDCAN frames transmitted/received without bit rate switching */
+#define FDCAN_BRS_ON  ((uint32_t)0x00100000U) /*!< FDCAN frames transmitted/received with bit rate switching    */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_format FDCAN format
+  * @{
+  */
+#define FDCAN_CLASSIC_CAN ((uint32_t)0x00000000U) /*!< Frame transmitted/received in Classic CAN format */
+#define FDCAN_FD_CAN      ((uint32_t)0x00200000U) /*!< Frame transmitted/received in FDCAN format       */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_EFC FDCAN Event FIFO control
+  * @{
+  */
+#define FDCAN_NO_TX_EVENTS    ((uint32_t)0x00000000U) /*!< Do not store Tx events */
+#define FDCAN_STORE_TX_EVENTS ((uint32_t)0x00800000U) /*!< Store Tx events        */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_filter_type FDCAN Filter Type
+  * @{
+  */
+#define FDCAN_FILTER_RANGE         ((uint32_t)0x00000000U) /*!< Range filter from FilterID1 to FilterID2                        */
+#define FDCAN_FILTER_DUAL          ((uint32_t)0x00000001U) /*!< Dual ID filter for FilterID1 or FilterID2                       */
+#define FDCAN_FILTER_MASK          ((uint32_t)0x00000002U) /*!< Classic filter: FilterID1 = filter, FilterID2 = mask            */
+#define FDCAN_FILTER_RANGE_NO_EIDM ((uint32_t)0x00000003U) /*!< Range filter from FilterID1 to FilterID2, EIDM mask not applied */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_filter_config FDCAN Filter Configuration
+  * @{
+  */
+#define FDCAN_FILTER_DISABLE       ((uint32_t)0x00000000U) /*!< Disable filter element                                    */
+#define FDCAN_FILTER_TO_RXFIFO0    ((uint32_t)0x00000001U) /*!< Store in Rx FIFO 0 if filter matches                      */
+#define FDCAN_FILTER_TO_RXFIFO1    ((uint32_t)0x00000002U) /*!< Store in Rx FIFO 1 if filter matches                      */
+#define FDCAN_FILTER_REJECT        ((uint32_t)0x00000003U) /*!< Reject ID if filter matches                               */
+#define FDCAN_FILTER_HP            ((uint32_t)0x00000004U) /*!< Set high priority if filter matches                       */
+#define FDCAN_FILTER_TO_RXFIFO0_HP ((uint32_t)0x00000005U) /*!< Set high priority and store in FIFO 0 if filter matches   */
+#define FDCAN_FILTER_TO_RXFIFO1_HP ((uint32_t)0x00000006U) /*!< Set high priority and store in FIFO 1 if filter matches   */
+#define FDCAN_FILTER_TO_RXBUFFER   ((uint32_t)0x00000007U) /*!< Store into Rx Buffer, configuration of FilterType ignored */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Tx_location FDCAN Tx Location
+  * @{
+  */
+#define FDCAN_TX_BUFFER0  ((uint32_t)0x00000001U) /*!< Add message to Tx Buffer 0  */
+#define FDCAN_TX_BUFFER1  ((uint32_t)0x00000002U) /*!< Add message to Tx Buffer 1  */
+#define FDCAN_TX_BUFFER2  ((uint32_t)0x00000004U) /*!< Add message to Tx Buffer 2  */
+#define FDCAN_TX_BUFFER3  ((uint32_t)0x00000008U) /*!< Add message to Tx Buffer 3  */
+#define FDCAN_TX_BUFFER4  ((uint32_t)0x00000010U) /*!< Add message to Tx Buffer 4  */
+#define FDCAN_TX_BUFFER5  ((uint32_t)0x00000020U) /*!< Add message to Tx Buffer 5  */
+#define FDCAN_TX_BUFFER6  ((uint32_t)0x00000040U) /*!< Add message to Tx Buffer 6  */
+#define FDCAN_TX_BUFFER7  ((uint32_t)0x00000080U) /*!< Add message to Tx Buffer 7  */
+#define FDCAN_TX_BUFFER8  ((uint32_t)0x00000100U) /*!< Add message to Tx Buffer 8  */
+#define FDCAN_TX_BUFFER9  ((uint32_t)0x00000200U) /*!< Add message to Tx Buffer 9  */
+#define FDCAN_TX_BUFFER10 ((uint32_t)0x00000400U) /*!< Add message to Tx Buffer 10 */
+#define FDCAN_TX_BUFFER11 ((uint32_t)0x00000800U) /*!< Add message to Tx Buffer 11 */
+#define FDCAN_TX_BUFFER12 ((uint32_t)0x00001000U) /*!< Add message to Tx Buffer 12 */
+#define FDCAN_TX_BUFFER13 ((uint32_t)0x00002000U) /*!< Add message to Tx Buffer 13 */
+#define FDCAN_TX_BUFFER14 ((uint32_t)0x00004000U) /*!< Add message to Tx Buffer 14 */
+#define FDCAN_TX_BUFFER15 ((uint32_t)0x00008000U) /*!< Add message to Tx Buffer 15 */
+#define FDCAN_TX_BUFFER16 ((uint32_t)0x00010000U) /*!< Add message to Tx Buffer 16 */
+#define FDCAN_TX_BUFFER17 ((uint32_t)0x00020000U) /*!< Add message to Tx Buffer 17 */
+#define FDCAN_TX_BUFFER18 ((uint32_t)0x00040000U) /*!< Add message to Tx Buffer 18 */
+#define FDCAN_TX_BUFFER19 ((uint32_t)0x00080000U) /*!< Add message to Tx Buffer 19 */
+#define FDCAN_TX_BUFFER20 ((uint32_t)0x00100000U) /*!< Add message to Tx Buffer 20 */
+#define FDCAN_TX_BUFFER21 ((uint32_t)0x00200000U) /*!< Add message to Tx Buffer 21 */
+#define FDCAN_TX_BUFFER22 ((uint32_t)0x00400000U) /*!< Add message to Tx Buffer 22 */
+#define FDCAN_TX_BUFFER23 ((uint32_t)0x00800000U) /*!< Add message to Tx Buffer 23 */
+#define FDCAN_TX_BUFFER24 ((uint32_t)0x01000000U) /*!< Add message to Tx Buffer 24 */
+#define FDCAN_TX_BUFFER25 ((uint32_t)0x02000000U) /*!< Add message to Tx Buffer 25 */
+#define FDCAN_TX_BUFFER26 ((uint32_t)0x04000000U) /*!< Add message to Tx Buffer 26 */
+#define FDCAN_TX_BUFFER27 ((uint32_t)0x08000000U) /*!< Add message to Tx Buffer 27 */
+#define FDCAN_TX_BUFFER28 ((uint32_t)0x10000000U) /*!< Add message to Tx Buffer 28 */
+#define FDCAN_TX_BUFFER29 ((uint32_t)0x20000000U) /*!< Add message to Tx Buffer 29 */
+#define FDCAN_TX_BUFFER30 ((uint32_t)0x40000000U) /*!< Add message to Tx Buffer 30 */
+#define FDCAN_TX_BUFFER31 ((uint32_t)0x80000000U) /*!< Add message to Tx Buffer 31 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Rx_location FDCAN Rx Location
+  * @{
+  */
+#define FDCAN_RX_FIFO0    ((uint32_t)0x00000040U) /*!< Get received message from Rx FIFO 0    */
+#define FDCAN_RX_FIFO1    ((uint32_t)0x00000041U) /*!< Get received message from Rx FIFO 1    */
+#define FDCAN_RX_BUFFER0  ((uint32_t)0x00000000U) /*!< Get received message from Rx Buffer 0  */
+#define FDCAN_RX_BUFFER1  ((uint32_t)0x00000001U) /*!< Get received message from Rx Buffer 1  */
+#define FDCAN_RX_BUFFER2  ((uint32_t)0x00000002U) /*!< Get received message from Rx Buffer 2  */
+#define FDCAN_RX_BUFFER3  ((uint32_t)0x00000003U) /*!< Get received message from Rx Buffer 3  */
+#define FDCAN_RX_BUFFER4  ((uint32_t)0x00000004U) /*!< Get received message from Rx Buffer 4  */
+#define FDCAN_RX_BUFFER5  ((uint32_t)0x00000005U) /*!< Get received message from Rx Buffer 5  */
+#define FDCAN_RX_BUFFER6  ((uint32_t)0x00000006U) /*!< Get received message from Rx Buffer 6  */
+#define FDCAN_RX_BUFFER7  ((uint32_t)0x00000007U) /*!< Get received message from Rx Buffer 7  */
+#define FDCAN_RX_BUFFER8  ((uint32_t)0x00000008U) /*!< Get received message from Rx Buffer 8  */
+#define FDCAN_RX_BUFFER9  ((uint32_t)0x00000009U) /*!< Get received message from Rx Buffer 9  */
+#define FDCAN_RX_BUFFER10 ((uint32_t)0x0000000AU) /*!< Get received message from Rx Buffer 10 */
+#define FDCAN_RX_BUFFER11 ((uint32_t)0x0000000BU) /*!< Get received message from Rx Buffer 11 */
+#define FDCAN_RX_BUFFER12 ((uint32_t)0x0000000CU) /*!< Get received message from Rx Buffer 12 */
+#define FDCAN_RX_BUFFER13 ((uint32_t)0x0000000DU) /*!< Get received message from Rx Buffer 13 */
+#define FDCAN_RX_BUFFER14 ((uint32_t)0x0000000EU) /*!< Get received message from Rx Buffer 14 */
+#define FDCAN_RX_BUFFER15 ((uint32_t)0x0000000FU) /*!< Get received message from Rx Buffer 15 */
+#define FDCAN_RX_BUFFER16 ((uint32_t)0x00000010U) /*!< Get received message from Rx Buffer 16 */
+#define FDCAN_RX_BUFFER17 ((uint32_t)0x00000011U) /*!< Get received message from Rx Buffer 17 */
+#define FDCAN_RX_BUFFER18 ((uint32_t)0x00000012U) /*!< Get received message from Rx Buffer 18 */
+#define FDCAN_RX_BUFFER19 ((uint32_t)0x00000013U) /*!< Get received message from Rx Buffer 19 */
+#define FDCAN_RX_BUFFER20 ((uint32_t)0x00000014U) /*!< Get received message from Rx Buffer 20 */
+#define FDCAN_RX_BUFFER21 ((uint32_t)0x00000015U) /*!< Get received message from Rx Buffer 21 */
+#define FDCAN_RX_BUFFER22 ((uint32_t)0x00000016U) /*!< Get received message from Rx Buffer 22 */
+#define FDCAN_RX_BUFFER23 ((uint32_t)0x00000017U) /*!< Get received message from Rx Buffer 23 */
+#define FDCAN_RX_BUFFER24 ((uint32_t)0x00000018U) /*!< Get received message from Rx Buffer 24 */
+#define FDCAN_RX_BUFFER25 ((uint32_t)0x00000019U) /*!< Get received message from Rx Buffer 25 */
+#define FDCAN_RX_BUFFER26 ((uint32_t)0x0000001AU) /*!< Get received message from Rx Buffer 26 */
+#define FDCAN_RX_BUFFER27 ((uint32_t)0x0000001BU) /*!< Get received message from Rx Buffer 27 */
+#define FDCAN_RX_BUFFER28 ((uint32_t)0x0000001CU) /*!< Get received message from Rx Buffer 28 */
+#define FDCAN_RX_BUFFER29 ((uint32_t)0x0000001DU) /*!< Get received message from Rx Buffer 29 */
+#define FDCAN_RX_BUFFER30 ((uint32_t)0x0000001EU) /*!< Get received message from Rx Buffer 30 */
+#define FDCAN_RX_BUFFER31 ((uint32_t)0x0000001FU) /*!< Get received message from Rx Buffer 31 */
+#define FDCAN_RX_BUFFER32 ((uint32_t)0x00000020U) /*!< Get received message from Rx Buffer 32 */
+#define FDCAN_RX_BUFFER33 ((uint32_t)0x00000021U) /*!< Get received message from Rx Buffer 33 */
+#define FDCAN_RX_BUFFER34 ((uint32_t)0x00000022U) /*!< Get received message from Rx Buffer 34 */
+#define FDCAN_RX_BUFFER35 ((uint32_t)0x00000023U) /*!< Get received message from Rx Buffer 35 */
+#define FDCAN_RX_BUFFER36 ((uint32_t)0x00000024U) /*!< Get received message from Rx Buffer 36 */
+#define FDCAN_RX_BUFFER37 ((uint32_t)0x00000025U) /*!< Get received message from Rx Buffer 37 */
+#define FDCAN_RX_BUFFER38 ((uint32_t)0x00000026U) /*!< Get received message from Rx Buffer 38 */
+#define FDCAN_RX_BUFFER39 ((uint32_t)0x00000027U) /*!< Get received message from Rx Buffer 39 */
+#define FDCAN_RX_BUFFER40 ((uint32_t)0x00000028U) /*!< Get received message from Rx Buffer 40 */
+#define FDCAN_RX_BUFFER41 ((uint32_t)0x00000029U) /*!< Get received message from Rx Buffer 41 */
+#define FDCAN_RX_BUFFER42 ((uint32_t)0x0000002AU) /*!< Get received message from Rx Buffer 42 */
+#define FDCAN_RX_BUFFER43 ((uint32_t)0x0000002BU) /*!< Get received message from Rx Buffer 43 */
+#define FDCAN_RX_BUFFER44 ((uint32_t)0x0000002CU) /*!< Get received message from Rx Buffer 44 */
+#define FDCAN_RX_BUFFER45 ((uint32_t)0x0000002DU) /*!< Get received message from Rx Buffer 45 */
+#define FDCAN_RX_BUFFER46 ((uint32_t)0x0000002EU) /*!< Get received message from Rx Buffer 46 */
+#define FDCAN_RX_BUFFER47 ((uint32_t)0x0000002FU) /*!< Get received message from Rx Buffer 47 */
+#define FDCAN_RX_BUFFER48 ((uint32_t)0x00000030U) /*!< Get received message from Rx Buffer 48 */
+#define FDCAN_RX_BUFFER49 ((uint32_t)0x00000031U) /*!< Get received message from Rx Buffer 49 */
+#define FDCAN_RX_BUFFER50 ((uint32_t)0x00000032U) /*!< Get received message from Rx Buffer 50 */
+#define FDCAN_RX_BUFFER51 ((uint32_t)0x00000033U) /*!< Get received message from Rx Buffer 51 */
+#define FDCAN_RX_BUFFER52 ((uint32_t)0x00000034U) /*!< Get received message from Rx Buffer 52 */
+#define FDCAN_RX_BUFFER53 ((uint32_t)0x00000035U) /*!< Get received message from Rx Buffer 53 */
+#define FDCAN_RX_BUFFER54 ((uint32_t)0x00000036U) /*!< Get received message from Rx Buffer 54 */
+#define FDCAN_RX_BUFFER55 ((uint32_t)0x00000037U) /*!< Get received message from Rx Buffer 55 */
+#define FDCAN_RX_BUFFER56 ((uint32_t)0x00000038U) /*!< Get received message from Rx Buffer 56 */
+#define FDCAN_RX_BUFFER57 ((uint32_t)0x00000039U) /*!< Get received message from Rx Buffer 57 */
+#define FDCAN_RX_BUFFER58 ((uint32_t)0x0000003AU) /*!< Get received message from Rx Buffer 58 */
+#define FDCAN_RX_BUFFER59 ((uint32_t)0x0000003BU) /*!< Get received message from Rx Buffer 59 */
+#define FDCAN_RX_BUFFER60 ((uint32_t)0x0000003CU) /*!< Get received message from Rx Buffer 60 */
+#define FDCAN_RX_BUFFER61 ((uint32_t)0x0000003DU) /*!< Get received message from Rx Buffer 61 */
+#define FDCAN_RX_BUFFER62 ((uint32_t)0x0000003EU) /*!< Get received message from Rx Buffer 62 */
+#define FDCAN_RX_BUFFER63 ((uint32_t)0x0000003FU) /*!< Get received message from Rx Buffer 63 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_event_type FDCAN Event Type
+  * @{
+  */
+#define FDCAN_TX_EVENT             ((uint32_t)0x00400000U) /*!< Tx event                              */
+#define FDCAN_TX_IN_SPITE_OF_ABORT ((uint32_t)0x00800000U) /*!< Transmission in spite of cancellation */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_hp_msg_storage FDCAN High Priority Message Storage
+  * @{
+  */
+#define FDCAN_HP_STORAGE_NO_FIFO  ((uint32_t)0x00000000U) /*!< No FIFO selected         */
+#define FDCAN_HP_STORAGE_MSG_LOST ((uint32_t)0x00000040U) /*!< FIFO message lost        */
+#define FDCAN_HP_STORAGE_RXFIFO0  ((uint32_t)0x00000080U) /*!< Message stored in FIFO 0 */
+#define FDCAN_HP_STORAGE_RXFIFO1  ((uint32_t)0x000000C0U) /*!< Message stored in FIFO 1 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_protocol_error_code FDCAN protocol error code
+  * @{
+  */
+#define FDCAN_PROTOCOL_ERROR_NONE      ((uint32_t)0x00000000U) /*!< No error occurred         */
+#define FDCAN_PROTOCOL_ERROR_STUFF     ((uint32_t)0x00000001U) /*!< Stuff error               */
+#define FDCAN_PROTOCOL_ERROR_FORM      ((uint32_t)0x00000002U) /*!< Form error                */
+#define FDCAN_PROTOCOL_ERROR_ACK       ((uint32_t)0x00000003U) /*!< Acknowledge error         */
+#define FDCAN_PROTOCOL_ERROR_BIT1      ((uint32_t)0x00000004U) /*!< Bit 1 (recessive) error   */
+#define FDCAN_PROTOCOL_ERROR_BIT0      ((uint32_t)0x00000005U) /*!< Bit 0 (dominant) error    */
+#define FDCAN_PROTOCOL_ERROR_CRC       ((uint32_t)0x00000006U) /*!< CRC check sum error       */
+#define FDCAN_PROTOCOL_ERROR_NO_CHANGE ((uint32_t)0x00000007U) /*!< No change since last read */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_communication_state FDCAN communication state
+  * @{
+  */
+#define FDCAN_COM_STATE_SYNC ((uint32_t)0x00000000U) /*!< Node is synchronizing on CAN communication */
+#define FDCAN_COM_STATE_IDLE ((uint32_t)0x00000008U) /*!< Node is neither receiver nor transmitter   */
+#define FDCAN_COM_STATE_RX   ((uint32_t)0x00000010U) /*!< Node is operating as receiver              */
+#define FDCAN_COM_STATE_TX   ((uint32_t)0x00000018U) /*!< Node is operating as transmitter           */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_FIFO_watermark FDCAN FIFO watermark
+  * @{
+  */
+#define FDCAN_CFG_TX_EVENT_FIFO ((uint32_t)0x00000000U) /*!< Tx event FIFO */
+#define FDCAN_CFG_RX_FIFO0      ((uint32_t)0x00000001U) /*!< Rx FIFO0      */
+#define FDCAN_CFG_RX_FIFO1      ((uint32_t)0x00000002U) /*!< Rx FIFO1      */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Rx_FIFO_operation_mode FDCAN FIFO operation mode
+  * @{
+  */
+#define FDCAN_RX_FIFO_BLOCKING  ((uint32_t)0x00000000U) /*!< Rx FIFO blocking mode  */
+#define FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x80000000U) /*!< Rx FIFO overwrite mode */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Non_Matching_Frames FDCAN non-matching frames
+  * @{
+  */
+#define FDCAN_ACCEPT_IN_RX_FIFO0 ((uint32_t)0x00000000U) /*!< Accept in Rx FIFO 0 */
+#define FDCAN_ACCEPT_IN_RX_FIFO1 ((uint32_t)0x00000001U) /*!< Accept in Rx FIFO 1 */
+#define FDCAN_REJECT             ((uint32_t)0x00000002U) /*!< Reject              */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Reject_Remote_Frames FDCAN reject remote frames
+  * @{
+  */
+#define FDCAN_FILTER_REMOTE ((uint32_t)0x00000000U) /*!< Filter remote frames */
+#define FDCAN_REJECT_REMOTE ((uint32_t)0x00000001U) /*!< Reject all remote frames */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Interrupt_Line FDCAN interrupt line
+  * @{
+  */
+#define FDCAN_INTERRUPT_LINE0 ((uint32_t)0x00000001U) /*!< Interrupt Line 0 */
+#define FDCAN_INTERRUPT_LINE1 ((uint32_t)0x00000002U) /*!< Interrupt Line 1 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Timestamp FDCAN timestamp
+  * @{
+  */
+#define FDCAN_TIMESTAMP_INTERNAL ((uint32_t)0x00000001U) /*!< Timestamp counter value incremented according to TCP */
+#define FDCAN_TIMESTAMP_EXTERNAL ((uint32_t)0x00000002U) /*!< External timestamp counter value used                */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Timestamp_Prescaler FDCAN timestamp prescaler
+  * @{
+  */
+#define FDCAN_TIMESTAMP_PRESC_1  ((uint32_t)0x00000000U) /*!< Timestamp counter time unit in equal to CAN bit time                 */
+#define FDCAN_TIMESTAMP_PRESC_2  ((uint32_t)0x00010000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 2  */
+#define FDCAN_TIMESTAMP_PRESC_3  ((uint32_t)0x00020000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 3  */
+#define FDCAN_TIMESTAMP_PRESC_4  ((uint32_t)0x00030000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 4  */
+#define FDCAN_TIMESTAMP_PRESC_5  ((uint32_t)0x00040000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 5  */
+#define FDCAN_TIMESTAMP_PRESC_6  ((uint32_t)0x00050000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 6  */
+#define FDCAN_TIMESTAMP_PRESC_7  ((uint32_t)0x00060000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 7  */
+#define FDCAN_TIMESTAMP_PRESC_8  ((uint32_t)0x00070000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 8  */
+#define FDCAN_TIMESTAMP_PRESC_9  ((uint32_t)0x00080000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 9  */
+#define FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 10 */
+#define FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 11 */
+#define FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 12 */
+#define FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 13 */
+#define FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 14 */
+#define FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 15 */
+#define FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 16 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Timeout_Operation FDCAN timeout operation
+  * @{
+  */
+#define FDCAN_TIMEOUT_CONTINUOUS    ((uint32_t)0x00000000U) /*!< Timeout continuous operation        */
+#define FDCAN_TIMEOUT_TX_EVENT_FIFO ((uint32_t)0x00000002U) /*!< Timeout controlled by Tx Event FIFO */
+#define FDCAN_TIMEOUT_RX_FIFO0      ((uint32_t)0x00000004U) /*!< Timeout controlled by Rx FIFO 0     */
+#define FDCAN_TIMEOUT_RX_FIFO1      ((uint32_t)0x00000006U) /*!< Timeout controlled by Rx FIFO 1     */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_Reference_Message_Payload FDCAN TT reference message payload
+  * @{
+  */
+#define FDCAN_TT_REF_MESSAGE_NO_PAYLOAD  ((uint32_t)0x00000000U)      /*!< Reference message has no additional payload  */
+#define FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD ((uint32_t)FDCAN_TTRMC_RMPS) /*!< Additional payload is taken from Tx Buffer 0 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_Repeat_Factor FDCAN TT repeat factor
+  * @{
+  */
+#define FDCAN_TT_REPEAT_EVERY_CYCLE      ((uint32_t)0x00000000U) /*!< Trigger valid for all cycles   */
+#define FDCAN_TT_REPEAT_EVERY_2ND_CYCLE  ((uint32_t)0x00000002U) /*!< Trigger valid every 2dn cycle  */
+#define FDCAN_TT_REPEAT_EVERY_4TH_CYCLE  ((uint32_t)0x00000004U) /*!< Trigger valid every 4th cycle  */
+#define FDCAN_TT_REPEAT_EVERY_8TH_CYCLE  ((uint32_t)0x00000008U) /*!< Trigger valid every 8th cycle  */
+#define FDCAN_TT_REPEAT_EVERY_16TH_CYCLE ((uint32_t)0x00000010U) /*!< Trigger valid every 16th cycle */
+#define FDCAN_TT_REPEAT_EVERY_32ND_CYCLE ((uint32_t)0x00000020U) /*!< Trigger valid every 32nd cycle */
+#define FDCAN_TT_REPEAT_EVERY_64TH_CYCLE ((uint32_t)0x00000040U) /*!< Trigger valid every 64th cycle */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_Trigger_Type FDCAN TT trigger type
+  * @{
+  */
+#define FDCAN_TT_TX_REF_TRIGGER         ((uint32_t)0x00000000U) /*!< Transmit reference message in strictly time-triggered operation                                                     */
+#define FDCAN_TT_TX_REF_TRIGGER_GAP     ((uint32_t)0x00000001U) /*!< Transmit reference message in external event-synchronized time-triggered operation                                  */
+#define FDCAN_TT_TX_TRIGGER_SINGLE      ((uint32_t)0x00000002U) /*!< Start a single transmission in an exclusive time window                                                             */
+#define FDCAN_TT_TX_TRIGGER_CONTINUOUS  ((uint32_t)0x00000003U) /*!< Start a continuous transmission in an exclusive time window                                                         */
+#define FDCAN_TT_TX_TRIGGER_ARBITRATION ((uint32_t)0x00000004U) /*!< Start a transmission in an arbitration time window                                                                  */
+#define FDCAN_TT_TX_TRIGGER_MERGED      ((uint32_t)0x00000005U) /*!< Start a merged arbitration window                                                                                   */
+#define FDCAN_TT_WATCH_TRIGGER          ((uint32_t)0x00000006U) /*!< Check for missing reference messages in strictly time-triggered operation                                           */
+#define FDCAN_TT_WATCH_TRIGGER_GAP      ((uint32_t)0x00000007U) /*!< Check for missing reference messages in external event-synchronized time-triggered operation                        */
+#define FDCAN_TT_RX_TRIGGER             ((uint32_t)0x00000008U) /*!< Check for the reception of periodic messages in exclusive time windows                                              */
+#define FDCAN_TT_TIME_BASE_TRIGGER      ((uint32_t)0x00000009U) /*!< Generate internal/external events depending on TmEventInt/TmEventExt configuration                                  */
+#define FDCAN_TT_END_OF_LIST            ((uint32_t)0x0000000AU) /*!< Illegal trigger, to be assigned to the unused triggers after a FDCAN_TT_WATCH_TRIGGER or FDCAN_TT_WATCH_TRIGGER_GAP */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_Time_Mark_Event_Internal FDCAN TT time mark event internal
+  * @{
+  */
+#define FDCAN_TT_TM_NO_INTERNAL_EVENT  ((uint32_t)0x00000000U) /*!< No action                                               */
+#define FDCAN_TT_TM_GEN_INTERNAL_EVENT ((uint32_t)0x00000020U) /*!< Internal event is generated when trigger becomes active */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_Time_Mark_Event_External FDCAN TT time mark event external
+  * @{
+  */
+#define FDCAN_TT_TM_NO_EXTERNAL_EVENT  ((uint32_t)0x00000000U) /*!< No action                                                       */
+#define FDCAN_TT_TM_GEN_EXTERNAL_EVENT ((uint32_t)0x00000010U) /*!< External event (pulse) is generated when trigger becomes active */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_operation_mode FDCAN Operation Mode
+  * @{
+  */
+#define FDCAN_TT_COMMUNICATION_LEVEL1    ((uint32_t)0x00000001U) /*!< Time triggered communication, level 1 */
+#define FDCAN_TT_COMMUNICATION_LEVEL2    ((uint32_t)0x00000002U) /*!< Time triggered communication, level 2 */
+#define FDCAN_TT_COMMUNICATION_LEVEL0    ((uint32_t)0x00000003U) /*!< Time triggered communication, level 0 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_operation FDCAN TT Operation
+  * @{
+  */
+#define FDCAN_STRICTLY_TT_OPERATION     ((uint32_t)0x00000000U)     /*!< Strictly time-triggered operation                    */
+#define FDCAN_EXT_EVT_SYNC_TT_OPERATION ((uint32_t)FDCAN_TTOCF_GEN) /*!< External event-synchronized time-triggered operation */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_time_master FDCAN TT Time Master
+  * @{
+  */
+#define FDCAN_TT_SLAVE            ((uint32_t)0x00000000U)    /*!< Time slave            */
+#define FDCAN_TT_POTENTIAL_MASTER ((uint32_t)FDCAN_TTOCF_TM) /*!< Potential time master */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_external_clk_sync FDCAN TT External Clock Synchronization
+  * @{
+  */
+#define FDCAN_TT_EXT_CLK_SYNC_DISABLE ((uint32_t)0x00000000U)      /*!< External clock synchronization in Level 0,2 disabled */
+#define FDCAN_TT_EXT_CLK_SYNC_ENABLE  ((uint32_t)FDCAN_TTOCF_EECS) /*!< External clock synchronization in Level 0,2 enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_global_time_filtering FDCAN TT Global Time Filtering
+  * @{
+  */
+#define FDCAN_TT_GLOB_TIME_FILT_DISABLE ((uint32_t)0x00000000U)      /*!< Global time filtering in Level 0,2 disabled */
+#define FDCAN_TT_GLOB_TIME_FILT_ENABLE  ((uint32_t)FDCAN_TTOCF_EGTF) /*!< Global time filtering in Level 0,2 enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_auto_clk_calibration FDCAN TT Automatic Clock Calibration
+  * @{
+  */
+#define FDCAN_TT_AUTO_CLK_CALIB_DISABLE ((uint32_t)0x00000000U)     /*!< Automatic clock calibration in Level 0,2 disabled */
+#define FDCAN_TT_AUTO_CLK_CALIB_ENABLE  ((uint32_t)FDCAN_TTOCF_ECC) /*!< Automatic clock calibration in Level 0,2 enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_event_trig_polarity FDCAN TT Event Trigger Polarity
+  * @{
+  */
+#define FDCAN_TT_EVT_TRIG_POL_RISING  ((uint32_t)0x00000000U)      /*!< Rising edge trigger  */
+#define FDCAN_TT_EVT_TRIG_POL_FALLING ((uint32_t)FDCAN_TTOCF_EVTP) /*!< Falling edge trigger */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_basic_cycle_number FDCAN TT Basic Cycle Number
+  * @{
+  */
+#define FDCAN_TT_CYCLES_PER_MATRIX_1  ((uint32_t)0x00000000U) /*!< 1 Basic Cycle per Matrix   */
+#define FDCAN_TT_CYCLES_PER_MATRIX_2  ((uint32_t)0x00000001U) /*!< 2 Basic Cycles per Matrix  */
+#define FDCAN_TT_CYCLES_PER_MATRIX_4  ((uint32_t)0x00000003U) /*!< 4 Basic Cycles per Matrix  */
+#define FDCAN_TT_CYCLES_PER_MATRIX_8  ((uint32_t)0x00000007U) /*!< 8 Basic Cycles per Matrix  */
+#define FDCAN_TT_CYCLES_PER_MATRIX_16 ((uint32_t)0x0000000FU) /*!< 16 Basic Cycles per Matrix */
+#define FDCAN_TT_CYCLES_PER_MATRIX_32 ((uint32_t)0x0000001FU) /*!< 32 Basic Cycles per Matrix */
+#define FDCAN_TT_CYCLES_PER_MATRIX_64 ((uint32_t)0x0000003FU) /*!< 64 Basic Cycles per Matrix */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_cycle_start_sync FDCAN TT Cycle Start Sync
+  * @{
+  */
+#define FDCAN_TT_NO_SYNC_PULSE          ((uint32_t)0x00000000U) /*!< No sync pulse                      */
+#define FDCAN_TT_SYNC_BASIC_CYCLE_START ((uint32_t)0x00000040U) /*!< Sync pulse at start of basic cycle */
+#define FDCAN_TT_SYNC_MATRIX_START      ((uint32_t)0x00000080U) /*!< Sync pulse at start of matrix      */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_stop_watch_trig_selection FDCAN TT Stop Watch Trigger Selection
+  * @{
+  */
+#define FDCAN_TT_STOP_WATCH_TRIGGER_0 ((uint32_t)0x00000000U) /*!< TIM2 selected as stop watch trigger  */
+#define FDCAN_TT_STOP_WATCH_TRIGGER_1 ((uint32_t)0x00000001U) /*!< TIM3 selected as stop watch trigger  */
+#define FDCAN_TT_STOP_WATCH_TRIGGER_2 ((uint32_t)0x00000002U) /*!< ETH selected as stop watch trigger   */
+#define FDCAN_TT_STOP_WATCH_TRIGGER_3 ((uint32_t)0x00000003U) /*!< HRTIM selected as stop watch trigger */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_event_trig_selection FDCAN TT Event Trigger Selection
+  * @{
+  */
+#define FDCAN_TT_EVENT_TRIGGER_0 ((uint32_t)0x00000000U) /*!< TIM2 selected as event trigger  */
+#define FDCAN_TT_EVENT_TRIGGER_1 ((uint32_t)0x00000010U) /*!< TIM3 selected as event trigger  */
+#define FDCAN_TT_EVENT_TRIGGER_2 ((uint32_t)0x00000020U) /*!< ETH selected as event trigger   */
+#define FDCAN_TT_EVENT_TRIGGER_3 ((uint32_t)0x00000030U) /*!< HRTIM selected as event trigger */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_stop_watch_source FDCAN TT Stop Watch Source
+  * @{
+  */
+#define FDCAN_TT_STOP_WATCH_DISABLED    ((uint32_t)0x00000000U) /*!< Stop Watch disabled                                                        */
+#define FDCAN_TT_STOP_WATCH_CYCLE_TIME  ((uint32_t)0x00000008U) /*!< Actual value of cycle time is copied to Capture Time register (TTCPT.SWV)  */
+#define FDCAN_TT_STOP_WATCH_LOCAL_TIME  ((uint32_t)0x00000010U) /*!< Actual value of local time is copied to Capture Time register (TTCPT.SWV)  */
+#define FDCAN_TT_STOP_WATCH_GLOBAL_TIME ((uint32_t)0x00000018U) /*!< Actual value of global time is copied to Capture Time register (TTCPT.SWV) */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_stop_watch_polarity FDCAN TT Stop Watch Polarity
+  * @{
+  */
+#define FDCAN_TT_STOP_WATCH_RISING  ((uint32_t)0x00000000U) /*!< Selected stop watch source is captured at rising edge of fdcan1_swt  */
+#define FDCAN_TT_STOP_WATCH_FALLING ((uint32_t)0x00000004U) /*!< Selected stop watch source is captured at falling edge of fdcan1_swt */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_time_mark_source FDCAN TT Time Mark Source
+  * @{
+  */
+#define FDCAN_TT_REG_TIMEMARK_DIABLED  ((uint32_t)0x00000000U) /*!< No Register Time Mark Interrupt generated               */
+#define FDCAN_TT_REG_TIMEMARK_CYC_TIME ((uint32_t)0x00000040U) /*!< Register Time Mark Interrupt if Time Mark = cycle time  */
+#define FDCAN_TT_REG_TIMEMARK_LOC_TIME ((uint32_t)0x00000080U) /*!< Register Time Mark Interrupt if Time Mark = local time  */
+#define FDCAN_TT_REG_TIMEMARK_GLO_TIME ((uint32_t)0x000000C0U) /*!< Register Time Mark Interrupt if Time Mark = global time */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_error_level FDCAN TT Error Level
+  * @{
+  */
+#define FDCAN_TT_NO_ERROR     ((uint32_t)0x00000000U) /*!< Severity 0 - No Error     */
+#define FDCAN_TT_WARNING      ((uint32_t)0x00000001U) /*!< Severity 1 - Warning      */
+#define FDCAN_TT_ERROR        ((uint32_t)0x00000002U) /*!< Severity 2 - Error        */
+#define FDCAN_TT_SEVERE_ERROR ((uint32_t)0x00000003U) /*!< Severity 3 - Severe Error */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_master_state FDCAN TT Master State
+  * @{
+  */
+#define FDCAN_TT_MASTER_OFF          ((uint32_t)0x00000000U) /*!< Master_Off, no master properties relevant */
+#define FDCAN_TT_TIME_SLAVE          ((uint32_t)0x00000004U) /*!< Operating as Time Slave                   */
+#define FDCAN_TT_BACKUP_TIME_MASTER  ((uint32_t)0x00000008U) /*!< Operating as Backup Time Master           */
+#define FDCAN_TT_CURRENT_TIME_MASTER ((uint32_t)0x0000000CU) /*!< Operating as current Time Master          */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_sync_state FDCAN TT Synchronization State
+  * @{
+  */
+#define FDCAN_TT_OUT_OF_SYNC   ((uint32_t)0x00000000U) /*!< Out of Synchronization         */
+#define FDCAN_TT_SYNCHRONIZING ((uint32_t)0x00000010U) /*!< Synchronizing to communication */
+#define FDCAN_TT_IN_GAP        ((uint32_t)0x00000020U) /*!< Schedule suspended by Gap      */
+#define FDCAN_TT_IN_SCHEDULE   ((uint32_t)0x00000030U) /*!< Synchronized to schedule       */
+/**
+  * @}
+  */
+
+/** @defgroup Interrupt_Masks Interrupt masks
+  * @{
+  */
+#define FDCAN_IR_MASK ((uint32_t)0x3FCFFFFFU) /*!< FDCAN interrupts mask */
+#define CCU_IR_MASK   ((uint32_t)0xC0000000U) /*!< CCU interrupts mask   */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_flags FDCAN Flags
+  * @{
+  */
+#define FDCAN_FLAG_TX_COMPLETE             FDCAN_IR_TC             /*!< Transmission Completed                                */
+#define FDCAN_FLAG_TX_ABORT_COMPLETE       FDCAN_IR_TCF            /*!< Transmission Cancellation Finished                    */
+#define FDCAN_FLAG_TX_FIFO_EMPTY           FDCAN_IR_TFE            /*!< Tx FIFO Empty                                         */
+#define FDCAN_FLAG_RX_HIGH_PRIORITY_MSG    FDCAN_IR_HPM            /*!< High priority message received                        */
+#define FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE   FDCAN_IR_DRX            /*!< At least one received message stored into a Rx Buffer */
+#define FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST    FDCAN_IR_TEFL           /*!< Tx Event FIFO element lost                            */
+#define FDCAN_FLAG_TX_EVT_FIFO_FULL        FDCAN_IR_TEFF           /*!< Tx Event FIFO full                                    */
+#define FDCAN_FLAG_TX_EVT_FIFO_WATERMARK   FDCAN_IR_TEFW           /*!< Tx Event FIFO fill level reached watermark            */
+#define FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA    FDCAN_IR_TEFN           /*!< Tx Handler wrote Tx Event FIFO element                */
+#define FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST   FDCAN_IR_RF0L           /*!< Rx FIFO 0 message lost                                */
+#define FDCAN_FLAG_RX_FIFO0_FULL           FDCAN_IR_RF0F           /*!< Rx FIFO 0 full                                        */
+#define FDCAN_FLAG_RX_FIFO0_WATERMARK      FDCAN_IR_RF0W           /*!< Rx FIFO 0 fill level reached watermark                */
+#define FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE    FDCAN_IR_RF0N           /*!< New message written to Rx FIFO 0                      */
+#define FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST   FDCAN_IR_RF1L           /*!< Rx FIFO 1 message lost                                */
+#define FDCAN_FLAG_RX_FIFO1_FULL           FDCAN_IR_RF1F           /*!< Rx FIFO 1 full                                        */
+#define FDCAN_FLAG_RX_FIFO1_WATERMARK      FDCAN_IR_RF1W           /*!< Rx FIFO 1 fill level reached watermark                */
+#define FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE    FDCAN_IR_RF1N           /*!< New message written to Rx FIFO 1                      */
+#define FDCAN_FLAG_RAM_ACCESS_FAILURE      FDCAN_IR_MRAF           /*!< Message RAM access failure occurred                   */
+#define FDCAN_FLAG_ERROR_LOGGING_OVERFLOW  FDCAN_IR_ELO            /*!< Overflow of FDCAN Error Logging Counter occurred      */
+#define FDCAN_FLAG_ERROR_PASSIVE           FDCAN_IR_EP             /*!< Error_Passive status changed                          */
+#define FDCAN_FLAG_ERROR_WARNING           FDCAN_IR_EW             /*!< Error_Warning status changed                          */
+#define FDCAN_FLAG_BUS_OFF                 FDCAN_IR_BO             /*!< Bus_Off status changed                                */
+#define FDCAN_FLAG_RAM_WATCHDOG            FDCAN_IR_WDI            /*!< Message RAM Watchdog event due to missing READY       */
+#define FDCAN_FLAG_ARB_PROTOCOL_ERROR      FDCAN_IR_PEA            /*!< Protocol error in arbitration phase detected          */
+#define FDCAN_FLAG_DATA_PROTOCOL_ERROR     FDCAN_IR_PED            /*!< Protocol error in data phase detected                 */
+#define FDCAN_FLAG_RESERVED_ADDRESS_ACCESS FDCAN_IR_ARA            /*!< Access to reserved address occurred                   */
+#define FDCAN_FLAG_TIMESTAMP_WRAPAROUND    FDCAN_IR_TSW            /*!< Timestamp counter wrapped around                      */
+#define FDCAN_FLAG_TIMEOUT_OCCURRED        FDCAN_IR_TOO            /*!< Timeout reached                                       */
+#define FDCAN_FLAG_CALIB_STATE_CHANGED     (FDCANCCU_IR_CSC << 30) /*!< Clock calibration state changed                       */
+#define FDCAN_FLAG_CALIB_WATCHDOG_EVENT    (FDCANCCU_IR_CWE << 30) /*!< Clock calibration watchdog event occurred             */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Interrupts FDCAN Interrupts
+  * @{
+  */
+
+/** @defgroup FDCAN_Tx_Interrupts FDCAN Tx Interrupts
+  * @{
+  */
+#define FDCAN_IT_TX_COMPLETE           FDCAN_IE_TCE   /*!< Transmission Completed                                */
+#define FDCAN_IT_TX_ABORT_COMPLETE     FDCAN_IE_TCFE  /*!< Transmission Cancellation Finished                    */
+#define FDCAN_IT_TX_FIFO_EMPTY         FDCAN_IE_TFEE  /*!< Tx FIFO Empty                                         */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Rx_Interrupts FDCAN Rx Interrupts
+  * @{
+  */
+#define FDCAN_IT_RX_HIGH_PRIORITY_MSG  FDCAN_IE_HPME  /*!< High priority message received                        */
+#define FDCAN_IT_RX_BUFFER_NEW_MESSAGE FDCAN_IE_DRXE  /*!< At least one received message stored into a Rx Buffer */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Counter_Interrupts FDCAN Counter Interrupts
+  * @{
+  */
+#define FDCAN_IT_TIMESTAMP_WRAPAROUND  FDCAN_IE_TSWE  /*!< Timestamp counter wrapped around                      */
+#define FDCAN_IT_TIMEOUT_OCCURRED      FDCAN_IE_TOOE  /*!< Timeout reached                                       */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Clock_Calibration_Interrupts Clock Calibration Interrupts
+  * @{
+  */
+#define FDCAN_IT_CALIB_STATE_CHANGED  (FDCANCCU_IE_CSCE << 30) /*!< Clock calibration state changed           */
+#define FDCAN_IT_CALIB_WATCHDOG_EVENT (FDCANCCU_IE_CWEE << 30) /*!< Clock calibration watchdog event occurred */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Tx_Event_Fifo_Interrupts FDCAN Tx Event FIFO Interrupts
+  * @{
+  */
+#define FDCAN_IT_TX_EVT_FIFO_ELT_LOST  FDCAN_IE_TEFLE /*!< Tx Event FIFO element lost                 */
+#define FDCAN_IT_TX_EVT_FIFO_FULL      FDCAN_IE_TEFFE /*!< Tx Event FIFO full                         */
+#define FDCAN_IT_TX_EVT_FIFO_WATERMARK FDCAN_IE_TEFWE /*!< Tx Event FIFO fill level reached watermark */
+#define FDCAN_IT_TX_EVT_FIFO_NEW_DATA  FDCAN_IE_TEFNE /*!< Tx Handler wrote Tx Event FIFO element     */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Rx_Fifo0_Interrupts FDCAN Rx FIFO 0 Interrupts
+  * @{
+  */
+#define FDCAN_IT_RX_FIFO0_MESSAGE_LOST FDCAN_IE_RF0LE /*!< Rx FIFO 0 message lost                 */
+#define FDCAN_IT_RX_FIFO0_FULL         FDCAN_IE_RF0FE /*!< Rx FIFO 0 full                         */
+#define FDCAN_IT_RX_FIFO0_WATERMARK    FDCAN_IE_RF0WE /*!< Rx FIFO 0 fill level reached watermark */
+#define FDCAN_IT_RX_FIFO0_NEW_MESSAGE  FDCAN_IE_RF0NE /*!< New message written to Rx FIFO 0       */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Rx_Fifo1_Interrupts FDCAN Rx FIFO 1 Interrupts
+  * @{
+  */
+#define FDCAN_IT_RX_FIFO1_MESSAGE_LOST FDCAN_IE_RF1LE /*!< Rx FIFO 1 message lost                 */
+#define FDCAN_IT_RX_FIFO1_FULL         FDCAN_IE_RF1FE /*!< Rx FIFO 1 full                         */
+#define FDCAN_IT_RX_FIFO1_WATERMARK    FDCAN_IE_RF1WE /*!< Rx FIFO 1 fill level reached watermark */
+#define FDCAN_IT_RX_FIFO1_NEW_MESSAGE  FDCAN_IE_RF1NE /*!< New message written to Rx FIFO 1       */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Error_Interrupts FDCAN Error Interrupts
+  * @{
+  */
+#define FDCAN_IT_RAM_ACCESS_FAILURE      FDCAN_IE_MRAFE /*!< Message RAM access failure occurred              */
+#define FDCAN_IT_ERROR_LOGGING_OVERFLOW  FDCAN_IE_ELOE  /*!< Overflow of FDCAN Error Logging Counter occurred */
+#define FDCAN_IT_RAM_WATCHDOG            FDCAN_IE_WDIE  /*!< Message RAM Watchdog event due to missing READY  */
+#define FDCAN_IT_ARB_PROTOCOL_ERROR      FDCAN_IE_PEAE  /*!< Protocol error in arbitration phase detected     */
+#define FDCAN_IT_DATA_PROTOCOL_ERROR     FDCAN_IE_PEDE  /*!< Protocol error in data phase detected            */
+#define FDCAN_IT_RESERVED_ADDRESS_ACCESS FDCAN_IE_ARAE  /*!< Access to reserved address occurred              */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Error_Status_Interrupts FDCAN Error Status Interrupts
+  * @{
+  */
+#define FDCAN_IT_ERROR_PASSIVE FDCAN_IE_EPE /*!< Error_Passive status changed */
+#define FDCAN_IT_ERROR_WARNING FDCAN_IE_EWE /*!< Error_Warning status changed */
+#define FDCAN_IT_BUS_OFF       FDCAN_IE_BOE /*!< Bus_Off status changed       */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TTflags FDCAN TT Flags
+  * @{
+  */
+#define FDCAN_TT_FLAG_BASIC_CYCLE_START    FDCAN_TTIR_SBC  /*!< Start of Basic Cycle             */
+#define FDCAN_TT_FLAG_MATRIX_CYCLE_START   FDCAN_TTIR_SMC  /*!< Start of Matrix Cycle            */
+#define FDCAN_TT_FLAG_SYNC_MODE_CHANGE     FDCAN_TTIR_CSM  /*!< Change of Synchronization Mode   */
+#define FDCAN_TT_FLAG_START_OF_GAP         FDCAN_TTIR_SOG  /*!< Start of Gap                     */
+#define FDCAN_TT_FLAG_REG_TIME_MARK        FDCAN_TTIR_RTMI /*!< Register Time Mark Interrupt     */
+#define FDCAN_TT_FLAG_TRIG_TIME_MARK       FDCAN_TTIR_TTMI /*!< Trigger Time Mark Event Internal */
+#define FDCAN_TT_FLAG_STOP_WATCH           FDCAN_TTIR_SWE  /*!< Stop Watch Event                 */
+#define FDCAN_TT_FLAG_GLOBAL_TIME_WRAP     FDCAN_TTIR_GTW  /*!< Global Time Wrap                 */
+#define FDCAN_TT_FLAG_GLOBAL_TIME_DISC     FDCAN_TTIR_GTD  /*!< Global Time Discontinuity        */
+#define FDCAN_TT_FLAG_GLOBAL_TIME_ERROR    FDCAN_TTIR_GTE  /*!< Global Time Error                */
+#define FDCAN_TT_FLAG_TX_COUNT_UNDERFLOW   FDCAN_TTIR_TXU  /*!< Tx Count Underflow               */
+#define FDCAN_TT_FLAG_TX_COUNT_OVERFLOW    FDCAN_TTIR_TXO  /*!< Tx Count Overflow                */
+#define FDCAN_TT_FLAG_SCHEDULING_ERROR_1   FDCAN_TTIR_SE1  /*!< Scheduling Error 1               */
+#define FDCAN_TT_FLAG_SCHEDULING_ERROR_2   FDCAN_TTIR_SE2  /*!< Scheduling Error 2               */
+#define FDCAN_TT_FLAG_ERROR_LEVEL_CHANGE   FDCAN_TTIR_ELC  /*!< Error Level Changed              */
+#define FDCAN_TT_FLAG_INIT_WATCH_TRIGGER   FDCAN_TTIR_IWT  /*!< Initialization Watch Trigger     */
+#define FDCAN_TT_FLAG_WATCH_TRIGGER        FDCAN_TTIR_WT   /*!< Watch Trigger                    */
+#define FDCAN_TT_FLAG_APPLICATION_WATCHDOG FDCAN_TTIR_AW   /*!< Application Watchdog             */
+#define FDCAN_TT_FLAG_CONFIG_ERROR         FDCAN_TTIR_CER  /*!< Configuration Error              */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TTInterrupts FDCAN TT Interrupts
+  * @{
+  */
+
+/** @defgroup FDCAN_TTScheduleSynchronization_Interrupts FDCAN TT Schedule Synchronization Interrupts
+  * @{
+  */
+#define FDCAN_TT_IT_BASIC_CYCLE_START  FDCAN_TTIE_SBCE /*!< Start of Basic Cycle           */
+#define FDCAN_TT_IT_MATRIX_CYCLE_START FDCAN_TTIE_SMCE /*!< Start of Matrix Cycle          */
+#define FDCAN_TT_IT_SYNC_MODE_CHANGE   FDCAN_TTIE_CSME /*!< Change of Synchronization Mode */
+#define FDCAN_TT_IT_START_OF_GAP       FDCAN_TTIE_SOGE /*!< Start of Gap                   */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TTTimeMark_Interrupts FDCAN TT Time Mark Interrupts
+  * @{
+  */
+#define FDCAN_TT_IT_REG_TIME_MARK  FDCAN_TTIE_RTMIE /*!< Register Time Mark Interrupt     */
+#define FDCAN_TT_IT_TRIG_TIME_MARK FDCAN_TTIE_TTMIE /*!< Trigger Time Mark Event Internal */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TTStopWatch_Interrupt FDCAN TT Stop Watch Interrupt
+  * @{
+  */
+#define FDCAN_TT_IT_STOP_WATCH FDCAN_TTIE_SWEE /*!< Stop Watch Event */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TTGlobalTime_Interrupts FDCAN TT Global Time Interrupts
+  * @{
+  */
+#define FDCAN_TT_IT_GLOBAL_TIME_WRAP FDCAN_TTIE_GTWE  /*!< Global Time Wrap          */
+#define FDCAN_TT_IT_GLOBAL_TIME_DISC FDCAN_TTIE_GTDE  /*!< Global Time Discontinuity */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TTDisturbingError_Interrupts FDCAN TT Disturbing Error Interrupts
+  * @{
+  */
+#define FDCAN_TT_IT_GLOBAL_TIME_ERROR  FDCAN_TTIE_GTEE /*!< Global Time Error   */
+#define FDCAN_TT_IT_TX_COUNT_UNDERFLOW FDCAN_TTIE_TXUE /*!< Tx Count Underflow  */
+#define FDCAN_TT_IT_TX_COUNT_OVERFLOW  FDCAN_TTIE_TXOE /*!< Tx Count Overflow   */
+#define FDCAN_TT_IT_SCHEDULING_ERROR_1 FDCAN_TTIE_SE1E /*!< Scheduling Error 1  */
+#define FDCAN_TT_IT_SCHEDULING_ERROR_2 FDCAN_TTIE_SE2E /*!< Scheduling Error 2  */
+#define FDCAN_TT_IT_ERROR_LEVEL_CHANGE FDCAN_TTIE_ELCE /*!< Error Level Changed */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TTFatalError_Interrupts FDCAN TT Fatal Error Interrupts
+  * @{
+  */
+#define FDCAN_TT_IT_INIT_WATCH_TRIGGER   FDCAN_TTIE_IWTE /*!< Initialization Watch Trigger */
+#define FDCAN_TT_IT_WATCH_TRIGGER        FDCAN_TTIE_WTE  /*!< Watch Trigger                */
+#define FDCAN_TT_IT_APPLICATION_WATCHDOG FDCAN_TTIE_AWE  /*!< Application Watchdog         */
+#define FDCAN_TT_IT_CONFIG_ERROR         FDCAN_TTIE_CERE /*!< Configuration Error          */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup FDCAN_Exported_Macros FDCAN Exported Macros
+  * @{
+  */
+
+/** @brief  Reset FDCAN handle state.
+  * @param  __HANDLE__ FDCAN handle.
+  * @retval None
+  */
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) do{                                                \
+                                                      (__HANDLE__)->State = HAL_FDCAN_STATE_RESET;    \
+                                                      (__HANDLE__)->MspInitCallback = NULL;           \
+                                                      (__HANDLE__)->MspDeInitCallback = NULL;         \
+                                                     } while(0)
+#else
+#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FDCAN_STATE_RESET)
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+/**
+  * @brief  Enable the specified FDCAN interrupts.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ FDCAN interrupt.
+  *         This parameter can be any combination of @arg FDCAN_Interrupts
+  * @retval None
+  */
+#define __HAL_FDCAN_ENABLE_IT(__HANDLE__, __INTERRUPT__)             \
+  do{                                                                \
+    (__HANDLE__)->Instance->IE |= ((__INTERRUPT__) & FDCAN_IR_MASK); \
+    FDCAN_CCU->IE |= (((__INTERRUPT__) & CCU_IR_MASK) >> 30);        \
+  }while(0)
+
+
+/**
+  * @brief  Disable the specified FDCAN interrupts.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ FDCAN interrupt.
+  *         This parameter can be any combination of @arg FDCAN_Interrupts
+  * @retval None
+  */
+#define __HAL_FDCAN_DISABLE_IT(__HANDLE__, __INTERRUPT__)               \
+  do{                                                                   \
+    ((__HANDLE__)->Instance->IE) &= ~((__INTERRUPT__) & FDCAN_IR_MASK); \
+    FDCAN_CCU->IE &= ~(((__INTERRUPT__) & CCU_IR_MASK) >> 30);          \
+  }while(0)
+
+/**
+  * @brief  Check whether the specified FDCAN interrupt is set or not.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ FDCAN interrupt.
+  *         This parameter can be one of @arg FDCAN_Interrupts
+  * @retval ITStatus
+  */
+#define __HAL_FDCAN_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__INTERRUPT__)) : ((FDCAN_CCU->IR << 30) & (__INTERRUPT__)))
+
+/**
+  * @brief  Clear the specified FDCAN interrupts.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ specifies the interrupts to clear.
+  *         This parameter can be any combination of @arg FDCAN_Interrupts
+  * @retval None
+  */
+#define __HAL_FDCAN_CLEAR_IT(__HANDLE__, __INTERRUPT__)               \
+do{                                                                   \
+    ((__HANDLE__)->Instance->IR) = ((__INTERRUPT__) & FDCAN_IR_MASK); \
+    FDCAN_CCU->IR = (((__INTERRUPT__) & CCU_IR_MASK) >> 30);          \
+  }while(0)
+
+/**
+  * @brief  Check whether the specified FDCAN flag is set or not.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __FLAG__ FDCAN flag.
+  *         This parameter can be one of @arg FDCAN_flags
+  * @retval FlagStatus
+  */
+#define __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) < FDCAN_FLAG_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__FLAG__)) : ((FDCAN_CCU->IR << 30) & (__FLAG__)))
+
+/**
+  * @brief  Clear the specified FDCAN flags.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __FLAG__ specifies the flags to clear.
+  *         This parameter can be any combination of @arg FDCAN_flags
+  * @retval None
+  */
+#define __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__)             \
+do{                                                              \
+    ((__HANDLE__)->Instance->IR) = ((__FLAG__) & FDCAN_IR_MASK); \
+    FDCAN_CCU->IR = (((__FLAG__) & CCU_IR_MASK) >> 30);          \
+  }while(0)
+
+/** @brief  Check if the specified FDCAN interrupt source is enabled or disabled.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ specifies the FDCAN interrupt source to check.
+  *         This parameter can be a value of @arg FDCAN_Interrupts
+  * @retval ITStatus
+  */
+#define __HAL_FDCAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IE & (__INTERRUPT__)) : ((FDCAN_CCU->IE << 30) & (__INTERRUPT__)))
+
+/**
+  * @brief  Enable the specified FDCAN TT interrupts.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ FDCAN TT interrupt.
+  *         This parameter can be any combination of @arg FDCAN_TTInterrupts
+  * @retval None
+  */
+#define __HAL_FDCAN_TT_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the specified FDCAN TT interrupts.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ FDCAN TT interrupt.
+  *         This parameter can be any combination of @arg FDCAN_TTInterrupts
+  * @retval None
+  */
+#define __HAL_FDCAN_TT_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified FDCAN TT interrupt is set or not.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ FDCAN TT interrupt.
+  *         This parameter can be one of @arg FDCAN_TTInterrupts
+  * @retval ITStatus
+  */
+#define __HAL_FDCAN_TT_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) & (__INTERRUPT__))
+
+/**
+  * @brief  Clear the specified FDCAN TT interrupts.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ specifies the TT interrupts to clear.
+  *         This parameter can be any combination of @arg FDCAN_TTInterrupts
+  * @retval None
+  */
+#define __HAL_FDCAN_TT_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) = (__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified FDCAN TT flag is set or not.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __FLAG__ FDCAN TT flag.
+  *         This parameter can be one of @arg FDCAN_TTflags
+  * @retval FlagStatus
+  */
+#define __HAL_FDCAN_TT_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) & (__FLAG__))
+
+/**
+  * @brief  Clear the specified FDCAN TT flags.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __FLAG__ specifies the TT flags to clear.
+  *         This parameter can be any combination of @arg FDCAN_TTflags
+  * @retval None
+  */
+#define __HAL_FDCAN_TT_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) = (__FLAG__))
+
+/** @brief  Check if the specified FDCAN TT interrupt source is enabled or disabled.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ specifies the FDCAN TT interrupt source to check.
+  *         This parameter can be a value of @arg FDCAN_TTInterrupts
+  * @retval ITStatus
+  */
+#define __HAL_FDCAN_TT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) & (__INTERRUPT__))
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FDCAN_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup FDCAN_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan);
+void              HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan);
+void              HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+/* Callbacks Register/UnRegister functions  ***********************************/
+HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, pFDCAN_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID);
+HAL_StatusTypeDef HAL_FDCAN_RegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ClockCalibrationCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxEventFifoCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo0CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo1CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferCompleteCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferAbortCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ErrorStatusCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_ScheduleSyncCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_TimeMarkCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_StopWatchCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_GlobalTimeCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @addtogroup FDCAN_Exported_Functions_Group2
+  * @{
+  */
+/* Configuration functions ****************************************************/
+HAL_StatusTypeDef HAL_FDCAN_ConfigClockCalibration(FDCAN_HandleTypeDef *hfdcan, FDCAN_ClkCalUnitTypeDef *sCcuConfig);
+uint32_t          HAL_FDCAN_GetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ResetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan);
+uint32_t          HAL_FDCAN_GetClockCalibrationCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t Counter);
+HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig);
+HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd, uint32_t NonMatchingExt, uint32_t RejectRemoteStd, uint32_t RejectRemoteExt);
+HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask);
+HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode);
+HAL_StatusTypeDef HAL_FDCAN_ConfigFifoWatermark(FDCAN_HandleTypeDef *hfdcan, uint32_t FIFO, uint32_t Watermark);
+HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue);
+HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler);
+HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation);
+HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
+uint16_t          HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod);
+HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
+uint16_t          HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter);
+HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan);
+/**
+  * @}
+  */
+
+/** @addtogroup FDCAN_Exported_Functions_Group3
+  * @{
+  */
+/* Control functions **********************************************************/
+HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData);
+HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxBuffer(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex);
+HAL_StatusTypeDef HAL_FDCAN_EnableTxBufferRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex);
+uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex);
+HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData);
+HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent);
+HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus);
+HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus);
+HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters);
+uint32_t HAL_FDCAN_IsRxBufferMessageAvailable(FDCAN_HandleTypeDef *hfdcan, uint32_t RxBufferIndex);
+uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex);
+uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo);
+uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan);
+uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan);
+/**
+  * @}
+  */
+
+/** @addtogroup FDCAN_Exported_Functions_Group4
+  * @{
+  */
+/* TT Configuration and control functions**************************************/
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigOperation(FDCAN_HandleTypeDef *hfdcan, FDCAN_TT_ConfigTypeDef *pTTParams);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigReferenceMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t IdType, uint32_t Identifier, uint32_t Payload);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigTrigger(FDCAN_HandleTypeDef *hfdcan, FDCAN_TriggerTypeDef *sTriggerConfig);
+HAL_StatusTypeDef HAL_FDCAN_TT_SetGlobalTime(FDCAN_HandleTypeDef *hfdcan, uint32_t TimePreset);
+HAL_StatusTypeDef HAL_FDCAN_TT_SetClockSynchronization(FDCAN_HandleTypeDef *hfdcan, uint32_t NewTURNumerator);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigStopWatch(FDCAN_HandleTypeDef *hfdcan, uint32_t Source, uint32_t Polarity);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigRegisterTimeMark(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeMarkSource, uint32_t TimeMarkValue, uint32_t RepeatFactor, uint32_t StartCycle);
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_SetNextIsGap(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_SetEndOfGap(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigExternalSyncPhase(FDCAN_HandleTypeDef *hfdcan, uint32_t TargetPhase);
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_GetOperationStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_TTOperationStatusTypeDef *TTOpStatus);
+/**
+  * @}
+  */
+
+/** @addtogroup FDCAN_Exported_Functions_Group5
+  * @{
+  */
+/* Interrupts management ******************************************************/
+HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t TTITList, uint32_t InterruptLine);
+HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes);
+HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs);
+HAL_StatusTypeDef HAL_FDCAN_TT_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveTTITs);
+HAL_StatusTypeDef HAL_FDCAN_TT_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveTTITs);
+void              HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan);
+/**
+  * @}
+  */
+
+/** @addtogroup FDCAN_Exported_Functions_Group6
+  * @{
+  */
+/* Callback functions *********************************************************/
+void HAL_FDCAN_ClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs);
+void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs);
+void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs);
+void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs);
+void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);
+void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);
+void HAL_FDCAN_RxBufferNewMessageCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs);
+void HAL_FDCAN_TT_ScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs);
+void HAL_FDCAN_TT_TimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs);
+void HAL_FDCAN_TT_StopWatchCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount);
+void HAL_FDCAN_TT_GlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs);
+/**
+  * @}
+  */
+
+/** @addtogroup FDCAN_Exported_Functions_Group7
+  * @{
+  */
+/* Peripheral State functions *************************************************/
+uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan);
+HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup FDCAN_Private_Types FDCAN Private Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup FDCAN_Private_Variables FDCAN Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup FDCAN_Private_Constants FDCAN Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FDCAN_Private_Macros FDCAN Private Macros
+  * @{
+  */
+#define IS_FDCAN_FRAME_FORMAT(FORMAT) (((FORMAT) == FDCAN_FRAME_CLASSIC  ) || \
+                                       ((FORMAT) == FDCAN_FRAME_FD_NO_BRS) || \
+                                       ((FORMAT) == FDCAN_FRAME_FD_BRS   ))
+#define IS_FDCAN_MODE(MODE) (((MODE) == FDCAN_MODE_NORMAL              ) || \
+                             ((MODE) == FDCAN_MODE_RESTRICTED_OPERATION) || \
+                             ((MODE) == FDCAN_MODE_BUS_MONITORING      ) || \
+                             ((MODE) == FDCAN_MODE_INTERNAL_LOOPBACK   ) || \
+                             ((MODE) == FDCAN_MODE_EXTERNAL_LOOPBACK   ))
+
+#define IS_FDCAN_CLOCK_CALIBRATION(CALIBRATION) (((CALIBRATION) == FDCAN_CLOCK_CALIBRATION_DISABLE) || \
+                                                 ((CALIBRATION) == FDCAN_CLOCK_CALIBRATION_ENABLE ))
+
+#define IS_FDCAN_CKDIV(CKDIV) (((CKDIV) == FDCAN_CLOCK_DIV1 ) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV2 ) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV4 ) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV6 ) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV8 ) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV10) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV12) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV14) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV16) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV18) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV20) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV22) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV24) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV26) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV28) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV30))
+#define IS_FDCAN_NOMINAL_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 512U))
+#define IS_FDCAN_NOMINAL_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 128U))
+#define IS_FDCAN_NOMINAL_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 256U))
+#define IS_FDCAN_NOMINAL_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 128U))
+#define IS_FDCAN_DATA_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 32U))
+#define IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 16U))
+#define IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 32U))
+#define IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 16U))
+#define IS_FDCAN_MAX_VALUE(VALUE, MAX) ((VALUE) <= (MAX))
+#define IS_FDCAN_MIN_VALUE(VALUE, MIN) ((VALUE) >= (MIN))
+#define IS_FDCAN_DATA_SIZE(SIZE) (((SIZE) == FDCAN_DATA_BYTES_8 ) || \
+                                  ((SIZE) == FDCAN_DATA_BYTES_12) || \
+                                  ((SIZE) == FDCAN_DATA_BYTES_16) || \
+                                  ((SIZE) == FDCAN_DATA_BYTES_20) || \
+                                  ((SIZE) == FDCAN_DATA_BYTES_24) || \
+                                  ((SIZE) == FDCAN_DATA_BYTES_32) || \
+                                  ((SIZE) == FDCAN_DATA_BYTES_48) || \
+                                  ((SIZE) == FDCAN_DATA_BYTES_64))
+#define IS_FDCAN_TX_FIFO_QUEUE_MODE(MODE) (((MODE) == FDCAN_TX_FIFO_OPERATION ) || \
+                                           ((MODE) == FDCAN_TX_QUEUE_OPERATION))
+#define IS_FDCAN_ID_TYPE(ID_TYPE) (((ID_TYPE) == FDCAN_STANDARD_ID) || \
+                                   ((ID_TYPE) == FDCAN_EXTENDED_ID))
+#define IS_FDCAN_FILTER_CFG(CONFIG) (((CONFIG) == FDCAN_FILTER_DISABLE      ) || \
+                                     ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0   ) || \
+                                     ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1   ) || \
+                                     ((CONFIG) == FDCAN_FILTER_REJECT       ) || \
+                                     ((CONFIG) == FDCAN_FILTER_HP           ) || \
+                                     ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0_HP) || \
+                                     ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1_HP) || \
+                                     ((CONFIG) == FDCAN_FILTER_TO_RXBUFFER  ))
+#define IS_FDCAN_TX_LOCATION(LOCATION) (((LOCATION) == FDCAN_TX_BUFFER0 ) || ((LOCATION) == FDCAN_TX_BUFFER1 ) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER2 ) || ((LOCATION) == FDCAN_TX_BUFFER3 ) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER4 ) || ((LOCATION) == FDCAN_TX_BUFFER5 ) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER6 ) || ((LOCATION) == FDCAN_TX_BUFFER7 ) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER8 ) || ((LOCATION) == FDCAN_TX_BUFFER9 ) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER10) || ((LOCATION) == FDCAN_TX_BUFFER11) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER12) || ((LOCATION) == FDCAN_TX_BUFFER13) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER14) || ((LOCATION) == FDCAN_TX_BUFFER15) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER16) || ((LOCATION) == FDCAN_TX_BUFFER17) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER18) || ((LOCATION) == FDCAN_TX_BUFFER19) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER20) || ((LOCATION) == FDCAN_TX_BUFFER21) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER22) || ((LOCATION) == FDCAN_TX_BUFFER23) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER24) || ((LOCATION) == FDCAN_TX_BUFFER25) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER26) || ((LOCATION) == FDCAN_TX_BUFFER27) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER28) || ((LOCATION) == FDCAN_TX_BUFFER29) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER30) || ((LOCATION) == FDCAN_TX_BUFFER31))
+#define IS_FDCAN_RX_FIFO(FIFO) (((FIFO) == FDCAN_RX_FIFO0) || \
+                                ((FIFO) == FDCAN_RX_FIFO1))
+#define IS_FDCAN_RX_FIFO_MODE(MODE) (((MODE) == FDCAN_RX_FIFO_BLOCKING ) || \
+                                     ((MODE) == FDCAN_RX_FIFO_OVERWRITE))
+#define IS_FDCAN_STD_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE) || \
+                                        ((TYPE) == FDCAN_FILTER_DUAL ) || \
+                                        ((TYPE) == FDCAN_FILTER_MASK ))
+#define IS_FDCAN_EXT_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE        ) || \
+                                        ((TYPE) == FDCAN_FILTER_DUAL         ) || \
+                                        ((TYPE) == FDCAN_FILTER_MASK         ) || \
+                                        ((TYPE) == FDCAN_FILTER_RANGE_NO_EIDM))
+#define IS_FDCAN_FRAME_TYPE(TYPE) (((TYPE) == FDCAN_DATA_FRAME  ) || \
+                                   ((TYPE) == FDCAN_REMOTE_FRAME))
+#define IS_FDCAN_DLC(DLC) (((DLC) == FDCAN_DLC_BYTES_0 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_1 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_2 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_3 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_4 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_5 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_6 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_7 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_8 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_12) || \
+                           ((DLC) == FDCAN_DLC_BYTES_16) || \
+                           ((DLC) == FDCAN_DLC_BYTES_20) || \
+                           ((DLC) == FDCAN_DLC_BYTES_24) || \
+                           ((DLC) == FDCAN_DLC_BYTES_32) || \
+                           ((DLC) == FDCAN_DLC_BYTES_48) || \
+                           ((DLC) == FDCAN_DLC_BYTES_64))
+#define IS_FDCAN_ESI(ESI) (((ESI) == FDCAN_ESI_ACTIVE ) || \
+                           ((ESI) == FDCAN_ESI_PASSIVE))
+#define IS_FDCAN_BRS(BRS) (((BRS) == FDCAN_BRS_OFF) || \
+                           ((BRS) == FDCAN_BRS_ON ))
+#define IS_FDCAN_FDF(FDF) (((FDF) == FDCAN_CLASSIC_CAN) || \
+                           ((FDF) == FDCAN_FD_CAN     ))
+#define IS_FDCAN_EFC(EFC) (((EFC) == FDCAN_NO_TX_EVENTS   ) || \
+                           ((EFC) == FDCAN_STORE_TX_EVENTS))
+#define IS_FDCAN_IT(IT) (((IT) & ~(FDCAN_IR_MASK | CCU_IR_MASK)) == 0U)
+#define IS_FDCAN_TT_IT(IT) (((IT) & 0xFFF80000U) == 0U)
+#define IS_FDCAN_FIFO_WATERMARK(FIFO) (((FIFO) == FDCAN_CFG_TX_EVENT_FIFO) || \
+                                       ((FIFO) == FDCAN_CFG_RX_FIFO0     ) || \
+                                       ((FIFO) == FDCAN_CFG_RX_FIFO1     ))
+#define IS_FDCAN_NON_MATCHING(DESTINATION) (((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO0) || \
+                                            ((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO1) || \
+                                            ((DESTINATION) == FDCAN_REJECT            ))
+#define IS_FDCAN_REJECT_REMOTE(DESTINATION) (((DESTINATION) == FDCAN_FILTER_REMOTE) || \
+                                             ((DESTINATION) == FDCAN_REJECT_REMOTE))
+#define IS_FDCAN_IT_LINE(IT_LINE) (((IT_LINE) == FDCAN_INTERRUPT_LINE0) || \
+                                   ((IT_LINE) == FDCAN_INTERRUPT_LINE1))
+#define IS_FDCAN_TIMESTAMP(OPERATION) (((OPERATION) == FDCAN_TIMESTAMP_INTERNAL) || \
+                                       ((OPERATION) == FDCAN_TIMESTAMP_EXTERNAL))
+#define IS_FDCAN_TIMESTAMP_PRESCALER(PRESCALER) (((PRESCALER) == FDCAN_TIMESTAMP_PRESC_1 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_2 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_3 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_4 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_5 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_6 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_7 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_8 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_9 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_10) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_11) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_12) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_13) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_14) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_15) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_16))
+#define IS_FDCAN_TIMEOUT(OPERATION) (((OPERATION) == FDCAN_TIMEOUT_CONTINUOUS   ) || \
+                                     ((OPERATION) == FDCAN_TIMEOUT_TX_EVENT_FIFO) || \
+                                     ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO0     ) || \
+                                     ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO1     ))
+#define IS_FDCAN_CALIBRATION_FIELD_LENGTH(LENGTH) (((LENGTH) == FDCAN_CALIB_FIELD_LENGTH_32) || \
+                                                   ((LENGTH) == FDCAN_CALIB_FIELD_LENGTH_64))
+#define IS_FDCAN_CALIBRATION_COUNTER(COUNTER) (((COUNTER) == FDCAN_CALIB_TIME_QUANTA_COUNTER ) || \
+                                               ((COUNTER) == FDCAN_CALIB_CLOCK_PERIOD_COUNTER) || \
+                                               ((COUNTER) == FDCAN_CALIB_WATCHDOG_COUNTER    ))
+#define IS_FDCAN_TT_REFERENCE_MESSAGE_PAYLOAD(PAYLOAD) (((PAYLOAD) == FDCAN_TT_REF_MESSAGE_NO_PAYLOAD ) || \
+                                                        ((PAYLOAD) == FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD))
+#define IS_FDCAN_TT_REPEAT_FACTOR(FACTOR) (((FACTOR) == FDCAN_TT_REPEAT_EVERY_CYCLE     ) || \
+                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_2ND_CYCLE ) || \
+                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_4TH_CYCLE ) || \
+                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_8TH_CYCLE ) || \
+                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_16TH_CYCLE) || \
+                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_32ND_CYCLE) || \
+                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_64TH_CYCLE))
+#define IS_FDCAN_TT_TRIGGER_TYPE(TYPE) (((TYPE) == FDCAN_TT_TX_REF_TRIGGER        ) || \
+                                        ((TYPE) == FDCAN_TT_TX_REF_TRIGGER_GAP    ) || \
+                                        ((TYPE) == FDCAN_TT_TX_TRIGGER_SINGLE     ) || \
+                                        ((TYPE) == FDCAN_TT_TX_TRIGGER_CONTINUOUS ) || \
+                                        ((TYPE) == FDCAN_TT_TX_TRIGGER_ARBITRATION) || \
+                                        ((TYPE) == FDCAN_TT_TX_TRIGGER_MERGED     ) || \
+                                        ((TYPE) == FDCAN_TT_WATCH_TRIGGER         ) || \
+                                        ((TYPE) == FDCAN_TT_WATCH_TRIGGER_GAP     ) || \
+                                        ((TYPE) == FDCAN_TT_RX_TRIGGER            ) || \
+                                        ((TYPE) == FDCAN_TT_TIME_BASE_TRIGGER     ) || \
+                                        ((TYPE) == FDCAN_TT_END_OF_LIST           ))
+#define IS_FDCAN_TT_TM_EVENT_INTERNAL(EVENT) (((EVENT) == FDCAN_TT_TM_NO_INTERNAL_EVENT ) || \
+                                              ((EVENT) == FDCAN_TT_TM_GEN_INTERNAL_EVENT))
+#define IS_FDCAN_TT_TM_EVENT_EXTERNAL(EVENT) (((EVENT) == FDCAN_TT_TM_NO_EXTERNAL_EVENT ) || \
+                                              ((EVENT) == FDCAN_TT_TM_GEN_EXTERNAL_EVENT))
+#define IS_FDCAN_OPERATION_MODE(MODE) (((MODE) == FDCAN_TT_COMMUNICATION_LEVEL1 ) || \
+                                       ((MODE) == FDCAN_TT_COMMUNICATION_LEVEL2 ) || \
+                                       ((MODE) == FDCAN_TT_COMMUNICATION_LEVEL0 ))
+#define IS_FDCAN_TT_OPERATION(OPERATION) (((OPERATION) == FDCAN_STRICTLY_TT_OPERATION      ) || \
+                                          ((OPERATION) == FDCAN_EXT_EVT_SYNC_TT_OPERATION))
+#define IS_FDCAN_TT_TIME_MASTER(FUNCTION) (((FUNCTION) == FDCAN_TT_SLAVE           ) || \
+                                           ((FUNCTION) == FDCAN_TT_POTENTIAL_MASTER))
+#define IS_FDCAN_TT_EXTERNAL_CLK_SYNC(SYNC) (((SYNC) == FDCAN_TT_EXT_CLK_SYNC_DISABLE) || \
+                                             ((SYNC) == FDCAN_TT_EXT_CLK_SYNC_ENABLE ))
+#define IS_FDCAN_TT_GLOBAL_TIME_FILTERING(FILTERING) (((FILTERING) == FDCAN_TT_GLOB_TIME_FILT_DISABLE) || \
+                                                      ((FILTERING) == FDCAN_TT_GLOB_TIME_FILT_ENABLE ))
+#define IS_FDCAN_TT_AUTO_CLK_CALIBRATION(CALIBRATION) (((CALIBRATION) == FDCAN_TT_AUTO_CLK_CALIB_DISABLE) || \
+                                                       ((CALIBRATION) == FDCAN_TT_AUTO_CLK_CALIB_ENABLE ))
+#define IS_FDCAN_TT_EVENT_TRIGGER_POLARITY(POLARITY) (((POLARITY) == FDCAN_TT_EVT_TRIG_POL_RISING ) || \
+                                                      ((POLARITY) == FDCAN_TT_EVT_TRIG_POL_FALLING))
+#define IS_FDCAN_TT_BASIC_CYCLES_NUMBER(NUMBER) (((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_1 ) || \
+                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_2 ) || \
+                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_4 ) || \
+                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_8 ) || \
+                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_16) || \
+                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_32) || \
+                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_64))
+#define IS_FDCAN_TT_CYCLE_START_SYNC(SYNC) (((SYNC) == FDCAN_TT_NO_SYNC_PULSE         ) || \
+                                            ((SYNC) == FDCAN_TT_SYNC_BASIC_CYCLE_START) || \
+                                            ((SYNC) == FDCAN_TT_SYNC_MATRIX_START     ))
+#define IS_FDCAN_TT_TX_ENABLE_WINDOW(NTU) (((NTU) >= 1U) && ((NTU) <= 16U))
+#define IS_FDCAN_TT_TUR_NUMERATOR(NUMERATOR) (((NUMERATOR) >= 0x10000U) && ((NUMERATOR) <= 0x1FFFFU))
+#define IS_FDCAN_TT_TUR_DENOMINATOR(DENOMINATOR) (((DENOMINATOR) >= 0x0001U) && ((DENOMINATOR) <= 0x3FFFU))
+#define IS_FDCAN_TT_TUR_LEVEL_1(NC,DC) ((NC) >= (4U * (DC)))
+#define IS_FDCAN_TT_TUR_LEVEL_0_2(NC,DC) ((NC) >= (8U * (DC)))
+#define IS_FDCAN_TT_STOP_WATCH_TRIGGER(TRIGGER) (((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_0) || \
+                                                 ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_1) || \
+                                                 ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_2) || \
+                                                 ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_3))
+#define IS_FDCAN_TT_EVENT_TRIGGER(TRIGGER) (((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_0) || \
+                                            ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_1) || \
+                                            ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_2) || \
+                                            ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_3))
+#define IS_FDCAN_TT_TIME_PRESET(TIME) (((TIME) <= 0xFFFFU) && ((TIME) != 0x8000U))
+#define IS_FDCAN_TT_STOP_WATCH_SOURCE(SOURCE) (((SOURCE) == FDCAN_TT_STOP_WATCH_DISABLED   ) || \
+                                               ((SOURCE) == FDCAN_TT_STOP_WATCH_CYCLE_TIME ) || \
+                                               ((SOURCE) == FDCAN_TT_STOP_WATCH_LOCAL_TIME ) || \
+                                               ((SOURCE) == FDCAN_TT_STOP_WATCH_GLOBAL_TIME))
+#define IS_FDCAN_TT_STOP_WATCH_POLARITY(POLARITY) (((POLARITY) == FDCAN_TT_STOP_WATCH_RISING ) || \
+                                                   ((POLARITY) == FDCAN_TT_STOP_WATCH_FALLING))
+#define IS_FDCAN_TT_REGISTER_TIME_MARK_SOURCE(SOURCE) (((SOURCE) == FDCAN_TT_REG_TIMEMARK_DIABLED ) || \
+                                                       ((SOURCE) == FDCAN_TT_REG_TIMEMARK_CYC_TIME) || \
+                                                       ((SOURCE) == FDCAN_TT_REG_TIMEMARK_LOC_TIME) || \
+                                                       ((SOURCE) == FDCAN_TT_REG_TIMEMARK_GLO_TIME))
+/**
+  * @}
+  */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup FDCAN_Private_Functions_Prototypes FDCAN Private Functions Prototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup FDCAN_Private_Functions FDCAN Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_FDCAN_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h
new file mode 100644
index 00000000..6bda249e
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h
@@ -0,0 +1,829 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_flash.h
+  * @author  MCD Application Team
+  * @brief   Header file of FLASH HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_FLASH_H
+#define STM32H7xx_HAL_FLASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FLASH
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Types FLASH Exported Types
+  * @{
+  */
+
+/**
+  * @brief  FLASH Procedure structure definition
+  */
+typedef enum
+{
+  FLASH_PROC_NONE = 0U,
+  FLASH_PROC_SECTERASE_BANK1,
+  FLASH_PROC_MASSERASE_BANK1,
+  FLASH_PROC_PROGRAM_BANK1,
+  FLASH_PROC_SECTERASE_BANK2,
+  FLASH_PROC_MASSERASE_BANK2,
+  FLASH_PROC_PROGRAM_BANK2,
+  FLASH_PROC_ALLBANK_MASSERASE
+} FLASH_ProcedureTypeDef;
+
+
+/**
+  * @brief  FLASH handle Structure definition
+  */
+typedef struct
+{
+  __IO FLASH_ProcedureTypeDef ProcedureOnGoing;   /*!< Internal variable to indicate which procedure is ongoing or not in IT context */
+
+  __IO uint32_t               NbSectorsToErase;   /*!< Internal variable to save the remaining sectors to erase in IT context        */
+
+  __IO uint32_t               VoltageForErase;    /*!< Internal variable to provide voltage range selected by user in IT context     */
+
+  __IO uint32_t               Sector;             /*!< Internal variable to define the current sector which is erasing               */
+
+  __IO uint32_t               Address;            /*!< Internal variable to save address selected for program                        */
+
+  HAL_LockTypeDef             Lock;               /*!< FLASH locking object                                                          */
+
+  __IO uint32_t               ErrorCode;          /*!< FLASH error code                                                              */
+
+}FLASH_ProcessTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
+  * @{
+  */
+
+/** @defgroup FLASH_Error_Code FLASH Error Code
+  * @brief    FLASH Error Code
+  * @{
+  */
+#define HAL_FLASH_ERROR_NONE         0x00000000U               /*!< No error                              */
+
+#define HAL_FLASH_ERROR_WRP          FLASH_FLAG_WRPERR         /*!< Write Protection Error                */
+#define HAL_FLASH_ERROR_PGS          FLASH_FLAG_PGSERR         /*!< Program Sequence Error                */
+#define HAL_FLASH_ERROR_STRB         FLASH_FLAG_STRBERR        /*!< Strobe Error                          */
+#define HAL_FLASH_ERROR_INC          FLASH_FLAG_INCERR         /*!< Inconsistency Error                   */
+#if defined (FLASH_SR_OPERR)
+#define HAL_FLASH_ERROR_OPE          FLASH_FLAG_OPERR          /*!< Operation Error                       */
+#endif /* FLASH_SR_OPERR */
+#define HAL_FLASH_ERROR_RDP          FLASH_FLAG_RDPERR         /*!< Read Protection Error                 */
+#define HAL_FLASH_ERROR_RDS          FLASH_FLAG_RDSERR         /*!< Read Secured Error                    */
+#define HAL_FLASH_ERROR_SNECC        FLASH_FLAG_SNECCERR       /*!< ECC Single Correction Error           */
+#define HAL_FLASH_ERROR_DBECC        FLASH_FLAG_DBECCERR       /*!< ECC Double Detection Error            */
+#define HAL_FLASH_ERROR_CRCRD        FLASH_FLAG_CRCRDERR       /*!< CRC Read Error                        */
+
+#define HAL_FLASH_ERROR_WRP_BANK1    FLASH_FLAG_WRPERR_BANK1   /*!< Write Protection Error on Bank 1      */
+#define HAL_FLASH_ERROR_PGS_BANK1    FLASH_FLAG_PGSERR_BANK1   /*!< Program Sequence Error on Bank 1      */
+#define HAL_FLASH_ERROR_STRB_BANK1   FLASH_FLAG_STRBERR_BANK1  /*!< Strobe Error on Bank 1                */
+#define HAL_FLASH_ERROR_INC_BANK1    FLASH_FLAG_INCERR_BANK1   /*!< Inconsistency Error on Bank 1         */
+#if defined (FLASH_SR_OPERR)
+#define HAL_FLASH_ERROR_OPE_BANK1    FLASH_FLAG_OPERR_BANK1    /*!< Operation Error on Bank 1             */
+#endif /* FLASH_SR_OPERR */
+#define HAL_FLASH_ERROR_RDP_BANK1    FLASH_FLAG_RDPERR_BANK1   /*!< Read Protection Error on Bank 1       */
+#define HAL_FLASH_ERROR_RDS_BANK1    FLASH_FLAG_RDSERR_BANK1   /*!< Read Secured Error on Bank 1          */
+#define HAL_FLASH_ERROR_SNECC_BANK1  FLASH_FLAG_SNECCERR_BANK1 /*!< ECC Single Correction Error on Bank 1 */
+#define HAL_FLASH_ERROR_DBECC_BANK1  FLASH_FLAG_DBECCERR_BANK1 /*!< ECC Double Detection Error on Bank 1  */
+#define HAL_FLASH_ERROR_CRCRD_BANK1  FLASH_FLAG_CRCRDERR_BANK1 /*!< CRC Read Error on Bank1               */
+
+#define HAL_FLASH_ERROR_WRP_BANK2    FLASH_FLAG_WRPERR_BANK2    /*!< Write Protection Error on Bank 2      */
+#define HAL_FLASH_ERROR_PGS_BANK2    FLASH_FLAG_PGSERR_BANK2    /*!< Program Sequence Error on Bank 2      */
+#define HAL_FLASH_ERROR_STRB_BANK2   FLASH_FLAG_STRBERR_BANK2   /*!< Strobe Error on Bank 2                */
+#define HAL_FLASH_ERROR_INC_BANK2    FLASH_FLAG_INCERR_BANK2    /*!< Inconsistency Error on Bank 2         */
+#if defined (FLASH_SR_OPERR)
+#define HAL_FLASH_ERROR_OPE_BANK2    FLASH_FLAG_OPERR_BANK2     /*!< Operation Error on Bank 2             */
+#endif /* FLASH_SR_OPERR */
+#define HAL_FLASH_ERROR_RDP_BANK2    FLASH_FLAG_RDPERR_BANK2    /*!< Read Protection Error on Bank 2       */
+#define HAL_FLASH_ERROR_RDS_BANK2    FLASH_FLAG_RDSERR_BANK2    /*!< Read Secured Error on Bank 2          */
+#define HAL_FLASH_ERROR_SNECC_BANK2  FLASH_FLAG_SNECCERR_BANK2  /*!< ECC Single Correction Error on Bank 2 */
+#define HAL_FLASH_ERROR_DBECC_BANK2  FLASH_FLAG_DBECCERR_BANK2  /*!< ECC Double Detection Error on Bank 2  */
+#define HAL_FLASH_ERROR_CRCRD_BANK2  FLASH_FLAG_CRCRDERR_BANK2  /*!< CRC Read Error on Bank2               */
+
+#define HAL_FLASH_ERROR_OB_CHANGE    FLASH_OPTSR_OPTCHANGEERR   /*!< Option Byte Change Error              */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Type_Program FLASH Type Program
+  * @{
+  */
+#define FLASH_TYPEPROGRAM_FLASHWORD  0x01U        /*!< Program a flash word at a specified address */
+#if defined (FLASH_OPTCR_PG_OTP)
+#define FLASH_TYPEPROGRAM_OTPWORD    0x02U        /*!< Program an OTP word at a specified address  */
+#endif /* FLASH_OPTCR_PG_OTP */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Flag_definition FLASH Flag definition
+  * @brief Flag definition
+  * @{
+  */
+#define FLASH_FLAG_BSY                     FLASH_SR_BSY             /*!< FLASH Busy flag */
+#define FLASH_FLAG_WBNE                    FLASH_SR_WBNE            /*!< Write Buffer Not Empty flag */
+#define FLASH_FLAG_QW                      FLASH_SR_QW              /*!< Wait Queue on flag */
+#define FLASH_FLAG_CRC_BUSY                FLASH_SR_CRC_BUSY        /*!< CRC Busy flag */
+#define FLASH_FLAG_EOP                     FLASH_SR_EOP             /*!< End Of Program on flag */
+#define FLASH_FLAG_WRPERR                  FLASH_SR_WRPERR          /*!< Write Protection Error on flag */
+#define FLASH_FLAG_PGSERR                  FLASH_SR_PGSERR          /*!< Program Sequence Error on flag */
+#define FLASH_FLAG_STRBERR                 FLASH_SR_STRBERR         /*!< Strobe Error flag */
+#define FLASH_FLAG_INCERR                  FLASH_SR_INCERR          /*!< Inconsistency Error on flag */
+#if defined (FLASH_SR_OPERR)
+#define FLASH_FLAG_OPERR                   FLASH_SR_OPERR           /*!< Operation Error on flag */
+#endif /* FLASH_SR_OPERR */
+#define FLASH_FLAG_RDPERR                  FLASH_SR_RDPERR          /*!< Read Protection Error on flag */
+#define FLASH_FLAG_RDSERR                  FLASH_SR_RDSERR          /*!< Read Secured Error on flag */
+#define FLASH_FLAG_SNECCERR                FLASH_SR_SNECCERR        /*!< Single ECC Error Correction on flag */
+#define FLASH_FLAG_DBECCERR                FLASH_SR_DBECCERR        /*!< Double Detection ECC Error on flag */
+#define FLASH_FLAG_CRCEND                  FLASH_SR_CRCEND          /*!< CRC End of Calculation flag */
+#define FLASH_FLAG_CRCRDERR                FLASH_SR_CRCRDERR        /*!< CRC Read Error on bank flag */
+
+#define FLASH_FLAG_BSY_BANK1               FLASH_SR_BSY             /*!< FLASH Bank 1 Busy flag */
+#define FLASH_FLAG_WBNE_BANK1              FLASH_SR_WBNE            /*!< Write Buffer Not Empty on Bank 1 flag */
+#define FLASH_FLAG_QW_BANK1                FLASH_SR_QW              /*!< Wait Queue on Bank 1 flag */
+#define FLASH_FLAG_CRC_BUSY_BANK1          FLASH_SR_CRC_BUSY        /*!< CRC Busy on Bank 1 flag */
+#define FLASH_FLAG_EOP_BANK1               FLASH_SR_EOP             /*!< End Of Program on Bank 1 flag */
+#define FLASH_FLAG_WRPERR_BANK1            FLASH_SR_WRPERR          /*!< Write Protection Error on Bank 1 flag */
+#define FLASH_FLAG_PGSERR_BANK1            FLASH_SR_PGSERR          /*!< Program Sequence Error on Bank 1 flag */
+#define FLASH_FLAG_STRBERR_BANK1           FLASH_SR_STRBERR         /*!< Strobe Error on Bank 1 flag */
+#define FLASH_FLAG_INCERR_BANK1            FLASH_SR_INCERR          /*!< Inconsistency Error on Bank 1 flag */
+#if defined (FLASH_SR_OPERR)
+#define FLASH_FLAG_OPERR_BANK1             FLASH_SR_OPERR           /*!< Operation Error on Bank 1 flag */
+#endif /* FLASH_SR_OPERR */
+#define FLASH_FLAG_RDPERR_BANK1            FLASH_SR_RDPERR          /*!< Read Protection Error on Bank 1 flag */
+#define FLASH_FLAG_RDSERR_BANK1            FLASH_SR_RDSERR          /*!< Read Secured Error on Bank 1 flag */
+#define FLASH_FLAG_SNECCERR_BANK1          FLASH_SR_SNECCERR        /*!< Single ECC Error Correction on Bank 1 flag */
+#define FLASH_FLAG_DBECCERR_BANK1          FLASH_SR_DBECCERR        /*!< Double Detection ECC Error on Bank 1 flag */
+#define FLASH_FLAG_CRCEND_BANK1            FLASH_SR_CRCEND          /*!< CRC End of Calculation on Bank 1 flag */
+#define FLASH_FLAG_CRCRDERR_BANK1          FLASH_SR_CRCRDERR        /*!< CRC Read error on Bank 1 flag */
+
+#if defined (FLASH_SR_OPERR)
+#define FLASH_FLAG_ALL_ERRORS_BANK1       (FLASH_FLAG_WRPERR_BANK1   | FLASH_FLAG_PGSERR_BANK1   | \
+                                           FLASH_FLAG_STRBERR_BANK1  | FLASH_FLAG_INCERR_BANK1   | \
+                                           FLASH_FLAG_OPERR_BANK1    | FLASH_FLAG_RDPERR_BANK1   | \
+                                           FLASH_FLAG_RDSERR_BANK1   | FLASH_FLAG_SNECCERR_BANK1 | \
+                                           FLASH_FLAG_DBECCERR_BANK1 | FLASH_FLAG_CRCRDERR_BANK1) /*!< All Bank 1 error flags */
+#else
+#define FLASH_FLAG_ALL_ERRORS_BANK1       (FLASH_FLAG_WRPERR_BANK1   | FLASH_FLAG_PGSERR_BANK1   | \
+                                           FLASH_FLAG_STRBERR_BANK1  | FLASH_FLAG_INCERR_BANK1   | \
+                                           FLASH_FLAG_RDPERR_BANK1   | FLASH_FLAG_RDSERR_BANK1   | \
+                                           FLASH_FLAG_SNECCERR_BANK1 | FLASH_FLAG_DBECCERR_BANK1 | \
+                                           FLASH_FLAG_CRCRDERR_BANK1) /*!< All Bank 1 error flags */
+#endif /* FLASH_SR_OPERR */
+
+#define FLASH_FLAG_ALL_BANK1              (FLASH_FLAG_BSY_BANK1      | FLASH_FLAG_WBNE_BANK1     | \
+                                           FLASH_FLAG_QW_BANK1       | FLASH_FLAG_CRC_BUSY_BANK1 | \
+                                           FLASH_FLAG_EOP_BANK1      | FLASH_FLAG_CRCEND_BANK1   | \
+                                           FLASH_FLAG_ALL_ERRORS_BANK1) /*!< All Bank 1 flags */
+
+#define FLASH_FLAG_BSY_BANK2               (FLASH_SR_BSY      | 0x80000000U)        /*!< FLASH Bank 2 Busy flag */
+#define FLASH_FLAG_WBNE_BANK2              (FLASH_SR_WBNE     | 0x80000000U)        /*!< Write Buffer Not Empty on Bank 2 flag */
+#define FLASH_FLAG_QW_BANK2                (FLASH_SR_QW       | 0x80000000U)        /*!< Wait Queue on Bank 2 flag */
+#define FLASH_FLAG_CRC_BUSY_BANK2          (FLASH_SR_CRC_BUSY | 0x80000000U)        /*!< CRC Busy on Bank 2 flag */
+#define FLASH_FLAG_EOP_BANK2               (FLASH_SR_EOP      | 0x80000000U)        /*!< End Of Program on Bank 2 flag */
+#define FLASH_FLAG_WRPERR_BANK2            (FLASH_SR_WRPERR   | 0x80000000U)        /*!< Write Protection Error on Bank 2 flag */
+#define FLASH_FLAG_PGSERR_BANK2            (FLASH_SR_PGSERR   | 0x80000000U)        /*!< Program Sequence Error on Bank 2 flag */
+#define FLASH_FLAG_STRBERR_BANK2           (FLASH_SR_STRBERR  | 0x80000000U)        /*!< Strobe Error on Bank 2 flag */
+#define FLASH_FLAG_INCERR_BANK2            (FLASH_SR_INCERR   | 0x80000000U)        /*!< Inconsistency Error on Bank 2 flag */
+#if defined (FLASH_SR_OPERR)
+#define FLASH_FLAG_OPERR_BANK2             (FLASH_SR_OPERR    | 0x80000000U)        /*!< Operation Error on Bank 2 flag */
+#endif /* FLASH_SR_OPERR */
+#define FLASH_FLAG_RDPERR_BANK2            (FLASH_SR_RDPERR   | 0x80000000U)        /*!< Read Protection Error on Bank 2 flag */
+#define FLASH_FLAG_RDSERR_BANK2            (FLASH_SR_RDSERR   | 0x80000000U)        /*!< Read Secured Error on Bank 2 flag */
+#define FLASH_FLAG_SNECCERR_BANK2          (FLASH_SR_SNECCERR | 0x80000000U)        /*!< Single ECC Error Correction on Bank 2 flag */
+#define FLASH_FLAG_DBECCERR_BANK2          (FLASH_SR_DBECCERR | 0x80000000U)        /*!< Double Detection ECC Error on Bank 2 flag */
+#define FLASH_FLAG_CRCEND_BANK2            (FLASH_SR_CRCEND   | 0x80000000U)        /*!< CRC End of Calculation on Bank 2 flag */
+#define FLASH_FLAG_CRCRDERR_BANK2          (FLASH_SR_CRCRDERR | 0x80000000U)        /*!< CRC Read error on Bank 2 flag */
+
+#if defined (FLASH_SR_OPERR)
+#define FLASH_FLAG_ALL_ERRORS_BANK2       (FLASH_FLAG_WRPERR_BANK2   | FLASH_FLAG_PGSERR_BANK2   | \
+                                           FLASH_FLAG_STRBERR_BANK2  | FLASH_FLAG_INCERR_BANK2   | \
+                                           FLASH_FLAG_OPERR_BANK2    | FLASH_FLAG_RDPERR_BANK2   | \
+                                           FLASH_FLAG_RDSERR_BANK2   | FLASH_FLAG_SNECCERR_BANK2 | \
+                                           FLASH_FLAG_DBECCERR_BANK2 | FLASH_FLAG_CRCRDERR_BANK2) /*!< All Bank 2 error flags */
+#else
+#define FLASH_FLAG_ALL_ERRORS_BANK2       (FLASH_FLAG_WRPERR_BANK2   | FLASH_FLAG_PGSERR_BANK2   | \
+                                           FLASH_FLAG_STRBERR_BANK2  | FLASH_FLAG_INCERR_BANK2   | \
+                                           FLASH_FLAG_RDPERR_BANK2   | FLASH_FLAG_RDSERR_BANK2   | \
+                                           FLASH_FLAG_SNECCERR_BANK2 | FLASH_FLAG_DBECCERR_BANK2 | \
+                                           FLASH_FLAG_CRCRDERR_BANK2) /*!< All Bank 2 error flags */
+#endif /* FLASH_SR_OPERR */
+
+#define FLASH_FLAG_ALL_BANK2              (FLASH_FLAG_BSY_BANK2      | FLASH_FLAG_WBNE_BANK2     | \
+                                           FLASH_FLAG_QW_BANK2       | FLASH_FLAG_CRC_BUSY_BANK2 | \
+                                           FLASH_FLAG_EOP_BANK2      | FLASH_FLAG_CRCEND_BANK2   | \
+                                           FLASH_FLAG_ALL_ERRORS_BANK2) /*!< All Bank 2 flags */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition
+  * @brief FLASH Interrupt definition
+  * @{
+  */
+#define FLASH_IT_EOP_BANK1                  FLASH_CR_EOPIE       /*!< End of FLASH Bank 1 Operation Interrupt source */
+#define FLASH_IT_WRPERR_BANK1               FLASH_CR_WRPERRIE    /*!< Write Protection Error on Bank 1 Interrupt source */
+#define FLASH_IT_PGSERR_BANK1               FLASH_CR_PGSERRIE    /*!< Program Sequence Error on Bank 1 Interrupt source */
+#define FLASH_IT_STRBERR_BANK1              FLASH_CR_STRBERRIE   /*!< Strobe Error on Bank 1 Interrupt source */
+#define FLASH_IT_INCERR_BANK1               FLASH_CR_INCERRIE    /*!< Inconsistency Error on Bank 1 Interrupt source */
+#if defined (FLASH_CR_OPERRIE)
+#define FLASH_IT_OPERR_BANK1                FLASH_CR_OPERRIE     /*!< Operation Error on Bank 1 Interrupt source */
+#endif /* FLASH_CR_OPERRIE */
+#define FLASH_IT_RDPERR_BANK1               FLASH_CR_RDPERRIE    /*!< Read protection Error on Bank 1 Interrupt source */
+#define FLASH_IT_RDSERR_BANK1               FLASH_CR_RDSERRIE    /*!< Read Secured Error on Bank 1 Interrupt source */
+#define FLASH_IT_SNECCERR_BANK1             FLASH_CR_SNECCERRIE  /*!< Single ECC Error Correction on Bank 1 Interrupt source */
+#define FLASH_IT_DBECCERR_BANK1             FLASH_CR_DBECCERRIE  /*!< Double Detection ECC Error on Bank 1 Interrupt source */
+#define FLASH_IT_CRCEND_BANK1               FLASH_CR_CRCENDIE    /*!< CRC End on Bank 1 Interrupt source */
+#define FLASH_IT_CRCRDERR_BANK1             FLASH_CR_CRCRDERRIE  /*!< CRC Read error on Bank 1 Interrupt source */
+
+#if defined (FLASH_CR_OPERRIE)
+#define FLASH_IT_ALL_BANK1                 (FLASH_IT_EOP_BANK1       | FLASH_IT_WRPERR_BANK1    | \
+                                            FLASH_IT_PGSERR_BANK1    | FLASH_IT_STRBERR_BANK1   | \
+                                            FLASH_IT_INCERR_BANK1    | FLASH_IT_OPERR_BANK1     | \
+                                            FLASH_IT_RDPERR_BANK1    | FLASH_IT_RDSERR_BANK1    | \
+                                            FLASH_IT_SNECCERR_BANK1  | FLASH_IT_DBECCERR_BANK1  | \
+                                            FLASH_IT_CRCEND_BANK1    | FLASH_IT_CRCRDERR_BANK1) /*!< All Bank 1 Interrupt sources */
+#else
+#define FLASH_IT_ALL_BANK1                 (FLASH_IT_EOP_BANK1       | FLASH_IT_WRPERR_BANK1    | \
+                                            FLASH_IT_PGSERR_BANK1    | FLASH_IT_STRBERR_BANK1   | \
+                                            FLASH_IT_INCERR_BANK1    | FLASH_IT_RDPERR_BANK1    | \
+                                            FLASH_IT_RDSERR_BANK1    | FLASH_IT_SNECCERR_BANK1  | \
+                                            FLASH_IT_DBECCERR_BANK1  | FLASH_IT_CRCEND_BANK1    | \
+                                            FLASH_IT_CRCRDERR_BANK1) /*!< All Bank 1 Interrupt sources */
+#endif /* FLASH_CR_OPERRIE */
+
+#define FLASH_IT_EOP_BANK2                 (FLASH_CR_EOPIE      | 0x80000000U)  /*!< End of FLASH Bank 2 Operation Interrupt source */
+#define FLASH_IT_WRPERR_BANK2              (FLASH_CR_WRPERRIE   | 0x80000000U)  /*!< Write Protection Error on Bank 2 Interrupt source */
+#define FLASH_IT_PGSERR_BANK2              (FLASH_CR_PGSERRIE   | 0x80000000U)  /*!< Program Sequence Error on Bank 2 Interrupt source */
+#define FLASH_IT_STRBERR_BANK2             (FLASH_CR_STRBERRIE  | 0x80000000U)  /*!< Strobe Error on Bank 2 Interrupt source */
+#define FLASH_IT_INCERR_BANK2              (FLASH_CR_INCERRIE   | 0x80000000U)  /*!< Inconsistency Error on Bank 2 Interrupt source */
+#if defined (FLASH_CR_OPERRIE)
+#define FLASH_IT_OPERR_BANK2               (FLASH_CR_OPERRIE    | 0x80000000U)  /*!< Operation Error on Bank 2 Interrupt source */
+#endif /* FLASH_CR_OPERRIE */
+#define FLASH_IT_RDPERR_BANK2              (FLASH_CR_RDPERRIE   | 0x80000000U)  /*!< Read protection Error on Bank 2 Interrupt source */
+#define FLASH_IT_RDSERR_BANK2              (FLASH_CR_RDSERRIE   | 0x80000000U)  /*!< Read Secured Error on Bank 2 Interrupt source */
+#define FLASH_IT_SNECCERR_BANK2            (FLASH_CR_SNECCERRIE | 0x80000000U)  /*!< Single ECC Error Correction on Bank 2 Interrupt source */
+#define FLASH_IT_DBECCERR_BANK2            (FLASH_CR_DBECCERRIE | 0x80000000U)  /*!< Double Detection ECC Error on Bank 2 Interrupt source */
+#define FLASH_IT_CRCEND_BANK2              (FLASH_CR_CRCENDIE   | 0x80000000U)  /*!< CRC End on Bank 2 Interrupt source */
+#define FLASH_IT_CRCRDERR_BANK2            (FLASH_CR_CRCRDERRIE | 0x80000000U)  /*!< CRC Read Error on Bank 2 Interrupt source */
+
+#if defined (FLASH_CR_OPERRIE)
+#define FLASH_IT_ALL_BANK2                 (FLASH_IT_EOP_BANK2       | FLASH_IT_WRPERR_BANK2    | \
+                                            FLASH_IT_PGSERR_BANK2    | FLASH_IT_STRBERR_BANK2   | \
+                                            FLASH_IT_INCERR_BANK2    | FLASH_IT_OPERR_BANK2     | \
+                                            FLASH_IT_RDPERR_BANK2    | FLASH_IT_RDSERR_BANK2    | \
+                                            FLASH_IT_SNECCERR_BANK2  | FLASH_IT_DBECCERR_BANK2  | \
+                                            FLASH_IT_CRCEND_BANK2    | FLASH_IT_CRCRDERR_BANK2) /*!< All Bank 2 Interrupt sources */
+#else
+#define FLASH_IT_ALL_BANK2                 (FLASH_IT_EOP_BANK2       | FLASH_IT_WRPERR_BANK2    | \
+                                            FLASH_IT_PGSERR_BANK2    | FLASH_IT_STRBERR_BANK2   | \
+                                            FLASH_IT_INCERR_BANK2    | FLASH_IT_RDPERR_BANK2    | \
+                                            FLASH_IT_RDSERR_BANK2    | FLASH_IT_SNECCERR_BANK2  | \
+                                            FLASH_IT_DBECCERR_BANK2  | FLASH_IT_CRCEND_BANK2    | \
+                                            FLASH_IT_CRCRDERR_BANK2) /*!< All Bank 2 Interrupt sources */
+#endif /* FLASH_CR_OPERRIE */
+/**
+  * @}
+  */
+
+#if defined (FLASH_CR_PSIZE)
+/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism
+  * @{
+  */
+#define FLASH_PSIZE_BYTE           0x00000000U       /*!< Flash program/erase by 8 bits  */
+#define FLASH_PSIZE_HALF_WORD      FLASH_CR_PSIZE_0  /*!< Flash program/erase by 16 bits */
+#define FLASH_PSIZE_WORD           FLASH_CR_PSIZE_1  /*!< Flash program/erase by 32 bits */
+#define FLASH_PSIZE_DOUBLE_WORD    FLASH_CR_PSIZE    /*!< Flash program/erase by 64 bits */
+/**
+  * @}
+  */
+#endif /* FLASH_CR_PSIZE */
+
+
+/** @defgroup FLASH_Keys FLASH Keys
+  * @{
+  */
+#define FLASH_KEY1                 0x45670123U
+#define FLASH_KEY2                 0xCDEF89ABU
+#define FLASH_OPT_KEY1             0x08192A3BU
+#define FLASH_OPT_KEY2             0x4C5D6E7FU
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Sectors FLASH Sectors
+  * @{
+  */
+#define FLASH_SECTOR_0             0U       /*!< Sector Number 0   */
+#define FLASH_SECTOR_1             1U       /*!< Sector Number 1   */
+#define FLASH_SECTOR_2             2U       /*!< Sector Number 2   */
+#define FLASH_SECTOR_3             3U       /*!< Sector Number 3   */
+#define FLASH_SECTOR_4             4U       /*!< Sector Number 4   */
+#define FLASH_SECTOR_5             5U       /*!< Sector Number 5   */
+#define FLASH_SECTOR_6             6U       /*!< Sector Number 6   */
+#define FLASH_SECTOR_7             7U       /*!< Sector Number 7   */
+#if (FLASH_SECTOR_TOTAL == 128)
+#define FLASH_SECTOR_8             8U       /*!< Sector Number 8   */
+#define FLASH_SECTOR_9             9U       /*!< Sector Number 9   */
+#define FLASH_SECTOR_10            10U      /*!< Sector Number 10  */
+#define FLASH_SECTOR_11            11U      /*!< Sector Number 11  */
+#define FLASH_SECTOR_12            12U      /*!< Sector Number 12  */
+#define FLASH_SECTOR_13            13U      /*!< Sector Number 13  */
+#define FLASH_SECTOR_14            14U      /*!< Sector Number 14  */
+#define FLASH_SECTOR_15            15U      /*!< Sector Number 15  */
+#define FLASH_SECTOR_16            16U      /*!< Sector Number 16  */
+#define FLASH_SECTOR_17            17U      /*!< Sector Number 17  */
+#define FLASH_SECTOR_18            18U      /*!< Sector Number 18  */
+#define FLASH_SECTOR_19            19U      /*!< Sector Number 19  */
+#define FLASH_SECTOR_20            20U      /*!< Sector Number 20  */
+#define FLASH_SECTOR_21            21U      /*!< Sector Number 21  */
+#define FLASH_SECTOR_22            22U      /*!< Sector Number 22  */
+#define FLASH_SECTOR_23            23U      /*!< Sector Number 23  */
+#define FLASH_SECTOR_24            24U      /*!< Sector Number 24  */
+#define FLASH_SECTOR_25            25U      /*!< Sector Number 25  */
+#define FLASH_SECTOR_26            26U      /*!< Sector Number 26  */
+#define FLASH_SECTOR_27            27U      /*!< Sector Number 27  */
+#define FLASH_SECTOR_28            28U      /*!< Sector Number 28  */
+#define FLASH_SECTOR_29            29U      /*!< Sector Number 29  */
+#define FLASH_SECTOR_30            30U      /*!< Sector Number 30  */
+#define FLASH_SECTOR_31            31U      /*!< Sector Number 31  */
+#define FLASH_SECTOR_32            32U      /*!< Sector Number 32  */
+#define FLASH_SECTOR_33            33U      /*!< Sector Number 33  */
+#define FLASH_SECTOR_34            34U      /*!< Sector Number 34  */
+#define FLASH_SECTOR_35            35U      /*!< Sector Number 35  */
+#define FLASH_SECTOR_36            36U      /*!< Sector Number 36  */
+#define FLASH_SECTOR_37            37U      /*!< Sector Number 37  */
+#define FLASH_SECTOR_38            38U      /*!< Sector Number 38  */
+#define FLASH_SECTOR_39            39U      /*!< Sector Number 39  */
+#define FLASH_SECTOR_40            40U      /*!< Sector Number 40  */
+#define FLASH_SECTOR_41            41U      /*!< Sector Number 41  */
+#define FLASH_SECTOR_42            42U      /*!< Sector Number 42  */
+#define FLASH_SECTOR_43            43U      /*!< Sector Number 43  */
+#define FLASH_SECTOR_44            44U      /*!< Sector Number 44  */
+#define FLASH_SECTOR_45            45U      /*!< Sector Number 45  */
+#define FLASH_SECTOR_46            46U      /*!< Sector Number 46  */
+#define FLASH_SECTOR_47            47U      /*!< Sector Number 47  */
+#define FLASH_SECTOR_48            48U      /*!< Sector Number 48  */
+#define FLASH_SECTOR_49            49U      /*!< Sector Number 49  */
+#define FLASH_SECTOR_50            50U      /*!< Sector Number 50  */
+#define FLASH_SECTOR_51            51U      /*!< Sector Number 51  */
+#define FLASH_SECTOR_52            52U      /*!< Sector Number 52  */
+#define FLASH_SECTOR_53            53U      /*!< Sector Number 53  */
+#define FLASH_SECTOR_54            54U      /*!< Sector Number 54  */
+#define FLASH_SECTOR_55            55U      /*!< Sector Number 55  */
+#define FLASH_SECTOR_56            56U      /*!< Sector Number 56  */
+#define FLASH_SECTOR_57            57U      /*!< Sector Number 57  */
+#define FLASH_SECTOR_58            58U      /*!< Sector Number 58  */
+#define FLASH_SECTOR_59            59U      /*!< Sector Number 59  */
+#define FLASH_SECTOR_60            60U      /*!< Sector Number 60  */
+#define FLASH_SECTOR_61            61U      /*!< Sector Number 61  */
+#define FLASH_SECTOR_62            62U      /*!< Sector Number 62  */
+#define FLASH_SECTOR_63            63U      /*!< Sector Number 63  */
+#define FLASH_SECTOR_64            64U      /*!< Sector Number 64  */
+#define FLASH_SECTOR_65            65U      /*!< Sector Number 65  */
+#define FLASH_SECTOR_66            66U      /*!< Sector Number 66  */
+#define FLASH_SECTOR_67            67U      /*!< Sector Number 67  */
+#define FLASH_SECTOR_68            68U      /*!< Sector Number 68  */
+#define FLASH_SECTOR_69            69U      /*!< Sector Number 69  */
+#define FLASH_SECTOR_70            70U      /*!< Sector Number 70  */
+#define FLASH_SECTOR_71            71U      /*!< Sector Number 71  */
+#define FLASH_SECTOR_72            72U      /*!< Sector Number 72  */
+#define FLASH_SECTOR_73            73U      /*!< Sector Number 73  */
+#define FLASH_SECTOR_74            74U      /*!< Sector Number 74  */
+#define FLASH_SECTOR_75            75U      /*!< Sector Number 75  */
+#define FLASH_SECTOR_76            76U      /*!< Sector Number 76  */
+#define FLASH_SECTOR_77            77U      /*!< Sector Number 77  */
+#define FLASH_SECTOR_78            78U      /*!< Sector Number 78  */
+#define FLASH_SECTOR_79            79U      /*!< Sector Number 79  */
+#define FLASH_SECTOR_80            80U      /*!< Sector Number 80  */
+#define FLASH_SECTOR_81            81U      /*!< Sector Number 81  */
+#define FLASH_SECTOR_82            82U      /*!< Sector Number 82  */
+#define FLASH_SECTOR_83            83U      /*!< Sector Number 83  */
+#define FLASH_SECTOR_84            84U      /*!< Sector Number 84  */
+#define FLASH_SECTOR_85            85U      /*!< Sector Number 85  */
+#define FLASH_SECTOR_86            86U      /*!< Sector Number 86  */
+#define FLASH_SECTOR_87            87U      /*!< Sector Number 87  */
+#define FLASH_SECTOR_88            88U      /*!< Sector Number 88  */
+#define FLASH_SECTOR_89            89U      /*!< Sector Number 89  */
+#define FLASH_SECTOR_90            90U      /*!< Sector Number 90  */
+#define FLASH_SECTOR_91            91U      /*!< Sector Number 91  */
+#define FLASH_SECTOR_92            92U      /*!< Sector Number 92  */
+#define FLASH_SECTOR_93            93U      /*!< Sector Number 93  */
+#define FLASH_SECTOR_94            94U      /*!< Sector Number 94  */
+#define FLASH_SECTOR_95            95U      /*!< Sector Number 95  */
+#define FLASH_SECTOR_96            96U      /*!< Sector Number 96  */
+#define FLASH_SECTOR_97            97U      /*!< Sector Number 97  */
+#define FLASH_SECTOR_98            98U      /*!< Sector Number 98  */
+#define FLASH_SECTOR_99            99U      /*!< Sector Number 99  */
+#define FLASH_SECTOR_100           100U     /*!< Sector Number 100 */
+#define FLASH_SECTOR_101           101U     /*!< Sector Number 101 */
+#define FLASH_SECTOR_102           102U     /*!< Sector Number 102 */
+#define FLASH_SECTOR_103           103U     /*!< Sector Number 103 */
+#define FLASH_SECTOR_104           104U     /*!< Sector Number 104 */
+#define FLASH_SECTOR_105           105U     /*!< Sector Number 105 */
+#define FLASH_SECTOR_106           106U     /*!< Sector Number 106 */
+#define FLASH_SECTOR_107           107U     /*!< Sector Number 107 */
+#define FLASH_SECTOR_108           108U     /*!< Sector Number 108 */
+#define FLASH_SECTOR_109           109U     /*!< Sector Number 109 */
+#define FLASH_SECTOR_110           110U     /*!< Sector Number 110 */
+#define FLASH_SECTOR_111           111U     /*!< Sector Number 111 */
+#define FLASH_SECTOR_112           112U     /*!< Sector Number 112 */
+#define FLASH_SECTOR_113           113U     /*!< Sector Number 113 */
+#define FLASH_SECTOR_114           114U     /*!< Sector Number 114 */
+#define FLASH_SECTOR_115           115U     /*!< Sector Number 115 */
+#define FLASH_SECTOR_116           116U     /*!< Sector Number 116 */
+#define FLASH_SECTOR_117           117U     /*!< Sector Number 117 */
+#define FLASH_SECTOR_118           118U     /*!< Sector Number 118 */
+#define FLASH_SECTOR_119           119U     /*!< Sector Number 119 */
+#define FLASH_SECTOR_120           120U     /*!< Sector Number 120 */
+#define FLASH_SECTOR_121           121U     /*!< Sector Number 121 */
+#define FLASH_SECTOR_122           122U     /*!< Sector Number 122 */
+#define FLASH_SECTOR_123           123U     /*!< Sector Number 123 */
+#define FLASH_SECTOR_124           124U     /*!< Sector Number 124 */
+#define FLASH_SECTOR_125           125U     /*!< Sector Number 125 */
+#define FLASH_SECTOR_126           126U     /*!< Sector Number 126 */
+#define FLASH_SECTOR_127           127U     /*!< Sector Number 127 */
+#endif /* FLASH_SECTOR_TOTAL == 128 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
+  * @{
+  */
+/**
+  * @brief  Set the FLASH Latency.
+  * @param  __LATENCY__: FLASH Latency
+  *         The value of this parameter depend on device used within the same series
+  * @retval none
+  */
+#define __HAL_FLASH_SET_LATENCY(__LATENCY__) \
+                  MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__))
+
+/**
+  * @brief  Get the FLASH Latency.
+  * @retval FLASH Latency
+  *          The value of this parameter depend on device used within the same series
+  */
+#define __HAL_FLASH_GET_LATENCY()     (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
+
+/**
+  * @brief  Enable the specified FLASH interrupt.
+  * @param  __INTERRUPT__ : FLASH interrupt
+  *   In case of Bank 1 This parameter can be any combination of the following values:
+  *     @arg FLASH_IT_EOP_BANK1       : End of FLASH Bank 1 Operation Interrupt source
+  *     @arg FLASH_IT_WRPERR_BANK1    : Write Protection Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_PGSERR_BANK1    : Program Sequence Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_STRBERR_BANK1   : Strobe Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_INCERR_BANK1    : Inconsistency Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_OPERR_BANK1     : Operation Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_RDPERR_BANK1    : Read protection Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_RDSERR_BANK1    : Read secure Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_SNECCERR_BANK1  : Single ECC Error Correction on Bank 1 Interrupt source
+  *     @arg FLASH_IT_DBECCERR_BANK1  : Double Detection ECC Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_CRCEND_BANK1    : CRC End on Bank 1 Interrupt source
+  *     @arg FLASH_IT_CRCRDERR_BANK1  : CRC Read error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_ALL_BANK1       : All Bank 1 Interrupt sources
+  *
+  *   In case of Bank 2, this parameter can be any combination of the following values:
+  *     @arg FLASH_IT_EOP_BANK2       : End of FLASH Bank 2 Operation Interrupt source
+  *     @arg FLASH_IT_WRPERR_BANK2    : Write Protection Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_PGSERR_BANK2    : Program Sequence Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_STRBERR_BANK2   : Strobe Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_INCERR_BANK2    : Inconsistency Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_OPERR_BANK2     : Operation Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_RDPERR_BANK2    : Read protection Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_RDSERR_BANK2    : Read secure Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_SNECCERR_BANK2  : Single ECC Error Correction on Bank 2 Interrupt source
+  *     @arg FLASH_IT_DBECCERR_BANK2  : Double Detection ECC Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_CRCEND_BANK2    : CRC End on Bank 2 Interrupt source
+  *     @arg FLASH_IT_CRCRDERR_BANK2  : CRC Read error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_ALL_BANK2       : All Bank 2 Interrupt sources
+  * @retval none
+  */
+
+#define __HAL_FLASH_ENABLE_IT_BANK1(__INTERRUPT__)      (FLASH->CR1 |= (__INTERRUPT__))
+
+#define __HAL_FLASH_ENABLE_IT_BANK2(__INTERRUPT__)      (FLASH->CR2 |= ((__INTERRUPT__) & 0x7FFFFFFFU))
+
+#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)    (IS_FLASH_IT_BANK1(__INTERRUPT__) ? \
+                                                 __HAL_FLASH_ENABLE_IT_BANK1(__INTERRUPT__) : \
+                                                 __HAL_FLASH_ENABLE_IT_BANK2(__INTERRUPT__))
+
+
+/**
+  * @brief  Disable the specified FLASH interrupt.
+  * @param  __INTERRUPT__ : FLASH interrupt
+  *   In case of Bank 1 This parameter can be any combination of the following values:
+  *     @arg FLASH_IT_EOP_BANK1       : End of FLASH Bank 1 Operation Interrupt source
+  *     @arg FLASH_IT_WRPERR_BANK1    : Write Protection Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_PGSERR_BANK1    : Program Sequence Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_STRBERR_BANK1   : Strobe Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_INCERR_BANK1    : Inconsistency Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_OPERR_BANK1     : Operation Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_RDPERR_BANK1    : Read protection Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_RDSERR_BANK1    : Read secure Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_SNECCERR_BANK1  : Single ECC Error Correction on Bank 1 Interrupt source
+  *     @arg FLASH_IT_DBECCERR_BANK1  : Double Detection ECC Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_CRCEND_BANK1    : CRC End on Bank 1 Interrupt source
+  *     @arg FLASH_IT_CRCRDERR_BANK1  : CRC Read error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_ALL_BANK1       : All Bank 1 Interrupt sources
+  *
+  *   In case of Bank 2, this parameter can be any combination of the following values:
+  *     @arg FLASH_IT_EOP_BANK2       : End of FLASH Bank 2 Operation Interrupt source
+  *     @arg FLASH_IT_WRPERR_BANK2    : Write Protection Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_PGSERR_BANK2    : Program Sequence Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_STRBERR_BANK2   : Strobe Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_INCERR_BANK2    : Inconsistency Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_OPERR_BANK2     : Operation Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_RDPERR_BANK2    : Read protection Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_RDSERR_BANK2    : Read secure Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_SNECCERR_BANK2  : Single ECC Error Correction on Bank 2 Interrupt source
+  *     @arg FLASH_IT_DBECCERR_BANK2  : Double Detection ECC Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_CRCEND_BANK2    : CRC End on Bank 2 Interrupt source
+  *     @arg FLASH_IT_CRCRDERR_BANK2  : CRC Read error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_ALL_BANK2       : All Bank 2 Interrupt sources
+  * @retval none
+  */
+
+#define __HAL_FLASH_DISABLE_IT_BANK1(__INTERRUPT__)  (FLASH->CR1 &= ~(uint32_t)(__INTERRUPT__))
+
+#define __HAL_FLASH_DISABLE_IT_BANK2(__INTERRUPT__)  (FLASH->CR2 &= ~(uint32_t)((__INTERRUPT__) & 0x7FFFFFFFU))
+
+#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)  (IS_FLASH_IT_BANK1(__INTERRUPT__) ? \
+                                                __HAL_FLASH_DISABLE_IT_BANK1(__INTERRUPT__) : \
+                                                __HAL_FLASH_DISABLE_IT_BANK2(__INTERRUPT__))
+
+
+/**
+  * @brief  Checks whether the specified FLASH flag is set or not.
+  * @param  __FLAG__: specifies the FLASH flag to check.
+  *   In case of Bank 1 This parameter can be one of the following values :
+  *     @arg FLASH_FLAG_BSY_BANK1      : FLASH Bank 1 Busy flag
+  *     @arg FLASH_FLAG_WBNE_BANK1     : Write Buffer Not Empty on Bank 1 flag
+  *     @arg FLASH_FLAG_QW_BANK1       : Wait Queue on Bank 1 flag
+  *     @arg FLASH_FLAG_CRC_BUSY_BANK1 : CRC module is working on Bank 1 flag
+  *     @arg FLASH_FLAG_EOP_BANK1      : End Of Program on Bank 1 flag
+  *     @arg FLASH_FLAG_WRPERR_BANK1   : Write Protection Error on Bank 1 flag
+  *     @arg FLASH_FLAG_PGSERR_BANK1   : Program Sequence Error on Bank 1 flag
+  *     @arg FLASH_FLAG_STRBER_BANK1   : Program Alignment Error on Bank 1 flag
+  *     @arg FLASH_FLAG_INCERR_BANK1   : Inconsistency Error on Bank 1 flag
+  *     @arg FLASH_FLAG_OPERR_BANK1    : Operation Error on Bank 1 flag
+  *     @arg FLASH_FLAG_RDPERR_BANK1   : Read Protection Error on Bank 1 flag
+  *     @arg FLASH_FLAG_RDSERR_BANK1   : Read secure  Error on Bank 1 flag
+  *     @arg FLASH_FLAG_SNECCE_BANK1   : Single ECC Error Correction on Bank 1 flag
+  *     @arg FLASH_FLAG_DBECCE_BANK1   : Double Detection ECC Error on Bank 1 flag
+  *     @arg FLASH_FLAG_CRCEND_BANK1   : CRC End on Bank 1 flag
+  *     @arg FLASH_FLAG_CRCRDERR_BANK1 : CRC Read error on Bank 1 flag
+  *
+  *   In case of Bank 2 This parameter can be one of the following values :
+  *     @arg FLASH_FLAG_BSY_BANK2      : FLASH Bank 2 Busy flag
+  *     @arg FLASH_FLAG_WBNE_BANK2     : Write Buffer Not Empty on Bank 2 flag
+  *     @arg FLASH_FLAG_QW_BANK2       : Wait Queue on Bank 2 flag
+  *     @arg FLASH_FLAG_CRC_BUSY_BANK2 : CRC module is working on Bank 2 flag
+  *     @arg FLASH_FLAG_EOP_BANK2      : End Of Program on Bank 2 flag
+  *     @arg FLASH_FLAG_WRPERR_BANK2   : Write Protection Error on Bank 2 flag
+  *     @arg FLASH_FLAG_PGSERR_BANK2   : Program Sequence Error on Bank 2 flag
+  *     @arg FLASH_FLAG_STRBER_BANK2   : Program Alignment Error on Bank 2 flag
+  *     @arg FLASH_FLAG_INCERR_BANK2   : Inconsistency Error on Bank 2 flag
+  *     @arg FLASH_FLAG_OPERR_BANK2    : Operation Error on Bank 2 flag
+  *     @arg FLASH_FLAG_RDPERR_BANK2   : Read Protection Error on Bank 2 flag
+  *     @arg FLASH_FLAG_RDSERR_BANK2   : Read secure  Error on Bank 2 flag
+  *     @arg FLASH_FLAG_SNECCE_BANK2   : Single ECC Error Correction on Bank 2 flag
+  *     @arg FLASH_FLAG_DBECCE_BANK2   : Double Detection ECC Error on Bank 2 flag
+  *     @arg FLASH_FLAG_CRCEND_BANK2   : CRC End on Bank 2 flag
+  *     @arg FLASH_FLAG_CRCRDERR_BANK2 : CRC Read error on Bank 2 flag
+  * @retval The new state of FLASH_FLAG (SET or RESET).
+  */
+#define __HAL_FLASH_GET_FLAG_BANK1(__FLAG__)     (READ_BIT(FLASH->SR1, (__FLAG__)) == (__FLAG__))
+
+#define __HAL_FLASH_GET_FLAG_BANK2(__FLAG__)     (READ_BIT(FLASH->SR2, ((__FLAG__) & 0x7FFFFFFFU)) == (((__FLAG__) & 0x7FFFFFFFU)))
+
+#define __HAL_FLASH_GET_FLAG(__FLAG__)           (IS_FLASH_FLAG_BANK1(__FLAG__) ?  __HAL_FLASH_GET_FLAG_BANK1(__FLAG__) : \
+                                                  __HAL_FLASH_GET_FLAG_BANK2(__FLAG__))
+
+
+/**
+  * @brief  Clear the specified FLASH flag.
+  * @param  __FLAG__: specifies the FLASH flags to clear.
+  *    In case of Bank 1, this parameter can be any combination of the following values:
+  *     @arg FLASH_FLAG_EOP_BANK1        : End Of Program on Bank 1 flag
+  *     @arg FLASH_FLAG_WRPERR_BANK1     : Write Protection Error on Bank 1 flag
+  *     @arg FLASH_FLAG_PGSERR_BANK1     : Program Sequence Error on Bank 1 flag
+  *     @arg FLASH_FLAG_STRBER_BANK1     : Program Alignment Error on Bank 1 flag
+  *     @arg FLASH_FLAG_INCERR_BANK1     : Inconsistency Error on Bank 1 flag
+  *     @arg FLASH_FLAG_OPERR_BANK1      : Operation Error on Bank 1 flag
+  *     @arg FLASH_FLAG_RDPERR_BANK1     : Read Protection Error on Bank 1 flag
+  *     @arg FLASH_FLAG_RDSERR_BANK1     : Read secure  Error on Bank 1 flag
+  *     @arg FLASH_FLAG_SNECCE_BANK1     : Single ECC Error Correction on Bank 1 flag
+  *     @arg FLASH_FLAG_DBECCE_BANK1     : Double Detection ECC Error on Bank 1 flag
+  *     @arg FLASH_FLAG_CRCEND_BANK1     : CRC End on Bank 1 flag
+  *     @arg FLASH_FLAG_CRCRDERR_BANK1   : CRC Read error on Bank 1 flag
+  *     @arg FLASH_FLAG_ALL_ERRORS_BANK1 : All Bank 1 error flags
+  *     @arg FLASH_FLAG_ALL_BANK1        : All Bank 1 flags
+  *
+  *   In case of Bank 2, this parameter can be any combination of the following values :
+  *     @arg FLASH_FLAG_EOP_BANK2        : End Of Program on Bank 2 flag
+  *     @arg FLASH_FLAG_WRPERR_BANK2     : Write Protection Error on Bank 2 flag
+  *     @arg FLASH_FLAG_PGSERR_BANK2     : Program Sequence Error on Bank 2 flag
+  *     @arg FLASH_FLAG_STRBER_BANK2     : Program Alignment Error on Bank 2 flag
+  *     @arg FLASH_FLAG_INCERR_BANK2     : Inconsistency Error on Bank 2 flag
+  *     @arg FLASH_FLAG_OPERR_BANK2      : Operation Error on Bank 2 flag
+  *     @arg FLASH_FLAG_RDPERR_BANK2     : Read Protection Error on Bank 2 flag
+  *     @arg FLASH_FLAG_RDSERR_BANK2     : Read secure  Error on Bank 2 flag
+  *     @arg FLASH_FLAG_SNECCE_BANK2     : Single ECC Error Correction on Bank 2 flag
+  *     @arg FLASH_FLAG_DBECCE_BANK2     : Double Detection ECC Error on Bank 2 flag
+  *     @arg FLASH_FLAG_CRCEND_BANK2     : CRC End on Bank 2 flag
+  *     @arg FLASH_FLAG_CRCRDERR_BANK2   : CRC Read error on Bank 2 flag
+  *     @arg FLASH_FLAG_ALL_ERRORS_BANK2 : All Bank 2 error flags
+  *     @arg FLASH_FLAG_ALL_BANK2        : All Bank 2 flags
+  * @retval none
+  */
+
+#define __HAL_FLASH_CLEAR_FLAG_BANK1(__FLAG__)    WRITE_REG(FLASH->CCR1, (__FLAG__))
+
+#define __HAL_FLASH_CLEAR_FLAG_BANK2(__FLAG__)    WRITE_REG(FLASH->CCR2, ((__FLAG__) & 0x7FFFFFFFU))
+
+#define __HAL_FLASH_CLEAR_FLAG(__FLAG__)         (IS_FLASH_FLAG_BANK1(__FLAG__) ?  __HAL_FLASH_CLEAR_FLAG_BANK1(__FLAG__) : \
+                                                   __HAL_FLASH_CLEAR_FLAG_BANK2(__FLAG__))
+
+/**
+  * @}
+  */
+
+/* Include FLASH HAL Extension module */
+#include "stm32h7xx_hal_flash_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASH_Exported_Functions
+  * @{
+  */
+/** @addtogroup FLASH_Exported_Functions_Group1
+  * @{
+  */
+/* Program operation functions  ***********************************************/
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress);
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress);
+/* FLASH IRQ handler method */
+void HAL_FLASH_IRQHandler(void);
+/* Callbacks in non blocking modes */
+void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
+void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
+/**
+  * @}
+  */
+
+/** @addtogroup FLASH_Exported_Functions_Group2
+  * @{
+  */
+/* Peripheral Control functions  **********************************************/
+HAL_StatusTypeDef HAL_FLASH_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_Lock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
+/* Option bytes control */
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
+/**
+  * @}
+  */
+
+/** @addtogroup FLASH_Exported_Functions_Group3
+  * @{
+  */
+/* Peripheral State functions  ************************************************/
+uint32_t HAL_FLASH_GetError(void);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup FLASH_Private_Variables FLASH Private Variables
+  * @{
+  */
+extern FLASH_ProcessTypeDef pFlash;
+/**
+  * @}
+  */
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup FLASH_Private_Constants FLASH Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FLASH_Private_Macros FLASH Private Macros
+  * @{
+  */
+
+#if defined (FLASH_OPTCR_PG_OTP)
+#define IS_FLASH_TYPEPROGRAM(VALUE)      (((VALUE) == FLASH_TYPEPROGRAM_FLASHWORD) || \
+                                          ((VALUE) == FLASH_TYPEPROGRAM_OTPWORD))
+#else
+#define IS_FLASH_TYPEPROGRAM(VALUE)      ((VALUE) == FLASH_TYPEPROGRAM_FLASHWORD)
+#endif /* FLASH_OPTCR_PG_OTP */
+
+#define IS_FLASH_IT_BANK1(IT)            (((IT) & FLASH_IT_ALL_BANK1) == (IT))
+
+#define IS_FLASH_IT_BANK2(IT)            (((IT) & FLASH_IT_ALL_BANK2) == (IT))
+
+#define IS_FLASH_FLAG_BANK1(FLAG)        (((FLAG) & FLASH_FLAG_ALL_BANK1) == (FLAG))
+
+#define IS_FLASH_FLAG_BANK2(FLAG)        (((FLAG) & FLASH_FLAG_ALL_BANK2) == (FLAG))
+
+#define IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) (((ADDRESS) >= FLASH_BANK1_BASE) && ((ADDRESS) < FLASH_BANK2_BASE))
+#define IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS) (((ADDRESS) >= FLASH_BANK2_BASE ) && ((ADDRESS) <= FLASH_END))
+
+#if defined (FLASH_OPTCR_PG_OTP)
+#define IS_FLASH_PROGRAM_ADDRESS_OTP(ADDRESS)   (((ADDRESS) >= 0x08FFF000U) && ((ADDRESS) <= 0x08FFF3FFU))
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS)       (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || \
+                                                 IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS) || \
+                                                 IS_FLASH_PROGRAM_ADDRESS_OTP(ADDRESS))
+#else
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS)       (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || \
+                                                 IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS))
+#endif /* FLASH_OPTCR_PG_OTP */
+
+#define IS_BOOT_ADDRESS(ADDRESS)           ((ADDRESS) <= (0x3FFF0000U))
+
+#define IS_FLASH_BANK(BANK)                (((BANK) == FLASH_BANK_1)  || \
+                                            ((BANK) == FLASH_BANK_2)  || \
+                                            ((BANK) == FLASH_BANK_BOTH))
+
+#define IS_FLASH_BANK_EXCLUSIVE(BANK)      (((BANK) == FLASH_BANK_1)  || \
+                                            ((BANK) == FLASH_BANK_2))
+
+
+/**
+  * @}
+  */
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup FLASH_Private_Functions FLASH Private functions
+  * @{
+  */
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout, uint32_t Bank);
+HAL_StatusTypeDef FLASH_OB_WaitForLastOperation(uint32_t Timeout);
+HAL_StatusTypeDef FLASH_CRC_WaitForLastOperation(uint32_t Timeout, uint32_t Bank);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_FLASH_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h
new file mode 100644
index 00000000..834c5d23
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h
@@ -0,0 +1,910 @@
+/**
+  ******************************************************************************
+  * @file    stm32H7xx_hal_flash_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of FLASH HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_FLASH_EX_H
+#define STM32H7xx_HAL_FLASH_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FLASHEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Types FLASH Exported Types
+  * @{
+  */
+
+/**
+  * @brief  FLASH Erase structure definition
+  */
+typedef struct
+{
+  uint32_t TypeErase;   /*!< Mass erase or sector Erase.
+                             This parameter can be a value of @ref FLASHEx_Type_Erase */
+
+  uint32_t Banks;       /*!< Select banks to erase when Mass erase is enabled.
+                             This parameter must be a value of @ref FLASHEx_Banks */
+
+  uint32_t Sector;      /*!< Initial FLASH sector to erase when Mass erase is disabled
+                             This parameter must be a value of @ref FLASH_Sectors */
+
+  uint32_t NbSectors;   /*!< Number of sectors to be erased.
+                             This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
+
+  uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism
+                             This parameter must be a value of @ref FLASHEx_Voltage_Range */
+
+} FLASH_EraseInitTypeDef;
+
+
+/**
+  * @brief  FLASH Option Bytes Program structure definition
+  */
+typedef struct
+{
+  uint32_t OptionType;     /*!< Option byte to be configured.
+                                This parameter can be a value of @ref FLASHEx_Option_Type */
+
+  uint32_t WRPState;       /*!< Write protection activation or deactivation.
+                                This parameter can be a value of @ref FLASHEx_WRP_State */
+
+  uint32_t WRPSector;      /*!< Specifies the sector(s) to be write protected.
+                                The value of this parameter depend on device used within the same series */
+
+  uint32_t RDPLevel;       /*!< Set the read protection level.
+                                This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
+
+  uint32_t BORLevel;       /*!< Set the BOR Level.
+                                This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */
+
+  uint32_t USERType;       /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER).
+                                This parameter can be a combination of @ref FLASHEx_OB_USER_Type */
+
+  uint32_t USERConfig;     /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY /
+                                IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / IO_HSLV / SWAP_BANK_OPT */
+
+  uint32_t Banks;          /*!< Select banks for WRP , PCROP and secure area config .
+                                This parameter must be a value of @ref FLASHEx_Banks */
+
+  uint32_t PCROPConfig;    /*!< specifies if the PCROP area shall be erased or not
+                                when RDP level decreased from Level 1 to Level 0 or during a mass erase.
+                                This parameter must be a value of @ref FLASHEx_OB_PCROP_RDP enumeration */
+
+  uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP).
+                                This parameter must be a value between begin and end of a bank */
+
+  uint32_t PCROPEndAddr;   /*!< PCROP End address (used for OPTIONBYTE_PCROP).
+                                This parameter must be a value between PCROP Start address and end of a bank */
+
+  uint32_t BootConfig;     /*!< Specifies if the Boot Address to be configured BOOT_ADD0, BOOT_ADD1
+                                or both. This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION enumeration */
+
+  uint32_t BootAddr0;      /*!< Boot Address 0.
+                                This parameter must be a value between begin and end of a bank */
+
+  uint32_t BootAddr1;      /*!< Boot Address 1.
+                                This parameter must be a value between begin and end of a bank */
+#if defined(DUAL_CORE)
+  uint32_t CM4BootConfig;  /*!< specifies if the CM4 boot Address to be configured BOOT_ADD0, BOOT_ADD1
+                                or both.
+                                This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION enumeration */
+
+  uint32_t CM4BootAddr0;   /*!< CM4 Boot Address 0.
+                                This parameter must be a value between begin and end of a bank */
+
+  uint32_t CM4BootAddr1;   /*!< CM4 Boot Address 1.
+                                This parameter must be a value between begin and end of a bank */
+#endif /*DUAL_CORE*/
+
+  uint32_t SecureAreaConfig;    /*!< specifies if the bank secured area shall be erased or not
+                                     when RDP level decreased from Level 1 to Level 0 or during a mass erase.
+                                     This parameter must be a value of @ref FLASHEx_OB_SECURE_RDP enumeration */
+
+  uint32_t SecureAreaStartAddr; /*!< Bank Secure area Start address.
+                                     This parameter must be a value between begin address and end address of bank1 */
+
+  uint32_t SecureAreaEndAddr;   /*!< Bank Secure area End address.
+                                     This parameter must be a value between Secure Area Start address and end address of a bank1 */
+
+#if defined (FLASH_OTPBL_LOCKBL)
+  uint32_t OTPBlockLock;   /*!< Specifies the OTP block(s) to be locked.
+                                This parameter must be a value of @ref FLASHEx_OTP_Blocks */
+#endif /* FLASH_OTPBL_LOCKBL */
+
+} FLASH_OBProgramInitTypeDef;
+
+/**
+  * @brief  FLASH Erase structure definition
+  */
+typedef struct
+{
+  uint32_t TypeCRC;      /*!< CRC Selection Type.
+                              This parameter can be a value of @ref FLASHEx_CRC_Selection_Type */
+
+  uint32_t BurstSize;    /*!< CRC Burst Size.
+                              This parameter can be a value of @ref FLASHEx_CRC_Burst_Size */
+
+  uint32_t Bank;         /*!< Select bank where CRC computation is enabled.
+                              This parameter must be FLASH_BANK_1 or FLASH_BANK_2 */
+
+  uint32_t Sector;       /*!< Initial FLASH sector from which starts the CRC computation
+                              This parameter must be a value of @ref FLASH_Sectors */
+
+  uint32_t NbSectors;    /*!< Number of sectors to be computed.
+                              This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
+
+  uint32_t CRCStartAddr; /*!< CRC Start address.
+                              This parameter must be a value between begin address and end address of a bank */
+
+  uint32_t CRCEndAddr;   /*!< CRC End address.
+                              This parameter must be a value between CRC Start address and end address of a bank */
+
+} FLASH_CRCInitTypeDef;
+
+/**
+  * @}
+  */
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants
+  * @{
+  */
+
+/** @defgroup FLASHEx_Type_Erase FLASH Type Erase
+  * @{
+  */
+#define FLASH_TYPEERASE_SECTORS      0x00U  /*!< Sectors erase only          */
+#define FLASH_TYPEERASE_MASSERASE    0x01U  /*!< Flash Mass erase activation */
+/**
+  * @}
+  */
+
+#if defined (FLASH_CR_PSIZE)
+/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range
+  * @{
+  */
+#define FLASH_VOLTAGE_RANGE_1        0x00000000U       /*!< Flash program/erase by 8 bits  */
+#define FLASH_VOLTAGE_RANGE_2        FLASH_CR_PSIZE_0  /*!< Flash program/erase by 16 bits */
+#define FLASH_VOLTAGE_RANGE_3        FLASH_CR_PSIZE_1  /*!< Flash program/erase by 32 bits */
+#define FLASH_VOLTAGE_RANGE_4        FLASH_CR_PSIZE    /*!< Flash program/erase by 64 bits */
+/**
+  * @}
+  */
+#endif /* FLASH_CR_PSIZE */
+
+/** @defgroup FLASHEx_WRP_State FLASH WRP State
+  * @{
+  */
+#define OB_WRPSTATE_DISABLE          0x00000000U  /*!< Disable the write protection of the desired bank 1 sectors */
+#define OB_WRPSTATE_ENABLE           0x00000001U  /*!< Enable the write protection of the desired bank 1 sectors  */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Option_Type FLASH Option Type
+  * @{
+  */
+#define OPTIONBYTE_WRP           0x01U  /*!< WRP option byte configuration  */
+#define OPTIONBYTE_RDP           0x02U  /*!< RDP option byte configuration  */
+#define OPTIONBYTE_USER          0x04U  /*!< USER option byte configuration */
+#define OPTIONBYTE_PCROP         0x08U  /*!< PCROP option byte configuration */
+#define OPTIONBYTE_BOR           0x10U  /*!< BOR option byte configuration */
+#define OPTIONBYTE_SECURE_AREA   0x20U  /*!< secure area option byte configuration */
+#if defined (DUAL_CORE)
+#define OPTIONBYTE_CM7_BOOTADD   0x40U  /*!< CM7 BOOT ADD option byte configuration */
+#define OPTIONBYTE_CM4_BOOTADD   0x80U  /*!< CM4 BOOT ADD option byte configuration */
+#define OPTIONBYTE_BOOTADD       OPTIONBYTE_CM7_BOOTADD  /*!< BOOT ADD option byte configuration */
+#else /* Single core */
+#define OPTIONBYTE_BOOTADD       0x40U  /*!< BOOT ADD option byte configuration */
+#endif /*DUAL_CORE*/
+#if defined (FLASH_OTPBL_LOCKBL)
+#define OPTIONBYTE_OTP_LOCK      0x80U  /*!< OTP Lock option byte configuration */
+#endif /* FLASH_OTPBL_LOCKBL */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection
+  * @{
+  */
+#define OB_RDP_LEVEL_0       0xAA00U
+#define OB_RDP_LEVEL_1       0x5500U
+#define OB_RDP_LEVEL_2       0xCC00U   /*!< Warning: When enabling read protection level 2
+                                            it s no more possible to go back to level 1 or 0 */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Option_Bytes_WWatchdog FLASH Option Bytes WWatchdog
+  * @{
+  */
+#define OB_WWDG_SW           0x10U  /*!< Software WWDG selected */
+#define OB_WWDG_HW           0x00U  /*!< Hardware WWDG selected */
+/**
+  * @}
+  */
+
+
+/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog
+  * @{
+  */
+#define OB_IWDG_SW           0x20U  /*!< Software IWDG selected */
+#define OB_IWDG_HW           0x00U  /*!< Hardware IWDG selected */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP
+  * @{
+  */
+#define OB_STOP_NO_RST       0x40U /*!< No reset generated when entering in STOP */
+#define OB_STOP_RST          0x00U /*!< Reset generated when entering in STOP    */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY
+  * @{
+  */
+#define OB_STDBY_NO_RST      0x80U /*!< No reset generated when entering in STANDBY */
+#define OB_STDBY_RST         0x00U /*!< Reset generated when entering in STANDBY    */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP
+  * @{
+  */
+#define OB_IWDG_STOP_FREEZE  0x00000000U /*!< Freeze IWDG counter in STOP mode */
+#define OB_IWDG_STOP_ACTIVE  FLASH_OPTSR_FZ_IWDG_STOP /*!< IWDG counter active in STOP mode */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY
+  * @{
+  */
+#define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Freeze IWDG counter in STANDBY mode */
+#define OB_IWDG_STDBY_ACTIVE FLASH_OPTSR_FZ_IWDG_SDBY  /*!< IWDG counter active in STANDBY mode */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level
+  * @{
+  */
+#define OB_BOR_LEVEL0        0x00000000U                /*!< Reset level threshold is set to 1.6V */
+#define OB_BOR_LEVEL1        FLASH_OPTSR_BOR_LEV_0      /*!< Reset level threshold is set to 2.1V */
+#define OB_BOR_LEVEL2        FLASH_OPTSR_BOR_LEV_1      /*!< Reset level threshold is set to 2.4V */
+#define OB_BOR_LEVEL3        (FLASH_OPTSR_BOR_LEV_1 | FLASH_OPTSR_BOR_LEV_0) /*!< Reset level threshold is set to 2.7V  */
+/**
+  * @}
+  */
+
+
+
+/** @defgroup FLASHEx_Boot_Address FLASH Boot Address
+  * @{
+  */
+#define OB_BOOTADDR_ITCM_RAM     0x0000U  /*!< Boot from ITCM RAM (0x00000000)                 */
+#define OB_BOOTADDR_SYSTEM       0x0040U  /*!< Boot from System memory bootloader (0x00100000) */
+#define OB_BOOTADDR_ITCM_FLASH   0x0080U  /*!< Boot from Flash on ITCM interface (0x00200000)  */
+#define OB_BOOTADDR_AXIM_FLASH   0x2000U  /*!< Boot from Flash on AXIM interface (0x08000000)  */
+#define OB_BOOTADDR_DTCM_RAM     0x8000U  /*!< Boot from DTCM RAM (0x20000000)                 */
+#define OB_BOOTADDR_SRAM1        0x8004U  /*!< Boot from SRAM1 (0x20010000)                    */
+#define OB_BOOTADDR_SRAM2        0x8013U  /*!< Boot from SRAM2 (0x2004C000)                    */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Latency FLASH Latency
+  * @{
+  */
+#define FLASH_LATENCY_0          FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero Latency cycle      */
+#define FLASH_LATENCY_1          FLASH_ACR_LATENCY_1WS   /*!< FLASH One Latency cycle       */
+#define FLASH_LATENCY_2          FLASH_ACR_LATENCY_2WS   /*!< FLASH Two Latency cycles      */
+#define FLASH_LATENCY_3          FLASH_ACR_LATENCY_3WS   /*!< FLASH Three Latency cycles    */
+#define FLASH_LATENCY_4          FLASH_ACR_LATENCY_4WS   /*!< FLASH Four Latency cycles     */
+#define FLASH_LATENCY_5          FLASH_ACR_LATENCY_5WS   /*!< FLASH Five Latency cycles     */
+#define FLASH_LATENCY_6          FLASH_ACR_LATENCY_6WS   /*!< FLASH Six Latency cycles      */
+#define FLASH_LATENCY_7          FLASH_ACR_LATENCY_7WS   /*!< FLASH Seven Latency cycles    */
+#define FLASH_LATENCY_8          FLASH_ACR_LATENCY_8WS   /*!< FLASH Eight Latency cycle     */
+#define FLASH_LATENCY_9          FLASH_ACR_LATENCY_9WS   /*!< FLASH Nine Latency cycle      */
+#define FLASH_LATENCY_10         FLASH_ACR_LATENCY_10WS  /*!< FLASH Ten Latency cycles      */
+#define FLASH_LATENCY_11         FLASH_ACR_LATENCY_11WS  /*!< FLASH Eleven Latency cycles   */
+#define FLASH_LATENCY_12         FLASH_ACR_LATENCY_12WS  /*!< FLASH Twelve Latency cycles   */
+#define FLASH_LATENCY_13         FLASH_ACR_LATENCY_13WS  /*!< FLASH Thirteen Latency cycles */
+#define FLASH_LATENCY_14         FLASH_ACR_LATENCY_14WS  /*!< FLASH Fourteen Latency cycles */
+#define FLASH_LATENCY_15         FLASH_ACR_LATENCY_15WS  /*!< FLASH Fifteen Latency cycles  */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Banks FLASH Banks
+  * @{
+  */
+#define FLASH_BANK_1             0x01U                         /*!< Bank 1   */
+#define FLASH_BANK_2             0x02U                         /*!< Bank 2   */
+#define FLASH_BANK_BOTH          (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2  */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_OB_PCROP_RDP  FLASHEx OB PCROP RDP
+  * @{
+  */
+#define OB_PCROP_RDP_NOT_ERASE   0x00000000U     /*!< PCROP area is not erased when the RDP level
+                                                      is decreased from Level 1 to Level 0 or during a mass erase */
+#define OB_PCROP_RDP_ERASE       FLASH_PRAR_DMEP /*!< PCROP area is erased when the RDP level is
+                                                      decreased from Level 1 to Level 0 (full mass erase) */
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
+  * @{
+  */
+#if (FLASH_SECTOR_TOTAL == 128)
+#define OB_WRP_SECTOR_0TO3       0x00000001U /*!< Write protection of Sector0  to Sector3    */
+#define OB_WRP_SECTOR_4TO7       0x00000002U /*!< Write protection of Sector4  to Sector7    */
+#define OB_WRP_SECTOR_8TO11      0x00000004U /*!< Write protection of Sector8  to Sector11   */
+#define OB_WRP_SECTOR_12TO15     0x00000008U /*!< Write protection of Sector12 to Sector15   */
+#define OB_WRP_SECTOR_16TO19     0x00000010U /*!< Write protection of Sector16 to Sector19   */
+#define OB_WRP_SECTOR_20TO23     0x00000020U /*!< Write protection of Sector20 to Sector23   */
+#define OB_WRP_SECTOR_24TO27     0x00000040U /*!< Write protection of Sector24 to Sector27   */
+#define OB_WRP_SECTOR_28TO31     0x00000080U /*!< Write protection of Sector28 to Sector31   */
+#define OB_WRP_SECTOR_32TO35     0x00000100U /*!< Write protection of Sector32 to Sector35   */
+#define OB_WRP_SECTOR_36TO39     0x00000200U /*!< Write protection of Sector36 to Sector39   */
+#define OB_WRP_SECTOR_40TO43     0x00000400U /*!< Write protection of Sector40 to Sector43   */
+#define OB_WRP_SECTOR_44TO47     0x00000800U /*!< Write protection of Sector44 to Sector47   */
+#define OB_WRP_SECTOR_48TO51     0x00001000U /*!< Write protection of Sector48 to Sector51   */
+#define OB_WRP_SECTOR_52TO55     0x00002000U /*!< Write protection of Sector52 to Sector55   */
+#define OB_WRP_SECTOR_56TO59     0x00004000U /*!< Write protection of Sector56 to Sector59   */
+#define OB_WRP_SECTOR_60TO63     0x00008000U /*!< Write protection of Sector60 to Sector63   */
+#define OB_WRP_SECTOR_64TO67     0x00010000U /*!< Write protection of Sector64 to Sector67   */
+#define OB_WRP_SECTOR_68TO71     0x00020000U /*!< Write protection of Sector68 to Sector71   */
+#define OB_WRP_SECTOR_72TO75     0x00040000U /*!< Write protection of Sector72 to Sector75   */
+#define OB_WRP_SECTOR_76TO79     0x00080000U /*!< Write protection of Sector76 to Sector79   */
+#define OB_WRP_SECTOR_80TO83     0x00100000U /*!< Write protection of Sector80 to Sector83   */
+#define OB_WRP_SECTOR_84TO87     0x00200000U /*!< Write protection of Sector84 to Sector87   */
+#define OB_WRP_SECTOR_88TO91     0x00400000U /*!< Write protection of Sector88 to Sector91   */
+#define OB_WRP_SECTOR_92TO95     0x00800000U /*!< Write protection of Sector92 to Sector95   */
+#define OB_WRP_SECTOR_96TO99     0x01000000U /*!< Write protection of Sector96  to Sector99  */
+#define OB_WRP_SECTOR_100TO103   0x02000000U /*!< Write protection of Sector100 to Sector103 */
+#define OB_WRP_SECTOR_104TO107   0x04000000U /*!< Write protection of Sector104 to Sector107 */
+#define OB_WRP_SECTOR_108TO111   0x08000000U /*!< Write protection of Sector108 to Sector111 */
+#define OB_WRP_SECTOR_112TO115   0x10000000U /*!< Write protection of Sector112 to Sector115 */
+#define OB_WRP_SECTOR_116TO119   0x20000000U /*!< Write protection of Sector116 to Sector119 */
+#define OB_WRP_SECTOR_120TO123   0x40000000U /*!< Write protection of Sector120 to Sector123 */
+#define OB_WRP_SECTOR_124TO127   0x80000000U /*!< Write protection of Sector124 to Sector127 */
+#define OB_WRP_SECTOR_ALL        0xFFFFFFFFU /*!< Write protection of all Sectors            */
+#else
+#define OB_WRP_SECTOR_0          0x00000001U /*!< Write protection of Sector0                */
+#define OB_WRP_SECTOR_1          0x00000002U /*!< Write protection of Sector1                */
+#define OB_WRP_SECTOR_2          0x00000004U /*!< Write protection of Sector2                */
+#define OB_WRP_SECTOR_3          0x00000008U /*!< Write protection of Sector3                */
+#define OB_WRP_SECTOR_4          0x00000010U /*!< Write protection of Sector4                */
+#define OB_WRP_SECTOR_5          0x00000020U /*!< Write protection of Sector5                */
+#define OB_WRP_SECTOR_6          0x00000040U /*!< Write protection of Sector6                */
+#define OB_WRP_SECTOR_7          0x00000080U /*!< Write protection of Sector7                */
+#define OB_WRP_SECTOR_ALL        0x000000FFU /*!< Write protection of all Sectors            */
+#endif /* FLASH_SECTOR_TOTAL == 128 */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_OB_SECURITY  FLASHEx OB SECURITY
+  * @{
+  */
+#define OB_SECURITY_DISABLE   0x00000000U             /*!< security enabled */
+#define OB_SECURITY_ENABLE    FLASH_OPTSR_SECURITY    /*!< security disabled */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_OB_ST_RAM_SIZE  FLASHEx OB ST RAM SIZE
+  * @{
+  */
+#define OB_ST_RAM_SIZE_2KB    0x00000000U               /*!< 2 Kbytes reserved to ST code */
+#define OB_ST_RAM_SIZE_4KB    FLASH_OPTSR_ST_RAM_SIZE_0 /*!< 4 Kbytes reserved to ST code */
+#define OB_ST_RAM_SIZE_8KB    FLASH_OPTSR_ST_RAM_SIZE_1 /*!< 8 Kbytes reserved to ST code */
+#define OB_ST_RAM_SIZE_16KB   FLASH_OPTSR_ST_RAM_SIZE   /*!< 16 Kbytes reserved to ST code */
+/**
+  * @}
+  */
+
+#if defined(DUAL_CORE)
+/** @defgroup FLASHEx_OB_BCM7  FLASHEx OB BCM7
+  * @{
+  */
+#define OB_BCM7_DISABLE       0x00000000U              /*!< CM7 Boot disabled */
+#define OB_BCM7_ENABLE        FLASH_OPTSR_BCM7         /*!< CM7 Boot enabled */
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_OB_BCM4  FLASHEx OB BCM4
+  * @{
+  */
+#define OB_BCM4_DISABLE       0x00000000U              /*!< CM4 Boot disabled */
+#define OB_BCM4_ENABLE        FLASH_OPTSR_BCM4         /*!< CM4 Boot enabled */
+/**
+  * @}
+  */
+#endif /* DUAL_CORE */
+
+/** @defgroup FLASHEx_OB_IWDG1_SW  FLASHEx OB IWDG1 SW
+  * @{
+  */
+#define OB_IWDG1_SW            FLASH_OPTSR_IWDG1_SW /*!< Hardware independent watchdog 1 */
+#define OB_IWDG1_HW            0x00000000U          /*!< Software independent watchdog 1 */
+/**
+  * @}
+  */
+
+#if defined(DUAL_CORE)
+/** @defgroup FLASHEx_OB_IWDG2_SW  FLASHEx OB IWDG2 SW
+  * @{
+  */
+#define OB_IWDG2_SW            FLASH_OPTSR_IWDG2_SW  /*!< Hardware independent watchdog 2*/
+#define OB_IWDG2_HW            0x00000000U           /*!< Software independent watchdog 2*/
+/**
+  * @}
+  */
+#endif
+
+/** @defgroup FLASHEx_OB_NRST_STOP_D1  FLASHEx OB NRST STOP D1
+  * @{
+  */
+#define OB_STOP_RST_D1         0x00000000U              /*!< Reset generated when entering the D1 to stop mode */
+#define OB_STOP_NO_RST_D1      FLASH_OPTSR_NRST_STOP_D1 /*!< No reset generated when entering the D1 to stop mode */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_OB_NRST_STDBY_D1  FLASHEx OB NRST STDBY D1
+  * @{
+  */
+#define OB_STDBY_RST_D1        0x00000000U              /*!< Reset generated when entering the D1 to standby mode */
+#define OB_STDBY_NO_RST_D1     FLASH_OPTSR_NRST_STBY_D1 /*!< No reset generated when entering the D1 to standby mode */
+/**
+  * @}
+  */
+
+#if defined (DUAL_CORE)
+/** @defgroup FLASHEx_OB_NRST_STOP_D2  FLASHEx OB NRST STOP D2
+  * @{
+  */
+#define OB_STOP_RST_D2         0x00000000U              /*!< Reset generated when entering the D2 to stop mode */
+#define OB_STOP_NO_RST_D2      FLASH_OPTSR_NRST_STOP_D2 /*!< No reset generated when entering the D2 to stop mode */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_OB_NRST_STDBY_D2  FLASHEx OB NRST STDBY D2
+  * @{
+  */
+#define OB_STDBY_RST_D2        0x00000000U              /*!< Reset generated when entering the D2 to standby mode */
+#define OB_STDBY_NO_RST_D2     FLASH_OPTSR_NRST_STBY_D2 /*!< No reset generated when entering the D2 to standby mode */
+/**
+  * @}
+  */
+#endif /* DUAL_CORE */
+
+/** @defgroup FLASHEx_OB_SWAP_BANK  FLASHEx OB SWAP BANK
+  * @{
+  */
+#define OB_SWAP_BANK_DISABLE   0x00000000U               /*!< Bank swap disabled */
+#define OB_SWAP_BANK_ENABLE    FLASH_OPTSR_SWAP_BANK_OPT /*!< Bank swap enabled */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_OB_IOHSLV FLASHEx OB IOHSLV
+  * @{
+  */
+#define OB_IOHSLV_DISABLE      0x00000000U         /*!< IOHSLV disabled */
+#define OB_IOHSLV_ENABLE       FLASH_OPTSR_IO_HSLV /*!< IOHSLV enabled */
+/**
+  * @}
+  */
+
+#if defined (FLASH_OPTSR_VDDMMC_HSLV)
+/** @defgroup FLASHEx_OB_VDDMMC_HSLV FLASHEx OB VDDMMC HSLV
+  * @{
+  */
+#define OB_VDDMMC_HSLV_DISABLE 0x00000000U             /*!< VDDMMC HSLV disabled */
+#define OB_VDDMMC_HSLV_ENABLE  FLASH_OPTSR_VDDMMC_HSLV /*!< VDDMMC HSLV enabled */
+/**
+  * @}
+  */
+#endif /* FLASH_OPTSR_VDDMMC_HSLV */
+
+/** @defgroup FLASHEx_OB_BOOT_OPTION  FLASHEx OB BOOT OPTION
+  * @{
+  */
+#define OB_BOOT_ADD0           0x01U       /*!< Select Boot Address 0 */
+#define OB_BOOT_ADD1           0x02U       /*!< Select Boot Address 1 */
+#define OB_BOOT_ADD_BOTH       0x03U       /*!< Select Boot Address 0 and 1 */
+/**
+  * @}
+  */
+
+ /** @defgroup FLASHEx_OB_USER_Type  FLASHEx OB USER Type
+  * @{
+  */
+#define OB_USER_IWDG1_SW          0x0001U /*!< Independent watchdog selection */
+#define OB_USER_NRST_STOP_D1      0x0002U /*!< Reset when entering Stop mode selection*/
+#define OB_USER_NRST_STDBY_D1     0x0004U /*!< Reset when entering standby mode selection*/
+#define OB_USER_IWDG_STOP         0x0008U /*!< Independent watchdog counter freeze in stop mode */
+#define OB_USER_IWDG_STDBY        0x0010U /*!< Independent watchdog counter freeze in standby mode */
+#define OB_USER_ST_RAM_SIZE       0x0020U /*!< dedicated DTCM Ram size selection */
+#define OB_USER_SECURITY          0x0040U /*!< security selection */
+#define OB_USER_IOHSLV            0x0080U /*!< IO HSLV selection */
+#define OB_USER_SWAP_BANK         0x0100U /*!< Bank swap selection */
+#if defined (FLASH_OPTSR_VDDMMC_HSLV)
+#define OB_USER_VDDMMC_HSLV       0x0200U /*!< VDDMMC HSLV selection */
+#endif /* FLASH_OPTSR_VDDMMC_HSLV */
+#if defined (DUAL_CORE)
+#define OB_USER_IWDG2_SW          0x0200U /*!< Window watchdog selection */
+#define OB_USER_BCM4              0x0400U /*!< CM4 boot selection */
+#define OB_USER_BCM7              0x0800U /*!< CM7 boot selection */
+#define OB_USER_NRST_STOP_D2      0x1000U /*!< Reset when entering Stop mode selection*/
+#define OB_USER_NRST_STDBY_D2     0x2000U /*!< Reset when entering standby mode selection*/
+#endif /*DUAL_CORE*/
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_OB_SECURE_RDP  FLASHEx OB SECURE RDP
+  * @{
+  */
+#define OB_SECURE_RDP_NOT_ERASE   0x00000000U     /*!< Secure area is not erased when the RDP level
+                                                       is decreased from Level 1 to Level 0 or during a mass erase */
+#define OB_SECURE_RDP_ERASE       FLASH_SCAR_DMES /*!< Secure area is erased when the RDP level is
+                                                       decreased from Level 1 to Level 0 (full mass erase) */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_CRC_Selection_Type FLASH CRC Selection Type
+  * @{
+  */
+#define FLASH_CRC_ADDR         0x00000000U              /*!< CRC selection type by address  */
+#define FLASH_CRC_SECTORS      FLASH_CRCCR_CRC_BY_SECT  /*!< CRC selection type by sectors  */
+#define FLASH_CRC_BANK         (FLASH_CRCCR_ALL_BANK | FLASH_CRCCR_CRC_BY_SECT) /*!< CRC selection type by bank */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_CRC_Burst_Size FLASH CRC Burst Size
+  * @{
+  */
+#define FLASH_CRC_BURST_SIZE_4    0x00000000U              /*!< Every burst has a size of 4 Flash words (256-bit)  */
+#define FLASH_CRC_BURST_SIZE_16   FLASH_CRCCR_CRC_BURST_0  /*!< Every burst has a size of 16 Flash words (256-bit)   */
+#define FLASH_CRC_BURST_SIZE_64   FLASH_CRCCR_CRC_BURST_1  /*!< Every burst has a size of 64 Flash words (256-bit)   */
+#define FLASH_CRC_BURST_SIZE_256  FLASH_CRCCR_CRC_BURST    /*!< Every burst has a size of 256 Flash words (256-bit) */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Programming_Delay FLASH Programming Delay
+  * @{
+  */
+#define FLASH_PROGRAMMING_DELAY_0   0x00000000U            /*!< programming delay set for Flash running at 70 MHz or below          */
+#define FLASH_PROGRAMMING_DELAY_1   FLASH_ACR_WRHIGHFREQ_0 /*!< programming delay set for Flash running between 70 MHz and 185 MHz  */
+#define FLASH_PROGRAMMING_DELAY_2   FLASH_ACR_WRHIGHFREQ_1 /*!< programming delay set for Flash running between 185 MHz and 225 MHz */
+#define FLASH_PROGRAMMING_DELAY_3   FLASH_ACR_WRHIGHFREQ   /*!< programming delay set for Flash at startup */
+/**
+  * @}
+  */
+
+#if defined (FLASH_OTPBL_LOCKBL)
+/** @defgroup FLASHEx_OTP_Blocks FLASH OTP blocks
+  * @{
+  */
+#define FLASH_OTP_BLOCK_0          0x00000001U /*!< OTP Block0     */
+#define FLASH_OTP_BLOCK_1          0x00000002U /*!< OTP Block1     */
+#define FLASH_OTP_BLOCK_2          0x00000004U /*!< OTP Block2     */
+#define FLASH_OTP_BLOCK_3          0x00000008U /*!< OTP Block3     */
+#define FLASH_OTP_BLOCK_4          0x00000010U /*!< OTP Block4     */
+#define FLASH_OTP_BLOCK_5          0x00000020U /*!< OTP Block5     */
+#define FLASH_OTP_BLOCK_6          0x00000040U /*!< OTP Block6     */
+#define FLASH_OTP_BLOCK_7          0x00000080U /*!< OTP Block7     */
+#define FLASH_OTP_BLOCK_8          0x00000100U /*!< OTP Block8     */
+#define FLASH_OTP_BLOCK_9          0x00000200U /*!< OTP Block9     */
+#define FLASH_OTP_BLOCK_10         0x00000400U /*!< OTP Block10    */
+#define FLASH_OTP_BLOCK_11         0x00000800U /*!< OTP Block11    */
+#define FLASH_OTP_BLOCK_12         0x00001000U /*!< OTP Block12    */
+#define FLASH_OTP_BLOCK_13         0x00002000U /*!< OTP Block13    */
+#define FLASH_OTP_BLOCK_14         0x00004000U /*!< OTP Block14    */
+#define FLASH_OTP_BLOCK_15         0x00008000U /*!< OTP Block15    */
+#define FLASH_OTP_BLOCK_ALL        0x0000FFFFU /*!< OTP All Blocks */
+/**
+  * @}
+  */
+#endif /* FLASH_OTPBL_LOCKBL */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Macros FLASH Exported Macros
+  * @{
+  */
+/**
+  * @brief  Calculate the FLASH Boot Base Adress (BOOT_ADD0 or BOOT_ADD1)
+  * @note   Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14].
+  * @param  __ADDRESS__: FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB)
+  * @retval The FLASH Boot Base Adress
+  */
+#define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14U)
+ /**
+  * @}
+  */
+
+#if defined (FLASH_CR_PSIZE)
+/**
+  * @brief  Set the FLASH Program/Erase parallelism.
+  * @param  __PSIZE__ FLASH Program/Erase parallelism
+  *         This parameter can be a value of @ref FLASH_Program_Parallelism
+  * @param  __BANK__: Flash bank (FLASH_BANK_1 or FLASH_BANK_2)
+  * @retval none
+  */
+#define __HAL_FLASH_SET_PSIZE(__PSIZE__, __BANK__) (((__BANK__) == FLASH_BANK_1)  ? \
+                              MODIFY_REG(FLASH->CR1, FLASH_CR_PSIZE, (__PSIZE__)) : \
+                              MODIFY_REG(FLASH->CR2, FLASH_CR_PSIZE, (__PSIZE__)))
+
+/**
+  * @brief  Get the FLASH Program/Erase parallelism.
+  * @param  __BANK__ Flash bank (FLASH_BANK_1 or FLASH_BANK_2)
+  * @retval FLASH Program/Erase parallelism
+  *         This return value can be a value of @ref FLASH_Program_Parallelism
+  */
+#define __HAL_FLASH_GET_PSIZE(__BANK__) (((__BANK__) == FLASH_BANK_1) ? \
+                              READ_BIT((FLASH->CR1), FLASH_CR_PSIZE)  : \
+                              READ_BIT((FLASH->CR2), FLASH_CR_PSIZE))
+#endif /* FLASH_CR_PSIZE */
+
+/**
+  * @brief  Set the FLASH Programming Delay.
+  * @param  __DELAY__ FLASH Programming Delay
+  *         This parameter can be a value of @ref FLASHEx_Programming_Delay
+  * @retval none
+  */
+#define __HAL_FLASH_SET_PROGRAM_DELAY(__DELAY__)  MODIFY_REG(FLASH->ACR, FLASH_ACR_WRHIGHFREQ, (__DELAY__))
+
+/**
+  * @brief  Get the FLASH Programming Delay.
+  * @retval FLASH Programming Delay
+  *         This return value can be a value of @ref FLASHEx_Programming_Delay
+  */
+#define __HAL_FLASH_GET_PROGRAM_DELAY()     READ_BIT(FLASH->ACR, FLASH_ACR_WRHIGHFREQ)
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASHEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup FLASHEx_Exported_Functions_Group1
+  * @{
+  */
+/* Extension Program operation functions  *************************************/
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError);
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
+void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
+
+HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank1(void);
+HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1(void);
+HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank2(void);
+HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank2(void);
+
+HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_t *CRC_Result);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros
+  * @{
+  */
+
+/** @defgroup FLASHEx_IS_FLASH_Definitions FLASHEx Private macros to check input parameters
+  * @{
+  */
+
+#define IS_FLASH_TYPEERASE(VALUE)        (((VALUE) == FLASH_TYPEERASE_SECTORS) || \
+                                          ((VALUE) == FLASH_TYPEERASE_MASSERASE))
+
+#if defined (FLASH_CR_PSIZE)
+#define IS_VOLTAGERANGE(RANGE)           (((RANGE) == FLASH_VOLTAGE_RANGE_1) || \
+                                          ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \
+                                          ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \
+                                          ((RANGE) == FLASH_VOLTAGE_RANGE_4))
+#endif /* FLASH_CR_PSIZE */
+
+#define IS_WRPSTATE(VALUE)               (((VALUE) == OB_WRPSTATE_DISABLE) || \
+                                          ((VALUE) == OB_WRPSTATE_ENABLE))
+
+#if defined (FLASH_OPTSR_VDDMMC_HSLV)
+#define IS_OPTIONBYTE(VALUE)             (((VALUE) <= 0x03FFU) && ((VALUE) != 0U))
+#elif defined (DUAL_CORE)
+#define IS_OPTIONBYTE(VALUE)             (((VALUE) <= 0x3FFFU) && ((VALUE) != 0U))
+#else
+#define IS_OPTIONBYTE(VALUE)             (((VALUE) <= 0x01FFU) && ((VALUE) != 0U))
+#endif /*DUAL_CORE*/
+
+#define IS_OB_BOOT_ADDRESS(ADDRESS)      ((ADDRESS) <= 0x8013U)
+
+#define IS_OB_RDP_LEVEL(LEVEL)           (((LEVEL) == OB_RDP_LEVEL_0)   ||\
+                                          ((LEVEL) == OB_RDP_LEVEL_1)   ||\
+                                          ((LEVEL) == OB_RDP_LEVEL_2))
+
+#define IS_OB_WWDG_SOURCE(SOURCE)        (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW))
+
+#define IS_OB_IWDG_SOURCE(SOURCE)        (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+
+#define IS_OB_STOP_SOURCE(SOURCE)        (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
+
+#define IS_OB_STDBY_SOURCE(SOURCE)       (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
+
+#define IS_OB_IWDG_STOP_FREEZE(FREEZE)   (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE))
+
+#define IS_OB_IWDG_STDBY_FREEZE(FREEZE)  (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE))
+
+#define IS_OB_BOR_LEVEL(LEVEL)           (((LEVEL) == OB_BOR_LEVEL0) || ((LEVEL) == OB_BOR_LEVEL1) || \
+                                          ((LEVEL) == OB_BOR_LEVEL2) || ((LEVEL) == OB_BOR_LEVEL3))
+
+#define IS_FLASH_LATENCY(LATENCY)        (((LATENCY) == FLASH_LATENCY_0)  || \
+                                          ((LATENCY) == FLASH_LATENCY_1)  || \
+                                          ((LATENCY) == FLASH_LATENCY_2)  || \
+                                          ((LATENCY) == FLASH_LATENCY_3)  || \
+                                          ((LATENCY) == FLASH_LATENCY_4)  || \
+                                          ((LATENCY) == FLASH_LATENCY_5)  || \
+                                          ((LATENCY) == FLASH_LATENCY_6)  || \
+                                          ((LATENCY) == FLASH_LATENCY_7)  || \
+                                          ((LATENCY) == FLASH_LATENCY_8)  || \
+                                          ((LATENCY) == FLASH_LATENCY_9)  || \
+                                          ((LATENCY) == FLASH_LATENCY_10) || \
+                                          ((LATENCY) == FLASH_LATENCY_11) || \
+                                          ((LATENCY) == FLASH_LATENCY_12) || \
+                                          ((LATENCY) == FLASH_LATENCY_13) || \
+                                          ((LATENCY) == FLASH_LATENCY_14) || \
+                                          ((LATENCY) == FLASH_LATENCY_15))
+
+#define IS_FLASH_SECTOR(SECTOR)          ((SECTOR) < FLASH_SECTOR_TOTAL)
+
+#if (FLASH_SECTOR_TOTAL == 8U)
+#define IS_OB_WRP_SECTOR(SECTOR)         ((((SECTOR) & 0xFFFFFF00U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
+#else
+#define IS_OB_WRP_SECTOR(SECTOR)         ((SECTOR) != 0x00000000U)
+#endif /* FLASH_SECTOR_TOTAL == 8U */
+
+#define IS_OB_PCROP_RDP(CONFIG)          (((CONFIG) == OB_PCROP_RDP_NOT_ERASE) || \
+                                          ((CONFIG) == OB_PCROP_RDP_ERASE))
+
+#define IS_OB_SECURE_RDP(CONFIG)         (((CONFIG) == OB_SECURE_RDP_NOT_ERASE) || \
+                                          ((CONFIG) == OB_SECURE_RDP_ERASE))
+
+#define IS_OB_USER_SWAP_BANK(VALUE)      (((VALUE) == OB_SWAP_BANK_DISABLE) || ((VALUE) == OB_SWAP_BANK_ENABLE))
+
+#define IS_OB_USER_IOHSLV(VALUE)         (((VALUE) == OB_IOHSLV_DISABLE) || ((VALUE) == OB_IOHSLV_ENABLE))
+
+#if defined (FLASH_OPTSR_VDDMMC_HSLV)
+#define IS_OB_USER_VDDMMC_HSLV(VALUE)    (((VALUE) == OB_VDDMMC_HSLV_DISABLE) || ((VALUE) == OB_VDDMMC_HSLV_ENABLE))
+#endif /* FLASH_OPTSR_VDDMMC_HSLV */
+
+#define IS_OB_IWDG1_SOURCE(SOURCE)       (((SOURCE) == OB_IWDG1_SW) || ((SOURCE) == OB_IWDG1_HW))
+#if defined (DUAL_CORE)
+#define IS_OB_IWDG2_SOURCE(SOURCE)       (((SOURCE) == OB_IWDG2_SW) || ((SOURCE) == OB_IWDG2_HW))
+#endif /* DUAL_CORE */
+#define IS_OB_STOP_D1_RESET(VALUE)       (((VALUE) == OB_STOP_NO_RST_D1) || ((VALUE) == OB_STOP_RST_D1))
+
+#define IS_OB_STDBY_D1_RESET(VALUE)      (((VALUE) == OB_STDBY_NO_RST_D1) || ((VALUE) == OB_STDBY_RST_D1))
+
+#define IS_OB_USER_IWDG_STOP(VALUE)      (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_ACTIVE))
+
+#define IS_OB_USER_IWDG_STDBY(VALUE)     (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_ACTIVE))
+
+#define IS_OB_USER_ST_RAM_SIZE(VALUE)    (((VALUE) == OB_ST_RAM_SIZE_2KB) || ((VALUE) == OB_ST_RAM_SIZE_4KB) || \
+                                          ((VALUE) == OB_ST_RAM_SIZE_8KB) || ((VALUE) == OB_ST_RAM_SIZE_16KB))
+
+#define IS_OB_USER_SECURITY(VALUE)       (((VALUE) == OB_SECURITY_ENABLE) || ((VALUE) == OB_SECURITY_DISABLE))
+
+#if defined (DUAL_CORE)
+#define IS_OB_USER_BCM4(VALUE)           (((VALUE) == OB_BCM4_DISABLE) || ((VALUE) == OB_BCM4_ENABLE))
+
+#define IS_OB_USER_BCM7(VALUE)           (((VALUE) == OB_BCM7_DISABLE) || ((VALUE) == OB_BCM7_ENABLE))
+
+#define IS_OB_STOP_D2_RESET(VALUE)       (((VALUE) == OB_STOP_NO_RST_D2) || ((VALUE) == OB_STOP_RST_D2))
+
+#define IS_OB_STDBY_D2_RESET(VALUE)      (((VALUE) == OB_STDBY_NO_RST_D2) || ((VALUE) == OB_STDBY_RST_D2))
+#endif /* DUAL_CORE */
+#if defined (DUAL_CORE)
+#define IS_OB_USER_TYPE(TYPE)            (((TYPE) <= (uint32_t)0x3FFFU) && ((TYPE) != 0U))
+#else
+#define IS_OB_USER_TYPE(TYPE)            (((TYPE) <= (uint32_t)0x73FU) && ((TYPE) != 0U))
+#endif /* DUAL_CORE */
+
+#define IS_OB_BOOT_ADD_OPTION(VALUE)     (((VALUE) == OB_BOOT_ADD0)  || \
+                                          ((VALUE) == OB_BOOT_ADD1)  || \
+                                          ((VALUE) == OB_BOOT_ADD_BOTH))
+
+#define IS_FLASH_TYPECRC(VALUE)          (((VALUE) == FLASH_CRC_ADDR)    || \
+                                          ((VALUE) == FLASH_CRC_SECTORS) || \
+                                          ((VALUE) == FLASH_CRC_BANK))
+
+#if defined (FLASH_OTPBL_LOCKBL)
+#define IS_OTP_BLOCK(VALUE)              ((((VALUE) & 0xFFFF0000U) == 0x00000000U) && ((VALUE) != 0x00000000U))
+#endif /* FLASH_OTPBL_LOCKBL */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
+  * @{
+  */
+void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_FLASH_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h
new file mode 100644
index 00000000..c1855665
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h
@@ -0,0 +1,346 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_gpio.h
+  * @author  MCD Application Team
+  * @brief   Header file of GPIO HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_GPIO_H
+#define STM32H7xx_HAL_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup GPIO
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Types GPIO Exported Types
+  * @{
+  */
+
+/**
+  * @brief   GPIO Init structure definition
+  */
+typedef struct
+{
+  uint32_t Pin;       /*!< Specifies the GPIO pins to be configured.
+                           This parameter can be any value of @ref GPIO_pins_define */
+
+  uint32_t Mode;      /*!< Specifies the operating mode for the selected pins.
+                           This parameter can be a value of @ref GPIO_mode_define */
+
+  uint32_t Pull;      /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
+                           This parameter can be a value of @ref GPIO_pull_define */
+
+  uint32_t Speed;     /*!< Specifies the speed for the selected pins.
+                           This parameter can be a value of @ref GPIO_speed_define */
+
+  uint32_t Alternate;  /*!< Peripheral to be connected to the selected pins.
+                            This parameter can be a value of @ref GPIO_Alternate_function_selection */
+} GPIO_InitTypeDef;
+
+/**
+  * @brief  GPIO Bit SET and Bit RESET enumeration
+  */
+typedef enum
+{
+  GPIO_PIN_RESET = 0U,
+  GPIO_PIN_SET
+} GPIO_PinState;
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Constants  GPIO Exported Constants
+  * @{
+  */
+
+/** @defgroup GPIO_pins_define  GPIO pins define
+  * @{
+  */
+#define GPIO_PIN_0                 ((uint16_t)0x0001)  /* Pin 0 selected    */
+#define GPIO_PIN_1                 ((uint16_t)0x0002)  /* Pin 1 selected    */
+#define GPIO_PIN_2                 ((uint16_t)0x0004)  /* Pin 2 selected    */
+#define GPIO_PIN_3                 ((uint16_t)0x0008)  /* Pin 3 selected    */
+#define GPIO_PIN_4                 ((uint16_t)0x0010)  /* Pin 4 selected    */
+#define GPIO_PIN_5                 ((uint16_t)0x0020)  /* Pin 5 selected    */
+#define GPIO_PIN_6                 ((uint16_t)0x0040)  /* Pin 6 selected    */
+#define GPIO_PIN_7                 ((uint16_t)0x0080)  /* Pin 7 selected    */
+#define GPIO_PIN_8                 ((uint16_t)0x0100)  /* Pin 8 selected    */
+#define GPIO_PIN_9                 ((uint16_t)0x0200)  /* Pin 9 selected    */
+#define GPIO_PIN_10                ((uint16_t)0x0400)  /* Pin 10 selected   */
+#define GPIO_PIN_11                ((uint16_t)0x0800)  /* Pin 11 selected   */
+#define GPIO_PIN_12                ((uint16_t)0x1000)  /* Pin 12 selected   */
+#define GPIO_PIN_13                ((uint16_t)0x2000)  /* Pin 13 selected   */
+#define GPIO_PIN_14                ((uint16_t)0x4000)  /* Pin 14 selected   */
+#define GPIO_PIN_15                ((uint16_t)0x8000)  /* Pin 15 selected   */
+#define GPIO_PIN_All               ((uint16_t)0xFFFF)  /* All pins selected */
+
+#define GPIO_PIN_MASK              (0x0000FFFFU) /* PIN mask for assert test */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_mode_define  GPIO mode define
+  * @brief GPIO Configuration Mode
+  *        Elements values convention: 0xX0yz00YZ
+  *           - X  : GPIO mode or EXTI Mode
+  *           - y  : External IT or Event trigger detection
+  *           - z  : IO configuration on External IT or Event
+  *           - Y  : Output type (Push Pull or Open Drain)
+  *           - Z  : IO Direction mode (Input, Output, Alternate or Analog)
+  * @{
+  */
+#define  GPIO_MODE_INPUT                        (0x00000000U)   /*!< Input Floating Mode                   */
+#define  GPIO_MODE_OUTPUT_PP                    (0x00000001U)   /*!< Output Push Pull Mode                 */
+#define  GPIO_MODE_OUTPUT_OD                    (0x00000011U)   /*!< Output Open Drain Mode                */
+#define  GPIO_MODE_AF_PP                        (0x00000002U)   /*!< Alternate Function Push Pull Mode     */
+#define  GPIO_MODE_AF_OD                        (0x00000012U)   /*!< Alternate Function Open Drain Mode    */
+
+#define  GPIO_MODE_ANALOG                       (0x00000003U)   /*!< Analog Mode  */
+
+#define  GPIO_MODE_IT_RISING                    (0x11110000U)   /*!< External Interrupt Mode with Rising edge trigger detection          */
+#define  GPIO_MODE_IT_FALLING                   (0x11210000U)   /*!< External Interrupt Mode with Falling edge trigger detection         */
+#define  GPIO_MODE_IT_RISING_FALLING            (0x11310000U)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */
+
+#define  GPIO_MODE_EVT_RISING                   (0x11120000U)   /*!< External Event Mode with Rising edge trigger detection               */
+#define  GPIO_MODE_EVT_FALLING                  (0x11220000U)   /*!< External Event Mode with Falling edge trigger detection              */
+#define  GPIO_MODE_EVT_RISING_FALLING           (0x11320000U)   /*!< External Event Mode with Rising/Falling edge trigger detection       */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_speed_define  GPIO speed define
+  * @brief GPIO Output Maximum frequency
+  * @{
+  */
+#define  GPIO_SPEED_FREQ_LOW         (0x00000000U)  /*!< Low speed     */
+#define  GPIO_SPEED_FREQ_MEDIUM      (0x00000001U)  /*!< Medium speed  */
+#define  GPIO_SPEED_FREQ_HIGH        (0x00000002U)  /*!< Fast speed    */
+#define  GPIO_SPEED_FREQ_VERY_HIGH   (0x00000003U)  /*!< High speed    */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_pull_define  GPIO pull define
+  * @brief GPIO Pull-Up or Pull-Down Activation
+  * @{
+  */
+#define  GPIO_NOPULL        (0x00000000U)   /*!< No Pull-up or Pull-down activation  */
+#define  GPIO_PULLUP        (0x00000001U)   /*!< Pull-up activation                  */
+#define  GPIO_PULLDOWN      (0x00000002U)   /*!< Pull-down activation                */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
+  * @{
+  */
+
+/**
+  * @brief  Checks whether the specified EXTI line flag is set or not.
+  * @param  __EXTI_LINE__: specifies the EXTI line flag to check.
+  *         This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval The new state of __EXTI_LINE__ (SET or RESET).
+  */
+#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
+
+/**
+  * @brief  Clears the EXTI's line pending flags.
+  * @param  __EXTI_LINE__: specifies the EXTI lines flags to clear.
+  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
+
+/**
+  * @brief  Checks whether the specified EXTI line is asserted or not.
+  * @param  __EXTI_LINE__: specifies the EXTI line to check.
+  *          This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval The new state of __EXTI_LINE__ (SET or RESET).
+  */
+#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
+
+/**
+  * @brief  Clears the EXTI's line pending bits.
+  * @param  __EXTI_LINE__: specifies the EXTI lines to clear.
+  *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Checks whether the specified EXTI line flag is set or not.
+  * @param  __EXTI_LINE__: specifies the EXTI line flag to check.
+  *         This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval The new state of __EXTI_LINE__ (SET or RESET).
+  */
+#define __HAL_GPIO_EXTID2_GET_FLAG(__EXTI_LINE__) (EXTI->C2PR1 & (__EXTI_LINE__))
+
+/**
+  * @brief  Clears the EXTI's line pending flags.
+  * @param  __EXTI_LINE__: specifies the EXTI lines flags to clear.
+  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTID2_CLEAR_FLAG(__EXTI_LINE__) (EXTI->C2PR1 = (__EXTI_LINE__))
+
+/**
+  * @brief  Checks whether the specified EXTI line is asserted or not.
+  * @param  __EXTI_LINE__: specifies the EXTI line to check.
+  *          This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval The new state of __EXTI_LINE__ (SET or RESET).
+  */
+#define __HAL_GPIO_EXTID2_GET_IT(__EXTI_LINE__) (EXTI->C2PR1 & (__EXTI_LINE__))
+
+/**
+  * @brief  Clears the EXTI's line pending bits.
+  * @param  __EXTI_LINE__: specifies the EXTI lines to clear.
+  *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTID2_CLEAR_IT(__EXTI_LINE__) (EXTI->C2PR1 = (__EXTI_LINE__))
+#endif
+
+/**
+  * @brief  Generates a Software interrupt on selected EXTI line.
+  * @param  __EXTI_LINE__: specifies the EXTI line to check.
+  *          This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__))
+/**
+  * @}
+  */
+
+/* Include GPIO HAL Extension module */
+#include "stm32h7xx_hal_gpio_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup GPIO_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup GPIO_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de-initialization functions *****************************/
+void  HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init);
+void  HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin);
+/**
+  * @}
+  */
+
+/** @addtogroup GPIO_Exported_Functions_Group2
+  * @{
+  */
+/* IO operation functions *****************************************************/
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
+void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup GPIO_Private_Constants GPIO Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup GPIO_Private_Macros GPIO Private Macros
+  * @{
+  */
+#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
+#define IS_GPIO_PIN(__PIN__)        ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
+                                     (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT)              ||\
+                            ((MODE) == GPIO_MODE_OUTPUT_PP)          ||\
+                            ((MODE) == GPIO_MODE_OUTPUT_OD)          ||\
+                            ((MODE) == GPIO_MODE_AF_PP)              ||\
+                            ((MODE) == GPIO_MODE_AF_OD)              ||\
+                            ((MODE) == GPIO_MODE_IT_RISING)          ||\
+                            ((MODE) == GPIO_MODE_IT_FALLING)         ||\
+                            ((MODE) == GPIO_MODE_IT_RISING_FALLING)  ||\
+                            ((MODE) == GPIO_MODE_EVT_RISING)         ||\
+                            ((MODE) == GPIO_MODE_EVT_FALLING)        ||\
+                            ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
+                            ((MODE) == GPIO_MODE_ANALOG))
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW)  || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \
+                              ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH))
+
+#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
+                            ((PULL) == GPIO_PULLDOWN))
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup GPIO_Private_Functions GPIO Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_GPIO_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h
new file mode 100644
index 00000000..ff2efb3c
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h
@@ -0,0 +1,428 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_gpio_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of GPIO HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_GPIO_EX_H
+#define STM32H7xx_HAL_GPIO_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup GPIOEx GPIOEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants
+  * @{
+  */
+
+/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection
+  * @{
+  */
+
+/**
+  * @brief   AF 0 selection
+  */
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                                                     */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping                                          */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping                                           */
+#define GPIO_AF0_LCDBIAS       ((uint8_t)0x00)  /* LCDBIAS Alternate Function mapping                                                      */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                                                        */
+#if defined (PWR_CPUCR_PDDS_D2) /* PWR D1 and D2 domains exists */
+#define GPIO_AF0_C1DSLEEP      ((uint8_t)0x00)  /* Cortex-M7 Deep Sleep Alternate Function mapping : available on STM32H7 Rev.B and above  */
+#define GPIO_AF0_C1SLEEP       ((uint8_t)0x00)  /* Cortex-M7 Sleep Alternate Function mapping : available on STM32H7 Rev.B and above       */
+#define GPIO_AF0_D1PWREN       ((uint8_t)0x00)  /* Domain 1 PWR enable Alternate Function mapping : available on STM32H7 Rev.B and above   */
+#define GPIO_AF0_D2PWREN       ((uint8_t)0x00)  /* Domain 2 PWR enable Alternate Function mapping : available on STM32H7 Rev.B and above   */
+#if defined(DUAL_CORE)
+#define GPIO_AF0_C2DSLEEP      ((uint8_t)0x00)  /* Cortex-M4 Deep Sleep Alternate Function mapping : available on STM32H7 Rev.B and above  */
+#define GPIO_AF0_C2SLEEP       ((uint8_t)0x00)  /* Cortex-M4 Sleep Alternate Function mapping : available on STM32H7 Rev.B and above       */
+#endif /* DUAL_CORE */
+#endif /* PWR_CPUCR_PDDS_D2 */
+
+/**
+  * @brief   AF 1 selection
+  */
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping   */
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping   */
+#define GPIO_AF1_TIM16         ((uint8_t)0x01)  /* TIM16 Alternate Function mapping  */
+#define GPIO_AF1_TIM17         ((uint8_t)0x01)  /* TIM17 Alternate Function mapping  */
+#define GPIO_AF1_LPTIM1        ((uint8_t)0x01)  /* LPTIM1 Alternate Function mapping */
+#if defined(HRTIM1)
+#define GPIO_AF1_HRTIM1        ((uint8_t)0x01)  /* HRTIM1 Alternate Function mapping */
+#endif /* HRTIM1 */
+
+/**
+  * @brief   AF 2 selection
+  */
+#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping   */
+#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping   */
+#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping   */
+#define GPIO_AF2_TIM12         ((uint8_t)0x02)  /* TIM12 Alternate Function mapping  */
+#define GPIO_AF2_SAI1          ((uint8_t)0x02)  /* SAI1 Alternate Function mapping   */
+#if defined(HRTIM1)
+#define GPIO_AF2_HRTIM1        ((uint8_t)0x02)  /* HRTIM1 Alternate Function mapping */
+#endif /* HRTIM1 */
+#define GPIO_AF2_TIM15         ((uint8_t)0x02)  /* TIM15 Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx */
+
+/**
+  * @brief   AF 3 selection
+  */
+#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping   */
+#define GPIO_AF3_LPTIM2        ((uint8_t)0x03)  /* LPTIM2 Alternate Function mapping */
+#define GPIO_AF3_DFSDM1        ((uint8_t)0x03)  /* DFSDM Alternate Function mapping  */
+#define GPIO_AF3_LPTIM3        ((uint8_t)0x03)  /* LPTIM3 Alternate Function mapping */
+#define GPIO_AF3_LPTIM4        ((uint8_t)0x03)  /* LPTIM4 Alternate Function mapping */
+#define GPIO_AF3_LPTIM5        ((uint8_t)0x03)  /* LPTIM5 Alternate Function mapping */
+#define GPIO_AF3_LPUART        ((uint8_t)0x03)  /* LPUART Alternate Function mapping */
+#if defined(OCTOSPIM)
+#define GPIO_AF3_OCTOSPIM_P1   ((uint8_t)0x03)  /* OCTOSPI Manager Port 1 Alternate Function mapping */
+#define GPIO_AF3_OCTOSPIM_P2   ((uint8_t)0x03)  /* OCTOSPI Manager Port 2 Alternate Function mapping */
+#endif /* OCTOSPIM */
+#if defined(HRTIM1)
+#define GPIO_AF3_HRTIM1        ((uint8_t)0x03)  /* HRTIM1 Alternate Function mapping */
+#endif /* HRTIM1 */
+
+/**
+  * @brief   AF 4 selection
+  */
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping   */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping   */
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping   */
+#define GPIO_AF4_I2C4          ((uint8_t)0x04)  /* I2C4 Alternate Function mapping   */
+#define GPIO_AF4_TIM15         ((uint8_t)0x04)  /* TIM15 Alternate Function mapping  */
+#define GPIO_AF4_CEC           ((uint8_t)0x04)  /* CEC Alternate Function mapping    */
+#define GPIO_AF4_LPTIM2        ((uint8_t)0x04)  /* LPTIM2 Alternate Function mapping */
+#define GPIO_AF4_USART1        ((uint8_t)0x04)  /* USART1 Alternate Function mapping */
+#define GPIO_AF4_DFSDM1        ((uint8_t)0x04)  /* DFSDM  Alternate Function mapping */
+#if defined(DFSDM2_BASE)
+#define GPIO_AF4_DFSDM2        ((uint8_t)0x04)  /* DFSDM2 Alternate Function mapping */
+#endif /* DFSDM2_BASE */
+#if defined(PSSI)
+#define GPIO_AF4_PSSI          ((uint8_t)0x04)  /* PSSI Alternate Function mapping   */
+#endif /* PSSI */
+
+/**
+  * @brief   AF 5 selection
+  */
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping   */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2 Alternate Function mapping   */
+#define GPIO_AF5_SPI3          ((uint8_t)0x05)  /* SPI3 Alternate Function mapping   */
+#define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4 Alternate Function mapping   */
+#define GPIO_AF5_SPI5          ((uint8_t)0x05)  /* SPI5 Alternate Function mapping   */
+#define GPIO_AF5_SPI6          ((uint8_t)0x05)  /* SPI6 Alternate Function mapping   */
+#define GPIO_AF5_CEC           ((uint8_t)0x05)  /* CEC  Alternate Function mapping   */
+
+/**
+  * @brief   AF 6 selection
+  */
+#define GPIO_AF6_SPI2          ((uint8_t)0x06)  /* SPI2 Alternate Function mapping   */
+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3 Alternate Function mapping   */
+#define GPIO_AF6_SAI1          ((uint8_t)0x06)  /* SAI1 Alternate Function mapping   */
+#define GPIO_AF6_I2C4          ((uint8_t)0x06)  /* I2C4 Alternate Function mapping   */
+#define GPIO_AF6_DFSDM1        ((uint8_t)0x06)  /* DFSDM Alternate Function mapping  */
+#define GPIO_AF6_UART4         ((uint8_t)0x06)  /* UART4 Alternate Function mapping  */
+#if defined(DFSDM2_BASE)
+#define GPIO_AF6_DFSDM2        ((uint8_t)0x06)  /* DFSDM2 Alternate Function mapping */
+#endif /* DFSDM2_BASE */
+#if defined(SAI3)
+#define GPIO_AF6_SAI3          ((uint8_t)0x06)  /* SAI3 Alternate Function mapping   */
+#endif /* SAI3 */
+#if defined(OCTOSPIM)
+#define GPIO_AF6_OCTOSPIM_P1   ((uint8_t)0x06)  /* OCTOSPI Manager Port 1 Alternate Function mapping */
+#endif /* OCTOSPIM */
+
+/**
+  * @brief   AF 7 selection
+  */
+#define GPIO_AF7_SPI2          ((uint8_t)0x07)  /* SPI2 Alternate Function mapping   */
+#define GPIO_AF7_SPI3          ((uint8_t)0x07)  /* SPI3 Alternate Function mapping   */
+#define GPIO_AF7_SPI6          ((uint8_t)0x07)  /* SPI6 Alternate Function mapping   */
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping */
+#define GPIO_AF7_USART6        ((uint8_t)0x07)  /* USART6 Alternate Function mapping */
+#define GPIO_AF7_UART7         ((uint8_t)0x07)  /* UART7 Alternate Function mapping  */
+#define GPIO_AF7_DFSDM1        ((uint8_t)0x07)  /* DFSDM Alternate Function mapping  */
+#define GPIO_AF7_SDMMC1        ((uint8_t)0x07)  /* SDMMC1 Alternate Function mapping */
+
+/**
+  * @brief   AF 8 selection
+  */
+#define GPIO_AF8_SPI6          ((uint8_t)0x08)  /* SPI6 Alternate Function mapping   */
+#define GPIO_AF8_SAI2          ((uint8_t)0x08)  /* SAI2 Alternate Function mapping   */
+#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */
+#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */
+#define GPIO_AF8_UART8         ((uint8_t)0x08)  /* UART8 Alternate Function mapping  */
+#define GPIO_AF8_SPDIF         ((uint8_t)0x08)  /* SPDIF Alternate Function mapping  */
+#define GPIO_AF8_LPUART        ((uint8_t)0x08)  /* LPUART Alternate Function mapping */
+#define GPIO_AF8_SDMMC1        ((uint8_t)0x08)  /* SDMMC1 Alternate Function mapping */
+#if defined(SAI4)
+#define GPIO_AF8_SAI4          ((uint8_t)0x08)  /* SAI4 Alternate Function mapping   */
+#endif /* SAI4 */
+
+/**
+  * @brief   AF 9 selection
+  */
+#define GPIO_AF9_FDCAN1        ((uint8_t)0x09)  /* FDCAN1 Alternate Function mapping   */
+#define GPIO_AF9_FDCAN2        ((uint8_t)0x09)  /* FDCAN2 Alternate Function mapping   */
+#define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping    */
+#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping    */
+#define GPIO_AF9_SDMMC2        ((uint8_t)0x09)  /* SDMMC2 Alternate Function mapping   */
+#define GPIO_AF9_LTDC          ((uint8_t)0x09)  /* LTDC Alternate Function mapping     */
+#define GPIO_AF9_SPDIF         ((uint8_t)0x09)  /* SPDIF Alternate Function mapping    */
+#define GPIO_AF9_FMC           ((uint8_t)0x09)  /* FMC Alternate Function mapping      */
+#if defined(QUADSPI)
+#define GPIO_AF9_QUADSPI       ((uint8_t)0x09)  /* QUADSPI Alternate Function mapping  */
+#endif /* QUADSPI */
+#if defined(SAI4)
+#define GPIO_AF9_SAI4          ((uint8_t)0x09)  /* SAI4 Alternate Function mapping     */
+#endif /* SAI4 */
+#if defined(OCTOSPIM)
+#define GPIO_AF9_OCTOSPIM_P1   ((uint8_t)0x09)  /* OCTOSPI Manager Port 1 Alternate Function mapping */
+#define GPIO_AF9_OCTOSPIM_P2   ((uint8_t)0x09)  /* OCTOSPI Manager Port 2 Alternate Function mapping */
+#endif /* OCTOSPIM */
+
+/**
+  * @brief   AF 10 selection
+  */
+#define GPIO_AF10_SAI2          ((uint8_t)0x0A)  /* SAI2 Alternate Function mapping                                             */
+#define GPIO_AF10_SDMMC2        ((uint8_t)0x0A)  /* SDMMC2 Alternate Function mapping                                           */
+#if defined(USB2_OTG_FS)
+#define GPIO_AF10_OTG2_FS       ((uint8_t)0x0A)  /* OTG2_FS Alternate Function mapping                                          */
+#endif /*USB2_OTG_FS*/
+#define GPIO_AF10_COMP1         ((uint8_t)0x0A)  /* COMP1 Alternate Function mapping                                            */
+#define GPIO_AF10_COMP2         ((uint8_t)0x0A)  /* COMP2 Alternate Function mapping                                            */
+#if defined(LTDC)
+#define GPIO_AF10_LTDC          ((uint8_t)0x0A)  /* LTDC Alternate Function mapping                                             */
+#endif /*LTDC*/
+#define GPIO_AF10_CRS_SYNC      ((uint8_t)0x0A)  /* CRS Sync Alternate Function mapping : available on STM32H7 Rev.B and above  */
+#if defined(QUADSPI)
+#define GPIO_AF10_QUADSPI       ((uint8_t)0x0A)  /* QUADSPI Alternate Function mapping                                          */
+#endif /* QUADSPI */
+#if defined(SAI4)
+#define GPIO_AF10_SAI4          ((uint8_t)0x0A)  /* SAI4 Alternate Function mapping                                             */
+#endif /* SAI4 */
+#if !defined(USB2_OTG_FS)
+#define GPIO_AF10_OTG1_FS       ((uint8_t)0x0A)  /* OTG1_FS Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx */
+#endif /* !USB2_OTG_FS */
+#define GPIO_AF10_OTG1_HS       ((uint8_t)0x0A)  /* OTG1_HS Alternate Function mapping                                          */
+#if defined(OCTOSPIM)
+#define GPIO_AF10_OCTOSPIM_P1   ((uint8_t)0x0A)  /* OCTOSPI Manager Port 1 Alternate Function mapping */
+#endif /* OCTOSPIM */
+#define GPIO_AF10_TIM8          ((uint8_t)0x0A)  /* TIM8 Alternate Function mapping                                             */
+
+/**
+  * @brief   AF 11 selection
+  */
+#define GPIO_AF11_SWP           ((uint8_t)0x0B)  /* SWP Alternate Function mapping     */
+#define GPIO_AF11_MDIOS         ((uint8_t)0x0B)  /* MDIOS Alternate Function mapping   */
+#define GPIO_AF11_UART7         ((uint8_t)0x0B)  /* UART7 Alternate Function mapping   */
+#define GPIO_AF11_SDMMC2        ((uint8_t)0x0B)  /* SDMMC2 Alternate Function mapping  */
+#define GPIO_AF11_DFSDM1        ((uint8_t)0x0B)  /* DFSDM1 Alternate Function mapping  */
+#define GPIO_AF11_COMP1         ((uint8_t)0x0B)  /* COMP1 Alternate Function mapping   */
+#define GPIO_AF11_COMP2         ((uint8_t)0x0B)  /* COMP2 Alternate Function mapping   */
+#define GPIO_AF11_TIM1          ((uint8_t)0x0B)  /* TIM1 Alternate Function mapping    */
+#define GPIO_AF11_TIM8          ((uint8_t)0x0B)  /* TIM8 Alternate Function mapping    */
+#define GPIO_AF11_I2C4          ((uint8_t)0x0B)  /* I2C4 Alternate Function mapping    */
+#if defined(DFSDM2_BASE)
+#define GPIO_AF11_DFSDM2        ((uint8_t)0x0B)  /* DFSDM2 Alternate Function mapping  */
+#endif /* DFSDM2_BASE */
+#if defined(USART10)
+#define GPIO_AF11_USART10       ((uint8_t)0x0B)  /* USART10 Alternate Function mapping */
+#endif /* USART10 */
+#if defined(UART9)
+#define GPIO_AF11_UART9         ((uint8_t)0x0B)  /* UART9 Alternate Function mapping   */
+#endif /* UART9 */
+#if defined(ETH)
+#define GPIO_AF11_ETH           ((uint8_t)0x0B)  /* ETH Alternate Function mapping     */
+#endif /* ETH */
+#if defined(LTDC)
+#define GPIO_AF11_LTDC          ((uint8_t)0x0B)  /* LTDC Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx  */
+#endif /*LTDC*/
+#if defined(OCTOSPIM)
+#define GPIO_AF11_OCTOSPIM_P1   ((uint8_t)0x0B)  /* OCTOSPI Manager Port 1 Alternate Function mapping */
+#endif /* OCTOSPIM */
+
+/**
+  * @brief   AF 12 selection
+  */
+#define GPIO_AF12_FMC           ((uint8_t)0x0C)  /* FMC Alternate Function mapping     */
+#define GPIO_AF12_SDMMC1        ((uint8_t)0x0C)  /* SDMMC1 Alternate Function mapping  */
+#define GPIO_AF12_MDIOS         ((uint8_t)0x0C)  /* MDIOS Alternate Function mapping   */
+#define GPIO_AF12_COMP1         ((uint8_t)0x0C)  /* COMP1 Alternate Function mapping   */
+#define GPIO_AF12_COMP2         ((uint8_t)0x0C)  /* COMP2 Alternate Function mapping   */
+#define GPIO_AF12_TIM1          ((uint8_t)0x0C)  /* TIM1 Alternate Function mapping    */
+#define GPIO_AF12_TIM8          ((uint8_t)0x0C)  /* TIM8 Alternate Function mapping    */
+#if defined(LTDC)
+#define GPIO_AF12_LTDC          ((uint8_t)0x0C)  /* LTDC Alternate Function mapping    */
+#endif /*LTDC*/
+#if defined(USB2_OTG_FS)
+#define GPIO_AF12_OTG1_FS       ((uint8_t)0x0C)  /* OTG1_FS Alternate Function mapping */
+#endif /* USB2_OTG_FS */
+
+/**
+  * @brief   AF 13 selection
+  */
+#define GPIO_AF13_DCMI          ((uint8_t)0x0D)   /* DCMI Alternate Function mapping  */
+#define GPIO_AF13_COMP1         ((uint8_t)0x0D)   /* COMP1 Alternate Function mapping */
+#define GPIO_AF13_COMP2         ((uint8_t)0x0D)   /* COMP2 Alternate Function mapping */
+#if defined(LTDC)
+#define GPIO_AF13_LTDC          ((uint8_t)0x0D)   /* LTDC Alternate Function mapping  */
+#endif /*LTDC*/
+#if defined(DSI)
+#define GPIO_AF13_DSI           ((uint8_t)0x0D)   /* DSI Alternate Function mapping   */
+#endif /* DSI */
+#if defined(PSSI)
+#define GPIO_AF13_PSSI          ((uint8_t)0x0D)   /* PSSI Alternate Function mapping  */
+#endif /* PSSI */
+#define GPIO_AF13_TIM1          ((uint8_t)0x0D)    /* TIM1 Alternate Function mapping */
+
+/**
+  * @brief   AF 14 selection
+  */
+#define GPIO_AF14_LTDC         ((uint8_t)0x0E)   /* LTDC Alternate Function mapping  */
+#define GPIO_AF14_UART5        ((uint8_t)0x0E)   /* UART5 Alternate Function mapping */
+
+/**
+  * @brief   AF 15 selection
+  */
+#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF)   ((AF) <= (uint8_t)0x0F)
+
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros
+  * @{
+  */
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions
+  * @{
+  */
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup GPIOEx_Private_Constants GPIO Private Constants
+  * @{
+  */
+
+/**
+  * @brief   GPIO pin available on the platform
+  */
+/* Defines the available pins per GPIOs */
+#define GPIOA_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOB_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOC_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOD_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOE_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOF_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOG_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOI_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOJ_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOH_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOK_PIN_AVAILABLE  (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | \
+                              GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7)
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup GPIOEx_Private_Macros GPIO Private Macros
+  * @{
+  */
+/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index
+  * @{
+  */
+#define GPIO_GET_INDEX(__GPIOx__)  (((__GPIOx__) == (GPIOA))? 0UL :\
+                                    ((__GPIOx__) == (GPIOB))? 1UL :\
+                                    ((__GPIOx__) == (GPIOC))? 2UL :\
+                                    ((__GPIOx__) == (GPIOD))? 3UL :\
+                                    ((__GPIOx__) == (GPIOE))? 4UL :\
+                                    ((__GPIOx__) == (GPIOF))? 5UL :\
+                                    ((__GPIOx__) == (GPIOG))? 6UL :\
+                                    ((__GPIOx__) == (GPIOH))? 7UL :\
+                                    ((__GPIOx__) == (GPIOI))? 8UL :\
+                                    ((__GPIOx__) == (GPIOJ))? 9UL : 10UL)
+/**
+  * @}
+  */
+
+/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function
+  * @{
+  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup GPIOEx_Private_Functions GPIO Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_GPIO_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h
new file mode 100644
index 00000000..1ef97f3d
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h
@@ -0,0 +1,214 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_hsem.h
+  * @author  MCD Application Team
+  * @brief   Header file of HSEM HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_HSEM_H
+#define STM32H7xx_HAL_HSEM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+   * @{
+   */
+
+/** @addtogroup HSEM
+   * @{
+   */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup HSEM_Exported_Macros HSEM Exported Macros
+  * @{
+  */
+
+/**
+  * @brief  SemID to mask helper Macro.
+  * @param  __SEMID__: semaphore ID from 0 to 31
+  * @retval Semaphore Mask.
+  */
+#define __HAL_HSEM_SEMID_TO_MASK(__SEMID__) (1 << (__SEMID__))
+
+/**
+  * @brief  Enables the specified HSEM interrupts.
+  * @param  __SEM_MASK__: semaphores Mask
+  * @retval None.
+  */
+#if defined(DUAL_CORE)
+#define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
+                                            (HSEM->C1IER |= (__SEM_MASK__)) : \
+                                            (HSEM->C2IER |= (__SEM_MASK__)))
+#else
+#define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) (HSEM->IER |= (__SEM_MASK__))
+#endif /* DUAL_CORE */
+/**
+  * @brief  Disables the specified HSEM interrupts.
+  * @param  __SEM_MASK__: semaphores Mask
+  * @retval None.
+  */
+#if defined(DUAL_CORE)
+#define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
+                                             (HSEM->C1IER &= ~(__SEM_MASK__)) :       \
+                                             (HSEM->C2IER &= ~(__SEM_MASK__)))
+#else
+#define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) (HSEM->IER &= ~(__SEM_MASK__))
+#endif /* DUAL_CORE */
+
+/**
+  * @brief  Checks whether interrupt has occurred or not for semaphores specified by a mask.
+  * @param  __SEM_MASK__: semaphores Mask
+  * @retval semaphores Mask : Semaphores where an interrupt occurred.
+  */
+#if defined(DUAL_CORE)
+#define __HAL_HSEM_GET_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
+                                         ((__SEM_MASK__) & HSEM->C1MISR) :        \
+                                         ((__SEM_MASK__) & HSEM->C2MISR1))
+#else
+#define __HAL_HSEM_GET_IT(__SEM_MASK__) ((__SEM_MASK__) & HSEM->MISR)
+#endif /* DUAL_CORE */
+
+/**
+  * @brief  Get the semaphores release status flags.
+  * @param  __SEM_MASK__: semaphores Mask
+  * @retval semaphores Mask : Semaphores where Release flags rise.
+  */
+#if defined(DUAL_CORE)
+#define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
+                                           (__SEM_MASK__) & HSEM->C1ISR :           \
+                                           (__SEM_MASK__) & HSEM->C2ISR)
+#else
+#define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((__SEM_MASK__) & HSEM->ISR)
+#endif /* DUAL_CORE */
+
+/**
+  * @brief  Clears the HSEM Interrupt flags.
+  * @param  __SEM_MASK__: semaphores Mask
+  * @retval None.
+  */
+#if defined(DUAL_CORE)
+#define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
+                                             (HSEM->C1ICR |= (__SEM_MASK__)) :        \
+                                             (HSEM->C2ICR |= (__SEM_MASK__)))
+#else
+#define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) (HSEM->ICR |= (__SEM_MASK__))
+#endif /* DUAL_CORE */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup HSEM_Exported_Functions HSEM Exported Functions
+  * @{
+  */
+
+/** @addtogroup HSEM_Exported_Functions_Group1 Take and Release functions
+  * @brief    HSEM Take and Release functions
+  * @{
+  */
+
+/* HSEM semaphore take (lock) using 2-Step  method ****************************/
+HAL_StatusTypeDef  HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID);
+/* HSEM semaphore fast take (lock) using 1-Step  method ***********************/
+HAL_StatusTypeDef  HAL_HSEM_FastTake(uint32_t SemID);
+/* HSEM Check semaphore state Taken or not   **********************************/
+uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID);
+/* HSEM Release  **************************************************************/
+void  HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID);
+/* HSEM Release All************************************************************/
+void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t CoreID);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HSEM_Exported_Functions_Group2 HSEM Set and Get Key functions
+  * @brief    HSEM Set and Get Key functions.
+  * @{
+  */
+/* HSEM Set Clear Key *********************************************************/
+void  HAL_HSEM_SetClearKey(uint32_t Key);
+/* HSEM Get Clear Key *********************************************************/
+uint32_t HAL_HSEM_GetClearKey(void);
+/**
+  * @}
+  */
+
+/** @addtogroup HSEM_Exported_Functions_Group3
+  * @brief   HSEM Notification functions
+  * @{
+  */
+/* HSEM Activate HSEM Notification (When a semaphore is released) ) *****************/
+void HAL_HSEM_ActivateNotification(uint32_t SemMask);
+/* HSEM Deactivate HSEM Notification (When a semaphore is released)  ****************/
+void HAL_HSEM_DeactivateNotification(uint32_t SemMask);
+/* HSEM Free Callback (When a semaphore is released)  *******************************/
+void HAL_HSEM_FreeCallback(uint32_t SemMask);
+/* HSEM IRQ Handler  **********************************************************/
+void HAL_HSEM_IRQHandler(void);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup HSEM_Private_Macros HSEM Private Macros
+  * @{
+  */
+
+#define IS_HSEM_SEMID(__SEMID__) ((__SEMID__) <= HSEM_SEMID_MAX )
+
+#define IS_HSEM_PROCESSID(__PROCESSID__) ((__PROCESSID__) <= HSEM_PROCESSID_MAX )
+
+#define IS_HSEM_KEY(__KEY__) ((__KEY__) <= HSEM_CLEAR_KEY_MAX )
+
+#if defined(DUAL_CORE)
+#define IS_HSEM_COREID(__COREID__) (((__COREID__) == HSEM_CPU1_COREID) || \
+                                    ((__COREID__) == HSEM_CPU2_COREID))
+#else
+#define IS_HSEM_COREID(__COREID__) ((__COREID__) == HSEM_CPU1_COREID)
+#endif
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_HSEM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h
new file mode 100644
index 00000000..ea2cd885
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h
@@ -0,0 +1,782 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_i2c.h
+  * @author  MCD Application Team
+  * @brief   Header file of I2C HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_I2C_H
+#define STM32H7xx_HAL_I2C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup I2C
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup I2C_Exported_Types I2C Exported Types
+  * @{
+  */
+
+/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
+  * @brief  I2C Configuration Structure definition
+  * @{
+  */
+typedef struct
+{
+  uint32_t Timing;              /*!< Specifies the I2C_TIMINGR_register value.
+                                  This parameter calculated by referring to I2C initialization
+                                         section in Reference manual */
+
+  uint32_t OwnAddress1;         /*!< Specifies the first device own address.
+                                  This parameter can be a 7-bit or 10-bit address. */
+
+  uint32_t AddressingMode;      /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
+                                  This parameter can be a value of @ref I2C_ADDRESSING_MODE */
+
+  uint32_t DualAddressMode;     /*!< Specifies if dual addressing mode is selected.
+                                  This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
+
+  uint32_t OwnAddress2;         /*!< Specifies the second device own address if dual addressing mode is selected
+                                  This parameter can be a 7-bit address. */
+
+  uint32_t OwnAddress2Masks;    /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
+                                  This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
+
+  uint32_t GeneralCallMode;     /*!< Specifies if general call mode is selected.
+                                  This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
+
+  uint32_t NoStretchMode;       /*!< Specifies if nostretch mode is selected.
+                                  This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
+
+} I2C_InitTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_state_structure_definition HAL state structure definition
+  * @brief  HAL State structure definition
+  * @note  HAL I2C State value coding follow below described bitmap :\n
+  *          b7-b6  Error information\n
+  *             00 : No Error\n
+  *             01 : Abort (Abort user request on going)\n
+  *             10 : Timeout\n
+  *             11 : Error\n
+  *          b5     Peripheral initialization status\n
+  *             0  : Reset (peripheral not initialized)\n
+  *             1  : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n
+  *          b4     (not used)\n
+  *             x  : Should be set to 0\n
+  *          b3\n
+  *             0  : Ready or Busy (No Listen mode ongoing)\n
+  *             1  : Listen (peripheral in Address Listen Mode)\n
+  *          b2     Intrinsic process state\n
+  *             0  : Ready\n
+  *             1  : Busy (peripheral busy with some configuration or internal operations)\n
+  *          b1     Rx state\n
+  *             0  : Ready (no Rx operation ongoing)\n
+  *             1  : Busy (Rx operation ongoing)\n
+  *          b0     Tx state\n
+  *             0  : Ready (no Tx operation ongoing)\n
+  *             1  : Busy (Tx operation ongoing)
+  * @{
+  */
+typedef enum
+{
+  HAL_I2C_STATE_RESET             = 0x00U,   /*!< Peripheral is not yet Initialized         */
+  HAL_I2C_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use  */
+  HAL_I2C_STATE_BUSY              = 0x24U,   /*!< An internal process is ongoing            */
+  HAL_I2C_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing      */
+  HAL_I2C_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing         */
+  HAL_I2C_STATE_LISTEN            = 0x28U,   /*!< Address Listen Mode is ongoing            */
+  HAL_I2C_STATE_BUSY_TX_LISTEN    = 0x29U,   /*!< Address Listen Mode and Data Transmission
+                                                 process is ongoing                         */
+  HAL_I2C_STATE_BUSY_RX_LISTEN    = 0x2AU,   /*!< Address Listen Mode and Data Reception
+                                                 process is ongoing                         */
+  HAL_I2C_STATE_ABORT             = 0x60U,   /*!< Abort user request ongoing                */
+  HAL_I2C_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state                             */
+  HAL_I2C_STATE_ERROR             = 0xE0U    /*!< Error                                     */
+
+} HAL_I2C_StateTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_mode_structure_definition HAL mode structure definition
+  * @brief  HAL Mode structure definition
+  * @note  HAL I2C Mode value coding follow below described bitmap :\n
+  *          b7     (not used)\n
+  *             x  : Should be set to 0\n
+  *          b6\n
+  *             0  : None\n
+  *             1  : Memory (HAL I2C communication is in Memory Mode)\n
+  *          b5\n
+  *             0  : None\n
+  *             1  : Slave (HAL I2C communication is in Slave Mode)\n
+  *          b4\n
+  *             0  : None\n
+  *             1  : Master (HAL I2C communication is in Master Mode)\n
+  *          b3-b2-b1-b0  (not used)\n
+  *             xxxx : Should be set to 0000
+  * @{
+  */
+typedef enum
+{
+  HAL_I2C_MODE_NONE               = 0x00U,   /*!< No I2C communication on going             */
+  HAL_I2C_MODE_MASTER             = 0x10U,   /*!< I2C communication is in Master Mode       */
+  HAL_I2C_MODE_SLAVE              = 0x20U,   /*!< I2C communication is in Slave Mode        */
+  HAL_I2C_MODE_MEM                = 0x40U    /*!< I2C communication is in Memory Mode       */
+
+} HAL_I2C_ModeTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Error_Code_definition I2C Error Code definition
+  * @brief  I2C Error Code definition
+  * @{
+  */
+#define HAL_I2C_ERROR_NONE      (0x00000000U)    /*!< No error              */
+#define HAL_I2C_ERROR_BERR      (0x00000001U)    /*!< BERR error            */
+#define HAL_I2C_ERROR_ARLO      (0x00000002U)    /*!< ARLO error            */
+#define HAL_I2C_ERROR_AF        (0x00000004U)    /*!< ACKF error            */
+#define HAL_I2C_ERROR_OVR       (0x00000008U)    /*!< OVR error             */
+#define HAL_I2C_ERROR_DMA       (0x00000010U)    /*!< DMA transfer error    */
+#define HAL_I2C_ERROR_TIMEOUT   (0x00000020U)    /*!< Timeout error         */
+#define HAL_I2C_ERROR_SIZE      (0x00000040U)    /*!< Size Management error */
+#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U)    /*!< DMA Parameter Error   */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+#define HAL_I2C_ERROR_INVALID_CALLBACK  (0x00000100U)    /*!< Invalid Callback error */
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+#define HAL_I2C_ERROR_INVALID_PARAM     (0x00000200U)    /*!< Invalid Parameters error  */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
+  * @brief  I2C handle Structure definition
+  * @{
+  */
+typedef struct __I2C_HandleTypeDef
+{
+  I2C_TypeDef                *Instance;      /*!< I2C registers base address                */
+
+  I2C_InitTypeDef            Init;           /*!< I2C communication parameters              */
+
+  uint8_t                    *pBuffPtr;      /*!< Pointer to I2C transfer buffer            */
+
+  uint16_t                   XferSize;       /*!< I2C transfer size                         */
+
+  __IO uint16_t              XferCount;      /*!< I2C transfer counter                      */
+
+  __IO uint32_t              XferOptions;    /*!< I2C sequantial transfer options, this parameter can
+                                                  be a value of @ref I2C_XFEROPTIONS */
+
+  __IO uint32_t              PreviousState;  /*!< I2C communication Previous state          */
+
+  HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);  /*!< I2C transfer IRQ handler function pointer */
+
+  DMA_HandleTypeDef          *hdmatx;        /*!< I2C Tx DMA handle parameters              */
+
+  DMA_HandleTypeDef          *hdmarx;        /*!< I2C Rx DMA handle parameters              */
+
+  HAL_LockTypeDef            Lock;           /*!< I2C locking object                        */
+
+  __IO HAL_I2C_StateTypeDef  State;          /*!< I2C communication state                   */
+
+  __IO HAL_I2C_ModeTypeDef   Mode;           /*!< I2C communication mode                    */
+
+  __IO uint32_t              ErrorCode;      /*!< I2C Error code                            */
+
+  __IO uint32_t              AddrEventCount; /*!< I2C Address Event counter                 */
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+  void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);           /*!< I2C Master Tx Transfer completed callback */
+  void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);           /*!< I2C Master Rx Transfer completed callback */
+  void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);            /*!< I2C Slave Tx Transfer completed callback  */
+  void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);            /*!< I2C Slave Rx Transfer completed callback  */
+  void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);             /*!< I2C Listen Complete callback              */
+  void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Memory Tx Transfer completed callback */
+  void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Memory Rx Transfer completed callback */
+  void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);                  /*!< I2C Error callback                        */
+  void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Abort callback                        */
+
+  void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);  /*!< I2C Slave Address Match callback */
+
+  void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);                /*!< I2C Msp Init callback                     */
+  void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Msp DeInit callback                   */
+
+#endif  /* USE_HAL_I2C_REGISTER_CALLBACKS */
+} I2C_HandleTypeDef;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL I2C Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_I2C_MASTER_TX_COMPLETE_CB_ID      = 0x00U,    /*!< I2C Master Tx Transfer completed callback ID  */
+  HAL_I2C_MASTER_RX_COMPLETE_CB_ID      = 0x01U,    /*!< I2C Master Rx Transfer completed callback ID  */
+  HAL_I2C_SLAVE_TX_COMPLETE_CB_ID       = 0x02U,    /*!< I2C Slave Tx Transfer completed callback ID   */
+  HAL_I2C_SLAVE_RX_COMPLETE_CB_ID       = 0x03U,    /*!< I2C Slave Rx Transfer completed callback ID   */
+  HAL_I2C_LISTEN_COMPLETE_CB_ID         = 0x04U,    /*!< I2C Listen Complete callback ID               */
+  HAL_I2C_MEM_TX_COMPLETE_CB_ID         = 0x05U,    /*!< I2C Memory Tx Transfer callback ID            */
+  HAL_I2C_MEM_RX_COMPLETE_CB_ID         = 0x06U,    /*!< I2C Memory Rx Transfer completed callback ID  */
+  HAL_I2C_ERROR_CB_ID                   = 0x07U,    /*!< I2C Error callback ID                         */
+  HAL_I2C_ABORT_CB_ID                   = 0x08U,    /*!< I2C Abort callback ID                         */
+
+  HAL_I2C_MSPINIT_CB_ID                 = 0x09U,    /*!< I2C Msp Init callback ID                      */
+  HAL_I2C_MSPDEINIT_CB_ID               = 0x0AU     /*!< I2C Msp DeInit callback ID                    */
+
+} HAL_I2C_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL I2C Callback pointer definition
+  */
+typedef  void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */
+typedef  void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */
+
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Constants I2C Exported Constants
+  * @{
+  */
+
+/** @defgroup I2C_XFEROPTIONS  I2C Sequential Transfer Options
+  * @{
+  */
+#define I2C_FIRST_FRAME                 ((uint32_t)I2C_SOFTEND_MODE)
+#define I2C_FIRST_AND_NEXT_FRAME        ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
+#define I2C_NEXT_FRAME                  ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
+#define I2C_FIRST_AND_LAST_FRAME        ((uint32_t)I2C_AUTOEND_MODE)
+#define I2C_LAST_FRAME                  ((uint32_t)I2C_AUTOEND_MODE)
+#define I2C_LAST_FRAME_NO_STOP          ((uint32_t)I2C_SOFTEND_MODE)
+
+/* List of XferOptions in usage of :
+ * 1- Restart condition in all use cases (direction change or not)
+ */
+#define  I2C_OTHER_FRAME                (0x000000AAU)
+#define  I2C_OTHER_AND_LAST_FRAME       (0x0000AA00U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
+  * @{
+  */
+#define I2C_ADDRESSINGMODE_7BIT         (0x00000001U)
+#define I2C_ADDRESSINGMODE_10BIT        (0x00000002U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
+  * @{
+  */
+#define I2C_DUALADDRESS_DISABLE         (0x00000000U)
+#define I2C_DUALADDRESS_ENABLE          I2C_OAR2_OA2EN
+/**
+  * @}
+  */
+
+/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
+  * @{
+  */
+#define I2C_OA2_NOMASK                  ((uint8_t)0x00U)
+#define I2C_OA2_MASK01                  ((uint8_t)0x01U)
+#define I2C_OA2_MASK02                  ((uint8_t)0x02U)
+#define I2C_OA2_MASK03                  ((uint8_t)0x03U)
+#define I2C_OA2_MASK04                  ((uint8_t)0x04U)
+#define I2C_OA2_MASK05                  ((uint8_t)0x05U)
+#define I2C_OA2_MASK06                  ((uint8_t)0x06U)
+#define I2C_OA2_MASK07                  ((uint8_t)0x07U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
+  * @{
+  */
+#define I2C_GENERALCALL_DISABLE         (0x00000000U)
+#define I2C_GENERALCALL_ENABLE          I2C_CR1_GCEN
+/**
+  * @}
+  */
+
+/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
+  * @{
+  */
+#define I2C_NOSTRETCH_DISABLE           (0x00000000U)
+#define I2C_NOSTRETCH_ENABLE            I2C_CR1_NOSTRETCH
+/**
+  * @}
+  */
+
+/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
+  * @{
+  */
+#define I2C_MEMADD_SIZE_8BIT            (0x00000001U)
+#define I2C_MEMADD_SIZE_16BIT           (0x00000002U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
+  * @{
+  */
+#define I2C_DIRECTION_TRANSMIT          (0x00000000U)
+#define I2C_DIRECTION_RECEIVE           (0x00000001U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
+  * @{
+  */
+#define  I2C_RELOAD_MODE                I2C_CR2_RELOAD
+#define  I2C_AUTOEND_MODE               I2C_CR2_AUTOEND
+#define  I2C_SOFTEND_MODE               (0x00000000U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
+  * @{
+  */
+#define  I2C_NO_STARTSTOP               (0x00000000U)
+#define  I2C_GENERATE_STOP              (uint32_t)(0x80000000U | I2C_CR2_STOP)
+#define  I2C_GENERATE_START_READ        (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
+#define  I2C_GENERATE_START_WRITE       (uint32_t)(0x80000000U | I2C_CR2_START)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
+  * @brief I2C Interrupt definition
+  *        Elements values convention: 0xXXXXXXXX
+  *           - XXXXXXXX  : Interrupt control mask
+  * @{
+  */
+#define I2C_IT_ERRI                     I2C_CR1_ERRIE
+#define I2C_IT_TCI                      I2C_CR1_TCIE
+#define I2C_IT_STOPI                    I2C_CR1_STOPIE
+#define I2C_IT_NACKI                    I2C_CR1_NACKIE
+#define I2C_IT_ADDRI                    I2C_CR1_ADDRIE
+#define I2C_IT_RXI                      I2C_CR1_RXIE
+#define I2C_IT_TXI                      I2C_CR1_TXIE
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Flag_definition I2C Flag definition
+  * @{
+  */
+#define I2C_FLAG_TXE                    I2C_ISR_TXE
+#define I2C_FLAG_TXIS                   I2C_ISR_TXIS
+#define I2C_FLAG_RXNE                   I2C_ISR_RXNE
+#define I2C_FLAG_ADDR                   I2C_ISR_ADDR
+#define I2C_FLAG_AF                     I2C_ISR_NACKF
+#define I2C_FLAG_STOPF                  I2C_ISR_STOPF
+#define I2C_FLAG_TC                     I2C_ISR_TC
+#define I2C_FLAG_TCR                    I2C_ISR_TCR
+#define I2C_FLAG_BERR                   I2C_ISR_BERR
+#define I2C_FLAG_ARLO                   I2C_ISR_ARLO
+#define I2C_FLAG_OVR                    I2C_ISR_OVR
+#define I2C_FLAG_PECERR                 I2C_ISR_PECERR
+#define I2C_FLAG_TIMEOUT                I2C_ISR_TIMEOUT
+#define I2C_FLAG_ALERT                  I2C_ISR_ALERT
+#define I2C_FLAG_BUSY                   I2C_ISR_BUSY
+#define I2C_FLAG_DIR                    I2C_ISR_DIR
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Macros I2C Exported Macros
+  * @{
+  */
+
+/** @brief Reset I2C handle state.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                do{                                                   \
+                                                                    (__HANDLE__)->State = HAL_I2C_STATE_RESET;       \
+                                                                    (__HANDLE__)->MspInitCallback = NULL;            \
+                                                                    (__HANDLE__)->MspDeInitCallback = NULL;          \
+                                                                  } while(0)
+#else
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
+#endif
+
+/** @brief  Enable the specified I2C interrupt.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __INTERRUPT__ specifies the interrupt source to enable.
+  *        This parameter can be one of the following values:
+  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
+  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
+  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
+  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
+  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
+  *            @arg @ref I2C_IT_RXI   RX interrupt enable
+  *            @arg @ref I2C_IT_TXI   TX interrupt enable
+  *
+  * @retval None
+  */
+#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)          ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
+
+/** @brief  Disable the specified I2C interrupt.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __INTERRUPT__ specifies the interrupt source to disable.
+  *        This parameter can be one of the following values:
+  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
+  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
+  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
+  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
+  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
+  *            @arg @ref I2C_IT_RXI   RX interrupt enable
+  *            @arg @ref I2C_IT_TXI   TX interrupt enable
+  *
+  * @retval None
+  */
+#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
+
+/** @brief  Check whether the specified I2C interrupt source is enabled or not.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __INTERRUPT__ specifies the I2C interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
+  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
+  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
+  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
+  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
+  *            @arg @ref I2C_IT_RXI   RX interrupt enable
+  *            @arg @ref I2C_IT_TXI   TX interrupt enable
+  *
+  * @retval The new state of __INTERRUPT__ (SET or RESET).
+  */
+#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)      ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief  Check whether the specified I2C flag is set or not.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg @ref I2C_FLAG_TXE     Transmit data register empty
+  *            @arg @ref I2C_FLAG_TXIS    Transmit interrupt status
+  *            @arg @ref I2C_FLAG_RXNE    Receive data register not empty
+  *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)
+  *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag
+  *            @arg @ref I2C_FLAG_STOPF   STOP detection flag
+  *            @arg @ref I2C_FLAG_TC      Transfer complete (master mode)
+  *            @arg @ref I2C_FLAG_TCR     Transfer complete reload
+  *            @arg @ref I2C_FLAG_BERR    Bus error
+  *            @arg @ref I2C_FLAG_ARLO    Arbitration lost
+  *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun
+  *            @arg @ref I2C_FLAG_PECERR  PEC error in reception
+  *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
+  *            @arg @ref I2C_FLAG_ALERT   SMBus alert
+  *            @arg @ref I2C_FLAG_BUSY    Bus busy
+  *            @arg @ref I2C_FLAG_DIR     Transfer direction (slave mode)
+  *
+  * @retval The new state of __FLAG__ (SET or RESET).
+  */
+#define I2C_FLAG_MASK  (0x0001FFFFU)
+#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+
+/** @brief  Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __FLAG__ specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg @ref I2C_FLAG_TXE     Transmit data register empty
+  *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)
+  *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag
+  *            @arg @ref I2C_FLAG_STOPF   STOP detection flag
+  *            @arg @ref I2C_FLAG_BERR    Bus error
+  *            @arg @ref I2C_FLAG_ARLO    Arbitration lost
+  *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun
+  *            @arg @ref I2C_FLAG_PECERR  PEC error in reception
+  *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
+  *            @arg @ref I2C_FLAG_ALERT   SMBus alert
+  *
+  * @retval None
+  */
+#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
+                                                                                 : ((__HANDLE__)->Instance->ICR = (__FLAG__)))
+
+/** @brief  Enable the specified I2C peripheral.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#define __HAL_I2C_ENABLE(__HANDLE__)                            (SET_BIT((__HANDLE__)->Instance->CR1,  I2C_CR1_PE))
+
+/** @brief  Disable the specified I2C peripheral.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#define __HAL_I2C_DISABLE(__HANDLE__)                           (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
+
+/** @brief  Generate a Non-Acknowledge I2C peripheral in Slave mode.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#define __HAL_I2C_GENERATE_NACK(__HANDLE__)                     (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
+/**
+  * @}
+  */
+
+/* Include I2C HAL Extended module */
+#include "stm32h7xx_hal_i2c_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2C_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+/* Initialization and de-initialization functions******************************/
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
+  * @{
+  */
+/* IO operation functions  ****************************************************/
+/******* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
+
+/******* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
+
+/******* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
+void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
+  * @{
+  */
+/* Peripheral State, Mode and Error functions  *********************************/
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
+HAL_I2C_ModeTypeDef  HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
+uint32_t             HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Constants I2C Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2C_Private_Macro I2C Private Macros
+  * @{
+  */
+
+#define IS_I2C_ADDRESSING_MODE(MODE)    (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
+                                         ((MODE) == I2C_ADDRESSINGMODE_10BIT))
+
+#define IS_I2C_DUAL_ADDRESS(ADDRESS)    (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
+                                         ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
+
+#define IS_I2C_OWN_ADDRESS2_MASK(MASK)  (((MASK) == I2C_OA2_NOMASK)  || \
+                                         ((MASK) == I2C_OA2_MASK01) || \
+                                         ((MASK) == I2C_OA2_MASK02) || \
+                                         ((MASK) == I2C_OA2_MASK03) || \
+                                         ((MASK) == I2C_OA2_MASK04) || \
+                                         ((MASK) == I2C_OA2_MASK05) || \
+                                         ((MASK) == I2C_OA2_MASK06) || \
+                                         ((MASK) == I2C_OA2_MASK07))
+
+#define IS_I2C_GENERAL_CALL(CALL)       (((CALL) == I2C_GENERALCALL_DISABLE) || \
+                                         ((CALL) == I2C_GENERALCALL_ENABLE))
+
+#define IS_I2C_NO_STRETCH(STRETCH)      (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
+                                         ((STRETCH) == I2C_NOSTRETCH_ENABLE))
+
+#define IS_I2C_MEMADD_SIZE(SIZE)        (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
+                                         ((SIZE) == I2C_MEMADD_SIZE_16BIT))
+
+#define IS_TRANSFER_MODE(MODE)          (((MODE) == I2C_RELOAD_MODE)   || \
+                                         ((MODE) == I2C_AUTOEND_MODE) || \
+                                         ((MODE) == I2C_SOFTEND_MODE))
+
+#define IS_TRANSFER_REQUEST(REQUEST)    (((REQUEST) == I2C_GENERATE_STOP)        || \
+                                         ((REQUEST) == I2C_GENERATE_START_READ)  || \
+                                         ((REQUEST) == I2C_GENERATE_START_WRITE) || \
+                                         ((REQUEST) == I2C_NO_STARTSTOP))
+
+#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)  (((REQUEST) == I2C_FIRST_FRAME)          || \
+                                                   ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
+                                                   ((REQUEST) == I2C_NEXT_FRAME)           || \
+                                                   ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
+                                                   ((REQUEST) == I2C_LAST_FRAME)           || \
+                                                   ((REQUEST) == I2C_LAST_FRAME_NO_STOP)   || \
+                                                   IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
+
+#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME)     || \
+                                                        ((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
+
+#define I2C_RESET_CR2(__HANDLE__)                 ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
+
+#define I2C_GET_ADDR_MATCH(__HANDLE__)            ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U))
+#define I2C_GET_DIR(__HANDLE__)                   ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U))
+#define I2C_GET_STOP_MODE(__HANDLE__)             ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
+#define I2C_GET_OWN_ADDRESS1(__HANDLE__)          ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
+#define I2C_GET_OWN_ADDRESS2(__HANDLE__)          ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
+
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1)             ((ADDRESS1) <= 0x000003FFU)
+#define IS_I2C_OWN_ADDRESS2(ADDRESS2)             ((ADDRESS2) <= (uint16_t)0x00FFU)
+
+#define I2C_MEM_ADD_MSB(__ADDRESS__)              ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
+#define I2C_MEM_ADD_LSB(__ADDRESS__)              ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
+
+#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
+                                                          (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
+
+#define I2C_CHECK_FLAG(__ISR__, __FLAG__)         ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
+#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__)      ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
+/**
+  * @}
+  */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Functions I2C Private Functions
+  * @{
+  */
+/* Private functions are defined in stm32h7xx_hal_i2c.c file */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32H7xx_HAL_I2C_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h
new file mode 100644
index 00000000..bf89420b
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h
@@ -0,0 +1,181 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_i2c_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of I2C HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_I2C_EX_H
+#define STM32H7xx_HAL_I2C_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup I2CEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
+  * @{
+  */
+
+/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
+  * @{
+  */
+#define I2C_ANALOGFILTER_ENABLE         0x00000000U
+#define I2C_ANALOGFILTER_DISABLE        I2C_CR1_ANFOFF
+/**
+  * @}
+  */
+
+/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
+  * @{
+  */
+#define I2C_FASTMODEPLUS_PB6            SYSCFG_PMCR_I2C_PB6_FMP                        /*!< Enable Fast Mode Plus on PB6       */
+#define I2C_FASTMODEPLUS_PB7            SYSCFG_PMCR_I2C_PB7_FMP                        /*!< Enable Fast Mode Plus on PB7       */
+#define I2C_FASTMODEPLUS_PB8            SYSCFG_PMCR_I2C_PB8_FMP                        /*!< Enable Fast Mode Plus on PB8       */
+#define I2C_FASTMODEPLUS_PB9            SYSCFG_PMCR_I2C_PB9_FMP                        /*!< Enable Fast Mode Plus on PB9       */
+#define I2C_FASTMODEPLUS_I2C1           SYSCFG_PMCR_I2C1_FMP                           /*!< Enable Fast Mode Plus on I2C1 pins */
+#define I2C_FASTMODEPLUS_I2C2           SYSCFG_PMCR_I2C2_FMP                           /*!< Enable Fast Mode Plus on I2C2 pins */
+#define I2C_FASTMODEPLUS_I2C3           SYSCFG_PMCR_I2C3_FMP                           /*!< Enable Fast Mode Plus on I2C3 pins */
+#define I2C_FASTMODEPLUS_I2C4           SYSCFG_PMCR_I2C4_FMP                           /*!< Enable Fast Mode Plus on I2C4 pins */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
+  * @{
+  */
+
+/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions
+  * @brief    Extended features functions
+  * @{
+  */
+
+/* Peripheral Control functions  ************************************************/
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
+HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
+void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
+void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
+  * @{
+  */
+#define IS_I2C_ANALOG_FILTER(FILTER)    (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
+                                          ((FILTER) == I2C_ANALOGFILTER_DISABLE))
+
+#define IS_I2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000FU)
+
+#if (defined(SYSCFG_PMCR_I2C1_FMP) && defined(SYSCFG_PMCR_I2C2_FMP) && defined(SYSCFG_PMCR_I2C3_FMP) && defined(SYSCFG_PMCR_I2C4_FMP))
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3) || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C4) == I2C_FASTMODEPLUS_I2C4))
+#elif defined(SYSCFG_PMCR_I2C1_FMP) && defined(SYSCFG_PMCR_I2C2_FMP) && defined(SYSCFG_PMCR_I2C3_FMP)
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3))
+#elif defined(SYSCFG_PMCR_I2C1_FMP) && defined(SYSCFG_PMCR_I2C2_FMP)
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2))
+#elif defined(SYSCFG_PMCR_I2C1_FMP)
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1))
+#endif /* SYSCFG_PMCR_I2C1_FMP && SYSCFG_PMCR_I2C2_FMP && SYSCFG_PMCR_I2C3_FMP && SYSCFG_PMCR_I2C4_FMP */
+
+
+
+/**
+  * @}
+  */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
+  * @{
+  */
+/* Private functions are defined in stm32h7xx_hal_i2c_ex.c file */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_I2C_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h
new file mode 100644
index 00000000..6c1d9b71
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h
@@ -0,0 +1,855 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_mdma.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMA HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_MDMA_H
+#define STM32H7xx_HAL_MDMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup MDMA
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup MDMA_Exported_Types MDMA Exported Types
+  * @brief    MDMA Exported Types
+  * @{
+  */
+
+/**
+  * @brief  MDMA Configuration Structure definition
+  */
+typedef struct
+{
+
+  uint32_t Request;                 /*!< Specifies the MDMA request.
+                                        This parameter can be a value of @ref MDMA_Request_selection*/
+
+  uint32_t TransferTriggerMode;     /*!< Specifies the Trigger Transfer mode : each request triggers a :
+                                         a buffer transfer, a block transfer, a repeated block transfer or a linked list transfer
+                                         This parameter can be a value of @ref MDMA_Transfer_TriggerMode  */
+
+  uint32_t Priority;                 /*!< Specifies the software priority for the MDMAy channelx.
+                                         This parameter can be a value of @ref MDMA_Priority_level */
+
+  uint32_t Endianness;                /*!< Specifies if the MDMA transactions preserve the Little endianness.
+                                         This parameter can be a value of @ref MDMA_Endianness */
+
+  uint32_t SourceInc;                /*!< Specifies if the Source increment mode .
+                                         This parameter can be a value of @ref MDMA_Source_increment_mode */
+
+  uint32_t DestinationInc;           /*!< Specifies if the Destination increment mode .
+                                         This parameter can be a value of @ref MDMA_Destination_increment_mode */
+
+  uint32_t SourceDataSize;           /*!< Specifies the source data size.
+                                         This parameter can be a value of @ref MDMA_Source_data_size */
+
+  uint32_t DestDataSize;             /*!< Specifies the destination data size.
+                                          This parameter can be a value of @ref MDMA_Destination_data_size */
+
+
+  uint32_t DataAlignment;            /*!< Specifies the source to destination Memory data packing/padding mode.
+                                            This parameter can be a value of @ref MDMA_data_Alignment */
+
+  uint32_t BufferTransferLength;      /*!< Specifies the buffer Transfer Length (number of bytes),
+                                          this is the number of bytes to be transferred in a single transfer (1 byte to 128 bytes)*/
+
+  uint32_t SourceBurst;              /*!< Specifies the Burst transfer configuration for the source memory transfers.
+                                         It specifies the amount of data to be transferred in a single non interruptable
+                                         transaction.
+                                         This parameter can be a value of @ref MDMA_Source_burst
+                                         @note : the burst may be FIXED/INCR based on SourceInc value ,
+                                         the BURST must be programmed as to ensure that the burst size will be lower than than
+                                         BufferTransferLength */
+
+  uint32_t DestBurst;                 /*!< Specifies the Burst transfer configuration for the destination memory transfers.
+                                           It specifies the amount of data to be transferred in a single non interruptable
+                                           transaction.
+                                           This parameter can be a value of @ref MDMA_Destination_burst
+                                           @note : the burst may be FIXED/INCR based on DestinationInc value ,
+                                           the BURST must be programmed as to ensure that the burst size will be lower than than
+                                           BufferTransferLength */
+
+  int32_t SourceBlockAddressOffset;   /*!< this field specifies the Next block source address offset
+                                           signed value : if > 0 then  increment the next block source Address by offset from where the last block ends
+                                                          if < 0 then  decrement the next block source Address by offset from where the last block ends
+                                                          if == 0, the next block source address starts from where the last block ends
+                                       */
+
+
+  int32_t DestBlockAddressOffset;      /*!< this field specifies the Next block destination address offset
+                                           signed value : if > 0 then  increment the next block destination Address by offset from where the last block ends
+                                                          if < 0 then  decrement the next block destination Address by offset from where the last block ends
+                                                          if == 0, the next block destination address starts from where the last block ends
+                                       */
+
+}MDMA_InitTypeDef;
+
+/**
+  * @brief  HAL MDMA linked list node structure definition
+  * @note   The Linked list node allows to define a new MDMA configuration
+  *         (CTCR ,CBNDTR ,CSAR ,CDAR ,CBRUR, CLAR, CTBR, CMAR and CMDR registers).
+  *         When CLAR register is configured to a non NULL value , each time a transfer ends,
+  *         a new configuration (linked list node) is automatically loaded from the address given in CLAR register.
+  */
+typedef struct
+{
+  __IO uint32_t CTCR;     /*!< New CTCR register configuration for the given MDMA linked list node   */
+  __IO uint32_t CBNDTR;   /*!< New CBNDTR register configuration for the given MDMA linked list node */
+  __IO uint32_t CSAR;     /*!< New CSAR register configuration for the given MDMA linked list node   */
+  __IO uint32_t CDAR;     /*!< New CDAR register configuration for the given MDMA linked list node   */
+  __IO uint32_t CBRUR;    /*!< New CBRUR register configuration for the given MDMA linked list node  */
+  __IO uint32_t CLAR;     /*!< New CLAR register configuration for the given MDMA linked list node   */
+  __IO uint32_t CTBR;     /*!< New CTBR register configuration for the given MDMA linked list node   */
+  __IO uint32_t Reserved; /*!< Reserved register                                                     */
+  __IO uint32_t CMAR;     /*!< New CMAR register configuration for the given MDMA linked list node   */
+  __IO uint32_t CMDR;     /*!< New CMDR register configuration for the given MDMA linked list node   */
+
+}MDMA_LinkNodeTypeDef;
+
+/**
+  * @brief  HAL MDMA linked list node configuration structure definition
+  * @note   used with HAL_MDMA_LinkedList_CreateNode function
+  */
+typedef struct
+{
+  MDMA_InitTypeDef Init;            /*!< configuration of the specified MDMA Linked List Node    */
+  uint32_t         SrcAddress;      /*!< The source memory address for the Linked list Node      */
+  uint32_t         DstAddress;      /*!< The destination memory address for the Linked list Node */
+  uint32_t         BlockDataLength; /*!< The data length of a block in bytes                     */
+  uint32_t         BlockCount;      /*!< The number of blocks to be transferred                  */
+
+  uint32_t PostRequestMaskAddress;  /*!< specifies the address to be updated (written) with PostRequestMaskData after a request is served.
+                                         PostRequestMaskAddress and PostRequestMaskData could be used to automatically clear a peripheral flag when the request is served  */
+
+  uint32_t PostRequestMaskData;     /*!< specifies the value to be written to PostRequestMaskAddress after a request is served.
+                                         PostRequestMaskAddress and PostRequestMaskData could be used to automatically clear a peripheral flag when the request is served  */
+
+
+}MDMA_LinkNodeConfTypeDef;
+
+
+/**
+  * @brief  HAL MDMA State structure definition
+  */
+typedef enum
+{
+  HAL_MDMA_STATE_RESET               = 0x00U,  /*!< MDMA not yet initialized or disabled */
+  HAL_MDMA_STATE_READY               = 0x01U,  /*!< MDMA initialized and ready for use   */
+  HAL_MDMA_STATE_BUSY                = 0x02U,  /*!< MDMA process is ongoing              */
+  HAL_MDMA_STATE_ERROR               = 0x03U,  /*!< MDMA error state                     */
+  HAL_MDMA_STATE_ABORT               = 0x04U,  /*!< MDMA Abort state                     */
+
+}HAL_MDMA_StateTypeDef;
+
+/**
+  * @brief  HAL MDMA Level Complete structure definition
+  */
+typedef enum
+{
+  HAL_MDMA_FULL_TRANSFER         = 0x00U,   /*!< Full transfer         */
+  HAL_MDMA_BUFFER_TRANSFER       = 0x01U,   /*!< Buffer Transfer       */
+  HAL_MDMA_BLOCK_TRANSFER        = 0x02U,   /*!< Block Transfer        */
+  HAL_MDMA_REPEAT_BLOCK_TRANSFER = 0x03U    /*!< repeat block Transfer */
+
+}HAL_MDMA_LevelCompleteTypeDef;
+
+/**
+  * @brief  HAL MDMA Callbacks IDs structure definition
+  */
+typedef enum
+{
+  HAL_MDMA_XFER_CPLT_CB_ID          = 0x00U,    /*!< Full transfer           */
+  HAL_MDMA_XFER_BUFFERCPLT_CB_ID    = 0x01U,    /*!< Buffer Transfer         */
+  HAL_MDMA_XFER_BLOCKCPLT_CB_ID     = 0x02U,    /*!< Block Transfer          */
+  HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID  = 0x03U,    /*!< Repeated Block Transfer */
+  HAL_MDMA_XFER_ERROR_CB_ID         = 0x04U,    /*!< Error                   */
+  HAL_MDMA_XFER_ABORT_CB_ID         = 0x05U,    /*!< Abort                   */
+  HAL_MDMA_XFER_ALL_CB_ID           = 0x06U     /*!< All                     */
+
+}HAL_MDMA_CallbackIDTypeDef;
+
+
+/**
+  * @brief  MDMA handle Structure definition
+  */
+typedef struct __MDMA_HandleTypeDef
+{
+  MDMA_Channel_TypeDef *Instance;                                                              /*!< Register base address                  */
+
+  MDMA_InitTypeDef      Init;                                                                  /*!< MDMA communication parameters          */
+
+  HAL_LockTypeDef       Lock;                                                                  /*!< MDMA locking object                    */
+
+  __IO HAL_MDMA_StateTypeDef  State;                                                           /*!< MDMA transfer state                    */
+
+  void                  *Parent;                                                               /*!< Parent object state                    */
+
+  void                  (* XferCpltCallback)( struct __MDMA_HandleTypeDef * hmdma);            /*!< MDMA transfer complete callback        */
+
+  void                  (* XferBufferCpltCallback)( struct __MDMA_HandleTypeDef * hmdma);      /*!< MDMA buffer transfer complete callback */
+
+  void                  (* XferBlockCpltCallback)( struct __MDMA_HandleTypeDef * hmdma);       /*!< MDMA block transfer complete callback  */
+
+  void                  (* XferRepeatBlockCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA block transfer repeat callback    */
+
+  void                  (* XferErrorCallback)( struct __MDMA_HandleTypeDef * hmdma);           /*!< MDMA transfer error callback           */
+
+  void                  (* XferAbortCallback)( struct __MDMA_HandleTypeDef * hmdma);           /*!< MDMA transfer Abort callback           */
+
+
+  MDMA_LinkNodeTypeDef *FirstLinkedListNodeAddress;                                             /*!< specifies the first node address of the transfer list
+                                                                                                     (after the initial node defined by the Init struct)
+                                                                                                     this parameter is used internally by the MDMA driver
+                                                                                                     to construct the linked list node
+                                                                                                */
+
+  MDMA_LinkNodeTypeDef *LastLinkedListNodeAddress;                                             /*!< specifies the last node address of the transfer list
+                                                                                                    this parameter is used internally by the MDMA driver
+                                                                                                    to construct the linked list node
+                                                                                                */
+  uint32_t LinkedListNodeCounter;                                                               /*!< Number of nodes in the MDMA linked list */
+
+  __IO uint32_t          ErrorCode;                                                            /*!< MDMA Error code                        */
+
+} MDMA_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup MDMA_Exported_Constants MDMA Exported Constants
+  * @brief    MDMA Exported constants
+  * @{
+  */
+
+/** @defgroup MDMA_Error_Codes MDMA Error Codes
+  * @brief    MDMA Error Codes
+  * @{
+  */
+#define HAL_MDMA_ERROR_NONE        ((uint32_t)0x00000000U)   /*!< No error                               */
+#define HAL_MDMA_ERROR_READ_XFER   ((uint32_t)0x00000001U)   /*!< Read Transfer error                    */
+#define HAL_MDMA_ERROR_WRITE_XFER  ((uint32_t)0x00000002U)   /*!< Write Transfer error                   */
+#define HAL_MDMA_ERROR_MASK_DATA   ((uint32_t)0x00000004U)   /*!< Error Mask Data error                  */
+#define HAL_MDMA_ERROR_LINKED_LIST ((uint32_t)0x00000008U)   /*!< Linked list Data error                 */
+#define HAL_MDMA_ERROR_ALIGNMENT   ((uint32_t)0x00000010U)   /*!< Address/Size alignment  error          */
+#define HAL_MDMA_ERROR_BLOCK_SIZE  ((uint32_t)0x00000020U)   /*!< Block Size error                       */
+#define HAL_MDMA_ERROR_TIMEOUT     ((uint32_t)0x00000040U)   /*!< Timeout error                          */
+#define HAL_MDMA_ERROR_NO_XFER     ((uint32_t)0x00000080U)   /*!< Abort or SW trigger requested with no Xfer ongoing   */
+#define HAL_MDMA_ERROR_BUSY        ((uint32_t)0x00000100U)   /*!< DeInit or SW trigger requested with Xfer ongoing   */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_Request_selection MDMA Request selection
+  * @brief    MDMA_Request_selection
+  * @{
+  */
+
+#define MDMA_REQUEST_DMA1_Stream0_TC      ((uint32_t)0x00000000U)  /*!< MDMA HW request is DMA1 Stream 0 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA1_Stream1_TC      ((uint32_t)0x00000001U)  /*!< MDMA HW request is DMA1 Stream 1 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA1_Stream2_TC      ((uint32_t)0x00000002U)  /*!< MDMA HW request is DMA1 Stream 2 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA1_Stream3_TC      ((uint32_t)0x00000003U)  /*!< MDMA HW request is DMA1 Stream 3 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA1_Stream4_TC      ((uint32_t)0x00000004U)  /*!< MDMA HW request is DMA1 Stream 4 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA1_Stream5_TC      ((uint32_t)0x00000005U)  /*!< MDMA HW request is DMA1 Stream 5 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA1_Stream6_TC      ((uint32_t)0x00000006U)  /*!< MDMA HW request is DMA1 Stream 6 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA1_Stream7_TC      ((uint32_t)0x00000007U)  /*!< MDMA HW request is DMA1 Stream 7 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA2_Stream0_TC      ((uint32_t)0x00000008U)  /*!< MDMA HW request is DMA2 Stream 0 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA2_Stream1_TC      ((uint32_t)0x00000009U)  /*!< MDMA HW request is DMA2 Stream 1 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA2_Stream2_TC      ((uint32_t)0x0000000AU)  /*!< MDMA HW request is DMA2 Stream 2 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA2_Stream3_TC      ((uint32_t)0x0000000BU)  /*!< MDMA HW request is DMA2 Stream 3 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA2_Stream4_TC      ((uint32_t)0x0000000CU)  /*!< MDMA HW request is DMA2 Stream 4 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA2_Stream5_TC      ((uint32_t)0x0000000DU)  /*!< MDMA HW request is DMA2 Stream 5 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA2_Stream6_TC      ((uint32_t)0x0000000EU)  /*!< MDMA HW request is DMA2 Stream 6 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA2_Stream7_TC      ((uint32_t)0x0000000FU)  /*!< MDMA HW request is DMA2 Stream 7 Transfer Complete Flag   */
+#if defined (LTDC)
+#define MDMA_REQUEST_LTDC_LINE_IT         ((uint32_t)0x00000010U)  /*!< MDMA HW request is LTDC Line interrupt Flag               */
+#endif /* LTDC */
+#if defined (JPEG)
+#define MDMA_REQUEST_JPEG_INFIFO_TH       ((uint32_t)0x00000011U)  /*!< MDMA HW request is JPEG Input FIFO threshold Flag         */
+#define MDMA_REQUEST_JPEG_INFIFO_NF       ((uint32_t)0x00000012U)  /*!< MDMA HW request is JPEG Input FIFO not full Flag          */
+#define MDMA_REQUEST_JPEG_OUTFIFO_TH      ((uint32_t)0x00000013U)  /*!< MDMA HW request is JPEG Output FIFO threshold Flag        */
+#define MDMA_REQUEST_JPEG_OUTFIFO_NE      ((uint32_t)0x00000014U)  /*!< MDMA HW request is JPEG Output FIFO not empty Flag        */
+#define MDMA_REQUEST_JPEG_END_CONVERSION  ((uint32_t)0x00000015U)  /*!< MDMA HW request is JPEG End of conversion Flag            */
+#endif /* JPEG */
+#if defined (OCTOSPI1)
+#define MDMA_REQUEST_OCTOSPI1_FIFO_TH     ((uint32_t)0x00000016U)  /*!< MDMA HW request is OCTOSPI1 FIFO threshold Flag           */
+#define MDMA_REQUEST_OCTOSPI1_TC          ((uint32_t)0x00000017U)  /*!< MDMA HW request is OCTOSPI1 Transfer complete Flag        */
+#endif /* OCTOSPI1 */
+#if defined (QUADSPI)
+#define MDMA_REQUEST_QUADSPI_FIFO_TH      ((uint32_t)0x00000016U)  /*!< MDMA HW request is QSPI FIFO threshold Flag               */
+#define MDMA_REQUEST_QUADSPI_TC           ((uint32_t)0x00000017U)  /*!< MDMA HW request is QSPI Transfer complete Flag            */
+#endif /* QUADSPI */
+#define MDMA_REQUEST_DMA2D_CLUT_TC        ((uint32_t)0x00000018U)  /*!< MDMA HW request is DMA2D CLUT Transfer Complete Flag      */
+#define MDMA_REQUEST_DMA2D_TC             ((uint32_t)0x00000019U)  /*!< MDMA HW request is DMA2D Transfer Complete Flag           */
+#define MDMA_REQUEST_DMA2D_TW             ((uint32_t)0x0000001AU)  /*!< MDMA HW request is DMA2D Transfer Watermark Flag          */
+
+#if defined (DSI)
+#define MDMA_REQUEST_DSI_TEARING_EFFECT   ((uint32_t)0x0000001BU)  /*!< MDMA HW request is DSI Tearing Effect Flag                */
+#define MDMA_REQUEST_DSI_END_REFRESH      ((uint32_t)0x0000001CU)  /*!< MDMA HW request is DSI End of refresh  Flag               */
+#endif /* DSI */
+
+#define MDMA_REQUEST_SDMMC1_END_DATA      ((uint32_t)0x0000001DU)  /*!< MDMA HW request is SDMMC1 End of Data Flag                */
+
+#define MDMA_REQUEST_SDMMC1_DMA_ENDBUFFER ((uint32_t)0x0000001EU)  /*!< MDMA HW request is SDMMC1 Internal DMA buffer End Flag    */
+#define MDMA_REQUEST_SDMMC1_COMMAND_END   ((uint32_t)0x0000001FU)  /*!< MDMA HW request is SDMMC1 Command End Flag                */
+
+#if defined (OCTOSPI2)
+#define MDMA_REQUEST_OCTOSPI2_FIFO_TH     ((uint32_t)0x00000020U)  /*!< MDMA HW request is OCTOSPI2 FIFO threshold Flag           */
+#define MDMA_REQUEST_OCTOSPI2_TC          ((uint32_t)0x00000021U)  /*!< MDMA HW request is OCTOSPI2 Transfer complete Flag        */
+#endif /* OCTOSPI2 */
+
+#define MDMA_REQUEST_SW                   ((uint32_t)0x40000000U) /*!< MDMA SW request                                            */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_Transfer_TriggerMode MDMA Transfer Trigger  Mode
+  * @brief    MDMA Transfer Trigger Mode
+  * @{
+  */
+#define MDMA_BUFFER_TRANSFER          ((uint32_t)0x00000000U)        /*!< Each MDMA request (SW or HW) triggers a buffer transfer                                */
+#define MDMA_BLOCK_TRANSFER           ((uint32_t)MDMA_CTCR_TRGM_0)   /*!< Each MDMA request (SW or HW) triggers a block transfer                                 */
+#define MDMA_REPEAT_BLOCK_TRANSFER    ((uint32_t)MDMA_CTCR_TRGM_1)   /*!< Each MDMA request (SW or HW) triggers a repeated block transfer                        */
+#define MDMA_FULL_TRANSFER            ((uint32_t)MDMA_CTCR_TRGM)     /*!< Each MDMA request (SW or HW) triggers a Full transfer or a linked list transfer if any */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_Priority_level MDMA Priority level
+  * @brief    MDMA Priority level
+  * @{
+  */
+#define MDMA_PRIORITY_LOW             ((uint32_t)0x00000000U)     /*!< Priority level: Low      */
+#define MDMA_PRIORITY_MEDIUM          ((uint32_t)MDMA_CCR_PL_0)  /*!< Priority level: Medium    */
+#define MDMA_PRIORITY_HIGH            ((uint32_t)MDMA_CCR_PL_1)  /*!< Priority level: High      */
+#define MDMA_PRIORITY_VERY_HIGH       ((uint32_t)MDMA_CCR_PL)    /*!< Priority level: Very High */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup MDMA_Endianness MDMA Endianness
+  * @brief    MDMA Endianness
+  * @{
+  */
+#define MDMA_LITTLE_ENDIANNESS_PRESERVE          ((uint32_t)0x00000000U)   /*!< little endianness preserve                                               */
+#define MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE     ((uint32_t)MDMA_CCR_BEX)  /*!< BYTEs endianness exchange when destination data size is > Byte           */
+#define MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_HEX)  /*!< HALF WORDs endianness exchange when destination data size is > HALF WORD */
+#define MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE     ((uint32_t)MDMA_CCR_WEX)  /*!< WORDs endianness exchange  when destination data size is > DOUBLE WORD   */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_Source_increment_mode MDMA Source increment mode
+  * @brief    MDMA Source increment mode
+  * @{
+  */
+#define MDMA_SRC_INC_DISABLE      ((uint32_t)0x00000000U)                                     /*!< Source address pointer is fixed                                   */
+#define MDMA_SRC_INC_BYTE         ((uint32_t)MDMA_CTCR_SINC_1)                                /*!< Source address pointer is incremented by a BYTE (8 bits)          */
+#define MDMA_SRC_INC_HALFWORD     ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits)    */
+#define MDMA_SRC_INC_WORD         ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits)         */
+#define MDMA_SRC_INC_DOUBLEWORD   ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS)   /*!< Source address pointer is incremented by a double Word (64 bits)) */
+#define MDMA_SRC_DEC_BYTE         ((uint32_t)MDMA_CTCR_SINC)                                  /*!< Source address pointer is decremented by a BYTE (8 bits)          */
+#define MDMA_SRC_DEC_HALFWORD     ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_0)   /*!< Source address pointer is decremented by a half Word (16 bits)    */
+#define MDMA_SRC_DEC_WORD         ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_1)   /*!< Source address pointer is decremented by a Word (32 bits)         */
+#define MDMA_SRC_DEC_DOUBLEWORD   ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS)     /*!< Source address pointer is decremented by a double Word (64 bits)) */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_Destination_increment_mode MDMA Destination increment mode
+  * @brief    MDMA Destination increment mode
+  * @{
+  */
+#define MDMA_DEST_INC_DISABLE      ((uint32_t)0x00000000U)                                     /*!< Source address pointer is fixed                                   */
+#define MDMA_DEST_INC_BYTE         ((uint32_t)MDMA_CTCR_DINC_1)                                /*!< Source address pointer is incremented by a BYTE (8 bits)          */
+#define MDMA_DEST_INC_HALFWORD     ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits)    */
+#define MDMA_DEST_INC_WORD         ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits)         */
+#define MDMA_DEST_INC_DOUBLEWORD   ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS)   /*!< Source address pointer is incremented by a double Word (64 bits)) */
+#define MDMA_DEST_DEC_BYTE         ((uint32_t)MDMA_CTCR_DINC)                                  /*!< Source address pointer is decremented by a BYTE (8 bits)          */
+#define MDMA_DEST_DEC_HALFWORD     ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_0)   /*!< Source address pointer is decremented by a half Word (16 bits)    */
+#define MDMA_DEST_DEC_WORD         ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_1)   /*!< Source address pointer is decremented by a Word (32 bits)         */
+#define MDMA_DEST_DEC_DOUBLEWORD   ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS)     /*!< Source address pointer is decremented by a double Word (64 bits)) */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_Source_data_size MDMA Source data size
+  * @brief    MDMA Source data size
+  * @{
+  */
+#define MDMA_SRC_DATASIZE_BYTE        ((uint32_t)0x00000000U)         /*!< Source data size is Byte        */
+#define MDMA_SRC_DATASIZE_HALFWORD    ((uint32_t)MDMA_CTCR_SSIZE_0)   /*!< Source data size is half word   */
+#define MDMA_SRC_DATASIZE_WORD        ((uint32_t)MDMA_CTCR_SSIZE_1)   /*!< Source data size is word        */
+#define MDMA_SRC_DATASIZE_DOUBLEWORD  ((uint32_t)MDMA_CTCR_SSIZE)     /*!< Source data size is double word */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_Destination_data_size MDMA Destination data size
+  * @brief    MDMA Destination data size
+  * @{
+  */
+#define MDMA_DEST_DATASIZE_BYTE        ((uint32_t)0x00000000U)         /*!< Destination data size is Byte        */
+#define MDMA_DEST_DATASIZE_HALFWORD    ((uint32_t)MDMA_CTCR_DSIZE_0)   /*!< Destination data size is half word   */
+#define MDMA_DEST_DATASIZE_WORD        ((uint32_t)MDMA_CTCR_DSIZE_1)   /*!< Destination data size is word        */
+#define MDMA_DEST_DATASIZE_DOUBLEWORD  ((uint32_t)MDMA_CTCR_DSIZE)     /*!< Destination data size is double word */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_data_Alignment MDMA data alignment
+  * @brief    MDMA data alignment
+  * @{
+  */
+#define MDMA_DATAALIGN_PACKENABLE        ((uint32_t)MDMA_CTCR_PKE)     /*!< The source data is packed/un-packed into the destination data size
+                                                                            All data are right aligned, in Little Endien mode.                                              */
+#define MDMA_DATAALIGN_RIGHT            ((uint32_t)0x00000000U)        /*!< Right Aligned, padded w/ 0s (default)                                                           */
+#define MDMA_DATAALIGN_RIGHT_SIGNED     ((uint32_t)MDMA_CTCR_PAM_0)    /*!< Right Aligned, Sign extended ,
+                                                                            Note : this mode is allowed only if the Source data size is smaller than Destination data size  */
+#define MDMA_DATAALIGN_LEFT             ((uint32_t)MDMA_CTCR_PAM_1)    /*!< Left Aligned (padded with 0s)                                                                   */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_Source_burst MDMA Source burst
+  * @brief    MDMA Source burst
+  * @{
+  */
+#define MDMA_SOURCE_BURST_SINGLE        ((uint32_t)0x00000000U)                                       /*!< single transfer */
+#define MDMA_SOURCE_BURST_2BEATS        ((uint32_t)MDMA_CTCR_SBURST_0)                                /*!< Burst 2 beats   */
+#define MDMA_SOURCE_BURST_4BEATS        ((uint32_t)MDMA_CTCR_SBURST_1)                                /*!< Burst 4 beats   */
+#define MDMA_SOURCE_BURST_8BEATS        ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_1) /*!< Burst 8 beats   */
+#define MDMA_SOURCE_BURST_16BEATS       ((uint32_t)MDMA_CTCR_SBURST_2)                                /*!< Burst 16 beats  */
+#define MDMA_SOURCE_BURST_32BEATS       ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 32 beats  */
+#define MDMA_SOURCE_BURST_64BEATS       ((uint32_t)MDMA_CTCR_SBURST_1 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 64 beats  */
+#define MDMA_SOURCE_BURST_128BEATS      ((uint32_t)MDMA_CTCR_SBURST)                                  /*!< Burst 128 beats */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_Destination_burst MDMA Destination burst
+  * @brief    MDMA Destination burst
+  * @{
+  */
+#define MDMA_DEST_BURST_SINGLE        ((uint32_t)0x00000000U)                                        /*!< single transfer */
+#define MDMA_DEST_BURST_2BEATS        ((uint32_t)MDMA_CTCR_DBURST_0)                                 /*!< Burst 2 beats   */
+#define MDMA_DEST_BURST_4BEATS        ((uint32_t)MDMA_CTCR_DBURST_1)                                 /*!< Burst 4 beats   */
+#define MDMA_DEST_BURST_8BEATS        ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_1)  /*!< Burst 8 beats   */
+#define MDMA_DEST_BURST_16BEATS       ((uint32_t)MDMA_CTCR_DBURST_2)                                 /*!< Burst 16 beats  */
+#define MDMA_DEST_BURST_32BEATS       ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_2)  /*!< Burst 32 beats  */
+#define MDMA_DEST_BURST_64BEATS       ((uint32_t)MDMA_CTCR_DBURST_1 | (uint32_t)MDMA_CTCR_DBURST_2)  /*!< Burst 64 beats  */
+#define MDMA_DEST_BURST_128BEATS      ((uint32_t)MDMA_CTCR_DBURST)                                   /*!< Burst 128 beats */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_interrupt_enable_definitions MDMA interrupt enable definitions
+  * @brief    MDMA interrupt enable definitions
+  * @{
+  */
+#define MDMA_IT_TE   ((uint32_t)MDMA_CCR_TEIE)   /*!< Transfer Error interrupt            */
+#define MDMA_IT_CTC  ((uint32_t)MDMA_CCR_CTCIE)  /*!< Channel Transfer Complete interrupt */
+#define MDMA_IT_BRT  ((uint32_t)MDMA_CCR_BRTIE)  /*!< Block Repeat Transfer interrupt     */
+#define MDMA_IT_BT   ((uint32_t)MDMA_CCR_BTIE)   /*!< Block Transfer interrupt            */
+#define MDMA_IT_BFTC ((uint32_t)MDMA_CCR_TCIE)   /*!< Buffer Transfer Complete interrupt  */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_flag_definitions MDMA flag definitions
+  * @brief    MDMA flag definitions
+  * @{
+  */
+#define MDMA_FLAG_TE    ((uint32_t)MDMA_CISR_TEIF)  /*!< Transfer Error flag                 */
+#define MDMA_FLAG_CTC   ((uint32_t)MDMA_CISR_CTCIF) /*!< Channel Transfer Complete flag      */
+#define MDMA_FLAG_BRT   ((uint32_t)MDMA_CISR_BRTIF) /*!< Block Repeat Transfer complete flag */
+#define MDMA_FLAG_BT    ((uint32_t)MDMA_CISR_BTIF)  /*!< Block Transfer complete flag        */
+#define MDMA_FLAG_BFTC  ((uint32_t)MDMA_CISR_TCIF)  /*!< BuFfer Transfer complete flag       */
+#define MDMA_FLAG_CRQA  ((uint32_t)MDMA_CISR_CRQA)  /*!< Channel ReQest Active flag          */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup MDMA_Exported_Macros MDMA Exported Macros
+  * @{
+  */
+
+/**
+  * @brief  Enable the specified MDMA Channel.
+  * @param  __HANDLE__: MDMA handle
+  * @retval None
+  */
+#define __HAL_MDMA_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CCR |=  MDMA_CCR_EN)
+
+/**
+  * @brief  Disable the specified MDMA Channel.
+  * @param  __HANDLE__: MDMA handle
+  * @retval None
+  */
+#define __HAL_MDMA_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CCR &=  ~MDMA_CCR_EN)
+
+/**
+  * @brief  Get the MDMA Channel pending flags.
+  * @param  __HANDLE__: MDMA handle
+  * @param  __FLAG__: Get the specified flag.
+  *          This parameter can be any combination of the following values:
+  *            @arg MDMA_FLAG_TE   : Transfer Error flag.
+  *            @arg MDMA_FLAG_CTC  : Channel Transfer Complete flag.
+  *            @arg MDMA_FLAG_BRT  : Block Repeat Transfer flag.
+  *            @arg MDMA_FLAG_BT   : Block Transfer complete flag.
+  *            @arg MDMA_FLAG_BFTC : BuFfer Transfer Complete flag.
+  *            @arg MDMA_FLAG_CRQA : Channel ReQest Active flag.
+  * @retval The state of FLAG (SET or RESET).
+  */
+#define __HAL_MDMA_GET_FLAG(__HANDLE__, __FLAG__)  ((__HANDLE__)->Instance->CISR & (__FLAG__))
+
+/**
+  * @brief  Clear the MDMA Stream pending flags.
+  * @param  __HANDLE__: MDMA handle
+  * @param  __FLAG__: specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg MDMA_FLAG_TE   : Transfer Error flag.
+  *            @arg MDMA_FLAG_CTC  : Channel Transfer Complete flag.
+  *            @arg MDMA_FLAG_BRT  : Block Repeat Transfer flag.
+  *            @arg MDMA_FLAG_BT   : Block Transfer complete flag.
+  *            @arg MDMA_FLAG_BFTC : BuFfer Transfer Complete flag.
+  * @retval None
+  */
+#define __HAL_MDMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CIFCR = (__FLAG__))
+
+/**
+  * @brief  Enables the specified MDMA Channel interrupts.
+  * @param  __HANDLE__: MDMA handle
+  * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg MDMA_IT_TE   :  Transfer Error interrupt mask
+  *            @arg MDMA_IT_CTC  :  Channel Transfer Complete interrupt mask
+  *            @arg MDMA_IT_BRT  :  Block Repeat Transfer interrupt mask
+  *            @arg MDMA_IT_BT   :  Block Transfer interrupt mask
+  *            @arg MDMA_IT_BFTC :  BuFfer Transfer Complete interrupt mask
+  * @retval None
+  */
+#define __HAL_MDMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
+
+/**
+  * @brief  Disables the specified MDMA Channel interrupts.
+  * @param  __HANDLE__: MDMA handle
+  * @param __INTERRUPT__: specifies the MDMA interrupt sources to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg MDMA_IT_TE   :  Transfer Error interrupt mask
+  *            @arg MDMA_IT_CTC  :  Channel Transfer Complete interrupt mask
+  *            @arg MDMA_IT_BRT  :  Block Repeat Transfer interrupt mask
+  *            @arg MDMA_IT_BT   :  Block Transfer interrupt mask
+  *            @arg MDMA_IT_BFTC :  BuFfer Transfer Complete interrupt mask
+  * @retval None
+  */
+#define __HAL_MDMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Checks whether the specified MDMA Channel interrupt is enabled or not.
+  * @param  __HANDLE__: DMA handle
+  * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
+  *            @arg MDMA_IT_TE   :  Transfer Error interrupt mask
+  *            @arg MDMA_IT_CTC  :  Channel Transfer Complete interrupt mask
+  *            @arg MDMA_IT_BRT  :  Block Repeat Transfer interrupt mask
+  *            @arg MDMA_IT_BT   :  Block Transfer interrupt mask
+  *            @arg MDMA_IT_BFTC :  BuFfer Transfer Complete interrupt mask
+  * @retval The state of MDMA_IT (SET or RESET).
+  */
+#define __HAL_MDMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup MDMA_Exported_Functions  MDMA Exported Functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions *****************************/
+/** @defgroup MDMA_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief   Initialization and de-initialization functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_MDMA_Init(MDMA_HandleTypeDef *hmdma);
+HAL_StatusTypeDef HAL_MDMA_DeInit (MDMA_HandleTypeDef *hmdma);
+HAL_StatusTypeDef HAL_MDMA_ConfigPostRequestMask(MDMA_HandleTypeDef *hmdma, uint32_t MaskAddress, uint32_t MaskData);
+
+HAL_StatusTypeDef HAL_MDMA_RegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID, void (* pCallback)(MDMA_HandleTypeDef *_hmdma));
+HAL_StatusTypeDef HAL_MDMA_UnRegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID);
+
+/**
+  * @}
+  */
+
+/* Linked list operation functions ********************************************/
+/** @defgroup MDMA_Exported_Functions_Group2 Linked List operation functions
+  * @brief   Linked list operation functions
+  * @{
+  */
+
+HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig);
+HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, MDMA_LinkNodeTypeDef *pPrevNode);
+HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNode);
+HAL_StatusTypeDef HAL_MDMA_LinkedList_EnableCircularMode(MDMA_HandleTypeDef *hmdma);
+HAL_StatusTypeDef HAL_MDMA_LinkedList_DisableCircularMode(MDMA_HandleTypeDef *hmdma);
+
+
+/**
+  * @}
+  */
+
+/* IO operation functions *****************************************************/
+/** @defgroup MDMA_Exported_Functions_Group3 I/O operation functions
+  * @brief   I/O operation functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_MDMA_Start (MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount);
+HAL_StatusTypeDef HAL_MDMA_Start_IT(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount);
+HAL_StatusTypeDef HAL_MDMA_Abort(MDMA_HandleTypeDef *hmdma);
+HAL_StatusTypeDef HAL_MDMA_Abort_IT(MDMA_HandleTypeDef *hmdma);
+HAL_StatusTypeDef HAL_MDMA_PollForTransfer(MDMA_HandleTypeDef *hmdma, HAL_MDMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
+HAL_StatusTypeDef HAL_MDMA_GenerateSWRequest(MDMA_HandleTypeDef *hmdma);
+void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma);
+
+/**
+  * @}
+  */
+
+/* Peripheral State and Error functions ***************************************/
+/** @defgroup MDMA_Exported_Functions_Group4 Peripheral State functions
+  * @brief    Peripheral State functions
+  * @{
+  */
+HAL_MDMA_StateTypeDef HAL_MDMA_GetState(MDMA_HandleTypeDef *hmdma);
+uint32_t              HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup MDMA_Private_Types MDMA Private Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup MDMA_Private_Defines MDMA Private Defines
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup MDMA_Private_Variables MDMA Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup MDMA_Private_Constants MDMA Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup MDMA_Private_Macros MDMA Private Macros
+  * @{
+  */
+
+#define IS_MDMA_LEVEL_COMPLETE(__LEVEL__) (((__LEVEL__) == HAL_MDMA_FULL_TRANSFER )  || \
+                                           ((__LEVEL__) == HAL_MDMA_BUFFER_TRANSFER )|| \
+                                           ((__LEVEL__) == HAL_MDMA_BLOCK_TRANSFER ) || \
+                                           ((__LEVEL__) == HAL_MDMA_REPEAT_BLOCK_TRANSFER ))
+
+
+#define IS_MDMA_PRIORITY(__PRIORITY__) (((__PRIORITY__) == MDMA_PRIORITY_LOW )   || \
+                                        ((__PRIORITY__) == MDMA_PRIORITY_MEDIUM) || \
+                                        ((__PRIORITY__) == MDMA_PRIORITY_HIGH)   || \
+                                        ((__PRIORITY__) == MDMA_PRIORITY_VERY_HIGH))
+
+#define IS_MDMA_ENDIANNESS_MODE(__ENDIANNESS__) (((__ENDIANNESS__) == MDMA_LITTLE_ENDIANNESS_PRESERVE )         || \
+                                                 ((__ENDIANNESS__) == MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE)     || \
+                                                 ((__ENDIANNESS__) == MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE) || \
+                                                 ((__ENDIANNESS__) == MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE))
+
+
+#if defined (OCTOSPI2)
+#define IS_MDMA_REQUEST(__REQUEST__) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_OCTOSPI2_TC))
+#else
+#define IS_MDMA_REQUEST(__REQUEST__) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_SDMMC1_COMMAND_END))
+#endif /* OCTOSPI2 */
+
+#define IS_MDMA_SOURCE_INC(__INC__) (((__INC__) == MDMA_SRC_INC_DISABLE )   || \
+                                     ((__INC__) == MDMA_SRC_INC_BYTE )      || \
+                                     ((__INC__) == MDMA_SRC_INC_HALFWORD )  || \
+                                     ((__INC__) == MDMA_SRC_INC_WORD )      || \
+                                     ((__INC__) == MDMA_SRC_INC_DOUBLEWORD) || \
+                                     ((__INC__) == MDMA_SRC_DEC_BYTE)       || \
+                                     ((__INC__) == MDMA_SRC_DEC_HALFWORD)   || \
+                                     ((__INC__) == MDMA_SRC_DEC_WORD)       || \
+                                     ((__INC__) == MDMA_SRC_DEC_DOUBLEWORD))
+
+#define IS_MDMA_DESTINATION_INC(__INC__) (((__INC__) == MDMA_DEST_INC_DISABLE )   || \
+                                          ((__INC__) == MDMA_DEST_INC_BYTE )      || \
+                                          ((__INC__) == MDMA_DEST_INC_HALFWORD )  || \
+                                          ((__INC__) == MDMA_DEST_INC_WORD )      || \
+                                          ((__INC__) == MDMA_DEST_INC_DOUBLEWORD) || \
+                                          ((__INC__) == MDMA_DEST_DEC_BYTE)       || \
+                                          ((__INC__) == MDMA_DEST_DEC_HALFWORD)   || \
+                                          ((__INC__) == MDMA_DEST_DEC_WORD)       || \
+                                          ((__INC__) == MDMA_DEST_DEC_DOUBLEWORD))
+
+#define IS_MDMA_SOURCE_DATASIZE(__SIZE__) (((__SIZE__) == MDMA_SRC_DATASIZE_BYTE )     || \
+                                           ((__SIZE__) == MDMA_SRC_DATASIZE_HALFWORD ) || \
+                                           ((__SIZE__) == MDMA_SRC_DATASIZE_WORD )     || \
+                                           ((__SIZE__) == MDMA_SRC_DATASIZE_DOUBLEWORD))
+
+#define IS_MDMA_DESTINATION_DATASIZE(__SIZE__) (((__SIZE__) == MDMA_DEST_DATASIZE_BYTE )     || \
+                                                ((__SIZE__) == MDMA_DEST_DATASIZE_HALFWORD ) || \
+                                                ((__SIZE__) == MDMA_DEST_DATASIZE_WORD )     || \
+                                                ((__SIZE__) == MDMA_DEST_DATASIZE_DOUBLEWORD))
+
+#define IS_MDMA_DATA_ALIGNMENT(__ALIGNMENT__) (((__ALIGNMENT__) == MDMA_DATAALIGN_PACKENABLE )    || \
+                                               ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT )         || \
+                                               ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT_SIGNED )  || \
+                                               ((__ALIGNMENT__) == MDMA_DATAALIGN_LEFT))
+
+
+#define IS_MDMA_SOURCE_BURST(__BURST__) (((__BURST__) == MDMA_SOURCE_BURST_SINGLE ) || \
+                                         ((__BURST__) == MDMA_SOURCE_BURST_2BEATS ) || \
+                                         ((__BURST__) == MDMA_SOURCE_BURST_4BEATS ) || \
+                                         ((__BURST__) == MDMA_SOURCE_BURST_8BEATS)  || \
+                                         ((__BURST__) == MDMA_SOURCE_BURST_16BEATS) || \
+                                         ((__BURST__) == MDMA_SOURCE_BURST_32BEATS) || \
+                                         ((__BURST__) == MDMA_SOURCE_BURST_64BEATS) || \
+                                         ((__BURST__) == MDMA_SOURCE_BURST_128BEATS))
+
+
+#define IS_MDMA_DESTINATION_BURST(__BURST__) (((__BURST__) == MDMA_DEST_BURST_SINGLE ) || \
+                                              ((__BURST__) == MDMA_DEST_BURST_2BEATS ) || \
+                                              ((__BURST__) == MDMA_DEST_BURST_4BEATS ) || \
+                                              ((__BURST__) == MDMA_DEST_BURST_8BEATS)  || \
+                                              ((__BURST__) == MDMA_DEST_BURST_16BEATS) || \
+                                              ((__BURST__) == MDMA_DEST_BURST_32BEATS) || \
+                                              ((__BURST__) == MDMA_DEST_BURST_64BEATS) || \
+                                              ((__BURST__) == MDMA_DEST_BURST_128BEATS))
+
+ #define IS_MDMA_TRANSFER_TRIGGER_MODE(__MODE__) (((__MODE__) == MDMA_BUFFER_TRANSFER )      || \
+                                                  ((__MODE__) == MDMA_BLOCK_TRANSFER )        || \
+                                                  ((__MODE__) == MDMA_REPEAT_BLOCK_TRANSFER ) || \
+                                                  ((__MODE__) == MDMA_FULL_TRANSFER))
+
+#define IS_MDMA_BUFFER_TRANSFER_LENGTH(__LENGTH__) (((__LENGTH__) >= 0x00000001U) && ((__LENGTH__) < 0x000000FFU))
+
+#define IS_MDMA_BLOCK_COUNT(__COUNT__) (((__COUNT__) > 0U ) && ((__COUNT__) <= 4096U))
+
+#define IS_MDMA_TRANSFER_LENGTH(SIZE) (((SIZE) > 0U) && ((SIZE) <= 65536U))
+
+#define IS_MDMA_BLOCK_ADDR_OFFSET(__BLOCK_ADD_OFFSET__) (((__BLOCK_ADD_OFFSET__) > (-65536)) && ((__BLOCK_ADD_OFFSET__) < 65536))
+
+/**
+  * @}
+  */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup MDMA_Private_Functions_Prototypes MDMA Private Functions Prototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup MDMA_Private_Functions MDMA Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_MDMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h
new file mode 100644
index 00000000..a47aaaef
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h
@@ -0,0 +1,436 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_pcd.h
+  * @author  MCD Application Team
+  * @brief   Header file of PCD HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_PCD_H
+#define STM32H7xx_HAL_PCD_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_ll_usb.h"
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup PCD
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup PCD_Exported_Types PCD Exported Types
+  * @{
+  */
+
+/**
+  * @brief  PCD State structure definition
+  */
+typedef enum
+{
+  HAL_PCD_STATE_RESET   = 0x00,
+  HAL_PCD_STATE_READY   = 0x01,
+  HAL_PCD_STATE_ERROR   = 0x02,
+  HAL_PCD_STATE_BUSY    = 0x03,
+  HAL_PCD_STATE_TIMEOUT = 0x04
+} PCD_StateTypeDef;
+
+/* Device LPM suspend state */
+typedef enum
+{
+  LPM_L0 = 0x00, /* on */
+  LPM_L1 = 0x01, /* LPM L1 sleep */
+  LPM_L2 = 0x02, /* suspend */
+  LPM_L3 = 0x03, /* off */
+} PCD_LPM_StateTypeDef;
+
+typedef enum
+{
+  PCD_LPM_L0_ACTIVE = 0x00, /* on */
+  PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
+} PCD_LPM_MsgTypeDef;
+
+typedef enum
+{
+  PCD_BCD_ERROR                     = 0xFF,
+  PCD_BCD_CONTACT_DETECTION         = 0xFE,
+  PCD_BCD_STD_DOWNSTREAM_PORT       = 0xFD,
+  PCD_BCD_CHARGING_DOWNSTREAM_PORT  = 0xFC,
+  PCD_BCD_DEDICATED_CHARGING_PORT   = 0xFB,
+  PCD_BCD_DISCOVERY_COMPLETED       = 0x00,
+
+} PCD_BCD_MsgTypeDef;
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+typedef USB_OTG_GlobalTypeDef  PCD_TypeDef;
+typedef USB_OTG_CfgTypeDef     PCD_InitTypeDef;
+typedef USB_OTG_EPTypeDef      PCD_EPTypeDef;
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+/**
+  * @brief  PCD Handle Structure definition
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+typedef struct __PCD_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  PCD_TypeDef             *Instance;   /*!< Register base address              */
+  PCD_InitTypeDef         Init;        /*!< PCD required parameters            */
+  __IO uint8_t            USB_Address; /*!< USB Address                        */
+  PCD_EPTypeDef           IN_ep[16];   /*!< IN endpoint parameters             */
+  PCD_EPTypeDef           OUT_ep[16];  /*!< OUT endpoint parameters            */
+  HAL_LockTypeDef         Lock;        /*!< PCD peripheral status              */
+  __IO PCD_StateTypeDef   State;       /*!< PCD communication state            */
+  __IO  uint32_t          ErrorCode;   /*!< PCD Error code                     */
+  uint32_t                Setup[12];   /*!< Setup packet buffer                */
+  PCD_LPM_StateTypeDef    LPM_State;   /*!< LPM State                          */
+  uint32_t                BESL;
+
+
+  uint32_t lpm_active;                 /*!< Enable or disable the Link Power Management .
+                                       This parameter can be set to ENABLE or DISABLE        */
+
+  uint32_t battery_charging_active;    /*!< Enable or disable Battery charging.
+                                       This parameter can be set to ENABLE or DISABLE        */
+  void                    *pData;      /*!< Pointer to upper stack Handler */
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+  void (* SOFCallback)(struct __PCD_HandleTypeDef *hpcd);                              /*!< USB OTG PCD SOF callback                */
+  void (* SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd);                       /*!< USB OTG PCD Setup Stage callback        */
+  void (* ResetCallback)(struct __PCD_HandleTypeDef *hpcd);                            /*!< USB OTG PCD Reset callback              */
+  void (* SuspendCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Suspend callback            */
+  void (* ResumeCallback)(struct __PCD_HandleTypeDef *hpcd);                           /*!< USB OTG PCD Resume callback             */
+  void (* ConnectCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Connect callback            */
+  void (* DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd);                       /*!< USB OTG PCD Disconnect callback         */
+
+  void (* DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);      /*!< USB OTG PCD Data OUT Stage callback     */
+  void (* DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);       /*!< USB OTG PCD Data IN Stage callback      */
+  void (* ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);  /*!< USB OTG PCD ISO OUT Incomplete callback */
+  void (* ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);   /*!< USB OTG PCD ISO IN Incomplete callback  */
+  void (* BCDCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);      /*!< USB OTG PCD BCD callback                */
+  void (* LPMCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);      /*!< USB OTG PCD LPM callback                */
+
+  void (* MspInitCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Msp Init callback           */
+  void (* MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd);                        /*!< USB OTG PCD Msp DeInit callback         */
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+} PCD_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Include PCD HAL Extended module */
+#include "stm32h7xx_hal_pcd_ex.h"
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PCD_Exported_Constants PCD Exported Constants
+  * @{
+  */
+
+/** @defgroup PCD_Speed PCD Speed
+  * @{
+  */
+#define PCD_SPEED_HIGH               USBD_HS_SPEED
+#define PCD_SPEED_HIGH_IN_FULL       USBD_HSINFS_SPEED
+#define PCD_SPEED_FULL               USBD_FS_SPEED
+/**
+  * @}
+  */
+
+/** @defgroup PCD_PHY_Module PCD PHY Module
+  * @{
+  */
+#define PCD_PHY_ULPI                 1U
+#define PCD_PHY_EMBEDDED             2U
+#define PCD_PHY_UTMI                 3U
+/**
+  * @}
+  */
+
+/** @defgroup PCD_Error_Code_definition PCD Error Code definition
+  * @brief  PCD Error Code definition
+  * @{
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+#define  HAL_PCD_ERROR_INVALID_CALLBACK                        (0x00000010U)    /*!< Invalid Callback error  */
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup PCD_Exported_Macros PCD Exported Macros
+ *  @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+#define __HAL_PCD_ENABLE(__HANDLE__)                       (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_PCD_DISABLE(__HANDLE__)                      (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
+
+#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) &=  (__INTERRUPT__))
+#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
+
+
+#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__)             *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
+                                                          ~(USB_OTG_PCGCCTL_STOPCLK)
+
+#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__)               *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
+
+#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__)            ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)
+
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT()    EXTI_D1->IMR2 |= (USB_OTG_HS_WAKEUP_EXTI_LINE)
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT()   EXTI_D1->IMR2 &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT()    EXTI_D1->IMR2 |= (USB_OTG_FS_WAKEUP_EXTI_LINE)
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT()   EXTI_D1->IMR2 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PCD_Exported_Functions PCD Exported Functions
+  * @{
+  */
+
+/* Initialization/de-initialization functions  ********************************/
+/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+/** @defgroup HAL_PCD_Callback_ID_enumeration_definition HAL USB OTG PCD Callback ID enumeration definition
+  * @brief  HAL USB OTG PCD Callback ID enumeration definition
+  * @{
+  */
+typedef enum
+{
+  HAL_PCD_SOF_CB_ID          = 0x01,      /*!< USB PCD SOF callback ID          */
+  HAL_PCD_SETUPSTAGE_CB_ID   = 0x02,      /*!< USB PCD Setup Stage callback ID  */
+  HAL_PCD_RESET_CB_ID        = 0x03,      /*!< USB PCD Reset callback ID        */
+  HAL_PCD_SUSPEND_CB_ID      = 0x04,      /*!< USB PCD Suspend callback ID      */
+  HAL_PCD_RESUME_CB_ID       = 0x05,      /*!< USB PCD Resume callback ID       */
+  HAL_PCD_CONNECT_CB_ID      = 0x06,      /*!< USB PCD Connect callback ID      */
+  HAL_PCD_DISCONNECT_CB_ID  = 0x07,      /*!< USB PCD Disconnect callback ID   */
+
+  HAL_PCD_MSPINIT_CB_ID      = 0x08,      /*!< USB PCD MspInit callback ID      */
+  HAL_PCD_MSPDEINIT_CB_ID    = 0x09       /*!< USB PCD MspDeInit callback ID    */
+
+} HAL_PCD_CallbackIDTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup HAL_PCD_Callback_pointer_definition HAL USB OTG PCD Callback pointer definition
+  * @brief  HAL USB OTG PCD Callback pointer definition
+  * @{
+  */
+
+typedef void (*pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd);                                   /*!< pointer to a common USB OTG PCD callback function  */
+typedef void (*pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);        /*!< pointer to USB OTG PCD Data OUT Stage callback     */
+typedef void (*pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);         /*!< pointer to USB OTG PCD Data IN Stage callback      */
+typedef void (*pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);        /*!< pointer to USB OTG PCD ISO OUT Incomplete callback */
+typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);         /*!< pointer to USB OTG PCD ISO IN Incomplete callback  */
+typedef void (*pPCD_LpmCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);        /*!< pointer to USB OTG PCD LPM callback                */
+typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);        /*!< pointer to USB OTG PCD BCD callback                */
+
+/**
+  * @}
+  */
+
+HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/* I/O operation functions  ***************************************************/
+/* Non-Blocking mode: Interrupt */
+/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
+
+void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
+
+void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+/**
+  * @}
+  */
+
+/* Peripheral Control functions  **********************************************/
+/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
+HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
+uint32_t          HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
+/**
+  * @}
+  */
+
+/* Peripheral State functions  ************************************************/
+/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
+  * @{
+  */
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup PCD_Private_Constants PCD Private Constants
+  * @{
+  */
+/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt
+  * @{
+  */
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE                            0x08U
+#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE                           0x0CU
+#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE                    0x10U
+
+#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE                            0x08U
+#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE                           0x0CU
+#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE                    0x10U
+
+#define USB_OTG_FS_WAKEUP_EXTI_LINE                                   (0x1U << 12)  /*!< USB FS EXTI Line WakeUp Interrupt */
+#define USB_OTG_HS_WAKEUP_EXTI_LINE                                   (0x1U << 11)  /*!< USB HS EXTI Line WakeUp Interrupt */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+#ifndef USB_OTG_DOEPINT_OTEPSPR
+#define USB_OTG_DOEPINT_OTEPSPR                (0x1UL << 5)      /*!< Status Phase Received interrupt */
+#endif
+
+#ifndef USB_OTG_DOEPMSK_OTEPSPRM
+#define USB_OTG_DOEPMSK_OTEPSPRM               (0x1UL << 5)      /*!< Setup Packet Received interrupt mask */
+#endif
+
+#ifndef USB_OTG_DOEPINT_NAK
+#define USB_OTG_DOEPINT_NAK                    (0x1UL << 13)      /*!< NAK interrupt */
+#endif
+
+#ifndef USB_OTG_DOEPMSK_NAKM
+#define USB_OTG_DOEPMSK_NAKM                   (0x1UL << 13)      /*!< OUT Packet NAK interrupt mask */
+#endif
+
+#ifndef USB_OTG_DOEPINT_STPKTRX
+#define USB_OTG_DOEPINT_STPKTRX                (0x1UL << 15)      /*!< Setup Packet Received interrupt */
+#endif
+
+#ifndef USB_OTG_DOEPMSK_NYETM
+#define USB_OTG_DOEPMSK_NYETM                  (0x1UL << 14)      /*!< Setup Packet Received interrupt mask */
+#endif
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PCD_Private_Macros PCD Private Macros
+ * @{
+ */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_PCD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h
new file mode 100644
index 00000000..21d5b92f
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h
@@ -0,0 +1,91 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_pcd_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of PCD HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_PCD_EX_H
+#define STM32H7xx_HAL_PCD_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup PCDEx
+  * @{
+  */
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
+  * @{
+  */
+/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
+  * @{
+  */
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
+HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+
+HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
+
+
+HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd);
+void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd);
+
+void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
+void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32H7xx_HAL_PCD_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h
new file mode 100644
index 00000000..0d462402
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h
@@ -0,0 +1,774 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_pwr.h
+  * @author  MCD Application Team
+  * @brief   Header file of PWR HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_PWR_H
+#define STM32H7xx_HAL_PWR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup PWR
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Types PWR Exported Types
+  * @{
+  */
+
+/**
+  * @brief  PWR PVD configuration structure definition
+  */
+typedef struct
+{
+  uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. This
+                                    parameter can be a value of @ref
+                                    PWR_PVD_detection_level.
+                     */
+
+  uint32_t Mode;     /*!< Mode: Specifies the EXTI operating mode for the PVD
+                                event. This parameter can be a value of @ref
+                                PWR_PVD_Mode.
+                     */
+}PWR_PVDTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PWR_Exported_Constants PWR Exported Constants
+  * @{
+  */
+
+/** @defgroup PWR_PVD_detection_level PWR PVD detection level
+  * @{
+  */
+#define PWR_PVDLEVEL_0  PWR_CR1_PLS_LEV0  /*!< Programmable voltage detector
+                                               level 0 selection : 1V95       */
+#define PWR_PVDLEVEL_1  PWR_CR1_PLS_LEV1  /*!< Programmable voltage detector
+                                               level 1 selection : 2V1        */
+#define PWR_PVDLEVEL_2  PWR_CR1_PLS_LEV2  /*!< Programmable voltage detector
+                                               level 2 selection : 2V25       */
+#define PWR_PVDLEVEL_3  PWR_CR1_PLS_LEV3  /*!< Programmable voltage detector
+                                               level 3 selection : 2V4        */
+#define PWR_PVDLEVEL_4  PWR_CR1_PLS_LEV4  /*!< Programmable voltage detector
+                                               level 4 selection : 2V55       */
+#define PWR_PVDLEVEL_5  PWR_CR1_PLS_LEV5  /*!< Programmable voltage detector
+                                               level 5 selection : 2V7        */
+#define PWR_PVDLEVEL_6  PWR_CR1_PLS_LEV6  /*!< Programmable voltage detector
+                                               level 6 selection : 2V85       */
+#define PWR_PVDLEVEL_7  PWR_CR1_PLS_LEV7  /*!< External input analog voltage
+                                               (Compare internally to VREF)   */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_PVD_Mode PWR PVD Mode
+  * @{
+  */
+#define PWR_PVD_MODE_NORMAL               (0x00000000U) /*!< Basic mode is used                                        */
+#define PWR_PVD_MODE_IT_RISING            (0x00010001U) /*!< Interrupt Mode with Rising edge trigger detection         */
+#define PWR_PVD_MODE_IT_FALLING           (0x00010002U) /*!< Interrupt Mode with Falling edge trigger detection        */
+#define PWR_PVD_MODE_IT_RISING_FALLING    (0x00010003U) /*!< Interrupt Mode with Rising/Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING         (0x00020001U) /*!< Event Mode with Rising edge trigger detection             */
+#define PWR_PVD_MODE_EVENT_FALLING        (0x00020002U) /*!< Event Mode with Falling edge trigger detection            */
+#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection     */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
+  * @{
+  */
+#define PWR_MAINREGULATOR_ON      (0U)
+#define PWR_LOWPOWERREGULATOR_ON  PWR_CR1_LPDS
+/**
+  * @}
+  */
+
+/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
+  * @{
+  */
+#define PWR_SLEEPENTRY_WFI  (0x01U)
+#define PWR_SLEEPENTRY_WFE  (0x02U)
+/**
+  * @}
+  */
+
+/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
+  * @{
+  */
+#define PWR_STOPENTRY_WFI  (0x01U)
+#define PWR_STOPENTRY_WFE  (0x02U)
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale
+  * @{
+  */
+#if defined(PWR_SRDCR_VOS)
+#define PWR_REGULATOR_VOLTAGE_SCALE0  (PWR_SRDCR_VOS_1 | PWR_SRDCR_VOS_0)
+#define PWR_REGULATOR_VOLTAGE_SCALE1  (PWR_SRDCR_VOS_1)
+#define PWR_REGULATOR_VOLTAGE_SCALE2  (PWR_SRDCR_VOS_0)
+#define PWR_REGULATOR_VOLTAGE_SCALE3  (0U)
+#else
+#define PWR_REGULATOR_VOLTAGE_SCALE0  (0U)
+#define PWR_REGULATOR_VOLTAGE_SCALE1  (PWR_D3CR_VOS_1 | PWR_D3CR_VOS_0)
+#define PWR_REGULATOR_VOLTAGE_SCALE2  (PWR_D3CR_VOS_1)
+#define PWR_REGULATOR_VOLTAGE_SCALE3  (PWR_D3CR_VOS_0)
+#endif /* PWR_SRDCR_VOS */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Flag PWR Flag
+  * @{
+  */
+/* PWR CPU flag */
+#define PWR_FLAG_STOP       (0x01U)
+#if defined (PWR_CPUCR_SBF_D2)
+#define PWR_FLAG_SB_D1      (0x02U)
+#define PWR_FLAG_SB_D2      (0x03U)
+#endif /* defined (PWR_CPUCR_SBF_D2) */
+#define PWR_FLAG_SB         (0x04U)
+#if defined (DUAL_CORE)
+#define PWR_FLAG_CPU_HOLD   (0x05U)
+#define PWR_FLAG_CPU2_HOLD  (0x06U)
+#define PWR_FLAG2_STOP      (0x07U)
+#define PWR_FLAG2_SB_D1     (0x08U)
+#define PWR_FLAG2_SB_D2     (0x09U)
+#define PWR_FLAG2_SB        (0x0AU)
+#endif /* defined (DUAL_CORE) */
+#define PWR_FLAG_PVDO       (0x0BU)
+#define PWR_FLAG_AVDO       (0x0CU)
+#define PWR_FLAG_ACTVOSRDY  (0x0DU)
+#define PWR_FLAG_ACTVOS     (0x0EU)
+#define PWR_FLAG_BRR        (0x0FU)
+#define PWR_FLAG_VOSRDY     (0x10U)
+#if defined (SMPS)
+#define PWR_FLAG_SMPSEXTRDY (0x11U)
+#else
+#define PWR_FLAG_SCUEN      (0x11U)
+#endif /* defined (SMPS) */
+#if defined (PWR_CSR1_MMCVDO)
+#define PWR_FLAG_MMCVDO     (0x12U)
+#endif /* defined (PWR_CSR1_MMCVDO) */
+#define PWR_FLAG_USB33RDY   (0x13U)
+#define PWR_FLAG_TEMPH      (0x14U)
+#define PWR_FLAG_TEMPL      (0x15U)
+#define PWR_FLAG_VBATH      (0x16U)
+#define PWR_FLAG_VBATL      (0x17U)
+
+/* PWR Wake up flag */
+#define PWR_FLAG_WKUP1 PWR_WKUPCR_WKUPC1
+#define PWR_FLAG_WKUP2 PWR_WKUPCR_WKUPC2
+#define PWR_FLAG_WKUP3 PWR_WKUPCR_WKUPC3
+#define PWR_FLAG_WKUP4 PWR_WKUPCR_WKUPC4
+#define PWR_FLAG_WKUP5 PWR_WKUPCR_WKUPC5
+#define PWR_FLAG_WKUP6 PWR_WKUPCR_WKUPC6
+/**
+  * @}
+  */
+
+/** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask
+  * @{
+  */
+#define  PWR_EWUP_MASK  (0x0FFF3F3FU)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PWR_Exported_Macro PWR Exported Macro
+  * @{
+  */
+
+/** @brief  Configure the main internal regulator output voltage.
+  * @param  __REGULATOR__ : Specifies the regulator output voltage to achieve a
+  *                         trade-off between performance and power consumption
+  *                         when the device does not operate at the maximum
+  *                         frequency (refer to the datasheet for more details).
+  *          This parameter can be one of the following values:
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE0 : Regulator voltage output
+  *                                                Scale 0 mode.
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output
+  *                                                Scale 1 mode.
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output
+  *                                                Scale 2 mode.
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output
+  *                                                Scale 3 mode.
+  * @note   For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines,
+  *         configuring Voltage Scale 0 is only possible when Vcore is supplied
+  *         from LDO (Low DropOut). The SYSCFG Clock must be enabled through
+  *         __HAL_RCC_SYSCFG_CLK_ENABLE() macro before configuring Voltage Scale
+  *         0 using __HAL_PWR_VOLTAGESCALING_CONFIG().
+  *         Transition to Voltage Scale 0 is only possible when the system is
+  *         already in Voltage Scale 1.
+  *         Transition from Voltage Scale 0 is only possible to Voltage Scale 1
+  *         then once in Voltage Scale 1 it is possible to switch to another
+  *         voltage scale.
+  *         After each regulator voltage setting, wait on VOSRDY flag to be set
+  *         using macro __HAL_PWR_GET_FLAG().
+  *         To enter low power mode , and if current regulator voltage is
+  *         Voltage Scale 0 then first switch to Voltage Scale 1 before entering
+  *         low power mode.
+  * @retval None.
+  */
+#if defined(PWR_SRDCR_VOS) /* STM32H7Axxx and STM32H7Bxxx lines */
+#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__)                         \
+do {                                                                           \
+      __IO uint32_t tmpreg = 0x00;                                             \
+      MODIFY_REG(PWR->SRDCR, PWR_SRDCR_VOS, (__REGULATOR__));                  \
+      /* Delay after setting the voltage scaling */                            \
+      tmpreg = READ_BIT(PWR->SRDCR, PWR_SRDCR_VOS);                            \
+      UNUSED(tmpreg);                                                          \
+} while(0)
+#else /* All H7 lines except STM32H7Axxx and STM32H7Bxxx lines */
+#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__)                         \
+do {                                                                           \
+      __IO uint32_t tmpreg = 0x00;                                             \
+      /* Check the voltage scaling to be configured */                         \
+      if((__REGULATOR__) == PWR_REGULATOR_VOLTAGE_SCALE0)                      \
+      {                                                                        \
+        /* Configure the Voltage Scaling 1 */                                  \
+        MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);     \
+        /* Delay after setting the voltage scaling */                          \
+        tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS);                            \
+        /* Enable the PWR overdrive */                                         \
+        SET_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);                             \
+        /* Delay after setting the syscfg boost setting */                     \
+        tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);                   \
+      }                                                                        \
+      else                                                                     \
+      {                                                                        \
+        /* Disable the PWR overdrive */                                        \
+        CLEAR_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);                           \
+        /* Delay after setting the syscfg boost setting */                     \
+        tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);                   \
+        /* Configure the Voltage Scaling x */                                  \
+        MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__));                  \
+        /* Delay after setting the voltage scaling */                          \
+        tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS);                            \
+      }                                                                        \
+      UNUSED(tmpreg);                                                          \
+} while(0)
+#endif /* PWR_SRDCR_VOS */
+
+/** @brief  Check PWR flags are set or not.
+  * @param  __FLAG__ : Specifies the flag to check.
+  *           This parameter can be one of the following values:
+  *            @arg PWR_FLAG_PVDO : PVD Output. This flag is valid only if PVD
+  *                                 is enabled by the HAL_PWR_EnablePVD()
+  *                                 function.
+  *                                 The PVD is stopped by STANDBY mode. For this
+  *                                 reason, this bit is equal to 0 after STANDBY
+  *                                 or reset until the PVDE bit is set.
+  *            @arg PWR_FLAG_AVDO : AVD Output. This flag is valid only if AVD
+  *                                 is enabled by the HAL_PWREx_EnableAVD()
+  *                                 function. The AVD is stopped by STANDBY mode.
+  *                                 For this reason, this bit is equal to 0
+  *                                 after STANDBY or reset until the AVDE bit
+  *                                 is set.
+  *            @arg PWR_FLAG_ACTVOSRDY : This flag indicates that the Regulator
+  *                                      voltage scaling output selection is
+  *                                      ready.
+  *            @arg PWR_FLAG_BRR : Backup regulator ready flag. This bit is not
+  *                                reset when the device wakes up from STANDBY
+  *                                mode or by a system reset or power-on reset.
+  *            @arg PWR_FLAG_VOSRDY : This flag indicates that the Regulator
+  *                                   voltage scaling output selection is ready.
+  *                                mode or by a system reset or power-on reset.
+  *            @arg PWR_FLAG_USB33RDY : This flag indicates that the USB supply
+  *                                     from regulator is ready.
+  *            @arg PWR_FLAG_TEMPH : This flag indicates that the temperature
+  *                                  equal or above high threshold level.
+  *            @arg PWR_FLAG_TEMPL : This flag indicates that the temperature
+  *                                  equal or below low threshold level.
+  *            @arg PWR_FLAG_VBATH : This flag indicates that VBAT level equal
+  *                                  or above high threshold level.
+  *            @arg PWR_FLAG_VBATL : This flag indicates that VBAT level equal
+  *                                  or below low threshold level.
+  *            @arg PWR_FLAG_STOP : This flag indicates that the system entered
+  *                                 in STOP mode.
+  *            @arg PWR_FLAG_SB : This flag indicates that the system entered in
+  *                               STANDBY mode.
+  *            @arg PWR_FLAG_SB_D1 : This flag indicates that the D1 domain
+  *                                  entered in STANDBY mode.
+  *            @arg PWR_FLAG_SB_D2 : This flag indicates that the D2 domain
+  *                                  entered in STANDBY mode.
+  *            @arg PWR_FLAG2_STOP : This flag indicates that the system entered
+  *                                 in STOP mode.
+  *            @arg PWR_FLAG2_SB : This flag indicates that the system entered
+  *                                in STANDBY mode.
+  *            @arg PWR_FLAG2_SB_D1 : This flag indicates that the D1 domain
+  *                                   entered in STANDBY mode.
+  *            @arg PWR_FLAG2_SB_D2 : This flag indicates that the D2 domain
+  *                                   entered in STANDBY mode.
+  *            @arg PWR_FLAG_CPU_HOLD : This flag indicates that the CPU1 wakes
+  *                                     up with hold.
+  *            @arg PWR_FLAG_CPU2_HOLD : This flag indicates that the CPU2 wakes
+  *                                      up with hold.
+  *            @arg PWR_FLAG_SMPSEXTRDY : This flag indicates that the SMPS
+  *                                       External supply is sready.
+  *            @arg PWR_FLAG_SCUEN : This flag indicates that the supply
+  *                                  configuration update is enabled.
+  *            @arg PWR_FLAG_MMCVDO : This flag indicates that the VDDMMC is
+  *                                   above or equal to 1.2 V.
+  * @note   The PWR_FLAG_PVDO, PWR_FLAG_AVDO, PWR_FLAG_ACTVOSRDY, PWR_FLAG_BRR,
+  *         PWR_FLAG_VOSRDY, PWR_FLAG_USB33RDY, PWR_FLAG_TEMPH, PWR_FLAG_TEMPL,
+  *         PWR_FLAG_VBATH, PWR_FLAG_VBATL, PWR_FLAG_STOP and PWR_FLAG_SB flags
+  *         are used for all H7 family lines.
+  *         The PWR_FLAG2_STOP, PWR_FLAG2_SB, PWR_FLAG2_SB_D1, PWR_FLAG2_SB_D2,
+  *         PWR_FLAG_CPU_HOLD and PWR_FLAG_CPU2_HOLD flags are used only for H7
+  *         dual core lines.
+  *         The PWR_FLAG_SB_D1 and PWR_FLAG_SB_D2 flags are used for all H7
+  *         family except STM32H7Axxx and STM32H7Bxxx lines.
+  *         The PWR_FLAG_MMCVDO flag is used only for STM32H7Axxx and
+  *         STM32H7Bxxx lines.
+  *         The PWR_FLAG_SCUEN flag is used for STM32H743, STM32H753, STM32H742,
+  *         STM32H750, STM32H7Axx and STM32H7Bxx lines.
+  *         The PWR_FLAG_SMPSEXTRDY flag is used for dual core and STM32H7AxxQ,
+  *         STM32H7BxxQ lines.
+  * @retval The (__FLAG__) state (TRUE or FALSE).
+  */
+#if defined (DUAL_CORE) /* Dual core lines */
+#define __HAL_PWR_GET_FLAG(__FLAG__)                                                              \
+(((__FLAG__) == PWR_FLAG_PVDO)       ? ((PWR->CSR1 & PWR_CSR1_PVDO)       == PWR_CSR1_PVDO)      :\
+ ((__FLAG__) == PWR_FLAG_AVDO)       ? ((PWR->CSR1 & PWR_CSR1_AVDO)       == PWR_CSR1_AVDO)      :\
+ ((__FLAG__) == PWR_FLAG_ACTVOSRDY)  ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY)  == PWR_CSR1_ACTVOSRDY) :\
+ ((__FLAG__) == PWR_FLAG_VOSRDY)     ? ((PWR->D3CR & PWR_D3CR_VOSRDY)     == PWR_D3CR_VOSRDY)    :\
+ ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_CR3_SMPSEXTRDY)   == PWR_CR3_SMPSEXTRDY) :\
+ ((__FLAG__) == PWR_FLAG_BRR)        ? ((PWR->CR2 & PWR_CR2_BRRDY)        == PWR_CR2_BRRDY)      :\
+ ((__FLAG__) == PWR_FLAG_CPU_HOLD)   ? ((PWR->CPU2CR & PWR_CPU2CR_HOLD1F) == PWR_CPU2CR_HOLD1F)  :\
+ ((__FLAG__) == PWR_FLAG_CPU2_HOLD)  ? ((PWR->CPUCR & PWR_CPUCR_HOLD2F)   == PWR_CPUCR_HOLD2F)   :\
+ ((__FLAG__) == PWR_FLAG_SB)         ? ((PWR->CPUCR & PWR_CPUCR_SBF)      == PWR_CPUCR_SBF)      :\
+ ((__FLAG__) == PWR_FLAG2_SB)        ? ((PWR->CPU2CR & PWR_CPU2CR_SBF)    == PWR_CPU2CR_SBF)     :\
+ ((__FLAG__) == PWR_FLAG_STOP)       ? ((PWR->CPUCR & PWR_CPUCR_STOPF)    == PWR_CPUCR_STOPF)    :\
+ ((__FLAG__) == PWR_FLAG2_STOP)      ? ((PWR->CPU2CR & PWR_CPU2CR_STOPF)  == PWR_CPU2CR_STOPF)   :\
+ ((__FLAG__) == PWR_FLAG_SB_D1)      ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1)   == PWR_CPUCR_SBF_D1)   :\
+ ((__FLAG__) == PWR_FLAG2_SB_D1)     ? ((PWR->CPU2CR & PWR_CPU2CR_SBF_D1) == PWR_CPU2CR_SBF_D1)  :\
+ ((__FLAG__) == PWR_FLAG_SB_D2)      ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2)   == PWR_CPUCR_SBF_D2)   :\
+ ((__FLAG__) == PWR_FLAG2_SB_D2)     ? ((PWR->CPU2CR & PWR_CPU2CR_SBF_D2) == PWR_CPU2CR_SBF_D2)  :\
+ ((__FLAG__) == PWR_FLAG_USB33RDY)   ? ((PWR->CR3 & PWR_CR3_USB33RDY)     == PWR_CR3_USB33RDY)   :\
+ ((__FLAG__) == PWR_FLAG_TEMPH)      ? ((PWR->CR2 & PWR_CR2_TEMPH)        == PWR_CR2_TEMPH)      :\
+ ((__FLAG__) == PWR_FLAG_TEMPL)      ? ((PWR->CR2 & PWR_CR2_TEMPL)        == PWR_CR2_TEMPL)      :\
+ ((__FLAG__) == PWR_FLAG_VBATH)      ? ((PWR->CR2 & PWR_CR2_VBATH)        == PWR_CR2_VBATH)      :\
+ ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
+#else /* Single core lines */
+#if defined (PWR_CPUCR_SBF_D2) /* STM32H743, STM32H753, STM32H742 and STM32H750 lines */
+#define __HAL_PWR_GET_FLAG(__FLAG__)                                                            \
+(((__FLAG__) == PWR_FLAG_PVDO)      ? ((PWR->CSR1 & PWR_CSR1_PVDO)      == PWR_CSR1_PVDO)      :\
+ ((__FLAG__) == PWR_FLAG_AVDO)      ? ((PWR->CSR1 & PWR_CSR1_AVDO)      == PWR_CSR1_AVDO)      :\
+ ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
+ ((__FLAG__) == PWR_FLAG_VOSRDY)    ? ((PWR->D3CR & PWR_D3CR_VOSRDY)    == PWR_D3CR_VOSRDY)    :\
+ ((__FLAG__) == PWR_FLAG_SCUEN)     ? ((PWR->CR3 & PWR_CR3_SCUEN)       == PWR_CR3_SCUEN)      :\
+ ((__FLAG__) == PWR_FLAG_BRR)       ? ((PWR->CR2 & PWR_CR2_BRRDY)       == PWR_CR2_BRRDY)      :\
+ ((__FLAG__) == PWR_FLAG_SB)        ? ((PWR->CPUCR & PWR_CPUCR_SBF)     == PWR_CPUCR_SBF)      :\
+ ((__FLAG__) == PWR_FLAG_STOP)      ? ((PWR->CPUCR & PWR_CPUCR_STOPF)   == PWR_CPUCR_STOPF)    :\
+ ((__FLAG__) == PWR_FLAG_SB_D1)     ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1)  == PWR_CPUCR_SBF_D1)   :\
+ ((__FLAG__) == PWR_FLAG_SB_D2)     ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2)  == PWR_CPUCR_SBF_D2)   :\
+ ((__FLAG__) == PWR_FLAG_USB33RDY)  ? ((PWR->CR3 & PWR_CR3_USB33RDY)    == PWR_CR3_USB33RDY)   :\
+ ((__FLAG__) == PWR_FLAG_TEMPH)     ? ((PWR->CR2 & PWR_CR2_TEMPH)       == PWR_CR2_TEMPH)      :\
+ ((__FLAG__) == PWR_FLAG_TEMPL)     ? ((PWR->CR2 & PWR_CR2_TEMPL)       == PWR_CR2_TEMPL)      :\
+ ((__FLAG__) == PWR_FLAG_VBATH)     ? ((PWR->CR2 & PWR_CR2_VBATH)       == PWR_CR2_VBATH)      :\
+ ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
+#else /* STM32H7Axxx and STM32H7Bxxx lines */
+#if defined (SMPS) /* STM32H7AxxQ and STM32H7BxxQ SMPS lines */
+#define __HAL_PWR_GET_FLAG(__FLAG__)                                                            \
+(((__FLAG__) == PWR_FLAG_PVDO)       ? ((PWR->CSR1 & PWR_CSR1_PVDO)      == PWR_CSR1_PVDO)      :\
+ ((__FLAG__) == PWR_FLAG_AVDO)       ? ((PWR->CSR1 & PWR_CSR1_AVDO)      == PWR_CSR1_AVDO)      :\
+ ((__FLAG__) == PWR_FLAG_ACTVOSRDY)  ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
+ ((__FLAG__) == PWR_FLAG_BRR)        ? ((PWR->CR2 & PWR_CR2_BRRDY)       == PWR_CR2_BRRDY)      :\
+ ((__FLAG__) == PWR_FLAG_VOSRDY)     ? ((PWR->SRDCR & PWR_SRDCR_VOSRDY)  == PWR_SRDCR_VOSRDY)   :\
+ ((__FLAG__) == PWR_FLAG_STOP)       ? ((PWR->CPUCR & PWR_CPUCR_STOPF)   == PWR_CPUCR_STOPF)    :\
+ ((__FLAG__) == PWR_FLAG_SB)         ? ((PWR->CPUCR & PWR_CPUCR_SBF)     == PWR_CPUCR_SBF)      :\
+ ((__FLAG__) == PWR_FLAG_MMCVDO)     ? ((PWR->CSR1 & PWR_CSR1_MMCVDO)    == PWR_CSR1_MMCVDO)    :\
+ ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_CR3_SMPSEXTRDY)  == PWR_CR3_SMPSEXTRDY) :\
+ ((__FLAG__) == PWR_FLAG_USB33RDY)   ? ((PWR->CR3 & PWR_CR3_USB33RDY)    == PWR_CR3_USB33RDY)   :\
+ ((__FLAG__) == PWR_FLAG_TEMPH)      ? ((PWR->CR2 & PWR_CR2_TEMPH)       == PWR_CR2_TEMPH)      :\
+ ((__FLAG__) == PWR_FLAG_TEMPL)      ? ((PWR->CR2 & PWR_CR2_TEMPL)       == PWR_CR2_TEMPL)      :\
+ ((__FLAG__) == PWR_FLAG_VBATH)      ? ((PWR->CR2 & PWR_CR2_VBATH)       == PWR_CR2_VBATH)      :\
+ ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
+#else /* STM32H7Axx and STM32H7Bxx LDO lines */
+#define __HAL_PWR_GET_FLAG(__FLAG__)                                    \
+(((__FLAG__) == PWR_FLAG_PVDO)      ? ((PWR->CSR1 & PWR_CSR1_PVDO)      == PWR_CSR1_PVDO)      :\
+ ((__FLAG__) == PWR_FLAG_AVDO)      ? ((PWR->CSR1 & PWR_CSR1_AVDO)      == PWR_CSR1_AVDO)      :\
+ ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
+ ((__FLAG__) == PWR_FLAG_BRR)       ? ((PWR->CR2 & PWR_CR2_BRRDY)       == PWR_CR2_BRRDY)      :\
+ ((__FLAG__) == PWR_FLAG_VOSRDY)    ? ((PWR->SRDCR & PWR_SRDCR_VOSRDY)  == PWR_SRDCR_VOSRDY)   :\
+ ((__FLAG__) == PWR_FLAG_SCUEN)     ? ((PWR->CR3 & PWR_CR3_SCUEN)       == PWR_CR3_SCUEN)      :\
+ ((__FLAG__) == PWR_FLAG_STOP)      ? ((PWR->CPUCR & PWR_CPUCR_STOPF)   == PWR_CPUCR_STOPF)    :\
+ ((__FLAG__) == PWR_FLAG_SB)        ? ((PWR->CPUCR & PWR_CPUCR_SBF)     == PWR_CPUCR_SBF)      :\
+ ((__FLAG__) == PWR_FLAG_MMCVDO)    ? ((PWR->CSR1 & PWR_CSR1_MMCVDO)    == PWR_CSR1_MMCVDO)    :\
+ ((__FLAG__) == PWR_FLAG_USB33RDY)  ? ((PWR->CR3 & PWR_CR3_USB33RDY)    == PWR_CR3_USB33RDY)   :\
+ ((__FLAG__) == PWR_FLAG_TEMPH)     ? ((PWR->CR2 & PWR_CR2_TEMPH)       == PWR_CR2_TEMPH)      :\
+ ((__FLAG__) == PWR_FLAG_TEMPL)     ? ((PWR->CR2 & PWR_CR2_TEMPL)       == PWR_CR2_TEMPL)      :\
+ ((__FLAG__) == PWR_FLAG_VBATH)     ? ((PWR->CR2 & PWR_CR2_VBATH)       == PWR_CR2_VBATH)      :\
+ ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
+#endif /* SMPS */
+#endif /* PWR_CPUCR_SBF_D2 */
+#endif /* DUAL_CORE */
+
+/** @brief  Check PWR wake up flags are set or not.
+  * @param  __FLAG__: specifies the wake up flag to check.
+  *           This parameter can be one of the following values:
+  *            @arg PWR_FLAG_WKUP1 : This parameter clear Wake up line 1 flag.
+  *            @arg PWR_FLAG_WKUP2 : This parameter clear Wake up line 2 flag.
+  *            @arg PWR_FLAG_WKUP3 : This parameter clear Wake up line 3 flag.
+  *            @arg PWR_FLAG_WKUP4 : This parameter clear Wake up line 4 flag.
+  *            @arg PWR_FLAG_WKUP5 : This parameter clear Wake up line 5 flag.
+  *            @arg PWR_FLAG_WKUP6 : This parameter clear Wake up line 6 flag.
+  * @retval The (__FLAG__) state (TRUE or FALSE).
+  */
+#define __HAL_PWR_GET_WAKEUPFLAG(__FLAG__) ((PWR->WKUPFR & (__FLAG__)) ? 0 : 1)
+
+#if defined (DUAL_CORE)
+/** @brief  Clear CPU PWR flags.
+  * @param  __FLAG__ : Specifies the flag to clear.
+  * @note   This parameter is not used for the STM32H7 family and is kept as
+  *         parameter just to maintain compatibility with other families.
+  * @note   This macro clear all CPU flags STOPF, SBF, SBF_D1, and SBF_D2.
+  *           This parameter can be one of the following values :
+  *            @arg PWR_CPU_FLAGS : Clear HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2
+  *                                 CPU flags.
+  * @retval None.
+  */
+#define __HAL_PWR_CLEAR_FLAG(__FLAG__)      \
+do {                                        \
+     SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF);   \
+     SET_BIT(PWR->CPU2CR, PWR_CPU2CR_CSSF); \
+} while(0)
+#else
+/** @brief  Clear CPU PWR flags.
+  * @param  __FLAG__ : Specifies the flag to clear.
+  * @note   This parameter is not used for the STM32H7 family and is kept as
+  *         parameter just to maintain compatibility with other families.
+  * @note   This macro clear all CPU flags.
+  *         For STM32H7Axxx and STM32H7Bxxx lines CPU flags are STOPF and SBF.
+  *         For dual core lines flags are HOLDxF, STOPF, SBF and SBF_Dx.
+  * @retval None.
+  */
+#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF)
+#endif /* defined (DUAL_CORE) */
+
+/** @brief  Clear PWR wake up flags.
+  * @param  __FLAG__ : Specifies the wake up flag to be cleared.
+  *           This parameter can be one of the following values :
+  *            @arg PWR_FLAG_WKUP1 : This parameter clear Wake up line 1 flag.
+  *            @arg PWR_FLAG_WKUP2 : This parameter clear Wake up line 2 flag.
+  *            @arg PWR_FLAG_WKUP3 : This parameter clear Wake up line 3 flag.
+  *            @arg PWR_FLAG_WKUP4 : This parameter clear Wake up line 4 flag.
+  *            @arg PWR_FLAG_WKUP5 : This parameter clear Wake up line 5 flag.
+  *            @arg PWR_FLAG_WKUP6 : This parameter clear Wake up line 6 flag.
+  * @retval None.
+  */
+#define __HAL_PWR_CLEAR_WAKEUPFLAG(__FLAG__) SET_BIT(PWR->WKUPCR, (__FLAG__))
+
+/**
+  * @brief Enable the PVD EXTI Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Enable the PVD EXTI D2 Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief Disable the PVD EXTI Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Disable the PVD EXTI D2 Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief   Enable event on PVD EXTI Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Enable event on PVD EXTI D2 Line.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief   Disable event on PVD EXTI Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Disable event on PVD EXTI D2 Line.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief Enable the PVD Rising Interrupt Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Disable the PVD Rising Interrupt Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Enable the PVD Falling Interrupt Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Disable the PVD Falling Interrupt Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Enable the PVD Rising & Falling Interrupt Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
+do {                                                    \
+      __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();          \
+      __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();         \
+} while(0);
+
+/**
+  * @brief Disable the PVD Rising & Falling Interrupt Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
+do {                                                     \
+      __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();          \
+      __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();         \
+} while(0);
+
+/**
+  * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
+  * @retval EXTI PVD Line Status.
+  */
+#define __HAL_PWR_PVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Checks whether the specified PVD EXTI interrupt flag is set or not.
+  * @retval EXTI D2 PVD Line Status.
+  */
+#define __HAL_PWR_PVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief Clear the PVD EXTI flag.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Clear the PVD EXTI D2 flag.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief  Generates a Software interrupt on PVD EXTI line.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
+/**
+  * @}
+  */
+
+/* Include PWR HAL Extension module */
+#include "stm32h7xx_hal_pwr_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PWR_Exported_Functions PWR Exported Functions
+  * @{
+  */
+
+/** @addtogroup PWR_Exported_Functions_Group1 Initialization and De-Initialization functions
+  * @{
+  */
+/* Initialization and de-initialization functions *****************************/
+void HAL_PWR_DeInit(void);
+void HAL_PWR_EnableBkUpAccess(void);
+void HAL_PWR_DisableBkUpAccess(void);
+/**
+  * @}
+  */
+
+/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
+  * @{
+  */
+/* Peripheral Control functions  **********************************************/
+/* PVD configuration */
+void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
+void HAL_PWR_EnablePVD(void);
+void HAL_PWR_DisablePVD(void);
+
+/* WakeUp pins configuration */
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
+
+/* Low Power modes entry */
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
+void HAL_PWR_EnterSTANDBYMode(void);
+
+/* Power PVD IRQ Handler */
+void HAL_PWR_PVD_IRQHandler(void);
+void HAL_PWR_PVDCallback(void);
+
+/* Cortex System Control functions  *******************************************/
+void HAL_PWR_EnableSleepOnExit(void);
+void HAL_PWR_DisableSleepOnExit(void);
+void HAL_PWR_EnableSEVOnPend(void);
+void HAL_PWR_DisableSEVOnPend(void);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup PWR_Private_Constants PWR Private Constants
+  * @{
+  */
+
+/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line
+  * @{
+  */
+#define PWR_EXTI_LINE_PVD  EXTI_IMR1_IM16 /*!< External interrupt line 16
+                                               Connected to the PVD EXTI Line */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PWR_Private_Macros PWR Private Macros
+  * @{
+  */
+
+/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters
+  * @{
+  */
+/* Check PVD level parameter */
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) ||\
+                                 ((LEVEL) == PWR_PVDLEVEL_1) ||\
+                                 ((LEVEL) == PWR_PVDLEVEL_2) ||\
+                                 ((LEVEL) == PWR_PVDLEVEL_3) ||\
+                                 ((LEVEL) == PWR_PVDLEVEL_4) ||\
+                                 ((LEVEL) == PWR_PVDLEVEL_5) ||\
+                                 ((LEVEL) == PWR_PVDLEVEL_6) ||\
+                                 ((LEVEL) == PWR_PVDLEVEL_7))
+
+/* Check PVD mode parameter */
+#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)            ||\
+                               ((MODE) == PWR_PVD_MODE_IT_FALLING)           ||\
+                               ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING)    ||\
+                               ((MODE) == PWR_PVD_MODE_EVENT_RISING)         ||\
+                               ((MODE) == PWR_PVD_MODE_EVENT_FALLING)        ||\
+                               ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) ||\
+                               ((MODE) == PWR_PVD_MODE_NORMAL))
+
+/* Check low power regulator parameter */
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON)   ||\
+                                     ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
+
+/* Check low power mode entry parameter */
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) ||\
+                                   ((ENTRY) == PWR_SLEEPENTRY_WFE))
+
+/* Check low power mode entry parameter */
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) ||\
+                                  ((ENTRY) == PWR_STOPENTRY_WFE))
+
+/* Check voltage scale level parameter */
+#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE0) || \
+                                           ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
+                                           ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
+                                           ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* STM32H7xx_HAL_PWR_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h
new file mode 100644
index 00000000..ebad73c5
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h
@@ -0,0 +1,743 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_pwr_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of PWR HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_PWR_EX_H
+#define STM32H7xx_HAL_PWR_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup PWREx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup PWREx_Exported_Types PWREx Exported Types
+  * @{
+  */
+/**
+  * @brief  PWREx AVD configuration structure definition
+  */
+typedef struct
+{
+  uint32_t AVDLevel; /*!< AVDLevel : Specifies the AVD detection level. This
+                          parameter can be a value of @ref
+                          PWREx_AVD_detection_level
+                     */
+
+  uint32_t Mode;     /*!< Mode : Specifies the EXTI operating mode for the AVD
+                                 event. This parameter can be a value of @ref
+                                 PWREx_AVD_Mode.
+                     */
+}PWREx_AVDTypeDef;
+
+/**
+  * @brief  PWREx Wakeup pin configuration structure definition
+  */
+typedef struct
+{
+  uint32_t WakeUpPin;   /*!< WakeUpPin: Specifies the Wake-Up pin to be enabled.
+                                        This parameter can be a value of @ref
+                                        PWREx_WakeUp_Pins
+                        */
+
+  uint32_t PinPolarity; /*!< PinPolarity: Specifies the Wake-Up pin polarity.
+                                          This parameter can be a value of @ref
+                                          PWREx_PIN_Polarity
+                        */
+
+  uint32_t PinPull;     /*!< PinPull: Specifies the Wake-Up pin pull. This
+                                      parameter can be a value of @ref
+                                      PWREx_PIN_Pull
+                        */
+}PWREx_WakeupPinTypeDef;
+
+#if defined (PWR_CSR1_MMCVDO)
+/**
+  * @brief  PWR VDDMMC voltage level enum definition
+  */
+typedef enum
+{
+  PWR_MMC_VOLTAGE_BELOW_1V2,      /*!< VDDMMC is below 1V2          */
+  PWR_MMC_VOLTAGE_EQUAL_ABOVE_1V2 /*!< VDDMMC is above or equal 1V2 */
+} PWREx_MMC_VoltageLevel;
+#endif /* defined (PWR_CSR1_MMCVDO) */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PWREx_Exported_Constants PWREx Exported Constants
+  * @{
+  */
+/** @defgroup PWREx_WakeUp_Pins PWREx Wake-Up Pins
+  * @{
+  */
+/* High level and No pull (default configuration) */
+#define PWR_WAKEUP_PIN6      PWR_WKUPEPR_WKUPEN6
+#define PWR_WAKEUP_PIN5      PWR_WKUPEPR_WKUPEN5
+#define PWR_WAKEUP_PIN4      PWR_WKUPEPR_WKUPEN4
+#define PWR_WAKEUP_PIN3      PWR_WKUPEPR_WKUPEN3
+#define PWR_WAKEUP_PIN2      PWR_WKUPEPR_WKUPEN2
+#define PWR_WAKEUP_PIN1      PWR_WKUPEPR_WKUPEN1
+
+/* High level and No pull */
+#define PWR_WAKEUP_PIN6_HIGH PWR_WKUPEPR_WKUPEN6
+#define PWR_WAKEUP_PIN5_HIGH PWR_WKUPEPR_WKUPEN5
+#define PWR_WAKEUP_PIN4_HIGH PWR_WKUPEPR_WKUPEN4
+#define PWR_WAKEUP_PIN3_HIGH PWR_WKUPEPR_WKUPEN3
+#define PWR_WAKEUP_PIN2_HIGH PWR_WKUPEPR_WKUPEN2
+#define PWR_WAKEUP_PIN1_HIGH PWR_WKUPEPR_WKUPEN1
+
+/* Low level and No pull */
+#define PWR_WAKEUP_PIN6_LOW  (PWR_WKUPEPR_WKUPP6 | PWR_WKUPEPR_WKUPEN6)
+#define PWR_WAKEUP_PIN5_LOW  (PWR_WKUPEPR_WKUPP5 | PWR_WKUPEPR_WKUPEN5)
+#define PWR_WAKEUP_PIN4_LOW  (PWR_WKUPEPR_WKUPP4 | PWR_WKUPEPR_WKUPEN4)
+#define PWR_WAKEUP_PIN3_LOW  (PWR_WKUPEPR_WKUPP3 | PWR_WKUPEPR_WKUPEN3)
+#define PWR_WAKEUP_PIN2_LOW  (PWR_WKUPEPR_WKUPP2 | PWR_WKUPEPR_WKUPEN2)
+#define PWR_WAKEUP_PIN1_LOW  (PWR_WKUPEPR_WKUPP1 | PWR_WKUPEPR_WKUPEN1)
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_PIN_Polarity PWREx Pin Polarity configuration
+  * @{
+  */
+#define PWR_PIN_POLARITY_HIGH (0x00000000U)
+#define PWR_PIN_POLARITY_LOW  (0x00000001U)
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_PIN_Pull PWREx Pin Pull configuration
+  * @{
+  */
+#define PWR_PIN_NO_PULL   (0x00000000U)
+#define PWR_PIN_PULL_UP   (0x00000001U)
+#define PWR_PIN_PULL_DOWN (0x00000002U)
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_Wakeup_Pins_Flags PWREx Wakeup Pins Flags.
+  * @{
+  */
+#define PWR_WAKEUP_FLAG1 PWR_WKUPFR_WKUPF1 /*!< Wakeup flag on PA0  */
+#define PWR_WAKEUP_FLAG2 PWR_WKUPFR_WKUPF2 /*!< Wakeup flag on PA2  */
+#define PWR_WAKEUP_FLAG3 PWR_WKUPFR_WKUPF3 /*!< Wakeup flag on PI8  */
+#define PWR_WAKEUP_FLAG4 PWR_WKUPFR_WKUPF4 /*!< Wakeup flag on PC13 */
+#define PWR_WAKEUP_FLAG5 PWR_WKUPFR_WKUPF5 /*!< Wakeup flag on PI11 */
+#define PWR_WAKEUP_FLAG6 PWR_WKUPFR_WKUPF6 /*!< Wakeup flag on PC1  */
+#define PWR_WAKEUP_FLAG_ALL (PWR_WKUPFR_WKUPF1 | PWR_WKUPFR_WKUPF2 |\
+                             PWR_WKUPFR_WKUPF3 | PWR_WKUPFR_WKUPF4 |\
+                             PWR_WKUPFR_WKUPF5 | PWR_WKUPFR_WKUPF6)
+/**
+  * @}
+  */
+
+#if defined (DUAL_CORE)
+/** @defgroup PWREx_Core_Select PWREx Core definition
+  * @{
+  */
+#define PWR_CORE_CPU1 (0x00000000U)
+#define PWR_CORE_CPU2 (0x00000001U)
+/**
+  * @}
+  */
+#endif /* defined (DUAL_CORE) */
+
+/** @defgroup PWREx_Domains PWREx Domains definition
+  * @{
+  */
+#define PWR_D1_DOMAIN (0x00000000U)
+#if defined (PWR_CPUCR_PDDS_D2)
+#define PWR_D2_DOMAIN (0x00000001U)
+#endif /* defined (PWR_CPUCR_PDDS_D2) */
+#define PWR_D3_DOMAIN (0x00000002U)
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_Domain_Flags PWREx Domain Flags definition
+  * @{
+  */
+#if defined (DUAL_CORE)
+#define PWR_D1_DOMAIN_FLAGS  (0x00000000U)
+#define PWR_D2_DOMAIN_FLAGS  (0x00000001U)
+#define PWR_ALL_DOMAIN_FLAGS (0x00000002U)
+#else
+#define PWR_CPU_FLAGS       (0x00000000U)
+#endif /* defined (DUAL_CORE) */
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_D3_State PWREx D3 Domain State
+  * @{
+  */
+#define PWR_D3_DOMAIN_STOP (0x00000000U)
+#define PWR_D3_DOMAIN_RUN  (0x00000800U)
+
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_Supply_configuration PWREx Supply configuration
+  * @{
+  */
+#define PWR_LDO_SUPPLY                      PWR_CR3_LDOEN                                                               /*!< Core domains are suppplied from the LDO                                                                     */
+#if defined (SMPS)
+#define PWR_DIRECT_SMPS_SUPPLY              PWR_CR3_SMPSEN                                                              /*!< Core domains are suppplied from the SMPS only                                                               */
+#define PWR_SMPS_1V8_SUPPLIES_LDO           (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN    | PWR_CR3_LDOEN)                   /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains                                       */
+#define PWR_SMPS_2V5_SUPPLIES_LDO           (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN    | PWR_CR3_LDOEN)                   /*!< The SMPS 2.5V output supplies the LDO which supplies the Core domains                                       */
+#define PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO   (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)  /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */
+#define PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO   (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)  /*!< The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */
+#define PWR_SMPS_1V8_SUPPLIES_EXT           (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 1.8V output supplies an external source which supplies the Core domains                            */
+#define PWR_SMPS_2V5_SUPPLIES_EXT           (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 2.5V output supplies an external source which supplies the Core domains                            */
+#endif /* defined (SMPS) */
+#define PWR_EXTERNAL_SOURCE_SUPPLY          PWR_CR3_BYPASS                                                              /*!< The SMPS disabled and the LDO Bypass. The Core domains are supplied from an external source                 */
+
+#if defined (SMPS)
+#define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | \
+                                PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)
+#else
+#define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)
+#endif /* defined (SMPS) */
+/**
+  * @}
+  */
+
+
+/** @defgroup PWREx_AVD_detection_level PWREx AVD detection level
+  * @{
+  */
+#define PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0 /*!< Analog voltage detector level 0
+                                             selection : 1V7                 */
+#define PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1 /*!< Analog voltage detector level 1
+                                             selection : 2V1                 */
+#define PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2 /*!< Analog voltage detector level 2
+                                             selection : 2V5                 */
+#define PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3 /*!< Analog voltage detector level 3
+                                             selection : 2V8                 */
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_AVD_Mode PWREx AVD Mode
+  * @{
+  */
+#define PWR_AVD_MODE_NORMAL               (0x00000000U)   /*!< Basic mode is used                                                 */
+#define PWR_AVD_MODE_IT_RISING            (0x00010001U)   /*!< External Interrupt Mode with Rising edge trigger detection         */
+#define PWR_AVD_MODE_IT_FALLING           (0x00010002U)   /*!< External Interrupt Mode with Falling edge trigger detection        */
+#define PWR_AVD_MODE_IT_RISING_FALLING    (0x00010003U)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define PWR_AVD_MODE_EVENT_RISING         (0x00020001U)   /*!< Event Mode with Rising edge trigger detection                      */
+#define PWR_AVD_MODE_EVENT_FALLING        (0x00020002U)   /*!< Event Mode with Falling edge trigger detection                     */
+#define PWR_AVD_MODE_EVENT_RISING_FALLING (0x00020003U)   /*!< Event Mode with Rising/Falling edge trigger detection              */
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale
+  * @{
+  */
+#define PWR_REGULATOR_SVOS_SCALE5 (PWR_CR1_SVOS_0)
+#define PWR_REGULATOR_SVOS_SCALE4 (PWR_CR1_SVOS_1)
+#define PWR_REGULATOR_SVOS_SCALE3 (PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1)
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_VBAT_Battery_Charging_Resistor PWR battery charging resistor selection
+  * @{
+  */
+#define PWR_BATTERY_CHARGING_RESISTOR_5    (0x00000000U) /*!< VBAT charging through a 5 kOhms resistor   */
+#define PWR_BATTERY_CHARGING_RESISTOR_1_5  PWR_CR3_VBRS  /*!< VBAT charging through a 1.5 kOhms resistor */
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_VBAT_Thresholds PWREx VBAT Thresholds
+  * @{
+  */
+#define PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD  (0x00000000U)
+#define PWR_VBAT_BELOW_LOW_THRESHOLD         PWR_CR2_VBATL
+#define PWR_VBAT_ABOVE_HIGH_THRESHOLD        PWR_CR2_VBATH
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_TEMP_Thresholds PWREx Temperature Thresholds
+  * @{
+  */
+#define PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD  (0x00000000U)
+#define PWR_TEMP_BELOW_LOW_THRESHOLD         PWR_CR2_TEMPL
+#define PWR_TEMP_ABOVE_HIGH_THRESHOLD        PWR_CR2_TEMPH
+/**
+  * @}
+  */
+/** @defgroup PWREx_AVD_EXTI_Line PWREx AVD EXTI Line 16
+  * @{
+  */
+#define PWR_EXTI_LINE_AVD EXTI_IMR1_IM16 /*!< External interrupt line 16
+                                              Connected to the AVD EXTI Line */
+/**
+  * @}
+  */
+
+#if defined (PWR_CR1_SRDRAMSO)
+/** @defgroup PWREx_Memory_Shut_Off Memory shut-off block selection
+  * @{
+  */
+#define PWR_SRD_AHB_MEMORY_BLOCK        PWR_CR1_SRDRAMSO    /*!< SmartRun domain AHB memory shut-off in DStop/DStop2 low-power mode         */
+#define PWR_USB_FDCAN_MEMORY_BLOCK      PWR_CR1_HSITFSO     /*!< High-speed interfaces USB and FDCAN memories shut-off in DStop/DStop2 mode */
+#define PWR_GFXMMU_JPEG_MEMORY_BLOCK    PWR_CR1_GFXSO       /*!< GFXMMU and JPEG memories shut-off in DStop/DStop2 mode                     */
+#define PWR_TCM_ECM_MEMORY_BLOCK        PWR_CR1_ITCMSO      /*!< Instruction TCM and ETM memories shut-off in DStop/DStop2 mode             */
+#define PWR_RAM1_AHB_MEMORY_BLOCK       PWR_CR1_AHBRAM1SO   /*!< AHB RAM1 shut-off in DStop/DStop2 mode                                     */
+#define PWR_RAM2_AHB_MEMORY_BLOCK       PWR_CR1_AHBRAM2SO   /*!< AHB RAM2 shut-off in DStop/DStop2 mode                                     */
+#define PWR_RAM1_AXI_MEMORY_BLOCK       PWR_CR1_AXIRAM1SO   /*!< AXI RAM1 shut-off in DStop/DStop2 mode                                     */
+#define PWR_RAM2_AXI_MEMORY_BLOCK       PWR_CR1_AXIRAM2SO   /*!< AXI RAM2 shut-off in DStop/DStop2 mode                                     */
+#define PWR_RAM3_AXI_MEMORY_BLOCK       PWR_CR1_AXIRAM3SO   /*!< AXI RAM3 shut-off in DStop/DStop2 mode                                     */
+#define PWR_MEMORY_BLOCK_KEEP_ON        0U                  /*!< Memory content is kept in DStop or DStop2 mode                             */
+#define PWR_MEMORY_BLOCK_SHUT_OFF       1U                  /*!< Memory content is lost in DStop or DStop2 mode                             */
+/**
+  * @}
+  */
+#endif /* defined (PWR_CR1_SRDRAMSO) */
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup PWREx_Exported_Macro PWREx Exported Macro
+  *  @{
+  */
+
+/**
+  * @brief Enable the AVD EXTI Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Enable the AVD EXTI D2 Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief Disable the AVD EXTI Line 16
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Disable the AVD EXTI D2 Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief Enable event on AVD EXTI Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Enable event on AVD EXTI D2 Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief Disable event on AVD EXTI Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Disable event on AVD EXTI D2 Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief Enable the AVD Extended Interrupt Rising Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)
+
+/**
+  * @brief Disable the AVD Extended Interrupt Rising Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)
+
+/**
+  * @brief Enable the AVD Extended Interrupt Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)
+
+/**
+  * @brief Disable the AVD Extended Interrupt Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)
+
+/**
+  * @brief Enable the AVD Extended Interrupt Rising and Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
+do {                                                    \
+     __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE();           \
+     __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE();          \
+} while(0);
+
+/**
+  * @brief Disable the AVD Extended Interrupt Rising & Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
+do {                                                     \
+     __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE();           \
+     __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE();          \
+} while(0);
+
+/**
+  * @brief Check whether the specified AVD EXTI interrupt flag is set or not.
+  * @retval EXTI AVD Line Status.
+  */
+#define __HAL_PWR_AVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? 1UL : 0UL)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Check whether the specified AVD EXTI D2 interrupt flag is set or not.
+  * @retval EXTI D2 AVD Line Status.
+  */
+#define __HAL_PWR_AVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? 1UL : 0UL)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief  Clear the AVD EXTI flag.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Clear the AVD EXTI D2 flag.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief  Generates a Software interrupt on AVD EXTI line.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_AVD)
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions
+  * @{
+  */
+
+/** @addtogroup PWREx_Exported_Functions_Group1 Power Supply Control Functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource);
+uint32_t HAL_PWREx_GetSupplyConfig(void);
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
+uint32_t HAL_PWREx_GetVoltageRange(void);
+HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling(uint32_t VoltageScaling);
+uint32_t HAL_PWREx_GetStopModeVoltageRange(void);
+/**
+  * @}
+  */
+
+/** @addtogroup PWREx_Exported_Functions_Group2 Low Power Control Functions
+  * @{
+  */
+/* System low power control functions */
+#if defined (PWR_CPUCR_RETDS_CD)
+void HAL_PWREx_EnterSTOP2Mode(uint32_t Regulator, uint8_t STOPEntry);
+#endif /* defined (PWR_CPUCR_RETDS_CD) */
+void HAL_PWREx_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain);
+void HAL_PWREx_EnterSTANDBYMode(uint32_t Domain);
+void HAL_PWREx_ConfigD3Domain(uint32_t D3State);
+/* Clear Cortex-Mx pending flag */
+void HAL_PWREx_ClearPendingEvent(void);
+#if defined (DUAL_CORE)
+/* Clear domain flags */
+void HAL_PWREx_ClearDomainFlags(uint32_t DomainFlags);
+/* Core Hold/Release functions */
+HAL_StatusTypeDef HAL_PWREx_HoldCore(uint32_t CPU);
+void HAL_PWREx_ReleaseCore(uint32_t CPU);
+#endif /* defined (DUAL_CORE) */
+/* Flash low power control functions */
+void HAL_PWREx_EnableFlashPowerDown(void);
+void HAL_PWREx_DisableFlashPowerDown(void);
+#if defined (PWR_CR1_SRDRAMSO)
+/* Memory shut-off functions */
+void HAL_PWREx_EnableMemoryShutOff(uint32_t MemoryBlock);
+void HAL_PWREx_DisableMemoryShutOff(uint32_t MemoryBlock);
+#endif /* defined(PWR_CR1_SRDRAMSO) */
+/* Wakeup Pins control functions */
+void HAL_PWREx_EnableWakeUpPin(PWREx_WakeupPinTypeDef *sPinParams);
+void HAL_PWREx_DisableWakeUpPin(uint32_t WakeUpPin);
+uint32_t HAL_PWREx_GetWakeupFlag(uint32_t WakeUpFlag);
+HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag(uint32_t WakeUpFlag);
+/* Power Wakeup PIN IRQ Handler */
+void HAL_PWREx_WAKEUP_PIN_IRQHandler(void);
+void HAL_PWREx_WKUP1_Callback(void);
+void HAL_PWREx_WKUP2_Callback(void);
+void HAL_PWREx_WKUP3_Callback(void);
+void HAL_PWREx_WKUP4_Callback(void);
+void HAL_PWREx_WKUP5_Callback(void);
+void HAL_PWREx_WKUP6_Callback(void);
+/**
+  * @}
+  */
+
+/** @addtogroup PWREx_Exported_Functions_Group3 Peripherals Control Functions
+  * @{
+  */
+/* Backup regulator control functions */
+HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);
+HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void);
+/* USB regulator control functions */
+HAL_StatusTypeDef HAL_PWREx_EnableUSBReg(void);
+HAL_StatusTypeDef HAL_PWREx_DisableUSBReg(void);
+void HAL_PWREx_EnableUSBVoltageDetector(void);
+void HAL_PWREx_DisableUSBVoltageDetector(void);
+/* Battery control functions */
+void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorValue);
+void HAL_PWREx_DisableBatteryCharging(void);
+#if defined(PWR_CR1_BOOSTE)
+/* Analog Booster functions */
+void HAL_PWREx_EnableAnalogBooster(void);
+void HAL_PWREx_DisableAnalogBooster(void);
+#endif /* PWR_CR1_BOOSTE */
+/**
+  * @}
+  */
+
+/** @addtogroup PWREx_Exported_Functions_Group4 Power Monitoring functions
+  * @{
+  */
+/* Power VBAT/Temperature monitoring functions */
+void HAL_PWREx_EnableMonitoring(void);
+void HAL_PWREx_DisableMonitoring(void);
+uint32_t HAL_PWREx_GetTemperatureLevel(void);
+uint32_t HAL_PWREx_GetVBATLevel(void);
+#if defined(PWR_CSR1_MMCVDO)
+PWREx_MMC_VoltageLevel HAL_PWREx_GetMMCVoltage(void);
+#endif /* PWR_CSR1_MMCVDO */
+/* Power AVD configuration functions */
+void HAL_PWREx_ConfigAVD(PWREx_AVDTypeDef *sConfigAVD);
+void HAL_PWREx_EnableAVD(void);
+void HAL_PWREx_DisableAVD(void);
+/* Power PVD/AVD IRQ Handler */
+void HAL_PWREx_PVD_AVD_IRQHandler(void);
+void HAL_PWREx_AVDCallback(void);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PWREx_Private_Macros PWREx Private Macros
+  * @{
+  */
+
+/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters
+  * @{
+  */
+/* Check PWR regulator configuration parameter */
+#if defined (SMPS)
+#define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY)                    ||\
+                                   ((PWR_SOURCE) == PWR_DIRECT_SMPS_SUPPLY)            ||\
+                                   ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_LDO)         ||\
+                                   ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_LDO)         ||\
+                                   ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) ||\
+                                   ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) ||\
+                                   ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT)         ||\
+                                   ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT)         ||\
+                                   ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY))
+
+#else
+#define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) ||\
+                                   ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY))
+#endif /* defined (SMPS) */
+
+/* Check PWR regulator configuration in STOP mode parameter */
+#define IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE3)  ||\
+                                                     ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE4)  ||\
+                                                     ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE5))
+
+/* Check PWR domain parameter */
+#if defined (PWR_CPUCR_PDDS_D2)
+#define IS_PWR_DOMAIN(DOMAIN) (((DOMAIN) == PWR_D1_DOMAIN) ||\
+                               ((DOMAIN) == PWR_D2_DOMAIN) ||\
+                               ((DOMAIN) == PWR_D3_DOMAIN))
+#else
+#define IS_PWR_DOMAIN(DOMAIN) (((DOMAIN) == PWR_D1_DOMAIN) ||\
+                               ((DOMAIN) == PWR_D3_DOMAIN))
+#endif /* defined (PWR_CPUCR_PDDS_D2) */
+
+/* Check D3/SRD domain state parameter */
+#define IS_D3_STATE(STATE) (((STATE) == PWR_D3_DOMAIN_STOP) ||\
+                            ((STATE) == PWR_D3_DOMAIN_RUN))
+
+/* Check wake up pin parameter */
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1)      ||\
+                                ((PIN) == PWR_WAKEUP_PIN2)      ||\
+                                ((PIN) == PWR_WAKEUP_PIN3)      ||\
+                                ((PIN) == PWR_WAKEUP_PIN4)      ||\
+                                ((PIN) == PWR_WAKEUP_PIN5)      ||\
+                                ((PIN) == PWR_WAKEUP_PIN6)      ||\
+                                ((PIN) == PWR_WAKEUP_PIN1_HIGH) ||\
+                                ((PIN) == PWR_WAKEUP_PIN2_HIGH) ||\
+                                ((PIN) == PWR_WAKEUP_PIN3_HIGH) ||\
+                                ((PIN) == PWR_WAKEUP_PIN4_HIGH) ||\
+                                ((PIN) == PWR_WAKEUP_PIN5_HIGH) ||\
+                                ((PIN) == PWR_WAKEUP_PIN6_HIGH) ||\
+                                ((PIN) == PWR_WAKEUP_PIN1_LOW)  ||\
+                                ((PIN) == PWR_WAKEUP_PIN2_LOW)  ||\
+                                ((PIN) == PWR_WAKEUP_PIN3_LOW)  ||\
+                                ((PIN) == PWR_WAKEUP_PIN4_LOW)  ||\
+                                ((PIN) == PWR_WAKEUP_PIN5_LOW)  ||\
+                                ((PIN) == PWR_WAKEUP_PIN6_LOW))
+
+/* Check wake up pin polarity parameter */
+#define IS_PWR_WAKEUP_PIN_POLARITY(POLARITY) (((POLARITY) == PWR_PIN_POLARITY_HIGH) ||\
+                                              ((POLARITY) == PWR_PIN_POLARITY_LOW))
+
+/* Check wake up pin pull configuration parameter */
+#define IS_PWR_WAKEUP_PIN_PULL(PULL) (((PULL) == PWR_PIN_NO_PULL) ||\
+                                      ((PULL) == PWR_PIN_PULL_UP) ||\
+                                      ((PULL) == PWR_PIN_PULL_DOWN))
+
+/* Check wake up flag parameter */
+#define IS_PWR_WAKEUP_FLAG(FLAG) (((FLAG) == PWR_WAKEUP_FLAG1) ||\
+                                  ((FLAG) == PWR_WAKEUP_FLAG2) ||\
+                                  ((FLAG) == PWR_WAKEUP_FLAG3) ||\
+                                  ((FLAG) == PWR_WAKEUP_FLAG4) ||\
+                                  ((FLAG) == PWR_WAKEUP_FLAG5) ||\
+                                  ((FLAG) == PWR_WAKEUP_FLAG6) ||\
+                                  ((FLAG) == PWR_WAKEUP_FLAG_ALL))
+
+/* Check wake up flag parameter */
+#define IS_PWR_AVD_LEVEL(LEVEL) (((LEVEL) == PWR_AVDLEVEL_0) ||\
+                                 ((LEVEL) == PWR_AVDLEVEL_1) ||\
+                                 ((LEVEL) == PWR_AVDLEVEL_2) ||\
+                                 ((LEVEL) == PWR_AVDLEVEL_3))
+
+/* Check AVD mode parameter */
+#define IS_PWR_AVD_MODE(MODE) (((MODE) == PWR_AVD_MODE_IT_RISING)         ||\
+                               ((MODE) == PWR_AVD_MODE_IT_FALLING)        ||\
+                               ((MODE) == PWR_AVD_MODE_IT_RISING_FALLING) ||\
+                               ((MODE) == PWR_AVD_MODE_EVENT_RISING)      ||\
+                               ((MODE) == PWR_AVD_MODE_EVENT_FALLING)     ||\
+                               ((MODE) == PWR_AVD_MODE_NORMAL)            ||\
+                               ((MODE) == PWR_AVD_MODE_EVENT_RISING_FALLING))
+
+/* Check resistor battery parameter */
+#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
+                                                  ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
+/* Check D1/CD CPU ID parameter */
+#define IS_PWR_D1_CPU(CPU) ((CPU) == CM7_CPUID)
+
+#if defined (DUAL_CORE)
+/* Check CPU parameter */
+#define IS_PWR_CORE(CPU)  (((CPU) == PWR_CORE_CPU1) || ((CPU) == PWR_CORE_CPU2))
+
+/* Check D2 CPU ID parameter */
+#define IS_PWR_D2_CPU(CPU) ((CPU) == CM4_CPUID)
+
+/* Check PWR domain flag parameter */
+#define IS_PWR_DOMAIN_FLAG(FLAG)  (((FLAG) == PWR_D1_DOMAIN_FLAGS) || \
+                                   ((FLAG) == PWR_D2_DOMAIN_FLAGS) || \
+                                   ((FLAG) == PWR_ALL_DOMAIN_FLAGS))
+#endif /* defined (DUAL_CORE) */
+
+#if defined (PWR_CR1_SRDRAMSO)
+/* Check memory block parameter */
+#define IS_PWR_MEMORY_BLOCK(BLOCK) (((BLOCK) == PWR_SRD_AHB_MEMORY_BLOCK)     || \
+                                    ((BLOCK) == PWR_USB_FDCAN_MEMORY_BLOCK)   || \
+                                    ((BLOCK) == PWR_GFXMMU_JPEG_MEMORY_BLOCK) || \
+                                    ((BLOCK) == PWR_TCM_ECM_MEMORY_BLOCK)     || \
+                                    ((BLOCK) == PWR_RAM1_AHB_MEMORY_BLOCK)    || \
+                                    ((BLOCK) == PWR_RAM2_AHB_MEMORY_BLOCK)    || \
+                                    ((BLOCK) == PWR_RAM1_AXI_MEMORY_BLOCK)    || \
+                                    ((BLOCK) == PWR_RAM2_AXI_MEMORY_BLOCK)    || \
+                                    ((BLOCK) == PWR_RAM3_AXI_MEMORY_BLOCK))
+#endif /* defined (PWR_CR1_SRDRAMSO) */
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* STM32H7xx_HAL_PWR_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h
new file mode 100644
index 00000000..ceb86440
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h
@@ -0,0 +1,7973 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_rcc.h
+  * @author  MCD Application Team
+  * @brief   Header file of RCC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_RCC_H
+#define STM32H7xx_HAL_RCC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup RCC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Types RCC Exported Types
+  * @{
+  */
+
+/**
+  * @brief  RCC PLL configuration structure definition
+  */
+typedef struct
+{
+  uint32_t PLLState;   /*!< The new state of the PLL.
+                            This parameter can be a value of @ref RCC_PLL_Config                      */
+
+  uint32_t PLLSource;  /*!< RCC_PLLSource: PLL entry clock source.
+                            This parameter must be a value of @ref RCC_PLL_Clock_Source               */
+
+  uint32_t PLLM;       /*!< PLLM: Division factor for PLL VCO input clock.
+                            This parameter must be a number between Min_Data = 1 and Max_Data = 63    */
+
+  uint32_t PLLN;       /*!< PLLN: Multiplication factor for PLL VCO output clock.
+                            This parameter must be a number between Min_Data = 4 and Max_Data = 512 
+                            or between Min_Data = 8 and Max_Data = 420(*)
+                            (*) : For stm32h7a3xx and stm32h7b3xx family lines.                       */                        
+
+  uint32_t PLLP;       /*!< PLLP: Division factor for system clock.
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 128
+                          odd division factors are not allowed                                        */
+
+  uint32_t PLLQ;       /*!< PLLQ: Division factor for peripheral clocks.
+                            This parameter must be a number between Min_Data = 1 and Max_Data = 128   */
+
+  uint32_t PLLR;       /*!< PLLR: Division factor for peripheral clocks.
+                            This parameter must be a number between Min_Data = 1 and Max_Data = 128   */
+  uint32_t PLLRGE;     /*!<PLLRGE: PLL1 clock Input range
+                         This parameter must be a value of @ref RCC_PLL1_VCI_Range                    */
+  uint32_t PLLVCOSEL;  /*!<PLLVCOSEL: PLL1 clock Output range
+                         This parameter must be a value of @ref RCC_PLL1_VCO_Range                    */
+
+  uint32_t PLLFRACN;   /*!<PLLFRACN: Specifies Fractional Part Of The Multiplication Factor for
+                        PLL1 VCO It should be a value between 0 and 8191                              */
+
+}RCC_PLLInitTypeDef;
+
+/**
+  * @brief  RCC Internal/External Oscillator (HSE, HSI, CSI, LSE and LSI) configuration structure definition
+  */
+typedef struct
+{
+  uint32_t OscillatorType;       /*!< The oscillators to be configured.
+                                      This parameter can be a value of @ref RCC_Oscillator_Type                   */
+
+  uint32_t HSEState;             /*!< The new state of the HSE.
+                                      This parameter can be a value of @ref RCC_HSE_Config                        */
+
+  uint32_t LSEState;             /*!< The new state of the LSE.
+                                      This parameter can be a value of @ref RCC_LSE_Config                        */
+
+  uint32_t HSIState;             /*!< The new state of the HSI.
+                                      This parameter can be a value of @ref RCC_HSI_Config                        */
+
+  uint32_t HSICalibrationValue;  /*!< The calibration trimming value.
+                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F for STM32H7 rev.Y
+                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F for STM32H7 rev.B and above */
+
+  uint32_t LSIState;             /*!< The new state of the LSI.
+                                      This parameter can be a value of @ref RCC_LSI_Config                        */
+
+ uint32_t HSI48State;            /*!< The new state of the HSI48.
+                                      This parameter can be a value of @ref RCC_HSI48_Config                      */
+
+  uint32_t CSIState;             /*!< The new state of the CSI.
+                                      This parameter can be a value of @ref RCC_CSI_Config */
+
+  uint32_t CSICalibrationValue;  /*!< The calibration trimming value.
+                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F for STM32H7 rev.Y
+                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F for STM32H7 rev.B and above */
+
+  RCC_PLLInitTypeDef PLL;        /*!< PLL structure parameters                                                    */
+
+}RCC_OscInitTypeDef;
+
+/**
+  * @brief  RCC System, AHB and APB busses clock configuration structure definition
+  */
+typedef struct
+{
+  uint32_t ClockType;             /*!< The clock to be configured.
+                                       This parameter can be a value of @ref RCC_System_Clock_Type                          */
+
+  uint32_t SYSCLKSource;          /*!< The clock source (SYSCLKS) used as system clock.
+                                       This parameter can be a value of @ref RCC_System_Clock_Source                        */
+
+  uint32_t SYSCLKDivider;         /*!< The system clock  divider. This parameter can be
+                                       a value of @ref RCC_SYS_Clock_Source                                                 */
+
+  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
+                                       This parameter can be a value of @ref RCC_HCLK_Clock_Source                          */
+
+  uint32_t APB3CLKDivider;        /*!< The APB3 clock (D1PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_APB3_Clock_Source                        */
+
+  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_APB1_Clock_Source                        */
+  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_APB2_Clock_Source                        */
+  uint32_t APB4CLKDivider;      /*!< The APB4 clock (D3PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_APB4_Clock_Source                        */
+}RCC_ClkInitTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Constants RCC Exported Constants
+  * @{
+  */
+
+/** @defgroup RCC_Oscillator_Type  RCC Oscillator Type
+  * @{
+  */
+#define RCC_OSCILLATORTYPE_NONE        (0x00000000U)
+#define RCC_OSCILLATORTYPE_HSE         (0x00000001U)
+#define RCC_OSCILLATORTYPE_HSI         (0x00000002U)
+#define RCC_OSCILLATORTYPE_LSE         (0x00000004U)
+#define RCC_OSCILLATORTYPE_LSI         (0x00000008U)
+#define RCC_OSCILLATORTYPE_CSI         (0x00000010U)
+#define RCC_OSCILLATORTYPE_HSI48       (0x00000020U)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_HSE_Config  RCC HSE Config
+  * @{
+  */
+#define RCC_HSE_OFF                    (0x00000000U)
+#define RCC_HSE_ON                     RCC_CR_HSEON
+#define RCC_HSE_BYPASS                 ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
+#if defined(RCC_CR_HSEEXT)
+#define RCC_HSE_BYPASS_DIGITAL         ((uint32_t)(RCC_CR_HSEEXT | RCC_CR_HSEBYP | RCC_CR_HSEON))
+#endif /* RCC_CR_HSEEXT */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LSE_Config  RCC LSE Config
+  * @{
+  */
+#define RCC_LSE_OFF                    (0x00000000U)
+#define RCC_LSE_ON                     RCC_BDCR_LSEON
+#define RCC_LSE_BYPASS                 ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
+#if defined(RCC_BDCR_LSEEXT)
+#define RCC_LSE_BYPASS_DIGITAL         ((uint32_t)(RCC_BDCR_LSEEXT | RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
+#endif /* RCC_BDCR_LSEEXT */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_HSI_Config  RCC HSI Config
+  * @{
+  */
+#define RCC_HSI_OFF                      (0x00000000U)           /*!< HSI clock deactivation */
+#define RCC_HSI_ON                       RCC_CR_HSION                     /*!< HSI clock activation */
+
+#define RCC_HSI_DIV1                     (RCC_CR_HSIDIV_1 | RCC_CR_HSION) /*!< HSI_DIV1 clock activation */
+#define RCC_HSI_DIV2                     (RCC_CR_HSIDIV_2 | RCC_CR_HSION) /*!< HSI_DIV2 clock activation */
+#define RCC_HSI_DIV4                     (RCC_CR_HSIDIV_4 | RCC_CR_HSION) /*!< HSI_DIV4 clock activation */
+#define RCC_HSI_DIV8                     (RCC_CR_HSIDIV | RCC_CR_HSION)   /*!< HSI_DIV8 clock activation */
+
+
+#if defined(RCC_HSICFGR_HSITRIM_6)
+#define RCC_HSICALIBRATION_DEFAULT     (0x40U)         /* Default HSI calibration trimming value, for STM32H7 rev.V and above  */
+#else
+#define RCC_HSICALIBRATION_DEFAULT     (0x20U)         /* Default HSI calibration trimming value, for STM32H7 rev.Y */
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup RCC_HSI48_Config  RCC HSI48 Config
+  * @{
+  */
+#define RCC_HSI48_OFF                      ((uint8_t)0x00)
+#define RCC_HSI48_ON                       ((uint8_t)0x01)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LSI_Config  RCC LSI Config
+  * @{
+  */
+#define RCC_LSI_OFF                    (0x00000000U)
+#define RCC_LSI_ON                     RCC_CSR_LSION
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_CSI_Config  RCC CSI Config
+  * @{
+  */
+#define RCC_CSI_OFF                    (0x00000000U)
+#define RCC_CSI_ON                     RCC_CR_CSION
+
+#if defined(RCC_CSICFGR_CSITRIM_5)
+#define RCC_CSICALIBRATION_DEFAULT     (0x20U)         /* Default CSI calibration trimming value */
+#else
+#define RCC_CSICALIBRATION_DEFAULT     (0x10U)         /* Default CSI calibration trimming value */
+#endif /* RCC_CSICFGR_CSITRIM_5 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLL_Config  RCC PLL Config
+  * @{
+  */
+#define RCC_PLL_NONE                   (0x00000000U)
+#define RCC_PLL_OFF                    (0x00000001U)
+#define RCC_PLL_ON                     (0x00000002U)
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_PLL_Clock_Source  RCC PLL Clock Source
+  * @{
+  */
+#define RCC_PLLSOURCE_HSI              (0x00000000U)
+#define RCC_PLLSOURCE_CSI              (0x00000001U)
+#define RCC_PLLSOURCE_HSE              (0x00000002U)
+#define RCC_PLLSOURCE_NONE             (0x00000003U)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLL_Clock_Output  RCC PLL Clock Output
+  * @{
+  */
+#define RCC_PLL1_DIVP                RCC_PLLCFGR_DIVP1EN
+#define RCC_PLL1_DIVQ                RCC_PLLCFGR_DIVQ1EN
+#define RCC_PLL1_DIVR                RCC_PLLCFGR_DIVR1EN
+
+/**
+  * @}
+  */
+
+
+
+/** @defgroup RCC_PLL1_VCI_Range  RCC PLL1 VCI Range
+  * @{
+  */
+#define RCC_PLL1VCIRANGE_0                RCC_PLLCFGR_PLL1RGE_0       /*!< Clock range frequency between 1 and 2 MHz  */
+#define RCC_PLL1VCIRANGE_1                RCC_PLLCFGR_PLL1RGE_1       /*!< Clock range frequency between 2 and 4 MHz  */
+#define RCC_PLL1VCIRANGE_2                RCC_PLLCFGR_PLL1RGE_2       /*!< Clock range frequency between 4 and 8 MHz  */
+#define RCC_PLL1VCIRANGE_3                RCC_PLLCFGR_PLL1RGE_3       /*!< Clock range frequency between 8 and 16 MHz */
+
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_PLL1_VCO_Range  RCC PLL1 VCO Range
+  * @{
+  */
+#define RCC_PLL1VCOWIDE                 (0x00000000U)
+#define RCC_PLL1VCOMEDIUM               RCC_PLLCFGR_PLL1VCOSEL
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_System_Clock_Type  RCC System Clock Type
+  * @{
+  */
+#define RCC_CLOCKTYPE_SYSCLK           (0x00000001U)
+#define RCC_CLOCKTYPE_HCLK             (0x00000002U)
+#define RCC_CLOCKTYPE_D1PCLK1          (0x00000004U)
+#define RCC_CLOCKTYPE_PCLK1            (0x00000008U)
+#define RCC_CLOCKTYPE_PCLK2            (0x00000010U)
+#define RCC_CLOCKTYPE_D3PCLK1          (0x00000020U)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_System_Clock_Source  RCC System Clock Source
+  * @{
+  */
+#define RCC_SYSCLKSOURCE_CSI           RCC_CFGR_SW_CSI
+#define RCC_SYSCLKSOURCE_HSI           RCC_CFGR_SW_HSI
+#define RCC_SYSCLKSOURCE_HSE           RCC_CFGR_SW_HSE
+#define RCC_SYSCLKSOURCE_PLLCLK        RCC_CFGR_SW_PLL1
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
+  * @{
+  */
+#define RCC_SYSCLKSOURCE_STATUS_CSI    RCC_CFGR_SWS_CSI   /*!< CSI used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL1  /*!< PLL1 used as system clock */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_SYS_Clock_Source  RCC SYS Clock Source
+  * @{
+  */
+#if defined(RCC_D1CFGR_D1CPRE_DIV1)
+#define RCC_SYSCLK_DIV1                RCC_D1CFGR_D1CPRE_DIV1
+#define RCC_SYSCLK_DIV2                RCC_D1CFGR_D1CPRE_DIV2
+#define RCC_SYSCLK_DIV4                RCC_D1CFGR_D1CPRE_DIV4
+#define RCC_SYSCLK_DIV8                RCC_D1CFGR_D1CPRE_DIV8
+#define RCC_SYSCLK_DIV16               RCC_D1CFGR_D1CPRE_DIV16
+#define RCC_SYSCLK_DIV64               RCC_D1CFGR_D1CPRE_DIV64
+#define RCC_SYSCLK_DIV128              RCC_D1CFGR_D1CPRE_DIV128
+#define RCC_SYSCLK_DIV256              RCC_D1CFGR_D1CPRE_DIV256
+#define RCC_SYSCLK_DIV512              RCC_D1CFGR_D1CPRE_DIV512
+#else
+#define RCC_SYSCLK_DIV1                RCC_CDCFGR1_CDCPRE_DIV1
+#define RCC_SYSCLK_DIV2                RCC_CDCFGR1_CDCPRE_DIV2
+#define RCC_SYSCLK_DIV4                RCC_CDCFGR1_CDCPRE_DIV4
+#define RCC_SYSCLK_DIV8                RCC_CDCFGR1_CDCPRE_DIV8
+#define RCC_SYSCLK_DIV16               RCC_CDCFGR1_CDCPRE_DIV16
+#define RCC_SYSCLK_DIV64               RCC_CDCFGR1_CDCPRE_DIV64
+#define RCC_SYSCLK_DIV128              RCC_CDCFGR1_CDCPRE_DIV128
+#define RCC_SYSCLK_DIV256              RCC_CDCFGR1_CDCPRE_DIV256
+#define RCC_SYSCLK_DIV512              RCC_CDCFGR1_CDCPRE_DIV512
+#endif
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_HCLK_Clock_Source  RCC HCLK Clock Source
+  * @{
+  */
+#if defined(RCC_D1CFGR_HPRE_DIV1)
+#define RCC_HCLK_DIV1                RCC_D1CFGR_HPRE_DIV1
+#define RCC_HCLK_DIV2                RCC_D1CFGR_HPRE_DIV2
+#define RCC_HCLK_DIV4                RCC_D1CFGR_HPRE_DIV4
+#define RCC_HCLK_DIV8                RCC_D1CFGR_HPRE_DIV8
+#define RCC_HCLK_DIV16               RCC_D1CFGR_HPRE_DIV16
+#define RCC_HCLK_DIV64               RCC_D1CFGR_HPRE_DIV64
+#define RCC_HCLK_DIV128              RCC_D1CFGR_HPRE_DIV128
+#define RCC_HCLK_DIV256              RCC_D1CFGR_HPRE_DIV256
+#define RCC_HCLK_DIV512              RCC_D1CFGR_HPRE_DIV512
+#else
+#define RCC_HCLK_DIV1                RCC_CDCFGR1_HPRE_DIV1
+#define RCC_HCLK_DIV2                RCC_CDCFGR1_HPRE_DIV2
+#define RCC_HCLK_DIV4                RCC_CDCFGR1_HPRE_DIV4
+#define RCC_HCLK_DIV8                RCC_CDCFGR1_HPRE_DIV8
+#define RCC_HCLK_DIV16               RCC_CDCFGR1_HPRE_DIV16
+#define RCC_HCLK_DIV64               RCC_CDCFGR1_HPRE_DIV64
+#define RCC_HCLK_DIV128              RCC_CDCFGR1_HPRE_DIV128
+#define RCC_HCLK_DIV256              RCC_CDCFGR1_HPRE_DIV256
+#define RCC_HCLK_DIV512              RCC_CDCFGR1_HPRE_DIV512
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB3_Clock_Source  RCC APB3 Clock Source
+  * @{
+  */
+#if defined (RCC_D1CFGR_D1PPRE_DIV1)
+#define RCC_APB3_DIV1                  RCC_D1CFGR_D1PPRE_DIV1
+#define RCC_APB3_DIV2                  RCC_D1CFGR_D1PPRE_DIV2
+#define RCC_APB3_DIV4                  RCC_D1CFGR_D1PPRE_DIV4
+#define RCC_APB3_DIV8                  RCC_D1CFGR_D1PPRE_DIV8
+#define RCC_APB3_DIV16                 RCC_D1CFGR_D1PPRE_DIV16
+#else
+#define RCC_APB3_DIV1                  RCC_CDCFGR1_CDPPRE_DIV1
+#define RCC_APB3_DIV2                  RCC_CDCFGR1_CDPPRE_DIV2
+#define RCC_APB3_DIV4                  RCC_CDCFGR1_CDPPRE_DIV4
+#define RCC_APB3_DIV8                  RCC_CDCFGR1_CDPPRE_DIV8
+#define RCC_APB3_DIV16                 RCC_CDCFGR1_CDPPRE_DIV16
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB1_Clock_Source  RCC APB1 Clock Source
+  * @{
+  */
+#if defined (RCC_D2CFGR_D2PPRE1_DIV1)
+#define RCC_APB1_DIV1                  RCC_D2CFGR_D2PPRE1_DIV1
+#define RCC_APB1_DIV2                  RCC_D2CFGR_D2PPRE1_DIV2
+#define RCC_APB1_DIV4                  RCC_D2CFGR_D2PPRE1_DIV4
+#define RCC_APB1_DIV8                  RCC_D2CFGR_D2PPRE1_DIV8
+#define RCC_APB1_DIV16                 RCC_D2CFGR_D2PPRE1_DIV16
+#else
+#define RCC_APB1_DIV1                  RCC_CDCFGR2_CDPPRE1_DIV1
+#define RCC_APB1_DIV2                  RCC_CDCFGR2_CDPPRE1_DIV2
+#define RCC_APB1_DIV4                  RCC_CDCFGR2_CDPPRE1_DIV4
+#define RCC_APB1_DIV8                  RCC_CDCFGR2_CDPPRE1_DIV8
+#define RCC_APB1_DIV16                 RCC_CDCFGR2_CDPPRE1_DIV16
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB2_Clock_Source  RCC APB2 Clock Source
+  * @{
+  */
+#if defined (RCC_D2CFGR_D2PPRE2_DIV1)
+#define RCC_APB2_DIV1                  RCC_D2CFGR_D2PPRE2_DIV1
+#define RCC_APB2_DIV2                  RCC_D2CFGR_D2PPRE2_DIV2
+#define RCC_APB2_DIV4                  RCC_D2CFGR_D2PPRE2_DIV4
+#define RCC_APB2_DIV8                  RCC_D2CFGR_D2PPRE2_DIV8
+#define RCC_APB2_DIV16                 RCC_D2CFGR_D2PPRE2_DIV16
+#else
+#define RCC_APB2_DIV1                  RCC_CDCFGR2_CDPPRE2_DIV1
+#define RCC_APB2_DIV2                  RCC_CDCFGR2_CDPPRE2_DIV2
+#define RCC_APB2_DIV4                  RCC_CDCFGR2_CDPPRE2_DIV4
+#define RCC_APB2_DIV8                  RCC_CDCFGR2_CDPPRE2_DIV8
+#define RCC_APB2_DIV16                 RCC_CDCFGR2_CDPPRE2_DIV16
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB4_Clock_Source  RCC APB4 Clock Source
+  * @{
+  */
+#if defined(RCC_D3CFGR_D3PPRE_DIV1)
+#define RCC_APB4_DIV1                  RCC_D3CFGR_D3PPRE_DIV1
+#define RCC_APB4_DIV2                  RCC_D3CFGR_D3PPRE_DIV2
+#define RCC_APB4_DIV4                  RCC_D3CFGR_D3PPRE_DIV4
+#define RCC_APB4_DIV8                  RCC_D3CFGR_D3PPRE_DIV8
+#define RCC_APB4_DIV16                 RCC_D3CFGR_D3PPRE_DIV16
+#else
+#define RCC_APB4_DIV1                  RCC_SRDCFGR_SRDPPRE_DIV1
+#define RCC_APB4_DIV2                  RCC_SRDCFGR_SRDPPRE_DIV2
+#define RCC_APB4_DIV4                  RCC_SRDCFGR_SRDPPRE_DIV4
+#define RCC_APB4_DIV8                  RCC_SRDCFGR_SRDPPRE_DIV8
+#define RCC_APB4_DIV16                 RCC_SRDCFGR_SRDPPRE_DIV16
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup RCC_RTC_Clock_Source  RCC RTC Clock Source
+  * @{
+  */
+#define RCC_RTCCLKSOURCE_NO_CLK          (0x00000000U)
+#define RCC_RTCCLKSOURCE_LSE             (0x00000100U)
+#define RCC_RTCCLKSOURCE_LSI             (0x00000200U)
+#define RCC_RTCCLKSOURCE_HSE_DIV2        (0x00002300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV3        (0x00003300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV4        (0x00004300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV5        (0x00005300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV6        (0x00006300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV7        (0x00007300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV8        (0x00008300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV9        (0x00009300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV10       (0x0000A300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV11       (0x0000B300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV12       (0x0000C300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV13       (0x0000D300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV14       (0x0000E300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV15       (0x0000F300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV16       (0x00010300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV17       (0x00011300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV18       (0x00012300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV19       (0x00013300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV20       (0x00014300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV21       (0x00015300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV22       (0x00016300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV23       (0x00017300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV24       (0x00018300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV25       (0x00019300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV26       (0x0001A300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV27       (0x0001B300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV28       (0x0001C300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV29       (0x0001D300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV30       (0x0001E300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV31       (0x0001F300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV32       (0x00020300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV33       (0x00021300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV34       (0x00022300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV35       (0x00023300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV36       (0x00024300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV37       (0x00025300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV38       (0x00026300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV39       (0x00027300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV40       (0x00028300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV41       (0x00029300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV42       (0x0002A300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV43       (0x0002B300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV44       (0x0002C300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV45       (0x0002D300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV46       (0x0002E300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV47       (0x0002F300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV48       (0x00030300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV49       (0x00031300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV50       (0x00032300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV51       (0x00033300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV52       (0x00034300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV53       (0x00035300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV54       (0x00036300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV55       (0x00037300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV56       (0x00038300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV57       (0x00039300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV58       (0x0003A300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV59       (0x0003B300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV60       (0x0003C300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV61       (0x0003D300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV62       (0x0003E300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV63       (0x0003F300U)
+
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_MCO_Index  RCC MCO Index
+  * @{
+  */
+#define RCC_MCO1                         (0x00000000U)
+#define RCC_MCO2                         (0x00000001U)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MCO1_Clock_Source  RCC MCO1 Clock Source
+  * @{
+  */
+#define RCC_MCO1SOURCE_HSI               (0x00000000U)
+#define RCC_MCO1SOURCE_LSE               RCC_CFGR_MCO1_0
+#define RCC_MCO1SOURCE_HSE               RCC_CFGR_MCO1_1
+#define RCC_MCO1SOURCE_PLL1QCLK          ((uint32_t)RCC_CFGR_MCO1_0 | RCC_CFGR_MCO1_1)
+#define RCC_MCO1SOURCE_HSI48              RCC_CFGR_MCO1_2
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MCO2_Clock_Source  RCC MCO2 Clock Source
+  * @{
+  */
+#define RCC_MCO2SOURCE_SYSCLK            (0x00000000U)
+#define RCC_MCO2SOURCE_PLL2PCLK          RCC_CFGR_MCO2_0
+#define RCC_MCO2SOURCE_HSE               RCC_CFGR_MCO2_1
+#define RCC_MCO2SOURCE_PLLCLK            ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_1)
+#define RCC_MCO2SOURCE_CSICLK            RCC_CFGR_MCO2_2
+#define RCC_MCO2SOURCE_LSICLK            ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_2)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MCOx_Clock_Prescaler  RCC MCOx Clock Prescaler
+  * @{
+  */
+#define RCC_MCODIV_1                    RCC_CFGR_MCO1PRE_0
+#define RCC_MCODIV_2                    RCC_CFGR_MCO1PRE_1
+#define RCC_MCODIV_3                    ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1)
+#define RCC_MCODIV_4                    RCC_CFGR_MCO1PRE_2
+#define RCC_MCODIV_5                    ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
+#define RCC_MCODIV_6                    ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
+#define RCC_MCODIV_7                    ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
+#define RCC_MCODIV_8                    RCC_CFGR_MCO1PRE_3
+#define RCC_MCODIV_9                    ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_3)
+#define RCC_MCODIV_10                   ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
+#define RCC_MCODIV_11                   ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
+#define RCC_MCODIV_12                   ((uint32_t)RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
+#define RCC_MCODIV_13                   ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
+#define RCC_MCODIV_14                   ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
+#define RCC_MCODIV_15                   RCC_CFGR_MCO1PRE
+
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Interrupt  RCC Interrupt
+  * @{
+  */
+#define RCC_IT_LSIRDY                  (0x00000001U)
+#define RCC_IT_LSERDY                  (0x00000002U)
+#define RCC_IT_HSIRDY                  (0x00000004U)
+#define RCC_IT_HSERDY                  (0x00000008U)
+#define RCC_IT_CSIRDY                  (0x00000010U)
+#define RCC_IT_HSI48RDY                (0x00000020U)
+#define RCC_IT_PLLRDY                  (0x00000040U)
+#define RCC_IT_PLL2RDY                 (0x00000080U)
+#define RCC_IT_PLL3RDY                 (0x00000100U)
+#define RCC_IT_LSECSS                  (0x00000200U)
+#define RCC_IT_CSS                     (0x00000400U)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Flag  RCC Flag
+  *        Elements values convention: XXXYYYYYb
+  *           - YYYYY  : Flag position in the register
+  *           - XXX  : Register index
+  *                 - 001: CR register
+  *                 - 010: BDCR register
+  *                 - 011: CSR register
+  *                 - 100: RSR register
+  * @{
+  */
+/* Flags in the CR register */
+#define RCC_FLAG_HSIRDY                ((uint8_t)0x22)
+#define RCC_FLAG_HSIDIV                ((uint8_t)0x25)
+#define RCC_FLAG_CSIRDY                ((uint8_t)0x28)
+#define RCC_FLAG_HSI48RDY              ((uint8_t)0x2D)
+#if defined(RCC_CR_D1CKRDY)
+#define RCC_FLAG_D1CKRDY               ((uint8_t)0x2E)
+#else
+#define RCC_FLAG_CPUCKRDY              ((uint8_t)0x2E)
+#define RCC_FLAG_D1CKRDY               RCC_FLAG_CPUCKRDY   /* alias */
+#endif /* RCC_CR_D1CKRDY */
+#if defined(RCC_CR_D2CKRDY)
+#define RCC_FLAG_D2CKRDY               ((uint8_t)0x2F)
+#else
+#define RCC_FLAG_CDCKRDY               ((uint8_t)0x2F)
+#define RCC_FLAG_D2CKRDY               RCC_FLAG_CDCKRDY    /* alias */
+#endif /* RCC_CR_D2CKRDY */
+#define RCC_FLAG_HSERDY                ((uint8_t)0x31)
+#define RCC_FLAG_PLLRDY                ((uint8_t)0x39)
+#define RCC_FLAG_PLL2RDY               ((uint8_t)0x3B)
+#define RCC_FLAG_PLL3RDY               ((uint8_t)0x3D)
+/* Flags in the BDCR register */
+#define RCC_FLAG_LSERDY                ((uint8_t)0x41)
+
+/* Flags in the CSR register */
+#define RCC_FLAG_LSIRDY                ((uint8_t)0x61)
+
+/* Flags in the RSR register */
+#if defined(RCC_RSR_CPURSTF)
+#define RCC_FLAG_CPURST                ((uint8_t)0x91)
+#endif /* RCC_RSR_CPURSTF */
+
+#if defined(RCC_RSR_D1RSTF)
+#define RCC_FLAG_D1RST                 ((uint8_t)0x93)
+#else
+#define RCC_FLAG_CDRST                 ((uint8_t)0x93)
+#endif /* RCC_RSR_D1RSTF */
+#if defined(RCC_RSR_D2RSTF)
+#define RCC_FLAG_D2RST                 ((uint8_t)0x94)
+#endif /* RCC_RSR_D2RSTF */
+#define RCC_FLAG_BORRST                ((uint8_t)0x95)
+#define RCC_FLAG_PINRST                ((uint8_t)0x96)
+#define RCC_FLAG_PORRST                ((uint8_t)0x97)
+#define RCC_FLAG_SFTRST                ((uint8_t)0x98)
+#define RCC_FLAG_IWDG1RST              ((uint8_t)0x9A)
+#define RCC_FLAG_WWDG1RST              ((uint8_t)0x9C)
+#define RCC_FLAG_LPWR1RST              ((uint8_t)0x9E)
+#define RCC_FLAG_LPWR2RST              ((uint8_t)0x9F)
+
+#if defined(DUAL_CORE)
+#define RCC_FLAG_C1RST                 (RCC_FLAG_CPURST)
+#define RCC_FLAG_C2RST                 ((uint8_t)0x92)
+#define RCC_FLAG_SFTR1ST               (RCC_FLAG_SFTRST)
+#define RCC_FLAG_SFTR2ST               ((uint8_t)0x99)
+#define RCC_FLAG_WWDG2RST              ((uint8_t)0x9D)
+#define RCC_FLAG_IWDG2RST              ((uint8_t)0x9B)
+#endif /*DUAL_CORE*/
+
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LSEDrive_Config LSE Drive Config
+  * @{
+  */
+#define RCC_LSEDRIVE_LOW                 (0x00000000U) /*!< LSE low drive capability */
+#define RCC_LSEDRIVE_MEDIUMLOW           RCC_BDCR_LSEDRV_0      /*!< LSE medium low drive capability */
+#define RCC_LSEDRIVE_MEDIUMHIGH          RCC_BDCR_LSEDRV_1      /*!< LSE medium high drive capability */
+#define RCC_LSEDRIVE_HIGH                RCC_BDCR_LSEDRV        /*!< LSE high drive capability */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Stop_WakeUpClock  RCC Stop WakeUpClock
+  * @{
+  */
+#define RCC_STOP_WAKEUPCLOCK_HSI       (0x00000000U)
+#define RCC_STOP_WAKEUPCLOCK_CSI       RCC_CFGR_STOPWUCK
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Stop_KernelWakeUpClock  RCC Stop KernelWakeUpClock
+  * @{
+  */
+#define RCC_STOP_KERWAKEUPCLOCK_HSI       (0x00000000U)
+#define RCC_STOP_KERWAKEUPCLOCK_CSI        RCC_CFGR_STOPKERWUCK
+
+
+/**
+  * @}
+  */
+
+#if defined(RCC_VER_X)
+#define HAL_RCC_REV_Y_HSITRIM_Pos  (12U)
+#define HAL_RCC_REV_Y_HSITRIM_Msk  (0x3F000U)
+#define HAL_RCC_REV_Y_CSITRIM_Pos  (26U)
+#define HAL_RCC_REV_Y_CSITRIM_Msk  (0x7C000000U)
+#endif /* RCC_VER_X */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Macros RCC Exported Macros
+  * @{
+  */
+
+/** @brief  Enable or disable the AHB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+#define __HAL_RCC_MDMA_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_DMA2D_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(JPEG)
+#define __HAL_RCC_JPGDECEN_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* JPEG */
+
+#define __HAL_RCC_FMC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* QUADSPI */
+#if defined(OCTOSPI1)
+#define __HAL_RCC_OSPI1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* OCTOSPI1 */
+#if defined(OCTOSPI2)
+#define __HAL_RCC_OSPI2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* OCTOSPI2 */
+#if defined(OCTOSPIM)
+#define __HAL_RCC_OCTOSPIM_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_IOMNGREN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_IOMNGREN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* OCTOSPIM */
+#if defined(OTFDEC1)
+#define __HAL_RCC_OTFDEC1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* OTFDEC1 */
+#if defined(OTFDEC2)
+#define __HAL_RCC_OTFDEC2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* OTFDEC2 */
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GFXMMUEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GFXMMUEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* GFXMMU */
+#define __HAL_RCC_SDMMC1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_MDMA_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN))
+#define __HAL_RCC_DMA2D_CLK_DISABLE()           (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN))
+#if defined(JPEG)
+#define __HAL_RCC_JPGDECEN_CLK_DISABLE()        (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN))
+#endif /* JPEG */
+#define __HAL_RCC_FMC_CLK_DISABLE()             (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))
+
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN))
+#endif /* QUADSPI */
+#if defined(OCTOSPI1)
+#define __HAL_RCC_OSPI1_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OSPI1EN))
+#endif /* OCTOSPII */
+#if defined(OCTOSPI2)
+#define __HAL_RCC_OSPI2_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OSPI2EN))
+#endif /* OCTOSPI2 */
+#define __HAL_RCC_SDMMC1_CLK_DISABLE()          (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN))
+#if defined(OCTOSPIM)
+#define __HAL_RCC_OCTOSPIM_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_IOMNGREN))
+#endif /* OCTOSPIM */
+#if defined(OTFDEC1)
+#define __HAL_RCC_OTFDEC1_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OTFDEC1EN))
+#endif /* OTOFDEC1 */
+#if defined(OTFDEC2)
+#define __HAL_RCC_OTFDEC2_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OTFDEC2EN))
+#endif /* OTOFDEC2 */
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_GFXMMUEN))
+#endif /* GFXMMU */
+
+/** @brief  Get the enable or disable status of the AHB3 peripheral clock
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_MDMA_IS_CLK_ENABLED()          ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN)   != 0U)
+#define __HAL_RCC_DMA2D_IS_CLK_ENABLED()         ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN)  != 0U)
+#if defined(JPEG)
+#define __HAL_RCC_JPGDECEN_IS_CLK_ENABLED()      ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) != 0U)
+#endif /* JPEG */
+#define __HAL_RCC_FMC_IS_CLK_ENABLED()           ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN)    != 0U)
+#if defined (QUADSPI)
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED()          ((RCC->AHB3ENR & RCC_AHB3ENR_QSPIEN)   != 0U)
+#endif /* QUADSPI */
+#if defined(OCTOSPI1)
+#define __HAL_RCC_OSPI1_IS_CLK_ENABLED()          ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI1EN)   != 0U)
+#endif /* OCTOSPII */
+#if defined(OCTOSPI2)
+#define __HAL_RCC_OSPI2_IS_CLK_ENABLED()          ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI2EN)   != 0U)
+#endif /* OCTOSPI2 */
+#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) != 0U)
+#if defined(OCTOSPIM)
+#define __HAL_RCC_OCTOSPIM_IS_CLK_ENABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_IOMNGREN) != 0U)
+#endif /* OCTOSPIM */
+#if defined(OTFDEC1)
+#define __HAL_RCC_OTFDEC1_IS_CLK_ENABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC1EN) != 0U)
+#endif /* OTOFDEC1 */
+#if defined(OTFDEC2)
+#define __HAL_RCC_OTFDEC2_IS_CLK_ENABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC2EN) != 0U)
+#endif /* OTOFDEC2 */
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_IS_CLK_ENABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_GFXMMUEN) != 0U)
+#endif /* GFXMMU */
+
+#define __HAL_RCC_MDMA_IS_CLK_DISABLED()         ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN)   == 0U)
+#define __HAL_RCC_DMA2D_IS_CLK_DISABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN)  == 0U)
+#if defined(JPEG)
+#define __HAL_RCC_JPGDECEN_IS_CLK_DISABLED()     ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) == 0U)
+#endif /* JPEG */
+#define __HAL_RCC_FMC_IS_CLK_DISABLED()          ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN)    == 0U)
+#if defined (QUADSPI)
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED()         ((RCC->AHB3ENR & RCC_AHB3ENR_QSPIEN)   == 0U)
+#endif /* QUADSPI */
+#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED()       ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) == 0U)
+#if defined(OCTOSPI1)
+#define __HAL_RCC_OSPI1_IS_CLK_DISABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI1EN) == 0U)
+#endif
+#if defined(OCTOSPI2)
+#define __HAL_RCC_OSPI2_IS_CLK_DISABLED()     ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI2EN) == 0U)
+#endif
+#if defined(OCTOSPIM)
+#define __HAL_RCC_OCTOSPIM_IS_CLK_DISABLED()     ((RCC->AHB3ENR & RCC_AHB3ENR_IOMNGREN) == 0U)
+#endif
+#if defined(OTFDEC1)
+#define __HAL_RCC_OTFDEC1_IS_CLK_DISABLED()      ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC1EN) == 0U)
+#endif
+#if defined(OTFDEC2)
+#define __HAL_RCC_OTFDEC2_IS_CLK_DISABLED()      ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC2EN) == 0U)
+#endif
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_IS_CLK_DISABLED()       ((RCC->AHB3ENR & RCC_AHB3ENR_GFXMMUEN) == 0U)
+#endif
+/** @brief  Enable or disable the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_DMA1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_DMA2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_ADC12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(DUAL_CORE)
+#define __HAL_RCC_ART_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ARTEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ARTEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /*DUAL_CORE*/
+
+#if defined(RCC_AHB1ENR_CRCEN)
+#define __HAL_RCC_CRC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif
+
+#if defined(ETH)
+#define __HAL_RCC_ETH1MAC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_ETH1TX_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_ETH1RX_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif
+
+#define __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(USB2_OTG_FS)
+#define __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif
+
+#define __HAL_RCC_DMA1_CLK_DISABLE()             (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN))
+#define __HAL_RCC_DMA2_CLK_DISABLE()             (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN))
+#define __HAL_RCC_ADC12_CLK_DISABLE()            (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN))
+#if defined(DUAL_CORE)
+#define __HAL_RCC_ART_CLK_DISABLE()              (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN))
+#endif /*DUAL_CORE*/
+#if defined(RCC_AHB1ENR_CRCEN)
+#define __HAL_RCC_CRC_CLK_DISABLE()              (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_CRCEN))
+#endif
+#if defined(ETH)
+#define __HAL_RCC_ETH1MAC_CLK_DISABLE()          (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN))
+#define __HAL_RCC_ETH1TX_CLK_DISABLE()           (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN))
+#define __HAL_RCC_ETH1RX_CLK_DISABLE()           (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN))
+#endif
+#define __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()      (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN))
+#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN))
+#if defined(USB2_OTG_FS)
+#define __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()      (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN))
+#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN))
+#endif /* USB2_OTG_FS */
+
+/** @brief  Get the enable or disable status of the AHB1 peripheral clock
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_DMA1_IS_CLK_ENABLED()              ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN)          != 0U)
+#define __HAL_RCC_DMA2_IS_CLK_ENABLED()              ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN)          != 0U)
+#define __HAL_RCC_ADC12_IS_CLK_ENABLED()             ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN)         != 0U)
+#if defined(DUAL_CORE)
+#define __HAL_RCC_ART_IS_CLK_ENABLED()               ((RCC->AHB1ENR & RCC_AHB1ENR_ARTEN)           != 0U)
+#endif /*DUAL_CORE*/
+#if defined(RCC_AHB1ENR_CRCEN)
+#define __HAL_RCC_CRC_IS_CLK_ENABLED()              ((RCC->AHB1ENR & RCC_AHB1ENR_CRCEN)       != 0U)
+#endif
+#if defined(ETH)
+#define __HAL_RCC_ETH1MAC_IS_CLK_ENABLED()           ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1MACEN)       != 0U)
+#define __HAL_RCC_ETH1TX_IS_CLK_ENABLED()            ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1TXEN)        != 0U)
+#define __HAL_RCC_ETH1RX_IS_CLK_ENABLED()            ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1RXEN)        != 0U)
+#endif
+#define __HAL_RCC_USB1_OTG_HS_IS_CLK_ENABLED()       ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN)     != 0U)
+#define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_ENABLED()  ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) != 0U)
+#if defined(USB2_OTG_FS)
+#define __HAL_RCC_USB2_OTG_FS_IS_CLK_ENABLED()       ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSEN)     != 0U)
+#define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_ENABLED()  ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSULPIEN) != 0U)
+#endif /* USB2_OTG_FS */
+
+#define __HAL_RCC_DMA1_IS_CLK_DISABLED()             ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN)          == 0U)
+#define __HAL_RCC_DMA2_IS_CLK_DISABLED()             ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN)          == 0U)
+#define __HAL_RCC_ADC12_IS_CLK_DISABLED()            ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN)         == 0U)
+#if defined(DUAL_CORE)
+#define __HAL_RCC_ART_IS_CLK_DISABLED()              ((RCC->AHB1ENR & RCC_AHB1ENR_ARTEN)           == 0U)
+#endif /*DUAL_CORE*/
+#if defined(RCC_AHB1ENR_CRCEN)
+#define __HAL_RCC_CRC_IS_CLK_DISABLED()              ((RCC->AHB1ENR & RCC_AHB1ENR_CRCEN)           == 0U)
+#endif
+#if defined(ETH)
+#define __HAL_RCC_ETH1MAC_IS_CLK_DISABLED()          ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1MACEN)       == 0U)
+#define __HAL_RCC_ETH1TX_IS_CLK_DISABLED()           ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1TXEN)        == 0U)
+#define __HAL_RCC_ETH1RX_IS_CLK_DISABLED()           ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1RXEN)        == 0U)
+#endif
+#define __HAL_RCC_USB1_OTG_HS_IS_CLK_DISABLED()      ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN)     == 0U)
+#define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) == 0U)
+#if defined(USB2_OTG_FS)
+#define __HAL_RCC_USB2_OTG_FS_IS_CLK_DISABLED()      ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSEN)     == 0U)
+#define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSULPIEN) == 0U)
+#endif /* USB2_OTG_FS */
+
+/** @brief  Enable or disable the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#if defined(DCMI) && defined(PSSI)
+#define __HAL_RCC_DCMI_PSSI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_DCMI_CLK_ENABLE()  __HAL_RCC_DCMI_PSSI_CLK_ENABLE()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_DCMI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* DCMI && PSSI */
+
+#if defined(CRYP)
+#define __HAL_RCC_CRYP_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* CRYP */
+
+#if defined(HASH)
+#define __HAL_RCC_HASH_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* HASH */
+
+#define __HAL_RCC_RNG_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_SDMMC2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(RCC_AHB2ENR_D2SRAM1EN)
+#define __HAL_RCC_D2SRAM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#else
+#define __HAL_RCC_AHBSRAM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* RCC_AHB2ENR_D2SRAM1EN */
+
+#if defined(RCC_AHB2ENR_D2SRAM2EN)
+#define __HAL_RCC_D2SRAM2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#else
+#define __HAL_RCC_AHBSRAM2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* RCC_AHB2ENR_D2SRAM2EN */
+
+#if defined(RCC_AHB2ENR_D2SRAM3EN)
+#define __HAL_RCC_D2SRAM3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif
+
+#if defined(RCC_AHB2ENR_HSEMEN)
+#define __HAL_RCC_HSEM_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* RCC_AHB2ENR_HSEMEN */
+
+#if defined(BDMA1)
+#define __HAL_RCC_BDMA1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_BDMA1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_BDMA1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* BDMA1 */
+
+#if defined(DCMI) && defined(PSSI)
+#define __HAL_RCC_DCMI_PSSI_CLK_DISABLE()         (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMI_PSSIEN))
+#define __HAL_RCC_DCMI_CLK_DISABLE()              __HAL_RCC_DCMI_PSSI_CLK_DISABLE()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_DCMI_CLK_DISABLE()             (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))
+#endif /* DCMI && PSSI */
+#if defined(CRYP)
+#define __HAL_RCC_CRYP_CLK_DISABLE()             (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_HASH_CLK_DISABLE()             (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))
+#endif /* HASH */
+#define __HAL_RCC_RNG_CLK_DISABLE()              (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))
+#define __HAL_RCC_SDMMC2_CLK_DISABLE()           (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))
+#if defined(RCC_AHB2ENR_D2SRAM1EN)
+#define __HAL_RCC_D2SRAM1_CLK_DISABLE()          (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN))
+#else
+#define __HAL_RCC_AHBSRAM1_CLK_DISABLE()         (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_AHBSRAM1EN))
+#endif /* RCC_AHB2ENR_D2SRAM1EN */
+#if defined(RCC_AHB2ENR_D2SRAM2EN)
+#define __HAL_RCC_D2SRAM2_CLK_DISABLE()          (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN))
+#else
+#define __HAL_RCC_AHBSRAM2_CLK_DISABLE()         (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_AHBSRAM2EN))
+#endif /* RCC_AHB2ENR_D2SRAM2EN */
+#if defined(RCC_AHB2ENR_D2SRAM3EN)
+#define __HAL_RCC_D2SRAM3_CLK_DISABLE()          (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN))
+#endif
+#if defined(RCC_AHB2ENR_HSEMEN)
+#define __HAL_RCC_HSEM_CLK_DISABLE()             (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HSEMEN))
+#endif
+#if defined(BDMA1)
+#define __HAL_RCC_BDMA1_CLK_DISABLE()            (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_BDMA1EN))
+#endif
+
+/** @brief  Get the enable or disable status of the AHB2 peripheral clock
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#if defined(DCMI) && defined(PSSI)
+#define __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED()         ((RCC->AHB2ENR & RCC_AHB2ENR_DCMI_PSSIEN)    != 0U)
+#define __HAL_RCC_DCMI_IS_CLK_ENABLED()              __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_DCMI_IS_CLK_ENABLED()              ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN)    != 0U)
+#endif /* DCMI && PSSI */
+#if defined(CRYP)
+#define __HAL_RCC_CRYP_IS_CLK_ENABLED()              ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN)    != 0U)
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_HASH_IS_CLK_ENABLED()              ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN)    != 0U)
+#endif /* HASH */
+#define __HAL_RCC_RNG_IS_CLK_ENABLED()               ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN)     != 0U)
+#define __HAL_RCC_SDMMC2_IS_CLK_ENABLED()            ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN)  != 0U)
+#if defined(RCC_AHB2ENR_D2SRAM1EN)
+#define __HAL_RCC_D2SRAM1_IS_CLK_ENABLED()           ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM1EN) != 0U)
+#else
+#define __HAL_RCC_AHBSRAM1_IS_CLK_ENABLED()          ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM1EN) != 0U)
+#endif /* RCC_AHB2ENR_D2SRAM1EN */
+#if defined(RCC_AHB2ENR_D2SRAM2EN)
+#define __HAL_RCC_D2SRAM2_IS_CLK_ENABLED()           ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM2EN) != 0U)
+#else
+#define __HAL_RCC_AHBSRAM2_IS_CLK_ENABLED()          ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM2EN) != 0U)
+#endif /* RCC_AHB2ENR_D2SRAM2EN */
+#if defined(RCC_AHB2ENR_D2SRAM3EN)
+#define __HAL_RCC_D2SRAM3_IS_CLK_ENABLED()           ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM3EN) != 0U)
+#endif
+#if defined(RCC_AHB2ENR_HSEMEN)
+#define __HAL_RCC_HSEM_IS_CLK_ENABLED()              ((RCC->AHB2ENR & RCC_AHB2ENR_HSEMEN)    != 0U)
+#endif
+#if defined(BDMA1)
+#define __HAL_RCC_BDMA1_IS_CLK_ENABLED()             ((RCC->AHB2ENR & RCC_AHB2ENR_BDMA1EN)  != 0U)
+#endif
+
+#if defined(DCMI) && defined(PSSI)
+#define __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED()        ((RCC->AHB2ENR & RCC_AHB2ENR_DCMI_PSSIEN)    == 0U)
+#define __HAL_RCC_DCMI_IS_CLK_DISABLED()             __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_DCMI_IS_CLK_DISABLED()             ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN)    == 0U)
+#endif /* DCMI && PSSI */
+#if defined(CRYP)
+#define __HAL_RCC_CRYP_IS_CLK_DISABLED()             ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN)    == 0U)
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_HASH_IS_CLK_DISABLED()             ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN)    == 0U)
+#endif /* HASH */
+#define __HAL_RCC_RNG_IS_CLK_DISABLED()              ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN)     == 0U)
+#define __HAL_RCC_SDMMC2_IS_CLK_DISABLED()           ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN)  == 0U)
+#if defined(RCC_AHB2ENR_D2SRAM1EN)
+#define __HAL_RCC_D2SRAM1_IS_CLK_DISABLED()          ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM1EN) == 0U)
+#else
+#define __HAL_RCC_AHBSRAM1_IS_CLK_DISABLED()         ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM1EN) == 0U)
+#endif /* RCC_AHB2ENR_D2SRAM1EN */
+#if defined(RCC_AHB2ENR_D2SRAM2EN)
+#define __HAL_RCC_D2SRAM2_IS_CLK_DISABLED()          ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM2EN) == 0U)
+#else
+#define __HAL_RCC_AHBSRAM2_IS_CLK_DISABLED()         ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM2EN) == 0U)
+#endif /* RCC_AHB2ENR_D2SRAM2EN */
+#if defined(RCC_AHB2ENR_D2SRAM3EN)
+#define __HAL_RCC_D2SRAM3_IS_CLK_DISABLED()          ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM3EN) == 0U)
+#endif
+#if defined(RCC_AHB2ENR_HSEMEN)
+#define __HAL_RCC_HSEM_IS_CLK_DISABLED()             ((RCC->AHB2ENR & RCC_AHB2ENR_HSEMEN)    == 0U)
+#endif
+#if defined(BDMA1)
+#define __HAL_RCC_BDMA1_IS_CLK_DISABLED()            ((RCC->AHB2ENR & RCC_AHB2ENR_BDMA1EN)   == 0U)
+#endif
+
+/** @brief  Enable or disable the AHB4 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_GPIOA_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_GPIOB_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_GPIOC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_GPIOF_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_GPIOG_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_GPIOH_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_GPIOI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_GPIOJ_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_GPIOK_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(RCC_AHB4ENR_CRCEN)
+#define __HAL_RCC_CRC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif
+
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMA2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMA2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_BDMA_CLK_ENABLE()  __HAL_RCC_BDMA2_CLK_ENABLE()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_BDMA_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif
+
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif
+
+#if defined(RCC_AHB4ENR_HSEMEN)
+#define __HAL_RCC_HSEM_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif
+
+#if defined(RCC_AHB4ENR_SRDSRAMEN)
+#define __HAL_RCC_SRDSRAM_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SRDSRAMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SRDSRAMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif
+
+#define __HAL_RCC_BKPRAM_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_GPIOA_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN)
+#define __HAL_RCC_GPIOB_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN)
+#define __HAL_RCC_GPIOC_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN)
+#define __HAL_RCC_GPIOD_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN)
+#define __HAL_RCC_GPIOE_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN)
+#define __HAL_RCC_GPIOF_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN)
+#define __HAL_RCC_GPIOG_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN)
+#define __HAL_RCC_GPIOH_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN)
+#define __HAL_RCC_GPIOI_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN)
+#define __HAL_RCC_GPIOJ_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN)
+#define __HAL_RCC_GPIOK_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN)
+#if defined(RCC_AHB4ENR_CRCEN)
+#define __HAL_RCC_CRC_CLK_DISABLE()             (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN)
+#endif
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMA2EN)
+#define __HAL_RCC_BDMA_CLK_DISABLE()            __HAL_RCC_BDMA2_CLK_DISABLE()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_BDMA_CLK_DISABLE()            (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN)
+#endif
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_CLK_DISABLE()            (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN)
+#endif
+#if defined(RCC_AHB4ENR_HSEMEN)
+#define __HAL_RCC_HSEM_CLK_DISABLE()            (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN)
+#endif
+#if defined(RCC_AHB4ENR_SRDSRAMEN)
+#define __HAL_RCC_SRDSRAM_CLK_DISABLE()         (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_SRDSRAMEN)
+#endif
+#define __HAL_RCC_BKPRAM_CLK_DISABLE()          (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN)
+
+
+/** @brief  Get the enable or disable status of the AHB4 peripheral clock
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_GPIOA_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN)  != 0U)
+#define __HAL_RCC_GPIOB_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN)  != 0U)
+#define __HAL_RCC_GPIOC_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN)  != 0U)
+#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN)  != 0U)
+#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN)  != 0U)
+#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN)  != 0U)
+#define __HAL_RCC_GPIOG_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN)  != 0U)
+#define __HAL_RCC_GPIOH_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN)  != 0U)
+#define __HAL_RCC_GPIOI_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN)  != 0U)
+#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN)  != 0U)
+#define __HAL_RCC_GPIOK_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN)  != 0U)
+#if defined(RCC_AHB4ENR_CRCEN)
+#define __HAL_RCC_CRC_IS_CLK_ENABLED()              ((RCC->AHB4ENR & RCC_AHB4ENR_CRCEN)    != 0U)
+#endif
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_BDMA2EN)   != 0U)
+#define __HAL_RCC_BDMA_IS_CLK_ENABLED()  __HAL_RCC_BDMA2_IS_CLK_ENABLED()            /* for API backward compatibility*/
+#else
+#define __HAL_RCC_BDMA_IS_CLK_ENABLED()             ((RCC->AHB4ENR & RCC_AHB4ENR_BDMAEN)   != 0U)
+#endif
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_IS_CLK_ENABLED()             ((RCC->AHB4ENR & RCC_AHB4ENR_ADC3EN)   != 0U)
+#endif
+#if defined(RCC_AHB4ENR_HSEMEN)
+#define __HAL_RCC_HSEM_IS_CLK_ENABLED()             ((RCC->AHB4ENR & RCC_AHB4ENR_HSEMEN)   != 0U)
+#endif
+#if defined(RCC_AHB4ENR_SRDSRAMEN)
+#define __HAL_RCC_SRDSRAM_IS_CLK_ENABLED()          ((RCC->AHB4ENR & RCC_AHB4ENR_SRDSRAMEN) != 0U)
+#endif
+#define __HAL_RCC_BKPRAM_IS_CLK_ENABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) != 0U)
+
+#define __HAL_RCC_GPIOA_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN)  == 0U)
+#define __HAL_RCC_GPIOB_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN)  == 0U)
+#define __HAL_RCC_GPIOC_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN)  == 0U)
+#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN)  == 0U)
+#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN)  == 0U)
+#define __HAL_RCC_GPIOF_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN)  == 0U)
+#define __HAL_RCC_GPIOG_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN)  == 0U)
+#define __HAL_RCC_GPIOH_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN)  == 0U)
+#define __HAL_RCC_GPIOI_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN)  == 0U)
+#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN)  == 0U)
+#define __HAL_RCC_GPIOK_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN)  == 0U)
+
+#if defined(RCC_AHB4ENR_CRCEN)
+#define __HAL_RCC_CRC_IS_CLK_DISABLED()             ((RCC->AHB4ENR & RCC_AHB4ENR_CRCEN)    == 0U)
+#endif
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_IS_CLK_DISABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_BDMA2EN)   == 0U)
+#define __HAL_RCC_BDMA_IS_CLK_DISABLED()  __HAL_RCC_BDMA2_IS_CLK_DISABLED()           /* for API backward compatibility*/
+#else
+#define __HAL_RCC_BDMA_IS_CLK_DISABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_BDMAEN)   == 0U)
+#endif
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_IS_CLK_DISABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_ADC3EN)   == 0U)
+#endif
+#if defined(RCC_AHB4ENR_HSEMEN)
+#define __HAL_RCC_HSEM_IS_CLK_DISABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_HSEMEN)   == 0U)
+#endif
+#if defined(RCC_AHB4ENR_SRDSRAMEN)
+#define __HAL_RCC_SRDSRAM_IS_CLK_DISABLED()         ((RCC->AHB4ENR & RCC_AHB4ENR_SRDSRAMEN)   == 0U)
+#endif
+#define __HAL_RCC_BKPRAM_IS_CLK_DISABLED()          ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) == 0U)
+
+
+/** @brief  Enable or disable the APB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LTDCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LTDCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* LTDC */
+
+#if defined(DSI)
+#define __HAL_RCC_DSI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB3ENR, RCC_APB3ENR_DSIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_DSIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /*DSI*/
+
+#define __HAL_RCC_WWDG1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_CLK_DISABLE()           (RCC->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN)
+#endif /* LTDC */
+#if defined(DSI)
+#define __HAL_RCC_DSI_CLK_DISABLE()            (RCC->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN)
+#endif /*DSI*/
+#define __HAL_RCC_WWDG1_CLK_DISABLE()          (RCC->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN)
+
+/** @brief  Get the enable or disable status of the APB3 peripheral clock
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_IS_CLK_ENABLED()            ((RCC->APB3ENR & RCC_APB3ENR_LTDCEN)  != 0U)
+#endif /* LTDC */
+#if defined(DSI)
+#define __HAL_RCC_DSI_IS_CLK_ENABLED()             ((RCC->APB3ENR & RCC_APB3ENR_DSIEN)   != 0U)
+#endif /*DSI*/
+#define __HAL_RCC_WWDG1_IS_CLK_ENABLED()           ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) != 0U)
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_IS_CLK_DISABLED()           ((RCC->APB3ENR & RCC_APB3ENR_LTDCEN)  == 0U)
+#endif /* LTDC */
+#if defined(DSI)
+#define __HAL_RCC_DSI_IS_CLK_DISABLED()            ((RCC->APB3ENR & RCC_APB3ENR_DSIEN)   == 0U)
+#endif /*DSI*/
+#define __HAL_RCC_WWDG1_IS_CLK_DISABLED()          ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) == 0U)
+
+
+/** @brief  Enable or disable the APB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_TIM2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM6_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM7_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM13_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM14_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_LPTIM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(DUAL_CORE)
+#define __HAL_RCC_WWDG2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDG2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDG2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /*DUAL_CORE*/
+
+#define __HAL_RCC_SPI2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_SPI3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_SPDIFRX_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_USART2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_USART3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_UART4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_UART5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_I2C1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_I2C2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_I2C3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_CEC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_DAC12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_UART7_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_UART8_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_CRS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_SWPMI1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_OPAMP_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_MDIOS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_FDCAN_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_TIM2_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN)
+#define __HAL_RCC_TIM3_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN)
+#define __HAL_RCC_TIM4_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN)
+#define __HAL_RCC_TIM5_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN)
+#define __HAL_RCC_TIM6_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN)
+#define __HAL_RCC_TIM7_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN)
+#define __HAL_RCC_TIM12_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN)
+#define __HAL_RCC_TIM13_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN)
+#define __HAL_RCC_TIM14_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN)
+#define __HAL_RCC_LPTIM1_CLK_DISABLE()         (RCC->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN)
+
+#if defined(DUAL_CORE)
+#define __HAL_RCC_WWDG2_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN)
+#endif /*DUAL_CORE*/
+
+#define __HAL_RCC_SPI2_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN)
+#define __HAL_RCC_SPI3_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN)
+#define __HAL_RCC_SPDIFRX_CLK_DISABLE()        (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN)
+#define __HAL_RCC_USART2_CLK_DISABLE()         (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN)
+#define __HAL_RCC_USART3_CLK_DISABLE()         (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN)
+#define __HAL_RCC_UART4_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN)
+#define __HAL_RCC_UART5_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN)
+#define __HAL_RCC_I2C1_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN)
+#define __HAL_RCC_I2C2_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN)
+#define __HAL_RCC_I2C3_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN)
+#define __HAL_RCC_CEC_CLK_DISABLE()            (RCC->APB1LENR) &= ~ (RCC_APB1LENR_CECEN)
+#define __HAL_RCC_DAC12_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN)
+#define __HAL_RCC_UART7_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN)
+#define __HAL_RCC_UART8_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN)
+#define __HAL_RCC_CRS_CLK_DISABLE()            (RCC->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN)
+#define __HAL_RCC_SWPMI1_CLK_DISABLE()          (RCC->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN)
+#define __HAL_RCC_OPAMP_CLK_DISABLE()          (RCC->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN)
+#define __HAL_RCC_MDIOS_CLK_DISABLE()          (RCC->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN)
+#define __HAL_RCC_FDCAN_CLK_DISABLE()          (RCC->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN)
+
+
+/** @brief  Get the enable or disable status of the APB1 peripheral clock
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_TIM2_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN)    != 0U)
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN)    != 0U)
+#define __HAL_RCC_TIM4_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN)    != 0U)
+#define __HAL_RCC_TIM5_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN)    != 0U)
+#define __HAL_RCC_TIM6_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN)    != 0U)
+#define __HAL_RCC_TIM7_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN)    != 0U)
+#define __HAL_RCC_TIM12_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN)   != 0U)
+#define __HAL_RCC_TIM13_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN)   != 0U)
+#define __HAL_RCC_TIM14_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN)   != 0U)
+#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED()          ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN)  != 0U)
+#if defined(DUAL_CORE)
+#define __HAL_RCC_WWDG2_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_WWDG2EN)   != 0U)
+#endif /*DUAL_CORE*/
+#define __HAL_RCC_SPI2_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN)    != 0U)
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN)    != 0U)
+#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED()         ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) != 0U)
+#define __HAL_RCC_USART2_IS_CLK_ENABLED()          ((RCC->APB1LENR & RCC_APB1LENR_USART2EN)  != 0U)
+#define __HAL_RCC_USART3_IS_CLK_ENABLED()          ((RCC->APB1LENR & RCC_APB1LENR_USART3EN)  != 0U)
+#define __HAL_RCC_UART4_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_UART4EN)   != 0U)
+#define __HAL_RCC_UART5_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_UART5EN)   != 0U)
+#define __HAL_RCC_I2C1_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN)    != 0U)
+#define __HAL_RCC_I2C2_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN)    != 0U)
+#define __HAL_RCC_I2C3_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN)    != 0U)
+#define __HAL_RCC_CEC_IS_CLK_ENABLED()             ((RCC->APB1LENR & RCC_APB1LENR_CECEN)     != 0U)
+#define __HAL_RCC_DAC12_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN)   != 0U)
+#define __HAL_RCC_UART7_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_UART7EN)   != 0U)
+#define __HAL_RCC_UART8_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_UART8EN)   != 0U)
+#define __HAL_RCC_CRS_IS_CLK_ENABLED()             ((RCC->APB1HENR & RCC_APB1HENR_CRSEN)     != 0U)
+#define __HAL_RCC_SWPMI1_IS_CLK_ENABLED()          ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN)   != 0U)
+#define __HAL_RCC_OPAMP_IS_CLK_ENABLED()           ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN)   != 0U)
+#define __HAL_RCC_MDIOS_IS_CLK_ENABLED()           ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN)   != 0U)
+#define __HAL_RCC_FDCAN_IS_CLK_ENABLED()           ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN)   != 0U)
+
+#define __HAL_RCC_TIM2_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN)    == 0U)
+#define __HAL_RCC_TIM3_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN)    == 0U)
+#define __HAL_RCC_TIM4_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN)    == 0U)
+#define __HAL_RCC_TIM5_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN)    == 0U)
+#define __HAL_RCC_TIM6_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN)    == 0U)
+#define __HAL_RCC_TIM7_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN)    == 0U)
+#define __HAL_RCC_TIM12_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN)   == 0U)
+#define __HAL_RCC_TIM13_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN)   == 0U)
+#define __HAL_RCC_TIM14_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN)   == 0U)
+#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED()         ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN)  == 0U)
+#if defined(DUAL_CORE)
+#define __HAL_RCC_WWDG2_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_WWDG2EN)   == 0U)
+#endif /*DUAL_CORE*/
+#define __HAL_RCC_SPI2_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN)    == 0U)
+#define __HAL_RCC_SPI3_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN)    == 0U)
+#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED()        ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) == 0U)
+#define __HAL_RCC_USART2_IS_CLK_DISABLED()         ((RCC->APB1LENR & RCC_APB1LENR_USART2EN)  == 0U)
+#define __HAL_RCC_USART3_IS_CLK_DISABLED()         ((RCC->APB1LENR & RCC_APB1LENR_USART3EN)  == 0U)
+#define __HAL_RCC_UART4_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_UART4EN)   == 0U)
+#define __HAL_RCC_UART5_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_UART5EN)   == 0U)
+#define __HAL_RCC_I2C1_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN)    == 0U)
+#define __HAL_RCC_I2C2_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN)    == 0U)
+#define __HAL_RCC_I2C3_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN)    == 0U)
+#define __HAL_RCC_CEC_IS_CLK_DISABLED()            ((RCC->APB1LENR & RCC_APB1LENR_CECEN)     == 0U)
+#define __HAL_RCC_DAC12_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN)   == 0U)
+#define __HAL_RCC_UART7_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_UART7EN)   == 0U)
+#define __HAL_RCC_UART8_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_UART8EN)   == 0U)
+#define __HAL_RCC_CRS_IS_CLK_DISABLED()            ((RCC->APB1HENR & RCC_APB1HENR_CRSEN)     == 0U)
+#define __HAL_RCC_SWPMI1_IS_CLK_DISABLED()         ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN)   == 0U)
+#define __HAL_RCC_OPAMP_IS_CLK_DISABLED()          ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN)   == 0U)
+#define __HAL_RCC_MDIOS_IS_CLK_DISABLED()          ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN)   == 0U)
+#define __HAL_RCC_FDCAN_IS_CLK_DISABLED()          ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN)   == 0U)
+
+
+/** @brief  Enable or disable the APB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_TIM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM8_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_USART1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_USART6_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(UART9)
+#define __HAL_RCC_UART9_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /*UART9*/
+
+#if defined(USART10)
+#define __HAL_RCC_USART10_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART10EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART10EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /*USART10*/
+
+#define __HAL_RCC_SPI1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_SPI4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM15_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM16_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM17_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_SPI5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_SAI1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_SAI2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(SAI3)
+#define __HAL_RCC_SAI3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /*SAI3*/
+
+#define __HAL_RCC_DFSDM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /*HRTIM1*/
+
+#define __HAL_RCC_TIM1_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)
+#define __HAL_RCC_TIM8_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)
+#define __HAL_RCC_USART1_CLK_DISABLE()         (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)
+#define __HAL_RCC_USART6_CLK_DISABLE()         (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)
+#if defined(UART9)
+#define __HAL_RCC_UART9_CLK_DISABLE()          (RCC->APB2ENR) &= ~ (RCC_APB2ENR_UART9EN)
+#endif /*UART9*/
+#if defined(USART10)
+#define __HAL_RCC_USART10_CLK_DISABLE()        (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART10EN)
+#endif /*USART10*/
+#define __HAL_RCC_SPI1_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)
+#define __HAL_RCC_SPI4_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)
+#define __HAL_RCC_TIM15_CLK_DISABLE()          (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)
+#define __HAL_RCC_TIM16_CLK_DISABLE()          (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)
+#define __HAL_RCC_TIM17_CLK_DISABLE()          (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)
+#define __HAL_RCC_SPI5_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)
+#define __HAL_RCC_SAI1_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)
+#define __HAL_RCC_SAI2_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN)
+#if defined(SAI3)
+#define __HAL_RCC_SAI3_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN)
+#endif /*SAI3*/
+#define __HAL_RCC_DFSDM1_CLK_DISABLE()         (RCC->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_CLK_DISABLE()         (RCC->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN)
+#endif /*HRTIM*/
+
+/** @brief  Get the enable or disable status of the APB2 peripheral clock
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_TIM1_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN)   != 0U)
+#define __HAL_RCC_TIM8_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN)   != 0U)
+#define __HAL_RCC_USART1_IS_CLK_ENABLED()          ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) != 0U)
+#define __HAL_RCC_USART6_IS_CLK_ENABLED()          ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) != 0U)
+#if defined(UART9)
+#define __HAL_RCC_UART9_IS_CLK_ENABLED()           ((RCC->APB2ENR & RCC_APB2ENR_UART9EN) != 0U)
+#endif /*UART9*/
+#if defined(USART10)
+#define __HAL_RCC_USART10_IS_CLK_ENABLED()         ((RCC->APB2ENR & RCC_APB2ENR_USART10EN) != 0U)
+#endif /*USART10*/
+#define __HAL_RCC_SPI1_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN)   != 0U)
+#define __HAL_RCC_SPI4_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN)   != 0U)
+#define __HAL_RCC_TIM15_IS_CLK_ENABLED()           ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN)  != 0U)
+#define __HAL_RCC_TIM16_IS_CLK_ENABLED()           ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN)  != 0U)
+#define __HAL_RCC_TIM17_IS_CLK_ENABLED()           ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN)  != 0U)
+#define __HAL_RCC_SPI5_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN)   != 0U)
+#define __HAL_RCC_SAI1_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN)   != 0U)
+#define __HAL_RCC_SAI2_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN)   != 0U)
+#if defined(SAI3)
+#define __HAL_RCC_SAI3_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_SAI3EN)   != 0U)
+#endif /* SAI3 */
+#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED()          ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) != 0U)
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_IS_CLK_ENABLED()          ((RCC->APB2ENR & RCC_APB2ENR_HRTIMEN)  != 0U)
+#endif /*HRTIM1*/
+
+#define __HAL_RCC_TIM1_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN)   == 0U)
+#define __HAL_RCC_TIM8_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN)   == 0U)
+#define __HAL_RCC_USART1_IS_CLK_DISABLED()         ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) == 0U)
+#define __HAL_RCC_USART6_IS_CLK_DISABLED()         ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) == 0U)
+#if defined(UART9)
+#define __HAL_RCC_UART9_IS_CLK_DISABLED()         ((RCC->APB2ENR & RCC_APB2ENR_UART9EN) == 0U)
+#endif /*UART9*/
+#if defined(USART10)
+#define __HAL_RCC_USART10_IS_CLK_DISABLED()         ((RCC->APB2ENR & RCC_APB2ENR_USART10EN) == 0U)
+#endif /*USART10*/
+#define __HAL_RCC_SPI1_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN)   == 0U)
+#define __HAL_RCC_SPI4_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN)   == 0U)
+#define __HAL_RCC_TIM15_IS_CLK_DISABLED()          ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN)  == 0U)
+#define __HAL_RCC_TIM16_IS_CLK_DISABLED()          ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN)  == 0U)
+#define __HAL_RCC_TIM17_IS_CLK_DISABLED()          ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN)  == 0U)
+#define __HAL_RCC_SPI5_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN)   == 0U)
+#define __HAL_RCC_SAI1_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN)   == 0U)
+#define __HAL_RCC_SAI2_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN)   == 0U)
+#if defined(SAI3)
+#define __HAL_RCC_SAI3_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_SAI3EN)   == 0U)
+#endif /*SAI3*/
+#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED()         ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) == 0U)
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_IS_CLK_DISABLED()         ((RCC->APB2ENR & RCC_APB2ENR_HRTIMEN)  == 0U)
+#endif /*HRTIM1*/
+
+/** @brief  Enable or disable the APB4 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_SYSCFG_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_LPUART1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_SPI6_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_I2C4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_LPTIM2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_LPTIM3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* LPTIM4 */
+
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* LPTIM5 */
+
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DAC2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DAC2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /*  DAC2 */
+
+#define __HAL_RCC_COMP12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_VREF_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SAI4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SAI4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* SAI4 */
+
+#define __HAL_RCC_RTC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(DTS)
+#define __HAL_RCC_DTS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DTSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DTSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /*DTS*/
+
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DFSDM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DFSDM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /*DFSDM2*/
+
+#define __HAL_RCC_SYSCFG_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN)
+#define __HAL_RCC_LPUART1_CLK_DISABLE()          (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN)
+#define __HAL_RCC_SPI6_CLK_DISABLE()             (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN)
+#define __HAL_RCC_I2C4_CLK_DISABLE()             (RCC->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN)
+#define __HAL_RCC_LPTIM2_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN)
+#define __HAL_RCC_LPTIM3_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN)
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN)
+#endif /*LPTIM4*/
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN)
+#endif /*LPTIM5*/
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_CLK_DISABLE()             (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DAC2EN)
+#endif /*DAC2*/
+#define __HAL_RCC_COMP12_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN)
+#define __HAL_RCC_VREF_CLK_DISABLE()             (RCC->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN)
+#define __HAL_RCC_RTC_CLK_DISABLE()              (RCC->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN)
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_CLK_DISABLE()             (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN)
+#endif /*SAI4*/
+#if defined(DTS)
+#define __HAL_RCC_DTS_CLK_DISABLE()              (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DTSEN)
+#endif /*DTS*/
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DFSDM2EN)
+#endif /*DFSDM2*/
+
+/** @brief  Get the enable or disable status of the APB4 peripheral clock
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED()            ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN)  != 0U)
+#define __HAL_RCC_LPUART1_IS_CLK_ENABLED()           ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) != 0U)
+#define __HAL_RCC_SPI6_IS_CLK_ENABLED()              ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN)    != 0U)
+#define __HAL_RCC_I2C4_IS_CLK_ENABLED()              ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN)    != 0U)
+#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED()            ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN)  != 0U)
+#define __HAL_RCC_LPTIM3_IS_CLK_ENABLED()            ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN)  != 0U)
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_IS_CLK_ENABLED()            ((RCC->APB4ENR & RCC_APB4ENR_LPTIM4EN)  != 0U)
+#endif /*LPTIM4*/
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_IS_CLK_ENABLED()            ((RCC->APB4ENR & RCC_APB4ENR_LPTIM5EN)  != 0U)
+#endif /*LPTIM5*/
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_IS_CLK_ENABLED()              ((RCC->APB4ENR & RCC_APB4ENR_DAC2EN)  != 0U)
+#endif /*DAC2*/
+#define __HAL_RCC_COMP12_IS_CLK_ENABLED()            ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN)  != 0U)
+#define __HAL_RCC_VREF_IS_CLK_ENABLED()              ((RCC->APB4ENR & RCC_APB4ENR_VREFEN)    != 0U)
+#define __HAL_RCC_RTC_IS_CLK_ENABLED()               ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN)  != 0U)
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_IS_CLK_ENABLED()              ((RCC->APB4ENR & RCC_APB4ENR_SAI4EN)    != 0U)
+#endif /*SAI4*/
+#if defined(DTS)
+#define __HAL_RCC_DTS_IS_CLK_ENABLED()               ((RCC->APB4ENR & RCC_APB4ENR_DTSEN)    != 0U)
+#endif /*DTS*/
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_IS_CLK_ENABLED()              ((RCC->APB4ENR & RCC_APB4ENR_DFSDM2EN)    != 0U)
+#endif /*DFSDM2*/
+
+#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED()           ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN)  == 0U)
+#define __HAL_RCC_LPUART1_IS_CLK_DISABLED()          ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) == 0U)
+#define __HAL_RCC_SPI6_IS_CLK_DISABLED()             ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN)    == 0U)
+#define __HAL_RCC_I2C4_IS_CLK_DISABLED()             ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN)    == 0U)
+#define __HAL_RCC_LPTIM2_IS_CLK_DISABLED()           ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN)  == 0U)
+#define __HAL_RCC_LPTIM3_IS_CLK_DISABLED()           ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN)  == 0U)
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_IS_CLK_DISABLED()           ((RCC->APB4ENR & RCC_APB4ENR_LPTIM4EN)  == 0U)
+#endif /*LPTIM4*/
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_IS_CLK_DISABLED()           ((RCC->APB4ENR & RCC_APB4ENR_LPTIM5EN)  == 0U)
+#endif /*LPTIM5*/
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_IS_CLK_DISABLED()             ((RCC->APB4ENR & RCC_APB4ENR_DAC2EN)  == 0U)
+#endif /*DAC2*/
+#define __HAL_RCC_COMP12_IS_CLK_DISABLED()           ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN)  == 0U)
+#define __HAL_RCC_VREF_IS_CLK_DISABLED()             ((RCC->APB4ENR & RCC_APB4ENR_VREFEN)    == 0U)
+#define __HAL_RCC_RTC_IS_CLK_DISABLED()              ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN)  == 0U)
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_IS_CLK_DISABLED()             ((RCC->APB4ENR & RCC_APB4ENR_SAI4EN)    == 0U)
+#endif /*SAI4*/
+#if defined(DTS)
+#define __HAL_RCC_DTS_IS_CLK_DISABLED()              ((RCC->APB4ENR & RCC_APB4ENR_DTSEN)    == 0U)
+#endif /*DTS*/
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_IS_CLK_DISABLED()          ((RCC->APB4ENR & RCC_APB4ENR_DFSDM2EN)    == 0U)
+#endif /*DFSDM2*/
+
+#if defined(DUAL_CORE)
+
+/* Exported macros for RCC_C1 -------------------------------------------------*/
+
+/** @brief  Enable or disable the AHB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C1_MDMA_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_DMA2D_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_JPGDECEN_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_C1_FMC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_QSPI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SDMMC1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+
+
+#define __HAL_RCC_C1_MDMA_CLK_DISABLE()            (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN))
+#define __HAL_RCC_C1_DMA2D_CLK_DISABLE()           (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN))
+#define __HAL_RCC_C1_JPGDECEN_CLK_DISABLE()        (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN))
+#define __HAL_RCC_C1_FMC_CLK_DISABLE()             (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))
+#define __HAL_RCC_C1_QSPI_CLK_DISABLE()            (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN))
+#define __HAL_RCC_C1_SDMMC1_CLK_DISABLE()          (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN))
+
+
+
+
+/** @brief  Enable or disable the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C1_DMA1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_DMA2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_ADC12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_ART_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ARTEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ARTEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_ETH1MAC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_ETH1TX_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_ETH1RX_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_C1_USB1_OTG_HS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_USB2_OTG_FS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_DMA1_CLK_DISABLE()             (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN))
+#define __HAL_RCC_C1_DMA2_CLK_DISABLE()             (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN))
+#define __HAL_RCC_C1_ADC12_CLK_DISABLE()            (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN))
+#define __HAL_RCC_C1_ART_CLK_DISABLE()              (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN))
+#define __HAL_RCC_C1_ETH1MAC_CLK_DISABLE()          (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN))
+#define __HAL_RCC_C1_ETH1TX_CLK_DISABLE()           (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN))
+#define __HAL_RCC_C1_ETH1RX_CLK_DISABLE()           (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN))
+#define __HAL_RCC_C1_USB1_OTG_HS_CLK_DISABLE()      (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN))
+#define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN))
+#define __HAL_RCC_C1_USB2_OTG_FS_CLK_DISABLE()      (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN))
+#define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN))
+
+/** @brief  Enable or disable the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C1_DCMI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#if defined(CRYP)
+#define __HAL_RCC_C1_CRYP_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* CRYP */
+
+#if defined(HASH)
+#define __HAL_RCC_C1_HASH_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* HASH */
+
+#define __HAL_RCC_C1_RNG_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SDMMC2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_D2SRAM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_D2SRAM2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_D2SRAM3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_DCMI_CLK_DISABLE()             (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))
+#if defined(CRYP)
+#define __HAL_RCC_C1_CRYP_CLK_DISABLE()             (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_C1_HASH_CLK_DISABLE()             (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))
+#endif /* HASH */
+#define __HAL_RCC_C1_RNG_CLK_DISABLE()              (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))
+#define __HAL_RCC_C1_SDMMC2_CLK_DISABLE()           (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))
+#define __HAL_RCC_C1_D2SRAM1_CLK_DISABLE()          (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN))
+#define __HAL_RCC_C1_D2SRAM2_CLK_DISABLE()          (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN))
+#define __HAL_RCC_C1_D2SRAM3_CLK_DISABLE()          (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN))
+
+/** @brief  Enable or disable the AHB4 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C1_GPIOA_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_GPIOB_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_GPIOC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_GPIOD_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_GPIOE_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_GPIOF_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_GPIOG_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_GPIOH_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_GPIOI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_GPIOJ_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_GPIOK_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_CRC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_CRCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_CRCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_BDMA_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_ADC3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_HSEM_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_BKPRAM_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_C1_GPIOA_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN)
+#define __HAL_RCC_C1_GPIOB_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN)
+#define __HAL_RCC_C1_GPIOC_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN)
+#define __HAL_RCC_C1_GPIOD_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN)
+#define __HAL_RCC_C1_GPIOE_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN)
+#define __HAL_RCC_C1_GPIOF_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN)
+#define __HAL_RCC_C1_GPIOG_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN)
+#define __HAL_RCC_C1_GPIOH_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN)
+#define __HAL_RCC_C1_GPIOI_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN)
+#define __HAL_RCC_C1_GPIOJ_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN)
+#define __HAL_RCC_C1_GPIOK_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN)
+#define __HAL_RCC_C1_CRC_CLK_DISABLE()             (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN)
+#define __HAL_RCC_C1_BDMA_CLK_DISABLE()            (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN)
+#define __HAL_RCC_C1_ADC3_CLK_DISABLE()            (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN)
+#define __HAL_RCC_C1_HSEM_CLK_DISABLE()            (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN)
+#define __HAL_RCC_C1_BKPRAM_CLK_DISABLE()          (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN)
+
+
+/** @brief  Enable or disable the APB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C1_LTDC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_LTDCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_LTDCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_DSI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_DSIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_DSIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_WWDG1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_WWDG1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_WWDG1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_LTDC_CLK_DISABLE()           (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN)
+#define __HAL_RCC_C1_DSI_CLK_DISABLE()            (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN)
+#define __HAL_RCC_C1_WWDG1_CLK_DISABLE()          (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN)
+
+/** @brief  Enable or disable the APB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C1_TIM2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM6_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM6EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM6EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM7_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM7EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM7EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM13_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM13EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM13EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM14_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM14EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM14EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_LPTIM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_WWDG2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_WWDG2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_WWDG2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SPI2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SPI3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SPDIFRX_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_USART2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_USART3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_UART4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_UART5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_I2C1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_I2C2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_I2C3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_CEC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_CECEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_CECEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_DAC12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_DAC12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_DAC12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_UART7_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART7EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART7EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_UART8_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART8EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART8EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_CRS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_CRSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_CRSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SWPMI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_SWPMIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_SWPMIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_OPAMP_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_OPAMPEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_OPAMPEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_MDIOS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_MDIOSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_MDIOSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_FDCAN_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_FDCANEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_FDCANEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_C1_TIM2_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN)
+#define __HAL_RCC_C1_TIM3_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN)
+#define __HAL_RCC_C1_TIM4_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN)
+#define __HAL_RCC_C1_TIM5_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN)
+#define __HAL_RCC_C1_TIM6_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN)
+#define __HAL_RCC_C1_TIM7_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN)
+#define __HAL_RCC_C1_TIM12_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN)
+#define __HAL_RCC_C1_TIM13_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN)
+#define __HAL_RCC_C1_TIM14_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN)
+#define __HAL_RCC_C1_LPTIM1_CLK_DISABLE()         (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN)
+#define __HAL_RCC_C1_WWDG2_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN)
+#define __HAL_RCC_C1_SPI2_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN)
+#define __HAL_RCC_C1_SPI3_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN)
+#define __HAL_RCC_C1_SPDIFRX_CLK_DISABLE()        (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN)
+#define __HAL_RCC_C1_USART2_CLK_DISABLE()         (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN)
+#define __HAL_RCC_C1_USART3_CLK_DISABLE()         (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN)
+#define __HAL_RCC_C1_UART4_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN)
+#define __HAL_RCC_C1_UART5_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN)
+#define __HAL_RCC_C1_I2C1_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN)
+#define __HAL_RCC_C1_I2C2_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN)
+#define __HAL_RCC_C1_I2C3_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN)
+#define __HAL_RCC_C1_CEC_CLK_DISABLE()            (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_CECEN)
+#define __HAL_RCC_C1_DAC12_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN)
+#define __HAL_RCC_C1_UART7_CLK_DISABLE()         (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN)
+#define __HAL_RCC_C1_UART8_CLK_DISABLE()         (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN)
+#define __HAL_RCC_C1_CRS_CLK_DISABLE()            (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN)
+#define __HAL_RCC_C1_SWPMI_CLK_DISABLE()          (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN)
+#define __HAL_RCC_C1_OPAMP_CLK_DISABLE()          (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN)
+#define __HAL_RCC_C1_MDIOS_CLK_DISABLE()          (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN)
+#define __HAL_RCC_C1_FDCAN_CLK_DISABLE()          (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN)
+
+/** @brief  Enable or disable the APB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C1_TIM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM8_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM8EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM8EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_USART1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_USART6_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART6EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART6EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SPI1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SPI4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM15_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM15EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM15EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM16_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM16EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM16EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM17_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM17EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM17EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SPI5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SAI1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SAI2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SAI3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_DFSDM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_HRTIM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_HRTIMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_HRTIMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM1_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)
+#define __HAL_RCC_C1_TIM8_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)
+#define __HAL_RCC_C1_USART1_CLK_DISABLE()         (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)
+#define __HAL_RCC_C1_USART6_CLK_DISABLE()         (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)
+#define __HAL_RCC_C1_SPI1_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)
+#define __HAL_RCC_C1_SPI4_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)
+#define __HAL_RCC_C1_TIM15_CLK_DISABLE()          (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)
+#define __HAL_RCC_C1_TIM16_CLK_DISABLE()          (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)
+#define __HAL_RCC_C1_TIM17_CLK_DISABLE()          (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)
+#define __HAL_RCC_C1_SPI5_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)
+#define __HAL_RCC_C1_SAI1_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)
+#define __HAL_RCC_C1_SAI2_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN)
+#define __HAL_RCC_C1_SAI3_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN)
+#define __HAL_RCC_C1_DFSDM1_CLK_DISABLE()         (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)
+#define __HAL_RCC_C1_HRTIM1_CLK_DISABLE()         (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN)
+
+/** @brief  Enable or disable the APB4 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C1_SYSCFG_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_LPUART1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPUART1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPUART1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SPI6_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SPI6EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SPI6EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_I2C4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_I2C4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_I2C4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_LPTIM2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_LPTIM3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_LPTIM4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_LPTIM5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_COMP12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_COMP12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_COMP12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_C1_VREF_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_VREFEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_VREFEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_RTC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SAI4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SAI4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SAI4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_C1_SYSCFG_CLK_DISABLE()           (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN)
+#define __HAL_RCC_C1_LPUART1_CLK_DISABLE()          (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN)
+#define __HAL_RCC_C1_SPI6_CLK_DISABLE()             (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN)
+#define __HAL_RCC_C1_I2C4_CLK_DISABLE()             (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN)
+#define __HAL_RCC_C1_LPTIM2_CLK_DISABLE()           (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN)
+#define __HAL_RCC_C1_LPTIM3_CLK_DISABLE()           (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN)
+#define __HAL_RCC_C1_LPTIM4_CLK_DISABLE()           (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN)
+#define __HAL_RCC_C1_LPTIM5_CLK_DISABLE()           (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN)
+#define __HAL_RCC_C1_COMP12_CLK_DISABLE()           (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN)
+#define __HAL_RCC_C1_VREF_CLK_DISABLE()             (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN)
+#define __HAL_RCC_C1_RTC_CLK_DISABLE()              (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN)
+#define __HAL_RCC_C1_SAI4_CLK_DISABLE()             (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN)
+
+/* Exported macros for RCC_C2 -------------------------------------------------*/
+
+/** @brief  Enable or disable the AHB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+
+#define __HAL_RCC_C2_MDMA_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_DMA2D_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_JPGDECEN_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_FLASH_C2_ALLOCATE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FLASHEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FLASHEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_DTCM1_C2_ALLOCATE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_DTCM2_C2_ALLOCATE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_ITCM_C2_ALLOCATE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_ITCMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_ITCMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_D1SRAM1_C2_ALLOCATE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_AXISRAMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_AXISRAMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_FMC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_QSPI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SDMMC1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+
+
+#define __HAL_RCC_C2_MDMA_CLK_DISABLE()            (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN))
+#define __HAL_RCC_C2_DMA2D_CLK_DISABLE()           (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN))
+#define __HAL_RCC_C2_JPGDECEN_CLK_DISABLE()        (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN))
+#define __HAL_RCC_C2_FMC_CLK_DISABLE()             (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))
+#define __HAL_RCC_C2_QSPI_CLK_DISABLE()            (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN))
+#define __HAL_RCC_C2_SDMMC1_CLK_DISABLE()          (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN))
+#define __HAL_RCC_FLASH_C2_DEALLOCATE()            (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_FLASHEN))
+#define __HAL_RCC_DTCM1_C2_DEALLOCATE()            (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DTCM1EN))
+#define __HAL_RCC_DTCM2_C2_DEALLOCATE()            (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DTCM2EN))
+#define __HAL_RCC_ITCM_C2_DEALLOCATE()             (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_ITCMEN))
+#define __HAL_RCC_D1SRAM1_C2_DEALLOCATE()          (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_AXISRAMEN))
+
+/** @brief  Enable or disable the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C2_DMA1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_DMA2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_ADC12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_ART_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ARTEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ARTEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_ETH1MAC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_ETH1TX_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_ETH1RX_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_USB1_OTG_HS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_USB2_OTG_FS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_C2_DMA1_CLK_DISABLE()             (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN))
+#define __HAL_RCC_C2_DMA2_CLK_DISABLE()             (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN))
+#define __HAL_RCC_C2_ADC12_CLK_DISABLE()            (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN))
+#define __HAL_RCC_C2_ART_CLK_DISABLE()              (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN))
+#define __HAL_RCC_C2_ETH1MAC_CLK_DISABLE()          (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN))
+#define __HAL_RCC_C2_ETH1TX_CLK_DISABLE()           (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN))
+#define __HAL_RCC_C2_ETH1RX_CLK_DISABLE()           (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN))
+#define __HAL_RCC_C2_USB1_OTG_HS_CLK_DISABLE()      (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN))
+#define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN))
+#define __HAL_RCC_C2_USB2_OTG_FS_CLK_DISABLE()      (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN))
+#define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN))
+
+/** @brief  Enable or disable the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C2_DCMI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(CRYP)
+#define __HAL_RCC_C2_CRYP_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* CRYP */
+
+#if defined(HASH)
+#define __HAL_RCC_C2_HASH_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* HASH */
+
+#define __HAL_RCC_C2_RNG_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SDMMC2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_D2SRAM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_D2SRAM2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_D2SRAM3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_DCMI_CLK_DISABLE()             (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))
+#if defined(CRYP)
+#define __HAL_RCC_C2_CRYP_CLK_DISABLE()             (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_C2_HASH_CLK_DISABLE()             (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))
+#endif /* HASH */
+#define __HAL_RCC_C2_RNG_CLK_DISABLE()              (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))
+#define __HAL_RCC_C2_SDMMC2_CLK_DISABLE()           (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))
+#define __HAL_RCC_C2_D2SRAM1_CLK_DISABLE()          (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN))
+#define __HAL_RCC_C2_D2SRAM2_CLK_DISABLE()          (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN))
+#define __HAL_RCC_C2_D2SRAM3_CLK_DISABLE()          (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN))
+
+/** @brief  Enable or disable the AHB4 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C2_GPIOA_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_GPIOB_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_GPIOC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_GPIOD_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_GPIOE_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_GPIOF_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_GPIOG_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_GPIOH_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_GPIOI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_GPIOJ_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_GPIOK_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_CRC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_CRCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_CRCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_BDMA_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_ADC3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_HSEM_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_BKPRAM_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_C2_GPIOA_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN)
+#define __HAL_RCC_C2_GPIOB_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN)
+#define __HAL_RCC_C2_GPIOC_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN)
+#define __HAL_RCC_C2_GPIOD_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN)
+#define __HAL_RCC_C2_GPIOE_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN)
+#define __HAL_RCC_C2_GPIOF_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN)
+#define __HAL_RCC_C2_GPIOG_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN)
+#define __HAL_RCC_C2_GPIOH_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN)
+#define __HAL_RCC_C2_GPIOI_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN)
+#define __HAL_RCC_C2_GPIOJ_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN)
+#define __HAL_RCC_C2_GPIOK_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN)
+#define __HAL_RCC_C2_CRC_CLK_DISABLE()             (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN)
+#define __HAL_RCC_C2_BDMA_CLK_DISABLE()            (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN)
+#define __HAL_RCC_C2_ADC3_CLK_DISABLE()            (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN)
+#define __HAL_RCC_C2_HSEM_CLK_DISABLE()            (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN)
+#define __HAL_RCC_C2_BKPRAM_CLK_DISABLE()          (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN)
+
+
+/** @brief  Enable or disable the APB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C2_LTDC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_LTDCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_LTDCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_DSI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_DSIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_DSIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_WWDG1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_WWDG1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_WWDG1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_LTDC_CLK_DISABLE()           (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN)
+#define __HAL_RCC_C2_DSI_CLK_DISABLE()            (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN)
+#define __HAL_RCC_C2_WWDG1_CLK_DISABLE()          (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN)
+
+/** @brief  Enable or disable the APB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C2_TIM2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM6_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM6EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM6EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM7_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM7EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM7EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM13_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM13EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM13EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM14_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM14EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM14EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_LPTIM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_WWDG2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_WWDG2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_WWDG2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SPI2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SPI3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SPDIFRX_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_USART2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_USART3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_UART4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_UART5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_I2C1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_I2C2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_I2C3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_CEC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_CECEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_CECEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_DAC12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_DAC12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_DAC12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_UART7_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART7EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART7EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_UART8_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART8EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART8EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_CRS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_CRSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_CRSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SWPMI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_SWPMIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_SWPMIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_OPAMP_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_OPAMPEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_OPAMPEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_MDIOS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_MDIOSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_MDIOSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_FDCAN_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_FDCANEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_FDCANEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_C2_TIM2_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN)
+#define __HAL_RCC_C2_TIM3_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN)
+#define __HAL_RCC_C2_TIM4_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN)
+#define __HAL_RCC_C2_TIM5_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN)
+#define __HAL_RCC_C2_TIM6_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN)
+#define __HAL_RCC_C2_TIM7_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN)
+#define __HAL_RCC_C2_TIM12_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN)
+#define __HAL_RCC_C2_TIM13_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN)
+#define __HAL_RCC_C2_TIM14_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN)
+#define __HAL_RCC_C2_LPTIM1_CLK_DISABLE()         (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN)
+#define __HAL_RCC_C2_WWDG2_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN)
+#define __HAL_RCC_C2_SPI2_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN)
+#define __HAL_RCC_C2_SPI3_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN)
+#define __HAL_RCC_C2_SPDIFRX_CLK_DISABLE()        (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN)
+#define __HAL_RCC_C2_USART2_CLK_DISABLE()         (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN)
+#define __HAL_RCC_C2_USART3_CLK_DISABLE()         (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN)
+#define __HAL_RCC_C2_UART4_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN)
+#define __HAL_RCC_C2_UART5_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN)
+#define __HAL_RCC_C2_I2C1_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN)
+#define __HAL_RCC_C2_I2C2_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN)
+#define __HAL_RCC_C2_I2C3_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN)
+#define __HAL_RCC_C2_CEC_CLK_DISABLE()            (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_CECEN)
+#define __HAL_RCC_C2_DAC12_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN)
+#define __HAL_RCC_C2_UART7_CLK_DISABLE()         (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN)
+#define __HAL_RCC_C2_UART8_CLK_DISABLE()         (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN)
+#define __HAL_RCC_C2_CRS_CLK_DISABLE()            (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN)
+#define __HAL_RCC_C2_SWPMI_CLK_DISABLE()          (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN)
+#define __HAL_RCC_C2_OPAMP_CLK_DISABLE()          (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN)
+#define __HAL_RCC_C2_MDIOS_CLK_DISABLE()          (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN)
+#define __HAL_RCC_C2_FDCAN_CLK_DISABLE()          (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN)
+
+/** @brief  Enable or disable the APB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C2_TIM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM8_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM8EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM8EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_USART1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_USART6_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART6EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART6EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SPI1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SPI4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM15_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM15EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM15EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM16_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM16EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM16EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM17_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM17EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM17EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SPI5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SAI1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SAI2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SAI3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_DFSDM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_HRTIM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_HRTIMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_HRTIMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM1_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)
+#define __HAL_RCC_C2_TIM8_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)
+#define __HAL_RCC_C2_USART1_CLK_DISABLE()         (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)
+#define __HAL_RCC_C2_USART6_CLK_DISABLE()         (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)
+#define __HAL_RCC_C2_SPI1_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)
+#define __HAL_RCC_C2_SPI4_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)
+#define __HAL_RCC_C2_TIM15_CLK_DISABLE()          (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)
+#define __HAL_RCC_C2_TIM16_CLK_DISABLE()          (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)
+#define __HAL_RCC_C2_TIM17_CLK_DISABLE()          (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)
+#define __HAL_RCC_C2_SPI5_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)
+#define __HAL_RCC_C2_SAI1_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)
+#define __HAL_RCC_C2_SAI2_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN)
+#define __HAL_RCC_C2_SAI3_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN)
+#define __HAL_RCC_C2_DFSDM1_CLK_DISABLE()         (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)
+#define __HAL_RCC_C2_HRTIM1_CLK_DISABLE()         (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN)
+
+/** @brief  Enable or disable the APB4 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C2_SYSCFG_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_LPUART1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPUART1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPUART1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SPI6_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SPI6EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SPI6EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_I2C4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_I2C4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_I2C4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_LPTIM2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_LPTIM3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_LPTIM4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_LPTIM5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_COMP12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_COMP12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_COMP12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_VREF_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_VREFEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_VREFEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_RTC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SAI4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SAI4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SAI4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+
+#define __HAL_RCC_C2_SYSCFG_CLK_DISABLE()           (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN)
+#define __HAL_RCC_C2_LPUART1_CLK_DISABLE()          (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN)
+#define __HAL_RCC_C2_SPI6_CLK_DISABLE()             (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN)
+#define __HAL_RCC_C2_I2C4_CLK_DISABLE()             (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN)
+#define __HAL_RCC_C2_LPTIM2_CLK_DISABLE()           (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN)
+#define __HAL_RCC_C2_LPTIM3_CLK_DISABLE()           (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN)
+#define __HAL_RCC_C2_LPTIM4_CLK_DISABLE()           (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN)
+#define __HAL_RCC_C2_LPTIM5_CLK_DISABLE()           (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN)
+#define __HAL_RCC_C2_COMP12_CLK_DISABLE()           (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN)
+#define __HAL_RCC_C2_VREF_CLK_DISABLE()             (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN)
+#define __HAL_RCC_C2_RTC_CLK_DISABLE()              (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN)
+#define __HAL_RCC_C2_SAI4_CLK_DISABLE()             (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN)
+
+#endif /*DUAL_CORE*/
+
+/** @brief  Enable or disable the AHB3 peripheral reset.
+  */
+
+#define __HAL_RCC_AHB3_FORCE_RESET()          (RCC->AHB3RSTR = 0x7FFFFFFFU)
+#define __HAL_RCC_MDMA_FORCE_RESET()          (RCC->AHB3RSTR |= (RCC_AHB3RSTR_MDMARST))
+#define __HAL_RCC_DMA2D_FORCE_RESET()         (RCC->AHB3RSTR |= (RCC_AHB3RSTR_DMA2DRST))
+#if defined(JPEG)
+#define __HAL_RCC_JPGDECRST_FORCE_RESET()     (RCC->AHB3RSTR |= (RCC_AHB3RSTR_JPGDECRST))
+#endif /* JPEG */
+#define __HAL_RCC_FMC_FORCE_RESET()           (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_FORCE_RESET()          (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
+#endif /*QUADSPI*/
+#if defined(OCTOSPI1)
+#define __HAL_RCC_OSPI1_FORCE_RESET()         (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OSPI1RST))
+#endif /*OCTOSPI1*/
+#define __HAL_RCC_SDMMC1_FORCE_RESET()        (RCC->AHB3RSTR |= (RCC_AHB3RSTR_SDMMC1RST))
+#if defined(OCTOSPI2)
+#define __HAL_RCC_OSPI2_FORCE_RESET()         (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OSPI2RST))
+#endif /*OCTOSPI2*/
+#if defined(OCTOSPIM)
+#define __HAL_RCC_IOMNGR_FORCE_RESET()      (RCC->AHB3RSTR |= (RCC_AHB3RSTR_IOMNGRRST))
+#endif /*OCTOSPIM*/
+#if defined(OTFDEC1)
+#define __HAL_RCC_OTFDEC1_FORCE_RESET()         (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OTFDEC1RST))
+#endif /*OTFDEC1*/
+#if defined(OTFDEC2)
+#define __HAL_RCC_OTFDEC2_FORCE_RESET()         (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OTFDEC2RST))
+#endif /*OTFDEC2*/
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_FORCE_RESET()        (RCC->AHB3RSTR |= (RCC_AHB3RSTR_GFXMMURST))
+#endif /*GFXMMU*/
+
+#define __HAL_RCC_AHB3_RELEASE_RESET()        (RCC->AHB3RSTR = 0x00)
+#define __HAL_RCC_MDMA_RELEASE_RESET()        (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_MDMARST))
+#define __HAL_RCC_DMA2D_RELEASE_RESET()       (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_DMA2DRST))
+#if defined(JPEG)
+#define __HAL_RCC_JPGDECRST_RELEASE_RESET()   (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_JPGDECRST))
+#endif /* JPEG */
+#define __HAL_RCC_FMC_RELEASE_RESET()         (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_FMCRST))
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_RELEASE_RESET()        (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_QSPIRST))
+#endif /*QUADSPI*/
+#if defined(OCTOSPI1)
+#define __HAL_RCC_OSPI1_RELEASE_RESET()       (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OSPI1RST))
+#endif /*OCTOSPI1*/
+#define __HAL_RCC_SDMMC1_RELEASE_RESET()      (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_SDMMC1RST))
+#if defined(OCTOSPI2)
+#define __HAL_RCC_OSPI2_RELEASE_RESET()       (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OSPI2RST))
+#endif /*OCTOSPI2*/
+#if defined(OCTOSPIM)
+#define __HAL_RCC_IOMNGR_RELEASE_RESET()      (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_IOMNGRRST))
+#endif /*OCTOSPIM*/
+#if defined(OTFDEC1)
+#define __HAL_RCC_OTFDEC1_RELEASE_RESET()       (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OTFDEC1RST))
+#endif /*OTFDEC1*/
+#if defined(OTFDEC2)
+#define __HAL_RCC_OTFDEC2_RELEASE_RESET()       (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OTFDEC2RST))
+#endif /*OTFDEC2*/
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_RELEASE_RESET()      (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_GFXMMURST))
+#endif /*GFXMMU*/
+
+
+
+/** @brief  Force or release the AHB1 peripheral reset.
+  */
+#define __HAL_RCC_AHB1_FORCE_RESET()             (RCC->AHB1RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_DMA1_FORCE_RESET()             (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
+#define __HAL_RCC_DMA2_FORCE_RESET()             (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
+#define __HAL_RCC_ADC12_FORCE_RESET()            (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ADC12RST))
+#if defined(DUAL_CORE)
+#define __HAL_RCC_ART_FORCE_RESET()              (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ARTRST))
+#endif /*DUAL_CORE*/
+#if defined(RCC_AHB1RSTR_CRCRST)
+#define __HAL_RCC_CRC_FORCE_RESET()            (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
+#endif
+#if defined(ETH)
+#define __HAL_RCC_ETH1MAC_FORCE_RESET()          (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETH1MACRST))
+#endif /*ETH*/
+#define __HAL_RCC_USB1_OTG_HS_FORCE_RESET()      (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB1OTGHSRST))
+#if defined(USB2_OTG_FS)
+#define __HAL_RCC_USB2_OTG_FS_FORCE_RESET()      (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB2OTGHSRST))
+#endif /*USB2_OTG_FS*/
+
+#define __HAL_RCC_AHB1_RELEASE_RESET()           (RCC->AHB1RSTR = 0x00U)
+#define __HAL_RCC_DMA1_RELEASE_RESET()             (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA1RST))
+#define __HAL_RCC_DMA2_RELEASE_RESET()             (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA2RST))
+#define __HAL_RCC_ADC12_RELEASE_RESET()            (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ADC12RST))
+#if defined(DUAL_CORE)
+#define __HAL_RCC_ART_RELEASE_RESET()              (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ARTRST))
+#endif /*DUAL_CORE*/
+#if defined(RCC_AHB1RSTR_CRCRST)
+#define __HAL_RCC_CRC_RELEASE_RESET()                (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_CRCRST))
+#endif
+#if defined(ETH)
+#define __HAL_RCC_ETH1MAC_RELEASE_RESET()          (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ETH1MACRST))
+#endif /*ETH*/
+#define __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()      (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB1OTGHSRST))
+#if defined(USB2_OTG_FS)
+#define __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()      (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB2OTGHSRST))
+#endif /*USB2_OTG_FS*/
+
+/** @brief  Force or release the AHB2 peripheral reset.
+  */
+#define __HAL_RCC_AHB2_FORCE_RESET()           (RCC->AHB2RSTR = 0xFFFFFFFFU)
+#if defined(DCMI) && defined(PSSI)
+#define __HAL_RCC_DCMI_PSSI_FORCE_RESET()        (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMI_PSSIRST))
+#define __HAL_RCC_DCMI_FORCE_RESET()             __HAL_RCC_DCMI_PSSI_FORCE_RESET()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_DCMI_FORCE_RESET()             (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
+#endif /* DCMI && PSSI */
+#if defined(CRYP)
+#define __HAL_RCC_CRYP_FORCE_RESET()             (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_HASH_FORCE_RESET()             (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
+#endif /* HASH */
+#define __HAL_RCC_RNG_FORCE_RESET()              (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
+#define __HAL_RCC_SDMMC2_FORCE_RESET()           (RCC->AHB2RSTR |= (RCC_AHB2RSTR_SDMMC2RST))
+#if defined(RCC_AHB2RSTR_HSEMRST)
+#define __HAL_RCC_HSEM_FORCE_RESET()             (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HSEMRST))
+#endif
+#if defined(BDMA1)
+#define __HAL_RCC_BDMA1_FORCE_RESET()           (RCC->AHB2RSTR |= (RCC_AHB2RSTR_BDMA1RST))
+#endif /*BDMA1*/
+
+#define __HAL_RCC_AHB2_RELEASE_RESET()           (RCC->AHB2RSTR = 0x00U)
+#if defined(DCMI) && defined(PSSI)
+#define __HAL_RCC_DCMI_PSSI_RELEASE_RESET()        (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMI_PSSIRST))
+#define __HAL_RCC_DCMI_RELEASE_RESET()             __HAL_RCC_DCMI_PSSI_RELEASE_RESET()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_DCMI_RELEASE_RESET()             (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMIRST))
+#endif /* DCMI && PSSI */
+#if defined(CRYP)
+#define __HAL_RCC_CRYP_RELEASE_RESET()             (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_CRYPRST))
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_HASH_RELEASE_RESET()             (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HASHRST))
+#endif /* HASH */
+#define __HAL_RCC_RNG_RELEASE_RESET()              (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_RNGRST))
+#define __HAL_RCC_SDMMC2_RELEASE_RESET()           (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_SDMMC2RST))
+#if defined(RCC_AHB2RSTR_HSEMRST)
+#define __HAL_RCC_HSEM_RELEASE_RESET()             (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HSEMRST))
+#endif
+#if defined(BDMA1)
+#define __HAL_RCC_BDMA1_RELEASE_RESET()           (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_BDMA1RST))
+#endif /*BDMA1*/
+
+
+/** @brief  Force or release the AHB4 peripheral reset.
+  */
+
+#define __HAL_RCC_AHB4_FORCE_RESET()            (RCC->AHB4RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_GPIOA_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOARST)
+#define __HAL_RCC_GPIOB_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOBRST)
+#define __HAL_RCC_GPIOC_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOCRST)
+#define __HAL_RCC_GPIOD_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIODRST)
+#define __HAL_RCC_GPIOE_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOERST)
+#define __HAL_RCC_GPIOF_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOFRST)
+#define __HAL_RCC_GPIOG_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOGRST)
+#define __HAL_RCC_GPIOH_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOHRST)
+#define __HAL_RCC_GPIOI_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOIRST)
+#define __HAL_RCC_GPIOJ_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOJRST)
+#define __HAL_RCC_GPIOK_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOKRST)
+#if defined(RCC_AHB4RSTR_CRCRST)
+#define __HAL_RCC_CRC_FORCE_RESET()             (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_CRCRST)
+#endif
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_BDMA2RST)
+#define __HAL_RCC_BDMA_FORCE_RESET()            __HAL_RCC_BDMA2_FORCE_RESET()         /* for API backward compatibility*/
+#else
+#define __HAL_RCC_BDMA_FORCE_RESET()            (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_BDMARST)
+#endif /*BDMA2*/
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_FORCE_RESET()            (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_ADC3RST)
+#endif /*ADC3*/
+#if defined(RCC_AHB4RSTR_HSEMRST)
+#define __HAL_RCC_HSEM_FORCE_RESET()            (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_HSEMRST)
+#endif
+
+#define __HAL_RCC_AHB4_RELEASE_RESET()          (RCC->AHB4RSTR = 0x00U)
+#define __HAL_RCC_GPIOA_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOARST)
+#define __HAL_RCC_GPIOB_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOBRST)
+#define __HAL_RCC_GPIOC_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOCRST)
+#define __HAL_RCC_GPIOD_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIODRST)
+#define __HAL_RCC_GPIOE_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOERST)
+#define __HAL_RCC_GPIOF_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOFRST)
+#define __HAL_RCC_GPIOG_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOGRST)
+#define __HAL_RCC_GPIOH_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOHRST)
+#define __HAL_RCC_GPIOI_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOIRST)
+#define __HAL_RCC_GPIOJ_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOJRST)
+#define __HAL_RCC_GPIOK_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOKRST)
+#if defined(RCC_AHB4RSTR_CRCRST)
+#define __HAL_RCC_CRC_RELEASE_RESET()             (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_CRCRST)
+#endif
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_RELEASE_RESET()            (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_BDMA2RST)
+#define __HAL_RCC_BDMA_RELEASE_RESET()   __HAL_RCC_BDMA2_RELEASE_RESET()      /* for API backward compatibility*/
+#else
+#define __HAL_RCC_BDMA_RELEASE_RESET()            (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_BDMARST)
+#endif /*BDMA2*/
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_RELEASE_RESET()            (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_ADC3RST)
+#endif /*ADC3*/
+#if defined(RCC_AHB4RSTR_HSEMRST)
+#define __HAL_RCC_HSEM_RELEASE_RESET()            (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_HSEMRST)
+#endif
+
+/** @brief  Force or release the APB3 peripheral reset.
+  */
+#define __HAL_RCC_APB3_FORCE_RESET()         (RCC->APB3RSTR = 0xFFFFFFFFU)
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_FORCE_RESET()           (RCC->APB3RSTR) |= (RCC_APB3RSTR_LTDCRST)
+#endif /* LTDC */
+#if defined(DSI)
+#define __HAL_RCC_DSI_FORCE_RESET()            (RCC->APB3RSTR) |= (RCC_APB3RSTR_DSIRST)
+#endif /*DSI*/
+
+#define __HAL_RCC_APB3_RELEASE_RESET()         (RCC->APB3RSTR = 0x00U)
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_RELEASE_RESET()           (RCC->APB3RSTR) &= ~ (RCC_APB3RSTR_LTDCRST)
+#endif /* LTDC */
+#if defined(DSI)
+#define __HAL_RCC_DSI_RELEASE_RESET()            (RCC->APB3RSTR) &= ~ (RCC_APB3RSTR_DSIRST)
+#endif /*DSI*/
+
+/** @brief  Force or release the APB1 peripheral reset.
+  */
+#define __HAL_RCC_APB1L_FORCE_RESET()        (RCC->APB1LRSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_APB1H_FORCE_RESET()        (RCC->APB1HRSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_TIM2_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM2RST)
+#define __HAL_RCC_TIM3_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM3RST)
+#define __HAL_RCC_TIM4_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM4RST)
+#define __HAL_RCC_TIM5_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM5RST)
+#define __HAL_RCC_TIM6_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM6RST)
+#define __HAL_RCC_TIM7_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM7RST)
+#define __HAL_RCC_TIM12_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM12RST)
+#define __HAL_RCC_TIM13_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM13RST)
+#define __HAL_RCC_TIM14_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM14RST)
+#define __HAL_RCC_LPTIM1_FORCE_RESET()         (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_LPTIM1RST)
+#define __HAL_RCC_SPI2_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI2RST)
+#define __HAL_RCC_SPI3_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI3RST)
+#define __HAL_RCC_SPDIFRX_FORCE_RESET()        (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPDIFRXRST)
+#define __HAL_RCC_USART2_FORCE_RESET()         (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART2RST)
+#define __HAL_RCC_USART3_FORCE_RESET()         (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART3RST)
+#define __HAL_RCC_UART4_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART4RST)
+#define __HAL_RCC_UART5_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART5RST)
+#define __HAL_RCC_I2C1_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C1RST)
+#define __HAL_RCC_I2C2_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C2RST)
+#define __HAL_RCC_I2C3_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C3RST)
+#define __HAL_RCC_CEC_FORCE_RESET()            (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_CECRST)
+#define __HAL_RCC_DAC12_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_DAC12RST)
+#define __HAL_RCC_UART7_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART7RST)
+#define __HAL_RCC_UART8_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART8RST)
+#define __HAL_RCC_CRS_FORCE_RESET()            (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_CRSRST)
+#define __HAL_RCC_SWPMI1_FORCE_RESET()          (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_SWPMIRST)
+#define __HAL_RCC_OPAMP_FORCE_RESET()          (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_OPAMPRST)
+#define __HAL_RCC_MDIOS_FORCE_RESET()          (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_MDIOSRST)
+#define __HAL_RCC_FDCAN_FORCE_RESET()          (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_FDCANRST)
+
+#define __HAL_RCC_APB1L_RELEASE_RESET()       (RCC->APB1LRSTR = 0x00U)
+#define __HAL_RCC_APB1H_RELEASE_RESET()       (RCC->APB1HRSTR = 0x00U)
+#define __HAL_RCC_TIM2_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM2RST)
+#define __HAL_RCC_TIM3_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM3RST)
+#define __HAL_RCC_TIM4_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM4RST)
+#define __HAL_RCC_TIM5_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM5RST)
+#define __HAL_RCC_TIM6_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM6RST)
+#define __HAL_RCC_TIM7_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM7RST)
+#define __HAL_RCC_TIM12_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM12RST)
+#define __HAL_RCC_TIM13_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM13RST)
+#define __HAL_RCC_TIM14_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM14RST)
+#define __HAL_RCC_LPTIM1_RELEASE_RESET()         (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_LPTIM1RST)
+#define __HAL_RCC_SPI2_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI2RST)
+#define __HAL_RCC_SPI3_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI3RST)
+#define __HAL_RCC_SPDIFRX_RELEASE_RESET()        (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPDIFRXRST)
+#define __HAL_RCC_USART2_RELEASE_RESET()         (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART2RST)
+#define __HAL_RCC_USART3_RELEASE_RESET()         (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART3RST)
+#define __HAL_RCC_UART4_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART4RST)
+#define __HAL_RCC_UART5_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART5RST)
+#define __HAL_RCC_I2C1_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C1RST)
+#define __HAL_RCC_I2C2_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C2RST)
+#define __HAL_RCC_I2C3_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C3RST)
+#define __HAL_RCC_CEC_RELEASE_RESET()            (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_CECRST)
+#define __HAL_RCC_DAC12_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_DAC12RST)
+#define __HAL_RCC_UART7_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART7RST)
+#define __HAL_RCC_UART8_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART8RST)
+#define __HAL_RCC_CRS_RELEASE_RESET()            (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_CRSRST)
+#define __HAL_RCC_SWPMI1_RELEASE_RESET()          (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_SWPMIRST)
+#define __HAL_RCC_OPAMP_RELEASE_RESET()          (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_OPAMPRST)
+#define __HAL_RCC_MDIOS_RELEASE_RESET()          (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_MDIOSRST)
+#define __HAL_RCC_FDCAN_RELEASE_RESET()          (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_FDCANRST)
+
+/** @brief  Force or release the APB2 peripheral reset.
+  */
+#define __HAL_RCC_APB2_FORCE_RESET()         (RCC->APB2RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_TIM1_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM1RST)
+#define __HAL_RCC_TIM8_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM8RST)
+#define __HAL_RCC_USART1_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART1RST)
+#define __HAL_RCC_USART6_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART6RST)
+#if defined(UART9)
+#define __HAL_RCC_UART9_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_UART9RST)
+#endif /*UART9*/
+#if defined(USART10)
+#define __HAL_RCC_USART10_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART10RST)
+#endif /*USART10*/
+#define __HAL_RCC_SPI1_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI1RST)
+#define __HAL_RCC_SPI4_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI4RST)
+#define __HAL_RCC_TIM15_FORCE_RESET()          (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM15RST)
+#define __HAL_RCC_TIM16_FORCE_RESET()          (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM16RST)
+#define __HAL_RCC_TIM17_FORCE_RESET()          (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM17RST)
+#define __HAL_RCC_SPI5_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI5RST)
+#define __HAL_RCC_SAI1_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI1RST)
+#define __HAL_RCC_SAI2_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI2RST)
+#if defined(SAI3)
+#define __HAL_RCC_SAI3_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI3RST)
+#endif /*SAI3*/
+#define __HAL_RCC_DFSDM1_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_DFSDM1RST)
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_HRTIMRST)
+#endif /*HRTIM1*/
+
+#define __HAL_RCC_APB2_RELEASE_RESET()         (RCC->APB2RSTR = 0x00U)
+#define __HAL_RCC_TIM1_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM1RST)
+#define __HAL_RCC_TIM8_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM8RST)
+#define __HAL_RCC_USART1_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART1RST)
+#define __HAL_RCC_USART6_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART6RST)
+#if defined(UART9)
+#define __HAL_RCC_UART9_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_UART9RST)
+#endif /*UART9*/
+#if defined(USART10)
+#define __HAL_RCC_USART10_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART10RST)
+#endif /*USART10*/
+#define __HAL_RCC_SPI1_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI1RST)
+#define __HAL_RCC_SPI4_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI4RST)
+#define __HAL_RCC_TIM15_RELEASE_RESET()          (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM15RST)
+#define __HAL_RCC_TIM16_RELEASE_RESET()          (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM16RST)
+#define __HAL_RCC_TIM17_RELEASE_RESET()          (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM17RST)
+#define __HAL_RCC_SPI5_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI5RST)
+#define __HAL_RCC_SAI1_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI1RST)
+#define __HAL_RCC_SAI2_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI2RST)
+#if defined(SAI3)
+#define __HAL_RCC_SAI3_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI3RST)
+#endif /*SAI3*/
+#define __HAL_RCC_DFSDM1_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_DFSDM1RST)
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_HRTIMRST)
+#endif /*HRTIM1*/
+
+/** @brief  Force or release the APB4 peripheral reset.
+  */
+
+#define __HAL_RCC_APB4_FORCE_RESET()           (RCC->APB4RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_SYSCFG_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_SYSCFGRST)
+#define __HAL_RCC_LPUART1_FORCE_RESET()          (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPUART1RST)
+#define __HAL_RCC_SPI6_FORCE_RESET()             (RCC->APB4RSTR) |= (RCC_APB4RSTR_SPI6RST)
+#define __HAL_RCC_I2C4_FORCE_RESET()             (RCC->APB4RSTR) |= (RCC_APB4RSTR_I2C4RST)
+#define __HAL_RCC_LPTIM2_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM2RST)
+#define __HAL_RCC_LPTIM3_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM3RST)
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM4RST)
+#endif /*LPTIM4*/
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM5RST)
+#endif /*LPTIM5*/
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_FORCE_RESET()             (RCC->APB4RSTR) |= (RCC_APB4RSTR_DAC2RST)
+#endif /*DAC2*/
+#define __HAL_RCC_COMP12_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_COMP12RST)
+#define __HAL_RCC_VREF_FORCE_RESET()             (RCC->APB4RSTR) |= (RCC_APB4RSTR_VREFRST)
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_FORCE_RESET()             (RCC->APB4RSTR) |= (RCC_APB4RSTR_SAI4RST)
+#endif /*SAI4*/
+#if defined(DTS)
+#define __HAL_RCC_DTS_FORCE_RESET()              (RCC->APB4RSTR) |= (RCC_APB4RSTR_DTSRST)
+#endif /*DTS*/
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_DFSDM2RST)
+#endif /*DFSDM2*/
+
+#define __HAL_RCC_APB4_RELEASE_RESET()           (RCC->APB4RSTR = 0x00U)
+#define __HAL_RCC_SYSCFG_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SYSCFGRST)
+#define __HAL_RCC_LPUART1_RELEASE_RESET()          (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPUART1RST)
+#define __HAL_RCC_SPI6_RELEASE_RESET()             (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SPI6RST)
+#define __HAL_RCC_I2C4_RELEASE_RESET()             (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_I2C4RST)
+#define __HAL_RCC_LPTIM2_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM2RST)
+#define __HAL_RCC_LPTIM3_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM3RST)
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM4RST)
+#endif /*LPTIM4*/
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM5RST)
+#endif /*LPTIM5*/
+#if defined(RCC_APB4RSTR_DAC2RST)
+#define __HAL_RCC_DAC2_RELEASE_RESET()             (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DAC2RST)
+#endif
+#define __HAL_RCC_COMP12_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_COMP12RST)
+#define __HAL_RCC_VREF_RELEASE_RESET()             (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_VREFRST)
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_RELEASE_RESET()             (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SAI4RST)
+#endif /*SAI4*/
+#if defined(DTS)
+#define __HAL_RCC_DTS_RELEASE_RESET()              (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DTSRST)
+#endif /*DTS*/
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DFSDM2RST)
+#endif /*DFSDM2*/
+
+/** @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+
+
+#define __HAL_RCC_MDMA_CLK_SLEEP_ENABLE()            (RCC->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN))
+#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE()           (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN))
+#if defined(JPEG)
+#define __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN))
+#endif /* JPEG */
+#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE()           (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN))
+#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE()             (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE()            (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
+#endif /*QUADSPI*/
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN))
+#if defined(OCTOSPI1)
+#define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OSPI1LPEN))
+#endif /*OCTOSPI1*/
+#if defined(OCTOSPI2)
+#define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OSPI2LPEN))
+#endif /*OCTOSPI2*/
+#if defined(OCTOSPIM)
+#define __HAL_RCC_IOMNGR_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_IOMNGRLPEN))
+#endif /*OCTOSPIM*/
+#if defined(OTFDEC1)
+#define __HAL_RCC_OTFDEC1_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OTFDEC1LPEN))
+#endif /*OTFDEC1*/
+#if defined(OTFDEC2)
+#define __HAL_RCC_OTFDEC2_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OTFDEC2LPEN))
+#endif /*OTFDEC2*/
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_GFXMMULPEN))
+#endif /*GFXMMU*/
+#if defined(CD_AXISRAM2_BASE)
+#define __HAL_RCC_AXISRAM2_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM2LPEN))
+#endif
+#if defined(CD_AXISRAM3_BASE)
+#define __HAL_RCC_AXISRAM3_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM3LPEN))
+#endif
+#define __HAL_RCC_DTCM1_CLK_SLEEP_ENABLE()           (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN))
+#define __HAL_RCC_DTCM2_CLK_SLEEP_ENABLE()           (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN))
+#define __HAL_RCC_ITCM_CLK_SLEEP_ENABLE()            (RCC->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN))
+#if defined(RCC_AHB3LPENR_AXISRAMLPEN)
+#define __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE()         (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN))
+#define __HAL_RCC_AXISRAM_CLK_SLEEP_ENABLE           __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE
+#else
+#define __HAL_RCC_AXISRAM1_CLK_SLEEP_ENABLE()        (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM1LPEN))
+#define __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE           __HAL_RCC_AXISRAM1_CLK_SLEEP_ENABLE  /* For backward compatibility */
+#endif /* RCC_AHB3LPENR_AXISRAMLPEN */
+
+#define __HAL_RCC_MDMA_CLK_SLEEP_DISABLE()            (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN))
+#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN))
+#if defined(JPEG)
+#define __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE()          (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN))
+#endif /* JPEG */
+#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN))
+#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE()             (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN))
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE()            (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN))
+#endif /*QUADSPI*/
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE()          (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN))
+#if defined(OCTOSPI1)
+#define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OSPI1LPEN))
+#endif /*OCTOSPI1*/
+#if defined(OCTOSPI2)
+#define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OSPI2LPEN))
+#endif /*OCTOSPI2*/
+#if defined(OCTOSPIM)
+#define __HAL_RCC_IOMNGR_CLK_SLEEP_DISABLE()          (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_IOMNGRLPEN))
+#endif /*OCTOSPIM*/
+#if defined(OTFDEC1)
+#define __HAL_RCC_OTFDEC1_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OTFDEC1LPEN))
+#endif /*OTFDEC1*/
+#if defined(OTFDEC2)
+#define __HAL_RCC_OTFDEC2_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OTFDEC2LPEN))
+#endif /*OTFDEC2*/
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_GFXMMULPEN))
+#endif /*GFXMMU*/
+#if defined(CD_AXISRAM2_BASE)
+#define __HAL_RCC_AXISRAM2_CLK_SLEEP_DISABLE()         (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM2LPEN))
+#endif
+#if defined(CD_AXISRAM3_BASE)
+#define __HAL_RCC_AXISRAM3_CLK_SLEEP_DISABLE()         (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM3LPEN))
+#endif
+#define __HAL_RCC_DTCM1_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN))
+#define __HAL_RCC_DTCM2_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN))
+#define __HAL_RCC_ITCM_CLK_SLEEP_DISABLE()            (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN))
+#if defined(RCC_AHB3LPENR_AXISRAMLPEN)
+#define __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE()         (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN))
+#define __HAL_RCC_AXISRAM_CLK_SLEEP_DISABLE           __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE
+#else
+#define __HAL_RCC_AXISRAM1_CLK_SLEEP_DISABLE()        (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM1LPEN))
+#define __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE          __HAL_RCC_AXISRAM1_CLK_SLEEP_DISABLE      /* For backward compatibility */
+#endif  /* RCC_AHB3LPENR_AXISRAMLPEN */
+
+/** @brief  Get the enable or disable status of the AHB3 peripheral clock during Low Poser (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+
+#define __HAL_RCC_MDMA_IS_CLK_SLEEP_ENABLED()             ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN)    != 0U)
+#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN)   != 0U)
+#if defined(JPEG)
+#define __HAL_RCC_JPGDEC_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_JPGDECLPEN)  != 0U)
+#endif /* JPEG */
+#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN)   != 0U)
+#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN)     != 0U)
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED()             ((RCC->AHB3LPENR & RCC_AHB3LPENR_QSPILPEN)    != 0U)
+#endif /*QUADSPI*/
+#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN)  != 0U)
+#if defined(OCTOSPI1)
+#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI1LPEN)    != 0U)
+#endif /*OCTOSPI1*/
+#if defined(OCTOSPI2)
+#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI2LPEN)    != 0U)
+#endif /*OCTOSPI2*/
+#if defined(OCTOSPIM)
+#define __HAL_RCC_IOMNGR_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_IOMNGRLPEN)   != 0U)
+#endif /*OCTOSPIM*/
+#if defined(OTFDEC1)
+#define __HAL_RCC_OTFDEC1_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC1LPEN) != 0U)
+#endif /*OTFDEC1*/
+#if defined(OTFDEC2)
+#define __HAL_RCC_OTFDEC2_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC2LPEN) != 0U)
+#endif /*OTFDEC2*/
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_GFXMMULPEN)    != 0U)
+#endif /*GFXMMU*/
+#if defined(CD_AXISRAM2_BASE)
+#define __HAL_RCC_AXISRAM2_IS_CLK_SLEEP_ENABLED()         ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM2LPEN)   != 0U)
+#endif
+#if defined(CD_AXISRAM3_BASE)
+#define __HAL_RCC_AXISRAM3_IS_CLK_SLEEP_ENABLED()         ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM3LPEN)   != 0U)
+#endif
+#define __HAL_RCC_DTCM1_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN)   != 0U)
+#define __HAL_RCC_DTCM2_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN)   != 0U)
+#define __HAL_RCC_ITCM_IS_CLK_SLEEP_ENABLED()             ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN)    != 0U)
+#if defined(RCC_AHB3LPENR_AXISRAMLPEN)
+#define __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_ENABLED()          ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAMLPEN) != 0U)
+#else
+#define __HAL_RCC_AXISRAM1_IS_CLK_SLEEP_ENABLED()         ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM1LPEN) != 0U)
+#endif
+
+#define __HAL_RCC_MDMA_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN)    == 0U)
+#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN)   == 0U)
+#if defined(JPEG)
+#define __HAL_RCC_JPGDEC_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB3LPENR & RCC_AHB3LPENR_JPGDECLPEN)  == 0U)
+#endif /* JPEG */
+#define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN)   == 0U)
+#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN)     == 0U)
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_QSPILPEN)    == 0U)
+#endif /*QUADSPI*/
+#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN)  == 0U)
+#if defined(OCTOSPI1)
+#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI1LPEN)  == 0U)
+#endif /*OCTOSPI1*/
+#if defined(OCTOSPI2)
+#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI2LPEN)  == 0U)
+#endif /*OCTOSPI2*/
+#if defined(OCTOSPIM)
+#define __HAL_RCC_IOMNGR_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_IOMNGRLPEN) == 0U)
+#endif /*OCTOSPIM*/
+#if defined(OTFDEC1)
+#define __HAL_RCC_OTFDEC1_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC1LPEN)  == 0U)
+#endif /*OTFDEC1*/
+#if defined(OTFDEC2)
+#define __HAL_RCC_OTFDEC2_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC2LPEN)  == 0U)
+#endif /*OTFDEC2*/
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_GFXMMULPEN)  == 0U)
+#endif /*GFXMMU*/
+#if defined(CD_AXISRAM2_BASE)
+#define __HAL_RCC_AXISRAM2_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM2LPEN)  == 0U)
+#endif
+#if defined(CD_AXISRAM3_BASE)
+#define __HAL_RCC_AXISRAM3_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM3LPEN)  == 0U)
+#endif
+#define __HAL_RCC_DTCM1_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN)   == 0U)
+#define __HAL_RCC_DTCM2_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN)   == 0U)
+#define __HAL_RCC_ITCM_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN)    == 0U)
+#if defined(RCC_AHB3LPENR_AXISRAMLPEN)
+#define __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAMLPEN) == 0U)
+#else
+#define __HAL_RCC_AXISRAM1_IS_CLK_SLEEP_DISABLED()        ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAML1PEN) == 0U)
+#endif /* RCC_AHB3LPENR_AXISRAMLPEN */
+
+/** @brief  ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE()             (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
+#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE()             (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
+#define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE()            (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN))
+#if defined(RCC_AHB1LPENR_CRCLPEN)
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()              (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
+#endif
+#if defined(ETH)
+#define __HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE()          (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN))
+#endif /*ETH*/
+#if defined(DUAL_CORE)
+#define __HAL_RCC_ART_CLK_SLEEP_ENABLE()              (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ARTLPEN))
+#endif /*DUAL_CORE*/
+#if defined(ETH)
+#define __HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE()           (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN))
+#define __HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE()           (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN))
+#endif /*ETH*/
+#define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN))
+#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
+#if defined(USB2_OTG_FS)
+#define __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN))
+#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
+#endif /* USB2_OTG_FS */
+
+#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE()             (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN))
+#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE()             (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN))
+#define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE()            (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN))
+#if defined(RCC_AHB1LPENR_CRCLPEN)
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()              (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_CRCLPEN))
+#endif
+#if defined(ETH)
+#define __HAL_RCC_ETH1MAC_CLK_SLEEP_DISABLE()          (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN))
+#endif  /*ETH*/
+#if defined(DUAL_CORE)
+#define __HAL_RCC_ART_CLK_SLEEP_DISABLE()              (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ARTLPEN))
+#endif /*DUAL_CORE*/
+#if defined(ETH)
+#define __HAL_RCC_ETH1TX_CLK_SLEEP_DISABLE()           (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN))
+#define __HAL_RCC_ETH1RX_CLK_SLEEP_DISABLE()           (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN))
+#endif  /*ETH*/
+#define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()      (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN))
+#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
+#if defined(USB2_OTG_FS)
+#define __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()      (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN))
+#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
+#endif /* USB2_OTG_FS */
+
+/** @brief  Get the enable or disable status of the AHB1 peripheral clock during Low Poser (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+
+#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN))          != 0U)
+#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN))          != 0U)
+#define __HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED()             ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN))         != 0U)
+#if defined(RCC_AHB1LPENR_CRCLPEN)
+#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED()                ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN))         != 0U)
+#endif
+#if defined(ETH)
+#define __HAL_RCC_ETH1MAC_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1MACLPEN))       != 0U)
+#endif  /*ETH*/
+#if defined(DUAL_CORE)
+#define __HAL_RCC_ART_IS_CLK_SLEEP_ENABLED()               ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ARTLPEN))       != 0U)
+#endif /*DUAL_CORE*/
+#if defined(ETH)
+#define __HAL_RCC_ETH1TX_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1TXLPEN))        != 0U)
+#define __HAL_RCC_ETH1RX_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1RXLPEN))        != 0U)
+#endif  /*ETH*/
+#define __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_ENABLED()       ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN))     != 0U)
+#define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED()  ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) != 0U)
+#if defined(USB2_OTG_FS)
+#define __HAL_RCC_USB2_OTG_FS_IS_CLK_SLEEP_ENABLED()       ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSLPEN))     != 0U)
+#define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_SLEEP_ENABLED()  ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) != 0U)
+#endif /* USB2_OTG_FS */
+
+#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN))          == 0U)
+#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN))          == 0U)
+#define __HAL_RCC_ADC12_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN))         == 0U)
+#if defined(RCC_AHB1LPENR_CRCLPEN)
+#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED()              ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN))           == 0U)
+#endif
+#if defined(ETH)
+#define __HAL_RCC_ETH1MAC_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1MACLPEN))       == 0U)
+#endif /* ETH */
+#if defined(DUAL_CORE)
+#define __HAL_RCC_ART_IS_CLK_SLEEP_DISABLED()              ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ARTLPEN))           == 0U)
+#endif /*DUAL_CORE*/
+#if defined(ETH)
+#define __HAL_RCC_ETH1TX_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1TXLPEN))        == 0U)
+#define __HAL_RCC_ETH1RX_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1RXLPEN))        == 0U)
+#endif /* ETH */
+#define __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_DISABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN))     == 0U)
+#define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) == 0U)
+#if defined(USB2_OTG_FS)
+#define __HAL_RCC_USB2_OTG_FS_IS_CLK_SLEEP_DISABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSLPEN))     == 0U)
+#define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) == 0U)
+#endif /* USB2_OTG_FS */
+
+
+/** @brief  ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#if defined(DCMI) && defined(PSSI)
+#define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE()        (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMI_PSSILPEN))
+#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE()             __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE()             (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
+#endif /* DCMI && PSSI */
+#if defined(CRYP)
+#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE()             (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE()             (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
+#endif /* HASH */
+#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()              (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
+#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE()           (RCC->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))
+#if defined(RCC_AHB2LPENR_DFSDMDMALPEN)
+#define __HAL_RCC_DFSDMDMA_CLK_SLEEP_ENABLE()         (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DFSDMDMALPEN))
+#endif
+#if defined(RCC_AHB2LPENR_D2SRAM1LPEN)
+#define __HAL_RCC_D2SRAM1_CLK_SLEEP_ENABLE()          (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN))
+#else
+#define __HAL_RCC_AHBSRAM1_CLK_SLEEP_ENABLE()         (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AHBSRAM1LPEN))
+#endif /* RCC_AHB2LPENR_D2SRAM1LPEN */
+#if defined(RCC_AHB2LPENR_D2SRAM2LPEN)
+#define __HAL_RCC_D2SRAM2_CLK_SLEEP_ENABLE()          (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN))
+#else
+#define __HAL_RCC_AHBSRAM2_CLK_SLEEP_ENABLE()         (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AHBSRAM2LPEN))
+#endif /* RCC_AHB2LPENR_D2SRAM2LPEN */
+#if defined(RCC_AHB2LPENR_D2SRAM3LPEN)
+#define __HAL_RCC_D2SRAM3_CLK_SLEEP_ENABLE()          (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN))
+#endif
+
+#if defined(DCMI) && defined(PSSI)
+#define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE()        (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMI_PSSILPEN))
+#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE()             __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE()             (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))
+#endif /* DCMI && PSSI */
+#if defined(CRYP)
+#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE()             (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE()             (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))
+#endif /* HASH */
+#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()              (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))
+#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE()           (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))
+#if defined(RCC_AHB2LPENR_DFSDMDMALPEN)
+#define __HAL_RCC_DFSDMDMA_CLK_SLEEP_DISABLE()         (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DFSDMDMALPEN))
+#endif
+#if defined(RCC_AHB2LPENR_D2SRAM1LPEN)
+#define __HAL_RCC_D2SRAM1_CLK_SLEEP_DISABLE()          (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN))
+#else
+#define __HAL_RCC_AHBSRAM1_CLK_SLEEP_DISABLE()         (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_AHBSRAM1LPEN))
+#endif /* RCC_AHB2LPENR_D2SRAM1LPEN */
+#if defined(RCC_AHB2LPENR_D2SRAM2LPEN)
+#define __HAL_RCC_D2SRAM2_CLK_SLEEP_DISABLE()          (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN))
+#else
+#define __HAL_RCC_AHBSRAM2_CLK_SLEEP_DISABLE()          (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_AHBSRAM2LPEN))
+#endif /* RCC_AHB2LPENR_D2SRAM2LPEN */
+#if defined(RCC_AHB2LPENR_D2SRAM3LPEN)
+#define __HAL_RCC_D2SRAM3_CLK_SLEEP_DISABLE()          (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN))
+#endif
+
+/** @brief  Get the enable or disable status of the AHB2 peripheral clock during Low Poser (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+
+#if defined(DCMI) && defined(PSSI)
+#define __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_ENABLED()         ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMI_PSSILPEN))    != 0U)
+#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED()              __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_ENABLED()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN))    != 0U)
+#endif /* DCMI && PSSI */
+#if defined(CRYP)
+#define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN))    != 0U)
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN))    != 0U)
+#endif /* HASH */
+#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED()               ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN))     != 0U)
+#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN))  != 0U)
+#if defined(RCC_AHB2LPENR_DFSDMDMALPEN)
+#define __HAL_RCC_DFSDMDMA_IS_CLK_SLEEP_ENABLED()          ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DFSDMDMALPEN)) != 0U)
+#endif
+#if defined(RCC_AHB2LPENR_D2SRAM1LPEN)
+#define __HAL_RCC_D2SRAM1_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM1LPEN)) != 0U)
+#else
+#define __HAL_RCC_AHBSRAM1_IS_CLK_SLEEP_ENABLED()          ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM1LPEN)) != 0U)
+#endif /* RCC_AHB2LPENR_D2SRAM1LPEN */
+#if defined(RCC_AHB2LPENR_D2SRAM2LPEN)
+#define __HAL_RCC_D2SRAM2_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM2LPEN)) != 0U)
+#else
+#define __HAL_RCC_AHBSRAM2_IS_CLK_SLEEP_ENABLED()          ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM2LPEN)) != 0U)
+#endif /* RCC_AHB2LPENR_D2SRAM2LPEN */
+#if defined(RCC_AHB2LPENR_D2SRAM3LPEN)
+#define __HAL_RCC_D2SRAM3_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM3LPEN)) != 0U)
+#endif /* RCC_AHB2LPENR_D2SRAM3LPEN */
+
+#if defined(DCMI) && defined(PSSI)
+#define __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_DISABLED()        ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMI_PSSILPEN))    == 0U)
+#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED()             __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_DISABLED()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN))    == 0U)
+#endif /* DCMI && PSSI */
+#if defined(CRYP)
+#define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN))    == 0U)
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN))    == 0U)
+#endif /* HASH */
+#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED()              ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN))     == 0U)
+#if defined(RCC_AHB2LPENR_DFSDMDMALPEN)
+#define __HAL_RCC_DFSDMDMA_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DFSDMDMALPEN)) == 0U)
+#endif
+#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN))  == 0U)
+#if defined(RCC_AHB2LPENR_D2SRAM1LPEN)
+#define __HAL_RCC_D2SRAM1_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM1LPEN)) == 0U)
+#else
+#define __HAL_RCC_AHBSRAM1_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM1LPEN)) == 0U)
+#endif /* RCC_AHB2LPENR_D2SRAM1LPEN */
+#if defined(RCC_AHB2LPENR_D2SRAM2LPEN)
+#define __HAL_RCC_D2SRAM2_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM2LPEN)) == 0U)
+#else
+#define __HAL_RCC_AHBSRAM2_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM2LPEN)) == 0U)
+#endif /* RCC_AHB2LPENR_D2SRAM2LPEN */
+#if defined(RCC_AHB2LPENR_D2SRAM3LPEN)
+#define __HAL_RCC_D2SRAM3_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM3LPEN)) == 0U)
+#endif /* RCC_AHB2LPENR_D2SRAM1LPEN*/
+
+
+/** @brief  ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN)
+#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN)
+#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN)
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN)
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN)
+#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN)
+#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN)
+#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN)
+#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN)
+#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN)
+#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN)
+#if defined(RCC_AHB4LPENR_CRCLPEN)
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()             (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN)
+#endif
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_CLK_SLEEP_ENABLE()            (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BDMA2LPEN)
+#define __HAL_RCC_BDMA_CLK_SLEEP_ENABLE  __HAL_RCC_BDMA2_CLK_SLEEP_ENABLE /* for API backward compatibility*/
+#else
+#define __HAL_RCC_BDMA_CLK_SLEEP_ENABLE()            (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN)
+#endif /* BDMA2 */
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE()            (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN)
+#endif /* ADC3 */
+#define __HAL_RCC_BKPRAM_CLK_SLEEP_ENABLE()          (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN)
+#if defined(RCC_AHB4LPENR_SRDSRAMLPEN)
+#define __HAL_RCC_SRDSRAM_CLK_SLEEP_ENABLE()         (RCC->AHB4LPENR  |= (RCC_AHB4LPENR_SRDSRAMLPEN))
+#define __HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE  __HAL_RCC_SRDSRAM_CLK_SLEEP_ENABLE /* for API backward compatibility*/
+#else
+#define __HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE()         (RCC->AHB4LPENR  |= (RCC_AHB4LPENR_D3SRAM1LPEN))
+#endif /* RCC_AHB4LPENR_SRDSRAMLPEN */
+
+#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN)
+#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN)
+#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN)
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN)
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN)
+#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN)
+#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN)
+#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN)
+#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN)
+#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN)
+#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN)
+#if defined(RCC_AHB4LPENR_CRCLPEN)
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()             (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN)
+#endif
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_CLK_SLEEP_DISABLE()            (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMA2LPEN)
+#define __HAL_RCC_BDMA_CLK_SLEEP_DISABLE  __HAL_RCC_BDMA2_CLK_SLEEP_DISABLE  /* For API backward compatibility*/
+#else
+#define __HAL_RCC_BDMA_CLK_SLEEP_DISABLE()            (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN)
+#endif /*BDMA2*/
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE()            (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN)
+#endif /*ADC3*/
+#define __HAL_RCC_BKPRAM_CLK_SLEEP_DISABLE()          (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN)
+#if defined(RCC_AHB4LPENR_SRDSRAMLPEN)
+#define __HAL_RCC_SRDSRAM_CLK_SLEEP_DISABLE()         (RCC->AHB4LPENR  &= ~ (RCC_AHB4LPENR_SRDSRAMLPEN))
+#define __HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE  __HAL_RCC_SRDSRAM_CLK_SLEEP_DISABLE
+#else
+#define __HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE()         (RCC->AHB4LPENR  &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN))
+#endif
+
+
+/** @brief  Get the enable or disable status of the AHB4 peripheral clock during Low Poser (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+
+#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN))   != 0U)
+#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN))   != 0U)
+#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN))   != 0U)
+#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN))   != 0U)
+#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN))   != 0U)
+#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN))   != 0U)
+#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN))   != 0U)
+#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN))   != 0U)
+#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN))   != 0U)
+#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN))   != 0U)
+#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN))   != 0U)
+#if defined(RCC_AHB4LPENR_CRCLPEN)
+#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB4LPENR & (RCC_AHB4LPENR_CRCLPEN))     != 0U)
+#endif
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMA2LPEN))    != 0U)
+#define __HAL_RCC_BDMA_IS_CLK_SLEEP_ENABLED __HAL_RCC_BDMA2_IS_CLK_SLEEP_ENABLED  /* For API backward compatibility*/
+#else
+#define __HAL_RCC_BDMA_IS_CLK_SLEEP_ENABLED()             ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMALPEN))    != 0U)
+#endif /*BDMA2*/
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED()             ((RCC->AHB4LPENR & (RCC_AHB4LPENR_ADC3LPEN))    != 0U)
+#endif /*ADC3*/
+#define __HAL_RCC_BKPRAM_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN))  != 0U)
+#if defined(RCC_AHB4LPENR_SRDSRAMLPEN)
+#define __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_ENABLED()          ((RCC->AHB4LPENR & (RCC_AHB4LPENR_SRDSRAMLPEN)) != 0U)
+#define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_ENABLED  __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_ENABLED  /* For API backward compatibility*/
+#else
+#define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_ENABLED()          ((RCC->AHB4LPENR & (RCC_AHB4LPENR_D3SRAM1LPEN)) != 0U)
+#endif
+
+#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN))   == 0U)
+#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN))   == 0U)
+#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN))   == 0U)
+#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN))   == 0U)
+#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN))   == 0U)
+#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN))   == 0U)
+#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN))   == 0U)
+#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN))   == 0U)
+#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN))   == 0U)
+#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN))   == 0U)
+#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN))   == 0U)
+#if defined(RCC_AHB4LPENR_CRCLPEN)
+#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB4LPENR & (RCC_AHB4LPENR_CRCLPEN))     == 0U)
+#endif
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMA2LPEN))  == 0U)
+#define __HAL_RCC_BDMA_IS_CLK_SLEEP_DISABLED __HAL_RCC_BDMA2_IS_CLK_SLEEP_DISABLED  /* For API backward compatibility*/
+#else
+#define __HAL_RCC_BDMA_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMALPEN))    == 0U)
+#endif /*BDMA2*/
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_ADC3LPEN))    == 0U)
+#endif /*ADC3*/
+#define __HAL_RCC_BKPRAM_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN))  == 0U)
+#if defined(RCC_AHB4LPENR_SRDSRAMLPEN)
+#define __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB4LPENR & (RCC_AHB4LPENR_SRDSRAMLPEN)) == 0U)
+#define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_DISABLED  __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_DISABLED  /* For API backward compatibility*/
+#else
+#define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB4LPENR & (RCC_AHB4LPENR_D3SRAM1LPEN)) == 0U)
+#endif
+
+
+/** @brief  ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE()           (RCC->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN)
+#endif /* LTDC */
+#if defined(DSI)
+#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE()            (RCC->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN)
+#endif /*DSI*/
+#define __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE()          (RCC->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN)
+
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE()           (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN)
+#endif /* LTDC */
+#if defined(DSI)
+#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE()            (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN)
+#endif /*DSI*/
+#define __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE()          (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN)
+
+
+/** @brief  Get the enable or disable status of the APB3 peripheral clock during Low Poser (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED()            ((RCC->APB3LPENR & (RCC_APB3LPENR_LTDCLPEN))  != 0U)
+#endif /* LTDC */
+#if defined(DSI)
+#define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED()             ((RCC->APB3LPENR & (RCC_APB3LPENR_DSILPEN))   != 0U)
+#endif /*DSI*/
+#define __HAL_RCC_WWDG1_IS_CLK_SLEEP_ENABLED()           ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) != 0U)
+
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED()           ((RCC->APB3LPENR & (RCC_APB3LPENR_LTDCLPEN))  == 0U)
+#endif /* LTDC */
+#if defined(DSI)
+#define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED()            ((RCC->APB3LPENR & (RCC_APB3LPENR_DSILPEN))   == 0U)
+#endif /*DSI*/
+#define __HAL_RCC_WWDG1_IS_CLK_SLEEP_DISABLED()          ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) == 0U)
+
+
+/** @brief  ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN)
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN)
+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN)
+#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN)
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN)
+#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN)
+#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN)
+#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN)
+#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN)
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE()         (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN)
+
+#if defined(DUAL_CORE)
+#define __HAL_RCC_WWDG2_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN)
+#endif /*DUAL_CORE*/
+
+#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN)
+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN)
+#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE()        (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN)
+#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE()         (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN)
+#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()         (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN)
+#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN)
+#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN)
+#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN)
+#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN)
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN)
+#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE()            (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN)
+#define __HAL_RCC_DAC12_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN)
+#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN)
+#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN)
+#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE()            (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN)
+#define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE()          (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN)
+#define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE()          (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN)
+#define __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE()          (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN)
+#define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE()          (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN)
+
+
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN)
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN)
+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN)
+#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN)
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN)
+#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN)
+#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN)
+#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN)
+#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN)
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE()         (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN)
+
+#if defined(DUAL_CORE)
+#define __HAL_RCC_WWDG2_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN)
+#endif /*DUAL_CORE*/
+
+#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN)
+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN)
+#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()        (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN)
+#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE()         (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN)
+#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE()         (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN)
+#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN)
+#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN)
+#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN)
+#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN)
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN)
+#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE()            (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN)
+#define __HAL_RCC_DAC12_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN)
+#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN)
+#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN)
+#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE()            (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN)
+#define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE()          (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN)
+#define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE()          (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN)
+#define __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE()          (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN)
+#define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE()          (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN)
+
+
+/** @brief  Get the enable or disable status of the APB1 peripheral clock during Low Poser (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+
+#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN))    != 0U)
+#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN))    != 0U)
+#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN))    != 0U)
+#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN))    != 0U)
+#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN))    != 0U)
+#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN))    != 0U)
+#define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN))   != 0U)
+#define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN))   != 0U)
+#define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN))   != 0U)
+#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN))  != 0U)
+#if defined(DUAL_CORE)
+#define __HAL_RCC_WWDG2_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_WWDG2LPEN))   != 0U)
+#endif /*DUAL_CORE*/
+#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN))    != 0U)
+#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN))    != 0U)
+#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED()         ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) != 0U)
+#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN))  != 0U)
+#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN))  != 0U)
+#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN))   != 0U)
+#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN))   != 0U)
+#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN))    != 0U)
+#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN))    != 0U)
+#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN))    != 0U)
+#define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED()             ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN))     != 0U)
+#define __HAL_RCC_DAC12_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN))   != 0U)
+#define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN))   != 0U)
+#define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN))   != 0U)
+#define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED()             ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN))     != 0U)
+#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED()          ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN))   != 0U)
+#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN))   != 0U)
+#define __HAL_RCC_MDIOS_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN))   != 0U)
+#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN))   != 0U)
+
+#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN))    == 0U)
+#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN))    == 0U)
+#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN))    == 0U)
+#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN))    == 0U)
+#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN))    == 0U)
+#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN))    == 0U)
+#define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN))   == 0U)
+#define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN))   == 0U)
+#define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN))   == 0U)
+#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED()         ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN))  == 0U)
+#if defined(DUAL_CORE)
+#define __HAL_RCC_WWDG2_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_WWDG2LPEN))   == 0U)
+#endif /*DUAL_CORE*/
+#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN))    == 0U)
+#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN))    == 0U)
+#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED()        ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) == 0U)
+#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED()         ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN))  == 0U)
+#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED()         ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN))  == 0U)
+#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN))   == 0U)
+#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN))   == 0U)
+#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN))    == 0U)
+#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN))    == 0U)
+#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN))    == 0U)
+#define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN))     == 0U)
+#define __HAL_RCC_DAC12_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN))   == 0U)
+#define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN))   == 0U)
+#define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN))   == 0U)
+#define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED()            ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN))     == 0U)
+#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED()         ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN))   == 0U)
+#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN))   == 0U)
+#define __HAL_RCC_MDIOS_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN))   == 0U)
+#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN))   == 0U)
+
+
+/** @brief  ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN)
+#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN)
+#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE()         (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN)
+#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE()         (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN)
+#if defined(UART9)
+#define __HAL_RCC_UART9_CLK_SLEEP_ENABLE()          (RCC->APB2LPENR) |= (RCC_APB2LPENR_UART9LPEN)
+#endif /*UART9*/
+#if defined(USART10)
+#define __HAL_RCC_USART10_CLK_SLEEP_ENABLE()        (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART10LPEN)
+#endif /*USART10*/
+#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN)
+#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN)
+#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE()          (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN)
+#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE()          (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN)
+#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE()          (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN)
+#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN)
+#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN)
+#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN)
+#if defined(SAI3)
+#define __HAL_RCC_SAI3_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN)
+#endif /*SAI3*/
+#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE()         (RCC->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN)
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_CLK_SLEEP_ENABLE()         (RCC->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN)
+#endif /*HRTIM1*/
+
+#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN)
+#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN)
+#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE()         (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN)
+#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE()         (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN)
+#if defined(UART9)
+#define __HAL_RCC_UART9_CLK_SLEEP_DISABLE()          (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_UART9LPEN)
+#endif /*UART9*/
+#if defined(USART10)
+#define __HAL_RCC_USART10_CLK_SLEEP_DISABLE()         (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART10LPEN)
+#endif /*USART10*/
+#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN)
+#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN)
+#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE()          (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN)
+#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE()          (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN)
+#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE()          (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN)
+#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN)
+#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN)
+#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN)
+#if defined(SAI3)
+#define __HAL_RCC_SAI3_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN)
+#endif /*SAI3*/
+#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE()         (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN)
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_CLK_SLEEP_DISABLE()         (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN)
+#endif /*HRTIM1*/
+
+
+/** @brief  Get the enable or disable status of the APB2 peripheral clock during Low Poser (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+
+#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN))   != 0U)
+#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN))   != 0U)
+#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != 0U)
+#define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != 0U)
+#if defined(UART9)
+#define __HAL_RCC_UART9_IS_CLK_SLEEP_ENABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_UART9LPEN)) != 0U)
+#endif /*UART9*/
+#if defined(USART10)
+#define __HAL_RCC_USART10_IS_CLK_SLEEP_ENABLED()         ((RCC->APB2LPENR & (RCC_APB2LPENR_USART10LPEN)) != 0U)
+#endif /*USART10*/
+#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN))   != 0U)
+#define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN))   != 0U)
+#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN))  != 0U)
+#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN))  != 0U)
+#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN))  != 0U)
+#define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN))   != 0U)
+#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN))   != 0U)
+#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN))   != 0U)
+#if defined(SAI3)
+#define __HAL_RCC_SAI3_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI3LPEN))   != 0U)
+#endif /*SAI3*/
+#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != 0U)
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_ENABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_HRTIMLPEN))  != 0U)
+#endif /*HRTIM1*/
+
+#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN))   == 0U)
+#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN))   == 0U)
+#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED()         ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == 0U)
+#define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED()         ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == 0U)
+#if defined(UART9)
+#define __HAL_RCC_USART9_IS_CLK_SLEEP_DISABLED()         ((RCC->APB2LPENR & (RCC_APB2LPENR_USART9LPEN)) == 0U)
+#endif /*UART9*/
+#if defined(USART10)
+#define __HAL_RCC_USART10_IS_CLK_SLEEP_DISABLED()        ((RCC->APB2LPENR & (RCC_APB2LPENR_USART10LPEN)) == 0U)
+#endif /*USART10*/
+#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN))   == 0U)
+#define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN))   == 0U)
+#define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN))  == 0U)
+#define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN))  == 0U)
+#define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN))  == 0U)
+#define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN))   == 0U)
+#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN))   == 0U)
+#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN))   == 0U)
+#if defined(SAI3)
+#define __HAL_RCC_SAI3_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI3LPEN))   == 0U)
+#endif /*SAI3*/
+#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED()         ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == 0U)
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_DISABLED()         ((RCC->APB2LPENR & (RCC_APB2LPENR_HRTIMLPEN))  == 0U)
+#endif /*HRTIM1*/
+
+/** @brief  ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN)
+#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE()          (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN)
+#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE()             (RCC->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN)
+#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE()             (RCC->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN)
+#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN)
+#define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN)
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN)
+#endif /*LPTIM4*/
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN)
+#endif /*LPTIM5*/
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_DAC2LPEN)
+#endif /*DAC2*/
+#define __HAL_RCC_COMP12_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN)
+#define __HAL_RCC_VREF_CLK_SLEEP_ENABLE()             (RCC->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN)
+#define __HAL_RCC_RTC_CLK_SLEEP_ENABLE()              (RCC->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN)
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_CLK_SLEEP_ENABLE()             (RCC->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN)
+#endif /*SAI4*/
+#if defined(DTS)
+#define __HAL_RCC_DTS_CLK_SLEEP_ENABLE()              (RCC->APB4LPENR) |= (RCC_APB4LPENR_DTSLPEN)
+#endif /*DTS*/
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_DFSDM2LPEN)
+#endif /*DFSDM2*/
+
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN)
+#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE()          (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN)
+#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE()             (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN)
+#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE()             (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN)
+#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN)
+#define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN)
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN)
+#endif /*LPTIM4*/
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN)
+#endif /*LPTIM5*/
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_CLK_SLEEP_DISABLE()             (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DAC2LPEN)
+#endif /*DAC2*/
+#define __HAL_RCC_COMP12_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN)
+#define __HAL_RCC_VREF_CLK_SLEEP_DISABLE()             (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN)
+#define __HAL_RCC_RTC_CLK_SLEEP_DISABLE()              (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN)
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_CLK_SLEEP_DISABLE()             (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN)
+#endif /*SAI4*/
+#if defined(DTS)
+#define __HAL_RCC_DTS_CLK_SLEEP_DISABLE()              (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DTSLPEN)
+#endif /*DTS*/
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_CLK_SLEEP_DISABLE()          (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DFSDM2LPEN)
+#endif /*DFSDM2*/
+
+
+/** @brief  Get the enable or disable status of the APB4 peripheral clock during Low Poser (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+
+#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN))  != 0U)
+#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) != 0U)
+#define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN))    != 0U)
+#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN))    != 0U)
+#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN))  != 0U)
+#define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN))  != 0U)
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM4LPEN))  != 0U)
+#endif /*LPTIM4*/
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM5LPEN))  != 0U)
+#endif /*LPTIM5*/
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_IS_CLK_SLEEP_ENABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_DAC2LPEN))  != 0U)
+#endif /*DAC2*/
+#define __HAL_RCC_COMP12_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN))  != 0U)
+#define __HAL_RCC_VREF_IS_CLK_SLEEP_ENABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN))    != 0U)
+#define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED()               ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN))  != 0U)
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_IS_CLK_SLEEP_ENABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_SAI4LPEN))    != 0U)
+#endif /*SAI4*/
+#if defined(DTS)
+#define __HAL_RCC_DTS_IS_CLK_SLEEP_ENABLED()               ((RCC->APB4LPENR & (RCC_APB4LPENR_DTSLPEN))    != 0U)
+#endif /*DTS*/
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_DFSDM2LPEN)) != 0U)
+#endif /*DFSDM2*/
+
+#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN))  == 0U)
+#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED()          ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) == 0U)
+#define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED()             ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN))    == 0U)
+#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED()             ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN))    == 0U)
+#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN))  == 0U)
+#define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN))  == 0U)
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM4LPEN))  == 0U)
+#endif /*LPTIM4*/
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM5LPEN))  == 0U)
+#endif /*LPTIM5*/
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_IS_CLK_SLEEP_DISABLED()             ((RCC->APB4LPENR & (RCC_APB4LPENR_DAC2LPEN))  == 0U)
+#endif /*DAC2*/
+#define __HAL_RCC_COMP12_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN))  == 0U)
+#define __HAL_RCC_VREF_IS_CLK_SLEEP_DISABLED()             ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN))    == 0U)
+#define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN))  == 0U)
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_IS_CLK_SLEEP_DISABLED()             ((RCC->APB4LPENR & (RCC_APB4LPENR_SAI4LPEN))    == 0U)
+#endif /*SAI4*/
+#if defined(DTS)
+#define __HAL_RCC_DTS_IS_CLK_SLEEP_DISABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_DTSLPEN))    == 0U)
+#endif /*DTS*/
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_DFSDM2LPEN)) == 0U)
+#endif /*DFSDM2*/
+
+
+#if defined(DUAL_CORE)
+
+/** @brief  Enable or disable the RCC_C1 AHB3 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+#define __HAL_RCC_C1_MDMA_CLK_SLEEP_ENABLE()            (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN))
+#define __HAL_RCC_C1_DMA2D_CLK_SLEEP_ENABLE()           (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN))
+#define __HAL_RCC_C1_JPGDEC_CLK_SLEEP_ENABLE()          (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN))
+#define __HAL_RCC_C1_FLASH_CLK_SLEEP_ENABLE()           (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN))
+#define __HAL_RCC_C1_FMC_CLK_SLEEP_ENABLE()             (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
+#define __HAL_RCC_C1_QSPI_CLK_SLEEP_ENABLE()            (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
+#define __HAL_RCC_C1_SDMMC1_CLK_SLEEP_ENABLE()          (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN))
+#define __HAL_RCC_C1_DTCM1_CLK_SLEEP_ENABLE()           (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN))
+#define __HAL_RCC_C1_DTCM2_CLK_SLEEP_ENABLE()           (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN))
+#define __HAL_RCC_C1_ITCM_CLK_SLEEP_ENABLE()            (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN))
+#define __HAL_RCC_C1_D1SRAM1_CLK_SLEEP_ENABLE()         (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN))
+
+
+#define __HAL_RCC_C1_MDMA_CLK_SLEEP_DISABLE()            (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN))
+#define __HAL_RCC_C1_DMA2D_CLK_SLEEP_DISABLE()           (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN))
+#define __HAL_RCC_C1_JPGDEC_CLK_SLEEP_DISABLE()          (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN))
+#define __HAL_RCC_C1_FLASH_CLK_SLEEP_DISABLE()           (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN))
+#define __HAL_RCC_C1_FMC_CLK_SLEEP_DISABLE()             (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN))
+#define __HAL_RCC_C1_QSPI_CLK_SLEEP_DISABLE()            (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN))
+#define __HAL_RCC_C1_SDMMC1_CLK_SLEEP_DISABLE()          (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN))
+#define __HAL_RCC_C1_DTCM1_CLK_SLEEP_DISABLE()           (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN))
+#define __HAL_RCC_C1_DTCM2_CLK_SLEEP_DISABLE()           (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN))
+#define __HAL_RCC_C1_ITCM_CLK_SLEEP_DISABLE()            (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN))
+#define __HAL_RCC_C1_D1SRAM1_CLK_SLEEP_DISABLE()         (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN))
+
+
+
+/** @brief  ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C1_DMA1_CLK_SLEEP_ENABLE()             (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
+#define __HAL_RCC_C1_DMA2_CLK_SLEEP_ENABLE()             (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
+#define __HAL_RCC_C1_ADC12_CLK_SLEEP_ENABLE()            (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN))
+#define __HAL_RCC_C1_ETH1MAC_CLK_SLEEP_ENABLE()          (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN))
+#define __HAL_RCC_C1_ETH1TX_CLK_SLEEP_ENABLE()           (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN))
+#define __HAL_RCC_C1_ETH1RX_CLK_SLEEP_ENABLE()           (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN))
+#define __HAL_RCC_C1_USB1_OTG_HS_CLK_SLEEP_ENABLE()      (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN))
+#define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
+#define __HAL_RCC_C1_USB2_OTG_FS_CLK_SLEEP_ENABLE()      (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN))
+#define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
+
+#define __HAL_RCC_C1_DMA1_CLK_SLEEP_DISABLE()             (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN))
+#define __HAL_RCC_C1_DMA2_CLK_SLEEP_DISABLE()             (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN))
+#define __HAL_RCC_C1_ADC12_CLK_SLEEP_DISABLE()            (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN))
+#define __HAL_RCC_C1_ETH1MAC_CLK_SLEEP_DISABLE()          (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN))
+#define __HAL_RCC_C1_ETH1TX_CLK_SLEEP_DISABLE()           (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN))
+#define __HAL_RCC_C1_ETH1RX_CLK_SLEEP_DISABLE()           (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN))
+#define __HAL_RCC_C1_USB1_OTG_HS_CLK_SLEEP_DISABLE()      (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN))
+#define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
+#define __HAL_RCC_C1_USB2_OTG_FS_CLK_SLEEP_DISABLE()      (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN))
+#define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
+
+/** @brief  ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C1_DCMI_CLK_SLEEP_ENABLE()             (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
+#if defined(CRYP)
+#define __HAL_RCC_C1_CRYP_CLK_SLEEP_ENABLE()             (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_C1_HASH_CLK_SLEEP_ENABLE()             (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
+#endif /* HASH */
+#define __HAL_RCC_C1_RNG_CLK_SLEEP_ENABLE()              (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
+#define __HAL_RCC_C1_SDMMC2_CLK_SLEEP_ENABLE()           (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))
+#define __HAL_RCC_C1_D2SRAM1_CLK_SLEEP_ENABLE()          (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN))
+#define __HAL_RCC_C1_D2SRAM2_CLK_SLEEP_ENABLE()          (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN))
+#define __HAL_RCC_C1_D2SRAM3_CLK_SLEEP_ENABLE()          (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN))
+
+#define __HAL_RCC_C1_DCMI_CLK_SLEEP_DISABLE()             (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))
+#if defined(CRYP)
+#define __HAL_RCC_C1_CRYP_CLK_SLEEP_DISABLE()             (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_C1_HASH_CLK_SLEEP_DISABLE()             (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))
+#endif /* HASH */
+#define __HAL_RCC_C1_RNG_CLK_SLEEP_DISABLE()              (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))
+#define __HAL_RCC_C1_SDMMC2_CLK_SLEEP_DISABLE()           (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))
+#define __HAL_RCC_C1_D2SRAM1_CLK_SLEEP_DISABLE()          (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN))
+#define __HAL_RCC_C1_D2SRAM2_CLK_SLEEP_DISABLE()          (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN))
+#define __HAL_RCC_C1_D2SRAM3_CLK_SLEEP_DISABLE()          (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN))
+
+/** @brief  ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C1_GPIOA_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN)
+#define __HAL_RCC_C1_GPIOB_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN)
+#define __HAL_RCC_C1_GPIOC_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN)
+#define __HAL_RCC_C1_GPIOD_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN)
+#define __HAL_RCC_C1_GPIOE_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN)
+#define __HAL_RCC_C1_GPIOF_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN)
+#define __HAL_RCC_C1_GPIOG_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN)
+#define __HAL_RCC_C1_GPIOH_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN)
+#define __HAL_RCC_C1_GPIOI_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN)
+#define __HAL_RCC_C1_GPIOJ_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN)
+#define __HAL_RCC_C1_GPIOK_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN)
+#define __HAL_RCC_C1_CRC_CLK_SLEEP_ENABLE()             (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN)
+#define __HAL_RCC_C1_BDMA_CLK_SLEEP_ENABLE()            (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN)
+#define __HAL_RCC_C1_ADC3_CLK_SLEEP_ENABLE()            (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN)
+#define __HAL_RCC_C1_BKPRAM_CLK_SLEEP_ENABLE()          (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN)
+#define __HAL_RCC_C1_D3SRAM1_CLK_SLEEP_ENABLE()         (RCC_C1->AHB4LPENR  |= (RCC_AHB4LPENR_D3SRAM1LPEN))
+
+#define __HAL_RCC_C1_GPIOA_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN)
+#define __HAL_RCC_C1_GPIOB_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN)
+#define __HAL_RCC_C1_GPIOC_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN)
+#define __HAL_RCC_C1_GPIOD_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN)
+#define __HAL_RCC_C1_GPIOE_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN)
+#define __HAL_RCC_C1_GPIOF_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN)
+#define __HAL_RCC_C1_GPIOG_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN)
+#define __HAL_RCC_C1_GPIOH_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN)
+#define __HAL_RCC_C1_GPIOI_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN)
+#define __HAL_RCC_C1_GPIOJ_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN)
+#define __HAL_RCC_C1_GPIOK_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN)
+#define __HAL_RCC_C1_CRC_CLK_SLEEP_DISABLE()             (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN)
+#define __HAL_RCC_C1_BDMA_CLK_SLEEP_DISABLE()            (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN)
+#define __HAL_RCC_C1_ADC3_CLK_SLEEP_DISABLE()            (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN)
+#define __HAL_RCC_C1_BKPRAM_CLK_SLEEP_DISABLE()          (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN)
+#define __HAL_RCC_C1_D3SRAM1_CLK_SLEEP_DISABLE()         (RCC_C1->AHB4LPENR  &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN))
+
+/** @brief  ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C1_LTDC_CLK_SLEEP_ENABLE()           (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN)
+#define __HAL_RCC_C1_DSI_CLK_SLEEP_ENABLE()            (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN)
+#define __HAL_RCC_C1_WWDG1_CLK_SLEEP_ENABLE()          (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN)
+
+#define __HAL_RCC_C1_LTDC_CLK_SLEEP_DISABLE()           (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN)
+#define __HAL_RCC_C1_DSI_CLK_SLEEP_DISABLE()            (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN)
+#define __HAL_RCC_C1_WWDG1_CLK_SLEEP_DISABLE()          (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN)
+
+/** @brief  ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C1_TIM2_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN)
+#define __HAL_RCC_C1_TIM3_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN)
+#define __HAL_RCC_C1_TIM4_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN)
+#define __HAL_RCC_C1_TIM5_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN)
+#define __HAL_RCC_C1_TIM6_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN)
+#define __HAL_RCC_C1_TIM7_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN)
+#define __HAL_RCC_C1_TIM12_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN)
+#define __HAL_RCC_C1_TIM13_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN)
+#define __HAL_RCC_C1_TIM14_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN)
+#define __HAL_RCC_C1_LPTIM1_CLK_SLEEP_ENABLE()         (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN)
+#define __HAL_RCC_C1_WWDG2_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN)
+#define __HAL_RCC_C1_SPI2_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN)
+#define __HAL_RCC_C1_SPI3_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN)
+#define __HAL_RCC_C1_SPDIFRX_CLK_SLEEP_ENABLE()        (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN)
+#define __HAL_RCC_C1_USART2_CLK_SLEEP_ENABLE()         (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN)
+#define __HAL_RCC_C1_USART3_CLK_SLEEP_ENABLE()         (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN)
+#define __HAL_RCC_C1_UART4_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN)
+#define __HAL_RCC_C1_UART5_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN)
+#define __HAL_RCC_C1_I2C1_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN)
+#define __HAL_RCC_C1_I2C2_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN)
+#define __HAL_RCC_C1_I2C3_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN)
+#define __HAL_RCC_C1_CEC_CLK_SLEEP_ENABLE()            (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN)
+#define __HAL_RCC_C1_DAC12_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN)
+#define __HAL_RCC_C1_UART7_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN)
+#define __HAL_RCC_C1_UART8_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN)
+#define __HAL_RCC_C1_CRS_CLK_SLEEP_ENABLE()            (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN)
+#define __HAL_RCC_C1_SWPMI_CLK_SLEEP_ENABLE()          (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN)
+#define __HAL_RCC_C1_OPAMP_CLK_SLEEP_ENABLE()          (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN)
+#define __HAL_RCC_C1_MDIOS_CLK_SLEEP_ENABLE()          (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN)
+#define __HAL_RCC_C1_FDCAN_CLK_SLEEP_ENABLE()          (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN)
+
+
+#define __HAL_RCC_C1_TIM2_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN)
+#define __HAL_RCC_C1_TIM3_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN)
+#define __HAL_RCC_C1_TIM4_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN)
+#define __HAL_RCC_C1_TIM5_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN)
+#define __HAL_RCC_C1_TIM6_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN)
+#define __HAL_RCC_C1_TIM7_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN)
+#define __HAL_RCC_C1_TIM12_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN)
+#define __HAL_RCC_C1_TIM13_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN)
+#define __HAL_RCC_C1_TIM14_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN)
+#define __HAL_RCC_C1_LPTIM1_CLK_SLEEP_DISABLE()         (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN)
+#define __HAL_RCC_C1_WWDG2_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN)
+#define __HAL_RCC_C1_SPI2_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN)
+#define __HAL_RCC_C1_SPI3_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN)
+#define __HAL_RCC_C1_SPDIFRX_CLK_SLEEP_DISABLE()        (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN)
+#define __HAL_RCC_C1_USART2_CLK_SLEEP_DISABLE()         (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN)
+#define __HAL_RCC_C1_USART3_CLK_SLEEP_DISABLE()         (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN)
+#define __HAL_RCC_C1_UART4_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN)
+#define __HAL_RCC_C1_UART5_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN)
+#define __HAL_RCC_C1_I2C1_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN)
+#define __HAL_RCC_C1_I2C2_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN)
+#define __HAL_RCC_C1_I2C3_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN)
+#define __HAL_RCC_C1_CEC_CLK_SLEEP_DISABLE()            (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN)
+#define __HAL_RCC_C1_DAC12_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN)
+#define __HAL_RCC_C1_UART7_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN)
+#define __HAL_RCC_C1_UART8_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN)
+#define __HAL_RCC_C1_CRS_CLK_SLEEP_DISABLE()            (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN)
+#define __HAL_RCC_C1_SWPMI_CLK_SLEEP_DISABLE()          (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN)
+#define __HAL_RCC_C1_OPAMP_CLK_SLEEP_DISABLE()          (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN)
+#define __HAL_RCC_C1_MDIOS_CLK_SLEEP_DISABLE()          (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN)
+#define __HAL_RCC_C1_FDCAN_CLK_SLEEP_DISABLE()          (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN)
+
+/** @brief  ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C1_TIM1_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN)
+#define __HAL_RCC_C1_TIM8_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN)
+#define __HAL_RCC_C1_USART1_CLK_SLEEP_ENABLE()         (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN)
+#define __HAL_RCC_C1_USART6_CLK_SLEEP_ENABLE()         (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN)
+#define __HAL_RCC_C1_SPI1_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN)
+#define __HAL_RCC_C1_SPI4_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN)
+#define __HAL_RCC_C1_TIM15_CLK_SLEEP_ENABLE()          (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN)
+#define __HAL_RCC_C1_TIM16_CLK_SLEEP_ENABLE()          (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN)
+#define __HAL_RCC_C1_TIM17_CLK_SLEEP_ENABLE()          (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN)
+#define __HAL_RCC_C1_SPI5_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN)
+#define __HAL_RCC_C1_SAI1_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN)
+#define __HAL_RCC_C1_SAI2_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN)
+#define __HAL_RCC_C1_SAI3_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN)
+#define __HAL_RCC_C1_DFSDM1_CLK_SLEEP_ENABLE()         (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN)
+#define __HAL_RCC_C1_HRTIM1_CLK_SLEEP_ENABLE()         (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN)
+
+#define __HAL_RCC_C1_TIM1_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN)
+#define __HAL_RCC_C1_TIM8_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN)
+#define __HAL_RCC_C1_USART1_CLK_SLEEP_DISABLE()         (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN)
+#define __HAL_RCC_C1_USART6_CLK_SLEEP_DISABLE()         (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN)
+#define __HAL_RCC_C1_SPI1_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN)
+#define __HAL_RCC_C1_SPI4_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN)
+#define __HAL_RCC_C1_TIM15_CLK_SLEEP_DISABLE()          (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN)
+#define __HAL_RCC_C1_TIM16_CLK_SLEEP_DISABLE()          (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN)
+#define __HAL_RCC_C1_TIM17_CLK_SLEEP_DISABLE()          (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN)
+#define __HAL_RCC_C1_SPI5_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN)
+#define __HAL_RCC_C1_SAI1_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN)
+#define __HAL_RCC_C1_SAI2_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN)
+#define __HAL_RCC_C1_SAI3_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN)
+#define __HAL_RCC_C1_DFSDM1_CLK_SLEEP_DISABLE()         (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN)
+#define __HAL_RCC_C1_HRTIM1_CLK_SLEEP_DISABLE()         (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN)
+
+/** @brief  ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C1_SYSCFG_CLK_SLEEP_ENABLE()           (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN)
+#define __HAL_RCC_C1_LPUART1_CLK_SLEEP_ENABLE()          (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN)
+#define __HAL_RCC_C1_SPI6_CLK_SLEEP_ENABLE()             (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN)
+#define __HAL_RCC_C1_I2C4_CLK_SLEEP_ENABLE()             (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN)
+#define __HAL_RCC_C1_LPTIM2_CLK_SLEEP_ENABLE()           (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN)
+#define __HAL_RCC_C1_LPTIM3_CLK_SLEEP_ENABLE()           (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN)
+#define __HAL_RCC_C1_LPTIM4_CLK_SLEEP_ENABLE()           (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN)
+#define __HAL_RCC_C1_LPTIM5_CLK_SLEEP_ENABLE()           (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN)
+#define __HAL_RCC_C1_COMP12_CLK_SLEEP_ENABLE()           (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN)
+#define __HAL_RCC_C1_VREF_CLK_SLEEP_ENABLE()             (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN)
+#define __HAL_RCC_C1_SAI4_CLK_SLEEP_ENABLE()             (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN)
+#define __HAL_RCC_C1_RTC_CLK_SLEEP_ENABLE()              (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN)
+
+
+#define __HAL_RCC_C1_SYSCFG_CLK_SLEEP_DISABLE()           (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN)
+#define __HAL_RCC_C1_LPUART1_CLK_SLEEP_DISABLE()          (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN)
+#define __HAL_RCC_C1_SPI6_CLK_SLEEP_DISABLE()             (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN)
+#define __HAL_RCC_C1_I2C4_CLK_SLEEP_DISABLE()             (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN)
+#define __HAL_RCC_C1_LPTIM2_CLK_SLEEP_DISABLE()           (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN)
+#define __HAL_RCC_C1_LPTIM3_CLK_SLEEP_DISABLE()           (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN)
+#define __HAL_RCC_C1_LPTIM4_CLK_SLEEP_DISABLE()           (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN)
+#define __HAL_RCC_C1_LPTIM5_CLK_SLEEP_DISABLE()           (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN)
+#define __HAL_RCC_C1_COMP12_CLK_SLEEP_DISABLE()           (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN)
+#define __HAL_RCC_C1_VREF_CLK_SLEEP_DISABLE()             (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN)
+#define __HAL_RCC_C1_SAI4_CLK_SLEEP_DISABLE()             (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN)
+#define __HAL_RCC_C1_RTC_CLK_SLEEP_DISABLE()              (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN)
+
+/** @brief  Enable or disable the RCC_C2 AHB3 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+
+
+#define __HAL_RCC_C2_MDMA_CLK_SLEEP_ENABLE()            (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN))
+#define __HAL_RCC_C2_DMA2D_CLK_SLEEP_ENABLE()           (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN))
+#define __HAL_RCC_C2_JPGDEC_CLK_SLEEP_ENABLE()          (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN))
+#define __HAL_RCC_C2_FLASH_CLK_SLEEP_ENABLE()           (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN))
+#define __HAL_RCC_C2_FMC_CLK_SLEEP_ENABLE()             (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
+#define __HAL_RCC_C2_QSPI_CLK_SLEEP_ENABLE()            (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
+#define __HAL_RCC_C2_SDMMC1_CLK_SLEEP_ENABLE()          (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN))
+#define __HAL_RCC_C2_DTCM1_CLK_SLEEP_ENABLE()           (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN))
+#define __HAL_RCC_C2_DTCM2_CLK_SLEEP_ENABLE()           (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN))
+#define __HAL_RCC_C2_ITCM_CLK_SLEEP_ENABLE()            (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN))
+#define __HAL_RCC_C2_D1SRAM1_CLK_SLEEP_ENABLE()         (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN))
+
+
+#define __HAL_RCC_C2_MDMA_CLK_SLEEP_DISABLE()            (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN))
+#define __HAL_RCC_C2_DMA2D_CLK_SLEEP_DISABLE()           (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN))
+#define __HAL_RCC_C2_JPGDEC_CLK_SLEEP_DISABLE()          (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN))
+#define __HAL_RCC_C2_FLASH_CLK_SLEEP_DISABLE()           (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN))
+#define __HAL_RCC_C2_FMC_CLK_SLEEP_DISABLE()             (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN))
+#define __HAL_RCC_C2_QSPI_CLK_SLEEP_DISABLE()            (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN))
+#define __HAL_RCC_C2_SDMMC1_CLK_SLEEP_DISABLE()          (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN))
+#define __HAL_RCC_C2_DTCM1_CLK_SLEEP_DISABLE()           (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN))
+#define __HAL_RCC_C2_DTCM2_CLK_SLEEP_DISABLE()           (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN))
+#define __HAL_RCC_C2_ITCM_CLK_SLEEP_DISABLE()            (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN))
+#define __HAL_RCC_C2_D1SRAM1_CLK_SLEEP_DISABLE()         (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN))
+
+
+
+/** @brief  ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C2_DMA1_CLK_SLEEP_ENABLE()             (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
+#define __HAL_RCC_C2_DMA2_CLK_SLEEP_ENABLE()             (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
+#define __HAL_RCC_C2_ADC12_CLK_SLEEP_ENABLE()            (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN))
+#define __HAL_RCC_C2_ETH1MAC_CLK_SLEEP_ENABLE()          (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN))
+#define __HAL_RCC_C2_ETH1TX_CLK_SLEEP_ENABLE()           (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN))
+#define __HAL_RCC_C2_ETH1RX_CLK_SLEEP_ENABLE()           (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN))
+#define __HAL_RCC_C2_USB1_OTG_HS_CLK_SLEEP_ENABLE()      (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN))
+#define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
+#define __HAL_RCC_C2_USB2_OTG_FS_CLK_SLEEP_ENABLE()      (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN))
+#define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
+
+#define __HAL_RCC_C2_DMA1_CLK_SLEEP_DISABLE()             (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN))
+#define __HAL_RCC_C2_DMA2_CLK_SLEEP_DISABLE()             (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN))
+#define __HAL_RCC_C2_ADC12_CLK_SLEEP_DISABLE()            (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN))
+#define __HAL_RCC_C2_ETH1MAC_CLK_SLEEP_DISABLE()          (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN))
+#define __HAL_RCC_C2_ETH1TX_CLK_SLEEP_DISABLE()           (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN))
+#define __HAL_RCC_C2_ETH1RX_CLK_SLEEP_DISABLE()           (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN))
+#define __HAL_RCC_C2_USB1_OTG_HS_CLK_SLEEP_DISABLE()      (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN))
+#define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
+#define __HAL_RCC_C2_USB2_OTG_FS_CLK_SLEEP_DISABLE()      (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN))
+#define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
+
+/** @brief  ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C2_DCMI_CLK_SLEEP_ENABLE()             (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
+#if defined(CRYP)
+#define __HAL_RCC_C2_CRYP_CLK_SLEEP_ENABLE()             (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_C2_HASH_CLK_SLEEP_ENABLE()             (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
+#endif /* HASH */
+#define __HAL_RCC_C2_RNG_CLK_SLEEP_ENABLE()              (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
+#define __HAL_RCC_C2_SDMMC2_CLK_SLEEP_ENABLE()           (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))
+#define __HAL_RCC_C2_D2SRAM1_CLK_SLEEP_ENABLE()          (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN))
+#define __HAL_RCC_C2_D2SRAM2_CLK_SLEEP_ENABLE()          (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN))
+#define __HAL_RCC_C2_D2SRAM3_CLK_SLEEP_ENABLE()          (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN))
+
+#define __HAL_RCC_C2_DCMI_CLK_SLEEP_DISABLE()             (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))
+#if defined(CRYP)
+#define __HAL_RCC_C2_CRYP_CLK_SLEEP_DISABLE()             (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_C2_HASH_CLK_SLEEP_DISABLE()             (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))
+#endif /* HASH */
+#define __HAL_RCC_C2_RNG_CLK_SLEEP_DISABLE()              (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))
+#define __HAL_RCC_C2_SDMMC2_CLK_SLEEP_DISABLE()           (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))
+#define __HAL_RCC_C2_D2SRAM1_CLK_SLEEP_DISABLE()          (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN))
+#define __HAL_RCC_C2_D2SRAM2_CLK_SLEEP_DISABLE()          (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN))
+#define __HAL_RCC_C2_D2SRAM3_CLK_SLEEP_DISABLE()          (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN))
+
+/** @brief  ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C2_GPIOA_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN)
+#define __HAL_RCC_C2_GPIOB_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN)
+#define __HAL_RCC_C2_GPIOC_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN)
+#define __HAL_RCC_C2_GPIOD_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN)
+#define __HAL_RCC_C2_GPIOE_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN)
+#define __HAL_RCC_C2_GPIOF_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN)
+#define __HAL_RCC_C2_GPIOG_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN)
+#define __HAL_RCC_C2_GPIOH_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN)
+#define __HAL_RCC_C2_GPIOI_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN)
+#define __HAL_RCC_C2_GPIOJ_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN)
+#define __HAL_RCC_C2_GPIOK_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN)
+#define __HAL_RCC_C2_CRC_CLK_SLEEP_ENABLE()             (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN)
+#define __HAL_RCC_C2_BDMA_CLK_SLEEP_ENABLE()            (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN)
+#define __HAL_RCC_C2_ADC3_CLK_SLEEP_ENABLE()            (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN)
+#define __HAL_RCC_C2_BKPRAM_CLK_SLEEP_ENABLE()          (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN)
+#define __HAL_RCC_C2_D3SRAM1_CLK_SLEEP_ENABLE()         (RCC_C2->AHB4LPENR  |= (RCC_AHB4LPENR_D3SRAM1LPEN))
+
+#define __HAL_RCC_C2_GPIOA_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN)
+#define __HAL_RCC_C2_GPIOB_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN)
+#define __HAL_RCC_C2_GPIOC_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN)
+#define __HAL_RCC_C2_GPIOD_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN)
+#define __HAL_RCC_C2_GPIOE_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN)
+#define __HAL_RCC_C2_GPIOF_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN)
+#define __HAL_RCC_C2_GPIOG_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN)
+#define __HAL_RCC_C2_GPIOH_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN)
+#define __HAL_RCC_C2_GPIOI_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN)
+#define __HAL_RCC_C2_GPIOJ_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN)
+#define __HAL_RCC_C2_GPIOK_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN)
+#define __HAL_RCC_C2_CRC_CLK_SLEEP_DISABLE()             (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN)
+#define __HAL_RCC_C2_BDMA_CLK_SLEEP_DISABLE()            (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN)
+#define __HAL_RCC_C2_ADC3_CLK_SLEEP_DISABLE()            (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN)
+#define __HAL_RCC_C2_BKPRAM_CLK_SLEEP_DISABLE()          (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN)
+#define __HAL_RCC_C2_D3SRAM1_CLK_SLEEP_DISABLE()         (RCC_C2->AHB4LPENR  &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN))
+
+/** @brief  ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C2_LTDC_CLK_SLEEP_ENABLE()           (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN)
+#define __HAL_RCC_C2_DSI_CLK_SLEEP_ENABLE()            (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN)
+#define __HAL_RCC_C2_WWDG1_CLK_SLEEP_ENABLE()          (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN)
+
+#define __HAL_RCC_C2_LTDC_CLK_SLEEP_DISABLE()           (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN)
+#define __HAL_RCC_C2_DSI_CLK_SLEEP_DISABLE()            (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN)
+#define __HAL_RCC_C2_WWDG1_CLK_SLEEP_DISABLE()          (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN)
+
+/** @brief  ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C2_TIM2_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN)
+#define __HAL_RCC_C2_TIM3_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN)
+#define __HAL_RCC_C2_TIM4_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN)
+#define __HAL_RCC_C2_TIM5_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN)
+#define __HAL_RCC_C2_TIM6_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN)
+#define __HAL_RCC_C2_TIM7_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN)
+#define __HAL_RCC_C2_TIM12_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN)
+#define __HAL_RCC_C2_TIM13_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN)
+#define __HAL_RCC_C2_TIM14_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN)
+#define __HAL_RCC_C2_LPTIM1_CLK_SLEEP_ENABLE()         (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN)
+#define __HAL_RCC_C2_WWDG2_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN)
+#define __HAL_RCC_C2_SPI2_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN)
+#define __HAL_RCC_C2_SPI3_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN)
+#define __HAL_RCC_C2_SPDIFRX_CLK_SLEEP_ENABLE()        (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN)
+#define __HAL_RCC_C2_USART2_CLK_SLEEP_ENABLE()         (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN)
+#define __HAL_RCC_C2_USART3_CLK_SLEEP_ENABLE()         (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN)
+#define __HAL_RCC_C2_UART4_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN)
+#define __HAL_RCC_C2_UART5_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN)
+#define __HAL_RCC_C2_I2C1_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN)
+#define __HAL_RCC_C2_I2C2_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN)
+#define __HAL_RCC_C2_I2C3_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN)
+#define __HAL_RCC_C2_CEC_CLK_SLEEP_ENABLE()            (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN)
+#define __HAL_RCC_C2_DAC12_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN)
+#define __HAL_RCC_C2_UART7_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN)
+#define __HAL_RCC_C2_UART8_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN)
+#define __HAL_RCC_C2_CRS_CLK_SLEEP_ENABLE()            (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN)
+#define __HAL_RCC_C2_SWPMI_CLK_SLEEP_ENABLE()          (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN)
+#define __HAL_RCC_C2_OPAMP_CLK_SLEEP_ENABLE()          (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN)
+#define __HAL_RCC_C2_MDIOS_CLK_SLEEP_ENABLE()          (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN)
+#define __HAL_RCC_C2_FDCAN_CLK_SLEEP_ENABLE()          (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN)
+
+
+#define __HAL_RCC_C2_TIM2_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN)
+#define __HAL_RCC_C2_TIM3_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN)
+#define __HAL_RCC_C2_TIM4_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN)
+#define __HAL_RCC_C2_TIM5_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN)
+#define __HAL_RCC_C2_TIM6_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN)
+#define __HAL_RCC_C2_TIM7_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN)
+#define __HAL_RCC_C2_TIM12_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN)
+#define __HAL_RCC_C2_TIM13_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN)
+#define __HAL_RCC_C2_TIM14_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN)
+#define __HAL_RCC_C2_LPTIM1_CLK_SLEEP_DISABLE()         (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN)
+#define __HAL_RCC_C2_WWDG2_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN)
+#define __HAL_RCC_C2_SPI2_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN)
+#define __HAL_RCC_C2_SPI3_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN)
+#define __HAL_RCC_C2_SPDIFRX_CLK_SLEEP_DISABLE()        (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN)
+#define __HAL_RCC_C2_USART2_CLK_SLEEP_DISABLE()         (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN)
+#define __HAL_RCC_C2_USART3_CLK_SLEEP_DISABLE()         (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN)
+#define __HAL_RCC_C2_UART4_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN)
+#define __HAL_RCC_C2_UART5_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN)
+#define __HAL_RCC_C2_I2C1_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN)
+#define __HAL_RCC_C2_I2C2_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN)
+#define __HAL_RCC_C2_I2C3_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN)
+#define __HAL_RCC_C2_CEC_CLK_SLEEP_DISABLE()            (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN)
+#define __HAL_RCC_C2_DAC12_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN)
+#define __HAL_RCC_C2_UART7_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN)
+#define __HAL_RCC_C2_UART8_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN)
+#define __HAL_RCC_C2_CRS_CLK_SLEEP_DISABLE()            (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN)
+#define __HAL_RCC_C2_SWPMI_CLK_SLEEP_DISABLE()          (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN)
+#define __HAL_RCC_C2_OPAMP_CLK_SLEEP_DISABLE()          (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN)
+#define __HAL_RCC_C2_MDIOS_CLK_SLEEP_DISABLE()          (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN)
+#define __HAL_RCC_C2_FDCAN_CLK_SLEEP_DISABLE()          (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN)
+
+/** @brief  ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C2_TIM1_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN)
+#define __HAL_RCC_C2_TIM8_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN)
+#define __HAL_RCC_C2_USART1_CLK_SLEEP_ENABLE()         (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN)
+#define __HAL_RCC_C2_USART6_CLK_SLEEP_ENABLE()         (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN)
+#define __HAL_RCC_C2_SPI1_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN)
+#define __HAL_RCC_C2_SPI4_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN)
+#define __HAL_RCC_C2_TIM15_CLK_SLEEP_ENABLE()          (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN)
+#define __HAL_RCC_C2_TIM16_CLK_SLEEP_ENABLE()          (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN)
+#define __HAL_RCC_C2_TIM17_CLK_SLEEP_ENABLE()          (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN)
+#define __HAL_RCC_C2_SPI5_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN)
+#define __HAL_RCC_C2_SAI1_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN)
+#define __HAL_RCC_C2_SAI2_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN)
+#define __HAL_RCC_C2_SAI3_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN)
+#define __HAL_RCC_C2_DFSDM1_CLK_SLEEP_ENABLE()         (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN)
+#define __HAL_RCC_C2_HRTIM1_CLK_SLEEP_ENABLE()         (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN)
+
+#define __HAL_RCC_C2_TIM1_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN)
+#define __HAL_RCC_C2_TIM8_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN)
+#define __HAL_RCC_C2_USART1_CLK_SLEEP_DISABLE()         (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN)
+#define __HAL_RCC_C2_USART6_CLK_SLEEP_DISABLE()         (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN)
+#define __HAL_RCC_C2_SPI1_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN)
+#define __HAL_RCC_C2_SPI4_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN)
+#define __HAL_RCC_C2_TIM15_CLK_SLEEP_DISABLE()          (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN)
+#define __HAL_RCC_C2_TIM16_CLK_SLEEP_DISABLE()          (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN)
+#define __HAL_RCC_C2_TIM17_CLK_SLEEP_DISABLE()          (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN)
+#define __HAL_RCC_C2_SPI5_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN)
+#define __HAL_RCC_C2_SAI1_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN)
+#define __HAL_RCC_C2_SAI2_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN)
+#define __HAL_RCC_C2_SAI3_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN)
+#define __HAL_RCC_C2_DFSDM1_CLK_SLEEP_DISABLE()         (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN)
+#define __HAL_RCC_C2_HRTIM1_CLK_SLEEP_DISABLE()         (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN)
+
+/** @brief  ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C2_SYSCFG_CLK_SLEEP_ENABLE()           (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN)
+#define __HAL_RCC_C2_LPUART1_CLK_SLEEP_ENABLE()          (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN)
+#define __HAL_RCC_C2_SPI6_CLK_SLEEP_ENABLE()             (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN)
+#define __HAL_RCC_C2_I2C4_CLK_SLEEP_ENABLE()             (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN)
+#define __HAL_RCC_C2_LPTIM2_CLK_SLEEP_ENABLE()           (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN)
+#define __HAL_RCC_C2_LPTIM3_CLK_SLEEP_ENABLE()           (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN)
+#define __HAL_RCC_C2_LPTIM4_CLK_SLEEP_ENABLE()           (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN)
+#define __HAL_RCC_C2_LPTIM5_CLK_SLEEP_ENABLE()           (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN)
+#define __HAL_RCC_C2_COMP12_CLK_SLEEP_ENABLE()           (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN)
+#define __HAL_RCC_C2_VREF_CLK_SLEEP_ENABLE()             (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN)
+#define __HAL_RCC_C2_SAI4_CLK_SLEEP_ENABLE()             (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN)
+#define __HAL_RCC_C2_RTC_CLK_SLEEP_ENABLE()              (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN)
+
+#define __HAL_RCC_C2_SYSCFG_CLK_SLEEP_DISABLE()           (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN)
+#define __HAL_RCC_C2_LPUART1_CLK_SLEEP_DISABLE()          (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN)
+#define __HAL_RCC_C2_SPI6_CLK_SLEEP_DISABLE()             (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN)
+#define __HAL_RCC_C2_I2C4_CLK_SLEEP_DISABLE()             (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN)
+#define __HAL_RCC_C2_LPTIM2_CLK_SLEEP_DISABLE()           (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN)
+#define __HAL_RCC_C2_LPTIM3_CLK_SLEEP_DISABLE()           (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN)
+#define __HAL_RCC_C2_LPTIM4_CLK_SLEEP_DISABLE()           (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN)
+#define __HAL_RCC_C2_LPTIM5_CLK_SLEEP_DISABLE()           (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN)
+#define __HAL_RCC_C2_COMP12_CLK_SLEEP_DISABLE()           (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN)
+#define __HAL_RCC_C2_VREF_CLK_SLEEP_DISABLE()             (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN)
+#define __HAL_RCC_C2_SAI4_CLK_SLEEP_DISABLE()             (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN)
+#define __HAL_RCC_C2_RTC_CLK_SLEEP_DISABLE()              (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN)
+
+#endif /*DUAL_CORE*/
+
+#if defined(DUAL_CORE)
+/** @brief  Enable or disable peripheral bus clock  when D3 domain is in DRUN
+  * @note   After reset (default config), peripheral clock is disabled when both CPUs are in CSTOP
+  */
+#else
+/** @brief  Enable or disable peripheral bus clock  when D3 domain is in DRUN
+  * @note   After reset (default config), peripheral clock is disabled when CPU is in CSTOP
+  */
+#endif /*DUAL_CORE*/
+
+#if defined(RCC_D3AMR_BDMAAMEN)
+#define __HAL_RCC_BDMA_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_BDMAAMEN)
+#endif
+#if defined(RCC_D3AMR_LPUART1AMEN)
+#define __HAL_RCC_LPUART1_CLKAM_ENABLE()          (RCC->D3AMR) |= (RCC_D3AMR_LPUART1AMEN)
+#endif
+#if defined(RCC_D3AMR_SPI6AMEN)
+#define __HAL_RCC_SPI6_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_SPI6AMEN)
+#endif
+#if defined(RCC_D3AMR_I2C4AMEN)
+#define __HAL_RCC_I2C4_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_I2C4AMEN)
+#endif
+#if defined(RCC_D3AMR_LPTIM2AMEN)
+#define __HAL_RCC_LPTIM2_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_LPTIM2AMEN)
+#endif
+#if defined(RCC_D3AMR_LPTIM3AMEN)
+#define __HAL_RCC_LPTIM3_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_LPTIM3AMEN)
+#endif
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_LPTIM4AMEN)
+#endif
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_LPTIM5AMEN)
+#endif
+#if defined(RCC_D3AMR_COMP12AMEN)
+#define __HAL_RCC_COMP12_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_COMP12AMEN)
+#endif
+#if defined(RCC_D3AMR_VREFAMEN)
+#define __HAL_RCC_VREF_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_VREFAMEN)
+#endif
+#if defined(RCC_D3AMR_RTCAMEN)
+#define __HAL_RCC_RTC_CLKAM_ENABLE()              (RCC->D3AMR) |= (RCC_D3AMR_RTCAMEN)
+#endif
+#if defined(RCC_D3AMR_CRCAMEN)
+#define __HAL_RCC_CRC_CLKAM_ENABLE()              (RCC->D3AMR) |= (RCC_D3AMR_CRCAMEN)
+#endif
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_SAI4AMEN)
+#endif
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_ADC3AMEN)
+#endif
+#if defined(RCC_D3AMR_BKPRAMAMEN)
+#define __HAL_RCC_BKPRAM_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_BKPRAMAMEN)
+#endif
+#if defined(RCC_D3AMR_SRAM4AMEN)
+#define __HAL_RCC_D3SRAM1_CLKAM_ENABLE()          (RCC->D3AMR) |= (RCC_D3AMR_SRAM4AMEN)
+#endif
+
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_CLKAM_ENABLE()            (RCC->SRDAMR) |= (RCC_SRDAMR_BDMA2AMEN)
+#endif
+#if defined(RCC_SRDAMR_GPIOAMEN)
+#define __HAL_RCC_GPIO_CLKAM_ENABLE()             (RCC->SRDAMR) |= (RCC_SRDAMR_GPIOAMEN)
+#endif
+#if defined(RCC_SRDAMR_LPUART1AMEN)
+#define __HAL_RCC_LPUART1_CLKAM_ENABLE()          (RCC->SRDAMR) |= (RCC_SRDAMR_LPUART1AMEN)
+#endif
+#if defined(RCC_SRDAMR_SPI6AMEN)
+#define __HAL_RCC_SPI6_CLKAM_ENABLE()             (RCC->SRDAMR) |= (RCC_SRDAMR_SPI6AMEN)
+#endif
+#if defined(RCC_SRDAMR_I2C4AMEN)
+#define __HAL_RCC_I2C4_CLKAM_ENABLE()             (RCC->SRDAMR) |= (RCC_SRDAMR_I2C4AMEN)
+#endif
+#if defined(RCC_SRDAMR_LPTIM2AMEN)
+#define __HAL_RCC_LPTIM2_CLKAM_ENABLE()           (RCC->SRDAMR) |= (RCC_SRDAMR_LPTIM2AMEN)
+#endif
+#if defined(RCC_SRDAMR_LPTIM3AMEN)
+#define __HAL_RCC_LPTIM3_CLKAM_ENABLE()           (RCC->SRDAMR) |= (RCC_SRDAMR_LPTIM3AMEN)
+#endif
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_CLKAM_ENABLE()             (RCC->SRDAMR) |= (RCC_SRDAMR_DAC2AMEN)
+#endif
+#if defined(RCC_SRDAMR_COMP12AMEN)
+#define __HAL_RCC_COMP12_CLKAM_ENABLE()           (RCC->SRDAMR) |= (RCC_SRDAMR_COMP12AMEN)
+#endif
+#if defined(RCC_SRDAMR_VREFAMEN)
+#define __HAL_RCC_VREF_CLKAM_ENABLE()             (RCC->SRDAMR) |= (RCC_SRDAMR_VREFAMEN)
+#endif
+#if defined(RCC_SRDAMR_RTCAMEN)
+#define __HAL_RCC_RTC_CLKAM_ENABLE()              (RCC->SRDAMR) |= (RCC_SRDAMR_RTCAMEN)
+#endif
+#if defined(RCC_SRDAMR_DTSAMEN)
+#define __HAL_RCC_DTS_CLKAM_ENABLE()              (RCC->SRDAMR) |= (RCC_SRDAMR_DTSAMEN)
+#endif
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_CLKAM_ENABLE()           (RCC->SRDAMR) |= (RCC_SRDAMR_DFSDM2AMEN)
+#endif
+#if defined(RCC_SRDAMR_BKPRAMAMEN)
+#define __HAL_RCC_BKPRAM_CLKAM_ENABLE()           (RCC->SRDAMR) |= (RCC_SRDAMR_BKPRAMAMEN)
+#endif
+#if defined(RCC_SRDAMR_SRDSRAMAMEN)
+#define __HAL_RCC_SRDSRAM_CLKAM_ENABLE()          (RCC->SRDAMR) |= (RCC_SRDAMR_SRDSRAMAMEN)
+#endif
+
+#if defined(RCC_D3AMR_BDMAAMEN)
+#define __HAL_RCC_BDMA_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_BDMAAMEN)
+#endif
+#if defined(RCC_D3AMR_LPUART1AMEN)
+#define __HAL_RCC_LPUART1_CLKAM_DISABLE()          (RCC->D3AMR) &= ~ (RCC_D3AMR_LPUART1AMEN)
+#endif
+#if defined(RCC_D3AMR_SPI6AMEN)
+#define __HAL_RCC_SPI6_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_SPI6AMEN)
+#endif
+#if defined(RCC_D3AMR_I2C4AMEN)
+#define __HAL_RCC_I2C4_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_I2C4AMEN)
+#endif
+#if defined(RCC_D3AMR_LPTIM2AMEN)
+#define __HAL_RCC_LPTIM2_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM2AMEN)
+#endif
+#if defined(RCC_D3AMR_LPTIM3AMEN)
+#define __HAL_RCC_LPTIM3_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM3AMEN)
+#endif
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM4AMEN)
+#endif
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM5AMEN)
+#endif
+#if defined(RCC_D3AMR_COMP12AMEN)
+#define __HAL_RCC_COMP12_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_COMP12AMEN)
+#endif
+#if defined(RCC_D3AMR_VREFAMEN)
+#define __HAL_RCC_VREF_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_VREFAMEN)
+#endif
+#if defined(RCC_D3AMR_RTCAMEN)
+#define __HAL_RCC_RTC_CLKAM_DISABLE()              (RCC->D3AMR) &= ~ (RCC_D3AMR_RTCAMEN)
+#endif
+#if defined(RCC_D3AMR_CRCAMEN)
+#define __HAL_RCC_CRC_CLKAM_DISABLE()              (RCC->D3AMR) &= ~ (RCC_D3AMR_CRCAMEN)
+#endif
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_SAI4AMEN)
+#endif
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_ADC3AMEN)
+#endif
+#if defined(RCC_D3AMR_BKPRAMAMEN)
+#define __HAL_RCC_BKPRAM_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_BKPRAMAMEN)
+#endif
+#if defined(RCC_D3AMR_SRAM4AMEN)
+#define __HAL_RCC_D3SRAM1_CLKAM_DISABLE()          (RCC->D3AMR)&= ~ (RCC_D3AMR_SRAM4AMEN)
+#endif
+
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_CLKAM_DISABLE()            (RCC->SRDAMR) &= ~ (RCC_SRDAMR_BDMA2AMEN)
+#endif
+#if defined(RCC_SRDAMR_GPIOAMEN)
+#define __HAL_RCC_GPIO_CLKAM_DISABLE()             (RCC->SRDAMR) &= ~ (RCC_SRDAMR_GPIOAMEN)
+#endif
+#if defined(RCC_SRDAMR_LPUART1AMEN)
+#define __HAL_RCC_LPUART1_CLKAM_DISABLE()          (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPUART1AMEN)
+#endif
+#if defined(RCC_SRDAMR_SPI6AMEN)
+#define __HAL_RCC_SPI6_CLKAM_DISABLE()             (RCC->SRDAMR) &= ~ (RCC_SRDAMR_SPI6AMEN)
+#endif
+#if defined(RCC_SRDAMR_I2C4AMEN)
+#define __HAL_RCC_I2C4_CLKAM_DISABLE()             (RCC->SRDAMR) &= ~ (RCC_SRDAMR_I2C4AMEN)
+#endif
+#if defined(RCC_SRDAMR_LPTIM2AMEN)
+#define __HAL_RCC_LPTIM2_CLKAM_DISABLE()           (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPTIM2AMEN)
+#endif
+#if defined(RCC_SRDAMR_LPTIM3AMEN)
+#define __HAL_RCC_LPTIM3_CLKAM_DISABLE()           (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPTIM3AMEN)
+#endif
+#if defined(RCC_SRDAMR_DAC2AMEN)
+#define __HAL_RCC_DAC2_CLKAM_DISABLE()             (RCC->SRDAMR) &= ~ (RCC_SRDAMR_DAC2AMEN)
+#endif
+#if defined(RCC_SRDAMR_COMP12AMEN)
+#define __HAL_RCC_COMP12_CLKAM_DISABLE()           (RCC->SRDAMR) &= ~ (RCC_SRDAMR_COMP12AMEN)
+#endif
+#if defined(RCC_SRDAMR_VREFAMEN)
+#define __HAL_RCC_VREF_CLKAM_DISABLE()             (RCC->SRDAMR) &= ~ (RCC_SRDAMR_VREFAMEN)
+#endif
+#if defined(RCC_SRDAMR_RTCAMEN)
+#define __HAL_RCC_RTC_CLKAM_DISABLE()              (RCC->SRDAMR) &= ~(RCC_SRDAMR_RTCAMEN)
+#endif
+#if defined(RCC_SRDAMR_DTSAMEN)
+#define __HAL_RCC_DTS_CLKAM_DISABLE()              (RCC->SRDAMR) &= ~(RCC_SRDAMR_DTSAMEN)
+#endif
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_CLKAM_DISABLE()           (RCC->SRDAMR) &= ~(RCC_SRDAMR_DFSDM2AMEN)
+#endif
+#if defined(RCC_SRDAMR_BKPRAMAMEN)
+#define __HAL_RCC_BKPRAM_CLKAM_DISABLE()           (RCC->SRDAMR) &= ~ (RCC_SRDAMR_BKPRAMAMEN)
+#endif
+#if defined(RCC_SRDAMR_SRDSRAMAMEN)
+#define __HAL_RCC_SRDSRAM_CLKAM_DISABLE()          (RCC->SRDAMR) &= ~ (RCC_SRDAMR_SRDSRAMAMEN)
+#endif
+
+
+#if defined(RCC_CKGAENR_AXICKG)
+    /** @brief  Macro to enable or disable the RCC_CKGAENR bits (AXI clocks gating enable register).
+  * @note
+  * @note
+  * @note
+  * @param
+  * @note
+  */
+
+#define __HAL_RCC_AXI_CLKGA_ENABLE()             (RCC->CKGAENR) |= (RCC_CKGAENR_AXICKG)
+#define __HAL_RCC_AHB_CLKGA_ENABLE()             (RCC->CKGAENR) |= (RCC_CKGAENR_AHBCKG)
+#define __HAL_RCC_CPU_CLKGA_ENABLE()             (RCC->CKGAENR) |= (RCC_CKGAENR_CPUCKG)
+#define __HAL_RCC_SDMMC_CLKGA_ENABLE()           (RCC->CKGAENR) |= (RCC_CKGAENR_SDMMCCKG)
+#define __HAL_RCC_MDMA_CLKGA_ENABLE()            (RCC->CKGAENR) |= (RCC_CKGAENR_MDMACKG)
+#define __HAL_RCC_DMA2D_CLKGA_ENABLE()           (RCC->CKGAENR) |= (RCC_CKGAENR_DMA2DCKG)
+#define __HAL_RCC_LTDC_CLKGA_ENABLE()            (RCC->CKGAENR) |= (RCC_CKGAENR_LTDCCKG)
+#define __HAL_RCC_GFXMMUM_CLKGA_ENABLE()         (RCC->CKGAENR) |= (RCC_CKGAENR_GFXMMUMCKG)
+#define __HAL_RCC_AHB12_CLKGA_ENABLE()           (RCC->CKGAENR) |= (RCC_CKGAENR_AHB12CKG)
+#define __HAL_RCC_AHB34_CLKGA_ENABLE()           (RCC->CKGAENR) |= (RCC_CKGAENR_AHB34CKG)
+#define __HAL_RCC_FLIFT_CLKGA_ENABLE()           (RCC->CKGAENR) |= (RCC_CKGAENR_FLIFTCKG)
+#define __HAL_RCC_OCTOSPI2_CLKGA_ENABLE()        (RCC->CKGAENR) |= (RCC_CKGAENR_OCTOSPI2CKG)
+#define __HAL_RCC_FMC_CLKGA_ENABLE()             (RCC->CKGAENR) |= (RCC_CKGAENR_FMCCKG)
+#define __HAL_RCC_OCTOSPI1_CLKGA_ENABLE()        (RCC->CKGAENR) |= (RCC_CKGAENR_OCTOSPI1CKG)
+#define __HAL_RCC_AXIRAM1_CLKGA_ENABLE()         (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM1CKG)
+#define __HAL_RCC_AXIRAM2_CLKGA_ENABLE()         (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM2CKG)
+#define __HAL_RCC_AXIRAM3_CLKGA_ENABLE()         (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM3CKG)
+#define __HAL_RCC_GFXMMUS_CLKGA_ENABLE()         (RCC->CKGAENR) |= (RCC_CKGAENR_GFXMMUSCKG)
+#define __HAL_RCC_ECCRAM_CLKGA_ENABLE()          (RCC->CKGAENR) |= (RCC_CKGAENR_ECCRAMCKG)
+#define __HAL_RCC_EXTI_CLKGA_ENABLE()            (RCC->CKGAENR) |= (RCC_CKGAENR_EXTICKG)
+#define __HAL_RCC_JTAG_CLKGA_ENABLE()            (RCC->CKGAENR) |= (RCC_CKGAENR_JTAGCKG)
+
+
+#define __HAL_RCC_AXI_CLKGA_DISABLE()             (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXICKG)
+#define __HAL_RCC_AHB_CLKGA_DISABLE()             (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHBCKG)
+#define __HAL_RCC_CPU_CLKGA_DISABLE()             (RCC->CKGAENR) &= ~ (RCC_CKGAENR_CPUCKG)
+#define __HAL_RCC_SDMMC_CLKGA_DISABLE()           (RCC->CKGAENR) &= ~ (RCC_CKGAENR_SDMMCCKG)
+#define __HAL_RCC_MDMA_CLKGA_DISABLE()            (RCC->CKGAENR) &= ~ (RCC_CKGAENR_MDMACKG)
+#define __HAL_RCC_DMA2D_CLKGA_DISABLE()           (RCC->CKGAENR) &= ~ (RCC_CKGAENR_DMA2DCKG)
+#define __HAL_RCC_LTDC_CLKGA_DISABLE()            (RCC->CKGAENR) &= ~ (RCC_CKGAENR_LTDCCKG)
+#define __HAL_RCC_GFXMMUM_CLKGA_DISABLE()         (RCC->CKGAENR) &= ~ (RCC_CKGAENR_GFXMMUMCKG)
+#define __HAL_RCC_AHB12_CLKGA_DISABLE()           (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHB12CKG)
+#define __HAL_RCC_AHB34_CLKGA_DISABLE()           (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHB34CKG)
+#define __HAL_RCC_FLIFT_CLKGA_DISABLE()           (RCC->CKGAENR) &= ~ (RCC_CKGAENR_FLIFTCKG)
+#define __HAL_RCC_OCTOSPI2_CLKGA_DISABLE()        (RCC->CKGAENR) &= ~ (RCC_CKGAENR_OCTOSPI2CKG)
+#define __HAL_RCC_FMC_CLKGA_DISABLE()             (RCC->CKGAENR) &= ~ (RCC_CKGAENR_FMCCKG)
+#define __HAL_RCC_OCTOSPI1_CLKGA_DISABLE()        (RCC->CKGAENR) &= ~ (RCC_CKGAENR_OCTOSPI1CKG)
+#define __HAL_RCC_AXIRAM1_CLKGA_DISABLE()         (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM1CKG)
+#define __HAL_RCC_AXIRAM2_CLKGA_DISABLE()         (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM2CKG)
+#define __HAL_RCC_AXIRAM3_CLKGA_DISABLE()         (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM3CKG)
+#define __HAL_RCC_GFXMMUS_CLKGA_DISABLE()         (RCC->CKGAENR) &= ~ (RCC_CKGAENR_GFXMMUSCKG)
+#define __HAL_RCC_ECCRAM_CLKGA_DISABLE()          (RCC->CKGAENR) &= ~ (RCC_CKGAENR_ECCRAMCKG)
+#define __HAL_RCC_EXTI_CLKGA_DISABLE()            (RCC->CKGAENR) &= ~ (RCC_CKGAENR_EXTICKG)
+#define __HAL_RCC_JTAG_CLKGA_DISABLE()            (RCC->CKGAENR) &= ~ (RCC_CKGAENR_JTAGCKG)
+
+#endif /* RCC_CKGAENR_AXICKG */
+
+
+
+
+/** @brief  Macro to enable or disable the Internal High Speed oscillator (HSI).
+  * @note     After enabling the HSI, the application software should wait on
+  *           HSIRDY flag to be set indicating that HSI clock is stable and can
+  *           be used to clock the PLL and/or system clock.
+  * @note     HSI can not be stopped if it is used directly or through the PLL
+  *           as system clock. In this case, you have to select another source
+  *           of the system clock then stop the HSI.
+  * @note     The HSI is stopped by hardware when entering STOP and STANDBY modes.
+  * @param    __STATE__ specifies the new state of the HSI.
+  *           This parameter can be one of the following values:
+  *            @arg RCC_HSI_OFF turn OFF the HSI oscillator
+  *            @arg RCC_HSI_ON turn ON the HSI oscillator
+  *            @arg RCC_HSI_DIV1 turn ON the HSI oscillator and divide it by 1 (default after reset)
+  *            @arg RCC_HSI_DIV2 turn ON the HSI oscillator and divide it by 2
+  *            @arg RCC_HSI_DIV4 turn ON the HSI oscillator and divide it by 4
+  *            @arg RCC_HSI_DIV8 turn ON the HSI oscillator and divide it by 8
+  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
+  *         clock cycles.
+  */
+#define __HAL_RCC_HSI_CONFIG(__STATE__) \
+                  MODIFY_REG(RCC->CR, RCC_CR_HSION | RCC_CR_HSIDIV , (uint32_t)(__STATE__))
+
+
+/** @brief  Macro to get the HSI divider.
+  * @retval The HSI divider. The returned value can be one
+  *         of the following:
+  *            - RCC_CR_HSIDIV_1  HSI oscillator divided by 1 (default after reset)
+  *            - RCC_CR_HSIDIV_2  HSI oscillator divided by 2
+  *            - RCC_CR_HSIDIV_4  HSI oscillator divided by 4
+  *            - RCC_CR_HSIDIV_8  HSI oscillator divided by 8
+  */
+#define __HAL_RCC_GET_HSI_DIVIDER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV)))
+
+/** @brief  Macros to enable or disable the Internal High Speed oscillator (HSI).
+  * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
+  *         It is used (enabled by hardware) as system clock source after start-up
+  *         from Reset, wakeup from STOP and STANDBY mode, or in case of failure
+  *         of the HSE used directly or indirectly as system clock (if the Clock
+  *         Security System CSS is enabled).
+  * @note   HSI can not be stopped if it is used as system clock source. In this case,
+  *         you have to select another source of the system clock then stop the HSI.
+  * @note   After enabling the HSI, the application software should wait on HSIRDY
+  *         flag to be set indicating that HSI clock is stable and can be used as
+  *         system clock source.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
+  *         clock cycles.
+  */
+#define __HAL_RCC_HSI_ENABLE()  SET_BIT(RCC->CR, RCC_CR_HSION)
+#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
+
+
+/** @brief  Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
+  * @note   The calibration is used to compensate for the variations in voltage
+  *         and temperature that influence the frequency of the internal HSI RC.
+  * @param  __HSICalibrationValue__: specifies the calibration trimming value.
+  *         This parameter must be a number between 0 and 0x7F (3F for Rev Y device).
+  */
+#if defined(RCC_VER_X)
+#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__)                                                                   \
+           do {                                                                                                                          \
+              if(HAL_GetREVID() <= REV_ID_Y)                                                                                             \
+             {                                                                                                                           \
+               MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk, (uint32_t)(__HSICalibrationValue__) << HAL_RCC_REV_Y_HSITRIM_Pos);    \
+             }                                                                                                                           \
+             else                                                                                                                        \
+             {                                                                                                                           \
+               MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_HSICFGR_HSITRIM_Pos);            \
+             }                                                                                                                           \
+           } while(0)
+
+#else
+#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__)                                                                   \
+               MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_HSICFGR_HSITRIM_Pos);
+#endif /*RCC_VER_X*/
+/**
+  * @brief    Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
+  *           in STOP mode to be quickly available as kernel clock for some peripherals.
+  * @note     Keeping the HSI ON in STOP mode allows to avoid slowing down the communication
+  *           speed because of the HSI start-up time.
+  * @note     The enable of this function has not effect on the HSION bit.
+  *           This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+#define __HAL_RCC_HSISTOP_ENABLE()     SET_BIT(RCC->CR, RCC_CR_HSIKERON)
+#define __HAL_RCC_HSISTOP_DISABLE()    CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
+
+
+/**
+  * @brief  Macro to enable or disable the Internal High Speed oscillator for USB (HSI48).
+  * @note   After enabling the HSI48, the application software should wait on
+  *         HSI48RDY flag to be set indicating that HSI48 clock is stable and can
+  *         be used to clock the USB.
+  * @note   The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
+  */
+#define __HAL_RCC_HSI48_ENABLE()    SET_BIT(RCC->CR, RCC_CR_HSI48ON);
+
+#define __HAL_RCC_HSI48_DISABLE()   CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON);
+
+/**
+  * @brief  Macros to enable or disable the Internal  oscillator (CSI).
+  * @note     The CSI is stopped by hardware when entering STOP and STANDBY modes.
+  *           It is used (enabled by hardware) as system clock source after
+  *           start-up from Reset, wakeup from STOP and STANDBY mode, or in case
+  *           of failure of the HSE used directly or indirectly as system clock
+  *           (if the Clock Security System CSS is enabled).
+  * @note     CSI can not be stopped if it is used as system clock source.
+  *           In this case, you have to select another source of the system
+  *           clock then stop the CSI.
+  * @note     After enabling the CSI, the application software should wait on
+  *           CSIRDY flag to be set indicating that CSI clock is stable and can
+  *           be used as system clock source.
+  * @note     When the CSI is stopped, CSIRDY flag goes low after 6 CSI oscillator
+  *           clock cycles.
+  */
+#define __HAL_RCC_CSI_ENABLE()  SET_BIT(RCC->CR, RCC_CR_CSION)
+#define __HAL_RCC_CSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSION)
+
+/** @brief  Macro Adjusts the Internal  oscillator (CSI) calibration value.
+  * @note   The calibration is used to compensate for the variations in voltage
+  *         and temperature that influence the frequency of the internal CSI RC.
+  * @param  __CSICalibrationValue__: specifies the calibration trimming value.
+  *         This parameter must be a number between 0 and 0x1F.
+  */
+#if defined(RCC_VER_X)
+#define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__)                                                                   \
+           do {                                                                                                                          \
+             if(HAL_GetREVID() <= REV_ID_Y)                                                                                              \
+             {                                                                                                                           \
+               MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk, (uint32_t)(__CSICalibrationValue__) << HAL_RCC_REV_Y_CSITRIM_Pos);    \
+             }                                                                                                                           \
+             else                                                                                                                        \
+             {                                                                                                                           \
+               MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, (uint32_t)(__CSICalibrationValue__) << RCC_CSICFGR_CSITRIM_Pos);            \
+             }                                                                                                                           \
+           } while(0)
+
+#else
+#define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__)                                                                   \
+           do {                                                                                                                          \
+               MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, (uint32_t)(__CSICalibrationValue__) << RCC_CSICFGR_CSITRIM_Pos);            \
+               } while(0)
+
+#endif /*RCC_VER_X*/
+/**
+  * @brief    Macros to enable or disable the force of the Low-power Internal oscillator (CSI)
+  *           in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
+  * @note     Keeping the CSI ON in STOP mode allows to avoid slowing down the communication
+  *           speed because of the CSI start-up time.
+  * @note     The enable of this function has not effect on the CSION bit.
+  *           This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+#define __HAL_RCC_CSISTOP_ENABLE()     SET_BIT(RCC->CR, RCC_CR_CSIKERON)
+#define __HAL_RCC_CSISTOP_DISABLE()    CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON)
+
+
+/** @brief  Macros to enable or disable the Internal Low Speed oscillator (LSI).
+  * @note   After enabling the LSI, the application software should wait on
+  *         LSIRDY flag to be set indicating that LSI clock is stable and can
+  *         be used to clock the IWDG and/or the RTC.
+  * @note   LSI can not be disabled if the IWDG is running.
+  * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
+  *         clock cycles.
+  */
+#define __HAL_RCC_LSI_ENABLE()         SET_BIT(RCC->CSR, RCC_CSR_LSION)
+#define __HAL_RCC_LSI_DISABLE()        CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
+
+/**
+  * @brief  Macro to configure the External High Speed oscillator (__HSE__).
+  * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
+  *         software should wait on HSERDY flag to be set indicating that HSE clock
+  *         is stable and can be used to clock the PLL and/or system clock.
+  * @note   HSE state can not be changed if it is used directly or through the
+  *         PLL as system clock. In this case, you have to select another source
+  *         of the system clock then change the HSE state (ex. disable it).
+  * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
+  * @note   This function reset the CSSON bit, so if the clock security system(CSS)
+  *         was previously enabled you have to enable it again after calling this
+  *         function.
+  * @param  __STATE__: specifies the new state of the HSE.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
+  *                              6 HSE oscillator clock cycles.
+  *            @arg RCC_HSE_ON: turn ON the HSE oscillator.
+  *            @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
+  */
+#if defined(RCC_CR_HSEEXT)
+#define __HAL_RCC_HSE_CONFIG(__STATE__)                                \
+                    do {                                               \
+                      if ((__STATE__) == RCC_HSE_ON)                   \
+                      {                                                \
+                        SET_BIT(RCC->CR, RCC_CR_HSEON);                \
+                      }                                                \
+                      else if ((__STATE__) == RCC_HSE_OFF)             \
+                      {                                                \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);              \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT);             \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);             \
+                      }                                                \
+                      else if ((__STATE__) == RCC_HSE_BYPASS)          \
+                      {                                                \
+                        SET_BIT(RCC->CR, RCC_CR_HSEBYP);               \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT);             \
+                        SET_BIT(RCC->CR, RCC_CR_HSEON);                \
+                      }                                                \
+                      else if((__STATE__) == RCC_HSE_BYPASS_DIGITAL)   \
+                      {                                                \
+                        SET_BIT(RCC->CR, RCC_CR_HSEBYP);               \
+                        SET_BIT(RCC->CR, RCC_CR_HSEEXT);               \
+                        SET_BIT(RCC->CR, RCC_CR_HSEON);                \
+                      }                                                \
+                      else                                             \
+                      {                                                \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);              \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);             \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT);             \
+                      }                                                \
+                    } while(0)
+#else
+#define __HAL_RCC_HSE_CONFIG(__STATE__)                         \
+                    do {                                        \
+                      if ((__STATE__) == RCC_HSE_ON)            \
+                      {                                         \
+                        SET_BIT(RCC->CR, RCC_CR_HSEON);         \
+                      }                                         \
+                      else if ((__STATE__) == RCC_HSE_OFF)      \
+                      {                                         \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);       \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);      \
+                      }                                         \
+                      else if ((__STATE__) == RCC_HSE_BYPASS)   \
+                      {                                         \
+                        SET_BIT(RCC->CR, RCC_CR_HSEBYP);        \
+                        SET_BIT(RCC->CR, RCC_CR_HSEON);         \
+                      }                                         \
+                      else                                      \
+                      {                                         \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);       \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);      \
+                      }                                         \
+                    } while(0)
+#endif /* RCC_CR_HSEEXT */
+
+/** @defgroup RCC_LSE_Configuration LSE Configuration
+  * @{
+  */
+
+/**
+  * @brief  Macro to configure the External Low Speed oscillator (LSE).
+  * @note   Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
+  *         User should request a transition to LSE Off first and then LSE On or LSE Bypass.
+  * @note   The external input clock can have a frequency up to 1 MHz and be low swing (analog) or digital(*).
+            A duty cycle close to 50% is recommended.
+  * @note   As the LSE is in the Backup domain and write access is denied to
+  *         this domain after reset, you have to enable write access using
+  *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE
+  *         (to be done once after reset).
+  * @note   After enabling the LSE (RCC_LSE_ON, RCC_LSE_BYPASS or RCC_LSE_BYPASS_DIGITAL*), the application
+  *         software should wait on LSERDY flag to be set indicating that LSE clock
+  *         is stable and can be used to clock the RTC.
+  * @note   If the RTC is used, the LSE bypass must not be configured in digital mode but in low swing analog mode (*)
+  * @param  __STATE__: specifies the new state of the LSE.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
+  *                              6 LSE oscillator clock cycles.
+  *            @arg RCC_LSE_ON: turn ON the LSE oscillator.
+  *            @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
+  *            @arg RCC_LSE_BYPASS_DIGITAL: LSE oscillator bypassed with external digital clock. (*)
+  *
+  *         (*) Available on some STM32H7 lines only.
+  */
+#if defined(RCC_BDCR_LSEEXT)
+#define __HAL_RCC_LSE_CONFIG(__STATE__) \
+                    do {                                               \
+                      if((__STATE__) == RCC_LSE_ON)                    \
+                      {                                                \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);            \
+                      }                                                \
+                      else if((__STATE__) == RCC_LSE_OFF)              \
+                      {                                                \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);          \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);         \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);         \
+                      }                                                \
+                      else if((__STATE__) == RCC_LSE_BYPASS)           \
+                      {                                                \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);           \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);         \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);            \
+                      }                                                \
+                      else if((__STATE__) == RCC_LSE_BYPASS_DIGITAL)   \
+                      {                                                \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);           \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);           \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);            \
+                      }                                                \
+                      else                                             \
+                      {                                                \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);          \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);         \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);         \
+                      }                                                \
+                    } while(0)
+#else
+
+#define __HAL_RCC_LSE_CONFIG(__STATE__) \
+                    do {                                       \
+                      if((__STATE__) == RCC_LSE_ON)            \
+                      {                                        \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \
+                      }                                        \
+                      else if((__STATE__) == RCC_LSE_OFF)      \
+                      {                                        \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);  \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
+                      }                                        \
+                      else if((__STATE__) == RCC_LSE_BYPASS)   \
+                      {                                        \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);   \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \
+                      }                                        \
+                      else                                     \
+                      {                                        \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);  \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
+                      }                                        \
+                    } while(0)
+
+#endif /* RCC_BDCR_LSEEXT */
+/**
+  * @}
+  */
+
+/** @brief  Macros to enable or disable the the RTC clock.
+  * @note   These macros must be used only after the RTC clock source was selected.
+  */
+#define __HAL_RCC_RTC_ENABLE()         SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
+#define __HAL_RCC_RTC_DISABLE()        CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
+
+/** @brief  Macros to configure the RTC clock (RTCCLK).
+  * @note   As the RTC clock configuration bits are in the Backup domain and write
+  *         access is denied to this domain after reset, you have to enable write
+  *         access using the Power Backup Access macro before to configure
+  *         the RTC clock source (to be done once after reset).
+  * @note   Once the RTC clock is configured it can't be changed unless the
+  *         Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
+  *         a Power On Reset (POR).
+  * @param  __RTCCLKSource__: specifies the RTC clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
+  *            @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
+  *            @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
+  *                                            as RTC clock, where x:[2,31]
+  * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
+  *         work in STOP and STANDBY modes, and can be used as wakeup source.
+  *         However, when the HSE clock is used as RTC clock source, the RTC
+  *         cannot be used in STOP and STANDBY modes.
+  * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as
+  *         RTC clock source).
+  */
+#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ?    \
+                                                 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, (((__RTCCLKSource__) & 0xFFFFCFFU) >> 4)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
+
+#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__);    \
+                                                    RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU);  \
+                                                   } while (0)
+
+#define  __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
+
+
+/** @brief  Macros to force or release the Backup domain reset.
+  * @note   This function resets the RTC peripheral (including the backup registers)
+  *         and the RTC clock source selection in RCC_BDCR register.
+  * @note   The BKPSRAM is not affected by this reset.
+  */
+#define __HAL_RCC_BACKUPRESET_FORCE()   SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
+#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
+
+/** @brief  Macros to enable or disable the main PLL.
+  * @note   After enabling the main PLL, the application software should wait on
+  *         PLLRDY flag to be set indicating that PLL clock is stable and can
+  *         be used as system clock source.
+  * @note   The main PLL can not be disabled if it is used as system clock source
+  * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.
+  */
+#define __HAL_RCC_PLL_ENABLE()         SET_BIT(RCC->CR, RCC_CR_PLL1ON)
+#define __HAL_RCC_PLL_DISABLE()        CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON)
+
+/**
+  * @brief  Enables or disables each clock output (PLL_P_CLK, PLL_Q_CLK, PLL_R_CLK)
+  * @note   Enabling/disabling  those Clocks can be done only when the PLL is disabled.
+  *         This is mainly used to save Power.
+  *        (The ck_pll_p of the System PLL cannot be stopped if used as System Clock).
+  * @param  __RCC_PLL1ClockOut__: specifies the PLL clock to be outputted
+  *          This parameter can be one of the following values:
+  *            @arg RCC_PLL1_DIVP: This clock is used to generate system clock up to 400MHZ or 280MHZ(*)
+  *            @arg RCC_PLL1_DIVQ: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
+  *            @arg RCC_PLL1_DIVR: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
+  *
+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  *
+  * @retval None
+  */
+#define __HAL_RCC_PLLCLKOUT_ENABLE(__RCC_PLL1ClockOut__)   SET_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__))
+
+#define __HAL_RCC_PLLCLKOUT_DISABLE(__RCC_PLL1ClockOut__)  CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__))
+
+
+/**
+  * @brief  Enables or disables Fractional Part Of The Multiplication Factor of PLL1 VCO
+  * @note   Enabling/disabling  Fractional Part can be any time  without the need to stop the PLL1
+  * @retval None
+  */
+#define __HAL_RCC_PLLFRACN_ENABLE()   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN)
+
+#define __HAL_RCC_PLLFRACN_DISABLE()  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN)
+
+
+/**
+  * @brief  Macro to configures the main PLL clock source, multiplication and division factors.
+  * @note   This function must be used only when the main PLL is disabled.
+  *
+  * @param  __RCC_PLLSOURCE__: specifies the PLL entry clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_PLLSOURCE_CSI: CSI oscillator clock selected as PLL clock entry
+  *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
+  *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
+  * @note   This clock source (__RCC_PLLSource__) is common for the main PLL1 (main PLL) and PLL2 & PLL3 .
+  *
+  * @param  __PLLM1__: specifies the division factor for PLL VCO input clock
+  *          This parameter must be a number between 1 and 63.
+  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
+  *         frequency ranges from 1 to 16 MHz.
+  *
+  * @param  __PLLN1__: specifies the multiplication factor for PLL VCO output clock
+  *          This parameter must be a number between 4 and 512 or between 8 and 420(*).
+  * @note   You have to set the PLLN parameter correctly to ensure that the VCO
+  *         output frequency is between 150 and 420 MHz (when in medium VCO range) or
+  *         between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range)
+  *
+  * @param  __PLLP1__: specifies the division factor for system  clock.
+  *          This parameter must be a number between 2 and 128 (where odd numbers are not allowed)
+  *
+  * @param  __PLLQ1__: specifies the division factor for peripheral kernel clocks
+  *          This parameter must be a number between 1 and 128
+  *
+  * @param  __PLLR1__: specifies the division factor for peripheral kernel clocks
+  *          This parameter must be a number between 1 and 128
+  *
+  * @note   To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR)
+  *         is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible 
+  *         value to  __PLL1P__, __PLL1Q__ or __PLL1R__ parameters.
+  * @retval None
+  *
+  *  (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  */
+
+
+#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLM1__, __PLLN1__, __PLLP1__, __PLLQ1__,__PLLR1__ ) \
+                  do{ MODIFY_REG(RCC->PLLCKSELR, (RCC_PLLCKSELR_PLLSRC | RCC_PLLCKSELR_DIVM1) , ((__RCC_PLLSOURCE__) | ( (__PLLM1__) <<4U)));  \
+                      WRITE_REG (RCC->PLL1DIVR , ( (((__PLLN1__) - 1U )& RCC_PLL1DIVR_N1) | ((((__PLLP1__) -1U ) << 9U) & RCC_PLL1DIVR_P1) | \
+                                ((((__PLLQ1__) -1U) << 16U)& RCC_PLL1DIVR_Q1) | ((((__PLLR1__) - 1U) << 24U)& RCC_PLL1DIVR_R1))); \
+                    } while(0)
+
+
+/** @brief  Macro to configure the PLLs clock source.
+  * @note   This function must be used only when all PLLs are disabled.
+  * @param  __PLLSOURCE__: specifies the PLLs entry clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PLLSOURCE_CSI: CSI oscillator clock selected as PLL clock entry
+  *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
+  *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
+  *
+  */
+#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, (__PLLSOURCE__))
+
+
+/**
+  * @brief  Macro to configures the main PLL clock Fractional Part Of The Multiplication Factor
+  *
+  * @note   These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO
+  *
+  * @param  __RCC_PLL1FRACN__: specifies Fractional Part Of The Multiplication Factor for PLL1 VCO
+  *                            It should be a value between 0 and 8191
+  * @note   Warning: The software has to set correctly these bits to insure that the VCO
+  *                  output frequency is between its valid frequency range, which is:
+  *                   192 to 836 MHz or 128 to 560 MHz(*) if PLL1VCOSEL = 0
+  *                   150 to 420 MHz if PLL1VCOSEL = 1.
+  *
+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  *
+  * @retval None
+  */
+ #define  __HAL_RCC_PLLFRACN_CONFIG(__RCC_PLL1FRACN__) MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, (uint32_t)(__RCC_PLL1FRACN__) << RCC_PLL1FRACR_FRACN1_Pos)
+
+
+/** @brief  Macro to select  the PLL1  reference frequency range.
+  * @param  __RCC_PLL1VCIRange__: specifies the PLL1 input frequency range
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PLL1VCIRANGE_0: Range frequency is between 1 and 2 MHz
+  *            @arg RCC_PLL1VCIRANGE_1: Range frequency is between 2 and 4 MHz
+  *            @arg RCC_PLL1VCIRANGE_2: Range frequency is between 4 and 8 MHz
+  *            @arg RCC_PLL1VCIRANGE_3: Range frequency is between 8 and 16 MHz
+  * @retval None
+  */
+#define __HAL_RCC_PLL_VCIRANGE(__RCC_PLL1VCIRange__) \
+                  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, (__RCC_PLL1VCIRange__))
+
+
+/** @brief  Macro to select  the PLL1  reference frequency range.
+  * @param  __RCC_PLL1VCORange__: specifies the PLL1 input frequency range
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PLL1VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*)
+  *            @arg RCC_PLL1VCOMEDIUM: Range frequency is between 150 and 420 MHz
+  *
+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  *
+  * @retval None
+  */
+#define __HAL_RCC_PLL_VCORANGE(__RCC_PLL1VCORange__) \
+                  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, (__RCC_PLL1VCORange__))
+
+
+
+/** @brief  Macro to get the clock source used as system clock.
+  * @retval The clock source used as system clock. The returned value can be one
+  *         of the following:
+  *              - RCC_CFGR_SWS_CSI: CSI used as system clock.
+  *              - RCC_CFGR_SWS_HSI: HSI used as system clock.
+  *              - RCC_CFGR_SWS_HSE: HSE used as system clock.
+  *              - RCC_CFGR_SWS_PLL: PLL used as system clock.
+  */
+#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
+
+
+/**
+  * @brief Macro to configure the system clock source.
+  * @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
+  * This parameter can be one of the following values:
+  *              - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
+  *              - RCC_SYSCLKSOURCE_CSI: CSI oscillator is used as system clock source.
+  *              - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
+  *              - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
+  */
+#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
+
+/** @brief  Macro to get the oscillator used as PLL clock source.
+  * @retval The oscillator used as PLL clock source. The returned value can be one
+  *         of the following:
+  *              - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.
+  *              - RCC_PLLSOURCE_CSI: CSI oscillator is used as PLL clock source.
+  *              - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
+  *              - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
+  */
+#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC))
+
+/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
+  * @{
+  */
+
+/** @brief  Macro to configure the MCO1 clock.
+  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_PLL1QCLK:  PLL1Q clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_HSI48: HSI48 (48MHZ) selected as MCO1 source
+  * @param  __MCODIV__ specifies the MCO clock prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCODIV_1 up to RCC_MCODIV_15  : divider applied to MCO1 clock
+  */
+#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
+                 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
+
+/** @brief  Macro to configure the MCO2 clock.
+  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_PLL2PCLK: PLL2P clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_PLLCLK:  PLL1P clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_CSICLK:  CSI clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_LSICLK:  LSI clock selected as MCO2 source
+  * @param  __MCODIV__ specifies the MCO clock prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCODIV_1 up to RCC_MCODIV_15  : divider applied to MCO2 clock
+  */
+#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
+    MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 7)));
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Macro to configure the External Low Speed oscillator (LSE) drive capability.
+  * @note   As the LSE is in the Backup domain and write access is denied to
+  *         this domain after reset, you have to enable write access using
+  *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE
+  *         (to be done once after reset).
+  * @note   On STM32H7 Rev.B and above devices this can't be updated while LSE is ON.
+  * @param  __LSEDRIVE__: specifies the new state of the LSE drive capability.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.
+  *            @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.
+  *            @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.
+  *            @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.
+  * @retval None
+  */
+#if defined(RCC_VER_X)
+#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
+           do{                                                                                                                                \
+             if((HAL_GetREVID() <= REV_ID_Y) && (((__LSEDRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || ((__LSEDRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH)))  \
+             {                                                                                                                                \
+              MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (~(uint32_t)(__LSEDRIVE__)) & RCC_BDCR_LSEDRV_Msk);                                      \
+             }                                                                                                                                \
+             else                                                                                                                             \
+             {                                                                                                                                \
+               MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__));                                                              \
+             }                                                                                                                                \
+           } while(0)
+#else
+#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
+               MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__));
+#endif /*RCC_VER_X*/
+/**
+  * @brief  Macro to configure the wake up from stop clock.
+  * @param  __RCC_STOPWUCLK__: specifies the clock source used after wake up from stop
+  *         This parameter can be one of the following values:
+  *            @arg RCC_STOP_WAKEUPCLOCK_CSI: CSI selected as system clock source
+  *            @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI selected as system clock source
+  * @retval None
+  */
+#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) \
+                  MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__RCC_STOPWUCLK__))
+
+/**
+  * @brief  Macro to configure the Kernel wake up from stop clock.
+  * @param  __RCC_STOPKERWUCLK__: specifies the Kernel clock source used after wake up from stop
+  *         This parameter can be one of the following values:
+  *            @arg RCC_STOP_KERWAKEUPCLOCK_CSI: CSI selected as Kernel clock source
+  *            @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI selected as Kernel clock source
+  * @retval None
+  */
+#define __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(__RCC_STOPKERWUCLK__) \
+                  MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, (__RCC_STOPKERWUCLK__))
+
+/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
+  * @brief macros to manage the specified RCC Flags and interrupts.
+  * @{
+  */
+/** @brief  Enable RCC interrupt.
+  * @param  __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
+  *         This parameter can be any combination of the following values:
+  *            @arg RCC_IT_LSIRDY: LSI ready interrupt
+  *            @arg RCC_IT_LSERDY: LSE ready interrupt
+  *            @arg RCC_IT_CSIRDY: HSI ready interrupt
+  *            @arg RCC_IT_HSIRDY: HSI ready interrupt
+  *            @arg RCC_IT_HSERDY: HSE ready interrupt
+  *            @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
+  *            @arg RCC_IT_PLLRDY: main PLL ready interrupt
+  *            @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
+  *            @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
+  *            @arg RCC_IT_LSECSS: Clock security system interrupt
+  */
+#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
+
+/** @brief Disable RCC interrupt
+  * @param  __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
+  *         This parameter can be any combination of the following values:
+  *            @arg RCC_IT_LSIRDY: LSI ready interrupt
+  *            @arg RCC_IT_LSERDY: LSE ready interrupt
+  *            @arg RCC_IT_CSIRDY: HSI ready interrupt
+  *            @arg RCC_IT_HSIRDY: HSI ready interrupt
+  *            @arg RCC_IT_HSERDY: HSE ready interrupt
+  *            @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
+  *            @arg RCC_IT_PLLRDY: main PLL ready interrupt
+  *            @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
+  *            @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
+  *            @arg RCC_IT_LSECSS: Clock security system interrupt
+  */
+#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
+
+/** @brief  Clear the RCC's interrupt pending bits
+  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
+  *         This parameter can be any combination of the following values:
+  *            @arg RCC_IT_LSIRDY: LSI ready interrupt
+  *            @arg RCC_IT_LSERDY: LSE ready interrupt
+  *            @arg RCC_IT_CSIRDY: CSI ready interrupt
+  *            @arg RCC_IT_HSIRDY: HSI ready interrupt
+  *            @arg RCC_IT_HSERDY: HSE ready interrupt
+  *            @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
+  *            @arg RCC_IT_PLLRDY: main PLL ready interrupt
+  *            @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
+  *            @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
+  *            @arg RCC_IT_HSECSS: HSE Clock Security interrupt
+  *            @arg RCC_IT_LSECSS: Clock security system interrupt
+  */
+#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
+
+/** @brief  Check the RCC's interrupt has occurred or not.
+  * @param  __INTERRUPT__: specifies the RCC interrupt source to check.
+  *         This parameter can be any combination of the following values:
+  *            @arg RCC_IT_LSIRDY: LSI ready interrupt
+  *            @arg RCC_IT_LSERDY: LSE ready interrupt
+  *            @arg RCC_IT_CSIRDY: CSI ready interrupt
+  *            @arg RCC_IT_HSIRDY: HSI ready interrupt
+  *            @arg RCC_IT_HSERDY: HSE ready interrupt
+  *            @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
+  *            @arg RCC_IT_PLLRDY: main PLL ready interrupt
+  *            @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
+  *            @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
+  *            @arg RCC_IT_HSECSS: HSE Clock Security interrupt
+  *            @arg RCC_IT_LSECSS: Clock security system interrupt
+  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+  */
+#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/** @brief Set RMVF bit to clear the reset flags.
+  */
+#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->RSR |= RCC_RSR_RMVF)
+
+#if defined(DUAL_CORE)
+#define __HAL_RCC_C1_CLEAR_RESET_FLAGS() (RCC_C1->RSR |= RCC_RSR_RMVF)
+
+#define __HAL_RCC_C2_CLEAR_RESET_FLAGS() (RCC_C2->RSR |= RCC_RSR_RMVF)
+#endif /*DUAL_CORE*/
+
+#if defined(DUAL_CORE)
+/** @brief  Check RCC flag is set or not.
+  * @param  __FLAG__: specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
+  *            @arg RCC_FLAG_HSIDIV: HSI divider flag
+  *            @arg RCC_FLAG_CSIRDY: CSI oscillator clock ready
+  *            @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready
+  *            @arg RCC_FLAG_HSERDY:  HSE oscillator clock ready
+  *            @arg RCC_FLAG_D1CKRDY:  Domain1 clock ready
+  *            @arg RCC_FLAG_D2CKRDY:  Domain2 clock ready
+  *            @arg RCC_FLAG_PLLRDY:  PLL1 clock ready
+  *            @arg RCC_FLAG_PLL2RDY: PLL2 clock ready
+  *            @arg RCC_FLAG_PLL3RDY: PLL3 clock ready
+  *            @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
+  *            @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
+  *            @arg RCC_FLAG_C1RST:  CPU reset flag
+  *            @arg RCC_FLAG_C2RST:  CPU2 reset flag
+  *            @arg RCC_FLAG_D1RST:  D1 domain power switch reset flag
+  *            @arg RCC_FLAG_D2RST:  D2 domain power switch reset flag
+  *            @arg RCC_FLAG_BORRST: BOR reset flag
+  *            @arg RCC_FLAG_PINRST: Pin reset
+  *            @arg RCC_FLAG_PORRST: POR/PDR  reset
+  *            @arg RCC_FLAG_SFTR1ST: System reset from CPU reset flag
+  *            @arg RCC_FLAG_SFTR2ST: System reset from CPU2 reset flag
+  *            @arg RCC_FLAG_BORRST:   D2 domain power switch reset flag
+  *            @arg RCC_FLAG_IWDG1RST: CPU Independent Watchdog reset
+  *            @arg RCC_FLAG_IWDG2RST: CPU2 Independent Watchdog reset
+  *            @arg RCC_FLAG_WWDG2RST: Window Watchdog2 reset
+  *            @arg RCC_FLAG_WWDG1RST: Window Watchdog1 reset
+  *            @arg RCC_FLAG_LPWR1RST: Reset due to illegal D1 DSTANDBY or CPU CSTOP flag
+  *            @arg RCC_FLAG_LPWR2RST: Reset due to illegal D2 DSTANDBY or CPU2 CSTOP flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define RCC_FLAG_MASK  ((uint8_t)0x1F)
+#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
+((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC->RSR :RCC->CIFR))))  & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
+
+#define __HAL_RCC_C1_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
+((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC_C1->RSR :RCC->CIFR))))  & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
+
+#define __HAL_RCC_C2_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
+((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC_C2->RSR :RCC->CIFR))))  & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
+
+#else
+
+/** @brief  Check RCC flag is set or not.
+  * @param  __FLAG__: specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
+  *            @arg RCC_FLAG_HSIDIV: HSI divider flag
+  *            @arg RCC_FLAG_CSIRDY: CSI oscillator clock ready
+  *            @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready
+  *            @arg RCC_FLAG_HSERDY:  HSE oscillator clock ready
+  *            @arg RCC_FLAG_D1CKRDY:  Domain1 clock ready (*)
+  *            @arg RCC_FLAG_D2CKRDY:  Domain2 clock ready (*)
+  *            @arg RCC_FLAG_CPUCKRDY: CPU Domain clock ready (CPU, APB3, bus matrix1 and related memories) (*)
+  *            @arg RCC_FLAG_CDCKRDY:  CPU Domain clock ready (*)
+  *            @arg RCC_FLAG_PLLRDY:  PLL1 clock ready
+  *            @arg RCC_FLAG_PLL2RDY: PLL2 clock ready
+  *            @arg RCC_FLAG_PLL3RDY: PLL3 clock ready
+  *            @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
+  *            @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
+  *            @arg RCC_FLAG_CPURST: CPU reset flag
+  *            @arg RCC_FLAG_D1RST:  D1 domain power switch reset flag (*)
+  *            @arg RCC_FLAG_D2RST:  D2 domain power switch reset flag (*)
+  *            @arg RCC_FLAG_CDRST:  CD domain power switch reset flag (*)
+  *            @arg RCC_FLAG_BORRST: BOR reset flag
+  *            @arg RCC_FLAG_PINRST: Pin reset
+  *            @arg RCC_FLAG_PORRST: POR/PDR  reset
+  *            @arg RCC_FLAG_SFTRST: System reset from CPU reset flag
+  *            @arg RCC_FLAG_BORRST:   D2 domain power switch reset flag
+  *            @arg RCC_FLAG_IWDG1RST: CPU Independent Watchdog reset
+  *            @arg RCC_FLAG_WWDG1RST: Window Watchdog1 reset
+  *            @arg RCC_FLAG_LPWR1RST: Reset due to illegal D1 DSTANDBY or CPU CSTOP flag
+  *            @arg RCC_FLAG_LPWR2RST: Reset due to illegal D2 DSTANDBY flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  *
+  *  (*) Available on some STM32H7 lines only.
+  */
+#define RCC_FLAG_MASK  ((uint8_t)0x1F)
+#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
+((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC->RSR :RCC->CIFR))))  & (1UL << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
+#endif /*DUAL_CORE*/
+
+/**
+  * @}
+  */
+
+#define RCC_GET_PLL_OSCSOURCE() ((RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC) >> RCC_PLLCKSELR_PLLSRC_Pos)
+
+/**
+  * @}
+  */
+
+/* Include RCC HAL Extension module */
+#include "stm32h7xx_hal_rcc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+ /** @addtogroup RCC_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup RCC_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de-initialization functions  ******************************/
+HAL_StatusTypeDef HAL_RCC_DeInit(void);
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
+
+/**
+  * @}
+  */
+
+/** @addtogroup RCC_Exported_Functions_Group2
+  * @{
+  */
+/* Peripheral Control functions  ************************************************/
+void     HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
+void     HAL_RCC_EnableCSS(void);
+void     HAL_RCC_DisableCSS(void);
+uint32_t HAL_RCC_GetSysClockFreq(void);
+uint32_t HAL_RCC_GetHCLKFreq(void);
+uint32_t HAL_RCC_GetPCLK1Freq(void);
+uint32_t HAL_RCC_GetPCLK2Freq(void);
+void     HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
+void     HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
+/* CSS NMI IRQ handler */
+void     HAL_RCC_NMI_IRQHandler(void);
+/* User Callbacks in non blocking mode (IT mode) */
+void     HAL_RCC_CCSCallback(void);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RCC_Private_Constants RCC Private Constants
+  * @{
+  */
+
+#define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT
+#define HSI_TIMEOUT_VALUE          (2U)    /* 2 ms */
+#define HSI48_TIMEOUT_VALUE        (2U)    /* 2 ms */
+#define CSI_TIMEOUT_VALUE          (2U)    /* 2 ms */
+#define LSI_TIMEOUT_VALUE          (2U)    /* 2 ms */
+#define PLL_TIMEOUT_VALUE          (2U)    /* 2 ms */
+#define CLOCKSWITCH_TIMEOUT_VALUE  (5000U) /* 5 s  */
+#define RCC_DBP_TIMEOUT_VALUE      (100U)
+#define RCC_LSE_TIMEOUT_VALUE      LSE_STARTUP_TIMEOUT
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RCC_Private_Macros RCC Private Macros
+  * @{
+  */
+
+/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
+  * @{
+  */
+
+#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE)                           || \
+                                           (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
+                                           (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
+                                           (((OSCILLATOR) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) || \
+                                           (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
+                                           (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \
+                                           (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48))
+
+#if defined(RCC_CR_HSEEXT)
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
+                         ((HSE) == RCC_HSE_BYPASS) || ((HSE) == RCC_HSE_BYPASS_DIGITAL))
+#else
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
+                         ((HSE) == RCC_HSE_BYPASS))
+#endif /* RCC_CR_HSEEXT */
+
+#if defined(RCC_BDCR_LSEEXT)
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
+                         ((LSE) == RCC_LSE_BYPASS) || ((LSE) == RCC_LSE_BYPASS_DIGITAL))
+#else
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
+                         ((LSE) == RCC_LSE_BYPASS))
+#endif /* RCC_BDCR_LSEEXT */
+
+#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON)    || \
+                         ((HSI) == RCC_HSI_DIV1) || ((HSI) == RCC_HSI_DIV2) || \
+                         ((HSI) == RCC_HSI_DIV4) || ((HSI) == RCC_HSI_DIV8))
+
+#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON))
+
+#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
+
+#define IS_RCC_CSI(CSI) (((CSI) == RCC_CSI_OFF) || ((CSI) == RCC_CSI_ON))
+
+#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || \
+                         ((PLL) == RCC_PLL_ON))
+
+#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_CSI)  || \
+                                  ((SOURCE) == RCC_PLLSOURCE_HSI)  || \
+                                  ((SOURCE) == RCC_PLLSOURCE_NONE) || \
+                                  ((SOURCE) == RCC_PLLSOURCE_HSE))
+#define IS_RCC_PLLM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))
+#if !defined(RCC_VER_2_0)
+#define IS_RCC_PLLN_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))
+#else
+#define IS_RCC_PLLN_VALUE(VALUE) ((8U <= (VALUE)) && ((VALUE) <= 420U))
+#endif /* !RCC_VER_2_0 */
+#define IS_RCC_PLLP_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
+#define IS_RCC_PLLQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
+#define IS_RCC_PLLR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
+
+#define IS_RCC_PLLCLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL1_DIVP) || \
+                                         ((VALUE) == RCC_PLL1_DIVQ) || \
+                                         ((VALUE) == RCC_PLL1_DIVR))
+
+#define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 0x3FU))
+
+#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_CSI) || \
+                                     ((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
+                                     ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
+                                     ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
+
+#define IS_RCC_SYSCLK(SYSCLK) (((SYSCLK) == RCC_SYSCLK_DIV1)   || ((SYSCLK) == RCC_SYSCLK_DIV2)   || \
+                               ((SYSCLK) == RCC_SYSCLK_DIV4)   || ((SYSCLK) == RCC_SYSCLK_DIV8)   || \
+                               ((SYSCLK) == RCC_SYSCLK_DIV16)  || ((SYSCLK) == RCC_SYSCLK_DIV64)  || \
+                               ((SYSCLK) == RCC_SYSCLK_DIV128) || ((SYSCLK) == RCC_SYSCLK_DIV256) || \
+                               ((SYSCLK) == RCC_SYSCLK_DIV512))
+
+
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_HCLK_DIV1)   || ((HCLK) == RCC_HCLK_DIV2)   || \
+                           ((HCLK) == RCC_HCLK_DIV4)   || ((HCLK) == RCC_HCLK_DIV8)   || \
+                           ((HCLK) == RCC_HCLK_DIV16)  || ((HCLK) == RCC_HCLK_DIV64)  || \
+                           ((HCLK) == RCC_HCLK_DIV128) || ((HCLK) == RCC_HCLK_DIV256) || \
+                           ((HCLK) == RCC_HCLK_DIV512))
+
+#define IS_RCC_CDPCLK1(CDPCLK1) (((CDPCLK1) == RCC_APB3_DIV1) || ((CDPCLK1) == RCC_APB3_DIV2) || \
+                                 ((CDPCLK1) == RCC_APB3_DIV4) || ((CDPCLK1) == RCC_APB3_DIV8) || \
+                                 ((CDPCLK1) == RCC_APB3_DIV16))
+
+#define IS_RCC_D1PCLK1 IS_RCC_CDPCLK1  /* for legacy compatibility between H7 lines */
+
+#define IS_RCC_PCLK1(PCLK1) (((PCLK1) == RCC_APB1_DIV1) || ((PCLK1) == RCC_APB1_DIV2) || \
+                             ((PCLK1) == RCC_APB1_DIV4) || ((PCLK1) == RCC_APB1_DIV8) || \
+                            ((PCLK1) == RCC_APB1_DIV16))
+
+#define IS_RCC_PCLK2(PCLK2) (((PCLK2) == RCC_APB2_DIV1) || ((PCLK2) == RCC_APB2_DIV2) || \
+                             ((PCLK2) == RCC_APB2_DIV4) || ((PCLK2) == RCC_APB2_DIV8) || \
+                             ((PCLK2) == RCC_APB2_DIV16))
+
+#define IS_RCC_SRDPCLK1(SRDPCLK1) (((SRDPCLK1) == RCC_APB4_DIV1) || ((SRDPCLK1) == RCC_APB4_DIV2) || \
+                                  ((SRDPCLK1) == RCC_APB4_DIV4)  || ((SRDPCLK1) == RCC_APB4_DIV8) || \
+                                  ((SRDPCLK1) == RCC_APB4_DIV16))
+
+#define IS_RCC_D3PCLK1 IS_RCC_SRDPCLK1 /* for legacy compatibility between H7 lines*/
+
+#define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE)       || ((SOURCE) == RCC_RTCCLKSOURCE_LSI)       || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2)  || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3)  || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4)  || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5)  || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6)  || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7)  || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8)  || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9)  || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV33) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV34) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV35) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV36) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV37) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV38) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV39) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV40) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV41) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV42) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV43) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV44) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV45) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV46) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV47) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV48) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV49) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV50) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV51) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV52) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV53) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV54) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV55) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV56) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV57) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV58) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV59) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV60) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV61) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV62) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV63))
+
+#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
+
+#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE)       || \
+                                   ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLL1QCLK)  || \
+                                   ((SOURCE) == RCC_MCO1SOURCE_HSI48))
+
+#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK)    || ((SOURCE) == RCC_MCO2SOURCE_PLL2PCLK) || \
+                                   ((SOURCE) == RCC_MCO2SOURCE_HSE)       || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK)   || \
+                                   ((SOURCE) == RCC_MCO2SOURCE_CSICLK)    || ((SOURCE) == RCC_MCO2SOURCE_LSICLK))
+
+#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1)  || ((DIV) == RCC_MCODIV_2)   || \
+                            ((DIV) == RCC_MCODIV_3)  || ((DIV) == RCC_MCODIV_4)   || \
+                            ((DIV) == RCC_MCODIV_5)  || ((DIV) == RCC_MCODIV_6)   || \
+                            ((DIV) == RCC_MCODIV_7)  || ((DIV) == RCC_MCODIV_8)   || \
+                            ((DIV) == RCC_MCODIV_9)  || ((DIV) == RCC_MCODIV_10)  || \
+                            ((DIV) == RCC_MCODIV_11) || ((DIV) == RCC_MCODIV_12)  || \
+                            ((DIV) == RCC_MCODIV_13) || ((DIV) == RCC_MCODIV_14)  || \
+                            ((DIV) == RCC_MCODIV_15))
+
+#if defined(DUAL_CORE)
+#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY)    || ((FLAG) == RCC_FLAG_CSIRDY)  || \
+                           ((FLAG) == RCC_FLAG_HSI48RDY)  || ((FLAG) == RCC_FLAG_HSERDY)  || \
+                           ((FLAG) == RCC_FLAG_D1CKRDY)   || ((FLAG) == RCC_FLAG_D2CKRDY) || \
+                           ((FLAG) == RCC_FLAG_PLLRDY)    || ((FLAG) == RCC_FLAG_PLL2RDY) || \
+                           ((FLAG) == RCC_FLAG_PLL3RDY)   || ((FLAG) == RCC_FLAG_LSERDY)  || \
+                           ((FLAG) == RCC_FLAG_LSIRDY)    || \
+                           ((FLAG) == RCC_FLAG_C1RST)     || ((FLAG) == RCC_FLAG_C2RST)   || \
+                           ((FLAG) == RCC_FLAG_SFTR2ST)   || ((FLAG) == RCC_FLAG_WWDG2RST)|| \
+                           ((FLAG) == RCC_FLAG_IWDG2RST)  || ((FLAG) == RCC_FLAG_D1RST)   || \
+                           ((FLAG) == RCC_FLAG_D2RST)     || ((FLAG) == RCC_FLAG_BORRST)  || \
+                           ((FLAG) == RCC_FLAG_PINRST)    || ((FLAG) == RCC_FLAG_PORRST)  || \
+                           ((FLAG) == RCC_FLAG_SFTR1ST)   || ((FLAG) == RCC_FLAG_IWDG1RST)|| \
+                           ((FLAG) == RCC_FLAG_WWDG1RST)  || ((FLAG) == RCC_FLAG_LPWR1RST)|| \
+                           ((FLAG) == RCC_FLAG_LPWR2RST)  || ((FLAG) == RCC_FLAG_HSIDIV))
+
+#else
+
+#if defined(RCC_CR_D2CKRDY)
+#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY)    || ((FLAG) == RCC_FLAG_CSIRDY)  || \
+                           ((FLAG) == RCC_FLAG_HSI48RDY)  || ((FLAG) == RCC_FLAG_HSERDY)  || \
+                           ((FLAG) == RCC_FLAG_D1CKRDY)   || ((FLAG) == RCC_FLAG_D2CKRDY) || \
+                           ((FLAG) == RCC_FLAG_PLLRDY)    || ((FLAG) == RCC_FLAG_PLL2RDY) || \
+                           ((FLAG) == RCC_FLAG_PLL3RDY)   || ((FLAG) == RCC_FLAG_LSERDY)  || \
+                           ((FLAG) == RCC_FLAG_LSIRDY)    || \
+                           ((FLAG) == RCC_FLAG_CPURST)    || ((FLAG) == RCC_FLAG_D1RST)   || \
+                           ((FLAG) == RCC_FLAG_D2RST)     || ((FLAG) == RCC_FLAG_BORRST)  || \
+                           ((FLAG) == RCC_FLAG_PINRST)    || ((FLAG) == RCC_FLAG_PORRST)  || \
+                           ((FLAG) == RCC_FLAG_SFTRST)    || ((FLAG) == RCC_FLAG_IWDG1RST)|| \
+                           ((FLAG) == RCC_FLAG_WWDG1RST)  || ((FLAG) == RCC_FLAG_LPWR1RST)|| \
+                           ((FLAG) == RCC_FLAG_LPWR2RST)  || ((FLAG) == RCC_FLAG_HSIDIV ))
+#else
+#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY)    || ((FLAG) == RCC_FLAG_CSIRDY)  || \
+                           ((FLAG) == RCC_FLAG_HSI48RDY)  || ((FLAG) == RCC_FLAG_HSERDY)  || \
+                           ((FLAG) == RCC_FLAG_CPUCKRDY)  || ((FLAG) == RCC_FLAG_CDCKRDY) || \
+                           ((FLAG) == RCC_FLAG_PLLRDY)    || ((FLAG) == RCC_FLAG_PLL2RDY) || \
+                           ((FLAG) == RCC_FLAG_PLL3RDY)   || ((FLAG) == RCC_FLAG_LSERDY)  || \
+                           ((FLAG) == RCC_FLAG_LSIRDY)    || \
+                           ((FLAG) == RCC_FLAG_CDRST)     || ((FLAG) == RCC_FLAG_BORRST)  || \
+                           ((FLAG) == RCC_FLAG_PINRST)    || ((FLAG) == RCC_FLAG_PORRST)  || \
+                           ((FLAG) == RCC_FLAG_SFTRST)    || ((FLAG) == RCC_FLAG_IWDG1RST)|| \
+                           ((FLAG) == RCC_FLAG_WWDG1RST)  || ((FLAG) == RCC_FLAG_LPWR1RST)|| \
+                           ((FLAG) == RCC_FLAG_LPWR2RST)  || ((FLAG) == RCC_FLAG_HSIDIV ))
+#endif /* RCC_CR_D2CKRDY */
+
+#endif /*DUAL_CORE*/
+
+#define IS_RCC_HSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7FU)
+#define IS_RCC_CSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x3FU)
+
+#define IS_RCC_STOP_WAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_WAKEUPCLOCK_CSI) || \
+                                         ((SOURCE) == RCC_STOP_WAKEUPCLOCK_HSI))
+
+#define IS_RCC_STOP_KERWAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_CSI) || \
+                                          ((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_HSI))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_RCC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h
new file mode 100644
index 00000000..42beccc8
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h
@@ -0,0 +1,4262 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_rcc_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of RCC HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_RCC_EX_H
+#define STM32H7xx_HAL_RCC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup RCCEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
+  * @{
+  */
+
+/**
+  * @brief  PLL2 Clock structure definition
+  */
+typedef struct
+{
+
+  uint32_t PLL2M;       /*!< PLL2M: Division factor for PLL2 VCO input clock.
+                             This parameter must be a number between Min_Data = 1 and Max_Data = 63    */
+
+  uint32_t PLL2N;       /*!< PLL2N: Multiplication factor for PLL2 VCO output clock.
+                             This parameter must be a number between Min_Data = 4 and Max_Data = 512
+                             or between Min_Data = 8 and Max_Data = 420(*)
+                             (*) : For stm32h7a3xx and stm32h7b3xx family lines.                       */   
+
+  uint32_t PLL2P;       /*!< PLL2P: Division factor for system clock.
+                             This parameter must be a number between Min_Data = 2 and Max_Data = 128
+                             odd division factors are not allowed                                      */
+
+  uint32_t PLL2Q;        /*!< PLL2Q: Division factor for peripheral clocks.
+                             This parameter must be a number between Min_Data = 1 and Max_Data = 128   */
+
+  uint32_t PLL2R;        /*!< PLL2R: Division factor for peripheral clocks.
+                             This parameter must be a number between Min_Data = 1 and Max_Data = 128   */
+  uint32_t PLL2RGE;      /*!<PLL2RGE: PLL2 clock Input range
+                          This parameter must be a value of @ref RCC_PLL2_VCI_Range                    */
+  uint32_t PLL2VCOSEL;   /*!<PLL2VCOSEL: PLL2 clock Output range
+                          This parameter must be a value of @ref RCC_PLL2_VCO_Range                    */
+
+  uint32_t PLL2FRACN;    /*!<PLL2FRACN: Specifies Fractional Part Of The Multiplication Factor for
+                            PLL2 VCO It should be a value between 0 and 8191                           */
+}RCC_PLL2InitTypeDef;
+
+/**
+  * @brief  PLL3 Clock structure definition
+  */
+typedef struct
+{
+
+  uint32_t PLL3M;       /*!< PLL3M: Division factor for PLL3 VCO input clock.
+                             This parameter must be a number between Min_Data = 1 and Max_Data = 63    */
+
+  uint32_t PLL3N;       /*!< PLL3N: Multiplication factor for PLL3 VCO output clock.
+                             This parameter must be a number between Min_Data = 4 and Max_Data = 512
+                             or between Min_Data = 8 and Max_Data = 420(*)
+                             (*) : For stm32h7a3xx and stm32h7b3xx family lines.                       */  
+
+  uint32_t PLL3P;       /*!< PLL3P: Division factor for system clock.
+                             This parameter must be a number between Min_Data = 2 and Max_Data = 128
+                             odd division factors are not allowed                                      */
+
+  uint32_t PLL3Q;        /*!< PLL3Q: Division factor for peripheral clocks.
+                             This parameter must be a number between Min_Data = 1 and Max_Data = 128   */
+
+  uint32_t PLL3R;        /*!< PLL3R: Division factor for peripheral clocks.
+                             This parameter must be a number between Min_Data = 1 and Max_Data = 128   */
+  uint32_t PLL3RGE;      /*!<PLL3RGE: PLL3 clock Input range
+                          This parameter must be a value of @ref RCC_PLL3_VCI_Range                    */
+  uint32_t PLL3VCOSEL;   /*!<PLL3VCOSEL: PLL3 clock Output range
+                          This parameter must be a value of @ref RCC_PLL3_VCO_Range                    */
+
+  uint32_t PLL3FRACN;    /*!<PLL3FRACN: Specifies Fractional Part Of The Multiplication Factor for
+                            PLL3 VCO It should be a value between 0 and 8191                           */
+}RCC_PLL3InitTypeDef;
+
+/**
+  * @brief  RCC PLL1 Clocks structure definition
+  */
+typedef struct
+{
+  uint32_t PLL1_P_Frequency;
+  uint32_t PLL1_Q_Frequency;
+  uint32_t PLL1_R_Frequency;
+}PLL1_ClocksTypeDef;
+
+/**
+  * @brief  RCC PLL2 Clocks structure definition
+  */
+typedef struct
+{
+  uint32_t PLL2_P_Frequency;
+  uint32_t PLL2_Q_Frequency;
+  uint32_t PLL2_R_Frequency;
+}PLL2_ClocksTypeDef;
+
+/**
+  * @brief  RCC PLL3 Clocks structure definition
+  */
+typedef struct
+{
+  uint32_t PLL3_P_Frequency;
+  uint32_t PLL3_Q_Frequency;
+  uint32_t PLL3_R_Frequency;
+}PLL3_ClocksTypeDef;
+
+
+/**
+  * @brief  RCC extended clocks structure definition
+  */
+typedef struct
+{
+  uint32_t PeriphClockSelection;   /*!< The Extended Clock to be configured.
+                                        This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+  RCC_PLL2InitTypeDef PLL2;        /*!< PLL2structure parameters.
+                                        This parameter will be used only when PLL2 is selected as kernel clock Source for some peripherals */
+
+  RCC_PLL3InitTypeDef PLL3;        /*!< PLL3 structure parameters.
+                                        This parameter will be used only when PLL2 is selected as kernel clock Source for some peripherals */
+
+  uint32_t FmcClockSelection;     /*!< Specifies FMC clock source
+                                        This parameter can be a value of @ref RCCEx_FMC_Clock_Source     */
+
+#if defined(QUADSPI)
+  uint32_t QspiClockSelection;    /*!< Specifies QSPI clock source
+                                        This parameter can be a value of @ref RCCEx_QSPI_Clock_Source    */
+#endif /* QUADSPI */
+
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+  uint32_t OspiClockSelection;    /*!< Specifies OSPI clock source
+                                        This parameter can be a value of @ref RCCEx_OSPI_Clock_Source    */
+#endif /*(OCTOSPI1) || (OCTOSPI2)*/
+
+
+#if defined(DSI)
+  uint32_t DsiClockSelection;     /*!< Specifies DSI clock source
+                                     This parameter can be a value of @ref RCCEx_DSI_Clock_Source        */
+#endif /* DSI */
+
+  uint32_t SdmmcClockSelection;    /*!< Specifies SDMMC clock source
+                                        This parameter can be a value of @ref RCCEx_SDMMC_Clock_Source   */
+
+  uint32_t CkperClockSelection;   /*!< Specifies CKPER clock source
+                                        This parameter can be a value of @ref RCCEx_CLKP_Clock_Source   */
+
+  uint32_t Sai1ClockSelection;     /*!< Specifies SAI1 clock source
+                                        This parameter can be a value of @ref RCCEx_SAI1_Clock_Source    */
+
+#if defined(SAI3)
+  uint32_t Sai23ClockSelection;     /*!< Specifies SAI2/3 clock source
+                                         This parameter can be a value of @ref RCCEx_SAI23_Clock_Source  */
+#endif /* SAI3 */
+
+#if defined(RCC_CDCCIP1R_SAI2ASEL)
+  uint32_t Sai2AClockSelection;     /*!< Specifies SAI2A clock source
+                                        This parameter can be a value of @ref RCCEx_SAI2A_Clock_Source  */
+#endif /* RCC_CDCCIP1R_SAI2ASEL */
+
+#if defined(RCC_CDCCIP1R_SAI2BSEL)
+  uint32_t Sai2BClockSelection;     /*!< Specifies SAI2B clock source
+                                         This parameter can be a value of @ref RCCEx_SAI2B_Clock_Source    */
+#endif /* RCC_CDCCIP1R_SAI2BSEL */
+
+  uint32_t Spi123ClockSelection;     /*!< Specifies SPI1/2/3 clock source
+                                          This parameter can be a value of @ref RCCEx_SPI123_Clock_Source    */
+
+  uint32_t Spi45ClockSelection;     /*!< Specifies SPI4/5 clock source
+                                         This parameter can be a value of @ref RCCEx_SPI45_Clock_Source    */
+
+  uint32_t SpdifrxClockSelection;   /*!< Specifies SPDIFRX Clock clock source
+                                        This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */
+
+  uint32_t Dfsdm1ClockSelection;    /*!< Specifies DFSDM1 Clock clock source
+                                        This parameter can be a value of @ref RCCEx_DFSDM1_Clock_Source  */
+
+#if defined(DFSDM2_BASE)
+  uint32_t Dfsdm2ClockSelection;    /*!< Specifies DFSDM2 Clock clock source
+                                        This parameter can be a value of @ref RCCEx_DFSDM2_Clock_Source  */
+#endif /* DFSDM2_BASE */
+
+#if defined(FDCAN1) || defined(FDCAN2)
+  uint32_t FdcanClockSelection;   /*!< Specifies FDCAN Clock clock source
+                                        This parameter can be a value of @ref RCCEx_FDCAN_Clock_Source   */
+#endif /*FDCAN1 || FDCAN2*/
+
+  uint32_t Swpmi1ClockSelection;   /*!< Specifies SWPMI1 Clock clock source
+                                        This parameter can be a value of @ref RCCEx_SWPMI1_Clock_Source  */
+
+  uint32_t Usart234578ClockSelection;   /*!< Specifies USART2/3/4/5/7/8 clock source
+                                             This parameter can be a value of @ref RCCEx_USART234578_Clock_Source  */
+
+  uint32_t Usart16ClockSelection;  /*!< Specifies USART1/6 clock source
+                                        This parameter can be a value of @ref RCCEx_USART16_Clock_Source  */
+
+   uint32_t RngClockSelection;      /*!< Specifies RNG clock source
+                                        This parameter can be a value of @ref RCCEx_RNG_Clock_Source     */
+
+   uint32_t I2c123ClockSelection;   /*!< Specifies I2C1/2/3 clock source
+                                        This parameter can be a value of @ref RCCEx_I2C123_Clock_Source    */
+
+  uint32_t UsbClockSelection;      /*!< Specifies USB clock source
+                                        This parameter can be a value of @ref RCCEx_USB_Clock_Source     */
+
+  uint32_t CecClockSelection;     /*!< Specifies CEC clock source
+                                        This parameter can be a value of @ref RCCEx_CEC_Clock_Source     */
+
+  uint32_t Lptim1ClockSelection;   /*!< Specifies LPTIM1 clock source
+                                        This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source  */
+
+  uint32_t Lpuart1ClockSelection;  /*!< Specifies LPUART1 clock source
+                                        This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
+
+  uint32_t I2c4ClockSelection;     /*!< Specifies I2C4 clock source
+                                        This parameter can be a value of @ref RCCEx_I2C4_Clock_Source    */
+
+  uint32_t Lptim2ClockSelection;   /*!< Specifies LPTIM2 clock source
+                                        This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source  */
+
+  uint32_t Lptim345ClockSelection;   /*!< Specifies LPTIM3/4/5 clock source
+                                          This parameter can be a value of @ref RCCEx_LPTIM345_Clock_Source  */
+
+  uint32_t AdcClockSelection;      /*!< Specifies ADC interface clock source
+                                        This parameter can be a value of @ref RCCEx_ADC_Clock_Source     */
+#if defined(SAI4)
+  uint32_t Sai4AClockSelection;     /*!< Specifies SAI4A clock source
+                                        This parameter can be a value of @ref RCCEx_SAI4A_Clock_Source   */
+
+  uint32_t Sai4BClockSelection;     /*!< Specifies SAI4B clock source
+                                        This parameter can be a value of @ref RCCEx_SAI4B_Clock_Source   */
+#endif /* SAI4 */
+
+  uint32_t Spi6ClockSelection;     /*!< Specifies SPI6 clock source
+                                        This parameter can be a value of @ref RCCEx_SPI6_Clock_Source    */
+
+  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock clock source
+                                        This parameter can be a value of @ref RCC_RTC_Clock_Source       */
+
+#if defined(HRTIM1)
+  uint32_t Hrtim1ClockSelection;      /*!< Specifies HRTIM1 Clock clock source
+                                        This parameter can be a value of @ref RCCEx_HRTIM1_Clock_Source   */
+#endif /* HRTIM1 */
+
+  uint32_t TIMPresSelection;       /*!< Specifies TIM Clock Prescalers Selection.
+                                       This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */
+}RCC_PeriphCLKInitTypeDef;
+
+
+/**
+  * @brief RCC_CRS Init structure definition
+  */
+typedef struct
+{
+  uint32_t Prescaler;             /*!< Specifies the division factor of the SYNC signal.
+                                     This parameter can be a value of @ref RCCEx_CRS_SynchroDivider  */
+
+  uint32_t Source;                /*!< Specifies the SYNC signal source.
+                                     This parameter can be a value of @ref RCCEx_CRS_SynchroSource   */
+
+  uint32_t Polarity;              /*!< Specifies the input polarity for the SYNC signal source.
+                                     This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
+
+  uint32_t ReloadValue;           /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
+                                      It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)
+                                     This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
+
+  uint32_t ErrorLimitValue;       /*!< Specifies the value to be used to evaluate the captured frequency error value.
+                                     This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
+
+  uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
+                                     This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
+
+}RCC_CRSInitTypeDef;
+
+/**
+  * @brief RCC_CRS Synchronization structure definition
+  */
+typedef struct
+{
+  uint32_t ReloadValue;           /*!< Specifies the value loaded in the Counter reload value.
+                                     This parameter must be a number between 0 and 0xFFFF */
+
+  uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
+                                     This parameter must be a number between 0 and 0x3F */
+
+  uint32_t FreqErrorCapture;      /*!< Specifies the value loaded in the .FECAP, the frequency error counter
+                                                                    value latched in the time of the last SYNC event.
+                                    This parameter must be a number between 0 and 0xFFFF */
+
+  uint32_t FreqErrorDirection;    /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
+                                                                    frequency error counter latched in the time of the last SYNC event.
+                                                                    It shows whether the actual frequency is below or above the target.
+                                    This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
+
+}RCC_CRSSynchroInfoTypeDef;
+
+/**
+  * @}
+  */
+
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Constants  RCCEx Exported Constants
+  * @{
+  */
+
+/** @defgroup RCCEx_Periph_Clock_Selection  RCCEx Periph Clock Selection
+  * @{
+  */
+
+#if defined(UART9) && defined(USART10)
+#define RCC_PERIPHCLK_USART16910       (0x00000001U)
+#define RCC_PERIPHCLK_USART1           RCC_PERIPHCLK_USART16910
+#define RCC_PERIPHCLK_USART6           RCC_PERIPHCLK_USART16910
+#define RCC_PERIPHCLK_UART9            RCC_PERIPHCLK_USART16910
+#define RCC_PERIPHCLK_USART10          RCC_PERIPHCLK_USART16910
+/*alias*/
+#define RCC_PERIPHCLK_USART16          RCC_PERIPHCLK_USART16910
+#else
+#define RCC_PERIPHCLK_USART16          (0x00000001U)
+#define RCC_PERIPHCLK_USART1           RCC_PERIPHCLK_USART16
+#define RCC_PERIPHCLK_USART6           RCC_PERIPHCLK_USART16
+/* alias */
+#define RCC_PERIPHCLK_USART16910       RCC_PERIPHCLK_USART16
+#endif /* UART9 && USART10*/
+#define RCC_PERIPHCLK_USART234578      (0x00000002U)
+#define RCC_PERIPHCLK_USART2           RCC_PERIPHCLK_USART234578
+#define RCC_PERIPHCLK_USART3           RCC_PERIPHCLK_USART234578
+#define RCC_PERIPHCLK_UART4            RCC_PERIPHCLK_USART234578
+#define RCC_PERIPHCLK_UART5            RCC_PERIPHCLK_USART234578
+#define RCC_PERIPHCLK_UART7            RCC_PERIPHCLK_USART234578
+#define RCC_PERIPHCLK_UART8            RCC_PERIPHCLK_USART234578
+#define RCC_PERIPHCLK_LPUART1          (0x00000004U)
+#define RCC_PERIPHCLK_I2C123           (0x00000008U)
+#define RCC_PERIPHCLK_I2C1             RCC_PERIPHCLK_I2C123
+#define RCC_PERIPHCLK_I2C2             RCC_PERIPHCLK_I2C123
+#define RCC_PERIPHCLK_I2C3             RCC_PERIPHCLK_I2C123
+#define RCC_PERIPHCLK_I2C4             (0x00000010U)
+#define RCC_PERIPHCLK_LPTIM1           (0x00000020U)
+#define RCC_PERIPHCLK_LPTIM2           (0x00000040U)
+#define RCC_PERIPHCLK_LPTIM345         (0x00000080U)
+#define RCC_PERIPHCLK_LPTIM3           RCC_PERIPHCLK_LPTIM345
+#if defined(LPTIM4)
+#define RCC_PERIPHCLK_LPTIM4           RCC_PERIPHCLK_LPTIM345
+#endif /*LPTIM4*/
+#if defined(LPTIM5)
+#define RCC_PERIPHCLK_LPTIM5           RCC_PERIPHCLK_LPTIM345
+#endif /*LPTIM5*/
+#define RCC_PERIPHCLK_SAI1             (0x00000100U)
+#if defined(SAI3)
+#define RCC_PERIPHCLK_SAI23            (0x00000200U)
+#define RCC_PERIPHCLK_SAI2             RCC_PERIPHCLK_SAI23
+#define RCC_PERIPHCLK_SAI3             RCC_PERIPHCLK_SAI23
+#endif /* SAI3 */
+#if defined(RCC_CDCCIP1R_SAI2ASEL_0)
+#define RCC_PERIPHCLK_SAI2A            (0x00000200U)
+#endif /* RCC_CDCCIP1R_SAI2ASEL_0 */
+#if defined(RCC_CDCCIP1R_SAI2BSEL_0)
+#define RCC_PERIPHCLK_SAI2B            (0x00000400U)
+#endif /* RCC_CDCCIP1R_SAI2BSEL_0 */
+#if defined(SAI4)
+#define RCC_PERIPHCLK_SAI4A            (0x00000400U)
+#define RCC_PERIPHCLK_SAI4B            (0x00000800U)
+#endif /* SAI4 */
+#define RCC_PERIPHCLK_SPI123           (0x00001000U)
+#define RCC_PERIPHCLK_SPI1             RCC_PERIPHCLK_SPI123
+#define RCC_PERIPHCLK_SPI2             RCC_PERIPHCLK_SPI123
+#define RCC_PERIPHCLK_SPI3             RCC_PERIPHCLK_SPI123
+#define RCC_PERIPHCLK_SPI45            (0x00002000U)
+#define RCC_PERIPHCLK_SPI4             RCC_PERIPHCLK_SPI45
+#define RCC_PERIPHCLK_SPI5             RCC_PERIPHCLK_SPI45
+#define RCC_PERIPHCLK_SPI6             (0x00004000U)
+#define RCC_PERIPHCLK_FDCAN            (0x00008000U)
+#define RCC_PERIPHCLK_SDMMC            (0x00010000U)
+#define RCC_PERIPHCLK_RNG              (0x00020000U)
+#define RCC_PERIPHCLK_USB              (0x00040000U)
+#define RCC_PERIPHCLK_ADC              (0x00080000U)
+#define RCC_PERIPHCLK_SWPMI1           (0x00100000U)
+#define RCC_PERIPHCLK_DFSDM1           (0x00200000U)
+#if defined(DFSDM2_BASE)
+#define RCC_PERIPHCLK_DFSDM2           (0x00000800U)
+#endif /* DFSDM2 */
+#define RCC_PERIPHCLK_RTC              (0x00400000U)
+#define RCC_PERIPHCLK_CEC              (0x00800000U)
+#define RCC_PERIPHCLK_FMC              (0x01000000U)
+#if defined(QUADSPI)
+#define RCC_PERIPHCLK_QSPI             (0x02000000U)
+#endif /* QUADSPI */
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+#define RCC_PERIPHCLK_OSPI             (0x02000000U)
+#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
+#define RCC_PERIPHCLK_DSI              (0x04000000U)
+#define RCC_PERIPHCLK_SPDIFRX          (0x08000000U)
+#if defined(HRTIM1)
+#define RCC_PERIPHCLK_HRTIM1           (0x10000000U)
+#endif /* HRTIM1 */
+#if defined(LTDC)
+#define RCC_PERIPHCLK_LTDC             (0x20000000U)
+#endif /* LTDC */
+#define RCC_PERIPHCLK_TIM              (0x40000000U)
+#define RCC_PERIPHCLK_CKPER            (0x80000000U)
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_PLL2_Clock_Output  RCC PLL2 Clock Output
+  * @{
+  */
+#define RCC_PLL2_DIVP                RCC_PLLCFGR_DIVP2EN
+#define RCC_PLL2_DIVQ                RCC_PLLCFGR_DIVQ2EN
+#define RCC_PLL2_DIVR                RCC_PLLCFGR_DIVR2EN
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLL3_Clock_Output  RCC PLL3 Clock Output
+  * @{
+  */
+#define RCC_PLL3_DIVP                RCC_PLLCFGR_DIVP3EN
+#define RCC_PLL3_DIVQ                RCC_PLLCFGR_DIVQ3EN
+#define RCC_PLL3_DIVR                RCC_PLLCFGR_DIVR3EN
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLL2_VCI_Range  RCC PLL2 VCI Range
+  * @{
+  */
+#define RCC_PLL2VCIRANGE_0                RCC_PLLCFGR_PLL2RGE_0        /*!< Clock range frequency between 1 and 2 MHz  */
+#define RCC_PLL2VCIRANGE_1                RCC_PLLCFGR_PLL2RGE_1        /*!< Clock range frequency between 2 and 4 MHz  */
+#define RCC_PLL2VCIRANGE_2                RCC_PLLCFGR_PLL2RGE_2        /*!< Clock range frequency between 4 and 8 MHz  */
+#define RCC_PLL2VCIRANGE_3                RCC_PLLCFGR_PLL2RGE_3        /*!< Clock range frequency between 8 and 16 MHz */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_PLL2_VCO_Range  RCC PLL2 VCO Range
+  * @{
+  */
+#define RCC_PLL2VCOWIDE                 (0x00000000U)
+#define RCC_PLL2VCOMEDIUM               RCC_PLLCFGR_PLL2VCOSEL
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLL3_VCI_Range  RCC PLL3 VCI Range
+  * @{
+  */
+#define RCC_PLL3VCIRANGE_0                RCC_PLLCFGR_PLL3RGE_0         /*!< Clock range frequency between 1 and 2 MHz  */
+#define RCC_PLL3VCIRANGE_1                RCC_PLLCFGR_PLL3RGE_1         /*!< Clock range frequency between 2 and 4 MHz  */
+#define RCC_PLL3VCIRANGE_2                RCC_PLLCFGR_PLL3RGE_2         /*!< Clock range frequency between 4 and 8 MHz  */
+#define RCC_PLL3VCIRANGE_3                RCC_PLLCFGR_PLL3RGE_3         /*!< Clock range frequency between 8 and 16 MHz */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_PLL3_VCO_Range  RCC PLL3 VCO Range
+  * @{
+  */
+#define RCC_PLL3VCOWIDE                 (0x00000000U)
+#define RCC_PLL3VCOMEDIUM               RCC_PLLCFGR_PLL3VCOSEL
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_USART16_Clock_Source  RCCEx USART1/6 Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP2R_USART16SEL)
+#define RCC_USART16CLKSOURCE_D2PCLK2    (0x00000000U)
+/* alias */
+#define RCC_USART16CLKSOURCE_PCLK2        RCC_USART16CLKSOURCE_D2PCLK2
+#define RCC_USART16CLKSOURCE_PLL2         RCC_D2CCIP2R_USART16SEL_0
+#define RCC_USART16CLKSOURCE_PLL3         RCC_D2CCIP2R_USART16SEL_1
+#define RCC_USART16CLKSOURCE_HSI         (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_1)
+#define RCC_USART16CLKSOURCE_CSI          RCC_D2CCIP2R_USART16SEL_2
+#define RCC_USART16CLKSOURCE_LSE         (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_2)
+
+#else
+#define RCC_USART16910CLKSOURCE_CDPCLK2   (0x00000000U)
+/* alias */
+#define RCC_USART16910CLKSOURCE_D2PCLK2   RCC_USART16910CLKSOURCE_CDPCLK2
+#define RCC_USART16910CLKSOURCE_PLL2      RCC_CDCCIP2R_USART16910SEL_0
+#define RCC_USART16910CLKSOURCE_PLL3      RCC_CDCCIP2R_USART16910SEL_1
+#define RCC_USART16910CLKSOURCE_HSI      (RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_1)
+#define RCC_USART16910CLKSOURCE_CSI       RCC_CDCCIP2R_USART16910SEL_2
+#define RCC_USART16910CLKSOURCE_LSE      (RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_2)
+
+/*  Aliases */
+#define RCC_USART16CLKSOURCE_CDPCLK2     RCC_USART16910CLKSOURCE_CDPCLK2
+#define RCC_USART16CLKSOURCE_PCLK2       RCC_USART16CLKSOURCE_CDPCLK2
+#define RCC_USART16CLKSOURCE_D2PCLK2     RCC_USART16CLKSOURCE_CDPCLK2
+#define RCC_USART16CLKSOURCE_PLL2        RCC_USART16910CLKSOURCE_PLL2
+#define RCC_USART16CLKSOURCE_PLL3        RCC_USART16910CLKSOURCE_PLL3
+#define RCC_USART16CLKSOURCE_HSI         RCC_USART16910CLKSOURCE_HSI
+#define RCC_USART16CLKSOURCE_CSI         RCC_USART16910CLKSOURCE_CSI
+#define RCC_USART16CLKSOURCE_LSE         RCC_USART16910CLKSOURCE_LSE
+#endif /* RCC_D2CCIP2R_USART16SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_USART1_Clock_Source  RCCEx USART1 Clock Source
+  * @{
+  */
+#define RCC_USART1CLKSOURCE_D2PCLK2   RCC_USART16CLKSOURCE_D2PCLK2
+#define RCC_USART1CLKSOURCE_PLL2      RCC_USART16CLKSOURCE_PLL2
+#define RCC_USART1CLKSOURCE_PLL3      RCC_USART16CLKSOURCE_PLL3
+#define RCC_USART1CLKSOURCE_HSI       RCC_USART16CLKSOURCE_HSI
+#define RCC_USART1CLKSOURCE_CSI       RCC_USART16CLKSOURCE_CSI
+#define RCC_USART1CLKSOURCE_LSE       RCC_USART16CLKSOURCE_LSE
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_USART6_Clock_Source  RCCEx USART6 Clock Source
+  * @{
+  */
+#define RCC_USART6CLKSOURCE_D2PCLK2   RCC_USART16CLKSOURCE_D2PCLK2
+#define RCC_USART6CLKSOURCE_PLL2      RCC_USART16CLKSOURCE_PLL2
+#define RCC_USART6CLKSOURCE_PLL3      RCC_USART16CLKSOURCE_PLL3
+#define RCC_USART6CLKSOURCE_HSI       RCC_USART16CLKSOURCE_HSI
+#define RCC_USART6CLKSOURCE_CSI       RCC_USART16CLKSOURCE_CSI
+#define RCC_USART6CLKSOURCE_LSE       RCC_USART16CLKSOURCE_LSE
+
+/**
+  * @}
+  */
+
+#if defined(UART9)
+/** @defgroup RCCEx_UART9_Clock_Source  RCCEx UART9 Clock Source
+  * @{
+  */
+#define RCC_UART9CLKSOURCE_D2PCLK2   RCC_USART16CLKSOURCE_D2PCLK2
+#define RCC_UART9CLKSOURCE_PLL2      RCC_USART16CLKSOURCE_PLL2
+#define RCC_UART9CLKSOURCE_PLL3      RCC_USART16CLKSOURCE_PLL3
+#define RCC_UART9CLKSOURCE_HSI       RCC_USART16CLKSOURCE_HSI
+#define RCC_UART9CLKSOURCE_CSI       RCC_USART16CLKSOURCE_CSI
+#define RCC_UART9CLKSOURCE_LSE       RCC_USART16CLKSOURCE_LSE
+/**
+  * @}
+  */
+#endif /* UART9 */
+
+#if defined(USART10)
+/** @defgroup RCCEx_USART10_Clock_Source  RCCEx USART10 Clock Source
+  * @{
+  */
+#define RCC_USART10CLKSOURCE_D2PCLK2   RCC_USART16CLKSOURCE_D2PCLK2
+#define RCC_USART10CLKSOURCE_PLL2      RCC_USART16CLKSOURCE_PLL2
+#define RCC_USART10CLKSOURCE_PLL3      RCC_USART16CLKSOURCE_PLL3
+#define RCC_USART10CLKSOURCE_HSI       RCC_USART16CLKSOURCE_HSI
+#define RCC_USART10CLKSOURCE_CSI       RCC_USART16CLKSOURCE_CSI
+#define RCC_USART10CLKSOURCE_LSE       RCC_USART16CLKSOURCE_LSE
+/**
+  * @}
+  */
+#endif /* USART10 */
+
+/** @defgroup RCCEx_USART234578_Clock_Source  RCCEx USART2/3/4/5/7/8 Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP2R_USART28SEL)
+#define RCC_USART234578CLKSOURCE_D2PCLK1    (0x00000000U)
+/* alias */
+#define RCC_USART234578CLKSOURCE_PCLK1      RCC_USART234578CLKSOURCE_D2PCLK1
+#define RCC_USART234578CLKSOURCE_PLL2       RCC_D2CCIP2R_USART28SEL_0
+#define RCC_USART234578CLKSOURCE_PLL3       RCC_D2CCIP2R_USART28SEL_1
+#define RCC_USART234578CLKSOURCE_HSI        (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)
+#define RCC_USART234578CLKSOURCE_CSI        RCC_D2CCIP2R_USART28SEL_2
+#define RCC_USART234578CLKSOURCE_LSE        (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)
+#else
+#define RCC_USART234578CLKSOURCE_CDPCLK1   (0x00000000U)
+/* alias */
+#define RCC_USART234578CLKSOURCE_PCLK1     RCC_USART234578CLKSOURCE_CDPCLK1
+#define RCC_USART234578CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_CDPCLK1
+#define RCC_USART234578CLKSOURCE_PLL2      RCC_CDCCIP2R_USART234578SEL_0
+#define RCC_USART234578CLKSOURCE_PLL3      RCC_CDCCIP2R_USART234578SEL_1
+#define RCC_USART234578CLKSOURCE_HSI      (RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_1)
+#define RCC_USART234578CLKSOURCE_CSI       RCC_CDCCIP2R_USART234578SEL_2
+#define RCC_USART234578CLKSOURCE_LSE      (RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_2)
+#endif /* RCC_D2CCIP2R_USART28SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_USART2_Clock_Source  RCCEx USART2 Clock Source
+  * @{
+  */
+#define RCC_USART2CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1
+#define RCC_USART2CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2
+#define RCC_USART2CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3
+#define RCC_USART2CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI
+#define RCC_USART2CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI
+#define RCC_USART2CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_USART3_Clock_Source  RCCEx USART3 Clock Source
+  * @{
+  */
+#define RCC_USART3CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1
+#define RCC_USART3CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2
+#define RCC_USART3CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3
+#define RCC_USART3CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI
+#define RCC_USART3CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI
+#define RCC_USART3CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_UART4_Clock_Source  RCCEx UART4 Clock Source
+  * @{
+  */
+#define RCC_UART4CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1
+#define RCC_UART4CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2
+#define RCC_UART4CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3
+#define RCC_UART4CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI
+#define RCC_UART4CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI
+#define RCC_UART4CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_UART5_Clock_Source  RCCEx UART5 Clock Source
+  * @{
+  */
+#define RCC_UART5CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1
+#define RCC_UART5CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2
+#define RCC_UART5CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3
+#define RCC_UART5CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI
+#define RCC_UART5CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI
+#define RCC_UART5CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_UART7_Clock_Source  RCCEx UART7 Clock Source
+  * @{
+  */
+#define RCC_UART7CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1
+#define RCC_UART7CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2
+#define RCC_UART7CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3
+#define RCC_UART7CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI
+#define RCC_UART7CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI
+#define RCC_UART7CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_UART8_Clock_Source  RCCEx UART8 Clock Source
+  * @{
+  */
+#define RCC_UART8CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1
+#define RCC_UART8CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2
+#define RCC_UART8CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3
+#define RCC_UART8CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI
+#define RCC_UART8CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI
+#define RCC_UART8CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_LPUART1_Clock_Source  RCCEx LPUART1 Clock Source
+  * @{
+  */
+#if defined(RCC_D3CCIPR_LPUART1SEL)
+#define RCC_LPUART1CLKSOURCE_D3PCLK1    (0x00000000U)
+/* alias */
+#define RCC_LPUART1CLKSOURCE_PCLK4     RCC_LPUART1CLKSOURCE_D3PCLK1
+#define RCC_LPUART1CLKSOURCE_PLL2      RCC_D3CCIPR_LPUART1SEL_0
+#define RCC_LPUART1CLKSOURCE_PLL3      RCC_D3CCIPR_LPUART1SEL_1
+#define RCC_LPUART1CLKSOURCE_HSI       (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_1)
+#define RCC_LPUART1CLKSOURCE_CSI        RCC_D3CCIPR_LPUART1SEL_2
+#define RCC_LPUART1CLKSOURCE_LSE       (RCC_D3CCIPR_LPUART1SEL_2 | RCC_D3CCIPR_LPUART1SEL_0)
+#else
+#define RCC_LPUART1CLKSOURCE_SRDPCLK4   (0x00000000U)
+/* alias*/
+#define RCC_LPUART1CLKSOURCE_PCLK4     RCC_LPUART1CLKSOURCE_SRDPCLK4
+#define RCC_LPUART1CLKSOURCE_D3PCLK1   RCC_LPUART1CLKSOURCE_SRDPCLK4
+#define RCC_LPUART1CLKSOURCE_PLL2      RCC_SRDCCIPR_LPUART1SEL_0
+#define RCC_LPUART1CLKSOURCE_PLL3      RCC_SRDCCIPR_LPUART1SEL_1
+#define RCC_LPUART1CLKSOURCE_HSI       (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_1)
+#define RCC_LPUART1CLKSOURCE_CSI        RCC_SRDCCIPR_LPUART1SEL_2
+#define RCC_LPUART1CLKSOURCE_LSE       (RCC_SRDCCIPR_LPUART1SEL_2 | RCC_SRDCCIPR_LPUART1SEL_0)
+#endif /* RCC_D3CCIPR_LPUART1SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_I2C123_Clock_Source  RCCEx I2C1/2/3 Clock Source
+  * @{
+  */
+#if defined (RCC_D2CCIP2R_I2C123SEL)
+#define RCC_I2C123CLKSOURCE_D2PCLK1      (0x00000000U)
+#define RCC_I2C123CLKSOURCE_PLL3         RCC_D2CCIP2R_I2C123SEL_0
+#define RCC_I2C123CLKSOURCE_HSI          RCC_D2CCIP2R_I2C123SEL_1
+#define RCC_I2C123CLKSOURCE_CSI         (RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1)
+#else
+#define RCC_I2C123CLKSOURCE_CDPCLK1      (0x00000000U)
+/* alias */
+#define RCC_I2C123CLKSOURCE_D2PCLK1      RCC_I2C123CLKSOURCE_CDPCLK1
+#define RCC_I2C123CLKSOURCE_PLL3         RCC_CDCCIP2R_I2C123SEL_0
+#define RCC_I2C123CLKSOURCE_HSI          RCC_CDCCIP2R_I2C123SEL_1
+#define RCC_I2C123CLKSOURCE_CSI         (RCC_CDCCIP2R_I2C123SEL_0 | RCC_CDCCIP2R_I2C123SEL_1)
+#endif /* RCC_D2CCIP2R_I2C123SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_I2C1_Clock_Source  RCCEx I2C1 Clock Source
+  * @{
+  */
+#define RCC_I2C1CLKSOURCE_D2PCLK1     RCC_I2C123CLKSOURCE_D2PCLK1
+#define RCC_I2C1CLKSOURCE_PLL3        RCC_I2C123CLKSOURCE_PLL3
+#define RCC_I2C1CLKSOURCE_HSI         RCC_I2C123CLKSOURCE_HSI
+#define RCC_I2C1CLKSOURCE_CSI         RCC_I2C123CLKSOURCE_CSI
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_I2C2_Clock_Source  RCCEx I2C2 Clock Source
+  * @{
+  */
+#define RCC_I2C2CLKSOURCE_D2PCLK1     RCC_I2C123CLKSOURCE_D2PCLK1
+#define RCC_I2C2CLKSOURCE_PLL3        RCC_I2C123CLKSOURCE_PLL3
+#define RCC_I2C2CLKSOURCE_HSI         RCC_I2C123CLKSOURCE_HSI
+#define RCC_I2C2CLKSOURCE_CSI         RCC_I2C123CLKSOURCE_CSI
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_I2C3_Clock_Source  RCCEx I2C3 Clock Source
+  * @{
+  */
+#define RCC_I2C3CLKSOURCE_D2PCLK1     RCC_I2C123CLKSOURCE_D2PCLK1
+#define RCC_I2C3CLKSOURCE_PLL3        RCC_I2C123CLKSOURCE_PLL3
+#define RCC_I2C3CLKSOURCE_HSI         RCC_I2C123CLKSOURCE_HSI
+#define RCC_I2C3CLKSOURCE_CSI         RCC_I2C123CLKSOURCE_CSI
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_I2C4_Clock_Source  RCCEx I2C4 Clock Source
+  * @{
+  */
+#if defined(RCC_D3CCIPR_I2C4SEL)
+#define RCC_I2C4CLKSOURCE_D3PCLK1      (0x00000000U)
+#define RCC_I2C4CLKSOURCE_PLL3         RCC_D3CCIPR_I2C4SEL_0
+#define RCC_I2C4CLKSOURCE_HSI          RCC_D3CCIPR_I2C4SEL_1
+#define RCC_I2C4CLKSOURCE_CSI         (RCC_D3CCIPR_I2C4SEL_0 | RCC_D3CCIPR_I2C4SEL_1)
+#else
+#define RCC_I2C4CLKSOURCE_SRDPCLK4     (0x00000000U)
+/* alias */
+#define RCC_I2C4CLKSOURCE_D3PCLK1     RCC_I2C4CLKSOURCE_SRDPCLK4
+#define RCC_I2C4CLKSOURCE_PLL3         RCC_SRDCCIPR_I2C4SEL_0
+#define RCC_I2C4CLKSOURCE_HSI          RCC_SRDCCIPR_I2C4SEL_1
+#define RCC_I2C4CLKSOURCE_CSI         (RCC_SRDCCIPR_I2C4SEL_0 | RCC_SRDCCIPR_I2C4SEL_1)
+#endif /* RCC_D3CCIPR_I2C4SEL */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_RNG_Clock_Source  RCCEx RNG Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP2R_RNGSEL)
+#define RCC_RNGCLKSOURCE_HSI48        (0x00000000U)
+#define RCC_RNGCLKSOURCE_PLL           RCC_D2CCIP2R_RNGSEL_0
+#define RCC_RNGCLKSOURCE_LSE           RCC_D2CCIP2R_RNGSEL_1
+#define RCC_RNGCLKSOURCE_LSI           RCC_D2CCIP2R_RNGSEL
+#else
+#define RCC_RNGCLKSOURCE_HSI48        (0x00000000U)
+#define RCC_RNGCLKSOURCE_PLL           RCC_CDCCIP2R_RNGSEL_0
+#define RCC_RNGCLKSOURCE_LSE           RCC_CDCCIP2R_RNGSEL_1
+#define RCC_RNGCLKSOURCE_LSI           RCC_CDCCIP2R_RNGSEL
+#endif /* RCC_D2CCIP2R_RNGSEL */
+
+/**
+  * @}
+  */
+#if defined(HRTIM1)
+
+/** @defgroup RCCEx_HRTIM1_Clock_Source RCC Extended HRTIM1 Clock Source
+  * @{
+  */
+#define RCC_HRTIM1CLK_TIMCLK                (0x00000000U)
+#define RCC_HRTIM1CLK_CPUCLK                RCC_CFGR_HRTIMSEL
+
+/**
+  * @}
+  */
+#endif /*HRTIM1*/
+
+/** @defgroup RCCEx_USB_Clock_Source  RCCEx USB Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP2R_USBSEL)
+#define RCC_USBCLKSOURCE_PLL                  RCC_D2CCIP2R_USBSEL_0
+#define RCC_USBCLKSOURCE_PLL3                 RCC_D2CCIP2R_USBSEL_1
+#define RCC_USBCLKSOURCE_HSI48                RCC_D2CCIP2R_USBSEL
+#else
+#define RCC_USBCLKSOURCE_PLL                  RCC_CDCCIP2R_USBSEL_0
+#define RCC_USBCLKSOURCE_PLL3                 RCC_CDCCIP2R_USBSEL_1
+#define RCC_USBCLKSOURCE_HSI48                RCC_CDCCIP2R_USBSEL
+#endif /* RCC_D2CCIP2R_USBSEL */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_SAI1SEL)
+#define RCC_SAI1CLKSOURCE_PLL         (0x00000000U)
+#define RCC_SAI1CLKSOURCE_PLL2         RCC_D2CCIP1R_SAI1SEL_0
+#define RCC_SAI1CLKSOURCE_PLL3         RCC_D2CCIP1R_SAI1SEL_1
+#define RCC_SAI1CLKSOURCE_PIN         (RCC_D2CCIP1R_SAI1SEL_0 | RCC_D2CCIP1R_SAI1SEL_1)
+#define RCC_SAI1CLKSOURCE_CLKP         RCC_D2CCIP1R_SAI1SEL_2
+#else
+#define RCC_SAI1CLKSOURCE_PLL         (0x00000000U)
+#define RCC_SAI1CLKSOURCE_PLL2         RCC_CDCCIP1R_SAI1SEL_0
+#define RCC_SAI1CLKSOURCE_PLL3         RCC_CDCCIP1R_SAI1SEL_1
+#define RCC_SAI1CLKSOURCE_PIN         (RCC_CDCCIP1R_SAI1SEL_0 | RCC_CDCCIP1R_SAI1SEL_1)
+#define RCC_SAI1CLKSOURCE_CLKP         RCC_CDCCIP1R_SAI1SEL_2
+#endif /* RCC_D2CCIP1R_SAI1SEL */
+/**
+  * @}
+  */
+
+#if defined(SAI3)
+/** @defgroup RCCEx_SAI23_Clock_Source SAI2/3 Clock Source
+  * @{
+  */
+#define RCC_SAI23CLKSOURCE_PLL         (0x00000000U)
+#define RCC_SAI23CLKSOURCE_PLL2         RCC_D2CCIP1R_SAI23SEL_0
+#define RCC_SAI23CLKSOURCE_PLL3         RCC_D2CCIP1R_SAI23SEL_1
+#define RCC_SAI23CLKSOURCE_PIN         (RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1)
+#define RCC_SAI23CLKSOURCE_CLKP         RCC_D2CCIP1R_SAI23SEL_2
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source
+  * @{
+  */
+#define RCC_SAI2CLKSOURCE_PLL         RCC_SAI23CLKSOURCE_PLL
+#define RCC_SAI2CLKSOURCE_PLL2        RCC_SAI23CLKSOURCE_PLL2
+#define RCC_SAI2CLKSOURCE_PLL3        RCC_SAI23CLKSOURCE_PLL3
+#define RCC_SAI2CLKSOURCE_PIN         RCC_SAI23CLKSOURCE_PIN
+#define RCC_SAI2CLKSOURCE_CLKP        RCC_SAI23CLKSOURCE_CLKP
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SAI3_Clock_Source SAI3 Clock Source
+  * @{
+  */
+#define RCC_SAI3CLKSOURCE_PLL         RCC_SAI23CLKSOURCE_PLL
+#define RCC_SAI3CLKSOURCE_PLL2        RCC_SAI23CLKSOURCE_PLL2
+#define RCC_SAI3CLKSOURCE_PLL3        RCC_SAI23CLKSOURCE_PLL3
+#define RCC_SAI3CLKSOURCE_PIN         RCC_SAI23CLKSOURCE_PIN
+#define RCC_SAI3CLKSOURCE_CLKP        RCC_SAI23CLKSOURCE_CLKP
+/**
+  * @}
+  */
+#endif /* SAI3 */
+
+#if defined(RCC_CDCCIP1R_SAI2ASEL)
+/** @defgroup RCCEx_SAI2_Clock_A Source SAI2A Clock Source
+  * @{
+  */
+#define RCC_SAI2ACLKSOURCE_PLL         (0x00000000U)
+#define RCC_SAI2ACLKSOURCE_PLL2         RCC_CDCCIP1R_SAI2ASEL_0
+#define RCC_SAI2ACLKSOURCE_PLL3         RCC_CDCCIP1R_SAI2ASEL_1
+#define RCC_SAI2ACLKSOURCE_PIN         (RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_1)
+#define RCC_SAI2ACLKSOURCE_CLKP         RCC_CDCCIP1R_SAI2ASEL_2
+#define RCC_SAI2ACLKSOURCE_SPDIF       (RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_2)
+ /**
+  * @}
+  */
+#endif /* RCC_CDCCIP1R_SAI2ASEL */
+
+#if defined(RCC_CDCCIP1R_SAI2BSEL)
+/** @defgroup RCCEx_SAI2_Block_B Clock_Source SAI2B Clock Source
+  * @{
+  */
+#define RCC_SAI2BCLKSOURCE_PLL         (0x00000000U)
+#define RCC_SAI2BCLKSOURCE_PLL2         RCC_CDCCIP1R_SAI2BSEL_0
+#define RCC_SAI2BCLKSOURCE_PLL3         RCC_CDCCIP1R_SAI2BSEL_1
+#define RCC_SAI2BCLKSOURCE_PIN         (RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_1)
+#define RCC_SAI2BCLKSOURCE_CLKP         RCC_CDCCIP1R_SAI2BSEL_2
+#define RCC_SAI2BCLKSOURCE_SPDIF       (RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_2)
+/**
+  * @}
+  */
+#endif /* RCC_CDCCIP1R_SAI2BSEL */
+
+
+/** @defgroup RCCEx_SPI123_Clock_Source SPI1/2/3 Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_SPI123SEL)
+#define RCC_SPI123CLKSOURCE_PLL         (0x00000000U)
+#define RCC_SPI123CLKSOURCE_PLL2         RCC_D2CCIP1R_SPI123SEL_0
+#define RCC_SPI123CLKSOURCE_PLL3         RCC_D2CCIP1R_SPI123SEL_1
+#define RCC_SPI123CLKSOURCE_PIN         (RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1)
+#define RCC_SPI123CLKSOURCE_CLKP         RCC_D2CCIP1R_SPI123SEL_2
+#else
+#define RCC_SPI123CLKSOURCE_PLL         (0x00000000U)
+#define RCC_SPI123CLKSOURCE_PLL2         RCC_CDCCIP1R_SPI123SEL_0
+#define RCC_SPI123CLKSOURCE_PLL3         RCC_CDCCIP1R_SPI123SEL_1
+#define RCC_SPI123CLKSOURCE_PIN         (RCC_CDCCIP1R_SPI123SEL_0 | RCC_CDCCIP1R_SPI123SEL_1)
+#define RCC_SPI123CLKSOURCE_CLKP         RCC_CDCCIP1R_SPI123SEL_2
+#endif /* RCC_D2CCIP1R_SPI123SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SPI1_Clock_Source SPI1 Clock Source
+  * @{
+  */
+#define RCC_SPI1CLKSOURCE_PLL         RCC_SPI123CLKSOURCE_PLL
+#define RCC_SPI1CLKSOURCE_PLL2        RCC_SPI123CLKSOURCE_PLL2
+#define RCC_SPI1CLKSOURCE_PLL3        RCC_SPI123CLKSOURCE_PLL3
+#define RCC_SPI1CLKSOURCE_PIN         RCC_SPI123CLKSOURCE_PIN
+#define RCC_SPI1CLKSOURCE_CLKP        RCC_SPI123CLKSOURCE_CLKP
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SPI2_Clock_Source SPI2 Clock Source
+  * @{
+  */
+#define RCC_SPI2CLKSOURCE_PLL         RCC_SPI123CLKSOURCE_PLL
+#define RCC_SPI2CLKSOURCE_PLL2        RCC_SPI123CLKSOURCE_PLL2
+#define RCC_SPI2CLKSOURCE_PLL3        RCC_SPI123CLKSOURCE_PLL3
+#define RCC_SPI2CLKSOURCE_PIN         RCC_SPI123CLKSOURCE_PIN
+#define RCC_SPI2CLKSOURCE_CLKP        RCC_SPI123CLKSOURCE_CLKP
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SPI3_Clock_Source SPI3 Clock Source
+  * @{
+  */
+#define RCC_SPI3CLKSOURCE_PLL         RCC_SPI123CLKSOURCE_PLL
+#define RCC_SPI3CLKSOURCE_PLL2        RCC_SPI123CLKSOURCE_PLL2
+#define RCC_SPI3CLKSOURCE_PLL3        RCC_SPI123CLKSOURCE_PLL3
+#define RCC_SPI3CLKSOURCE_PIN         RCC_SPI123CLKSOURCE_PIN
+#define RCC_SPI3CLKSOURCE_CLKP        RCC_SPI123CLKSOURCE_CLKP
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SPI45_Clock_Source SPI4/5 Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_SPI45SEL)
+#define RCC_SPI45CLKSOURCE_D2PCLK1     (0x00000000U)
+#define RCC_SPI45CLKSOURCE_PCLK1        RCC_SPI45CLKSOURCE_D2PCLK1
+#define RCC_SPI45CLKSOURCE_PLL2         RCC_D2CCIP1R_SPI45SEL_0
+#define RCC_SPI45CLKSOURCE_PLL3         RCC_D2CCIP1R_SPI45SEL_1
+#define RCC_SPI45CLKSOURCE_HSI         (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_1)
+#define RCC_SPI45CLKSOURCE_CSI          RCC_D2CCIP1R_SPI45SEL_2
+#define RCC_SPI45CLKSOURCE_HSE         (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_2)
+#else
+#define RCC_SPI45CLKSOURCE_CDPCLK1     (0x00000000U)
+/* aliases */
+#define RCC_SPI45CLKSOURCE_D2PCLK1      RCC_SPI45CLKSOURCE_CDPCLK1  /* D2PCLK1 is used in STM32H74xxx, STM32H75xxx, STM32H72xxx and STM32H73xxx family lines */
+#define RCC_SPI45CLKSOURCE_PCLK1        RCC_SPI45CLKSOURCE_CDPCLK1
+#define RCC_SPI45CLKSOURCE_PLL2         RCC_CDCCIP1R_SPI45SEL_0
+#define RCC_SPI45CLKSOURCE_PLL3         RCC_CDCCIP1R_SPI45SEL_1
+#define RCC_SPI45CLKSOURCE_HSI         (RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_1)
+#define RCC_SPI45CLKSOURCE_CSI          RCC_CDCCIP1R_SPI45SEL_2
+#define RCC_SPI45CLKSOURCE_HSE         (RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_2)
+#endif /* RCC_D2CCIP1R_SPI45SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SPI4_Clock_Source SPI4 Clock Source
+  * @{
+  */
+#define RCC_SPI4CLKSOURCE_D2PCLK1     RCC_SPI45CLKSOURCE_D2PCLK1
+#define RCC_SPI4CLKSOURCE_PLL2        RCC_SPI45CLKSOURCE_PLL2
+#define RCC_SPI4CLKSOURCE_PLL3        RCC_SPI45CLKSOURCE_PLL3
+#define RCC_SPI4CLKSOURCE_HSI         RCC_SPI45CLKSOURCE_HSI
+#define RCC_SPI4CLKSOURCE_CSI         RCC_SPI45CLKSOURCE_CSI
+#define RCC_SPI4CLKSOURCE_HSE         RCC_SPI45CLKSOURCE_HSE
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SPI5_Clock_Source SPI5 Clock Source
+  * @{
+  */
+#define RCC_SPI5CLKSOURCE_D2PCLK1     RCC_SPI45CLKSOURCE_D2PCLK1
+#define RCC_SPI5CLKSOURCE_PLL2        RCC_SPI45CLKSOURCE_PLL2
+#define RCC_SPI5CLKSOURCE_PLL3        RCC_SPI45CLKSOURCE_PLL3
+#define RCC_SPI5CLKSOURCE_HSI         RCC_SPI45CLKSOURCE_HSI
+#define RCC_SPI5CLKSOURCE_CSI         RCC_SPI45CLKSOURCE_CSI
+#define RCC_SPI5CLKSOURCE_HSE         RCC_SPI45CLKSOURCE_HSE
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SPI6_Clock_Source SPI6 Clock Source
+  * @{
+  */
+#if defined(RCC_D3CCIPR_SPI6SEL)
+#define RCC_SPI6CLKSOURCE_D3PCLK1     (0x00000000U)
+#define RCC_SPI6CLKSOURCE_PCLK4        RCC_SPI6CLKSOURCE_D3PCLK1
+#define RCC_SPI6CLKSOURCE_PLL2         RCC_D3CCIPR_SPI6SEL_0
+#define RCC_SPI6CLKSOURCE_PLL3         RCC_D3CCIPR_SPI6SEL_1
+#define RCC_SPI6CLKSOURCE_HSI         (RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_1)
+#define RCC_SPI6CLKSOURCE_CSI          RCC_D3CCIPR_SPI6SEL_2
+#define RCC_SPI6CLKSOURCE_HSE         (RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_2)
+#else
+#define RCC_SPI6CLKSOURCE_SRDPCLK4    (0x00000000U)
+/* alias */
+#define RCC_SPI6CLKSOURCE_D3PCLK1      RCC_SPI6CLKSOURCE_SRDPCLK4  /* D3PCLK1 is used in STM32H74xxx, STM32H75xxx, STM32H72xxx and STM32H73xxx family lines */
+#define RCC_SPI6CLKSOURCE_PCLK4        RCC_SPI6CLKSOURCE_SRDPCLK4
+#define RCC_SPI6CLKSOURCE_PLL2         RCC_SRDCCIPR_SPI6SEL_0
+#define RCC_SPI6CLKSOURCE_PLL3         RCC_SRDCCIPR_SPI6SEL_1
+#define RCC_SPI6CLKSOURCE_HSI         (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_1)
+#define RCC_SPI6CLKSOURCE_CSI          RCC_SRDCCIPR_SPI6SEL_2
+#define RCC_SPI6CLKSOURCE_HSE         (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_2)
+#define RCC_SPI6CLKSOURCE_PIN         (RCC_SRDCCIPR_SPI6SEL_1 | RCC_SRDCCIPR_SPI6SEL_2)
+#endif /* RCC_D3CCIPR_SPI6SEL */
+
+/**
+  * @}
+  */
+
+
+#if defined(SAI4_Block_A)
+/** @defgroup RCCEx_SAI4A_Clock_Source SAI4A Clock Source
+  * @{
+  */
+#define RCC_SAI4ACLKSOURCE_PLL         (0x00000000U)
+#define RCC_SAI4ACLKSOURCE_PLL2         RCC_D3CCIPR_SAI4ASEL_0
+#define RCC_SAI4ACLKSOURCE_PLL3         RCC_D3CCIPR_SAI4ASEL_1
+#define RCC_SAI4ACLKSOURCE_PIN         (RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1)
+#define RCC_SAI4ACLKSOURCE_CLKP         RCC_D3CCIPR_SAI4ASEL_2
+
+/**
+  * @}
+  */
+#endif /* SAI4_Block_A */
+
+
+
+#if defined(SAI4_Block_B)
+/** @defgroup RCCEx_SAI4B_Clock_Source SAI4B Clock Source
+  * @{
+  */
+#define RCC_SAI4BCLKSOURCE_PLL         (0x00000000U)
+#define RCC_SAI4BCLKSOURCE_PLL2         RCC_D3CCIPR_SAI4BSEL_0
+#define RCC_SAI4BCLKSOURCE_PLL3         RCC_D3CCIPR_SAI4BSEL_1
+#define RCC_SAI4BCLKSOURCE_PIN         (RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1)
+#define RCC_SAI4BCLKSOURCE_CLKP         RCC_D3CCIPR_SAI4BSEL_2
+
+/**
+  * @}
+  */
+#endif /* SAI4_Block_B */
+
+
+/** @defgroup RCCEx_LPTIM1_Clock_Source  RCCEx LPTIM1 Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP2R_LPTIM1SEL)
+#define RCC_LPTIM1CLKSOURCE_D2PCLK1        (0x00000000U)
+/* alias */
+#define RCC_LPTIM1CLKSOURCE_PCLK1         RCC_LPTIM1CLKSOURCE_D2PCLK1
+#define RCC_LPTIM1CLKSOURCE_PLL2          RCC_D2CCIP2R_LPTIM1SEL_0
+#define RCC_LPTIM1CLKSOURCE_PLL3          RCC_D2CCIP2R_LPTIM1SEL_1
+#define RCC_LPTIM1CLKSOURCE_LSE          (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_1)
+#define RCC_LPTIM1CLKSOURCE_LSI           RCC_D2CCIP2R_LPTIM1SEL_2
+#define RCC_LPTIM1CLKSOURCE_CLKP         (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_2)
+#else
+#define RCC_LPTIM1CLKSOURCE_CDPCLK1        (0x00000000U)
+/* alias */
+#define RCC_LPTIM1CLKSOURCE_PCLK1         RCC_LPTIM1CLKSOURCE_CDPCLK1
+#define RCC_LPTIM1CLKSOURCE_D2PCLK1       RCC_LPTIM1CLKSOURCE_CDPCLK1
+#define RCC_LPTIM1CLKSOURCE_PLL2          RCC_CDCCIP2R_LPTIM1SEL_0
+#define RCC_LPTIM1CLKSOURCE_PLL3          RCC_CDCCIP2R_LPTIM1SEL_1
+#define RCC_LPTIM1CLKSOURCE_LSE          (RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_1)
+#define RCC_LPTIM1CLKSOURCE_LSI           RCC_CDCCIP2R_LPTIM1SEL_2
+#define RCC_LPTIM1CLKSOURCE_CLKP         (RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_2)
+#endif /* RCC_D2CCIP2R_LPTIM1SEL */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_LPTIM2_Clock_Source  RCCEx LPTIM2 Clock Source
+  * @{
+  */
+#if defined(RCC_D3CCIPR_LPTIM2SEL)
+#define RCC_LPTIM2CLKSOURCE_D3PCLK1       (0x00000000U)
+/* alias */
+#define RCC_LPTIM2CLKSOURCE_PCLK4         RCC_LPTIM2CLKSOURCE_D3PCLK1
+#define RCC_LPTIM2CLKSOURCE_PLL2          RCC_D3CCIPR_LPTIM2SEL_0
+#define RCC_LPTIM2CLKSOURCE_PLL3          RCC_D3CCIPR_LPTIM2SEL_1
+#define RCC_LPTIM2CLKSOURCE_LSE          (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_1)
+#define RCC_LPTIM2CLKSOURCE_LSI           RCC_D3CCIPR_LPTIM2SEL_2
+#define RCC_LPTIM2CLKSOURCE_CLKP         (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_2)
+#else
+#define RCC_LPTIM2CLKSOURCE_SRDPCLK4       (0x00000000U)
+/*alias*/
+#define RCC_LPTIM2CLKSOURCE_PCLK4         RCC_LPTIM2CLKSOURCE_SRDPCLK4
+#define RCC_LPTIM2CLKSOURCE_D3PCLK1       RCC_LPTIM2CLKSOURCE_SRDPCLK4
+#define RCC_LPTIM2CLKSOURCE_PLL2          RCC_SRDCCIPR_LPTIM2SEL_0
+#define RCC_LPTIM2CLKSOURCE_PLL3          RCC_SRDCCIPR_LPTIM2SEL_1
+#define RCC_LPTIM2CLKSOURCE_LSE          (RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_1)
+#define RCC_LPTIM2CLKSOURCE_LSI           RCC_SRDCCIPR_LPTIM2SEL_2
+#define RCC_LPTIM2CLKSOURCE_CLKP         (RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_2)
+#endif /* RCC_D3CCIPR_LPTIM2SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_LPTIM345_Clock_Source  RCCEx LPTIM3/4/5 Clock Source
+  * @{
+  */
+#if defined(RCC_D3CCIPR_LPTIM345SEL)
+#define RCC_LPTIM345CLKSOURCE_D3PCLK1        (0x00000000U)
+/* alias*/
+#define RCC_LPTIM345CLKSOURCE_PCLK4         RCC_LPTIM345CLKSOURCE_D3PCLK1
+#define RCC_LPTIM345CLKSOURCE_PLL2          RCC_D3CCIPR_LPTIM345SEL_0
+#define RCC_LPTIM345CLKSOURCE_PLL3          RCC_D3CCIPR_LPTIM345SEL_1
+#define RCC_LPTIM345CLKSOURCE_LSE          (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1)
+#define RCC_LPTIM345CLKSOURCE_LSI           RCC_D3CCIPR_LPTIM345SEL_2
+#define RCC_LPTIM345CLKSOURCE_CLKP         (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2)
+#else
+#define RCC_LPTIM345CLKSOURCE_SRDPCLK4      (0x00000000U)
+/* alias */
+#define RCC_LPTIM345CLKSOURCE_PCLK4         RCC_LPTIM345CLKSOURCE_SRDPCLK4
+#define RCC_LPTIM345CLKSOURCE_D3PCLK1       RCC_LPTIM345CLKSOURCE_SRDPCLK4
+#define RCC_LPTIM345CLKSOURCE_PLL2          RCC_SRDCCIPR_LPTIM3SEL_0
+#define RCC_LPTIM345CLKSOURCE_PLL3          RCC_SRDCCIPR_LPTIM3SEL_1
+#define RCC_LPTIM345CLKSOURCE_LSE          (RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_1)
+#define RCC_LPTIM345CLKSOURCE_LSI           RCC_SRDCCIPR_LPTIM3SEL_2
+#define RCC_LPTIM345CLKSOURCE_CLKP         (RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_2)
+#endif /* RCC_D3CCIPR_LPTIM345SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_LPTIM3_Clock_Source  RCCEx LPTIM3 Clock Source
+  * @{
+  */
+#define RCC_LPTIM3CLKSOURCE_D3PCLK1       RCC_LPTIM345CLKSOURCE_D3PCLK1
+#define RCC_LPTIM3CLKSOURCE_PLL2          RCC_LPTIM345CLKSOURCE_PLL2
+#define RCC_LPTIM3CLKSOURCE_PLL3          RCC_LPTIM345CLKSOURCE_PLL3
+#define RCC_LPTIM3CLKSOURCE_LSE           RCC_LPTIM345CLKSOURCE_LSE
+#define RCC_LPTIM3CLKSOURCE_LSI           RCC_LPTIM345CLKSOURCE_LSI
+#define RCC_LPTIM3CLKSOURCE_CLKP          RCC_LPTIM345CLKSOURCE_CLKP
+
+/**
+  * @}
+  */
+#if defined(LPTIM4)
+/** @defgroup RCCEx_LPTIM4_Clock_Source  RCCEx LPTIM4 Clock Source
+  * @{
+  */
+#define RCC_LPTIM4CLKSOURCE_D3PCLK1       RCC_LPTIM345CLKSOURCE_D3PCLK1
+#define RCC_LPTIM4CLKSOURCE_PLL2          RCC_LPTIM345CLKSOURCE_PLL2
+#define RCC_LPTIM4CLKSOURCE_PLL3          RCC_LPTIM345CLKSOURCE_PLL3
+#define RCC_LPTIM4CLKSOURCE_LSE           RCC_LPTIM345CLKSOURCE_LSE
+#define RCC_LPTIM4CLKSOURCE_LSI           RCC_LPTIM345CLKSOURCE_LSI
+#define RCC_LPTIM4CLKSOURCE_CLKP          RCC_LPTIM345CLKSOURCE_CLKP
+/**
+  * @}
+  */
+#endif /* LPTIM4 */
+
+#if defined(LPTIM5)
+/** @defgroup RCCEx_LPTIM5_Clock_Source  RCCEx LPTIM5 Clock Source
+  * @{
+  */
+#define RCC_LPTIM5CLKSOURCE_D3PCLK1       RCC_LPTIM345CLKSOURCE_D3PCLK1
+#define RCC_LPTIM5CLKSOURCE_PLL2          RCC_LPTIM345CLKSOURCE_PLL2
+#define RCC_LPTIM5CLKSOURCE_PLL3          RCC_LPTIM345CLKSOURCE_PLL3
+#define RCC_LPTIM5CLKSOURCE_LSE           RCC_LPTIM345CLKSOURCE_LSE
+#define RCC_LPTIM5CLKSOURCE_LSI           RCC_LPTIM345CLKSOURCE_LSI
+#define RCC_LPTIM5CLKSOURCE_CLKP          RCC_LPTIM345CLKSOURCE_CLKP
+
+/**
+  * @}
+  */
+#endif /* LPTIM5 */
+
+#if defined(QUADSPI)
+/** @defgroup RCCEx_QSPI_Clock_Source  RCCEx QSPI Clock Source
+  * @{
+  */
+#define RCC_QSPICLKSOURCE_D1HCLK       (0x00000000U)
+#define RCC_QSPICLKSOURCE_PLL          RCC_D1CCIPR_QSPISEL_0
+#define RCC_QSPICLKSOURCE_PLL2         RCC_D1CCIPR_QSPISEL_1
+#define RCC_QSPICLKSOURCE_CLKP         RCC_D1CCIPR_QSPISEL
+
+/**
+  * @}
+  */
+#endif /* QUADSPI */
+
+
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+/** @defgroup RCCEx_OSPI_Clock_Source  RCCEx OSPI Clock Source
+  * @{
+  */
+#define RCC_OSPICLKSOURCE_CDHCLK       (0x00000000U)
+/*aliases*/
+#define RCC_OSPICLKSOURCE_D1HCLK       RCC_OSPICLKSOURCE_CDHCLK
+#define RCC_OSPICLKSOURCE_HCLK         RCC_OSPICLKSOURCE_CDHCLK
+#define RCC_OSPICLKSOURCE_PLL          RCC_CDCCIPR_OCTOSPISEL_0
+#define RCC_OSPICLKSOURCE_PLL2         RCC_CDCCIPR_OCTOSPISEL_1
+#define RCC_OSPICLKSOURCE_CLKP         RCC_CDCCIPR_OCTOSPISEL
+
+/**
+  * @}
+  */
+#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
+
+#if defined(DSI)
+/** @defgroup RCCEx_DSI_Clock_Source  RCCEx DSI Clock Source
+  * @{
+  */
+#define RCC_DSICLKSOURCE_PHY       (0x00000000U)
+#define RCC_DSICLKSOURCE_PLL2       RCC_D1CCIPR_DSISEL
+
+/**
+  * @}
+  */
+#endif /* DSI */
+
+/** @defgroup RCCEx_FMC_Clock_Source  RCCEx FMC Clock Source
+  * @{
+  */
+#if defined(RCC_D1CCIPR_FMCSEL)
+#define RCC_FMCCLKSOURCE_D1HCLK       (0x00000000U)
+#define RCC_FMCCLKSOURCE_HCLK         RCC_FMCCLKSOURCE_D1HCLK
+#define RCC_FMCCLKSOURCE_PLL          RCC_D1CCIPR_FMCSEL_0
+#define RCC_FMCCLKSOURCE_PLL2         RCC_D1CCIPR_FMCSEL_1
+#define RCC_FMCCLKSOURCE_CLKP         RCC_D1CCIPR_FMCSEL
+#else
+#define RCC_FMCCLKSOURCE_CDHCLK       (0x00000000U)
+#define RCC_FMCCLKSOURCE_HCLK         RCC_FMCCLKSOURCE_CDHCLK
+/*alias*/
+#define RCC_FMCCLKSOURCE_D1HCLK       RCC_FMCCLKSOURCE_CDHCLK
+#define RCC_FMCCLKSOURCE_PLL          RCC_CDCCIPR_FMCSEL_0
+#define RCC_FMCCLKSOURCE_PLL2         RCC_CDCCIPR_FMCSEL_1
+#define RCC_FMCCLKSOURCE_CLKP         RCC_CDCCIPR_FMCSEL
+#endif /* RCC_D1CCIPR_FMCSEL */
+/**
+  * @}
+  */
+
+#if defined(FDCAN1) || defined(FDCAN2)
+/** @defgroup RCCEx_FDCAN_Clock_Source  RCCEx FDCAN Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_FDCANSEL)
+#define RCC_FDCANCLKSOURCE_HSE         (0x00000000U)
+#define RCC_FDCANCLKSOURCE_PLL          RCC_D2CCIP1R_FDCANSEL_0
+#define RCC_FDCANCLKSOURCE_PLL2         RCC_D2CCIP1R_FDCANSEL_1
+#else
+#define RCC_FDCANCLKSOURCE_HSE         (0x00000000U)
+#define RCC_FDCANCLKSOURCE_PLL          RCC_CDCCIP1R_FDCANSEL_0
+#define RCC_FDCANCLKSOURCE_PLL2         RCC_CDCCIP1R_FDCANSEL_1
+#endif /* D3_SRAM_BASE */
+/**
+  * @}
+  */
+#endif /*FDCAN1 || FDCAN2*/
+
+
+/** @defgroup RCCEx_SDMMC_Clock_Source  RCCEx SDMMC Clock Source
+  * @{
+  */
+#if defined(RCC_D1CCIPR_SDMMCSEL)
+#define RCC_SDMMCCLKSOURCE_PLL           (0x00000000U)
+#define RCC_SDMMCCLKSOURCE_PLL2           RCC_D1CCIPR_SDMMCSEL
+#else
+#define RCC_SDMMCCLKSOURCE_PLL           (0x00000000U)
+#define RCC_SDMMCCLKSOURCE_PLL2           RCC_CDCCIPR_SDMMCSEL
+#endif /* RCC_D1CCIPR_SDMMCSEL */
+/**
+  * @}
+  */
+
+
+/** @defgroup RCCEx_ADC_Clock_Source  RCCEx ADC Clock Source
+  * @{
+  */
+#if defined(RCC_D3CCIPR_ADCSEL_0)
+#define RCC_ADCCLKSOURCE_PLL2       (0x00000000U)
+#define RCC_ADCCLKSOURCE_PLL3       RCC_D3CCIPR_ADCSEL_0
+#define RCC_ADCCLKSOURCE_CLKP       RCC_D3CCIPR_ADCSEL_1
+#else
+#define RCC_ADCCLKSOURCE_PLL2       (0x00000000U)
+#define RCC_ADCCLKSOURCE_PLL3       RCC_SRDCCIPR_ADCSEL_0
+#define RCC_ADCCLKSOURCE_CLKP       RCC_SRDCCIPR_ADCSEL_1
+#endif /* RCC_D3CCIPR_ADCSEL_0  */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SWPMI1_Clock_Source  RCCEx SWPMI1 Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_SWPSEL)
+#define RCC_SWPMI1CLKSOURCE_D2PCLK1       (0x00000000U)
+#define RCC_SWPMI1CLKSOURCE_HSI            RCC_D2CCIP1R_SWPSEL
+#else
+#define RCC_SWPMI1CLKSOURCE_CDPCLK1       (0x00000000U)
+/* alias */
+#define RCC_SWPMI1CLKSOURCE_D2PCLK1        RCC_SWPMI1CLKSOURCE_CDPCLK1
+#define RCC_SWPMI1CLKSOURCE_HSI            RCC_CDCCIP1R_SWPSEL
+#endif /* RCC_D2CCIP1R_SWPSEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_DFSDM1_Clock_Source  RCCEx DFSDM1 Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_DFSDM1SEL)
+#define RCC_DFSDM1CLKSOURCE_D2PCLK1        (0x00000000U)
+#define RCC_DFSDM1CLKSOURCE_SYS            RCC_D2CCIP1R_DFSDM1SEL
+#else
+#define RCC_DFSDM1CLKSOURCE_CDPCLK1        (0x00000000U)
+/* alias */
+#define RCC_DFSDM1CLKSOURCE_D2PCLK1        RCC_DFSDM1CLKSOURCE_CDPCLK1
+#define RCC_DFSDM1CLKSOURCE_SYS            RCC_CDCCIP1R_DFSDM1SEL
+#endif /* RCC_D2CCIP1R_DFSDM1SEL */
+/**
+  * @}
+  */
+
+#if defined(DFSDM2_BASE)
+/** @defgroup RCCEx_DFSDM2_Clock_Source  RCCEx DFSDM2 Clock Source
+  * @{
+  */
+#define RCC_DFSDM2CLKSOURCE_SRDPCLK4       (0x00000000U)
+/* alias */
+#define RCC_DFSDM2CLKSOURCE_SRDPCLK1       RCC_DFSDM2CLKSOURCE_SRDPCLK4
+#define RCC_DFSDM2CLKSOURCE_SYS            RCC_SRDCCIPR_DFSDM2SEL
+/**
+  * @}
+  */
+#endif /* DFSDM2 */
+
+/** @defgroup RCCEx_SPDIFRX_Clock_Source  RCCEx SPDIFRX Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_SPDIFSEL_0)
+#define RCC_SPDIFRXCLKSOURCE_PLL        (0x00000000U)
+#define RCC_SPDIFRXCLKSOURCE_PLL2       RCC_D2CCIP1R_SPDIFSEL_0
+#define RCC_SPDIFRXCLKSOURCE_PLL3       RCC_D2CCIP1R_SPDIFSEL_1
+#define RCC_SPDIFRXCLKSOURCE_HSI        RCC_D2CCIP1R_SPDIFSEL
+#else
+#define RCC_SPDIFRXCLKSOURCE_PLL        (0x00000000U)
+#define RCC_SPDIFRXCLKSOURCE_PLL2       RCC_CDCCIP1R_SPDIFSEL_0
+#define RCC_SPDIFRXCLKSOURCE_PLL3       RCC_CDCCIP1R_SPDIFSEL_1
+#define RCC_SPDIFRXCLKSOURCE_HSI        RCC_CDCCIP1R_SPDIFSEL
+#endif /* RCC_D2CCIP1R_SPDIFSEL_0 */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CEC_Clock_Source  RCCEx CEC Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP2R_CECSEL_0)
+#define RCC_CECCLKSOURCE_LSE        (0x00000000U)
+#define RCC_CECCLKSOURCE_LSI         RCC_D2CCIP2R_CECSEL_0
+#define RCC_CECCLKSOURCE_CSI         RCC_D2CCIP2R_CECSEL_1
+#else
+#define RCC_CECCLKSOURCE_LSE        (0x00000000U)
+#define RCC_CECCLKSOURCE_LSI         RCC_CDCCIP2R_CECSEL_0
+#define RCC_CECCLKSOURCE_CSI         RCC_CDCCIP2R_CECSEL_1
+#endif /* RCC_D2CCIP2R_CECSEL_0 */
+/**
+  * @}
+  */
+
+
+/** @defgroup RCCEx_CLKP_Clock_Source  RCCEx CLKP Clock Source
+  * @{
+  */
+#if defined(RCC_D1CCIPR_CKPERSEL_0)
+#define RCC_CLKPSOURCE_HSI        (0x00000000U)
+#define RCC_CLKPSOURCE_CSI         RCC_D1CCIPR_CKPERSEL_0
+#define RCC_CLKPSOURCE_HSE         RCC_D1CCIPR_CKPERSEL_1
+#else
+#define RCC_CLKPSOURCE_HSI        (0x00000000U)
+#define RCC_CLKPSOURCE_CSI         RCC_CDCCIPR_CKPERSEL_0
+#define RCC_CLKPSOURCE_HSE         RCC_CDCCIPR_CKPERSEL_1
+#endif /* RCC_D1CCIPR_CKPERSEL_0 */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection
+  * @{
+  */
+#define RCC_TIMPRES_DESACTIVATED        (0x00000000U)
+#define RCC_TIMPRES_ACTIVATED            RCC_CFGR_TIMPRE
+
+/**
+  * @}
+  */
+
+#if defined(DUAL_CORE)
+
+/** @defgroup RCCEx_RCC_BootCx RCCEx RCC BootCx
+  * @{
+  */
+#define RCC_BOOT_C1        RCC_GCR_BOOT_C1
+#define RCC_BOOT_C2        RCC_GCR_BOOT_C2
+
+/**
+  * @}
+  */
+#endif /*DUAL_CORE*/
+
+#if defined(DUAL_CORE)
+/** @defgroup RCCEx_RCC_WWDGx  RCCEx RCC WWDGx
+  * @{
+  */
+#define RCC_WWDG1        RCC_GCR_WW1RSC
+#define RCC_WWDG2        RCC_GCR_WW2RSC
+
+/**
+  * @}
+  */
+
+#else
+
+/** @defgroup RCCEx_RCC_WWDGx  RCCEx RCC WWDGx
+  * @{
+  */
+#define RCC_WWDG1        RCC_GCR_WW1RSC
+
+/**
+  * @}
+  */
+
+#endif /*DUAL_CORE*/
+
+/** @defgroup RCCEx_EXTI_LINE_LSECSS  RCC LSE CSS external interrupt line
+  * @{
+  */
+#define RCC_EXTI_LINE_LSECSS           EXTI_IMR1_IM18        /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_Status RCCEx CRS Status
+  * @{
+  */
+#define RCC_CRS_NONE                   (0x00000000U)
+#define RCC_CRS_TIMEOUT                (0x00000001U)
+#define RCC_CRS_SYNCOK                 (0x00000002U)
+#define RCC_CRS_SYNCWARN               (0x00000004U)
+#define RCC_CRS_SYNCERR                (0x00000008U)
+#define RCC_CRS_SYNCMISS               (0x00000010U)
+#define RCC_CRS_TRIMOVF                (0x00000020U)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
+  * @{
+  */
+#define RCC_CRS_SYNC_SOURCE_PIN       (0x00000000U)                            /*!< Synchro Signal source external pin, Available on STM32H7 Rev.B and above devices only */
+#define RCC_CRS_SYNC_SOURCE_LSE        CRS_CFGR_SYNCSRC_0                      /*!< Synchro Signal source LSE */
+#define RCC_CRS_SYNC_SOURCE_USB1       CRS_CFGR_SYNCSRC_1                      /*!< Synchro Signal source USB1 SOF (default) */
+#define RCC_CRS_SYNC_SOURCE_USB2      (CRS_CFGR_SYNCSRC_1|CRS_CFGR_SYNCSRC_0)  /*!< Synchro Signal source USB2 SOF */
+
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider
+  * @{
+  */
+#define RCC_CRS_SYNC_DIV1        (0x00000000U)           /*!< Synchro Signal not divided (default) */
+#define RCC_CRS_SYNC_DIV2        CRS_CFGR_SYNCDIV_0                         /*!< Synchro Signal divided by 2 */
+#define RCC_CRS_SYNC_DIV4        CRS_CFGR_SYNCDIV_1                         /*!< Synchro Signal divided by 4 */
+#define RCC_CRS_SYNC_DIV8        (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0)  /*!< Synchro Signal divided by 8 */
+#define RCC_CRS_SYNC_DIV16       CRS_CFGR_SYNCDIV_2                        /*!< Synchro Signal divided by 16 */
+#define RCC_CRS_SYNC_DIV32       (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
+#define RCC_CRS_SYNC_DIV64       (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
+#define RCC_CRS_SYNC_DIV128      CRS_CFGR_SYNCDIV                         /*!< Synchro Signal divided by 128 */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity
+  * @{
+  */
+#define RCC_CRS_SYNC_POLARITY_RISING   (0x00000000U) /*!< Synchro Active on rising edge (default) */
+#define RCC_CRS_SYNC_POLARITY_FALLING  CRS_CFGR_SYNCPOL        /*!< Synchro Active on falling edge */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault
+  * @{
+  */
+#define RCC_CRS_RELOADVALUE_DEFAULT    (0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds
+                                                                    to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault
+  * @{
+  */
+#define RCC_CRS_ERRORLIMIT_DEFAULT     (0x00000022U) /*!< Default Frequency error limit */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault
+  * @{
+  */
+#define RCC_CRS_HSI48CALIBRATION_DEFAULT (0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
+                                                                      The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
+                                                                      corresponds to a higher output frequency */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection
+  * @{
+  */
+#define RCC_CRS_FREQERRORDIR_UP        (0x00000000U)   /*!< Upcounting direction, the actual frequency is above the target */
+#define RCC_CRS_FREQERRORDIR_DOWN      (CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
+  * @{
+  */
+#define RCC_CRS_IT_SYNCOK              CRS_CR_SYNCOKIE       /*!< SYNC event OK */
+#define RCC_CRS_IT_SYNCWARN            CRS_CR_SYNCWARNIE     /*!< SYNC warning */
+#define RCC_CRS_IT_ERR                 CRS_CR_ERRIE          /*!< Error */
+#define RCC_CRS_IT_ESYNC               CRS_CR_ESYNCIE        /*!< Expected SYNC */
+#define RCC_CRS_IT_SYNCERR             CRS_CR_ERRIE          /*!< SYNC error */
+#define RCC_CRS_IT_SYNCMISS            CRS_CR_ERRIE          /*!< SYNC missed */
+#define RCC_CRS_IT_TRIMOVF             CRS_CR_ERRIE          /*!< Trimming overflow or underflow */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
+  * @{
+  */
+#define RCC_CRS_FLAG_SYNCOK            CRS_ISR_SYNCOKF       /*!< SYNC event OK flag     */
+#define RCC_CRS_FLAG_SYNCWARN          CRS_ISR_SYNCWARNF     /*!< SYNC warning flag      */
+#define RCC_CRS_FLAG_ERR               CRS_ISR_ERRF          /*!< Error flag        */
+#define RCC_CRS_FLAG_ESYNC             CRS_ISR_ESYNCF        /*!< Expected SYNC flag     */
+#define RCC_CRS_FLAG_SYNCERR           CRS_ISR_SYNCERR       /*!< SYNC error */
+#define RCC_CRS_FLAG_SYNCMISS          CRS_ISR_SYNCMISS      /*!< SYNC missed*/
+#define RCC_CRS_FLAG_TRIMOVF           CRS_ISR_TRIMOVF       /*!< Trimming overflow or underflow */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
+  * @{
+  */
+
+/** @brief  Macros to enable or disable PLL2.
+  * @note   After enabling PLL2, the application software should wait on
+  *         PLL2RDY flag to be set indicating that PLL2 clock is stable and can
+  *         be used as kernel clock source.
+  * @note   PLL2 is disabled by hardware when entering STOP and STANDBY modes.
+  */
+#define __HAL_RCC_PLL2_ENABLE()         SET_BIT(RCC->CR, RCC_CR_PLL2ON)
+#define __HAL_RCC_PLL2_DISABLE()        CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON)
+
+/**
+  * @brief  Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK)
+  * @note   Enabling/disabling  those Clocks can be done only when the PLL2 is disabled,
+  *         This is mainly used to save Power.
+  * @param  __RCC_PLL2ClockOut__ Specifies the PLL2 clock to be outputted
+  *          This parameter can be one of the following values:
+  *            @arg RCC_PLL2_DIVP: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
+  *            @arg RCC_PLL2_DIVQ: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
+  *            @arg RCC_PLL2_DIVR: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
+  *
+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  *
+  * @retval None
+  */
+#define __HAL_RCC_PLL2CLKOUT_ENABLE(__RCC_PLL2ClockOut__)   SET_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))
+
+#define __HAL_RCC_PLL2CLKOUT_DISABLE(__RCC_PLL2ClockOut__)  CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))
+
+/**
+  * @brief  Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO
+  * @note   Enabling/disabling  Fractional Part can be any time  without the need to stop the PLL2
+  * @retval None
+  */
+#define __HAL_RCC_PLL2FRACN_ENABLE()   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)
+
+#define __HAL_RCC_PLL2FRACN_DISABLE()  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)
+
+/**
+  * @brief  Macro to configures the PLL2  multiplication and division factors.
+  * @note   This function must be used only when PLL2 is disabled.
+  *
+  * @param  __PLL2M__ specifies the division factor for PLL2 VCO input clock
+  *          This parameter must be a number between 1 and 63.
+  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
+  *         frequency ranges from 1 to 16 MHz.
+  *
+  * @param  __PLL2N__ specifies the multiplication factor for PLL2 VCO output clock
+  *          This parameter must be a number between 4 and 512 or between 8 and 420(*).
+  * @note   You have to set the PLL2N parameter correctly to ensure that the VCO
+  *         output frequency is between 150 and 420 MHz (when in medium VCO range) or
+  *         between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range)
+  *
+  * @param  __PLL2P__ specifies the division factor for peripheral kernel clocks
+  *          This parameter must be a number between 1 and 128.
+  *
+  * @param  __PLL2Q__ specifies the division factor for peripheral kernel clocks
+  *          This parameter must be a number between 1 and 128.
+  *
+  * @param  __PLL2R__ specifies the division factor for peripheral kernel clocks
+  *          This parameter must be a number between 1 and 128.
+  *
+  * @note   To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR)
+  *         is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible
+  *         value to  __PLL2P__, __PLL2Q__ or __PLL2R__ parameters.
+  * @retval None
+  *
+  *  (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  */
+
+#define __HAL_RCC_PLL2_CONFIG(__PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__,__PLL2R__ ) \
+                  do{ \
+                       MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM2) , ( (__PLL2M__) <<12U));  \
+                       WRITE_REG (RCC->PLL2DIVR , ( (((__PLL2N__) - 1U ) & RCC_PLL2DIVR_N2) | ((((__PLL2P__) -1U ) << 9U) & RCC_PLL2DIVR_P2) | \
+                       ((((__PLL2Q__) -1U) << 16U) & RCC_PLL2DIVR_Q2) | ((((__PLL2R__)- 1U) << 24U) & RCC_PLL2DIVR_R2))); \
+                    } while(0)
+
+/**
+  * @brief  Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor
+  *
+  * @note   These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO
+  *
+  * @param  __RCC_PLL2FRACN__ Specifies Fractional Part Of The Multiplication factor for PLL2 VCO
+  *                           It should be a value between 0 and 8191
+  * @note   Warning: the software has to set correctly these bits to insure that the VCO
+  *                  output frequency is between its valid frequency range, which is:
+  *                  192 to 836 MHz or 128 to 560 MHz(*) if PLL2VCOSEL = 0
+  *                  150 to 420 MHz if PLL2VCOSEL = 1.
+  *
+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  *
+  * @retval None
+  */
+#define  __HAL_RCC_PLL2FRACN_CONFIG(__RCC_PLL2FRACN__) \
+                 MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2,((uint32_t)(__RCC_PLL2FRACN__) << RCC_PLL2FRACR_FRACN2_Pos))
+
+/** @brief  Macro to select  the PLL2  reference frequency range.
+  * @param  __RCC_PLL2VCIRange__ specifies the PLL2 input frequency range
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PLL2VCIRANGE_0: Range frequency is between 1 and 2 MHz
+  *            @arg RCC_PLL2VCIRANGE_1: Range frequency is between 2 and 4 MHz
+  *            @arg RCC_PLL2VCIRANGE_2: Range frequency is between 4 and 8 MHz
+  *            @arg RCC_PLL2VCIRANGE_3: Range frequency is between 8 and 16 MHz
+  * @retval None
+  */
+#define __HAL_RCC_PLL2_VCIRANGE(__RCC_PLL2VCIRange__) \
+                  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, (__RCC_PLL2VCIRange__))
+
+
+/** @brief  Macro to select  the PLL2  reference frequency range.
+  * @param  __RCC_PLL2VCORange__ Specifies the PLL2 input frequency range
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PLL2VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*)
+  *            @arg RCC_PLL2VCOMEDIUM: Range frequency is between 150 and 420 MHz
+  *
+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  *
+  * @retval None
+  */
+#define __HAL_RCC_PLL2_VCORANGE(__RCC_PLL2VCORange__) \
+                  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, (__RCC_PLL2VCORange__))
+
+/** @brief  Macros to enable or disable the main PLL3.
+  * @note   After enabling  PLL3, the application software should wait on
+  *         PLL3RDY flag to be set indicating that PLL3 clock is stable and can
+  *         be used as kernel clock source.
+  * @note   PLL3 is disabled by hardware when entering STOP and STANDBY modes.
+  */
+#define __HAL_RCC_PLL3_ENABLE()         SET_BIT(RCC->CR, RCC_CR_PLL3ON)
+#define __HAL_RCC_PLL3_DISABLE()        CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON)
+
+/**
+  * @brief  Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO
+  * @note   Enabling/disabling  Fractional Part can be any time  without the need to stop the PLL3
+  * @retval None
+  */
+#define __HAL_RCC_PLL3FRACN_ENABLE()   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)
+
+#define __HAL_RCC_PLL3FRACN_DISABLE()  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)
+
+/**
+  * @brief  Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK)
+  * @note   Enabling/disabling  those Clocks can be done only when the PLL3 is disabled,
+  *         This is mainly used to save Power.
+  * @param  __RCC_PLL3ClockOut__ specifies the PLL3 clock to be outputted
+  *          This parameter can be one of the following values:
+  *            @arg RCC_PLL3_DIVP: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
+  *            @arg RCC_PLL3_DIVQ: This clock is used to generate peripherals clock  up to 400MHZ or 280MHZ(*)
+  *            @arg RCC_PLL3_DIVR: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
+  *
+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  *
+  * @retval None
+  */
+#define __HAL_RCC_PLL3CLKOUT_ENABLE(__RCC_PLL3ClockOut__)   SET_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))
+
+#define __HAL_RCC_PLL3CLKOUT_DISABLE(__RCC_PLL3ClockOut__)  CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))
+
+/**
+  * @brief  Macro to configures the PLL3  multiplication and division factors.
+  * @note   This function must be used only when PLL3 is disabled.
+  *
+  * @param  __PLL3M__ specifies the division factor for PLL3 VCO input clock
+  *          This parameter must be a number between 1 and 63.
+  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
+  *         frequency ranges from 1 to 16 MHz.
+  *
+  * @param  __PLL3N__ specifies the multiplication factor for PLL3 VCO output clock
+  *          This parameter must be a number between 4 and 512.
+  * @note   You have to set the PLL3N parameter correctly to ensure that the VCO
+  *         output frequency is between 150 and 420 MHz (when in medium VCO range) or
+  *         between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range)
+  *
+  * @param  __PLL3P__ specifies the division factor for peripheral kernel clocks
+  *          This parameter must be a number between 2 and 128 (where odd numbers not allowed)
+  *
+  * @param  __PLL3Q__ specifies the division factor for peripheral kernel clocks
+  *          This parameter must be a number between 1 and 128
+  *
+  * @param  __PLL3R__ specifies the division factor for peripheral kernel clocks
+  *          This parameter must be a number between 1 and 128
+  *
+  * @note   To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR)
+  *         is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible
+  *         value to  __PLL3P__, __PLL3Q__ or __PLL3R__ parameters.
+  * @retval None
+  *
+  *  (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  */
+
+#define __HAL_RCC_PLL3_CONFIG(__PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__,__PLL3R__ ) \
+                  do{ MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM3) , ( (__PLL3M__) <<20U));  \
+                         WRITE_REG (RCC->PLL3DIVR , ( (((__PLL3N__) - 1U ) & RCC_PLL3DIVR_N3) | ((((__PLL3P__) -1U ) << 9U) & RCC_PLL3DIVR_P3) | \
+                                   ((((__PLL3Q__) -1U) << 16U) & RCC_PLL3DIVR_Q3) | ((((__PLL3R__) - 1U) << 24U) & RCC_PLL3DIVR_R3))); \
+                       } while(0)
+
+
+
+/**
+  * @brief  Macro to configures  PLL3 clock Fractional Part of The Multiplication Factor
+  *
+  * @note   These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO
+  *
+  * @param  __RCC_PLL3FRACN__ specifies Fractional Part Of The Multiplication Factor for PLL3 VCO
+  *                            It should be a value between 0 and 8191
+  * @note   Warning: the software has to set correctly these bits to insure that the VCO
+  *                  output frequency is between its valid frequency range, which is:
+  *                  192 to 836 MHz or 128 to 560 MHz(*) if PLL3VCOSEL = 0
+  *                  150 to 420 MHz if PLL3VCOSEL = 1.
+  *
+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  *
+  * @retval None
+  */
+ #define  __HAL_RCC_PLL3FRACN_CONFIG(__RCC_PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << RCC_PLL3FRACR_FRACN3_Pos)
+
+/** @brief  Macro to select  the PLL3  reference frequency range.
+  * @param  __RCC_PLL3VCIRange__ specifies the PLL1 input frequency range
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PLL3VCIRANGE_0: Range frequency is between 1 and 2 MHz
+  *            @arg RCC_PLL3VCIRANGE_1: Range frequency is between 2 and 4 MHz
+  *            @arg RCC_PLL3VCIRANGE_2: Range frequency is between 4 and 8 MHz
+  *            @arg RCC_PLL3VCIRANGE_3: Range frequency is between 8 and 16 MHz
+  * @retval None
+  */
+#define __HAL_RCC_PLL3_VCIRANGE(__RCC_PLL3VCIRange__) \
+                  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, (__RCC_PLL3VCIRange__))
+
+
+/** @brief  Macro to select  the PLL3  reference frequency range.
+  * @param  __RCC_PLL3VCORange__ specifies the PLL1 input frequency range
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PLL3VCOWIDE: Range frequency is between 192 and 836 MHz  or between 128 to 560 MHz(*)
+  *            @arg RCC_PLL3VCOMEDIUM: Range frequency is between 150 and 420 MHz
+  *
+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  *
+  * @retval None
+  */
+#define __HAL_RCC_PLL3_VCORANGE(__RCC_PLL3VCORange__) \
+                  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__))
+/**
+  * @brief  Macro to Configure the SAI1 clock source.
+  * @param  __RCC_SAI1CLKSource__ defines the SAI1 clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL
+  *             @arg RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2
+  *             @arg RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3
+  *             @arg RCC_SAI1CLKSOURCE_OSC: SAI1 clock  = OSC
+  *             @arg RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock
+  * @retval None
+  */
+#if defined(RCC_D2CCIP1R_SAI1SEL)
+#define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__ )\
+                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__))
+#else
+#define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__ )\
+                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__))
+#endif /* RCC_D2CCIP1R_SAI1SEL */
+
+/** @brief  Macro to get the SAI1 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL
+  *             @arg RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2
+  *             @arg RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3
+  *             @arg RCC_SAI1CLKSOURCE_CLKP: SAI1 clock  = CLKP
+  *             @arg RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock
+  */
+#if defined(RCC_D2CCIP1R_SAI1SEL)
+#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL)))
+#else
+#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL)))
+#endif /* RCC_D2CCIP1R_SAI1SEL */
+
+/**
+  * @brief  Macro to Configure the SPDIFRX clock source.
+  * @param  __RCC_SPDIFCLKSource__ defines the SPDIFRX clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3,  or internal OSC clock
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SPDIFRXCLKSOURCE_PLL:  SPDIFRX clock = PLL
+  *             @arg RCC_SPDIFRXCLKSOURCE_PLL2: SPDIFRX clock = PLL2
+  *             @arg RCC_SPDIFRXCLKSOURCE_PLL3: SPDIFRX clock = PLL3
+  *             @arg RCC_SPDIFRXCLKSOURCE_HSI:  SPDIFRX clock  = HSI
+  * @retval None
+  */
+#if defined(RCC_D2CCIP1R_SPDIFSEL)
+#define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__ )\
+                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__))
+#else
+#define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__ )\
+                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__))
+#endif /* RCC_D2CCIP1R_SPDIFSEL */
+
+/**
+  * @brief  Macro to get the SPDIFRX clock source.
+  * @retval None
+  */
+#if defined(RCC_D2CCIP1R_SPDIFSEL)
+#define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL)))
+#else
+#define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL)))
+#endif /* RCC_D2CCIP1R_SPDIFSEL */
+
+#if defined(SAI3)
+/**
+  * @brief  Macro to Configure the SAI2/3 clock source.
+  * @param  __RCC_SAI23CLKSource__ defines the SAI2/3 clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SAI23CLKSOURCE_PLL: SAI2/3 clock = PLL
+  *             @arg RCC_SAI23CLKSOURCE_PLL2: SAI2/3 clock = PLL2
+  *             @arg RCC_SAI23CLKSOURCE_PLL3: SAI2/3 clock = PLL3
+  *             @arg RCC_SAI23CLKSOURCE_CLKP: SAI2/3 clock  = CLKP
+  *             @arg RCC_SAI23CLKSOURCE_PIN: SAI2/3 clock = External Clock
+  * @retval None
+  */
+#define __HAL_RCC_SAI23_CONFIG(__RCC_SAI23CLKSource__ )\
+                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL, (__RCC_SAI23CLKSource__))
+
+/** @brief  Macro to get the SAI2/3 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SAI23CLKSOURCE_PLL: SAI2/3 clock = PLL
+  *             @arg RCC_SAI23CLKSOURCE_PLL2: SAI2/3 clock = PLL2
+  *             @arg RCC_SAI23CLKSOURCE_PLL3: SAI2/3 clock = PLL3
+  *             @arg RCC_SAI23CLKSOURCE_CLKP: SAI2/3 clock  = CLKP
+  *             @arg RCC_SAI23CLKSOURCE_PIN: SAI2/3 clock = External Clock
+  */
+#define __HAL_RCC_GET_SAI23_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL)))
+
+/**
+  * @brief  Macro to Configure the SAI2 clock source.
+  * @param  __RCC_SAI2CLKSource__ defines the SAI2 clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SAI2CLKSOURCE_PLL: SAI2 clock = PLL
+  *             @arg RCC_SAI2CLKSOURCE_PLL2: SAI2 clock = PLL2
+  *             @arg RCC_SAI2CLKSOURCE_PLL3: SAI2 clock = PLL3
+  *             @arg RCC_SAI2CLKSOURCE_CLKP: SAI2 clock  = CLKP
+  *             @arg RCC_SAI2CLKSOURCE_PIN: SAI2 clock = External Clock
+  * @retval None
+  */
+#define __HAL_RCC_SAI2_CONFIG  __HAL_RCC_SAI23_CONFIG
+
+/** @brief  Macro to get the SAI2 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SAI2CLKSOURCE_PLL: SAI2 clock = PLL
+  *             @arg RCC_SAI2CLKSOURCE_PLL2: SAI2 clock = PLL2
+  *             @arg RCC_SAI2CLKSOURCE_PLL3: SAI2 clock = PLL3
+  *             @arg RCC_SAI2CLKSOURCE_CLKP: SAI2 clock  = CLKP
+  *             @arg RCC_SAI2CLKSOURCE_PIN: SAI2 clock = External Clock
+  */
+#define __HAL_RCC_GET_SAI2_SOURCE  __HAL_RCC_GET_SAI23_SOURCE
+
+/**
+  * @brief  Macro to Configure the SAI3 clock source.
+  * @param  __RCC_SAI3CLKSource__ defines the SAI3 clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SAI3CLKSOURCE_PLL: SAI3 clock = PLL
+  *             @arg RCC_SAI3CLKSOURCE_PLL2: SAI3 clock = PLL2
+  *             @arg RCC_SAI3CLKSOURCE_PLL3: SAI3 clock = PLL3
+  *             @arg RCC_SAI3CLKSOURCE_CLKP: SAI3 clock  = CLKP
+  *             @arg RCC_SAI3CLKSOURCE_PIN: SAI3 clock = External Clock
+  * @retval None
+  */
+#define __HAL_RCC_SAI3_CONFIG __HAL_RCC_SAI23_CONFIG
+
+/** @brief  Macro to get the SAI3 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SAI3CLKSOURCE_PLL: SAI3 clock = PLL
+  *             @arg RCC_SAI3CLKSOURCE_PLL2: SAI3 clock = PLL2
+  *             @arg RCC_SAI3CLKSOURCE_PLL3: SAI3 clock = PLL3
+  *             @arg RCC_SAI3CLKSOURCE_CLKP: SAI3 clock  = CLKP
+  *             @arg RCC_SAI3CLKSOURCE_PIN: SAI3 clock = External Clock
+  */
+#define __HAL_RCC_GET_SAI3_SOURCE  __HAL_RCC_GET_SAI23_SOURCE
+#endif /* SAI3 */
+
+#if defined(RCC_CDCCIP1R_SAI2ASEL)
+/**
+  * @brief  Macro to Configure the SAI2A clock source.
+  * @param  __RCC_SAI2ACLKSource__ defines the SAI2A clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SAI2ACLKSOURCE_PLL: SAI2A clock = PLL
+  *             @arg RCC_SAI2ACLKSOURCE_PLL2: SAI2A clock = PLL2
+  *             @arg RCC_SAI2ACLKSOURCE_PLL3: SAI2A clock = PLL3
+  *             @arg RCC_SAI2ACLKSOURCE_CLKP: SAI2A clock  = CLKP
+  *             @arg RCC_SAI2ACLKSOURCE_PIN: SAI2A clock = External Clock
+  *             @arg RCC_SAI2ACLKSOURCE_SPDIF: SAI2A clock = SPDIF Clock
+  * @retval None
+  */
+#define __HAL_RCC_SAI2A_CONFIG(__RCC_SAI2ACLKSource__ )\
+                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2ASEL, (__RCC_SAI2ACLKSource__))
+
+/** @brief  Macro to get the SAI2A clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SAI2CLKSOURCE_PLL: SAI2A clock = PLL
+  *             @arg RCC_SAI2CLKSOURCE_PLL2: SAI2A clock = PLL2
+  *             @arg RCC_SAI2CLKSOURCE_PLL3: SAI2A clock = PLL3
+  *             @arg RCC_SAI2CLKSOURCE_CLKP: SAI2A clock  = CLKP
+  *             @arg RCC_SAI2CLKSOURCE_PIN: SAI2A clock = External Clock
+  *             @arg RCC_SAI2ACLKSOURCE_SPDIF: SAI2A clock = SPDIF Clock
+  */
+#define __HAL_RCC_GET_SAI2A_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2ASEL)))
+#endif /* defined(RCC_CDCCIP1R_SAI2ASEL) */
+
+#if defined(RCC_CDCCIP1R_SAI2BSEL)
+/**
+  * @brief  Macro to Configure the SAI2B clock source.
+  * @param  __RCC_SAI2BCLKSource__ defines the SAI2B clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SAI2BCLKSOURCE_PLL: SAI2B clock = PLL
+  *             @arg RCC_SAI2BCLKSOURCE_PLL2: SAI2B clock = PLL2
+  *             @arg RCC_SAI2BCLKSOURCE_PLL3: SAI2B clock = PLL3
+  *             @arg RCC_SAI2BCLKSOURCE_CLKP: SAI2B clock  = CLKP
+  *             @arg RCC_SAI2BCLKSOURCE_PIN: SAI2B clock = External Clock
+  *             @arg RCC_SAI2BCLKSOURCE_SPDIF: SAI2B clock = SPDIF Clock
+  * @retval None
+  */
+#define __HAL_RCC_SAI2B_CONFIG(__RCC_SAI2BCLKSource__ )\
+                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2BSEL, (__RCC_SAI2BCLKSource__))
+
+/** @brief  Macro to get the SAI2B clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SAI2BCLKSOURCE_PLL: SAI2B clock = PLL
+  *             @arg RCC_SAI2BCLKSOURCE_PLL2: SAI2B clock = PLL2
+  *             @arg RCC_SAI2BCLKSOURCE_PLL3: SAI2B clock = PLL3
+  *             @arg RCC_SAI2BCLKSOURCE_CLKP: SAI2B clock  = CLKP
+  *             @arg RCC_SAI2BCLKSOURCE_PIN: SAI2B clock = External Clock
+  *             @arg RCC_SAI2BCLKSOURCE_SPDIF: SAI2B clock = SPDIF Clock
+  */
+#define __HAL_RCC_GET_SAI2B_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2BSEL)))
+#endif /* defined(RCC_CDCCIP1R_SAI2BSEL) */
+
+
+#if defined(SAI4_Block_A)
+/**
+  * @brief  Macro to Configure the SAI4A clock source.
+  * @param  __RCC_SAI4ACLKSource__ defines the SAI4A clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SAI4ACLKSOURCE_PLL: SAI4A clock = PLL
+  *             @arg RCC_SAI4ACLKSOURCE_PLL2: SAI4A clock = PLL2
+  *             @arg RCC_SAI4ACLKSOURCE_PLL3: SAI4A clock = PLL3
+  *             @arg RCC_SAI4ACLKSOURCE_CLKP: SAI4A clock  = CLKP
+  *             @arg RCC_SAI4ACLKSOURCE_PIN: SAI4A clock = External Clock
+  * @retval None
+  */
+#define __HAL_RCC_SAI4A_CONFIG(__RCC_SAI4ACLKSource__ )\
+                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL, (__RCC_SAI4ACLKSource__))
+
+/** @brief  Macro to get the SAI4A clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SAI4ACLKSOURCE_PLL: SAI4B clock = PLL
+  *             @arg RCC_SAI4ACLKSOURCE_PLL2: SAI4B clock = PLL2
+  *             @arg RCC_SAI4ACLKSOURCE_PLL3: SAI4B clock = PLL3
+  *             @arg RCC_SAI4ACLKSOURCE_CLKP: SAI4B clock  = CLKP
+  *             @arg RCC_SAI4ACLKSOURCE_PIN: SAI4B clock = External Clock
+  */
+#define __HAL_RCC_GET_SAI4A_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL)))
+#endif /* SAI4_Block_A */
+
+#if defined(SAI4_Block_B)
+/**
+  * @brief  Macro to Configure the SAI4B clock source.
+  * @param  __RCC_SAI4BCLKSource__ defines the SAI4B clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SAI4BCLKSOURCE_PLL: SAI4B clock = PLL
+  *             @arg RCC_SAI4BCLKSOURCE_PLL2: SAI4B clock = PLL2
+  *             @arg RCC_SAI4BCLKSOURCE_PLL3: SAI4B clock = PLL3
+  *             @arg RCC_SAI4BCLKSOURCE_CLKP: SAI4B clock  = CLKP
+  *             @arg RCC_SAI4BCLKSOURCE_PIN: SAI4B clock = External Clock
+  * @retval None
+  */
+#define __HAL_RCC_SAI4B_CONFIG(__RCC_SAI4BCLKSource__ )\
+                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL, (__RCC_SAI4BCLKSource__))
+
+/** @brief  Macro to get the SAI4B clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SAI4BCLKSOURCE_PLL: SAI4B clock = PLL
+  *             @arg RCC_SAI4BCLKSOURCE_PLL2: SAI4B clock = PLL2
+  *             @arg RCC_SAI4BCLKSOURCE_PLL3: SAI4B clock = PLL3
+  *             @arg RCC_SAI4BCLKSOURCE_CLKP: SAI4B clock  = CLKP
+  *             @arg RCC_SAI4BCLKSOURCE_PIN: SAI4B clock = External Clock
+  */
+#define __HAL_RCC_GET_SAI4B_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL)))
+#endif /* SAI4_Block_B */
+
+/** @brief macro to configure the I2C1/2/3 clock (I2C123CLK).
+  *
+  * @param  __I2C123CLKSource__ specifies the I2C1/2/3 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3 clock
+  *            @arg RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3 clock
+  *            @arg RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3 clock
+  *            @arg RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3 clock
+  */
+#if defined(RCC_D2CCIP2R_I2C123SEL)
+#define __HAL_RCC_I2C123_CONFIG(__I2C123CLKSource__) \
+                  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C123CLKSource__))
+#else
+#define __HAL_RCC_I2C123_CONFIG(__I2C123CLKSource__) \
+                  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_I2C123SEL, (uint32_t)(__I2C123CLKSource__))
+#endif /* RCC_D2CCIP2R_I2C123SEL */
+
+/** @brief  macro to get the I2C1/2/3 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3 clock
+  *            @arg RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3 clock
+  *            @arg RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3 clock
+  *            @arg RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3 clock
+  */
+#if defined(RCC_D2CCIP2R_I2C123SEL)
+#define __HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL)))
+#else
+#define __HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_I2C123SEL)))
+#endif /* RCC_D2CCIP2R_I2C123SEL */
+
+/** @brief macro to configure the I2C1 clock (I2C1CLK).
+  *
+  * @param  __I2C1CLKSource__ specifies the I2C1 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock
+  *            @arg RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock
+  *            @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
+  *            @arg RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock
+  */
+#define __HAL_RCC_I2C1_CONFIG  __HAL_RCC_I2C123_CONFIG
+
+/** @brief  macro to get the I2C1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock
+  *            @arg RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock
+  *            @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
+  *            @arg RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock
+  */
+#define __HAL_RCC_GET_I2C1_SOURCE __HAL_RCC_GET_I2C123_SOURCE
+
+/** @brief macro to configure the I2C2 clock (I2C2CLK).
+  *
+  * @param  __I2C2CLKSource__ specifies the I2C2 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock
+  *            @arg RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock
+  *            @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
+  *            @arg RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock
+  */
+#define __HAL_RCC_I2C2_CONFIG __HAL_RCC_I2C123_CONFIG
+
+/** @brief  macro to get the I2C2 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock
+  *            @arg RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock
+  *            @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
+  *            @arg RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock
+  */
+#define __HAL_RCC_GET_I2C2_SOURCE __HAL_RCC_GET_I2C123_SOURCE
+
+/** @brief macro to configure the I2C3 clock (I2C3CLK).
+  *
+  * @param  __I2C3CLKSource__ specifies the I2C3 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock
+  *            @arg RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock
+  *            @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
+  *            @arg RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock
+  */
+#define __HAL_RCC_I2C3_CONFIG __HAL_RCC_I2C123_CONFIG
+
+/** @brief  macro to get the I2C3 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock
+  *            @arg RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock
+  *            @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
+  *            @arg RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock
+  */
+#define __HAL_RCC_GET_I2C3_SOURCE __HAL_RCC_GET_I2C123_SOURCE
+
+/** @brief macro to configure the I2C4 clock (I2C4CLK).
+  *
+  * @param  __I2C4CLKSource__ specifies the I2C4 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock
+  *            @arg RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock
+  *            @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
+  *            @arg RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock
+  */
+#if defined(RCC_D3CCIPR_I2C4SEL)
+#define __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) \
+                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__))
+#else
+#define __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) \
+                  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__))
+#endif /* RCC_D3CCIPR_I2C4SEL */
+
+/** @brief  macro to get the I2C4 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock
+  *            @arg RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock
+  *            @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
+  *            @arg RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock
+  */
+#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL)))
+
+/** @brief macro to configure the USART1/6/9* /10* clock (USART16CLK).
+  *
+  * @param  __USART16CLKSource__ specifies the USART1/6/9* /10* clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6/9* /10* clock
+  *            @arg RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6/9* /10* clock
+  *            @arg RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6/9* /10* clock
+  *            @arg RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6/9* /10* clock
+  *            @arg RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6/9* /10* clock
+  *            @arg RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6/9* /10* clock
+  *
+  * (*) : Available on some STM32H7 lines only.
+  */
+#if defined(RCC_D2CCIP2R_USART16SEL)
+#define __HAL_RCC_USART16_CONFIG(__USART16CLKSource__) \
+                  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART16CLKSource__))
+#else
+#define __HAL_RCC_USART16910_CONFIG(__USART16910CLKSource__) \
+                  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART16910SEL, (uint32_t)(__USART16910CLKSource__))
+/* alias */
+#define __HAL_RCC_USART16_CONFIG  __HAL_RCC_USART16910_CONFIG
+#endif /* RCC_D2CCIP2R_USART16SEL */
+
+/** @brief  macro to get the USART1/6/9* /10* clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6/9* /10* clock
+  *            @arg RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6/9* /10* clock
+  *            @arg RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6/9* /10* clock
+  *            @arg RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6/9* /10* clock
+  *            @arg RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6/9* /10* clock
+  *            @arg RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6/9* /10* clock
+  *
+  * (*) : Available on some STM32H7 lines only.
+  */
+#if defined(RCC_D2CCIP2R_USART16SEL)
+#define __HAL_RCC_GET_USART16_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL)))
+#else
+#define __HAL_RCC_GET_USART16910_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART16910SEL)))
+/* alias*/
+#define  __HAL_RCC_GET_USART16_SOURCE  __HAL_RCC_GET_USART16910_SOURCE
+#endif /* RCC_D2CCIP2R_USART16SEL */
+
+/** @brief macro to configure the USART234578 clock (USART234578CLK).
+  *
+  * @param  __USART234578CLKSource__ specifies the USART2/3/4/5/7/8 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock
+  *            @arg RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock
+  *            @arg RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock
+  *            @arg RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock
+  *            @arg RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock
+  *            @arg RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock
+  */
+#if defined(RCC_D2CCIP2R_USART28SEL)
+#define __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) \
+                  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART234578CLKSource__))
+#else
+#define __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) \
+                  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL, (uint32_t)(__USART234578CLKSource__))
+#endif /* RCC_D2CCIP2R_USART28SEL */
+
+/** @brief  macro to get the USART2/3/4/5/7/8 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock
+  *            @arg RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock
+  *            @arg RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock
+  *            @arg RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock
+  *            @arg RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock
+  *            @arg RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock
+  */
+#if defined(RCC_D2CCIP2R_USART28SEL)
+#define __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
+#else
+#define __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL)))
+#endif /* RCC_D2CCIP2R_USART28SEL */
+
+/** @brief macro to configure the USART1 clock (USART1CLK).
+  *
+  * @param  __USART1CLKSource__ specifies the USART1 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
+  */
+#define __HAL_RCC_USART1_CONFIG  __HAL_RCC_USART16_CONFIG
+
+/** @brief  macro to get the USART1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
+  */
+#define __HAL_RCC_GET_USART1_SOURCE  __HAL_RCC_GET_USART16_SOURCE
+
+/** @brief macro to configure the USART2 clock (USART2CLK).
+  *
+  * @param  __USART2CLKSource__ specifies the USART2 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
+  */
+#define __HAL_RCC_USART2_CONFIG  __HAL_RCC_USART234578_CONFIG
+
+/** @brief  macro to get the USART2 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
+  */
+#define __HAL_RCC_GET_USART2_SOURCE __HAL_RCC_GET_USART234578_SOURCE
+
+/** @brief macro to configure the USART3 clock (USART3CLK).
+  *
+  * @param  __USART3CLKSource__ specifies the USART3 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_USART3CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
+  */
+#define __HAL_RCC_USART3_CONFIG  __HAL_RCC_USART234578_CONFIG
+
+/** @brief  macro to get the USART3 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
+  */
+#define __HAL_RCC_GET_USART3_SOURCE  __HAL_RCC_GET_USART234578_SOURCE
+
+/** @brief macro to configure the UART4 clock (UART4CLK).
+  *
+  * @param  __UART4CLKSource__ specifies the UART4 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
+  */
+#define __HAL_RCC_UART4_CONFIG  __HAL_RCC_USART234578_CONFIG
+
+/** @brief  macro to get the UART4 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
+  */
+#define __HAL_RCC_GET_UART4_SOURCE  __HAL_RCC_GET_USART234578_SOURCE
+
+/** @brief macro to configure the UART5 clock (UART5CLK).
+  *
+  * @param  __UART5CLKSource__ specifies the UART5 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
+  */
+#define __HAL_RCC_UART5_CONFIG  __HAL_RCC_USART234578_CONFIG
+
+/** @brief  macro to get the UART5 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
+  */
+#define __HAL_RCC_GET_UART5_SOURCE  __HAL_RCC_GET_USART234578_SOURCE
+
+/** @brief macro to configure the USART6 clock (USART6CLK).
+  *
+  * @param  __USART6CLKSource__ specifies the USART6 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
+  */
+#define __HAL_RCC_USART6_CONFIG  __HAL_RCC_USART16_CONFIG
+
+/** @brief  macro to get the USART6 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
+  */
+#define __HAL_RCC_GET_USART6_SOURCE  __HAL_RCC_GET_USART16_SOURCE
+
+/** @brief macro to configure the UART5 clock (UART7CLK).
+  *
+  * @param  __UART7CLKSource__ specifies the UART7 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
+  */
+#define __HAL_RCC_UART7_CONFIG  __HAL_RCC_USART234578_CONFIG
+
+/** @brief  macro to get the UART7 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
+  */
+#define __HAL_RCC_GET_UART7_SOURCE  __HAL_RCC_GET_USART234578_SOURCE
+
+/** @brief macro to configure the UART8 clock (UART8CLK).
+  *
+  * @param  __UART8CLKSource__ specifies the UART8 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
+  */
+#define __HAL_RCC_UART8_CONFIG  __HAL_RCC_USART234578_CONFIG
+
+/** @brief  macro to get the UART8 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
+  */
+#define __HAL_RCC_GET_UART8_SOURCE  __HAL_RCC_GET_USART234578_SOURCE
+
+#if defined(UART9)
+/** @brief macro to configure the UART9 clock (UART9CLK).
+  *
+  * @param  __UART8CLKSource__ specifies the UART8 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_UART9CLKSOURCE_D2PCLK1: APB1 Clock selected as UART9 clock
+  *            @arg RCC_UART9CLKSOURCE_PLL2: PLL2_Q Clock selected as UART9 clock
+  *            @arg RCC_UART9CLKSOURCE_PLL3: PLL3_Q Clock selected as UART9 clock
+  *            @arg RCC_UART9CLKSOURCE_HSI: HSI selected as UART9 clock
+  *            @arg RCC_UART9CLKSOURCE_CSI: CSI Clock selected as UART9 clock
+  *            @arg RCC_UART9CLKSOURCE_LSE: LSE selected as UART9 clock
+  */
+#define __HAL_RCC_UART9_CONFIG  __HAL_RCC_USART16_CONFIG
+
+/** @brief  macro to get the UART9 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_UART9CLKSOURCE_D2PCLK1: APB1 Clock selected as UART99 clock
+  *            @arg RCC_UART9CLKSOURCE_PLL2: PLL2_Q Clock selected as UART99 clock
+  *            @arg RCC_UART9CLKSOURCE_PLL3: PLL3_Q Clock selected as UART99 clock
+  *            @arg RCC_UART9CLKSOURCE_HSI: HSI selected as UART9 clock
+  *            @arg RCC_UART9CLKSOURCE_CSI: CSI Clock selected as UART9 clock
+  *            @arg RCC_UART9CLKSOURCE_LSE: LSE selected as UART9 clock
+  */
+#define __HAL_RCC_GET_UART9_SOURCE  __HAL_RCC_GET_USART16_SOURCE
+#endif /* UART9 */
+
+#if defined(USART10)
+/** @brief macro to configure the USART10 clock (USART10CLK).
+  *
+  * @param  __UART8CLKSource__ specifies the UART8 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_USART10CLKSOURCE_D2PCLK1: APB1 Clock selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_PLL2: PLL2_Q Clock selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_PLL3: PLL3_Q Clock selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_HSI: HSI selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_CSI: CSI Clock selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_LSE: LSE selected as USART10 clock
+  */
+#define __HAL_RCC_USART10_CONFIG  __HAL_RCC_USART16_CONFIG
+
+/** @brief  macro to get the USART10 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_USART10CLKSOURCE_D2PCLK1: APB1 Clock selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_PLL2: PLL2_Q Clock selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_PLL3: PLL3_Q Clock selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_HSI: HSI selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_CSI: CSI Clock selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_LSE: LSE selected as USART10 clock
+  */
+#define __HAL_RCC_GET_USART10_SOURCE  __HAL_RCC_GET_USART16_SOURCE
+#endif /* USART10 */
+
+/** @brief macro to configure the LPUART1 clock (LPUART1CLK).
+  *
+  * @param  __LPUART1CLKSource__ specifies the LPUART1 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock
+  */
+#if defined (RCC_D3CCIPR_LPUART1SEL)
+#define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \
+                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))
+#else
+#define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \
+                  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))
+#endif /* RCC_D3CCIPR_LPUART1SEL */
+
+/** @brief  macro to get the LPUART1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock
+  */
+#if defined (RCC_D3CCIPR_LPUART1SEL)
+#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL)))
+#else
+#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL)))
+#endif /* RCC_D3CCIPR_LPUART1SEL */
+
+/** @brief  macro to configure the LPTIM1 clock source.
+  *
+  * @param  __LPTIM1CLKSource__ specifies the LPTIM1 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock
+  */
+#if defined(RCC_D2CCIP2R_LPTIM1SEL)
+#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \
+                  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))
+#else
+#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \
+                  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))
+#endif /* RCC_D2CCIP2R_LPTIM1SEL */
+
+/** @brief  macro to get the LPTIM1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock
+  */
+#if defined(RCC_D2CCIP2R_LPTIM1SEL)
+#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL)))
+#else
+#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL)))
+#endif /* RCC_D2CCIP2R_LPTIM1SEL */
+
+/** @brief  macro to configure the LPTIM2 clock source.
+  *
+  * @param  __LPTIM2CLKSource__ specifies the LPTIM2 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock
+  */
+#if defined(RCC_D3CCIPR_LPTIM2SEL)
+#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) \
+                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__))
+#else
+#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) \
+                  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__))
+#endif /* RCC_D3CCIPR_LPTIM2SEL */
+
+/** @brief  macro to get the LPTIM2 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock
+  */
+#if defined(RCC_D3CCIPR_LPTIM2SEL)
+#define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL)))
+#else
+#define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL)))
+#endif /* RCC_D3CCIPR_LPTIM2SEL */
+
+/** @brief  macro to configure the LPTIM3/4/5 clock source.
+  *
+  * @param  __LPTIM345CLKSource__ specifies the LPTIM3/4/5 clock source.
+  *            @arg RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock
+  *            @arg RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock
+  *            @arg RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock
+  *            @arg RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock
+  *            @arg RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock
+  *            @arg RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock
+  */
+#if defined(RCC_D3CCIPR_LPTIM345SEL)
+#define __HAL_RCC_LPTIM345_CONFIG(__LPTIM345CLKSource__) \
+                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM345CLKSource__))
+#else
+#define __HAL_RCC_LPTIM345_CONFIG(__LPTIM3CLKSource__) \
+                  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL, (uint32_t)(__LPTIM3CLKSource__))
+#endif /* RCC_D3CCIPR_LPTIM345SEL */
+
+/** @brief  macro to get the LPTIM3/4/5 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock
+  *            @arg RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock
+  *            @arg RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock
+  *            @arg RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock
+  *            @arg RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock
+  *            @arg RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock
+  */
+#if defined(RCC_D3CCIPR_LPTIM345SEL)
+#define __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL)))
+#else
+#define __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL)))
+#endif /* RCC_D3CCIPR_LPTIM345SEL */
+
+/** @brief  macro to configure the LPTIM3 clock source.
+  *
+  * @param  __LPTIM3CLKSource__ specifies the LPTIM3 clock source.
+  *            @arg RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock
+  */
+#define __HAL_RCC_LPTIM3_CONFIG  __HAL_RCC_LPTIM345_CONFIG
+
+/** @brief  macro to get the LPTIM3 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock
+  */
+#define __HAL_RCC_GET_LPTIM3_SOURCE  __HAL_RCC_GET_LPTIM345_SOURCE
+
+#if defined(LPTIM4)
+/** @brief  macro to configure the LPTIM4 clock source.
+  *
+  * @param  __LPTIM4CLKSource__ specifies the LPTIM4 clock source.
+  *            @arg RCC_LPTIM4CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_LSE: LSE selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_LSI: LSI Clock selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_CLKP: CLKP selected as LPTIM4 clock
+  */
+#define __HAL_RCC_LPTIM4_CONFIG  __HAL_RCC_LPTIM345_CONFIG
+
+
+/** @brief  macro to get the LPTIM4 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_LPTIM4CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_LSE: LSE selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_LSI: LSI Clock selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_CLKP: CLKP selected as LPTIM4 clock
+  */
+#define __HAL_RCC_GET_LPTIM4_SOURCE  __HAL_RCC_GET_LPTIM345_SOURCE
+#endif /* LPTIM4 */
+
+#if defined(LPTIM5)
+/** @brief  macro to configure the LPTIM5 clock source.
+  *
+  * @param  __LPTIM5CLKSource__ specifies the LPTIM5 clock source.
+  *            @arg RCC_LPTIM5CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_LSE: LSE selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_LSI: LSI Clock selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_CLKP: CLKP selected as LPTIM5 clock
+  */
+#define __HAL_RCC_LPTIM5_CONFIG  __HAL_RCC_LPTIM345_CONFIG
+
+
+/** @brief  macro to get the LPTIM5 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_LPTIM5CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_LSE: LSE selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_LSI: LSI Clock selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_CLKP: CLKP selected as LPTIM5 clock
+  */
+#define __HAL_RCC_GET_LPTIM5_SOURCE  __HAL_RCC_GET_LPTIM345_SOURCE
+#endif /* LPTIM5 */
+
+#if defined(QUADSPI)
+/** @brief  macro to configure the QSPI clock source.
+  *
+  * @param  __QSPICLKSource__ specifies the QSPI clock source.
+  *            @arg RCC_RCC_QSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as QSPI clock
+  *            @arg RCC_RCC_QSPICLKSOURCE_PLL   : PLL1_Q Clock selected as QSPI clock
+  *            @arg RCC_RCC_QSPICLKSOURCE_PLL2  : PLL2_R Clock selected as QSPI clock
+  *            @arg RCC_RCC_QSPICLKSOURCE_CLKP    CLKP selected as QSPI clock
+  */
+#define __HAL_RCC_QSPI_CONFIG(__QSPICLKSource__) \
+                  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL, (uint32_t)(__QSPICLKSource__))
+
+
+/** @brief  macro to get the QSPI clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_RCC_QSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as QSPI clock
+  *            @arg RCC_RCC_QSPICLKSOURCE_PLL   : PLL1_Q Clock selected as QSPI clock
+  *            @arg RCC_RCC_QSPICLKSOURCE_PLL2  : PLL2_R Clock selected as QSPI clock
+  *            @arg RCC_RCC_QSPICLKSOURCE_CLKP    CLKP selected as QSPI clock
+  */
+#define __HAL_RCC_GET_QSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL)))
+#endif /* QUADSPI */
+
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+/** @brief  macro to configure the OSPI clock source.
+  *
+  * @param  __OSPICLKSource__ specifies the OSPI clock source.
+  *            @arg RCC_RCC_OSPICLKSOURCE_CDHCLK: Domain1 HCLK Clock selected as OSPI clock
+  *            @arg RCC_RCC_OSPICLKSOURCE_PLL   : PLL1_Q Clock selected as OSPI clock
+  *            @arg RCC_RCC_OSPICLKSOURCE_PLL2  : PLL2_R Clock selected as OSPI clock
+  *            @arg RCC_RCC_OSPICLKSOURCE_CLKP    CLKP selected as OSPI clock
+  */
+#define __HAL_RCC_OSPI_CONFIG(__OSPICLKSource__) \
+                  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL, (uint32_t)(__OSPICLKSource__))
+
+
+/** @brief  macro to get the OSPI clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_RCC_OSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as OSPI clock
+  *            @arg RCC_RCC_OSPICLKSOURCE_PLL   : PLL1_Q Clock selected as OSPI clock
+  *            @arg RCC_RCC_OSPICLKSOURCE_PLL2  : PLL2_R Clock selected as OSPI clock
+  *            @arg RCC_RCC_OSPICLKSOURCE_CLKP    CLKP selected as OSPI clock
+  */
+#define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL)))
+#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
+
+
+#if defined(DSI)
+/** @brief  macro to configure the DSI clock source.
+  *
+  * @param  __DSICLKSource__ specifies the DSI clock source.
+  *            @arg RCC_RCC_DSICLKSOURCE_PHY:DSI clock from PHY is selected as DSI byte lane clock
+  *            @arg RCC_RCC_DSICLKSOURCE_PLL2   : PLL2_Q Clock clock is selected as DSI byte lane clock
+  */
+#define __HAL_RCC_DSI_CONFIG(__DSICLKSource__) \
+                  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL, (uint32_t)(__DSICLKSource__))
+
+
+/** @brief  macro to get the DSI clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_RCC_DSICLKSOURCE_PHY: DSI clock from PHY is selected as DSI byte lane clock
+  *            @arg RCC_RCC_DSICLKSOURCE_PLL2: PLL2_Q Clock clock is selected as DSI byte lane clock
+  */
+#define __HAL_RCC_GET_DSI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL)))
+#endif /*DSI*/
+
+/** @brief  macro to configure the FMC clock source.
+  *
+  * @param  __FMCCLKSource__ specifies the FMC clock source.
+  *            @arg RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock
+  *            @arg RCC_RCC_FMCCLKSOURCE_PLL   : PLL1_Q Clock selected as FMC clock
+  *            @arg RCC_RCC_FMCCLKSOURCE_PLL2  : PLL2_R Clock selected as FMC clock
+  *            @arg RCC_RCC_FMCCLKSOURCE_CLKP    CLKP selected as FMC clock
+  */
+#if defined(RCC_D1CCIPR_FMCSEL)
+#define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) \
+                  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__))
+#else
+#define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) \
+                  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__))
+#endif /* RCC_D1CCIPR_FMCSEL */
+
+/** @brief  macro to get the FMC clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock
+  *            @arg RCC_RCC_FMCCLKSOURCE_PLL   : PLL1_Q Clock selected as FMC clock
+  *            @arg RCC_RCC_FMCCLKSOURCE_PLL2  : PLL2_R Clock selected as FMC clock
+  *            @arg RCC_RCC_FMCCLKSOURCE_CLKP    CLKP selected as FMC clock
+  */
+#if defined(RCC_D1CCIPR_FMCSEL)
+#define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL)))
+#else
+#define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL)))
+#endif /* RCC_D1CCIPR_FMCSEL */
+
+/** @brief  Macro to configure the USB clock (USBCLK).
+  * @param  __USBCLKSource__ specifies the USB clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_USBCLKSOURCE_PLL:   PLL1Q selected as USB clock
+  *            @arg RCC_USBCLKSOURCE_PLL3:  PLL3Q Clock selected as USB clock
+  *            @arg RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock
+  */
+#if defined(RCC_D2CCIP2R_USBSEL)
+#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
+                  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, (uint32_t)(__USBCLKSource__))
+#else
+#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
+                  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL, (uint32_t)(__USBCLKSource__))
+#endif /* RCC_D2CCIP2R_USBSEL */
+
+/** @brief  Macro to get the USB clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_USBCLKSOURCE_PLL:   PLL1Q selected as USB clock
+  *            @arg RCC_USBCLKSOURCE_PLL3:  PLL3Q Clock selected as USB clock
+  *            @arg RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock
+  */
+#if defined(RCC_D2CCIP2R_USBSEL)
+#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL)))
+#else
+#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL)))
+#endif /* RCC_D2CCIP2R_USBSEL */
+
+/** @brief  Macro to configure the ADC clock
+  * @param  __ADCCLKSource__ specifies the ADC digital interface clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock
+  *            @arg RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock
+  *            @arg RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock
+  */
+#if defined(RCC_D3CCIPR_ADCSEL)
+#define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \
+                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__))
+#else
+#define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \
+                  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__))
+#endif /* RCC_D3CCIPR_ADCSEL */
+
+/** @brief  Macro to get the ADC clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock
+  *            @arg RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock
+  *            @arg RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock
+  */
+#if defined(RCC_D3CCIPR_ADCSEL)
+#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL)))
+#else
+#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL)))
+#endif /* RCC_D3CCIPR_ADCSEL */
+
+ /** @brief  Macro to configure the SWPMI1 clock
+  * @param  __SWPMI1CLKSource__ specifies the SWPMI1  clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_SWPMI1CLKSOURCE_D2PCLK1:  D2PCLK1 Clock selected as SWPMI1 clock
+  *            @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock
+  */
+#if defined(RCC_D2CCIP1R_SWPSEL)
+#define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) \
+                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__))
+#else
+#define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) \
+                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__))
+#endif /* RCC_D2CCIP1R_SWPSEL */
+
+/** @brief  Macro to get the SWPMI1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_SWPMI1CLKSOURCE_D2PCLK1:  D2PCLK1 Clock selected as SWPMI1 clock
+  *            @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock
+  */
+#if defined(RCC_D2CCIP1R_SWPSEL)
+#define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL)))
+#else
+#define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL)))
+#endif /* RCC_D2CCIP1R_SWPSEL */
+
+ /** @brief  Macro to configure the DFSDM1 clock
+  * @param  __DFSDM1CLKSource__ specifies the DFSDM1  clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_DFSDM1CLKSOURCE_D2PCLK:  D2PCLK Clock selected as DFSDM1 clock
+  *            @arg RCC_DFSDM1CLKSOURCE_SYS:     System Clock selected as DFSDM1 clock
+  */
+#if defined(RCC_D2CCIP1R_DFSDM1SEL)
+#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) \
+                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__))
+#else
+#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) \
+                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__))
+#endif /* RCC_D2CCIP1R_DFSDM1SEL */
+
+/** @brief  Macro to get the DFSDM1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_DFSDM1CLKSOURCE_D2PCLK:  D2PCLK Clock selected as DFSDM1 clock
+  *            @arg RCC_DFSDM1CLKSOURCE_SYS:   System Clock selected as DFSDM1 clock
+  */
+#if defined (RCC_D2CCIP1R_DFSDM1SEL)
+#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL)))
+#else
+#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL)))
+#endif /* RCC_D2CCIP1R_DFSDM1SEL */
+
+#if defined(DFSDM2_BASE)
+ /** @brief  Macro to configure the DFSDM2 clock
+  * @param  __DFSDM2CLKSource__ specifies the DFSDM2  clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_DFSDM2CLKSOURCE_SRDPCLK1:  SRDPCLK1 (APB4) selected as DFSDM2 clock
+  *            @arg RCC_DFSDM2CLKSOURCE_SYS:   System Clock selected as DFSDM2 clock
+  */
+#define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2CLKSource__) \
+                  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL, (uint32_t)(__DFSDM2CLKSource__))
+
+/** @brief  Macro to get the DFSDM2 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_DFSDM2CLKSOURCE_SRDPCLK1:  SRDPCLK1 (APB4) Clock selected as DFSDM2 clock
+  *            @arg RCC_DFSDM2CLKSOURCE_SYS:   System Clock selected as DFSDM2 clock
+  */
+#define __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL)))
+#endif /* DFSDM2 */
+
+/** @brief macro to configure the CEC clock (CECCLK).
+  *
+  * @param  __CECCLKSource__ specifies the CEC clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
+  *            @arg RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock
+  *            @arg RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock
+  */
+#if defined(RCC_D2CCIP2R_CECSEL)
+#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
+                  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, (uint32_t)(__CECCLKSource__))
+#else
+#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
+                  MODIFY_REG(RCC->D2CCIP2R, RCC_CDCCIP2R_CECSEL, (uint32_t)(__CECCLKSource__))
+#endif /* RCC_D2CCIP2R_CECSEL */
+
+/** @brief  macro to get the CEC clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
+  *            @arg RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock
+  *            @arg RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock
+  */
+#if defined(RCC_D2CCIP2R_CECSEL)
+#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL)))
+#else
+#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL)))
+#endif /* RCC_D2CCIP2R_CECSEL */
+
+/** @brief  Macro to configure the CLKP : Oscillator clock for peripheral
+  * @param  __CLKPSource__ specifies Oscillator clock for peripheral
+  *         This parameter can be one of the following values:
+  *            @arg RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral
+  *            @arg RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral
+  *            @arg RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral
+  */
+#if defined(RCC_D1CCIPR_CKPERSEL)
+#define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \
+                  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, (uint32_t)(__CLKPSource__))
+#else
+#define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \
+                  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL, (uint32_t)(__CLKPSource__))
+#endif /* RCC_D1CCIPR_CKPERSEL */
+
+/** @brief  Macro to get the Oscillator clock for peripheral  source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral
+  *            @arg RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral
+  *            @arg RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral
+  */
+#if defined(RCC_D1CCIPR_CKPERSEL)
+#define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL)))
+#else
+#define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL)))
+#endif /* RCC_D1CCIPR_CKPERSEL */
+
+#if defined(FDCAN1) || defined(FDCAN2)
+/** @brief  Macro to configure the FDCAN clock
+  * @param  __FDCANCLKSource__ specifies  clock source  for FDCAN
+  *         This parameter can be one of the following values:
+  *            @arg RCC_FDCANCLKSOURCE_HSE: HSE selected as FDCAN clock
+  *            @arg RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock
+  *            @arg RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock
+  */
+#if defined(RCC_D2CCIP1R_FDCANSEL)
+#define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) \
+                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__))
+#else
+#define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) \
+                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__))
+#endif /* RCC_D2CCIP1R_FDCANSEL */
+
+/** @brief  Macro to get the FDCAN clock
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_FDCANCLKSOURCE_HSE: HSE selected as FDCAN clock
+  *            @arg RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock
+  *            @arg RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock
+  */
+#if defined(RCC_D2CCIP1R_FDCANSEL)
+#define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL)))
+#else
+#define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL)))
+#endif /* RCC_D2CCIP1R_FDCANSEL */
+
+#endif /*FDCAN1 || FDCAN2*/
+
+/**
+  * @brief  Macro to Configure the SPI1/2/3 clock source.
+  * @param  __RCC_SPI123CLKSource__ defines the SPI1/2/3 clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL
+  *             @arg RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2
+  *             @arg RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3
+  *             @arg RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock  = CLKP
+  *             @arg RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock
+  * @retval None
+  */
+#if defined(RCC_D2CCIP1R_SPI123SEL)
+#define __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__ )\
+                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__))
+#else
+#define __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__ )\
+                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__))
+#endif /* RCC_D2CCIP1R_SPI123SEL */
+
+/** @brief  Macro to get the SPI1/2/3 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL
+  *             @arg RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2
+  *             @arg RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3
+  *             @arg RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock  = CLKP
+  *             @arg RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock
+  */
+#if defined(RCC_D2CCIP1R_SPI123SEL)
+#define __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL)))
+#else
+#define __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL)))
+#endif /* RCC_D2CCIP1R_SPI123SEL */
+
+/**
+  * @brief  Macro to Configure the SPI1 clock source.
+  * @param  __RCC_SPI1CLKSource__ defines the SPI1 clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL
+  *             @arg RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2
+  *             @arg RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3
+  *             @arg RCC_SPI1CLKSOURCE_CLKP: SPI1 clock  = CLKP
+  *             @arg RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock
+  * @retval None
+  */
+#define __HAL_RCC_SPI1_CONFIG  __HAL_RCC_SPI123_CONFIG
+
+/** @brief  Macro to get the SPI1 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL
+  *             @arg RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2
+  *             @arg RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3
+  *             @arg RCC_SPI1CLKSOURCE_CLKP: SPI1 clock  = CLKP
+  *             @arg RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock
+  */
+#define __HAL_RCC_GET_SPI1_SOURCE  __HAL_RCC_GET_SPI123_SOURCE
+
+/**
+  * @brief  Macro to Configure the SPI2 clock source.
+  * @param  __RCC_SPI2CLKSource__ defines the SPI2 clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL
+  *             @arg RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2
+  *             @arg RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3
+  *             @arg RCC_SPI2CLKSOURCE_CLKP: SPI2 clock  = CLKP
+  *             @arg RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock
+  * @retval None
+  */
+#define __HAL_RCC_SPI2_CONFIG  __HAL_RCC_SPI123_CONFIG
+
+/** @brief  Macro to get the SPI2 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL
+  *             @arg RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2
+  *             @arg RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3
+  *             @arg RCC_SPI2CLKSOURCE_CLKP: SPI2 clock  = CLKP
+  *             @arg RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock
+  */
+#define __HAL_RCC_GET_SPI2_SOURCE  __HAL_RCC_GET_SPI123_SOURCE
+
+/**
+  * @brief  Macro to Configure the SPI3 clock source.
+  * @param  __RCC_SPI3CLKSource__ defines the SPI3 clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL
+  *             @arg RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2
+  *             @arg RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3
+  *             @arg RCC_SPI3CLKSOURCE_CLKP: SPI3 clock  = CLKP
+  *             @arg RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock
+  * @retval None
+  */
+#define __HAL_RCC_SPI3_CONFIG  __HAL_RCC_SPI123_CONFIG
+
+/** @brief  Macro to get the SPI3 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL
+  *             @arg RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2
+  *             @arg RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3
+  *             @arg RCC_SPI3CLKSOURCE_CLKP: SPI3 clock  = CLKP
+  *             @arg RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock
+  */
+#define __HAL_RCC_GET_SPI3_SOURCE  __HAL_RCC_GET_SPI123_SOURCE
+
+/**
+  * @brief  Macro to Configure the SPI4/5 clock source.
+  * @param  __RCC_SPI45CLKSource__ defines the SPI4/5 clock source. This clock is derived
+  *         from system PCLK, PLL2, PLL3, OSC
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SPI45CLKSOURCE_D2PCLK1:SPI4/5 clock = D2PCLK1
+  *             @arg RCC_SPI45CLKSOURCE_PLL2:   SPI4/5 clock = PLL2
+  *             @arg RCC_SPI45CLKSOURCE_PLL3:   SPI4/5 clock = PLL3
+  *             @arg RCC_SPI45CLKSOURCE_HSI:    SPI4/5 clock = HSI
+  *             @arg RCC_SPI45CLKSOURCE_CSI:    SPI4/5 clock = CSI
+  *             @arg RCC_SPI45CLKSOURCE_HSE:    SPI4/5 clock = HSE
+  * @retval None
+  */
+#if defined(RCC_D2CCIP1R_SPI45SEL)
+#define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__ )\
+                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__))
+#else
+#define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__ )\
+                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__))
+#endif /* RCC_D2CCIP1R_SPI45SEL */
+
+/** @brief  Macro to get the SPI4/5 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SPI45CLKSOURCE_D2PCLK1:SPI4/5 clock = D2PCLK1
+  *             @arg RCC_SPI45CLKSOURCE_PLL2:   SPI4/5 clock = PLL2
+  *             @arg RCC_SPI45CLKSOURCE_PLL3:   SPI4/5 clock = PLL3
+  *             @arg RCC_SPI45CLKSOURCE_HSI:    SPI4/5 clock = HSI
+  *             @arg RCC_SPI45CLKSOURCE_CSI:    SPI4/5 clock = CSI
+  *             @arg RCC_SPI45CLKSOURCE_HSE:    SPI4/5 clock = HSE
+*/
+#if defined(RCC_D2CCIP1R_SPI45SEL)
+#define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL)))
+#else
+#define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL)))
+#endif /* RCC_D2CCIP1R_SPI45SEL */
+
+/**
+  * @brief  Macro to Configure the SPI4 clock source.
+  * @param  __RCC_SPI4CLKSource__ defines the SPI4 clock source. This clock is derived
+  *         from system PCLK, PLL2, PLL3, OSC
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1
+  *             @arg RCC_SPI4CLKSOURCE_PLL2:   SPI4 clock = PLL2
+  *             @arg RCC_SPI4CLKSOURCE_PLL3:   SPI4 clock = PLL3
+  *             @arg RCC_SPI4CLKSOURCE_HSI:    SPI4 clock = HSI
+  *             @arg RCC_SPI4CLKSOURCE_CSI:    SPI4 clock = CSI
+  *             @arg RCC_SPI4CLKSOURCE_HSE:    SPI4 clock = HSE
+  * @retval None
+  */
+#define __HAL_RCC_SPI4_CONFIG  __HAL_RCC_SPI45_CONFIG
+
+/** @brief  Macro to get the SPI4 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1
+  *             @arg RCC_SPI4CLKSOURCE_PLL2:   SPI4 clock = PLL2
+  *             @arg RCC_SPI4CLKSOURCE_PLL3:   SPI4 clock = PLL3
+  *             @arg RCC_SPI4CLKSOURCE_HSI:    SPI4 clock = HSI
+  *             @arg RCC_SPI4CLKSOURCE_CSI:    SPI4 clock = CSI
+  *             @arg RCC_SPI4CLKSOURCE_HSE:    SPI4 clock = HSE
+*/
+#define __HAL_RCC_GET_SPI4_SOURCE  __HAL_RCC_GET_SPI45_SOURCE
+
+/**
+  * @brief  Macro to Configure the SPI5 clock source.
+  * @param  __RCC_SPI5CLKSource__ defines the SPI5 clock source. This clock is derived
+  *         from system PCLK, PLL2, PLL3, OSC
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1
+  *             @arg RCC_SPI5CLKSOURCE_PLL2:   SPI5 clock = PLL2
+  *             @arg RCC_SPI5CLKSOURCE_PLL3:   SPI5 clock = PLL3
+  *             @arg RCC_SPI5CLKSOURCE_HSI:    SPI5 clock = HSI
+  *             @arg RCC_SPI5CLKSOURCE_CSI:    SPI5 clock = CSI
+  *             @arg RCC_SPI5CLKSOURCE_HSE:    SPI5 clock = HSE
+  * @retval None
+  */
+#define __HAL_RCC_SPI5_CONFIG  __HAL_RCC_SPI45_CONFIG
+
+/** @brief  Macro to get the SPI5 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1
+  *             @arg RCC_SPI5CLKSOURCE_PLL2:   SPI5 clock = PLL2
+  *             @arg RCC_SPI5CLKSOURCE_PLL3:   SPI5 clock = PLL3
+  *             @arg RCC_SPI5CLKSOURCE_HSI:    SPI5 clock = HSI
+  *             @arg RCC_SPI5CLKSOURCE_CSI:    SPI5 clock = CSI
+  *             @arg RCC_SPI5CLKSOURCE_HSE:    SPI5 clock = HSE
+*/
+#define __HAL_RCC_GET_SPI5_SOURCE  __HAL_RCC_GET_SPI45_SOURCE
+
+/**
+  * @brief  Macro to Configure the SPI6 clock source.
+  * @param  __RCC_SPI6CLKSource__ defines the SPI6 clock source. This clock is derived
+  *         from system PCLK, PLL2, PLL3, OSC
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1
+  *             @arg RCC_SPI6CLKSOURCE_PLL2:   SPI6 clock = PLL2
+  *             @arg RCC_SPI6CLKSOURCE_PLL3:   SPI6 clock = PLL3
+  *             @arg RCC_SPI6CLKSOURCE_HSI:    SPI6 clock = HSI
+  *             @arg RCC_SPI6CLKSOURCE_CSI:    SPI6 clock = CSI
+  *             @arg RCC_SPI6CLKSOURCE_HSE:    SPI6 clock = HSE
+  *             @arg RCC_SPI6CLKSOURCE_PIN:    SPI6 clock = I2S_CKIN (*)
+  *
+  * @retval None
+  *
+  * (*) : Available on stm32h7a3xx and stm32h7b3xx family lines.
+  *
+  */
+#if defined(RCC_D3CCIPR_SPI6SEL)
+#define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__ )\
+                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL, (__RCC_SPI6CLKSource__))
+#else
+#define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__ )\
+                  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL, (__RCC_SPI6CLKSource__))
+#endif /* RCC_D3CCIPR_SPI6SEL */
+
+/** @brief  Macro to get the SPI6 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1
+  *             @arg RCC_SPI6CLKSOURCE_PLL2:   SPI6 clock = PLL2
+  *             @arg RCC_SPI6CLKSOURCE_PLL3:   SPI6 clock = PLL3
+  *             @arg RCC_SPI6CLKSOURCE_HSI:    SPI6 clock = HSI
+  *             @arg RCC_SPI6CLKSOURCE_CSI:    SPI6 clock = CSI
+  *             @arg RCC_SPI6CLKSOURCE_HSE:    SPI6 clock = HSE
+  *                @arg RCC_SPI6CLKSOURCE_PIN:    SPI6 clock = I2S_CKIN
+*/
+#if defined(RCC_D3CCIPR_SPI6SEL)
+#define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL)))
+#else
+#define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL)))
+#endif /* RCC_D3CCIPR_SPI6SEL */
+
+/** @brief  Macro to configure the SDMMC clock
+  * @param  __SDMMCCLKSource__ specifies  clock source  for SDMMC
+  *         This parameter can be one of the following values:
+  *            @arg RCC_SDMMCCLKSOURCE_PLL:  PLLQ selected as SDMMC clock
+  *            @arg RCC_SDMMCCLKSOURCE_PLL2: PLL2R selected as SDMMC clock
+  */
+#if defined(RCC_D1CCIPR_SDMMCSEL)
+#define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) \
+                  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__))
+#else
+#define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) \
+                  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__))
+#endif /* RCC_D1CCIPR_SDMMCSEL */
+
+/** @brief  Macro to get the SDMMC clock
+  */
+#if defined(RCC_D1CCIPR_SDMMCSEL)
+#define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL)))
+#else
+#define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL)))
+#endif /* RCC_D1CCIPR_SDMMCSEL */
+
+/** @brief macro to configure the RNG clock (RNGCLK).
+  *
+  * @param  __RNGCLKSource__ specifies the RNG clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
+  *            @arg RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock
+  *            @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock
+  *            @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock
+  */
+#if defined(RCC_D2CCIP2R_RNGSEL)
+#define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \
+                  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__))
+#else
+#define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \
+                  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__))
+#endif /* RCC_D2CCIP2R_RNGSEL */
+
+/** @brief  macro to get the RNG clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
+  *            @arg RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock
+  *            @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock
+  *            @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock
+  */
+#if defined(RCC_D2CCIP2R_RNGSEL)
+#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL)))
+#else
+#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL)))
+#endif /* RCC_D2CCIP2R_RNGSEL */
+
+#if defined(HRTIM1)
+/** @defgroup RCCEx_HRTIMx_Clock_Config RCC Extended HRTIMx Clock Config
+  * @{
+  */
+/** @brief  Macro to configure the HRTIM1 prescaler clock source.
+  * @param  __HRTIM1CLKSource__ specifies the HRTIM1 prescaler clock source.
+  *         This parameter can be one of the following values:
+  *            @arg @ref RCC_HRTIM1CLK_TIMCLK    Timers  clock  selected as HRTIM1 prescaler clock
+  *            @arg @ref RCC_HRTIM1CLK_CPUCLK CPU Clock selected as HRTIM1 clock
+  */
+#define __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) \
+                  MODIFY_REG(RCC->CFGR, RCC_CFGR_HRTIMSEL, (uint32_t)(__HRTIM1CLKSource__))
+
+/** @brief  Macro to get the HRTIM1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg @ref RCC_HRTIM1CLK_TIMCLK   Timers  clock  selected as HRTIM1 prescaler clock
+  *            @arg @ref RCC_HRTIM1CLK_CPUCLK CPU Clock selected as HRTIM1 clock
+  */
+#define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HRTIMSEL)))
+#endif /* HRTIM1 */
+
+/** @brief  Macro to configure the Timers clocks prescalers
+  * @param  __PRESC__  specifies the Timers clocks prescalers selection
+  *         This parameter can be one of the following values:
+  *            @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
+  *                 equal to rcc_hclk1 if D2PPREx is corresponding to division by 1 or 2,
+  *                 else it is equal to 2 x Frcc_pclkx_d2 (default after reset)
+  *            @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
+  *                 equal to rcc_hclk1 if D2PPREx is corresponding to division by 1, 2 or 4,
+  *                 else it is equal to 4 x Frcc_pclkx_d2
+  */
+#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->CFGR &= ~(RCC_CFGR_TIMPRE);\
+                                                 RCC->CFGR |= (__PRESC__);       \
+                                                }while(0)
+
+/**
+  * @}
+  */
+    
+/**
+  * @brief Enable the RCC LSE CSS Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT()      SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Disable the RCC LSE CSS Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT()     CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Enable the RCC LSE CSS Event Line.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Disable the RCC LSE CSS Event Line.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
+
+#if defined(DUAL_CORE)
+/**
+  * @brief Enable the RCC LSE CSS Extended Interrupt Line for CM4.
+  * @retval None
+  */
+#define __HAL_RCC_C2_LSECSS_EXTI_ENABLE_IT()       SET_BIT(EXTI->C2IMR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Disable the RCC LSE CSS Extended Interrupt Line for CM4.
+  * @retval None
+  */
+#define __HAL_RCC_C2_LSECSS_EXTI_DISABLE_IT()      CLEAR_BIT(EXTI->C2IMR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Enable the RCC LSE CSS Event Line for CM4.
+  * @retval None.
+  */
+#define __HAL_RCC_C2_LSECSS_EXTI_ENABLE_EVENT()    SET_BIT(EXTI->C2EMR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Disable the RCC LSE CSS Event Line for CM4.
+  * @retval None.
+  */
+#define __HAL_RCC_C2_LSECSS_EXTI_DISABLE_EVENT()   CLEAR_BIT(EXTI->C2EMR1, RCC_EXTI_LINE_LSECSS)
+#endif /* DUAL_CORE */
+
+/**
+  * @brief  Enable the RCC LSE CSS Extended Interrupt Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE()  SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
+
+
+/**
+  * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
+
+
+/**
+  * @brief  Enable the RCC LSE CSS Extended Interrupt Rising Trigger.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE()  \
+  do {                                                      \
+    __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();             \
+    __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE();            \
+  } while(0)
+
+/**
+  * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE()  \
+  do {                                                       \
+    __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE();             \
+    __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE();            \
+  } while(0)
+
+/**
+  * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
+  * @retval EXTI RCC LSE CSS Line Status.
+  */
+#define __HAL_RCC_LSECSS_EXTI_GET_FLAG()       (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Clear the RCC LSE CSS EXTI flag.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG()     WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS)
+
+#if defined(DUAL_CORE)
+/**
+  * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not for CM4.
+  * @retval EXTI RCC LSE CSS Line Status.
+  */
+#define __HAL_RCC_C2_LSECSS_EXTI_GET_FLAG()       (READ_BIT(EXTI->C2PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Clear the RCC LSE CSS EXTI flag or not for CM4.
+  * @retval None.
+  */
+#define __HAL_RCC_C2_LSECSS_EXTI_CLEAR_FLAG()     WRITE_REG(EXTI->C2PR1, RCC_EXTI_LINE_LSECSS)
+#endif /* DUAL_CORE */
+/**
+  * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT()  SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS)
+ 
+/**
+  * @brief  Enable the specified CRS interrupts.
+  * @param  __INTERRUPT__ specifies the CRS interrupt sources to be enabled.
+  *          This parameter can be any combination of the following values:
+  *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
+  *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
+  *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
+  *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
+  * @retval None
+  */
+#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__)   SET_BIT(CRS->CR, (__INTERRUPT__))
+
+/**
+  * @brief  Disable the specified CRS interrupts.
+  * @param  __INTERRUPT__ specifies the CRS interrupt sources to be disabled.
+  *          This parameter can be any combination of the following values:
+  *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
+  *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
+  *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
+  *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
+  * @retval None
+  */
+#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__)  CLEAR_BIT(CRS->CR, (__INTERRUPT__))
+
+/** @brief  Check whether the CRS interrupt has occurred or not.
+  * @param  __INTERRUPT__ specifies the CRS interrupt source to check.
+  *         This parameter can be one of the following values:
+  *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
+  *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
+  *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
+  *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
+  * @retval The new state of __INTERRUPT__ (SET or RESET).
+  */
+#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__)  ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET)
+
+/** @brief  Clear the CRS interrupt pending bits
+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
+  *         This parameter can be any combination of the following values:
+  *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
+  *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
+  *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
+  *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
+  *              @arg @ref RCC_CRS_IT_TRIMOVF  Trimming overflow or underflow interrupt
+  *              @arg @ref RCC_CRS_IT_SYNCERR  SYNC error interrupt
+  *              @arg @ref RCC_CRS_IT_SYNCMISS  SYNC missed interrupt
+  */
+/* CRS IT Error Mask */
+#define  RCC_CRS_IT_ERROR_MASK                 ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))
+
+#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__)  do { \
+                                                 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \
+                                                 { \
+                                                   WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
+                                                 } \
+                                                 else \
+                                                 { \
+                                                   WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
+                                                 } \
+                                               } while(0)
+
+/**
+  * @brief  Check whether the specified CRS flag is set or not.
+  * @param  __FLAG__ specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *              @arg @ref RCC_CRS_FLAG_SYNCOK  SYNC event OK
+  *              @arg @ref RCC_CRS_FLAG_SYNCWARN  SYNC warning
+  *              @arg @ref RCC_CRS_FLAG_ERR  Error
+  *              @arg @ref RCC_CRS_FLAG_ESYNC  Expected SYNC
+  *              @arg @ref RCC_CRS_FLAG_TRIMOVF  Trimming overflow or underflow
+  *              @arg @ref RCC_CRS_FLAG_SYNCERR  SYNC error
+  *              @arg @ref RCC_CRS_FLAG_SYNCMISS  SYNC missed
+  * @retval The new state of _FLAG_ (TRUE or FALSE).
+  */
+#define __HAL_RCC_CRS_GET_FLAG(__FLAG__)  (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
+
+/**
+  * @brief  Clear the CRS specified FLAG.
+  * @param __FLAG__ specifies the flag to clear.
+  *          This parameter can be one of the following values:
+  *              @arg @ref RCC_CRS_FLAG_SYNCOK  SYNC event OK
+  *              @arg @ref RCC_CRS_FLAG_SYNCWARN  SYNC warning
+  *              @arg @ref RCC_CRS_FLAG_ERR  Error
+  *              @arg @ref RCC_CRS_FLAG_ESYNC  Expected SYNC
+  *              @arg @ref RCC_CRS_FLAG_TRIMOVF  Trimming overflow or underflow
+  *              @arg @ref RCC_CRS_FLAG_SYNCERR  SYNC error
+  *              @arg @ref RCC_CRS_FLAG_SYNCMISS  SYNC missed
+  * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR
+  * @retval None
+  */
+
+/* CRS Flag Error Mask */
+#define RCC_CRS_FLAG_ERROR_MASK                ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))
+
+#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__)     do { \
+                                                 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \
+                                                 { \
+                                                   WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
+                                                 } \
+                                                 else \
+                                                 { \
+                                                   WRITE_REG(CRS->ICR, (__FLAG__)); \
+                                                 } \
+                                               } while(0)
+
+ /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
+  * @{
+  */
+/**
+  * @brief  Enable the oscillator clock for frequency error counter.
+  * @note   when the CEN bit is set the CRS_CFGR register becomes write-protected.
+  * @retval None
+  */
+#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE()  SET_BIT(CRS->CR, CRS_CR_CEN)
+
+/**
+  * @brief  Disable the oscillator clock for frequency error counter.
+  * @retval None
+  */
+#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
+
+/**
+  * @brief  Enable the automatic hardware adjustment of TRIM bits.
+  * @note   When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
+  * @retval None
+  */
+#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE()     SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
+
+/**
+  * @brief  Enable or disable the automatic hardware adjustment of TRIM bits.
+  * @retval None
+  */
+#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE()    CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
+
+/**
+  * @brief  Macro to calculate reload value to be set in CRS register according to target and sync frequencies
+  * @note   The RELOAD value should be selected according to the ratio between the target frequency and the frequency
+  *             of the synchronization source after pre-scaling. It is then decreased by one in order to
+  *             reach the expected synchronization on the zero value. The formula is the following:
+  *             RELOAD = (fTARGET / fSYNC) -1
+  * @param  __FTARGET__ Target frequency (value in Hz)
+  * @param  __FSYNC__ Synchronization signal frequency (value in Hz)
+  * @retval None
+  */
+#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)  (((__FTARGET__) / (__FSYNC__)) - 1U)
+
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCCEx_Exported_Functions_Group1
+  * @{
+  */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
+uint32_t HAL_RCCEx_GetD1PCLK1Freq(void);
+uint32_t HAL_RCCEx_GetD3PCLK1Freq(void);
+uint32_t HAL_RCCEx_GetD1SysClockFreq(void);
+void     HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef* PLL1_Clocks);
+void     HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef* PLL2_Clocks);
+void     HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef* PLL3_Clocks);
+/**
+  * @}
+  */
+
+/** @addtogroup RCCEx_Exported_Functions_Group2
+  * @{
+  */
+void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk);
+void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk);
+void HAL_RCCEx_EnableLSECSS(void);
+void HAL_RCCEx_DisableLSECSS(void);
+void HAL_RCCEx_EnableLSECSS_IT(void);
+void HAL_RCCEx_LSECSS_IRQHandler(void);
+void HAL_RCCEx_LSECSS_Callback(void);
+#if defined(DUAL_CORE)
+void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx);
+#endif /*DUAL_CORE*/
+#if defined(RCC_GCR_WW1RSC)
+void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx);
+#endif /*RCC_GCR_WW1RSC*/
+/**
+  * @}
+  */
+
+
+/** @addtogroup RCCEx_Exported_Functions_Group3
+  * @{
+  */
+
+void     HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
+void     HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
+void     HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
+uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
+void     HAL_RCCEx_CRS_IRQHandler(void);
+void     HAL_RCCEx_CRS_SyncOkCallback(void);
+void     HAL_RCCEx_CRS_SyncWarnCallback(void);
+void     HAL_RCCEx_CRS_ExpectedSyncCallback(void);
+void     HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
+
+/**
+  * @}
+  */
+
+ /* Private macros ------------------------------------------------------------*/
+/** @addtogroup RCCEx_Private_Macros RCCEx Private Macros
+  * @{
+  */
+/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
+  * @{
+  */
+
+#define IS_RCC_PLL2CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL2_DIVP) || \
+                                         ((VALUE) == RCC_PLL2_DIVQ)  || \
+                                         ((VALUE) == RCC_PLL2_DIVR))
+
+#define IS_RCC_PLL3CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL3_DIVP) || \
+                                          ((VALUE) == RCC_PLL3_DIVQ) || \
+                                          ((VALUE) == RCC_PLL3_DIVR))
+
+#if defined(RCC_D2CCIP2R_USART16SEL)
+#define IS_RCC_USART16CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART16CLKSOURCE_D2PCLK2)|| \
+                                         ((SOURCE) == RCC_USART16CLKSOURCE_PLL2)   || \
+                                         ((SOURCE) == RCC_USART16CLKSOURCE_PLL3)   || \
+                                         ((SOURCE) == RCC_USART16CLKSOURCE_CSI)    || \
+                                         ((SOURCE) == RCC_USART16CLKSOURCE_LSE)    || \
+                                         ((SOURCE) == RCC_USART16CLKSOURCE_HSI))
+#else
+#define IS_RCC_USART16CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART16CLKSOURCE_D2PCLK2)|| \
+                                         ((SOURCE) == RCC_USART16CLKSOURCE_CDPCLK2)|| \
+                                         ((SOURCE) == RCC_USART16CLKSOURCE_PLL2)   || \
+                                         ((SOURCE) == RCC_USART16CLKSOURCE_PLL3)   || \
+                                         ((SOURCE) == RCC_USART16CLKSOURCE_CSI)    || \
+                                         ((SOURCE) == RCC_USART16CLKSOURCE_LSE)    || \
+                                         ((SOURCE) == RCC_USART16CLKSOURCE_HSI))
+/* alias*/
+#define IS_RCC_USART16910CLKSOURCE    IS_RCC_USART16CLKSOURCE
+#endif /* RCC_D2CCIP2R_USART16SEL */
+
+#if defined(RCC_D2CCIP2R_USART28SEL)
+#define IS_RCC_USART234578CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART234578CLKSOURCE_D2PCLK1)|| \
+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_PLL2)   || \
+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_PLL3)   || \
+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_CSI)    || \
+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_LSE)    || \
+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_HSI))
+#else
+#define IS_RCC_USART234578CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART234578CLKSOURCE_D2PCLK1)|| \
+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_CDPCLK1)|| \
+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_PLL2)   || \
+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_PLL3)   || \
+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_CSI)    || \
+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_LSE)    || \
+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_HSI))
+#endif /* RCC_D2CCIP2R_USART28SEL */
+
+#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_D2PCLK2)|| \
+                                        ((SOURCE) == RCC_USART1CLKSOURCE_PLL2)   || \
+                                        ((SOURCE) == RCC_USART1CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_USART1CLKSOURCE_CSI)    || \
+                                        ((SOURCE) == RCC_USART1CLKSOURCE_LSE)    || \
+                                        ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
+
+#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_D2PCLK1)|| \
+                                        ((SOURCE) == RCC_USART2CLKSOURCE_PLL2)   || \
+                                        ((SOURCE) == RCC_USART2CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_USART2CLKSOURCE_CSI)    || \
+                                        ((SOURCE) == RCC_USART2CLKSOURCE_LSE)    || \
+                                        ((SOURCE) == RCC_USART2CLKSOURCE_HSI))
+
+#define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_D2PCLK1)|| \
+                                        ((SOURCE) == RCC_USART3CLKSOURCE_PLL2)   || \
+                                        ((SOURCE) == RCC_USART3CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_USART3CLKSOURCE_CSI)    || \
+                                        ((SOURCE) == RCC_USART3CLKSOURCE_LSE)    || \
+                                        ((SOURCE) == RCC_USART3CLKSOURCE_HSI))
+
+#define IS_RCC_UART4CLKSOURCE(SOURCE)  (((SOURCE) == RCC_UART4CLKSOURCE_D2PCLK1) || \
+                                        ((SOURCE) == RCC_UART4CLKSOURCE_PLL2)    || \
+                                        ((SOURCE) == RCC_UART4CLKSOURCE_PLL3)    || \
+                                        ((SOURCE) == RCC_UART4CLKSOURCE_CSI)     || \
+                                        ((SOURCE) == RCC_UART4CLKSOURCE_LSE)     || \
+                                        ((SOURCE) == RCC_UART4CLKSOURCE_HSI))
+
+#define IS_RCC_UART5CLKSOURCE(SOURCE)  (((SOURCE) == RCC_UART5CLKSOURCE_D2PCLK1) || \
+                                        ((SOURCE) == RCC_UART5CLKSOURCE_PLL2)    || \
+                                        ((SOURCE) == RCC_UART5CLKSOURCE_PLL3)    || \
+                                        ((SOURCE) == RCC_UART5CLKSOURCE_CSI)     || \
+                                        ((SOURCE) == RCC_UART5CLKSOURCE_LSE)     || \
+                                        ((SOURCE) == RCC_UART5CLKSOURCE_HSI))
+
+#define IS_RCC_USART6CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART6CLKSOURCE_D2PCLK2)|| \
+                                        ((SOURCE) == RCC_USART6CLKSOURCE_PLL2)   || \
+                                        ((SOURCE) == RCC_USART6CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_USART6CLKSOURCE_CSI)    || \
+                                        ((SOURCE) == RCC_USART6CLKSOURCE_LSE)    || \
+                                        ((SOURCE) == RCC_USART6CLKSOURCE_HSI))
+
+#define IS_RCC_UART7CLKSOURCE(SOURCE)  (((SOURCE) == RCC_UART7CLKSOURCE_D2PCLK1) || \
+                                        ((SOURCE) == RCC_UART7CLKSOURCE_PLL2)    || \
+                                        ((SOURCE) == RCC_UART7CLKSOURCE_PLL3)    || \
+                                        ((SOURCE) == RCC_UART7CLKSOURCE_CSI)     || \
+                                        ((SOURCE) == RCC_UART7CLKSOURCE_LSE)     || \
+                                        ((SOURCE) == RCC_UART7CLKSOURCE_HSI))
+
+#define IS_RCC_UART8CLKSOURCE(SOURCE)  (((SOURCE) == RCC_UART8CLKSOURCE_D2PCLK1) || \
+                                        ((SOURCE) == RCC_UART8CLKSOURCE_PLL2)    || \
+                                        ((SOURCE) == RCC_UART8CLKSOURCE_PLL3)    || \
+                                        ((SOURCE) == RCC_UART8CLKSOURCE_CSI)     || \
+                                        ((SOURCE) == RCC_UART8CLKSOURCE_LSE)     || \
+                                        ((SOURCE) == RCC_UART8CLKSOURCE_HSI))
+
+#if defined(UART9)
+#define IS_RCC_UART9CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART9CLKSOURCE_D2PCLK2)|| \
+                                        ((SOURCE) == RCC_UART9CLKSOURCE_PLL2)  || \
+                                        ((SOURCE) == RCC_UART9CLKSOURCE_PLL3)  || \
+                                        ((SOURCE) == RCC_UART9CLKSOURCE_CSI)   || \
+                                        ((SOURCE) == RCC_UART9CLKSOURCE_LSE)   || \
+                                        ((SOURCE) == RCC_UART9CLKSOURCE_HSI))
+#endif
+
+#if defined(USART10)
+#define IS_RCC_USART10CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART10CLKSOURCE_D2PCLK2)|| \
+                                        ((SOURCE) == RCC_USART10CLKSOURCE_PLL2)    || \
+                                        ((SOURCE) == RCC_USART10CLKSOURCE_PLL3)    || \
+                                        ((SOURCE) == RCC_USART10CLKSOURCE_CSI)     || \
+                                        ((SOURCE) == RCC_USART10CLKSOURCE_LSE)     || \
+                                        ((SOURCE) == RCC_USART10CLKSOURCE_HSI))
+#endif
+
+#define IS_RCC_LPUART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPUART1CLKSOURCE_D3PCLK1) || \
+                                         ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL2)    || \
+                                         ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL3)    || \
+                                         ((SOURCE) == RCC_LPUART1CLKSOURCE_CSI)     || \
+                                         ((SOURCE) == RCC_LPUART1CLKSOURCE_LSE)     || \
+                                         ((SOURCE) == RCC_LPUART1CLKSOURCE_HSI))
+
+#define IS_RCC_I2C123CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C123CLKSOURCE_PLL3)   || \
+                                          ((SOURCE) == RCC_I2C123CLKSOURCE_HSI)    || \
+                                          ((SOURCE) == RCC_I2C123CLKSOURCE_D2PCLK1)|| \
+                                          ((SOURCE) == RCC_I2C123CLKSOURCE_CSI))
+
+#define IS_RCC_I2C1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C1CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_I2C1CLKSOURCE_HSI)    || \
+                                        ((SOURCE) == RCC_I2C1CLKSOURCE_D2PCLK1)|| \
+                                        ((SOURCE) == RCC_I2C1CLKSOURCE_CSI))
+
+#define IS_RCC_I2C2CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C2CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_I2C2CLKSOURCE_HSI)    || \
+                                        ((SOURCE) == RCC_I2C2CLKSOURCE_D2PCLK1)|| \
+                                        ((SOURCE) == RCC_I2C2CLKSOURCE_CSI))
+
+#define IS_RCC_I2C3CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C3CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_I2C3CLKSOURCE_HSI)    || \
+                                        ((SOURCE) == RCC_I2C3CLKSOURCE_D2PCLK1)|| \
+                                        ((SOURCE) == RCC_I2C3CLKSOURCE_CSI))
+
+#define IS_RCC_I2C4CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C4CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_I2C4CLKSOURCE_HSI)    || \
+                                        ((SOURCE) == RCC_I2C4CLKSOURCE_D3PCLK1)|| \
+                                        ((SOURCE) == RCC_I2C3CLKSOURCE_CSI))
+
+#define IS_RCC_RNGCLKSOURCE(SOURCE)    (((SOURCE) == RCC_RNGCLKSOURCE_HSI48)|| \
+                                        ((SOURCE) == RCC_RNGCLKSOURCE_PLL)  || \
+                                        ((SOURCE) == RCC_RNGCLKSOURCE_LSE)  || \
+                                        ((SOURCE) == RCC_RNGCLKSOURCE_LSI))
+
+#if defined(HRTIM1)
+#define IS_RCC_HRTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_HRTIM1CLK_TIMCLK) || \
+                                        ((SOURCE) == RCC_HRTIM1CLK_CPUCLK))
+#endif
+
+#define IS_RCC_USBCLKSOURCE(SOURCE)    (((SOURCE) == RCC_USBCLKSOURCE_PLL)  || \
+                                        ((SOURCE) == RCC_USBCLKSOURCE_PLL3) || \
+                                        ((SOURCE) == RCC_USBCLKSOURCE_HSI48))
+
+#define IS_RCC_SAI1CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SAI1CLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))
+
+#if defined(SAI3)
+#define IS_RCC_SAI23CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SAI23CLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SAI23CLKSOURCE_PIN))
+
+#define IS_RCC_SAI2CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SAI2CLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN))
+
+
+#define IS_RCC_SAI3CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SAI3CLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SAI3CLKSOURCE_PIN))
+#endif
+
+#if defined(RCC_CDCCIP1R_SAI2ASEL)
+#define IS_RCC_SAI2ACLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SAI2ACLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PIN) || \
+                ((__SOURCE__) == RCC_SAI2ACLKSOURCE_SPDIF))
+#endif
+
+#if defined(RCC_CDCCIP1R_SAI2BSEL)
+#define IS_RCC_SAI2BCLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SAI2BCLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PIN) || \
+                ((__SOURCE__) == RCC_SAI2BCLKSOURCE_SPDIF))
+#endif
+
+#define IS_RCC_SPI123CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SPI123CLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SPI123CLKSOURCE_PIN))
+
+#define IS_RCC_SPI1CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SPI1CLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SPI1CLKSOURCE_PIN))
+
+#define IS_RCC_SPI2CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SPI2CLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SPI2CLKSOURCE_PIN))
+
+#define IS_RCC_SPI3CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SPI3CLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SPI3CLKSOURCE_PIN))
+
+#define IS_RCC_SPI45CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SPI45CLKSOURCE_D2PCLK1)  || \
+                ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL2)     || \
+                ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL3)     || \
+                ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSI)      || \
+                ((__SOURCE__) == RCC_SPI45CLKSOURCE_CSI)      || \
+                ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSE))
+
+#define IS_RCC_SPI4CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SPI4CLKSOURCE_D2PCLK1)  || \
+                ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL2)     || \
+                ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL3)     || \
+                ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSI)      || \
+                ((__SOURCE__) == RCC_SPI4CLKSOURCE_CSI)      || \
+                ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSE))
+
+#define IS_RCC_SPI5CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SPI5CLKSOURCE_D2PCLK1)|| \
+                ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL2)   || \
+                ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL3)   || \
+                ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSI)    || \
+                ((__SOURCE__) == RCC_SPI5CLKSOURCE_CSI)    || \
+                ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSE))
+
+#if defined(RCC_D3CCIPR_SPI6SEL)
+#define IS_RCC_SPI6CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) || \
+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2)    || \
+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3)    || \
+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI)     || \
+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI)     || \
+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE))
+#else
+#define IS_RCC_SPI6CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) || \
+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2)    || \
+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3)    || \
+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI)     || \
+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI)     || \
+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE)     || \
+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_PIN))
+#endif /* RCC_D3CCIPR_SPI6SEL */
+
+#if defined(SAI4)
+#define IS_RCC_SAI4ACLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SAI4ACLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PIN))
+
+#define IS_RCC_SAI4BCLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SAI4BCLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PIN))
+#endif /*SAI4*/
+
+#define IS_RCC_PLL3M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))
+#define IS_RCC_PLL3N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))
+#define IS_RCC_PLL3P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
+#define IS_RCC_PLL3Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
+#define IS_RCC_PLL3R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
+
+#define IS_RCC_PLL2M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))
+#define IS_RCC_PLL2N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))
+#define IS_RCC_PLL2P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
+#define IS_RCC_PLL2Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
+#define IS_RCC_PLL2R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
+
+#define IS_RCC_PLL2RGE_VALUE(VALUE) (((VALUE) == RCC_PLL2VCIRANGE_0)  || \
+                                    ((VALUE) == RCC_PLL2VCIRANGE_1)   || \
+                                    ((VALUE) == RCC_PLL2VCIRANGE_2)   || \
+                                    ((VALUE) == RCC_PLL2VCIRANGE_3))
+
+#define IS_RCC_PLL3RGE_VALUE(VALUE) (((VALUE) == RCC_PLL3VCIRANGE_0)  || \
+                                    ((VALUE) == RCC_PLL3VCIRANGE_1)   || \
+                                    ((VALUE) == RCC_PLL3VCIRANGE_2)   || \
+                                    ((VALUE) == RCC_PLL3VCIRANGE_3))
+
+#define IS_RCC_PLL2VCO_VALUE(VALUE) (((VALUE) == RCC_PLL2VCOWIDE)  || \
+                                    ((VALUE) == RCC_PLL2VCOMEDIUM))
+
+#define IS_RCC_PLL3VCO_VALUE(VALUE) (((VALUE) == RCC_PLL3VCOWIDE)  || \
+                                    ((VALUE) == RCC_PLL3VCOMEDIUM))
+
+#define IS_RCC_PLLFRACN_VALUE(VALUE) ((VALUE) <=8191U)
+
+#define IS_RCC_LPTIM1CLK(SOURCE)       (((SOURCE) == RCC_LPTIM1CLKSOURCE_D2PCLK1)|| \
+                                        ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL2)   || \
+                                        ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)    || \
+                                        ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI)    || \
+                                        ((SOURCE) == RCC_LPTIM1CLKSOURCE_CLKP))
+
+#define IS_RCC_LPTIM2CLK(SOURCE)       (((SOURCE) == RCC_LPTIM2CLKSOURCE_D3PCLK1)|| \
+                                        ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL2)   || \
+                                        ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSE)    || \
+                                        ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSI)    || \
+                                        ((SOURCE) == RCC_LPTIM2CLKSOURCE_CLKP))
+
+#define IS_RCC_LPTIM345CLK(SOURCE)     (((SOURCE) == RCC_LPTIM345CLKSOURCE_D3PCLK1)|| \
+                                        ((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL2)   || \
+                                        ((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_LPTIM345CLKSOURCE_LSE)    || \
+                                        ((SOURCE) == RCC_LPTIM345CLKSOURCE_LSI)    || \
+                                        ((SOURCE) == RCC_LPTIM345CLKSOURCE_CLKP))
+
+#define IS_RCC_LPTIM3CLK(SOURCE)       (((SOURCE) == RCC_LPTIM3CLKSOURCE_D3PCLK1)  || \
+                                        ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL2)     || \
+                                        ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL3)     || \
+                                        ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSE)      || \
+                                        ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSI)      || \
+                                        ((SOURCE) == RCC_LPTIM3CLKSOURCE_CLKP))
+
+#if defined(LPTIM4)
+#define IS_RCC_LPTIM4CLK(SOURCE)       (((SOURCE) == RCC_LPTIM4CLKSOURCE_D3PCLK1)|| \
+                                        ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL2)   || \
+                                        ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSE)    || \
+                                        ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSI)    || \
+                                        ((SOURCE) == RCC_LPTIM4CLKSOURCE_CLKP))
+#endif /* LPTIM4*/
+
+#if defined(LPTIM5)
+#define IS_RCC_LPTIM5CLK(SOURCE)       (((SOURCE) == RCC_LPTIM5CLKSOURCE_D3PCLK1)|| \
+                                        ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL2)   || \
+                                        ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSE)    || \
+                                        ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSI)    || \
+                                        ((SOURCE) == RCC_LPTIM5CLKSOURCE_CLKP))
+#endif /*LPTIM5*/
+
+#if defined(QUADSPI)
+#define IS_RCC_QSPICLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_QSPICLKSOURCE_D1HCLK)  || \
+                ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL)     || \
+                ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL2)    || \
+                ((__SOURCE__) == RCC_QSPICLKSOURCE_CLKP))
+#endif /*QUADSPI*/
+
+#if defined(OCTOSPI1) || defined(OCTOSPI1)
+#define IS_RCC_OSPICLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_OSPICLKSOURCE_D1HCLK)  || \
+                ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL)     || \
+                ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL2)    || \
+                ((__SOURCE__) == RCC_OSPICLKSOURCE_CLKP))
+#endif /*OCTOSPI1 || OCTOSPI1*/
+
+#if defined(DSI)
+#define IS_RCC_DSICLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_DSICLKSOURCE_PHY)  || \
+                ((__SOURCE__) == RCC_DSICLKSOURCE_PLL2))
+#endif /*DSI*/
+
+#define IS_RCC_FMCCLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_FMCCLKSOURCE_D1HCLK)  || \
+                ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL)     || \
+                ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL2)    || \
+                ((__SOURCE__) == RCC_FMCCLKSOURCE_CLKP))
+
+#if defined(FDCAN1) || defined(FDCAN2)
+#define IS_RCC_FDCANCLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE)  || \
+                ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL2))
+#endif /*FDCAN1 || FDCAN2*/
+
+#define IS_RCC_SDMMC(__SOURCE__)   \
+                (((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL2))
+
+#define IS_RCC_ADCCLKSOURCE(SOURCE)    (((SOURCE) == RCC_ADCCLKSOURCE_PLL2) || \
+                                        ((SOURCE) == RCC_ADCCLKSOURCE_PLL3) || \
+                                        ((SOURCE) == RCC_ADCCLKSOURCE_CLKP))
+
+#define IS_RCC_SWPMI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SWPMI1CLKSOURCE_D2PCLK1) || \
+                                        ((SOURCE) == RCC_SWPMI1CLKSOURCE_HSI))
+
+#define IS_RCC_DFSDM1CLKSOURCE(SOURCE)  (((SOURCE) == RCC_DFSDM1CLKSOURCE_D2PCLK1) || \
+                                         ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYS))
+
+#if defined(DFSDM2_BASE)
+#define IS_RCC_DFSDM2CLKSOURCE(SOURCE)  (((SOURCE) == RCC_DFSDM2CLKSOURCE_SRDPCLK1) || \
+                                        ((SOURCE) == RCC_DFSDM2CLKSOURCE_SYS))
+#endif /*DFSDM2*/
+
+#define IS_RCC_SPDIFRXCLKSOURCE(SOURCE)(((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL)  || \
+                                        ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL2) || \
+                                        ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL3) || \
+                                        ((SOURCE) == RCC_SPDIFRXCLKSOURCE_HSI))
+
+#define IS_RCC_CECCLKSOURCE(SOURCE)  (((SOURCE) == RCC_CECCLKSOURCE_LSE) || \
+                                      ((SOURCE) == RCC_CECCLKSOURCE_LSI) || \
+                                      ((SOURCE) == RCC_CECCLKSOURCE_CSI))
+
+#define IS_RCC_CLKPSOURCE(SOURCE)   (((SOURCE) == RCC_CLKPSOURCE_HSI)  || \
+                                      ((SOURCE) == RCC_CLKPSOURCE_CSI) || \
+                                      ((SOURCE) == RCC_CLKPSOURCE_HSE))
+#define IS_RCC_TIMPRES(VALUE)  \
+               (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \
+                ((VALUE) == RCC_TIMPRES_ACTIVATED))
+
+#if defined(DUAL_CORE)
+#define IS_RCC_BOOT_CORE(CORE)   (((CORE) == RCC_BOOT_C1)  || \
+                                  ((CORE) == RCC_BOOT_C2))
+#endif /*DUAL_CORE*/
+
+#if defined(DUAL_CORE)
+#define IS_RCC_SCOPE_WWDG(WWDG)   (((WWDG) == RCC_WWDG1)  || \
+                                  ((WWDG) == RCC_WWDG2))
+#else
+#define IS_RCC_SCOPE_WWDG(WWDG)   ((WWDG) == RCC_WWDG1)
+
+#endif /*DUAL_CORE*/
+
+#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB2) || \
+                                            ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE)  || \
+                                            ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB1) || \
+                                            ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_PIN))
+
+#define IS_RCC_CRS_SYNC_DIV(__DIV__)       (((__DIV__) == RCC_CRS_SYNC_DIV1)  || ((__DIV__) == RCC_CRS_SYNC_DIV2)  || \
+                                            ((__DIV__) == RCC_CRS_SYNC_DIV4)  || ((__DIV__) == RCC_CRS_SYNC_DIV8)  || \
+                                            ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
+                                            ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))
+
+#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
+                                                ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
+
+#define IS_RCC_CRS_RELOADVALUE(__VALUE__)  (((__VALUE__) <= 0xFFFFU))
+
+#define IS_RCC_CRS_ERRORLIMIT(__VALUE__)   (((__VALUE__) <= 0xFFU))
+
+#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))
+
+#define IS_RCC_CRS_FREQERRORDIR(__DIR__)   (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
+                                            ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_RCC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h
new file mode 100644
index 00000000..37a7ada8
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h
@@ -0,0 +1,2285 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_tim.h
+  * @author  MCD Application Team
+  * @brief   Header file of TIM HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_TIM_H
+#define STM32H7xx_HAL_TIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup TIM
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TIM_Exported_Types TIM Exported Types
+  * @{
+  */
+
+/**
+  * @brief  TIM Time base Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
+                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+  uint32_t CounterMode;       /*!< Specifies the counter mode.
+                                   This parameter can be a value of @ref TIM_Counter_Mode */
+
+  uint32_t Period;            /*!< Specifies the period value to be loaded into the active
+                                   Auto-Reload Register at the next update event.
+                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.  */
+
+  uint32_t ClockDivision;     /*!< Specifies the clock division.
+                                   This parameter can be a value of @ref TIM_ClockDivision */
+
+  uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
+                                    reaches zero, an update event is generated and counting restarts
+                                    from the RCR value (N).
+                                    This means in PWM mode that (N+1) corresponds to:
+                                        - the number of PWM periods in edge-aligned mode
+                                        - the number of half PWM period in center-aligned mode
+                                     GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+                                     Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+  uint32_t AutoReloadPreload;  /*!< Specifies the auto-reload preload.
+                                   This parameter can be a value of @ref TIM_AutoReloadPreload */
+} TIM_Base_InitTypeDef;
+
+/**
+  * @brief  TIM Output Compare Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t OCMode;        /*!< Specifies the TIM mode.
+                               This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+  uint32_t OCPolarity;    /*!< Specifies the output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t OCFastMode;    /*!< Specifies the Fast mode state.
+                               This parameter can be a value of @ref TIM_Output_Fast_State
+                               @note This parameter is valid only in PWM1 and PWM2 mode. */
+
+
+  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+                               @note This parameter is valid only for timer instances supporting break feature. */
+} TIM_OC_InitTypeDef;
+
+/**
+  * @brief  TIM One Pulse Mode Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t OCMode;        /*!< Specifies the TIM mode.
+                               This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+  uint32_t OCPolarity;    /*!< Specifies the output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint32_t ICSelection;   /*!< Specifies the input.
+                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t ICFilter;      /*!< Specifies the input capture filter.
+                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_OnePulse_InitTypeDef;
+
+/**
+  * @brief  TIM Input Capture Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t  ICPolarity;  /*!< Specifies the active edge of the input signal.
+                              This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint32_t ICSelection;  /*!< Specifies the input.
+                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
+                              This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t ICFilter;     /*!< Specifies the input capture filter.
+                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_IC_InitTypeDef;
+
+/**
+  * @brief  TIM Encoder Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t EncoderMode;   /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Encoder_Mode */
+
+  uint32_t IC1Polarity;   /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
+
+  uint32_t IC1Selection;  /*!< Specifies the input.
+                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t IC1Prescaler;  /*!< Specifies the Input Capture Prescaler.
+                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t IC1Filter;     /*!< Specifies the input capture filter.
+                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+  uint32_t IC2Polarity;   /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
+
+  uint32_t IC2Selection;  /*!< Specifies the input.
+                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t IC2Prescaler;  /*!< Specifies the Input Capture Prescaler.
+                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t IC2Filter;     /*!< Specifies the input capture filter.
+                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_Encoder_InitTypeDef;
+
+/**
+  * @brief  Clock Configuration Handle Structure definition
+  */
+typedef struct
+{
+  uint32_t ClockSource;     /*!< TIM clock sources
+                                 This parameter can be a value of @ref TIM_Clock_Source */
+  uint32_t ClockPolarity;   /*!< TIM clock polarity
+                                 This parameter can be a value of @ref TIM_Clock_Polarity */
+  uint32_t ClockPrescaler;  /*!< TIM clock prescaler
+                                 This parameter can be a value of @ref TIM_Clock_Prescaler */
+  uint32_t ClockFilter;     /*!< TIM clock filter
+                                 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_ClockConfigTypeDef;
+
+/**
+  * @brief  TIM Clear Input Configuration Handle Structure definition
+  */
+typedef struct
+{
+  uint32_t ClearInputState;      /*!< TIM clear Input state
+                                      This parameter can be ENABLE or DISABLE */
+  uint32_t ClearInputSource;     /*!< TIM clear Input sources
+                                      This parameter can be a value of @ref TIM_ClearInput_Source */
+  uint32_t ClearInputPolarity;   /*!< TIM Clear Input polarity
+                                      This parameter can be a value of @ref TIM_ClearInput_Polarity */
+  uint32_t ClearInputPrescaler;  /*!< TIM Clear Input prescaler
+                                      This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */
+  uint32_t ClearInputFilter;     /*!< TIM Clear Input filter
+                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_ClearInputConfigTypeDef;
+
+/**
+  * @brief  TIM Master configuration Structure definition
+  * @note   Advanced timers provide TRGO2 internal line which is redirected
+  *         to the ADC
+  */
+typedef struct
+{
+  uint32_t  MasterOutputTrigger;   /*!< Trigger output (TRGO) selection
+                                        This parameter can be a value of @ref TIM_Master_Mode_Selection */
+  uint32_t  MasterOutputTrigger2;  /*!< Trigger output2 (TRGO2) selection
+                                        This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */
+  uint32_t  MasterSlaveMode;       /*!< Master/slave mode selection
+                                        This parameter can be a value of @ref TIM_Master_Slave_Mode
+                                        @note When the Master/slave mode is enabled, the effect of
+                                        an event on the trigger input (TRGI) is delayed to allow a
+                                        perfect synchronization between the current timer and its
+                                        slaves (through TRGO). It is not mandatory in case of timer
+                                        synchronization mode. */
+} TIM_MasterConfigTypeDef;
+
+/**
+  * @brief  TIM Slave configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t  SlaveMode;         /*!< Slave mode selection
+                                    This parameter can be a value of @ref TIM_Slave_Mode */
+  uint32_t  InputTrigger;      /*!< Input Trigger source
+                                    This parameter can be a value of @ref TIM_Trigger_Selection */
+  uint32_t  TriggerPolarity;   /*!< Input Trigger polarity
+                                    This parameter can be a value of @ref TIM_Trigger_Polarity */
+  uint32_t  TriggerPrescaler;  /*!< Input trigger prescaler
+                                    This parameter can be a value of @ref TIM_Trigger_Prescaler */
+  uint32_t  TriggerFilter;     /*!< Input trigger filter
+                                    This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF  */
+
+} TIM_SlaveConfigTypeDef;
+
+/**
+  * @brief  TIM Break input(s) and Dead time configuration Structure definition
+  * @note   2 break inputs can be configured (BKIN and BKIN2) with configurable
+  *        filter and polarity.
+  */
+typedef struct
+{
+  uint32_t OffStateRunMode;      /*!< TIM off state in run mode
+                                      This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
+  uint32_t OffStateIDLEMode;     /*!< TIM off state in IDLE mode
+                                      This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
+  uint32_t LockLevel;            /*!< TIM Lock level
+                                      This parameter can be a value of @ref TIM_Lock_level */
+  uint32_t DeadTime;             /*!< TIM dead Time
+                                      This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+  uint32_t BreakState;           /*!< TIM Break State
+                                      This parameter can be a value of @ref TIM_Break_Input_enable_disable */
+  uint32_t BreakPolarity;        /*!< TIM Break input polarity
+                                      This parameter can be a value of @ref TIM_Break_Polarity */
+  uint32_t BreakFilter;          /*!< Specifies the break input filter.
+                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+  uint32_t Break2State;          /*!< TIM Break2 State
+                                      This parameter can be a value of @ref TIM_Break2_Input_enable_disable */
+  uint32_t Break2Polarity;       /*!< TIM Break2 input polarity
+                                      This parameter can be a value of @ref TIM_Break2_Polarity */
+  uint32_t Break2Filter;         /*!< TIM break2 input filter.
+                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+  uint32_t AutomaticOutput;      /*!< TIM Automatic Output Enable state
+                                      This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+} TIM_BreakDeadTimeConfigTypeDef;
+
+/**
+  * @brief  HAL State structures definition
+  */
+typedef enum
+{
+  HAL_TIM_STATE_RESET             = 0x00U,    /*!< Peripheral not yet initialized or disabled  */
+  HAL_TIM_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */
+  HAL_TIM_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */
+  HAL_TIM_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */
+  HAL_TIM_STATE_ERROR             = 0x04U     /*!< Reception process is ongoing                */
+} HAL_TIM_StateTypeDef;
+
+/**
+  * @brief  HAL Active channel structures definition
+  */
+typedef enum
+{
+  HAL_TIM_ACTIVE_CHANNEL_1        = 0x01U,    /*!< The active channel is 1     */
+  HAL_TIM_ACTIVE_CHANNEL_2        = 0x02U,    /*!< The active channel is 2     */
+  HAL_TIM_ACTIVE_CHANNEL_3        = 0x04U,    /*!< The active channel is 3     */
+  HAL_TIM_ACTIVE_CHANNEL_4        = 0x08U,    /*!< The active channel is 4     */
+  HAL_TIM_ACTIVE_CHANNEL_5        = 0x10U,    /*!< The active channel is 5     */
+  HAL_TIM_ACTIVE_CHANNEL_6        = 0x20U,    /*!< The active channel is 6     */
+  HAL_TIM_ACTIVE_CHANNEL_CLEARED  = 0x00U     /*!< All active channels cleared */
+} HAL_TIM_ActiveChannel;
+
+/**
+  * @brief  TIM Time Base Handle Structure definition
+  */
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+typedef struct __TIM_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+{
+  TIM_TypeDef                 *Instance;     /*!< Register base address             */
+  TIM_Base_InitTypeDef        Init;          /*!< TIM Time Base required parameters */
+  HAL_TIM_ActiveChannel       Channel;       /*!< Active channel                    */
+  DMA_HandleTypeDef           *hdma[7];      /*!< DMA Handlers array
+                                                  This array is accessed by a @ref DMA_Handle_index */
+  HAL_LockTypeDef             Lock;          /*!< Locking object                    */
+  __IO HAL_TIM_StateTypeDef   State;         /*!< TIM operation state               */
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM Base Msp Init Callback                              */
+  void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);            /*!< TIM Base Msp DeInit Callback                            */
+  void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM IC Msp Init Callback                                */
+  void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM IC Msp DeInit Callback                              */
+  void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM OC Msp Init Callback                                */
+  void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM OC Msp DeInit Callback                              */
+  void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM PWM Msp Init Callback                               */
+  void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM PWM Msp DeInit Callback                             */
+  void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim);          /*!< TIM One Pulse Msp Init Callback                         */
+  void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM One Pulse Msp DeInit Callback                       */
+  void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Encoder Msp Init Callback                           */
+  void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM Encoder Msp DeInit Callback                         */
+  void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Hall Sensor Msp Init Callback                       */
+  void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);      /*!< TIM Hall Sensor Msp DeInit Callback                     */
+  void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM Period Elapsed Callback                             */
+  void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);     /*!< TIM Period Elapsed half complete Callback               */
+  void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim);                   /*!< TIM Trigger Callback                                    */
+  void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Trigger half complete Callback                      */
+  void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM Input Capture Callback                              */
+  void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Input Capture half complete Callback                */
+  void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Output Compare Delay Elapsed Callback               */
+  void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM PWM Pulse Finished Callback                         */
+  void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback           */
+  void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Error Callback                                      */
+  void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM Commutation Callback                                */
+  void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);       /*!< TIM Commutation half complete Callback                  */
+  void (* BreakCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Break Callback                                      */
+  void (* Break2Callback)(struct __TIM_HandleTypeDef *htim);                    /*!< TIM Break2 Callback                                     */
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+} TIM_HandleTypeDef;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL TIM Callback ID enumeration definition
+  */
+typedef enum
+{
+   HAL_TIM_BASE_MSPINIT_CB_ID            = 0x00U    /*!< TIM Base MspInit Callback ID                              */
+  ,HAL_TIM_BASE_MSPDEINIT_CB_ID          = 0x01U    /*!< TIM Base MspDeInit Callback ID                            */
+  ,HAL_TIM_IC_MSPINIT_CB_ID              = 0x02U    /*!< TIM IC MspInit Callback ID                                */
+  ,HAL_TIM_IC_MSPDEINIT_CB_ID            = 0x03U    /*!< TIM IC MspDeInit Callback ID                              */
+  ,HAL_TIM_OC_MSPINIT_CB_ID              = 0x04U    /*!< TIM OC MspInit Callback ID                                */
+  ,HAL_TIM_OC_MSPDEINIT_CB_ID            = 0x05U    /*!< TIM OC MspDeInit Callback ID                              */
+  ,HAL_TIM_PWM_MSPINIT_CB_ID             = 0x06U    /*!< TIM PWM MspInit Callback ID                               */
+  ,HAL_TIM_PWM_MSPDEINIT_CB_ID           = 0x07U    /*!< TIM PWM MspDeInit Callback ID                             */
+  ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID       = 0x08U    /*!< TIM One Pulse MspInit Callback ID                         */
+  ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID     = 0x09U    /*!< TIM One Pulse MspDeInit Callback ID                       */
+  ,HAL_TIM_ENCODER_MSPINIT_CB_ID         = 0x0AU    /*!< TIM Encoder MspInit Callback ID                           */
+  ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID       = 0x0BU    /*!< TIM Encoder MspDeInit Callback ID                         */
+  ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID     = 0x0CU    /*!< TIM Hall Sensor MspDeInit Callback ID                     */
+  ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID   = 0x0DU    /*!< TIM Hall Sensor MspDeInit Callback ID                     */
+  ,HAL_TIM_PERIOD_ELAPSED_CB_ID          = 0x0EU    /*!< TIM Period Elapsed Callback ID                             */
+  ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID     = 0x0FU    /*!< TIM Period Elapsed half complete Callback ID               */
+  ,HAL_TIM_TRIGGER_CB_ID                 = 0x10U    /*!< TIM Trigger Callback ID                                    */
+  ,HAL_TIM_TRIGGER_HALF_CB_ID            = 0x11U    /*!< TIM Trigger half complete Callback ID                      */
+
+  ,HAL_TIM_IC_CAPTURE_CB_ID              = 0x12U    /*!< TIM Input Capture Callback ID                              */
+  ,HAL_TIM_IC_CAPTURE_HALF_CB_ID         = 0x13U    /*!< TIM Input Capture half complete Callback ID                */
+  ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID        = 0x14U    /*!< TIM Output Compare Delay Elapsed Callback ID               */
+  ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID      = 0x15U    /*!< TIM PWM Pulse Finished Callback ID           */
+  ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U    /*!< TIM PWM Pulse Finished half complete Callback ID           */
+  ,HAL_TIM_ERROR_CB_ID                   = 0x17U    /*!< TIM Error Callback ID                                      */
+  ,HAL_TIM_COMMUTATION_CB_ID             = 0x18U    /*!< TIM Commutation Callback ID                                */
+  ,HAL_TIM_COMMUTATION_HALF_CB_ID        = 0x19U    /*!< TIM Commutation half complete Callback ID                  */
+  ,HAL_TIM_BREAK_CB_ID                   = 0x1AU    /*!< TIM Break Callback ID                                      */
+  ,HAL_TIM_BREAK2_CB_ID                  = 0x1BU    /*!< TIM Break2 Callback ID                                     */
+} HAL_TIM_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL TIM Callback pointer definition
+  */
+typedef  void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);  /*!< pointer to the TIM callback function */
+
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+/* End of exported types -----------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIM_Exported_Constants TIM Exported Constants
+  * @{
+  */
+
+/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
+  * @{
+  */
+#define TIM_CLEARINPUTSOURCE_NONE           0x00000000U   /*!< OCREF_CLR is disabled */
+#define TIM_CLEARINPUTSOURCE_ETR            0x00000001U   /*!< OCREF_CLR is connected to ETRF input */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
+  * @{
+  */
+#define TIM_DMABASE_CR1                    0x00000000U
+#define TIM_DMABASE_CR2                    0x00000001U
+#define TIM_DMABASE_SMCR                   0x00000002U
+#define TIM_DMABASE_DIER                   0x00000003U
+#define TIM_DMABASE_SR                     0x00000004U
+#define TIM_DMABASE_EGR                    0x00000005U
+#define TIM_DMABASE_CCMR1                  0x00000006U
+#define TIM_DMABASE_CCMR2                  0x00000007U
+#define TIM_DMABASE_CCER                   0x00000008U
+#define TIM_DMABASE_CNT                    0x00000009U
+#define TIM_DMABASE_PSC                    0x0000000AU
+#define TIM_DMABASE_ARR                    0x0000000BU
+#define TIM_DMABASE_RCR                    0x0000000CU
+#define TIM_DMABASE_CCR1                   0x0000000DU
+#define TIM_DMABASE_CCR2                   0x0000000EU
+#define TIM_DMABASE_CCR3                   0x0000000FU
+#define TIM_DMABASE_CCR4                   0x00000010U
+#define TIM_DMABASE_BDTR                   0x00000011U
+#define TIM_DMABASE_DCR                    0x00000012U
+#define TIM_DMABASE_DMAR                   0x00000013U
+#define TIM_DMABASE_CCMR3                  0x00000015U
+#define TIM_DMABASE_CCR5                   0x00000016U
+#define TIM_DMABASE_CCR6                   0x00000017U
+#if   defined(TIM_BREAK_INPUT_SUPPORT)
+#define TIM_DMABASE_AF1                    0x00000018U
+#define TIM_DMABASE_AF2                    0x00000019U
+#endif /* TIM_BREAK_INPUT_SUPPORT */
+#define TIM_DMABASE_TISEL                  0x0000001AU
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Event_Source TIM Event Source
+  * @{
+  */
+#define TIM_EVENTSOURCE_UPDATE              TIM_EGR_UG     /*!< Reinitialize the counter and generates an update of the registers */
+#define TIM_EVENTSOURCE_CC1                 TIM_EGR_CC1G   /*!< A capture/compare event is generated on channel 1 */
+#define TIM_EVENTSOURCE_CC2                 TIM_EGR_CC2G   /*!< A capture/compare event is generated on channel 2 */
+#define TIM_EVENTSOURCE_CC3                 TIM_EGR_CC3G   /*!< A capture/compare event is generated on channel 3 */
+#define TIM_EVENTSOURCE_CC4                 TIM_EGR_CC4G   /*!< A capture/compare event is generated on channel 4 */
+#define TIM_EVENTSOURCE_COM                 TIM_EGR_COMG   /*!< A commutation event is generated */
+#define TIM_EVENTSOURCE_TRIGGER             TIM_EGR_TG     /*!< A trigger event is generated */
+#define TIM_EVENTSOURCE_BREAK               TIM_EGR_BG     /*!< A break event is generated */
+#define TIM_EVENTSOURCE_BREAK2              TIM_EGR_B2G    /*!< A break 2 event is generated */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
+  * @{
+  */
+#define  TIM_INPUTCHANNELPOLARITY_RISING      0x00000000U                       /*!< Polarity for TIx source */
+#define  TIM_INPUTCHANNELPOLARITY_FALLING     TIM_CCER_CC1P                     /*!< Polarity for TIx source */
+#define  TIM_INPUTCHANNELPOLARITY_BOTHEDGE    (TIM_CCER_CC1P | TIM_CCER_CC1NP)  /*!< Polarity for TIx source */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
+  * @{
+  */
+#define TIM_ETRPOLARITY_INVERTED              TIM_SMCR_ETP                      /*!< Polarity for ETR source */
+#define TIM_ETRPOLARITY_NONINVERTED           0x00000000U                       /*!< Polarity for ETR source */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
+  * @{
+  */
+#define TIM_ETRPRESCALER_DIV1                 0x00000000U                       /*!< No prescaler is used */
+#define TIM_ETRPRESCALER_DIV2                 TIM_SMCR_ETPS_0                   /*!< ETR input source is divided by 2 */
+#define TIM_ETRPRESCALER_DIV4                 TIM_SMCR_ETPS_1                   /*!< ETR input source is divided by 4 */
+#define TIM_ETRPRESCALER_DIV8                 TIM_SMCR_ETPS                     /*!< ETR input source is divided by 8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Counter_Mode TIM Counter Mode
+  * @{
+  */
+#define TIM_COUNTERMODE_UP                 0x00000000U                          /*!< Counter used as up-counter   */
+#define TIM_COUNTERMODE_DOWN               TIM_CR1_DIR                          /*!< Counter used as down-counter */
+#define TIM_COUNTERMODE_CENTERALIGNED1     TIM_CR1_CMS_0                        /*!< Center-aligned mode 1        */
+#define TIM_COUNTERMODE_CENTERALIGNED2     TIM_CR1_CMS_1                        /*!< Center-aligned mode 2        */
+#define TIM_COUNTERMODE_CENTERALIGNED3     TIM_CR1_CMS                          /*!< Center-aligned mode 3        */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap
+  * @{
+  */
+#define TIM_UIFREMAP_DISABLE               0x00000000U                          /*!< Update interrupt flag remap disabled */
+#define TIM_UIFREMAP_ENABLE                TIM_CR1_UIFREMAP                     /*!< Update interrupt flag remap enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ClockDivision TIM Clock Division
+  * @{
+  */
+#define TIM_CLOCKDIVISION_DIV1             0x00000000U                          /*!< Clock division: tDTS=tCK_INT   */
+#define TIM_CLOCKDIVISION_DIV2             TIM_CR1_CKD_0                        /*!< Clock division: tDTS=2*tCK_INT */
+#define TIM_CLOCKDIVISION_DIV4             TIM_CR1_CKD_1                        /*!< Clock division: tDTS=4*tCK_INT */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_State TIM Output Compare State
+  * @{
+  */
+#define TIM_OUTPUTSTATE_DISABLE            0x00000000U                          /*!< Capture/Compare 1 output disabled */
+#define TIM_OUTPUTSTATE_ENABLE             TIM_CCER_CC1E                        /*!< Capture/Compare 1 output enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
+  * @{
+  */
+#define TIM_AUTORELOAD_PRELOAD_DISABLE                0x00000000U               /*!< TIMx_ARR register is not buffered */
+#define TIM_AUTORELOAD_PRELOAD_ENABLE                 TIM_CR1_ARPE              /*!< TIMx_ARR register is buffered */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Fast_State TIM Output Fast State
+  * @{
+  */
+#define TIM_OCFAST_DISABLE                 0x00000000U                          /*!< Output Compare fast disable */
+#define TIM_OCFAST_ENABLE                  TIM_CCMR1_OC1FE                      /*!< Output Compare fast enable  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
+  * @{
+  */
+#define TIM_OUTPUTNSTATE_DISABLE           0x00000000U                          /*!< OCxN is disabled  */
+#define TIM_OUTPUTNSTATE_ENABLE            TIM_CCER_CC1NE                       /*!< OCxN is enabled   */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
+  * @{
+  */
+#define TIM_OCPOLARITY_HIGH                0x00000000U                          /*!< Capture/Compare output polarity  */
+#define TIM_OCPOLARITY_LOW                 TIM_CCER_CC1P                        /*!< Capture/Compare output polarity  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
+  * @{
+  */
+#define TIM_OCNPOLARITY_HIGH               0x00000000U                          /*!< Capture/Compare complementary output polarity */
+#define TIM_OCNPOLARITY_LOW                TIM_CCER_CC1NP                       /*!< Capture/Compare complementary output polarity */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
+  * @{
+  */
+#define TIM_OCIDLESTATE_SET                TIM_CR2_OIS1                         /*!< Output Idle state: OCx=1 when MOE=0 */
+#define TIM_OCIDLESTATE_RESET              0x00000000U                          /*!< Output Idle state: OCx=0 when MOE=0 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
+  * @{
+  */
+#define TIM_OCNIDLESTATE_SET               TIM_CR2_OIS1N                        /*!< Complementary output Idle state: OCxN=1 when MOE=0 */
+#define TIM_OCNIDLESTATE_RESET             0x00000000U                          /*!< Complementary output Idle state: OCxN=0 when MOE=0 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
+  * @{
+  */
+#define  TIM_ICPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING      /*!< Capture triggered by rising edge on timer input                  */
+#define  TIM_ICPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Capture triggered by falling edge on timer input                 */
+#define  TIM_ICPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE    /*!< Capture triggered by both rising and falling edges on timer input*/
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
+  * @{
+  */
+#define  TIM_ENCODERINPUTPOLARITY_RISING   TIM_INPUTCHANNELPOLARITY_RISING      /*!< Encoder input with rising edge polarity  */
+#define  TIM_ENCODERINPUTPOLARITY_FALLING  TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Encoder input with falling edge polarity */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
+  * @{
+  */
+#define TIM_ICSELECTION_DIRECTTI           TIM_CCMR1_CC1S_0                     /*!< TIM Input 1, 2, 3 or 4 is selected to be
+                                                                                     connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSELECTION_INDIRECTTI         TIM_CCMR1_CC1S_1                     /*!< TIM Input 1, 2, 3 or 4 is selected to be
+                                                                                     connected to IC2, IC1, IC4 or IC3, respectively */
+#define TIM_ICSELECTION_TRC                TIM_CCMR1_CC1S                       /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
+  * @{
+  */
+#define TIM_ICPSC_DIV1                     0x00000000U                          /*!< Capture performed each time an edge is detected on the capture input */
+#define TIM_ICPSC_DIV2                     TIM_CCMR1_IC1PSC_0                   /*!< Capture performed once every 2 events                                */
+#define TIM_ICPSC_DIV4                     TIM_CCMR1_IC1PSC_1                   /*!< Capture performed once every 4 events                                */
+#define TIM_ICPSC_DIV8                     TIM_CCMR1_IC1PSC                     /*!< Capture performed once every 8 events                                */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
+  * @{
+  */
+#define TIM_OPMODE_SINGLE                  TIM_CR1_OPM                          /*!< Counter stops counting at the next update event */
+#define TIM_OPMODE_REPETITIVE              0x00000000U                          /*!< Counter is not stopped at update event          */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
+  * @{
+  */
+#define TIM_ENCODERMODE_TI1                      TIM_SMCR_SMS_0                                                      /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level  */
+#define TIM_ENCODERMODE_TI2                      TIM_SMCR_SMS_1                                                      /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */
+#define TIM_ENCODERMODE_TI12                     (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                                   /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
+  * @{
+  */
+#define TIM_IT_UPDATE                      TIM_DIER_UIE                         /*!< Update interrupt            */
+#define TIM_IT_CC1                         TIM_DIER_CC1IE                       /*!< Capture/Compare 1 interrupt */
+#define TIM_IT_CC2                         TIM_DIER_CC2IE                       /*!< Capture/Compare 2 interrupt */
+#define TIM_IT_CC3                         TIM_DIER_CC3IE                       /*!< Capture/Compare 3 interrupt */
+#define TIM_IT_CC4                         TIM_DIER_CC4IE                       /*!< Capture/Compare 4 interrupt */
+#define TIM_IT_COM                         TIM_DIER_COMIE                       /*!< Commutation interrupt       */
+#define TIM_IT_TRIGGER                     TIM_DIER_TIE                         /*!< Trigger interrupt           */
+#define TIM_IT_BREAK                       TIM_DIER_BIE                         /*!< Break interrupt             */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Commutation_Source  TIM Commutation Source
+  * @{
+  */
+#define TIM_COMMUTATION_TRGI              TIM_CR2_CCUS                          /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */
+#define TIM_COMMUTATION_SOFTWARE          0x00000000U                           /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_DMA_sources TIM DMA Sources
+  * @{
+  */
+#define TIM_DMA_UPDATE                     TIM_DIER_UDE                         /*!< DMA request is triggered by the update event */
+#define TIM_DMA_CC1                        TIM_DIER_CC1DE                       /*!< DMA request is triggered by the capture/compare macth 1 event */
+#define TIM_DMA_CC2                        TIM_DIER_CC2DE                       /*!< DMA request is triggered by the capture/compare macth 2 event event */
+#define TIM_DMA_CC3                        TIM_DIER_CC3DE                       /*!< DMA request is triggered by the capture/compare macth 3 event event */
+#define TIM_DMA_CC4                        TIM_DIER_CC4DE                       /*!< DMA request is triggered by the capture/compare macth 4 event event */
+#define TIM_DMA_COM                        TIM_DIER_COMDE                       /*!< DMA request is triggered by the commutation event */
+#define TIM_DMA_TRIGGER                    TIM_DIER_TDE                         /*!< DMA request is triggered by the trigger event */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Flag_definition TIM Flag Definition
+  * @{
+  */
+#define TIM_FLAG_UPDATE                    TIM_SR_UIF                           /*!< Update interrupt flag         */
+#define TIM_FLAG_CC1                       TIM_SR_CC1IF                         /*!< Capture/Compare 1 interrupt flag */
+#define TIM_FLAG_CC2                       TIM_SR_CC2IF                         /*!< Capture/Compare 2 interrupt flag */
+#define TIM_FLAG_CC3                       TIM_SR_CC3IF                         /*!< Capture/Compare 3 interrupt flag */
+#define TIM_FLAG_CC4                       TIM_SR_CC4IF                         /*!< Capture/Compare 4 interrupt flag */
+#define TIM_FLAG_CC5                       TIM_SR_CC5IF                         /*!< Capture/Compare 5 interrupt flag */
+#define TIM_FLAG_CC6                       TIM_SR_CC6IF                         /*!< Capture/Compare 6 interrupt flag */
+#define TIM_FLAG_COM                       TIM_SR_COMIF                         /*!< Commutation interrupt flag    */
+#define TIM_FLAG_TRIGGER                   TIM_SR_TIF                           /*!< Trigger interrupt flag        */
+#define TIM_FLAG_BREAK                     TIM_SR_BIF                           /*!< Break interrupt flag          */
+#define TIM_FLAG_BREAK2                    TIM_SR_B2IF                          /*!< Break 2 interrupt flag        */
+#define TIM_FLAG_SYSTEM_BREAK              TIM_SR_SBIF                          /*!< System Break interrupt flag   */
+#define TIM_FLAG_CC1OF                     TIM_SR_CC1OF                         /*!< Capture 1 overcapture flag    */
+#define TIM_FLAG_CC2OF                     TIM_SR_CC2OF                         /*!< Capture 2 overcapture flag    */
+#define TIM_FLAG_CC3OF                     TIM_SR_CC3OF                         /*!< Capture 3 overcapture flag    */
+#define TIM_FLAG_CC4OF                     TIM_SR_CC4OF                         /*!< Capture 4 overcapture flag    */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Channel TIM Channel
+  * @{
+  */
+#define TIM_CHANNEL_1                      0x00000000U                          /*!< Capture/compare channel 1 identifier      */
+#define TIM_CHANNEL_2                      0x00000004U                          /*!< Capture/compare channel 2 identifier      */
+#define TIM_CHANNEL_3                      0x00000008U                          /*!< Capture/compare channel 3 identifier      */
+#define TIM_CHANNEL_4                      0x0000000CU                          /*!< Capture/compare channel 4 identifier      */
+#define TIM_CHANNEL_5                      0x00000010U                          /*!< Compare channel 5 identifier              */
+#define TIM_CHANNEL_6                      0x00000014U                          /*!< Compare channel 6 identifier              */
+#define TIM_CHANNEL_ALL                    0x0000003CU                          /*!< Global Capture/compare channel identifier  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Clock_Source TIM Clock Source
+  * @{
+  */
+#define TIM_CLOCKSOURCE_ETRMODE2    TIM_SMCR_ETPS_1      /*!< External clock source mode 2                          */
+#define TIM_CLOCKSOURCE_INTERNAL    TIM_SMCR_ETPS_0      /*!< Internal clock source                                 */
+#define TIM_CLOCKSOURCE_ITR0        TIM_TS_ITR0          /*!< External clock source mode 1 (ITR0)                   */
+#define TIM_CLOCKSOURCE_ITR1        TIM_TS_ITR1          /*!< External clock source mode 1 (ITR1)                   */
+#define TIM_CLOCKSOURCE_ITR2        TIM_TS_ITR2          /*!< External clock source mode 1 (ITR2)                   */
+#define TIM_CLOCKSOURCE_ITR3        TIM_TS_ITR3          /*!< External clock source mode 1 (ITR3)                   */
+#define TIM_CLOCKSOURCE_TI1ED       TIM_TS_TI1F_ED       /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
+#define TIM_CLOCKSOURCE_TI1         TIM_TS_TI1FP1        /*!< External clock source mode 1 (TTI1FP1)                */
+#define TIM_CLOCKSOURCE_TI2         TIM_TS_TI2FP2        /*!< External clock source mode 1 (TTI2FP2)                */
+#define TIM_CLOCKSOURCE_ETRMODE1    TIM_TS_ETRF          /*!< External clock source mode 1 (ETRF)                   */
+#define TIM_CLOCKSOURCE_ITR4        TIM_TS_ITR4          /*!< External clock source mode 1 (ITR4)                   */
+#define TIM_CLOCKSOURCE_ITR5        TIM_TS_ITR5          /*!< External clock source mode 1 (ITR5)                   */
+#define TIM_CLOCKSOURCE_ITR6        TIM_TS_ITR6          /*!< External clock source mode 1 (ITR6)                   */
+#define TIM_CLOCKSOURCE_ITR7        TIM_TS_ITR7          /*!< External clock source mode 1 (ITR7)                   */
+#define TIM_CLOCKSOURCE_ITR8        TIM_TS_ITR8          /*!< External clock source mode 1 (ITR8)                   */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
+  * @{
+  */
+#define TIM_CLOCKPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED           /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED        /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING    /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING   /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE  /*!< Polarity for TIx clock sources */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
+  * @{
+  */
+#define TIM_CLOCKPRESCALER_DIV1                 TIM_ETRPRESCALER_DIV1           /*!< No prescaler is used                                                     */
+#define TIM_CLOCKPRESCALER_DIV2                 TIM_ETRPRESCALER_DIV2           /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
+#define TIM_CLOCKPRESCALER_DIV4                 TIM_ETRPRESCALER_DIV4           /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
+#define TIM_CLOCKPRESCALER_DIV8                 TIM_ETRPRESCALER_DIV8           /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
+  * @{
+  */
+#define TIM_CLEARINPUTPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED      /*!< Polarity for ETRx pin */
+#define TIM_CLEARINPUTPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED   /*!< Polarity for ETRx pin */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
+  * @{
+  */
+#define TIM_CLEARINPUTPRESCALER_DIV1              TIM_ETRPRESCALER_DIV1         /*!< No prescaler is used                                                   */
+#define TIM_CLEARINPUTPRESCALER_DIV2              TIM_ETRPRESCALER_DIV2         /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV4              TIM_ETRPRESCALER_DIV4         /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV8              TIM_ETRPRESCALER_DIV8         /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
+  * @{
+  */
+#define TIM_OSSR_ENABLE                          TIM_BDTR_OSSR                  /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer)           */
+#define TIM_OSSR_DISABLE                         0x00000000U                    /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
+  * @{
+  */
+#define TIM_OSSI_ENABLE                          TIM_BDTR_OSSI                  /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer)           */
+#define TIM_OSSI_DISABLE                         0x00000000U                    /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
+/**
+  * @}
+  */
+/** @defgroup TIM_Lock_level  TIM Lock level
+  * @{
+  */
+#define TIM_LOCKLEVEL_OFF                  0x00000000U                          /*!< LOCK OFF     */
+#define TIM_LOCKLEVEL_1                    TIM_BDTR_LOCK_0                      /*!< LOCK Level 1 */
+#define TIM_LOCKLEVEL_2                    TIM_BDTR_LOCK_1                      /*!< LOCK Level 2 */
+#define TIM_LOCKLEVEL_3                    TIM_BDTR_LOCK                        /*!< LOCK Level 3 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
+  * @{
+  */
+#define TIM_BREAK_ENABLE                   TIM_BDTR_BKE                         /*!< Break input BRK is enabled  */
+#define TIM_BREAK_DISABLE                  0x00000000U                          /*!< Break input BRK is disabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
+  * @{
+  */
+#define TIM_BREAKPOLARITY_LOW              0x00000000U                          /*!< Break input BRK is active low  */
+#define TIM_BREAKPOLARITY_HIGH             TIM_BDTR_BKP                         /*!< Break input BRK is active high */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable
+  * @{
+  */
+#define TIM_BREAK2_DISABLE                 0x00000000U                          /*!< Break input BRK2 is disabled  */
+#define TIM_BREAK2_ENABLE                  TIM_BDTR_BK2E                        /*!< Break input BRK2 is enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity
+  * @{
+  */
+#define TIM_BREAK2POLARITY_LOW             0x00000000U                          /*!< Break input BRK2 is active low   */
+#define TIM_BREAK2POLARITY_HIGH            TIM_BDTR_BK2P                        /*!< Break input BRK2 is active high  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
+  * @{
+  */
+#define TIM_AUTOMATICOUTPUT_DISABLE        0x00000000U                          /*!< MOE can be set only by software */
+#define TIM_AUTOMATICOUTPUT_ENABLE         TIM_BDTR_AOE                         /*!< MOE can be set by software or automatically at the next update event 
+                                                                                    (if none of the break inputs BRK and BRK2 is active) */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3
+  * @{
+  */
+#define TIM_GROUPCH5_NONE                  0x00000000U                          /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
+#define TIM_GROUPCH5_OC1REFC               TIM_CCR5_GC5C1                       /* !< OC1REFC is the logical AND of OC1REFC and OC5REF    */
+#define TIM_GROUPCH5_OC2REFC               TIM_CCR5_GC5C2                       /* !< OC2REFC is the logical AND of OC2REFC and OC5REF    */
+#define TIM_GROUPCH5_OC3REFC               TIM_CCR5_GC5C3                       /* !< OC3REFC is the logical AND of OC3REFC and OC5REF    */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
+  * @{
+  */
+#define TIM_TRGO_RESET            0x00000000U                                      /*!< TIMx_EGR.UG bit is used as trigger output (TRGO)              */
+#define TIM_TRGO_ENABLE           TIM_CR2_MMS_0                                    /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO)             */
+#define TIM_TRGO_UPDATE           TIM_CR2_MMS_1                                    /*!< Update event is used as trigger output (TRGO)                 */
+#define TIM_TRGO_OC1              (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                  /*!< Capture or a compare match 1 is used as trigger output (TRGO) */
+#define TIM_TRGO_OC1REF           TIM_CR2_MMS_2                                    /*!< OC1REF signal is used as trigger output (TRGO)                */
+#define TIM_TRGO_OC2REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                  /*!< OC2REF signal is used as trigger output(TRGO)                 */
+#define TIM_TRGO_OC3REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                  /*!< OC3REF signal is used as trigger output(TRGO)                 */
+#define TIM_TRGO_OC4REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)  /*!< OC4REF signal is used as trigger output(TRGO)                 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2)
+  * @{
+  */
+#define TIM_TRGO2_RESET                          0x00000000U                                                         /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2)              */
+#define TIM_TRGO2_ENABLE                         TIM_CR2_MMS2_0                                                      /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2)             */
+#define TIM_TRGO2_UPDATE                         TIM_CR2_MMS2_1                                                      /*!< Update event is used as trigger output (TRGO2)                 */
+#define TIM_TRGO2_OC1                            (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                                   /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */
+#define TIM_TRGO2_OC1REF                         TIM_CR2_MMS2_2                                                      /*!< OC1REF signal is used as trigger output (TRGO2)                */
+#define TIM_TRGO2_OC2REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                                   /*!< OC2REF signal is used as trigger output (TRGO2)                */
+#define TIM_TRGO2_OC3REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)                                   /*!< OC3REF signal is used as trigger output (TRGO2)                */
+#define TIM_TRGO2_OC4REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC4REF signal is used as trigger output (TRGO2)                */
+#define TIM_TRGO2_OC5REF                         TIM_CR2_MMS2_3                                                      /*!< OC5REF signal is used as trigger output (TRGO2)                */
+#define TIM_TRGO2_OC6REF                         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)                                   /*!< OC6REF signal is used as trigger output (TRGO2)                */
+#define TIM_TRGO2_OC4REF_RISINGFALLING           (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)                                   /*!< OC4REF rising or falling edges generate pulses on TRGO2        */
+#define TIM_TRGO2_OC6REF_RISINGFALLING           (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC6REF rising or falling edges generate pulses on TRGO2        */
+#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)                                   /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2         */
+#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING   (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                  /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */
+#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)                   /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2         */
+#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING   (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2         */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
+  * @{
+  */
+#define TIM_MASTERSLAVEMODE_ENABLE         TIM_SMCR_MSM                         /*!< No action */
+#define TIM_MASTERSLAVEMODE_DISABLE        0x00000000U                          /*!< Master/slave mode is selected */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Slave_Mode TIM Slave mode
+  * @{
+  */
+#define TIM_SLAVEMODE_DISABLE                0x00000000U                                        /*!< Slave mode disabled           */
+#define TIM_SLAVEMODE_RESET                  TIM_SMCR_SMS_2                                     /*!< Reset Mode                    */
+#define TIM_SLAVEMODE_GATED                  (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)                  /*!< Gated Mode                    */
+#define TIM_SLAVEMODE_TRIGGER                (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)                  /*!< Trigger Mode                  */
+#define TIM_SLAVEMODE_EXTERNAL1              (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1         */
+#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER  TIM_SMCR_SMS_3                                     /*!< Combined reset + trigger mode */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
+  * @{
+  */
+#define TIM_OCMODE_TIMING                   0x00000000U                                              /*!< Frozen                                 */
+#define TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!< Set channel to active level on match   */
+#define TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!< Set channel to inactive level on match */
+#define TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!< Toggle                                 */
+#define TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!< PWM mode 1                             */
+#define TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2                             */
+#define TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!< Force active level                     */
+#define TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                         /*!< Force inactive level                   */
+#define TIM_OCMODE_RETRIGERRABLE_OPM1      TIM_CCMR1_OC1M_3                                          /*!< Retrigerrable OPM mode 1               */
+#define TIM_OCMODE_RETRIGERRABLE_OPM2      (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)                     /*!< Retrigerrable OPM mode 2               */
+#define TIM_OCMODE_COMBINED_PWM1           (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)                     /*!< Combined PWM mode 1                    */
+#define TIM_OCMODE_COMBINED_PWM2           (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)  /*!< Combined PWM mode 2                    */
+#define TIM_OCMODE_ASSYMETRIC_PWM1         (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)  /*!< Asymmetric PWM mode 1                  */
+#define TIM_OCMODE_ASSYMETRIC_PWM2         TIM_CCMR1_OC1M                                            /*!< Asymmetric PWM mode 2                  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
+  * @{
+  */
+#define TIM_TS_ITR0          0x00000000U                                                       /*!< Internal Trigger 0 (ITR0)              */
+#define TIM_TS_ITR1          TIM_SMCR_TS_0                                                     /*!< Internal Trigger 1 (ITR1)              */
+#define TIM_TS_ITR2          TIM_SMCR_TS_1                                                     /*!< Internal Trigger 2 (ITR2)              */
+#define TIM_TS_ITR3          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                   /*!< Internal Trigger 3 (ITR3)              */
+#define TIM_TS_TI1F_ED       TIM_SMCR_TS_2                                                     /*!< TI1 Edge Detector (TI1F_ED)            */
+#define TIM_TS_TI1FP1        (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 1 (TI1FP1)        */
+#define TIM_TS_TI2FP2        (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 2 (TI2FP2)        */
+#define TIM_TS_ETRF          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                   /*!< Filtered External Trigger input (ETRF) */
+#define TIM_TS_ITR4          (TIM_SMCR_TS_3)                                                   /*!< Internal Trigger 4 (ITR4)              */
+#define TIM_TS_ITR5          (TIM_SMCR_TS_0 | TIM_SMCR_TS_3)                                   /*!< Internal Trigger 5 (ITR5)              */
+#define TIM_TS_ITR6          (TIM_SMCR_TS_1 | TIM_SMCR_TS_3)                                   /*!< Internal Trigger 6 (ITR6)              */
+#define TIM_TS_ITR7          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3)                   /*!< Internal Trigger 7 (ITR7)              */
+#define TIM_TS_ITR8          (TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                                   /*!< Internal Trigger 8 (ITR8)              */
+#define TIM_TS_ITR9          (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                   /*!< Internal Trigger 9 (ITR9)              */
+#define TIM_TS_ITR10         (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                   /*!< Internal Trigger 10 (ITR10)            */
+#define TIM_TS_ITR11         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)   /*!< Internal Trigger 11 (ITR11)            */
+#define TIM_TS_ITR12         (TIM_SMCR_TS_4)                                                   /*!< Internal Trigger 12 (ITR12)            */
+#define TIM_TS_ITR13         (TIM_SMCR_TS_0 | TIM_SMCR_TS_4)                                   /*!< Internal Trigger 13 (ITR13)            */
+#define TIM_TS_NONE          0x0000FFFFU                                                       /*!< No trigger selected                    */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
+  * @{
+  */
+#define TIM_TRIGGERPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED               /*!< Polarity for ETRx trigger sources             */
+#define TIM_TRIGGERPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED            /*!< Polarity for ETRx trigger sources             */
+#define TIM_TRIGGERPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING        /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING       /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE      /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
+  * @{
+  */
+#define TIM_TRIGGERPRESCALER_DIV1             TIM_ETRPRESCALER_DIV1             /*!< No prescaler is used                                                       */
+#define TIM_TRIGGERPRESCALER_DIV2             TIM_ETRPRESCALER_DIV2             /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
+#define TIM_TRIGGERPRESCALER_DIV4             TIM_ETRPRESCALER_DIV4             /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
+#define TIM_TRIGGERPRESCALER_DIV8             TIM_ETRPRESCALER_DIV8             /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
+  * @{
+  */
+#define TIM_TI1SELECTION_CH1               0x00000000U                          /*!< The TIMx_CH1 pin is connected to TI1 input */
+#define TIM_TI1SELECTION_XORCOMBINATION    TIM_CR2_TI1S                         /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
+  * @{
+  */
+#define TIM_DMABURSTLENGTH_1TRANSFER       0x00000000U                          /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA   */
+#define TIM_DMABURSTLENGTH_2TRANSFERS      0x00000100U                          /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_3TRANSFERS      0x00000200U                          /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_4TRANSFERS      0x00000300U                          /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_5TRANSFERS      0x00000400U                          /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_6TRANSFERS      0x00000500U                          /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_7TRANSFERS      0x00000600U                          /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_8TRANSFERS      0x00000700U                          /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_9TRANSFERS      0x00000800U                          /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_10TRANSFERS     0x00000900U                          /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_11TRANSFERS     0x00000A00U                          /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_12TRANSFERS     0x00000B00U                          /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_13TRANSFERS     0x00000C00U                          /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_14TRANSFERS     0x00000D00U                          /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_15TRANSFERS     0x00000E00U                          /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_16TRANSFERS     0x00000F00U                          /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_17TRANSFERS     0x00001000U                          /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_18TRANSFERS     0x00001100U                          /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Handle_index TIM DMA Handle Index
+  * @{
+  */
+#define TIM_DMA_ID_UPDATE                ((uint16_t) 0x0000)       /*!< Index of the DMA handle used for Update DMA requests */
+#define TIM_DMA_ID_CC1                   ((uint16_t) 0x0001)       /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
+#define TIM_DMA_ID_CC2                   ((uint16_t) 0x0002)       /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
+#define TIM_DMA_ID_CC3                   ((uint16_t) 0x0003)       /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
+#define TIM_DMA_ID_CC4                   ((uint16_t) 0x0004)       /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
+#define TIM_DMA_ID_COMMUTATION           ((uint16_t) 0x0005)       /*!< Index of the DMA handle used for Commutation DMA requests */
+#define TIM_DMA_ID_TRIGGER               ((uint16_t) 0x0006)       /*!< Index of the DMA handle used for Trigger DMA requests */
+/**
+  * @}
+  */
+
+/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
+  * @{
+  */
+#define TIM_CCx_ENABLE                   0x00000001U                            /*!< Input or output channel is enabled */
+#define TIM_CCx_DISABLE                  0x00000000U                            /*!< Input or output channel is disabled */
+#define TIM_CCxN_ENABLE                  0x00000004U                            /*!< Complementary output channel is enabled */
+#define TIM_CCxN_DISABLE                 0x00000000U                            /*!< Complementary output channel is enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break_System TIM Break System
+  * @{
+  */
+#define TIM_BREAK_SYSTEM_ECC                 SYSCFG_CFGR2_ECCL   /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */
+#define TIM_BREAK_SYSTEM_PVD                 SYSCFG_CFGR2_PVDL   /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */
+#define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR   SYSCFG_CFGR2_SPL    /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17 */
+#define TIM_BREAK_SYSTEM_LOCKUP              SYSCFG_CFGR2_CLL    /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported constants -------------------------------------------------*/
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup TIM_Exported_Macros TIM Exported Macros
+  * @{
+  */
+
+/** @brief  Reset TIM handle state.
+  * @param  __HANDLE__ TIM handle.
+  * @retval None
+  */
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                        \
+                                                      (__HANDLE__)->State             = HAL_TIM_STATE_RESET; \
+                                                      (__HANDLE__)->Base_MspInitCallback         = NULL;     \
+                                                      (__HANDLE__)->Base_MspDeInitCallback       = NULL;     \
+                                                      (__HANDLE__)->IC_MspInitCallback           = NULL;     \
+                                                      (__HANDLE__)->IC_MspDeInitCallback         = NULL;     \
+                                                      (__HANDLE__)->OC_MspInitCallback           = NULL;     \
+                                                      (__HANDLE__)->OC_MspDeInitCallback         = NULL;     \
+                                                      (__HANDLE__)->PWM_MspInitCallback          = NULL;     \
+                                                      (__HANDLE__)->PWM_MspDeInitCallback        = NULL;     \
+                                                      (__HANDLE__)->OnePulse_MspInitCallback     = NULL;     \
+                                                      (__HANDLE__)->OnePulse_MspDeInitCallback   = NULL;     \
+                                                      (__HANDLE__)->Encoder_MspInitCallback      = NULL;     \
+                                                      (__HANDLE__)->Encoder_MspDeInitCallback    = NULL;     \
+                                                      (__HANDLE__)->HallSensor_MspInitCallback   = NULL;     \
+                                                      (__HANDLE__)->HallSensor_MspDeInitCallback = NULL;     \
+                                                     } while(0)
+#else
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @brief  Enable the TIM peripheral.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
+
+/**
+  * @brief  Enable the TIM main Output.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  */
+#define __HAL_TIM_MOE_ENABLE(__HANDLE__)             ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
+
+/**
+  * @brief  Disable the TIM peripheral.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE(__HANDLE__) \
+  do { \
+    if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
+    { \
+      if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
+      { \
+        (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
+      } \
+    } \
+  } while(0)
+
+/**
+  * @brief  Disable the TIM main Output.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
+  */
+#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
+  do { \
+    if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
+    { \
+      if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
+      { \
+        (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
+      } \
+    } \
+  } while(0)
+
+/**
+  * @brief  Disable the TIM main Output.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  * @note The Main Output Enable of a timer instance is disabled unconditionally
+  */
+#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__)  (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
+
+/** @brief  Enable the specified TIM interrupt.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __INTERRUPT__ specifies the TIM interrupt source to enable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_COM:   Commutation interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  *            @arg TIM_IT_BREAK: Break interrupt
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
+
+/** @brief  Disable the specified TIM interrupt.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __INTERRUPT__ specifies the TIM interrupt source to disable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_COM:   Commutation interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  *            @arg TIM_IT_BREAK: Break interrupt
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
+
+/** @brief  Enable the specified DMA request.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __DMA__ specifies the TIM DMA request to enable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: Update DMA request
+  *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
+  *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
+  *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
+  *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
+  *            @arg TIM_DMA_COM:   Commutation DMA request
+  *            @arg TIM_DMA_TRIGGER: Trigger DMA request
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__)         ((__HANDLE__)->Instance->DIER |= (__DMA__))
+
+/** @brief  Disable the specified DMA request.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __DMA__ specifies the TIM DMA request to disable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: Update DMA request
+  *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
+  *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
+  *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
+  *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
+  *            @arg TIM_DMA_COM:   Commutation DMA request
+  *            @arg TIM_DMA_TRIGGER: Trigger DMA request
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__)        ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
+
+/** @brief  Check whether the specified TIM interrupt flag is set or not.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __FLAG__ specifies the TIM interrupt flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg TIM_FLAG_UPDATE: Update interrupt flag
+  *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
+  *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
+  *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
+  *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
+  *            @arg TIM_FLAG_CC5: Compare 5 interrupt flag
+  *            @arg TIM_FLAG_CC6: Compare 6 interrupt flag
+  *            @arg TIM_FLAG_COM:  Commutation interrupt flag
+  *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
+  *            @arg TIM_FLAG_BREAK: Break interrupt flag
+  *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
+  *            @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
+  *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
+  *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
+  *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
+  *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
+
+/** @brief  Clear the specified TIM interrupt flag.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __FLAG__ specifies the TIM interrupt flag to clear.
+  *        This parameter can be one of the following values:
+  *            @arg TIM_FLAG_UPDATE: Update interrupt flag
+  *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
+  *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
+  *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
+  *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
+  *            @arg TIM_FLAG_CC5: Compare 5 interrupt flag
+  *            @arg TIM_FLAG_CC6: Compare 6 interrupt flag
+  *            @arg TIM_FLAG_COM:  Commutation interrupt flag
+  *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
+  *            @arg TIM_FLAG_BREAK: Break interrupt flag
+  *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
+  *            @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
+  *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
+  *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
+  *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
+  *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->SR = ~(__FLAG__))
+
+/**
+  * @brief  Check whether the specified TIM interrupt source is enabled or not.
+  * @param  __HANDLE__ TIM handle
+  * @param  __INTERRUPT__ specifies the TIM interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_COM:   Commutation interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  *            @arg TIM_IT_BREAK: Break interrupt
+  * @retval The state of TIM_IT (SET or RESET).
+  */
+#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
+                                                             == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Clear the TIM interrupt pending bits.
+  * @param  __HANDLE__ TIM handle
+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_COM:   Commutation interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  *            @arg TIM_IT_BREAK: Break interrupt
+  * @retval None
+  */
+#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
+
+/**
+  * @brief  Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
+  * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
+  * @param  __HANDLE__ TIM handle.
+  * @retval None
+mode.
+  */
+#define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__)    (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP))
+
+/**
+  * @brief  Disable update interrupt flag (UIF) remapping.
+  * @param  __HANDLE__ TIM handle.
+  * @retval None
+mode.
+  */
+#define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__)    (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP))
+
+/**
+  * @brief  Get update interrupt flag (UIF) copy status.
+  * @param  __COUNTER__ Counter value.
+  * @retval The state of UIFCPY (TRUE or FALSE).
+mode.
+  */
+#define __HAL_TIM_GET_UIFCPY(__COUNTER__)    (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY))
+
+/**
+  * @brief  Indicates whether or not the TIM Counter is used as downcounter.
+  * @param  __HANDLE__ TIM handle.
+  * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
+  * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
+mode.
+  */
+#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__)    (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
+
+/**
+  * @brief  Set the TIM Prescaler on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __PRESC__ specifies the Prescaler new value.
+  * @retval None
+  */
+#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__)       ((__HANDLE__)->Instance->PSC = (__PRESC__))
+
+/**
+  * @brief  Set the TIM Counter Register value on runtime.
+  * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in case of 32 bits counter TIM instance.
+  *      Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __COUNTER__ specifies the Counter register new value.
+  * @retval None
+  */
+#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__)  ((__HANDLE__)->Instance->CNT = (__COUNTER__))
+
+/**
+  * @brief  Get the TIM Counter Register value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
+  */
+#define __HAL_TIM_GET_COUNTER(__HANDLE__)  ((__HANDLE__)->Instance->CNT)
+
+/**
+  * @brief  Set the TIM Autoreload Register value on runtime without calling another time any Init function.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __AUTORELOAD__ specifies the Counter register new value.
+  * @retval None
+  */
+#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
+  do{                                                    \
+    (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
+    (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
+  } while(0)
+
+/**
+  * @brief  Get the TIM Autoreload Register value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
+  */
+#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__)  ((__HANDLE__)->Instance->ARR)
+
+/**
+  * @brief  Set the TIM Clock Division value on runtime without calling another time any Init function.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CKD__ specifies the clock division value.
+  *          This parameter can be one of the following value:
+  *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
+  * @retval None
+  */
+#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
+  do{                                                   \
+    (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD);  \
+    (__HANDLE__)->Instance->CR1 |= (__CKD__);       \
+    (__HANDLE__)->Init.ClockDivision = (__CKD__);   \
+  } while(0)
+
+/**
+  * @brief  Get the TIM Clock Division value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @retval The clock division can be one of the following values:
+  *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
+  */
+#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__)  ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
+
+/**
+  * @brief  Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  __ICPSC__ specifies the Input Capture4 prescaler new value.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPSC_DIV1: no prescaler
+  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+  * @retval None
+  */
+#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
+  do{                                                    \
+    TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \
+    TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
+  } while(0)
+
+/**
+  * @brief  Get the TIM Input Capture prescaler on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: get input capture 1 prescaler value
+  *            @arg TIM_CHANNEL_2: get input capture 2 prescaler value
+  *            @arg TIM_CHANNEL_3: get input capture 3 prescaler value
+  *            @arg TIM_CHANNEL_4: get input capture 4 prescaler value
+  * @retval The input capture prescaler can be one of the following values:
+  *            @arg TIM_ICPSC_DIV1: no prescaler
+  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+  */
+#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)  \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
+   (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
+
+/**
+  * @brief  Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @param  __COMPARE__ specifies the Capture Compare register new value.
+  * @retval None
+  */
+#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
+   ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
+
+/**
+  * @brief  Get the TIM Capture Compare Register value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channel associated with the capture compare register
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: get capture/compare 1 register value
+  *            @arg TIM_CHANNEL_2: get capture/compare 2 register value
+  *            @arg TIM_CHANNEL_3: get capture/compare 3 register value
+  *            @arg TIM_CHANNEL_4: get capture/compare 4 register value
+  *            @arg TIM_CHANNEL_5: get capture/compare 5 register value
+  *            @arg TIM_CHANNEL_6: get capture/compare 6 register value
+  * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
+  */
+#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
+   ((__HANDLE__)->Instance->CCR6))
+
+/**
+  * @brief  Set the TIM Output compare preload.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
+   ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))
+
+/**
+  * @brief  Reset the TIM Output compare preload.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\
+   ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE))
+
+/**
+  * @brief  Enable fast mode for a given channel.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @note  When fast mode is enabled an active edge on the trigger input acts
+  *        like a compare match on CCx output. Delay to sample the trigger
+  *        input and to activate CCx output is reduced to 3 clock cycles.
+  * @note  Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\
+   ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE))
+
+/**
+  * @brief  Disable fast mode for a given channel.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @note  When fast mode is disabled CCx output behaves normally depending
+  *        on counter and CCRx values even when the trigger is ON. The minimum
+  *        delay to activate CCx output when an active edge occurs on the
+  *        trigger input is 5 clock cycles.
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\
+   ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE))
+
+/**
+  * @brief  Set the Update Request Source (URS) bit of the TIMx_CR1 register.
+  * @param  __HANDLE__ TIM handle.
+  * @note  When the URS bit of the TIMx_CR1 register is set, only counter
+  *        overflow/underflow generates an update interrupt or DMA request (if
+  *        enabled)
+  * @retval None
+  */
+#define __HAL_TIM_URS_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
+
+/**
+  * @brief  Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
+  * @param  __HANDLE__ TIM handle.
+  * @note  When the URS bit of the TIMx_CR1 register is reset, any of the
+  *        following events generate an update interrupt or DMA request (if
+  *        enabled):
+  *           _ Counter overflow underflow
+  *           _ Setting the UG bit
+  *           _ Update generation through the slave mode controller
+  * @retval None
+  */
+#define __HAL_TIM_URS_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
+
+/**
+  * @brief  Set the TIM Capture x input polarity on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  __POLARITY__ Polarity for TIx source
+  *            @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
+  *            @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
+  *            @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
+  * @retval None
+  */
+#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)    \
+  do{                                                                     \
+    TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \
+    TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
+  }while(0)
+
+/**
+  * @}
+  */
+/* End of exported macros ----------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup TIM_Private_Constants TIM Private Constants
+  * @{
+  */
+/* The counter of a timer instance is disabled only if all the CCx and CCxN
+   channels have been disabled */
+#define TIM_CCER_CCxE_MASK  ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
+#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
+/**
+  * @}
+  */
+/* End of private constants --------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TIM_Private_Macros TIM Private Macros
+  * @{
+  */
+#define IS_TIM_CLEARINPUT_SOURCE(__MODE__)  (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)      || \
+                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))
+
+#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1)   || \
+                                   ((__BASE__) == TIM_DMABASE_CR2)   || \
+                                   ((__BASE__) == TIM_DMABASE_SMCR)  || \
+                                   ((__BASE__) == TIM_DMABASE_DIER)  || \
+                                   ((__BASE__) == TIM_DMABASE_SR)    || \
+                                   ((__BASE__) == TIM_DMABASE_EGR)   || \
+                                   ((__BASE__) == TIM_DMABASE_CCMR1) || \
+                                   ((__BASE__) == TIM_DMABASE_CCMR2) || \
+                                   ((__BASE__) == TIM_DMABASE_CCER)  || \
+                                   ((__BASE__) == TIM_DMABASE_CNT)   || \
+                                   ((__BASE__) == TIM_DMABASE_PSC)   || \
+                                   ((__BASE__) == TIM_DMABASE_ARR)   || \
+                                   ((__BASE__) == TIM_DMABASE_RCR)   || \
+                                   ((__BASE__) == TIM_DMABASE_CCR1)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCR2)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCR3)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCR4)  || \
+                                   ((__BASE__) == TIM_DMABASE_BDTR)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCMR3) || \
+                                   ((__BASE__) == TIM_DMABASE_CCR5)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCR6)  || \
+                                   ((__BASE__) == TIM_DMABASE_AF1)   || \
+                                   ((__BASE__) == TIM_DMABASE_AF2)   || \
+                                   ((__BASE__) == TIM_DMABASE_TISEL))
+
+
+#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
+
+#define IS_TIM_COUNTER_MODE(__MODE__)      (((__MODE__) == TIM_COUNTERMODE_UP)              || \
+                                            ((__MODE__) == TIM_COUNTERMODE_DOWN)            || \
+                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
+                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
+                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
+
+#define IS_TIM_UIFREMAP_MODE(__MODE__)     (((__MODE__) == TIM_UIFREMAP_DISABLE) || \
+                                            ((__MODE__) == TIM_UIFREMAP_ENALE))
+
+#define IS_TIM_CLOCKDIVISION_DIV(__DIV__)  (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
+                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
+                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
+
+#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
+                                            ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
+
+#define IS_TIM_FAST_STATE(__STATE__)       (((__STATE__) == TIM_OCFAST_DISABLE) || \
+                                            ((__STATE__) == TIM_OCFAST_ENABLE))
+
+#define IS_TIM_OC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
+                                            ((__POLARITY__) == TIM_OCPOLARITY_LOW))
+
+#define IS_TIM_OCN_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
+                                            ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
+
+#define IS_TIM_OCIDLE_STATE(__STATE__)     (((__STATE__) == TIM_OCIDLESTATE_SET) || \
+                                            ((__STATE__) == TIM_OCIDLESTATE_RESET))
+
+#define IS_TIM_OCNIDLE_STATE(__STATE__)    (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
+                                            ((__STATE__) == TIM_OCNIDLESTATE_RESET))
+
+#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING)   || \
+                                                      ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
+
+#define IS_TIM_IC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ICPOLARITY_RISING)   || \
+                                            ((__POLARITY__) == TIM_ICPOLARITY_FALLING)  || \
+                                            ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
+
+#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
+                                            ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
+                                            ((__SELECTION__) == TIM_ICSELECTION_TRC))
+
+#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
+                                            ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
+                                            ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
+                                            ((__PRESCALER__) == TIM_ICPSC_DIV8))
+
+#define IS_TIM_OPM_MODE(__MODE__)          (((__MODE__) == TIM_OPMODE_SINGLE) || \
+                                            ((__MODE__) == TIM_OPMODE_REPETITIVE))
+
+#define IS_TIM_ENCODER_MODE(__MODE__)      (((__MODE__) == TIM_ENCODERMODE_TI1) || \
+                                            ((__MODE__) == TIM_ENCODERMODE_TI2) || \
+                                            ((__MODE__) == TIM_ENCODERMODE_TI12))
+
+#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
+
+#define IS_TIM_CHANNELS(__CHANNEL__)       (((__CHANNEL__) == TIM_CHANNEL_1) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_2) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_3) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_4) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_5) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_6) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_ALL))
+
+#define IS_TIM_OPM_CHANNELS(__CHANNEL__)   (((__CHANNEL__) == TIM_CHANNEL_1) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_2))
+
+#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
+                                                    ((__CHANNEL__) == TIM_CHANNEL_2) || \
+                                                    ((__CHANNEL__) == TIM_CHANNEL_3))
+
+#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
+
+#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED)    || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING)      || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING)     || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
+
+#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
+                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
+                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
+                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
+
+#define IS_TIM_CLOCKFILTER(__ICFILTER__)      ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
+                                                  ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
+
+#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
+                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
+                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
+                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
+
+#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_OSSR_STATE(__STATE__)       (((__STATE__) == TIM_OSSR_ENABLE) || \
+                                            ((__STATE__) == TIM_OSSR_DISABLE))
+
+#define IS_TIM_OSSI_STATE(__STATE__)       (((__STATE__) == TIM_OSSI_ENABLE) || \
+                                            ((__STATE__) == TIM_OSSI_DISABLE))
+
+#define IS_TIM_LOCK_LEVEL(__LEVEL__)       (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
+                                            ((__LEVEL__) == TIM_LOCKLEVEL_1)   || \
+                                            ((__LEVEL__) == TIM_LOCKLEVEL_2)   || \
+                                            ((__LEVEL__) == TIM_LOCKLEVEL_3))
+
+#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
+
+
+#define IS_TIM_BREAK_STATE(__STATE__)      (((__STATE__) == TIM_BREAK_ENABLE) || \
+                                            ((__STATE__) == TIM_BREAK_DISABLE))
+
+#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
+                                             ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
+
+#define IS_TIM_BREAK2_STATE(__STATE__)     (((__STATE__) == TIM_BREAK2_ENABLE) || \
+                                            ((__STATE__) == TIM_BREAK2_DISABLE))
+
+#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
+                                              ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
+
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
+                                                  ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
+
+#define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))
+
+#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET)  || \
+                                        ((__SOURCE__) == TIM_TRGO_ENABLE) || \
+                                        ((__SOURCE__) == TIM_TRGO_UPDATE) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC1)    || \
+                                        ((__SOURCE__) == TIM_TRGO_OC1REF) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC2REF) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC3REF) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC4REF))
+
+#define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET)                        || \
+                                         ((__SOURCE__) == TIM_TRGO2_ENABLE)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_UPDATE)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC1)                          || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC1REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC2REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC4REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC5REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC6REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING)         || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING)         || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING)  || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING)  || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
+
+#define IS_TIM_MSM_STATE(__STATE__)      (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
+                                          ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
+
+#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE)   || \
+                                     ((__MODE__) == TIM_SLAVEMODE_RESET)     || \
+                                     ((__MODE__) == TIM_SLAVEMODE_GATED)     || \
+                                     ((__MODE__) == TIM_SLAVEMODE_TRIGGER)   || \
+                                     ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \
+                                     ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
+
+#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1)               || \
+                                   ((__MODE__) == TIM_OCMODE_PWM2)               || \
+                                   ((__MODE__) == TIM_OCMODE_COMBINED_PWM1)      || \
+                                   ((__MODE__) == TIM_OCMODE_COMBINED_PWM2)      || \
+                                   ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1)    || \
+                                   ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))
+
+#define IS_TIM_OC_MODE(__MODE__)  (((__MODE__) == TIM_OCMODE_TIMING)             || \
+                                   ((__MODE__) == TIM_OCMODE_ACTIVE)             || \
+                                   ((__MODE__) == TIM_OCMODE_INACTIVE)           || \
+                                   ((__MODE__) == TIM_OCMODE_TOGGLE)             || \
+                                   ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE)      || \
+                                   ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)    || \
+                                   ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
+                                   ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2))
+
+#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR1) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR2) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR3) || \
+                                                 ((__SELECTION__) == TIM_TS_TI1F_ED) || \
+                                                 ((__SELECTION__) == TIM_TS_TI1FP1) || \
+                                                 ((__SELECTION__) == TIM_TS_TI2FP2) || \
+                                                 ((__SELECTION__) == TIM_TS_ETRF) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR4) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR5) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR6) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR7) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR8) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR12) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR13))
+
+#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR1) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR2) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR3) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR4) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR5) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR6) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR7) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR8) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR12) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR13) || \
+                                                               ((__SELECTION__) == TIM_TS_NONE))
+
+#define IS_TIM_TRIGGERPOLARITY(__POLARITY__)   (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING     ) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING    ) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))
+
+#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
+                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
+                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
+                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
+
+#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_TI1SELECTION(__TI1SELECTION__)  (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
+                                                ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
+
+#define IS_TIM_DMA_LENGTH(__LENGTH__)      (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
+
+#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
+
+#define IS_TIM_IC_FILTER(__ICFILTER__)   ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_DEADTIME(__DEADTIME__)    ((__DEADTIME__) <= 0xFFU)
+
+#define IS_TIM_BREAK_SYSTEM(__CONFIG__)    (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC)                  || \
+                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD)                  || \
+                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR)    || \
+                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))
+
+#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \
+                                                       ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
+
+#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
+   ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
+
+#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
+   ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
+
+#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
+   ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
+
+#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
+   ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
+
+/**
+  * @}
+  */
+/* End of private macros -----------------------------------------------------*/
+
+/* Include TIM HAL Extended module */
+#include "stm32h7xx_hal_tim_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIM_Exported_Functions TIM Exported Functions
+  * @{
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
+  *  @brief   Time Base functions
+  * @{
+  */
+/* Time Base functions ********************************************************/
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
+  *  @brief   TIM Output Compare functions
+  * @{
+  */
+/* Timer Output Compare functions *********************************************/
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
+  *  @brief   TIM PWM functions
+  * @{
+  */
+/* Timer PWM functions ********************************************************/
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
+  *  @brief   TIM Input Capture functions
+  * @{
+  */
+/* Timer Input Capture functions **********************************************/
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
+  *  @brief   TIM One Pulse functions
+  * @{
+  */
+/* Timer One Pulse functions **************************************************/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
+  *  @brief   TIM Encoder functions
+  * @{
+  */
+/* Timer Encoder functions ****************************************************/
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef *sConfig);
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
+                                            uint32_t *pData2, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
+  *  @brief   IRQ handler management
+  * @{
+  */
+/* Interrupt Handler functions  ***********************************************/
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
+  *  @brief   Peripheral Control functions
+  * @{
+  */
+/* Control functions  *********************************************************/
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
+                                                 uint32_t OutputChannel,  uint32_t InputChannel);
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,
+                                           uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                              uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                                   uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
+                                                   uint32_t DataLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                             uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                                  uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength,
+                                                  uint32_t  DataLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
+  *  @brief   TIM Callbacks functions
+  * @{
+  */
+/* Callback in non blocking modes (Interrupt and DMA) *************************/
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
+                                           pTIM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
+  *  @brief  Peripheral State functions
+  * @{
+  */
+/* Peripheral State functions  ************************************************/
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private functions----------------------------------------------------------*/
+/** @defgroup TIM_Private_Functions TIM Private Functions
+  * @{
+  */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
+                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
+
+void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMAError(DMA_HandleTypeDef *hdma);
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
+void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+void TIM_ResetCallback(TIM_HandleTypeDef *htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+/* End of private functions --------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_TIM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h
new file mode 100644
index 00000000..0a7ef48a
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h
@@ -0,0 +1,529 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_tim_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of TIM HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_TIM_EX_H
+#define STM32H7xx_HAL_TIM_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup TIMEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
+  * @{
+  */
+
+/**
+  * @brief  TIM Hall sensor Configuration Structure definition
+  */
+
+typedef struct
+{
+  uint32_t IC1Polarity;         /*!< Specifies the active edge of the input signal.
+                                     This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint32_t IC1Prescaler;        /*!< Specifies the Input Capture Prescaler.
+                                     This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t IC1Filter;           /*!< Specifies the input capture filter.
+                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+  uint32_t Commutation_Delay;   /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+                                     This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+} TIM_HallSensor_InitTypeDef;
+#if defined(TIM_BREAK_INPUT_SUPPORT)
+
+/**
+  * @brief  TIM Break/Break2 input configuration
+  */
+typedef struct
+{
+  uint32_t Source;         /*!< Specifies the source of the timer break input.
+                                This parameter can be a value of @ref TIMEx_Break_Input_Source */
+  uint32_t Enable;         /*!< Specifies whether or not the break input source is enabled.
+                                This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */
+  uint32_t Polarity;       /*!< Specifies the break input source polarity.
+                                This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity
+                                Not relevant when analog watchdog output of the DFSDM1 used as break input source */
+}
+TIMEx_BreakInputConfigTypeDef;
+
+#endif /* TIM_BREAK_INPUT_SUPPORT */
+/**
+  * @}
+  */
+/* End of exported types -----------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
+  * @{
+  */
+
+/** @defgroup TIMEx_Remap TIM Extended Remapping
+  * @{
+  */
+#define TIM_TIM1_ETR_GPIO        0x00000000U                                                 /* !< TIM1_ETR is connected to GPIO */
+#define TIM_TIM1_ETR_COMP1       TIM1_AF1_ETRSEL_0                                           /* !< TIM1_ETR is connected to COMP1 OUT */
+#define TIM_TIM1_ETR_COMP2       TIM1_AF1_ETRSEL_1                                           /* !< TIM1_ETR is connected to COMP2 OUT */
+#define TIM_TIM1_ETR_ADC1_AWD1   (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                     /* !< TIM1_ETR is connected to ADC1 AWD1 */
+#define TIM_TIM1_ETR_ADC1_AWD2   (TIM1_AF1_ETRSEL_2)                                         /* !< TIM1_ETR is connected to ADC1 AWD2 */
+#define TIM_TIM1_ETR_ADC1_AWD3   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                     /* !< TIM1_ETR is connected to ADC1 AWD3 */
+#define TIM_TIM1_ETR_ADC3_AWD1   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                     /* !< TIM1_ETR is connected to ADC3 AWD1 */
+#define TIM_TIM1_ETR_ADC3_AWD2   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC3 AWD2 */
+#define TIM_TIM1_ETR_ADC3_AWD3   TIM1_AF1_ETRSEL_3                                           /* !< TIM1_ETR is connected to ADC3 AWD3 */
+
+#define TIM_TIM8_ETR_GPIO        0x00000000U                                                 /* !< TIM8_ETR is connected to GPIO */
+#define TIM_TIM8_ETR_COMP1       TIM8_AF1_ETRSEL_0                                           /* !< TIM8_ETR is connected to COMP1 OUT */
+#define TIM_TIM8_ETR_COMP2       TIM8_AF1_ETRSEL_1                                           /* !< TIM8_ETR is connected to COMP2 OUT */
+#define TIM_TIM8_ETR_ADC2_AWD1   (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)                     /* !< TIM8_ETR is connected to ADC2 AWD1 */
+#define TIM_TIM8_ETR_ADC2_AWD2   (TIM8_AF1_ETRSEL_2)                                         /* !< TIM8_ETR is connected to ADC2 AWD2 */
+#define TIM_TIM8_ETR_ADC2_AWD3   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0)                     /* !< TIM8_ETR is connected to ADC2 AWD3 */
+#define TIM_TIM8_ETR_ADC3_AWD1   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1)                     /* !< TIM8_ETR is connected to ADC3 AWD1 */
+#define TIM_TIM8_ETR_ADC3_AWD2   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC3 AWD2 */
+#define TIM_TIM8_ETR_ADC3_AWD3   TIM8_AF1_ETRSEL_3                                           /* !< TIM8_ETR is connected to ADC3 AWD3 */
+
+#define TIM_TIM2_ETR_GPIO        0x00000000U                             /* !< TIM2_ETR is connected to GPIO */
+#define TIM_TIM2_ETR_COMP1       (TIM2_AF1_ETRSEL_0)                     /* !< TIM2_ETR is connected to COMP1 OUT */
+#define TIM_TIM2_ETR_COMP2       (TIM2_AF1_ETRSEL_1)                     /* !< TIM2_ETR is connected to COMP2 OUT */
+#define TIM_TIM2_ETR_RCC_LSE     (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to RCC LSE */
+#define TIM_TIM2_ETR_SAI1_FSA    TIM2_AF1_ETRSEL_2                       /* !< TIM2_ETR is connected to SAI1 FS_A */
+#define TIM_TIM2_ETR_SAI1_FSB    (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to SAI1 FS_B */
+
+#define TIM_TIM3_ETR_GPIO        0x00000000U          /* !< TIM3_ETR is connected to GPIO */
+#define TIM_TIM3_ETR_COMP1       TIM3_AF1_ETRSEL_0    /* !< TIM3_ETR is connected to COMP1 OUT */
+
+#define TIM_TIM5_ETR_GPIO        0x00000000U          /* !< TIM5_ETR is connected to GPIO */
+#define TIM_TIM5_ETR_SAI2_FSA    TIM5_AF1_ETRSEL_0    /* !< TIM5_ETR is connected to SAI2 FS_A */
+#define TIM_TIM5_ETR_SAI2_FSB    TIM5_AF1_ETRSEL_1    /* !< TIM5_ETR is connected to SAI2 FS_B */
+#define TIM_TIM5_ETR_SAI4_FSA    TIM5_AF1_ETRSEL_0    /* !< TIM5_ETR is connected to SAI4 FS_A */
+#define TIM_TIM5_ETR_SAI4_FSB    TIM5_AF1_ETRSEL_1    /* !< TIM5_ETR is connected to SAI4 FS_B */
+
+#define TIM_TIM23_ETR_GPIO       0x00000000U          /* !< TIM23_ETR is connected to GPIO */
+#define TIM_TIM23_ETR_COMP1      (TIM2_AF1_ETRSEL_0)  /* !< TIM23_ETR is connected to COMP1 OUT */
+#define TIM_TIM23_ETR_COMP2      (TIM2_AF1_ETRSEL_1)  /* !< TIM23_ETR is connected to COMP2 OUT */
+
+#define TIM_TIM24_ETR_GPIO        0x00000000U                                /* !< TIM24_ETR is connected to GPIO */
+#define TIM_TIM24_ETR_SAI4_FSA    TIM5_AF1_ETRSEL_0                          /* !< TIM24_ETR is connected to SAI4 FS_A */
+#define TIM_TIM24_ETR_SAI4_FSB    TIM5_AF1_ETRSEL_1                          /* !< TIM24_ETR is connected to SAI4 FS_B */
+#define TIM_TIM24_ETR_SAI1_FSA    (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)    /* !< TIM24_ETR is connected to SAI1 FS_A */
+#define TIM_TIM24_ETR_SAI1_FSB    TIM2_AF1_ETRSEL_2                          /* !< TIM24_ETR is connected to SAI1 FS_B */
+/**
+  * @}
+  */
+#if defined(TIM_BREAK_INPUT_SUPPORT)
+
+/** @defgroup TIMEx_Break_Input TIM Extended Break input
+  * @{
+  */
+#define TIM_BREAKINPUT_BRK     0x00000001U                                      /* !< Timer break input  */
+#define TIM_BREAKINPUT_BRK2    0x00000002U                                      /* !< Timer break2 input */
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source
+  * @{
+  */
+#define TIM_BREAKINPUTSOURCE_BKIN     0x00000001U                               /* !< An external source (GPIO) is connected to the BKIN pin  */
+#define TIM_BREAKINPUTSOURCE_COMP1    0x00000002U                               /* !< The COMP1 output is connected to the break input */
+#define TIM_BREAKINPUTSOURCE_COMP2    0x00000004U                               /* !< The COMP2 output is connected to the break input */
+#define TIM_BREAKINPUTSOURCE_DFSDM1   0x00000008U                               /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling
+  * @{
+  */
+#define TIM_BREAKINPUTSOURCE_DISABLE     0x00000000U                            /* !< Break input source is disabled */
+#define TIM_BREAKINPUTSOURCE_ENABLE      0x00000001U                            /* !< Break input source is enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity
+  * @{
+  */
+#define TIM_BREAKINPUTSOURCE_POLARITY_LOW     0x00000001U                       /* !< Break input source is active low */
+#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH    0x00000000U                       /* !< Break input source is active_high */
+/**
+  * @}
+  */
+#endif /* TIM_BREAK_INPUT_SUPPORT */
+
+/** @defgroup TIMEx_Timer_Input_Selection TIM Extended Timer input selection
+  * @{
+  */
+#define TIM_TIM1_TI1_GPIO                          0x00000000U                               /* !< TIM1_TI1 is connected to GPIO */
+#define TIM_TIM1_TI1_COMP1                         TIM_TISEL_TI1SEL_0                        /* !< TIM1_TI1 is connected to COMP1 OUT */
+
+#define TIM_TIM8_TI1_GPIO                          0x00000000U                               /* !< TIM8_TI1 is connected to GPIO */
+#define TIM_TIM8_TI1_COMP2                         TIM_TISEL_TI1SEL_0                        /* !< TIM8_TI1 is connected to COMP2 OUT */
+
+#define TIM_TIM2_TI4_GPIO                          0x00000000U                               /* !< TIM2_TI4 is connected to GPIO */
+#define TIM_TIM2_TI4_COMP1                         TIM_TISEL_TI4SEL_0                        /* !< TIM2_TI4 is connected to COMP1 OUT */
+#define TIM_TIM2_TI4_COMP2                         TIM_TISEL_TI4SEL_1                        /* !< TIM2_TI4 is connected to COMP2 OUT */
+#define TIM_TIM2_TI4_COMP1_COMP2                   (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM2_TI4 is connected to COMP2 OUT OR COMP2 OUT */
+
+#define TIM_TIM3_TI1_GPIO                          0x00000000U                               /* !< TIM3_TI1 is connected to GPIO */
+#define TIM_TIM3_TI1_COMP1                         TIM_TISEL_TI1SEL_0                        /* !< TIM3_TI1 is connected to COMP1 OUT */
+#define TIM_TIM3_TI1_COMP2                         TIM_TISEL_TI1SEL_1                        /* !< TIM3_TI1 is connected to COMP2 OUT */
+#define TIM_TIM3_TI1_COMP1_COMP2                   (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM3_TI1 is connected to COMP1 OUT or COMP2 OUT */
+
+#define TIM_TIM5_TI1_GPIO                          0x00000000U                               /* !< TIM5_TI1 is connected to GPIO */
+#define TIM_TIM5_TI1_CAN_TMP                       TIM_TISEL_TI1SEL_0                        /* !< TIM5_TI1 is connected to CAN TMP */
+#define TIM_TIM5_TI1_CAN_RTP                       TIM_TISEL_TI1SEL_1                        /* !< TIM5_TI1 is connected to CAN RTP */
+
+#define TIM_TIM12_TI1_GPIO                         0x00000000U                               /* !< TIM12 TI1 is connected to GPIO */
+#define TIM_TIM12_TI1_SPDIF_FS                     TIM_TISEL_TI1SEL_0                        /* !< TIM12 TI1 is connected to SPDIF FS */
+
+#define TIM_TIM15_TI1_GPIO                         0x00000000U                               /* !< TIM15_TI1 is connected to GPIO */
+#define TIM_TIM15_TI1_TIM2_CH1                     TIM_TISEL_TI1SEL_0                        /* !< TIM15_TI1 is connected to TIM2 CH1 */
+#define TIM_TIM15_TI1_TIM3_CH1                     TIM_TISEL_TI1SEL_1                        /* !< TIM15_TI1 is connected to TIM3 CH1 */
+#define TIM_TIM15_TI1_TIM4_CH1                     (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM15_TI1 is connected to TIM4 CH1 */
+#define TIM_TIM15_TI1_RCC_LSE                      (TIM_TISEL_TI1SEL_2)                      /* !< TIM15_TI1 is connected to RCC LSE  */
+#define TIM_TIM15_TI1_RCC_CSI                      (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /* !< TIM15_TI1 is connected to RCC CSI  */
+#define TIM_TIM15_TI1_RCC_MCO2                     (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /* !< TIM15_TI1 is connected to RCC MCO2 */
+
+#define TIM_TIM15_TI2_GPIO                         0x00000000U                               /* !< TIM15_TI2 is connected to GPIO */
+#define TIM_TIM15_TI2_TIM2_CH2                     (TIM_TISEL_TI2SEL_0)                      /* !< TIM15_TI2 is connected to TIM2 CH2 */
+#define TIM_TIM15_TI2_TIM3_CH2                     (TIM_TISEL_TI2SEL_1)                      /* !< TIM15_TI2 is connected to TIM3 CH2 */
+#define TIM_TIM15_TI2_TIM4_CH2                     (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1) /* !< TIM15_TI2 is connected to TIM4 CH2 */
+
+#define TIM_TIM16_TI1_GPIO                         0x00000000U                               /* !< TIM16 TI1 is connected to GPIO */
+#define TIM_TIM16_TI1_RCC_LSI                      TIM_TISEL_TI1SEL_0                        /* !< TIM16 TI1 is connected to RCC LSI */
+#define TIM_TIM16_TI1_RCC_LSE                      TIM_TISEL_TI1SEL_1                        /* !< TIM16 TI1 is connected to RCC LSE */
+#define TIM_TIM16_TI1_WKUP_IT                      (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM16 TI1 is connected to WKUP_IT */
+
+#define TIM_TIM17_TI1_GPIO                         0x00000000U                               /* !< TIM17 TI1 is connected to GPIO */
+#define TIM_TIM17_TI1_SPDIF_FS                     TIM_TISEL_TI1SEL_0                        /* !< TIM17 TI1 is connected to SPDIF FS */
+#define TIM_TIM17_TI1_RCC_HSE1MHZ                  TIM_TISEL_TI1SEL_1                        /* !< TIM17 TI1 is connected to RCC HSE 1Mhz */
+#define TIM_TIM17_TI1_RCC_MCO1                     (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM17 TI1 is connected to RCC MCO1 */
+
+#define TIM_TIM23_TI4_GPIO                         0x00000000U                               /* !< TIM23_TI4 is connected to GPIO */
+#define TIM_TIM23_TI4_COMP1                        TIM_TISEL_TI4SEL_0                        /* !< TIM23_TI4 is connected to COMP1 OUT */
+#define TIM_TIM23_TI4_COMP2                        TIM_TISEL_TI4SEL_1                        /* !< TIM23_TI4 is connected to COMP2 OUT */
+#define TIM_TIM23_TI4_COMP1_COMP2                  (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM23_TI4 is connected to COMP1 OUT or COMP2 OUT */
+
+#define TIM_TIM24_TI1_GPIO                         0x00000000U                               /* !< TIM24_TI1 is connected to GPIO */
+#define TIM_TIM24_TI1_CAN_TMP                      TIM_TISEL_TI1SEL_0                        /* !< TIM24_TI1 is connected to CAN TMP  */
+#define TIM_TIM24_TI1_CAN_RTP                      TIM_TISEL_TI1SEL_1                        /* !< TIM24_TI1 is connected to CAN RTP  */
+#define TIM_TIM24_TI1_CAN_SOC                      (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM24_TI1 is connected to CAN SOC */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported constants -------------------------------------------------*/
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+/* End of exported macro -----------------------------------------------------*/
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
+  * @{
+  */
+#define IS_TIM_BREAKINPUT(__BREAKINPUT__)  (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK)  || \
+                                            ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
+
+#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__)  (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)  || \
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM1))
+
+#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__)  (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE)  || \
+                                                   ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
+
+#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW)  || \
+                                                         ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
+
+#define IS_TIM_TISEL(__TISEL__)  (((__TISEL__) == TIM_TIM1_TI1_GPIO)         ||\
+                                  ((__TISEL__) == TIM_TIM1_TI1_COMP1)        ||\
+                                  ((__TISEL__) == TIM_TIM8_TI1_GPIO)         ||\
+                                  ((__TISEL__) == TIM_TIM8_TI1_COMP2)        ||\
+                                  ((__TISEL__) == TIM_TIM2_TI4_GPIO)         ||\
+                                  ((__TISEL__) == TIM_TIM2_TI4_COMP1)        ||\
+                                  ((__TISEL__) == TIM_TIM2_TI4_COMP2)        ||\
+                                  ((__TISEL__) == TIM_TIM2_TI4_COMP1_COMP2)  ||\
+                                  ((__TISEL__) == TIM_TIM3_TI1_GPIO)         ||\
+                                  ((__TISEL__) == TIM_TIM3_TI1_COMP1)        ||\
+                                  ((__TISEL__) == TIM_TIM3_TI1_COMP2)        ||\
+                                  ((__TISEL__) == TIM_TIM3_TI1_COMP1_COMP2)  ||\
+                                  ((__TISEL__) == TIM_TIM5_TI1_GPIO)         ||\
+                                  ((__TISEL__) == TIM_TIM5_TI1_CAN_TMP)      ||\
+                                  ((__TISEL__) == TIM_TIM5_TI1_CAN_RTP)      ||\
+                                  ((__TISEL__) == TIM_TIM12_TI1_SPDIF_FS)    ||\
+                                  ((__TISEL__) == TIM_TIM12_TI1_GPIO)        ||\
+                                  ((__TISEL__) == TIM_TIM15_TI1_GPIO)        ||\
+                                  ((__TISEL__) == TIM_TIM15_TI1_TIM2_CH1)    ||\
+                                  ((__TISEL__) == TIM_TIM15_TI1_TIM3_CH1)    ||\
+                                  ((__TISEL__) == TIM_TIM15_TI1_TIM4_CH1)    ||\
+                                  ((__TISEL__) == TIM_TIM15_TI1_RCC_LSE)     ||\
+                                  ((__TISEL__) == TIM_TIM15_TI1_RCC_CSI)     ||\
+                                  ((__TISEL__) == TIM_TIM15_TI1_RCC_MCO2)    ||\
+                                  ((__TISEL__) == TIM_TIM15_TI2_GPIO)        ||\
+                                  ((__TISEL__) == TIM_TIM15_TI2_TIM2_CH2)    ||\
+                                  ((__TISEL__) == TIM_TIM15_TI2_TIM3_CH2)    ||\
+                                  ((__TISEL__) == TIM_TIM15_TI2_TIM4_CH2)    ||\
+                                  ((__TISEL__) == TIM_TIM16_TI1_GPIO)        ||\
+                                  ((__TISEL__) == TIM_TIM16_TI1_RCC_LSI)     ||\
+                                  ((__TISEL__) == TIM_TIM16_TI1_RCC_LSE)     ||\
+                                  ((__TISEL__) == TIM_TIM16_TI1_WKUP_IT)     ||\
+                                  ((__TISEL__) == TIM_TIM17_TI1_GPIO)        ||\
+                                  ((__TISEL__) == TIM_TIM17_TI1_SPDIF_FS)    ||\
+                                  ((__TISEL__) == TIM_TIM17_TI1_RCC_HSE1MHZ) ||\
+                                  ((__TISEL__) == TIM_TIM17_TI1_RCC_MCO1)    ||\
+                                  ((__TISEL__) == TIM_TIM23_TI4_GPIO)        ||\
+                                  ((__TISEL__) == TIM_TIM23_TI4_COMP1)       ||\
+                                  ((__TISEL__) == TIM_TIM23_TI4_COMP2)       ||\
+                                  ((__TISEL__) == TIM_TIM23_TI4_COMP1_COMP2) ||\
+                                  ((__TISEL__) == TIM_TIM24_TI1_GPIO)        ||\
+                                  ((__TISEL__) == TIM_TIM24_TI1_CAN_TMP)     ||\
+                                  ((__TISEL__) == TIM_TIM24_TI1_CAN_RTP)     ||\
+                                  ((__TISEL__) == TIM_TIM24_TI1_CAN_SOC))
+
+#define IS_TIM_REMAP(__RREMAP__)     (((__RREMAP__) == TIM_TIM1_ETR_GPIO)      ||\
+                                      ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD1) ||\
+                                      ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD2) ||\
+                                      ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD3) ||\
+                                      ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD1) ||\
+                                      ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD2) ||\
+                                      ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD3) ||\
+                                      ((__RREMAP__) == TIM_TIM1_ETR_COMP1)     ||\
+                                      ((__RREMAP__) == TIM_TIM1_ETR_COMP2)     ||\
+                                      ((__RREMAP__) == TIM_TIM8_ETR_GPIO)      ||\
+                                      ((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD1) ||\
+                                      ((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD2) ||\
+                                      ((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD3) ||\
+                                      ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD1) ||\
+                                      ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD2) ||\
+                                      ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD3) ||\
+                                      ((__RREMAP__) == TIM_TIM8_ETR_COMP1)     ||\
+                                      ((__RREMAP__) == TIM_TIM8_ETR_COMP2)     ||\
+                                      ((__RREMAP__) == TIM_TIM2_ETR_GPIO)      ||\
+                                      ((__RREMAP__) == TIM_TIM2_ETR_COMP1)     ||\
+                                      ((__RREMAP__) == TIM_TIM2_ETR_COMP2)     ||\
+                                      ((__RREMAP__) == TIM_TIM2_ETR_RCC_LSE)   ||\
+                                      ((__RREMAP__) == TIM_TIM2_ETR_SAI1_FSA)  ||\
+                                      ((__RREMAP__) == TIM_TIM2_ETR_SAI1_FSB)  ||\
+                                      ((__RREMAP__) == TIM_TIM3_ETR_GPIO)      ||\
+                                      ((__RREMAP__) == TIM_TIM3_ETR_COMP1)     ||\
+                                      ((__RREMAP__) == TIM_TIM5_ETR_GPIO)      ||\
+                                      ((__RREMAP__) == TIM_TIM5_ETR_SAI2_FSA)  ||\
+                                      ((__RREMAP__) == TIM_TIM5_ETR_SAI2_FSB)  ||\
+                                      ((__RREMAP__) == TIM_TIM23_ETR_GPIO)     ||\
+                                      ((__RREMAP__) == TIM_TIM23_ETR_COMP1)    ||\
+                                      ((__RREMAP__) == TIM_TIM23_ETR_COMP2)    ||\
+                                      ((__RREMAP__) == TIM_TIM24_ETR_GPIO)     ||\
+                                      ((__RREMAP__) == TIM_TIM24_ETR_SAI4_FSA) ||\
+                                      ((__RREMAP__) == TIM_TIM24_ETR_SAI4_FSB) ||\
+                                      ((__RREMAP__) == TIM_TIM24_ETR_SAI1_FSA) ||\
+                                      ((__RREMAP__) == TIM_TIM24_ETR_SAI1_FSB))
+
+/**
+  * @}
+  */
+/* End of private macro ------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
+  * @{
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
+  *  @brief    Timer Hall Sensor functions
+  * @{
+  */
+/*  Timer Hall Sensor functions  **********************************************/
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
+
+void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
+
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
+  *  @brief   Timer Complementary Output Compare functions
+  * @{
+  */
+/*  Timer Complementary Output Compare functions  *****************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
+  *  @brief    Timer Complementary PWM functions
+  * @{
+  */
+/*  Timer Complementary PWM functions  ****************************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
+  *  @brief    Timer Complementary One Pulse functions
+  * @{
+  */
+/*  Timer Complementary One Pulse functions  **********************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
+  *  @brief    Peripheral Control functions
+  * @{
+  */
+/* Extended Control functions  ************************************************/
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                              uint32_t  CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                                 uint32_t  CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                                  uint32_t  CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+                                                        TIM_MasterConfigTypeDef *sMasterConfig);
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
+                                                TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
+#if defined(TIM_BREAK_INPUT_SUPPORT)
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput,
+                                             TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
+#endif /* TIM_BREAK_INPUT_SUPPORT */
+HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
+HAL_StatusTypeDef  HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
+  * @brief    Extended Callbacks functions
+  * @{
+  */
+/* Extended Callback **********************************************************/
+void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
+  * @brief    Extended Peripheral State functions
+  * @{
+  */
+/* Extended Peripheral State functions  ***************************************/
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private functions----------------------------------------------------------*/
+/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions
+  * @{
+  */
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
+void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+/* End of private functions --------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32H7xx_HAL_TIM_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bus.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bus.h
new file mode 100644
index 00000000..6ee1528a
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bus.h
@@ -0,0 +1,6635 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_bus.h
+  * @author  MCD Application Team
+  * @version $VERSION$
+  * @date    $DATE$
+  * @brief   Header file of BUS LL module.
+
+  @verbatim
+                      ##### RCC Limitations #####
+  ==============================================================================
+    [..]
+      A delay between an RCC peripheral clock enable and the effective peripheral
+      enabling should be taken into account in order to manage the peripheral read/write
+      from/to registers.
+      (+) This delay depends on the peripheral mapping.
+        (++) AHB & APB peripherals, 1 dummy read is necessary
+
+    [..]
+      Workarounds:
+      (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
+          inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_LL_BUS_H
+#define STM32H7xx_LL_BUS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined(RCC)
+
+/** @defgroup BUS_LL BUS
+  * @{
+  */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
+  * @{
+  */
+
+/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH  AHB3 GRP1 PERIPH
+  * @{
+  */
+#define LL_AHB3_GRP1_PERIPH_MDMA           RCC_AHB3ENR_MDMAEN
+#define LL_AHB3_GRP1_PERIPH_DMA2D          RCC_AHB3ENR_DMA2DEN
+
+#if defined(JPEG)
+#define LL_AHB3_GRP1_PERIPH_JPGDEC         RCC_AHB3ENR_JPGDECEN
+#endif /* JPEG */
+
+#define LL_AHB3_GRP1_PERIPH_FMC            RCC_AHB3ENR_FMCEN
+#if defined(QUADSPI)
+#define LL_AHB3_GRP1_PERIPH_QSPI           RCC_AHB3ENR_QSPIEN
+#endif /* QUADSPI */
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+#define LL_AHB3_GRP1_PERIPH_OSPI1          RCC_AHB3ENR_OSPI1EN
+#define LL_AHB3_GRP1_PERIPH_OSPI2          RCC_AHB3ENR_OSPI2EN
+#endif /*(OCTOSPI1) || (OCTOSPI2)*/
+#if defined(OCTOSPIM)
+#define LL_AHB3_GRP1_PERIPH_OCTOSPIM       RCC_AHB3ENR_IOMNGREN
+#endif /* OCTOSPIM */
+#if defined(OTFDEC1) || defined(OTFDEC2)
+#define LL_AHB3_GRP1_PERIPH_OTFDEC1        RCC_AHB3ENR_OTFDEC1EN
+#define LL_AHB3_GRP1_PERIPH_OTFDEC2        RCC_AHB3ENR_OTFDEC2EN
+#endif /* (OTFDEC1) || (OTFDEC2) */
+#if defined(GFXMMU)
+#define LL_AHB3_GRP1_PERIPH_GFXMMU         RCC_AHB3ENR_GFXMMUEN
+#endif /* GFXMMU */
+#define LL_AHB3_GRP1_PERIPH_SDMMC1         RCC_AHB3ENR_SDMMC1EN
+#define LL_AHB3_GRP1_PERIPH_FLASH          RCC_AHB3LPENR_FLASHLPEN
+#define LL_AHB3_GRP1_PERIPH_DTCM1          RCC_AHB3LPENR_DTCM1LPEN
+#define LL_AHB3_GRP1_PERIPH_DTCM2          RCC_AHB3LPENR_DTCM2LPEN
+#define LL_AHB3_GRP1_PERIPH_ITCM           RCC_AHB3LPENR_ITCMLPEN
+#if defined(RCC_AHB3LPENR_AXISRAMLPEN)
+#define LL_AHB3_GRP1_PERIPH_AXISRAM        RCC_AHB3LPENR_AXISRAMLPEN
+#else
+#define LL_AHB3_GRP1_PERIPH_AXISRAM1       RCC_AHB3LPENR_AXISRAM1LPEN
+#define LL_AHB3_GRP1_PERIPH_AXISRAM        LL_AHB3_GRP1_PERIPH_AXISRAM1   /* for backward compatibility*/
+#endif /* RCC_AHB3LPENR_AXISRAMLPEN */
+#if defined(CD_AXISRAM2_BASE)
+#define LL_AHB3_GRP1_PERIPH_AXISRAM2       RCC_AHB3LPENR_AXISRAM2LPEN
+#endif /* CD_AXISRAM2_BASE */
+#if defined(CD_AXISRAM3_BASE)
+#define LL_AHB3_GRP1_PERIPH_AXISRAM3       RCC_AHB3LPENR_AXISRAM3LPEN
+#endif /* CD_AXISRAM3_BASE */
+/**
+  * @}
+  */
+
+
+/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH  AHB1 GRP1 PERIPH
+  * @{
+  */
+#define LL_AHB1_GRP1_PERIPH_DMA1           RCC_AHB1ENR_DMA1EN
+#define LL_AHB1_GRP1_PERIPH_DMA2           RCC_AHB1ENR_DMA2EN
+#define LL_AHB1_GRP1_PERIPH_ADC12          RCC_AHB1ENR_ADC12EN
+#if defined(DUAL_CORE)
+#define LL_AHB1_GRP1_PERIPH_ART            RCC_AHB1ENR_ARTEN
+#endif /* DUAL_CORE */
+#if defined(RCC_AHB1ENR_CRCEN)
+#define LL_AHB1_GRP1_PERIPH_CRC            RCC_AHB1ENR_CRCEN
+#endif /* RCC_AHB1ENR_CRCEN */
+#if defined(ETH)
+#define LL_AHB1_GRP1_PERIPH_ETH1MAC        RCC_AHB1ENR_ETH1MACEN
+#define LL_AHB1_GRP1_PERIPH_ETH1TX         RCC_AHB1ENR_ETH1TXEN
+#define LL_AHB1_GRP1_PERIPH_ETH1RX         RCC_AHB1ENR_ETH1RXEN
+#endif /* ETH */
+#define LL_AHB1_GRP1_PERIPH_USB1OTGHS      RCC_AHB1ENR_USB1OTGHSEN
+#define LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI  RCC_AHB1ENR_USB1OTGHSULPIEN
+#if defined(USB2_OTG_FS)
+#define LL_AHB1_GRP1_PERIPH_USB2OTGHS      RCC_AHB1ENR_USB2OTGHSEN
+#define LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI  RCC_AHB1ENR_USB2OTGHSULPIEN
+#endif /* USB2_OTG_FS */
+/**
+  * @}
+  */
+
+
+/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH  AHB2 GRP1 PERIPH
+  * @{
+  */
+#define LL_AHB2_GRP1_PERIPH_DCMI           RCC_AHB2ENR_DCMIEN
+#if defined(HSEM) && defined(RCC_AHB2ENR_HSEMEN)
+#define LL_AHB2_GRP1_PERIPH_HSEM           RCC_AHB2ENR_HSEMEN
+#endif /* HSEM && RCC_AHB2ENR_HSEMEN */
+#if defined(CRYP)
+#define LL_AHB2_GRP1_PERIPH_CRYP           RCC_AHB2ENR_CRYPEN
+#endif /* CRYP */
+#if defined(HASH)
+#define LL_AHB2_GRP1_PERIPH_HASH           RCC_AHB2ENR_HASHEN
+#endif /* HASH */
+#define LL_AHB2_GRP1_PERIPH_RNG            RCC_AHB2ENR_RNGEN
+#define LL_AHB2_GRP1_PERIPH_SDMMC2         RCC_AHB2ENR_SDMMC2EN
+#if defined(BDMA1)
+#define LL_AHB2_GRP1_PERIPH_BDMA1          RCC_AHB2ENR_BDMA1EN
+#endif /* BDMA1 */
+#if defined(RCC_AHB2ENR_D2SRAM1EN)
+#define LL_AHB2_GRP1_PERIPH_D2SRAM1        RCC_AHB2ENR_D2SRAM1EN
+#else
+#define LL_AHB2_GRP1_PERIPH_AHBSRAM1       RCC_AHB2ENR_AHBSRAM1EN
+#define LL_AHB2_GRP1_PERIPH_D2SRAM1        LL_AHB2_GRP1_PERIPH_AHBSRAM1    /* for backward compatibility*/
+#endif /* RCC_AHB2ENR_D2SRAM1EN */
+#if defined(RCC_AHB2ENR_D2SRAM2EN)
+#define LL_AHB2_GRP1_PERIPH_D2SRAM2        RCC_AHB2ENR_D2SRAM2EN
+#else
+#define LL_AHB2_GRP1_PERIPH_AHBSRAM2       RCC_AHB2ENR_AHBSRAM2EN
+#define LL_AHB2_GRP1_PERIPH_D2SRAM2        LL_AHB2_GRP1_PERIPH_AHBSRAM2    /* for backward compatibility*/
+#endif /* RCC_AHB2ENR_D2SRAM2EN */
+#if defined(RCC_AHB2ENR_D2SRAM3EN)
+#define LL_AHB2_GRP1_PERIPH_D2SRAM3        RCC_AHB2ENR_D2SRAM3EN
+#endif /* RCC_AHB2ENR_D2SRAM3EN */
+/**
+  * @}
+  */
+
+
+/** @defgroup BUS_LL_EC_AHB4_GRP1_PERIPH  AHB4 GRP1 PERIPH
+  * @{
+  */
+#define LL_AHB4_GRP1_PERIPH_GPIOA          RCC_AHB4ENR_GPIOAEN
+#define LL_AHB4_GRP1_PERIPH_GPIOB          RCC_AHB4ENR_GPIOBEN
+#define LL_AHB4_GRP1_PERIPH_GPIOC          RCC_AHB4ENR_GPIOCEN
+#define LL_AHB4_GRP1_PERIPH_GPIOD          RCC_AHB4ENR_GPIODEN
+#define LL_AHB4_GRP1_PERIPH_GPIOE          RCC_AHB4ENR_GPIOEEN
+#define LL_AHB4_GRP1_PERIPH_GPIOF          RCC_AHB4ENR_GPIOFEN
+#define LL_AHB4_GRP1_PERIPH_GPIOG          RCC_AHB4ENR_GPIOGEN
+#define LL_AHB4_GRP1_PERIPH_GPIOH          RCC_AHB4ENR_GPIOHEN
+#define LL_AHB4_GRP1_PERIPH_GPIOI          RCC_AHB4ENR_GPIOIEN
+#define LL_AHB4_GRP1_PERIPH_GPIOJ          RCC_AHB4ENR_GPIOJEN
+#define LL_AHB4_GRP1_PERIPH_GPIOK          RCC_AHB4ENR_GPIOKEN
+#if defined(RCC_AHB4ENR_CRCEN)
+#define LL_AHB4_GRP1_PERIPH_CRC            RCC_AHB4ENR_CRCEN
+#endif /* RCC_AHB4ENR_CRCEN */
+#if defined(BDMA2)
+#define LL_AHB4_GRP1_PERIPH_BDMA2          RCC_AHB4ENR_BDMA2EN
+#define LL_AHB4_GRP1_PERIPH_BDMA           LL_AHB4_GRP1_PERIPH_BDMA2  /* for backward compatibility*/
+#else
+#define LL_AHB4_GRP1_PERIPH_BDMA           RCC_AHB4ENR_BDMAEN
+#endif /* BDMA2 */
+#if defined(ADC3)
+#define LL_AHB4_GRP1_PERIPH_ADC3           RCC_AHB4ENR_ADC3EN
+#endif /* ADC3 */
+#if defined(HSEM) && defined(RCC_AHB4ENR_HSEMEN)
+#define LL_AHB4_GRP1_PERIPH_HSEM           RCC_AHB4ENR_HSEMEN
+#endif /* HSEM && RCC_AHB4ENR_HSEMEN*/
+#define LL_AHB4_GRP1_PERIPH_BKPRAM         RCC_AHB4ENR_BKPRAMEN
+#if defined(RCC_AHB4LPENR_SRAM4LPEN)
+#define LL_AHB4_GRP1_PERIPH_SRAM4          RCC_AHB4LPENR_SRAM4LPEN
+#define LL_AHB4_GRP1_PERIPH_D3SRAM1        LL_AHB4_GRP1_PERIPH_SRAM4
+#else
+#define LL_AHB4_GRP1_PERIPH_SRDSRAM        RCC_AHB4ENR_SRDSRAMEN
+#define LL_AHB4_GRP1_PERIPH_SRAM4          LL_AHB4_GRP1_PERIPH_SRDSRAM  /* for backward compatibility*/
+#define LL_AHB4_GRP1_PERIPH_D3SRAM1        LL_AHB4_GRP1_PERIPH_SRDSRAM  /* for backward compatibility*/
+#endif /* RCC_AHB4ENR_D3SRAM1EN */
+/**
+  * @}
+  */
+
+
+/** @defgroup BUS_LL_EC_APB3_GRP1_PERIPH  APB3 GRP1 PERIPH
+  * @{
+  */
+#define LL_APB3_GRP1_PERIPH_LTDC           RCC_APB3ENR_LTDCEN
+#if defined(DSI)
+#define LL_APB3_GRP1_PERIPH_DSI            RCC_APB3ENR_DSIEN
+#endif /* DSI */
+#define LL_APB3_GRP1_PERIPH_WWDG1          RCC_APB3ENR_WWDG1EN
+#if defined(RCC_APB3ENR_WWDGEN)
+#define LL_APB3_GRP1_PERIPH_WWDG           LL_APB3_GRP1_PERIPH_WWDG1   /* for backward compatibility*/
+#endif
+/**
+  * @}
+  */
+
+
+/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH  APB1 GRP1 PERIPH
+  * @{
+  */
+#define LL_APB1_GRP1_PERIPH_TIM2           RCC_APB1LENR_TIM2EN
+#define LL_APB1_GRP1_PERIPH_TIM3           RCC_APB1LENR_TIM3EN
+#define LL_APB1_GRP1_PERIPH_TIM4           RCC_APB1LENR_TIM4EN
+#define LL_APB1_GRP1_PERIPH_TIM5           RCC_APB1LENR_TIM5EN
+#define LL_APB1_GRP1_PERIPH_TIM6           RCC_APB1LENR_TIM6EN
+#define LL_APB1_GRP1_PERIPH_TIM7           RCC_APB1LENR_TIM7EN
+#define LL_APB1_GRP1_PERIPH_TIM12          RCC_APB1LENR_TIM12EN
+#define LL_APB1_GRP1_PERIPH_TIM13          RCC_APB1LENR_TIM13EN
+#define LL_APB1_GRP1_PERIPH_TIM14          RCC_APB1LENR_TIM14EN
+#define LL_APB1_GRP1_PERIPH_LPTIM1         RCC_APB1LENR_LPTIM1EN
+#if defined(DUAL_CORE)
+#define LL_APB1_GRP1_PERIPH_WWDG2          RCC_APB1LENR_WWDG2EN
+#endif /*DUAL_CORE*/
+#define LL_APB1_GRP1_PERIPH_SPI2           RCC_APB1LENR_SPI2EN
+#define LL_APB1_GRP1_PERIPH_SPI3           RCC_APB1LENR_SPI3EN
+#define LL_APB1_GRP1_PERIPH_SPDIFRX        RCC_APB1LENR_SPDIFRXEN
+#define LL_APB1_GRP1_PERIPH_USART2         RCC_APB1LENR_USART2EN
+#define LL_APB1_GRP1_PERIPH_USART3         RCC_APB1LENR_USART3EN
+#define LL_APB1_GRP1_PERIPH_UART4          RCC_APB1LENR_UART4EN
+#define LL_APB1_GRP1_PERIPH_UART5          RCC_APB1LENR_UART5EN
+#define LL_APB1_GRP1_PERIPH_I2C1           RCC_APB1LENR_I2C1EN
+#define LL_APB1_GRP1_PERIPH_I2C2           RCC_APB1LENR_I2C2EN
+#define LL_APB1_GRP1_PERIPH_I2C3           RCC_APB1LENR_I2C3EN
+#define LL_APB1_GRP1_PERIPH_CEC            RCC_APB1LENR_CECEN
+#define LL_APB1_GRP1_PERIPH_DAC12          RCC_APB1LENR_DAC12EN
+#define LL_APB1_GRP1_PERIPH_UART7          RCC_APB1LENR_UART7EN
+#define LL_APB1_GRP1_PERIPH_UART8          RCC_APB1LENR_UART8EN
+/**
+  * @}
+  */
+
+
+/** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH  APB1 GRP2 PERIPH
+  * @{
+  */
+#define LL_APB1_GRP2_PERIPH_CRS            RCC_APB1HENR_CRSEN
+#define LL_APB1_GRP2_PERIPH_SWPMI1         RCC_APB1HENR_SWPMIEN
+#define LL_APB1_GRP2_PERIPH_OPAMP          RCC_APB1HENR_OPAMPEN
+#define LL_APB1_GRP2_PERIPH_MDIOS          RCC_APB1HENR_MDIOSEN
+#define LL_APB1_GRP2_PERIPH_FDCAN          RCC_APB1HENR_FDCANEN
+/**
+  * @}
+  */
+
+
+/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH  APB2 GRP1 PERIPH
+  * @{
+  */
+#define LL_APB2_GRP1_PERIPH_TIM1           RCC_APB2ENR_TIM1EN
+#define LL_APB2_GRP1_PERIPH_TIM8           RCC_APB2ENR_TIM8EN
+#define LL_APB2_GRP1_PERIPH_USART1         RCC_APB2ENR_USART1EN
+#define LL_APB2_GRP1_PERIPH_USART6         RCC_APB2ENR_USART6EN
+#if defined(UART9)
+#define LL_APB2_GRP1_PERIPH_UART9          RCC_APB2ENR_UART9EN
+#endif /* UART9 */
+#if defined(USART10)
+#define LL_APB2_GRP1_PERIPH_USART10        RCC_APB2ENR_USART10EN
+#endif /* USART10 */
+#define LL_APB2_GRP1_PERIPH_SPI1           RCC_APB2ENR_SPI1EN
+#define LL_APB2_GRP1_PERIPH_SPI4           RCC_APB2ENR_SPI4EN
+#define LL_APB2_GRP1_PERIPH_TIM15          RCC_APB2ENR_TIM15EN
+#define LL_APB2_GRP1_PERIPH_TIM16          RCC_APB2ENR_TIM16EN
+#define LL_APB2_GRP1_PERIPH_TIM17          RCC_APB2ENR_TIM17EN
+#define LL_APB2_GRP1_PERIPH_SPI5           RCC_APB2ENR_SPI5EN
+#define LL_APB2_GRP1_PERIPH_SAI1           RCC_APB2ENR_SAI1EN
+#define LL_APB2_GRP1_PERIPH_SAI2           RCC_APB2ENR_SAI2EN
+#if defined(SAI3)
+#define LL_APB2_GRP1_PERIPH_SAI3           RCC_APB2ENR_SAI3EN
+#endif /* SAI3 */
+#define LL_APB2_GRP1_PERIPH_DFSDM1         RCC_APB2ENR_DFSDM1EN
+#if defined(HRTIM1)
+#define LL_APB2_GRP1_PERIPH_HRTIM          RCC_APB2ENR_HRTIMEN
+#endif /* HRTIM1 */
+/**
+  * @}
+  */
+
+
+/** @defgroup BUS_LL_EC_APB4_GRP1_PERIPH  APB4 GRP1 PERIPH
+  * @{
+  */
+#define LL_APB4_GRP1_PERIPH_SYSCFG         RCC_APB4ENR_SYSCFGEN
+#define LL_APB4_GRP1_PERIPH_LPUART1        RCC_APB4ENR_LPUART1EN
+#define LL_APB4_GRP1_PERIPH_SPI6           RCC_APB4ENR_SPI6EN
+#define LL_APB4_GRP1_PERIPH_I2C4           RCC_APB4ENR_I2C4EN
+#define LL_APB4_GRP1_PERIPH_LPTIM2         RCC_APB4ENR_LPTIM2EN
+#define LL_APB4_GRP1_PERIPH_LPTIM3         RCC_APB4ENR_LPTIM3EN
+#if defined(LPTIM4)
+#define LL_APB4_GRP1_PERIPH_LPTIM4         RCC_APB4ENR_LPTIM4EN
+#endif /* LPTIM4 */
+#if defined(LPTIM5)
+#define LL_APB4_GRP1_PERIPH_LPTIM5         RCC_APB4ENR_LPTIM5EN
+#endif /* LPTIM5 */
+#if defined(DAC2)
+#define LL_APB4_GRP1_PERIPH_DAC2           RCC_APB4ENR_DAC2EN
+#endif /* DAC2 */
+#define LL_APB4_GRP1_PERIPH_COMP12         RCC_APB4ENR_COMP12EN
+#define LL_APB4_GRP1_PERIPH_VREF           RCC_APB4ENR_VREFEN
+#define LL_APB4_GRP1_PERIPH_RTCAPB         RCC_APB4ENR_RTCAPBEN
+#if defined(SAI4)
+#define LL_APB4_GRP1_PERIPH_SAI4           RCC_APB4ENR_SAI4EN
+#endif /* SAI4 */
+#if defined(DTS)
+#define LL_APB4_GRP1_PERIPH_DTS            RCC_APB4ENR_DTSEN
+#endif /*DTS*/
+#if defined(DFSDM2_BASE)
+#define LL_APB4_GRP1_PERIPH_DFSDM2         RCC_APB4ENR_DFSDM2EN
+#endif /* DFSDM2_BASE */
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EC_CLKAM_PERIPH  CLKAM PERIPH
+  * @{
+  */
+#if defined(RCC_D3AMR_BDMAAMEN)
+#define LL_CLKAM_PERIPH_BDMA          RCC_D3AMR_BDMAAMEN
+#else
+#define LL_CLKAM_PERIPH_BDMA2         RCC_SRDAMR_BDMA2AMEN
+#define LL_CLKAM_PERIPH_BDMA          LL_CLKAM_PERIPH_BDMA2 /* for backward compatibility*/
+#endif /* RCC_D3AMR_BDMAAMEN */
+#if defined(RCC_SRDAMR_GPIOAMEN)
+#define LL_CLKAM_PERIPH_GPIO          RCC_SRDAMR_GPIOAMEN
+#endif /* RCC_SRDAMR_GPIOAMEN */
+#if defined(RCC_D3AMR_LPUART1AMEN)
+#define LL_CLKAM_PERIPH_LPUART1       RCC_D3AMR_LPUART1AMEN
+#else
+#define LL_CLKAM_PERIPH_LPUART1       RCC_SRDAMR_LPUART1AMEN
+#endif /* RCC_D3AMR_LPUART1AMEN */
+#if defined(RCC_D3AMR_SPI6AMEN)
+#define LL_CLKAM_PERIPH_SPI6          RCC_D3AMR_SPI6AMEN
+#else
+#define LL_CLKAM_PERIPH_SPI6          RCC_SRDAMR_SPI6AMEN
+#endif /* RCC_D3AMR_SPI6AMEN */
+#if defined(RCC_D3AMR_I2C4AMEN)
+#define LL_CLKAM_PERIPH_I2C4          RCC_D3AMR_I2C4AMEN
+#else
+#define LL_CLKAM_PERIPH_I2C4          RCC_SRDAMR_I2C4AMEN
+#endif /* RCC_D3AMR_I2C4AMEN */
+#if defined(RCC_D3AMR_LPTIM2AMEN)
+#define LL_CLKAM_PERIPH_LPTIM2        RCC_D3AMR_LPTIM2AMEN
+#else
+#define LL_CLKAM_PERIPH_LPTIM2        RCC_SRDAMR_LPTIM2AMEN
+#endif /* RCC_D3AMR_LPTIM2AMEN */
+#if defined(RCC_D3AMR_LPTIM3AMEN)
+#define LL_CLKAM_PERIPH_LPTIM3        RCC_D3AMR_LPTIM3AMEN
+#else
+#define LL_CLKAM_PERIPH_LPTIM3        RCC_SRDAMR_LPTIM3AMEN
+#endif /* RCC_D3AMR_LPTIM3AMEN */
+#if defined(RCC_D3AMR_LPTIM4AMEN)
+#define LL_CLKAM_PERIPH_LPTIM4        RCC_D3AMR_LPTIM4AMEN
+#endif /* RCC_D3AMR_LPTIM4AMEN */
+#if defined(RCC_D3AMR_LPTIM5AMEN)
+#define LL_CLKAM_PERIPH_LPTIM5        RCC_D3AMR_LPTIM5AMEN
+#endif /* RCC_D3AMR_LPTIM5AMEN */
+#if defined(DAC2)
+#define LL_CLKAM_PERIPH_DAC2          RCC_SRDAMR_DAC2AMEN
+#endif /* DAC2 */
+#if defined(RCC_D3AMR_COMP12AMEN)
+#define LL_CLKAM_PERIPH_COMP12        RCC_D3AMR_COMP12AMEN
+#else
+#define LL_CLKAM_PERIPH_COMP12        RCC_SRDAMR_COMP12AMEN
+#endif /* RCC_D3AMR_COMP12AMEN */
+#if defined(RCC_D3AMR_VREFAMEN)
+#define LL_CLKAM_PERIPH_VREF          RCC_D3AMR_VREFAMEN
+#else
+#define LL_CLKAM_PERIPH_VREF          RCC_SRDAMR_VREFAMEN
+#endif /* RCC_D3AMR_VREFAMEN */
+#if defined(RCC_D3AMR_RTCAMEN)
+#define LL_CLKAM_PERIPH_RTC           RCC_D3AMR_RTCAMEN
+#else
+#define LL_CLKAM_PERIPH_RTC           RCC_SRDAMR_RTCAMEN
+#endif /* RCC_D3AMR_RTCAMEN */
+#if defined(RCC_D3AMR_CRCAMEN)
+#define LL_CLKAM_PERIPH_CRC           RCC_D3AMR_CRCAMEN
+#endif /* RCC_D3AMR_CRCAMEN */
+#if defined(SAI4)
+#define LL_CLKAM_PERIPH_SAI4          RCC_D3AMR_SAI4AMEN
+#endif /* SAI4 */
+#if defined(ADC3)
+#define LL_CLKAM_PERIPH_ADC3          RCC_D3AMR_ADC3AMEN
+#endif /* ADC3 */
+#if defined(DTS)
+#define LL_CLKAM_PERIPH_DTS           RCC_SRDAMR_DTSAMEN
+#endif /* DTS */
+#if defined(DFSDM2_BASE)
+#define LL_CLKAM_PERIPH_DFSDM2        RCC_SRDAMR_DFSDM2AMEN
+#endif /* DFSDM2_BASE */
+#if defined(RCC_D3AMR_BKPRAMAMEN)
+#define LL_CLKAM_PERIPH_BKPRAM        RCC_D3AMR_BKPRAMAMEN
+#else
+#define LL_CLKAM_PERIPH_BKPRAM        RCC_SRDAMR_BKPRAMAMEN
+#endif /* RCC_D3AMR_BKPRAMAMEN */
+#if defined(RCC_D3AMR_SRAM4AMEN)
+#define LL_CLKAM_PERIPH_SRAM4         RCC_D3AMR_SRAM4AMEN
+#else
+#define LL_CLKAM_PERIPH_SRDSRAM       RCC_SRDAMR_SRDSRAMAMEN
+#define LL_CLKAM_PERIPH_SRAM4         LL_CLKAM_PERIPH_SRDSRAM
+#endif /* RCC_D3AMR_SRAM4AMEN */
+/**
+  * @}
+  */
+
+#if defined(RCC_CKGAENR_AXICKG)
+/** @defgroup BUS_LL_EC_CKGA_PERIPH  CKGA (AXI Clocks Gating) PERIPH
+  * @{
+  */
+#define LL_CKGA_PERIPH_AXI            RCC_CKGAENR_AXICKG
+#define LL_CKGA_PERIPH_AHB            RCC_CKGAENR_AHBCKG
+#define LL_CKGA_PERIPH_CPU            RCC_CKGAENR_CPUCKG
+#define LL_CKGA_PERIPH_SDMMC          RCC_CKGAENR_SDMMCCKG
+#define LL_CKGA_PERIPH_MDMA           RCC_CKGAENR_MDMACKG
+#define LL_CKGA_PERIPH_DMA2D          RCC_CKGAENR_DMA2DCKG
+#define LL_CKGA_PERIPH_LTDC           RCC_CKGAENR_LTDCCKG
+#define LL_CKGA_PERIPH_GFXMMUM        RCC_CKGAENR_GFXMMUMCKG
+#define LL_CKGA_PERIPH_AHB12          RCC_CKGAENR_AHB12CKG
+#define LL_CKGA_PERIPH_AHB34          RCC_CKGAENR_AHB34CKG
+#define LL_CKGA_PERIPH_FLIFT          RCC_CKGAENR_FLIFTCKG
+#define LL_CKGA_PERIPH_OCTOSPI2       RCC_CKGAENR_OCTOSPI2CKG
+#define LL_CKGA_PERIPH_FMC            RCC_CKGAENR_FMCCKG
+#define LL_CKGA_PERIPH_OCTOSPI1       RCC_CKGAENR_OCTOSPI1CKG
+#define LL_CKGA_PERIPH_AXIRAM1        RCC_CKGAENR_AXIRAM1CKG
+#define LL_CKGA_PERIPH_AXIRAM2        RCC_CKGAENR_AXIRAM2CKG
+#define LL_CKGA_PERIPH_AXIRAM3        RCC_CKGAENR_AXIRAM3CKG
+#define LL_CKGA_PERIPH_GFXMMUS        RCC_CKGAENR_GFXMMUSCKG
+#define LL_CKGA_PERIPH_ECCRAM         RCC_CKGAENR_ECCRAMCKG
+#define LL_CKGA_PERIPH_EXTI           RCC_CKGAENR_EXTICKG
+#define LL_CKGA_PERIPH_JTAG           RCC_CKGAENR_JTAGCKG
+/**
+  * @}
+  */
+#endif /* RCC_CKGAENR_AXICKG */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
+  * @{
+  */
+
+/** @defgroup BUS_LL_EF_AHB3 AHB3
+  * @{
+  */
+
+/**
+  * @brief  Enable AHB3 peripherals clock.
+  * @rmtoll AHB3ENR      MDMAEN        LL_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      DMA2DEN       LL_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      JPGDECEN      LL_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      FMCEN         LL_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_EnableClock\n  (*)
+  *         AHB3ENR      OSPI1EN       LL_AHB3_GRP1_EnableClock\n  (*)
+  *         AHB3ENR      OSPI2EN       LL_AHB3_GRP1_EnableClock\n  (*)
+  *         AHB3ENR      IOMNGREN      LL_AHB3_GRP1_EnableClock\n  (*)
+  *         AHB3ENR      OTFDEC1EN     LL_AHB3_GRP1_EnableClock\n  (*)
+  *         AHB3ENR      OTFDEC2EN     LL_AHB3_GRP1_EnableClock\n  (*)
+  *         AHB3ENR      GFXMMU        LL_AHB3_GRP1_EnableClock\n  (*)
+  *         AHB3ENR      SDMMC1EN      LL_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      FLASHEN       LL_AHB3_GRP1_EnableClock\n  (*)
+  *         AHB3ENR      DTCM1EN       LL_AHB3_GRP1_EnableClock\n  (*)
+  *         AHB3ENR      DTCM2EN       LL_AHB3_GRP1_EnableClock\n  (*)
+  *         AHB3ENR      ITCMEN        LL_AHB3_GRP1_EnableClock\n  (*)
+  *         AHB3ENR      AXISRAMEN     LL_AHB3_GRP1_EnableClock    (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB3ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if AHB3 peripheral clock is enabled or not
+  * @rmtoll AHB3ENR      MDMAEN        LL_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      DMA2DEN       LL_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      JPGDECEN      LL_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      FMCEN         LL_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      OSPI1EN       LL_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      OSPI2EN       LL_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      IOMNGREN      LL_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      OTFDEC1EN     LL_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      OTFDEC2EN     LL_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      GFXMMU        LL_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      SDMMC1EN      LL_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      FLASHEN       LL_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      DTCM1EN       LL_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      DTCM2EN       LL_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      ITCMEN        LL_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      AXISRAMEN     LL_AHB3_GRP1_IsEnabledClock   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1   (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2   (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_IOMNGR  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable AHB3 peripherals clock.
+  * @rmtoll AHB3ENR      MDMAEN        LL_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      DMA2DEN       LL_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      JPGDECEN      LL_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      FMCEN         LL_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      OSPI1EN       LL_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      OSPI2EN       LL_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      IOMNGREN      LL_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      OTFDEC1EN     LL_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      OTFDEC2EN     LL_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      GFXMMU        LL_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      SDMMC1EN      LL_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      FLASHEN       LL_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      DTCM1EN       LL_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      DTCM2EN       LL_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      ITCMEN        LL_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      AXISRAMEN     LL_AHB3_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1   (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2   (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_IOMNGR  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB3ENR, Periphs);
+}
+
+/**
+  * @brief  Force AHB3 peripherals reset.
+  * @rmtoll AHB3RSTR     MDMARST       LL_AHB3_GRP1_ForceReset\n
+  *         AHB3RSTR     DMA2DRST      LL_AHB3_GRP1_ForceReset\n
+  *         AHB3RSTR     JPGDECRST     LL_AHB3_GRP1_ForceReset\n
+  *         AHB3RSTR     FMCRST        LL_AHB3_GRP1_ForceReset\n
+  *         AHB3RSTR     QSPIRST       LL_AHB3_GRP1_ForceReset\n (*)
+  *         AHB3RSTR     OSPI1RST      LL_AHB3_GRP1_ForceReset\n (*)
+  *         AHB3RSTR     OSPI2RST      LL_AHB3_GRP1_ForceReset\n (*)
+  *         AHB3RSTR     IOMNGRRST     LL_AHB3_GRP1_ForceReset\n (*)
+  *         AHB3RSTR     OTFDEC1RST    LL_AHB3_GRP1_ForceReset\n (*)
+  *         AHB3RSTR     OTFDEC2RST    LL_AHB3_GRP1_ForceReset\n (*)
+  *         AHB3RSTR     GFXMMURST     LL_AHB3_GRP1_ForceReset\n (*)
+  *         AHB3RSTR     SDMMC1RST     LL_AHB3_GRP1_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI     (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU   (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->AHB3RSTR, Periphs);
+}
+
+/**
+  * @brief  Release AHB3 peripherals reset.
+  * @rmtoll AHB3RSTR     MDMARST       LL_AHB3_GRP1_ReleaseReset\n
+  *         AHB3RSTR     DMA2DRST      LL_AHB3_GRP1_ReleaseReset\n
+  *         AHB3RSTR     JPGDECRST     LL_AHB3_GRP1_ReleaseReset\n
+  *         AHB3RSTR     FMCRST        LL_AHB3_GRP1_ReleaseReset\n
+  *         AHB3RSTR     QSPIRST       LL_AHB3_GRP1_ReleaseReset\n
+  *         AHB3RSTR     OSPI1RST      LL_AHB3_GRP1_ReleaseReset\n (*)
+  *         AHB3RSTR     OSPI2RST      LL_AHB3_GRP1_ReleaseReset\n (*)
+  *         AHB3RSTR     IOMNGRRST     LL_AHB3_GRP1_ReleaseReset\n (*)
+  *         AHB3RSTR     OTFDEC1RST    LL_AHB3_GRP1_ReleaseReset\n (*)
+  *         AHB3RSTR     OTFDEC2RST    LL_AHB3_GRP1_ReleaseReset\n (*)
+  *         AHB3RSTR     GFXMMURST     LL_AHB3_GRP1_ReleaseReset\n (*)
+  *         AHB3RSTR     SDMMC1RST     LL_AHB3_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI     (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU   (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB3RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable AHB3 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB3LPENR    MDMALPEN      LL_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    DMA2DLPEN     LL_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    JPGDECLPEN    LL_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    FMCLPEN       LL_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    QSPILPEN      LL_AHB3_GRP1_EnableClockSleep\n  (*)
+  *         AHB3LPENR    OSPI1LPEN     LL_AHB3_GRP1_EnableClockSleep\n  (*)
+  *         AHB3LPENR    OSPI2LPEN     LL_AHB3_GRP1_EnableClockSleep\n  (*)
+  *         AHB3LPENR    IOMNGRLPEN    LL_AHB3_GRP1_EnableClockSleep\n  (*)
+  *         AHB3LPENR    OTFDEC1LPEN   LL_AHB3_GRP1_EnableClockSleep\n  (*)
+  *         AHB3LPENR    OTFDEC1LPEN   LL_AHB3_GRP1_EnableClockSleep\n  (*)
+  *         AHB3LPENR    GFXMMULPEN    LL_AHB3_GRP1_EnableClockSleep\n  (*)
+  *         AHB3LPENR    SDMMC1LPEN    LL_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    FLASHLPEN     LL_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    DTCM1LPEN     LL_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    DTCM2LPEN     LL_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    ITCMLPEN      LL_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    AXISRAMLPEN   LL_AHB3_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI     (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU   (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB3LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable AHB3 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB3LPENR    MDMALPEN      LL_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    DMA2DLPEN     LL_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    JPGDECLPEN    LL_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    FMCLPEN       LL_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    QSPILPEN      LL_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    OSPI1LPEN     LL_AHB3_GRP1_DisableClockSleep\n  (*)
+  *         AHB3LPENR    OSPI2LPEN     LL_AHB3_GRP1_DisableClockSleep\n  (*)
+  *         AHB3LPENR    IOMNGRLPEN    LL_AHB3_GRP1_DisableClockSleep\n  (*)
+  *         AHB3LPENR    OTFDEC1LPEN   LL_AHB3_GRP1_DisableClockSleep\n  (*)
+  *         AHB3LPENR    OTFDEC1LPEN   LL_AHB3_GRP1_DisableClockSleep\n  (*)
+  *         AHB3LPENR    GFXMMULPEN    LL_AHB3_GRP1_DisableClockSleep\n  (*)
+  *         AHB3LPENR    SDMMC1LPEN    LL_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    FLASHLPEN     LL_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    DTCM1LPEN     LL_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    DTCM2LPEN     LL_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    ITCMLPEN      LL_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    AXISRAMLPEN   LL_AHB3_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI     (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU   (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB3LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_AHB1 AHB1
+  * @{
+  */
+
+/**
+  * @brief  Enable AHB1 peripherals clock.
+  * @rmtoll AHB1ENR      DMA1EN        LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      DMA2EN        LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      ADC12EN       LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      ARTEN         LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      ETH1MACEN     LL_AHB1_GRP1_EnableClock\n (*)
+  *         AHB1ENR      ETH1TXEN      LL_AHB1_GRP1_EnableClock\n (*)
+  *         AHB1ENR      ETH1RXEN      LL_AHB1_GRP1_EnableClock\n (*)
+  *         AHB1ENR      USB1OTGHSEN   LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      USB1OTGHSULPIEN  LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      USB2OTGHSEN   LL_AHB1_GRP1_EnableClock\n  (*)
+  *         AHB1ENR      USB2OTGHSULPIEN  LL_AHB1_GRP1_EnableClock (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB1ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if AHB1 peripheral clock is enabled or not
+  * @rmtoll AHB1ENR      DMA1EN        LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      DMA2EN        LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      ADC12EN       LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      ARTEN         LL_AHB1_GRP1_IsEnabledClock\n (*)
+  *         AHB1ENR      CRCEN         LL_AHB1_GRP1_IsEnabledClock\n (*)
+  *         AHB1ENR      ETH1MACEN     LL_AHB1_GRP1_IsEnabledClock\n (*)
+  *         AHB1ENR      ETH1TXEN      LL_AHB1_GRP1_IsEnabledClock\n (*)
+  *         AHB1ENR      ETH1RXEN      LL_AHB1_GRP1_IsEnabledClock\n (*)
+  *         AHB1ENR      USB1OTGHSEN   LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      USB1OTGHSULPIEN  LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      USB2OTGHSEN   LL_AHB1_GRP1_IsEnabledClock\n  (*)
+  *         AHB1ENR      USB2OTGHSULPIEN  LL_AHB1_GRP1_IsEnabledClock (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable AHB1 peripherals clock.
+  * @rmtoll AHB1ENR      DMA1EN        LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      DMA2EN        LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      ADC12EN       LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      ARTEN         LL_AHB1_GRP1_DisableClock\n (*)
+  *         AHB1ENR      ETH1MACEN     LL_AHB1_GRP1_DisableClock\n (*)
+  *         AHB1ENR      ETH1TXEN      LL_AHB1_GRP1_DisableClock\n (*)
+  *         AHB1ENR      ETH1RXEN      LL_AHB1_GRP1_DisableClock\n (*)
+  *         AHB1ENR      USB1OTGHSEN   LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      USB1OTGHSULPIEN  LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      USB2OTGHSEN   LL_AHB1_GRP1_DisableClock\n  (*)
+  *         AHB1ENR      USB2OTGHSULPIEN  LL_AHB1_GRP1_DisableClock (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB1ENR, Periphs);
+}
+
+/**
+  * @brief  Force AHB1 peripherals reset.
+  * @rmtoll AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     ADC12RST      LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     ARTRST        LL_AHB1_GRP1_ForceReset\n (*)
+  *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ForceReset\n (*)
+  *         AHB1RSTR     ETH1MACRST    LL_AHB1_GRP1_ForceReset\n (*)
+  *         AHB1RSTR     USB1OTGHSRST  LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     USB2OTGHSRST  LL_AHB1_GRP1_ForceReset   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->AHB1RSTR, Periphs);
+}
+
+/**
+  * @brief  Release AHB1 peripherals reset.
+  * @rmtoll AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     ADC12RST      LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     ARTRST        LL_AHB1_GRP1_ReleaseReset\n (*)
+  *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ReleaseReset\n (*)
+  *         AHB1RSTR     ETH1MACRST    LL_AHB1_GRP1_ReleaseReset\n (*)
+  *         AHB1RSTR     USB1OTGHSRST  LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     USB2OTGHSRST  LL_AHB1_GRP1_ReleaseReset   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB1RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable AHB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB1LPENR    DMA1LPEN      LL_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    DMA2LPEN      LL_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    ADC12LPEN     LL_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    ARTLPEN       LL_AHB1_GRP1_EnableClockSleep\n (*)
+  *         AHB1LPENR    CRCLPEN       LL_AHB1_GRP1_EnableClockSleep\n (*)
+  *         AHB1LPENR    ETH1MACLPEN   LL_AHB1_GRP1_EnableClockSleep\n (*)
+  *         AHB1LPENR    ETH1TXLPEN    LL_AHB1_GRP1_EnableClockSleep\n (*)
+  *         AHB1LPENR    ETH1RXLPEN    LL_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    USB1OTGHSLPEN  LL_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    USB1OTGHSULPILPEN  LL_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    USB2OTGHSLPEN  LL_AHB1_GRP1_EnableClockSleep\n   (*)
+  *         AHB1LPENR    USB2OTGHSULPILPEN  LL_AHB1_GRP1_EnableClockSleep (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB1LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable AHB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB1LPENR    DMA1LPEN      LL_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    DMA2LPEN      LL_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    ADC12LPEN     LL_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    ARTLPEN       LL_AHB1_GRP1_DisableClockSleep\n (*)
+  *         AHB1LPENR    CRCLPEN       LL_AHB1_GRP1_DisableClockSleep\n (*)
+  *         AHB1LPENR    ETH1MACLPEN   LL_AHB1_GRP1_DisableClockSleep\n (*)
+  *         AHB1LPENR    ETH1TXLPEN    LL_AHB1_GRP1_DisableClockSleep\n (*)
+  *         AHB1LPENR    ETH1RXLPEN    LL_AHB1_GRP1_DisableClockSleep\n (*)
+  *         AHB1LPENR    USB1OTGHSLPEN  LL_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    USB1OTGHSULPILPEN  LL_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    USB2OTGHSLPEN  LL_AHB1_GRP1_DisableClockSleep\n   (*)
+  *         AHB1LPENR    USB2OTGHSULPILPEN  LL_AHB1_GRP1_DisableClockSleep (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB1LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_AHB2 AHB2
+  * @{
+  */
+
+/**
+  * @brief  Enable AHB2 peripherals clock.
+  * @rmtoll AHB2ENR      DCMIEN        LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      HSEMEN        LL_AHB2_GRP1_EnableClock\n (*)
+  *         AHB2ENR      CRYPEN        LL_AHB2_GRP1_EnableClock\n (*)
+  *         AHB2ENR      HASHEN        LL_AHB2_GRP1_EnableClock\n (*)
+  *         AHB2ENR      RNGEN         LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      SDMMC2EN      LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      BDMA1EN       LL_AHB2_GRP1_EnableClock\n (*)
+  *         AHB2ENR      D2SRAM1EN     LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      D2SRAM2EN     LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      D2SRAM3EN     LL_AHB2_GRP1_EnableClock   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1   (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB2ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if AHB2 peripheral clock is enabled or not
+  * @rmtoll AHB2ENR      DCMIEN        LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      HSEMEN        LL_AHB2_GRP1_IsEnabledClock\n (*)
+  *         AHB2ENR      CRYPEN        LL_AHB2_GRP1_IsEnabledClock\n (*)
+  *         AHB2ENR      HASHEN        LL_AHB2_GRP1_IsEnabledClock\n (*)
+  *         AHB2ENR      RNGEN         LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      SDMMC2EN      LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      BDMA1EN       LL_AHB2_GRP1_IsEnabledClock\n (*)
+  *         AHB2ENR      D2SRAM1EN     LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      D2SRAM2EN     LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      D2SRAM3EN     LL_AHB2_GRP1_IsEnabledClock   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEMEN (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1   (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable AHB2 peripherals clock.
+  * @rmtoll AHB2ENR      DCMIEN        LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      HSEMEN        LL_AHB2_GRP1_DisableClock\n (*)
+  *         AHB2ENR      CRYPEN        LL_AHB2_GRP1_DisableClock\n (*)
+  *         AHB2ENR      HASHEN        LL_AHB2_GRP1_DisableClock\n (*)
+  *         AHB2ENR      RNGEN         LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      SDMMC2EN      LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      BDMA1EN       LL_AHB2_GRP1_DisableClock\n (*)
+  *         AHB2ENR      D2SRAM1EN     LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      D2SRAM2EN     LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      D2SRAM3EN     LL_AHB2_GRP1_DisableClock   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEMEN (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1   (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB2ENR, Periphs);
+}
+
+/**
+  * @brief  Force AHB2 peripherals reset.
+  * @rmtoll AHB2RSTR     DCMIRST       LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR     HSEMRST       LL_AHB2_GRP1_ForceReset\n (*)
+  *         AHB2RSTR     CRYPRST       LL_AHB2_GRP1_ForceReset\n (*)
+  *         AHB2RSTR     HASHRST       LL_AHB2_GRP1_ForceReset\n (*)
+  *         AHB2RSTR     RNGRST        LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR     SDMMC2RST     LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR     BDMA1RST      LL_AHB2_GRP1_ForceReset   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->AHB2RSTR, Periphs);
+}
+
+/**
+  * @brief  Release AHB2 peripherals reset.
+  * @rmtoll AHB2RSTR     DCMIRST       LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR     HSEMRST       LL_AHB2_GRP1_ReleaseReset\n (*)
+  *         AHB2RSTR     CRYPRST       LL_AHB2_GRP1_ReleaseReset\n (*)
+  *         AHB2RSTR     HASHRST       LL_AHB2_GRP1_ReleaseReset\n (*)
+  *         AHB2RSTR     RNGRST        LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR     SDMMC2RST     LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR     BDMA1RST      LL_AHB2_GRP1_ReleaseReset   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB2RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable AHB2 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB2LPENR    DCMILPEN      LL_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    CRYPLPEN      LL_AHB2_GRP1_EnableClockSleep\n (*)
+  *         AHB2LPENR    HASHLPEN      LL_AHB2_GRP1_EnableClockSleep\n (*)
+  *         AHB2LPENR    RNGLPEN       LL_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    SDMMC2LPEN    LL_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    BDMA1LPEN     LL_AHB2_GRP1_EnableClockSleep\n (*)
+  *         AHB2LPENR    D2SRAM1LPEN   LL_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    D2SRAM2LPEN   LL_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    D2SRAM3LPEN   LL_AHB2_GRP1_EnableClockSleep   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1   (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB2LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable AHB2 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB2LPENR    DCMILPEN      LL_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    CRYPLPEN      LL_AHB2_GRP1_DisableClockSleep\n (*)
+  *         AHB2LPENR    HASHLPEN      LL_AHB2_GRP1_DisableClockSleep\n (*)
+  *         AHB2LPENR    RNGLPEN       LL_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    SDMMC2LPEN    LL_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    BDMA1LPEN     LL_AHB2_GRP1_DisableClockSleep\n (*)
+  *         AHB2LPENR    D2SRAM1LPEN   LL_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    D2SRAM2LPEN   LL_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    D2SRAM3LPEN   LL_AHB2_GRP1_DisableClockSleep   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB2LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_AHB4 AHB4
+  * @{
+  */
+
+/**
+  * @brief  Enable AHB4 peripherals clock.
+  * @rmtoll AHB4ENR      GPIOAEN       LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOBEN       LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOCEN       LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIODEN       LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOEEN       LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOFEN       LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOGEN       LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOHEN       LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOIEN       LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOJEN       LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOKEN       LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      CRCEN         LL_AHB4_GRP1_EnableClock\n (*)
+  *         AHB4ENR      BDMAEN        LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      ADC3EN        LL_AHB4_GRP1_EnableClock\n (*)
+  *         AHB4ENR      HSEMEN        LL_AHB4_GRP1_EnableClock\n (*)
+  *         AHB4ENR      BKPRAMEN      LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      SRAM4EN       LL_AHB4_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC   (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB4_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB4ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB4ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if AHB4 peripheral clock is enabled or not
+  * @rmtoll AHB4ENR      GPIOAEN       LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOBEN       LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOCEN       LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIODEN       LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOEEN       LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOFEN       LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOGEN       LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOHEN       LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOIEN       LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOJEN       LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOKEN       LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      CRCEN         LL_AHB4_GRP1_IsEnabledClock\n (*)
+  *         AHB4ENR      BDMAEN        LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      ADC3EN        LL_AHB4_GRP1_IsEnabledClock\n (*)
+  *         AHB4ENR      HSEMEN        LL_AHB4_GRP1_IsEnabledClock\n (*)
+  *         AHB4ENR      BKPRAMEN      LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      SRAM4EN       LL_AHB4_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->AHB4ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable AHB4 peripherals clock.
+  * @rmtoll AHB4ENR      GPIOAEN       LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOBEN       LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOCEN       LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIODEN       LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOEEN       LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOFEN       LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOGEN       LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOHEN       LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOIEN       LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOJEN       LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOKEN       LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      CRCEN         LL_AHB4_GRP1_DisableClock\n (*)
+  *         AHB4ENR      BDMAEN        LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      ADC3EN        LL_AHB4_GRP1_DisableClock\n (*)
+  *         AHB4ENR      HSEMEN        LL_AHB4_GRP1_DisableClock\n (*)
+  *         AHB4ENR      BKPRAMEN      LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      SRAM4EN       LL_AHB4_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB4_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB4ENR, Periphs);
+}
+
+/**
+  * @brief  Force AHB4 peripherals reset.
+  * @rmtoll AHB4RSTR     GPIOARST      LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTR     GPIOBRST      LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTR     GPIOCRST      LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTR     GPIODRST      LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTR     GPIOERST      LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTR     GPIOFRST      LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTR     GPIOGRST      LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTR     GPIOHRST      LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTR     GPIOIRST      LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTR     GPIOJRST      LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTR     GPIOKRST      LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTR     CRCRST        LL_AHB4_GRP1_ForceReset\n (*)
+  *         AHB4RSTR     BDMARST       LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTR     ADC3RST       LL_AHB4_GRP1_ForceReset\n (*)
+  *         AHB4RSTR     HSEMRST       LL_AHB4_GRP1_ForceReset   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB4_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->AHB4RSTR, Periphs);
+}
+
+/**
+  * @brief  Release AHB4 peripherals reset.
+  * @rmtoll AHB4RSTR     GPIOARST      LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTR     GPIOBRST      LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTR     GPIOCRST      LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTR     GPIODRST      LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTR     GPIOERST      LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTR     GPIOFRST      LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTR     GPIOGRST      LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTR     GPIOHRST      LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTR     GPIOIRST      LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTR     GPIOJRST      LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTR     GPIOKRST      LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTR     CRCRST        LL_AHB4_GRP1_ReleaseReset\n (*)
+  *         AHB4RSTR     BDMARST       LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTR     ADC3RST       LL_AHB4_GRP1_ReleaseReset\n (*)
+  *         AHB4RSTR     HSEMRST       LL_AHB4_GRP1_ReleaseReset   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB4_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB4RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable AHB4 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB4LPENR    GPIOALPEN     LL_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOBLPEN     LL_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOCLPEN     LL_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIODLPEN     LL_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOELPEN     LL_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOFLPEN     LL_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOGLPEN     LL_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOHLPEN     LL_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOILPEN     LL_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOJLPEN     LL_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOKLPEN     LL_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    CRCLPEN       LL_AHB4_GRP1_EnableClockSleep\n (*)
+  *         AHB4LPENR    BDMALPEN      LL_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    ADC3LPEN      LL_AHB4_GRP1_EnableClockSleep\n (*)
+  *         AHB4LPENR    BKPRAMLPEN    LL_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    SRAM4LPEN     LL_AHB4_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB4_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB4LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB4LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable AHB4 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB4LPENR    GPIOALPEN     LL_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOBLPEN     LL_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOCLPEN     LL_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIODLPEN     LL_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOELPEN     LL_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOFLPEN     LL_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOGLPEN     LL_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOHLPEN     LL_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOILPEN     LL_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOJLPEN     LL_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOKLPEN     LL_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    CRCLPEN       LL_AHB4_GRP1_DisableClockSleep\n (*)
+  *         AHB4LPENR    BDMALPEN      LL_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    ADC3LPEN      LL_AHB4_GRP1_DisableClockSleep\n (*)
+  *         AHB4LPENR    BKPRAMLPEN    LL_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    SRAM4LPEN   LL_AHB4_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB4_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB4LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_APB3 APB3
+  * @{
+  */
+
+/**
+  * @brief  Enable APB3 peripherals clock.
+  * @rmtoll APB3ENR      LTDCEN        LL_APB3_GRP1_EnableClock\n (*)
+  *         APB3ENR      DSIEN         LL_APB3_GRP1_EnableClock\n (*)
+  *         APB3ENR      WWDG1EN       LL_APB3_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB3_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB3ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB3ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if APB3 peripheral clock is enabled or not
+  * @rmtoll APB3ENR      LTDCEN        LL_APB3_GRP1_IsEnabledClock\n (*)
+  *         APB3ENR      DSIEN         LL_APB3_GRP1_IsEnabledClock\n (*)
+  *         APB3ENR      WWDG1EN       LL_APB3_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->APB3ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable APB3 peripherals clock.
+  * @rmtoll APB3ENR      LTDCEN        LL_APB3_GRP1_DisableClock\n
+  *         APB3ENR      DSIEN         LL_APB3_GRP1_DisableClock\n
+  *         APB3ENR      WWDG1EN       LL_APB3_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB3_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB3ENR, Periphs);
+}
+
+/**
+  * @brief  Force APB3 peripherals reset.
+  * @rmtoll APB3RSTR     LTDCRST       LL_APB3_GRP1_ForceReset\n (*)
+  *         APB3RSTR     DSIRST        LL_APB3_GRP1_ForceReset   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB3_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->APB3RSTR, Periphs);
+}
+
+/**
+  * @brief  Release APB3 peripherals reset.
+  * @rmtoll APB3RSTR     LTDCRST       LL_APB3_GRP1_ReleaseReset\n
+  *         APB3RSTR     DSIRST        LL_APB3_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB3_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB3RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable APB3 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB3LPENR    LTDCLPEN      LL_APB3_GRP1_EnableClockSleep\n (*)
+  *         APB3LPENR    DSILPEN       LL_APB3_GRP1_EnableClockSleep\n (*)
+  *         APB3LPENR    WWDG1LPEN     LL_APB3_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB3_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB3LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB3LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable APB3 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB3LPENR    LTDCLPEN      LL_APB3_GRP1_DisableClockSleep\n (*)
+  *         APB3LPENR    DSILPEN       LL_APB3_GRP1_DisableClockSleep\n (*)
+  *         APB3LPENR    WWDG1LPEN     LL_APB3_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB3_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB3LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_APB1 APB1
+  * @{
+  */
+
+/**
+  * @brief  Enable APB1 peripherals clock.
+  * @rmtoll APB1LENR     TIM2EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM3EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM4EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM5EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM6EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM7EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM12EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM13EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM14EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     LPTIM1EN      LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     WWDG2EN       LL_APB1_GRP1_EnableClock\n (*)
+  *         APB1LENR     SPI2EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     SPI3EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     SPDIFRXEN     LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     USART2EN      LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     USART3EN      LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     UART4EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     UART5EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     I2C1EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     I2C2EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     I2C3EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     CECEN         LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     DAC12EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     UART7EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     UART8EN       LL_APB1_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB1LENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB1LENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if APB1 peripheral clock is enabled or not
+  * @rmtoll APB1LENR     TIM2EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM3EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM4EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM5EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM6EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM7EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM12EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM13EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM14EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     LPTIM1EN      LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     WWDG2EN       LL_APB1_GRP1_IsEnabledClock\n (*)
+  *         APB1LENR     SPI2EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     SPI3EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     SPDIFRXEN     LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     USART2EN      LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     USART3EN      LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     UART4EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     UART5EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     I2C1EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     I2C2EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     I2C3EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     CECEN         LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     DAC12EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     UART7EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     UART8EN       LL_APB1_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->APB1LENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable APB1 peripherals clock.
+  * @rmtoll APB1LENR     TIM2EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM3EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM4EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM5EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM6EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM7EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM12EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM13EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM14EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     LPTIM1EN      LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     WWDG2EN       LL_APB1_GRP1_DisableClock\n (*)
+  *         APB1LENR     SPI2EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     SPI3EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     SPDIFRXEN     LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     USART2EN      LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     USART3EN      LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     UART4EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     UART5EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     I2C1EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     I2C2EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     I2C3EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     CECEN         LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     DAC12EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     UART7EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     UART8EN       LL_APB1_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB1LENR, Periphs);
+}
+
+/**
+  * @brief  Force APB1 peripherals reset.
+  * @rmtoll APB1LRSTR    TIM2RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    TIM3RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    TIM4RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    TIM5RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    TIM6RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    TIM7RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    TIM12RST      LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    TIM13RST      LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    TIM14RST      LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    LPTIM1RST     LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    SPI2RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    SPI3RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    SPDIFRXRST    LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    USART2RST     LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    USART3RST     LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    UART4RST      LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    UART5RST      LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    I2C1RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    I2C2RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    I2C3RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    CECRST        LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    DAC12RST      LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    UART7RST      LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    UART8RST      LL_APB1_GRP1_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->APB1LRSTR, Periphs);
+}
+
+/**
+  * @brief  Release APB1 peripherals reset.
+  * @rmtoll APB1LRSTR    TIM2RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    TIM3RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    TIM4RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    TIM5RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    TIM6RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    TIM7RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    TIM12RST      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    TIM13RST      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    TIM14RST      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    LPTIM1RST     LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    SPI2RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    SPI3RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    SPDIFRXRST    LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    USART2RST     LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    USART3RST     LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    UART4RST      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    UART5RST      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    I2C1RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    I2C2RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    I2C3RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    CECRST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    DAC12RST      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    UART7RST      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    UART8RST      LL_APB1_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB1LRSTR, Periphs);
+}
+
+/**
+  * @brief  Enable APB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB1LLPENR   TIM2LPEN      LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM3LPEN      LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM4LPEN      LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM5LPEN      LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM6LPEN      LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM7LPEN      LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM12LPEN     LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM13LPEN     LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM14LPEN     LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   LPTIM1LPEN    LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   WWDG2LPEN     LL_APB1_GRP1_EnableClockSleep\n (*)
+  *         APB1LLPENR   SPI2LPEN      LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   SPI3LPEN      LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   SPDIFRXLPEN   LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   USART2LPEN    LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   USART3LPEN    LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   UART4LPEN     LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   UART5LPEN     LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   I2C1LPEN      LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   I2C2LPEN      LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   I2C3LPEN      LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   CECLPEN       LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   DAC12LPEN     LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   UART7LPEN     LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   UART8LPEN     LL_APB1_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB1LLPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB1LLPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable APB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB1LLPENR   TIM2LPEN      LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM3LPEN      LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM4LPEN      LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM5LPEN      LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM6LPEN      LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM7LPEN      LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM12LPEN     LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM13LPEN     LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM14LPEN     LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   LPTIM1LPEN    LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   WWDG2LPEN     LL_APB1_GRP1_DisableClockSleep\n (*)
+  *         APB1LLPENR   SPI2LPEN      LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   SPI3LPEN      LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   SPDIFRXLPEN   LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   USART2LPEN    LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   USART3LPEN    LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   UART4LPEN     LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   UART5LPEN     LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   I2C1LPEN      LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   I2C2LPEN      LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   I2C3LPEN      LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   CECLPEN       LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   DAC12LPEN     LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   UART7LPEN     LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   UART8LPEN     LL_APB1_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB1LLPENR, Periphs);
+}
+
+/**
+  * @brief  Enable APB1 peripherals clock.
+  * @rmtoll APB1HENR     CRSEN         LL_APB1_GRP2_EnableClock\n
+  *         APB1HENR     SWPMIEN       LL_APB1_GRP2_EnableClock\n
+  *         APB1HENR     OPAMPEN       LL_APB1_GRP2_EnableClock\n
+  *         APB1HENR     MDIOSEN       LL_APB1_GRP2_EnableClock\n
+  *         APB1HENR     FDCANEN       LL_APB1_GRP2_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB1HENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB1HENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if APB1 peripheral clock is enabled or not
+  * @rmtoll APB1HENR     CRSEN         LL_APB1_GRP2_IsEnabledClock\n
+  *         APB1HENR     SWPMIEN       LL_APB1_GRP2_IsEnabledClock\n
+  *         APB1HENR     OPAMPEN       LL_APB1_GRP2_IsEnabledClock\n
+  *         APB1HENR     MDIOSEN       LL_APB1_GRP2_IsEnabledClock\n
+  *         APB1HENR     FDCANEN       LL_APB1_GRP2_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->APB1HENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable APB1 peripherals clock.
+  * @rmtoll APB1HENR     CRSEN         LL_APB1_GRP2_DisableClock\n
+  *         APB1HENR     SWPMIEN       LL_APB1_GRP2_DisableClock\n
+  *         APB1HENR     OPAMPEN       LL_APB1_GRP2_DisableClock\n
+  *         APB1HENR     MDIOSEN       LL_APB1_GRP2_DisableClock\n
+  *         APB1HENR     FDCANEN       LL_APB1_GRP2_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB1HENR, Periphs);
+}
+
+/**
+  * @brief  Force APB1 peripherals reset.
+  * @rmtoll APB1HRSTR    CRSRST        LL_APB1_GRP2_ForceReset\n
+  *         APB1HRSTR    SWPMIRST      LL_APB1_GRP2_ForceReset\n
+  *         APB1HRSTR    OPAMPRST      LL_APB1_GRP2_ForceReset\n
+  *         APB1HRSTR    MDIOSRST      LL_APB1_GRP2_ForceReset\n
+  *         APB1HRSTR    FDCANRST      LL_APB1_GRP2_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->APB1HRSTR, Periphs);
+}
+
+/**
+  * @brief  Release APB1 peripherals reset.
+  * @rmtoll APB1HRSTR    CRSRST        LL_APB1_GRP2_ReleaseReset\n
+  *         APB1HRSTR    SWPMIRST      LL_APB1_GRP2_ReleaseReset\n
+  *         APB1HRSTR    OPAMPRST      LL_APB1_GRP2_ReleaseReset\n
+  *         APB1HRSTR    MDIOSRST      LL_APB1_GRP2_ReleaseReset\n
+  *         APB1HRSTR    FDCANRST      LL_APB1_GRP2_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB1HRSTR, Periphs);
+}
+
+/**
+  * @brief  Enable APB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB1HLPENR   CRSLPEN       LL_APB1_GRP2_EnableClockSleep\n
+  *         APB1HLPENR   SWPMILPEN     LL_APB1_GRP2_EnableClockSleep\n
+  *         APB1HLPENR   OPAMPLPEN     LL_APB1_GRP2_EnableClockSleep\n
+  *         APB1HLPENR   MDIOSLPEN     LL_APB1_GRP2_EnableClockSleep\n
+  *         APB1HLPENR   FDCANLPEN     LL_APB1_GRP2_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP2_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB1HLPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB1HLPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable APB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB1HLPENR   CRSLPEN       LL_APB1_GRP2_DisableClockSleep\n
+  *         APB1HLPENR   SWPMILPEN     LL_APB1_GRP2_DisableClockSleep\n
+  *         APB1HLPENR   OPAMPLPEN     LL_APB1_GRP2_DisableClockSleep\n
+  *         APB1HLPENR   MDIOSLPEN     LL_APB1_GRP2_DisableClockSleep\n
+  *         APB1HLPENR   FDCANLPEN     LL_APB1_GRP2_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP2_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB1HLPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_APB2 APB2
+  * @{
+  */
+
+/**
+  * @brief  Enable APB2 peripherals clock.
+  * @rmtoll APB2ENR      TIM1EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM8EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      USART1EN      LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      USART6EN      LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      UART9EN       LL_APB2_GRP1_EnableClock\n (*)
+  *         APB2ENR      USART10EN     LL_APB2_GRP1_EnableClock\n (*)
+  *         APB2ENR      SPI1EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SPI4EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM15EN       LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM16EN       LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM17EN       LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SPI5EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SAI1EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SAI2EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SAI3EN        LL_APB2_GRP1_EnableClock\n (*)
+  *         APB2ENR      DFSDM1EN      LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      HRTIMEN       LL_APB2_GRP1_EnableClock   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB2ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if APB2 peripheral clock is enabled or not
+  * @rmtoll APB2ENR      TIM1EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM8EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      USART1EN      LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      USART6EN      LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      UART9EN       LL_APB2_GRP1_IsEnabledClock\n (*)
+  *         APB2ENR      USART10EN     LL_APB2_GRP1_IsEnabledClock\n (*)
+  *         APB2ENR      SPI1EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SPI4EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM15EN       LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM16EN       LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM17EN       LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SPI5EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SAI1EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SAI2EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SAI3EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      DFSDM1EN      LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      HRTIMEN       LL_APB2_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable APB2 peripherals clock.
+  * @rmtoll APB2ENR      TIM1EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM8EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      USART1EN      LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      USART6EN      LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      UART9EN       LL_APB2_GRP1_DisableClock\n (*)
+  *         APB2ENR      USART10EN     LL_APB2_GRP1_DisableClock\n (*)
+  *         APB2ENR      SPI1EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SPI4EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM15EN       LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM16EN       LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM17EN       LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SPI5EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SAI1EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SAI2EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SAI3EN        LL_APB2_GRP1_DisableClock\n (*)
+  *         APB2ENR      DFSDM1EN      LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      HRTIMEN       LL_APB2_GRP1_DisableClock   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB2ENR, Periphs);
+}
+
+/**
+  * @brief  Force APB2 peripherals reset.
+  * @rmtoll APB2RSTR     TIM1RST       LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     TIM8RST       LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     USART1RST     LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     USART6RST     LL_APB2_GRP1_ForceReset\n
+  *         APB2ENR      UART9RST      LL_APB2_GRP1_ForceReset\n (*)
+  *         APB2ENR      USART10RST    LL_APB2_GRP1_ForceReset\n (*)
+  *         APB2RSTR     SPI1RST       LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     SPI4RST       LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     TIM15RST      LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     TIM16RST      LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     TIM17RST      LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     SPI5RST       LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     SAI1RST       LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     SAI2RST       LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     SAI3RST       LL_APB2_GRP1_ForceReset\n (*)
+  *         APB2RSTR     DFSDM1RST     LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     HRTIMRST      LL_APB2_GRP1_ForceReset   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3   (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM  (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->APB2RSTR, Periphs);
+}
+
+/**
+  * @brief  Release APB2 peripherals reset.
+  * @rmtoll APB2RSTR     TIM1RST       LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     TIM8RST       LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     USART1RST     LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     USART6RST     LL_APB2_GRP1_ReleaseReset\n
+  *         APB2ENR      UART9RST      LL_APB2_GRP1_ReleaseReset\n (*)
+  *         APB2ENR      USART10RST    LL_APB2_GRP1_ReleaseReset\n (*)
+  *         APB2RSTR     SPI1RST       LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     SPI4RST       LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     TIM15RST      LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     TIM16RST      LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     TIM17RST      LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     SPI5RST       LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     SAI1RST       LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     SAI2RST       LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     SAI3RST       LL_APB2_GRP1_ReleaseReset\n (*)
+  *         APB2RSTR     DFSDM1RST     LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     HRTIMRST      LL_APB2_GRP1_ReleaseReset   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3   (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM  (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB2RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable APB2 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB2LPENR    TIM1LPEN      LL_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    TIM8LPEN      LL_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    USART1LPEN    LL_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    USART6LPEN    LL_APB2_GRP1_EnableClockSleep\n
+  *         APB2ENR      UART9LPEN     LL_APB2_GRP1_EnableClockSleep\n (*)
+  *         APB2ENR      USART10LPEN   LL_APB2_GRP1_EnableClockSleep\n (*)
+  *         APB2LPENR    SPI1LPEN      LL_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SPI4LPEN      LL_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    TIM15LPEN     LL_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    TIM16LPEN     LL_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    TIM17LPEN     LL_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SPI5LPEN      LL_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SAI1LPEN      LL_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SAI2LPEN      LL_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SAI3LPEN      LL_APB2_GRP1_EnableClockSleep\n (*)
+  *         APB2LPENR    DFSDM1LPEN    LL_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    HRTIMLPEN     LL_APB2_GRP1_EnableClockSleep   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB2LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB2LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable APB2 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB2LPENR    TIM1LPEN      LL_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    TIM8LPEN      LL_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    USART1LPEN    LL_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    USART6LPEN    LL_APB2_GRP1_DisableClockSleep\n
+  *         APB2ENR      UART9LPEN     LL_APB2_GRP1_DisableClockSleep\n (*)
+  *         APB2ENR      USART10LPEN   LL_APB2_GRP1_DisableClockSleep\n (*)
+  *         APB2LPENR    SPI1LPEN      LL_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SPI4LPEN      LL_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    TIM15LPEN     LL_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    TIM16LPEN     LL_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    TIM17LPEN     LL_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SPI5LPEN      LL_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SAI1LPEN      LL_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SAI2LPEN      LL_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SAI3LPEN      LL_APB2_GRP1_DisableClockSleep\n (*)
+  *         APB2LPENR    DFSDM1LPEN    LL_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    HRTIMLPEN     LL_APB2_GRP1_DisableClockSleep   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB2LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_APB4 APB4
+  * @{
+  */
+
+/**
+  * @brief  Enable APB4 peripherals clock.
+  * @rmtoll APB4ENR      SYSCFGEN      LL_APB4_GRP1_EnableClock\n
+  *         APB4ENR      LPUART1EN     LL_APB4_GRP1_EnableClock\n
+  *         APB4ENR      SPI6EN        LL_APB4_GRP1_EnableClock\n
+  *         APB4ENR      I2C4EN        LL_APB4_GRP1_EnableClock\n
+  *         APB4ENR      LPTIM2EN      LL_APB4_GRP1_EnableClock\n
+  *         APB4ENR      LPTIM3EN      LL_APB4_GRP1_EnableClock\n
+  *         APB4ENR      LPTIM4EN      LL_APB4_GRP1_EnableClock\n  (*)
+  *         APB4ENR      LPTIM5EN      LL_APB4_GRP1_EnableClock\n  (*)
+  *         APB4ENR      DAC2EN        LL_APB4_GRP1_EnableClock\n  (*)
+  *         APB4ENR      COMP12EN      LL_APB4_GRP1_EnableClock\n
+  *         APB4ENR      VREFEN        LL_APB4_GRP1_EnableClock\n
+  *         APB4ENR      RTCAPBEN      LL_APB4_GRP1_EnableClock\n
+  *         APB4ENR      SAI4EN        LL_APB4_GRP1_EnableClock\n  (*)
+  *         APB4ENR      DTSEN         LL_APB4_GRP1_EnableClock\n  (*)
+  *         APB4ENR      DFSDM2EN      LL_APB4_GRP1_EnableClock    (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DAC2   (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB4_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB4ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB4ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if APB4 peripheral clock is enabled or not
+  * @rmtoll APB4ENR      SYSCFGEN      LL_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      LPUART1EN     LL_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      SPI6EN        LL_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      I2C4EN        LL_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      LPTIM2EN      LL_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      LPTIM3EN      LL_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      LPTIM4EN      LL_APB4_GRP1_IsEnabledClock\n (*)
+  *         APB4ENR      LPTIM5EN      LL_APB4_GRP1_IsEnabledClock\n (*)
+  *         APB4ENR      DAC2EN        LL_APB4_GRP1_IsEnabledClock\n (*)
+  *         APB4ENR      COMP12EN      LL_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      VREFEN        LL_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      RTCAPBEN      LL_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      SAI4EN        LL_APB4_GRP1_IsEnabledClock\n (*)
+  *         APB4ENR      DTSEN         LL_APB4_GRP1_IsEnabledClock\n (*)
+  *         APB4ENR      DFSDM2EN      LL_APB4_GRP1_IsEnabledClock   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DAC2   (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_APB4_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->APB4ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable APB4 peripherals clock.
+  * @rmtoll APB4ENR      SYSCFGEN      LL_APB4_GRP1_DisableClock\n
+  *         APB4ENR      LPUART1EN     LL_APB4_GRP1_DisableClock\n
+  *         APB4ENR      SPI6EN        LL_APB4_GRP1_DisableClock\n
+  *         APB4ENR      I2C4EN        LL_APB4_GRP1_DisableClock\n
+  *         APB4ENR      LPTIM2EN      LL_APB4_GRP1_DisableClock\n
+  *         APB4ENR      LPTIM3EN      LL_APB4_GRP1_DisableClock\n
+  *         APB4ENR      LPTIM4EN      LL_APB4_GRP1_DisableClock\n  (*)
+  *         APB4ENR      LPTIM5EN      LL_APB4_GRP1_DisableClock\n  (*)
+  *         APB4ENR      DAC2EN        LL_APB4_GRP1_DisableClock\n  (*)
+  *         APB4ENR      COMP12EN      LL_APB4_GRP1_DisableClock\n
+  *         APB4ENR      VREFEN        LL_APB4_GRP1_DisableClock\n
+  *         APB4ENR      RTCAPBEN      LL_APB4_GRP1_DisableClock\n
+  *         APB4ENR      SAI4EN        LL_APB4_GRP1_DisableClock\n  (*)
+  *         APB4ENR      DTSEN         LL_APB4_GRP1_DisableClock\n  (*)
+  *         APB4ENR      DFSDM2EN      LL_APB4_GRP1_DisableClock    (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DAC2   (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB4_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB4ENR, Periphs);
+}
+
+/**
+  * @brief  Force APB4 peripherals reset.
+  * @rmtoll APB4RSTR     SYSCFGRST     LL_APB4_GRP1_ForceReset\n
+  *         APB4RSTR     LPUART1RST    LL_APB4_GRP1_ForceReset\n
+  *         APB4RSTR     SPI6RST       LL_APB4_GRP1_ForceReset\n
+  *         APB4RSTR     I2C4RST       LL_APB4_GRP1_ForceReset\n
+  *         APB4RSTR     LPTIM2RST     LL_APB4_GRP1_ForceReset\n
+  *         APB4RSTR     LPTIM3RST     LL_APB4_GRP1_ForceReset\n
+  *         APB4RSTR     LPTIM4RST     LL_APB4_GRP1_ForceReset\n  (*)
+  *         APB4RSTR     LPTIM5RST     LL_APB4_GRP1_ForceReset\n  (*)
+  *         APB4RSTR     DAC2EN        LL_APB4_GRP1_ForceReset\n  (*)
+  *         APB4RSTR     COMP12RST     LL_APB4_GRP1_ForceReset\n
+  *         APB4RSTR     VREFRST       LL_APB4_GRP1_ForceReset\n
+  *         APB4RSTR     SAI4RST       LL_APB4_GRP1_ForceReset\n  (*)
+  *         APB4RSTR     DTSRST        LL_APB4_GRP1_ForceReset\n  (*)
+  *         APB4RSTR      DFSDM2RST    LL_APB4_GRP1_ForceReset    (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DAC2   (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB4_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->APB4RSTR, Periphs);
+}
+
+/**
+  * @brief  Release APB4 peripherals reset.
+  * @rmtoll APB4RSTR     SYSCFGRST     LL_APB4_GRP1_ReleaseReset\n
+  *         APB4RSTR     LPUART1RST    LL_APB4_GRP1_ReleaseReset\n
+  *         APB4RSTR     SPI6RST       LL_APB4_GRP1_ReleaseReset\n
+  *         APB4RSTR     I2C4RST       LL_APB4_GRP1_ReleaseReset\n
+  *         APB4RSTR     LPTIM2RST     LL_APB4_GRP1_ReleaseReset\n
+  *         APB4RSTR     LPTIM3RST     LL_APB4_GRP1_ReleaseReset\n
+  *         APB4RSTR     LPTIM4RST     LL_APB4_GRP1_ReleaseReset\n  (*)
+  *         APB4RSTR     LPTIM5RST     LL_APB4_GRP1_ReleaseReset\n  (*)
+  *         APB4RSTR     DAC2RST       LL_APB4_GRP1_ReleaseReset\n  (*)
+  *         APB4RSTR     COMP12RST     LL_APB4_GRP1_ReleaseReset\n
+  *         APB4RSTR     VREFRST       LL_APB4_GRP1_ReleaseReset\n
+  *         APB4RSTR     SAI4RST       LL_APB4_GRP1_ReleaseReset\n
+  *         APB4RSTR     DTSRST        LL_APB4_GRP1_ReleaseReset\n  (*)
+  *         APB4RSTR     DFSDM2RST     LL_APB4_GRP1_ReleaseReset    (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DAC2   (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB4_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB4RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable APB4 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB4LPENR    SYSCFGLPEN    LL_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    LPUART1LPEN   LL_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    SPI6LPEN      LL_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    I2C4LPEN      LL_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    LPTIM2LPEN    LL_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    LPTIM3LPEN    LL_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    LPTIM4LPEN    LL_APB4_GRP1_EnableClockSleep\n (*)
+  *         APB4LPENR    LPTIM5LPEN    LL_APB4_GRP1_EnableClockSleep\n (*)
+  *         APB4LPENR    DAC2LPEN      LL_APB4_GRP1_EnableClockSleep\n (*)
+  *         APB4LPENR    COMP12LPEN    LL_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    VREFLPEN      LL_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    RTCAPBLPEN    LL_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    SAI4LPEN      LL_APB4_GRP1_EnableClockSleep\n (*)
+  *         APB4LPENR    DTSLPEN       LL_APB4_GRP1_EnableClockSleep\n (*)
+  *         APB4LPENR    DFSDM2LPEN    LL_APB4_GRP1_EnableClockSleep   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DAC2   (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB4_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB4LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB4LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable APB4 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB4LPENR    SYSCFGLPEN    LL_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    LPUART1LPEN   LL_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    SPI6LPEN      LL_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    I2C4LPEN      LL_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    LPTIM2LPEN    LL_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    LPTIM3LPEN    LL_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    LPTIM4LPEN    LL_APB4_GRP1_DisableClockSleep\n (*)
+  *         APB4LPENR    LPTIM5LPEN    LL_APB4_GRP1_DisableClockSleep\n (*)
+  *         APB4LPENR    DAC2LPEN      LL_APB4_GRP1_DisableClockSleep\n (*)
+  *         APB4LPENR    COMP12LPEN    LL_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    VREFLPEN      LL_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    RTCAPBLPEN    LL_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    SAI4LPEN      LL_APB4_GRP1_DisableClockSleep\n (*)
+  *         APB4LPENR    DTSLPEN       LL_APB4_GRP1_DisableClockSleep\n (*)
+  *         APB4LPENR    DFSDM2LPEN    LL_APB4_GRP1_DisableClockSleep   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DAC2   (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB4_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB4LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_CLKAM
+  * @{
+  */
+
+/**
+  * @brief  Enable peripherals clock for CLKAM Mode.
+  * @rmtoll D3AMR / SRDAMR         BDMA          LL_CLKAM_Enable\n
+  *         D3AMR / SRDAMR         LPUART1       LL_CLKAM_Enable\n
+  *         D3AMR / SRDAMR         SPI6          LL_CLKAM_Enable\n
+  *         D3AMR / SRDAMR         I2C4          LL_CLKAM_Enable\n
+  *         D3AMR / SRDAMR         LPTIM2        LL_CLKAM_Enable\n
+  *         D3AMR / SRDAMR         LPTIM3        LL_CLKAM_Enable\n
+  *         D3AMR / SRDAMR         LPTIM4        LL_CLKAM_Enable\n  (*)
+  *         D3AMR / SRDAMR         LPTIM5        LL_CLKAM_Enable\n  (*)
+  *         D3AMR / SRDAMR         DAC2          LL_CLKAM_Enable\n  (*)
+  *         D3AMR / SRDAMR         COMP12        LL_CLKAM_Enable\n
+  *         D3AMR / SRDAMR         VREF          LL_CLKAM_Enable\n
+  *         D3AMR / SRDAMR         RTC           LL_CLKAM_Enable\n
+  *         D3AMR / SRDAMR         CRC           LL_CLKAM_Enable\n
+  *         D3AMR / SRDAMR         SAI4          LL_CLKAM_Enable\n  (*)
+  *         D3AMR / SRDAMR         ADC3          LL_CLKAM_Enable\n  (*)
+  *         D3AMR / SRDAMR         DTS           LL_CLKAM_Enable\n  (*)
+  *         D3AMR / SRDAMR         DFSDM2        LL_CLKAM_Enable\n  (*)
+  *         D3AMR / SRDAMR         BKPRAM        LL_CLKAM_Enable\n
+  *         D3AMR / SRDAMR         SRAM4         LL_CLKAM_Enable
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_CLKAM_PERIPH_BDMA
+  *         @arg @ref LL_CLKAM_PERIPH_LPUART1
+  *         @arg @ref LL_CLKAM_PERIPH_SPI6
+  *         @arg @ref LL_CLKAM_PERIPH_I2C4
+  *         @arg @ref LL_CLKAM_PERIPH_LPTIM2
+  *         @arg @ref LL_CLKAM_PERIPH_LPTIM3
+  *         @arg @ref LL_CLKAM_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_CLKAM_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_CLKAM_PERIPH_DAC2   (*)
+  *         @arg @ref LL_CLKAM_PERIPH_COMP12
+  *         @arg @ref LL_CLKAM_PERIPH_VREF
+  *         @arg @ref LL_CLKAM_PERIPH_RTC
+  *         @arg @ref LL_CLKAM_PERIPH_CRC
+  *         @arg @ref LL_CLKAM_PERIPH_SAI4   (*)
+  *         @arg @ref LL_CLKAM_PERIPH_ADC3   (*)
+  *         @arg @ref LL_CLKAM_PERIPH_DTS    (*)
+  *         @arg @ref LL_CLKAM_PERIPH_DFSDM2 (*)
+  *         @arg @ref LL_CLKAM_PERIPH_BKPRAM
+  *         @arg @ref LL_CLKAM_PERIPH_SRAM4
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_CLKAM_Enable(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+
+#if defined(RCC_D3AMR_BDMAAMEN)
+  SET_BIT(RCC->D3AMR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->D3AMR, Periphs);
+#else
+  SET_BIT(RCC->SRDAMR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->SRDAMR, Periphs);
+#endif /* RCC_D3AMR_BDMAAMEN */
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable peripherals clock for CLKAM Mode.
+  * @rmtoll D3AMR / SRDAMR        BDMA          LL_CLKAM_Disable\n
+  *         D3AMR / SRDAMR        LPUART1       LL_CLKAM_Disable\n
+  *         D3AMR / SRDAMR        SPI6          LL_CLKAM_Disable\n
+  *         D3AMR / SRDAMR        I2C4          LL_CLKAM_Disable\n
+  *         D3AMR / SRDAMR        LPTIM2        LL_CLKAM_Disable\n
+  *         D3AMR / SRDAMR        LPTIM3        LL_CLKAM_Disable\n
+  *         D3AMR / SRDAMR        LPTIM4        LL_CLKAM_Disable\n (*)
+  *         D3AMR / SRDAMR        LPTIM5        LL_CLKAM_Disable\n (*)
+  *         D3AMR / SRDAMR        DAC2          LL_CLKAM_Disable\n (*)
+  *         D3AMR / SRDAMR        COMP12        LL_CLKAM_Disable\n
+  *         D3AMR / SRDAMR        VREF          LL_CLKAM_Disable\n
+  *         D3AMR / SRDAMR        RTC           LL_CLKAM_Disable\n
+  *         D3AMR / SRDAMR        CRC           LL_CLKAM_Disable\n
+  *         D3AMR / SRDAMR        SAI4          LL_CLKAM_Disable\n (*)
+  *         D3AMR / SRDAMR        ADC3          LL_CLKAM_Disable\n (*)
+  *         D3AMR / SRDAMR        DTS           LL_CLKAM_Disable\n (*)
+  *         D3AMR / SRDAMR        DFSDM2        LL_CLKAM_Disable\n (*)
+  *         D3AMR / SRDAMR        BKPRAM        LL_CLKAM_Disable\n
+  *         D3AMR / SRDAMR        SRAM4         LL_CLKAM_Disable
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_CLKAM_PERIPH_BDMA
+  *         @arg @ref LL_CLKAM_PERIPH_LPUART1
+  *         @arg @ref LL_CLKAM_PERIPH_SPI6
+  *         @arg @ref LL_CLKAM_PERIPH_I2C4
+  *         @arg @ref LL_CLKAM_PERIPH_LPTIM2
+  *         @arg @ref LL_CLKAM_PERIPH_LPTIM3
+  *         @arg @ref LL_CLKAM_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_CLKAM_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_CLKAM_PERIPH_DAC2   (*)
+  *         @arg @ref LL_CLKAM_PERIPH_COMP12
+  *         @arg @ref LL_CLKAM_PERIPH_VREF
+  *         @arg @ref LL_CLKAM_PERIPH_RTC
+  *         @arg @ref LL_CLKAM_PERIPH_CRC
+  *         @arg @ref LL_CLKAM_PERIPH_SAI4 (*)
+  *         @arg @ref LL_CLKAM_PERIPH_ADC3 (*)
+  *         @arg @ref LL_CLKAM_PERIPH_DTS  (*)
+  *         @arg @ref LL_CLKAM_PERIPH_DFSDM2  (*)
+  *         @arg @ref LL_CLKAM_PERIPH_BKPRAM
+  *         @arg @ref LL_CLKAM_PERIPH_SRAM4
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_CLKAM_Disable(uint32_t Periphs)
+{
+#if defined(RCC_D3AMR_BDMAAMEN)
+  CLEAR_BIT(RCC->D3AMR, Periphs);
+#else
+  CLEAR_BIT(RCC->SRDAMR, Periphs);
+#endif /* RCC_D3AMR_BDMAAMEN */
+}
+
+#if defined(RCC_CKGAENR_AXICKG)
+/**
+  * @}
+  */
+
+/**
+  * @brief  Enable clock gating for AXI bus peripherals.
+  * @rmtoll
+  * @param :
+  * @retval None
+*/
+__STATIC_INLINE void LL_CKGA_Enable(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->CKGAENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->CKGAENR, Periphs);
+  (void)tmpreg;
+}
+/**
+  * @}
+  */
+#endif /* RCC_CKGAENR_AXICKG */
+
+#if defined(RCC_CKGAENR_AXICKG)
+/**
+  * @}
+  */
+
+/**
+  * @brief  Disable  clock gating for AXI bus peripherals.
+  * @rmtoll
+  * @param :
+  * @retval None
+*/
+__STATIC_INLINE void LL_CKGA_Disable(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->CKGAENR, Periphs);
+}
+/**
+  * @}
+  */
+#endif /* RCC_CKGAENR_AXICKG */
+
+
+#if defined(DUAL_CORE)
+/** @defgroup BUS_LL_EF_AHB3 AHB3
+  * @{
+  */
+
+/**
+  * @brief  Enable C1 AHB3 peripherals clock.
+  * @rmtoll AHB3ENR      MDMAEN        LL_C1_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      DMA2DEN       LL_C1_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      JPGDECEN      LL_C1_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      FMCEN         LL_C1_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      QSPIEN        LL_C1_AHB3_GRP1_EnableClock\n (*)
+  *         AHB3ENR      OSPI1EN       LL_C1_AHB3_GRP1_EnableClock\n (*)
+  *         AHB3ENR      OSPI2EN       LL_C1_AHB3_GRP1_EnableClock\n (*)
+  *         AHB3ENR      IOMNGREN      LL_C1_AHB3_GRP1_EnableClock\n (*)
+  *         AHB3ENR      OTFDEC1EN     LL_C1_AHB3_GRP1_EnableClock\n (*)
+  *         AHB3ENR      OTFDEC2EN     LL_C1_AHB3_GRP1_EnableClock\n (*)
+  *         AHB3ENR      GFXMMU        LL_C1_AHB3_GRP1_EnableClock\n (*)
+  *         AHB3ENR      SDMMC1EN      LL_C1_AHB3_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1   (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2   (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_IOMNGR  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB3_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->AHB3ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->AHB3ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C1 AHB3 peripheral clock is enabled or not
+  * @rmtoll AHB3ENR      MDMAEN        LL_C1_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      DMA2DEN       LL_C1_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      JPGDECEN      LL_C1_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      FMCEN         LL_C1_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      QSPIEN        LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      OSPI1EN       LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      OSPI2EN       LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      IOMNGREN      LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      OTFDEC1EN     LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      OTFDEC2EN     LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      GFXMMU        LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      SDMMC1EN      LL_C1_AHB3_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1   (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2   (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_IOMNGR  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C1_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C1->AHB3ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C1 AHB3 peripherals clock.
+  * @rmtoll AHB3ENR      MDMAEN        LL_C1_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      DMA2DEN       LL_C1_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      JPGDECEN      LL_C1_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      FMCEN         LL_C1_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      QSPIEN        LL_C1_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      OSPI1EN       LL_C1_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      OSPI2EN       LL_C1_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      IOMNGREN      LL_C1_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      OTFDEC1EN     LL_C1_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      OTFDEC2EN     LL_C1_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      GFXMMU        LL_C1_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      SDMMC1EN      LL_C1_AHB3_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1   (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2   (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_IOMNGR  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB3_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->AHB3ENR, Periphs);
+}
+
+/**
+  * @brief  Enable C1 AHB3 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB3LPENR    MDMALPEN      LL_C1_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    DMA2DLPEN     LL_C1_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    JPGDECLPEN    LL_C1_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    FMCLPEN       LL_C1_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    QSPILPEN      LL_C1_AHB3_GRP1_EnableClockSleep\n  (*)
+  *         AHB3LPENR    OSPI1LPEN     LL_C1_AHB3_GRP1_EnableClockSleep\n  (*)
+  *         AHB3LPENR    OSPI2LPEN     LL_C1_AHB3_GRP1_EnableClockSleep\n  (*)
+  *         AHB3LPENR    IOMNGRLPEN    LL_C1_AHB3_GRP1_EnableClockSleep\n  (*)
+  *         AHB3LPENR    OTFDEC1LPEN   LL_C1_AHB3_GRP1_EnableClockSleep\n  (*)
+  *         AHB3LPENR    OTFDEC1LPEN   LL_C1_AHB3_GRP1_EnableClockSleep\n  (*)
+  *         AHB3LPENR    GFXMMULPEN    LL_C1_AHB3_GRP1_EnableClockSleep\n  (*)
+  *         AHB3LPENR    SDMMC1LPEN    LL_C1_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    FLASHLPEN     LL_C1_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    DTCM1LPEN     LL_C1_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    DTCM2LPEN     LL_C1_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    ITCMLPEN      LL_C1_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    AXISRAMLPEN   LL_C1_AHB3_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI     (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU   (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->AHB3LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->AHB3LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C1 AHB3 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB3LPENR    MDMALPEN      LL_C1_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    DMA2DLPEN     LL_C1_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    JPGDECLPEN    LL_C1_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    FMCLPEN       LL_C1_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    QSPILPEN      LL_C1_AHB3_GRP1_DisableClockSleep\n  (*)
+  *         AHB3LPENR    OSPI1LPEN     LL_C1_AHB3_GRP1_DisableClockSleep\n  (*)
+  *         AHB3LPENR    OSPI2LPEN     LL_C1_AHB3_GRP1_DisableClockSleep\n  (*)
+  *         AHB3LPENR    IOMNGRLPEN    LL_C1_AHB3_GRP1_DisableClockSleep\n  (*)
+  *         AHB3LPENR    OTFDEC1LPEN   LL_C1_AHB3_GRP1_DisableClockSleep\n  (*)
+  *         AHB3LPENR    OTFDEC1LPEN   LL_C1_AHB3_GRP1_DisableClockSleep\n  (*)
+  *         AHB3LPENR    GFXMMULPEN    LL_C1_AHB3_GRP1_DisableClockSleep\n  (*)
+  *         AHB3LPENR    SDMMC1LPEN    LL_C1_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    FLASHLPEN     LL_C1_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    DTCM1LPEN     LL_C1_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    DTCM2LPEN     LL_C1_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    ITCMLPEN      LL_C1_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    AXISRAMLPEN   LL_C1_AHB3_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI     (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU   (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->AHB3LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_AHB1 AHB1
+  * @{
+  */
+
+/**
+  * @brief  Enable C1 AHB1 peripherals clock.
+  * @rmtoll AHB1ENR      DMA1EN        LL_C1_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      DMA2EN        LL_C1_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      ADC12EN       LL_C1_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      CRCEN         LL_C1_AHB1_GRP1_EnableClock\n  (*)
+  *         AHB1ENR      ARTEN         LL_C1_AHB1_GRP1_EnableClock\n  (*)
+  *         AHB1ENR      ETH1MACEN     LL_C1_AHB1_GRP1_EnableClock\n  (*)
+  *         AHB1ENR      ETH1TXEN      LL_C1_AHB1_GRP1_EnableClock\n  (*)
+  *         AHB1ENR      ETH1RXEN      LL_C1_AHB1_GRP1_EnableClock\n  (*)
+  *         AHB1ENR      USB1OTGHSEN   LL_C1_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      USB1OTGHSULPIEN  LL_C1_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      USB2OTGHSEN   LL_C1_AHB1_GRP1_EnableClock\n   (*)
+  *         AHB1ENR      USB2OTGHSULPIEN  LL_C1_AHB1_GRP1_EnableClock  (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX   (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX   (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB1_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->AHB1ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->AHB1ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C1 AHB1 peripheral clock is enabled or not
+  * @rmtoll AHB1ENR      DMA1EN        LL_C1_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      DMA2EN        LL_C1_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      ADC12EN       LL_C1_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      CRCEN         LL_C1_AHB1_GRP1_IsEnabledClock\n  (*)
+  *         AHB1ENR      ARTEN         LL_C1_AHB1_GRP1_IsEnabledClock\n  (*)
+  *         AHB1ENR      ETH1MACEN     LL_C1_AHB1_GRP1_IsEnabledClock\n  (*)
+  *         AHB1ENR      ETH1TXEN      LL_C1_AHB1_GRP1_IsEnabledClock\n  (*)
+  *         AHB1ENR      ETH1RXEN      LL_C1_AHB1_GRP1_IsEnabledClock\n  (*)
+  *         AHB1ENR      USB1OTGHSEN   LL_C1_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      USB1OTGHSULPIEN  LL_C1_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      USB2OTGHSEN   LL_C1_AHB1_GRP1_IsEnabledClock\n  (*)
+  *         AHB1ENR      USB2OTGHSULPIEN  LL_C1_AHB1_GRP1_IsEnabledClock (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX   (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX   (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C1_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C1->AHB1ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C1 AHB1 peripherals clock.
+  * @rmtoll AHB1ENR      DMA1EN        LL_C1_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      DMA2EN        LL_C1_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      ADC12EN       LL_C1_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      CRCEN         LL_C1_AHB1_GRP1_DisableClock\n (*)
+  *         AHB1ENR      ARTEN         LL_C1_AHB1_GRP1_DisableClock\n (*)
+  *         AHB1ENR      ETH1MACEN     LL_C1_AHB1_GRP1_DisableClock\n (*)
+  *         AHB1ENR      ETH1TXEN      LL_C1_AHB1_GRP1_DisableClock\n (*)
+  *         AHB1ENR      ETH1RXEN      LL_C1_AHB1_GRP1_DisableClock\n (*)
+  *         AHB1ENR      USB1OTGHSEN   LL_C1_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      USB1OTGHSULPIEN  LL_C1_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      USB2OTGHSEN   LL_C1_AHB1_GRP1_DisableClock\n (*)
+  *         AHB1ENR      USB2OTGHSULPIEN  LL_C1_AHB1_GRP1_DisableClock (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX   (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX   (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB1_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->AHB1ENR, Periphs);
+}
+
+/**
+  * @brief  Enable C1 AHB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB1LPENR    DMA1LPEN      LL_C1_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    DMA2LPEN      LL_C1_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    ADC12LPEN     LL_C1_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    CRCLPEN       LL_C1_AHB1_GRP1_EnableClockSleep\n (*)
+  *         AHB1LPENR    ARTLPEN       LL_C1_AHB1_GRP1_EnableClockSleep\n (*)
+  *         AHB1LPENR    ETH1MACLPEN   LL_C1_AHB1_GRP1_EnableClockSleep\n (*)
+  *         AHB1LPENR    ETH1TXLPEN    LL_C1_AHB1_GRP1_EnableClockSleep\n (*)
+  *         AHB1LPENR    ETH1RXLPEN    LL_C1_AHB1_GRP1_EnableClockSleep\n (*)
+  *         AHB1LPENR    USB1OTGHSLPEN  LL_C1_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    USB1OTGHSULPILPEN  LL_C1_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    USB2OTGHSLPEN  LL_C1_AHB1_GRP1_EnableClockSleep\n   (*)
+  *         AHB1LPENR    USB2OTGHSULPILPEN  LL_C1_AHB1_GRP1_EnableClockSleep (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX   (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX   (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->AHB1LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->AHB1LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C1 AHB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB1LPENR    DMA1LPEN      LL_C1_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    DMA2LPEN      LL_C1_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    ADC12LPEN     LL_C1_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    CRCLPEN       LL_C1_AHB1_GRP1_DisableClockSleep\n (*)
+  *         AHB1LPENR    ARTLPEN       LL_C1_AHB1_GRP1_DisableClockSleep\n (*)
+  *         AHB1LPENR    ETH1MACLPEN   LL_C1_AHB1_GRP1_DisableClockSleep\n (*)
+  *         AHB1LPENR    ETH1TXLPEN    LL_C1_AHB1_GRP1_DisableClockSleep\n (*)
+  *         AHB1LPENR    ETH1RXLPEN    LL_C1_AHB1_GRP1_DisableClockSleep\n (*)
+  *         AHB1LPENR    USB1OTGHSLPEN  LL_C1_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    USB1OTGHSULPILPEN  LL_C1_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    USB2OTGHSLPEN  LL_C1_AHB1_GRP1_DisableClockSleep\n   (*)
+  *         AHB1LPENR    USB2OTGHSULPILPEN  LL_C1_AHB1_GRP1_DisableClockSleep (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX   (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX   (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->AHB1LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_AHB2 AHB2
+  * @{
+  */
+
+/**
+  * @brief  Enable C1 AHB2 peripherals clock.
+  * @rmtoll AHB2ENR      DCMIEN        LL_C1_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      HSEMEN        LL_C1_AHB2_GRP1_EnableClock\n (*)
+  *         AHB2ENR      CRYPEN        LL_C1_AHB2_GRP1_EnableClock\n (*)
+  *         AHB2ENR      HASHEN        LL_C1_AHB2_GRP1_EnableClock\n (*)
+  *         AHB2ENR      RNGEN         LL_C1_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      SDMMC2EN      LL_C1_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      BDMA1EN       LL_C1_AHB2_GRP1_EnableClock\n (*)
+  *         AHB2ENR      D2SRAM1EN     LL_C1_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      D2SRAM2EN     LL_C1_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      D2SRAM3EN     LL_C1_AHB2_GRP1_EnableClock   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB2_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->AHB2ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->AHB2ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C1 AHB2 peripheral clock is enabled or not
+  * @rmtoll AHB2ENR      DCMIEN        LL_C1_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      HSEMEN        LL_C1_AHB2_GRP1_IsEnabledClock\n (*)
+  *         AHB2ENR      CRYPEN        LL_C1_AHB2_GRP1_IsEnabledClock\n (*)
+  *         AHB2ENR      HASHEN        LL_C1_AHB2_GRP1_IsEnabledClock\n (*)
+  *         AHB2ENR      RNGEN         LL_C1_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      SDMMC2EN      LL_C1_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      BDMA1EN       LL_C1_AHB2_GRP1_IsEnabledClock\n (*)
+  *         AHB2ENR      D2SRAM1EN     LL_C1_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      D2SRAM2EN     LL_C1_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      D2SRAM3EN     LL_C1_AHB2_GRP1_IsEnabledClock   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C1_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C1->AHB2ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C1 AHB2 peripherals clock.
+  * @rmtoll AHB2ENR      DCMIEN        LL_C1_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      HSEMEN        LL_C1_AHB2_GRP1_DisableClock\n (*)
+  *         AHB2ENR      CRYPEN        LL_C1_AHB2_GRP1_DisableClock\n (*)
+  *         AHB2ENR      HASHEN        LL_C1_AHB2_GRP1_DisableClock\n (*)
+  *         AHB2ENR      RNGEN         LL_C1_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      SDMMC2EN      LL_C1_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      BDMA1EN       LL_C1_AHB2_GRP1_DisableClock\n (*)
+  *         AHB2ENR      D2SRAM1EN     LL_C1_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      D2SRAM2EN     LL_C1_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      D2SRAM3EN     LL_C1_AHB2_GRP1_DisableClock   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB2_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->AHB2ENR, Periphs);
+}
+
+/**
+  * @brief  Enable C1 AHB2 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB2LPENR    DCMILPEN      LL_C1_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    CRYPLPEN      LL_C1_AHB2_GRP1_EnableClockSleep\n (*)
+  *         AHB2LPENR    HASHLPEN      LL_C1_AHB2_GRP1_EnableClockSleep\n (*)
+  *         AHB2LPENR    RNGLPEN       LL_C1_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    SDMMC2LPEN    LL_C1_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    SDMMC2LPEN    LL_C1_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    BDAM1LPEN     LL_C1_AHB2_GRP1_EnableClockSleep\n (*)
+  *         AHB2LPENR    D2SRAM2LPEN   LL_C1_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    D2SRAM3LPEN   LL_C1_AHB2_GRP1_EnableClockSleep   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDAM1 (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->AHB2LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->AHB2LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C1 AHB2 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB2LPENR    DCMILPEN      LL_C1_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    CRYPLPEN      LL_C1_AHB2_GRP1_DisableClockSleep\n (*)
+  *         AHB2LPENR    HASHLPEN      LL_C1_AHB2_GRP1_DisableClockSleep\n (*)
+  *         AHB2LPENR    RNGLPEN       LL_C1_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    SDMMC2LPEN    LL_C1_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    BDAM1LPEN     LL_C1_AHB2_GRP1_DisableClockSleep\n (*)
+  *         AHB2LPENR    D2SRAM1LPEN   LL_C1_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    D2SRAM2LPEN   LL_C1_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    D2SRAM3LPEN   LL_C1_AHB2_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDAM1 (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->AHB2LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_AHB4 AHB4
+  * @{
+  */
+
+/**
+  * @brief  Enable C1 AHB4 peripherals clock.
+  * @rmtoll AHB4ENR      GPIOAEN       LL_C1_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOBEN       LL_C1_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOCEN       LL_C1_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIODEN       LL_C1_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOEEN       LL_C1_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOFEN       LL_C1_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOGEN       LL_C1_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOHEN       LL_C1_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOIEN       LL_C1_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOJEN       LL_C1_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOKEN       LL_C1_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      CRCEN         LL_C1_AHB4_GRP1_EnableClock\n (*)
+  *         AHB4ENR      BDMAEN        LL_C1_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      ADC3EN        LL_C1_AHB4_GRP1_EnableClock\n (*)
+  *         AHB4ENR      HSEMEN        LL_C1_AHB4_GRP1_EnableClock\n (*)
+  *         AHB4ENR      BKPRAMEN      LL_C1_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      SRAM4EN       LL_C1_AHB4_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB4_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->AHB4ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->AHB4ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C1 AHB4 peripheral clock is enabled or not
+  * @rmtoll AHB4ENR      GPIOAEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOBEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOCEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIODEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOEEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOFEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOGEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOHEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOIEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOJEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOKEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      CRCEN         LL_C1_AHB4_GRP1_IsEnabledClock\n (*)
+  *         AHB4ENR      BDMAEN        LL_C1_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      ADC3EN        LL_C1_AHB4_GRP1_IsEnabledClock\n (*)
+  *         AHB4ENR      HSEMEN        LL_C1_AHB4_GRP1_IsEnabledClock\n (*)
+  *         AHB4ENR      BKPRAMEN      LL_C1_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      SRAM4EN       LL_C1_AHB4_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C1_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C1->AHB4ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C1 AHB4 peripherals clock.
+  * @rmtoll AHB4ENR      GPIOAEN       LL_C1_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOBEN       LL_C1_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOCEN       LL_C1_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIODEN       LL_C1_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOEEN       LL_C1_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOFEN       LL_C1_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOGEN       LL_C1_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOHEN       LL_C1_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOIEN       LL_C1_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOJEN       LL_C1_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOKEN       LL_C1_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      CRCEN         LL_C1_AHB4_GRP1_DisableClock\n (*)
+  *         AHB4ENR      BDMAEN        LL_C1_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      ADC3EN        LL_C1_AHB4_GRP1_DisableClock\n (*)
+  *         AHB4ENR      HSEMEN        LL_C1_AHB4_GRP1_DisableClock\n (*)
+  *         AHB4ENR      BKPRAMEN      LL_C1_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      SRAM4EN       LL_C1_AHB4_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB4_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->AHB4ENR, Periphs);
+}
+
+/**
+  * @brief  Enable C1 AHB4 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB4LPENR    GPIOALPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOBLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOCLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIODLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOELPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOFLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOGLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOHLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOILPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOJLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOKLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    CRCLPEN       LL_C1_AHB4_GRP1_EnableClockSleep\n (*)
+  *         AHB4LPENR    BDMALPEN      LL_C1_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    ADC3LPEN      LL_C1_AHB4_GRP1_EnableClockSleep\n (*)
+  *         AHB4LPENR    BKPRAMLPEN    LL_C1_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    SRAM4LPEN     LL_C1_AHB4_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB4_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->AHB4LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->AHB4LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C1 AHB4 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB4LPENR    GPIOALPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOBLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOCLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIODLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOELPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOFLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOGLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOHLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOILPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOJLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOKLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    CRCLPEN       LL_C1_AHB4_GRP1_DisableClockSleep\n (*)
+  *         AHB4LPENR    BDMALPEN      LL_C1_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    ADC3LPEN      LL_C1_AHB4_GRP1_DisableClockSleep\n (*)
+  *         AHB4LPENR    BKPRAMLPEN    LL_C1_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    SRAM4LPEN     LL_C1_AHB4_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB4_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->AHB4LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_APB3 APB3
+  * @{
+  */
+
+/**
+  * @brief  Enable C1 APB3 peripherals clock.
+  * @rmtoll APB3ENR      LTDCEN        LL_C1_APB3_GRP1_EnableClock\n (*)
+  *         APB3ENR      DSIEN         LL_C1_APB3_GRP1_EnableClock\n (*)
+  *         APB3ENR      WWDG1EN       LL_C1_APB3_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI  (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB3_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->APB3ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->APB3ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C1 APB3 peripheral clock is enabled or not
+  * @rmtoll APB3ENR      LTDCEN        LL_C1_APB3_GRP1_IsEnabledClock\n (*)
+  *         APB3ENR      DSIEN         LL_C1_APB3_GRP1_IsEnabledClock\n (*)
+  *         APB3ENR      WWDG1EN       LL_C1_APB3_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI  (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C1_APB3_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C1->APB3ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C1 APB3 peripherals clock.
+  * @rmtoll APB3ENR      LTDCEN        LL_C1_APB3_GRP1_DisableClock\n (*)
+  *         APB3ENR      DSIEN         LL_C1_APB3_GRP1_DisableClock\n (*)
+  *         APB3ENR      WWDG1EN       LL_C1_APB3_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI  (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB3_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->APB3ENR, Periphs);
+}
+
+/**
+  * @brief  Enable C1 APB3 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB3LPENR    LTDCLPEN      LL_C1_APB3_GRP1_EnableClockSleep\n (*)
+  *         APB3LPENR    DSILPEN       LL_C1_APB3_GRP1_EnableClockSleep\n (*)
+  *         APB3LPENR    WWDG1LPEN     LL_C1_APB3_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI  (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB3_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->APB3LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->APB3LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C1 APB3 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB3LPENR    LTDCLPEN      LL_C1_APB3_GRP1_DisableClockSleep\n (*)
+  *         APB3LPENR    DSILPEN       LL_C1_APB3_GRP1_DisableClockSleep\n (*)
+  *         APB3LPENR    WWDG1LPEN     LL_C1_APB3_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI  (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB3_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->APB3LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_APB1 APB1
+  * @{
+  */
+
+/**
+  * @brief  Enable C1 APB1 peripherals clock.
+  * @rmtoll APB1LENR     TIM2EN        LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM3EN        LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM4EN        LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM5EN        LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM6EN        LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM7EN        LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM12EN       LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM13EN       LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM14EN       LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     LPTIM1EN      LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     WWDG2EN       LL_C1_APB1_GRP1_EnableClock\n (*)
+  *         APB1LENR     SPI2EN        LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     SPI3EN        LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     SPDIFRXEN     LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     USART2EN      LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     USART3EN      LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     UART4EN       LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     UART5EN       LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     I2C1EN        LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     I2C2EN        LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     I2C3EN        LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     CECEN         LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     DAC12EN       LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     UART7EN       LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     UART8EN       LL_C1_APB1_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB1_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->APB1LENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->APB1LENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C1 APB1 peripheral clock is enabled or not
+  * @rmtoll APB1LENR     TIM2EN        LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM3EN        LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM4EN        LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM5EN        LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM6EN        LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM7EN        LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM12EN       LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM13EN       LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM14EN       LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     LPTIM1EN      LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     WWDG2EN       LL_C1_APB1_GRP1_IsEnabledClock\n (*)
+  *         APB1LENR     SPI2EN        LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     SPI3EN        LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     SPDIFRXEN     LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     USART2EN      LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     USART3EN      LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     UART4EN       LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     UART5EN       LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     I2C1EN        LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     I2C2EN        LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     I2C3EN        LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     CECEN         LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     DAC12EN       LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     UART7EN       LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     UART8EN       LL_C1_APB1_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C1_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C1->APB1LENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C1 APB1 peripherals clock.
+  * @rmtoll APB1LENR     TIM2EN        LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM3EN        LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM4EN        LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM5EN        LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM6EN        LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM7EN        LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM12EN       LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM13EN       LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM14EN       LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     LPTIM1EN      LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     WWDG2EN       LL_C1_APB1_GRP1_DisableClock\n (*)
+  *         APB1LENR     SPI2EN        LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     SPI3EN        LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     SPDIFRXEN     LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     USART2EN      LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     USART3EN      LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     UART4EN       LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     UART5EN       LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     I2C1EN        LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     I2C2EN        LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     I2C3EN        LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     CECEN         LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     DAC12EN       LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     UART7EN       LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     UART8EN       LL_C1_APB1_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE void LL_C1_APB1_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->APB1LENR, Periphs);
+}
+
+/**
+  * @brief  Enable C1 APB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB1LLPENR   TIM2LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM3LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM4LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM5LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM6LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM7LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM12LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM13LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM14LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   LPTIM1LPEN    LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   WWDG2LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n (*)
+  *         APB1LLPENR   SPI2LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   SPI3LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   SPDIFRXLPEN   LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   USART2LPEN    LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   USART3LPEN    LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   UART4LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   UART5LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   I2C1LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   I2C2LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   I2C3LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   CECLPEN       LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   DAC12LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   UART7LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   UART8LPEN     LL_C1_APB1_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->APB1LLPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->APB1LLPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C1 APB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB1LLPENR   TIM2LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM3LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM4LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM5LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM6LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM7LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM12LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM13LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM14LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   LPTIM1LPEN    LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   WWDG2LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n (*)
+  *         APB1LLPENR   SPI2LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   SPI3LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   SPDIFRXLPEN   LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   USART2LPEN    LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   USART3LPEN    LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   UART4LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   UART5LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   I2C1LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   I2C2LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   I2C3LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   CECLPEN       LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   DAC12LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   UART7LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   UART8LPEN     LL_C1_APB1_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->APB1LLPENR, Periphs);
+}
+
+/**
+  * @brief  Enable C1 APB1 peripherals clock.
+  * @rmtoll APB1HENR     CRSEN         LL_C1_APB1_GRP2_EnableClock\n
+  *         APB1HENR     SWPMIEN       LL_C1_APB1_GRP2_EnableClock\n
+  *         APB1HENR     OPAMPEN       LL_C1_APB1_GRP2_EnableClock\n
+  *         APB1HENR     MDIOSEN       LL_C1_APB1_GRP2_EnableClock\n
+  *         APB1HENR     FDCANEN       LL_C1_APB1_GRP2_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB1_GRP2_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->APB1HENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->APB1HENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C1 APB1 peripheral clock is enabled or not
+  * @rmtoll APB1HENR     CRSEN         LL_C1_APB1_GRP2_IsEnabledClock\n
+  *         APB1HENR     SWPMIEN       LL_C1_APB1_GRP2_IsEnabledClock\n
+  *         APB1HENR     OPAMPEN       LL_C1_APB1_GRP2_IsEnabledClock\n
+  *         APB1HENR     MDIOSEN       LL_C1_APB1_GRP2_IsEnabledClock\n
+  *         APB1HENR     FDCANEN       LL_C1_APB1_GRP2_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C1_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C1->APB1HENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C1 APB1 peripherals clock.
+  * @rmtoll APB1HENR     CRSEN         LL_C1_APB1_GRP2_DisableClock\n
+  *         APB1HENR     SWPMIEN       LL_C1_APB1_GRP2_DisableClock\n
+  *         APB1HENR     OPAMPEN       LL_C1_APB1_GRP2_DisableClock\n
+  *         APB1HENR     MDIOSEN       LL_C1_APB1_GRP2_DisableClock\n
+  *         APB1HENR     FDCANEN       LL_C1_APB1_GRP2_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB1_GRP2_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->APB1HENR, Periphs);
+}
+
+/**
+  * @brief  Enable C1 APB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB1HLPENR   CRSLPEN       LL_C1_APB1_GRP2_EnableClockSleep\n
+  *         APB1HLPENR   SWPMILPEN     LL_C1_APB1_GRP2_EnableClockSleep\n
+  *         APB1HLPENR   OPAMPLPEN     LL_C1_APB1_GRP2_EnableClockSleep\n
+  *         APB1HLPENR   MDIOSLPEN     LL_C1_APB1_GRP2_EnableClockSleep\n
+  *         APB1HLPENR   FDCANLPEN     LL_C1_APB1_GRP2_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB1_GRP2_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->APB1HLPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->APB1HLPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C1 APB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB1HLPENR   CRSLPEN       LL_C1_APB1_GRP2_DisableClockSleep\n
+  *         APB1HLPENR   SWPMILPEN     LL_C1_APB1_GRP2_DisableClockSleep\n
+  *         APB1HLPENR   OPAMPLPEN     LL_C1_APB1_GRP2_DisableClockSleep\n
+  *         APB1HLPENR   MDIOSLPEN     LL_C1_APB1_GRP2_DisableClockSleep\n
+  *         APB1HLPENR   FDCANLPEN     LL_C1_APB1_GRP2_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB1_GRP2_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->APB1HLPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_APB2 APB2
+  * @{
+  */
+
+/**
+  * @brief  Enable C1 APB2 peripherals clock.
+  * @rmtoll APB2ENR      TIM1EN        LL_C1_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM8EN        LL_C1_APB2_GRP1_EnableClock\n
+  *         APB2ENR      USART1EN      LL_C1_APB2_GRP1_EnableClock\n
+  *         APB2ENR      USART6EN      LL_C1_APB2_GRP1_EnableClock\n
+  *         APB2ENR      UART9EN       LL_C1_APB2_GRP1_EnableClock\n (*)
+  *         APB2ENR      USART10EN     LL_C1_APB2_GRP1_EnableClock\n (*)
+  *         APB2ENR      SPI1EN        LL_C1_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SPI4EN        LL_C1_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM15EN       LL_C1_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM16EN       LL_C1_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM17EN       LL_C1_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SPI5EN        LL_C1_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SAI1EN        LL_C1_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SAI2EN        LL_C1_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SAI3EN        LL_C1_APB2_GRP1_EnableClock\n (*)
+  *         APB2ENR      DFSDM1EN      LL_C1_APB2_GRP1_EnableClock\n
+  *         APB2ENR      HRTIMEN       LL_C1_APB2_GRP1_EnableClock   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB2_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->APB2ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->APB2ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C1 APB2 peripheral clock is enabled or not
+  * @rmtoll APB2ENR      TIM1EN        LL_C1_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM8EN        LL_C1_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      USART1EN      LL_C1_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      USART6EN      LL_C1_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      UART9EN       LL_C1_APB2_GRP1_IsEnabledClock\n (*)
+  *         APB2ENR      USART10EN     LL_C1_APB2_GRP1_IsEnabledClock\n (*)
+  *         APB2ENR      SPI1EN        LL_C1_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SPI4EN        LL_C1_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM15EN       LL_C1_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM16EN       LL_C1_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM17EN       LL_C1_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SPI5EN        LL_C1_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SAI1EN        LL_C1_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SAI2EN        LL_C1_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SAI3EN        LL_C1_APB2_GRP1_IsEnabledClock\n (*)
+  *         APB2ENR      DFSDM1EN      LL_C1_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      HRTIMEN       LL_C1_APB2_GRP1_IsEnabledClock   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE uint32_t LL_C1_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C1->APB2ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C1 APB2 peripherals clock.
+  * @rmtoll APB2ENR      TIM1EN        LL_C1_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM8EN        LL_C1_APB2_GRP1_DisableClock\n
+  *         APB2ENR      USART1EN      LL_C1_APB2_GRP1_DisableClock\n
+  *         APB2ENR      USART6EN      LL_C1_APB2_GRP1_DisableClock\n
+  *         APB2ENR      UART9EN       LL_C1_APB2_GRP1_DisableClock\n (*)
+  *         APB2ENR      USART10EN     LL_C1_APB2_GRP1_DisableClock\n (*)
+  *         APB2ENR      SPI1EN        LL_C1_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SPI4EN        LL_C1_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM15EN       LL_C1_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM16EN       LL_C1_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM17EN       LL_C1_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SPI5EN        LL_C1_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SAI1EN        LL_C1_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SAI2EN        LL_C1_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SAI3EN        LL_C1_APB2_GRP1_DisableClock\n  (*)
+  *         APB2ENR      DFSDM1EN      LL_C1_APB2_GRP1_DisableClock\n
+  *         APB2ENR      HRTIMEN       LL_C1_APB2_GRP1_DisableClock    (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB2_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->APB2ENR, Periphs);
+}
+
+/**
+  * @brief  Enable C1 APB2 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB2LPENR    TIM1LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    TIM8LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    USART1LPEN    LL_C1_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    USART6LPEN    LL_C1_APB2_GRP1_EnableClockSleep\n
+  *         APB2ENR      UART9EN       LL_C1_APB2_GRP1_EnableClockSleep\n (*)
+  *         APB2ENR      USART10EN     LL_C1_APB2_GRP1_EnableClockSleep\n (*)
+  *         APB2LPENR    SPI1LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SPI4LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    TIM15LPEN     LL_C1_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    TIM16LPEN     LL_C1_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    TIM17LPEN     LL_C1_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SPI5LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SAI1LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SAI2LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SAI3LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n (*)
+  *         APB2LPENR    DFSDM1LPEN    LL_C1_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    HRTIMLPEN     LL_C1_APB2_GRP1_EnableClockSleep   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->APB2LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->APB2LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C1 APB2 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB2LPENR    TIM1LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    TIM8LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    USART1LPEN    LL_C1_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    UART9LPEN     LL_C1_APB2_GRP1_DisableClockSleep\n (*)
+  *         APB2LPENR    USART10LPEN   LL_C1_APB2_GRP1_DisableClockSleep\n (*)
+  *         APB2LPENR    USART6LPEN    LL_C1_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SPI1LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SPI4LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    TIM15LPEN     LL_C1_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    TIM16LPEN     LL_C1_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    TIM17LPEN     LL_C1_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SPI5LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SAI1LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SAI2LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SAI3LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n (*)
+  *         APB2LPENR    DFSDM1LPEN    LL_C1_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    HRTIMLPEN     LL_C1_APB2_GRP1_DisableClockSleep   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->APB2LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_APB4 APB4
+  * @{
+  */
+
+/**
+  * @brief  Enable C1 APB4 peripherals clock.
+  * @rmtoll APB4ENR      SYSCFGEN      LL_C1_APB4_GRP1_EnableClock\n
+  *         APB4ENR      LPUART1EN     LL_C1_APB4_GRP1_EnableClock\n
+  *         APB4ENR      SPI6EN        LL_C1_APB4_GRP1_EnableClock\n
+  *         APB4ENR      I2C4EN        LL_C1_APB4_GRP1_EnableClock\n
+  *         APB4ENR      LPTIM2EN      LL_C1_APB4_GRP1_EnableClock\n
+  *         APB4ENR      LPTIM3EN      LL_C1_APB4_GRP1_EnableClock\n
+  *         APB4ENR      LPTIM4EN      LL_C1_APB4_GRP1_EnableClock\n (*)
+  *         APB4ENR      LPTIM5EN      LL_C1_APB4_GRP1_EnableClock\n (*)
+  *         APB4ENR      DAC2EN        LL_C1_APB4_GRP1_EnableClock\n (*)
+  *         APB4ENR      COMP12EN      LL_C1_APB4_GRP1_EnableClock\n
+  *         APB4ENR      VREFEN        LL_C1_APB4_GRP1_EnableClock\n
+  *         APB4ENR      RTCAPBEN      LL_C1_APB4_GRP1_EnableClock\n
+  *         APB4ENR      SAI4EN        LL_C1_APB4_GRP1_EnableClock\n (*)
+  *         APB4ENR      DTSEN         LL_C1_APB4_GRP1_EnableClock\n (*)
+  *         APB4ENR      DFSDM2EN      LL_C1_APB4_GRP1_EnableClock   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB4_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->APB4ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->APB4ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C1 APB4 peripheral clock is enabled or not
+  * @rmtoll APB4ENR      SYSCFGEN      LL_C1_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      LPUART1EN     LL_C1_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      SPI6EN        LL_C1_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      I2C4EN        LL_C1_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      LPTIM2EN      LL_C1_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      LPTIM3EN      LL_C1_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      LPTIM4EN      LL_C1_APB4_GRP1_IsEnabledClock\n (*)
+  *         APB4ENR      LPTIM5EN      LL_C1_APB4_GRP1_IsEnabledClock\n (*)
+  *         APB4ENR      COMP12EN      LL_C1_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      VREFEN        LL_C1_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      RTCAPBEN      LL_C1_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      SAI4EN        LL_C1_APB4_GRP1_IsEnabledClock\n (*)
+  *         APB4ENR      DTSEN         LL_C1_APB4_GRP1_IsEnabledClock\n (*)
+  *         APB4ENR      DFSDM2EN      LL_C1_APB4_GRP1_IsEnabledClock   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C1_APB4_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C1->APB4ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C1 APB4 peripherals clock.
+  * @rmtoll APB4ENR      SYSCFGEN      LL_C1_APB4_GRP1_DisableClock\n
+  *         APB4ENR      LPUART1EN     LL_C1_APB4_GRP1_DisableClock\n
+  *         APB4ENR      SPI6EN        LL_C1_APB4_GRP1_DisableClock\n
+  *         APB4ENR      I2C4EN        LL_C1_APB4_GRP1_DisableClock\n
+  *         APB4ENR      LPTIM2EN      LL_C1_APB4_GRP1_DisableClock\n
+  *         APB4ENR      LPTIM3EN      LL_C1_APB4_GRP1_DisableClock\n
+  *         APB4ENR      LPTIM4EN      LL_C1_APB4_GRP1_DisableClock\n (*)
+  *         APB4ENR      LPTIM5EN      LL_C1_APB4_GRP1_DisableClock\n (*)
+  *         APB4ENR      COMP12EN      LL_C1_APB4_GRP1_DisableClock\n
+  *         APB4ENR      VREFEN        LL_C1_APB4_GRP1_DisableClock\n
+  *         APB4ENR      RTCAPBEN      LL_C1_APB4_GRP1_DisableClock\n
+  *         APB4ENR      SAI4EN        LL_C1_APB4_GRP1_DisableClock\n (*)
+  *         APB4ENR      DTSEN         LL_C1_APB4_GRP1_DisableClock\n (*)
+  *         APB4ENR      DFSDM2EN      LL_C1_APB4_GRP1_DisableClock   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB4_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->APB4ENR, Periphs);
+}
+
+/**
+  * @brief  Enable C1 APB4 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB4LPENR    SYSCFGLPEN    LL_C1_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    LPUART1LPEN   LL_C1_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    SPI6LPEN      LL_C1_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    I2C4LPEN      LL_C1_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    LPTIM2LPEN    LL_C1_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    LPTIM3LPEN    LL_C1_APB4_GRP1_EnableClockSleep\n (*)
+  *         APB4LPENR    LPTIM4LPEN    LL_C1_APB4_GRP1_EnableClockSleep\n (*)
+  *         APB4LPENR    LPTIM5LPEN    LL_C1_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    COMP12LPEN    LL_C1_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    VREFLPEN      LL_C1_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    RTCAPBLPEN    LL_C1_APB4_GRP1_EnableClockSleep\n
+  *         APB4ENR      SAI4EN        LL_C1_APB4_GRP1_EnableClockSleep\n (*)
+  *         APB4ENR      DTSEN         LL_C1_APB4_GRP1_EnableClockSleep\n (*)
+  *         APB4ENR      DFSDM2EN      LL_C1_APB4_GRP1_EnableClockSleep   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB4_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->APB4LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->APB4LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C1 APB4 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB4LPENR    SYSCFGLPEN    LL_C1_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    LPUART1LPEN   LL_C1_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    SPI6LPEN      LL_C1_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    I2C4LPEN      LL_C1_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    LPTIM2LPEN    LL_C1_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    LPTIM3LPEN    LL_C1_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    LPTIM4LPEN    LL_C1_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    LPTIM5LPEN    LL_C1_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    COMP12LPEN    LL_C1_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    VREFLPEN      LL_C1_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    RTCAPBLPEN    LL_C1_APB4_GRP1_DisableClockSleep\n
+  *         APB4ENR      SAI4EN        LL_C1_APB4_GRP1_DisableClockSleep\n (*)
+  *         APB4ENR      DTSEN         LL_C1_APB4_GRP1_DisableClockSleep\n (*)
+  *         APB4ENR      DFSDM2EN      LL_C1_APB4_GRP1_DisableClockSleep   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB4_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->APB4LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_AHB3 AHB3
+  * @{
+  */
+
+/**
+  * @brief  Enable C2 AHB3 peripherals clock.
+  * @rmtoll AHB3ENR      MDMAEN        LL_C2_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      DMA2DEN       LL_C2_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      JPGDECEN      LL_C2_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      FMCEN         LL_C2_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      QSPIEN        LL_C2_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      SDMMC1EN      LL_C2_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      FLASHEN       LL_C2_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      DTCM1EN       LL_C2_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      DTCM2EN       LL_C2_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      ITCMEN        LL_C2_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      AXISRAMEN     LL_C2_AHB3_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->AHB3ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->AHB3ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C2 AHB3 peripheral clock is enabled or not
+  * @rmtoll AHB3ENR      MDMAEN        LL_C2_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      DMA2DEN       LL_C2_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      JPGDECEN      LL_C2_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      FMCEN         LL_C2_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      QSPIEN        LL_C2_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      SDMMC1EN      LL_C2_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      FLASHEN       LL_C2_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      DTCM1EN       LL_C2_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      DTCM2EN       LL_C2_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      ITCMEN        LL_C2_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      AXISRAMEN     LL_C2_AHB3_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C2_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C2->AHB3ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C2 AHB3 peripherals clock.
+  * @rmtoll AHB3ENR      MDMAEN        LL_C2_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      DMA2DEN       LL_C2_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      JPGDECEN      LL_C2_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      FMCEN         LL_C2_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      QSPIEN        LL_C2_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      SDMMC1EN      LL_C2_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      FLASHEN       LL_C2_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      DTCM1EN       LL_C2_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      DTCM2EN       LL_C2_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      ITCMEN        LL_C2_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      AXISRAMEN     LL_C2_AHB3_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->AHB3ENR, Periphs);
+}
+
+/**
+  * @brief  Enable C2 AHB3 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB3LPENR    MDMALPEN      LL_C2_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    DMA2DLPEN     LL_C2_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    JPGDECLPEN    LL_C2_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    FMCLPEN       LL_C2_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    QSPILPEN      LL_C2_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    SDMMC1LPEN    LL_C2_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    FLASHLPEN     LL_C2_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    DTCM1LPEN     LL_C2_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    DTCM2LPEN     LL_C2_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    ITCMLPEN      LL_C2_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    AXISRAMLPEN   LL_C2_AHB3_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->AHB3LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->AHB3LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C2 AHB3 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB3LPENR    MDMALPEN      LL_C2_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    DMA2DLPEN     LL_C2_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    JPGDECLPEN    LL_C2_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    FMCLPEN       LL_C2_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    QSPILPEN      LL_C2_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    SDMMC1LPEN    LL_C2_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    FLASHLPEN     LL_C2_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    DTCM1LPEN     LL_C2_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    DTCM2LPEN     LL_C2_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    ITCMLPEN      LL_C2_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    AXISRAMLPEN   LL_C2_AHB3_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->AHB3LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_AHB1 AHB1
+  * @{
+  */
+
+/**
+  * @brief  Enable C2 AHB1 peripherals clock.
+  * @rmtoll AHB1ENR      DMA1EN        LL_C2_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      DMA2EN        LL_C2_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      ADC12EN       LL_C2_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      ARTEN         LL_C2_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      ETH1MACEN     LL_C2_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      ETH1TXEN      LL_C2_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      ETH1RXEN      LL_C2_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      USB1OTGHSEN   LL_C2_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      USB1OTGHSULPIEN  LL_C2_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      USB2OTGHSEN   LL_C2_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      USB2OTGHSULPIEN  LL_C2_AHB1_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->AHB1ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->AHB1ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C2 AHB1 peripheral clock is enabled or not
+  * @rmtoll AHB1ENR      DMA1EN        LL_C2_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      DMA2EN        LL_C2_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      ADC12EN       LL_C2_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      ARTEN         LL_C2_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      ETH1MACEN     LL_C2_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      ETH1TXEN      LL_C2_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      ETH1RXEN      LL_C2_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      USB1OTGHSEN   LL_C2_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      USB1OTGHSULPIEN  LL_C2_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      USB2OTGHSEN   LL_C2_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      USB2OTGHSULPIEN  LL_C2_AHB1_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C2_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C2->AHB1ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C2 AHB1 peripherals clock.
+  * @rmtoll AHB1ENR      DMA1EN        LL_C2_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      DMA2EN        LL_C2_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      ADC12EN       LL_C2_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      ARTEN         LL_C2_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      ETH1MACEN     LL_C2_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      ETH1TXEN      LL_C2_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      ETH1RXEN      LL_C2_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      USB1OTGHSEN   LL_C2_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      USB1OTGHSULPIEN  LL_C2_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      USB2OTGHSEN   LL_C2_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      USB2OTGHSULPIEN  LL_C2_AHB1_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->AHB1ENR, Periphs);
+}
+
+/**
+  * @brief  Enable C2 AHB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB1LPENR    DMA1LPEN      LL_C2_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    DMA2LPEN      LL_C2_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    ADC12LPEN     LL_C2_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    ARTLPEN       LL_C2_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    ETH1MACLPEN   LL_C2_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    ETH1TXLPEN    LL_C2_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    ETH1RXLPEN    LL_C2_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    USB1OTGHSLPEN  LL_C2_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    USB1OTGHSULPILPEN  LL_C2_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    USB2OTGHSLPEN  LL_C2_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    USB2OTGHSULPILPEN  LL_C2_AHB1_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->AHB1LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->AHB1LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C2 AHB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB1LPENR    DMA1LPEN      LL_C2_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    DMA2LPEN      LL_C2_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    ADC12LPEN     LL_C2_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    ARTLPEN       LL_C2_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    ETH1MACLPEN   LL_C2_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    ETH1TXLPEN    LL_C2_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    ETH1RXLPEN    LL_C2_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    USB1OTGHSLPEN  LL_C2_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    USB1OTGHSULPILPEN  LL_C2_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    USB2OTGHSLPEN  LL_C2_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    USB2OTGHSULPILPEN  LL_C2_AHB1_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->AHB1LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_AHB2 AHB2
+  * @{
+  */
+
+/**
+  * @brief  Enable C2 AHB2 peripherals clock.
+  * @rmtoll AHB2ENR      DCMIEN        LL_C2_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      CRYPEN        LL_C2_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      HASHEN        LL_C2_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      RNGEN         LL_C2_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      SDMMC2EN      LL_C2_AHB2_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->AHB2ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->AHB2ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C2 AHB2 peripheral clock is enabled or not
+  * @rmtoll AHB2ENR      DCMIEN        LL_C2_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      CRYPEN        LL_C2_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      HASHEN        LL_C2_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      RNGEN         LL_C2_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      SDMMC2EN      LL_C2_AHB2_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C2_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C2->AHB2ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C2 AHB2 peripherals clock.
+  * @rmtoll AHB2ENR      DCMIEN        LL_C2_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      CRYPEN        LL_C2_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      HASHEN        LL_C2_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      RNGEN         LL_C2_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      SDMMC2EN      LL_C2_AHB2_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->AHB2ENR, Periphs);
+}
+
+/**
+  * @brief  Enable C2 AHB2 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB2LPENR    DCMILPEN      LL_C2_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    CRYPLPEN      LL_C2_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    HASHLPEN      LL_C2_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    RNGLPEN       LL_C2_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    SDMMC2LPEN    LL_C2_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    D2SRAM1LPEN   LL_C2_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    D2SRAM2LPEN   LL_C2_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    D2SRAM3LPEN   LL_C2_AHB2_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->AHB2LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->AHB2LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C2 AHB2 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB2LPENR    DCMILPEN      LL_C2_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    CRYPLPEN      LL_C2_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    HASHLPEN      LL_C2_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    RNGLPEN       LL_C2_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    SDMMC2LPEN    LL_C2_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    D2SRAM1LPEN   LL_C2_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    D2SRAM2LPEN   LL_C2_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    D2SRAM3LPEN   LL_C2_AHB2_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->AHB2LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_AHB4 AHB4
+  * @{
+  */
+
+/**
+  * @brief  Enable C2 AHB4 peripherals clock.
+  * @rmtoll AHB4ENR      GPIOAEN       LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOBEN       LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOCEN       LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIODEN       LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOEEN       LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOFEN       LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOGEN       LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOHEN       LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOIEN       LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOJEN       LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOKEN       LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      CRCEN         LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      BDMAEN        LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      ADC3EN        LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      HSEMEN        LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      BKPRAMEN      LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      SRAM4EN     LL_C2_AHB4_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB4_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->AHB4ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->AHB4ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C2 AHB4 peripheral clock is enabled or not
+  * @rmtoll AHB4ENR      GPIOAEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOBEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOCEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIODEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOEEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOFEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOGEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOHEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOIEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOJEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOKEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      CRCEN         LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      BDMAEN        LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      ADC3EN        LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      HSEMEN        LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      BKPRAMEN      LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      SRAM4EN       LL_C2_AHB4_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C2_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C2->AHB4ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C2 AHB4 peripherals clock.
+  * @rmtoll AHB4ENR      GPIOAEN       LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOBEN       LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOCEN       LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIODEN       LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOEEN       LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOFEN       LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOGEN       LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOHEN       LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOIEN       LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOJEN       LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOKEN       LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      CRCEN         LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      BDMAEN        LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      ADC3EN        LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      HSEMEN        LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      BKPRAMEN      LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      SRAM4EN       LL_C2_AHB4_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB4_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->AHB4ENR, Periphs);
+}
+
+/**
+  * @brief  Enable C2 AHB4 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB4LPENR    GPIOALPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOBLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOCLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIODLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOELPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOFLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOGLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOHLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOILPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOJLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOKLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    CRCLPEN       LL_C2_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    BDMALPEN      LL_C2_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    ADC3LPEN      LL_C2_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    BKPRAMLPEN    LL_C2_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    SRAM4LPEN     LL_C2_AHB4_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB4_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->AHB4LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->AHB4LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C2 AHB4 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB4LPENR    GPIOALPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOBLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOCLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIODLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOELPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOFLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOGLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOHLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOILPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOJLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOKLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    CRCLPEN       LL_C2_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    BDMALPEN      LL_C2_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    ADC3LPEN      LL_C2_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    BKPRAMLPEN    LL_C2_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    SRAM4LPEN     LL_C2_AHB4_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB4_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->AHB4LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_APB3 APB3
+  * @{
+  */
+
+/**
+  * @brief  Enable C2 APB3 peripherals clock.
+  * @rmtoll APB3ENR      LTDCEN        LL_C2_APB3_GRP1_EnableClock\n
+  *         APB3ENR      DSIEN         LL_C2_APB3_GRP1_EnableClock\n
+  *         APB3ENR      WWDG1EN       LL_C2_APB3_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB3_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->APB3ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->APB3ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C2 APB3 peripheral clock is enabled or not
+  * @rmtoll APB3ENR      LTDCEN        LL_C2_APB3_GRP1_IsEnabledClock\n
+  *         APB3ENR      DSIEN         LL_C2_APB3_GRP1_IsEnabledClock\n
+  *         APB3ENR      WWDG1EN       LL_C2_APB3_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C2_APB3_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C2->APB3ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C2 APB3 peripherals clock.
+  * @rmtoll APB3ENR      LTDCEN        LL_C2_APB3_GRP1_DisableClock\n
+  *         APB3ENR      DSIEN         LL_C2_APB3_GRP1_DisableClock\n
+  *         APB3ENR      WWDG1EN       LL_C2_APB3_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB3_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->APB3ENR, Periphs);
+}
+
+/**
+  * @brief  Enable C2 APB3 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB3LPENR    LTDCLPEN      LL_C2_APB3_GRP1_EnableClockSleep\n
+  *         APB3LPENR    DSILPEN       LL_C2_APB3_GRP1_EnableClockSleep\n
+  *         APB3LPENR    WWDG1LPEN     LL_C2_APB3_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB3_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->APB3LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->APB3LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C2 APB3 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB3LPENR    LTDCLPEN      LL_C2_APB3_GRP1_DisableClockSleep\n
+  *         APB3LPENR    DSILPEN       LL_C2_APB3_GRP1_DisableClockSleep\n
+  *         APB3LPENR    WWDG1LPEN     LL_C2_APB3_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB3_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->APB3LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_APB1 APB1
+  * @{
+  */
+
+/**
+  * @brief  Enable C2 APB1 peripherals clock.
+  * @rmtoll APB1LENR     TIM2EN        LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM3EN        LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM4EN        LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM5EN        LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM6EN        LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM7EN        LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM12EN       LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM13EN       LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM14EN       LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     LPTIM1EN      LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     WWDG2EN       LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     SPI2EN        LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     SPI3EN        LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     SPDIFRXEN     LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     USART2EN      LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     USART3EN      LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     UART4EN       LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     UART5EN       LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     I2C1EN        LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     I2C2EN        LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     I2C3EN        LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     CECEN         LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     DAC12EN       LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     UART7EN       LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     UART8EN       LL_C2_APB1_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB1_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->APB1LENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->APB1LENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C2 APB1 peripheral clock is enabled or not
+  * @rmtoll APB1LENR     TIM2EN        LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM3EN        LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM4EN        LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM5EN        LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM6EN        LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM7EN        LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM12EN       LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM13EN       LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM14EN       LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     LPTIM1EN      LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     WWDG2EN       LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     SPI2EN        LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     SPI3EN        LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     SPDIFRXEN     LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     USART2EN      LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     USART3EN      LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     UART4EN       LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     UART5EN       LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     I2C1EN        LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     I2C2EN        LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     I2C3EN        LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     CECEN         LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     DAC12EN       LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     UART7EN       LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     UART8EN       LL_C2_APB1_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C2_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C2->APB1LENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C2 APB1 peripherals clock.
+  * @rmtoll APB1LENR     TIM2EN        LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM3EN        LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM4EN        LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM5EN        LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM6EN        LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM7EN        LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM12EN       LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM13EN       LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM14EN       LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     LPTIM1EN      LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     WWDG2EN       LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     SPI2EN        LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     SPI3EN        LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     SPDIFRXEN     LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     USART2EN      LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     USART3EN      LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     UART4EN       LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     UART5EN       LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     I2C1EN        LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     I2C2EN        LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     I2C3EN        LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     CECEN         LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     DAC12EN       LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     UART7EN       LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     UART8EN       LL_C2_APB1_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB1_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->APB1LENR, Periphs);
+}
+
+/**
+  * @brief  Enable C2 APB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB1LLPENR   TIM2LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM3LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM4LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM5LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM6LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM7LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM12LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM13LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM14LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   LPTIM1LPEN    LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   WWDG2LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   SPI2LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   SPI3LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   SPDIFRXLPEN   LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   USART2LPEN    LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   USART3LPEN    LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   UART4LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   UART5LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   I2C1LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   I2C2LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   I2C3LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   CECLPEN       LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   DAC12LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   UART7LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   UART8LPEN     LL_C2_APB1_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->APB1LLPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->APB1LLPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C2 APB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB1LLPENR   TIM2LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM3LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM4LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM5LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM6LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM7LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM12LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM13LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM14LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   LPTIM1LPEN    LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   WWDG2LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   SPI2LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   SPI3LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   SPDIFRXLPEN   LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   USART2LPEN    LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   USART3LPEN    LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   UART4LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   UART5LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   I2C1LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   I2C2LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   I2C3LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   CECLPEN       LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   DAC12LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   UART7LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   UART8LPEN     LL_C2_APB1_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->APB1LLPENR, Periphs);
+}
+
+/**
+  * @brief  Enable C2 APB1 peripherals clock.
+  * @rmtoll APB1HENR     CRSEN         LL_C2_APB1_GRP2_EnableClock\n
+  *         APB1HENR     SWPMIEN       LL_C2_APB1_GRP2_EnableClock\n
+  *         APB1HENR     OPAMPEN       LL_C2_APB1_GRP2_EnableClock\n
+  *         APB1HENR     MDIOSEN       LL_C2_APB1_GRP2_EnableClock\n
+  *         APB1HENR     FDCANEN       LL_C2_APB1_GRP2_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB1_GRP2_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->APB1HENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->APB1HENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C2 APB1 peripheral clock is enabled or not
+  * @rmtoll APB1HENR     CRSEN         LL_C2_APB1_GRP2_IsEnabledClock\n
+  *         APB1HENR     SWPMIEN       LL_C2_APB1_GRP2_IsEnabledClock\n
+  *         APB1HENR     OPAMPEN       LL_C2_APB1_GRP2_IsEnabledClock\n
+  *         APB1HENR     MDIOSEN       LL_C2_APB1_GRP2_IsEnabledClock\n
+  *         APB1HENR     FDCANEN       LL_C2_APB1_GRP2_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C2_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C2->APB1HENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C2 APB1 peripherals clock.
+  * @rmtoll APB1HENR     CRSEN         LL_C2_APB1_GRP2_DisableClock\n
+  *         APB1HENR     SWPMIEN       LL_C2_APB1_GRP2_DisableClock\n
+  *         APB1HENR     OPAMPEN       LL_C2_APB1_GRP2_DisableClock\n
+  *         APB1HENR     MDIOSEN       LL_C2_APB1_GRP2_DisableClock\n
+  *         APB1HENR     FDCANEN       LL_C2_APB1_GRP2_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB1_GRP2_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->APB1HENR, Periphs);
+}
+
+/**
+  * @brief  Enable C2 APB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB1HLPENR   CRSLPEN       LL_C2_APB1_GRP2_EnableClockSleep\n
+  *         APB1HLPENR   SWPMILPEN     LL_C2_APB1_GRP2_EnableClockSleep\n
+  *         APB1HLPENR   OPAMPLPEN     LL_C2_APB1_GRP2_EnableClockSleep\n
+  *         APB1HLPENR   MDIOSLPEN     LL_C2_APB1_GRP2_EnableClockSleep\n
+  *         APB1HLPENR   FDCANLPEN     LL_C2_APB1_GRP2_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB1_GRP2_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->APB1HLPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->APB1HLPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C2 APB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB1HLPENR   CRSLPEN       LL_C2_APB1_GRP2_DisableClockSleep\n
+  *         APB1HLPENR   SWPMILPEN     LL_C2_APB1_GRP2_DisableClockSleep\n
+  *         APB1HLPENR   OPAMPLPEN     LL_C2_APB1_GRP2_DisableClockSleep\n
+  *         APB1HLPENR   MDIOSLPEN     LL_C2_APB1_GRP2_DisableClockSleep\n
+  *         APB1HLPENR   FDCANLPEN     LL_C2_APB1_GRP2_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB1_GRP2_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->APB1HLPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_APB2 APB2
+  * @{
+  */
+
+/**
+  * @brief  Enable C2 APB2 peripherals clock.
+  * @rmtoll APB2ENR      TIM1EN        LL_C2_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM8EN        LL_C2_APB2_GRP1_EnableClock\n
+  *         APB2ENR      USART1EN      LL_C2_APB2_GRP1_EnableClock\n
+  *         APB2ENR      USART6EN      LL_C2_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SPI1EN        LL_C2_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SPI4EN        LL_C2_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM15EN       LL_C2_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM16EN       LL_C2_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM17EN       LL_C2_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SPI5EN        LL_C2_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SAI1EN        LL_C2_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SAI2EN        LL_C2_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SAI3EN        LL_C2_APB2_GRP1_EnableClock\n
+  *         APB2ENR      DFSDM1EN      LL_C2_APB2_GRP1_EnableClock\n
+  *         APB2ENR      HRTIMEN       LL_C2_APB2_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB2_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->APB2ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->APB2ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C2 APB2 peripheral clock is enabled or not
+  * @rmtoll APB2ENR      TIM1EN        LL_C2_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM8EN        LL_C2_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      USART1EN      LL_C2_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      USART6EN      LL_C2_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SPI1EN        LL_C2_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SPI4EN        LL_C2_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM15EN       LL_C2_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM16EN       LL_C2_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM17EN       LL_C2_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SPI5EN        LL_C2_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SAI1EN        LL_C2_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SAI2EN        LL_C2_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SAI3EN        LL_C2_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      DFSDM1EN      LL_C2_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      HRTIMEN       LL_C2_APB2_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C2_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C2->APB2ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C2 APB2 peripherals clock.
+  * @rmtoll APB2ENR      TIM1EN        LL_C2_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM8EN        LL_C2_APB2_GRP1_DisableClock\n
+  *         APB2ENR      USART1EN      LL_C2_APB2_GRP1_DisableClock\n
+  *         APB2ENR      USART6EN      LL_C2_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SPI1EN        LL_C2_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SPI4EN        LL_C2_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM15EN       LL_C2_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM16EN       LL_C2_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM17EN       LL_C2_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SPI5EN        LL_C2_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SAI1EN        LL_C2_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SAI2EN        LL_C2_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SAI3EN        LL_C2_APB2_GRP1_DisableClock\n
+  *         APB2ENR      DFSDM1EN      LL_C2_APB2_GRP1_DisableClock\n
+  *         APB2ENR      HRTIMEN       LL_C2_APB2_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB2_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->APB2ENR, Periphs);
+}
+
+/**
+  * @brief  Enable C2 APB2 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB2LPENR    TIM1LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    TIM8LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    USART1LPEN    LL_C2_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    USART6LPEN    LL_C2_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SPI1LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SPI4LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    TIM15LPEN     LL_C2_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    TIM16LPEN     LL_C2_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    TIM17LPEN     LL_C2_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SPI5LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SAI1LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SAI2LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SAI3LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    DFSDM1LPEN    LL_C2_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    HRTIMLPEN     LL_C2_APB2_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->APB2LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->APB2LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C2 APB2 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB2LPENR    TIM1LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    TIM8LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    USART1LPEN    LL_C2_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    USART6LPEN    LL_C2_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SPI1LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SPI4LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    TIM15LPEN     LL_C2_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    TIM16LPEN     LL_C2_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    TIM17LPEN     LL_C2_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SPI5LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SAI1LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SAI2LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SAI3LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    DFSDM1LPEN    LL_C2_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    HRTIMLPEN     LL_C2_APB2_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->APB2LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_APB4 APB4
+  * @{
+  */
+
+/**
+  * @brief  Enable C2 APB4 peripherals clock.
+  * @rmtoll APB4ENR      SYSCFGEN      LL_C2_APB4_GRP1_EnableClock\n
+  *         APB4ENR      LPUART1EN     LL_C2_APB4_GRP1_EnableClock\n
+  *         APB4ENR      SPI6EN        LL_C2_APB4_GRP1_EnableClock\n
+  *         APB4ENR      I2C4EN        LL_C2_APB4_GRP1_EnableClock\n
+  *         APB4ENR      LPTIM2EN      LL_C2_APB4_GRP1_EnableClock\n
+  *         APB4ENR      LPTIM3EN      LL_C2_APB4_GRP1_EnableClock\n
+  *         APB4ENR      LPTIM4EN      LL_C2_APB4_GRP1_EnableClock\n
+  *         APB4ENR      LPTIM5EN      LL_C2_APB4_GRP1_EnableClock\n
+  *         APB4ENR      COMP12EN      LL_C2_APB4_GRP1_EnableClock\n
+  *         APB4ENR      VREFEN        LL_C2_APB4_GRP1_EnableClock\n
+  *         APB4ENR      RTCAPBEN      LL_C2_APB4_GRP1_EnableClock\n
+  *         APB4ENR      SAI4EN        LL_C2_APB4_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB4_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->APB4ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->APB4ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C2 APB4 peripheral clock is enabled or not
+  * @rmtoll APB4ENR      SYSCFGEN      LL_C2_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      LPUART1EN     LL_C2_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      SPI6EN        LL_C2_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      I2C4EN        LL_C2_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      LPTIM2EN      LL_C2_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      LPTIM3EN      LL_C2_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      LPTIM4EN      LL_C2_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      LPTIM5EN      LL_C2_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      COMP12EN      LL_C2_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      VREFEN        LL_C2_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      RTCAPBEN      LL_C2_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      SAI4EN        LL_C2_APB4_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C2_APB4_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C2->APB4ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C2 APB4 peripherals clock.
+  * @rmtoll APB4ENR      SYSCFGEN      LL_C2_APB4_GRP1_DisableClock\n
+  *         APB4ENR      LPUART1EN     LL_C2_APB4_GRP1_DisableClock\n
+  *         APB4ENR      SPI6EN        LL_C2_APB4_GRP1_DisableClock\n
+  *         APB4ENR      I2C4EN        LL_C2_APB4_GRP1_DisableClock\n
+  *         APB4ENR      LPTIM2EN      LL_C2_APB4_GRP1_DisableClock\n
+  *         APB4ENR      LPTIM3EN      LL_C2_APB4_GRP1_DisableClock\n
+  *         APB4ENR      LPTIM4EN      LL_C2_APB4_GRP1_DisableClock\n
+  *         APB4ENR      LPTIM5EN      LL_C2_APB4_GRP1_DisableClock\n
+  *         APB4ENR      COMP12EN      LL_C2_APB4_GRP1_DisableClock\n
+  *         APB4ENR      VREFEN        LL_C2_APB4_GRP1_DisableClock\n
+  *         APB4ENR      RTCAPBEN      LL_C2_APB4_GRP1_DisableClock\n
+  *         APB4ENR      SAI4EN        LL_C2_APB4_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB4_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->APB4ENR, Periphs);
+}
+
+/**
+  * @brief  Enable C2 APB4 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB4LPENR    SYSCFGLPEN    LL_C2_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    LPUART1LPEN   LL_C2_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    SPI6LPEN      LL_C2_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    I2C4LPEN      LL_C2_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    LPTIM2LPEN    LL_C2_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    LPTIM3LPEN    LL_C2_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    LPTIM4LPEN    LL_C2_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    LPTIM5LPEN    LL_C2_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    COMP12LPEN    LL_C2_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    VREFLPEN      LL_C2_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    RTCAPBLPEN    LL_C2_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    SAI4LPEN      LL_C2_APB4_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB4_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->APB4LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->APB4LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C2 APB4 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB4LPENR    SYSCFGLPEN    LL_C2_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    LPUART1LPEN   LL_C2_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    SPI6LPEN      LL_C2_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    I2C4LPEN      LL_C2_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    LPTIM2LPEN    LL_C2_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    LPTIM3LPEN    LL_C2_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    LPTIM4LPEN    LL_C2_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    LPTIM5LPEN    LL_C2_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    COMP12LPEN    LL_C2_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    VREFLPEN      LL_C2_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    RTCAPBLPEN    LL_C2_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    SAI4LPEN      LL_C2_APB4_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB4_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->APB4LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+#endif /*DUAL_CORE*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(RCC) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_LL_BUS_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cortex.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cortex.h
new file mode 100644
index 00000000..c7363b9c
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cortex.h
@@ -0,0 +1,669 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_cortex.h
+  * @author  MCD Application Team
+  * @brief   Header file of CORTEX LL module.
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The LL CORTEX driver contains a set of generic APIs that can be
+    used by user:
+      (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
+          functions
+      (+) Low power mode configuration (SCB register of Cortex-MCU)
+      (+) MPU API to configure and enable regions
+      (+) API to access to MCU info (CPUID register)
+      (+) API to enable fault handler (SHCSR accesses)
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_LL_CORTEX_H
+#define STM32H7xx_LL_CORTEX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+/** @defgroup CORTEX_LL CORTEX
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
+  * @{
+  */
+
+/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
+  * @{
+  */
+#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8     0x00000000UL                /*!< AHB clock divided by 8 selected as SysTick clock source.*/
+#define LL_SYSTICK_CLKSOURCE_HCLK          SysTick_CTRL_CLKSOURCE_Msk  /*!< AHB clock selected as SysTick clock source. */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
+  * @{
+  */
+#define LL_HANDLER_FAULT_USG               SCB_SHCSR_USGFAULTENA_Msk              /*!< Usage fault */
+#define LL_HANDLER_FAULT_BUS               SCB_SHCSR_BUSFAULTENA_Msk              /*!< Bus fault */
+#define LL_HANDLER_FAULT_MEM               SCB_SHCSR_MEMFAULTENA_Msk              /*!< Memory management fault */
+/**
+  * @}
+  */
+
+#if __MPU_PRESENT
+
+/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
+  * @{
+  */
+#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE     0x00000000UL                                      /*!< Disable NMI and privileged SW access */
+#define LL_MPU_CTRL_HARDFAULT_NMI          MPU_CTRL_HFNMIENA_Msk                             /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
+#define LL_MPU_CTRL_PRIVILEGED_DEFAULT     MPU_CTRL_PRIVDEFENA_Msk                           /*!< Enable privileged software access to default memory map */
+#define LL_MPU_CTRL_HFNMI_PRIVDEF          (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_REGION MPU Region Number
+  * @{
+  */
+#define LL_MPU_REGION_NUMBER0              0x00UL /*!< REGION Number 0  */
+#define LL_MPU_REGION_NUMBER1              0x01UL /*!< REGION Number 1  */
+#define LL_MPU_REGION_NUMBER2              0x02UL /*!< REGION Number 2  */
+#define LL_MPU_REGION_NUMBER3              0x03UL /*!< REGION Number 3  */
+#define LL_MPU_REGION_NUMBER4              0x04UL /*!< REGION Number 4  */
+#define LL_MPU_REGION_NUMBER5              0x05UL /*!< REGION Number 5  */
+#define LL_MPU_REGION_NUMBER6              0x06UL /*!< REGION Number 6  */
+#define LL_MPU_REGION_NUMBER7              0x07UL /*!< REGION Number 7  */
+#if !defined(CORE_CM4)
+#define LL_MPU_REGION_NUMBER8              0x08UL /*!< REGION Number 8  */
+#define LL_MPU_REGION_NUMBER9              0x09UL /*!< REGION Number 9  */
+#define LL_MPU_REGION_NUMBER10             0x0AUL /*!< REGION Number 10 */
+#define LL_MPU_REGION_NUMBER11             0x0BUL /*!< REGION Number 11 */
+#define LL_MPU_REGION_NUMBER12             0x0CUL /*!< REGION Number 12 */
+#define LL_MPU_REGION_NUMBER13             0x0DUL /*!< REGION Number 13 */
+#define LL_MPU_REGION_NUMBER14             0x0EUL /*!< REGION Number 14 */
+#define LL_MPU_REGION_NUMBER15             0x0FUL /*!< REGION Number 15 */
+#endif /* !defined(CORE_CM4) */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
+  * @{
+  */
+#define LL_MPU_REGION_SIZE_32B             (0x04UL << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64B             (0x05UL << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128B            (0x06UL << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256B            (0x07UL << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512B            (0x08UL << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1KB             (0x09UL << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2KB             (0x0AUL << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4KB             (0x0BUL << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_8KB             (0x0CUL << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_16KB            (0x0DUL << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_32KB            (0x0EUL << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64KB            (0x0FUL << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128KB           (0x10UL << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256KB           (0x11UL << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512KB           (0x12UL << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1MB             (0x13UL << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2MB             (0x14UL << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4MB             (0x15UL << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_8MB             (0x16UL << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_16MB            (0x17UL << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_32MB            (0x18UL << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64MB            (0x19UL << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128MB           (0x1AUL << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256MB           (0x1BUL << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512MB           (0x1CUL << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1GB             (0x1DUL << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2GB             (0x1EUL << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4GB             (0x1FUL << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
+  * @{
+  */
+#define LL_MPU_REGION_NO_ACCESS            (0x00UL << MPU_RASR_AP_Pos) /*!< No access*/
+#define LL_MPU_REGION_PRIV_RW              (0x01UL << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
+#define LL_MPU_REGION_PRIV_RW_URO          (0x02UL << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
+#define LL_MPU_REGION_FULL_ACCESS          (0x03UL << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
+#define LL_MPU_REGION_PRIV_RO              (0x05UL << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
+#define LL_MPU_REGION_PRIV_RO_URO          (0x06UL << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
+  * @{
+  */
+#define LL_MPU_TEX_LEVEL0                  (0x00UL << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
+#define LL_MPU_TEX_LEVEL1                  (0x01UL << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
+#define LL_MPU_TEX_LEVEL2                  (0x02UL << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
+#define LL_MPU_TEX_LEVEL4                  (0x04UL << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
+  * @{
+  */
+#define LL_MPU_INSTRUCTION_ACCESS_ENABLE   0x00UL            /*!< Instruction fetches enabled */
+#define LL_MPU_INSTRUCTION_ACCESS_DISABLE  MPU_RASR_XN_Msk  /*!< Instruction fetches disabled*/
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
+  * @{
+  */
+#define LL_MPU_ACCESS_SHAREABLE            MPU_RASR_S_Msk   /*!< Shareable memory attribute */
+#define LL_MPU_ACCESS_NOT_SHAREABLE        0x00UL           /*!< Not Shareable memory attribute */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
+  * @{
+  */
+#define LL_MPU_ACCESS_CACHEABLE            MPU_RASR_C_Msk   /*!< Cacheable memory attribute */
+#define LL_MPU_ACCESS_NOT_CACHEABLE        0x00UL           /*!< Not Cacheable memory attribute */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
+  * @{
+  */
+#define LL_MPU_ACCESS_BUFFERABLE           MPU_RASR_B_Msk   /*!< Bufferable memory attribute */
+#define LL_MPU_ACCESS_NOT_BUFFERABLE       0x00UL           /*!< Not Bufferable memory attribute */
+/**
+  * @}
+  */
+#endif /* __MPU_PRESENT */
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
+  * @{
+  */
+
+/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
+  * @{
+  */
+
+/**
+  * @brief  This function checks if the Systick counter flag is active or not.
+  * @note   It can be used in timeout function on application side.
+  * @rmtoll STK_CTRL     COUNTFLAG     LL_SYSTICK_IsActiveCounterFlag
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
+{
+  return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configures the SysTick clock source
+  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_SetClkSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
+{
+  MODIFY_REG(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK, Source);
+}
+
+/**
+  * @brief  Get the SysTick clock source
+  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_GetClkSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
+  */
+__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
+{
+  return (uint32_t)(READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK));
+}
+
+/**
+  * @brief  Enable SysTick exception request
+  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_EnableIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
+{
+  SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+  * @brief  Disable SysTick exception request
+  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_DisableIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
+{
+  CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+  * @brief  Checks if the SYSTICK interrupt is enabled or disabled.
+  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_IsEnabledIT
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
+{
+  return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
+  * @{
+  */
+
+/**
+  * @brief  Processor uses sleep as its low power mode
+  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableSleep
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_EnableSleep(void)
+{
+  /* Clear SLEEPDEEP bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+}
+
+/**
+  * @brief  Processor uses deep sleep as its low power mode
+  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableDeepSleep
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
+{
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+}
+
+/**
+  * @brief  Configures sleep-on-exit when returning from Handler mode to Thread mode.
+  * @note   Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
+  *         empty main application.
+  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_EnableSleepOnExit
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
+{
+  /* Set SLEEPONEXIT bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
+}
+
+/**
+  * @brief  Do not sleep when returning to Thread mode.
+  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_DisableSleepOnExit
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
+{
+  /* Clear SLEEPONEXIT bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
+}
+
+/**
+  * @brief  Enabled events and all interrupts, including disabled interrupts, can wakeup the
+  *         processor.
+  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_EnableEventOnPend
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
+{
+  /* Set SEVEONPEND bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk);
+}
+
+/**
+  * @brief  Only enabled interrupts or events can wakeup the processor, disabled interrupts are
+  *         excluded
+  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_DisableEventOnPend
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
+{
+  /* Clear SEVEONPEND bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EF_HANDLER HANDLER
+  * @{
+  */
+
+/**
+  * @brief  Enable a fault in System handler control register (SHCSR)
+  * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_EnableFault
+  * @param  Fault This parameter can be a combination of the following values:
+  *         @arg @ref LL_HANDLER_FAULT_USG
+  *         @arg @ref LL_HANDLER_FAULT_BUS
+  *         @arg @ref LL_HANDLER_FAULT_MEM
+  * @retval None
+  */
+__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
+{
+  /* Enable the system handler fault */
+  SET_BIT(SCB->SHCSR, Fault);
+}
+
+/**
+  * @brief  Disable a fault in System handler control register (SHCSR)
+  * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_DisableFault
+  * @param  Fault This parameter can be a combination of the following values:
+  *         @arg @ref LL_HANDLER_FAULT_USG
+  *         @arg @ref LL_HANDLER_FAULT_BUS
+  *         @arg @ref LL_HANDLER_FAULT_MEM
+  * @retval None
+  */
+__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
+{
+  /* Disable the system handler fault */
+  CLEAR_BIT(SCB->SHCSR, Fault);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
+  * @{
+  */
+
+/**
+  * @brief  Get Implementer code
+  * @rmtoll SCB_CPUID    IMPLEMENTER   LL_CPUID_GetImplementer
+  * @retval Value should be equal to 0x41 for ARM
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
+}
+
+/**
+  * @brief  Get Variant number (The r value in the rnpn product revision identifier)
+  * @rmtoll SCB_CPUID    VARIANT       LL_CPUID_GetVariant
+  * @retval Value between 0 and 255 (0x0: revision 0)
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
+}
+
+/**
+  * @brief  Get Constant number
+  * @rmtoll SCB_CPUID    ARCHITECTURE  LL_CPUID_GetConstant
+  * @retval Value should be equal to 0xF for Cortex-M7 and Cortex-M4 devices
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
+}
+
+/**
+  * @brief  Get Part number
+  * @rmtoll SCB_CPUID    PARTNO        LL_CPUID_GetParNo
+  * @retval Value should be equal to 0xC27 for Cortex-M7 and equal to 0xC24 for Cortex-M4
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
+}
+
+/**
+  * @brief  Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
+  * @rmtoll SCB_CPUID    REVISION      LL_CPUID_GetRevision
+  * @retval Value between 0 and 255 (0x1: patch 1)
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
+}
+
+/**
+  * @}
+  */
+
+#if __MPU_PRESENT
+/** @defgroup CORTEX_LL_EF_MPU MPU
+  * @{
+  */
+
+/**
+  * @brief  Enable MPU with input options
+  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Enable
+  * @param  Options This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
+  *         @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
+  *         @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
+  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
+{
+  /* Enable the MPU*/
+  WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
+  /* Ensure MPU settings take effects */
+  __DSB();
+  /* Sequence instruction fetches using update settings */
+  __ISB();
+}
+
+/**
+  * @brief  Disable MPU
+  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_Disable(void)
+{
+  /* Make sure outstanding transfers are done */
+  __DMB();
+  /* Disable MPU*/
+  WRITE_REG(MPU->CTRL, 0U);
+}
+
+/**
+  * @brief  Check if MPU is enabled or not
+  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
+{
+  return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable a MPU region
+  * @rmtoll MPU_RASR     ENABLE        LL_MPU_EnableRegion
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  *         @arg @ref LL_MPU_REGION_NUMBER8
+  *         @arg @ref LL_MPU_REGION_NUMBER9
+  *         @arg @ref LL_MPU_REGION_NUMBER10
+  *         @arg @ref LL_MPU_REGION_NUMBER11
+  *         @arg @ref LL_MPU_REGION_NUMBER12
+  *         @arg @ref LL_MPU_REGION_NUMBER13
+  *         @arg @ref LL_MPU_REGION_NUMBER14
+  *         @arg @ref LL_MPU_REGION_NUMBER15
+  * @note   For cortex-M4 only 8 regions are available i.e only values from LL_MPU_REGION_NUMBER0 to LL_MPU_REGION_NUMBER7 are possible.
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
+{
+  /* Set Region number */
+  WRITE_REG(MPU->RNR, Region);
+  /* Enable the MPU region */
+  SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+  * @brief  Configure and enable a region
+  * @rmtoll MPU_RNR      REGION        LL_MPU_ConfigRegion\n
+  *         MPU_RBAR     REGION        LL_MPU_ConfigRegion\n
+  *         MPU_RBAR     ADDR          LL_MPU_ConfigRegion\n
+  *         MPU_RASR     XN            LL_MPU_ConfigRegion\n
+  *         MPU_RASR     AP            LL_MPU_ConfigRegion\n
+  *         MPU_RASR     S             LL_MPU_ConfigRegion\n
+  *         MPU_RASR     C             LL_MPU_ConfigRegion\n
+  *         MPU_RASR     B             LL_MPU_ConfigRegion\n
+  *         MPU_RASR     SIZE          LL_MPU_ConfigRegion
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  *         @arg @ref LL_MPU_REGION_NUMBER8
+  *         @arg @ref LL_MPU_REGION_NUMBER9
+  *         @arg @ref LL_MPU_REGION_NUMBER10
+  *         @arg @ref LL_MPU_REGION_NUMBER11
+  *         @arg @ref LL_MPU_REGION_NUMBER12
+  *         @arg @ref LL_MPU_REGION_NUMBER13
+  *         @arg @ref LL_MPU_REGION_NUMBER14
+  *         @arg @ref LL_MPU_REGION_NUMBER15
+  * @param  Address Value of region base address
+  * @param  SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
+  * @param  Attributes This parameter can be a combination of the following values:
+  *         @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
+  *           or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
+  *           or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
+  *           or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
+  *           or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
+  *           or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
+  *         @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
+  *           or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
+  *         @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
+  *         @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or  @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
+  *         @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
+  *         @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
+  *         @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
+  * @note   For cortex-M4 only 8 regions are available i.e only values from LL_MPU_REGION_NUMBER0 to LL_MPU_REGION_NUMBER7 are possible.
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
+{
+  /* Set Region number */
+  WRITE_REG(MPU->RNR, Region);
+  /* Set base address */
+  WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
+  /* Configure MPU */
+  WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos)));
+}
+
+/**
+  * @brief  Disable a region
+  * @rmtoll MPU_RNR      REGION        LL_MPU_DisableRegion\n
+  *         MPU_RASR     ENABLE        LL_MPU_DisableRegion
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  *         @arg @ref LL_MPU_REGION_NUMBER8
+  *         @arg @ref LL_MPU_REGION_NUMBER9
+  *         @arg @ref LL_MPU_REGION_NUMBER10
+  *         @arg @ref LL_MPU_REGION_NUMBER11
+  *         @arg @ref LL_MPU_REGION_NUMBER12
+  *         @arg @ref LL_MPU_REGION_NUMBER13
+  *         @arg @ref LL_MPU_REGION_NUMBER14
+  *         @arg @ref LL_MPU_REGION_NUMBER15
+  * @note   For cortex-M4 only 8 regions are available i.e only values from LL_MPU_REGION_NUMBER0 to LL_MPU_REGION_NUMBER7 are possible.
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
+{
+  /* Set Region number */
+  WRITE_REG(MPU->RNR, Region);
+  /* Disable the MPU region */
+  CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+  * @}
+  */
+
+#endif /* __MPU_PRESENT */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_LL_CORTEX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_crs.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_crs.h
new file mode 100644
index 00000000..40baadd1
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_crs.h
@@ -0,0 +1,783 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_crs.h
+  * @author  MCD Application Team
+  * @brief   Header file of CRS LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_LL_CRS_H
+#define STM32H7xx_LL_CRS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined(CRS)
+
+/** @defgroup CRS_LL CRS
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
+  * @{
+  */
+
+/** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_CRS_ReadReg function
+  * @{
+  */
+#define LL_CRS_ISR_SYNCOKF                 CRS_ISR_SYNCOKF
+#define LL_CRS_ISR_SYNCWARNF               CRS_ISR_SYNCWARNF
+#define LL_CRS_ISR_ERRF                    CRS_ISR_ERRF
+#define LL_CRS_ISR_ESYNCF                  CRS_ISR_ESYNCF
+#define LL_CRS_ISR_SYNCERR                 CRS_ISR_SYNCERR
+#define LL_CRS_ISR_SYNCMISS                CRS_ISR_SYNCMISS
+#define LL_CRS_ISR_TRIMOVF                 CRS_ISR_TRIMOVF
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_CRS_ReadReg and  LL_CRS_WriteReg functions
+  * @{
+  */
+#define LL_CRS_CR_SYNCOKIE                 CRS_CR_SYNCOKIE
+#define LL_CRS_CR_SYNCWARNIE               CRS_CR_SYNCWARNIE
+#define LL_CRS_CR_ERRIE                    CRS_CR_ERRIE
+#define LL_CRS_CR_ESYNCIE                  CRS_CR_ESYNCIE
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
+  * @{
+  */
+#define LL_CRS_SYNC_DIV_1                  0x00000000U                               /*!< Synchro Signal not divided (default) */
+#define LL_CRS_SYNC_DIV_2                  CRS_CFGR_SYNCDIV_0                        /*!< Synchro Signal divided by 2 */
+#define LL_CRS_SYNC_DIV_4                  CRS_CFGR_SYNCDIV_1                        /*!< Synchro Signal divided by 4 */
+#define LL_CRS_SYNC_DIV_8                  (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
+#define LL_CRS_SYNC_DIV_16                 CRS_CFGR_SYNCDIV_2                        /*!< Synchro Signal divided by 16 */
+#define LL_CRS_SYNC_DIV_32                 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
+#define LL_CRS_SYNC_DIV_64                 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
+#define LL_CRS_SYNC_DIV_128                CRS_CFGR_SYNCDIV                          /*!< Synchro Signal divided by 128 */
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
+  * @{
+  */
+#define LL_CRS_SYNC_SOURCE_GPIO            0x00000000U             /*!< Synchro Signal soucre GPIO */
+#define LL_CRS_SYNC_SOURCE_LSE             CRS_CFGR_SYNCSRC_0      /*!< Synchro Signal source LSE */
+#define LL_CRS_SYNC_SOURCE_USB             CRS_CFGR_SYNCSRC_1      /*!< Synchro Signal source USB SOF (default)*/
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
+  * @{
+  */
+#define LL_CRS_SYNC_POLARITY_RISING        0x00000000U           /*!< Synchro Active on rising edge (default) */
+#define LL_CRS_SYNC_POLARITY_FALLING       CRS_CFGR_SYNCPOL      /*!< Synchro Active on falling edge */
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
+  * @{
+  */
+#define LL_CRS_FREQ_ERROR_DIR_UP           0x00000000U         /*!< Upcounting direction, the actual frequency is above the target */
+#define LL_CRS_FREQ_ERROR_DIR_DOWN         CRS_ISR_FEDIR       /*!< Downcounting direction, the actual frequency is below the target */
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
+  * @{
+  */
+/**
+  * @brief Reset value of the RELOAD field
+  * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz
+  *       and a synchronization signal frequency of 1 kHz (SOF signal from USB)
+  */
+#define LL_CRS_RELOADVALUE_DEFAULT         0x0000BB7FU
+
+/**
+  * @brief Reset value of Frequency error limit.
+  */
+#define LL_CRS_ERRORLIMIT_DEFAULT          0x00000022U
+
+/**
+  * @brief Reset value of the HSI48 Calibration field
+  * @note The default value is 64, which corresponds to the middle of the trimming interval.
+  *       The trimming step is specified in the product datasheet.
+  *       A higher TRIM value corresponds to a higher output frequency.
+  */
+#define LL_CRS_HSI48CALIBRATION_DEFAULT    0x00000020U
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
+  * @{
+  */
+
+/** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in CRS register
+  * @param  __INSTANCE__ CRS Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in CRS register
+  * @param  __INSTANCE__ CRS Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload
+  * @{
+  */
+
+/**
+  * @brief  Macro to calculate reload value to be set in CRS register according to target and sync frequencies
+  * @note   The RELOAD value should be selected according to the ratio between
+  *         the target frequency and the frequency of the synchronization source after
+  *         prescaling. It is then decreased by one in order to reach the expected
+  *         synchronization on the zero value. The formula is the following:
+  *              RELOAD = (fTARGET / fSYNC) -1
+  * @param  __FTARGET__ Target frequency (value in Hz)
+  * @param  __FSYNC__ Synchronization signal frequency (value in Hz)
+  * @retval Reload value (in Hz)
+  */
+#define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
+  * @{
+  */
+
+/** @defgroup CRS_LL_EF_Configuration Configuration
+  * @{
+  */
+
+/**
+  * @brief  Enable Frequency error counter
+  * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
+  * @rmtoll CR           CEN           LL_CRS_EnableFreqErrorCounter
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_CEN);
+}
+
+/**
+  * @brief  Disable Frequency error counter
+  * @rmtoll CR           CEN           LL_CRS_DisableFreqErrorCounter
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)
+{
+  CLEAR_BIT(CRS->CR, CRS_CR_CEN);
+}
+
+/**
+  * @brief  Check if Frequency error counter is enabled or not
+  * @rmtoll CR           CEN           LL_CRS_IsEnabledFreqErrorCounter
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
+{
+  return ((READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Automatic trimming counter
+  * @rmtoll CR           AUTOTRIMEN    LL_CRS_EnableAutoTrimming
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
+}
+
+/**
+  * @brief  Disable Automatic trimming counter
+  * @rmtoll CR           AUTOTRIMEN    LL_CRS_DisableAutoTrimming
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)
+{
+  CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
+}
+
+/**
+  * @brief  Check if Automatic trimming is enabled or not
+  * @rmtoll CR           AUTOTRIMEN    LL_CRS_IsEnabledAutoTrimming
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)
+{
+  return ((READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set HSI48 oscillator smooth trimming
+  * @note   When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
+  * @rmtoll CR           TRIM          LL_CRS_SetHSI48SmoothTrimming
+  * @param  Value a number between Min_Data = 0 and Max_Data = 127
+  * @note   Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
+{
+  MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos);
+}
+
+/**
+  * @brief  Get HSI48 oscillator smooth trimming
+  * @rmtoll CR           TRIM          LL_CRS_GetHSI48SmoothTrimming
+  * @retval a number between Min_Data = 0 and Max_Data = 127
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
+{
+  return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
+}
+
+/**
+  * @brief  Set counter reload value
+  * @rmtoll CFGR         RELOAD        LL_CRS_SetReloadCounter
+  * @param  Value a number between Min_Data = 0 and Max_Data = 0xFFFF
+  * @note   Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT
+  *         Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)
+{
+  MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
+}
+
+/**
+  * @brief  Get counter reload value
+  * @rmtoll CFGR         RELOAD        LL_CRS_GetReloadCounter
+  * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)
+{
+  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
+}
+
+/**
+  * @brief  Set frequency error limit
+  * @rmtoll CFGR         FELIM         LL_CRS_SetFreqErrorLimit
+  * @param  Value a number between Min_Data = 0 and Max_Data = 255
+  * @note   Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
+{
+  MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos);
+}
+
+/**
+  * @brief  Get frequency error limit
+  * @rmtoll CFGR         FELIM         LL_CRS_GetFreqErrorLimit
+  * @retval A number between Min_Data = 0 and Max_Data = 255
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
+{
+  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos);
+}
+
+/**
+  * @brief  Set division factor for SYNC signal
+  * @rmtoll CFGR         SYNCDIV       LL_CRS_SetSyncDivider
+  * @param  Divider This parameter can be one of the following values:
+  *         @arg @ref LL_CRS_SYNC_DIV_1
+  *         @arg @ref LL_CRS_SYNC_DIV_2
+  *         @arg @ref LL_CRS_SYNC_DIV_4
+  *         @arg @ref LL_CRS_SYNC_DIV_8
+  *         @arg @ref LL_CRS_SYNC_DIV_16
+  *         @arg @ref LL_CRS_SYNC_DIV_32
+  *         @arg @ref LL_CRS_SYNC_DIV_64
+  *         @arg @ref LL_CRS_SYNC_DIV_128
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)
+{
+  MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
+}
+
+/**
+  * @brief  Get division factor for SYNC signal
+  * @rmtoll CFGR         SYNCDIV       LL_CRS_GetSyncDivider
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_CRS_SYNC_DIV_1
+  *         @arg @ref LL_CRS_SYNC_DIV_2
+  *         @arg @ref LL_CRS_SYNC_DIV_4
+  *         @arg @ref LL_CRS_SYNC_DIV_8
+  *         @arg @ref LL_CRS_SYNC_DIV_16
+  *         @arg @ref LL_CRS_SYNC_DIV_32
+  *         @arg @ref LL_CRS_SYNC_DIV_64
+  *         @arg @ref LL_CRS_SYNC_DIV_128
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)
+{
+  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
+}
+
+/**
+  * @brief  Set SYNC signal source
+  * @rmtoll CFGR         SYNCSRC       LL_CRS_SetSyncSignalSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO
+  *         @arg @ref LL_CRS_SYNC_SOURCE_LSE
+  *         @arg @ref LL_CRS_SYNC_SOURCE_USB
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)
+{
+  MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
+}
+
+/**
+  * @brief  Get SYNC signal source
+  * @rmtoll CFGR         SYNCSRC       LL_CRS_GetSyncSignalSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO
+  *         @arg @ref LL_CRS_SYNC_SOURCE_LSE
+  *         @arg @ref LL_CRS_SYNC_SOURCE_USB
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)
+{
+  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
+}
+
+/**
+  * @brief  Set input polarity for the SYNC signal source
+  * @rmtoll CFGR         SYNCPOL       LL_CRS_SetSyncPolarity
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_CRS_SYNC_POLARITY_RISING
+  *         @arg @ref LL_CRS_SYNC_POLARITY_FALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)
+{
+  MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
+}
+
+/**
+  * @brief  Get input polarity for the SYNC signal source
+  * @rmtoll CFGR         SYNCPOL       LL_CRS_GetSyncPolarity
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_CRS_SYNC_POLARITY_RISING
+  *         @arg @ref LL_CRS_SYNC_POLARITY_FALLING
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
+{
+  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
+}
+
+/**
+  * @brief  Configure CRS for the synchronization
+  * @rmtoll CR           TRIM          LL_CRS_ConfigSynchronization\n
+  *         CFGR         RELOAD        LL_CRS_ConfigSynchronization\n
+  *         CFGR         FELIM         LL_CRS_ConfigSynchronization\n
+  *         CFGR         SYNCDIV       LL_CRS_ConfigSynchronization\n
+  *         CFGR         SYNCSRC       LL_CRS_ConfigSynchronization\n
+  *         CFGR         SYNCPOL       LL_CRS_ConfigSynchronization
+  * @param  HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63
+  * @param  ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF
+  * @param  ReloadValue a number between Min_Data = 0 and Max_Data = 255
+  * @param  Settings This parameter can be a combination of the following values:
+  *         @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8
+  *              or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128
+  *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB
+  *         @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings)
+{
+  MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue);
+  MODIFY_REG(CRS->CFGR,
+             CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
+             ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EF_CRS_Management CRS_Management
+  * @{
+  */
+
+/**
+  * @brief  Generate software SYNC event
+  * @rmtoll CR           SWSYNC        LL_CRS_GenerateEvent_SWSYNC
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_SWSYNC);
+}
+
+/**
+  * @brief  Get the frequency error direction latched in the time of the last
+  * SYNC event
+  * @rmtoll ISR          FEDIR         LL_CRS_GetFreqErrorDirection
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
+  *         @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)
+{
+  return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
+}
+
+/**
+  * @brief  Get the frequency error counter value latched in the time of the last SYNC event
+  * @rmtoll ISR          FECAP         LL_CRS_GetFreqErrorCapture
+  * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
+{
+  return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Check if SYNC event OK signal occurred or not
+  * @rmtoll ISR          SYNCOKF       LL_CRS_IsActiveFlag_SYNCOK
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
+{
+  return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if SYNC warning signal occurred or not
+  * @rmtoll ISR          SYNCWARNF     LL_CRS_IsActiveFlag_SYNCWARN
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
+{
+  return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Synchronization or trimming error signal occurred or not
+  * @rmtoll ISR          ERRF          LL_CRS_IsActiveFlag_ERR
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)
+{
+  return ((READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Expected SYNC signal occurred or not
+  * @rmtoll ISR          ESYNCF        LL_CRS_IsActiveFlag_ESYNC
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
+{
+  return ((READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if SYNC error signal occurred or not
+  * @rmtoll ISR          SYNCERR       LL_CRS_IsActiveFlag_SYNCERR
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
+{
+  return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if SYNC missed error signal occurred or not
+  * @rmtoll ISR          SYNCMISS      LL_CRS_IsActiveFlag_SYNCMISS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
+{
+  return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Trimming overflow or underflow occurred or not
+  * @rmtoll ISR          TRIMOVF       LL_CRS_IsActiveFlag_TRIMOVF
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
+{
+  return ((READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the SYNC event OK flag
+  * @rmtoll ICR          SYNCOKC       LL_CRS_ClearFlag_SYNCOK
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)
+{
+  WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
+}
+
+/**
+  * @brief  Clear the  SYNC warning flag
+  * @rmtoll ICR          SYNCWARNC     LL_CRS_ClearFlag_SYNCWARN
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)
+{
+  WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
+}
+
+/**
+  * @brief  Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
+  * the ERR flag
+  * @rmtoll ICR          ERRC          LL_CRS_ClearFlag_ERR
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)
+{
+  WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
+}
+
+/**
+  * @brief  Clear Expected SYNC flag
+  * @rmtoll ICR          ESYNCC        LL_CRS_ClearFlag_ESYNC
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)
+{
+  WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable SYNC event OK interrupt
+  * @rmtoll CR           SYNCOKIE      LL_CRS_EnableIT_SYNCOK
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
+}
+
+/**
+  * @brief  Disable SYNC event OK interrupt
+  * @rmtoll CR           SYNCOKIE      LL_CRS_DisableIT_SYNCOK
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)
+{
+  CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
+}
+
+/**
+  * @brief  Check if SYNC event OK interrupt is enabled or not
+  * @rmtoll CR           SYNCOKIE      LL_CRS_IsEnabledIT_SYNCOK
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
+{
+  return ((READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable SYNC warning interrupt
+  * @rmtoll CR           SYNCWARNIE    LL_CRS_EnableIT_SYNCWARN
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
+}
+
+/**
+  * @brief  Disable SYNC warning interrupt
+  * @rmtoll CR           SYNCWARNIE    LL_CRS_DisableIT_SYNCWARN
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)
+{
+  CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
+}
+
+/**
+  * @brief  Check if SYNC warning interrupt is enabled or not
+  * @rmtoll CR           SYNCWARNIE    LL_CRS_IsEnabledIT_SYNCWARN
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
+{
+  return ((READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Synchronization or trimming error interrupt
+  * @rmtoll CR           ERRIE         LL_CRS_EnableIT_ERR
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_EnableIT_ERR(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_ERRIE);
+}
+
+/**
+  * @brief  Disable Synchronization or trimming error interrupt
+  * @rmtoll CR           ERRIE         LL_CRS_DisableIT_ERR
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_DisableIT_ERR(void)
+{
+  CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
+}
+
+/**
+  * @brief  Check if Synchronization or trimming error interrupt is enabled or not
+  * @rmtoll CR           ERRIE         LL_CRS_IsEnabledIT_ERR
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)
+{
+  return ((READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Expected SYNC interrupt
+  * @rmtoll CR           ESYNCIE       LL_CRS_EnableIT_ESYNC
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
+}
+
+/**
+  * @brief  Disable Expected SYNC interrupt
+  * @rmtoll CR           ESYNCIE       LL_CRS_DisableIT_ESYNC
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)
+{
+  CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
+}
+
+/**
+  * @brief  Check if Expected SYNC interrupt is enabled or not
+  * @rmtoll CR           ESYNCIE       LL_CRS_IsEnabledIT_ESYNC
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
+{
+  return ((READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_CRS_DeInit(void);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(CRS) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_LL_CRS_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma.h
new file mode 100644
index 00000000..342f7d4e
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma.h
@@ -0,0 +1,3246 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_dma.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMA LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_LL_DMA_H
+#define STM32H7xx_LL_DMA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+#include "stm32h7xx_ll_dmamux.h"
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined (DMA1) || defined (DMA2)
+
+/** @defgroup DMA_LL DMA
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup DMA_LL_Private_Variables DMA Private Variables
+  * @{
+  */
+/* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */
+static const uint8_t LL_DMA_STR_OFFSET_TAB[] =
+{
+  (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE)
+};
+
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+
+/**
+  * @brief  Helper macro to convert DMA Instance DMAx into DMAMUX channel
+  * @note   DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7.
+  *         DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7.
+  * @param  __DMA_INSTANCE__ DMAx
+  * @retval Channel_Offset (LL_DMAMUX_CHANNEL_8 or 0).
+  */
+#define LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__)   \
+(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0UL : 8UL)
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
+  * @{
+  */
+typedef struct
+{
+  uint32_t PeriphOrM2MSrcAddress;  /*!< Specifies the peripheral base address for DMA transfer
+                                        or as Source base address in case of memory to memory transfer direction.
+
+                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
+
+  uint32_t MemoryOrM2MDstAddress;  /*!< Specifies the memory base address for DMA transfer
+                                        or as Destination base address in case of memory to memory transfer direction.
+
+                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
+
+  uint32_t Direction;              /*!< Specifies if the data will be transferred from memory to peripheral,
+                                        from memory to memory or from peripheral to memory.
+                                        This parameter can be a value of @ref DMA_LL_EC_DIRECTION
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
+
+  uint32_t Mode;                   /*!< Specifies the normal or circular operation mode.
+                                        This parameter can be a value of @ref DMA_LL_EC_MODE
+                                        @note The circular buffer mode cannot be used if the memory to memory
+                                              data transfer direction is configured on the selected Stream
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
+
+  uint32_t PeriphOrM2MSrcIncMode;  /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
+                                        is incremented or not.
+                                        This parameter can be a value of @ref DMA_LL_EC_PERIPH
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
+
+  uint32_t MemoryOrM2MDstIncMode;  /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
+                                        is incremented or not.
+                                        This parameter can be a value of @ref DMA_LL_EC_MEMORY
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
+
+  uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
+                                        in case of memory to memory transfer direction.
+                                        This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
+
+  uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
+                                        in case of memory to memory transfer direction.
+                                        This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
+
+  uint32_t NbData;                 /*!< Specifies the number of data to transfer, in data unit.
+                                        The data unit is equal to the source buffer configuration set in PeripheralSize
+                                        or MemorySize parameters depending in the transfer direction.
+                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
+
+  uint32_t PeriphRequest;          /*!< Specifies the peripheral request.
+                                        This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
+
+  uint32_t Priority;               /*!< Specifies the channel priority level.
+                                        This parameter can be a value of @ref DMA_LL_EC_PRIORITY
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */
+
+  uint32_t FIFOMode;               /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
+                                        This parameter can be a value of @ref DMA_LL_FIFOMODE
+                                        @note The Direct mode (FIFO mode disabled) cannot be used if the
+                                        memory-to-memory data transfer is configured on the selected stream
+
+                                        This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */
+
+  uint32_t FIFOThreshold;          /*!< Specifies the FIFO threshold level.
+                                        This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */
+
+  uint32_t MemBurst;               /*!< Specifies the Burst transfer configuration for the memory transfers.
+                                        It specifies the amount of data to be transferred in a single non interruptible
+                                        transaction.
+                                        This parameter can be a value of @ref DMA_LL_EC_MBURST
+                                        @note The burst mode is possible only if the address Increment mode is enabled.
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */
+
+  uint32_t PeriphBurst;            /*!< Specifies the Burst transfer configuration for the peripheral transfers.
+                                        It specifies the amount of data to be transferred in a single non interruptible
+                                        transaction.
+                                        This parameter can be a value of @ref DMA_LL_EC_PBURST
+                                        @note The burst mode is possible only if the address Increment mode is enabled.
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */
+
+} LL_DMA_InitTypeDef;
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
+  * @{
+  */
+
+/** @defgroup DMA_LL_EC_STREAM STREAM
+  * @{
+  */
+#define LL_DMA_STREAM_0                   0x00000000U
+#define LL_DMA_STREAM_1                   0x00000001U
+#define LL_DMA_STREAM_2                   0x00000002U
+#define LL_DMA_STREAM_3                   0x00000003U
+#define LL_DMA_STREAM_4                   0x00000004U
+#define LL_DMA_STREAM_5                   0x00000005U
+#define LL_DMA_STREAM_6                   0x00000006U
+#define LL_DMA_STREAM_7                   0x00000007U
+#define LL_DMA_STREAM_ALL                 0xFFFF0000U
+/**
+  * @}
+  */
+
+
+/** @defgroup DMA_LL_EC_DIRECTION DIRECTION
+  * @{
+  */
+#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U               /*!< Peripheral to memory direction */
+#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0            /*!< Memory to peripheral direction */
+#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1            /*!< Memory to memory direction     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_MODE MODE
+  * @{
+  */
+#define LL_DMA_MODE_NORMAL                0x00000000U               /*!< Normal Mode                  */
+#define LL_DMA_MODE_CIRCULAR              DMA_SxCR_CIRC             /*!< Circular Mode                */
+#define LL_DMA_MODE_PFCTRL                DMA_SxCR_PFCTRL           /*!< Peripheral flow control mode */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE
+  * @{
+  */
+#define LL_DMA_DOUBLEBUFFER_MODE_DISABLE  0x00000000U               /*!< Disable double buffering mode */
+#define LL_DMA_DOUBLEBUFFER_MODE_ENABLE   DMA_SxCR_DBM              /*!< Enable double buffering mode  */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_PERIPH PERIPH
+  * @{
+  */
+#define LL_DMA_PERIPH_NOINCREMENT         0x00000000U               /*!< Peripheral increment mode Disable */
+#define LL_DMA_PERIPH_INCREMENT           DMA_SxCR_PINC             /*!< Peripheral increment mode Enable  */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_MEMORY MEMORY
+  * @{
+  */
+#define LL_DMA_MEMORY_NOINCREMENT         0x00000000U               /*!< Memory increment mode Disable */
+#define LL_DMA_MEMORY_INCREMENT           DMA_SxCR_MINC             /*!< Memory increment mode Enable  */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN
+  * @{
+  */
+#define LL_DMA_PDATAALIGN_BYTE            0x00000000U               /*!< Peripheral data alignment : Byte     */
+#define LL_DMA_PDATAALIGN_HALFWORD        DMA_SxCR_PSIZE_0          /*!< Peripheral data alignment : HalfWord */
+#define LL_DMA_PDATAALIGN_WORD            DMA_SxCR_PSIZE_1          /*!< Peripheral data alignment : Word     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN
+  * @{
+  */
+#define LL_DMA_MDATAALIGN_BYTE            0x00000000U               /*!< Memory data alignment : Byte     */
+#define LL_DMA_MDATAALIGN_HALFWORD        DMA_SxCR_MSIZE_0          /*!< Memory data alignment : HalfWord */
+#define LL_DMA_MDATAALIGN_WORD            DMA_SxCR_MSIZE_1          /*!< Memory data alignment : Word     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE
+  * @{
+  */
+#define LL_DMA_OFFSETSIZE_PSIZE           0x00000000U               /*!< Peripheral increment offset size is linked to the PSIZE           */
+#define LL_DMA_OFFSETSIZE_FIXEDTO4        DMA_SxCR_PINCOS           /*!< Peripheral increment offset size is fixed to 4 (32-bit alignment) */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_PRIORITY PRIORITY
+  * @{
+  */
+#define LL_DMA_PRIORITY_LOW               0x00000000U               /*!< Priority level : Low       */
+#define LL_DMA_PRIORITY_MEDIUM            DMA_SxCR_PL_0             /*!< Priority level : Medium    */
+#define LL_DMA_PRIORITY_HIGH              DMA_SxCR_PL_1             /*!< Priority level : High      */
+#define LL_DMA_PRIORITY_VERYHIGH          DMA_SxCR_PL               /*!< Priority level : Very_High */
+/**
+  * @}
+  */
+
+
+/** @defgroup DMA_LL_EC_MBURST MBURST
+  * @{
+  */
+#define LL_DMA_MBURST_SINGLE              0x00000000U                             /*!< Memory burst single transfer configuration      */
+#define LL_DMA_MBURST_INC4                DMA_SxCR_MBURST_0                       /*!< Memory burst of 4 beats transfer configuration  */
+#define LL_DMA_MBURST_INC8                DMA_SxCR_MBURST_1                       /*!< Memory burst of 8 beats transfer configuration  */
+#define LL_DMA_MBURST_INC16               (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst of 16 beats transfer configuration */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_PBURST PBURST
+  * @{
+  */
+#define LL_DMA_PBURST_SINGLE              0x00000000U                             /*!< Peripheral burst single transfer configuration      */
+#define LL_DMA_PBURST_INC4                DMA_SxCR_PBURST_0                       /*!< Peripheral burst of 4 beats transfer configuration  */
+#define LL_DMA_PBURST_INC8                DMA_SxCR_PBURST_1                       /*!< Peripheral burst of 8 beats transfer configuration  */
+#define LL_DMA_PBURST_INC16               (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral burst of 16 beats transfer configuration */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE
+  * @{
+  */
+#define LL_DMA_FIFOMODE_DISABLE           0x00000000U                             /*!< FIFO mode disable (direct mode is enabled) */
+#define LL_DMA_FIFOMODE_ENABLE            DMA_SxFCR_DMDIS                         /*!< FIFO mode enable                           */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0
+  * @{
+  */
+#define LL_DMA_FIFOSTATUS_0_25            0x00000000U                             /*!< 0 < fifo_level < 1/4    */
+#define LL_DMA_FIFOSTATUS_25_50           DMA_SxFCR_FS_0                          /*!< 1/4 < fifo_level < 1/2  */
+#define LL_DMA_FIFOSTATUS_50_75           DMA_SxFCR_FS_1                          /*!< 1/2 < fifo_level < 3/4  */
+#define LL_DMA_FIFOSTATUS_75_100          (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0)       /*!< 3/4 < fifo_level < full */
+#define LL_DMA_FIFOSTATUS_EMPTY           DMA_SxFCR_FS_2                          /*!< FIFO is empty           */
+#define LL_DMA_FIFOSTATUS_FULL            (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0)       /*!< FIFO is full            */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD
+  * @{
+  */
+#define LL_DMA_FIFOTHRESHOLD_1_4          0x00000000U                             /*!< FIFO threshold 1 quart full configuration  */
+#define LL_DMA_FIFOTHRESHOLD_1_2          DMA_SxFCR_FTH_0                         /*!< FIFO threshold half full configuration     */
+#define LL_DMA_FIFOTHRESHOLD_3_4          DMA_SxFCR_FTH_1                         /*!< FIFO threshold 3 quarts full configuration */
+#define LL_DMA_FIFOTHRESHOLD_FULL         DMA_SxFCR_FTH                           /*!< FIFO threshold full configuration          */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
+  * @{
+  */
+#define LL_DMA_CURRENTTARGETMEM0          0x00000000U                             /*!< Set CurrentTarget Memory to Memory 0  */
+#define LL_DMA_CURRENTTARGETMEM1          DMA_SxCR_CT                             /*!< Set CurrentTarget Memory to Memory 1  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
+  * @{
+  */
+
+/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
+  * @{
+  */
+/**
+  * @brief  Write a value in DMA register
+  * @param  __INSTANCE__ DMA Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in DMA register
+  * @param  __INSTANCE__ DMA Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy
+  * @{
+  */
+/**
+  * @brief  Convert DMAx_Streamy into DMAx
+  * @param  __STREAM_INSTANCE__ DMAx_Streamy
+  * @retval DMAx
+  */
+#define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__)   \
+(((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ?  DMA2 : DMA1)
+
+/**
+  * @brief  Convert DMAx_Streamy into LL_DMA_STREAM_y
+  * @param  __STREAM_INSTANCE__ DMAx_Streamy
+  * @retval LL_DMA_STREAM_y
+  */
+#define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__)   \
+(((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \
+ LL_DMA_STREAM_7)
+
+/**
+  * @brief  Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy
+  * @param  __DMA_INSTANCE__ DMAx
+  * @param  __STREAM__ LL_DMA_STREAM_y
+  * @retval DMAx_Streamy
+  */
+#define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__)   \
+((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \
+ DMA2_Stream7)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
+ * @{
+ */
+
+/** @defgroup DMA_LL_EF_Configuration Configuration
+  * @{
+  */
+/**
+  * @brief Enable DMA stream.
+  * @rmtoll CR          EN            LL_DMA_EnableStream
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN);
+}
+
+/**
+  * @brief Disable DMA stream.
+  * @rmtoll CR          EN            LL_DMA_DisableStream
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN);
+}
+
+/**
+  * @brief Check if DMA stream is enabled or disabled.
+  * @rmtoll CR          EN            LL_DMA_IsEnabledStream
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure all parameters linked to DMA transfer.
+  * @rmtoll CR          DIR           LL_DMA_ConfigTransfer\n
+  *         CR          CIRC          LL_DMA_ConfigTransfer\n
+  *         CR          PINC          LL_DMA_ConfigTransfer\n
+  *         CR          MINC          LL_DMA_ConfigTransfer\n
+  *         CR          PSIZE         LL_DMA_ConfigTransfer\n
+  *         CR          MSIZE         LL_DMA_ConfigTransfer\n
+  *         CR          PL            LL_DMA_ConfigTransfer\n
+  *         CR          PFCTRL        LL_DMA_ConfigTransfer
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Configuration This parameter must be a combination of all the following values:
+  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+  *         @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR  or @ref LL_DMA_MODE_PFCTRL
+  *         @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
+  *         @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
+  *         @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
+  *         @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
+  *         @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
+  *@retval None
+  */
+__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR,
+             DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL,
+             Configuration);
+}
+
+/**
+  * @brief Set Data transfer direction (read from peripheral or from memory).
+  * @rmtoll CR          DIR           LL_DMA_SetDataTransferDirection
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Direction This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Direction)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DIR, Direction);
+}
+
+/**
+  * @brief Get Data transfer direction (read from peripheral or from memory).
+  * @rmtoll CR          DIR           LL_DMA_GetDataTransferDirection
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DIR));
+}
+
+/**
+  * @brief Set DMA mode normal, circular or peripheral flow control.
+  * @rmtoll CR          CIRC           LL_DMA_SetMode\n
+  *         CR          PFCTRL         LL_DMA_SetMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_MODE_NORMAL
+  *         @arg @ref LL_DMA_MODE_CIRCULAR
+  *         @arg @ref LL_DMA_MODE_PFCTRL
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL, Mode);
+}
+
+/**
+  * @brief Get DMA mode normal, circular or peripheral flow control.
+  * @rmtoll CR          CIRC           LL_DMA_GetMode\n
+  *         CR          PFCTRL         LL_DMA_GetMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_MODE_NORMAL
+  *         @arg @ref LL_DMA_MODE_CIRCULAR
+  *         @arg @ref LL_DMA_MODE_PFCTRL
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL));
+}
+
+/**
+  * @brief Set Peripheral increment mode.
+  * @rmtoll CR          PINC           LL_DMA_SetPeriphIncMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  IncrementMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
+  *         @arg @ref LL_DMA_PERIPH_INCREMENT
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINC, IncrementMode);
+}
+
+/**
+  * @brief Get Peripheral increment mode.
+  * @rmtoll CR          PINC           LL_DMA_GetPeriphIncMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
+  *         @arg @ref LL_DMA_PERIPH_INCREMENT
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINC));
+}
+
+/**
+  * @brief Set Memory increment mode.
+  * @rmtoll CR          MINC           LL_DMA_SetMemoryIncMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  IncrementMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
+  *         @arg @ref LL_DMA_MEMORY_INCREMENT
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MINC, IncrementMode);
+}
+
+/**
+  * @brief Get Memory increment mode.
+  * @rmtoll CR          MINC           LL_DMA_GetMemoryIncMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
+  *         @arg @ref LL_DMA_MEMORY_INCREMENT
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MINC));
+}
+
+/**
+  * @brief Set Peripheral size.
+  * @rmtoll CR          PSIZE           LL_DMA_SetPeriphSize
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Size This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_PDATAALIGN_BYTE
+  *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
+  *         @arg @ref LL_DMA_PDATAALIGN_WORD
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Size)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PSIZE, Size);
+}
+
+/**
+  * @brief Get Peripheral size.
+  * @rmtoll CR          PSIZE           LL_DMA_GetPeriphSize
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_PDATAALIGN_BYTE
+  *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
+  *         @arg @ref LL_DMA_PDATAALIGN_WORD
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PSIZE));
+}
+
+/**
+  * @brief Set Memory size.
+  * @rmtoll CR          MSIZE           LL_DMA_SetMemorySize
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Size This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_MDATAALIGN_BYTE
+  *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
+  *         @arg @ref LL_DMA_MDATAALIGN_WORD
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Size)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MSIZE, Size);
+}
+
+/**
+  * @brief Get Memory size.
+  * @rmtoll CR          MSIZE           LL_DMA_GetMemorySize
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_MDATAALIGN_BYTE
+  *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
+  *         @arg @ref LL_DMA_MDATAALIGN_WORD
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MSIZE));
+}
+
+/**
+  * @brief Set Peripheral increment offset size.
+  * @rmtoll CR          PINCOS           LL_DMA_SetIncOffsetSize
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  OffsetSize This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_OFFSETSIZE_PSIZE
+  *         @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINCOS, OffsetSize);
+}
+
+/**
+  * @brief Get Peripheral increment offset size.
+  * @rmtoll CR          PINCOS           LL_DMA_GetIncOffsetSize
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_OFFSETSIZE_PSIZE
+  *         @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINCOS));
+}
+
+/**
+  * @brief Set Stream priority level.
+  * @rmtoll CR          PL           LL_DMA_SetStreamPriorityLevel
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Priority This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_PRIORITY_LOW
+  *         @arg @ref LL_DMA_PRIORITY_MEDIUM
+  *         @arg @ref LL_DMA_PRIORITY_HIGH
+  *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Priority)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PL, Priority);
+}
+
+/**
+  * @brief Get Stream priority level.
+  * @rmtoll CR          PL           LL_DMA_GetStreamPriorityLevel
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_PRIORITY_LOW
+  *         @arg @ref LL_DMA_PRIORITY_MEDIUM
+  *         @arg @ref LL_DMA_PRIORITY_HIGH
+  *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PL));
+}
+
+/**
+  * @brief Enable DMA stream bufferable transfer.
+  * @rmtoll CR          TRBUFF            LL_DMA_EnableBufferableTransfer
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableBufferableTransfer(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TRBUFF);
+}
+
+/**
+  * @brief Disable DMA stream bufferable transfer.
+  * @rmtoll CR          TRBUFF            LL_DMA_DisableBufferableTransfer
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableBufferableTransfer(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TRBUFF);
+}
+
+/**
+  * @brief Set Number of data to transfer.
+  * @rmtoll NDTR          NDT           LL_DMA_SetDataLength
+  * @note   This action has no effect if
+  *         stream is enabled.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  NbData Between 0 to 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t NbData)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->NDTR, DMA_SxNDT, NbData);
+}
+
+/**
+  * @brief Get Number of data to transfer.
+  * @rmtoll NDTR          NDT           LL_DMA_GetDataLength
+  * @note   Once the stream is enabled, the return value indicate the
+  *         remaining bytes to be transmitted.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Between 0 to 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->NDTR, DMA_SxNDT));
+}
+/**
+  * @brief  Set DMA request for DMA Streams on DMAMUX Channel x.
+  * @note   DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7.
+  *         DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7.
+  * @rmtoll CxCR         DMAREQ_ID     LL_DMA_SetPeriphRequest
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Request This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX1_REQ_MEM2MEM
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR0
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR1
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR2
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR3
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR4
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR5
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR6
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR7
+  *         @arg @ref LL_DMAMUX1_REQ_ADC1
+  *         @arg @ref LL_DMAMUX1_REQ_ADC2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_COM
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_UP
+  *         @arg @ref LL_DMAMUX1_REQ_I2C1_RX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C1_TX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C2_RX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C2_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI1_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI1_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI2_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI2_TX
+  *         @arg @ref LL_DMAMUX1_REQ_USART1_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART1_TX
+  *         @arg @ref LL_DMAMUX1_REQ_USART2_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART2_TX
+  *         @arg @ref LL_DMAMUX1_REQ_USART3_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART3_TX
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_COM
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_SPI3_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI3_TX
+  *         @arg @ref LL_DMAMUX1_REQ_UART4_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART4_TX
+  *         @arg @ref LL_DMAMUX1_REQ_UART5_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART5_TX
+  *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM6_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM7_UP
+  *         @arg @ref LL_DMAMUX1_REQ_USART6_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART6_TX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C3_RX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C3_TX
+  *         @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI
+  *         @arg @ref LL_DMAMUX1_REQ_CRYP_IN
+  *         @arg @ref LL_DMAMUX1_REQ_CRYP_OUT
+  *         @arg @ref LL_DMAMUX1_REQ_HASH_IN
+  *         @arg @ref LL_DMAMUX1_REQ_UART7_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART7_TX
+  *         @arg @ref LL_DMAMUX1_REQ_UART8_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART8_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI4_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI4_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI5_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI5_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SAI1_A
+  *         @arg @ref LL_DMAMUX1_REQ_SAI1_B
+  *         @arg @ref LL_DMAMUX1_REQ_SAI2_A
+  *         @arg @ref LL_DMAMUX1_REQ_SAI2_B
+  *         @arg @ref LL_DMAMUX1_REQ_SWPMI_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SWPMI_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
+  *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*)
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_COM
+  *         @arg @ref LL_DMAMUX1_REQ_TIM16_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM16_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM17_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM17_UP
+  *         @arg @ref LL_DMAMUX1_REQ_SAI3_A (*)
+  *         @arg @ref LL_DMAMUX1_REQ_SAI3_B (*)
+  *         @arg @ref LL_DMAMUX1_REQ_ADC3 (*)
+  *         @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
+  *         @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
+  *         @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
+  *         @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
+  * @note   (*) Availability depends on devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Request)
+{
+  MODIFY_REG(((DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Stream)) + (uint32_t)(DMAMUX_CCR_SIZE * LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
+}
+
+/**
+  * @brief  Get DMA request for DMA Channels on DMAMUX Channel x.
+  * @note   DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7.
+  *         DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7.
+  * @rmtoll CxCR         DMAREQ_ID     LL_DMA_GetPeriphRequest
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMAMUX1_REQ_MEM2MEM
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR0
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR1
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR2
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR3
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR4
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR5
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR6
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR7
+  *         @arg @ref LL_DMAMUX1_REQ_ADC1
+  *         @arg @ref LL_DMAMUX1_REQ_ADC2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_COM
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_UP
+  *         @arg @ref LL_DMAMUX1_REQ_I2C1_RX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C1_TX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C2_RX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C2_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI1_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI1_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI2_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI2_TX
+  *         @arg @ref LL_DMAMUX1_REQ_USART1_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART1_TX
+  *         @arg @ref LL_DMAMUX1_REQ_USART2_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART2_TX
+  *         @arg @ref LL_DMAMUX1_REQ_USART3_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART3_TX
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_COM
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_SPI3_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI3_TX
+  *         @arg @ref LL_DMAMUX1_REQ_UART4_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART4_TX
+  *         @arg @ref LL_DMAMUX1_REQ_UART5_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART5_TX
+  *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM6_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM7_UP
+  *         @arg @ref LL_DMAMUX1_REQ_USART6_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART6_TX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C3_RX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C3_TX
+  *         @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI
+  *         @arg @ref LL_DMAMUX1_REQ_CRYP_IN
+  *         @arg @ref LL_DMAMUX1_REQ_CRYP_OUT
+  *         @arg @ref LL_DMAMUX1_REQ_HASH_IN
+  *         @arg @ref LL_DMAMUX1_REQ_UART7_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART7_TX
+  *         @arg @ref LL_DMAMUX1_REQ_UART8_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART8_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI4_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI4_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI5_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI5_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SAI1_A
+  *         @arg @ref LL_DMAMUX1_REQ_SAI1_B
+  *         @arg @ref LL_DMAMUX1_REQ_SAI2_A
+  *         @arg @ref LL_DMAMUX1_REQ_SAI2_B
+  *         @arg @ref LL_DMAMUX1_REQ_SWPMI_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SWPMI_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
+  *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*)
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_COM
+  *         @arg @ref LL_DMAMUX1_REQ_TIM16_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM16_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM17_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM17_UP
+  *         @arg @ref LL_DMAMUX1_REQ_SAI3_A (*)
+  *         @arg @ref LL_DMAMUX1_REQ_SAI3_B (*)
+  *         @arg @ref LL_DMAMUX1_REQ_ADC3 (*)
+  *         @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
+  *         @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
+  *         @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
+  *         @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
+  * @note   (*) Availability depends on devices.
+  */
+__STATIC_INLINE  uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Stream)) + (uint32_t)(DMAMUX_CCR_SIZE * LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx)))))->CCR, DMAMUX_CxCR_DMAREQ_ID));
+}
+
+/**
+  * @brief Set Memory burst transfer configuration.
+  * @rmtoll CR          MBURST           LL_DMA_SetMemoryBurstxfer
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Mburst This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_MBURST_SINGLE
+  *         @arg @ref LL_DMA_MBURST_INC4
+  *         @arg @ref LL_DMA_MBURST_INC8
+  *         @arg @ref LL_DMA_MBURST_INC16
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MBURST, Mburst);
+}
+
+/**
+  * @brief Get Memory burst transfer configuration.
+  * @rmtoll CR          MBURST           LL_DMA_GetMemoryBurstxfer
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_MBURST_SINGLE
+  *         @arg @ref LL_DMA_MBURST_INC4
+  *         @arg @ref LL_DMA_MBURST_INC8
+  *         @arg @ref LL_DMA_MBURST_INC16
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MBURST));
+}
+
+/**
+  * @brief Set  Peripheral burst transfer configuration.
+  * @rmtoll CR          PBURST           LL_DMA_SetPeriphBurstxfer
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Pburst This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_PBURST_SINGLE
+  *         @arg @ref LL_DMA_PBURST_INC4
+  *         @arg @ref LL_DMA_PBURST_INC8
+  *         @arg @ref LL_DMA_PBURST_INC16
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PBURST, Pburst);
+}
+
+/**
+  * @brief Get Peripheral burst transfer configuration.
+  * @rmtoll CR          PBURST           LL_DMA_GetPeriphBurstxfer
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_PBURST_SINGLE
+  *         @arg @ref LL_DMA_PBURST_INC4
+  *         @arg @ref LL_DMA_PBURST_INC8
+  *         @arg @ref LL_DMA_PBURST_INC16
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PBURST));
+}
+
+/**
+  * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
+  * @rmtoll CR          CT           LL_DMA_SetCurrentTargetMem
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param CurrentMemory This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CURRENTTARGETMEM0
+  *         @arg @ref LL_DMA_CURRENTTARGETMEM1
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CT, CurrentMemory);
+}
+
+/**
+  * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
+  * @rmtoll CR          CT           LL_DMA_GetCurrentTargetMem
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_CURRENTTARGETMEM0
+  *         @arg @ref LL_DMA_CURRENTTARGETMEM1
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CT));
+}
+
+/**
+  * @brief Enable the double buffer mode.
+  * @rmtoll CR          DBM           LL_DMA_EnableDoubleBufferMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM);
+}
+
+/**
+  * @brief Disable the double buffer mode.
+  * @rmtoll CR          DBM           LL_DMA_DisableDoubleBufferMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM);
+}
+
+/**
+  * @brief Get FIFO status.
+  * @rmtoll FCR          FS          LL_DMA_GetFIFOStatus
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_FIFOSTATUS_0_25
+  *         @arg @ref LL_DMA_FIFOSTATUS_25_50
+  *         @arg @ref LL_DMA_FIFOSTATUS_50_75
+  *         @arg @ref LL_DMA_FIFOSTATUS_75_100
+  *         @arg @ref LL_DMA_FIFOSTATUS_EMPTY
+  *         @arg @ref LL_DMA_FIFOSTATUS_FULL
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FS));
+}
+
+/**
+  * @brief Disable Fifo mode.
+  * @rmtoll FCR          DMDIS          LL_DMA_DisableFifoMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_DMDIS);
+}
+
+/**
+  * @brief Enable Fifo mode.
+  * @rmtoll FCR          DMDIS          LL_DMA_EnableFifoMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_DMDIS);
+}
+
+/**
+  * @brief Select FIFO threshold.
+  * @rmtoll FCR         FTH          LL_DMA_SetFIFOThreshold
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Threshold This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH, Threshold);
+}
+
+/**
+  * @brief Get FIFO threshold.
+  * @rmtoll FCR         FTH          LL_DMA_GetFIFOThreshold
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH));
+}
+
+/**
+  * @brief Configure the FIFO .
+  * @rmtoll FCR         FTH          LL_DMA_ConfigFifo\n
+  *         FCR         DMDIS        LL_DMA_ConfigFifo
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  FifoMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_FIFOMODE_ENABLE
+  *         @arg @ref LL_DMA_FIFOMODE_DISABLE
+  * @param  FifoThreshold This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH | DMA_SxFCR_DMDIS, FifoMode | FifoThreshold);
+}
+
+/**
+  * @brief Configure the Source and Destination addresses.
+  * @note   This API must not be called when the DMA stream is enabled.
+  * @rmtoll M0AR        M0A         LL_DMA_ConfigAddresses\n
+  *         PAR         PA          LL_DMA_ConfigAddresses
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  SrcAddress Between 0 to 0xFFFFFFFF
+  * @param  DstAddress Between 0 to 0xFFFFFFFF
+  * @param  Direction This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  /* Direction Memory to Periph */
+  if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
+  {
+    WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, SrcAddress);
+    WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, DstAddress);
+  }
+  /* Direction Periph to Memory and Memory to Memory */
+  else
+  {
+    WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, SrcAddress);
+    WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, DstAddress);
+  }
+}
+
+/**
+  * @brief  Set the Memory address.
+  * @rmtoll M0AR        M0A         LL_DMA_SetMemoryAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+  * @note   This API must not be called when the DMA stream is enabled.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  MemoryAddress Between 0 to 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, MemoryAddress);
+}
+
+/**
+  * @brief  Set the Peripheral address.
+  * @rmtoll PAR        PA         LL_DMA_SetPeriphAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+  * @note   This API must not be called when the DMA stream is enabled.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  PeriphAddress Between 0 to 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t PeriphAddress)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, PeriphAddress);
+}
+
+/**
+  * @brief  Get the Memory address.
+  * @rmtoll M0AR        M0A         LL_DMA_GetMemoryAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Between 0 to 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR));
+}
+
+/**
+  * @brief  Get the Peripheral address.
+  * @rmtoll PAR        PA         LL_DMA_GetPeriphAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Between 0 to 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR));
+}
+
+/**
+  * @brief  Set the Memory to Memory Source address.
+  * @rmtoll PAR        PA         LL_DMA_SetM2MSrcAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+  * @note   This API must not be called when the DMA stream is enabled.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  MemoryAddress Between 0 to 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, MemoryAddress);
+}
+
+/**
+  * @brief  Set the Memory to Memory Destination address.
+  * @rmtoll M0AR        M0A         LL_DMA_SetM2MDstAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+  * @note   This API must not be called when the DMA stream is enabled.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  MemoryAddress Between 0 to 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, MemoryAddress);
+}
+
+/**
+  * @brief  Get the Memory to Memory Source address.
+  * @rmtoll PAR        PA         LL_DMA_GetM2MSrcAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Between 0 to 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR));
+}
+
+/**
+  * @brief  Get the Memory to Memory Destination address.
+  * @rmtoll M0AR        M0A         LL_DMA_GetM2MDstAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Between 0 to 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR));
+}
+
+/**
+  * @brief Set Memory 1 address (used in case of Double buffer mode).
+  * @rmtoll M1AR        M1A         LL_DMA_SetMemory1Address
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Address Between 0 to 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M1AR, DMA_SxM1AR_M1A, Address);
+}
+
+/**
+  * @brief Get Memory 1 address (used in case of Double buffer mode).
+  * @rmtoll M1AR        M1A         LL_DMA_GetMemory1Address
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Between 0 to 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M1AR);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief Get Stream 0 half transfer flag.
+  * @rmtoll LISR  HTIF0    LL_DMA_IsActiveFlag_HT0
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF0) == (DMA_LISR_HTIF0)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 1 half transfer flag.
+  * @rmtoll LISR  HTIF1    LL_DMA_IsActiveFlag_HT1
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF1) == (DMA_LISR_HTIF1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 2 half transfer flag.
+  * @rmtoll LISR  HTIF2    LL_DMA_IsActiveFlag_HT2
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF2) == (DMA_LISR_HTIF2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 3 half transfer flag.
+  * @rmtoll LISR  HTIF3    LL_DMA_IsActiveFlag_HT3
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF3) == (DMA_LISR_HTIF3)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 4 half transfer flag.
+  * @rmtoll HISR  HTIF4    LL_DMA_IsActiveFlag_HT4
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF4) == (DMA_HISR_HTIF4)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 5 half transfer flag.
+  * @rmtoll HISR  HTIF0    LL_DMA_IsActiveFlag_HT5
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF5) == (DMA_HISR_HTIF5)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 6 half transfer flag.
+  * @rmtoll HISR  HTIF6    LL_DMA_IsActiveFlag_HT6
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF6) == (DMA_HISR_HTIF6)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 7 half transfer flag.
+  * @rmtoll HISR  HTIF7    LL_DMA_IsActiveFlag_HT7
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF7) == (DMA_HISR_HTIF7)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 0 transfer complete flag.
+  * @rmtoll LISR  TCIF0    LL_DMA_IsActiveFlag_TC0
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF0) == (DMA_LISR_TCIF0)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 1 transfer complete flag.
+  * @rmtoll LISR  TCIF1    LL_DMA_IsActiveFlag_TC1
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF1) == (DMA_LISR_TCIF1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 2 transfer complete flag.
+  * @rmtoll LISR  TCIF2    LL_DMA_IsActiveFlag_TC2
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF2) == (DMA_LISR_TCIF2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 3 transfer complete flag.
+  * @rmtoll LISR  TCIF3    LL_DMA_IsActiveFlag_TC3
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF3) == (DMA_LISR_TCIF3)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 4 transfer complete flag.
+  * @rmtoll HISR  TCIF4    LL_DMA_IsActiveFlag_TC4
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF4) == (DMA_HISR_TCIF4)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 5 transfer complete flag.
+  * @rmtoll HISR  TCIF0    LL_DMA_IsActiveFlag_TC5
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF5) == (DMA_HISR_TCIF5)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 6 transfer complete flag.
+  * @rmtoll HISR  TCIF6    LL_DMA_IsActiveFlag_TC6
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF6) == (DMA_HISR_TCIF6)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 7 transfer complete flag.
+  * @rmtoll HISR  TCIF7    LL_DMA_IsActiveFlag_TC7
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF7) == (DMA_HISR_TCIF7)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 0 transfer error flag.
+  * @rmtoll LISR  TEIF0    LL_DMA_IsActiveFlag_TE0
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF0) == (DMA_LISR_TEIF0)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 1 transfer error flag.
+  * @rmtoll LISR  TEIF1    LL_DMA_IsActiveFlag_TE1
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF1) == (DMA_LISR_TEIF1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 2 transfer error flag.
+  * @rmtoll LISR  TEIF2    LL_DMA_IsActiveFlag_TE2
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF2) == (DMA_LISR_TEIF2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 3 transfer error flag.
+  * @rmtoll LISR  TEIF3    LL_DMA_IsActiveFlag_TE3
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF3) == (DMA_LISR_TEIF3)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 4 transfer error flag.
+  * @rmtoll HISR  TEIF4    LL_DMA_IsActiveFlag_TE4
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF4) == (DMA_HISR_TEIF4)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 5 transfer error flag.
+  * @rmtoll HISR  TEIF0    LL_DMA_IsActiveFlag_TE5
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF5) == (DMA_HISR_TEIF5)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 6 transfer error flag.
+  * @rmtoll HISR  TEIF6    LL_DMA_IsActiveFlag_TE6
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF6) == (DMA_HISR_TEIF6)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 7 transfer error flag.
+  * @rmtoll HISR  TEIF7    LL_DMA_IsActiveFlag_TE7
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF7) == (DMA_HISR_TEIF7)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 0 direct mode error flag.
+  * @rmtoll LISR  DMEIF0    LL_DMA_IsActiveFlag_DME0
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF0) == (DMA_LISR_DMEIF0)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 1 direct mode error flag.
+  * @rmtoll LISR  DMEIF1    LL_DMA_IsActiveFlag_DME1
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF1) == (DMA_LISR_DMEIF1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 2 direct mode error flag.
+  * @rmtoll LISR  DMEIF2    LL_DMA_IsActiveFlag_DME2
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF2) == (DMA_LISR_DMEIF2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 3 direct mode error flag.
+  * @rmtoll LISR  DMEIF3    LL_DMA_IsActiveFlag_DME3
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF3) == (DMA_LISR_DMEIF3)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 4 direct mode error flag.
+  * @rmtoll HISR  DMEIF4    LL_DMA_IsActiveFlag_DME4
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF4) == (DMA_HISR_DMEIF4)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 5 direct mode error flag.
+  * @rmtoll HISR  DMEIF0    LL_DMA_IsActiveFlag_DME5
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF5) == (DMA_HISR_DMEIF5)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 6 direct mode error flag.
+  * @rmtoll HISR  DMEIF6    LL_DMA_IsActiveFlag_DME6
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF6) == (DMA_HISR_DMEIF6)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 7 direct mode error flag.
+  * @rmtoll HISR  DMEIF7    LL_DMA_IsActiveFlag_DME7
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF7) == (DMA_HISR_DMEIF7)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 0 FIFO error flag.
+  * @rmtoll LISR  FEIF0    LL_DMA_IsActiveFlag_FE0
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF0) == (DMA_LISR_FEIF0)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 1 FIFO error flag.
+  * @rmtoll LISR  FEIF1    LL_DMA_IsActiveFlag_FE1
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF1) == (DMA_LISR_FEIF1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 2 FIFO error flag.
+  * @rmtoll LISR  FEIF2    LL_DMA_IsActiveFlag_FE2
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF2) == (DMA_LISR_FEIF2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 3 FIFO error flag.
+  * @rmtoll LISR  FEIF3    LL_DMA_IsActiveFlag_FE3
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF3) == (DMA_LISR_FEIF3)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 4 FIFO error flag.
+  * @rmtoll HISR  FEIF4    LL_DMA_IsActiveFlag_FE4
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF4) == (DMA_HISR_FEIF4)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 5 FIFO error flag.
+  * @rmtoll HISR  FEIF0    LL_DMA_IsActiveFlag_FE5
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF5) == (DMA_HISR_FEIF5)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 6 FIFO error flag.
+  * @rmtoll HISR  FEIF6    LL_DMA_IsActiveFlag_FE6
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF6) == (DMA_HISR_FEIF6)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 7 FIFO error flag.
+  * @rmtoll HISR  FEIF7    LL_DMA_IsActiveFlag_FE7
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF7) == (DMA_HISR_FEIF7)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Clear Stream 0 half transfer flag.
+  * @rmtoll LIFCR  CHTIF0    LL_DMA_ClearFlag_HT0
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF0);
+}
+
+/**
+  * @brief Clear Stream 1 half transfer flag.
+  * @rmtoll LIFCR  CHTIF1    LL_DMA_ClearFlag_HT1
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF1);
+}
+
+/**
+  * @brief Clear Stream 2 half transfer flag.
+  * @rmtoll LIFCR  CHTIF2    LL_DMA_ClearFlag_HT2
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF2);
+}
+
+/**
+  * @brief Clear Stream 3 half transfer flag.
+  * @rmtoll LIFCR  CHTIF3    LL_DMA_ClearFlag_HT3
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF3);
+}
+
+/**
+  * @brief Clear Stream 4 half transfer flag.
+  * @rmtoll HIFCR  CHTIF4    LL_DMA_ClearFlag_HT4
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF4);
+}
+
+/**
+  * @brief Clear Stream 5 half transfer flag.
+  * @rmtoll HIFCR  CHTIF5    LL_DMA_ClearFlag_HT5
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF5);
+}
+
+/**
+  * @brief Clear Stream 6 half transfer flag.
+  * @rmtoll HIFCR  CHTIF6    LL_DMA_ClearFlag_HT6
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF6);
+}
+
+/**
+  * @brief Clear Stream 7 half transfer flag.
+  * @rmtoll HIFCR  CHTIF7    LL_DMA_ClearFlag_HT7
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF7);
+}
+
+/**
+  * @brief Clear Stream 0 transfer complete flag.
+  * @rmtoll LIFCR  CTCIF0    LL_DMA_ClearFlag_TC0
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF0);
+}
+
+/**
+  * @brief Clear Stream 1 transfer complete flag.
+  * @rmtoll LIFCR  CTCIF1    LL_DMA_ClearFlag_TC1
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF1);
+}
+
+/**
+  * @brief Clear Stream 2 transfer complete flag.
+  * @rmtoll LIFCR  CTCIF2    LL_DMA_ClearFlag_TC2
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF2);
+}
+
+/**
+  * @brief Clear Stream 3 transfer complete flag.
+  * @rmtoll LIFCR  CTCIF3    LL_DMA_ClearFlag_TC3
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF3);
+}
+
+/**
+  * @brief Clear Stream 4 transfer complete flag.
+  * @rmtoll HIFCR  CTCIF4    LL_DMA_ClearFlag_TC4
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF4);
+}
+
+/**
+  * @brief Clear Stream 5 transfer complete flag.
+  * @rmtoll HIFCR  CTCIF5    LL_DMA_ClearFlag_TC5
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF5);
+}
+
+/**
+  * @brief Clear Stream 6 transfer complete flag.
+  * @rmtoll HIFCR  CTCIF6    LL_DMA_ClearFlag_TC6
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF6);
+}
+
+/**
+  * @brief Clear Stream 7 transfer complete flag.
+  * @rmtoll HIFCR  CTCIF7    LL_DMA_ClearFlag_TC7
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF7);
+}
+
+/**
+  * @brief Clear Stream 0 transfer error flag.
+  * @rmtoll LIFCR  CTEIF0    LL_DMA_ClearFlag_TE0
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF0);
+}
+
+/**
+  * @brief Clear Stream 1 transfer error flag.
+  * @rmtoll LIFCR  CTEIF1    LL_DMA_ClearFlag_TE1
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF1);
+}
+
+/**
+  * @brief Clear Stream 2 transfer error flag.
+  * @rmtoll LIFCR  CTEIF2    LL_DMA_ClearFlag_TE2
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF2);
+}
+
+/**
+  * @brief Clear Stream 3 transfer error flag.
+  * @rmtoll LIFCR  CTEIF3    LL_DMA_ClearFlag_TE3
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF3);
+}
+
+/**
+  * @brief Clear Stream 4 transfer error flag.
+  * @rmtoll HIFCR  CTEIF4    LL_DMA_ClearFlag_TE4
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF4);
+}
+
+/**
+  * @brief Clear Stream 5 transfer error flag.
+  * @rmtoll HIFCR  CTEIF5    LL_DMA_ClearFlag_TE5
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF5);
+}
+
+/**
+  * @brief Clear Stream 6 transfer error flag.
+  * @rmtoll HIFCR  CTEIF6    LL_DMA_ClearFlag_TE6
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF6);
+}
+
+/**
+  * @brief Clear Stream 7 transfer error flag.
+  * @rmtoll HIFCR  CTEIF7    LL_DMA_ClearFlag_TE7
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF7);
+}
+
+/**
+  * @brief Clear Stream 0 direct mode error flag.
+  * @rmtoll LIFCR  CDMEIF0    LL_DMA_ClearFlag_DME0
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF0);
+}
+
+/**
+  * @brief Clear Stream 1 direct mode error flag.
+  * @rmtoll LIFCR  CDMEIF1    LL_DMA_ClearFlag_DME1
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF1);
+}
+
+/**
+  * @brief Clear Stream 2 direct mode error flag.
+  * @rmtoll LIFCR  CDMEIF2    LL_DMA_ClearFlag_DME2
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF2);
+}
+
+/**
+  * @brief Clear Stream 3 direct mode error flag.
+  * @rmtoll LIFCR  CDMEIF3    LL_DMA_ClearFlag_DME3
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF3);
+}
+
+/**
+  * @brief Clear Stream 4 direct mode error flag.
+  * @rmtoll HIFCR  CDMEIF4    LL_DMA_ClearFlag_DME4
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF4);
+}
+
+/**
+  * @brief Clear Stream 5 direct mode error flag.
+  * @rmtoll HIFCR  CDMEIF5    LL_DMA_ClearFlag_DME5
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF5);
+}
+
+/**
+  * @brief Clear Stream 6 direct mode error flag.
+  * @rmtoll HIFCR  CDMEIF6    LL_DMA_ClearFlag_DME6
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF6);
+}
+
+/**
+  * @brief Clear Stream 7 direct mode error flag.
+  * @rmtoll HIFCR  CDMEIF7    LL_DMA_ClearFlag_DME7
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF7);
+}
+
+/**
+  * @brief Clear Stream 0 FIFO error flag.
+  * @rmtoll LIFCR  CFEIF0    LL_DMA_ClearFlag_FE0
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF0);
+}
+
+/**
+  * @brief Clear Stream 1 FIFO error flag.
+  * @rmtoll LIFCR  CFEIF1    LL_DMA_ClearFlag_FE1
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF1);
+}
+
+/**
+  * @brief Clear Stream 2 FIFO error flag.
+  * @rmtoll LIFCR  CFEIF2    LL_DMA_ClearFlag_FE2
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF2);
+}
+
+/**
+  * @brief Clear Stream 3 FIFO error flag.
+  * @rmtoll LIFCR  CFEIF3    LL_DMA_ClearFlag_FE3
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF3);
+}
+
+/**
+  * @brief Clear Stream 4 FIFO error flag.
+  * @rmtoll HIFCR  CFEIF4    LL_DMA_ClearFlag_FE4
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF4);
+}
+
+/**
+  * @brief Clear Stream 5 FIFO error flag.
+  * @rmtoll HIFCR  CFEIF5    LL_DMA_ClearFlag_FE5
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF5);
+}
+
+/**
+  * @brief Clear Stream 6 FIFO error flag.
+  * @rmtoll HIFCR  CFEIF6    LL_DMA_ClearFlag_FE6
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF6);
+}
+
+/**
+  * @brief Clear Stream 7 FIFO error flag.
+  * @rmtoll HIFCR  CFEIF7    LL_DMA_ClearFlag_FE7
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF7);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief Enable Half transfer interrupt.
+  * @rmtoll CR        HTIE         LL_DMA_EnableIT_HT
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE);
+}
+
+/**
+  * @brief Enable Transfer error interrupt.
+  * @rmtoll CR        TEIE         LL_DMA_EnableIT_TE
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE);
+}
+
+/**
+  * @brief Enable Transfer complete interrupt.
+  * @rmtoll CR        TCIE         LL_DMA_EnableIT_TC
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE);
+}
+
+/**
+  * @brief Enable Direct mode error interrupt.
+  * @rmtoll CR        DMEIE         LL_DMA_EnableIT_DME
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE);
+}
+
+/**
+  * @brief Enable FIFO error interrupt.
+  * @rmtoll FCR        FEIE         LL_DMA_EnableIT_FE
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE);
+}
+
+/**
+  * @brief Disable Half transfer interrupt.
+  * @rmtoll CR        HTIE         LL_DMA_DisableIT_HT
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE);
+}
+
+/**
+  * @brief Disable Transfer error interrupt.
+  * @rmtoll CR        TEIE         LL_DMA_DisableIT_TE
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE);
+}
+
+/**
+  * @brief Disable Transfer complete interrupt.
+  * @rmtoll CR        TCIE         LL_DMA_DisableIT_TC
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE);
+}
+
+/**
+  * @brief Disable Direct mode error interrupt.
+  * @rmtoll CR        DMEIE         LL_DMA_DisableIT_DME
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE);
+}
+
+/**
+  * @brief Disable FIFO error interrupt.
+  * @rmtoll FCR        FEIE         LL_DMA_DisableIT_FE
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE);
+}
+
+/**
+  * @brief Check if Half transfer interrup is enabled.
+  * @rmtoll CR        HTIE         LL_DMA_IsEnabledIT_HT
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Check if Transfer error nterrup is enabled.
+  * @rmtoll CR        TEIE         LL_DMA_IsEnabledIT_TE
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Check if Transfer complete interrup is enabled.
+  * @rmtoll CR        TCIE         LL_DMA_IsEnabledIT_TC
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Check if Direct mode error interrupt is enabled.
+  * @rmtoll CR        DMEIE         LL_DMA_IsEnabledIT_DME
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Check if FIFO error interrup is enabled.
+  * @rmtoll FCR        FEIE         LL_DMA_IsEnabledIT_FE
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct);
+uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream);
+void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* DMA1 || DMA2 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32H7xx_LL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dmamux.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dmamux.h
new file mode 100644
index 00000000..13f81186
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dmamux.h
@@ -0,0 +1,2363 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_dmamux.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMAMUX LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_LL_DMAMUX_H
+#define STM32H7xx_LL_DMAMUX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined (DMAMUX1) || defined (DMAMUX2)
+
+/** @defgroup DMAMUX_LL DMAMUX
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup DMAMUX_LL_Private_Constants DMAMUX Private Constants
+  * @{
+  */
+/* Define used to get DMAMUX CCR register size */
+#define DMAMUX_CCR_SIZE                   0x00000004U
+
+/* Define used to get DMAMUX RGCR register size */
+#define DMAMUX_RGCR_SIZE                  0x00000004U
+
+/* Define used to get DMAMUX RequestGenerator offset */
+#define DMAMUX_REQ_GEN_OFFSET             (DMAMUX1_RequestGenerator0_BASE - DMAMUX1_BASE)
+/* Define used to get DMAMUX Channel Status offset */
+#define DMAMUX_CH_STATUS_OFFSET           (DMAMUX1_ChannelStatus_BASE - DMAMUX1_BASE)
+/* Define used to get DMAMUX RequestGenerator status offset */
+#define DMAMUX_REQ_GEN_STATUS_OFFSET      (DMAMUX1_RequestGenStatus_BASE - DMAMUX1_BASE)
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DMAMUX_LL_Exported_Constants DMAMUX Exported Constants
+  * @{
+  */
+/** @defgroup DMAMUX_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_DMAMUX_WriteReg function
+  * @{
+  */
+#define LL_DMAMUX_CFR_CSOF0               DMAMUX_CFR_CSOF0       /*!< Synchronization Event Overrun Flag Channel 0   */
+#define LL_DMAMUX_CFR_CSOF1               DMAMUX_CFR_CSOF1       /*!< Synchronization Event Overrun Flag Channel 1   */
+#define LL_DMAMUX_CFR_CSOF2               DMAMUX_CFR_CSOF2       /*!< Synchronization Event Overrun Flag Channel 2   */
+#define LL_DMAMUX_CFR_CSOF3               DMAMUX_CFR_CSOF3       /*!< Synchronization Event Overrun Flag Channel 3   */
+#define LL_DMAMUX_CFR_CSOF4               DMAMUX_CFR_CSOF4       /*!< Synchronization Event Overrun Flag Channel 4   */
+#define LL_DMAMUX_CFR_CSOF5               DMAMUX_CFR_CSOF5       /*!< Synchronization Event Overrun Flag Channel 5   */
+#define LL_DMAMUX_CFR_CSOF6               DMAMUX_CFR_CSOF6       /*!< Synchronization Event Overrun Flag Channel 6   */
+#define LL_DMAMUX_CFR_CSOF7               DMAMUX_CFR_CSOF7       /*!< Synchronization Event Overrun Flag Channel 7   */
+#define LL_DMAMUX_CFR_CSOF8               DMAMUX_CFR_CSOF8       /*!< Synchronization Event Overrun Flag Channel 8   */
+#define LL_DMAMUX_CFR_CSOF9               DMAMUX_CFR_CSOF9       /*!< Synchronization Event Overrun Flag Channel 9   */
+#define LL_DMAMUX_CFR_CSOF10              DMAMUX_CFR_CSOF10      /*!< Synchronization Event Overrun Flag Channel 10  */
+#define LL_DMAMUX_CFR_CSOF11              DMAMUX_CFR_CSOF11      /*!< Synchronization Event Overrun Flag Channel 11  */
+#define LL_DMAMUX_CFR_CSOF12              DMAMUX_CFR_CSOF12      /*!< Synchronization Event Overrun Flag Channel 12  */
+#define LL_DMAMUX_CFR_CSOF13              DMAMUX_CFR_CSOF13      /*!< Synchronization Event Overrun Flag Channel 13  */
+#define LL_DMAMUX_CFR_CSOF14              DMAMUX_CFR_CSOF14      /*!< Synchronization Event Overrun Flag Channel 14  */
+#define LL_DMAMUX_CFR_CSOF15              DMAMUX_CFR_CSOF15      /*!< Synchronization Event Overrun Flag Channel 15  */
+#define LL_DMAMUX_RGCFR_RGCOF0            DMAMUX_RGCFR_COF0      /*!< Request Generator 0 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGCFR_RGCOF1            DMAMUX_RGCFR_COF1      /*!< Request Generator 1 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGCFR_RGCOF2            DMAMUX_RGCFR_COF2      /*!< Request Generator 2 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGCFR_RGCOF3            DMAMUX_RGCFR_COF3      /*!< Request Generator 3 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGCFR_RGCOF4            DMAMUX_RGCFR_COF4      /*!< Request Generator 4 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGCFR_RGCOF5            DMAMUX_RGCFR_COF5      /*!< Request Generator 5 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGCFR_RGCOF6            DMAMUX_RGCFR_COF6      /*!< Request Generator 6 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGCFR_RGCOF7            DMAMUX_RGCFR_COF7      /*!< Request Generator 7 Trigger Event Overrun Flag */
+/**
+  * @}
+  */
+
+/** @defgroup DMAMUX_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_DMAMUX_ReadReg function
+  * @{
+  */
+#define LL_DMAMUX_CSR_SOF0                DMAMUX_CSR_SOF0       /*!< Synchronization Event Overrun Flag Channel 0   */
+#define LL_DMAMUX_CSR_SOF1                DMAMUX_CSR_SOF1       /*!< Synchronization Event Overrun Flag Channel 1   */
+#define LL_DMAMUX_CSR_SOF2                DMAMUX_CSR_SOF2       /*!< Synchronization Event Overrun Flag Channel 2   */
+#define LL_DMAMUX_CSR_SOF3                DMAMUX_CSR_SOF3       /*!< Synchronization Event Overrun Flag Channel 3   */
+#define LL_DMAMUX_CSR_SOF4                DMAMUX_CSR_SOF4       /*!< Synchronization Event Overrun Flag Channel 4   */
+#define LL_DMAMUX_CSR_SOF5                DMAMUX_CSR_SOF5       /*!< Synchronization Event Overrun Flag Channel 5   */
+#define LL_DMAMUX_CSR_SOF6                DMAMUX_CSR_SOF6       /*!< Synchronization Event Overrun Flag Channel 6   */
+#define LL_DMAMUX_CSR_SOF7                DMAMUX_CSR_SOF7       /*!< Synchronization Event Overrun Flag Channel 7   */
+#define LL_DMAMUX_CSR_SOF8                DMAMUX_CSR_SOF8       /*!< Synchronization Event Overrun Flag Channel 8   */
+#define LL_DMAMUX_CSR_SOF9                DMAMUX_CSR_SOF9       /*!< Synchronization Event Overrun Flag Channel 9   */
+#define LL_DMAMUX_CSR_SOF10               DMAMUX_CSR_SOF10      /*!< Synchronization Event Overrun Flag Channel 10  */
+#define LL_DMAMUX_CSR_SOF11               DMAMUX_CSR_SOF11      /*!< Synchronization Event Overrun Flag Channel 11  */
+#define LL_DMAMUX_CSR_SOF12               DMAMUX_CSR_SOF12      /*!< Synchronization Event Overrun Flag Channel 12  */
+#define LL_DMAMUX_CSR_SOF13               DMAMUX_CSR_SOF13      /*!< Synchronization Event Overrun Flag Channel 13  */
+#define LL_DMAMUX_CSR_SOF14               DMAMUX_CSR_SOF14      /*!< Synchronization Event Overrun Flag Channel 14  */
+#define LL_DMAMUX_CSR_SOF15               DMAMUX_CSR_SOF15      /*!< Synchronization Event Overrun Flag Channel 15  */
+#define LL_DMAMUX_RGSR_RGOF0              DMAMUX_RGSR_OF0       /*!< Request Generator 0 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGSR_RGOF1              DMAMUX_RGSR_OF1       /*!< Request Generator 1 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGSR_RGOF2              DMAMUX_RGSR_OF2       /*!< Request Generator 2 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGSR_RGOF3              DMAMUX_RGSR_OF3       /*!< Request Generator 3 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGSR_RGOF4              DMAMUX_RGSR_OF4       /*!< Request Generator 4 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGSR_RGOF5              DMAMUX_RGSR_OF5       /*!< Request Generator 5 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGSR_RGOF6              DMAMUX_RGSR_OF6       /*!< Request Generator 6 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGSR_RGOF7              DMAMUX_RGSR_OF7       /*!< Request Generator 7 Trigger Event Overrun Flag */
+/**
+  * @}
+  */
+
+/** @defgroup DMAMUX_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_DMA_ReadReg and  LL_DMAMUX_WriteReg functions
+  * @{
+  */
+#define LL_DMAMUX_CCR_SOIE                DMAMUX_CxCR_SOIE          /*!< Synchronization Event Overrun Interrupt               */
+#define LL_DMAMUX_RGCR_RGOIE              DMAMUX_RGxCR_OIE          /*!< Request Generation Trigger Event Overrun Interrupt    */
+/**
+  * @}
+  */
+
+/** @defgroup DMAMUX_Request_selection DMAMUX Request selection
+  * @brief    DMA Request selection
+  * @{
+  */
+/* DMAMUX1 requests */
+#define LL_DMAMUX1_REQ_MEM2MEM          0U   /*!< memory to memory transfer       */
+#define LL_DMAMUX1_REQ_GENERATOR0       1U   /*!< DMAMUX1 request generator 0     */
+#define LL_DMAMUX1_REQ_GENERATOR1       2U   /*!< DMAMUX1 request generator 1     */
+#define LL_DMAMUX1_REQ_GENERATOR2       3U   /*!< DMAMUX1 request generator 2     */
+#define LL_DMAMUX1_REQ_GENERATOR3       4U   /*!< DMAMUX1 request generator 3     */
+#define LL_DMAMUX1_REQ_GENERATOR4       5U   /*!< DMAMUX1 request generator 4     */
+#define LL_DMAMUX1_REQ_GENERATOR5       6U   /*!< DMAMUX1 request generator 5     */
+#define LL_DMAMUX1_REQ_GENERATOR6       7U   /*!< DMAMUX1 request generator 6     */
+#define LL_DMAMUX1_REQ_GENERATOR7       8U   /*!< DMAMUX1 request generator 7     */
+#define LL_DMAMUX1_REQ_ADC1             9U   /*!< DMAMUX1 ADC1 request            */
+#define LL_DMAMUX1_REQ_ADC2             10U  /*!< DMAMUX1 ADC2 request            */
+#define LL_DMAMUX1_REQ_TIM1_CH1         11U  /*!< DMAMUX1 TIM1 CH1 request        */
+#define LL_DMAMUX1_REQ_TIM1_CH2         12U  /*!< DMAMUX1 TIM1 CH2 request        */
+#define LL_DMAMUX1_REQ_TIM1_CH3         13U  /*!< DMAMUX1 TIM1 CH3 request        */
+#define LL_DMAMUX1_REQ_TIM1_CH4         14U  /*!< DMAMUX1 TIM1 CH4 request        */
+#define LL_DMAMUX1_REQ_TIM1_UP          15U  /*!< DMAMUX1 TIM1 UP request         */
+#define LL_DMAMUX1_REQ_TIM1_TRIG        16U  /*!< DMAMUX1 TIM1 TRIG request       */
+#define LL_DMAMUX1_REQ_TIM1_COM         17U  /*!< DMAMUX1 TIM1 COM request        */
+#define LL_DMAMUX1_REQ_TIM2_CH1         18U  /*!< DMAMUX1 TIM2 CH1 request        */
+#define LL_DMAMUX1_REQ_TIM2_CH2         19U  /*!< DMAMUX1 TIM2 CH2 request        */
+#define LL_DMAMUX1_REQ_TIM2_CH3         20U  /*!< DMAMUX1 TIM2 CH3 request        */
+#define LL_DMAMUX1_REQ_TIM2_CH4         21U  /*!< DMAMUX1 TIM2 CH4 request        */
+#define LL_DMAMUX1_REQ_TIM2_UP          22U  /*!< DMAMUX1 TIM2 UP request         */
+#define LL_DMAMUX1_REQ_TIM3_CH1         23U  /*!< DMAMUX1 TIM3 CH1 request        */
+#define LL_DMAMUX1_REQ_TIM3_CH2         24U  /*!< DMAMUX1 TIM3 CH2 request        */
+#define LL_DMAMUX1_REQ_TIM3_CH3         25U  /*!< DMAMUX1 TIM3 CH3 request        */
+#define LL_DMAMUX1_REQ_TIM3_CH4         26U  /*!< DMAMUX1 TIM3 CH4 request        */
+#define LL_DMAMUX1_REQ_TIM3_UP          27U  /*!< DMAMUX1 TIM3 UP request         */
+#define LL_DMAMUX1_REQ_TIM3_TRIG        28U  /*!< DMAMUX1 TIM3 TRIG request       */
+#define LL_DMAMUX1_REQ_TIM4_CH1         29U  /*!< DMAMUX1 TIM4 CH1 request        */
+#define LL_DMAMUX1_REQ_TIM4_CH2         30U  /*!< DMAMUX1 TIM4 CH2 request        */
+#define LL_DMAMUX1_REQ_TIM4_CH3         31U  /*!< DMAMUX1 TIM4 CH3 request        */
+#define LL_DMAMUX1_REQ_TIM4_UP          32U  /*!< DMAMUX1 TIM4 UP request         */
+#define LL_DMAMUX1_REQ_I2C1_RX          33U  /*!< DMAMUX1 I2C1 RX request         */
+#define LL_DMAMUX1_REQ_I2C1_TX          34U  /*!< DMAMUX1 I2C1 TX request         */
+#define LL_DMAMUX1_REQ_I2C2_RX          35U  /*!< DMAMUX1 I2C2 RX request         */
+#define LL_DMAMUX1_REQ_I2C2_TX          36U  /*!< DMAMUX1 I2C2 TX request         */
+#define LL_DMAMUX1_REQ_SPI1_RX          37U  /*!< DMAMUX1 SPI1 RX request         */
+#define LL_DMAMUX1_REQ_SPI1_TX          38U  /*!< DMAMUX1 SPI1 TX request         */
+#define LL_DMAMUX1_REQ_SPI2_RX          39U  /*!< DMAMUX1 SPI2 RX request         */
+#define LL_DMAMUX1_REQ_SPI2_TX          40U  /*!< DMAMUX1 SPI2 TX request         */
+#define LL_DMAMUX1_REQ_USART1_RX        41U  /*!< DMAMUX1 USART1 RX request       */
+#define LL_DMAMUX1_REQ_USART1_TX        42U  /*!< DMAMUX1 USART1 TX request       */
+#define LL_DMAMUX1_REQ_USART2_RX        43U  /*!< DMAMUX1 USART2 RX request       */
+#define LL_DMAMUX1_REQ_USART2_TX        44U  /*!< DMAMUX1 USART2 TX request       */
+#define LL_DMAMUX1_REQ_USART3_RX        45U  /*!< DMAMUX1 USART3 RX request       */
+#define LL_DMAMUX1_REQ_USART3_TX        46U  /*!< DMAMUX1 USART3 TX request       */
+#define LL_DMAMUX1_REQ_TIM8_CH1         47U  /*!< DMAMUX1 TIM8 CH1 request        */
+#define LL_DMAMUX1_REQ_TIM8_CH2         48U  /*!< DMAMUX1 TIM8 CH2 request        */
+#define LL_DMAMUX1_REQ_TIM8_CH3         49U  /*!< DMAMUX1 TIM8 CH3 request        */
+#define LL_DMAMUX1_REQ_TIM8_CH4         50U  /*!< DMAMUX1 TIM8 CH4 request        */
+#define LL_DMAMUX1_REQ_TIM8_UP          51U  /*!< DMAMUX1 TIM8 UP request         */
+#define LL_DMAMUX1_REQ_TIM8_TRIG        52U  /*!< DMAMUX1 TIM8 TRIG request       */
+#define LL_DMAMUX1_REQ_TIM8_COM         53U  /*!< DMAMUX1 TIM8 COM request        */
+#define LL_DMAMUX1_REQ_TIM5_CH1         55U  /*!< DMAMUX1 TIM5 CH1 request        */
+#define LL_DMAMUX1_REQ_TIM5_CH2         56U  /*!< DMAMUX1 TIM5 CH2 request        */
+#define LL_DMAMUX1_REQ_TIM5_CH3         57U  /*!< DMAMUX1 TIM5 CH3 request        */
+#define LL_DMAMUX1_REQ_TIM5_CH4         58U  /*!< DMAMUX1 TIM5 CH4 request        */
+#define LL_DMAMUX1_REQ_TIM5_UP          59U  /*!< DMAMUX1 TIM5 UP request         */
+#define LL_DMAMUX1_REQ_TIM5_TRIG        60U  /*!< DMAMUX1 TIM5 TRIG request       */
+#define LL_DMAMUX1_REQ_SPI3_RX          61U  /*!< DMAMUX1 SPI3 RX request         */
+#define LL_DMAMUX1_REQ_SPI3_TX          62U  /*!< DMAMUX1 SPI3 TX request         */
+#define LL_DMAMUX1_REQ_UART4_RX         63U  /*!< DMAMUX1 UART4 RX request        */
+#define LL_DMAMUX1_REQ_UART4_TX         64U  /*!< DMAMUX1 UART4 TX request        */
+#define LL_DMAMUX1_REQ_UART5_RX         65U  /*!< DMAMUX1 UART5 RX request        */
+#define LL_DMAMUX1_REQ_UART5_TX         66U  /*!< DMAMUX1 UART5 TX request        */
+#define LL_DMAMUX1_REQ_DAC1_CH1         67U  /*!< DMAMUX1 DAC1 Channel 1 request  */
+#define LL_DMAMUX1_REQ_DAC1_CH2         68U  /*!< DMAMUX1 DAC1 Channel 2 request  */
+#define LL_DMAMUX1_REQ_TIM6_UP          69U  /*!< DMAMUX1 TIM6 UP request         */
+#define LL_DMAMUX1_REQ_TIM7_UP          70U  /*!< DMAMUX1 TIM7 UP request         */
+#define LL_DMAMUX1_REQ_USART6_RX        71U  /*!< DMAMUX1 USART6 RX request       */
+#define LL_DMAMUX1_REQ_USART6_TX        72U  /*!< DMAMUX1 USART6 TX request       */
+#define LL_DMAMUX1_REQ_I2C3_RX          73U  /*!< DMAMUX1 I2C3 RX request         */
+#define LL_DMAMUX1_REQ_I2C3_TX          74U  /*!< DMAMUX1 I2C3 TX request         */
+#if defined (PSSI)
+#define LL_DMAMUX1_REQ_DCMI_PSSI        75U  /*!< DMAMUX1 DCMI/PSSI request       */
+#define LL_DMAMUX1_REQ_DCMI             LL_DMAMUX1_REQ_DCMI_PSSI /* Legacy define */
+#else
+#define LL_DMAMUX1_REQ_DCMI             75U  /*!< DMAMUX1 DCMI request            */
+#endif /* PSSI */
+#define LL_DMAMUX1_REQ_CRYP_IN          76U  /*!< DMAMUX1 CRYP IN request         */
+#define LL_DMAMUX1_REQ_CRYP_OUT         77U  /*!< DMAMUX1 CRYP OUT request        */
+#define LL_DMAMUX1_REQ_HASH_IN          78U  /*!< DMAMUX1 HASH IN request         */
+#define LL_DMAMUX1_REQ_UART7_RX         79U  /*!< DMAMUX1 UART7 RX request        */
+#define LL_DMAMUX1_REQ_UART7_TX         80U  /*!< DMAMUX1 UART7 TX request        */
+#define LL_DMAMUX1_REQ_UART8_RX         81U  /*!< DMAMUX1 UART8 RX request        */
+#define LL_DMAMUX1_REQ_UART8_TX         82U  /*!< DMAMUX1 UART8 TX request        */
+#define LL_DMAMUX1_REQ_SPI4_RX          83U  /*!< DMAMUX1 SPI4 RX request         */
+#define LL_DMAMUX1_REQ_SPI4_TX          84U  /*!< DMAMUX1 SPI4 TX request         */
+#define LL_DMAMUX1_REQ_SPI5_RX          85U  /*!< DMAMUX1 SPI5 RX request         */
+#define LL_DMAMUX1_REQ_SPI5_TX          86U  /*!< DMAMUX1 SPI5 TX request         */
+#define LL_DMAMUX1_REQ_SAI1_A           87U  /*!< DMAMUX1 SAI1 A request          */
+#define LL_DMAMUX1_REQ_SAI1_B           88U  /*!< DMAMUX1 SAI1 B request          */
+#define LL_DMAMUX1_REQ_SAI2_A           89U  /*!< DMAMUX1 SAI2 A request          */
+#define LL_DMAMUX1_REQ_SAI2_B           90U  /*!< DMAMUX1 SAI2 B request          */
+#define LL_DMAMUX1_REQ_SWPMI_RX         91U  /*!< DMAMUX1 SWPMI RX request        */
+#define LL_DMAMUX1_REQ_SWPMI_TX         92U  /*!< DMAMUX1 SWPMI TX request        */
+#define LL_DMAMUX1_REQ_SPDIF_RX_DT      93U  /*!< DMAMUX1 SPDIF RXDT request      */
+#define LL_DMAMUX1_REQ_SPDIF_RX_CS      94U  /*!< DMAMUX1 SPDIF RXCS request      */
+#if defined (HRTIM1)
+#define LL_DMAMUX1_REQ_HRTIM_MASTER     95U  /*!< DMAMUX1 HRTIM1 Master request 1 */
+#define LL_DMAMUX1_REQ_HRTIM_TIMER_A    96U  /*!< DMAMUX1 HRTIM1 TimerA request 2 */
+#define LL_DMAMUX1_REQ_HRTIM_TIMER_B    97U  /*!< DMAMUX1 HRTIM1 TimerB request 3 */
+#define LL_DMAMUX1_REQ_HRTIM_TIMER_C    98U  /*!< DMAMUX1 HRTIM1 TimerC request 4 */
+#define LL_DMAMUX1_REQ_HRTIM_TIMER_D    99U  /*!< DMAMUX1 HRTIM1 TimerD request 5 */
+#define LL_DMAMUX1_REQ_HRTIM_TIMER_E   100U  /*!< DMAMUX1 HRTIM1 TimerE request 6 */
+#endif /* HRTIM1 */
+#define LL_DMAMUX1_REQ_DFSDM1_FLT0     101U  /*!< DMAMUX1 DFSDM1 Filter0 request  */
+#define LL_DMAMUX1_REQ_DFSDM1_FLT1     102U  /*!< DMAMUX1 DFSDM1 Filter1 request  */
+#define LL_DMAMUX1_REQ_DFSDM1_FLT2     103U  /*!< DMAMUX1 DFSDM1 Filter2 request  */
+#define LL_DMAMUX1_REQ_DFSDM1_FLT3     104U  /*!< DMAMUX1 DFSDM1 Filter3 request  */
+#define LL_DMAMUX1_REQ_TIM15_CH1       105U  /*!< DMAMUX1 TIM15 CH1 request       */
+#define LL_DMAMUX1_REQ_TIM15_UP        106U  /*!< DMAMUX1 TIM15 UP request        */
+#define LL_DMAMUX1_REQ_TIM15_TRIG      107U  /*!< DMAMUX1 TIM15 TRIG request      */
+#define LL_DMAMUX1_REQ_TIM15_COM       108U  /*!< DMAMUX1 TIM15 COM request       */
+#define LL_DMAMUX1_REQ_TIM16_CH1       109U  /*!< DMAMUX1 TIM16 CH1 request       */
+#define LL_DMAMUX1_REQ_TIM16_UP        110U  /*!< DMAMUX1 TIM16 UP request        */
+#define LL_DMAMUX1_REQ_TIM17_CH1       111U  /*!< DMAMUX1 TIM17 CH1 request       */
+#define LL_DMAMUX1_REQ_TIM17_UP        112U  /*!< DMAMUX1 TIM17 UP request        */
+#if defined (SAI3)
+#define LL_DMAMUX1_REQ_SAI3_A          113U  /*!< DMAMUX1 SAI3 A request          */
+#define LL_DMAMUX1_REQ_SAI3_B          114U  /*!< DMAMUX1 SAI3 B request          */
+#endif /* SAI3 */
+#if defined (ADC3)
+#define LL_DMAMUX1_REQ_ADC3            115U  /*!< DMAMUX1 ADC3  request           */
+#endif /* ADC3 */
+#if defined (UART9)
+#define LL_DMAMUX1_REQ_UART9_RX        116U  /*!< DMAMUX1 UART9 RX request        */
+#define LL_DMAMUX1_REQ_UART9_TX        117U  /*!< DMAMUX1 UART9 TX request        */
+#endif /* UART9 */
+#if defined (USART10)
+#define LL_DMAMUX1_REQ_USART10_RX      118U  /*!< DMAMUX1 USART10 RX request      */
+#define LL_DMAMUX1_REQ_USART10_TX      119U  /*!< DMAMUX1 USART10 TX request      */
+#endif /* USART10 */
+
+/* DMAMUX2 requests */
+#define LL_DMAMUX2_REQ_MEM2MEM          0U  /*!< memory to memory transfer        */
+#define LL_DMAMUX2_REQ_GENERATOR0       1U  /*!< DMAMUX2 request generator 0      */
+#define LL_DMAMUX2_REQ_GENERATOR1       2U  /*!< DMAMUX2 request generator 1      */
+#define LL_DMAMUX2_REQ_GENERATOR2       3U  /*!< DMAMUX2 request generator 2      */
+#define LL_DMAMUX2_REQ_GENERATOR3       4U  /*!< DMAMUX2 request generator 3      */
+#define LL_DMAMUX2_REQ_GENERATOR4       5U  /*!< DMAMUX2 request generator 4      */
+#define LL_DMAMUX2_REQ_GENERATOR5       6U  /*!< DMAMUX2 request generator 5      */
+#define LL_DMAMUX2_REQ_GENERATOR6       7U  /*!< DMAMUX2 request generator 6      */
+#define LL_DMAMUX2_REQ_GENERATOR7       8U  /*!< DMAMUX2 request generator 7      */
+#define LL_DMAMUX2_REQ_LPUART1_RX       9U  /*!< DMAMUX2 LP_UART1_RX request      */
+#define LL_DMAMUX2_REQ_LPUART1_TX      10U  /*!< DMAMUX2 LP_UART1_TX request      */
+#define LL_DMAMUX2_REQ_SPI6_RX         11U  /*!< DMAMUX2 SPI6 RX request          */
+#define LL_DMAMUX2_REQ_SPI6_TX         12U  /*!< DMAMUX2 SPI6 TX request          */
+#define LL_DMAMUX2_REQ_I2C4_RX         13U  /*!< DMAMUX2 I2C4 RX request          */
+#define LL_DMAMUX2_REQ_I2C4_TX         14U  /*!< DMAMUX2 I2C4 TX request          */
+#if defined (SAI4)
+#define LL_DMAMUX2_REQ_SAI4_A          15U  /*!< DMAMUX2 SAI4 A request           */
+#define LL_DMAMUX2_REQ_SAI4_B          16U  /*!< DMAMUX2 SAI4 B request           */
+#endif /* SAI4 */
+#if defined (ADC3)
+#define LL_DMAMUX2_REQ_ADC3            17U  /*!< DMAMUX2 ADC3 request             */
+#endif /* ADC3 */
+#if defined (DAC2)
+#define LL_DMAMUX2_REQ_DAC2_CH1        17U  /*!< DMAMUX2 DAC2 CH1 request         */
+#endif /* DAC2 */
+#if defined (DFSDM2_Channel0)
+#define LL_DMAMUX2_REQ_DFSDM2_FLT0     18U  /*!< DMAMUX2 DFSDM2 Filter0 request   */
+#endif /* DFSDM2_Channel0 */
+/**
+  * @}
+  */
+
+
+/** @defgroup DMAMUX_LL_EC_CHANNEL DMAMUX Channel
+  * @{
+  */
+#define LL_DMAMUX_CHANNEL_0     0x00000000U  /*!< DMAMUX1 Channel 0  connected to DMA1 Channel 0 , DMAMUX2 Channel 0 connected to BDMA Channel 0 */
+#define LL_DMAMUX_CHANNEL_1     0x00000001U  /*!< DMAMUX1 Channel 1  connected to DMA1 Channel 1 , DMAMUX2 Channel 1 connected to BDMA Channel 1 */
+#define LL_DMAMUX_CHANNEL_2     0x00000002U  /*!< DMAMUX1 Channel 2  connected to DMA1 Channel 2 , DMAMUX2 Channel 2 connected to BDMA Channel 2 */
+#define LL_DMAMUX_CHANNEL_3     0x00000003U  /*!< DMAMUX1 Channel 3  connected to DMA1 Channel 3 , DMAMUX2 Channel 3 connected to BDMA Channel 3 */
+#define LL_DMAMUX_CHANNEL_4     0x00000004U  /*!< DMAMUX1 Channel 4  connected to DMA1 Channel 4 , DMAMUX2 Channel 4 connected to BDMA Channel 4 */
+#define LL_DMAMUX_CHANNEL_5     0x00000005U  /*!< DMAMUX1 Channel 5  connected to DMA1 Channel 5 , DMAMUX2 Channel 5 connected to BDMA Channel 5 */
+#define LL_DMAMUX_CHANNEL_6     0x00000006U  /*!< DMAMUX1 Channel 6  connected to DMA1 Channel 6 , DMAMUX2 Channel 6 connected to BDMA Channel 6 */
+#define LL_DMAMUX_CHANNEL_7     0x00000007U  /*!< DMAMUX1 Channel 7  connected to DMA1 Channel 7 , DMAMUX2 Channel 7 connected to BDMA Channel 7 */
+#define LL_DMAMUX_CHANNEL_8     0x00000008U  /*!< DMAMUX1 Channel 8  connected to DMA2 Channel 0 */
+#define LL_DMAMUX_CHANNEL_9     0x00000009U  /*!< DMAMUX1 Channel 9  connected to DMA2 Channel 1 */
+#define LL_DMAMUX_CHANNEL_10    0x0000000AU  /*!< DMAMUX1 Channel 10 connected to DMA2 Channel 2 */
+#define LL_DMAMUX_CHANNEL_11    0x0000000BU  /*!< DMAMUX1 Channel 11 connected to DMA2 Channel 3 */
+#define LL_DMAMUX_CHANNEL_12    0x0000000CU  /*!< DMAMUX1 Channel 12 connected to DMA2 Channel 4 */
+#define LL_DMAMUX_CHANNEL_13    0x0000000DU  /*!< DMAMUX1 Channel 13 connected to DMA2 Channel 5 */
+#define LL_DMAMUX_CHANNEL_14    0x0000000EU  /*!< DMAMUX1 Channel 14 connected to DMA2 Channel 6 */
+#define LL_DMAMUX_CHANNEL_15    0x0000000FU  /*!< DMAMUX1 Channel 15 connected to DMA2 Channel 7 */
+/**
+  * @}
+  */
+
+/** @defgroup DMAMUX_LL_EC_SYNC_NO Synchronization Signal Polarity
+  * @{
+  */
+#define LL_DMAMUX_SYNC_NO_EVENT            0x00000000U                               /*!< All requests are blocked                            */
+#define LL_DMAMUX_SYNC_POL_RISING          DMAMUX_CxCR_SPOL_0                        /*!< Synchronization on event on rising edge             */
+#define LL_DMAMUX_SYNC_POL_FALLING         DMAMUX_CxCR_SPOL_1                        /*!< Synchronization on event on falling edge            */
+#define LL_DMAMUX_SYNC_POL_RISING_FALLING  (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1) /*!< Synchronization on event on rising and falling edge */
+/**
+  * @}
+  */
+
+/** @defgroup DMAMUX_LL_EC_SYNC_EVT Synchronization Signal Event
+  * @{
+  */
+#define LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT   0x00000000U   /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel0 Event */
+#define LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT   0x01000000U   /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel1 Event */
+#define LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT   0x02000000U   /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel2 Event */
+#define LL_DMAMUX1_SYNC_LPTIM1_OUT        0x03000000U   /*!< DMAMUX1 synchronization Signal is LPTIM1 OUT             */
+#define LL_DMAMUX1_SYNC_LPTIM2_OUT        0x04000000U   /*!< DMAMUX1 synchronization Signal is LPTIM2 OUT             */
+#define LL_DMAMUX1_SYNC_LPTIM3_OUT        0x05000000U   /*!< DMAMUX1 synchronization Signal is LPTIM3 OUT             */
+#define LL_DMAMUX1_SYNC_EXTI0             0x06000000U   /*!< DMAMUX1 synchronization Signal is EXTI0 IT               */
+#define LL_DMAMUX1_SYNC_TIM12_TRGO        0x07000000U   /*!< DMAMUX1 synchronization Signal is TIM12 TRGO             */
+
+#define LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT   0x00000000U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel0 Event */
+#define LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT   0x01000000U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel1 Event */
+#define LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT   0x02000000U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel2 Event */
+#define LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT   0x03000000U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel3 Event */
+#define LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT   0x04000000U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel4 Event */
+#define LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT   0x05000000U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel5 Event */
+#define LL_DMAMUX2_SYNC_LPUART1_RX_WKUP   0x06000000U   /*!< DMAMUX2 synchronization Signal is LPUART1 RX Wakeup      */
+#define LL_DMAMUX2_SYNC_LPUART1_TX_WKUP   0x07000000U   /*!< DMAMUX2 synchronization Signal is LPUART1 TX Wakeup      */
+#define LL_DMAMUX2_SYNC_LPTIM2_OUT        0x08000000U   /*!< DMAMUX2 synchronization Signal is LPTIM2 output          */
+#define LL_DMAMUX2_SYNC_LPTIM3_OUT        0x09000000U   /*!< DMAMUX2 synchronization Signal is LPTIM3 output          */
+#define LL_DMAMUX2_SYNC_I2C4_WKUP         0x0A000000U   /*!< DMAMUX2 synchronization Signal is I2C4 Wakeup            */
+#define LL_DMAMUX2_SYNC_SPI6_WKUP         0x0B000000U   /*!< DMAMUX2 synchronization Signal is SPI6 Wakeup            */
+#define LL_DMAMUX2_SYNC_COMP1_OUT         0x0C000000U   /*!< DMAMUX2 synchronization Signal is Comparator 1 output    */
+#define LL_DMAMUX2_SYNC_RTC_WKUP          0x0D000000U   /*!< DMAMUX2 synchronization Signal is RTC Wakeup             */
+#define LL_DMAMUX2_SYNC_EXTI0             0x0E000000U   /*!< DMAMUX2 synchronization Signal is EXTI0 IT               */
+#define LL_DMAMUX2_SYNC_EXTI2             0x0F000000U   /*!< DMAMUX2 synchronization Signal is EXTI2 IT               */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMAMUX_LL_EC_REQUEST_GENERATOR Request Generator Channel
+  * @{
+  */
+#define LL_DMAMUX_REQ_GEN_0           0x00000000U
+#define LL_DMAMUX_REQ_GEN_1           0x00000001U
+#define LL_DMAMUX_REQ_GEN_2           0x00000002U
+#define LL_DMAMUX_REQ_GEN_3           0x00000003U
+#define LL_DMAMUX_REQ_GEN_4           0x00000004U
+#define LL_DMAMUX_REQ_GEN_5           0x00000005U
+#define LL_DMAMUX_REQ_GEN_6           0x00000006U
+#define LL_DMAMUX_REQ_GEN_7           0x00000007U
+/**
+  * @}
+  */
+
+/** @defgroup DMAMUX_LL_EC_REQUEST_GEN_POLARITY External Request Signal Generation Polarity
+  * @{
+  */
+#define LL_DMAMUX_REQ_GEN_NO_EVENT             0x00000000U                                  /*!< No external DMA request  generation                        */
+#define LL_DMAMUX_REQ_GEN_POL_RISING           DMAMUX_RGxCR_GPOL_0                          /*!< External DMA request generation on event on rising edge    */
+#define LL_DMAMUX_REQ_GEN_POL_FALLING          DMAMUX_RGxCR_GPOL_1                          /*!< External DMA request generation on event on falling edge   */
+#define LL_DMAMUX_REQ_GEN_POL_RISING_FALLING   (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1)  /*!< External DMA request generation on rising and falling edge */
+/**
+  * @}
+  */
+
+/** @defgroup DMAMUX_LL_EC_REQUEST_GEN External Request Signal Generation
+  * @{
+  */
+#define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT   0U   /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel0 Event        */
+#define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT   1U   /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel1 Event        */
+#define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT   2U   /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel2 Event        */
+#define LL_DMAMUX1_REQ_GEN_LPTIM1_OUT        3U   /*!< DMAMUX1 Request generator Signal is LPTIM1 OUT                    */
+#define LL_DMAMUX1_REQ_GEN_LPTIM2_OUT        4U   /*!< DMAMUX1 Request generator Signal is LPTIM2 OUT                    */
+#define LL_DMAMUX1_REQ_GEN_LPTIM3_OUT        5U   /*!< DMAMUX1 Request generator Signal is LPTIM3 OUT                    */
+#define LL_DMAMUX1_REQ_GEN_EXTI0             6U   /*!< DMAMUX1 Request generator Signal is EXTI0 IT                      */
+#define LL_DMAMUX1_REQ_GEN_TIM12_TRGO        7U   /*!< DMAMUX1 Request generator Signal is TIM12 TRGO                    */
+
+#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT   0U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel0 Event        */
+#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT   1U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel1 Event        */
+#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT   2U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel2 Event        */
+#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT   3U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel3 Event        */
+#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT   4U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel4 Event        */
+#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT   5U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel5 Event        */
+#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT   6U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel6 Event        */
+#define LL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP   7U   /*!< DMAMUX2 Request generator Signal is LPUART1 RX Wakeup             */
+#define LL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP   8U   /*!< DMAMUX2 Request generator Signal is LPUART1 TX Wakeup             */
+#define LL_DMAMUX2_REQ_GEN_LPTIM2_WKUP       9U   /*!< DMAMUX2 Request generator Signal is LPTIM2 Wakeup                 */
+#define LL_DMAMUX2_REQ_GEN_LPTIM2_OUT       10U   /*!< DMAMUX2 Request generator Signal is LPTIM2 OUT                    */
+#define LL_DMAMUX2_REQ_GEN_LPTIM3_WKUP      11U   /*!< DMAMUX2 Request generator Signal is LPTIM3 Wakeup                 */
+#define LL_DMAMUX2_REQ_GEN_LPTIM3_OUT       12U   /*!< DMAMUX2 Request generator Signal is LPTIM3 OUT                    */
+#if defined (LPTIM4)
+#define LL_DMAMUX2_REQ_GEN_LPTIM4_WKUP      13U   /*!< DMAMUX2 Request generator Signal is LPTIM4 Wakeup                 */
+#endif /* LPTIM4 */
+#if defined (LPTIM5)
+#define LL_DMAMUX2_REQ_GEN_LPTIM5_WKUP      14U   /*!< DMAMUX2 Request generator Signal is LPTIM5 Wakeup                 */
+#endif /* LPTIM5 */
+#define LL_DMAMUX2_REQ_GEN_I2C4_WKUP        15U   /*!< DMAMUX2 Request generator Signal is I2C4 Wakeup                   */
+#define LL_DMAMUX2_REQ_GEN_SPI6_WKUP        16U   /*!< DMAMUX2 Request generator Signal is SPI6 Wakeup                   */
+#define LL_DMAMUX2_REQ_GEN_COMP1_OUT        17U   /*!< DMAMUX2 Request generator Signal is Comparator 1 output           */
+#define LL_DMAMUX2_REQ_GEN_COMP2_OUT        18U   /*!< DMAMUX2 Request generator Signal is Comparator 2 output           */
+#define LL_DMAMUX2_REQ_GEN_RTC_WKUP         19U   /*!< DMAMUX2 Request generator Signal is RTC Wakeup                    */
+#define LL_DMAMUX2_REQ_GEN_EXTI0            20U   /*!< DMAMUX2 Request generator Signal is EXTI0                         */
+#define LL_DMAMUX2_REQ_GEN_EXTI2            21U   /*!< DMAMUX2 Request generator Signal is EXTI2                         */
+#define LL_DMAMUX2_REQ_GEN_I2C4_IT_EVT      22U   /*!< DMAMUX2 Request generator Signal is I2C4 IT Event                 */
+#define LL_DMAMUX2_REQ_GEN_SPI6_IT          23U   /*!< DMAMUX2 Request generator Signal is SPI6 IT                       */
+#define LL_DMAMUX2_REQ_GEN_LPUART1_TX_IT    24U   /*!< DMAMUX2 Request generator Signal is LPUART1 Tx IT                 */
+#define LL_DMAMUX2_REQ_GEN_LPUART1_RX_IT    25U   /*!< DMAMUX2 Request generator Signal is LPUART1 Rx IT                 */
+#if defined (ADC3)
+#define LL_DMAMUX2_REQ_GEN_ADC3_IT          26U   /*!< DMAMUX2 Request generator Signal is ADC3 IT                       */
+#define LL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT    27U   /*!< DMAMUX2 Request generator Signal is ADC3 Analog Watchdog 1 output */
+#endif /* ADC3 */
+#define LL_DMAMUX2_REQ_GEN_BDMA_CH0_IT      28U   /*!< DMAMUX2 Request generator Signal is BDMA Channel 0 IT             */
+#define LL_DMAMUX2_REQ_GEN_BDMA_CH1_IT      29U   /*!< DMAMUX2 Request generator Signal is BDMA Channel 1 IT             */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DMAMUX_LL_Exported_Macros DMAMUX Exported Macros
+  * @{
+  */
+
+/** @defgroup DMAMUX_LL_EM_WRITE_READ Common Write and read registers macros
+  * @{
+  */
+/**
+  * @brief  Write a value in DMAMUX register
+  * @param  __INSTANCE__ DMAMUX Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_DMAMUX_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in DMAMUX register
+  * @param  __INSTANCE__ DMAMUX Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_DMAMUX_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DMAMUX_LL_Exported_Functions DMAMUX Exported Functions
+ * @{
+ */
+
+/** @defgroup DMAMUX_LL_EF_Configuration Configuration
+  * @{
+  */
+/**
+  * @brief  Set DMAMUX request ID for DMAMUX Channel x.
+  * @note   DMAMUX1 channel 0 to 7 are mapped to DMA1 channel 0 to 7.
+  *         DMAMUX1 channel 8 to 15 are mapped to DMA2 channel 0 to 7.
+  *         DMAMUX2 channel 0 to 7 are mapped to  BDMA channel 0 to 7.
+  * @rmtoll CxCR         DMAREQ_ID     LL_DMAMUX_SetRequestID
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @param  Request This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX1_REQ_MEM2MEM
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR0
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR1
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR2
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR3
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR4
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR5
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR6
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR7
+  *         @arg @ref LL_DMAMUX1_REQ_ADC1
+  *         @arg @ref LL_DMAMUX1_REQ_ADC2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_COM
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_UP
+  *         @arg @ref LL_DMAMUX1_REQ_I2C1_RX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C1_TX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C2_RX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C2_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI1_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI1_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI2_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI2_TX
+  *         @arg @ref LL_DMAMUX1_REQ_USART1_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART1_TX
+  *         @arg @ref LL_DMAMUX1_REQ_USART2_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART2_TX
+  *         @arg @ref LL_DMAMUX1_REQ_USART3_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART3_TX
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_COM
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_SPI3_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI3_TX
+  *         @arg @ref LL_DMAMUX1_REQ_UART4_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART4_TX
+  *         @arg @ref LL_DMAMUX1_REQ_UART5_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART5_TX
+  *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM6_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM7_UP
+  *         @arg @ref LL_DMAMUX1_REQ_USART6_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART6_TX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C3_RX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C3_TX
+  *         @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI
+  *         @arg @ref LL_DMAMUX1_REQ_CRYP_IN
+  *         @arg @ref LL_DMAMUX1_REQ_CRYP_OUT
+  *         @arg @ref LL_DMAMUX1_REQ_HASH_IN
+  *         @arg @ref LL_DMAMUX1_REQ_UART7_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART7_TX
+  *         @arg @ref LL_DMAMUX1_REQ_UART8_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART8_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI4_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI4_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI5_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI5_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SAI1_A
+  *         @arg @ref LL_DMAMUX1_REQ_SAI1_B
+  *         @arg @ref LL_DMAMUX1_REQ_SAI2_A
+  *         @arg @ref LL_DMAMUX1_REQ_SAI2_B
+  *         @arg @ref LL_DMAMUX1_REQ_SWPMI_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SWPMI_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
+  *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*)
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_COM
+  *         @arg @ref LL_DMAMUX1_REQ_TIM16_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM16_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM17_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM17_UP
+  *         @arg @ref LL_DMAMUX1_REQ_SAI3_A (*)
+  *         @arg @ref LL_DMAMUX1_REQ_SAI3_B (*)
+  *         @arg @ref LL_DMAMUX1_REQ_ADC3 (*)
+  *         @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
+  *         @arg @ref LL_DMAMUX1_REQ_UART9_TX (*)
+  *         @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
+  *         @arg @ref LL_DMAMUX1_REQ_USART10_TX (*)
+  *         @arg @ref LL_DMAMUX2_REQ_MEM2MEM
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR0
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR1
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR2
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR3
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR4
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR5
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR6
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR7
+  *         @arg @ref LL_DMAMUX2_REQ_LPUART1_RX
+  *         @arg @ref LL_DMAMUX2_REQ_LPUART1_TX
+  *         @arg @ref LL_DMAMUX2_REQ_SPI6_RX
+  *         @arg @ref LL_DMAMUX2_REQ_SPI6_TX
+  *         @arg @ref LL_DMAMUX2_REQ_I2C4_RX
+  *         @arg @ref LL_DMAMUX2_REQ_I2C4_TX
+  *         @arg @ref LL_DMAMUX2_REQ_SAI4_A (*)
+  *         @arg @ref LL_DMAMUX2_REQ_SAI4_B (*)
+  *         @arg @ref LL_DMAMUX2_REQ_ADC3 (*)
+  *         @arg @ref LL_DMAMUX2_REQ_DAC2_CH1 (*)
+  *         @arg @ref LL_DMAMUX2_REQ_DFSDM2_FLT0 (*)
+  * @note   (*) Availability depends on devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
+}
+
+/**
+  * @brief  Get DMAMUX request ID for DMAMUX Channel x.
+  * @note   DMAMUX1 channel 0 to 7  are mapped to DMA1 channel 0 to 7.
+  *         DMAMUX1 channel 8 to 15 are mapped to DMA2 channel 0 to 7.
+  *         DMAMUX2 channel 0 to 7  are mapped to BDMA channel 0 to 7.
+  * @rmtoll CxCR         DMAREQ_ID     LL_DMAMUX_GetRequestID
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMAMUX1_REQ_MEM2MEM
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR0
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR1
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR2
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR3
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR4
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR5
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR6
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR7
+  *         @arg @ref LL_DMAMUX1_REQ_ADC1
+  *         @arg @ref LL_DMAMUX1_REQ_ADC2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_COM
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_UP
+  *         @arg @ref LL_DMAMUX1_REQ_I2C1_RX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C1_TX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C2_RX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C2_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI1_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI1_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI2_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI2_TX
+  *         @arg @ref LL_DMAMUX1_REQ_USART1_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART1_TX
+  *         @arg @ref LL_DMAMUX1_REQ_USART2_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART2_TX
+  *         @arg @ref LL_DMAMUX1_REQ_USART3_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART3_TX
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_COM
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_SPI3_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI3_TX
+  *         @arg @ref LL_DMAMUX1_REQ_UART4_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART4_TX
+  *         @arg @ref LL_DMAMUX1_REQ_UART5_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART5_TX
+  *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM6_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM7_UP
+  *         @arg @ref LL_DMAMUX1_REQ_USART6_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART6_TX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C3_RX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C3_TX
+  *         @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI
+  *         @arg @ref LL_DMAMUX1_REQ_CRYP_IN
+  *         @arg @ref LL_DMAMUX1_REQ_CRYP_OUT
+  *         @arg @ref LL_DMAMUX1_REQ_HASH_IN
+  *         @arg @ref LL_DMAMUX1_REQ_UART7_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART7_TX
+  *         @arg @ref LL_DMAMUX1_REQ_UART8_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART8_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI4_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI4_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI5_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI5_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SAI1_A
+  *         @arg @ref LL_DMAMUX1_REQ_SAI1_B
+  *         @arg @ref LL_DMAMUX1_REQ_SAI2_A
+  *         @arg @ref LL_DMAMUX1_REQ_SAI2_B
+  *         @arg @ref LL_DMAMUX1_REQ_SWPMI_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SWPMI_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
+  *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*)
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_COM
+  *         @arg @ref LL_DMAMUX1_REQ_TIM16_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM16_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM17_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM17_UP
+  *         @arg @ref LL_DMAMUX1_REQ_SAI3_A (*)
+  *         @arg @ref LL_DMAMUX1_REQ_SAI3_B (*)
+  *         @arg @ref LL_DMAMUX1_REQ_ADC3 (*)
+  *         @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
+  *         @arg @ref LL_DMAMUX1_REQ_UART9_TX (*)
+  *         @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
+  *         @arg @ref LL_DMAMUX1_REQ_USART10_TX (*)
+  *         @arg @ref LL_DMAMUX2_REQ_MEM2MEM
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR0
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR1
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR2
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR3
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR4
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR5
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR6
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR7
+  *         @arg @ref LL_DMAMUX2_REQ_LPUART1_RX
+  *         @arg @ref LL_DMAMUX2_REQ_LPUART1_TX
+  *         @arg @ref LL_DMAMUX2_REQ_SPI6_RX
+  *         @arg @ref LL_DMAMUX2_REQ_SPI6_TX
+  *         @arg @ref LL_DMAMUX2_REQ_I2C4_RX
+  *         @arg @ref LL_DMAMUX2_REQ_I2C4_TX
+  *         @arg @ref LL_DMAMUX2_REQ_SAI4_A (*)
+  *         @arg @ref LL_DMAMUX2_REQ_SAI4_B (*)
+  *         @arg @ref LL_DMAMUX2_REQ_ADC3 (*)
+  *         @arg @ref LL_DMAMUX2_REQ_DAC2_CH1 (*)
+  *         @arg @ref LL_DMAMUX2_REQ_DFSDM2_FLT0 (*)
+  * @note   (*) Availability depends on devices.
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID));
+}
+
+/**
+  * @brief  Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
+  * @rmtoll CxCR         NBREQ         LL_DMAMUX_SetSyncRequestNb
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @param  RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_NBREQ, (RequestNb - 1U) << DMAMUX_CxCR_NBREQ_Pos);
+}
+
+/**
+  * @brief  Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
+  * @rmtoll CxCR         NBREQ         LL_DMAMUX_GetSyncRequestNb
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval Between Min_Data = 1 and Max_Data = 32
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return (uint32_t)((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_NBREQ) >> DMAMUX_CxCR_NBREQ_Pos) + 1U);
+}
+
+/**
+  * @brief  Set the polarity of the signal on which the DMA request is synchronized.
+  * @rmtoll CxCR         SPOL          LL_DMAMUX_SetSyncPolarity
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_SYNC_NO_EVENT
+  *         @arg @ref LL_DMAMUX_SYNC_POL_RISING
+  *         @arg @ref LL_DMAMUX_SYNC_POL_FALLING
+  *         @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SPOL, Polarity);
+}
+
+/**
+  * @brief  Get the polarity of the signal on which the DMA request is synchronized.
+  * @rmtoll CxCR         SPOL          LL_DMAMUX_GetSyncPolarity
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMAMUX_SYNC_NO_EVENT
+  *         @arg @ref LL_DMAMUX_SYNC_POL_RISING
+  *         @arg @ref LL_DMAMUX_SYNC_POL_FALLING
+  *         @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SPOL));
+}
+
+/**
+  * @brief  Enable the Event Generation on DMAMUX channel x.
+  * @rmtoll CxCR         EGE           LL_DMAMUX_EnableEventGeneration
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE);
+}
+
+/**
+  * @brief  Disable the Event Generation on DMAMUX channel x.
+  * @rmtoll CxCR         EGE           LL_DMAMUX_DisableEventGeneration
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  CLEAR_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE);
+}
+
+/**
+  * @brief  Check if the Event Generation on DMAMUX channel x is enabled or disabled.
+  * @rmtoll CxCR         EGE           LL_DMAMUX_IsEnabledEventGeneration
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the synchronization mode.
+  * @rmtoll CxCR         SE            LL_DMAMUX_EnableSync
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE);
+}
+
+/**
+  * @brief  Disable the synchronization mode.
+  * @rmtoll CxCR         SE            LL_DMAMUX_DisableSync
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  CLEAR_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE);
+}
+
+/**
+  * @brief  Check if the synchronization mode is enabled or disabled.
+  * @rmtoll CxCR         SE            LL_DMAMUX_IsEnabledSync
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set DMAMUX synchronization ID  on DMAMUX Channel x.
+  * @rmtoll CxCR         SYNC_ID       LL_DMAMUX_SetSyncID
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @param  SyncID This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT
+  *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT
+  *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT
+  *         @arg @ref LL_DMAMUX1_SYNC_LPTIM1_OUT
+  *         @arg @ref LL_DMAMUX1_SYNC_LPTIM2_OUT
+  *         @arg @ref LL_DMAMUX1_SYNC_LPTIM3_OUT
+  *         @arg @ref LL_DMAMUX1_SYNC_EXTI0
+  *         @arg @ref LL_DMAMUX1_SYNC_TIM12_TRGO
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_LPUART1_RX_WKUP
+  *         @arg @ref LL_DMAMUX2_SYNC_LPUART1_TX_WKUP
+  *         @arg @ref LL_DMAMUX2_SYNC_LPTIM2_OUT
+  *         @arg @ref LL_DMAMUX2_SYNC_LPTIM3_OUT
+  *         @arg @ref LL_DMAMUX2_SYNC_I2C4_WKUP
+  *         @arg @ref LL_DMAMUX2_SYNC_SPI6_WKUP
+  *         @arg @ref LL_DMAMUX2_SYNC_COMP1_OUT
+  *         @arg @ref LL_DMAMUX2_SYNC_RTC_WKUP
+  *         @arg @ref LL_DMAMUX2_SYNC_EXTI0
+  *         @arg @ref LL_DMAMUX2_SYNC_EXTI2
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SYNC_ID, SyncID);
+}
+
+/**
+  * @brief  Get DMAMUX synchronization ID  on DMAMUX Channel x.
+  * @rmtoll CxCR         SYNC_ID       LL_DMAMUX_GetSyncID
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT
+  *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT
+  *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT
+  *         @arg @ref LL_DMAMUX1_SYNC_LPTIM1_OUT
+  *         @arg @ref LL_DMAMUX1_SYNC_LPTIM2_OUT
+  *         @arg @ref LL_DMAMUX1_SYNC_LPTIM3_OUT
+  *         @arg @ref LL_DMAMUX1_SYNC_EXTI0
+  *         @arg @ref LL_DMAMUX1_SYNC_TIM12_TRGO
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_LPUART1_RX_WKUP
+  *         @arg @ref LL_DMAMUX2_SYNC_LPUART1_TX_WKUP
+  *         @arg @ref LL_DMAMUX2_SYNC_LPTIM2_OUT
+  *         @arg @ref LL_DMAMUX2_SYNC_LPTIM3_OUT
+  *         @arg @ref LL_DMAMUX2_SYNC_I2C4_WKUP
+  *         @arg @ref LL_DMAMUX2_SYNC_SPI6_WKUP
+  *         @arg @ref LL_DMAMUX2_SYNC_COMP1_OUT
+  *         @arg @ref LL_DMAMUX2_SYNC_RTC_WKUP
+  *         @arg @ref LL_DMAMUX2_SYNC_EXTI0
+  *         @arg @ref LL_DMAMUX2_SYNC_EXTI2
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SYNC_ID));
+}
+
+/**
+  * @brief  Enable the Request Generator.
+  * @rmtoll RGxCR        GE            LL_DMAMUX_EnableRequestGen
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  *         @arg @ref LL_DMAMUX_REQ_GEN_4
+  *         @arg @ref LL_DMAMUX_REQ_GEN_5
+  *         @arg @ref LL_DMAMUX_REQ_GEN_6
+  *         @arg @ref LL_DMAMUX_REQ_GEN_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * (RequestGenChannel))))->RGCR, DMAMUX_RGxCR_GE);
+}
+
+/**
+  * @brief  Disable the Request Generator.
+  * @rmtoll RGxCR        GE            LL_DMAMUX_DisableRequestGen
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * (RequestGenChannel))))->RGCR, DMAMUX_RGxCR_GE);
+}
+
+/**
+  * @brief  Check if the Request Generator is enabled or disabled.
+  * @rmtoll RGxCR        GE            LL_DMAMUX_IsEnabledRequestGen
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  *         @arg @ref LL_DMAMUX_REQ_GEN_4
+  *         @arg @ref LL_DMAMUX_REQ_GEN_5
+  *         @arg @ref LL_DMAMUX_REQ_GEN_6
+  *         @arg @ref LL_DMAMUX_REQ_GEN_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the polarity of the signal on which the DMA request is generated.
+  * @rmtoll RGxCR        GPOL          LL_DMAMUX_SetRequestGenPolarity
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  *         @arg @ref LL_DMAMUX_REQ_GEN_4
+  *         @arg @ref LL_DMAMUX_REQ_GEN_5
+  *         @arg @ref LL_DMAMUX_REQ_GEN_6
+  *         @arg @ref LL_DMAMUX_REQ_GEN_7
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
+  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
+  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
+  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GPOL, Polarity);
+}
+
+/**
+  * @brief  Get the polarity of the signal on which the DMA request is generated.
+  * @rmtoll RGxCR        GPOL          LL_DMAMUX_GetRequestGenPolarity
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  *         @arg @ref LL_DMAMUX_REQ_GEN_4
+  *         @arg @ref LL_DMAMUX_REQ_GEN_5
+  *         @arg @ref LL_DMAMUX_REQ_GEN_6
+  *         @arg @ref LL_DMAMUX_REQ_GEN_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
+  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
+  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
+  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GPOL));
+}
+
+/**
+  * @brief  Set the number of DMA request that will be autorized after a generation event.
+  * @note   This field can only be written when Generator is disabled.
+  * @rmtoll RGxCR        GNBREQ        LL_DMAMUX_SetGenRequestNb
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  *         @arg @ref LL_DMAMUX_REQ_GEN_4
+  *         @arg @ref LL_DMAMUX_REQ_GEN_5
+  *         @arg @ref LL_DMAMUX_REQ_GEN_6
+  *         @arg @ref LL_DMAMUX_REQ_GEN_7
+  * @param  RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GNBREQ, (RequestNb - 1U) << DMAMUX_RGxCR_GNBREQ_Pos);
+}
+
+/**
+  * @brief  Get the number of DMA request that will be autorized after a generation event.
+  * @rmtoll RGxCR        GNBREQ        LL_DMAMUX_GetGenRequestNb
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  *         @arg @ref LL_DMAMUX_REQ_GEN_4
+  *         @arg @ref LL_DMAMUX_REQ_GEN_5
+  *         @arg @ref LL_DMAMUX_REQ_GEN_6
+  *         @arg @ref LL_DMAMUX_REQ_GEN_7
+  * @retval Between Min_Data = 1 and Max_Data = 32
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return (uint32_t)((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1U);
+}
+
+/**
+  * @brief  Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x.
+  * @rmtoll RGxCR        SIG_ID        LL_DMAMUX_SetRequestSignalID
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  *         @arg @ref LL_DMAMUX_REQ_GEN_4
+  *         @arg @ref LL_DMAMUX_REQ_GEN_5
+  *         @arg @ref LL_DMAMUX_REQ_GEN_6
+  *         @arg @ref LL_DMAMUX_REQ_GEN_7
+  * @param  RequestSignalID This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
+  *         @arg @ref LL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
+  *         @arg @ref LL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
+  *         @arg @ref LL_DMAMUX1_REQ_GEN_LPTIM1_OUT
+  *         @arg @ref LL_DMAMUX1_REQ_GEN_LPTIM2_OUT
+  *         @arg @ref LL_DMAMUX1_REQ_GEN_LPTIM3_OUT
+  *         @arg @ref LL_DMAMUX1_REQ_GEN_EXTI0
+  *         @arg @ref LL_DMAMUX1_REQ_GEN_TIM12_TRGO
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM2_OUT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM3_OUT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM4_WKUP (*)
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM5_WKUP (*)
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_I2C4_WKUP
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_SPI6_WKUP
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_COMP1_OUT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_COMP2_OUT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_RTC_WKUP
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_EXTI0
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_EXTI2
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_SPI6_IT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_ADC3_IT (*)
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT (*)
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
+  * @note   (*) Availability depends on devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_SIG_ID, RequestSignalID);
+}
+
+/**
+  * @brief  Get DMAMUX external Request Signal ID set on DMAMUX Channel x.
+  * @rmtoll RGxCR        SIG_ID        LL_DMAMUX_GetRequestSignalID
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  *         @arg @ref LL_DMAMUX_REQ_GEN_4
+  *         @arg @ref LL_DMAMUX_REQ_GEN_5
+  *         @arg @ref LL_DMAMUX_REQ_GEN_6
+  *         @arg @ref LL_DMAMUX_REQ_GEN_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT
+  *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT
+  *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT
+  *         @arg @ref LL_DMAMUX1_SYNC_LPTIM1_OUT
+  *         @arg @ref LL_DMAMUX1_SYNC_LPTIM2_OUT
+  *         @arg @ref LL_DMAMUX1_SYNC_LPTIM3_OUT
+  *         @arg @ref LL_DMAMUX1_SYNC_EXTI0
+  *         @arg @ref LL_DMAMUX1_SYNC_TIM12_TRGO
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_LPUART1_RX_WKUP
+  *         @arg @ref LL_DMAMUX2_SYNC_LPUART1_TX_WKUP
+  *         @arg @ref LL_DMAMUX2_SYNC_LPTIM2_OUT
+  *         @arg @ref LL_DMAMUX2_SYNC_LPTIM3_OUT
+  *         @arg @ref LL_DMAMUX2_SYNC_I2C4_WKUP
+  *         @arg @ref LL_DMAMUX2_SYNC_SPI6_WKUP
+  *         @arg @ref LL_DMAMUX2_SYNC_COMP1_OUT
+  *         @arg @ref LL_DMAMUX2_SYNC_RTC_WKUP
+  *         @arg @ref LL_DMAMUX2_SYNC_EXTI0
+  *         @arg @ref LL_DMAMUX2_SYNC_EXTI2
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_SIG_ID));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMAMUX_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 0.
+  * @rmtoll CSR          SOF0          LL_DMAMUX_IsActiveFlag_SO0
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF0) == (DMAMUX_CSR_SOF0)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 1.
+  * @rmtoll CSR          SOF1          LL_DMAMUX_IsActiveFlag_SO1
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF1) == (DMAMUX_CSR_SOF1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 2.
+  * @rmtoll CSR          SOF2          LL_DMAMUX_IsActiveFlag_SO2
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF2) == (DMAMUX_CSR_SOF2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 3.
+  * @rmtoll CSR          SOF3          LL_DMAMUX_IsActiveFlag_SO3
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF3) == (DMAMUX_CSR_SOF3)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 4.
+  * @rmtoll CSR          SOF4          LL_DMAMUX_IsActiveFlag_SO4
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF4) == (DMAMUX_CSR_SOF4)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 5.
+  * @rmtoll CSR          SOF5          LL_DMAMUX_IsActiveFlag_SO5
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF5) == (DMAMUX_CSR_SOF5)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 6.
+  * @rmtoll CSR          SOF6          LL_DMAMUX_IsActiveFlag_SO6
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 7.
+  * @rmtoll CSR          SOF7          LL_DMAMUX_IsActiveFlag_SO7
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 8.
+  * @rmtoll CSR          SOF8          LL_DMAMUX_IsActiveFlag_SO8
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 9.
+  * @rmtoll CSR          SOF9          LL_DMAMUX_IsActiveFlag_SO9
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 10.
+  * @rmtoll CSR          SOF10         LL_DMAMUX_IsActiveFlag_SO10
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 11.
+  * @rmtoll CSR          SOF11         LL_DMAMUX_IsActiveFlag_SO11
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 12.
+  * @rmtoll CSR          SOF12         LL_DMAMUX_IsActiveFlag_SO12
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF12) == (DMAMUX_CSR_SOF12)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 13.
+  * @rmtoll CSR          SOF13         LL_DMAMUX_IsActiveFlag_SO13
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF13) == (DMAMUX_CSR_SOF13)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 14.
+  * @rmtoll CSR          SOF14         LL_DMAMUX_IsActiveFlag_SO14
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF14) == (DMAMUX_CSR_SOF14)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 15.
+  * @rmtoll CSR          SOF15         LL_DMAMUX_IsActiveFlag_SO15
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF15) == (DMAMUX_CSR_SOF15)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Request Generator 0 Trigger Event Overrun Flag.
+  * @rmtoll RGSR         OF0           LL_DMAMUX_IsActiveFlag_RGO0
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF0) == (DMAMUX_RGSR_OF0)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Request Generator 1 Trigger Event Overrun Flag.
+  * @rmtoll RGSR         OF1           LL_DMAMUX_IsActiveFlag_RGO1
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF1) == (DMAMUX_RGSR_OF1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Request Generator 2 Trigger Event Overrun Flag.
+  * @rmtoll RGSR         OF2           LL_DMAMUX_IsActiveFlag_RGO2
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF2) == (DMAMUX_RGSR_OF2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Request Generator 3 Trigger Event Overrun Flag.
+  * @rmtoll RGSR         OF3           LL_DMAMUX_IsActiveFlag_RGO3
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF3) == (DMAMUX_RGSR_OF3)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Request Generator 4 Trigger Event Overrun Flag.
+  * @rmtoll RGSR         OF4           LL_DMAMUX_IsActiveFlag_RGO4
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO4(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF4) == (DMAMUX_RGSR_OF4)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Request Generator 5 Trigger Event Overrun Flag.
+  * @rmtoll RGSR         OF5           LL_DMAMUX_IsActiveFlag_RGO5
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO5(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF5) == (DMAMUX_RGSR_OF5)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Request Generator 6 Trigger Event Overrun Flag.
+  * @rmtoll RGSR         OF6           LL_DMAMUX_IsActiveFlag_RGO6
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO6(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF6) == (DMAMUX_RGSR_OF6)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Request Generator 7 Trigger Event Overrun Flag.
+  * @rmtoll RGSR         OF7           LL_DMAMUX_IsActiveFlag_RGO7
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO7(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF7) == (DMAMUX_RGSR_OF7)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 0.
+  * @rmtoll CFR          CSOF0         LL_DMAMUX_ClearFlag_SO0
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF0);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 1.
+  * @rmtoll CFR          CSOF1         LL_DMAMUX_ClearFlag_SO1
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF1);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 2.
+  * @rmtoll CFR          CSOF2         LL_DMAMUX_ClearFlag_SO2
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF2);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 3.
+  * @rmtoll CFR          CSOF3         LL_DMAMUX_ClearFlag_SO3
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF3);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 4.
+  * @rmtoll CFR          CSOF4         LL_DMAMUX_ClearFlag_SO4
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF4);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 5.
+  * @rmtoll CFR          CSOF5         LL_DMAMUX_ClearFlag_SO5
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF5);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 6.
+  * @rmtoll CFR          CSOF6         LL_DMAMUX_ClearFlag_SO6
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF6);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 7.
+  * @rmtoll CFR          CSOF7         LL_DMAMUX_ClearFlag_SO7
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF7);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 8.
+  * @rmtoll CFR          CSOF8         LL_DMAMUX_ClearFlag_SO8
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF8);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 9.
+  * @rmtoll CFR          CSOF9         LL_DMAMUX_ClearFlag_SO9
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF9);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 10.
+  * @rmtoll CFR          CSOF10        LL_DMAMUX_ClearFlag_SO10
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF10);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 11.
+  * @rmtoll CFR          CSOF11        LL_DMAMUX_ClearFlag_SO11
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF11);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 12.
+  * @rmtoll CFR          CSOF12        LL_DMAMUX_ClearFlag_SO12
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF12);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 13.
+  * @rmtoll CFR          CSOF13        LL_DMAMUX_ClearFlag_SO13
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF13);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 14.
+  * @rmtoll CFR          CSOF14        LL_DMAMUX_ClearFlag_SO14
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF14);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 15.
+  * @rmtoll CFR          CSOF15        LL_DMAMUX_ClearFlag_SO15
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF15);
+}
+
+/**
+  * @brief  Clear Request Generator 0 Trigger Event Overrun Flag.
+  * @rmtoll RGCFR        COF0          LL_DMAMUX_ClearFlag_RGO0
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF0);
+}
+
+/**
+  * @brief  Clear Request Generator 1 Trigger Event Overrun Flag.
+  * @rmtoll RGCFR        COF1          LL_DMAMUX_ClearFlag_RGO1
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF1);
+}
+
+/**
+  * @brief  Clear Request Generator 2 Trigger Event Overrun Flag.
+  * @rmtoll RGCFR        COF2          LL_DMAMUX_ClearFlag_RGO2
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF2);
+}
+
+/**
+  * @brief  Clear Request Generator 3 Trigger Event Overrun Flag.
+  * @rmtoll RGCFR        COF3          LL_DMAMUX_ClearFlag_RGO3
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF3);
+}
+
+/**
+  * @brief  Clear Request Generator 4 Trigger Event Overrun Flag.
+  * @rmtoll RGCFR        COF4          LL_DMAMUX_ClearFlag_RGO4
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO4(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF4);
+}
+
+/**
+  * @brief  Clear Request Generator 5 Trigger Event Overrun Flag.
+  * @rmtoll RGCFR        COF5          LL_DMAMUX_ClearFlag_RGO5
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO5(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF5);
+}
+
+/**
+  * @brief  Clear Request Generator 6 Trigger Event Overrun Flag.
+  * @rmtoll RGCFR        COF6          LL_DMAMUX_ClearFlag_RGO6
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO6(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF6);
+}
+
+/**
+  * @brief  Clear Request Generator 7 Trigger Event Overrun Flag.
+  * @rmtoll RGCFR        COF7          LL_DMAMUX_ClearFlag_RGO7
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO7(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF7);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMAMUX_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
+  * @rmtoll CxCR         SOIE          LL_DMAMUX_EnableIT_SO
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SOIE);
+}
+
+/**
+  * @brief  Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
+  * @rmtoll CxCR         SOIE          LL_DMAMUX_DisableIT_SO
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  CLEAR_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SOIE);
+}
+
+/**
+  * @brief  Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
+  * @rmtoll CxCR         SOIE          LL_DMAMUX_IsEnabledIT_SO
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return (READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SOIE));
+}
+
+/**
+  * @brief  Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
+  * @rmtoll RGxCR        OIE           LL_DMAMUX_EnableIT_RGO
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  *         @arg @ref LL_DMAMUX_REQ_GEN_4
+  *         @arg @ref LL_DMAMUX_REQ_GEN_5
+  *         @arg @ref LL_DMAMUX_REQ_GEN_6
+  *         @arg @ref LL_DMAMUX_REQ_GEN_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE);
+}
+
+/**
+  * @brief  Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
+  * @rmtoll RGxCR        OIE           LL_DMAMUX_DisableIT_RGO
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  *         @arg @ref LL_DMAMUX_REQ_GEN_4
+  *         @arg @ref LL_DMAMUX_REQ_GEN_5
+  *         @arg @ref LL_DMAMUX_REQ_GEN_6
+  *         @arg @ref LL_DMAMUX_REQ_GEN_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE);
+}
+
+/**
+  * @brief  Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
+  * @rmtoll RGxCR        OIE           LL_DMAMUX_IsEnabledIT_RGO
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  *         @arg @ref LL_DMAMUX_REQ_GEN_4
+  *         @arg @ref LL_DMAMUX_REQ_GEN_5
+  *         @arg @ref LL_DMAMUX_REQ_GEN_6
+  *         @arg @ref LL_DMAMUX_REQ_GEN_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* DMAMUX1 || DMAMUX2 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32H7xx_LL_DMAMUX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_exti.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_exti.h
new file mode 100644
index 00000000..294f03a6
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_exti.h
@@ -0,0 +1,3159 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_exti.h
+  * @author  MCD Application Team
+  * @brief   Header file of EXTI LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32H7xx_LL_EXTI_H
+#define __STM32H7xx_LL_EXTI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined (EXTI)
+
+/** @defgroup EXTI_LL EXTI
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private Macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
+  * @{
+  */
+typedef struct
+{
+
+  uint32_t Line_0_31;           /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31
+                                     This parameter can be any combination of @ref EXTI_LL_EC_LINE */
+
+  uint32_t Line_32_63;          /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 32 to 63
+                                     This parameter can be any combination of @ref EXTI_LL_EC_LINE */
+
+  uint32_t Line_64_95;          /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 64 to 95
+                                     This parameter can be any combination of @ref EXTI_LL_EC_LINE */
+
+  FunctionalState LineCommand;  /*!< Specifies the new state of the selected EXTI lines.
+                                     This parameter can be set either to ENABLE or DISABLE */
+
+  uint8_t Mode;                 /*!< Specifies the mode for the EXTI lines.
+                                     This parameter can be a value of @ref EXTI_LL_EC_MODE. */
+
+  uint8_t Trigger;              /*!< Specifies the trigger signal active edge for the EXTI lines.
+                                     This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
+} LL_EXTI_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
+  * @{
+  */
+
+/** @defgroup EXTI_LL_EC_LINE LINE
+  * @{
+  */
+#define LL_EXTI_LINE_0                 EXTI_IMR1_IM0           /*!< Extended line 0 */
+#define LL_EXTI_LINE_1                 EXTI_IMR1_IM1           /*!< Extended line 1 */
+#define LL_EXTI_LINE_2                 EXTI_IMR1_IM2           /*!< Extended line 2 */
+#define LL_EXTI_LINE_3                 EXTI_IMR1_IM3           /*!< Extended line 3 */
+#define LL_EXTI_LINE_4                 EXTI_IMR1_IM4           /*!< Extended line 4 */
+#define LL_EXTI_LINE_5                 EXTI_IMR1_IM5           /*!< Extended line 5 */
+#define LL_EXTI_LINE_6                 EXTI_IMR1_IM6           /*!< Extended line 6 */
+#define LL_EXTI_LINE_7                 EXTI_IMR1_IM7           /*!< Extended line 7 */
+#define LL_EXTI_LINE_8                 EXTI_IMR1_IM8           /*!< Extended line 8 */
+#define LL_EXTI_LINE_9                 EXTI_IMR1_IM9           /*!< Extended line 9 */
+#define LL_EXTI_LINE_10                EXTI_IMR1_IM10          /*!< Extended line 10 */
+#define LL_EXTI_LINE_11                EXTI_IMR1_IM11          /*!< Extended line 11 */
+#define LL_EXTI_LINE_12                EXTI_IMR1_IM12          /*!< Extended line 12 */
+#define LL_EXTI_LINE_13                EXTI_IMR1_IM13          /*!< Extended line 13 */
+#define LL_EXTI_LINE_14                EXTI_IMR1_IM14          /*!< Extended line 14 */
+#define LL_EXTI_LINE_15                EXTI_IMR1_IM15          /*!< Extended line 15 */
+#define LL_EXTI_LINE_16                EXTI_IMR1_IM16          /*!< Extended line 16 */
+#define LL_EXTI_LINE_17                EXTI_IMR1_IM17          /*!< Extended line 17 */
+#define LL_EXTI_LINE_18                EXTI_IMR1_IM18          /*!< Extended line 18 */
+#define LL_EXTI_LINE_19                EXTI_IMR1_IM19          /*!< Extended line 19 */
+#define LL_EXTI_LINE_20                EXTI_IMR1_IM20          /*!< Extended line 20 */
+#define LL_EXTI_LINE_21                EXTI_IMR1_IM21          /*!< Extended line 21 */
+#define LL_EXTI_LINE_22                EXTI_IMR1_IM22          /*!< Extended line 22 */
+#define LL_EXTI_LINE_23                EXTI_IMR1_IM23          /*!< Extended line 23 */
+#define LL_EXTI_LINE_24                EXTI_IMR1_IM24          /*!< Extended line 24 */
+#define LL_EXTI_LINE_25                EXTI_IMR1_IM25          /*!< Extended line 25 */
+#define LL_EXTI_LINE_26                EXTI_IMR1_IM26          /*!< Extended line 26 */
+#define LL_EXTI_LINE_27                EXTI_IMR1_IM27          /*!< Extended line 27 */
+#define LL_EXTI_LINE_28                EXTI_IMR1_IM28          /*!< Extended line 28 */
+#define LL_EXTI_LINE_29                EXTI_IMR1_IM29          /*!< Extended line 29 */
+#define LL_EXTI_LINE_30                EXTI_IMR1_IM30          /*!< Extended line 30 */
+#define LL_EXTI_LINE_31                EXTI_IMR1_IM31          /*!< Extended line 31 */
+#define LL_EXTI_LINE_ALL_0_31          EXTI_IMR1_IM            /*!< All Extended line not reserved*/
+
+#define LL_EXTI_LINE_32                EXTI_IMR2_IM32          /*!< Extended line 32 */
+#define LL_EXTI_LINE_33                EXTI_IMR2_IM33          /*!< Extended line 33 */
+#define LL_EXTI_LINE_34                EXTI_IMR2_IM34          /*!< Extended line 34 */
+#define LL_EXTI_LINE_35                EXTI_IMR2_IM35          /*!< Extended line 35 */
+#define LL_EXTI_LINE_36                EXTI_IMR2_IM36          /*!< Extended line 36 */
+#define LL_EXTI_LINE_37                EXTI_IMR2_IM37          /*!< Extended line 37 */
+#define LL_EXTI_LINE_38                EXTI_IMR2_IM38          /*!< Extended line 38 */
+#define LL_EXTI_LINE_39                EXTI_IMR2_IM39          /*!< Extended line 39 */
+#define LL_EXTI_LINE_40                EXTI_IMR2_IM40          /*!< Extended line 40 */
+#define LL_EXTI_LINE_41                EXTI_IMR2_IM41          /*!< Extended line 41 */
+#define LL_EXTI_LINE_42                EXTI_IMR2_IM42          /*!< Extended line 42 */
+#define LL_EXTI_LINE_43                EXTI_IMR2_IM43          /*!< Extended line 43 */
+#if defined(USB2_OTG_FS)
+#define LL_EXTI_LINE_44                EXTI_IMR2_IM44          /*!< Extended line 44 */
+#endif /* USB2_OTG_FS */
+#if defined(DSI)
+#define LL_EXTI_LINE_46                EXTI_IMR2_IM46          /*!< Extended line 46 */
+#endif /* DSI */
+#define LL_EXTI_LINE_47                EXTI_IMR2_IM47          /*!< Extended line 47 */
+#define LL_EXTI_LINE_48                EXTI_IMR2_IM48          /*!< Extended line 48 */
+#define LL_EXTI_LINE_49                EXTI_IMR2_IM49          /*!< Extended line 49 */
+#define LL_EXTI_LINE_50                EXTI_IMR2_IM50          /*!< Extended line 50 */
+#define LL_EXTI_LINE_51                EXTI_IMR2_IM51          /*!< Extended line 51 */
+#define LL_EXTI_LINE_52                EXTI_IMR2_IM52          /*!< Extended line 52 */
+#define LL_EXTI_LINE_53                EXTI_IMR2_IM53          /*!< Extended line 53 */
+#define LL_EXTI_LINE_54                EXTI_IMR2_IM54          /*!< Extended line 54 */
+#define LL_EXTI_LINE_55                EXTI_IMR2_IM55          /*!< Extended line 55 */
+#define LL_EXTI_LINE_56                EXTI_IMR2_IM56          /*!< Extended line 56 */
+#define LL_EXTI_LINE_57                EXTI_IMR2_IM57          /*!< Extended line 57 */
+#define LL_EXTI_LINE_58                EXTI_IMR2_IM58          /*!< Extended line 58 */
+#define LL_EXTI_LINE_59                EXTI_IMR2_IM59          /*!< Extended line 59 */
+#define LL_EXTI_LINE_60                EXTI_IMR2_IM60          /*!< Extended line 60 */
+#define LL_EXTI_LINE_61                EXTI_IMR2_IM61          /*!< Extended line 61 */
+#define LL_EXTI_LINE_62                EXTI_IMR2_IM62          /*!< Extended line 62 */
+#define LL_EXTI_LINE_63                EXTI_IMR2_IM63          /*!< Extended line 63 */
+#define LL_EXTI_LINE_ALL_32_63         EXTI_IMR2_IM            /*!< All Extended line not reserved*/
+
+#define LL_EXTI_LINE_64                EXTI_IMR3_IM64          /*!< Extended line 64 */
+#define LL_EXTI_LINE_65                EXTI_IMR3_IM65          /*!< Extended line 65 */
+#define LL_EXTI_LINE_66                EXTI_IMR3_IM66          /*!< Extended line 66 */
+#define LL_EXTI_LINE_67                EXTI_IMR3_IM67          /*!< Extended line 67 */
+#define LL_EXTI_LINE_68                EXTI_IMR3_IM68          /*!< Extended line 68 */
+#define LL_EXTI_LINE_69                EXTI_IMR3_IM69          /*!< Extended line 69 */
+#define LL_EXTI_LINE_70                EXTI_IMR3_IM70          /*!< Extended line 70 */
+#define LL_EXTI_LINE_71                EXTI_IMR3_IM71          /*!< Extended line 71 */
+#define LL_EXTI_LINE_72                EXTI_IMR3_IM72          /*!< Extended line 72 */
+#define LL_EXTI_LINE_73                EXTI_IMR3_IM73          /*!< Extended line 73 */
+#define LL_EXTI_LINE_74                EXTI_IMR3_IM74          /*!< Extended line 74 */
+#if defined(ADC3)
+#define LL_EXTI_LINE_75                EXTI_IMR3_IM75          /*!< Extended line 75 */
+#endif /* ADC3 */
+#if defined(SAI4)
+#define LL_EXTI_LINE_76                EXTI_IMR3_IM76          /*!< Extended line 76 */
+#endif /* SAI4 */
+#if defined(DUAL_CORE)
+#define LL_EXTI_LINE_77                EXTI_IMR3_IM77          /*!< Extended line 77 */
+#define LL_EXTI_LINE_78                EXTI_IMR3_IM78          /*!< Extended line 78 */
+#define LL_EXTI_LINE_79                EXTI_IMR3_IM79          /*!< Extended line 79 */
+#define LL_EXTI_LINE_80                EXTI_IMR3_IM80          /*!< Extended line 80 */
+#define LL_EXTI_LINE_82                EXTI_IMR3_IM82          /*!< Extended line 82 */
+#define LL_EXTI_LINE_84                EXTI_IMR3_IM84          /*!< Extended line 84 */
+#endif /* DUAL_CORE */
+#define LL_EXTI_LINE_85                EXTI_IMR3_IM85          /*!< Extended line 85 */
+#if defined(ETH)
+#define LL_EXTI_LINE_86                EXTI_IMR3_IM86          /*!< Extended line 86 */
+#endif /* ETH */
+#define LL_EXTI_LINE_87                EXTI_IMR3_IM87          /*!< Extended line 87 */
+#if defined(DTS)
+#define LL_EXTI_LINE_88                EXTI_IMR3_IM88          /*!< Extended line 87 */
+#endif /* DTS */
+#define LL_EXTI_LINE_ALL_64_95         EXTI_IMR3_IM            /*!< All Extended line not reserved*/
+
+
+#define LL_EXTI_LINE_ALL               (0xFFFFFFFFU)  /*!< All Extended line */
+
+#if defined(USE_FULL_LL_DRIVER)
+#define LL_EXTI_LINE_NONE              (0x00000000U)  /*!< None Extended line */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/**
+  * @}
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/** @defgroup EXTI_LL_EC_MODE Mode
+  * @{
+  */
+#define LL_EXTI_MODE_IT               ((uint8_t)0x01U)      /*!< Cortex-M7 Interrupt Mode  */
+#define LL_EXTI_MODE_EVENT            ((uint8_t)0x02U)      /*!< Cortex-M7 Event Mode */
+#define LL_EXTI_MODE_IT_EVENT         ((uint8_t)0x03U)      /*!< Cortex-M7 Interrupt & Event Mode */
+
+#if defined(DUAL_CORE)
+#define LL_EXTI_MODE_C1_IT            LL_EXTI_MODE_IT       /*!< Cortex-M7 Interrupt Mode */
+#define LL_EXTI_MODE_C1_EVENT         LL_EXTI_MODE_EVENT    /*!< Cortex-M7 Event Mode */
+#define LL_EXTI_MODE_C1_IT_EVENT      LL_EXTI_MODE_IT_EVENT /*!< Cortex-M7 Interrupt & Event Mode */
+
+#define LL_EXTI_MODE_C2_IT            ((uint8_t)0x10U)      /*!< Cortex-M4 Interrupt Mode  */
+#define LL_EXTI_MODE_C2_EVENT         ((uint8_t)0x20U)      /*!< Cortex-M4 Event Mode  */
+#define LL_EXTI_MODE_C2_IT_EVENT      ((uint8_t)0x30U)      /*!< Cortex-M4 Interrupt & Event Mode */
+#endif /* DUAL_CORE */
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
+  * @{
+  */
+#define LL_EXTI_TRIGGER_NONE            ((uint8_t)0x00U) /*!< No Trigger Mode */
+#define LL_EXTI_TRIGGER_RISING          ((uint8_t)0x01U) /*!< Trigger Rising Mode */
+#define LL_EXTI_TRIGGER_FALLING         ((uint8_t)0x02U) /*!< Trigger Falling Mode */
+#define LL_EXTI_TRIGGER_RISING_FALLING  ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_D3_PEND_CLR D3 Pend Clear Source
+  * @{
+  */
+#define LL_EXTI_D3_PEND_CLR_DMACH6      ((uint8_t)0x00U) /*!< DMA ch6 event selected as D3 domain pendclear source */
+#define LL_EXTI_D3_PEND_CLR_DMACH7      ((uint8_t)0x01U) /*!< DMA ch7 event selected as D3 domain pendclear source */
+#if defined (LPTIM4)
+#define LL_EXTI_D3_PEND_CLR_LPTIM4      ((uint8_t)0x02U) /*!< LPTIM4 out selected as D3 domain pendclear source */
+#else
+#define LL_EXTI_D3_PEND_CLR_LPTIM2      ((uint8_t)0x02U) /*!< LPTIM2 out selected as D3 domain pendclear source */
+#endif /*LPTIM4*/
+#if defined (LPTIM5)
+#define LL_EXTI_D3_PEND_CLR_LPTIM5      ((uint8_t)0x03U) /*!< LPTIM5 out selected as D3 domain pendclear source */
+#else
+#define LL_EXTI_D3_PEND_CLR_LPTIM3      ((uint8_t)0x02U) /*!< LPTIM3 out selected as D3 domain pendclear source */
+#endif /*LPTIM5*/
+/**
+  * @}
+  */
+
+
+#endif /*USE_FULL_LL_DRIVER*/
+
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
+  * @{
+  */
+
+/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in EXTI register
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in EXTI register
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
+ * @{
+ */
+/** @defgroup EXTI_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable ExtiLine Interrupt request for Lines in range 0 to 31
+  * @rmtoll IMR1         IMx           LL_EXTI_EnableIT_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->IMR1, ExtiLine);
+}
+
+/**
+  * @brief  Enable ExtiLine Interrupt request for Lines in range 32 to 63
+  * @rmtoll IMR2         IMx           LL_EXTI_EnableIT_32_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44
+  *         @arg @ref LL_EXTI_LINE_46
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_59
+  *         @arg @ref LL_EXTI_LINE_60
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->IMR2, ExtiLine);
+}
+
+
+/**
+  * @brief  Enable ExtiLine Interrupt request for Lines in range 64 to 95
+  * @rmtoll IMR3         IMx           LL_EXTI_EnableIT_64_95
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_67
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_75
+  *         @arg @ref LL_EXTI_LINE_76
+  *         @arg @ref LL_EXTI_LINE_77
+  *         @arg @ref LL_EXTI_LINE_78
+  *         @arg @ref LL_EXTI_LINE_79
+  *         @arg @ref LL_EXTI_LINE_80
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  *         @arg @ref LL_EXTI_LINE_87
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableIT_64_95(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->IMR3, ExtiLine);
+}
+
+
+/**
+  * @brief  Disable ExtiLine Interrupt request for Lines in range 0 to 31
+  * @rmtoll IMR1         IMx           LL_EXTI_DisableIT_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->IMR1, ExtiLine);
+}
+
+
+/**
+  * @brief  Disable ExtiLine Interrupt request for Lines in range 32 to 63
+  * @rmtoll IMR2         IMx           LL_EXTI_DisableIT_32_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44
+  *         @arg @ref LL_EXTI_LINE_46
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_59
+  *         @arg @ref LL_EXTI_LINE_60
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->IMR2, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Interrupt request for Lines in range 64 to 95
+  * @rmtoll IMR3         IMx           LL_EXTI_DisableIT_64_95
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_67
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_75
+  *         @arg @ref LL_EXTI_LINE_76
+  *         @arg @ref LL_EXTI_LINE_77
+  *         @arg @ref LL_EXTI_LINE_78
+  *         @arg @ref LL_EXTI_LINE_79
+  *         @arg @ref LL_EXTI_LINE_80
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  *         @arg @ref LL_EXTI_LINE_87
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableIT_64_95(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->IMR3, ExtiLine);
+}
+
+
+/**
+  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
+  * @rmtoll IMR1         IMx           LL_EXTI_IsEnabledIT_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->IMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+
+/**
+  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63
+  * @rmtoll IMR2         IMx           LL_EXTI_IsEnabledIT_32_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44
+  *         @arg @ref LL_EXTI_LINE_46
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_59
+  *         @arg @ref LL_EXTI_LINE_60
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->IMR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+
+/**
+  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 64 to 95
+  * @rmtoll IMR3         IMx           LL_EXTI_IsEnabledIT_64_95
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_67
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_75
+  *         @arg @ref LL_EXTI_LINE_76
+  *         @arg @ref LL_EXTI_LINE_77
+  *         @arg @ref LL_EXTI_LINE_78
+  *         @arg @ref LL_EXTI_LINE_79
+  *         @arg @ref LL_EXTI_LINE_80
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  *         @arg @ref LL_EXTI_LINE_87
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_64_95(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->IMR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Enable ExtiLine Interrupt request for Lines in range 0 to 31 for cpu2
+  * @rmtoll C2IMR1         IMx           LL_C2_EXTI_EnableIT_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_EXTI_EnableIT_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->C2IMR1, ExtiLine);
+}
+
+
+/**
+  * @brief  Enable ExtiLine Interrupt request for Lines in range 32 to 63 for cpu2
+  * @rmtoll C2IMR2         IMx           LL_C2_EXTI_EnableIT_32_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44
+  *         @arg @ref LL_EXTI_LINE_46
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_59
+  *         @arg @ref LL_EXTI_LINE_60
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_EXTI_EnableIT_32_63(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->C2IMR2, ExtiLine);
+}
+
+
+/**
+  * @brief  Enable ExtiLine Interrupt request for Lines in range 64 to 95
+  * @rmtoll C2IMR3         IMx           LL_C2_EXTI_EnableIT_64_95
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_67
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_75
+  *         @arg @ref LL_EXTI_LINE_76
+  *         @arg @ref LL_EXTI_LINE_77
+  *         @arg @ref LL_EXTI_LINE_78
+  *         @arg @ref LL_EXTI_LINE_79
+  *         @arg @ref LL_EXTI_LINE_80
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  *         @arg @ref LL_EXTI_LINE_87
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_EXTI_EnableIT_64_95(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->C2IMR3, ExtiLine);
+}
+
+
+/**
+  * @brief  Disable ExtiLine Interrupt request for Lines in range 0 to 31 for cpu2
+  * @rmtoll C2IMR1         IMx           LL_C2_EXTI_DisableIT_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_EXTI_DisableIT_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->C2IMR1, ExtiLine);
+}
+
+
+
+/**
+  * @brief  Disable ExtiLine Interrupt request for Lines in range 32 to 63 for cpu2
+  * @rmtoll C2IMR2         IMx           LL_C2_EXTI_DisableIT_32_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44
+  *         @arg @ref LL_EXTI_LINE_46
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_59
+  *         @arg @ref LL_EXTI_LINE_60
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_EXTI_DisableIT_32_63(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->C2IMR2, ExtiLine);
+}
+
+
+/**
+  * @brief  Disable ExtiLine Interrupt request for Lines in range 64 to 95 for cpu2
+  * @rmtoll C2IMR3         IMx           LL_C2_EXTI_DisableIT_64_95
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_67
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_75
+  *         @arg @ref LL_EXTI_LINE_76
+  *         @arg @ref LL_EXTI_LINE_77
+  *         @arg @ref LL_EXTI_LINE_78
+  *         @arg @ref LL_EXTI_LINE_79
+  *         @arg @ref LL_EXTI_LINE_80
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  *         @arg @ref LL_EXTI_LINE_87
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_EXTI_DisableIT_64_95(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->C2IMR3, ExtiLine);
+}
+
+
+/**
+  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 for cpu2
+  * @rmtoll C2IMR1         IMx           LL_C2_EXTI_IsEnabledIT_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->C2IMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+
+/**
+  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63 for cpu2
+  * @rmtoll C2IMR2         IMx           LL_C2_EXTI_IsEnabledIT_32_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44
+  *         @arg @ref LL_EXTI_LINE_46
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_59
+  *         @arg @ref LL_EXTI_LINE_60
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->C2IMR2, ExtiLine) == (ExtiLine))? 1U : 0U);
+}
+
+
+/**
+  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 64 to 95
+  * @rmtoll C2IMR3         IMx           LL_C2_EXTI_IsEnabledIT_64_95
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_67
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_75
+  *         @arg @ref LL_EXTI_LINE_76
+  *         @arg @ref LL_EXTI_LINE_77
+  *         @arg @ref LL_EXTI_LINE_78
+  *         @arg @ref LL_EXTI_LINE_79
+  *         @arg @ref LL_EXTI_LINE_80
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  *         @arg @ref LL_EXTI_LINE_87
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_64_95(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->C2IMR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+#endif /* DUAL_CORE */
+
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Event_Management Event_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable ExtiLine Event request for Lines in range 0 to 31
+  * @rmtoll EMR1         EMx           LL_EXTI_EnableEvent_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->EMR1, ExtiLine);
+}
+
+/**
+  * @brief  Enable ExtiLine Event request for Lines in range 32 to 63
+  * @rmtoll EMR2         EMx           LL_EXTI_EnableEvent_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44
+  *         @arg @ref LL_EXTI_LINE_46
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_59
+  *         @arg @ref LL_EXTI_LINE_60
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->EMR2, ExtiLine);
+}
+
+/**
+  * @brief  Enable ExtiLine Event request for Lines in range 64 to 95
+  * @rmtoll EMR3         EMx           LL_EXTI_EnableEvent_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_67
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_75
+  *         @arg @ref LL_EXTI_LINE_76
+  *         @arg @ref LL_EXTI_LINE_77
+  *         @arg @ref LL_EXTI_LINE_78
+  *         @arg @ref LL_EXTI_LINE_79
+  *         @arg @ref LL_EXTI_LINE_80
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  *         @arg @ref LL_EXTI_LINE_87
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableEvent_64_95(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->EMR3, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Event request for Lines in range 0 to 31
+  * @rmtoll EMR1         EMx           LL_EXTI_DisableEvent_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->EMR1, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Event request for Lines in range 32 to 63
+  * @rmtoll EMR2         EMx           LL_EXTI_DisableEvent_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44
+  *         @arg @ref LL_EXTI_LINE_46
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_59
+  *         @arg @ref LL_EXTI_LINE_60
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->EMR2, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Event request for Lines in range 64 to 95
+  * @rmtoll EMR3         EMx           LL_EXTI_DisableEvent_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_67
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_75
+  *         @arg @ref LL_EXTI_LINE_76
+  *         @arg @ref LL_EXTI_LINE_77
+  *         @arg @ref LL_EXTI_LINE_78
+  *         @arg @ref LL_EXTI_LINE_79
+  *         @arg @ref LL_EXTI_LINE_80
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  *         @arg @ref LL_EXTI_LINE_87
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableEvent_64_95(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->EMR3, ExtiLine);
+}
+
+/**
+  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
+  * @rmtoll EMR1         EMx           LL_EXTI_IsEnabledEvent_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->EMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63
+  * @rmtoll EMR2         EMx           LL_EXTI_IsEnabledEvent_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44
+  *         @arg @ref LL_EXTI_LINE_46
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_59
+  *         @arg @ref LL_EXTI_LINE_60
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->EMR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 64 to 95
+  * @rmtoll EMR3         EMx           LL_EXTI_IsEnabledEvent_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_67
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_75
+  *         @arg @ref LL_EXTI_LINE_76
+  *         @arg @ref LL_EXTI_LINE_77
+  *         @arg @ref LL_EXTI_LINE_78
+  *         @arg @ref LL_EXTI_LINE_79
+  *         @arg @ref LL_EXTI_LINE_80
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  *         @arg @ref LL_EXTI_LINE_87
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_64_95(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->EMR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+#if defined(DUAL_CORE)
+
+/**
+  * @brief  Enable ExtiLine Event request for Lines in range 0 to 31 for cpu2
+  * @rmtoll C2EMR1         EMx           LL_C2_EXTI_EnableEvent_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->C2EMR1, ExtiLine);
+}
+
+
+/**
+  * @brief  Enable ExtiLine Event request for Lines in range 32 to 63 for cpu2
+  * @rmtoll C2EMR2         EMx           LL_C2_EXTI_EnableEvent_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44
+  *         @arg @ref LL_EXTI_LINE_46
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_59
+  *         @arg @ref LL_EXTI_LINE_60
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_EXTI_EnableEvent_32_63(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->C2EMR2, ExtiLine);
+}
+
+/**
+  * @brief  Enable ExtiLine Event request for Lines in range 64 to 95 for cpu2
+  * @rmtoll C2EMR3         EMx           LL_C2_EXTI_EnableEvent_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_67
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_75
+  *         @arg @ref LL_EXTI_LINE_76
+  *         @arg @ref LL_EXTI_LINE_77
+  *         @arg @ref LL_EXTI_LINE_78
+  *         @arg @ref LL_EXTI_LINE_79
+  *         @arg @ref LL_EXTI_LINE_80
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  *         @arg @ref LL_EXTI_LINE_87
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_EXTI_EnableEvent_64_95(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->C2EMR3, ExtiLine);
+}
+
+
+/**
+  * @brief  Disable ExtiLine Event request for Lines in range 0 to 31 for cpu2
+  * @rmtoll C2EMR1         EMx           LL_C2_EXTI_DisableEvent_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->C2EMR1, ExtiLine);
+}
+
+
+/**
+  * @brief  Disable ExtiLine Event request for Lines in range 32 to 63 for cpu2
+  * @rmtoll C2EMR2         EMx           LL_C2_EXTI_DisableEvent_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44
+  *         @arg @ref LL_EXTI_LINE_46
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_59
+  *         @arg @ref LL_EXTI_LINE_60
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_EXTI_DisableEvent_32_63(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->C2EMR2, ExtiLine);
+}
+
+
+/**
+  * @brief  Disable ExtiLine Event request for Lines in range 64 to 95 for cpu2
+  * @rmtoll C2EMR3         EMx           LL_C2_EXTI_DisableEvent_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_67
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_75
+  *         @arg @ref LL_EXTI_LINE_76
+  *         @arg @ref LL_EXTI_LINE_77
+  *         @arg @ref LL_EXTI_LINE_78
+  *         @arg @ref LL_EXTI_LINE_79
+  *         @arg @ref LL_EXTI_LINE_80
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  *         @arg @ref LL_EXTI_LINE_87
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_EXTI_DisableEvent_64_95(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->C2EMR3, ExtiLine);
+}
+
+
+/**
+  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 for cpu2
+  * @rmtoll C2EMR1         EMx           LL_C2_EXTI_IsEnabledEvent_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->C2EMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+
+/**
+  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63 for cpu2
+  * @rmtoll C2EMR2         EMx           LL_C2_EXTI_IsEnabledEvent_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44
+  *         @arg @ref LL_EXTI_LINE_46
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_59
+  *         @arg @ref LL_EXTI_LINE_60
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->C2EMR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+
+/**
+  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 64 to 95 for cpu2
+  * @rmtoll C2EMR3         EMx           LL_C2_EXTI_IsEnabledEvent_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_67
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_75
+  *         @arg @ref LL_EXTI_LINE_76
+  *         @arg @ref LL_EXTI_LINE_77
+  *         @arg @ref LL_EXTI_LINE_78
+  *         @arg @ref LL_EXTI_LINE_79
+  *         @arg @ref LL_EXTI_LINE_80
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  *         @arg @ref LL_EXTI_LINE_87
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledEvent_64_95(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->C2EMR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+
+#endif /* DUAL_CORE */
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a rising edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_RTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll RTSR1        RTx           LL_EXTI_EnableRisingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->RTSR1, ExtiLine);
+
+}
+
+/**
+  * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a rising edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_RTSR register, the
+  *       pending bit is not set.Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll RTSR2        RTx           LL_EXTI_EnableRisingTrig_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_51
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->RTSR2, ExtiLine);
+}
+
+/**
+  * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 64 to 95
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a rising edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_RTSR register, the
+  *       pending bit is not set.Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll RTSR3        RTx           LL_EXTI_EnableRisingTrig_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableRisingTrig_64_95(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->RTSR3, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a rising edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_RTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll RTSR1        RTx           LL_EXTI_DisableRisingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->RTSR1, ExtiLine);
+
+}
+
+/**
+  * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a rising edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_RTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll RTSR2        RTx           LL_EXTI_DisableRisingTrig_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_51
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->RTSR2, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 64 to 95
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a rising edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_RTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll RTSR3        RTx           LL_EXTI_DisableRisingTrig_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableRisingTrig_64_95(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->RTSR3, ExtiLine);
+}
+
+/**
+  * @brief  Check if rising edge trigger is enabled for Lines in range 0 to 31
+  * @rmtoll RTSR1        RTx           LL_EXTI_IsEnabledRisingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->RTSR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+
+/**
+  * @brief  Check if rising edge trigger is enabled for Lines in range 32 to 63
+  * @rmtoll RTSR2        RTx           LL_EXTI_IsEnabledRisingTrig_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_51
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->RTSR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Check if rising edge trigger is enabled for Lines in range 64 to 95
+  * @rmtoll RTSR3        RTx           LL_EXTI_IsEnabledRisingTrig_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_64_95(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->RTSR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a falling edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_FTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll FTSR1        FTx           LL_EXTI_EnableFallingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->FTSR1, ExtiLine);
+}
+
+/**
+  * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a Falling edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_FTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll FTSR2        FTx           LL_EXTI_EnableFallingTrig_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_51
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->FTSR2, ExtiLine);
+}
+
+/**
+  * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 64 to 95
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a Falling edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_FTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll FTSR3        FTx           LL_EXTI_EnableFallingTrig_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableFallingTrig_64_95(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->FTSR3, ExtiLine);
+}
+
+
+/**
+  * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a Falling edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_FTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for the same interrupt line.
+  *       In this case, both generate a trigger condition.
+  * @rmtoll FTSR1        FTx           LL_EXTI_DisableFallingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->FTSR1, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a Falling edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_FTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for the same interrupt line.
+  *       In this case, both generate a trigger condition.
+  * @rmtoll FTSR2        FTx           LL_EXTI_DisableFallingTrig_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_51
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->FTSR2, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 64 to 95
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a Falling edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_FTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for the same interrupt line.
+  *       In this case, both generate a trigger condition.
+  * @rmtoll FTSR3        FTx           LL_EXTI_DisableFallingTrig_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableFallingTrig_64_95(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->FTSR3, ExtiLine);
+}
+
+
+/**
+  * @brief  Check if falling edge trigger is enabled for Lines in range 0 to 31
+  * @rmtoll FTSR1        FTx           LL_EXTI_IsEnabledFallingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->FTSR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Check if falling edge trigger is enabled for Lines in range 32 to 63
+  * @rmtoll FTSR2        FTx           LL_EXTI_IsEnabledFallingTrig_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_51
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->FTSR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Check if falling edge trigger is enabled for Lines in range 64 to 95
+  * @rmtoll FTSR3        FTx           LL_EXTI_IsEnabledFallingTrig_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_64_95(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->FTSR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management
+  * @{
+  */
+
+/**
+  * @brief  Generate a software Interrupt Event for Lines in range 0 to 31
+  * @note If the interrupt is enabled on this line in the EXTI_C1IMR1, writing a 1 to
+  *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR1
+  *       resulting in an interrupt request generation.
+  *       This bit is cleared by clearing the corresponding bit in the EXTI_PR1
+  *       register (by writing a 1 into the bit)
+  * @rmtoll SWIER1       SWIx          LL_EXTI_GenerateSWI_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->SWIER1, ExtiLine);
+}
+
+/**
+  * @brief  Generate a software Interrupt Event for Lines in range 32 to 63
+  * @note If the interrupt is enabled on this line in the EXTI_IMR2, writing a 1 to
+  *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2
+  *       resulting in an interrupt request generation.
+  *       This bit is cleared by clearing the corresponding bit in the EXTI_PR2
+  *       register (by writing a 1 into the bit)
+  * @rmtoll SWIER2       SWIx          LL_EXTI_GenerateSWI_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_51
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->SWIER2, ExtiLine);
+}
+
+/**
+  * @brief  Generate a software Interrupt Event for Lines in range 64 to 95
+  * @note If the interrupt is enabled on this line in the EXTI_IMR2, writing a 1 to
+  *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2
+  *       resulting in an interrupt request generation.
+  *       This bit is cleared by clearing the corresponding bit in the EXTI_PR3
+  *       register (by writing a 1 into the bit)
+  * @rmtoll SWIER3       SWIx          LL_EXTI_GenerateSWI_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_GenerateSWI_64_95(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->SWIER3, ExtiLine);
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
+  * @{
+  */
+
+/**
+  * @brief  Check if the ExtLine Flag is set or not for Lines in range 0 to 31
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR1          PIFx           LL_EXTI_IsActiveFlag_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->PR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Check if the ExtLine Flag is set or not for  Lines in range 32 to 63
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR2          PIFx           LL_EXTI_IsActiveFlag_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->PR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Check if the ExtLine Flag is set or not for  Lines in range 64 to 95
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR3          PIFx           LL_EXTI_IsActiveFlag_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_64_95(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->PR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+
+/**
+  * @brief  Read ExtLine Combination Flag for Lines in range 0 to 31
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR1          PIFx           LL_EXTI_ReadFlag_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @retval @note This bit is set when the selected edge event arrives on the interrupt
+  */
+__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
+{
+  return (uint32_t)(READ_BIT(EXTI->PR1, ExtiLine));
+}
+
+
+/**
+  * @brief  Read ExtLine Combination Flag for  Lines in range 32 to 63
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR2          PIFx           LL_EXTI_ReadFlag_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_51
+  * @retval @note This bit is set when the selected edge event arrives on the interrupt
+  */
+__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_32_63(uint32_t ExtiLine)
+{
+  return (uint32_t)(READ_BIT(EXTI->PR2, ExtiLine));
+}
+
+
+/**
+  * @brief  Read ExtLine Combination Flag for  Lines in range 64 to 95
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR3          PIFx           LL_EXTI_ReadFlag_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  * @retval @note This bit is set when the selected edge event arrives on the interrupt
+  */
+__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_64_95(uint32_t ExtiLine)
+{
+  return (uint32_t)(READ_BIT(EXTI->PR3, ExtiLine));
+}
+
+/**
+  * @brief  Clear ExtLine Flags for Lines in range 0 to 31
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR1          PIFx           LL_EXTI_ClearFlag_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
+{
+  WRITE_REG(EXTI->PR1, ExtiLine);
+}
+
+/**
+  * @brief  Clear ExtLine Flags for Lines in range 32 to 63
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR2          PIFx           LL_EXTI_ClearFlag_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_51
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_ClearFlag_32_63(uint32_t ExtiLine)
+{
+  WRITE_REG(EXTI->PR2, ExtiLine);
+}
+
+/**
+  * @brief  Clear ExtLine Flags for Lines in range 64 to 95
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR3          PIFx           LL_EXTI_ClearFlag_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_ClearFlag_64_95(uint32_t ExtiLine)
+{
+  WRITE_REG(EXTI->PR3, ExtiLine);
+}
+
+#if defined(DUAL_CORE)
+
+/**
+  * @brief  Check if the ExtLine Flag is set or not for Lines in range 0 to 31 for cpu2
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll C2PR1          PIFx           LL_C2_EXTI_IsActiveFlag_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->C2PR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Check if the ExtLine Flag is set or not for  Lines in range 32 to 63 for cpu2
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll C2PR2          PIFx           LL_C2_EXTI_IsActiveFlag_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->C2PR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Check if the ExtLine Flag is set or not for  Lines in range 64 to 95 for cpu2
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll C2PR3          PIFx           LL_C2_EXTI_IsActiveFlag_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_EXTI_IsActiveFlag_64_95(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->C2PR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Read ExtLine Combination Flag for Lines in range 0 to 31 for cpu2
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll C2PR1          PIFx           LL_C2_EXTI_ReadFlag_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @retval @note This bit is set when the selected edge event arrives on the interrupt
+  */
+__STATIC_INLINE uint32_t LL_C2_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
+{
+  return (uint32_t)(READ_BIT(EXTI->C2PR1, ExtiLine));
+}
+
+/**
+  * @brief  Read ExtLine Combination Flag for  Lines in range 32 to 63 for cpu2
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll C2PR2          PIFx           LL_C2_EXTI_ReadFlag_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_51
+  * @retval @note This bit is set when the selected edge event arrives on the interrupt
+  */
+__STATIC_INLINE uint32_t LL_C2_EXTI_ReadFlag_32_63(uint32_t ExtiLine)
+{
+  return (uint32_t)(READ_BIT(EXTI->C2PR2, ExtiLine));
+}
+
+
+/**
+  * @brief  Read ExtLine Combination Flag for  Lines in range 64 to 95 for cpu2
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll C2PR3          PIFx           LL_C2_EXTI_ReadFlag_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  * @retval @note This bit is set when the selected edge event arrives on the interrupt
+  */
+__STATIC_INLINE uint32_t LL_C2_EXTI_ReadFlag_64_95(uint32_t ExtiLine)
+{
+  return (uint32_t)(READ_BIT(EXTI->C2PR3, ExtiLine));
+}
+/**
+  * @brief  Clear ExtLine Flags for Lines in range 0 to 31 for cpu2
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll C2PR1          PIFx           LL_C2_EXTI_ClearFlag_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
+{
+  WRITE_REG(EXTI->C2PR1, ExtiLine);
+}
+
+/**
+  * @brief  Clear ExtLine Flags for Lines in range 32 to 63 for cpu2
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll C2PR2          PIFx           LL_C2_EXTI_ClearFlag_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_51
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_EXTI_ClearFlag_32_63(uint32_t ExtiLine)
+{
+  WRITE_REG(EXTI->C2PR2, ExtiLine);
+}
+
+/**
+  * @brief  Clear ExtLine Flags for Lines in range 64 to 95 for cpu2
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll C2PR3          PIFx           LL_C2_EXTI_ClearFlag_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_EXTI_ClearFlag_64_95(uint32_t ExtiLine)
+{
+  WRITE_REG(EXTI->C2PR3, ExtiLine);
+}
+
+#endif /* DUAL_CORE */
+
+/**
+  * @brief  Enable ExtiLine D3 Pending Mask for Lines in range 0 to 31
+  * @rmtoll D3PMR1         MRx           LL_D3_EXTI_EnablePendMask_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_25
+  * @retval None
+  */
+__STATIC_INLINE void LL_D3_EXTI_EnablePendMask_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->D3PMR1, ExtiLine);
+}
+
+/**
+  * @brief  Enable ExtiLine D3 Pending Mask for Lines in range 32 to 63
+  * @rmtoll D3PMR2         MRx           LL_D3_EXTI_EnablePendMask_32_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  * @retval None
+  */
+__STATIC_INLINE void LL_D3_EXTI_EnablePendMask_32_63(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->D3PMR2, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine D3 Pending Mask for Lines in range 0 to 31
+  * @rmtoll D3PMR1         MRx           LL_D3_EXTI_DisablePendMask_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_25
+  * @retval None
+  */
+__STATIC_INLINE void LL_D3_EXTI_DisablePendMask_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->D3PMR1, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine D3 Pending Mask for Lines in range 32 to 63
+  * @rmtoll D3PMR2         MRx           LL_D3_EXTI_DisablePendMask_32_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  * @retval None
+  */
+__STATIC_INLINE void LL_D3_EXTI_DisablePendMask_32_63(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->D3PMR2, ExtiLine);
+}
+
+/**
+  * @brief  Indicate if ExtiLine D3 Pending Mask is enabled for Lines in range 0 to 31
+  * @rmtoll D3PMR1         MRx           LL_D3_EXTI_IsEnabledPendMask_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_25
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_D3_EXTI_IsEnabledPendMask_0_31(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->D3PMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Indicate if ExtiLine D3 Pending Mask is enabled for Lines in range 32 to 63
+  * @rmtoll D3PMR2         MRx           LL_D3_EXTI_IsEnabledPendMask_32_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_D3_EXTI_IsEnabledPendMask_32_63(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->D3PMR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 0 to 15
+  * @rmtoll D3PCR1L          PCSx           LL_D3_EXTI_SetPendClearSel_0_15
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  * @param  ClrSrc This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5
+  * @retval None
+  */
+__STATIC_INLINE void LL_D3_EXTI_SetPendClearSel_0_15(uint32_t ExtiLine, uint32_t ClrSrc)
+{
+  MODIFY_REG(EXTI->D3PCR1L, ((ExtiLine * ExtiLine) * 3UL), ((ExtiLine * ExtiLine) * ClrSrc));
+}
+
+/**
+  * @brief  Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 16 to 31
+  * @rmtoll D3PCR1H          PCSx           LL_D3_EXTI_SetPendClearSel_16_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_25
+  * @param  ClrSrc This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5
+  * @retval None
+  */
+__STATIC_INLINE void LL_D3_EXTI_SetPendClearSel_16_31(uint32_t ExtiLine, uint32_t ClrSrc)
+{
+  MODIFY_REG(EXTI->D3PCR1H, (((ExtiLine >> EXTI_IMR1_IM16_Pos) * (ExtiLine >> EXTI_IMR1_IM16_Pos)) * 3UL), (((ExtiLine >> EXTI_IMR1_IM16_Pos) * (ExtiLine >> EXTI_IMR1_IM16_Pos)) * ClrSrc));
+}
+
+
+/**
+  * @brief  Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 32 to 47
+  * @rmtoll D3PCR2L          PCSx           LL_D3_EXTI_SetPendClearSel_32_47
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_41
+  * @param  ClrSrc This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5
+  * @retval None
+  */
+__STATIC_INLINE void LL_D3_EXTI_SetPendClearSel_32_47(uint32_t ExtiLine, uint32_t ClrSrc)
+{
+  MODIFY_REG(EXTI->D3PCR2L, ((ExtiLine * ExtiLine) * 3UL), ((ExtiLine * ExtiLine) * ClrSrc));
+}
+
+/**
+  * @brief  Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 48 to 63
+  * @rmtoll D3PCR2H          PCSx           LL_D3_EXTI_SetPendClearSel_48_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  * @param  ClrSrc This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5
+  * @retval None
+  */
+__STATIC_INLINE void LL_D3_EXTI_SetPendClearSel_48_63(uint32_t ExtiLine, uint32_t ClrSrc)
+{
+  MODIFY_REG(EXTI->D3PCR2H, (((ExtiLine >> EXTI_IMR2_IM48_Pos) * (ExtiLine >> EXTI_IMR2_IM48_Pos)) * 3UL), (((ExtiLine >> EXTI_IMR2_IM48_Pos) * (ExtiLine >> EXTI_IMR2_IM48_Pos)) * ClrSrc));
+}
+
+/**
+  * @brief  Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 0 to 15
+  * @rmtoll D3PCR1L          PCSx           LL_D3_EXTI_GetPendClearSel_0_15
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5
+  */
+__STATIC_INLINE uint32_t LL_D3_EXTI_GetPendClearSel_0_15(uint32_t ExtiLine)
+{
+  return (uint32_t)(READ_BIT(EXTI->D3PCR1L, ((ExtiLine * ExtiLine) * 3UL)) / (ExtiLine * ExtiLine));
+}
+
+/**
+  * @brief  Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 16 to 31
+  * @rmtoll D3PCR1H          PCSx           LL_D3_EXTI_GetPendClearSel_16_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_25
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5
+  */
+__STATIC_INLINE uint32_t LL_D3_EXTI_GetPendClearSel_16_31(uint32_t ExtiLine)
+{
+  return (uint32_t)(READ_BIT(EXTI->D3PCR1H, (((ExtiLine >> EXTI_IMR1_IM16_Pos) * (ExtiLine >> EXTI_IMR1_IM16_Pos)) * 3UL)) / ((ExtiLine >> EXTI_IMR1_IM16_Pos) * (ExtiLine >> EXTI_IMR1_IM16_Pos)));
+}
+
+/**
+  * @brief  Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 32 to 47
+  * @rmtoll D3PCR2L          PCSx           LL_D3_EXTI_GetPendClearSel_32_47
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_41
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5
+  */
+__STATIC_INLINE uint32_t LL_D3_EXTI_GetPendClearSel_32_47(uint32_t ExtiLine)
+{
+  return (uint32_t)(READ_BIT(EXTI->D3PCR2L, ((ExtiLine * ExtiLine) * 3UL)) / (ExtiLine * ExtiLine));
+}
+
+/**
+  * @brief  Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 48 to 63
+  * @rmtoll D3PCR2H          PCSx           LL_D3_EXTI_GetPendClearSel_48_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5
+  */
+__STATIC_INLINE uint32_t LL_D3_EXTI_GetPendClearSel_48_63(uint32_t ExtiLine)
+{
+  return (uint32_t)(READ_BIT(EXTI->D3PCR2H, (((ExtiLine >> EXTI_IMR2_IM48_Pos) * (ExtiLine >> EXTI_IMR2_IM48_Pos)) * 3UL)) / ((ExtiLine >> EXTI_IMR2_IM48_Pos) * (ExtiLine >> EXTI_IMR2_IM48_Pos)));
+}
+
+
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
+  * @{,
+  */
+
+ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
+ErrorStatus LL_EXTI_DeInit(void);
+void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
+
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* EXTI */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32H7xx_LL_EXTI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_gpio.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_gpio.h
new file mode 100644
index 00000000..a375a124
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_gpio.h
@@ -0,0 +1,985 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_gpio.h
+  * @author  MCD Application Team
+  * @brief   Header file of GPIO LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_LL_GPIO_H
+#define STM32H7xx_LL_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK)
+
+/** @defgroup GPIO_LL GPIO
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
+  * @{
+  */
+
+/**
+  * @brief LL GPIO Init Structure definition
+  */
+typedef struct
+{
+  uint32_t Pin;          /*!< Specifies the GPIO pins to be configured.
+                              This parameter can be any value of @ref GPIO_LL_EC_PIN */
+
+  uint32_t Mode;         /*!< Specifies the operating mode for the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_MODE.
+
+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/
+
+  uint32_t Speed;        /*!< Specifies the speed for the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_SPEED.
+
+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/
+
+  uint32_t OutputType;   /*!< Specifies the operating output type for the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
+
+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/
+
+  uint32_t Pull;         /*!< Specifies the operating Pull-up/Pull down for the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_PULL.
+
+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/
+
+  uint32_t Alternate;    /*!< Specifies the Peripheral to be connected to the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_AF.
+
+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/
+} LL_GPIO_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
+  * @{
+  */
+
+/** @defgroup GPIO_LL_EC_PIN PIN
+  * @{
+  */
+#define LL_GPIO_PIN_0                      GPIO_BSRR_BS0 /*!< Select pin 0 */
+#define LL_GPIO_PIN_1                      GPIO_BSRR_BS1 /*!< Select pin 1 */
+#define LL_GPIO_PIN_2                      GPIO_BSRR_BS2 /*!< Select pin 2 */
+#define LL_GPIO_PIN_3                      GPIO_BSRR_BS3 /*!< Select pin 3 */
+#define LL_GPIO_PIN_4                      GPIO_BSRR_BS4 /*!< Select pin 4 */
+#define LL_GPIO_PIN_5                      GPIO_BSRR_BS5 /*!< Select pin 5 */
+#define LL_GPIO_PIN_6                      GPIO_BSRR_BS6 /*!< Select pin 6 */
+#define LL_GPIO_PIN_7                      GPIO_BSRR_BS7 /*!< Select pin 7 */
+#define LL_GPIO_PIN_8                      GPIO_BSRR_BS8 /*!< Select pin 8 */
+#define LL_GPIO_PIN_9                      GPIO_BSRR_BS9 /*!< Select pin 9 */
+#define LL_GPIO_PIN_10                     GPIO_BSRR_BS10 /*!< Select pin 10 */
+#define LL_GPIO_PIN_11                     GPIO_BSRR_BS11 /*!< Select pin 11 */
+#define LL_GPIO_PIN_12                     GPIO_BSRR_BS12 /*!< Select pin 12 */
+#define LL_GPIO_PIN_13                     GPIO_BSRR_BS13 /*!< Select pin 13 */
+#define LL_GPIO_PIN_14                     GPIO_BSRR_BS14 /*!< Select pin 14 */
+#define LL_GPIO_PIN_15                     GPIO_BSRR_BS15 /*!< Select pin 15 */
+#define LL_GPIO_PIN_ALL                    (GPIO_BSRR_BS0 | GPIO_BSRR_BS1  | GPIO_BSRR_BS2  | \
+                                           GPIO_BSRR_BS3  | GPIO_BSRR_BS4  | GPIO_BSRR_BS5  | \
+                                           GPIO_BSRR_BS6  | GPIO_BSRR_BS7  | GPIO_BSRR_BS8  | \
+                                           GPIO_BSRR_BS9  | GPIO_BSRR_BS10 | GPIO_BSRR_BS11 | \
+                                           GPIO_BSRR_BS12 | GPIO_BSRR_BS13 | GPIO_BSRR_BS14 | \
+                                           GPIO_BSRR_BS15) /*!< Select all pins */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EC_MODE Mode
+  * @{
+  */
+#define LL_GPIO_MODE_INPUT                 (0x00000000U) /*!< Select input mode */
+#define LL_GPIO_MODE_OUTPUT                GPIO_MODER_MODE0_0  /*!< Select output mode */
+#define LL_GPIO_MODE_ALTERNATE             GPIO_MODER_MODE0_1  /*!< Select alternate function mode */
+#define LL_GPIO_MODE_ANALOG                GPIO_MODER_MODE0    /*!< Select analog mode */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EC_OUTPUT Output Type
+  * @{
+  */
+#define LL_GPIO_OUTPUT_PUSHPULL            (0x00000000U) /*!< Select push-pull as output type */
+#define LL_GPIO_OUTPUT_OPENDRAIN           GPIO_OTYPER_OT0 /*!< Select open-drain as output type */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EC_SPEED Output Speed
+  * @{
+  */
+#define LL_GPIO_SPEED_FREQ_LOW             (0x00000000U) /*!< Select I/O low output speed    */
+#define LL_GPIO_SPEED_FREQ_MEDIUM          GPIO_OSPEEDR_OSPEED0_0 /*!< Select I/O medium output speed */
+#define LL_GPIO_SPEED_FREQ_HIGH            GPIO_OSPEEDR_OSPEED0_1 /*!< Select I/O fast output speed   */
+#define LL_GPIO_SPEED_FREQ_VERY_HIGH       GPIO_OSPEEDR_OSPEED0   /*!< Select I/O high output speed   */
+/**
+  * @}
+  */
+#define LL_GPIO_SPEED_LOW                  LL_GPIO_SPEED_FREQ_LOW
+#define LL_GPIO_SPEED_MEDIUM               LL_GPIO_SPEED_FREQ_MEDIUM
+#define LL_GPIO_SPEED_FAST                 LL_GPIO_SPEED_FREQ_HIGH
+#define LL_GPIO_SPEED_HIGH                 LL_GPIO_SPEED_FREQ_VERY_HIGH
+
+
+/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
+  * @{
+  */
+#define LL_GPIO_PULL_NO                    (0x00000000U) /*!< Select I/O no pull */
+#define LL_GPIO_PULL_UP                    GPIO_PUPDR_PUPD0_0 /*!< Select I/O pull up */
+#define LL_GPIO_PULL_DOWN                  GPIO_PUPDR_PUPD0_1 /*!< Select I/O pull down */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EC_AF Alternate Function
+  * @{
+  */
+#define LL_GPIO_AF_0                       (0x0000000U) /*!< Select alternate function 0 */
+#define LL_GPIO_AF_1                       (0x0000001U) /*!< Select alternate function 1 */
+#define LL_GPIO_AF_2                       (0x0000002U) /*!< Select alternate function 2 */
+#define LL_GPIO_AF_3                       (0x0000003U) /*!< Select alternate function 3 */
+#define LL_GPIO_AF_4                       (0x0000004U) /*!< Select alternate function 4 */
+#define LL_GPIO_AF_5                       (0x0000005U) /*!< Select alternate function 5 */
+#define LL_GPIO_AF_6                       (0x0000006U) /*!< Select alternate function 6 */
+#define LL_GPIO_AF_7                       (0x0000007U) /*!< Select alternate function 7 */
+#define LL_GPIO_AF_8                       (0x0000008U) /*!< Select alternate function 8 */
+#define LL_GPIO_AF_9                       (0x0000009U) /*!< Select alternate function 9 */
+#define LL_GPIO_AF_10                      (0x000000AU) /*!< Select alternate function 10 */
+#define LL_GPIO_AF_11                      (0x000000BU) /*!< Select alternate function 11 */
+#define LL_GPIO_AF_12                      (0x000000CU) /*!< Select alternate function 12 */
+#define LL_GPIO_AF_13                      (0x000000DU) /*!< Select alternate function 13 */
+#define LL_GPIO_AF_14                      (0x000000EU) /*!< Select alternate function 14 */
+#define LL_GPIO_AF_15                      (0x000000FU) /*!< Select alternate function 15 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
+  * @{
+  */
+
+/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in GPIO register
+  * @param  __INSTANCE__ GPIO Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in GPIO register
+  * @param  __INSTANCE__ GPIO Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
+  * @{
+  */
+
+/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
+  * @{
+  */
+
+/**
+  * @brief  Configure gpio mode for a dedicated pin on dedicated port.
+  * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll MODER        MODEy         LL_GPIO_SetPinMode
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_MODE_INPUT
+  *         @arg @ref LL_GPIO_MODE_OUTPUT
+  *         @arg @ref LL_GPIO_MODE_ALTERNATE
+  *         @arg @ref LL_GPIO_MODE_ANALOG
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
+{
+  MODIFY_REG(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0), ((Pin * Pin) * Mode));
+}
+
+/**
+  * @brief  Return gpio mode for a dedicated pin on dedicated port.
+  * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll MODER        MODEy         LL_GPIO_GetPinMode
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_MODE_INPUT
+  *         @arg @ref LL_GPIO_MODE_OUTPUT
+  *         @arg @ref LL_GPIO_MODE_ALTERNATE
+  *         @arg @ref LL_GPIO_MODE_ANALOG
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0)) / (Pin * Pin));
+}
+
+/**
+  * @brief  Configure gpio output type for several pins on dedicated port.
+  * @note   Output type as to be set when gpio pin is in output or
+  *         alternate modes. Possible type are Push-pull or Open-drain.
+  * @rmtoll OTYPER       OTy           LL_GPIO_SetPinOutputType
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @param  OutputType This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
+  *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
+{
+  MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
+}
+
+/**
+  * @brief  Return gpio output type for several pins on dedicated port.
+  * @note   Output type as to be set when gpio pin is in output or
+  *         alternate modes. Possible type are Push-pull or Open-drain.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll OTYPER       OTy           LL_GPIO_GetPinOutputType
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
+  *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) / Pin);
+}
+
+/**
+  * @brief  Configure gpio speed for a dedicated pin on dedicated port.
+  * @note   I/O speed can be Low, Medium, Fast or High speed.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @note   Refer to datasheet for frequency specifications and the power
+  *         supply and load conditions for each speed.
+  * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_SetPinSpeed
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @param  Speed This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
+  *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
+  *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
+  *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t  Speed)
+{
+  MODIFY_REG(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEED0), ((Pin * Pin) * Speed));
+}
+
+/**
+  * @brief  Return gpio speed for a dedicated pin on dedicated port.
+  * @note   I/O speed can be Low, Medium, Fast or High speed.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @note   Refer to datasheet for frequency specifications and the power
+  *         supply and load conditions for each speed.
+  * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_GetPinSpeed
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
+  *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
+  *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
+  *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEED0)) / (Pin * Pin));
+}
+
+/**
+  * @brief  Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll PUPDR        PUPDy         LL_GPIO_SetPinPull
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @param  Pull This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PULL_NO
+  *         @arg @ref LL_GPIO_PULL_UP
+  *         @arg @ref LL_GPIO_PULL_DOWN
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
+{
+  MODIFY_REG(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0), ((Pin * Pin) * Pull));
+}
+
+/**
+  * @brief  Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll PUPDR        PUPDy         LL_GPIO_GetPinPull
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_PULL_NO
+  *         @arg @ref LL_GPIO_PULL_UP
+  *         @arg @ref LL_GPIO_PULL_DOWN
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0)) / (Pin * Pin));
+}
+
+/**
+  * @brief  Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
+  * @note   Possible values are from AF0 to AF15 depending on target.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll AFRL         AFSELy        LL_GPIO_SetAFPin_0_7
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  * @param  Alternate This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_AF_0
+  *         @arg @ref LL_GPIO_AF_1
+  *         @arg @ref LL_GPIO_AF_2
+  *         @arg @ref LL_GPIO_AF_3
+  *         @arg @ref LL_GPIO_AF_4
+  *         @arg @ref LL_GPIO_AF_5
+  *         @arg @ref LL_GPIO_AF_6
+  *         @arg @ref LL_GPIO_AF_7
+  *         @arg @ref LL_GPIO_AF_8
+  *         @arg @ref LL_GPIO_AF_9
+  *         @arg @ref LL_GPIO_AF_10
+  *         @arg @ref LL_GPIO_AF_11
+  *         @arg @ref LL_GPIO_AF_12
+  *         @arg @ref LL_GPIO_AF_13
+  *         @arg @ref LL_GPIO_AF_14
+  *         @arg @ref LL_GPIO_AF_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
+{
+  MODIFY_REG(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0),
+             ((((Pin * Pin) * Pin) * Pin) * Alternate));
+}
+
+/**
+  * @brief  Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
+  * @rmtoll AFRL         AFSELy        LL_GPIO_GetAFPin_0_7
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_AF_0
+  *         @arg @ref LL_GPIO_AF_1
+  *         @arg @ref LL_GPIO_AF_2
+  *         @arg @ref LL_GPIO_AF_3
+  *         @arg @ref LL_GPIO_AF_4
+  *         @arg @ref LL_GPIO_AF_5
+  *         @arg @ref LL_GPIO_AF_6
+  *         @arg @ref LL_GPIO_AF_7
+  *         @arg @ref LL_GPIO_AF_8
+  *         @arg @ref LL_GPIO_AF_9
+  *         @arg @ref LL_GPIO_AF_10
+  *         @arg @ref LL_GPIO_AF_11
+  *         @arg @ref LL_GPIO_AF_12
+  *         @arg @ref LL_GPIO_AF_13
+  *         @arg @ref LL_GPIO_AF_14
+  *         @arg @ref LL_GPIO_AF_15
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->AFR[0],
+                             ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0)) / (((Pin * Pin) * Pin) * Pin));
+}
+
+/**
+  * @brief  Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
+  * @note   Possible values are from AF0 to AF15 depending on target.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll AFRH         AFSELy        LL_GPIO_SetAFPin_8_15
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @param  Alternate This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_AF_0
+  *         @arg @ref LL_GPIO_AF_1
+  *         @arg @ref LL_GPIO_AF_2
+  *         @arg @ref LL_GPIO_AF_3
+  *         @arg @ref LL_GPIO_AF_4
+  *         @arg @ref LL_GPIO_AF_5
+  *         @arg @ref LL_GPIO_AF_6
+  *         @arg @ref LL_GPIO_AF_7
+  *         @arg @ref LL_GPIO_AF_8
+  *         @arg @ref LL_GPIO_AF_9
+  *         @arg @ref LL_GPIO_AF_10
+  *         @arg @ref LL_GPIO_AF_11
+  *         @arg @ref LL_GPIO_AF_12
+  *         @arg @ref LL_GPIO_AF_13
+  *         @arg @ref LL_GPIO_AF_14
+  *         @arg @ref LL_GPIO_AF_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
+{
+  MODIFY_REG(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8),
+             (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * Alternate));
+}
+
+/**
+  * @brief  Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
+  * @note   Possible values are from AF0 to AF15 depending on target.
+  * @rmtoll AFRH         AFSELy        LL_GPIO_GetAFPin_8_15
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_AF_0
+  *         @arg @ref LL_GPIO_AF_1
+  *         @arg @ref LL_GPIO_AF_2
+  *         @arg @ref LL_GPIO_AF_3
+  *         @arg @ref LL_GPIO_AF_4
+  *         @arg @ref LL_GPIO_AF_5
+  *         @arg @ref LL_GPIO_AF_6
+  *         @arg @ref LL_GPIO_AF_7
+  *         @arg @ref LL_GPIO_AF_8
+  *         @arg @ref LL_GPIO_AF_9
+  *         @arg @ref LL_GPIO_AF_10
+  *         @arg @ref LL_GPIO_AF_11
+  *         @arg @ref LL_GPIO_AF_12
+  *         @arg @ref LL_GPIO_AF_13
+  *         @arg @ref LL_GPIO_AF_14
+  *         @arg @ref LL_GPIO_AF_15
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->AFR[1],
+                             (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8)) / ((((Pin >> 8U) *
+                                 (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)));
+}
+
+
+/**
+  * @brief  Lock configuration of several pins for a dedicated port.
+  * @note   When the lock sequence has been applied on a port bit, the
+  *         value of this port bit can no longer be modified until the
+  *         next reset.
+  * @note   Each lock bit freezes a specific configuration register
+  *         (control and alternate function registers).
+  * @rmtoll LCKR         LCKK          LL_GPIO_LockPin
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  __IO uint32_t temp;
+  WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
+  WRITE_REG(GPIOx->LCKR, PinMask);
+  WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
+  /* Read LCKK register. This read is mandatory to complete key lock sequence */
+  temp = READ_REG(GPIOx->LCKR);
+  (void) temp;
+}
+
+/**
+  * @brief  Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
+  * @rmtoll LCKR         LCKy          LL_GPIO_IsPinLocked
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Return 1 if one of the pin of a dedicated port is locked. else return 0.
+  * @rmtoll LCKR         LCKK          LL_GPIO_IsAnyPinLocked
+  * @param  GPIOx GPIO Port
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
+{
+  return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EF_Data_Access Data Access
+  * @{
+  */
+
+/**
+  * @brief  Return full input data register value for a dedicated port.
+  * @rmtoll IDR          IDy           LL_GPIO_ReadInputPort
+  * @param  GPIOx GPIO Port
+  * @retval Input data register value of port
+  */
+__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
+{
+  return (uint32_t)(READ_REG(GPIOx->IDR));
+}
+
+/**
+  * @brief  Return if input data level for several pins of dedicated port is high or low.
+  * @rmtoll IDR          IDy           LL_GPIO_IsInputPinSet
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Write output data register for the port.
+  * @rmtoll ODR          ODy           LL_GPIO_WriteOutputPort
+  * @param  GPIOx GPIO Port
+  * @param  PortValue Level value for each pin of the port
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
+{
+  WRITE_REG(GPIOx->ODR, PortValue);
+}
+
+/**
+  * @brief  Return full output data register value for a dedicated port.
+  * @rmtoll ODR          ODy           LL_GPIO_ReadOutputPort
+  * @param  GPIOx GPIO Port
+  * @retval Output data register value of port
+  */
+__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
+{
+  return (uint32_t)(READ_REG(GPIOx->ODR));
+}
+
+/**
+  * @brief  Return if input data level for several pins of dedicated port is high or low.
+  * @rmtoll ODR          ODy           LL_GPIO_IsOutputPinSet
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set several pins to high level on dedicated gpio port.
+  * @rmtoll BSRR         BSy           LL_GPIO_SetOutputPin
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  WRITE_REG(GPIOx->BSRR, PinMask);
+}
+
+/**
+  * @brief  Set several pins to low level on dedicated gpio port.
+  * @rmtoll BSRR         BRy           LL_GPIO_ResetOutputPin
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  WRITE_REG(GPIOx->BSRR, PinMask << 16U);
+}
+
+/**
+  * @brief  Toggle data value for several pin of dedicated port.
+  * @rmtoll ODR          ODy           LL_GPIO_TogglePin
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ PinMask);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
+ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
+void        LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /*defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) */
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_LL_GPIO_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_pwr.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_pwr.h
new file mode 100644
index 00000000..19169584
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_pwr.h
@@ -0,0 +1,2249 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_pwr.h
+  * @author  MCD Application Team
+  * @brief   Header file of PWR LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_LL_PWR_H
+#define STM32H7xx_LL_PWR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined (PWR)
+
+/** @defgroup PWR_LL PWR
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup PWR_LL_Private_Constants PWR Private Constants
+  * @{
+  */
+
+/** @defgroup PWR_LL_WAKEUP_PIN_OFFSET Wake-Up Pins register offsets Defines
+  * @brief    Flags defines which can be used with LL_PWR_WriteReg function
+  * @{
+  */
+/* Wake-Up Pins PWR register offsets */
+#define LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET    2UL
+#define LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK       0x1FU
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+/* Private macros ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
+  * @{
+  */
+
+/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_PWR_WriteReg function
+  * @{
+  */
+#define LL_PWR_FLAG_CPU_CSSF          PWR_CPUCR_CSSF      /*!< Clear flags for CPU  */
+#if defined (DUAL_CORE)
+#define LL_PWR_FLAG_CPU2_CSSF         PWR_CPU2CR_CSSF     /*!< Clear flags for CPU2 */
+#endif /* DUAL_CORE */
+#define LL_PWR_FLAG_WKUPCR_WKUPC6     PWR_WKUPCR_WKUPC6   /*!< Clear PC1 WKUP flag  */
+#define LL_PWR_FLAG_WKUPCR_WKUPC5     PWR_WKUPCR_WKUPC5   /*!< Clear PI11 WKUP flag */
+#define LL_PWR_FLAG_WKUPCR_WKUPC4     PWR_WKUPCR_WKUPC4   /*!< Clear PC13 WKUP flag */
+#define LL_PWR_FLAG_WKUPCR_WKUPC3     PWR_WKUPCR_WKUPC3   /*!< Clear PI8 WKUP flag  */
+#define LL_PWR_FLAG_WKUPCR_WKUPC2     PWR_WKUPCR_WKUPC2   /*!< Clear PA2 WKUP flag  */
+#define LL_PWR_FLAG_WKUPCR_WKUPC1     PWR_WKUPCR_WKUPC1   /*!< Clear PA0 WKUP flag  */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_PWR_ReadReg function
+  * @{
+  */
+#define LL_PWR_FLAG_AVDO              PWR_CSR1_AVDO       /*!< Analog voltage detector output on VDDA flag                          */
+#define LL_PWR_FLAG_PVDO              PWR_CSR1_PVDO       /*!< Programmable voltage detect output flag                              */
+#define LL_PWR_FLAG_ACTVOS            PWR_CSR1_ACTVOS     /*!< Current VOS applied for VCORE voltage scaling flag                   */
+#define LL_PWR_FLAG_ACTVOSRDY         PWR_CSR1_ACTVOSRDY  /*!< Ready bit for current actual used VOS for VCORE voltage scaling flag */
+#if defined (PWR_CSR1_MMCVDO)
+#define LL_PWR_FLAG_MMCVDO            PWR_CSR1_MMCVDO     /*!< Voltage detector output on VDDMMC flag                               */
+#endif /* PWR_CSR1_MMCVDO */
+
+#define LL_PWR_FLAG_TEMPH             PWR_CR2_TEMPH       /*!< Temperature high threshold flag */
+#define LL_PWR_FLAG_TEMPL             PWR_CR2_TEMPL       /*!< Temperature low threshold flag  */
+#define LL_PWR_FLAG_VBATH             PWR_CR2_VBATH       /*!< VBAT high threshold flag        */
+#define LL_PWR_FLAG_VBATL             PWR_CR2_VBATL       /*!< VBAT low threshold flag         */
+#define LL_PWR_FLAG_BRRDY             PWR_CR2_BRRDY       /*!< Backup Regulator ready flag     */
+
+#define LL_PWR_FLAG_USBRDY            PWR_CR3_USB33RDY    /*!< USB supply ready flag           */
+#define LL_PWR_FLAG_SMPSEXTRDY        PWR_CR3_SMPSEXTRDY  /*!< SMPS External supply ready flag */
+
+#if defined (PWR_CPUCR_SBF_D2)
+#define LL_PWR_FLAG_CPU_SBF_D2        PWR_CPUCR_SBF_D2    /*!< D2 domain DSTANDBY Flag  */
+#endif /* PWR_CPUCR_SBF_D2 */
+#if defined (PWR_CPUCR_SBF_D1)
+#define LL_PWR_FLAG_CPU_SBF_D1        PWR_CPUCR_SBF_D1    /*!< D1 domain DSTANDBY Flag  */
+#endif /* PWR_CPUCR_SBF_D1 */
+#define LL_PWR_FLAG_CPU_SBF           PWR_CPUCR_SBF       /*!< System STANDBY Flag      */
+#define LL_PWR_FLAG_CPU_STOPF         PWR_CPUCR_STOPF     /*!< STOP Flag                */
+#if defined (DUAL_CORE)
+#define LL_PWR_FLAG_CPU_HOLD2F        PWR_CPUCR_HOLD2F    /*!< CPU2 in hold wakeup flag */
+#endif /* DUAL_CORE */
+
+#if defined (DUAL_CORE)
+#define LL_PWR_FLAG_CPU2_SBF_D2       PWR_CPU2CR_SBF_D2   /*!< D2 domain DSTANDBY Flag  */
+#define LL_PWR_FLAG_CPU2_SBF_D1       PWR_CPU2CR_SBF_D1   /*!< D1 domain DSTANDBY Flag  */
+#define LL_PWR_FLAG_CPU2_SBF          PWR_CPU2CR_SBF      /*!< System STANDBY Flag      */
+#define LL_PWR_FLAG_CPU2_STOPF        PWR_CPU2CR_STOPF    /*!< STOP Flag                */
+#define LL_PWR_FLAG_CPU2_HOLD1F       PWR_CPU2CR_HOLD1F   /*!< CPU1 in hold wakeup flag */
+#endif /* DUAL_CORE */
+
+#if defined (PWR_CPUCR_PDDS_D2)
+#define LL_PWR_D3CR_VOSRDY            PWR_D3CR_VOSRDY     /*!< Voltage scaling ready flag */
+#else
+#define LL_PWR_SRDCR_VOSRDY           PWR_SRDCR_VOSRDY    /*!< Voltage scaling ready flag */
+#endif /* PWR_CPUCR_PDDS_D2 */
+
+#define LL_PWR_WKUPFR_WKUPF6          PWR_WKUPFR_WKUPF6   /*!< Wakeup flag on PC1  */
+#define LL_PWR_WKUPFR_WKUPF5          PWR_WKUPFR_WKUPF5   /*!< Wakeup flag on PI11 */
+#define LL_PWR_WKUPFR_WKUPF4          PWR_WKUPFR_WKUPF4   /*!< Wakeup flag on PC13 */
+#define LL_PWR_WKUPFR_WKUPF3          PWR_WKUPFR_WKUPF3   /*!< Wakeup flag on PI8  */
+#define LL_PWR_WKUPFR_WKUPF2          PWR_WKUPFR_WKUPF2   /*!< Wakeup flag on PA2  */
+#define LL_PWR_WKUPFR_WKUPF1          PWR_WKUPFR_WKUPF1   /*!< Wakeup flag on PA0  */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_MODE_PWR Power mode
+  * @{
+  */
+#if defined (PWR_CPUCR_PDDS_D2)
+#define LL_PWR_CPU_MODE_D1STOP        0x00000000U           /*!< Enter D1 domain to Stop mode when the CPU enters deepsleep       */
+#define LL_PWR_CPU_MODE_D1STANDBY     PWR_CPUCR_PDDS_D1     /*!< Enter D1 domain to Standby mode when the CPU enters deepsleep    */
+#else
+#define LL_PWR_CPU_MODE_CDSTOP        0x00000000U           /*!< Enter CD domain to Stop mode when the CPU enters deepsleep       */
+#define LL_PWR_CPU_MODE_CDSTOP2       PWR_CPUCR_RETDS_CD    /*!< Enter CD domain to Stop2 mode when the CPU enters deepsleep      */
+#endif /* PWR_CPUCR_PDDS_D2 */
+
+#if defined (PWR_CPUCR_PDDS_D2)
+#define LL_PWR_CPU_MODE_D2STOP        0x00000000U           /*!< Enter D2 domain to Stop mode when the CPU enters deepsleep       */
+#define LL_PWR_CPU_MODE_D2STANDBY     PWR_CPUCR_PDDS_D2     /*!< Enter D2 domain to Standby mode when the CPU enters deepsleep    */
+#endif /* PWR_CPUCR_PDDS_D2 */
+
+#if defined (PWR_CPUCR_PDDS_D2)
+#define LL_PWR_CPU_MODE_D3RUN         PWR_CPUCR_RUN_D3      /*!< Keep system D3 domain in Run mode when the CPU enter deepsleep   */
+#define LL_PWR_CPU_MODE_D3STOP        0x00000000U           /*!< Enter D3 domain to Stop mode when the CPU enters deepsleep       */
+#define LL_PWR_CPU_MODE_D3STANDBY     PWR_CPUCR_PDDS_D3     /*!< Enter D3 domain to Standby mode when the CPU enters deepsleep    */
+#else
+#define LL_PWR_CPU_MODE_SRDRUN        PWR_CPUCR_RUN_SRD     /*!< Keep system SRD domain in Run mode when the CPU enter deepsleep  */
+#define LL_PWR_CPU_MODE_SRDSTOP       0x00000000U           /*!< Enter SRD domain to Stop mode when the CPU enters deepsleep      */
+#define LL_PWR_CPU_MODE_SRDSTANDBY    PWR_CPUCR_PDDS_SRD    /*!< Enter SRD domain to Standby mode when the CPU enters deepsleep   */
+#endif /* PWR_CPUCR_PDDS_D2 */
+
+#if defined (DUAL_CORE)
+#define LL_PWR_CPU2_MODE_D1STOP       0x00000000U           /*!< Enter D1 domain to Stop mode when the CPU2 enters deepsleep      */
+#define LL_PWR_CPU2_MODE_D1STANDBY    PWR_CPU2CR_PDDS_D1    /*!< Enter D1 domain to Standby mode when the CPU2 enters deepsleep   */
+#define LL_PWR_CPU2_MODE_D2STOP       0x00000000U           /*!< Enter D2 domain to Stop mode when the CPU2 enters deepsleep      */
+#define LL_PWR_CPU2_MODE_D2STANDBY    PWR_CPU2CR_PDDS_D2    /*!< Enter D2 domain to Standby mode when the CPU2 enters deepsleep   */
+#define LL_PWR_CPU2_MODE_D3RUN        PWR_CPU2CR_RUN_D3     /*!< Keep system D3 domain in RUN mode when the CPU2 enter deepsleep  */
+#define LL_PWR_CPU2_MODE_D3STOP       0x00000000U           /*!< Enter D3 domain to Stop mode when the CPU2 enters deepsleep      */
+#define LL_PWR_CPU2_MODE_D3STANDBY    PWR_CPU2CR_PDDS_D3    /*!< Enter D3 domain to Standby mode when the CPU2 enter deepsleep    */
+#endif /* DUAL_CORE */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_REGU_VOLTAGE Run mode Regulator Voltage Scaling
+  * @{
+  */
+#if defined (PWR_CPUCR_PDDS_D2)
+#define LL_PWR_REGU_VOLTAGE_SCALE3      PWR_D3CR_VOS_0                    /*!< Select voltage scale 3 */
+#define LL_PWR_REGU_VOLTAGE_SCALE2      PWR_D3CR_VOS_1                    /*!< Select voltage scale 2 */
+#define LL_PWR_REGU_VOLTAGE_SCALE1      (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 1 */
+#define LL_PWR_REGU_VOLTAGE_SCALE0      (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 0 */
+#else
+#define LL_PWR_REGU_VOLTAGE_SCALE3      0x00000000U                       /*!< Select voltage scale 3 */
+#define LL_PWR_REGU_VOLTAGE_SCALE2      PWR_D3CR_VOS_0                    /*!< Select voltage scale 2 */
+#define LL_PWR_REGU_VOLTAGE_SCALE1      PWR_D3CR_VOS_1                    /*!< Select voltage scale 1 */
+#define LL_PWR_REGU_VOLTAGE_SCALE0      (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 0 */
+#endif /* PWR_CPUCR_PDDS_D2 */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_STOP_MODE_REGU_VOLTAGE Stop mode Regulator Voltage Scaling
+  * @{
+  */
+#define LL_PWR_REGU_VOLTAGE_SVOS_SCALE5   PWR_CR1_SVOS_0                    /*!< Select voltage scale 5 when system enters STOP mode */
+#define LL_PWR_REGU_VOLTAGE_SVOS_SCALE4   PWR_CR1_SVOS_1                    /*!< Select voltage scale 4 when system enters STOP mode */
+#define LL_PWR_REGU_VOLTAGE_SVOS_SCALE3   (PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1) /*!< Select voltage scale 3 when system enters STOP mode */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE  Regulator Mode In Deep Sleep Mode
+  * @{
+  */
+#define LL_PWR_REGU_DSMODE_MAIN           0x00000000U   /*!< Voltage Regulator in main mode during deepsleep mode      */
+#define LL_PWR_REGU_DSMODE_LOW_POWER      PWR_CR1_LPDS  /*!< Voltage Regulator in low-power mode during deepsleep mode */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_PVDLEVEL Power Digital Voltage Level Detector
+  * @{
+  */
+#define LL_PWR_PVDLEVEL_0   PWR_CR1_PLS_LEV0  /*!< Voltage threshold detected by PVD 1.95 V */
+#define LL_PWR_PVDLEVEL_1   PWR_CR1_PLS_LEV1  /*!< Voltage threshold detected by PVD 2.1 V  */
+#define LL_PWR_PVDLEVEL_2   PWR_CR1_PLS_LEV2  /*!< Voltage threshold detected by PVD 2.25 V */
+#define LL_PWR_PVDLEVEL_3   PWR_CR1_PLS_LEV3  /*!< Voltage threshold detected by PVD 2.4 V  */
+#define LL_PWR_PVDLEVEL_4   PWR_CR1_PLS_LEV4  /*!< Voltage threshold detected by PVD 2.55 V */
+#define LL_PWR_PVDLEVEL_5   PWR_CR1_PLS_LEV5  /*!< Voltage threshold detected by PVD 2.7 V  */
+#define LL_PWR_PVDLEVEL_6   PWR_CR1_PLS_LEV6  /*!< Voltage threshold detected by PVD 2.85 V */
+#define LL_PWR_PVDLEVEL_7   PWR_CR1_PLS_LEV7  /*!< External voltage level on PVD_IN pin, compared to internal VREFINT level. */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_AVDLEVEL Power Analog Voltage Level Detector
+  * @{
+  */
+#define LL_PWR_AVDLEVEL_0   PWR_CR1_ALS_LEV0  /*!< Analog Voltage threshold detected by AVD 1.7 V */
+#define LL_PWR_AVDLEVEL_1   PWR_CR1_ALS_LEV1  /*!< Analog Voltage threshold detected by AVD 2.1 V */
+#define LL_PWR_AVDLEVEL_2   PWR_CR1_ALS_LEV2  /*!< Analog Voltage threshold detected by AVD 2.5 V */
+#define LL_PWR_AVDLEVEL_3   PWR_CR1_ALS_LEV3  /*!< Analog Voltage threshold detected by AVD 2.8 V */
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR Battery Charge Resistor
+  * @{
+  */
+#define LL_PWR_BATT_CHARG_RESISTOR_5K     0x00000000U   /*!< Charge the Battery through a 5 kO resistor    */
+#define LL_PWR_BATT_CHARGRESISTOR_1_5K    PWR_CR3_VBRS  /*!< Charge the Battery through a 1.5 kO resistor  */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_WAKEUP_PIN  Wakeup Pins
+  * @{
+  */
+#define LL_PWR_WAKEUP_PIN1    PWR_WKUPEPR_WKUPEN1  /*!< Wake-Up pin 1 : PA0  */
+#define LL_PWR_WAKEUP_PIN2    PWR_WKUPEPR_WKUPEN2  /*!< Wake-Up pin 2 : PA2  */
+#define LL_PWR_WAKEUP_PIN3    PWR_WKUPEPR_WKUPEN3  /*!< Wake-Up pin 3 : PI8  */
+#define LL_PWR_WAKEUP_PIN4    PWR_WKUPEPR_WKUPEN4  /*!< Wake-Up pin 4 : PC13 */
+#define LL_PWR_WAKEUP_PIN5    PWR_WKUPEPR_WKUPEN5  /*!< Wake-Up pin 5 : PI11 */
+#define LL_PWR_WAKEUP_PIN6    PWR_WKUPEPR_WKUPEN6  /*!< Wake-Up pin 6 : PC1  */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_WAKEUP_PIN_PULL  Wakeup Pins pull configuration
+  * @{
+  */
+#define LL_PWR_WAKEUP_PIN_NOPULL      0x00000000UL   /*!< Configure Wake-Up pin in no pull   */
+#define LL_PWR_WAKEUP_PIN_PULLUP      0x00000001UL   /*!< Configure Wake-Up pin in pull Up   */
+#define LL_PWR_WAKEUP_PIN_PULLDOWN    0x00000002UL   /*!< Configure Wake-Up pin in pull Down */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_SUPPLY_PWR Power supply source configuration
+  * @{
+  */
+#define LL_PWR_LDO_SUPPLY                     PWR_CR3_LDOEN                                                               /*!< Core domains are suppplied from the LDO                                                                     */
+#if defined (SMPS)                                                                                                                                                                                                                       
+#define LL_PWR_DIRECT_SMPS_SUPPLY             PWR_CR3_SMPSEN                                                              /*!< Core domains are suppplied from the SMPS                                                                    */
+#define LL_PWR_SMPS_1V8_SUPPLIES_LDO          (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)                      /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains                                       */
+#define LL_PWR_SMPS_2V5_SUPPLIES_LDO          (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)                      /*!< The SMPS 2.5V output supplies the LDO which supplies the Core domains                                       */
+#define LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO  (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)  /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */
+#define LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO  (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)  /*!< The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */
+#define LL_PWR_SMPS_1V8_SUPPLIES_EXT          (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 1.8V output supplies an external source which supplies the Core domains                            */
+#define LL_PWR_SMPS_2V5_SUPPLIES_EXT          (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 2.5V output supplies an external source which supplies the Core domains                            */
+#endif /* SMPS */
+#define LL_PWR_EXTERNAL_SOURCE_SUPPLY         PWR_CR3_BYPASS                                                              /*!< The SMPS and the LDO are Bypassed. The Core domains are supplied from an external source                    */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
+  * @{
+  */
+
+/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in PWR register
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in PWR register
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
+  * @{
+  */
+
+/** @defgroup PWR_LL_EF_Configuration Configuration
+  * @{
+  */
+
+  /**
+  * @brief  Set the voltage Regulator mode during deep sleep mode
+  * @rmtoll CR1    LPDS         LL_PWR_SetRegulModeDS
+  * @param  RegulMode This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_REGU_DSMODE_MAIN
+  *         @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
+{
+  MODIFY_REG(PWR->CR1, PWR_CR1_LPDS, RegulMode);
+}
+
+/**
+  * @brief  Get the voltage Regulator mode during deep sleep mode
+  * @rmtoll CR1    LPDS         LL_PWR_GetRegulModeDS
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_REGU_DSMODE_MAIN
+  *         @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPDS));
+}
+
+/**
+  * @brief  Enable Power Voltage Detector
+  * @rmtoll CR1    PVDEN       LL_PWR_EnablePVD
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnablePVD(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_PVDEN);
+}
+
+/**
+  * @brief  Disable Power Voltage Detector
+  * @rmtoll CR1    PVDEN       LL_PWR_DisablePVD
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisablePVD(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_PVDEN);
+}
+
+/**
+  * @brief  Check if Power Voltage Detector is enabled
+  * @rmtoll CR1    PVDEN       LL_PWR_IsEnabledPVD
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
+{
+  return ((READ_BIT(PWR->CR1, PWR_CR1_PVDEN) == (PWR_CR1_PVDEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure the voltage threshold detected by the Power Voltage Detector
+  * @rmtoll CR1    PLS       LL_PWR_SetPVDLevel
+  * @param  PVDLevel This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_PVDLEVEL_0
+  *         @arg @ref LL_PWR_PVDLEVEL_1
+  *         @arg @ref LL_PWR_PVDLEVEL_2
+  *         @arg @ref LL_PWR_PVDLEVEL_3
+  *         @arg @ref LL_PWR_PVDLEVEL_4
+  *         @arg @ref LL_PWR_PVDLEVEL_5
+  *         @arg @ref LL_PWR_PVDLEVEL_6
+  *         @arg @ref LL_PWR_PVDLEVEL_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
+{
+  MODIFY_REG(PWR->CR1, PWR_CR1_PLS, PVDLevel);
+}
+
+/**
+  * @brief  Get the voltage threshold detection
+  * @rmtoll CR1    PLS       LL_PWR_GetPVDLevel
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_PVDLEVEL_0
+  *         @arg @ref LL_PWR_PVDLEVEL_1
+  *         @arg @ref LL_PWR_PVDLEVEL_2
+  *         @arg @ref LL_PWR_PVDLEVEL_3
+  *         @arg @ref LL_PWR_PVDLEVEL_4
+  *         @arg @ref LL_PWR_PVDLEVEL_5
+  *         @arg @ref LL_PWR_PVDLEVEL_6
+  *         @arg @ref LL_PWR_PVDLEVEL_7
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_PLS));
+}
+
+/**
+  * @brief  Enable access to the backup domain
+  * @rmtoll CR1    DBP       LL_PWR_EnableBkUpAccess
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_DBP);
+}
+
+/**
+  * @brief  Disable access to the backup domain
+  * @rmtoll CR1    DBP       LL_PWR_DisableBkUpAccess
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
+}
+
+/**
+  * @brief  Check if the backup domain is enabled
+  * @rmtoll CR1    DBP       LL_PWR_IsEnabledBkUpAccess
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
+{
+  return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the Flash Power Down in Stop Mode
+  * @rmtoll CR1    FLPS       LL_PWR_EnableFlashPowerDown
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_FLPS);
+}
+
+/**
+  * @brief  Disable the Flash Power Down in Stop Mode
+  * @rmtoll CR1    FLPS       LL_PWR_DisableFlashPowerDown
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_FLPS);
+}
+
+/**
+  * @brief  Check if the Flash Power Down in Stop Mode is enabled
+  * @rmtoll CR1    FLPS       LL_PWR_IsEnabledFlashPowerDown
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void)
+{
+  return ((READ_BIT(PWR->CR1, PWR_CR1_FLPS) == (PWR_CR1_FLPS)) ? 1UL : 0UL);
+}
+
+#if defined (PWR_CR1_BOOSTE)
+/**
+  * @brief  Enable the Analog Voltage Booster (VDDA)
+  * @rmtoll CR1    BOOSTE     LL_PWR_EnableAnalogBooster
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableAnalogBooster(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_BOOSTE);
+}
+
+/**
+  * @brief  Disable the Analog Voltage Booster (VDDA)
+  * @rmtoll CR1    BOOSTE     LL_PWR_DisableAnalogBooster
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableAnalogBooster(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_BOOSTE);
+}
+
+/**
+  * @brief  Check if the Analog Voltage Booster (VDDA) is enabled
+  * @rmtoll CR1    BOOSTE     LL_PWR_IsEnabledAnalogBooster
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledAnalogBooster(void)
+{
+  return ((READ_BIT(PWR->CR1, PWR_CR1_BOOSTE) == (PWR_CR1_BOOSTE)) ? 1UL : 0UL);
+}
+#endif /* PWR_CR1_BOOSTE */
+
+#if defined (PWR_CR1_AVD_READY)
+/**
+  * @brief  Enable the Analog Voltage Ready to isolate the BOOST IP untill VDDA will be ready
+  * @rmtoll CR1    AVD_READY  LL_PWR_EnableAnalogVoltageReady
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableAnalogVoltageReady(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_AVD_READY);
+}
+
+/**
+  * @brief  Disable the Analog Voltage Ready (VDDA)
+  * @rmtoll CR1    AVD_READY  LL_PWR_DisableAnalogVoltageReady
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableAnalogVoltageReady(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_AVD_READY);
+}
+
+/**
+  * @brief  Check if the Analog Voltage Booster (VDDA) is enabled
+  * @rmtoll CR1    AVD_READY  LL_PWR_IsEnabledAnalogVoltageReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledAnalogVoltageReady(void)
+{
+  return ((READ_BIT(PWR->CR1, PWR_CR1_AVD_READY) == (PWR_CR1_AVD_READY)) ? 1UL : 0UL);
+}
+#endif /* PWR_CR1_AVD_READY */
+
+/**
+  * @brief  Set the internal Regulator output voltage in STOP mode
+  * @rmtoll CR1    SVOS       LL_PWR_SetStopModeRegulVoltageScaling
+  * @param  VoltageScaling This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE3
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE4
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE5
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetStopModeRegulVoltageScaling(uint32_t VoltageScaling)
+{
+  MODIFY_REG(PWR->CR1, PWR_CR1_SVOS, VoltageScaling);
+}
+
+/**
+  * @brief  Get the internal Regulator output voltage in STOP mode
+  * @rmtoll CR1    SVOS       LL_PWR_GetStopModeRegulVoltageScaling
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE3
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE4
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE5
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetStopModeRegulVoltageScaling(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_SVOS));
+}
+
+/**
+  * @brief  Enable Analog Power Voltage Detector
+  * @rmtoll CR1    AVDEN       LL_PWR_EnableAVD
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableAVD(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_AVDEN);
+}
+
+/**
+  * @brief  Disable Analog Power Voltage Detector
+  * @rmtoll CR1    AVDEN       LL_PWR_DisableAVD
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableAVD(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_AVDEN);
+}
+
+/**
+  * @brief  Check if Analog Power Voltage Detector is enabled
+  * @rmtoll CR1    AVDEN       LL_PWR_IsEnabledAVD
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledAVD(void)
+{
+  return ((READ_BIT(PWR->CR1, PWR_CR1_AVDEN) == (PWR_CR1_AVDEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure the voltage threshold to be detected by the Analog Power Voltage Detector
+  * @rmtoll CR1    ALS       LL_PWR_SetAVDLevel
+  * @param  AVDLevel This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_AVDLEVEL_0
+  *         @arg @ref LL_PWR_AVDLEVEL_1
+  *         @arg @ref LL_PWR_AVDLEVEL_2
+  *         @arg @ref LL_PWR_AVDLEVEL_3
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetAVDLevel(uint32_t AVDLevel)
+{
+  MODIFY_REG(PWR->CR1, PWR_CR1_ALS, AVDLevel);
+}
+
+/**
+  * @brief  Get the Analog Voltage threshold to be detected by the Analog Power Voltage Detector
+  * @rmtoll CR1    ALS       LL_PWR_GetAVDLevel
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_AVDLEVEL_0
+  *         @arg @ref LL_PWR_AVDLEVEL_1
+  *         @arg @ref LL_PWR_AVDLEVEL_2
+  *         @arg @ref LL_PWR_AVDLEVEL_3
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetAVDLevel(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_ALS));
+}
+
+#if defined (PWR_CR1_AXIRAM1SO)
+/**
+  * @brief  Enable the AXI RAM1 shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    AXIRAM1SO     LL_PWR_EnableAXIRAM1ShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableAXIRAM1ShutOff(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO);
+}
+
+/**
+  * @brief  Disable the AXI RAM1 shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    AXIRAM1SO     LL_PWR_DisableAXIRAM1ShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableAXIRAM1ShutOff(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO);
+}
+
+/**
+  * @brief  Check if the AXI RAM1 shut-off in DStop/DStop2 mode is enabled
+  * @rmtoll CR1    AXIRAM1SO     LL_PWR_IsEnabledAXIRAM1ShutOff
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM1ShutOff(void)
+{
+  return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO) == (PWR_CR1_AXIRAM1SO)) ? 1UL : 0UL);
+}
+#endif /* PWR_CR1_AXIRAM1SO */
+
+#if defined (PWR_CR1_AXIRAM2SO)
+/**
+  * @brief  Enable the AXI RAM2 shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    AXIRAM2SO     LL_PWR_EnableAXIRAM2ShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableAXIRAM2ShutOff(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO);
+}
+
+/**
+  * @brief  Disable the AXI RAM2 shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    AXIRAM2SO     LL_PWR_DisableAXIRAM2ShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableAXIRAM2ShutOff(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO);
+}
+
+/**
+  * @brief  Check if the AXI RAM2 shut-off in DStop/DStop2 mode is enabled
+  * @rmtoll CR1    AXIRAM2SO     LL_PWR_IsEnabledAXIRAM2ShutOff
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM2ShutOff(void)
+{
+  return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO) == (PWR_CR1_AXIRAM2SO)) ? 1UL : 0UL);
+}
+#endif /* PWR_CR1_AXIRAM2SO */
+
+#if defined (PWR_CR1_AXIRAM3SO)
+/**
+  * @brief  Enable the AXI RAM3 shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    AXIRAM3SO     LL_PWR_EnableAXIRAM3ShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableAXIRAM3ShutOff(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO);
+}
+
+/**
+  * @brief  Disable the AXI RAM3 shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    AXIRAM3SO     LL_PWR_DisableAXIRAM3ShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableAXIRAM3ShutOff(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO);
+}
+
+/**
+  * @brief  Check if the AXI RAM3 shut-off in DStop/DStop2 mode is enabled
+  * @rmtoll CR1    AXIRAM3SO     LL_PWR_IsEnabledAXIRAM3ShutOff
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM3ShutOff(void)
+{
+  return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO) == (PWR_CR1_AXIRAM3SO)) ? 1UL : 0UL);
+}
+#endif /* PWR_CR1_AXIRAM3SO */
+
+#if defined (PWR_CR1_AHBRAM1SO)
+/**
+  * @brief  Enable the AHB RAM1 shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    AHBRAM1SO     LL_PWR_EnableAHBRAM1ShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableAHBRAM1ShutOff(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO);
+}
+
+/**
+  * @brief  Disable the AHB RAM1 shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    AHBRAM1SO     LL_PWR_DisableAHBRAM1ShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableAHBRAM1ShutOff(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO);
+}
+
+/**
+  * @brief  Check if the AHB RAM1 shut-off in DStop/DStop2 mode is enabled
+  * @rmtoll CR1    AHBRAM1SO     LL_PWR_IsEnabledAHBRAM1ShutOff
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM1ShutOff(void)
+{
+  return ((READ_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO) == (PWR_CR1_AHBRAM1SO)) ? 1UL : 0UL);
+}
+#endif /* PWR_CR1_AHBRAM1SO */
+
+#if defined (PWR_CR1_AHBRAM2SO)
+/**
+  * @brief  Enable the AHB RAM2 shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    AHBRAM2SO     LL_PWR_EnableAHBRAM2ShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableAHBRAM2ShutOff(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO);
+}
+
+/**
+  * @brief  Disable the AHB RAM2 shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    AHBRAM2SO     LL_PWR_DisableAHBRAM2ShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableAHBRAM2ShutOff(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO);
+}
+
+/**
+  * @brief  Check if the AHB RAM2 shut-off in DStop/DStop2 mode is enabled
+  * @rmtoll CR1    AHBRAM2SO     LL_PWR_IsEnabledAHBRAM2ShutOff
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM2ShutOff(void)
+{
+  return ((READ_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO) == (PWR_CR1_AHBRAM2SO)) ? 1UL : 0UL);
+}
+#endif /* PWR_CR1_AHBRAM2SO */
+
+#if defined (PWR_CR1_ITCMSO)
+/**
+  * @brief  Enable the ITCM shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    ITCMSO     LL_PWR_EnableITCMSOShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableITCMSOShutOff(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_ITCMSO);
+}
+
+/**
+  * @brief  Disable the ITCM shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    ITCMSO     LL_PWR_DisableITCMSOShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableITCMSOShutOff(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_ITCMSO);
+}
+
+/**
+  * @brief  Check if the ITCM shut-off in DStop/DStop2 mode is enabled
+  * @rmtoll CR1    ITCMSO     LL_PWR_IsEnabledITCMShutOff
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledITCMShutOff(void)
+{
+  return ((READ_BIT(PWR->CR1, PWR_CR1_ITCMSO) == (PWR_CR1_ITCMSO)) ? 1UL : 0UL);
+}
+#endif /* PWR_CR1_ITCMSO */
+
+#if defined (PWR_CR1_HSITFSO)
+/**
+  * @brief  Enable the USB and FDCAN shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    HSITFSO     LL_PWR_EnableHSITFShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableHSITFShutOff(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_HSITFSO);
+}
+
+/**
+  * @brief  Disable the USB and FDCAN shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    HSITFSO     LL_PWR_DisableHSITFShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableHSITFShutOff(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_HSITFSO);
+}
+
+/**
+  * @brief  Check if the USB and FDCAN shut-off in DStop/DStop2 mode is enabled
+  * @rmtoll CR1    HSITFSO     LL_PWR_IsEnabledHSITFShutOff
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledHSITFShutOff(void)
+{
+  return ((READ_BIT(PWR->CR1, PWR_CR1_HSITFSO) == (PWR_CR1_HSITFSO)) ? 1UL : 0UL);
+}
+#endif /* PWR_CR1_HSITFSO */
+
+#if defined (PWR_CR1_SRDRAMSO)
+/**
+  * @brief  Enable the SRD AHB RAM shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    SRDRAMSO     LL_PWR_EnableSRDRAMShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableSRDRAMShutOff(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_SRDRAMSO);
+}
+
+/**
+  * @brief  Disable the SRD AHB RAM shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    SRDRAMSO     LL_PWR_DisableSRDRAMShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableSRDRAMShutOff(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_SRDRAMSO);
+}
+
+/**
+  * @brief  Check if the SRD AHB RAM shut-off in DStop/DStop2 mode is enabled
+  * @rmtoll CR1    SRDRAMSO     LL_PWR_IsEnabledSRDRAMShutOff
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledSRDRAMShutOff(void)
+{
+  return ((READ_BIT(PWR->CR1, PWR_CR1_SRDRAMSO) == (PWR_CR1_SRDRAMSO)) ? 1UL : 0UL);
+}
+#endif /* PWR_CR1_SRDRAMSO */
+
+/**
+  * @brief  Enable Backup Regulator
+  * @rmtoll CR2    BREN       LL_PWR_EnableBkUpRegulator
+  * @note When set, the Backup Regulator (used to maintain backup SRAM content in Standby and
+  *       VBAT modes) is enabled. If BRE is reset, the backup Regulator is switched off. The backup
+  *       SRAM can still be used but its content will be lost in the Standby and VBAT modes. Once set,
+  *       the application must wait that the Backup Regulator Ready flag (BRR) is set to indicate that
+  *       the data written into the RAM will be maintained in the Standby and VBAT modes.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void)
+{
+  SET_BIT(PWR->CR2, PWR_CR2_BREN);
+}
+
+/**
+  * @brief  Disable Backup Regulator
+  * @rmtoll CR2    BREN       LL_PWR_DisableBkUpRegulator
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void)
+{
+  CLEAR_BIT(PWR->CR2, PWR_CR2_BREN);
+}
+
+/**
+  * @brief  Check if the backup Regulator is enabled
+  * @rmtoll CR2    BREN      LL_PWR_IsEnabledBkUpRegulator
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void)
+{
+  return ((READ_BIT(PWR->CR2, PWR_CR2_BREN) == (PWR_CR2_BREN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable VBAT and Temperature monitoring
+  * @rmtoll CR2    MONEN       LL_PWR_EnableMonitoring
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableMonitoring(void)
+{
+  SET_BIT(PWR->CR2, PWR_CR2_MONEN);
+}
+
+/**
+  * @brief  Disable VBAT and Temperature monitoring
+  * @rmtoll CR2    MONEN       LL_PWR_DisableMonitoring
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableMonitoring(void)
+{
+  CLEAR_BIT(PWR->CR2, PWR_CR2_MONEN);
+}
+
+/**
+  * @brief  Check if the VBAT and Temperature monitoring is enabled
+  * @rmtoll CR2    MONEN      LL_PWR_IsEnabledMonitoring
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledMonitoring(void)
+{
+  return ((READ_BIT(PWR->CR2, PWR_CR2_MONEN) == (PWR_CR2_MONEN)) ? 1UL : 0UL);
+}
+
+#if defined (SMPS)
+/**
+  * @brief  Configure the PWR supply
+  * @rmtoll CR3          BYPASS          LL_PWR_ConfigSupply
+  * @rmtoll CR3          LDOEN           LL_PWR_ConfigSupply
+  * @rmtoll CR3          SMPSEN          LL_PWR_ConfigSupply
+  * @rmtoll CR3          SMPSEXTHP       LL_PWR_ConfigSupply
+  * @rmtoll CR3          SMPSLEVEL       LL_PWR_ConfigSupply
+  * @param  SupplySource This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_LDO_SUPPLY
+  *         @arg @ref LL_PWR_DIRECT_SMPS_SUPPLY
+  *         @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_LDO
+  *         @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_LDO
+  *         @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO
+  *         @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO
+  *         @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT
+  *         @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT
+  *         @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ConfigSupply(uint32_t SupplySource)
+{
+  /* Set the power supply configuration */
+  MODIFY_REG(PWR->CR3, (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS), SupplySource);
+}
+#else
+/**
+  * @brief  Configure the PWR supply
+  * @rmtoll CR3          BYPASS          LL_PWR_ConfigSupply
+  * @rmtoll CR3          LDOEN           LL_PWR_ConfigSupply
+  * @rmtoll CR3          SCUEN           LL_PWR_ConfigSupply
+  * @param  SupplySource This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_LDO_SUPPLY
+  *         @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ConfigSupply(uint32_t SupplySource)
+{
+  /* Set the power supply configuration */
+  MODIFY_REG(PWR->CR3, (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS), SupplySource);
+}
+#endif /* defined (SMPS) */
+
+#if defined (SMPS)
+/**
+  * @brief  Get the PWR supply
+  * @rmtoll CR3          BYPASS          LL_PWR_GetSupply
+  * @rmtoll CR3          LDOEN           LL_PWR_GetSupply
+  * @rmtoll CR3          SMPSEN          LL_PWR_GetSupply
+  * @rmtoll CR3          SMPSEXTHP       LL_PWR_GetSupply
+  * @rmtoll CR3          SMPSLEVEL       LL_PWR_GetSupply
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_LDO_SUPPLY
+  *         @arg @ref LL_PWR_DIRECT_SMPS_SUPPLY
+  *         @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_LDO
+  *         @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_LDO
+  *         @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO
+  *         @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO
+  *         @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT
+  *         @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT
+  *         @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetSupply(void)
+{
+  /* Get the power supply configuration */
+  return(uint32_t)(READ_BIT(PWR->CR3, (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)));
+}
+#else
+/**
+  * @brief  Get the PWR supply
+  * @rmtoll CR3          BYPASS          LL_PWR_GetSupply
+  * @rmtoll CR3          LDOEN           LL_PWR_GetSupply
+  * @rmtoll CR3          SCUEN           LL_PWR_GetSupply
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_LDO_SUPPLY
+  *         @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetSupply(void)
+{
+  /* Get the power supply configuration */
+  return(uint32_t)(READ_BIT(PWR->CR3, (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)));
+}
+#endif /* defined (SMPS) */
+
+/**
+  * @brief  Enable battery charging
+  * @rmtoll CR3          VBE           LL_PWR_EnableBatteryCharging
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableBatteryCharging(void)
+{
+  SET_BIT(PWR->CR3, PWR_CR3_VBE);
+}
+
+/**
+  * @brief  Disable battery charging
+  * @rmtoll CR3          VBE           LL_PWR_DisableBatteryCharging
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableBatteryCharging(void)
+{
+  CLEAR_BIT(PWR->CR3, PWR_CR3_VBE);
+}
+
+/**
+  * @brief  Check if battery charging is enabled
+  * @rmtoll CR3          VBE           LL_PWR_IsEnabledBatteryCharging
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)
+{
+  return ((READ_BIT(PWR->CR3, PWR_CR3_VBE) == (PWR_CR3_VBE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the Battery charge resistor impedance
+  * @rmtoll CR3          VBRS          LL_PWR_SetBattChargResistor
+  * @param  Resistor This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
+  *         @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor)
+{
+  MODIFY_REG(PWR->CR3, PWR_CR3_VBRS, Resistor);
+}
+
+/**
+  * @brief  Get the Battery charge resistor impedance
+  * @rmtoll CR3          VBRS          LL_PWR_GetBattChargResistor
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
+  *         @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CR3, PWR_CR3_VBRS));
+}
+
+/**
+  * @brief  Enable the USB regulator
+  * @rmtoll CR3          USBREGEN           LL_PWR_EnableUSBReg
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableUSBReg(void)
+{
+  SET_BIT(PWR->CR3, PWR_CR3_USBREGEN);
+}
+
+/**
+  * @brief  Disable the USB regulator
+  * @rmtoll CR3          USBREGEN           LL_PWR_DisableUSBReg
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableUSBReg(void)
+{
+  CLEAR_BIT(PWR->CR3, PWR_CR3_USBREGEN);
+}
+
+/**
+  * @brief  Check if the USB regulator is enabled
+  * @rmtoll CR3          USBREGEN           LL_PWR_IsEnabledUSBReg
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBReg(void)
+{
+  return ((READ_BIT(PWR->CR3, PWR_CR3_USBREGEN) == (PWR_CR3_USBREGEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the USB voltage detector
+  * @rmtoll CR3          USB33DEN           LL_PWR_EnableUSBVoltageDetector
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableUSBVoltageDetector(void)
+{
+  SET_BIT(PWR->CR3, PWR_CR3_USB33DEN);
+}
+
+/**
+  * @brief  Disable the USB voltage detector
+  * @rmtoll CR3          USB33DEN           LL_PWR_DisableUSBVoltageDetector
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableUSBVoltageDetector(void)
+{
+  CLEAR_BIT(PWR->CR3, PWR_CR3_USB33DEN);
+}
+
+/**
+  * @brief  Check if the USB voltage detector is enabled
+  * @rmtoll CR3          USB33DEN           LL_PWR_IsEnabledUSBVoltageDetector
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBVoltageDetector(void)
+{
+  return ((READ_BIT(PWR->CR3, PWR_CR3_USB33DEN) == (PWR_CR3_USB33DEN)) ? 1UL : 0UL);
+}
+
+#if defined (PWR_CPUCR_PDDS_D2)
+/**
+  * @brief  Set the D1 domain Power Down mode when the CPU enters deepsleep
+  * @rmtoll CPUCR     PDDS_D1       LL_PWR_CPU_SetD1PowerMode
+  * @param  PDMode This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_CPU_MODE_D1STOP
+  *         @arg @ref LL_PWR_CPU_MODE_D1STANDBY
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_CPU_SetD1PowerMode(uint32_t PDMode)
+{
+  MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D1, PDMode);
+}
+#else
+/**
+  * @brief  Set the CPU domain Power Down mode when the CPU enters deepsleep
+  * @rmtoll CPUCR     RETDS_CD       LL_PWR_CPU_SetCDPowerMode
+  * @param  PDMode This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_CPU_MODE_CDSTOP
+  *         @arg @ref LL_PWR_CPU_MODE_CDSTOP2
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_CPU_SetCDPowerMode(uint32_t PDMode)
+{
+  MODIFY_REG(PWR->CPUCR, PWR_CPUCR_RETDS_CD, PDMode);
+}
+#endif /* PWR_CPUCR_PDDS_D2 */
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Set the D1 domain Power Down mode when the CPU2 enters deepsleep
+  * @rmtoll CPU2CR     PDDS_D1       LL_PWR_CPU2_SetD1PowerMode
+  * @param  PDMode This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_CPU2_MODE_D1STOP
+  *         @arg @ref LL_PWR_CPU2_MODE_D1STANDBY
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_CPU2_SetD1PowerMode(uint32_t PDMode)
+{
+  MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D1, PDMode);
+}
+#endif /* DUAL_CORE */
+
+#if defined (PWR_CPUCR_PDDS_D2)
+/**
+  * @brief  Get the D1 Domain Power Down mode when the CPU enters deepsleep
+  * @rmtoll CPUCR     PDDS_D1       LL_PWR_CPU_GetD1PowerMode
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_CPU_MODE_D1STOP
+  *         @arg @ref LL_PWR_CPU_MODE_D1STANDBY
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU_GetD1PowerMode(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1));
+}
+#else
+/**
+  * @brief  Get the CD Domain Power Down mode when the CPU enters deepsleep
+  * @rmtoll CPUCR     RETDS_CD       LL_PWR_CPU_GetCDPowerMode
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_CPU_MODE_CDSTOP
+  *         @arg @ref LL_PWR_CPU_MODE_CDSTOP2
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU_GetCDPowerMode(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_RETDS_CD));
+}
+#endif /* PWR_CPUCR_PDDS_D2 */
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Get the D1 Domain Power Down mode when the CPU2 enters deepsleep
+  * @rmtoll CPU2CR     PDDS_D1       LL_PWR_CPU2_GetD1PowerMode
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_CPU2_MODE_D1STOP
+  *         @arg @ref LL_PWR_CPU2_MODE_D1STANDBY
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU2_GetD1PowerMode(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D1));
+}
+#endif /* DUAL_CORE */
+
+#if defined (PWR_CPUCR_PDDS_D2)
+/**
+  * @brief  Set the D2 domain Power Down mode when the CPU enters deepsleep
+  * @rmtoll CPUCR     PDDS_D2       LL_PWR_CPU_SetD2PowerMode
+  * @param  PDMode This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_CPU_MODE_D2STOP
+  *         @arg @ref LL_PWR_CPU_MODE_D2STANDBY
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_CPU_SetD2PowerMode(uint32_t PDMode)
+{
+  MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D2, PDMode);
+}
+#endif /* PWR_CPUCR_PDDS_D2 */
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Set the D2 domain Power Down mode when the CPU2 enters deepsleep
+  * @rmtoll CPU2CR     PDDS_D2       LL_PWR_CPU2_SetD2PowerMode
+  * @param  PDMode This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_CPU2_MODE_D2STOP
+  *         @arg @ref LL_PWR_CPU2_MODE_D2STANDBY
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_CPU2_SetD2PowerMode(uint32_t PDMode)
+{
+  MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D2, PDMode);
+}
+#endif /* DUAL_CORE */
+
+#if defined (PWR_CPUCR_PDDS_D2)
+/**
+  * @brief  Get the D2 Domain Power Down mode when the CPU enters deepsleep
+  * @rmtoll CPUCR     PDDS_D2       LL_PWR_CPU_GetD2PowerMode
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_CPU_MODE_D2STOP
+  *         @arg @ref LL_PWR_CPU_MODE_D2STANDBY
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU_GetD2PowerMode(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D2));
+}
+#endif /* PWR_CPUCR_PDDS_D2 */
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Get the D2 Domain Power Down mode when the CPU2 enters deepsleep
+  * @rmtoll CPU2CR     PDDS_D2       LL_PWR_CPU2_GetD2PowerMode
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_CPU2_MODE_D2STOP
+  *         @arg @ref LL_PWR_CPU2_MODE_D2STANDBY
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU2_GetD2PowerMode(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D2));
+}
+#endif /* DUAL_CORE */
+
+#if defined (PWR_CPUCR_PDDS_D2)
+/**
+  * @brief  Set the D3 domain Power Down mode when the CPU enters deepsleep
+  * @rmtoll CPUCR     PDDS_D3       LL_PWR_CPU_SetD3PowerMode
+  * @param  PDMode This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_CPU_MODE_D3STOP
+  *         @arg @ref LL_PWR_CPU_MODE_D3STANDBY
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_CPU_SetD3PowerMode(uint32_t PDMode)
+{
+  MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D3 , PDMode);
+}
+#else
+/**
+  * @brief  Set the SRD domain Power Down mode when the CPU enters deepsleep
+  * @rmtoll CPUCR     PDDS_SRD       LL_PWR_CPU_SetSRDPowerMode
+  * @param  PDMode This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_CPU_MODE_SRDSTOP
+  *         @arg @ref LL_PWR_CPU_MODE_SRDSTANDBY
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_CPU_SetSRDPowerMode(uint32_t PDMode)
+{
+  MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_SRD , PDMode);
+}
+#endif /* PWR_CPUCR_PDDS_D2 */
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Set the D3 domain Power Down mode when the CPU2 enters deepsleep
+  * @rmtoll CPU2CR     PDDS_D3       LL_PWR_CPU2_SetD3PowerMode
+  * @param  PDMode This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_CPU2_MODE_D3STOP
+  *         @arg @ref LL_PWR_CPU2_MODE_D3STANDBY
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_CPU2_SetD3PowerMode(uint32_t PDMode)
+{
+  MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D3, PDMode);
+}
+#endif /* DUAL_CORE */
+
+#if defined (PWR_CPUCR_PDDS_D3)
+/**
+  * @brief  Get the D3 Domain Power Down mode when the CPU enters deepsleep
+  * @rmtoll CPUCR     PDDS_D3       LL_PWR_CPU_GetD3PowerMode
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_CPU_MODE_D3STOP
+  *         @arg @ref LL_PWR_CPU_MODE_D3STANDBY
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU_GetD3PowerMode(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D3));
+}
+#else
+/**
+  * @brief  Get the SRD Domain Power Down mode when the CPU enters deepsleep
+  * @rmtoll CPUCR     PDDS_SRD       LL_PWR_CPU_GetSRDPowerMode
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_CPU_MODE_SRDSTOP
+  *         @arg @ref LL_PWR_CPU_MODE_SRDSTANDBY
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU_GetSRDPowerMode(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_SRD));
+}
+#endif /* PWR_CPUCR_PDDS_D3 */
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Get the D3 Domain Power Down mode when the CPU2 enters deepsleep
+  * @rmtoll CPU2CR     PDDS_D3       LL_PWR_CPU2_GetD3PowerMode
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_CPU2_MODE_D3STOP
+  *         @arg @ref LL_PWR_CPU2_MODE_D3STANDBY
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU2_GetD3PowerMode(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D3));
+}
+#endif /* DUAL_CORE */
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Hold the CPU1 and allocated peripherals when exiting from STOP mode
+  * @rmtoll CPU2CR     HOLD1       LL_PWR_HoldCPU1
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_HoldCPU1(void)
+{
+  SET_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1);
+}
+
+/**
+  * @brief  Release the CPU1 and allocated peripherals
+  * @rmtoll CPU2CR     HOLD1       LL_PWR_ReleaseCPU1
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ReleaseCPU1(void)
+{
+  CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1);
+}
+
+/**
+  * @brief  Ckeck if the CPU1 and allocated peripherals are held
+  * @rmtoll CPU2CR     HOLD1       LL_PWR_IsCPU1Held
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsCPU1Held(void)
+{
+  return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1) == (PWR_CPU2CR_HOLD1))  ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Hold the CPU2 and allocated peripherals when exiting from STOP mode
+  * @rmtoll CPUCR     HOLD2       LL_PWR_HoldCPU2
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_HoldCPU2(void)
+{
+  SET_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2);
+}
+
+/**
+  * @brief  Release the CPU2 and allocated peripherals
+  * @rmtoll CPUCR     HOLD2       LL_PWR_ReleaseCPU2
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ReleaseCPU2(void)
+{
+  CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2);
+}
+
+/**
+  * @brief  Ckeck if the CPU2 and allocated peripherals are held
+  * @rmtoll CPUCR     HOLD2       LL_PWR_IsCPU2Held
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsCPU2Held(void)
+{
+  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2) == (PWR_CPUCR_HOLD2)) ? 1UL : 0UL);
+}
+#endif /* DUAL_CORE */
+
+#if defined (PWR_CPUCR_PDDS_D2)
+/**
+  * @brief  D3 domain remains in Run mode regardless of CPU subsystem modes
+  * @rmtoll CPUCR     RUN_D3       LL_PWR_CPU_EnableD3RunInLowPowerMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_CPU_EnableD3RunInLowPowerMode(void)
+{
+  SET_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3);
+}
+#else
+/**
+  * @brief  SRD domain remains in Run mode regardless of CPU subsystem modes
+  * @rmtoll CPUCR     RUN_SRD      LL_PWR_CPU_EnableSRDRunInLowPowerMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_CPU_EnableSRDRunInLowPowerMode(void)
+{
+  SET_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD);
+}
+#endif /* PWR_CPUCR_PDDS_D2 */
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  D3 domain remains in Run mode regardless of CPU2 subsystem modes
+  * @rmtoll CPU2CR     RUN_D3       LL_PWR_CPU2_EnableD3RunInLowPowerMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_CPU2_EnableD3RunInLowPowerMode(void)
+{
+  SET_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3);
+}
+#endif /* DUAL_CORE */
+
+#if defined (PWR_CPUCR_PDDS_D2)
+/**
+  * @brief  D3 domain follows CPU subsystem modes
+  * @rmtoll CPUCR     RUN_D3       LL_PWR_CPU_DisableD3RunInLowPowerMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_CPU_DisableD3RunInLowPowerMode(void)
+{
+  CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3);
+}
+#else
+/**
+  * @brief  SRD domain follows CPU subsystem modes
+  * @rmtoll CPUCR     RUN_SRD      LL_PWR_CPU_DisableSRDRunInLowPowerMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_CPU_DisableSRDRunInLowPowerMode(void)
+{
+  CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD);
+}
+#endif /* PWR_CPUCR_PDDS_D2 */
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  D3 domain follows CPU2 subsystem modes
+  * @rmtoll CPU2CR     RUN_D3       LL_PWR_CPU2_DisableD3RunInLowPowerMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_CPU2_DisableD3RunInLowPowerMode(void)
+{
+  CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3);
+}
+#endif /* DUAL_CORE */
+
+#if defined (PWR_CPUCR_PDDS_D2)
+/**
+  * @brief  Check if D3 is kept in Run mode when CPU enters low power mode
+  * @rmtoll CPUCR     RUN_D3    LL_PWR_CPU_IsEnabledD3RunInLowPowerMode
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU_IsEnabledD3RunInLowPowerMode(void)
+{
+  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3) == (PWR_CPUCR_RUN_D3)) ? 1UL : 0UL);
+}
+#else
+/**
+  * @brief  Check if SRD is kept in Run mode when CPU enters low power mode
+  * @rmtoll CPUCR     RUN_SRD    LL_PWR_CPU_IsEnabledSRDRunInLowPowerMode
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU_IsEnabledSRDRunInLowPowerMode(void)
+{
+  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD) == (PWR_CPUCR_RUN_SRD)) ? 1UL : 0UL);
+}
+#endif /* PWR_CPUCR_PDDS_D2 */
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Check if D3 is kept in Run mode when CPU2 enters low power mode
+  * @rmtoll CPU2CR     RUN_D3    LL_PWR_CPU2_IsEnabledD3RunInLowPowerMode
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU2_IsEnabledD3RunInLowPowerMode(void)
+{
+  return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3) == (PWR_CPU2CR_RUN_D3)) ? 1UL : 0UL);
+}
+#endif /* DUAL_CORE */
+
+/**
+  * @brief  Set the main internal Regulator output voltage
+  * @rmtoll D3CR    VOS       LL_PWR_SetRegulVoltageScaling
+  * @param  VoltageScaling This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
+  * @note   For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines, VOS0 
+  *         is applied when PWR_D3CR_VOS[1:0] = 0b11 and  SYSCFG_PWRCR_ODEN = 0b1.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
+{
+#if defined (PWR_CPUCR_PDDS_D2)
+  MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, VoltageScaling);
+#else
+  MODIFY_REG(PWR->SRDCR, PWR_SRDCR_VOS, VoltageScaling);
+#endif /* PWR_CPUCR_PDDS_D2 */
+}
+
+/**
+  * @brief  Get the main internal Regulator output voltage
+  * @rmtoll D3CR    VOS       LL_PWR_GetRegulVoltageScaling
+  * @note   For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines, checking 
+  *         VOS0 need the check of PWR_D3CR_VOS[1:0] field and SYSCFG_PWRCR_ODEN bit.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
+{
+#if defined (PWR_CPUCR_PDDS_D2)
+  return (uint32_t)(READ_BIT(PWR->D3CR, PWR_D3CR_VOS));
+#else
+  return (uint32_t)(READ_BIT(PWR->SRDCR, PWR_SRDCR_VOS));
+#endif /* PWR_CPUCR_PDDS_D2 */
+}
+
+/**
+  * @brief  Enable the WakeUp PINx functionality
+  * @rmtoll WKUPEPR   WKUPEN1       LL_PWR_EnableWakeUpPin\n
+  *         WKUPEPR   WKUPEN2       LL_PWR_EnableWakeUpPin\n
+  *         WKUPEPR   WKUPEN3       LL_PWR_EnableWakeUpPin\n
+  *         WKUPEPR   WKUPEN4       LL_PWR_EnableWakeUpPin\n
+  *         WKUPEPR   WKUPEN5       LL_PWR_EnableWakeUpPin\n
+  *         WKUPEPR   WKUPEN6       LL_PWR_EnableWakeUpPin
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  *         @arg @ref LL_PWR_WAKEUP_PIN6
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
+{
+  SET_BIT(PWR->WKUPEPR, WakeUpPin);
+}
+
+/**
+  * @brief  Disable the WakeUp PINx functionality
+  * @rmtoll WKUPEPR   WKUPEN1       LL_PWR_DisableWakeUpPin\n
+  *         WKUPEPR   WKUPEN2       LL_PWR_DisableWakeUpPin\n
+  *         WKUPEPR   WKUPEN3       LL_PWR_DisableWakeUpPin\n
+  *         WKUPEPR   WKUPEN4       LL_PWR_DisableWakeUpPin\n
+  *         WKUPEPR   WKUPEN5       LL_PWR_DisableWakeUpPin\n
+  *         WKUPEPR   WKUPEN6       LL_PWR_DisableWakeUpPin
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  *         @arg @ref LL_PWR_WAKEUP_PIN6
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
+{
+  CLEAR_BIT(PWR->WKUPEPR, WakeUpPin);
+}
+
+/**
+  * @brief  Check if the WakeUp PINx functionality is enabled
+  * @rmtoll WKUPEPR   WKUPEN1       LL_PWR_IsEnabledWakeUpPin\n
+  *         WKUPEPR   WKUPEN2       LL_PWR_IsEnabledWakeUpPin\n
+  *         WKUPEPR   WKUPEN3       LL_PWR_IsEnabledWakeUpPin\n
+  *         WKUPEPR   WKUPEN4       LL_PWR_IsEnabledWakeUpPin\n
+  *         WKUPEPR   WKUPEN5       LL_PWR_IsEnabledWakeUpPin\n
+  *         WKUPEPR   WKUPEN6       LL_PWR_IsEnabledWakeUpPin
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  *         @arg @ref LL_PWR_WAKEUP_PIN6
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
+{
+  return ((READ_BIT(PWR->WKUPEPR, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the Wake-Up pin polarity low for the event detection
+  * @rmtoll WKUPEPR   WKUPP1       LL_PWR_SetWakeUpPinPolarityLow\n
+  *         WKUPEPR   WKUPP2       LL_PWR_SetWakeUpPinPolarityLow\n
+  *         WKUPEPR   WKUPP3       LL_PWR_SetWakeUpPinPolarityLow\n
+  *         WKUPEPR   WKUPP4       LL_PWR_SetWakeUpPinPolarityLow\n
+  *         WKUPEPR   WKUPP5       LL_PWR_SetWakeUpPinPolarityLow\n
+  *         WKUPEPR   WKUPP6       LL_PWR_SetWakeUpPinPolarityLow
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  *         @arg @ref LL_PWR_WAKEUP_PIN6
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
+{
+  SET_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos));
+}
+
+/**
+  * @brief  Set the Wake-Up pin polarity high for the event detection
+  * @rmtoll WKUPEPR   WKUPP1       LL_PWR_SetWakeUpPinPolarityHigh\n
+  *         WKUPEPR   WKUPP2       LL_PWR_SetWakeUpPinPolarityHigh\n
+  *         WKUPEPR   WKUPP3       LL_PWR_SetWakeUpPinPolarityHigh\n
+  *         WKUPEPR   WKUPP4       LL_PWR_SetWakeUpPinPolarityHigh\n
+  *         WKUPEPR   WKUPP5       LL_PWR_SetWakeUpPinPolarityHigh\n
+  *         WKUPEPR   WKUPP6       LL_PWR_SetWakeUpPinPolarityHigh
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  *         @arg @ref LL_PWR_WAKEUP_PIN6
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
+{
+  CLEAR_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos));
+}
+
+/**
+  * @brief  Get the Wake-Up pin polarity for the event detection
+  * @rmtoll WKUPEPR   WKUPP1       LL_PWR_IsWakeUpPinPolarityLow\n
+  *         WKUPEPR   WKUPP2       LL_PWR_IsWakeUpPinPolarityLow\n
+  *         WKUPEPR   WKUPP3       LL_PWR_IsWakeUpPinPolarityLow\n
+  *         WKUPEPR   WKUPP4       LL_PWR_IsWakeUpPinPolarityLow\n
+  *         WKUPEPR   WKUPP5       LL_PWR_IsWakeUpPinPolarityLow\n
+  *         WKUPEPR   WKUPP6       LL_PWR_IsWakeUpPinPolarityLow
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  *         @arg @ref LL_PWR_WAKEUP_PIN6
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
+{
+  return ((READ_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) == (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the Wake-Up pin Pull None
+  * @rmtoll WKUPEPR   WKUPPUPD1       LL_PWR_SetWakeUpPinPullNone\n
+  *         WKUPEPR   WKUPPUPD2       LL_PWR_SetWakeUpPinPullNone\n
+  *         WKUPEPR   WKUPPUPD3       LL_PWR_SetWakeUpPinPullNone\n
+  *         WKUPEPR   WKUPPUPD4       LL_PWR_SetWakeUpPinPullNone\n
+  *         WKUPEPR   WKUPPUPD5       LL_PWR_SetWakeUpPinPullNone\n
+  *         WKUPEPR   WKUPPUPD6       LL_PWR_SetWakeUpPinPullNone
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  *         @arg @ref LL_PWR_WAKEUP_PIN6
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetWakeUpPinPullNone(uint32_t WakeUpPin)
+{
+  MODIFY_REG(PWR->WKUPEPR, \
+            (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \
+            (LL_PWR_WAKEUP_PIN_NOPULL << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
+}
+
+/**
+  * @brief  Set the Wake-Up pin Pull Up
+  * @rmtoll WKUPEPR   WKUPPUPD1       LL_PWR_SetWakeUpPinPullUp\n
+  *         WKUPEPR   WKUPPUPD2       LL_PWR_SetWakeUpPinPullUp\n
+  *         WKUPEPR   WKUPPUPD3       LL_PWR_SetWakeUpPinPullUp\n
+  *         WKUPEPR   WKUPPUPD4       LL_PWR_SetWakeUpPinPullUp\n
+  *         WKUPEPR   WKUPPUPD5       LL_PWR_SetWakeUpPinPullUp\n
+  *         WKUPEPR   WKUPPUPD6       LL_PWR_SetWakeUpPinPullUp
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  *         @arg @ref LL_PWR_WAKEUP_PIN6
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetWakeUpPinPullUp(uint32_t WakeUpPin)
+{
+  MODIFY_REG(PWR->WKUPEPR, \
+            (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \
+            (LL_PWR_WAKEUP_PIN_PULLUP << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
+}
+
+/**
+  * @brief  Set the Wake-Up pin Pull Down
+  * @rmtoll WKUPEPR   WKUPPUPD1       LL_PWR_SetWakeUpPinPullDown\n
+  *         WKUPEPR   WKUPPUPD2       LL_PWR_SetWakeUpPinPullDown\n
+  *         WKUPEPR   WKUPPUPD3       LL_PWR_SetWakeUpPinPullDown\n
+  *         WKUPEPR   WKUPPUPD4       LL_PWR_SetWakeUpPinPullDown\n
+  *         WKUPEPR   WKUPPUPD5       LL_PWR_SetWakeUpPinPullDown\n
+  *         WKUPEPR   WKUPPUPD6       LL_PWR_SetWakeUpPinPullDown
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  *         @arg @ref LL_PWR_WAKEUP_PIN6
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetWakeUpPinPullDown(uint32_t WakeUpPin)
+{
+  MODIFY_REG(PWR->WKUPEPR, \
+            (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \
+            (LL_PWR_WAKEUP_PIN_PULLDOWN << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
+}
+
+/**
+  * @brief  Get the Wake-Up pin pull
+  * @rmtoll WKUPEPR   WKUPPUPD1       LL_PWR_GetWakeUpPinPull\n
+  *         WKUPEPR   WKUPPUPD2       LL_PWR_GetWakeUpPinPull\n
+  *         WKUPEPR   WKUPPUPD3       LL_PWR_GetWakeUpPinPull\n
+  *         WKUPEPR   WKUPPUPD4       LL_PWR_GetWakeUpPinPull\n
+  *         WKUPEPR   WKUPPUPD5       LL_PWR_GetWakeUpPinPull\n
+  *         WKUPEPR   WKUPPUPD6       LL_PWR_GetWakeUpPinPull
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  *         @arg @ref LL_PWR_WAKEUP_PIN6
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN_NOPULL
+  *         @arg @ref LL_PWR_WAKEUP_PIN_PULLUP
+  *         @arg @ref LL_PWR_WAKEUP_PIN_PULLDOWN
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinPull(uint32_t WakeUpPin)
+{
+  register uint32_t regValue = READ_BIT(PWR->WKUPEPR, (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
+
+  return (uint32_t)(regValue >> ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Indicate whether VDD voltage is below the selected PVD threshold
+  * @rmtoll CSR1   PVDO       LL_PWR_IsActiveFlag_PVDO
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
+{
+  return ((READ_BIT(PWR->CSR1, PWR_CSR1_PVDO) == (PWR_CSR1_PVDO)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate whether the voltage level is ready for current actual used VOS
+  * @rmtoll CSR1   ACTVOSRDY       LL_PWR_IsActiveFlag_ACTVOS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ACTVOS(void)
+{
+  return ((READ_BIT(PWR->CSR1, PWR_CSR1_ACTVOSRDY) == (PWR_CSR1_ACTVOSRDY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate whether VDDA voltage is below the selected AVD threshold
+  * @rmtoll CSR1   AVDO       LL_PWR_IsActiveFlag_AVDO
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_AVDO(void)
+{
+  return ((READ_BIT(PWR->CSR1, PWR_CSR1_AVDO) == (PWR_CSR1_AVDO)) ? 1UL : 0UL);
+}
+
+#if defined (PWR_CSR1_MMCVDO)
+/**
+  * @brief  Indicate whether VDDMMC voltage is below 1V2
+  * @rmtoll CSR1   MMCVDO     LL_PWR_IsActiveFlag_MMCVDO
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_MMCVDO(void)
+{
+  return ((READ_BIT(PWR->CSR1, PWR_CSR1_MMCVDO) == (PWR_CSR1_MMCVDO)) ? 1UL : 0UL);
+}
+#endif /* PWR_CSR1_MMCVDO */
+
+/**
+  * @brief  Get Backup Regulator ready Flag
+  * @rmtoll CR2   BRRDY       LL_PWR_IsActiveFlag_BRR
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void)
+{
+  return ((READ_BIT(PWR->CR2, PWR_CR2_BRRDY) == (PWR_CR2_BRRDY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate whether the VBAT level is above or below low threshold
+  * @rmtoll CR2   VBATL       LL_PWR_IsActiveFlag_VBATL
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATL(void)
+{
+  return ((READ_BIT(PWR->CR2, PWR_CR2_VBATL) == (PWR_CR2_VBATL)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate whether the VBAT level is above or below high threshold
+  * @rmtoll CR2   VBATH       LL_PWR_IsActiveFlag_VBATH
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATH(void)
+{
+  return ((READ_BIT(PWR->CR2, PWR_CR2_VBATH) == (PWR_CR2_VBATH)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate whether the CPU temperature level is above or below low threshold
+  * @rmtoll CR2   TEMPL       LL_PWR_IsActiveFlag_TEMPL
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPL(void)
+{
+  return ((READ_BIT(PWR->CR2, PWR_CR2_TEMPL) == (PWR_CR2_TEMPL)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate whether the CPU temperature level is above or below high threshold
+  * @rmtoll CR2   TEMPH       LL_PWR_IsActiveFlag_TEMPH
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPH(void)
+{
+  return ((READ_BIT(PWR->CR2, PWR_CR2_TEMPH) == (PWR_CR2_TEMPH)) ? 1UL : 0UL);
+}
+
+#if defined (SMPS)
+/**
+  * @brief  Indicate whether the SMPS external supply is ready or not
+  * @rmtoll CR3   SMPSEXTRDY       LL_PWR_IsActiveFlag_SMPSEXT
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SMPSEXT(void)
+{
+  return ((READ_BIT(PWR->CR3, PWR_CR3_SMPSEXTRDY) == (PWR_CR3_SMPSEXTRDY)) ? 1UL : 0UL);
+}
+#endif /* SMPS */
+
+/**
+  * @brief  Indicate whether the USB supply is ready or not
+  * @rmtoll CR3   USBRDY       LL_PWR_IsActiveFlag_USB
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_USB(void)
+{
+  return ((READ_BIT(PWR->CR3, PWR_CR3_USB33RDY) == (PWR_CR3_USB33RDY)) ? 1UL : 0UL);
+}
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Get HOLD2 Flag
+  * @rmtoll CPUCR   HOLD2F       LL_PWR_IsActiveFlag_HOLD2
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_HOLD2(void)
+{
+  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2F) == (PWR_CPUCR_HOLD2F)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get HOLD1 Flag
+  * @rmtoll CPU2CR   HOLD1F       LL_PWR_IsActiveFlag_HOLD1
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_HOLD1(void)
+{
+  return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1F) == (PWR_CPU2CR_HOLD1F)) ? 1UL : 0UL);
+}
+#endif /* DUAL_CORE */
+
+/**
+  * @brief  Get CPU System Stop Flag
+  * @rmtoll CPUCR   STOPF       LL_PWR_CPU_IsActiveFlag_STOP
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_STOP(void)
+{
+  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_STOPF) == (PWR_CPUCR_STOPF)) ? 1UL : 0UL);
+}
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Get CPU2 System Stop Flag
+  * @rmtoll CPU2CR   STOPF       LL_PWR_CPU2_IsActiveFlag_STOP
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_STOP(void)
+{
+  return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_STOPF) == (PWR_CPU2CR_STOPF)) ? 1UL : 0UL);
+}
+#endif /* DUAL_CORE */
+
+/**
+  * @brief  Get CPU System Standby Flag
+  * @rmtoll CPUCR   SBF       LL_PWR_CPU_IsActiveFlag_SB
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB(void)
+{
+  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF) == (PWR_CPUCR_SBF)) ? 1UL : 0UL);
+}
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Get CPU2 System Standby Flag
+  * @rmtoll CPU2CR   SBF       LL_PWR_CPU2_IsActiveFlag_SB
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_SB(void)
+{
+  return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF) == (PWR_CPU2CR_SBF)) ? 1UL : 0UL);
+}
+#endif /* DUAL_CORE */
+
+#if defined (PWR_CPUCR_SBF_D1)
+/**
+  * @brief  Get CPU D1 Domain Standby Flag
+  * @rmtoll CPUCR   SBF_D1       LL_PWR_CPU_IsActiveFlag_SB_D1
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB_D1(void)
+{
+  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D1) == (PWR_CPUCR_SBF_D1)) ? 1UL : 0UL);
+}
+#endif /* PWR_CPUCR_SBF_D1 */
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Get CPU2 D1 Domain Standby Flag
+  * @rmtoll CPU2CR   SBF_D1       LL_PWR_CPU2_IsActiveFlag_SB_D1
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_SB_D1(void)
+{
+  return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D1) == (PWR_CPU2CR_SBF_D1)) ? 1UL : 0UL);
+}
+#endif /* DUAL_CORE */
+
+#if defined (PWR_CPUCR_SBF_D2)
+/**
+  * @brief  Get CPU D2 Domain Standby Flag
+  * @rmtoll CPUCR   SBF_D2       LL_PWR_CPU_IsActiveFlag_SB_D2
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB_D2(void)
+{
+  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D2) == (PWR_CPUCR_SBF_D2)) ? 1UL : 0UL);
+}
+#endif /* PWR_CPUCR_SBF_D2 */
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Get CPU2 D2 Domain Standby Flag
+  * @rmtoll CPU2CR   SBF_D2       LL_PWR_CPU2_IsActiveFlag_SB_D2
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_SB_D2(void)
+{
+  return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D2) == (PWR_CPU2CR_SBF_D2)) ? 1UL : 0UL);
+}
+#endif /* DUAL_CORE */
+
+
+/**
+  * @brief  Indicate whether the Regulator is ready in the selected voltage range
+  *         or if its output voltage is still changing to the required voltage level
+  * @rmtoll D3CR   VOSRDY       LL_PWR_IsActiveFlag_VOS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
+{
+#if defined (PWR_CPUCR_PDDS_D2)
+  return ((READ_BIT(PWR->D3CR, PWR_D3CR_VOSRDY) == (PWR_D3CR_VOSRDY)) ? 1UL : 0UL);
+#else
+  return ((READ_BIT(PWR->SRDCR, PWR_SRDCR_VOSRDY) == (PWR_SRDCR_VOSRDY)) ? 1UL : 0UL);
+#endif /* PWR_CPUCR_PDDS_D2 */
+}
+
+/**
+  * @brief  Get Wake-up Flag 6
+  * @rmtoll WKUPFR          WKUPF6          LL_PWR_IsActiveFlag_WU6
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void)
+{
+  return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF6) == (PWR_WKUPFR_WKUPF6)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Wake-up Flag 5
+  * @rmtoll WKUPFR          WKUPF5          LL_PWR_IsActiveFlag_WU5
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
+{
+  return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF5) == (PWR_WKUPFR_WKUPF5)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Wake-up Flag 4
+  * @rmtoll WKUPFR          WKUPF4          LL_PWR_IsActiveFlag_WU4
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
+{
+  return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF4) == (PWR_WKUPFR_WKUPF4)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Wake-up Flag 3
+  * @rmtoll WKUPFR          WKUPF3          LL_PWR_IsActiveFlag_WU3
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
+{
+  return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF3) == (PWR_WKUPFR_WKUPF3)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Wake-up Flag 2
+  * @rmtoll WKUPFR          WKUPF2          LL_PWR_IsActiveFlag_WU2
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
+{
+  return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF2) == (PWR_WKUPFR_WKUPF2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Wake-up Flag 1
+  * @rmtoll WKUPFR          WKUPF1          LL_PWR_IsActiveFlag_WU1
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
+{
+  return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF1) == (PWR_WKUPFR_WKUPF1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear CPU STANDBY, STOP and HOLD flags
+  * @rmtoll CPUCR   CSSF       LL_PWR_ClearFlag_CPU
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_CPU(void)
+{
+  SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF);
+}
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Clear CPU2 STANDBY, STOP and HOLD flags
+  * @rmtoll CPU2CR   CSSF       LL_PWR_ClearFlag_CPU2
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_CPU2(void)
+{
+  SET_BIT(PWR->CPU2CR, PWR_CPU2CR_CSSF);
+}
+#endif /* DUAL_CORE */
+
+/**
+  * @brief  Clear Wake-up Flag 6
+  * @rmtoll WKUPCR          WKUPC6         LL_PWR_ClearFlag_WU6
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU6(void)
+{
+  WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC6);
+}
+
+/**
+  * @brief  Clear Wake-up Flag 5
+  * @rmtoll WKUPCR          WKUPC5         LL_PWR_ClearFlag_WU5
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
+{
+  WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC5);
+}
+
+/**
+  * @brief  Clear Wake-up Flag 4
+  * @rmtoll WKUPCR          WKUPC4         LL_PWR_ClearFlag_WU4
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
+{
+  WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC4);
+}
+
+/**
+  * @brief  Clear Wake-up Flag 3
+  * @rmtoll WKUPCR          WKUPC3         LL_PWR_ClearFlag_WU3
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
+{
+  WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC3);
+}
+
+/**
+  * @brief  Clear Wake-up Flag 2
+  * @rmtoll WKUPCR          WKUPC2         LL_PWR_ClearFlag_WU2
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
+{
+  WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC2);
+}
+
+/**
+  * @brief  Clear Wake-up Flag 1
+  * @rmtoll WKUPCR          WKUPC1         LL_PWR_ClearFlag_WU1
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
+{
+  WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC1);
+}
+
+#if defined (USE_FULL_LL_DRIVER)
+/** @defgroup PWR_LL_EF_Init De-initialization function
+  * @{
+  */
+ErrorStatus LL_PWR_DeInit(void);
+/**
+  * @}
+  */
+#endif /* defined (USE_FULL_LL_DRIVER) */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (PWR) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_LL_PWR_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rcc.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rcc.h
new file mode 100644
index 00000000..2fdd1d02
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rcc.h
@@ -0,0 +1,6326 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_rcc.h
+  * @author  MCD Application Team
+  * @version $VERSION$
+  * @date    $DATE$
+  * @brief   Header file of RCC LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_LL_RCC_H
+#define STM32H7xx_LL_RCC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+#include <math.h>
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined(RCC)
+
+/** @defgroup RCC_LL RCC
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup RCC_LL_Private_Variables RCC Private Variables
+  * @{
+  */
+extern const uint8_t LL_RCC_PrescTable[16];
+
+/**
+  * @}
+  */
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+#if !defined(UNUSED)
+#define UNUSED(x) ((void)(x))
+#endif
+
+/* 32            24           16            8             0
+   --------------------------------------------------------
+   | Mask        | ClkSource   |  Bit       | Register    |
+   |             |  Config     | Position   | Offset      |
+   --------------------------------------------------------*/
+
+#if defined(RCC_VER_2_0)
+/* Clock source register offset Vs CDCCIPR regsiter */
+#define CDCCIP    0x0UL
+#define CDCCIP1   0x4UL
+#define CDCCIP2   0x8UL
+#define SRDCCIP   0xCUL
+#else
+/* Clock source register offset Vs D1CCIPR regsiter */
+#define D1CCIP    0x0UL
+#define D2CCIP1   0x4UL
+#define D2CCIP2   0x8UL
+#define D3CCIP    0xCUL
+#endif /* RCC_VER_2_0 */
+
+#define LL_RCC_REG_SHIFT     0U
+#define LL_RCC_POS_SHIFT     8U
+#define LL_RCC_CONFIG_SHIFT  16U
+#define LL_RCC_MASK_SHIFT    24U
+
+#define LL_CLKSOURCE_SHIFT(__CLKSOURCE__)   (((__CLKSOURCE__) >> LL_RCC_POS_SHIFT   ) & 0x1FUL)
+
+#define LL_CLKSOURCE_MASK(__CLKSOURCE__)   ((((__CLKSOURCE__) >> LL_RCC_MASK_SHIFT  ) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__))
+
+#define LL_CLKSOURCE_CONFIG(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_CONFIG_SHIFT) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__))
+
+#define LL_CLKSOURCE_REG(__CLKSOURCE__)     (((__CLKSOURCE__) >> LL_RCC_REG_SHIFT   ) & 0xFFUL)
+
+#define LL_CLKSOURCE(__REG__, __MSK__, __POS__, __CLK__) ((uint32_t)((((__MSK__) >> (__POS__)) << LL_RCC_MASK_SHIFT) | \
+                                                                     (( __POS__              ) << LL_RCC_POS_SHIFT)  | \
+                                                                     (( __REG__              ) << LL_RCC_REG_SHIFT)  | \
+                                                                     (((__CLK__) >> (__POS__)) << LL_RCC_CONFIG_SHIFT)))
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_Private_Macros RCC Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_Exported_Types RCC Exported Types
+  * @{
+  */
+
+/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
+  * @{
+  */
+
+/**
+  * @brief  RCC Clocks Frequency Structure
+  */
+typedef struct
+{
+  uint32_t SYSCLK_Frequency;
+  uint32_t CPUCLK_Frequency;
+  uint32_t HCLK_Frequency;
+  uint32_t PCLK1_Frequency;
+  uint32_t PCLK2_Frequency;
+  uint32_t PCLK3_Frequency;
+  uint32_t PCLK4_Frequency;
+} LL_RCC_ClocksTypeDef;
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  PLL Clocks Frequency Structure
+  */
+typedef struct
+{
+  uint32_t PLL_P_Frequency;
+  uint32_t PLL_Q_Frequency;
+  uint32_t PLL_R_Frequency;
+} LL_PLL_ClocksTypeDef;
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
+  * @{
+  */
+
+/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
+  * @brief    Defines used to adapt values of different oscillators
+  * @note     These values could be modified in the user environment according to
+  *           HW set-up.
+  * @{
+  */
+#if !defined  (HSE_VALUE)
+#if defined(RCC_VER_X)
+#define HSE_VALUE    25000000U  /*!< Value of the HSE oscillator in Hz */
+#else
+#define HSE_VALUE    24000000U  /*!< Value of the HSE oscillator in Hz */
+#endif /* RCC_VER_X */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    64000000U  /*!< Value of the HSI oscillator in Hz */
+#endif /* HSI_VALUE */
+
+#if !defined  (CSI_VALUE)
+#define CSI_VALUE    4000000U   /*!< Value of the CSI oscillator in Hz */
+#endif /* CSI_VALUE */
+
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U     /*!< Value of the LSE oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined  (LSI_VALUE)
+#define LSI_VALUE    32000U     /*!< Value of the LSI oscillator in Hz */
+#endif /* LSI_VALUE */
+
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+#define EXTERNAL_CLOCK_VALUE    12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+#if !defined  (HSI48_VALUE)
+#define HSI48_VALUE  48000000U  /*!< Value of the HSI48 oscillator in Hz */
+#endif /* HSI48_VALUE */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_HSIDIV  HSI oscillator divider
+  * @{
+  */
+#define LL_RCC_HSI_DIV1                   RCC_CR_HSIDIV_1
+#define LL_RCC_HSI_DIV2                   RCC_CR_HSIDIV_2
+#define LL_RCC_HSI_DIV4                   RCC_CR_HSIDIV_4
+#define LL_RCC_HSI_DIV8                   RCC_CR_HSIDIV_8
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_LSEDRIVE  LSE oscillator drive capability
+  * @{
+  */
+#define LL_RCC_LSEDRIVE_LOW                (uint32_t)(0x00000000U)
+#define LL_RCC_LSEDRIVE_MEDIUMLOW          (uint32_t)(RCC_BDCR_LSEDRV_0)
+#define LL_RCC_LSEDRIVE_MEDIUMHIGH         (uint32_t)(RCC_BDCR_LSEDRV_1)
+#define LL_RCC_LSEDRIVE_HIGH               (uint32_t)(RCC_BDCR_LSEDRV)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SYS_CLKSOURCE  System clock switch
+  * @{
+  */
+#define LL_RCC_SYS_CLKSOURCE_HSI           RCC_CFGR_SW_HSI
+#define LL_RCC_SYS_CLKSOURCE_CSI           RCC_CFGR_SW_CSI
+#define LL_RCC_SYS_CLKSOURCE_HSE           RCC_CFGR_SW_HSE
+#define LL_RCC_SYS_CLKSOURCE_PLL1          RCC_CFGR_SW_PLL1
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS  System clock switch status
+  * @{
+  */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_CSI    RCC_CFGR_SWS_CSI   /*!< CSI used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL1   RCC_CFGR_SWS_PLL1  /*!< PLL1 used as system clock */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SYSWAKEUP_CLKSOURCE  System wakeup clock source
+  * @{
+  */
+#define LL_RCC_SYSWAKEUP_CLKSOURCE_HSI     (uint32_t)(0x00000000U)
+#define LL_RCC_SYSWAKEUP_CLKSOURCE_CSI     (uint32_t)(RCC_CFGR_STOPWUCK)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_KERWAKEUP_CLKSOURCE  Kernel wakeup clock source
+  * @{
+  */
+#define LL_RCC_KERWAKEUP_CLKSOURCE_HSI     (uint32_t)(0x00000000U)
+#define LL_RCC_KERWAKEUP_CLKSOURCE_CSI     (uint32_t)(RCC_CFGR_STOPKERWUCK)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SYSCLK_DIV  System prescaler
+  * @{
+  */
+#if defined(RCC_D1CFGR_D1CPRE_DIV1)
+#define LL_RCC_SYSCLK_DIV_1                RCC_D1CFGR_D1CPRE_DIV1
+#define LL_RCC_SYSCLK_DIV_2                RCC_D1CFGR_D1CPRE_DIV2
+#define LL_RCC_SYSCLK_DIV_4                RCC_D1CFGR_D1CPRE_DIV4
+#define LL_RCC_SYSCLK_DIV_8                RCC_D1CFGR_D1CPRE_DIV8
+#define LL_RCC_SYSCLK_DIV_16               RCC_D1CFGR_D1CPRE_DIV16
+#define LL_RCC_SYSCLK_DIV_64               RCC_D1CFGR_D1CPRE_DIV64
+#define LL_RCC_SYSCLK_DIV_128              RCC_D1CFGR_D1CPRE_DIV128
+#define LL_RCC_SYSCLK_DIV_256              RCC_D1CFGR_D1CPRE_DIV256
+#define LL_RCC_SYSCLK_DIV_512              RCC_D1CFGR_D1CPRE_DIV512
+#else
+#define LL_RCC_SYSCLK_DIV_1                RCC_CDCFGR1_CDCPRE_DIV1
+#define LL_RCC_SYSCLK_DIV_2                RCC_CDCFGR1_CDCPRE_DIV2
+#define LL_RCC_SYSCLK_DIV_4                RCC_CDCFGR1_CDCPRE_DIV4
+#define LL_RCC_SYSCLK_DIV_8                RCC_CDCFGR1_CDCPRE_DIV8
+#define LL_RCC_SYSCLK_DIV_16               RCC_CDCFGR1_CDCPRE_DIV16
+#define LL_RCC_SYSCLK_DIV_64               RCC_CDCFGR1_CDCPRE_DIV64
+#define LL_RCC_SYSCLK_DIV_128              RCC_CDCFGR1_CDCPRE_DIV128
+#define LL_RCC_SYSCLK_DIV_256              RCC_CDCFGR1_CDCPRE_DIV256
+#define LL_RCC_SYSCLK_DIV_512              RCC_CDCFGR1_CDCPRE_DIV512
+#endif /* RCC_D1CFGR_D1CPRE_DIV1 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_AHB_DIV  AHB prescaler
+  * @{
+  */
+#if defined(RCC_D1CFGR_HPRE_DIV1)
+#define LL_RCC_AHB_DIV_1                   RCC_D1CFGR_HPRE_DIV1
+#define LL_RCC_AHB_DIV_2                   RCC_D1CFGR_HPRE_DIV2
+#define LL_RCC_AHB_DIV_4                   RCC_D1CFGR_HPRE_DIV4
+#define LL_RCC_AHB_DIV_8                   RCC_D1CFGR_HPRE_DIV8
+#define LL_RCC_AHB_DIV_16                  RCC_D1CFGR_HPRE_DIV16
+#define LL_RCC_AHB_DIV_64                  RCC_D1CFGR_HPRE_DIV64
+#define LL_RCC_AHB_DIV_128                 RCC_D1CFGR_HPRE_DIV128
+#define LL_RCC_AHB_DIV_256                 RCC_D1CFGR_HPRE_DIV256
+#define LL_RCC_AHB_DIV_512                 RCC_D1CFGR_HPRE_DIV512
+#else
+#define LL_RCC_AHB_DIV_1                   RCC_CDCFGR1_HPRE_DIV1
+#define LL_RCC_AHB_DIV_2                   RCC_CDCFGR1_HPRE_DIV2
+#define LL_RCC_AHB_DIV_4                   RCC_CDCFGR1_HPRE_DIV4
+#define LL_RCC_AHB_DIV_8                   RCC_CDCFGR1_HPRE_DIV8
+#define LL_RCC_AHB_DIV_16                  RCC_CDCFGR1_HPRE_DIV16
+#define LL_RCC_AHB_DIV_64                  RCC_CDCFGR1_HPRE_DIV64
+#define LL_RCC_AHB_DIV_128                 RCC_CDCFGR1_HPRE_DIV128
+#define LL_RCC_AHB_DIV_256                 RCC_CDCFGR1_HPRE_DIV256
+#define LL_RCC_AHB_DIV_512                 RCC_CDCFGR1_HPRE_DIV512
+#endif /* RCC_D1CFGR_HPRE_DIV1 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_APB1_DIV  APB low-speed prescaler (APB1)
+  * @{
+  */
+#if defined(RCC_D2CFGR_D2PPRE1_DIV1)
+#define LL_RCC_APB1_DIV_1                  RCC_D2CFGR_D2PPRE1_DIV1
+#define LL_RCC_APB1_DIV_2                  RCC_D2CFGR_D2PPRE1_DIV2
+#define LL_RCC_APB1_DIV_4                  RCC_D2CFGR_D2PPRE1_DIV4
+#define LL_RCC_APB1_DIV_8                  RCC_D2CFGR_D2PPRE1_DIV8
+#define LL_RCC_APB1_DIV_16                 RCC_D2CFGR_D2PPRE1_DIV16
+#else
+#define LL_RCC_APB1_DIV_1                  RCC_CDCFGR2_CDPPRE1_DIV1
+#define LL_RCC_APB1_DIV_2                  RCC_CDCFGR2_CDPPRE1_DIV2
+#define LL_RCC_APB1_DIV_4                  RCC_CDCFGR2_CDPPRE1_DIV4
+#define LL_RCC_APB1_DIV_8                  RCC_CDCFGR2_CDPPRE1_DIV8
+#define LL_RCC_APB1_DIV_16                 RCC_CDCFGR2_CDPPRE1_DIV16
+#endif /* RCC_D2CFGR_D2PPRE1_DIV1 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_APB2_DIV  APB low-speed prescaler (APB2)
+  * @{
+  */
+#if defined(RCC_D2CFGR_D2PPRE2_DIV1)
+#define LL_RCC_APB2_DIV_1                  RCC_D2CFGR_D2PPRE2_DIV1
+#define LL_RCC_APB2_DIV_2                  RCC_D2CFGR_D2PPRE2_DIV2
+#define LL_RCC_APB2_DIV_4                  RCC_D2CFGR_D2PPRE2_DIV4
+#define LL_RCC_APB2_DIV_8                  RCC_D2CFGR_D2PPRE2_DIV8
+#define LL_RCC_APB2_DIV_16                 RCC_D2CFGR_D2PPRE2_DIV16
+#else
+#define LL_RCC_APB2_DIV_1                  RCC_CDCFGR2_CDPPRE2_DIV1
+#define LL_RCC_APB2_DIV_2                  RCC_CDCFGR2_CDPPRE2_DIV2
+#define LL_RCC_APB2_DIV_4                  RCC_CDCFGR2_CDPPRE2_DIV4
+#define LL_RCC_APB2_DIV_8                  RCC_CDCFGR2_CDPPRE2_DIV8
+#define LL_RCC_APB2_DIV_16                 RCC_CDCFGR2_CDPPRE2_DIV16
+#endif /* RCC_D2CFGR_D2PPRE2_DIV1 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_APB3_DIV  APB low-speed prescaler (APB3)
+  * @{
+  */
+#if defined(RCC_D1CFGR_D1PPRE_DIV1)
+#define LL_RCC_APB3_DIV_1                  RCC_D1CFGR_D1PPRE_DIV1
+#define LL_RCC_APB3_DIV_2                  RCC_D1CFGR_D1PPRE_DIV2
+#define LL_RCC_APB3_DIV_4                  RCC_D1CFGR_D1PPRE_DIV4
+#define LL_RCC_APB3_DIV_8                  RCC_D1CFGR_D1PPRE_DIV8
+#define LL_RCC_APB3_DIV_16                 RCC_D1CFGR_D1PPRE_DIV16
+#else
+#define LL_RCC_APB3_DIV_1                  RCC_CDCFGR1_CDPPRE_DIV1
+#define LL_RCC_APB3_DIV_2                  RCC_CDCFGR1_CDPPRE_DIV2
+#define LL_RCC_APB3_DIV_4                  RCC_CDCFGR1_CDPPRE_DIV4
+#define LL_RCC_APB3_DIV_8                  RCC_CDCFGR1_CDPPRE_DIV8
+#define LL_RCC_APB3_DIV_16                 RCC_CDCFGR1_CDPPRE_DIV16
+#endif /* RCC_D1CFGR_D1PPRE_DIV1 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_APB4_DIV  APB low-speed prescaler (APB4)
+  * @{
+  */
+#if defined(RCC_D3CFGR_D3PPRE_DIV1)
+#define LL_RCC_APB4_DIV_1                  RCC_D3CFGR_D3PPRE_DIV1
+#define LL_RCC_APB4_DIV_2                  RCC_D3CFGR_D3PPRE_DIV2
+#define LL_RCC_APB4_DIV_4                  RCC_D3CFGR_D3PPRE_DIV4
+#define LL_RCC_APB4_DIV_8                  RCC_D3CFGR_D3PPRE_DIV8
+#define LL_RCC_APB4_DIV_16                 RCC_D3CFGR_D3PPRE_DIV16
+#else
+#define LL_RCC_APB4_DIV_1                  RCC_SRDCFGR_SRDPPRE_DIV1
+#define LL_RCC_APB4_DIV_2                  RCC_SRDCFGR_SRDPPRE_DIV2
+#define LL_RCC_APB4_DIV_4                  RCC_SRDCFGR_SRDPPRE_DIV4
+#define LL_RCC_APB4_DIV_8                  RCC_SRDCFGR_SRDPPRE_DIV8
+#define LL_RCC_APB4_DIV_16                 RCC_SRDCFGR_SRDPPRE_DIV16
+#endif /* RCC_D3CFGR_D3PPRE_DIV1 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_MCOxSOURCE  MCO source selection
+  * @{
+  */
+#define LL_RCC_MCO1SOURCE_HSI              (uint32_t)((RCC_CFGR_MCO1>>16U) | 0x00000000U)
+#define LL_RCC_MCO1SOURCE_LSE              (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_0)
+#define LL_RCC_MCO1SOURCE_HSE              (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_1)
+#define LL_RCC_MCO1SOURCE_PLL1QCLK         (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0)
+#define LL_RCC_MCO1SOURCE_HSI48            (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_2)
+#define LL_RCC_MCO2SOURCE_SYSCLK           (uint32_t)((RCC_CFGR_MCO2>>16U) | 0x00000000U)
+#define LL_RCC_MCO2SOURCE_PLL2PCLK         (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_0)
+#define LL_RCC_MCO2SOURCE_HSE              (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_1)
+#define LL_RCC_MCO2SOURCE_PLL1PCLK         (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0)
+#define LL_RCC_MCO2SOURCE_CSI              (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_2)
+#define LL_RCC_MCO2SOURCE_LSI              (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_2|RCC_CFGR_MCO2_0)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_MCOx_DIV  MCO prescaler
+  * @{
+  */
+#define LL_RCC_MCO1_DIV_1                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0)
+#define LL_RCC_MCO1_DIV_2                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1)
+#define LL_RCC_MCO1_DIV_3                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1)
+#define LL_RCC_MCO1_DIV_4                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2)
+#define LL_RCC_MCO1_DIV_5                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
+#define LL_RCC_MCO1_DIV_6                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
+#define LL_RCC_MCO1_DIV_7                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
+#define LL_RCC_MCO1_DIV_8                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_3)
+#define LL_RCC_MCO1_DIV_9                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_3)
+#define LL_RCC_MCO1_DIV_10                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
+#define LL_RCC_MCO1_DIV_11                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
+#define LL_RCC_MCO1_DIV_12                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
+#define LL_RCC_MCO1_DIV_13                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
+#define LL_RCC_MCO1_DIV_14                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
+#define LL_RCC_MCO1_DIV_15                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE)
+#define LL_RCC_MCO2_DIV_1                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0)
+#define LL_RCC_MCO2_DIV_2                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1)
+#define LL_RCC_MCO2_DIV_3                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1)
+#define LL_RCC_MCO2_DIV_4                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2)
+#define LL_RCC_MCO2_DIV_5                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_2)
+#define LL_RCC_MCO2_DIV_6                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2)
+#define LL_RCC_MCO2_DIV_7                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2)
+#define LL_RCC_MCO2_DIV_8                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_3)
+#define LL_RCC_MCO2_DIV_9                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_3)
+#define LL_RCC_MCO2_DIV_10                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_3)
+#define LL_RCC_MCO2_DIV_11                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_3)
+#define LL_RCC_MCO2_DIV_12                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3)
+#define LL_RCC_MCO2_DIV_13                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3)
+#define LL_RCC_MCO2_DIV_14                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3)
+#define LL_RCC_MCO2_DIV_15                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_RTC_HSEDIV  HSE prescaler for RTC clock
+  * @{
+  */
+#define LL_RCC_RTC_NOCLOCK                  (uint32_t)(0x00000000U)
+#define LL_RCC_RTC_HSE_DIV_2                (uint32_t)(RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_3                (uint32_t)(RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_4                (uint32_t)(RCC_CFGR_RTCPRE_2)
+#define LL_RCC_RTC_HSE_DIV_5                (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_6                (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_7                (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_8                (uint32_t)(RCC_CFGR_RTCPRE_3)
+#define LL_RCC_RTC_HSE_DIV_9                (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_10               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_11               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_12               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
+#define LL_RCC_RTC_HSE_DIV_13               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_14               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_15               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_16               (uint32_t)(RCC_CFGR_RTCPRE_4)
+#define LL_RCC_RTC_HSE_DIV_17               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_18               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_19               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_20               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2)
+#define LL_RCC_RTC_HSE_DIV_21               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_22               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_23               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_24               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3)
+#define LL_RCC_RTC_HSE_DIV_25               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_26               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_27               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_28               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
+#define LL_RCC_RTC_HSE_DIV_29               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_30               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_31               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_32               (uint32_t)(RCC_CFGR_RTCPRE_5)
+#define LL_RCC_RTC_HSE_DIV_33               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_34               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_35               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_36               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2)
+#define LL_RCC_RTC_HSE_DIV_37               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_38               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_39               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_40               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3)
+#define LL_RCC_RTC_HSE_DIV_41               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_42               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_43               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_44               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
+#define LL_RCC_RTC_HSE_DIV_45               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_46               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_47               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_48               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4)
+#define LL_RCC_RTC_HSE_DIV_49               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_50               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_51               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_52               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2)
+#define LL_RCC_RTC_HSE_DIV_53               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_54               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_55               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_56               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3)
+#define LL_RCC_RTC_HSE_DIV_57               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_58               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_59               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_60               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
+#define LL_RCC_RTC_HSE_DIV_61               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_62               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_63               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_USARTx_CLKSOURCE  Peripheral USART clock source selection
+  * @{
+  */
+#if defined(RCC_D2CCIP2R_USART16SEL)
+#define LL_RCC_USART16_CLKSOURCE_PCLK2         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, 0x00000000U)
+#define LL_RCC_USART16_CLKSOURCE_PLL2Q         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0)
+#define LL_RCC_USART16_CLKSOURCE_PLL3Q         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_1)
+#define LL_RCC_USART16_CLKSOURCE_HSI           LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_1)
+#define LL_RCC_USART16_CLKSOURCE_CSI           LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_2)
+#define LL_RCC_USART16_CLKSOURCE_LSE           LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_2)
+#else
+#define LL_RCC_USART16910_CLKSOURCE_PCLK2      LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, 0x00000000U)
+#define LL_RCC_USART16910_CLKSOURCE_PLL2Q      LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0)
+#define LL_RCC_USART16910_CLKSOURCE_PLL3Q      LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_1)
+#define LL_RCC_USART16910_CLKSOURCE_HSI        LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_1)
+#define LL_RCC_USART16910_CLKSOURCE_CSI        LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_2)
+#define LL_RCC_USART16910_CLKSOURCE_LSE        LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_2)
+/*  Aliases */
+#define LL_RCC_USART16_CLKSOURCE_PCLK2         LL_RCC_USART16910_CLKSOURCE_PCLK2
+#define LL_RCC_USART16_CLKSOURCE_PLL2Q         LL_RCC_USART16910_CLKSOURCE_PLL2Q
+#define LL_RCC_USART16_CLKSOURCE_PLL3Q         LL_RCC_USART16910_CLKSOURCE_PLL3Q
+#define LL_RCC_USART16_CLKSOURCE_HSI           LL_RCC_USART16910_CLKSOURCE_HSI
+#define LL_RCC_USART16_CLKSOURCE_CSI           LL_RCC_USART16910_CLKSOURCE_CSI
+#define LL_RCC_USART16_CLKSOURCE_LSE           LL_RCC_USART16910_CLKSOURCE_LSE
+#endif  /* RCC_D2CCIP2R_USART16SEL */
+#if defined(RCC_D2CCIP2R_USART28SEL)
+#define LL_RCC_USART234578_CLKSOURCE_PCLK1     LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, 0x00000000U)
+#define LL_RCC_USART234578_CLKSOURCE_PLL2Q     LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0)
+#define LL_RCC_USART234578_CLKSOURCE_PLL3Q     LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_1)
+#define LL_RCC_USART234578_CLKSOURCE_HSI       LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)
+#define LL_RCC_USART234578_CLKSOURCE_CSI       LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_2)
+#define LL_RCC_USART234578_CLKSOURCE_LSE       LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)
+#else
+#define LL_RCC_USART234578_CLKSOURCE_PCLK1     LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, 0x00000000U)
+#define LL_RCC_USART234578_CLKSOURCE_PLL2Q     LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0)
+#define LL_RCC_USART234578_CLKSOURCE_PLL3Q     LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_1)
+#define LL_RCC_USART234578_CLKSOURCE_HSI       LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_1)
+#define LL_RCC_USART234578_CLKSOURCE_CSI       LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_2)
+#define LL_RCC_USART234578_CLKSOURCE_LSE       LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_2)
+#endif /* RCC_D2CCIP2R_USART28SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_LPUARTx_CLKSOURCE  Peripheral LPUART clock source selection
+  * @{
+  */
+#if defined(RCC_D3CCIPR_LPUART1SEL)
+#define LL_RCC_LPUART1_CLKSOURCE_PCLK4         (0x00000000U)
+#define LL_RCC_LPUART1_CLKSOURCE_PLL2Q         (RCC_D3CCIPR_LPUART1SEL_0)
+#define LL_RCC_LPUART1_CLKSOURCE_PLL3Q         (RCC_D3CCIPR_LPUART1SEL_1)
+#define LL_RCC_LPUART1_CLKSOURCE_HSI           (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_1)
+#define LL_RCC_LPUART1_CLKSOURCE_CSI           (RCC_D3CCIPR_LPUART1SEL_2)
+#define LL_RCC_LPUART1_CLKSOURCE_LSE           (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_2)
+#else
+#define LL_RCC_LPUART1_CLKSOURCE_PCLK4         (0x00000000U)
+#define LL_RCC_LPUART1_CLKSOURCE_PLL2Q         (RCC_SRDCCIPR_LPUART1SEL_0)
+#define LL_RCC_LPUART1_CLKSOURCE_PLL3Q         (RCC_SRDCCIPR_LPUART1SEL_1)
+#define LL_RCC_LPUART1_CLKSOURCE_HSI           (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_1)
+#define LL_RCC_LPUART1_CLKSOURCE_CSI           (RCC_SRDCCIPR_LPUART1SEL_2)
+#define LL_RCC_LPUART1_CLKSOURCE_LSE           (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_2)
+#endif /* RCC_D3CCIPR_LPUART1SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE  Peripheral I2C clock source selection
+  * @{
+  */
+#if defined (RCC_D2CCIP2R_I2C123SEL)
+#define LL_RCC_I2C123_CLKSOURCE_PCLK1          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, 0x00000000U)
+#define LL_RCC_I2C123_CLKSOURCE_PLL3R          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_0)
+#define LL_RCC_I2C123_CLKSOURCE_HSI            LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_1)
+#define LL_RCC_I2C123_CLKSOURCE_CSI            LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1)
+#else
+#define LL_RCC_I2C123_CLKSOURCE_PCLK1          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, 0x00000000U)
+#define LL_RCC_I2C123_CLKSOURCE_PLL3R          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_0)
+#define LL_RCC_I2C123_CLKSOURCE_HSI            LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_1)
+#define LL_RCC_I2C123_CLKSOURCE_CSI            LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_0 | RCC_CDCCIP2R_I2C123SEL_1)
+#endif /* RCC_D2CCIP2R_I2C123SEL */
+#if defined (RCC_D3CCIPR_I2C4SEL)
+#define LL_RCC_I2C4_CLKSOURCE_PCLK4            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_I2C4SEL,    RCC_D3CCIPR_I2C4SEL_Pos,    0x00000000U)
+#define LL_RCC_I2C4_CLKSOURCE_PLL3R            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_I2C4SEL,    RCC_D3CCIPR_I2C4SEL_Pos,    RCC_D3CCIPR_I2C4SEL_0)
+#define LL_RCC_I2C4_CLKSOURCE_HSI              LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_I2C4SEL,    RCC_D3CCIPR_I2C4SEL_Pos,    RCC_D3CCIPR_I2C4SEL_1)
+#define LL_RCC_I2C4_CLKSOURCE_CSI              LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_I2C4SEL,    RCC_D3CCIPR_I2C4SEL_Pos,    RCC_D3CCIPR_I2C4SEL_0 | RCC_D3CCIPR_I2C4SEL_1)
+#else
+#define LL_RCC_I2C4_CLKSOURCE_PCLK4            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_I2C4SEL,    RCC_SRDCCIPR_I2C4SEL_Pos,    0x00000000U)
+#define LL_RCC_I2C4_CLKSOURCE_PLL3R            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_I2C4SEL,    RCC_SRDCCIPR_I2C4SEL_Pos,    RCC_SRDCCIPR_I2C4SEL_0)
+#define LL_RCC_I2C4_CLKSOURCE_HSI              LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_I2C4SEL,    RCC_SRDCCIPR_I2C4SEL_Pos,    RCC_SRDCCIPR_I2C4SEL_1)
+#define LL_RCC_I2C4_CLKSOURCE_CSI              LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_I2C4SEL,    RCC_SRDCCIPR_I2C4SEL_Pos,    RCC_SRDCCIPR_I2C4SEL_0 | RCC_SRDCCIPR_I2C4SEL_1)
+#endif /* RCC_D3CCIPR_I2C4SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_LPTIMx_CLKSOURCE  Peripheral LPTIM clock source selection
+  * @{
+  */
+#if defined(RCC_D2CCIP2R_LPTIM1SEL)
+#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  0x00000000U)
+#define LL_RCC_LPTIM1_CLKSOURCE_PLL2P          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  RCC_D2CCIP2R_LPTIM1SEL_0)
+#define LL_RCC_LPTIM1_CLKSOURCE_PLL3R          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  RCC_D2CCIP2R_LPTIM1SEL_1)
+#define LL_RCC_LPTIM1_CLKSOURCE_LSE            LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_1)
+#define LL_RCC_LPTIM1_CLKSOURCE_LSI            LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  RCC_D2CCIP2R_LPTIM1SEL_2)
+#define LL_RCC_LPTIM1_CLKSOURCE_CLKP           LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_2)
+#else
+#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  0x00000000U)
+#define LL_RCC_LPTIM1_CLKSOURCE_PLL2P          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  RCC_CDCCIP2R_LPTIM1SEL_0)
+#define LL_RCC_LPTIM1_CLKSOURCE_PLL3R          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  RCC_CDCCIP2R_LPTIM1SEL_1)
+#define LL_RCC_LPTIM1_CLKSOURCE_LSE            LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_1)
+#define LL_RCC_LPTIM1_CLKSOURCE_LSI            LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  RCC_CDCCIP2R_LPTIM1SEL_2)
+#define LL_RCC_LPTIM1_CLKSOURCE_CLKP           LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_2)
+#endif /* RCC_D2CCIP2R_LPTIM1SEL */
+#if defined(RCC_D3CCIPR_LPTIM2SEL)
+#define LL_RCC_LPTIM2_CLKSOURCE_PCLK4          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   0x00000000U)
+#define LL_RCC_LPTIM2_CLKSOURCE_PLL2P          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   RCC_D3CCIPR_LPTIM2SEL_0)
+#define LL_RCC_LPTIM2_CLKSOURCE_PLL3R          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   RCC_D3CCIPR_LPTIM2SEL_1)
+#define LL_RCC_LPTIM2_CLKSOURCE_LSE            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_1)
+#define LL_RCC_LPTIM2_CLKSOURCE_LSI            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   RCC_D3CCIPR_LPTIM2SEL_2)
+#define LL_RCC_LPTIM2_CLKSOURCE_CLKP           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_2)
+#else
+#define LL_RCC_LPTIM2_CLKSOURCE_PCLK4          LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   0x00000000U)
+#define LL_RCC_LPTIM2_CLKSOURCE_PLL2P          LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   RCC_SRDCCIPR_LPTIM2SEL_0)
+#define LL_RCC_LPTIM2_CLKSOURCE_PLL3R          LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   RCC_SRDCCIPR_LPTIM2SEL_1)
+#define LL_RCC_LPTIM2_CLKSOURCE_LSE            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_1)
+#define LL_RCC_LPTIM2_CLKSOURCE_LSI            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   RCC_SRDCCIPR_LPTIM2SEL_2)
+#define LL_RCC_LPTIM2_CLKSOURCE_CLKP           LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_2)
+#endif /* RCC_D3CCIPR_LPTIM2SEL */
+#if defined(RCC_D3CCIPR_LPTIM345SEL)
+#define LL_RCC_LPTIM345_CLKSOURCE_PCLK4        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, 0x00000000U)
+#define LL_RCC_LPTIM345_CLKSOURCE_PLL2P        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0)
+#define LL_RCC_LPTIM345_CLKSOURCE_PLL3R        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_1)
+#define LL_RCC_LPTIM345_CLKSOURCE_LSE          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1)
+#define LL_RCC_LPTIM345_CLKSOURCE_LSI          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_2)
+#define LL_RCC_LPTIM345_CLKSOURCE_CLKP         LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2)
+#else
+#define LL_RCC_LPTIM345_CLKSOURCE_PCLK4        LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, 0x00000000U)
+#define LL_RCC_LPTIM345_CLKSOURCE_PLL2P        LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0)
+#define LL_RCC_LPTIM345_CLKSOURCE_PLL3R        LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_1)
+#define LL_RCC_LPTIM345_CLKSOURCE_LSE          LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_1)
+#define LL_RCC_LPTIM345_CLKSOURCE_LSI          LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_2)
+#define LL_RCC_LPTIM345_CLKSOURCE_CLKP         LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_2)
+/* aliases*/
+#define LL_RCC_LPTIM3_CLKSOURCE_PCLK4          LL_RCC_LPTIM345_CLKSOURCE_PCLK4
+#define LL_RCC_LPTIM3_CLKSOURCE_PLL2P          LL_RCC_LPTIM345_CLKSOURCE_PLL2P
+#define LL_RCC_LPTIM3_CLKSOURCE_PLL3R          LL_RCC_LPTIM345_CLKSOURCE_PLL3R
+#define LL_RCC_LPTIM3_CLKSOURCE_LSE            LL_RCC_LPTIM345_CLKSOURCE_LSE
+#define LL_RCC_LPTIM3_CLKSOURCE_LSI            LL_RCC_LPTIM345_CLKSOURCE_LSI
+#define LL_RCC_LPTIM3_CLKSOURCE_CLKP           LL_RCC_LPTIM345_CLKSOURCE_CLKP
+#endif /* RCC_D3CCIPR_LPTIM345SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SAIx_CLKSOURCE  Peripheral SAI clock source selection
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_SAI1SEL)
+#define LL_RCC_SAI1_CLKSOURCE_PLL1Q            LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  0x00000000U)
+#define LL_RCC_SAI1_CLKSOURCE_PLL2P            LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  RCC_D2CCIP1R_SAI1SEL_0)
+#define LL_RCC_SAI1_CLKSOURCE_PLL3P            LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  RCC_D2CCIP1R_SAI1SEL_1)
+#define LL_RCC_SAI1_CLKSOURCE_I2S_CKIN         LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  RCC_D2CCIP1R_SAI1SEL_0 | RCC_D2CCIP1R_SAI1SEL_1)
+#define LL_RCC_SAI1_CLKSOURCE_CLKP             LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  RCC_D2CCIP1R_SAI1SEL_2)
+#else
+#define LL_RCC_SAI1_CLKSOURCE_PLL1Q            LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  0x00000000U)
+#define LL_RCC_SAI1_CLKSOURCE_PLL2P            LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  RCC_CDCCIP1R_SAI1SEL_0)
+#define LL_RCC_SAI1_CLKSOURCE_PLL3P            LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  RCC_CDCCIP1R_SAI1SEL_1)
+#define LL_RCC_SAI1_CLKSOURCE_I2S_CKIN         LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  RCC_CDCCIP1R_SAI1SEL_0 | RCC_CDCCIP1R_SAI1SEL_1)
+#define LL_RCC_SAI1_CLKSOURCE_CLKP             LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  RCC_CDCCIP1R_SAI1SEL_2)
+#endif
+#if defined(SAI3)
+#define LL_RCC_SAI23_CLKSOURCE_PLL1Q           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, 0x00000000U)
+#define LL_RCC_SAI23_CLKSOURCE_PLL2P           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_0)
+#define LL_RCC_SAI23_CLKSOURCE_PLL3P           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_1)
+#define LL_RCC_SAI23_CLKSOURCE_I2S_CKIN        LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1)
+#define LL_RCC_SAI23_CLKSOURCE_CLKP            LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_2)
+#endif /* SAI3 */
+#if defined(RCC_CDCCIP1R_SAI2ASEL)
+#define LL_RCC_SAI2A_CLKSOURCE_PLL1Q           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  0x00000000U)
+#define LL_RCC_SAI2A_CLKSOURCE_PLL2P           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  RCC_CDCCIP1R_SAI2ASEL_0)
+#define LL_RCC_SAI2A_CLKSOURCE_PLL3P           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  RCC_CDCCIP1R_SAI2ASEL_1)
+#define LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN        LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_1)
+#define LL_RCC_SAI2A_CLKSOURCE_CLKP            LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  RCC_CDCCIP1R_SAI2ASEL_2)
+#define LL_RCC_SAI2A_CLKSOURCE_SPDIF           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_2)
+#endif /* RCC_CDCCIP1R_SAI2ASEL */
+#if defined(RCC_CDCCIP1R_SAI2BSEL)
+#define LL_RCC_SAI2B_CLKSOURCE_PLL1Q           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  0x00000000U)
+#define LL_RCC_SAI2B_CLKSOURCE_PLL2P           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  RCC_CDCCIP1R_SAI2BSEL_0)
+#define LL_RCC_SAI2B_CLKSOURCE_PLL3P           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  RCC_CDCCIP1R_SAI2BSEL_1)
+#define LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN        LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_1)
+#define LL_RCC_SAI2B_CLKSOURCE_CLKP            LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  RCC_CDCCIP1R_SAI2BSEL_2)
+#define LL_RCC_SAI2B_CLKSOURCE_SPDIF           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_2)
+#endif /* RCC_CDCCIP1R_SAI2BSEL */
+#if defined(SAI4_Block_A)
+#define LL_RCC_SAI4A_CLKSOURCE_PLL1Q           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  0x00000000U)
+#define LL_RCC_SAI4A_CLKSOURCE_PLL2P           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  RCC_D3CCIPR_SAI4ASEL_0)
+#define LL_RCC_SAI4A_CLKSOURCE_PLL3P           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  RCC_D3CCIPR_SAI4ASEL_1)
+#define LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1)
+#define LL_RCC_SAI4A_CLKSOURCE_CLKP            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  RCC_D3CCIPR_SAI4ASEL_2)
+#endif /* SAI4_Block_A */
+#if defined(SAI4_Block_B)
+#define LL_RCC_SAI4B_CLKSOURCE_PLL1Q           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  0x00000000U)
+#define LL_RCC_SAI4B_CLKSOURCE_PLL2P           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  RCC_D3CCIPR_SAI4BSEL_0)
+#define LL_RCC_SAI4B_CLKSOURCE_PLL3P           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  RCC_D3CCIPR_SAI4BSEL_1)
+#define LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1)
+#define LL_RCC_SAI4B_CLKSOURCE_CLKP            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  RCC_D3CCIPR_SAI4BSEL_2)
+#endif /* SAI4_Block_B */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SDMMC_CLKSOURCE  Peripheral SDMMC clock source selection
+  * @{
+  */
+#if defined(RCC_D1CCIPR_SDMMCSEL)
+#define LL_RCC_SDMMC_CLKSOURCE_PLL1Q           (0x00000000U)
+#define LL_RCC_SDMMC_CLKSOURCE_PLL2R           (RCC_D1CCIPR_SDMMCSEL)
+#else
+#define LL_RCC_SDMMC_CLKSOURCE_PLL1Q           (0x00000000U)
+#define LL_RCC_SDMMC_CLKSOURCE_PLL2R           (RCC_CDCCIPR_SDMMCSEL)
+#endif /* RCC_D1CCIPR_SDMMCSEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_RNG_CLKSOURCE  Peripheral RNG clock source selection
+  * @{
+  */
+#if defined(RCC_D2CCIP2R_RNGSEL)
+#define LL_RCC_RNG_CLKSOURCE_HSI48             (0x00000000U)
+#define LL_RCC_RNG_CLKSOURCE_PLL1Q             (RCC_D2CCIP2R_RNGSEL_0)
+#define LL_RCC_RNG_CLKSOURCE_LSE               (RCC_D2CCIP2R_RNGSEL_1)
+#define LL_RCC_RNG_CLKSOURCE_LSI               (RCC_D2CCIP2R_RNGSEL_1 | RCC_D2CCIP2R_RNGSEL_0)
+#else
+#define LL_RCC_RNG_CLKSOURCE_HSI48             (0x00000000U)
+#define LL_RCC_RNG_CLKSOURCE_PLL1Q             (RCC_CDCCIP2R_RNGSEL_0)
+#define LL_RCC_RNG_CLKSOURCE_LSE               (RCC_CDCCIP2R_RNGSEL_1)
+#define LL_RCC_RNG_CLKSOURCE_LSI               (RCC_CDCCIP2R_RNGSEL_1 | RCC_CDCCIP2R_RNGSEL_0)
+#endif /* RCC_D2CCIP2R_RNGSEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_USB_CLKSOURCE  Peripheral USB clock source selection
+  * @{
+  */
+#if defined(RCC_D2CCIP2R_USBSEL)
+#define LL_RCC_USB_CLKSOURCE_DISABLE           (0x00000000U)
+#define LL_RCC_USB_CLKSOURCE_PLL1Q             (RCC_D2CCIP2R_USBSEL_0)
+#define LL_RCC_USB_CLKSOURCE_PLL3Q             (RCC_D2CCIP2R_USBSEL_1)
+#define LL_RCC_USB_CLKSOURCE_HSI48             (RCC_D2CCIP2R_USBSEL_1 | RCC_D2CCIP2R_USBSEL_0)
+#else
+#define LL_RCC_USB_CLKSOURCE_DISABLE           (0x00000000U)
+#define LL_RCC_USB_CLKSOURCE_PLL1Q             (RCC_CDCCIP2R_USBSEL_0)
+#define LL_RCC_USB_CLKSOURCE_PLL3Q             (RCC_CDCCIP2R_USBSEL_1)
+#define LL_RCC_USB_CLKSOURCE_HSI48             (RCC_CDCCIP2R_USBSEL_1 | RCC_CDCCIP2R_USBSEL_0)
+#endif /* RCC_D2CCIP2R_USBSEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_CEC_CLKSOURCE  Peripheral CEC clock source selection
+  * @{
+  */
+#if defined(RCC_D2CCIP2R_CECSEL)
+#define LL_RCC_CEC_CLKSOURCE_LSE               (0x00000000U)
+#define LL_RCC_CEC_CLKSOURCE_LSI               (RCC_D2CCIP2R_CECSEL_0)
+#define LL_RCC_CEC_CLKSOURCE_CSI_DIV122        (RCC_D2CCIP2R_CECSEL_1)
+#else
+#define LL_RCC_CEC_CLKSOURCE_LSE               (0x00000000U)
+#define LL_RCC_CEC_CLKSOURCE_LSI               (RCC_CDCCIP2R_CECSEL_0)
+#define LL_RCC_CEC_CLKSOURCE_CSI_DIV122        (RCC_CDCCIP2R_CECSEL_1)
+#endif
+/**
+  * @}
+  */
+
+#if defined(DSI)
+/** @defgroup RCC_LL_EC_DSI_CLKSOURCE  Peripheral DSI clock source selection
+  * @{
+  */
+#define LL_RCC_DSI_CLKSOURCE_PHY               (0x00000000U)
+#define LL_RCC_DSI_CLKSOURCE_PLL2Q             (RCC_D1CCIPR_DSISEL)
+/**
+  * @}
+  */
+#endif /* DSI */
+
+/** @defgroup RCC_LL_EC_DFSDM_CLKSOURCE  Peripheral DFSDM clock source selection
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_DFSDM1SEL)
+#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2          (0x00000000U)
+#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK         (RCC_D2CCIP1R_DFSDM1SEL)
+#else
+#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2          (0x00000000U)
+#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK         (RCC_CDCCIP1R_DFSDM1SEL)
+#endif /* RCC_D2CCIP1R_DFSDM1SEL */
+/**
+  * @}
+  */
+
+#if defined(DFSDM2_BASE)
+/** @defgroup RCC_LL_EC_DFSDM2_CLKSOURCE  Peripheral DFSDM2 clock source selection
+  * @{
+  */
+#define LL_RCC_DFSDM2_CLKSOURCE_PCLK4          (0x00000000U)
+#define LL_RCC_DFSDM2_CLKSOURCE_SYSCLK         (RCC_SRDCCIPR_DFSDM2SEL)
+/**
+  * @}
+  */
+#endif /* DFSDM2_BASE */
+
+/** @defgroup RCC_LL_EC_FMC_CLKSOURCE  Peripheral FMC clock source selection
+  * @{
+  */
+#if defined(RCC_D1CCIPR_FMCSEL)
+#define LL_RCC_FMC_CLKSOURCE_HCLK              (0x00000000U)
+#define LL_RCC_FMC_CLKSOURCE_PLL1Q             (RCC_D1CCIPR_FMCSEL_0)
+#define LL_RCC_FMC_CLKSOURCE_PLL2R             (RCC_D1CCIPR_FMCSEL_1)
+#define LL_RCC_FMC_CLKSOURCE_CLKP              (RCC_D1CCIPR_FMCSEL_0 | RCC_D1CCIPR_FMCSEL_1)
+#else
+#define LL_RCC_FMC_CLKSOURCE_HCLK              (0x00000000U)
+#define LL_RCC_FMC_CLKSOURCE_PLL1Q             (RCC_CDCCIPR_FMCSEL_0)
+#define LL_RCC_FMC_CLKSOURCE_PLL2R             (RCC_CDCCIPR_FMCSEL_1)
+#define LL_RCC_FMC_CLKSOURCE_CLKP              (RCC_CDCCIPR_FMCSEL_0 | RCC_CDCCIPR_FMCSEL_1)
+#endif /* RCC_D1CCIPR_FMCSEL */
+/**
+  * @}
+  */
+
+#if defined(QUADSPI)
+/** @defgroup RCC_LL_EC_QSPI_CLKSOURCE  Peripheral QSPI clock source selection
+  * @{
+  */
+#define LL_RCC_QSPI_CLKSOURCE_HCLK             (0x00000000U)
+#define LL_RCC_QSPI_CLKSOURCE_PLL1Q            (RCC_D1CCIPR_QSPISEL_0)
+#define LL_RCC_QSPI_CLKSOURCE_PLL2R            (RCC_D1CCIPR_QSPISEL_1)
+#define LL_RCC_QSPI_CLKSOURCE_CLKP             (RCC_D1CCIPR_QSPISEL_0 | RCC_D1CCIPR_QSPISEL_1)
+/**
+  * @}
+  */
+#endif /* QUADSPI */
+
+
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+/** @defgroup RCC_LL_EC_OSPI_CLKSOURCE  Peripheral OSPI clock source selection
+  * @{
+  */
+#define LL_RCC_OSPI_CLKSOURCE_HCLK             (0x00000000U)
+#define LL_RCC_OSPI_CLKSOURCE_PLL1Q            (RCC_CDCCIPR_OCTOSPISEL_0)
+#define LL_RCC_OSPI_CLKSOURCE_PLL2R            (RCC_CDCCIPR_OCTOSPISEL_1)
+#define LL_RCC_OSPI_CLKSOURCE_CLKP             (RCC_CDCCIPR_OCTOSPISEL_0 | RCC_CDCCIPR_OCTOSPISEL_1)
+/**
+  * @}
+  */
+#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
+
+
+/** @defgroup RCC_LL_EC_CLKP_CLKSOURCE  Peripheral CLKP clock source selection
+  * @{
+  */
+#if defined(RCC_D1CCIPR_CKPERSEL)
+#define LL_RCC_CLKP_CLKSOURCE_HSI              (0x00000000U)
+#define LL_RCC_CLKP_CLKSOURCE_CSI              (RCC_D1CCIPR_CKPERSEL_0)
+#define LL_RCC_CLKP_CLKSOURCE_HSE              (RCC_D1CCIPR_CKPERSEL_1)
+#else
+#define LL_RCC_CLKP_CLKSOURCE_HSI              (0x00000000U)
+#define LL_RCC_CLKP_CLKSOURCE_CSI              (RCC_CDCCIPR_CKPERSEL_0)
+#define LL_RCC_CLKP_CLKSOURCE_HSE              (RCC_CDCCIPR_CKPERSEL_1)
+#endif /* RCC_D1CCIPR_CKPERSEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SPIx_CLKSOURCE  Peripheral SPI clock source selection
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_SPI123SEL)
+#define LL_RCC_SPI123_CLKSOURCE_PLL1Q          LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, 0x00000000U)
+#define LL_RCC_SPI123_CLKSOURCE_PLL2P          LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_0)
+#define LL_RCC_SPI123_CLKSOURCE_PLL3P          LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_1)
+#define LL_RCC_SPI123_CLKSOURCE_I2S_CKIN       LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1)
+#define LL_RCC_SPI123_CLKSOURCE_CLKP           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_2)
+#else
+#define LL_RCC_SPI123_CLKSOURCE_PLL1Q          LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, 0x00000000U)
+#define LL_RCC_SPI123_CLKSOURCE_PLL2P          LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_0)
+#define LL_RCC_SPI123_CLKSOURCE_PLL3P          LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_1)
+#define LL_RCC_SPI123_CLKSOURCE_I2S_CKIN       LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_0 | RCC_CDCCIP1R_SPI123SEL_1)
+#define LL_RCC_SPI123_CLKSOURCE_CLKP           LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_2)
+#endif /* RCC_D2CCIP1R_SPI123SEL */
+#if defined(RCC_D2CCIP1R_SPI45SEL)
+#define LL_RCC_SPI45_CLKSOURCE_PCLK2           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  0x00000000U)
+#define LL_RCC_SPI45_CLKSOURCE_PLL2Q           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  RCC_D2CCIP1R_SPI45SEL_0)
+#define LL_RCC_SPI45_CLKSOURCE_PLL3Q           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  RCC_D2CCIP1R_SPI45SEL_1)
+#define LL_RCC_SPI45_CLKSOURCE_HSI             LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_1)
+#define LL_RCC_SPI45_CLKSOURCE_CSI             LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  RCC_D2CCIP1R_SPI45SEL_2)
+#define LL_RCC_SPI45_CLKSOURCE_HSE             LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_2)
+#else
+#define LL_RCC_SPI45_CLKSOURCE_PCLK2           LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  0x00000000U)
+#define LL_RCC_SPI45_CLKSOURCE_PLL2Q           LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  RCC_CDCCIP1R_SPI45SEL_0)
+#define LL_RCC_SPI45_CLKSOURCE_PLL3Q           LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  RCC_CDCCIP1R_SPI45SEL_1)
+#define LL_RCC_SPI45_CLKSOURCE_HSI             LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_1)
+#define LL_RCC_SPI45_CLKSOURCE_CSI             LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  RCC_CDCCIP1R_SPI45SEL_2)
+#define LL_RCC_SPI45_CLKSOURCE_HSE             LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_2)
+#endif /* (RCC_D2CCIP1R_SPI45SEL */
+#if defined(RCC_D3CCIPR_SPI6SEL)
+#define LL_RCC_SPI6_CLKSOURCE_PCLK4            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    0x00000000U)
+#define LL_RCC_SPI6_CLKSOURCE_PLL2Q            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    RCC_D3CCIPR_SPI6SEL_0)
+#define LL_RCC_SPI6_CLKSOURCE_PLL3Q            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    RCC_D3CCIPR_SPI6SEL_1)
+#define LL_RCC_SPI6_CLKSOURCE_HSI              LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_1)
+#define LL_RCC_SPI6_CLKSOURCE_CSI              LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    RCC_D3CCIPR_SPI6SEL_2)
+#define LL_RCC_SPI6_CLKSOURCE_HSE              LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_2)
+#else
+#define LL_RCC_SPI6_CLKSOURCE_PCLK4            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    0x00000000U)
+#define LL_RCC_SPI6_CLKSOURCE_PLL2Q            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_0)
+#define LL_RCC_SPI6_CLKSOURCE_PLL3Q            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_1)
+#define LL_RCC_SPI6_CLKSOURCE_HSI              LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_1)
+#define LL_RCC_SPI6_CLKSOURCE_CSI              LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_2)
+#define LL_RCC_SPI6_CLKSOURCE_HSE              LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_2)
+#define LL_RCC_SPI6_CLKSOURCE_I2S_CKIN         LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_1 | RCC_SRDCCIPR_SPI6SEL_2)
+#endif /* RCC_D3CCIPR_SPI6SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SPDIF_CLKSOURCE  Peripheral SPDIF clock source selection
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_SPDIFSEL)
+#define LL_RCC_SPDIF_CLKSOURCE_PLL1Q           (0x00000000U)
+#define LL_RCC_SPDIF_CLKSOURCE_PLL2R           (RCC_D2CCIP1R_SPDIFSEL_0)
+#define LL_RCC_SPDIF_CLKSOURCE_PLL3R           (RCC_D2CCIP1R_SPDIFSEL_1)
+#define LL_RCC_SPDIF_CLKSOURCE_HSI             (RCC_D2CCIP1R_SPDIFSEL_0 | RCC_D2CCIP1R_SPDIFSEL_1)
+#else
+#define LL_RCC_SPDIF_CLKSOURCE_PLL1Q           (0x00000000U)
+#define LL_RCC_SPDIF_CLKSOURCE_PLL2R           (RCC_CDCCIP1R_SPDIFSEL_0)
+#define LL_RCC_SPDIF_CLKSOURCE_PLL3R           (RCC_CDCCIP1R_SPDIFSEL_1)
+#define LL_RCC_SPDIF_CLKSOURCE_HSI             (RCC_CDCCIP1R_SPDIFSEL_0 | RCC_CDCCIP1R_SPDIFSEL_1)
+#endif /* RCC_D2CCIP1R_SPDIFSEL */
+/**
+  * @}
+  */
+
+#if defined(FDCAN1) || defined(FDCAN2)
+/** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE  Peripheral FDCAN clock source selection
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_FDCANSEL)
+#define LL_RCC_FDCAN_CLKSOURCE_HSE             (0x00000000U)
+#define LL_RCC_FDCAN_CLKSOURCE_PLL1Q           (RCC_D2CCIP1R_FDCANSEL_0)
+#define LL_RCC_FDCAN_CLKSOURCE_PLL2Q           (RCC_D2CCIP1R_FDCANSEL_1)
+#else
+#define LL_RCC_FDCAN_CLKSOURCE_HSE             (0x00000000U)
+#define LL_RCC_FDCAN_CLKSOURCE_PLL1Q           (RCC_CDCCIP1R_FDCANSEL_0)
+#define LL_RCC_FDCAN_CLKSOURCE_PLL2Q           (RCC_CDCCIP1R_FDCANSEL_1)
+#endif /* RCC_D2CCIP1R_FDCANSEL */
+/**
+  * @}
+  */
+#endif /*FDCAN1 || FDCAN2*/
+
+/** @defgroup RCC_LL_EC_SWP_CLKSOURCE  Peripheral SWP clock source selection
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_SWPSEL)
+#define LL_RCC_SWP_CLKSOURCE_PCLK1             (0x00000000U)
+#define LL_RCC_SWP_CLKSOURCE_HSI               (RCC_D2CCIP1R_SWPSEL)
+#else
+#define LL_RCC_SWP_CLKSOURCE_PCLK1             (0x00000000U)
+#define LL_RCC_SWP_CLKSOURCE_HSI               (RCC_CDCCIP1R_SWPSEL)
+#endif /* RCC_D2CCIP1R_SWPSEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_ADC_CLKSOURCE  Peripheral ADC clock source selection
+  * @{
+  */
+#if defined(RCC_D3CCIPR_ADCSEL)
+#define LL_RCC_ADC_CLKSOURCE_PLL2P             (0x00000000U)
+#define LL_RCC_ADC_CLKSOURCE_PLL3R             (RCC_D3CCIPR_ADCSEL_0)
+#define LL_RCC_ADC_CLKSOURCE_CLKP              (RCC_D3CCIPR_ADCSEL_1)
+#else
+#define LL_RCC_ADC_CLKSOURCE_PLL2P             (0x00000000U)
+#define LL_RCC_ADC_CLKSOURCE_PLL3R             (RCC_SRDCCIPR_ADCSEL_0)
+#define LL_RCC_ADC_CLKSOURCE_CLKP              (RCC_SRDCCIPR_ADCSEL_1)
+#endif /* RCC_D3CCIPR_ADCSEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_USARTx_CLKSOURCE  Peripheral USART get clock source
+  * @{
+  */
+#if defined (RCC_D2CCIP2R_USART16SEL)
+#define LL_RCC_USART16_CLKSOURCE         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, 0x00000000U)
+#else
+#define LL_RCC_USART16_CLKSOURCE         LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, 0x00000000U)
+/* alias*/
+#define LL_RCC_USART16910_CLKSOURCE      LL_RCC_USART16_CLKSOURCE
+#endif /* RCC_D2CCIP2R_USART16SEL */
+#if defined (RCC_D2CCIP2R_USART28SEL)
+#define LL_RCC_USART234578_CLKSOURCE     LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, 0x00000000U)
+#else
+#define LL_RCC_USART234578_CLKSOURCE     LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, 0x00000000U)
+#endif /* RCC_D2CCIP2R_USART28SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_LPUARTx_CLKSOURCE  Peripheral LPUART get clock source
+  * @{
+  */
+#if defined(RCC_D3CCIPR_LPUART1SEL)
+#define LL_RCC_LPUART1_CLKSOURCE         RCC_D3CCIPR_LPUART1SEL
+#else
+#define LL_RCC_LPUART1_CLKSOURCE         RCC_SRDCCIPR_LPUART1SEL
+#endif /* RCC_D3CCIPR_LPUART1SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE  Peripheral I2C get clock source
+  * @{
+  */
+#if defined(RCC_D2CCIP2R_I2C123SEL)
+#define LL_RCC_I2C123_CLKSOURCE          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, 0x00000000U)
+#else
+#define LL_RCC_I2C123_CLKSOURCE          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, 0x00000000U)
+#endif /* RCC_D2CCIP2R_I2C123SEL */
+#if defined(RCC_D3CCIPR_I2C4SEL)
+#define LL_RCC_I2C4_CLKSOURCE            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_I2C4SEL,    RCC_D3CCIPR_I2C4SEL_Pos,    0x00000000U)
+#else
+#define LL_RCC_I2C4_CLKSOURCE            LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL,   RCC_SRDCCIPR_I2C4SEL_Pos,   0x00000000U)
+#endif /* RCC_D3CCIPR_I2C4SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_LPTIMx_CLKSOURCE  Peripheral LPTIM get clock source
+  * @{
+  */
+#if defined(RCC_D2CCIP2R_LPTIM1SEL)
+#define LL_RCC_LPTIM1_CLKSOURCE          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,   0x00000000U)
+#else
+#define LL_RCC_LPTIM1_CLKSOURCE          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,   0x00000000U)
+#endif /* RCC_D2CCIP2R_LPTIM1SEL) */
+#if defined(RCC_D3CCIPR_LPTIM2SEL)
+#define LL_RCC_LPTIM2_CLKSOURCE          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,    0x00000000U)
+#else
+#define LL_RCC_LPTIM2_CLKSOURCE          LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL,  RCC_SRDCCIPR_LPTIM2SEL_Pos,   0x00000000U)
+#endif /* RCC_D3CCIPR_LPTIM2SEL */
+#if defined(RCC_D3CCIPR_LPTIM345SEL)
+#define LL_RCC_LPTIM345_CLKSOURCE        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos,  0x00000000U)
+#else
+#define LL_RCC_LPTIM345_CLKSOURCE        LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos,   0x00000000U)
+#define LL_RCC_LPTIM3_CLKSOURCE          LL_RCC_LPTIM345_CLKSOURCE  /* alias */
+#endif /* RCC_D3CCIPR_LPTIM345SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SAIx_CLKSOURCE  Peripheral SAI get clock source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_SAI1SEL)
+#define LL_RCC_SAI1_CLKSOURCE            LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  0x00000000U)
+#else
+#define LL_RCC_SAI1_CLKSOURCE            LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  0x00000000U)
+#endif /* RCC_D2CCIP1R_SAI1SEL */
+#if defined(RCC_D2CCIP1R_SAI23SEL)
+#define LL_RCC_SAI23_CLKSOURCE           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, 0x00000000U)
+#endif /* RCC_D2CCIP1R_SAI23SEL */
+#if defined(RCC_CDCCIP1R_SAI2ASEL)
+#define LL_RCC_SAI2A_CLKSOURCE           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  0x00000000U)
+#endif /* RCC_CDCCIP1R_SAI2ASEL */
+#if defined(RCC_CDCCIP1R_SAI2BSEL)
+#define LL_RCC_SAI2B_CLKSOURCE           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  0x00000000U)
+#endif /*  RCC_CDCCIP1R_SAI2BSEL */
+#if defined(RCC_D3CCIPR_SAI4ASEL)
+#define LL_RCC_SAI4A_CLKSOURCE           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  0x00000000U)
+#endif /* RCC_D3CCIPR_SAI4ASEL */
+#if defined(RCC_D3CCIPR_SAI4BSEL)
+#define LL_RCC_SAI4B_CLKSOURCE           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  0x00000000U)
+#endif /*  RCC_D3CCIPR_SAI4BSEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SDMMC_CLKSOURCE  Peripheral SDMMC get clock source
+  * @{
+  */
+#if defined(RCC_D1CCIPR_SDMMCSEL)
+#define LL_RCC_SDMMC_CLKSOURCE           RCC_D1CCIPR_SDMMCSEL
+#else
+#define LL_RCC_SDMMC_CLKSOURCE           RCC_CDCCIPR_SDMMCSEL
+#endif /* RCC_D1CCIPR_SDMMCSEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_RNG_CLKSOURCE  Peripheral RNG get clock source
+  * @{
+  */
+#if (RCC_D2CCIP2R_RNGSEL)
+#define LL_RCC_RNG_CLKSOURCE             RCC_D2CCIP2R_RNGSEL
+#else
+#define LL_RCC_RNG_CLKSOURCE             RCC_CDCCIP2R_RNGSEL
+#endif /* RCC_D2CCIP2R_RNGSEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_USB_CLKSOURCE  Peripheral USB get clock source
+  * @{
+  */
+#if (RCC_D2CCIP2R_USBSEL)
+#define LL_RCC_USB_CLKSOURCE             RCC_D2CCIP2R_USBSEL
+#else
+#define LL_RCC_USB_CLKSOURCE             RCC_CDCCIP2R_USBSEL
+#endif  /* RCC_D2CCIP2R_USBSEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_CEC_CLKSOURCE  Peripheral CEC get clock source
+  * @{
+  */
+#if (RCC_D2CCIP2R_CECSEL)
+#define LL_RCC_CEC_CLKSOURCE             RCC_D2CCIP2R_CECSEL
+#else
+#define LL_RCC_CEC_CLKSOURCE             RCC_CDCCIP2R_CECSEL
+#endif /* RCC_D2CCIP2R_CECSEL */
+/**
+  * @}
+  */
+
+#if defined(DSI)
+/** @defgroup RCC_LL_EC_DSI_CLKSOURCE  Peripheral DSI get clock source
+  * @{
+  */
+#define LL_RCC_DSI_CLKSOURCE             RCC_D1CCIPR_DSISEL
+/**
+  * @}
+  */
+#endif /* DSI */
+
+/** @defgroup RCC_LL_EC_DFSDM_CLKSOURCE  Peripheral DFSDM get clock source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_DFSDM1SEL)
+#define LL_RCC_DFSDM1_CLKSOURCE          RCC_D2CCIP1R_DFSDM1SEL
+#else
+#define LL_RCC_DFSDM1_CLKSOURCE          RCC_CDCCIP1R_DFSDM1SEL
+#endif /* RCC_D2CCIP1R_DFSDM1SEL */
+/**
+  * @}
+  */
+
+#if defined(DFSDM2_BASE)
+/** @defgroup RCC_LL_EC_DFSDM2_CLKSOURCE  Peripheral DFSDM2 get clock source
+  * @{
+  */
+#define LL_RCC_DFSDM2_CLKSOURCE          RCC_SRDCCIPR_DFSDM2SEL
+/**
+  * @}
+  */
+#endif /* DFSDM2 */
+
+
+/** @defgroup RCC_LL_EC_FMC_CLKSOURCE  Peripheral FMC get clock source
+  * @{
+  */
+#if defined(RCC_D1CCIPR_FMCSEL)
+#define LL_RCC_FMC_CLKSOURCE             RCC_D1CCIPR_FMCSEL
+#else
+#define LL_RCC_FMC_CLKSOURCE             RCC_CDCCIPR_FMCSEL
+#endif
+/**
+  * @}
+  */
+
+#if defined(QUADSPI)
+/** @defgroup RCC_LL_EC_QSPI_CLKSOURCE  Peripheral QSPI get clock source
+  * @{
+  */
+#define LL_RCC_QSPI_CLKSOURCE            RCC_D1CCIPR_QSPISEL
+/**
+  * @}
+  */
+#endif /* QUADSPI */
+
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+/** @defgroup RCC_LL_EC_OSPI_CLKSOURCE  Peripheral OSPI get clock source
+  * @{
+  */
+#define LL_RCC_OSPI_CLKSOURCE            RCC_CDCCIPR_OCTOSPISEL
+/**
+  * @}
+  */
+#endif /* OCTOSPI1 || OCTOSPI2 */
+
+/** @defgroup RCC_LL_EC_CLKP_CLKSOURCE  Peripheral CLKP get clock source
+  * @{
+  */
+#if defined(RCC_D1CCIPR_CKPERSEL)
+#define LL_RCC_CLKP_CLKSOURCE            RCC_D1CCIPR_CKPERSEL
+#else
+#define LL_RCC_CLKP_CLKSOURCE            RCC_CDCCIPR_CKPERSEL
+#endif /* RCC_D1CCIPR_CKPERSEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SPIx_CLKSOURCE  Peripheral SPI get clock source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_SPI123SEL)
+#define LL_RCC_SPI123_CLKSOURCE          LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, 0x00000000U)
+#else
+#define LL_RCC_SPI123_CLKSOURCE          LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, 0x00000000U)
+#endif /* RCC_D2CCIP1R_SPI123SEL */
+#if defined(RCC_D2CCIP1R_SPI45SEL)
+#define LL_RCC_SPI45_CLKSOURCE           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  0x00000000U)
+#else
+#define LL_RCC_SPI45_CLKSOURCE           LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  0x00000000U)
+#endif /* RCC_D2CCIP1R_SPI45SEL */
+#if defined(RCC_D3CCIPR_SPI6SEL)
+#define LL_RCC_SPI6_CLKSOURCE            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    0x00000000U)
+#else
+#define LL_RCC_SPI6_CLKSOURCE            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,   RCC_SRDCCIPR_SPI6SEL_Pos,  0x00000000U)
+#endif /* RCC_D3CCIPR_SPI6SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SPDIF_CLKSOURCE  Peripheral SPDIF get clock source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_SPDIFSEL)
+#define LL_RCC_SPDIF_CLKSOURCE           RCC_D2CCIP1R_SPDIFSEL
+#else
+#define LL_RCC_SPDIF_CLKSOURCE           RCC_CDCCIP1R_SPDIFSEL
+#endif /* RCC_D2CCIP1R_SPDIFSEL */
+/**
+  * @}
+  */
+
+#if defined(FDCAN1) || defined(FDCAN2)
+/** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE  Peripheral FDCAN get clock source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_FDCANSEL)
+#define LL_RCC_FDCAN_CLKSOURCE           RCC_D2CCIP1R_FDCANSEL
+#else
+#define LL_RCC_FDCAN_CLKSOURCE           RCC_CDCCIP1R_FDCANSEL
+#endif
+/**
+  * @}
+  */
+#endif /*FDCAN1 || FDCAN2*/
+
+/** @defgroup RCC_LL_EC_SWP_CLKSOURCE  Peripheral SWP get clock source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_SWPSEL)
+#define LL_RCC_SWP_CLKSOURCE             RCC_D2CCIP1R_SWPSEL
+#else
+#define LL_RCC_SWP_CLKSOURCE             RCC_CDCCIP1R_SWPSEL
+#endif /* RCC_D2CCIP1R_SWPSEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_ADC_CLKSOURCE  Peripheral ADC get clock source
+  * @{
+  */
+#if defined(RCC_D3CCIPR_ADCSEL)
+#define LL_RCC_ADC_CLKSOURCE             RCC_D3CCIPR_ADCSEL
+#else
+#define LL_RCC_ADC_CLKSOURCE             RCC_SRDCCIPR_ADCSEL
+#endif /* RCC_D3CCIPR_ADCSEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_RTC_CLKSOURCE  RTC clock source selection
+  * @{
+  */
+#define LL_RCC_RTC_CLKSOURCE_NONE          (uint32_t)(0x00000000U)
+#define LL_RCC_RTC_CLKSOURCE_LSE           (uint32_t)(RCC_BDCR_RTCSEL_0)
+#define LL_RCC_RTC_CLKSOURCE_LSI           (uint32_t)(RCC_BDCR_RTCSEL_1)
+#define LL_RCC_RTC_CLKSOURCE_HSE           (uint32_t)(RCC_BDCR_RTCSEL_0 | RCC_BDCR_RTCSEL_1)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_TIM_CLKPRESCALER  Timers clocks prescalers selection
+  * @{
+  */
+#define LL_RCC_TIM_PRESCALER_TWICE          (uint32_t)(0x00000000U)
+#define LL_RCC_TIM_PRESCALER_FOUR_TIMES     (uint32_t)(RCC_CFGR_TIMPRE)
+/**
+  * @}
+  */
+
+#if defined(HRTIM1)
+/** @defgroup RCC_LL_EC_HRTIM_CLKSOURCE  High Resolution Timers clock selection
+  * @{
+  */
+#define LL_RCC_HRTIM_CLKSOURCE_TIM          (uint32_t)(0x00000000U)           /* HRTIM Clock source is same as other timers */
+#define LL_RCC_HRTIM_CLKSOURCE_CPU          (uint32_t)(RCC_CFGR_HRTIMSEL)     /* HRTIM Clock source is the CPU clock */
+/**
+  * @}
+  */
+#endif /* HRTIM1 */
+
+/** @defgroup RCC_LL_EC_PLLSOURCE   All PLLs entry clock source
+  * @{
+  */
+#define LL_RCC_PLLSOURCE_HSI               RCC_PLLCKSELR_PLLSRC_HSI
+#define LL_RCC_PLLSOURCE_CSI               RCC_PLLCKSELR_PLLSRC_CSI
+#define LL_RCC_PLLSOURCE_HSE               RCC_PLLCKSELR_PLLSRC_HSE
+#define LL_RCC_PLLSOURCE_NONE              RCC_PLLCKSELR_PLLSRC_NONE
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_PLLINPUTRANGE   All PLLs input range
+  * @{
+  */
+#define LL_RCC_PLLINPUTRANGE_1_2           (uint32_t)(0x00000000U)
+#define LL_RCC_PLLINPUTRANGE_2_4           (uint32_t)(0x00000001)
+#define LL_RCC_PLLINPUTRANGE_4_8           (uint32_t)(0x00000002)
+#define LL_RCC_PLLINPUTRANGE_8_16          (uint32_t)(0x00000003)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_PLLVCORANGE   All PLLs VCO range
+  * @{
+  */
+#define LL_RCC_PLLVCORANGE_WIDE            (uint32_t)(0x00000000U)      /* VCO output range: 192 to 836 MHz   OR  128 to 544 MHz (*) */
+#define LL_RCC_PLLVCORANGE_MEDIUM          (uint32_t)(0x00000001)       /* VCO output range: 150 to 420 MHz */
+/**
+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
+  * @{
+  */
+
+/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in RCC register
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in RCC register
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
+  * @{
+  */
+
+/**
+  * @brief  Helper macro to calculate the SYSCLK frequency
+  * @param  __SYSINPUTCLKFREQ__ Frequency of the input of sys_ck (based on HSE/CSI/HSI/PLL1P)
+  * @param  __SYSPRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SYSCLK_DIV_1
+  *         @arg @ref LL_RCC_SYSCLK_DIV_2
+  *         @arg @ref LL_RCC_SYSCLK_DIV_4
+  *         @arg @ref LL_RCC_SYSCLK_DIV_8
+  *         @arg @ref LL_RCC_SYSCLK_DIV_16
+  *         @arg @ref LL_RCC_SYSCLK_DIV_64
+  *         @arg @ref LL_RCC_SYSCLK_DIV_128
+  *         @arg @ref LL_RCC_SYSCLK_DIV_256
+  *         @arg @ref LL_RCC_SYSCLK_DIV_512
+  * @retval SYSCLK clock frequency (in Hz)
+  */
+#if defined(RCC_D1CFGR_D1CPRE)
+#define LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> ((LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_D1CFGR_D1CPRE) >>  RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU))
+#else
+#define LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> ((LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU))
+#endif /* RCC_D1CFGR_D1CPRE */
+
+/**
+  * @brief  Helper macro to calculate the HCLK frequency
+  * @param  __SYSCLKFREQ__ SYSCLK frequency.
+  * @param  __HPRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_AHB_DIV_1
+  *         @arg @ref LL_RCC_AHB_DIV_2
+  *         @arg @ref LL_RCC_AHB_DIV_4
+  *         @arg @ref LL_RCC_AHB_DIV_8
+  *         @arg @ref LL_RCC_AHB_DIV_16
+  *         @arg @ref LL_RCC_AHB_DIV_64
+  *         @arg @ref LL_RCC_AHB_DIV_128
+  *         @arg @ref LL_RCC_AHB_DIV_256
+  *         @arg @ref LL_RCC_AHB_DIV_512
+  * @retval HCLK clock frequency (in Hz)
+  */
+#if defined(RCC_D1CFGR_HPRE)
+#define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> ((LL_RCC_PrescTable[((__HPRESCALER__) & RCC_D1CFGR_HPRE) >>  RCC_D1CFGR_HPRE_Pos]) & 0x1FU))
+#else
+#define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> ((LL_RCC_PrescTable[((__HPRESCALER__) & RCC_CDCFGR1_HPRE) >>  RCC_CDCFGR1_HPRE_Pos]) & 0x1FU))
+#endif  /* RCC_D1CFGR_HPRE */
+
+/**
+  * @brief  Helper macro to calculate the PCLK1 frequency (ABP1)
+  * @param  __HCLKFREQ__ HCLK frequency
+  * @param  __APB1PRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB1_DIV_1
+  *         @arg @ref LL_RCC_APB1_DIV_2
+  *         @arg @ref LL_RCC_APB1_DIV_4
+  *         @arg @ref LL_RCC_APB1_DIV_8
+  *         @arg @ref LL_RCC_APB1_DIV_16
+  * @retval PCLK1 clock frequency (in Hz)
+  */
+#if defined(RCC_D2CFGR_D2PPRE1)
+#define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_D2CFGR_D2PPRE1) >>  RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU))
+#else
+#define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_CDCFGR2_CDPPRE1) >>  RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU))
+#endif /* RCC_D2CFGR_D2PPRE1 */
+
+/**
+  * @brief  Helper macro to calculate the PCLK2 frequency (ABP2)
+  * @param  __HCLKFREQ__ HCLK frequency
+  * @param  __APB2PRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB2_DIV_1
+  *         @arg @ref LL_RCC_APB2_DIV_2
+  *         @arg @ref LL_RCC_APB2_DIV_4
+  *         @arg @ref LL_RCC_APB2_DIV_8
+  *         @arg @ref LL_RCC_APB2_DIV_16
+  * @retval PCLK2 clock frequency (in Hz)
+  */
+#if defined(RCC_D2CFGR_D2PPRE2)
+#define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_D2CFGR_D2PPRE2) >>  RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU))
+#else
+#define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU))
+#endif /* RCC_D2CFGR_D2PPRE2 */
+
+/**
+  * @brief  Helper macro to calculate the PCLK3 frequency (APB3)
+  * @param  __HCLKFREQ__ HCLK frequency
+  * @param  __APB3PRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB3_DIV_1
+  *         @arg @ref LL_RCC_APB3_DIV_2
+  *         @arg @ref LL_RCC_APB3_DIV_4
+  *         @arg @ref LL_RCC_APB3_DIV_8
+  *         @arg @ref LL_RCC_APB3_DIV_16
+  * @retval PCLK1 clock frequency (in Hz)
+  */
+#if defined(RCC_D1CFGR_D1PPRE)
+#define LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_D1CFGR_D1PPRE) >>  RCC_D1CFGR_D1PPRE_Pos]) & 0x1FU))
+#else
+#define LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_CDCFGR1_CDPPRE) >> RCC_CDCFGR1_CDPPRE_Pos]) & 0x1FU))
+#endif /* RCC_D1CFGR_D1PPRE */
+
+/**
+  * @brief  Helper macro to calculate the PCLK4 frequency (ABP4)
+  * @param  __HCLKFREQ__ HCLK frequency
+  * @param  __APB4PRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB4_DIV_1
+  *         @arg @ref LL_RCC_APB4_DIV_2
+  *         @arg @ref LL_RCC_APB4_DIV_4
+  *         @arg @ref LL_RCC_APB4_DIV_8
+  *         @arg @ref LL_RCC_APB4_DIV_16
+  * @retval PCLK1 clock frequency (in Hz)
+  */
+#if defined(RCC_D3CFGR_D3PPRE)
+#define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_D3CFGR_D3PPRE) >>  RCC_D3CFGR_D3PPRE_Pos]) & 0x1FU))
+#else
+#define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_SRDCFGR_SRDPPRE) >>  RCC_SRDCFGR_SRDPPRE_Pos]) & 0x1FU))
+#endif /* RCC_D3CFGR_D3PPRE */
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
+  * @{
+  */
+#define LL_RCC_PERIPH_FREQUENCY_NO         0x00000000U                 /*!< No clock enabled for the peripheral            */
+#define LL_RCC_PERIPH_FREQUENCY_NA         0xFFFFFFFFU                 /*!< Frequency cannot be provided as external clock */
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
+  * @{
+  */
+
+/** @defgroup RCC_LL_EF_HSE HSE
+  * @{
+  */
+
+/**
+  * @brief  Enable the Clock Security System.
+  * @note Once HSE Clock Security System is enabled it cannot be changed anymore unless
+  *       a reset occurs or system enter in standby mode.
+  * @rmtoll CR           CSSHSEON         LL_RCC_HSE_EnableCSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_CSSHSEON);
+}
+
+/**
+  * @brief  Enable HSE external oscillator (HSE Bypass)
+  * @rmtoll CR           HSEBYP        LL_RCC_HSE_EnableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_HSEBYP);
+}
+
+/**
+  * @brief  Disable HSE external oscillator (HSE Bypass)
+  * @rmtoll CR           HSEBYP        LL_RCC_HSE_DisableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
+}
+
+#if defined(RCC_CR_HSEEXT)
+/**
+  * @brief  Select the Analog HSE external clock type in Bypass mode
+  * @rmtoll CR           HSEEXT        LL_RCC_HSE_SelectAnalogClock
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_SelectAnalogClock(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT);
+}
+
+/**
+  * @brief  Select the Digital HSE external clock type in Bypass mode
+  * @rmtoll CR           HSEEXT        LL_RCC_HSE_SelectDigitalClock
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_SelectDigitalClock(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_HSEEXT);
+}
+#endif /* RCC_CR_HSEEXT */
+
+/**
+  * @brief  Enable HSE crystal oscillator (HSE ON)
+  * @rmtoll CR           HSEON         LL_RCC_HSE_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_HSEON);
+}
+
+/**
+  * @brief  Disable HSE crystal oscillator (HSE ON)
+  * @rmtoll CR           HSEON         LL_RCC_HSE_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
+}
+
+/**
+  * @brief  Check if HSE oscillator Ready
+  * @rmtoll CR           HSERDY        LL_RCC_HSE_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
+{
+  return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY))?1UL:0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_HSI HSI
+  * @{
+  */
+
+/**
+  * @brief  Enable HSI oscillator
+  * @rmtoll CR           HSION         LL_RCC_HSI_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_HSION);
+}
+
+/**
+  * @brief  Disable HSI oscillator
+  * @rmtoll CR           HSION         LL_RCC_HSI_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_HSION);
+}
+
+/**
+  * @brief  Check if HSI clock is ready
+  * @rmtoll CR           HSIRDY        LL_RCC_HSI_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
+{
+  return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if HSI new divider applied and ready
+  * @rmtoll CR           HSIDIVF        LL_RCC_HSI_IsDividerReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI_IsDividerReady(void)
+{
+  return ((READ_BIT(RCC->CR, RCC_CR_HSIDIVF) == (RCC_CR_HSIDIVF))?1UL:0UL);
+}
+
+/**
+  * @brief  Set HSI divider
+  * @rmtoll CR           HSIDIV        LL_RCC_HSI_SetDivider
+  * @param  Divider This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_HSI_DIV1
+  *         @arg @ref LL_RCC_HSI_DIV2
+  *         @arg @ref LL_RCC_HSI_DIV4
+  *         @arg @ref LL_RCC_HSI_DIV8
+  * @retval None.
+  */
+__STATIC_INLINE void LL_RCC_HSI_SetDivider(uint32_t Divider)
+{
+  MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, Divider);
+}
+
+/**
+  * @brief  Get HSI divider
+  * @rmtoll CR           HSIDIV        LL_RCC_HSI_GetDivider
+  * @retval can be one of the following values:
+  *         @arg @ref LL_RCC_HSI_DIV1
+  *         @arg @ref LL_RCC_HSI_DIV2
+  *         @arg @ref LL_RCC_HSI_DIV4
+  *         @arg @ref LL_RCC_HSI_DIV8
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI_GetDivider(void)
+{
+  return (READ_BIT(RCC->CR, RCC_CR_HSIDIV));
+}
+
+/**
+  * @brief  Enable HSI oscillator in Stop mode
+  * @rmtoll CR           HSIKERON         LL_RCC_HSI_EnableStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_EnableStopMode(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_HSIKERON);
+}
+
+/**
+  * @brief  Disable HSI oscillator in Stop mode
+  * @rmtoll CR           HSION         LL_RCC_HSI_DisableStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_DisableStopMode(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
+}
+
+/**
+  * @brief  Get HSI Calibration value
+  * @note When HSITRIM is written, HSICAL is updated with the sum of
+  *       HSITRIM and the factory trim value
+  * @rmtoll HSICFGR        HSICAL        LL_RCC_HSI_GetCalibration
+  * @retval A value between 0 and 4095 (0xFFF)
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
+{
+  return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSICAL) >> RCC_HSICFGR_HSICAL_Pos);
+}
+
+/**
+  * @brief  Set HSI Calibration trimming
+  * @note user-programmable trimming value that is added to the HSICAL
+  * @note Default value is 64 (32 for Cut1.x), which, when added to the HSICAL value,
+  *       should trim the HSI to 64 MHz +/- 1 %
+  * @rmtoll HSICFGR        HSITRIM       LL_RCC_HSI_SetCalibTrimming
+  * @param  Parameter can be a value between 0 and 127 (63 for Cut1.x)
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
+{
+#if defined(RCC_VER_X)
+  if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)
+  {
+    /* STM32H7 Rev.Y */
+    MODIFY_REG(RCC->HSICFGR, 0x3F000U, Value << 12U);
+  }
+  else
+  {
+    /* STM32H7 Rev.V */
+    MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, Value << RCC_HSICFGR_HSITRIM_Pos);
+  }
+#else
+    MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, Value << RCC_HSICFGR_HSITRIM_Pos);
+#endif /* RCC_VER_X */
+}
+
+/**
+  * @brief  Get HSI Calibration trimming
+  * @rmtoll HSICFGR        HSITRIM       LL_RCC_HSI_GetCalibTrimming
+  * @retval A value between 0 and 127 (63 for Cut1.x)
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
+{
+#if defined(RCC_VER_X)
+  if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)
+  {
+    /* STM32H7 Rev.Y */
+    return (uint32_t)(READ_BIT(RCC->HSICFGR, 0x3F000U) >> 12U);
+  }
+  else
+  {
+    /* STM32H7 Rev.V */
+    return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
+  }
+#else
+    return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
+#endif /* RCC_VER_X */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_CSI CSI
+  * @{
+  */
+
+/**
+  * @brief  Enable CSI oscillator
+  * @rmtoll CR           CSION         LL_RCC_CSI_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_CSI_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_CSION);
+}
+
+/**
+  * @brief  Disable CSI oscillator
+  * @rmtoll CR           CSION         LL_RCC_CSI_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_CSI_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_CSION);
+}
+
+/**
+  * @brief  Check if CSI clock is ready
+  * @rmtoll CR           CSIRDY        LL_RCC_CSI_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_CSI_IsReady(void)
+{
+  return ((READ_BIT(RCC->CR, RCC_CR_CSIRDY) == (RCC_CR_CSIRDY))?1UL:0UL);
+}
+
+/**
+  * @brief  Enable CSI oscillator in Stop mode
+  * @rmtoll CR           CSIKERON         LL_RCC_CSI_EnableStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_CSI_EnableStopMode(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_CSIKERON);
+}
+
+/**
+  * @brief  Disable CSI oscillator in Stop mode
+  * @rmtoll CR           CSIKERON         LL_RCC_CSI_DisableStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_CSI_DisableStopMode(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON);
+}
+
+/**
+  * @brief  Get CSI Calibration value
+  * @note When CSITRIM is written, CSICAL is updated with the sum of
+  *       CSITRIM and the factory trim value
+  * @rmtoll CSICFGR        CSICAL        LL_RCC_CSI_GetCalibration
+  * @retval A value between 0 and 255 (0xFF)
+  */
+__STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibration(void)
+{
+#if defined(RCC_VER_X)
+  if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)
+  {
+    /* STM32H7 Rev.Y */
+    return (uint32_t)(READ_BIT(RCC->HSICFGR, 0x3FC0000U) >> 18U);
+  }
+  else
+  {
+    /* STM32H7 Rev.V */
+    return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSICAL) >> RCC_CSICFGR_CSICAL_Pos);
+  }
+#else
+    return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSICAL) >> RCC_CSICFGR_CSICAL_Pos);
+#endif /* RCC_VER_X */
+}
+
+/**
+  * @brief  Set CSI Calibration trimming
+  * @note user-programmable trimming value that is added to the CSICAL
+  * @note Default value is 16, which, when added to the CSICAL value,
+  *       should trim the CSI to 4 MHz +/- 1 %
+  * @rmtoll CSICFGR        CSITRIM       LL_RCC_CSI_SetCalibTrimming
+  * @param  Value can be a value between 0 and 31
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_CSI_SetCalibTrimming(uint32_t Value)
+{
+#if defined(RCC_VER_X)
+  if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)
+  {
+    /* STM32H7 Rev.Y */
+    MODIFY_REG(RCC->HSICFGR, 0x7C000000U, Value << 26U);
+  }
+  else
+  {
+    /* STM32H7 Rev.V */
+    MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, Value << RCC_CSICFGR_CSITRIM_Pos);
+  }
+#else
+    MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, Value << RCC_CSICFGR_CSITRIM_Pos);
+#endif /* RCC_VER_X */
+}
+
+/**
+  * @brief  Get CSI Calibration trimming
+  * @rmtoll CSICFGR        CSITRIM       LL_RCC_CSI_GetCalibTrimming
+  * @retval A value between 0 and 31
+  */
+__STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibTrimming(void)
+{
+#if defined(RCC_VER_X)
+  if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)
+  {
+    /* STM32H7 Rev.Y */
+    return (uint32_t)(READ_BIT(RCC->HSICFGR, 0x7C000000U) >> 26U);
+  }
+  else
+  {
+    /* STM32H7 Rev.V */
+    return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
+  }
+#else
+    return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
+#endif /* RCC_VER_X */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_HSI48 HSI48
+  * @{
+  */
+
+/**
+  * @brief  Enable HSI48 oscillator
+  * @rmtoll CR           HSI48ON         LL_RCC_HSI48_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI48_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_HSI48ON);
+}
+
+/**
+  * @brief  Disable HSI48 oscillator
+  * @rmtoll CR           HSI48ON         LL_RCC_HSI48_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI48_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON);
+}
+
+/**
+  * @brief  Check if HSI48 clock is ready
+  * @rmtoll CR           HSI48RDY        LL_RCC_HSI48_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
+{
+  return ((READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == (RCC_CR_HSI48RDY))?1UL:0UL);
+}
+
+/**
+  * @brief  Get HSI48 Calibration value
+  * @note When HSI48TRIM is written, HSI48CAL is updated with the sum of
+  *       HSI48TRIM and the factory trim value
+  * @rmtoll CRRCR        HSI48CAL        LL_RCC_HSI48_GetCalibration
+  * @retval A value between 0 and 1023 (0x3FF)
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos);
+}
+/**
+  * @}
+  */
+
+#if defined(RCC_CR_D1CKRDY)
+
+/** @defgroup RCC_LL_EF_D1CLK D1CKREADY
+  * @{
+  */
+
+/**
+  * @brief  Check if D1 clock is ready
+  * @rmtoll CR           D1CKRDY        LL_RCC_D1CK_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_D1CK_IsReady(void)
+{
+  return ((READ_BIT(RCC->CR, RCC_CR_D1CKRDY) == (RCC_CR_D1CKRDY))?1UL:0UL);
+}
+
+/**
+  * @}
+  */
+#else
+
+/** @defgroup RCC_LL_EF_CPUCLK CPUCKREADY
+  * @{
+  */
+
+/**
+  * @brief  Check if CPU clock is ready
+  * @rmtoll CR           CPUCKRDY        LL_RCC_CPUCK_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_CPUCK_IsReady(void)
+{
+  return ((READ_BIT(RCC->CR, RCC_CR_CPUCKRDY) == (RCC_CR_CPUCKRDY))?1UL:0UL);
+}
+ /* alias */
+#define LL_RCC_D1CK_IsReady  LL_RCC_CPUCK_IsReady
+/**
+  * @}
+  */
+#endif /* RCC_CR_D1CKRDY */
+
+#if defined(RCC_CR_D2CKRDY)
+
+/** @defgroup RCC_LL_EF_D2CLK D2CKREADY
+  * @{
+  */
+
+/**
+  * @brief  Check if D2 clock is ready
+  * @rmtoll CR           D2CKRDY        LL_RCC_D2CK_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_D2CK_IsReady(void)
+{
+  return ((READ_BIT(RCC->CR, RCC_CR_D2CKRDY) == (RCC_CR_D2CKRDY))?1UL:0UL);
+}
+/**
+  * @}
+  */
+#else
+
+/** @defgroup RCC_LL_EF_CDCLK CDCKREADY
+  * @{
+  */
+
+/**
+  * @brief  Check if CD clock is ready
+  * @rmtoll CR           CDCKRDY        LL_RCC_CDCK_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_CDCK_IsReady(void)
+{
+  return ((READ_BIT(RCC->CR, RCC_CR_CDCKRDY) == (RCC_CR_CDCKRDY))?1UL:0UL);
+}
+#define LL_RCC_D2CK_IsReady LL_RCC_CDCK_IsReady
+/**
+  * @}
+  */
+#endif /* RCC_CR_D2CKRDY */
+
+/** @defgroup RCC_LL_EF_SYSTEM_WIDE_RESET RESET
+  * @{
+  */
+#if defined(RCC_GCR_WW1RSC)
+
+/**
+  * @brief  Enable system wide reset for Window Watch Dog 1
+  * @rmtoll GCR          WW1RSC        LL_RCC_WWDG1_EnableSystemReset
+  * @retval None.
+  */
+__STATIC_INLINE void LL_RCC_WWDG1_EnableSystemReset(void)
+{
+  SET_BIT(RCC->GCR, RCC_GCR_WW1RSC);
+}
+
+/**
+  * @brief  Check if Window Watch Dog 1 reset is system wide
+  * @rmtoll GCR          WW1RSC        LL_RCC_WWDG1_IsSystemReset
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_WWDG1_IsSystemReset(void)
+{
+  return ((READ_BIT(RCC->GCR, RCC_GCR_WW1RSC) == RCC_GCR_WW1RSC)?1UL:0UL);
+}
+#endif  /* RCC_GCR_WW1RSC */
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Enable system wide reset for Window Watch Dog 2
+  * @rmtoll GCR          WW1RSC        LL_RCC_WWDG2_EnableSystemReset
+  * @retval None.
+  */
+__STATIC_INLINE void LL_RCC_WWDG2_EnableSystemReset(void)
+{
+  SET_BIT(RCC->GCR, RCC_GCR_WW2RSC);
+}
+
+/**
+  * @brief  Check if Window Watch Dog 2 reset is system wide
+  * @rmtoll GCR          WW2RSC        LL_RCC_WWDG2_IsSystemReset
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_WWDG2_IsSystemReset(void)
+{
+  return ((READ_BIT(RCC->GCR, RCC_GCR_WW2RSC) == RCC_GCR_WW2RSC)?1UL:0UL);
+}
+#endif  /*DUAL_CORE*/
+/**
+  * @}
+  */
+
+#if defined(DUAL_CORE)
+/** @defgroup RCC_LL_EF_BOOT_CPU CPU
+  * @{
+  */
+
+/**
+  * @brief  Force CM4 boot (if hold by option byte BCM4 = 0)
+  * @rmtoll GCR          BOOT_C2        LL_RCC_ForceCM4Boot
+  * @retval None.
+  */
+__STATIC_INLINE void LL_RCC_ForceCM4Boot(void)
+{
+  SET_BIT(RCC->GCR, RCC_GCR_BOOT_C2);
+}
+
+/**
+  * @brief  Check if CM4 boot is forced
+  * @rmtoll GCR          BOOT_C2        LL_RCC_IsCM4BootForced
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsCM4BootForced(void)
+{
+  return ((READ_BIT(RCC->GCR, RCC_GCR_BOOT_C2) == RCC_GCR_BOOT_C2)?1UL:0UL);
+}
+
+/**
+  * @brief  Force CM7 boot (if hold by option byte BCM7 = 0)
+  * @rmtoll GCR          BOOT_C1        LL_RCC_ForceCM7Boot
+  * @retval None.
+  */
+__STATIC_INLINE void LL_RCC_ForceCM7Boot(void)
+{
+  SET_BIT(RCC->GCR, RCC_GCR_BOOT_C1);
+}
+
+/**
+  * @brief  Check if CM7 boot is forced
+  * @rmtoll GCR          BOOT_C1        LL_RCC_IsCM7BootForced
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsCM7BootForced(void)
+{
+  return ((READ_BIT(RCC->GCR, RCC_GCR_BOOT_C1) == RCC_GCR_BOOT_C1)?1UL:0UL);
+}
+
+/**
+  * @}
+  */
+#endif  /*DUAL_CORE*/
+
+/** @defgroup RCC_LL_EF_LSE LSE
+  * @{
+  */
+
+/**
+  * @brief  Enable the Clock Security System on LSE.
+  * @note Once LSE Clock Security System is enabled it cannot be changed anymore unless
+  *       a clock failure is detected.
+  * @rmtoll BDCR          LSECSSON         LL_RCC_LSE_EnableCSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
+}
+
+/**
+  * @brief  Check if LSE failure is detected by Clock Security System
+  * @rmtoll BDCR         LSECSSD       LL_RCC_LSE_IsFailureDetected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_LSE_IsFailureDetected(void)
+{
+  return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD))?1UL:0UL);
+}
+
+/**
+  * @brief  Enable  Low Speed External (LSE) crystal.
+  * @rmtoll BDCR         LSEON         LL_RCC_LSE_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_Enable(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
+}
+
+/**
+  * @brief  Disable  Low Speed External (LSE) crystal.
+  * @rmtoll BDCR         LSEON         LL_RCC_LSE_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_Disable(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
+}
+
+/**
+  * @brief  Enable external clock source (LSE bypass).
+  * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_EnableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
+}
+
+/**
+  * @brief  Disable external clock source (LSE bypass).
+  * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_DisableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
+}
+
+#if defined(RCC_BDCR_LSEEXT)
+/**
+  * @brief  Enable Low-speed external DIGITAL clock type in Bypass mode (not to be used if RTC is active).
+  * @note   The external clock must be enabled with the LSEON bit, to be used by the device.
+  *         The LSEEXT bit can be written only if the LSE oscillator is disabled.
+  * @rmtoll BDCR         LSEEXT        LL_RCC_LSE_SelectDigitalClock
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_SelectDigitalClock(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);
+}
+
+/**
+  * @brief  Enable Low-speed external ANALOG clock type in Bypass mode (default after Backup domain reset).
+  * @note   The external clock must be enabled with the LSEON bit, to be used by the device.
+  *         The LSEEXT bit can be written only if the LSE oscillator is disabled.
+  * @rmtoll BDCR         LSEEXT        LL_RCC_LSE_SelectAnalogClock
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_SelectAnalogClock(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);
+}
+#endif /* RCC_BDCR_LSEEXT */
+
+/**
+  * @brief  Set LSE oscillator drive capability
+  * @note The oscillator is in Xtal mode when it is not in bypass mode.
+  * @rmtoll BDCR         LSEDRV        LL_RCC_LSE_SetDriveCapability
+  * @param  LSEDrive This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LSEDRIVE_LOW
+  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
+  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
+  *         @arg @ref LL_RCC_LSEDRIVE_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
+{
+  MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
+}
+
+/**
+  * @brief  Get LSE oscillator drive capability
+  * @rmtoll BDCR         LSEDRV        LL_RCC_LSE_GetDriveCapability
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_LSEDRIVE_LOW
+  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
+  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
+  *         @arg @ref LL_RCC_LSEDRIVE_HIGH
+  */
+__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
+{
+  return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
+}
+
+/**
+  * @brief  Check if LSE oscillator Ready
+  * @rmtoll BDCR         LSERDY        LL_RCC_LSE_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
+{
+  return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY))?1UL:0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_LSI LSI
+  * @{
+  */
+
+/**
+  * @brief  Enable LSI Oscillator
+  * @rmtoll CSR          LSION         LL_RCC_LSI_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSI_Enable(void)
+{
+  SET_BIT(RCC->CSR, RCC_CSR_LSION);
+}
+
+/**
+  * @brief  Disable LSI Oscillator
+  * @rmtoll CSR          LSION         LL_RCC_LSI_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSI_Disable(void)
+{
+  CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
+}
+
+/**
+  * @brief  Check if LSI is Ready
+  * @rmtoll CSR          LSIRDY        LL_RCC_LSI_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
+{
+  return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY))?1UL:0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_System System
+  * @{
+  */
+
+/**
+  * @brief  Configure the system clock source
+  * @rmtoll CFGR         SW            LL_RCC_SetSysClkSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_PLL1
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
+}
+
+/**
+  * @brief  Get the system clock source
+  * @rmtoll CFGR         SWS           LL_RCC_GetSysClkSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_CSI
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL1
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
+}
+
+/**
+  * @brief  Configure the system wakeup clock source
+  * @rmtoll CFGR         STOPWUCK       LL_RCC_SetSysWakeUpClkSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_CSI
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSysWakeUpClkSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Source);
+}
+
+/**
+  * @brief  Get the system wakeup clock source
+  * @rmtoll CFGR         STOPWUCK           LL_RCC_GetSysWakeUpClkSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_CSI
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSysWakeUpClkSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK));
+}
+
+/**
+  * @brief  Configure the kernel wakeup clock source
+  * @rmtoll CFGR         STOPKERWUCK       LL_RCC_SetKerWakeUpClkSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_CSI
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetKerWakeUpClkSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, Source);
+}
+
+/**
+  * @brief  Get the kernel wakeup clock source
+  * @rmtoll CFGR         STOPKERWUCK           LL_RCC_GetKerWakeUpClkSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_CSI
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetKerWakeUpClkSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPKERWUCK));
+}
+
+/**
+  * @brief  Set System prescaler
+  * @rmtoll D1CFGR/CDCFGR1        D1CPRE/CDCPRE          LL_RCC_SetSysPrescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SYSCLK_DIV_1
+  *         @arg @ref LL_RCC_SYSCLK_DIV_2
+  *         @arg @ref LL_RCC_SYSCLK_DIV_4
+  *         @arg @ref LL_RCC_SYSCLK_DIV_8
+  *         @arg @ref LL_RCC_SYSCLK_DIV_16
+  *         @arg @ref LL_RCC_SYSCLK_DIV_64
+  *         @arg @ref LL_RCC_SYSCLK_DIV_128
+  *         @arg @ref LL_RCC_SYSCLK_DIV_256
+  *         @arg @ref LL_RCC_SYSCLK_DIV_512
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSysPrescaler(uint32_t Prescaler)
+{
+#if defined(RCC_D1CFGR_D1CPRE)
+  MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, Prescaler);
+#else
+  MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, Prescaler);
+#endif /* RCC_D1CFGR_D1CPRE */
+}
+
+/**
+  * @brief  Set AHB prescaler
+  * @rmtoll D1CFGR/CDCFGR1        HPRE         LL_RCC_SetAHBPrescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_AHB_DIV_1
+  *         @arg @ref LL_RCC_AHB_DIV_2
+  *         @arg @ref LL_RCC_AHB_DIV_4
+  *         @arg @ref LL_RCC_AHB_DIV_8
+  *         @arg @ref LL_RCC_AHB_DIV_16
+  *         @arg @ref LL_RCC_AHB_DIV_64
+  *         @arg @ref LL_RCC_AHB_DIV_128
+  *         @arg @ref LL_RCC_AHB_DIV_256
+  *         @arg @ref LL_RCC_AHB_DIV_512
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
+{
+#if defined(RCC_D1CFGR_HPRE)
+  MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, Prescaler);
+#else
+  MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, Prescaler);
+#endif /* RCC_D1CFGR_HPRE */
+}
+
+/**
+  * @brief  Set APB1 prescaler
+  * @rmtoll D2CFGR/CDCFGR2         D2PPRE1/CDPPRE1         LL_RCC_SetAPB1Prescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB1_DIV_1
+  *         @arg @ref LL_RCC_APB1_DIV_2
+  *         @arg @ref LL_RCC_APB1_DIV_4
+  *         @arg @ref LL_RCC_APB1_DIV_8
+  *         @arg @ref LL_RCC_APB1_DIV_16
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
+{
+#if defined(RCC_D2CFGR_D2PPRE1)
+  MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, Prescaler);
+#else
+  MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, Prescaler);
+#endif /* RCC_D2CFGR_D2PPRE1 */
+}
+
+/**
+  * @brief  Set APB2 prescaler
+  * @rmtoll D2CFGR/CDCFGR2         D2PPRE2/CDPPRE2         LL_RCC_SetAPB2Prescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB2_DIV_1
+  *         @arg @ref LL_RCC_APB2_DIV_2
+  *         @arg @ref LL_RCC_APB2_DIV_4
+  *         @arg @ref LL_RCC_APB2_DIV_8
+  *         @arg @ref LL_RCC_APB2_DIV_16
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
+{
+#if defined(RCC_D2CFGR_D2PPRE2)
+  MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, Prescaler);
+#else
+  MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, Prescaler);
+#endif /* RCC_D2CFGR_D2PPRE2 */
+}
+
+/**
+  * @brief  Set APB3 prescaler
+  * @rmtoll D1CFGR/CDCFGR1         D1PPRE/CDPPRE         LL_RCC_SetAPB3Prescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB3_DIV_1
+  *         @arg @ref LL_RCC_APB3_DIV_2
+  *         @arg @ref LL_RCC_APB3_DIV_4
+  *         @arg @ref LL_RCC_APB3_DIV_8
+  *         @arg @ref LL_RCC_APB3_DIV_16
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetAPB3Prescaler(uint32_t Prescaler)
+{
+#if defined(RCC_D1CFGR_D1PPRE)
+  MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, Prescaler);
+#else
+  MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, Prescaler);
+#endif /* RCC_D1CFGR_D1PPRE */
+}
+
+/**
+  * @brief  Set APB4 prescaler
+  * @rmtoll D3CFGR/SRDCFGR         D3PPRE/SRDPPRE         LL_RCC_SetAPB4Prescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB4_DIV_1
+  *         @arg @ref LL_RCC_APB4_DIV_2
+  *         @arg @ref LL_RCC_APB4_DIV_4
+  *         @arg @ref LL_RCC_APB4_DIV_8
+  *         @arg @ref LL_RCC_APB4_DIV_16
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetAPB4Prescaler(uint32_t Prescaler)
+{
+#if defined(RCC_D3CFGR_D3PPRE)
+  MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, Prescaler);
+#else
+  MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, Prescaler);
+#endif /* RCC_D3CFGR_D3PPRE */
+}
+
+/**
+  * @brief  Get System prescaler
+  * @rmtoll D1CFGR/CDCFGR1        D1CPRE/CDCPRE          LL_RCC_GetSysPrescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SYSCLK_DIV_1
+  *         @arg @ref LL_RCC_SYSCLK_DIV_2
+  *         @arg @ref LL_RCC_SYSCLK_DIV_4
+  *         @arg @ref LL_RCC_SYSCLK_DIV_8
+  *         @arg @ref LL_RCC_SYSCLK_DIV_16
+  *         @arg @ref LL_RCC_SYSCLK_DIV_64
+  *         @arg @ref LL_RCC_SYSCLK_DIV_128
+  *         @arg @ref LL_RCC_SYSCLK_DIV_256
+  *         @arg @ref LL_RCC_SYSCLK_DIV_512
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSysPrescaler(void)
+{
+#if defined(RCC_D1CFGR_D1CPRE)
+  return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_D1CPRE));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE));
+#endif /* RCC_D1CFGR_D1CPRE */
+}
+
+/**
+  * @brief  Get AHB prescaler
+  * @rmtoll D1CFGR/ CDCFGR1       HPRE         LL_RCC_GetAHBPrescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_AHB_DIV_1
+  *         @arg @ref LL_RCC_AHB_DIV_2
+  *         @arg @ref LL_RCC_AHB_DIV_4
+  *         @arg @ref LL_RCC_AHB_DIV_8
+  *         @arg @ref LL_RCC_AHB_DIV_16
+  *         @arg @ref LL_RCC_AHB_DIV_64
+  *         @arg @ref LL_RCC_AHB_DIV_128
+  *         @arg @ref LL_RCC_AHB_DIV_256
+  *         @arg @ref LL_RCC_AHB_DIV_512
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
+{
+#if defined(RCC_D1CFGR_HPRE)
+  return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_HPRE));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCFGR1, RCC_CDCFGR1_HPRE));
+#endif /* RCC_D1CFGR_HPRE */
+}
+
+/**
+  * @brief  Get APB1 prescaler
+  * @rmtoll D2CFGR/CDCFGR2         D2PPRE1/CDPPRE1         LL_RCC_GetAPB1Prescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_APB1_DIV_1
+  *         @arg @ref LL_RCC_APB1_DIV_2
+  *         @arg @ref LL_RCC_APB1_DIV_4
+  *         @arg @ref LL_RCC_APB1_DIV_8
+  *         @arg @ref LL_RCC_APB1_DIV_16
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
+{
+#if defined(RCC_D2CFGR_D2PPRE1)
+  return (uint32_t)(READ_BIT(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1));
+#endif /* RCC_D2CFGR_D2PPRE1 */
+}
+
+/**
+  * @brief  Get APB2 prescaler
+  * @rmtoll D2CFGR/CDCFGR2         D2PPRE2/CDPPRE2         LL_RCC_GetAPB2Prescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_APB2_DIV_1
+  *         @arg @ref LL_RCC_APB2_DIV_2
+  *         @arg @ref LL_RCC_APB2_DIV_4
+  *         @arg @ref LL_RCC_APB2_DIV_8
+  *         @arg @ref LL_RCC_APB2_DIV_16
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
+{
+#if defined(RCC_D2CFGR_D2PPRE2)
+  return (uint32_t)(READ_BIT(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2));
+#endif /* RCC_D2CFGR_D2PPRE2 */
+}
+
+/**
+  * @brief  Get APB3 prescaler
+  * @rmtoll D1CFGR/CDCFGR1         D1PPRE/CDPPRE         LL_RCC_GetAPB3Prescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_APB3_DIV_1
+  *         @arg @ref LL_RCC_APB3_DIV_2
+  *         @arg @ref LL_RCC_APB3_DIV_4
+  *         @arg @ref LL_RCC_APB3_DIV_8
+  *         @arg @ref LL_RCC_APB3_DIV_16
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetAPB3Prescaler(void)
+{
+#if defined(RCC_D1CFGR_D1PPRE)
+  return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_D1PPRE));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE));
+#endif /* RCC_D1CFGR_D1PPRE */
+}
+
+/**
+  * @brief  Get APB4 prescaler
+  * @rmtoll D3CFGR/SRDCFGR         D3PPRE/SRDPPRE         LL_RCC_GetAPB4Prescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_APB4_DIV_1
+  *         @arg @ref LL_RCC_APB4_DIV_2
+  *         @arg @ref LL_RCC_APB4_DIV_4
+  *         @arg @ref LL_RCC_APB4_DIV_8
+  *         @arg @ref LL_RCC_APB4_DIV_16
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetAPB4Prescaler(void)
+{
+#if defined(RCC_D3CFGR_D3PPRE)
+  return (uint32_t)(READ_BIT(RCC->D3CFGR, RCC_D3CFGR_D3PPRE));
+#else
+  return (uint32_t)(READ_BIT(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE));
+#endif /* RCC_D3CFGR_D3PPRE */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_MCO MCO
+  * @{
+  */
+
+/**
+  * @brief  Configure MCOx
+  * @rmtoll CFGR         MCO1          LL_RCC_ConfigMCO\n
+  *         CFGR         MCO1PRE       LL_RCC_ConfigMCO\n
+  *         CFGR         MCO2          LL_RCC_ConfigMCO\n
+  *         CFGR         MCO2PRE       LL_RCC_ConfigMCO
+  * @param  MCOxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_MCO1SOURCE_HSI
+  *         @arg @ref LL_RCC_MCO1SOURCE_LSE
+  *         @arg @ref LL_RCC_MCO1SOURCE_HSE
+  *         @arg @ref LL_RCC_MCO1SOURCE_PLL1QCLK
+  *         @arg @ref LL_RCC_MCO1SOURCE_HSI48
+  *         @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
+  *         @arg @ref LL_RCC_MCO2SOURCE_PLL2PCLK
+  *         @arg @ref LL_RCC_MCO2SOURCE_HSE
+  *         @arg @ref LL_RCC_MCO2SOURCE_PLL1PCLK
+  *         @arg @ref LL_RCC_MCO2SOURCE_CSI
+  *         @arg @ref LL_RCC_MCO2SOURCE_LSI
+  * @param  MCOxPrescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_MCO1_DIV_1
+  *         @arg @ref LL_RCC_MCO1_DIV_2
+  *         @arg @ref LL_RCC_MCO1_DIV_3
+  *         @arg @ref LL_RCC_MCO1_DIV_4
+  *         @arg @ref LL_RCC_MCO1_DIV_5
+  *         @arg @ref LL_RCC_MCO1_DIV_6
+  *         @arg @ref LL_RCC_MCO1_DIV_7
+  *         @arg @ref LL_RCC_MCO1_DIV_8
+  *         @arg @ref LL_RCC_MCO1_DIV_9
+  *         @arg @ref LL_RCC_MCO1_DIV_10
+  *         @arg @ref LL_RCC_MCO1_DIV_11
+  *         @arg @ref LL_RCC_MCO1_DIV_12
+  *         @arg @ref LL_RCC_MCO1_DIV_13
+  *         @arg @ref LL_RCC_MCO1_DIV_14
+  *         @arg @ref LL_RCC_MCO1_DIV_15
+  *         @arg @ref LL_RCC_MCO2_DIV_1
+  *         @arg @ref LL_RCC_MCO2_DIV_2
+  *         @arg @ref LL_RCC_MCO2_DIV_3
+  *         @arg @ref LL_RCC_MCO2_DIV_4
+  *         @arg @ref LL_RCC_MCO2_DIV_5
+  *         @arg @ref LL_RCC_MCO2_DIV_6
+  *         @arg @ref LL_RCC_MCO2_DIV_7
+  *         @arg @ref LL_RCC_MCO2_DIV_8
+  *         @arg @ref LL_RCC_MCO2_DIV_9
+  *         @arg @ref LL_RCC_MCO2_DIV_10
+  *         @arg @ref LL_RCC_MCO2_DIV_11
+  *         @arg @ref LL_RCC_MCO2_DIV_12
+  *         @arg @ref LL_RCC_MCO2_DIV_13
+  *         @arg @ref LL_RCC_MCO2_DIV_14
+  *         @arg @ref LL_RCC_MCO2_DIV_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
+{
+  MODIFY_REG(RCC->CFGR,  (MCOxSource << 16U) | (MCOxPrescaler << 16U), (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
+  * @{
+  */
+
+/**
+  * @brief  Configure periph clock source
+  * @rmtoll D2CCIP1R/CDCCIP1R        *     LL_RCC_SetClockSource\n
+  *         D2CCIP2R/CDCCIP2R        *     LL_RCC_SetClockSource\n
+  *         D3CCIPR/SRDCCIPR         *     LL_RCC_SetClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P  (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P  (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN  (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q  (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P  (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P  (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN  (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP  (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_SPDIF  (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q  (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF  (*)
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetClockSource(uint32_t ClkSource)
+{
+#if defined(RCC_D1CCIPR_FMCSEL)
+  register uint32_t * pReg = (uint32_t *)((uint32_t)&RCC->D1CCIPR + LL_CLKSOURCE_REG(ClkSource));
+#else
+  register uint32_t * pReg = (uint32_t *)((uint32_t)&RCC->CDCCIPR + LL_CLKSOURCE_REG(ClkSource));
+#endif /*  */
+  MODIFY_REG(*pReg, LL_CLKSOURCE_MASK(ClkSource), LL_CLKSOURCE_CONFIG(ClkSource));
+}
+
+/**
+  * @brief  Configure USARTx clock source
+  * @rmtoll D2CCIP2R / D2CCIP2R        USART16SEL     LL_RCC_SetUSARTClockSource\n
+  *         D2CCIP2R / D2CCIP2R        USART28SEL     LL_RCC_SetUSARTClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t ClkSource)
+{
+  LL_RCC_SetClockSource(ClkSource);
+}
+
+/**
+  * @brief  Configure LPUARTx clock source
+  * @rmtoll D3CCIPR / SRDCCIPR        LPUART1SEL     LL_RCC_SetLPUARTClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t ClkSource)
+{
+#if defined(RCC_D3CCIPR_LPUART1SEL)
+  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, ClkSource);
+#else
+  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL, ClkSource);
+#endif /* RCC_D3CCIPR_LPUART1SEL */
+}
+
+/**
+  * @brief  Configure I2Cx clock source
+  * @rmtoll D2CCIP2R / CDCCIP2R       I2C123SEL       LL_RCC_SetI2CClockSource\n
+  *         D3CCIPR / SRDCCIPR        I2C4SEL         LL_RCC_SetI2CClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t ClkSource)
+{
+  LL_RCC_SetClockSource(ClkSource);
+}
+
+/**
+  * @brief  Configure LPTIMx clock source
+  * @rmtoll D2CCIP2R / CDCCIP2R      LPTIM1SEL     LL_RCC_SetLPTIMClockSource
+  *         D3CCIPR  / SRDCCIPR      LPTIM2SEL     LL_RCC_SetLPTIMClockSource\n
+  *         D3CCIPR  / SRDCCIPR      LPTIM345SEL   LL_RCC_SetLPTIMClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t ClkSource)
+{
+  LL_RCC_SetClockSource(ClkSource);
+}
+
+/**
+  * @brief  Configure SAIx clock source
+  * @rmtoll D2CCIP1R / CDCCIP1R       SAI1SEL       LL_RCC_SetSAIClockSource\n
+  *         D2CCIP1R / CDCCIP1R       SAI23SEL      LL_RCC_SetSAIClockSource
+  *         D3CCIPR  / SRDCCIPR       SAI4ASEL      LL_RCC_SetSAI4xClockSource\n
+  *         D3CCIPR  / SRDCCIPR       SAI4BSEL      LL_RCC_SetSAI4xClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P  (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P  (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN  (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q  (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P  (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P  (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN  (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP  (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_SPDIF  (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q  (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF  (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t ClkSource)
+{
+  LL_RCC_SetClockSource(ClkSource);
+}
+
+/**
+  * @brief  Configure SDMMCx clock source
+  * @rmtoll D1CCIPR / CDCCIPR       SDMMCSEL      LL_RCC_SetSDMMCClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL2R
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t ClkSource)
+{
+#if defined(RCC_D1CCIPR_SDMMCSEL)
+  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, ClkSource);
+#else
+  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL, ClkSource);
+#endif /* RCC_D1CCIPR_SDMMCSEL */
+}
+
+/**
+  * @brief  Configure RNGx clock source
+  * @rmtoll D2CCIP2R / CDCCIP2R       RNGSEL      LL_RCC_SetRNGClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_LSI
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t ClkSource)
+{
+#if defined(RCC_D2CCIP2R_RNGSEL)
+  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, ClkSource);
+#else
+  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL, ClkSource);
+#endif /* RCC_D2CCIP2R_RNGSEL */
+}
+
+/**
+  * @brief  Configure USBx clock source
+  * @rmtoll D2CCIP2R / CDCCIP2R      USBSEL      LL_RCC_SetUSBClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_DISABLE
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t ClkSource)
+{
+#if defined(RCC_D2CCIP2R_USBSEL)
+  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, ClkSource);
+#else
+  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL, ClkSource);
+#endif /* RCC_D2CCIP2R_USBSEL */
+}
+
+/**
+  * @brief  Configure CECx clock source
+  * @rmtoll D2CCIP2R / CDCCIP2R         CECSEL        LL_RCC_SetCECClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_CEC_CLKSOURCE_CSI_DIV122
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t ClkSource)
+{
+#if defined(RCC_D2CCIP2R_CECSEL)
+  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, ClkSource);
+#else
+  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL, ClkSource);
+#endif /* RCC_D2CCIP2R_CECSEL */
+}
+
+#if defined(DSI)
+/**
+  * @brief  Configure DSIx clock source
+  * @rmtoll D1CCIPR         DSISEL        LL_RCC_SetDSIClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
+  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PLL2Q
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t ClkSource)
+{
+  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL, ClkSource);
+}
+#endif /* DSI */
+
+/**
+  * @brief  Configure DFSDMx Kernel clock source
+  * @rmtoll D2CCIP1R / CDCCIP1R         DFSDM1SEL        LL_RCC_SetDFSDMClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t ClkSource)
+{
+#if defined(RCC_D2CCIP1R_DFSDM1SEL)
+  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, ClkSource);
+#else
+  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, ClkSource);
+#endif /* RCC_D2CCIP1R_DFSDM1SEL */
+}
+
+#if defined(DFSDM2_BASE)
+/**
+  * @brief  Configure DFSDMx Kernel clock source
+  * @rmtoll SRDCCIPR                   DFSDM2SEL        LL_RCC_SetDFSDM2ClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetDFSDM2ClockSource(uint32_t ClkSource)
+{
+   MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL, ClkSource);
+}
+#endif /* DFSDM2 */
+
+/**
+  * @brief  Configure FMCx Kernel clock source
+  * @rmtoll D1CCIPR / CDCCIPR        FMCSEL        LL_RCC_SetFMCClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_FMC_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_FMC_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_FMC_CLKSOURCE_PLL2R
+  *         @arg @ref LL_RCC_FMC_CLKSOURCE_CLKP
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetFMCClockSource(uint32_t ClkSource)
+{
+#if defined(RCC_D1CCIPR_FMCSEL)
+  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, ClkSource);
+#else
+  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL, ClkSource);
+#endif /* RCC_D1CCIPR_FMCSEL */
+}
+
+#if defined(QUADSPI)
+/**
+  * @brief  Configure QSPIx Kernel clock source
+  * @rmtoll D1CCIPR         QSPISEL        LL_RCC_SetQSPIClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_QSPI_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL2R
+  *         @arg @ref LL_RCC_QSPI_CLKSOURCE_CLKP
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetQSPIClockSource(uint32_t ClkSource)
+{
+  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL, ClkSource);
+}
+#endif /* QUADSPI */
+
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+/**
+  * @brief  Configure OSPIx Kernel clock source
+  * @rmtoll D1CCIPR         OPISEL        LL_RCC_SetOSPIClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_OSPI_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL2R
+  *         @arg @ref LL_RCC_OSPI_CLKSOURCE_CLKP
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetOSPIClockSource(uint32_t ClkSource)
+{
+  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL, ClkSource);
+}
+#endif /* OCTOSPI1 || OCTOSPI2 */
+
+/**
+  * @brief  Configure CLKP Kernel clock source
+  * @rmtoll D1CCIPR / CDCCIPR         CKPERSEL        LL_RCC_SetCLKPClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetCLKPClockSource(uint32_t ClkSource)
+{
+#if defined(RCC_D1CCIPR_CKPERSEL)
+  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, ClkSource);
+#else
+  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL, ClkSource);
+#endif /* RCC_D1CCIPR_CKPERSEL */
+}
+
+/**
+  * @brief  Configure SPIx Kernel clock source
+  * @rmtoll D2CCIP1R / CDCCIP1R       SPI123SEL        LL_RCC_SetSPIClockSource\n
+  *         D2CCIP1R / CDCCIP1R       SPI45SEL         LL_RCC_SetSPIClockSource\n
+  *         D3CCIPR  / SRDCCIPR       SPI6SEL          LL_RCC_SetSPIClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSPIClockSource(uint32_t ClkSource)
+{
+  LL_RCC_SetClockSource(ClkSource);
+}
+
+/**
+  * @brief  Configure SPDIFx Kernel clock source
+  * @rmtoll D2CCIP1R / CDCCIP1R       SPDIFSEL        LL_RCC_SetSPDIFClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL2R
+  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_HSI
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSPDIFClockSource(uint32_t ClkSource)
+{
+#if defined(RCC_D2CCIP1R_SPDIFSEL)
+  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, ClkSource);
+#else
+  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL, ClkSource);
+#endif /* RCC_D2CCIP1R_SPDIFSEL */
+}
+
+/**
+  * @brief  Configure FDCANx Kernel clock source
+  * @rmtoll D2CCIP1R / CDCCIP1R      FDCANSEL        LL_RCC_SetFDCANClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2Q
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t ClkSource)
+{
+#if defined(RCC_D2CCIP1R_FDCANSEL)
+  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, ClkSource);
+#else
+  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL, ClkSource);
+#endif /* RCC_D2CCIP1R_FDCANSEL */
+}
+
+/**
+  * @brief  Configure SWPx Kernel clock source
+  * @rmtoll D2CCIP1R /  CDCCIP1R       SWPSEL        LL_RCC_SetSWPClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SWP_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_SWP_CLKSOURCE_HSI
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSWPClockSource(uint32_t ClkSource)
+{
+#if defined(RCC_D2CCIP1R_SWPSEL)
+  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, ClkSource);
+#else
+  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL, ClkSource);
+#endif /* RCC_D2CCIP1R_SWPSEL */
+}
+
+/**
+  * @brief  Configure ADCx Kernel clock source
+  * @rmtoll D3CCIPR / SRDCCIPR        ADCSEL        LL_RCC_SetADCClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_CLKP
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ClkSource)
+{
+#if defined(RCC_D3CCIPR_ADCSEL)
+  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, ClkSource);
+#else
+  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL, ClkSource);
+#endif /* RCC_D3CCIPR_ADCSEL */
+}
+
+/**
+  * @brief  Get periph clock source
+  * @rmtoll D1CCIPR  / CDCCIPR       *     LL_RCC_GetClockSource\n
+  *         D2CCIP1R / CDCCIP1R      *     LL_RCC_GetClockSource\n
+  *         D2CCIP2R / CDCCIP2R      *     LL_RCC_GetClockSource\n
+  *         D3CCIPR  / SRDCCIPR      *     LL_RCC_GetClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE (*)
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE (*)
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE (*)
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE (*)
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*)
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*)
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*)
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*)
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_CLKP (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*)
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetClockSource(uint32_t Periph)
+{
+#if defined(RCC_D1CCIPR_FMCSEL)
+  register const uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->D1CCIPR) + LL_CLKSOURCE_REG(Periph)));
+#else
+  register const uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->CDCCIPR) + LL_CLKSOURCE_REG(Periph)));
+#endif /* RCC_D1CCIPR_FMCSEL */
+  return (uint32_t) (Periph | (((READ_BIT(*pReg, LL_CLKSOURCE_MASK(Periph))) >> LL_CLKSOURCE_SHIFT(Periph)) << LL_RCC_CONFIG_SHIFT) );
+}
+
+/**
+  * @brief  Get USARTx clock source
+  * @rmtoll D2CCIP2R / CDCCIP2R      USART16SEL     LL_RCC_GetUSARTClockSource\n
+  *         D2CCIP2R / CDCCIP2R      USART28SEL     LL_RCC_GetUSARTClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t Periph)
+{
+  return LL_RCC_GetClockSource(Periph);
+}
+
+/**
+  * @brief  Get LPUART clock source
+  * @rmtoll D3CCIPR / SRDCCIPR       LPUART1SEL     LL_RCC_GetLPUARTClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+#if defined(RCC_D3CCIPR_LPUART1SEL)
+  return (uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL));
+#else
+  return (uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL));
+#endif  /* RCC_D3CCIPR_LPUART1SEL */
+}
+
+/**
+  * @brief  Get I2Cx clock source
+  * @rmtoll D2CCIP2R / CDCCIP2R     I2C123SEL       LL_RCC_GetI2CClockSource\n
+  *         D3CCIPR  / SRDCCIPR     I2C4SEL         LL_RCC_GetI2CClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t Periph)
+{
+  return LL_RCC_GetClockSource(Periph);
+}
+
+/**
+  * @brief  Get LPTIM clock source
+  * @rmtoll D2CCIP2R / CDCCIP2R      LPTIM1SEL     LL_RCC_GetLPTIMClockSource\n
+  *         D3CCIPR  / SRDCCIPR      LPTIM2SEL     LL_RCC_GetLPTIMClockSource\n
+  *         D3CCIPR  / SRDCCIPR      LPTIM345SEL   LL_RCC_GetLPTIMClockSource
+  * @param  Perihp This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t Periph)
+{
+  return LL_RCC_GetClockSource(Periph);
+}
+
+/**
+  * @brief  Get SAIx clock source
+  * @rmtoll D2CCIP1R / CDCCIP1R     SAI1SEL       LL_RCC_GetSAIClockSource\n
+  *         D2CCIP1R / CDCCIP1R     SAI23SEL      LL_RCC_GetSAIClockSource
+  *         D3CCIPR  / SRDCCIPR     SAI4ASEL      LL_RCC_GetSAIClockSource\n
+  *         D3CCIPR  / SRDCCIPR     SAI4BSEL      LL_RCC_GetSAIClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*)
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*)
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*)
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*)
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_SPDIF (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_CLKP (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*)
+  * 
+  *  (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t Periph)
+{
+  return LL_RCC_GetClockSource(Periph);
+}
+
+/**
+  * @brief  Get SDMMC clock source
+  * @rmtoll D1CCIPR / CDCCIPR      SDMMCSEL      LL_RCC_GetSDMMCClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SDMMC_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL2R
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+#if defined(RCC_D1CCIPR_SDMMCSEL)
+  return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL));
+#endif /* RCC_D1CCIPR_SDMMCSEL */
+}
+
+/**
+  * @brief  Get RNG clock source
+  * @rmtoll D2CCIP2R        RNGSEL      LL_RCC_GetRNGClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_LSI
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+#if defined(RCC_D2CCIP2R_RNGSEL)
+  return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL));
+#endif /* RCC_D2CCIP2R_RNGSEL */
+}
+
+/**
+  * @brief  Get USB clock source
+  * @rmtoll D2CCIP2R / CDCCIP2R      USBSEL      LL_RCC_GetUSBClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USB_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_DISABLE
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+#if defined(RCC_D2CCIP2R_USBSEL)
+  return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL));
+#endif /* RCC_D2CCIP2R_USBSEL */
+}
+
+/**
+  * @brief  Get CEC clock source
+  * @rmtoll D2CCIP2R / CDCCIP2R        CECSEL        LL_RCC_GetCECClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_CEC_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_CEC_CLKSOURCE_CSI_DIV122
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+#if defined(RCC_D2CCIP2R_CECSEL)
+  return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL));
+#endif  /* RCC_D2CCIP2R_CECSEL */
+}
+
+#if defined(DSI)
+/**
+  * @brief  Get DSI clock source
+  * @rmtoll D1CCIPR         DSISEL        LL_RCC_GetDSIClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DSI_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
+  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PLL2Q
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+  return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL));
+}
+#endif /* DSI */
+
+/**
+  * @brief  Get DFSDM Kernel clock source
+  * @rmtoll D2CCIP1R / CDCCIP1R         DFSDM1SEL        LL_RCC_GetDFSDMClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+#if defined(RCC_D2CCIP1R_DFSDM1SEL)
+  return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL));
+#endif /* RCC_D2CCIP1R_DFSDM1SEL */
+}
+
+#if defined(DFSDM2_BASE)
+/**
+  * @brief  Get DFSDM2 Kernel clock source
+  * @rmtoll SRDCCIPR         DFSDM2SEL        LL_RCC_GetDFSDM2ClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetDFSDM2ClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+  return (uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL));
+}
+#endif /* DFSDM2_BASE */
+
+/**
+  * @brief  Get FMC Kernel clock source
+  * @rmtoll D1CCIPR / D1CCIPR         FMCSEL        LL_RCC_GetFMCClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_FMC_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_FMC_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_FMC_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_FMC_CLKSOURCE_PLL2R
+  *         @arg @ref LL_RCC_FMC_CLKSOURCE_CLKP
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetFMCClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+#if defined(RCC_D1CCIPR_FMCSEL)
+  return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL));
+#endif /* RCC_D1CCIPR_FMCSEL */
+}
+
+#if defined(QUADSPI)
+/**
+  * @brief  Get QSPI Kernel clock source
+  * @rmtoll D1CCIPR / CDCCIPR      QSPISEL        LL_RCC_GetQSPIClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_QSPI_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_QSPI_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL2R
+  *         @arg @ref LL_RCC_QSPI_CLKSOURCE_CLKP
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetQSPIClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+  return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL));
+}
+#endif /* QUADSPI */
+
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+/**
+  * @brief  Get OSPI Kernel clock source
+  * @rmtoll CDCCIPR      OSPISEL        LL_RCC_GetOSPIClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_OSPI_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_OSPI_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL2R
+  *         @arg @ref LL_RCC_OSPI_CLKSOURCE_CLKP
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetOSPIClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+  return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL));
+}
+#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
+
+/**
+  * @brief  Get CLKP Kernel clock source
+  * @rmtoll D1CCIPR / CDCCIPR       CKPERSEL        LL_RCC_GetCLKPClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetCLKPClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+#if defined(RCC_D1CCIPR_CKPERSEL)
+  return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL));
+#endif /* RCC_D1CCIPR_CKPERSEL */
+}
+
+/**
+  * @brief  Get SPIx Kernel clock source
+  * @rmtoll D2CCIP1R / CDCCIP1R     SPI123SEL       LL_RCC_GetSPIClockSource\n
+  *         D2CCIP1R / CDCCIP1R     SPI45SEL        LL_RCC_GetSPIClockSource\n
+  *         D3CCIPR  / SRDCCIPR     SPI6SEL         LL_RCC_GetSPIClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*)
+  *
+  *         (*) value not defined in all stm32h7xx lines.
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSPIClockSource(uint32_t Periph)
+{
+  return LL_RCC_GetClockSource(Periph);
+}
+
+/**
+  * @brief  Get SPDIF Kernel clock source
+  * @rmtoll D2CCIP1R / CDCCIP1R      SPDIFSEL        LL_RCC_GetSPDIFClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL2R
+  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_HSI
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSPDIFClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+#if defined(RCC_D2CCIP1R_SPDIFSEL)
+  return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL));
+#endif /* RCC_D2CCIP1R_SPDIFSEL */
+}
+
+/**
+  * @brief  Get FDCAN Kernel clock source
+  * @rmtoll D2CCIP1R / CDCCIP1R       FDCANSEL        LL_RCC_GetFDCANClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2Q
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+#if defined(RCC_D2CCIP1R_FDCANSEL)
+  return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL));
+#endif /* RCC_D2CCIP1R_FDCANSEL */
+}
+
+/**
+  * @brief  Get SWP Kernel clock source
+  * @rmtoll D2CCIP1R / CDCCIP1R       SWPSEL        LL_RCC_GetSWPClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SWP_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SWP_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_SWP_CLKSOURCE_HSI
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSWPClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+#if defined(RCC_D2CCIP1R_SWPSEL)
+  return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL));
+#endif /* RCC_D2CCIP1R_SWPSEL */
+}
+
+/**
+  * @brief  Get ADC Kernel clock source
+  * @rmtoll D3CCIPR / SRDCCIPR       ADCSEL        LL_RCC_GetADCClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_CLKP
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+#if defined (RCC_D3CCIPR_ADCSEL)
+  return (uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL));
+#else
+  return (uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL));
+#endif /* RCC_D3CCIPR_ADCSEL */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_RTC RTC
+  * @{
+  */
+
+/**
+  * @brief  Set RTC Clock Source
+  * @note   Once the RTC clock source has been selected, it cannot be changed anymore unless
+  *         the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
+  *         set). The BDRST bit can be used to reset them.
+  * @rmtoll BDCR         RTCSEL        LL_RCC_SetRTCClockSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
+}
+
+/**
+  * @brief  Get RTC Clock Source
+  * @rmtoll BDCR         RTCSEL        LL_RCC_GetRTCClockSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
+}
+
+/**
+  * @brief  Enable RTC
+  * @rmtoll BDCR         RTCEN         LL_RCC_EnableRTC
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableRTC(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
+}
+
+/**
+  * @brief  Disable RTC
+  * @rmtoll BDCR         RTCEN         LL_RCC_DisableRTC
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableRTC(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
+}
+
+/**
+  * @brief  Check if RTC has been enabled or not
+  * @rmtoll BDCR         RTCEN         LL_RCC_IsEnabledRTC
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
+{
+  return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN))?1UL:0UL);
+}
+
+/**
+  * @brief  Force the Backup domain reset
+  * @rmtoll BDCR         BDRST / VSWRST         LL_RCC_ForceBackupDomainReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
+}
+
+/**
+  * @brief  Release the Backup domain reset
+  * @rmtoll BDCR         BDRST / VSWRST          LL_RCC_ReleaseBackupDomainReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
+{
+#if defined(RCC_BDCR_BDRST)
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
+#else
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_VSWRST);
+#endif /* RCC_BDCR_BDRST */
+}
+
+/**
+  * @brief  Set HSE Prescalers for RTC Clock
+  * @rmtoll CFGR         RTCPRE        LL_RCC_SetRTC_HSEPrescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_RTC_NOCLOCK
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_2
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_3
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_4
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_5
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_6
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_7
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_8
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_9
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_10
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_11
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_12
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_13
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_14
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_15
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_16
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_17
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_18
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_19
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_20
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_21
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_22
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_23
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_24
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_25
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_26
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_27
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_28
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_29
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_30
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_31
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_32
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_33
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_34
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_35
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_36
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_37
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_38
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_39
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_40
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_41
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_42
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_43
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_44
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_45
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_46
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_47
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_48
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_49
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_50
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_51
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_52
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_53
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_54
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_55
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_56
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_57
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_58
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_59
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_60
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_61
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_62
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_63
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler);
+}
+
+/**
+  * @brief  Get HSE Prescalers for RTC Clock
+  * @rmtoll CFGR         RTCPRE        LL_RCC_GetRTC_HSEPrescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_RTC_NOCLOCK
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_2
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_3
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_4
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_5
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_6
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_7
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_8
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_9
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_10
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_11
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_12
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_13
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_14
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_15
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_16
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_17
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_18
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_19
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_20
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_21
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_22
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_23
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_24
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_25
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_26
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_27
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_28
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_29
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_30
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_31
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_32
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_33
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_34
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_35
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_36
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_37
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_38
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_39
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_40
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_41
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_42
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_43
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_44
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_45
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_46
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_47
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_48
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_49
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_50
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_51
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_52
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_53
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_54
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_55
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_56
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_57
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_58
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_59
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_60
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_61
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_62
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_63
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM
+  * @{
+  */
+
+/**
+  * @brief  Set Timers Clock Prescalers
+  * @rmtoll CFGR         TIMPRE        LL_RCC_SetTIMPrescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_TIM_PRESCALER_TWICE
+  *         @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_TIMPRE, Prescaler);
+}
+
+/**
+  * @brief  Get Timers Clock Prescalers
+  * @rmtoll CFGR         TIMPRE        LL_RCC_GetTIMPrescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_TIM_PRESCALER_TWICE
+  *         @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_TIMPRE));
+}
+
+/**
+  * @}
+  */
+
+#if defined(HRTIM1)
+/** @defgroup RCC_LL_EF_HRTIM_SET_CLOCK_SOURCE HRTIM
+  * @{
+  */
+
+/**
+  * @brief  Set High Resolution Timers Clock Source
+  * @rmtoll CFGR         HRTIMSEL        LL_RCC_SetHRTIMClockSource
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_HRTIM_CLKSOURCE_TIM
+  *         @arg @ref LL_RCC_HRTIM_CLKSOURCE_CPU
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetHRTIMClockSource(uint32_t Prescaler)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_HRTIMSEL, Prescaler);
+}
+#endif /* HRTIM1 */
+
+#if defined(HRTIM1)
+/**
+  * @brief  Get High Resolution Timers Clock Source
+  * @rmtoll CFGR         HRTIMSEL        LL_RCC_GetHRTIMClockSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_HRTIM_CLKSOURCE_TIM
+  *         @arg @ref LL_RCC_HRTIM_CLKSOURCE_CPU
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetHRTIMClockSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HRTIMSEL));
+}
+/**
+  * @}
+  */
+#endif /* HRTIM1 */
+
+/** @defgroup RCC_LL_EF_PLL PLL
+  * @{
+  */
+
+/**
+  * @brief  Set the oscillator used as PLL clock source.
+  * @note   PLLSRC can be written only when All PLLs are disabled.
+  * @rmtoll PLLCKSELR      PLLSRC        LL_RCC_PLL_SetSource
+  * @param  PLLSource parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_CSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  *         @arg @ref LL_RCC_PLLSOURCE_NONE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_SetSource(uint32_t PLLSource)
+{
+  MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, PLLSource);
+}
+
+/**
+  * @brief  Get the oscillator used as PLL clock source.
+  * @rmtoll PLLCKSELR      PLLSRC        LL_RCC_PLL_GetSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_CSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  *         @arg @ref LL_RCC_PLLSOURCE_NONE
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC));
+}
+
+/**
+  * @brief  Enable PLL1
+  * @rmtoll CR           PLL1ON         LL_RCC_PLL1_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_PLL1ON);
+}
+
+/**
+  * @brief  Disable PLL1
+  * @note Cannot be disabled if the PLL1 clock is used as the system clock
+  * @rmtoll CR           PLL1ON         LL_RCC_PLL1_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON);
+}
+
+/**
+  * @brief  Check if PLL1 Ready
+  * @rmtoll CR           PLL1RDY        LL_RCC_PLL1_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL1_IsReady(void)
+{
+  return ((READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == (RCC_CR_PLL1RDY))?1UL:0UL);
+}
+
+/**
+  * @brief  Enable PLL1P
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLLCFGR           DIVP1EN         LL_RCC_PLL1P_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1P_Enable(void)
+{
+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN);
+}
+
+/**
+  * @brief  Enable PLL1Q
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLLCFGR           DIVQ1EN         LL_RCC_PLL1Q_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1Q_Enable(void)
+{
+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN);
+}
+
+/**
+  * @brief  Enable PLL1R
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLLCFGR           DIVR1EN         LL_RCC_PLL1R_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1R_Enable(void)
+{
+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN);
+}
+
+/**
+  * @brief  Enable PLL1 FRACN
+  * @rmtoll PLLCFGR           PLL1FRACEN         LL_RCC_PLL1FRACN_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1FRACN_Enable(void)
+{
+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN);
+}
+
+/**
+  * @brief  Check if PLL1 P is enabled
+  * @rmtoll PLLCFGR           DIVP1EN         LL_RCC_PLL1P_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL1P_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN) == RCC_PLLCFGR_DIVP1EN)?1UL:0UL);
+}
+
+/**
+  * @brief  Check if PLL1 Q is enabled
+  * @rmtoll PLLCFGR           DIVQ1EN         LL_RCC_PLL1Q_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL1Q_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN) == RCC_PLLCFGR_DIVQ1EN)?1UL:0UL);
+}
+
+/**
+  * @brief  Check if PLL1 R is enabled
+  * @rmtoll PLLCFGR           DIVR1EN         LL_RCC_PLL1R_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL1R_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN) == RCC_PLLCFGR_DIVR1EN)?1UL:0UL);
+}
+
+/**
+  * @brief  Check if PLL1 FRACN is enabled
+  * @rmtoll PLLCFGR           PLL1FRACEN         LL_RCC_PLL1FRACN_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL1FRACN_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN) == RCC_PLLCFGR_PLL1FRACEN)?1UL:0UL);
+}
+
+/**
+  * @brief  Disable PLL1P
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLLCFGR           DIVP1EN         LL_RCC_PLL1P_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1P_Disable(void)
+{
+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN);
+}
+
+/**
+  * @brief  Disable PLL1Q
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLLCFGR           DIVQ1EN         LL_RCC_PLL1Q_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1Q_Disable(void)
+{
+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN);
+}
+
+/**
+  * @brief  Disable PLL1R
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLLCFGR           DIVR1EN         LL_RCC_PLL1R_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1R_Disable(void)
+{
+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN);
+}
+
+/**
+  * @brief  Disable PLL1 FRACN
+  * @rmtoll PLLCFGR           PLL1FRACEN         LL_RCC_PLL1FRACN_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1FRACN_Disable(void)
+{
+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN);
+}
+
+/**
+  * @brief  Set PLL1 VCO OutputRange
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLLCFGR        PLL1VCOSEL       LL_RCC_PLL1_SetVCOOuputRange
+  * @param  VCORange This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLVCORANGE_WIDE
+  *         @arg @ref LL_RCC_PLLVCORANGE_MEDIUM
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1_SetVCOOutputRange(uint32_t VCORange)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, VCORange << RCC_PLLCFGR_PLL1VCOSEL_Pos);
+}
+
+/**
+  * @brief  Set PLL1 VCO Input Range
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLLCFGR        PLL1RGE       LL_RCC_PLL1_SetVCOInputRange
+  * @param  InputRange This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLINPUTRANGE_1_2
+  *         @arg @ref LL_RCC_PLLINPUTRANGE_2_4
+  *         @arg @ref LL_RCC_PLLINPUTRANGE_4_8
+  *         @arg @ref LL_RCC_PLLINPUTRANGE_8_16
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1_SetVCOInputRange(uint32_t InputRange)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, InputRange << RCC_PLLCFGR_PLL1RGE_Pos);
+}
+
+/**
+  * @brief  Get PLL1 N Coefficient
+  * @rmtoll PLL1DIVR        N1          LL_RCC_PLL1_GetN
+  * @retval A value between 4 and 512
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL1_GetN(void)
+{
+  return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_N1) >>  RCC_PLL1DIVR_N1_Pos) + 1UL);
+}
+
+/**
+  * @brief  Get PLL1 M Coefficient
+  * @rmtoll PLLCKSELR       DIVM1          LL_RCC_PLL1_GetM
+  * @retval A value between 0 and 63
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL1_GetM(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1) >>  RCC_PLLCKSELR_DIVM1_Pos);
+}
+
+/**
+  * @brief  Get PLL1 P Coefficient
+  * @rmtoll PLL1DIVR        P1          LL_RCC_PLL1_GetP
+  * @retval A value between 2 and 128
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL1_GetP(void)
+{
+  return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_P1) >>  RCC_PLL1DIVR_P1_Pos) + 1UL);
+}
+
+/**
+  * @brief  Get PLL1 Q Coefficient
+  * @rmtoll PLL1DIVR        Q1          LL_RCC_PLL1_GetQ
+  * @retval A value between 1 and 128
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL1_GetQ(void)
+{
+  return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_Q1) >>  RCC_PLL1DIVR_Q1_Pos) + 1UL);
+}
+
+/**
+  * @brief  Get PLL1 R Coefficient
+  * @rmtoll PLL1DIVR        R1          LL_RCC_PLL1_GetR
+  * @retval A value between 1 and 128
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL1_GetR(void)
+{
+  return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_R1) >>  RCC_PLL1DIVR_R1_Pos) + 1UL);
+}
+
+/**
+  * @brief  Get PLL1 FRACN Coefficient
+  * @rmtoll PLL1FRACR      FRACN1          LL_RCC_PLL1_GetFRACN
+  * @retval A value between 0 and 8191 (0x1FFF)
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL1_GetFRACN(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1) >>  RCC_PLL1FRACR_FRACN1_Pos);
+}
+
+/**
+  * @brief  Set PLL1 N Coefficient
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLL1DIVR        N1          LL_RCC_PLL1_SetN
+  * @param  N parameter can be a value between 4 and 512
+  */
+__STATIC_INLINE void LL_RCC_PLL1_SetN(uint32_t N)
+{
+  MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_N1, (N-1UL) << RCC_PLL1DIVR_N1_Pos);
+}
+
+/**
+  * @brief  Set PLL1 M Coefficient
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLLCKSELR       DIVM1          LL_RCC_PLL1_SetM
+  * @param  M parameter can be a value between 0 and 63
+  */
+__STATIC_INLINE void LL_RCC_PLL1_SetM(uint32_t M)
+{
+  MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1, M << RCC_PLLCKSELR_DIVM1_Pos);
+}
+
+/**
+  * @brief  Set PLL1 P Coefficient
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLL1DIVR        P1          LL_RCC_PLL1_SetP
+  * @param  P parameter can be a value between 2 and 128 (ODD division factor not supportted)
+  */
+__STATIC_INLINE void LL_RCC_PLL1_SetP(uint32_t P)
+{
+  MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_P1, (P-1UL) << RCC_PLL1DIVR_P1_Pos);
+}
+
+/**
+  * @brief  Set PLL1 Q Coefficient
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLL1DIVR        Q1          LL_RCC_PLL1_SetQ
+  * @param  Q parameter can be a value between 1 and 128
+  */
+__STATIC_INLINE void LL_RCC_PLL1_SetQ(uint32_t Q)
+{
+  MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_Q1, (Q-1UL) << RCC_PLL1DIVR_Q1_Pos);
+}
+
+/**
+  * @brief  Set PLL1 R Coefficient
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLL1DIVR        R1          LL_RCC_PLL1_SetR
+  * @param  R parameter can be a value between 1 and 128
+  */
+__STATIC_INLINE void LL_RCC_PLL1_SetR(uint32_t R)
+{
+  MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_R1, (R-1UL) << RCC_PLL1DIVR_R1_Pos);
+}
+
+/**
+  * @brief  Set PLL1 FRACN Coefficient
+  * @rmtoll PLL1FRACR        FRACN1          LL_RCC_PLL1_SetFRACN
+  * @param  FRACN parameter can be a value between 0 and 8191 (0x1FFF)
+  */
+__STATIC_INLINE void LL_RCC_PLL1_SetFRACN(uint32_t FRACN)
+{
+  MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, FRACN << RCC_PLL1FRACR_FRACN1_Pos);
+}
+
+/**
+  * @brief  Enable PLL2
+  * @rmtoll CR           PLL2ON         LL_RCC_PLL2_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_PLL2ON);
+}
+
+/**
+  * @brief  Disable PLL2
+  * @note Cannot be disabled if the PLL2 clock is used as the system clock
+  * @rmtoll CR           PLL2ON         LL_RCC_PLL2_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
+}
+
+/**
+  * @brief  Check if PLL2 Ready
+  * @rmtoll CR           PLL2RDY        LL_RCC_PLL2_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void)
+{
+  return ((READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == (RCC_CR_PLL2RDY))?1UL:0UL);
+}
+
+/**
+  * @brief  Enable PLL2P
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLLCFGR           DIVP2EN         LL_RCC_PLL2P_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2P_Enable(void)
+{
+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN);
+}
+
+/**
+  * @brief  Enable PLL2Q
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLLCFGR           DIVQ2EN         LL_RCC_PLL2Q_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2Q_Enable(void)
+{
+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN);
+}
+
+/**
+  * @brief  Enable PLL2R
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLLCFGR           DIVR2EN         LL_RCC_PLL2R_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2R_Enable(void)
+{
+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN);
+}
+
+/**
+  * @brief  Enable PLL2 FRACN
+  * @rmtoll PLLCFGR           PLL2FRACEN         LL_RCC_PLL2FRACN_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2FRACN_Enable(void)
+{
+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN);
+}
+
+/**
+  * @brief  Check if PLL2 P is enabled
+  * @rmtoll PLLCFGR           DIVP2EN         LL_RCC_PLL2P_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL2P_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN) == RCC_PLLCFGR_DIVP2EN)?1UL:0UL);
+}
+
+/**
+  * @brief  Check if PLL2 Q is enabled
+  * @rmtoll PLLCFGR           DIVQ2EN         LL_RCC_PLL2Q_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL2Q_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN) == RCC_PLLCFGR_DIVQ2EN)?1UL:0UL);
+}
+
+/**
+  * @brief  Check if PLL2 R is enabled
+  * @rmtoll PLLCFGR           DIVR2EN         LL_RCC_PLL2R_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL2R_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN) == RCC_PLLCFGR_DIVR2EN)?1UL:0UL);
+}
+
+/**
+  * @brief  Check if PLL2 FRACN is enabled
+  * @rmtoll PLLCFGR           PLL2FRACEN         LL_RCC_PLL2FRACN_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL2FRACN_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) == RCC_PLLCFGR_PLL2FRACEN)?1UL:0UL);
+}
+
+/**
+  * @brief  Disable PLL2P
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLLCFGR           DIVP2EN         LL_RCC_PLL2P_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2P_Disable(void)
+{
+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN);
+}
+
+/**
+  * @brief  Disable PLL2Q
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLLCFGR           DIVQ2EN         LL_RCC_PLL2Q_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2Q_Disable(void)
+{
+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN);
+}
+
+/**
+  * @brief  Disable PLL2R
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLLCFGR           DIVR2EN         LL_RCC_PLL2R_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2R_Disable(void)
+{
+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN);
+}
+
+/**
+  * @brief  Disable PLL2 FRACN
+  * @rmtoll PLLCFGR           PLL2FRACEN         LL_RCC_PLL2FRACN_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2FRACN_Disable(void)
+{
+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN);
+}
+
+/**
+  * @brief  Set PLL2 VCO OutputRange
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLLCFGR        PLL2VCOSEL       LL_RCC_PLL2_SetVCOOuputRange
+  * @param  VCORange This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLVCORANGE_WIDE
+  *         @arg @ref LL_RCC_PLLVCORANGE_MEDIUM
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2_SetVCOOutputRange(uint32_t VCORange)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, VCORange << RCC_PLLCFGR_PLL2VCOSEL_Pos);
+}
+
+/**
+  * @brief  Set PLL2 VCO Input Range
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLLCFGR        PLL2RGE       LL_RCC_PLL2_SetVCOInputRange
+  * @param  InputRange This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLINPUTRANGE_1_2
+  *         @arg @ref LL_RCC_PLLINPUTRANGE_2_4
+  *         @arg @ref LL_RCC_PLLINPUTRANGE_4_8
+  *         @arg @ref LL_RCC_PLLINPUTRANGE_8_16
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2_SetVCOInputRange(uint32_t InputRange)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, InputRange << RCC_PLLCFGR_PLL2RGE_Pos);
+}
+
+/**
+  * @brief  Get PLL2 N Coefficient
+  * @rmtoll PLL2DIVR        N2          LL_RCC_PLL2_GetN
+  * @retval A value between 4 and 512
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL2_GetN(void)
+{
+  return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_N2) >>  RCC_PLL2DIVR_N2_Pos) + 1UL);
+}
+
+/**
+  * @brief  Get PLL2 M Coefficient
+  * @rmtoll PLLCKSELR       DIVM2          LL_RCC_PLL2_GetM
+  * @retval A value between 0 and 63
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL2_GetM(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM2) >>  RCC_PLLCKSELR_DIVM2_Pos);
+}
+
+/**
+  * @brief  Get PLL2 P Coefficient
+  * @rmtoll PLL2DIVR        P2          LL_RCC_PLL2_GetP
+  * @retval A value between 1 and 128
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL2_GetP(void)
+{
+  return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_P2) >>  RCC_PLL2DIVR_P2_Pos) + 1UL);
+}
+
+/**
+  * @brief  Get PLL2 Q Coefficient
+  * @rmtoll PLL2DIVR        Q2          LL_RCC_PLL2_GetQ
+  * @retval A value between 1 and 128
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL2_GetQ(void)
+{
+  return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_Q2) >>  RCC_PLL2DIVR_Q2_Pos) + 1UL);
+}
+
+/**
+  * @brief  Get PLL2 R Coefficient
+  * @rmtoll PLL2DIVR        R2          LL_RCC_PLL2_GetR
+  * @retval A value between 1 and 128
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL2_GetR(void)
+{
+  return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_R2) >>  RCC_PLL2DIVR_R2_Pos) + 1UL);
+}
+
+/**
+  * @brief  Get PLL2 FRACN Coefficient
+  * @rmtoll PLL2FRACR      FRACN2          LL_RCC_PLL2_GetFRACN
+  * @retval A value between 0 and 8191 (0x1FFF)
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL2_GetFRACN(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2) >>  RCC_PLL2FRACR_FRACN2_Pos);
+}
+
+/**
+  * @brief  Set PLL2 N Coefficient
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLL2DIVR        N2          LL_RCC_PLL2_SetN
+  * @param  N parameter can be a value between 4 and 512
+  */
+__STATIC_INLINE void LL_RCC_PLL2_SetN(uint32_t N)
+{
+  MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_N2, (N-1UL) << RCC_PLL2DIVR_N2_Pos);
+}
+
+/**
+  * @brief  Set PLL2 M Coefficient
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLLCKSELR       DIVM2          LL_RCC_PLL2_SetM
+  * @param  M parameter can be a value between 0 and 63
+  */
+__STATIC_INLINE void LL_RCC_PLL2_SetM(uint32_t M)
+{
+  MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM2, M << RCC_PLLCKSELR_DIVM2_Pos);
+}
+
+/**
+  * @brief  Set PLL2 P Coefficient
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLL2DIVR        P2          LL_RCC_PLL2_SetP
+  * @param  P parameter can be a value between 1 and 128
+  */
+__STATIC_INLINE void LL_RCC_PLL2_SetP(uint32_t P)
+{
+  MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_P2, (P-1UL) << RCC_PLL2DIVR_P2_Pos);
+}
+
+/**
+  * @brief  Set PLL2 Q Coefficient
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLL2DIVR        Q2          LL_RCC_PLL2_SetQ
+  * @param  Q parameter can be a value between 1 and 128
+  */
+__STATIC_INLINE void LL_RCC_PLL2_SetQ(uint32_t Q)
+{
+  MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_Q2, (Q-1UL) << RCC_PLL2DIVR_Q2_Pos);
+}
+
+/**
+  * @brief  Set PLL2 R Coefficient
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLL2DIVR        R2          LL_RCC_PLL2_SetR
+  * @param  R parameter can be a value between 1 and 128
+  */
+__STATIC_INLINE void LL_RCC_PLL2_SetR(uint32_t R)
+{
+  MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_R2, (R-1UL) << RCC_PLL2DIVR_R2_Pos);
+}
+
+/**
+  * @brief  Set PLL2 FRACN Coefficient
+  * @rmtoll PLL2FRACR        FRACN2          LL_RCC_PLL2_SetFRACN
+  * @param  FRACN parameter can be a value between 0 and 8191 (0x1FFF)
+  */
+__STATIC_INLINE void LL_RCC_PLL2_SetFRACN(uint32_t FRACN)
+{
+  MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2, FRACN << RCC_PLL2FRACR_FRACN2_Pos);
+}
+
+/**
+  * @brief  Enable PLL3
+  * @rmtoll CR           PLL3ON         LL_RCC_PLL3_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_PLL3ON);
+}
+
+/**
+  * @brief  Disable PLL3
+  * @note Cannot be disabled if the PLL3 clock is used as the system clock
+  * @rmtoll CR           PLL3ON         LL_RCC_PLL3_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
+}
+
+/**
+  * @brief  Check if PLL3 Ready
+  * @rmtoll CR           PLL3RDY        LL_RCC_PLL3_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL3_IsReady(void)
+{
+  return ((READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == (RCC_CR_PLL3RDY))?1UL:0UL);
+}
+
+/**
+  * @brief  Enable PLL3P
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLLCFGR           DIVP3EN         LL_RCC_PLL3P_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3P_Enable(void)
+{
+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN);
+}
+
+/**
+  * @brief  Enable PLL3Q
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLLCFGR           DIVQ3EN         LL_RCC_PLL3Q_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3Q_Enable(void)
+{
+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN);
+}
+
+/**
+  * @brief  Enable PLL3R
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLLCFGR           DIVR3EN         LL_RCC_PLL3R_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3R_Enable(void)
+{
+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN);
+}
+
+/**
+  * @brief  Enable PLL3 FRACN
+  * @rmtoll PLLCFGR           PLL3FRACEN         LL_RCC_PLL3FRACN_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3FRACN_Enable(void)
+{
+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN);
+}
+
+/**
+  * @brief  Check if PLL3 P is enabled
+  * @rmtoll PLLCFGR           DIVP3EN         LL_RCC_PLL3P_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL3P_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN) == RCC_PLLCFGR_DIVP3EN)?1UL:0UL);
+}
+
+/**
+  * @brief  Check if PLL3 Q is enabled
+  * @rmtoll PLLCFGR           DIVQ3EN         LL_RCC_PLL3Q_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL3Q_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN) == RCC_PLLCFGR_DIVQ3EN)?1UL:0UL);
+}
+
+/**
+  * @brief  Check if PLL3 R is enabled
+  * @rmtoll PLLCFGR           DIVR3EN         LL_RCC_PLL3R_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL3R_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN) == RCC_PLLCFGR_DIVR3EN)?1UL:0UL);
+}
+
+/**
+  * @brief  Check if PLL3 FRACN is enabled
+  * @rmtoll PLLCFGR           PLL3FRACEN         LL_RCC_PLL3FRACN_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL3FRACN_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) == RCC_PLLCFGR_PLL3FRACEN)?1UL:0UL);
+}
+
+/**
+  * @brief  Disable PLL3P
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLLCFGR           DIVP2EN         LL_RCC_PLL3P_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3P_Disable(void)
+{
+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN);
+}
+
+/**
+  * @brief  Disable PLL3Q
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLLCFGR           DIVQ3EN         LL_RCC_PLL3Q_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3Q_Disable(void)
+{
+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN);
+}
+
+/**
+  * @brief  Disable PLL3R
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLLCFGR           DIVR3EN         LL_RCC_PLL3R_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3R_Disable(void)
+{
+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN);
+}
+
+/**
+  * @brief  Disable PLL3 FRACN
+  * @rmtoll PLLCFGR           PLL3FRACEN         LL_RCC_PLL3FRACN_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3FRACN_Disable(void)
+{
+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN);
+}
+
+/**
+  * @brief  Set PLL3 VCO OutputRange
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLLCFGR        PLL3VCOSEL       LL_RCC_PLL3_SetVCOOuputRange
+  * @param  VCORange This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLVCORANGE_WIDE
+  *         @arg @ref LL_RCC_PLLVCORANGE_MEDIUM
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3_SetVCOOutputRange(uint32_t VCORange)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, VCORange << RCC_PLLCFGR_PLL3VCOSEL_Pos);
+}
+
+/**
+  * @brief  Set PLL3 VCO Input Range
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLLCFGR        PLL3RGE       LL_RCC_PLL3_SetVCOInputRange
+  * @param  InputRange This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLINPUTRANGE_1_2
+  *         @arg @ref LL_RCC_PLLINPUTRANGE_2_4
+  *         @arg @ref LL_RCC_PLLINPUTRANGE_4_8
+  *         @arg @ref LL_RCC_PLLINPUTRANGE_8_16
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3_SetVCOInputRange(uint32_t InputRange)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, InputRange << RCC_PLLCFGR_PLL3RGE_Pos);
+}
+
+/**
+  * @brief  Get PLL3 N Coefficient
+  * @rmtoll PLL3DIVR        N3          LL_RCC_PLL3_GetN
+  * @retval A value between 4 and 512
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL3_GetN(void)
+{
+  return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_N3) >>  RCC_PLL3DIVR_N3_Pos) + 1UL);
+}
+
+/**
+  * @brief  Get PLL3 M Coefficient
+  * @rmtoll PLLCKSELR       DIVM3          LL_RCC_PLL3_GetM
+  * @retval A value between 0 and 63
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL3_GetM(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM3) >>  RCC_PLLCKSELR_DIVM3_Pos);
+}
+
+/**
+  * @brief  Get PLL3 P Coefficient
+  * @rmtoll PLL3DIVR        P3          LL_RCC_PLL3_GetP
+  * @retval A value between 1 and 128
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL3_GetP(void)
+{
+  return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_P3) >>  RCC_PLL3DIVR_P3_Pos) + 1UL);
+}
+
+/**
+  * @brief  Get PLL3 Q Coefficient
+  * @rmtoll PLL3DIVR        Q3          LL_RCC_PLL3_GetQ
+  * @retval A value between 1 and 128
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL3_GetQ(void)
+{
+  return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_Q3) >>  RCC_PLL3DIVR_Q3_Pos) + 1UL);
+}
+
+/**
+  * @brief  Get PLL3 R Coefficient
+  * @rmtoll PLL3DIVR        R3          LL_RCC_PLL3_GetR
+  * @retval A value between 1 and 128
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL3_GetR(void)
+{
+  return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_R3) >>  RCC_PLL3DIVR_R3_Pos) + 1UL);
+}
+
+/**
+  * @brief  Get PLL3 FRACN Coefficient
+  * @rmtoll PLL3FRACR      FRACN3          LL_RCC_PLL3_GetFRACN
+  * @retval A value between 0 and 8191 (0x1FFF)
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL3_GetFRACN(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3) >>  RCC_PLL3FRACR_FRACN3_Pos);
+}
+
+/**
+  * @brief  Set PLL3 N Coefficient
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLL3DIVR        N3          LL_RCC_PLL3_SetN
+  * @param  N parameter can be a value between 4 and 512
+  */
+__STATIC_INLINE void LL_RCC_PLL3_SetN(uint32_t N)
+{
+  MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_N3, (N-1UL) << RCC_PLL3DIVR_N3_Pos);
+}
+
+/**
+  * @brief  Set PLL3 M Coefficient
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLLCKSELR       DIVM3          LL_RCC_PLL3_SetM
+  * @param  M parameter can be a value between 0 and 63
+  */
+__STATIC_INLINE void LL_RCC_PLL3_SetM(uint32_t M)
+{
+  MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM3, M << RCC_PLLCKSELR_DIVM3_Pos);
+}
+
+/**
+  * @brief  Set PLL3 P Coefficient
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLL3DIVR        P3          LL_RCC_PLL3_SetP
+  * @param  P parameter can be a value between 1 and 128
+  */
+__STATIC_INLINE void LL_RCC_PLL3_SetP(uint32_t P)
+{
+  MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_P3, (P-1UL) << RCC_PLL3DIVR_P3_Pos);
+}
+
+/**
+  * @brief  Set PLL3 Q Coefficient
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLL3DIVR        Q3          LL_RCC_PLL3_SetQ
+  * @param  Q parameter can be a value between 1 and 128
+  */
+__STATIC_INLINE void LL_RCC_PLL3_SetQ(uint32_t Q)
+{
+  MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_Q3, (Q-1UL) << RCC_PLL3DIVR_Q3_Pos);
+}
+
+/**
+  * @brief  Set PLL3 R Coefficient
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLL3DIVR        R3          LL_RCC_PLL3_SetR
+  * @param  R parameter can be a value between 1 and 128
+  */
+__STATIC_INLINE void LL_RCC_PLL3_SetR(uint32_t R)
+{
+  MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_R3, (R-1UL) << RCC_PLL3DIVR_R3_Pos);
+}
+
+/**
+  * @brief  Set PLL3 FRACN Coefficient
+  * @rmtoll PLL3FRACR        FRACN3          LL_RCC_PLL3_SetFRACN
+  * @param  FRACN parameter can be a value between 0 and 8191 (0x1FFF)
+  */
+__STATIC_INLINE void LL_RCC_PLL3_SetFRACN(uint32_t FRACN)
+{
+  MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, FRACN << RCC_PLL3FRACR_FRACN3_Pos);
+}
+
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
+  * @{
+  */
+
+/**
+  * @brief  Clear LSI ready interrupt flag
+  * @rmtoll CICR         LSIRDYC       LL_RCC_ClearFlag_LSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
+}
+
+/**
+  * @brief  Clear LSE ready interrupt flag
+  * @rmtoll CICR         LSERDYC       LL_RCC_ClearFlag_LSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
+}
+
+/**
+  * @brief  Clear HSI ready interrupt flag
+  * @rmtoll CICR         HSIRDYC       LL_RCC_ClearFlag_HSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
+}
+
+/**
+  * @brief  Clear HSE ready interrupt flag
+  * @rmtoll CICR         HSERDYC       LL_RCC_ClearFlag_HSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
+}
+
+/**
+  * @brief  Clear CSI ready interrupt flag
+  * @rmtoll CICR         CSIRDYC       LL_RCC_ClearFlag_CSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_CSIRDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_CSIRDYC);
+}
+
+/**
+  * @brief  Clear HSI48 ready interrupt flag
+  * @rmtoll CICR         HSI48RDYC       LL_RCC_ClearFlag_HSI48RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
+}
+
+/**
+  * @brief  Clear PLL1 ready interrupt flag
+  * @rmtoll CICR         PLL1RDYC       LL_RCC_ClearFlag_PLL1RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_PLL1RDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
+}
+
+/**
+  * @brief  Clear PLL2 ready interrupt flag
+  * @rmtoll CICR         PLL2RDYC       LL_RCC_ClearFlag_PLL2RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_PLL2RDYC);
+}
+
+/**
+  * @brief  Clear PLL3 ready interrupt flag
+  * @rmtoll CICR         PLL3RDYC       LL_RCC_ClearFlag_PLL3RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_PLL3RDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_PLL3RDYC);
+}
+
+/**
+  * @brief  Clear LSE Clock security system interrupt flag
+  * @rmtoll CICR         LSECSSC         LL_RCC_ClearFlag_LSECSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
+}
+
+/**
+  * @brief  Clear HSE Clock security system interrupt flag
+  * @rmtoll CICR         HSECSSC         LL_RCC_ClearFlag_HSECSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_HSECSSC);
+}
+
+/**
+  * @brief  Check if LSI ready interrupt occurred or not
+  * @rmtoll CIFR         LSIRDYF       LL_RCC_IsActiveFlag_LSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if LSE ready interrupt occurred or not
+  * @rmtoll CIFR         LSERDYF       LL_RCC_IsActiveFlag_LSERDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if HSI ready interrupt occurred or not
+  * @rmtoll CIFR         HSIRDYF       LL_RCC_IsActiveFlag_HSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if HSE ready interrupt occurred or not
+  * @rmtoll CIFR         HSERDYF       LL_RCC_IsActiveFlag_HSERDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if CSI ready interrupt occurred or not
+  * @rmtoll CIFR         CSIRDYF       LL_RCC_IsActiveFlag_CSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CSIRDY(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSIRDYF) == (RCC_CIFR_CSIRDYF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if HSI48 ready interrupt occurred or not
+  * @rmtoll CIFR         HSI48RDYF       LL_RCC_IsActiveFlag_HSI48RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if PLL1 ready interrupt occurred or not
+  * @rmtoll CIFR         PLLRDYF       LL_RCC_IsActiveFlag_PLL1RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL1RDY(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if PLL2 ready interrupt occurred or not
+  * @rmtoll CIFR         PLL2RDYF       LL_RCC_IsActiveFlag_PLL2RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL2RDYF) == (RCC_CIFR_PLL2RDYF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if PLL3 ready interrupt occurred or not
+  * @rmtoll CIFR         PLL3RDYF       LL_RCC_IsActiveFlag_PLL3RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL3RDY(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL3RDYF) == (RCC_CIFR_PLL3RDYF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if LSE Clock security system interrupt occurred or not
+  * @rmtoll CIFR         LSECSSF          LL_RCC_IsActiveFlag_LSECSS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if HSE Clock security system interrupt occurred or not
+  * @rmtoll CIFR         HSECSSF          LL_RCC_IsActiveFlag_HSECSS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSECSSF) == (RCC_CIFR_HSECSSF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC flag Low Power D1 reset is set or not.
+  * @rmtoll RSR          LPWRRSTF       LL_RCC_IsActiveFlag_LPWRRST (*)\n
+  *         RSR          LPWR1RSTF      LL_RCC_IsActiveFlag_LPWRRST (**)
+  *
+  * (*) Only available for single core devices
+  * (**) Only available for Dual core devices
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
+{
+#if defined(DUAL_CORE)
+  return ((READ_BIT(RCC->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF))?1UL:0UL);
+#else
+  return ((READ_BIT(RCC->RSR, RCC_RSR_LPWRRSTF) == (RCC_RSR_LPWRRSTF))?1UL:0UL);
+#endif /*DUAL_CORE*/
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Check if RCC flag Low Power D2 reset is set or not.
+  * @rmtoll RSR          LPWR2RSTF      LL_RCC_IsActiveFlag_LPWR2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWR2RST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF))?1UL:0UL);
+}
+#endif  /*DUAL_CORE*/
+
+/**
+  * @brief  Check if RCC flag Window Watchdog 1 reset is set or not.
+  * @rmtoll RSR          WWDG1RSTF      LL_RCC_IsActiveFlag_WWDG1RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDG1RST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF))?1UL:0UL);
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Check if RCC flag Window Watchdog 2 reset is set or not.
+  * @rmtoll RSR          WWDG2RSTF      LL_RCC_IsActiveFlag_WWDG2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDG2RST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF))?1UL:0UL);
+}
+#endif  /*DUAL_CORE*/
+
+/**
+  * @brief  Check if RCC flag Independent Watchdog 1 reset is set or not.
+  * @rmtoll RSR          IWDG1RSTF      LL_RCC_IsActiveFlag_IWDG1RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDG1RST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF))?1UL:0UL);
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Check if RCC flag Independent Watchdog 2 reset is set or not.
+  * @rmtoll RSR          IWDG2RSTF      LL_RCC_IsActiveFlag_IWDG2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDG2RST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF))?1UL:0UL);
+}
+#endif  /*DUAL_CORE*/
+
+/**
+  * @brief  Check if RCC flag Software reset is set or not.
+  * @rmtoll RSR          SFTRSTF        LL_RCC_IsActiveFlag_SFTRST (*)\n
+  *         RSR          SFT1RSTF       LL_RCC_IsActiveFlag_SFTRST (**)
+  *
+  * (*) Only available for single core devices
+  * (**) Only available for Dual core devices
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
+{
+#if defined(DUAL_CORE)
+  return ((READ_BIT(RCC->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF))?1UL:0UL);
+#else
+  return ((READ_BIT(RCC->RSR, RCC_RSR_SFTRSTF) == (RCC_RSR_SFTRSTF))?1UL:0UL);
+#endif  /*DUAL_CORE*/
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Check if RCC flag Software reset is set or not.
+  * @rmtoll RSR          SFT2RSTF       LL_RCC_IsActiveFlag_SFT2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFT2RST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF))?1UL:0UL);
+}
+#endif  /*DUAL_CORE*/
+
+/**
+  * @brief  Check if RCC flag POR/PDR reset is set or not.
+  * @rmtoll RSR          PORRSTF       LL_RCC_IsActiveFlag_PORRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC flag Pin reset is set or not.
+  * @rmtoll RSR          PINRSTF       LL_RCC_IsActiveFlag_PINRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC flag BOR reset is set or not.
+  * @rmtoll RSR          BORRSTF       LL_RCC_IsActiveFlag_BORRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF))?1UL:0UL);
+}
+
+#if defined(RCC_RSR_D1RSTF)
+/**
+  * @brief  Check if RCC flag D1 reset is set or not.
+  * @rmtoll RSR          D1RSTF       LL_RCC_IsActiveFlag_D1RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_D1RST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF))?1UL:0UL);
+}
+#endif /* RCC_RSR_D1RSTF */
+
+#if defined(RCC_RSR_CDRSTF)
+/**
+  * @brief  Check if RCC flag CD reset is set or not.
+  * @rmtoll RSR          CDRSTF       LL_RCC_IsActiveFlag_CDRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CDRST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_CDRSTF) == (RCC_RSR_CDRSTF))?1UL:0UL);
+}
+#endif /* RCC_RSR_CDRSTF */
+
+#if defined(RCC_RSR_D2RSTF)
+/**
+  * @brief  Check if RCC flag D2 reset is set or not.
+  * @rmtoll RSR          D2RSTF       LL_RCC_IsActiveFlag_D2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_D2RST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF))?1UL:0UL);
+}
+#endif /* RCC_RSR_D2RSTF */
+
+#if defined(RCC_RSR_C1RSTF) || defined(RCC_RSR_CPURSTF)
+/**
+  * @brief  Check if RCC flag CPU reset is set or not.
+  * @rmtoll RSR          CPURSTF       LL_RCC_IsActiveFlag_CPURST (*)\n
+  *         RSR          C1RSTF        LL_RCC_IsActiveFlag_CPURST (**)
+  *
+  * (*) Only available for single core devices
+  * (**) Only available for Dual core devices
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CPURST(void)
+{
+#if defined(DUAL_CORE)
+  return ((READ_BIT(RCC->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF))?1UL:0UL);
+#else
+  return ((READ_BIT(RCC->RSR, RCC_RSR_CPURSTF) == (RCC_RSR_CPURSTF))?1UL:0UL);
+#endif/*DUAL_CORE*/
+}
+#endif /* defined(RCC_RSR_C1RSTF) || defined(RCC_RSR_CPURSTF) */
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Check if RCC flag CPU2 reset is set or not.
+  * @rmtoll RSR          C2RSTF       LL_RCC_IsActiveFlag_CPU2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CPU2RST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF))?1UL:0UL);
+}
+#endif  /*DUAL_CORE*/
+
+/**
+  * @brief  Set RMVF bit to clear all reset flags.
+  * @rmtoll RSR          RMVF          LL_RCC_ClearResetFlags
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
+{
+  SET_BIT(RCC->RSR, RCC_RSR_RMVF);
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Check if RCC_C1 flag Low Power D1 reset is set or not.
+  * @rmtoll RSR          LPWR1RSTF      LL_C1_RCC_IsActiveFlag_LPWRRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_LPWRRST(void)
+{
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C1 flag Low Power D2 reset is set or not.
+  * @rmtoll RSR          LPWR2RSTF      LL_C1_RCC_IsActiveFlag_LPWR2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_LPWR2RST(void)
+{
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C1 flag Window Watchdog 1 reset is set or not.
+  * @rmtoll RSR          WWDG1RSTF      LL_C1_RCC_IsActiveFlag_WWDG1RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_WWDG1RST(void)
+{
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C1 flag Window Watchdog 2 reset is set or not.
+  * @rmtoll RSR          WWDG2RSTF      LL_C1_RCC_IsActiveFlag_WWDG2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_WWDG2RST(void)
+{
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C1 flag Independent Watchdog 1 reset is set or not.
+  * @rmtoll RSR          IWDG1RSTF      LL_C1_RCC_IsActiveFlag_IWDG1RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_IWDG1RST(void)
+{
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C1 flag Independent Watchdog 2 reset is set or not.
+  * @rmtoll RSR          IWDG2RSTF      LL_C1_RCC_IsActiveFlag_IWDG2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_IWDG2RST(void)
+{
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C1 flag Software reset is set or not.
+  * @rmtoll RSR          SFT1RSTF       LL_C1_RCC_IsActiveFlag_SFTRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_SFTRST(void)
+{
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C1 flag Software reset is set or not.
+  * @rmtoll RSR          SFT2RSTF       LL_C1_RCC_IsActiveFlag_SFT2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_SFT2RST(void)
+{
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C1 flag POR/PDR reset is set or not.
+  * @rmtoll RSR          PORRSTF       LL_C1_RCC_IsActiveFlag_PORRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_PORRST(void)
+{
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C1 flag Pin reset is set or not.
+  * @rmtoll RSR          PINRSTF       LL_C1_RCC_IsActiveFlag_PINRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_PINRST(void)
+{
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C1 flag BOR reset is set or not.
+  * @rmtoll RSR          BORRSTF       LL_C1_RCC_IsActiveFlag_BORRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_BORRST(void)
+{
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C1 flag D1 reset is set or not.
+  * @rmtoll RSR          D1RSTF       LL_C1_RCC_IsActiveFlag_D1RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_D1RST(void)
+{
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C1 flag D2 reset is set or not.
+  * @rmtoll RSR          D2RSTF       LL_C1_RCC_IsActiveFlag_D2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_D2RST(void)
+{
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C1 flag CPU reset is set or not.
+  * @rmtoll RSR          C1RSTF       LL_C1_RCC_IsActiveFlag_CPURST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_CPURST(void)
+{
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C1 flag CPU2 reset is set or not.
+  * @rmtoll RSR          C2RSTF       LL_C1_RCC_IsActiveFlag_CPU2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_CPU2RST(void)
+{
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Set RMVF bit to clear the reset flags.
+  * @rmtoll RSR          RMVF          LL_C1_RCC_ClearResetFlags
+  * @retval None
+  */
+__STATIC_INLINE void LL_C1_RCC_ClearResetFlags(void)
+{
+  SET_BIT(RCC_C1->RSR, RCC_RSR_RMVF);
+}
+
+/**
+  * @brief  Check if RCC_C2 flag Low Power D1 reset is set or not.
+  * @rmtoll RSR          LPWR1RSTF      LL_C2_RCC_IsActiveFlag_LPWRRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_LPWRRST(void)
+{
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C2 flag Low Power D2 reset is set or not.
+  * @rmtoll RSR          LPWR2RSTF      LL_C2_RCC_IsActiveFlag_LPWR2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_LPWR2RST(void)
+{
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C2 flag Window Watchdog 1 reset is set or not.
+  * @rmtoll RSR          WWDG1RSTF      LL_C2_RCC_IsActiveFlag_WWDG1RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_WWDG1RST(void)
+{
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C2 flag Window Watchdog 2 reset is set or not.
+  * @rmtoll RSR          WWDG2RSTF      LL_C2_RCC_IsActiveFlag_WWDG2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_WWDG2RST(void)
+{
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C2 flag Independent Watchdog 1 reset is set or not.
+  * @rmtoll RSR          IWDG1RSTF      LL_C2_RCC_IsActiveFlag_IWDG1RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_IWDG1RST(void)
+{
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C2 flag Independent Watchdog 2 reset is set or not.
+  * @rmtoll RSR          IWDG2RSTF      LL_C2_RCC_IsActiveFlag_IWDG2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_IWDG2RST(void)
+{
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C2 flag Software reset is set or not.
+  * @rmtoll RSR          SFT1RSTF       LL_C2_RCC_IsActiveFlag_SFTRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_SFTRST(void)
+{
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C2 flag Software reset is set or not.
+  * @rmtoll RSR          SFT2RSTF       LL_C2_RCC_IsActiveFlag_SFT2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_SFT2RST(void)
+{
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C2 flag POR/PDR reset is set or not.
+  * @rmtoll RSR          PORRSTF       LL_C2_RCC_IsActiveFlag_PORRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_PORRST(void)
+{
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C2 flag Pin reset is set or not.
+  * @rmtoll RSR          PINRSTF       LL_C2_RCC_IsActiveFlag_PINRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_PINRST(void)
+{
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C2 flag BOR reset is set or not.
+  * @rmtoll RSR          BORRSTF       LL_C2_RCC_IsActiveFlag_BORRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_BORRST(void)
+{
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C2 flag D1 reset is set or not.
+  * @rmtoll RSR          D1RSTF       LL_C2_RCC_IsActiveFlag_D1RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_D1RST(void)
+{
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C2 flag D2 reset is set or not.
+  * @rmtoll RSR          D2RSTF       LL_C2_RCC_IsActiveFlag_D2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_D2RST(void)
+{
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C2 flag CPU reset is set or not.
+  * @rmtoll RSR          C1RSTF       LL_C2_RCC_IsActiveFlag_CPURST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_CPURST(void)
+{
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C2 flag CPU2 reset is set or not.
+  * @rmtoll RSR          C2RSTF       LL_C2_RCC_IsActiveFlag_CPU2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_CPU2RST(void)
+{
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Set RMVF bit to clear the reset flags.
+  * @rmtoll RSR          RMVF          LL_C2_RCC_ClearResetFlags
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_RCC_ClearResetFlags(void)
+{
+  SET_BIT(RCC_C2->RSR, RCC_RSR_RMVF);
+}
+#endif /*DUAL_CORE*/
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_IT_Management IT Management
+  * @{
+  */
+
+/**
+  * @brief  Enable LSI ready interrupt
+  * @rmtoll CIER         LSIRDYIE      LL_RCC_EnableIT_LSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
+}
+
+/**
+  * @brief  Enable LSE ready interrupt
+  * @rmtoll CIER         LSERDYIE      LL_RCC_EnableIT_LSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
+}
+
+/**
+  * @brief  Enable HSI ready interrupt
+  * @rmtoll CIER         HSIRDYIE      LL_RCC_EnableIT_HSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
+}
+
+/**
+  * @brief  Enable HSE ready interrupt
+  * @rmtoll CIER         HSERDYIE      LL_RCC_EnableIT_HSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
+}
+
+/**
+  * @brief  Enable CSI ready interrupt
+  * @rmtoll CIER         CSIRDYIE      LL_RCC_EnableIT_CSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_CSIRDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_CSIRDYIE);
+}
+
+/**
+  * @brief  Enable HSI48 ready interrupt
+  * @rmtoll CIER         HSI48RDYIE      LL_RCC_EnableIT_HSI48RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
+}
+
+/**
+  * @brief  Enable PLL1 ready interrupt
+  * @rmtoll CIER         PLL1RDYIE      LL_RCC_EnableIT_PLL1RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_PLL1RDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE);
+}
+
+/**
+  * @brief  Enable PLL2 ready interrupt
+  * @rmtoll CIER         PLL2RDYIE  LL_RCC_EnableIT_PLL2RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE);
+}
+
+/**
+  * @brief  Enable PLL3 ready interrupt
+  * @rmtoll CIER         PLL3RDYIE  LL_RCC_EnableIT_PLL3RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_PLL3RDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE);
+}
+
+/**
+  * @brief  Enable LSECSS interrupt
+  * @rmtoll CIER         LSECSSIE  LL_RCC_EnableIT_LSECSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
+}
+
+/**
+  * @brief  Disable LSI ready interrupt
+  * @rmtoll CIER         LSIRDYIE      LL_RCC_DisableIT_LSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
+}
+
+/**
+  * @brief  Disable LSE ready interrupt
+  * @rmtoll CIER         LSERDYIE      LL_RCC_DisableIT_LSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
+}
+
+/**
+  * @brief  Disable HSI ready interrupt
+  * @rmtoll CIER         HSIRDYIE      LL_RCC_DisableIT_HSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
+}
+
+/**
+  * @brief  Disable HSE ready interrupt
+  * @rmtoll CIER         HSERDYIE      LL_RCC_DisableIT_HSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
+}
+
+/**
+  * @brief  Disable CSI ready interrupt
+  * @rmtoll CIER         CSIRDYIE      LL_RCC_DisableIT_CSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_CSIRDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_CSIRDYIE);
+}
+
+/**
+  * @brief  Disable HSI48 ready interrupt
+  * @rmtoll CIER         HSI48RDYIE      LL_RCC_DisableIT_HSI48RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
+}
+
+/**
+  * @brief  Disable PLL1 ready interrupt
+  * @rmtoll CIER         PLL1RDYIE      LL_RCC_DisableIT_PLL1RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_PLL1RDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE);
+}
+
+/**
+  * @brief  Disable PLL2 ready interrupt
+  * @rmtoll CIER         PLL2RDYIE  LL_RCC_DisableIT_PLL2RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE);
+}
+
+/**
+  * @brief  Disable PLL3 ready interrupt
+  * @rmtoll CIER         PLL3RDYIE  LL_RCC_DisableIT_PLL3RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_PLL3RDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE);
+}
+
+/**
+  * @brief  Disable LSECSS interrupt
+  * @rmtoll CIER         LSECSSIE  LL_RCC_DisableIT_LSECSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
+}
+
+/**
+  * @brief  Checks if LSI ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         LSIRDYIE      LL_RCC_IsEnableIT_LSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSIRDY(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE)?1UL:0UL);
+}
+
+/**
+  * @brief  Checks if LSE ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         LSERDYIE      LL_RCC_IsEnableIT_LSERDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSERDY(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE)?1UL:0UL);
+}
+
+/**
+  * @brief  Checks if HSI ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         HSIRDYIE      LL_RCC_IsEnableIT_HSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSIRDY(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE)?1UL:0UL);
+}
+
+/**
+  * @brief  Checks if HSE ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         HSERDYIE      LL_RCC_IsEnableIT_HSERDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSERDY(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE)?1UL:0UL);
+}
+
+/**
+  * @brief  Checks if CSI ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         CSIRDYIE      LL_RCC_IsEnableIT_CSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_CSIRDY(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_CSIRDYIE) == RCC_CIER_CSIRDYIE)?1UL:0UL);
+}
+
+/**
+  * @brief  Checks if HSI48 ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         HSI48RDYIE      LL_RCC_IsEnableIT_HSI48RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSI48RDY(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == RCC_CIER_HSI48RDYIE)?1UL:0UL);
+}
+
+/**
+  * @brief  Checks if PLL1 ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         PLL1RDYIE      LL_RCC_IsEnableIT_PLL1RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL1RDY(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE) == RCC_CIER_PLL1RDYIE)?1UL:0UL);
+}
+
+/**
+  * @brief  Checks if PLL2 ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         PLL2RDYIE  LL_RCC_IsEnableIT_PLL2RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL2RDY(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE) == RCC_CIER_PLL2RDYIE)?1UL:0UL);
+}
+
+/**
+  * @brief  Checks if PLL3 ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         PLL3RDYIE  LL_RCC_IsEnableIT_PLL3RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL3RDY(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE) == RCC_CIER_PLL3RDYIE)?1UL:0UL);
+}
+
+/**
+  * @brief  Checks if LSECSS interrupt source is enabled or disabled.
+  * @rmtoll CIER         LSECSSIE  LL_RCC_IsEnableIT_LSECSS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSECSS(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == RCC_CIER_LSECSSIE)?1UL:0UL);
+}
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_EF_Init De-initialization function
+  * @{
+  */
+void LL_RCC_DeInit(void);
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
+  * @{
+  */
+uint32_t    LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t PQR);
+
+void        LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks);
+void        LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks);
+void        LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks);
+void        LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
+
+uint32_t    LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
+uint32_t    LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
+uint32_t    LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
+uint32_t    LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
+uint32_t    LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
+uint32_t    LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
+uint32_t    LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource);
+uint32_t    LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
+uint32_t    LL_RCC_GetCECClockFreq(uint32_t CECxSource);
+uint32_t    LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
+uint32_t    LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
+#if defined(DFSDM2_BASE)
+uint32_t    LL_RCC_GetDFSDM2ClockFreq(uint32_t DFSDMxSource);
+#endif /* DFSDM2 */
+#if defined(DSI)
+uint32_t    LL_RCC_GetDSIClockFreq(uint32_t DSIxSource);
+#endif /* DSI */
+uint32_t    LL_RCC_GetSPDIFClockFreq(uint32_t SPDIFxSource);
+uint32_t    LL_RCC_GetSPIClockFreq(uint32_t SPIxSource);
+uint32_t    LL_RCC_GetSWPClockFreq(uint32_t SWPxSource);
+uint32_t    LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource);
+uint32_t    LL_RCC_GetFMCClockFreq(uint32_t FMCxSource);
+#if defined(QUADSPI)
+uint32_t    LL_RCC_GetQSPIClockFreq(uint32_t QSPIxSource);
+#endif /* QUADSPI */
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+uint32_t    LL_RCC_GetOSPIClockFreq(uint32_t OSPIxSource);
+#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
+uint32_t    LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource);
+
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+#endif /* defined(RCC) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_LL_RCC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_system.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_system.h
new file mode 100644
index 00000000..77fc4ff5
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_system.h
@@ -0,0 +1,2274 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_system.h
+  * @author  MCD Application Team
+  * @brief   Header file of SYSTEM LL module.
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The LL SYSTEM driver contains a set of generic APIs that can be
+    used by user:
+      (+) Some of the FLASH features need to be handled in the SYSTEM file.
+      (+) Access to DBGCMU registers
+      (+) Access to SYSCFG registers
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32H7xx_LL_SYSTEM_H
+#define __STM32H7xx_LL_SYSTEM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)
+
+/** @defgroup SYSTEM_LL SYSTEM
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
+  * @{
+  */
+/** @defgroup SYSTEM_LL_EC_FLASH_BANK1_SECTORS SYSCFG Flash Bank1 sectors bits status
+  * @{
+  */
+#define LL_SYSCFG_FLASH_B1_SECTOR0_STATUS_BIT   0x10000U
+#define LL_SYSCFG_FLASH_B1_SECTOR1_STATUS_BIT   0x20000U
+#define LL_SYSCFG_FLASH_B1_SECTOR2_STATUS_BIT   0x40000U
+#define LL_SYSCFG_FLASH_B1_SECTOR3_STATUS_BIT   0x80000U
+#define LL_SYSCFG_FLASH_B1_SECTOR4_STATUS_BIT   0x100000U
+#define LL_SYSCFG_FLASH_B1_SECTOR5_STATUS_BIT   0x200000U
+#define LL_SYSCFG_FLASH_B1_SECTOR6_STATUS_BIT   0x400000U
+#define LL_SYSCFG_FLASH_B1_SECTOR7_STATUS_BIT   0x800000U
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_FLASH_BANK2_SECTORS SYSCFG Flash Bank2 sectors bits status
+  * @{
+  */
+#define LL_SYSCFG_FLASH_B2_SECTOR0_STATUS_BIT   0x10000U
+#define LL_SYSCFG_FLASH_B2_SECTOR1_STATUS_BIT   0x20000U
+#define LL_SYSCFG_FLASH_B2_SECTOR2_STATUS_BIT   0x40000U
+#define LL_SYSCFG_FLASH_B2_SECTOR3_STATUS_BIT   0x80000U
+#define LL_SYSCFG_FLASH_B2_SECTOR4_STATUS_BIT   0x100000U
+#define LL_SYSCFG_FLASH_B2_SECTOR5_STATUS_BIT   0x200000U
+#define LL_SYSCFG_FLASH_B2_SECTOR6_STATUS_BIT   0x400000U
+#define LL_SYSCFG_FLASH_B2_SECTOR7_STATUS_BIT   0x800000U
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
+  * @{
+  */
+
+/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
+  * @{
+  */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1        SYSCFG_PMCR_I2C1_FMP       /*!< Enable Fast Mode Plus for I2C1      */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2        SYSCFG_PMCR_I2C2_FMP       /*!< Enable Fast Mode Plus for I2C2      */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3        SYSCFG_PMCR_I2C3_FMP       /*!< Enable Fast Mode Plus for I2C3      */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4        SYSCFG_PMCR_I2C4_FMP       /*!< Enable Fast Mode Plus for I2C4      */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6         SYSCFG_PMCR_I2C_PB6_FMP    /*!< Enable Fast Mode Plus on PB6        */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7         SYSCFG_PMCR_I2C_PB7_FMP    /*!< Enable Fast Mode Plus on PB7        */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8         SYSCFG_PMCR_I2C_PB8_FMP    /*!< Enable Fast Mode Plus on PB8        */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9         SYSCFG_PMCR_I2C_PB9_FMP    /*!< Enable Fast Mode Plus on PB9        */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_ANALOG_SWITCH Analog Switch control
+* @{
+*/
+#define LL_SYSCFG_ANALOG_SWITCH_BOOSTEN           SYSCFG_PMCR_BOOSTEN               /*!< I/O analog switch voltage booster enable */
+#define LL_SYSCFG_ANALOG_SWITCH_PA0               SYSCFG_PMCR_PA0SO                 /*!< PA0 Switch Open */
+#define LL_SYSCFG_ANALOG_SWITCH_PA1               SYSCFG_PMCR_PA1SO                 /*!< PA1 Switch Open */
+#define LL_SYSCFG_ANALOG_SWITCH_PC2               SYSCFG_PMCR_PC2SO                 /*!< PC2 Switch Open */
+#define LL_SYSCFG_ANALOG_SWITCH_PC3               SYSCFG_PMCR_PC3SO                 /*!< PC3 Switch Open */
+/**
+  * @}
+  */
+
+#if defined(SYSCFG_PMCR_EPIS_SEL)
+/** @defgroup SYSTEM_LL_EC_EPIS Ethernet PHY Interface Selection
+* @{
+*/
+#define LL_SYSCFG_ETH_MII               0x00000000U                           /*!< ETH Media MII interface */
+#define LL_SYSCFG_ETH_RMII              SYSCFG_PMCR_EPIS_SEL                   /*!< ETH Media RMII interface */
+/**
+  * @}
+  */
+#endif /* SYSCFG_PMCR_EPIS_SEL */
+
+/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
+  * @{
+  */
+#define LL_SYSCFG_EXTI_PORTA               0U               /*!< EXTI PORT A                        */
+#define LL_SYSCFG_EXTI_PORTB               1U               /*!< EXTI PORT B                        */
+#define LL_SYSCFG_EXTI_PORTC               2U               /*!< EXTI PORT C                        */
+#define LL_SYSCFG_EXTI_PORTD               3U               /*!< EXTI PORT D                        */
+#define LL_SYSCFG_EXTI_PORTE               4U               /*!< EXTI PORT E                        */
+#define LL_SYSCFG_EXTI_PORTF               5U               /*!< EXTI PORT F                        */
+#define LL_SYSCFG_EXTI_PORTG               6U               /*!< EXTI PORT G                        */
+#define LL_SYSCFG_EXTI_PORTH               7U               /*!< EXTI PORT H                        */
+#define LL_SYSCFG_EXTI_PORTI               8U               /*!< EXTI PORT I                        */
+#define LL_SYSCFG_EXTI_PORTJ               9U               /*!< EXTI PORT J                        */
+#define LL_SYSCFG_EXTI_PORTK               10U              /*!< EXTI PORT k                        */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
+  * @{
+  */
+#define LL_SYSCFG_EXTI_LINE0               ((0x000FUL << 16U) | 0U)  /*!< EXTI_POSITION_0  | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE1               ((0x00F0UL << 16U) | 0U)  /*!< EXTI_POSITION_4  | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE2               ((0x0F00UL << 16U) | 0U)  /*!< EXTI_POSITION_8  | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE3               ((0xF000UL << 16U) | 0U)  /*!< EXTI_POSITION_12 | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE4               ((0x000FUL << 16U) | 1U)  /*!< EXTI_POSITION_0  | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE5               ((0x00F0UL << 16U) | 1U)  /*!< EXTI_POSITION_4  | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE6               ((0x0F00UL << 16U) | 1U)  /*!< EXTI_POSITION_8  | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE7               ((0xF000UL << 16U) | 1U)  /*!< EXTI_POSITION_12 | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE8               ((0x000FUL << 16U) | 2U)  /*!< EXTI_POSITION_0  | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE9               ((0x00F0UL << 16U) | 2U)  /*!< EXTI_POSITION_4  | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE10              ((0x0F00UL << 16U) | 2U)  /*!< EXTI_POSITION_8  | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE11              ((0xF000UL << 16U) | 2U)  /*!< EXTI_POSITION_12 | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE12              ((0x000FUL << 16U) | 3U)  /*!< EXTI_POSITION_0  | EXTICR[3] */
+#define LL_SYSCFG_EXTI_LINE13              ((0x00F0UL << 16U) | 3U)  /*!< EXTI_POSITION_4  | EXTICR[3] */
+#define LL_SYSCFG_EXTI_LINE14              ((0x0F00UL << 16U) | 3U)  /*!< EXTI_POSITION_8  | EXTICR[3] */
+#define LL_SYSCFG_EXTI_LINE15              ((0xF000UL << 16U) | 3U)  /*!< EXTI_POSITION_12 | EXTICR[3] */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
+  * @{
+  */
+#define LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC SYSCFG_CFGR_AXISRAML /*!< Enables and locks the AXIRAM double ECC error signal
+                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */
+
+#define LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC    SYSCFG_CFGR_ITCML    /*!< Enables and locks the ITCM double ECC error signal
+                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */
+
+#define LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC    SYSCFG_CFGR_DTCML    /*!< Enables and locks the DTCM double ECC error signal
+                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */
+
+#define LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC   SYSCFG_CFGR_SRAM1L   /*!< Enables and locks the SRAM1 double ECC error signal
+                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */
+
+#define LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC   SYSCFG_CFGR_SRAM2L   /*!< Enables and locks the SRAM2 double ECC error signal
+                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */
+
+#define LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC   SYSCFG_CFGR_SRAM3L   /*!< Enables and locks the SRAM3 double ECC error signal
+                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */
+
+#define LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC   SYSCFG_CFGR_SRAM4L   /*!< Enables and locks the SRAM4 double ECC error signal
+                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */
+
+#define LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC   SYSCFG_CFGR_BKRAML   /*!< Enables and locks the BKRAM double ECC error signal
+                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */
+
+#define LL_SYSCFG_TIMBREAK_CM7_LOCKUP      SYSCFG_CFGR_CM7L     /*!< Enables and locks the Cortex-M7 LOCKUP signal
+                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */
+
+#define LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC   SYSCFG_CFGR_FLASHL   /*!< Enables and locks the FLASH double ECC error signal
+                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */
+
+#define LL_SYSCFG_TIMBREAK_PVD             SYSCFG_CFGR_PVDL     /*!< Enables and locks the PVD connection
+                                                                     with TIM1/8/15/16/17 and HRTIM Break Input
+                                                                     and also the PVDE and PLS bits of the Power Control Interface */
+#if defined(DUAL_CORE)
+#define LL_SYSCFG_TIMBREAK_CM4_LOCKUP      SYSCFG_CFGR_CM4L     /*!< Enables and locks the Cortex-M4 LOCKUP signal
+                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */
+#endif /* DUAL_CORE */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_CS SYSCFG I/O compensation cell Code selection
+  * @{
+  */
+#define LL_SYSCFG_CELL_CODE               0U
+#define LL_SYSCFG_REGISTER_CODE           SYSCFG_CCCSR_CS
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_IWDG1_CONTROL_MODES SYSCFG IWDG1 control modes
+  * @{
+  */
+#define LL_SYSCFG_IWDG1_SW_CONTROL_MODE   0U
+#define LL_SYSCFG_IWDG1_HW_CONTROL_MODE   SYSCFG_UR11_IWDG1M
+/**
+  * @}
+  */
+
+#if defined (DUAL_CORE)
+/** @defgroup SYSTEM_LL_IWDG2_CONTROL_MODES SYSCFG IWDG2 control modes
+  * @{
+  */
+#define LL_SYSCFG_IWDG2_SW_CONTROL_MODE   0U
+#define LL_SYSCFG_IWDG2_HW_CONTROL_MODE   SYSCFG_UR12_IWDG2M
+/**
+  * @}
+  */
+#endif /* DUAL_CORE */
+
+/** @defgroup SYSTEM_LL_DTCM_RAM_SIZE SYSCFG DTCM RAM size configuration
+  * @{
+  */
+#define LL_SYSCFG_DTCM_RAM_SIZE_2KB     0U
+#define LL_SYSCFG_DTCM_RAM_SIZE_4KB     1U
+#define LL_SYSCFG_DTCM_RAM_SIZE_8KB     2U
+#define LL_SYSCFG_DTCM_RAM_SIZE_16KB    3U
+/**
+  * @}
+  */
+#ifdef SYSCFG_PKGR_PKG
+/** @defgroup SYSTEM_LL_PACKAGE SYSCFG device package
+  * @{
+  */
+#define LL_SYSCFG_LQFP100_PACKAGE             0U
+#define LL_SYSCFG_TQFP144_PACKAGE             2U
+#define LL_SYSCFG_TQFP176_UFBGA176_PACKAGE    5U
+#define LL_SYSCFG_LQFP208_TFBGA240_PACKAGE    8U
+/**
+  * @}
+  */
+#endif /* SYSCFG_PKGR_PKG */
+
+/** @defgroup SYSTEM_LL_SYSCFG_BOR SYSCFG Brownout Reset Threshold Level
+  * @{
+  */
+#define LL_SYSCFG_BOR_OFF_RESET_LEVEL      0x00000000U
+#define LL_SYSCFG_BOR_LOW_RESET_LEVEL      SYSCFG_UR2_BORH_0
+#define LL_SYSCFG_BOR_MEDIUM_RESET_LEVEL   SYSCFG_UR2_BORH_1
+#define LL_SYSCFG_BOR_HIGH_RESET_LEVEL     SYSCFG_UR2_BORH
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
+  * @{
+  */
+#define LL_DBGMCU_TRACE_NONE               0x00000000U                                     /*!< TRACE pins not assigned (default state) */
+#define LL_DBGMCU_TRACE_ASYNCH             DBGMCU_CR_TRACE_IOEN                            /*!< TRACE pin assignment for Asynchronous Mode */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE1        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE2        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE4        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)   /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
+  * @{
+  */
+#define LL_DBGMCU_APB1_GRP1_TIM2_STOP      DBGMCU_APB1LFZ1_DBG_TIM2     /*!< TIM2 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_TIM3_STOP      DBGMCU_APB1LFZ1_DBG_TIM3     /*!< TIM3 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_TIM4_STOP      DBGMCU_APB1LFZ1_DBG_TIM4     /*!< TIM4 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_TIM5_STOP      DBGMCU_APB1LFZ1_DBG_TIM5     /*!< TIM5 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_TIM6_STOP      DBGMCU_APB1LFZ1_DBG_TIM6     /*!< TIM6 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_TIM7_STOP      DBGMCU_APB1LFZ1_DBG_TIM7     /*!< TIM7 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_TIM12_STOP     DBGMCU_APB1LFZ1_DBG_TIM12    /*!< TIM12 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_TIM13_STOP     DBGMCU_APB1LFZ1_DBG_TIM13    /*!< TIM13 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_TIM14_STOP     DBGMCU_APB1LFZ1_DBG_TIM14    /*!< TIM14 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP    DBGMCU_APB1LFZ1_DBG_LPTIM1   /*!< LPTIM1 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_I2C1_STOP      DBGMCU_APB1LFZ1_DBG_I2C1     /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+#define LL_DBGMCU_APB1_GRP1_I2C2_STOP      DBGMCU_APB1LFZ1_DBG_I2C2     /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
+#define LL_DBGMCU_APB1_GRP1_I2C3_STOP      DBGMCU_APB1LFZ1_DBG_I2C3     /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
+  * @{
+  */
+#define LL_DBGMCU_APB1_GRP2_FDCAN_STOP    DBGMCU_APB1HFZ1_DBG_FDCAN    /*!< FDCAN is frozen while the core is in debug mode */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
+  * @{
+  */
+#define LL_DBGMCU_APB2_GRP1_TIM1_STOP      DBGMCU_APB2FZ1_DBG_TIM1    /*!< TIM1 counter stopped when core is halted */
+#define LL_DBGMCU_APB2_GRP1_TIM8_STOP      DBGMCU_APB2FZ1_DBG_TIM8    /*!< TIM8 counter stopped when core is halted */
+#define LL_DBGMCU_APB2_GRP1_TIM15_STOP     DBGMCU_APB2FZ1_DBG_TIM15   /*!< TIM15 counter stopped when core is halted */
+#define LL_DBGMCU_APB2_GRP1_TIM16_STOP     DBGMCU_APB2FZ1_DBG_TIM16   /*!< TIM16 counter stopped when core is halted */
+#define LL_DBGMCU_APB2_GRP1_TIM17_STOP     DBGMCU_APB2FZ1_DBG_TIM17   /*!< TIM17 counter stopped when core is halted */
+#define LL_DBGMCU_APB2_GRP1_HRTIM_STOP     DBGMCU_APB2FZ1_DBG_HRTIM   /*!< HRTIM counter stopped when core is halted */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_APB3_GRP1_STOP_IP DBGMCU APB3 GRP1 STOP IP
+  * @{
+  */
+#define LL_DBGMCU_APB3_GRP1_WWDG1_STOP      DBGMCU_APB3FZ1_DBG_WWDG1   /*!< WWDG1 is frozen while the core is in debug mode */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_APB4_GRP1_STOP_IP DBGMCU APB4 GRP1 STOP IP
+  * @{
+  */
+#define LL_DBGMCU_APB4_GRP1_I2C4_STOP       DBGMCU_APB4FZ1_DBG_I2C4     /*!< I2C4 is frozen while the core is in debug mode */
+#define LL_DBGMCU_APB4_GRP1_LPTIM2_STOP     DBGMCU_APB4FZ1_DBG_LPTIM2   /*!< LPTIM2 is frozen while the core is in debug mode */
+#define LL_DBGMCU_APB4_GRP1_LPTIM3_STOP     DBGMCU_APB4FZ1_DBG_LPTIM3   /*!< LPTIM3 is frozen while the core is in debug mode */
+#define LL_DBGMCU_APB4_GRP1_LPTIM4_STOP     DBGMCU_APB4FZ1_DBG_LPTIM4   /*!< LPTIM4 is frozen while the core is in debug mode */
+#define LL_DBGMCU_APB4_GRP1_LPTIM5_STOP     DBGMCU_APB4FZ1_DBG_LPTIM5   /*!< LPTIM5 is frozen while the core is in debug mode */
+#define LL_DBGMCU_APB4_GRP1_RTC_STOP        DBGMCU_APB4FZ1_DBG_RTC      /*!< RTC is frozen while the core is in debug mode */
+#define LL_DBGMCU_APB4_GRP1_IWDG1_STOP      DBGMCU_APB4FZ1_DBG_IWDG1    /*!< IWDG1 is frozen while the core is in debug mode */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
+  * @{
+  */
+#define LL_FLASH_LATENCY_0                 FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero wait state */
+#define LL_FLASH_LATENCY_1                 FLASH_ACR_LATENCY_1WS   /*!< FLASH One wait state */
+#define LL_FLASH_LATENCY_2                 FLASH_ACR_LATENCY_2WS   /*!< FLASH Two wait states */
+#define LL_FLASH_LATENCY_3                 FLASH_ACR_LATENCY_3WS   /*!< FLASH Three wait states */
+#define LL_FLASH_LATENCY_4                 FLASH_ACR_LATENCY_4WS   /*!< FLASH Four wait states */
+#define LL_FLASH_LATENCY_5                 FLASH_ACR_LATENCY_5WS   /*!< FLASH five wait state */
+#define LL_FLASH_LATENCY_6                 FLASH_ACR_LATENCY_6WS   /*!< FLASH six wait state */
+#define LL_FLASH_LATENCY_7                 FLASH_ACR_LATENCY_7WS   /*!< FLASH seven wait states */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
+  * @{
+  */
+
+/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
+  * @{
+  */
+
+#if defined(SYSCFG_PMCR_EPIS_SEL)
+/**
+  * @brief  Select Ethernet PHY interface
+  * @rmtoll PMCR    EPIS_SEL    LL_SYSCFG_SetPHYInterface
+  * @param  Interface This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_ETH_MII
+  *         @arg @ref LL_SYSCFG_ETH_RMII
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface)
+{
+  MODIFY_REG(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL, Interface);
+}
+
+/**
+  * @brief  Get Ethernet PHY interface
+  * @rmtoll PMCR    EPIS_SEL    LL_SYSCFG_GetPHYInterface
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_ETH_MII
+  *         @arg @ref LL_SYSCFG_ETH_RMII
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL));
+}
+
+#endif /* SYSCFG_PMCR_EPIS_SEL */
+/**
+  * @brief  Open an Analog Switch
+  * @rmtoll PMCR    PA0SO   LL_SYSCFG_OpenAnalogSwitch
+  * @rmtoll PMCR    PA1SO   LL_SYSCFG_OpenAnalogSwitch
+  * @rmtoll PMCR    PC2SO   LL_SYSCFG_OpenAnalogSwitch
+  * @rmtoll PMCR    PC3SO   LL_SYSCFG_OpenAnalogSwitch
+  * @param  AnalogSwitch This parameter can be one of the following values:
+  *         @arg LL_SYSCFG_ANALOG_SWITCH_PA0 : PA0 analog switch
+  *         @arg LL_SYSCFG_ANALOG_SWITCH_PA1:  PA1 analog switch
+  *         @arg LL_SYSCFG_ANALOG_SWITCH_PC2 : PC2 analog switch
+  *         @arg LL_SYSCFG_ANALOG_SWITCH_PC3:  PC3 analog switch
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_OpenAnalogSwitch(uint32_t AnalogSwitch)
+{
+  SET_BIT(SYSCFG->PMCR, AnalogSwitch);
+}
+
+/**
+  * @brief  Close an Analog Switch
+  * @rmtoll PMCR    PA0SO   LL_SYSCFG_CloseAnalogSwitch
+  * @rmtoll PMCR    PA1SO   LL_SYSCFG_CloseAnalogSwitch
+  * @rmtoll PMCR    PC2SO   LL_SYSCFG_CloseAnalogSwitch
+  * @rmtoll PMCR    PC3SO   LL_SYSCFG_CloseAnalogSwitch
+  * @param  AnalogSwitch This parameter can be one of the following values:
+  *         @arg LL_SYSCFG_ANALOG_SWITCH_PA0 : PA0 analog switch
+  *         @arg LL_SYSCFG_ANALOG_SWITCH_PA1:  PA1 analog switch
+  *         @arg LL_SYSCFG_ANALOG_SWITCH_PC2 : PC2 analog switch
+  *         @arg LL_SYSCFG_ANALOG_SWITCH_PC3:  PC3 analog switch
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_CloseAnalogSwitch(uint32_t AnalogSwitch)
+{
+  CLEAR_BIT(SYSCFG->PMCR, AnalogSwitch);
+}
+#ifdef SYSCFG_PMCR_BOOSTEN
+/**
+  * @brief  Enable the Analog booster to reduce the total harmonic distortion
+  *         of the analog switch when the supply voltage is lower than 2.7 V
+  * @rmtoll PMCR    BOOSTEN   LL_SYSCFG_EnableAnalogBooster
+  * @note   Activating the booster allows to guaranty the analog switch AC performance
+  *         when the supply voltage is below 2.7 V: in this case, the analog switch
+  *         performance is the same on the full voltage range
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)
+{
+ SET_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
+}
+
+/**
+  * @brief  Disable the Analog booster
+  * @rmtoll PMCR    BOOSTEN   LL_SYSCFG_DisableAnalogBooster
+  * @note   Activating the booster allows to guaranty the analog switch AC performance
+  *         when the supply voltage is below 2.7 V: in this case, the analog switch
+  *         performance is the same on the full voltage range
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
+{
+ CLEAR_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
+}
+#endif /*SYSCFG_PMCR_BOOSTEN*/
+/**
+  * @brief  Enable the I2C fast mode plus driving capability.
+  * @rmtoll SYSCFG_PMCR   I2C_PBx_FMP   LL_SYSCFG_EnableFastModePlus\n
+  *         SYSCFG_PMCR   I2Cx_FMP      LL_SYSCFG_EnableFastModePlus
+  * @param  ConfigFastModePlus This parameter can be a combination of the following values:
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4(*)
+  *
+  *         (*) value not defined in all devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
+{
+  SET_BIT(SYSCFG->PMCR, ConfigFastModePlus);
+}
+
+/**
+  * @brief  Disable the I2C fast mode plus driving capability.
+  * @rmtoll SYSCFG_PMCR    I2C_PBx_FMP   LL_SYSCFG_DisableFastModePlus\n
+  *         SYSCFG_PMCR    I2Cx_FMP      LL_SYSCFG_DisableFastModePlus
+  * @param  ConfigFastModePlus This parameter can be a combination of the following values:
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4
+  *         (*) value not defined in all devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
+{
+  CLEAR_BIT(SYSCFG->PMCR, ConfigFastModePlus);
+}
+
+/**
+  * @brief  Configure source input for the EXTI external interrupt.
+  * @rmtoll SYSCFG_EXTICR1  EXTIx         LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR2 EXTIx         LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR3 EXTIx         LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR4 EXTIx         LL_SYSCFG_SetEXTISource
+  * @param  Port This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_EXTI_PORTA
+  *         @arg @ref LL_SYSCFG_EXTI_PORTB
+  *         @arg @ref LL_SYSCFG_EXTI_PORTC
+  *         @arg @ref LL_SYSCFG_EXTI_PORTD
+  *         @arg @ref LL_SYSCFG_EXTI_PORTE
+  *         @arg @ref LL_SYSCFG_EXTI_PORTF
+  *         @arg @ref LL_SYSCFG_EXTI_PORTG
+  *         @arg @ref LL_SYSCFG_EXTI_PORTH
+  *         @arg @ref LL_SYSCFG_EXTI_PORTI
+  *         @arg @ref LL_SYSCFG_EXTI_PORTJ
+  *         @arg @ref LL_SYSCFG_EXTI_PORTK
+  *
+  *         (*) value not defined in all devices
+  * @param  Line This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_EXTI_LINE0
+  *         @arg @ref LL_SYSCFG_EXTI_LINE1
+  *         @arg @ref LL_SYSCFG_EXTI_LINE2
+  *         @arg @ref LL_SYSCFG_EXTI_LINE3
+  *         @arg @ref LL_SYSCFG_EXTI_LINE4
+  *         @arg @ref LL_SYSCFG_EXTI_LINE5
+  *         @arg @ref LL_SYSCFG_EXTI_LINE6
+  *         @arg @ref LL_SYSCFG_EXTI_LINE7
+  *         @arg @ref LL_SYSCFG_EXTI_LINE8
+  *         @arg @ref LL_SYSCFG_EXTI_LINE9
+  *         @arg @ref LL_SYSCFG_EXTI_LINE10
+  *         @arg @ref LL_SYSCFG_EXTI_LINE11
+  *         @arg @ref LL_SYSCFG_EXTI_LINE12
+  *         @arg @ref LL_SYSCFG_EXTI_LINE13
+  *         @arg @ref LL_SYSCFG_EXTI_LINE14
+  *         @arg @ref LL_SYSCFG_EXTI_LINE15
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
+{
+  MODIFY_REG(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U), Port << ((POSITION_VAL(Line >> 16U)) & 31U));
+}
+
+/**
+  * @brief  Get the configured defined for specific EXTI Line
+  * @rmtoll SYSCFG_EXTICR1 EXTIx         LL_SYSCFG_GetEXTISource\n
+  *         SYSCFG_EXTICR2 EXTIx         LL_SYSCFG_GetEXTISource\n
+  *         SYSCFG_EXTICR3 EXTIx         LL_SYSCFG_GetEXTISource\n
+  *         SYSCFG_EXTICR4 EXTIx         LL_SYSCFG_GetEXTISource
+  * @param  Line This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_EXTI_LINE0
+  *         @arg @ref LL_SYSCFG_EXTI_LINE1
+  *         @arg @ref LL_SYSCFG_EXTI_LINE2
+  *         @arg @ref LL_SYSCFG_EXTI_LINE3
+  *         @arg @ref LL_SYSCFG_EXTI_LINE4
+  *         @arg @ref LL_SYSCFG_EXTI_LINE5
+  *         @arg @ref LL_SYSCFG_EXTI_LINE6
+  *         @arg @ref LL_SYSCFG_EXTI_LINE7
+  *         @arg @ref LL_SYSCFG_EXTI_LINE8
+  *         @arg @ref LL_SYSCFG_EXTI_LINE9
+  *         @arg @ref LL_SYSCFG_EXTI_LINE10
+  *         @arg @ref LL_SYSCFG_EXTI_LINE11
+  *         @arg @ref LL_SYSCFG_EXTI_LINE12
+  *         @arg @ref LL_SYSCFG_EXTI_LINE13
+  *         @arg @ref LL_SYSCFG_EXTI_LINE14
+  *         @arg @ref LL_SYSCFG_EXTI_LINE15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_EXTI_PORTA
+  *         @arg @ref LL_SYSCFG_EXTI_PORTB
+  *         @arg @ref LL_SYSCFG_EXTI_PORTC
+  *         @arg @ref LL_SYSCFG_EXTI_PORTD
+  *         @arg @ref LL_SYSCFG_EXTI_PORTE
+  *         @arg @ref LL_SYSCFG_EXTI_PORTF
+  *         @arg @ref LL_SYSCFG_EXTI_PORTG
+  *         @arg @ref LL_SYSCFG_EXTI_PORTH
+  *         @arg @ref LL_SYSCFG_EXTI_PORTI
+  *         @arg @ref LL_SYSCFG_EXTI_PORTJ
+  *         @arg @ref LL_SYSCFG_EXTI_PORTK
+  *         (*) value not defined in all devices
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U)) >> (POSITION_VAL(Line >> 16U) & 31U));
+}
+
+/**
+  * @brief  Set connections to TIM1/8/15/16/17 and HRTIM Break inputs
+  * @note this feature is available on STM32H7 rev.B and above
+  * @rmtoll SYSCFG_CFGR AXISRAML       LL_SYSCFG_SetTIMBreakInputs\n
+  *         SYSCFG_CFGR ITCML          LL_SYSCFG_SetTIMBreakInputs\n
+  *         SYSCFG_CFGR DTCML          LL_SYSCFG_SetTIMBreakInputs\n
+  *         SYSCFG_CFGR SRAM1L         LL_SYSCFG_SetTIMBreakInputs\n
+  *         SYSCFG_CFGR SRAM2L         LL_SYSCFG_SetTIMBreakInputs\n
+  *         SYSCFG_CFGR SRAM3L         LL_SYSCFG_SetTIMBreakInputs\n
+  *         SYSCFG_CFGR SRAM4L         LL_SYSCFG_SetTIMBreakInputs\n
+  *         SYSCFG_CFGR BKRAML         LL_SYSCFG_SetTIMBreakInputs\n
+  *         SYSCFG_CFGR CM7L           LL_SYSCFG_SetTIMBreakInputs\n
+  *         SYSCFG_CFGR FLASHL         LL_SYSCFG_SetTIMBreakInputs\n
+  *         SYSCFG_CFGR PVDL           LL_SYSCFG_SetTIMBreakInputs\n
+  *         SYSCFG_CFGR_CM4L           LL_SYSCFG_SetTIMBreakInputs
+  * @param  Break This parameter can be a combination of the following values:
+  *         @arg @ref LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_CM7_LOCKUP
+  *         @arg @ref LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_PVD
+  *         @arg @ref LL_SYSCFG_TIMBREAK_CM4_LOCKUP (available for dual core lines only)
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
+{
+#if defined(DUAL_CORE)
+  MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML  | SYSCFG_CFGR_DTCML  | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \
+                           SYSCFG_CFGR_SRAM3L   | SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L   | SYSCFG_CFGR_FLASHL | \
+                           SYSCFG_CFGR_PVDL     | SYSCFG_CFGR_CM4L, Break);
+#elif defined (SYSCFG_CFGR_AXISRAML)
+  MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML  | SYSCFG_CFGR_DTCML  | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \
+                           SYSCFG_CFGR_SRAM3L   | SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L   | SYSCFG_CFGR_FLASHL | \
+                           SYSCFG_CFGR_PVDL, Break);
+#else
+  MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_ITCML  | SYSCFG_CFGR_DTCML  |\
+                           SYSCFG_CFGR_CM7L   | SYSCFG_CFGR_FLASHL | \
+                           SYSCFG_CFGR_PVDL, Break);
+#endif /* DUAL_CORE */
+}
+
+/**
+  * @brief  Get connections to TIM1/8/15/16/17 and HRTIM Break inputs
+  * @note this feature is available on STM32H7 rev.B and above
+  * @rmtoll SYSCFG_CFGR AXISRAML       LL_SYSCFG_GetTIMBreakInputs\n
+  *         SYSCFG_CFGR ITCML          LL_SYSCFG_GetTIMBreakInputs\n
+  *         SYSCFG_CFGR DTCML          LL_SYSCFG_GetTIMBreakInputs\n
+  *         SYSCFG_CFGR SRAM1L         LL_SYSCFG_GetTIMBreakInputs\n
+  *         SYSCFG_CFGR SRAM2L         LL_SYSCFG_GetTIMBreakInputs\n
+  *         SYSCFG_CFGR SRAM3L         LL_SYSCFG_GetTIMBreakInputs\n
+  *         SYSCFG_CFGR SRAM4L         LL_SYSCFG_GetTIMBreakInputs\n
+  *         SYSCFG_CFGR BKRAML         LL_SYSCFG_GetTIMBreakInputs\n
+  *         SYSCFG_CFGR CM7L           LL_SYSCFG_GetTIMBreakInputs\n
+  *         SYSCFG_CFGR FLASHL         LL_SYSCFG_GetTIMBreakInputs\n
+  *         SYSCFG_CFGR PVDL           LL_SYSCFG_GetTIMBreakInputs\n
+  *         SYSCFG_CFGR_CM4L           LL_SYSCFG_GetTIMBreakInputs
+  * @retval Returned value can be can be a combination of the following values:
+  *         @arg @ref LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_CM7_LOCKUP
+  *         @arg @ref LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_PVD
+  *         @arg @ref LL_SYSCFG_TIMBREAK_CM4_LOCKUP (available for dual core lines only)
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
+{
+#if defined(DUAL_CORE)
+  return (uint32_t)(READ_BIT(SYSCFG->CFGR,  SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML  | SYSCFG_CFGR_DTCML  | \
+                                            SYSCFG_CFGR_SRAM1L   | SYSCFG_CFGR_SRAM2L | SYSCFG_CFGR_SRAM3L | \
+                                            SYSCFG_CFGR_SRAM4L   | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L   | \
+                                            SYSCFG_CFGR_FLASHL   | SYSCFG_CFGR_PVDL   | SYSCFG_CFGR_CM4L));
+#elif defined (SYSCFG_CFGR_AXISRAML)
+  return (uint32_t)(READ_BIT(SYSCFG->CFGR,  SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML  | SYSCFG_CFGR_DTCML  | \
+                                            SYSCFG_CFGR_SRAM1L   | SYSCFG_CFGR_SRAM2L | SYSCFG_CFGR_SRAM3L | \
+                                            SYSCFG_CFGR_SRAM4L   | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L   | \
+                                            SYSCFG_CFGR_FLASHL   | SYSCFG_CFGR_PVDL ));
+#else
+  return (uint32_t)(READ_BIT(SYSCFG->CFGR,  SYSCFG_CFGR_ITCML    | SYSCFG_CFGR_DTCML  | SYSCFG_CFGR_CM7L   | \
+                                            SYSCFG_CFGR_FLASHL   | SYSCFG_CFGR_PVDL ));
+#endif /* DUAL_CORE */
+}
+
+/**
+  * @brief  Enable the Compensation Cell
+  * @rmtoll CCCSR   EN    LL_SYSCFG_EnableCompensationCell
+  * @note   The I/O compensation cell can be used only when the device supply
+  *         voltage ranges from 2.4 to 3.6 V
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void)
+{
+  SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN);
+}
+
+/**
+  * @brief  Disable the Compensation Cell
+  * @rmtoll CCCSR   EN    LL_SYSCFG_DisableCompensationCell
+  * @note   The I/O compensation cell can be used only when the device supply
+  *         voltage ranges from 2.4 to 3.6 V
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void)
+{
+  CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN);
+}
+
+/**
+  * @brief  Check if the Compensation Cell is enabled
+  * @rmtoll CCCSR   EN    LL_SYSCFG_IsEnabledCompensationCell
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledCompensationCell(void)
+{
+  return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN) == SYSCFG_CCCSR_EN) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Compensation Cell ready Flag
+  * @rmtoll CCCSR   READY   LL_SYSCFG_IsActiveFlag_CMPCR
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void)
+{
+  return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_READY) == (SYSCFG_CCCSR_READY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the I/O speed optimization when the product voltage is low.
+  * @rmtoll CCCSR   HSLV    LL_SYSCFG_EnableIOSpeedOptimize
+  * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the
+  *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
+  *         might be destructive.
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization(void)
+{
+#if defined(SYSCFG_CCCSR_HSLV)
+  SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);
+#else
+  SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0);
+#endif   /* SYSCFG_CCCSR_HSLV */
+}
+
+#if defined(SYSCFG_CCCSR_HSLV1)
+/**
+  * @brief  Enable the I/O speed optimization when the product voltage is low.
+  * @rmtoll CCCSR   HSLV1    LL_SYSCFG_EnableIOSpeedOptimize
+  * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the
+  *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
+  *         might be destructive.
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization1(void)
+{
+  SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1);
+}
+
+/**
+  * @brief  Enable the I/O speed optimization when the product voltage is low.
+  * @rmtoll CCCSR   HSLV2    LL_SYSCFG_EnableIOSpeedOptimize
+  * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the
+  *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
+  *         might be destructive.
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization2(void)
+{
+  SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2);
+}
+
+/**
+  * @brief  Enable the I/O speed optimization when the product voltage is low.
+  * @rmtoll CCCSR   HSLV3    LL_SYSCFG_EnableIOSpeedOptimize
+  * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the
+  *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
+  *         might be destructive.
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization3(void)
+{
+  SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3);
+}
+#endif /*SYSCFG_CCCSR_HSLV1*/
+
+
+/**
+  * @brief  To Disable optimize the I/O speed when the product voltage is low.
+  * @rmtoll CCCSR   HSLV    LL_SYSCFG_DisableIOSpeedOptimize
+  * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the
+  *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
+  *         might be destructive.
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization(void)
+{
+#if defined(SYSCFG_CCCSR_HSLV)
+  CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);
+#else
+  CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0);
+#endif   /* SYSCFG_CCCSR_HSLV */
+}
+
+#if defined(SYSCFG_CCCSR_HSLV1)
+/**
+  * @brief  To Disable optimize the I/O speed when the product voltage is low.
+  * @rmtoll CCCSR   HSLV1    LL_SYSCFG_DisableIOSpeedOptimize
+  * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the
+  *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
+  *         might be destructive.
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization1(void)
+{
+  CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1);
+}
+
+/**
+  * @brief  To Disable optimize the I/O speed when the product voltage is low.
+  * @rmtoll CCCSR   HSLV2    LL_SYSCFG_DisableIOSpeedOptimize
+  * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the
+  *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
+  *         might be destructive.
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization2(void)
+{
+  CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2);
+}
+
+/**
+  * @brief  To Disable optimize the I/O speed when the product voltage is low.
+  * @rmtoll CCCSR   HSLV3    LL_SYSCFG_DisableIOSpeedOptimize
+  * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the
+  *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
+  *         might be destructive.
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization3(void)
+{
+  CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3);
+}
+#endif /*SYSCFG_CCCSR_HSLV1*/
+
+/**
+  * @brief  Check if the I/O speed optimization is enabled
+  * @rmtoll CCCSR   HSLV    LL_SYSCFG_IsEnabledIOSpeedOptimization
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization(void)
+{
+#if defined(SYSCFG_CCCSR_HSLV)
+  return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV) == SYSCFG_CCCSR_HSLV) ? 1UL : 0UL);
+#else
+  return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0) == SYSCFG_CCCSR_HSLV0) ? 1UL : 0UL);
+#endif /*SYSCFG_CCCSR_HSLV*/
+}
+
+#if defined(SYSCFG_CCCSR_HSLV1)
+/**
+  * @brief  Check if the I/O speed optimization is enabled
+  * @rmtoll CCCSR   HSLV1    LL_SYSCFG_IsEnabledIOSpeedOptimization
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization1(void)
+{
+  return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1) == SYSCFG_CCCSR_HSLV1) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the I/O speed optimization is enabled
+  * @rmtoll CCCSR   HSLV2    LL_SYSCFG_IsEnabledIOSpeedOptimization
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization2(void)
+{
+  return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2) == SYSCFG_CCCSR_HSLV2) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the I/O speed optimization is enabled
+  * @rmtoll CCCSR   HSLV3    LL_SYSCFG_IsEnabledIOSpeedOptimization
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization3(void)
+{
+  return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3) == SYSCFG_CCCSR_HSLV3) ? 1UL : 0UL);
+}
+#endif /*SYSCFG_CCCSR_HSLV1*/
+
+/**
+  * @brief  Set the code selection for the I/O Compensation cell
+  * @rmtoll CCCSR   CS    LL_SYSCFG_SetCellCompensationCode
+  * @param  CompCode: Selects the code to be applied for the I/O compensation cell
+  *   This parameter can be one of the following values:
+  *   @arg LL_SYSCFG_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR)
+  *   @arg LL_SYSCFG_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR)
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetCellCompensationCode(uint32_t CompCode)
+{
+  SET_BIT(SYSCFG->CCCSR, CompCode);
+}
+
+/**
+  * @brief  Get the code selected for the I/O Compensation cell
+  * @rmtoll CCCSR   CS    LL_SYSCFG_GetCellCompensationCode
+  * @retval Returned value can be one of the following values:
+  *   @arg LL_SYSCFG_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR)
+  *   @arg LL_SYSCFG_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register (SYSCFG_CCCR)
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetCellCompensationCode(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS));
+}
+
+#ifdef SYSCFG_CCCSR_CS_MMC
+
+/**
+  * @brief  Get the code selected for the I/O Compensation cell on the VDDMMC power rail
+  * @rmtoll CCCSR   CS    LL_SYSCFG_GetCellCompensationCode
+  * @retval Returned value can be one of the following values:
+  *   @arg LL_SYSCFG_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR)
+  *   @arg LL_SYSCFG_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register (SYSCFG_CCCR)
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_MMCGetCellCompensationCode(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS_MMC));
+}
+#endif /*SYSCFG_CCCSR_CS_MMC*/
+
+/**
+  * @brief  Get I/O compensation cell value for PMOS transistors
+  * @rmtoll CCVR    PCV   LL_SYSCFG_GetPMOSCompensationValue
+  * @retval Returned value is the I/O compensation cell value for PMOS transistors
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSCompensationValue(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_PCV));
+}
+
+/**
+  * @brief  Get I/O compensation cell value for NMOS transistors
+  * @rmtoll CCVR    NCV   LL_SYSCFG_GetNMOSCompensationValue
+  * @retval Returned value is the I/O compensation cell value for NMOS transistors
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSCompensationValue(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_NCV));
+}
+
+/**
+  * @brief  Set I/O compensation cell code for PMOS transistors
+  * @rmtoll CCCR    PCC   LL_SYSCFG_SetPMOSCompensationCode
+  * @param  PMOSCode PMOS compensation code
+  *         This code is applied to the I/O compensation cell when the CS bit of the
+  *         SYSCFG_CMPCR is set
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetPMOSCompensationCode(uint32_t PMOSCode)
+{
+  MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC, PMOSCode);
+}
+
+/**
+  * @brief  Get I/O compensation cell code for PMOS transistors
+  * @rmtoll CCCR    PCC   LL_SYSCFG_GetPMOSCompensationCode
+  * @retval Returned value is the I/O compensation cell code for PMOS transistors
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSCompensationCode(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC));
+}
+
+#ifdef SYSCFG_CCCR_PCC_MMC
+
+/**
+  * @brief  Set I/O compensation cell code for PMOS transistors corresponding to the VDDMMC power rail
+  * @rmtoll CCCR    PCC   LL_SYSCFG_SetPMOSCompensationCode
+  * @param  PMOSCode PMOS compensation code
+  *         This code is applied to the I/O compensation cell when the CS bit of the
+  *         SYSCFG_CMPCR is set
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_MMCSetPMOSCompensationCode(uint32_t PMOSCode)
+{
+  MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC_MMC, PMOSCode);
+}
+
+/**
+  * @brief  Get I/O compensation cell code for PMOS transistors corresponding to the VDDMMC power rail
+  * @rmtoll CCCR    PCC   LL_SYSCFG_GetPMOSCompensationCode
+  * @retval Returned value is the I/O compensation cell code for PMOS transistors
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_MMCGetPMOSCompensationCode(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC_MMC));
+}
+#endif /* SYSCFG_CCCR_PCC_MMC */
+
+/**
+  * @brief  Set I/O compensation cell code for NMOS transistors
+  * @rmtoll CCCR    NCC   LL_SYSCFG_SetNMOSCompensationCode
+  * @param  NMOSCode NMOS compensation code
+  *         This code is applied to the I/O compensation cell when the CS bit of the
+  *         SYSCFG_CMPCR is set
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetNMOSCompensationCode(uint32_t NMOSCode)
+{
+  MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC, NMOSCode);
+}
+
+/**
+  * @brief  Get I/O compensation cell code for NMOS transistors
+  * @rmtoll CCCR    NCC   LL_SYSCFG_GetNMOSCompensationCode
+  * @retval Returned value is the I/O compensation cell code for NMOS transistors
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSCompensationCode(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC));
+}
+
+#ifdef SYSCFG_CCCR_NCC_MMC
+
+/**
+  * @brief  Set I/O compensation cell code for NMOS transistors on the VDDMMC power rail.
+  * @rmtoll CCCR    NCC   LL_SYSCFG_SetNMOSCompensationCode
+  * @param  NMOSCode: NMOS compensation code
+  *         This code is applied to the I/O compensation cell when the CS bit of the
+  *         SYSCFG_CMPCR is set
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_VDMMCSetNMOSCompensationCode(uint32_t NMOSCode)
+{
+  MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC_MMC, NMOSCode);
+}
+
+/**
+  * @brief  Get I/O compensation cell code for NMOS transistors on the VDDMMC power rail.
+  * @rmtoll CCCR    NCC   LL_SYSCFG_GetNMOSCompensationCode
+  * @retval Returned value is the I/O compensation cell code for NMOS transistors
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_VDMMCGetNMOSCompensationCode(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC_MMC));
+}
+#endif /*SYSCFG_CCCR_NCC_MMC*/
+
+#ifdef SYSCFG_PKGR_PKG
+/**
+  * @brief  Get the device package
+  * @rmtoll PKGR    PKG   LL_SYSCFG_GetPackage
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_LQFP100_PACKAGE
+  *         @arg @ref LL_SYSCFG_TQFP144_PACKAGE
+  *         @arg @ref LL_SYSCFG_TQFP176_UFBGA176_PACKAGE
+  *         @arg @ref LL_SYSCFG_LQFP208_TFBGA240_PACKAGE
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetPackage(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->PKGR, SYSCFG_PKGR_PKG));
+}
+#endif /*SYSCFG_PKGR_PKG*/
+
+#ifdef SYSCFG_UR0_RDP
+/**
+  * @brief  Get the Flash memory protection level
+  * @rmtoll UR0   RDP   LL_SYSCFG_GetFLashProtectionLevel
+  * @retval Returned value can be one of the following values:
+  *         0xAA : RDP level 0
+  *         0xCC : RDP level 2
+  *         Any other value : RDP level 1
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetFLashProtectionLevel(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->UR0, SYSCFG_UR0_RDP));
+}
+/**
+  * @brief  Indicate if the Flash memory bank addresses are inverted or not
+  * @rmtoll UR0   BKS   LL_SYSCFG_IsFLashBankAddressesSwaped
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFLashBankAddressesSwaped(void)
+{
+  return ((READ_BIT(SYSCFG->UR0, SYSCFG_UR0_BKS) == 0U) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get the BOR Threshold Reset Level
+  * @rmtoll UR2   BORH    LL_SYSCFG_GetBrownoutResetLevel
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_BOR_HIGH_RESET_LEVEL
+  *         @arg @ref LL_SYSCFG_BOR_MEDIUM_RESET_LEVEL
+  *         @arg @ref LL_SYSCFG_BOR_LOW_RESET_LEVEL
+  *         @arg @ref LL_SYSCFG_BOR_OFF_RESET_LEVEL
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetBrownoutResetLevel(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BORH));
+}
+/**
+  * @brief  BootCM7 address 0 configuration
+  * @rmtoll UR2   BOOT_ADD0   LL_SYSCFG_SetCM7BootAddress0
+  * @param  BootAddress :Specifies the CM7 Boot Address to be loaded in Address0
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetCM7BootAddress0(uint16_t BootAddress)
+{
+  /* Configure CM7 BOOT ADD0 */
+#if defined(DUAL_CORE)
+  MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0, ((uint32_t)BootAddress << SYSCFG_UR2_BCM7_ADD0_Pos));
+#else
+  MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0, ((uint32_t)BootAddress << SYSCFG_UR2_BOOT_ADD0_Pos));
+#endif /*DUAL_CORE*/
+
+}
+
+/**
+  * @brief  Get BootCM7 address 0
+  * @rmtoll UR2   BOOT_ADD0   LL_SYSCFG_GetCM7BootAddress0
+  * @retval Returned the CM7 Boot Address0
+  */
+__STATIC_INLINE uint16_t LL_SYSCFG_GetCM7BootAddress0(void)
+{
+  /* Get CM7 BOOT ADD0 */
+#if defined(DUAL_CORE)
+  return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0) >> SYSCFG_UR2_BCM7_ADD0_Pos);
+#else
+  return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0) >> SYSCFG_UR2_BOOT_ADD0_Pos);
+#endif /*DUAL_CORE*/
+}
+
+/**
+  * @brief  BootCM7 address 1 configuration
+  * @rmtoll UR3   BOOT_ADD1   LL_SYSCFG_SetCM7BootAddress1
+  * @param  BootAddress :Specifies the CM7 Boot Address to be loaded in Address1
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetCM7BootAddress1(uint16_t BootAddress)
+{
+  /* Configure CM7 BOOT ADD1 */
+#if defined(DUAL_CORE)
+  MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1, BootAddress);
+#else
+  MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1, BootAddress);
+#endif /*DUAL_CORE*/
+}
+
+/**
+  * @brief  Get BootCM7 address 1
+  * @rmtoll UR3   BOOT_ADD1   LL_SYSCFG_GetCM7BootAddress1
+  * @retval Returned the CM7 Boot Address0
+  */
+__STATIC_INLINE uint16_t LL_SYSCFG_GetCM7BootAddress1(void)
+{
+  /* Get CM7 BOOT ADD0 */
+#if defined(DUAL_CORE)
+  return (uint16_t)(READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1));
+#else
+  return (uint16_t)(READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1));
+#endif /* DUAL_CORE */
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  BootCM4 address 0 configuration
+  * @rmtoll UR3   BCM4_ADD0   LL_SYSCFG_SetCM4BootAddress0
+  * @param  BootAddress :Specifies the CM4 Boot Address to be loaded in Address0
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetCM4BootAddress0(uint16_t BootAddress)
+{
+  /* Configure CM4 BOOT ADD0 */
+  MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0, ((uint32_t)BootAddress << SYSCFG_UR3_BCM4_ADD0_Pos));
+}
+
+/**
+  * @brief  Get BootCM4 address 0
+  * @rmtoll UR3   BCM4_ADD0   LL_SYSCFG_GetCM4BootAddress0
+  * @retval Returned the CM4 Boot Address0
+  */
+__STATIC_INLINE uint16_t LL_SYSCFG_GetCM4BootAddress0(void)
+{
+  /* Get CM4 BOOT ADD0 */
+  return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0) >> SYSCFG_UR3_BCM4_ADD0_Pos);
+}
+
+/**
+  * @brief  BootCM4 address 1 configuration
+  * @rmtoll UR4   BCM4_ADD1   LL_SYSCFG_SetCM4BootAddress1
+  * @param  BootAddress :Specifies the CM4 Boot Address to be loaded in Address1
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetCM4BootAddress1(uint16_t BootAddress)
+{
+  /* Configure CM4 BOOT ADD1 */
+  MODIFY_REG(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1, BootAddress);
+}
+
+/**
+  * @brief  Get BootCM4 address 1
+  * @rmtoll UR4   BCM4_ADD1   LL_SYSCFG_GetCM4BootAddress1
+  * @retval Returned the CM4 Boot Address0
+  */
+__STATIC_INLINE uint16_t LL_SYSCFG_GetCM4BootAddress1(void)
+{
+  /* Get CM4 BOOT ADD0 */
+  return (uint16_t)(READ_BIT(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1));
+}
+#endif /*DUAL_CORE*/
+
+/**
+  * @brief  Indicates if the flash protected area (Bank 1) is erased by a mass erase
+  * @rmtoll UR4   MEPAD_BANK1   LL_SYSCFG_IsFlashB1ProtectedAreaErasable
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1ProtectedAreaErasable(void)
+{
+  return ((READ_BIT(SYSCFG->UR4, SYSCFG_UR4_MEPAD_BANK1) == SYSCFG_UR4_MEPAD_BANK1) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the flash secured area (Bank 1) is erased by a mass erase
+  * @rmtoll UR5   MESAD_BANK1   LL_SYSCFG_IsFlashB1SecuredAreaErasable
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1SecuredAreaErasable(void)
+{
+  return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_MESAD_BANK1) == SYSCFG_UR5_MESAD_BANK1) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 0 of the Flash memory bank 1 is write protected
+  * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector0WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector0WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR0_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 1 of the Flash memory bank 1 is write protected
+  * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector1WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector1WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR1_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 2 of the Flash memory bank 1 is write protected
+  * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector2WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector2WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR2_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 3 of the Flash memory bank 1 is write protected
+  * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector3WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector3WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR3_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 4 of the Flash memory bank 1 is write protected
+  * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector4WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector4WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR4_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 5 of the Flash memory bank 1 is write protected
+  * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector5WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector5WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR5_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 6 of the Flash memory bank 1 is write protected
+  * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector6WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector6WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR6_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 7 of the Flash memory bank 1 is write protected
+  * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector7WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector7WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR7_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get the protected area start address for Flash bank 1
+  * @rmtoll UR6   PABEG_BANK1    LL_SYSCFG_GetFlashB1ProtectedAreaStartAddress
+  * @retval Returned the protected area start address for Flash bank 1
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1ProtectedAreaStartAddress(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->UR6, SYSCFG_UR6_PABEG_BANK1));
+}
+
+/**
+  * @brief  Get the protected area end address for Flash bank 1
+  * @rmtoll UR6   PAEND_BANK1   LL_SYSCFG_GetFlashB1ProtectedAreaEndAddress
+  * @retval Returned the protected area end address for Flash bank 1
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1ProtectedAreaEndAddress(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->UR6, SYSCFG_UR6_PAEND_BANK1));
+}
+
+/**
+  * @brief  Get the secured area start address for Flash bank 1
+  * @rmtoll UR7   SABEG_BANK1   LL_SYSCFG_GetFlashB1SecuredAreaStartAddress
+  * @retval Returned the secured area start address for Flash bank 1
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1SecuredAreaStartAddress(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->UR7, SYSCFG_UR7_SABEG_BANK1));
+}
+
+/**
+  * @brief  Get the secured area end address for Flash bank 1
+  * @rmtoll UR7   SAEND_BANK1   LL_SYSCFG_GetFlashB1SecuredAreaEndAddress
+  * @retval Returned the secured area end address for Flash bank 1
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1SecuredAreaEndAddress(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->UR7, SYSCFG_UR7_SAEND_BANK1));
+}
+
+/**
+  * @brief  Indicates if the flash protected area (Bank 2) is erased by a mass erase
+  * @rmtoll UR8   MEPAD_BANK2   LL_SYSCFG_IsFlashB2ProtectedAreaErasable
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2ProtectedAreaErasable(void)
+{
+  return ((READ_BIT(SYSCFG->UR8, SYSCFG_UR8_MEPAD_BANK2) == SYSCFG_UR8_MEPAD_BANK2) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the flash secured area (Bank 2) is erased by a mass erase
+  * @rmtoll UR8   MESAD_BANK2   LL_SYSCFG_IsFlashB2SecuredAreaErasable
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2SecuredAreaErasable(void)
+{
+  return ((READ_BIT(SYSCFG->UR8, SYSCFG_UR8_MESAD_BANK2) == SYSCFG_UR8_MESAD_BANK2) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 0 of the Flash memory bank 2 is write protected
+  * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector0WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector0WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR0_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 1 of the Flash memory bank 2 is write protected
+  * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector1WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector1WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR1_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 2 of the Flash memory bank 2 is write protected
+  * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector2WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector2WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR2_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 3 of the Flash memory bank 2 is write protected
+  * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector3WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector3WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR3_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 4 of the Flash memory bank 2 is write protected
+  * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector4WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector4WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR4_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 5 of the Flash memory bank 2 is write protected
+  * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector5WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector5WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR5_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 6 of the Flash memory bank 2 is write protected
+  * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector6WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector6WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR6_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 7 of the Flash memory bank 2 is write protected
+  * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector7WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector7WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR7_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get the protected area start address for Flash bank 2
+  * @rmtoll UR9   PABEG_BANK2   LL_SYSCFG_GetFlashB2ProtectedAreaStartAddress
+  * @retval Returned the protected area start address for Flash bank 2
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2ProtectedAreaStartAddress(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->UR9, SYSCFG_UR9_PABEG_BANK2));
+}
+
+/**
+  * @brief  Get the protected area end address for Flash bank 2
+  * @rmtoll UR10    PAEND_BANK2   LL_SYSCFG_GetFlashB2ProtectedAreaEndAddress
+  * @retval Returned the protected area end address for Flash bank 2
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2ProtectedAreaEndAddress(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->UR10, SYSCFG_UR10_PAEND_BANK2));
+}
+
+/**
+  * @brief  Get the secured area start address for Flash bank 2
+  * @rmtoll UR10    SABEG_BANK2   LL_SYSCFG_GetFlashB2SecuredAreaStartAddress
+  * @retval Returned the secured area start address for Flash bank 2
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2SecuredAreaStartAddress(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->UR10, SYSCFG_UR10_SABEG_BANK2));
+}
+
+/**
+  * @brief  Get the secured area end address for Flash bank 2
+  * @rmtoll UR11    SAEND_BANK2   LL_SYSCFG_GetFlashB2SecuredAreaEndAddress
+  * @retval Returned the secured area end address for Flash bank 2
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2SecuredAreaEndAddress(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->UR11, SYSCFG_UR11_SAEND_BANK2));
+}
+
+/**
+  * @brief  Get the Independent Watchdog 1 control mode (Software or Hardware)
+  * @rmtoll UR11    IWDG1M    LL_SYSCFG_GetIWDG1ControlMode
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_IWDG1_SW_CONTROL_MODE
+  *         @arg @ref LL_SYSCFG_IWDG1_HW_CONTROL_MODE
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetIWDG1ControlMode(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->UR11, SYSCFG_UR11_IWDG1M));
+}
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Get the Independent Watchdog 2 control mode (Software or Hardware)
+  * @rmtoll UR12    IWDG2M    LL_SYSCFG_GetIWDG2ControlMode
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_IWDG2_SW_CONTROL_MODE
+  *         @arg @ref LL_SYSCFG_IWDG2_HW_CONTROL_MODE
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetIWDG2ControlMode(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->UR12, SYSCFG_UR12_IWDG2M));
+}
+#endif /* DUAL_CORE */
+
+/**
+  * @brief  Indicates the Secure mode status
+  * @rmtoll UR12    SECURE    LL_SYSCFG_IsSecureModeEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsSecureModeEnabled(void)
+{
+  return ((READ_BIT(SYSCFG->UR12, SYSCFG_UR12_SECURE) == SYSCFG_UR12_SECURE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if a reset is generated when D1 domain enters DStandby mode
+  * @rmtoll UR13    D1SBRST   LL_SYSCFG_IsD1StandbyGenerateReset
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsD1StandbyGenerateReset(void)
+{
+  return ((READ_BIT(SYSCFG->UR13, SYSCFG_UR13_D1SBRST) == 0U) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get the secured DTCM RAM size
+  * @rmtoll UR13    SDRS    LL_SYSCFG_GetSecuredDTCMSize
+  * @retval Returned value can be one of the following values:
+  *           @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_2KB
+  *           @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_4KB
+  *           @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_8KB
+  *           @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_16KB
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetSecuredDTCMSize(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->UR13, SYSCFG_UR13_SDRS));
+}
+
+/**
+  * @brief  Indicates if a reset is generated when D1 domain enters DStop mode
+  * @rmtoll UR14    D1STPRST    LL_SYSCFG_IsD1StopGenerateReset
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsD1StopGenerateReset(void)
+{
+  return ((READ_BIT(SYSCFG->UR14, SYSCFG_UR14_D1STPRST) == 0U) ? 1UL : 0UL);
+}
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Indicates if a reset is generated when D2 domain enters DStandby mode
+  * @rmtoll UR14    D2SBRST   LL_SYSCFG_IsD2StandbyGenerateReset
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsD2StandbyGenerateReset(void)
+{
+  return ((READ_BIT(SYSCFG->UR14, SYSCFG_UR14_D2SBRST) == 0U) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if a reset is generated when D2 domain enters DStop mode
+  * @rmtoll UR15    D2STPRST    LL_SYSCFG_IsD2StopGenerateReset
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsD2StopGenerateReset(void)
+{
+  return ((READ_BIT(SYSCFG->UR15, SYSCFG_UR15_D2STPRST) == 0U) ? 1UL : 0UL);
+}
+#endif /* DUAL_CORE */
+
+/**
+  * @brief  Indicates if the independent watchdog is frozen in Standby mode
+  * @rmtoll UR15    FZIWDGSTB   LL_SYSCFG_IsIWDGFrozenInStandbyMode
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsIWDGFrozenInStandbyMode(void)
+{
+  return ((READ_BIT(SYSCFG->UR15, SYSCFG_UR15_FZIWDGSTB) == 0U) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the independent watchdog is frozen in Stop mode
+  * @rmtoll UR16    FZIWDGSTP   LL_SYSCFG_IsIWDGFrozenInStopMode
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsIWDGFrozenInStopMode(void)
+{
+  return ((READ_BIT(SYSCFG->UR16, SYSCFG_UR16_FZIWDGSTP) == 0U) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the device private key is programmed
+  * @rmtoll UR16    PKP   LL_SYSCFG_IsPrivateKeyProgrammed
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsPrivateKeyProgrammed(void)
+{
+  return ((READ_BIT(SYSCFG->UR16, SYSCFG_UR16_PKP) == SYSCFG_UR16_PKP) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the Product is working on the full voltage range or not
+  * @rmtoll UR17    IOHSLV    LL_SYSCFG_IsActiveFlag_IOHSLV
+  * @note   When the IOHSLV option bit is set the Product is working below 2.7 V.
+  *         When the IOHSLV option bit is reset the Product is working on the
+  *         full voltage range.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_IOHSLV(void)
+{
+  return ((READ_BIT(SYSCFG->UR17, SYSCFG_UR17_IOHSLV) == SYSCFG_UR17_IOHSLV) ? 1UL : 0UL);
+}
+#endif /*SYSCFG_UR0_RDP*/
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
+  * @{
+  */
+
+/**
+  * @brief  Return the device identifier
+  * @rmtoll DBGMCU_IDCODE DEV_ID        LL_DBGMCU_GetDeviceID
+  * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
+  */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
+{
+  return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
+}
+
+/**
+  * @brief  Return the device revision identifier
+  * @note This field indicates the revision of the device.
+          For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001
+  * @rmtoll DBGMCU_IDCODE REV_ID        LL_DBGMCU_GetRevisionID
+  * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
+{
+  return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
+}
+
+/**
+  * @brief  Enable D1 Domain/CDomain debug during SLEEP mode
+  * @rmtoll DBGMCU_CR    DBGSLEEP_D1/DBGSLEEP_CD     LL_DBGMCU_EnableD1DebugInSleepMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableD1DebugInSleepMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
+}
+
+/**
+  * @brief  Disable D1 Domain/CDomain debug during SLEEP mode
+  * @rmtoll DBGMCU_CR    DBGSLEEP_D1/DBGSLEEP_CD     LL_DBGMCU_DisableD1DebugInSleepMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableD1DebugInSleepMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
+}
+
+/**
+  * @brief  Enable D1 Domain/CDomain debug during STOP mode
+  * @rmtoll DBGMCU_CR    DBGSTOP_D1/DBGSLEEP_CD     LL_DBGMCU_EnableD1DebugInStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableD1DebugInStopMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
+}
+
+/**
+  * @brief  Disable D1 Domain/CDomain debug during STOP mode
+  * @rmtoll DBGMCU_CR    DBGSTOP_D1/DBGSLEEP_CD     LL_DBGMCU_DisableD1DebugInStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableD1DebugInStopMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
+}
+
+/**
+  * @brief  Enable D1 Domain/CDomain debug during STANDBY mode
+  * @rmtoll DBGMCU_CR    DBGSTBY_D1/DBGSLEEP_CD     LL_DBGMCU_EnableD1DebugInStandbyMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableD1DebugInStandbyMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
+}
+
+/**
+  * @brief  Disable D1 Domain/CDomain debug during STANDBY mode
+  * @rmtoll DBGMCU_CR    DBGSTBY_D1/DBGSLEEP_CD     LL_DBGMCU_DisableD1DebugInStandbyMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableD1DebugInStandbyMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
+}
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Enable D2 Domain debug during SLEEP mode
+  * @rmtoll DBGMCU_CR    DBGSLEEP_D2     LL_DBGMCU_EnableD2DebugInSleepMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableD2DebugInSleepMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2);
+}
+
+/**
+  * @brief  Disable D2 Domain debug during SLEEP mode
+  * @rmtoll DBGMCU_CR    DBGSLEEP_D2     LL_DBGMCU_DisableD2DebugInSleepMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableD2DebugInSleepMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2);
+}
+
+/**
+  * @brief  Enable D2 Domain debug during STOP mode
+  * @rmtoll DBGMCU_CR    DBGSTOP_D2     LL_DBGMCU_EnableD2DebugInStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableD2DebugInStopMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2);
+}
+
+/**
+  * @brief  Disable D2 Domain debug during STOP mode
+  * @rmtoll DBGMCU_CR    DBGSTOP_D2     LL_DBGMCU_DisableD2DebugInStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableD2DebugInStopMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2);
+}
+
+/**
+  * @brief  Enable D2 Domain debug during STANDBY mode
+  * @rmtoll DBGMCU_CR    DBGSTBY_D2     LL_DBGMCU_EnableD2DebugInStandbyMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableD2DebugInStandbyMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2);
+}
+
+/**
+  * @brief  Disable D2 Domain debug during STANDBY mode
+  * @rmtoll DBGMCU_CR    DBGSTBY_D2     LL_DBGMCU_DisableD2DebugInStandbyMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableD2DebugInStandbyMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2);
+}
+#endif /* DUAL_CORE */
+
+
+/**
+  * @brief  Enable D3 Domain/SRDomain debug during STOP mode
+  * @rmtoll DBGMCU_CR    DBGSTOP_D3/DBGSTOP_SRD    LL_DBGMCU_EnableD3DebugInStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableD3DebugInStopMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
+}
+
+/**
+  * @brief  Disable D3 Domain/SRDomain debug during STOP mode
+  * @rmtoll DBGMCU_CR    DBGSTOP_D3/DBGSTOP_SRD     LL_DBGMCU_DisableD3DebugInStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableD3DebugInStopMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
+}
+
+/**
+  * @brief  Enable D3 Domain/SRDomain debug during STANDBY mode
+  * @rmtoll DBGMCU_CR    DBGSTBY_D3/DBGSTBY_SRD     LL_DBGMCU_EnableD3DebugInStandbyMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableD3DebugInStandbyMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
+}
+
+/**
+  * @brief  Disable D3 Domain/SRDomain debug during STANDBY mode
+  * @rmtoll DBGMCU_CR    DBGSTBY_D3/DBGSTBY_SRD     LL_DBGMCU_DisableD3DebugInStandbyMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableD3DebugInStandbyMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
+}
+
+/**
+  * @brief  Enable the trace port clock
+  * @rmtoll DBGMCU_CR    TRACECKEN     LL_DBGMCU_EnableTracePortClock
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableTracePortClock(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRACECKEN);
+}
+
+/**
+  * @brief  Disable the trace port clock
+  * @rmtoll DBGMCU_CR    TRACECKEN     LL_DBGMCU_DisableTracePortClock
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableTracePortClock(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRACECKEN);
+}
+
+/**
+  * @brief  Enable the Domain1/CDomain debug clock enable
+  * @rmtoll DBGMCU_CR    CKD1EN/CKCDEN     LL_DBGMCU_EnableD1DebugClock
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableD1DebugClock(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD1EN);
+}
+
+/**
+  * @brief  Disable the Domain1/CDomain debug clock enable
+  * @rmtoll DBGMCU_CR    CKD1EN/CKCDEN     LL_DBGMCU_DisableD1DebugClock
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableD1DebugClock(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD1EN);
+}
+
+/**
+  * @brief  Enable the Domain3/SRDomain debug clock enable
+  * @rmtoll DBGMCU_CR    CKD3EN/CKSRDEN     LL_DBGMCU_EnableD3DebugClock
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableD3DebugClock(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD3EN);
+}
+
+/**
+  * @brief  Disable the Domain3/SRDomain debug clock enable
+  * @rmtoll DBGMCU_CR    CKD3EN/CKSRDEN    LL_DBGMCU_DisableD3DebugClock
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableD3DebugClock(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD3EN);
+}
+
+#define LL_DBGMCU_TRGIO_INPUT_DIRECTION   0U
+#define LL_DBGMCU_TRGIO_OUTPUT_DIRECTION  DBGMCU_CR_DBG_TRGOEN
+/**
+  * @brief  Set the direction of the bi-directional trigger pin TRGIO
+  * @rmtoll DBGMCU_CR    TRGOEN    LL_DBGMCU_SetExternalTriggerPinDirection\n
+  * @param  PinDirection This parameter can be one of the following values:
+  *         @arg @ref LL_DBGMCU_TRGIO_INPUT_DIRECTION
+  *         @arg @ref LL_DBGMCU_TRGIO_OUTPUT_DIRECTION
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_SetExternalTriggerPinDirection(uint32_t PinDirection)
+{
+  MODIFY_REG(DBGMCU->CR, DBGMCU_CR_DBG_TRGOEN, PinDirection);
+}
+
+/**
+  * @brief  Get the direction of the bi-directional trigger pin TRGIO
+  * @rmtoll DBGMCU_CR    TRGOEN    LL_DBGMCU_GetExternalTriggerPinDirection\n
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DBGMCU_TRGIO_INPUT_DIRECTION
+  *         @arg @ref LL_DBGMCU_TRGIO_OUTPUT_DIRECTION
+  */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetExternalTriggerPinDirection(void)
+{
+  return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRGOEN));
+}
+
+/**
+  * @brief  Freeze APB1 group1 peripherals
+  * @rmtoll DBGMCU_APB1LFZ1   TIM2      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM3      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM4      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM5      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM6      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM7      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM12     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM13     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM14     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   LPTIM1    LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   I2C1      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   I2C2      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   I2C3      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
+{
+  SET_BIT(DBGMCU->APB1LFZ1, Periphs);
+}
+
+/**
+  * @brief  Unfreeze APB1 peripherals (group1 peripherals)
+  * @rmtoll DBGMCU_APB1LFZ1   TIM2      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM3      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM4      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM5      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM6      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM7      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM12     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM13     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM14     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   LPTIM1    LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   I2C1      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   I2C2      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   I2C3      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
+{
+  CLEAR_BIT(DBGMCU->APB1LFZ1, Periphs);
+}
+
+/**
+  * @brief  Freeze APB1 group2 peripherals
+  * @rmtoll DBGMCU_APB1HFZ1   FDCAN   LL_DBGMCU_APB1_GRP2_FreezePeriph\n
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB1_GRP2_FDCAN_STOP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
+{
+  SET_BIT(DBGMCU->APB1HFZ1, Periphs);
+}
+
+/**
+  * @brief  Unfreeze APB1 group2 peripherals
+  * @rmtoll DBGMCU_APB1HFZ1   FDCAN   LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB1_GRP2_FDCAN_STOP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
+{
+  CLEAR_BIT(DBGMCU->APB1HFZ1, Periphs);
+}
+
+/**
+  * @brief  Freeze APB2 peripherals
+  * @rmtoll DBGMCU_APB2FZ1    TIM1     LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+  *         DBGMCU_APB2FZ1    TIM8     LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+  *         DBGMCU_APB2FZ1    TIM15    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+  *         DBGMCU_APB2FZ1    TIM16    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+  *         DBGMCU_APB2FZ1    TIM17    LL_DBGMCU_APB2_GRP1_FreezePeriph
+  *         DBGMCU_APB2FZ1    HRTIM    LL_DBGMCU_APB2_GRP1_FreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM_STOP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
+{
+  SET_BIT(DBGMCU->APB2FZ1, Periphs);
+}
+
+/**
+  * @brief  Unfreeze APB2 peripherals
+  * @rmtoll DBGMCU_APB2FZ1    TIM1     LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+  *         DBGMCU_APB2FZ1    TIM8     LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+  *         DBGMCU_APB2FZ1    TIM15    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+  *         DBGMCU_APB2FZ1    TIM16    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+  *         DBGMCU_APB2FZ1    TIM17    LL_DBGMCU_APB2_GRP1_FreezePeriph
+  *         DBGMCU_APB2FZ1    HRTIM    LL_DBGMCU_APB2_GRP1_FreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM_STOP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
+{
+  CLEAR_BIT(DBGMCU->APB2FZ1, Periphs);
+}
+
+/**
+  * @brief  Freeze APB3 peripherals
+  * @rmtoll DBGMCU_APB3FZ1    WWDG1     LL_DBGMCU_APB3_GRP1_FreezePeriph\n
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB3_GRP1_WWDG1_STOP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB3_GRP1_FreezePeriph(uint32_t Periphs)
+{
+  SET_BIT(DBGMCU->APB3FZ1, Periphs);
+}
+
+/**
+  * @brief  Unfreeze APB3 peripherals
+  * @rmtoll DBGMCU_APB3FZ1    WWDG1     LL_DBGMCU_APB3_GRP1_UnFreezePeriph\n
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB3_GRP1_WWDG1_STOP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB3_GRP1_UnFreezePeriph(uint32_t Periphs)
+{
+  CLEAR_BIT(DBGMCU->APB3FZ1, Periphs);
+}
+
+/**
+  * @brief  Freeze APB4 peripherals
+  * @rmtoll DBGMCU_APB4FZ1    I2C4      LL_DBGMCU_APB4_GRP1_FreezePeriph\n
+  * @rmtoll DBGMCU_APB4FZ1    LPTIM2    LL_DBGMCU_APB4_GRP1_FreezePeriph\n
+  * @rmtoll DBGMCU_APB4FZ1    LPTIM3    LL_DBGMCU_APB4_GRP1_FreezePeriph\n
+  * @rmtoll DBGMCU_APB4FZ1    LPTIM4    LL_DBGMCU_APB4_GRP1_FreezePeriph\n
+  * @rmtoll DBGMCU_APB4FZ1    LPTIM5    LL_DBGMCU_APB4_GRP1_FreezePeriph\n
+  * @rmtoll DBGMCU_APB4FZ1    RTC       LL_DBGMCU_APB4_GRP1_FreezePeriph\n
+  * @rmtoll DBGMCU_APB4FZ1    WDGLSD1   LL_DBGMCU_APB4_GRP1_FreezePeriph\n
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_I2C4_STOP
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_IWDG1_STOP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB4_GRP1_FreezePeriph(uint32_t Periphs)
+{
+  SET_BIT(DBGMCU->APB4FZ1, Periphs);
+}
+
+/**
+  * @brief  Unfreeze APB4 peripherals
+  * @rmtoll DBGMCU_APB4FZ1    I2C4      LL_DBGMCU_APB4_GRP1_FreezePeriph\n
+  * @rmtoll DBGMCU_APB4FZ1    LPTIM2    LL_DBGMCU_APB4_GRP1_FreezePeriph\n
+  * @rmtoll DBGMCU_APB4FZ1    LPTIM3    LL_DBGMCU_APB4_GRP1_FreezePeriph\n
+  * @rmtoll DBGMCU_APB4FZ1    LPTIM4    LL_DBGMCU_APB4_GRP1_FreezePeriph\n
+  * @rmtoll DBGMCU_APB4FZ1    LPTIM5    LL_DBGMCU_APB4_GRP1_FreezePeriph\n
+  * @rmtoll DBGMCU_APB4FZ1    RTC       LL_DBGMCU_APB4_GRP1_FreezePeriph\n
+  * @rmtoll DBGMCU_APB4FZ1    WDGLSD1   LL_DBGMCU_APB4_GRP1_FreezePeriph\n
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_I2C4_STOP
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_IWDG1_STOP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB4_GRP1_UnFreezePeriph(uint32_t Periphs)
+{
+  CLEAR_BIT(DBGMCU->APB4FZ1, Periphs);
+}
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EF_FLASH FLASH
+  * @{
+  */
+
+/**
+  * @brief  Set FLASH Latency
+  * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_SetLatency
+  * @param  Latency This parameter can be one of the following values:
+  *         @arg @ref LL_FLASH_LATENCY_0
+  *         @arg @ref LL_FLASH_LATENCY_1
+  *         @arg @ref LL_FLASH_LATENCY_2
+  *         @arg @ref LL_FLASH_LATENCY_3
+  *         @arg @ref LL_FLASH_LATENCY_4
+  *         @arg @ref LL_FLASH_LATENCY_5
+  *         @arg @ref LL_FLASH_LATENCY_6
+  *         @arg @ref LL_FLASH_LATENCY_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
+{
+  MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
+}
+
+/**
+  * @brief  Get FLASH Latency
+  * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_GetLatency
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_FLASH_LATENCY_0
+  *         @arg @ref LL_FLASH_LATENCY_1
+  *         @arg @ref LL_FLASH_LATENCY_2
+  *         @arg @ref LL_FLASH_LATENCY_3
+  *         @arg @ref LL_FLASH_LATENCY_4
+  *         @arg @ref LL_FLASH_LATENCY_5
+  *         @arg @ref LL_FLASH_LATENCY_6
+  *         @arg @ref LL_FLASH_LATENCY_7
+  */
+__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
+{
+  return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
+}
+
+/**
+  * @}
+  */
+
+#if defined(DUAL_CORE)
+/** @defgroup SYSTEM_LL_EF_ART ART
+  * @{
+  */
+
+/**
+  * @brief  Enable the Cortex-M4 ART cache.
+  * @rmtoll ART_CTR    EN   LL_ART_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_ART_Enable(void)
+{
+ SET_BIT(ART->CTR, ART_CTR_EN);
+}
+
+/**
+  * @brief  Disable the Cortex-M4 ART cache.
+  * @rmtoll ART_CTR    EN   LL_ART_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_ART_Disable(void)
+{
+ CLEAR_BIT(ART->CTR, ART_CTR_EN);
+}
+
+/**
+  * @brief  Check if the Cortex-M4 ART cache is enabled
+  * @rmtoll ART_CTR   EN    LL_ART_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ART_IsEnabled(void)
+{
+  return ((READ_BIT(ART->CTR, ART_CTR_EN) == ART_CTR_EN) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the Cortex-M4 ART cache Base Address.
+  * @rmtoll ART_CTR    PCACHEADDR   LL_ART_SetBaseAddress
+  * @param  BaseAddress Specifies the Base address of 1 Mbyte address page (cacheable page)
+            from which the ART accelerator loads code to the cache.
+  * @retval None
+  */
+__STATIC_INLINE void LL_ART_SetBaseAddress(uint32_t BaseAddress)
+{
+ MODIFY_REG(ART->CTR, ART_CTR_PCACHEADDR, (((BaseAddress) >> 12U) & 0x000FFF00UL));
+}
+
+/**
+  * @brief  Get the Cortex-M4 ART cache Base Address.
+  * @rmtoll ART_CTR    PCACHEADDR   LL_ART_GetBaseAddress
+  * @retval the Base address of 1 Mbyte address page (cacheable page)
+            from which the ART accelerator loads code to the cache
+  */
+__STATIC_INLINE uint32_t LL_ART_GetBaseAddress(void)
+{
+  return (uint32_t)(READ_BIT(ART->CTR, ART_CTR_PCACHEADDR) << 12U);
+}
+#endif /* DUAL_CORE */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32H7xx_LL_SYSTEM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usart.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usart.h
new file mode 100644
index 00000000..63941018
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usart.h
@@ -0,0 +1,4385 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_usart.h
+  * @author  MCD Application Team
+  * @brief   Header file of USART LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_LL_USART_H
+#define STM32H7xx_LL_USART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5) || defined (UART7) || defined (UART8) || defined (UART9) || defined (USART10)
+
+/** @defgroup USART_LL USART
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup USART_LL_Private_Variables USART Private Variables
+  * @{
+  */
+/* Array used to get the USART prescaler division decimal values versus @ref USART_LL_EC_PRESCALER values */
+static const uint32_t USART_PRESCALER_TAB[] =
+{
+  1UL,
+  2UL,
+  4UL,
+  6UL,
+  8UL,
+  10UL,
+  12UL,
+  16UL,
+  32UL,
+  64UL,
+  128UL,
+  256UL
+};
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_Private_Macros USART Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_ES_INIT USART Exported Init structures
+  * @{
+  */
+
+/**
+  * @brief LL USART Init Structure definition
+  */
+typedef struct
+{
+  uint32_t PrescalerValue;            /*!< Specifies the Prescaler to compute the communication baud rate.
+                                           This parameter can be a value of @ref USART_LL_EC_PRESCALER.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetPrescaler().*/
+
+  uint32_t BaudRate;                  /*!< This field defines expected Usart communication baud rate.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/
+
+  uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/
+
+  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
+                                           This parameter can be a value of @ref USART_LL_EC_STOPBITS.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/
+
+  uint32_t Parity;                    /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref USART_LL_EC_PARITY.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/
+
+  uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref USART_LL_EC_DIRECTION.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/
+
+  uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.
+                                           This parameter can be a value of @ref USART_LL_EC_HWCONTROL.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/
+
+  uint32_t OverSampling;              /*!< Specifies whether USART oversampling mode is 16 or 8.
+                                           This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/
+
+} LL_USART_InitTypeDef;
+
+/**
+  * @brief LL USART Clock Init Structure definition
+  */
+typedef struct
+{
+  uint32_t ClockOutput;               /*!< Specifies whether the USART clock is enabled or disabled.
+                                           This parameter can be a value of @ref USART_LL_EC_CLOCK.
+
+                                           USART HW configuration can be modified afterwards using unitary functions
+                                           @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput().
+                                           For more details, refer to description of this function. */
+
+  uint32_t ClockPolarity;             /*!< Specifies the steady state of the serial clock.
+                                           This parameter can be a value of @ref USART_LL_EC_POLARITY.
+
+                                           USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity().
+                                           For more details, refer to description of this function. */
+
+  uint32_t ClockPhase;                /*!< Specifies the clock transition on which the bit capture is made.
+                                           This parameter can be a value of @ref USART_LL_EC_PHASE.
+
+                                           USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase().
+                                           For more details, refer to description of this function. */
+
+  uint32_t LastBitClockPulse;         /*!< Specifies whether the clock pulse corresponding to the last transmitted
+                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+                                           This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.
+
+                                           USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput().
+                                           For more details, refer to description of this function. */
+
+} LL_USART_ClockInitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup USART_LL_Exported_Constants USART Exported Constants
+  * @{
+  */
+
+/** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_USART_WriteReg function
+  * @{
+  */
+#define LL_USART_ICR_PECF                       USART_ICR_PECF                /*!< Parity error flag */
+#define LL_USART_ICR_FECF                       USART_ICR_FECF                /*!< Framing error flag */
+#define LL_USART_ICR_NECF                       USART_ICR_NECF                /*!< Noise error detected flag */
+#define LL_USART_ICR_ORECF                      USART_ICR_ORECF               /*!< Overrun error flag */
+#define LL_USART_ICR_IDLECF                     USART_ICR_IDLECF              /*!< Idle line detected flag */
+#define LL_USART_ICR_TXFECF                     USART_ICR_TXFECF              /*!< TX FIFO Empty Clear flag */
+#define LL_USART_ICR_TCCF                       USART_ICR_TCCF                /*!< Transmission complete flag */
+#define LL_USART_ICR_TCBGTCF                    USART_ICR_TCBGTCF             /*!< Transmission completed before guard time flag */
+#define LL_USART_ICR_LBDCF                      USART_ICR_LBDCF               /*!< LIN break detection flag */
+#define LL_USART_ICR_CTSCF                      USART_ICR_CTSCF               /*!< CTS flag */
+#define LL_USART_ICR_RTOCF                      USART_ICR_RTOCF               /*!< Receiver timeout flag */
+#define LL_USART_ICR_EOBCF                      USART_ICR_EOBCF               /*!< End of block flag */
+#define LL_USART_ICR_UDRCF                      USART_ICR_UDRCF               /*!< SPI Slave Underrun Clear flag */
+#define LL_USART_ICR_CMCF                       USART_ICR_CMCF                /*!< Character match flag */
+#define LL_USART_ICR_WUCF                       USART_ICR_WUCF                /*!< Wakeup from Stop mode flag */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_USART_ReadReg function
+  * @{
+  */
+#define LL_USART_ISR_PE                         USART_ISR_PE                  /*!< Parity error flag */
+#define LL_USART_ISR_FE                         USART_ISR_FE                  /*!< Framing error flag */
+#define LL_USART_ISR_NE                         USART_ISR_NE                  /*!< Noise detected flag */
+#define LL_USART_ISR_ORE                        USART_ISR_ORE                 /*!< Overrun error flag */
+#define LL_USART_ISR_IDLE                       USART_ISR_IDLE                /*!< Idle line detected flag */
+#define LL_USART_ISR_RXNE_RXFNE                 USART_ISR_RXNE_RXFNE          /*!< Read data register or RX FIFO not empty flag */
+#define LL_USART_ISR_TC                         USART_ISR_TC                  /*!< Transmission complete flag */
+#define LL_USART_ISR_TXE_TXFNF                  USART_ISR_TXE_TXFNF           /*!< Transmit data register empty or TX FIFO Not Full flag*/
+#define LL_USART_ISR_LBDF                       USART_ISR_LBDF                /*!< LIN break detection flag */
+#define LL_USART_ISR_CTSIF                      USART_ISR_CTSIF               /*!< CTS interrupt flag */
+#define LL_USART_ISR_CTS                        USART_ISR_CTS                 /*!< CTS flag */
+#define LL_USART_ISR_RTOF                       USART_ISR_RTOF                /*!< Receiver timeout flag */
+#define LL_USART_ISR_EOBF                       USART_ISR_EOBF                /*!< End of block flag */
+#define LL_USART_ISR_UDR                        USART_ISR_UDR                 /*!< SPI Slave underrun error flag */
+#define LL_USART_ISR_ABRE                       USART_ISR_ABRE                /*!< Auto baud rate error flag */
+#define LL_USART_ISR_ABRF                       USART_ISR_ABRF                /*!< Auto baud rate flag */
+#define LL_USART_ISR_BUSY                       USART_ISR_BUSY                /*!< Busy flag */
+#define LL_USART_ISR_CMF                        USART_ISR_CMF                 /*!< Character match flag */
+#define LL_USART_ISR_SBKF                       USART_ISR_SBKF                /*!< Send break flag */
+#define LL_USART_ISR_RWU                        USART_ISR_RWU                 /*!< Receiver wakeup from Mute mode flag */
+#define LL_USART_ISR_WUF                        USART_ISR_WUF                 /*!< Wakeup from Stop mode flag */
+#define LL_USART_ISR_TEACK                      USART_ISR_TEACK               /*!< Transmit enable acknowledge flag */
+#define LL_USART_ISR_REACK                      USART_ISR_REACK               /*!< Receive enable acknowledge flag */
+#define LL_USART_ISR_TXFE                       USART_ISR_TXFE                /*!< TX FIFO empty flag */
+#define LL_USART_ISR_RXFF                       USART_ISR_RXFF                /*!< RX FIFO full flag */
+#define LL_USART_ISR_TCBGT                      USART_ISR_TCBGT               /*!< Transmission complete before guard time completion flag */
+#define LL_USART_ISR_RXFT                       USART_ISR_RXFT                /*!< RX FIFO threshold flag */
+#define LL_USART_ISR_TXFT                       USART_ISR_TXFT                /*!< TX FIFO threshold flag */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_USART_ReadReg and  LL_USART_WriteReg functions
+  * @{
+  */
+#define LL_USART_CR1_IDLEIE                     USART_CR1_IDLEIE              /*!< IDLE interrupt enable */
+#define LL_USART_CR1_RXNEIE_RXFNEIE             USART_CR1_RXNEIE_RXFNEIE      /*!< Read data register and RXFIFO not empty interrupt enable */
+#define LL_USART_CR1_TCIE                       USART_CR1_TCIE                /*!< Transmission complete interrupt enable */
+#define LL_USART_CR1_TXEIE_TXFNFIE              USART_CR1_TXEIE_TXFNFIE       /*!< Transmit data register empty and TX FIFO not full interrupt enable */
+#define LL_USART_CR1_PEIE                       USART_CR1_PEIE                /*!< Parity error */
+#define LL_USART_CR1_CMIE                       USART_CR1_CMIE                /*!< Character match interrupt enable */
+#define LL_USART_CR1_RTOIE                      USART_CR1_RTOIE               /*!< Receiver timeout interrupt enable */
+#define LL_USART_CR1_EOBIE                      USART_CR1_EOBIE               /*!< End of Block interrupt enable */
+#define LL_USART_CR1_TXFEIE                     USART_CR1_TXFEIE              /*!< TX FIFO empty interrupt enable */
+#define LL_USART_CR1_RXFFIE                     USART_CR1_RXFFIE              /*!< RX FIFO full interrupt enable */
+#define LL_USART_CR2_LBDIE                      USART_CR2_LBDIE               /*!< LIN break detection interrupt enable */
+#define LL_USART_CR3_EIE                        USART_CR3_EIE                 /*!< Error interrupt enable */
+#define LL_USART_CR3_CTSIE                      USART_CR3_CTSIE               /*!< CTS interrupt enable */
+#define LL_USART_CR3_WUFIE                      USART_CR3_WUFIE               /*!< Wakeup from Stop mode interrupt enable */
+#define LL_USART_CR3_TXFTIE                     USART_CR3_TXFTIE              /*!< TX FIFO threshold interrupt enable */
+#define LL_USART_CR3_TCBGTIE                    USART_CR3_TCBGTIE             /*!< Transmission complete before guard time interrupt enable */
+#define LL_USART_CR3_RXFTIE                     USART_CR3_RXFTIE              /*!< RX FIFO threshold interrupt enable */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_FIFOTHRESHOLD FIFO Threshold
+  * @{
+  */
+#define LL_USART_FIFOTHRESHOLD_1_8              0x00000000U /*!< FIFO reaches 1/8 of its depth */
+#define LL_USART_FIFOTHRESHOLD_1_4              0x00000001U /*!< FIFO reaches 1/4 of its depth */
+#define LL_USART_FIFOTHRESHOLD_1_2              0x00000002U /*!< FIFO reaches 1/2 of its depth */
+#define LL_USART_FIFOTHRESHOLD_3_4              0x00000003U /*!< FIFO reaches 3/4 of its depth */
+#define LL_USART_FIFOTHRESHOLD_7_8              0x00000004U /*!< FIFO reaches 7/8 of its depth */
+#define LL_USART_FIFOTHRESHOLD_8_8              0x00000005U /*!< FIFO becomes empty for TX and full for RX */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_DIRECTION Communication Direction
+  * @{
+  */
+#define LL_USART_DIRECTION_NONE                 0x00000000U                        /*!< Transmitter and Receiver are disabled */
+#define LL_USART_DIRECTION_RX                   USART_CR1_RE                       /*!< Transmitter is disabled and Receiver is enabled */
+#define LL_USART_DIRECTION_TX                   USART_CR1_TE                       /*!< Transmitter is enabled and Receiver is disabled */
+#define LL_USART_DIRECTION_TX_RX                (USART_CR1_TE |USART_CR1_RE)       /*!< Transmitter and Receiver are enabled */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_PARITY Parity Control
+  * @{
+  */
+#define LL_USART_PARITY_NONE                    0x00000000U                          /*!< Parity control disabled */
+#define LL_USART_PARITY_EVEN                    USART_CR1_PCE                        /*!< Parity control enabled and Even Parity is selected */
+#define LL_USART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)       /*!< Parity control enabled and Odd Parity is selected */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_WAKEUP Wakeup
+  * @{
+  */
+#define LL_USART_WAKEUP_IDLELINE                0x00000000U           /*!<  USART wake up from Mute mode on Idle Line */
+#define LL_USART_WAKEUP_ADDRESSMARK             USART_CR1_WAKE        /*!<  USART wake up from Mute mode on Address Mark */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_DATAWIDTH Datawidth
+  * @{
+  */
+#define LL_USART_DATAWIDTH_7B                   USART_CR1_M1            /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
+#define LL_USART_DATAWIDTH_8B                   0x00000000U             /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
+#define LL_USART_DATAWIDTH_9B                   USART_CR1_M0            /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling
+  * @{
+  */
+#define LL_USART_OVERSAMPLING_16                0x00000000U            /*!< Oversampling by 16 */
+#define LL_USART_OVERSAMPLING_8                 USART_CR1_OVER8        /*!< Oversampling by 8 */
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_EC_CLOCK Clock Signal
+  * @{
+  */
+
+#define LL_USART_CLOCK_DISABLE                  0x00000000U            /*!< Clock signal not provided */
+#define LL_USART_CLOCK_ENABLE                   USART_CR2_CLKEN        /*!< Clock signal provided */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse
+  * @{
+  */
+#define LL_USART_LASTCLKPULSE_NO_OUTPUT         0x00000000U           /*!< The clock pulse of the last data bit is not output to the SCLK pin */
+#define LL_USART_LASTCLKPULSE_OUTPUT            USART_CR2_LBCL        /*!< The clock pulse of the last data bit is output to the SCLK pin */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_PHASE Clock Phase
+  * @{
+  */
+#define LL_USART_PHASE_1EDGE                    0x00000000U           /*!< The first clock transition is the first data capture edge */
+#define LL_USART_PHASE_2EDGE                    USART_CR2_CPHA        /*!< The second clock transition is the first data capture edge */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_POLARITY Clock Polarity
+  * @{
+  */
+#define LL_USART_POLARITY_LOW                   0x00000000U           /*!< Steady low value on SCLK pin outside transmission window*/
+#define LL_USART_POLARITY_HIGH                  USART_CR2_CPOL        /*!< Steady high value on SCLK pin outside transmission window */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_PRESCALER Clock Source Prescaler
+  * @{
+  */
+#define LL_USART_PRESCALER_DIV1                 0x00000000U                                                                   /*!< Input clock not devided   */
+#define LL_USART_PRESCALER_DIV2                 (USART_PRESC_PRESCALER_0)                                                     /*!< Input clock devided by 2  */
+#define LL_USART_PRESCALER_DIV4                 (USART_PRESC_PRESCALER_1)                                                     /*!< Input clock devided by 4  */
+#define LL_USART_PRESCALER_DIV6                 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)                           /*!< Input clock devided by 6  */
+#define LL_USART_PRESCALER_DIV8                 (USART_PRESC_PRESCALER_2)                                                     /*!< Input clock devided by 8  */
+#define LL_USART_PRESCALER_DIV10                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0)                           /*!< Input clock devided by 10 */
+#define LL_USART_PRESCALER_DIV12                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1)                           /*!< Input clock devided by 12 */
+#define LL_USART_PRESCALER_DIV16                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 16 */
+#define LL_USART_PRESCALER_DIV32                (USART_PRESC_PRESCALER_3)                                                     /*!< Input clock devided by 32 */
+#define LL_USART_PRESCALER_DIV64                (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0)                           /*!< Input clock devided by 64 */
+#define LL_USART_PRESCALER_DIV128               (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1)                           /*!< Input clock devided by 128 */
+#define LL_USART_PRESCALER_DIV256               (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 256 */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_STOPBITS Stop Bits
+  * @{
+  */
+#define LL_USART_STOPBITS_0_5                   USART_CR2_STOP_0                           /*!< 0.5 stop bit */
+#define LL_USART_STOPBITS_1                     0x00000000U                                /*!< 1 stop bit */
+#define LL_USART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1)      /*!< 1.5 stop bits */
+#define LL_USART_STOPBITS_2                     USART_CR2_STOP_1                           /*!< 2 stop bits */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_TXRX TX RX Pins Swap
+  * @{
+  */
+#define LL_USART_TXRX_STANDARD                  0x00000000U           /*!< TX/RX pins are used as defined in standard pinout */
+#define LL_USART_TXRX_SWAPPED                   (USART_CR2_SWAP)      /*!< TX and RX pins functions are swapped.             */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
+  * @{
+  */
+#define LL_USART_RXPIN_LEVEL_STANDARD           0x00000000U           /*!< RX pin signal works using the standard logic levels */
+#define LL_USART_RXPIN_LEVEL_INVERTED           (USART_CR2_RXINV)     /*!< RX pin signal values are inverted.                  */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
+  * @{
+  */
+#define LL_USART_TXPIN_LEVEL_STANDARD           0x00000000U           /*!< TX pin signal works using the standard logic levels */
+#define LL_USART_TXPIN_LEVEL_INVERTED           (USART_CR2_TXINV)     /*!< TX pin signal values are inverted.                  */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion
+  * @{
+  */
+#define LL_USART_BINARY_LOGIC_POSITIVE          0x00000000U           /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */
+#define LL_USART_BINARY_LOGIC_NEGATIVE          USART_CR2_DATAINV     /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_BITORDER Bit Order
+  * @{
+  */
+#define LL_USART_BITORDER_LSBFIRST              0x00000000U           /*!< data is transmitted/received with data bit 0 first, following the start bit */
+#define LL_USART_BITORDER_MSBFIRST              USART_CR2_MSBFIRST    /*!< data is transmitted/received with the MSB first, following the start bit */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection
+  * @{
+  */
+#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT    0x00000000U                                 /*!< Measurement of the start bit is used to detect the baud rate */
+#define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0                         /*!< Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx */
+#define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME    USART_CR2_ABRMODE_1                         /*!< 0x7F frame detection */
+#define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME    (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x55 frame detection */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection
+  * @{
+  */
+#define LL_USART_ADDRESS_DETECT_4B              0x00000000U           /*!< 4-bit address detection method selected */
+#define LL_USART_ADDRESS_DETECT_7B              USART_CR2_ADDM7       /*!< 7-bit address detection (in 8-bit data mode) method selected */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_HWCONTROL Hardware Control
+  * @{
+  */
+#define LL_USART_HWCONTROL_NONE                 0x00000000U                          /*!< CTS and RTS hardware flow control disabled */
+#define LL_USART_HWCONTROL_RTS                  USART_CR3_RTSE                       /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
+#define LL_USART_HWCONTROL_CTS                  USART_CR3_CTSE                       /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
+#define LL_USART_HWCONTROL_RTS_CTS              (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< CTS and RTS hardware flow control enabled */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation
+  * @{
+  */
+#define LL_USART_WAKEUP_ON_ADDRESS              0x00000000U                             /*!< Wake up active on address match */
+#define LL_USART_WAKEUP_ON_STARTBIT             USART_CR3_WUS_1                         /*!< Wake up active on Start bit detection */
+#define LL_USART_WAKEUP_ON_RXNE                 (USART_CR3_WUS_0 | USART_CR3_WUS_1)     /*!< Wake up active on RXNE */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
+  * @{
+  */
+#define LL_USART_IRDA_POWER_NORMAL              0x00000000U           /*!< IrDA normal power mode */
+#define LL_USART_IRDA_POWER_LOW                 USART_CR3_IRLP        /*!< IrDA low power mode */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length
+  * @{
+  */
+#define LL_USART_LINBREAK_DETECT_10B            0x00000000U           /*!< 10-bit break detection method selected */
+#define LL_USART_LINBREAK_DETECT_11B            USART_CR2_LBDL        /*!< 11-bit break detection method selected */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity
+  * @{
+  */
+#define LL_USART_DE_POLARITY_HIGH               0x00000000U           /*!< DE signal is active high */
+#define LL_USART_DE_POLARITY_LOW                USART_CR3_DEP         /*!< DE signal is active low */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data
+  * @{
+  */
+#define LL_USART_DMA_REG_DATA_TRANSMIT          0x00000000U          /*!< Get address of data register used for transmission */
+#define LL_USART_DMA_REG_DATA_RECEIVE           0x00000001U          /*!< Get address of data register used for reception */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup USART_LL_Exported_Macros USART Exported Macros
+  * @{
+  */
+
+/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in USART register
+  * @param  __INSTANCE__ USART Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in USART register
+  * @param  __INSTANCE__ USART Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
+  * @{
+  */
+
+/**
+  * @brief  Compute USARTDIV value according to Peripheral Clock and
+  *         expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
+  * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
+  * @param  __PRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PRESCALER_DIV1
+  *         @arg @ref LL_USART_PRESCALER_DIV2
+  *         @arg @ref LL_USART_PRESCALER_DIV4
+  *         @arg @ref LL_USART_PRESCALER_DIV6
+  *         @arg @ref LL_USART_PRESCALER_DIV8
+  *         @arg @ref LL_USART_PRESCALER_DIV10
+  *         @arg @ref LL_USART_PRESCALER_DIV12
+  *         @arg @ref LL_USART_PRESCALER_DIV16
+  *         @arg @ref LL_USART_PRESCALER_DIV32
+  *         @arg @ref LL_USART_PRESCALER_DIV64
+  *         @arg @ref LL_USART_PRESCALER_DIV128
+  *         @arg @ref LL_USART_PRESCALER_DIV256
+  * @param  __BAUDRATE__ Baud rate value to achieve
+  * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
+  */
+#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\
+                                                                               + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
+
+/**
+  * @brief  Compute USARTDIV value according to Peripheral Clock and
+  *         expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
+  * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
+  * @param  __PRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PRESCALER_DIV1
+  *         @arg @ref LL_USART_PRESCALER_DIV2
+  *         @arg @ref LL_USART_PRESCALER_DIV4
+  *         @arg @ref LL_USART_PRESCALER_DIV6
+  *         @arg @ref LL_USART_PRESCALER_DIV8
+  *         @arg @ref LL_USART_PRESCALER_DIV10
+  *         @arg @ref LL_USART_PRESCALER_DIV12
+  *         @arg @ref LL_USART_PRESCALER_DIV16
+  *         @arg @ref LL_USART_PRESCALER_DIV32
+  *         @arg @ref LL_USART_PRESCALER_DIV64
+  *         @arg @ref LL_USART_PRESCALER_DIV128
+  *         @arg @ref LL_USART_PRESCALER_DIV256
+  * @param  __BAUDRATE__ Baud rate value to achieve
+  * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
+  */
+#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) ((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\
+                                                                                + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup USART_LL_Exported_Functions USART Exported Functions
+  * @{
+  */
+
+/** @defgroup USART_LL_EF_Configuration Configuration functions
+  * @{
+  */
+
+/**
+  * @brief  USART Enable
+  * @rmtoll CR1          UE            LL_USART_Enable
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_UE);
+}
+
+/**
+  * @brief  USART Disable (all USART prescalers and outputs are disabled)
+  * @note   When USART is disabled, USART prescalers and outputs are stopped immediately,
+  *         and current operations are discarded. The configuration of the USART is kept, but all the status
+  *         flags, in the USARTx_ISR are set to their default values.
+  * @rmtoll CR1          UE            LL_USART_Disable
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_UE);
+}
+
+/**
+  * @brief  Indicate if USART is enabled
+  * @rmtoll CR1          UE            LL_USART_IsEnabled
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  FIFO Mode Enable
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          FIFOEN        LL_USART_EnableFIFO
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableFIFO(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_FIFOEN);
+}
+
+/**
+  * @brief  FIFO Mode Disable
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          FIFOEN        LL_USART_DisableFIFO
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableFIFO(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_FIFOEN);
+}
+
+/**
+  * @brief  Indicate if FIFO Mode is enabled
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          FIFOEN        LL_USART_IsEnabledFIFO
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure TX FIFO Threshold
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          TXFTCFG       LL_USART_SetTXFIFOThreshold
+  * @param  USARTx USART Instance
+  * @param  Threshold This parameter can be one of the following values:
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
+}
+
+/**
+  * @brief  Return TX FIFO Threshold Configuration
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          TXFTCFG       LL_USART_GetTXFIFOThreshold
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
+}
+
+/**
+  * @brief  Configure RX FIFO Threshold
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          RXFTCFG       LL_USART_SetRXFIFOThreshold
+  * @param  USARTx USART Instance
+  * @param  Threshold This parameter can be one of the following values:
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
+}
+
+/**
+  * @brief  Return RX FIFO Threshold Configuration
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          RXFTCFG       LL_USART_GetRXFIFOThreshold
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+  */
+__STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
+}
+
+/**
+  * @brief  Configure TX and RX FIFOs Threshold
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          TXFTCFG       LL_USART_ConfigFIFOsThreshold\n
+  *         CR3          RXFTCFG       LL_USART_ConfigFIFOsThreshold
+  * @param  USARTx USART Instance
+  * @param  TXThreshold This parameter can be one of the following values:
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+  * @param  RXThreshold This parameter can be one of the following values:
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | (RXThreshold << USART_CR3_RXFTCFG_Pos));
+}
+
+/**
+  * @brief  USART enabled in STOP Mode.
+  * @note   When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that
+  *         USART clock selection is HSI or LSE in RCC.
+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          UESM          LL_USART_EnableInStopMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+  * @brief  USART disabled in STOP Mode.
+  * @note   When this function is disabled, USART is not able to wake up the MCU from Stop mode
+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          UESM          LL_USART_DisableInStopMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+  * @brief  Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          UESM          LL_USART_IsEnabledInStopMode
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)
+  * @rmtoll CR1          RE            LL_USART_EnableDirectionRx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_RE);
+}
+
+/**
+  * @brief  Receiver Disable
+  * @rmtoll CR1          RE            LL_USART_DisableDirectionRx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
+}
+
+/**
+  * @brief  Transmitter Enable
+  * @rmtoll CR1          TE            LL_USART_EnableDirectionTx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_TE);
+}
+
+/**
+  * @brief  Transmitter Disable
+  * @rmtoll CR1          TE            LL_USART_DisableDirectionTx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
+}
+
+/**
+  * @brief  Configure simultaneously enabled/disabled states
+  *         of Transmitter and Receiver
+  * @rmtoll CR1          RE            LL_USART_SetTransferDirection\n
+  *         CR1          TE            LL_USART_SetTransferDirection
+  * @param  USARTx USART Instance
+  * @param  TransferDirection This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DIRECTION_NONE
+  *         @arg @ref LL_USART_DIRECTION_RX
+  *         @arg @ref LL_USART_DIRECTION_TX
+  *         @arg @ref LL_USART_DIRECTION_TX_RX
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
+}
+
+/**
+  * @brief  Return enabled/disabled states of Transmitter and Receiver
+  * @rmtoll CR1          RE            LL_USART_GetTransferDirection\n
+  *         CR1          TE            LL_USART_GetTransferDirection
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_DIRECTION_NONE
+  *         @arg @ref LL_USART_DIRECTION_RX
+  *         @arg @ref LL_USART_DIRECTION_TX
+  *         @arg @ref LL_USART_DIRECTION_TX_RX
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
+}
+
+/**
+  * @brief  Configure Parity (enabled/disabled and parity mode if enabled).
+  * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.
+  *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
+  *         (9th or 8th bit depending on data width) and parity is checked on the received data.
+  * @rmtoll CR1          PS            LL_USART_SetParity\n
+  *         CR1          PCE           LL_USART_SetParity
+  * @param  USARTx USART Instance
+  * @param  Parity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PARITY_NONE
+  *         @arg @ref LL_USART_PARITY_EVEN
+  *         @arg @ref LL_USART_PARITY_ODD
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
+}
+
+/**
+  * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)
+  * @rmtoll CR1          PS            LL_USART_GetParity\n
+  *         CR1          PCE           LL_USART_GetParity
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_PARITY_NONE
+  *         @arg @ref LL_USART_PARITY_EVEN
+  *         @arg @ref LL_USART_PARITY_ODD
+  */
+__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
+}
+
+/**
+  * @brief  Set Receiver Wake Up method from Mute mode.
+  * @rmtoll CR1          WAKE          LL_USART_SetWakeUpMethod
+  * @param  USARTx USART Instance
+  * @param  Method This parameter can be one of the following values:
+  *         @arg @ref LL_USART_WAKEUP_IDLELINE
+  *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);
+}
+
+/**
+  * @brief  Return Receiver Wake Up method from Mute mode
+  * @rmtoll CR1          WAKE          LL_USART_GetWakeUpMethod
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_WAKEUP_IDLELINE
+  *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
+  */
+__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
+}
+
+/**
+  * @brief  Set Word length (i.e. nb of data bits, excluding start and stop bits)
+  * @rmtoll CR1          M0            LL_USART_SetDataWidth\n
+  *         CR1          M1            LL_USART_SetDataWidth
+  * @param  USARTx USART Instance
+  * @param  DataWidth This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DATAWIDTH_7B
+  *         @arg @ref LL_USART_DATAWIDTH_8B
+  *         @arg @ref LL_USART_DATAWIDTH_9B
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);
+}
+
+/**
+  * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)
+  * @rmtoll CR1          M0            LL_USART_GetDataWidth\n
+  *         CR1          M1            LL_USART_GetDataWidth
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_DATAWIDTH_7B
+  *         @arg @ref LL_USART_DATAWIDTH_8B
+  *         @arg @ref LL_USART_DATAWIDTH_9B
+  */
+__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
+}
+
+/**
+  * @brief  Allow switch between Mute Mode and Active mode
+  * @rmtoll CR1          MME           LL_USART_EnableMuteMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_MME);
+}
+
+/**
+  * @brief  Prevent Mute Mode use. Set Receiver in active mode permanently.
+  * @rmtoll CR1          MME           LL_USART_DisableMuteMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_MME);
+}
+
+/**
+  * @brief  Indicate if switch between Mute Mode and Active mode is allowed
+  * @rmtoll CR1          MME           LL_USART_IsEnabledMuteMode
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set Oversampling to 8-bit or 16-bit mode
+  * @rmtoll CR1          OVER8         LL_USART_SetOverSampling
+  * @param  USARTx USART Instance
+  * @param  OverSampling This parameter can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);
+}
+
+/**
+  * @brief  Return Oversampling mode
+  * @rmtoll CR1          OVER8         LL_USART_GetOverSampling
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  */
+__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
+}
+
+/**
+  * @brief  Configure if Clock pulse of the last data bit is output to the SCLK pin or not
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          LBCL          LL_USART_SetLastClkPulseOutput
+  * @param  USARTx USART Instance
+  * @param  LastBitClockPulse This parameter can be one of the following values:
+  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);
+}
+
+/**
+  * @brief  Retrieve Clock pulse of the last data bit output configuration
+  *         (Last bit Clock pulse output to the SCLK pin or not)
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          LBCL          LL_USART_GetLastClkPulseOutput
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+  */
+__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
+}
+
+/**
+  * @brief  Select the phase of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPHA          LL_USART_SetClockPhase
+  * @param  USARTx USART Instance
+  * @param  ClockPhase This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PHASE_1EDGE
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);
+}
+
+/**
+  * @brief  Return phase of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPHA          LL_USART_GetClockPhase
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_PHASE_1EDGE
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  */
+__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
+}
+
+/**
+  * @brief  Select the polarity of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPOL          LL_USART_SetClockPolarity
+  * @param  USARTx USART Instance
+  * @param  ClockPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_POLARITY_LOW
+  *         @arg @ref LL_USART_POLARITY_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);
+}
+
+/**
+  * @brief  Return polarity of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPOL          LL_USART_GetClockPolarity
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_POLARITY_LOW
+  *         @arg @ref LL_USART_POLARITY_HIGH
+  */
+__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
+}
+
+/**
+  * @brief  Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
+  *         - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function
+  *         - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function
+  * @rmtoll CR2          CPHA          LL_USART_ConfigClock\n
+  *         CR2          CPOL          LL_USART_ConfigClock\n
+  *         CR2          LBCL          LL_USART_ConfigClock
+  * @param  USARTx USART Instance
+  * @param  Phase This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PHASE_1EDGE
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_POLARITY_LOW
+  *         @arg @ref LL_USART_POLARITY_HIGH
+  * @param  LBCPOutput This parameter can be one of the following values:
+  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput);
+}
+
+/**
+  * @brief  Configure Clock source prescaler for baudrate generator and oversampling
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll PRESC        PRESCALER     LL_USART_SetPrescaler
+  * @param  USARTx USART Instance
+  * @param  PrescalerValue This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PRESCALER_DIV1
+  *         @arg @ref LL_USART_PRESCALER_DIV2
+  *         @arg @ref LL_USART_PRESCALER_DIV4
+  *         @arg @ref LL_USART_PRESCALER_DIV6
+  *         @arg @ref LL_USART_PRESCALER_DIV8
+  *         @arg @ref LL_USART_PRESCALER_DIV10
+  *         @arg @ref LL_USART_PRESCALER_DIV12
+  *         @arg @ref LL_USART_PRESCALER_DIV16
+  *         @arg @ref LL_USART_PRESCALER_DIV32
+  *         @arg @ref LL_USART_PRESCALER_DIV64
+  *         @arg @ref LL_USART_PRESCALER_DIV128
+  *         @arg @ref LL_USART_PRESCALER_DIV256
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+{
+  MODIFY_REG(USARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
+}
+
+/**
+  * @brief  Retrieve the Clock source prescaler for baudrate generator and oversampling
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll PRESC        PRESCALER     LL_USART_GetPrescaler
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_PRESCALER_DIV1
+  *         @arg @ref LL_USART_PRESCALER_DIV2
+  *         @arg @ref LL_USART_PRESCALER_DIV4
+  *         @arg @ref LL_USART_PRESCALER_DIV6
+  *         @arg @ref LL_USART_PRESCALER_DIV8
+  *         @arg @ref LL_USART_PRESCALER_DIV10
+  *         @arg @ref LL_USART_PRESCALER_DIV12
+  *         @arg @ref LL_USART_PRESCALER_DIV16
+  *         @arg @ref LL_USART_PRESCALER_DIV32
+  *         @arg @ref LL_USART_PRESCALER_DIV64
+  *         @arg @ref LL_USART_PRESCALER_DIV128
+  *         @arg @ref LL_USART_PRESCALER_DIV256
+  */
+__STATIC_INLINE uint32_t LL_USART_GetPrescaler(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->PRESC, USART_PRESC_PRESCALER));
+}
+
+/**
+  * @brief  Enable Clock output on SCLK pin
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CLKEN         LL_USART_EnableSCLKOutput
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+  * @brief  Disable Clock output on SCLK pin
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CLKEN         LL_USART_DisableSCLKOutput
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+  * @brief  Indicate if Clock output on SCLK pin is enabled
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CLKEN         LL_USART_IsEnabledSCLKOutput
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the length of the stop bits
+  * @rmtoll CR2          STOP          LL_USART_SetStopBitsLength
+  * @param  USARTx USART Instance
+  * @param  StopBits This parameter can be one of the following values:
+  *         @arg @ref LL_USART_STOPBITS_0_5
+  *         @arg @ref LL_USART_STOPBITS_1
+  *         @arg @ref LL_USART_STOPBITS_1_5
+  *         @arg @ref LL_USART_STOPBITS_2
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+  * @brief  Retrieve the length of the stop bits
+  * @rmtoll CR2          STOP          LL_USART_GetStopBitsLength
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_STOPBITS_0_5
+  *         @arg @ref LL_USART_STOPBITS_1
+  *         @arg @ref LL_USART_STOPBITS_1_5
+  *         @arg @ref LL_USART_STOPBITS_2
+  */
+__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
+}
+
+/**
+  * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Data Width configuration using @ref LL_USART_SetDataWidth() function
+  *         - Parity Control and mode configuration using @ref LL_USART_SetParity() function
+  *         - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function
+  * @rmtoll CR1          PS            LL_USART_ConfigCharacter\n
+  *         CR1          PCE           LL_USART_ConfigCharacter\n
+  *         CR1          M0            LL_USART_ConfigCharacter\n
+  *         CR1          M1            LL_USART_ConfigCharacter\n
+  *         CR2          STOP          LL_USART_ConfigCharacter
+  * @param  USARTx USART Instance
+  * @param  DataWidth This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DATAWIDTH_7B
+  *         @arg @ref LL_USART_DATAWIDTH_8B
+  *         @arg @ref LL_USART_DATAWIDTH_9B
+  * @param  Parity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PARITY_NONE
+  *         @arg @ref LL_USART_PARITY_EVEN
+  *         @arg @ref LL_USART_PARITY_ODD
+  * @param  StopBits This parameter can be one of the following values:
+  *         @arg @ref LL_USART_STOPBITS_0_5
+  *         @arg @ref LL_USART_STOPBITS_1
+  *         @arg @ref LL_USART_STOPBITS_1_5
+  *         @arg @ref LL_USART_STOPBITS_2
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity,
+                                              uint32_t StopBits)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
+  MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+  * @brief  Configure TX/RX pins swapping setting.
+  * @rmtoll CR2          SWAP          LL_USART_SetTXRXSwap
+  * @param  USARTx USART Instance
+  * @param  SwapConfig This parameter can be one of the following values:
+  *         @arg @ref LL_USART_TXRX_STANDARD
+  *         @arg @ref LL_USART_TXRX_SWAPPED
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig);
+}
+
+/**
+  * @brief  Retrieve TX/RX pins swapping configuration.
+  * @rmtoll CR2          SWAP          LL_USART_GetTXRXSwap
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_TXRX_STANDARD
+  *         @arg @ref LL_USART_TXRX_SWAPPED
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP));
+}
+
+/**
+  * @brief  Configure RX pin active level logic
+  * @rmtoll CR2          RXINV         LL_USART_SetRXPinLevel
+  * @param  USARTx USART Instance
+  * @param  PinInvMethod This parameter can be one of the following values:
+  *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod);
+}
+
+/**
+  * @brief  Retrieve RX pin active level logic configuration
+  * @rmtoll CR2          RXINV         LL_USART_GetRXPinLevel
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
+  */
+__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV));
+}
+
+/**
+  * @brief  Configure TX pin active level logic
+  * @rmtoll CR2          TXINV         LL_USART_SetTXPinLevel
+  * @param  USARTx USART Instance
+  * @param  PinInvMethod This parameter can be one of the following values:
+  *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod);
+}
+
+/**
+  * @brief  Retrieve TX pin active level logic configuration
+  * @rmtoll CR2          TXINV         LL_USART_GetTXPinLevel
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV));
+}
+
+/**
+  * @brief  Configure Binary data logic.
+  * @note   Allow to define how Logical data from the data register are send/received :
+  *         either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
+  * @rmtoll CR2          DATAINV       LL_USART_SetBinaryDataLogic
+  * @param  USARTx USART Instance
+  * @param  DataLogic This parameter can be one of the following values:
+  *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
+  *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic);
+}
+
+/**
+  * @brief  Retrieve Binary data configuration
+  * @rmtoll CR2          DATAINV       LL_USART_GetBinaryDataLogic
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
+  *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
+  */
+__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV));
+}
+
+/**
+  * @brief  Configure transfer bit order (either Less or Most Significant Bit First)
+  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
+  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
+  * @rmtoll CR2          MSBFIRST      LL_USART_SetTransferBitOrder
+  * @param  USARTx USART Instance
+  * @param  BitOrder This parameter can be one of the following values:
+  *         @arg @ref LL_USART_BITORDER_LSBFIRST
+  *         @arg @ref LL_USART_BITORDER_MSBFIRST
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
+}
+
+/**
+  * @brief  Return transfer bit order (either Less or Most Significant Bit First)
+  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
+  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
+  * @rmtoll CR2          MSBFIRST      LL_USART_GetTransferBitOrder
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_BITORDER_LSBFIRST
+  *         @arg @ref LL_USART_BITORDER_MSBFIRST
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST));
+}
+
+/**
+  * @brief  Enable Auto Baud-Rate Detection
+  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABREN         LL_USART_EnableAutoBaudRate
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_ABREN);
+}
+
+/**
+  * @brief  Disable Auto Baud-Rate Detection
+  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABREN         LL_USART_DisableAutoBaudRate
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN);
+}
+
+/**
+  * @brief  Indicate if Auto Baud-Rate Detection mechanism is enabled
+  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABREN         LL_USART_IsEnabledAutoBaud
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set Auto Baud-Rate mode bits
+  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABRMODE       LL_USART_SetAutoBaudRateMode
+  * @param  USARTx USART Instance
+  * @param  AutoBaudRateMode This parameter can be one of the following values:
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode);
+}
+
+/**
+  * @brief  Return Auto Baud-Rate mode
+  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABRMODE       LL_USART_GetAutoBaudRateMode
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
+  */
+__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE));
+}
+
+/**
+  * @brief  Enable Receiver Timeout
+  * @rmtoll CR2          RTOEN         LL_USART_EnableRxTimeout
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_RTOEN);
+}
+
+/**
+  * @brief  Disable Receiver Timeout
+  * @rmtoll CR2          RTOEN         LL_USART_DisableRxTimeout
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN);
+}
+
+/**
+  * @brief  Indicate if Receiver Timeout feature is enabled
+  * @rmtoll CR2          RTOEN         LL_USART_IsEnabledRxTimeout
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set Address of the USART node.
+  * @note   This is used in multiprocessor communication during Mute mode or Stop mode,
+  *         for wake up with address mark detection.
+  * @note   4bits address node is used when 4-bit Address Detection is selected in ADDM7.
+  *         (b7-b4 should be set to 0)
+  *         8bits address node is used when 7-bit Address Detection is selected in ADDM7.
+  *         (This is used in multiprocessor communication during Mute mode or Stop mode,
+  *         for wake up with 7-bit address mark detection.
+  *         The MSB of the character sent by the transmitter should be equal to 1.
+  *         It may also be used for character detection during normal reception,
+  *         Mute mode inactive (for example, end of block detection in ModBus protocol).
+  *         In this case, the whole received character (8-bit) is compared to the ADD[7:0]
+  *         value and CMF flag is set on match)
+  * @rmtoll CR2          ADD           LL_USART_ConfigNodeAddress\n
+  *         CR2          ADDM7         LL_USART_ConfigNodeAddress
+  * @param  USARTx USART Instance
+  * @param  AddressLen This parameter can be one of the following values:
+  *         @arg @ref LL_USART_ADDRESS_DETECT_4B
+  *         @arg @ref LL_USART_ADDRESS_DETECT_7B
+  * @param  NodeAddress 4 or 7 bit Address of the USART node.
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
+             (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
+}
+
+/**
+  * @brief  Return 8 bit Address of the USART node as set in ADD field of CR2.
+  * @note   If 4-bit Address Detection is selected in ADDM7,
+  *         only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
+  *         If 7-bit Address Detection is selected in ADDM7,
+  *         only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
+  * @rmtoll CR2          ADD           LL_USART_GetNodeAddress
+  * @param  USARTx USART Instance
+  * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
+}
+
+/**
+  * @brief  Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
+  * @rmtoll CR2          ADDM7         LL_USART_GetNodeAddressLen
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_ADDRESS_DETECT_4B
+  *         @arg @ref LL_USART_ADDRESS_DETECT_7B
+  */
+__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7));
+}
+
+/**
+  * @brief  Enable RTS HW Flow Control
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_EnableRTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+  * @brief  Disable RTS HW Flow Control
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_DisableRTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+  * @brief  Enable CTS HW Flow Control
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSE          LL_USART_EnableCTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+  * @brief  Disable CTS HW Flow Control
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSE          LL_USART_DisableCTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+  * @brief  Configure HW Flow Control mode (both CTS and RTS)
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_SetHWFlowCtrl\n
+  *         CR3          CTSE          LL_USART_SetHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @param  HardwareFlowControl This parameter can be one of the following values:
+  *         @arg @ref LL_USART_HWCONTROL_NONE
+  *         @arg @ref LL_USART_HWCONTROL_RTS
+  *         @arg @ref LL_USART_HWCONTROL_CTS
+  *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
+}
+
+/**
+  * @brief  Return HW Flow Control configuration (both CTS and RTS)
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_GetHWFlowCtrl\n
+  *         CR3          CTSE          LL_USART_GetHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_HWCONTROL_NONE
+  *         @arg @ref LL_USART_HWCONTROL_RTS
+  *         @arg @ref LL_USART_HWCONTROL_CTS
+  *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
+  */
+__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
+}
+
+/**
+  * @brief  Enable One bit sampling method
+  * @rmtoll CR3          ONEBIT        LL_USART_EnableOneBitSamp
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);
+}
+
+/**
+  * @brief  Disable One bit sampling method
+  * @rmtoll CR3          ONEBIT        LL_USART_DisableOneBitSamp
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);
+}
+
+/**
+  * @brief  Indicate if One bit sampling method is enabled
+  * @rmtoll CR3          ONEBIT        LL_USART_IsEnabledOneBitSamp
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Overrun detection
+  * @rmtoll CR3          OVRDIS        LL_USART_EnableOverrunDetect
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+  * @brief  Disable Overrun detection
+  * @rmtoll CR3          OVRDIS        LL_USART_DisableOverrunDetect
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+  * @brief  Indicate if Overrun detection is enabled
+  * @rmtoll CR3          OVRDIS        LL_USART_IsEnabledOverrunDetect
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUS           LL_USART_SetWKUPType
+  * @param  USARTx USART Instance
+  * @param  Type This parameter can be one of the following values:
+  *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
+  *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
+  *         @arg @ref LL_USART_WAKEUP_ON_RXNE
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type);
+}
+
+/**
+  * @brief  Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUS           LL_USART_GetWKUPType
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
+  *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
+  *         @arg @ref LL_USART_WAKEUP_ON_RXNE
+  */
+__STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS));
+}
+
+/**
+  * @brief  Configure USART BRR register for achieving expected Baud Rate value.
+  * @note   Compute and set USARTDIV value in BRR Register (full BRR content)
+  *         according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
+  * @note   Peripheral clock and Baud rate values provided as function parameters should be valid
+  *         (Baud rate value != 0)
+  * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
+  * @rmtoll BRR          BRR           LL_USART_SetBaudRate
+  * @param  USARTx USART Instance
+  * @param  PeriphClk Peripheral Clock
+  * @param  PrescalerValue This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PRESCALER_DIV1
+  *         @arg @ref LL_USART_PRESCALER_DIV2
+  *         @arg @ref LL_USART_PRESCALER_DIV4
+  *         @arg @ref LL_USART_PRESCALER_DIV6
+  *         @arg @ref LL_USART_PRESCALER_DIV8
+  *         @arg @ref LL_USART_PRESCALER_DIV10
+  *         @arg @ref LL_USART_PRESCALER_DIV12
+  *         @arg @ref LL_USART_PRESCALER_DIV16
+  *         @arg @ref LL_USART_PRESCALER_DIV32
+  *         @arg @ref LL_USART_PRESCALER_DIV64
+  *         @arg @ref LL_USART_PRESCALER_DIV128
+  *         @arg @ref LL_USART_PRESCALER_DIV256
+  * @param  OverSampling This parameter can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  * @param  BaudRate Baud Rate
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
+                                          uint32_t OverSampling,
+                                          uint32_t BaudRate)
+{
+  uint32_t usartdiv;
+  register uint32_t brrtemp;
+
+  if (PrescalerValue > LL_USART_PRESCALER_DIV256)
+  {
+    /* Do not overstep the size of USART_PRESCALER_TAB */
+  }
+  else if (OverSampling == LL_USART_OVERSAMPLING_8)
+  {
+    usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint8_t)PrescalerValue, BaudRate));
+    brrtemp = usartdiv & 0xFFF0U;
+    brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+    USARTx->BRR = brrtemp;
+  }
+  else
+  {
+    USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, (uint8_t)PrescalerValue, BaudRate));
+  }
+}
+
+/**
+  * @brief  Return current Baud Rate value, according to USARTDIV present in BRR register
+  *         (full BRR content), and to used Peripheral Clock and Oversampling mode values
+  * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
+  * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
+  * @rmtoll BRR          BRR           LL_USART_GetBaudRate
+  * @param  USARTx USART Instance
+  * @param  PeriphClk Peripheral Clock
+  * @param  PrescalerValue This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PRESCALER_DIV1
+  *         @arg @ref LL_USART_PRESCALER_DIV2
+  *         @arg @ref LL_USART_PRESCALER_DIV4
+  *         @arg @ref LL_USART_PRESCALER_DIV6
+  *         @arg @ref LL_USART_PRESCALER_DIV8
+  *         @arg @ref LL_USART_PRESCALER_DIV10
+  *         @arg @ref LL_USART_PRESCALER_DIV12
+  *         @arg @ref LL_USART_PRESCALER_DIV16
+  *         @arg @ref LL_USART_PRESCALER_DIV32
+  *         @arg @ref LL_USART_PRESCALER_DIV64
+  *         @arg @ref LL_USART_PRESCALER_DIV128
+  *         @arg @ref LL_USART_PRESCALER_DIV256
+  * @param  OverSampling This parameter can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  * @retval Baud Rate
+  */
+__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
+                                              uint32_t OverSampling)
+{
+  register uint32_t usartdiv;
+  register uint32_t brrresult = 0x0U;
+  register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (USART_PRESCALER_TAB[(uint8_t)PrescalerValue]));
+
+  usartdiv = USARTx->BRR;
+
+  if (usartdiv == 0U)
+  {
+    /* Do not perform a division by 0 */
+  }
+  else if (OverSampling == LL_USART_OVERSAMPLING_8)
+  {
+    usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
+    if (usartdiv != 0U)
+    {
+      brrresult = (periphclkpresc * 2U) / usartdiv;
+    }
+  }
+  else
+  {
+    if ((usartdiv & 0xFFFFU) != 0U)
+    {
+      brrresult = periphclkpresc / usartdiv;
+    }
+  }
+  return (brrresult);
+}
+
+/**
+  * @brief  Set Receiver Time Out Value (expressed in nb of bits duration)
+  * @rmtoll RTOR         RTO           LL_USART_SetRxTimeout
+  * @param  USARTx USART Instance
+  * @param  Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout)
+{
+  MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout);
+}
+
+/**
+  * @brief  Get Receiver Time Out Value (expressed in nb of bits duration)
+  * @rmtoll RTOR         RTO           LL_USART_GetRxTimeout
+  * @param  USARTx USART Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
+  */
+__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO));
+}
+
+/**
+  * @brief  Set Block Length value in reception
+  * @rmtoll RTOR         BLEN          LL_USART_SetBlockLength
+  * @param  USARTx USART Instance
+  * @param  BlockLength Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength)
+{
+  MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos);
+}
+
+/**
+  * @brief  Get Block Length value in reception
+  * @rmtoll RTOR         BLEN          LL_USART_GetBlockLength
+  * @param  USARTx USART Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_USART_GetBlockLength(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature
+  * @{
+  */
+
+/**
+  * @brief  Enable IrDA mode
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IREN          LL_USART_EnableIrda
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+  * @brief  Disable IrDA mode
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IREN          LL_USART_DisableIrda
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+  * @brief  Indicate if IrDA mode is enabled
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IREN          LL_USART_IsEnabledIrda
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure IrDA Power Mode (Normal or Low Power)
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IRLP          LL_USART_SetIrdaPowerMode
+  * @param  USARTx USART Instance
+  * @param  PowerMode This parameter can be one of the following values:
+  *         @arg @ref LL_USART_IRDA_POWER_NORMAL
+  *         @arg @ref LL_USART_IRDA_POWER_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);
+}
+
+/**
+  * @brief  Retrieve IrDA Power Mode configuration (Normal or Low Power)
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IRLP          LL_USART_GetIrdaPowerMode
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_IRDA_POWER_NORMAL
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  */
+__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
+}
+
+/**
+  * @brief  Set Irda prescaler value, used for dividing the USART clock source
+  *         to achieve the Irda Low Power frequency (8 bits value)
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_SetIrdaPrescaler
+  * @param  USARTx USART Instance
+  * @param  PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+{
+  MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)PrescalerValue);
+}
+
+/**
+  * @brief  Return Irda prescaler value, used for dividing the USART clock source
+  *         to achieve the Irda Low Power frequency (8 bits value)
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_GetIrdaPrescaler
+  * @param  USARTx USART Instance
+  * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature
+  * @{
+  */
+
+/**
+  * @brief  Enable Smartcard NACK transmission
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          NACK          LL_USART_EnableSmartcardNACK
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_NACK);
+}
+
+/**
+  * @brief  Disable Smartcard NACK transmission
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          NACK          LL_USART_DisableSmartcardNACK
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);
+}
+
+/**
+  * @brief  Indicate if Smartcard NACK transmission is enabled
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          NACK          LL_USART_IsEnabledSmartcardNACK
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Smartcard mode
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCEN          LL_USART_EnableSmartcard
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+  * @brief  Disable Smartcard mode
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCEN          LL_USART_DisableSmartcard
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+  * @brief  Indicate if Smartcard mode is enabled
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCEN          LL_USART_IsEnabledSmartcard
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @note   This bit-field specifies the number of retries in transmit and receive, in Smartcard mode.
+  *         In transmission mode, it specifies the number of automatic retransmission retries, before
+  *         generating a transmission error (FE bit set).
+  *         In reception mode, it specifies the number or erroneous reception trials, before generating a
+  *         reception error (RXNE and PE bits set)
+  * @rmtoll CR3          SCARCNT       LL_USART_SetSmartcardAutoRetryCount
+  * @param  USARTx USART Instance
+  * @param  AutoRetryCount Value between Min_Data=0 and Max_Data=7
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos);
+}
+
+/**
+  * @brief  Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCARCNT       LL_USART_GetSmartcardAutoRetryCount
+  * @param  USARTx USART Instance
+  * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos);
+}
+
+/**
+  * @brief  Set Smartcard prescaler value, used for dividing the USART clock
+  *         source to provide the SMARTCARD Clock (5 bits value)
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_SetSmartcardPrescaler
+  * @param  USARTx USART Instance
+  * @param  PrescalerValue Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+{
+  MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)PrescalerValue);
+}
+
+/**
+  * @brief  Return Smartcard prescaler value, used for dividing the USART clock
+  *         source to provide the SMARTCARD Clock (5 bits value)
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_GetSmartcardPrescaler
+  * @param  USARTx USART Instance
+  * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
+}
+
+/**
+  * @brief  Set Smartcard Guard time value, expressed in nb of baud clocks periods
+  *         (GT[7:0] bits : Guard time value)
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         GT            LL_USART_SetSmartcardGuardTime
+  * @param  USARTx USART Instance
+  * @param  GuardTime Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
+{
+  MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos));
+}
+
+/**
+  * @brief  Return Smartcard Guard time value, expressed in nb of baud clocks periods
+  *         (GT[7:0] bits : Guard time value)
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         GT            LL_USART_GetSmartcardGuardTime
+  * @param  USARTx USART Instance
+  * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
+  * @{
+  */
+
+/**
+  * @brief  Enable Single Wire Half-Duplex mode
+  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @rmtoll CR3          HDSEL         LL_USART_EnableHalfDuplex
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Disable Single Wire Half-Duplex mode
+  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @rmtoll CR3          HDSEL         LL_USART_DisableHalfDuplex
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Indicate if Single Wire Half-Duplex mode is enabled
+  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @rmtoll CR3          HDSEL         LL_USART_IsEnabledHalfDuplex
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_SPI_SLAVE Configuration functions related to SPI Slave feature
+  * @{
+  */
+/**
+  * @brief  Enable SPI Synchronous Slave mode
+  * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @rmtoll CR2          SLVEN         LL_USART_EnableSPISlave
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSPISlave(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_SLVEN);
+}
+
+/**
+  * @brief  Disable SPI Synchronous Slave mode
+  * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @rmtoll CR2          SLVEN         LL_USART_DisableSPISlave
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_SLVEN);
+}
+
+/**
+  * @brief  Indicate if  SPI Synchronous Slave mode is enabled
+  * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @rmtoll CR2          SLVEN         LL_USART_IsEnabledSPISlave
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_SLVEN) == (USART_CR2_SLVEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable SPI Slave Selection using NSS input pin
+  * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @note   SPI Slave Selection depends on NSS input pin
+  *         (The slave is selected when NSS is low and deselected when NSS is high).
+  * @rmtoll CR2          DIS_NSS       LL_USART_EnableSPISlaveSelect
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSPISlaveSelect(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_DIS_NSS);
+}
+
+/**
+  * @brief  Disable SPI Slave Selection using NSS input pin
+  * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @note   SPI Slave will be always selected and NSS input pin will be ignored.
+  * @rmtoll CR2          DIS_NSS       LL_USART_DisableSPISlaveSelect
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_DIS_NSS);
+}
+
+/**
+  * @brief  Indicate if  SPI Slave Selection depends on NSS input pin
+  * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @rmtoll CR2          DIS_NSS       LL_USART_IsEnabledSPISlaveSelect
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_DIS_NSS) != (USART_CR2_DIS_NSS)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature
+  * @{
+  */
+
+/**
+  * @brief  Set LIN Break Detection Length
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDL          LL_USART_SetLINBrkDetectionLen
+  * @param  USARTx USART Instance
+  * @param  LINBDLength This parameter can be one of the following values:
+  *         @arg @ref LL_USART_LINBREAK_DETECT_10B
+  *         @arg @ref LL_USART_LINBREAK_DETECT_11B
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);
+}
+
+/**
+  * @brief  Return LIN Break Detection Length
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDL          LL_USART_GetLINBrkDetectionLen
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_LINBREAK_DETECT_10B
+  *         @arg @ref LL_USART_LINBREAK_DETECT_11B
+  */
+__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
+}
+
+/**
+  * @brief  Enable LIN mode
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LINEN         LL_USART_EnableLIN
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+  * @brief  Disable LIN mode
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LINEN         LL_USART_DisableLIN
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+  * @brief  Indicate if LIN mode is enabled
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LINEN         LL_USART_IsEnabledLIN
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
+  * @{
+  */
+
+/**
+  * @brief  Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR1          DEDT          LL_USART_SetDEDeassertionTime
+  * @param  USARTx USART Instance
+  * @param  Time Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
+}
+
+/**
+  * @brief  Return DEDT (Driver Enable De-Assertion Time)
+  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR1          DEDT          LL_USART_GetDEDeassertionTime
+  * @param  USARTx USART Instance
+  * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
+  */
+__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
+}
+
+/**
+  * @brief  Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR1          DEAT          LL_USART_SetDEAssertionTime
+  * @param  USARTx USART Instance
+  * @param  Time Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
+}
+
+/**
+  * @brief  Return DEAT (Driver Enable Assertion Time)
+  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR1          DEAT          LL_USART_GetDEAssertionTime
+  * @param  USARTx USART Instance
+  * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
+  */
+__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
+}
+
+/**
+  * @brief  Enable Driver Enable (DE) Mode
+  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEM           LL_USART_EnableDEMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+  * @brief  Disable Driver Enable (DE) Mode
+  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEM           LL_USART_DisableDEMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+  * @brief  Indicate if Driver Enable (DE) Mode is enabled
+  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEM           LL_USART_IsEnabledDEMode
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Select Driver Enable Polarity
+  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEP           LL_USART_SetDESignalPolarity
+  * @param  USARTx USART Instance
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DE_POLARITY_HIGH
+  *         @arg @ref LL_USART_DE_POLARITY_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity);
+}
+
+/**
+  * @brief  Return Driver Enable Polarity
+  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEP           LL_USART_GetDESignalPolarity
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_DE_POLARITY_HIGH
+  *         @arg @ref LL_USART_DE_POLARITY_LOW
+  */
+__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services
+  * @{
+  */
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
+  * @note   In UART mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - CLKEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  * @note   Other remaining configurations items related to Asynchronous Mode
+  *         (as Baud Rate, Word length, Parity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigAsyncMode\n
+  *         CR2          CLKEN         LL_USART_ConfigAsyncMode\n
+  *         CR3          SCEN          LL_USART_ConfigAsyncMode\n
+  *         CR3          IREN          LL_USART_ConfigAsyncMode\n
+  *         CR3          HDSEL         LL_USART_ConfigAsyncMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
+{
+  /* In Asynchronous mode, the following bits must be kept cleared:
+  - LINEN, CLKEN bits in the USART_CR2 register,
+  - SCEN, IREN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Synchronous Mode
+  * @note   In Synchronous mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also sets the USART in Synchronous mode.
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
+  * @note   Other remaining configurations items related to Synchronous Mode
+  *         (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigSyncMode\n
+  *         CR2          CLKEN         LL_USART_ConfigSyncMode\n
+  *         CR3          SCEN          LL_USART_ConfigSyncMode\n
+  *         CR3          IREN          LL_USART_ConfigSyncMode\n
+  *         CR3          HDSEL         LL_USART_ConfigSyncMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
+{
+  /* In Synchronous mode, the following bits must be kept cleared:
+  - LINEN bit in the USART_CR2 register,
+  - SCEN, IREN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
+  /* set the UART/USART in Synchronous mode */
+  SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in LIN Mode
+  * @note   In LIN mode, the following bits must be kept cleared:
+  *           - STOP and CLKEN bits in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also set the UART/USART in LIN mode.
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function
+  * @note   Other remaining configurations items related to LIN Mode
+  *         (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          CLKEN         LL_USART_ConfigLINMode\n
+  *         CR2          STOP          LL_USART_ConfigLINMode\n
+  *         CR2          LINEN         LL_USART_ConfigLINMode\n
+  *         CR3          IREN          LL_USART_ConfigLINMode\n
+  *         CR3          SCEN          LL_USART_ConfigLINMode\n
+  *         CR3          HDSEL         LL_USART_ConfigLINMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
+{
+  /* In LIN mode, the following bits must be kept cleared:
+  - STOP and CLKEN bits in the USART_CR2 register,
+  - IREN, SCEN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
+  /* Set the UART/USART in LIN mode */
+  SET_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Half Duplex Mode
+  * @note   In Half Duplex mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - CLKEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *         This function also sets the UART/USART in Half Duplex mode.
+  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function
+  * @note   Other remaining configurations items related to Half Duplex Mode
+  *         (as Baud Rate, Word length, Parity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigHalfDuplexMode\n
+  *         CR2          CLKEN         LL_USART_ConfigHalfDuplexMode\n
+  *         CR3          HDSEL         LL_USART_ConfigHalfDuplexMode\n
+  *         CR3          SCEN          LL_USART_ConfigHalfDuplexMode\n
+  *         CR3          IREN          LL_USART_ConfigHalfDuplexMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
+{
+  /* In Half Duplex mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - SCEN and IREN bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
+  /* set the UART/USART in Half Duplex mode */
+  SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Smartcard Mode
+  * @note   In Smartcard mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also configures Stop bits to 1.5 bits and
+  *         sets the USART in Smartcard mode (SCEN bit).
+  *         Clock Output is also enabled (CLKEN).
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+  *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
+  *         - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function
+  * @note   Other remaining configurations items related to Smartcard Mode
+  *         (as Baud Rate, Word length, Parity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigSmartcardMode\n
+  *         CR2          STOP          LL_USART_ConfigSmartcardMode\n
+  *         CR2          CLKEN         LL_USART_ConfigSmartcardMode\n
+  *         CR3          HDSEL         LL_USART_ConfigSmartcardMode\n
+  *         CR3          SCEN          LL_USART_ConfigSmartcardMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
+{
+  /* In Smartcard mode, the following bits must be kept cleared:
+  - LINEN bit in the USART_CR2 register,
+  - IREN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
+  /* Configure Stop bits to 1.5 bits */
+  /* Synchronous mode is activated by default */
+  SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));
+  /* set the UART/USART in Smartcard mode */
+  SET_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Irda Mode
+  * @note   In IRDA mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - STOP and CLKEN bits in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also sets the UART/USART in IRDA mode (IREN bit).
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+  *         - Set IREN in CR3 using @ref LL_USART_EnableIrda() function
+  * @note   Other remaining configurations items related to Irda Mode
+  *         (as Baud Rate, Word length, Power mode, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigIrdaMode\n
+  *         CR2          CLKEN         LL_USART_ConfigIrdaMode\n
+  *         CR2          STOP          LL_USART_ConfigIrdaMode\n
+  *         CR3          SCEN          LL_USART_ConfigIrdaMode\n
+  *         CR3          HDSEL         LL_USART_ConfigIrdaMode\n
+  *         CR3          IREN          LL_USART_ConfigIrdaMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)
+{
+  /* In IRDA mode, the following bits must be kept cleared:
+  - LINEN, STOP and CLKEN bits in the USART_CR2 register,
+  - SCEN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
+  /* set the UART/USART in IRDA mode */
+  SET_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Multi processor Mode
+  *         (several USARTs connected in a network, one of the USARTs can be the master,
+  *         its TX output connected to the RX inputs of the other slaves USARTs).
+  * @note   In MultiProcessor mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - CLKEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  * @note   Other remaining configurations items related to Multi processor Mode
+  *         (as Baud Rate, Wake Up Method, Node address, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigMultiProcessMode\n
+  *         CR2          CLKEN         LL_USART_ConfigMultiProcessMode\n
+  *         CR3          SCEN          LL_USART_ConfigMultiProcessMode\n
+  *         CR3          HDSEL         LL_USART_ConfigMultiProcessMode\n
+  *         CR3          IREN          LL_USART_ConfigMultiProcessMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
+{
+  /* In Multi Processor mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - IREN, SCEN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Check if the USART Parity Error Flag is set or not
+  * @rmtoll ISR          PE            LL_USART_IsActiveFlag_PE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Framing Error Flag is set or not
+  * @rmtoll ISR          FE            LL_USART_IsActiveFlag_FE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Noise error detected Flag is set or not
+  * @rmtoll ISR          NE            LL_USART_IsActiveFlag_NE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART OverRun Error Flag is set or not
+  * @rmtoll ISR          ORE           LL_USART_IsActiveFlag_ORE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART IDLE line detected Flag is set or not
+  * @rmtoll ISR          IDLE          LL_USART_IsActiveFlag_IDLE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
+}
+
+/* Legacy define */
+#define LL_USART_IsActiveFlag_RXNE  LL_USART_IsActiveFlag_RXNE_RXFNE
+
+/**
+  * @brief  Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          RXNE_RXFNE    LL_USART_IsActiveFlag_RXNE_RXFNE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Transmission Complete Flag is set or not
+  * @rmtoll ISR          TC            LL_USART_IsActiveFlag_TC
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
+}
+
+/* Legacy define */
+#define LL_USART_IsActiveFlag_TXE  LL_USART_IsActiveFlag_TXE_TXFNF
+
+/**
+  * @brief  Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          TXE_TXFNF     LL_USART_IsActiveFlag_TXE_TXFNF
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART LIN Break Detection Flag is set or not
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll ISR          LBDF          LL_USART_IsActiveFlag_LBD
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART CTS interrupt Flag is set or not
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll ISR          CTSIF         LL_USART_IsActiveFlag_nCTS
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART CTS Flag is set or not
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll ISR          CTS           LL_USART_IsActiveFlag_CTS
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Receiver Time Out Flag is set or not
+  * @rmtoll ISR          RTOF          LL_USART_IsActiveFlag_RTO
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART End Of Block Flag is set or not
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll ISR          EOBF          LL_USART_IsActiveFlag_EOB
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the SPI Slave Underrun error flag is set or not
+  * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          UDR           LL_USART_IsActiveFlag_UDR
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Auto-Baud Rate Error Flag is set or not
+  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll ISR          ABRE          LL_USART_IsActiveFlag_ABRE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Auto-Baud Rate Flag is set or not
+  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll ISR          ABRF          LL_USART_IsActiveFlag_ABR
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Busy Flag is set or not
+  * @rmtoll ISR          BUSY          LL_USART_IsActiveFlag_BUSY
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Character Match Flag is set or not
+  * @rmtoll ISR          CMF           LL_USART_IsActiveFlag_CM
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Send Break Flag is set or not
+  * @rmtoll ISR          SBKF          LL_USART_IsActiveFlag_SBK
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Receive Wake Up from mute mode Flag is set or not
+  * @rmtoll ISR          RWU           LL_USART_IsActiveFlag_RWU
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Wake Up from stop mode Flag is set or not
+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          WUF           LL_USART_IsActiveFlag_WKUP
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Transmit Enable Acknowledge Flag is set or not
+  * @rmtoll ISR          TEACK         LL_USART_IsActiveFlag_TEACK
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Receive Enable Acknowledge Flag is set or not
+  * @rmtoll ISR          REACK         LL_USART_IsActiveFlag_REACK
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART TX FIFO Empty Flag is set or not
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          TXFE          LL_USART_IsActiveFlag_TXFE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART RX FIFO Full Flag is set or not
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          RXFF          LL_USART_IsActiveFlag_RXFF
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not
+  * @rmtoll ISR          TCBGT         LL_USART_IsActiveFlag_TCBGT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART TX FIFO Threshold Flag is set or not
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          TXFT          LL_USART_IsActiveFlag_TXFT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART RX FIFO Threshold Flag is set or not
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          RXFT          LL_USART_IsActiveFlag_RXFT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear Parity Error Flag
+  * @rmtoll ICR          PECF          LL_USART_ClearFlag_PE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_PECF);
+}
+
+/**
+  * @brief  Clear Framing Error Flag
+  * @rmtoll ICR          FECF          LL_USART_ClearFlag_FE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_FECF);
+}
+
+/**
+  * @brief  Clear Noise Error detected Flag
+  * @rmtoll ICR          NECF          LL_USART_ClearFlag_NE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_NECF);
+}
+
+/**
+  * @brief  Clear OverRun Error Flag
+  * @rmtoll ICR          ORECF         LL_USART_ClearFlag_ORE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_ORECF);
+}
+
+/**
+  * @brief  Clear IDLE line detected Flag
+  * @rmtoll ICR          IDLECF        LL_USART_ClearFlag_IDLE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_IDLECF);
+}
+
+/**
+  * @brief  Clear TX FIFO Empty Flag
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ICR          TXFECF        LL_USART_ClearFlag_TXFE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_TXFE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_TXFECF);
+}
+
+/**
+  * @brief  Clear Transmission Complete Flag
+  * @rmtoll ICR          TCCF          LL_USART_ClearFlag_TC
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_TCCF);
+}
+
+/**
+  * @brief  Clear Smartcard Transmission Complete Before Guard Time Flag
+  * @rmtoll ICR          TCBGTCF       LL_USART_ClearFlag_TCBGT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF);
+}
+
+/**
+  * @brief  Clear LIN Break Detection Flag
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll ICR          LBDCF         LL_USART_ClearFlag_LBD
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_LBDCF);
+}
+
+/**
+  * @brief  Clear CTS Interrupt Flag
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll ICR          CTSCF         LL_USART_ClearFlag_nCTS
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_CTSCF);
+}
+
+/**
+  * @brief  Clear Receiver Time Out Flag
+  * @rmtoll ICR          RTOCF         LL_USART_ClearFlag_RTO
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_RTOCF);
+}
+
+/**
+  * @brief  Clear End Of Block Flag
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll ICR          EOBCF         LL_USART_ClearFlag_EOB
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_EOBCF);
+}
+
+/**
+  * @brief  Clear SPI Slave Underrun Flag
+  * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @rmtoll ICR          UDRCF         LL_USART_ClearFlag_UDR
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_UDR(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_UDRCF);
+}
+
+/**
+  * @brief  Clear Character Match Flag
+  * @rmtoll ICR          CMCF          LL_USART_ClearFlag_CM
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_CMCF);
+}
+
+/**
+  * @brief  Clear Wake Up from stop mode Flag
+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll ICR          WUCF          LL_USART_ClearFlag_WKUP
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_WUCF);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable IDLE Interrupt
+  * @rmtoll CR1          IDLEIE        LL_USART_EnableIT_IDLE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+}
+
+/* Legacy define */
+#define LL_USART_EnableIT_RXNE  LL_USART_EnableIT_RXNE_RXFNE
+
+/**
+  * @brief  Enable RX Not Empty and RX FIFO Not Empty Interrupt
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_EnableIT_RXNE_RXFNE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+}
+
+/**
+  * @brief  Enable Transmission Complete Interrupt
+  * @rmtoll CR1          TCIE          LL_USART_EnableIT_TC
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_TCIE);
+}
+
+/* Legacy define */
+#define LL_USART_EnableIT_TXE  LL_USART_EnableIT_TXE_TXFNF
+
+/**
+  * @brief  Enable TX Empty and TX FIFO Not Full Interrupt
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1         TXEIE_TXFNFIE  LL_USART_EnableIT_TXE_TXFNF
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+}
+
+/**
+  * @brief  Enable Parity Error Interrupt
+  * @rmtoll CR1          PEIE          LL_USART_EnableIT_PE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+  * @brief  Enable Character Match Interrupt
+  * @rmtoll CR1          CMIE          LL_USART_EnableIT_CM
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+  * @brief  Enable Receiver Timeout Interrupt
+  * @rmtoll CR1          RTOIE         LL_USART_EnableIT_RTO
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_RTOIE);
+}
+
+/**
+  * @brief  Enable End Of Block Interrupt
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR1          EOBIE         LL_USART_EnableIT_EOB
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_EOBIE);
+}
+
+/**
+  * @brief  Enable TX FIFO Empty Interrupt
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          TXFEIE        LL_USART_EnableIT_TXFE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TXFE(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_TXFEIE);
+}
+
+/**
+  * @brief  Enable RX FIFO Full Interrupt
+  * @rmtoll CR1          RXFFIE        LL_USART_EnableIT_RXFF
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_RXFF(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_RXFFIE);
+}
+
+/**
+  * @brief  Enable LIN Break Detection Interrupt
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDIE         LL_USART_EnableIT_LBD
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_LBDIE);
+}
+
+/**
+  * @brief  Enable Error Interrupt
+  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
+  *           0: Interrupt is inhibited
+  *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
+  * @rmtoll CR3          EIE           LL_USART_EnableIT_ERROR
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+  * @brief  Enable CTS Interrupt
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSIE         LL_USART_EnableIT_CTS
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+  * @brief  Enable Wake Up from Stop Mode Interrupt
+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUFIE         LL_USART_EnableIT_WKUP
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_WUFIE);
+}
+
+/**
+  * @brief  Enable TX FIFO Threshold Interrupt
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          TXFTIE        LL_USART_EnableIT_TXFT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_TXFTIE);
+}
+
+/**
+  * @brief  Enable Smartcard Transmission Complete Before Guard Time Interrupt
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          TCBGTIE       LL_USART_EnableIT_TCBGT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
+}
+
+/**
+  * @brief  Enable RX FIFO Threshold Interrupt
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          RXFTIE        LL_USART_EnableIT_RXFT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_RXFT(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_RXFTIE);
+}
+
+/**
+  * @brief  Disable IDLE Interrupt
+  * @rmtoll CR1          IDLEIE        LL_USART_DisableIT_IDLE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+}
+
+/* Legacy define */
+#define LL_USART_DisableIT_RXNE  LL_USART_DisableIT_RXNE_RXFNE
+
+/**
+  * @brief  Disable RX Not Empty and RX FIFO Not Empty Interrupt
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_DisableIT_RXNE_RXFNE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+}
+
+/**
+  * @brief  Disable Transmission Complete Interrupt
+  * @rmtoll CR1          TCIE          LL_USART_DisableIT_TC
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
+}
+
+/* Legacy define */
+#define LL_USART_DisableIT_TXE  LL_USART_DisableIT_TXE_TXFNF
+
+/**
+  * @brief  Disable TX Empty and TX FIFO Not Full Interrupt
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1        TXEIE_TXFNFIE  LL_USART_DisableIT_TXE_TXFNF
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+}
+
+/**
+  * @brief  Disable Parity Error Interrupt
+  * @rmtoll CR1          PEIE          LL_USART_DisableIT_PE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+  * @brief  Disable Character Match Interrupt
+  * @rmtoll CR1          CMIE          LL_USART_DisableIT_CM
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+  * @brief  Disable Receiver Timeout Interrupt
+  * @rmtoll CR1          RTOIE         LL_USART_DisableIT_RTO
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE);
+}
+
+/**
+  * @brief  Disable End Of Block Interrupt
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR1          EOBIE         LL_USART_DisableIT_EOB
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE);
+}
+
+/**
+  * @brief  Disable TX FIFO Empty Interrupt
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          TXFEIE        LL_USART_DisableIT_TXFE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TXFE(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_TXFEIE);
+}
+
+/**
+  * @brief  Disable RX FIFO Full Interrupt
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          RXFFIE        LL_USART_DisableIT_RXFF
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_RXFF(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_RXFFIE);
+}
+
+/**
+  * @brief  Disable LIN Break Detection Interrupt
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDIE         LL_USART_DisableIT_LBD
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);
+}
+
+/**
+  * @brief  Disable Error Interrupt
+  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
+  *           0: Interrupt is inhibited
+  *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
+  * @rmtoll CR3          EIE           LL_USART_DisableIT_ERROR
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+  * @brief  Disable CTS Interrupt
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSIE         LL_USART_DisableIT_CTS
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+  * @brief  Disable Wake Up from Stop Mode Interrupt
+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUFIE         LL_USART_DisableIT_WKUP
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE);
+}
+
+/**
+  * @brief  Disable TX FIFO Threshold Interrupt
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          TXFTIE        LL_USART_DisableIT_TXFT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_TXFTIE);
+}
+
+/**
+  * @brief  Disable Smartcard Transmission Complete Before Guard Time Interrupt
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          TCBGTIE       LL_USART_DisableIT_TCBGT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
+}
+
+/**
+  * @brief  Disable RX FIFO Threshold Interrupt
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          RXFTIE        LL_USART_DisableIT_RXFT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_RXFTIE);
+}
+
+/**
+  * @brief  Check if the USART IDLE Interrupt  source is enabled or disabled.
+  * @rmtoll CR1          IDLEIE        LL_USART_IsEnabledIT_IDLE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
+}
+
+/* Legacy define */
+#define LL_USART_IsEnabledIT_RXNE  LL_USART_IsEnabledIT_RXNE_RXFNE
+
+/**
+  * @brief  Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled.
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_IsEnabledIT_RXNE_RXFNE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Transmission Complete Interrupt is enabled or disabled.
+  * @rmtoll CR1          TCIE          LL_USART_IsEnabledIT_TC
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
+}
+
+/* Legacy define */
+#define LL_USART_IsEnabledIT_TXE  LL_USART_IsEnabledIT_TXE_TXFNF
+
+/**
+  * @brief  Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1         TXEIE_TXFNFIE  LL_USART_IsEnabledIT_TXE_TXFNF
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Parity Error Interrupt is enabled or disabled.
+  * @rmtoll CR1          PEIE          LL_USART_IsEnabledIT_PE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Character Match Interrupt is enabled or disabled.
+  * @rmtoll CR1          CMIE          LL_USART_IsEnabledIT_CM
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Receiver Timeout Interrupt is enabled or disabled.
+  * @rmtoll CR1          RTOIE         LL_USART_IsEnabledIT_RTO
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART End Of Block Interrupt is enabled or disabled.
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR1          EOBIE         LL_USART_IsEnabledIT_EOB
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART TX FIFO Empty Interrupt is enabled or disabled
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          TXFEIE        LL_USART_IsEnabledIT_TXFE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART RX FIFO Full Interrupt is enabled or disabled
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          RXFFIE        LL_USART_IsEnabledIT_RXFF
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART LIN Break Detection Interrupt is enabled or disabled.
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDIE         LL_USART_IsEnabledIT_LBD
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Error Interrupt is enabled or disabled.
+  * @rmtoll CR3          EIE           LL_USART_IsEnabledIT_ERROR
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART CTS Interrupt is enabled or disabled.
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSIE         LL_USART_IsEnabledIT_CTS
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.
+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUFIE         LL_USART_IsEnabledIT_WKUP
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if USART TX FIFO Threshold Interrupt is enabled or disabled
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          TXFTIE        LL_USART_IsEnabledIT_TXFT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled.
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          TCBGTIE       LL_USART_IsEnabledIT_TCBGT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if USART RX FIFO Threshold Interrupt is enabled or disabled
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          RXFTIE        LL_USART_IsEnabledIT_RXFT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_DMA_Management DMA_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable DMA Mode for reception
+  * @rmtoll CR3          DMAR          LL_USART_EnableDMAReq_RX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+  * @brief  Disable DMA Mode for reception
+  * @rmtoll CR3          DMAR          LL_USART_DisableDMAReq_RX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+  * @brief  Check if DMA Mode is enabled for reception
+  * @rmtoll CR3          DMAR          LL_USART_IsEnabledDMAReq_RX
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable DMA Mode for transmission
+  * @rmtoll CR3          DMAT          LL_USART_EnableDMAReq_TX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+  * @brief  Disable DMA Mode for transmission
+  * @rmtoll CR3          DMAT          LL_USART_DisableDMAReq_TX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+  * @brief  Check if DMA Mode is enabled for transmission
+  * @rmtoll CR3          DMAT          LL_USART_IsEnabledDMAReq_TX
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable DMA Disabling on Reception Error
+  * @rmtoll CR3          DDRE          LL_USART_EnableDMADeactOnRxErr
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+  * @brief  Disable DMA Disabling on Reception Error
+  * @rmtoll CR3          DDRE          LL_USART_DisableDMADeactOnRxErr
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+  * @brief  Indicate if DMA Disabling on Reception Error is disabled
+  * @rmtoll CR3          DDRE          LL_USART_IsEnabledDMADeactOnRxErr
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get the data register address used for DMA transfer
+  * @rmtoll RDR          RDR           LL_USART_DMA_GetRegAddr\n
+  * @rmtoll TDR          TDR           LL_USART_DMA_GetRegAddr
+  * @param  USARTx USART Instance
+  * @param  Direction This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT
+  *         @arg @ref LL_USART_DMA_REG_DATA_RECEIVE
+  * @retval Address of data register
+  */
+__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction)
+{
+  register uint32_t data_reg_addr;
+
+  if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT)
+  {
+    /* return address of TDR register */
+    data_reg_addr = (uint32_t) &(USARTx->TDR);
+  }
+  else
+  {
+    /* return address of RDR register */
+    data_reg_addr = (uint32_t) &(USARTx->RDR);
+  }
+
+  return data_reg_addr;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Data_Management Data_Management
+  * @{
+  */
+
+/**
+  * @brief  Read Receiver Data register (Receive Data value, 8 bits)
+  * @rmtoll RDR          RDR           LL_USART_ReceiveData8
+  * @param  USARTx USART Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)
+{
+  return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU);
+}
+
+/**
+  * @brief  Read Receiver Data register (Receive Data value, 9 bits)
+  * @rmtoll RDR          RDR           LL_USART_ReceiveData9
+  * @param  USARTx USART Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x1FF
+  */
+__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx)
+{
+  return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
+}
+
+/**
+  * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)
+  * @rmtoll TDR          TDR           LL_USART_TransmitData8
+  * @param  USARTx USART Instance
+  * @param  Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value)
+{
+  USARTx->TDR = Value;
+}
+
+/**
+  * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)
+  * @rmtoll TDR          TDR           LL_USART_TransmitData9
+  * @param  USARTx USART Instance
+  * @param  Value between Min_Data=0x00 and Max_Data=0x1FF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)
+{
+  USARTx->TDR = (uint16_t)(Value & 0x1FFUL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Execution Execution
+  * @{
+  */
+
+/**
+  * @brief  Request an Automatic Baud Rate measurement on next received data frame
+  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll RQR          ABRRQ         LL_USART_RequestAutoBaudRate
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_ABRRQ);
+}
+
+/**
+  * @brief  Request Break sending
+  * @rmtoll RQR          SBKRQ         LL_USART_RequestBreakSending
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
+}
+
+/**
+  * @brief  Put USART in mute mode and set the RWU flag
+  * @rmtoll RQR          MMRQ          LL_USART_RequestEnterMuteMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_MMRQ);
+}
+
+/**
+  * @brief  Request a Receive Data and FIFO flush
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @note   Allows to discard the received data without reading them, and avoid an overrun
+  *         condition.
+  * @rmtoll RQR          RXFRQ         LL_USART_RequestRxDataFlush
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
+}
+
+/**
+  * @brief  Request a Transmit data and FIFO flush
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll RQR          TXFRQ         LL_USART_RequestTxDataFlush
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_TXFRQ);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx);
+ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct);
+void        LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
+ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
+void        LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 || UART9 || USART10 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_LL_USART_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h
new file mode 100644
index 00000000..503b12f3
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h
@@ -0,0 +1,510 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_usb.h
+  * @author  MCD Application Team
+  * @brief   Header file of USB Low Layer HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_LL_USB_H
+#define STM32H7xx_LL_USB_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup USB_LL
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+  * @brief  USB Mode definition
+  */
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+
+typedef enum
+{
+  USB_DEVICE_MODE  = 0,
+  USB_HOST_MODE    = 1,
+  USB_DRD_MODE     = 2
+} USB_OTG_ModeTypeDef;
+
+/**
+  * @brief  URB States definition
+  */
+typedef enum
+{
+  URB_IDLE = 0,
+  URB_DONE,
+  URB_NOTREADY,
+  URB_NYET,
+  URB_ERROR,
+  URB_STALL
+} USB_OTG_URBStateTypeDef;
+
+/**
+  * @brief  Host channel States  definition
+  */
+typedef enum
+{
+  HC_IDLE = 0,
+  HC_XFRC,
+  HC_HALTED,
+  HC_NAK,
+  HC_NYET,
+  HC_STALL,
+  HC_XACTERR,
+  HC_BBLERR,
+  HC_DATATGLERR
+} USB_OTG_HCStateTypeDef;
+
+/**
+  * @brief  USB OTG Initialization Structure definition
+  */
+typedef struct
+{
+  uint32_t dev_endpoints;           /*!< Device Endpoints number.
+                                         This parameter depends on the used USB core.
+                                         This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+
+  uint32_t Host_channels;           /*!< Host Channels number.
+                                         This parameter Depends on the used USB core.
+                                         This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+
+  uint32_t speed;                   /*!< USB Core speed.
+                                         This parameter can be any value of @ref USB_Core_Speed_                */
+
+  uint32_t dma_enable;              /*!< Enable or disable of the USB embedded DMA used only for OTG HS.        */
+
+  uint32_t ep0_mps;                 /*!< Set the Endpoint 0 Max Packet size.                                    */
+
+  uint32_t phy_itface;              /*!< Select the used PHY interface.
+                                         This parameter can be any value of @ref USB_Core_PHY_                  */
+
+  uint32_t Sof_enable;              /*!< Enable or disable the output of the SOF signal.                        */
+
+  uint32_t low_power_enable;        /*!< Enable or disable the low power mode.                                  */
+
+  uint32_t lpm_enable;              /*!< Enable or disable Link Power Management.                               */
+
+  uint32_t battery_charging_enable; /*!< Enable or disable Battery charging.                                    */
+
+  uint32_t vbus_sensing_enable;     /*!< Enable or disable the VBUS Sensing feature.                            */
+
+  uint32_t use_dedicated_ep1;       /*!< Enable or disable the use of the dedicated EP1 interrupt.              */
+
+  uint32_t use_external_vbus;       /*!< Enable or disable the use of the external VBUS.                        */
+} USB_OTG_CfgTypeDef;
+
+typedef struct
+{
+  uint8_t   num;                  /*!< Endpoint number
+                                       This parameter must be a number between Min_Data = 1 and Max_Data = 15   */
+
+  uint8_t   is_in;                /*!< Endpoint direction
+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 1    */
+
+  uint8_t   is_stall;             /*!< Endpoint stall condition
+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 1    */
+
+  uint8_t   type;                 /*!< Endpoint type
+                                       This parameter can be any value of @ref USB_EP_Type_                     */
+
+  uint8_t   data_pid_start;       /*!< Initial data PID
+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 1    */
+
+  uint8_t   even_odd_frame;       /*!< IFrame parity
+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 1    */
+
+  uint16_t  tx_fifo_num;          /*!< Transmission FIFO number
+                                       This parameter must be a number between Min_Data = 1 and Max_Data = 15   */
+
+  uint32_t  maxpacket;            /*!< Endpoint Max packet size
+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
+
+  uint8_t   *xfer_buff;           /*!< Pointer to transfer buffer                                               */
+
+  uint32_t  dma_addr;             /*!< 32 bits aligned transfer buffer address                                  */
+
+  uint32_t  xfer_len;             /*!< Current transfer length                                                  */
+
+  uint32_t  xfer_count;           /*!< Partial transfer length in case of multi packet transfer                 */
+} USB_OTG_EPTypeDef;
+
+typedef struct
+{
+  uint8_t   dev_addr ;          /*!< USB device address.
+                                     This parameter must be a number between Min_Data = 1 and Max_Data = 255    */
+
+  uint8_t   ch_num;             /*!< Host channel number.
+                                     This parameter must be a number between Min_Data = 1 and Max_Data = 15     */
+
+  uint8_t   ep_num;             /*!< Endpoint number.
+                                     This parameter must be a number between Min_Data = 1 and Max_Data = 15     */
+
+  uint8_t   ep_is_in;           /*!< Endpoint direction
+                                     This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
+
+  uint8_t   speed;              /*!< USB Host speed.
+                                     This parameter can be any value of @ref USB_Core_Speed_                    */
+
+  uint8_t   do_ping;            /*!< Enable or disable the use of the PING protocol for HS mode.                */
+
+  uint8_t   process_ping;       /*!< Execute the PING protocol for HS mode.                                     */
+
+  uint8_t   ep_type;            /*!< Endpoint Type.
+                                     This parameter can be any value of @ref USB_EP_Type_                       */
+
+  uint16_t  max_packet;         /*!< Endpoint Max packet size.
+                                     This parameter must be a number between Min_Data = 0 and Max_Data = 64KB   */
+
+  uint8_t   data_pid;           /*!< Initial data PID.
+                                     This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
+
+  uint8_t   *xfer_buff;         /*!< Pointer to transfer buffer.                                                */
+
+  uint32_t  xfer_len;           /*!< Current transfer length.                                                   */
+
+  uint32_t  xfer_count;         /*!< Partial transfer length in case of multi packet transfer.                  */
+
+  uint8_t   toggle_in;          /*!< IN transfer current toggle flag.
+                                     This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
+
+  uint8_t   toggle_out;         /*!< OUT transfer current toggle flag
+                                     This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
+
+  uint32_t  dma_addr;           /*!< 32 bits aligned transfer buffer address.                                   */
+
+  uint32_t  ErrCnt;             /*!< Host channel error count.*/
+
+  USB_OTG_URBStateTypeDef  urb_state;  /*!< URB state.
+                                            This parameter can be any value of @ref USB_OTG_URBStateTypeDef */
+
+  USB_OTG_HCStateTypeDef   state;     /*!< Host Channel state.
+                                           This parameter can be any value of @ref USB_OTG_HCStateTypeDef   */
+} USB_OTG_HCTypeDef;
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PCD_Exported_Constants PCD Exported Constants
+  * @{
+  */
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+/** @defgroup USB_OTG_CORE VERSION ID
+  * @{
+  */
+#define USB_OTG_CORE_ID_300A          0x4F54300AU
+#define USB_OTG_CORE_ID_310A          0x4F54310AU
+/**
+  * @}
+  */
+
+/** @defgroup USB_Core_Mode_ USB Core Mode
+  * @{
+  */
+#define USB_OTG_MODE_DEVICE                    0U
+#define USB_OTG_MODE_HOST                      1U
+#define USB_OTG_MODE_DRD                       2U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL Device Speed
+  * @{
+  */
+#define USBD_HS_SPEED               0U
+#define USBD_HSINFS_SPEED           1U
+#define USBH_HS_SPEED               0U
+#define USBD_FS_SPEED               2U
+#define USBH_FS_SPEED               1U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed
+  * @{
+  */
+#define USB_OTG_SPEED_HIGH                     0U
+#define USB_OTG_SPEED_HIGH_IN_FULL             1U
+#define USB_OTG_SPEED_FULL                     3U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY
+  * @{
+  */
+#define USB_OTG_ULPI_PHY                       1U
+#define USB_OTG_EMBEDDED_PHY                   2U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_Turnaround_Timeout Turnaround Timeout Value
+  * @{
+  */
+#ifndef USBD_HS_TRDT_VALUE
+#define USBD_HS_TRDT_VALUE           9U
+#endif /* USBD_HS_TRDT_VALUE */
+#ifndef USBD_FS_TRDT_VALUE
+#define USBD_FS_TRDT_VALUE           5U
+#define USBD_DEFAULT_TRDT_VALUE      9U
+#endif /* USBD_HS_TRDT_VALUE */
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS
+  * @{
+  */
+#define USB_OTG_HS_MAX_PACKET_SIZE             512U
+#define USB_OTG_FS_MAX_PACKET_SIZE             64U
+#define USB_OTG_MAX_EP0_SIZE                   64U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency
+  * @{
+  */
+#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ     (0U << 1)
+#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ     (1U << 1)
+#define DSTS_ENUMSPD_FS_PHY_48MHZ              (3U << 1)
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval
+  * @{
+  */
+#define DCFG_FRAME_INTERVAL_80                 0U
+#define DCFG_FRAME_INTERVAL_85                 1U
+#define DCFG_FRAME_INTERVAL_90                 2U
+#define DCFG_FRAME_INTERVAL_95                 3U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
+  * @{
+  */
+#define DEP0CTL_MPS_64                         0U
+#define DEP0CTL_MPS_32                         1U
+#define DEP0CTL_MPS_16                         2U
+#define DEP0CTL_MPS_8                          3U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed
+  * @{
+  */
+#define EP_SPEED_LOW                           0U
+#define EP_SPEED_FULL                          1U
+#define EP_SPEED_HIGH                          2U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_EP_Type USB Low Layer EP Type
+  * @{
+  */
+#define EP_TYPE_CTRL                           0U
+#define EP_TYPE_ISOC                           1U
+#define EP_TYPE_BULK                           2U
+#define EP_TYPE_INTR                           3U
+#define EP_TYPE_MSK                            3U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines
+  * @{
+  */
+#define STS_GOUT_NAK                           1U
+#define STS_DATA_UPDT                          2U
+#define STS_XFER_COMP                          3U
+#define STS_SETUP_COMP                         4U
+#define STS_SETUP_UPDT                         6U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines
+  * @{
+  */
+#define HCFG_30_60_MHZ                         0U
+#define HCFG_48_MHZ                            1U
+#define HCFG_6_MHZ                             2U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines
+  * @{
+  */
+#define HPRT0_PRTSPD_HIGH_SPEED                0U
+#define HPRT0_PRTSPD_FULL_SPEED                1U
+#define HPRT0_PRTSPD_LOW_SPEED                 2U
+/**
+  * @}
+  */
+
+#define HCCHAR_CTRL                            0U
+#define HCCHAR_ISOC                            1U
+#define HCCHAR_BULK                            2U
+#define HCCHAR_INTR                            3U
+
+#define HC_PID_DATA0                           0U
+#define HC_PID_DATA2                           1U
+#define HC_PID_DATA1                           2U
+#define HC_PID_SETUP                           3U
+
+#define GRXSTS_PKTSTS_IN                       2U
+#define GRXSTS_PKTSTS_IN_XFER_COMP             3U
+#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR          5U
+#define GRXSTS_PKTSTS_CH_HALTED                7U
+
+#define USBx_PCGCCTL    *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE)
+#define USBx_HPRT0      *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE)
+
+#define USBx_DEVICE     ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE))
+#define USBx_INEP(i)    ((USB_OTG_INEndpointTypeDef *)(USBx_BASE + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
+#define USBx_OUTEP(i)   ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
+#define USBx_DFIFO(i)   *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE))
+
+#define USBx_HOST       ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE))
+#define USBx_HC(i)      ((USB_OTG_HostChannelTypeDef *)(USBx_BASE + USB_OTG_HOST_CHANNEL_BASE + ((i) * USB_OTG_HOST_CHANNEL_SIZE)))
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+#define EP_ADDR_MSK                            0xFU
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup USB_LL_Exported_Macros USB Low Layer Exported Macros
+  * @{
+  */
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__)     ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))
+#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__)   ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))
+
+#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__)          (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__))
+#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__)         (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions
+  * @{
+  */
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
+HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
+HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed);
+HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode);
+HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed);
+HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num);
+HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma);
+HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma);
+HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma);
+void             *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
+HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address);
+HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup);
+uint8_t           USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_GetMode(USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
+uint32_t          USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
+void              USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);
+
+HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
+HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq);
+HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state);
+uint32_t          USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
+                              uint8_t ch_num,
+                              uint8_t epnum,
+                              uint8_t dev_address,
+                              uint8_t speed,
+                              uint8_t ep_type,
+                              uint16_t mps);
+HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma);
+uint32_t          USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num);
+HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num);
+HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32H7xx_LL_USB_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_utils.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_utils.h
new file mode 100644
index 00000000..ca336c26
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_utils.h
@@ -0,0 +1,382 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_utils.h
+  * @author  MCD Application Team
+  * @brief   Header file of UTILS LL module.
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The LL UTILS driver contains a set of generic APIs that can be
+    used by user:
+      (+) Device electronic signature
+      (+) Timing functions
+      (+) PLL configuration functions
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_LL_UTILS_H
+#define STM32H7xx_LL_UTILS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+#include "stm32h7xx_ll_system.h"
+#include "stm32h7xx_ll_bus.h"
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+/** @defgroup UTILS_LL UTILS
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
+  * @{
+  */
+
+/* Max delay can be used in LL_mDelay */
+#define LL_MAX_DELAY                  0xFFFFFFFFU
+
+/**
+ * @brief Unique device ID register base address
+ */
+#define UID_BASE_ADDRESS              UID_BASE
+
+/**
+ * @brief Flash size data register base address
+ */
+#define FLASHSIZE_BASE_ADDRESS        FLASHSIZE_BASE
+
+/**
+ * @brief Package data register base address
+ */
+#define PACKAGE_BASE_ADDRESS          PACKAGE_BASE
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
+  * @{
+  */
+/**
+  * @brief  UTILS PLL structure definition
+  */
+typedef struct
+{
+  uint32_t PLLM;   /*!< Division factor for PLL VCO input clock.
+                        This parameter must be a number between Min_Data = 0 and Max_Data = 63
+
+                        This feature can be modified afterwards using unitary function
+                        @ref LL_RCC_PLL1_SetM(). */
+
+  uint32_t PLLN;   /*!< Multiplication factor for PLL VCO output clock.
+                        This parameter must be a number between Min_Data = 4 and Max_Data = 512
+
+                        This feature can be modified afterwards using unitary function
+                        @ref LL_RCC_PLL1_SetN(). */
+
+  uint32_t PLLP;   /*!< Division for the main system clock.
+                        This parameter must be a number between Min_Data = 2 and Max_Data = 128
+                          odd division factors are not allowed
+
+                        This feature can be modified afterwards using unitary function
+                        @ref LL_RCC_PLL1_SetP(). */
+
+  uint32_t FRACN;  /*!< Fractional part of the multiplication factor for PLL VCO.
+                        This parameter can be a value between 0 and 8191
+
+                        This feature can be modified afterwards using unitary function
+                        @ref LL_RCC_PLL1_SetFRACN(). */
+
+  uint32_t VCO_Input;  /*!< PLL clock Input range.
+                        This parameter can be a value of @ref RCC_LL_EC_PLLINPUTRANGE
+
+                        This feature can be modified afterwards using unitary function
+                        @ref LL_RCC_PLL1_SetVCOInputRange(). */
+
+  uint32_t VCO_Output;  /*!< PLL clock Output range.
+                        This parameter can be a value of @ref RCC_LL_EC_PLLVCORANGE
+
+                      This feature can be modified afterwards using unitary function
+                      @ref LL_RCC_PLL1_SetVCOOutputRange(). */
+
+} LL_UTILS_PLLInitTypeDef;
+
+/**
+  * @brief  UTILS System, AHB and APB buses clock configuration structure definition
+  */
+typedef struct
+{
+  uint32_t SYSCLKDivider;         /*!< The System clock (SYSCLK) divider. This clock is derived from the PLL output.
+                                     This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
+
+                                     This feature can be modified afterwards using unitary function
+                                     @ref LL_RCC_SetSysPrescaler(). */
+
+  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
+                                       This parameter can be a value of @ref RCC_LL_EC_AHB_DIV
+
+                                       This feature can be modified afterwards using unitary function
+                                       @ref LL_RCC_SetAHBPrescaler(). */
+
+  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
+
+                                       This feature can be modified afterwards using unitary function
+                                       @ref LL_RCC_SetAPB1Prescaler(). */
+
+  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
+
+                                       This feature can be modified afterwards using unitary function
+                                       @ref LL_RCC_SetAPB2Prescaler(). */
+
+  uint32_t APB3CLKDivider;        /*!< The APB2 clock (PCLK3) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_LL_EC_APB3_DIV
+
+                                       This feature can be modified afterwards using unitary function
+                                       @ref LL_RCC_SetAPB3Prescaler(). */
+
+  uint32_t APB4CLKDivider;        /*!< The APB4 clock (PCLK4) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_LL_EC_APB4_DIV
+
+                                       This feature can be modified afterwards using unitary function
+                                       @ref LL_RCC_SetAPB4Prescaler(). */
+
+} LL_UTILS_ClkInitTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
+  * @{
+  */
+
+/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
+  * @{
+  */
+#define LL_UTILS_HSEBYPASS_OFF        0x00000000U       /*!< HSE Bypass is not enabled                */
+#define LL_UTILS_HSEBYPASS_ON         0x00000001U       /*!< HSE Bypass is enabled                    */
+/**
+  * @}
+  */
+
+/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
+  * @{
+  */
+#if defined(SYSCFG_PKGR_PKG)
+#define LL_UTILS_PACKAGETYPE_LQFP100            LL_SYSCFG_LQFP100_PACKAGE          /*!< LQFP100 package type             */
+#define LL_UTILS_PACKAGETYPE_TQFP144            LL_SYSCFG_TQFP144_PACKAGE          /*!< TQFP144 package type             */
+#define LL_UTILS_PACKAGETYPE_TQFP176_UFBGA176   LL_SYSCFG_TQFP176_UFBGA176_PACKAGE /*!< TQFP176 or UFBGA176 package type */
+#define LL_UTILS_PACKAGETYPE_LQFP208_TFBGA240   LL_SYSCFG_LQFP208_TFBGA240_PACKAGE /*!< LQFP208 or TFBGA240 package type */
+#else
+#define LL_UTILS_PACKAGETYPE_LQFP64                  0x00000000UL                  /*!< LQFP64 package type              */
+#define LL_UTILS_PACKAGETYPE_TFBGA100_LQFP100        0x00000001UL                  /*!< TFBGA100 or LQFP100 package type */
+#define LL_UTILS_PACKAGETYPE_LQFP100_SMPS            0x00000002UL                  /*!< LQFP100  with SMPS package type  */
+#define LL_UTILS_PACKAGETYPE_TFBGA100_SMPS           0x00000003UL                  /*!< TFBGA100 with SMPS package type  */
+#define LL_UTILS_PACKAGETYPE_WLCSP132_SMPS           0x00000004UL                  /*!< WLCSP132 package type            */
+#define LL_UTILS_PACKAGETYPE_LQFP144                 0x00000005UL                  /*!< LQFP144 package type             */
+#define LL_UTILS_PACKAGETYPE_LQFP144_SMPS            0x00000006UL                  /*!< LQFP144 with SMPS package type   */
+#define LL_UTILS_PACKAGETYPE_UFBGA169                0x00000007UL                  /*!< UFBGA169 package type            */
+#define LL_UTILS_PACKAGETYPE_UFBGA176_LQFP176        0x00000008UL                  /*!< UFBGA176 or LQFP176 package type */
+#define LL_UTILS_PACKAGETYPE_LQFP176_SMPS            0x00000009UL                  /*!< LQFP176 with SMPS package type   */
+#define LL_UTILS_PACKAGETYPE_UFBGA176_SMPS           0x0000000AUL                  /*!< UFBGA176 with SMPS package type  */
+#define LL_UTILS_PACKAGETYPE_TFBGA216                0x0000000CUL                  /*!< TFBGA216  package type           */
+#define LL_UTILS_PACKAGETYPE_TFBGA225                0x0000000EUL                  /*!< TFBGA225  package type           */
+#endif /* SYSCFG_PKGR_PKG */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
+  * @{
+  */
+
+/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
+  * @{
+  */
+
+/**
+  * @brief  Get Word0 of the unique device identifier (UID based on 96 bits)
+  * @retval UID[31:0]
+  */
+__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
+{
+  return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
+}
+
+/**
+  * @brief  Get Word1 of the unique device identifier (UID based on 96 bits)
+  * @retval UID[63:32]
+  */
+__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
+{
+  return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
+}
+
+/**
+  * @brief  Get Word2 of the unique device identifier (UID based on 96 bits)
+  * @retval UID[95:64]
+  */
+__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
+{
+  return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
+}
+
+/**
+  * @brief  Get Flash memory size
+  * @note   This bitfield indicates the size of the device Flash memory expressed in
+  *         Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
+  * @retval FLASH_SIZE[15:0]: Flash memory size
+  */
+__STATIC_INLINE uint32_t LL_GetFlashSize(void)
+{
+  return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));
+}
+
+/**
+  * @brief  Get Package type
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP100
+  *         @arg @ref LL_UTILS_PACKAGETYPE_TQFP144
+  *         @arg @ref LL_UTILS_PACKAGETYPE_TQFP176_UFBGA176
+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP208_TFBGA240
+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP64 (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_TFBGA100_LQFP100  (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_SMPS  (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_TFBGA100_SMPS  (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_WLCSP132_SMPS  (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP144     (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_SMPS (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169  (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176_LQFP176  (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP176_SMPS    (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176_SMPS   (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_TFBGA216   (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_TFBGA225   (*)
+  *
+  *        (*) Packages available on some STM32H7 lines only.
+  * @note   For some SM32H7 lines, enabling the SYSCFG clock is mandatory.
+            the SYSCFG clock enabling is ensured by LL_APB4_GRP1_EnableClock
+  */
+__STATIC_INLINE uint32_t LL_GetPackageType(void)
+{
+#if defined(SYSCFG_PKGR_PKG)
+
+  return LL_SYSCFG_GetPackage();
+#else
+   return (uint16_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)));
+
+#endif  /* SYSCFG_PKGR_PKG */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UTILS_LL_EF_DELAY DELAY
+  * @{
+  */
+
+/**
+  * @brief  This function configures the Cortex-M SysTick source of the time base.
+  * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
+  * @note   When a RTOS is used, it is recommended to avoid changing the SysTick
+  *         configuration by calling this function, for a delay use rather osDelay RTOS service.
+  * @param  Ticks Number of ticks
+  * @retval None
+  */
+__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
+{
+  /* Configure the SysTick to have interrupt in 1ms time base */
+  SysTick->LOAD  = (uint32_t)((HCLKFrequency / Ticks) - 1UL);  /* set reload register */
+  SysTick->VAL   = 0UL;                                       /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_ENABLE_Msk;                   /* Enable the Systick Timer */
+}
+
+void        LL_Init1msTick(uint32_t CPU_Frequency);
+void        LL_mDelay(uint32_t Delay);
+
+/**
+  * @}
+  */
+
+/** @defgroup UTILS_EF_SYSTEM SYSTEM
+  * @{
+  */
+
+void        LL_SetSystemCoreClock(uint32_t CPU_Frequency);
+ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
+                                         LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency,
+                                         uint32_t HSEBypass,
+                                         LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
+                                         LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_LL_UTILS_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c
new file mode 100644
index 00000000..3e92312e
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c
@@ -0,0 +1,1276 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal.c
+  * @author  MCD Application Team
+  * @brief   HAL module driver.
+  *          This is the common part of the HAL initialization
+  *
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The common HAL driver contains a set of generic and common APIs that can be
+    used by the PPP peripheral drivers and the user to start using the HAL.
+    [..]
+    The HAL contains two APIs' categories:
+         (+) Common HAL APIs
+         (+) Services HAL APIs
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup HAL  HAL
+  * @brief HAL module driver.
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/**
+ * @brief STM32H7xx HAL Driver version number V1.8.0
+   */
+#define __STM32H7xx_HAL_VERSION_MAIN   (0x01UL) /*!< [31:24] main version */
+#define __STM32H7xx_HAL_VERSION_SUB1   (0x08UL) /*!< [23:16] sub1 version */
+#define __STM32H7xx_HAL_VERSION_SUB2   (0x00UL) /*!< [15:8]  sub2 version */
+#define __STM32H7xx_HAL_VERSION_RC     (0x00UL) /*!< [7:0]  release candidate */
+#define __STM32H7xx_HAL_VERSION         ((__STM32H7xx_HAL_VERSION_MAIN << 24)\
+                                        |(__STM32H7xx_HAL_VERSION_SUB1 << 16)\
+                                        |(__STM32H7xx_HAL_VERSION_SUB2 << 8 )\
+                                        |(__STM32H7xx_HAL_VERSION_RC))
+
+#define IDCODE_DEVID_MASK    ((uint32_t)0x00000FFF)
+#define VREFBUF_TIMEOUT_VALUE     (uint32_t)10   /* 10 ms  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Exported variables --------------------------------------------------------*/
+
+/** @defgroup HAL_Exported_Variables HAL Exported Variables
+  * @{
+  */
+__IO uint32_t uwTick;
+uint32_t uwTickPrio   = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
+HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT;  /* 1KHz */
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup HAL_Private_Functions  HAL Private Functions
+  * @{
+  */
+
+/** @defgroup HAL_Group1 Initialization and de-initialization Functions
+ *  @brief    Initialization and de-initialization functions
+ *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initializes the Flash interface the NVIC allocation and initial clock
+          configuration. It initializes the systick also when timeout is needed
+          and the backup domain when enabled.
+      (+) De-Initializes common part of the HAL.
+      (+) Configure The time base source to have 1ms time base with a dedicated
+          Tick interrupt priority.
+        (++) SysTick timer is used by default as source of time base, but user
+             can eventually implement his proper time base source (a general purpose
+             timer for example or other time source), keeping in mind that Time base
+             duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
+             handled in milliseconds basis.
+        (++) Time base configuration function (HAL_InitTick ()) is called automatically
+             at the beginning of the program after reset by HAL_Init() or at any time
+             when clock is configured, by HAL_RCC_ClockConfig().
+        (++) Source of time base is configured  to generate interrupts at regular
+             time intervals. Care must be taken if HAL_Delay() is called from a
+             peripheral ISR process, the Tick interrupt line must have higher priority
+            (numerically lower) than the peripheral interrupt. Otherwise the caller
+            ISR process will be blocked.
+       (++) functions affecting time base configurations are declared as __weak
+             to make  override possible  in case of other  implementations in user file.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function is used to initialize the HAL Library; it must be the first
+  *         instruction to be executed in the main program (before to call any other
+  *         HAL function), it performs the following:
+  *           Configures the SysTick to generate an interrupt each 1 millisecond,
+  *           which is clocked by the HSI (at this stage, the clock is not yet
+  *           configured and thus the system is running from the internal HSI at 16 MHz).
+  *           Set NVIC Group Priority to 4.
+  *           Calls the HAL_MspInit() callback function defined in user file
+  *           "stm32h7xx_hal_msp.c" to do the global low level hardware initialization
+  *
+  * @note   SysTick is used as time base for the HAL_Delay() function, the application
+  *         need to ensure that the SysTick time base is always set to 1 millisecond
+  *         to have correct HAL operation.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_Init(void)
+{
+
+uint32_t common_system_clock;
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+   /* Configure Cortex-M4 Instruction cache through ART accelerator */
+   __HAL_RCC_ART_CLK_ENABLE();                   /* Enable the Cortex-M4 ART Clock */
+   __HAL_ART_CONFIG_BASE_ADDRESS(0x08100000UL);  /* Configure the Cortex-M4 ART Base address to the Flash Bank 2 : */
+   __HAL_ART_ENABLE();                           /* Enable the Cortex-M4 ART */
+#endif /* DUAL_CORE &&  CORE_CM4 */
+
+  /* Set Interrupt Group Priority */
+  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+  /* Update the SystemCoreClock global variable */
+#if defined(RCC_D1CFGR_D1CPRE)
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
+#else
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
+#endif
+
+  /* Update the SystemD2Clock global variable */
+#if defined(RCC_D1CFGR_HPRE)
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+#else
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+#endif
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  SystemCoreClock = SystemD2Clock;
+#else
+  SystemCoreClock = common_system_clock;
+#endif /* DUAL_CORE && CORE_CM4 */
+
+  /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
+  if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Init the low level hardware */
+  HAL_MspInit();
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function de-Initializes common part of the HAL and stops the systick.
+  *         This function is optional.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DeInit(void)
+{
+  /* Reset of all peripherals */
+  __HAL_RCC_AHB3_FORCE_RESET();
+  __HAL_RCC_AHB3_RELEASE_RESET();
+
+  __HAL_RCC_AHB1_FORCE_RESET();
+  __HAL_RCC_AHB1_RELEASE_RESET();
+
+  __HAL_RCC_AHB2_FORCE_RESET();
+  __HAL_RCC_AHB2_RELEASE_RESET();
+
+  __HAL_RCC_AHB4_FORCE_RESET();
+ __HAL_RCC_AHB4_RELEASE_RESET();
+
+  __HAL_RCC_APB3_FORCE_RESET();
+  __HAL_RCC_APB3_RELEASE_RESET();
+
+  __HAL_RCC_APB1L_FORCE_RESET();
+  __HAL_RCC_APB1L_RELEASE_RESET();
+
+  __HAL_RCC_APB1H_FORCE_RESET();
+  __HAL_RCC_APB1H_RELEASE_RESET();
+
+   __HAL_RCC_APB2_FORCE_RESET();
+   __HAL_RCC_APB2_RELEASE_RESET();
+
+  __HAL_RCC_APB4_FORCE_RESET();
+  __HAL_RCC_APB4_RELEASE_RESET();
+
+  /* De-Init the low level hardware */
+  HAL_MspDeInit();
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the MSP.
+  * @retval None
+  */
+__weak void HAL_MspInit(void)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes the MSP.
+  * @retval None
+  */
+__weak void HAL_MspDeInit(void)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief This function configures the source of the time base.
+  *        The time source is configured  to have 1ms time base with a dedicated
+  *        Tick interrupt priority.
+  * @note This function is called  automatically at the beginning of program after
+  *       reset by HAL_Init() or at any time when clock is reconfigured  by HAL_RCC_ClockConfig().
+  * @note In the default implementation, SysTick timer is the source of time base.
+  *       It is used to generate interrupts at regular time intervals.
+  *       Care must be taken if HAL_Delay() is called from a peripheral ISR process,
+  *       The the SysTick interrupt must have higher priority (numerically lower)
+  *       than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+  *       The function is declared as __weak  to be overwritten  in case of other
+  *       implementation  in user file.
+  * @param TickPriority: Tick interrupt priority.
+  * @retval HAL status
+  */
+__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+  /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/
+  if((uint32_t)uwTickFreq == 0UL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Configure the SysTick to have interrupt in 1ms time basis*/
+  if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Configure the SysTick IRQ priority */
+  if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+  {
+    HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
+    uwTickPrio = TickPriority;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Group2 HAL Control functions
+ *  @brief    HAL Control functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### HAL Control functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Provide a tick value in millisecond
+      (+) Provide a blocking delay in millisecond
+      (+) Suspend the time base source interrupt
+      (+) Resume the time base source interrupt
+      (+) Get the HAL API driver version
+      (+) Get the device identifier
+      (+) Get the device revision identifier
+      (+) Enable/Disable Debug module during SLEEP mode
+      (+) Enable/Disable Debug module during STOP mode
+      (+) Enable/Disable Debug module during STANDBY mode
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief This function is called to increment  a global variable "uwTick"
+  *        used as application time base.
+  * @note In the default implementation, this variable is incremented each 1ms
+  *       in Systick ISR.
+ * @note This function is declared as __weak to be overwritten in case of other
+  *      implementations in user file.
+  * @retval None
+  */
+__weak void HAL_IncTick(void)
+{
+  uwTick += (uint32_t)uwTickFreq;
+}
+
+/**
+  * @brief Provides a tick value in millisecond.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @retval tick value
+  */
+__weak uint32_t HAL_GetTick(void)
+{
+  return uwTick;
+}
+
+/**
+  * @brief This function returns a tick priority.
+  * @retval tick priority
+  */
+uint32_t HAL_GetTickPrio(void)
+{
+  return uwTickPrio;
+}
+
+/**
+  * @brief Set new tick Freq.
+  * @retval Status
+  */
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
+{
+  HAL_StatusTypeDef status  = HAL_OK;
+  HAL_TickFreqTypeDef prevTickFreq;
+
+  assert_param(IS_TICKFREQ(Freq));
+
+  if (uwTickFreq != Freq)
+  {
+
+    /* Back up uwTickFreq frequency */
+    prevTickFreq = uwTickFreq;
+
+    /* Update uwTickFreq global variable used by HAL_InitTick() */
+    uwTickFreq = Freq;
+
+    /* Apply the new tick Freq  */
+    status = HAL_InitTick(uwTickPrio);
+    if (status != HAL_OK)
+    {
+      /* Restore previous tick frequency */
+      uwTickFreq = prevTickFreq;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief Return tick frequency.
+  * @retval tick period in Hz
+  */
+HAL_TickFreqTypeDef HAL_GetTickFreq(void)
+{
+  return uwTickFreq;
+}
+
+/**
+  * @brief This function provides minimum delay (in milliseconds) based
+  *        on variable incremented.
+  * @note In the default implementation , SysTick timer is the source of time base.
+  *       It is used to generate interrupts at regular time intervals where uwTick
+  *       is incremented.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @param Delay  specifies the delay time length, in milliseconds.
+  * @retval None
+  */
+__weak void HAL_Delay(uint32_t Delay)
+{
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t wait = Delay;
+
+  /* Add a freq to guarantee minimum wait */
+  if (wait < HAL_MAX_DELAY)
+  {
+    wait += (uint32_t)(uwTickFreq);
+  }
+
+  while ((HAL_GetTick() - tickstart) < wait)
+  {
+  }
+}
+
+/**
+  * @brief Suspend Tick increment.
+  * @note In the default implementation , SysTick timer is the source of time base. It is
+  *       used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
+  *       is called, the the SysTick interrupt will be disabled and so Tick increment
+  *       is suspended.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @retval None
+  */
+__weak void HAL_SuspendTick(void)
+{
+  /* Disable SysTick Interrupt */
+  SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
+}
+
+/**
+  * @brief Resume Tick increment.
+  * @note In the default implementation , SysTick timer is the source of time base. It is
+  *       used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
+  *       is called, the the SysTick interrupt will be enabled and so Tick increment
+  *       is resumed.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @retval None
+  */
+__weak void HAL_ResumeTick(void)
+{
+  /* Enable SysTick Interrupt */
+  SysTick->CTRL  |= SysTick_CTRL_TICKINT_Msk;
+}
+
+/**
+  * @brief  Returns the HAL revision
+  * @retval version : 0xXYZR (8bits for each decimal, R for RC)
+  */
+uint32_t HAL_GetHalVersion(void)
+{
+ return __STM32H7xx_HAL_VERSION;
+}
+
+/**
+  * @brief  Returns the device revision identifier.
+  * @retval Device revision identifier
+  */
+uint32_t HAL_GetREVID(void)
+{
+   return((DBGMCU->IDCODE) >> 16);
+}
+
+/**
+  * @brief  Returns the device identifier.
+  * @retval Device identifier
+  */
+uint32_t HAL_GetDEVID(void)
+{
+   return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
+}
+
+/**
+  * @brief  Return the first word of the unique device identifier (UID based on 96 bits)
+  * @retval Device identifier
+  */
+uint32_t HAL_GetUIDw0(void)
+{
+  return(READ_REG(*((uint32_t *)UID_BASE)));
+}
+
+/**
+  * @brief  Return the second word of the unique device identifier (UID based on 96 bits)
+  * @retval Device identifier
+  */
+uint32_t HAL_GetUIDw1(void)
+{
+  return(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
+}
+
+/**
+  * @brief  Return the third word of the unique device identifier (UID based on 96 bits)
+  * @retval Device identifier
+  */
+uint32_t HAL_GetUIDw2(void)
+{
+  return(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
+}
+
+/**
+  * @brief Configure the internal voltage reference buffer voltage scale.
+  * @param VoltageScaling  specifies the output voltage to achieve
+  *          This parameter can be one of the following values:
+  *            @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 2.048 V.
+  *                                                This requires VDDA equal to or higher than 2.4 V.
+  *            @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT2 around 2.5 V.
+  *                                                This requires VDDA equal to or higher than 2.8 V.
+  *            @arg SYSCFG_VREFBUF_VOLTAGE_SCALE2: VREF_OUT3 around 1.5 V.
+  *                                                This requires VDDA equal to or higher than 1.8 V.
+  *            @arg SYSCFG_VREFBUF_VOLTAGE_SCALE3: VREF_OUT4 around 1.8 V.
+  *                                                This requires VDDA equal to or higher than 2.1 V.
+  * @retval None
+  */
+void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling));
+
+  MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling);
+}
+
+/**
+  * @brief Configure the internal voltage reference buffer high impedance mode.
+  * @param Mode  specifies the high impedance mode
+  *          This parameter can be one of the following values:
+  *            @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output.
+  *            @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance.
+  * @retval None
+  */
+void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode));
+
+  MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode);
+}
+
+/**
+  * @brief  Tune the Internal Voltage Reference buffer (VREFBUF).
+  * @retval None
+  */
+void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue));
+
+  MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue);
+}
+
+/**
+  * @brief  Enable the Internal Voltage Reference buffer (VREFBUF).
+  * @retval HAL_OK/HAL_TIMEOUT
+  */
+HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void)
+{
+  uint32_t  tickstart;
+
+  SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
+
+  /* Get Start Tick*/
+  tickstart = HAL_GetTick();
+
+  /* Wait for VRR bit  */
+  while(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0UL)
+  {
+    if((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the Internal Voltage Reference buffer (VREFBUF).
+  *
+  * @retval None
+  */
+void HAL_SYSCFG_DisableVREFBUF(void)
+{
+  CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
+}
+
+#if defined(SYSCFG_PMCR_EPIS_SEL)
+/**
+  * @brief  Ethernet PHY Interface Selection either MII or RMII
+  * @param  SYSCFG_ETHInterface: Selects the Ethernet PHY interface
+  *   This parameter can be one of the following values:
+  *   @arg SYSCFG_ETH_MII : Select the Media Independent Interface
+  *   @arg SYSCFG_ETH_RMII: Select the Reduced Media Independent Interface
+  * @retval None
+  */
+void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface)
+{
+  /* Check the parameter */
+  assert_param(IS_SYSCFG_ETHERNET_CONFIG(SYSCFG_ETHInterface));
+
+  MODIFY_REG(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL, (uint32_t)(SYSCFG_ETHInterface));
+}
+#endif /* SYSCFG_PMCR_EPIS_SEL */
+
+/**
+  * @brief  Analog Switch control for dual analog pads.
+  * @param  SYSCFG_AnalogSwitch: Selects the analog pad
+  *   This parameter can be one or a combination of the following values:
+  *   @arg SYSCFG_SWITCH_PA0 : Select PA0 analog switch
+  *   @arg SYSCFG_SWITCH_PA1:  Select PA1 analog switch
+  *   @arg SYSCFG_SWITCH_PC2 : Select PC2 analog switch
+  *   @arg SYSCFG_SWITCH_PC3:  Select PC3 analog switch
+  * @param  SYSCFG_SwitchState: Open or Close the analog switch between dual pads (PXn and PXn_C)
+  *   This parameter can be one or a combination of the following values:
+  *   @arg SYSCFG_SWITCH_PA0_OPEN
+  *   @arg SYSCFG_SWITCH_PA0_CLOSE
+  *   @arg SYSCFG_SWITCH_PA1_OPEN
+  *   @arg SYSCFG_SWITCH_PA1_CLOSE
+  *   @arg SYSCFG_SWITCH_PC2_OPEN
+  *   @arg SYSCFG_SWITCH_PC2_CLOSE
+  *   @arg SYSCFG_SWITCH_PC3_OPEN
+  *   @arg SYSCFG_SWITCH_PC3_CLOSE
+  * @retval None
+  */
+
+void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState )
+{
+  /* Check the parameter */
+  assert_param(IS_SYSCFG_ANALOG_SWITCH(SYSCFG_AnalogSwitch));
+  assert_param(IS_SYSCFG_SWITCH_STATE(SYSCFG_SwitchState));
+
+  MODIFY_REG(SYSCFG->PMCR, (uint32_t) SYSCFG_AnalogSwitch, (uint32_t)(SYSCFG_SwitchState));
+}
+
+#if defined(SYSCFG_PMCR_BOOSTEN)
+/**
+  * @brief  Enables the booster to reduce the total harmonic distortion of the analog
+  *         switch when the supply voltage is lower than 2.7 V.
+  * @note   Activating the booster allows to guaranty the analog switch AC performance
+  *         when the supply voltage is below 2.7 V: in this case, the analog switch
+  *         performance is the same on the full voltage range
+  * @retval None
+  */
+void HAL_SYSCFG_EnableBOOST(void)
+{
+ SET_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
+}
+
+/**
+  * @brief  Disables the booster
+  * @note   Activating the booster allows to guaranty the analog switch AC performance
+  *         when the supply voltage is below 2.7 V: in this case, the analog switch
+  *         performance is the same on the full voltage range
+  * @retval None
+  */
+void HAL_SYSCFG_DisableBOOST(void)
+{
+ CLEAR_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
+}
+#endif /* SYSCFG_PMCR_BOOSTEN */
+
+#if defined (SYSCFG_UR2_BOOT_ADD0) ||  defined (SYSCFG_UR2_BCM7_ADD0)
+/**
+  * @brief  BootCM7 address 0 configuration
+  * @param  BootRegister :Specifies the Boot Address register (Address0 or Address1)
+  *   This parameter can be one of the following values:
+  *   @arg SYSCFG_BOOT_ADDR0 : Select the boot address0
+  *   @arg SYSCFG_BOOT_ADDR1:  Select the boot address1
+  * @param  BootAddress :Specifies the CM7 Boot Address to be loaded in Address0 or Address1
+  * @retval None
+  */
+void HAL_SYSCFG_CM7BootAddConfig(uint32_t BootRegister, uint32_t BootAddress)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_BOOT_REGISTER(BootRegister));
+  assert_param(IS_SYSCFG_BOOT_ADDRESS(BootAddress));
+  if ( BootRegister == SYSCFG_BOOT_ADDR0 )
+  {
+    /* Configure CM7 BOOT ADD0 */
+#if defined(DUAL_CORE)
+    MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0, ((BootAddress >> 16) << SYSCFG_UR2_BCM7_ADD0_Pos));
+#else
+    MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0, ((BootAddress >> 16) << SYSCFG_UR2_BOOT_ADD0_Pos));
+#endif /*DUAL_CORE*/
+  }
+  else
+  {
+    /* Configure CM7 BOOT ADD1 */
+#if defined(DUAL_CORE)
+    MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1, (BootAddress >> 16));
+#else
+    MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1, (BootAddress >> 16));
+#endif /*DUAL_CORE*/
+  }
+}
+#endif /* SYSCFG_UR2_BOOT_ADD0 || SYSCFG_UR2_BCM7_ADD0 */
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  BootCM4 address 0 configuration
+  * @param  BootRegister :Specifies the Boot Address register (Address0 or Address1)
+  *   This parameter can be one of the following values:
+  *   @arg SYSCFG_BOOT_ADDR0 : Select the boot address0
+  *   @arg SYSCFG_BOOT_ADDR1:  Select the boot address1
+  * @param  BootAddress :Specifies the CM4 Boot Address to be loaded in Address0 or Address1
+  * @retval None
+  */
+void HAL_SYSCFG_CM4BootAddConfig(uint32_t BootRegister, uint32_t BootAddress)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_BOOT_REGISTER(BootRegister));
+  assert_param(IS_SYSCFG_BOOT_ADDRESS(BootAddress));
+
+  if ( BootRegister == SYSCFG_BOOT_ADDR0 )
+  {
+    /* Configure CM4 BOOT ADD0 */
+    MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0, ((BootAddress >> 16)<< SYSCFG_UR3_BCM4_ADD0_Pos));
+  }
+
+  else
+  {
+    /* Configure CM4 BOOT ADD1 */
+    MODIFY_REG(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1, (BootAddress >> 16));
+  }
+}
+
+/**
+  * @brief  Enables the Cortex-M7 boot
+  * @retval None
+  */
+void HAL_SYSCFG_EnableCM7BOOT(void)
+{
+ SET_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM7);
+}
+
+/**
+  * @brief  Disables the Cortex-M7 boot
+  * @note   Disabling the boot will gate the CPU clock
+  * @retval None
+  */
+void HAL_SYSCFG_DisableCM7BOOT(void)
+{
+ CLEAR_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM7) ;
+}
+
+/**
+  * @brief  Enables the Cortex-M4 boot
+  * @retval None
+  */
+void HAL_SYSCFG_EnableCM4BOOT(void)
+{
+ SET_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4);
+}
+
+/**
+  * @brief  Disables the Cortex-M4 boot
+  * @note   Disabling the boot will gate the CPU clock
+  * @retval None
+  */
+void HAL_SYSCFG_DisableCM4BOOT(void)
+{
+  CLEAR_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4);
+}
+#endif /*DUAL_CORE*/
+/**
+  * @brief  Enables the I/O Compensation Cell.
+  * @note   The I/O compensation cell can be used only when the device supply
+  *         voltage ranges from 2.4 to 3.6 V.
+  * @retval None
+  */
+void HAL_EnableCompensationCell(void)
+{
+  SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN) ;
+}
+
+/**
+  * @brief  Power-down the I/O Compensation Cell.
+  * @note   The I/O compensation cell can be used only when the device supply
+  *         voltage ranges from 2.4 to 3.6 V.
+  * @retval None
+  */
+void HAL_DisableCompensationCell(void)
+{
+  CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN);
+}
+
+
+/**
+  * @brief  To Enable optimize the I/O speed when the product voltage is low.
+  * @note   This bit is active only if PRODUCT_BELOW_25V user option bit is set. It must be
+  *         used only if the product supply voltage is below 2.5 V. Setting this bit when VDD is
+  *         higher than 2.5 V might be destructive.
+  * @retval None
+  */
+void HAL_SYSCFG_EnableIOSpeedOptimize(void)
+{
+#if defined(SYSCFG_CCCSR_HSLV)
+  SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);
+#else
+  SET_BIT(SYSCFG->CCCSR, (SYSCFG_CCCSR_HSLV0| SYSCFG_CCCSR_HSLV1 | SYSCFG_CCCSR_HSLV2  | SYSCFG_CCCSR_HSLV3));
+#endif   /* SYSCFG_CCCSR_HSLV */
+}
+
+/**
+  * @brief  To Disable optimize the I/O speed when the product voltage is low.
+  * @note   This bit is active only if PRODUCT_BELOW_25V user option bit is set. It must be
+  *         used only if the product supply voltage is below 2.5 V. Setting this bit when VDD is
+  *         higher than 2.5 V might be destructive.
+  * @retval None
+  */
+void HAL_SYSCFG_DisableIOSpeedOptimize(void)
+{
+#if defined(SYSCFG_CCCSR_HSLV)
+  CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);
+#else
+  CLEAR_BIT(SYSCFG->CCCSR, (SYSCFG_CCCSR_HSLV0| SYSCFG_CCCSR_HSLV1 | SYSCFG_CCCSR_HSLV2  | SYSCFG_CCCSR_HSLV3));
+#endif   /* SYSCFG_CCCSR_HSLV */
+}
+
+/**
+  * @brief  Code selection for the I/O Compensation cell
+  * @param  SYSCFG_CompCode: Selects the code to be applied for the I/O compensation cell
+  *   This parameter can be one of the following values:
+  *   @arg SYSCFG_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR)
+  *   @arg SYSCFG_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR)
+  * @retval None
+  */
+void HAL_SYSCFG_CompensationCodeSelect(uint32_t SYSCFG_CompCode)
+{
+  /* Check the parameter */
+  assert_param(IS_SYSCFG_CODE_SELECT(SYSCFG_CompCode));
+  MODIFY_REG(SYSCFG->CCCSR, SYSCFG_CCCSR_CS, (uint32_t)(SYSCFG_CompCode));
+}
+
+/**
+  * @brief  Code selection for the I/O Compensation cell
+  * @param  SYSCFG_PMOSCode: PMOS compensation code
+  *         This code is applied to the I/O compensation cell when the CS bit of the
+  *          SYSCFG_CMPCR is set
+  * @param  SYSCFG_NMOSCode: NMOS compensation code
+  *         This code is applied to the I/O compensation cell when the CS bit of the
+  *          SYSCFG_CMPCR is set
+  * @retval None
+  */
+void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode )
+{
+  /* Check the parameter */
+  assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_PMOSCode));
+  assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_NMOSCode));
+  MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC|SYSCFG_CCCR_PCC, (((uint32_t)(SYSCFG_PMOSCode)<< 4)|(uint32_t)(SYSCFG_NMOSCode)) );
+}
+
+#if defined(SYSCFG_CCCR_NCC_MMC)
+/**
+  * @brief  Code selection for the I/O Compensation cell
+  * @param  SYSCFG_PMOSCode: VDDMMC PMOS compensation code
+  *         This code is applied to the I/O compensation cell when the CS bit of the
+  *          SYSCFG_CMPCR is set
+  * @param  SYSCFG_NMOSCode: VDDMMC NMOS compensation code
+  *         This code is applied to the I/O compensation cell when the CS bit of the
+  *          SYSCFG_CMPCR is set
+  * @retval None
+  */
+void HAL_SYSCFG_VDDMMC_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode )
+{
+  /* Check the parameter */
+  assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_PMOSCode));
+  assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_NMOSCode));
+  MODIFY_REG(SYSCFG->CCCR, (SYSCFG_CCCR_NCC_MMC | SYSCFG_CCCR_PCC_MMC), (((uint32_t)(SYSCFG_PMOSCode)<< 4)|(uint32_t)(SYSCFG_NMOSCode)) );
+}
+#endif /* SYSCFG_CCCR_NCC_MMC */
+
+/**
+  * @brief  Enable the Debug Module during Domain1/CDomain SLEEP mode
+  * @retval None
+  */
+void HAL_EnableDBGSleepMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
+}
+
+/**
+  * @brief  Disable the Debug Module during Domain1/CDomain SLEEP mode
+  * @retval None
+  */
+void HAL_DisableDBGSleepMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
+}
+
+
+/**
+  * @brief  Enable the Debug Module during Domain1/CDomain STOP mode
+  * @retval None
+  */
+void HAL_EnableDBGStopMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
+}
+
+/**
+  * @brief  Disable the Debug Module during Domain1/CDomain STOP mode
+  * @retval None
+  */
+void HAL_DisableDBGStopMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
+}
+
+/**
+  * @brief  Enable the Debug Module during Domain1/CDomain STANDBY mode
+  * @retval None
+  */
+void HAL_EnableDBGStandbyMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
+}
+
+/**
+  * @brief  Disable the Debug Module during Domain1/CDomain STANDBY mode
+  * @retval None
+  */
+void HAL_DisableDBGStandbyMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Enable the Debug Module during Domain1 SLEEP mode
+  * @retval None
+  */
+void HAL_EnableDomain2DBGSleepMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2);
+}
+
+/**
+  * @brief  Disable the Debug Module during Domain2 SLEEP mode
+  * @retval None
+  */
+void HAL_DisableDomain2DBGSleepMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2);
+}
+
+/**
+  * @brief  Enable the Debug Module during Domain2 STOP mode
+  * @retval None
+  */
+void HAL_EnableDomain2DBGStopMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2);
+}
+
+/**
+  * @brief  Disable the Debug Module during Domain2 STOP mode
+  * @retval None
+  */
+void HAL_DisableDomain2DBGStopMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2);
+}
+
+/**
+  * @brief  Enable the Debug Module during Domain2 STANDBY mode
+  * @retval None
+  */
+void HAL_EnableDomain2DBGStandbyMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2);
+}
+
+/**
+  * @brief  Disable the Debug Module during Domain2 STANDBY mode
+  * @retval None
+  */
+void HAL_DisableDomain2DBGStandbyMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2);
+}
+#endif /*DUAL_CORE*/
+
+/**
+  * @brief  Enable the Debug Module during Domain3/SRDomain STOP mode
+  * @retval None
+  */
+void HAL_EnableDomain3DBGStopMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
+}
+/**
+  * @brief  Disable the Debug Module during Domain3/SRDomain STOP mode
+  * @retval None
+  */
+void HAL_DisableDomain3DBGStopMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
+}
+
+/**
+  * @brief  Enable the Debug Module during Domain3/SRDomain STANDBY mode
+  * @retval None
+  */
+void HAL_EnableDomain3DBGStandbyMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
+}
+
+/**
+  * @brief  Disable the Debug Module during Domain3/SRDomain STANDBY mode
+  * @retval None
+  */
+void HAL_DisableDomain3DBGStandbyMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
+}
+
+/**
+  * @brief  Set the FMC Memory Mapping Swapping config.
+  * @param  BankMapConfig: Defines the FMC Bank mapping configuration. This parameter can be
+            FMC_SWAPBMAP_DISABLE, FMC_SWAPBMAP_SDRAM_SRAM, FMC_SWAPBMAP_SDRAMB2
+  * @retval HAL state
+  */
+void HAL_SetFMCMemorySwappingConfig(uint32_t BankMapConfig)
+{
+  /* Check the parameter */
+  assert_param(IS_FMC_SWAPBMAP_MODE(BankMapConfig));
+  MODIFY_REG(FMC_Bank1_R->BTCR[0], FMC_BCR1_BMAP, BankMapConfig);
+}
+
+/**
+  * @brief  Get FMC Bank mapping mode.
+  * @retval The FMC Bank mapping mode. This parameter can be
+            FMC_SWAPBMAP_DISABLE, FMC_SWAPBMAP_SDRAM_SRAM, FMC_SWAPBMAP_SDRAMB2
+*/
+uint32_t HAL_GetFMCMemorySwappingConfig(void)
+{
+  return READ_BIT(FMC_Bank1_R->BTCR[0], FMC_BCR1_BMAP);
+}
+
+/**
+  * @brief  Configure the EXTI input event line edge
+  * @note    No edge configuration for direct lines but for configurable lines:(EXTI_LINE0..EXTI_LINE21),
+  *          EXTI_LINE49,EXTI_LINE51,EXTI_LINE82,EXTI_LINE84,EXTI_LINE85 and EXTI_LINE86.
+  * @param   EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
+  *         (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
+  * @param   EXTI_Edge: Specifies  EXTI line Edge used.
+  *          This parameter can be one of the following values :
+  *   @arg EXTI_RISING_EDGE : Configurable line, with Rising edge trigger detection
+  *   @arg EXTI_FALLING_EDGE: Configurable line, with Falling edge trigger detection
+  * @retval None
+  */
+void HAL_EXTI_EdgeConfig(uint32_t EXTI_Line , uint32_t EXTI_Edge )
+{
+  /* Check the parameter */
+  assert_param(IS_HAL_EXTI_CONFIG_LINE(EXTI_Line));
+  assert_param(IS_EXTI_EDGE_LINE(EXTI_Edge));
+
+  /* Clear Rising Falling edge configuration */
+  CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+  CLEAR_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+
+  if( (EXTI_Edge & EXTI_RISING_EDGE) == EXTI_RISING_EDGE)
+  {
+   SET_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+  }
+  if( (EXTI_Edge & EXTI_FALLING_EDGE) == EXTI_FALLING_EDGE)
+  {
+   SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+  }
+}
+
+/**
+  * @brief  Generates a Software interrupt on selected EXTI line.
+  * @param   EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
+  *          (EXTI_LINE0..EXTI_LINE21),EXTI_LINE49,EXTI_LINE51,EXTI_LINE82,EXTI_LINE84,EXTI_LINE85 and EXTI_LINE86.
+  * @retval None
+  */
+void HAL_EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
+{
+  /* Check the parameters */
+  assert_param(IS_HAL_EXTI_CONFIG_LINE(EXTI_Line));
+
+  SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->SWIER1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+}
+
+
+/**
+  * @brief  Clears the EXTI's line pending flags for Domain D1
+  * @param   EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
+  *         (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
+  * @retval None
+  */
+void HAL_EXTI_D1_ClearFlag(uint32_t EXTI_Line)
+{
+  /* Check the parameters */
+ assert_param(IS_EXTI_D1_LINE(EXTI_Line));
+ WRITE_REG(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->PR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Clears the EXTI's line pending flags for Domain D2
+  * @param   EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
+  *         (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
+  * @retval None
+  */
+void HAL_EXTI_D2_ClearFlag(uint32_t EXTI_Line)
+{
+  /* Check the parameters */
+ assert_param(IS_EXTI_D2_LINE(EXTI_Line));
+ WRITE_REG(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->PR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+}
+
+#endif /*DUAL_CORE*/
+/**
+  * @brief  Configure the EXTI input event line for Domain D1
+  * @param   EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
+  *         (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
+  * @param   EXTI_Mode: Specifies which EXTI line is used as interrupt or an event.
+  *          This parameter can be one or a combination of the following values :
+  *   @arg EXTI_MODE_IT :  Interrupt Mode selected
+  *   @arg EXTI_MODE_EVT : Event Mode selected
+  * @param   EXTI_LineCmd controls (Enable/Disable) the EXTI line.
+
+  * @retval None
+  */
+void HAL_EXTI_D1_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode,  uint32_t EXTI_LineCmd )
+{
+  /* Check the parameter */
+  assert_param(IS_EXTI_D1_LINE(EXTI_Line));
+  assert_param(IS_EXTI_MODE_LINE(EXTI_Mode));
+
+  if( (EXTI_Mode & EXTI_MODE_IT) == EXTI_MODE_IT)
+  {
+     if( EXTI_LineCmd == 0UL)
+     {
+       /* Clear EXTI line configuration */
+        CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)),(uint32_t)(1UL << (EXTI_Line & 0x1FUL)) );
+     }
+     else
+     {
+        SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+     }
+  }
+
+  if( (EXTI_Mode & EXTI_MODE_EVT) == EXTI_MODE_EVT)
+  {
+    if( EXTI_LineCmd == 0UL)
+    {
+      /* Clear EXTI line configuration */
+      CLEAR_BIT(  *(__IO uint32_t *) (((uint32_t) &(EXTI_D1->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+    }
+    else
+    {
+      SET_BIT(  *(__IO uint32_t *) (((uint32_t) &(EXTI_D1->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+    }
+  }
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Configure the EXTI input event line for Domain D2
+  * @param   EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
+  *         (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
+  * @param   EXTI_Mode: Specifies which EXTI line is used as interrupt or an event.
+  *          This parameter can be one or a combination of the following values :
+  *   @arg EXTI_MODE_IT :  Interrupt Mode selected
+  *   @arg EXTI_MODE_EVT : Event Mode selected
+  * @param   EXTI_LineCmd controls (Enable/Disable) the EXTI line.
+
+  * @retval None
+  */
+void HAL_EXTI_D2_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode,  uint32_t EXTI_LineCmd )
+{
+  /* Check the parameter */
+  assert_param(IS_EXTI_D2_LINE(EXTI_Line));
+  assert_param(IS_EXTI_MODE_LINE(EXTI_Mode));
+
+  if( (EXTI_Mode & EXTI_MODE_IT) == EXTI_MODE_IT)
+  {
+    if( EXTI_LineCmd == 0UL)
+    {
+    /* Clear EXTI line configuration */
+     CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)),(uint32_t)(1UL << (EXTI_Line & 0x1FUL)) );
+    }
+    else
+    {
+     SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+    }
+  }
+
+  if( (EXTI_Mode & EXTI_MODE_EVT) == EXTI_MODE_EVT)
+  {
+    if( EXTI_LineCmd == 0UL)
+    {
+      /* Clear EXTI line configuration */
+      CLEAR_BIT(  *(__IO uint32_t *) (((uint32_t) &(EXTI_D2->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+    }
+    else
+    {
+      SET_BIT(  *(__IO uint32_t *) (((uint32_t) &(EXTI_D2->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+    }
+  }
+}
+#endif /*DUAL_CORE*/
+
+/**
+  * @brief  Configure the EXTI input event line for Domain D3
+  * @param   EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
+  *         (EXTI_LINE0...EXTI_LINE15),(EXTI_LINE19...EXTI_LINE21),EXTI_LINE25, EXTI_LINE34,
+  *          EXTI_LINE35,EXTI_LINE41,(EXTI_LINE48...EXTI_LINE53)
+  * @param   EXTI_LineCmd controls (Enable/Disable) the EXTI line.
+  * @param   EXTI_ClearSrc: Specifies the clear source of D3 pending event.
+  *          This parameter can be one of the following values :
+  *   @arg BDMA_CH6_CLEAR : BDMA ch6 event selected as D3 domain pendclear source
+  *   @arg BDMA_CH7_CLEAR : BDMA ch7 event selected as D3 domain pendclear source
+  *   @arg LPTIM4_OUT_CLEAR : LPTIM4 out selected as D3 domain pendclear source
+  *   @arg LPTIM5_OUT_CLEAR : LPTIM5 out selected as D3 domain pendclear source
+  * @retval None
+  */
+void HAL_EXTI_D3_EventInputConfig(uint32_t EXTI_Line, uint32_t EXTI_LineCmd , uint32_t EXTI_ClearSrc  )
+{
+  __IO uint32_t *pRegv;
+
+  /* Check the parameter */
+  assert_param(IS_EXTI_D3_LINE(EXTI_Line));
+  assert_param(IS_EXTI_D3_CLEAR(EXTI_ClearSrc));
+
+  if( EXTI_LineCmd == 0UL)
+  {
+    /* Clear EXTI line configuration */
+    CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->D3PMR1)) + ((EXTI_Line >> 5 ) * 0x20UL)),(uint32_t)(1UL << (EXTI_Line & 0x1FUL)) );
+  }
+  else
+  {
+    SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->D3PMR1)) +((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+  }
+
+  if(((EXTI_Line>>4)%2UL) == 0UL)
+  {
+    pRegv = (__IO uint32_t *) (((uint32_t) &(EXTI->D3PCR1L)) + ((EXTI_Line >> 5 ) * 0x20UL));
+  }
+  else
+  {
+    pRegv = (__IO uint32_t *) (((uint32_t) &(EXTI->D3PCR1H)) + ((EXTI_Line >> 5 ) * 0x20UL));
+  }
+  MODIFY_REG(*pRegv, (uint32_t)(3UL << ((EXTI_Line*2UL) & 0x1FUL)), (uint32_t)(EXTI_ClearSrc << ((EXTI_Line*2UL) & 0x1FUL)));
+
+}
+
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c
new file mode 100644
index 00000000..631f432f
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c
@@ -0,0 +1,533 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_cortex.c
+  * @author  MCD Application Team
+  * @brief   CORTEX HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the CORTEX:
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions
+  *
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+
+    [..]
+    *** How to configure Interrupts using CORTEX HAL driver ***
+    ===========================================================
+    [..]
+    This section provides functions allowing to configure the NVIC interrupts (IRQ).
+    The Cortex-M exceptions are managed by CMSIS functions.
+
+    (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
+        function according to the following table.
+    (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
+    (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
+    (#) please refer to programming manual for details in how to configure priority.
+
+     -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
+         The pending IRQ priority will be managed only by the sub priority.
+
+     -@- IRQ priority order (sorted by highest to lowest priority):
+        (+@) Lowest preemption priority
+        (+@) Lowest sub priority
+        (+@) Lowest hardware priority (IRQ number)
+
+    [..]
+    *** How to configure Systick using CORTEX HAL driver ***
+    ========================================================
+    [..]
+    Setup SysTick Timer for time base.
+
+   (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
+       is a CMSIS function that:
+        (++) Configures the SysTick Reload register with value passed as function parameter.
+        (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
+        (++) Resets the SysTick Counter register.
+        (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
+        (++) Enables the SysTick Interrupt.
+        (++) Starts the SysTick Counter.
+
+   (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
+       HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
+       HAL_SYSTICK_Config() function call. The HAL_SYSTICK_CLKSourceConfig() macro is defined
+       inside the stm32h7xx_hal_cortex.h file.
+
+   (+) You can change the SysTick IRQ priority by calling the
+       HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
+       call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
+
+   (+) To adjust the SysTick time base, use the following formula:
+
+       Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
+       (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
+       (++) Reload Value should not exceed 0xFFFFFF
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup CORTEX CORTEX
+  * @brief CORTEX HAL module driver
+  * @{
+  */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
+  * @{
+  */
+
+
+/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+  ==============================================================================
+              ##### Initialization and de-initialization functions #####
+  ==============================================================================
+    [..]
+      This section provides the CORTEX HAL driver functions allowing to configure Interrupts
+      Systick functionalities
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Sets the priority grouping field (preemption priority and subpriority)
+  *         using the required unlock sequence.
+  * @param  PriorityGroup The priority grouping bits length.
+  *         This parameter can be one of the following values:
+  *         @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
+  *                                    4 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
+  *                                    3 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
+  *                                    2 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
+  *                                    1 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
+  *                                    0 bits for subpriority
+  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
+  *         The pending IRQ priority will be managed only by the subpriority.
+  * @retval None
+  */
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+
+  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
+  NVIC_SetPriorityGrouping(PriorityGroup);
+}
+
+/**
+  * @brief  Sets the priority of an interrupt.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
+  * @param  PreemptPriority The preemption priority for the IRQn channel.
+  *         This parameter can be a value between 0 and 15
+  *         A lower priority value indicates a higher priority
+  * @param  SubPriority the subpriority level for the IRQ channel.
+  *         This parameter can be a value between 0 and 15
+  *         A lower priority value indicates a higher priority.
+  * @retval None
+  */
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t prioritygroup;
+
+  /* Check the parameters */
+  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
+  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
+
+  prioritygroup = NVIC_GetPriorityGrouping();
+
+  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
+}
+
+/**
+  * @brief  Enables a device specific interrupt in the NVIC interrupt controller.
+  * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
+  *         function should be called before.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+  /* Enable interrupt */
+  NVIC_EnableIRQ(IRQn);
+}
+
+/**
+  * @brief  Disables a device specific interrupt in the NVIC interrupt controller.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+  /* Disable interrupt */
+  NVIC_DisableIRQ(IRQn);
+}
+
+/**
+  * @brief  Initiates a system reset request to reset the MCU.
+  * @retval None
+  */
+void HAL_NVIC_SystemReset(void)
+{
+  /* System Reset */
+  NVIC_SystemReset();
+}
+
+/**
+  * @brief  Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+  *         Counter is in free running mode to generate periodic interrupts.
+  * @param  TicksNumb Specifies the ticks Number of ticks between two interrupts.
+  * @retval status   - 0  Function succeeded.
+  *                  - 1  Function failed.
+  */
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
+{
+   return SysTick_Config(TicksNumb);
+}
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
+ *  @brief   Cortex control functions
+ *
+@verbatim
+  ==============================================================================
+                      ##### Peripheral Control functions #####
+  ==============================================================================
+    [..]
+      This subsection provides a set of functions allowing to control the CORTEX
+      (NVIC, SYSTICK, MPU) functionalities.
+
+
+@endverbatim
+  * @{
+  */
+#if (__MPU_PRESENT == 1)
+/**
+  * @brief  Disables the MPU
+  * @retval None
+  */
+void HAL_MPU_Disable(void)
+{
+  /* Make sure outstanding transfers are done */
+  __DMB();
+
+  /* Disable fault exceptions */
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+
+  /* Disable the MPU and clear the control register*/
+  MPU->CTRL = 0;
+}
+
+/**
+  * @brief  Enables the MPU
+  * @param  MPU_Control Specifies the control mode of the MPU during hard fault,
+  *         NMI, FAULTMASK and privileged access to the default memory
+  *         This parameter can be one of the following values:
+  *            @arg MPU_HFNMI_PRIVDEF_NONE
+  *            @arg MPU_HARDFAULT_NMI
+  *            @arg MPU_PRIVILEGED_DEFAULT
+  *            @arg MPU_HFNMI_PRIVDEF
+  * @retval None
+  */
+void HAL_MPU_Enable(uint32_t MPU_Control)
+{
+  /* Enable the MPU */
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+
+  /* Enable fault exceptions */
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+
+  /* Ensure MPU setting take effects */
+  __DSB();
+  __ISB();
+}
+/**
+  * @brief  Initializes and configures the Region and the memory to be protected.
+  * @param  MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
+  *                  the initialization and configuration information.
+  * @retval None
+  */
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
+{
+  /* Check the parameters */
+  assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
+  assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
+
+  /* Set the Region number */
+  MPU->RNR = MPU_Init->Number;
+
+  if ((MPU_Init->Enable) != 0UL)
+  {
+    /* Check the parameters */
+    assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
+    assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
+    assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
+    assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
+    assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
+    assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
+    assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
+    assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
+
+    MPU->RBAR = MPU_Init->BaseAddress;
+    MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
+                ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
+                ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
+                ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
+                ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
+                ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
+                ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
+                ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
+                ((uint32_t)MPU_Init->Enable                  << MPU_RASR_ENABLE_Pos);
+  }
+  else
+  {
+    MPU->RBAR = 0x00;
+    MPU->RASR = 0x00;
+  }
+}
+#endif /* __MPU_PRESENT */
+
+/**
+  * @brief  Gets the priority grouping field from the NVIC Interrupt Controller.
+  * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
+  */
+uint32_t HAL_NVIC_GetPriorityGrouping(void)
+{
+  /* Get the PRIGROUP[10:8] field value */
+  return NVIC_GetPriorityGrouping();
+}
+
+/**
+  * @brief  Gets the priority of an interrupt.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
+  * @param   PriorityGroup the priority grouping bits length.
+  *         This parameter can be one of the following values:
+  *           @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
+  *                                      4 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
+  *                                      3 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
+  *                                      2 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
+  *                                      1 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
+  *                                      0 bits for subpriority
+  * @param  pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
+  * @param  pSubPriority Pointer on the Subpriority value (starting from 0).
+  * @retval None
+  */
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+ /* Get priority for Cortex-M system or device specific interrupts */
+  NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
+}
+
+/**
+  * @brief  Sets Pending bit of an external interrupt.
+  * @param  IRQn External interrupt number
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+  /* Set interrupt pending */
+  NVIC_SetPendingIRQ(IRQn);
+}
+
+/**
+  * @brief  Gets Pending Interrupt (reads the pending register in the NVIC
+  *         and returns the pending bit for the specified interrupt).
+  * @param  IRQn External interrupt number.
+  *          This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
+  * @retval status  - 0  Interrupt status is not pending.
+  *                 - 1  Interrupt status is pending.
+  */
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+  /* Return 1 if pending else 0 */
+  return NVIC_GetPendingIRQ(IRQn);
+}
+
+/**
+  * @brief  Clears the pending bit of an external interrupt.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+  /* Clear pending interrupt */
+  NVIC_ClearPendingIRQ(IRQn);
+}
+
+/**
+  * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
+  * @param IRQn External interrupt number
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
+  * @retval status  - 0  Interrupt status is not pending.
+  *                 - 1  Interrupt status is pending.
+  */
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+  /* Return 1 if active else 0 */
+  return NVIC_GetActive(IRQn);
+}
+
+/**
+  * @brief  Configures the SysTick clock source.
+  * @param  CLKSource specifies the SysTick clock source.
+  *         This parameter can be one of the following values:
+  *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
+  *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
+  * @retval None
+  */
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
+  if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
+  {
+    SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
+  }
+  else
+  {
+    SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
+  }
+}
+
+/**
+  * @brief  This function handles SYSTICK interrupt request.
+  * @retval None
+  */
+void HAL_SYSTICK_IRQHandler(void)
+{
+  HAL_SYSTICK_Callback();
+}
+
+/**
+  * @brief  SYSTICK callback.
+  * @retval None
+  */
+__weak void HAL_SYSTICK_Callback(void)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SYSTICK_Callback could be implemented in the user file
+   */
+}
+
+#if defined(DUAL_CORE)
+
+/**
+  * @brief  Returns the current CPU ID.
+  * @retval CPU identifier
+  */
+uint32_t HAL_GetCurrentCPUID(void)
+{
+  if (((SCB->CPUID & 0x000000F0U) >> 4 )== 0x7U)
+  {
+    return  CM7_CPUID;
+  }
+  else
+  {
+    return CM4_CPUID;
+  }
+}
+
+#else
+
+/**
+* @brief  Returns the current CPU ID.
+* @retval CPU identifier
+*/
+uint32_t HAL_GetCurrentCPUID(void)
+{
+  return  CM7_CPUID;
+}
+
+#endif /*DUAL_CORE*/
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c
new file mode 100644
index 00000000..e2bbea73
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c
@@ -0,0 +1,2055 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_dma.c
+  * @author  MCD Application Team
+  * @brief   DMA HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Direct Memory Access (DMA) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral State and errors functions
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+   (#) Enable and configure the peripheral to be connected to the DMA Stream
+       (except for internal SRAM/FLASH memories: no initialization is
+       necessary) please refer to Reference manual for connection between peripherals
+       and DMA requests .
+
+   (#) For a given Stream, program the required configuration through the following parameters:
+       Transfer Direction, Source and Destination data formats,
+       Circular, Normal or peripheral flow control mode, Stream Priority level,
+       Source and Destination Increment mode, FIFO mode and its Threshold (if needed),
+       Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.
+
+     *** Polling mode IO operation ***
+     =================================
+    [..]
+          (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
+              address and destination address and the Length of data to be transferred
+          (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
+              case a fixed Timeout can be configured by User depending from his application.
+
+     *** Interrupt mode IO operation ***
+     ===================================
+    [..]
+          (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
+          (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
+          (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
+              Source address and destination address and the Length of data to be transferred. In this
+              case the DMA interrupt is configured
+          (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
+          (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
+              add his own function by customization of function pointer XferCpltCallback and
+              XferErrorCallback (i.e a member of DMA handle structure).
+    [..]
+     (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
+         detection.
+
+     (#) Use HAL_DMA_Abort() function to abort the current transfer
+
+     -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.
+
+     -@-   The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is
+           possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set
+           Half-Word data size for the peripheral to access its data register and set Word data size
+           for the Memory to gain in access time. Each two half words will be packed and written in
+           a single access to a Word in the Memory).
+
+     -@-   When FIFO is disabled, it is not allowed to configure different Data Sizes for Source
+           and Destination. In this case the Peripheral Data Size will be applied to both Source
+           and Destination.
+
+     *** DMA HAL driver macros list ***
+     =============================================
+     [..]
+       Below the list of most used macros in DMA HAL driver.
+
+      (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.
+      (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.
+      (+) __HAL_DMA_GET_FS: Return the current DMA Stream FIFO filled level.
+      (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Stream interrupts.
+      (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts.
+      (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not.
+
+     [..]
+      (@) You can refer to the DMA HAL driver header file for more useful macros.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup DMA DMA
+  * @brief DMA HAL module driver
+  * @{
+  */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+typedef struct
+{
+  __IO uint32_t ISR;   /*!< DMA interrupt status register */
+  __IO uint32_t Reserved0;
+  __IO uint32_t IFCR;  /*!< DMA interrupt flag clear register */
+} DMA_Base_Registers;
+
+typedef struct
+{
+  __IO uint32_t ISR;   /*!< BDMA interrupt status register */
+  __IO uint32_t IFCR;  /*!< BDMA interrupt flag clear register */
+} BDMA_Base_Registers;
+
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup DMA_Private_Constants
+ * @{
+ */
+#define HAL_TIMEOUT_DMA_ABORT         (5U)  /* 5 ms */
+
+#define BDMA_PERIPH_TO_MEMORY         (0x00000000U)                /*!< Peripheral to memory direction */
+#define BDMA_MEMORY_TO_PERIPH         ((uint32_t)BDMA_CCR_DIR)     /*!< Memory to peripheral direction */
+#define BDMA_MEMORY_TO_MEMORY         ((uint32_t)BDMA_CCR_MEM2MEM) /*!< Memory to memory direction     */
+
+/* DMA to BDMA conversion */
+#define DMA_TO_BDMA_DIRECTION(__DMA_DIRECTION__) (((__DMA_DIRECTION__) == DMA_MEMORY_TO_PERIPH)? BDMA_MEMORY_TO_PERIPH: \
+                                                  ((__DMA_DIRECTION__) == DMA_MEMORY_TO_MEMORY)? BDMA_MEMORY_TO_MEMORY: \
+                                                  BDMA_PERIPH_TO_MEMORY)
+
+#define DMA_TO_BDMA_PERIPHERAL_INC(__DMA_PERIPHERAL_INC__) ((__DMA_PERIPHERAL_INC__) >> 3U)
+#define DMA_TO_BDMA_MEMORY_INC(__DMA_MEMORY_INC__) ((__DMA_MEMORY_INC__) >> 3U)
+
+#define DMA_TO_BDMA_PDATA_SIZE(__DMA_PDATA_SIZE__) ((__DMA_PDATA_SIZE__) >> 3U)
+#define DMA_TO_BDMA_MDATA_SIZE(__DMA_MDATA_SIZE__) ((__DMA_MDATA_SIZE__) >> 3U)
+
+#define DMA_TO_BDMA_MODE(__DMA_MODE__) ((__DMA_MODE__) >> 3U)
+
+#define DMA_TO_BDMA_PRIORITY(__DMA_PRIORITY__) ((__DMA_PRIORITY__) >> 4U)
+
+#if defined(UART9)
+#define IS_DMA_UART_USART_REQUEST(__REQUEST__) ((((__REQUEST__) >= DMA_REQUEST_USART1_RX)  &&  ((__REQUEST__) <= DMA_REQUEST_USART3_TX)) || \
+                                                 (((__REQUEST__) >= DMA_REQUEST_UART4_RX)  &&  ((__REQUEST__) <= DMA_REQUEST_UART5_TX )) || \
+                                                 (((__REQUEST__) >= DMA_REQUEST_USART6_RX) &&  ((__REQUEST__) <= DMA_REQUEST_USART6_TX)) || \
+                                                 (((__REQUEST__) >= DMA_REQUEST_UART7_RX)  &&  ((__REQUEST__) <= DMA_REQUEST_UART8_TX )) || \
+                                                 (((__REQUEST__) >= DMA_REQUEST_UART9_RX)  &&  ((__REQUEST__) <= DMA_REQUEST_USART10_TX )))
+#else
+#define IS_DMA_UART_USART_REQUEST(__REQUEST__) ((((__REQUEST__) >= DMA_REQUEST_USART1_RX)  &&  ((__REQUEST__) <= DMA_REQUEST_USART3_TX)) || \
+                                                 (((__REQUEST__) >= DMA_REQUEST_UART4_RX)  &&  ((__REQUEST__) <= DMA_REQUEST_UART5_TX )) || \
+                                                 (((__REQUEST__) >= DMA_REQUEST_USART6_RX) &&  ((__REQUEST__) <= DMA_REQUEST_USART6_TX)) || \
+                                                 (((__REQUEST__) >= DMA_REQUEST_UART7_RX)  &&  ((__REQUEST__) <= DMA_REQUEST_UART8_TX )))
+
+#endif
+/**
+  * @}
+  */
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup DMA_Private_Functions
+  * @{
+  */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma);
+static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma);
+static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma);
+
+/**
+  * @}
+  */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @addtogroup DMA_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group1
+  *
+@verbatim
+ ===============================================================================
+             ##### Initialization and de-initialization functions  #####
+ ===============================================================================
+    [..]
+    This section provides functions allowing to initialize the DMA Stream source
+    and destination incrementation and data sizes, transfer direction,
+    circular/normal mode selection, memory-to-memory mode selection and Stream priority value.
+    [..]
+    The HAL_DMA_Init() function follows the DMA configuration procedures as described in
+    reference manual.
+    The HAL_DMA_DeInit function allows to deinitialize the DMA stream.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the DMA according to the specified
+  *         parameters in the DMA_InitTypeDef and create the associated handle.
+  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
+{
+  uint32_t registerValue;
+  uint32_t tickstart = HAL_GetTick();
+  DMA_Base_Registers *regs_dma;
+  BDMA_Base_Registers *regs_bdma;
+
+  /* Check the DMA peripheral handle */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+  assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
+  assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
+  assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
+  assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
+  assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
+  assert_param(IS_DMA_MODE(hdma->Init.Mode));
+  assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
+
+  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+  {
+    assert_param(IS_DMA_REQUEST(hdma->Init.Request));
+    assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode));
+    /* Check the memory burst, peripheral burst and FIFO threshold parameters only
+       when FIFO mode is enabled */
+    if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE)
+    {
+      assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold));
+      assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
+      assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
+    }
+
+    /* Allocate lock resource */
+    __HAL_UNLOCK(hdma);
+
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+
+    /* Disable the peripheral */
+    __HAL_DMA_DISABLE(hdma);
+
+    /* Check if the DMA Stream is effectively disabled */
+    while((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U)
+    {
+      /* Check for the Timeout */
+      if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
+      {
+        /* Update error code */
+        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+
+        /* Change the DMA state */
+        hdma->State = HAL_DMA_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+    }
+
+    /* Get the CR register value */
+    registerValue = ((DMA_Stream_TypeDef   *)hdma->Instance)->CR;
+
+    /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
+    registerValue &= ((uint32_t)~(DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
+                        DMA_SxCR_PL    | DMA_SxCR_MSIZE  | DMA_SxCR_PSIZE  | \
+                        DMA_SxCR_MINC  | DMA_SxCR_PINC   | DMA_SxCR_CIRC   | \
+                        DMA_SxCR_DIR   | DMA_SxCR_CT     | DMA_SxCR_DBM));
+
+    /* Prepare the DMA Stream configuration */
+    registerValue |=  hdma->Init.Direction           |
+            hdma->Init.PeriphInc           | hdma->Init.MemInc           |
+            hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
+            hdma->Init.Mode                | hdma->Init.Priority;
+
+    /* the Memory burst and peripheral burst are not used when the FIFO is disabled */
+    if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
+    {
+      /* Get memory burst and peripheral burst */
+      registerValue |=  hdma->Init.MemBurst | hdma->Init.PeriphBurst;
+    }
+
+    /* Work around for Errata 2.22: UART/USART- DMA transfer lock: DMA stream could be
+                                    lock when transfering data to/from USART/UART */
+#if (STM32H7_DEV_ID == 0x450UL)
+    if((DBGMCU->IDCODE & 0xFFFF0000U) >= 0x20000000U)
+    {
+#endif /* STM32H7_DEV_ID == 0x450UL */
+      if(IS_DMA_UART_USART_REQUEST(hdma->Init.Request) != 0U)
+      {
+        registerValue |= DMA_SxCR_TRBUFF;
+      }
+#if (STM32H7_DEV_ID == 0x450UL)
+    }
+#endif /* STM32H7_DEV_ID == 0x450UL */
+
+    /* Write to DMA Stream CR register */
+    ((DMA_Stream_TypeDef   *)hdma->Instance)->CR = registerValue;
+
+    /* Get the FCR register value */
+    registerValue = ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR;
+
+    /* Clear Direct mode and FIFO threshold bits */
+    registerValue &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
+
+    /* Prepare the DMA Stream FIFO configuration */
+    registerValue |= hdma->Init.FIFOMode;
+
+    /* the FIFO threshold is not used when the FIFO mode is disabled */
+    if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
+    {
+      /* Get the FIFO threshold */
+      registerValue |= hdma->Init.FIFOThreshold;
+
+      /* Check compatibility between FIFO threshold level and size of the memory burst */
+      /* for INCR4, INCR8, INCR16 */
+      if(hdma->Init.MemBurst != DMA_MBURST_SINGLE)
+      {
+        if (DMA_CheckFifoParam(hdma) != HAL_OK)
+        {
+          /* Update error code */
+          hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
+
+          /* Change the DMA state */
+          hdma->State = HAL_DMA_STATE_READY;
+
+          return HAL_ERROR;
+        }
+      }
+    }
+
+    /* Write to DMA Stream FCR */
+    ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR = registerValue;
+
+    /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
+       DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
+    regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
+
+    /* Clear all interrupt flags */
+    regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
+  }
+  else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */
+  {
+    if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U)
+    {
+      /* Check the request parameter */
+      assert_param(IS_BDMA_REQUEST(hdma->Init.Request));
+    }
+
+    /* Allocate lock resource */
+    __HAL_UNLOCK(hdma);
+
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+
+    /* Get the CR register value */
+    registerValue = ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR;
+
+    /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, MEM2MEM, DBM and CT bits */
+    registerValue &= ((uint32_t)~(BDMA_CCR_PL    | BDMA_CCR_MSIZE   | BDMA_CCR_PSIZE  | \
+                                  BDMA_CCR_MINC  | BDMA_CCR_PINC    | BDMA_CCR_CIRC   | \
+                                  BDMA_CCR_DIR   | BDMA_CCR_MEM2MEM | BDMA_CCR_DBM    | \
+                                  BDMA_CCR_CT));
+
+    /* Prepare the DMA Channel configuration */
+    registerValue |=  DMA_TO_BDMA_DIRECTION(hdma->Init.Direction)            |
+                      DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc)       |
+                      DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc)              |
+                      DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) |
+                      DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment)    |
+                      DMA_TO_BDMA_MODE(hdma->Init.Mode)                      |
+                      DMA_TO_BDMA_PRIORITY(hdma->Init.Priority);
+
+    /* Write to DMA Channel CR register */
+    ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR = registerValue;
+
+    /* calculation of the channel index */
+    hdma->StreamIndex = (((uint32_t)((uint32_t*)hdma->Instance) - (uint32_t)BDMA_Channel0) / ((uint32_t)BDMA_Channel1 - (uint32_t)BDMA_Channel0)) << 2U;
+
+    /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
+    DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
+    regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
+
+    /* Clear all interrupt flags */
+    regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
+  }
+  else
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
+    hdma->State     = HAL_DMA_STATE_ERROR;
+
+    return HAL_ERROR;
+  }
+
+  if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+  {
+    /* Initialize parameters for DMAMUX channel :
+    DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask
+    */
+    DMA_CalcDMAMUXChannelBaseAndMask(hdma);
+
+    if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
+    {
+      /* if memory to memory force the request to 0*/
+      hdma->Init.Request = DMA_REQUEST_MEM2MEM;
+    }
+
+    /* Set peripheral request  to DMAMUX channel */
+    hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);
+
+    /* Clear the DMAMUX synchro overrun flag */
+    hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+    /* Initialize parameters for DMAMUX request generator :
+    if the DMA request is DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR7
+    */
+    if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7))
+    {
+      /* Initialize parameters for DMAMUX request generator :
+      DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */
+      DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
+
+      /* Reset the DMAMUX request generator register */
+      hdma->DMAmuxRequestGen->RGCR = 0U;
+
+      /* Clear the DMAMUX request generator overrun flag */
+      hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+    }
+    else
+    {
+      hdma->DMAmuxRequestGen = 0U;
+      hdma->DMAmuxRequestGenStatus = 0U;
+      hdma->DMAmuxRequestGenStatusMask = 0U;
+    }
+  }
+
+  /* Initialize the error code */
+  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+  /* Initialize the DMA state */
+  hdma->State = HAL_DMA_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the DMA peripheral
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
+{
+  DMA_Base_Registers *regs_dma;
+  BDMA_Base_Registers *regs_bdma;
+
+  /* Check the DMA peripheral handle */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Disable the selected DMA Streamx */
+  __HAL_DMA_DISABLE(hdma);
+
+  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+  {
+    /* Reset DMA Streamx control register */
+    ((DMA_Stream_TypeDef   *)hdma->Instance)->CR   = 0U;
+
+    /* Reset DMA Streamx number of data to transfer register */
+    ((DMA_Stream_TypeDef   *)hdma->Instance)->NDTR = 0U;
+
+    /* Reset DMA Streamx peripheral address register */
+    ((DMA_Stream_TypeDef   *)hdma->Instance)->PAR  = 0U;
+
+    /* Reset DMA Streamx memory 0 address register */
+    ((DMA_Stream_TypeDef   *)hdma->Instance)->M0AR = 0U;
+
+    /* Reset DMA Streamx memory 1 address register */
+    ((DMA_Stream_TypeDef   *)hdma->Instance)->M1AR = 0U;
+
+    /* Reset DMA Streamx FIFO control register */
+    ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR  = (uint32_t)0x00000021U;
+
+    /* Get DMA steam Base Address */
+    regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
+
+    /* Clear all interrupt flags at correct offset within the register */
+    regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
+  }
+  else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */
+  {
+    /* Reset DMA Channel control register */
+    ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR  = 0U;
+
+    /* Reset DMA Channel Number of Data to Transfer register */
+    ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = 0U;
+
+    /* Reset DMA Channel peripheral address register */
+    ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR  = 0U;
+
+    /* Reset DMA Channel memory 0 address register */
+    ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = 0U;
+
+    /* Reset DMA Channel memory 1 address register */
+    ((BDMA_Channel_TypeDef *)hdma->Instance)->CM1AR = 0U;
+
+    /* Get DMA steam Base Address */
+    regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
+
+    /* Clear all interrupt flags at correct offset within the register */
+    regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
+  }
+  else
+  {
+    /* Return error status */
+    return HAL_ERROR;
+  }
+
+  if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+  {
+    /* Initialize parameters for DMAMUX channel :
+    DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */
+    DMA_CalcDMAMUXChannelBaseAndMask(hdma);
+
+    if(hdma->DMAmuxChannel != 0U)
+    {
+      /* Resett he DMAMUX channel that corresponds to the DMA stream */
+      hdma->DMAmuxChannel->CCR = 0U;
+
+      /* Clear the DMAMUX synchro overrun flag */
+      hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+    }
+
+    if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7))
+    {
+      /* Initialize parameters for DMAMUX request generator :
+      DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */
+      DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
+
+      /* Reset the DMAMUX request generator register */
+      hdma->DMAmuxRequestGen->RGCR = 0U;
+
+      /* Clear the DMAMUX request generator overrun flag */
+      hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+    }
+
+    hdma->DMAmuxRequestGen = 0U;
+    hdma->DMAmuxRequestGenStatus = 0U;
+    hdma->DMAmuxRequestGenStatusMask = 0U;
+  }
+
+
+  /* Clean callbacks */
+  hdma->XferCpltCallback       = NULL;
+  hdma->XferHalfCpltCallback   = NULL;
+  hdma->XferM1CpltCallback     = NULL;
+  hdma->XferM1HalfCpltCallback = NULL;
+  hdma->XferErrorCallback      = NULL;
+  hdma->XferAbortCallback      = NULL;
+
+  /* Initialize the error code */
+  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+  /* Initialize the DMA state */
+  hdma->State = HAL_DMA_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdma);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group2
+  *
+@verbatim
+ ===============================================================================
+                      #####  IO operation functions  #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure the source, destination address and data length and Start DMA transfer
+      (+) Configure the source, destination address and data length and
+          Start DMA transfer with interrupt
+      (+) Register and Unregister DMA callbacks
+      (+) Abort DMA transfer
+      (+) Poll for transfer complete
+      (+) Handle DMA interrupt request
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the DMA Transfer.
+  * @param  hdma      : pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @param  SrcAddress: The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  DataLength: The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+  /* Check the DMA peripheral handle */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hdma);
+
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+
+    /* Initialize the error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+    /* Disable the peripheral */
+    __HAL_DMA_DISABLE(hdma);
+
+    /* Configure the source, destination address and the data length */
+    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+    /* Enable the Peripheral */
+    __HAL_DMA_ENABLE(hdma);
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hdma);
+
+    /* Set the error code to busy */
+    hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  return status;
+}
+
+/**
+  * @brief  Start the DMA Transfer with interrupt enabled.
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @param  SrcAddress: The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  DataLength: The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+  /* Check the DMA peripheral handle */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hdma);
+
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+
+    /* Initialize the error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+    /* Disable the peripheral */
+    __HAL_DMA_DISABLE(hdma);
+
+    /* Configure the source, destination address and the data length */
+    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+    {
+      /* Enable Common interrupts*/
+      MODIFY_REG(((DMA_Stream_TypeDef   *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME));
+
+      if(hdma->XferHalfCpltCallback != NULL)
+      {
+        /* Enable Half Transfer IT if corresponding Callback is set */
+        ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  |= DMA_IT_HT;
+      }
+    }
+    else /* BDMA channel */
+    {
+      /* Enable Common interrupts */
+      MODIFY_REG(((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR, (BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE), (BDMA_CCR_TCIE | BDMA_CCR_TEIE));
+
+      if(hdma->XferHalfCpltCallback != NULL)
+      {
+        /*Enable Half Transfer IT if corresponding Callback is set */
+        ((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR  |= BDMA_CCR_HTIE;
+      }
+    }
+
+    if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+    {
+      /* Check if DMAMUX Synchronization is enabled */
+      if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
+      {
+        /* Enable DMAMUX sync overrun IT*/
+        hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
+      }
+
+      if(hdma->DMAmuxRequestGen != 0U)
+      {
+        /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
+        /* enable the request gen overrun IT */
+        hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
+      }
+    }
+
+    /* Enable the Peripheral */
+    __HAL_DMA_ENABLE(hdma);
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hdma);
+
+    /* Set the error code to busy */
+    hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Aborts the DMA Transfer.
+  * @param  hdma  : pointer to a DMA_HandleTypeDef structure that contains
+  *                 the configuration information for the specified DMA Stream.
+  *
+  * @note  After disabling a DMA Stream, a check for wait until the DMA Stream is
+  *        effectively disabled is added. If a Stream is disabled
+  *        while a data transfer is ongoing, the current data will be transferred
+  *        and the Stream will be effectively disabled only after the transfer of
+  *        this single data is finished.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
+{
+  /* calculate DMA base and stream number */
+  DMA_Base_Registers *regs_dma;
+  BDMA_Base_Registers *regs_bdma;
+  const __IO uint32_t *enableRegister;
+
+  uint32_t tickstart = HAL_GetTick();
+
+ /* Check the DMA peripheral handle */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the DMA peripheral state */
+  if(hdma->State != HAL_DMA_STATE_BUSY)
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Disable all the transfer interrupts */
+    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+    {
+       /* Disable DMA All Interrupts  */
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT);
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR &= ~(DMA_IT_FE);
+
+      enableRegister = (__IO uint32_t *)(&(((DMA_Stream_TypeDef   *)hdma->Instance)->CR));
+    }
+    else /* BDMA channel */
+    {
+      /* Disable DMA All Interrupts */
+      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR  &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE);
+
+      enableRegister = (__IO uint32_t *)(&(((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR));
+    }
+
+    if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+    {
+      /* disable the DMAMUX sync overrun IT */
+      hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
+    }
+
+    /* Disable the stream */
+    __HAL_DMA_DISABLE(hdma);
+
+    /* Check if the DMA Stream is effectively disabled */
+    while(((*enableRegister) & DMA_SxCR_EN) != 0U)
+    {
+      /* Check for the Timeout */
+      if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
+      {
+        /* Update error code */
+        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdma);
+
+        /* Change the DMA state */
+        hdma->State = HAL_DMA_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+    }
+
+    /* Clear all interrupt flags at correct offset within the register */
+    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+    {
+      regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+      regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
+    }
+    else /* BDMA channel */
+    {
+      regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
+      regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
+    }
+
+    if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+    {
+      /* Clear the DMAMUX synchro overrun flag */
+      hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+      if(hdma->DMAmuxRequestGen != 0U)
+      {
+        /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT */
+        /* disable the request gen overrun IT */
+        hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
+
+        /* Clear the DMAMUX request generator overrun flag */
+        hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+      }
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+
+    /* Change the DMA state */
+    hdma->State = HAL_DMA_STATE_READY;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Aborts the DMA Transfer in Interrupt mode.
+  * @param  hdma  : pointer to a DMA_HandleTypeDef structure that contains
+  *                 the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
+{
+  BDMA_Base_Registers *regs_bdma;
+
+  /* Check the DMA peripheral handle */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if(hdma->State != HAL_DMA_STATE_BUSY)
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+    return HAL_ERROR;
+  }
+  else
+  {
+    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+    {
+      /* Set Abort State  */
+      hdma->State = HAL_DMA_STATE_ABORT;
+
+      /* Disable the stream */
+      __HAL_DMA_DISABLE(hdma);
+    }
+    else /* BDMA channel */
+    {
+      /* Disable DMA All Interrupts  */
+      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR  &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE);
+
+      /* Disable the channel */
+      __HAL_DMA_DISABLE(hdma);
+
+      if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+      {
+        /* disable the DMAMUX sync overrun IT */
+        hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
+
+        /* Clear all flags */
+        regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
+        regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
+
+        /* Clear the DMAMUX synchro overrun flag */
+        hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+        if(hdma->DMAmuxRequestGen != 0U)
+        {
+          /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
+          /* disable the request gen overrun IT */
+          hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
+
+          /* Clear the DMAMUX request generator overrun flag */
+          hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+        }
+      }
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma);
+
+      /* Change the DMA state */
+      hdma->State = HAL_DMA_STATE_READY;
+
+      /* Call User Abort callback */
+      if(hdma->XferAbortCallback != NULL)
+      {
+        hdma->XferAbortCallback(hdma);
+      }
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Polling for transfer complete.
+  * @param  hdma:          pointer to a DMA_HandleTypeDef structure that contains
+  *                        the configuration information for the specified DMA Stream.
+  * @param  CompleteLevel: Specifies the DMA level complete.
+  * @note   The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead.
+  *         This model could be used for debug purpose.
+  * @note   The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode).
+  * @param  Timeout:       Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t cpltlevel_mask;
+  uint32_t tickstart = HAL_GetTick();
+
+  /* IT status register */
+  __IO uint32_t *isr_reg;
+  /* IT clear flag register */
+  __IO uint32_t *ifcr_reg;
+
+  /* Check the DMA peripheral handle */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if(HAL_DMA_STATE_BUSY != hdma->State)
+  {
+    /* No transfer ongoing */
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+    __HAL_UNLOCK(hdma);
+
+    return HAL_ERROR;
+  }
+
+  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+  {
+    /* Polling mode not supported in circular mode and double buffering mode */
+    if ((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CIRC) != 0U)
+    {
+      hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+      return HAL_ERROR;
+    }
+
+    /* Get the level transfer complete flag */
+    if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
+    {
+      /* Transfer Complete flag */
+      cpltlevel_mask = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU);
+    }
+    else
+    {
+      /* Half Transfer Complete flag */
+      cpltlevel_mask = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU);
+    }
+
+    isr_reg  = &(((DMA_Base_Registers *)hdma->StreamBaseAddress)->ISR);
+    ifcr_reg = &(((DMA_Base_Registers *)hdma->StreamBaseAddress)->IFCR);
+  }
+  else /* BDMA channel */
+  {
+    /* Polling mode not supported in circular mode */
+    if ((((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR & BDMA_CCR_CIRC) != 0U)
+    {
+      hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+      return HAL_ERROR;
+    }
+
+    /* Get the level transfer complete flag */
+    if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
+    {
+      /* Transfer Complete flag */
+      cpltlevel_mask = BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU);
+    }
+    else
+    {
+      /* Half Transfer Complete flag */
+      cpltlevel_mask = BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU);
+    }
+
+    isr_reg  = &(((BDMA_Base_Registers *)hdma->StreamBaseAddress)->ISR);
+    ifcr_reg = &(((BDMA_Base_Registers *)hdma->StreamBaseAddress)->IFCR);
+  }
+
+  while(((*isr_reg) & cpltlevel_mask) == 0U)
+  {
+    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+    {
+      if(((*isr_reg) & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
+      {
+        /* Update error code */
+        hdma->ErrorCode |= HAL_DMA_ERROR_FE;
+
+        /* Clear the FIFO error flag */
+        (*ifcr_reg) = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU);
+      }
+
+      if(((*isr_reg) & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
+      {
+        /* Update error code */
+        hdma->ErrorCode |= HAL_DMA_ERROR_DME;
+
+        /* Clear the Direct Mode error flag */
+        (*ifcr_reg) = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU);
+      }
+
+      if(((*isr_reg) & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
+      {
+        /* Update error code */
+        hdma->ErrorCode |= HAL_DMA_ERROR_TE;
+
+        /* Clear the transfer error flag */
+        (*ifcr_reg) = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU);
+
+        /* Change the DMA state */
+        hdma->State = HAL_DMA_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdma);
+
+        return HAL_ERROR;
+      }
+    }
+    else /* BDMA channel */
+    {
+      if(((*isr_reg) & (BDMA_FLAG_TE0 << (hdma->StreamIndex & 0x1FU))) != 0U)
+      {
+        /* When a DMA transfer error occurs */
+        /* A hardware clear of its EN bits is performed */
+        /* Clear all flags */
+        (*isr_reg) = ((BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU));
+
+        /* Update error code */
+        hdma->ErrorCode = HAL_DMA_ERROR_TE;
+
+        /* Change the DMA state */
+        hdma->State = HAL_DMA_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdma);
+
+        return HAL_ERROR;
+      }
+    }
+
+    /* Check for the Timeout (Not applicable in circular mode)*/
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
+      {
+        /* Update error code */
+        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+
+        /* if timeout then abort the current transfer */
+        /* No need to check return value: as in this case we will return HAL_ERROR with HAL_DMA_ERROR_TIMEOUT error code  */
+        (void) HAL_DMA_Abort(hdma);
+          /*
+            Note that the Abort function will
+              - Clear the transfer error flags
+              - Unlock
+              - Set the State
+          */
+
+        return HAL_ERROR;
+      }
+    }
+
+    if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+    {
+      /* Check for DMAMUX Request generator (if used) overrun status */
+      if(hdma->DMAmuxRequestGen != 0U)
+      {
+        /* if using DMAMUX request generator Check for DMAMUX request generator overrun */
+        if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
+        {
+          /* Clear the DMAMUX request generator overrun flag */
+          hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+
+          /* Update error code */
+          hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
+        }
+      }
+
+      /* Check for DMAMUX Synchronization overrun */
+      if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
+      {
+        /* Clear the DMAMUX synchro overrun flag */
+        hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+        /* Update error code */
+        hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
+      }
+    }
+  }
+
+
+  /* Get the level transfer complete flag */
+  if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
+  {
+    /* Clear the half transfer and transfer complete flags */
+    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+    {
+      (*ifcr_reg) = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << (hdma->StreamIndex & 0x1FU);
+    }
+    else /* BDMA channel */
+    {
+      (*ifcr_reg) = (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU));
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+
+    hdma->State = HAL_DMA_STATE_READY;
+  }
+  else /*CompleteLevel = HAL_DMA_HALF_TRANSFER*/
+  {
+    /* Clear the half transfer and transfer complete flags */
+    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+    {
+      (*ifcr_reg) = (DMA_FLAG_HTIF0_4) << (hdma->StreamIndex & 0x1FU);
+    }
+    else /* BDMA channel */
+    {
+      (*ifcr_reg) = (BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU));
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Handles DMA interrupt request.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Stream.
+  * @retval None
+  */
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
+{
+  uint32_t tmpisr_dma, tmpisr_bdma;
+  uint32_t ccr_reg;
+  __IO uint32_t count = 0U;
+  uint32_t timeout = SystemCoreClock / 9600U;
+
+  /* calculate DMA base and stream number */
+  DMA_Base_Registers  *regs_dma  = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+  BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
+
+  tmpisr_dma  = regs_dma->ISR;
+  tmpisr_bdma = regs_bdma->ISR;
+
+  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U)  /* DMA1 or DMA2 instance */
+  {
+    /* Transfer Error Interrupt management ***************************************/
+    if ((tmpisr_dma & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
+    {
+      if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != 0U)
+      {
+        /* Disable the transfer error interrupt */
+        ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_TE);
+
+        /* Clear the transfer error flag */
+        regs_dma->IFCR = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU);
+
+        /* Update error code */
+        hdma->ErrorCode |= HAL_DMA_ERROR_TE;
+      }
+    }
+    /* FIFO Error Interrupt management ******************************************/
+    if ((tmpisr_dma & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
+    {
+      if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != 0U)
+      {
+        /* Clear the FIFO error flag */
+        regs_dma->IFCR = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU);
+
+        /* Update error code */
+        hdma->ErrorCode |= HAL_DMA_ERROR_FE;
+      }
+    }
+    /* Direct Mode Error Interrupt management ***********************************/
+    if ((tmpisr_dma & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
+    {
+      if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != 0U)
+      {
+        /* Clear the direct mode error flag */
+        regs_dma->IFCR = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU);
+
+        /* Update error code */
+        hdma->ErrorCode |= HAL_DMA_ERROR_DME;
+      }
+    }
+    /* Half Transfer Complete Interrupt management ******************************/
+    if ((tmpisr_dma & (DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
+    {
+      if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U)
+      {
+        /* Clear the half transfer complete flag */
+        regs_dma->IFCR = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU);
+
+        /* Multi_Buffering mode enabled */
+        if(((((DMA_Stream_TypeDef   *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U)
+        {
+          /* Current memory buffer used is Memory 0 */
+          if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U)
+          {
+            if(hdma->XferHalfCpltCallback != NULL)
+            {
+              /* Half transfer callback */
+              hdma->XferHalfCpltCallback(hdma);
+            }
+          }
+          /* Current memory buffer used is Memory 1 */
+          else
+          {
+            if(hdma->XferM1HalfCpltCallback != NULL)
+            {
+              /* Half transfer callback */
+              hdma->XferM1HalfCpltCallback(hdma);
+            }
+          }
+        }
+        else
+        {
+          /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
+          if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U)
+          {
+            /* Disable the half transfer interrupt */
+            ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_HT);
+          }
+
+          if(hdma->XferHalfCpltCallback != NULL)
+          {
+            /* Half transfer callback */
+            hdma->XferHalfCpltCallback(hdma);
+          }
+        }
+      }
+    }
+    /* Transfer Complete Interrupt management ***********************************/
+    if ((tmpisr_dma & (DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
+    {
+      if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U)
+      {
+        /* Clear the transfer complete flag */
+        regs_dma->IFCR = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU);
+
+        if(HAL_DMA_STATE_ABORT == hdma->State)
+        {
+          /* Disable all the transfer interrupts */
+          ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
+          ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR &= ~(DMA_IT_FE);
+
+          if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
+          {
+            ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_HT);
+          }
+
+          /* Clear all interrupt flags at correct offset within the register */
+          regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hdma);
+
+          /* Change the DMA state */
+          hdma->State = HAL_DMA_STATE_READY;
+
+          if(hdma->XferAbortCallback != NULL)
+          {
+            hdma->XferAbortCallback(hdma);
+          }
+          return;
+        }
+
+        if(((((DMA_Stream_TypeDef   *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U)
+        {
+          /* Current memory buffer used is Memory 0 */
+          if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U)
+          {
+            if(hdma->XferM1CpltCallback != NULL)
+            {
+              /* Transfer complete Callback for memory1 */
+              hdma->XferM1CpltCallback(hdma);
+            }
+          }
+          /* Current memory buffer used is Memory 1 */
+          else
+          {
+            if(hdma->XferCpltCallback != NULL)
+            {
+              /* Transfer complete Callback for memory0 */
+              hdma->XferCpltCallback(hdma);
+            }
+          }
+        }
+        /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
+        else
+        {
+          if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U)
+          {
+            /* Disable the transfer complete interrupt */
+            ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_TC);
+
+            /* Process Unlocked */
+            __HAL_UNLOCK(hdma);
+
+            /* Change the DMA state */
+            hdma->State = HAL_DMA_STATE_READY;
+          }
+
+          if(hdma->XferCpltCallback != NULL)
+          {
+            /* Transfer complete callback */
+            hdma->XferCpltCallback(hdma);
+          }
+        }
+      }
+    }
+
+    /* manage error case */
+    if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
+    {
+      if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != 0U)
+      {
+        hdma->State = HAL_DMA_STATE_ABORT;
+
+        /* Disable the stream */
+        __HAL_DMA_DISABLE(hdma);
+
+        do
+        {
+          if (++count > timeout)
+          {
+            break;
+          }
+        }
+        while((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U);
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdma);
+
+        if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U)
+        {
+          /* Change the DMA state to error if DMA disable fails */
+          hdma->State = HAL_DMA_STATE_ERROR;
+        }
+        else
+        {
+          /* Change the DMA state to Ready if DMA disable success */
+          hdma->State = HAL_DMA_STATE_READY;
+        }
+      }
+
+      if(hdma->XferErrorCallback != NULL)
+      {
+        /* Transfer error callback */
+        hdma->XferErrorCallback(hdma);
+      }
+    }
+  }
+  else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U)  /* BDMA instance(s) */
+  {
+    ccr_reg = (((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR);
+
+    /* Half Transfer Complete Interrupt management ******************************/
+    if (((tmpisr_bdma & (BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_HTIE) != 0U))
+    {
+      /* Clear the half transfer complete flag */
+      regs_bdma->IFCR = (BDMA_ISR_HTIF0 << (hdma->StreamIndex & 0x1FU));
+
+      /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */
+      if((ccr_reg & BDMA_CCR_DBM) != 0U)
+      {
+        /* Current memory buffer used is Memory 0 */
+        if((ccr_reg & BDMA_CCR_CT) == 0U)
+        {
+          if(hdma->XferM1HalfCpltCallback != NULL)
+          {
+            /* Half transfer Callback for Memory 1 */
+            hdma->XferM1HalfCpltCallback(hdma);
+          }
+        }
+        /* Current memory buffer used is Memory 1 */
+        else
+        {
+          if(hdma->XferHalfCpltCallback != NULL)
+          {
+            /* Half transfer Callback for Memory 0 */
+            hdma->XferHalfCpltCallback(hdma);
+          }
+        }
+      }
+      else
+      {
+        if((ccr_reg & BDMA_CCR_CIRC) == 0U)
+        {
+          /* Disable the half transfer interrupt */
+          __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
+        }
+
+        /* DMA peripheral state is not updated in Half Transfer */
+        /* but in Transfer Complete case */
+
+       if(hdma->XferHalfCpltCallback != NULL)
+        {
+          /* Half transfer callback */
+          hdma->XferHalfCpltCallback(hdma);
+        }
+      }
+    }
+
+    /* Transfer Complete Interrupt management ***********************************/
+    else if (((tmpisr_bdma & (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TCIE) != 0U))
+    {
+      /* Clear the transfer complete flag */
+      regs_bdma->IFCR = (BDMA_ISR_TCIF0) << (hdma->StreamIndex & 0x1FU);
+
+      /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */
+      if((ccr_reg & BDMA_CCR_DBM) != 0U)
+      {
+        /* Current memory buffer used is Memory 0 */
+        if((ccr_reg & BDMA_CCR_CT) == 0U)
+        {
+          if(hdma->XferM1CpltCallback != NULL)
+          {
+            /* Transfer complete Callback for Memory 1 */
+            hdma->XferM1CpltCallback(hdma);
+          }
+        }
+        /* Current memory buffer used is Memory 1 */
+        else
+        {
+          if(hdma->XferCpltCallback != NULL)
+          {
+            /* Transfer complete Callback for Memory 0 */
+            hdma->XferCpltCallback(hdma);
+          }
+        }
+      }
+      else
+      {
+        if((ccr_reg & BDMA_CCR_CIRC) == 0U)
+        {
+          /* Disable the transfer complete and error interrupt, if the DMA mode is not CIRCULAR */
+          __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hdma);
+
+          /* Change the DMA state */
+          hdma->State = HAL_DMA_STATE_READY;
+        }
+
+        if(hdma->XferCpltCallback != NULL)
+        {
+          /* Transfer complete callback */
+          hdma->XferCpltCallback(hdma);
+        }
+      }
+    }
+    /* Transfer Error Interrupt management **************************************/
+    else if (((tmpisr_bdma & (BDMA_FLAG_TE0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TEIE) != 0U))
+    {
+      /* When a DMA transfer error occurs */
+      /* A hardware clear of its EN bits is performed */
+      /* Disable ALL DMA IT */
+      __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+
+      /* Clear all flags */
+      regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);
+
+      /* Update error code */
+      hdma->ErrorCode = HAL_DMA_ERROR_TE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma);
+
+      /* Change the DMA state */
+      hdma->State = HAL_DMA_STATE_READY;
+
+      if (hdma->XferErrorCallback != NULL)
+      {
+        /* Transfer error callback */
+        hdma->XferErrorCallback(hdma);
+      }
+    }
+    else
+    {
+      /* Nothing To Do */
+    }
+  }
+  else
+  {
+    /* Nothing To Do */
+  }
+}
+
+/**
+  * @brief  Register callbacks
+  * @param  hdma:                 pointer to a DMA_HandleTypeDef structure that contains
+  *                               the configuration information for the specified DMA Stream.
+  * @param  CallbackID:           User Callback identifier
+  *                               a DMA_HandleTypeDef structure as parameter.
+  * @param  pCallback:            pointer to private callback function which has pointer to
+  *                               a DMA_HandleTypeDef structure as parameter.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))
+{
+
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the DMA peripheral handle */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hdma);
+
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    switch (CallbackID)
+    {
+    case  HAL_DMA_XFER_CPLT_CB_ID:
+      hdma->XferCpltCallback = pCallback;
+      break;
+
+    case  HAL_DMA_XFER_HALFCPLT_CB_ID:
+      hdma->XferHalfCpltCallback = pCallback;
+      break;
+
+    case  HAL_DMA_XFER_M1CPLT_CB_ID:
+      hdma->XferM1CpltCallback = pCallback;
+      break;
+
+    case  HAL_DMA_XFER_M1HALFCPLT_CB_ID:
+      hdma->XferM1HalfCpltCallback = pCallback;
+      break;
+
+    case  HAL_DMA_XFER_ERROR_CB_ID:
+      hdma->XferErrorCallback = pCallback;
+      break;
+
+    case  HAL_DMA_XFER_ABORT_CB_ID:
+      hdma->XferAbortCallback = pCallback;
+      break;
+
+    default:
+      break;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdma);
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister callbacks
+  * @param  hdma:                 pointer to a DMA_HandleTypeDef structure that contains
+  *                               the configuration information for the specified DMA Stream.
+  * @param  CallbackID:           User Callback identifier
+  *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the DMA peripheral handle */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hdma);
+
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    switch (CallbackID)
+    {
+    case  HAL_DMA_XFER_CPLT_CB_ID:
+      hdma->XferCpltCallback = NULL;
+      break;
+
+    case  HAL_DMA_XFER_HALFCPLT_CB_ID:
+      hdma->XferHalfCpltCallback = NULL;
+      break;
+
+    case  HAL_DMA_XFER_M1CPLT_CB_ID:
+      hdma->XferM1CpltCallback = NULL;
+      break;
+
+    case  HAL_DMA_XFER_M1HALFCPLT_CB_ID:
+      hdma->XferM1HalfCpltCallback = NULL;
+      break;
+
+    case  HAL_DMA_XFER_ERROR_CB_ID:
+      hdma->XferErrorCallback = NULL;
+      break;
+
+    case  HAL_DMA_XFER_ABORT_CB_ID:
+      hdma->XferAbortCallback = NULL;
+      break;
+
+    case   HAL_DMA_XFER_ALL_CB_ID:
+      hdma->XferCpltCallback = NULL;
+      hdma->XferHalfCpltCallback = NULL;
+      hdma->XferM1CpltCallback = NULL;
+      hdma->XferM1HalfCpltCallback = NULL;
+      hdma->XferErrorCallback = NULL;
+      hdma->XferAbortCallback = NULL;
+      break;
+
+    default:
+      status = HAL_ERROR;
+      break;
+    }
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdma);
+
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group3
+  *
+@verbatim
+ ===============================================================================
+                    ##### State and Errors functions #####
+ ===============================================================================
+    [..]
+    This subsection provides functions allowing to
+      (+) Check the DMA state
+      (+) Get error code
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the DMA state.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Stream.
+  * @retval HAL state
+  */
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
+{
+  return hdma->State;
+}
+
+/**
+  * @brief  Return the DMA error code
+  * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA Stream.
+  * @retval DMA Error Code
+  */
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
+{
+  return hdma->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMA_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Sets the DMA Transfer parameter.
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @param  SrcAddress: The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  DataLength: The length of data to be transferred from source to destination
+  * @retval None
+  */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+  /* calculate DMA base and stream number */
+  DMA_Base_Registers  *regs_dma  = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+  BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
+
+  if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+  {
+    /* Clear the DMAMUX synchro overrun flag */
+    hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+    if(hdma->DMAmuxRequestGen != 0U)
+    {
+      /* Clear the DMAMUX request generator overrun flag */
+      hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+    }
+  }
+
+  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+  {
+    /* Clear all interrupt flags at correct offset within the register */
+    regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
+
+    /* Clear DBM bit */
+    ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= (uint32_t)(~DMA_SxCR_DBM);
+
+    /* Configure DMA Stream data length */
+    ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = DataLength;
+
+    /* Peripheral to Memory */
+    if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+    {
+      /* Configure DMA Stream destination address */
+      ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = DstAddress;
+
+      /* Configure DMA Stream source address */
+      ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = SrcAddress;
+    }
+    /* Memory to Peripheral */
+    else
+    {
+      /* Configure DMA Stream source address */
+      ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = SrcAddress;
+
+      /* Configure DMA Stream destination address */
+      ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = DstAddress;
+    }
+  }
+  else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */
+  {
+    /* Clear all flags */
+    regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);
+
+    /* Configure DMA Channel data length */
+    ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = DataLength;
+
+    /* Peripheral to Memory */
+    if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+    {
+      /* Configure DMA Channel destination address */
+      ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = DstAddress;
+
+      /* Configure DMA Channel source address */
+      ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = SrcAddress;
+    }
+    /* Memory to Peripheral */
+    else
+    {
+      /* Configure DMA Channel source address */
+      ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = SrcAddress;
+
+      /* Configure DMA Channel destination address */
+      ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = DstAddress;
+    }
+  }
+  else
+  {
+    /* Nothing To Do */
+  }
+}
+
+/**
+  * @brief  Returns the DMA Stream base address depending on stream number
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @retval Stream base address
+  */
+static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
+{
+  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+  {
+    uint32_t stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U;
+
+    /* lookup table for necessary bitshift of flags within status registers */
+    static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};
+    hdma->StreamIndex = flagBitshiftOffset[stream_number & 0x7U];
+
+    if (stream_number > 3U)
+    {
+      /* return pointer to HISR and HIFCR */
+      hdma->StreamBaseAddress = (((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)) + 4U);
+    }
+    else
+    {
+      /* return pointer to LISR and LIFCR */
+      hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU));
+    }
+  }
+  else /* BDMA instance(s) */
+  {
+    /* return pointer to ISR and IFCR */
+    hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0xFFU));
+  }
+
+  return hdma->StreamBaseAddress;
+}
+
+/**
+  * @brief  Check compatibility between FIFO threshold level and size of the memory burst
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Memory Data size equal to Byte */
+  if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)
+  {
+    switch (hdma->Init.FIFOThreshold)
+    {
+      case DMA_FIFO_THRESHOLD_1QUARTERFULL:
+      case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
+
+        if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+        {
+          status = HAL_ERROR;
+        }
+        break;
+
+      case DMA_FIFO_THRESHOLD_HALFFULL:
+        if (hdma->Init.MemBurst == DMA_MBURST_INC16)
+        {
+          status = HAL_ERROR;
+        }
+        break;
+
+      case DMA_FIFO_THRESHOLD_FULL:
+        break;
+
+      default:
+        break;
+    }
+  }
+
+  /* Memory Data size equal to Half-Word */
+  else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
+  {
+    switch (hdma->Init.FIFOThreshold)
+    {
+      case DMA_FIFO_THRESHOLD_1QUARTERFULL:
+      case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
+        status = HAL_ERROR;
+        break;
+
+      case DMA_FIFO_THRESHOLD_HALFFULL:
+        if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+        {
+          status = HAL_ERROR;
+        }
+        break;
+
+      case DMA_FIFO_THRESHOLD_FULL:
+        if (hdma->Init.MemBurst == DMA_MBURST_INC16)
+        {
+          status = HAL_ERROR;
+        }
+        break;
+
+      default:
+        break;
+    }
+  }
+
+  /* Memory Data size equal to Word */
+  else
+  {
+    switch (hdma->Init.FIFOThreshold)
+    {
+      case DMA_FIFO_THRESHOLD_1QUARTERFULL:
+      case DMA_FIFO_THRESHOLD_HALFFULL:
+      case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
+        status = HAL_ERROR;
+        break;
+
+      case DMA_FIFO_THRESHOLD_FULL:
+        if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+        {
+          status = HAL_ERROR;
+        }
+    break;
+
+      default:
+        break;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Updates the DMA handle with the DMAMUX  channel and status mask depending on stream number
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)
+{
+  uint32_t stream_number;
+  uint32_t stream_baseaddress = (uint32_t)((uint32_t*)hdma->Instance);
+
+  if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U)
+  {
+    /* BDMA Channels are connected to DMAMUX2 channels */
+    stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 8U) / 20U;
+    hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_Channel0) + (stream_number * 4U)));
+    hdma->DMAmuxChannelStatus = DMAMUX2_ChannelStatus;
+    hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU);
+  }
+  else
+  {
+    /* DMA1/DMA2 Streams are connected to DMAMUX1 channels */
+    stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U;
+
+    if((stream_baseaddress <= ((uint32_t)DMA2_Stream7) ) && \
+       (stream_baseaddress >= ((uint32_t)DMA2_Stream0)))
+    {
+      stream_number += 8U;
+    }
+    hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U)));
+    hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
+    hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU);
+  }
+}
+
+/**
+  * @brief  Updates the DMA handle with the DMAMUX  request generator params
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma)
+{
+  uint32_t request =  hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID;
+
+  if((request >= DMA_REQUEST_GENERATOR0) && (request <= DMA_REQUEST_GENERATOR7))
+  {
+    if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U)
+    {
+      /* BDMA Channels are connected to DMAMUX2 request generator blocks */
+      hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_RequestGenerator0) + ((request - 1U) * 4U)));
+
+      hdma->DMAmuxRequestGenStatus = DMAMUX2_RequestGenStatus;
+    }
+    else
+    {
+      /* DMA1 and DMA2 Streams use DMAMUX1 request generator blocks */
+      hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U)));
+
+      hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
+    }
+
+    hdma->DMAmuxRequestGenStatusMask = 1UL << (request - 1U);
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c
new file mode 100644
index 00000000..6a48d942
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c
@@ -0,0 +1,714 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_dma_ex.c
+  * @author  MCD Application Team
+  * @brief   DMA Extension HAL module driver
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the DMA Extension peripheral:
+  *           + Extended features functions
+  *
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+  The DMA Extension HAL driver can be used as follows:
+   (+) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function
+       for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.
+
+   (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
+   (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
+       Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
+       to respectively enable/disable the request generator.
+
+   (+) To handle the DMAMUX Interrupts, the function  HAL_DMAEx_MUX_IRQHandler should be called from
+       the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler or DMAMUX2_OVR_IRQHandler .
+       As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMA_MUX_IRQHandler should be
+       called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project
+      (exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator)
+
+     -@-  In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.
+     -@-  When Multi (Double) Buffer mode is enabled, the transfer is circular by default.
+     -@-  In Multi (Double) buffer mode, it is possible to update the base address for
+          the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.
+     -@-  Multi (Double) buffer mode is possible with DMA and BDMA instances.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup DMAEx DMAEx
+  * @brief DMA Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private Constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup DMAEx_Private_Functions
+  * @{
+  */
+
+static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+
+/**
+  * @}
+  */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @addtogroup DMAEx_Exported_Functions
+  * @{
+  */
+
+
+/** @addtogroup DMAEx_Exported_Functions_Group1
+  *
+@verbatim
+ ===============================================================================
+                #####  Extended features functions  #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure the source, destination address and data length and
+          Start MultiBuffer DMA transfer
+      (+) Configure the source, destination address and data length and
+          Start MultiBuffer DMA transfer with interrupt
+      (+) Change on the fly the memory0 or memory1 address.
+      (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
+      (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
+      (+) Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
+          to respectively enable/disable the request generator.
+      (+) Handle DMAMUX interrupts using HAL_DMAEx_MUX_IRQHandler : should be called from
+          the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler or DMAMUX2_OVR_IRQHandler
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Starts the multi_buffer DMA Transfer.
+  * @param  hdma      : pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @param  SrcAddress: The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer
+  * @param  DataLength: The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  __IO uint32_t *ifcRegister_Base; /* DMA Stream Interrupt Clear register */
+
+  /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+
+  /* Memory-to-memory transfer not supported in double buffering mode */
+  if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Process Locked */
+    __HAL_LOCK(hdma);
+
+    if(HAL_DMA_STATE_READY == hdma->State)
+    {
+      /* Change DMA peripheral state */
+      hdma->State = HAL_DMA_STATE_BUSY;
+
+      /* Initialize the error code */
+      hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+      if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+      {
+        /* Enable the Double buffer mode */
+        ((DMA_Stream_TypeDef   *)hdma->Instance)->CR |= DMA_SxCR_DBM;
+
+        /* Configure DMA Stream destination address */
+        ((DMA_Stream_TypeDef   *)hdma->Instance)->M1AR = SecondMemAddress;
+
+        /* Calculate the interrupt clear flag register (IFCR) base address  */
+        ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 8U));
+
+        /* Clear all flags */
+        *ifcRegister_Base = 0x3FUL << (hdma->StreamIndex & 0x1FU);
+      }
+      else /* BDMA instance(s) */
+      {
+        /* Enable the Double buffer mode */
+        ((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR |= (BDMA_CCR_DBM | BDMA_CCR_CIRC);
+
+        /* Configure DMA Stream destination address */
+        ((BDMA_Channel_TypeDef   *)hdma->Instance)->CM1AR = SecondMemAddress;
+
+        /* Calculate the interrupt clear flag register (IFCR) base address  */
+        ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 4U));
+
+        /* Clear all flags */
+        *ifcRegister_Base = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);
+      }
+
+      if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+      {
+        /* Configure the source, destination address and the data length */
+        DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+        /* Clear the DMAMUX synchro overrun flag */
+        hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+        if(hdma->DMAmuxRequestGen != 0U)
+        {
+          /* Clear the DMAMUX request generator overrun flag */
+          hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+        }
+      }
+
+      /* Enable the peripheral */
+      __HAL_DMA_ENABLE(hdma);
+    }
+    else
+    {
+      /* Set the error code to busy */
+      hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+      /* Return error status */
+      status = HAL_ERROR;
+    }
+  }
+  return status;
+}
+
+/**
+  * @brief  Starts the multi_buffer DMA Transfer with interrupt enabled.
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @param  SrcAddress: The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer
+  * @param  DataLength: The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  __IO uint32_t *ifcRegister_Base; /* DMA Stream Interrupt Clear register */
+
+  /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+
+  /* Memory-to-memory transfer not supported in double buffering mode */
+  if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hdma);
+
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+
+    /* Initialize the error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+    {
+      /* Enable the Double buffer mode */
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->CR |= DMA_SxCR_DBM;
+
+      /* Configure DMA Stream destination address */
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->M1AR = SecondMemAddress;
+
+      /* Calculate the interrupt clear flag register (IFCR) base address  */
+      ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 8U));
+
+      /* Clear all flags */
+      *ifcRegister_Base = 0x3FUL << (hdma->StreamIndex & 0x1FU);
+    }
+    else /* BDMA instance(s) */
+    {
+      /* Enable the Double buffer mode */
+      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR |= (BDMA_CCR_DBM | BDMA_CCR_CIRC);
+
+      /* Configure DMA Stream destination address */
+      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CM1AR = SecondMemAddress;
+
+      /* Calculate the interrupt clear flag register (IFCR) base address  */
+      ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 4U));
+
+      /* Clear all flags */
+      *ifcRegister_Base = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);
+    }
+
+    /* Configure the source, destination address and the data length */
+    DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+    if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+    {
+      /* Clear the DMAMUX synchro overrun flag */
+      hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+      if(hdma->DMAmuxRequestGen != 0U)
+      {
+        /* Clear the DMAMUX request generator overrun flag */
+        hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+      }
+    }
+
+    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+    {
+      /* Enable Common interrupts*/
+      MODIFY_REG(((DMA_Stream_TypeDef   *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME));
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR |= DMA_IT_FE;
+
+      if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
+      {
+        /*Enable Half Transfer IT if corresponding Callback is set*/
+        ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  |= DMA_IT_HT;
+      }
+    }
+    else /* BDMA instance(s) */
+    {
+      /* Enable Common interrupts*/
+      MODIFY_REG(((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR, (BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE), (BDMA_CCR_TCIE | BDMA_CCR_TEIE));
+
+      if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
+      {
+        /*Enable Half Transfer IT if corresponding Callback is set*/
+        ((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR  |= BDMA_CCR_HTIE;
+      }
+    }
+
+    if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+    {
+      /* Check if DMAMUX Synchronization is enabled*/
+      if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
+      {
+        /* Enable DMAMUX sync overrun IT*/
+        hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
+      }
+
+      if(hdma->DMAmuxRequestGen != 0U)
+      {
+        /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
+        /* enable the request gen overrun IT*/
+        hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
+      }
+    }
+
+    /* Enable the peripheral */
+    __HAL_DMA_ENABLE(hdma);
+  }
+  else
+  {
+    /* Set the error code to busy */
+    hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  return status;
+}
+
+/**
+  * @brief  Change the memory0 or memory1 address on the fly.
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @param  Address:    The new address
+  * @param  memory:     the memory to be changed, This parameter can be one of
+  *                     the following values:
+  *                      MEMORY0 /
+  *                      MEMORY1
+  * @note   The MEMORY0 address can be changed only when the current transfer use
+  *         MEMORY1 and the MEMORY1 address can be changed only when the current
+  *         transfer use MEMORY0.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)
+{
+  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+  {
+    if(memory == MEMORY0)
+    {
+      /* change the memory0 address */
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->M0AR = Address;
+    }
+    else
+    {
+      /* change the memory1 address */
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->M1AR = Address;
+    }
+  }
+  else /* BDMA instance(s) */
+  {
+    if(memory == MEMORY0)
+    {
+      /* change the memory0 address */
+      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CM0AR = Address;
+    }
+    else
+    {
+      /* change the memory1 address */
+      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CM1AR = Address;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the DMAMUX synchronization parameters for a given DMA stream (instance).
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @param  pSyncConfig : pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the DMAMUX synchronization parameters
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)
+{
+  uint32_t syncSignalID = 0;
+  uint32_t syncPolarity = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));
+  assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable));
+  assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable));
+  assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber));
+
+  if(pSyncConfig->SyncEnable == ENABLE)
+  {
+    assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig->SyncPolarity));
+
+    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+    {
+      assert_param(IS_DMA_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));
+    }
+    else
+    {
+      assert_param(IS_BDMA_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));
+    }
+    syncSignalID = pSyncConfig->SyncSignalID;
+    syncPolarity = pSyncConfig->SyncPolarity;
+  }
+
+  /*Check if the DMA state is ready */
+  if(hdma->State == HAL_DMA_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hdma);
+
+    /* Disable the synchronization and event generation before applying a new config */
+    CLEAR_BIT(hdma->DMAmuxChannel->CCR,(DMAMUX_CxCR_SE | DMAMUX_CxCR_EGE));
+
+    /* Set the new synchronization parameters (and keep the request ID filled during the Init)*/
+    MODIFY_REG( hdma->DMAmuxChannel->CCR, \
+               (~DMAMUX_CxCR_DMAREQ_ID) , \
+               (syncSignalID << DMAMUX_CxCR_SYNC_ID_Pos)       | \
+               ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \
+               syncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos)    | \
+               ((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos));
+
+      /* Process Locked */
+    __HAL_UNLOCK(hdma);
+
+    return HAL_OK;
+  }
+  else
+  {
+    /* Set the error code to busy */
+    hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+    /* Return error status */
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the DMAMUX request generator block used by the given DMA stream (instance).
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @param  pRequestGeneratorConfig : pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef :
+  *         contains the request generator parameters.
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
+{
+  HAL_StatusTypeDef status;
+  HAL_DMA_StateTypeDef temp_state = hdma->State;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));
+
+  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+  {
+    assert_param(IS_DMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));
+  }
+  else
+  {
+    assert_param(IS_BDMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));
+  }
+
+
+  assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity));
+  assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber));
+
+  /* check if the DMA state is ready
+     and DMA is using a DMAMUX request generator block
+  */
+  if(hdma->DMAmuxRequestGen == 0U)
+  {
+    /* Set the error code to busy */
+    hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
+
+    /* error status */
+    status = HAL_ERROR;
+  }
+  else if(((hdma->DMAmuxRequestGen->RGCR & DMAMUX_RGxCR_GE) == 0U) && (temp_state == HAL_DMA_STATE_READY))
+  {
+    /* RequestGenerator must be disable prior to the configuration i.e GE bit is 0 */
+
+    /* Process Locked */
+    __HAL_LOCK(hdma);
+
+    /* Set the request generator new parameters */
+    hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \
+                                  ((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GNBREQ_Pos)| \
+                                  pRequestGeneratorConfig->Polarity;
+    /* Process Locked */
+    __HAL_UNLOCK(hdma);
+
+    return HAL_OK;
+  }
+  else
+  {
+    /* Set the error code to busy */
+    hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+    /* error status */
+    status = HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Enable the DMAMUX request generator block used by the given DMA stream (instance).
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));
+
+  /* check if the DMA state is ready
+     and DMA is using a DMAMUX request generator block */
+  if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0U))
+  {
+    /* Enable the request generator*/
+    hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE;
+
+   return HAL_OK;
+ }
+ else
+ {
+   return HAL_ERROR;
+ }
+}
+
+/**
+  * @brief  Disable the DMAMUX request generator block used by the given DMA stream (instance).
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));
+
+  /* check if the DMA state is ready
+     and DMA is using a DMAMUX request generator block */
+  if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0U))
+  {
+    /* Disable the request generator*/
+    hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE;
+
+   return HAL_OK;
+ }
+ else
+ {
+   return HAL_ERROR;
+ }
+}
+
+/**
+  * @brief  Handles DMAMUX interrupt request.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Stream.
+  * @retval None
+  */
+void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma)
+{
+  /* Check for DMAMUX Synchronization overrun */
+  if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
+  {
+    /* Disable the synchro overrun interrupt */
+    hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
+
+    /* Clear the DMAMUX synchro overrun flag */
+    hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+    /* Update error code */
+    hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
+
+    if(hdma->XferErrorCallback != NULL)
+    {
+      /* Transfer error callback */
+      hdma->XferErrorCallback(hdma);
+    }
+  }
+
+  if(hdma->DMAmuxRequestGen != 0)
+  {
+   /* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */
+    if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
+    {
+      /* Disable the request gen overrun interrupt */
+      hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
+
+      /* Clear the DMAMUX request generator overrun flag */
+      hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+
+      /* Update error code */
+      hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
+
+      if(hdma->XferErrorCallback != NULL)
+      {
+        /* Transfer error callback */
+        hdma->XferErrorCallback(hdma);
+      }
+    }
+  }
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMAEx_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Set the DMA Transfer parameter.
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @param  SrcAddress: The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  DataLength: The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+  {
+    /* Configure DMA Stream data length */
+    ((DMA_Stream_TypeDef   *)hdma->Instance)->NDTR = DataLength;
+
+    /* Peripheral to Memory */
+    if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+    {
+      /* Configure DMA Stream destination address */
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->PAR = DstAddress;
+
+      /* Configure DMA Stream source address */
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->M0AR = SrcAddress;
+    }
+    /* Memory to Peripheral */
+    else
+    {
+      /* Configure DMA Stream source address */
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->PAR = SrcAddress;
+
+      /* Configure DMA Stream destination address */
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->M0AR = DstAddress;
+    }
+  }
+  else /* BDMA instance(s) */
+  {
+    /* Configure DMA Stream data length */
+    ((BDMA_Channel_TypeDef   *)hdma->Instance)->CNDTR = DataLength;
+
+    /* Peripheral to Memory */
+    if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+    {
+      /* Configure DMA Stream destination address */
+      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CPAR = DstAddress;
+
+      /* Configure DMA Stream source address */
+      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CM0AR = SrcAddress;
+    }
+    /* Memory to Peripheral */
+    else
+    {
+      /* Configure DMA Stream source address */
+      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CPAR = SrcAddress;
+
+      /* Configure DMA Stream destination address */
+      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CM0AR = DstAddress;
+    }
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c
new file mode 100644
index 00000000..ffb5deef
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c
@@ -0,0 +1,877 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_exti.c
+  * @author  MCD Application Team
+  * @brief   EXTI HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the General Purpose Input/Output (EXTI) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *
+  @verbatim
+  ==============================================================================
+                    ##### EXTI Peripheral features #####
+  ==============================================================================
+  [..]
+    (+) Each Exti line can be configured within this driver.
+
+    (+) Exti line can be configured in 3 different modes
+        (++) Interrupt (CORE1 or CORE2 in case of dual core line )
+        (++) Event (CORE1 or CORE2 in case of dual core line )
+        (++) a combination of the previous
+
+    (+) Configurable Exti lines can be configured with 3 different triggers
+        (++) Rising
+        (++) Falling
+        (++) Both of them
+
+    (+) When set in interrupt mode, configurable Exti lines have two diffenrents
+        interrupt pending registers which allow to distinguish which transition
+        occurs:
+        (++) Rising edge pending interrupt
+        (++) Falling
+
+    (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
+        be selected throught multiplexer.
+
+    (+) PendClearSource used to set the D3 Smart Run Domain autoamtic pend clear soure.
+        It is applicable for line with wkaeup target is Any (CPU1 , CPU2 and D3 smart run domain).
+        Value can be one of the following:
+        (++)  EXTI_D3_PENDCLR_SRC_NONE : no pend clear source is selcted :
+              In this case corresponding bit of D2PMRx register is set to 0
+                (+++) On a configurable Line : the D3 domain wakeup signal is
+                      automatically cleared after after the Delay + Rising Edge detect
+                (+++) On a direct Line : the D3 domain wakeup signal is
+                      cleared after the direct event input signal is cleared
+
+        (++)  EXTI_D3_PENDCLR_SRC_DMACH6 : no pend clear source is selcted :
+              In this case corresponding bit of D2PMRx register is set to 1
+              and corresponding bits(2) of D3PCRxL/H is set to b00 :
+                DMA ch6 event selected as D3 domain pendclear source
+
+        (++)  EXTI_D3_PENDCLR_SRC_DMACH7 : no pend clear source is selcted :
+              In this case corresponding bit of D2PMRx register is set to 1
+              and corresponding bits(2) of D3PCRxL/H is set to b01 :
+                DMA ch7 event selected as D3 domain pendclear source
+
+        (++)  EXTI_D3_PENDCLR_SRC_LPTIM4 : no pend clear source is selcted :
+              In this case corresponding bit of D2PMRx register is set to 1
+              and corresponding bits(2) of D3PCRxL/H is set to b10 :
+                LPTIM4 out selected as D3 domain pendclear source
+
+        (++)  EXTI_D3_PENDCLR_SRC_LPTIM5 : no pend clear source is selcted :
+              In this case corresponding bit of D2PMRx register is set to 1
+              and corresponding bits(2) of D3PCRxL/H is set to b11 :
+                LPTIM5 out selected as D3 domain pendclear source
+
+
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+
+    (#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
+        (++) Choose the interrupt line number by setting "Line" member from
+             EXTI_ConfigTypeDef structure.
+        (++) Configure the interrupt and/or event mode using "Mode" member from
+             EXTI_ConfigTypeDef structure.
+        (++) For configurable lines, configure rising and/or falling trigger
+             "Trigger" member from EXTI_ConfigTypeDef structure.
+        (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
+             member from GPIO_InitTypeDef structure.
+        (++) For Exti lines with wkaeup target is Any (CPU1 , CPU2 and D3 smart run domain),
+             choose gpio D3 PendClearSource using PendClearSource
+             member from EXTI_PendClear_Source structure.
+
+    (#) Get current Exti configuration of a dedicated line using
+        HAL_EXTI_GetConfigLine().
+        (++) Provide exiting handle as parameter.
+        (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
+
+    (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
+        (++) Provide exiting handle as parameter.
+
+    (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
+        (++) Provide exiting handle as first parameter.
+        (++) Provide which callback will be registered using one value from
+             EXTI_CallbackIDTypeDef.
+        (++) Provide callback function pointer.
+
+    (#) Get interrupt pending bit using HAL_EXTI_GetPending().
+
+    (#) Clear interrupt pending bit using HAL_EXTI_GetPending().
+
+    (#) Generate software interrupt using HAL_EXTI_GenerateSWI().
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup EXTI
+  * @{
+  */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines ------------------------------------------------------------*/
+/** @defgroup EXTI_Private_Constants EXTI Private Constants
+  * @{
+  */
+#define EXTI_MODE_OFFSET                    0x04U   /* 0x10: offset between CPU IMR/EMR registers */
+#define EXTI_CONFIG_OFFSET                  0x08U   /* 0x20: offset between CPU Rising/Falling configuration registers */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup EXTI_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup EXTI_Exported_Functions_Group1
+ *  @brief    Configuration functions
+ *
+@verbatim
+ ===============================================================================
+              ##### Configuration functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Set configuration of a dedicated Exti line.
+  * @param  hexti Exti handle.
+  * @param  pExtiConfig Pointer on EXTI configuration to be set.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
+{
+  __IO uint32_t *regaddr;
+  uint32_t regval;
+  uint32_t linepos;
+  uint32_t maskline;
+  uint32_t offset;
+  uint32_t pcrlinepos;
+
+  /* Check null pointer */
+  if ((hexti == NULL) || (pExtiConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(pExtiConfig->Line));
+  assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
+
+  /* Assign line number to handle */
+  hexti->Line = pExtiConfig->Line;
+
+  /* compute line register offset and line mask */
+  offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
+  maskline = (1UL << linepos);
+
+  /* Configure triggers for configurable lines */
+  if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00U)
+  {
+    assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
+
+    /* Configure rising trigger */
+    regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = *regaddr;
+
+    /* Mask or set line */
+    if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00U)
+    {
+      regval |= maskline;
+    }
+    else
+    {
+      regval &= ~maskline;
+    }
+
+    /* Store rising trigger mode */
+    *regaddr = regval;
+
+    /* Configure falling trigger */
+    regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = *regaddr;
+
+    /* Mask or set line */
+    if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00U)
+    {
+      regval |= maskline;
+    }
+    else
+    {
+      regval &= ~maskline;
+    }
+
+    /* Store falling trigger mode */
+    *regaddr = regval;
+
+    /* Configure gpio port selection in case of gpio exti line */
+    if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
+    {
+      assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
+      assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+      regval = SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL];
+      regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03U)));
+      regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03U)));
+      SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL] = regval;
+    }
+  }
+
+  /* Configure interrupt mode : read current mode */
+  regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = *regaddr;
+
+  /* Mask or set line */
+  if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00U)
+  {
+    regval |= maskline;
+  }
+  else
+  {
+    regval &= ~maskline;
+  }
+
+  /* Store interrupt mode */
+  *regaddr = regval;
+
+  /* The event mode cannot be configured if the line does not support it */
+  assert_param(((pExtiConfig->Line & EXTI_EVENT) == EXTI_EVENT) || ((pExtiConfig->Mode & EXTI_MODE_EVENT) != EXTI_MODE_EVENT));
+
+  /* Configure event mode : read current mode */
+  regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = *regaddr;
+
+  /* Mask or set line */
+  if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00U)
+  {
+    regval |= maskline;
+  }
+  else
+  {
+    regval &= ~maskline;
+  }
+
+  /* Store event mode */
+  *regaddr = regval;
+
+#if defined (DUAL_CORE)
+  /* Configure interrupt mode for Core2 : read current mode */
+  regaddr = (__IO uint32_t *)(&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = *regaddr;
+
+  /* Mask or set line */
+  if ((pExtiConfig->Mode & EXTI_MODE_CORE2_INTERRUPT) != 0x00U)
+  {
+    regval |= maskline;
+  }
+  else
+  {
+    regval &= ~maskline;
+  }
+
+  /* Store interrupt mode */
+  *regaddr = regval;
+
+  /* The event mode cannot be configured if the line does not support it */
+  assert_param(((pExtiConfig->Line & EXTI_EVENT) == EXTI_EVENT) || ((pExtiConfig->Mode & EXTI_MODE_CORE2_EVENT) != EXTI_MODE_CORE2_EVENT));
+
+  /* Configure event mode : read current mode */
+  regaddr = (__IO uint32_t *)(&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = *regaddr;
+
+  /* Mask or set line */
+  if ((pExtiConfig->Mode & EXTI_MODE_CORE2_EVENT) != 0x00U)
+  {
+    regval |= maskline;
+  }
+  else
+  {
+    regval &= ~maskline;
+  }
+
+  /* Store event mode */
+  *regaddr = regval;
+#endif /* DUAL_CORE */
+
+  /* Configure the D3 PendClear source in case of Wakeup target is Any */
+  if ((pExtiConfig->Line & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL)
+  {
+    assert_param(IS_EXTI_D3_PENDCLR_SRC(pExtiConfig->PendClearSource));
+
+    /*Calc the PMR register address for the given line */
+    regaddr = (__IO uint32_t *)(&EXTI->D3PMR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = *regaddr;
+
+    if(pExtiConfig->PendClearSource == EXTI_D3_PENDCLR_SRC_NONE)
+    {
+      /* Clear D3PMRx register for the given line */
+      regval &= ~maskline;
+      /* Store D3PMRx register value */
+      *regaddr = regval;
+    }
+    else
+    {
+      /* Set D3PMRx register to 1 for the given line */
+      regval |= maskline;
+      /* Store D3PMRx register value */
+      *regaddr = regval;
+
+      if(linepos < 16UL)
+      {
+        regaddr = (__IO uint32_t *)(&EXTI->D3PCR1L + (EXTI_CONFIG_OFFSET * offset));
+        pcrlinepos = 1UL << linepos;
+      }
+      else
+      {
+        regaddr = (__IO uint32_t *)(&EXTI->D3PCR1H + (EXTI_CONFIG_OFFSET * offset));
+        pcrlinepos = 1UL << (linepos - 16UL);
+      }
+
+      regval = (*regaddr & (~(pcrlinepos * pcrlinepos * 3UL))) | (pcrlinepos * pcrlinepos * (pExtiConfig->PendClearSource - 1UL));
+      *regaddr = regval;
+    }
+  }
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Get configuration of a dedicated Exti line.
+  * @param  hexti Exti handle.
+  * @param  pExtiConfig Pointer on structure to store Exti configuration.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
+{
+  __IO uint32_t *regaddr;
+  uint32_t regval;
+  uint32_t linepos;
+  uint32_t maskline;
+  uint32_t offset;
+  uint32_t pcrlinepos;
+
+  /* Check null pointer */
+  if ((hexti == NULL) || (pExtiConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameter */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+
+  /* Store handle line number to configuration structure */
+  pExtiConfig->Line = hexti->Line;
+
+  /* compute line register offset and line mask */
+  offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
+  maskline = (1UL << linepos);
+
+  /* 1] Get core mode : interrupt */
+  regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = *regaddr;
+
+  pExtiConfig->Mode = EXTI_MODE_NONE;
+
+  /* Check if selected line is enable */
+  if ((regval & maskline) != 0x00U)
+  {
+    pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
+  }
+
+  /* Get event mode */
+  regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = *regaddr;
+
+  /* Check if selected line is enable */
+  if ((regval & maskline) != 0x00U)
+  {
+    pExtiConfig->Mode |= EXTI_MODE_EVENT;
+  }
+#if defined (DUAL_CORE)
+  regaddr = (__IO uint32_t *)(&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = *regaddr;
+
+  /* Check if selected line is enable */
+  if ((regval & maskline) != 0x00U)
+  {
+    pExtiConfig->Mode = EXTI_MODE_CORE2_INTERRUPT;
+  }
+
+  /* Get event mode */
+  regaddr = (__IO uint32_t *)(&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = *regaddr;
+
+  /* Check if selected line is enable */
+  if ((regval & maskline) != 0x00U)
+  {
+    pExtiConfig->Mode |= EXTI_MODE_CORE2_EVENT;
+  }
+#endif /*DUAL_CORE*/
+
+  /* 2] Get trigger for configurable lines : rising */
+  if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00U)
+  {
+    regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = *regaddr;
+
+    /* Check if configuration of selected line is enable */
+    if ((regval & maskline) != 0x00U)
+    {
+      pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
+    }
+    else
+    {
+      pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
+    }
+
+    /* Get falling configuration */
+    regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = *regaddr;
+
+    /* Check if configuration of selected line is enable */
+    if ((regval & maskline) != 0x00U)
+    {
+      pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
+    }
+
+    /* Get Gpio port selection for gpio lines */
+    if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
+    {
+      assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+      regval = SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL];
+      pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3UL - (linepos & 0x03UL)))) >> 24U);
+    }
+    else
+    {
+      pExtiConfig->GPIOSel = 0x00U;
+    }
+  }
+  else
+  {
+    pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
+    pExtiConfig->GPIOSel = 0x00U;
+  }
+
+  /* 3] Get D3 Pend Clear source */
+  if ((pExtiConfig->Line & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL)
+  {
+    regaddr = (__IO uint32_t *)(&EXTI->D3PMR1 + (EXTI_CONFIG_OFFSET * offset));
+    if(((*regaddr) & linepos) == 0UL)
+    {
+      /* if PMR unset, then no pend clear source is used */
+      pExtiConfig->PendClearSource = EXTI_D3_PENDCLR_SRC_NONE;
+    }
+    else
+    {
+      /* if wakeup target is any and PMR set, the read pend clear source from  D3PCRxL/H */
+      if(linepos < 16UL)
+      {
+        regaddr = (__IO uint32_t *)(&EXTI->D3PCR1L + (EXTI_CONFIG_OFFSET * offset));
+        pcrlinepos = 1UL << linepos;
+      }
+      else
+      {
+        regaddr = (__IO uint32_t *)(&EXTI->D3PCR1H + (EXTI_CONFIG_OFFSET * offset));
+        pcrlinepos = 1UL << (linepos - 16UL);
+      }
+
+      pExtiConfig->PendClearSource = 1UL + ((*regaddr & (pcrlinepos * pcrlinepos * 3UL)) / (pcrlinepos * pcrlinepos));
+    }
+  }
+  else
+  {
+    /* if line wakeup target is not any, then no pend clear source is used  */
+    pExtiConfig->PendClearSource = EXTI_D3_PENDCLR_SRC_NONE;
+  }
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Clear whole configuration of a dedicated Exti line.
+  * @param  hexti Exti handle.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
+{
+  __IO uint32_t *regaddr;
+  uint32_t regval;
+  uint32_t linepos;
+  uint32_t maskline;
+  uint32_t offset;
+  uint32_t pcrlinepos;
+
+  /* Check null pointer */
+  if (hexti == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameter */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+
+  /* compute line register offset and line mask */
+  offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  linepos = (hexti->Line & EXTI_PIN_MASK);
+  maskline = (1UL << linepos);
+
+  /* 1] Clear interrupt mode */
+  regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = (*regaddr & ~maskline);
+  *regaddr = regval;
+
+  /* 2] Clear event mode */
+  regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = (*regaddr & ~maskline);
+  *regaddr = regval;
+
+#if defined (DUAL_CORE)
+    /* 1] Clear CM4 interrupt mode */
+  regaddr = (__IO uint32_t *)(&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = (*regaddr & ~maskline);
+  *regaddr = regval;
+
+  /* 2] Clear CM4 event mode */
+  regaddr = (__IO uint32_t *)(&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = (*regaddr & ~maskline);
+  *regaddr = regval;
+#endif /* DUAL_CORE */
+
+  /* 3] Clear triggers in case of configurable lines */
+  if ((hexti->Line & EXTI_CONFIG) != 0x00U)
+  {
+    regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = (*regaddr & ~maskline);
+    *regaddr = regval;
+
+    regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = (*regaddr & ~maskline);
+    *regaddr = regval;
+
+    /* Get Gpio port selection for gpio lines */
+    if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
+    {
+      assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+      regval = SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL];
+      regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03UL)));
+      SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL] = regval;
+    }
+  }
+
+  /* 4] Clear D3 Config lines */
+  if ((hexti->Line & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL)
+  {
+    regaddr = (__IO uint32_t *)(&EXTI->D3PMR1 + (EXTI_CONFIG_OFFSET * offset));
+    *regaddr = (*regaddr & ~maskline);
+
+    if(linepos < 16UL)
+    {
+      regaddr = (__IO uint32_t *)(&EXTI->D3PCR1L + (EXTI_CONFIG_OFFSET * offset));
+      pcrlinepos = 1UL << linepos;
+    }
+    else
+    {
+      regaddr = (__IO uint32_t *)(&EXTI->D3PCR1H + (EXTI_CONFIG_OFFSET * offset));
+      pcrlinepos = 1UL << (linepos - 16UL);
+    }
+
+    /*Clear D3 PendClear source */
+    *regaddr &= (~(pcrlinepos * pcrlinepos * 3UL));
+  }
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Register callback for a dedicated Exti line.
+  * @param  hexti Exti handle.
+  * @param  CallbackID User callback identifier.
+  *         This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
+  * @param  pPendingCbfn function pointer to be stored as callback.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check null pointer */
+  if (hexti == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  switch (CallbackID)
+  {
+    case  HAL_EXTI_COMMON_CB_ID:
+      hexti->PendingCallback = pPendingCbfn;
+      break;
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  return status;
+}
+
+
+/**
+  * @brief  Store line number as handle private field.
+  * @param  hexti Exti handle.
+  * @param  ExtiLine Exti line number.
+  *         This parameter can be from 0 to @ref EXTI_LINE_NB.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
+{
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(ExtiLine));
+
+  /* Check null pointer */
+  if (hexti == NULL)
+  {
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Store line number as handle private field */
+    hexti->Line = ExtiLine;
+
+    return HAL_OK;
+  }
+}
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup EXTI_Exported_Functions_Group2
+ *  @brief EXTI IO functions.
+ *
+@verbatim
+ ===============================================================================
+                       ##### IO operation functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Handle EXTI interrupt request.
+  * @param  hexti Exti handle.
+  * @retval none.
+  */
+void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
+{
+  __IO uint32_t *regaddr;
+  uint32_t regval;
+  uint32_t maskline;
+  uint32_t offset;
+
+  /* Compute line register offset and line mask */
+  offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  maskline = (1UL << (hexti->Line & EXTI_PIN_MASK));
+
+#if defined(DUAL_CORE)
+  if (HAL_GetCurrentCPUID() == CM7_CPUID)
+  {
+    /* Get pending register address */
+    regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
+  }
+  else /* Cortex-M4*/
+  {
+    /* Get pending register address */
+    regaddr = (__IO uint32_t *)(&EXTI->C2PR1 + (EXTI_MODE_OFFSET * offset));
+  }
+#else
+  regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
+#endif /* DUAL_CORE */
+
+  /* Get pending bit  */
+  regval = (*regaddr & maskline);
+
+  if (regval != 0x00U)
+  {
+    /* Clear pending bit */
+    *regaddr = maskline;
+
+    /* Call callback */
+    if (hexti->PendingCallback != NULL)
+    {
+      hexti->PendingCallback();
+    }
+  }
+}
+
+
+/**
+  * @brief  Get interrupt pending bit of a dedicated line.
+  * @param  hexti Exti handle.
+  * @param  Edge Specify which pending edge as to be checked.
+  *         This parameter can be one of the following values:
+  *           @arg @ref EXTI_TRIGGER_RISING_FALLING
+  *         This parameter is kept for compatibility with other series.
+  * @retval 1 if interrupt is pending else 0.
+  */
+uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
+{
+  __IO uint32_t *regaddr;
+  uint32_t regval;
+  uint32_t linepos;
+  uint32_t maskline;
+  uint32_t offset;
+
+  /* Check parameters */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+  assert_param(IS_EXTI_PENDING_EDGE(Edge));
+
+  /* compute line register offset and line mask */
+  offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  linepos = (hexti->Line & EXTI_PIN_MASK);
+  maskline = (1UL << linepos);
+
+#if defined(DUAL_CORE)
+  if (HAL_GetCurrentCPUID() == CM7_CPUID)
+  {
+    /* Get pending register address */
+    regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
+  }
+  else /* Cortex-M4 */
+  {
+    /* Get pending register address */
+    regaddr = (__IO uint32_t *)(&EXTI->C2PR1 + (EXTI_MODE_OFFSET * offset));
+  }
+#else
+  regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
+#endif /* DUAL_CORE */
+
+  /* return 1 if bit is set else 0 */
+  regval = ((*regaddr & maskline) >> linepos);
+  return regval;
+}
+
+
+/**
+  * @brief  Clear interrupt pending bit of a dedicated line.
+  * @param  hexti Exti handle.
+  * @param  Edge Specify which pending edge as to be clear.
+  *         This parameter can be one of the following values:
+  *           @arg @ref EXTI_TRIGGER_RISING_FALLING
+  *         This parameter is kept for compatibility with other series.
+  * @retval None.
+  */
+void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
+{
+  __IO uint32_t *regaddr;
+  uint32_t maskline;
+  uint32_t offset;
+
+  /* Check parameters */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+  assert_param(IS_EXTI_PENDING_EDGE(Edge));
+
+  /* compute line register offset and line mask */
+  offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  maskline = (1UL << (hexti->Line & EXTI_PIN_MASK));
+
+#if defined(DUAL_CORE)
+  if (HAL_GetCurrentCPUID() == CM7_CPUID)
+  {
+    /* Get pending register address */
+    regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
+  }
+  else /* Cortex-M4 */
+  {
+    /* Get pending register address */
+    regaddr = (__IO uint32_t *)(&EXTI->C2PR1 + (EXTI_MODE_OFFSET * offset));
+  }
+#else
+  regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
+#endif /* DUAL_CORE */
+
+  /* Clear Pending bit */
+  *regaddr =  maskline;
+}
+
+/**
+  * @brief  Generate a software interrupt for a dedicated line.
+  * @param  hexti Exti handle.
+  * @retval None.
+  */
+void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
+{
+  __IO uint32_t *regaddr;
+  uint32_t maskline;
+  uint32_t offset;
+
+  /* Check parameters */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+
+  /* compute line register offset and line mask */
+  offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  maskline = (1UL << (hexti->Line & EXTI_PIN_MASK));
+
+  regaddr = (__IO uint32_t *)(&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset));
+  *regaddr = maskline;
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_EXTI_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c
new file mode 100644
index 00000000..7505fd5a
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c
@@ -0,0 +1,6169 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_fdcan.c
+  * @author  MCD Application Team
+  * @brief   FDCAN HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Flexible DataRate Controller Area Network
+  *          (FDCAN) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Configuration and Control functions
+  *           + Peripheral State and Error functions
+  *
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      (#) Initialize the FDCAN peripheral using HAL_FDCAN_Init function.
+
+      (#) If needed , configure the reception filters and optional features using
+          the following configuration functions:
+            (++) HAL_FDCAN_ConfigClockCalibration
+            (++) HAL_FDCAN_ConfigFilter
+            (++) HAL_FDCAN_ConfigGlobalFilter
+            (++) HAL_FDCAN_ConfigExtendedIdMask
+            (++) HAL_FDCAN_ConfigRxFifoOverwrite
+            (++) HAL_FDCAN_ConfigFifoWatermark
+            (++) HAL_FDCAN_ConfigRamWatchdog
+            (++) HAL_FDCAN_ConfigTimestampCounter
+            (++) HAL_FDCAN_EnableTimestampCounter
+            (++) HAL_FDCAN_DisableTimestampCounter
+            (++) HAL_FDCAN_ConfigTimeoutCounter
+            (++) HAL_FDCAN_EnableTimeoutCounter
+            (++) HAL_FDCAN_DisableTimeoutCounter
+            (++) HAL_FDCAN_ConfigTxDelayCompensation
+            (++) HAL_FDCAN_EnableTxDelayCompensation
+            (++) HAL_FDCAN_DisableTxDelayCompensation
+            (++) HAL_FDCAN_EnableISOMode
+            (++) HAL_FDCAN_DisableISOMode
+            (++) HAL_FDCAN_EnableEdgeFiltering
+            (++) HAL_FDCAN_DisableEdgeFiltering
+            (++) HAL_FDCAN_TT_ConfigOperation
+            (++) HAL_FDCAN_TT_ConfigReferenceMessage
+            (++) HAL_FDCAN_TT_ConfigTrigger
+
+      (#) Start the FDCAN module using HAL_FDCAN_Start function. At this level
+          the node is active on the bus: it can send and receive messages.
+
+      (#) The following Tx control functions can only be called when the FDCAN
+          module is started:
+            (++) HAL_FDCAN_AddMessageToTxFifoQ
+            (++) HAL_FDCAN_EnableTxBufferRequest
+            (++) HAL_FDCAN_AbortTxRequest
+
+      (#) After having submitted a Tx request in Tx Fifo or Queue, it is possible to
+          get Tx buffer location used to place the Tx request thanks to
+          HAL_FDCAN_GetLatestTxFifoQRequestBuffer API.
+          It is then possible to abort later on the corresponding Tx Request using
+          HAL_FDCAN_AbortTxRequest API.
+
+      (#) When a message is received into the FDCAN message RAM, it can be
+          retrieved using the HAL_FDCAN_GetRxMessage function.
+
+      (#) Calling the HAL_FDCAN_Stop function stops the FDCAN module by entering
+          it to initialization mode and re-enabling access to configuration
+          registers through the configuration functions listed here above.
+
+      (#) All other control functions can be called any time after initialization
+          phase, no matter if the FDCAN module is started or stoped.
+
+      *** Polling mode operation ***
+      ==============================
+
+    [..]
+        (#) Reception and transmission states can be monitored via the following
+            functions:
+              (++) HAL_FDCAN_IsRxBufferMessageAvailable
+              (++) HAL_FDCAN_IsTxBufferMessagePending
+              (++) HAL_FDCAN_GetRxFifoFillLevel
+              (++) HAL_FDCAN_GetTxFifoFreeLevel
+
+      *** Interrupt mode operation ***
+      ================================
+      [..]
+        (#) There are two interrupt lines: line 0 and 1.
+            By default, all interrupts are assigned to line 0. Interrupt lines
+            can be configured using HAL_FDCAN_ConfigInterruptLines function.
+
+        (#) Notifications are activated using HAL_FDCAN_ActivateNotification
+            function. Then, the process can be controlled through one of the
+            available user callbacks: HAL_FDCAN_xxxCallback.
+
+  *** Callback registration ***
+  =============================================
+
+  The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS when set to 1
+  allows the user to configure dynamically the driver callbacks.
+  Use Function @ref HAL_FDCAN_RegisterCallback() or HAL_FDCAN_RegisterXXXCallback()
+  to register an interrupt callback.
+
+  Function @ref HAL_FDCAN_RegisterCallback() allows to register following callbacks:
+    (+) TxFifoEmptyCallback          : Tx Fifo Empty Callback.
+    (+) RxBufferNewMessageCallback   : Rx Buffer New Message Callback.
+    (+) HighPriorityMessageCallback  : High Priority Message Callback.
+    (+) TimestampWraparoundCallback  : Timestamp Wraparound Callback.
+    (+) TimeoutOccurredCallback      : Timeout Occurred Callback.
+    (+) ErrorCallback                : Error Callback.
+    (+) MspInitCallback              : FDCAN MspInit.
+    (+) MspDeInitCallback            : FDCAN MspDeInit.
+  This function takes as parameters the HAL peripheral handle, the Callback ID
+  and a pointer to the user callback function.
+
+  For specific callbacks ClockCalibrationCallback, TxEventFifoCallback, RxFifo0Callback, RxFifo1Callback,
+  TxBufferCompleteCallback, TxBufferAbortCallback, ErrorStatusCallback, TT_ScheduleSyncCallback, TT_TimeMarkCallback,
+  TT_StopWatchCallback and TT_GlobalTimeCallback, use dedicated register callbacks :
+  respectively @ref HAL_FDCAN_RegisterClockCalibrationCallback(), @ref HAL_FDCAN_RegisterTxEventFifoCallback(),
+  @ref HAL_FDCAN_RegisterRxFifo0Callback(), @ref HAL_FDCAN_RegisterRxFifo1Callback(),
+  @ref HAL_FDCAN_RegisterTxBufferCompleCallback(), @ref HAL_FDCAN_RegisterTxBufferAbortCallback(),
+  @ref HAL_FDCAN_RegisterErrorStatusCallback(), @ref HAL_FDCAN_TT_RegisterScheduleSyncCallback(),
+  @ref HAL_FDCAN_TT_RegisterTimeMarkCallback(), @ref HAL_FDCAN_TT_RegisterStopWatchCallback() and
+  @ref HAL_FDCAN_TT_RegisterGlobalTimeCallback().
+
+  Use function @ref HAL_FDCAN_UnRegisterCallback() to reset a callback to the default
+  weak function.
+  @ref HAL_FDCAN_UnRegisterCallback takes as parameters the HAL peripheral handle,
+  and the Callback ID.
+  This function allows to reset following callbacks:
+    (+) TxFifoEmptyCallback          : Tx Fifo Empty Callback.
+    (+) RxBufferNewMessageCallback   : Rx Buffer New Message Callback.
+    (+) HighPriorityMessageCallback  : High Priority Message Callback.
+    (+) TimestampWraparoundCallback  : Timestamp Wraparound Callback.
+    (+) TimeoutOccurredCallback      : Timeout Occurred Callback.
+    (+) ErrorCallback                : Error Callback.
+    (+) MspInitCallback              : FDCAN MspInit.
+    (+) MspDeInitCallback            : FDCAN MspDeInit.
+
+  For specific callbacks ClockCalibrationCallback, TxEventFifoCallback, RxFifo0Callback,
+  RxFifo1Callback, TxBufferCompleteCallback, TxBufferAbortCallback, TT_ScheduleSyncCallback,
+  TT_TimeMarkCallback, TT_StopWatchCallback and TT_GlobalTimeCallback, use dedicated
+  register callbacks : respectively @ref HAL_FDCAN_UnRegisterClockCalibrationCallback(),
+  @ref HAL_FDCAN_UnRegisterTxEventFifoCallback(), @ref HAL_FDCAN_UnRegisterRxFifo0Callback(),
+  @ref HAL_FDCAN_UnRegisterRxFifo1Callback(), @ref HAL_FDCAN_UnRegisterTxBufferCompleCallback(),
+  @ref HAL_FDCAN_UnRegisterTxBufferAbortCallback(), @ref HAL_FDCAN_UnRegisterErrorStatusCallback(),
+  @ref HAL_FDCAN_TT_UnRegisterScheduleSyncCallback(), @ref HAL_FDCAN_TT_UnRegisterTimeMarkCallback(),
+  @ref HAL_FDCAN_TT_UnRegisterStopWatchCallback() and @ref HAL_FDCAN_TT_UnRegisterGlobalTimeCallback().
+
+  By default, after the @ref HAL_FDCAN_Init() and when the state is HAL_FDCAN_STATE_RESET,
+  all callbacks are set to the corresponding weak functions:
+  examples @ref HAL_FDCAN_ErrorCallback().
+  Exception done for MspInit and MspDeInit functions that are
+  reset to the legacy weak function in the @ref HAL_FDCAN_Init()/ @ref HAL_FDCAN_DeInit() only when
+  these callbacks are null (not registered beforehand).
+  if not, MspInit or MspDeInit are not null, the @ref HAL_FDCAN_Init()/ @ref HAL_FDCAN_DeInit()
+  keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+  Callbacks can be registered/unregistered in HAL_FDCAN_STATE_READY state only.
+  Exception done MspInit/MspDeInit that can be registered/unregistered
+  in HAL_FDCAN_STATE_READY or HAL_FDCAN_STATE_RESET state,
+  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+  In that case first register the MspInit/MspDeInit user callbacks
+  using @ref HAL_FDCAN_RegisterCallback() before calling @ref HAL_FDCAN_DeInit()
+  or @ref HAL_FDCAN_Init() function.
+
+  When The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS is set to 0 or
+  not defined, the callback registration feature is not available and all callbacks
+  are set to the corresponding weak functions.
+
+  @endverbatim
+
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup FDCAN FDCAN
+  * @brief FDCAN HAL module driver
+  * @{
+  */
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup FDCAN_Private_Constants
+  * @{
+  */
+#define FDCAN_TIMEOUT_VALUE 10U
+
+#define FDCAN_TX_EVENT_FIFO_MASK (FDCAN_IR_TEFL | FDCAN_IR_TEFF | FDCAN_IR_TEFW | FDCAN_IR_TEFN)
+#define FDCAN_RX_FIFO0_MASK (FDCAN_IR_RF0L | FDCAN_IR_RF0F | FDCAN_IR_RF0W | FDCAN_IR_RF0N)
+#define FDCAN_RX_FIFO1_MASK (FDCAN_IR_RF1L | FDCAN_IR_RF1F | FDCAN_IR_RF1W | FDCAN_IR_RF1N)
+#define FDCAN_ERROR_MASK (FDCAN_IR_ELO | FDCAN_IR_WDI | FDCAN_IR_PEA | FDCAN_IR_PED | FDCAN_IR_ARA)
+#define FDCAN_ERROR_STATUS_MASK (FDCAN_IR_EP | FDCAN_IR_EW | FDCAN_IR_BO)
+#define FDCAN_TT_SCHEDULE_SYNC_MASK (FDCAN_TTIR_SBC | FDCAN_TTIR_SMC | FDCAN_TTIR_CSM | FDCAN_TTIR_SOG)
+#define FDCAN_TT_TIME_MARK_MASK (FDCAN_TTIR_RTMI | FDCAN_TTIR_TTMI)
+#define FDCAN_TT_GLOBAL_TIME_MASK (FDCAN_TTIR_GTW | FDCAN_TTIR_GTD)
+#define FDCAN_TT_DISTURBING_ERROR_MASK (FDCAN_TTIR_GTE | FDCAN_TTIR_TXU | FDCAN_TTIR_TXO | \
+                                        FDCAN_TTIR_SE1 | FDCAN_TTIR_SE2 | FDCAN_TTIR_ELC)
+#define FDCAN_TT_FATAL_ERROR_MASK (FDCAN_TTIR_IWT | FDCAN_TTIR_WT | FDCAN_TTIR_AW | FDCAN_TTIR_CER)
+
+#define FDCAN_ELEMENT_MASK_STDID ((uint32_t)0x1FFC0000U) /* Standard Identifier         */
+#define FDCAN_ELEMENT_MASK_EXTID ((uint32_t)0x1FFFFFFFU) /* Extended Identifier         */
+#define FDCAN_ELEMENT_MASK_RTR   ((uint32_t)0x20000000U) /* Remote Transmission Request */
+#define FDCAN_ELEMENT_MASK_XTD   ((uint32_t)0x40000000U) /* Extended Identifier         */
+#define FDCAN_ELEMENT_MASK_ESI   ((uint32_t)0x80000000U) /* Error State Indicator       */
+#define FDCAN_ELEMENT_MASK_TS    ((uint32_t)0x0000FFFFU) /* Timestamp                   */
+#define FDCAN_ELEMENT_MASK_DLC   ((uint32_t)0x000F0000U) /* Data Length Code            */
+#define FDCAN_ELEMENT_MASK_BRS   ((uint32_t)0x00100000U) /* Bit Rate Switch             */
+#define FDCAN_ELEMENT_MASK_FDF   ((uint32_t)0x00200000U) /* FD Format                   */
+#define FDCAN_ELEMENT_MASK_EFC   ((uint32_t)0x00800000U) /* Event FIFO Control          */
+#define FDCAN_ELEMENT_MASK_MM    ((uint32_t)0xFF000000U) /* Message Marker              */
+#define FDCAN_ELEMENT_MASK_FIDX  ((uint32_t)0x7F000000U) /* Filter Index                */
+#define FDCAN_ELEMENT_MASK_ANMF  ((uint32_t)0x80000000U) /* Accepted Non-matching Frame */
+#define FDCAN_ELEMENT_MASK_ET    ((uint32_t)0x00C00000U) /* Event type                  */
+
+#define FDCAN_MESSAGE_RAM_SIZE 0x2800U
+#define FDCAN_MESSAGE_RAM_END_ADDRESS (SRAMCAN_BASE + FDCAN_MESSAGE_RAM_SIZE - 0x4U) /* The Message RAM has a width of 4 Bytes */
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+static const uint8_t DLCtoBytes[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64};
+
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup FDCAN_Private_Functions_Prototypes
+  * @{
+  */
+static HAL_StatusTypeDef FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan);
+static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup FDCAN_Exported_Functions FDCAN Exported Functions
+  * @{
+  */
+
+/** @defgroup FDCAN_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+  ==============================================================================
+              ##### Initialization and de-initialization functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize and configure the FDCAN.
+      (+) De-initialize the FDCAN.
+      (+) Enter FDCAN peripheral in power down mode.
+      (+) Exit power down mode.
+      (+) Register callbacks.
+      (+) Unregister callbacks.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the FDCAN peripheral according to the specified
+  *         parameters in the FDCAN_InitTypeDef structure.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t tickstart;
+  HAL_StatusTypeDef status;
+  const uint32_t CvtEltSize[] = {0, 0, 0, 0, 0, 1, 2, 3, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0, 7};
+
+  /* Check FDCAN handle */
+  if (hfdcan == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check FDCAN instance */
+  if (hfdcan->Instance == FDCAN1)
+  {
+    hfdcan->ttcan = (TTCAN_TypeDef *)((uint32_t)hfdcan->Instance + 0x100U);
+  }
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_FRAME_FORMAT(hfdcan->Init.FrameFormat));
+  assert_param(IS_FDCAN_MODE(hfdcan->Init.Mode));
+  assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.AutoRetransmission));
+  assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.TransmitPause));
+  assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.ProtocolException));
+  assert_param(IS_FDCAN_NOMINAL_PRESCALER(hfdcan->Init.NominalPrescaler));
+  assert_param(IS_FDCAN_NOMINAL_SJW(hfdcan->Init.NominalSyncJumpWidth));
+  assert_param(IS_FDCAN_NOMINAL_TSEG1(hfdcan->Init.NominalTimeSeg1));
+  assert_param(IS_FDCAN_NOMINAL_TSEG2(hfdcan->Init.NominalTimeSeg2));
+  if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS)
+  {
+    assert_param(IS_FDCAN_DATA_PRESCALER(hfdcan->Init.DataPrescaler));
+    assert_param(IS_FDCAN_DATA_SJW(hfdcan->Init.DataSyncJumpWidth));
+    assert_param(IS_FDCAN_DATA_TSEG1(hfdcan->Init.DataTimeSeg1));
+    assert_param(IS_FDCAN_DATA_TSEG2(hfdcan->Init.DataTimeSeg2));
+  }
+  assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.StdFiltersNbr, 128U));
+  assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.ExtFiltersNbr, 64U));
+  assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.RxFifo0ElmtsNbr, 64U));
+  if (hfdcan->Init.RxFifo0ElmtsNbr > 0U)
+  {
+    assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.RxFifo0ElmtSize));
+  }
+  assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.RxFifo1ElmtsNbr, 64U));
+  if (hfdcan->Init.RxFifo1ElmtsNbr > 0U)
+  {
+    assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.RxFifo1ElmtSize));
+  }
+  assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.RxBuffersNbr, 64U));
+  if (hfdcan->Init.RxBuffersNbr > 0U)
+  {
+    assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.RxBufferSize));
+  }
+  assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.TxEventsNbr, 32U));
+  assert_param(IS_FDCAN_MAX_VALUE((hfdcan->Init.TxBuffersNbr + hfdcan->Init.TxFifoQueueElmtsNbr), 32U));
+  if (hfdcan->Init.TxFifoQueueElmtsNbr > 0U)
+  {
+    assert_param(IS_FDCAN_TX_FIFO_QUEUE_MODE(hfdcan->Init.TxFifoQueueMode));
+  }
+  if ((hfdcan->Init.TxBuffersNbr + hfdcan->Init.TxFifoQueueElmtsNbr) > 0U)
+  {
+    assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.TxElmtSize));
+  }
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+  if (hfdcan->State == HAL_FDCAN_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hfdcan->Lock = HAL_UNLOCKED;
+
+    /* Reset callbacks to legacy functions */
+    hfdcan->ClockCalibrationCallback    = HAL_FDCAN_ClockCalibrationCallback;    /* Legacy weak ClockCalibrationCallback    */
+    hfdcan->TxEventFifoCallback         = HAL_FDCAN_TxEventFifoCallback;         /* Legacy weak TxEventFifoCallback         */
+    hfdcan->RxFifo0Callback             = HAL_FDCAN_RxFifo0Callback;             /* Legacy weak RxFifo0Callback             */
+    hfdcan->RxFifo1Callback             = HAL_FDCAN_RxFifo1Callback;             /* Legacy weak RxFifo1Callback             */
+    hfdcan->TxFifoEmptyCallback         = HAL_FDCAN_TxFifoEmptyCallback;         /* Legacy weak TxFifoEmptyCallback         */
+    hfdcan->TxBufferCompleteCallback    = HAL_FDCAN_TxBufferCompleteCallback;    /* Legacy weak TxBufferCompleteCallback    */
+    hfdcan->TxBufferAbortCallback       = HAL_FDCAN_TxBufferAbortCallback;       /* Legacy weak TxBufferAbortCallback       */
+    hfdcan->RxBufferNewMessageCallback  = HAL_FDCAN_RxBufferNewMessageCallback;  /* Legacy weak RxBufferNewMessageCallback  */
+    hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback; /* Legacy weak HighPriorityMessageCallback */
+    hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback; /* Legacy weak TimestampWraparoundCallback */
+    hfdcan->TimeoutOccurredCallback     = HAL_FDCAN_TimeoutOccurredCallback;     /* Legacy weak TimeoutOccurredCallback     */
+    hfdcan->ErrorCallback               = HAL_FDCAN_ErrorCallback;               /* Legacy weak ErrorCallback               */
+    hfdcan->ErrorStatusCallback         = HAL_FDCAN_ErrorStatusCallback;         /* Legacy weak ErrorStatusCallback         */
+    hfdcan->TT_ScheduleSyncCallback     = HAL_FDCAN_TT_ScheduleSyncCallback;     /* Legacy weak TT_ScheduleSyncCallback     */
+    hfdcan->TT_TimeMarkCallback         = HAL_FDCAN_TT_TimeMarkCallback;         /* Legacy weak TT_TimeMarkCallback         */
+    hfdcan->TT_StopWatchCallback        = HAL_FDCAN_TT_StopWatchCallback;        /* Legacy weak TT_StopWatchCallback        */
+    hfdcan->TT_GlobalTimeCallback       = HAL_FDCAN_TT_GlobalTimeCallback;       /* Legacy weak TT_GlobalTimeCallback       */
+
+    if (hfdcan->MspInitCallback == NULL)
+    {
+      hfdcan->MspInitCallback = HAL_FDCAN_MspInit;  /* Legacy weak MspInit */
+    }
+
+    /* Init the low level hardware: CLOCK, NVIC */
+    hfdcan->MspInitCallback(hfdcan);
+  }
+#else
+  if (hfdcan->State == HAL_FDCAN_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hfdcan->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware: CLOCK, NVIC */
+    HAL_FDCAN_MspInit(hfdcan);
+  }
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+  /* Exit from Sleep mode */
+  CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Check Sleep mode acknowledge */
+  while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
+  {
+    if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+      /* Change FDCAN state */
+      hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+      return HAL_ERROR;
+    }
+  }
+
+  /* Request initialisation */
+  SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait until the INIT bit into CCCR register is set */
+  while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U)
+  {
+    /* Check for the Timeout */
+    if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+      /* Change FDCAN state */
+      hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+      return HAL_ERROR;
+    }
+  }
+
+  /* Enable configuration change */
+  SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE);
+
+  /* Set the no automatic retransmission */
+  if (hfdcan->Init.AutoRetransmission == ENABLE)
+  {
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR);
+  }
+  else
+  {
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR);
+  }
+
+  /* Set the transmit pause feature */
+  if (hfdcan->Init.TransmitPause == ENABLE)
+  {
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP);
+  }
+  else
+  {
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP);
+  }
+
+  /* Set the Protocol Exception Handling */
+  if (hfdcan->Init.ProtocolException == ENABLE)
+  {
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD);
+  }
+  else
+  {
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD);
+  }
+
+  /* Set FDCAN Frame Format */
+  MODIFY_REG(hfdcan->Instance->CCCR, FDCAN_FRAME_FD_BRS, hfdcan->Init.FrameFormat);
+
+  /* Reset FDCAN Operation Mode */
+  CLEAR_BIT(hfdcan->Instance->CCCR, (FDCAN_CCCR_TEST | FDCAN_CCCR_MON | FDCAN_CCCR_ASM));
+  CLEAR_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK);
+
+  /* Set FDCAN Operating Mode:
+               | Normal | Restricted |    Bus     | Internal | External
+               |        | Operation  | Monitoring | LoopBack | LoopBack
+     CCCR.TEST |   0    |     0      |     0      |    1     |    1
+     CCCR.MON  |   0    |     0      |     1      |    1     |    0
+     TEST.LBCK |   0    |     0      |     0      |    1     |    1
+     CCCR.ASM  |   0    |     1      |     0      |    0     |    0
+  */
+  if (hfdcan->Init.Mode == FDCAN_MODE_RESTRICTED_OPERATION)
+  {
+    /* Enable Restricted Operation mode */
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM);
+  }
+  else if (hfdcan->Init.Mode != FDCAN_MODE_NORMAL)
+  {
+    if (hfdcan->Init.Mode != FDCAN_MODE_BUS_MONITORING)
+    {
+      /* Enable write access to TEST register */
+      SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TEST);
+
+      /* Enable LoopBack mode */
+      SET_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK);
+
+      if (hfdcan->Init.Mode == FDCAN_MODE_INTERNAL_LOOPBACK)
+      {
+        SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON);
+      }
+    }
+    else
+    {
+      /* Enable bus monitoring mode */
+      SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON);
+    }
+  }
+  else
+  {
+    /* Nothing to do: normal mode */
+  }
+
+  /* Set the nominal bit timing register */
+  hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U) << FDCAN_NBTP_NSJW_Pos) | \
+                            (((uint32_t)hfdcan->Init.NominalTimeSeg1 - 1U) << FDCAN_NBTP_NTSEG1_Pos)    | \
+                            (((uint32_t)hfdcan->Init.NominalTimeSeg2 - 1U) << FDCAN_NBTP_NTSEG2_Pos)    | \
+                            (((uint32_t)hfdcan->Init.NominalPrescaler - 1U) << FDCAN_NBTP_NBRP_Pos));
+
+  /* If FD operation with BRS is selected, set the data bit timing register */
+  if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS)
+  {
+    hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos) | \
+                              (((uint32_t)hfdcan->Init.DataTimeSeg1 - 1U) << FDCAN_DBTP_DTSEG1_Pos)    | \
+                              (((uint32_t)hfdcan->Init.DataTimeSeg2 - 1U) << FDCAN_DBTP_DTSEG2_Pos)    | \
+                              (((uint32_t)hfdcan->Init.DataPrescaler - 1U) << FDCAN_DBTP_DBRP_Pos));
+  }
+
+  if (hfdcan->Init.TxFifoQueueElmtsNbr > 0U)
+  {
+    /* Select between Tx FIFO and Tx Queue operation modes */
+    SET_BIT(hfdcan->Instance->TXBC, hfdcan->Init.TxFifoQueueMode);
+  }
+
+  /* Configure Tx element size */
+  if ((hfdcan->Init.TxBuffersNbr + hfdcan->Init.TxFifoQueueElmtsNbr) > 0U)
+  {
+    MODIFY_REG(hfdcan->Instance->TXESC, FDCAN_TXESC_TBDS, CvtEltSize[hfdcan->Init.TxElmtSize]);
+  }
+
+  /* Configure Rx FIFO 0 element size */
+  if (hfdcan->Init.RxFifo0ElmtsNbr > 0U)
+  {
+    MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_F0DS, (CvtEltSize[hfdcan->Init.RxFifo0ElmtSize] << FDCAN_RXESC_F0DS_Pos));
+  }
+
+  /* Configure Rx FIFO 1 element size */
+  if (hfdcan->Init.RxFifo1ElmtsNbr > 0U)
+  {
+    MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_F1DS, (CvtEltSize[hfdcan->Init.RxFifo1ElmtSize] << FDCAN_RXESC_F1DS_Pos));
+  }
+
+  /* Configure Rx buffer element size */
+  if (hfdcan->Init.RxBuffersNbr > 0U)
+  {
+    MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_RBDS, (CvtEltSize[hfdcan->Init.RxBufferSize] << FDCAN_RXESC_RBDS_Pos));
+  }
+
+  /* By default operation mode is set to Event-driven communication.
+     If Time-triggered communication is needed, user should call the
+     HAL_FDCAN_TT_ConfigOperation function just after the HAL_FDCAN_Init */
+  if (hfdcan->Instance == FDCAN1)
+  {
+    CLEAR_BIT(hfdcan->ttcan->TTOCF, FDCAN_TTOCF_OM);
+  }
+
+  /* Initialize the Latest Tx FIFO/Queue request buffer index */
+  hfdcan->LatestTxFifoQRequest = 0U;
+
+  /* Initialize the error code */
+  hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
+
+  /* Initialize the FDCAN state */
+  hfdcan->State = HAL_FDCAN_STATE_READY;
+
+  /* Calculate each RAM block address */
+  status = FDCAN_CalcultateRamBlockAddresses(hfdcan);
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Deinitializes the FDCAN peripheral registers to their default reset values.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Check FDCAN handle */
+  if (hfdcan == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance));
+
+  /* Stop the FDCAN module: return value is voluntary ignored */
+  (void)HAL_FDCAN_Stop(hfdcan);
+
+  /* Disable Interrupt lines */
+  CLEAR_BIT(hfdcan->Instance->ILE, (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1));
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+  if (hfdcan->MspDeInitCallback == NULL)
+  {
+    hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit; /* Legacy weak MspDeInit */
+  }
+
+  /* DeInit the low level hardware: CLOCK, NVIC */
+  hfdcan->MspDeInitCallback(hfdcan);
+#else
+  /* DeInit the low level hardware: CLOCK, NVIC */
+  HAL_FDCAN_MspDeInit(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+  /* Reset the FDCAN ErrorCode */
+  hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
+
+  /* Change FDCAN state */
+  hfdcan->State = HAL_FDCAN_STATE_RESET;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the FDCAN MSP.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes the FDCAN MSP.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Enter FDCAN peripheral in sleep mode.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t tickstart;
+
+  /* Request clock stop */
+  SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait until FDCAN is ready for power down */
+  while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+      /* Change FDCAN state */
+      hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+      return HAL_ERROR;
+    }
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Exit power down mode.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t tickstart;
+
+  /* Reset clock stop request */
+  CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait until FDCAN exits sleep mode */
+  while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
+  {
+    if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+      /* Change FDCAN state */
+      hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+      return HAL_ERROR;
+    }
+  }
+
+  /* Enter normal operation */
+  CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+/**
+  * @brief  Register a FDCAN CallBack.
+  *         To be used instead of the weak predefined callback
+  * @param  hfdcan pointer to a FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for FDCAN module
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_FDCAN_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty callback ID
+  *           @arg @ref HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID Rx buffer new message callback ID
+  *           @arg @ref HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID High priority message callback ID
+  *           @arg @ref HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID Timestamp wraparound callback ID
+  *           @arg @ref HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID Timeout occurred callback ID
+  *           @arg @ref HAL_FDCAN_ERROR_CALLBACK_CB_ID Error callback ID
+  *           @arg @ref HAL_FDCAN_MSPINIT_CB_ID MspInit callback ID
+  *           @arg @ref HAL_FDCAN_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, void (* pCallback)(FDCAN_HandleTypeDef *_hFDCAN))
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_FDCAN_TX_FIFO_EMPTY_CB_ID :
+        hfdcan->TxFifoEmptyCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID :
+        hfdcan->RxBufferNewMessageCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID :
+        hfdcan->HighPriorityMessageCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID :
+        hfdcan->TimestampWraparoundCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID :
+        hfdcan->TimeoutOccurredCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_ERROR_CALLBACK_CB_ID :
+        hfdcan->ErrorCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_MSPINIT_CB_ID :
+        hfdcan->MspInitCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_MSPDEINIT_CB_ID :
+        hfdcan->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hfdcan->State == HAL_FDCAN_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_FDCAN_MSPINIT_CB_ID :
+        hfdcan->MspInitCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_MSPDEINIT_CB_ID :
+        hfdcan->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a FDCAN CallBack.
+  *         FDCAN callback is redirected to the weak predefined callback
+  * @param  hfdcan pointer to a FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for FDCAN module
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_FDCAN_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty callback ID
+  *           @arg @ref HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID Rx buffer new message callback ID
+  *           @arg @ref HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID High priority message callback ID
+  *           @arg @ref HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID Timestamp wraparound callback ID
+  *           @arg @ref HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID Timeout occurred callback ID
+  *           @arg @ref HAL_FDCAN_ERROR_CALLBACK_CB_ID Error callback ID
+  *           @arg @ref HAL_FDCAN_MSPINIT_CB_ID MspInit callback ID
+  *           @arg @ref HAL_FDCAN_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_FDCAN_TX_FIFO_EMPTY_CB_ID :
+        hfdcan->TxFifoEmptyCallback = HAL_FDCAN_TxFifoEmptyCallback;
+        break;
+
+      case HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID :
+        hfdcan->RxBufferNewMessageCallback = HAL_FDCAN_RxBufferNewMessageCallback;
+        break;
+
+      case HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID :
+        hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback;
+        break;
+
+      case HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID :
+        hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback;
+        break;
+
+      case HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID :
+        hfdcan->TimeoutOccurredCallback = HAL_FDCAN_TimeoutOccurredCallback;
+        break;
+
+      case HAL_FDCAN_ERROR_CALLBACK_CB_ID :
+        hfdcan->ErrorCallback = HAL_FDCAN_ErrorCallback;
+        break;
+
+      case HAL_FDCAN_MSPINIT_CB_ID :
+        hfdcan->MspInitCallback = HAL_FDCAN_MspInit;
+        break;
+
+      case HAL_FDCAN_MSPDEINIT_CB_ID :
+        hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hfdcan->State == HAL_FDCAN_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_FDCAN_MSPINIT_CB_ID :
+        hfdcan->MspInitCallback = HAL_FDCAN_MspInit;
+        break;
+
+      case HAL_FDCAN_MSPDEINIT_CB_ID :
+        hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register Clock Calibration FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_ClockCalibrationCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the Clock Calibration Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ClockCalibrationCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->ClockCalibrationCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Clock Calibration FDCAN Callback
+  *         Clock Calibration FDCAN Callback is redirected to the weak HAL_FDCAN_ClockCalibrationCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->ClockCalibrationCallback = HAL_FDCAN_ClockCalibrationCallback; /* Legacy weak ClockCalibrationCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register Tx Event Fifo FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_TxEventFifoCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the Tx Event Fifo Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxEventFifoCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TxEventFifoCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Tx Event Fifo FDCAN Callback
+  *         Tx Event Fifo FDCAN Callback is redirected to the weak HAL_FDCAN_TxEventFifoCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TxEventFifoCallback = HAL_FDCAN_TxEventFifoCallback; /* Legacy weak TxEventFifoCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register Rx Fifo 0 FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_RxFifo0Callback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the Rx Fifo 0 Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo0CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->RxFifo0Callback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Rx Fifo 0 FDCAN Callback
+  *         Rx Fifo 0 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo0Callback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->RxFifo0Callback = HAL_FDCAN_RxFifo0Callback; /* Legacy weak RxFifo0Callback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register Rx Fifo 1 FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_RxFifo1Callback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the Rx Fifo 1 Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo1CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->RxFifo1Callback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Rx Fifo 1 FDCAN Callback
+  *         Rx Fifo 1 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo1Callback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->RxFifo1Callback = HAL_FDCAN_RxFifo1Callback; /* Legacy weak RxFifo1Callback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register Tx Buffer Complete FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the Tx Buffer Complete Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferCompleteCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TxBufferCompleteCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Tx Buffer Complete FDCAN Callback
+  *         Tx Buffer Complete FDCAN Callback is redirected to the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TxBufferCompleteCallback = HAL_FDCAN_TxBufferCompleteCallback; /* Legacy weak TxBufferCompleteCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register Tx Buffer Abort FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the Tx Buffer Abort Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferAbortCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TxBufferAbortCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Tx Buffer Abort FDCAN Callback
+  *         Tx Buffer Abort FDCAN Callback is redirected to the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TxBufferAbortCallback = HAL_FDCAN_TxBufferAbortCallback; /* Legacy weak TxBufferAbortCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register Error Status FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_ErrorStatusCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the Error Status Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ErrorStatusCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->ErrorStatusCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Error Status FDCAN Callback
+  *         Error Status FDCAN Callback is redirected to the weak HAL_FDCAN_ErrorStatusCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->ErrorStatusCallback = HAL_FDCAN_ErrorStatusCallback; /* Legacy weak ErrorStatusCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register TT Schedule Synchronization FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_TT_ScheduleSyncCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the TT Schedule Synchronization Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_ScheduleSyncCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_ScheduleSyncCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the TT Schedule Synchronization FDCAN Callback
+  *         TT Schedule Synchronization Callback is redirected to the weak HAL_FDCAN_TT_ScheduleSyncCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_ScheduleSyncCallback = HAL_FDCAN_TT_ScheduleSyncCallback; /* Legacy weak TT_ScheduleSyncCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register TT Time Mark FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_TT_TimeMarkCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the TT Time Mark Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_TimeMarkCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_TimeMarkCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the TT Time Mark FDCAN Callback
+  *         TT Time Mark Callback is redirected to the weak HAL_FDCAN_TT_TimeMarkCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_TimeMarkCallback = HAL_FDCAN_TT_TimeMarkCallback; /* Legacy weak TT_TimeMarkCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register TT Stop Watch FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_TT_StopWatchCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the TT Stop Watch Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_StopWatchCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_StopWatchCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the TT Stop Watch FDCAN Callback
+  *         TT Stop Watch Callback is redirected to the weak HAL_FDCAN_TT_StopWatchCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_StopWatchCallback = HAL_FDCAN_TT_StopWatchCallback; /* Legacy weak TT_StopWatchCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register TT Global Time FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_TT_GlobalTimeCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the TT Global Time Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_GlobalTimeCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_GlobalTimeCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the TT Global Time FDCAN Callback
+  *         TT Global Time Callback is redirected to the weak HAL_FDCAN_TT_GlobalTimeCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_GlobalTimeCallback = HAL_FDCAN_TT_GlobalTimeCallback; /* Legacy weak TT_GlobalTimeCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Exported_Functions_Group2 Configuration functions
+ *  @brief    FDCAN Configuration functions.
+ *
+@verbatim
+  ==============================================================================
+              ##### Configuration functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) HAL_FDCAN_ConfigClockCalibration        : Configure the FDCAN clock calibration unit
+        (+) HAL_FDCAN_GetClockCalibrationState      : Get the clock calibration state
+        (+) HAL_FDCAN_ResetClockCalibrationState    : Reset the clock calibration state
+        (+) HAL_FDCAN_GetClockCalibrationCounter    : Get the clock calibration counters values
+      (+) HAL_FDCAN_ConfigFilter                  : Configure the FDCAN reception filters
+      (+) HAL_FDCAN_ConfigGlobalFilter            : Configure the FDCAN global filter
+      (+) HAL_FDCAN_ConfigExtendedIdMask          : Configure the extended ID mask
+      (+) HAL_FDCAN_ConfigRxFifoOverwrite         : Configure the Rx FIFO operation mode
+      (+) HAL_FDCAN_ConfigFifoWatermark           : Configure the FIFO watermark
+      (+) HAL_FDCAN_ConfigRamWatchdog             : Configure the RAM watchdog
+      (+) HAL_FDCAN_ConfigTimestampCounter        : Configure the timestamp counter
+        (+) HAL_FDCAN_EnableTimestampCounter        : Enable the timestamp counter
+        (+) HAL_FDCAN_DisableTimestampCounter       : Disable the timestamp counter
+        (+) HAL_FDCAN_GetTimestampCounter           : Get the timestamp counter value
+        (+) HAL_FDCAN_ResetTimestampCounter         : Reset the timestamp counter to zero
+      (+) HAL_FDCAN_ConfigTimeoutCounter          : Configure the timeout counter
+        (+) HAL_FDCAN_EnableTimeoutCounter          : Enable the timeout counter
+        (+) HAL_FDCAN_DisableTimeoutCounter         : Disable the timeout counter
+        (+) HAL_FDCAN_GetTimeoutCounter             : Get the timeout counter value
+        (+) HAL_FDCAN_ResetTimeoutCounter           : Reset the timeout counter to its start value
+      (+) HAL_FDCAN_ConfigTxDelayCompensation     : Configure the transmitter delay compensation
+        (+) HAL_FDCAN_EnableTxDelayCompensation     : Enable the transmitter delay compensation
+        (+) HAL_FDCAN_DisableTxDelayCompensation    : Disable the transmitter delay compensation
+      (+) HAL_FDCAN_EnableISOMode                 : Enable ISO 11898-1 protocol mode
+      (+) HAL_FDCAN_DisableISOMode                : Disable ISO 11898-1 protocol mode
+      (+) HAL_FDCAN_EnableEdgeFiltering           : Enable edge filtering during bus integration
+      (+) HAL_FDCAN_DisableEdgeFiltering          : Disable edge filtering during bus integration
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the FDCAN clock calibration unit according to the specified
+  *         parameters in the FDCAN_ClkCalUnitTypeDef structure.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  sCcuConfig pointer to an FDCAN_ClkCalUnitTypeDef structure that
+  *         contains the clock calibration information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigClockCalibration(FDCAN_HandleTypeDef *hfdcan, FDCAN_ClkCalUnitTypeDef *sCcuConfig)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_CLOCK_CALIBRATION(sCcuConfig->ClockCalibration));
+  if (sCcuConfig->ClockCalibration == FDCAN_CLOCK_CALIBRATION_DISABLE)
+  {
+    assert_param(IS_FDCAN_CKDIV(sCcuConfig->ClockDivider));
+  }
+  else
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(sCcuConfig->MinOscClkPeriods, 0xFFU));
+    assert_param(IS_FDCAN_CALIBRATION_FIELD_LENGTH(sCcuConfig->CalFieldLength));
+    assert_param(IS_FDCAN_MIN_VALUE(sCcuConfig->TimeQuantaPerBitTime, 4U));
+    assert_param(IS_FDCAN_MAX_VALUE(sCcuConfig->TimeQuantaPerBitTime, 0x25U));
+    assert_param(IS_FDCAN_MAX_VALUE(sCcuConfig->WatchdogStartValue, 0xFFFFU));
+  }
+
+  /* FDCAN1 should be initialized in order to use clock calibration */
+  if (hfdcan->Instance != FDCAN1)
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    if (sCcuConfig->ClockCalibration == FDCAN_CLOCK_CALIBRATION_DISABLE)
+    {
+      /* Bypass clock calibration */
+      SET_BIT(FDCAN_CCU->CCFG, FDCANCCU_CCFG_BCC);
+
+      /* Configure clock divider */
+      MODIFY_REG(FDCAN_CCU->CCFG, FDCANCCU_CCFG_CDIV, sCcuConfig->ClockDivider);
+    }
+    else /* sCcuConfig->ClockCalibration == ENABLE */
+    {
+      /* Clock calibration unit generates time quanta clock */
+      CLEAR_BIT(FDCAN_CCU->CCFG, FDCANCCU_CCFG_BCC);
+
+      /* Configure clock calibration unit */
+      MODIFY_REG(FDCAN_CCU->CCFG,
+                 (FDCANCCU_CCFG_TQBT | FDCANCCU_CCFG_CFL | FDCANCCU_CCFG_OCPM),
+                 ((sCcuConfig->TimeQuantaPerBitTime << FDCANCCU_CCFG_TQBT_Pos) | sCcuConfig->CalFieldLength | (sCcuConfig->MinOscClkPeriods << FDCANCCU_CCFG_OCPM_Pos)));
+
+      /* Configure the start value of the calibration watchdog counter */
+      MODIFY_REG(FDCAN_CCU->CWD, FDCANCCU_CWD_WDC, sCcuConfig->WatchdogStartValue);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get the clock calibration state.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval State clock calibration state (can be a value of @arg FDCAN_calibration_state)
+  */
+uint32_t HAL_FDCAN_GetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  return (FDCAN_CCU->CSTAT & FDCANCCU_CSTAT_CALS);
+}
+
+/**
+  * @brief  Reset the clock calibration state.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ResetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* FDCAN1 should be initialized in order to use clock calibration */
+  if (hfdcan->Instance != FDCAN1)
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Calibration software reset */
+    SET_BIT(FDCAN_CCU->CCFG, FDCANCCU_CCFG_SWR);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get the clock calibration counter value.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  Counter clock calibration counter.
+  *         This parameter can be a value of @arg FDCAN_calibration_counter.
+  * @retval Value clock calibration counter value
+  */
+uint32_t HAL_FDCAN_GetClockCalibrationCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t Counter)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_CALIBRATION_COUNTER(Counter));
+
+  if (Counter == FDCAN_CALIB_TIME_QUANTA_COUNTER)
+  {
+    return ((FDCAN_CCU->CSTAT & FDCANCCU_CSTAT_TQC) >> FDCANCCU_CSTAT_TQC_Pos);
+  }
+  else if (Counter == FDCAN_CALIB_CLOCK_PERIOD_COUNTER)
+  {
+    return (FDCAN_CCU->CSTAT & FDCANCCU_CSTAT_OCPC);
+  }
+  else /* Counter == FDCAN_CALIB_WATCHDOG_COUNTER */
+  {
+    return ((FDCAN_CCU->CWD & FDCANCCU_CWD_WDV) >> FDCANCCU_CWD_WDV_Pos);
+  }
+}
+
+/**
+  * @brief  Configure the FDCAN reception filter according to the specified
+  *         parameters in the FDCAN_FilterTypeDef structure.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  sFilterConfig pointer to an FDCAN_FilterTypeDef structure that
+  *         contains the filter configuration information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig)
+{
+  uint32_t FilterElementW1;
+  uint32_t FilterElementW2;
+  uint32_t *FilterAddress;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Check function parameters */
+    assert_param(IS_FDCAN_ID_TYPE(sFilterConfig->IdType));
+    assert_param(IS_FDCAN_FILTER_CFG(sFilterConfig->FilterConfig));
+    if (sFilterConfig->FilterConfig == FDCAN_FILTER_TO_RXBUFFER)
+    {
+      assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->RxBufferIndex, 63U));
+      assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->IsCalibrationMsg, 1U));
+    }
+
+    if (sFilterConfig->IdType == FDCAN_STANDARD_ID)
+    {
+      /* Check function parameters */
+      assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.StdFiltersNbr - 1U)));
+      assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x7FFU));
+      if (sFilterConfig->FilterConfig != FDCAN_FILTER_TO_RXBUFFER)
+      {
+        assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x7FFU));
+        assert_param(IS_FDCAN_STD_FILTER_TYPE(sFilterConfig->FilterType));
+      }
+
+      /* Build filter element */
+      if (sFilterConfig->FilterConfig == FDCAN_FILTER_TO_RXBUFFER)
+      {
+        FilterElementW1 = ((FDCAN_FILTER_TO_RXBUFFER << 27U)       |
+                           (sFilterConfig->FilterID1 << 16U)       |
+                           (sFilterConfig->IsCalibrationMsg << 8U) |
+                           sFilterConfig->RxBufferIndex);
+      }
+      else
+      {
+        FilterElementW1 = ((sFilterConfig->FilterType << 30U)   |
+                           (sFilterConfig->FilterConfig << 27U) |
+                           (sFilterConfig->FilterID1 << 16U)    |
+                           sFilterConfig->FilterID2);
+      }
+
+      /* Calculate filter address */
+      FilterAddress = (uint32_t *)(hfdcan->msgRam.StandardFilterSA + (sFilterConfig->FilterIndex * 4U));
+
+      /* Write filter element to the message RAM */
+      *FilterAddress = FilterElementW1;
+    }
+    else /* sFilterConfig->IdType == FDCAN_EXTENDED_ID */
+    {
+      /* Check function parameters */
+      assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.ExtFiltersNbr - 1U)));
+      assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x1FFFFFFFU));
+      if (sFilterConfig->FilterConfig != FDCAN_FILTER_TO_RXBUFFER)
+      {
+        assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x1FFFFFFFU));
+        assert_param(IS_FDCAN_EXT_FILTER_TYPE(sFilterConfig->FilterType));
+      }
+
+      /* Build first word of filter element */
+      FilterElementW1 = ((sFilterConfig->FilterConfig << 29U) | sFilterConfig->FilterID1);
+
+      /* Build second word of filter element */
+      if (sFilterConfig->FilterConfig == FDCAN_FILTER_TO_RXBUFFER)
+      {
+        FilterElementW2 = sFilterConfig->RxBufferIndex;
+      }
+      else
+      {
+        FilterElementW2 = ((sFilterConfig->FilterType << 30U) | sFilterConfig->FilterID2);
+      }
+
+      /* Calculate filter address */
+      FilterAddress = (uint32_t *)(hfdcan->msgRam.ExtendedFilterSA + (sFilterConfig->FilterIndex * 4U * 2U));
+
+      /* Write filter element to the message RAM */
+      *FilterAddress = FilterElementW1;
+      FilterAddress++;
+      *FilterAddress = FilterElementW2;
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the FDCAN global filter.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  NonMatchingStd Defines how received messages with 11-bit IDs that
+  *         do not match any element of the filter list are treated.
+  *         This parameter can be a value of @arg FDCAN_Non_Matching_Frames.
+  * @param  NonMatchingExt Defines how received messages with 29-bit IDs that
+  *         do not match any element of the filter list are treated.
+  *         This parameter can be a value of @arg FDCAN_Non_Matching_Frames.
+  * @param  RejectRemoteStd Filter or reject all the remote 11-bit IDs frames.
+  *         This parameter can be a value of @arg FDCAN_Reject_Remote_Frames.
+  * @param  RejectRemoteExt Filter or reject all the remote 29-bit IDs frames.
+  *         This parameter can be a value of @arg FDCAN_Reject_Remote_Frames.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan,
+                                               uint32_t NonMatchingStd,
+                                               uint32_t NonMatchingExt,
+                                               uint32_t RejectRemoteStd,
+                                               uint32_t RejectRemoteExt)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_NON_MATCHING(NonMatchingStd));
+  assert_param(IS_FDCAN_NON_MATCHING(NonMatchingExt));
+  assert_param(IS_FDCAN_REJECT_REMOTE(RejectRemoteStd));
+  assert_param(IS_FDCAN_REJECT_REMOTE(RejectRemoteExt));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Configure global filter */
+    hfdcan->Instance->GFC = ((NonMatchingStd << FDCAN_GFC_ANFS_Pos)  |
+                             (NonMatchingExt << FDCAN_GFC_ANFE_Pos)  |
+                             (RejectRemoteStd << FDCAN_GFC_RRFS_Pos) |
+                             (RejectRemoteExt << FDCAN_GFC_RRFE_Pos));
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the extended ID mask.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  Mask Extended ID Mask.
+  *         This parameter must be a number between 0 and 0x1FFFFFFF
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_MAX_VALUE(Mask, 0x1FFFFFFFU));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Configure the extended ID mask */
+    hfdcan->Instance->XIDAM = Mask;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the Rx FIFO operation mode.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  RxFifo Rx FIFO.
+  *         This parameter can be one of the following values:
+  *           @arg FDCAN_RX_FIFO0: Rx FIFO 0
+  *           @arg FDCAN_RX_FIFO1: Rx FIFO 1
+  * @param  OperationMode operation mode.
+  *         This parameter can be a value of @arg FDCAN_Rx_FIFO_operation_mode.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_RX_FIFO(RxFifo));
+  assert_param(IS_FDCAN_RX_FIFO_MODE(OperationMode));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    if (RxFifo == FDCAN_RX_FIFO0)
+    {
+      /* Select FIFO 0 Operation Mode */
+      MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0OM, OperationMode);
+    }
+    else /* RxFifo == FDCAN_RX_FIFO1 */
+    {
+      /* Select FIFO 1 Operation Mode */
+      MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1OM, OperationMode);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the FIFO watermark.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  FIFO select the FIFO to be configured.
+  *         This parameter can be a value of @arg FDCAN_FIFO_watermark.
+  * @param  Watermark level for FIFO watermark interrupt.
+  *         This parameter must be a number between:
+  *           - 0 and 32, if FIFO is FDCAN_CFG_TX_EVENT_FIFO
+  *           - 0 and 64, if FIFO is FDCAN_CFG_RX_FIFO0 or FDCAN_CFG_RX_FIFO1
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigFifoWatermark(FDCAN_HandleTypeDef *hfdcan, uint32_t FIFO, uint32_t Watermark)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_FIFO_WATERMARK(FIFO));
+  if (FIFO == FDCAN_CFG_TX_EVENT_FIFO)
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(Watermark, 32U));
+  }
+  else /* (FIFO == FDCAN_CFG_RX_FIFO0) || (FIFO == FDCAN_CFG_RX_FIFO1) */
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(Watermark, 64U));
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Set the level for FIFO watermark interrupt */
+    if (FIFO == FDCAN_CFG_TX_EVENT_FIFO)
+    {
+      MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFWM, (Watermark << FDCAN_TXEFC_EFWM_Pos));
+    }
+    else if (FIFO == FDCAN_CFG_RX_FIFO0)
+    {
+      MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0WM, (Watermark << FDCAN_RXF0C_F0WM_Pos));
+    }
+    else /* FIFO == FDCAN_CFG_RX_FIFO1 */
+    {
+      MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1WM, (Watermark << FDCAN_RXF1C_F1WM_Pos));
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the RAM watchdog.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  CounterStartValue Start value of the Message RAM Watchdog Counter,
+  *         This parameter must be a number between 0x00 and 0xFF,
+  *         with the reset value of 0x00 the counter is disabled.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_MAX_VALUE(CounterStartValue, 0xFFU));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Configure the RAM watchdog counter start value */
+    MODIFY_REG(hfdcan->Instance->RWD, FDCAN_RWD_WDC, CounterStartValue);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the timestamp counter.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TimestampPrescaler Timestamp Counter Prescaler.
+  *         This parameter can be a value of @arg FDCAN_Timestamp_Prescaler.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TIMESTAMP_PRESCALER(TimestampPrescaler));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Configure prescaler */
+    MODIFY_REG(hfdcan->Instance->TSCC, FDCAN_TSCC_TCP, TimestampPrescaler);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable the timestamp counter.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TimestampOperation Timestamp counter operation.
+  *         This parameter can be a value of @arg FDCAN_Timestamp.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TIMESTAMP(TimestampOperation));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Enable timestamp counter */
+    MODIFY_REG(hfdcan->Instance->TSCC, FDCAN_TSCC_TSS, TimestampOperation);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable the timestamp counter.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Disable timestamp counter */
+    CLEAR_BIT(hfdcan->Instance->TSCC, FDCAN_TSCC_TSS);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get the timestamp counter value.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval Value Timestamp counter value
+  */
+uint16_t HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+  return (uint16_t)(hfdcan->Instance->TSCV);
+}
+
+/**
+  * @brief  Reset the timestamp counter to zero.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+  if ((hfdcan->Instance->TSCC & FDCAN_TSCC_TSS) != FDCAN_TIMESTAMP_EXTERNAL)
+  {
+    /* Reset timestamp counter.
+       Actually any write operation to TSCV clears the counter */
+    CLEAR_REG(hfdcan->Instance->TSCV);
+  }
+  else
+  {
+    /* Update error code.
+       Unable to reset external counter */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+    return HAL_ERROR;
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the timeout counter.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TimeoutOperation Timeout counter operation.
+  *         This parameter can be a value of @arg FDCAN_Timeout_Operation.
+  * @param  TimeoutPeriod Start value of the timeout down-counter.
+  *         This parameter must be a number between 0x0000 and 0xFFFF
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TIMEOUT(TimeoutOperation));
+  assert_param(IS_FDCAN_MAX_VALUE(TimeoutPeriod, 0xFFFFU));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Select timeout operation and configure period */
+    MODIFY_REG(hfdcan->Instance->TOCC, (FDCAN_TOCC_TOS | FDCAN_TOCC_TOP), (TimeoutOperation | (TimeoutPeriod << FDCAN_TOCC_TOP_Pos)));
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable the timeout counter.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Enable timeout counter */
+    SET_BIT(hfdcan->Instance->TOCC, FDCAN_TOCC_ETOC);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable the timeout counter.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Disable timeout counter */
+    CLEAR_BIT(hfdcan->Instance->TOCC, FDCAN_TOCC_ETOC);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get the timeout counter value.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval Value Timeout counter value
+  */
+uint16_t HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+  return (uint16_t)(hfdcan->Instance->TOCV);
+}
+
+/**
+  * @brief  Reset the timeout counter to its start value.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+  if ((hfdcan->Instance->TOCC & FDCAN_TOCC_TOS) == FDCAN_TIMEOUT_CONTINUOUS)
+  {
+    /* Reset timeout counter to start value */
+    CLEAR_REG(hfdcan->Instance->TOCV);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code.
+       Unable to reset counter: controlled only by FIFO empty state */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the transmitter delay compensation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TdcOffset Transmitter Delay Compensation Offset.
+  *         This parameter must be a number between 0x00 and 0x7F.
+  * @param  TdcFilter Transmitter Delay Compensation Filter Window Length.
+  *         This parameter must be a number between 0x00 and 0x7F.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_MAX_VALUE(TdcOffset, 0x7FU));
+  assert_param(IS_FDCAN_MAX_VALUE(TdcFilter, 0x7FU));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Configure TDC offset and filter window */
+    hfdcan->Instance->TDCR = ((TdcFilter << FDCAN_TDCR_TDCF_Pos) | (TdcOffset << FDCAN_TDCR_TDCO_Pos));
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable the transmitter delay compensation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Enable transmitter delay compensation */
+    SET_BIT(hfdcan->Instance->DBTP, FDCAN_DBTP_TDC);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable the transmitter delay compensation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Disable transmitter delay compensation */
+    CLEAR_BIT(hfdcan->Instance->DBTP, FDCAN_DBTP_TDC);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable ISO 11898-1 protocol mode.
+  *         CAN FD frame format is according to ISO 11898-1 standard.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Disable Non ISO protocol mode */
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_NISO);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable ISO 11898-1 protocol mode.
+  *         CAN FD frame format is according to Bosch CAN FD specification V1.0.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Enable Non ISO protocol mode */
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_NISO);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable edge filtering during bus integration.
+  *         Two consecutive dominant tq are required to detect an edge for hard synchronization.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Enable edge filtering */
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_EFBI);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable edge filtering during bus integration.
+  *         One dominant tq is required to detect an edge for hard synchronization.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Disable edge filtering */
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_EFBI);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Exported_Functions_Group3 Control functions
+ *  @brief    Control functions
+ *
+@verbatim
+  ==============================================================================
+                          ##### Control functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) HAL_FDCAN_Start                         : Start the FDCAN module
+      (+) HAL_FDCAN_Stop                          : Stop the FDCAN module and enable access to configuration registers
+      (+) HAL_FDCAN_AddMessageToTxFifoQ           : Add a message to the Tx FIFO/Queue and activate the corresponding transmission request
+      (+) HAL_FDCAN_AddMessageToTxBuffer          : Add a message to a dedicated Tx buffer
+      (+) HAL_FDCAN_EnableTxBufferRequest         : Enable transmission request
+      (+) HAL_FDCAN_GetLatestTxFifoQRequestBuffer : Get Tx buffer index of latest Tx FIFO/Queue request
+      (+) HAL_FDCAN_AbortTxRequest                : Abort transmission request
+      (+) HAL_FDCAN_GetRxMessage                  : Get an FDCAN frame from the Rx Buffer/FIFO zone into the message RAM
+      (+) HAL_FDCAN_GetTxEvent                    : Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM
+      (+) HAL_FDCAN_GetHighPriorityMessageStatus  : Get high priority message status
+      (+) HAL_FDCAN_GetProtocolStatus             : Get protocol status
+      (+) HAL_FDCAN_GetErrorCounters              : Get error counter values
+      (+) HAL_FDCAN_IsRxBufferMessageAvailable    : Check if a new message is received in the selected Rx buffer
+      (+) HAL_FDCAN_IsTxBufferMessagePending      : Check if a transmission request is pending on the selected Tx buffer
+      (+) HAL_FDCAN_GetRxFifoFillLevel            : Return Rx FIFO fill level
+      (+) HAL_FDCAN_GetTxFifoFreeLevel            : Return Tx FIFO free level
+      (+) HAL_FDCAN_IsRestrictedOperationMode     : Check if the FDCAN peripheral entered Restricted Operation Mode
+      (+) HAL_FDCAN_ExitRestrictedOperationMode   : Exit Restricted Operation Mode
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Start the FDCAN module.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Change FDCAN peripheral state */
+    hfdcan->State = HAL_FDCAN_STATE_BUSY;
+
+    /* Request leave initialisation */
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
+
+    /* Reset the FDCAN ErrorCode */
+    hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Stop the FDCAN module and enable access to configuration registers.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
+  {
+    /* Request initialisation */
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
+
+    /* Wait until the INIT bit into CCCR register is set */
+    while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Reset counter */
+    Counter = 0U;
+
+    /* Exit from Sleep mode */
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
+
+    /* Wait until FDCAN exits sleep mode */
+    while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Enable configuration change */
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE);
+
+    /* Reset Latest Tx FIFO/Queue Request Buffer Index */
+    hfdcan->LatestTxFifoQRequest = 0U;
+
+    /* Change FDCAN peripheral state */
+    hfdcan->State = HAL_FDCAN_STATE_READY;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Add a message to the Tx FIFO/Queue and activate the corresponding transmission request
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure.
+  * @param  pTxData pointer to a buffer containing the payload of the Tx frame.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData)
+{
+  uint32_t PutIndex;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_ID_TYPE(pTxHeader->IdType));
+  if (pTxHeader->IdType == FDCAN_STANDARD_ID)
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x7FFU));
+  }
+  else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x1FFFFFFFU));
+  }
+  assert_param(IS_FDCAN_FRAME_TYPE(pTxHeader->TxFrameType));
+  assert_param(IS_FDCAN_DLC(pTxHeader->DataLength));
+  assert_param(IS_FDCAN_ESI(pTxHeader->ErrorStateIndicator));
+  assert_param(IS_FDCAN_BRS(pTxHeader->BitRateSwitch));
+  assert_param(IS_FDCAN_FDF(pTxHeader->FDFormat));
+  assert_param(IS_FDCAN_EFC(pTxHeader->TxEventFifoControl));
+  assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->MessageMarker, 0xFFU));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
+  {
+    /* Check that the Tx FIFO/Queue has an allocated area into the RAM */
+    if ((hfdcan->Instance->TXBC & FDCAN_TXBC_TFQS) == 0U)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+      return HAL_ERROR;
+    }
+
+    /* Check that the Tx FIFO/Queue is not full */
+    if ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQF) != 0U)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_FULL;
+
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Retrieve the Tx FIFO PutIndex */
+      PutIndex = ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQPI) >> FDCAN_TXFQS_TFQPI_Pos);
+
+      /* Add the message to the Tx FIFO/Queue */
+      FDCAN_CopyMessageToRAM(hfdcan, pTxHeader, pTxData, PutIndex);
+
+      /* Activate the corresponding transmission request */
+      hfdcan->Instance->TXBAR = ((uint32_t)1 << PutIndex);
+
+      /* Store the Latest Tx FIFO/Queue Request Buffer Index */
+      hfdcan->LatestTxFifoQRequest = ((uint32_t)1 << PutIndex);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Add a message to a dedicated Tx buffer
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure.
+  * @param  pTxData pointer to a buffer containing the payload of the Tx frame.
+  * @param  BufferIndex index of the buffer to be configured.
+  *         This parameter can be a value of @arg FDCAN_Tx_location.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxBuffer(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex)
+{
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_ID_TYPE(pTxHeader->IdType));
+  if (pTxHeader->IdType == FDCAN_STANDARD_ID)
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x7FFU));
+  }
+  else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x1FFFFFFFU));
+  }
+  assert_param(IS_FDCAN_FRAME_TYPE(pTxHeader->TxFrameType));
+  assert_param(IS_FDCAN_DLC(pTxHeader->DataLength));
+  assert_param(IS_FDCAN_ESI(pTxHeader->ErrorStateIndicator));
+  assert_param(IS_FDCAN_BRS(pTxHeader->BitRateSwitch));
+  assert_param(IS_FDCAN_FDF(pTxHeader->FDFormat));
+  assert_param(IS_FDCAN_EFC(pTxHeader->TxEventFifoControl));
+  assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->MessageMarker, 0xFFU));
+  assert_param(IS_FDCAN_TX_LOCATION(BufferIndex));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Check that the selected buffer has an allocated area into the RAM */
+    if (POSITION_VAL(BufferIndex) >= ((hfdcan->Instance->TXBC & FDCAN_TXBC_NDTB) >> FDCAN_TXBC_NDTB_Pos))
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+      return HAL_ERROR;
+    }
+
+    /* Check that there is no transmittion request pending for the selected buffer */
+    if ((hfdcan->Instance->TXBRP & BufferIndex) != 0U)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING;
+
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Add the message to the Tx buffer */
+      FDCAN_CopyMessageToRAM(hfdcan, pTxHeader, pTxData, POSITION_VAL(BufferIndex));
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable transmission request.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  BufferIndex buffer index.
+  *         This parameter can be any combination of @arg FDCAN_Tx_location.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_EnableTxBufferRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
+  {
+    /* Add transmission request */
+    hfdcan->Instance->TXBAR = BufferIndex;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get Tx buffer index of latest Tx FIFO/Queue request
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval Tx buffer index of last Tx FIFO/Queue request
+  *          - Any value of @arg FDCAN_Tx_location if Tx request has been submitted.
+  *          - 0 if no Tx FIFO/Queue request have been submitted.
+  */
+uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Return Last Tx FIFO/Queue Request Buffer */
+  return hfdcan->LatestTxFifoQRequest;
+}
+
+/**
+  * @brief  Abort transmission request
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  BufferIndex buffer index.
+  *         This parameter can be any combination of @arg FDCAN_Tx_location.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
+  {
+    /* Add cancellation request */
+    hfdcan->Instance->TXBCR = BufferIndex;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get an FDCAN frame from the Rx Buffer/FIFO zone into the message RAM.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  RxLocation Location of the received message to be read.
+  *         This parameter can be a value of @arg FDCAN_Rx_location.
+  * @param  pRxHeader pointer to a FDCAN_RxHeaderTypeDef structure.
+  * @param  pRxData pointer to a buffer where the payload of the Rx frame will be stored.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData)
+{
+  uint32_t *RxAddress;
+  uint8_t  *pData;
+  uint32_t ByteCounter;
+  uint32_t GetIndex = 0;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  if (state == HAL_FDCAN_STATE_BUSY)
+  {
+    if (RxLocation == FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */
+    {
+      /* Check that the Rx FIFO 0 has an allocated area into the RAM */
+      if ((hfdcan->Instance->RXF0C & FDCAN_RXF0C_F0S) == 0U)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+        return HAL_ERROR;
+      }
+
+      /* Check that the Rx FIFO 0 is not empty */
+      if ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0FL) == 0U)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
+
+        return HAL_ERROR;
+      }
+      else
+      {
+        /* Calculate Rx FIFO 0 element address */
+        GetIndex = ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0GI) >> FDCAN_RXF0S_F0GI_Pos);
+        RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO0SA + (GetIndex * hfdcan->Init.RxFifo0ElmtSize * 4U));
+      }
+    }
+    else if (RxLocation == FDCAN_RX_FIFO1) /* Rx element is assigned to the Rx FIFO 1 */
+    {
+      /* Check that the Rx FIFO 1 has an allocated area into the RAM */
+      if ((hfdcan->Instance->RXF1C & FDCAN_RXF1C_F1S) == 0U)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+        return HAL_ERROR;
+      }
+
+      /* Check that the Rx FIFO 0 is not empty */
+      if ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL) == 0U)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
+
+        return HAL_ERROR;
+      }
+      else
+      {
+        /* Calculate Rx FIFO 1 element address */
+        GetIndex = ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1GI) >> FDCAN_RXF1S_F1GI_Pos);
+        RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO1SA + (GetIndex * hfdcan->Init.RxFifo1ElmtSize * 4U));
+      }
+    }
+    else /* Rx element is assigned to a dedicated Rx buffer */
+    {
+      /* Check that the selected buffer has an allocated area into the RAM */
+      if (RxLocation >= hfdcan->Init.RxBuffersNbr)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+        return HAL_ERROR;
+      }
+      else
+      {
+        /* Calculate Rx buffer address */
+        RxAddress = (uint32_t *)(hfdcan->msgRam.RxBufferSA + (RxLocation * hfdcan->Init.RxBufferSize * 4U));
+      }
+    }
+
+    /* Retrieve IdType */
+    pRxHeader->IdType = *RxAddress & FDCAN_ELEMENT_MASK_XTD;
+
+    /* Retrieve Identifier */
+    if (pRxHeader->IdType == FDCAN_STANDARD_ID) /* Standard ID element */
+    {
+      pRxHeader->Identifier = ((*RxAddress & FDCAN_ELEMENT_MASK_STDID) >> 18);
+    }
+    else /* Extended ID element */
+    {
+      pRxHeader->Identifier = (*RxAddress & FDCAN_ELEMENT_MASK_EXTID);
+    }
+
+    /* Retrieve RxFrameType */
+    pRxHeader->RxFrameType = (*RxAddress & FDCAN_ELEMENT_MASK_RTR);
+
+    /* Retrieve ErrorStateIndicator */
+    pRxHeader->ErrorStateIndicator = (*RxAddress & FDCAN_ELEMENT_MASK_ESI);
+
+    /* Increment RxAddress pointer to second word of Rx FIFO element */
+    RxAddress++;
+
+    /* Retrieve RxTimestamp */
+    pRxHeader->RxTimestamp = (*RxAddress & FDCAN_ELEMENT_MASK_TS);
+
+    /* Retrieve DataLength */
+    pRxHeader->DataLength = (*RxAddress & FDCAN_ELEMENT_MASK_DLC);
+
+    /* Retrieve BitRateSwitch */
+    pRxHeader->BitRateSwitch = (*RxAddress & FDCAN_ELEMENT_MASK_BRS);
+
+    /* Retrieve FDFormat */
+    pRxHeader->FDFormat = (*RxAddress & FDCAN_ELEMENT_MASK_FDF);
+
+    /* Retrieve FilterIndex */
+    pRxHeader->FilterIndex = ((*RxAddress & FDCAN_ELEMENT_MASK_FIDX) >> 24);
+
+    /* Retrieve NonMatchingFrame */
+    pRxHeader->IsFilterMatchingFrame = ((*RxAddress & FDCAN_ELEMENT_MASK_ANMF) >> 31);
+
+    /* Increment RxAddress pointer to payload of Rx FIFO element */
+    RxAddress++;
+
+    /* Retrieve Rx payload */
+    pData = (uint8_t *)RxAddress;
+    for (ByteCounter = 0; ByteCounter < DLCtoBytes[pRxHeader->DataLength >> 16]; ByteCounter++)
+    {
+      pRxData[ByteCounter] = pData[ByteCounter];
+    }
+
+    if (RxLocation == FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */
+    {
+      /* Acknowledge the Rx FIFO 0 that the oldest element is read so that it increments the GetIndex */
+      hfdcan->Instance->RXF0A = GetIndex;
+    }
+    else if (RxLocation == FDCAN_RX_FIFO1) /* Rx element is assigned to the Rx FIFO 1 */
+    {
+      /* Acknowledge the Rx FIFO 1 that the oldest element is read so that it increments the GetIndex */
+      hfdcan->Instance->RXF1A = GetIndex;
+    }
+    else /* Rx element is assigned to a dedicated Rx buffer */
+    {
+      /* Clear the New Data flag of the current Rx buffer */
+      if (RxLocation < FDCAN_RX_BUFFER32)
+      {
+        hfdcan->Instance->NDAT1 = ((uint32_t)1 << RxLocation);
+      }
+      else /* FDCAN_RX_BUFFER32 <= RxLocation <= FDCAN_RX_BUFFER63 */
+      {
+        hfdcan->Instance->NDAT2 = ((uint32_t)1 << (RxLocation & 0x1FU));
+      }
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  pTxEvent pointer to a FDCAN_TxEventFifoTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent)
+{
+  uint32_t *TxEventAddress;
+  uint32_t GetIndex;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_MIN_VALUE(hfdcan->Init.TxEventsNbr, 1U));
+
+  if (state == HAL_FDCAN_STATE_BUSY)
+  {
+    /* Check that the Tx Event FIFO has an allocated area into the RAM */
+    if ((hfdcan->Instance->TXEFC & FDCAN_TXEFC_EFS) == 0U)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+      return HAL_ERROR;
+    }
+
+    /* Check that the Tx event FIFO is not empty */
+    if ((hfdcan->Instance->TXEFS & FDCAN_TXEFS_EFFL) == 0U)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
+
+      return HAL_ERROR;
+    }
+
+    /* Calculate Tx event FIFO element address */
+    GetIndex = ((hfdcan->Instance->TXEFS & FDCAN_TXEFS_EFGI) >> FDCAN_TXEFS_EFGI_Pos);
+    TxEventAddress = (uint32_t *)(hfdcan->msgRam.TxEventFIFOSA + (GetIndex * 2U * 4U));
+
+    /* Retrieve IdType */
+    pTxEvent->IdType = *TxEventAddress & FDCAN_ELEMENT_MASK_XTD;
+
+    /* Retrieve Identifier */
+    if (pTxEvent->IdType == FDCAN_STANDARD_ID) /* Standard ID element */
+    {
+      pTxEvent->Identifier = ((*TxEventAddress & FDCAN_ELEMENT_MASK_STDID) >> 18U);
+    }
+    else /* Extended ID element */
+    {
+      pTxEvent->Identifier = (*TxEventAddress & FDCAN_ELEMENT_MASK_EXTID);
+    }
+
+    /* Retrieve RxFrameType */
+    pTxEvent->TxFrameType = (*TxEventAddress & FDCAN_ELEMENT_MASK_RTR);
+
+    /* Retrieve ErrorStateIndicator */
+    pTxEvent->ErrorStateIndicator = (*TxEventAddress & FDCAN_ELEMENT_MASK_ESI);
+
+    /* Increment TxEventAddress pointer to second word of Tx Event FIFO element */
+    TxEventAddress++;
+
+    /* Retrieve RxTimestamp */
+    pTxEvent->TxTimestamp = (*TxEventAddress & FDCAN_ELEMENT_MASK_TS);
+
+    /* Retrieve DataLength */
+    pTxEvent->DataLength = (*TxEventAddress & FDCAN_ELEMENT_MASK_DLC);
+
+    /* Retrieve BitRateSwitch */
+    pTxEvent->BitRateSwitch = (*TxEventAddress & FDCAN_ELEMENT_MASK_BRS);
+
+    /* Retrieve FDFormat */
+    pTxEvent->FDFormat = (*TxEventAddress & FDCAN_ELEMENT_MASK_FDF);
+
+    /* Retrieve EventType */
+    pTxEvent->EventType = (*TxEventAddress & FDCAN_ELEMENT_MASK_ET);
+
+    /* Retrieve MessageMarker */
+    pTxEvent->MessageMarker = ((*TxEventAddress & FDCAN_ELEMENT_MASK_MM) >> 24);
+
+    /* Acknowledge the Tx Event FIFO that the oldest element is read so that it increments the GetIndex */
+    hfdcan->Instance->TXEFA = GetIndex;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get high priority message status.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  HpMsgStatus pointer to an FDCAN_HpMsgStatusTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus)
+{
+  HpMsgStatus->FilterList = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FLST) >> FDCAN_HPMS_FLST_Pos);
+  HpMsgStatus->FilterIndex = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FIDX) >> FDCAN_HPMS_FIDX_Pos);
+  HpMsgStatus->MessageStorage = (hfdcan->Instance->HPMS & FDCAN_HPMS_MSI);
+  HpMsgStatus->MessageIndex = (hfdcan->Instance->HPMS & FDCAN_HPMS_BIDX);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get protocol status.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  ProtocolStatus pointer to an FDCAN_ProtocolStatusTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus)
+{
+  uint32_t StatusReg;
+
+  /* Read the protocol status register */
+  StatusReg = READ_REG(hfdcan->Instance->PSR);
+
+  /* Fill the protocol status structure */
+  ProtocolStatus->LastErrorCode = (StatusReg & FDCAN_PSR_LEC);
+  ProtocolStatus->DataLastErrorCode = ((StatusReg & FDCAN_PSR_DLEC) >> FDCAN_PSR_DLEC_Pos);
+  ProtocolStatus->Activity = (StatusReg & FDCAN_PSR_ACT);
+  ProtocolStatus->ErrorPassive = ((StatusReg & FDCAN_PSR_EP) >> FDCAN_PSR_EP_Pos);
+  ProtocolStatus->Warning = ((StatusReg & FDCAN_PSR_EW) >> FDCAN_PSR_EW_Pos);
+  ProtocolStatus->BusOff = ((StatusReg & FDCAN_PSR_BO) >> FDCAN_PSR_BO_Pos);
+  ProtocolStatus->RxESIflag = ((StatusReg & FDCAN_PSR_RESI) >> FDCAN_PSR_RESI_Pos);
+  ProtocolStatus->RxBRSflag = ((StatusReg & FDCAN_PSR_RBRS) >> FDCAN_PSR_RBRS_Pos);
+  ProtocolStatus->RxFDFflag = ((StatusReg & FDCAN_PSR_REDL) >> FDCAN_PSR_REDL_Pos);
+  ProtocolStatus->ProtocolException = ((StatusReg & FDCAN_PSR_PXE) >> FDCAN_PSR_PXE_Pos);
+  ProtocolStatus->TDCvalue = ((StatusReg & FDCAN_PSR_TDCV) >> FDCAN_PSR_TDCV_Pos);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get error counter values.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  ErrorCounters pointer to an FDCAN_ErrorCountersTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters)
+{
+  uint32_t CountersReg;
+
+  /* Read the error counters register */
+  CountersReg = READ_REG(hfdcan->Instance->ECR);
+
+  /* Fill the error counters structure */
+  ErrorCounters->TxErrorCnt = ((CountersReg & FDCAN_ECR_TEC) >> FDCAN_ECR_TEC_Pos);
+  ErrorCounters->RxErrorCnt = ((CountersReg & FDCAN_ECR_REC) >> FDCAN_ECR_REC_Pos);
+  ErrorCounters->RxErrorPassive = ((CountersReg & FDCAN_ECR_RP) >> FDCAN_ECR_RP_Pos);
+  ErrorCounters->ErrorLogging = ((CountersReg & FDCAN_ECR_CEL) >> FDCAN_ECR_CEL_Pos);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Check if a new message is received in the selected Rx buffer.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  RxBufferIndex Rx buffer index.
+  *         This parameter must be a number between 0 and 63.
+  * @retval Status
+  *          - 0 : No new message on RxBufferIndex.
+  *          - 1 : New message received on RxBufferIndex.
+  */
+uint32_t HAL_FDCAN_IsRxBufferMessageAvailable(FDCAN_HandleTypeDef *hfdcan, uint32_t RxBufferIndex)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_MAX_VALUE(RxBufferIndex, 63U));
+  uint32_t NewData1 = hfdcan->Instance->NDAT1;
+  uint32_t NewData2 = hfdcan->Instance->NDAT2;
+
+  /* Check new message reception on the selected buffer */
+  if (((RxBufferIndex < 32U) && ((NewData1 & (uint32_t)((uint32_t)1 << RxBufferIndex)) == 0U)) ||
+      ((RxBufferIndex >= 32U) && ((NewData2 & (uint32_t)((uint32_t)1 << (RxBufferIndex & 0x1FU))) == 0U)))
+  {
+    return 0;
+  }
+
+  /* Clear the New Data flag of the current Rx buffer */
+  if (RxBufferIndex < 32U)
+  {
+    hfdcan->Instance->NDAT1 = ((uint32_t)1 << RxBufferIndex);
+  }
+  else /* 32 <= RxBufferIndex <= 63 */
+  {
+    hfdcan->Instance->NDAT2 = ((uint32_t)1 << (RxBufferIndex & 0x1FU));
+  }
+
+  return 1;
+}
+
+/**
+  * @brief  Check if a transmission request is pending on the selected Tx buffer.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TxBufferIndex Tx buffer index.
+  *         This parameter can be any combination of @arg FDCAN_Tx_location.
+  * @retval Status
+  *          - 0 : No pending transmission request on TxBufferIndex.
+  *          - 1 : Pending transmission request on TxBufferIndex.
+  */
+uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex)
+{
+  /* Check pending transmittion request on the selected buffer */
+  if ((hfdcan->Instance->TXBRP & TxBufferIndex) == 0U)
+  {
+    return 0;
+  }
+  return 1;
+}
+
+/**
+  * @brief  Return Rx FIFO fill level.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  RxFifo Rx FIFO.
+  *         This parameter can be one of the following values:
+  *           @arg FDCAN_RX_FIFO0: Rx FIFO 0
+  *           @arg FDCAN_RX_FIFO1: Rx FIFO 1
+  * @retval Level Rx FIFO fill level.
+  */
+uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo)
+{
+  uint32_t FillLevel;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_RX_FIFO(RxFifo));
+
+  if (RxFifo == FDCAN_RX_FIFO0)
+  {
+    FillLevel = hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0FL;
+  }
+  else /* RxFifo == FDCAN_RX_FIFO1 */
+  {
+    FillLevel = hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL;
+  }
+
+  /* Return Rx FIFO fill level */
+  return FillLevel;
+}
+
+/**
+  * @brief  Return Tx FIFO free level: number of consecutive free Tx FIFO
+  *         elements starting from Tx FIFO GetIndex.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval Level Tx FIFO free level.
+  */
+uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t FreeLevel;
+
+  FreeLevel = hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFFL;
+
+  /* Return Tx FIFO free level */
+  return FreeLevel;
+}
+
+/**
+  * @brief  Check if the FDCAN peripheral entered Restricted Operation Mode.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval Status
+  *          - 0 : Normal FDCAN operation.
+  *          - 1 : Restricted Operation Mode active.
+  */
+uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t OperationMode;
+
+  /* Get Operation Mode */
+  OperationMode = ((hfdcan->Instance->CCCR & FDCAN_CCCR_ASM) >> FDCAN_CCCR_ASM_Pos);
+
+  return OperationMode;
+}
+
+/**
+  * @brief  Exit Restricted Operation Mode.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Exit Restricted Operation mode */
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Exported_Functions_Group4 TT Configuration and control functions
+ *  @brief    TT Configuration and control functions
+ *
+@verbatim
+  ==============================================================================
+              ##### TT Configuration and control functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) HAL_FDCAN_TT_ConfigOperation                  : Initialize TT operation parameters
+      (+) HAL_FDCAN_TT_ConfigReferenceMessage           : Configure the reference message
+      (+) HAL_FDCAN_TT_ConfigTrigger                    : Configure the FDCAN trigger
+      (+) HAL_FDCAN_TT_SetGlobalTime                    : Schedule global time adjustment
+      (+) HAL_FDCAN_TT_SetClockSynchronization          : Schedule TUR numerator update
+      (+) HAL_FDCAN_TT_ConfigStopWatch                  : Configure stop watch source and polarity
+      (+) HAL_FDCAN_TT_ConfigRegisterTimeMark           : Configure register time mark pulse generation
+        (+) HAL_FDCAN_TT_EnableRegisterTimeMarkPulse      : Enable register time mark pulse generation
+        (+) HAL_FDCAN_TT_DisableRegisterTimeMarkPulse     : Disable register time mark pulse generation
+      (+) HAL_FDCAN_TT_EnableTriggerTimeMarkPulse       : Enable trigger time mark pulse generation
+      (+) HAL_FDCAN_TT_DisableTriggerTimeMarkPulse      : Disable trigger time mark pulse generation
+      (+) HAL_FDCAN_TT_EnableHardwareGapControl         : Enable gap control by input pin fdcan1_evt
+      (+) HAL_FDCAN_TT_DisableHardwareGapControl        : Disable gap control by input pin fdcan1_evt
+      (+) HAL_FDCAN_TT_EnableTimeMarkGapControl         : Enable gap control (finish only) by register time mark interrupt
+      (+) HAL_FDCAN_TT_DisableTimeMarkGapControl        : Disable gap control by register time mark interrupt
+      (+) HAL_FDCAN_TT_SetNextIsGap                     : Transmit next reference message with Next_is_Gap = "1"
+      (+) HAL_FDCAN_TT_SetEndOfGap                      : Finish a Gap by requesting start of reference message
+      (+) HAL_FDCAN_TT_ConfigExternalSyncPhase          : Configure target phase used for external synchronization
+        (+) HAL_FDCAN_TT_EnableExternalSynchronization    : Synchronize the phase of the FDCAN schedule to an external schedule
+        (+) HAL_FDCAN_TT_DisableExternalSynchronization   : Disable external schedule synchronization
+      (+) HAL_FDCAN_TT_GetOperationStatus               : Get TT operation status
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize TT operation parameters.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  pTTParams pointer to a FDCAN_TT_ConfigTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigOperation(FDCAN_HandleTypeDef *hfdcan, FDCAN_TT_ConfigTypeDef *pTTParams)
+{
+  uint32_t tickstart;
+  uint32_t RAMcounter;
+  uint32_t StartAddress;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_TUR_NUMERATOR(pTTParams->TURNumerator));
+  assert_param(IS_FDCAN_TT_TUR_DENOMINATOR(pTTParams->TURDenominator));
+  assert_param(IS_FDCAN_TT_TIME_MASTER(pTTParams->TimeMaster));
+  assert_param(IS_FDCAN_MAX_VALUE(pTTParams->SyncDevLimit, 7U));
+  assert_param(IS_FDCAN_MAX_VALUE(pTTParams->InitRefTrigOffset, 127U));
+  assert_param(IS_FDCAN_MAX_VALUE(pTTParams->TriggerMemoryNbr, 64U));
+  assert_param(IS_FDCAN_TT_CYCLE_START_SYNC(pTTParams->CycleStartSync));
+  assert_param(IS_FDCAN_TT_STOP_WATCH_TRIGGER(pTTParams->StopWatchTrigSel));
+  assert_param(IS_FDCAN_TT_EVENT_TRIGGER(pTTParams->EventTrigSel));
+  if (pTTParams->TimeMaster == FDCAN_TT_POTENTIAL_MASTER)
+  {
+    assert_param(IS_FDCAN_TT_BASIC_CYCLES_NUMBER(pTTParams->BasicCyclesNbr));
+  }
+  if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL0)
+  {
+    assert_param(IS_FDCAN_TT_OPERATION(pTTParams->GapEnable));
+    assert_param(IS_FDCAN_MAX_VALUE(pTTParams->AppWdgLimit, 255U));
+    assert_param(IS_FDCAN_TT_EVENT_TRIGGER_POLARITY(pTTParams->EvtTrigPolarity));
+    assert_param(IS_FDCAN_TT_TX_ENABLE_WINDOW(pTTParams->TxEnableWindow));
+    assert_param(IS_FDCAN_MAX_VALUE(pTTParams->ExpTxTrigNbr, 4095U));
+  }
+  if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL1)
+  {
+    assert_param(IS_FDCAN_TT_TUR_LEVEL_0_2(pTTParams->TURNumerator, pTTParams->TURDenominator));
+    assert_param(IS_FDCAN_TT_EXTERNAL_CLK_SYNC(pTTParams->ExternalClkSync));
+    assert_param(IS_FDCAN_TT_GLOBAL_TIME_FILTERING(pTTParams->GlobalTimeFilter));
+    assert_param(IS_FDCAN_TT_AUTO_CLK_CALIBRATION(pTTParams->ClockCalibration));
+  }
+  else
+  {
+    assert_param(IS_FDCAN_TT_TUR_LEVEL_1(pTTParams->TURNumerator, pTTParams->TURDenominator));
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Stop local time in order to enable write access to the other bits of TURCF register */
+    CLEAR_BIT(hfdcan->ttcan->TURCF, FDCAN_TURCF_ELT);
+
+    /* Get tick */
+    tickstart = HAL_GetTick();
+
+    /* Wait until the ELT bit into TURCF register is reset */
+    while ((hfdcan->ttcan->TURCF & FDCAN_TURCF_ELT) != 0U)
+    {
+      /* Check for the Timeout */
+      if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+    }
+
+    /* Configure TUR (Time Unit Ratio) */
+    MODIFY_REG(hfdcan->ttcan->TURCF,
+               (FDCAN_TURCF_NCL | FDCAN_TURCF_DC),
+               (((pTTParams->TURNumerator - 0x10000U) << FDCAN_TURCF_NCL_Pos) | (pTTParams->TURDenominator << FDCAN_TURCF_DC_Pos)));
+
+    /* Enable local time */
+    SET_BIT(hfdcan->ttcan->TURCF, FDCAN_TURCF_ELT);
+
+    /* Configure TT operation */
+    MODIFY_REG(hfdcan->ttcan->TTOCF,
+               (FDCAN_TTOCF_OM | FDCAN_TTOCF_TM | FDCAN_TTOCF_LDSDL | FDCAN_TTOCF_IRTO),
+               (pTTParams->OperationMode                           | \
+                pTTParams->TimeMaster                              | \
+                (pTTParams->SyncDevLimit << FDCAN_TTOCF_LDSDL_Pos) | \
+                (pTTParams->InitRefTrigOffset << FDCAN_TTOCF_IRTO_Pos)));
+    if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      MODIFY_REG(hfdcan->ttcan->TTOCF,
+                 (FDCAN_TTOCF_GEN | FDCAN_TTOCF_AWL | FDCAN_TTOCF_EVTP),
+                 (pTTParams->GapEnable                            | \
+                  (pTTParams->AppWdgLimit << FDCAN_TTOCF_AWL_Pos) | \
+                  pTTParams->EvtTrigPolarity));
+    }
+    if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL1)
+    {
+      MODIFY_REG(hfdcan->ttcan->TTOCF,
+                 (FDCAN_TTOCF_EECS | FDCAN_TTOCF_EGTF | FDCAN_TTOCF_ECC),
+                 (pTTParams->ExternalClkSync  | \
+                  pTTParams->GlobalTimeFilter | \
+                  pTTParams->ClockCalibration));
+    }
+
+    /* Configure system matrix limits */
+    MODIFY_REG(hfdcan->ttcan->TTMLM, FDCAN_TTMLM_CSS, pTTParams->CycleStartSync);
+    if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      MODIFY_REG(hfdcan->ttcan->TTMLM,
+                 (FDCAN_TTMLM_TXEW | FDCAN_TTMLM_ENTT),
+                 (((pTTParams->TxEnableWindow - 1U) << FDCAN_TTMLM_TXEW_Pos) | (pTTParams->ExpTxTrigNbr << FDCAN_TTMLM_ENTT_Pos)));
+    }
+    if (pTTParams->TimeMaster == FDCAN_TT_POTENTIAL_MASTER)
+    {
+      MODIFY_REG(hfdcan->ttcan->TTMLM, FDCAN_TTMLM_CCM, pTTParams->BasicCyclesNbr);
+    }
+
+    /* Configure input triggers: Stop watch and Event */
+    MODIFY_REG(hfdcan->ttcan->TTTS,
+               (FDCAN_TTTS_SWTSEL | FDCAN_TTTS_EVTSEL),
+               (pTTParams->StopWatchTrigSel | pTTParams->EventTrigSel));
+
+    /* Configure trigger memory start address */
+    StartAddress = (hfdcan->msgRam.EndAddress - SRAMCAN_BASE) / 4U;
+    MODIFY_REG(hfdcan->ttcan->TTTMC, FDCAN_TTTMC_TMSA, (StartAddress << FDCAN_TTTMC_TMSA_Pos));
+
+    /* Trigger memory elements number */
+    MODIFY_REG(hfdcan->ttcan->TTTMC, FDCAN_TTTMC_TME, (pTTParams->TriggerMemoryNbr << FDCAN_TTTMC_TME_Pos));
+
+    /* Recalculate End Address */
+    hfdcan->msgRam.TTMemorySA = hfdcan->msgRam.EndAddress;
+    hfdcan->msgRam.EndAddress = hfdcan->msgRam.TTMemorySA + (pTTParams->TriggerMemoryNbr * 2U * 4U);
+
+    if (hfdcan->msgRam.EndAddress > FDCAN_MESSAGE_RAM_END_ADDRESS) /* Last address of the Message RAM */
+    {
+      /* Update error code.
+         Message RAM overflow */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Flush the allocated Message RAM area */
+      for (RAMcounter = hfdcan->msgRam.TTMemorySA; RAMcounter < hfdcan->msgRam.EndAddress; RAMcounter += 4U)
+      {
+        *(uint32_t *)(RAMcounter) = 0x00000000;
+      }
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the reference message.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  IdType Identifier Type.
+  *         This parameter can be a value of @arg FDCAN_id_type.
+  * @param  Identifier Reference Identifier.
+  *         This parameter must be a number between:
+  *           - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+  *           - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID
+  * @param  Payload Enable or disable the additional payload.
+  *         This parameter can be a value of @arg FDCAN_TT_Reference_Message_Payload.
+  *         This parameter is ignored in case of time slaves.
+  *         If this parameter is set to FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD, the
+  *         following elements are taken from Tx Buffer 0:
+  *          - MessageMarker
+  *          - TxEventFifoControl
+  *          - DataLength
+  *          - Data Bytes (payload):
+  *             - bytes 2-8, for Level 1
+  *             - bytes 5-8, for Level 0 and Level 2
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigReferenceMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t IdType, uint32_t Identifier, uint32_t Payload)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_ID_TYPE(IdType));
+  if (IdType == FDCAN_STANDARD_ID)
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(Identifier, 0x7FFU));
+  }
+  else /* IdType == FDCAN_EXTENDED_ID */
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(Identifier, 0x1FFFFFFFU));
+  }
+  assert_param(IS_FDCAN_TT_REFERENCE_MESSAGE_PAYLOAD(Payload));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Configure reference message identifier type, identifier and payload */
+    if (IdType == FDCAN_EXTENDED_ID)
+    {
+      MODIFY_REG(hfdcan->ttcan->TTRMC, (FDCAN_TTRMC_RID | FDCAN_TTRMC_XTD | FDCAN_TTRMC_RMPS), (Payload | IdType | Identifier));
+    }
+    else /* IdType == FDCAN_STANDARD_ID */
+    {
+      MODIFY_REG(hfdcan->ttcan->TTRMC, (FDCAN_TTRMC_RID | FDCAN_TTRMC_XTD | FDCAN_TTRMC_RMPS), (Payload | IdType | (Identifier << 18)));
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the FDCAN trigger according to the specified
+  *         parameters in the FDCAN_TriggerTypeDef structure.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  sTriggerConfig pointer to an FDCAN_TriggerTypeDef structure that
+  *         contains the trigger configuration information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigTrigger(FDCAN_HandleTypeDef *hfdcan, FDCAN_TriggerTypeDef *sTriggerConfig)
+{
+  uint32_t CycleCode;
+  uint32_t MessageNumber;
+  uint32_t TriggerElementW1;
+  uint32_t TriggerElementW2;
+  uint32_t *TriggerAddress;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->TriggerIndex, 63U));
+  assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->TimeMark, 0xFFFFU));
+  assert_param(IS_FDCAN_TT_REPEAT_FACTOR(sTriggerConfig->RepeatFactor));
+  if (sTriggerConfig->RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE)
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->StartCycle, (sTriggerConfig->RepeatFactor - 1U)));
+  }
+  assert_param(IS_FDCAN_TT_TM_EVENT_INTERNAL(sTriggerConfig->TmEventInt));
+  assert_param(IS_FDCAN_TT_TM_EVENT_EXTERNAL(sTriggerConfig->TmEventExt));
+  assert_param(IS_FDCAN_TT_TRIGGER_TYPE(sTriggerConfig->TriggerType));
+  assert_param(IS_FDCAN_ID_TYPE(sTriggerConfig->FilterType));
+  if ((sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_SINGLE) ||
+      (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_CONTINUOUS) ||
+      (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_ARBITRATION) ||
+      (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_MERGED))
+  {
+    assert_param(IS_FDCAN_TX_LOCATION(sTriggerConfig->TxBufferIndex));
+  }
+  if (sTriggerConfig->TriggerType == FDCAN_TT_RX_TRIGGER)
+  {
+    if (sTriggerConfig->FilterType == FDCAN_STANDARD_ID)
+    {
+      assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->FilterIndex, 63U));
+    }
+    else /* sTriggerConfig->FilterType == FDCAN_EXTENDED_ID */
+    {
+      assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->FilterIndex, 127U));
+    }
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Calculate cycle code */
+    if (sTriggerConfig->RepeatFactor == FDCAN_TT_REPEAT_EVERY_CYCLE)
+    {
+      CycleCode = FDCAN_TT_REPEAT_EVERY_CYCLE;
+    }
+    else /* sTriggerConfig->RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE */
+    {
+      CycleCode = sTriggerConfig->RepeatFactor + sTriggerConfig->StartCycle;
+    }
+
+    /* Build first word of trigger element */
+    TriggerElementW1 = ((sTriggerConfig->TimeMark << 16) | \
+                        (CycleCode << 8)                 | \
+                        sTriggerConfig->TmEventInt       | \
+                        sTriggerConfig->TmEventExt       | \
+                        sTriggerConfig->TriggerType);
+
+    /* Select message number depending on trigger type (transmission or reception) */
+    if (sTriggerConfig->TriggerType == FDCAN_TT_RX_TRIGGER)
+    {
+      MessageNumber = sTriggerConfig->FilterIndex;
+    }
+    else if ((sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_SINGLE) ||
+             (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_CONTINUOUS) ||
+             (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_ARBITRATION) ||
+             (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_MERGED))
+    {
+      MessageNumber = POSITION_VAL(sTriggerConfig->TxBufferIndex);
+    }
+    else
+    {
+      MessageNumber = 0U;
+    }
+
+    /* Build second word of trigger element */
+    TriggerElementW2 = ((sTriggerConfig->FilterType >> 7) | (MessageNumber << 16));
+
+    /* Calculate trigger address */
+    TriggerAddress = (uint32_t *)(hfdcan->msgRam.TTMemorySA + (sTriggerConfig->TriggerIndex * 4U * 2U));
+
+    /* Write trigger element to the message RAM */
+    *TriggerAddress = TriggerElementW1;
+    TriggerAddress++;
+    *TriggerAddress = TriggerElementW2;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Schedule global time adjustment for the next reference message.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TimePreset time preset value.
+  *         This parameter must be a number between:
+  *           - 0x0000 and 0x7FFF, Next_Master_Ref_Mark = Current_Master_Ref_Mark + TimePreset
+  *           or
+  *           - 0x8001 and 0xFFFF, Next_Master_Ref_Mark = Current_Master_Ref_Mark - (0x10000 - TimePreset)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_SetGlobalTime(FDCAN_HandleTypeDef *hfdcan, uint32_t TimePreset)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_TIME_PRESET(TimePreset));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Check that the external clock synchronization is enabled */
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_EECS) != FDCAN_TTOCF_EECS)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+
+    /* Check that no global time preset is pending */
+    if ((hfdcan->ttcan->TTOST & FDCAN_TTOST_WGTD) == FDCAN_TTOST_WGTD)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING;
+
+      return HAL_ERROR;
+    }
+
+    /* Configure time preset */
+    MODIFY_REG(hfdcan->ttcan->TTGTP, FDCAN_TTGTP_TP, (TimePreset << FDCAN_TTGTP_TP_Pos));
+
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Schedule time preset to take effect by the next reference message */
+    SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_SGT);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Schedule TUR numerator update for the next reference message.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  NewTURNumerator new value of the TUR numerator.
+  *         This parameter must be a number between 0x10000 and 0x1FFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_SetClockSynchronization(FDCAN_HandleTypeDef *hfdcan, uint32_t NewTURNumerator)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_TUR_NUMERATOR(NewTURNumerator));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Check that the external clock synchronization is enabled */
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_EECS) != FDCAN_TTOCF_EECS)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+
+    /* Check that no external clock synchronization is pending */
+    if ((hfdcan->ttcan->TTOST & FDCAN_TTOST_WECS) == FDCAN_TTOST_WECS)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING;
+
+      return HAL_ERROR;
+    }
+
+    /* Configure new TUR numerator */
+    MODIFY_REG(hfdcan->ttcan->TURCF, FDCAN_TURCF_NCL, (NewTURNumerator - 0x10000U));
+
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Schedule TUR numerator update by the next reference message */
+    SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_ECS);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure stop watch source and polarity.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  Source stop watch source.
+  *         This parameter can be a value of @arg FDCAN_TT_stop_watch_source.
+  * @param  Polarity stop watch polarity.
+  *         This parameter can be a value of @arg FDCAN_TT_stop_watch_polarity.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigStopWatch(FDCAN_HandleTypeDef *hfdcan, uint32_t Source, uint32_t Polarity)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_STOP_WATCH_SOURCE(Source));
+  assert_param(IS_FDCAN_TT_STOP_WATCH_POLARITY(Polarity));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Select stop watch source and polarity */
+    MODIFY_REG(hfdcan->ttcan->TTOCN, (FDCAN_TTOCN_SWS | FDCAN_TTOCN_SWP), (Source | Polarity));
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure register time mark pulse generation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TimeMarkSource time mark source.
+  *         This parameter can be a value of @arg FDCAN_TT_time_mark_source.
+  * @param  TimeMarkValue time mark value (reference).
+  *         This parameter must be a number between 0 and 0xFFFF.
+  * @param  RepeatFactor repeat factor of the cycle for which the time mark is valid.
+  *         This parameter can be a value of @arg FDCAN_TT_Repeat_Factor.
+  * @param  StartCycle index of the first cycle in which the time mark becomes valid.
+  *         This parameter is ignored if RepeatFactor is set to FDCAN_TT_REPEAT_EVERY_CYCLE.
+  *         This parameter must be a number between 0 and RepeatFactor.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigRegisterTimeMark(FDCAN_HandleTypeDef *hfdcan,
+                                                      uint32_t TimeMarkSource, uint32_t TimeMarkValue,
+                                                      uint32_t RepeatFactor, uint32_t StartCycle)
+{
+  uint32_t Counter = 0U;
+  uint32_t CycleCode;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_REGISTER_TIME_MARK_SOURCE(TimeMarkSource));
+  assert_param(IS_FDCAN_MAX_VALUE(TimeMarkValue, 0xFFFFU));
+  assert_param(IS_FDCAN_TT_REPEAT_FACTOR(RepeatFactor));
+  if (RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE)
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(StartCycle, (RepeatFactor - 1U)));
+  }
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Disable the time mark compare function */
+    CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMC);
+
+    if (TimeMarkSource != FDCAN_TT_REG_TIMEMARK_DIABLED)
+    {
+      /* Calculate cycle code */
+      if (RepeatFactor == FDCAN_TT_REPEAT_EVERY_CYCLE)
+      {
+        CycleCode = FDCAN_TT_REPEAT_EVERY_CYCLE;
+      }
+      else /* RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE */
+      {
+        CycleCode = RepeatFactor + StartCycle;
+      }
+
+      Counter = 0U;
+
+      /* Wait until the LCKM bit into TTTMK register is reset */
+      while ((hfdcan->ttcan->TTTMK & FDCAN_TTTMK_LCKM) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_VALUE)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Configure time mark value and cycle code */
+      hfdcan->ttcan->TTTMK = ((TimeMarkValue << FDCAN_TTTMK_TM_Pos) | (CycleCode << FDCAN_TTTMK_TICC_Pos));
+
+      Counter = 0U;
+
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_VALUE)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Update the register time mark compare source */
+      MODIFY_REG(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMC, TimeMarkSource);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable register time mark pulse generation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Enable Register Time Mark Interrupt output on fdcan1_rtp */
+    SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_RTIE);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable register time mark pulse generation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Disable Register Time Mark Interrupt output on fdcan1_rtp */
+    CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_RTIE);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable trigger time mark pulse generation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_VALUE)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Enable Trigger Time Mark Interrupt output on fdcan1_tmp */
+      SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TTIE);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable trigger time mark pulse generation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_VALUE)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Disable Trigger Time Mark Interrupt output on fdcan1_rtp */
+      CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TTIE);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable gap control by input pin fdcan1_evt.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_VALUE)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Enable gap control by pin fdcan1_evt */
+      SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_GCS);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable gap control by input pin fdcan1_evt.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_VALUE)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Disable gap control by pin fdcan1_evt */
+      CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_GCS);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable gap control (finish only) by register time mark interrupt.
+  *         The next register time mark interrupt (TTIR.RTMI = "1") will finish
+  *         the Gap and start the reference message.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_VALUE)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Enable gap control by register time mark interrupt */
+      SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMG);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable gap control by register time mark interrupt.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_VALUE)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Disable gap control by register time mark interrupt */
+      CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMG);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Transmit next reference message with Next_is_Gap = "1".
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_SetNextIsGap(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Check that the node is configured for external event-synchronized TT operation */
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_GEN) != FDCAN_TTOCF_GEN)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_VALUE)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Set Next is Gap */
+      SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_NIG);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Finish a Gap by requesting start of reference message.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_SetEndOfGap(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Check that the node is configured for external event-synchronized TT operation */
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_GEN) != FDCAN_TTOCF_GEN)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_VALUE)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Set Finish Gap */
+      SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_FGP);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure target phase used for external synchronization by event
+  *         trigger input pin fdcan1_evt.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TargetPhase defines target value of cycle time when a rising edge
+  *         of fdcan1_evt is expected.
+  *         This parameter must be a number between 0 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigExternalSyncPhase(FDCAN_HandleTypeDef *hfdcan, uint32_t TargetPhase)
+{
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_MAX_VALUE(TargetPhase, 0xFFFFU));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Check that no external schedule synchronization is pending */
+    if ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_ESCN) == FDCAN_TTOCN_ESCN)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING;
+
+      return HAL_ERROR;
+    }
+
+    /* Configure cycle time target phase */
+    MODIFY_REG(hfdcan->ttcan->TTGTP, FDCAN_TTGTP_CTP, (TargetPhase << FDCAN_TTGTP_CTP_Pos));
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Synchronize the phase of the FDCAN schedule to an external schedule
+  *         using event trigger input pin fdcan1_evt.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Enable external synchronization */
+    SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_ESCN);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable external schedule synchronization.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Disable external synchronization */
+    CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_ESCN);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get TT operation status.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TTOpStatus pointer to an FDCAN_TTOperationStatusTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_GetOperationStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_TTOperationStatusTypeDef *TTOpStatus)
+{
+  uint32_t TTStatusReg;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  /* Read the TT operation status register */
+  TTStatusReg = READ_REG(hfdcan->ttcan->TTOST);
+
+  /* Fill the TT operation status structure */
+  TTOpStatus->ErrorLevel = (TTStatusReg & FDCAN_TTOST_EL);
+  TTOpStatus->MasterState = (TTStatusReg & FDCAN_TTOST_MS);
+  TTOpStatus->SyncState = (TTStatusReg & FDCAN_TTOST_SYS);
+  TTOpStatus->GTimeQuality = ((TTStatusReg & FDCAN_TTOST_QGTP) >> FDCAN_TTOST_QGTP_Pos);
+  TTOpStatus->ClockQuality = ((TTStatusReg & FDCAN_TTOST_QCS) >> FDCAN_TTOST_QCS_Pos);
+  TTOpStatus->RefTrigOffset = ((TTStatusReg & FDCAN_TTOST_RTO) >> FDCAN_TTOST_RTO_Pos);
+  TTOpStatus->GTimeDiscPending = ((TTStatusReg & FDCAN_TTOST_WGTD) >> FDCAN_TTOST_WGTD_Pos);
+  TTOpStatus->GapFinished = ((TTStatusReg & FDCAN_TTOST_GFI) >> FDCAN_TTOST_GFI_Pos);
+  TTOpStatus->MasterPriority = ((TTStatusReg & FDCAN_TTOST_TMP) >> FDCAN_TTOST_TMP_Pos);
+  TTOpStatus->GapStarted = ((TTStatusReg & FDCAN_TTOST_GSI) >> FDCAN_TTOST_GSI_Pos);
+  TTOpStatus->WaitForEvt = ((TTStatusReg & FDCAN_TTOST_WFE) >> FDCAN_TTOST_WFE_Pos);
+  TTOpStatus->AppWdgEvt = ((TTStatusReg & FDCAN_TTOST_AWE) >> FDCAN_TTOST_AWE_Pos);
+  TTOpStatus->ECSPending = ((TTStatusReg & FDCAN_TTOST_WECS) >> FDCAN_TTOST_WECS_Pos);
+  TTOpStatus->PhaseLock = ((TTStatusReg & FDCAN_TTOST_SPL) >> FDCAN_TTOST_SPL_Pos);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Exported_Functions_Group5 Interrupts management
+ *  @brief    Interrupts management
+ *
+@verbatim
+  ==============================================================================
+                       ##### Interrupts management #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) HAL_FDCAN_ConfigInterruptLines      : Assign interrupts to either Interrupt line 0 or 1
+      (+) HAL_FDCAN_TT_ConfigInterruptLines   : Assign TT interrupts to either Interrupt line 0 or 1
+      (+) HAL_FDCAN_ActivateNotification      : Enable interrupts
+      (+) HAL_FDCAN_DeactivateNotification    : Disable interrupts
+      (+) HAL_FDCAN_TT_ActivateNotification   : Enable TT interrupts
+      (+) HAL_FDCAN_TT_DeactivateNotification : Disable TT interrupts
+      (+) HAL_FDCAN_IRQHandler                : Handles FDCAN interrupt request
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Assign interrupts to either Interrupt line 0 or 1.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  ITList indicates which interrupts will be assigned to the selected interrupt line.
+  *         This parameter can be any combination of @arg FDCAN_Interrupts.
+  * @param  InterruptLine Interrupt line.
+  *         This parameter can be a value of @arg FDCAN_Interrupt_Line.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine)
+{
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_IT(ITList));
+  assert_param(IS_FDCAN_IT_LINE(InterruptLine));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Assign list of interrupts to the selected line */
+    if (InterruptLine == FDCAN_INTERRUPT_LINE0)
+    {
+      CLEAR_BIT(hfdcan->Instance->ILS, ITList);
+    }
+    else /* InterruptLine == FDCAN_INTERRUPT_LINE1 */
+    {
+      SET_BIT(hfdcan->Instance->ILS, ITList);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Assign TT interrupts to either Interrupt line 0 or 1.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TTITList indicates which interrupts will be assigned to the selected interrupt line.
+  *         This parameter can be any combination of @arg FDCAN_TTInterrupts.
+  * @param  InterruptLine Interrupt line.
+  *         This parameter can be a value of @arg FDCAN_Interrupt_Line.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t TTITList, uint32_t InterruptLine)
+{
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_IT(TTITList));
+  assert_param(IS_FDCAN_IT_LINE(InterruptLine));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Assign list of interrupts to the selected line */
+    if (InterruptLine == FDCAN_INTERRUPT_LINE0)
+    {
+      CLEAR_BIT(hfdcan->ttcan->TTILS, TTITList);
+    }
+    else /* InterruptLine == FDCAN_INTERRUPT_LINE1 */
+    {
+      SET_BIT(hfdcan->ttcan->TTILS, TTITList);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable interrupts.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  ActiveITs indicates which interrupts will be enabled.
+  *         This parameter can be any combination of @arg FDCAN_Interrupts.
+  * @param  BufferIndexes Tx Buffer Indexes.
+  *         This parameter can be any combination of @arg FDCAN_Tx_location.
+  *         This parameter is ignored if ActiveITs does not include one of the following:
+  *           - FDCAN_IT_TX_COMPLETE
+  *           - FDCAN_IT_TX_ABORT_COMPLETE
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes)
+{
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_IT(ActiveITs));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Enable Interrupt lines */
+    if ((ActiveITs & hfdcan->Instance->ILS) == 0U)
+    {
+      /* Enable Interrupt line 0 */
+      SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
+    }
+    else if ((ActiveITs & hfdcan->Instance->ILS) == ActiveITs)
+    {
+      /* Enable Interrupt line 1 */
+      SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
+    }
+    else
+    {
+      /* Enable Interrupt lines 0 and 1 */
+      hfdcan->Instance->ILE = (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1);
+    }
+
+    if ((ActiveITs & FDCAN_IT_TX_COMPLETE) != 0U)
+    {
+      /* Enable Tx Buffer Transmission Interrupt to set TC flag in IR register,
+         but interrupt will only occure if TC is enabled in IE register */
+      SET_BIT(hfdcan->Instance->TXBTIE, BufferIndexes);
+    }
+
+    if ((ActiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != 0U)
+    {
+      /* Enable Tx Buffer Cancellation Finished Interrupt to set TCF flag in IR register,
+         but interrupt will only occure if TCF is enabled in IE register */
+      SET_BIT(hfdcan->Instance->TXBCIE, BufferIndexes);
+    }
+
+    /* Enable the selected interrupts */
+    __HAL_FDCAN_ENABLE_IT(hfdcan, ActiveITs);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable interrupts.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  InactiveITs indicates which interrupts will be disabled.
+  *         This parameter can be any combination of @arg FDCAN_Interrupts.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs)
+{
+  uint32_t ITLineSelection;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_IT(InactiveITs));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Disable the selected interrupts */
+    __HAL_FDCAN_DISABLE_IT(hfdcan, InactiveITs);
+
+    if ((InactiveITs & FDCAN_IT_TX_COMPLETE) != 0U)
+    {
+      /* Disable Tx Buffer Transmission Interrupts */
+      CLEAR_REG(hfdcan->Instance->TXBTIE);
+    }
+
+    if ((InactiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != 0U)
+    {
+      /* Disable Tx Buffer Cancellation Finished Interrupt */
+      CLEAR_REG(hfdcan->Instance->TXBCIE);
+    }
+
+    ITLineSelection = hfdcan->Instance->ILS;
+
+    if ((hfdcan->Instance->IE | ITLineSelection) == ITLineSelection)
+    {
+      /* Disable Interrupt line 0 */
+      CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
+    }
+
+    if ((hfdcan->Instance->IE & ITLineSelection) == 0U)
+    {
+      /* Disable Interrupt line 1 */
+      CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable TT interrupts.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  ActiveTTITs indicates which TT interrupts will be enabled.
+  *         This parameter can be any combination of @arg FDCAN_TTInterrupts.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveTTITs)
+{
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_IT(ActiveTTITs));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Enable Interrupt lines */
+    if ((ActiveTTITs & hfdcan->ttcan->TTILS) == 0U)
+    {
+      /* Enable Interrupt line 0 */
+      SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
+    }
+    else if ((ActiveTTITs & hfdcan->ttcan->TTILS) == ActiveTTITs)
+    {
+      /* Enable Interrupt line 1 */
+      SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
+    }
+    else
+    {
+      /* Enable Interrupt lines 0 and 1 */
+      hfdcan->Instance->ILE = (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1);
+    }
+
+    /* Enable the selected TT interrupts */
+    __HAL_FDCAN_TT_ENABLE_IT(hfdcan, ActiveTTITs);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable TT interrupts.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  InactiveTTITs indicates which TT interrupts will be disabled.
+  *         This parameter can be any combination of @arg FDCAN_TTInterrupts.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveTTITs)
+{
+  uint32_t ITLineSelection;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_IT(InactiveTTITs));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Disable the selected TT interrupts */
+    __HAL_FDCAN_TT_DISABLE_IT(hfdcan, InactiveTTITs);
+
+    ITLineSelection = hfdcan->ttcan->TTILS;
+
+    if ((hfdcan->ttcan->TTIE | ITLineSelection) == ITLineSelection)
+    {
+      /* Disable Interrupt line 0 */
+      CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
+    }
+
+    if ((hfdcan->ttcan->TTIE & ITLineSelection) == 0U)
+    {
+      /* Disable Interrupt line 1 */
+      CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Handles FDCAN interrupt request.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t ClkCalibrationITs;
+  uint32_t TxEventFifoITs;
+  uint32_t RxFifo0ITs;
+  uint32_t RxFifo1ITs;
+  uint32_t Errors;
+  uint32_t ErrorStatusITs;
+  uint32_t TransmittedBuffers;
+  uint32_t AbortedBuffers;
+  uint32_t TTSchedSyncITs;
+  uint32_t TTTimeMarkITs;
+  uint32_t TTGlobTimeITs;
+  uint32_t TTDistErrors;
+  uint32_t TTFatalErrors;
+  uint32_t SWTime;
+  uint32_t SWCycleCount;
+
+  ClkCalibrationITs = (FDCAN_CCU->IR << 30);
+  ClkCalibrationITs &= (FDCAN_CCU->IE << 30);
+  TxEventFifoITs = hfdcan->Instance->IR & FDCAN_TX_EVENT_FIFO_MASK;
+  TxEventFifoITs &= hfdcan->Instance->IE;
+  RxFifo0ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO0_MASK;
+  RxFifo0ITs &= hfdcan->Instance->IE;
+  RxFifo1ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO1_MASK;
+  RxFifo1ITs &= hfdcan->Instance->IE;
+  Errors = hfdcan->Instance->IR & FDCAN_ERROR_MASK;
+  Errors &= hfdcan->Instance->IE;
+  ErrorStatusITs = hfdcan->Instance->IR & FDCAN_ERROR_STATUS_MASK;
+  ErrorStatusITs &= hfdcan->Instance->IE;
+
+  /* High Priority Message interrupt management *******************************/
+  if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RX_HIGH_PRIORITY_MSG) != 0U)
+  {
+    if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG) != 0U)
+    {
+      /* Clear the High Priority Message flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->HighPriorityMessageCallback(hfdcan);
+#else
+      /* High Priority Message Callback */
+      HAL_FDCAN_HighPriorityMessageCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Transmission Abort interrupt management **********************************/
+  if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_ABORT_COMPLETE) != 0U)
+  {
+    if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE) != 0U)
+    {
+      /* List of aborted monitored buffers */
+      AbortedBuffers = hfdcan->Instance->TXBCF;
+      AbortedBuffers &= hfdcan->Instance->TXBCIE;
+
+      /* Clear the Transmission Cancellation flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->TxBufferAbortCallback(hfdcan, AbortedBuffers);
+#else
+      /* Transmission Cancellation Callback */
+      HAL_FDCAN_TxBufferAbortCallback(hfdcan, AbortedBuffers);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Clock calibration unit interrupts management *****************************/
+  if (ClkCalibrationITs != 0U)
+  {
+    /* Clear the Clock Calibration flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, ClkCalibrationITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->ClockCalibrationCallback(hfdcan, ClkCalibrationITs);
+#else
+    /* Clock Calibration Callback */
+    HAL_FDCAN_ClockCalibrationCallback(hfdcan, ClkCalibrationITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+
+  /* Tx event FIFO interrupts management **************************************/
+  if (TxEventFifoITs != 0U)
+  {
+    /* Clear the Tx Event FIFO flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, TxEventFifoITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->TxEventFifoCallback(hfdcan, TxEventFifoITs);
+#else
+    /* Tx Event FIFO Callback */
+    HAL_FDCAN_TxEventFifoCallback(hfdcan, TxEventFifoITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+
+  /* Rx FIFO 0 interrupts management ******************************************/
+  if (RxFifo0ITs != 0U)
+  {
+    /* Clear the Rx FIFO 0 flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo0ITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->RxFifo0Callback(hfdcan, RxFifo0ITs);
+#else
+    /* Rx FIFO 0 Callback */
+    HAL_FDCAN_RxFifo0Callback(hfdcan, RxFifo0ITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+
+  /* Rx FIFO 1 interrupts management ******************************************/
+  if (RxFifo1ITs != 0U)
+  {
+    /* Clear the Rx FIFO 1 flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo1ITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->RxFifo1Callback(hfdcan, RxFifo1ITs);
+#else
+    /* Rx FIFO 1 Callback */
+    HAL_FDCAN_RxFifo1Callback(hfdcan, RxFifo1ITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+
+  /* Tx FIFO empty interrupt management ***************************************/
+  if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_FIFO_EMPTY) != 0U)
+  {
+    if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY) != 0U)
+    {
+      /* Clear the Tx FIFO empty flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->TxFifoEmptyCallback(hfdcan);
+#else
+      /* Tx FIFO empty Callback */
+      HAL_FDCAN_TxFifoEmptyCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Transmission Complete interrupt management *******************************/
+  if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_COMPLETE) != 0U)
+  {
+    if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_COMPLETE) != 0U)
+    {
+      /* List of transmitted monitored buffers */
+      TransmittedBuffers = hfdcan->Instance->TXBTO;
+      TransmittedBuffers &= hfdcan->Instance->TXBTIE;
+
+      /* Clear the Transmission Complete flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_COMPLETE);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->TxBufferCompleteCallback(hfdcan, TransmittedBuffers);
+#else
+      /* Transmission Complete Callback */
+      HAL_FDCAN_TxBufferCompleteCallback(hfdcan, TransmittedBuffers);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Rx Buffer New Message interrupt management *******************************/
+  if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RX_BUFFER_NEW_MESSAGE) != 0U)
+  {
+    if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE) != 0U)
+    {
+      /* Clear the Rx Buffer New Message flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->RxBufferNewMessageCallback(hfdcan);
+#else
+      /* Rx Buffer New Message Callback */
+      HAL_FDCAN_RxBufferNewMessageCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Timestamp Wraparound interrupt management ********************************/
+  if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TIMESTAMP_WRAPAROUND) != 0U)
+  {
+    if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND) != 0U)
+    {
+      /* Clear the Timestamp Wraparound flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->TimestampWraparoundCallback(hfdcan);
+#else
+      /* Timestamp Wraparound Callback */
+      HAL_FDCAN_TimestampWraparoundCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Timeout Occurred interrupt management ************************************/
+  if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TIMEOUT_OCCURRED) != 0U)
+  {
+    if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED) != 0U)
+    {
+      /* Clear the Timeout Occurred flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->TimeoutOccurredCallback(hfdcan);
+#else
+      /* Timeout Occurred Callback */
+      HAL_FDCAN_TimeoutOccurredCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Message RAM access failure interrupt management **************************/
+  if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RAM_ACCESS_FAILURE) != 0U)
+  {
+    if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE) != 0U)
+    {
+      /* Clear the Message RAM access failure flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE);
+
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_RAM_ACCESS;
+    }
+  }
+
+  /* Error Status interrupts management ***************************************/
+  if (ErrorStatusITs != 0U)
+  {
+    /* Clear the Error flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, ErrorStatusITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->ErrorStatusCallback(hfdcan, ErrorStatusITs);
+#else
+    /* Error Status Callback */
+    HAL_FDCAN_ErrorStatusCallback(hfdcan, ErrorStatusITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+
+  /* Error interrupts management **********************************************/
+  if (Errors != 0U)
+  {
+    /* Clear the Error flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, Errors);
+
+    /* Update error code */
+    hfdcan->ErrorCode |= Errors;
+  }
+
+  if (hfdcan->Instance == FDCAN1)
+  {
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != 0U)
+    {
+      TTSchedSyncITs = hfdcan->ttcan->TTIR & FDCAN_TT_SCHEDULE_SYNC_MASK;
+      TTSchedSyncITs &= hfdcan->ttcan->TTIE;
+      TTTimeMarkITs = hfdcan->ttcan->TTIR & FDCAN_TT_TIME_MARK_MASK;
+      TTTimeMarkITs &= hfdcan->ttcan->TTIE;
+      TTGlobTimeITs = hfdcan->ttcan->TTIR & FDCAN_TT_GLOBAL_TIME_MASK;
+      TTGlobTimeITs &= hfdcan->ttcan->TTIE;
+      TTDistErrors = hfdcan->ttcan->TTIR & FDCAN_TT_DISTURBING_ERROR_MASK;
+      TTDistErrors &= hfdcan->ttcan->TTIE;
+      TTFatalErrors = hfdcan->ttcan->TTIR & FDCAN_TT_FATAL_ERROR_MASK;
+      TTFatalErrors &= hfdcan->ttcan->TTIE;
+
+      /* TT Schedule Synchronization interrupts management **********************/
+      if (TTSchedSyncITs != 0U)
+      {
+        /* Clear the TT Schedule Synchronization flags */
+        __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTSchedSyncITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+        /* Call registered callback*/
+        hfdcan->TT_ScheduleSyncCallback(hfdcan, TTSchedSyncITs);
+#else
+        /* TT Schedule Synchronization Callback */
+        HAL_FDCAN_TT_ScheduleSyncCallback(hfdcan, TTSchedSyncITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+      }
+
+      /* TT Time Mark interrupts management *************************************/
+      if (TTTimeMarkITs != 0U)
+      {
+        /* Clear the TT Time Mark flags */
+        __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTTimeMarkITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+        /* Call registered callback*/
+        hfdcan->TT_TimeMarkCallback(hfdcan, TTTimeMarkITs);
+#else
+        /* TT Time Mark Callback */
+        HAL_FDCAN_TT_TimeMarkCallback(hfdcan, TTTimeMarkITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+      }
+
+      /* TT Stop Watch interrupt management *************************************/
+      if (__HAL_FDCAN_TT_GET_IT_SOURCE(hfdcan, FDCAN_TT_IT_STOP_WATCH) != 0U)
+      {
+        if (__HAL_FDCAN_TT_GET_FLAG(hfdcan, FDCAN_TT_FLAG_STOP_WATCH) != 0U)
+        {
+          /* Retrieve Stop watch Time and Cycle count */
+          SWTime = ((hfdcan->ttcan->TTCPT & FDCAN_TTCPT_SWV) >> FDCAN_TTCPT_SWV_Pos);
+          SWCycleCount = ((hfdcan->ttcan->TTCPT & FDCAN_TTCPT_CCV) >> FDCAN_TTCPT_CCV_Pos);
+
+          /* Clear the TT Stop Watch flag */
+          __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, FDCAN_TT_FLAG_STOP_WATCH);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+          /* Call registered callback*/
+          hfdcan->TT_StopWatchCallback(hfdcan, SWTime, SWCycleCount);
+#else
+          /* TT Stop Watch Callback */
+          HAL_FDCAN_TT_StopWatchCallback(hfdcan, SWTime, SWCycleCount);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+        }
+      }
+
+      /* TT Global Time interrupts management ***********************************/
+      if (TTGlobTimeITs != 0U)
+      {
+        /* Clear the TT Global Time flags */
+        __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTGlobTimeITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+        /* Call registered callback*/
+        hfdcan->TT_GlobalTimeCallback(hfdcan, TTGlobTimeITs);
+#else
+        /* TT Global Time Callback */
+        HAL_FDCAN_TT_GlobalTimeCallback(hfdcan, TTGlobTimeITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+      }
+
+      /* TT Disturbing Error interrupts management ******************************/
+      if (TTDistErrors != 0U)
+      {
+        /* Clear the TT Disturbing Error flags */
+        __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTDistErrors);
+
+        /* Update error code */
+        hfdcan->ErrorCode |= TTDistErrors;
+      }
+
+      /* TT Fatal Error interrupts management ***********************************/
+      if (TTFatalErrors != 0U)
+      {
+        /* Clear the TT Fatal Error flags */
+        __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTFatalErrors);
+
+        /* Update error code */
+        hfdcan->ErrorCode |= TTFatalErrors;
+      }
+    }
+  }
+
+  if (hfdcan->ErrorCode != HAL_FDCAN_ERROR_NONE)
+  {
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->ErrorCallback(hfdcan);
+#else
+    /* Error Callback */
+    HAL_FDCAN_ErrorCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Exported_Functions_Group6 Callback functions
+ *  @brief   FDCAN Callback functions
+ *
+@verbatim
+  ==============================================================================
+                          ##### Callback functions #####
+  ==============================================================================
+    [..]
+    This subsection provides the following callback functions:
+      (+) HAL_FDCAN_ClockCalibrationCallback
+      (+) HAL_FDCAN_TxEventFifoCallback
+      (+) HAL_FDCAN_RxFifo0Callback
+      (+) HAL_FDCAN_RxFifo1Callback
+      (+) HAL_FDCAN_TxFifoEmptyCallback
+      (+) HAL_FDCAN_TxBufferCompleteCallback
+      (+) HAL_FDCAN_TxBufferAbortCallback
+      (+) HAL_FDCAN_RxBufferNewMessageCallback
+      (+) HAL_FDCAN_HighPriorityMessageCallback
+      (+) HAL_FDCAN_TimestampWraparoundCallback
+      (+) HAL_FDCAN_TimeoutOccurredCallback
+      (+) HAL_FDCAN_ErrorCallback
+      (+) HAL_FDCAN_ErrorStatusCallback
+      (+) HAL_FDCAN_TT_ScheduleSyncCallback
+      (+) HAL_FDCAN_TT_TimeMarkCallback
+      (+) HAL_FDCAN_TT_StopWatchCallback
+      (+) HAL_FDCAN_TT_GlobalTimeCallback
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Clock Calibration callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  ClkCalibrationITs indicates which Clock Calibration interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_Clock_Calibration_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_ClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(ClkCalibrationITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_ClockCalibrationCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Tx Event callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TxEventFifoITs indicates which Tx Event FIFO interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_Tx_Event_Fifo_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(TxEventFifoITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TxEventFifoCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Rx FIFO 0 callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  RxFifo0ITs indicates which Rx FIFO 0 interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_Rx_Fifo0_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(RxFifo0ITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_RxFifo0Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Rx FIFO 1 callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  RxFifo1ITs indicates which Rx FIFO 1 interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_Rx_Fifo1_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(RxFifo1ITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_RxFifo1Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Tx FIFO Empty callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TxFifoEmptyCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Transmission Complete callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  BufferIndexes Indexes of the transmitted buffers.
+  *         This parameter can be any combination of @arg FDCAN_Tx_location.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(BufferIndexes);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TxBufferCompleteCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Transmission Cancellation callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  BufferIndexes Indexes of the aborted buffers.
+  *         This parameter can be any combination of @arg FDCAN_Tx_location.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(BufferIndexes);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TxBufferAbortCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Rx Buffer New Message callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_RxBufferNewMessageCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_RxBufferNewMessageCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Timestamp Wraparound callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TimestampWraparoundCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Timeout Occurred callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TimeoutOccurredCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  High Priority Message callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_HighPriorityMessageCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Error callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Error status callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  ErrorStatusITs indicates which Error Status interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_Error_Status_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(ErrorStatusITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_ErrorStatusCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  TT Schedule Synchronization callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TTSchedSyncITs indicates which TT Schedule Synchronization interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_TTScheduleSynchronization_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TT_ScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(TTSchedSyncITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TT_ScheduleSyncCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  TT Time Mark callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TTTimeMarkITs indicates which TT Schedule Synchronization interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_TTTimeMark_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TT_TimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(TTTimeMarkITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TT_TimeMarkCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  TT Stop Watch callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  SWTime Time Value captured at the Stop Watch Trigger pin (fdcan1_swt) falling/rising
+  *         edge (as configured via HAL_FDCAN_TTConfigStopWatch).
+  *         This parameter is a number between 0 and 0xFFFF.
+  * @param  SWCycleCount Cycle count value captured together with SWTime.
+  *         This parameter is a number between 0 and 0x3F.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TT_StopWatchCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(SWTime);
+  UNUSED(SWCycleCount);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TT_StopWatchCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  TT Global Time callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TTGlobTimeITs indicates which TT Global Time interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_TTGlobalTime_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TT_GlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(TTGlobTimeITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TT_GlobalTimeCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Exported_Functions_Group7 Peripheral State functions
+ *  @brief   FDCAN Peripheral State functions
+ *
+@verbatim
+  ==============================================================================
+                      ##### Peripheral State functions #####
+  ==============================================================================
+    [..]
+    This subsection provides functions allowing to :
+      (+) HAL_FDCAN_GetState()  : Return the FDCAN state.
+      (+) HAL_FDCAN_GetError()  : Return the FDCAN error code if any.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Return the FDCAN state
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL state
+  */
+HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Return FDCAN state */
+  return hfdcan->State;
+}
+
+/**
+  * @brief  Return the FDCAN error code
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval FDCAN Error Code
+  */
+uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Return FDCAN error code */
+  return hfdcan->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup FDCAN_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Calculate each RAM block start address and size
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+ */
+static HAL_StatusTypeDef FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t RAMcounter;
+  uint32_t StartAddress;
+
+  StartAddress = hfdcan->Init.MessageRAMOffset;
+
+  /* Standard filter list start address */
+  MODIFY_REG(hfdcan->Instance->SIDFC, FDCAN_SIDFC_FLSSA, (StartAddress << FDCAN_SIDFC_FLSSA_Pos));
+
+  /* Standard filter elements number */
+  MODIFY_REG(hfdcan->Instance->SIDFC, FDCAN_SIDFC_LSS, (hfdcan->Init.StdFiltersNbr << FDCAN_SIDFC_LSS_Pos));
+
+  /* Extended filter list start address */
+  StartAddress += hfdcan->Init.StdFiltersNbr;
+  MODIFY_REG(hfdcan->Instance->XIDFC, FDCAN_XIDFC_FLESA, (StartAddress << FDCAN_XIDFC_FLESA_Pos));
+
+  /* Extended filter elements number */
+  MODIFY_REG(hfdcan->Instance->XIDFC, FDCAN_XIDFC_LSE, (hfdcan->Init.ExtFiltersNbr << FDCAN_XIDFC_LSE_Pos));
+
+  /* Rx FIFO 0 start address */
+  StartAddress += (hfdcan->Init.ExtFiltersNbr * 2U);
+  MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0SA, (StartAddress << FDCAN_RXF0C_F0SA_Pos));
+
+  /* Rx FIFO 0 elements number */
+  MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0S, (hfdcan->Init.RxFifo0ElmtsNbr << FDCAN_RXF0C_F0S_Pos));
+
+  /* Rx FIFO 1 start address */
+  StartAddress += (hfdcan->Init.RxFifo0ElmtsNbr * hfdcan->Init.RxFifo0ElmtSize);
+  MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1SA, (StartAddress << FDCAN_RXF1C_F1SA_Pos));
+
+  /* Rx FIFO 1 elements number */
+  MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1S, (hfdcan->Init.RxFifo1ElmtsNbr << FDCAN_RXF1C_F1S_Pos));
+
+  /* Rx buffer list start address */
+  StartAddress += (hfdcan->Init.RxFifo1ElmtsNbr * hfdcan->Init.RxFifo1ElmtSize);
+  MODIFY_REG(hfdcan->Instance->RXBC, FDCAN_RXBC_RBSA, (StartAddress << FDCAN_RXBC_RBSA_Pos));
+
+  /* Tx event FIFO start address */
+  StartAddress += (hfdcan->Init.RxBuffersNbr * hfdcan->Init.RxBufferSize);
+  MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFSA, (StartAddress << FDCAN_TXEFC_EFSA_Pos));
+
+  /* Tx event FIFO elements number */
+  MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFS, (hfdcan->Init.TxEventsNbr << FDCAN_TXEFC_EFS_Pos));
+
+  /* Tx buffer list start address */
+  StartAddress += (hfdcan->Init.TxEventsNbr * 2U);
+  MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_TBSA, (StartAddress << FDCAN_TXBC_TBSA_Pos));
+
+  /* Dedicated Tx buffers number */
+  MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_NDTB, (hfdcan->Init.TxBuffersNbr << FDCAN_TXBC_NDTB_Pos));
+
+  /* Tx FIFO/queue elements number */
+  MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_TFQS, (hfdcan->Init.TxFifoQueueElmtsNbr << FDCAN_TXBC_TFQS_Pos));
+
+  hfdcan->msgRam.StandardFilterSA = SRAMCAN_BASE + (hfdcan->Init.MessageRAMOffset * 4U);
+  hfdcan->msgRam.ExtendedFilterSA = hfdcan->msgRam.StandardFilterSA + (hfdcan->Init.StdFiltersNbr * 4U);
+  hfdcan->msgRam.RxFIFO0SA = hfdcan->msgRam.ExtendedFilterSA + (hfdcan->Init.ExtFiltersNbr * 2U * 4U);
+  hfdcan->msgRam.RxFIFO1SA = hfdcan->msgRam.RxFIFO0SA + (hfdcan->Init.RxFifo0ElmtsNbr * hfdcan->Init.RxFifo0ElmtSize * 4U);
+  hfdcan->msgRam.RxBufferSA = hfdcan->msgRam.RxFIFO1SA + (hfdcan->Init.RxFifo1ElmtsNbr * hfdcan->Init.RxFifo1ElmtSize * 4U);
+  hfdcan->msgRam.TxEventFIFOSA = hfdcan->msgRam.RxBufferSA + (hfdcan->Init.RxBuffersNbr * hfdcan->Init.RxBufferSize * 4U);
+  hfdcan->msgRam.TxBufferSA = hfdcan->msgRam.TxEventFIFOSA + (hfdcan->Init.TxEventsNbr * 2U * 4U);
+  hfdcan->msgRam.TxFIFOQSA = hfdcan->msgRam.TxBufferSA + (hfdcan->Init.TxBuffersNbr * hfdcan->Init.TxElmtSize * 4U);
+
+  hfdcan->msgRam.EndAddress = hfdcan->msgRam.TxFIFOQSA + (hfdcan->Init.TxFifoQueueElmtsNbr * hfdcan->Init.TxElmtSize * 4U);
+
+  if (hfdcan->msgRam.EndAddress > FDCAN_MESSAGE_RAM_END_ADDRESS) /* Last address of the Message RAM */
+  {
+    /* Update error code.
+       Message RAM overflow */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+    /* Change FDCAN state */
+    hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Flush the allocated Message RAM area */
+    for (RAMcounter = hfdcan->msgRam.StandardFilterSA; RAMcounter < hfdcan->msgRam.EndAddress; RAMcounter += 4U)
+    {
+      *(uint32_t *)(RAMcounter) = 0x00000000;
+    }
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Copy Tx message to the message RAM.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure.
+  * @param  pTxData pointer to a buffer containing the payload of the Tx frame.
+  * @param  BufferIndex index of the buffer to be configured.
+  * @retval HAL status
+ */
+static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex)
+{
+  uint32_t TxElementW1;
+  uint32_t TxElementW2;
+  uint32_t *TxAddress;
+  uint32_t ByteCounter;
+
+  /* Build first word of Tx header element */
+  if (pTxHeader->IdType == FDCAN_STANDARD_ID)
+  {
+    TxElementW1 = (pTxHeader->ErrorStateIndicator |
+                   FDCAN_STANDARD_ID |
+                   pTxHeader->TxFrameType |
+                   (pTxHeader->Identifier << 18));
+  }
+  else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
+  {
+    TxElementW1 = (pTxHeader->ErrorStateIndicator |
+                   FDCAN_EXTENDED_ID |
+                   pTxHeader->TxFrameType |
+                   pTxHeader->Identifier);
+  }
+
+  /* Build second word of Tx header element */
+  TxElementW2 = ((pTxHeader->MessageMarker << 24) |
+                 pTxHeader->TxEventFifoControl |
+                 pTxHeader->FDFormat |
+                 pTxHeader->BitRateSwitch |
+                 pTxHeader->DataLength);
+
+  /* Calculate Tx element address */
+  TxAddress = (uint32_t *)(hfdcan->msgRam.TxBufferSA + (BufferIndex * hfdcan->Init.TxElmtSize * 4U));
+
+  /* Write Tx element header to the message RAM */
+  *TxAddress = TxElementW1;
+  TxAddress++;
+  *TxAddress = TxElementW2;
+  TxAddress++;
+
+  /* Write Tx payload to the message RAM */
+  for (ByteCounter = 0; ByteCounter < DLCtoBytes[pTxHeader->DataLength >> 16]; ByteCounter += 4U)
+  {
+    *TxAddress = (((uint32_t)pTxData[ByteCounter + 3U] << 24) |
+                  ((uint32_t)pTxData[ByteCounter + 2U] << 16) |
+                  ((uint32_t)pTxData[ByteCounter + 1U] << 8) |
+                  (uint32_t)pTxData[ByteCounter]);
+    TxAddress++;
+  }
+}
+
+/**
+  * @}
+  */
+#endif /* HAL_FDCAN_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c
new file mode 100644
index 00000000..3a6b651f
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c
@@ -0,0 +1,1099 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_flash.c
+  * @author  MCD Application Team
+  * @brief   FLASH HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the internal FLASH memory:
+  *           + Program operations functions
+  *           + Memory Control functions
+  *           + Peripheral Errors functions
+  *
+ @verbatim
+  ==============================================================================
+                        ##### FLASH peripheral features #####
+  ==============================================================================
+
+  [..] The Flash memory interface manages CPU AXI I-Code and D-Code accesses
+       to the Flash memory. It implements the erase and program Flash memory operations
+       and the read and write protection mechanisms.
+
+  [..] The FLASH main features are:
+      (+) Flash memory read operations
+      (+) Flash memory program/erase operations
+      (+) Read / write protections
+      (+) Option bytes programming
+      (+) Error code correction (ECC) : Data in flash are 266-bits word
+          (10 bits added per flash word)
+
+                        ##### How to use this driver #####
+ ==============================================================================
+    [..]
+      This driver provides functions and macros to configure and program the FLASH
+      memory of all STM32H7xx devices.
+
+      (#) FLASH Memory IO Programming functions:
+           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
+                HAL_FLASH_Lock() functions
+           (++) Program functions: 256-bit word only
+           (++) There Two modes of programming :
+            (+++) Polling mode using HAL_FLASH_Program() function
+            (+++) Interrupt mode using HAL_FLASH_Program_IT() function
+
+      (#) Interrupts and flags management functions :
+           (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
+           (++) Callback functions are called when the flash operations are finished :
+                HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise
+                HAL_FLASH_OperationErrorCallback()
+           (++) Get error flag status by calling HAL_FLASH_GetError()
+
+      (#) Option bytes management functions :
+           (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and
+                HAL_FLASH_OB_Lock() functions
+           (++) Launch the reload of the option bytes using HAL_FLASH_OB_Launch() function.
+                In this case, a reset is generated
+    [..]
+      In addition to these functions, this driver includes a set of macros allowing
+      to handle the following operations:
+       (+) Set the latency
+       (+) Enable/Disable the FLASH interrupts
+       (+) Monitor the FLASH flags status
+     [..]
+    (@) For any Flash memory program operation (erase or program), the CPU clock frequency
+        (HCLK) must be at least 1MHz.
+    (@) The contents of the Flash memory are not guaranteed if a device reset occurs during
+        a Flash memory operation.
+    (@) The application can simultaneously request a read and a write operation through each AXI
+        interface.
+        As the Flash memory is divided into two independent banks, the embedded Flash
+        memory interface can drive different operations at the same time on each bank. For
+        example a read, write or erase operation can be executed on bank 1 while another read,
+        write or erase operation is executed on bank 2.
+
+ @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup FLASH FLASH
+  * @brief FLASH HAL module driver
+  * @{
+  */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup FLASH_Private_Constants
+  * @{
+  */
+#define FLASH_TIMEOUT_VALUE              50000U /* 50 s */
+
+/**
+  * @}
+  */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+FLASH_ProcessTypeDef pFlash;
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup FLASH_Exported_Functions FLASH Exported functions
+  * @{
+  */
+
+/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
+ *  @brief   Programming operation functions
+ *
+@verbatim
+ ===============================================================================
+                  ##### Programming operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the FLASH
+    program operations.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Program flash word at a specified address
+  * @param  TypeProgram Indicate the way to program at a specified address.
+  *         This parameter can be a value of @ref FLASH_Type_Program
+  * @param  FlashAddress specifies the address to be programmed.
+  * @param  DataAddress specifies the address of data to be programmed
+  *
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress)
+{
+  HAL_StatusTypeDef status;
+  __IO uint32_t *dest_addr = (__IO uint32_t *)FlashAddress;
+  __IO uint32_t *src_addr = (__IO uint32_t*)DataAddress;
+  uint32_t bank;
+  uint8_t row_index = FLASH_NB_32BITWORD_IN_FLASHWORD;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+  assert_param(IS_FLASH_PROGRAM_ADDRESS(FlashAddress));
+
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+#if defined (FLASH_OPTCR_PG_OTP)
+  if((IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress)) || (IS_FLASH_PROGRAM_ADDRESS_OTP(FlashAddress)))
+#else
+  if(IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress))
+#endif /* FLASH_OPTCR_PG_OTP */
+  {
+    bank = FLASH_BANK_1;
+  }
+  else
+  {
+    bank = FLASH_BANK_2;
+  }
+
+  /* Reset error code */
+  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, bank);
+
+  if(status == HAL_OK)
+  {
+    if(bank == FLASH_BANK_1)
+    {
+#if defined (FLASH_OPTCR_PG_OTP)
+      if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD)
+      {
+        /* Set OTP_PG bit */
+        SET_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP);
+      }
+      else
+#endif /* FLASH_OPTCR_PG_OTP */
+      {
+        /* Set PG bit */
+        SET_BIT(FLASH->CR1, FLASH_CR_PG);
+      }
+    }
+    else
+    {
+      /* Set PG bit */
+      SET_BIT(FLASH->CR2, FLASH_CR_PG);
+    }
+
+    __ISB();
+    __DSB();
+
+#if defined (FLASH_OPTCR_PG_OTP)
+    if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD)
+    {
+      /* Program an OTP word (16 bits) */
+      *(__IO uint16_t *)FlashAddress = *(__IO uint16_t*)DataAddress;
+    }
+    else
+#endif /* FLASH_OPTCR_PG_OTP */
+    {
+      /* Program the flash word */
+      do
+      {
+        *dest_addr = *src_addr;
+        dest_addr++;
+        src_addr++;
+        row_index--;
+     } while (row_index != 0U);
+    }
+
+    __ISB();
+    __DSB();
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, bank);
+
+#if defined (FLASH_OPTCR_PG_OTP)
+    if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD)
+    {
+      /* If the program operation is completed, disable the OTP_PG */
+      CLEAR_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP);
+    }
+    else
+#endif /* FLASH_OPTCR_PG_OTP */
+    {
+      if(bank == FLASH_BANK_1)
+      {
+        /* If the program operation is completed, disable the PG */
+        CLEAR_BIT(FLASH->CR1, FLASH_CR_PG);
+      }
+      else
+      {
+        /* If the program operation is completed, disable the PG */
+        CLEAR_BIT(FLASH->CR2, FLASH_CR_PG);
+      }
+    }
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(&pFlash);
+
+  return status;
+}
+
+/**
+  * @brief  Program flash words of 256 bits at a specified address with interrupt enabled.
+  * @param  TypeProgram Indicate the way to program at a specified address.
+  *                      This parameter can be a value of @ref FLASH_Type_Program
+  * @param  FlashAddress specifies the address to be programmed.
+  * @param  DataAddress specifies the address of data (256 bits) to be programmed
+  *
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress)
+{
+  HAL_StatusTypeDef status;
+  __IO uint32_t *dest_addr = (__IO uint32_t*)FlashAddress;
+  __IO uint32_t *src_addr = (__IO uint32_t*)DataAddress;
+  uint32_t bank;
+  uint8_t row_index = FLASH_NB_32BITWORD_IN_FLASHWORD;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+  assert_param(IS_FLASH_PROGRAM_ADDRESS(FlashAddress));
+
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Reset error code */
+  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+#if defined (FLASH_OPTCR_PG_OTP)
+  if((IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress)) || (IS_FLASH_PROGRAM_ADDRESS_OTP(FlashAddress)))
+#else
+  if(IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress))
+#endif /* FLASH_OPTCR_PG_OTP */
+  {
+    bank = FLASH_BANK_1;
+  }
+  else
+  {
+    bank = FLASH_BANK_2;
+  }
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, bank);
+
+  if (status != HAL_OK)
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(&pFlash);
+  }
+  else
+  {
+    pFlash.Address = FlashAddress;
+
+    if(bank == FLASH_BANK_1)
+    {
+      /* Set internal variables used by the IRQ handler */
+      pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_BANK1;
+
+#if defined (FLASH_OPTCR_PG_OTP)
+      if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD)
+      {
+        /* Set OTP_PG bit */
+        SET_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP);
+      }
+      else
+#endif /* FLASH_OPTCR_PG_OTP */
+      {
+        /* Set PG bit */
+        SET_BIT(FLASH->CR1, FLASH_CR_PG);
+      }
+
+      /* Enable End of Operation and Error interrupts for Bank 1 */
+#if defined (FLASH_CR_OPERRIE)
+      __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1     | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
+                                  FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1);
+#else
+      __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1     | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
+                                  FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1);
+#endif /* FLASH_CR_OPERRIE */
+    }
+    else
+    {
+      /* Set internal variables used by the IRQ handler */
+      pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_BANK2;
+
+      /* Set PG bit */
+      SET_BIT(FLASH->CR2, FLASH_CR_PG);
+
+      /* Enable End of Operation and Error interrupts for Bank2 */
+#if defined (FLASH_CR_OPERRIE)
+      __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2     | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
+                                  FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2);
+#else
+      __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2     | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
+                                  FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2);
+#endif /* FLASH_CR_OPERRIE */
+    }
+
+    __ISB();
+    __DSB();
+
+#if defined (FLASH_OPTCR_PG_OTP)
+    if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD)
+    {
+      /* Program an OTP word (16 bits) */
+      *(__IO uint16_t *)FlashAddress = *(__IO uint16_t*)DataAddress;
+    }
+    else
+#endif /* FLASH_OPTCR_PG_OTP */
+    {
+      /* Program the flash word */
+      do
+      {
+        *dest_addr = *src_addr;
+        dest_addr++;
+        src_addr++;
+        row_index--;
+      } while (row_index != 0U);
+    }
+
+    __ISB();
+    __DSB();
+  }
+
+  return status;
+}
+
+/**
+  * @brief This function handles FLASH interrupt request.
+  * @retval None
+  */
+void HAL_FLASH_IRQHandler(void)
+{
+  uint32_t temp;
+  uint32_t errorflag;
+  FLASH_ProcedureTypeDef procedure;
+
+  /* Check FLASH Bank1 End of Operation flag  */
+  if(__HAL_FLASH_GET_FLAG_BANK1(FLASH_SR_EOP) != RESET)
+  {
+    if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE_BANK1)
+    {
+      /* Nb of sector to erased can be decreased */
+      pFlash.NbSectorsToErase--;
+
+      /* Check if there are still sectors to erase */
+      if(pFlash.NbSectorsToErase != 0U)
+      {
+        /* Indicate user which sector has been erased */
+        HAL_FLASH_EndOfOperationCallback(pFlash.Sector);
+
+        /* Clear bank 1 End of Operation pending bit */
+        __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1);
+
+        /* Increment sector number */
+        pFlash.Sector++;
+        temp = pFlash.Sector;
+        FLASH_Erase_Sector(temp, FLASH_BANK_1, pFlash.VoltageForErase);
+      }
+      else
+      {
+        /* No more sectors to Erase, user callback can be called */
+        /* Reset Sector and stop Erase sectors procedure */
+        pFlash.Sector = 0xFFFFFFFFU;
+        pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+
+        /* FLASH EOP interrupt user callback */
+        HAL_FLASH_EndOfOperationCallback(pFlash.Sector);
+
+        /* Clear FLASH End of Operation pending bit */
+        __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1);
+      }
+    }
+    else
+    {
+      procedure = pFlash.ProcedureOnGoing;
+
+      if((procedure == FLASH_PROC_MASSERASE_BANK1) || (procedure == FLASH_PROC_ALLBANK_MASSERASE))
+      {
+        /* MassErase ended. Return the selected bank */
+        /* FLASH EOP interrupt user callback */
+        HAL_FLASH_EndOfOperationCallback(FLASH_BANK_1);
+      }
+      else if(procedure == FLASH_PROC_PROGRAM_BANK1)
+      {
+        /* Program ended. Return the selected address */
+        /* FLASH EOP interrupt user callback */
+        HAL_FLASH_EndOfOperationCallback(pFlash.Address);
+      }
+      else
+      {
+        /* Nothing to do */
+      }
+
+      if((procedure != FLASH_PROC_SECTERASE_BANK2) && \
+         (procedure != FLASH_PROC_MASSERASE_BANK2) && \
+         (procedure != FLASH_PROC_PROGRAM_BANK2))
+      {
+        pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+        /* Clear FLASH End of Operation pending bit */
+        __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1);
+      }
+    }
+  }
+
+  /* Check FLASH Bank2 End of Operation flag  */
+  if(__HAL_FLASH_GET_FLAG_BANK2(FLASH_SR_EOP) != RESET)
+  {
+    if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE_BANK2)
+    {
+      /*Nb of sector to erased can be decreased*/
+      pFlash.NbSectorsToErase--;
+
+      /* Check if there are still sectors to erase*/
+      if(pFlash.NbSectorsToErase != 0U)
+      {
+        /*Indicate user which sector has been erased*/
+        HAL_FLASH_EndOfOperationCallback(pFlash.Sector);
+
+        /* Clear bank 2 End of Operation pending bit */
+        __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2);
+
+        /*Increment sector number*/
+        pFlash.Sector++;
+        temp = pFlash.Sector;
+        FLASH_Erase_Sector(temp, FLASH_BANK_2, pFlash.VoltageForErase);
+      }
+      else
+      {
+        /* No more sectors to Erase, user callback can be called */
+        /* Reset Sector and stop Erase sectors procedure */
+        pFlash.Sector = 0xFFFFFFFFU;
+        pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+
+        /* FLASH EOP interrupt user callback */
+        HAL_FLASH_EndOfOperationCallback(pFlash.Sector);
+
+        /* Clear FLASH End of Operation pending bit */
+        __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2);
+      }
+    }
+    else
+    {
+      procedure = pFlash.ProcedureOnGoing;
+
+      if((procedure == FLASH_PROC_MASSERASE_BANK2) || (procedure == FLASH_PROC_ALLBANK_MASSERASE))
+      {
+        /*MassErase ended. Return the selected bank*/
+        /* FLASH EOP interrupt user callback */
+        HAL_FLASH_EndOfOperationCallback(FLASH_BANK_2);
+      }
+      else if(procedure == FLASH_PROC_PROGRAM_BANK2)
+      {
+        /* Program ended. Return the selected address */
+        /* FLASH EOP interrupt user callback */
+        HAL_FLASH_EndOfOperationCallback(pFlash.Address);
+      }
+      else
+      {
+        /* Nothing to do */
+      }
+
+      if((procedure != FLASH_PROC_SECTERASE_BANK1) && \
+         (procedure != FLASH_PROC_MASSERASE_BANK1) && \
+         (procedure != FLASH_PROC_PROGRAM_BANK1))
+      {
+        pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+        /* Clear FLASH End of Operation pending bit */
+        __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2);
+      }
+    }
+  }
+
+  /* Check FLASH Bank1 operation error flags */
+#if defined (FLASH_SR_OPERR)
+  errorflag = FLASH->SR1 & (FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | FLASH_FLAG_STRBERR_BANK1 | \
+                            FLASH_FLAG_INCERR_BANK1 | FLASH_FLAG_OPERR_BANK1);
+#else
+  errorflag = FLASH->SR1 & (FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | FLASH_FLAG_STRBERR_BANK1 | \
+                            FLASH_FLAG_INCERR_BANK1);
+#endif /* FLASH_SR_OPERR */
+
+  if(errorflag != 0U)
+  {
+    /* Save the error code */
+    pFlash.ErrorCode |= errorflag;
+
+    /* Clear error programming flags */
+    __HAL_FLASH_CLEAR_FLAG_BANK1(errorflag);
+
+    procedure = pFlash.ProcedureOnGoing;
+
+    if(procedure == FLASH_PROC_SECTERASE_BANK1)
+    {
+      /* Return the faulty sector */
+      temp = pFlash.Sector;
+      pFlash.Sector = 0xFFFFFFFFU;
+    }
+    else if((procedure == FLASH_PROC_MASSERASE_BANK1) || (procedure == FLASH_PROC_ALLBANK_MASSERASE))
+    {
+      /* Return the faulty bank */
+      temp = FLASH_BANK_1;
+    }
+    else
+    {
+      /* Return the faulty address */
+      temp = pFlash.Address;
+    }
+
+    /* Stop the procedure ongoing*/
+    pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+
+    /* FLASH error interrupt user callback */
+    HAL_FLASH_OperationErrorCallback(temp);
+  }
+
+  /* Check FLASH Bank2 operation error flags */
+#if defined (FLASH_SR_OPERR)
+  errorflag = FLASH->SR2 & ((FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | FLASH_FLAG_STRBERR_BANK2 | \
+                             FLASH_FLAG_INCERR_BANK2 | FLASH_FLAG_OPERR_BANK2) & 0x7FFFFFFFU);
+#else
+  errorflag = FLASH->SR2 & ((FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | FLASH_FLAG_STRBERR_BANK2 | \
+                             FLASH_FLAG_INCERR_BANK2) & 0x7FFFFFFFU);
+#endif /* FLASH_SR_OPERR */
+
+  if(errorflag != 0U)
+  {
+    /* Save the error code */
+    pFlash.ErrorCode |= (errorflag | 0x80000000U);
+
+    /* Clear error programming flags */
+    __HAL_FLASH_CLEAR_FLAG_BANK2(errorflag);
+
+    procedure = pFlash.ProcedureOnGoing;
+
+    if(procedure== FLASH_PROC_SECTERASE_BANK2)
+    {
+      /*return the faulty sector*/
+      temp = pFlash.Sector;
+      pFlash.Sector = 0xFFFFFFFFU;
+    }
+    else if((procedure == FLASH_PROC_MASSERASE_BANK2) || (procedure == FLASH_PROC_ALLBANK_MASSERASE))
+    {
+      /*return the faulty bank*/
+      temp = FLASH_BANK_2;
+    }
+    else
+    {
+      /*return the faulty address*/
+      temp = pFlash.Address;
+    }
+
+    /*Stop the procedure ongoing*/
+    pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+
+    /* FLASH error interrupt user callback */
+    HAL_FLASH_OperationErrorCallback(temp);
+  }
+
+  if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
+  {
+#if defined (FLASH_CR_OPERRIE)
+    /* Disable Bank1 Operation and Error source interrupt */
+    __HAL_FLASH_DISABLE_IT_BANK1(FLASH_IT_EOP_BANK1    | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
+                                 FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1);
+
+    /* Disable Bank2 Operation and Error source interrupt */
+    __HAL_FLASH_DISABLE_IT_BANK2(FLASH_IT_EOP_BANK2    | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
+                                 FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2);
+#else
+    /* Disable Bank1 Operation and Error source interrupt */
+    __HAL_FLASH_DISABLE_IT_BANK1(FLASH_IT_EOP_BANK1    | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
+                                 FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1);
+
+    /* Disable Bank2 Operation and Error source interrupt */
+    __HAL_FLASH_DISABLE_IT_BANK2(FLASH_IT_EOP_BANK2    | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
+                                 FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2);
+#endif /* FLASH_CR_OPERRIE */
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(&pFlash);
+  }
+}
+
+/**
+  * @brief  FLASH end of operation interrupt callback
+  * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure
+  *                  Mass Erase: Bank number which has been requested to erase
+  *                  Sectors Erase: Sector which has been erased
+  *                    (if 0xFFFFFFFF, it means that all the selected sectors have been erased)
+  *                  Program: Address which was selected for data program
+  * @retval None
+  */
+__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(ReturnValue);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  FLASH operation error interrupt callback
+  * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure
+  *                 Mass Erase: Bank number which has been requested to erase
+  *                 Sectors Erase: Sector number which returned an error
+  *                 Program: Address which was selected for data program
+  * @retval None
+  */
+__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(ReturnValue);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FLASH_OperationErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
+ *  @brief   Management functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the FLASH
+    memory operations.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Unlock the FLASH control registers access
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Unlock(void)
+{
+  if(READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != 0U)
+  {
+    /* Authorize the FLASH Bank1 Registers access */
+    WRITE_REG(FLASH->KEYR1, FLASH_KEY1);
+    WRITE_REG(FLASH->KEYR1, FLASH_KEY2);
+
+    /* Verify Flash Bank1 is unlocked */
+    if (READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != 0U)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  if(READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != 0U)
+  {
+    /* Authorize the FLASH Bank2 Registers access */
+    WRITE_REG(FLASH->KEYR2, FLASH_KEY1);
+    WRITE_REG(FLASH->KEYR2, FLASH_KEY2);
+
+    /* Verify Flash Bank2 is unlocked */
+    if (READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != 0U)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Locks the FLASH control registers access
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Lock(void)
+{
+  /* Set the LOCK Bit to lock the FLASH Bank1 Control Register access */
+  SET_BIT(FLASH->CR1, FLASH_CR_LOCK);
+
+  /* Verify Flash Bank1 is locked */
+  if (READ_BIT(FLASH->CR1, FLASH_CR_LOCK) == 0U)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the LOCK Bit to lock the FLASH Bank2 Control Register access */
+  SET_BIT(FLASH->CR2, FLASH_CR_LOCK);
+
+  /* Verify Flash Bank2 is locked */
+  if (READ_BIT(FLASH->CR2, FLASH_CR_LOCK) == 0U)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Unlock the FLASH Option Control Registers access.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
+{
+  if(READ_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK) != 0U)
+  {
+    /* Authorizes the Option Byte registers programming */
+    WRITE_REG(FLASH->OPTKEYR, FLASH_OPT_KEY1);
+    WRITE_REG(FLASH->OPTKEYR, FLASH_OPT_KEY2);
+
+    /* Verify that the Option Bytes are unlocked */
+    if (READ_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK) != 0U)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Lock the FLASH Option Control Registers access.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
+{
+  /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
+  SET_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK);
+
+  /* Verify that the Option Bytes are locked */
+  if (READ_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK) == 0U)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Launch the option bytes loading.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
+{
+  HAL_StatusTypeDef status;
+
+  /* Wait for CRC computation to be completed */
+  if (FLASH_CRC_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK)
+  {
+    status = HAL_ERROR;
+  }
+  else if (FLASH_CRC_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    status = HAL_OK;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Set OPTSTRT Bit */
+    SET_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTSTART);
+
+    /* Wait for OB change operation to be completed */
+    status = FLASH_OB_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+  }
+
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions
+ *  @brief   Peripheral Errors functions
+ *
+@verbatim
+ ===============================================================================
+                ##### Peripheral Errors functions #####
+ ===============================================================================
+    [..]
+    This subsection permits to get in run-time Errors of the FLASH peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Get the specific FLASH error flag.
+  * @retval HAL_FLASH_ERRORCode The returned value can be:
+  *            @arg HAL_FLASH_ERROR_NONE       : No error set
+  *
+  *            @arg HAL_FLASH_ERROR_WRP_BANK1  : Write Protection Error on Bank 1
+  *            @arg HAL_FLASH_ERROR_PGS_BANK1  : Program Sequence Error on Bank 1
+  *            @arg HAL_FLASH_ERROR_STRB_BANK1 : Strobe Error on Bank 1
+  *            @arg HAL_FLASH_ERROR_INC_BANK1  : Inconsistency Error on Bank 1
+  *            @arg HAL_FLASH_ERROR_OPE_BANK1  : Operation Error on Bank 1
+  *            @arg HAL_FLASH_ERROR_RDP_BANK1  : Read Protection Error on Bank 1
+  *            @arg HAL_FLASH_ERROR_RDS_BANK1  : Read Secured Error on Bank 1
+  *            @arg HAL_FLASH_ERROR_SNECC_BANK1: ECC Single Correction Error on Bank 1
+  *            @arg HAL_FLASH_ERROR_DBECC_BANK1: ECC Double Detection Error on Bank 1
+  *            @arg HAL_FLASH_ERROR_CRCRD_BANK1: CRC Read Error on Bank 1
+  *
+  *            @arg HAL_FLASH_ERROR_WRP_BANK2  : Write Protection Error on Bank 2
+  *            @arg HAL_FLASH_ERROR_PGS_BANK2  : Program Sequence Error on Bank 2
+  *            @arg HAL_FLASH_ERROR_STRB_BANK2 : Strobe Error on Bank 2
+  *            @arg HAL_FLASH_ERROR_INC_BANK2  : Inconsistency Error on Bank 2
+  *            @arg HAL_FLASH_ERROR_OPE_BANK2  : Operation Error on Bank 2
+  *            @arg HAL_FLASH_ERROR_RDP_BANK2  : Read Protection Error on Bank 2
+  *            @arg HAL_FLASH_ERROR_RDS_BANK2  : Read Secured Error on Bank 2
+  *            @arg HAL_FLASH_ERROR_SNECC_BANK2: SNECC Error on Bank 2
+  *            @arg HAL_FLASH_ERROR_DBECC_BANK2: Double Detection ECC on Bank 2
+  *            @arg HAL_FLASH_ERROR_CRCRD_BANK2: CRC Read Error on Bank 2
+*/
+
+uint32_t HAL_FLASH_GetError(void)
+{
+   return pFlash.ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @addtogroup FLASH_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Wait for a FLASH operation to complete.
+  * @param  Timeout maximum flash operation timeout
+  * @param  Bank flash FLASH_BANK_1 or FLASH_BANK_2
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout, uint32_t Bank)
+{
+  /* Wait for the FLASH operation to complete by polling on QW flag to be reset.
+     Even if the FLASH operation fails, the QW flag will be reset and an error
+     flag will be set */
+
+  uint32_t bsyflag, errorflag;
+  uint32_t tickstart = HAL_GetTick();
+
+  assert_param(IS_FLASH_BANK_EXCLUSIVE(Bank));
+
+  /* Select bsyflag depending on Bank */
+  if(Bank == FLASH_BANK_1)
+  {
+    bsyflag = FLASH_FLAG_QW_BANK1;
+  }
+  else
+  {
+    bsyflag = FLASH_FLAG_QW_BANK2;
+  }
+
+  while(__HAL_FLASH_GET_FLAG(bsyflag))
+  {
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  /* Get Error Flags */
+  if (Bank == FLASH_BANK_1)
+  {
+    errorflag = FLASH->SR1 & FLASH_FLAG_ALL_ERRORS_BANK1;
+  }
+  else
+  {
+    errorflag = (FLASH->SR2 & FLASH_FLAG_ALL_ERRORS_BANK2) | 0x80000000U;
+  }
+
+  /* In case of error reported in Flash SR1 or SR2 registers (ECCC not managed as an error) */
+  if((errorflag & 0x7DFFFFFFU) != 0U)
+  {
+    /*Save the error code*/
+    pFlash.ErrorCode |= errorflag;
+
+    /* Clear error programming flags */
+    __HAL_FLASH_CLEAR_FLAG(errorflag);
+
+    return HAL_ERROR;
+  }
+
+  /* Check FLASH End of Operation flag  */
+  if(Bank == FLASH_BANK_1)
+  {
+    if (__HAL_FLASH_GET_FLAG_BANK1(FLASH_FLAG_EOP_BANK1))
+    {
+      /* Clear FLASH End of Operation pending bit */
+      __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1);
+    }
+  }
+  else
+  {
+    if (__HAL_FLASH_GET_FLAG_BANK2(FLASH_FLAG_EOP_BANK2))
+    {
+      /* Clear FLASH End of Operation pending bit */
+      __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2);
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Wait for a FLASH Option Bytes change operation to complete.
+  * @param  Timeout maximum flash operation timeout
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef FLASH_OB_WaitForLastOperation(uint32_t Timeout)
+{
+  /* Get timeout */
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Wait for the FLASH Option Bytes change operation to complete by polling on OPT_BUSY flag to be reset */
+  while(READ_BIT(FLASH->OPTSR_CUR, FLASH_OPTSR_OPT_BUSY) != 0U)
+  {
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  /* Check option byte change error */
+  if(READ_BIT(FLASH->OPTSR_CUR, FLASH_OPTSR_OPTCHANGEERR) != 0U)
+  {
+    /* Save the error code */
+    pFlash.ErrorCode |= HAL_FLASH_ERROR_OB_CHANGE;
+
+    /* Clear the OB error flag */
+    FLASH->OPTCCR |= FLASH_OPTCCR_CLR_OPTCHANGEERR;
+
+    return HAL_ERROR;
+  }
+
+  /* If there is no error flag set */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Wait for a FLASH CRC computation to complete.
+  * @param  Timeout maximum flash operation timeout
+  * @param  Bank flash FLASH_BANK_1 or FLASH_BANK_2
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef FLASH_CRC_WaitForLastOperation(uint32_t Timeout, uint32_t Bank)
+{
+  uint32_t bsyflag;
+  uint32_t tickstart = HAL_GetTick();
+
+  assert_param(IS_FLASH_BANK_EXCLUSIVE(Bank));
+
+  /* Select bsyflag depending on Bank */
+  if(Bank == FLASH_BANK_1)
+  {
+    bsyflag = FLASH_FLAG_CRC_BUSY_BANK1;
+  }
+  else
+  {
+    bsyflag = FLASH_FLAG_CRC_BUSY_BANK2;
+  }
+
+  /* Wait for the FLASH CRC computation to complete by polling on CRC_BUSY flag to be reset */
+  while(__HAL_FLASH_GET_FLAG(bsyflag))
+  {
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  /* Check FLASH CRC read error flag  */
+  if(Bank == FLASH_BANK_1)
+  {
+    if (__HAL_FLASH_GET_FLAG_BANK1(FLASH_FLAG_CRCRDERR_BANK1))
+    {
+      /* Save the error code */
+      pFlash.ErrorCode |= HAL_FLASH_ERROR_CRCRD_BANK1;
+
+      /* Clear FLASH CRC read error pending bit */
+      __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_CRCRDERR_BANK1);
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    if (__HAL_FLASH_GET_FLAG_BANK2(FLASH_FLAG_CRCRDERR_BANK2))
+    {
+      /* Save the error code */
+      pFlash.ErrorCode |= HAL_FLASH_ERROR_CRCRD_BANK2;
+
+      /* Clear FLASH CRC read error pending bit */
+      __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_CRCRDERR_BANK2);
+
+      return HAL_ERROR;
+    }
+  }
+
+  /* If there is no error flag set */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c
new file mode 100644
index 00000000..77b809f7
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c
@@ -0,0 +1,1709 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_flash_ex.c
+  * @author  MCD Application Team
+  * @brief   Extended FLASH HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the FLASH extension peripheral:
+  *           + Extended programming operations functions
+  *
+ @verbatim
+ ==============================================================================
+                   ##### Flash Extension features #####
+  ==============================================================================
+
+  [..] Comparing to other previous devices, the FLASH interface for STM32H7xx
+       devices contains the following additional features
+
+       (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
+           capability (RWW)
+       (+) Dual bank memory organization
+       (+) PCROP protection for all banks
+       (+) Global readout protection (RDP)
+       (+) Write protection
+       (+) Secure access only protection
+       (+) Bank / register swapping
+       (+) Cyclic Redundancy Check (CRC)
+
+                        ##### How to use this driver #####
+ ==============================================================================
+  [..] This driver provides functions to configure and program the FLASH memory
+       of all STM32H7xx devices. It includes
+      (#) FLASH Memory Erase functions:
+           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
+                HAL_FLASH_Lock() functions
+           (++) Erase function: Sector erase, bank erase and dual-bank mass erase
+           (++) There are two modes of erase :
+             (+++) Polling Mode using HAL_FLASHEx_Erase()
+             (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
+
+      (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to:
+        (++) Set/Reset the write protection per bank
+        (++) Set the Read protection Level
+        (++) Set the BOR level
+        (++) Program the user Option Bytes
+        (++) PCROP protection configuration and control per bank
+        (++) Secure area configuration and control per bank
+        (++) Core Boot address configuration
+
+      (#) FLASH Memory Lock and unlock per Bank: HAL_FLASHEx_Lock_Bank1(), HAL_FLASHEx_Unlock_Bank1(),
+          HAL_FLASHEx_Lock_Bank2() and HAL_FLASHEx_Unlock_Bank2() functions
+
+      (#) FLASH CRC computation function: Use HAL_FLASHEx_ComputeCRC() to:
+          (++) Enable CRC feature
+          (++) Program the desired burst size
+          (++) Define the user Flash Area on which the CRC has be computed
+          (++) Perform the CRC computation
+          (++) Disable CRC feature
+
+ @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup FLASHEx  FLASHEx
+  * @brief FLASH HAL Extension module driver
+  * @{
+  */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup FLASHEx_Private_Constants
+  * @{
+  */
+#define FLASH_TIMEOUT_VALUE       50000U /* 50 s */
+
+/**
+  * @}
+  */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
+  * @{
+  */
+static void FLASH_MassErase(uint32_t VoltageRange, uint32_t Banks);
+static void FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks);
+static void FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Bank);
+static void FLASH_OB_GetWRP(uint32_t *WRPState, uint32_t *WRPSector, uint32_t Bank);
+static void FLASH_OB_RDPConfig(uint32_t RDPLevel);
+static uint32_t FLASH_OB_GetRDP(void);
+static void FLASH_OB_PCROPConfig(uint32_t PCROConfigRDP, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr, uint32_t Banks);
+static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROPStartAddr,uint32_t *PCROPEndAddr, uint32_t Bank);
+static void FLASH_OB_BOR_LevelConfig(uint32_t Level);
+static uint32_t FLASH_OB_GetBOR(void);
+static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig);
+static uint32_t FLASH_OB_GetUser(void);
+static void FLASH_OB_BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1);
+static void FLASH_OB_GetBootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1);
+static void FLASH_OB_SecureAreaConfig(uint32_t SecureAreaConfig, uint32_t SecureAreaStartAddr, uint32_t SecureAreaEndAddr, uint32_t Banks);
+static void FLASH_OB_GetSecureArea(uint32_t *SecureAreaConfig, uint32_t *SecureAreaStartAddr, uint32_t *SecureAreaEndAddr, uint32_t Bank);
+static void FLASH_CRC_AddSector(uint32_t Sector, uint32_t Bank);
+static void FLASH_CRC_SelectAddress(uint32_t CRCStartAddr, uint32_t CRCEndAddr, uint32_t Bank);
+
+#if defined (DUAL_CORE)
+static void FLASH_OB_CM4BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1);
+static void FLASH_OB_GetCM4BootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1);
+#endif /* DUAL_CORE */
+
+#if defined (FLASH_OTPBL_LOCKBL)
+static void FLASH_OB_OTP_LockConfig(uint32_t OTP_Block);
+static uint32_t FLASH_OB_OTP_GetLock(void);
+#endif /* FLASH_OTPBL_LOCKBL */
+/**
+  * @}
+  */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
+  * @{
+  */
+
+/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
+ *  @brief   Extended IO operation functions
+ *
+@verbatim
+ ===============================================================================
+                ##### Extended programming operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the Extension FLASH
+    programming operations Operations.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Perform a mass erase or erase the specified FLASH memory sectors
+  * @param[in]  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
+  *         contains the configuration information for the erasing.
+  *
+  * @param[out]  SectorError pointer to variable  that contains the configuration
+  *          information on faulty sector in case of error (0xFFFFFFFF means that all
+  *          the sectors have been correctly erased)
+  *
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t sector_index;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
+  assert_param(IS_FLASH_BANK(pEraseInit->Banks));
+
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Reset error code */
+  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+  /* Wait for last operation to be completed on Bank1 */
+  if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
+  {
+    if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK)
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  /* Wait for last operation to be completed on Bank2 */
+  if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
+  {
+    if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK)
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  if(status == HAL_OK)
+  {
+    if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
+    {
+      /* Mass erase to be done */
+      FLASH_MassErase(pEraseInit->VoltageRange, pEraseInit->Banks);
+
+      /* Wait for last operation to be completed */
+      if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
+      {
+        if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK)
+        {
+          status = HAL_ERROR;
+        }
+        /* if the erase operation is completed, disable the Bank1 BER Bit */
+        FLASH->CR1 &= (~FLASH_CR_BER);
+      }
+      if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
+      {
+        if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK)
+        {
+          status = HAL_ERROR;
+        }
+        /* if the erase operation is completed, disable the Bank2 BER Bit */
+        FLASH->CR2 &= (~FLASH_CR_BER);
+      }
+    }
+    else
+    {
+      /*Initialization of SectorError variable*/
+      *SectorError = 0xFFFFFFFFU;
+
+      /* Erase by sector by sector to be done*/
+      for(sector_index = pEraseInit->Sector; sector_index < (pEraseInit->NbSectors + pEraseInit->Sector); sector_index++)
+      {
+        FLASH_Erase_Sector(sector_index, pEraseInit->Banks, pEraseInit->VoltageRange);
+
+        if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
+        {
+          /* Wait for last operation to be completed */
+          status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
+
+          /* If the erase operation is completed, disable the SER Bit */
+          FLASH->CR1 &= (~(FLASH_CR_SER | FLASH_CR_SNB));
+        }
+        if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
+        {
+          /* Wait for last operation to be completed */
+          status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
+
+          /* If the erase operation is completed, disable the SER Bit */
+          FLASH->CR2 &= (~(FLASH_CR_SER | FLASH_CR_SNB));
+        }
+
+        if(status != HAL_OK)
+        {
+          /* In case of error, stop erase procedure and return the faulty sector */
+          *SectorError = sector_index;
+          break;
+        }
+      }
+    }
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(&pFlash);
+
+  return status;
+}
+
+/**
+  * @brief  Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled
+  * @param  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
+  *         contains the configuration information for the erasing.
+  *
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
+  assert_param(IS_FLASH_BANK(pEraseInit->Banks));
+
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Reset error code */
+  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+  /* Wait for last operation to be completed */
+  if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
+  {
+    if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK)
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
+  {
+    if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK)
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  if (status != HAL_OK)
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(&pFlash);
+  }
+  else
+  {
+    if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
+    {
+      /* Enable End of Operation and Error interrupts for Bank 1 */
+#if defined (FLASH_CR_OPERRIE)
+      __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1     | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
+                                  FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1);
+#else
+      __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1     | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
+                                  FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1);
+#endif /* FLASH_CR_OPERRIE */
+    }
+    if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
+    {
+      /* Enable End of Operation and Error interrupts for Bank 2 */
+#if defined (FLASH_CR_OPERRIE)
+      __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2     | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
+                                  FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2);
+#else
+      __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2     | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
+                                  FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2);
+#endif /* FLASH_CR_OPERRIE */
+    }
+
+    if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
+    {
+      /*Mass erase to be done*/
+      if(pEraseInit->Banks == FLASH_BANK_1)
+      {
+        pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE_BANK1;
+      }
+      else if(pEraseInit->Banks == FLASH_BANK_2)
+      {
+        pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE_BANK2;
+      }
+      else
+      {
+        pFlash.ProcedureOnGoing = FLASH_PROC_ALLBANK_MASSERASE;
+      }
+
+      FLASH_MassErase(pEraseInit->VoltageRange, pEraseInit->Banks);
+    }
+    else
+    {
+      /* Erase by sector to be done */
+      if(pEraseInit->Banks == FLASH_BANK_1)
+      {
+        pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE_BANK1;
+      }
+      else
+      {
+        pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE_BANK2;
+      }
+
+      pFlash.NbSectorsToErase = pEraseInit->NbSectors;
+      pFlash.Sector = pEraseInit->Sector;
+      pFlash.VoltageForErase = pEraseInit->VoltageRange;
+
+      /* Erase first sector and wait for IT */
+      FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->Banks, pEraseInit->VoltageRange);
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Program option bytes
+  * @param  pOBInit pointer to an FLASH_OBInitStruct structure that
+  *         contains the configuration information for the programming.
+  *
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check the parameters */
+  assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
+
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Reset Error Code */
+  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+  /* Wait for last operation to be completed */
+  if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK)
+  {
+    status = HAL_ERROR;
+  }
+  else if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    status = HAL_OK;
+  }
+
+  if(status == HAL_OK)
+  {
+    /*Write protection configuration*/
+    if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
+    {
+      assert_param(IS_WRPSTATE(pOBInit->WRPState));
+
+      if(pOBInit->WRPState == OB_WRPSTATE_ENABLE)
+      {
+        /*Enable of Write protection on the selected Sector*/
+        FLASH_OB_EnableWRP(pOBInit->WRPSector,pOBInit->Banks);
+      }
+      else
+      {
+        /*Disable of Write protection on the selected Sector*/
+        FLASH_OB_DisableWRP(pOBInit->WRPSector, pOBInit->Banks);
+      }
+    }
+
+    /* Read protection configuration */
+    if((pOBInit->OptionType & OPTIONBYTE_RDP) != 0U)
+    {
+      /* Configure the Read protection level */
+      FLASH_OB_RDPConfig(pOBInit->RDPLevel);
+    }
+
+    /* User Configuration */
+    if((pOBInit->OptionType & OPTIONBYTE_USER) != 0U)
+    {
+      /* Configure the user option bytes */
+      FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig);
+    }
+
+    /* PCROP Configuration */
+    if((pOBInit->OptionType & OPTIONBYTE_PCROP) != 0U)
+    {
+      assert_param(IS_FLASH_BANK(pOBInit->Banks));
+
+      /*Configure the Proprietary code readout protection */
+      FLASH_OB_PCROPConfig(pOBInit->PCROPConfig, pOBInit->PCROPStartAddr, pOBInit->PCROPEndAddr, pOBInit->Banks);
+    }
+
+    /* BOR Level configuration */
+    if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR)
+    {
+      FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel);
+    }
+
+#if defined(DUAL_CORE)
+    /* CM7 Boot Address  configuration */
+    if((pOBInit->OptionType & OPTIONBYTE_CM7_BOOTADD) == OPTIONBYTE_CM7_BOOTADD)
+    {
+      FLASH_OB_BootAddConfig(pOBInit->BootConfig, pOBInit->BootAddr0, pOBInit->BootAddr1);
+    }
+
+    /* CM4 Boot Address  configuration */
+    if((pOBInit->OptionType & OPTIONBYTE_CM4_BOOTADD) == OPTIONBYTE_CM4_BOOTADD)
+    {
+      FLASH_OB_CM4BootAddConfig(pOBInit->CM4BootConfig, pOBInit->CM4BootAddr0, pOBInit->CM4BootAddr1);
+    }
+#else /* Single Core*/
+    /* Boot Address  configuration */
+    if((pOBInit->OptionType & OPTIONBYTE_BOOTADD) == OPTIONBYTE_BOOTADD)
+    {
+      FLASH_OB_BootAddConfig(pOBInit->BootConfig, pOBInit->BootAddr0, pOBInit->BootAddr1);
+    }
+#endif /*DUAL_CORE*/
+
+    /* Secure area configuration */
+    if((pOBInit->OptionType & OPTIONBYTE_SECURE_AREA) == OPTIONBYTE_SECURE_AREA)
+    {
+      FLASH_OB_SecureAreaConfig(pOBInit->SecureAreaConfig, pOBInit->SecureAreaStartAddr, pOBInit->SecureAreaEndAddr,pOBInit->Banks);
+    }
+
+#if defined(FLASH_OTPBL_LOCKBL)
+    /* OTP Block Lock configuration */
+    if((pOBInit->OptionType & OPTIONBYTE_OTP_LOCK) == OPTIONBYTE_OTP_LOCK)
+    {
+      FLASH_OB_OTP_LockConfig(pOBInit->OTPBlockLock);
+    }
+#endif /* FLASH_OTPBL_LOCKBL */
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(&pFlash);
+
+  return status;
+}
+
+/**
+  * @brief Get the Option byte configuration
+  * @param  pOBInit pointer to an FLASH_OBInitStruct structure that
+  *         contains the configuration information for the programming.
+  * @note   The parameter Banks of the pOBInit structure must be set exclusively to FLASH_BANK_1 or FLASH_BANK_2,
+  *         as this parameter is use to get the given Bank WRP, PCROP and secured area configuration.
+  *
+  * @retval None
+  */
+void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
+{
+  pOBInit->OptionType = (OPTIONBYTE_USER | OPTIONBYTE_RDP | OPTIONBYTE_BOR);
+
+  /* Get Read protection level */
+  pOBInit->RDPLevel = FLASH_OB_GetRDP();
+
+  /* Get the user option bytes */
+  pOBInit->USERConfig = FLASH_OB_GetUser();
+
+  /*Get BOR Level*/
+  pOBInit->BORLevel = FLASH_OB_GetBOR();
+
+  if ((pOBInit->Banks == FLASH_BANK_1) || (pOBInit->Banks == FLASH_BANK_2))
+  {
+    pOBInit->OptionType |= (OPTIONBYTE_WRP | OPTIONBYTE_PCROP | OPTIONBYTE_SECURE_AREA);
+
+    /* Get write protection on the selected area */
+    FLASH_OB_GetWRP(&(pOBInit->WRPState), &(pOBInit->WRPSector), pOBInit->Banks);
+
+    /* Get the Proprietary code readout protection */
+    FLASH_OB_GetPCROP(&(pOBInit->PCROPConfig), &(pOBInit->PCROPStartAddr), &(pOBInit->PCROPEndAddr), pOBInit->Banks);
+
+    /*Get Bank Secure area*/
+    FLASH_OB_GetSecureArea(&(pOBInit->SecureAreaConfig), &(pOBInit->SecureAreaStartAddr), &(pOBInit->SecureAreaEndAddr), pOBInit->Banks);
+  }
+
+  /*Get Boot Address*/
+  FLASH_OB_GetBootAdd(&(pOBInit->BootAddr0), &(pOBInit->BootAddr1));
+#if defined(DUAL_CORE)
+  pOBInit->OptionType |= OPTIONBYTE_CM7_BOOTADD | OPTIONBYTE_CM4_BOOTADD;
+
+  /*Get CM4 Boot Address*/
+  FLASH_OB_GetCM4BootAdd(&(pOBInit->CM4BootAddr0), &(pOBInit->CM4BootAddr1));
+#else
+  pOBInit->OptionType |= OPTIONBYTE_BOOTADD;
+#endif /*DUAL_CORE*/
+
+#if defined (FLASH_OTPBL_LOCKBL)
+  pOBInit->OptionType |= OPTIONBYTE_OTP_LOCK;
+
+  /* Get OTP Block Lock */
+  pOBInit->OTPBlockLock = FLASH_OB_OTP_GetLock();
+#endif /* FLASH_OTPBL_LOCKBL */
+}
+
+/**
+  * @brief  Unlock the FLASH Bank1 control registers access
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank1(void)
+{
+  if(READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != 0U)
+  {
+    /* Authorize the FLASH Bank1 Registers access */
+    WRITE_REG(FLASH->KEYR1, FLASH_KEY1);
+    WRITE_REG(FLASH->KEYR1, FLASH_KEY2);
+
+    /* Verify Flash Bank1 is unlocked */
+    if (READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != 0U)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Locks the FLASH Bank1 control registers access
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1(void)
+{
+  /* Set the LOCK Bit to lock the FLASH Bank1 Registers access */
+  SET_BIT(FLASH->CR1, FLASH_CR_LOCK);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Unlock the FLASH Bank2 control registers access
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank2(void)
+{
+  if(READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != 0U)
+  {
+    /* Authorize the FLASH Bank2 Registers access */
+    WRITE_REG(FLASH->KEYR2, FLASH_KEY1);
+    WRITE_REG(FLASH->KEYR2, FLASH_KEY2);
+
+    /* Verify Flash Bank1 is unlocked */
+    if (READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != 0U)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Locks the FLASH Bank2 control registers access
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank2(void)
+{
+  /* Set the LOCK Bit to lock the FLASH Bank2 Registers access */
+  SET_BIT(FLASH->CR2, FLASH_CR_LOCK);
+  return HAL_OK;
+}
+
+/*
+  * @brief  Perform a CRC computation on the specified FLASH memory area
+  * @param  pCRCInit pointer to an FLASH_CRCInitTypeDef structure that
+  *         contains the configuration information for the CRC computation.
+  * @note   CRC computation uses CRC-32 (Ethernet) polynomial 0x4C11DB7
+  * @note   The application should avoid running a CRC on PCROP or secure-only
+  *         user Flash memory area since it may alter the expected CRC value.
+  *         A special error flag (CRC read error: CRCRDERR) can be used to
+  *         detect such a case.
+  * @retval HAL Status
+*/
+HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_t *CRC_Result)
+{
+  HAL_StatusTypeDef status;
+  uint32_t sector_index;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_BANK_EXCLUSIVE(pCRCInit->Bank));
+  assert_param(IS_FLASH_TYPECRC(pCRCInit->TypeCRC));
+
+  /* Wait for OB change operation to be completed */
+  status = FLASH_OB_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if (status == HAL_OK)
+  {
+    if (pCRCInit->Bank == FLASH_BANK_1)
+    {
+      /* Enable CRC feature */
+      FLASH->CR1 |= FLASH_CR_CRC_EN;
+
+      /* Clear CRC flags in Status Register: CRC end of calculation and CRC read error */
+      FLASH->CCR1 |= (FLASH_CCR_CLR_CRCEND | FLASH_CCR_CLR_CRCRDERR);
+
+      /* Clear current CRC result, program burst size and define memory area on which CRC has to be computed */
+      FLASH->CRCCR1 |= FLASH_CRCCR_CLEAN_CRC | pCRCInit->BurstSize | pCRCInit->TypeCRC;
+
+      if (pCRCInit->TypeCRC == FLASH_CRC_SECTORS)
+      {
+        /* Clear sectors list */
+        FLASH->CRCCR1 |= FLASH_CRCCR_CLEAN_SECT;
+
+        /* Select CRC sectors */
+        for(sector_index = pCRCInit->Sector; sector_index < (pCRCInit->NbSectors + pCRCInit->Sector); sector_index++)
+        {
+          FLASH_CRC_AddSector(sector_index, FLASH_BANK_1);
+        }
+      }
+      else if (pCRCInit->TypeCRC == FLASH_CRC_BANK)
+      {
+        /* Enable Bank 1 CRC select bit */
+        FLASH->CRCCR1 |= FLASH_CRCCR_ALL_BANK;
+      }
+      else
+      {
+        /* Select CRC start and end addresses */
+        FLASH_CRC_SelectAddress(pCRCInit->CRCStartAddr, pCRCInit->CRCEndAddr, FLASH_BANK_1);
+      }
+
+      /* Start the CRC calculation */
+      FLASH->CRCCR1 |= FLASH_CRCCR_START_CRC;
+
+      /* Wait on CRC busy flag */
+      status = FLASH_CRC_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
+
+      /* Return CRC result */
+      (*CRC_Result) = FLASH->CRCDATA;
+
+      /* Disable CRC feature */
+      FLASH->CR1 &= (~FLASH_CR_CRC_EN);
+
+      /* Clear CRC flags */
+      __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_CRCEND_BANK1 | FLASH_FLAG_CRCRDERR_BANK1);
+    }
+    else
+    {
+      /* Enable CRC feature */
+      FLASH->CR2 |= FLASH_CR_CRC_EN;
+
+      /* Clear CRC flags in Status Register: CRC end of calculation and CRC read error */
+      FLASH->CCR2 |= (FLASH_CCR_CLR_CRCEND | FLASH_CCR_CLR_CRCRDERR);
+
+      /* Clear current CRC result, program burst size and define memory area on which CRC has to be computed */
+      FLASH->CRCCR2 |= FLASH_CRCCR_CLEAN_CRC | pCRCInit->BurstSize | pCRCInit->TypeCRC;
+
+      if (pCRCInit->TypeCRC == FLASH_CRC_SECTORS)
+      {
+        /* Clear sectors list */
+        FLASH->CRCCR2 |= FLASH_CRCCR_CLEAN_SECT;
+
+        /* Add CRC sectors */
+        for(sector_index = pCRCInit->Sector; sector_index < (pCRCInit->NbSectors + pCRCInit->Sector); sector_index++)
+        {
+          FLASH_CRC_AddSector(sector_index, FLASH_BANK_2);
+        }
+      }
+      else if (pCRCInit->TypeCRC == FLASH_CRC_BANK)
+      {
+        /* Enable Bank 2 CRC select bit */
+        FLASH->CRCCR2 |= FLASH_CRCCR_ALL_BANK;
+      }
+      else
+      {
+        /* Select CRC start and end addresses */
+        FLASH_CRC_SelectAddress(pCRCInit->CRCStartAddr, pCRCInit->CRCEndAddr, FLASH_BANK_2);
+      }
+
+      /* Start the CRC calculation */
+      FLASH->CRCCR2 |= FLASH_CRCCR_START_CRC;
+
+      /* Wait on CRC busy flag */
+      status = FLASH_CRC_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
+
+      /* Return CRC result */
+      (*CRC_Result) = FLASH->CRCDATA;
+
+      /* Disable CRC feature */
+      FLASH->CR2 &= (~FLASH_CR_CRC_EN);
+
+      /* Clear CRC flags */
+      __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_CRCEND_BANK2 | FLASH_FLAG_CRCRDERR_BANK2);
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @addtogroup FLASHEx_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Mass erase of FLASH memory
+  * @param  VoltageRange The device program/erase parallelism.
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_VOLTAGE_RANGE_1 : Flash program/erase by 8 bits
+  *            @arg FLASH_VOLTAGE_RANGE_2 : Flash program/erase by 16 bits
+  *            @arg FLASH_VOLTAGE_RANGE_3 : Flash program/erase by 32 bits
+  *            @arg FLASH_VOLTAGE_RANGE_4 : Flash program/erase by 64 bits
+  *
+  * @param  Banks Banks to be erased
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: Bank1 to be erased
+  *            @arg FLASH_BANK_2: Bank2 to be erased
+  *            @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
+  *
+  * @retval HAL Status
+  */
+static void FLASH_MassErase(uint32_t VoltageRange, uint32_t Banks)
+{
+  /* Check the parameters */
+#if defined (FLASH_CR_PSIZE)
+  assert_param(IS_VOLTAGERANGE(VoltageRange));
+#else
+  UNUSED(VoltageRange);
+#endif /* FLASH_CR_PSIZE */
+  assert_param(IS_FLASH_BANK(Banks));
+
+  /* Flash Mass Erase */
+  if((Banks & FLASH_BANK_BOTH) == FLASH_BANK_BOTH)
+  {
+#if defined (FLASH_CR_PSIZE)
+    /* Reset Program/erase VoltageRange for Bank1 and Bank2 */
+    FLASH->CR1 &= (~FLASH_CR_PSIZE);
+    FLASH->CR2 &= (~FLASH_CR_PSIZE);
+
+    /* Set voltage range */
+    FLASH->CR1 |= VoltageRange;
+    FLASH->CR2 |= VoltageRange;
+#endif /* FLASH_CR_PSIZE */
+
+    /* Set Mass Erase Bit */
+    FLASH->OPTCR |= FLASH_OPTCR_MER;
+  }
+  else
+  {
+    /* Proceed to erase Flash Bank  */
+    if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
+    {
+#if defined (FLASH_CR_PSIZE)
+      /* Set Program/erase VoltageRange for Bank1 */
+      FLASH->CR1 &= (~FLASH_CR_PSIZE);
+      FLASH->CR1 |=  VoltageRange;
+#endif /* FLASH_CR_PSIZE */
+
+      /* Erase Bank1 */
+      FLASH->CR1 |= (FLASH_CR_BER | FLASH_CR_START);
+    }
+    if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
+    {
+#if defined (FLASH_CR_PSIZE)
+      /* Set Program/erase VoltageRange for Bank2 */
+      FLASH->CR2 &= (~FLASH_CR_PSIZE);
+      FLASH->CR2 |= VoltageRange;
+#endif /* FLASH_CR_PSIZE */
+
+      /* Erase Bank2 */
+      FLASH->CR2 |= (FLASH_CR_BER | FLASH_CR_START);
+    }
+  }
+}
+
+/**
+  * @brief  Erase the specified FLASH memory sector
+  * @param  Sector FLASH sector to erase
+  *          This parameter can be a value of @ref FLASH_Sectors
+  * @param  Banks Banks to be erased
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: Bank1 to be erased
+  *            @arg FLASH_BANK_2: Bank2 to be erased
+  *            @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
+  * @param  VoltageRange The device program/erase parallelism.
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_VOLTAGE_RANGE_1 : Flash program/erase by 8 bits
+  *            @arg FLASH_VOLTAGE_RANGE_2 : Flash program/erase by 16 bits
+  *            @arg FLASH_VOLTAGE_RANGE_3 : Flash program/erase by 32 bits
+  *            @arg FLASH_VOLTAGE_RANGE_4 : Flash program/erase by 64 bits
+  *
+  * @retval None
+  */
+void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange)
+{
+  assert_param(IS_FLASH_SECTOR(Sector));
+  assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks));
+#if defined (FLASH_CR_PSIZE)
+  assert_param(IS_VOLTAGERANGE(VoltageRange));
+#else
+  UNUSED(VoltageRange);
+#endif /* FLASH_CR_PSIZE */
+
+  if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
+  {
+#if defined (FLASH_CR_PSIZE)
+    /* Reset Program/erase VoltageRange and Sector Number for Bank1 */
+    FLASH->CR1 &= ~(FLASH_CR_PSIZE | FLASH_CR_SNB);
+
+    FLASH->CR1 |= (FLASH_CR_SER | VoltageRange | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START);
+#else
+    /* Reset Sector Number for Bank1 */
+    FLASH->CR1 &= ~(FLASH_CR_SNB);
+
+    FLASH->CR1 |= (FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START);
+#endif /* FLASH_CR_PSIZE */
+  }
+
+  if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
+  {
+#if defined (FLASH_CR_PSIZE)
+    /* Reset Program/erase VoltageRange and Sector Number for Bank2 */
+    FLASH->CR2 &= ~(FLASH_CR_PSIZE | FLASH_CR_SNB);
+
+    FLASH->CR2 |= (FLASH_CR_SER | VoltageRange  | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START);
+#else
+    /* Reset Sector Number for Bank2 */
+    FLASH->CR2 &= ~(FLASH_CR_SNB);
+
+    FLASH->CR2 |= (FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START);
+#endif /* FLASH_CR_PSIZE */
+  }
+}
+
+/**
+  * @brief  Enable the write protection of the desired bank1 or bank 2 sectors
+  * @param  WRPSector specifies the sector(s) to be write protected.
+  *          This parameter can be one of the following values:
+  *            @arg WRPSector:  A combination of OB_WRP_SECTOR_0 to OB_WRP_SECTOR_7 or OB_WRP_SECTOR_All
+  *
+  * @param  Banks the specific bank to apply WRP sectors
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: enable WRP on specified bank1 sectors
+  *            @arg FLASH_BANK_2: enable WRP on specified bank2 sectors
+  *            @arg FLASH_BANK_BOTH: enable WRP on both bank1 and bank2 specified sectors
+  *
+  * @retval HAL FLASH State
+  */
+static void FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
+{
+  /* Check the parameters */
+  assert_param(IS_OB_WRP_SECTOR(WRPSector));
+  assert_param(IS_FLASH_BANK(Banks));
+
+  if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
+  {
+    /* Enable Write Protection for bank 1 */
+    FLASH->WPSN_PRG1 &= (~(WRPSector & FLASH_WPSN_WRPSN));
+  }
+
+  if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
+  {
+    /* Enable Write Protection for bank 2 */
+    FLASH->WPSN_PRG2 &= (~(WRPSector & FLASH_WPSN_WRPSN));
+  }
+}
+
+/**
+  * @brief  Disable the write protection of the desired bank1 or bank 2 sectors
+  * @param  WRPSector specifies the sector(s) to disable write protection.
+  *          This parameter can be one of the following values:
+  *            @arg WRPSector:  A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_All
+  *
+  * @param  Banks the specific bank to apply WRP sectors
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: disable WRP on specified bank1 sectors
+  *            @arg FLASH_BANK_2: disable WRP on specified bank2 sectors
+  *            @arg FLASH_BANK_BOTH: disable WRP on both bank1 and bank2 specified sectors
+  *
+  * @retval HAL FLASH State
+  */
+static void FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)
+{
+  /* Check the parameters */
+  assert_param(IS_OB_WRP_SECTOR(WRPSector));
+  assert_param(IS_FLASH_BANK(Banks));
+
+  if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
+  {
+    /* Disable Write Protection for bank 1 */
+    FLASH->WPSN_PRG1 |= (WRPSector & FLASH_WPSN_WRPSN);
+  }
+
+  if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
+  {
+    /* Disable Write Protection for bank 2 */
+    FLASH->WPSN_PRG2 |= (WRPSector & FLASH_WPSN_WRPSN);
+  }
+}
+
+/**
+  * @brief  Get the write protection of the given bank 1 or bank 2 sectors
+  * @param  WRPState gives the write protection state on the given bank.
+  *          This parameter can be one of the following values:
+  *          @arg WRPState: OB_WRPSTATE_DISABLE or OB_WRPSTATE_ENABLE
+
+  * @param  WRPSector gives the write protected sector(s) on the given bank .
+  *          This parameter can be one of the following values:
+  *          @arg WRPSector: A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_All
+  *
+  * @param  Bank the specific bank to apply WRP sectors
+  *          This parameter can be exclusively one of the following values:
+  *            @arg FLASH_BANK_1: Get bank1 WRP sectors
+  *            @arg FLASH_BANK_2: Get bank2 WRP sectors
+  *            @arg FLASH_BANK_BOTH: note allowed in this functions
+  *
+  * @retval HAL FLASH State
+  */
+static void FLASH_OB_GetWRP(uint32_t *WRPState, uint32_t *WRPSector, uint32_t Bank)
+{
+  uint32_t regvalue = 0U;
+
+  if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_1)
+  {
+    regvalue = FLASH->WPSN_CUR1;
+  }
+
+  if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_2)
+  {
+    regvalue = FLASH->WPSN_CUR2;
+  }
+
+  (*WRPSector) = (~regvalue) & FLASH_WPSN_WRPSN;
+
+  if(*WRPSector == 0U)
+  {
+    (*WRPState) = OB_WRPSTATE_DISABLE;
+  }
+  else
+  {
+    (*WRPState) = OB_WRPSTATE_ENABLE;
+  }
+}
+
+/**
+  * @brief  Set the read protection level.
+  *
+  * @note   To configure the RDP level, the option lock bit OPTLOCK must be
+  *         cleared with the call of the HAL_FLASH_OB_Unlock() function.
+  * @note   To validate the RDP level, the option bytes must be reloaded
+  *         through the call of the HAL_FLASH_OB_Launch() function.
+  * @note   !!! Warning : When enabling OB_RDP level 2 it's no more possible
+  *         to go back to level 1 or 0 !!!
+  *
+  * @param  RDPLevel specifies the read protection level.
+  *         This parameter can be one of the following values:
+  *            @arg OB_RDP_LEVEL_0: No protection
+  *            @arg OB_RDP_LEVEL_1: Read protection of the memory
+  *            @arg OB_RDP_LEVEL_2: Full chip protection
+  *
+  * @retval HAL status
+  */
+static void FLASH_OB_RDPConfig(uint32_t RDPLevel)
+{
+  /* Check the parameters */
+  assert_param(IS_OB_RDP_LEVEL(RDPLevel));
+
+  /* Configure the RDP level in the option bytes register */
+  MODIFY_REG(FLASH->OPTSR_PRG, FLASH_OPTSR_RDP, RDPLevel);
+}
+
+/**
+  * @brief  Get the read protection level.
+  * @retval RDPLevel specifies the read protection level.
+  *         This return value can be one of the following values:
+  *            @arg OB_RDP_LEVEL_0: No protection
+  *            @arg OB_RDP_LEVEL_1: Read protection of the memory
+  *            @arg OB_RDP_LEVEL_2: Full chip protection
+  */
+static uint32_t FLASH_OB_GetRDP(void)
+{
+  uint32_t rdp_level = READ_BIT(FLASH->OPTSR_CUR, FLASH_OPTSR_RDP);
+  
+  if ((rdp_level != OB_RDP_LEVEL_0) && (rdp_level != OB_RDP_LEVEL_2))
+  {
+    return (OB_RDP_LEVEL_1);
+  }
+  else
+  {
+    return rdp_level;
+  }
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Program the FLASH User Option Byte.
+  *
+  * @note   To configure the user option bytes, the option lock bit OPTLOCK must
+  *         be cleared with the call of the HAL_FLASH_OB_Unlock() function.
+  *
+  * @note   To validate the user option bytes, the option bytes must be reloaded
+  *         through the call of the HAL_FLASH_OB_Launch() function.
+  *
+  * @param  UserType The FLASH User Option Bytes to be modified :
+  *                   a combination of @ref FLASHEx_OB_USER_Type
+  *
+  * @param  UserConfig The FLASH User Option Bytes values:
+  *         IWDG1_SW(Bit4), IWDG2_SW(Bit 5), nRST_STOP_D1(Bit 6), nRST_STDY_D1(Bit 7),
+  *         FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]),
+  *         SECURITY(Bit 21), BCM4(Bit 22), BCM7(Bit 23), nRST_STOP_D2(Bit 24),
+  *         nRST_STDY_D2(Bit 25), IO_HSLV (Bit 29) and SWAP_BANK_OPT(Bit 31).
+  *
+  * @retval HAL status
+  */
+#else
+/**
+  * @brief  Program the FLASH User Option Byte.
+  *
+  * @note   To configure the user option bytes, the option lock bit OPTLOCK must
+  *         be cleared with the call of the HAL_FLASH_OB_Unlock() function.
+  *
+  * @note   To validate the user option bytes, the option bytes must be reloaded
+  *         through the call of the HAL_FLASH_OB_Launch() function.
+  *
+  * @param  UserType The FLASH User Option Bytes to be modified :
+  *                   a combination of @arg FLASHEx_OB_USER_Type
+  *
+  * @param  UserConfig The FLASH User Option Bytes values:
+  *         IWDG_SW(Bit4), nRST_STOP_D1(Bit 6), nRST_STDY_D1(Bit 7),
+  *         FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]),
+  *         SECURITY(Bit 21), IO_HSLV (Bit 29) and SWAP_BANK_OPT(Bit 31).
+  *
+  * @retval HAL status
+  */
+#endif /*DUAL_CORE*/
+static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig)
+{
+  uint32_t optr_reg_val = 0;
+  uint32_t optr_reg_mask = 0;
+
+  /* Check the parameters */
+  assert_param(IS_OB_USER_TYPE(UserType));
+
+  if((UserType & OB_USER_IWDG1_SW) != 0U)
+  {
+    /* IWDG_HW option byte should be modified */
+    assert_param(IS_OB_IWDG1_SOURCE(UserConfig & FLASH_OPTSR_IWDG1_SW));
+
+    /* Set value and mask for IWDG_HW option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_IWDG1_SW);
+    optr_reg_mask |= FLASH_OPTSR_IWDG1_SW;
+  }
+#if defined(DUAL_CORE)
+  if((UserType & OB_USER_IWDG2_SW) != 0U)
+  {
+    /* IWDG2_SW option byte should be modified */
+    assert_param(IS_OB_IWDG2_SOURCE(UserConfig & FLASH_OPTSR_IWDG2_SW));
+
+    /* Set value and mask for IWDG2_SW option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_IWDG2_SW);
+    optr_reg_mask |= FLASH_OPTSR_IWDG2_SW;
+  }
+#endif /*DUAL_CORE*/
+  if((UserType & OB_USER_NRST_STOP_D1) != 0U)
+  {
+    /* NRST_STOP option byte should be modified */
+    assert_param(IS_OB_STOP_D1_RESET(UserConfig & FLASH_OPTSR_NRST_STOP_D1));
+
+    /* Set value and mask for NRST_STOP option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STOP_D1);
+    optr_reg_mask |= FLASH_OPTSR_NRST_STOP_D1;
+  }
+
+  if((UserType & OB_USER_NRST_STDBY_D1) != 0U)
+  {
+    /* NRST_STDBY option byte should be modified */
+    assert_param(IS_OB_STDBY_D1_RESET(UserConfig & FLASH_OPTSR_NRST_STBY_D1));
+
+    /* Set value and mask for NRST_STDBY option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STBY_D1);
+    optr_reg_mask |= FLASH_OPTSR_NRST_STBY_D1;
+  }
+
+  if((UserType & OB_USER_IWDG_STOP) != 0U)
+  {
+    /* IWDG_STOP option byte should be modified */
+    assert_param(IS_OB_USER_IWDG_STOP(UserConfig & FLASH_OPTSR_FZ_IWDG_STOP));
+
+    /* Set value and mask for IWDG_STOP option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_FZ_IWDG_STOP);
+    optr_reg_mask |= FLASH_OPTSR_FZ_IWDG_STOP;
+  }
+
+  if((UserType & OB_USER_IWDG_STDBY) != 0U)
+  {
+    /* IWDG_STDBY option byte should be modified */
+    assert_param(IS_OB_USER_IWDG_STDBY(UserConfig & FLASH_OPTSR_FZ_IWDG_SDBY));
+
+    /* Set value and mask for IWDG_STDBY option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_FZ_IWDG_SDBY);
+    optr_reg_mask |= FLASH_OPTSR_FZ_IWDG_SDBY;
+  }
+
+  if((UserType & OB_USER_ST_RAM_SIZE) != 0U)
+  {
+    /* ST_RAM_SIZE option byte should be modified */
+    assert_param(IS_OB_USER_ST_RAM_SIZE(UserConfig & FLASH_OPTSR_ST_RAM_SIZE));
+
+    /* Set value and mask for ST_RAM_SIZE option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_ST_RAM_SIZE);
+    optr_reg_mask |= FLASH_OPTSR_ST_RAM_SIZE;
+  }
+
+  if((UserType & OB_USER_SECURITY) != 0U)
+  {
+    /* SECURITY option byte should be modified */
+    assert_param(IS_OB_USER_SECURITY(UserConfig & FLASH_OPTSR_SECURITY));
+
+    /* Set value and mask for SECURITY option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_SECURITY);
+    optr_reg_mask |= FLASH_OPTSR_SECURITY;
+  }
+
+#if defined(DUAL_CORE)
+  if((UserType & OB_USER_BCM4) != 0U)
+  {
+    /* BCM4 option byte should be modified */
+    assert_param(IS_OB_USER_BCM4(UserConfig & FLASH_OPTSR_BCM4));
+
+    /* Set value and mask for BCM4 option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_BCM4);
+    optr_reg_mask |= FLASH_OPTSR_BCM4;
+  }
+
+  if((UserType & OB_USER_BCM7) != 0U)
+  {
+    /* BCM7 option byte should be modified */
+    assert_param(IS_OB_USER_BCM7(UserConfig & FLASH_OPTSR_BCM7));
+
+    /* Set value and mask for BCM7 option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_BCM7);
+    optr_reg_mask |= FLASH_OPTSR_BCM7;
+  }
+
+  if((UserType & OB_USER_NRST_STOP_D2) != 0U)
+  {
+    /* NRST_STOP option byte should be modified */
+    assert_param(IS_OB_STOP_D2_RESET(UserConfig & FLASH_OPTSR_NRST_STOP_D2));
+
+    /* Set value and mask for NRST_STOP option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STOP_D2);
+    optr_reg_mask |= FLASH_OPTSR_NRST_STOP_D2;
+  }
+
+  if((UserType & OB_USER_NRST_STDBY_D2) != 0U)
+  {
+    /* NRST_STDBY option byte should be modified */
+    assert_param(IS_OB_STDBY_D2_RESET(UserConfig & FLASH_OPTSR_NRST_STBY_D2));
+
+    /* Set value and mask for NRST_STDBY option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STBY_D2);
+    optr_reg_mask |= FLASH_OPTSR_NRST_STBY_D2;
+  }
+#endif /* DUAL_CORE */
+  if((UserType & OB_USER_SWAP_BANK) != 0U)
+  {
+    /* SWAP_BANK_OPT option byte should be modified */
+    assert_param(IS_OB_USER_SWAP_BANK(UserConfig & FLASH_OPTSR_SWAP_BANK_OPT));
+
+    /* Set value and mask for SWAP_BANK_OPT option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_SWAP_BANK_OPT);
+    optr_reg_mask |= FLASH_OPTSR_SWAP_BANK_OPT;
+  }
+
+  if((UserType & OB_USER_IOHSLV) != 0U)
+  {
+    /* IOHSLV_OPT option byte should be modified */
+    assert_param(IS_OB_USER_IOHSLV(UserConfig & FLASH_OPTSR_IO_HSLV));
+
+    /* Set value and mask for IOHSLV_OPT option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_IO_HSLV);
+    optr_reg_mask |= FLASH_OPTSR_IO_HSLV;
+  }
+
+#if defined (FLASH_OPTSR_VDDMMC_HSLV)
+  if((UserType & OB_USER_VDDMMC_HSLV) != 0U)
+  {
+    /* VDDMMC_HSLV option byte should be modified */
+    assert_param(IS_OB_USER_VDDMMC_HSLV(UserConfig & FLASH_OPTSR_VDDMMC_HSLV));
+
+    /* Set value and mask for VDDMMC_HSLV option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_VDDMMC_HSLV);
+    optr_reg_mask |= FLASH_OPTSR_VDDMMC_HSLV;
+  }
+#endif /* FLASH_OPTSR_VDDMMC_HSLV */
+
+  /* Configure the option bytes register */
+  MODIFY_REG(FLASH->OPTSR_PRG, optr_reg_mask, optr_reg_val);
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Return the FLASH User Option Byte value.
+  * @retval The FLASH User Option Bytes values
+  *         IWDG1_SW(Bit4), IWDG2_SW(Bit 5), nRST_STOP_D1(Bit 6), nRST_STDY_D1(Bit 7),
+  *         FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]),
+  *         SECURITY(Bit 21), BCM4(Bit 22), BCM7(Bit 23), nRST_STOP_D2(Bit 24),
+  *         nRST_STDY_D2(Bit 25), IO_HSLV (Bit 29) and SWAP_BANK_OPT(Bit 31).
+  */
+#else
+/**
+  * @brief  Return the FLASH User Option Byte value.
+  * @retval The FLASH User Option Bytes values
+  *         IWDG_SW(Bit4), nRST_STOP_D1(Bit 6), nRST_STDY_D1(Bit 7),
+  *         FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]),
+  *         SECURITY(Bit 21), IO_HSLV (Bit 29) and SWAP_BANK_OPT(Bit 31).
+  */
+#endif /*DUAL_CORE*/
+static uint32_t FLASH_OB_GetUser(void)
+{
+  uint32_t userConfig = READ_REG(FLASH->OPTSR_CUR);
+  userConfig &= (~(FLASH_OPTSR_BOR_LEV | FLASH_OPTSR_RDP));
+
+  return userConfig;
+}
+
+/**
+  * @brief  Configure the Proprietary code readout protection of the desired addresses
+  *
+  * @note   To configure the PCROP options, the option lock bit OPTLOCK must be
+  *         cleared with the call of the HAL_FLASH_OB_Unlock() function.
+  * @note   To validate the PCROP options, the option bytes must be reloaded
+  *         through the call of the HAL_FLASH_OB_Launch() function.
+  *
+  * @param  PCROPConfig specifies if the PCROP area for the given Bank shall be erased or not
+  *         when RDP level decreased from Level 1 to Level 0, or after a bank erase with protection removal
+  *         This parameter must be a value of @arg FLASHEx_OB_PCROP_RDP enumeration
+  *
+  * @param  PCROPStartAddr specifies the start address of the Proprietary code readout protection
+  *          This parameter can be an address between begin and end of the bank
+  *
+  * @param  PCROPEndAddr specifies the end address of the Proprietary code readout protection
+  *          This parameter can be an address between PCROPStartAddr and end of the bank
+  *
+  * @param  Banks the specific bank to apply PCROP protection
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: PCROP on specified bank1 area
+  *            @arg FLASH_BANK_2: PCROP on specified bank2 area
+  *            @arg FLASH_BANK_BOTH: PCROP on specified bank1 and bank2 area (same config will be applied on both banks)
+  *
+  * @retval None
+  */
+static void FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr, uint32_t Banks)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_BANK(Banks));
+  assert_param(IS_OB_PCROP_RDP(PCROPConfig));
+
+  if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
+  {
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(PCROPStartAddr));
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(PCROPEndAddr));
+
+    /* Configure the Proprietary code readout protection */
+    FLASH->PRAR_PRG1 = ((PCROPStartAddr - FLASH_BANK1_BASE) >> 8)                                 | \
+                       (((PCROPEndAddr - FLASH_BANK1_BASE) >> 8) << FLASH_PRAR_PROT_AREA_END_Pos) | \
+                       PCROPConfig;
+  }
+
+  if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
+  {
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(PCROPStartAddr));
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(PCROPEndAddr));
+
+    /* Configure the Proprietary code readout protection */
+    FLASH->PRAR_PRG2 = ((PCROPStartAddr - FLASH_BANK2_BASE) >> 8)                                 | \
+                       (((PCROPEndAddr - FLASH_BANK2_BASE) >> 8) << FLASH_PRAR_PROT_AREA_END_Pos) | \
+                       PCROPConfig;
+  }
+}
+
+/**
+  * @brief  Get the Proprietary code readout protection configuration on a given Bank
+  *
+  * @param  PCROPConfig indicates if the PCROP area for the given Bank shall be erased or not
+  *         when RDP level decreased from Level 1 to Level 0 or after a bank erase with protection removal
+  *
+  * @param  PCROPStartAddr gives the start address of the Proprietary code readout protection of the bank
+  *
+  * @param  PCROPEndAddr gives the end address of the Proprietary code readout protection of the bank
+  *
+  * @param  Bank the specific bank to apply PCROP protection
+  *          This parameter can be exclusively one of the following values:
+  *            @arg FLASH_BANK_1: PCROP on specified bank1 area
+  *            @arg FLASH_BANK_2: PCROP on specified bank2 area
+  *            @arg FLASH_BANK_BOTH: is  not allowed here
+  *
+  * @retval None
+  */
+static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROPStartAddr, uint32_t *PCROPEndAddr, uint32_t Bank)
+{
+  uint32_t regvalue = 0;
+  uint32_t bankBase = 0;
+
+  if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_1)
+  {
+    regvalue = FLASH->PRAR_CUR1;
+    bankBase = FLASH_BANK1_BASE;
+  }
+
+  if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_2)
+  {
+    regvalue = FLASH->PRAR_CUR2;
+    bankBase = FLASH_BANK2_BASE;
+  }
+
+  (*PCROPConfig) =  (regvalue & FLASH_PRAR_DMEP);
+
+  (*PCROPStartAddr) = ((regvalue & FLASH_PRAR_PROT_AREA_START) << 8) + bankBase;
+  (*PCROPEndAddr) = (regvalue & FLASH_PRAR_PROT_AREA_END) >> FLASH_PRAR_PROT_AREA_END_Pos;
+  (*PCROPEndAddr) = ((*PCROPEndAddr) << 8) + bankBase;
+}
+
+/**
+  * @brief  Set the BOR Level.
+  * @param  Level specifies the Option Bytes BOR Reset Level.
+  *          This parameter can be one of the following values:
+  *            @arg OB_BOR_LEVEL0: Reset level threshold is set to 1.6V
+  *            @arg OB_BOR_LEVEL1: Reset level threshold is set to 2.1V
+  *            @arg OB_BOR_LEVEL2: Reset level threshold is set to 2.4V
+  *            @arg OB_BOR_LEVEL3: Reset level threshold is set to 2.7V
+  * @retval None
+  */
+static void FLASH_OB_BOR_LevelConfig(uint32_t Level)
+{
+  assert_param(IS_OB_BOR_LEVEL(Level));
+
+  /* Configure BOR_LEV option byte */
+  MODIFY_REG(FLASH->OPTSR_PRG, FLASH_OPTSR_BOR_LEV, Level);
+}
+
+/**
+  * @brief  Get the BOR Level.
+  * @retval The Option Bytes BOR Reset Level.
+  *            This parameter can be one of the following values:
+  *            @arg OB_BOR_LEVEL0: Reset level threshold is set to 1.6V
+  *            @arg OB_BOR_LEVEL1: Reset level threshold is set to 2.1V
+  *            @arg OB_BOR_LEVEL2: Reset level threshold is set to 2.4V
+  *            @arg OB_BOR_LEVEL3: Reset level threshold is set to 2.7V
+  */
+static uint32_t FLASH_OB_GetBOR(void)
+{
+  return (FLASH->OPTSR_CUR & FLASH_OPTSR_BOR_LEV);
+}
+
+/**
+  * @brief  Set Boot address
+  * @param  BootOption Boot address option byte to be programmed,
+  *                     This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION
+                        (OB_BOOT_ADD0, OB_BOOT_ADD1 or OB_BOOT_ADD_BOTH)
+  *
+  * @param  BootAddress0 Specifies the Boot Address 0
+  * @param  BootAddress1 Specifies the Boot Address 1
+  * @retval HAL Status
+  */
+static void FLASH_OB_BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1)
+{
+  /* Check the parameters */
+  assert_param(IS_OB_BOOT_ADD_OPTION(BootOption));
+
+  if((BootOption & OB_BOOT_ADD0) == OB_BOOT_ADD0)
+  {
+    /* Check the parameters */
+    assert_param(IS_BOOT_ADDRESS(BootAddress0));
+
+    /* Configure CM7 BOOT ADD0 */
+#if defined(DUAL_CORE)
+    MODIFY_REG(FLASH->BOOT7_PRG, FLASH_BOOT7_BCM7_ADD0, (BootAddress0 >> 16));
+#else /* Single Core*/
+    MODIFY_REG(FLASH->BOOT_PRG, FLASH_BOOT_ADD0, (BootAddress0 >> 16));
+#endif /* DUAL_CORE */
+  }
+
+  if((BootOption & OB_BOOT_ADD1) == OB_BOOT_ADD1)
+  {
+    /* Check the parameters */
+    assert_param(IS_BOOT_ADDRESS(BootAddress1));
+
+    /* Configure CM7 BOOT ADD1 */
+#if defined(DUAL_CORE)
+    MODIFY_REG(FLASH->BOOT7_PRG, FLASH_BOOT7_BCM7_ADD1, BootAddress1);
+#else /* Single Core*/
+    MODIFY_REG(FLASH->BOOT_PRG, FLASH_BOOT_ADD1, BootAddress1);
+#endif /* DUAL_CORE */
+  }
+}
+
+/**
+  * @brief  Get Boot address
+  * @param  BootAddress0 Specifies the Boot Address 0.
+  * @param  BootAddress1 Specifies the Boot Address 1.
+  * @retval HAL Status
+  */
+static void FLASH_OB_GetBootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1)
+{
+  uint32_t regvalue;
+
+#if defined(DUAL_CORE)
+  regvalue = FLASH->BOOT7_CUR;
+
+  (*BootAddress0) = (regvalue & FLASH_BOOT7_BCM7_ADD0) << 16;
+  (*BootAddress1) = (regvalue & FLASH_BOOT7_BCM7_ADD1);
+#else /* Single Core */
+  regvalue = FLASH->BOOT_CUR;
+
+  (*BootAddress0) = (regvalue & FLASH_BOOT_ADD0) << 16;
+  (*BootAddress1) = (regvalue & FLASH_BOOT_ADD1);
+#endif /* DUAL_CORE */
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Set CM4 Boot address
+  * @param  BootOption Boot address option byte to be programmed,
+  *                     This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION
+                        (OB_BOOT_ADD0, OB_BOOT_ADD1 or OB_BOOT_ADD_BOTH)
+  *
+  * @param  BootAddress0 Specifies the CM4 Boot Address 0.
+  * @param  BootAddress1 Specifies the CM4 Boot Address 1.
+  * @retval HAL Status
+  */
+static void FLASH_OB_CM4BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1)
+{
+  /* Check the parameters */
+  assert_param(IS_OB_BOOT_ADD_OPTION(BootOption));
+
+  if((BootOption & OB_BOOT_ADD0) == OB_BOOT_ADD0)
+  {
+    /* Check the parameters */
+    assert_param(IS_BOOT_ADDRESS(BootAddress0));
+
+    /* Configure CM4 BOOT ADD0 */
+    MODIFY_REG(FLASH->BOOT4_PRG, FLASH_BOOT4_BCM4_ADD0, (BootAddress0 >> 16));
+
+  }
+
+  if((BootOption & OB_BOOT_ADD1) == OB_BOOT_ADD1)
+  {
+    /* Check the parameters */
+    assert_param(IS_BOOT_ADDRESS(BootAddress1));
+
+    /* Configure CM4 BOOT ADD1 */
+    MODIFY_REG(FLASH->BOOT4_PRG, FLASH_BOOT4_BCM4_ADD1, BootAddress1);
+  }
+}
+
+/**
+  * @brief  Get CM4 Boot address
+  * @param  BootAddress0 Specifies the CM4 Boot Address 0.
+  * @param  BootAddress1 Specifies the CM4 Boot Address 1.
+  * @retval HAL Status
+  */
+static void FLASH_OB_GetCM4BootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1)
+{
+  uint32_t regvalue;
+
+  regvalue = FLASH->BOOT4_CUR;
+
+  (*BootAddress0) = (regvalue & FLASH_BOOT4_BCM4_ADD0) << 16;
+  (*BootAddress1) = (regvalue & FLASH_BOOT4_BCM4_ADD1);
+}
+#endif /*DUAL_CORE*/
+
+/**
+  * @brief  Set secure area configuration
+  * @param  SecureAreaConfig specify if the secure area will be deleted or not
+  *         when RDP level decreased from Level 1 to Level 0 or during a mass erase.
+  *
+  * @param  SecureAreaStartAddr Specifies the secure area start address
+  * @param  SecureAreaEndAddr Specifies the secure area end address
+  * @param  Banks the specific bank to apply Security protection
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: Secure area on specified bank1 area
+  *            @arg FLASH_BANK_2: Secure area on specified bank2 area
+  *            @arg FLASH_BANK_BOTH: Secure area on specified bank1 and bank2 area (same config will be applied on both banks)
+  * @retval None
+  */
+static void FLASH_OB_SecureAreaConfig(uint32_t SecureAreaConfig, uint32_t SecureAreaStartAddr, uint32_t SecureAreaEndAddr, uint32_t Banks)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_BANK(Banks));
+  assert_param(IS_OB_SECURE_RDP(SecureAreaConfig));
+
+  if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
+  {
+    /* Check the parameters */
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(SecureAreaStartAddr));
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(SecureAreaEndAddr));
+
+    /* Configure the secure area */
+    FLASH->SCAR_PRG1 = ((SecureAreaStartAddr - FLASH_BANK1_BASE) >> 8)                                | \
+                       (((SecureAreaEndAddr - FLASH_BANK1_BASE) >> 8) << FLASH_SCAR_SEC_AREA_END_Pos) | \
+                       (SecureAreaConfig & FLASH_SCAR_DMES);
+  }
+
+  if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
+  {
+    /* Check the parameters */
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(SecureAreaStartAddr));
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(SecureAreaEndAddr));
+
+    /* Configure the secure area */
+    FLASH->SCAR_PRG2 = ((SecureAreaStartAddr - FLASH_BANK2_BASE) >> 8)                                | \
+                       (((SecureAreaEndAddr - FLASH_BANK2_BASE) >> 8) << FLASH_SCAR_SEC_AREA_END_Pos) | \
+                       (SecureAreaConfig & FLASH_SCAR_DMES);
+  }
+}
+
+/**
+  * @brief  Get secure area configuration
+  * @param  SecureAreaConfig indicates if the secure area will be deleted or not
+  *         when RDP level decreased from Level 1 to Level 0 or during a mass erase.
+  * @param  SecureAreaStartAddr gives the secure area start address
+  * @param  SecureAreaEndAddr gives the secure area end address
+  * @param  Bank Specifies the Bank
+  * @retval None
+  */
+static void FLASH_OB_GetSecureArea(uint32_t *SecureAreaConfig, uint32_t *SecureAreaStartAddr, uint32_t *SecureAreaEndAddr, uint32_t Bank)
+{
+  uint32_t regvalue = 0;
+  uint32_t bankBase = 0;
+
+  /* Check Bank parameter value */
+  if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_1)
+  {
+    regvalue = FLASH->SCAR_CUR1;
+    bankBase = FLASH_BANK1_BASE;
+  }
+
+  if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_2)
+  {
+    regvalue = FLASH->SCAR_CUR2;
+    bankBase = FLASH_BANK2_BASE;
+  }
+
+  /* Get the secure area settings */
+  (*SecureAreaConfig) = (regvalue & FLASH_SCAR_DMES);
+  (*SecureAreaStartAddr) = ((regvalue & FLASH_SCAR_SEC_AREA_START) << 8) + bankBase;
+  (*SecureAreaEndAddr) = (regvalue & FLASH_SCAR_SEC_AREA_END) >> FLASH_SCAR_SEC_AREA_END_Pos;
+  (*SecureAreaEndAddr) = ((*SecureAreaEndAddr) << 8) + bankBase;
+}
+
+/**
+  * @brief  Add a CRC sector to the list of sectors on which the CRC will be calculated
+  * @param  Sector Specifies the CRC sector number
+  * @param  Bank Specifies the Bank
+  * @retval None
+  */
+static void FLASH_CRC_AddSector(uint32_t Sector, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_SECTOR(Sector));
+
+  if (Bank == FLASH_BANK_1)
+  {
+    /* Clear CRC sector */
+    FLASH->CRCCR1 &= (~FLASH_CRCCR_CRC_SECT);
+
+    /* Select CRC Sector and activate ADD_SECT bit */
+    FLASH->CRCCR1 |= Sector | FLASH_CRCCR_ADD_SECT;
+  }
+  else
+  {
+    /* Clear CRC sector */
+    FLASH->CRCCR2 &= (~FLASH_CRCCR_CRC_SECT);
+
+    /* Select CRC Sector and activate ADD_SECT bit */
+    FLASH->CRCCR2 |= Sector | FLASH_CRCCR_ADD_SECT;
+  }
+}
+
+/**
+  * @brief  Select CRC start and end memory addresses on which the CRC will be calculated
+  * @param  CRCStartAddr Specifies the CRC start address
+  * @param  CRCEndAddr Specifies the CRC end address
+  * @param  Bank Specifies the Bank
+  * @retval None
+  */
+static void FLASH_CRC_SelectAddress(uint32_t CRCStartAddr, uint32_t CRCEndAddr, uint32_t Bank)
+{
+  if (Bank == FLASH_BANK_1)
+  {
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(CRCStartAddr));
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(CRCEndAddr));
+
+    /* Write CRC Start and End addresses */
+    FLASH->CRCSADD1 = CRCStartAddr;
+    FLASH->CRCEADD1 = CRCEndAddr;
+  }
+  else
+  {
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(CRCStartAddr));
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(CRCEndAddr));
+
+    /* Write CRC Start and End addresses */
+    FLASH->CRCSADD2 = CRCStartAddr;
+    FLASH->CRCEADD2 = CRCEndAddr;
+  }
+}
+/**
+  * @}
+  */
+
+#if defined (FLASH_OTPBL_LOCKBL)
+/**
+  * @brief  Configure the OTP Block Lock.
+  * @param  OTP_Block specifies the OTP Block to lock.
+  *         This parameter can be a value of @ref FLASHEx_OTP_Blocks
+  * @retval None
+  */
+static void FLASH_OB_OTP_LockConfig(uint32_t OTP_Block)
+{
+  /* Check the parameters */
+  assert_param(IS_OTP_BLOCK(OTP_Block));
+
+  /* Configure the OTP Block lock in the option bytes register */
+  FLASH->OTPBL_PRG |= (OTP_Block & FLASH_OTPBL_LOCKBL);
+}
+
+/**
+  * @brief  Get the OTP Block Lock.
+  * @retval OTP_Block specifies the OTP Block to lock.
+  *         This return value can be a value of @ref FLASHEx_OTP_Blocks
+  */
+static uint32_t FLASH_OB_OTP_GetLock(void)
+{
+  return (FLASH->OTPBL_CUR);
+}
+#endif /* FLASH_OTPBL_LOCKBL */
+
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c
new file mode 100644
index 00000000..13dcc40d
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c
@@ -0,0 +1,560 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_gpio.c
+  * @author  MCD Application Team
+  * @brief   GPIO HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *
+  @verbatim
+  ==============================================================================
+                    ##### GPIO Peripheral features #####
+  ==============================================================================
+  [..]
+    (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
+        configured by software in several modes:
+        (++) Input mode
+        (++) Analog mode
+        (++) Output mode
+        (++) Alternate function mode
+        (++) External interrupt/event lines
+
+    (+) During and just after reset, the alternate functions and external interrupt
+        lines are not active and the I/O ports are configured in input floating mode.
+
+    (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
+        activated or not.
+
+    (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
+        type and the IO speed can be selected depending on the VDD value.
+
+    (+) The microcontroller IO pins are connected to onboard peripherals/modules through a
+        multiplexer that allows only one peripheral alternate function (AF) connected
+       to an IO pin at a time. In this way, there can be no conflict between peripherals
+       sharing the same IO pin.
+
+    (+) All ports have external interrupt/event capability. To use external interrupt
+        lines, the port must be configured in input mode. All available GPIO pins are
+        connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
+
+  The external interrupt/event controller consists of up to 23 edge detectors
+        (16 lines are connected to GPIO) for generating event/interrupt requests (each
+        input line can be independently configured to select the type (interrupt or event)
+        and the corresponding trigger event (rising or falling or both). Each line can
+        also be masked independently.
+
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
+
+    (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
+        (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
+        (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
+             structure.
+        (++) In case of Output or alternate function mode selection: the speed is
+             configured through "Speed" member from GPIO_InitTypeDef structure.
+        (++) In alternate mode is selection, the alternate function connected to the IO
+             is configured through "Alternate" member from GPIO_InitTypeDef structure.
+        (++) Analog mode is required when a pin is to be used as ADC channel
+             or DAC output.
+        (++) In case of external interrupt/event selection the "Mode" member from
+             GPIO_InitTypeDef structure select the type (interrupt or event) and
+             the corresponding trigger event (rising or falling or both).
+
+    (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
+        mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
+        HAL_NVIC_EnableIRQ().
+
+    (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
+
+    (#) To set/reset the level of a pin configured in output mode use
+        HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
+
+   (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
+
+
+    (#) During and just after reset, the alternate functions are not
+        active and the GPIO pins are configured in input floating mode (except JTAG
+        pins).
+
+    (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
+        (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
+        priority over the GPIO function.
+
+    (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
+        general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
+        The HSE has priority over the GPIO function.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup GPIO  GPIO
+  * @brief GPIO HAL module driver
+  * @{
+  */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines ------------------------------------------------------------*/
+/** @addtogroup GPIO_Private_Constants GPIO Private Constants
+  * @{
+  */
+#define GPIO_MODE             (0x00000003U)
+#define ANALOG_MODE           (0x00000008U)
+#define EXTI_MODE             (0x10000000U)
+#define GPIO_MODE_IT          (0x00010000U)
+#define GPIO_MODE_EVT         (0x00020000U)
+#define RISING_EDGE           (0x00100000U)
+#define FALLING_EDGE          (0x00200000U)
+#define GPIO_OUTPUT_TYPE      (0x00000010U)
+
+#if defined(DUAL_CORE)
+#define EXTI_CPU1             (0x01000000U)
+#define EXTI_CPU2             (0x02000000U)
+#endif /*DUAL_CORE*/
+#define GPIO_NUMBER           (16U)
+/**
+  * @}
+  */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
+  * @{
+  */
+
+/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+  [..]
+    This section provides functions allowing to initialize and de-initialize the GPIOs
+    to be ready for use.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
+  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral.
+  * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
+  *         the configuration information for the specified GPIO peripheral.
+  * @retval None
+  */
+void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
+{
+  uint32_t position = 0x00U;
+  uint32_t iocurrent;
+  uint32_t temp;
+  EXTI_Core_TypeDef *EXTI_CurrentCPU;
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */
+#else
+  EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */
+#endif
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
+  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
+  assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
+
+  /* Configure the port pins */
+  while (((GPIO_Init->Pin) >> position) != 0x00U)
+  {
+    /* Get current io position */
+    iocurrent = (GPIO_Init->Pin) & (1UL << position);
+
+    if (iocurrent != 0x00U)
+    {
+      /*--------------------- GPIO Mode Configuration ------------------------*/
+      /* In case of Output or Alternate function mode selection */
+      if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
+          (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+      {
+        /* Check the Speed parameter */
+        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+        /* Configure the IO Speed */
+        temp = GPIOx->OSPEEDR;
+        temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
+        temp |= (GPIO_Init->Speed << (position * 2U));
+        GPIOx->OSPEEDR = temp;
+
+        /* Configure the IO Output Type */
+        temp = GPIOx->OTYPER;
+        temp &= ~(GPIO_OTYPER_OT0 << position) ;
+        temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
+        GPIOx->OTYPER = temp;
+      }
+
+      /* Activate the Pull-up or Pull down resistor for the current IO */
+      temp = GPIOx->PUPDR;
+      temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
+      temp |= ((GPIO_Init->Pull) << (position * 2U));
+      GPIOx->PUPDR = temp;
+
+      /* In case of Alternate function mode selection */
+      if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+      {
+        /* Check the Alternate function parameters */
+        assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
+        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
+
+        /* Configure Alternate function mapped with the current IO */
+        temp = GPIOx->AFR[position >> 3U];
+        temp &= ~(0xFU << ((position & 0x07U) * 4U));
+        temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
+        GPIOx->AFR[position >> 3U] = temp;
+      }
+
+      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+      temp = GPIOx->MODER;
+      temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
+      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
+      GPIOx->MODER = temp;
+
+      /*--------------------- EXTI Mode Configuration ------------------------*/
+      /* Configure the External Interrupt or event for the current IO */
+      if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
+      {
+        /* Enable SYSCFG Clock */
+        __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+        temp = SYSCFG->EXTICR[position >> 2U];
+        temp &= ~(0x0FUL << (4U * (position & 0x03U)));
+        temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
+        SYSCFG->EXTICR[position >> 2U] = temp;
+
+        /* Clear EXTI line configuration */
+        temp = EXTI_CurrentCPU->IMR1;
+        temp &= ~(iocurrent);
+        if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
+        {
+          temp |= iocurrent;
+        }
+        EXTI_CurrentCPU->IMR1 = temp;
+
+        temp = EXTI_CurrentCPU->EMR1;
+        temp &= ~(iocurrent);
+        if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
+        {
+          temp |= iocurrent;
+        }
+        EXTI_CurrentCPU->EMR1 = temp;
+
+        /* Clear Rising Falling edge configuration */
+        temp = EXTI->RTSR1;
+        temp &= ~(iocurrent);
+        if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
+        {
+          temp |= iocurrent;
+        }
+        EXTI->RTSR1 = temp;
+
+        temp = EXTI->FTSR1;
+        temp &= ~(iocurrent);
+        if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
+        {
+          temp |= iocurrent;
+        }
+        EXTI->FTSR1 = temp;
+      }
+    }
+
+    position++;
+  }
+}
+
+/**
+  * @brief  De-initializes the GPIOx peripheral registers to their default reset values.
+  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bit to be written.
+  *          This parameter can be one of GPIO_PIN_x where x can be (0..15).
+  * @retval None
+  */
+void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
+{
+  uint32_t position = 0x00U;
+  uint32_t iocurrent;
+  uint32_t tmp;
+  EXTI_Core_TypeDef *EXTI_CurrentCPU;
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */
+#else
+  EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */
+#endif
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  /* Configure the port pins */
+  while ((GPIO_Pin >> position) != 0x00U)
+  {
+    /* Get current io position */
+    iocurrent = GPIO_Pin & (1UL << position) ;
+
+    if (iocurrent != 0x00U)
+    {
+      /*------------------------- EXTI Mode Configuration --------------------*/
+      /* Clear the External Interrupt or Event for the current IO */
+      tmp = SYSCFG->EXTICR[position >> 2U];
+      tmp &= (0x0FUL << (4U * (position & 0x03U)));
+      if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
+      {
+        /* Clear EXTI line configuration for Current CPU */
+        EXTI_CurrentCPU->IMR1 &= ~(iocurrent);
+        EXTI_CurrentCPU->EMR1 &= ~(iocurrent);
+
+        /* Clear Rising Falling edge configuration */
+        EXTI->RTSR1 &= ~(iocurrent);
+        EXTI->FTSR1 &= ~(iocurrent);
+
+        tmp = 0x0FUL << (4U * (position & 0x03U));
+        SYSCFG->EXTICR[position >> 2U] &= ~tmp;
+      }
+
+      /*------------------------- GPIO Mode Configuration --------------------*/
+      /* Configure IO in Analog Mode */
+      GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2U));
+
+      /* Configure the default Alternate Function in current IO */
+      GPIOx->AFR[position >> 3U] &= ~(0xFU << ((position & 0x07U) * 4U)) ;
+
+      /* Deactivate the Pull-up and Pull-down resistor for the current IO */
+      GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
+
+      /* Configure the default value IO Output Type */
+      GPIOx->OTYPER  &= ~(GPIO_OTYPER_OT0 << position) ;
+
+      /* Configure the default value for IO Speed */
+      GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
+    }
+
+    position++;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
+ *  @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
+ *
+@verbatim
+ ===============================================================================
+                       ##### IO operation functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Reads the specified input port pin.
+  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bit to read.
+  *         This parameter can be GPIO_PIN_x where x can be (0..15).
+  * @retval The input port pin value.
+  */
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+  GPIO_PinState bitstatus;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  if ((GPIOx->IDR & GPIO_Pin) != 0x00U)
+  {
+    bitstatus = GPIO_PIN_SET;
+  }
+  else
+  {
+    bitstatus = GPIO_PIN_RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Sets or clears the selected data port bit.
+  *
+  * @note   This function uses GPIOx_BSRR register to allow atomic read/modify
+  *         accesses. In this way, there is no risk of an IRQ occurring between
+  *         the read and the modify access.
+  *
+  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bit to be written.
+  *          This parameter can be one of GPIO_PIN_x where x can be (0..15).
+  * @param  PinState: specifies the value to be written to the selected bit.
+  *          This parameter can be one of the GPIO_PinState enum values:
+  *            @arg GPIO_PIN_RESET: to clear the port pin
+  *            @arg GPIO_PIN_SET: to set the port pin
+  * @retval None
+  */
+void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+  assert_param(IS_GPIO_PIN_ACTION(PinState));
+
+  if (PinState != GPIO_PIN_RESET)
+  {
+    GPIOx->BSRR = GPIO_Pin;
+  }
+  else
+  {
+    GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
+  }
+}
+
+/**
+  * @brief  Toggles the specified GPIO pins.
+  * @param  GPIOx: Where x can be (A..K) to select the GPIO peripheral.
+  * @param  GPIO_Pin: Specifies the pins to be toggled.
+  * @retval None
+  */
+void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  if ((GPIOx->ODR & GPIO_Pin) == GPIO_Pin)
+  {
+    GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
+  }
+  else
+  {
+    GPIOx->BSRR = GPIO_Pin;
+  }
+}
+
+/**
+  * @brief  Locks GPIO Pins configuration registers.
+  * @note   The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
+  *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
+  * @note   The configuration of the locked GPIO pins can no longer be modified
+  *         until the next reset.
+  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32H7 family
+  * @param  GPIO_Pin: specifies the port bit to be locked.
+  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+  __IO uint32_t tmp = GPIO_LCKR_LCKK;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  /* Apply lock key write sequence */
+  tmp |= GPIO_Pin;
+  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+  GPIOx->LCKR = tmp;
+  /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
+  GPIOx->LCKR = GPIO_Pin;
+  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+  GPIOx->LCKR = tmp;
+  /* Read LCKK register. This read is mandatory to complete key lock sequence*/
+  tmp = GPIOx->LCKR;
+
+  /* read again in order to confirm lock is active */
+  if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00U)
+  {
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Handle EXTI interrupt request.
+  * @param  GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
+  * @retval None
+  */
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
+{
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  if (__HAL_GPIO_EXTID2_GET_IT(GPIO_Pin) != 0x00U)
+  {
+    __HAL_GPIO_EXTID2_CLEAR_IT(GPIO_Pin);
+    HAL_GPIO_EXTI_Callback(GPIO_Pin);
+  }
+#else
+  /* EXTI line interrupt detected */
+  if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00U)
+  {
+    __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
+    HAL_GPIO_EXTI_Callback(GPIO_Pin);
+  }
+#endif
+}
+
+/**
+  * @brief  EXTI line detection callback.
+  * @param  GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
+  * @retval None
+  */
+__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(GPIO_Pin);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+           the HAL_GPIO_EXTI_Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+#endif /* HAL_GPIO_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c
new file mode 100644
index 00000000..1fab0cef
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c
@@ -0,0 +1,441 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_hsem.c
+  * @author  MCD Application Team
+  * @brief   HSEM HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the semaphore peripheral:
+  *           + Semaphore Take function (2-Step Procedure) , non blocking
+  *           + Semaphore FastTake function (1-Step Procedure) , non blocking
+  *           + Semaphore Status check
+  *           + Semaphore Clear Key Set and Get
+  *           + Release and release all functions
+  *           + Semaphore notification enabling and disabling and callnack functions
+  *           + IRQ handler management
+  *
+  *
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+      (#)Take a semaphore In 2-Step mode Using function HAL_HSEM_Take. This function takes as parameters :
+           (++) the semaphore ID from 0 to 31
+           (++) the process ID from 0 to 255
+      (#) Fast Take semaphore In 1-Step mode Using function HAL_HSEM_FastTake. This function takes as parameter :
+           (++) the semaphore ID from 0_ID to 31. Note that the process ID value is implicitly assumed as zero
+      (#) Check if a semaphore is Taken using function HAL_HSEM_IsSemTaken. This function takes as parameter :
+          (++) the semaphore ID from 0_ID to 31
+          (++) It returns 1 if the given semaphore is taken otherwise (Free) zero
+      (#)Release a semaphore using function with HAL_HSEM_Release. This function takes as parameters :
+           (++) the semaphore ID from 0 to 31
+           (++) the process ID from 0 to 255:
+           (++) Note: If ProcessID and MasterID match, semaphore is freed, and an interrupt
+         may be generated when enabled (notification activated). If ProcessID or MasterID does not match,
+         semaphore remains taken (locked)
+
+      (#)Release all semaphores at once taken by a given Master using function HAL_HSEM_Release_All
+          This function takes as parameters :
+           (++) the Release Key (value from 0 to 0xFFFF) can be Set or Get respectively by
+              HAL_HSEM_SetClearKey() or HAL_HSEM_GetClearKey functions
+           (++) the Master ID:
+           (++) Note: If the Key and MasterID match, all semaphores taken by the given CPU that corresponds
+           to MasterID  will be freed, and an interrupt may be generated when enabled (notification activated). If the
+           Key or the MasterID doesn't match, semaphores remains taken (locked)
+
+      (#)Semaphores Release all key functions:
+         (++)  HAL_HSEM_SetClearKey() to set semaphore release all Key
+         (++)  HAL_HSEM_GetClearKey() to get release all Key
+      (#)Semaphores notification functions :
+         (++)  HAL_HSEM_ActivateNotification to activate a notification callback on
+               a given semaphores Mask (bitfield). When one or more semaphores defined by the mask are released
+               the callback HAL_HSEM_FreeCallback will be asserted giving as parameters a mask of the released
+               semaphores (bitfield).
+
+         (++)  HAL_HSEM_DeactivateNotification to deactivate the notification of a given semaphores Mask (bitfield).
+         (++) See the description of the macro __HAL_HSEM_SEMID_TO_MASK to check how to calculate a semaphore mask
+                Used by the notification functions
+     *** HSEM HAL driver macros list ***
+     =============================================
+     [..] Below the list of most used macros in HSEM HAL driver.
+
+      (+) __HAL_HSEM_SEMID_TO_MASK: Helper macro to convert a Semaphore ID to a Mask.
+      [..] Example of use :
+      [..] mask = __HAL_HSEM_SEMID_TO_MASK(8)  |  __HAL_HSEM_SEMID_TO_MASK(21) | __HAL_HSEM_SEMID_TO_MASK(25).
+      [..] All next macros take as parameter a semaphore Mask (bitfiled) that can be constructed using  __HAL_HSEM_SEMID_TO_MASK as the above example.
+      (+) __HAL_HSEM_ENABLE_IT: Enable the specified semaphores Mask interrupts.
+      (+) __HAL_HSEM_DISABLE_IT: Disable the specified semaphores Mask interrupts.
+      (+) __HAL_HSEM_GET_IT: Checks whether the specified semaphore interrupt has occurred or not.
+      (+) __HAL_HSEM_GET_FLAG: Get the semaphores status release flags.
+      (+) __HAL_HSEM_CLEAR_FLAG: Clear the semaphores status release flags.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup HSEM HSEM
+  * @brief HSEM HAL module driver
+  * @{
+  */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#if defined(DUAL_CORE)
+#ifndef HSEM_R_MASTERID
+#define HSEM_R_MASTERID HSEM_R_COREID
+#endif
+
+#ifndef HSEM_RLR_MASTERID
+#define HSEM_RLR_MASTERID HSEM_RLR_COREID
+#endif
+
+#ifndef HSEM_CR_MASTERID
+#define HSEM_CR_MASTERID HSEM_CR_COREID
+#endif
+#endif /* DUAL_CORE */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup HSEM_Exported_Functions  HSEM Exported Functions
+  * @{
+  */
+
+/** @defgroup HSEM_Exported_Functions_Group1 Take and Release functions
+  *  @brief    HSEM Take and Release functions
+  *
+@verbatim
+ ==============================================================================
+              ##### HSEM Take and Release functions #####
+ ==============================================================================
+[..] This section provides functions allowing to:
+      (+) Take a semaphore with 2 Step method
+      (+) Fast Take a semaphore with 1 Step method
+      (+) Check semaphore state Taken or not
+      (+) Release a semaphore
+      (+) Release all semaphore at once
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Take a semaphore in 2 Step mode.
+  * @param  SemID: semaphore ID from 0 to 31
+  * @param  ProcessID: Process ID from 0 to 255
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID)
+{
+  /* Check the parameters */
+  assert_param(IS_HSEM_SEMID(SemID));
+  assert_param(IS_HSEM_PROCESSID(ProcessID));
+
+#if  USE_MULTI_CORE_SHARED_CODE != 0U
+  /* First step  write R register with MasterID, processID and take bit=1*/
+  HSEM->R[SemID] = ((ProcessID & HSEM_R_PROCID) | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID) | HSEM_R_LOCK);
+
+  /* second step : read the R register . Take achieved if MasterID and processID match and take bit set to 1 */
+  if (HSEM->R[SemID] == ((ProcessID & HSEM_R_PROCID) | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID) | HSEM_R_LOCK))
+  {
+    /*take success when MasterID and ProcessID match and take bit set*/
+    return HAL_OK;
+  }
+#else
+  /* First step  write R register with MasterID, processID and take bit=1*/
+  HSEM->R[SemID] = (ProcessID | HSEM_CR_COREID_CURRENT | HSEM_R_LOCK);
+
+  /* second step : read the R register . Take achieved if MasterID and processID match and take bit set to 1 */
+  if (HSEM->R[SemID] == (ProcessID | HSEM_CR_COREID_CURRENT | HSEM_R_LOCK))
+  {
+    /*take success when MasterID and ProcessID match and take bit set*/
+    return HAL_OK;
+  }
+#endif
+
+  /* Semaphore take fails*/
+  return HAL_ERROR;
+}
+
+/**
+  * @brief  Fast Take a semaphore with 1 Step mode.
+  * @param  SemID: semaphore ID from 0 to 31
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HSEM_FastTake(uint32_t SemID)
+{
+  /* Check the parameters */
+  assert_param(IS_HSEM_SEMID(SemID));
+
+#if  USE_MULTI_CORE_SHARED_CODE != 0U
+  /* Read the RLR register to take the semaphore */
+  if (HSEM->RLR[SemID] == (((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_RLR_MASTERID) | HSEM_RLR_LOCK))
+  {
+    /*take success when MasterID match and take bit set*/
+    return HAL_OK;
+  }
+#else
+  /* Read the RLR register to take the semaphore */
+  if (HSEM->RLR[SemID] == (HSEM_CR_COREID_CURRENT | HSEM_RLR_LOCK))
+  {
+    /*take success when MasterID match and take bit set*/
+    return HAL_OK;
+  }
+#endif
+
+  /* Semaphore take fails */
+  return HAL_ERROR;
+}
+/**
+  * @brief  Check semaphore state Taken or not.
+  * @param  SemID: semaphore ID
+  * @retval HAL HSEM state
+  */
+uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID)
+{
+  return (((HSEM->R[SemID] & HSEM_R_LOCK) != 0U) ? 1UL : 0UL);
+}
+
+
+/**
+  * @brief  Release a semaphore.
+  * @param  SemID: semaphore ID from 0 to 31
+  * @param  ProcessID: Process ID from 0 to 255
+  * @retval None
+  */
+void  HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID)
+{
+  /* Check the parameters */
+  assert_param(IS_HSEM_SEMID(SemID));
+  assert_param(IS_HSEM_PROCESSID(ProcessID));
+
+  /* Clear the semaphore by writing to the R register : the MasterID , the processID and take bit = 0  */
+#if  USE_MULTI_CORE_SHARED_CODE != 0U
+  HSEM->R[SemID] = (ProcessID | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID));
+#else
+  HSEM->R[SemID] = (ProcessID | HSEM_CR_COREID_CURRENT);
+#endif
+
+}
+
+/**
+  * @brief  Release All semaphore used by a given Master .
+  * @param  Key: Semaphore Key , value from 0 to 0xFFFF
+  * @param  CoreID: CoreID of the CPU that is using semaphores to be released
+  * @retval None
+  */
+void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t CoreID)
+{
+  assert_param(IS_HSEM_KEY(Key));
+  assert_param(IS_HSEM_COREID(CoreID));
+
+  HSEM->CR = ((Key << HSEM_CR_KEY_Pos) | (CoreID << HSEM_CR_COREID_Pos));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HSEM_Exported_Functions_Group2 HSEM Set and Get Key functions
+  *  @brief    HSEM Set and Get Key functions.
+  *
+@verbatim
+  ==============================================================================
+              ##### HSEM Set and Get Key functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Set semaphore Key
+      (+) Get semaphore Key
+@endverbatim
+
+  * @{
+  */
+
+/**
+  * @brief  Set semaphore Key .
+  * @param  Key: Semaphore Key , value from 0 to 0xFFFF
+  * @retval None
+  */
+void  HAL_HSEM_SetClearKey(uint32_t Key)
+{
+  assert_param(IS_HSEM_KEY(Key));
+
+  MODIFY_REG(HSEM->KEYR, HSEM_KEYR_KEY, (Key << HSEM_KEYR_KEY_Pos));
+
+}
+
+/**
+  * @brief  Get semaphore Key .
+  * @retval Semaphore Key , value from 0 to 0xFFFF
+  */
+uint32_t HAL_HSEM_GetClearKey(void)
+{
+  return (HSEM->KEYR >> HSEM_KEYR_KEY_Pos);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HSEM_Exported_Functions_Group3 HSEM IRQ handler management
+  *  @brief    HSEM Notification functions.
+  *
+@verbatim
+  ==============================================================================
+      ##### HSEM IRQ handler management and Notification functions #####
+  ==============================================================================
+[..]  This section provides HSEM IRQ handler and Notification function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Activate Semaphore release Notification for a given Semaphores Mask .
+  * @param  SemMask: Mask of Released semaphores
+  * @retval Semaphore Key
+  */
+void HAL_HSEM_ActivateNotification(uint32_t SemMask)
+{
+#if  USE_MULTI_CORE_SHARED_CODE != 0U
+  /*enable the semaphore mask interrupts */
+  if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID)
+  {
+    /*Use interrupt line 0 for CPU1 Master */
+    HSEM->C1IER |= SemMask;
+  }
+  else /* HSEM_CPU2_COREID */
+  {
+    /*Use interrupt line 1 for CPU2 Master*/
+    HSEM->C2IER |= SemMask;
+  }
+#else
+  HSEM_COMMON->IER |= SemMask;
+#endif
+}
+
+/**
+  * @brief  Deactivate Semaphore release Notification for a given Semaphores Mask .
+  * @param  SemMask: Mask of Released semaphores
+  * @retval Semaphore Key
+  */
+void HAL_HSEM_DeactivateNotification(uint32_t SemMask)
+{
+#if  USE_MULTI_CORE_SHARED_CODE != 0U
+  /*enable the semaphore mask interrupts */
+  if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID)
+  {
+    /*Use interrupt line 0 for CPU1 Master */
+    HSEM->C1IER &= ~SemMask;
+  }
+  else /* HSEM_CPU2_COREID */
+  {
+    /*Use interrupt line 1 for CPU2 Master*/
+    HSEM->C2IER &= ~SemMask;
+  }
+#else
+  HSEM_COMMON->IER &= ~SemMask;
+#endif
+}
+
+/**
+  * @brief  This function handles HSEM interrupt request
+  * @retval None
+  */
+void HAL_HSEM_IRQHandler(void)
+{
+  uint32_t statusreg;
+#if  USE_MULTI_CORE_SHARED_CODE != 0U
+  if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID)
+  {
+    /* Get the list of masked freed semaphores*/
+    statusreg = HSEM->C1MISR; /*Use interrupt line 0 for CPU1 Master*/
+
+    /*Disable Interrupts*/
+    HSEM->C1IER &= ~((uint32_t)statusreg);
+
+    /*Clear Flags*/
+    HSEM->C1ICR = ((uint32_t)statusreg);
+  }
+  else /* HSEM_CPU2_COREID */
+  {
+    /* Get the list of masked freed semaphores*/
+    statusreg = HSEM->C2MISR;/*Use interrupt line 1 for CPU2 Master*/
+
+    /*Disable Interrupts*/
+    HSEM->C2IER &= ~((uint32_t)statusreg);
+
+    /*Clear Flags*/
+    HSEM->C2ICR = ((uint32_t)statusreg);
+  }
+#else
+  /* Get the list of masked freed semaphores*/
+  statusreg = HSEM_COMMON->MISR;
+
+  /*Disable Interrupts*/
+  HSEM_COMMON->IER &= ~((uint32_t)statusreg);
+
+  /*Clear Flags*/
+  HSEM_COMMON->ICR = ((uint32_t)statusreg);
+
+#endif
+  /* Call FreeCallback */
+  HAL_HSEM_FreeCallback(statusreg);
+}
+
+/**
+  * @brief Semaphore Released Callback.
+  * @param SemMask: Mask of Released semaphores
+  * @retval None
+  */
+__weak void HAL_HSEM_FreeCallback(uint32_t SemMask)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(SemMask);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+  the HAL_HSEM_FreeCallback can be implemented in the user file
+    */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_HSEM_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c
new file mode 100644
index 00000000..7c05d16f
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c
@@ -0,0 +1,6635 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_i2c.c
+  * @author  MCD Application Team
+  * @brief   I2C HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Inter Integrated Circuit (I2C) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral State and Errors functions
+  *
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The I2C HAL driver can be used as follows:
+
+    (#) Declare a I2C_HandleTypeDef handle structure, for example:
+        I2C_HandleTypeDef  hi2c;
+
+    (#)Initialize the I2C low level resources by implementing the @ref HAL_I2C_MspInit() API:
+        (##) Enable the I2Cx interface clock
+        (##) I2C pins configuration
+            (+++) Enable the clock for the I2C GPIOs
+            (+++) Configure I2C pins as alternate function open-drain
+        (##) NVIC configuration if you need to use interrupt process
+            (+++) Configure the I2Cx interrupt priority
+            (+++) Enable the NVIC I2C IRQ Channel
+        (##) DMA Configuration if you need to use DMA process
+            (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream or channel depends on Instance
+            (+++) Enable the DMAx interface clock using
+            (+++) Configure the DMA handle parameters
+            (+++) Configure the DMA Tx or Rx stream or channel depends on Instance
+            (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
+            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
+                  the DMA Tx or Rx stream or channel depends on Instance
+
+    (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
+        Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
+
+    (#) Initialize the I2C registers by calling the @ref HAL_I2C_Init(), configures also the low level Hardware
+        (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_I2C_MspInit(&hi2c) API.
+
+    (#) To check if target device is ready for communication, use the function @ref HAL_I2C_IsDeviceReady()
+
+    (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
+
+    *** Polling mode IO operation ***
+    =================================
+    [..]
+      (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Transmit()
+      (+) Receive in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Receive()
+      (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Transmit()
+      (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Receive()
+
+    *** Polling mode IO MEM operation ***
+    =====================================
+    [..]
+      (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_I2C_Mem_Write()
+      (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_I2C_Mem_Read()
+
+
+    *** Interrupt mode IO operation ***
+    ===================================
+    [..]
+      (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Transmit_IT()
+      (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
+      (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Receive_IT()
+      (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
+      (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Transmit_IT()
+      (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
+      (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Receive_IT()
+      (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
+      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
+      (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
+      (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
+      (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.
+           This action will inform Master to generate a Stop condition to discard the communication.
+
+
+    *** Interrupt mode or DMA mode IO sequential operation ***
+    ==========================================================
+    [..]
+      (@) These interfaces allow to manage a sequential transfer with a repeated start condition
+          when a direction change during transfer
+    [..]
+      (+) A specific option field manage the different steps of a sequential transfer
+      (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:
+      (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
+      (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
+                            and data to transfer without a final stop condition
+      (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
+                            and data to transfer without a final stop condition, an then permit a call the same master sequential interface
+                            several times (like @ref HAL_I2C_Master_Seq_Transmit_IT() then @ref HAL_I2C_Master_Seq_Transmit_IT()
+                            or @ref HAL_I2C_Master_Seq_Transmit_DMA() then @ref HAL_I2C_Master_Seq_Transmit_DMA())
+      (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
+                            and with new data to transfer if the direction change or manage only the new data to transfer
+                            if no direction change and without a final stop condition in both cases
+      (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
+                            and with new data to transfer if the direction change or manage only the new data to transfer
+                            if no direction change and with a final stop condition in both cases
+      (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential
+                            interface several times (link with option I2C_FIRST_AND_NEXT_FRAME).
+                            Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
+                              or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
+                              or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
+                              or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME).
+                            Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit
+                              without stopping the communication and so generate a restart condition.
+      (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential
+                            interface.
+                            Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
+                              or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
+                              or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
+                              or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME).
+                            Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition.
+
+      (+) Differents sequential I2C interfaces are listed below:
+      (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT()
+            or using @ref HAL_I2C_Master_Seq_Transmit_DMA()
+      (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
+      (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Receive_IT()
+            or using @ref HAL_I2C_Master_Seq_Receive_DMA()
+      (+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
+      (++) Abort a master IT or DMA I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
+      (+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
+      (++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen_IT() @ref HAL_I2C_DisableListen_IT()
+      (+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and user can
+           add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
+      (+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback()
+      (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Transmit_IT()
+            or using @ref HAL_I2C_Slave_Seq_Transmit_DMA()
+      (+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
+      (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Receive_IT()
+            or using @ref HAL_I2C_Slave_Seq_Receive_DMA()
+      (+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
+      (++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
+      (++) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.
+           This action will inform Master to generate a Stop condition to discard the communication.
+
+    *** Interrupt mode IO MEM operation ***
+    =======================================
+    [..]
+      (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
+          @ref HAL_I2C_Mem_Write_IT()
+      (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()
+      (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
+          @ref HAL_I2C_Mem_Read_IT()
+      (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()
+      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
+
+    *** DMA mode IO operation ***
+    ==============================
+    [..]
+      (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
+          @ref HAL_I2C_Master_Transmit_DMA()
+      (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
+      (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
+          @ref HAL_I2C_Master_Receive_DMA()
+      (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
+      (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
+          @ref HAL_I2C_Slave_Transmit_DMA()
+      (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
+      (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
+          @ref HAL_I2C_Slave_Receive_DMA()
+      (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
+      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
+      (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
+      (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
+      (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.
+           This action will inform Master to generate a Stop condition to discard the communication.
+
+    *** DMA mode IO MEM operation ***
+    =================================
+    [..]
+      (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
+          @ref HAL_I2C_Mem_Write_DMA()
+      (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()
+      (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
+          @ref HAL_I2C_Mem_Read_DMA()
+      (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()
+      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
+
+
+     *** I2C HAL driver macros list ***
+     ==================================
+     [..]
+       Below the list of most used macros in I2C HAL driver.
+
+      (+) @ref __HAL_I2C_ENABLE: Enable the I2C peripheral
+      (+) @ref __HAL_I2C_DISABLE: Disable the I2C peripheral
+      (+) @ref __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
+      (+) @ref __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
+      (+) @ref __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
+      (+) @ref __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
+      (+) @ref __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
+
+     *** Callback registration ***
+     =============================================
+    [..]
+     The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
+     allows the user to configure dynamically the driver callbacks.
+     Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback()
+     to register an interrupt callback.
+    [..]
+     Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks:
+       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+       (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
+       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
+       (+) ListenCpltCallback   : callback for end of listen mode.
+       (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.
+       (+) MemRxCpltCallback    : callback for Memory reception end of transfer.
+       (+) ErrorCallback        : callback for error detection.
+       (+) AbortCpltCallback    : callback for abort completion process.
+       (+) MspInitCallback      : callback for Msp Init.
+       (+) MspDeInitCallback    : callback for Msp DeInit.
+     This function takes as parameters the HAL peripheral handle, the Callback ID
+     and a pointer to the user callback function.
+    [..]
+     For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback().
+    [..]
+     Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default
+     weak function.
+     @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
+     and the Callback ID.
+     This function allows to reset following callbacks:
+       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+       (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
+       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
+       (+) ListenCpltCallback   : callback for end of listen mode.
+       (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.
+       (+) MemRxCpltCallback    : callback for Memory reception end of transfer.
+       (+) ErrorCallback        : callback for error detection.
+       (+) AbortCpltCallback    : callback for abort completion process.
+       (+) MspInitCallback      : callback for Msp Init.
+       (+) MspDeInitCallback    : callback for Msp DeInit.
+    [..]
+     For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback().
+    [..]
+     By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET
+     all callbacks are set to the corresponding weak functions:
+     examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback().
+     Exception done for MspInit and MspDeInit functions that are
+     reset to the legacy weak functions in the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() only when
+     these callbacks are null (not registered beforehand).
+     If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit()
+     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+    [..]
+     Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.
+     Exception done MspInit/MspDeInit functions that can be registered/unregistered
+     in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,
+     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+     Then, the user first registers the MspInit/MspDeInit user callbacks
+     using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit()
+     or @ref HAL_I2C_Init() function.
+    [..]
+     When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
+     not defined, the callback registration feature is not available and all callbacks
+     are set to the corresponding weak functions.
+
+     [..]
+       (@) You can refer to the I2C HAL driver header file for more useful macros
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup I2C I2C
+  * @brief I2C HAL module driver
+  * @{
+  */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup I2C_Private_Define I2C Private Define
+  * @{
+  */
+#define TIMING_CLEAR_MASK   (0xF0FFFFFFU)  /*!< I2C TIMING clear register Mask */
+#define I2C_TIMEOUT_ADDR    (10000U)       /*!< 10 s  */
+#define I2C_TIMEOUT_BUSY    (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_DIR     (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_RXNE    (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_STOPF   (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_TC      (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_TCR     (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_TXIS    (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_FLAG    (25U)          /*!< 25 ms */
+
+#define MAX_NBYTE_SIZE      255U
+#define SlaveAddr_SHIFT     7U
+#define SlaveAddr_MSK       0x06U
+
+/* Private define for @ref PreviousState usage */
+#define I2C_STATE_MSK             ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits            */
+#define I2C_STATE_NONE            ((uint32_t)(HAL_I2C_MODE_NONE))                                                        /*!< Default Value                                          */
+#define I2C_STATE_MASTER_BUSY_TX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER))            /*!< Master Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MASTER_BUSY_RX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER))            /*!< Master Busy RX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_SLAVE_BUSY_TX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE))             /*!< Slave Busy TX, combinaison of State LSB and Mode enum  */
+#define I2C_STATE_SLAVE_BUSY_RX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE))             /*!< Slave Busy RX, combinaison of State LSB and Mode enum  */
+#define I2C_STATE_MEM_BUSY_TX     ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM))               /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MEM_BUSY_RX     ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM))               /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
+
+
+/* Private define to centralize the enable/disable of Interrupts */
+#define I2C_XFER_TX_IT          (uint16_t)(0x0001U)   /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */
+#define I2C_XFER_RX_IT          (uint16_t)(0x0002U)   /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */
+#define I2C_XFER_LISTEN_IT      (uint16_t)(0x8000U)   /* Bit field can be combinated with @ref I2C_XFER_TX_IT and @ref I2C_XFER_RX_IT */
+
+#define I2C_XFER_ERROR_IT       (uint16_t)(0x0010U)   /* Bit definition to manage addition of global Error and NACK treatment */
+#define I2C_XFER_CPLT_IT        (uint16_t)(0x0020U)   /* Bit definition to manage only STOP evenement */
+#define I2C_XFER_RELOAD_IT      (uint16_t)(0x0040U)   /* Bit definition to manage only Reload of NBYTE */
+
+/* Private define Sequential Transfer Options default/reset value */
+#define I2C_NO_OPTION_FRAME     (0xFFFF0000U)
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/** @defgroup I2C_Private_Functions I2C Private Functions
+  * @{
+  */
+/* Private functions to handle DMA transfer */
+static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMAError(DMA_HandleTypeDef *hdma);
+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
+
+/* Private functions to handle IT transfer */
+static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c);
+static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c);
+static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
+
+/* Private functions to handle IT transfer */
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
+
+/* Private functions for I2C transfer IRQ handler */
+static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
+
+/* Private functions to handle flags during polling transfer */
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+
+/* Private functions to centralize the enable/disable of Interrupts */
+static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
+static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
+
+/* Private function to treat different error callback */
+static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c);
+
+/* Private function to flush TXDR register */
+static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
+
+/* Private function to handle  start, restart or stop a transfer */
+static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
+
+/* Private function to Convert Specific options */
+static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Functions I2C Exported Functions
+  * @{
+  */
+
+/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This subsection provides a set of functions allowing to initialize and
+          deinitialize the I2Cx peripheral:
+
+      (+) User must Implement HAL_I2C_MspInit() function in which he configures
+          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+      (+) Call the function HAL_I2C_Init() to configure the selected device with
+          the selected configuration:
+        (++) Clock Timing
+        (++) Own Address 1
+        (++) Addressing mode (Master, Slave)
+        (++) Dual Addressing mode
+        (++) Own Address 2
+        (++) Own Address 2 Mask
+        (++) General call mode
+        (++) Nostretch mode
+
+      (+) Call the function HAL_I2C_DeInit() to restore the default configuration
+          of the selected I2Cx peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the I2C according to the specified parameters
+  *         in the I2C_InitTypeDef and initialize the associated handle.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
+{
+  /* Check the I2C handle allocation */
+  if (hi2c == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
+  assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
+  assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
+  assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
+  assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
+  assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
+  assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
+
+  if (hi2c->State == HAL_I2C_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hi2c->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    /* Init the I2C Callback settings */
+    hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
+    hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
+    hi2c->SlaveTxCpltCallback  = HAL_I2C_SlaveTxCpltCallback;  /* Legacy weak SlaveTxCpltCallback  */
+    hi2c->SlaveRxCpltCallback  = HAL_I2C_SlaveRxCpltCallback;  /* Legacy weak SlaveRxCpltCallback  */
+    hi2c->ListenCpltCallback   = HAL_I2C_ListenCpltCallback;   /* Legacy weak ListenCpltCallback   */
+    hi2c->MemTxCpltCallback    = HAL_I2C_MemTxCpltCallback;    /* Legacy weak MemTxCpltCallback    */
+    hi2c->MemRxCpltCallback    = HAL_I2C_MemRxCpltCallback;    /* Legacy weak MemRxCpltCallback    */
+    hi2c->ErrorCallback        = HAL_I2C_ErrorCallback;        /* Legacy weak ErrorCallback        */
+    hi2c->AbortCpltCallback    = HAL_I2C_AbortCpltCallback;    /* Legacy weak AbortCpltCallback    */
+    hi2c->AddrCallback         = HAL_I2C_AddrCallback;         /* Legacy weak AddrCallback         */
+
+    if (hi2c->MspInitCallback == NULL)
+    {
+      hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit  */
+    }
+
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+    hi2c->MspInitCallback(hi2c);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+    HAL_I2C_MspInit(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+
+  hi2c->State = HAL_I2C_STATE_BUSY;
+
+  /* Disable the selected I2C peripheral */
+  __HAL_I2C_DISABLE(hi2c);
+
+  /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
+  /* Configure I2Cx: Frequency range */
+  hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
+
+  /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
+  /* Disable Own Address1 before set the Own Address1 configuration */
+  hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
+
+  /* Configure I2Cx: Own Address1 and ack own address1 mode */
+  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
+  {
+    hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
+  }
+  else /* I2C_ADDRESSINGMODE_10BIT */
+  {
+    hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
+  }
+
+  /*---------------------------- I2Cx CR2 Configuration ----------------------*/
+  /* Configure I2Cx: Addressing Master mode */
+  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+  {
+    hi2c->Instance->CR2 = (I2C_CR2_ADD10);
+  }
+  /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
+  hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
+
+  /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
+  /* Disable Own Address2 before set the Own Address2 configuration */
+  hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
+
+  /* Configure I2Cx: Dual mode and Own Address2 */
+  hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));
+
+  /*---------------------------- I2Cx CR1 Configuration ----------------------*/
+  /* Configure I2Cx: Generalcall and NoStretch mode */
+  hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
+
+  /* Enable the selected I2C peripheral */
+  __HAL_I2C_ENABLE(hi2c);
+
+  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+  hi2c->State = HAL_I2C_STATE_READY;
+  hi2c->PreviousState = I2C_STATE_NONE;
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the I2C peripheral.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
+{
+  /* Check the I2C handle allocation */
+  if (hi2c == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+
+  hi2c->State = HAL_I2C_STATE_BUSY;
+
+  /* Disable the I2C Peripheral Clock */
+  __HAL_I2C_DISABLE(hi2c);
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+  if (hi2c->MspDeInitCallback == NULL)
+  {
+    hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit  */
+  }
+
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  hi2c->MspDeInitCallback(hi2c);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_I2C_MspDeInit(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+
+  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+  hi2c->State = HAL_I2C_STATE_RESET;
+  hi2c->PreviousState = I2C_STATE_NONE;
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Initialize the I2C MSP.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief DeInitialize the I2C MSP.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MspDeInit could be implemented in the user file
+   */
+}
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User I2C Callback
+  *         To be used instead of the weak predefined callback
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+  *          @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
+  *          @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
+  *          @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
+  *          @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hi2c);
+
+  if (HAL_I2C_STATE_READY == hi2c->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
+        hi2c->MasterTxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
+        hi2c->MasterRxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
+        hi2c->SlaveTxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
+        hi2c->SlaveRxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_LISTEN_COMPLETE_CB_ID :
+        hi2c->ListenCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
+        hi2c->MemTxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
+        hi2c->MemRxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_ERROR_CB_ID :
+        hi2c->ErrorCallback = pCallback;
+        break;
+
+      case HAL_I2C_ABORT_CB_ID :
+        hi2c->AbortCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_MSPINIT_CB_ID :
+        hi2c->MspInitCallback = pCallback;
+        break;
+
+      case HAL_I2C_MSPDEINIT_CB_ID :
+        hi2c->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_I2C_STATE_RESET == hi2c->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_I2C_MSPINIT_CB_ID :
+        hi2c->MspInitCallback = pCallback;
+        break;
+
+      case HAL_I2C_MSPDEINIT_CB_ID :
+        hi2c->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hi2c);
+  return status;
+}
+
+/**
+  * @brief  Unregister an I2C Callback
+  *         I2C callback is redirected to the weak predefined callback
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+  *          @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
+  *          @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
+  *          @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
+  *          @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hi2c);
+
+  if (HAL_I2C_STATE_READY == hi2c->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
+        hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
+        break;
+
+      case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
+        hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
+        break;
+
+      case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
+        hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback;   /* Legacy weak SlaveTxCpltCallback  */
+        break;
+
+      case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
+        hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback;   /* Legacy weak SlaveRxCpltCallback  */
+        break;
+
+      case HAL_I2C_LISTEN_COMPLETE_CB_ID :
+        hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback;     /* Legacy weak ListenCpltCallback   */
+        break;
+
+      case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
+        hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback;       /* Legacy weak MemTxCpltCallback    */
+        break;
+
+      case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
+        hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback;       /* Legacy weak MemRxCpltCallback    */
+        break;
+
+      case HAL_I2C_ERROR_CB_ID :
+        hi2c->ErrorCallback = HAL_I2C_ErrorCallback;               /* Legacy weak ErrorCallback        */
+        break;
+
+      case HAL_I2C_ABORT_CB_ID :
+        hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback;       /* Legacy weak AbortCpltCallback    */
+        break;
+
+      case HAL_I2C_MSPINIT_CB_ID :
+        hi2c->MspInitCallback = HAL_I2C_MspInit;                   /* Legacy weak MspInit              */
+        break;
+
+      case HAL_I2C_MSPDEINIT_CB_ID :
+        hi2c->MspDeInitCallback = HAL_I2C_MspDeInit;               /* Legacy weak MspDeInit            */
+        break;
+
+      default :
+        /* Update the error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_I2C_STATE_RESET == hi2c->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_I2C_MSPINIT_CB_ID :
+        hi2c->MspInitCallback = HAL_I2C_MspInit;                   /* Legacy weak MspInit              */
+        break;
+
+      case HAL_I2C_MSPDEINIT_CB_ID :
+        hi2c->MspDeInitCallback = HAL_I2C_MspDeInit;               /* Legacy weak MspDeInit            */
+        break;
+
+      default :
+        /* Update the error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hi2c);
+  return status;
+}
+
+/**
+  * @brief  Register the Slave Address Match I2C Callback
+  *         To be used instead of the weak HAL_I2C_AddrCallback() predefined callback
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pCallback pointer to the Address Match Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hi2c);
+
+  if (HAL_I2C_STATE_READY == hi2c->State)
+  {
+    hi2c->AddrCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hi2c);
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Slave Address Match I2C Callback
+  *         Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hi2c);
+
+  if (HAL_I2C_STATE_READY == hi2c->State)
+  {
+    hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hi2c);
+  return status;
+}
+
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
+ *  @brief   Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the I2C data
+    transfers.
+
+    (#) There are two modes of transfer:
+       (++) Blocking mode : The communication is performed in the polling mode.
+            The status of all data processing is returned by the same function
+            after finishing transfer.
+       (++) No-Blocking mode : The communication is performed using Interrupts
+            or DMA. These functions return the status of the transfer startup.
+            The end of the data processing will be indicated through the
+            dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
+            using DMA mode.
+
+    (#) Blocking mode functions are :
+        (++) HAL_I2C_Master_Transmit()
+        (++) HAL_I2C_Master_Receive()
+        (++) HAL_I2C_Slave_Transmit()
+        (++) HAL_I2C_Slave_Receive()
+        (++) HAL_I2C_Mem_Write()
+        (++) HAL_I2C_Mem_Read()
+        (++) HAL_I2C_IsDeviceReady()
+
+    (#) No-Blocking mode functions with Interrupt are :
+        (++) HAL_I2C_Master_Transmit_IT()
+        (++) HAL_I2C_Master_Receive_IT()
+        (++) HAL_I2C_Slave_Transmit_IT()
+        (++) HAL_I2C_Slave_Receive_IT()
+        (++) HAL_I2C_Mem_Write_IT()
+        (++) HAL_I2C_Mem_Read_IT()
+        (++) HAL_I2C_Master_Seq_Transmit_IT()
+        (++) HAL_I2C_Master_Seq_Receive_IT()
+        (++) HAL_I2C_Slave_Seq_Transmit_IT()
+        (++) HAL_I2C_Slave_Seq_Receive_IT()
+        (++) HAL_I2C_EnableListen_IT()
+        (++) HAL_I2C_DisableListen_IT()
+        (++) HAL_I2C_Master_Abort_IT()
+
+    (#) No-Blocking mode functions with DMA are :
+        (++) HAL_I2C_Master_Transmit_DMA()
+        (++) HAL_I2C_Master_Receive_DMA()
+        (++) HAL_I2C_Slave_Transmit_DMA()
+        (++) HAL_I2C_Slave_Receive_DMA()
+        (++) HAL_I2C_Mem_Write_DMA()
+        (++) HAL_I2C_Mem_Read_DMA()
+        (++) HAL_I2C_Master_Seq_Transmit_DMA()
+        (++) HAL_I2C_Master_Seq_Receive_DMA()
+        (++) HAL_I2C_Slave_Seq_Transmit_DMA()
+        (++) HAL_I2C_Slave_Seq_Receive_DMA()
+
+    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+        (++) HAL_I2C_MasterTxCpltCallback()
+        (++) HAL_I2C_MasterRxCpltCallback()
+        (++) HAL_I2C_SlaveTxCpltCallback()
+        (++) HAL_I2C_SlaveRxCpltCallback()
+        (++) HAL_I2C_MemTxCpltCallback()
+        (++) HAL_I2C_MemRxCpltCallback()
+        (++) HAL_I2C_AddrCallback()
+        (++) HAL_I2C_ListenCpltCallback()
+        (++) HAL_I2C_ErrorCallback()
+        (++) HAL_I2C_AbortCpltCallback()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Transmits in master mode an amount of data in blocking mode.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferISR   = NULL;
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
+    }
+
+    while (hi2c->XferCount > 0U)
+    {
+      /* Wait until TXIS flag is set */
+      if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+
+      if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+      {
+        /* Wait until TCR flag is set */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        if (hi2c->XferCount > MAX_NBYTE_SIZE)
+        {
+          hi2c->XferSize = MAX_NBYTE_SIZE;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+        }
+        else
+        {
+          hi2c->XferSize = hi2c->XferCount;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+        }
+      }
+    }
+
+    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+    /* Wait until STOPF flag is set */
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Clear STOP Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Clear Configuration Register 2 */
+    I2C_RESET_CR2(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receives in master mode an amount of data in blocking mode.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferISR   = NULL;
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+    }
+
+    while (hi2c->XferCount > 0U)
+    {
+      /* Wait until RXNE flag is set */
+      if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Read data from RXDR */
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+
+      if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+      {
+        /* Wait until TCR flag is set */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        if (hi2c->XferCount > MAX_NBYTE_SIZE)
+        {
+          hi2c->XferSize = MAX_NBYTE_SIZE;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+        }
+        else
+        {
+          hi2c->XferSize = hi2c->XferCount;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+        }
+      }
+    }
+
+    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+    /* Wait until STOPF flag is set */
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Clear STOP Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Clear Configuration Register 2 */
+    I2C_RESET_CR2(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmits in slave mode an amount of data in blocking mode.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferISR   = NULL;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Wait until ADDR flag is set */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+
+    /* If 10bit addressing mode is selected */
+    if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+    {
+      /* Wait until ADDR flag is set */
+      if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+      {
+        /* Disable Address Acknowledge */
+        hi2c->Instance->CR2 |= I2C_CR2_NACK;
+        return HAL_ERROR;
+      }
+
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+    }
+
+    /* Wait until DIR flag is set Transmitter mode */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    while (hi2c->XferCount > 0U)
+    {
+      /* Wait until TXIS flag is set */
+      if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        /* Disable Address Acknowledge */
+        hi2c->Instance->CR2 |= I2C_CR2_NACK;
+        return HAL_ERROR;
+      }
+
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+    }
+
+    /* Wait until STOP flag is set */
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      {
+        /* Normal use case for Transmitter mode */
+        /* A NACK is generated to confirm the end of transfer */
+        hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+      }
+      else
+      {
+        return HAL_ERROR;
+      }
+    }
+
+    /* Clear STOP flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Wait until BUSY flag is reset */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    /* Disable Address Acknowledge */
+    hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in slave mode an amount of data in blocking mode
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferISR   = NULL;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Wait until ADDR flag is set */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+
+    /* Wait until DIR flag is reset Receiver mode */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    while (hi2c->XferCount > 0U)
+    {
+      /* Wait until RXNE flag is set */
+      if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        /* Disable Address Acknowledge */
+        hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+        /* Store Last receive data if any */
+        if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+        {
+          /* Read data from RXDR */
+          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+          /* Increment Buffer pointer */
+          hi2c->pBuffPtr++;
+
+          hi2c->XferCount--;
+        }
+
+        return HAL_ERROR;
+      }
+
+      /* Read data from RXDR */
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+    }
+
+    /* Wait until STOP flag is set */
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    /* Clear STOP flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Wait until BUSY flag is reset */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    /* Disable Address Acknowledge */
+    hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit in master mode an amount of data in non-blocking mode with Interrupt
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+  uint32_t xfermode;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_IT;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in master mode an amount of data in non-blocking mode with Interrupt
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+  uint32_t xfermode;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_IT;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit in slave mode an amount of data in non-blocking mode with Interrupt
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Slave_ISR_IT;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in slave mode an amount of data in non-blocking mode with Interrupt
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Slave_ISR_IT;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit in master mode an amount of data in non-blocking mode with DMA
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+  uint32_t xfermode;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_DMA;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    if (hi2c->XferSize > 0U)
+    {
+      if (hi2c->hdmatx != NULL)
+      {
+        /* Set the I2C DMA transfer complete callback */
+        hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+
+        /* Set the DMA error callback */
+        hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hi2c->hdmatx->XferHalfCpltCallback = NULL;
+        hi2c->hdmatx->XferAbortCallback = NULL;
+
+        /* Enable the DMA stream or channel depends on Instance */
+        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+
+      if (dmaxferstatus == HAL_OK)
+      {
+        /* Send Slave Address */
+        /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
+
+        /* Update XferCount value */
+        hi2c->XferCount -= hi2c->XferSize;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Note : The I2C interrupts must be enabled after unlocking current process
+                  to avoid the risk of I2C interrupt handle execution before current
+                  process unlock */
+        /* Enable ERR and NACK interrupts */
+        I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+        /* Enable DMA Request */
+        hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Update Transfer ISR function pointer */
+      hi2c->XferISR = I2C_Master_ISR_IT;
+
+      /* Send Slave Address */
+      /* Set NBYTES to write and generate START condition */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+      /* possible to enable all of these */
+      /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in master mode an amount of data in non-blocking mode with DMA
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+  uint32_t xfermode;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_DMA;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    if (hi2c->XferSize > 0U)
+    {
+      if (hi2c->hdmarx != NULL)
+      {
+        /* Set the I2C DMA transfer complete callback */
+        hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+
+        /* Set the DMA error callback */
+        hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hi2c->hdmarx->XferHalfCpltCallback = NULL;
+        hi2c->hdmarx->XferAbortCallback = NULL;
+
+        /* Enable the DMA stream or channel depends on Instance */
+        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+
+      if (dmaxferstatus == HAL_OK)
+      {
+        /* Send Slave Address */
+        /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+
+        /* Update XferCount value */
+        hi2c->XferCount -= hi2c->XferSize;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Note : The I2C interrupts must be enabled after unlocking current process
+                  to avoid the risk of I2C interrupt handle execution before current
+                  process unlock */
+        /* Enable ERR and NACK interrupts */
+        I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+        /* Enable DMA Request */
+        hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Update Transfer ISR function pointer */
+      hi2c->XferISR = I2C_Master_ISR_IT;
+
+      /* Send Slave Address */
+      /* Set NBYTES to read and generate START condition */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+      /* possible to enable all of these */
+      /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit in slave mode an amount of data in non-blocking mode with DMA
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef dmaxferstatus;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Slave_ISR_DMA;
+
+    if (hi2c->hdmatx != NULL)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmatx->XferHalfCpltCallback = NULL;
+      hi2c->hdmatx->XferAbortCallback = NULL;
+
+      /* Enable the DMA stream or channel depends on Instance */
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Enable Address Acknowledge */
+      hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, STOP, NACK, ADDR interrupts */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+      /* Enable DMA Request */
+      hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in slave mode an amount of data in non-blocking mode with DMA
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef dmaxferstatus;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Slave_ISR_DMA;
+
+    if (hi2c->hdmarx != NULL)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmarx->XferHalfCpltCallback = NULL;
+      hi2c->hdmarx->XferAbortCallback = NULL;
+
+      /* Enable the DMA stream or channel depends on Instance */
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Enable Address Acknowledge */
+      hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, STOP, NACK, ADDR interrupts */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+      /* Enable DMA Request */
+      hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+/**
+  * @brief  Write an amount of data in blocking mode to a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferISR   = NULL;
+
+    /* Send Slave Address and Memory Address */
+    if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+      return HAL_ERROR;
+    }
+
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+    }
+
+    do
+    {
+      /* Wait until TXIS flag is set */
+      if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+
+      if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+      {
+        /* Wait until TCR flag is set */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        if (hi2c->XferCount > MAX_NBYTE_SIZE)
+        {
+          hi2c->XferSize = MAX_NBYTE_SIZE;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+        }
+        else
+        {
+          hi2c->XferSize = hi2c->XferCount;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+        }
+      }
+
+    }
+    while (hi2c->XferCount > 0U);
+
+    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+    /* Wait until STOPF flag is reset */
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Clear STOP Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Clear Configuration Register 2 */
+    I2C_RESET_CR2(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Read an amount of data in blocking mode from a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferISR   = NULL;
+
+    /* Send Slave Address and Memory Address */
+    if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+      return HAL_ERROR;
+    }
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+    }
+
+    do
+    {
+      /* Wait until RXNE flag is set */
+      if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Read data from RXDR */
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+
+      if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+      {
+        /* Wait until TCR flag is set */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        if (hi2c->XferCount > MAX_NBYTE_SIZE)
+        {
+          hi2c->XferSize = MAX_NBYTE_SIZE;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+        }
+        else
+        {
+          hi2c->XferSize = hi2c->XferCount;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+        }
+      }
+    }
+    while (hi2c->XferCount > 0U);
+
+    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+    /* Wait until STOPF flag is reset */
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Clear STOP Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Clear Configuration Register 2 */
+    I2C_RESET_CR2(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+/**
+  * @brief  Write an amount of data in non-blocking mode with Interrupt to a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+  uint32_t tickstart;
+  uint32_t xfermode;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_IT;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    /* Send Slave Address and Memory Address */
+    if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+      return HAL_ERROR;
+    }
+
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Read an amount of data in non-blocking mode with Interrupt from a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+  uint32_t tickstart;
+  uint32_t xfermode;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_IT;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    /* Send Slave Address and Memory Address */
+    if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+      return HAL_ERROR;
+    }
+
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+/**
+  * @brief  Write an amount of data in non-blocking mode with DMA to a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+  uint32_t tickstart;
+  uint32_t xfermode;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_DMA;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    /* Send Slave Address and Memory Address */
+    if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+      return HAL_ERROR;
+    }
+
+
+    if (hi2c->hdmatx != NULL)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmatx->XferHalfCpltCallback = NULL;
+      hi2c->hdmatx->XferAbortCallback = NULL;
+
+      /* Enable the DMA stream or channel depends on Instance */
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_READY;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Send Slave Address */
+      /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+
+      /* Update XferCount value */
+      hi2c->XferCount -= hi2c->XferSize;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR and NACK interrupts */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+      /* Enable DMA Request */
+      hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_READY;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Reads an amount of data in non-blocking mode with DMA from a specific memory address.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be read
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+  uint32_t tickstart;
+  uint32_t xfermode;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_DMA;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    /* Send Slave Address and Memory Address */
+    if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+      return HAL_ERROR;
+    }
+
+    if (hi2c->hdmarx != NULL)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmarx->XferHalfCpltCallback = NULL;
+      hi2c->hdmarx->XferAbortCallback = NULL;
+
+      /* Enable the DMA stream or channel depends on Instance */
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_READY;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+
+      /* Update XferCount value */
+      hi2c->XferCount -= hi2c->XferSize;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR and NACK interrupts */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+      /* Enable DMA Request */
+      hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_READY;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Checks if target device is ready for communication.
+  * @note   This function is used with Memory devices
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  Trials Number of trials
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  __IO uint32_t I2C_Trials = 0UL;
+
+  FlagStatus tmp1;
+  FlagStatus tmp2;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    do
+    {
+      /* Generate Start */
+      hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress);
+
+      /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+      /* Wait until STOPF flag is set or a NACK flag is set*/
+      tickstart = HAL_GetTick();
+
+      tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
+      tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
+
+      while ((tmp1 == RESET) && (tmp2 == RESET))
+      {
+        if (Timeout != HAL_MAX_DELAY)
+        {
+          if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+          {
+            /* Update I2C state */
+            hi2c->State = HAL_I2C_STATE_READY;
+
+            /* Update I2C error code */
+            hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+
+            /* Process Unlocked */
+            __HAL_UNLOCK(hi2c);
+
+            return HAL_ERROR;
+          }
+        }
+
+        tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
+        tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
+      }
+
+      /* Check if the NACKF flag has not been set */
+      if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
+      {
+        /* Wait until STOPF flag is reset */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        /* Clear STOP Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+        /* Device is ready */
+        hi2c->State = HAL_I2C_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_OK;
+      }
+      else
+      {
+        /* Wait until STOPF flag is reset */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        /* Clear NACK Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+        /* Clear STOP Flag, auto generated with autoend*/
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+      }
+
+      /* Check if the maximum allowed number of trials has been reached */
+      if (I2C_Trials == Trials)
+      {
+        /* Generate Stop */
+        hi2c->Instance->CR2 |= I2C_CR2_STOP;
+
+        /* Wait until STOPF flag is reset */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        /* Clear STOP Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+      }
+
+      /* Increment Trials */
+      I2C_Trials++;
+    }
+    while (I2C_Trials < Trials);
+
+    /* Update I2C state */
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Update I2C error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_ERROR;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  uint32_t xfermode;
+  uint32_t xferrequest = I2C_GENERATE_START_WRITE;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Master_ISR_IT;
+
+    /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = hi2c->XferOptions;
+    }
+
+    /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+    /* Mean Previous state is same as current state */
+    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+    {
+      xferrequest = I2C_NO_STARTSTOP;
+    }
+    else
+    {
+      /* Convert OTHER_xxx XferOptions if any */
+      I2C_ConvertOtherXferOptions(hi2c);
+
+      /* Update xfermode accordingly if no reload is necessary */
+      if (hi2c->XferCount < MAX_NBYTE_SIZE)
+      {
+        xfermode = hi2c->XferOptions;
+      }
+    }
+
+    /* Send Slave Address and set NBYTES to write */
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  uint32_t xfermode;
+  uint32_t xferrequest = I2C_GENERATE_START_WRITE;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Master_ISR_DMA;
+
+    /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = hi2c->XferOptions;
+    }
+
+    /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+    /* Mean Previous state is same as current state */
+    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+    {
+      xferrequest = I2C_NO_STARTSTOP;
+    }
+    else
+    {
+      /* Convert OTHER_xxx XferOptions if any */
+      I2C_ConvertOtherXferOptions(hi2c);
+
+      /* Update xfermode accordingly if no reload is necessary */
+      if (hi2c->XferCount < MAX_NBYTE_SIZE)
+      {
+        xfermode = hi2c->XferOptions;
+      }
+    }
+
+    if (hi2c->XferSize > 0U)
+    {
+      if (hi2c->hdmatx != NULL)
+      {
+        /* Set the I2C DMA transfer complete callback */
+        hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+
+        /* Set the DMA error callback */
+        hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hi2c->hdmatx->XferHalfCpltCallback = NULL;
+        hi2c->hdmatx->XferAbortCallback = NULL;
+
+        /* Enable the DMA stream or channel depends on Instance */
+        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+
+      if (dmaxferstatus == HAL_OK)
+      {
+        /* Send Slave Address and set NBYTES to write */
+        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+
+        /* Update XferCount value */
+        hi2c->XferCount -= hi2c->XferSize;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Note : The I2C interrupts must be enabled after unlocking current process
+                  to avoid the risk of I2C interrupt handle execution before current
+                  process unlock */
+        /* Enable ERR and NACK interrupts */
+        I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+        /* Enable DMA Request */
+        hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Update Transfer ISR function pointer */
+      hi2c->XferISR = I2C_Master_ISR_IT;
+
+      /* Send Slave Address */
+      /* Set NBYTES to write and generate START condition */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+      /* possible to enable all of these */
+      /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  uint32_t xfermode;
+  uint32_t xferrequest = I2C_GENERATE_START_READ;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Master_ISR_IT;
+
+    /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = hi2c->XferOptions;
+    }
+
+    /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+    /* Mean Previous state is same as current state */
+    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+    {
+      xferrequest = I2C_NO_STARTSTOP;
+    }
+    else
+    {
+      /* Convert OTHER_xxx XferOptions if any */
+      I2C_ConvertOtherXferOptions(hi2c);
+
+      /* Update xfermode accordingly if no reload is necessary */
+      if (hi2c->XferCount < MAX_NBYTE_SIZE)
+      {
+        xfermode = hi2c->XferOptions;
+      }
+    }
+
+    /* Send Slave Address and set NBYTES to read */
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  uint32_t xfermode;
+  uint32_t xferrequest = I2C_GENERATE_START_READ;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Master_ISR_DMA;
+
+    /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = hi2c->XferOptions;
+    }
+
+    /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+    /* Mean Previous state is same as current state */
+    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+    {
+      xferrequest = I2C_NO_STARTSTOP;
+    }
+    else
+    {
+      /* Convert OTHER_xxx XferOptions if any */
+      I2C_ConvertOtherXferOptions(hi2c);
+
+      /* Update xfermode accordingly if no reload is necessary */
+      if (hi2c->XferCount < MAX_NBYTE_SIZE)
+      {
+        xfermode = hi2c->XferOptions;
+      }
+    }
+
+    if (hi2c->XferSize > 0U)
+    {
+      if (hi2c->hdmarx != NULL)
+      {
+        /* Set the I2C DMA transfer complete callback */
+        hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+
+        /* Set the DMA error callback */
+        hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hi2c->hdmarx->XferHalfCpltCallback = NULL;
+        hi2c->hdmarx->XferAbortCallback = NULL;
+
+        /* Enable the DMA stream or channel depends on Instance */
+        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+
+      if (dmaxferstatus == HAL_OK)
+      {
+        /* Send Slave Address and set NBYTES to read */
+        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+
+        /* Update XferCount value */
+        hi2c->XferCount -= hi2c->XferSize;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Note : The I2C interrupts must be enabled after unlocking current process
+                  to avoid the risk of I2C interrupt handle execution before current
+                  process unlock */
+        /* Enable ERR and NACK interrupts */
+        I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+        /* Enable DMA Request */
+        hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Update Transfer ISR function pointer */
+      hi2c->XferISR = I2C_Master_ISR_IT;
+
+      /* Send Slave Address */
+      /* Set NBYTES to read and generate START condition */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+      /* possible to enable all of these */
+      /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+    /* and then toggle the HAL slave RX state to TX state */
+    if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+    {
+      /* Disable associated Interrupts */
+      I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+      /* Abort DMA Xfer if any */
+      if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+      {
+        hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+        if (hi2c->hdmarx != NULL)
+        {
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA RX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+          }
+        }
+      }
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Slave_ISR_IT;
+
+    if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+    {
+      /* Clear ADDR flag after prepare the transfer parameters */
+      /* This action will generate an acknowledge to the Master */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
+    /* REnable ADDR interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+
+    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+    /* and then toggle the HAL slave RX state to TX state */
+    if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+    {
+      /* Disable associated Interrupts */
+      I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+      if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+      {
+        /* Abort DMA Xfer if any */
+        if (hi2c->hdmarx != NULL)
+        {
+          hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA RX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+          }
+        }
+      }
+    }
+    else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+    {
+      if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+      {
+        hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+        /* Abort DMA Xfer if any */
+        if (hi2c->hdmatx != NULL)
+        {
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA TX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+          }
+        }
+      }
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Slave_ISR_DMA;
+
+    if (hi2c->hdmatx != NULL)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmatx->XferHalfCpltCallback = NULL;
+      hi2c->hdmatx->XferAbortCallback = NULL;
+
+      /* Enable the DMA stream or channel depends on Instance */
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Update XferCount value */
+      hi2c->XferCount -= hi2c->XferSize;
+
+      /* Reset XferSize */
+      hi2c->XferSize = 0;
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+    {
+      /* Clear ADDR flag after prepare the transfer parameters */
+      /* This action will generate an acknowledge to the Master */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
+    /* Enable ERR, STOP, NACK, ADDR interrupts */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+    /* Enable DMA Request */
+    hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+    /* and then toggle the HAL slave TX state to RX state */
+    if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+    {
+      /* Disable associated Interrupts */
+      I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+      if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+      {
+        hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+        /* Abort DMA Xfer if any */
+        if (hi2c->hdmatx != NULL)
+        {
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA TX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+          }
+        }
+      }
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Slave_ISR_IT;
+
+    if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
+    {
+      /* Clear ADDR flag after prepare the transfer parameters */
+      /* This action will generate an acknowledge to the Master */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
+    /* REnable ADDR interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+    /* and then toggle the HAL slave TX state to RX state */
+    if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+    {
+      /* Disable associated Interrupts */
+      I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+      if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+      {
+        /* Abort DMA Xfer if any */
+        if (hi2c->hdmatx != NULL)
+        {
+          hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA TX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+          }
+        }
+      }
+    }
+    else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+    {
+      if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+      {
+        hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+        /* Abort DMA Xfer if any */
+        if (hi2c->hdmarx != NULL)
+        {
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA RX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+          }
+        }
+      }
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Slave_ISR_DMA;
+
+    if (hi2c->hdmarx != NULL)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmarx->XferHalfCpltCallback = NULL;
+      hi2c->hdmarx->XferAbortCallback = NULL;
+
+      /* Enable the DMA stream or channel depends on Instance */
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Update XferCount value */
+      hi2c->XferCount -= hi2c->XferSize;
+
+      /* Reset XferSize */
+      hi2c->XferSize = 0;
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
+    {
+      /* Clear ADDR flag after prepare the transfer parameters */
+      /* This action will generate an acknowledge to the Master */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
+    /* REnable ADDR interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
+
+    /* Enable DMA Request */
+    hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable the Address listen mode with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
+{
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    hi2c->State = HAL_I2C_STATE_LISTEN;
+    hi2c->XferISR = I2C_Slave_ISR_IT;
+
+    /* Enable the Address Match interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Disable the Address listen mode with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
+{
+  /* Declaration of tmp to prevent undefined behavior of volatile usage */
+  uint32_t tmp;
+
+  /* Disable Address listen mode only if a transfer is not ongoing */
+  if (hi2c->State == HAL_I2C_STATE_LISTEN)
+  {
+    tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
+    hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode = HAL_I2C_MODE_NONE;
+    hi2c->XferISR = NULL;
+
+    /* Disable the Address Match interrupt */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Abort a master I2C IT or DMA process communication with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
+{
+  if (hi2c->Mode == HAL_I2C_MODE_MASTER)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Disable Interrupts and Store Previous state */
+    if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+    {
+      I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+      hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+    }
+    else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+    {
+      I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+      hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+    }
+    else
+    {
+      /* Do nothing */
+    }
+
+    /* Set State at HAL_I2C_STATE_ABORT */
+    hi2c->State = HAL_I2C_STATE_ABORT;
+
+    /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
+    /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
+    I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    /* Wrong usage of abort function */
+    /* This function should be used only in case of abort monitored by master device */
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+
+/**
+  * @brief  This function handles I2C event interrupt request.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
+{
+  /* Get current IT Flags and IT sources value */
+  uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
+  uint32_t itsources = READ_REG(hi2c->Instance->CR1);
+
+  /* I2C events treatment -------------------------------------*/
+  if (hi2c->XferISR != NULL)
+  {
+    hi2c->XferISR(hi2c, itflags, itsources);
+  }
+}
+
+/**
+  * @brief  This function handles I2C error interrupt request.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
+{
+  uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
+  uint32_t itsources = READ_REG(hi2c->Instance->CR1);
+  uint32_t tmperror;
+
+  /* I2C Bus error interrupt occurred ------------------------------------*/
+  if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+  {
+    hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
+
+    /* Clear BERR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
+  }
+
+  /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
+  if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+  {
+    hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
+
+    /* Clear OVR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
+  }
+
+  /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
+  if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+  {
+    hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
+
+    /* Clear ARLO flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
+  }
+
+  /* Store current volatile hi2c->ErrorCode, misra rule */
+  tmperror = hi2c->ErrorCode;
+
+  /* Call the Error Callback in case of Error detected */
+  if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) !=  HAL_I2C_ERROR_NONE)
+  {
+    I2C_ITError(hi2c, tmperror);
+  }
+}
+
+/**
+  * @brief  Master Tx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Master Rx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
+   */
+}
+
+/** @brief  Slave Tx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Slave Rx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Slave Address Match callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
+  * @param  AddrMatchCode Address Match Code
+  * @retval None
+  */
+__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+  UNUSED(TransferDirection);
+  UNUSED(AddrMatchCode);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_AddrCallback() could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Listen Complete callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_ListenCpltCallback() could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Memory Tx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MemTxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Memory Rx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MemRxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  I2C error callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  I2C abort callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_AbortCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
+ *  @brief   Peripheral State, Mode and Error functions
+ *
+@verbatim
+ ===============================================================================
+            ##### Peripheral State, Mode and Error functions #####
+ ===============================================================================
+    [..]
+    This subsection permit to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the I2C handle state.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL state
+  */
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
+{
+  /* Return I2C handle state */
+  return hi2c->State;
+}
+
+/**
+  * @brief  Returns the I2C Master, Slave, Memory or no mode.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval HAL mode
+  */
+HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
+{
+  return hi2c->Mode;
+}
+
+/**
+* @brief  Return the I2C error code.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *              the configuration information for the specified I2C.
+* @retval I2C Error Code
+*/
+uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
+{
+  return hi2c->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  ITFlags Interrupt flags to handle.
+  * @param  ITSources Interrupt sources enabled.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
+{
+  uint16_t devaddress;
+  uint32_t tmpITFlags = ITFlags;
+
+  /* Process Locked */
+  __HAL_LOCK(hi2c);
+
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+  {
+    /* Clear NACK Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    /* Set corresponding Error Code */
+    /* No need to generate STOP, it is automatically done */
+    /* Error callback will be send during stop flag treatment */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+    /* Flush TX register */
+    I2C_Flush_TXDR(hi2c);
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+  {
+    /* Remove RXNE flag on temporary variable as read done */
+    tmpITFlags &= ~I2C_FLAG_RXNE;
+
+    /* Read data from RXDR */
+    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    hi2c->XferSize--;
+    hi2c->XferCount--;
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+  {
+    /* Write data to TXDR */
+    hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    hi2c->XferSize--;
+    hi2c->XferCount--;
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+  {
+    if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+    {
+      devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
+
+      if (hi2c->XferCount > MAX_NBYTE_SIZE)
+      {
+        hi2c->XferSize = MAX_NBYTE_SIZE;
+        I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+      }
+      else
+      {
+        hi2c->XferSize = hi2c->XferCount;
+        if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+        {
+          I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP);
+        }
+        else
+        {
+          I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+        }
+      }
+    }
+    else
+    {
+      /* Call TxCpltCallback() if no stop mode is set */
+      if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+      {
+        /* Call I2C Master Sequential complete process */
+        I2C_ITMasterSeqCplt(hi2c);
+      }
+      else
+      {
+        /* Wrong size Status regarding TCR flag event */
+        /* Call the corresponding callback to inform upper layer of End of Transfer */
+        I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+      }
+    }
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+  {
+    if (hi2c->XferCount == 0U)
+    {
+      if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+      {
+        /* Generate a stop condition in case of no transfer option */
+        if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
+        {
+          /* Generate Stop */
+          hi2c->Instance->CR2 |= I2C_CR2_STOP;
+        }
+        else
+        {
+          /* Call I2C Master Sequential complete process */
+          I2C_ITMasterSeqCplt(hi2c);
+        }
+      }
+    }
+    else
+    {
+      /* Wrong size Status regarding TC flag event */
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+      I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+    }
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+  {
+    /* Call I2C Master complete process */
+    I2C_ITMasterCplt(hi2c, tmpITFlags);
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  ITFlags Interrupt flags to handle.
+  * @param  ITSources Interrupt sources enabled.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
+{
+  uint32_t tmpoptions = hi2c->XferOptions;
+  uint32_t tmpITFlags = ITFlags;
+
+  /* Process locked */
+  __HAL_LOCK(hi2c);
+
+  /* Check if STOPF is set */
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+  {
+    /* Call I2C Slave complete process */
+    I2C_ITSlaveCplt(hi2c, tmpITFlags);
+  }
+
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+  {
+    /* Check that I2C transfer finished */
+    /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+    /* Mean XferCount == 0*/
+    /* So clear Flag NACKF only */
+    if (hi2c->XferCount == 0U)
+    {
+      if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */
+      {
+        /* Call I2C Listen complete process */
+        I2C_ITListenCplt(hi2c, tmpITFlags);
+      }
+      else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
+      {
+        /* Clear NACK Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+        /* Flush TX register */
+        I2C_Flush_TXDR(hi2c);
+
+        /* Last Byte is Transmitted */
+        /* Call I2C Slave Sequential complete process */
+        I2C_ITSlaveSeqCplt(hi2c);
+      }
+      else
+      {
+        /* Clear NACK Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+      }
+    }
+    else
+    {
+      /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
+      /* Clear NACK Flag */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+      /* Set ErrorCode corresponding to a Non-Acknowledge */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+      if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
+      {
+        /* Call the corresponding callback to inform upper layer of End of Transfer */
+        I2C_ITError(hi2c, hi2c->ErrorCode);
+      }
+    }
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+  {
+    if (hi2c->XferCount > 0U)
+    {
+      /* Read data from RXDR */
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+    }
+
+    if ((hi2c->XferCount == 0U) && \
+        (tmpoptions != I2C_NO_OPTION_FRAME))
+    {
+      /* Call I2C Slave Sequential complete process */
+      I2C_ITSlaveSeqCplt(hi2c);
+    }
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
+  {
+    I2C_ITAddrCplt(hi2c, tmpITFlags);
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+  {
+    /* Write data to TXDR only if XferCount not reach "0" */
+    /* A TXIS flag can be set, during STOP treatment      */
+    /* Check if all Datas have already been sent */
+    /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
+    if (hi2c->XferCount > 0U)
+    {
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+    }
+    else
+    {
+      if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
+      {
+        /* Last Byte is Transmitted */
+        /* Call I2C Slave Sequential complete process */
+        I2C_ITSlaveSeqCplt(hi2c);
+      }
+    }
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  ITFlags Interrupt flags to handle.
+  * @param  ITSources Interrupt sources enabled.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
+{
+  uint16_t devaddress;
+  uint32_t xfermode;
+
+  /* Process Locked */
+  __HAL_LOCK(hi2c);
+
+  if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+  {
+    /* Clear NACK Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    /* Set corresponding Error Code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+    /* No need to generate STOP, it is automatically done */
+    /* But enable STOP interrupt, to treat it */
+    /* Error callback will be send during stop flag treatment */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+
+    /* Flush TX register */
+    I2C_Flush_TXDR(hi2c);
+  }
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+  {
+    /* Disable TC interrupt */
+    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
+
+    if (hi2c->XferCount != 0U)
+    {
+      /* Recover Slave address */
+      devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
+
+      /* Prepare the new XferSize to transfer */
+      if (hi2c->XferCount > MAX_NBYTE_SIZE)
+      {
+        hi2c->XferSize = MAX_NBYTE_SIZE;
+        xfermode = I2C_RELOAD_MODE;
+      }
+      else
+      {
+        hi2c->XferSize = hi2c->XferCount;
+        if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+        {
+          xfermode = hi2c->XferOptions;
+        }
+        else
+        {
+          xfermode = I2C_AUTOEND_MODE;
+        }
+      }
+
+      /* Set the new XferSize in Nbytes register */
+      I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+
+      /* Update XferCount value */
+      hi2c->XferCount -= hi2c->XferSize;
+
+      /* Enable DMA Request */
+      if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+      {
+        hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+      }
+      else
+      {
+        hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+      }
+    }
+    else
+    {
+      /* Call TxCpltCallback() if no stop mode is set */
+      if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+      {
+        /* Call I2C Master Sequential complete process */
+        I2C_ITMasterSeqCplt(hi2c);
+      }
+      else
+      {
+        /* Wrong size Status regarding TCR flag event */
+        /* Call the corresponding callback to inform upper layer of End of Transfer */
+        I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+      }
+    }
+  }
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+  {
+    if (hi2c->XferCount == 0U)
+    {
+      if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+      {
+        /* Generate a stop condition in case of no transfer option */
+        if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
+        {
+          /* Generate Stop */
+          hi2c->Instance->CR2 |= I2C_CR2_STOP;
+        }
+        else
+        {
+          /* Call I2C Master Sequential complete process */
+          I2C_ITMasterSeqCplt(hi2c);
+        }
+      }
+    }
+    else
+    {
+      /* Wrong size Status regarding TC flag event */
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+      I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+    }
+  }
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+  {
+    /* Call I2C Master complete process */
+    I2C_ITMasterCplt(hi2c, ITFlags);
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  ITFlags Interrupt flags to handle.
+  * @param  ITSources Interrupt sources enabled.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
+{
+  uint32_t tmpoptions = hi2c->XferOptions;
+  uint32_t treatdmanack = 0U;
+  HAL_I2C_StateTypeDef tmpstate;
+
+  /* Process locked */
+  __HAL_LOCK(hi2c);
+
+  /* Check if STOPF is set */
+  if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+  {
+    /* Call I2C Slave complete process */
+    I2C_ITSlaveCplt(hi2c, ITFlags);
+  }
+
+  if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+  {
+    /* Check that I2C transfer finished */
+    /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+    /* Mean XferCount == 0 */
+    /* So clear Flag NACKF only */
+    if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
+        (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))
+    {
+      /* Split check of hdmarx, for MISRA compliance */
+      if (hi2c->hdmarx != NULL)
+      {
+        if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)
+        {
+          if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U)
+          {
+            treatdmanack = 1U;
+          }
+        }
+      }
+
+      /* Split check of hdmatx, for MISRA compliance  */
+      if (hi2c->hdmatx != NULL)
+      {
+        if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)
+        {
+          if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U)
+          {
+            treatdmanack = 1U;
+          }
+        }
+      }
+
+      if (treatdmanack == 1U)
+      {
+        if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */
+        {
+          /* Call I2C Listen complete process */
+          I2C_ITListenCplt(hi2c, ITFlags);
+        }
+        else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
+        {
+          /* Clear NACK Flag */
+          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+          /* Flush TX register */
+          I2C_Flush_TXDR(hi2c);
+
+          /* Last Byte is Transmitted */
+          /* Call I2C Slave Sequential complete process */
+          I2C_ITSlaveSeqCplt(hi2c);
+        }
+        else
+        {
+          /* Clear NACK Flag */
+          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+        }
+      }
+      else
+      {
+        /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
+        /* Clear NACK Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+        /* Set ErrorCode corresponding to a Non-Acknowledge */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+        /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */
+        tmpstate = hi2c->State;
+
+        if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
+        {
+          if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
+          {
+            hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+          }
+          else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+          {
+            hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+          }
+          else
+          {
+            /* Do nothing */
+          }
+
+          /* Call the corresponding callback to inform upper layer of End of Transfer */
+          I2C_ITError(hi2c, hi2c->ErrorCode);
+        }
+      }
+    }
+    else
+    {
+      /* Only Clear NACK Flag, no DMA treatment is pending */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+    }
+  }
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
+  {
+    I2C_ITAddrCplt(hi2c, ITFlags);
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Master sends target device address followed by internal memory address for write request.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
+{
+  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
+
+  /* Wait until TXIS flag is set */
+  if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* If Memory address size is 8Bit */
+  if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
+  {
+    /* Send Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+  }
+  /* If Memory address size is 16Bit */
+  else
+  {
+    /* Send MSB of Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+
+    /* Wait until TXIS flag is set */
+    if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Send LSB of Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+  }
+
+  /* Wait until TCR flag is set */
+  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Master sends target device address followed by internal memory address for read request.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
+{
+  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
+
+  /* Wait until TXIS flag is set */
+  if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* If Memory address size is 8Bit */
+  if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
+  {
+    /* Send Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+  }
+  /* If Memory address size is 16Bit */
+  else
+  {
+    /* Send MSB of Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+
+    /* Wait until TXIS flag is set */
+    if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Send LSB of Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+  }
+
+  /* Wait until TC flag is set */
+  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  I2C Address complete process callback.
+  * @param  hi2c I2C handle.
+  * @param  ITFlags Interrupt flags to handle.
+  * @retval None
+  */
+static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+  uint8_t transferdirection;
+  uint16_t slaveaddrcode;
+  uint16_t ownadd1code;
+  uint16_t ownadd2code;
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(ITFlags);
+
+  /* In case of Listen state, need to inform upper layer of address match code event */
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    transferdirection = I2C_GET_DIR(hi2c);
+    slaveaddrcode     = I2C_GET_ADDR_MATCH(hi2c);
+    ownadd1code       = I2C_GET_OWN_ADDRESS1(hi2c);
+    ownadd2code       = I2C_GET_OWN_ADDRESS2(hi2c);
+
+    /* If 10bits addressing mode is selected */
+    if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+    {
+      if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK))
+      {
+        slaveaddrcode = ownadd1code;
+        hi2c->AddrEventCount++;
+        if (hi2c->AddrEventCount == 2U)
+        {
+          /* Reset Address Event counter */
+          hi2c->AddrEventCount = 0U;
+
+          /* Clear ADDR flag */
+          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2c);
+
+          /* Call Slave Addr callback */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+          hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#else
+          HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+        }
+      }
+      else
+      {
+        slaveaddrcode = ownadd2code;
+
+        /* Disable ADDR Interrupts */
+        I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Call Slave Addr callback */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+        hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#else
+        HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+      }
+    }
+    /* else 7 bits addressing mode is selected */
+    else
+    {
+      /* Disable ADDR Interrupts */
+      I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Call Slave Addr callback */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#else
+      HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+  }
+  /* Else clear address flag only */
+  else
+  {
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+  }
+}
+
+/**
+  * @brief  I2C Master sequential complete process.
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c)
+{
+  /* Reset I2C handle mode */
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+
+  /* No Generate Stop, to permit restart mode */
+  /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
+  if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+  {
+    hi2c->State         = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+    hi2c->XferISR       = NULL;
+
+    /* Disable Interrupts */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->MasterTxCpltCallback(hi2c);
+#else
+    HAL_I2C_MasterTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+  /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
+  else
+  {
+    hi2c->State         = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+    hi2c->XferISR       = NULL;
+
+    /* Disable Interrupts */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->MasterRxCpltCallback(hi2c);
+#else
+    HAL_I2C_MasterRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief  I2C Slave sequential complete process.
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
+{
+  uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
+
+  /* Reset I2C handle mode */
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+
+  /* If a DMA is ongoing, Update handle size context */
+  if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+  }
+  else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+  }
+  else
+  {
+    /* Do nothing */
+  }
+
+  if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+  {
+    /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
+    hi2c->State         = HAL_I2C_STATE_LISTEN;
+    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+
+    /* Disable Interrupts */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->SlaveTxCpltCallback(hi2c);
+#else
+    HAL_I2C_SlaveTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+
+  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+  {
+    /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
+    hi2c->State         = HAL_I2C_STATE_LISTEN;
+    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+
+    /* Disable Interrupts */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->SlaveRxCpltCallback(hi2c);
+#else
+    HAL_I2C_SlaveRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+}
+
+/**
+  * @brief  I2C Master complete process.
+  * @param  hi2c I2C handle.
+  * @param  ITFlags Interrupt flags to handle.
+  * @retval None
+  */
+static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+  uint32_t tmperror;
+  uint32_t tmpITFlags = ITFlags;
+  uint32_t tmp;
+
+  /* Clear STOP Flag */
+  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+  /* Disable Interrupts and Store Previous state */
+  if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+  {
+    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+    hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+  }
+  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+  {
+    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+    hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+  }
+  else
+  {
+    /* Do nothing */
+  }
+
+  /* Clear Configuration Register 2 */
+  I2C_RESET_CR2(hi2c);
+
+  /* Reset handle parameters */
+  hi2c->XferISR       = NULL;
+  hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
+
+  if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET)
+  {
+    /* Clear NACK Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    /* Set acknowledge error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+  }
+
+  /* Fetch Last receive data if any */
+  if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET))
+  {
+    /* Read data from RXDR */
+    tmp = (uint8_t)hi2c->Instance->RXDR;
+
+    UNUSED(tmp);
+  }
+
+  /* Flush TX register */
+  I2C_Flush_TXDR(hi2c);
+
+  /* Store current volatile hi2c->ErrorCode, misra rule */
+  tmperror = hi2c->ErrorCode;
+
+  /* Call the corresponding callback to inform upper layer of End of Transfer */
+  if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE))
+  {
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    I2C_ITError(hi2c, hi2c->ErrorCode);
+  }
+  /* hi2c->State == HAL_I2C_STATE_BUSY_TX */
+  else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    if (hi2c->Mode == HAL_I2C_MODE_MEM)
+    {
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->MemTxCpltCallback(hi2c);
+#else
+      HAL_I2C_MemTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+    else
+    {
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->MasterTxCpltCallback(hi2c);
+#else
+      HAL_I2C_MasterTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+  }
+  /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
+  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    if (hi2c->Mode == HAL_I2C_MODE_MEM)
+    {
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->MemRxCpltCallback(hi2c);
+#else
+      HAL_I2C_MemRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+    else
+    {
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->MasterRxCpltCallback(hi2c);
+#else
+      HAL_I2C_MasterRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+}
+
+/**
+  * @brief  I2C Slave complete process.
+  * @param  hi2c I2C handle.
+  * @param  ITFlags Interrupt flags to handle.
+  * @retval None
+  */
+static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+  uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
+  uint32_t tmpITFlags = ITFlags;
+  HAL_I2C_StateTypeDef tmpstate = hi2c->State;
+
+  /* Clear STOP Flag */
+  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+  /* Disable Interrupts and Store Previous state */
+  if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
+  {
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+  }
+  else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+  {
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
+    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+  }
+  else
+  {
+    /* Do nothing */
+  }
+
+  /* Disable Address Acknowledge */
+  hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+  /* Clear Configuration Register 2 */
+  I2C_RESET_CR2(hi2c);
+
+  /* Flush TX register */
+  I2C_Flush_TXDR(hi2c);
+
+  /* If a DMA is ongoing, Update handle size context */
+  if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+    if (hi2c->hdmatx != NULL)
+    {
+      hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx);
+    }
+  }
+  else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+    if (hi2c->hdmarx != NULL)
+    {
+      hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx);
+    }
+  }
+  else
+  {
+    /* Do nothing */
+  }
+
+  /* Store Last receive data if any */
+  if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)
+  {
+    /* Remove RXNE flag on temporary variable as read done */
+    tmpITFlags &= ~I2C_FLAG_RXNE;
+
+    /* Read data from RXDR */
+    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    if ((hi2c->XferSize > 0U))
+    {
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+    }
+  }
+
+  /* All data are not transferred, so set error code accordingly */
+  if (hi2c->XferCount != 0U)
+  {
+    /* Set ErrorCode corresponding to a Non-Acknowledge */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+  }
+
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+  hi2c->XferISR = NULL;
+
+  if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+  {
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    I2C_ITError(hi2c, hi2c->ErrorCode);
+
+    /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+    if (hi2c->State == HAL_I2C_STATE_LISTEN)
+    {
+      /* Call I2C Listen complete process */
+      I2C_ITListenCplt(hi2c, tmpITFlags);
+    }
+  }
+  else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+  {
+    /* Call the Sequential Complete callback, to inform upper layer of the end of Tranfer */
+    I2C_ITSlaveSeqCplt(hi2c);
+
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->ListenCpltCallback(hi2c);
+#else
+    HAL_I2C_ListenCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+  /* Call the corresponding callback to inform upper layer of End of Transfer */
+  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->SlaveRxCpltCallback(hi2c);
+#else
+    HAL_I2C_SlaveRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->SlaveTxCpltCallback(hi2c);
+#else
+    HAL_I2C_SlaveTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief  I2C Listen complete process.
+  * @param  hi2c I2C handle.
+  * @param  ITFlags Interrupt flags to handle.
+  * @retval None
+  */
+static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+  /* Reset handle parameters */
+  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+  hi2c->PreviousState = I2C_STATE_NONE;
+  hi2c->State = HAL_I2C_STATE_READY;
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+  hi2c->XferISR = NULL;
+
+  /* Store Last receive data if any */
+  if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET)
+  {
+    /* Read data from RXDR */
+    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    if ((hi2c->XferSize > 0U))
+    {
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+
+      /* Set ErrorCode corresponding to a Non-Acknowledge */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+    }
+  }
+
+  /* Disable all Interrupts*/
+  I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
+
+  /* Clear NACK Flag */
+  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+  hi2c->ListenCpltCallback(hi2c);
+#else
+  HAL_I2C_ListenCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  I2C interrupts error process.
+  * @param  hi2c I2C handle.
+  * @param  ErrorCode Error code to handle.
+  * @retval None
+  */
+static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
+{
+  HAL_I2C_StateTypeDef tmpstate = hi2c->State;
+  uint32_t tmppreviousstate;
+
+  /* Reset handle parameters */
+  hi2c->Mode          = HAL_I2C_MODE_NONE;
+  hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
+  hi2c->XferCount     = 0U;
+
+  /* Set new error code */
+  hi2c->ErrorCode |= ErrorCode;
+
+  /* Disable Interrupts */
+  if ((tmpstate == HAL_I2C_STATE_LISTEN)         ||
+      (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
+      (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+  {
+    /* Disable all interrupts, except interrupts related to LISTEN state */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
+
+    /* keep HAL_I2C_STATE_LISTEN if set */
+    hi2c->State         = HAL_I2C_STATE_LISTEN;
+    hi2c->XferISR       = I2C_Slave_ISR_IT;
+  }
+  else
+  {
+    /* Disable all interrupts */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
+
+    /* If state is an abort treatment on goind, don't change state */
+    /* This change will be do later */
+    if (hi2c->State != HAL_I2C_STATE_ABORT)
+    {
+      /* Set HAL_I2C_STATE_READY */
+      hi2c->State         = HAL_I2C_STATE_READY;
+    }
+    hi2c->XferISR       = NULL;
+  }
+
+  /* Abort DMA TX transfer if any */
+  tmppreviousstate = hi2c->PreviousState;
+  if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
+  {
+    if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+    {
+      hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+    }
+
+    if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
+    {
+      /* Set the I2C DMA Abort callback :
+       will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+      hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Abort DMA TX */
+      if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+      {
+        /* Call Directly XferAbortCallback function in case of error */
+        hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+      }
+    }
+    else
+    {
+      I2C_TreatErrorCallback(hi2c);
+    }
+  }
+  /* Abort DMA RX transfer if any */
+  else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
+  {
+    if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+    {
+      hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+    }
+
+    if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
+    {
+      /* Set the I2C DMA Abort callback :
+        will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+      hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Abort DMA RX */
+      if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+      {
+        /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
+        hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+      }
+    }
+    else
+    {
+      I2C_TreatErrorCallback(hi2c);
+    }
+  }
+  else
+  {
+    I2C_TreatErrorCallback(hi2c);
+  }
+}
+
+/**
+  * @brief  I2C Error callback treatment.
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c)
+{
+  if (hi2c->State == HAL_I2C_STATE_ABORT)
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->AbortCpltCallback(hi2c);
+#else
+    HAL_I2C_AbortCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->ErrorCallback(hi2c);
+#else
+    HAL_I2C_ErrorCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief  I2C Tx data register flush process.
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
+{
+  /* If a pending TXIS flag is set */
+  /* Write a dummy data in TXDR to clear it */
+  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
+  {
+    hi2c->Instance->TXDR = 0x00U;
+  }
+
+  /* Flush TX register if not empty */
+  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
+  {
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
+  }
+}
+
+/**
+  * @brief  DMA I2C master transmit process complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+
+  /* Disable DMA Request */
+  hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+  /* If last transfer, enable STOP interrupt */
+  if (hi2c->XferCount == 0U)
+  {
+    /* Enable STOP interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+  }
+  /* else prepare a new DMA transfer and enable TCReload interrupt */
+  else
+  {
+    /* Update Buffer pointer */
+    hi2c->pBuffPtr += hi2c->XferSize;
+
+    /* Set the XferSize to transfer */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+    }
+
+    /* Enable the DMA stream or channel depends on Instance */
+    if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize) != HAL_OK)
+    {
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+      I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+    }
+    else
+    {
+      /* Enable TC interrupts */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
+    }
+  }
+}
+
+/**
+  * @brief  DMA I2C slave transmit process complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+  uint32_t tmpoptions = hi2c->XferOptions;
+
+  if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+    /* Last Byte is Transmitted */
+    /* Call I2C Slave Sequential complete process */
+    I2C_ITSlaveSeqCplt(hi2c);
+  }
+  else
+  {
+    /* No specific action, Master fully manage the generation of STOP condition */
+    /* Mean that this generation can arrive at any time, at the end or during DMA process */
+    /* So STOP condition should be manage through Interrupt treatment */
+  }
+}
+
+/**
+  * @brief DMA I2C master receive process complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+
+  /* Disable DMA Request */
+  hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+  /* If last transfer, enable STOP interrupt */
+  if (hi2c->XferCount == 0U)
+  {
+    /* Enable STOP interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+  }
+  /* else prepare a new DMA transfer and enable TCReload interrupt */
+  else
+  {
+    /* Update Buffer pointer */
+    hi2c->pBuffPtr += hi2c->XferSize;
+
+    /* Set the XferSize to transfer */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+    }
+
+    /* Enable the DMA stream or channel depends on Instance */
+    if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize) != HAL_OK)
+    {
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+      I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+    }
+    else
+    {
+      /* Enable TC interrupts */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
+    }
+  }
+}
+
+/**
+  * @brief  DMA I2C slave receive process complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+  uint32_t tmpoptions = hi2c->XferOptions;
+
+  if ((__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) && \
+      (tmpoptions != I2C_NO_OPTION_FRAME))
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+    /* Call I2C Slave Sequential complete process */
+    I2C_ITSlaveSeqCplt(hi2c);
+  }
+  else
+  {
+    /* No specific action, Master fully manage the generation of STOP condition */
+    /* Mean that this generation can arrive at any time, at the end or during DMA process */
+    /* So STOP condition should be manage through Interrupt treatment */
+  }
+}
+
+/**
+  * @brief  DMA I2C communication error callback.
+  * @param hdma DMA handle
+  * @retval None
+  */
+static void I2C_DMAError(DMA_HandleTypeDef *hdma)
+{
+  uint32_t treatdmaerror = 0U;
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+
+  if (hi2c->hdmatx != NULL)
+  {
+    if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U)
+    {
+      treatdmaerror = 1U;
+    }
+  }
+
+  if (hi2c->hdmarx != NULL)
+  {
+    if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U)
+    {
+      treatdmaerror = 1U;
+    }
+  }
+
+  /* Check if a FIFO error is detected, if true normal use case, so no specific action to perform */
+  if (!((HAL_DMA_GetError(hdma) == HAL_DMA_ERROR_FE)) && (treatdmaerror != 0U))
+  {
+    /* Disable Acknowledge */
+    hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+  }
+}
+
+/**
+  * @brief DMA I2C communication abort callback
+  *        (To be called at end of DMA Abort procedure).
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
+{
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+
+  /* Reset AbortCpltCallback */
+  if (hi2c->hdmatx != NULL)
+  {
+    hi2c->hdmatx->XferAbortCallback = NULL;
+  }
+  if (hi2c->hdmarx != NULL)
+  {
+    hi2c->hdmarx->XferAbortCallback = NULL;
+  }
+
+  I2C_TreatErrorCallback(hi2c);
+}
+
+/**
+  * @brief  This function handles I2C Communication Timeout.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Flag Specifies the I2C flag to check.
+  * @param  Status The new Flag status (SET or RESET).
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
+{
+  while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
+  {
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+      {
+        hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+        hi2c->State = HAL_I2C_STATE_READY;
+        hi2c->Mode = HAL_I2C_MODE_NONE;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        return HAL_ERROR;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles I2C Communication Timeout for specific usage of TXIS flag.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+{
+  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
+  {
+    /* Check if a NACK is detected */
+    if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+      {
+        hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+        hi2c->State = HAL_I2C_STATE_READY;
+        hi2c->Mode = HAL_I2C_MODE_NONE;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles I2C Communication Timeout for specific usage of STOP flag.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+{
+  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+  {
+    /* Check if a NACK is detected */
+    if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Check for the Timeout */
+    if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+    {
+      hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+      hi2c->State = HAL_I2C_STATE_READY;
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles I2C Communication Timeout for specific usage of RXNE flag.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+{
+  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
+  {
+    /* Check if a NACK is detected */
+    if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Check if a STOPF is detected */
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
+    {
+      /* Check if an RXNE is pending */
+      /* Store Last receive data if any */
+      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U))
+      {
+        /* Return HAL_OK */
+        /* The Reading of data from RXDR will be done in caller function */
+        return HAL_OK;
+      }
+      else
+      {
+        /* Clear STOP Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+        /* Clear Configuration Register 2 */
+        I2C_RESET_CR2(hi2c);
+
+        hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+        hi2c->State = HAL_I2C_STATE_READY;
+        hi2c->Mode = HAL_I2C_MODE_NONE;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+
+    /* Check for the Timeout */
+    if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+    {
+      hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+      hi2c->State = HAL_I2C_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles Acknowledge failed detection during an I2C Communication.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+{
+  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+  {
+    /* Wait until STOP Flag is reset */
+    /* AutoEnd should be initiate after AF */
+    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+    {
+      /* Check for the Timeout */
+      if (Timeout != HAL_MAX_DELAY)
+      {
+        if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+        {
+          hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+          hi2c->State = HAL_I2C_STATE_READY;
+          hi2c->Mode = HAL_I2C_MODE_NONE;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2c);
+
+          return HAL_ERROR;
+        }
+      }
+    }
+
+    /* Clear NACKF Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    /* Clear STOP Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Flush TX register */
+    I2C_Flush_TXDR(hi2c);
+
+    /* Clear Configuration Register 2 */
+    I2C_RESET_CR2(hi2c);
+
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_ERROR;
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
+  * @param  hi2c I2C handle.
+  * @param  DevAddress Specifies the slave address to be programmed.
+  * @param  Size Specifies the number of bytes to be programmed.
+  *   This parameter must be a value between 0 and 255.
+  * @param  Mode New state of the I2C START condition generation.
+  *   This parameter can be one of the following values:
+  *     @arg @ref I2C_RELOAD_MODE Enable Reload mode .
+  *     @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.
+  *     @arg @ref I2C_SOFTEND_MODE Enable Software end mode.
+  * @param  Request New state of the I2C START condition generation.
+  *   This parameter can be one of the following values:
+  *     @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.
+  *     @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
+  *     @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
+  *     @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
+  * @retval None
+  */
+static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  assert_param(IS_TRANSFER_MODE(Mode));
+  assert_param(IS_TRANSFER_REQUEST(Request));
+
+  /* update CR2 register */
+  MODIFY_REG(hi2c->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \
+             (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
+}
+
+/**
+  * @brief  Manage the enabling of Interrupts.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
+  * @retval None
+  */
+static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
+{
+  uint32_t tmpisr = 0U;
+
+  if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \
+      (hi2c->XferISR == I2C_Slave_ISR_DMA))
+  {
+    if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+    {
+      /* Enable ERR, STOP, NACK and ADDR interrupts */
+      tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+    }
+
+    if (InterruptRequest == I2C_XFER_ERROR_IT)
+    {
+      /* Enable ERR and NACK interrupts */
+      tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
+    }
+
+    if (InterruptRequest == I2C_XFER_CPLT_IT)
+    {
+      /* Enable STOP interrupts */
+      tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
+    }
+
+    if (InterruptRequest == I2C_XFER_RELOAD_IT)
+    {
+      /* Enable TC interrupts */
+      tmpisr |= I2C_IT_TCI;
+    }
+  }
+  else
+  {
+    if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+    {
+      /* Enable ERR, STOP, NACK, and ADDR interrupts */
+      tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+    }
+
+    if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
+    {
+      /* Enable ERR, TC, STOP, NACK and RXI interrupts */
+      tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
+    }
+
+    if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
+    {
+      /* Enable ERR, TC, STOP, NACK and TXI interrupts */
+      tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
+    }
+
+    if (InterruptRequest == I2C_XFER_CPLT_IT)
+    {
+      /* Enable STOP interrupts */
+      tmpisr |= I2C_IT_STOPI;
+    }
+  }
+
+  /* Enable interrupts only at the end */
+  /* to avoid the risk of I2C interrupt handle execution before */
+  /* all interrupts requested done */
+  __HAL_I2C_ENABLE_IT(hi2c, tmpisr);
+}
+
+/**
+  * @brief  Manage the disabling of Interrupts.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
+  * @retval None
+  */
+static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
+{
+  uint32_t tmpisr = 0U;
+
+  if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
+  {
+    /* Disable TC and TXI interrupts */
+    tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
+
+    if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
+    {
+      /* Disable NACK and STOP interrupts */
+      tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+    }
+  }
+
+  if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
+  {
+    /* Disable TC and RXI interrupts */
+    tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
+
+    if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
+    {
+      /* Disable NACK and STOP interrupts */
+      tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+    }
+  }
+
+  if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+  {
+    /* Disable ADDR, NACK and STOP interrupts */
+    tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+  }
+
+  if (InterruptRequest == I2C_XFER_ERROR_IT)
+  {
+    /* Enable ERR and NACK interrupts */
+    tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
+  }
+
+  if (InterruptRequest == I2C_XFER_CPLT_IT)
+  {
+    /* Enable STOP interrupts */
+    tmpisr |= I2C_IT_STOPI;
+  }
+
+  if (InterruptRequest == I2C_XFER_RELOAD_IT)
+  {
+    /* Enable TC interrupts */
+    tmpisr |= I2C_IT_TCI;
+  }
+
+  /* Disable interrupts only at the end */
+  /* to avoid a breaking situation like at "t" time */
+  /* all disable interrupts request are not done */
+  __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
+}
+
+/**
+  * @brief  Convert I2Cx OTHER_xxx XferOptions to functionnal XferOptions.
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
+{
+  /* if user set XferOptions to I2C_OTHER_FRAME            */
+  /* it request implicitly to generate a restart condition */
+  /* set XferOptions to I2C_FIRST_FRAME                    */
+  if (hi2c->XferOptions == I2C_OTHER_FRAME)
+  {
+    hi2c->XferOptions = I2C_FIRST_FRAME;
+  }
+  /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
+  /* it request implicitly to generate a restart condition    */
+  /* then generate a stop condition at the end of transfer    */
+  /* set XferOptions to I2C_FIRST_AND_LAST_FRAME              */
+  else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
+  {
+    hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_I2C_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c
new file mode 100644
index 00000000..ea50ce31
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c
@@ -0,0 +1,339 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_i2c_ex.c
+  * @author  MCD Application Team
+  * @brief   I2C Extended HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of I2C Extended peripheral:
+  *           + Extended features functions
+  *
+  @verbatim
+  ==============================================================================
+               ##### I2C peripheral Extended features  #####
+  ==============================================================================
+
+  [..] Comparing to other previous devices, the I2C interface for STM32H7xx
+       devices contains the following additional features
+
+       (+) Possibility to disable or enable Analog Noise Filter
+       (+) Use of a configured Digital Noise Filter
+       (+) Disable or enable wakeup from Stop mode(s)
+       (+) Disable or enable Fast Mode Plus
+
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..] This driver provides functions to configure Noise Filter and Wake Up Feature
+    (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
+    (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
+    (#) Configure the enable or disable of I2C Wake Up Mode using the functions :
+          (++) HAL_I2CEx_EnableWakeUp()
+          (++) HAL_I2CEx_DisableWakeUp()
+    (#) Configure the enable or disable of fast mode plus driving capability using the functions :
+          (++) HAL_I2CEx_EnableFastModePlus()
+          (++) HAL_I2CEx_DisableFastModePlus()
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup I2CEx I2CEx
+  * @brief I2C Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions
+  * @brief    Extended features functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### Extended features functions #####
+ ===============================================================================
+    [..] This section provides functions allowing to:
+      (+) Configure Noise Filters
+      (+) Configure Wake Up Feature
+      (+) Configure Fast Mode Plus
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure I2C Analog noise filter.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2Cx peripheral.
+  * @param  AnalogFilter New state of the Analog filter.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+
+    /* Disable the selected I2C peripheral */
+    __HAL_I2C_DISABLE(hi2c);
+
+    /* Reset I2Cx ANOFF bit */
+    hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
+
+    /* Set analog filter bit*/
+    hi2c->Instance->CR1 |= AnalogFilter;
+
+    __HAL_I2C_ENABLE(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Configure I2C Digital noise filter.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2Cx peripheral.
+  * @param  DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
+{
+  uint32_t tmpreg;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+
+    /* Disable the selected I2C peripheral */
+    __HAL_I2C_DISABLE(hi2c);
+
+    /* Get the old register value */
+    tmpreg = hi2c->Instance->CR1;
+
+    /* Reset I2Cx DNF bits [11:8] */
+    tmpreg &= ~(I2C_CR1_DNF);
+
+    /* Set I2Cx DNF coefficient */
+    tmpreg |= DigitalFilter << 8U;
+
+    /* Store the new register value */
+    hi2c->Instance->CR1 = tmpreg;
+
+    __HAL_I2C_ENABLE(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Enable I2C wakeup from Stop mode(s).
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2Cx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+
+    /* Disable the selected I2C peripheral */
+    __HAL_I2C_DISABLE(hi2c);
+
+    /* Enable wakeup from stop mode */
+    hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
+
+    __HAL_I2C_ENABLE(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Disable I2C wakeup from Stop mode(s).
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2Cx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+
+    /* Disable the selected I2C peripheral */
+    __HAL_I2C_DISABLE(hi2c);
+
+    /* Enable wakeup from stop mode */
+    hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
+
+    __HAL_I2C_ENABLE(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Enable the I2C fast mode plus driving capability.
+  * @param ConfigFastModePlus Selects the pin.
+  *   This parameter can be one of the @ref I2CEx_FastModePlus values
+  * @note  For I2C1, fast mode plus driving capability can be enabled on all selected
+  *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
+  *        on each one of the following pins PB6, PB7, PB8 and PB9.
+  * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
+  *        can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
+  * @note  For all I2C2 pins fast mode plus driving capability can be enabled
+  *        only by using I2C_FASTMODEPLUS_I2C2 parameter.
+  * @note  For all I2C3 pins fast mode plus driving capability can be enabled
+  *        only by using I2C_FASTMODEPLUS_I2C3 parameter.
+  * @note  For all I2C4 pins fast mode plus driving capability can be enabled
+  *        only by using I2C_FASTMODEPLUS_I2C4 parameter.
+  * @retval None
+  */
+void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
+{
+  /* Check the parameter */
+  assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
+
+  /* Enable SYSCFG clock */
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+  /* Enable fast mode plus driving capability for selected pin */
+  SET_BIT(SYSCFG->PMCR, (uint32_t)ConfigFastModePlus);
+}
+
+/**
+  * @brief Disable the I2C fast mode plus driving capability.
+  * @param ConfigFastModePlus Selects the pin.
+  *   This parameter can be one of the @ref I2CEx_FastModePlus values
+  * @note  For I2C1, fast mode plus driving capability can be disabled on all selected
+  *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
+  *        on each one of the following pins PB6, PB7, PB8 and PB9.
+  * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
+  *        can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
+  * @note  For all I2C2 pins fast mode plus driving capability can be disabled
+  *        only by using I2C_FASTMODEPLUS_I2C2 parameter.
+  * @note  For all I2C3 pins fast mode plus driving capability can be disabled
+  *        only by using I2C_FASTMODEPLUS_I2C3 parameter.
+  * @note  For all I2C4 pins fast mode plus driving capability can be disabled
+  *        only by using I2C_FASTMODEPLUS_I2C4 parameter.
+  * @retval None
+  */
+void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
+{
+  /* Check the parameter */
+  assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
+
+  /* Enable SYSCFG clock */
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+  /* Disable fast mode plus driving capability for selected pin */
+  CLEAR_BIT(SYSCFG->PMCR, (uint32_t)ConfigFastModePlus);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_I2C_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c
new file mode 100644
index 00000000..08498c46
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c
@@ -0,0 +1,1901 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_mdma.c
+  * @author  MCD Application Team
+  * @brief  This file provides firmware functions to manage the following
+  *         functionalities of the Master Direct Memory Access (MDMA) peripheral:
+  *           + Initialization/de-initialization functions
+  *           + I/O operation functions
+  *           + Peripheral State and errors functions
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+   (#) Enable and configure the peripheral to be connected to the MDMA Channel
+       (except for internal SRAM/FLASH memories: no initialization is
+       necessary) please refer to Reference manual for connection between peripherals
+       and MDMA requests.
+
+   (#)
+       For a given Channel use HAL_MDMA_Init function to program the required configuration through the following parameters:
+       transfer request , channel priority, data endianness, Source increment, destination increment ,
+       source data size, destination data size, data alignment, source Burst, destination Burst ,
+       buffer Transfer Length, Transfer Trigger Mode (buffer transfer, block transfer, repeated block transfer
+       or full transfer) source and destination block address offset, mask address and data.
+
+       If using the MDMA in linked list mode then use function HAL_MDMA_LinkedList_CreateNode to fill a transfer node.
+       Note that parameters given to the function HAL_MDMA_Init corresponds always to the node zero.
+       Use function HAL_MDMA_LinkedList_AddNode to connect the created node to the linked list at a given position.
+       User can make a linked list circular using function HAL_MDMA_LinkedList_EnableCircularMode , this function will automatically connect the
+       last node of the list to the first one in order to make the list circular.
+       In this case the linked list will loop on node 1 : first node connected after the initial transfer defined by the HAL_MDMA_Init
+
+      -@-   The initial transfer itself (node 0 corresponding to the Init).
+            User can disable the circular mode using function HAL_MDMA_LinkedList_DisableCircularMode, this function will then remove
+            the connection between last node and first one.
+
+       Function HAL_MDMA_LinkedList_RemoveNode can be used to remove (disconnect) a node from the transfer linked list.
+       When a linked list is circular (last node connected to first one), if removing node1  (node where the linked list loops),
+       the linked list remains circular and node 2 becomes the first one.
+       Note that if the linked list is made circular the transfer will loop infinitely (or until aborted by the user).
+
+    [..]
+       (+) User can select the transfer trigger mode (parameter TransferTriggerMode) to define the amount of data to be
+           transfer upon a request :
+             (++) MDMA_BUFFER_TRANSFER : each request triggers a transfer of BufferTransferLength data
+               with BufferTransferLength defined within the HAL_MDMA_Init.
+             (++) MDMA_BLOCK_TRANSFER : each request triggers a transfer of a block
+               with block size defined within the function HAL_MDMA_Start/HAL_MDMA_Start_IT
+               or within the current linked list node parameters.
+             (++) MDMA_REPEAT_BLOCK_TRANSFER : each request triggers a transfer of a number of blocks
+               with block size and number of blocks defined within the function HAL_MDMA_Start/HAL_MDMA_Start_IT
+               or within the current linked list node parameters.
+             (++) MDMA_FULL_TRANSFER : each request triggers a full transfer
+              all blocks and all nodes(if a linked list has been created using HAL_MDMA_LinkedList_CreateNode \ HAL_MDMA_LinkedList_AddNode).
+
+     *** Polling mode IO operation ***
+     =================================
+    [..]
+          (+) Use HAL_MDMA_Start() to start MDMA transfer after the configuration of Source
+              address and destination address and the Length of data to be transferred.
+          (+) Use HAL_MDMA_PollForTransfer() to poll for the end of current transfer or a transfer level
+             In this case a fixed Timeout can be configured by User depending from his application.
+          (+) Use HAL_MDMA_Abort() function to abort the current transfer : blocking method this API returns
+              when the abort ends or timeout (should not be called from an interrupt service routine).
+
+     *** Interrupt mode IO operation ***
+     ===================================
+    [..]
+          (+) Configure the MDMA interrupt priority using HAL_NVIC_SetPriority()
+          (+) Enable the MDMA IRQ handler using HAL_NVIC_EnableIRQ()
+          (+) Use HAL_MDMA_Start_IT() to start MDMA transfer after the configuration of
+              Source address and destination address and the Length of data to be transferred. In this
+              case the MDMA interrupt is configured.
+          (+) Use HAL_MDMA_IRQHandler() called under MDMA_IRQHandler() Interrupt subroutine
+          (+) At the end of data transfer HAL_MDMA_IRQHandler() function is executed and user can
+              add his own function by customization of function pointer XferCpltCallback and
+              XferErrorCallback (i.e a member of MDMA handle structure).
+
+          (+) Use HAL_MDMA_Abort_IT() function to abort the current transfer : non-blocking method. This API will finish the execution immediately
+              then the callback XferAbortCallback (if specified  by the user) is asserted once the MDMA channel has effectively aborted.
+              (could be called from an interrupt service routine).
+
+          (+) Use functions HAL_MDMA_RegisterCallback and HAL_MDMA_UnRegisterCallback respectevely to register unregister user callbacks
+              from the following list :
+              (++) XferCpltCallback            : transfer complete callback.
+              (++) XferBufferCpltCallback      : buffer transfer complete callback.
+              (++) XferBlockCpltCallback       : block transfer complete callback.
+              (++) XferRepeatBlockCpltCallback : repeated block transfer complete callback.
+              (++) XferErrorCallback           : transfer error callback.
+              (++) XferAbortCallback           : transfer abort complete callback.
+
+    [..]
+         (+)  If the transfer Request corresponds to SW request (MDMA_REQUEST_SW) User can use function HAL_MDMA_GenerateSWRequest to
+              trigger requests manually. Function HAL_MDMA_GenerateSWRequest must be used with the following precautions:
+              (++) This function returns an error if used while the Transfer has ended or not started.
+              (++) If used while the current request has not been served yet (current request transfer on going)
+                this function returns an error and the new request is ignored.
+
+              Generally this function should be used in conjunctions with the MDMA callbacks:
+              (++) example 1:
+                 (+++) Configure a transfer with request set to MDMA_REQUEST_SW and trigger mode set to MDMA_BUFFER_TRANSFER
+                 (+++) Register a callback for buffer transfer complete (using callback ID set to HAL_MDMA_XFER_BUFFERCPLT_CB_ID)
+                 (+++) After calling HAL_MDMA_Start_IT the MDMA will issue the transfer of a first BufferTransferLength data.
+                 (+++) When the buffer transfer complete callback is asserted first buffer has been transferred and user can ask for a new buffer transfer
+                   request using HAL_MDMA_GenerateSWRequest.
+
+              (++) example 2:
+                 (+++) Configure a transfer with request set to MDMA_REQUEST_SW and trigger mode set to MDMA_BLOCK_TRANSFER
+                 (+++) Register a callback for block transfer complete (using callback ID HAL_MDMA_XFER_BLOCKCPLT_CB_ID)
+                 (+++) After calling HAL_MDMA_Start_IT the MDMA will issue the transfer of a first block of data.
+                 (+++) When the block transfer complete callback is asserted the first block has been transferred and user can ask
+                   for a new block transfer request using HAL_MDMA_GenerateSWRequest.
+
+    [..]  Use HAL_MDMA_GetState() function to return the MDMA state and HAL_MDMA_GetError() in case of error detection.
+
+     *** MDMA HAL driver macros list ***
+     =============================================
+     [..]
+       Below the list of most used macros in MDMA HAL driver.
+
+      (+) __HAL_MDMA_ENABLE: Enable the specified MDMA Channel.
+      (+) __HAL_MDMA_DISABLE: Disable the specified MDMA Channel.
+      (+) __HAL_MDMA_GET_FLAG: Get the MDMA Channel pending flags.
+      (+) __HAL_MDMA_CLEAR_FLAG: Clear the MDMA Channel pending flags.
+      (+) __HAL_MDMA_ENABLE_IT: Enable the specified MDMA Channel interrupts.
+      (+) __HAL_MDMA_DISABLE_IT: Disable the specified MDMA Channel interrupts.
+      (+) __HAL_MDMA_GET_IT_SOURCE: Check whether the specified MDMA Channel interrupt has occurred or not.
+
+     [..]
+      (@) You can refer to the header file of the MDMA HAL driver for more useful macros.
+
+    [..]
+
+    @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup MDMA  MDMA
+  * @brief MDMA HAL module driver
+  * @{
+  */
+
+#ifdef HAL_MDMA_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup MDMA_Private_Constants
+ * @{
+ */
+#define HAL_TIMEOUT_MDMA_ABORT    5U    /* 5 ms */
+#define HAL_MDMA_CHANNEL_SIZE     0x40U /* an MDMA instance channel size is 64 byte  */
+/**
+  * @}
+  */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup MDMA_Private_Functions_Prototypes
+  * @{
+  */
+static void MDMA_SetConfig(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount);
+static void MDMA_Init(MDMA_HandleTypeDef *hmdma);
+
+/**
+  * @}
+  */
+
+/** @addtogroup MDMA_Exported_Functions MDMA Exported Functions
+  * @{
+  */
+
+/** @addtogroup MDMA_Exported_Functions_Group1
+  *
+@verbatim
+ ===============================================================================
+             ##### Initialization and de-initialization functions  #####
+ ===============================================================================
+    [..]
+    This section provides functions allowing to :
+      Initialize and de-initialize the MDMA channel.
+      Register and Unregister MDMA callbacks
+    [..]
+    The HAL_MDMA_Init() function follows the MDMA channel configuration procedures as described in
+    reference manual.
+    The HAL_MDMA_DeInit function allows to deinitialize the MDMA channel.
+    HAL_MDMA_RegisterCallback and  HAL_MDMA_UnRegisterCallback functions allows
+    respectevely to register/unregister an MDMA callback function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the MDMA according to the specified
+  *         parameters in the MDMA_InitTypeDef and create the associated handle.
+  * @param  hmdma: Pointer to a MDMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified MDMA Channel.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_Init(MDMA_HandleTypeDef *hmdma)
+{
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_MDMA_STREAM_ALL_INSTANCE(hmdma->Instance));
+  assert_param(IS_MDMA_PRIORITY(hmdma->Init.Priority));
+  assert_param(IS_MDMA_ENDIANNESS_MODE(hmdma->Init.Endianness));
+  assert_param(IS_MDMA_REQUEST(hmdma->Init.Request));
+  assert_param(IS_MDMA_SOURCE_INC(hmdma->Init.SourceInc));
+  assert_param(IS_MDMA_DESTINATION_INC(hmdma->Init.DestinationInc));
+  assert_param(IS_MDMA_SOURCE_DATASIZE(hmdma->Init.SourceDataSize));
+  assert_param(IS_MDMA_DESTINATION_DATASIZE(hmdma->Init.DestDataSize));
+  assert_param(IS_MDMA_DATA_ALIGNMENT(hmdma->Init.DataAlignment));
+  assert_param(IS_MDMA_SOURCE_BURST(hmdma->Init.SourceBurst));
+  assert_param(IS_MDMA_DESTINATION_BURST(hmdma->Init.DestBurst));
+  assert_param(IS_MDMA_BUFFER_TRANSFER_LENGTH(hmdma->Init.BufferTransferLength));
+  assert_param(IS_MDMA_TRANSFER_TRIGGER_MODE(hmdma->Init.TransferTriggerMode));
+  assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(hmdma->Init.SourceBlockAddressOffset));
+  assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(hmdma->Init.DestBlockAddressOffset));
+
+
+  /* Allocate lock resource */
+  __HAL_UNLOCK(hmdma);
+
+  /* Change MDMA peripheral state */
+  hmdma->State = HAL_MDMA_STATE_BUSY;
+
+  /* Disable the MDMA channel */
+  __HAL_MDMA_DISABLE(hmdma);
+
+  /* Check if the MDMA channel is effectively disabled */
+  while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U)
+  {
+    /* Check for the Timeout */
+    if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_MDMA_ABORT)
+    {
+      /* Update error code */
+      hmdma->ErrorCode = HAL_MDMA_ERROR_TIMEOUT;
+
+      /* Change the MDMA state */
+      hmdma->State = HAL_MDMA_STATE_ERROR;
+
+      return HAL_ERROR;
+    }
+  }
+
+  /* Initialize the MDMA channel registers */
+  MDMA_Init(hmdma);
+
+  /* Reset the MDMA first/last linkedlist node addresses and node counter */
+  hmdma->FirstLinkedListNodeAddress  = 0;
+  hmdma->LastLinkedListNodeAddress   = 0;
+  hmdma->LinkedListNodeCounter  = 0;
+
+  /* Initialize the error code */
+  hmdma->ErrorCode = HAL_MDMA_ERROR_NONE;
+
+  /* Initialize the MDMA state */
+  hmdma->State = HAL_MDMA_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the MDMA peripheral
+  * @param  hmdma: pointer to a MDMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified MDMA Channel.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_DeInit(MDMA_HandleTypeDef *hmdma)
+{
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Disable the selected MDMA Channelx */
+  __HAL_MDMA_DISABLE(hmdma);
+
+  /* Reset MDMA Channel control register */
+  hmdma->Instance->CCR  = 0;
+  hmdma->Instance->CTCR = 0;
+  hmdma->Instance->CBNDTR = 0;
+  hmdma->Instance->CSAR = 0;
+  hmdma->Instance->CDAR = 0;
+  hmdma->Instance->CBRUR = 0;
+  hmdma->Instance->CLAR = 0;
+  hmdma->Instance->CTBR = 0;
+  hmdma->Instance->CMAR = 0;
+  hmdma->Instance->CMDR = 0;
+
+  /* Clear all flags */
+  __HAL_MDMA_CLEAR_FLAG(hmdma,(MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_FLAG_BRT | MDMA_FLAG_BT | MDMA_FLAG_BFTC));
+
+  /* Reset the  MDMA first/last linkedlist node addresses and node counter */
+  hmdma->FirstLinkedListNodeAddress  = 0;
+  hmdma->LastLinkedListNodeAddress   = 0;
+  hmdma->LinkedListNodeCounter  = 0;
+
+  /* Initialize the error code */
+  hmdma->ErrorCode = HAL_MDMA_ERROR_NONE;
+
+  /* Initialize the MDMA state */
+  hmdma->State = HAL_MDMA_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hmdma);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Config the Post request Mask address and Mask data
+  * @param  hmdma      : pointer to a MDMA_HandleTypeDef structure that contains
+  *                               the configuration information for the specified MDMA Channel.
+  * @param  MaskAddress: specifies the address to be updated (written) with MaskData after a request is served.
+  * @param  MaskData:    specifies the value to be written to MaskAddress after a request is served.
+  *                      MaskAddress and MaskData could be used to automatically clear a peripheral flag when the request is served.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_ConfigPostRequestMask(MDMA_HandleTypeDef *hmdma, uint32_t MaskAddress, uint32_t MaskData)
+{
+  HAL_StatusTypeDef  status = HAL_OK;
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hmdma);
+
+  if(HAL_MDMA_STATE_READY == hmdma->State)
+  {
+    /* if HW request set Post Request MaskAddress and MaskData,  */
+    if((hmdma->Instance->CTCR & MDMA_CTCR_SWRM) == 0U)
+    {
+      /* Set the HW request clear Mask and Data */
+      hmdma->Instance->CMAR = MaskAddress;
+      hmdma->Instance->CMDR = MaskData;
+
+      /*
+      -If the request is done by SW : BWM could be set to 1 or 0.
+      -If the request is done by a peripheral :
+         If mask address not set (0) => BWM must be set to 0
+         If mask address set (different than 0) => BWM could be set to 1 or 0
+      */
+      if(MaskAddress == 0U)
+      {
+        hmdma->Instance->CTCR &=  ~MDMA_CTCR_BWM;
+      }
+      else
+      {
+        hmdma->Instance->CTCR |=  MDMA_CTCR_BWM;
+      }
+    }
+    else
+    {
+      /* Return error status */
+      status =  HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+  /* Release Lock */
+  __HAL_UNLOCK(hmdma);
+
+  return status;
+}
+
+/**
+  * @brief  Register callbacks
+  * @param  hmdma:                pointer to a MDMA_HandleTypeDef structure that contains
+  *                               the configuration information for the specified MDMA Channel.
+  * @param  CallbackID:           User Callback identifier
+  * @param  pCallback:            pointer to callbacsk function.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_RegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID, void (* pCallback)(MDMA_HandleTypeDef *_hmdma))
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hmdma);
+
+  if(HAL_MDMA_STATE_READY == hmdma->State)
+  {
+    switch (CallbackID)
+    {
+    case  HAL_MDMA_XFER_CPLT_CB_ID:
+      hmdma->XferCpltCallback = pCallback;
+      break;
+
+    case  HAL_MDMA_XFER_BUFFERCPLT_CB_ID:
+      hmdma->XferBufferCpltCallback = pCallback;
+      break;
+
+    case  HAL_MDMA_XFER_BLOCKCPLT_CB_ID:
+      hmdma->XferBlockCpltCallback = pCallback;
+      break;
+
+    case  HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID:
+      hmdma->XferRepeatBlockCpltCallback = pCallback;
+      break;
+
+    case  HAL_MDMA_XFER_ERROR_CB_ID:
+      hmdma->XferErrorCallback = pCallback;
+      break;
+
+    case  HAL_MDMA_XFER_ABORT_CB_ID:
+      hmdma->XferAbortCallback = pCallback;
+      break;
+
+    default:
+      break;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hmdma);
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister callbacks
+  * @param  hmdma:                 pointer to a MDMA_HandleTypeDef structure that contains
+  *                               the configuration information for the specified MDMA Channel.
+  * @param  CallbackID:           User Callback identifier
+  *                               a HAL_MDMA_CallbackIDTypeDef ENUM as parameter.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_UnRegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hmdma);
+
+  if(HAL_MDMA_STATE_READY == hmdma->State)
+  {
+    switch (CallbackID)
+    {
+    case  HAL_MDMA_XFER_CPLT_CB_ID:
+      hmdma->XferCpltCallback = NULL;
+      break;
+
+    case  HAL_MDMA_XFER_BUFFERCPLT_CB_ID:
+      hmdma->XferBufferCpltCallback = NULL;
+      break;
+
+    case  HAL_MDMA_XFER_BLOCKCPLT_CB_ID:
+      hmdma->XferBlockCpltCallback = NULL;
+      break;
+
+    case  HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID:
+      hmdma->XferRepeatBlockCpltCallback = NULL;
+      break;
+
+    case  HAL_MDMA_XFER_ERROR_CB_ID:
+      hmdma->XferErrorCallback = NULL;
+      break;
+
+    case  HAL_MDMA_XFER_ABORT_CB_ID:
+      hmdma->XferAbortCallback = NULL;
+      break;
+
+    case   HAL_MDMA_XFER_ALL_CB_ID:
+      hmdma->XferCpltCallback = NULL;
+      hmdma->XferBufferCpltCallback = NULL;
+      hmdma->XferBlockCpltCallback = NULL;
+      hmdma->XferRepeatBlockCpltCallback = NULL;
+      hmdma->XferErrorCallback = NULL;
+      hmdma->XferAbortCallback = NULL;
+      break;
+
+    default:
+      status = HAL_ERROR;
+      break;
+    }
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hmdma);
+
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup MDMA_Exported_Functions_Group2
+ *
+@verbatim
+ ===============================================================================
+                      #####  Linked list operation functions  #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Create a linked list node
+      (+) Add a node to the MDMA linked list
+      (+) Remove a node from the MDMA linked list
+      (+) Enable/Disable linked list circular mode
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes an MDMA Link Node according to the specified
+  *         parameters in the pMDMA_LinkedListNodeConfig .
+  * @param  pNode: Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node
+  *         registers configurations.
+  * @param  pNodeConfig: Pointer to a MDMA_LinkNodeConfTypeDef structure that contains
+  *               the configuration information for the specified MDMA Linked List Node.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig)
+{
+  uint32_t addressMask;
+  uint32_t blockoffset;
+
+  /* Check the MDMA peripheral state */
+  if((pNode == NULL) || (pNodeConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_MDMA_PRIORITY(pNodeConfig->Init.Priority));
+  assert_param(IS_MDMA_ENDIANNESS_MODE(pNodeConfig->Init.Endianness));
+  assert_param(IS_MDMA_REQUEST(pNodeConfig->Init.Request));
+  assert_param(IS_MDMA_SOURCE_INC(pNodeConfig->Init.SourceInc));
+  assert_param(IS_MDMA_DESTINATION_INC(pNodeConfig->Init.DestinationInc));
+  assert_param(IS_MDMA_SOURCE_DATASIZE(pNodeConfig->Init.SourceDataSize));
+  assert_param(IS_MDMA_DESTINATION_DATASIZE(pNodeConfig->Init.DestDataSize));
+  assert_param(IS_MDMA_DATA_ALIGNMENT(pNodeConfig->Init.DataAlignment));
+  assert_param(IS_MDMA_SOURCE_BURST(pNodeConfig->Init.SourceBurst));
+  assert_param(IS_MDMA_DESTINATION_BURST(pNodeConfig->Init.DestBurst));
+  assert_param(IS_MDMA_BUFFER_TRANSFER_LENGTH(pNodeConfig->Init.BufferTransferLength));
+  assert_param(IS_MDMA_TRANSFER_TRIGGER_MODE(pNodeConfig->Init.TransferTriggerMode));
+  assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(pNodeConfig->Init.SourceBlockAddressOffset));
+  assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(pNodeConfig->Init.DestBlockAddressOffset));
+
+  assert_param(IS_MDMA_TRANSFER_LENGTH(pNodeConfig->BlockDataLength));
+  assert_param(IS_MDMA_BLOCK_COUNT(pNodeConfig->BlockCount));
+
+
+  /* Configure next Link node Address Register to zero */
+  pNode->CLAR =  0;
+
+  /* Configure the Link Node registers*/
+  pNode->CTBR   = 0;
+  pNode->CMAR   = 0;
+  pNode->CMDR   = 0;
+  pNode->Reserved = 0;
+
+  /* Write new CTCR Register value */
+  pNode->CTCR =  pNodeConfig->Init.SourceInc | pNodeConfig->Init.DestinationInc | \
+    pNodeConfig->Init.SourceDataSize | pNodeConfig->Init.DestDataSize           | \
+      pNodeConfig->Init.DataAlignment| pNodeConfig->Init.SourceBurst            | \
+        pNodeConfig->Init.DestBurst                                             | \
+          ((pNodeConfig->Init.BufferTransferLength - 1U) << MDMA_CTCR_TLEN_Pos) | \
+            pNodeConfig->Init.TransferTriggerMode;
+
+  /* If SW request set the CTCR register to SW Request Mode*/
+  if(pNodeConfig->Init.Request == MDMA_REQUEST_SW)
+  {
+    pNode->CTCR |= MDMA_CTCR_SWRM;
+  }
+
+  /*
+  -If the request is done by SW : BWM could be set to 1 or 0.
+  -If the request is done by a peripheral :
+     If mask address not set (0) => BWM must be set to 0
+     If mask address set (different than 0) => BWM could be set to 1 or 0
+  */
+  if((pNodeConfig->Init.Request == MDMA_REQUEST_SW) || (pNodeConfig->PostRequestMaskAddress != 0U))
+  {
+    pNode->CTCR |=  MDMA_CTCR_BWM;
+  }
+
+  /* Set the new CBNDTR Register value */
+  pNode->CBNDTR = ((pNodeConfig->BlockCount - 1U) << MDMA_CBNDTR_BRC_Pos) & MDMA_CBNDTR_BRC;
+
+  /* if block source address offset is negative set the Block Repeat Source address Update Mode to decrement */
+  if(pNodeConfig->Init.SourceBlockAddressOffset < 0)
+  {
+    pNode->CBNDTR |= MDMA_CBNDTR_BRSUM;
+    /*write new CBRUR Register value : source repeat block offset */
+    blockoffset = (uint32_t)(- pNodeConfig->Init.SourceBlockAddressOffset);
+    pNode->CBRUR = blockoffset & 0x0000FFFFU;
+  }
+  else
+  {
+    /*write new CBRUR Register value : source repeat block offset */
+    pNode->CBRUR = (((uint32_t) pNodeConfig->Init.SourceBlockAddressOffset) & 0x0000FFFFU);
+  }
+
+  /* if block destination address offset is negative set the Block Repeat destination address Update Mode to decrement */
+  if(pNodeConfig->Init.DestBlockAddressOffset < 0)
+  {
+    pNode->CBNDTR |= MDMA_CBNDTR_BRDUM;
+    /*write new CBRUR Register value : destination repeat block offset */
+    blockoffset = (uint32_t)(- pNodeConfig->Init.DestBlockAddressOffset);
+    pNode->CBRUR |= ((blockoffset & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos);
+  }
+  else
+  {
+    /*write new CBRUR Register value : destination repeat block offset */
+    pNode->CBRUR |= ((((uint32_t)pNodeConfig->Init.DestBlockAddressOffset) & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos);
+  }
+
+  /* Configure MDMA Link Node data length */
+  pNode->CBNDTR |=  pNodeConfig->BlockDataLength;
+
+  /* Configure MDMA Link Node destination address */
+  pNode->CDAR = pNodeConfig->DstAddress;
+
+  /* Configure MDMA Link Node Source address */
+  pNode->CSAR = pNodeConfig->SrcAddress;
+
+  /* if HW request set the HW request and the requet CleraMask and ClearData MaskData,  */
+  if(pNodeConfig->Init.Request != MDMA_REQUEST_SW)
+  {
+    /* Set the HW request in CTBR register  */
+    pNode->CTBR = pNodeConfig->Init.Request & MDMA_CTBR_TSEL;
+    /* Set the HW request clear Mask and Data */
+    pNode->CMAR = pNodeConfig->PostRequestMaskAddress;
+    pNode->CMDR = pNodeConfig->PostRequestMaskData;
+  }
+
+  addressMask = pNodeConfig->SrcAddress & 0xFF000000U;
+  if((addressMask == 0x20000000U) || (addressMask == 0x00000000U))
+  {
+    /*The AHBSbus is used as source (read operation) on channel x */
+    pNode->CTBR |= MDMA_CTBR_SBUS;
+  }
+
+  addressMask = pNodeConfig->DstAddress & 0xFF000000U;
+  if((addressMask == 0x20000000U) || (addressMask == 0x00000000U))
+  {
+    /*The AHB bus is used as destination (write operation) on channel x */
+    pNode->CTBR |= MDMA_CTBR_DBUS;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Connect a node to the linked list.
+  * @param  hmdma    : Pointer to a MDMA_HandleTypeDef structure that contains
+  *                    the configuration information for the specified MDMA Channel.
+  * @param  pNewNode : Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node
+  *                    to be add to the list.
+  * @param pPrevNode : Pointer to the new node position in the linked list or zero to insert the new node
+  *                    at the end of the list
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, MDMA_LinkNodeTypeDef *pPrevNode)
+{
+  MDMA_LinkNodeTypeDef *pNode;
+  uint32_t counter = 0, nodeInserted = 0;
+  HAL_StatusTypeDef hal_status = HAL_OK;
+
+  /* Check the MDMA peripheral handle */
+  if((hmdma == NULL) || (pNewNode == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hmdma);
+
+  if(HAL_MDMA_STATE_READY == hmdma->State)
+  {
+    /* Change MDMA peripheral state */
+    hmdma->State = HAL_MDMA_STATE_BUSY;
+
+    /* Check if this is the first node (after the Inititlization node) */
+    if((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U)
+    {
+      if(pPrevNode == NULL)
+      {
+        /* if this is the first node after the initialization
+        connect this node to the node 0 by updating
+        the MDMA channel CLAR register to this node address */
+        hmdma->Instance->CLAR = (uint32_t)pNewNode;
+        /* Set the MDMA handle First linked List node*/
+        hmdma->FirstLinkedListNodeAddress = pNewNode;
+
+        /*reset New node link */
+        pNewNode->CLAR = 0;
+
+        /* Update the Handle last node address */
+        hmdma->LastLinkedListNodeAddress = pNewNode;
+
+        hmdma->LinkedListNodeCounter = 1;
+      }
+      else
+      {
+        hal_status = HAL_ERROR;
+      }
+    }
+    else if(hmdma->FirstLinkedListNodeAddress != pNewNode)
+    {
+      /* Check if the node to insert already exists*/
+      pNode = hmdma->FirstLinkedListNodeAddress;
+      while((counter < hmdma->LinkedListNodeCounter) && (hal_status == HAL_OK))
+      {
+        if(pNode->CLAR == (uint32_t)pNewNode)
+        {
+          hal_status = HAL_ERROR; /* error this node already exist in the linked list and it is not first node */
+        }
+        pNode = (MDMA_LinkNodeTypeDef *)pNode->CLAR;
+        counter++;
+      }
+
+      if(hal_status == HAL_OK)
+      {
+        /* Check if the previous node is the last one in the current list or zero */
+        if((pPrevNode == hmdma->LastLinkedListNodeAddress) || (pPrevNode == NULL))
+        {
+          /* insert the new node at the end of the list */
+          pNewNode->CLAR = hmdma->LastLinkedListNodeAddress->CLAR;
+          hmdma->LastLinkedListNodeAddress->CLAR = (uint32_t)pNewNode;
+          /* Update the Handle last node address */
+          hmdma->LastLinkedListNodeAddress = pNewNode;
+          /* Increment the linked list node counter */
+          hmdma->LinkedListNodeCounter++;
+        }
+        else
+        {
+          /*insert the new node after the pPreviousNode node */
+          pNode = hmdma->FirstLinkedListNodeAddress;
+          counter = 0;
+          while((counter < hmdma->LinkedListNodeCounter) && (nodeInserted == 0U))
+          {
+            counter++;
+            if(pNode == pPrevNode)
+            {
+              /*Insert the new node after the previous one */
+              pNewNode->CLAR = pNode->CLAR;
+              pNode->CLAR = (uint32_t)pNewNode;
+              /* Increment the linked list node counter */
+              hmdma->LinkedListNodeCounter++;
+              nodeInserted = 1;
+            }
+            else
+            {
+              pNode = (MDMA_LinkNodeTypeDef *)pNode->CLAR;
+            }
+          }
+
+          if(nodeInserted == 0U)
+          {
+            hal_status = HAL_ERROR;
+          }
+        }
+      }
+    }
+    else
+    {
+      hal_status = HAL_ERROR;
+    }
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hmdma);
+
+    hmdma->State = HAL_MDMA_STATE_READY;
+
+    return hal_status;
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hmdma);
+
+    /* Return error status */
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Disconnect/Remove a node from the transfer linked list.
+  * @param  hmdma : Pointer to a MDMA_HandleTypeDef structure that contains
+  *                 the configuration information for the specified MDMA Channel.
+  * @param  pNode : Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node
+  *                 to be removed from the list.
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNode)
+{
+  MDMA_LinkNodeTypeDef *ptmpNode;
+  uint32_t counter = 0, nodeDeleted = 0;
+  HAL_StatusTypeDef hal_status = HAL_OK;
+
+  /* Check the MDMA peripheral handle */
+  if((hmdma == NULL) || (pNode == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hmdma);
+
+  if(HAL_MDMA_STATE_READY == hmdma->State)
+  {
+    /* Change MDMA peripheral state */
+    hmdma->State = HAL_MDMA_STATE_BUSY;
+
+    /* If first and last node are null (no nodes in the list) : return error*/
+    if(((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U) || ((uint32_t)hmdma->LastLinkedListNodeAddress == 0U) || (hmdma->LinkedListNodeCounter == 0U))
+    {
+      hal_status = HAL_ERROR;
+    }
+    else if(hmdma->FirstLinkedListNodeAddress == pNode) /* Deleting first node */
+    {
+      /* Delete 1st node */
+      if(hmdma->LastLinkedListNodeAddress == pNode)
+      {
+        /*if the last node is at the same time the first one (1 single node after the init node 0)
+        then update the last node too */
+
+        hmdma->FirstLinkedListNodeAddress = 0;
+        hmdma->LastLinkedListNodeAddress  = 0;
+        hmdma->LinkedListNodeCounter = 0;
+
+        hmdma->Instance->CLAR = 0;
+      }
+      else
+      {
+        if((uint32_t)hmdma->FirstLinkedListNodeAddress == hmdma->LastLinkedListNodeAddress->CLAR)
+        {
+          /* if last node is looping to first (circular list) one update the last node connection */
+          hmdma->LastLinkedListNodeAddress->CLAR = pNode->CLAR;
+        }
+
+        /* if deleting the first node after the initialization
+        connect the next node to the node 0 by updating
+        the MDMA channel CLAR register to this node address */
+        hmdma->Instance->CLAR = pNode->CLAR;
+        hmdma->FirstLinkedListNodeAddress = (MDMA_LinkNodeTypeDef *)hmdma->Instance->CLAR;
+        /* Update the Handle node counter */
+        hmdma->LinkedListNodeCounter--;
+      }
+    }
+    else /* Deleting any other node */
+    {
+      /*Deleted node is not the first one : find it  */
+      ptmpNode = hmdma->FirstLinkedListNodeAddress;
+      while((counter < hmdma->LinkedListNodeCounter) && (nodeDeleted == 0U))
+      {
+        counter++;
+        if(ptmpNode->CLAR == ((uint32_t)pNode))
+        {
+          /* if deleting the last node */
+          if(pNode == hmdma->LastLinkedListNodeAddress)
+          {
+            /*Update the linked list last node address in the handle*/
+            hmdma->LastLinkedListNodeAddress = ptmpNode;
+          }
+          /* update the next node link after deleting pMDMA_LinkedListNode */
+          ptmpNode->CLAR = pNode->CLAR;
+          nodeDeleted = 1;
+          /* Update the Handle node counter */
+          hmdma->LinkedListNodeCounter--;
+        }
+        else
+        {
+          ptmpNode = (MDMA_LinkNodeTypeDef *)ptmpNode->CLAR;
+        }
+      }
+
+      if(nodeDeleted == 0U)
+      {
+        /* last node reashed without finding the node to delete : return error */
+        hal_status = HAL_ERROR;
+      }
+    }
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hmdma);
+
+    hmdma->State = HAL_MDMA_STATE_READY;
+
+    return hal_status;
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hmdma);
+
+    /* Return error status */
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Make the linked list circular by connecting the last node to the first.
+  * @param  hmdma : Pointer to a MDMA_HandleTypeDef structure that contains
+  *                 the configuration information for the specified MDMA Channel.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_LinkedList_EnableCircularMode(MDMA_HandleTypeDef *hmdma)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hmdma);
+
+  if(HAL_MDMA_STATE_READY == hmdma->State)
+  {
+    /* Change MDMA peripheral state */
+    hmdma->State = HAL_MDMA_STATE_BUSY;
+
+    /* If first and last node are null (no nodes in the list) : return error*/
+    if(((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U) || ((uint32_t)hmdma->LastLinkedListNodeAddress == 0U) || (hmdma->LinkedListNodeCounter == 0U))
+    {
+      hal_status = HAL_ERROR;
+    }
+    else
+    {
+      /* to enable circular mode Last Node should be connected to first node */
+      hmdma->LastLinkedListNodeAddress->CLAR = (uint32_t)hmdma->FirstLinkedListNodeAddress;
+    }
+
+  }
+  /* Process unlocked */
+  __HAL_UNLOCK(hmdma);
+
+  hmdma->State = HAL_MDMA_STATE_READY;
+
+  return hal_status;
+}
+
+/**
+  * @brief  Disable the linked list circular mode by setting the last node connection to null
+  * @param  hmdma : Pointer to a MDMA_HandleTypeDef structure that contains
+  *                 the configuration information for the specified MDMA Channel.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_LinkedList_DisableCircularMode(MDMA_HandleTypeDef *hmdma)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hmdma);
+
+  if(HAL_MDMA_STATE_READY == hmdma->State)
+  {
+    /* Change MDMA peripheral state */
+    hmdma->State = HAL_MDMA_STATE_BUSY;
+
+    /* If first and last node are null (no nodes in the list) : return error*/
+    if(((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U) || ((uint32_t)hmdma->LastLinkedListNodeAddress == 0U) || (hmdma->LinkedListNodeCounter == 0U))
+    {
+      hal_status = HAL_ERROR;
+    }
+    else
+    {
+      /* to disable circular mode Last Node should be connected to NULL */
+      hmdma->LastLinkedListNodeAddress->CLAR = 0;
+    }
+
+  }
+  /* Process unlocked */
+  __HAL_UNLOCK(hmdma);
+
+  hmdma->State = HAL_MDMA_STATE_READY;
+
+  return hal_status;
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup MDMA_Exported_Functions_Group3
+ *
+@verbatim
+ ===============================================================================
+                      #####  IO operation functions  #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure the source, destination address and data length and Start MDMA transfer
+      (+) Configure the source, destination address and data length and
+          Start MDMA transfer with interrupt
+      (+) Abort MDMA transfer
+      (+) Poll for transfer complete
+      (+) Generate a SW request (when Request is set to MDMA_REQUEST_SW)
+      (+) Handle MDMA interrupt request
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the MDMA Transfer.
+  * @param  hmdma           : pointer to a MDMA_HandleTypeDef structure that contains
+  *                           the configuration information for the specified MDMA Channel.
+  * @param  SrcAddress      : The source memory Buffer address
+  * @param  DstAddress      : The destination memory Buffer address
+  * @param  BlockDataLength : The length of a block transfer in bytes
+  * @param  BlockCount      : The number of a blocks to be transfer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_Start(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
+{
+  /* Check the parameters */
+  assert_param(IS_MDMA_TRANSFER_LENGTH(BlockDataLength));
+  assert_param(IS_MDMA_BLOCK_COUNT(BlockCount));
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hmdma);
+
+  if(HAL_MDMA_STATE_READY == hmdma->State)
+  {
+    /* Change MDMA peripheral state */
+    hmdma->State = HAL_MDMA_STATE_BUSY;
+
+    /* Initialize the error code */
+    hmdma->ErrorCode = HAL_MDMA_ERROR_NONE;
+
+    /* Disable the peripheral */
+    __HAL_MDMA_DISABLE(hmdma);
+
+    /* Configure the source, destination address and the data length */
+    MDMA_SetConfig(hmdma, SrcAddress, DstAddress, BlockDataLength, BlockCount);
+
+    /* Enable the Peripheral */
+    __HAL_MDMA_ENABLE(hmdma);
+
+    if(hmdma->Init.Request == MDMA_REQUEST_SW)
+    {
+      /* activate If SW request mode*/
+      hmdma->Instance->CCR |=  MDMA_CCR_SWRQ;
+    }
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hmdma);
+
+    /* Return error status */
+    return HAL_BUSY;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the MDMA Transfer with interrupts enabled.
+  * @param  hmdma           : pointer to a MDMA_HandleTypeDef structure that contains
+  *                           the configuration information for the specified MDMA Channel.
+  * @param  SrcAddress      : The source memory Buffer address
+  * @param  DstAddress      : The destination memory Buffer address
+  * @param  BlockDataLength : The length of a block transfer in bytes
+  * @param  BlockCount      : The number of a blocks to be transfer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_Start_IT(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
+{
+  /* Check the parameters */
+  assert_param(IS_MDMA_TRANSFER_LENGTH(BlockDataLength));
+  assert_param(IS_MDMA_BLOCK_COUNT(BlockCount));
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hmdma);
+
+  if(HAL_MDMA_STATE_READY == hmdma->State)
+  {
+    /* Change MDMA peripheral state */
+    hmdma->State = HAL_MDMA_STATE_BUSY;
+
+    /* Initialize the error code */
+    hmdma->ErrorCode = HAL_MDMA_ERROR_NONE;
+
+    /* Disable the peripheral */
+    __HAL_MDMA_DISABLE(hmdma);
+
+    /* Configure the source, destination address and the data length */
+    MDMA_SetConfig(hmdma, SrcAddress, DstAddress, BlockDataLength, BlockCount);
+
+    /* Enable Common interrupts i.e Transfer Error IT and Channel Transfer Complete IT*/
+    __HAL_MDMA_ENABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC));
+
+    if(hmdma->XferBlockCpltCallback != NULL)
+    {
+      /* if Block transfer complete Callback is set enable the corresponding IT*/
+      __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BT);
+    }
+
+    if(hmdma->XferRepeatBlockCpltCallback != NULL)
+    {
+      /* if Repeated Block transfer complete Callback is set enable the corresponding IT*/
+      __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BRT);
+    }
+
+    if(hmdma->XferBufferCpltCallback != NULL)
+    {
+      /* if buffer transfer complete Callback is set enable the corresponding IT*/
+      __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BFTC);
+    }
+
+    /* Enable the Peripheral */
+    __HAL_MDMA_ENABLE(hmdma);
+
+    if(hmdma->Init.Request == MDMA_REQUEST_SW)
+    {
+      /* activate If SW request mode*/
+      hmdma->Instance->CCR |=  MDMA_CCR_SWRQ;
+    }
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hmdma);
+
+    /* Return error status */
+    return HAL_BUSY;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Aborts the MDMA Transfer.
+  * @param  hmdma  : pointer to a MDMA_HandleTypeDef structure that contains
+  *                 the configuration information for the specified MDMA Channel.
+  *
+  * @note  After disabling a MDMA Channel, a check for wait until the MDMA Channel is
+  *        effectively disabled is added. If a Channel is disabled
+  *        while a data transfer is ongoing, the current data will be transferred
+  *        and the Channel will be effectively disabled only after the transfer of
+  *        this single data is finished.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_Abort(MDMA_HandleTypeDef *hmdma)
+{
+  uint32_t tickstart =  HAL_GetTick();
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if(HAL_MDMA_STATE_BUSY != hmdma->State)
+  {
+    hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hmdma);
+
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Disable all the transfer interrupts */
+    __HAL_MDMA_DISABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC | MDMA_IT_BT | MDMA_IT_BRT | MDMA_IT_BFTC));
+
+    /* Disable the channel */
+    __HAL_MDMA_DISABLE(hmdma);
+
+    /* Check if the MDMA Channel is effectively disabled */
+    while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U)
+    {
+      /* Check for the Timeout */
+      if( (HAL_GetTick()  - tickstart ) > HAL_TIMEOUT_MDMA_ABORT)
+      {
+        /* Update error code */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_TIMEOUT;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hmdma);
+
+        /* Change the MDMA state */
+        hmdma->State = HAL_MDMA_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+    }
+
+    /* Clear all interrupt flags */
+    __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_FLAG_BT | MDMA_FLAG_BRT | MDMA_FLAG_BFTC));
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hmdma);
+
+    /* Change the MDMA state*/
+    hmdma->State = HAL_MDMA_STATE_READY;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Aborts the MDMA Transfer in Interrupt mode.
+  * @param  hmdma  : pointer to a MDMA_HandleTypeDef structure that contains
+  *                 the configuration information for the specified MDMA Channel.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_Abort_IT(MDMA_HandleTypeDef *hmdma)
+{
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if(HAL_MDMA_STATE_BUSY != hmdma->State)
+  {
+    /* No transfer ongoing */
+    hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER;
+
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Set Abort State  */
+    hmdma->State = HAL_MDMA_STATE_ABORT;
+
+    /* Disable the stream */
+    __HAL_MDMA_DISABLE(hmdma);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Polling for transfer complete.
+  * @param  hmdma:          pointer to a MDMA_HandleTypeDef structure that contains
+  *                        the configuration information for the specified MDMA Channel.
+  * @param  CompleteLevel: Specifies the MDMA level complete.
+  * @param  Timeout:       Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_PollForTransfer(MDMA_HandleTypeDef *hmdma, HAL_MDMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
+{
+  uint32_t levelFlag, errorFlag;
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param(IS_MDMA_LEVEL_COMPLETE(CompleteLevel));
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if(HAL_MDMA_STATE_BUSY != hmdma->State)
+  {
+    /* No transfer ongoing */
+    hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER;
+
+    return HAL_ERROR;
+  }
+
+  /* Get the level transfer complete flag */
+  levelFlag = ((CompleteLevel == HAL_MDMA_FULL_TRANSFER)  ? MDMA_FLAG_CTC  : \
+               (CompleteLevel == HAL_MDMA_BUFFER_TRANSFER)? MDMA_FLAG_BFTC : \
+               (CompleteLevel == HAL_MDMA_BLOCK_TRANSFER) ? MDMA_FLAG_BT   : \
+               MDMA_FLAG_BRT);
+
+
+  /* Get timeout */
+  tickstart = HAL_GetTick();
+
+  while(__HAL_MDMA_GET_FLAG(hmdma, levelFlag) == 0U)
+  {
+    if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_TE) != 0U))
+    {
+      /* Get the transfer error source flag */
+      errorFlag = hmdma->Instance->CESR;
+
+      if((errorFlag & MDMA_CESR_TED) == 0U)
+      {
+        /* Update error code : Read Transfer error  */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_READ_XFER;
+      }
+      else
+      {
+        /* Update error code : Write Transfer error */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_WRITE_XFER;
+      }
+
+      if((errorFlag & MDMA_CESR_TEMD) != 0U)
+      {
+        /* Update error code : Error Mask Data */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_MASK_DATA;
+      }
+
+      if((errorFlag & MDMA_CESR_TELD) != 0U)
+      {
+        /* Update error code : Error Linked list */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_LINKED_LIST;
+      }
+
+      if((errorFlag & MDMA_CESR_ASE) != 0U)
+      {
+        /* Update error code : Address/Size alignment error */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_ALIGNMENT;
+      }
+
+      if((errorFlag & MDMA_CESR_BSE) != 0U)
+      {
+        /* Update error code : Block Size error */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_BLOCK_SIZE;
+      }
+
+      (void) HAL_MDMA_Abort(hmdma); /* if error then abort the current transfer */
+
+      /*
+        Note that the Abort function will
+          - Clear all transfer flags
+          - Unlock
+          - Set the State
+      */
+
+      return HAL_ERROR;
+
+    }
+
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(((HAL_GetTick() - tickstart ) > Timeout) || (Timeout == 0U))
+      {
+        /* Update error code */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_TIMEOUT;
+
+        (void) HAL_MDMA_Abort(hmdma); /* if timeout then abort the current transfer */
+
+        /*
+          Note that the Abort function will
+            - Clear all transfer flags
+            - Unlock
+            - Set the State
+        */
+
+        return HAL_ERROR;
+      }
+    }
+  }
+
+  /* Clear the transfer level flag */
+  if(CompleteLevel == HAL_MDMA_BUFFER_TRANSFER)
+  {
+    __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BFTC);
+
+  }
+  else if(CompleteLevel == HAL_MDMA_BLOCK_TRANSFER)
+  {
+    __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BFTC | MDMA_FLAG_BT));
+
+  }
+  else if(CompleteLevel == HAL_MDMA_REPEAT_BLOCK_TRANSFER)
+  {
+    __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BFTC | MDMA_FLAG_BT | MDMA_FLAG_BRT));
+  }
+  else if(CompleteLevel == HAL_MDMA_FULL_TRANSFER)
+  {
+    __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BRT | MDMA_FLAG_BT | MDMA_FLAG_BFTC | MDMA_FLAG_CTC));
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hmdma);
+
+    hmdma->State = HAL_MDMA_STATE_READY;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Generate an MDMA SW request trigger to activate the request on the given Channel.
+  * @param  hmdma:       pointer to a MDMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified MDMA Stream.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_GenerateSWRequest(MDMA_HandleTypeDef *hmdma)
+{
+  uint32_t request_mode;
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Get the softawre request mode */
+  request_mode = hmdma->Instance->CTCR & MDMA_CTCR_SWRM;
+
+  if((hmdma->Instance->CCR &  MDMA_CCR_EN) == 0U)
+  {
+    /* if no Transfer on going (MDMA enable bit not set) retrun error */
+    hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER;
+
+    return HAL_ERROR;
+  }
+  else if(((hmdma->Instance->CISR &  MDMA_CISR_CRQA) != 0U) || (request_mode == 0U))
+  {
+    /* if an MDMA ongoing request has not yet end or if request mode is not SW request retrun error */
+    hmdma->ErrorCode = HAL_MDMA_ERROR_BUSY;
+
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Set the SW request bit to activate the request on the Channel */
+    hmdma->Instance->CCR |= MDMA_CCR_SWRQ;
+
+    return HAL_OK;
+  }
+}
+
+/**
+  * @brief  Handles MDMA interrupt request.
+  * @param  hmdma: pointer to a MDMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified MDMA Channel.
+  * @retval None
+  */
+void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma)
+{
+  __IO uint32_t count = 0;
+  uint32_t timeout = SystemCoreClock / 9600U;
+
+  uint32_t generalIntFlag, errorFlag;
+
+  /* General Interrupt Flag management ****************************************/
+  generalIntFlag =  1UL << ((((uint32_t)hmdma->Instance - (uint32_t)(MDMA_Channel0))/HAL_MDMA_CHANNEL_SIZE) & 0x1FU);
+  if((MDMA->GISR0 & generalIntFlag) == 0U)
+  {
+    return; /* the  General interrupt flag for the current channel is down , nothing to do */
+  }
+
+  /* Transfer Error Interrupt management ***************************************/
+  if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_TE) != 0U))
+  {
+    if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_TE) != 0U)
+    {
+      /* Disable the transfer error interrupt */
+      __HAL_MDMA_DISABLE_IT(hmdma, MDMA_IT_TE);
+
+      /* Get the transfer error source flag */
+      errorFlag = hmdma->Instance->CESR;
+
+      if((errorFlag & MDMA_CESR_TED) == 0U)
+      {
+        /* Update error code : Read Transfer error  */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_READ_XFER;
+      }
+      else
+      {
+        /* Update error code : Write Transfer error */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_WRITE_XFER;
+      }
+
+      if((errorFlag & MDMA_CESR_TEMD) != 0U)
+      {
+        /* Update error code : Error Mask Data */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_MASK_DATA;
+      }
+
+      if((errorFlag & MDMA_CESR_TELD) != 0U)
+      {
+        /* Update error code : Error Linked list */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_LINKED_LIST;
+      }
+
+      if((errorFlag & MDMA_CESR_ASE) != 0U)
+      {
+        /* Update error code : Address/Size alignment error */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_ALIGNMENT;
+      }
+
+      if((errorFlag & MDMA_CESR_BSE) != 0U)
+      {
+        /* Update error code : Block Size error error */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_BLOCK_SIZE;
+      }
+
+      /* Clear the transfer error flags */
+      __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_TE);
+    }
+  }
+
+  /* Buffer Transfer Complete Interrupt management ******************************/
+  if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BFTC) != 0U))
+  {
+    if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BFTC) != 0U)
+    {
+      /* Clear the buffer transfer complete flag */
+      __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BFTC);
+
+      if(hmdma->XferBufferCpltCallback != NULL)
+      {
+        /* Buffer transfer callback */
+        hmdma->XferBufferCpltCallback(hmdma);
+      }
+    }
+  }
+
+  /* Block Transfer Complete Interrupt management ******************************/
+  if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BT) != 0U))
+  {
+    if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BT) != 0U)
+    {
+      /* Clear the block transfer complete flag */
+      __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BT);
+
+      if(hmdma->XferBlockCpltCallback != NULL)
+      {
+        /* Block transfer callback */
+        hmdma->XferBlockCpltCallback(hmdma);
+      }
+    }
+  }
+
+  /* Repeated Block Transfer Complete Interrupt management ******************************/
+  if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BRT) != 0U))
+  {
+    if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BRT) != 0U)
+    {
+      /* Clear the repeat block transfer complete flag */
+      __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BRT);
+
+      if(hmdma->XferRepeatBlockCpltCallback != NULL)
+      {
+        /* Repeated Block transfer callback */
+        hmdma->XferRepeatBlockCpltCallback(hmdma);
+      }
+    }
+  }
+
+  /* Channel Transfer Complete Interrupt management ***********************************/
+  if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_CTC) != 0U))
+  {
+    if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_CTC) != 0U)
+    {
+      /* Disable all the transfer interrupts */
+      __HAL_MDMA_DISABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC | MDMA_IT_BT | MDMA_IT_BRT | MDMA_IT_BFTC));
+
+      if(HAL_MDMA_STATE_ABORT == hmdma->State)
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hmdma);
+
+        /* Change the DMA state */
+        hmdma->State = HAL_MDMA_STATE_READY;
+
+        if(hmdma->XferAbortCallback != NULL)
+        {
+          hmdma->XferAbortCallback(hmdma);
+        }
+        return;
+      }
+
+      /* Clear the Channel Transfer Complete flag */
+      __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_CTC);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hmdma);
+
+      /* Change MDMA peripheral state */
+      hmdma->State = HAL_MDMA_STATE_READY;
+
+      if(hmdma->XferCpltCallback != NULL)
+      {
+        /* Channel Transfer Complete callback */
+        hmdma->XferCpltCallback(hmdma);
+      }
+    }
+  }
+
+  /* manage error case */
+  if(hmdma->ErrorCode != HAL_MDMA_ERROR_NONE)
+  {
+    hmdma->State = HAL_MDMA_STATE_ABORT;
+
+    /* Disable the channel */
+    __HAL_MDMA_DISABLE(hmdma);
+
+    do
+    {
+      if (++count > timeout)
+      {
+        break;
+      }
+    }
+    while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hmdma);
+
+    if((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U)
+    {
+      /* Change the MDMA state to error if MDMA disable fails */
+      hmdma->State = HAL_MDMA_STATE_ERROR;
+    }
+    else
+    {
+      /* Change the MDMA state to Ready if MDMA disable success */
+      hmdma->State = HAL_MDMA_STATE_READY;
+    }
+
+
+    if (hmdma->XferErrorCallback != NULL)
+    {
+      /* Transfer error callback */
+      hmdma->XferErrorCallback(hmdma);
+    }
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup MDMA_Exported_Functions_Group4
+ *
+@verbatim
+ ===============================================================================
+                    ##### State and Errors functions #####
+ ===============================================================================
+    [..]
+    This subsection provides functions allowing to
+      (+) Check the MDMA state
+      (+) Get error code
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the MDMA state.
+  * @param  hmdma: pointer to a MDMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified MDMA Channel.
+  * @retval HAL state
+  */
+HAL_MDMA_StateTypeDef HAL_MDMA_GetState(MDMA_HandleTypeDef *hmdma)
+{
+  return hmdma->State;
+}
+
+/**
+  * @brief  Return the MDMA error code
+  * @param  hmdma : pointer to a MDMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified MDMA Channel.
+  * @retval MDMA Error Code
+  */
+uint32_t HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma)
+{
+  return hmdma->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup MDMA_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Sets the MDMA Transfer parameter.
+  * @param  hmdma:       pointer to a MDMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified MDMA Channel.
+  * @param  SrcAddress: The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  BlockDataLength : The length of a block transfer in bytes
+  * @param  BlockCount: The number of blocks to be transfered
+  * @retval HAL status
+  */
+static void MDMA_SetConfig(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
+{
+  uint32_t addressMask;
+
+  /* Configure the MDMA Channel data length */
+  MODIFY_REG(hmdma->Instance->CBNDTR ,MDMA_CBNDTR_BNDT, (BlockDataLength & MDMA_CBNDTR_BNDT));
+
+  /* Configure the MDMA block repeat count */
+  MODIFY_REG(hmdma->Instance->CBNDTR , MDMA_CBNDTR_BRC , ((BlockCount - 1U) << MDMA_CBNDTR_BRC_Pos) & MDMA_CBNDTR_BRC);
+
+  /* Clear all interrupt flags */
+  __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_CISR_BRTIF | MDMA_CISR_BTIF | MDMA_CISR_TCIF);
+
+  /* Configure MDMA Channel destination address */
+  hmdma->Instance->CDAR = DstAddress;
+
+  /* Configure MDMA Channel Source address */
+  hmdma->Instance->CSAR = SrcAddress;
+
+  addressMask = SrcAddress & 0xFF000000U;
+  if((addressMask == 0x20000000U) || (addressMask == 0x00000000U))
+  {
+    /*The AHBSbus is used as source (read operation) on channel x */
+    hmdma->Instance->CTBR |= MDMA_CTBR_SBUS;
+  }
+  else
+  {
+    /*The AXI bus is used as source (read operation) on channel x */
+    hmdma->Instance->CTBR &= (~MDMA_CTBR_SBUS);
+  }
+
+  addressMask = DstAddress & 0xFF000000U;
+  if((addressMask == 0x20000000U) || (addressMask == 0x00000000U))
+  {
+    /*The AHB bus is used as destination (write operation) on channel x */
+    hmdma->Instance->CTBR |= MDMA_CTBR_DBUS;
+  }
+  else
+  {
+    /*The AXI bus is used as destination (write operation) on channel x */
+    hmdma->Instance->CTBR &= (~MDMA_CTBR_DBUS);
+  }
+
+  /* Set the linked list register to the first node of the list */
+  hmdma->Instance->CLAR = (uint32_t)hmdma->FirstLinkedListNodeAddress;
+}
+
+/**
+  * @brief  Initializes the MDMA handle according to the specified
+  *         parameters in the MDMA_InitTypeDef
+  * @param  hmdma:       pointer to a MDMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified MDMA Channel.
+  * @retval None
+  */
+static void MDMA_Init(MDMA_HandleTypeDef *hmdma)
+{
+  uint32_t blockoffset;
+
+  /* Prepare the MDMA Channel configuration */
+  hmdma->Instance->CCR = hmdma->Init.Priority  | hmdma->Init.Endianness;
+
+  /* Write new CTCR Register value */
+  hmdma->Instance->CTCR =  hmdma->Init.SourceInc      | hmdma->Init.DestinationInc | \
+                           hmdma->Init.SourceDataSize | hmdma->Init.DestDataSize   | \
+                           hmdma->Init.DataAlignment  | hmdma->Init.SourceBurst    | \
+                           hmdma->Init.DestBurst                                   | \
+                           ((hmdma->Init.BufferTransferLength - 1U) << MDMA_CTCR_TLEN_Pos) | \
+                           hmdma->Init.TransferTriggerMode;
+
+  /* If SW request set the CTCR register to SW Request Mode */
+  if(hmdma->Init.Request == MDMA_REQUEST_SW)
+  {
+    /*
+    -If the request is done by SW : BWM could be set to 1 or 0.
+    -If the request is done by a peripheral :
+    If mask address not set (0) => BWM must be set to 0
+    If mask address set (different than 0) => BWM could be set to 1 or 0
+    */
+    hmdma->Instance->CTCR |= (MDMA_CTCR_SWRM | MDMA_CTCR_BWM);
+  }
+
+  /* Reset CBNDTR Register */
+  hmdma->Instance->CBNDTR = 0;
+
+  /* if block source address offset is negative set the Block Repeat Source address Update Mode to decrement */
+  if(hmdma->Init.SourceBlockAddressOffset < 0)
+  {
+    hmdma->Instance->CBNDTR |= MDMA_CBNDTR_BRSUM;
+    /* Write new CBRUR Register value : source repeat block offset */
+    blockoffset = (uint32_t)(- hmdma->Init.SourceBlockAddressOffset);
+    hmdma->Instance->CBRUR = (blockoffset & 0x0000FFFFU);
+  }
+  else
+  {
+    /* Write new CBRUR Register value : source repeat block offset */
+    hmdma->Instance->CBRUR = (((uint32_t)hmdma->Init.SourceBlockAddressOffset) & 0x0000FFFFU);
+  }
+
+  /* If block destination address offset is negative set the Block Repeat destination address Update Mode to decrement */
+  if(hmdma->Init.DestBlockAddressOffset < 0)
+  {
+    hmdma->Instance->CBNDTR |= MDMA_CBNDTR_BRDUM;
+    /* Write new CBRUR Register value : destination repeat block offset */
+    blockoffset = (uint32_t)(- hmdma->Init.DestBlockAddressOffset);
+    hmdma->Instance->CBRUR |= ((blockoffset & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos);
+  }
+  else
+  {
+    /*write new CBRUR Register value : destination repeat block offset */
+    hmdma->Instance->CBRUR |= ((((uint32_t)hmdma->Init.DestBlockAddressOffset) & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos);
+  }
+
+  /* if HW request set the HW request and the requet CleraMask and ClearData MaskData, */
+  if(hmdma->Init.Request != MDMA_REQUEST_SW)
+  {
+    /* Set the HW request in CTRB register  */
+    hmdma->Instance->CTBR = hmdma->Init.Request & MDMA_CTBR_TSEL;
+  }
+  else /* SW request : reset the CTBR register */
+  {
+    hmdma->Instance->CTBR = 0;
+  }
+
+  /* Write Link Address Register */
+  hmdma->Instance->CLAR =  0;
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_MDMA_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c
new file mode 100644
index 00000000..3a847e87
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c
@@ -0,0 +1,2201 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_pcd.c
+  * @author  MCD Application Team
+  * @brief   PCD HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the USB Peripheral Controller:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State functions
+  *
+  @verbatim
+  ==============================================================================
+                    ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      The PCD HAL driver can be used as follows:
+
+     (#) Declare a PCD_HandleTypeDef handle structure, for example:
+         PCD_HandleTypeDef  hpcd;
+
+     (#) Fill parameters of Init structure in HCD handle
+
+     (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...)
+
+     (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
+         (##) Enable the PCD/USB Low Level interface clock using
+              (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
+              (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode)
+
+         (##) Initialize the related GPIO clocks
+         (##) Configure PCD pin-out
+         (##) Configure PCD NVIC interrupt
+
+     (#)Associate the Upper USB device stack to the HAL PCD Driver:
+         (##) hpcd.pData = pdev;
+
+     (#)Enable PCD transmission and reception:
+         (##) HAL_PCD_Start();
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup PCD PCD
+  * @brief PCD HAL module driver
+  * @{
+  */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PCD_Private_Macros PCD Private Macros
+  * @{
+  */
+#define PCD_MIN(a, b)  (((a) < (b)) ? (a) : (b))
+#define PCD_MAX(a, b)  (((a) > (b)) ? (a) : (b))
+/**
+  * @}
+  */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup PCD_Private_Functions PCD Private Functions
+  * @{
+  */
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum);
+static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum);
+static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum);
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup PCD_Exported_Functions PCD Exported Functions
+  * @{
+  */
+
+/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+            ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the PCD according to the specified
+  *         parameters in the PCD_InitTypeDef and initialize the associated handle.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
+{
+  USB_OTG_GlobalTypeDef *USBx;
+  uint8_t i;
+
+  /* Check the PCD handle allocation */
+  if (hpcd == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
+
+  USBx = hpcd->Instance;
+
+  if (hpcd->State == HAL_PCD_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hpcd->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+    hpcd->SOFCallback = HAL_PCD_SOFCallback;
+    hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;
+    hpcd->ResetCallback = HAL_PCD_ResetCallback;
+    hpcd->SuspendCallback = HAL_PCD_SuspendCallback;
+    hpcd->ResumeCallback = HAL_PCD_ResumeCallback;
+    hpcd->ConnectCallback = HAL_PCD_ConnectCallback;
+    hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;
+    hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback;
+    hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback;
+    hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback;
+    hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback;
+    hpcd->LPMCallback = HAL_PCDEx_LPM_Callback;
+    hpcd->BCDCallback = HAL_PCDEx_BCD_Callback;
+
+    if (hpcd->MspInitCallback == NULL)
+    {
+      hpcd->MspInitCallback = HAL_PCD_MspInit;
+    }
+
+    /* Init the low level hardware */
+    hpcd->MspInitCallback(hpcd);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+    HAL_PCD_MspInit(hpcd);
+#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
+  }
+
+  hpcd->State = HAL_PCD_STATE_BUSY;
+
+  /* Disable DMA mode for FS instance */
+  if ((USBx->CID & (0x1U << 8)) == 0U)
+  {
+    hpcd->Init.dma_enable = 0U;
+  }
+
+  /* Disable the Interrupts */
+  __HAL_PCD_DISABLE(hpcd);
+
+  /*Init the Core (common init.) */
+  if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK)
+  {
+    hpcd->State = HAL_PCD_STATE_ERROR;
+    return HAL_ERROR;
+  }
+
+  /* Force Device Mode*/
+  (void)USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE);
+
+  /* Init endpoints structures */
+  for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
+  {
+    /* Init ep structure */
+    hpcd->IN_ep[i].is_in = 1U;
+    hpcd->IN_ep[i].num = i;
+    hpcd->IN_ep[i].tx_fifo_num = i;
+    /* Control until ep is activated */
+    hpcd->IN_ep[i].type = EP_TYPE_CTRL;
+    hpcd->IN_ep[i].maxpacket = 0U;
+    hpcd->IN_ep[i].xfer_buff = 0U;
+    hpcd->IN_ep[i].xfer_len = 0U;
+  }
+
+  for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
+  {
+    hpcd->OUT_ep[i].is_in = 0U;
+    hpcd->OUT_ep[i].num = i;
+    /* Control until ep is activated */
+    hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
+    hpcd->OUT_ep[i].maxpacket = 0U;
+    hpcd->OUT_ep[i].xfer_buff = 0U;
+    hpcd->OUT_ep[i].xfer_len = 0U;
+  }
+
+  /* Init Device */
+  if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK)
+  {
+    hpcd->State = HAL_PCD_STATE_ERROR;
+    return HAL_ERROR;
+  }
+
+  hpcd->USB_Address = 0U;
+  hpcd->State = HAL_PCD_STATE_READY;
+  
+  /* Activate LPM */
+  if (hpcd->Init.lpm_enable == 1U)
+  {
+    (void)HAL_PCDEx_ActivateLPM(hpcd);
+  }
+  
+  (void)USB_DevDisconnect(hpcd->Instance);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the PCD peripheral.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
+{
+  /* Check the PCD handle allocation */
+  if (hpcd == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  hpcd->State = HAL_PCD_STATE_BUSY;
+
+  /* Stop Device */
+  (void)HAL_PCD_Stop(hpcd);
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+  if (hpcd->MspDeInitCallback == NULL)
+  {
+    hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; /* Legacy weak MspDeInit  */
+  }
+
+  /* DeInit the low level hardware */
+  hpcd->MspDeInitCallback(hpcd);
+#else
+  /* DeInit the low level hardware: CLOCK, NVIC.*/
+  HAL_PCD_MspDeInit(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+  hpcd->State = HAL_PCD_STATE_RESET;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the PCD MSP.
+  * @param  hpcd PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes PCD MSP.
+  * @param  hpcd PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_MspDeInit could be implemented in the user file
+   */
+}
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+/**
+  * @brief  Register a User USB PCD Callback
+  *         To be used instead of the weak predefined callback
+  * @param  hpcd USB PCD handle
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
+  *          @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
+  *          @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
+  *          @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
+  *          @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
+  *          @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
+  *          @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
+  *          @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
+  *          @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_PCD_SOF_CB_ID :
+        hpcd->SOFCallback = pCallback;
+        break;
+
+      case HAL_PCD_SETUPSTAGE_CB_ID :
+        hpcd->SetupStageCallback = pCallback;
+        break;
+
+      case HAL_PCD_RESET_CB_ID :
+        hpcd->ResetCallback = pCallback;
+        break;
+
+      case HAL_PCD_SUSPEND_CB_ID :
+        hpcd->SuspendCallback = pCallback;
+        break;
+
+      case HAL_PCD_RESUME_CB_ID :
+        hpcd->ResumeCallback = pCallback;
+        break;
+
+      case HAL_PCD_CONNECT_CB_ID :
+        hpcd->ConnectCallback = pCallback;
+        break;
+
+      case HAL_PCD_DISCONNECT_CB_ID :
+        hpcd->DisconnectCallback = pCallback;
+        break;
+
+      case HAL_PCD_MSPINIT_CB_ID :
+        hpcd->MspInitCallback = pCallback;
+        break;
+
+      case HAL_PCD_MSPDEINIT_CB_ID :
+        hpcd->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hpcd->State == HAL_PCD_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_PCD_MSPINIT_CB_ID :
+        hpcd->MspInitCallback = pCallback;
+        break;
+
+      case HAL_PCD_MSPDEINIT_CB_ID :
+        hpcd->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+  return status;
+}
+
+/**
+  * @brief  Unregister an USB PCD Callback
+  *         USB PCD callabck is redirected to the weak predefined callback
+  * @param  hpcd USB PCD handle
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
+  *          @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
+  *          @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
+  *          @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
+  *          @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
+  *          @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
+  *          @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
+  *          @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
+  *          @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  /* Setup Legacy weak Callbacks  */
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_PCD_SOF_CB_ID :
+        hpcd->SOFCallback = HAL_PCD_SOFCallback;
+        break;
+
+      case HAL_PCD_SETUPSTAGE_CB_ID :
+        hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;
+        break;
+
+      case HAL_PCD_RESET_CB_ID :
+        hpcd->ResetCallback = HAL_PCD_ResetCallback;
+        break;
+
+      case HAL_PCD_SUSPEND_CB_ID :
+        hpcd->SuspendCallback = HAL_PCD_SuspendCallback;
+        break;
+
+      case HAL_PCD_RESUME_CB_ID :
+        hpcd->ResumeCallback = HAL_PCD_ResumeCallback;
+        break;
+
+      case HAL_PCD_CONNECT_CB_ID :
+        hpcd->ConnectCallback = HAL_PCD_ConnectCallback;
+        break;
+
+      case HAL_PCD_DISCONNECT_CB_ID :
+        hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;
+        break;
+
+      case HAL_PCD_MSPINIT_CB_ID :
+        hpcd->MspInitCallback = HAL_PCD_MspInit;
+        break;
+
+      case HAL_PCD_MSPDEINIT_CB_ID :
+        hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hpcd->State == HAL_PCD_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_PCD_MSPINIT_CB_ID :
+        hpcd->MspInitCallback = HAL_PCD_MspInit;
+        break;
+
+      case HAL_PCD_MSPDEINIT_CB_ID :
+        hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+  return status;
+}
+
+/**
+  * @brief  Register USB PCD Data OUT Stage Callback
+  *         To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback
+  * @param  hpcd PCD handle
+  * @param  pCallback pointer to the USB PCD Data OUT Stage Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->DataOutStageCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the USB PCD Data OUT Stage Callback
+  *         USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; /* Legacy weak DataOutStageCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  Register USB PCD Data IN Stage Callback
+  *         To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback
+  * @param  hpcd PCD handle
+  * @param  pCallback pointer to the USB PCD Data IN Stage Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->DataInStageCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the USB PCD Data IN Stage Callback
+  *         USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; /* Legacy weak DataInStageCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  Register USB PCD Iso OUT incomplete Callback
+  *         To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
+  * @param  hpcd PCD handle
+  * @param  pCallback pointer to the USB PCD Iso OUT incomplete Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->ISOOUTIncompleteCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the USB PCD Iso OUT incomplete Callback
+  *         USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; /* Legacy weak ISOOUTIncompleteCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  Register USB PCD Iso IN incomplete Callback
+  *         To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
+  * @param  hpcd PCD handle
+  * @param  pCallback pointer to the USB PCD Iso IN incomplete Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->ISOINIncompleteCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the USB PCD Iso IN incomplete Callback
+  *         USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; /* Legacy weak ISOINIncompleteCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  Register USB PCD BCD Callback
+  *         To be used instead of the weak HAL_PCDEx_BCD_Callback() predefined callback
+  * @param  hpcd PCD handle
+  * @param  pCallback pointer to the USB PCD BCD Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->BCDCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the USB PCD BCD Callback
+  *         USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->BCDCallback = HAL_PCDEx_BCD_Callback; /* Legacy weak HAL_PCDEx_BCD_Callback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  Register USB PCD LPM Callback
+  *         To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined callback
+  * @param  hpcd PCD handle
+  * @param  pCallback pointer to the USB PCD LPM Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->LPMCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the USB PCD LPM Callback
+  *         USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->LPMCallback = HAL_PCDEx_LPM_Callback; /* Legacy weak HAL_PCDEx_LPM_Callback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions
+ *  @brief   Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the PCD data
+    transfers.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Start the USB device
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
+{
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+  __HAL_LOCK(hpcd);
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+  if ((hpcd->Init.battery_charging_enable == 1U) &&
+      (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY))
+  {
+    /* Enable USB Transceiver */
+    USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
+  }
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+  (void)USB_DevConnect(hpcd->Instance);
+  __HAL_PCD_ENABLE(hpcd);
+  __HAL_UNLOCK(hpcd);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the USB device.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
+{
+  __HAL_LOCK(hpcd);
+  __HAL_PCD_DISABLE(hpcd);
+
+  if (USB_StopDevice(hpcd->Instance) != HAL_OK)
+  {
+    __HAL_UNLOCK(hpcd);
+    return HAL_ERROR;
+  }
+
+  (void)USB_DevDisconnect(hpcd->Instance);
+  __HAL_UNLOCK(hpcd);
+
+  return HAL_OK;
+}
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+/**
+  * @brief  Handles PCD interrupt request.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t i, ep_intr, epint, epnum;
+  uint32_t fifoemptymsk, temp;
+  USB_OTG_EPTypeDef *ep;
+
+  /* ensure that we are in device mode */
+  if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
+  {
+    /* avoid spurious interrupt */
+    if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd))
+    {
+      return;
+    }
+
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))
+    {
+      /* incorrect mode, acknowledge the interrupt */
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);
+    }
+
+     /* Handle RxQLevel Interrupt */
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
+    {
+      USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
+
+      temp = USBx->GRXSTSP;
+
+      ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];
+
+      if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) ==  STS_DATA_UPDT)
+      {
+        if ((temp & USB_OTG_GRXSTSP_BCNT) != 0U)
+        {
+          (void)USB_ReadPacket(USBx, ep->xfer_buff,
+                               (uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4));
+
+          ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
+          ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
+        }
+      }
+      else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) ==  STS_SETUP_UPDT)
+      {
+        (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U);
+        ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
+      }
+      else
+      {
+        /* ... */
+      }
+      USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
+    }
+
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))
+    {
+      epnum = 0U;
+
+      /* Read in the device interrupt bits */
+      ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance);
+
+      while (ep_intr != 0U)
+      {
+        if ((ep_intr & 0x1U) != 0U)
+        {
+          epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum);
+
+          if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC)
+          {
+            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC);
+            (void)PCD_EP_OutXfrComplete_int(hpcd, epnum);
+          }
+
+          if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)
+          {
+            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
+            /* Class B setup phase done for previous decoded setup */
+            (void)PCD_EP_OutSetupPacket_int(hpcd, epnum);
+          }
+
+          if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)
+          {
+            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);
+          }
+
+          /* Clear Status Phase Received interrupt */
+          if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
+          {
+            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
+          }
+
+          /* Clear OUT NAK interrupt */
+          if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK)
+          {
+            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK);
+          }
+        }
+        epnum++;
+        ep_intr >>= 1U;
+      }
+    }
+
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT))
+    {
+      /* Read in the device interrupt bits */
+      ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance);
+
+      epnum = 0U;
+
+      while (ep_intr != 0U)
+      {
+        if ((ep_intr & 0x1U) != 0U) /* In ITR */
+        {
+          epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum);
+
+          if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)
+          {
+            fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK));
+            USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
+
+            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);
+
+            if (hpcd->Init.dma_enable == 1U)
+            {
+              hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket;
+
+              /* this is ZLP, so prepare EP0 for next setup */
+              if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U))
+              {
+                /* prepare to rx more setup packets */
+                (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
+              }
+            }
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+            hpcd->DataInStageCallback(hpcd, (uint8_t)epnum);
+#else
+            HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+          }
+          if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)
+          {
+            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC);
+          }
+          if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE)
+          {
+            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE);
+          }
+          if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE)
+          {
+            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE);
+          }
+          if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD)
+          {
+            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD);
+          }
+          if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)
+          {
+            (void)PCD_WriteEmptyTxFifo(hpcd, epnum);
+          }
+        }
+        epnum++;
+        ep_intr >>= 1U;
+      }
+    }
+
+    /* Handle Resume Interrupt */
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))
+    {
+      /* Clear the Remote Wake-up Signaling */
+      USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
+
+      if (hpcd->LPM_State == LPM_L1)
+      {
+        hpcd->LPM_State = LPM_L0;
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+        hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE);
+#else
+        HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+      }
+      else
+      {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+        hpcd->ResumeCallback(hpcd);
+#else
+        HAL_PCD_ResumeCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+      }
+
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);
+    }
+
+    /* Handle Suspend Interrupt */
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))
+    {
+      if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
+      {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+        hpcd->SuspendCallback(hpcd);
+#else
+        HAL_PCD_SuspendCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+      }
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);
+    }
+    
+    /* Handle LPM Interrupt */
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT))
+    {
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT);
+
+      if (hpcd->LPM_State == LPM_L0)
+      {
+        hpcd->LPM_State = LPM_L1;
+        hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U;
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+        hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE);
+#else
+        HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+      }
+      else
+      {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+        hpcd->SuspendCallback(hpcd);
+#else
+        HAL_PCD_SuspendCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+      }
+    }
+    
+    /* Handle Reset Interrupt */
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
+    {
+      USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
+      (void)USB_FlushTxFifo(hpcd->Instance, 0x10U);
+
+      for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
+      {
+        USBx_INEP(i)->DIEPINT = 0xFB7FU;
+        USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
+        USBx_INEP(i)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
+        USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
+        USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
+        USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
+      }
+      USBx_DEVICE->DAINTMSK |= 0x10001U;
+
+      if (hpcd->Init.use_dedicated_ep1 != 0U)
+      {
+        USBx_DEVICE->DOUTEP1MSK |= USB_OTG_DOEPMSK_STUPM |
+                                   USB_OTG_DOEPMSK_XFRCM |
+                                   USB_OTG_DOEPMSK_EPDM;
+
+        USBx_DEVICE->DINEP1MSK |= USB_OTG_DIEPMSK_TOM |
+                                  USB_OTG_DIEPMSK_XFRCM |
+                                  USB_OTG_DIEPMSK_EPDM;
+      }
+      else
+      {
+        USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM |
+                                USB_OTG_DOEPMSK_XFRCM |
+                                USB_OTG_DOEPMSK_EPDM |
+                                USB_OTG_DOEPMSK_OTEPSPRM |
+                                USB_OTG_DOEPMSK_NAKM;
+
+        USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM |
+                                USB_OTG_DIEPMSK_XFRCM |
+                                USB_OTG_DIEPMSK_EPDM;
+      }
+
+      /* Set Default Address to 0 */
+      USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD;
+
+      /* setup EP0 to receive SETUP packets */
+      (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable,
+                             (uint8_t *)hpcd->Setup);
+
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST);
+    }
+
+    /* Handle Enumeration done Interrupt */
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))
+    {
+      (void)USB_ActivateSetup(hpcd->Instance);
+      hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance);
+
+      /* Set USB Turnaround time */
+      (void)USB_SetTurnaroundTime(hpcd->Instance,
+                                  HAL_RCC_GetHCLKFreq(),
+                                  (uint8_t)hpcd->Init.speed);
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+      hpcd->ResetCallback(hpcd);
+#else
+      HAL_PCD_ResetCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);
+    }
+
+    /* Handle SOF Interrupt */
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))
+    {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+      hpcd->SOFCallback(hpcd);
+#else
+      HAL_PCD_SOFCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF);
+    }
+
+    /* Handle Incomplete ISO IN Interrupt */
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))
+    {
+      /* Keep application checking the corresponding Iso IN endpoint
+      causing the incomplete Interrupt */
+      epnum = 0U;
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+      hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
+#else
+      HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR);
+    }
+
+    /* Handle Incomplete ISO OUT Interrupt */
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
+    {
+      /* Keep application checking the corresponding Iso OUT endpoint
+      causing the incomplete Interrupt */
+      epnum = 0U;
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+      hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
+#else
+      HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
+    }
+
+    /* Handle Connection event Interrupt */
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT))
+    {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+      hpcd->ConnectCallback(hpcd);
+#else
+      HAL_PCD_ConnectCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT);
+    }
+
+    /* Handle Disconnection event Interrupt */
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))
+    {
+      temp = hpcd->Instance->GOTGINT;
+
+      if ((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)
+      {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+        hpcd->DisconnectCallback(hpcd);
+#else
+        HAL_PCD_DisconnectCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+      }
+      hpcd->Instance->GOTGINT |= temp;
+    }
+  }
+}
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+
+/**
+  * @brief  Data OUT stage callback.
+  * @param  hpcd PCD handle
+  * @param  epnum endpoint number
+  * @retval None
+  */
+__weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(epnum);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_DataOutStageCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Data IN stage callback
+  * @param  hpcd PCD handle
+  * @param  epnum endpoint number
+  * @retval None
+  */
+__weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(epnum);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_DataInStageCallback could be implemented in the user file
+   */
+}
+/**
+  * @brief  Setup stage callback
+  * @param  hpcd PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_SetupStageCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  USB Start Of Frame callback.
+  * @param  hpcd PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_SOFCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  USB Reset callback.
+  * @param  hpcd PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_ResetCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Suspend event callback.
+  * @param  hpcd PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_SuspendCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Resume event callback.
+  * @param  hpcd PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_ResumeCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Incomplete ISO OUT callback.
+  * @param  hpcd PCD handle
+  * @param  epnum endpoint number
+  * @retval None
+  */
+__weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(epnum);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Incomplete ISO IN callback.
+  * @param  hpcd PCD handle
+  * @param  epnum endpoint number
+  * @retval None
+  */
+__weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(epnum);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Connection event callback.
+  * @param  hpcd PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_ConnectCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Disconnection event callback.
+  * @param  hpcd PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_DisconnectCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
+ *  @brief   management functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the PCD data
+    transfers.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Connect the USB device
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
+{
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+  __HAL_LOCK(hpcd);
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+  if ((hpcd->Init.battery_charging_enable == 1U) &&
+      (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY))
+  {
+    /* Enable USB Transceiver */
+    USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
+  }
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+  (void)USB_DevConnect(hpcd->Instance);
+  __HAL_UNLOCK(hpcd);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disconnect the USB device.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
+{
+  __HAL_LOCK(hpcd);
+  (void)USB_DevDisconnect(hpcd->Instance);
+  __HAL_UNLOCK(hpcd);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the USB Device address.
+  * @param  hpcd PCD handle
+  * @param  address new device address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
+{
+  __HAL_LOCK(hpcd);
+  hpcd->USB_Address = address;
+  (void)USB_SetDevAddress(hpcd->Instance, address);
+  __HAL_UNLOCK(hpcd);
+  return HAL_OK;
+}
+/**
+  * @brief  Open and configure an endpoint.
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
+  * @param  ep_mps endpoint max packet size
+  * @param  ep_type endpoint type
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
+{
+  HAL_StatusTypeDef  ret = HAL_OK;
+  PCD_EPTypeDef *ep;
+
+  if ((ep_addr & 0x80U) == 0x80U)
+  {
+    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+    ep->is_in = 1U;
+  }
+  else
+  {
+    ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
+    ep->is_in = 0U;
+  }
+
+  ep->num = ep_addr & EP_ADDR_MSK;
+  ep->maxpacket = ep_mps;
+  ep->type = ep_type;
+
+  if (ep->is_in != 0U)
+  {
+    /* Assign a Tx FIFO */
+    ep->tx_fifo_num = ep->num;
+  }
+  /* Set initial data PID. */
+  if (ep_type == EP_TYPE_BULK)
+  {
+    ep->data_pid_start = 0U;
+  }
+
+  __HAL_LOCK(hpcd);
+  (void)USB_ActivateEndpoint(hpcd->Instance, ep);
+  __HAL_UNLOCK(hpcd);
+
+  return ret;
+}
+
+/**
+  * @brief  Deactivate an endpoint.
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+  PCD_EPTypeDef *ep;
+
+  if ((ep_addr & 0x80U) == 0x80U)
+  {
+    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+    ep->is_in = 1U;
+  }
+  else
+  {
+    ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
+    ep->is_in = 0U;
+  }
+  ep->num   = ep_addr & EP_ADDR_MSK;
+
+  __HAL_LOCK(hpcd);
+  (void)USB_DeactivateEndpoint(hpcd->Instance, ep);
+  __HAL_UNLOCK(hpcd);
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Receive an amount of data.
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
+  * @param  pBuf pointer to the reception buffer
+  * @param  len amount of data to be received
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
+{
+  PCD_EPTypeDef *ep;
+
+  ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
+
+  /*setup and start the Xfer */
+  ep->xfer_buff = pBuf;
+  ep->xfer_len = len;
+  ep->xfer_count = 0U;
+  ep->is_in = 0U;
+  ep->num = ep_addr & EP_ADDR_MSK;
+
+  if (hpcd->Init.dma_enable == 1U)
+  {
+    ep->dma_addr = (uint32_t)pBuf;
+  }
+
+  if ((ep_addr & EP_ADDR_MSK) == 0U)
+  {
+    (void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
+  }
+  else
+  {
+    (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get Received Data Size
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
+  * @retval Data Size
+  */
+uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+  return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count;
+}
+/**
+  * @brief  Send an amount of data
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
+  * @param  pBuf pointer to the transmission buffer
+  * @param  len amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
+{
+  PCD_EPTypeDef *ep;
+
+  ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+
+  /*setup and start the Xfer */
+  ep->xfer_buff = pBuf;
+  ep->xfer_len = len;
+  ep->xfer_count = 0U;
+  ep->is_in = 1U;
+  ep->num = ep_addr & EP_ADDR_MSK;
+
+  if (hpcd->Init.dma_enable == 1U)
+  {
+    ep->dma_addr = (uint32_t)pBuf;
+  }
+
+  if ((ep_addr & EP_ADDR_MSK) == 0U)
+  {
+    (void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
+  }
+  else
+  {
+    (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set a STALL condition over an endpoint
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+  PCD_EPTypeDef *ep;
+
+  if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints)
+  {
+    return HAL_ERROR;
+  }
+
+  if ((0x80U & ep_addr) == 0x80U)
+  {
+    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+    ep->is_in = 1U;
+  }
+  else
+  {
+    ep = &hpcd->OUT_ep[ep_addr];
+    ep->is_in = 0U;
+  }
+
+  ep->is_stall = 1U;
+  ep->num = ep_addr & EP_ADDR_MSK;
+
+  __HAL_LOCK(hpcd);
+
+  (void)USB_EPSetStall(hpcd->Instance, ep);
+  if ((ep_addr & EP_ADDR_MSK) == 0U)
+  {
+    (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
+  }
+  __HAL_UNLOCK(hpcd);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Clear a STALL condition over in an endpoint
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+  PCD_EPTypeDef *ep;
+
+  if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints)
+  {
+    return HAL_ERROR;
+  }
+
+  if ((0x80U & ep_addr) == 0x80U)
+  {
+    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+    ep->is_in = 1U;
+  }
+  else
+  {
+    ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
+    ep->is_in = 0U;
+  }
+
+  ep->is_stall = 0U;
+  ep->num = ep_addr & EP_ADDR_MSK;
+
+  __HAL_LOCK(hpcd);
+  (void)USB_EPClearStall(hpcd->Instance, ep);
+  __HAL_UNLOCK(hpcd);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Flush an endpoint
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+  __HAL_LOCK(hpcd);
+
+  if ((ep_addr & 0x80U) == 0x80U)
+  {
+    (void)USB_FlushTxFifo(hpcd->Instance, (uint32_t)ep_addr & EP_ADDR_MSK);
+  }
+  else
+  {
+    (void)USB_FlushRxFifo(hpcd->Instance);
+  }
+
+  __HAL_UNLOCK(hpcd);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Activate remote wakeup signalling
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
+{
+  return (USB_ActivateRemoteWakeup(hpcd->Instance));
+}
+
+/**
+  * @brief  De-activate remote wakeup signalling.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
+{
+  return (USB_DeActivateRemoteWakeup(hpcd->Instance));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
+ *  @brief   Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral State functions #####
+ ===============================================================================
+    [..]
+    This subsection permits to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the PCD handle state.
+  * @param  hpcd PCD handle
+  * @retval HAL state
+  */
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
+{
+  return hpcd->State;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup PCD_Private_Functions
+  * @{
+  */
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+/**
+  * @brief  Check FIFO for the next packet to be loaded.
+  * @param  hpcd PCD handle
+  * @param  epnum endpoint number
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  USB_OTG_EPTypeDef *ep;
+  uint32_t len;
+  uint32_t len32b;
+  uint32_t fifoemptymsk;
+
+  ep = &hpcd->IN_ep[epnum];
+
+  if (ep->xfer_count > ep->xfer_len)
+  {
+    return HAL_ERROR;
+  }
+
+  len = ep->xfer_len - ep->xfer_count;
+
+  if (len > ep->maxpacket)
+  {
+    len = ep->maxpacket;
+  }
+
+  len32b = (len + 3U) / 4U;
+
+  while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) &&
+         (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U))
+  {
+    /* Write the FIFO */
+    len = ep->xfer_len - ep->xfer_count;
+
+    if (len > ep->maxpacket)
+    {
+      len = ep->maxpacket;
+    }
+    len32b = (len + 3U) / 4U;
+
+    (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len,
+                          (uint8_t)hpcd->Init.dma_enable);
+
+    ep->xfer_buff  += len;
+    ep->xfer_count += len;
+  }
+
+  if (ep->xfer_len <= ep->xfer_count)
+  {
+    fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK));
+    USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
+  }
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  process EP OUT transfer complete interrupt.
+  * @param  hpcd PCD handle
+  * @param  epnum endpoint number
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
+  uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
+
+  if (hpcd->Init.dma_enable == 1U)
+  {
+    if ((DoepintReg & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) /* Class C */
+    {
+      /* StupPktRcvd = 1 this is a setup packet */
+      if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
+          ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
+      {
+        CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
+      }
+    }
+    else if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) /* Class E */
+    {
+      CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
+    }
+    else if ((DoepintReg & (USB_OTG_DOEPINT_STUP | USB_OTG_DOEPINT_OTEPSPR)) == 0U)
+    {
+      /* StupPktRcvd = 1 this is a setup packet */
+      if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
+          ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
+      {
+        CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
+      }
+      else
+      {
+        /* out data packet received over EP0 */
+        hpcd->OUT_ep[epnum].xfer_count =
+          hpcd->OUT_ep[epnum].maxpacket -
+          (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ);
+
+        hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket;
+
+        if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U))
+        {
+          /* this is ZLP, so prepare EP0 for next setup */
+          (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
+        }
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+        hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
+#else
+        HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+      }
+    }
+    else
+    {
+      /* ... */
+    }
+  }
+  else
+  {
+    if (gSNPSiD == USB_OTG_CORE_ID_310A)
+    {
+      /* StupPktRcvd = 1 this is a setup packet */
+      if ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)
+      {
+        CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
+      }
+      else
+      {
+        if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
+        {
+          CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
+        }
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+        hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
+#else
+        HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+      }
+    }
+    else
+    {
+      if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U))
+      {
+        /* this is ZLP, so prepare EP0 for next setup */
+        (void)USB_EP0_OutStart(hpcd->Instance, 0U, (uint8_t *)hpcd->Setup);
+      }
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+      hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
+#else
+      HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+    }
+  }
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  process EP OUT setup packet received interrupt.
+  * @param  hpcd PCD handle
+  * @param  epnum endpoint number
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
+  uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
+
+  if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
+      ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
+  {
+    CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
+  }
+
+  /* Inform the upper layer that a setup packet is available */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+  hpcd->SetupStageCallback(hpcd);
+#else
+  HAL_PCD_SetupStageCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+  if ((gSNPSiD > USB_OTG_CORE_ID_300A) && (hpcd->Init.dma_enable == 1U))
+  {
+    (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
+  }
+
+  return HAL_OK;
+}
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+
+/**
+  * @}
+  */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c
new file mode 100644
index 00000000..17d3d5b0
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c
@@ -0,0 +1,348 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_pcd_ex.c
+  * @author  MCD Application Team
+  * @brief   PCD Extended HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the USB Peripheral Controller:
+  *           + Extended features functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup PCDEx PCDEx
+  * @brief PCD Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
+  * @{
+  */
+
+/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
+  * @brief    PCDEx control functions
+ *
+@verbatim
+ ===============================================================================
+                 ##### Extended features functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Update FIFO configuration
+
+@endverbatim
+  * @{
+  */
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+/**
+  * @brief  Set Tx FIFO
+  * @param  hpcd PCD handle
+  * @param  fifo The number of Tx fifo
+  * @param  size Fifo size
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
+{
+  uint8_t i;
+  uint32_t Tx_Offset;
+
+  /*  TXn min size = 16 words. (n  : Transmit FIFO index)
+      When a TxFIFO is not used, the Configuration should be as follows:
+          case 1 :  n > m    and Txn is not used    (n,m  : Transmit FIFO indexes)
+         --> Txm can use the space allocated for Txn.
+         case2  :  n < m    and Txn is not used    (n,m  : Transmit FIFO indexes)
+         --> Txn should be configured with the minimum space of 16 words
+     The FIFO is used optimally when used TxFIFOs are allocated in the top
+         of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
+     When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */
+
+  Tx_Offset = hpcd->Instance->GRXFSIZ;
+
+  if (fifo == 0U)
+  {
+    hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset;
+  }
+  else
+  {
+    Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;
+    for (i = 0U; i < (fifo - 1U); i++)
+    {
+      Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16);
+    }
+
+    /* Multiply Tx_Size by 2 to get higher performance */
+    hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set Rx FIFO
+  * @param  hpcd PCD handle
+  * @param  size Size of Rx fifo
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
+{
+  hpcd->Instance->GRXFSIZ = size;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Activate LPM feature.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+
+  hpcd->lpm_active = 1U;
+  hpcd->LPM_State = LPM_L0;
+  USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;
+  USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deactivate LPM feature.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+
+  hpcd->lpm_active = 0U;
+  USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM;
+  USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Handle BatteryCharging Process.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Enable DCD : Data Contact Detect */
+  USBx->GCCFG |= USB_OTG_GCCFG_DCDEN;
+
+  /* Wait Detect flag or a timeout is happen*/
+  while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0U)
+  {
+    /* Check for the Timeout */
+    if ((HAL_GetTick() - tickstart) > 1000U)
+    {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+      hpcd->BCDCallback(hpcd, PCD_BCD_ERROR);
+#else
+      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+      return;
+    }
+  }
+
+  /* Right response got */
+  HAL_Delay(200U);
+
+  /* Check Detect flag*/
+  if ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == USB_OTG_GCCFG_DCDET)
+  {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+    hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION);
+#else
+    HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+  }
+
+  /*Primary detection: checks if connected to Standard Downstream Port
+  (without charging capability) */
+  USBx->GCCFG &= ~ USB_OTG_GCCFG_DCDEN;
+  HAL_Delay(50U);
+  USBx->GCCFG |=  USB_OTG_GCCFG_PDEN;
+  HAL_Delay(50U);
+
+  if ((USBx->GCCFG & USB_OTG_GCCFG_PDET) == 0U)
+  {
+    /* Case of Standard Downstream Port */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+    hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
+#else
+    HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    /* start secondary detection to check connection to Charging Downstream
+    Port or Dedicated Charging Port */
+    USBx->GCCFG &= ~ USB_OTG_GCCFG_PDEN;
+    HAL_Delay(50U);
+    USBx->GCCFG |=  USB_OTG_GCCFG_SDEN;
+    HAL_Delay(50U);
+
+    if ((USBx->GCCFG & USB_OTG_GCCFG_SDET) == USB_OTG_GCCFG_SDET)
+    {
+      /* case Dedicated Charging Port  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+      hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
+#else
+      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+    }
+    else
+    {
+      /* case Charging Downstream Port  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+      hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
+#else
+      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Battery Charging capability discovery finished */
+  (void)HAL_PCDEx_DeActivateBCD(hpcd);
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+  hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
+#else
+  HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  Activate BatteryCharging feature.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+
+  USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN);
+  USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN);
+
+  /* Power Down USB tranceiver  */
+  USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
+
+  /* Enable Battery charging */
+  USBx->GCCFG |= USB_OTG_GCCFG_BCDEN;
+
+  hpcd->battery_charging_active = 1U;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deactivate BatteryCharging feature.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+
+  USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN);
+  USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN);
+
+  /* Disable Battery charging */
+  USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN);
+
+  hpcd->battery_charging_active = 0U;
+
+  return HAL_OK;
+}
+
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+/**
+  * @brief  Send LPM message to user layer callback.
+  * @param  hpcd PCD handle
+  * @param  msg LPM message
+  * @retval HAL status
+  */
+__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(msg);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCDEx_LPM_Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Send BatteryCharging message to user layer callback.
+  * @param  hpcd PCD handle
+  * @param  msg LPM message
+  * @retval HAL status
+  */
+__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(msg);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCDEx_BCD_Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c
new file mode 100644
index 00000000..43d9052a
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c
@@ -0,0 +1,868 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_pwr.c
+  * @author  MCD Application Team
+  * @brief   PWR HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Power Controller (PWR) peripheral:
+  *           + Initialization and de-initialization functions.
+  *           + Peripheral Control functions.
+  *           + Interrupt Handling functions.
+  @verbatim
+  ==============================================================================
+                        ##### PWR peripheral overview #####
+  ==============================================================================
+  [..]
+   (#) The Power control (PWR) provides an overview of the supply architecture
+       for the different power domains and of the supply configuration
+       controller.
+       In the H7 family, the number of power domains is different between
+       device lines. This difference is due to characteristics of each device.
+
+   (#) Domain architecture overview for the different H7 lines:
+      (+) Dual core lines are STM32H745, STM32H747, STM32H755 and STM32H757.
+          These devices have 3 power domains (D1, D2 and D3).
+          The domain D1 contains a CPU (Cortex-M7), a Flash memory and some
+          peripherals. The D2 domain contains peripherals and a CPU
+          (Cortex-M4). The D3 domain contains the system control, I/O logic
+          and low-power peripherals.
+      (+) STM32H743, STM32H753, STM32H742 and STM32H750 devices have 3 power
+          domains (D1, D2 and D3).
+          The domain D1 contains a CPU (Cortex-M7), a Flash memory and some
+          peripherals. The D2 domain contains peripherals. The D3 domains
+          contains the system control, I/O logic and low-power peripherals.
+      (+) STM32H7AxxQ, STM32H7BxxQ, STM32H7Axxx and STM32H7Bxxx devices have 2
+          power domains (CD and SRD).
+          The core domain (CD) contains a CPU (Cortex-M7), a Flash
+          memory and peripherals. The SmartRun domain contains the system
+          control, I/O logic and low-power peripherals.
+
+   (#) Every entity have low power mode as decribed below :
+   (#) The CPU low power modes are :
+      (+) CPU CRUN.
+      (+) CPU CSLEEP.
+      (+) CPU CSTOP.
+   (#) The domain low power modes are :
+      (+) DRUN.
+      (+) DSTOP.
+      (+) DSTANDBY.
+   (#) The SYSTEM low power modes are :
+      (+) RUN* : The Run* mode is entered after a POR reset and a wakeup from
+                 Standby. In Run* mode, the performance is limited and the
+                 system supply configuration shall be programmed. The system
+                 enters Run mode only when the ACTVOSRDY bit in PWR control
+                 status register 1 (PWR_CSR1) is set to 1.
+      (+) RUN.
+      (+) STOP.
+      (+) STANDBY.
+
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+   (#) Power management peripheral is active by default at startup level in
+       STM32h7xx lines.
+
+   (#) Call HAL_PWR_EnableBkUpAccess() and HAL_PWR_DisableBkUpAccess() functions
+       to enable/disable access to the backup domain (RTC registers, RTC backup
+       data registers and backup SRAM).
+
+   (#) Call HAL_PWR_ConfigPVD() after setting parameters to be configured (event
+       mode and voltage threshold) in order to set up the Power Voltage Detector,
+       then use HAL_PWR_EnablePVD() and  HAL_PWR_DisablePVD() functions to start
+       and stop the PVD detection.
+       (+) PVD level could be one of the following values :
+             (++) 1V95
+             (++) 2V1
+             (++) 2V25
+             (++) 2V4
+             (++) 2V55
+             (++) 2V7
+             (++) 2V85
+             (++) External voltage level
+
+   (#) Call HAL_PWR_EnableWakeUpPin() and HAL_PWR_DisableWakeUpPin() functions
+       with the right parameter to configure the wake up pin polarity (Low or
+       High) and to enable and disable it.
+
+   (#) Call HAL_PWR_EnterSLEEPMode() function to enter the current Core in SLEEP
+       mode. Wake-up from SLEEP mode could be following to an event or an
+       interrupt according to low power mode intrinsic request called (__WFI()
+       or __WFE()).
+       Please ensure to clear all CPU pending events by calling
+       HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx
+       in SLEEP mode with __WFE() entry.
+
+   (#) Call HAL_PWR_EnterSTOPMode() function to enter the whole system to Stop 0
+       mode for single core devices. For dual core devices, this API will enter
+       the domain (containing Cortex-Mx that executing this function) in DSTOP
+       mode. According to the used parameter, user could select the regulator to
+       be kept actif in low power mode and wake-up event type.
+       Please ensure to clear all CPU pending events by calling
+       HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx
+       in CSTOP mode with __WFE() entry.
+
+   (#) Call HAL_PWR_EnterSTANDBYMode() function to enter the whole system in
+       STANDBY mode for single core devices. For dual core devices, this API
+       will enter the domain (containing Cortex-Mx that executing this function)
+       in DSTANDBY mode.
+
+   (#) Call HAL_PWR_EnableSleepOnExit() and HAL_PWR_DisableSleepOnExit() APIs to
+       enable and disable the Cortex-Mx re-entring in SLEEP mode after an
+       interruption handling is over.
+
+   (#) Call HAL_PWR_EnableSEVOnPend() and HAL_PWR_DisableSEVOnPend() functions
+       to configure the Cortex-Mx to wake-up after any pending event / interrupt
+       even if it's disabled or has insufficient priority to cause exception
+       entry.
+
+   (#) Call HAL_PWR_PVD_IRQHandler() function to handle the PWR PVD interrupt
+       request.
+
+     *** PWR HAL driver macros list ***
+     =============================================
+     [..]
+       Below the list of most used macros in PWR HAL driver.
+
+      (+) __HAL_PWR_VOLTAGESCALING_CONFIG() : Configure the main internal
+                                              regulator output voltage.
+      (+) __HAL_PWR_GET_FLAG()              : Get the PWR pending flags.
+      (+) __HAL_PWR_CLEAR_FLAG()            : Clear the PWR pending flags.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup PWR PWR
+  * @brief PWR HAL module driver
+  * @{
+  */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @addtogroup PWR_Private_Constants PWR Private Constants
+  * @{
+  */
+
+/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
+  * @{
+  */
+#if !defined (DUAL_CORE)
+#define PVD_MODE_IT              (0x00010000U)
+#define PVD_MODE_EVT             (0x00020000U)
+#endif /* !defined (DUAL_CORE) */
+
+#define PVD_RISING_EDGE          (0x00000001U)
+#define PVD_FALLING_EDGE         (0x00000002U)
+#define PVD_RISING_FALLING_EDGE  (0x00000003U)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Functions PWR Exported Functions
+  * @{
+  */
+
+/** @defgroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions
+  * @brief    Initialization and De-Initialization functions
+  *
+@verbatim
+ ===============================================================================
+              ##### Initialization and De-Initialization Functions #####
+ ===============================================================================
+    [..]
+      This section provides functions allowing to deinitialize power peripheral.
+
+    [..]
+      After system reset, the backup domain (RTC registers, RTC backup data
+      registers and backup SRAM) is protected against possible unwanted write
+      accesses.
+      The HAL_PWR_EnableBkUpAccess() function enables the access to the backup
+      domain.
+      The HAL_PWR_DisableBkUpAccess() function disables the access to the backup
+      domain.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitialize the HAL PWR peripheral registers to their default reset
+  *         values.
+  * @note   This functionality is not available in this product.
+  *         The prototype is kept just to maintain compatibility with other
+  *         products.
+  * @retval None.
+  */
+void HAL_PWR_DeInit (void)
+{
+}
+
+/**
+  * @brief  Enable access to the backup domain (RTC registers, RTC backup data
+  *         registers and backup SRAM).
+  * @note   If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
+  *         Backup Domain Access should be kept enabled.
+  * @retval None.
+  */
+void HAL_PWR_EnableBkUpAccess (void)
+{
+  /* Enable access to RTC and backup registers */
+  SET_BIT (PWR->CR1, PWR_CR1_DBP);
+}
+
+/**
+  * @brief  Disable access to the backup domain (RTC registers, RTC backup data
+  *         registers and backup SRAM).
+  * @note   If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
+  *         Backup Domain Access should be kept enabled.
+  * @retval None.
+  */
+void HAL_PWR_DisableBkUpAccess (void)
+{
+  /* Disable access to RTC and backup registers */
+  CLEAR_BIT (PWR->CR1, PWR_CR1_DBP);
+}
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control Functions
+  *  @brief   Power Control functions
+  *
+@verbatim
+ ===============================================================================
+                 ##### Peripheral Control Functions #####
+ ===============================================================================
+    [..]
+      This section provides functions allowing to control power peripheral.
+
+    *** PVD configuration ***
+    =========================
+    [..]
+      (+) The PVD is used to monitor the VDD power supply by comparing it to a
+          threshold selected by the PVD Level (PLS[7:0] bits in the PWR_CR1
+          register).
+
+      (+) A PVDO flag is available to indicate if VDD is higher or lower
+          than the PVD threshold. This event is internally connected to the EXTI
+          line 16 to generate an interrupt if enabled.
+          It is configurable through __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
+
+      (+) The PVD is stopped in STANDBY mode.
+
+    *** Wake-up pin configuration ***
+    =================================
+    [..]
+      (+) Wake-up pin is used to wake up the system from STANDBY mode.
+          The pin pull is configurable through the WKUPEPR register to be in
+          No-pull, Pull-up and Pull-down.
+          The pin polarity is configurable through the WKUPEPR register to be
+          active on rising or falling edges.
+
+      (+) There are up to six Wake-up pin in the STM32H7 devices family.
+
+    *** Low Power modes configuration ***
+    =====================================
+    [..]
+     The device present 3 principles low-power modes features:
+      (+) SLEEP mode   : Cortex-Mx is stopped and all PWR domains are remaining
+                         active (Powered and Clocked).
+
+      (+) STOP mode    : Cortex-Mx is stopped, clocks are stopped and the
+                         regulator is running. The Main regulator or the LP
+                         regulator could be selected.
+
+      (+) STANDBY mode : All PWR domains enter DSTANDBY mode and the VCORE
+                         supply regulator is powered off.
+
+   *** SLEEP mode ***
+   ==================
+    [..]
+      (+) Entry:
+        The SLEEP mode is entered by using the HAL_PWR_EnterSLEEPMode(Regulator,
+        SLEEPEntry) function.
+
+          (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction.
+          (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction.
+
+      -@@- The Regulator parameter is not used for the STM32H7 family
+              and is kept as parameter just to maintain compatibility with the
+              lower power families (STM32L).
+
+      (+) Exit:
+        Any peripheral interrupt acknowledged by the nested vectored interrupt
+        controller (NVIC) can wake up the device from SLEEP mode.
+
+   *** STOP mode ***
+   =================
+    [..]
+      In system STOP mode, all clocks in the 1.2V domain are stopped, the PLL,
+      the HSI, and the HSE RC oscillators are disabled. Internal SRAM and
+      register contents are preserved.
+      The voltage regulator can be configured either in normal or low-power mode.
+      To minimize the consumption in STOP mode, FLASH can be powered off before
+      entering the STOP mode using the HAL_PWREx_EnableFlashPowerDown() function.
+      It can be switched on again by software after exiting the STOP mode using
+      the HAL_PWREx_DisableFlashPowerDown() function.
+
+      (+) Entry:
+         The STOP mode is entered using the HAL_PWR_EnterSTOPMode(Regulator,
+         STOPEntry) function with:
+
+         (++) Regulator:
+          (+++) PWR_MAINREGULATOR_ON: Main regulator ON.
+          (+++) PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON.
+
+         (++) STOPEntry:
+          (+++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction.
+          (+++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction.
+
+      (+) Exit:
+         Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
+
+   *** STANDBY mode ***
+   ====================
+    [..]
+    (+)
+      The system STANDBY mode allows to achieve the lowest power consumption.
+      It is based on the Cortex-Mx deep SLEEP mode, with the voltage regulator
+      disabled. The system is consequently powered off. The PLL, the HSI
+      oscillator and the HSE oscillator are also switched off. SRAM and register
+      contents are lost except for the RTC registers, RTC backup registers,
+      backup SRAM and standby circuitry.
+
+    [..]
+      The voltage regulator is OFF.
+
+      (++) Entry:
+        (+++) The STANDBY mode is entered using the HAL_PWR_EnterSTANDBYMode()
+              function.
+
+      (++) Exit:
+        (+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B),
+              RTC wakeup, tamper event, time stamp event, external reset in NRST
+              pin, IWDG reset.
+
+   *** Auto-wakeup (AWU) from low-power mode ***
+   =============================================
+    [..]
+     (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an
+         RTC Wakeup event, a tamper event or a time-stamp event, without
+         depending on an external interrupt (Auto-wakeup mode).
+
+     (+) RTC auto-wakeup (AWU) from the STOP and STANDBY modes
+
+       (++) To wake up from the STOP mode with an RTC alarm event, it is
+            necessary to configure the RTC to generate the RTC alarm using the
+            HAL_RTC_SetAlarm_IT() function.
+
+       (++) To wake up from the STOP mode with an RTC Tamper or time stamp event,
+            it is necessary to configure the RTC to detect the tamper or time
+            stamp event using the HAL_RTCEx_SetTimeStamp_IT() or
+            HAL_RTCEx_SetTamper_IT() functions.
+
+       (++) To wake up from the STOP mode with an RTC WakeUp event, it is
+            necessary to configure the RTC to generate the RTC WakeUp event
+            using the HAL_RTCEx_SetWakeUpTimer_IT() function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the event mode and the voltage threshold detected by the
+  *         Programmable Voltage Detector(PVD).
+  * @param  sConfigPVD : Pointer to an PWR_PVDTypeDef structure that contains
+  *                      the configuration information for the PVD.
+  * @note   Refer to the electrical characteristics of your device datasheet for
+  *         more details about the voltage threshold corresponding to each
+  *         detection level.
+  * @note   For dual core devices, please ensure to configure the EXTI lines for
+  *         the different Cortex-Mx through PWR_Exported_Macro provided by this
+  *         driver. All combination are allowed: wake up only Cortex-M7, wake up
+  *         only Cortex-M4 or wake up Cortex-M7 and Cortex-M4.
+  * @retval None.
+  */
+void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD)
+{
+  /* Check the PVD configuration parameter */
+  if (sConfigPVD == NULL)
+  {
+    return;
+  }
+
+  /* Check the parameters */
+  assert_param (IS_PWR_PVD_LEVEL (sConfigPVD->PVDLevel));
+  assert_param (IS_PWR_PVD_MODE (sConfigPVD->Mode));
+
+  /* Set PLS[7:5] bits according to PVDLevel value */
+  MODIFY_REG (PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel);
+
+  /* Clear previous config */
+#if !defined (DUAL_CORE)
+  __HAL_PWR_PVD_EXTI_DISABLE_EVENT ();
+  __HAL_PWR_PVD_EXTI_DISABLE_IT ();
+#endif /* !defined (DUAL_CORE) */
+
+  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE ();
+  __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE ();
+
+#if !defined (DUAL_CORE)
+  /* Interrupt mode configuration */
+  if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
+  {
+    __HAL_PWR_PVD_EXTI_ENABLE_IT ();
+  }
+
+  /* Event mode configuration */
+  if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
+  {
+    __HAL_PWR_PVD_EXTI_ENABLE_EVENT ();
+  }
+#endif /* !defined (DUAL_CORE) */
+
+  /* Rising edge configuration */
+  if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
+  {
+    __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE ();
+  }
+
+  /* Falling edge configuration */
+  if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
+  {
+    __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE ();
+  }
+}
+
+/**
+  * @brief Enable the Programmable Voltage Detector (PVD).
+  * @retval None.
+  */
+void HAL_PWR_EnablePVD (void)
+{
+  /* Enable the power voltage detector */
+  SET_BIT (PWR->CR1, PWR_CR1_PVDEN);
+}
+
+/**
+  * @brief Disable the Programmable Voltage Detector (PVD).
+  * @retval None.
+  */
+void HAL_PWR_DisablePVD (void)
+{
+  /* Disable the power voltage detector */
+  CLEAR_BIT (PWR->CR1, PWR_CR1_PVDEN);
+}
+
+/**
+  * @brief  Enable the WakeUp PINx functionality.
+  * @param  WakeUpPinPolarity : Specifies which Wake-Up pin to enable.
+  *          This parameter can be one of the following legacy values, which
+  *          sets the default (rising edge):
+  *            @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3,
+  *                 PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6.
+  *          or one of the following values where the user can explicitly states
+  *          the enabled pin and the chosen polarity:
+  *            @arg PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW,
+  *                 PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW,
+  *                 PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW,
+  *                 PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW,
+  *                 PWR_WAKEUP_PIN5_HIGH, PWR_WAKEUP_PIN5_LOW,
+  *                 PWR_WAKEUP_PIN6_HIGH, PWR_WAKEUP_PIN6_LOW.
+  * @note   PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
+  * @retval None.
+  */
+void HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity)
+{
+  /* Check the parameters */
+  assert_param (IS_PWR_WAKEUP_PIN (WakeUpPinPolarity));
+
+  /*
+     Enable and Specify the Wake-Up pin polarity and the pull configuration
+     for the event detection (rising or falling edge).
+  */
+  MODIFY_REG (PWR->WKUPEPR, PWR_EWUP_MASK, WakeUpPinPolarity);
+}
+
+/**
+  * @brief  Disable the WakeUp PINx functionality.
+  * @param  WakeUpPinx : Specifies the Power Wake-Up pin to disable.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3,
+  *                 PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6,
+  *                 PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW,
+  *                 PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW,
+  *                 PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW,
+  *                 PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW,
+  *                 PWR_WAKEUP_PIN5_HIGH, PWR_WAKEUP_PIN5_LOW,
+  *                 PWR_WAKEUP_PIN6_HIGH, PWR_WAKEUP_PIN6_LOW.
+  * @retval None.
+  */
+void HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx)
+{
+  /* Check the parameters */
+  assert_param (IS_PWR_WAKEUP_PIN (WakeUpPinx));
+
+  /* Disable the wake up pin selected */
+  CLEAR_BIT (PWR->WKUPEPR, (PWR_WKUPEPR_WKUPEN & WakeUpPinx));
+}
+
+/**
+  * @brief  Enter the current core in SLEEP mode (CSLEEP).
+  * @param  Regulator : Specifies the regulator state in SLEEP mode.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_MAINREGULATOR_ON     : SLEEP mode with regulator ON.
+  *            @arg PWR_LOWPOWERREGULATOR_ON : SLEEP mode with low power
+  *                                           regulator ON.
+  * @note   This parameter is not used for the STM32H7 family and is kept as
+  *         parameter just to maintain compatibility with the lower power
+  *         families.
+  * @param  SLEEPEntry : Specifies if SLEEP mode is entered with WFI or WFE
+  *                      intrinsic instruction.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_SLEEPENTRY_WFI : enter SLEEP mode with WFI instruction.
+  *            @arg PWR_SLEEPENTRY_WFE : enter SLEEP mode with WFE instruction.
+  * @note   Ensure to clear pending events before calling this API through
+  *         HAL_PWREx_ClearPendingEvent() when the SLEEP entry is WFE.
+  * @retval None.
+  */
+void HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry)
+{
+  /* Check the parameters */
+  assert_param (IS_PWR_REGULATOR (Regulator));
+  assert_param (IS_PWR_SLEEP_ENTRY (SLEEPEntry));
+
+  /* Clear SLEEPDEEP bit of Cortex System Control Register */
+  CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+
+  /* Select SLEEP mode entry */
+  if (SLEEPEntry == PWR_SLEEPENTRY_WFI)
+  {
+    /* Request Wait For Interrupt */
+    __WFI ();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __WFE ();
+  }
+}
+
+/**
+  * @brief  Enter STOP mode.
+  * @note   For single core devices, this API will enter the system in STOP mode
+  *         with all domains in DSTOP, if RUN_D3/RUN_SRD bit in CPUCR regiter is
+  *         cleared.
+  *         For dual core devices, this API will enter the domain (containing
+  *         Cortex-Mx that executing this function) in DSTOP mode. If all
+  *         Cortex-Mx domains are in DSTOP and RUN_D3 bit in CPUCR register is
+  *         cleared, all the system will enter in STOP mode.
+  * @param  Regulator : Specifies the regulator state in STOP mode.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_MAINREGULATOR_ON     : STOP mode with regulator ON.
+  *            @arg PWR_LOWPOWERREGULATOR_ON : STOP mode with low power
+  *                                            regulator ON.
+  * @param  STOPEntry : Specifies if STOP mode in entered with WFI or WFE
+  *                     intrinsic instruction.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction.
+  *            @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction.
+  * @note   In System STOP mode, all I/O pins keep the same state as in Run mode.
+  * @note   When exiting System STOP mode by issuing an interrupt or a wakeup
+  *         event, the HSI RC oscillator is selected as default system wakeup
+  *         clock.
+  * @note   In System STOP mode, when the voltage regulator operates in low
+  *         power mode, an additional startup delay is incurred when the system
+  *         is waking up. By keeping the internal regulator ON during STOP mode,
+  *         the consumption is higher although the startup time is reduced.
+  * @retval None.
+  */
+void HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry)
+{
+  /* Check the parameters */
+  assert_param (IS_PWR_REGULATOR (Regulator));
+  assert_param (IS_PWR_STOP_ENTRY (STOPEntry));
+
+  /* Select the regulator state in STOP mode */
+  MODIFY_REG (PWR->CR1, PWR_CR1_LPDS, Regulator);
+
+  /* Configure the PWR mode for the different Domains */
+#if defined (DUAL_CORE)
+  /* Check CPU ID */
+  if (HAL_GetCurrentCPUID () == CM7_CPUID)
+  {
+    /* Keep DSTOP mode when Cortex-M7 enters DEEP-SLEEP */
+    CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
+  }
+  else
+  {
+    /* Keep DSTOP mode when Cortex-M4 enters DEEP-SLEEP */
+    CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D2 | PWR_CPUCR_PDDS_D3));
+  }
+#else /* Single core devices */
+  /* Keep DSTOP mode when Cortex-M7 enter in DEEP-SLEEP */
+  CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
+
+#if defined (PWR_CPUCR_PDDS_D2)
+  /* Keep DSTOP mode when Cortex-M7 enter in DEEP-SLEEP */
+  CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2);
+#endif /* PWR_CPUCR_PDDS_D2 */
+#endif /* defined (DUAL_CORE) */
+
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+
+  /* Ensure that all instructions are done before entering STOP mode */
+  __DSB ();
+  __ISB ();
+
+  /* Select STOP mode entry */
+  if (STOPEntry == PWR_STOPENTRY_WFI)
+  {
+    /* Request Wait For Interrupt */
+    __WFI ();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __WFE ();
+  }
+
+  /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */
+  CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+}
+
+/**
+  * @brief  Enter STANDBY mode.
+  * @note   For single core devices, this API will enter the system in STANDBY
+  *         mode with all domains in DSTANDBY, if RUN_D3/RUN_SRD bit in CPUCR
+  *         regiter is cleared.
+  *         For dual core devices, this API will enter the domain (containing
+  *         Cortex-Mx that executing this function) in DSTANDBY mode. If all
+  *         Cortex-Mx domains are in DSTANDBY and RUN_D3 bit in CPUCR register
+  *         is cleared, all the system will enter in STANDBY mode.
+  * @note   The system enters Standby mode only when all domains are in DSTANDBY.
+  * @note   When the System exit STANDBY mode by issuing an interrupt or a
+  *         wakeup event, the HSI RC oscillator is selected as system clock.
+  * @retval None.
+  */
+void HAL_PWR_EnterSTANDBYMode (void)
+{
+  /* Configure the PWR mode for the different Domains */
+#if defined (DUAL_CORE)
+  /* Check CPU ID */
+  if (HAL_GetCurrentCPUID () == CM7_CPUID)
+  {
+    /* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */
+    SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
+    SET_BIT (PWR->CPU2CR, (PWR_CPU2CR_PDDS_D1 | PWR_CPU2CR_PDDS_D3));
+  }
+  else
+  {
+    /* Enter DSTANDBY mode when Cortex-M4 enters DEEP-SLEEP */
+    SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D2 | PWR_CPUCR_PDDS_D3));
+    SET_BIT (PWR->CPU2CR, (PWR_CPU2CR_PDDS_D2 | PWR_CPU2CR_PDDS_D3));
+  }
+#else /* Single core devices */
+  /* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */
+  SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
+
+#if defined (PWR_CPUCR_PDDS_D2)
+  /* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */
+  SET_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2);
+#endif /* PWR_CPUCR_PDDS_D2 */
+#endif /* defined (DUAL_CORE) */
+
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+
+  /* Ensure that all instructions are done before entering STOP mode */
+  __DSB ();
+  __ISB ();
+
+  /* This option is used to ensure that store operations are completed */
+#if defined (__CC_ARM)
+  __force_stores();
+#endif /* defined (__CC_ARM) */
+
+  /* Request Wait For Interrupt */
+  __WFI ();
+}
+
+/**
+  * @brief  Indicate Sleep-On-Exit feature when returning from Handler mode to
+  *         Thread mode.
+  * @note   Set SLEEPONEXIT bit of SCR register. When this bit is set, the
+  *         processor re-enters SLEEP mode when an interruption handling is over.
+  *         Setting this bit is useful when the processor is expected to run
+  *         only on interruptions handling.
+  * @retval None.
+  */
+void HAL_PWR_EnableSleepOnExit (void)
+{
+  /* Set SLEEPONEXIT bit of Cortex-Mx System Control Register */
+  SET_BIT (SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
+}
+
+/**
+  * @brief  Disable Sleep-On-Exit feature when returning from Handler mode to
+  *         Thread mode.
+  * @note   Clears SLEEPONEXIT bit of SCR register. When this bit is set, the
+  *         processor re-enters SLEEP mode when an interruption handling is over.
+  * @retval None
+  */
+void HAL_PWR_DisableSleepOnExit (void)
+{
+  /* Clear SLEEPONEXIT bit of Cortex-Mx System Control Register */
+  CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
+}
+
+/**
+  * @brief  Enable CORTEX SEVONPEND feature.
+  * @note   Sets SEVONPEND bit of SCR register. When this bit is set, any
+  *         pending event / interrupt even if it's disabled or has insufficient
+  *         priority to cause exception entry wakes up the Cortex-Mx.
+  * @retval None.
+  */
+void HAL_PWR_EnableSEVOnPend (void)
+{
+  /* Set SEVONPEND bit of Cortex-Mx System Control Register */
+  SET_BIT (SCB->SCR, SCB_SCR_SEVONPEND_Msk);
+}
+
+/**
+  * @brief  Disable CORTEX SEVONPEND feature.
+  * @note   Resets SEVONPEND bit of SCR register. When this bit is reset, only
+  *         enabled pending causes exception entry wakes up the Cortex-Mx.
+  * @retval None.
+  */
+void HAL_PWR_DisableSEVOnPend (void)
+{
+  /* Clear SEVONPEND bit of Cortex System Control Register */
+  CLEAR_BIT (SCB->SCR, SCB_SCR_SEVONPEND_Msk);
+}
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Exported_Functions_Group3 Interrupt Handling Functions
+  *  @brief   Interrupt Handling functions
+  *
+@verbatim
+ ===============================================================================
+                    ##### Interrupt Handling Functions #####
+ ===============================================================================
+    [..]
+    This section provides functions allowing to handle the PVD pending
+    interrupts.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function handles the PWR PVD interrupt request.
+  * @note   This API should be called under the PVD_AVD_IRQHandler().
+  * @retval None.
+  */
+void HAL_PWR_PVD_IRQHandler (void)
+{
+#if defined (DUAL_CORE)
+  /* Check Cortex-Mx ID */
+  if (HAL_GetCurrentCPUID () == CM7_CPUID)
+  {
+    /* Check PWR EXTI D1 flag */
+    if(__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U)
+    {
+      /* Clear PWR EXTI D1 pending bit */
+      __HAL_PWR_PVD_EXTI_CLEAR_FLAG ();
+
+      /* PWR PVD interrupt user callback */
+      HAL_PWR_PVDCallback ();
+    }
+  }
+  else
+  {
+    /* Check PWR EXTI D2 flag */
+    if (__HAL_PWR_PVD_EXTID2_GET_FLAG () != 0U)
+    {
+      /* Clear PWR EXTI D2 pending bit */
+      __HAL_PWR_PVD_EXTID2_CLEAR_FLAG ();
+
+      /* PWR PVD interrupt user callback */
+      HAL_PWR_PVDCallback ();
+    }
+  }
+#else /* Single core devices */
+  /* PVD EXTI line interrupt detected */
+  if (__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U)
+  {
+    /* Clear PWR EXTI pending bit */
+    __HAL_PWR_PVD_EXTI_CLEAR_FLAG ();
+
+    /* PWR PVD interrupt user callback */
+    HAL_PWR_PVDCallback ();
+  }
+#endif /* defined (DUAL_CORE) */
+}
+
+/**
+  * @brief  PWR PVD interrupt callback.
+  * @retval None.
+  */
+__weak void HAL_PWR_PVDCallback (void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PWR_PVDCallback can be implemented in the user file
+  */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_PWR_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c
new file mode 100644
index 00000000..82288f9e
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c
@@ -0,0 +1,2100 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_pwr_ex.c
+  * @author  MCD Application Team
+  * @brief   Extended PWR HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of PWR extension peripheral:
+  *           + Peripheral Extended features functions
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+   (#) Call HAL_PWREx_ConfigSupply() function to configure the regulator supply
+       with the following different setups according to hardware (support SMPS):
+       (+) PWR_DIRECT_SMPS_SUPPLY
+       (+) PWR_SMPS_1V8_SUPPLIES_LDO
+       (+) PWR_SMPS_2V5_SUPPLIES_LDO
+       (+) PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO
+       (+) PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO
+       (+) PWR_SMPS_1V8_SUPPLIES_EXT
+       (+) PWR_SMPS_2V5_SUPPLIES_EXT
+       (+) PWR_LDO_SUPPLY
+       (+) PWR_EXTERNAL_SOURCE_SUPPLY
+
+   (#) Call HAL_PWREx_GetSupplyConfig() function to get the current supply setup.
+
+   (#) Call HAL_PWREx_ControlVoltageScaling() function to configure the main
+       internal regulator output voltage. The voltage scaling could be one of
+       the following scales :
+       (+) PWR_REGULATOR_VOLTAGE_SCALE0
+       (+) PWR_REGULATOR_VOLTAGE_SCALE1
+       (+) PWR_REGULATOR_VOLTAGE_SCALE2
+       (+) PWR_REGULATOR_VOLTAGE_SCALE3
+
+   (#) Call HAL_PWREx_GetVoltageRange() function to get the current output
+       voltage applied to the main regulator.
+
+   (#) Call HAL_PWREx_ControlStopModeVoltageScaling() function to configure the
+       main internal regulator output voltage in STOP mode. The voltage scaling
+       in STOP mode could be one of the following scales :
+       (+) PWR_REGULATOR_SVOS_SCALE3
+       (+) PWR_REGULATOR_SVOS_SCALE4
+       (+) PWR_REGULATOR_SVOS_SCALE5
+
+   (#) Call HAL_PWREx_GetStopModeVoltageRange() function to get the current
+       output voltage applied to the main regulator in STOP mode.
+
+   (#) Call HAL_PWREx_EnterSTOP2Mode() function to enter the system in STOP mode
+       with core domain in D2STOP mode. This API is used only for STM32H7Axxx
+       and STM32H7Bxxx devices.
+       Please ensure to clear all CPU pending events by calling
+       HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx
+       in DEEP-SLEEP mode with __WFE() entry.
+
+   (#) Call HAL_PWREx_EnterSTOPMode() function to enter the selected domain in
+       DSTOP mode. Call this API with all available power domains to enter the
+       system in STOP mode.
+       Please ensure to clear all CPU pending events by calling
+       HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx
+       in DEEP-SLEEP mode with __WFE() entry.
+
+   (#) Call HAL_PWREx_ClearPendingEvent() function always before entring the
+       Cortex-Mx in any low power mode (SLEEP/DEEP-SLEEP) using WFE entry.
+
+   (#) Call HAL_PWREx_EnterSTANDBYMode() function to enter the selected domain
+       in DSTANDBY mode. Call this API with all available power domains to enter
+       the system in STANDBY mode.
+
+   (#) Call HAL_PWREx_ConfigD3Domain() function to setup the D3/SRD domain state
+       (RUN/STOP) when the system enter to low power mode.
+
+   (#) Call HAL_PWREx_ClearDomainFlags() function to clear the CPU flags for the
+       selected power domain. This API is used only for dual core devices.
+
+   (#) Call HAL_PWREx_HoldCore() and HAL_PWREx_ReleaseCore() functions to hold
+       and release the selected CPU and and their domain peripherals when
+       exiting STOP mode. These APIs are used only for dual core devices.
+
+   (#) Call HAL_PWREx_EnableFlashPowerDown() and
+       HAL_PWREx_DisableFlashPowerDown() functions to enable and disable the
+       Flash Power Down in STOP mode.
+
+   (#) Call HAL_PWREx_EnableMemoryShutOff() and
+       HAL_PWREx_DisableMemoryShutOff() functions to enable and disable the
+       memory block shut-off in DStop or DStop2. These APIs are used only for
+       STM32H7Axxx and STM32H7Bxxx lines.
+
+   (#) Call HAL_PWREx_EnableWakeUpPin() and HAL_PWREx_DisableWakeUpPin()
+       functions to enable and disable the Wake-up pin functionality for
+       the selected pin.
+
+   (#) Call HAL_PWREx_GetWakeupFlag() and HAL_PWREx_ClearWakeupFlag()
+       functions to manage wake-up flag for the selected pin.
+
+   (#) Call HAL_PWREx_WAKEUP_PIN_IRQHandler() function to handle all wake-up
+       pins interrupts.
+
+   (#) Call HAL_PWREx_EnableBkUpReg() and HAL_PWREx_DisableBkUpReg() functions
+       to enable and disable the backup domain regulator.
+
+   (#) Call HAL_PWREx_EnableUSBReg(), HAL_PWREx_DisableUSBReg(),
+       HAL_PWREx_EnableUSBVoltageDetector() and
+       HAL_PWREx_DisableUSBVoltageDetector() functions to manage USB power
+       regulation functionnalities.
+
+   (#) Call HAL_PWREx_EnableBatteryCharging() and
+       HAL_PWREx_DisableBatteryCharging() functions to enable and disable the
+       battery charging feature with the selected resistor.
+
+   (#) Call HAL_PWREx_EnableAnalogBooster() and
+       HAL_PWREx_DisableAnalogBooster() functions to enable and disable the
+       AVD boost feature when the VDD supply voltage is below 2V7.
+
+   (#) Call HAL_PWREx_EnableMonitoring() and HAL_PWREx_DisableMonitoring()
+       functions to enable and disable the VBAT and Temperature monitoring.
+       When VBAT and Temperature monitoring feature is enables, use
+       HAL_PWREx_GetTemperatureLevel() and HAL_PWREx_GetVBATLevel() to get
+       respectively the Temperature level and VBAT level.
+
+   (#) Call HAL_PWREx_GetMMCVoltage() and HAL_PWREx_DisableMonitoring()
+       function to get VDDMMC voltage level. This API is used only for
+       STM32H7AxxQ, STM32H7BxxQ, STM32H7Axxx and STM32H7Bxxx lines
+
+   (#) Call HAL_PWREx_ConfigAVD() after setting parameter to be configured
+       (event mode and voltage threshold) in order to set up the Analog Voltage
+       Detector then use HAL_PWREx_EnableAVD() and  HAL_PWREx_DisableAVD()
+       functions to start and stop the AVD detection.
+       (+) AVD level could be one of the following values :
+             (++) 1V7
+             (++) 2V1
+             (++) 2V5
+             (++) 2V8
+
+   (#) Call HAL_PWREx_PVD_AVD_IRQHandler() function to handle the PWR PVD and
+       AVD interrupt request.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup PWREx PWREx
+  * @brief PWR Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @addtogroup PWREx_Private_Constants
+  * @{
+  */
+
+/** @defgroup PWREx_AVD_Mode_Mask PWR Extended AVD Mode Mask
+  * @{
+  */
+#define AVD_MODE_IT              (0x00010000U)
+#define AVD_MODE_EVT             (0x00020000U)
+#define AVD_RISING_EDGE          (0x00000001U)
+#define AVD_FALLING_EDGE         (0x00000002U)
+#define AVD_RISING_FALLING_EDGE  (0x00000003U)
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_REG_SET_TIMEOUT PWR Extended Flag Setting Time Out Value
+  * @{
+  */
+#define PWR_FLAG_SETTING_DELAY   (1000U)
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_WakeUp_Pins_Offsets PWREx Wake-Up Pins masks and offsets
+  * @{
+  */
+/* Wake-Up Pins EXTI register mask */
+#define PWR_EXTI_WAKEUP_PINS_MASK  (EXTI_IMR2_IM55 | EXTI_IMR2_IM56 |\
+                                    EXTI_IMR2_IM57 | EXTI_IMR2_IM58 |\
+                                    EXTI_IMR2_IM59 | EXTI_IMR2_IM60)
+
+/* Wake-Up Pins PWR Pin Pull shift offsets */
+#define PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET (2U)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup PWREx_Exported_Functions PWREx Exported Functions
+  * @{
+  */
+
+/** @defgroup PWREx_Exported_Functions_Group1 Power Supply Control Functions
+  * @brief    Power supply control functions
+  *
+@verbatim
+ ===============================================================================
+                  ##### Power supply control functions #####
+ ===============================================================================
+    [..]
+   (#) When the system is powered on, the POR monitors VDD supply. Once VDD is
+       above the POR threshold level, the voltage regulator is enabled in the
+       default supply configuration:
+      (+) The Voltage converter output level is set at 1V0 in accordance with
+          the VOS3 level configured in PWR (D3/SRD) domain control register
+          (PWR_D3CR/PWR_SRDCR).
+      (+) The system is kept in reset mode as long as VCORE is not ok.
+      (+) Once VCORE is ok, the system is taken out of reset and the HSI
+          oscillator is enabled.
+      (+) Once the oscillator is stable, the system is initialized: Flash memory
+          and option bytes are loaded and the CPU starts in Run* mode.
+      (+) The software shall then initialize the system including supply
+          configuration programming using the HAL_PWREx_ConfigSupply().
+      (+) Once the supply configuration has been configured, the
+          HAL_PWREx_ConfigSupply() function checks the ACTVOSRDY bit in PWR
+          control status register 1 (PWR_CSR1) to guarantee a valid voltage
+          levels:
+       (++) As long as ACTVOSRDY indicates that voltage levels are invalid, the
+            system is in limited Run* mode, write accesses to the RAMs are not
+            permitted and VOS shall not be changed.
+       (++) Once ACTVOSRDY indicates that voltage levels are valid, the system
+            is in normal Run mode, write accesses to RAMs are allowed and VOS
+            can be changed.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Configure the system Power Supply.
+  * @param  SupplySource : Specifies the Power Supply source to set after a
+  *                        system startup.
+  *         This parameter can be one of the following values :
+  *            @arg PWR_DIRECT_SMPS_SUPPLY : The SMPS supplies the Vcore Power
+  *                                          Domains. The LDO is Bypassed.
+  *            @arg PWR_SMPS_1V8_SUPPLIES_LDO : The SMPS 1.8V output supplies
+  *                                             the LDO. The Vcore Power Domains
+  *                                             are supplied from the LDO.
+  *            @arg PWR_SMPS_2V5_SUPPLIES_LDO : The SMPS 2.5V output supplies
+  *                                             the LDO. The Vcore Power Domains
+  *                                             are supplied from the LDO.
+  *            @arg PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO : The SMPS 1.8V output
+  *                                                     supplies external
+  *                                                     circuits and the LDO.
+  *                                                     The Vcore Power Domains
+  *                                                     are supplied from the
+  *                                                     LDO.
+  *            @arg PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO : The SMPS 2.5V output
+  *                                                     supplies external
+  *                                                     circuits and the LDO.
+  *                                                     The Vcore Power Domains
+  *                                                     are supplied from the
+  *                                                     LDO.
+  *            @arg PWR_SMPS_1V8_SUPPLIES_EXT : The SMPS 1.8V output supplies
+  *                                             external circuits. The LDO is
+  *                                             Bypassed. The Vcore Power
+  *                                             Domains are supplied from
+  *                                             external source.
+  *            @arg PWR_SMPS_2V5_SUPPLIES_EXT : The SMPS 2.5V output supplies
+  *                                             external circuits. The LDO is
+  *                                             Bypassed. The Vcore Power
+  *                                             Domains are supplied from
+  *                                             external source.
+  *            @arg PWR_LDO_SUPPLY : The LDO regulator supplies the Vcore Power
+  *                                  Domains. The SMPS regulator is Bypassed.
+  *            @arg PWR_EXTERNAL_SOURCE_SUPPLY : The SMPS and the LDO are
+  *                                              Bypassed. The Vcore Power
+  *                                              Domains are supplied from
+  *                                              external source.
+  * @note   The PWR_LDO_SUPPLY and PWR_EXTERNAL_SOURCE_SUPPLY are used by all
+  *         H7 lines.
+  *         The PWR_DIRECT_SMPS_SUPPLY, PWR_SMPS_1V8_SUPPLIES_LDO,
+  *         PWR_SMPS_2V5_SUPPLIES_LDO, PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO,
+  *         PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO, PWR_SMPS_1V8_SUPPLIES_EXT and
+  *         PWR_SMPS_2V5_SUPPLIES_EXT are used only for lines that supports SMPS
+  *         regulator.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource)
+{
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param (IS_PWR_SUPPLY (SupplySource));
+
+  /* Check if supply source was configured */
+#if defined (PWR_FLAG_SCUEN)
+  if (__HAL_PWR_GET_FLAG (PWR_FLAG_SCUEN) == 0U)
+#else
+  if ((PWR->CR3 & (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)) != (PWR_CR3_SMPSEN | PWR_CR3_LDOEN))
+#endif /* defined (PWR_FLAG_SCUEN) */
+  {
+    /* Check supply configuration */
+    if ((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource)
+    {
+      /* Supply configuration update locked, can't apply a new supply config */
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Supply configuration update locked, but new supply configuration
+         matches with old supply configuration : nothing to do
+      */
+      return HAL_OK;
+    }
+  }
+
+  /* Set the power supply configuration */
+  MODIFY_REG (PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource);
+
+  /* Get tick */
+  tickstart = HAL_GetTick ();
+
+  /* Wait till voltage level flag is set */
+  while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
+  {
+    if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+#if defined (SMPS)
+  /* When the SMPS supplies external circuits verify that SDEXTRDY flag is set */
+  if ((SupplySource == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) ||
+      (SupplySource == PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) ||
+      (SupplySource == PWR_SMPS_1V8_SUPPLIES_EXT)         ||
+      (SupplySource == PWR_SMPS_2V5_SUPPLIES_EXT))
+  {
+    /* Get the current tick number */
+    tickstart = HAL_GetTick ();
+
+    /* Wait till SMPS external supply ready flag is set */
+    while (__HAL_PWR_GET_FLAG (PWR_FLAG_SMPSEXTRDY) == 0U)
+    {
+      if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY)
+      {
+        return HAL_ERROR;
+      }
+    }
+  }
+#endif /* defined (SMPS) */
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Get the power supply configuration.
+  * @retval The supply configuration.
+  */
+uint32_t HAL_PWREx_GetSupplyConfig (void)
+{
+  return (PWR->CR3 & PWR_SUPPLY_CONFIG_MASK);
+}
+
+/**
+  * @brief Configure the main internal regulator output voltage.
+  * @note   For STM32H7x3, STM32H7x5, STM32H7x7, STM32H742 and STM32H750 lines,
+  *         configuring Voltage Scale 0 is only possible when Vcore is supplied
+  *         from LDO (Low DropOut). The SYSCFG Clock must be enabled through
+  *         __HAL_RCC_SYSCFG_CLK_ENABLE() macro before configuring Voltage
+  *         Scale 0.
+  * @param  VoltageScaling : Specifies the regulator output voltage to achieve
+  *                          a tradeoff between performance and power
+  *                          consumption.
+  *          This parameter can be one of the following values :
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE0 : Regulator voltage output
+  *                                                Scale 0 mode.
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output
+  *                                                range 1 mode.
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output
+  *                                                range 2 mode.
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output
+  *                                                range 3 mode.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling)
+{
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param (IS_PWR_REGULATOR_VOLTAGE (VoltageScaling));
+
+  /* Get the voltage scaling  */
+  if ((PWR->CSR1 & PWR_CSR1_ACTVOS) == VoltageScaling)
+  {
+    /* Old and new voltage scaling configuration match : nothing to do */
+    return HAL_OK;
+  }
+
+#if defined (PWR_SRDCR_VOS)
+  /* Set the voltage range */
+  MODIFY_REG (PWR->SRDCR, PWR_SRDCR_VOS, VoltageScaling);
+#else
+  if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE0)
+  {
+    if ((PWR->CR3 & PWR_CR3_LDOEN) == PWR_CR3_LDOEN)
+    {
+      /* Set the voltage range */
+      MODIFY_REG (PWR->D3CR, PWR_D3CR_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
+
+      /* Get tick */
+      tickstart = HAL_GetTick ();
+
+      /* Wait till voltage level flag is set */
+      while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
+      {
+        if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY)
+        {
+          return HAL_ERROR;
+        }
+      }
+
+      /* Enable the PWR overdrive */
+      SET_BIT (SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);
+    }
+    else
+    {
+      /* The voltage scale 0 is only possible when LDO regulator is enabled */
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    if ((PWR->CSR1 & PWR_CSR1_ACTVOS) == PWR_REGULATOR_VOLTAGE_SCALE1)
+    {
+      if ((SYSCFG->PWRCR & SYSCFG_PWRCR_ODEN) != 0U)
+      {
+        /* Disable the PWR overdrive */
+        CLEAR_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);
+
+        /* Get tick */
+        tickstart = HAL_GetTick ();
+
+        /* Wait till voltage level flag is set */
+        while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
+        {
+          if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY)
+          {
+            return HAL_ERROR;
+          }
+        }
+      }
+    }
+
+    /* Set the voltage range */
+    MODIFY_REG (PWR->D3CR, PWR_D3CR_VOS, VoltageScaling);
+  }
+#endif /* defined (PWR_SRDCR_VOS) */
+
+  /* Get tick */
+  tickstart = HAL_GetTick ();
+
+  /* Wait till voltage level flag is set */
+  while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > PWR_FLAG_SETTING_DELAY)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Get the main internal regulator output voltage. Reflecting the last
+  *        VOS value applied to the PMU.
+  * @retval The current applied VOS selection.
+  */
+uint32_t HAL_PWREx_GetVoltageRange (void)
+{
+  /* Get the active voltage scaling */
+  return (PWR->CSR1 & PWR_CSR1_ACTVOS);
+}
+
+/**
+  * @brief Configure the main internal regulator output voltage in STOP mode.
+  * @param  VoltageScaling : Specifies the regulator output voltage when the
+  *         system enters Stop mode to achieve a tradeoff between performance
+  *         and power consumption.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_REGULATOR_SVOS_SCALE3 : Regulator voltage output range
+  *                                             3 mode.
+  *            @arg PWR_REGULATOR_SVOS_SCALE4 : Regulator voltage output range
+  *                                             4 mode.
+  *            @arg PWR_REGULATOR_SVOS_SCALE5 : Regulator voltage output range
+  *                                             5 mode.
+  * @note   The Stop mode voltage scaling for SVOS4 and SVOS5 sets the voltage
+  *         regulator in Low-power (LP) mode to further reduce power consumption.
+  *         When preselecting SVOS3, the use of the voltage regulator low-power
+  *         mode (LP) can be selected by LPDS register bit.
+  * @note   The selected SVOS4 and SVOS5 levels add an additional startup delay
+  *         when exiting from system Stop mode.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling (uint32_t VoltageScaling)
+{
+  /* Check the parameters */
+  assert_param (IS_PWR_STOP_MODE_REGULATOR_VOLTAGE (VoltageScaling));
+
+  /* Return the stop mode voltage range */
+  MODIFY_REG (PWR->CR1, PWR_CR1_SVOS, VoltageScaling);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Get the main internal regulator output voltage in STOP mode.
+  * @retval The actual applied VOS selection.
+  */
+uint32_t HAL_PWREx_GetStopModeVoltageRange (void)
+{
+  /* Return the stop voltage scaling */
+  return (PWR->CR1 & PWR_CR1_SVOS);
+}
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_Exported_Functions_Group2 Low Power Control Functions
+  * @brief    Low power control functions
+  *
+@verbatim
+ ===============================================================================
+                     ##### Low power control functions #####
+ ===============================================================================
+
+    *** Domains Low Power modes configuration ***
+    =============================================
+    [..]
+      This section provides the extended low power mode control APIs.
+      The system presents 3 principles domains (D1, D2 and D3) that can be
+      operated in low-power modes (DSTOP or DSTANDBY mode):
+
+      (+) DSTOP mode to enters a domain to STOP mode:
+       (++) D1 domain and/or D2 domain enters DSTOP mode only when the CPU
+            subsystem is in CSTOP mode and has allocated peripheral in the
+            domain.
+            In DSTOP mode the domain bus matrix clock is stopped.
+       (++) The system enters STOP mode using one of the following scenarios:
+        (+++) D1 domain enters DSTANDBY mode (powered off) and D2, D3 domains
+              enter DSTOP mode.
+        (+++) D2 domain enters DSTANDBY mode (powered off) and D1, D3 domains
+              enter DSTOP mode.
+        (+++) D3 domain enters DSTANDBY mode (powered off) and D1, D2 domains
+              enter DSTOP mode.
+        (+++) D1 and D2 domains enter DSTANDBY mode (powered off) and D3 domain
+              enters DSTOP mode.
+        (+++) D1 and D3 domains enter DSTANDBY mode (powered off) and D2 domain
+              enters DSTOP mode.
+        (+++) D2 and D3 domains enter DSTANDBY mode (powered off) and D1 domain
+              enters DSTOP mode.
+        (+++) D1, D2 and D3 domains enter DSTOP mode.
+       (++) When the system enters STOP mode, the clocks are stopped and the
+            regulator is running in main or low power mode.
+       (++) D3 domain can be kept in Run mode regardless of the CPU status when
+            enter STOP mode by using HAL_PWREx_ConfigD3Domain(D3State) function.
+
+      (+) DSTANDBY mode to enters a domain to STANDBY mode:
+       (++) The DSTANDBY mode is entered when the PDDS_Dn bit in PWR CPU control
+            register (PWR_CPUCR) for the Dn domain selects Standby mode.
+       (++) The system enters STANDBY mode only when D1, D2 and D3 domains enter
+            DSTANDBY mode. Consequently the VCORE supply regulator is powered
+            off.
+
+   *** DSTOP mode ***
+   ==================
+    [..]
+      In DStop mode the domain bus matrix clock is stopped.
+      The Flash memory can enter low-power Stop mode when it is enabled through
+      FLPS in PWR_CR1 register. This allows a trade-off between domain DStop
+      restart time and low power consumption.
+    [..]
+      In DStop mode domain peripherals using the LSI or LSE clock and
+      peripherals having a kernel clock request are still able to operate.
+    [..]
+      Before entering DSTOP mode it is recommended to call SCB_CleanDCache
+      function in order to clean the D-Cache and guarantee the data integrity
+      for the SRAM memories.
+
+      (+) Entry:
+         The DSTOP mode is entered using the HAL_PWREx_EnterSTOPMode(Regulator,
+         STOPEntry, Domain) function with:
+         (++) Regulator:
+          (+++) PWR_MAINREGULATOR_ON     : Main regulator ON.
+          (+++) PWR_LOWPOWERREGULATOR_ON : Low Power regulator ON.
+         (++) STOPEntry:
+          (+++) PWR_STOPENTRY_WFI : enter STOP mode with WFI instruction
+          (+++) PWR_STOPENTRY_WFE : enter STOP mode with WFE instruction
+         (++) Domain:
+          (+++) PWR_D1_DOMAIN : Enters D1 domain to DSTOP mode.
+          (+++) PWR_D2_DOMAIN : Enters D2 domain to DSTOP mode.
+          (+++) PWR_D3_DOMAIN : Enters D3 domain to DSTOP mode.
+
+      (+) Exit:
+        Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
+
+   *** DSTANDBY mode ***
+   =====================
+    [..]
+      In DStandby mode:
+        (+) The domain bus matrix clock is stopped.
+        (+) The domain is powered down and the domain RAM and register contents
+            are lost.
+    [..]
+      Before entering DSTANDBY mode it is recommended to call SCB_CleanDCache
+      function in order to clean the D-Cache and guarantee the data integrity
+      for the SRAM memories.
+
+      (+) Entry:
+         The DSTANDBY mode is entered using the HAL_PWREx_EnterSTANDBYMode
+         (Domain) function with:
+       (++) Domain:
+        (+++) PWR_D1_DOMAIN : Enters D1 domain to DSTANDBY mode.
+        (+++) PWR_D2_DOMAIN : Enters D2 domain to DSTANDBY mode.
+        (+++) PWR_D3_DOMAIN : Enters D3 domain to DSTANDBY mode.
+
+      (+) Exit:
+        WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC
+        wakeup, tamper event, time stamp event, external reset in NRST pin,
+        IWDG reset.
+
+   *** Keep D3/SRD in RUN mode ***
+   ===============================
+    [..]
+      D3/SRD domain can be kept in Run mode regardless of the CPU status when
+      entering STOP mode by using HAL_PWREx_ConfigD3Domain(D3State) function
+      with :
+       (+) D3State:
+        (++) PWR_D3_DOMAIN_STOP : D3/SDR domain follows the CPU sub-system
+                                  mode.
+        (++) PWR_D3_DOMAIN_RUN : D3/SRD domain remains in Run mode regardless
+                                 of CPU subsystem mode.
+
+    *** FLASH Power Down configuration ****
+    =======================================
+    [..]
+      By setting the FLPS bit in the PWR_CR1 register using the
+      HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters
+      power down mode when the device enters STOP mode. When the Flash memory is
+      in power down mode, an additional startup delay is incurred when waking up
+      from STOP mode.
+
+    *** Wakeup Pins configuration ****
+    ===================================
+    [..]
+      Wakeup pins allow the system to exit from Standby mode. The configuration
+      of wakeup pins is done with the HAL_PWREx_EnableWakeUpPin(sPinParams)
+      function with:
+       (+) sPinParams: structure to enable and configure a wakeup pin:
+        (++) WakeUpPin: Wakeup pin to be enabled.
+        (++) PinPolarity: Wakeup pin polarity (rising or falling edge).
+        (++) PinPull: Wakeup pin pull (no pull, pull-up or pull-down).
+    [..]
+      The wakeup pins are internally connected to the EXTI lines [55-60] to
+      generate an interrupt if enabled. The EXTI lines configuration is done by
+      the HAL_EXTI_Dx_EventInputConfig() functions defined in the stm32h7xxhal.c
+      file.
+    [..]
+      When a wakeup pin event is received the HAL_PWREx_WAKEUP_PIN_IRQHandler is
+      called and the appropriate flag is set in the PWR_WKUPFR register. Then in
+      the HAL_PWREx_WAKEUP_PIN_IRQHandler function the wakeup pin flag will be
+      cleared and the appropriate user callback will be called. The user can add
+      his own code by customization of function pointer HAL_PWREx_WKUPx_Callback.
+
+@endverbatim
+  * @{
+  */
+
+#if defined (PWR_CPUCR_RETDS_CD)
+/**
+  * @brief Enter the system to STOP mode with main domain in DSTOP2.
+  * @note   In STOP mode, the domain bus matrix clock is stalled.
+  * @note   In STOP mode, memories and registers are maintained and peripherals
+  *         in CPU domain are no longer operational.
+  * @note   All clocks in the VCORE domain are stopped, the PLL, the HSI and the
+  *         HSE oscillators are disabled. Only Peripherals that have wakeup
+  *         capability can switch on the HSI to receive a frame, and switch off
+  *         the HSI after receiving the frame if it is not a wakeup frame. In
+  *         this case the HSI clock is propagated only to the peripheral
+  *         requesting it.
+  * @note   When exiting STOP mode by issuing an interrupt or a wakeup event,
+  *         the HSI RC oscillator is selected as system clock if STOPWUCK bit in
+  *         RCC_CFGR register is set.
+  * @param  Regulator : Specifies the regulator state in STOP mode.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_MAINREGULATOR_ON     : STOP mode with regulator ON.
+  *            @arg PWR_LOWPOWERREGULATOR_ON : STOP mode with low power
+  *                                            regulator ON.
+  * @param  STOPEntry : Specifies if STOP mode in entered with WFI or WFE
+  *                     intrinsic instruction.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction.
+  *            @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction.
+  * @retval None.
+  */
+void HAL_PWREx_EnterSTOP2Mode (uint32_t Regulator, uint8_t STOPEntry)
+{
+  /* Check the parameters */
+  assert_param (IS_PWR_REGULATOR (Regulator));
+  assert_param (IS_PWR_STOP_ENTRY (STOPEntry));
+
+  /* Select the regulator state in Stop mode */
+  MODIFY_REG (PWR->CR1, PWR_CR1_LPDS, Regulator);
+
+  /* Go to DStop2 mode (deep retention) when CPU domain enters Deepsleep */
+  SET_BIT (PWR->CPUCR, PWR_CPUCR_RETDS_CD);
+
+  /* Keep DSTOP mode when SmartRun domain enters Deepsleep */
+  CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_SRD);
+
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+
+  /* Ensure that all instructions are done before entering STOP mode */
+  __ISB ();
+  __DSB ();
+
+  /* Select Stop mode entry */
+  if (STOPEntry == PWR_STOPENTRY_WFI)
+  {
+    /* Request Wait For Interrupt */
+    __WFI ();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __WFE ();
+  }
+
+  /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */
+  CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+}
+#endif /* defined (PWR_CPUCR_RETDS_CD) */
+
+/**
+  * @brief Enter a Domain to DSTOP mode.
+  * @note   This API gives flexibility to manage independently each domain STOP
+  *         mode. For dual core lines, this API should be executed with the
+  *         corresponding Cortex-Mx to enter domain to DSTOP mode. When it is
+  *         executed by all available Cortex-Mx, the system enter to STOP mode.
+  *         For single core lines, calling this API with domain parameter set to
+  *         PWR_D1_DOMAIN (D1/CD), the whole system will enter in STOP mode
+  *         independently of PWR_CPUCR_PDDS_Dx bits values if RUN_D3 bit in the
+  *         CPUCR_RUN_D3 is cleared.
+  * @note   In DStop mode the domain bus matrix clock is stopped.
+  * @note   The system D3/SRD domain enter Stop mode only when the CPU subsystem
+  *         is in CStop mode, the EXTI wakeup sources are inactive and at least
+  *         one PDDS_Dn bit in PWR CPU control register (PWR_CPUCR) for
+  *         any domain request Stop.
+  * @note   Before entering DSTOP mode it is recommended to call SCB_CleanDCache
+  *         function in order to clean the D-Cache and guarantee the data
+  *         integrity for the SRAM memories.
+  * @note   In System Stop mode, the domain peripherals that use the LSI or LSE
+  *         clock, and the peripherals that have a kernel clock request to
+  *         select HSI or CSI as source, are still able to operate.
+  * @param  Regulator : Specifies the regulator state in STOP mode.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_MAINREGULATOR_ON     : STOP mode with regulator ON.
+  *            @arg PWR_LOWPOWERREGULATOR_ON : STOP mode with low power
+  *                                            regulator ON.
+  * @param  STOPEntry : Specifies if STOP mode in entered with WFI or WFE
+  *                     intrinsic instruction.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction.
+  *            @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction.
+  * @param  Domain : Specifies the Domain to enter in DSTOP mode.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_D1_DOMAIN : Enter D1/CD Domain to DSTOP mode.
+  *            @arg PWR_D2_DOMAIN : Enter D2 Domain to DSTOP mode.
+  *            @arg PWR_D3_DOMAIN : Enter D3/SRD Domain to DSTOP mode.
+  * @retval None.
+  */
+void HAL_PWREx_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain)
+{
+  /* Check the parameters */
+  assert_param (IS_PWR_REGULATOR (Regulator));
+  assert_param (IS_PWR_STOP_ENTRY (STOPEntry));
+  assert_param (IS_PWR_DOMAIN (Domain));
+
+  /* Select the regulator state in Stop mode */
+  MODIFY_REG (PWR->CR1, PWR_CR1_LPDS, Regulator);
+
+  /* Select the domain Power Down DeepSleep */
+  if (Domain == PWR_D1_DOMAIN)
+  {
+#if defined (DUAL_CORE)
+    /* Check current core */
+    if (HAL_GetCurrentCPUID () != CM7_CPUID)
+    {
+      /*
+         When the domain selected and the cortex-mx don't match, entering stop
+         mode will not be performed
+      */
+      return;
+    }
+#endif /* defined (DUAL_CORE) */
+
+    /* Keep DSTOP mode when D1/CD domain enters Deepsleep */
+    CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D1);
+
+    /* Set SLEEPDEEP bit of Cortex System Control Register */
+    SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+
+    /* Ensure that all instructions are done before entering STOP mode */
+    __DSB ();
+    __ISB ();
+
+    /* Select Stop mode entry */
+    if (STOPEntry == PWR_STOPENTRY_WFI)
+    {
+      /* Request Wait For Interrupt */
+      __WFI ();
+    }
+    else
+    {
+      /* Request Wait For Event */
+      __WFE ();
+    }
+
+    /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */
+    CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+  }
+#if defined (PWR_CPUCR_PDDS_D2)
+  else if (Domain == PWR_D2_DOMAIN)
+  {
+    /* Keep DSTOP mode when D2 domain enters Deepsleep */
+    CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2);
+
+#if defined (DUAL_CORE)
+    /* Check current core */
+    if (HAL_GetCurrentCPUID () != CM4_CPUID)
+    {
+      /*
+         When the domain selected and the cortex-mx don't match, entering stop
+         mode will not be performed
+      */
+      return;
+    }
+
+    /* Set SLEEPDEEP bit of Cortex System Control Register */
+    SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+
+    /* Ensure that all instructions are done before entering STOP mode */
+    __DSB ();
+    __ISB ();
+
+    /* Select Stop mode entry */
+    if (STOPEntry == PWR_STOPENTRY_WFI)
+    {
+      /* Request Wait For Interrupt */
+      __WFI ();
+    }
+    else
+    {
+      /* Request Wait For Event */
+      __WFE ();
+    }
+
+    /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */
+    CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+#endif /* defined (DUAL_CORE) */
+  }
+#endif /* defined (PWR_CPUCR_PDDS_D2) */
+  else
+  {
+    /* Keep DSTOP mode when D3/SRD domain enters Deepsleep */
+    CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D3);
+  }
+}
+
+/**
+  * @brief Clear pending event.
+  * @note   This API clears the pending event in order to enter a given CPU
+  *         to CSLEEP or CSTOP. It should be called just before APIs performing
+  *         enter low power mode using Wait For Event request.
+  * @retval None.
+  */
+void HAL_PWREx_ClearPendingEvent (void)
+{
+#if defined (DUAL_CORE)
+  /* Check the current Core */
+  if (HAL_GetCurrentCPUID () == CM7_CPUID)
+  {
+    __WFE ();
+  }
+  else
+  {
+    __SEV ();
+    __WFE ();
+  }
+#else
+  __WFE ();
+#endif /* defined (DUAL_CORE) */
+}
+
+/**
+  * @brief Enter a Domain to DSTANDBY mode.
+  * @note   This API gives flexibility to manage independently each domain
+  *         STANDBY mode. For dual core lines, this API should be executed with
+  *         the corresponding Cortex-Mx to enter domain to DSTANDBY mode. When
+  *         it is executed by all available Cortex-Mx, the system enter STANDBY
+  *         mode.
+  *         For single core lines, calling this API with D1/SRD the selected
+  *         domain will enter the whole system in STOP if PWR_CPUCR_PDDS_D3 = 0
+  *         and enter the whole system in STANDBY if PWR_CPUCR_PDDS_D3 = 1.
+  * @note   The DStandby mode is entered when all PDDS_Dn bits in PWR_CPUCR for
+  *         the Dn domain select Standby mode. When the system enters Standby
+  *         mode, the voltage regulator is disabled.
+  * @note   When D2 or D3 domain is in DStandby mode and the CPU sets the
+  *         domain PDDS_Dn bit to select Stop mode, the domain remains in
+  *         DStandby mode. The domain will only exit DStandby when the CPU
+  *         allocates a peripheral in the domain.
+  * @note   The system D3/SRD domain enters Standby mode only when the D1 and D2
+  *         domain are in DStandby.
+  * @note   Before entering DSTANDBY mode it is recommended to call
+  *         SCB_CleanDCache function in order to clean the D-Cache and guarantee
+  *         the data integrity for the SRAM memories.
+  * @param  Domain : Specifies the Domain to enter to STANDBY mode.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_D1_DOMAIN: Enter D1/CD Domain to DSTANDBY mode.
+  *            @arg PWR_D2_DOMAIN: Enter D2 Domain to DSTANDBY mode.
+  *            @arg PWR_D3_DOMAIN: Enter D3/SRD Domain to DSTANDBY mode.
+  * @retval None
+  */
+void HAL_PWREx_EnterSTANDBYMode (uint32_t Domain)
+{
+  /* Check the parameters */
+  assert_param (IS_PWR_DOMAIN (Domain));
+
+  /* Select the domain Power Down DeepSleep */
+  if (Domain == PWR_D1_DOMAIN)
+  {
+#if defined (DUAL_CORE)
+    /* Check current core */
+    if (HAL_GetCurrentCPUID () != CM7_CPUID)
+    {
+      /*
+         When the domain selected and the cortex-mx don't match, entering
+         standby mode will not be performed
+      */
+      return;
+    }
+#endif /* defined (DUAL_CORE) */
+
+    /* Allow DSTANDBY mode when D1/CD domain enters Deepsleep */
+    SET_BIT (PWR-> CPUCR, PWR_CPUCR_PDDS_D1);
+
+#if defined (DUAL_CORE)
+    /* Allow DSTANDBY mode when D1/CD domain enters Deepsleep */
+    SET_BIT (PWR-> CPU2CR, PWR_CPU2CR_PDDS_D1);
+#endif /*DUAL_CORE*/
+
+    /* Set SLEEPDEEP bit of Cortex System Control Register */
+    SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+
+    /* This option is used to ensure that store operations are completed */
+#if defined (__CC_ARM)
+    __force_stores ();
+#endif /* defined (__CC_ARM) */
+
+    /* Request Wait For Interrupt */
+    __WFI ();
+  }
+#if defined (PWR_CPUCR_PDDS_D2)
+  else if (Domain == PWR_D2_DOMAIN)
+  {
+    /* Allow DSTANDBY mode when D2 domain enters Deepsleep */
+    SET_BIT (PWR-> CPUCR, PWR_CPUCR_PDDS_D2);
+
+#if defined (DUAL_CORE)
+    /* Check current core */
+    if (HAL_GetCurrentCPUID () != CM4_CPUID)
+    {
+      /*
+         When the domain selected and the cortex-mx don't match, entering
+         standby mode will not be performed
+      */
+      return;
+    }
+
+    /* Allow DSTANDBY mode when D2 domain enters Deepsleep */
+    SET_BIT (PWR-> CPU2CR, PWR_CPU2CR_PDDS_D2);
+
+    /* Set SLEEPDEEP bit of Cortex System Control Register */
+    SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+
+    /* This option is used to ensure that store operations are completed */
+#if defined (__CC_ARM)
+    __force_stores ();
+#endif /* defined (__CC_ARM) */
+
+    /* Request Wait For Interrupt */
+    __WFI ();
+#endif /* defined (DUAL_CORE) */
+  }
+#endif /* defined (PWR_CPUCR_PDDS_D2) */
+  else
+  {
+    /* Allow DSTANDBY mode when D3/SRD domain enters Deepsleep */
+    SET_BIT (PWR-> CPUCR, PWR_CPUCR_PDDS_D3);
+
+#if defined (DUAL_CORE)
+    /* Allow DSTANDBY mode when D3/SRD domain enters Deepsleep */
+    SET_BIT (PWR-> CPU2CR, PWR_CPU2CR_PDDS_D3);
+#endif /* defined (DUAL_CORE) */
+  }
+}
+
+/**
+  * @brief Configure the D3/SRD Domain state when the System in low power mode.
+  * @param  D3State : Specifies the D3/SRD state.
+  *          This parameter can be one of the following values :
+  *            @arg PWR_D3_DOMAIN_STOP : D3/SRD domain will follow the most deep
+  *                                      CPU sub-system low power mode.
+  *            @arg PWR_D3_DOMAIN_RUN : D3/SRD domain will stay in RUN mode
+  *                                     regardless of the CPU sub-system low
+  *                                     power mode.
+  * @retval None
+  */
+void HAL_PWREx_ConfigD3Domain (uint32_t D3State)
+{
+  /* Check the parameter */
+  assert_param (IS_D3_STATE (D3State));
+
+  /* Keep D3/SRD in run mode */
+  MODIFY_REG (PWR->CPUCR, PWR_CPUCR_RUN_D3, D3State);
+}
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Clear HOLD2F, HOLD1F, STOPF, SBF, SBF_D1, and SBF_D2 flags for a
+  *        given domain.
+  * @param  DomainFlags : Specifies the Domain flags to be cleared.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_D1_DOMAIN_FLAGS : Clear D1 Domain flags.
+  *            @arg PWR_D2_DOMAIN_FLAGS : Clear D2 Domain flags.
+  *            @arg PWR_ALL_DOMAIN_FLAGS : Clear D1 and D2 Domain flags.
+  * @retval None.
+  */
+void HAL_PWREx_ClearDomainFlags (uint32_t DomainFlags)
+{
+  /* Check the parameter */
+  assert_param (IS_PWR_DOMAIN_FLAG (DomainFlags));
+
+  /* D1 CPU flags */
+  if (DomainFlags == PWR_D1_DOMAIN_FLAGS)
+  {
+    /* Clear D1 domain flags (HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2) */
+    SET_BIT (PWR->CPUCR, PWR_CPUCR_CSSF);
+  }
+  /* D2 CPU flags */
+  else if (DomainFlags == PWR_D2_DOMAIN_FLAGS)
+  {
+    /* Clear D2 domain flags (HOLD1F, STOPF, SBF, SBF_D1, and SBF_D2) */
+    SET_BIT (PWR->CPU2CR, PWR_CPU2CR_CSSF);
+  }
+  else
+  {
+    /* Clear D1 domain flags (HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2) */
+    SET_BIT (PWR->CPUCR, PWR_CPUCR_CSSF);
+    /* Clear D2 domain flags (HOLD1F, STOPF, SBF, SBF_D1, and SBF_D2) */
+    SET_BIT (PWR->CPU2CR, PWR_CPU2CR_CSSF);
+  }
+}
+
+/**
+  * @brief Hold the CPU and their domain peripherals when exiting STOP mode.
+  * @param  CPU : Specifies the core to be held.
+  *         This parameter can be one of the following values:
+  *             @arg PWR_CORE_CPU1: Hold CPU1 and set CPU2 as master.
+  *             @arg PWR_CORE_CPU2: Hold CPU2 and set CPU1 as master.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PWREx_HoldCore (uint32_t CPU)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param (IS_PWR_CORE (CPU));
+
+  /* Check CPU index */
+  if (CPU == PWR_CORE_CPU2)
+  {
+    /* If CPU1 is not held */
+    if ((PWR->CPU2CR & PWR_CPU2CR_HOLD1) != PWR_CPU2CR_HOLD1)
+    {
+      /* Set HOLD2 bit */
+      SET_BIT (PWR->CPUCR, PWR_CPUCR_HOLD2);
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* If CPU2 is not held */
+    if ((PWR->CPUCR & PWR_CPUCR_HOLD2) != PWR_CPUCR_HOLD2)
+    {
+      /* Set HOLD1 bit */
+      SET_BIT (PWR->CPU2CR, PWR_CPU2CR_HOLD1);
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief Release the CPU and their domain peripherals after a wake-up from
+  *        STOP mode.
+  * @param  CPU: Specifies the core to be released.
+  *         This parameter can be one of the following values:
+  *             @arg  PWR_CORE_CPU1: Release the CPU1 and their domain
+  *                   peripherals from holding.
+  *             @arg  PWR_CORE_CPU2: Release the CPU2 and their domain
+  *                   peripherals from holding.
+  * @retval None
+  */
+void HAL_PWREx_ReleaseCore (uint32_t CPU)
+{
+  /* Check the parameters */
+  assert_param (IS_PWR_CORE (CPU));
+
+  /* Check CPU index */
+  if (CPU == PWR_CORE_CPU2)
+  {
+    /* Reset HOLD2 bit */
+    CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_HOLD2);
+  }
+  else
+  {
+    /* Reset HOLD1 bit */
+    CLEAR_BIT (PWR->CPU2CR, PWR_CPU2CR_HOLD1);
+  }
+}
+#endif /* defined (DUAL_CORE) */
+
+
+/**
+  * @brief Enable the Flash Power Down in Stop mode.
+  * @note   When Flash Power Down is enabled  the Flash memory enters low-power
+  *         mode when D1/SRD domain is in DStop mode. This feature allows to
+  *         obtain the best trade-off between low-power consumption and restart
+  *         time when exiting from DStop mode.
+  * @retval None.
+  */
+void HAL_PWREx_EnableFlashPowerDown (void)
+{
+  /* Enable the Flash Power Down */
+  SET_BIT (PWR->CR1, PWR_CR1_FLPS);
+}
+
+/**
+  * @brief Disable the Flash Power Down in Stop mode.
+  * @note   When Flash Power Down is disabled  the Flash memory is kept on
+  *         normal mode when D1/SRD domain is in DStop mode. This feature allows
+  *         to obtain the best trade-off between low-power consumption and
+  *         restart time when exiting from DStop mode.
+  * @retval None.
+  */
+void HAL_PWREx_DisableFlashPowerDown (void)
+{
+  /* Disable the Flash Power Down */
+  CLEAR_BIT (PWR->CR1, PWR_CR1_FLPS);
+}
+
+#if defined (PWR_CR1_SRDRAMSO)
+/**
+  * @brief Enable memory block shut-off in DStop or DStop2 modes
+  * @note   In DStop or DStop2 mode, the content of the memory blocks is
+  *         maintained. Further power optimization can be obtained by switching
+  *         off some memory blocks. This optimization implies loss of the memory
+  *         content. The user can select which memory is discarded during STOP
+  *         mode by means of xxSO bits.
+  * @param  MemoryBlock : Specifies the memory block to shut-off during DStop or
+  *                       DStop2 mode.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_SRD_AHB_MEMORY_BLOCK : SmartRun domain AHB memory.
+  *            @arg PWR_USB_FDCAN_MEMORY_BLOCK : High-speed interfaces USB and
+  *                                              FDCAN memories.
+  *            @arg PWR_GFXMMU_JPEG_MEMORY_BLOCK : GFXMMU and JPEG memories.
+  *            @arg PWR_TCM_ECM_MEMORY_BLOCK : Instruction TCM and ETM memories.
+  *            @arg PWR_RAM1_AHB_MEMORY_BLOCK : AHB RAM1 memory.
+  *            @arg PWR_RAM2_AHB_MEMORY_BLOCK : AHB RAM2 memory.
+  *            @arg PWR_RAM1_AXI_MEMORY_BLOCK : AXI RAM1 memory.
+  *            @arg PWR_RAM2_AXI_MEMORY_BLOCK : AXI RAM2 memory.
+  *            @arg PWR_RAM3_AXI_MEMORY_BLOCK : AXI RAM3 memory.
+  * @retval None.
+  */
+void HAL_PWREx_EnableMemoryShutOff (uint32_t MemoryBlock)
+{
+  /* Check the parameter */
+  assert_param (IS_PWR_MEMORY_BLOCK (MemoryBlock));
+
+  /* Enable memory block shut-off */
+  SET_BIT (PWR->CR1, MemoryBlock);
+}
+
+/**
+  * @brief Disable memory block shut-off in DStop or DStop2 modes
+  * @param  MemoryBlock : Specifies the memory block to keep content during
+  *                       DStop or DStop2 mode.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_SRD_AHB_MEMORY_BLOCK : SmartRun domain AHB memory.
+  *            @arg PWR_USB_FDCAN_MEMORY_BLOCK : High-speed interfaces USB and
+  *                                              FDCAN memories.
+  *            @arg PWR_GFXMMU_JPEG_MEMORY_BLOCK : GFXMMU and JPEG memories.
+  *            @arg PWR_TCM_ECM_MEMORY_BLOCK : Instruction TCM and ETM memories.
+  *            @arg PWR_RAM1_AHB_MEMORY_BLOCK : AHB RAM1 memory.
+  *            @arg PWR_RAM2_AHB_MEMORY_BLOCK : AHB RAM2 memory.
+  *            @arg PWR_RAM1_AXI_MEMORY_BLOCK : AXI RAM1 memory.
+  *            @arg PWR_RAM2_AXI_MEMORY_BLOCK : AXI RAM2 memory.
+  *            @arg PWR_RAM3_AXI_MEMORY_BLOCK : AXI RAM3 memory.
+  * @retval None.
+  */
+void HAL_PWREx_DisableMemoryShutOff (uint32_t MemoryBlock)
+{
+  /* Check the parameter */
+  assert_param (IS_PWR_MEMORY_BLOCK (MemoryBlock));
+
+  /* Disable memory block shut-off */
+  CLEAR_BIT (PWR->CR1, MemoryBlock);
+}
+#endif /* defined (PWR_CR1_SRDRAMSO) */
+
+/**
+  * @brief Enable the Wake-up PINx functionality.
+  * @param  sPinParams : Pointer to a PWREx_WakeupPinTypeDef structure that
+  *                      contains the configuration information for the wake-up
+  *                      Pin.
+  * @note   For dual core devices, please ensure to configure the EXTI lines for
+  *         the different Cortex-Mx. All combination are allowed: wake up only
+  *         Cortex-M7, wake up only Cortex-M4 and wake up Cortex-M7 and
+  *         Cortex-M4.
+  * @retval None.
+  */
+void HAL_PWREx_EnableWakeUpPin (PWREx_WakeupPinTypeDef *sPinParams)
+{
+  uint32_t pinConfig;
+  uint32_t regMask;
+  const uint32_t pullMask = PWR_WKUPEPR_WKUPPUPD1;
+
+  /* Check the parameters */
+  assert_param (IS_PWR_WAKEUP_PIN (sPinParams->WakeUpPin));
+  assert_param (IS_PWR_WAKEUP_PIN_POLARITY (sPinParams->PinPolarity));
+  assert_param (IS_PWR_WAKEUP_PIN_PULL (sPinParams->PinPull));
+
+  pinConfig = sPinParams->WakeUpPin | \
+              (sPinParams->PinPolarity << ((POSITION_VAL(sPinParams->WakeUpPin) + PWR_WKUPEPR_WKUPP1_Pos) & 0x1FU)) | \
+              (sPinParams->PinPull << (((POSITION_VAL(sPinParams->WakeUpPin) * PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET) + PWR_WKUPEPR_WKUPPUPD1_Pos) & 0x1FU));
+
+  regMask   = sPinParams->WakeUpPin | \
+              (PWR_WKUPEPR_WKUPP1 << (POSITION_VAL(sPinParams->WakeUpPin) & 0x1FU)) | \
+              (pullMask << ((POSITION_VAL(sPinParams->WakeUpPin) * PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET) & 0x1FU));
+
+  /* Enable and Specify the Wake-Up pin polarity and the pull configuration
+     for the event detection (rising or falling edge) */
+  MODIFY_REG (PWR->WKUPEPR, regMask, pinConfig);
+#ifndef DUAL_CORE
+  /* Configure the Wakeup Pin EXTI Line */
+  MODIFY_REG (EXTI->IMR2, PWR_EXTI_WAKEUP_PINS_MASK, (sPinParams->WakeUpPin << EXTI_IMR2_IM55_Pos));
+#endif /* !DUAL_CORE */
+}
+
+/**
+  * @brief Disable the Wake-up PINx functionality.
+  * @param  WakeUpPin : Specifies the Wake-Up pin to be disabled.
+  *          This parameter can be one of the following values:
+  *           @arg PWR_WAKEUP_PIN1 : Disable PA0  wake-up PIN.
+  *           @arg PWR_WAKEUP_PIN2 : Disable PA2  wake-up PIN.
+  *           @arg PWR_WAKEUP_PIN3 : Disable PI8  wake-up PIN.
+  *           @arg PWR_WAKEUP_PIN4 : Disable PC13 wake-up PIN.
+  *           @arg PWR_WAKEUP_PIN5 : Disable PI11 wake-up PIN.
+  *           @arg PWR_WAKEUP_PIN6 : Disable PC1  wake-up PIN.
+  * @retval None
+  */
+void HAL_PWREx_DisableWakeUpPin (uint32_t WakeUpPin)
+{
+  /* Check the parameter */
+  assert_param (IS_PWR_WAKEUP_PIN (WakeUpPin));
+
+  /* Disable the WakeUpPin */
+  CLEAR_BIT (PWR->WKUPEPR, WakeUpPin);
+}
+
+/**
+  * @brief Get the Wake-Up Pin pending flags.
+  * @param  WakeUpFlag : Specifies the Wake-Up PIN flag to be checked.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_WAKEUP_FLAG1    : Get wakeup event received from PA0.
+  *            @arg PWR_WAKEUP_FLAG2    : Get wakeup event received from PA2.
+  *            @arg PWR_WAKEUP_FLAG3    : Get wakeup event received from PI8.
+  *            @arg PWR_WAKEUP_FLAG4    : Get wakeup event received from PC13.
+  *            @arg PWR_WAKEUP_FLAG5    : Get wakeup event received from PI11.
+  *            @arg PWR_WAKEUP_FLAG6    : Get wakeup event received from PC1.
+  *            @arg PWR_WAKEUP_FLAG_ALL : Get Wakeup event received from all
+  *                                      wake up pins.
+  * @retval The Wake-Up pin flag.
+  */
+uint32_t HAL_PWREx_GetWakeupFlag (uint32_t WakeUpFlag)
+{
+  /* Check the parameters */
+  assert_param (IS_PWR_WAKEUP_FLAG (WakeUpFlag));
+
+  /* Return the wake up pin flag */
+  return (PWR->WKUPFR & WakeUpFlag);
+}
+
+/**
+  * @brief Clear the Wake-Up pin pending flag.
+  * @param  WakeUpFlag: Specifies the Wake-Up PIN flag to clear.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_WAKEUP_FLAG1 : Clear the wakeup event received from PA0.
+  *            @arg PWR_WAKEUP_FLAG2 : Clear the wakeup event received from PA2.
+  *            @arg PWR_WAKEUP_FLAG3 : Clear the wakeup event received from PI8.
+  *            @arg PWR_WAKEUP_FLAG4 : Clear the wakeup event received from PC13.
+  *            @arg PWR_WAKEUP_FLAG5 : Clear the wakeup event received from PI11.
+  *            @arg PWR_WAKEUP_FLAG6 : Clear the wakeup event received from PC1.
+  *            @arg PWR_WAKEUP_FLAG_ALL : Clear the wakeup events received from
+  *                                      all wake up pins.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag (uint32_t WakeUpFlag)
+{
+  /* Check the parameter */
+  assert_param (IS_PWR_WAKEUP_FLAG (WakeUpFlag));
+
+  /* Clear the wake up event received from wake up pin x */
+  SET_BIT (PWR->WKUPCR, WakeUpFlag);
+
+  /* Check if the wake up event is well cleared */
+  if ((PWR->WKUPFR & WakeUpFlag) != 0U)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief This function handles the PWR WAKEUP PIN interrupt request.
+  * @note   This API should be called under the WAKEUP_PIN_IRQHandler().
+  * @retval None.
+  */
+void HAL_PWREx_WAKEUP_PIN_IRQHandler (void)
+{
+  /* Wakeup pin EXTI line interrupt detected */
+  if (READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF1) != 0U)
+  {
+    /* Clear PWR WKUPF1 flag */
+    __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP1);
+
+    /* PWR WKUP1 interrupt user callback */
+    HAL_PWREx_WKUP1_Callback ();
+  }
+  else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF2) != 0U)
+  {
+    /* Clear PWR WKUPF2 flag */
+    __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP2);
+
+    /* PWR WKUP2 interrupt user callback */
+    HAL_PWREx_WKUP2_Callback ();
+  }
+  else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF3) != 0U)
+  {
+    /* Clear PWR WKUPF3 flag */
+    __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP3);
+
+    /* PWR WKUP3 interrupt user callback */
+    HAL_PWREx_WKUP3_Callback ();
+  }
+  else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF4) != 0U)
+  {
+    /* Clear PWR WKUPF4 flag */
+    __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP4);
+
+    /* PWR WKUP4 interrupt user callback */
+    HAL_PWREx_WKUP4_Callback ();
+  }
+  else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF5) != 0U)
+  {
+    /* Clear PWR WKUPF5 flag */
+    __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP5);
+
+    /* PWR WKUP5 interrupt user callback */
+    HAL_PWREx_WKUP5_Callback ();
+  }
+  else
+  {
+    /* Clear PWR WKUPF6 flag */
+    __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP6);
+
+    /* PWR WKUP6 interrupt user callback */
+    HAL_PWREx_WKUP6_Callback ();
+  }
+}
+
+/**
+  * @brief PWR WKUP1 interrupt callback.
+  * @retval None.
+  */
+__weak void HAL_PWREx_WKUP1_Callback (void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PWREx_WKUP1Callback can be implemented in the user file
+  */
+}
+
+/**
+  * @brief PWR WKUP2 interrupt callback.
+  * @retval None.
+  */
+__weak void HAL_PWREx_WKUP2_Callback (void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PWREx_WKUP2Callback can be implemented in the user file
+  */
+}
+
+/**
+  * @brief PWR WKUP3 interrupt callback.
+  * @retval None.
+  */
+__weak void HAL_PWREx_WKUP3_Callback (void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PWREx_WKUP3Callback can be implemented in the user file
+  */
+}
+
+/**
+  * @brief PWR WKUP4 interrupt callback.
+  * @retval None.
+  */
+__weak void HAL_PWREx_WKUP4_Callback (void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PWREx_WKUP4Callback can be implemented in the user file
+  */
+}
+
+/**
+  * @brief PWR WKUP5 interrupt callback.
+  * @retval None.
+  */
+__weak void HAL_PWREx_WKUP5_Callback (void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PWREx_WKUP5Callback can be implemented in the user file
+  */
+}
+
+/**
+  * @brief PWR WKUP6 interrupt callback.
+  * @retval None.
+  */
+__weak void HAL_PWREx_WKUP6_Callback (void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PWREx_WKUP6Callback can be implemented in the user file
+  */
+}
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_Exported_Functions_Group3 Peripherals control functions
+  * @brief    Peripherals control functions
+  *
+@verbatim
+ ===============================================================================
+                 ##### Peripherals control functions #####
+ ===============================================================================
+
+    *** Main and Backup Regulators configuration ***
+    ================================================
+    [..]
+      (+) The backup domain includes 4 Kbytes of backup SRAM accessible only
+          from the CPU, and addressed in 32-bit, 16-bit or 8-bit mode. Its
+          content is retained even in Standby or VBAT mode when the low power
+          backup regulator is enabled. It can be considered as an internal
+          EEPROM when VBAT is always present. You can use the
+          HAL_PWREx_EnableBkUpReg() function to enable the low power backup
+          regulator.
+      (+) When the backup domain is supplied by VDD (analog switch connected to
+          VDD) the backup SRAM is powered from VDD which replaces the VBAT power
+          supply to save battery life.
+      (+) The backup SRAM is not mass erased by a tamper event. It is read
+          protected to prevent confidential data, such as cryptographic private
+          key, from being accessed. The backup SRAM can be erased only through
+          the Flash interface when a protection level change from level 1 to
+          level 0 is requested.
+      -@- Refer to the description of Read protection (RDP) in the Flash
+          programming manual.
+      (+) The main internal regulator can be configured to have a tradeoff
+          between performance and power consumption when the device does not
+          operate at the maximum frequency. This is done through
+          HAL_PWREx_ControlVoltageScaling(VOS) function which configure the VOS
+          bit in PWR_D3CR register.
+      (+) The main internal regulator can be configured to operate in Low Power
+          mode when the system enters STOP mode to further reduce power
+          consumption.
+          This is done through HAL_PWREx_ControlStopModeVoltageScaling(SVOS)
+          function which configure the SVOS bit in PWR_CR1 register.
+          The selected SVOS4 and SVOS5 levels add an additional startup delay
+          when exiting from system Stop mode.
+    -@- Refer to the product datasheets for more details.
+
+    *** USB Regulator configuration ***
+    ===================================
+    [..]
+      (+) The USB transceivers are supplied from a dedicated VDD33USB supply
+          that can be provided either by the integrated USB regulator, or by an
+          external USB supply.
+      (+) The USB regulator is enabled by HAL_PWREx_EnableUSBReg() function, the
+          VDD33USB is then provided from the USB regulator.
+      (+) When the USB regulator is enabled, the VDD33USB supply level detector
+          shall be enabled through  HAL_PWREx_EnableUSBVoltageDetector()
+          function.
+      (+) The USB regulator is disabled through HAL_PWREx_DisableUSBReg()
+          function and VDD33USB can be provided from an external supply. In this
+          case VDD33USB and VDD50USB shall be connected together.
+
+    *** VBAT battery charging ***
+    =============================
+    [..]
+      (+) When VDD is present, the external battery connected to VBAT can be
+          charged through an internal resistance. VBAT charging can be performed
+          either through a 5 KOhm resistor or through a 1.5 KOhm resistor.
+      (+) VBAT charging is enabled by HAL_PWREx_EnableBatteryCharging
+          (ResistorValue) function with:
+       (++) ResistorValue:
+        (+++) PWR_BATTERY_CHARGING_RESISTOR_5: 5 KOhm resistor.
+        (+++) PWR_BATTERY_CHARGING_RESISTOR_1_5: 1.5 KOhm resistor.
+      (+) VBAT charging is disabled by HAL_PWREx_DisableBatteryCharging()
+          function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Enable the Backup Regulator.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg (void)
+{
+  uint32_t tickstart;
+
+  /* Enable the Backup regulator */
+  SET_BIT (PWR->CR2, PWR_CR2_BREN);
+
+  /* Get tick */
+  tickstart = HAL_GetTick ();
+
+  /* Wait till Backup regulator ready flag is set */
+  while (__HAL_PWR_GET_FLAG (PWR_FLAG_BRR) == 0U)
+  {
+    if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Disable the Backup Regulator.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg (void)
+{
+  uint32_t tickstart;
+
+  /* Disable the Backup regulator */
+  CLEAR_BIT (PWR->CR2, PWR_CR2_BREN);
+
+  /* Get tick */
+  tickstart = HAL_GetTick ();
+
+  /* Wait till Backup regulator ready flag is reset */
+  while (__HAL_PWR_GET_FLAG (PWR_FLAG_BRR) != 0U)
+  {
+    if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Enable the USB Regulator.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_PWREx_EnableUSBReg (void)
+{
+  uint32_t tickstart;
+
+  /* Enable the USB regulator */
+  SET_BIT (PWR->CR3, PWR_CR3_USBREGEN);
+
+  /* Get tick */
+  tickstart = HAL_GetTick ();
+
+  /* Wait till the USB regulator ready flag is set */
+  while (__HAL_PWR_GET_FLAG (PWR_FLAG_USB33RDY) == 0U)
+  {
+    if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Disable the USB Regulator.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_PWREx_DisableUSBReg (void)
+{
+  uint32_t tickstart;
+
+  /* Disable the USB regulator */
+  CLEAR_BIT (PWR->CR3, PWR_CR3_USBREGEN);
+
+  /* Get tick */
+  tickstart = HAL_GetTick ();
+
+  /* Wait till the USB regulator ready flag is reset */
+  while(__HAL_PWR_GET_FLAG (PWR_FLAG_USB33RDY) != 0U)
+  {
+    if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Enable the USB voltage level detector.
+  * @retval None.
+  */
+void HAL_PWREx_EnableUSBVoltageDetector (void)
+{
+  /* Enable the USB voltage detector */
+  SET_BIT (PWR->CR3, PWR_CR3_USB33DEN);
+}
+
+/**
+  * @brief Disable the USB voltage level detector.
+  * @retval None.
+  */
+void HAL_PWREx_DisableUSBVoltageDetector (void)
+{
+  /* Disable the USB voltage detector */
+  CLEAR_BIT (PWR->CR3, PWR_CR3_USB33DEN);
+}
+
+/**
+  * @brief Enable the Battery charging.
+  * @note   When VDD is present, charge the external battery through an internal
+  *         resistor.
+  * @param  ResistorValue : Specifies the charging resistor.
+  *          This parameter can be one of the following values :
+  *            @arg PWR_BATTERY_CHARGING_RESISTOR_5 : 5 KOhm resistor.
+  *            @arg PWR_BATTERY_CHARGING_RESISTOR_1_5 : 1.5 KOhm resistor.
+  * @retval None.
+  */
+void HAL_PWREx_EnableBatteryCharging (uint32_t ResistorValue)
+{
+  /* Check the parameter */
+  assert_param (IS_PWR_BATTERY_RESISTOR_SELECT (ResistorValue));
+
+  /* Specify the charging resistor */
+  MODIFY_REG (PWR->CR3, PWR_CR3_VBRS, ResistorValue);
+
+  /* Enable the Battery charging */
+  SET_BIT (PWR->CR3, PWR_CR3_VBE);
+}
+
+/**
+  * @brief Disable the Battery charging.
+  * @retval None.
+  */
+void HAL_PWREx_DisableBatteryCharging (void)
+{
+  /* Disable the Battery charging */
+  CLEAR_BIT (PWR->CR3, PWR_CR3_VBE);
+}
+
+#if defined (PWR_CR1_BOOSTE)
+/**
+  * @brief Enable the booster to guarantee the analog switch AC performance when
+  *        the VDD supply voltage is below 2V7.
+  * @note   The VDD supply voltage can be monitored through the PVD and the PLS
+  *         field bits.
+  * @retval None.
+  */
+void HAL_PWREx_EnableAnalogBooster (void)
+{
+  /* Enable the Analog voltage */
+  SET_BIT (PWR->CR1, PWR_CR1_AVD_READY);
+
+  /* Enable VDDA booster */
+  SET_BIT (PWR->CR1, PWR_CR1_BOOSTE);
+}
+
+/**
+  * @brief Disable the analog booster.
+  * @retval None.
+  */
+void HAL_PWREx_DisableAnalogBooster (void)
+{
+  /* Disable VDDA booster */
+  CLEAR_BIT (PWR->CR1, PWR_CR1_BOOSTE);
+
+  /* Disable the Analog voltage */
+  CLEAR_BIT (PWR->CR1, PWR_CR1_AVD_READY);
+}
+#endif /* defined (PWR_CR1_BOOSTE) */
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_Exported_Functions_Group4 Power Monitoring functions
+  * @brief    Power Monitoring functions
+  *
+@verbatim
+ ===============================================================================
+                 ##### Power Monitoring functions #####
+ ===============================================================================
+
+    *** VBAT and Temperature supervision ***
+    ========================================
+    [..]
+      (+) The VBAT battery voltage supply can be monitored by comparing it with
+          two threshold levels: VBAThigh and VBATlow. VBATH flag and VBATL flags
+          in the PWR control register 2 (PWR_CR2), indicate if VBAT is higher or
+          lower than the threshold.
+      (+) The temperature can be monitored by comparing it with two threshold
+          levels, TEMPhigh and TEMPlow. TEMPH and TEMPL flags, in the PWR
+          control register 2 (PWR_CR2), indicate whether the device temperature
+          is higher or lower than the threshold.
+      (+) The VBAT and the temperature monitoring is enabled by
+          HAL_PWREx_EnableMonitoring() function and disabled by
+          HAL_PWREx_DisableMonitoring() function.
+      (+) The HAL_PWREx_GetVBATLevel() function returns the VBAT level which can
+          be : PWR_VBAT_BELOW_LOW_THRESHOLD or PWR_VBAT_ABOVE_HIGH_THRESHOLD or
+          PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD.
+      (+) The HAL_PWREx_GetTemperatureLevel() function returns the Temperature
+          level which can be :
+          PWR_TEMP_BELOW_LOW_THRESHOLD or PWR_TEMP_ABOVE_HIGH_THRESHOLD or
+          PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD.
+
+    *** AVD configuration ***
+    =========================
+    [..]
+      (+) The AVD is used to monitor the VDDA power supply by comparing it to a
+          threshold selected by the AVD Level (ALS[3:0] bits in the PWR_CR1
+          register).
+      (+) A AVDO flag is available to indicate if VDDA is higher or lower
+          than the AVD threshold. This event is internally connected to the EXTI
+          line 16 to generate an interrupt if enabled.
+          It is configurable through __HAL_PWR_AVD_EXTI_ENABLE_IT() macro.
+      (+) The AVD is stopped in System Standby mode.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Enable the VBAT and temperature monitoring.
+  * @retval HAL status.
+  */
+void HAL_PWREx_EnableMonitoring (void)
+{
+  /* Enable the VBAT and Temperature monitoring */
+  SET_BIT (PWR->CR2, PWR_CR2_MONEN);
+}
+
+/**
+  * @brief Disable the VBAT and temperature monitoring.
+  * @retval HAL status.
+  */
+void HAL_PWREx_DisableMonitoring (void)
+{
+  /* Disable the VBAT and Temperature monitoring */
+  CLEAR_BIT (PWR->CR2, PWR_CR2_MONEN);
+}
+
+/**
+  * @brief Indicate whether the junction temperature is between, above or below
+  *        the thresholds.
+  * @retval Temperature level.
+  */
+uint32_t HAL_PWREx_GetTemperatureLevel (void)
+{
+  uint32_t tempLevel, regValue;
+
+  /* Read the temperature flags */
+  regValue = READ_BIT (PWR->CR2, (PWR_CR2_TEMPH | PWR_CR2_TEMPL));
+
+  /* Check if the temperature is below the threshold */
+  if (regValue == PWR_CR2_TEMPL)
+  {
+    tempLevel = PWR_TEMP_BELOW_LOW_THRESHOLD;
+  }
+  /* Check if the temperature is above the threshold */
+  else if (regValue == PWR_CR2_TEMPH)
+  {
+    tempLevel = PWR_TEMP_ABOVE_HIGH_THRESHOLD;
+  }
+  /* The temperature is between the thresholds */
+  else
+  {
+    tempLevel = PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD;
+  }
+
+  return tempLevel;
+}
+
+/**
+  * @brief Indicate whether the Battery voltage level is between, above or below
+  *        the thresholds.
+  * @retval VBAT level.
+  */
+uint32_t HAL_PWREx_GetVBATLevel (void)
+{
+  uint32_t VBATLevel, regValue;
+
+  /* Read the VBAT flags */
+  regValue = READ_BIT (PWR->CR2, (PWR_CR2_VBATH | PWR_CR2_VBATL));
+
+  /* Check if the VBAT is below the threshold */
+  if (regValue == PWR_CR2_VBATL)
+  {
+    VBATLevel = PWR_VBAT_BELOW_LOW_THRESHOLD;
+  }
+  /* Check if the VBAT is above the threshold */
+  else if (regValue == PWR_CR2_VBATH)
+  {
+    VBATLevel = PWR_VBAT_ABOVE_HIGH_THRESHOLD;
+  }
+  /* The VBAT is between the thresholds */
+  else
+  {
+    VBATLevel = PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD;
+  }
+
+  return VBATLevel;
+}
+
+#if defined (PWR_CSR1_MMCVDO)
+/**
+  * @brief Get the VDDMMC voltage level.
+  * @retval The VDDMMC voltage level.
+  */
+PWREx_MMC_VoltageLevel HAL_PWREx_GetMMCVoltage (void)
+{
+  PWREx_MMC_VoltageLevel mmc_voltage;
+
+  /* Check voltage detector output on VDDMMC value */
+  if ((PWR->CSR1 & PWR_CSR1_MMCVDO_Msk) == 0U)
+  {
+    mmc_voltage = PWR_MMC_VOLTAGE_BELOW_1V2;
+  }
+  else
+  {
+    mmc_voltage = PWR_MMC_VOLTAGE_EQUAL_ABOVE_1V2;
+  }
+
+  return mmc_voltage;
+}
+#endif /* defined (PWR_CSR1_MMCVDO) */
+
+/**
+  * @brief  Configure the event mode and the voltage threshold detected by the
+  *         Analog Voltage Detector (AVD).
+  * @param  sConfigAVD : Pointer to an PWREx_AVDTypeDef structure that contains
+  *                      the configuration information for the AVD.
+  * @note   Refer to the electrical characteristics of your device datasheet for
+  *         more details about the voltage threshold corresponding to each
+  *         detection level.
+  * @note   For dual core devices, please ensure to configure the EXTI lines for
+  *         the different Cortex-Mx through PWR_Exported_Macro provided by this
+  *         driver. All combination are allowed: wake up only Cortex-M7, wake up
+  *         only Cortex-M4 and wake up Cortex-M7 and Cortex-M4.
+  * @retval None.
+  */
+void HAL_PWREx_ConfigAVD (PWREx_AVDTypeDef *sConfigAVD)
+{
+  /* Check the parameters */
+  assert_param (IS_PWR_AVD_LEVEL (sConfigAVD->AVDLevel));
+  assert_param (IS_PWR_AVD_MODE (sConfigAVD->Mode));
+
+  /* Set the ALS[18:17] bits according to AVDLevel value */
+  MODIFY_REG (PWR->CR1, PWR_CR1_ALS, sConfigAVD->AVDLevel);
+
+  /* Clear any previous config */
+#if !defined (DUAL_CORE)
+  __HAL_PWR_AVD_EXTI_DISABLE_EVENT ();
+  __HAL_PWR_AVD_EXTI_DISABLE_IT ();
+#endif /* !defined (DUAL_CORE) */
+
+  __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE ();
+  __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE ();
+
+#if !defined (DUAL_CORE)
+  /* Configure the interrupt mode */
+  if ((sConfigAVD->Mode & AVD_MODE_IT) == AVD_MODE_IT)
+  {
+    __HAL_PWR_AVD_EXTI_ENABLE_IT ();
+  }
+
+  /* Configure the event mode */
+  if ((sConfigAVD->Mode & AVD_MODE_EVT) == AVD_MODE_EVT)
+  {
+    __HAL_PWR_AVD_EXTI_ENABLE_EVENT ();
+  }
+#endif /* !defined (DUAL_CORE) */
+
+  /* Rising edge configuration */
+  if ((sConfigAVD->Mode & AVD_RISING_EDGE) == AVD_RISING_EDGE)
+  {
+    __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE ();
+  }
+
+  /* Falling edge configuration */
+  if ((sConfigAVD->Mode & AVD_FALLING_EDGE) == AVD_FALLING_EDGE)
+  {
+    __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE ();
+  }
+}
+
+/**
+  * @brief Enable the Analog Voltage Detector (AVD).
+  * @retval None.
+  */
+void HAL_PWREx_EnableAVD (void)
+{
+  /* Enable the Analog Voltage Detector */
+  SET_BIT (PWR->CR1, PWR_CR1_AVDEN);
+}
+
+/**
+  * @brief Disable the Analog Voltage Detector(AVD).
+  * @retval None.
+  */
+void HAL_PWREx_DisableAVD (void)
+{
+  /* Disable the Analog Voltage Detector */
+  CLEAR_BIT (PWR->CR1, PWR_CR1_AVDEN);
+}
+
+/**
+  * @brief  This function handles the PWR PVD/AVD interrupt request.
+  * @note   This API should be called under the PVD_AVD_IRQHandler().
+  * @retval None
+  */
+void HAL_PWREx_PVD_AVD_IRQHandler (void)
+{
+  /* Check if the Programmable Voltage Detector is enabled (PVD) */
+  if(READ_BIT (PWR->CR1, PWR_CR1_PVDEN) != 0U)
+  {
+#if defined (DUAL_CORE)
+    if (HAL_GetCurrentCPUID () == CM7_CPUID)
+#endif /* defined (DUAL_CORE) */
+    {
+      /* Check PWR D1/CD EXTI flag */
+      if(__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U)
+      {
+        /* PWR PVD interrupt user callback */
+        HAL_PWR_PVDCallback ();
+
+        /* Clear PWR EXTI D1/CD pending bit */
+        __HAL_PWR_PVD_EXTI_CLEAR_FLAG ();
+      }
+    }
+#if defined (DUAL_CORE)
+    else
+    {
+      /* Check PWR EXTI D2 flag */
+      if (__HAL_PWR_PVD_EXTID2_GET_FLAG () != 0U)
+      {
+        /* PWR PVD interrupt user callback */
+        HAL_PWR_PVDCallback ();
+
+        /* Clear PWR EXTI D2 pending bit */
+        __HAL_PWR_PVD_EXTID2_CLEAR_FLAG();
+      }
+    }
+#endif /* defined (DUAL_CORE) */
+  }
+
+  /* Check if the Analog Voltage Detector is enabled (AVD) */
+  if (READ_BIT (PWR->CR1, PWR_CR1_AVDEN) != 0U)
+  {
+#if defined (DUAL_CORE)
+    if (HAL_GetCurrentCPUID () == CM7_CPUID)
+#endif /* defined (DUAL_CORE) */
+    {
+      /* Check PWR EXTI D1/CD flag */
+      if (__HAL_PWR_AVD_EXTI_GET_FLAG () != 0U)
+      {
+        /* PWR AVD interrupt user callback */
+        HAL_PWREx_AVDCallback ();
+
+        /* Clear PWR EXTI D1/CD pending bit */
+        __HAL_PWR_AVD_EXTI_CLEAR_FLAG ();
+      }
+    }
+#if defined (DUAL_CORE)
+    else
+    {
+      /* Check PWR EXTI D2 flag */
+      if (__HAL_PWR_AVD_EXTID2_GET_FLAG () != 0U)
+      {
+        /* PWR AVD interrupt user callback */
+        HAL_PWREx_AVDCallback ();
+
+        /* Clear PWR EXTI D2 pending bit */
+        __HAL_PWR_AVD_EXTID2_CLEAR_FLAG ();
+      }
+    }
+#endif /* defined (DUAL_CORE) */
+  }
+}
+
+/**
+  * @brief PWR AVD interrupt callback.
+  * @retval None.
+  */
+__weak void HAL_PWREx_AVDCallback (void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PWR_AVDCallback can be implemented in the user file
+  */
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c
new file mode 100644
index 00000000..7d73fa57
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c
@@ -0,0 +1,1775 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_rcc.c
+  * @author  MCD Application Team
+  * @brief   RCC HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Reset and Clock Control (RCC) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions
+  *
+  @verbatim
+  ==============================================================================
+                      ##### RCC specific features #####
+  ==============================================================================
+    [..]
+      After reset the device is running from Internal High Speed oscillator
+      (HSI 64MHz) with Flash 0 wait state,and all peripherals are off except
+      internal SRAM, Flash, JTAG and PWR
+      (+) There is no pre-scaler on High speed (AHB) and Low speed (APB) buses;
+          all peripherals mapped on these buses are running at HSI speed.
+      (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
+      (+) All GPIOs are in analogue mode , except the JTAG pins which
+          are assigned to be used for debug purpose.
+
+    [..]
+      Once the device started from reset, the user application has to:
+      (+) Configure the clock source to be used to drive the System clock
+          (if the application needs higher frequency/performance)
+      (+) Configure the System clock frequency and Flash settings
+      (+) Configure the AHB and APB buses pre-scalers
+      (+) Enable the clock for the peripheral(s) to be used
+      (+) Configure the clock kernel source(s) for peripherals which clocks are not
+          derived from the System clock through :RCC_D1CCIPR,RCC_D2CCIP1R,RCC_D2CCIP2R
+          and RCC_D3CCIPR registers
+
+                      ##### RCC Limitations #####
+  ==============================================================================
+    [..]
+      A delay between an RCC peripheral clock enable and the effective peripheral
+      enabling should be taken into account in order to manage the peripheral read/write
+      from/to registers.
+      (+) This delay depends on the peripheral mapping.
+      (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
+          after the clock enable bit is set on the hardware register
+      (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
+          after the clock enable bit is set on the hardware register
+
+    [..]
+      Implemented Workaround:
+      (+) For AHB & APB peripherals, a dummy read to the peripheral register has been
+          inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
+
+  @endverbatim
+ ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup RCC  RCC
+  * @brief RCC HAL module driver
+  * @{
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup RCC_Private_Macros RCC Private Macros
+  * @{
+  */
+#define MCO1_CLK_ENABLE()     __HAL_RCC_GPIOA_CLK_ENABLE()
+#define MCO1_GPIO_PORT        GPIOA
+#define MCO1_PIN              GPIO_PIN_8
+
+#define MCO2_CLK_ENABLE()      __HAL_RCC_GPIOC_CLK_ENABLE()
+#define MCO2_GPIO_PORT         GPIOC
+#define MCO2_PIN               GPIO_PIN_9
+
+/**
+  * @}
+  */
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup RCC_Private_Variables RCC Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Functions RCC Exported Functions
+  * @{
+  */
+
+/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+           ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]
+      This section provides functions allowing to configure the internal/external oscillators
+      (HSE, HSI, LSE,CSI, LSI,HSI48, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB3, AHB1
+       AHB2,AHB4,APB3, APB1L, APB1H, APB2, and APB4).
+
+    [..] Internal/external clock and PLL configuration
+         (#) HSI (high-speed internal), 64 MHz factory-trimmed RC used directly or through
+             the PLL as System clock source.
+         (#) CSI is a low-power RC oscillator which can be used directly as system clock, peripheral
+             clock, or PLL input.But even with frequency calibration, is less accurate than an
+             external crystal oscillator or ceramic resonator.
+         (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
+             clock source.
+
+         (#) HSE (high-speed external), 4 to 48 MHz crystal oscillator used directly or
+             through the PLL as System clock source. Can be used also as RTC clock source.
+
+         (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
+
+         (#) PLL , The RCC features three independent PLLs (clocked by HSI , HSE or CSI),
+             featuring three different output clocks and able  to work either in integer or Fractional mode.
+           (++) A main PLL, PLL1, which is generally used to provide clocks to the CPU
+                and to some peripherals.
+           (++) Two dedicated PLLs, PLL2 and PLL3, which are used to generate the kernel clock for peripherals.
+
+
+         (#) CSS (Clock security system), once enabled and if a HSE clock failure occurs
+            (HSE used directly or through PLL as System clock source), the System clock
+             is automatically switched to HSI and an interrupt is generated if enabled.
+             The interrupt is linked to the Cortex-M NMI (Non-Mask-able Interrupt)
+             exception vector.
+
+         (#) MCO1 (micro controller clock output), used to output HSI, LSE, HSE, PLL1(PLL1_Q)
+             or HSI48 clock (through a configurable pre-scaler) on PA8 pin.
+
+         (#) MCO2 (micro controller clock output), used to output HSE, PLL2(PLL2_P), SYSCLK,
+             LSI, CSI, or PLL1(PLL1_P) clock (through a configurable pre-scaler) on PC9 pin.
+
+    [..] System, AHB and APB buses clocks configuration
+         (#) Several clock sources can be used to drive the System clock (SYSCLK): CSI,HSI,
+             HSE and PLL.
+             The AHB clock (HCLK) is derived from System core clock through configurable
+             pre-scaler and used to clock the CPU, memory and peripherals mapped
+             on AHB and APB bus of the 3 Domains (D1, D2, D3)* through configurable pre-scalers
+             and used to clock the peripherals mapped on these buses. You can use
+             "HAL_RCC_GetSysClockFreq()" function to retrieve system clock frequency.
+
+         -@- All the peripheral clocks are derived from the System clock (SYSCLK) except those
+             with dual clock domain where kernel source clock could be selected through
+             RCC_D1CCIPR,RCC_D2CCIP1R,RCC_D2CCIP2R and RCC_D3CCIPR registers.
+
+     (*) : 2 Domains (CD and SRD) for stm32h7a3xx and stm32h7b3xx family lines.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Resets the RCC clock configuration to the default reset state.
+  * @note   The default reset state of the clock configuration is given below:
+  *            - HSI ON and used as system clock source
+  *            - HSE, PLL1, PLL2 and PLL3 OFF
+  *            - AHB, APB Bus pre-scaler set to 1.
+  *            - CSS, MCO1 and MCO2 OFF
+  *            - All interrupts disabled
+  * @note   This function doesn't modify the configuration of the
+  *            - Peripheral clocks
+  *            - LSI, LSE and RTC clocks
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCC_DeInit(void)
+{
+  uint32_t tickstart;
+
+        /* Increasing the CPU frequency */
+  if(FLASH_LATENCY_DEFAULT  > __HAL_FLASH_GET_LATENCY())
+  {
+    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+    __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT);
+
+    /* Check that the new number of wait states is taken into account to access the Flash
+    memory by reading the FLASH_ACR register */
+    if(__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT)
+    {
+      return HAL_ERROR;
+    }
+
+  }
+
+
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Set HSION bit */
+  SET_BIT(RCC->CR, RCC_CR_HSION);
+
+  /* Wait till HSI is ready */
+  while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Set HSITRIM[6:0] bits to the reset value */
+  SET_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM_6);
+
+  /* Reset CFGR register */
+  CLEAR_REG(RCC->CFGR);
+
+  /* Update the SystemCoreClock and SystemD2Clock global variables */
+  SystemCoreClock = HSI_VALUE;
+  SystemD2Clock = HSI_VALUE;
+
+  /* Adapt Systick interrupt period */
+  if(HAL_InitTick(uwTickPrio) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait till clock switch is ready */
+  while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Reset CSION, CSIKERON, HSEON, HSI48ON, HSECSSON, HSIDIV bits */
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSIKERON| RCC_CR_HSIDIV| RCC_CR_HSIDIVF| RCC_CR_CSION | RCC_CR_CSIKERON  \
+  | RCC_CR_HSI48ON | RCC_CR_CSSHSEON);
+
+  /* Wait till HSE is disabled */
+  while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Clear PLLON bit */
+  CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON);
+
+  /* Wait till PLL is disabled */
+  while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) != 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Reset PLL2ON bit */
+  CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
+
+  /* Wait till PLL2 is disabled */
+  while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Reset PLL3 bit */
+  CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
+
+  /* Wait till PLL3 is disabled */
+  while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+#if defined(RCC_D1CFGR_HPRE)
+  /* Reset D1CFGR register */
+  CLEAR_REG(RCC->D1CFGR);
+
+  /* Reset D2CFGR register */
+  CLEAR_REG(RCC->D2CFGR);
+
+  /* Reset D3CFGR register */
+  CLEAR_REG(RCC->D3CFGR);
+#else
+  /* Reset CDCFGR1 register */
+  CLEAR_REG(RCC->CDCFGR1);
+
+  /* Reset CDCFGR2 register */
+  CLEAR_REG(RCC->CDCFGR2);
+
+  /* Reset SRDCFGR register */
+  CLEAR_REG(RCC->SRDCFGR);
+#endif
+
+  /* Reset PLLCKSELR register to default value */
+  RCC->PLLCKSELR= RCC_PLLCKSELR_DIVM1_5|RCC_PLLCKSELR_DIVM2_5|RCC_PLLCKSELR_DIVM3_5;
+
+  /* Reset PLLCFGR register to default value */
+  WRITE_REG(RCC->PLLCFGR, 0x01FF0000U);
+
+  /* Reset PLL1DIVR register to default value */
+  WRITE_REG(RCC->PLL1DIVR,0x01010280U);
+
+  /* Reset PLL1FRACR register */
+  CLEAR_REG(RCC->PLL1FRACR);
+
+  /* Reset PLL2DIVR register to default value */
+  WRITE_REG(RCC->PLL2DIVR,0x01010280U);
+
+  /* Reset PLL2FRACR register */
+  CLEAR_REG(RCC->PLL2FRACR);
+
+  /* Reset PLL3DIVR register to default value */
+  WRITE_REG(RCC->PLL3DIVR,0x01010280U);
+
+  /* Reset PLL3FRACR register */
+  CLEAR_REG(RCC->PLL3FRACR);
+
+  /* Reset HSEBYP bit */
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
+
+  /* Disable all interrupts */
+  CLEAR_REG(RCC->CIER);
+
+  /* Clear all interrupts flags */
+  WRITE_REG(RCC->CICR,0xFFFFFFFFU);
+
+  /* Reset all RSR flags */
+  SET_BIT(RCC->RSR, RCC_RSR_RMVF);
+
+      /* Decreasing the number of wait states because of lower CPU frequency */
+  if(FLASH_LATENCY_DEFAULT  < __HAL_FLASH_GET_LATENCY())
+  {
+    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+    __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT);
+
+    /* Check that the new number of wait states is taken into account to access the Flash
+    memory by reading the FLASH_ACR register */
+    if(__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT)
+    {
+      return HAL_ERROR;
+    }
+
+}
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the RCC Oscillators according to the specified parameters in the
+  *         RCC_OscInitTypeDef.
+  * @param  RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
+  *         contains the configuration information for the RCC Oscillators.
+  * @note   The PLL is not disabled when used as system clock.
+  * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
+  *         supported by this function. User should request a transition to LSE Off
+  *         first and then LSE On or LSE Bypass.
+  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
+  *         supported by this function. User should request a transition to HSE Off
+  *         first and then HSE On or HSE Bypass.
+  * @retval HAL status
+  */
+__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
+{
+  uint32_t tickstart;
+  uint32_t temp1_pllckcfg, temp2_pllckcfg;
+
+    /* Check Null pointer */
+  if(RCC_OscInitStruct == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
+  /*------------------------------- HSE Configuration ------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
+
+    const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
+    const uint32_t temp_pllckselr = RCC->PLLCKSELR;
+    /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
+    if((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE)))
+    {
+      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
+      {
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Set the new HSE configuration ---------------------------------------*/
+      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
+
+      /* Check the HSE State */
+      if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
+      {
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSE is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
+        {
+          if((uint32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+      else
+      {
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSE is disabled */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
+        {
+          if((uint32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+  }
+  /*----------------------------- HSI Configuration --------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
+    assert_param(IS_RCC_HSICALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
+
+    /* When the HSI is used as system clock it will not be disabled */
+    const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
+    const uint32_t temp_pllckselr = RCC->PLLCKSELR;
+    if((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI)))
+    {
+      /* When HSI is used as system clock it will not be disabled */
+      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
+      {
+        return HAL_ERROR;
+      }
+      /* Otherwise, just the calibration is allowed */
+      else
+      {
+        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+      }
+    }
+
+    else
+    {
+      /* Check the HSI State */
+      if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
+      {
+     /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */
+        __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSI is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
+        {
+          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+
+        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+      }
+      else
+      {
+        /* Disable the Internal High Speed oscillator (HSI). */
+        __HAL_RCC_HSI_DISABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSI is disabled */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
+        {
+          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+  }
+  /*----------------------------- CSI Configuration --------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState));
+    assert_param(IS_RCC_CSICALIBRATION_VALUE(RCC_OscInitStruct->CSICalibrationValue));
+
+    /* When the CSI is used as system clock it will not disabled */
+    const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
+    const uint32_t temp_pllckselr = RCC->PLLCKSELR;
+    if((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI)))
+    {
+      /* When CSI is used as system clock it will not disabled */
+      if((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON))
+      {
+        return HAL_ERROR;
+      }
+      /* Otherwise, just the calibration is allowed */
+      else
+      {
+        /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/
+        __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
+      }
+    }
+    else
+    {
+      /* Check the CSI State */
+      if((RCC_OscInitStruct->CSIState)!= RCC_CSI_OFF)
+      {
+        /* Enable the Internal High Speed oscillator (CSI). */
+        __HAL_RCC_CSI_ENABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till CSI is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)
+        {
+          if((HAL_GetTick() - tickstart ) > CSI_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+
+        /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/
+        __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
+      }
+      else
+      {
+        /* Disable the Internal High Speed oscillator (CSI). */
+        __HAL_RCC_CSI_DISABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till CSI is disabled */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U)
+        {
+          if((HAL_GetTick() - tickstart ) > CSI_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+  }
+  /*------------------------------ LSI Configuration -------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
+
+    /* Check the LSI State */
+    if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
+    {
+      /* Enable the Internal Low Speed oscillator (LSI). */
+      __HAL_RCC_LSI_ENABLE();
+
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSI is ready */
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
+      {
+        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    else
+    {
+      /* Disable the Internal Low Speed oscillator (LSI). */
+      __HAL_RCC_LSI_DISABLE();
+
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSI is ready */
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
+      {
+        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /*------------------------------ HSI48 Configuration -------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
+
+    /* Check the HSI48 State */
+    if((RCC_OscInitStruct->HSI48State)!= RCC_HSI48_OFF)
+    {
+      /* Enable the Internal Low Speed oscillator (HSI48). */
+      __HAL_RCC_HSI48_ENABLE();
+
+      /* Get time-out */
+      tickstart = HAL_GetTick();
+
+      /* Wait till HSI48 is ready */
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U)
+      {
+        if((HAL_GetTick() - tickstart ) > HSI48_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    else
+    {
+      /* Disable the Internal Low Speed oscillator (HSI48). */
+      __HAL_RCC_HSI48_DISABLE();
+
+      /* Get time-out */
+      tickstart = HAL_GetTick();
+
+      /* Wait till HSI48 is ready */
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U)
+      {
+        if((HAL_GetTick() - tickstart ) > HSI48_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  /*------------------------------ LSE Configuration -------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
+
+    /* Enable write access to Backup domain */
+    PWR->CR1 |= PWR_CR1_DBP;
+
+    /* Wait for Backup domain Write protection disable */
+    tickstart = HAL_GetTick();
+
+    while((PWR->CR1 & PWR_CR1_DBP) == 0U)
+    {
+      if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Set the new LSE configuration -----------------------------------------*/
+    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
+    /* Check the LSE State */
+    if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
+    {
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSE is ready */
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
+      {
+        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    else
+    {
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSE is disabled */
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
+      {
+        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  /*-------------------------------- PLL Configuration -----------------------*/
+  /* Check the parameters */
+  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
+  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
+  {
+    /* Check if the PLL is used as system clock or not */
+    if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1)
+    {
+      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
+      {
+        /* Check the parameters */
+        assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
+        assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
+        assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
+        assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
+        assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
+        assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
+        assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN));
+
+        /* Disable the main PLL. */
+        __HAL_RCC_PLL_DISABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till PLL is disabled */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
+        {
+          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+
+        /* Configure the main PLL clock source, multiplication and division factors. */
+        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
+                             RCC_OscInitStruct->PLL.PLLM,
+                             RCC_OscInitStruct->PLL.PLLN,
+                             RCC_OscInitStruct->PLL.PLLP,
+                             RCC_OscInitStruct->PLL.PLLQ,
+                             RCC_OscInitStruct->PLL.PLLR);
+
+         /* Disable PLLFRACN . */
+         __HAL_RCC_PLLFRACN_DISABLE();
+
+         /* Configure PLL PLL1FRACN */
+         __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN);
+
+        /* Select PLL1 input reference frequency range: VCI */
+        __HAL_RCC_PLL_VCIRANGE(RCC_OscInitStruct->PLL.PLLRGE) ;
+
+        /* Select PLL1 output frequency range : VCO */
+        __HAL_RCC_PLL_VCORANGE(RCC_OscInitStruct->PLL.PLLVCOSEL) ;
+
+        /* Enable PLL System Clock output. */
+         __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
+
+        /* Enable PLL1Q Clock output. */
+         __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+        /* Enable PLL1R  Clock output. */
+         __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR);
+
+        /* Enable PLL1FRACN . */
+         __HAL_RCC_PLLFRACN_ENABLE();
+
+        /* Enable the main PLL. */
+        __HAL_RCC_PLL_ENABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till PLL is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
+        {
+          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+      else
+      {
+        /* Disable the main PLL. */
+        __HAL_RCC_PLL_DISABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till PLL is disabled */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
+        {
+          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+    else
+    {
+      /* Do not return HAL_ERROR if request repeats the current configuration */
+      temp1_pllckcfg = RCC->PLLCKSELR;
+      temp2_pllckcfg = RCC->PLL1DIVR;
+      if(((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
+	 (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
+         ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) ||
+         (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) ||
+         ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) ||
+         ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) ||
+         ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U)))
+      {
+        return HAL_ERROR;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CPU, AHB and APB buses clocks according to the specified
+  *         parameters in the RCC_ClkInitStruct.
+  * @param  RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
+  *         contains the configuration information for the RCC peripheral.
+  * @param  FLatency: FLASH Latency, this parameter depend on device selected
+  *
+  * @note   The SystemCoreClock CMSIS variable is used to store System Core Clock Frequency
+  *         and updated by HAL_InitTick() function called within this function
+  *
+  * @note   The HSI is used (enabled by hardware) as system clock source after
+  *         start-up from Reset, wake-up from STOP and STANDBY mode, or in case
+  *         of failure of the HSE used directly or indirectly as system clock
+  *         (if the Clock Security System CSS is enabled).
+  *
+  * @note   A switch from one clock source to another occurs only if the target
+  *         clock source is ready (clock stable after start-up delay or PLL locked).
+  *         If a clock source which is not yet ready is selected, the switch will
+  *         occur when the clock source will be ready.
+  *         You can use HAL_RCC_GetClockConfig() function to know which clock is
+  *         currently used as system clock source.
+  * @note   Depending on the device voltage range, the software has to set correctly
+  *         D1CPRE[3:0] bits to ensure that  Domain1 core clock not exceed the maximum allowed frequency
+  *         (for more details refer to section above "Initialization/de-initialization functions")
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
+{
+  HAL_StatusTypeDef halstatus;
+  uint32_t tickstart;
+  uint32_t common_system_clock;
+
+   /* Check Null pointer */
+  if(RCC_ClkInitStruct == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
+  assert_param(IS_FLASH_LATENCY(FLatency));
+
+  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
+    must be correctly programmed according to the frequency of the CPU clock
+    (HCLK) and the supply voltage of the device. */
+
+  /* Increasing the CPU frequency */
+  if(FLatency > __HAL_FLASH_GET_LATENCY())
+  {
+    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+    __HAL_FLASH_SET_LATENCY(FLatency);
+
+    /* Check that the new number of wait states is taken into account to access the Flash
+    memory by reading the FLASH_ACR register */
+    if(__HAL_FLASH_GET_LATENCY() != FLatency)
+    {
+      return HAL_ERROR;
+    }
+
+  }
+
+  /* Increasing the BUS frequency divider */
+  /*-------------------------- D1PCLK1/CDPCLK1 Configuration ---------------------------*/
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1)
+  {
+#if defined (RCC_D1CFGR_D1PPRE)
+    if((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_D1PPRE))
+    {
+      assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider));
+      MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider);
+    }
+#else
+    if((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE))
+    {
+      assert_param(IS_RCC_CDPCLK1(RCC_ClkInitStruct->APB3CLKDivider));
+      MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, RCC_ClkInitStruct->APB3CLKDivider);
+    }
+#endif
+  }
+
+  /*-------------------------- PCLK1 Configuration ---------------------------*/
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+  {
+#if defined (RCC_D2CFGR_D2PPRE1)
+    if((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1))
+    {
+      assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
+      MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
+    }
+#else
+    if((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1))
+    {
+      assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
+      MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
+  }
+#endif
+    }
+  /*-------------------------- PCLK2 Configuration ---------------------------*/
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+  {
+#if defined(RCC_D2CFGR_D2PPRE2)
+    if((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2))
+    {
+      assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
+      MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
+    }
+#else
+     if((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2))
+    {
+      assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
+      MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
+    }
+#endif
+  }
+
+  /*-------------------------- D3PCLK1 Configuration ---------------------------*/
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1)
+  {
+#if defined(RCC_D3CFGR_D3PPRE)
+    if((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->D3CFGR & RCC_D3CFGR_D3PPRE))
+    {
+      assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider));
+      MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider) );
+    }
+#else
+    if((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE))
+    {
+      assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider));
+      MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, (RCC_ClkInitStruct->APB4CLKDivider) );
+    }
+#endif
+  }
+
+   /*-------------------------- HCLK Configuration --------------------------*/
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+  {
+#if defined (RCC_D1CFGR_HPRE)
+    if((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_HPRE))
+    {
+      /* Set the new HCLK clock divider */
+      assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+      MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+    }
+#else
+        if((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->CDCFGR1 & RCC_CDCFGR1_HPRE))
+    {
+      /* Set the new HCLK clock divider */
+      assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+      MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+    }
+#endif
+  }
+
+    /*------------------------- SYSCLK Configuration -------------------------*/
+    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
+    {
+      assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider));
+      assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
+#if defined(RCC_D1CFGR_D1CPRE)
+      MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider);
+#else
+      MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, RCC_ClkInitStruct->SYSCLKDivider);
+#endif
+      /* HSE is selected as System Clock Source */
+      if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+      {
+        /* Check the HSE ready flag */
+        if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
+        {
+          return HAL_ERROR;
+        }
+      }
+      /* PLL is selected as System Clock Source */
+      else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+      {
+        /* Check the PLL ready flag */
+        if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
+        {
+          return HAL_ERROR;
+        }
+      }
+      /* CSI is selected as System Clock Source */
+      else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI)
+      {
+        /* Check the PLL ready flag */
+        if(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)
+        {
+          return HAL_ERROR;
+        }
+      }
+      /* HSI is selected as System Clock Source */
+      else
+      {
+        /* Check the HSI ready flag */
+        if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
+        {
+          return HAL_ERROR;
+        }
+      }
+      MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
+
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+        while (__HAL_RCC_GET_SYSCLK_SOURCE() !=  (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
+        {
+          if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+
+    }
+
+    /* Decreasing the BUS frequency divider */
+   /*-------------------------- HCLK Configuration --------------------------*/
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+  {
+#if defined(RCC_D1CFGR_HPRE)
+    if((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_HPRE))
+    {
+      /* Set the new HCLK clock divider */
+      assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+      MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+    }
+#else
+    if((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->CDCFGR1 & RCC_CDCFGR1_HPRE))
+    {
+      /* Set the new HCLK clock divider */
+      assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+      MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+    }
+#endif
+  }
+
+  /* Decreasing the number of wait states because of lower CPU frequency */
+  if(FLatency < __HAL_FLASH_GET_LATENCY())
+  {
+    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+    __HAL_FLASH_SET_LATENCY(FLatency);
+
+    /* Check that the new number of wait states is taken into account to access the Flash
+    memory by reading the FLASH_ACR register */
+    if(__HAL_FLASH_GET_LATENCY() != FLatency)
+    {
+      return HAL_ERROR;
+    }
+ }
+
+  /*-------------------------- D1PCLK1/CDPCLK Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1)
+ {
+#if defined(RCC_D1CFGR_D1PPRE)
+   if((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_D1PPRE))
+   {
+     assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider));
+     MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider);
+   }
+#else
+   if((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE))
+   {
+     assert_param(IS_RCC_CDPCLK1(RCC_ClkInitStruct->APB3CLKDivider));
+     MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, RCC_ClkInitStruct->APB3CLKDivider);
+   }
+#endif
+ }
+
+  /*-------------------------- PCLK1 Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ {
+#if defined(RCC_D2CFGR_D2PPRE1)
+   if((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1))
+   {
+     assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
+     MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
+   }
+#else
+   if((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1))
+   {
+     assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
+     MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
+   }
+#endif
+ }
+
+  /*-------------------------- PCLK2 Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+ {
+#if defined (RCC_D2CFGR_D2PPRE2)
+   if((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2))
+   {
+     assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
+     MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
+   }
+#else
+   if((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2))
+   {
+     assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
+     MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
+   }
+#endif
+ }
+
+  /*-------------------------- D3PCLK1/SRDPCLK1 Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1)
+ {
+#if defined(RCC_D3CFGR_D3PPRE)
+   if((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->D3CFGR & RCC_D3CFGR_D3PPRE))
+   {
+     assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider));
+     MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider) );
+   }
+#else
+   if((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE))
+   {
+     assert_param(IS_RCC_SRDPCLK1(RCC_ClkInitStruct->APB4CLKDivider));
+     MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, (RCC_ClkInitStruct->APB4CLKDivider) );
+   }
+#endif
+ }
+
+  /* Update the SystemCoreClock global variable */
+#if defined(RCC_D1CFGR_D1CPRE)
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
+#else
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
+#endif
+
+#if defined(RCC_D1CFGR_HPRE)
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+#else
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+#endif
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  SystemCoreClock = SystemD2Clock;
+#else
+  SystemCoreClock = common_system_clock;
+#endif /* DUAL_CORE && CORE_CM4 */
+
+  /* Configure the source of time base considering new system clocks settings*/
+  halstatus = HAL_InitTick (uwTickPrio);
+
+  return halstatus;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Group2 Peripheral Control functions
+ *  @brief   RCC clocks control functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the RCC Clocks
+    frequencies.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
+  * @note   PA8/PC9 should be configured in alternate function mode.
+  * @param  RCC_MCOx: specifies the output direction for the clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
+  *            @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
+  * @param  RCC_MCOSource: specifies the clock source to output.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_PLL1QCLK:  PLL1Q clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_HSI48: HSI48 (48MHZ) selected as MCO1 source
+  *            @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_PLL2PCLK: PLL2P clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_PLLCLK:  PLL1P clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_CSICLK:  CSI clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_LSICLK:  LSI clock selected as MCO2 source
+  * @param  RCC_MCODiv: specifies the MCOx pre-scaler.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCODIV_1 up to RCC_MCODIV_15  : divider applied to MCOx clock
+  * @retval None
+  */
+void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
+{
+  GPIO_InitTypeDef GPIO_InitStruct;
+  /* Check the parameters */
+  assert_param(IS_RCC_MCO(RCC_MCOx));
+  assert_param(IS_RCC_MCODIV(RCC_MCODiv));
+  /* RCC_MCO1 */
+  if(RCC_MCOx == RCC_MCO1)
+  {
+    assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
+
+    /* MCO1 Clock Enable */
+    MCO1_CLK_ENABLE();
+
+    /* Configure the MCO1 pin in alternate function mode */
+    GPIO_InitStruct.Pin = MCO1_PIN;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
+    HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
+
+    /* Mask MCO1 and MCO1PRE[3:0] bits then Select MCO1 clock source and pre-scaler */
+    MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
+  }
+  else
+  {
+    assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
+
+    /* MCO2 Clock Enable */
+    MCO2_CLK_ENABLE();
+
+    /* Configure the MCO2 pin in alternate function mode */
+    GPIO_InitStruct.Pin = MCO2_PIN;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
+    HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
+
+    /* Mask MCO2 and MCO2PRE[3:0] bits then Select MCO2 clock source and pre-scaler */
+    MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 7U)));
+  }
+}
+
+/**
+  * @brief  Enables the Clock Security System.
+  * @note   If a failure is detected on the HSE oscillator clock, this oscillator
+  *         is automatically disabled and an interrupt is generated to inform the
+  *         software about the failure (Clock Security System Interrupt, CSSI),
+  *         allowing the MCU to perform rescue operations. The CSSI is linked to
+  *         the Cortex-M NMI (Non-Mask-able Interrupt) exception vector.
+  * @retval None
+  */
+void HAL_RCC_EnableCSS(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_CSSHSEON) ;
+}
+
+/**
+  * @brief  Disables the Clock Security System.
+  * @retval None
+  */
+void HAL_RCC_DisableCSS(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_CSSHSEON);
+}
+
+/**
+  * @brief  Returns the SYSCLK frequency
+  *
+  * @note   The system frequency computed by this function is not the real
+  *         frequency in the chip. It is calculated based on the predefined
+  *         constant and the selected clock source:
+  * @note     If SYSCLK source is CSI, function returns values based on CSI_VALUE(*)
+  * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
+  * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
+  * @note     If SYSCLK source is PLL, function returns values based on CSI_VALUE(*),
+  *           HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
+  * @note     (*) CSI_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value
+  *               4 MHz) but the real value may vary depending on the variations
+  *               in voltage and temperature.
+  * @note     (**) HSI_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value
+  *               64 MHz) but the real value may vary depending on the variations
+  *               in voltage and temperature.
+  * @note     (***) HSE_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value
+  *                25 MHz), user has to ensure that HSE_VALUE is same as the real
+  *                frequency of the crystal used. Otherwise, this function may
+  *                have wrong result.
+  *
+  * @note   The result of this function could be not correct when using fractional
+  *         value for HSE crystal.
+  *
+  * @note   This function can be used by the user application to compute the
+  *         baud rate for the communication peripherals or configure other parameters.
+  *
+  * @note   Each time SYSCLK changes, this function must be called to update the
+  *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
+  *
+  *
+  * @retval SYSCLK frequency
+  */
+uint32_t HAL_RCC_GetSysClockFreq(void)
+{
+  uint32_t pllp, pllsource, pllm, pllfracen, hsivalue;
+  float_t fracn1, pllvco;
+  uint32_t sysclockfreq;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+  case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */
+
+   if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+      {
+        sysclockfreq = (uint32_t) (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
+      }
+      else
+      {
+        sysclockfreq = (uint32_t) HSI_VALUE;
+      }
+
+    break;
+
+  case RCC_CFGR_SWS_CSI:  /* CSI used as system clock  source */
+    sysclockfreq = CSI_VALUE;
+    break;
+
+  case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
+    sysclockfreq = HSE_VALUE;
+    break;
+
+  case RCC_CFGR_SWS_PLL1:  /* PLL1 used as system clock  source */
+
+    /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
+    SYSCLK = PLL_VCO / PLLR
+    */
+    pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+    pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4)  ;
+    pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
+    fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
+
+    if (pllm != 0U)
+    {
+      switch (pllsource)
+      {
+      case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
+
+       if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+        {
+          hsivalue= (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
+          pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+        }
+        else
+        {
+          pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+        }
+        break;
+
+      case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
+        pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+        break;
+
+      case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
+        pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+        break;
+
+      default:
+        pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+        break;
+      }
+      pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
+      sysclockfreq =  (uint32_t)(float_t)(pllvco/(float_t)pllp);
+    }
+    else
+    {
+      sysclockfreq = 0U;
+    }
+    break;
+
+  default:
+    sysclockfreq = CSI_VALUE;
+    break;
+  }
+
+  return sysclockfreq;
+}
+
+
+/**
+  * @brief  Returns the HCLK frequency
+  * @note   Each time HCLK changes, this function must be called to update the
+  *         right HCLK value. Otherwise, any configuration based on this function will be incorrect.
+  *
+  * @note   The SystemD2Clock CMSIS variable is used to store System domain2 Clock Frequency
+  *         and updated within this function
+  * @retval HCLK frequency
+  */
+uint32_t HAL_RCC_GetHCLKFreq(void)
+{
+uint32_t common_system_clock;
+
+#if defined(RCC_D1CFGR_D1CPRE)
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
+#else
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU);
+#endif
+
+#if defined(RCC_D1CFGR_HPRE)
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+#else
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+#endif
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  SystemCoreClock = SystemD2Clock;
+#else
+  SystemCoreClock = common_system_clock;
+#endif /* DUAL_CORE && CORE_CM4 */
+
+  return SystemD2Clock;
+}
+
+
+/**
+  * @brief  Returns the PCLK1 frequency
+  * @note   Each time PCLK1 changes, this function must be called to update the
+  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
+  * @retval PCLK1 frequency
+  */
+uint32_t HAL_RCC_GetPCLK1Freq(void)
+{
+#if defined (RCC_D2CFGR_D2PPRE1)
+  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)>> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU));
+#else
+ /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1)>> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU));
+#endif
+}
+
+
+/**
+  * @brief  Returns the PCLK2 frequency
+  * @note   Each time PCLK2 changes, this function must be called to update the
+  *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
+  * @retval PCLK1 frequency
+  */
+uint32_t HAL_RCC_GetPCLK2Freq(void)
+{
+  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
+#if defined(RCC_D2CFGR_D2PPRE2)
+  return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)>> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU));
+#else
+  return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2)>> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU));
+#endif
+}
+
+/**
+  * @brief  Configures the RCC_OscInitStruct according to the internal
+  * RCC configuration registers.
+  * @param  RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
+  * will be configured.
+  * @retval None
+  */
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
+{
+  /* Set all possible values for the Oscillator type parameter ---------------*/
+  RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_CSI | \
+                                      RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI| RCC_OSCILLATORTYPE_HSI48;
+
+  /* Get the HSE configuration -----------------------------------------------*/
+#if defined(RCC_CR_HSEEXT)
+  if((RCC->CR &(RCC_CR_HSEBYP | RCC_CR_HSEEXT)) == RCC_CR_HSEBYP)
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
+  }
+  else if((RCC->CR &(RCC_CR_HSEBYP | RCC_CR_HSEEXT)) == (RCC_CR_HSEBYP | RCC_CR_HSEEXT))
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS_DIGITAL;
+  }
+  else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
+  }
+#else
+  if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
+  }
+  else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
+  }
+#endif /* RCC_CR_HSEEXT */
+
+   /* Get the CSI configuration -----------------------------------------------*/
+  if((RCC->CR &RCC_CR_CSION) == RCC_CR_CSION)
+  {
+    RCC_OscInitStruct->CSIState = RCC_CSI_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->CSIState = RCC_CSI_OFF;
+  }
+
+#if defined(RCC_VER_X)
+  if(HAL_GetREVID() <= REV_ID_Y)
+  {
+    RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk) >> HAL_RCC_REV_Y_CSITRIM_Pos);
+  }
+  else
+  {
+    RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
+  }
+#else
+ RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
+#endif /*RCC_VER_X*/
+
+  /* Get the HSI configuration -----------------------------------------------*/
+  if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
+  {
+    RCC_OscInitStruct->HSIState = RCC_HSI_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
+  }
+
+#if defined(RCC_VER_X)
+  if(HAL_GetREVID() <= REV_ID_Y)
+  {
+    RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk) >> HAL_RCC_REV_Y_HSITRIM_Pos);
+  }
+  else
+  {
+    RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
+  }
+#else
+    RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
+#endif /*RCC_VER_X*/
+
+  /* Get the LSE configuration -----------------------------------------------*/
+#if defined(RCC_BDCR_LSEEXT)
+  if((RCC->BDCR &(RCC_BDCR_LSEBYP|RCC_BDCR_LSEEXT)) == RCC_BDCR_LSEBYP)
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
+  }
+  else if((RCC->BDCR &(RCC_BDCR_LSEBYP|RCC_BDCR_LSEEXT)) == (RCC_BDCR_LSEBYP|RCC_BDCR_LSEEXT))
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS_DIGITAL;
+  }
+  else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
+  }
+#else
+  if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
+  }
+  else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
+  }
+#endif /* RCC_BDCR_LSEEXT */
+
+  /* Get the LSI configuration -----------------------------------------------*/
+  if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
+  {
+    RCC_OscInitStruct->LSIState = RCC_LSI_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
+  }
+
+  /* Get the HSI48 configuration ---------------------------------------------*/
+  if((RCC->CR & RCC_CR_HSI48ON) == RCC_CR_HSI48ON)
+  {
+    RCC_OscInitStruct->HSI48State = RCC_HSI48_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF;
+  }
+
+  /* Get the PLL configuration -----------------------------------------------*/
+  if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
+  {
+    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
+  }
+  RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+  RCC_OscInitStruct->PLL.PLLM = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> RCC_PLLCKSELR_DIVM1_Pos);
+  RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) >> RCC_PLL1DIVR_N1_Pos)+ 1U;
+  RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos)+ 1U;
+  RCC_OscInitStruct->PLL.PLLP = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos)+ 1U;
+  RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos)+ 1U;
+  RCC_OscInitStruct->PLL.PLLRGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL1RGE));
+  RCC_OscInitStruct->PLL.PLLVCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL1VCOSEL) >> RCC_PLLCFGR_PLL1VCOSEL_Pos);
+  RCC_OscInitStruct->PLL.PLLFRACN = (uint32_t)(((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos));
+}
+
+/**
+  * @brief  Configures the RCC_ClkInitStruct according to the internal
+  * RCC configuration registers.
+  * @param  RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
+  * will be configured.
+  * @param  pFLatency: Pointer on the Flash Latency.
+  * @retval None
+  */
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
+{
+  /* Set all possible values for the Clock type parameter --------------------*/
+  RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 |
+                                 RCC_CLOCKTYPE_PCLK2 |  RCC_CLOCKTYPE_D3PCLK1  ;
+
+  /* Get the SYSCLK configuration --------------------------------------------*/
+  RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
+
+#if defined(RCC_D1CFGR_D1CPRE)
+  /* Get the SYSCLK configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1CPRE);
+
+  /* Get the D1HCLK configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_HPRE);
+
+  /* Get the APB3 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1PPRE);
+
+  /* Get the APB1 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1);
+
+  /* Get the APB2 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2);
+
+  /* Get the APB4 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->D3CFGR & RCC_D3CFGR_D3PPRE);
+#else
+  /* Get the SYSCLK configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE);
+
+  /* Get the D1HCLK configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE);
+
+  /* Get the APB3 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE);
+
+  /* Get the APB1 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1);
+
+  /* Get the APB2 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2);
+
+  /* Get the APB4 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE);
+#endif
+
+  /* Get the Flash Wait State (Latency) configuration ------------------------*/
+  *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
+}
+
+/**
+  * @brief This function handles the RCC CSS interrupt request.
+  * @note This API should be called under the NMI_Handler().
+  * @retval None
+  */
+void HAL_RCC_NMI_IRQHandler(void)
+{
+  /* Check RCC CSSF flag  */
+  if(__HAL_RCC_GET_IT(RCC_IT_CSS))
+  {
+    /* RCC Clock Security System interrupt user callback */
+    HAL_RCC_CCSCallback();
+
+    /* Clear RCC CSS pending bit */
+    __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
+  }
+}
+
+/**
+  * @brief  RCC Clock Security System interrupt callback
+  * @retval none
+  */
+__weak void HAL_RCC_CCSCallback(void)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_RCC_CCSCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_RCC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c
new file mode 100644
index 00000000..fa08e692
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c
@@ -0,0 +1,3437 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_rcc_ex.c
+  * @author  MCD Application Team
+  * @brief   Extended RCC HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities RCC extension peripheral:
+  *           + Extended Peripheral Control functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup RCCEx  RCCEx
+  * @brief RCC HAL module driver
+  * @{
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup RCCEx_Private_defines Private Defines
+ * @{
+ */
+#define PLL2_TIMEOUT_VALUE         PLL_TIMEOUT_VALUE    /* 2 ms */
+#define PLL3_TIMEOUT_VALUE         PLL_TIMEOUT_VALUE    /* 2 ms */
+
+#define DIVIDER_P_UPDATE          0U
+#define DIVIDER_Q_UPDATE          1U
+#define DIVIDER_R_UPDATE          2U
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider);
+static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider);
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Functions Exported Functions
+  * @{
+  */
+
+/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
+ *  @brief  Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+                ##### Extended Peripheral Control functions  #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the RCC Clocks
+    frequencies.
+    [..]
+    (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
+        select the RTC clock source; in this case the Backup domain will be reset in
+        order to modify the RTC Clock source, as consequence RTC registers (including
+        the backup registers) and RCC_BDCR register are set to their reset values.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the RCC extended peripherals clocks according to the specified
+  *         parameters in the RCC_PeriphCLKInitTypeDef.
+  * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
+  *         contains the configuration information for the Extended Peripherals
+  *         clocks (SDMMC, CKPER, FMC, QSPI*, OSPI*, DSI, SPI45, SPDIF, DFSDM1, DFSDM2*, FDCAN, SWPMI, SAI23*,SAI2A*, SAI2B*, SAI1, SPI123,
+  *         USART234578, USART16 (USART16910*), RNG, HRTIM1*, I2C123, USB, CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC,
+  *         SAI4A*, SAI4B*, SPI6, RTC).
+  * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
+  *         the RTC clock source; in this case the Backup domain will be reset in
+  *         order to modify the RTC Clock source, as consequence RTC registers (including
+  *         the backup registers) are set to their reset values.
+  *
+  * (*) : Available on some STM32H7 lines only.
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  uint32_t tmpreg;
+  uint32_t tickstart;
+  HAL_StatusTypeDef ret = HAL_OK;      /* Intermediate status */
+  HAL_StatusTypeDef status = HAL_OK;   /* Final status */
+
+  /*---------------------------- SPDIFRX configuration -------------------------------*/
+
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
+  {
+
+    switch(PeriphClkInit->SpdifrxClockSelection)
+    {
+    case RCC_SPDIFRXCLKSOURCE_PLL:      /* PLL is used as clock source for SPDIFRX*/
+      /* Enable PLL1Q Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* SPDIFRX clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPDIFRXCLKSOURCE_PLL2: /* PLL2 is used as clock source for SPDIFRX*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
+
+      /* SPDIFRX clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPDIFRXCLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPDIFRX*/
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
+
+      /* SPDIFRX clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPDIFRXCLKSOURCE_HSI:
+      /* Internal OSC clock is used as source of SPDIFRX clock*/
+      /* SPDIFRX clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SPDIFRX clock*/
+      __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+  /*---------------------------- SAI1 configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
+  {
+    switch(PeriphClkInit->Sai1ClockSelection)
+    {
+    case RCC_SAI1CLKSOURCE_PLL:      /* PLL is used as clock source for SAI1*/
+      /* Enable SAI Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* SAI1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+
+      /* SAI1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI1CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI1*/
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
+
+      /* SAI1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI1CLKSOURCE_PIN:
+      /* External clock is used as source of SAI1 clock*/
+      /* SAI1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI1CLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */
+      /* SAI1 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SAI1 clock*/
+      __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+#if defined(SAI3)
+  /*---------------------------- SAI2/3 configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23)
+  {
+    switch(PeriphClkInit->Sai23ClockSelection)
+    {
+    case RCC_SAI23CLKSOURCE_PLL:      /* PLL is used as clock source for SAI2/3 */
+      /* Enable SAI Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* SAI2/3 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2/3 */
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+
+      /* SAI2/3 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI23CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2/3 */
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
+
+      /* SAI2/3 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI23CLKSOURCE_PIN:
+      /* External clock is used as source of SAI2/3 clock*/
+      /* SAI2/3 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI23CLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of SAI2/3 clock */
+      /* SAI2/3 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SAI2/3 clock*/
+      __HAL_RCC_SAI23_CONFIG(PeriphClkInit->Sai23ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+#endif /* SAI3 */
+
+#if defined(RCC_CDCCIP1R_SAI2ASEL)
+  /*---------------------------- SAI2A configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2A) == RCC_PERIPHCLK_SAI2A)
+  {
+    switch(PeriphClkInit->Sai2AClockSelection)
+    {
+    case RCC_SAI2ACLKSOURCE_PLL:      /* PLL is used as clock source for SAI2A */
+      /* Enable SAI2A Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* SAI2A clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI2ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2A */
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+
+      /* SAI2A clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI2ACLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2A */
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
+
+      /* SAI2A clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI2ACLKSOURCE_PIN:
+      /* External clock is used as source of SAI2A clock*/
+      /* SAI2A clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI2ACLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of SAI2A clock */
+      /* SAI2A clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI2ACLKSOURCE_SPDIF:
+      /* SPDIF clock is used as source of SAI2A clock */
+      /* SAI2A clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SAI2A clock*/
+      __HAL_RCC_SAI2A_CONFIG(PeriphClkInit->Sai2AClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+#endif  /*SAI2A*/
+
+#if defined(RCC_CDCCIP1R_SAI2BSEL)
+
+  /*---------------------------- SAI2B configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2B) == RCC_PERIPHCLK_SAI2B)
+  {
+    switch(PeriphClkInit->Sai2BClockSelection)
+    {
+    case RCC_SAI2BCLKSOURCE_PLL:      /* PLL is used as clock source for SAI2B */
+      /* Enable SAI Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* SAI2B clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI2BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2B */
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+
+      /* SAI2B clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI2BCLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2B */
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
+
+      /* SAI2B clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI2BCLKSOURCE_PIN:
+      /* External clock is used as source of SAI2B clock*/
+      /* SAI2B clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI2BCLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of SAI2B clock */
+      /* SAI2B clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI2BCLKSOURCE_SPDIF:
+      /* SPDIF clock is used as source of SAI2B clock */
+      /* SAI2B clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SAI2B clock*/
+      __HAL_RCC_SAI2B_CONFIG(PeriphClkInit->Sai2BClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+#endif  /*SAI2B*/
+
+#if defined(SAI4)
+  /*---------------------------- SAI4A configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A)
+  {
+    switch(PeriphClkInit->Sai4AClockSelection)
+    {
+    case RCC_SAI4ACLKSOURCE_PLL:      /* PLL is used as clock source for SAI2*/
+      /* Enable SAI Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* SAI1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI4ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+
+      /* SAI2 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI4ACLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2*/
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
+
+      /* SAI1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI4ACLKSOURCE_PIN:
+      /* External clock is used as source of SAI2 clock*/
+      /* SAI2 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI4ACLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */
+      /* SAI1 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SAI4A clock*/
+      __HAL_RCC_SAI4A_CONFIG(PeriphClkInit->Sai4AClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+  /*---------------------------- SAI4B configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B)
+  {
+    switch(PeriphClkInit->Sai4BClockSelection)
+    {
+    case RCC_SAI4BCLKSOURCE_PLL:      /* PLL is used as clock source for SAI2*/
+      /* Enable SAI Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* SAI1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI4BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+
+      /* SAI2 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI4BCLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2*/
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
+
+      /* SAI1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI4BCLKSOURCE_PIN:
+      /* External clock is used as source of SAI2 clock*/
+      /* SAI2 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI4BCLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */
+      /* SAI1 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SAI4B clock*/
+      __HAL_RCC_SAI4B_CONFIG(PeriphClkInit->Sai4BClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+#endif  /*SAI4*/
+
+#if defined(QUADSPI)
+  /*---------------------------- QSPI configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI)
+  {
+    switch(PeriphClkInit->QspiClockSelection)
+    {
+    case RCC_QSPICLKSOURCE_PLL:      /* PLL is used as clock source for QSPI*/
+      /* Enable QSPI Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* QSPI clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_QSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for QSPI*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
+
+      /* QSPI clock source configuration done later after clock selection check */
+      break;
+
+
+    case RCC_QSPICLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of QSPI clock */
+      /* QSPI clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_QSPICLKSOURCE_D1HCLK:
+      /* Domain1 HCLK  clock selected as QSPI kernel peripheral clock */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of QSPI clock*/
+      __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+#endif  /*QUADSPI*/
+
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+  /*---------------------------- OCTOSPI configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI)
+  {
+    switch(PeriphClkInit->OspiClockSelection)
+    {
+    case RCC_OSPICLKSOURCE_PLL:      /* PLL is used as clock source for OSPI*/
+      /* Enable OSPI Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* OSPI clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_OSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for OSPI*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
+
+      /* OSPI clock source configuration done later after clock selection check */
+      break;
+
+
+    case RCC_OSPICLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of OSPI clock */
+      /* OSPI clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_OSPICLKSOURCE_HCLK:
+      /* HCLK clock selected as OSPI kernel peripheral clock */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of OSPI clock*/
+      __HAL_RCC_OSPI_CONFIG(PeriphClkInit->OspiClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+#endif  /*OCTOSPI*/
+
+  /*---------------------------- SPI1/2/3 configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123)
+  {
+    switch(PeriphClkInit->Spi123ClockSelection)
+    {
+    case RCC_SPI123CLKSOURCE_PLL:      /* PLL is used as clock source for SPI1/2/3 */
+      /* Enable SPI Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* SPI1/2/3 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI1/2/3 */
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+
+      /* SPI1/2/3 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI123CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPI1/2/3 */
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
+
+      /* SPI1/2/3 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI123CLKSOURCE_PIN:
+      /* External clock is used as source of SPI1/2/3 clock*/
+      /* SPI1/2/3 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI123CLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of SPI1/2/3 clock */
+      /* SPI1/2/3 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SPI1/2/3 clock*/
+      __HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+  /*---------------------------- SPI4/5 configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45)
+  {
+    switch(PeriphClkInit->Spi45ClockSelection)
+    {
+    case RCC_SPI45CLKSOURCE_PCLK1:      /* CD/D2 PCLK1 as clock source for SPI4/5 */
+      /* SPI4/5 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI4/5 */
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
+
+      /* SPI4/5 clock source configuration done later after clock selection check */
+      break;
+    case RCC_SPI45CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPI4/5 */
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
+      /* SPI4/5 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI45CLKSOURCE_HSI:
+      /* HSI oscillator clock is used as source of SPI4/5 clock*/
+      /* SPI4/5 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI45CLKSOURCE_CSI:
+      /*  CSI oscillator clock is used as source of SPI4/5 clock */
+      /* SPI4/5 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI45CLKSOURCE_HSE:
+      /* HSE,  oscillator is used as source of SPI4/5 clock */
+      /* SPI4/5 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SPI4/5 clock*/
+      __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+  /*---------------------------- SPI6 configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6)
+  {
+    switch(PeriphClkInit->Spi6ClockSelection)
+    {
+    case RCC_SPI6CLKSOURCE_PCLK4:      /* SRD/D3 PCLK1 (PCLK4) as clock source for SPI6*/
+      /* SPI6 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI6*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
+
+      /* SPI6 clock source configuration done later after clock selection check */
+      break;
+    case RCC_SPI6CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPI6*/
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
+      /* SPI6 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI6CLKSOURCE_HSI:
+      /* HSI oscillator clock is used as source of SPI6 clock*/
+      /* SPI6 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI6CLKSOURCE_CSI:
+      /*  CSI oscillator clock is used as source of SPI6 clock */
+      /* SPI6 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI6CLKSOURCE_HSE:
+      /* HSE,  oscillator is used as source of SPI6 clock */
+      /* SPI6 clock source configuration done later after clock selection check */
+      break;
+#if defined(RCC_SPI6CLKSOURCE_PIN)
+    case RCC_SPI6CLKSOURCE_PIN:
+      /* 2S_CKIN is used as source of SPI6 clock */
+      /* SPI6 clock source configuration done later after clock selection check */
+      break;
+#endif
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SPI6 clock*/
+      __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+#if defined(DSI)
+  /*---------------------------- DSI configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI)
+  {
+    switch(PeriphClkInit->DsiClockSelection)
+    {
+
+    case RCC_DSICLKSOURCE_PLL2: /* PLL2 is used as clock source for DSI*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
+
+      /* DSI clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_DSICLKSOURCE_PHY:
+      /* PHY is used as clock source for DSI*/
+      /* DSI clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of DSI clock*/
+      __HAL_RCC_DSI_CONFIG(PeriphClkInit->DsiClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+#endif /*DSI*/
+
+#if defined(FDCAN1) || defined(FDCAN2)
+  /*---------------------------- FDCAN configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
+  {
+    switch(PeriphClkInit->FdcanClockSelection)
+    {
+    case RCC_FDCANCLKSOURCE_PLL:      /* PLL is used as clock source for FDCAN*/
+      /* Enable FDCAN Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* FDCAN clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
+
+      /* FDCAN clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_FDCANCLKSOURCE_HSE:
+      /* HSE is used as clock source for FDCAN*/
+      /* FDCAN clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of FDCAN clock*/
+      __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+#endif /*FDCAN1 || FDCAN2*/
+
+  /*---------------------------- FMC configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC)
+  {
+    switch(PeriphClkInit->FmcClockSelection)
+    {
+    case RCC_FMCCLKSOURCE_PLL:      /* PLL is used as clock source for FMC*/
+      /* Enable FMC Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* FMC clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_FMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for FMC*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
+
+      /* FMC clock source configuration done later after clock selection check */
+      break;
+
+
+    case RCC_FMCCLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of FMC clock */
+      /* FMC clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_FMCCLKSOURCE_HCLK:
+      /* D1/CD HCLK  clock selected as FMC kernel peripheral clock */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of FMC clock*/
+      __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+  /*---------------------------- RTC configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
+  {
+    /* check for RTC Parameters used to output RTCCLK */
+    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+
+    /* Enable write access to Backup domain */
+    SET_BIT(PWR->CR1, PWR_CR1_DBP);
+
+    /* Wait for Backup domain Write protection disable */
+    tickstart = HAL_GetTick();
+
+    while((PWR->CR1 & PWR_CR1_DBP) == 0U)
+    {
+      if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+      {
+        ret = HAL_TIMEOUT;
+        break;
+      }
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Reset the Backup domain only if the RTC Clock source selection is modified */
+      if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
+      {
+        /* Store the content of BDCR register before the reset of Backup Domain */
+        tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+        /* RTC Clock selection can be changed only if the Backup Domain is reset */
+        __HAL_RCC_BACKUPRESET_FORCE();
+        __HAL_RCC_BACKUPRESET_RELEASE();
+        /* Restore the Content of BDCR register */
+        RCC->BDCR = tmpreg;
+      }
+
+      /* If LSE is selected as RTC clock source (and enabled prior to Backup Domain reset), wait for LSE reactivation */
+      if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
+      {
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till LSE is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
+        {
+          if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
+          {
+            ret = HAL_TIMEOUT;
+            break;
+          }
+        }
+      }
+
+      if(ret == HAL_OK)
+      {
+        __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+      }
+      else
+      {
+        /* set overall return value */
+        status = ret;
+      }
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+
+  /*-------------------------- USART1/6 configuration --------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16)
+  {
+    switch(PeriphClkInit->Usart16ClockSelection)
+    {
+    case RCC_USART16CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for USART1/6 */
+      /* USART1/6 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USART16CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART1/6 */
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
+      /* USART1/6 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USART16CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1/6 */
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
+      /* USART1/6 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USART16CLKSOURCE_HSI:
+      /* HSI oscillator clock is used as source of USART1/6 clock */
+      /* USART1/6 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USART16CLKSOURCE_CSI:
+      /* CSI oscillator clock is used as source of USART1/6 clock */
+      /* USART1/6 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USART16CLKSOURCE_LSE:
+      /* LSE,  oscillator is used as source of USART1/6 clock */
+      /* USART1/6 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of USART1/6 clock */
+      __HAL_RCC_USART16_CONFIG(PeriphClkInit->Usart16ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+  /*-------------------------- USART2/3/4/5/7/8 Configuration --------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578)
+  {
+    switch(PeriphClkInit->Usart234578ClockSelection)
+    {
+    case RCC_USART234578CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for USART2/3/4/5/7/8 */
+      /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USART234578CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART2/3/4/5/7/8 */
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
+      /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USART234578CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART2/3/4/5/7/8 */
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
+      /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USART234578CLKSOURCE_HSI:
+      /* HSI oscillator clock is used as source of USART2/3/4/5/7/8 clock */
+      /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USART234578CLKSOURCE_CSI:
+      /* CSI oscillator clock is used as source of USART2/3/4/5/7/8 clock */
+      /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USART234578CLKSOURCE_LSE:
+      /* LSE,  oscillator is used as source of USART2/3/4/5/7/8 clock */
+      /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of USART2/3/4/5/7/8 clock */
+      __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+  /*-------------------------- LPUART1 Configuration -------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
+  {
+    switch(PeriphClkInit->Lpuart1ClockSelection)
+    {
+    case RCC_LPUART1CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPUART1 */
+      /* LPUART1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPUART1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPUART1 */
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
+      /* LPUART1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPUART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPUART1 */
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
+      /* LPUART1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPUART1CLKSOURCE_HSI:
+      /* HSI oscillator clock is used as source of LPUART1 clock */
+      /* LPUART1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPUART1CLKSOURCE_CSI:
+      /* CSI oscillator clock is used as source of LPUART1 clock */
+      /* LPUART1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPUART1CLKSOURCE_LSE:
+      /* LSE,  oscillator is used as source of LPUART1 clock */
+      /* LPUART1 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of LPUART1 clock */
+      __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+  /*---------------------------- LPTIM1 configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
+  {
+    switch(PeriphClkInit->Lptim1ClockSelection)
+    {
+    case RCC_LPTIM1CLKSOURCE_PCLK1:      /* CD/D2 PCLK1 as clock source for LPTIM1*/
+      /* LPTIM1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM1*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+
+      /* LPTIM1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM1CLKSOURCE_PLL3:  /* PLL3 is used as clock source for LPTIM1*/
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
+
+      /* LPTIM1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM1CLKSOURCE_LSE:
+      /* External low speed OSC clock is used as source of LPTIM1 clock*/
+      /* LPTIM1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM1CLKSOURCE_LSI:
+      /* Internal  low speed OSC clock is used  as source of LPTIM1 clock*/
+      /* LPTIM1 clock source configuration done later after clock selection check */
+      break;
+    case RCC_LPTIM1CLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of LPTIM1 clock */
+      /* LPTIM1 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of LPTIM1 clock*/
+      __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+  /*---------------------------- LPTIM2 configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2)
+  {
+    switch(PeriphClkInit->Lptim2ClockSelection)
+    {
+    case RCC_LPTIM2CLKSOURCE_PCLK4:      /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM2*/
+      /* LPTIM2 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM2CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM2*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+
+      /* LPTIM2 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM2CLKSOURCE_PLL3:  /* PLL3 is used as clock source for LPTIM2*/
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
+
+      /* LPTIM2 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM2CLKSOURCE_LSE:
+      /* External low speed OSC clock is used as source of LPTIM2 clock*/
+      /* LPTIM2 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM2CLKSOURCE_LSI:
+      /* Internal  low speed OSC clock is used  as source of LPTIM2 clock*/
+      /* LPTIM2 clock source configuration done later after clock selection check */
+      break;
+    case RCC_LPTIM2CLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */
+      /* LPTIM2 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of LPTIM2 clock*/
+      __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+  /*---------------------------- LPTIM345 configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345)
+  {
+    switch(PeriphClkInit->Lptim345ClockSelection)
+    {
+
+    case RCC_LPTIM345CLKSOURCE_PCLK4:      /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM3/4/5 */
+      /* LPTIM3/4/5 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM345CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM3/4/5 */
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+
+      /* LPTIM3/4/5 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM345CLKSOURCE_PLL3:  /* PLL3 is used as clock source for LPTIM3/4/5 */
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
+
+      /* LPTIM3/4/5 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM345CLKSOURCE_LSE:
+      /* External low speed OSC clock is used as source of LPTIM3/4/5 clock */
+      /* LPTIM3/4/5 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM345CLKSOURCE_LSI:
+      /* Internal  low speed OSC clock is used  as source of LPTIM3/4/5 clock */
+      /* LPTIM3/4/5 clock source configuration done later after clock selection check */
+      break;
+    case RCC_LPTIM345CLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of LPTIM3/4/5 clock */
+      /* LPTIM3/4/5 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of LPTIM3/4/5 clock */
+      __HAL_RCC_LPTIM345_CONFIG(PeriphClkInit->Lptim345ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+  /*------------------------------ I2C1/2/3 Configuration ------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2C123CLKSOURCE(PeriphClkInit->I2c123ClockSelection));
+
+    if ((PeriphClkInit->I2c123ClockSelection )== RCC_I2C123CLKSOURCE_PLL3 )
+    {
+        if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!= HAL_OK)
+        {
+          status = HAL_ERROR;
+        }
+    }
+
+      __HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection);
+
+  }
+
+  /*------------------------------ I2C4 Configuration ------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
+
+    if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3 )
+    {
+      if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!= HAL_OK)
+      {
+        status = HAL_ERROR;
+      }
+    }
+
+      __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
+
+  }
+
+  /*---------------------------- ADC configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
+  {
+    switch(PeriphClkInit->AdcClockSelection)
+    {
+
+    case RCC_ADCCLKSOURCE_PLL2: /* PLL2 is used as clock source for ADC*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+
+      /* ADC clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_ADCCLKSOURCE_PLL3:  /* PLL3 is used as clock source for ADC*/
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
+
+      /* ADC clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_ADCCLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of ADC clock */
+      /* ADC clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of ADC clock*/
+      __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+  /*------------------------------ USB Configuration -------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
+  {
+
+    switch(PeriphClkInit->UsbClockSelection)
+    {
+    case RCC_USBCLKSOURCE_PLL:      /* PLL is used as clock source for USB*/
+      /* Enable USB Clock output generated form System USB . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* USB clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USBCLKSOURCE_PLL3: /* PLL3 is used as clock source for USB*/
+
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
+
+      /* USB clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USBCLKSOURCE_HSI48:
+      /* HSI48 oscillator is used as source of USB clock */
+      /* USB clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of USB clock*/
+      __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+
+  }
+
+  /*------------------------------------- SDMMC Configuration ------------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SDMMC(PeriphClkInit->SdmmcClockSelection));
+
+    switch(PeriphClkInit->SdmmcClockSelection)
+    {
+    case RCC_SDMMCCLKSOURCE_PLL:      /* PLL is used as clock source for SDMMC*/
+      /* Enable SDMMC Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* SDMMC clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for SDMMC*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
+
+      /* SDMMC clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SDMMC clock*/
+      __HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+#if defined(LTDC)
+  /*-------------------------------------- LTDC Configuration -----------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
+  {
+    if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!=HAL_OK)
+    {
+      status=HAL_ERROR;
+    }
+  }
+#endif /* LTDC */
+
+  /*------------------------------ RNG Configuration -------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG)
+  {
+
+    switch(PeriphClkInit->RngClockSelection)
+    {
+    case RCC_RNGCLKSOURCE_PLL:     /* PLL is used as clock source for RNG*/
+      /* Enable RNG Clock output generated form System RNG . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* RNG clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_RNGCLKSOURCE_LSE: /* LSE is used as clock source for RNG*/
+
+      /* RNG clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_RNGCLKSOURCE_LSI: /* LSI is used as clock source for RNG*/
+
+      /* RNG clock source configuration done later after clock selection check */
+      break;
+    case RCC_RNGCLKSOURCE_HSI48:
+      /* HSI48 oscillator is used as source of RNG clock */
+      /* RNG clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of RNG clock*/
+      __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+
+  }
+
+  /*------------------------------ SWPMI1 Configuration ------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection));
+
+    /* Configure the SWPMI1 interface clock source */
+    __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);
+  }
+#if defined(HRTIM)
+  /*------------------------------ HRTIM1 clock Configuration ----------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection));
+
+    /* Configure the HRTIM1 clock source */
+    __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection);
+  }
+#endif  /*HRTIM*/
+  /*------------------------------ DFSDM1 Configuration ------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
+
+    /* Configure the DFSDM1 interface clock source */
+    __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
+  }
+
+#if defined(DFSDM2_BASE)
+  /*------------------------------ DFSDM2 Configuration ------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2) == RCC_PERIPHCLK_DFSDM2)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_DFSDM2CLKSOURCE(PeriphClkInit->Dfsdm2ClockSelection));
+
+    /* Configure the DFSDM2 interface clock source */
+    __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection);
+  }
+#endif  /* DFSDM2 */
+
+  /*------------------------------------ TIM configuration --------------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
+
+    /* Configure Timer Prescaler */
+    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
+  }
+
+  /*------------------------------------ CKPER configuration --------------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_CLKPSOURCE(PeriphClkInit->CkperClockSelection));
+
+    /* Configure the CKPER clock source */
+    __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection);
+  }
+
+  if (status == HAL_OK)
+  {
+    return HAL_OK;
+  }
+  return HAL_ERROR;
+}
+
+/**
+  * @brief  Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
+  * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
+  *         returns the configuration information for the Extended Peripherals clocks :
+  *         (SDMMC, CKPER, FMC, QSPI*, OSPI*, DSI*, SPI45, SPDIF, DFSDM1, DFSDM2*, FDCAN, SWPMI, SAI23*, SAI1, SPI123,
+  *         USART234578, USART16, RNG, HRTIM1*, I2C123, USB, CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC.
+  *         SAI4A*, SAI4B*, SPI6, RTC, TIM).
+  * @retval None
+  *
+  *   (*) : Available on some STM32H7 lines only.
+  */
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  /* Set all possible values for the extended clock type parameter------------*/
+  PeriphClkInit->PeriphClockSelection =
+                 RCC_PERIPHCLK_USART16 | RCC_PERIPHCLK_USART234578 | RCC_PERIPHCLK_LPUART1 |
+                 RCC_PERIPHCLK_I2C4    | RCC_PERIPHCLK_LPTIM1      | RCC_PERIPHCLK_LPTIM2  | RCC_PERIPHCLK_LPTIM345 |
+                 RCC_PERIPHCLK_SAI1    | RCC_PERIPHCLK_SPI123      | RCC_PERIPHCLK_SPI45   | RCC_PERIPHCLK_SPI6     |
+	         RCC_PERIPHCLK_FDCAN   | RCC_PERIPHCLK_SDMMC       | RCC_PERIPHCLK_RNG     | RCC_PERIPHCLK_USB      |
+	         RCC_PERIPHCLK_ADC     | RCC_PERIPHCLK_SWPMI1      | RCC_PERIPHCLK_DFSDM1  | RCC_PERIPHCLK_RTC      |
+	         RCC_PERIPHCLK_CEC     | RCC_PERIPHCLK_FMC         | RCC_PERIPHCLK_SPDIFRX | RCC_PERIPHCLK_TIM      |
+	         RCC_PERIPHCLK_CKPER;
+
+PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C123;
+#if defined(RCC_CDCCIP1R_SAI2ASEL)
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI2A;
+#endif /* RCC_CDCCIP1R_SAI2ASEL */
+#if defined(RCC_CDCCIP1R_SAI2BSEL)
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI2B;
+#endif /* RCC_CDCCIP1R_SAI2BSEL */
+#if defined(SAI3)
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI23;
+#endif /* SAI3 */
+#if defined(SAI4)
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI4A;
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI4B;
+#endif /* SAI4 */
+#if defined(DFSDM2_BASE)
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_DFSDM2;
+#endif /* DFSDM2 */
+#if defined(QUADSPI)
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_QSPI;
+#endif /* QUADSPI */
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_OSPI;
+#endif /* OCTOSPI1 || OCTOSPI2 */
+#if defined(HRTIM)
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_HRTIM1;
+#endif /* HRTIM */
+#if defined(LTDC)
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LTDC;
+#endif /* LTDC */
+#if defined(DSI)
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_DSI;
+#endif /* DSI */
+
+  /* Get the PLL3 Clock configuration -----------------------------------------------*/
+  PeriphClkInit->PLL3.PLL3M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3)>> RCC_PLLCKSELR_DIVM3_Pos);
+  PeriphClkInit->PLL3.PLL3N = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_N3) >> RCC_PLL3DIVR_N3_Pos)+ 1U;
+  PeriphClkInit->PLL3.PLL3R = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> RCC_PLL3DIVR_R3_Pos)+ 1U;
+  PeriphClkInit->PLL3.PLL3P = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> RCC_PLL3DIVR_P3_Pos)+ 1U;
+  PeriphClkInit->PLL3.PLL3Q = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> RCC_PLL3DIVR_Q3_Pos)+ 1U;
+  PeriphClkInit->PLL3.PLL3RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3RGE) >> RCC_PLLCFGR_PLL3RGE_Pos);
+  PeriphClkInit->PLL3.PLL3VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3VCOSEL) >> RCC_PLLCFGR_PLL3VCOSEL_Pos);
+
+  /* Get the PLL2 Clock configuration -----------------------------------------------*/
+  PeriphClkInit->PLL2.PLL2M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2)>> RCC_PLLCKSELR_DIVM2_Pos);
+  PeriphClkInit->PLL2.PLL2N = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_N2) >> RCC_PLL2DIVR_N2_Pos)+ 1U;
+  PeriphClkInit->PLL2.PLL2R = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> RCC_PLL2DIVR_R2_Pos)+ 1U;
+  PeriphClkInit->PLL2.PLL2P = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> RCC_PLL2DIVR_P2_Pos)+ 1U;
+  PeriphClkInit->PLL2.PLL2Q = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> RCC_PLL2DIVR_Q2_Pos)+ 1U;
+  PeriphClkInit->PLL2.PLL2RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2RGE) >> RCC_PLLCFGR_PLL2RGE_Pos);
+  PeriphClkInit->PLL2.PLL2VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2VCOSEL) >> RCC_PLLCFGR_PLL2VCOSEL_Pos);
+
+  /* Get the USART1 configuration --------------------------------------------*/
+  PeriphClkInit->Usart16ClockSelection      = __HAL_RCC_GET_USART16_SOURCE();
+  /* Get the USART2/3/4/5/7/8 clock source -----------------------------------*/
+  PeriphClkInit->Usart234578ClockSelection  = __HAL_RCC_GET_USART234578_SOURCE();
+  /* Get the LPUART1 clock source --------------------------------------------*/
+  PeriphClkInit->Lpuart1ClockSelection      = __HAL_RCC_GET_LPUART1_SOURCE();
+  /* Get the I2C1/2/3 clock source -------------------------------------------*/
+  PeriphClkInit->I2c123ClockSelection       = __HAL_RCC_GET_I2C1_SOURCE();
+  /* Get the LPTIM1 clock source ---------------------------------------------*/
+  PeriphClkInit->Lptim1ClockSelection       = __HAL_RCC_GET_LPTIM1_SOURCE();
+  /* Get the LPTIM2 clock source ---------------------------------------------*/
+  PeriphClkInit->Lptim2ClockSelection       = __HAL_RCC_GET_LPTIM2_SOURCE();
+  /* Get the LPTIM3/4/5 clock source -----------------------------------------*/
+  PeriphClkInit->Lptim345ClockSelection     = __HAL_RCC_GET_LPTIM345_SOURCE();
+  /* Get the SAI1 clock source -----------------------------------------------*/
+  PeriphClkInit->Sai1ClockSelection         = __HAL_RCC_GET_SAI1_SOURCE();
+#if defined(SAI3)
+  /* Get the SAI2/3 clock source ---------------------------------------------*/
+  PeriphClkInit->Sai23ClockSelection        = __HAL_RCC_GET_SAI23_SOURCE();
+#endif  /*SAI3*/
+#if defined(RCC_CDCCIP1R_SAI2ASEL_0)
+  /* Get the SAI2A clock source ---------------------------------------------*/
+  PeriphClkInit->Sai2AClockSelection        = __HAL_RCC_GET_SAI2A_SOURCE();
+#endif  /*SAI2A*/
+#if defined(RCC_CDCCIP1R_SAI2BSEL_0)
+  /* Get the SAI2B clock source ---------------------------------------------*/
+  PeriphClkInit->Sai2BClockSelection        = __HAL_RCC_GET_SAI2B_SOURCE();
+#endif  /*SAI2B*/
+#if defined(SAI4)
+  /* Get the SAI4A clock source ----------------------------------------------*/
+  PeriphClkInit->Sai4AClockSelection        = __HAL_RCC_GET_SAI4A_SOURCE();
+  /* Get the SAI4B clock source ----------------------------------------------*/
+  PeriphClkInit->Sai4BClockSelection        = __HAL_RCC_GET_SAI4B_SOURCE();
+#endif  /*SAI4*/
+  /* Get the RTC clock source ------------------------------------------------*/
+  PeriphClkInit->RTCClockSelection          = __HAL_RCC_GET_RTC_SOURCE();
+  /* Get the USB clock source ------------------------------------------------*/
+  PeriphClkInit->UsbClockSelection          = __HAL_RCC_GET_USB_SOURCE();
+  /* Get the SDMMC clock source ----------------------------------------------*/
+  PeriphClkInit->SdmmcClockSelection        = __HAL_RCC_GET_SDMMC_SOURCE();
+  /* Get the RNG clock source ------------------------------------------------*/
+  PeriphClkInit->RngClockSelection          = __HAL_RCC_GET_RNG_SOURCE();
+#if defined(HRTIM1)
+  /* Get the HRTIM1 clock source ---------------------------------------------*/
+  PeriphClkInit->Hrtim1ClockSelection       = __HAL_RCC_GET_HRTIM1_SOURCE();
+#endif /* HRTIM1 */
+  /* Get the ADC clock source ------------------------------------------------*/
+  PeriphClkInit->AdcClockSelection          = __HAL_RCC_GET_ADC_SOURCE();
+  /* Get the SWPMI1 clock source ---------------------------------------------*/
+  PeriphClkInit->Swpmi1ClockSelection       = __HAL_RCC_GET_SWPMI1_SOURCE();
+  /* Get the DFSDM1 clock source ---------------------------------------------*/
+  PeriphClkInit->Dfsdm1ClockSelection       = __HAL_RCC_GET_DFSDM1_SOURCE();
+#if defined(DFSDM2_BASE)
+  /* Get the DFSDM2 clock source ---------------------------------------------*/
+  PeriphClkInit->Dfsdm2ClockSelection       = __HAL_RCC_GET_DFSDM2_SOURCE();
+#endif /* DFSDM2 */
+  /* Get the SPDIFRX clock source --------------------------------------------*/
+  PeriphClkInit->SpdifrxClockSelection      = __HAL_RCC_GET_SPDIFRX_SOURCE();
+  /* Get the SPI1/2/3 clock source -------------------------------------------*/
+  PeriphClkInit->Spi123ClockSelection       = __HAL_RCC_GET_SPI123_SOURCE();
+  /* Get the SPI4/5 clock source ---------------------------------------------*/
+  PeriphClkInit->Spi45ClockSelection        = __HAL_RCC_GET_SPI45_SOURCE();
+  /* Get the SPI6 clock source -----------------------------------------------*/
+  PeriphClkInit->Spi6ClockSelection         = __HAL_RCC_GET_SPI6_SOURCE();
+  /* Get the FDCAN clock source ----------------------------------------------*/
+  PeriphClkInit->FdcanClockSelection        = __HAL_RCC_GET_FDCAN_SOURCE();
+  /* Get the CEC clock source ------------------------------------------------*/
+  PeriphClkInit->CecClockSelection          = __HAL_RCC_GET_CEC_SOURCE();
+  /* Get the FMC clock source ------------------------------------------------*/
+  PeriphClkInit->FmcClockSelection          = __HAL_RCC_GET_FMC_SOURCE();
+#if defined(QUADSPI)
+  /* Get the QSPI clock source -----------------------------------------------*/
+  PeriphClkInit->QspiClockSelection         = __HAL_RCC_GET_QSPI_SOURCE();
+#endif /* QUADSPI */
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+  /* Get the OSPI clock source -----------------------------------------------*/
+  PeriphClkInit->OspiClockSelection         = __HAL_RCC_GET_OSPI_SOURCE();
+#endif /* OCTOSPI1 || OCTOSPI2 */
+
+#if defined(DSI)
+  /* Get the DSI clock source ------------------------------------------------*/
+  PeriphClkInit->DsiClockSelection          = __HAL_RCC_GET_DSI_SOURCE();
+#endif /*DSI*/
+
+  /* Get the CKPER clock source ----------------------------------------------*/
+  PeriphClkInit->CkperClockSelection        = __HAL_RCC_GET_CLKP_SOURCE();
+
+  /* Get the TIM Prescaler configuration -------------------------------------*/
+  if ((RCC->CFGR & RCC_CFGR_TIMPRE) == 0U)
+  {
+    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
+  }
+  else
+  {
+    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
+  }
+}
+
+/**
+  * @brief  Return the peripheral clock frequency for a given peripheral(SAI..)
+  * @note   Return 0 if peripheral clock identifier not managed by this API
+  * @param  PeriphClk: Peripheral clock identifier
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PERIPHCLK_SAI1  : SAI1 peripheral clock
+  *            @arg RCC_PERIPHCLK_SAI23 : SAI2/3  peripheral clock (*)
+  *            @arg RCC_PERIPHCLK_SAI2A : SAI2A peripheral clock (*)
+  *            @arg RCC_PERIPHCLK_SAI2B : SAI2B peripheral clock (*)
+  *            @arg RCC_PERIPHCLK_SAI4A : SAI4A peripheral clock (*)
+  *            @arg RCC_PERIPHCLK_SAI4B : SAI4B peripheral clock (*)
+  *            @arg RCC_PERIPHCLK_SPI123: SPI1/2/3 peripheral clock
+  *            @arg RCC_PERIPHCLK_ADC   : ADC peripheral clock
+  *            @arg RCC_PERIPHCLK_SDMMC : SDMMC peripheral clock
+  *            @arg RCC_PERIPHCLK_SPI6  : SPI6 peripheral clock
+  * @retval Frequency in KHz
+  *
+  *  (*) : Available on some STM32H7 lines only.
+  */
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
+{
+  PLL1_ClocksTypeDef pll1_clocks;
+  PLL2_ClocksTypeDef pll2_clocks;
+  PLL3_ClocksTypeDef pll3_clocks;
+
+  /* This variable is used to store the SAI clock frequency (value in Hz) */
+  uint32_t frequency;
+  /* This variable is used to store the SAI and CKP clock source */
+  uint32_t saiclocksource;
+  uint32_t ckpclocksource;
+  uint32_t srcclk;
+
+  if (PeriphClk == RCC_PERIPHCLK_SAI1)
+    {
+
+      saiclocksource= __HAL_RCC_GET_SAI1_SOURCE();
+
+      switch (saiclocksource)
+      {
+      case RCC_SAI1CLKSOURCE_PLL: /* PLL1 is the clock source for SAI1 */
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+          break;
+        }
+      case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI1 */
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_P_Frequency;
+          break;
+        }
+
+      case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI1 */
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+          frequency = pll3_clocks.PLL3_P_Frequency;
+          break;
+        }
+
+      case RCC_SAI1CLKSOURCE_CLKP: /* CKPER is the clock source for SAI1*/
+        {
+
+          ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
+
+          if(ckpclocksource== RCC_CLKPSOURCE_HSI)
+          {
+            /* In Case the CKPER Source is HSI */
+            frequency = HSI_VALUE;
+          }
+
+          else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
+          {
+            /* In Case the CKPER Source is CSI */
+            frequency = CSI_VALUE;
+          }
+
+          else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
+          {
+            /* In Case the CKPER Source is HSE */
+            frequency = HSE_VALUE;
+          }
+
+          else
+          {
+            /* In Case the CKPER is disabled*/
+            frequency = 0;
+          }
+
+          break;
+        }
+
+      case (RCC_SAI1CLKSOURCE_PIN): /* External clock is the clock source for SAI1 */
+        {
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+      default :
+        {
+          frequency = 0;
+          break;
+        }
+      }
+    }
+
+#if defined(SAI3)
+  else if (PeriphClk == RCC_PERIPHCLK_SAI23)
+    {
+
+      saiclocksource= __HAL_RCC_GET_SAI23_SOURCE();
+
+      switch (saiclocksource)
+      {
+      case 0: /* PLL1 is the clock source for SAI2/3 */
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+          break;
+        }
+      case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI2/3 */
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_P_Frequency;
+          break;
+        }
+
+      case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI2/3 */
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+          frequency = pll3_clocks.PLL3_P_Frequency;
+          break;
+        }
+
+      case RCC_SAI23CLKSOURCE_CLKP: /* CKPER is the clock source for SAI2/3 */
+        {
+
+          ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
+
+          if(ckpclocksource== RCC_CLKPSOURCE_HSI)
+          {
+            /* In Case the CKPER Source is HSI */
+            frequency = HSI_VALUE;
+          }
+
+          else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
+          {
+            /* In Case the CKPER Source is CSI */
+            frequency = CSI_VALUE;
+          }
+
+          else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
+          {
+            /* In Case the CKPER Source is HSE */
+            frequency = HSE_VALUE;
+          }
+
+          else
+          {
+            /* In Case the CKPER is disabled*/
+            frequency = 0;
+          }
+
+          break;
+        }
+
+      case (RCC_SAI23CLKSOURCE_PIN): /* External clock is the clock source for SAI2/3 */
+        {
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+      default :
+        {
+          frequency = 0;
+          break;
+        }
+      }
+    }
+#endif /* SAI3 */
+
+#if  defined(RCC_CDCCIP1R_SAI2ASEL)
+
+    else if (PeriphClk == RCC_PERIPHCLK_SAI2A)
+    {
+      saiclocksource= __HAL_RCC_GET_SAI2A_SOURCE();
+
+      switch (saiclocksource)
+      {
+      case 0: /* PLL1 is the clock source for SAI2A */
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+          break;
+        }
+      case RCC_SAI2ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI2A */
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_P_Frequency;
+          break;
+        }
+
+      case RCC_SAI2ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI2A  */
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+          frequency = pll3_clocks.PLL3_P_Frequency;
+          break;
+        }
+
+      case RCC_SAI2ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI2A  */
+        {
+
+          ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
+
+          if(ckpclocksource== RCC_CLKPSOURCE_HSI)
+          {
+            /* In Case the CKPER Source is HSI */
+            frequency = HSI_VALUE;
+          }
+
+          else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
+          {
+            /* In Case the CKPER Source is CSI */
+            frequency = CSI_VALUE;
+          }
+
+          else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
+          {
+            /* In Case the CKPER Source is HSE */
+            frequency = HSE_VALUE;
+          }
+
+          else
+          {
+            /* In Case the CKPER is disabled*/
+            frequency = 0;
+          }
+
+          break;
+        }
+
+      case (RCC_SAI2ACLKSOURCE_PIN): /* External clock is the clock source for SAI2A */
+        {
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+
+      default :
+        {
+          frequency = 0;
+          break;
+        }
+      }
+
+    }
+#endif
+
+#if  defined(RCC_CDCCIP1R_SAI2BSEL_0)
+  else if (PeriphClk == RCC_PERIPHCLK_SAI2B)
+    {
+
+      saiclocksource= __HAL_RCC_GET_SAI2B_SOURCE();
+
+      switch (saiclocksource)
+      {
+      case 0: /* PLL1 is the clock source for SAI2B */
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+          break;
+        }
+      case RCC_SAI2BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI2B */
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_P_Frequency;
+          break;
+        }
+
+      case RCC_SAI2BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI2B */
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+          frequency = pll3_clocks.PLL3_P_Frequency;
+          break;
+        }
+
+      case RCC_SAI2BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI2B*/
+        {
+
+          ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
+
+          if(ckpclocksource== RCC_CLKPSOURCE_HSI)
+          {
+            /* In Case the CKPER Source is HSI */
+            frequency = HSI_VALUE;
+          }
+
+          else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
+          {
+            /* In Case the CKPER Source is CSI */
+            frequency = CSI_VALUE;
+          }
+
+          else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
+          {
+            /* In Case the CKPER Source is HSE */
+            frequency = HSE_VALUE;
+          }
+
+          else
+          {
+            /* In Case the CKPER is disabled*/
+            frequency = 0;
+          }
+          break;
+        }
+
+      case (RCC_SAI2BCLKSOURCE_PIN): /* External clock is the clock source for SAI2B */
+        {
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+
+      default :
+        {
+          frequency = 0;
+          break;
+        }
+      }
+    }
+#endif
+
+#if defined(SAI4)
+  else if (PeriphClk == RCC_PERIPHCLK_SAI4A)
+    {
+
+      saiclocksource= __HAL_RCC_GET_SAI4A_SOURCE();
+
+      switch (saiclocksource)
+      {
+      case 0: /* PLL1 is the clock source for SAI4A */
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+          break;
+        }
+      case RCC_D3CCIPR_SAI4ASEL_0: /* PLLI2 is the clock source for SAI4A */
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_P_Frequency;
+          break;
+        }
+
+      case RCC_D3CCIPR_SAI4ASEL_1: /* PLLI3 is the clock source for SAI4A */
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+          frequency = pll3_clocks.PLL3_P_Frequency;
+          break;
+        }
+
+      case RCC_D3CCIPR_SAI4ASEL_2: /* CKPER is the clock source for SAI4A*/
+        {
+
+          ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
+
+          if(ckpclocksource== RCC_CLKPSOURCE_HSI)
+          {
+            /* In Case the CKPER Source is HSI */
+            frequency = HSI_VALUE;
+          }
+
+          else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
+          {
+            /* In Case the CKPER Source is CSI */
+            frequency = CSI_VALUE;
+          }
+
+          else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
+          {
+            /* In Case the CKPER Source is HSE */
+            frequency = HSE_VALUE;
+          }
+
+          else
+          {
+            /* In Case the CKPER is disabled*/
+            frequency = 0;
+          }
+
+          break;
+        }
+
+      case (RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1 ): /* External clock is the clock source for SAI4A */
+        {
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+
+      default :
+        {
+          frequency = 0;
+          break;
+        }
+      }
+    }
+
+  else if (PeriphClk == RCC_PERIPHCLK_SAI4B)
+    {
+
+      saiclocksource= __HAL_RCC_GET_SAI4B_SOURCE();
+
+      switch (saiclocksource)
+      {
+      case 0: /* PLL1 is the clock source for SAI4B */
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+          break;
+        }
+      case RCC_D3CCIPR_SAI4BSEL_0: /* PLLI2 is the clock source for SAI4B */
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_P_Frequency;
+          break;
+        }
+
+      case RCC_D3CCIPR_SAI4BSEL_1: /* PLLI3 is the clock source for SAI4B */
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+          frequency = pll3_clocks.PLL3_P_Frequency;
+          break;
+        }
+
+      case RCC_D3CCIPR_SAI4BSEL_2: /* CKPER is the clock source for SAI4B*/
+        {
+
+          ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
+
+          if(ckpclocksource== RCC_CLKPSOURCE_HSI)
+          {
+            /* In Case the CKPER Source is HSI */
+            frequency = HSI_VALUE;
+          }
+
+          else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
+          {
+            /* In Case the CKPER Source is CSI */
+            frequency = CSI_VALUE;
+          }
+
+          else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
+          {
+            /* In Case the CKPER Source is HSE */
+            frequency = HSE_VALUE;
+          }
+
+          else
+          {
+            /* In Case the CKPER is disabled*/
+            frequency = 0;
+          }
+
+          break;
+        }
+
+      case (RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1 ): /* External clock is the clock source for SAI4B */
+        {
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+
+      default :
+        {
+          frequency = 0;
+          break;
+        }
+      }
+    }
+#endif /*SAI4*/
+  else if (PeriphClk == RCC_PERIPHCLK_SPI123)
+    {
+      /* Get SPI1/2/3 clock source */
+      srcclk= __HAL_RCC_GET_SPI123_SOURCE();
+
+      switch (srcclk)
+      {
+      case RCC_SPI123CLKSOURCE_PLL: /* PLL1 is the clock source for I2S */
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+          break;
+        }
+      case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is the clock source for I2S */
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_P_Frequency;
+          break;
+        }
+
+      case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is the clock source for I2S */
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+          frequency = pll3_clocks.PLL3_P_Frequency;
+          break;
+        }
+
+      case RCC_SPI123CLKSOURCE_CLKP: /* CKPER is the clock source for I2S */
+        {
+
+          ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
+
+          if(ckpclocksource== RCC_CLKPSOURCE_HSI)
+          {
+            /* In Case the CKPER Source is HSI */
+            frequency = HSI_VALUE;
+          }
+
+          else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
+          {
+            /* In Case the CKPER Source is CSI */
+            frequency = CSI_VALUE;
+          }
+
+          else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
+          {
+            /* In Case the CKPER Source is HSE */
+            frequency = HSE_VALUE;
+          }
+
+          else
+          {
+            /* In Case the CKPER is disabled*/
+            frequency = 0;
+          }
+
+          break;
+        }
+
+      case (RCC_SPI123CLKSOURCE_PIN): /* External clock is the clock source for I2S */
+        {
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+      default :
+        {
+          frequency = 0;
+          break;
+        }
+      }
+    }
+  else if (PeriphClk == RCC_PERIPHCLK_ADC)
+    {
+      /* Get ADC clock source */
+      srcclk= __HAL_RCC_GET_ADC_SOURCE();
+
+      switch (srcclk)
+      {
+      case RCC_ADCCLKSOURCE_PLL2:
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_P_Frequency;
+          break;
+        }
+      case RCC_ADCCLKSOURCE_PLL3:
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+          frequency = pll3_clocks.PLL3_R_Frequency;
+          break;
+        }
+
+      case RCC_ADCCLKSOURCE_CLKP:
+        {
+
+          ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
+
+          if(ckpclocksource== RCC_CLKPSOURCE_HSI)
+          {
+            /* In Case the CKPER Source is HSI */
+            frequency = HSI_VALUE;
+          }
+
+          else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
+          {
+            /* In Case the CKPER Source is CSI */
+            frequency = CSI_VALUE;
+          }
+
+          else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
+          {
+            /* In Case the CKPER Source is HSE */
+            frequency = HSE_VALUE;
+          }
+
+          else
+          {
+            /* In Case the CKPER is disabled*/
+            frequency = 0;
+          }
+
+          break;
+        }
+
+      default :
+        {
+          frequency = 0;
+          break;
+        }
+      }
+    }
+  else if (PeriphClk == RCC_PERIPHCLK_SDMMC)
+    {
+      /* Get SDMMC clock source */
+      srcclk= __HAL_RCC_GET_SDMMC_SOURCE();
+
+      switch (srcclk)
+      {
+      case RCC_SDMMCCLKSOURCE_PLL: /* PLL1 is the clock source for SDMMC */
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+          break;
+        }
+      case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is the clock source for SDMMC */
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_R_Frequency;
+          break;
+        }
+
+      default :
+        {
+          frequency = 0;
+          break;
+        }
+      }
+    }
+  else if (PeriphClk == RCC_PERIPHCLK_SPI6)
+    {
+      /* Get SPI6 clock source */
+      srcclk= __HAL_RCC_GET_SPI6_SOURCE();
+
+      switch (srcclk)
+      {
+      case RCC_SPI6CLKSOURCE_D3PCLK1: /* D3PCLK1 (PCLK4) is the clock source for SPI6 */
+        {
+          frequency = HAL_RCCEx_GetD3PCLK1Freq();
+          break;
+        }
+      case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI6 */
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_Q_Frequency;
+          break;
+        }
+      case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI6 */
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+          frequency = pll3_clocks.PLL3_Q_Frequency;
+          break;
+        }
+      case RCC_SPI6CLKSOURCE_HSI: /* HSI is the clock source for SPI6 */
+        {
+          frequency = HSI_VALUE;
+          break;
+        }
+      case RCC_SPI6CLKSOURCE_CSI: /* CSI is the clock source for SPI6 */
+        {
+          frequency = CSI_VALUE;
+          break;
+        }
+      case RCC_SPI6CLKSOURCE_HSE: /* HSE is the clock source for SPI6 */
+        {
+          frequency = HSE_VALUE;
+          break;
+        }
+#if defined(RCC_SPI6CLKSOURCE_PIN)
+      case RCC_SPI6CLKSOURCE_PIN: /* External clock is the clock source for SPI6 */
+        {
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+#endif /* RCC_SPI6CLKSOURCE_PIN */
+      default :
+        {
+          frequency = 0;
+          break;
+        }
+      }
+    }
+  else
+    {
+      frequency = 0;
+    }
+
+  return frequency;
+}
+
+
+/**
+  * @brief  Returns the D1PCLK1 frequency
+  * @note   Each time D1PCLK1 changes, this function must be called to update the
+  *         right D1PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
+  * @retval D1PCLK1 frequency
+  */
+uint32_t HAL_RCCEx_GetD1PCLK1Freq(void)
+{
+#if defined(RCC_D1CFGR_D1PPRE)
+  /* Get HCLK source and Compute D1PCLK1 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1PPRE)>> RCC_D1CFGR_D1PPRE_Pos] & 0x1FU));
+#else
+/* Get HCLK source and Compute D1PCLK1 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE)>> RCC_CDCFGR1_CDPPRE_Pos] & 0x1FU));
+#endif
+}
+
+/**
+  * @brief  Returns the D3PCLK1 frequency
+  * @note   Each time D3PCLK1 changes, this function must be called to update the
+  *         right D3PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
+  * @retval D3PCLK1 frequency
+  */
+uint32_t HAL_RCCEx_GetD3PCLK1Freq(void)
+{
+#if defined(RCC_D3CFGR_D3PPRE)
+  /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE)>> RCC_D3CFGR_D3PPRE_Pos] & 0x1FU));
+#else
+  /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE)>> RCC_SRDCFGR_SRDPPRE_Pos] & 0x1FU));
+#endif
+}
+/**
+* @brief  Returns the PLL2 clock frequencies :PLL2_P_Frequency,PLL2_R_Frequency and PLL2_Q_Frequency
+  * @note   The PLL2 clock frequencies computed by this function is not the real
+  *         frequency in the chip. It is calculated based on the predefined
+  *         constant and the selected clock source:
+  * @note     The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors.
+  * @note   This function can be used by the user application to compute the
+  *         baud-rate for the communication peripherals or configure other parameters.
+  *
+  * @note   Each time PLL2CLK changes, this function must be called to update the
+  *         right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect.
+  * @param  PLL2_Clocks structure.
+  * @retval None
+  */
+void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef* PLL2_Clocks)
+{
+  uint32_t  pllsource, pll2m,  pll2fracen, hsivalue;
+  float_t fracn2, pll2vco;
+
+  /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL2M) * PLL2N
+     PLL2xCLK = PLL2_VCO / PLL2x
+  */
+  pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+  pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2)>> 12);
+  pll2fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) >> RCC_PLLCFGR_PLL2FRACEN_Pos;
+  fracn2 =(float_t)(uint32_t)(pll2fracen* ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2)>> 3));
+
+  if (pll2m != 0U)
+  {
+    switch (pllsource)
+    {
+
+    case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
+
+      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+      {
+        hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
+        pll2vco = ( (float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );
+      }
+      else
+      {
+        pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );
+      }
+      break;
+
+    case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
+      pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );
+      break;
+
+    case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
+      pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );
+      break;
+
+    default:
+      pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );
+      break;
+    }
+    PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >>9)  + (float_t)1 )) ;
+    PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >>16) + (float_t)1 )) ;
+    PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >>24) + (float_t)1 )) ;
+  }
+  else
+  {
+    PLL2_Clocks->PLL2_P_Frequency = 0U;
+    PLL2_Clocks->PLL2_Q_Frequency = 0U;
+    PLL2_Clocks->PLL2_R_Frequency = 0U;
+  }
+}
+
+/**
+* @brief  Returns the PLL3 clock frequencies :PLL3_P_Frequency,PLL3_R_Frequency and PLL3_Q_Frequency
+  * @note   The PLL3 clock frequencies computed by this function is not the real
+  *         frequency in the chip. It is calculated based on the predefined
+  *         constant and the selected clock source:
+  * @note     The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors.
+  * @note   This function can be used by the user application to compute the
+  *         baud-rate for the communication peripherals or configure other parameters.
+  *
+  * @note   Each time PLL3CLK changes, this function must be called to update the
+  *         right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect.
+  * @param  PLL3_Clocks structure.
+  * @retval None
+  */
+void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef* PLL3_Clocks)
+{
+  uint32_t pllsource, pll3m, pll3fracen, hsivalue;
+  float_t fracn3, pll3vco;
+
+  /* PLL3_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL3M) * PLL3N
+     PLL3xCLK = PLL3_VCO / PLLxR
+  */
+  pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+  pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3)>> 20)  ;
+  pll3fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) >> RCC_PLLCFGR_PLL3FRACEN_Pos;
+  fracn3 = (float_t)(uint32_t)(pll3fracen* ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3)>> 3));
+
+  if (pll3m != 0U)
+  {
+    switch (pllsource)
+    {
+    case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
+
+      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+      {
+        hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
+        pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );
+      }
+      else
+      {
+        pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );
+      }
+      break;
+    case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
+      pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );
+      break;
+
+    case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
+      pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );
+      break;
+
+    default:
+      pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );
+      break;
+    }
+    PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >>9)  + (float_t)1 )) ;
+    PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >>16) + (float_t)1 )) ;
+    PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >>24) + (float_t)1 )) ;
+  }
+  else
+  {
+    PLL3_Clocks->PLL3_P_Frequency = 0U;
+    PLL3_Clocks->PLL3_Q_Frequency = 0U;
+    PLL3_Clocks->PLL3_R_Frequency = 0U;
+  }
+
+}
+
+/**
+* @brief  Returns the PLL1 clock frequencies :PLL1_P_Frequency,PLL1_R_Frequency and PLL1_Q_Frequency
+  * @note   The PLL1 clock frequencies computed by this function is not the real
+  *         frequency in the chip. It is calculated based on the predefined
+  *         constant and the selected clock source:
+  * @note     The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors.
+  * @note   This function can be used by the user application to compute the
+  *         baud-rate for the communication peripherals or configure other parameters.
+  *
+  * @note   Each time PLL1CLK changes, this function must be called to update the
+  *         right PLL1CLK value. Otherwise, any configuration based on this function will be incorrect.
+  * @param  PLL1_Clocks structure.
+  * @retval None
+  */
+void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef* PLL1_Clocks)
+{
+  uint32_t pllsource, pll1m, pll1fracen, hsivalue;
+  float_t fracn1, pll1vco;
+
+  pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+  pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4);
+  pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN;
+  fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
+
+  if (pll1m != 0U)
+  {
+    switch (pllsource)
+    {
+
+    case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
+
+      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+      {
+        hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
+        pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+      }
+      else
+      {
+        pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+      }
+      break;
+    case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
+      pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+      break;
+
+    case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
+      pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+      break;
+
+    default:
+      pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+      break;
+    }
+
+    PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9)  + (float_t)1 )) ;
+    PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >>16) + (float_t)1 )) ;
+    PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >>24) + (float_t)1 )) ;
+  }
+  else
+  {
+    PLL1_Clocks->PLL1_P_Frequency = 0U;
+    PLL1_Clocks->PLL1_Q_Frequency = 0U;
+    PLL1_Clocks->PLL1_R_Frequency = 0U;
+  }
+
+}
+
+/**
+  * @brief  Returns the main System frequency
+  * @note   Each time System clock changes, this function must be called to update the
+  *         right core clock value. Otherwise, any configuration based on this function will be incorrect.
+  * @note   The SystemCoreClock CMSIS variable is used to store System current Core Clock Frequency
+  *         and updated within this function
+  * @retval HCLK frequency
+  */
+uint32_t HAL_RCCEx_GetD1SysClockFreq(void)
+{
+uint32_t common_system_clock;
+
+#if defined(RCC_D1CFGR_D1CPRE)
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
+#else
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU);
+#endif
+
+  /* Update the SystemD2Clock global variable */
+#if defined(RCC_D1CFGR_HPRE)
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+#else
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+#endif
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  SystemCoreClock = SystemD2Clock;
+#else
+  SystemCoreClock = common_system_clock;
+#endif /* DUAL_CORE && CORE_CM4 */
+
+  return common_system_clock;
+}
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_Exported_Functions_Group2 Extended System Control functions
+ *  @brief  Extended Peripheral Control functions
+  * @{
+  */
+/**
+  * @brief  Enables the LSE Clock Security System.
+  * @note   Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled
+  *         with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC
+  *         clock with HAL_RCCEx_PeriphCLKConfig().
+  * @retval None
+  */
+void HAL_RCCEx_EnableLSECSS(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
+}
+
+/**
+  * @brief  Disables the LSE Clock Security System.
+  * @note   LSE Clock Security System can only be disabled after a LSE failure detection.
+  * @retval None
+  */
+void HAL_RCCEx_DisableLSECSS(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
+  /* Disable LSE CSS IT if any */
+  __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS);
+}
+
+/**
+  * @brief  Enable the LSE Clock Security System Interrupt & corresponding EXTI line.
+  * @note   LSE Clock Security System Interrupt is mapped on EXTI line 18
+  * @retval None
+  */
+void HAL_RCCEx_EnableLSECSS_IT(void)
+{
+  /* Enable LSE CSS */
+  SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
+
+  /* Enable LSE CSS IT */
+  __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS);
+
+  /* Enable IT on EXTI Line 18 */
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  __HAL_RCC_C2_LSECSS_EXTI_ENABLE_IT();
+#else
+  __HAL_RCC_LSECSS_EXTI_ENABLE_IT();
+#endif /* DUAL_CORE && CORE_CM4 */
+  __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();
+}
+
+/**
+  * @brief  Configure the oscillator clock source for wakeup from Stop and CSS backup clock
+  * @param  WakeUpClk: Wakeup clock
+  *         This parameter can be one of the following values:
+  *            @arg RCC_STOP_WAKEUPCLOCK_CSI: CSI oscillator selection
+  *            @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI oscillator selection
+  * @note   This function shall not be called after the Clock Security System on HSE has been
+  *         enabled.
+  * @retval None
+  */
+void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)
+{
+  assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk));
+
+  __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk);
+}
+
+/**
+  * @brief  Configure the oscillator Kernel clock source for wakeup from Stop
+  * @param  WakeUpClk: Kernel Wakeup clock
+  *         This parameter can be one of the following values:
+  *            @arg RCC_STOP_KERWAKEUPCLOCK_CSI: CSI oscillator selection
+  *            @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI oscillator selection
+  * @retval None
+  */
+void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk)
+{
+  assert_param(IS_RCC_STOP_KERWAKEUPCLOCK(WakeUpClk));
+
+  __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(WakeUpClk);
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Enable COREx boot independently of CMx_B option byte value
+  * @param  RCC_BootCx: Boot Core to be enabled
+  *         This parameter can be one of the following values:
+  *            @arg RCC_BOOT_C1: CM7 core selection
+  *            @arg RCC_BOOT_C2: CM4 core selection
+  * @note   This bit can be set by software but is cleared by hardware after a system reset or STANDBY
+  *
+  * @retval None
+  */
+void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx)
+{
+  assert_param(IS_RCC_BOOT_CORE(RCC_BootCx));
+  SET_BIT(RCC->GCR, RCC_BootCx) ;
+}
+
+#endif /*DUAL_CORE*/
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Configure WWDGx to generate a system reset not only CPUx reset(default) when a time-out occurs
+  * @param  RCC_WWDGx: WWDGx to be configured
+  *         This parameter can be one of the following values:
+  *            @arg RCC_WWDG1: WWDG1 generates system reset
+  *            @arg RCC_WWDG2: WWDG2 generates system reset
+  * @note   This bit can be set by software but is cleared by hardware during a system reset
+  *
+  * @retval None
+  */
+void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx)
+{
+  assert_param(IS_RCC_SCOPE_WWDG(RCC_WWDGx));
+  SET_BIT(RCC->GCR, RCC_WWDGx) ;
+}
+
+#else
+#if defined(RCC_GCR_WW1RSC)
+/**
+  * @brief  Configure WWDG1 to generate a system reset not only CPU reset(default) when a time-out occurs
+  * @param  RCC_WWDGx: WWDGx to be configured
+  *         This parameter can be one of the following values:
+  *            @arg RCC_WWDG1: WWDG1 generates system reset
+  * @note   This bit can be set by software but is cleared by hardware during a system reset
+  *
+  * @retval None
+  */
+void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx)
+{
+  assert_param(IS_RCC_SCOPE_WWDG(RCC_WWDGx));
+  SET_BIT(RCC->GCR, RCC_WWDGx) ;
+}
+#endif
+#endif /*DUAL_CORE*/
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions
+ *  @brief  Extended Clock Recovery System Control functions
+ *
+@verbatim
+ ===============================================================================
+                ##### Extended Clock Recovery System Control functions  #####
+ ===============================================================================
+    [..]
+      For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows:
+
+      (#) In System clock config, HSI48 needs to be enabled
+
+      (#) Enable CRS clock in IP MSP init which will use CRS functions
+
+      (#) Call CRS functions as follows:
+          (##) Prepare synchronization configuration necessary for HSI48 calibration
+              (+++) Default values can be set for frequency Error Measurement (reload and error limit)
+                        and also HSI48 oscillator smooth trimming.
+              (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
+                        directly reload value with target and synchronization frequencies values
+          (##) Call function HAL_RCCEx_CRSConfig which
+              (+++) Resets CRS registers to their default values.
+              (+++) Configures CRS registers with synchronization configuration
+              (+++) Enables automatic calibration and frequency error counter feature
+           Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the
+           periodic USB SOF will not be generated by the host. No SYNC signal will therefore be
+           provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock
+           precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs
+           should be used as SYNC signal.
+
+          (##) A polling function is provided to wait for complete synchronization
+              (+++) Call function HAL_RCCEx_CRSWaitSynchronization()
+              (+++) According to CRS status, user can decide to adjust again the calibration or continue
+                        application if synchronization is OK
+
+      (#) User can retrieve information related to synchronization in calling function
+            HAL_RCCEx_CRSGetSynchronizationInfo()
+
+      (#) Regarding synchronization status and synchronization information, user can try a new calibration
+           in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
+           Note: When the SYNC event is detected during the down-counting phase (before reaching the zero value),
+           it means that the actual frequency is lower than the target (and so, that the TRIM value should be
+           incremented), while when it is detected during the up-counting phase it means that the actual frequency
+           is higher (and that the TRIM value should be decremented).
+
+      (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go
+          through CRS Handler (CRS_IRQn/CRS_IRQHandler)
+              (++) Call function HAL_RCCEx_CRSConfig()
+              (++) Enable CRS_IRQn (thanks to NVIC functions)
+              (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT)
+              (++) Implement CRS status management in the following user callbacks called from
+                   HAL_RCCEx_CRS_IRQHandler():
+                   (+++) HAL_RCCEx_CRS_SyncOkCallback()
+                   (+++) HAL_RCCEx_CRS_SyncWarnCallback()
+                   (+++) HAL_RCCEx_CRS_ExpectedSyncCallback()
+                   (+++) HAL_RCCEx_CRS_ErrorCallback()
+
+      (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate().
+          This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler)
+
+@endverbatim
+ * @{
+ */
+
+/**
+  * @brief  Start automatic synchronization for polling mode
+  * @param  pInit Pointer on RCC_CRSInitTypeDef structure
+  * @retval None
+  */
+void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
+{
+  uint32_t value;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));
+  assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));
+  assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));
+  assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));
+  assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));
+  assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));
+
+  /* CONFIGURATION */
+
+  /* Before configuration, reset CRS registers to their default values*/
+  __HAL_RCC_CRS_FORCE_RESET();
+  __HAL_RCC_CRS_RELEASE_RESET();
+
+  /* Set the SYNCDIV[2:0] bits according to Pre-scaler value */
+  /* Set the SYNCSRC[1:0] bits according to Source value */
+  /* Set the SYNCSPOL bit according to Polarity value */
+  if ((HAL_GetREVID() <= REV_ID_Y) && (pInit->Source == RCC_CRS_SYNC_SOURCE_USB2))
+  {
+    /* Use Rev.Y value of USB2 */
+    value = (pInit->Prescaler | RCC_CRS_SYNC_SOURCE_PIN | pInit->Polarity);
+  }
+  else
+  {
+    value = (pInit->Prescaler | pInit->Source | pInit->Polarity);
+  }
+  /* Set the RELOAD[15:0] bits according to ReloadValue value */
+  value |= pInit->ReloadValue;
+  /* Set the FELIM[7:0] bits according to ErrorLimitValue value */
+  value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos);
+  WRITE_REG(CRS->CFGR, value);
+
+  /* Adjust HSI48 oscillator smooth trimming */
+  /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */
+  MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos));
+
+  /* START AUTOMATIC SYNCHRONIZATION*/
+
+  /* Enable Automatic trimming & Frequency error counter */
+  SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN);
+}
+
+/**
+  * @brief  Generate the software synchronization event
+  * @retval None
+  */
+void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_SWSYNC);
+}
+
+/**
+  * @brief  Return synchronization info
+  * @param  pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
+  * @retval None
+  */
+void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
+{
+  /* Check the parameter */
+  assert_param(pSynchroInfo != (void *)NULL);
+
+  /* Get the reload value */
+  pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
+
+  /* Get HSI48 oscillator smooth trimming */
+  pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
+
+  /* Get Frequency error capture */
+  pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
+
+  /* Get Frequency error direction */
+  pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
+}
+
+/**
+* @brief Wait for CRS Synchronization status.
+* @param Timeout  Duration of the time-out
+* @note  Timeout is based on the maximum time to receive a SYNC event based on synchronization
+*        frequency.
+* @note    If Time-out set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
+* @retval Combination of Synchronization status
+*          This parameter can be a combination of the following values:
+*            @arg @ref RCC_CRS_TIMEOUT
+*            @arg @ref RCC_CRS_SYNCOK
+*            @arg @ref RCC_CRS_SYNCWARN
+*            @arg @ref RCC_CRS_SYNCERR
+*            @arg @ref RCC_CRS_SYNCMISS
+*            @arg @ref RCC_CRS_TRIMOVF
+*/
+uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
+{
+  uint32_t crsstatus = RCC_CRS_NONE;
+  uint32_t tickstart;
+
+  /* Get time-out */
+  tickstart = HAL_GetTick();
+
+  /* Wait for CRS flag or time-out detection */
+  do
+  {
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+      {
+        crsstatus = RCC_CRS_TIMEOUT;
+      }
+    }
+    /* Check CRS SYNCOK flag  */
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))
+    {
+      /* CRS SYNC event OK */
+      crsstatus |= RCC_CRS_SYNCOK;
+
+      /* Clear CRS SYNC event OK bit */
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);
+    }
+
+    /* Check CRS SYNCWARN flag  */
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))
+    {
+      /* CRS SYNC warning */
+      crsstatus |= RCC_CRS_SYNCWARN;
+
+      /* Clear CRS SYNCWARN bit */
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);
+    }
+
+    /* Check CRS TRIM overflow flag  */
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))
+    {
+      /* CRS SYNC Error */
+      crsstatus |= RCC_CRS_TRIMOVF;
+
+      /* Clear CRS Error bit */
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);
+    }
+
+    /* Check CRS Error flag  */
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))
+    {
+      /* CRS SYNC Error */
+      crsstatus |= RCC_CRS_SYNCERR;
+
+      /* Clear CRS Error bit */
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);
+    }
+
+    /* Check CRS SYNC Missed flag  */
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))
+    {
+      /* CRS SYNC Missed */
+      crsstatus |= RCC_CRS_SYNCMISS;
+
+      /* Clear CRS SYNC Missed bit */
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);
+    }
+
+    /* Check CRS Expected SYNC flag  */
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))
+    {
+      /* frequency error counter reached a zero value */
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
+    }
+  } while(RCC_CRS_NONE == crsstatus);
+
+  return crsstatus;
+}
+
+/**
+  * @brief Handle the Clock Recovery System interrupt request.
+  * @retval None
+  */
+void HAL_RCCEx_CRS_IRQHandler(void)
+{
+  uint32_t crserror = RCC_CRS_NONE;
+  /* Get current IT flags and IT sources values */
+  uint32_t itflags = READ_REG(CRS->ISR);
+  uint32_t itsources = READ_REG(CRS->CR);
+
+  /* Check CRS SYNCOK flag  */
+  if(((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U))
+  {
+    /* Clear CRS SYNC event OK flag */
+    WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
+
+    /* user callback */
+    HAL_RCCEx_CRS_SyncOkCallback();
+  }
+  /* Check CRS SYNCWARN flag  */
+  else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U))
+  {
+    /* Clear CRS SYNCWARN flag */
+    WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
+
+    /* user callback */
+    HAL_RCCEx_CRS_SyncWarnCallback();
+  }
+  /* Check CRS Expected SYNC flag  */
+  else if(((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U))
+  {
+    /* frequency error counter reached a zero value */
+    WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
+
+    /* user callback */
+    HAL_RCCEx_CRS_ExpectedSyncCallback();
+  }
+  /* Check CRS Error flags  */
+  else
+  {
+    if(((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U))
+    {
+      if((itflags & RCC_CRS_FLAG_SYNCERR) != 0U)
+      {
+        crserror |= RCC_CRS_SYNCERR;
+      }
+      if((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U)
+      {
+        crserror |= RCC_CRS_SYNCMISS;
+      }
+      if((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U)
+      {
+        crserror |= RCC_CRS_TRIMOVF;
+      }
+
+      /* Clear CRS Error flags */
+      WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
+
+      /* user error callback */
+      HAL_RCCEx_CRS_ErrorCallback(crserror);
+    }
+  }
+}
+
+/**
+  * @brief  RCCEx Clock Recovery System SYNCOK interrupt callback.
+  * @retval none
+  */
+__weak void HAL_RCCEx_CRS_SyncOkCallback(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file
+   */
+}
+
+/**
+  * @brief  RCCEx Clock Recovery System SYNCWARN interrupt callback.
+  * @retval none
+  */
+__weak void HAL_RCCEx_CRS_SyncWarnCallback(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file
+   */
+}
+
+/**
+  * @brief  RCCEx Clock Recovery System Expected SYNC interrupt callback.
+  * @retval none
+  */
+__weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file
+   */
+}
+
+/**
+  * @brief  RCCEx Clock Recovery System Error interrupt callback.
+  * @param  Error Combination of Error status.
+  *         This parameter can be a combination of the following values:
+  *           @arg @ref RCC_CRS_SYNCERR
+  *           @arg @ref RCC_CRS_SYNCMISS
+  *           @arg @ref RCC_CRS_TRIMOVF
+  * @retval none
+  */
+__weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(Error);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file
+   */
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_Private_functions Private Functions
+ * @{
+ */
+/**
+  * @brief  Configure the PLL2 VCI,VCO ranges, multiplication and division factors and enable it
+  * @param  pll2: Pointer to an RCC_PLL2InitTypeDef structure that
+  *         contains the configuration parameters  as well as VCI, VCO clock ranges.
+  * @param  Divider  divider parameter to be updated
+  * @note   PLL2 is temporary disabled to apply new parameters
+  *
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider)
+{
+
+  uint32_t tickstart;
+  HAL_StatusTypeDef status = HAL_OK;
+  assert_param(IS_RCC_PLL2M_VALUE(pll2->PLL2M));
+  assert_param(IS_RCC_PLL2N_VALUE(pll2->PLL2N));
+  assert_param(IS_RCC_PLL2P_VALUE(pll2->PLL2P));
+  assert_param(IS_RCC_PLL2R_VALUE(pll2->PLL2R));
+  assert_param(IS_RCC_PLL2Q_VALUE(pll2->PLL2Q));
+  assert_param(IS_RCC_PLL2RGE_VALUE(pll2->PLL2RGE));
+  assert_param(IS_RCC_PLL2VCO_VALUE(pll2->PLL2VCOSEL));
+  assert_param(IS_RCC_PLLFRACN_VALUE(pll2->PLL2FRACN));
+
+  /* Check that PLL2 OSC clock source is already set */
+  if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
+  {
+    return HAL_ERROR;
+  }
+
+
+  else
+  {
+    /* Disable  PLL2. */
+    __HAL_RCC_PLL2_DISABLE();
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+
+    /* Wait till PLL is disabled */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U)
+    {
+      if( (HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Configure PLL2 multiplication and division factors. */
+    __HAL_RCC_PLL2_CONFIG(pll2->PLL2M,
+                          pll2->PLL2N,
+                          pll2->PLL2P,
+                          pll2->PLL2Q,
+                          pll2->PLL2R);
+
+    /* Select PLL2 input reference frequency range: VCI */
+    __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE) ;
+
+    /* Select PLL2 output frequency range : VCO */
+    __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ;
+
+    /* Disable PLL2FRACN . */
+    __HAL_RCC_PLL2FRACN_DISABLE();
+
+    /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */
+    __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN);
+
+    /* Enable PLL2FRACN . */
+    __HAL_RCC_PLL2FRACN_ENABLE();
+
+    /* Enable the PLL2 clock output */
+    if(Divider == DIVIDER_P_UPDATE)
+    {
+      __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP);
+    }
+    else if(Divider == DIVIDER_Q_UPDATE)
+    {
+      __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ);
+    }
+    else
+    {
+      __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR);
+    }
+
+    /* Enable  PLL2. */
+    __HAL_RCC_PLL2_ENABLE();
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+
+    /* Wait till PLL2 is ready */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U)
+    {
+      if( (HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+
+  }
+
+
+  return status;
+}
+
+
+/**
+  * @brief  Configure the PLL3 VCI,VCO ranges, multiplication and division factors and enable it
+  * @param  pll3: Pointer to an RCC_PLL3InitTypeDef structure that
+  *         contains the configuration parameters  as well as VCI, VCO clock ranges.
+  * @param  Divider  divider parameter to be updated
+  * @note   PLL3 is temporary disabled to apply new parameters
+  *
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider)
+{
+  uint32_t tickstart;
+  HAL_StatusTypeDef status = HAL_OK;
+  assert_param(IS_RCC_PLL3M_VALUE(pll3->PLL3M));
+  assert_param(IS_RCC_PLL3N_VALUE(pll3->PLL3N));
+  assert_param(IS_RCC_PLL3P_VALUE(pll3->PLL3P));
+  assert_param(IS_RCC_PLL3R_VALUE(pll3->PLL3R));
+  assert_param(IS_RCC_PLL3Q_VALUE(pll3->PLL3Q));
+  assert_param(IS_RCC_PLL3RGE_VALUE(pll3->PLL3RGE));
+  assert_param(IS_RCC_PLL3VCO_VALUE(pll3->PLL3VCOSEL));
+  assert_param(IS_RCC_PLLFRACN_VALUE(pll3->PLL3FRACN));
+
+  /* Check that PLL3 OSC clock source is already set */
+  if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
+  {
+    return HAL_ERROR;
+  }
+
+
+  else
+  {
+    /* Disable  PLL3. */
+    __HAL_RCC_PLL3_DISABLE();
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+    /* Wait till PLL3 is ready */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U)
+    {
+      if( (HAL_GetTick() - tickstart ) > PLL3_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Configure the PLL3  multiplication and division factors. */
+    __HAL_RCC_PLL3_CONFIG(pll3->PLL3M,
+                          pll3->PLL3N,
+                          pll3->PLL3P,
+                          pll3->PLL3Q,
+                          pll3->PLL3R);
+
+    /* Select PLL3 input reference frequency range: VCI */
+    __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ;
+
+    /* Select PLL3 output frequency range : VCO */
+    __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ;
+
+    /* Disable PLL3FRACN . */
+    __HAL_RCC_PLL3FRACN_DISABLE();
+
+    /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */
+    __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN);
+
+    /* Enable PLL3FRACN . */
+    __HAL_RCC_PLL3FRACN_ENABLE();
+
+    /* Enable the PLL3 clock output */
+    if(Divider == DIVIDER_P_UPDATE)
+    {
+      __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP);
+    }
+    else if(Divider == DIVIDER_Q_UPDATE)
+    {
+      __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
+    }
+    else
+    {
+      __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
+    }
+
+    /* Enable  PLL3. */
+    __HAL_RCC_PLL3_ENABLE();
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+
+    /* Wait till PLL3 is ready */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U)
+    {
+      if( (HAL_GetTick() - tickstart ) > PLL3_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+
+  }
+
+
+  return status;
+}
+
+/**
+  * @brief Handle the RCC LSE Clock Security System interrupt request.
+  * @retval None
+  */
+void HAL_RCCEx_LSECSS_IRQHandler(void)
+{
+  /* Check RCC LSE CSSF flag  */
+  if(__HAL_RCC_GET_IT(RCC_IT_LSECSS))
+  {
+
+    /* Clear RCC LSE CSS pending bit */
+    __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS);
+
+    /* RCC LSE Clock Security System interrupt user callback */
+    HAL_RCCEx_LSECSS_Callback();
+
+  }
+}
+
+/**
+  * @brief  RCCEx LSE Clock Security System interrupt callback.
+  * @retval none
+  */
+__weak void HAL_RCCEx_LSECSS_Callback(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file
+   */
+}
+
+
+
+/**
+  * @}
+  */
+
+#endif /* HAL_RCC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c
new file mode 100644
index 00000000..1885d04b
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c
@@ -0,0 +1,7047 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_tim.c
+  * @author  MCD Application Team
+  * @brief   TIM HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Timer (TIM) peripheral:
+  *           + TIM Time Base Initialization
+  *           + TIM Time Base Start
+  *           + TIM Time Base Start Interruption
+  *           + TIM Time Base Start DMA
+  *           + TIM Output Compare/PWM Initialization
+  *           + TIM Output Compare/PWM Channel Configuration
+  *           + TIM Output Compare/PWM  Start
+  *           + TIM Output Compare/PWM  Start Interruption
+  *           + TIM Output Compare/PWM Start DMA
+  *           + TIM Input Capture Initialization
+  *           + TIM Input Capture Channel Configuration
+  *           + TIM Input Capture Start
+  *           + TIM Input Capture Start Interruption
+  *           + TIM Input Capture Start DMA
+  *           + TIM One Pulse Initialization
+  *           + TIM One Pulse Channel Configuration
+  *           + TIM One Pulse Start
+  *           + TIM Encoder Interface Initialization
+  *           + TIM Encoder Interface Start
+  *           + TIM Encoder Interface Start Interruption
+  *           + TIM Encoder Interface Start DMA
+  *           + Commutation Event configuration with Interruption and DMA
+  *           + TIM OCRef clear configuration
+  *           + TIM External Clock configuration
+  @verbatim
+  ==============================================================================
+                      ##### TIMER Generic features #####
+  ==============================================================================
+  [..] The Timer features include:
+       (#) 16-bit up, down, up/down auto-reload counter.
+       (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
+           counter clock frequency either by any factor between 1 and 65536.
+       (#) Up to 4 independent channels for:
+           (++) Input Capture
+           (++) Output Compare
+           (++) PWM generation (Edge and Center-aligned Mode)
+           (++) One-pulse mode output
+       (#) Synchronization circuit to control the timer with external signals and to interconnect
+            several timers together.
+       (#) Supports incremental encoder for positioning purposes
+
+            ##### How to use this driver #####
+  ==============================================================================
+    [..]
+     (#) Initialize the TIM low level resources by implementing the following functions
+         depending on the selected feature:
+           (++) Time Base : HAL_TIM_Base_MspInit()
+           (++) Input Capture : HAL_TIM_IC_MspInit()
+           (++) Output Compare : HAL_TIM_OC_MspInit()
+           (++) PWM generation : HAL_TIM_PWM_MspInit()
+           (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
+           (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
+
+     (#) Initialize the TIM low level resources :
+        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
+        (##) TIM pins configuration
+            (+++) Enable the clock for the TIM GPIOs using the following function:
+             __HAL_RCC_GPIOx_CLK_ENABLE();
+            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
+
+     (#) The external Clock can be configured, if needed (the default clock is the
+         internal clock from the APBx), using the following function:
+         HAL_TIM_ConfigClockSource, the clock configuration should be done before
+         any start function.
+
+     (#) Configure the TIM in the desired functioning mode using one of the
+       Initialization function of this driver:
+       (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
+       (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
+            Output Compare signal.
+       (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
+            PWM signal.
+       (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
+            external signal.
+       (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
+            in One Pulse Mode.
+       (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
+
+     (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
+           (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
+           (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
+           (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
+           (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
+           (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
+           (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
+
+     (#) The DMA Burst is managed with the two following functions:
+         HAL_TIM_DMABurst_WriteStart()
+         HAL_TIM_DMABurst_ReadStart()
+
+    *** Callback registration ***
+  =============================================
+
+  [..]
+  The compilation define  USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
+  allows the user to configure dynamically the driver callbacks.
+
+  [..]
+  Use Function @ref HAL_TIM_RegisterCallback() to register a callback.
+  @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
+  the Callback ID and a pointer to the user callback function.
+
+  [..]
+  Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default
+  weak function.
+  @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
+  and the Callback ID.
+
+  [..]
+  These functions allow to register/unregister following callbacks:
+    (+) Base_MspInitCallback              : TIM Base Msp Init Callback.
+    (+) Base_MspDeInitCallback            : TIM Base Msp DeInit Callback.
+    (+) IC_MspInitCallback                : TIM IC Msp Init Callback.
+    (+) IC_MspDeInitCallback              : TIM IC Msp DeInit Callback.
+    (+) OC_MspInitCallback                : TIM OC Msp Init Callback.
+    (+) OC_MspDeInitCallback              : TIM OC Msp DeInit Callback.
+    (+) PWM_MspInitCallback               : TIM PWM Msp Init Callback.
+    (+) PWM_MspDeInitCallback             : TIM PWM Msp DeInit Callback.
+    (+) OnePulse_MspInitCallback          : TIM One Pulse Msp Init Callback.
+    (+) OnePulse_MspDeInitCallback        : TIM One Pulse Msp DeInit Callback.
+    (+) Encoder_MspInitCallback           : TIM Encoder Msp Init Callback.
+    (+) Encoder_MspDeInitCallback         : TIM Encoder Msp DeInit Callback.
+    (+) HallSensor_MspInitCallback        : TIM Hall Sensor Msp Init Callback.
+    (+) HallSensor_MspDeInitCallback      : TIM Hall Sensor Msp DeInit Callback.
+    (+) PeriodElapsedCallback             : TIM Period Elapsed Callback.
+    (+) PeriodElapsedHalfCpltCallback     : TIM Period Elapsed half complete Callback.
+    (+) TriggerCallback                   : TIM Trigger Callback.
+    (+) TriggerHalfCpltCallback           : TIM Trigger half complete Callback.
+    (+) IC_CaptureCallback                : TIM Input Capture Callback.
+    (+) IC_CaptureHalfCpltCallback        : TIM Input Capture half complete Callback.
+    (+) OC_DelayElapsedCallback           : TIM Output Compare Delay Elapsed Callback.
+    (+) PWM_PulseFinishedCallback         : TIM PWM Pulse Finished Callback.
+    (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
+    (+) ErrorCallback                     : TIM Error Callback.
+    (+) CommutationCallback               : TIM Commutation Callback.
+    (+) CommutationHalfCpltCallback       : TIM Commutation half complete Callback.
+    (+) BreakCallback                     : TIM Break Callback.
+    (+) Break2Callback                    : TIM Break2 Callback.
+
+  [..]
+By default, after the Init and when the state is HAL_TIM_STATE_RESET
+all interrupt callbacks are set to the corresponding weak functions:
+  examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().
+
+  [..]
+  Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
+  functionalities in the Init / DeInit only when these callbacks are null
+  (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
+    keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
+
+  [..]
+    Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
+    Exception done MspInit / MspDeInit that can be registered / unregistered
+    in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
+    thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
+  In that case first register the MspInit/MspDeInit user callbacks
+      using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.
+
+  [..]
+      When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
+      not defined, the callback registration feature is not available and all callbacks
+      are set to the corresponding weak functions.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup TIM TIM
+  * @brief TIM HAL module driver
+  * @{
+  */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup TIM_Private_Functions
+  * @{
+  */
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter);
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter);
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter);
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+                                                  TIM_SlaveConfigTypeDef *sSlaveConfig);
+/**
+  * @}
+  */
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup TIM_Exported_Functions TIM Exported Functions
+  * @{
+  */
+
+/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
+  *  @brief    Time Base functions
+  *
+@verbatim
+  ==============================================================================
+              ##### Time Base functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM base.
+    (+) De-initialize the TIM base.
+    (+) Start the Time Base.
+    (+) Stop the Time Base.
+    (+) Start the Time Base and enable interrupt.
+    (+) Stop the Time Base and disable interrupt.
+    (+) Start the Time Base and enable DMA transfer.
+    (+) Stop the Time Base and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Time base Unit according to the specified
+  *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->Base_MspInitCallback == NULL)
+    {
+      htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->Base_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    HAL_TIM_Base_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Set the Time Base configuration */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM Base peripheral
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->Base_MspDeInitCallback == NULL)
+  {
+    htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->Base_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIM_Base_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Base MSP.
+  * @param  htim TIM Base handle
+  * @retval None
+  */
+__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_Base_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Base MSP.
+  * @param  htim TIM Base handle
+  * @retval None
+  */
+__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_Base_MspDeInit could be implemented in the user file
+   */
+}
+
+
+/**
+  * @brief  Starts the TIM Base generation.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Change the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Base generation.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Base generation in interrupt mode.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  /* Enable the TIM Update interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Base generation in interrupt mode.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  /* Disable the TIM Update interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Base generation in DMA mode.
+  * @param  htim TIM Base handle
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if ((pData == NULL) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+  /* Set the DMA Period elapsed callbacks */
+  htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+  htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+
+  /* Set the DMA error callback */
+  htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+  /* Enable the DMA stream */
+  if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Enable the TIM Update DMA request */
+  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Base generation in DMA mode.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+
+  /* Disable the TIM Update DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
+
+  (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
+  *  @brief    TIM Output Compare functions
+  *
+@verbatim
+  ==============================================================================
+                  ##### TIM Output Compare functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM Output Compare.
+    (+) De-initialize the TIM Output Compare.
+    (+) Start the TIM Output Compare.
+    (+) Stop the TIM Output Compare.
+    (+) Start the TIM Output Compare and enable interrupt.
+    (+) Stop the TIM Output Compare and disable interrupt.
+    (+) Start the TIM Output Compare and enable DMA transfer.
+    (+) Stop the TIM Output Compare and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Output Compare according to the specified
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
+  * @param  htim TIM Output Compare handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->OC_MspInitCallback == NULL)
+    {
+      htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->OC_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_OC_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Init the base time for the Output Compare */
+  TIM_Base_SetConfig(htim->Instance,  &htim->Init);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM peripheral
+  * @param  htim TIM Output Compare handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->OC_MspDeInitCallback == NULL)
+  {
+    htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->OC_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+  HAL_TIM_OC_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Output Compare MSP.
+  * @param  htim TIM Output Compare handle
+  * @retval None
+  */
+__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OC_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Output Compare MSP.
+  * @param  htim TIM Output Compare handle
+  * @retval None
+  */
+__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OC_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Enable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in interrupt mode.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Enable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Enable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in interrupt mode.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Disable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in DMA mode.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if ((pData == NULL) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Enable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 4 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Enable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in DMA mode.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Disable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
+  *  @brief    TIM PWM functions
+  *
+@verbatim
+  ==============================================================================
+                          ##### TIM PWM functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM PWM.
+    (+) De-initialize the TIM PWM.
+    (+) Start the TIM PWM.
+    (+) Stop the TIM PWM.
+    (+) Start the TIM PWM and enable interrupt.
+    (+) Stop the TIM PWM and disable interrupt.
+    (+) Start the TIM PWM and enable DMA transfer.
+    (+) Stop the TIM PWM and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM PWM Time Base according to the specified
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
+  * @param  htim TIM PWM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->PWM_MspInitCallback == NULL)
+    {
+      htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->PWM_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_PWM_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Init the base time for the PWM */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM peripheral
+  * @param  htim TIM PWM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->PWM_MspDeInitCallback == NULL)
+  {
+    htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->PWM_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+  HAL_TIM_PWM_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM PWM MSP.
+  * @param  htim TIM PWM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM PWM MSP.
+  * @param  htim TIM PWM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the PWM signal generation.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Enable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the PWM signal generation.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the PWM signal generation in interrupt mode.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Enable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Enable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the PWM signal generation in interrupt mode.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Disable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM PWM signal generation in DMA mode.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if ((pData == NULL) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Output Capture/Compare 3 request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 4 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Enable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM PWM signal generation in DMA mode.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Disable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
+  *  @brief    TIM Input Capture functions
+  *
+@verbatim
+  ==============================================================================
+              ##### TIM Input Capture functions #####
+  ==============================================================================
+ [..]
+   This section provides functions allowing to:
+   (+) Initialize and configure the TIM Input Capture.
+   (+) De-initialize the TIM Input Capture.
+   (+) Start the TIM Input Capture.
+   (+) Stop the TIM Input Capture.
+   (+) Start the TIM Input Capture and enable interrupt.
+   (+) Stop the TIM Input Capture and disable interrupt.
+   (+) Start the TIM Input Capture and enable DMA transfer.
+   (+) Stop the TIM Input Capture and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Input Capture Time base according to the specified
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
+  * @param  htim TIM Input Capture handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->IC_MspInitCallback == NULL)
+    {
+      htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->IC_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_IC_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Init the base time for the input capture */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM peripheral
+  * @param  htim TIM Input Capture handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->IC_MspDeInitCallback == NULL)
+  {
+    htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->IC_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+  HAL_TIM_IC_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Input Capture MSP.
+  * @param  htim TIM Input Capture handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Input Capture MSP.
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Input Capture measurement.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Enable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Input Capture measurement.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Input Capture measurement in interrupt mode.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Enable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      break;
+  }
+  /* Enable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Input Capture measurement in interrupt mode.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Disable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Input Capture measurement in DMA mode.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  pData The destination Buffer address.
+  * @param  Length The length of data to be transferred from TIM peripheral to memory.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if ((pData == NULL) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 2  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 3  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 4  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Enable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Input Capture measurement in DMA mode.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3  DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4  DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Disable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
+  *  @brief    TIM One Pulse functions
+  *
+@verbatim
+  ==============================================================================
+                        ##### TIM One Pulse functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM One Pulse.
+    (+) De-initialize the TIM One Pulse.
+    (+) Start the TIM One Pulse.
+    (+) Stop the TIM One Pulse.
+    (+) Start the TIM One Pulse and enable interrupt.
+    (+) Stop the TIM One Pulse and disable interrupt.
+    (+) Start the TIM One Pulse and enable DMA transfer.
+    (+) Stop the TIM One Pulse and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM One Pulse Time Base according to the specified
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
+  * @param  htim TIM One Pulse handle
+  * @param  OnePulseMode Select the One pulse mode.
+  *         This parameter can be one of the following values:
+  *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
+  *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_OPM_MODE(OnePulseMode));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->OnePulse_MspInitCallback == NULL)
+    {
+      htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->OnePulse_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_OnePulse_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Configure the Time base in the One Pulse Mode */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Reset the OPM Bit */
+  htim->Instance->CR1 &= ~TIM_CR1_OPM;
+
+  /* Configure the OPM Mode */
+  htim->Instance->CR1 |= OnePulseMode;
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM One Pulse
+  * @param  htim TIM One Pulse handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->OnePulse_MspDeInitCallback == NULL)
+  {
+    htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->OnePulse_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIM_OnePulse_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM One Pulse MSP.
+  * @param  htim TIM One Pulse handle
+  * @retval None
+  */
+__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OnePulse_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM One Pulse MSP.
+  * @param  htim TIM One Pulse handle
+  * @retval None
+  */
+__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation.
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Enable the Capture compare and the Input Capture channels
+    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+    in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+
+    No need to enable the counter, it's enabled automatically by hardware
+    (the counter starts in response to a stimulus and generate a pulse */
+
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM One Pulse signal generation.
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channels to be disable
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Disable the Capture compare and the Input Capture channels
+  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+  in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation in interrupt mode.
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Enable the Capture compare and the Input Capture channels
+    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+    in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+
+    No need to enable the counter, it's enabled automatically by hardware
+    (the counter starts in response to a stimulus and generate a pulse */
+
+  /* Enable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+  /* Enable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM One Pulse signal generation in interrupt mode.
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Disable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+  /* Disable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+
+  /* Disable the Capture compare and the Input Capture channels
+  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+  in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
+  *  @brief    TIM Encoder functions
+  *
+@verbatim
+  ==============================================================================
+                          ##### TIM Encoder functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM Encoder.
+    (+) De-initialize the TIM Encoder.
+    (+) Start the TIM Encoder.
+    (+) Stop the TIM Encoder.
+    (+) Start the TIM Encoder and enable interrupt.
+    (+) Stop the TIM Encoder and disable interrupt.
+    (+) Start the TIM Encoder and enable DMA transfer.
+    (+) Stop the TIM Encoder and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Encoder Interface and initialize the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
+  * @note   Encoder mode and External clock mode 2 are not compatible and must not be selected together
+  *         Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
+  *         using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
+  * @param  htim TIM Encoder Interface handle
+  * @param  sConfig TIM Encoder Interface configuration structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef *sConfig)
+{
+  uint32_t tmpsmcr;
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+  assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
+  assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
+  assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
+  assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
+  assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
+  assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+  assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->Encoder_MspInitCallback == NULL)
+    {
+      htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->Encoder_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_Encoder_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Reset the SMS and ECE bits */
+  htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
+
+  /* Configure the Time base in the Encoder Mode */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = htim->Instance->SMCR;
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmr1 = htim->Instance->CCMR1;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = htim->Instance->CCER;
+
+  /* Set the encoder Mode */
+  tmpsmcr |= sConfig->EncoderMode;
+
+  /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+  tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
+  tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
+
+  /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
+  tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
+  tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
+  tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
+  tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
+
+  /* Set the TI1 and the TI2 Polarities */
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
+  tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
+  tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
+
+  /* Write to TIMx SMCR */
+  htim->Instance->SMCR = tmpsmcr;
+
+  /* Write to TIMx CCMR1 */
+  htim->Instance->CCMR1 = tmpccmr1;
+
+  /* Write to TIMx CCER */
+  htim->Instance->CCER = tmpccer;
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  DeInitializes the TIM Encoder interface
+  * @param  htim TIM Encoder Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->Encoder_MspDeInitCallback == NULL)
+  {
+    htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->Encoder_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIM_Encoder_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Encoder Interface MSP.
+  * @param  htim TIM Encoder Interface handle
+  * @retval None
+  */
+__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_Encoder_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Encoder Interface MSP.
+  * @param  htim TIM Encoder Interface handle
+  * @retval None
+  */
+__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Encoder Interface.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Enable the encoder interface channels */
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      break;
+    }
+
+    default :
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      break;
+    }
+  }
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Encoder Interface.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channels 1 and 2
+    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+      break;
+    }
+
+    default :
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+      break;
+    }
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Encoder Interface in interrupt mode.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Enable the encoder interface channels */
+  /* Enable the capture compare Interrupts 1 and/or 2 */
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    default :
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+  }
+
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Encoder Interface in interrupt mode.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channels 1 and 2
+    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+  if (Channel == TIM_CHANNEL_1)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare Interrupts 1 */
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare Interrupts 2 */
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+  }
+  else
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare Interrupts 1 and 2 */
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Encoder Interface in DMA mode.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @param  pData1 The destination Buffer address for IC1.
+  * @param  pData2 The destination Buffer address for IC2.
+  * @param  Length The length of data to be transferred from TIM peripheral to memory.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
+                                            uint32_t *pData2, uint16_t Length)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Input Capture DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+
+      /* Enable the Peripheral */
+      __HAL_TIM_ENABLE(htim);
+
+      /* Enable the Capture compare channel */
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Input Capture  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+
+      /* Enable the Peripheral */
+      __HAL_TIM_ENABLE(htim);
+
+      /* Enable the Capture compare channel */
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      break;
+    }
+
+    case TIM_CHANNEL_ALL:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the Peripheral */
+      __HAL_TIM_ENABLE(htim);
+
+      /* Enable the Capture compare channel */
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+      /* Enable the TIM Input Capture  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      /* Enable the TIM Input Capture  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    default:
+      break;
+  }
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Encoder Interface in DMA mode.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channels 1 and 2
+    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+  if (Channel == TIM_CHANNEL_1)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare DMA Request 1 */
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare DMA Request 2 */
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+  }
+  else
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare DMA Request 1 and 2 */
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
+  *  @brief    TIM IRQ handler management
+  *
+@verbatim
+  ==============================================================================
+                        ##### IRQ handler management #####
+  ==============================================================================
+  [..]
+    This section provides Timer IRQ handler function.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  This function handles TIM interrupts requests.
+  * @param  htim TIM  handle
+  * @retval None
+  */
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
+{
+  /* Capture compare 1 event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
+    {
+      {
+        __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
+        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+        /* Input capture event */
+        if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
+        {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+          htim->IC_CaptureCallback(htim);
+#else
+          HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+        }
+        /* Output compare event */
+        else
+        {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+          htim->OC_DelayElapsedCallback(htim);
+          htim->PWM_PulseFinishedCallback(htim);
+#else
+          HAL_TIM_OC_DelayElapsedCallback(htim);
+          HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+        }
+        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+      }
+    }
+  }
+  /* Capture compare 2 event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+      /* Input capture event */
+      if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->IC_CaptureCallback(htim);
+#else
+        HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      /* Output compare event */
+      else
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->OC_DelayElapsedCallback(htim);
+        htim->PWM_PulseFinishedCallback(htim);
+#else
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+    }
+  }
+  /* Capture compare 3 event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+      /* Input capture event */
+      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->IC_CaptureCallback(htim);
+#else
+        HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      /* Output compare event */
+      else
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->OC_DelayElapsedCallback(htim);
+        htim->PWM_PulseFinishedCallback(htim);
+#else
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+    }
+  }
+  /* Capture compare 4 event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+      /* Input capture event */
+      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->IC_CaptureCallback(htim);
+#else
+        HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      /* Output compare event */
+      else
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->OC_DelayElapsedCallback(htim);
+        htim->PWM_PulseFinishedCallback(htim);
+#else
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+    }
+  }
+  /* TIM Update event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->PeriodElapsedCallback(htim);
+#else
+      HAL_TIM_PeriodElapsedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM Break input event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->BreakCallback(htim);
+#else
+      HAL_TIMEx_BreakCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM Break2 input event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->Break2Callback(htim);
+#else
+      HAL_TIMEx_Break2Callback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM Trigger detection event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->TriggerCallback(htim);
+#else
+      HAL_TIM_TriggerCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM commutation event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->CommutationCallback(htim);
+#else
+      HAL_TIMEx_CommutCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
+  *  @brief    TIM Peripheral Control functions
+  *
+@verbatim
+  ==============================================================================
+                   ##### Peripheral Control functions #####
+  ==============================================================================
+ [..]
+   This section provides functions allowing to:
+      (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
+      (+) Configure External Clock source.
+      (+) Configure Complementary channels, break features and dead time.
+      (+) Configure Master and the Slave synchronization.
+      (+) Configure the DMA Burst Mode.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the TIM Output Compare Channels according to the specified
+  *         parameters in the TIM_OC_InitTypeDef.
+  * @param  htim TIM Output Compare handle
+  * @param  sConfig TIM Output Compare configuration structure
+  * @param  Channel TIM Channels to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
+                                           TIM_OC_InitTypeDef *sConfig,
+                                           uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CHANNELS(Channel));
+  assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
+  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 1 in Output Compare */
+      TIM_OC1_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 2 in Output Compare */
+      TIM_OC2_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 3 in Output Compare */
+      TIM_OC3_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 4 in Output Compare */
+      TIM_OC4_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    case TIM_CHANNEL_5:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 5 in Output Compare */
+      TIM_OC5_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    case TIM_CHANNEL_6:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 6 in Output Compare */
+      TIM_OC6_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Input Capture Channels according to the specified
+  *         parameters in the TIM_IC_InitTypeDef.
+  * @param  htim TIM IC handle
+  * @param  sConfig TIM Input Capture configuration structure
+  * @param  Channel TIM Channel to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
+  assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
+  assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  if (Channel == TIM_CHANNEL_1)
+  {
+    /* TI1 Configuration */
+    TIM_TI1_SetConfig(htim->Instance,
+                      sConfig->ICPolarity,
+                      sConfig->ICSelection,
+                      sConfig->ICFilter);
+
+    /* Reset the IC1PSC Bits */
+    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+
+    /* Set the IC1PSC value */
+    htim->Instance->CCMR1 |= sConfig->ICPrescaler;
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    /* TI2 Configuration */
+    assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+    TIM_TI2_SetConfig(htim->Instance,
+                      sConfig->ICPolarity,
+                      sConfig->ICSelection,
+                      sConfig->ICFilter);
+
+    /* Reset the IC2PSC Bits */
+    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+    /* Set the IC2PSC value */
+    htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
+  }
+  else if (Channel == TIM_CHANNEL_3)
+  {
+    /* TI3 Configuration */
+    assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+    TIM_TI3_SetConfig(htim->Instance,
+                      sConfig->ICPolarity,
+                      sConfig->ICSelection,
+                      sConfig->ICFilter);
+
+    /* Reset the IC3PSC Bits */
+    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
+
+    /* Set the IC3PSC value */
+    htim->Instance->CCMR2 |= sConfig->ICPrescaler;
+  }
+  else
+  {
+    /* TI4 Configuration */
+    assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+    TIM_TI4_SetConfig(htim->Instance,
+                      sConfig->ICPolarity,
+                      sConfig->ICSelection,
+                      sConfig->ICFilter);
+
+    /* Reset the IC4PSC Bits */
+    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
+
+    /* Set the IC4PSC value */
+    htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
+  }
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM PWM  channels according to the specified
+  *         parameters in the TIM_OC_InitTypeDef.
+  * @param  htim TIM PWM handle
+  * @param  sConfig TIM PWM configuration structure
+  * @param  Channel TIM Channels to be configured
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
+                                            TIM_OC_InitTypeDef *sConfig,
+                                            uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CHANNELS(Channel));
+  assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
+  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+  assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 1 in PWM mode */
+      TIM_OC1_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel1 */
+      htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
+      htim->Instance->CCMR1 |= sConfig->OCFastMode;
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 2 in PWM mode */
+      TIM_OC2_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel2 */
+      htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
+      htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 3 in PWM mode */
+      TIM_OC3_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel3 */
+      htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
+      htim->Instance->CCMR2 |= sConfig->OCFastMode;
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 4 in PWM mode */
+      TIM_OC4_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel4 */
+      htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
+      htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
+      break;
+    }
+
+    case TIM_CHANNEL_5:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 5 in PWM mode */
+      TIM_OC5_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel5*/
+      htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
+      htim->Instance->CCMR3 |= sConfig->OCFastMode;
+      break;
+    }
+
+    case TIM_CHANNEL_6:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 6 in PWM mode */
+      TIM_OC6_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel6 */
+      htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
+      htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM One Pulse Channels according to the specified
+  *         parameters in the TIM_OnePulse_InitTypeDef.
+  * @param  htim TIM One Pulse handle
+  * @param  sConfig TIM One Pulse configuration structure
+  * @param  OutputChannel TIM output channel to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @param  InputChannel TIM input Channel to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @note  To output a waveform with a minimum delay user can enable the fast
+  *        mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
+  *        output is forced in response to the edge detection on TIx input,
+  *        without taking in account the comparison.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef *sConfig,
+                                                 uint32_t OutputChannel,  uint32_t InputChannel)
+{
+  TIM_OC_InitTypeDef temp1;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
+  assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
+
+  if (OutputChannel != InputChannel)
+  {
+    /* Process Locked */
+    __HAL_LOCK(htim);
+
+    htim->State = HAL_TIM_STATE_BUSY;
+
+    /* Extract the Output compare configuration from sConfig structure */
+    temp1.OCMode = sConfig->OCMode;
+    temp1.Pulse = sConfig->Pulse;
+    temp1.OCPolarity = sConfig->OCPolarity;
+    temp1.OCNPolarity = sConfig->OCNPolarity;
+    temp1.OCIdleState = sConfig->OCIdleState;
+    temp1.OCNIdleState = sConfig->OCNIdleState;
+
+    switch (OutputChannel)
+    {
+      case TIM_CHANNEL_1:
+      {
+        assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+        TIM_OC1_SetConfig(htim->Instance, &temp1);
+        break;
+      }
+      case TIM_CHANNEL_2:
+      {
+        assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+        TIM_OC2_SetConfig(htim->Instance, &temp1);
+        break;
+      }
+      default:
+        break;
+    }
+
+    switch (InputChannel)
+    {
+      case TIM_CHANNEL_1:
+      {
+        assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+        TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
+                          sConfig->ICSelection, sConfig->ICFilter);
+
+        /* Reset the IC1PSC Bits */
+        htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+
+        /* Select the Trigger source */
+        htim->Instance->SMCR &= ~TIM_SMCR_TS;
+        htim->Instance->SMCR |= TIM_TS_TI1FP1;
+
+        /* Select the Slave Mode */
+        htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+        htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+        break;
+      }
+      case TIM_CHANNEL_2:
+      {
+        assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+        TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
+                          sConfig->ICSelection, sConfig->ICFilter);
+
+        /* Reset the IC2PSC Bits */
+        htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+        /* Select the Trigger source */
+        htim->Instance->SMCR &= ~TIM_SMCR_TS;
+        htim->Instance->SMCR |= TIM_TS_TI2FP2;
+
+        /* Select the Slave Mode */
+        htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+        htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+        break;
+      }
+
+      default:
+        break;
+    }
+
+    htim->State = HAL_TIM_STATE_READY;
+
+    __HAL_UNLOCK(htim);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data write
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMABASE_CR1
+  *            @arg TIM_DMABASE_CR2
+  *            @arg TIM_DMABASE_SMCR
+  *            @arg TIM_DMABASE_DIER
+  *            @arg TIM_DMABASE_SR
+  *            @arg TIM_DMABASE_EGR
+  *            @arg TIM_DMABASE_CCMR1
+  *            @arg TIM_DMABASE_CCMR2
+  *            @arg TIM_DMABASE_CCER
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
+  *            @arg TIM_DMABASE_ARR
+  *            @arg TIM_DMABASE_RCR
+  *            @arg TIM_DMABASE_CCR1
+  *            @arg TIM_DMABASE_CCR2
+  *            @arg TIM_DMABASE_CCR3
+  *            @arg TIM_DMABASE_CCR4
+  *            @arg TIM_DMABASE_BDTR
+  *            @arg TIM_DMABASE_CCMR3 
+  *            @arg TIM_DMABASE_CCR5 
+  *            @arg TIM_DMABASE_CCR6 
+  *            @arg TIM_DMABASE_AF1  
+  *            @arg TIM_DMABASE_AF2  
+  *            @arg TIM_DMABASE_TISEL
+  *         
+  * @param  BurstRequestSrc TIM DMA Request sources
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+  * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                              uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t  BurstLength)
+{
+  return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+                                          ((BurstLength) >> 8U) + 1U);
+}
+
+/**
+  * @brief  Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA will start the Data write
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMABASE_CR1
+  *            @arg TIM_DMABASE_CR2
+  *            @arg TIM_DMABASE_SMCR
+  *            @arg TIM_DMABASE_DIER
+  *            @arg TIM_DMABASE_SR
+  *            @arg TIM_DMABASE_EGR
+  *            @arg TIM_DMABASE_CCMR1
+  *            @arg TIM_DMABASE_CCMR2
+  *            @arg TIM_DMABASE_CCER
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
+  *            @arg TIM_DMABASE_ARR
+  *            @arg TIM_DMABASE_RCR
+  *            @arg TIM_DMABASE_CCR1
+  *            @arg TIM_DMABASE_CCR2
+  *            @arg TIM_DMABASE_CCR3
+  *            @arg TIM_DMABASE_CCR4
+  *            @arg TIM_DMABASE_BDTR
+  *            @arg TIM_DMABASE_CCMR3 
+  *            @arg TIM_DMABASE_CCR5 
+  *            @arg TIM_DMABASE_CCR6 
+  *            @arg TIM_DMABASE_AF1  
+  *            @arg TIM_DMABASE_AF2  
+  *            @arg TIM_DMABASE_TISEL
+  *         
+  * @param  BurstRequestSrc TIM DMA Request sources
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+  * @param  DataLength Data length. This parameter can be one value
+  *         between 1 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                                   uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
+                                                   uint32_t  BurstLength,  uint32_t  DataLength)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+  assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+  assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if ((BurstBuffer == NULL) && (BurstLength > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+  switch (BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      /* Set the DMA Period elapsed callbacks */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC4:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_COM:
+    {
+      /* Set the DMA commutation callbacks */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_TRIGGER:
+    {
+      /* Set the DMA trigger callbacks */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    default:
+      break;
+  }
+
+  /* Configure the DMA Burst Mode */
+  htim->Instance->DCR = (BurstBaseAddress | BurstLength);
+  /* Enable the TIM DMA Request */
+  __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM DMA Burst mode
+  * @param  htim TIM handle
+  * @param  BurstRequestSrc TIM DMA Request sources to disable
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+
+  /* Abort the DMA transfer (at least disable the DMA stream) */
+  switch (BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+      break;
+    }
+    case TIM_DMA_CC1:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+    case TIM_DMA_CC2:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+    case TIM_DMA_CC3:
+    {
+      status =  HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+    case TIM_DMA_CC4:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+    case TIM_DMA_COM:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+      break;
+    }
+    case TIM_DMA_TRIGGER:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+      break;
+    }
+    default:
+      break;
+  }
+
+  if (HAL_OK == status)
+  {
+    /* Disable the TIM Update DMA request */
+    __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMABASE_CR1
+  *            @arg TIM_DMABASE_CR2
+  *            @arg TIM_DMABASE_SMCR
+  *            @arg TIM_DMABASE_DIER
+  *            @arg TIM_DMABASE_SR
+  *            @arg TIM_DMABASE_EGR
+  *            @arg TIM_DMABASE_CCMR1
+  *            @arg TIM_DMABASE_CCMR2
+  *            @arg TIM_DMABASE_CCER
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
+  *            @arg TIM_DMABASE_ARR
+  *            @arg TIM_DMABASE_RCR
+  *            @arg TIM_DMABASE_CCR1
+  *            @arg TIM_DMABASE_CCR2
+  *            @arg TIM_DMABASE_CCR3
+  *            @arg TIM_DMABASE_CCR4
+  *            @arg TIM_DMABASE_BDTR
+  *            @arg TIM_DMABASE_CCMR3 
+  *            @arg TIM_DMABASE_CCR5 
+  *            @arg TIM_DMABASE_CCR6 
+  *            @arg TIM_DMABASE_AF1  
+  *            @arg TIM_DMABASE_AF2  
+  *            @arg TIM_DMABASE_TISEL
+  *         
+  * @param  BurstRequestSrc TIM DMA Request sources
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+  * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                             uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength)
+{
+  return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+                                         ((BurstLength) >> 8U) + 1U);
+}
+
+/**
+  * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMABASE_CR1
+  *            @arg TIM_DMABASE_CR2
+  *            @arg TIM_DMABASE_SMCR
+  *            @arg TIM_DMABASE_DIER
+  *            @arg TIM_DMABASE_SR
+  *            @arg TIM_DMABASE_EGR
+  *            @arg TIM_DMABASE_CCMR1
+  *            @arg TIM_DMABASE_CCMR2
+  *            @arg TIM_DMABASE_CCER
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
+  *            @arg TIM_DMABASE_ARR
+  *            @arg TIM_DMABASE_RCR
+  *            @arg TIM_DMABASE_CCR1
+  *            @arg TIM_DMABASE_CCR2
+  *            @arg TIM_DMABASE_CCR3
+  *            @arg TIM_DMABASE_CCR4
+  *            @arg TIM_DMABASE_BDTR
+  *            @arg TIM_DMABASE_CCMR3 
+  *            @arg TIM_DMABASE_CCR5 
+  *            @arg TIM_DMABASE_CCR6 
+  *            @arg TIM_DMABASE_AF1  
+  *            @arg TIM_DMABASE_AF2  
+  *            @arg TIM_DMABASE_TISEL
+  *         
+  * @param  BurstRequestSrc TIM DMA Request sources
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+  * @param  DataLength Data length. This parameter can be one value
+  *         between 1 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                                  uint32_t BurstRequestSrc, uint32_t  *BurstBuffer,
+                                                  uint32_t  BurstLength, uint32_t  DataLength)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+  assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+  assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if ((BurstBuffer == NULL) && (BurstLength > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+  switch (BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      /* Set the DMA Period elapsed callbacks */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC1:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC2:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC3:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC4:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_COM:
+    {
+      /* Set the DMA commutation callbacks */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_TRIGGER:
+    {
+      /* Set the DMA trigger callbacks */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    default:
+      break;
+  }
+
+  /* Configure the DMA Burst Mode */
+  htim->Instance->DCR = (BurstBaseAddress | BurstLength);
+
+  /* Enable the TIM DMA Request */
+  __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the DMA burst reading
+  * @param  htim TIM handle
+  * @param  BurstRequestSrc TIM DMA Request sources to disable.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+
+  /* Abort the DMA transfer (at least disable the DMA stream) */
+  switch (BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+      break;
+    }
+    case TIM_DMA_CC1:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+    case TIM_DMA_CC2:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+    case TIM_DMA_CC3:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+    case TIM_DMA_CC4:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+    case TIM_DMA_COM:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+      break;
+    }
+    case TIM_DMA_TRIGGER:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+      break;
+    }
+    default:
+      break;
+  }
+
+  if (HAL_OK == status)
+  {
+    /* Disable the TIM Update DMA request */
+    __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Generate a software event
+  * @param  htim TIM handle
+  * @param  EventSource specifies the event source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
+  *            @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
+  *            @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
+  *            @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
+  *            @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
+  *            @arg TIM_EVENTSOURCE_COM: Timer COM event source
+  *            @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
+  *            @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
+  *            @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
+  * @note   Basic timers can only generate an update event.
+  * @note   TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
+  * @note   TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant
+  *         only for timer instances supporting break input(s).
+  * @retval HAL status
+  */
+
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_EVENT_SOURCE(EventSource));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  /* Change the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Set the event sources */
+  htim->Instance->EGR = EventSource;
+
+  /* Change the TIM state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the OCRef clear feature
+  * @param  htim TIM handle
+  * @param  sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
+  *         contains the OCREF clear feature and parameters for the TIM peripheral.
+  * @param  Channel specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1
+  *            @arg TIM_CHANNEL_2: TIM Channel 2
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  *            @arg TIM_CHANNEL_4: TIM Channel 4
+  *            @arg TIM_CHANNEL_5: TIM Channel 5
+  *            @arg TIM_CHANNEL_6: TIM Channel 6
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
+                                           TIM_ClearInputConfigTypeDef *sClearInputConfig,
+                                           uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  switch (sClearInputConfig->ClearInputSource)
+  {
+    case TIM_CLEARINPUTSOURCE_NONE:
+    {
+      /* Clear the OCREF clear selection bit and the the ETR Bits */
+      CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
+      break;
+    }
+
+    case TIM_CLEARINPUTSOURCE_ETR:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
+      assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
+      assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
+
+      /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
+      if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
+      {
+        htim->State = HAL_TIM_STATE_READY;
+        __HAL_UNLOCK(htim);
+        return HAL_ERROR;
+      }
+
+      TIM_ETR_SetConfig(htim->Instance,
+                        sClearInputConfig->ClearInputPrescaler,
+                        sClearInputConfig->ClearInputPolarity,
+                        sClearInputConfig->ClearInputFilter);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+      {
+        /* Enable the OCREF clear feature for Channel 1 */
+        SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
+      }
+      else
+      {
+        /* Disable the OCREF clear feature for Channel 1 */
+        CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
+      }
+      break;
+    }
+    case TIM_CHANNEL_2:
+    {
+      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+      {
+        /* Enable the OCREF clear feature for Channel 2 */
+        SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
+      }
+      else
+      {
+        /* Disable the OCREF clear feature for Channel 2 */
+        CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
+      }
+      break;
+    }
+    case TIM_CHANNEL_3:
+    {
+      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+      {
+        /* Enable the OCREF clear feature for Channel 3 */
+        SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
+      }
+      else
+      {
+        /* Disable the OCREF clear feature for Channel 3 */
+        CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
+      }
+      break;
+    }
+    case TIM_CHANNEL_4:
+    {
+      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+      {
+        /* Enable the OCREF clear feature for Channel 4 */
+        SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
+      }
+      else
+      {
+        /* Disable the OCREF clear feature for Channel 4 */
+        CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
+      }
+      break;
+    }
+    case TIM_CHANNEL_5:
+    {
+      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+      {
+        /* Enable the OCREF clear feature for Channel 5 */
+        SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
+      }
+      else
+      {
+        /* Disable the OCREF clear feature for Channel 5 */
+        CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
+      }
+      break;
+    }
+    case TIM_CHANNEL_6:
+    {
+      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+      {
+        /* Enable the OCREF clear feature for Channel 6 */
+        SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
+      }
+      else
+      {
+        /* Disable the OCREF clear feature for Channel 6 */
+        CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
+      }
+      break;
+    }
+    default:
+      break;
+  }
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief   Configures the clock source to be used
+  * @param  htim TIM handle
+  * @param  sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
+  *         contains the clock source information for the TIM peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
+{
+  uint32_t tmpsmcr;
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
+
+  /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
+  tmpsmcr = htim->Instance->SMCR;
+  tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+  htim->Instance->SMCR = tmpsmcr;
+
+  switch (sClockSourceConfig->ClockSource)
+  {
+    case TIM_CLOCKSOURCE_INTERNAL:
+    {
+      assert_param(IS_TIM_INSTANCE(htim->Instance));
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_ETRMODE1:
+    {
+      /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
+      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
+
+      /* Check ETR input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      /* Configure the ETR Clock source */
+      TIM_ETR_SetConfig(htim->Instance,
+                        sClockSourceConfig->ClockPrescaler,
+                        sClockSourceConfig->ClockPolarity,
+                        sClockSourceConfig->ClockFilter);
+
+      /* Select the External clock mode1 and the ETRF trigger */
+      tmpsmcr = htim->Instance->SMCR;
+      tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
+      /* Write to TIMx SMCR */
+      htim->Instance->SMCR = tmpsmcr;
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_ETRMODE2:
+    {
+      /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
+      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
+
+      /* Check ETR input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      /* Configure the ETR Clock source */
+      TIM_ETR_SetConfig(htim->Instance,
+                        sClockSourceConfig->ClockPrescaler,
+                        sClockSourceConfig->ClockPolarity,
+                        sClockSourceConfig->ClockFilter);
+      /* Enable the External clock mode2 */
+      htim->Instance->SMCR |= TIM_SMCR_ECE;
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_TI1:
+    {
+      /* Check whether or not the timer instance supports external clock mode 1 */
+      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+      /* Check TI1 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI1_ConfigInputStage(htim->Instance,
+                               sClockSourceConfig->ClockPolarity,
+                               sClockSourceConfig->ClockFilter);
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_TI2:
+    {
+      /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
+      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+      /* Check TI2 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI2_ConfigInputStage(htim->Instance,
+                               sClockSourceConfig->ClockPolarity,
+                               sClockSourceConfig->ClockFilter);
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_TI1ED:
+    {
+      /* Check whether or not the timer instance supports external clock mode 1 */
+      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+      /* Check TI1 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI1_ConfigInputStage(htim->Instance,
+                               sClockSourceConfig->ClockPolarity,
+                               sClockSourceConfig->ClockFilter);
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_ITR0:
+    case TIM_CLOCKSOURCE_ITR1:
+    case TIM_CLOCKSOURCE_ITR2:
+    case TIM_CLOCKSOURCE_ITR3:
+    case TIM_CLOCKSOURCE_ITR4:
+    case TIM_CLOCKSOURCE_ITR5:
+    case TIM_CLOCKSOURCE_ITR6:
+    case TIM_CLOCKSOURCE_ITR7:
+    case TIM_CLOCKSOURCE_ITR8:
+    {
+      /* Check whether or not the timer instance supports internal trigger input */
+      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
+
+      TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
+      break;
+    }
+
+    default:
+      break;
+  }
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Selects the signal connected to the TI1 input: direct from CH1_input
+  *         or a XOR combination between CH1_input, CH2_input & CH3_input
+  * @param  htim TIM handle.
+  * @param  TI1_Selection Indicate whether or not channel 1 is connected to the
+  *         output of a XOR gate.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
+  *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
+  *            pins are connected to the TI1 input (XOR combination)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
+{
+  uint32_t tmpcr2;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = htim->Instance->CR2;
+
+  /* Reset the TI1 selection */
+  tmpcr2 &= ~TIM_CR2_TI1S;
+
+  /* Set the TI1 selection */
+  tmpcr2 |= TI1_Selection;
+
+  /* Write to TIMxCR2 */
+  htim->Instance->CR2 = tmpcr2;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the TIM in Slave mode
+  * @param  htim TIM handle.
+  * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
+  *         contains the selected trigger (internal trigger input, filtered
+  *         timer input or external trigger input) and the Slave mode
+  *         (Disable, Reset, Gated, Trigger, External clock mode 1).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+  assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
+  {
+    htim->State = HAL_TIM_STATE_READY;
+    __HAL_UNLOCK(htim);
+    return HAL_ERROR;
+  }
+
+  /* Disable Trigger Interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
+
+  /* Disable Trigger DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the TIM in Slave mode in interrupt mode
+  * @param  htim TIM handle.
+  * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
+  *         contains the selected trigger (internal trigger input, filtered
+  *         timer input or external trigger input) and the Slave mode
+  *         (Disable, Reset, Gated, Trigger, External clock mode 1).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
+                                                TIM_SlaveConfigTypeDef *sSlaveConfig)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+  assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
+  {
+    htim->State = HAL_TIM_STATE_READY;
+    __HAL_UNLOCK(htim);
+    return HAL_ERROR;
+  }
+
+  /* Enable Trigger Interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
+
+  /* Disable Trigger DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Read the captured value from Capture Compare unit
+  * @param  htim TIM handle.
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval Captured value
+  */
+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpreg = 0U;
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+      /* Return the capture 1 value */
+      tmpreg =  htim->Instance->CCR1;
+
+      break;
+    }
+    case TIM_CHANNEL_2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+      /* Return the capture 2 value */
+      tmpreg =   htim->Instance->CCR2;
+
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+      /* Return the capture 3 value */
+      tmpreg =   htim->Instance->CCR3;
+
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+      /* Return the capture 4 value */
+      tmpreg =   htim->Instance->CCR4;
+
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  return tmpreg;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
+  *  @brief    TIM Callbacks functions
+  *
+@verbatim
+  ==============================================================================
+                        ##### TIM Callbacks functions #####
+  ==============================================================================
+ [..]
+   This section provides TIM callback functions:
+   (+) TIM Period elapsed callback
+   (+) TIM Output Compare callback
+   (+) TIM Input capture callback
+   (+) TIM Trigger callback
+   (+) TIM Error callback
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Period elapsed callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Period elapsed half complete callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Output Compare callback in non-blocking mode
+  * @param  htim TIM OC handle
+  * @retval None
+  */
+__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Input Capture callback in non-blocking mode
+  * @param  htim TIM IC handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_CaptureCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Input Capture half complete callback in non-blocking mode
+  * @param  htim TIM IC handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  PWM Pulse finished callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  PWM Pulse finished half complete callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Hall Trigger detection callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_TriggerCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Hall Trigger detection half complete callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Timer error callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_ErrorCallback could be implemented in the user file
+   */
+}
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User TIM callback to be used instead of the weak predefined callback
+  * @param htim tim handle
+  * @param CallbackID ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
+  *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
+  *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
+  *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
+  *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
+  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
+  *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
+  *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
+  *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
+  *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
+  *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
+  *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
+  *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
+  *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
+  *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
+  *          @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
+  *          @param pCallback pointer to the callback function
+  *          @retval status
+  */
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
+                                           pTIM_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(htim);
+
+  if (htim->State == HAL_TIM_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_TIM_BASE_MSPINIT_CB_ID :
+        htim->Base_MspInitCallback                 = pCallback;
+        break;
+
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+        htim->Base_MspDeInitCallback               = pCallback;
+        break;
+
+      case HAL_TIM_IC_MSPINIT_CB_ID :
+        htim->IC_MspInitCallback                   = pCallback;
+        break;
+
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :
+        htim->IC_MspDeInitCallback                 = pCallback;
+        break;
+
+      case HAL_TIM_OC_MSPINIT_CB_ID :
+        htim->OC_MspInitCallback                   = pCallback;
+        break;
+
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :
+        htim->OC_MspDeInitCallback                 = pCallback;
+        break;
+
+      case HAL_TIM_PWM_MSPINIT_CB_ID :
+        htim->PWM_MspInitCallback                  = pCallback;
+        break;
+
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+        htim->PWM_MspDeInitCallback                = pCallback;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+        htim->OnePulse_MspInitCallback             = pCallback;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+        htim->OnePulse_MspDeInitCallback           = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+        htim->Encoder_MspInitCallback              = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+        htim->Encoder_MspDeInitCallback            = pCallback;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+        htim->HallSensor_MspInitCallback           = pCallback;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+        htim->HallSensor_MspDeInitCallback         = pCallback;
+        break;
+
+      case HAL_TIM_PERIOD_ELAPSED_CB_ID :
+        htim->PeriodElapsedCallback                = pCallback;
+        break;
+
+      case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
+        htim->PeriodElapsedHalfCpltCallback        = pCallback;
+        break;
+
+      case HAL_TIM_TRIGGER_CB_ID :
+        htim->TriggerCallback                      = pCallback;
+        break;
+
+      case HAL_TIM_TRIGGER_HALF_CB_ID :
+        htim->TriggerHalfCpltCallback              = pCallback;
+        break;
+
+      case HAL_TIM_IC_CAPTURE_CB_ID :
+        htim->IC_CaptureCallback                   = pCallback;
+        break;
+
+      case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
+        htim->IC_CaptureHalfCpltCallback           = pCallback;
+        break;
+
+      case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
+        htim->OC_DelayElapsedCallback              = pCallback;
+        break;
+
+      case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
+        htim->PWM_PulseFinishedCallback            = pCallback;
+        break;
+
+      case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
+        htim->PWM_PulseFinishedHalfCpltCallback    = pCallback;
+        break;
+
+      case HAL_TIM_ERROR_CB_ID :
+        htim->ErrorCallback                        = pCallback;
+        break;
+
+      case HAL_TIM_COMMUTATION_CB_ID :
+        htim->CommutationCallback                  = pCallback;
+        break;
+
+      case HAL_TIM_COMMUTATION_HALF_CB_ID :
+        htim->CommutationHalfCpltCallback          = pCallback;
+        break;
+
+      case HAL_TIM_BREAK_CB_ID :
+        htim->BreakCallback                        = pCallback;
+        break;
+
+      case HAL_TIM_BREAK2_CB_ID :
+        htim->Break2Callback                       = pCallback;
+        break;
+
+      default :
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_TIM_BASE_MSPINIT_CB_ID :
+        htim->Base_MspInitCallback         = pCallback;
+        break;
+
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+        htim->Base_MspDeInitCallback       = pCallback;
+        break;
+
+      case HAL_TIM_IC_MSPINIT_CB_ID :
+        htim->IC_MspInitCallback           = pCallback;
+        break;
+
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :
+        htim->IC_MspDeInitCallback         = pCallback;
+        break;
+
+      case HAL_TIM_OC_MSPINIT_CB_ID :
+        htim->OC_MspInitCallback           = pCallback;
+        break;
+
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :
+        htim->OC_MspDeInitCallback         = pCallback;
+        break;
+
+      case HAL_TIM_PWM_MSPINIT_CB_ID :
+        htim->PWM_MspInitCallback          = pCallback;
+        break;
+
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+        htim->PWM_MspDeInitCallback        = pCallback;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+        htim->OnePulse_MspInitCallback     = pCallback;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+        htim->OnePulse_MspDeInitCallback   = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+        htim->Encoder_MspInitCallback      = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+        htim->Encoder_MspDeInitCallback    = pCallback;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+        htim->HallSensor_MspInitCallback   = pCallback;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+        htim->HallSensor_MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a TIM callback
+  *         TIM callback is redirected to the weak predefined callback
+  * @param htim tim handle
+  * @param CallbackID ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
+  *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
+  *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
+  *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
+  *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
+  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
+  *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
+  *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
+  *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
+  *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
+  *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
+  *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
+  *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
+  *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
+  *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
+  *          @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
+  *          @retval status
+  */
+HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(htim);
+
+  if (htim->State == HAL_TIM_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_TIM_BASE_MSPINIT_CB_ID :
+        htim->Base_MspInitCallback              = HAL_TIM_Base_MspInit;                      /* Legacy weak Base MspInit Callback */
+        break;
+
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+        htim->Base_MspDeInitCallback            = HAL_TIM_Base_MspDeInit;                    /* Legacy weak Base Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_IC_MSPINIT_CB_ID :
+        htim->IC_MspInitCallback                = HAL_TIM_IC_MspInit;                        /* Legacy weak IC Msp Init Callback */
+        break;
+
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :
+        htim->IC_MspDeInitCallback              = HAL_TIM_IC_MspDeInit;                      /* Legacy weak IC Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_OC_MSPINIT_CB_ID :
+        htim->OC_MspInitCallback                = HAL_TIM_OC_MspInit;                        /* Legacy weak OC Msp Init Callback */
+        break;
+
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :
+        htim->OC_MspDeInitCallback              = HAL_TIM_OC_MspDeInit;                      /* Legacy weak OC Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_PWM_MSPINIT_CB_ID :
+        htim->PWM_MspInitCallback               = HAL_TIM_PWM_MspInit;                       /* Legacy weak PWM Msp Init Callback */
+        break;
+
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+        htim->PWM_MspDeInitCallback             = HAL_TIM_PWM_MspDeInit;                     /* Legacy weak PWM Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+        htim->OnePulse_MspInitCallback          = HAL_TIM_OnePulse_MspInit;                  /* Legacy weak One Pulse Msp Init Callback */
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+        htim->OnePulse_MspDeInitCallback        = HAL_TIM_OnePulse_MspDeInit;                /* Legacy weak One Pulse Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+        htim->Encoder_MspInitCallback           = HAL_TIM_Encoder_MspInit;                   /* Legacy weak Encoder Msp Init Callback */
+        break;
+
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+        htim->Encoder_MspDeInitCallback         = HAL_TIM_Encoder_MspDeInit;                 /* Legacy weak Encoder Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+        htim->HallSensor_MspInitCallback        = HAL_TIMEx_HallSensor_MspInit;              /* Legacy weak Hall Sensor Msp Init Callback */
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+        htim->HallSensor_MspDeInitCallback      = HAL_TIMEx_HallSensor_MspDeInit;            /* Legacy weak Hall Sensor Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_PERIOD_ELAPSED_CB_ID :
+        htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;             /* Legacy weak Period Elapsed Callback */
+        break;
+
+      case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
+        htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;     /* Legacy weak Period Elapsed half complete Callback */
+        break;
+
+      case HAL_TIM_TRIGGER_CB_ID :
+        htim->TriggerCallback                   = HAL_TIM_TriggerCallback;                   /* Legacy weak Trigger Callback */
+        break;
+
+      case HAL_TIM_TRIGGER_HALF_CB_ID :
+        htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;           /* Legacy weak Trigger half complete Callback */
+        break;
+
+      case HAL_TIM_IC_CAPTURE_CB_ID :
+        htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;                /* Legacy weak IC Capture Callback */
+        break;
+
+      case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
+        htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;        /* Legacy weak IC Capture half complete Callback */
+        break;
+
+      case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
+        htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;           /* Legacy weak OC Delay Elapsed Callback */
+        break;
+
+      case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
+        htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;         /* Legacy weak PWM Pulse Finished Callback */
+        break;
+
+      case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
+        htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */
+        break;
+
+      case HAL_TIM_ERROR_CB_ID :
+        htim->ErrorCallback                     = HAL_TIM_ErrorCallback;                     /* Legacy weak Error Callback */
+        break;
+
+      case HAL_TIM_COMMUTATION_CB_ID :
+        htim->CommutationCallback               = HAL_TIMEx_CommutCallback;                  /* Legacy weak Commutation Callback */
+        break;
+
+      case HAL_TIM_COMMUTATION_HALF_CB_ID :
+        htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;          /* Legacy weak Commutation half complete Callback */
+        break;
+
+      case HAL_TIM_BREAK_CB_ID :
+        htim->BreakCallback                     = HAL_TIMEx_BreakCallback;                   /* Legacy weak Break Callback */
+        break;
+
+      case HAL_TIM_BREAK2_CB_ID :
+        htim->Break2Callback                    = HAL_TIMEx_Break2Callback;                  /* Legacy weak Break2 Callback */
+        break;
+
+      default :
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_TIM_BASE_MSPINIT_CB_ID :
+        htim->Base_MspInitCallback         = HAL_TIM_Base_MspInit;              /* Legacy weak Base MspInit Callback */
+        break;
+
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+        htim->Base_MspDeInitCallback       = HAL_TIM_Base_MspDeInit;            /* Legacy weak Base Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_IC_MSPINIT_CB_ID :
+        htim->IC_MspInitCallback           = HAL_TIM_IC_MspInit;                /* Legacy weak IC Msp Init Callback */
+        break;
+
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :
+        htim->IC_MspDeInitCallback         = HAL_TIM_IC_MspDeInit;              /* Legacy weak IC Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_OC_MSPINIT_CB_ID :
+        htim->OC_MspInitCallback           = HAL_TIM_OC_MspInit;                /* Legacy weak OC Msp Init Callback */
+        break;
+
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :
+        htim->OC_MspDeInitCallback         = HAL_TIM_OC_MspDeInit;              /* Legacy weak OC Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_PWM_MSPINIT_CB_ID :
+        htim->PWM_MspInitCallback          = HAL_TIM_PWM_MspInit;               /* Legacy weak PWM Msp Init Callback */
+        break;
+
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+        htim->PWM_MspDeInitCallback        = HAL_TIM_PWM_MspDeInit;             /* Legacy weak PWM Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+        htim->OnePulse_MspInitCallback     = HAL_TIM_OnePulse_MspInit;          /* Legacy weak One Pulse Msp Init Callback */
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+        htim->OnePulse_MspDeInitCallback   = HAL_TIM_OnePulse_MspDeInit;        /* Legacy weak One Pulse Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+        htim->Encoder_MspInitCallback      = HAL_TIM_Encoder_MspInit;           /* Legacy weak Encoder Msp Init Callback */
+        break;
+
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+        htim->Encoder_MspDeInitCallback    = HAL_TIM_Encoder_MspDeInit;         /* Legacy weak Encoder Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+        htim->HallSensor_MspInitCallback   = HAL_TIMEx_HallSensor_MspInit;      /* Legacy weak Hall Sensor Msp Init Callback */
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+        htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;    /* Legacy weak Hall Sensor Msp DeInit Callback */
+        break;
+
+      default :
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
+  *  @brief   TIM Peripheral State functions
+  *
+@verbatim
+  ==============================================================================
+                        ##### Peripheral State functions #####
+  ==============================================================================
+    [..]
+    This subsection permits to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the TIM Base handle state.
+  * @param  htim TIM Base handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM OC handle state.
+  * @param  htim TIM Output Compare handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM PWM handle state.
+  * @param  htim TIM handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM Input Capture handle state.
+  * @param  htim TIM IC handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM One Pulse Mode handle state.
+  * @param  htim TIM OPM handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM Encoder Mode handle state.
+  * @param  htim TIM Encoder Interface handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Private_Functions TIM Private Functions
+  * @{
+  */
+
+/**
+  * @brief  TIM DMA error callback
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMAError(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->ErrorCallback(htim);
+#else
+  HAL_TIM_ErrorCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Delay Pulse complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PWM_PulseFinishedCallback(htim);
+#else
+  HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Delay Pulse half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PWM_PulseFinishedHalfCpltCallback(htim);
+#else
+  HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Capture complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->IC_CaptureCallback(htim);
+#else
+  HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Capture half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->IC_CaptureHalfCpltCallback(htim);
+#else
+  HAL_TIM_IC_CaptureHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Period Elapse complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PeriodElapsedCallback(htim);
+#else
+  HAL_TIM_PeriodElapsedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Period Elapse half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PeriodElapsedHalfCpltCallback(htim);
+#else
+  HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Trigger callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->TriggerCallback(htim);
+#else
+  HAL_TIM_TriggerCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Trigger half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->TriggerHalfCpltCallback(htim);
+#else
+  HAL_TIM_TriggerHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  Time Base configuration
+  * @param  TIMx TIM peripheral
+  * @param  Structure TIM Base configuration structure
+  * @retval None
+  */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
+{
+  uint32_t tmpcr1;
+  tmpcr1 = TIMx->CR1;
+
+  /* Set TIM Time Base Unit parameters ---------------------------------------*/
+  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
+  {
+    /* Select the Counter Mode */
+    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
+    tmpcr1 |= Structure->CounterMode;
+  }
+
+  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
+  {
+    /* Set the clock division */
+    tmpcr1 &= ~TIM_CR1_CKD;
+    tmpcr1 |= (uint32_t)Structure->ClockDivision;
+  }
+
+  /* Set the auto-reload preload */
+  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
+
+  TIMx->CR1 = tmpcr1;
+
+  /* Set the Autoreload value */
+  TIMx->ARR = (uint32_t)Structure->Period ;
+
+  /* Set the Prescaler value */
+  TIMx->PSC = Structure->Prescaler;
+
+  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
+  {
+    /* Set the Repetition Counter value */
+    TIMx->RCR = Structure->RepetitionCounter;
+  }
+
+  /* Generate an update event to reload the Prescaler
+     and the repetition counter (only for advanced timer) value immediately */
+  TIMx->EGR = TIM_EGR_UG;
+}
+
+/**
+  * @brief  Timer Output Compare 1 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The ouput configuration structure
+  * @retval None
+  */
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR1;
+
+  /* Reset the Output Compare Mode Bits */
+  tmpccmrx &= ~TIM_CCMR1_OC1M;
+  tmpccmrx &= ~TIM_CCMR1_CC1S;
+  /* Select the Output Compare Mode */
+  tmpccmrx |= OC_Config->OCMode;
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC1P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= OC_Config->OCPolarity;
+
+  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+    /* Reset the Output N Polarity level */
+    tmpccer &= ~TIM_CCER_CC1NP;
+    /* Set the Output N Polarity */
+    tmpccer |= OC_Config->OCNPolarity;
+    /* Reset the Output N State */
+    tmpccer &= ~TIM_CCER_CC1NE;
+  }
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS1;
+    tmpcr2 &= ~TIM_CR2_OIS1N;
+    /* Set the Output Idle state */
+    tmpcr2 |= OC_Config->OCIdleState;
+    /* Set the Output N Idle state */
+    tmpcr2 |= OC_Config->OCNIdleState;
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR1 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Output Compare 2 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The ouput configuration structure
+  * @retval None
+  */
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR1;
+
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= ~TIM_CCMR1_OC2M;
+  tmpccmrx &= ~TIM_CCMR1_CC2S;
+
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (OC_Config->OCMode << 8U);
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC2P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 4U);
+
+  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
+  {
+    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+    /* Reset the Output N Polarity level */
+    tmpccer &= ~TIM_CCER_CC2NP;
+    /* Set the Output N Polarity */
+    tmpccer |= (OC_Config->OCNPolarity << 4U);
+    /* Reset the Output N State */
+    tmpccer &= ~TIM_CCER_CC2NE;
+
+  }
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS2;
+    tmpcr2 &= ~TIM_CR2_OIS2N;
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 2U);
+    /* Set the Output N Idle state */
+    tmpcr2 |= (OC_Config->OCNIdleState << 2U);
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR2 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Output Compare 3 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The ouput configuration structure
+  * @retval None
+  */
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Disable the Channel 3: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC3E;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+
+  /* Get the TIMx CCMR2 register value */
+  tmpccmrx = TIMx->CCMR2;
+
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= ~TIM_CCMR2_OC3M;
+  tmpccmrx &= ~TIM_CCMR2_CC3S;
+  /* Select the Output Compare Mode */
+  tmpccmrx |= OC_Config->OCMode;
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC3P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 8U);
+
+  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
+  {
+    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+    /* Reset the Output N Polarity level */
+    tmpccer &= ~TIM_CCER_CC3NP;
+    /* Set the Output N Polarity */
+    tmpccer |= (OC_Config->OCNPolarity << 8U);
+    /* Reset the Output N State */
+    tmpccer &= ~TIM_CCER_CC3NE;
+  }
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS3;
+    tmpcr2 &= ~TIM_CR2_OIS3N;
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 4U);
+    /* Set the Output N Idle state */
+    tmpcr2 |= (OC_Config->OCNIdleState << 4U);
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR2 */
+  TIMx->CCMR2 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR3 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Output Compare 4 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The ouput configuration structure
+  * @retval None
+  */
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Disable the Channel 4: Reset the CC4E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC4E;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+
+  /* Get the TIMx CCMR2 register value */
+  tmpccmrx = TIMx->CCMR2;
+
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= ~TIM_CCMR2_OC4M;
+  tmpccmrx &= ~TIM_CCMR2_CC4S;
+
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (OC_Config->OCMode << 8U);
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC4P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 12U);
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+    /* Reset the Output Compare IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS4;
+
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 6U);
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR2 */
+  TIMx->CCMR2 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR4 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Output Compare 5 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The ouput configuration structure
+  * @retval None
+  */
+static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
+                              TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Disable the output: Reset the CCxE Bit */
+  TIMx->CCER &= ~TIM_CCER_CC5E;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR3;
+
+  /* Reset the Output Compare Mode Bits */
+  tmpccmrx &= ~(TIM_CCMR3_OC5M);
+  /* Select the Output Compare Mode */
+  tmpccmrx |= OC_Config->OCMode;
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC5P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 16U);
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Reset the Output Compare IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS5;
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 8U);
+  }
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR3 */
+  TIMx->CCMR3 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR5 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Output Compare 6 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The ouput configuration structure
+  * @retval None
+  */
+static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
+                              TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Disable the output: Reset the CCxE Bit */
+  TIMx->CCER &= ~TIM_CCER_CC6E;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR3;
+
+  /* Reset the Output Compare Mode Bits */
+  tmpccmrx &= ~(TIM_CCMR3_OC6M);
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (OC_Config->OCMode << 8U);
+
+  /* Reset the Output Polarity level */
+  tmpccer &= (uint32_t)~TIM_CCER_CC6P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 20U);
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Reset the Output Compare IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS6;
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 10U);
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR3 */
+  TIMx->CCMR3 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR6 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Slave Timer configuration function
+  * @param  htim TIM handle
+  * @param  sSlaveConfig Slave timer configuration
+  * @retval None
+  */
+static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+                                                  TIM_SlaveConfigTypeDef *sSlaveConfig)
+{
+  uint32_t tmpsmcr;
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = htim->Instance->SMCR;
+
+  /* Reset the Trigger Selection Bits */
+  tmpsmcr &= ~TIM_SMCR_TS;
+  /* Set the Input Trigger source */
+  tmpsmcr |= sSlaveConfig->InputTrigger;
+
+  /* Reset the slave mode Bits */
+  tmpsmcr &= ~TIM_SMCR_SMS;
+  /* Set the slave mode */
+  tmpsmcr |= sSlaveConfig->SlaveMode;
+
+  /* Write to TIMx SMCR */
+  htim->Instance->SMCR = tmpsmcr;
+
+  /* Configure the trigger prescaler, filter, and polarity */
+  switch (sSlaveConfig->InputTrigger)
+  {
+    case TIM_TS_ETRF:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
+      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+      /* Configure the ETR Trigger source */
+      TIM_ETR_SetConfig(htim->Instance,
+                        sSlaveConfig->TriggerPrescaler,
+                        sSlaveConfig->TriggerPolarity,
+                        sSlaveConfig->TriggerFilter);
+      break;
+    }
+
+    case TIM_TS_TI1F_ED:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+      if(sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Disable the Channel 1: Reset the CC1E Bit */
+      tmpccer = htim->Instance->CCER;
+      htim->Instance->CCER &= ~TIM_CCER_CC1E;
+      tmpccmr1 = htim->Instance->CCMR1;
+
+      /* Set the filter */
+      tmpccmr1 &= ~TIM_CCMR1_IC1F;
+      tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
+
+      /* Write to TIMx CCMR1 and CCER registers */
+      htim->Instance->CCMR1 = tmpccmr1;
+      htim->Instance->CCER = tmpccer;
+      break;
+    }
+
+    case TIM_TS_TI1FP1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+      /* Configure TI1 Filter and Polarity */
+      TIM_TI1_ConfigInputStage(htim->Instance,
+                               sSlaveConfig->TriggerPolarity,
+                               sSlaveConfig->TriggerFilter);
+      break;
+    }
+
+    case TIM_TS_TI2FP2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+      /* Configure TI2 Filter and Polarity */
+      TIM_TI2_ConfigInputStage(htim->Instance,
+                               sSlaveConfig->TriggerPolarity,
+                               sSlaveConfig->TriggerFilter);
+      break;
+    }
+
+    case TIM_TS_ITR0:
+    case TIM_TS_ITR1:
+    case TIM_TS_ITR2:
+    case TIM_TS_ITR3:
+    case TIM_TS_ITR4:
+    case TIM_TS_ITR5:
+    case TIM_TS_ITR6:
+    case TIM_TS_ITR7:
+    case TIM_TS_ITR8:
+    case TIM_TS_ITR9:
+    case TIM_TS_ITR10:
+    case TIM_TS_ITR11:
+    case TIM_TS_ITR12:
+    case TIM_TS_ITR13:
+    {
+      /* Check the parameter */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+      break;
+    }
+
+    default:
+      break;
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the TI1 as Input.
+  * @param  TIMx to select the TIM peripheral.
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICSelection specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
+  *       (on channel2 path) is used as the input signal. Therefore CCMR1 must be
+  *        protected against un-initialized filter and polarity values.
+  */
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                       uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+  tmpccmr1 = TIMx->CCMR1;
+  tmpccer = TIMx->CCER;
+
+  /* Select the Input */
+  if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
+  {
+    tmpccmr1 &= ~TIM_CCMR1_CC1S;
+    tmpccmr1 |= TIM_ICSelection;
+  }
+  else
+  {
+    tmpccmr1 |= TIM_CCMR1_CC1S_0;
+  }
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC1F;
+  tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
+
+  /* Select the Polarity and set the CC1E Bit */
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+  tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the Polarity and Filter for TI1.
+  * @param  TIMx to select the TIM peripheral.
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  tmpccer = TIMx->CCER;
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC1F;
+  tmpccmr1 |= (TIM_ICFilter << 4U);
+
+  /* Select the Polarity and set the CC1E Bit */
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+  tmpccer |= TIM_ICPolarity;
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI2 as Input.
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICSelection specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
+  *       (on channel1 path) is used as the input signal. Therefore CCMR1 must be
+  *        protected against un-initialized filter and polarity values.
+  */
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+  tmpccmr1 = TIMx->CCMR1;
+  tmpccer = TIMx->CCER;
+
+  /* Select the Input */
+  tmpccmr1 &= ~TIM_CCMR1_CC2S;
+  tmpccmr1 |= (TIM_ICSelection << 8U);
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC2F;
+  tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
+
+  /* Select the Polarity and set the CC2E Bit */
+  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+  tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1 ;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the Polarity and Filter for TI2.
+  * @param  TIMx to select the TIM peripheral.
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+  tmpccmr1 = TIMx->CCMR1;
+  tmpccer = TIMx->CCER;
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC2F;
+  tmpccmr1 |= (TIM_ICFilter << 12U);
+
+  /* Select the Polarity and set the CC2E Bit */
+  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+  tmpccer |= (TIM_ICPolarity << 4U);
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1 ;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI3 as Input.
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICSelection specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
+  *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+  *        protected against un-initialized filter and polarity values.
+  */
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr2;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 3: Reset the CC3E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC3E;
+  tmpccmr2 = TIMx->CCMR2;
+  tmpccer = TIMx->CCER;
+
+  /* Select the Input */
+  tmpccmr2 &= ~TIM_CCMR2_CC3S;
+  tmpccmr2 |= TIM_ICSelection;
+
+  /* Set the filter */
+  tmpccmr2 &= ~TIM_CCMR2_IC3F;
+  tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
+
+  /* Select the Polarity and set the CC3E Bit */
+  tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
+  tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
+
+  /* Write to TIMx CCMR2 and CCER registers */
+  TIMx->CCMR2 = tmpccmr2;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI4 as Input.
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICSelection specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
+  *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+  *        protected against un-initialized filter and polarity values.
+  * @retval None
+  */
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr2;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 4: Reset the CC4E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC4E;
+  tmpccmr2 = TIMx->CCMR2;
+  tmpccer = TIMx->CCER;
+
+  /* Select the Input */
+  tmpccmr2 &= ~TIM_CCMR2_CC4S;
+  tmpccmr2 |= (TIM_ICSelection << 8U);
+
+  /* Set the filter */
+  tmpccmr2 &= ~TIM_CCMR2_IC4F;
+  tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
+
+  /* Select the Polarity and set the CC4E Bit */
+  tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
+  tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
+
+  /* Write to TIMx CCMR2 and CCER registers */
+  TIMx->CCMR2 = tmpccmr2;
+  TIMx->CCER = tmpccer ;
+}
+
+/**
+  * @brief  Selects the Input Trigger source
+  * @param  TIMx to select the TIM peripheral
+  * @param  InputTriggerSource The Input Trigger source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal Trigger 0
+  *            @arg TIM_TS_ITR1: Internal Trigger 1
+  *            @arg TIM_TS_ITR2: Internal Trigger 2
+  *            @arg TIM_TS_ITR3: Internal Trigger 3
+  *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
+  *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
+  *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
+  *            @arg TIM_TS_ETRF: External Trigger input
+  *            @arg TIM_TS_ITR4: Internal Trigger 4  (*)
+  *            @arg TIM_TS_ITR5: Internal Trigger 5
+  *            @arg TIM_TS_ITR6: Internal Trigger 6
+  *            @arg TIM_TS_ITR7: Internal Trigger 7
+  *            @arg TIM_TS_ITR8: Internal Trigger 8  (*)
+  *            @arg TIM_TS_ITR9: Internal Trigger 9  (*)
+  *            @arg TIM_TS_ITR10: Internal Trigger 10 (*)
+  *            @arg TIM_TS_ITR11: Internal Trigger 11 (*)
+  *            @arg TIM_TS_ITR12: Internal Trigger 12 (*)
+  *            @arg TIM_TS_ITR13: Internal Trigger 13 (*)
+  *
+  *       (*)  Value not defined in all devices.
+  *
+  * @retval None
+  */
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
+{
+  uint32_t tmpsmcr;
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = TIMx->SMCR;
+  /* Reset the TS Bits */
+  tmpsmcr &= ~TIM_SMCR_TS;
+  /* Set the Input Trigger source and the slave mode*/
+  tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+}
+/**
+  * @brief  Configures the TIMx External Trigger (ETR).
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ExtTRGPrescaler The external Trigger Prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
+  *            @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
+  *            @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
+  *            @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
+  * @param  TIM_ExtTRGPolarity The external Trigger Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
+  *            @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
+  * @param  ExtTRGFilter External Trigger Filter.
+  *          This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
+                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
+{
+  uint32_t tmpsmcr;
+
+  tmpsmcr = TIMx->SMCR;
+
+  /* Reset the ETR Bits */
+  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+
+  /* Set the Prescaler, the Filter value and the Polarity */
+  tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
+
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+}
+
+/**
+  * @brief  Enables or disables the TIM Capture Compare Channel x.
+  * @param  TIMx to select the TIM peripheral
+  * @param  Channel specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1
+  *            @arg TIM_CHANNEL_2: TIM Channel 2
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  *            @arg TIM_CHANNEL_4: TIM Channel 4
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @param  ChannelState specifies the TIM Channel CCxE bit new state.
+  *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
+  * @retval None
+  */
+void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
+{
+  uint32_t tmp;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+  assert_param(IS_TIM_CHANNELS(Channel));
+
+  tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
+
+  /* Reset the CCxE Bit */
+  TIMx->CCER &= ~tmp;
+
+  /* Set or reset the CCxE Bit */
+  TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
+}
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Reset interrupt callbacks to the legacy weak callbacks.
+  * @param  htim pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval None
+  */
+void TIM_ResetCallback(TIM_HandleTypeDef *htim)
+{
+  /* Reset the TIM callback to the legacy weak callbacks */
+  htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;             /* Legacy weak PeriodElapsedCallback             */
+  htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;     /* Legacy weak PeriodElapsedHalfCpltCallback     */
+  htim->TriggerCallback                   = HAL_TIM_TriggerCallback;                   /* Legacy weak TriggerCallback                   */
+  htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;           /* Legacy weak TriggerHalfCpltCallback           */
+  htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;                /* Legacy weak IC_CaptureCallback                */
+  htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;        /* Legacy weak IC_CaptureHalfCpltCallback        */
+  htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;           /* Legacy weak OC_DelayElapsedCallback           */
+  htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;         /* Legacy weak PWM_PulseFinishedCallback         */
+  htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */
+  htim->ErrorCallback                     = HAL_TIM_ErrorCallback;                     /* Legacy weak ErrorCallback                     */
+  htim->CommutationCallback               = HAL_TIMEx_CommutCallback;                  /* Legacy weak CommutationCallback               */
+  htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;          /* Legacy weak CommutationHalfCpltCallback       */
+  htim->BreakCallback                     = HAL_TIMEx_BreakCallback;                   /* Legacy weak BreakCallback                     */
+  htim->Break2Callback                    = HAL_TIMEx_Break2Callback;                  /* Legacy weak Break2Callback                    */
+}
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_TIM_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c
new file mode 100644
index 00000000..1dcd7704
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c
@@ -0,0 +1,2324 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_tim_ex.c
+  * @author  MCD Application Team
+  * @brief   TIM HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Timer Extended peripheral:
+  *           + Time Hall Sensor Interface Initialization
+  *           + Time Hall Sensor Interface Start
+  *           + Time Complementary signal break and dead time configuration
+  *           + Time Master and Slave synchronization configuration
+  *           + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
+  *           + Timer remapping capabilities configuration
+  @verbatim
+  ==============================================================================
+                      ##### TIMER Extended features #####
+  ==============================================================================
+  [..]
+    The Timer Extended features include:
+    (#) Complementary outputs with programmable dead-time for :
+        (++) Output Compare
+        (++) PWM generation (Edge and Center-aligned Mode)
+        (++) One-pulse mode output
+    (#) Synchronization circuit to control the timer with external signals and to
+        interconnect several timers together.
+    (#) Break input to put the timer output signals in reset state or in a known state.
+    (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
+        positioning purposes
+
+            ##### How to use this driver #####
+  ==============================================================================
+    [..]
+     (#) Initialize the TIM low level resources by implementing the following functions
+         depending on the selected feature:
+           (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
+
+     (#) Initialize the TIM low level resources :
+        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
+        (##) TIM pins configuration
+            (+++) Enable the clock for the TIM GPIOs using the following function:
+              __HAL_RCC_GPIOx_CLK_ENABLE();
+            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
+
+     (#) The external Clock can be configured, if needed (the default clock is the
+         internal clock from the APBx), using the following function:
+         HAL_TIM_ConfigClockSource, the clock configuration should be done before
+         any start function.
+
+     (#) Configure the TIM in the desired functioning mode using one of the
+         initialization function of this driver:
+          (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the
+               Timer Hall Sensor Interface and the commutation event with the corresponding
+               Interrupt and DMA request if needed (Note that One Timer is used to interface
+               with the Hall sensor Interface and another Timer should be used to use
+               the commutation event).
+
+     (#) Activate the TIM peripheral using one of the start functions:
+           (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()
+           (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
+           (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
+           (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup TIMEx TIMEx
+  * @brief TIM Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
+  * @brief    Timer Hall Sensor functions
+  *
+@verbatim
+  ==============================================================================
+                      ##### Timer Hall Sensor functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure TIM HAL Sensor.
+    (+) De-initialize TIM HAL Sensor.
+    (+) Start the Hall Sensor Interface.
+    (+) Stop the Hall Sensor Interface.
+    (+) Start the Hall Sensor Interface and enable interrupts.
+    (+) Stop the Hall Sensor Interface and disable interrupts.
+    (+) Start the Hall Sensor Interface and enable DMA transfers.
+    (+) Stop the Hall Sensor Interface and disable DMA transfers.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Hall Sensor Interface and initialize the associated handle.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @param  sConfig TIM Hall Sensor configuration structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
+{
+  TIM_OC_InitTypeDef OC_Config;
+
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+  assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+  assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy week callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->HallSensor_MspInitCallback == NULL)
+    {
+      htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->HallSensor_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIMEx_HallSensor_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Configure the Time base in the Encoder Mode */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the  Hall sensor */
+  TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
+
+  /* Reset the IC1PSC Bits */
+  htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+  /* Set the IC1PSC value */
+  htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
+
+  /* Enable the Hall sensor interface (XOR function of the three inputs) */
+  htim->Instance->CR2 |= TIM_CR2_TI1S;
+
+  /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
+  htim->Instance->SMCR &= ~TIM_SMCR_TS;
+  htim->Instance->SMCR |= TIM_TS_TI1F_ED;
+
+  /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
+  htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+  htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
+
+  /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
+  OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
+  OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
+  OC_Config.OCMode = TIM_OCMODE_PWM2;
+  OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
+  OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
+  OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
+  OC_Config.Pulse = sConfig->Commutation_Delay;
+
+  TIM_OC2_SetConfig(htim->Instance, &OC_Config);
+
+  /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
+    register to 101 */
+  htim->Instance->CR2 &= ~TIM_CR2_MMS;
+  htim->Instance->CR2 |= TIM_TRGO_OC2REF;
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM Hall Sensor interface
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->HallSensor_MspDeInitCallback == NULL)
+  {
+    htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->HallSensor_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIMEx_HallSensor_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Hall Sensor MSP.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Hall Sensor MSP.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Hall Sensor Interface.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Enable the Input Capture channel 1
+    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Hall sensor Interface.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channels 1, 2 and 3
+    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Hall Sensor Interface in interrupt mode.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Enable the capture compare Interrupts 1 event */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+  /* Enable the Input Capture channel 1
+    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Hall Sensor Interface in interrupt mode.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channel 1
+    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+  /* Disable the capture compare Interrupts event */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Hall Sensor Interface in DMA mode.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @param  pData The destination Buffer address.
+  * @param  Length The length of data to be transferred from TIM peripheral to memory.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if (((uint32_t)pData == 0U) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+  /* Enable the Input Capture channel 1
+    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+  /* Set the DMA Input Capture 1 Callbacks */
+  htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+  htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+  /* Set the DMA error callback */
+  htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+  /* Enable the DMA stream for Capture 1*/
+  if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  /* Enable the capture compare 1 Interrupt */
+  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Hall Sensor Interface in DMA mode.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channel 1
+    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+
+  /* Disable the capture compare Interrupts 1 event */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+
+  (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
+  *  @brief   Timer Complementary Output Compare functions
+  *
+@verbatim
+  ==============================================================================
+              ##### Timer Complementary Output Compare functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Start the Complementary Output Compare/PWM.
+    (+) Stop the Complementary Output Compare/PWM.
+    (+) Start the Complementary Output Compare/PWM and enable interrupts.
+    (+) Stop the Complementary Output Compare/PWM and disable interrupts.
+    (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
+    (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation on the complementary
+  *         output.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Enable the Capture compare channel N */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation on the complementary
+  *         output.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the Capture compare channel N */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in interrupt mode
+  *         on the complementary output.
+  * @param  htim TIM OC handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Output Compare interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Output Compare interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Output Compare interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+
+    default:
+      break;
+  }
+
+  /* Enable the TIM Break interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+
+  /* Enable the Capture compare channel N */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in interrupt mode
+  *         on the complementary output.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpccer;
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Output Compare interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Output Compare interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Output Compare interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Disable the Capture compare channel N */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+  /* Disable the TIM Break interrupt (only if no more channel is active) */
+  tmpccer = htim->Instance->CCER;
+  if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
+  {
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+  }
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in DMA mode
+  *         on the complementary output.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if (((uint32_t)pData == 0U) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do  */
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Output Compare DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Output Compare DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Output Compare DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Enable the Capture compare channel N */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in DMA mode
+  *         on the complementary output.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Output Compare DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Output Compare DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Output Compare DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Disable the Capture compare channel N */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
+  * @brief    Timer Complementary PWM functions
+  *
+@verbatim
+  ==============================================================================
+                 ##### Timer Complementary PWM functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Start the Complementary PWM.
+    (+) Stop the Complementary PWM.
+    (+) Start the Complementary PWM and enable interrupts.
+    (+) Stop the Complementary PWM and disable interrupts.
+    (+) Start the Complementary PWM and enable DMA transfers.
+    (+) Stop the Complementary PWM and disable DMA transfers.
+    (+) Start the Complementary Input Capture measurement.
+    (+) Stop the Complementary Input Capture.
+    (+) Start the Complementary Input Capture and enable interrupts.
+    (+) Stop the Complementary Input Capture and disable interrupts.
+    (+) Start the Complementary Input Capture and enable DMA transfers.
+    (+) Stop the Complementary Input Capture and disable DMA transfers.
+    (+) Start the Complementary One Pulse generation.
+    (+) Stop the Complementary One Pulse.
+    (+) Start the Complementary One Pulse and enable interrupts.
+    (+) Stop the Complementary One Pulse and disable interrupts.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the PWM signal generation on the complementary output.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Enable the complementary PWM output  */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the PWM signal generation on the complementary output.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the complementary PWM output  */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the PWM signal generation in interrupt mode on the
+  *         complementary output.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Enable the TIM Break interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+
+  /* Enable the complementary PWM output  */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the PWM signal generation in interrupt mode on the
+  *         complementary output.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpccer;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Disable the complementary PWM output  */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+  /* Disable the TIM Break interrupt (only if no more channel is active) */
+  tmpccer = htim->Instance->CCER;
+  if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
+  {
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+  }
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM PWM signal generation in DMA mode on the
+  *         complementary output
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if (((uint32_t)pData == 0U) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Enable the complementary PWM output  */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM PWM signal generation in DMA mode on the complementary
+  *         output
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Disable the complementary PWM output */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
+  * @brief    Timer Complementary One Pulse functions
+  *
+@verbatim
+  ==============================================================================
+                ##### Timer Complementary One Pulse functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Start the Complementary One Pulse generation.
+    (+) Stop the Complementary One Pulse.
+    (+) Start the Complementary One Pulse and enable interrupts.
+    (+) Stop the Complementary One Pulse and disable interrupts.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation on the complementary
+  *         output.
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+  /* Enable the complementary One Pulse output */
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM One Pulse signal generation on the complementary
+  *         output.
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+  /* Disable the complementary One Pulse output */
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation in interrupt mode on the
+  *         complementary channel.
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+  /* Enable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+  /* Enable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+
+  /* Enable the complementary One Pulse output */
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM One Pulse signal generation in interrupt mode on the
+  *         complementary channel.
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+  /* Disable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+  /* Disable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+
+  /* Disable the complementary One Pulse output */
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
+  * @brief    Peripheral Control functions
+  *
+@verbatim
+  ==============================================================================
+                    ##### Peripheral Control functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+      (+) Configure the commutation event in case of use of the Hall sensor interface.
+      (+) Configure Output channels for OC and PWM mode.
+
+      (+) Configure Complementary channels, break features and dead time.
+      (+) Configure Master synchronization.
+      (+) Configure timer remapping capabilities.
+      (+) Select timer input source.
+      (+) Enable or disable channel grouping.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the TIM commutation event sequence.
+  * @note  This function is mandatory to use the commutation event in order to
+  *        update the configuration at each commutation detection on the TRGI input of the Timer,
+  *        the typical use of this feature is with the use of another Timer(interface Timer)
+  *        configured in Hall sensor interface, this interface Timer will generate the
+  *        commutation at its TRGO output (connected to Timer used in this function) each time
+  *        the TI1 of the Interface Timer detect a commutation at its input TI1.
+  * @param  htim TIM handle
+  * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal trigger 0 selected
+  *            @arg TIM_TS_ITR1: Internal trigger 1 selected
+  *            @arg TIM_TS_ITR2: Internal trigger 2 selected
+  *            @arg TIM_TS_ITR3: Internal trigger 3 selected
+  *            @arg TIM_TS_ITR12: Internal trigger 12 selected (*)
+  *            @arg TIM_TS_ITR13: Internal trigger 13 selected (*)
+  *            @arg TIM_TS_NONE: No trigger is needed
+  * @param  CommutationSource the Commutation Event source
+  *          This parameter can be one of the following values:
+  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                              uint32_t  CommutationSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
+      (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
+      (InputTrigger == TIM_TS_ITR12)  || (InputTrigger == TIM_TS_ITR13))
+  {
+    /* Select the Input trigger */
+    htim->Instance->SMCR &= ~TIM_SMCR_TS;
+    htim->Instance->SMCR |= InputTrigger;
+  }
+
+  /* Select the Capture Compare preload feature */
+  htim->Instance->CR2 |= TIM_CR2_CCPC;
+  /* Select the Commutation event source */
+  htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+  htim->Instance->CR2 |= CommutationSource;
+
+  /* Disable Commutation Interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
+
+  /* Disable Commutation DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the TIM commutation event sequence with interrupt.
+  * @note  This function is mandatory to use the commutation event in order to
+  *        update the configuration at each commutation detection on the TRGI input of the Timer,
+  *        the typical use of this feature is with the use of another Timer(interface Timer)
+  *        configured in Hall sensor interface, this interface Timer will generate the
+  *        commutation at its TRGO output (connected to Timer used in this function) each time
+  *        the TI1 of the Interface Timer detect a commutation at its input TI1.
+  * @param  htim TIM handle
+  * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal trigger 0 selected
+  *            @arg TIM_TS_ITR1: Internal trigger 1 selected
+  *            @arg TIM_TS_ITR2: Internal trigger 2 selected
+  *            @arg TIM_TS_ITR3: Internal trigger 3 selected
+  *            @arg TIM_TS_ITR2: Internal trigger 12 selected (*)
+  *            @arg TIM_TS_ITR3: Internal trigger 13 selected (*)
+  *            @arg TIM_TS_NONE: No trigger is needed
+  * @param  CommutationSource the Commutation Event source
+  *          This parameter can be one of the following values:
+  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                                 uint32_t  CommutationSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
+      (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
+      (InputTrigger == TIM_TS_ITR12)  || (InputTrigger == TIM_TS_ITR13))
+  {
+    /* Select the Input trigger */
+    htim->Instance->SMCR &= ~TIM_SMCR_TS;
+    htim->Instance->SMCR |= InputTrigger;
+  }
+
+  /* Select the Capture Compare preload feature */
+  htim->Instance->CR2 |= TIM_CR2_CCPC;
+  /* Select the Commutation event source */
+  htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+  htim->Instance->CR2 |= CommutationSource;
+
+  /* Disable Commutation DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
+
+  /* Enable the Commutation Interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the TIM commutation event sequence with DMA.
+  * @note  This function is mandatory to use the commutation event in order to
+  *        update the configuration at each commutation detection on the TRGI input of the Timer,
+  *        the typical use of this feature is with the use of another Timer(interface Timer)
+  *        configured in Hall sensor interface, this interface Timer will generate the
+  *        commutation at its TRGO output (connected to Timer used in this function) each time
+  *        the TI1 of the Interface Timer detect a commutation at its input TI1.
+  * @note  The user should configure the DMA in his own software, in This function only the COMDE bit is set
+  * @param  htim TIM handle
+  * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal trigger 0 selected
+  *            @arg TIM_TS_ITR1: Internal trigger 1 selected
+  *            @arg TIM_TS_ITR2: Internal trigger 2 selected
+  *            @arg TIM_TS_ITR3: Internal trigger 3 selected
+  *            @arg TIM_TS_ITR2: Internal trigger 12 selected (*)
+  *            @arg TIM_TS_ITR3: Internal trigger 13 selected (*)
+  *            @arg TIM_TS_NONE: No trigger is needed
+  *
+  *         (*)  Value not defined in all devices.
+  *
+  * @param  CommutationSource the Commutation Event source
+  *          This parameter can be one of the following values:
+  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                                  uint32_t  CommutationSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
+      (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
+      (InputTrigger == TIM_TS_ITR12)  || (InputTrigger == TIM_TS_ITR13))
+  {
+    /* Select the Input trigger */
+    htim->Instance->SMCR &= ~TIM_SMCR_TS;
+    htim->Instance->SMCR |= InputTrigger;
+  }
+
+  /* Select the Capture Compare preload feature */
+  htim->Instance->CR2 |= TIM_CR2_CCPC;
+  /* Select the Commutation event source */
+  htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+  htim->Instance->CR2 |= CommutationSource;
+
+  /* Enable the Commutation DMA Request */
+  /* Set the DMA Commutation Callback */
+  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
+  /* Set the DMA error callback */
+  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
+
+  /* Disable Commutation Interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
+
+  /* Enable the Commutation DMA Request */
+  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the TIM in master mode.
+  * @param  htim TIM handle.
+  * @param  sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
+  *         contains the selected trigger output (TRGO) and the Master/Slave
+  *         mode.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+                                                        TIM_MasterConfigTypeDef *sMasterConfig)
+{
+  uint32_t tmpcr2;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
+  assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
+
+  /* Check input state */
+  __HAL_LOCK(htim);
+
+  /* Change the handler state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = htim->Instance->CR2;
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = htim->Instance->SMCR;
+
+  /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
+  if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
+  {
+    /* Check the parameters */
+    assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
+
+    /* Clear the MMS2 bits */
+    tmpcr2 &= ~TIM_CR2_MMS2;
+    /* Select the TRGO2 source*/
+    tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
+  }
+
+  /* Reset the MMS Bits */
+  tmpcr2 &= ~TIM_CR2_MMS;
+  /* Select the TRGO source */
+  tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
+
+  /* Update TIMx CR2 */
+  htim->Instance->CR2 = tmpcr2;
+
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    /* Reset the MSM Bit */
+    tmpsmcr &= ~TIM_SMCR_MSM;
+    /* Set master mode */
+    tmpsmcr |= sMasterConfig->MasterSlaveMode;
+
+    /* Update TIMx SMCR */
+    htim->Instance->SMCR = tmpsmcr;
+  }
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the Break feature, dead time, Lock level, OSSI/OSSR State
+  *         and the AOE(automatic output enable).
+  * @param  htim TIM handle
+  * @param  sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
+  *         contains the BDTR Register configuration  information for the TIM peripheral.
+  * @note   Interrupts can be generated when an active level is detected on the
+  *         break input, the break 2 input or the system break input. Break
+  *         interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
+                                                TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
+{
+  /* Keep this variable initialized to 0 as it is used to configure BDTR register */
+  uint32_t tmpbdtr = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
+  assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
+  assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
+  assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
+  assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
+  assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
+  assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
+  assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
+
+  /* Check input state */
+  __HAL_LOCK(htim);
+
+  /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
+     the OSSI State, the dead time value and the Automatic Output Enable Bit */
+
+  /* Set the BDTR bits */
+  MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
+
+  if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
+  {
+    /* Check the parameters */
+    assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
+    assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
+    assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
+
+    /* Set the BREAK2 input related BDTR bits */
+    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
+    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
+    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
+  }
+
+  /* Set TIMx_BDTR */
+  htim->Instance->BDTR = tmpbdtr;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+#if defined(TIM_BREAK_INPUT_SUPPORT)
+
+/**
+  * @brief  Configures the break input source.
+  * @param  htim TIM handle.
+  * @param  BreakInput Break input to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_BREAKINPUT_BRK: Timer break input
+  *            @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
+  * @param  sBreakInputConfig Break input source configuration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
+                                             uint32_t BreakInput,
+                                             TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
+
+{
+  uint32_t tmporx;
+  uint32_t bkin_enable_mask;
+  uint32_t bkin_polarity_mask;
+  uint32_t bkin_enable_bitpos;
+  uint32_t bkin_polarity_bitpos;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_BREAKINPUT(BreakInput));
+  assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
+  assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
+  if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
+  {
+    assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
+  }
+
+  /* Check input state */
+  __HAL_LOCK(htim);
+
+  switch (sBreakInputConfig->Source)
+  {
+    case TIM_BREAKINPUTSOURCE_BKIN:
+    {
+      bkin_enable_mask = TIM1_AF1_BKINE;
+      bkin_enable_bitpos = TIM1_AF1_BKINE_Pos;
+      bkin_polarity_mask = TIM1_AF1_BKINP;
+      bkin_polarity_bitpos = TIM1_AF1_BKINP_Pos;
+      break;
+    }
+    case TIM_BREAKINPUTSOURCE_COMP1:
+    {
+      bkin_enable_mask = TIM1_AF1_BKCMP1E;
+      bkin_enable_bitpos = TIM1_AF1_BKCMP1E_Pos;
+      bkin_polarity_mask = TIM1_AF1_BKCMP1P;
+      bkin_polarity_bitpos = TIM1_AF1_BKCMP1P_Pos;
+      break;
+    }
+    case TIM_BREAKINPUTSOURCE_COMP2:
+    {
+      bkin_enable_mask = TIM1_AF1_BKCMP2E;
+      bkin_enable_bitpos = TIM1_AF1_BKCMP2E_Pos;
+      bkin_polarity_mask = TIM1_AF1_BKCMP2P;
+      bkin_polarity_bitpos = TIM1_AF1_BKCMP2P_Pos;
+      break;
+    }
+    case TIM_BREAKINPUTSOURCE_DFSDM1:
+    {
+      bkin_enable_mask = TIM1_AF1_BKDF1BK0E;
+      bkin_enable_bitpos = 8U;
+      bkin_polarity_mask = 0U;
+      bkin_polarity_bitpos = 0U;
+      break;
+    }
+
+    default:
+    {
+      bkin_enable_mask = 0U;
+      bkin_polarity_mask = 0U;
+      bkin_enable_bitpos = 0U;
+      bkin_polarity_bitpos = 0U;
+      break;
+    }
+  }
+
+  switch (BreakInput)
+  {
+    case TIM_BREAKINPUT_BRK:
+    {
+      /* Get the TIMx_AF1 register value */
+      tmporx = htim->Instance->AF1;
+
+      /* Enable the break input */
+      tmporx &= ~bkin_enable_mask;
+      tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
+
+      /* Set the break input polarity */
+      if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
+      {
+        tmporx &= ~bkin_polarity_mask;
+        tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
+      }
+
+      /* Set TIMx_AF1 */
+      htim->Instance->AF1 = tmporx;
+      break;
+    }
+    case TIM_BREAKINPUT_BRK2:
+    {
+      /* Get the TIMx_AF2 register value */
+      tmporx = htim->Instance->AF2;
+
+      /* Enable the break input */
+      tmporx &= ~bkin_enable_mask;
+      tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
+
+      /* Set the break input polarity */
+      if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
+      {
+        tmporx &= ~bkin_polarity_mask;
+        tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
+      }
+
+      /* Set TIMx_AF2 */
+      htim->Instance->AF2 = tmporx;
+      break;
+    }
+    default:
+      break;
+  }
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+#endif /*TIM_BREAK_INPUT_SUPPORT */
+
+/**
+  * @brief  Configures the TIMx Remapping input capabilities.
+  * @param  htim TIM handle.
+  * @param  Remap specifies the TIM remapping source.
+  *         For TIM1, the parameter is one of the following values:
+  *            @arg TIM_TIM1_ETR_GPIO:               TIM1_ETR is connected to GPIO
+  *            @arg TIM_TIM1_ETR_COMP1:              TIM1_ETR is connected to COMP1 output
+  *            @arg TIM_TIM1_ETR_COMP2:              TIM1_ETR is connected to COMP2 output
+  *            @arg TIM_TIM1_ETR_ADC1_AWD1:          TIM1_ETR is connected to ADC1 AWD1
+  *            @arg TIM_TIM1_ETR_ADC1_AWD2:          TIM1_ETR is connected to ADC1 AWD2
+  *            @arg TIM_TIM1_ETR_ADC1_AWD3:          TIM1_ETR is connected to ADC1 AWD3
+  *            @arg TIM_TIM1_ETR_ADC3_AWD1:          TIM1_ETR is connected to ADC3 AWD1
+  *            @arg TIM_TIM1_ETR_ADC3_AWD2:          TIM1_ETR is connected to ADC3 AWD2
+  *            @arg TIM_TIM1_ETR_ADC3_AWD3:          TIM1_ETR is connected to ADC3 AWD3
+  *
+  *         For TIM2, the parameter is one of the following values:
+  *            @arg TIM_TIM2_ETR_GPIO:               TIM2_ETR is connected to GPIO
+  *            @arg TIM_TIM2_ETR_COMP1:              TIM2_ETR is connected to COMP1 output
+  *            @arg TIM_TIM2_ETR_COMP2:              TIM2_ETR is connected to COMP2 output
+  *            @arg TIM_TIM2_ETR_LSE:                TIM2_ETR is connected to LSE
+  *            @arg TIM_TIM2_ETR_SAI1_FSA:           TIM2_ETR is connected to SAI1 FS_A
+  *            @arg TIM_TIM2_ETR_SAI1_FSB:           TIM2_ETR is connected to SAI1 FS_B
+  *
+  *         For TIM3, the parameter is one of the following values:
+  *            @arg TIM_TIM3_ETR_GPIO:               TIM3_ETR is connected to GPIO
+  *            @arg TIM_TIM3_ETR_COMP1:              TIM3_ETR is connected to COMP1 output
+  *
+  *         For TIM5, the parameter is one of the following values:
+  *            @arg TIM_TIM5_ETR_GPIO:               TIM5_ETR is connected to GPIO
+  *            @arg TIM_TIM5_ETR_SAI2_FSA:           TIM5_ETR is connected to SAI2 FS_A (*)
+  *            @arg TIM_TIM5_ETR_SAI2_FSB:           TIM5_ETR is connected to SAI2 FS_B (*)
+  *            @arg TIM_TIM5_ETR_SAI4_FSA:           TIM5_ETR is connected to SAI2 FS_A (*)
+  *            @arg TIM_TIM5_ETR_SAI4_FSB:           TIM5_ETR is connected to SAI2 FS_B (*)
+  *
+  *         For TIM8, the parameter is one of the following values:
+  *            @arg TIM_TIM8_ETR_GPIO:               TIM8_ETR is connected to GPIO
+  *            @arg TIM_TIM8_ETR_COMP1:              TIM8_ETR is connected to COMP1 output
+  *            @arg TIM_TIM8_ETR_COMP2:              TIM8_ETR is connected to COMP2 output
+  *            @arg TIM_TIM8_ETR_ADC2_AWD1:          TIM8_ETR is connected to ADC2 AWD1
+  *            @arg TIM_TIM8_ETR_ADC2_AWD2:          TIM8_ETR is connected to ADC2 AWD2
+  *            @arg TIM_TIM8_ETR_ADC2_AWD3:          TIM8_ETR is connected to ADC2 AWD3
+  *            @arg TIM_TIM8_ETR_ADC3_AWD1:          TIM8_ETR is connected to ADC3 AWD1
+  *            @arg TIM_TIM8_ETR_ADC3_AWD2:          TIM8_ETR is connected to ADC3 AWD2
+  *            @arg TIM_TIM8_ETR_ADC3_AWD3:          TIM8_ETR is connected to ADC3 AWD3
+  *
+  *         For TIM23, the parameter is one of the following values: (*)
+  *            @arg TIM_TIM23_ETR_GPIO               TIM23_ETR is connected to GPIO
+  *            @arg TIM_TIM23_ETR_COMP1              TIM23_ETR is connected to COMP1 output
+  *            @arg TIM_TIM23_ETR_COMP2              TIM23_ETR is connected to COMP2 output
+  *
+  *         For TIM24, the parameter is one of the following values: (*)
+  *           @arg TIM_TIM24_ETR_GPIO                TIM24_ETR is connected to GPIO
+  *           @arg TIM_TIM24_ETR_SAI4_FSA            TIM24_ETR is connected to SAI4 FS_A
+  *           @arg TIM_TIM24_ETR_SAI4_FSB            TIM24_ETR is connected to SAI4 FS_B
+  *           @arg TIM_TIM24_ETR_SAI1_FSA            TIM24_ETR is connected to SAI1 FS_A
+  *           @arg TIM_TIM24_ETR_SAI1_FSB            TIM24_ETR is connected to SAI1 FS_B
+  *
+  *         (*)  Value not defined in all devices.
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
+{
+  /* Check parameters */
+  assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_REMAP(Remap));
+
+  __HAL_LOCK(htim);
+
+  MODIFY_REG(htim->Instance->AF1, TIM1_AF1_ETRSEL_Msk, Remap);
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Select the timer input source
+  * @param  htim TIM handle.
+  * @param  Channel specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TI1 input channel
+  *            @arg TIM_CHANNEL_2: TI2 input channel
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  *            @arg TIM_CHANNEL_4: TIM Channel 4
+  * @param  TISelection parameter of the TIM_TISelectionStruct structure is detailed as follows:
+  *         For TIM1, the parameter is one of the following values:
+  *            @arg TIM_TIM1_TI1_GPIO:                TIM1 TI1 is connected to GPIO
+  *            @arg TIM_TIM1_TI1_COMP1:               TIM1 TI1 is connected to COMP1 output
+  *
+  *         For TIM2, the parameter is one of the following values:
+  *            @arg TIM_TIM2_TI4_GPIO:                TIM2 TI4 is connected to GPIO
+  *            @arg TIM_TIM2_TI4_COMP1:               TIM2 TI4 is connected to COMP1 output
+  *            @arg TIM_TIM2_TI4_COMP2:               TIM2 TI4 is connected to COMP2 output
+  *            @arg TIM_TIM2_TI4_COMP1_COMP2:         TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output
+  *
+  *         For TIM3, the parameter is one of the following values:
+  *            @arg TIM_TIM3_TI1_GPIO:                TIM3 TI1 is connected to GPIO
+  *            @arg TIM_TIM3_TI1_COMP1:               TIM3 TI1 is connected to COMP1 output
+  *            @arg TIM_TIM3_TI1_COMP2:               TIM3 TI1 is connected to COMP2 output
+  *            @arg TIM_TIM3_TI1_COMP1_COMP2:         TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output
+  *
+  *         For TIM5, the parameter is one of the following values:
+  *            @arg TIM_TIM5_TI1_GPIO:                TIM5 TI1 is connected to GPIO
+  *            @arg TIM_TIM5_TI1_CAN_TMP:             TIM5 TI1 is connected to CAN TMP
+  *            @arg TIM_TIM5_TI1_CAN_RTP:             TIM5 TI1 is connected to CAN RTP
+  *
+  *         For TIM8, the parameter is one of the following values:
+  *            @arg TIM_TIM8_TI1_GPIO:               TIM8 TI1 is connected to GPIO
+  *            @arg TIM_TIM8_TI1_COMP2:              TIM8 TI1 is connected to COMP2 output
+  *
+  *         For TIM12, the parameter can have the following values: (*)
+  *            @arg TIM_TIM12_TI1_GPIO:              TIM12 TI1 is connected to GPIO
+  *            @arg TIM_TIM12_TI1_SPDIF_FS:          TIM12 TI1 is connected to SPDIF FS
+  *
+  *         For TIM15, the parameter is one of the following values:
+  *            @arg TIM_TIM15_TI1_GPIO:              TIM15 TI1 is connected to GPIO
+  *            @arg TIM_TIM15_TI1_TIM2:              TIM15 TI1 is connected to TIM2 CH1
+  *            @arg TIM_TIM15_TI1_TIM3:              TIM15 TI1 is connected to TIM3 CH1
+  *            @arg TIM_TIM15_TI1_TIM4:              TIM15 TI1 is connected to TIM4 CH1
+  *            @arg TIM_TIM15_TI1_LSE:               TIM15 TI1 is connected to LSE
+  *            @arg TIM_TIM15_TI1_CSI:               TIM15 TI1 is connected to CSI
+  *            @arg TIM_TIM15_TI1_MCO2:              TIM15 TI1 is connected to MCO2
+  *            @arg TIM_TIM15_TI2_GPIO:              TIM15 TI2 is connected to GPIO
+  *            @arg TIM_TIM15_TI2_TIM2:              TIM15 TI2 is connected to TIM2 CH2
+  *            @arg TIM_TIM15_TI2_TIM3:              TIM15 TI2 is connected to TIM3 CH2
+  *            @arg TIM_TIM15_TI2_TIM4:              TIM15 TI2 is connected to TIM4 CH2
+  *
+  *         For TIM16, the parameter can have the following values:
+  *            @arg TIM_TIM16_TI1_GPIO:              TIM16 TI1 is connected to GPIO
+  *            @arg TIM_TIM16_TI1_LSI:               TIM16 TI1 is connected to LSI
+  *            @arg TIM_TIM16_TI1_LSE:               TIM16 TI1 is connected to LSE
+  *            @arg TIM_TIM16_TI1_RTC:               TIM16 TI1 is connected to RTC wakeup interrupt
+  *
+  *         For TIM17, the parameter can have the following values:
+  *            @arg TIM_TIM17_TI1_GPIO:              TIM17 TI1 is connected to GPIO
+  *            @arg TIM_TIM17_TI1_SPDIF_FS:          TIM17 TI1 is connected to SPDIF FS (*)
+  *            @arg TIM_TIM17_TI1_HSE_1MHZ:          TIM17 TI1 is connected to HSE 1MHz
+  *            @arg TIM_TIM17_TI1_MCO1:              TIM17 TI1 is connected to MCO1
+  *
+  *         For TIM23, the parameter can have the following values: (*)
+  *            @arg TIM_TIM23_TI4_GPIO               TIM23_TI4 is connected to GPIO
+  *            @arg TIM_TIM23_TI4_COMP1              TIM23_TI4 is connected to COMP1 output
+  *            @arg TIM_TIM23_TI4_COMP2              TIM23_TI4 is connected to COMP2 output
+  *            @arg TIM_TIM23_TI4_COMP1_COMP2        TIM23_TI4 is connected to COMP2 output
+  *
+  *         For TIM24, the parameter can have the following values: (*)
+  *            @arg TIM_TIM24_TI1_GPIO               TIM24_TI1 is connected to GPIO
+  *            @arg TIM_TIM24_TI1_CAN_TMP            TIM24_TI1 is connected to CAN_TMP
+  *            @arg TIM_TIM24_TI1_CAN_RTP            TIM24_TI1 is connected to CAN_RTP
+  *            @arg TIM_TIM24_TI1_CAN_SOC            TIM24_TI1 is connected to CAN_SOC
+  *
+  *         (*)  Value not defined in all devices. \n
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_TIM_TISEL_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_TISEL(TISelection));
+
+  __HAL_LOCK(htim);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+      MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI1SEL, TISelection);
+      break;
+    case TIM_CHANNEL_2:
+      MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI2SEL, TISelection);
+      break;
+    case TIM_CHANNEL_3:
+      MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI3SEL, TISelection);
+      break;
+    case TIM_CHANNEL_4:
+      MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI4SEL, TISelection);
+      break;
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+
+/**
+  * @brief  Group channel 5 and channel 1, 2 or 3
+  * @param  htim TIM handle.
+  * @param  Channels specifies the reference signal(s) the OC5REF is combined with.
+  *         This parameter can be any combination of the following values:
+  *         TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
+  *         TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
+  *         TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
+  *         TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)
+{
+  /* Check parameters */
+  assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_GROUPCH5(Channels));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Clear GC5Cx bit fields */
+  htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1);
+
+  /* Set GC5Cx bit fields */
+  htim->Instance->CCR5 |= Channels;
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
+  * @brief    Extended Callbacks functions
+  *
+@verbatim
+  ==============================================================================
+                    ##### Extended Callbacks functions #####
+  ==============================================================================
+  [..]
+    This section provides Extended TIM callback functions:
+    (+) Timer Commutation callback
+    (+) Timer Break callback
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Hall commutation changed callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_CommutCallback could be implemented in the user file
+   */
+}
+/**
+  * @brief  Hall commutation changed half complete callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Hall Break detection callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_BreakCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Hall Break2 detection callback in non blocking mode
+  * @param  htim: TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_TIMEx_Break2Callback could be implemented in the user file
+   */
+}
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
+  * @brief    Extended Peripheral State functions
+  *
+@verbatim
+  ==============================================================================
+                ##### Extended Peripheral State functions #####
+  ==============================================================================
+  [..]
+    This subsection permits to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the TIM Hall Sensor interface handle state.
+  * @param  htim TIM Hall Sensor handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
+  * @{
+  */
+
+/**
+  * @brief  TIM DMA Commutation callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->CommutationCallback(htim);
+#else
+  HAL_TIMEx_CommutCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Commutation half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->CommutationHalfCpltCallback(htim);
+#else
+  HAL_TIMEx_CommutHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+
+/**
+  * @brief  Enables or disables the TIM Capture Compare Channel xN.
+  * @param  TIMx to select the TIM peripheral
+  * @param  Channel specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1
+  *            @arg TIM_CHANNEL_2: TIM Channel 2
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  * @param  ChannelNState specifies the TIM Channel CCxNE bit new state.
+  *          This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
+  * @retval None
+  */
+static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
+{
+  uint32_t tmp;
+
+  tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
+
+  /* Reset the CCxNE Bit */
+  TIMx->CCER &=  ~tmp;
+
+  /* Set or reset the CCxNE Bit */
+  TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
+}
+/**
+  * @}
+  */
+
+#endif /* HAL_TIM_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_dma.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_dma.c
new file mode 100644
index 00000000..51dafc51
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_dma.c
@@ -0,0 +1,423 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_dma.c
+  * @author  MCD Application Team
+  * @brief   DMA LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_ll_dma.h"
+#include "stm32h7xx_ll_bus.h"
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined (DMA1) || defined (DMA2)
+
+/** @addtogroup DMA_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup DMA_LL_Private_Macros
+  * @{
+  */
+#define IS_LL_DMA_DIRECTION(__VALUE__)          (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
+                                                 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
+                                                 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
+
+#define IS_LL_DMA_MODE(__VALUE__)               (((__VALUE__) == LL_DMA_MODE_NORMAL)    || \
+                                                 ((__VALUE__) == LL_DMA_MODE_CIRCULAR)  || \
+                                                 ((__VALUE__) == LL_DMA_MODE_PFCTRL))
+
+#define IS_LL_DMA_PERIPHINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
+                                                 ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
+
+#define IS_LL_DMA_MEMORYINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
+                                                 ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
+
+#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE)      || \
+                                                 ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD)  || \
+                                                 ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
+
+#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE)      || \
+                                                 ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD)  || \
+                                                 ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
+
+#define IS_LL_DMA_NBDATA(__VALUE__)             ((__VALUE__)  <= 0x0000FFFFU)
+
+#if defined(ADC3)
+#define IS_LL_DMA_REQUEST(REQUEST)              (((REQUEST)   <= LL_DMAMUX1_REQ_ADC3))
+#else
+#define IS_LL_DMA_REQUEST(REQUEST)              (((REQUEST)   <= LL_DMAMUX1_REQ_USART10_TX))
+#endif /* ADC3 */
+
+#define IS_LL_DMA_PRIORITY(__VALUE__)           (((__VALUE__) == LL_DMA_PRIORITY_LOW)    || \
+                                                 ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
+                                                 ((__VALUE__) == LL_DMA_PRIORITY_HIGH)   || \
+                                                 ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
+
+#define IS_LL_DMA_ALL_STREAM_INSTANCE(INSTANCE, STREAM)   ((((INSTANCE) == DMA1) && \
+                                                           (((STREAM) == LL_DMA_STREAM_0)     || \
+                                                            ((STREAM) == LL_DMA_STREAM_1)     || \
+                                                            ((STREAM) == LL_DMA_STREAM_2)     || \
+                                                            ((STREAM) == LL_DMA_STREAM_3)     || \
+                                                            ((STREAM) == LL_DMA_STREAM_4)     || \
+                                                            ((STREAM) == LL_DMA_STREAM_5)     || \
+                                                            ((STREAM) == LL_DMA_STREAM_6)     || \
+                                                            ((STREAM) == LL_DMA_STREAM_7)     || \
+                                                            ((STREAM) == LL_DMA_STREAM_ALL))) || \
+                                                           (((INSTANCE) == DMA2) && \
+                                                           (((STREAM) == LL_DMA_STREAM_0)     || \
+                                                            ((STREAM) == LL_DMA_STREAM_1)     || \
+                                                            ((STREAM) == LL_DMA_STREAM_2)     || \
+                                                            ((STREAM) == LL_DMA_STREAM_3)     || \
+                                                            ((STREAM) == LL_DMA_STREAM_4)     || \
+                                                            ((STREAM) == LL_DMA_STREAM_5)     || \
+                                                            ((STREAM) == LL_DMA_STREAM_6)     || \
+                                                            ((STREAM) == LL_DMA_STREAM_7)     || \
+                                                            ((STREAM) == LL_DMA_STREAM_ALL))))
+
+#define IS_LL_DMA_FIFO_MODE_STATE(STATE)    (((STATE) == LL_DMA_FIFOMODE_DISABLE ) || \
+                                             ((STATE) == LL_DMA_FIFOMODE_ENABLE))
+
+#define IS_LL_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_4)  || \
+                                             ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_2)  || \
+                                             ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_3_4)  || \
+                                             ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_FULL))
+
+#define IS_LL_DMA_MEMORY_BURST(BURST)       (((BURST) == LL_DMA_MBURST_SINGLE) || \
+                                             ((BURST) == LL_DMA_MBURST_INC4)   || \
+                                             ((BURST) == LL_DMA_MBURST_INC8)   || \
+                                             ((BURST) == LL_DMA_MBURST_INC16))
+
+#define IS_LL_DMA_PERIPHERAL_BURST(BURST)  (((BURST) == LL_DMA_PBURST_SINGLE) || \
+                                            ((BURST) == LL_DMA_PBURST_INC4)   || \
+                                            ((BURST) == LL_DMA_PBURST_INC8)   || \
+                                            ((BURST) == LL_DMA_PBURST_INC16))
+
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DMA_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup DMA_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize the DMA registers to their default reset values.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  *         @arg @ref LL_DMA_STREAM_ALL
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: DMA registers are de-initialized
+  *          - ERROR: DMA registers are not de-initialized
+  */
+uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  DMA_Stream_TypeDef *tmp;
+  ErrorStatus status = SUCCESS;
+
+  /* Check the DMA Instance DMAx and Stream parameters */
+  assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
+
+  if (Stream == LL_DMA_STREAM_ALL)
+  {
+    if (DMAx == DMA1)
+    {
+      /* Force reset of DMA clock */
+      LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
+
+      /* Release reset of DMA clock */
+      LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
+    }
+    else if (DMAx == DMA2)
+    {
+      /* Force reset of DMA clock */
+       LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2);
+
+      /* Release reset of DMA clock */
+      LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2);
+    }
+    else
+    {
+      status = ERROR;
+    }
+  }
+  else
+  {
+    /* Disable the selected Stream */
+    LL_DMA_DisableStream(DMAx, Stream);
+
+    /* Get the DMA Stream Instance */
+    tmp = (DMA_Stream_TypeDef *)(__LL_DMA_GET_STREAM_INSTANCE(DMAx, Stream));
+
+    /* Reset DMAx_Streamy configuration register */
+    LL_DMA_WriteReg(tmp, CR, 0U);
+
+    /* Reset DMAx_Streamy remaining bytes register */
+    LL_DMA_WriteReg(tmp, NDTR, 0U);
+
+    /* Reset DMAx_Streamy peripheral address register */
+    LL_DMA_WriteReg(tmp, PAR, 0U);
+
+    /* Reset DMAx_Streamy memory address register */
+    LL_DMA_WriteReg(tmp, M0AR, 0U);
+
+    /* Reset DMAx_Streamy memory address register */
+    LL_DMA_WriteReg(tmp, M1AR, 0U);
+
+    /* Reset DMAx_Streamy FIFO control register */
+    LL_DMA_WriteReg(tmp, FCR, 0x00000021U);
+
+    /* Reset Channel register field for DMAx Stream */
+    LL_DMA_SetPeriphRequest(DMAx, Stream, LL_DMAMUX1_REQ_MEM2MEM);
+
+    if (Stream == LL_DMA_STREAM_0)
+    {
+      /* Reset the Stream0 pending flags */
+      DMAx->LIFCR = 0x0000003FU;
+    }
+    else if (Stream == LL_DMA_STREAM_1)
+    {
+      /* Reset the Stream1 pending flags */
+      DMAx->LIFCR = 0x00000F40U;
+    }
+    else if (Stream == LL_DMA_STREAM_2)
+    {
+      /* Reset the Stream2 pending flags */
+      DMAx->LIFCR = 0x003F0000U;
+    }
+    else if (Stream == LL_DMA_STREAM_3)
+    {
+      /* Reset the Stream3 pending flags */
+      DMAx->LIFCR = 0x0F400000U;
+    }
+    else if (Stream == LL_DMA_STREAM_4)
+    {
+      /* Reset the Stream4 pending flags */
+      DMAx->HIFCR = 0x0000003FU;
+    }
+    else if (Stream == LL_DMA_STREAM_5)
+    {
+      /* Reset the Stream5 pending flags */
+      DMAx->HIFCR = 0x00000F40U;
+    }
+    else if (Stream == LL_DMA_STREAM_6)
+    {
+      /* Reset the Stream6 pending flags */
+      DMAx->HIFCR = 0x003F0000U;
+    }
+    else if (Stream == LL_DMA_STREAM_7)
+    {
+      /* Reset the Stream7 pending flags */
+      DMAx->HIFCR = 0x0F400000U;
+    }
+    else
+    {
+      status = ERROR;
+    }
+  }
+
+  return (uint32_t)status;
+}
+
+/**
+  * @brief  Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
+  * @note   To convert DMAx_Streamy Instance to DMAx Instance and Streamy, use helper macros :
+  *         @arg @ref __LL_DMA_GET_INSTANCE
+  *         @arg @ref __LL_DMA_GET_STREAM
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: DMA registers are initialized
+  *          - ERROR: Not applicable
+  */
+uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct)
+{
+  /* Check the DMA Instance DMAx and Stream parameters */
+  assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
+
+  /* Check the DMA parameters from DMA_InitStruct */
+  assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
+  assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
+  assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
+  assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
+  assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
+  assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
+  assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
+  assert_param(IS_LL_DMA_REQUEST(DMA_InitStruct->PeriphRequest));
+  assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
+  assert_param(IS_LL_DMA_FIFO_MODE_STATE(DMA_InitStruct->FIFOMode));
+
+  /* Check the memory burst, peripheral burst and FIFO threshold parameters only
+     when FIFO mode is enabled */
+  if (DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
+  {
+    assert_param(IS_LL_DMA_FIFO_THRESHOLD(DMA_InitStruct->FIFOThreshold));
+    assert_param(IS_LL_DMA_MEMORY_BURST(DMA_InitStruct->MemBurst));
+    assert_param(IS_LL_DMA_PERIPHERAL_BURST(DMA_InitStruct->PeriphBurst));
+  }
+
+  /*---------------------------- DMAx SxCR Configuration ------------------------
+   * Configure DMAx_Streamy: data transfer direction, data transfer mode,
+   *                          peripheral and memory increment mode,
+   *                          data size alignment and  priority level with parameters :
+   * - Direction:      DMA_SxCR_DIR[1:0] bits
+   * - Mode:           DMA_SxCR_CIRC bit
+   * - PeriphOrM2MSrcIncMode:  DMA_SxCR_PINC bit
+   * - MemoryOrM2MDstIncMode:  DMA_SxCR_MINC bit
+   * - PeriphOrM2MSrcDataSize: DMA_SxCR_PSIZE[1:0] bits
+   * - MemoryOrM2MDstDataSize: DMA_SxCR_MSIZE[1:0] bits
+   * - Priority:               DMA_SxCR_PL[1:0] bits
+   */
+  LL_DMA_ConfigTransfer(DMAx, Stream, DMA_InitStruct->Direction | \
+                        DMA_InitStruct->Mode                    | \
+                        DMA_InitStruct->PeriphOrM2MSrcIncMode   | \
+                        DMA_InitStruct->MemoryOrM2MDstIncMode   | \
+                        DMA_InitStruct->PeriphOrM2MSrcDataSize  | \
+                        DMA_InitStruct->MemoryOrM2MDstDataSize  | \
+                        DMA_InitStruct->Priority
+                       );
+
+  if (DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
+  {
+    /*---------------------------- DMAx SxFCR Configuration ------------------------
+     * Configure DMAx_Streamy:  fifo mode and fifo threshold with parameters :
+     * - FIFOMode:                DMA_SxFCR_DMDIS bit
+     * - FIFOThreshold:           DMA_SxFCR_FTH[1:0] bits
+     */
+    LL_DMA_ConfigFifo(DMAx, Stream, DMA_InitStruct->FIFOMode, DMA_InitStruct->FIFOThreshold);
+
+    /*---------------------------- DMAx SxCR Configuration --------------------------
+     * Configure DMAx_Streamy:  memory burst transfer with parameters :
+     * - MemBurst:                DMA_SxCR_MBURST[1:0] bits
+     */
+    LL_DMA_SetMemoryBurstxfer(DMAx, Stream, DMA_InitStruct->MemBurst);
+
+    /*---------------------------- DMAx SxCR Configuration --------------------------
+     * Configure DMAx_Streamy:  peripheral burst transfer with parameters :
+     * - PeriphBurst:             DMA_SxCR_PBURST[1:0] bits
+     */
+    LL_DMA_SetPeriphBurstxfer(DMAx, Stream, DMA_InitStruct->PeriphBurst);
+  }
+
+  /*-------------------------- DMAx SxM0AR Configuration --------------------------
+   * Configure the memory or destination base address with parameter :
+   * - MemoryOrM2MDstAddress:     DMA_SxM0AR_M0A[31:0] bits
+   */
+  LL_DMA_SetMemoryAddress(DMAx, Stream, DMA_InitStruct->MemoryOrM2MDstAddress);
+
+  /*-------------------------- DMAx SxPAR Configuration ---------------------------
+   * Configure the peripheral or source base address with parameter :
+   * - PeriphOrM2MSrcAddress:     DMA_SxPAR_PA[31:0] bits
+   */
+  LL_DMA_SetPeriphAddress(DMAx, Stream, DMA_InitStruct->PeriphOrM2MSrcAddress);
+
+  /*--------------------------- DMAx SxNDTR Configuration -------------------------
+   * Configure the peripheral base address with parameter :
+   * - NbData:                    DMA_SxNDT[15:0] bits
+   */
+  LL_DMA_SetDataLength(DMAx, Stream, DMA_InitStruct->NbData);
+
+  /*--------------------------- DMA SxCR_CHSEL Configuration ----------------------
+   * Configure the peripheral base address with parameter :
+   * - PeriphRequest:             DMA_SxCR_CHSEL[3:0] bits
+   */
+  LL_DMA_SetPeriphRequest(DMAx, Stream, DMA_InitStruct->PeriphRequest);
+
+  return (uint32_t)SUCCESS;
+}
+
+/**
+  * @brief  Set each @ref LL_DMA_InitTypeDef field to default value.
+  * @param  DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
+  * @retval None
+  */
+void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
+{
+  /* Set DMA_InitStruct fields to default values */
+  DMA_InitStruct->PeriphOrM2MSrcAddress  = 0x00000000U;
+  DMA_InitStruct->MemoryOrM2MDstAddress  = 0x00000000U;
+  DMA_InitStruct->Direction              = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
+  DMA_InitStruct->Mode                   = LL_DMA_MODE_NORMAL;
+  DMA_InitStruct->PeriphOrM2MSrcIncMode  = LL_DMA_PERIPH_NOINCREMENT;
+  DMA_InitStruct->MemoryOrM2MDstIncMode  = LL_DMA_MEMORY_NOINCREMENT;
+  DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
+  DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
+  DMA_InitStruct->NbData                 = 0x00000000U;
+  DMA_InitStruct->PeriphRequest          = LL_DMAMUX1_REQ_MEM2MEM;
+  DMA_InitStruct->Priority               = LL_DMA_PRIORITY_LOW;
+  DMA_InitStruct->FIFOMode               = LL_DMA_FIFOMODE_DISABLE;
+  DMA_InitStruct->FIFOThreshold          = LL_DMA_FIFOTHRESHOLD_1_4;
+  DMA_InitStruct->MemBurst               = LL_DMA_MBURST_SINGLE;
+  DMA_InitStruct->PeriphBurst            = LL_DMA_PBURST_SINGLE;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* DMA1 || DMA2 */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_exti.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_exti.c
new file mode 100644
index 00000000..f4c6320d
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_exti.c
@@ -0,0 +1,458 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_exti.c
+  * @author  MCD Application Team
+  * @brief   EXTI LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_ll_exti.h"
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined (EXTI)
+
+/** @defgroup EXTI_LL EXTI
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup EXTI_LL_Private_Macros
+  * @{
+  */
+
+#define IS_LL_EXTI_LINE_0_31(__VALUE__)              (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31)  == 0x00000000U)
+#define IS_LL_EXTI_LINE_32_63(__VALUE__)             (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U)
+#define IS_LL_EXTI_LINE_64_95(__VALUE__)             (((__VALUE__) & ~LL_EXTI_LINE_ALL_64_95) == 0x00000000U)
+
+#define IS_LL_EXTI_MODE(__VALUE__)                   (((__VALUE__) == LL_EXTI_MODE_IT)            \
+                                                   || ((__VALUE__) == LL_EXTI_MODE_EVENT)         \
+                                                   || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
+
+
+#define IS_LL_EXTI_TRIGGER(__VALUE__)                (((__VALUE__) == LL_EXTI_TRIGGER_NONE)       \
+                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_RISING)     \
+                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING)    \
+                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))
+
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup EXTI_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup EXTI_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize the EXTI registers to their default reset values.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: EXTI registers are de-initialized
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_EXTI_DeInit(void)
+{
+  /* Rising Trigger selection register set to default reset values */
+  LL_EXTI_WriteReg(RTSR1,  0x00000000U);
+  LL_EXTI_WriteReg(RTSR2,  0x00000000U);
+  LL_EXTI_WriteReg(RTSR3,  0x00000000U);
+
+  /* Falling Trigger selection register set to default reset values */
+  LL_EXTI_WriteReg(FTSR1,  0x00000000U);
+  LL_EXTI_WriteReg(FTSR2,  0x00000000U);
+  LL_EXTI_WriteReg(FTSR3,  0x00000000U);
+
+  /* Software interrupt event register set to default reset values */
+  LL_EXTI_WriteReg(SWIER1, 0x00000000U);
+  LL_EXTI_WriteReg(SWIER2, 0x00000000U);
+  LL_EXTI_WriteReg(SWIER3, 0x00000000U);
+
+  /* D3 Pending register set to default reset values */
+  LL_EXTI_WriteReg(D3PMR1, 0x00000000U);
+  LL_EXTI_WriteReg(D3PMR2, 0x00000000U);
+  LL_EXTI_WriteReg(D3PMR3, 0x00000000U);
+
+  /* D3 Pending clear selection register low to default reset values */
+  LL_EXTI_WriteReg(D3PCR1L, 0x00000000U);
+  LL_EXTI_WriteReg(D3PCR2L, 0x00000000U);
+  LL_EXTI_WriteReg(D3PCR3L, 0x00000000U);
+
+  /* D3 Pending clear selection register high to default reset values */
+  LL_EXTI_WriteReg(D3PCR1H, 0x00000000U);
+  LL_EXTI_WriteReg(D3PCR2H, 0x00000000U);
+  LL_EXTI_WriteReg(D3PCR3H, 0x00000000U);
+
+  /* Interrupt mask register set to default reset values */
+  LL_EXTI_WriteReg(IMR1, 0x00000000U);
+  LL_EXTI_WriteReg(IMR2, 0x00000000U);
+  LL_EXTI_WriteReg(IMR3, 0x00000000U);
+
+  /*  Event mask register set to default reset values */
+  LL_EXTI_WriteReg(EMR1, 0x00000000U);
+  LL_EXTI_WriteReg(EMR2, 0x00000000U);
+  LL_EXTI_WriteReg(EMR3, 0x00000000U);
+
+  /* Clear Pending requests */
+  LL_EXTI_WriteReg(PR1, EXTI_PR1_PR_Msk);
+  LL_EXTI_WriteReg(PR2, EXTI_PR2_PR_Msk);
+  LL_EXTI_WriteReg(PR3, EXTI_PR3_PR_Msk);
+
+#if defined(DUAL_CORE)
+  /* Interrupt mask register set to default reset values  for Core 2 (Coretx-M4)*/
+  LL_EXTI_WriteReg(C2IMR1, 0x00000000U);
+  LL_EXTI_WriteReg(C2IMR2, 0x00000000U);
+  LL_EXTI_WriteReg(C2IMR3, 0x00000000U);
+
+  /*  Event mask register set to default reset values */
+  LL_EXTI_WriteReg(C2EMR1, 0x00000000U);
+  LL_EXTI_WriteReg(C2EMR2, 0x00000000U);
+  LL_EXTI_WriteReg(C2EMR3, 0x00000000U);
+
+  /* Clear Pending requests */
+  LL_EXTI_WriteReg(C2PR1, EXTI_PR1_PR_Msk);
+  LL_EXTI_WriteReg(C2PR2, EXTI_PR2_PR_Msk);
+  LL_EXTI_WriteReg(C2PR3, EXTI_PR3_PR_Msk);
+
+#endif /* DUAL_CORE*/
+  return SUCCESS;
+}
+
+/**
+  * @brief  Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
+  * @param  EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: EXTI registers are initialized
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
+{
+  ErrorStatus status = SUCCESS;
+  /* Check the parameters */
+  assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31));
+  assert_param(IS_LL_EXTI_LINE_32_63(EXTI_InitStruct->Line_32_63));
+  assert_param(IS_LL_EXTI_LINE_64_95(EXTI_InitStruct->Line_64_95));
+  assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand));
+  assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode));
+
+  /* ENABLE LineCommand */
+  if (EXTI_InitStruct->LineCommand != DISABLE)
+  {
+    assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger));
+
+    /* Configure EXTI Lines in range from 0 to 31 */
+    if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE)
+    {
+      if((EXTI_InitStruct->Mode & LL_EXTI_MODE_IT) == LL_EXTI_MODE_IT)
+      {
+        /* Enable IT on provided Lines for Cortex-M7*/
+        LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
+      }
+      else
+      {
+        /* Disable IT on provided Lines for Cortex-M7*/
+        LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
+      }
+
+      if((EXTI_InitStruct->Mode & LL_EXTI_MODE_EVENT) == LL_EXTI_MODE_EVENT)
+      {
+        /* Enable event on provided Lines for Cortex-M7 */
+        LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
+      }
+      else
+      {
+        /* Disable event on provided Lines for Cortex-M7 */
+        LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
+      }
+#if defined(DUAL_CORE)
+      if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_IT) == LL_EXTI_MODE_C2_IT)
+      {
+        /* Enable IT on provided Lines for Cortex-M4 */
+        LL_C2_EXTI_EnableIT_0_31 (EXTI_InitStruct->Line_0_31);
+      }
+      else
+      {
+        /* Disable IT on provided Lines for Cortex-M4*/
+        LL_C2_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
+      }
+
+      if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_EVENT) == LL_EXTI_MODE_C2_EVENT)
+      {
+        /* Enable event on provided Lines for Cortex-M4 */
+        LL_C2_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
+      }
+      else
+      {
+        /* Disable event on provided Lines for Cortex-M4*/
+        LL_C2_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
+      }
+#endif /* DUAL_CORE */
+
+      if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
+      {
+        switch (EXTI_InitStruct->Trigger)
+        {
+          case LL_EXTI_TRIGGER_RISING:
+            /* First Disable Falling Trigger on provided Lines */
+            LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+            /* Then Enable Rising Trigger on provided Lines */
+            LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+            break;
+          case LL_EXTI_TRIGGER_FALLING:
+            /* First Disable Rising Trigger on provided Lines */
+            LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+            /* Then Enable Falling Trigger on provided Lines */
+            LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+            break;
+          case LL_EXTI_TRIGGER_RISING_FALLING:
+            LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+            LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+            break;
+          default:
+            status = ERROR;
+            break;
+        }
+      }
+    }
+    /* Configure EXTI Lines in range from 32 to 63 */
+    if (EXTI_InitStruct->Line_32_63 != LL_EXTI_LINE_NONE)
+    {
+      if((EXTI_InitStruct->Mode & LL_EXTI_MODE_IT) == LL_EXTI_MODE_IT)
+      {
+        /* Enable IT on provided Lines for Cortex-M7*/
+        LL_EXTI_EnableIT_32_63(EXTI_InitStruct->Line_32_63);
+      }
+      else
+      {
+        /* Disable IT on provided Lines for Cortex-M7*/
+        LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
+      }
+
+      if((EXTI_InitStruct->Mode & LL_EXTI_MODE_EVENT) == LL_EXTI_MODE_EVENT)
+      {
+        /* Enable event on provided Lines for Cortex-M7 */
+        LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63);
+      }
+      else
+      {
+        /* Disable event on provided Lines for Cortex-M7 */
+        LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
+      }
+#if defined(DUAL_CORE)
+      if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_IT) == LL_EXTI_MODE_C2_IT)
+      {
+        /* Enable IT on provided Lines for Cortex-M4 */
+        LL_C2_EXTI_EnableIT_32_63 (EXTI_InitStruct->Line_32_63);
+      }
+      else
+      {
+        /* Disable IT on provided Lines for Cortex-M4 */
+        LL_C2_EXTI_DisableIT_32_63 (EXTI_InitStruct->Line_32_63);
+      }
+
+      if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_EVENT) == LL_EXTI_MODE_C2_EVENT)
+      {
+        /* Enable event on provided Lines for Cortex-M4 */
+        LL_C2_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63);
+      }
+      else
+      {
+        /* Disable event on provided Lines for Cortex-M4 */
+        LL_C2_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
+      }
+#endif /* DUAL_CORE */
+
+      if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
+      {
+        switch (EXTI_InitStruct->Trigger)
+        {
+          case LL_EXTI_TRIGGER_RISING:
+            /* First Disable Falling Trigger on provided Lines */
+            LL_EXTI_DisableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
+            /* Then Enable IT on provided Lines */
+            LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
+            break;
+          case LL_EXTI_TRIGGER_FALLING:
+            /* First Disable Rising Trigger on provided Lines */
+            LL_EXTI_DisableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
+            /* Then Enable Falling Trigger on provided Lines */
+            LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
+            break;
+          case LL_EXTI_TRIGGER_RISING_FALLING:
+            LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
+            LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
+            break;
+          default:
+            status = ERROR;
+            break;
+        }
+      }
+    }
+    /* Configure EXTI Lines in range from 64 to 95 */
+    if (EXTI_InitStruct->Line_64_95 != LL_EXTI_LINE_NONE)
+    {
+      if((EXTI_InitStruct->Mode & LL_EXTI_MODE_IT) == LL_EXTI_MODE_IT)
+      {
+        /* Enable IT on provided Lines for Cortex-M7*/
+        LL_EXTI_EnableIT_64_95(EXTI_InitStruct->Line_64_95);
+      }
+      else
+      {
+        /* Disable IT on provided Lines for Cortex-M7*/
+        LL_EXTI_DisableIT_64_95(EXTI_InitStruct->Line_64_95);
+      }
+
+      if((EXTI_InitStruct->Mode & LL_EXTI_MODE_EVENT) == LL_EXTI_MODE_EVENT)
+      {
+        /* Enable event on provided Lines for Cortex-M7 */
+        LL_EXTI_EnableEvent_64_95(EXTI_InitStruct->Line_64_95);
+      }
+      else
+      {
+        /* Disable event on provided Lines for Cortex-M7 */
+        LL_EXTI_DisableEvent_64_95(EXTI_InitStruct->Line_64_95);
+      }
+
+#if defined(DUAL_CORE)
+      if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_IT) == LL_EXTI_MODE_C2_IT)
+      {
+        /* Enable IT on provided Lines for Cortex-M4 */
+        LL_C2_EXTI_EnableIT_64_95 (EXTI_InitStruct->Line_64_95);
+      }
+      else
+      {
+        /* Disable IT on provided Lines for Cortex-M4 */
+        LL_C2_EXTI_DisableIT_64_95 (EXTI_InitStruct->Line_64_95);
+      }
+
+      if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_EVENT) == LL_EXTI_MODE_C2_EVENT)
+      {
+        /* Enable event on provided Lines for Cortex-M4 */
+        LL_C2_EXTI_EnableEvent_64_95(EXTI_InitStruct->Line_64_95);
+      }
+      else
+      {
+        /* Disable event on provided Lines for Cortex-M4 */
+        LL_C2_EXTI_DisableEvent_64_95(EXTI_InitStruct->Line_64_95);
+      }
+#endif /* DUAL_CORE */
+
+      if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
+      {
+        switch (EXTI_InitStruct->Trigger)
+        {
+          case LL_EXTI_TRIGGER_RISING:
+            /* First Disable Falling Trigger on provided Lines */
+            LL_EXTI_DisableFallingTrig_64_95(EXTI_InitStruct->Line_64_95);
+            /* Then Enable IT on provided Lines */
+            LL_EXTI_EnableRisingTrig_64_95(EXTI_InitStruct->Line_64_95);
+            break;
+          case LL_EXTI_TRIGGER_FALLING:
+            /* First Disable Rising Trigger on provided Lines */
+            LL_EXTI_DisableRisingTrig_64_95(EXTI_InitStruct->Line_64_95);
+            /* Then Enable Falling Trigger on provided Lines */
+            LL_EXTI_EnableFallingTrig_64_95(EXTI_InitStruct->Line_64_95);
+            break;
+          case LL_EXTI_TRIGGER_RISING_FALLING:
+            LL_EXTI_EnableRisingTrig_64_95(EXTI_InitStruct->Line_64_95);
+            LL_EXTI_EnableFallingTrig_64_95(EXTI_InitStruct->Line_64_95);
+            break;
+          default:
+            status = ERROR;
+            break;
+        }
+      }
+    }
+  }
+  else /* DISABLE LineCommand */
+  {
+    /* Disable IT on provided Lines for Cortex-M7*/
+    LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
+    LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
+    LL_EXTI_DisableIT_64_95(EXTI_InitStruct->Line_64_95);
+
+    /* Disable event on provided Lines for Cortex-M7 */
+    LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
+    LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
+    LL_EXTI_DisableEvent_64_95(EXTI_InitStruct->Line_64_95);
+
+#if defined(DUAL_CORE)
+    /* Disable IT on provided Lines for Cortex-M4*/
+    LL_C2_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
+    LL_C2_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
+    LL_C2_EXTI_DisableIT_64_95(EXTI_InitStruct->Line_64_95);
+
+    /* Disable event on provided Lines for Cortex-M4 */
+    LL_C2_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
+    LL_C2_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
+    LL_C2_EXTI_DisableEvent_64_95(EXTI_InitStruct->Line_64_95);
+#endif /* DUAL_CORE */
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_EXTI_InitTypeDef field to default value.
+  * @param  EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure.
+  * @retval None
+  */
+void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct)
+{
+  EXTI_InitStruct->Line_0_31      = LL_EXTI_LINE_NONE;
+  EXTI_InitStruct->Line_32_63     = LL_EXTI_LINE_NONE;
+  EXTI_InitStruct->Line_64_95     = LL_EXTI_LINE_NONE;
+  EXTI_InitStruct->LineCommand    = DISABLE;
+  EXTI_InitStruct->Mode           = LL_EXTI_MODE_IT;
+  EXTI_InitStruct->Trigger        = LL_EXTI_TRIGGER_FALLING;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (EXTI) */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_gpio.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_gpio.c
new file mode 100644
index 00000000..176e27f8
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_gpio.c
@@ -0,0 +1,307 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_gpio.c
+  * @author  MCD Application Team
+  * @brief   GPIO LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+  
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_ll_gpio.h"
+#include "stm32h7xx_ll_bus.h"
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK)
+
+/** @addtogroup GPIO_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup GPIO_LL_Private_Macros
+  * @{
+  */
+#define IS_LL_GPIO_PIN(__VALUE__)          (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
+
+#define IS_LL_GPIO_MODE(__VALUE__)         (((__VALUE__) == LL_GPIO_MODE_INPUT)     ||\
+                                            ((__VALUE__) == LL_GPIO_MODE_OUTPUT)    ||\
+                                            ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\
+                                            ((__VALUE__) == LL_GPIO_MODE_ANALOG))
+
+#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__)  (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL)  ||\
+                                            ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))
+
+#define IS_LL_GPIO_SPEED(__VALUE__)        (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW)       ||\
+                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM)    ||\
+                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH)      ||\
+                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH))
+
+#define IS_LL_GPIO_PULL(__VALUE__)         (((__VALUE__) == LL_GPIO_PULL_NO)   ||\
+                                            ((__VALUE__) == LL_GPIO_PULL_UP)   ||\
+                                            ((__VALUE__) == LL_GPIO_PULL_DOWN))
+
+#define IS_LL_GPIO_ALTERNATE(__VALUE__)    (((__VALUE__) == LL_GPIO_AF_0  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_1  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_2  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_3  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_4  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_5  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_6  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_7  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_8  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_9  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_10 )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_11 )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_12 )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_13 )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_14 )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_15 ))
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup GPIO_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup GPIO_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize GPIO registers (Registers restored to their default values).
+  * @param  GPIOx GPIO Port
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: GPIO registers are de-initialized
+  *          - ERROR:   Wrong GPIO Port
+  */
+ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+
+  /* Force and Release reset on clock of GPIOx Port */
+  if (GPIOx == GPIOA)
+  {
+    LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOA);
+    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOA);
+  }
+  else if (GPIOx == GPIOB)
+  {
+    LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOB);
+    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOB);
+  }
+  else if (GPIOx == GPIOC)
+  {
+    LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOC);
+    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOC);
+  }
+#if defined(GPIOD)
+  else if (GPIOx == GPIOD)
+  {
+    LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOD);
+    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOD);
+  }
+#endif /* GPIOD */
+#if defined(GPIOE)
+  else if (GPIOx == GPIOE)
+  {
+    LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOE);
+    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOE);
+  }
+#endif /* GPIOE */
+#if defined(GPIOF)
+  else if (GPIOx == GPIOF)
+  {
+    LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOF);
+    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOF);
+  }
+#endif /* GPIOF */
+#if defined(GPIOG)
+  else if (GPIOx == GPIOG)
+  {
+    LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOG);
+    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOG);
+  }
+#endif /* GPIOG */
+#if defined(GPIOH)
+  else if (GPIOx == GPIOH)
+  {
+    LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOH);
+    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOH);
+  }
+#endif /* GPIOH */
+#if defined(GPIOI)
+  else if (GPIOx == GPIOI)
+  {
+    LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOI);
+    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOI);
+  }
+#endif /* GPIOI */
+#if defined(GPIOJ)
+  else if (GPIOx == GPIOJ)
+  {
+    LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOJ);
+    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOJ);
+  }
+#endif /* GPIOJ */
+#if defined(GPIOK)
+  else if (GPIOx == GPIOK)
+  {
+    LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOK);
+    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOK);
+  }
+#endif /* GPIOK */
+  else
+  {
+    status = ERROR;
+  }
+
+  return (status);
+}
+
+/**
+  * @brief  Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
+  * @param  GPIOx GPIO Port
+  * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
+  *         that contains the configuration information for the specified GPIO peripheral.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
+  *          - ERROR:   Not applicable
+  */
+ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
+{
+  uint32_t pinpos, currentpin;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin));
+  assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode));
+  assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull));
+
+  /* ------------------------- Configure the port pins ---------------- */
+  /* Initialize  pinpos on first pin set */
+  pinpos = POSITION_VAL(GPIO_InitStruct->Pin);
+
+  /* Configure the port pins */
+  while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U)
+  {
+    /* Get current io position */
+    currentpin = (GPIO_InitStruct->Pin) & (0x00000001UL << pinpos);
+
+    if (currentpin != 0x00000000U)
+    {
+
+      if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
+      {
+        /* Check Speed mode parameters */
+        assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed));
+
+        /* Speed mode configuration */
+        LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
+
+        /* Check Output mode parameters */
+        assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
+
+        /* Output mode configuration*/
+        LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);
+
+      }
+
+      /* Pull-up Pull down resistor configuration*/
+      LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull);
+
+      if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)
+      {
+        /* Check Alternate parameter */
+        assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate));
+
+        /* Alternate function configuration */
+        if (currentpin < LL_GPIO_PIN_8)
+        {
+          LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate);
+        }
+        else
+        {
+          LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate);
+        }
+      }
+
+      /* Pin Mode configuration */
+      LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
+    }
+    pinpos++;
+  }
+
+  return (SUCCESS);
+}
+
+/**
+  * @brief Set each @ref LL_GPIO_InitTypeDef field to default value.
+  * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
+  *                          whose fields will be set to default values.
+  * @retval None
+  */
+
+void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct)
+{
+  /* Reset GPIO init structure parameters values */
+  GPIO_InitStruct->Pin        = LL_GPIO_PIN_ALL;
+  GPIO_InitStruct->Mode       = LL_GPIO_MODE_ANALOG;
+  GPIO_InitStruct->Speed      = LL_GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct->Pull       = LL_GPIO_PULL_NO;
+  GPIO_InitStruct->Alternate  = LL_GPIO_AF_0;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_rcc.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_rcc.c
new file mode 100644
index 00000000..699cd0ff
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_rcc.c
@@ -0,0 +1,1770 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_rcc.c
+  * @author  MCD Application Team
+  * @brief   RCC LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_ll_rcc.h"
+#include "stm32h7xx_ll_bus.h"
+#ifdef  USE_FULL_ASSERT
+  #include "stm32_assert.h"
+#else
+  #define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined(RCC)
+
+/** @addtogroup RCC_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+const uint8_t LL_RCC_PrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RCC_LL_Private_Macros
+  * @{
+  */
+#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_USART16_CLKSOURCE) \
+                                            || ((__VALUE__) == LL_RCC_USART234578_CLKSOURCE))
+
+
+#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_I2C123_CLKSOURCE) \
+                                            || ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE))
+
+#define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE)  \
+                                            || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE)  \
+                                            || ((__VALUE__) == LL_RCC_LPTIM345_CLKSOURCE))
+
+#if defined(LL_RCC_SAI4A_CLKSOURCE)
+#define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
+                                            || ((__VALUE__) == LL_RCC_SAI23_CLKSOURCE) \
+                                            || ((__VALUE__) == LL_RCC_SAI4A_CLKSOURCE) \
+                                            || ((__VALUE__) == LL_RCC_SAI4B_CLKSOURCE))
+#else
+#define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
+                                            || ((__VALUE__) == LL_RCC_SAI2A_CLKSOURCE) \
+                                            || ((__VALUE__) == LL_RCC_SAI2B_CLKSOURCE))
+#endif /* LL_RCC_SAI4A_CLKSOURCE */
+
+#define IS_LL_RCC_SPI_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_SPI123_CLKSOURCE) \
+                                            || ((__VALUE__) == LL_RCC_SPI45_CLKSOURCE) \
+                                            || ((__VALUE__) == LL_RCC_SPI6_CLKSOURCE))
+
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup RCC_LL_Private_Functions RCC Private functions
+  * @{
+  */
+uint32_t RCC_GetSystemClockFreq(void);
+uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
+uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
+uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
+uint32_t RCC_GetPCLK3ClockFreq(uint32_t HCLK_Frequency);
+uint32_t RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency);
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCC_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup RCC_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  Resets the RCC clock configuration to the default reset state.
+  * @note   The default reset state of the clock configuration is given below:
+  *            - HSI ON and used as system clock source
+  *            - HSE, PLL1, PLL2 and PLL3 OFF
+  *            - AHB, APB Bus pre-scaler set to 1.
+  *            - CSS, MCO1 and MCO2 OFF
+  *            - All interrupts disabled
+  * @note   This function doesn't modify the configuration of the
+  *            - Peripheral clocks
+  *            - LSI, LSE and RTC clocks
+  * @retval None
+  */
+void LL_RCC_DeInit(void)
+{
+  /* Set HSION bit */
+  SET_BIT(RCC->CR, RCC_CR_HSION);
+
+  /* Wait for HSI READY bit */
+  while(LL_RCC_HSI_IsReady() == 0U)
+  {}
+
+  /* Reset CFGR register */
+  CLEAR_REG(RCC->CFGR);
+
+  /* Reset CSION , CSIKERON, HSEON, HSI48ON, HSECSSON,HSIDIV, PLL1ON, PLL2ON, PLL3ON bits */
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSIKERON| RCC_CR_HSIDIV| RCC_CR_HSIDIVF| RCC_CR_CSION | RCC_CR_CSIKERON |  RCC_CR_HSI48ON  \
+  |RCC_CR_CSSHSEON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON);
+
+  /* Wait for PLL1 READY bit to be reset */
+  while(LL_RCC_PLL1_IsReady() != 0U)
+  {}
+
+  /* Wait for PLL2 READY bit to be reset */
+  while(LL_RCC_PLL2_IsReady() != 0U)
+  {}
+
+  /* Wait for PLL3 READY bit to be reset */
+  while(LL_RCC_PLL3_IsReady() != 0U)
+  {}
+
+#if defined(RCC_D1CFGR_HPRE)
+  /* Reset D1CFGR register */
+  CLEAR_REG(RCC->D1CFGR);
+
+  /* Reset D2CFGR register */
+  CLEAR_REG(RCC->D2CFGR);
+
+  /* Reset D3CFGR register */
+  CLEAR_REG(RCC->D3CFGR);
+#else
+  /* Reset CDCFGR1 register */
+  CLEAR_REG(RCC->CDCFGR1);
+
+  /* Reset CDCFGR2 register */
+  CLEAR_REG(RCC->CDCFGR2);
+
+  /* Reset SRDCFGR register */
+  CLEAR_REG(RCC->SRDCFGR);
+
+#endif /* RCC_D1CFGR_HPRE */
+
+  /* Reset PLLCKSELR register to default value */
+  RCC->PLLCKSELR= RCC_PLLCKSELR_DIVM1_5|RCC_PLLCKSELR_DIVM2_5|RCC_PLLCKSELR_DIVM3_5;
+
+  /* Reset PLLCFGR register to default value */
+  LL_RCC_WriteReg(PLLCFGR, 0x01FF0000U);
+
+  /* Reset PLL1DIVR register to default value */
+  LL_RCC_WriteReg(PLL1DIVR, 0x01010280U);
+
+  /* Reset PLL1FRACR register */
+  CLEAR_REG(RCC->PLL1FRACR);
+
+  /* Reset PLL2DIVR register to default value */
+  LL_RCC_WriteReg(PLL2DIVR, 0x01010280U);
+
+  /* Reset PLL2FRACR register */
+  CLEAR_REG(RCC->PLL2FRACR);
+
+  /* Reset PLL3DIVR register to default value */
+  LL_RCC_WriteReg(PLL3DIVR, 0x01010280U);
+
+  /* Reset PLL3FRACR register */
+  CLEAR_REG(RCC->PLL3FRACR);
+
+  /* Reset HSEBYP bit */
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
+
+  /* Disable all interrupts */
+  CLEAR_REG(RCC->CIER);
+
+  /* Clear all interrupts */
+  SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC | RCC_CICR_LSERDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC
+                   | RCC_CICR_CSIRDYC | RCC_CICR_HSI48RDYC | RCC_CICR_PLLRDYC | RCC_CICR_PLL2RDYC
+                   | RCC_CICR_PLL3RDYC | RCC_CICR_LSECSSC | RCC_CICR_HSECSSC);
+
+  /* Clear reset source flags */
+  SET_BIT(RCC->RSR, RCC_RSR_RMVF);
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup RCC_LL_EF_Get_Freq
+  * @brief  Return the frequencies of different on chip clocks;  System, AHB, APB1, APB2, APB3 and APB4 buses clocks.
+  *         and different peripheral clocks available on the device.
+  * @note   If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
+  * @note   If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
+  * @note   If SYSCLK source is CSI, function returns values based on CSI_VALUE(***)
+  * @note   If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
+  *         or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  * @note   (*) HSI_VALUE is a constant defined in header file (default value
+  *             64 MHz) divider by HSIDIV, but the real value may vary depending on
+  *             on the variations in voltage and temperature.
+  * @note   (**) HSE_VALUE is a constant defined in header file (default value
+  *              25 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  * @note   (***) CSI_VALUE is a constant defined in header file (default value
+  *               4 MHz) but the real value may vary depending on the variations
+  *               in voltage and temperature.
+  * @note   The result of this function could be incorrect when using fractional
+  *         value for HSE crystal.
+  * @note   This function can be used by the user application to compute the
+  *         baud-rate for the communication peripherals or configure other parameters.
+  * @{
+  */
+
+/**
+  * @brief  Return the frequencies of different on chip clocks;  System, AHB, APB1, APB2, APB3 and APB4 buses clocks.
+  * @note   Each time SYSCLK, HCLK, PCLK1, PCLK2, PCLK3 and/or PCLK4 clock changes, this function
+  *         must be called to update structure fields. Otherwise, any
+  *         configuration based on this function will be incorrect.
+  * @param  RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
+  * @retval None
+  */
+void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
+{
+  /* Get SYSCLK frequency */
+  RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
+
+  /* HCLK clock frequency */
+  RCC_Clocks->HCLK_Frequency   = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
+
+  /* PCLK1 clock frequency */
+  RCC_Clocks->PCLK1_Frequency  = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
+
+  /* PCLK2 clock frequency */
+  RCC_Clocks->PCLK2_Frequency  = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
+
+  /* PCLK3 clock frequency */
+  RCC_Clocks->PCLK3_Frequency  = RCC_GetPCLK3ClockFreq(RCC_Clocks->HCLK_Frequency);
+
+  /* PCLK4 clock frequency */
+  RCC_Clocks->PCLK4_Frequency  = RCC_GetPCLK4ClockFreq(RCC_Clocks->HCLK_Frequency);
+}
+
+/**
+  * @brief  Return PLL1 clocks frequencies
+  * @note   LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
+  * @retval None
+  */
+void LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks)
+{
+  uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO, pllsource;
+  uint32_t m, n, fracn = 0U;
+
+  /* PLL_VCO = (HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
+     SYSCLK = PLL_VCO / PLLP
+  */
+  pllsource = LL_RCC_PLL_GetSource();
+
+  switch (pllsource)
+  {
+    case LL_RCC_PLLSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
+      }
+      break;
+
+    case LL_RCC_PLLSOURCE_CSI:
+      if (LL_RCC_CSI_IsReady() != 0U)
+      {
+        pllinputfreq = CSI_VALUE;
+      }
+      break;
+
+    case LL_RCC_PLLSOURCE_HSE:
+      if (LL_RCC_HSE_IsReady() != 0U)
+      {
+        pllinputfreq = HSE_VALUE;
+      }
+      break;
+
+    case LL_RCC_PLLSOURCE_NONE:
+    default:
+      /* PLL clock disabled */
+      break;
+  }
+
+  PLL_Clocks->PLL_P_Frequency = 0U;
+  PLL_Clocks->PLL_Q_Frequency = 0U;
+  PLL_Clocks->PLL_R_Frequency = 0U;
+
+  m = LL_RCC_PLL1_GetM();
+  n = LL_RCC_PLL1_GetN();
+  if (LL_RCC_PLL1FRACN_IsEnabled() != 0U)
+  {
+    fracn = LL_RCC_PLL1_GetFRACN();
+  }
+
+  if (m != 0U)
+  {
+    if (LL_RCC_PLL1P_IsEnabled() != 0U)
+    {
+      PLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL1_GetP());
+    }
+
+    if (LL_RCC_PLL1Q_IsEnabled() != 0U)
+    {
+      PLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL1_GetQ());
+    }
+
+    if (LL_RCC_PLL1R_IsEnabled() != 0U)
+    {
+      PLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL1_GetR());
+    }
+  }
+}
+
+/**
+  * @brief  Return PLL2 clocks frequencies
+  * @note   LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
+  * @retval None
+  */
+void LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks)
+{
+  uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO, pllsource;
+  uint32_t m, n, fracn = 0U;
+
+  /* PLL_VCO = (HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
+     SYSCLK = PLL_VCO / PLLP
+  */
+  pllsource = LL_RCC_PLL_GetSource();
+
+  switch (pllsource)
+  {
+    case LL_RCC_PLLSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
+      }
+      break;
+
+    case LL_RCC_PLLSOURCE_CSI:
+      if (LL_RCC_CSI_IsReady() != 0U)
+      {
+        pllinputfreq = CSI_VALUE;
+      }
+      break;
+
+    case LL_RCC_PLLSOURCE_HSE:
+      if (LL_RCC_HSE_IsReady() != 0U)
+      {
+        pllinputfreq = HSE_VALUE;
+      }
+      break;
+
+    case LL_RCC_PLLSOURCE_NONE:
+    default:
+      /* PLL clock disabled */
+      break;
+  }
+
+  PLL_Clocks->PLL_P_Frequency = 0U;
+  PLL_Clocks->PLL_Q_Frequency = 0U;
+  PLL_Clocks->PLL_R_Frequency = 0U;
+
+  m = LL_RCC_PLL2_GetM();
+  n = LL_RCC_PLL2_GetN();
+  if (LL_RCC_PLL2FRACN_IsEnabled() != 0U)
+  {
+    fracn = LL_RCC_PLL2_GetFRACN();
+  }
+
+  if (m != 0U)
+  {
+    if (LL_RCC_PLL2P_IsEnabled() != 0U)
+    {
+      PLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL2_GetP());
+    }
+
+    if (LL_RCC_PLL2Q_IsEnabled() != 0U)
+    {
+      PLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL2_GetQ());
+    }
+
+    if (LL_RCC_PLL2R_IsEnabled() != 0U)
+    {
+      PLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL2_GetR());
+    }
+  }
+}
+
+/**
+  * @brief  Return PLL3 clocks frequencies
+  * @note   LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
+  * @retval None
+  */
+void LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks)
+{
+  uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO, pllsource;
+  uint32_t m, n, fracn = 0U;
+
+  /* PLL_VCO = (HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
+     SYSCLK = PLL_VCO / PLLP
+  */
+  pllsource = LL_RCC_PLL_GetSource();
+
+  switch (pllsource)
+  {
+    case LL_RCC_PLLSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
+      }
+      break;
+
+    case LL_RCC_PLLSOURCE_CSI:
+      if (LL_RCC_CSI_IsReady() != 0U)
+      {
+        pllinputfreq = CSI_VALUE;
+      }
+      break;
+
+    case LL_RCC_PLLSOURCE_HSE:
+      if (LL_RCC_HSE_IsReady() != 0U)
+      {
+        pllinputfreq = HSE_VALUE;
+      }
+      break;
+
+    case LL_RCC_PLLSOURCE_NONE:
+    default:
+      /* PLL clock disabled */
+      break;
+  }
+
+  PLL_Clocks->PLL_P_Frequency = 0U;
+  PLL_Clocks->PLL_Q_Frequency = 0U;
+  PLL_Clocks->PLL_R_Frequency = 0U;
+
+  m = LL_RCC_PLL3_GetM();
+  n = LL_RCC_PLL3_GetN();
+  if (LL_RCC_PLL3FRACN_IsEnabled() != 0U)
+  {
+    fracn = LL_RCC_PLL3_GetFRACN();
+  }
+
+  if ((m != 0U) && (pllinputfreq != 0U))
+  {
+    if (LL_RCC_PLL3P_IsEnabled() != 0U)
+    {
+      PLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL3_GetP());
+    }
+
+    if (LL_RCC_PLL3Q_IsEnabled() != 0U)
+    {
+      PLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL3_GetQ());
+    }
+
+    if (LL_RCC_PLL3R_IsEnabled() != 0U)
+    {
+      PLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL3_GetR());
+    }
+  }
+}
+
+/**
+  * @brief  Helper function to calculate the PLL frequency output
+  * @note ex: @ref LL_RCC_CalcPLLClockFreq (HSE_VALUE, @ref LL_RCC_PLL1_GetM (),
+  *             @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetFRACN (), @ref LL_RCC_PLL1_GetP ());
+  * @param  PLLInputFreq PLL Input frequency (based on HSE/(HSI/HSIDIV)/CSI)
+  * @param  M      Between 1 and 63
+  * @param  N      Between 4 and 512
+  * @param  FRACN  Between 0 and 0x1FFF
+  * @param  PQR    VCO output divider (P, Q or R)
+  *                Between 1 and 128, except for PLL1P Odd value not allowed
+  * @retval PLL1 clock frequency (in Hz)
+  */
+uint32_t LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t PQR)
+{
+  float_t freq;
+
+  freq = ((float_t)PLLInputFreq / (float_t)M) * ((float_t)N + ((float_t)FRACN/(float_t)0x2000));
+
+  freq = freq/(float_t)PQR;
+
+  return (uint32_t)freq;
+}
+
+/**
+  * @brief  Return USARTx clock frequency
+  * @param  USARTxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE
+  * @retval USART clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
+{
+  uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  LL_PLL_ClocksTypeDef PLL_Clocks;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
+
+  switch (LL_RCC_GetUSARTClockSource(USARTxSource))
+  {
+    case LL_RCC_USART16_CLKSOURCE_PCLK2:
+      usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+      break;
+
+    case LL_RCC_USART234578_CLKSOURCE_PCLK1:
+      usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+      break;
+
+    case LL_RCC_USART16_CLKSOURCE_PLL2Q:
+    case LL_RCC_USART234578_CLKSOURCE_PLL2Q:
+      if (LL_RCC_PLL2_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
+        usart_frequency = PLL_Clocks.PLL_Q_Frequency;
+      }
+      break;
+
+    case LL_RCC_USART16_CLKSOURCE_PLL3Q:
+    case LL_RCC_USART234578_CLKSOURCE_PLL3Q:
+      if (LL_RCC_PLL3_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
+        usart_frequency = PLL_Clocks.PLL_Q_Frequency;
+      }
+      break;
+
+    case LL_RCC_USART16_CLKSOURCE_HSI:
+    case LL_RCC_USART234578_CLKSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        usart_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
+      }
+      break;
+
+    case LL_RCC_USART16_CLKSOURCE_CSI:
+    case LL_RCC_USART234578_CLKSOURCE_CSI:
+      if (LL_RCC_CSI_IsReady() != 0U)
+      {
+        usart_frequency = CSI_VALUE;
+      }
+      break;
+
+    case LL_RCC_USART16_CLKSOURCE_LSE:
+    case LL_RCC_USART234578_CLKSOURCE_LSE:
+      if (LL_RCC_LSE_IsReady() != 0U)
+      {
+        usart_frequency = LSE_VALUE;
+      }
+      break;
+
+    default:
+      /* Kernel clock disabled */
+      break;
+  }
+
+  return usart_frequency;
+}
+
+/**
+  * @brief  Return LPUART clock frequency
+  * @param  LPUARTxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE
+  * @retval LPUART clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)
+{
+  uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  LL_PLL_ClocksTypeDef PLL_Clocks;
+
+  switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))
+  {
+    case LL_RCC_LPUART1_CLKSOURCE_PCLK4:
+      lpuart_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+      break;
+
+    case LL_RCC_LPUART1_CLKSOURCE_PLL2Q:
+      if (LL_RCC_PLL2_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
+        lpuart_frequency = PLL_Clocks.PLL_Q_Frequency;
+      }
+      break;
+
+    case LL_RCC_LPUART1_CLKSOURCE_PLL3Q:
+      if (LL_RCC_PLL3_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
+        lpuart_frequency = PLL_Clocks.PLL_Q_Frequency;
+      }
+      break;
+
+    case LL_RCC_LPUART1_CLKSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        lpuart_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
+      }
+      break;
+
+    case LL_RCC_LPUART1_CLKSOURCE_CSI:
+      if (LL_RCC_CSI_IsReady() != 0U)
+      {
+        lpuart_frequency = CSI_VALUE;
+      }
+      break;
+
+    case LL_RCC_LPUART1_CLKSOURCE_LSE:
+      if (LL_RCC_LSE_IsReady() != 0U)
+      {
+        lpuart_frequency = LSE_VALUE;
+      }
+      break;
+
+    default:
+      /* Kernel clock disabled */
+      break;
+  }
+
+  return lpuart_frequency;
+}
+
+/**
+  * @brief  Return I2Cx clock frequency
+  * @param  I2CxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE
+  * @retval I2C clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
+{
+  uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  LL_PLL_ClocksTypeDef PLL_Clocks;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
+
+  switch (LL_RCC_GetI2CClockSource(I2CxSource))
+  {
+    case LL_RCC_I2C123_CLKSOURCE_PCLK1:
+      i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+      break;
+
+    case LL_RCC_I2C4_CLKSOURCE_PCLK4:
+      i2c_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+      break;
+
+    case LL_RCC_I2C123_CLKSOURCE_PLL3R:
+    case LL_RCC_I2C4_CLKSOURCE_PLL3R:
+      if (LL_RCC_PLL3_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
+        i2c_frequency = PLL_Clocks.PLL_R_Frequency;
+      }
+      break;
+
+    case LL_RCC_I2C123_CLKSOURCE_HSI:
+    case LL_RCC_I2C4_CLKSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        i2c_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
+      }
+      break;
+
+    case LL_RCC_I2C123_CLKSOURCE_CSI:
+    case LL_RCC_I2C4_CLKSOURCE_CSI:
+      if (LL_RCC_CSI_IsReady() != 0U)
+      {
+        i2c_frequency = CSI_VALUE;
+      }
+      break;
+
+    default:
+      /* Nothing to do */
+      break;
+  }
+
+  return i2c_frequency;
+}
+
+/**
+  * @brief  Return LPTIMx clock frequency
+  * @param  LPTIMxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE
+  * @retval LPTIM clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
+{
+  uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  LL_PLL_ClocksTypeDef PLL_Clocks;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
+
+  switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
+  {
+    case LL_RCC_LPTIM1_CLKSOURCE_PCLK1:
+      lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+      break;
+
+    case LL_RCC_LPTIM2_CLKSOURCE_PCLK4:
+    case LL_RCC_LPTIM345_CLKSOURCE_PCLK4:
+      lptim_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+      break;
+
+    case LL_RCC_LPTIM1_CLKSOURCE_PLL2P:
+    case LL_RCC_LPTIM2_CLKSOURCE_PLL2P:
+    case LL_RCC_LPTIM345_CLKSOURCE_PLL2P:
+      if (LL_RCC_PLL2_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
+        lptim_frequency = PLL_Clocks.PLL_P_Frequency;
+      }
+      break;
+
+    case LL_RCC_LPTIM1_CLKSOURCE_PLL3R:
+    case LL_RCC_LPTIM2_CLKSOURCE_PLL3R:
+    case LL_RCC_LPTIM345_CLKSOURCE_PLL3R:
+      if (LL_RCC_PLL3_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
+        lptim_frequency = PLL_Clocks.PLL_R_Frequency;
+      }
+      break;
+
+    case LL_RCC_LPTIM1_CLKSOURCE_LSE:
+    case LL_RCC_LPTIM2_CLKSOURCE_LSE:
+    case LL_RCC_LPTIM345_CLKSOURCE_LSE:
+      if (LL_RCC_LSE_IsReady() != 0U)
+      {
+        lptim_frequency = LSE_VALUE;
+      }
+      break;
+
+    case LL_RCC_LPTIM1_CLKSOURCE_LSI:
+    case LL_RCC_LPTIM2_CLKSOURCE_LSI:
+    case LL_RCC_LPTIM345_CLKSOURCE_LSI:
+      if (LL_RCC_LSI_IsReady() != 0U)
+      {
+        lptim_frequency = LSI_VALUE;
+      }
+      break;
+
+    case LL_RCC_LPTIM1_CLKSOURCE_CLKP:
+    case LL_RCC_LPTIM2_CLKSOURCE_CLKP:
+    case LL_RCC_LPTIM345_CLKSOURCE_CLKP:
+      lptim_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    default:
+      /* Kernel clock disabled */
+      break;
+  }
+
+  return lptim_frequency;
+}
+
+/**
+  * @brief  Return SAIx clock frequency
+  * @param  SAIxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE (*)
+  * @retval SAI clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  *
+  * (*) : Available on some STM32H7 lines only.
+  */
+uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
+{
+  uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  LL_PLL_ClocksTypeDef PLL_Clocks;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
+
+  switch (LL_RCC_GetSAIClockSource(SAIxSource))
+  {
+    case LL_RCC_SAI1_CLKSOURCE_PLL1Q:
+#if defined(SAI3)
+    case LL_RCC_SAI23_CLKSOURCE_PLL1Q:
+#endif /* SAI3 */
+#if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
+    case LL_RCC_SAI2A_CLKSOURCE_PLL1Q:
+    case LL_RCC_SAI2B_CLKSOURCE_PLL1Q:
+#endif /* (RCC_CDCCIP1R_SAI2ASEL) || (RCC_CDCCIP1R_SAI2BSEL) */
+#if defined(SAI4_Block_A) || defined(SAI4_Block_B)
+    case LL_RCC_SAI4A_CLKSOURCE_PLL1Q:
+    case LL_RCC_SAI4B_CLKSOURCE_PLL1Q:
+#endif /* (SAI4_Block_A) || (SAI4_Block_B) */
+      if (LL_RCC_PLL1_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
+        sai_frequency = PLL_Clocks.PLL_Q_Frequency;
+      }
+      break;
+
+    case LL_RCC_SAI1_CLKSOURCE_PLL2P:
+#if defined(SAI3)
+    case LL_RCC_SAI23_CLKSOURCE_PLL2P:
+#endif /* SAI3 */
+#if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
+    case LL_RCC_SAI2A_CLKSOURCE_PLL2P:
+    case LL_RCC_SAI2B_CLKSOURCE_PLL2P:
+#endif /* (RCC_CDCCIP1R_SAI2ASEL) || (RCC_CDCCIP1R_SAI2BSEL) */
+#if defined(SAI4_Block_A) || defined(SAI4_Block_B)
+    case LL_RCC_SAI4A_CLKSOURCE_PLL2P:
+    case LL_RCC_SAI4B_CLKSOURCE_PLL2P:
+#endif /* (SAI2_Block_A_BASE) || (SAI2_Block_B_BASE) */
+      if (LL_RCC_PLL2_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
+        sai_frequency = PLL_Clocks.PLL_P_Frequency;
+      }
+      break;
+
+    case LL_RCC_SAI1_CLKSOURCE_PLL3P:
+#if defined(SAI3)
+    case LL_RCC_SAI23_CLKSOURCE_PLL3P:
+#endif /* SAI3 */
+#if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
+    case LL_RCC_SAI2A_CLKSOURCE_PLL3P:
+    case LL_RCC_SAI2B_CLKSOURCE_PLL3P:
+#endif /* (RCC_CDCCIP1R_SAI2ASEL) || (RCC_CDCCIP1R_SAI2BSEL) */
+#if defined(SAI4_Block_A) || defined(SAI4_Block_B)
+    case LL_RCC_SAI4A_CLKSOURCE_PLL3P:
+    case LL_RCC_SAI4B_CLKSOURCE_PLL3P:
+#endif /* (SAI2_Block_A_BASE) || (SAI2_Block_B_BASE) */
+      if (LL_RCC_PLL3_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
+        sai_frequency = PLL_Clocks.PLL_P_Frequency;
+      }
+      break;
+
+    case LL_RCC_SAI1_CLKSOURCE_I2S_CKIN:
+#if defined(SAI3)
+    case LL_RCC_SAI23_CLKSOURCE_I2S_CKIN:
+#endif /* SAI3 */
+#if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
+    case LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN:
+    case LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN:
+#endif /* (RCC_CDCCIP1R_SAI2ASEL) || (RCC_CDCCIP1R_SAI2BSEL) */
+#if defined(SAI4_Block_A) || defined(SAI4_Block_B)
+    case LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN:
+    case LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN:
+#endif /* (SAI2_Block_A_BASE) || (SAI2_Block_B_BASE) */
+      sai_frequency = EXTERNAL_CLOCK_VALUE;
+      break;
+
+    case LL_RCC_SAI1_CLKSOURCE_CLKP:
+#if defined(SAI3)
+    case LL_RCC_SAI23_CLKSOURCE_CLKP:
+#endif /* SAI3 */
+#if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
+    case LL_RCC_SAI2A_CLKSOURCE_CLKP:
+    case LL_RCC_SAI2B_CLKSOURCE_CLKP:
+#endif /* (RCC_CDCCIP1R_SAI2ASEL) || (RCC_CDCCIP1R_SAI2BSEL) */
+#if defined(SAI4_Block_A) || defined(SAI4_Block_B)
+    case LL_RCC_SAI4A_CLKSOURCE_CLKP:
+    case LL_RCC_SAI4B_CLKSOURCE_CLKP:
+#endif /* (SAI2_Block_A_BASE) || (SAI2_Block_B_BASE) */
+      sai_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    default:
+      /* Kernel clock disabled */
+      break;
+  }
+
+  return sai_frequency;
+}
+
+/**
+  * @brief  Return ADC clock frequency
+  * @param  ADCxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE
+  * @retval ADC clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
+{
+  uint32_t adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  LL_PLL_ClocksTypeDef PLL_Clocks;
+
+  switch (LL_RCC_GetADCClockSource(ADCxSource))
+  {
+    case LL_RCC_ADC_CLKSOURCE_PLL2P:
+      if (LL_RCC_PLL2_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
+        adc_frequency = PLL_Clocks.PLL_P_Frequency;
+      }
+      break;
+
+    case LL_RCC_ADC_CLKSOURCE_PLL3R:
+      if (LL_RCC_PLL3_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
+        adc_frequency = PLL_Clocks.PLL_R_Frequency;
+      }
+      break;
+
+    case LL_RCC_ADC_CLKSOURCE_CLKP:
+      adc_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    default:
+      /* Kernel clock disabled */
+      break;
+  }
+
+  return adc_frequency;
+}
+
+/**
+  * @brief  Return SDMMC clock frequency
+  * @param  SDMMCxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SDMMC_CLKSOURCE
+  * @retval SDMMC clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)
+{
+  uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  LL_PLL_ClocksTypeDef PLL_Clocks;
+
+  switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))
+  {
+    case LL_RCC_SDMMC_CLKSOURCE_PLL1Q:
+      if (LL_RCC_PLL1_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
+        sdmmc_frequency = PLL_Clocks.PLL_Q_Frequency;
+      }
+      break;
+
+    case LL_RCC_SDMMC_CLKSOURCE_PLL2R:
+      if (LL_RCC_PLL2_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
+        sdmmc_frequency = PLL_Clocks.PLL_R_Frequency;
+      }
+      break;
+
+    default:
+      /* Nothing to do */
+      break;
+  }
+
+  return sdmmc_frequency;
+}
+
+/**
+  * @brief  Return RNG clock frequency
+  * @param  RNGxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE
+  * @retval RNG clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
+{
+  uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  LL_PLL_ClocksTypeDef PLL_Clocks;
+
+  switch (LL_RCC_GetRNGClockSource(RNGxSource))
+  {
+    case LL_RCC_RNG_CLKSOURCE_PLL1Q:
+      if (LL_RCC_PLL1_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
+        rng_frequency = PLL_Clocks.PLL_Q_Frequency;
+      }
+      break;
+
+    case LL_RCC_RNG_CLKSOURCE_HSI48:
+      if (LL_RCC_HSI48_IsReady() != 0U)
+      {
+        rng_frequency = 48000000U;
+      }
+      break;
+
+    case LL_RCC_RNG_CLKSOURCE_LSE:
+      if (LL_RCC_LSE_IsReady() != 0U)
+      {
+        rng_frequency = LSE_VALUE;
+      }
+      break;
+
+    case LL_RCC_RNG_CLKSOURCE_LSI:
+      if (LL_RCC_LSI_IsReady() != 0U)
+      {
+        rng_frequency = LSI_VALUE;
+      }
+      break;
+
+    default:
+      /* Nothing to do */
+      break;
+  }
+
+  return rng_frequency;
+}
+
+/**
+  * @brief  Return CEC clock frequency
+  * @param  CECxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE
+  * @retval CEC clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource)
+{
+  uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  switch (LL_RCC_GetCECClockSource(CECxSource))
+  {
+    case LL_RCC_CEC_CLKSOURCE_LSE:
+      if (LL_RCC_LSE_IsReady() != 0U)
+      {
+        cec_frequency = LSE_VALUE;
+      }
+      break;
+
+    case LL_RCC_CEC_CLKSOURCE_LSI:
+      if (LL_RCC_LSI_IsReady() != 0U)
+      {
+        cec_frequency = LSI_VALUE;
+      }
+      break;
+
+    case LL_RCC_CEC_CLKSOURCE_CSI_DIV122:
+      if (LL_RCC_CSI_IsReady() != 0U)
+      {
+        cec_frequency = CSI_VALUE / 122U;
+      }
+      break;
+
+    default:
+      /* Kernel clock disabled */
+      break;
+  }
+
+  return cec_frequency;
+}
+
+/**
+  * @brief  Return USB clock frequency
+  * @param  USBxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USB_CLKSOURCE
+  * @retval USB clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready or Disabled
+  */
+uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
+{
+  uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  LL_PLL_ClocksTypeDef PLL_Clocks;
+
+  switch (LL_RCC_GetUSBClockSource(USBxSource))
+  {
+    case LL_RCC_USB_CLKSOURCE_PLL1Q:
+      if (LL_RCC_PLL1_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
+        usb_frequency = PLL_Clocks.PLL_Q_Frequency;
+      }
+      break;
+
+    case LL_RCC_USB_CLKSOURCE_PLL3Q:
+      if (LL_RCC_PLL3_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
+        usb_frequency = PLL_Clocks.PLL_Q_Frequency;
+      }
+      break;
+
+    case LL_RCC_USB_CLKSOURCE_HSI48:
+      if (LL_RCC_HSI48_IsReady() != 0U)
+      {
+        usb_frequency = HSI48_VALUE;
+      }
+      break;
+
+    case LL_RCC_USB_CLKSOURCE_DISABLE:
+    default:
+      /* Nothing to do */
+      break;
+  }
+
+  return usb_frequency;
+}
+
+/**
+  * @brief  Return DFSDM clock frequency
+  * @param  DFSDMxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE
+  * @retval DFSDM clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)
+{
+  uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource))
+  {
+    case LL_RCC_DFSDM1_CLKSOURCE_SYSCLK:
+      dfsdm_frequency = RCC_GetSystemClockFreq();
+      break;
+
+    case LL_RCC_DFSDM1_CLKSOURCE_PCLK2:
+      dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+      break;
+
+    default:
+      /* Nothing to do */
+      break;
+  }
+
+  return dfsdm_frequency;
+}
+
+#if defined(DFSDM2_BASE)
+/**
+  * @brief  Return DFSDM clock frequency
+  * @param  DFSDMxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE
+  * @retval DFSDM clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetDFSDM2ClockFreq(uint32_t DFSDMxSource)
+{
+  uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+
+  switch (LL_RCC_GetDFSDM2ClockSource(DFSDMxSource))
+  {
+
+    case LL_RCC_DFSDM2_CLKSOURCE_SYSCLK:
+      dfsdm_frequency = RCC_GetSystemClockFreq();
+      break;
+
+    case LL_RCC_DFSDM2_CLKSOURCE_PCLK4:
+      dfsdm_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+      break;
+
+    default:
+      /* Nothing to do */
+      break;
+  }
+
+  return dfsdm_frequency;
+}
+#endif /* DFSDM2_BASE */
+
+#if defined(DSI)
+/**
+  * @brief  Return DSI clock frequency
+  * @param  DSIxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DSI_CLKSOURCE
+  * @retval DSI clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used
+  */
+uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource)
+{
+  uint32_t dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  LL_PLL_ClocksTypeDef PLL_Clocks;
+
+  switch (LL_RCC_GetDSIClockSource(DSIxSource))
+  {
+    case LL_RCC_DSI_CLKSOURCE_PLL2Q:
+      if (LL_RCC_PLL2_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
+        dsi_frequency = PLL_Clocks.PLL_Q_Frequency;
+      }
+      break;
+
+    case LL_RCC_DSI_CLKSOURCE_PHY:
+      dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
+      break;
+
+    default:
+      /* Nothing to do */
+      break;
+  }
+
+  return dsi_frequency;
+}
+#endif /* DSI */
+
+/**
+  * @brief  Return SPDIF clock frequency
+  * @param  SPDIFxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE
+  * @retval SPDIF clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetSPDIFClockFreq(uint32_t SPDIFxSource)
+{
+  uint32_t spdif_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  LL_PLL_ClocksTypeDef PLL_Clocks;
+
+  switch (LL_RCC_GetSPDIFClockSource(SPDIFxSource))
+  {
+    case LL_RCC_SPDIF_CLKSOURCE_PLL1Q:
+      if (LL_RCC_PLL1_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
+        spdif_frequency = PLL_Clocks.PLL_Q_Frequency;
+      }
+      break;
+
+    case LL_RCC_SPDIF_CLKSOURCE_PLL2R:
+      if (LL_RCC_PLL2_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
+        spdif_frequency = PLL_Clocks.PLL_R_Frequency;
+      }
+      break;
+
+    case LL_RCC_SPDIF_CLKSOURCE_PLL3R:
+      if (LL_RCC_PLL3_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
+        spdif_frequency = PLL_Clocks.PLL_R_Frequency;
+      }
+      break;
+
+    case LL_RCC_SPDIF_CLKSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        spdif_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
+      }
+      break;
+
+    default:
+      /* Nothing to do */
+      break;
+  }
+
+  return spdif_frequency;
+}
+
+/**
+  * @brief  Return SPIx clock frequency
+  * @param  SPIxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE
+  * @retval SPI clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource)
+{
+  uint32_t spi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  LL_PLL_ClocksTypeDef PLL_Clocks;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_SPI_CLKSOURCE(SPIxSource));
+
+  switch (LL_RCC_GetSPIClockSource(SPIxSource))
+  {
+    case LL_RCC_SPI123_CLKSOURCE_PLL1Q:
+      if (LL_RCC_PLL1_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
+        spi_frequency = PLL_Clocks.PLL_Q_Frequency;
+      }
+      break;
+
+    case LL_RCC_SPI123_CLKSOURCE_PLL2P:
+      if (LL_RCC_PLL2_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
+        spi_frequency = PLL_Clocks.PLL_P_Frequency;
+      }
+      break;
+
+    case LL_RCC_SPI123_CLKSOURCE_PLL3P:
+      if (LL_RCC_PLL3_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
+        spi_frequency = PLL_Clocks.PLL_P_Frequency;
+      }
+      break;
+
+    case LL_RCC_SPI123_CLKSOURCE_I2S_CKIN:
+#if defined(LL_RCC_SPI6_CLKSOURCE_I2S_CKIN)
+    case LL_RCC_SPI6_CLKSOURCE_I2S_CKIN:
+#endif /* LL_RCC_SPI6_CLKSOURCE_I2S_CKIN */
+      spi_frequency = EXTERNAL_CLOCK_VALUE;
+      break;
+
+    case LL_RCC_SPI123_CLKSOURCE_CLKP:
+      spi_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case LL_RCC_SPI45_CLKSOURCE_PCLK2:
+      spi_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+      break;
+
+    case LL_RCC_SPI6_CLKSOURCE_PCLK4:
+      spi_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+      break;
+
+    case LL_RCC_SPI45_CLKSOURCE_PLL2Q:
+    case LL_RCC_SPI6_CLKSOURCE_PLL2Q:
+      if (LL_RCC_PLL2_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
+        spi_frequency = PLL_Clocks.PLL_Q_Frequency;
+      }
+      break;
+
+    case LL_RCC_SPI45_CLKSOURCE_PLL3Q:
+    case LL_RCC_SPI6_CLKSOURCE_PLL3Q:
+      if (LL_RCC_PLL3_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
+        spi_frequency = PLL_Clocks.PLL_Q_Frequency;
+      }
+      break;
+
+    case LL_RCC_SPI45_CLKSOURCE_HSI:
+    case LL_RCC_SPI6_CLKSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        spi_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
+      }
+      break;
+
+    case LL_RCC_SPI45_CLKSOURCE_CSI:
+    case LL_RCC_SPI6_CLKSOURCE_CSI:
+      if (LL_RCC_CSI_IsReady() != 0U)
+      {
+        spi_frequency = CSI_VALUE;
+      }
+      break;
+
+    case LL_RCC_SPI45_CLKSOURCE_HSE:
+    case LL_RCC_SPI6_CLKSOURCE_HSE:
+      if (LL_RCC_HSE_IsReady() != 0U)
+      {
+        spi_frequency = HSE_VALUE;
+      }
+      break;
+
+    default:
+      /* Kernel clock disabled */
+      break;
+  }
+
+  return spi_frequency;
+}
+
+/**
+  * @brief  Return SWP clock frequency
+  * @param  SWPxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SWP_CLKSOURCE
+  * @retval SWP clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetSWPClockFreq(uint32_t SWPxSource)
+{
+  uint32_t swp_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  switch (LL_RCC_GetSWPClockSource(SWPxSource))
+  {
+    case LL_RCC_SWP_CLKSOURCE_PCLK1:
+      swp_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+      break;
+
+    case LL_RCC_SWP_CLKSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        swp_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
+      }
+      break;
+
+    default:
+      /* Nothing to do */
+      break;
+  }
+
+  return swp_frequency;
+}
+
+/**
+  * @brief  Return FDCAN clock frequency
+  * @param  FDCANxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE
+  * @retval FDCAN clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource)
+{
+  uint32_t fdcan_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  LL_PLL_ClocksTypeDef PLL_Clocks;
+
+  switch (LL_RCC_GetFDCANClockSource(FDCANxSource))
+  {
+    case LL_RCC_FDCAN_CLKSOURCE_HSE:
+      if (LL_RCC_HSE_IsReady() != 0U)
+      {
+        fdcan_frequency = HSE_VALUE;
+      }
+      break;
+
+    case LL_RCC_FDCAN_CLKSOURCE_PLL1Q:
+      if (LL_RCC_PLL1_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
+        fdcan_frequency = PLL_Clocks.PLL_Q_Frequency;
+      }
+      break;
+
+    case LL_RCC_FDCAN_CLKSOURCE_PLL2Q:
+      if (LL_RCC_PLL2_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
+        fdcan_frequency = PLL_Clocks.PLL_Q_Frequency;
+      }
+      break;
+
+    default:
+      /* Kernel clock disabled */
+      break;
+  }
+
+  return fdcan_frequency;
+}
+
+/**
+  * @brief  Return FMC clock frequency
+  * @param  FMCxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_FMC_CLKSOURCE
+  * @retval FMC clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetFMCClockFreq(uint32_t FMCxSource)
+{
+  uint32_t fmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  LL_PLL_ClocksTypeDef PLL_Clocks;
+
+  switch (LL_RCC_GetFMCClockSource(FMCxSource))
+  {
+    case LL_RCC_FMC_CLKSOURCE_HCLK:
+      fmc_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler()));
+      break;
+
+    case LL_RCC_FMC_CLKSOURCE_PLL1Q:
+      if (LL_RCC_PLL1_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
+        fmc_frequency = PLL_Clocks.PLL_Q_Frequency;
+      }
+      break;
+
+    case LL_RCC_FMC_CLKSOURCE_PLL2R:
+      if (LL_RCC_PLL2_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
+        fmc_frequency = PLL_Clocks.PLL_R_Frequency;
+      }
+      break;
+
+    case LL_RCC_FMC_CLKSOURCE_CLKP:
+      fmc_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    default:
+      /* Nothing to do */
+      break;
+  }
+
+  return fmc_frequency;
+}
+
+#if defined(QUADSPI)
+/**
+  * @brief  Return QSPI clock frequency
+  * @param  QSPIxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_QSPI_CLKSOURCE
+  * @retval QSPI clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetQSPIClockFreq(uint32_t QSPIxSource)
+{
+  uint32_t qspi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  LL_PLL_ClocksTypeDef PLL_Clocks;
+
+  switch (LL_RCC_GetQSPIClockSource(QSPIxSource))
+  {
+    case LL_RCC_QSPI_CLKSOURCE_HCLK:
+      qspi_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler()));
+      break;
+
+    case LL_RCC_QSPI_CLKSOURCE_PLL1Q:
+      if (LL_RCC_PLL1_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
+        qspi_frequency = PLL_Clocks.PLL_Q_Frequency;
+      }
+      break;
+
+    case LL_RCC_QSPI_CLKSOURCE_PLL2R:
+      if (LL_RCC_PLL2_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
+        qspi_frequency = PLL_Clocks.PLL_R_Frequency;
+      }
+      break;
+
+    case LL_RCC_QSPI_CLKSOURCE_CLKP:
+      qspi_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    default:
+      /* Nothing to do */
+      break;
+  }
+
+  return qspi_frequency;
+}
+#endif /* QUADSPI */
+
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+/**
+  * @brief  Return OSPI clock frequency
+  * @param  QSPIxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_OSPI_CLKSOURCE
+  * @retval OSPI clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+
+uint32_t LL_RCC_GetOSPIClockFreq(uint32_t OSPIxSource)
+{
+  uint32_t ospi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  LL_PLL_ClocksTypeDef PLL_Clocks;
+
+  switch (LL_RCC_GetOSPIClockSource(OSPIxSource))
+  {
+    case LL_RCC_OSPI_CLKSOURCE_HCLK:
+      ospi_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler()));
+      break;
+
+    case LL_RCC_OSPI_CLKSOURCE_PLL1Q:
+      if (LL_RCC_PLL1_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
+        ospi_frequency = PLL_Clocks.PLL_Q_Frequency;
+      }
+      break;
+
+    case LL_RCC_OSPI_CLKSOURCE_PLL2R:
+      if (LL_RCC_PLL2_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
+        ospi_frequency = PLL_Clocks.PLL_R_Frequency;
+      }
+      break;
+
+    case LL_RCC_OSPI_CLKSOURCE_CLKP:
+      ospi_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    default:
+      /* Nothing to do */
+      break;
+  }
+
+  return ospi_frequency;
+}
+#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
+
+/**
+  * @brief  Return CLKP clock frequency
+  * @param  CLKPxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE
+  * @retval CLKP clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource)
+{
+  uint32_t clkp_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  switch (LL_RCC_GetCLKPClockSource(CLKPxSource))
+  {
+    case LL_RCC_CLKP_CLKSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        clkp_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
+      }
+      break;
+
+    case LL_RCC_CLKP_CLKSOURCE_CSI:
+      if (LL_RCC_CSI_IsReady() != 0U)
+      {
+        clkp_frequency = CSI_VALUE;
+      }
+      break;
+
+    case LL_RCC_CLKP_CLKSOURCE_HSE:
+      if (LL_RCC_HSE_IsReady() != 0U)
+      {
+        clkp_frequency = HSE_VALUE;
+      }
+      break;
+
+    default:
+      /* CLKP clock disabled */
+      break;
+  }
+
+  return clkp_frequency;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup RCC_LL_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Return SYSTEM clock frequency
+  * @retval SYSTEM clock frequency (in Hz)
+  */
+uint32_t RCC_GetSystemClockFreq(void)
+{
+  uint32_t frequency = 0U;
+  LL_PLL_ClocksTypeDef PLL_Clocks;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (LL_RCC_GetSysClkSource())
+  {
+    /* No check on Ready: Won't be selected by hardware if not */
+    case LL_RCC_SYS_CLKSOURCE_STATUS_HSI:
+      frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
+      break;
+
+    case LL_RCC_SYS_CLKSOURCE_STATUS_CSI:
+      frequency = CSI_VALUE;
+      break;
+
+    case LL_RCC_SYS_CLKSOURCE_STATUS_HSE:
+      frequency = HSE_VALUE;
+      break;
+
+    case LL_RCC_SYS_CLKSOURCE_STATUS_PLL1:
+      LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
+      frequency = PLL_Clocks.PLL_P_Frequency;
+      break;
+
+    default:
+      /* Nothing to do */
+      break;
+  }
+
+  return frequency;
+}
+
+/**
+  * @brief  Return HCLK clock frequency
+  * @param  SYSCLK_Frequency SYSCLK clock frequency
+  * @retval HCLK clock frequency (in Hz)
+  */
+uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
+{
+  /* HCLK clock frequency */
+  return LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
+}
+
+/**
+  * @brief  Return PCLK1 clock frequency
+  * @param  HCLK_Frequency HCLK clock frequency
+  * @retval PCLK1 clock frequency (in Hz)
+  */
+uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
+{
+  /* PCLK1 clock frequency */
+  return LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
+}
+
+/**
+  * @brief  Return PCLK2 clock frequency
+  * @param  HCLK_Frequency HCLK clock frequency
+  * @retval PCLK2 clock frequency (in Hz)
+  */
+uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
+{
+  /* PCLK2 clock frequency */
+  return LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
+}
+
+/**
+  * @brief  Return PCLK3 clock frequency
+  * @param  HCLK_Frequency HCLK clock frequency
+  * @retval PCLK3 clock frequency (in Hz)
+  */
+uint32_t RCC_GetPCLK3ClockFreq(uint32_t HCLK_Frequency)
+{
+  /* PCLK3 clock frequency */
+  return LL_RCC_CALC_PCLK3_FREQ(HCLK_Frequency, LL_RCC_GetAPB3Prescaler());
+}
+
+/**
+  * @brief  Return PCLK4 clock frequency
+  * @param  HCLK_Frequency HCLK clock frequency
+  * @retval PCLK4 clock frequency (in Hz)
+  */
+uint32_t RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency)
+{
+  /* PCLK4 clock frequency */
+  return LL_RCC_CALC_PCLK4_FREQ(HCLK_Frequency, LL_RCC_GetAPB4Prescaler());
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(RCC) */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usart.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usart.c
new file mode 100644
index 00000000..9419620a
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usart.c
@@ -0,0 +1,496 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_usart.c
+  * @author  MCD Application Team
+  * @brief   USART LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_ll_usart.h"
+#include "stm32h7xx_ll_rcc.h"
+#include "stm32h7xx_ll_bus.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5) || defined (UART7) || defined (UART8) || defined (UART9) || defined (USART10)
+
+/** @addtogroup USART_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup USART_LL_Private_Macros
+  * @{
+  */
+
+#define IS_LL_USART_PRESCALER(__VALUE__)  (((__VALUE__) == LL_USART_PRESCALER_DIV1) \
+                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV2) \
+                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV4) \
+                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV6) \
+                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV8) \
+                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV10) \
+                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV12) \
+                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV16) \
+                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV32) \
+                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV64) \
+                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV128) \
+                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV256))
+
+/* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
+ *              divided by the smallest oversampling used on the USART (i.e. 8)    */
+#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 12500000U)
+
+/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
+#define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
+
+/* __VALUE__ BRR content must be lower than or equal to 0xFFFF. */
+#define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
+
+#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
+                                          || ((__VALUE__) == LL_USART_DIRECTION_RX) \
+                                          || ((__VALUE__) == LL_USART_DIRECTION_TX) \
+                                          || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
+
+#define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
+                                       || ((__VALUE__) == LL_USART_PARITY_EVEN) \
+                                       || ((__VALUE__) == LL_USART_PARITY_ODD))
+
+#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \
+                                          || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
+                                          || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
+
+#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
+                                             || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
+
+#define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
+                                                 || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
+
+#define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
+                                           || ((__VALUE__) == LL_USART_PHASE_2EDGE))
+
+#define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
+                                              || ((__VALUE__) == LL_USART_POLARITY_HIGH))
+
+#define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
+                                            || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
+
+#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
+                                         || ((__VALUE__) == LL_USART_STOPBITS_1) \
+                                         || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
+                                         || ((__VALUE__) == LL_USART_STOPBITS_2))
+
+#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
+                                          || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
+                                          || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
+                                          || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
+
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup USART_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup USART_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize USART registers (Registers restored to their default values).
+  * @param  USARTx USART Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: USART registers are de-initialized
+  *          - ERROR: USART registers are not de-initialized
+  */
+ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_UART_INSTANCE(USARTx));
+
+  if (USARTx == USART1)
+  {
+    /* Force reset of USART clock */
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
+
+    /* Release reset of USART clock */
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
+  }
+  else if (USARTx == USART2)
+  {
+    /* Force reset of USART clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
+
+    /* Release reset of USART clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
+  }
+  else if (USARTx == USART3)
+  {
+    /* Force reset of USART clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);
+
+    /* Release reset of USART clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
+  }
+  else if (USARTx == UART4)
+  {
+    /* Force reset of UART clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4);
+
+    /* Release reset of UART clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4);
+  }
+  else if (USARTx == UART5)
+  {
+    /* Force reset of UART clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5);
+
+    /* Release reset of UART clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5);
+  }
+  else if (USARTx == USART6)
+  {
+    /* Force reset of USART clock */
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART6);
+
+    /* Release reset of USART clock */
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART6);
+  }
+  else if (USARTx == UART7)
+  {
+    /* Force reset of UART clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART7);
+
+    /* Release reset of UART clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART7);
+  }
+  else if (USARTx == UART8)
+  {
+    /* Force reset of UART clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART8);
+
+    /* Release reset of UART clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART8);
+  }
+#if defined(UART9)
+  else if (USARTx == UART9)
+  {
+    /* Force reset of UART clock */
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_UART9);
+
+    /* Release reset of UART clock */
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_UART9);
+  }
+#endif /* UART9 */
+#if defined(USART10)
+  else if (USARTx == USART10)
+  {
+    /* Force reset of USART clock */
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART10);
+
+    /* Release reset of USART clock */
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART10);
+  }
+#endif /* USART10 */
+  else
+  {
+    status = ERROR;
+  }
+
+  return (status);
+}
+
+/**
+  * @brief  Initialize USART registers according to the specified
+  *         parameters in USART_InitStruct.
+  * @note   As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
+  *         USART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+  * @note   Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
+  * @param  USARTx USART Instance
+  * @param  USART_InitStruct pointer to a LL_USART_InitTypeDef structure
+  *         that contains the configuration information for the specified USART peripheral.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: USART registers are initialized according to USART_InitStruct content
+  *          - ERROR: Problem occurred during USART Registers initialization
+  */
+ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
+{
+  ErrorStatus status = ERROR;
+  uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  /* Check the parameters */
+  assert_param(IS_UART_INSTANCE(USARTx));
+  assert_param(IS_LL_USART_PRESCALER(USART_InitStruct->PrescalerValue));
+  assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
+  assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
+  assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
+  assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
+  assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
+  assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
+  assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
+
+  /* USART needs to be in disabled state, in order to be able to configure some bits in
+     CRx registers */
+  if (LL_USART_IsEnabled(USARTx) == 0U)
+  {
+    /*---------------------------- USART CR1 Configuration ---------------------
+     * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
+     * - DataWidth:          USART_CR1_M bits according to USART_InitStruct->DataWidth value
+     * - Parity:             USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
+     * - TransferDirection:  USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
+     * - Oversampling:       USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
+     */
+    MODIFY_REG(USARTx->CR1,
+               (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
+                USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
+               (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
+                USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
+
+    /*---------------------------- USART CR2 Configuration ---------------------
+     * Configure USARTx CR2 (Stop bits) with parameters:
+     * - Stop Bits:          USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
+     * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
+     */
+    LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
+
+    /*---------------------------- USART CR3 Configuration ---------------------
+     * Configure USARTx CR3 (Hardware Flow Control) with parameters:
+     * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value.
+     */
+    LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
+
+    /*---------------------------- USART BRR Configuration ---------------------
+     * Retrieve Clock frequency used for USART Peripheral
+     */
+    if (USARTx == USART1)
+    {
+      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART16_CLKSOURCE);
+    }
+    else if (USARTx == USART2)
+    {
+      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART234578_CLKSOURCE);
+    }
+    else if (USARTx == USART3)
+    {
+      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART234578_CLKSOURCE);
+    }
+    else if (USARTx == UART4)
+    {
+      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART234578_CLKSOURCE);
+    }
+    else if (USARTx == UART5)
+    {
+      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART234578_CLKSOURCE);
+    }
+    else if (USARTx == USART6)
+    {
+      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART16_CLKSOURCE);
+    }
+    else if (USARTx == UART7)
+    {
+      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART234578_CLKSOURCE);
+    }
+    else if (USARTx == UART8)
+    {
+      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART234578_CLKSOURCE);
+    }
+#if defined(UART9)
+    else if (USARTx == UART9)
+    {
+      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART16_CLKSOURCE);
+    }
+#endif /* UART9 */
+#if defined(USART10)
+    else if (USARTx == USART10)
+    {
+      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART16_CLKSOURCE);
+    }
+#endif /* USART10 */
+    else
+    {
+      /* Nothing to do, as error code is already assigned to ERROR value */
+    }
+
+    /* Configure the USART Baud Rate :
+       - prescaler value is required
+       - valid baud rate value (different from 0) is required
+       - Peripheral clock as returned by RCC service, should be valid (different from 0).
+    */
+    if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
+        && (USART_InitStruct->BaudRate != 0U))
+    {
+      status = SUCCESS;
+      LL_USART_SetBaudRate(USARTx,
+                           periphclk,
+                           USART_InitStruct->PrescalerValue,
+                           USART_InitStruct->OverSampling,
+                           USART_InitStruct->BaudRate);
+
+      /* Check BRR is greater than or equal to 16d */
+      assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
+
+      /* Check BRR is lower than or equal to 0xFFFF */
+      assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR));
+    }
+
+    /*---------------------------- USART PRESC Configuration -----------------------
+     * Configure USARTx PRESC (Prescaler) with parameters:
+     * - PrescalerValue: USART_PRESC_PRESCALER bits according to USART_InitStruct->PrescalerValue value.
+     */
+    LL_USART_SetPrescaler(USARTx, USART_InitStruct->PrescalerValue);
+  }
+  /* Endif (=> USART not in Disabled state => return ERROR) */
+
+  return (status);
+}
+
+/**
+  * @brief Set each @ref LL_USART_InitTypeDef field to default value.
+  * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure
+  *                         whose fields will be set to default values.
+  * @retval None
+  */
+
+void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
+{
+  /* Set USART_InitStruct fields to default values */
+  USART_InitStruct->PrescalerValue      = LL_USART_PRESCALER_DIV1;
+  USART_InitStruct->BaudRate            = 9600U;
+  USART_InitStruct->DataWidth           = LL_USART_DATAWIDTH_8B;
+  USART_InitStruct->StopBits            = LL_USART_STOPBITS_1;
+  USART_InitStruct->Parity              = LL_USART_PARITY_NONE ;
+  USART_InitStruct->TransferDirection   = LL_USART_DIRECTION_TX_RX;
+  USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
+  USART_InitStruct->OverSampling        = LL_USART_OVERSAMPLING_16;
+}
+
+/**
+  * @brief  Initialize USART Clock related settings according to the
+  *         specified parameters in the USART_ClockInitStruct.
+  * @note   As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
+  *         USART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+  * @param  USARTx USART Instance
+  * @param  USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
+  *         that contains the Clock configuration information for the specified USART peripheral.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
+  *          - ERROR: Problem occurred during USART Registers initialization
+  */
+ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check USART Instance and Clock signal output parameters */
+  assert_param(IS_UART_INSTANCE(USARTx));
+  assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
+
+  /* USART needs to be in disabled state, in order to be able to configure some bits in
+     CRx registers */
+  if (LL_USART_IsEnabled(USARTx) == 0U)
+  {
+    /*---------------------------- USART CR2 Configuration -----------------------*/
+    /* If Clock signal has to be output */
+    if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
+    {
+      /* Deactivate Clock signal delivery :
+       * - Disable Clock Output:        USART_CR2_CLKEN cleared
+       */
+      LL_USART_DisableSCLKOutput(USARTx);
+    }
+    else
+    {
+      /* Ensure USART instance is USART capable */
+      assert_param(IS_USART_INSTANCE(USARTx));
+
+      /* Check clock related parameters */
+      assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
+      assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
+      assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
+
+      /*---------------------------- USART CR2 Configuration -----------------------
+       * Configure USARTx CR2 (Clock signal related bits) with parameters:
+       * - Enable Clock Output:         USART_CR2_CLKEN set
+       * - Clock Polarity:              USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
+       * - Clock Phase:                 USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
+       * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
+       */
+      MODIFY_REG(USARTx->CR2,
+                 USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
+                 USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
+                 USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
+    }
+  }
+  /* Else (USART not in Disabled state => return ERROR */
+  else
+  {
+    status = ERROR;
+  }
+
+  return (status);
+}
+
+/**
+  * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
+  * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
+  *                              whose fields will be set to default values.
+  * @retval None
+  */
+void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
+{
+  /* Set LL_USART_ClockInitStruct fields with default values */
+  USART_ClockInitStruct->ClockOutput       = LL_USART_CLOCK_DISABLE;
+  USART_ClockInitStruct->ClockPolarity     = LL_USART_POLARITY_LOW;            /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
+  USART_ClockInitStruct->ClockPhase        = LL_USART_PHASE_1EDGE;             /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
+  USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT;  /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 || UART9 || USART10 */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c
new file mode 100644
index 00000000..1e4ae32f
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c
@@ -0,0 +1,1989 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_usb.c
+  * @author  MCD Application Team
+  * @brief   USB Low Layer HAL module driver.
+  *
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the USB Peripheral Controller:
+  *           + Initialization/de-initialization functions
+  *           + I/O operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State functions
+  *
+  @verbatim
+  ==============================================================================
+                    ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure.
+
+      (#) Call USB_CoreInit() API to initialize the USB Core peripheral.
+
+      (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_LL_USB_DRIVER
+  * @{
+  */
+
+#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED)
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx);
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup USB_LL_Exported_Functions USB Low Layer Exported Functions
+  * @{
+  */
+
+/** @defgroup USB_LL_Exported_Functions_Group1 Initialization/de-initialization functions
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### Initialization/de-initialization functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the USB Core
+  * @param  USBx USB Instance
+  * @param  cfg pointer to a USB_OTG_CfgTypeDef structure that contains
+  *         the configuration information for the specified USBx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
+{
+  HAL_StatusTypeDef ret;
+
+  if (cfg.phy_itface == USB_OTG_ULPI_PHY)
+  {
+    USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
+
+    /* Init The ULPI Interface */
+    USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
+
+    /* Select vbus source */
+    USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
+    if (cfg.use_external_vbus == 1U)
+    {
+      USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;
+    }
+    /* Reset after a PHY select  */
+    ret = USB_CoreReset(USBx);
+  }
+  else /* FS interface (embedded Phy) */
+  {
+    /* Select FS Embedded PHY */
+    USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
+
+    /* Reset after a PHY select and set Host mode */
+    ret = USB_CoreReset(USBx);
+
+    if (cfg.battery_charging_enable == 0U)
+    {
+      /* Activate the USB Transceiver */
+      USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
+    }
+    else
+    {
+      /* Deactivate the USB Transceiver */
+      USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
+    }
+  }
+
+  if (cfg.dma_enable == 1U)
+  {
+    USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2;
+    USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;
+  }
+
+  return ret;
+}
+
+
+/**
+  * @brief  Set the USB turnaround time
+  * @param  USBx USB Instance
+  * @param  hclk: AHB clock frequency
+  * @retval USB turnaround time In PHY Clocks number
+  */
+HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx,
+                                        uint32_t hclk, uint8_t speed)
+{
+  uint32_t UsbTrd;
+
+  /* The USBTRD is configured according to the tables below, depending on AHB frequency
+  used by application. In the low AHB frequency range it is used to stretch enough the USB response
+  time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access
+  latency to the Data FIFO */
+  if (speed == USBD_FS_SPEED)
+  {
+    if ((hclk >= 14200000U) && (hclk < 15000000U))
+    {
+      /* hclk Clock Range between 14.2-15 MHz */
+      UsbTrd = 0xFU;
+    }
+    else if ((hclk >= 15000000U) && (hclk < 16000000U))
+    {
+      /* hclk Clock Range between 15-16 MHz */
+      UsbTrd = 0xEU;
+    }
+    else if ((hclk >= 16000000U) && (hclk < 17200000U))
+    {
+      /* hclk Clock Range between 16-17.2 MHz */
+      UsbTrd = 0xDU;
+    }
+    else if ((hclk >= 17200000U) && (hclk < 18500000U))
+    {
+      /* hclk Clock Range between 17.2-18.5 MHz */
+      UsbTrd = 0xCU;
+    }
+    else if ((hclk >= 18500000U) && (hclk < 20000000U))
+    {
+      /* hclk Clock Range between 18.5-20 MHz */
+      UsbTrd = 0xBU;
+    }
+    else if ((hclk >= 20000000U) && (hclk < 21800000U))
+    {
+      /* hclk Clock Range between 20-21.8 MHz */
+      UsbTrd = 0xAU;
+    }
+    else if ((hclk >= 21800000U) && (hclk < 24000000U))
+    {
+      /* hclk Clock Range between 21.8-24 MHz */
+      UsbTrd = 0x9U;
+    }
+    else if ((hclk >= 24000000U) && (hclk < 27700000U))
+    {
+      /* hclk Clock Range between 24-27.7 MHz */
+      UsbTrd = 0x8U;
+    }
+    else if ((hclk >= 27700000U) && (hclk < 32000000U))
+    {
+      /* hclk Clock Range between 27.7-32 MHz */
+      UsbTrd = 0x7U;
+    }
+    else /* if(hclk >= 32000000) */
+    {
+      /* hclk Clock Range between 32-200 MHz */
+      UsbTrd = 0x6U;
+    }
+  }
+  else if (speed == USBD_HS_SPEED)
+  {
+    UsbTrd = USBD_HS_TRDT_VALUE;
+  }
+  else
+  {
+    UsbTrd = USBD_DEFAULT_TRDT_VALUE;
+  }
+
+  USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
+  USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_EnableGlobalInt
+  *         Enables the controller's Global Int in the AHB Config reg
+  * @param  USBx  Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
+{
+  USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_DisableGlobalInt
+  *         Disable the controller's Global Int in the AHB Config reg
+  * @param  USBx  Selected device
+  * @retval HAL status
+*/
+HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
+{
+  USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_SetCurrentMode : Set functional mode
+  * @param  USBx  Selected device
+  * @param  mode   current core mode
+  *          This parameter can be one of these values:
+  *            @arg USB_DEVICE_MODE: Peripheral mode
+  *            @arg USB_HOST_MODE: Host mode
+  *            @arg USB_DRD_MODE: Dual Role Device mode
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode)
+{
+  USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
+
+  if (mode == USB_HOST_MODE)
+  {
+    USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;
+  }
+  else if (mode == USB_DEVICE_MODE)
+  {
+    USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+  HAL_Delay(50U);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_DevInit : Initializes the USB_OTG controller registers
+  *         for device mode
+  * @param  USBx  Selected device
+  * @param  cfg   pointer to a USB_OTG_CfgTypeDef structure that contains
+  *         the configuration information for the specified USBx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
+{
+  HAL_StatusTypeDef ret = HAL_OK;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t i;
+
+  for (i = 0U; i < 15U; i++)
+  {
+    USBx->DIEPTXF[i] = 0U;
+  }
+
+  /* VBUS Sensing setup */
+  if (cfg.vbus_sensing_enable == 0U)
+  {
+    USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
+
+    /* Deactivate VBUS Sensing B */
+    USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
+
+    /* B-peripheral session valid override enable */
+    USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
+    USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
+  }
+  else
+  {
+    /* Enable HW VBUS sensing */
+    USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
+  }
+
+  /* Restart the Phy Clock */
+  USBx_PCGCCTL = 0U;
+
+  /* Device mode configuration */
+  USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80;
+
+  if (cfg.phy_itface == USB_OTG_ULPI_PHY)
+  {
+    if (cfg.speed == USBD_HS_SPEED)
+    {
+      /* Set Core speed to High speed mode */
+      (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH);
+    }
+    else
+    {
+      /* Set Core speed to Full speed mode */
+      (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL);
+    }
+  }
+  else
+  {
+    /* Set Core speed to Full speed mode */
+    (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL);
+  }
+
+  /* Flush the FIFOs */
+  if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */
+  {
+    ret = HAL_ERROR;
+  }
+
+  if (USB_FlushRxFifo(USBx) != HAL_OK)
+  {
+    ret = HAL_ERROR;
+  }
+
+  /* Clear all pending Device Interrupts */
+  USBx_DEVICE->DIEPMSK = 0U;
+  USBx_DEVICE->DOEPMSK = 0U;
+  USBx_DEVICE->DAINTMSK = 0U;
+
+  for (i = 0U; i < cfg.dev_endpoints; i++)
+  {
+    if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
+    {
+      if (i == 0U)
+      {
+        USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK;
+      }
+      else
+      {
+        USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK;
+      }
+    }
+    else
+    {
+      USBx_INEP(i)->DIEPCTL = 0U;
+    }
+
+    USBx_INEP(i)->DIEPTSIZ = 0U;
+    USBx_INEP(i)->DIEPINT  = 0xFB7FU;
+  }
+
+  for (i = 0U; i < cfg.dev_endpoints; i++)
+  {
+    if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
+    {
+      if (i == 0U)
+      {
+        USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK;
+      }
+      else
+      {
+        USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK;
+      }
+    }
+    else
+    {
+      USBx_OUTEP(i)->DOEPCTL = 0U;
+    }
+
+    USBx_OUTEP(i)->DOEPTSIZ = 0U;
+    USBx_OUTEP(i)->DOEPINT  = 0xFB7FU;
+  }
+
+  USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
+
+  /* Disable all interrupts. */
+  USBx->GINTMSK = 0U;
+
+  /* Clear any pending interrupts */
+  USBx->GINTSTS = 0xBFFFFFFFU;
+
+  /* Enable the common interrupts */
+  if (cfg.dma_enable == 0U)
+  {
+    USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
+  }
+
+  /* Enable interrupts matching to the Device mode ONLY */
+  USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |
+                   USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |
+                   USB_OTG_GINTMSK_OEPINT   | USB_OTG_GINTMSK_IISOIXFRM |
+                   USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM;
+
+  if (cfg.Sof_enable != 0U)
+  {
+    USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;
+  }
+
+  if (cfg.vbus_sensing_enable == 1U)
+  {
+    USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  USB_OTG_FlushTxFifo : Flush a Tx FIFO
+  * @param  USBx  Selected device
+  * @param  num  FIFO number
+  *         This parameter can be a value from 1 to 15
+            15 means Flush all Tx FIFOs
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
+{
+  uint32_t count = 0U;
+
+  USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6));
+
+  do
+  {
+    if (++count > 200000U)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_FlushRxFifo : Flush Rx FIFO
+  * @param  USBx  Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t count = 0;
+
+  USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
+
+  do
+  {
+    if (++count > 200000U)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_SetDevSpeed  Initializes the DevSpd field of DCFG register
+  *         depending the PHY type and the enumeration speed of the device.
+  * @param  USBx  Selected device
+  * @param  speed  device speed
+  *          This parameter can be one of these values:
+  *            @arg USB_OTG_SPEED_HIGH: High speed mode
+  *            @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode
+  *            @arg USB_OTG_SPEED_FULL: Full speed mode
+  * @retval  Hal status
+  */
+HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  USBx_DEVICE->DCFG |= speed;
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_GetDevSpeed  Return the Dev Speed
+  * @param  USBx  Selected device
+  * @retval speed  device speed
+  *          This parameter can be one of these values:
+  *            @arg PCD_SPEED_HIGH: High speed mode
+  *            @arg PCD_SPEED_FULL: Full speed mode
+  */
+uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint8_t speed;
+  uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD;
+
+  if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ)
+  {
+    speed = USBD_HS_SPEED;
+  }
+  else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) ||
+           (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ))
+  {
+    speed = USBD_FS_SPEED;
+  }
+  else
+  {
+    speed = 0xFU;
+  }
+
+  return speed;
+}
+
+/**
+  * @brief  Activate and configure an endpoint
+  * @param  USBx  Selected device
+  * @param  ep pointer to endpoint structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t epnum = (uint32_t)ep->num;
+
+  if (ep->is_in == 1U)
+  {
+    USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK));
+
+    if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U)
+    {
+      USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
+                                   ((uint32_t)ep->type << 18) | (epnum << 22) |
+                                   USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
+                                   USB_OTG_DIEPCTL_USBAEP;
+    }
+  }
+  else
+  {
+    USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16);
+
+    if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)
+    {
+      USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |
+                                    ((uint32_t)ep->type << 18) |
+                                    USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
+                                    USB_OTG_DOEPCTL_USBAEP;
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Activate and configure a dedicated endpoint
+  * @param  USBx  Selected device
+  * @param  ep pointer to endpoint structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t epnum = (uint32_t)ep->num;
+
+  /* Read DEPCTLn register */
+  if (ep->is_in == 1U)
+  {
+    if (((USBx_INEP(epnum)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U)
+    {
+      USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
+                                   ((uint32_t)ep->type << 18) | (epnum << 22) |
+                                   USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
+                                   USB_OTG_DIEPCTL_USBAEP;
+    }
+
+    USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK));
+  }
+  else
+  {
+    if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)
+    {
+      USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |
+                                    ((uint32_t)ep->type << 18) | (epnum << 22) |
+                                    USB_OTG_DOEPCTL_USBAEP;
+    }
+
+    USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  De-activate and de-initialize an endpoint
+  * @param  USBx  Selected device
+  * @param  ep pointer to endpoint structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t epnum = (uint32_t)ep->num;
+
+  /* Read DEPCTLn register */
+  if (ep->is_in == 1U)
+  {
+    USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
+    USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
+    USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP |
+                                   USB_OTG_DIEPCTL_MPSIZ |
+                                   USB_OTG_DIEPCTL_TXFNUM |
+                                   USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
+                                   USB_OTG_DIEPCTL_EPTYP);
+  }
+  else
+  {
+    USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
+    USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
+    USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP |
+                                    USB_OTG_DOEPCTL_MPSIZ |
+                                    USB_OTG_DOEPCTL_SD0PID_SEVNFRM |
+                                    USB_OTG_DOEPCTL_EPTYP);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  De-activate and de-initialize a dedicated endpoint
+  * @param  USBx  Selected device
+  * @param  ep pointer to endpoint structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t epnum = (uint32_t)ep->num;
+
+  /* Read DEPCTLn register */
+  if (ep->is_in == 1U)
+  {
+    USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
+    USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
+  }
+  else
+  {
+    USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
+    USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_EPStartXfer : setup and starts a transfer over an EP
+  * @param  USBx  Selected device
+  * @param  ep pointer to endpoint structure
+  * @param  dma USB dma enabled or disabled
+  *          This parameter can be one of these values:
+  *           0 : DMA feature not used
+  *           1 : DMA feature used
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t epnum = (uint32_t)ep->num;
+  uint16_t pktcnt;
+
+  /* IN endpoint */
+  if (ep->is_in == 1U)
+  {
+    /* Zero Length Packet? */
+    if (ep->xfer_len == 0U)
+    {
+      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
+      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
+      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
+    }
+    else
+    {
+      /* Program the transfer size and packet count
+      * as follows: xfersize = N * maxpacket +
+      * short_packet pktcnt = N + (short_packet
+      * exist ? 1 : 0)
+      */
+      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
+      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
+      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19));
+      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
+
+      if (ep->type == EP_TYPE_ISOC)
+      {
+        USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT);
+        USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29));
+      }
+    }
+
+    if (dma == 1U)
+    {
+      if ((uint32_t)ep->dma_addr != 0U)
+      {
+        USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr);
+      }
+
+      if (ep->type == EP_TYPE_ISOC)
+      {
+        if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
+        {
+          USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
+        }
+        else
+        {
+          USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
+        }
+      }
+
+      /* EP enable, IN data in FIFO */
+      USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
+    }
+    else
+    {
+      /* EP enable, IN data in FIFO */
+      USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
+
+      if (ep->type != EP_TYPE_ISOC)
+      {
+        /* Enable the Tx FIFO Empty Interrupt for this EP */
+        if (ep->xfer_len > 0U)
+        {
+          USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK);
+        }
+      }
+      else
+      {
+        if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
+        {
+          USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
+        }
+        else
+        {
+          USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
+        }
+
+        (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma);
+      }
+    }
+  }
+  else /* OUT endpoint */
+  {
+    /* Program the transfer size and packet count as follows:
+    * pktcnt = N
+    * xfersize = N * maxpacket
+    */
+    USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
+    USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
+
+    if (ep->xfer_len == 0U)
+    {
+      USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);
+      USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
+    }
+    else
+    {
+      pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket);
+      USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19);
+      USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt);
+    }
+
+    if (dma == 1U)
+    {
+      if ((uint32_t)ep->xfer_buff != 0U)
+      {
+        USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff);
+      }
+    }
+
+    if (ep->type == EP_TYPE_ISOC)
+    {
+      if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
+      {
+        USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;
+      }
+      else
+      {
+        USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
+      }
+    }
+    /* EP enable */
+    USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_EP0StartXfer : setup and starts a transfer over the EP  0
+  * @param  USBx  Selected device
+  * @param  ep pointer to endpoint structure
+  * @param  dma USB dma enabled or disabled
+  *          This parameter can be one of these values:
+  *           0 : DMA feature not used
+  *           1 : DMA feature used
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t epnum = (uint32_t)ep->num;
+
+  /* IN endpoint */
+  if (ep->is_in == 1U)
+  {
+    /* Zero Length Packet? */
+    if (ep->xfer_len == 0U)
+    {
+      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
+      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
+      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
+    }
+    else
+    {
+      /* Program the transfer size and packet count
+      * as follows: xfersize = N * maxpacket +
+      * short_packet pktcnt = N + (short_packet
+      * exist ? 1 : 0)
+      */
+      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
+      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
+
+      if (ep->xfer_len > ep->maxpacket)
+      {
+        ep->xfer_len = ep->maxpacket;
+      }
+      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
+      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
+    }
+
+    if (dma == 1U)
+    {
+      if ((uint32_t)ep->dma_addr != 0U)
+      {
+        USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr);
+      }
+
+      /* EP enable, IN data in FIFO */
+      USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
+    }
+    else
+    {
+      /* EP enable, IN data in FIFO */
+      USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
+
+      /* Enable the Tx FIFO Empty Interrupt for this EP */
+      if (ep->xfer_len > 0U)
+      {
+        USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK);
+      }
+    }
+  }
+  else /* OUT endpoint */
+  {
+    /* Program the transfer size and packet count as follows:
+    * pktcnt = N
+    * xfersize = N * maxpacket
+    */
+    USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
+    USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
+
+    if (ep->xfer_len > 0U)
+    {
+      ep->xfer_len = ep->maxpacket;
+    }
+
+    USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
+    USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket));
+
+    if (dma == 1U)
+    {
+      if ((uint32_t)ep->xfer_buff != 0U)
+      {
+        USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff);
+      }
+    }
+
+    /* EP enable */
+    USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_WritePacket : Writes a packet into the Tx FIFO associated
+  *         with the EP/channel
+  * @param  USBx  Selected device
+  * @param  src   pointer to source buffer
+  * @param  ch_ep_num  endpoint or host channel number
+  * @param  len  Number of bytes to write
+  * @param  dma USB dma enabled or disabled
+  *          This parameter can be one of these values:
+  *           0 : DMA feature not used
+  *           1 : DMA feature used
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t *pSrc = (uint32_t *)src;
+  uint32_t count32b, i;
+
+  if (dma == 0U)
+  {
+    count32b = ((uint32_t)len + 3U) / 4U;
+    for (i = 0U; i < count32b; i++)
+    {
+      USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc);
+      pSrc++;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_ReadPacket : read a packet from the RX FIFO
+  * @param  USBx  Selected device
+  * @param  dest  source pointer
+  * @param  len  Number of bytes to read
+  * @retval pointer to destination buffer
+  */
+void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t *pDest = (uint32_t *)dest;
+  uint32_t i;
+  uint32_t count32b = ((uint32_t)len + 3U) / 4U;
+
+  for (i = 0U; i < count32b; i++)
+  {
+    __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U));
+    pDest++;
+  }
+
+  return ((void *)pDest);
+}
+
+/**
+  * @brief  USB_EPSetStall : set a stall condition over an EP
+  * @param  USBx  Selected device
+  * @param  ep pointer to endpoint structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t epnum = (uint32_t)ep->num;
+
+  if (ep->is_in == 1U)
+  {
+    if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U))
+    {
+      USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS);
+    }
+    USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;
+  }
+  else
+  {
+    if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U))
+    {
+      USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS);
+    }
+    USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_EPClearStall : Clear a stall condition over an EP
+  * @param  USBx  Selected device
+  * @param  ep pointer to endpoint structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t epnum = (uint32_t)ep->num;
+
+  if (ep->is_in == 1U)
+  {
+    USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
+    if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))
+    {
+      USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */
+    }
+  }
+  else
+  {
+    USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
+    if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))
+    {
+      USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_StopDevice : Stop the usb device mode
+  * @param  USBx  Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)
+{
+  HAL_StatusTypeDef ret;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t i;
+
+  /* Clear Pending interrupt */
+  for (i = 0U; i < 15U; i++)
+  {
+    USBx_INEP(i)->DIEPINT = 0xFB7FU;
+    USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
+  }
+
+  /* Clear interrupt masks */
+  USBx_DEVICE->DIEPMSK  = 0U;
+  USBx_DEVICE->DOEPMSK  = 0U;
+  USBx_DEVICE->DAINTMSK = 0U;
+
+  /* Flush the FIFO */
+  ret = USB_FlushRxFifo(USBx);
+  if (ret != HAL_OK)
+  {
+    return ret;
+  }
+
+  ret = USB_FlushTxFifo(USBx,  0x10U);
+  if (ret != HAL_OK)
+  {
+    return ret;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  USB_SetDevAddress : Stop the usb device mode
+  * @param  USBx  Selected device
+  * @param  address  new device address to be assigned
+  *          This parameter can be a value from 0 to 255
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD);
+  USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down
+  * @param  USBx  Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  USB_DevConnect(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS;
+  HAL_Delay(3U);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down
+  * @param  USBx  Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
+  HAL_Delay(3U);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_ReadInterrupts: return the global USB interrupt status
+  * @param  USBx  Selected device
+  * @retval HAL status
+  */
+uint32_t  USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t tmpreg;
+
+  tmpreg = USBx->GINTSTS;
+  tmpreg &= USBx->GINTMSK;
+
+  return tmpreg;
+}
+
+/**
+  * @brief  USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status
+  * @param  USBx  Selected device
+  * @retval HAL status
+  */
+uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t tmpreg;
+
+  tmpreg  = USBx_DEVICE->DAINT;
+  tmpreg &= USBx_DEVICE->DAINTMSK;
+
+  return ((tmpreg & 0xffff0000U) >> 16);
+}
+
+/**
+  * @brief  USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status
+  * @param  USBx  Selected device
+  * @retval HAL status
+  */
+uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t tmpreg;
+
+  tmpreg  = USBx_DEVICE->DAINT;
+  tmpreg &= USBx_DEVICE->DAINTMSK;
+
+  return ((tmpreg & 0xFFFFU));
+}
+
+/**
+  * @brief  Returns Device OUT EP Interrupt register
+  * @param  USBx  Selected device
+  * @param  epnum  endpoint number
+  *          This parameter can be a value from 0 to 15
+  * @retval Device OUT EP Interrupt register
+  */
+uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t tmpreg;
+
+  tmpreg  = USBx_OUTEP((uint32_t)epnum)->DOEPINT;
+  tmpreg &= USBx_DEVICE->DOEPMSK;
+
+  return tmpreg;
+}
+
+/**
+  * @brief  Returns Device IN EP Interrupt register
+  * @param  USBx  Selected device
+  * @param  epnum  endpoint number
+  *          This parameter can be a value from 0 to 15
+  * @retval Device IN EP Interrupt register
+  */
+uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t tmpreg, msk, emp;
+
+  msk = USBx_DEVICE->DIEPMSK;
+  emp = USBx_DEVICE->DIEPEMPMSK;
+  msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7;
+  tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk;
+
+  return tmpreg;
+}
+
+/**
+  * @brief  USB_ClearInterrupts: clear a USB interrupt
+  * @param  USBx  Selected device
+  * @param  interrupt  interrupt flag
+  * @retval None
+  */
+void  USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)
+{
+  USBx->GINTSTS |= interrupt;
+}
+
+/**
+  * @brief  Returns USB core mode
+  * @param  USBx  Selected device
+  * @retval return core mode : Host or Device
+  *          This parameter can be one of these values:
+  *           0 : Host
+  *           1 : Device
+  */
+uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)
+{
+  return ((USBx->GINTSTS) & 0x1U);
+}
+
+/**
+  * @brief  Activate EP0 for Setup transactions
+  * @param  USBx  Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  /* Set the MPS of the IN EP0 to 64 bytes */
+  USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;
+
+  USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Prepare the EP0 to start the first control setup
+  * @param  USBx  Selected device
+  * @param  dma USB dma enabled or disabled
+  *          This parameter can be one of these values:
+  *           0 : DMA feature not used
+  *           1 : DMA feature used
+  * @param  psetup  pointer to setup packet
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
+
+  if (gSNPSiD > USB_OTG_CORE_ID_300A)
+  {
+    if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
+    {
+      return HAL_OK;
+    }
+  }
+
+  USBx_OUTEP(0U)->DOEPTSIZ = 0U;
+  USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
+  USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U);
+  USBx_OUTEP(0U)->DOEPTSIZ |=  USB_OTG_DOEPTSIZ_STUPCNT;
+
+  if (dma == 1U)
+  {
+    USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup;
+    /* EP enable */
+    USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Reset the USB Core (needed after USB clock settings change)
+  * @param  USBx  Selected device
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t count = 0U;
+
+  /* Wait for AHB master IDLE state. */
+  do
+  {
+    if (++count > 200000U)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
+
+  /* Core Soft Reset */
+  count = 0U;
+  USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
+
+  do
+  {
+    if (++count > 200000U)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_HostInit : Initializes the USB OTG controller registers
+  *         for Host mode
+  * @param  USBx  Selected device
+  * @param  cfg   pointer to a USB_OTG_CfgTypeDef structure that contains
+  *         the configuration information for the specified USBx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t i;
+
+  /* Restart the Phy Clock */
+  USBx_PCGCCTL = 0U;
+
+  /* Disable VBUS sensing */
+  USBx->GCCFG &= ~(USB_OTG_GCCFG_VBDEN);
+
+  /* Disable Battery chargin detector */
+  USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN);
+
+
+  if ((USBx->CID & (0x1U << 8)) != 0U)
+  {
+    if (cfg.speed == USB_OTG_SPEED_FULL)
+    {
+      /* Force Device Enumeration to FS/LS mode only */
+      USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS;
+    }
+    else
+    {
+      /* Set default Max speed support */
+      USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);
+    }
+  }
+  else
+  {
+    /* Set default Max speed support */
+    USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);
+  }
+
+  /* Make sure the FIFOs are flushed. */
+  (void)USB_FlushTxFifo(USBx, 0x10U); /* all Tx FIFOs */
+  (void)USB_FlushRxFifo(USBx);
+
+  /* Clear all pending HC Interrupts */
+  for (i = 0U; i < cfg.Host_channels; i++)
+  {
+    USBx_HC(i)->HCINT = 0xFFFFFFFFU;
+    USBx_HC(i)->HCINTMSK = 0U;
+  }
+
+  /* Enable VBUS driving */
+  (void)USB_DriveVbus(USBx, 1U);
+
+  HAL_Delay(200U);
+
+  /* Disable all interrupts. */
+  USBx->GINTMSK = 0U;
+
+  /* Clear any pending interrupts */
+  USBx->GINTSTS = 0xFFFFFFFFU;
+
+  if ((USBx->CID & (0x1U << 8)) != 0U)
+  {
+    /* set Rx FIFO size */
+    USBx->GRXFSIZ  = 0x200U;
+    USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x100U << 16) & USB_OTG_NPTXFD) | 0x200U);
+    USBx->HPTXFSIZ = (uint32_t)(((0xE0U << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U);
+  }
+  else
+  {
+    /* set Rx FIFO size */
+    USBx->GRXFSIZ  = 0x80U;
+    USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x60U << 16) & USB_OTG_NPTXFD) | 0x80U);
+    USBx->HPTXFSIZ = (uint32_t)(((0x40U << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U);
+  }
+
+  /* Enable the common interrupts */
+  if (cfg.dma_enable == 0U)
+  {
+    USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
+  }
+
+  /* Enable interrupts matching to the Host mode ONLY */
+  USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM            | USB_OTG_GINTMSK_HCIM | \
+                    USB_OTG_GINTMSK_SOFM             | USB_OTG_GINTSTS_DISCINT | \
+                    USB_OTG_GINTMSK_PXFRM_IISOOXFRM  | USB_OTG_GINTMSK_WUIM);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the
+  *         HCFG register on the PHY type and set the right frame interval
+  * @param  USBx  Selected device
+  * @param  freq  clock frequency
+  *          This parameter can be one of these values:
+  *           HCFG_48_MHZ : Full Speed 48 MHz Clock
+  *           HCFG_6_MHZ : Low Speed 6 MHz Clock
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS);
+  USBx_HOST->HCFG |= (uint32_t)freq & USB_OTG_HCFG_FSLSPCS;
+
+  if (freq == HCFG_48_MHZ)
+  {
+    USBx_HOST->HFIR = 48000U;
+  }
+  else if (freq == HCFG_6_MHZ)
+  {
+    USBx_HOST->HFIR = 6000U;
+  }
+  else
+  {
+    /* ... */
+  }
+
+  return HAL_OK;
+}
+
+/**
+* @brief  USB_OTG_ResetPort : Reset Host Port
+  * @param  USBx  Selected device
+  * @retval HAL status
+  * @note (1)The application must wait at least 10 ms
+  *   before clearing the reset bit.
+  */
+HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  __IO uint32_t hprt0 = 0U;
+
+  hprt0 = USBx_HPRT0;
+
+  hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |
+             USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
+
+  USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0);
+  HAL_Delay(100U);                                 /* See Note #1 */
+  USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0);
+  HAL_Delay(10U);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_DriveVbus : activate or de-activate vbus
+  * @param  state  VBUS state
+  *          This parameter can be one of these values:
+  *           0 : VBUS Active
+  *           1 : VBUS Inactive
+  * @retval HAL status
+*/
+HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  __IO uint32_t hprt0 = 0U;
+
+  hprt0 = USBx_HPRT0;
+
+  hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |
+             USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
+
+  if (((hprt0 & USB_OTG_HPRT_PPWR) == 0U) && (state == 1U))
+  {
+    USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0);
+  }
+  if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0U))
+  {
+    USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0);
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Return Host Core speed
+  * @param  USBx  Selected device
+  * @retval speed : Host speed
+  *          This parameter can be one of these values:
+  *            @arg HCD_SPEED_HIGH: High speed mode
+  *            @arg HCD_SPEED_FULL: Full speed mode
+  *            @arg HCD_SPEED_LOW: Low speed mode
+  */
+uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  __IO uint32_t hprt0 = 0U;
+
+  hprt0 = USBx_HPRT0;
+  return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17);
+}
+
+/**
+  * @brief  Return Host Current Frame number
+  * @param  USBx  Selected device
+  * @retval current frame number
+*/
+uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM);
+}
+
+/**
+  * @brief  Initialize a host channel
+  * @param  USBx  Selected device
+  * @param  ch_num  Channel number
+  *         This parameter can be a value from 1 to 15
+  * @param  epnum  Endpoint number
+  *          This parameter can be a value from 1 to 15
+  * @param  dev_address  Current device address
+  *          This parameter can be a value from 0 to 255
+  * @param  speed  Current device speed
+  *          This parameter can be one of these values:
+  *            @arg USB_OTG_SPEED_HIGH: High speed mode
+  *            @arg USB_OTG_SPEED_FULL: Full speed mode
+  *            @arg USB_OTG_SPEED_LOW: Low speed mode
+  * @param  ep_type  Endpoint Type
+  *          This parameter can be one of these values:
+  *            @arg EP_TYPE_CTRL: Control type
+  *            @arg EP_TYPE_ISOC: Isochronous type
+  *            @arg EP_TYPE_BULK: Bulk type
+  *            @arg EP_TYPE_INTR: Interrupt type
+  * @param  mps  Max Packet Size
+  *          This parameter can be a value from 0 to32K
+  * @retval HAL state
+  */
+HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
+                              uint8_t ch_num,
+                              uint8_t epnum,
+                              uint8_t dev_address,
+                              uint8_t speed,
+                              uint8_t ep_type,
+                              uint16_t mps)
+{
+  HAL_StatusTypeDef ret = HAL_OK;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t HCcharEpDir, HCcharLowSpeed;
+
+  /* Clear old interrupt conditions for this host channel. */
+  USBx_HC((uint32_t)ch_num)->HCINT = 0xFFFFFFFFU;
+
+  /* Enable channel interrupts required for this transfer. */
+  switch (ep_type)
+  {
+    case EP_TYPE_CTRL:
+    case EP_TYPE_BULK:
+      USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |
+                                            USB_OTG_HCINTMSK_STALLM |
+                                            USB_OTG_HCINTMSK_TXERRM |
+                                            USB_OTG_HCINTMSK_DTERRM |
+                                            USB_OTG_HCINTMSK_AHBERR |
+                                            USB_OTG_HCINTMSK_NAKM;
+
+      if ((epnum & 0x80U) == 0x80U)
+      {
+        USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
+      }
+      else
+      {
+        if ((USBx->CID & (0x1U << 8)) != 0U)
+        {
+          USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);
+        }
+      }
+      break;
+
+    case EP_TYPE_INTR:
+      USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |
+                                            USB_OTG_HCINTMSK_STALLM |
+                                            USB_OTG_HCINTMSK_TXERRM |
+                                            USB_OTG_HCINTMSK_DTERRM |
+                                            USB_OTG_HCINTMSK_NAKM   |
+                                            USB_OTG_HCINTMSK_AHBERR |
+                                            USB_OTG_HCINTMSK_FRMORM;
+
+      if ((epnum & 0x80U) == 0x80U)
+      {
+        USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
+      }
+
+      break;
+
+    case EP_TYPE_ISOC:
+      USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |
+                                            USB_OTG_HCINTMSK_ACKM   |
+                                            USB_OTG_HCINTMSK_AHBERR |
+                                            USB_OTG_HCINTMSK_FRMORM;
+
+      if ((epnum & 0x80U) == 0x80U)
+      {
+        USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM);
+      }
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+  }
+
+  /* Enable the top level host channel interrupt. */
+  USBx_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU);
+
+  /* Make sure host channel interrupts are enabled. */
+  USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM;
+
+  /* Program the HCCHAR register */
+  if ((epnum & 0x80U) == 0x80U)
+  {
+    HCcharEpDir = (0x1U << 15) & USB_OTG_HCCHAR_EPDIR;
+  }
+  else
+  {
+    HCcharEpDir = 0U;
+  }
+
+  if (speed == HPRT0_PRTSPD_LOW_SPEED)
+  {
+    HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV;
+  }
+  else
+  {
+    HCcharLowSpeed = 0U;
+  }
+
+  USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) |
+                                      ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) |
+                                      (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) |
+                                      ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | HCcharEpDir | HCcharLowSpeed;
+
+  if (ep_type == EP_TYPE_INTR)
+  {
+    USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Start a transfer over a host channel
+  * @param  USBx  Selected device
+  * @param  hc  pointer to host channel structure
+  * @param  dma USB dma enabled or disabled
+  *          This parameter can be one of these values:
+  *           0 : DMA feature not used
+  *           1 : DMA feature used
+  * @retval HAL state
+  */
+HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t ch_num = (uint32_t)hc->ch_num;
+  static __IO uint32_t tmpreg = 0U;
+  uint8_t  is_oddframe;
+  uint16_t len_words;
+  uint16_t num_packets;
+  uint16_t max_hc_pkt_count = 256U;
+
+  if (((USBx->CID & (0x1U << 8)) != 0U) && (hc->speed == USBH_HS_SPEED))
+  {
+    if ((dma == 0U) && (hc->do_ping == 1U))
+    {
+      (void)USB_DoPing(USBx, hc->ch_num);
+      return HAL_OK;
+    }
+    else if (dma == 1U)
+    {
+      USBx_HC(ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);
+      hc->do_ping = 0U;
+    }
+    else
+    {
+      /* ... */
+    }
+  }
+
+  /* Compute the expected number of packets associated to the transfer */
+  if (hc->xfer_len > 0U)
+  {
+    num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet);
+
+    if (num_packets > max_hc_pkt_count)
+    {
+      num_packets = max_hc_pkt_count;
+      hc->xfer_len = (uint32_t)num_packets * hc->max_packet;
+    }
+  }
+  else
+  {
+    num_packets = 1U;
+  }
+  if (hc->ep_is_in != 0U)
+  {
+    hc->xfer_len = (uint32_t)num_packets * hc->max_packet;
+  }
+
+  /* Initialize the HCTSIZn register */
+  USBx_HC(ch_num)->HCTSIZ = (hc->xfer_len & USB_OTG_HCTSIZ_XFRSIZ) |
+                            (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |
+                            (((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID);
+
+  if (dma != 0U)
+  {
+    /* xfer_buff MUST be 32-bits aligned */
+    USBx_HC(ch_num)->HCDMA = (uint32_t)hc->xfer_buff;
+  }
+
+  is_oddframe = (((uint32_t)USBx_HOST->HFNUM & 0x01U) != 0U) ? 0U : 1U;
+  USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM;
+  USBx_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29;
+
+  /* Set host channel enable */
+  tmpreg = USBx_HC(ch_num)->HCCHAR;
+  tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+
+  /* make sure to set the correct ep direction */
+  if (hc->ep_is_in != 0U)
+  {
+    tmpreg |= USB_OTG_HCCHAR_EPDIR;
+  }
+  else
+  {
+    tmpreg &= ~USB_OTG_HCCHAR_EPDIR;
+  }
+  tmpreg |= USB_OTG_HCCHAR_CHENA;
+  USBx_HC(ch_num)->HCCHAR = tmpreg;
+
+  if (dma == 0U) /* Slave mode */
+  {
+    if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U))
+    {
+      switch (hc->ep_type)
+      {
+        /* Non periodic transfer */
+        case EP_TYPE_CTRL:
+        case EP_TYPE_BULK:
+
+          len_words = (uint16_t)((hc->xfer_len + 3U) / 4U);
+
+          /* check if there is enough space in FIFO space */
+          if (len_words > (USBx->HNPTXSTS & 0xFFFFU))
+          {
+            /* need to process data in nptxfempty interrupt */
+            USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM;
+          }
+          break;
+
+        /* Periodic transfer */
+        case EP_TYPE_INTR:
+        case EP_TYPE_ISOC:
+          len_words = (uint16_t)((hc->xfer_len + 3U) / 4U);
+          /* check if there is enough space in FIFO space */
+          if (len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */
+          {
+            /* need to process data in ptxfempty interrupt */
+            USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM;
+          }
+          break;
+
+        default:
+          break;
+      }
+
+      /* Write packet into the Tx FIFO. */
+      (void)USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len, 0);
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Read all host channel interrupts status
+  * @param  USBx  Selected device
+  * @retval HAL state
+  */
+uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  return ((USBx_HOST->HAINT) & 0xFFFFU);
+}
+
+/**
+  * @brief  Halt a host channel
+  * @param  USBx  Selected device
+  * @param  hc_num  Host Channel number
+  *         This parameter can be a value from 1 to 15
+  * @retval HAL state
+  */
+HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t hcnum = (uint32_t)hc_num;
+  uint32_t count = 0U;
+  uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18;
+
+  /* Check for space in the request queue to issue the halt. */
+  if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK))
+  {
+    USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
+
+    if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U)
+    {
+      USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
+      USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+      USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
+      do
+      {
+        if (++count > 1000U)
+        {
+          break;
+        }
+      }
+      while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
+    }
+    else
+    {
+      USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+    }
+  }
+  else
+  {
+    USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
+
+    if ((USBx_HOST->HPTXSTS & (0xFFU << 16)) == 0U)
+    {
+      USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
+      USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+      USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
+      do
+      {
+        if (++count > 1000U)
+        {
+          break;
+        }
+      }
+      while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
+    }
+    else
+    {
+      USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initiate Do Ping protocol
+  * @param  USBx  Selected device
+  * @param  hc_num  Host Channel number
+  *         This parameter can be a value from 1 to 15
+  * @retval HAL state
+  */
+HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t chnum = (uint32_t)ch_num;
+  uint32_t num_packets = 1U;
+  uint32_t tmpreg;
+
+  USBx_HC(chnum)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |
+                           USB_OTG_HCTSIZ_DOPING;
+
+  /* Set host channel enable */
+  tmpreg = USBx_HC(chnum)->HCCHAR;
+  tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+  tmpreg |= USB_OTG_HCCHAR_CHENA;
+  USBx_HC(chnum)->HCCHAR = tmpreg;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop Host Core
+  * @param  USBx  Selected device
+  * @retval HAL state
+  */
+HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t count = 0U;
+  uint32_t value;
+  uint32_t i;
+
+  (void)USB_DisableGlobalInt(USBx);
+
+  /* Flush FIFO */
+  (void)USB_FlushTxFifo(USBx, 0x10U);
+  (void)USB_FlushRxFifo(USBx);
+
+  /* Flush out any leftover queued requests. */
+  for (i = 0U; i <= 15U; i++)
+  {
+    value = USBx_HC(i)->HCCHAR;
+    value |=  USB_OTG_HCCHAR_CHDIS;
+    value &= ~USB_OTG_HCCHAR_CHENA;
+    value &= ~USB_OTG_HCCHAR_EPDIR;
+    USBx_HC(i)->HCCHAR = value;
+  }
+
+  /* Halt all channels to put them into a known state. */
+  for (i = 0U; i <= 15U; i++)
+  {
+    value = USBx_HC(i)->HCCHAR;
+    value |= USB_OTG_HCCHAR_CHDIS;
+    value |= USB_OTG_HCCHAR_CHENA;
+    value &= ~USB_OTG_HCCHAR_EPDIR;
+    USBx_HC(i)->HCCHAR = value;
+
+    do
+    {
+      if (++count > 1000U)
+      {
+        break;
+      }
+    }
+    while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
+  }
+
+  /* Clear any pending Host interrupts */
+  USBx_HOST->HAINT = 0xFFFFFFFFU;
+  USBx->GINTSTS = 0xFFFFFFFFU;
+
+  (void)USB_EnableGlobalInt(USBx);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_ActivateRemoteWakeup active remote wakeup signalling
+  * @param  USBx Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
+  {
+    /* active Remote wakeup signalling */
+    USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_DeActivateRemoteWakeup de-active remote wakeup signalling
+  * @param  USBx Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  /* active Remote wakeup signalling */
+  USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);
+
+  return HAL_OK;
+}
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_utils.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_utils.c
new file mode 100644
index 00000000..cf19f617
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_utils.c
@@ -0,0 +1,975 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_utils.c
+  * @author  MCD Application Team
+  * @brief   UTILS LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_ll_utils.h"
+#include "stm32h7xx_ll_rcc.h"
+#include "stm32h7xx_ll_pwr.h"
+
+#ifdef  USE_FULL_ASSERT
+  #include "stm32_assert.h"
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+/** @addtogroup UTILS_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup UTILS_LL_Private_Constants
+  * @{
+  */
+#if (POWER_DOMAINS_NUMBER == 3U)
+#define UTILS_MAX_FREQUENCY_SCALE1  400000000U      /*!< Maximum frequency for system clock at power scale1, in Hz */
+#define UTILS_MAX_FREQUENCY_SCALE2  300000000U      /*!< Maximum frequency for system clock at power scale2, in Hz */
+#define UTILS_MAX_FREQUENCY_SCALE3  200000000U      /*!< Maximum frequency for system clock at power scale3, in Hz */
+#else
+#define UTILS_MAX_FREQUENCY_SCALE0  280000000U      /*!< Maximum frequency for system clock at power scale0, in Hz */
+#define UTILS_MAX_FREQUENCY_SCALE1  225000000U      /*!< Maximum frequency for system clock at power scale1, in Hz */
+#define UTILS_MAX_FREQUENCY_SCALE2  160000000U      /*!< Maximum frequency for system clock at power scale2, in Hz */
+#define UTILS_MAX_FREQUENCY_SCALE3   88000000U      /*!< Maximum frequency for system clock at power scale3, in Hz */
+#endif /*POWER_DOMAINS_NUMBER == 3U*/
+
+/* Defines used for PLL range */
+#define UTILS_PLLVCO_INPUT_MIN1       1000000U      /*!< Frequency min for the low range PLLVCO input, in Hz    */
+#define UTILS_PLLVCO_INPUT_MAX1       2000000U      /*!< Frequency max for the wide range PLLVCO input, in Hz   */
+#define UTILS_PLLVCO_INPUT_MIN2       2000000U      /*!< Frequency min for the low range PLLVCO input, in Hz    */
+#define UTILS_PLLVCO_INPUT_MAX2       4000000U      /*!< Frequency max for the wide range PLLVCO input, in Hz   */
+#define UTILS_PLLVCO_INPUT_MIN3       4000000U      /*!< Frequency min for the low range PLLVCO input, in Hz    */
+#define UTILS_PLLVCO_INPUT_MAX3       8000000U      /*!< Frequency max for the wide range PLLVCO input, in Hz   */
+#define UTILS_PLLVCO_INPUT_MIN4       8000000U      /*!< Frequency min for the low range PLLVCO input, in Hz    */
+#define UTILS_PLLVCO_INPUT_MAX4      16000000U      /*!< Frequency max for the wide range PLLVCO input, in Hz   */
+
+#if (POWER_DOMAINS_NUMBER == 3U)
+#define UTILS_PLLVCO_MEDIUM_OUTPUT_MIN    150000000U      /*!< Frequency min for the medium range PLLVCO output, in Hz   */
+#define UTILS_PLLVCO_WIDE_OUTPUT_MIN      192000000U      /*!< Frequency min for the wide range PLLVCO output, in Hz   */
+#define UTILS_PLLVCO_MEDIUM_OUTPUT_MAX    420000000U      /*!< Frequency max for the medium range PLLVCO output, in Hz  */
+#define UTILS_PLLVCO_WIDE_OUTPUT_MAX      836000000U      /*!< Frequency max for the wide range PLLVCO output, in Hz  */
+#else
+#define UTILS_PLLVCO_MEDIUM_OUTPUT_MIN    150000000U      /*!< Frequency min for the medium range PLLVCO output, in Hz   */
+#define UTILS_PLLVCO_WIDE_OUTPUT_MIN      128000000U      /*!< Frequency min for the wide range PLLVCO output, in Hz   */
+#define UTILS_PLLVCO_MEDIUM_OUTPUT_MAX    420000000U      /*!< Frequency max for the medium range PLLVCO output, in Hz  */
+#define UTILS_PLLVCO_WIDE_OUTPUT_MAX      560000000U      /*!< Frequency max for the wide range PLLVCO output, in Hz  */
+#endif /*POWER_DOMAINS_NUMBER == 3U*/
+
+/* Defines used for HSE range */
+#define UTILS_HSE_FREQUENCY_MIN      4000000U        /*!< Frequency min for HSE frequency, in Hz   */
+#define UTILS_HSE_FREQUENCY_MAX     48000000U        /*!< Frequency max for HSE frequency, in Hz   */
+
+/* Defines used for FLASH latency according to HCLK Frequency */
+#if (POWER_DOMAINS_NUMBER == 2U)
+#define UTILS_SCALE0_LATENCY0_FREQ   44000000U       /*!< HCLK frequency to set FLASH latency 0 in power scale 0  */
+#define UTILS_SCALE0_LATENCY1_FREQ   88000000U       /*!< HCLK frequency to set FLASH latency 1 in power scale 0  */
+#define UTILS_SCALE0_LATENCY2_FREQ  132000000U       /*!< HCLK frequency to set FLASH latency 2 in power scale 0  */
+#define UTILS_SCALE0_LATENCY3_FREQ  176000000U       /*!< HCLK frequency to set FLASH latency 3 in power scale 0  */
+#define UTILS_SCALE0_LATENCY4_FREQ  220000000U       /*!< HCLK frequency to set FLASH latency 4 in power scale 0  */
+#define UTILS_SCALE0_LATENCY5_FREQ  264000000U       /*!< HCLK frequency to set FLASH latency 5 in power scale 0  */
+#define UTILS_SCALE0_LATENCY6_FREQ  280000000U       /*!< HCLK frequency to set FLASH latency 6 in power scale 0  */
+
+#define UTILS_SCALE1_LATENCY0_FREQ   42000000U      /*!< HCLK frequency to set FLASH latency 0 in power scale 1  */
+#define UTILS_SCALE1_LATENCY1_FREQ   84000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 1  */
+#define UTILS_SCALE1_LATENCY2_FREQ  126000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 1  */
+#define UTILS_SCALE1_LATENCY3_FREQ  168000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 1  */
+#define UTILS_SCALE1_LATENCY4_FREQ  210000000U      /*!< HCLK frequency to set FLASH latency 4 in power scale 1  */
+#define UTILS_SCALE1_LATENCY5_FREQ  225000000U      /*!< HCLK frequency to set FLASH latency 5 in power scale 1  */
+
+#define UTILS_SCALE2_LATENCY0_FREQ   34000000U      /*!< HCLK frequency to set FLASH latency 0 in power scale 2  */
+#define UTILS_SCALE2_LATENCY1_FREQ   68000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 2  */
+#define UTILS_SCALE2_LATENCY2_FREQ  102000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 2  */
+#define UTILS_SCALE2_LATENCY3_FREQ  136000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 2  */
+#define UTILS_SCALE2_LATENCY4_FREQ  160000000U      /*!< HCLK frequency to set FLASH latency 4 in power scale 2  */
+
+#define UTILS_SCALE3_LATENCY0_FREQ   22000000U      /*!< HCLK frequency to set FLASH latency 0 in power scale 3  */
+#define UTILS_SCALE3_LATENCY1_FREQ   44000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 3  */
+#define UTILS_SCALE3_LATENCY2_FREQ   66000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 3  */
+#define UTILS_SCALE3_LATENCY3_FREQ   88000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 3  */
+
+#else
+
+#define UTILS_SCALE1_LATENCY0_FREQ   70000000U      /*!< HCLK frequency to set FLASH latency 0 in power scale 1  */
+#define UTILS_SCALE1_LATENCY1_FREQ  140000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 1  */
+#define UTILS_SCALE1_LATENCY2_FREQ  210000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 1  */
+
+#define UTILS_SCALE2_LATENCY0_FREQ   55000000U      /*!< HCLK frequency to set FLASH latency 0 in power scale 2  */
+#define UTILS_SCALE2_LATENCY1_FREQ  110000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 2  */
+#define UTILS_SCALE2_LATENCY2_FREQ  165000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 2  */
+#define UTILS_SCALE2_LATENCY3_FREQ  220000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 2  */
+
+#define UTILS_SCALE3_LATENCY0_FREQ   45000000U      /*!< HCLK frequency to set FLASH latency 0 in power scale 3  */
+#define UTILS_SCALE3_LATENCY1_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 3  */
+#define UTILS_SCALE3_LATENCY2_FREQ  135000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 3  */
+#define UTILS_SCALE3_LATENCY3_FREQ  180000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 3  */
+#define UTILS_SCALE3_LATENCY4_FREQ  225000000U      /*!< HCLK frequency to set FLASH latency 4 in power scale 3  */
+#endif /*POWER_DOMAINS_NUMBER == 2U*/
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup UTILS_LL_Private_Macros
+  * @{
+  */
+#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1)   \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2)   \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4)   \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8)   \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16)  \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64)  \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
+
+#define IS_LL_UTILS_AHB_DIV(__VALUE__)    (((__VALUE__) == LL_RCC_AHB_DIV_1)   \
+                                        || ((__VALUE__) == LL_RCC_AHB_DIV_2)   \
+                                        || ((__VALUE__) == LL_RCC_AHB_DIV_4)   \
+                                        || ((__VALUE__) == LL_RCC_AHB_DIV_8)   \
+                                        || ((__VALUE__) == LL_RCC_AHB_DIV_16)  \
+                                        || ((__VALUE__) == LL_RCC_AHB_DIV_64)  \
+                                        || ((__VALUE__) == LL_RCC_AHB_DIV_128) \
+                                        || ((__VALUE__) == LL_RCC_AHB_DIV_256) \
+                                        || ((__VALUE__) == LL_RCC_AHB_DIV_512))
+
+#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
+                                      || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
+                                      || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
+                                      || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
+                                      || ((__VALUE__) == LL_RCC_APB1_DIV_16))
+
+#define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
+                                      || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
+                                      || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
+                                      || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
+                                      || ((__VALUE__) == LL_RCC_APB2_DIV_16))
+
+#define IS_LL_UTILS_APB3_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB3_DIV_1) \
+                                      || ((__VALUE__) == LL_RCC_APB3_DIV_2) \
+                                      || ((__VALUE__) == LL_RCC_APB3_DIV_4) \
+                                      || ((__VALUE__) == LL_RCC_APB3_DIV_8) \
+                                      || ((__VALUE__) == LL_RCC_APB3_DIV_16))
+
+#define IS_LL_UTILS_APB4_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB4_DIV_1) \
+                                      || ((__VALUE__) == LL_RCC_APB4_DIV_2) \
+                                      || ((__VALUE__) == LL_RCC_APB4_DIV_4) \
+                                      || ((__VALUE__) == LL_RCC_APB4_DIV_8) \
+                                      || ((__VALUE__) == LL_RCC_APB4_DIV_16))
+
+#define IS_LL_UTILS_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 63U))
+
+#if (POWER_DOMAINS_NUMBER == 3U)
+#define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((4U <= (__VALUE__)) && ((__VALUE__) <= 512U))
+#else
+#define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 420U))
+#endif /*POWER_DOMAINS_NUMBER == 3U*/
+
+#define IS_LL_UTILS_PLLP_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 128U))
+
+#define IS_LL_UTILS_FRACN_VALUE(__VALUE__) ((__VALUE__) <= 0x1FFFU)
+
+#define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__, __RANGE__)  ( \
+(((__RANGE__) == LL_RCC_PLLINPUTRANGE_1_2) && (UTILS_PLLVCO_INPUT_MIN1 <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX1)) || \
+(((__RANGE__) == LL_RCC_PLLINPUTRANGE_2_4) && (UTILS_PLLVCO_INPUT_MIN2 <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX2)) || \
+(((__RANGE__) == LL_RCC_PLLINPUTRANGE_4_8) && (UTILS_PLLVCO_INPUT_MIN3 <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX3)) || \
+(((__RANGE__) == LL_RCC_PLLINPUTRANGE_8_16) && (UTILS_PLLVCO_INPUT_MIN4 <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX4)))
+
+#define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__, __RANGE__) ( \
+(((__RANGE__) == LL_RCC_PLLVCORANGE_MEDIUM) && (UTILS_PLLVCO_MEDIUM_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_MEDIUM_OUTPUT_MAX)) || \
+(((__RANGE__) == LL_RCC_PLLVCORANGE_WIDE) && (UTILS_PLLVCO_WIDE_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_WIDE_OUTPUT_MAX)))
+
+#define IS_LL_UTILS_CHECK_VCO_RANGES(__RANGEIN__, __RANGEOUT__) ( \
+(((__RANGEIN__) == LL_RCC_PLLINPUTRANGE_1_2) && ((__RANGEOUT__) == LL_RCC_PLLVCORANGE_MEDIUM)) || \
+(((__RANGEIN__) != LL_RCC_PLLINPUTRANGE_1_2) && ((__RANGEOUT__) == LL_RCC_PLLVCORANGE_WIDE)))
+
+#if (POWER_DOMAINS_NUMBER == 3U)
+#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
+                                              (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \
+                                              ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))
+#else
+#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE0) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE0) : \
+                                              (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
+                                              (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \
+                                              ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))
+#endif /*POWER_DOMAINS_NUMBER == 3U*/
+
+#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
+                                        || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
+
+#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
+/**
+  * @}
+  */
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Functions UTILS Private functions
+  * @{
+  */
+static uint32_t    UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
+static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+static ErrorStatus UTILS_IsPLLsReady(void);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UTILS_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup UTILS_LL_EF_DELAY
+  * @{
+  */
+#if defined (DUAL_CORE)
+/**
+  * @brief  This function configures the Cortex-M SysTick source to have 1ms time base.
+  * @note   When a RTOS is used, it is recommended to avoid changing the Systick
+  *         configuration by calling this function, for a delay use rather osDelay RTOS service.
+  * @param  CPU_Frequency Core frequency in Hz
+  * @note   CPU_Frequency can be calculated thanks to RCC helper macro or function
+  *         @ref LL_RCC_GetSystemClocksFreq
+  *         LL_RCC_GetSystemClocksFreq() is used to calculate the CM7 clock frequency
+  *         and __LL_RCC_CALC_HCLK_FREQ is used to caluclate the CM4 clock frequency.
+  * @retval None
+  */
+#else
+/**
+  * @brief  This function configures the Cortex-M SysTick source to have 1ms time base.
+  * @note   When a RTOS is used, it is recommended to avoid changing the Systick
+  *         configuration by calling this function, for a delay use rather osDelay RTOS service.
+  * @param  CPU_Frequency Core frequency in Hz
+  * @note   CPU_Frequency can be calculated thanks to RCC helper macro or function
+  *         @ref LL_RCC_GetSystemClocksFreq
+  * @retval None
+  */
+#endif /* DUAL_CORE */
+void LL_Init1msTick(uint32_t CPU_Frequency)
+{
+  /* Use frequency provided in argument */
+  LL_InitTick(CPU_Frequency, 1000U);
+}
+
+
+/**
+  * @brief  This function provides accurate delay (in milliseconds) based
+  *         on SysTick counter flag
+  * @note   When a RTOS is used, it is recommended to avoid using blocking delay
+  *         and use rather osDelay service.
+  * @note   To respect 1ms timebase, user should call @ref LL_Init1msTick function which
+  *         will configure Systick to 1ms
+  * @param  Delay specifies the delay time length, in milliseconds.
+  * @retval None
+  */
+void LL_mDelay(uint32_t Delay)
+{
+  uint32_t count = Delay;
+  __IO uint32_t  tmp = SysTick->CTRL;  /* Clear the COUNTFLAG first */
+  /* Add this code to indicate that local variable is not used */
+  ((void)tmp);
+
+  /* Add a period to guaranty minimum wait */
+  if(count < LL_MAX_DELAY)
+  {
+    count++;
+  }
+
+  while (count != 0U)
+  {
+    if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
+    {
+      count--;
+    }
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup UTILS_EF_SYSTEM
+  *  @brief    System Configuration functions
+  *
+  @verbatim
+ ===============================================================================
+           ##### System Configuration functions #####
+ ===============================================================================
+    [..]
+         System, AHB and APB buses clocks configuration
+
+#if (POWER_DOMAINS_NUMBER == 3U)
+         (+) The maximum frequency of the SYSCLK is 400 MHz and HCLK is 200 MHz.
+         (+) The maximum frequency of the PCLK1, PCLK2, PCLK3 and PCLK4 is 100 MHz.
+  @endverbatim
+  @internal
+             Depending on the device voltage range, the maximum frequency should be
+             adapted accordingly:
+             (++) +----------------------------------------------------------------------------+
+             (++) |  Wait states   |                           HCLK clock frequency (MHz)      |
+             (++) |                |-----------------------------------------------------------|
+             (++) |  (Latency)     |   voltage range 1 |   voltage range 2 |   voltage range 3 |
+             (++) |                |    1.15V - 1.26V  |    1.05V - 1.15V  |    0.95V - 1.05V  |
+             (++) |----------------|-------------------|-------------------|-------------------|
+             (++) |0WS(1CPU cycle) |   0 < HCLK <= 70  |   0 < HCLK <= 55  |   0 < HCLK <= 45  |
+             (++) |----------------|-------------------|-------------------|-------------------|
+             (++) |1WS(2CPU cycle) |  70 < HCLK <= 140 |  55 < HCLK <= 110 |  45 < HCLK <= 90  |
+             (++) |----------------|-------------------|-------------------|-------------------|
+             (++) |2WS(3CPU cycle) | 140 < HCLK <= 210 | 110 < HCLK <= 165 |  90 < HCLK <= 135 |
+             (++) |----------------|-------------------|-------------------|-------------------|
+             (++) |3WS(4CPU cycle) |        --         | 165 < HCLK <= 220 | 135 < HCLK <= 180 |
+             (++) |----------------|-------------------|-------------------|-------------------|
+             (++) |4WS(5CPU cycle) |        --         |        --         | 180 < HCLK <= 225 |
+             (++) +----------------------------------------------------------------------------+
+
+#else
+         (+) The maximum frequency of the SYSCLK is 280 MHz and HCLK is 280 MHz.
+         (+) The maximum frequency of the PCLK1, PCLK2, PCLK3 and PCLK4 is 140 MHz.
+  @endverbatim
+  @internal
+             Depending on the device voltage range, the maximum frequency should be
+             adapted accordingly:
+             (++) +------------------------------------------------------------------------------------------------+
+             (++) |  Wait states   |                          HCLK clock frequency (MHz)                           |
+             (++) |                |-------------------------------------------------------------------------------|
+             (++) |  (Latency)     |   voltage range 0 |   voltage range 1 |   voltage range 2 |   voltage range 3 |
+             (++) |                |    1.26V - 1.35V  |    1.15V - 1.26V  |    1.05V - 1.15V  |    0.95V - 1.05V  |
+             (++) |----------------|-------------------|-------------------|-------------------|-------------------|
+             (++) |0WS(1CPU cycle) |   0 < HCLK <= 44  |   0 < HCLK <= 42  |   0 < HCLK <= 34  |   0 < HCLK <= 22  |
+             (++) |----------------|-------------------|-------------------|-------------------|-------------------|
+             (++) |1WS(2CPU cycle) |  44 < HCLK <= 88  |  42 < HCLK <= 84  |  34 < HCLK <= 68  |  22 < HCLK <= 44  |
+             (++) |----------------|-------------------|-------------------|-------------------|-------------------|
+             (++) |2WS(3CPU cycle) |  88 < HCLK <= 132 |  84 < HCLK <= 126 |  68 < HCLK <= 102 |  44 < HCLK <= 66  |
+             (++) |----------------|-------------------|-------------------|-------------------|-------------------|
+             (++) |3WS(4CPU cycle) | 132 < HCLK <= 176 | 126 < HCLK <= 168 | 102 < HCLK <= 136 |  66 < HCLK <= 88  |
+             (++) |----------------|-------------------|-------------------|-------------------|-------------------|
+             (++) |4WS(5CPU cycle) | 176 < HCLK <= 220 | 168 < HCLK <= 210 | 136 < HCLK <= 160 |        --         |
+             (++) +------------------------------------------------------------------------------------------------+
+             (++) |5WS(6CPU cycle) | 220 < HCLK <= 264 | 210 < HCLK <= 225 |        --         |        --         |
+             (++) +------------------------------------------------------------------------------------------------+
+             (++) |6WS(7CPU cycle) | 264 < HCLK <= 280 |        --         |        --         |        --         |
+             (++) +------------------------------------------------------------------------------------------------+
+             (++) |7WS(8CPU cycle) |        --         |        --         |        --         |        --         |
+             (++) +------------------------------------------------------------------------------------------------+
+
+#endif
+  @endinternal
+  * @{
+  */
+#if defined (DUAL_CORE)
+/**
+  * @brief  This function sets directly SystemCoreClock CMSIS variable.
+  * @note   Variable can be calculated also through SystemCoreClockUpdate function.
+  * @param  CPU_Frequency Core frequency in Hz
+  * @note   CPU_Frequency can be calculated thanks to RCC helper macro or function
+  *         @ref LL_RCC_GetSystemClocksFreq
+  *         LL_RCC_GetSystemClocksFreq() is used to calculate the CM7 clock frequency
+  *         and __LL_RCC_CALC_HCLK_FREQ is used to caluclate the CM4 clock frequency.
+  * @retval None
+  */
+#else
+/**
+  * @brief  This function sets directly SystemCoreClock CMSIS variable.
+  * @note   Variable can be calculated also through SystemCoreClockUpdate function.
+  * @param  CPU_Frequency Core frequency in Hz
+  * @note   CPU_Frequency can be calculated thanks to RCC helper macro or function
+  *         @ref LL_RCC_GetSystemClocksFreq
+  * @retval None
+  */
+#endif /* DUAL_CORE */
+void LL_SetSystemCoreClock(uint32_t CPU_Frequency)
+{
+  /* HCLK clock frequency */
+  SystemCoreClock = CPU_Frequency;
+}
+
+/**
+  * @brief  This function configures system clock at maximum frequency with HSI as clock source of the PLL
+  * @note   The application need to ensure that PLL is disabled.
+  * @note   Function is based on the following formula:
+  *         - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP)
+  *         - PLLM: ensure that the VCO input frequency ranges from 1 to 16 MHz (PLLVCO_input = HSI frequency / PLLM)
+  *         - PLLN: ensure that the VCO output frequency is between 150 and 836 MHz or 128 to 560 MHz(*) (PLLVCO_output = PLLVCO_input * PLLN)
+  *         - PLLP: ensure that max frequency at 400000000 Hz or 280000000 Hz is reach (PLLVCO_output / PLLP)
+  * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+  *                             the configuration information for the PLL.
+  * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+  *                             the configuration information for the BUS prescalers.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: Max frequency configuration done
+  *          - ERROR: Max frequency configuration not done
+  *
+  * (*) : For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines.
+  *
+  */
+ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
+                                         LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
+{
+  ErrorStatus status;
+#ifdef  USE_FULL_ASSERT
+  uint32_t vcoinput_freq, vcooutput_freq;
+#endif
+  uint32_t pllfreq, hsi_clk;
+
+  /* Check the parameters */
+  assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
+  assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
+  assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
+  assert_param(IS_LL_UTILS_FRACN_VALUE(UTILS_PLLInitStruct->FRACN));
+
+  hsi_clk = (HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos));
+
+  /* Check VCO Input frequency */
+#ifdef  USE_FULL_ASSERT
+  vcoinput_freq = hsi_clk / UTILS_PLLInitStruct->PLLM;
+#endif
+  assert_param(IS_LL_UTILS_PLLVCO_INPUT(vcoinput_freq, UTILS_PLLInitStruct->VCO_Input));
+
+  /* Check VCO Output frequency */
+#ifdef  USE_FULL_ASSERT
+  vcooutput_freq = LL_RCC_CalcPLLClockFreq(hsi_clk, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->FRACN, 1UL);
+#endif
+  assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(vcooutput_freq, UTILS_PLLInitStruct->VCO_Output));
+
+  /* Check VCO Input ranges */
+  assert_param(IS_LL_UTILS_CHECK_VCO_RANGES(UTILS_PLLInitStruct->VCO_Input, UTILS_PLLInitStruct->VCO_Output));
+
+  /* Check if one of the PLL is enabled */
+  if(UTILS_IsPLLsReady() == SUCCESS)
+  {
+    /* Calculate the new PLL output frequency */
+    pllfreq = UTILS_GetPLLOutputFrequency(hsi_clk, UTILS_PLLInitStruct);
+
+    /* Enable HSI if not enabled */
+    if(LL_RCC_HSI_IsReady() != 1U)
+    {
+      LL_RCC_HSI_Enable();
+      while (LL_RCC_HSI_IsReady() != 1U)
+      {
+        /* Wait for HSI ready */
+      }
+    }
+
+    /* Configure PLL */
+    LL_RCC_PLL1P_Enable();
+    LL_RCC_PLL1FRACN_Enable();
+    LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_HSI);
+    LL_RCC_PLL1_SetVCOInputRange(UTILS_PLLInitStruct->VCO_Input);
+    LL_RCC_PLL1_SetVCOOutputRange(UTILS_PLLInitStruct->VCO_Output);
+    LL_RCC_PLL1_SetM(UTILS_PLLInitStruct->PLLM);
+    LL_RCC_PLL1_SetN(UTILS_PLLInitStruct->PLLN);
+    LL_RCC_PLL1_SetP(UTILS_PLLInitStruct->PLLP);
+    LL_RCC_PLL1_SetFRACN(UTILS_PLLInitStruct->FRACN);
+
+    /* Enable PLL and switch system clock to PLL */
+    status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
+  }
+  else
+  {
+    /* Current PLL configuration cannot be modified */
+    status = ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  This function configures system clock with HSE as clock source of the PLL
+  * @note   The application need to ensure that PLL is disabled.
+  * @note   Function is based on the following formula:
+  *         - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLP)
+  *         - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.10 MHz (PLLVCO_input = HSE frequency / PLLM)
+  *         - PLLN: ensure that the VCO output frequency is between 150 and 836 MHz or 128 to 560 MHz(*) (PLLVCO_output = PLLVCO_input * PLLN)
+  *         - PLLP: ensure that max frequency at 400000000 Hz or 280000000 Hz(*) is reached (PLLVCO_output / PLLP)
+  * @param  HSEFrequency Value between Min_Data = 4000000 and Max_Data = 48000000
+  * @param  HSEBypass This parameter can be one of the following values:
+  *         @arg @ref LL_UTILS_HSEBYPASS_ON
+  *         @arg @ref LL_UTILS_HSEBYPASS_OFF
+  * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+  *                             the configuration information for the PLL.
+  * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+  *                             the configuration information for the BUS prescalers.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: Max frequency configuration done
+  *          - ERROR: Max frequency configuration not done
+  *
+  * (*) : For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines.
+  *
+  */
+ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
+                                         LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
+{
+  ErrorStatus status;
+#ifdef  USE_FULL_ASSERT
+  uint32_t vcoinput_freq, vcooutput_freq;
+#endif
+  uint32_t pllfreq;
+
+  /* Check the parameters */
+  assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
+  assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
+  assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
+  assert_param(IS_LL_UTILS_FRACN_VALUE(UTILS_PLLInitStruct->FRACN));
+  assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
+  assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
+
+  /* Check VCO Input frequency */
+#ifdef  USE_FULL_ASSERT
+  vcoinput_freq = HSEFrequency / UTILS_PLLInitStruct->PLLM;
+#endif
+  assert_param(IS_LL_UTILS_PLLVCO_INPUT(vcoinput_freq, UTILS_PLLInitStruct->VCO_Input));
+
+  /* Check VCO output frequency */
+#ifdef  USE_FULL_ASSERT
+  vcooutput_freq = LL_RCC_CalcPLLClockFreq(HSEFrequency, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->FRACN, 1U);
+#endif
+  assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(vcooutput_freq, UTILS_PLLInitStruct->VCO_Output));
+
+  /* Check VCO Input/output ranges compatibility */
+  assert_param(IS_LL_UTILS_CHECK_VCO_RANGES(UTILS_PLLInitStruct->VCO_Input, UTILS_PLLInitStruct->VCO_Output));
+
+  /* Check if one of the PLL is enabled */
+  if(UTILS_IsPLLsReady() == SUCCESS)
+  {
+    /* Calculate the new PLL output frequency */
+    pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
+
+    /* Enable HSE if not enabled */
+    if(LL_RCC_HSE_IsReady() != 1U)
+    {
+      /* Check if need to enable HSE bypass feature or not */
+      if(HSEBypass == LL_UTILS_HSEBYPASS_ON)
+      {
+        LL_RCC_HSE_EnableBypass();
+      }
+      else
+      {
+        LL_RCC_HSE_DisableBypass();
+      }
+
+      /* Enable HSE */
+      LL_RCC_HSE_Enable();
+      while (LL_RCC_HSE_IsReady() != 1U)
+      {
+        /* Wait for HSE ready */
+      }
+    }
+
+    /* Configure PLL */
+    LL_RCC_PLL1P_Enable();
+    LL_RCC_PLL1FRACN_Enable();
+    LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_HSE);
+    LL_RCC_PLL1_SetVCOInputRange(UTILS_PLLInitStruct->VCO_Input);
+    LL_RCC_PLL1_SetVCOOutputRange(UTILS_PLLInitStruct->VCO_Output);
+    LL_RCC_PLL1_SetM(UTILS_PLLInitStruct->PLLM);
+    LL_RCC_PLL1_SetN(UTILS_PLLInitStruct->PLLN);
+    LL_RCC_PLL1_SetP(UTILS_PLLInitStruct->PLLP);
+    LL_RCC_PLL1_SetFRACN(UTILS_PLLInitStruct->FRACN);
+
+    /* Enable PLL and switch system clock to PLL */
+    status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
+  }
+  else
+  {
+    /* Current PLL configuration cannot be modified */
+    status = ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Update number of Flash wait states in line with new frequency and current
+            voltage range.
+  * @param  HCLK_Frequency  HCLK frequency
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: Latency has been modified
+  *          - ERROR: Latency cannot be modified
+  */
+ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency)
+{
+  ErrorStatus status = SUCCESS;
+  uint32_t timeout;
+  uint32_t getlatency;
+  uint32_t latency = LL_FLASH_LATENCY_0;  /* default value 0WS */
+
+
+
+  /* Frequency cannot be equal to 0 */
+  if (HCLK_Frequency == 0U)
+  {
+    status = ERROR;
+  }
+  else
+  {
+#if (POWER_DOMAINS_NUMBER == 2U)
+    if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE0)
+    {
+      if((HCLK_Frequency > UTILS_SCALE0_LATENCY5_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY6_FREQ))
+      {
+        /* 264 < HCLK <= 280 => 6WS (7 CPU cycles) */
+        latency = LL_FLASH_LATENCY_6;
+      }
+      else if((HCLK_Frequency > UTILS_SCALE0_LATENCY4_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY5_FREQ))
+      {
+        /* 220 < HCLK <= 264 => 5WS (6 CPU cycles) */
+        latency = LL_FLASH_LATENCY_5;
+      }
+      else if((HCLK_Frequency > UTILS_SCALE0_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY4_FREQ))
+      {
+        /* 176 < HCLK <= 220 => 4WS (5 CPU cycles) */
+        latency = LL_FLASH_LATENCY_4;
+      }
+      else if((HCLK_Frequency > UTILS_SCALE0_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY3_FREQ))
+      {
+        /* 132 < HCLK <= 176 => 3WS (4 CPU cycles) */
+        latency = LL_FLASH_LATENCY_3;
+      }
+      else if((HCLK_Frequency > UTILS_SCALE0_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY2_FREQ))
+      {
+        /* 88 < HCLK <= 132 => 2WS (3 CPU cycles) */
+        latency = LL_FLASH_LATENCY_2;
+      }
+      else if((HCLK_Frequency > UTILS_SCALE0_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY1_FREQ))
+      {
+        /* 44 < HCLK <= 88 => 1WS (2 CPU cycles) */
+        latency = LL_FLASH_LATENCY_1;
+      }
+      else if(HCLK_Frequency <= UTILS_SCALE0_LATENCY0_FREQ)
+      {
+        /* HCLK <= 44 => 0WS (1 CPU cycles) : Do nothing keep latency to default  LL_FLASH_LATENCY_0 */
+      }
+      else
+      {
+        status = ERROR;
+      }
+    }
+    else if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
+    {
+      if((HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY5_FREQ))
+      {
+        /* 210 < HCLK <= 225 => 5WS (6 CPU cycles) */
+        latency = LL_FLASH_LATENCY_5;
+      }
+      else if((HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY4_FREQ))
+      {
+        /* 168 < HCLK <= 210 => 4WS (5 CPU cycles) */
+        latency = LL_FLASH_LATENCY_4;
+      }
+      else if((HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY3_FREQ))
+      {
+        /* 126 < HCLK <= 168 => 3WS (4 CPU cycles) */
+        latency = LL_FLASH_LATENCY_3;
+      }
+      else if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY2_FREQ))
+#else
+    if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
+    {
+      if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY2_FREQ))
+#endif /*POWER_DOMAINS_NUMBER == 2U*/
+      {
+        /* 140 < HCLK <= 210 => 2WS (3 CPU cycles) */
+        latency = LL_FLASH_LATENCY_2;
+      }
+      else if((HCLK_Frequency > UTILS_SCALE1_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY1_FREQ))
+      {
+        /* 70 < HCLK <= 140 => 1WS (2 CPU cycles) */
+        latency = LL_FLASH_LATENCY_1;
+      }
+      else if(HCLK_Frequency <= UTILS_SCALE1_LATENCY0_FREQ)
+      {
+        /* HCLK <= 70 => 0WS (1 CPU cycles) : Do nothing keep latency to default  LL_FLASH_LATENCY_0 */
+      }
+      else
+      {
+        status = ERROR;
+      }
+    }
+    else if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2)
+    {
+#if (POWER_DOMAINS_NUMBER == 2U)
+      if((HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY4_FREQ))
+      {
+        /* 136 < HCLK <= 160 => 4WS (5 CPU cycles) */
+        latency = LL_FLASH_LATENCY_4;
+      }
+      else if((HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY3_FREQ))
+#else
+      if((HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY3_FREQ))
+#endif /*POWER_DOMAINS_NUMBER == 2U*/
+      {
+        /* 165 < HCLK <= 220 => 3WS (4 CPU cycles) */
+        latency = LL_FLASH_LATENCY_3;
+      }
+      else if((HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY2_FREQ))
+      {
+        /* 110 < HCLK <= 165 => 2WS (3 CPU cycles) */
+        latency = LL_FLASH_LATENCY_2;
+      }
+      else if((HCLK_Frequency > UTILS_SCALE2_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY1_FREQ))
+      {
+        /* 55 < HCLK <= 110 => 1WS (2 CPU cycles) */
+        latency = LL_FLASH_LATENCY_1;
+      }
+      else if(HCLK_Frequency <= UTILS_SCALE2_LATENCY0_FREQ)
+      {
+        /* HCLK <= 55 => 0WS (1 CPU cycles) : Do nothing keep latency to default  LL_FLASH_LATENCY_0 */
+      }
+      else
+      {
+        status = ERROR;
+      }
+    }
+    else /* Scale 3 */
+    {
+#if (POWER_DOMAINS_NUMBER == 3U)
+      if((HCLK_Frequency > UTILS_SCALE3_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY4_FREQ))
+      {
+        /* 180 < HCLK <= 225 => 4WS (5 CPU cycles) */
+        latency = LL_FLASH_LATENCY_4;
+      }
+      else if((HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY3_FREQ))
+#else
+      if((HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY3_FREQ))
+#endif /*POWER_DOMAINS_NUMBER == 3U*/
+      {
+        /* 135 < HCLK <= 180 => 3WS (4 CPU cycles) */
+        latency = LL_FLASH_LATENCY_3;
+      }
+      else if((HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY2_FREQ))
+      {
+        /* 90 < HCLK <= 135 => 2WS (3 CPU cycles) */
+        latency = LL_FLASH_LATENCY_2;
+      }
+      else if((HCLK_Frequency > UTILS_SCALE3_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY1_FREQ))
+      {
+        /* 45 < HCLK <= 90 => 1WS (2 CPU cycles) */
+        latency = LL_FLASH_LATENCY_1;
+      }
+      else if(HCLK_Frequency <= UTILS_SCALE3_LATENCY0_FREQ)
+      {
+        /* HCLK <= 45 => 0WS (1 CPU cycles) : Do nothing keep latency to default  LL_FLASH_LATENCY_0 */
+      }
+      else
+      {
+        status = ERROR;
+      }
+    }
+
+    if(status == SUCCESS)
+    {
+      LL_FLASH_SetLatency(latency);
+
+      /* Check that the new number of wait states is taken into account to access the Flash
+      memory by reading the FLASH_ACR register */
+      timeout = 2;
+      do
+      {
+        /* Wait for Flash latency to be updated */
+        getlatency = LL_FLASH_GetLatency();
+        timeout--;
+      } while ((getlatency != latency) && (timeout > 0U));
+
+      if(getlatency != latency)
+      {
+        status = ERROR;
+      }
+    }
+
+  }
+
+  return status;
+}
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup UTILS_LL_Private_Functions
+  * @{
+  */
+
+
+/**
+  * @brief  Function to check that PLL can be modified
+  * @param  PLL_InputFrequency  PLL input frequency (in Hz)
+  * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+  *                             the configuration information for the PLL.
+  * @retval PLL output frequency (in Hz)
+  */
+static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
+{
+  uint32_t pllfreq;
+
+  /* Check the parameters */
+  assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
+  assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
+  assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
+  assert_param(IS_LL_UTILS_FRACN_VALUE(UTILS_PLLInitStruct->FRACN));
+
+  pllfreq = LL_RCC_CalcPLLClockFreq(PLL_InputFrequency, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->FRACN, UTILS_PLLInitStruct->PLLP);
+
+  return pllfreq;
+}
+
+/**
+  * @brief  Check that all PLLs are ready therefore configuration can be done
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: All PLLs are ready so configuration can be done
+  *          - ERROR: One PLL at least is busy
+  */
+static ErrorStatus UTILS_IsPLLsReady(void)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check if one of the PLL1 is busy */
+  if(LL_RCC_PLL1_IsReady() != 0U)
+  {
+    /* PLL1 configuration cannot be done */
+    status = ERROR;
+  }
+
+  /* Check if one of the PLL2 is busy */
+  if(LL_RCC_PLL2_IsReady() != 0U)
+  {
+    /* PLL2 configuration cannot be done */
+    status = ERROR;
+  }
+
+  /* Check if one of the PLL3 is busy */
+  if(LL_RCC_PLL3_IsReady() != 0U)
+  {
+    /* PLL3 configuration cannot be done */
+    status = ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Function to enable PLL and switch system clock to PLL
+  * @param  SYSCLK_Frequency SYSCLK frequency
+  * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+  *                             the configuration information for the BUS prescalers.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: No problem to switch system to PLL
+  *          - ERROR: Problem to switch system to PLL
+  */
+static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
+{
+  ErrorStatus status = SUCCESS;
+  uint32_t new_hclk_frequency;
+
+  assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->SYSCLKDivider));
+  assert_param(IS_LL_UTILS_AHB_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
+  assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
+  assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
+  assert_param(IS_LL_UTILS_APB3_DIV(UTILS_ClkInitStruct->APB3CLKDivider));
+  assert_param(IS_LL_UTILS_APB4_DIV(UTILS_ClkInitStruct->APB4CLKDivider));
+
+  /* Calculate the new HCLK frequency */
+  new_hclk_frequency = LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
+
+  /* Increasing the number of wait states because of higher CPU frequency */
+  if (SystemD2Clock < new_hclk_frequency)
+  {
+    /* Set FLASH latency to highest latency */
+    status = LL_SetFlashLatency(new_hclk_frequency);
+  }
+
+  /* Update system clock configuration */
+  if(status == SUCCESS)
+  {
+    /* Enable PLL */
+    LL_RCC_PLL1_Enable();
+    while (LL_RCC_PLL1_IsReady() != 1U)
+    {
+      /* Wait for PLL ready */
+    }
+
+    /* Set All APBxPrescaler to the Highest Divider */
+    LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_16);
+    LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_16);
+    LL_RCC_SetAPB3Prescaler(LL_RCC_APB3_DIV_16);
+    LL_RCC_SetAPB4Prescaler(LL_RCC_APB4_DIV_16);
+
+    /* Set SYS prescaler*/
+    LL_RCC_SetSysPrescaler(UTILS_ClkInitStruct->SYSCLKDivider);
+
+    /* Set AHB prescaler*/
+    LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
+
+    /* Sysclk activation on the main PLL */
+    LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL1);
+    while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL1)
+    {
+      /* Wait for system clock switch to PLL */
+    }
+
+    /* Set APBn prescaler*/
+    LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
+    LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
+    LL_RCC_SetAPB3Prescaler(UTILS_ClkInitStruct->APB3CLKDivider);
+    LL_RCC_SetAPB4Prescaler(UTILS_ClkInitStruct->APB4CLKDivider);
+
+    /* Decreasing the number of wait states because of lower CPU frequency */
+    if (SystemD2Clock > new_hclk_frequency)
+    {
+      /* Set FLASH latency to lowest latency */
+      status = LL_SetFlashLatency(new_hclk_frequency);
+    }
+
+    /* Update the SystemD2Clock global variable */
+#if defined(RCC_D1CFGR_HPRE)
+    SystemD2Clock = (SYSCLK_Frequency >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+#else
+    SystemD2Clock = (SYSCLK_Frequency >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+#endif
+
+    /* Update SystemCoreClock variable */
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+    LL_SetSystemCoreClock(SystemD2Clock);
+#else
+    LL_SetSystemCoreClock(SYSCLK_Frequency);
+#endif /* DUAL_CORE && CORE_CM4 */
+
+  }
+
+
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32_USB_Device_Library/Core/Inc/usbd_core.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32_USB_Device_Library/Core/Inc/usbd_core.h
new file mode 100644
index 00000000..030927b3
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32_USB_Device_Library/Core/Inc/usbd_core.h
@@ -0,0 +1,161 @@
+/**
+  ******************************************************************************
+  * @file    usbd_core.h
+  * @author  MCD Application Team
+  * @brief   Header file for usbd_core.c file
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USBD_CORE_H
+#define __USBD_CORE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbd_conf.h"
+#include "usbd_def.h"
+#include "usbd_ioreq.h"
+#include "usbd_ctlreq.h"
+
+/** @addtogroup STM32_USB_DEVICE_LIBRARY
+  * @{
+  */
+
+/** @defgroup USBD_CORE
+  * @brief This file is the Header file for usbd_core.c file
+  * @{
+  */
+
+
+/** @defgroup USBD_CORE_Exported_Defines
+  * @{
+  */
+#ifndef USBD_DEBUG_LEVEL
+#define USBD_DEBUG_LEVEL           0U
+#endif /* USBD_DEBUG_LEVEL */
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_CORE_Exported_TypesDefinitions
+  * @{
+  */
+
+
+/**
+  * @}
+  */
+
+
+
+/** @defgroup USBD_CORE_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_CORE_Exported_Variables
+  * @{
+  */
+#define USBD_SOF          USBD_LL_SOF
+/**
+  * @}
+  */
+
+/** @defgroup USBD_CORE_Exported_FunctionsPrototype
+  * @{
+  */
+USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id);
+USBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev);
+USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev);
+USBD_StatusTypeDef USBD_Stop(USBD_HandleTypeDef *pdev);
+USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass);
+
+USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef  *pdev);
+USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef  *pdev, uint8_t cfgidx);
+USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef  *pdev, uint8_t cfgidx);
+
+USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup);
+USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata);
+USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata);
+
+USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef  *pdev);
+USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef  *pdev, USBD_SpeedTypeDef speed);
+USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef  *pdev);
+USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef  *pdev);
+
+USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef  *pdev);
+USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef  *pdev, uint8_t epnum);
+USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef  *pdev, uint8_t epnum);
+
+USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef  *pdev);
+USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef  *pdev);
+
+/* USBD Low Level Driver */
+USBD_StatusTypeDef  USBD_LL_Init(USBD_HandleTypeDef *pdev);
+USBD_StatusTypeDef  USBD_LL_DeInit(USBD_HandleTypeDef *pdev);
+USBD_StatusTypeDef  USBD_LL_Start(USBD_HandleTypeDef *pdev);
+USBD_StatusTypeDef  USBD_LL_Stop(USBD_HandleTypeDef *pdev);
+USBD_StatusTypeDef  USBD_LL_OpenEP(USBD_HandleTypeDef *pdev,
+                                   uint8_t  ep_addr,
+                                   uint8_t  ep_type,
+                                   uint16_t ep_mps);
+
+USBD_StatusTypeDef  USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
+USBD_StatusTypeDef  USBD_LL_FlushEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
+USBD_StatusTypeDef  USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
+USBD_StatusTypeDef  USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
+uint8_t             USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
+USBD_StatusTypeDef  USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr);
+USBD_StatusTypeDef  USBD_LL_Transmit(USBD_HandleTypeDef *pdev,
+                                     uint8_t  ep_addr,
+                                     uint8_t  *pbuf,
+                                     uint16_t  size);
+
+USBD_StatusTypeDef  USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev,
+                                           uint8_t  ep_addr,
+                                           uint8_t  *pbuf,
+                                           uint16_t  size);
+
+uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t  ep_addr);
+void  USBD_LL_Delay(uint32_t Delay);
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USBD_CORE_H */
+
+/**
+  * @}
+  */
+
+/**
+* @}
+*/
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
+
+
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h
new file mode 100644
index 00000000..25a47582
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h
@@ -0,0 +1,105 @@
+/**
+  ******************************************************************************
+  * @file    usbd_req.h
+  * @author  MCD Application Team
+  * @brief   Header file for the usbd_req.c file
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_REQUEST_H
+#define __USB_REQUEST_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include  "usbd_def.h"
+
+
+/** @addtogroup STM32_USB_DEVICE_LIBRARY
+  * @{
+  */
+
+/** @defgroup USBD_REQ
+  * @brief header file for the usbd_req.c file
+  * @{
+  */
+
+/** @defgroup USBD_REQ_Exported_Defines
+  * @{
+  */
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_REQ_Exported_Types
+  * @{
+  */
+/**
+  * @}
+  */
+
+
+
+/** @defgroup USBD_REQ_Exported_Macros
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup USBD_REQ_Exported_Variables
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup USBD_REQ_Exported_FunctionsPrototype
+  * @{
+  */
+
+USBD_StatusTypeDef  USBD_StdDevReq(USBD_HandleTypeDef  *pdev, USBD_SetupReqTypedef  *req);
+USBD_StatusTypeDef  USBD_StdItfReq(USBD_HandleTypeDef  *pdev, USBD_SetupReqTypedef  *req);
+USBD_StatusTypeDef  USBD_StdEPReq(USBD_HandleTypeDef  *pdev, USBD_SetupReqTypedef  *req);
+
+
+void USBD_CtlError(USBD_HandleTypeDef  *pdev, USBD_SetupReqTypedef *req);
+
+void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata);
+
+void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len);
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USB_REQUEST_H */
+
+/**
+  * @}
+  */
+
+/**
+* @}
+*/
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32_USB_Device_Library/Core/Inc/usbd_def.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32_USB_Device_Library/Core/Inc/usbd_def.h
new file mode 100644
index 00000000..8d7502f3
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32_USB_Device_Library/Core/Inc/usbd_def.h
@@ -0,0 +1,348 @@
+/**
+  ******************************************************************************
+  * @file    usbd_def.h
+  * @author  MCD Application Team
+  * @brief   General defines for the usb device library
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USBD_DEF_H
+#define __USBD_DEF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbd_conf.h"
+
+/** @addtogroup STM32_USBD_DEVICE_LIBRARY
+  * @{
+  */
+
+/** @defgroup USB_DEF
+  * @brief general defines for the usb device library file
+  * @{
+  */
+
+/** @defgroup USB_DEF_Exported_Defines
+  * @{
+  */
+
+#ifndef NULL
+#define NULL                                            0U
+#endif /* NULL */
+
+#ifndef USBD_MAX_NUM_INTERFACES
+#define USBD_MAX_NUM_INTERFACES                         1U
+#endif /* USBD_MAX_NUM_CONFIGURATION */
+
+#ifndef USBD_MAX_NUM_CONFIGURATION
+#define USBD_MAX_NUM_CONFIGURATION                      1U
+#endif /* USBD_MAX_NUM_CONFIGURATION */
+
+#ifndef USBD_LPM_ENABLED
+#define USBD_LPM_ENABLED                                0U
+#endif /* USBD_LPM_ENABLED */
+
+#ifndef USBD_SELF_POWERED
+#define USBD_SELF_POWERED                               1U
+#endif /*USBD_SELF_POWERED */
+
+#ifndef USBD_SUPPORT_USER_STRING_DESC
+#define USBD_SUPPORT_USER_STRING_DESC                   0U
+#endif /* USBD_SUPPORT_USER_STRING_DESC */
+
+#define  USB_LEN_DEV_QUALIFIER_DESC                     0x0AU
+#define  USB_LEN_DEV_DESC                               0x12U
+#define  USB_LEN_CFG_DESC                               0x09U
+#define  USB_LEN_IF_DESC                                0x09U
+#define  USB_LEN_EP_DESC                                0x07U
+#define  USB_LEN_OTG_DESC                               0x03U
+#define  USB_LEN_LANGID_STR_DESC                        0x04U
+#define  USB_LEN_OTHER_SPEED_DESC_SIZ                   0x09U
+
+#define  USBD_IDX_LANGID_STR                            0x00U
+#define  USBD_IDX_MFC_STR                               0x01U
+#define  USBD_IDX_PRODUCT_STR                           0x02U
+#define  USBD_IDX_SERIAL_STR                            0x03U
+#define  USBD_IDX_CONFIG_STR                            0x04U
+#define  USBD_IDX_INTERFACE_STR                         0x05U
+
+#define  USB_REQ_TYPE_STANDARD                          0x00U
+#define  USB_REQ_TYPE_CLASS                             0x20U
+#define  USB_REQ_TYPE_VENDOR                            0x40U
+#define  USB_REQ_TYPE_MASK                              0x60U
+
+#define  USB_REQ_RECIPIENT_DEVICE                       0x00U
+#define  USB_REQ_RECIPIENT_INTERFACE                    0x01U
+#define  USB_REQ_RECIPIENT_ENDPOINT                     0x02U
+#define  USB_REQ_RECIPIENT_MASK                         0x03U
+
+#define  USB_REQ_GET_STATUS                             0x00U
+#define  USB_REQ_CLEAR_FEATURE                          0x01U
+#define  USB_REQ_SET_FEATURE                            0x03U
+#define  USB_REQ_SET_ADDRESS                            0x05U
+#define  USB_REQ_GET_DESCRIPTOR                         0x06U
+#define  USB_REQ_SET_DESCRIPTOR                         0x07U
+#define  USB_REQ_GET_CONFIGURATION                      0x08U
+#define  USB_REQ_SET_CONFIGURATION                      0x09U
+#define  USB_REQ_GET_INTERFACE                          0x0AU
+#define  USB_REQ_SET_INTERFACE                          0x0BU
+#define  USB_REQ_SYNCH_FRAME                            0x0CU
+
+#define  USB_DESC_TYPE_DEVICE                           0x01U
+#define  USB_DESC_TYPE_CONFIGURATION                    0x02U
+#define  USB_DESC_TYPE_STRING                           0x03U
+#define  USB_DESC_TYPE_INTERFACE                        0x04U
+#define  USB_DESC_TYPE_ENDPOINT                         0x05U
+#define  USB_DESC_TYPE_DEVICE_QUALIFIER                 0x06U
+#define  USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION        0x07U
+#define  USB_DESC_TYPE_BOS                              0x0FU
+
+#define USB_CONFIG_REMOTE_WAKEUP                        0x02U
+#define USB_CONFIG_SELF_POWERED                         0x01U
+
+#define USB_FEATURE_EP_HALT                             0x00U
+#define USB_FEATURE_REMOTE_WAKEUP                       0x01U
+#define USB_FEATURE_TEST_MODE                           0x02U
+
+#define USB_DEVICE_CAPABITY_TYPE                        0x10U
+
+#define USB_HS_MAX_PACKET_SIZE                          512U
+#define USB_FS_MAX_PACKET_SIZE                          64U
+#define USB_MAX_EP0_SIZE                                64U
+
+/*  Device Status */
+#define USBD_STATE_DEFAULT                              0x01U
+#define USBD_STATE_ADDRESSED                            0x02U
+#define USBD_STATE_CONFIGURED                           0x03U
+#define USBD_STATE_SUSPENDED                            0x04U
+
+
+/*  EP0 State */
+#define USBD_EP0_IDLE                                   0x00U
+#define USBD_EP0_SETUP                                  0x01U
+#define USBD_EP0_DATA_IN                                0x02U
+#define USBD_EP0_DATA_OUT                               0x03U
+#define USBD_EP0_STATUS_IN                              0x04U
+#define USBD_EP0_STATUS_OUT                             0x05U
+#define USBD_EP0_STALL                                  0x06U
+
+#define USBD_EP_TYPE_CTRL                               0x00U
+#define USBD_EP_TYPE_ISOC                               0x01U
+#define USBD_EP_TYPE_BULK                               0x02U
+#define USBD_EP_TYPE_INTR                               0x03U
+
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_DEF_Exported_TypesDefinitions
+  * @{
+  */
+
+typedef  struct  usb_setup_req
+{
+  uint8_t   bmRequest;
+  uint8_t   bRequest;
+  uint16_t  wValue;
+  uint16_t  wIndex;
+  uint16_t  wLength;
+} USBD_SetupReqTypedef;
+
+struct _USBD_HandleTypeDef;
+
+typedef struct _Device_cb
+{
+  uint8_t (*Init)(struct _USBD_HandleTypeDef *pdev, uint8_t cfgidx);
+  uint8_t (*DeInit)(struct _USBD_HandleTypeDef *pdev, uint8_t cfgidx);
+  /* Control Endpoints*/
+  uint8_t (*Setup)(struct _USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef  *req);
+  uint8_t (*EP0_TxSent)(struct _USBD_HandleTypeDef *pdev);
+  uint8_t (*EP0_RxReady)(struct _USBD_HandleTypeDef *pdev);
+  /* Class Specific Endpoints*/
+  uint8_t (*DataIn)(struct _USBD_HandleTypeDef *pdev, uint8_t epnum);
+  uint8_t (*DataOut)(struct _USBD_HandleTypeDef *pdev, uint8_t epnum);
+  uint8_t (*SOF)(struct _USBD_HandleTypeDef *pdev);
+  uint8_t (*IsoINIncomplete)(struct _USBD_HandleTypeDef *pdev, uint8_t epnum);
+  uint8_t (*IsoOUTIncomplete)(struct _USBD_HandleTypeDef *pdev, uint8_t epnum);
+
+  uint8_t  *(*GetHSConfigDescriptor)(uint16_t *length);
+  uint8_t  *(*GetFSConfigDescriptor)(uint16_t *length);
+  uint8_t  *(*GetOtherSpeedConfigDescriptor)(uint16_t *length);
+  uint8_t  *(*GetDeviceQualifierDescriptor)(uint16_t *length);
+#if (USBD_SUPPORT_USER_STRING_DESC == 1U)
+  uint8_t  *(*GetUsrStrDescriptor)(struct _USBD_HandleTypeDef *pdev, uint8_t index,  uint16_t *length);
+#endif
+
+} USBD_ClassTypeDef;
+
+/* Following USB Device Speed */
+typedef enum
+{
+  USBD_SPEED_HIGH  = 0U,
+  USBD_SPEED_FULL  = 1U,
+  USBD_SPEED_LOW   = 2U,
+} USBD_SpeedTypeDef;
+
+/* Following USB Device status */
+typedef enum
+{
+  USBD_OK   = 0U,
+  USBD_BUSY,
+  USBD_FAIL,
+} USBD_StatusTypeDef;
+
+/* USB Device descriptors structure */
+typedef struct
+{
+  uint8_t  *(*GetDeviceDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
+  uint8_t  *(*GetLangIDStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
+  uint8_t  *(*GetManufacturerStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
+  uint8_t  *(*GetProductStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
+  uint8_t  *(*GetSerialStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
+  uint8_t  *(*GetConfigurationStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
+  uint8_t  *(*GetInterfaceStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
+#if (USBD_LPM_ENABLED == 1U)
+  uint8_t  *(*GetBOSDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
+#endif
+} USBD_DescriptorsTypeDef;
+
+/* USB Device handle structure */
+typedef struct
+{
+  uint32_t                status;
+  uint32_t                is_used;
+  uint32_t                total_length;
+  uint32_t                rem_length;
+  uint32_t                maxpacket;
+} USBD_EndpointTypeDef;
+
+/* USB Device handle structure */
+typedef struct _USBD_HandleTypeDef
+{
+  uint8_t                 id;
+  uint32_t                dev_config;
+  uint32_t                dev_default_config;
+  uint32_t                dev_config_status;
+  USBD_SpeedTypeDef       dev_speed;
+  USBD_EndpointTypeDef    ep_in[16];
+  USBD_EndpointTypeDef    ep_out[16];
+  uint32_t                ep0_state;
+  uint32_t                ep0_data_len;
+  uint8_t                 dev_state;
+  uint8_t                 dev_old_state;
+  uint8_t                 dev_address;
+  uint8_t                 dev_connection_status;
+  uint8_t                 dev_test_mode;
+  uint32_t                dev_remote_wakeup;
+
+  USBD_SetupReqTypedef    request;
+  USBD_DescriptorsTypeDef *pDesc;
+  USBD_ClassTypeDef       *pClass;
+  void                    *pClassData;
+  void                    *pUserData;
+  void                    *pData;
+} USBD_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+
+
+/** @defgroup USBD_DEF_Exported_Macros
+  * @{
+  */
+#define  SWAPBYTE(addr)        (((uint16_t)(*((uint8_t *)(addr)))) + \
+                               (((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U))
+
+#define LOBYTE(x)  ((uint8_t)((x) & 0x00FFU))
+#define HIBYTE(x)  ((uint8_t)(((x) & 0xFF00U) >> 8U))
+#define MIN(a, b)  (((a) < (b)) ? (a) : (b))
+#define MAX(a, b)  (((a) > (b)) ? (a) : (b))
+
+
+#if  defined ( __GNUC__ )
+#ifndef __weak
+#define __weak   __attribute__((weak))
+#endif /* __weak */
+#ifndef __packed
+#define __packed __attribute__((__packed__))
+#endif /* __packed */
+#endif /* __GNUC__ */
+
+
+/* In HS mode and when the DMA is used, all variables and data structures dealing
+   with the DMA during the transaction process should be 4-bytes aligned */
+
+#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
+#ifndef __ALIGN_END
+#define __ALIGN_END    __attribute__ ((aligned (4U)))
+#endif /* __ALIGN_END */
+#ifndef __ALIGN_BEGIN
+#define __ALIGN_BEGIN
+#endif /* __ALIGN_BEGIN */
+#else
+#ifndef __ALIGN_END
+#define __ALIGN_END
+#endif /* __ALIGN_END */
+#ifndef __ALIGN_BEGIN
+#if defined   (__CC_ARM)      /* ARM Compiler */
+#define __ALIGN_BEGIN    __align(4U)
+#elif defined (__ICCARM__)    /* IAR Compiler */
+#define __ALIGN_BEGIN
+#endif /* __CC_ARM */
+#endif /* __ALIGN_BEGIN */
+#endif /* __GNUC__ */
+
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DEF_Exported_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DEF_Exported_FunctionsPrototype
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USBD_DEF_H */
+
+/**
+  * @}
+  */
+
+/**
+* @}
+*/
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h
new file mode 100644
index 00000000..8a6dd5f7
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h
@@ -0,0 +1,119 @@
+/**
+  ******************************************************************************
+  * @file    usbd_ioreq.h
+  * @author  MCD Application Team
+  * @brief   Header file for the usbd_ioreq.c file
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USBD_IOREQ_H
+#define __USBD_IOREQ_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include  "usbd_def.h"
+#include  "usbd_core.h"
+
+/** @addtogroup STM32_USB_DEVICE_LIBRARY
+  * @{
+  */
+
+/** @defgroup USBD_IOREQ
+  * @brief header file for the usbd_ioreq.c file
+  * @{
+  */
+
+/** @defgroup USBD_IOREQ_Exported_Defines
+  * @{
+  */
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_IOREQ_Exported_Types
+  * @{
+  */
+
+
+/**
+  * @}
+  */
+
+
+
+/** @defgroup USBD_IOREQ_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_IOREQ_Exported_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_IOREQ_Exported_FunctionsPrototype
+  * @{
+  */
+
+USBD_StatusTypeDef  USBD_CtlSendData(USBD_HandleTypeDef *pdev,
+                                     uint8_t *pbuf,
+                                     uint16_t len);
+
+USBD_StatusTypeDef  USBD_CtlContinueSendData(USBD_HandleTypeDef  *pdev,
+                                             uint8_t *pbuf,
+                                             uint16_t len);
+
+USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef  *pdev,
+                                     uint8_t *pbuf,
+                                     uint16_t len);
+
+USBD_StatusTypeDef  USBD_CtlContinueRx(USBD_HandleTypeDef  *pdev,
+                                       uint8_t *pbuf,
+                                       uint16_t len);
+
+USBD_StatusTypeDef  USBD_CtlSendStatus(USBD_HandleTypeDef  *pdev);
+
+USBD_StatusTypeDef  USBD_CtlReceiveStatus(USBD_HandleTypeDef  *pdev);
+
+uint32_t  USBD_GetRxCount(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USBD_IOREQ_H */
+
+/**
+  * @}
+  */
+
+/**
+* @}
+*/
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32_USB_Device_Library/Core/Src/usbd_core.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32_USB_Device_Library/Core/Src/usbd_core.c
new file mode 100644
index 00000000..b1a60ae2
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32_USB_Device_Library/Core/Src/usbd_core.c
@@ -0,0 +1,611 @@
+/**
+  ******************************************************************************
+  * @file    usbd_core.c
+  * @author  MCD Application Team
+  * @brief   This file provides all the USBD core functions.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbd_core.h"
+
+/** @addtogroup STM32_USBD_DEVICE_LIBRARY
+* @{
+*/
+
+
+/** @defgroup USBD_CORE
+* @brief usbd core module
+* @{
+*/
+
+/** @defgroup USBD_CORE_Private_TypesDefinitions
+* @{
+*/
+
+/**
+* @}
+*/
+
+
+/** @defgroup USBD_CORE_Private_Defines
+* @{
+*/
+
+/**
+* @}
+*/
+
+
+/** @defgroup USBD_CORE_Private_Macros
+* @{
+*/
+
+/**
+* @}
+*/
+
+
+/** @defgroup USBD_CORE_Private_FunctionPrototypes
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup USBD_CORE_Private_Variables
+* @{
+*/
+
+/**
+* @}
+*/
+
+
+/** @defgroup USBD_CORE_Private_Functions
+* @{
+*/
+
+/**
+* @brief  USBD_Init
+*         Initializes the device stack and load the class driver
+* @param  pdev: device instance
+* @param  pdesc: Descriptor structure address
+* @param  id: Low level core index
+* @retval None
+*/
+USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev,
+                             USBD_DescriptorsTypeDef *pdesc, uint8_t id)
+{
+  /* Check whether the USB Host handle is valid */
+  if (pdev == NULL)
+  {
+#if (USBD_DEBUG_LEVEL > 1U)
+    USBD_ErrLog("Invalid Device handle");
+#endif
+    return USBD_FAIL;
+  }
+
+  /* Unlink previous class*/
+  if (pdev->pClass != NULL)
+  {
+    pdev->pClass = NULL;
+  }
+
+  /* Assign USBD Descriptors */
+  if (pdesc != NULL)
+  {
+    pdev->pDesc = pdesc;
+  }
+
+  /* Set Device initial State */
+  pdev->dev_state = USBD_STATE_DEFAULT;
+  pdev->id = id;
+  /* Initialize low level driver */
+  USBD_LL_Init(pdev);
+
+  return USBD_OK;
+}
+
+/**
+* @brief  USBD_DeInit
+*         Re-Initialize th device library
+* @param  pdev: device instance
+* @retval status: status
+*/
+USBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev)
+{
+  /* Set Default State */
+  pdev->dev_state = USBD_STATE_DEFAULT;
+
+  /* Free Class Resources */
+  pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config);
+
+  /* Stop the low level driver  */
+  USBD_LL_Stop(pdev);
+
+  /* Initialize low level driver */
+  USBD_LL_DeInit(pdev);
+
+  return USBD_OK;
+}
+
+/**
+  * @brief  USBD_RegisterClass
+  *         Link class driver to Device Core.
+  * @param  pDevice : Device Handle
+  * @param  pclass: Class handle
+  * @retval USBD Status
+  */
+USBD_StatusTypeDef  USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass)
+{
+  USBD_StatusTypeDef status = USBD_OK;
+  if (pclass != NULL)
+  {
+    /* link the class to the USB Device handle */
+    pdev->pClass = pclass;
+    status = USBD_OK;
+  }
+  else
+  {
+#if (USBD_DEBUG_LEVEL > 1U)
+    USBD_ErrLog("Invalid Class handle");
+#endif
+    status = USBD_FAIL;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  USBD_Start
+  *         Start the USB Device Core.
+  * @param  pdev: Device Handle
+  * @retval USBD Status
+  */
+USBD_StatusTypeDef  USBD_Start(USBD_HandleTypeDef *pdev)
+{
+  /* Start the low level driver  */
+  USBD_LL_Start(pdev);
+
+  return USBD_OK;
+}
+
+/**
+  * @brief  USBD_Stop
+  *         Stop the USB Device Core.
+  * @param  pdev: Device Handle
+  * @retval USBD Status
+  */
+USBD_StatusTypeDef  USBD_Stop(USBD_HandleTypeDef *pdev)
+{
+  /* Free Class Resources */
+  pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config);
+
+  /* Stop the low level driver */
+  USBD_LL_Stop(pdev);
+
+  return USBD_OK;
+}
+
+/**
+* @brief  USBD_RunTestMode
+*         Launch test mode process
+* @param  pdev: device instance
+* @retval status
+*/
+USBD_StatusTypeDef  USBD_RunTestMode(USBD_HandleTypeDef  *pdev)
+{
+  /* Prevent unused argument compilation warning */
+  UNUSED(pdev);
+
+  return USBD_OK;
+}
+
+/**
+* @brief  USBD_SetClassConfig
+*        Configure device and start the interface
+* @param  pdev: device instance
+* @param  cfgidx: configuration index
+* @retval status
+*/
+
+USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef  *pdev, uint8_t cfgidx)
+{
+  USBD_StatusTypeDef ret = USBD_FAIL;
+
+  if (pdev->pClass != NULL)
+  {
+    /* Set configuration  and Start the Class*/
+    if (pdev->pClass->Init(pdev, cfgidx) == 0U)
+    {
+      ret = USBD_OK;
+    }
+  }
+
+  return ret;
+}
+
+/**
+* @brief  USBD_ClrClassConfig
+*         Clear current configuration
+* @param  pdev: device instance
+* @param  cfgidx: configuration index
+* @retval status: USBD_StatusTypeDef
+*/
+USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef  *pdev, uint8_t cfgidx)
+{
+  /* Clear configuration  and De-initialize the Class process*/
+  pdev->pClass->DeInit(pdev, cfgidx);
+
+  return USBD_OK;
+}
+
+
+/**
+* @brief  USBD_SetupStage
+*         Handle the setup stage
+* @param  pdev: device instance
+* @retval status
+*/
+USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup)
+{
+  USBD_ParseSetupRequest(&pdev->request, psetup);
+
+  pdev->ep0_state = USBD_EP0_SETUP;
+
+  pdev->ep0_data_len = pdev->request.wLength;
+
+  switch (pdev->request.bmRequest & 0x1FU)
+  {
+    case USB_REQ_RECIPIENT_DEVICE:
+      USBD_StdDevReq(pdev, &pdev->request);
+      break;
+
+    case USB_REQ_RECIPIENT_INTERFACE:
+      USBD_StdItfReq(pdev, &pdev->request);
+      break;
+
+    case USB_REQ_RECIPIENT_ENDPOINT:
+      USBD_StdEPReq(pdev, &pdev->request);
+      break;
+
+    default:
+      USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U));
+      break;
+  }
+
+  return USBD_OK;
+}
+
+/**
+* @brief  USBD_DataOutStage
+*         Handle data OUT stage
+* @param  pdev: device instance
+* @param  epnum: endpoint index
+* @retval status
+*/
+USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev,
+                                        uint8_t epnum, uint8_t *pdata)
+{
+  USBD_EndpointTypeDef *pep;
+
+  if (epnum == 0U)
+  {
+    pep = &pdev->ep_out[0];
+
+    if (pdev->ep0_state == USBD_EP0_DATA_OUT)
+    {
+      if (pep->rem_length > pep->maxpacket)
+      {
+        pep->rem_length -= pep->maxpacket;
+
+        USBD_CtlContinueRx(pdev, pdata,
+                           (uint16_t)MIN(pep->rem_length, pep->maxpacket));
+      }
+      else
+      {
+        if ((pdev->pClass->EP0_RxReady != NULL) &&
+            (pdev->dev_state == USBD_STATE_CONFIGURED))
+        {
+          pdev->pClass->EP0_RxReady(pdev);
+        }
+        USBD_CtlSendStatus(pdev);
+      }
+    }
+    else
+    {
+      if (pdev->ep0_state == USBD_EP0_STATUS_OUT)
+      {
+        /*
+         * STATUS PHASE completed, update ep0_state to idle
+         */
+        pdev->ep0_state = USBD_EP0_IDLE;
+        USBD_LL_StallEP(pdev, 0U);
+      }
+    }
+  }
+  else if ((pdev->pClass->DataOut != NULL) &&
+           (pdev->dev_state == USBD_STATE_CONFIGURED))
+  {
+    pdev->pClass->DataOut(pdev, epnum);
+  }
+  else
+  {
+    /* should never be in this condition */
+    return USBD_FAIL;
+  }
+
+  return USBD_OK;
+}
+
+/**
+* @brief  USBD_DataInStage
+*         Handle data in stage
+* @param  pdev: device instance
+* @param  epnum: endpoint index
+* @retval status
+*/
+USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev,
+                                       uint8_t epnum, uint8_t *pdata)
+{
+  USBD_EndpointTypeDef *pep;
+
+  if (epnum == 0U)
+  {
+    pep = &pdev->ep_in[0];
+
+    if (pdev->ep0_state == USBD_EP0_DATA_IN)
+    {
+      if (pep->rem_length > pep->maxpacket)
+      {
+        pep->rem_length -= pep->maxpacket;
+
+        USBD_CtlContinueSendData(pdev, pdata, (uint16_t)pep->rem_length);
+
+        /* Prepare endpoint for premature end of transfer */
+        USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
+      }
+      else
+      {
+        /* last packet is MPS multiple, so send ZLP packet */
+        if ((pep->total_length % pep->maxpacket == 0U) &&
+            (pep->total_length >= pep->maxpacket) &&
+            (pep->total_length < pdev->ep0_data_len))
+        {
+          USBD_CtlContinueSendData(pdev, NULL, 0U);
+          pdev->ep0_data_len = 0U;
+
+          /* Prepare endpoint for premature end of transfer */
+          USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
+        }
+        else
+        {
+          if ((pdev->pClass->EP0_TxSent != NULL) &&
+              (pdev->dev_state == USBD_STATE_CONFIGURED))
+          {
+            pdev->pClass->EP0_TxSent(pdev);
+          }
+          USBD_LL_StallEP(pdev, 0x80U);
+          USBD_CtlReceiveStatus(pdev);
+        }
+      }
+    }
+    else
+    {
+      if ((pdev->ep0_state == USBD_EP0_STATUS_IN) ||
+          (pdev->ep0_state == USBD_EP0_IDLE))
+      {
+        USBD_LL_StallEP(pdev, 0x80U);
+      }
+    }
+
+    if (pdev->dev_test_mode == 1U)
+    {
+      USBD_RunTestMode(pdev);
+      pdev->dev_test_mode = 0U;
+    }
+  }
+  else if ((pdev->pClass->DataIn != NULL) &&
+           (pdev->dev_state == USBD_STATE_CONFIGURED))
+  {
+    pdev->pClass->DataIn(pdev, epnum);
+  }
+  else
+  {
+    /* should never be in this condition */
+    return USBD_FAIL;
+  }
+
+  return USBD_OK;
+}
+
+/**
+* @brief  USBD_LL_Reset
+*         Handle Reset event
+* @param  pdev: device instance
+* @retval status
+*/
+
+USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev)
+{
+  /* Open EP0 OUT */
+  USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
+  pdev->ep_out[0x00U & 0xFU].is_used = 1U;
+
+  pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE;
+
+  /* Open EP0 IN */
+  USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
+  pdev->ep_in[0x80U & 0xFU].is_used = 1U;
+
+  pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE;
+
+  /* Upon Reset call user call back */
+  pdev->dev_state = USBD_STATE_DEFAULT;
+  pdev->ep0_state = USBD_EP0_IDLE;
+  pdev->dev_config = 0U;
+  pdev->dev_remote_wakeup = 0U;
+
+  if (pdev->pClassData)
+  {
+    pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config);
+  }
+
+  return USBD_OK;
+}
+
+/**
+* @brief  USBD_LL_Reset
+*         Handle Reset event
+* @param  pdev: device instance
+* @retval status
+*/
+USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev,
+                                    USBD_SpeedTypeDef speed)
+{
+  pdev->dev_speed = speed;
+
+  return USBD_OK;
+}
+
+/**
+* @brief  USBD_Suspend
+*         Handle Suspend event
+* @param  pdev: device instance
+* @retval status
+*/
+
+USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev)
+{
+  pdev->dev_old_state =  pdev->dev_state;
+  pdev->dev_state  = USBD_STATE_SUSPENDED;
+
+  return USBD_OK;
+}
+
+/**
+* @brief  USBD_Resume
+*         Handle Resume event
+* @param  pdev: device instance
+* @retval status
+*/
+
+USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev)
+{
+  if (pdev->dev_state == USBD_STATE_SUSPENDED)
+  {
+    pdev->dev_state = pdev->dev_old_state;
+  }
+
+  return USBD_OK;
+}
+
+/**
+* @brief  USBD_SOF
+*         Handle SOF event
+* @param  pdev: device instance
+* @retval status
+*/
+
+USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev)
+{
+  if (pdev->dev_state == USBD_STATE_CONFIGURED)
+  {
+    if (pdev->pClass->SOF != NULL)
+    {
+      pdev->pClass->SOF(pdev);
+    }
+  }
+
+  return USBD_OK;
+}
+
+/**
+* @brief  USBD_IsoINIncomplete
+*         Handle iso in incomplete event
+* @param  pdev: device instance
+* @retval status
+*/
+USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev,
+                                           uint8_t epnum)
+{
+  /* Prevent unused arguments compilation warning */
+  UNUSED(pdev);
+  UNUSED(epnum);
+
+  return USBD_OK;
+}
+
+/**
+* @brief  USBD_IsoOUTIncomplete
+*         Handle iso out incomplete event
+* @param  pdev: device instance
+* @retval status
+*/
+USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev,
+                                            uint8_t epnum)
+{
+  /* Prevent unused arguments compilation warning */
+  UNUSED(pdev);
+  UNUSED(epnum);
+
+  return USBD_OK;
+}
+
+/**
+* @brief  USBD_DevConnected
+*         Handle device connection event
+* @param  pdev: device instance
+* @retval status
+*/
+USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev)
+{
+  /* Prevent unused argument compilation warning */
+  UNUSED(pdev);
+
+  return USBD_OK;
+}
+
+/**
+* @brief  USBD_DevDisconnected
+*         Handle device disconnection event
+* @param  pdev: device instance
+* @retval status
+*/
+USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev)
+{
+  /* Free Class Resources */
+  pdev->dev_state = USBD_STATE_DEFAULT;
+  pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config);
+
+  return USBD_OK;
+}
+/**
+* @}
+*/
+
+
+/**
+* @}
+*/
+
+
+/**
+* @}
+*/
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c
new file mode 100644
index 00000000..e57c1bcd
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c
@@ -0,0 +1,918 @@
+/**
+  ******************************************************************************
+  * @file    usbd_req.c
+  * @author  MCD Application Team
+  * @brief   This file provides the standard USB requests following chapter 9.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbd_ctlreq.h"
+#include "usbd_ioreq.h"
+
+
+/** @addtogroup STM32_USBD_STATE_DEVICE_LIBRARY
+  * @{
+  */
+
+
+/** @defgroup USBD_REQ
+  * @brief USB standard requests module
+  * @{
+  */
+
+/** @defgroup USBD_REQ_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_REQ_Private_Defines
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_REQ_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_REQ_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_REQ_Private_FunctionPrototypes
+  * @{
+  */
+static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev,
+                               USBD_SetupReqTypedef *req);
+
+static void USBD_SetAddress(USBD_HandleTypeDef *pdev,
+                            USBD_SetupReqTypedef *req);
+
+static void USBD_SetConfig(USBD_HandleTypeDef *pdev,
+                           USBD_SetupReqTypedef *req);
+
+static void USBD_GetConfig(USBD_HandleTypeDef *pdev,
+                           USBD_SetupReqTypedef *req);
+
+static void USBD_GetStatus(USBD_HandleTypeDef *pdev,
+                           USBD_SetupReqTypedef *req);
+
+static void USBD_SetFeature(USBD_HandleTypeDef *pdev,
+                            USBD_SetupReqTypedef *req);
+
+static void USBD_ClrFeature(USBD_HandleTypeDef *pdev,
+                            USBD_SetupReqTypedef *req);
+
+static uint8_t USBD_GetLen(uint8_t *buf);
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_REQ_Private_Functions
+  * @{
+  */
+
+
+/**
+* @brief  USBD_StdDevReq
+*         Handle standard usb device requests
+* @param  pdev: device instance
+* @param  req: usb request
+* @retval status
+*/
+USBD_StatusTypeDef  USBD_StdDevReq(USBD_HandleTypeDef *pdev,
+                                   USBD_SetupReqTypedef *req)
+{
+  USBD_StatusTypeDef ret = USBD_OK;
+
+  switch (req->bmRequest & USB_REQ_TYPE_MASK)
+  {
+    case USB_REQ_TYPE_CLASS:
+    case USB_REQ_TYPE_VENDOR:
+      pdev->pClass->Setup(pdev, req);
+      break;
+
+    case USB_REQ_TYPE_STANDARD:
+      switch (req->bRequest)
+      {
+        case USB_REQ_GET_DESCRIPTOR:
+          USBD_GetDescriptor(pdev, req);
+          break;
+
+        case USB_REQ_SET_ADDRESS:
+          USBD_SetAddress(pdev, req);
+          break;
+
+        case USB_REQ_SET_CONFIGURATION:
+          USBD_SetConfig(pdev, req);
+          break;
+
+        case USB_REQ_GET_CONFIGURATION:
+          USBD_GetConfig(pdev, req);
+          break;
+
+        case USB_REQ_GET_STATUS:
+          USBD_GetStatus(pdev, req);
+          break;
+
+        case USB_REQ_SET_FEATURE:
+          USBD_SetFeature(pdev, req);
+          break;
+
+        case USB_REQ_CLEAR_FEATURE:
+          USBD_ClrFeature(pdev, req);
+          break;
+
+        default:
+          USBD_CtlError(pdev, req);
+          break;
+      }
+      break;
+
+    default:
+      USBD_CtlError(pdev, req);
+      break;
+  }
+
+  return ret;
+}
+
+/**
+* @brief  USBD_StdItfReq
+*         Handle standard usb interface requests
+* @param  pdev: device instance
+* @param  req: usb request
+* @retval status
+*/
+USBD_StatusTypeDef  USBD_StdItfReq(USBD_HandleTypeDef *pdev,
+                                   USBD_SetupReqTypedef  *req)
+{
+  USBD_StatusTypeDef ret = USBD_OK;
+
+  switch (req->bmRequest & USB_REQ_TYPE_MASK)
+  {
+    case USB_REQ_TYPE_CLASS:
+    case USB_REQ_TYPE_VENDOR:
+    case USB_REQ_TYPE_STANDARD:
+      switch (pdev->dev_state)
+      {
+        case USBD_STATE_DEFAULT:
+        case USBD_STATE_ADDRESSED:
+        case USBD_STATE_CONFIGURED:
+
+          if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES)
+          {
+            ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req);
+
+            if ((req->wLength == 0U) && (ret == USBD_OK))
+            {
+              USBD_CtlSendStatus(pdev);
+            }
+          }
+          else
+          {
+            USBD_CtlError(pdev, req);
+          }
+          break;
+
+        default:
+          USBD_CtlError(pdev, req);
+          break;
+      }
+      break;
+
+    default:
+      USBD_CtlError(pdev, req);
+      break;
+  }
+
+  return USBD_OK;
+}
+
+/**
+* @brief  USBD_StdEPReq
+*         Handle standard usb endpoint requests
+* @param  pdev: device instance
+* @param  req: usb request
+* @retval status
+*/
+USBD_StatusTypeDef  USBD_StdEPReq(USBD_HandleTypeDef *pdev,
+                                  USBD_SetupReqTypedef  *req)
+{
+  USBD_EndpointTypeDef *pep;
+  uint8_t   ep_addr;
+  USBD_StatusTypeDef ret = USBD_OK;
+  ep_addr  = LOBYTE(req->wIndex);
+
+  switch (req->bmRequest & USB_REQ_TYPE_MASK)
+  {
+    case USB_REQ_TYPE_CLASS:
+    case USB_REQ_TYPE_VENDOR:
+      pdev->pClass->Setup(pdev, req);
+      break;
+
+    case USB_REQ_TYPE_STANDARD:
+      /* Check if it is a class request */
+      if ((req->bmRequest & 0x60U) == 0x20U)
+      {
+        ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req);
+
+        return ret;
+      }
+
+      switch (req->bRequest)
+      {
+        case USB_REQ_SET_FEATURE:
+          switch (pdev->dev_state)
+          {
+            case USBD_STATE_ADDRESSED:
+              if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
+              {
+                USBD_LL_StallEP(pdev, ep_addr);
+                USBD_LL_StallEP(pdev, 0x80U);
+              }
+              else
+              {
+                USBD_CtlError(pdev, req);
+              }
+              break;
+
+            case USBD_STATE_CONFIGURED:
+              if (req->wValue == USB_FEATURE_EP_HALT)
+              {
+                if ((ep_addr != 0x00U) &&
+                    (ep_addr != 0x80U) && (req->wLength == 0x00U))
+                {
+                  USBD_LL_StallEP(pdev, ep_addr);
+                }
+              }
+              USBD_CtlSendStatus(pdev);
+
+              break;
+
+            default:
+              USBD_CtlError(pdev, req);
+              break;
+          }
+          break;
+
+        case USB_REQ_CLEAR_FEATURE:
+
+          switch (pdev->dev_state)
+          {
+            case USBD_STATE_ADDRESSED:
+              if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
+              {
+                USBD_LL_StallEP(pdev, ep_addr);
+                USBD_LL_StallEP(pdev, 0x80U);
+              }
+              else
+              {
+                USBD_CtlError(pdev, req);
+              }
+              break;
+
+            case USBD_STATE_CONFIGURED:
+              if (req->wValue == USB_FEATURE_EP_HALT)
+              {
+                if ((ep_addr & 0x7FU) != 0x00U)
+                {
+                  USBD_LL_ClearStallEP(pdev, ep_addr);
+                }
+                USBD_CtlSendStatus(pdev);
+              }
+              break;
+
+            default:
+              USBD_CtlError(pdev, req);
+              break;
+          }
+          break;
+
+        case USB_REQ_GET_STATUS:
+          switch (pdev->dev_state)
+          {
+            case USBD_STATE_ADDRESSED:
+              if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
+              {
+                USBD_CtlError(pdev, req);
+                break;
+              }
+              pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
+                    &pdev->ep_out[ep_addr & 0x7FU];
+
+              pep->status = 0x0000U;
+
+              USBD_CtlSendData(pdev, (uint8_t *)(void *)&pep->status, 2U);
+              break;
+
+            case USBD_STATE_CONFIGURED:
+              if ((ep_addr & 0x80U) == 0x80U)
+              {
+                if (pdev->ep_in[ep_addr & 0xFU].is_used == 0U)
+                {
+                  USBD_CtlError(pdev, req);
+                  break;
+                }
+              }
+              else
+              {
+                if (pdev->ep_out[ep_addr & 0xFU].is_used == 0U)
+                {
+                  USBD_CtlError(pdev, req);
+                  break;
+                }
+              }
+
+              pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
+                    &pdev->ep_out[ep_addr & 0x7FU];
+
+              if ((ep_addr == 0x00U) || (ep_addr == 0x80U))
+              {
+                pep->status = 0x0000U;
+              }
+              else if (USBD_LL_IsStallEP(pdev, ep_addr))
+              {
+                pep->status = 0x0001U;
+              }
+              else
+              {
+                pep->status = 0x0000U;
+              }
+
+              USBD_CtlSendData(pdev, (uint8_t *)(void *)&pep->status, 2U);
+              break;
+
+            default:
+              USBD_CtlError(pdev, req);
+              break;
+          }
+          break;
+
+        default:
+          USBD_CtlError(pdev, req);
+          break;
+      }
+      break;
+
+    default:
+      USBD_CtlError(pdev, req);
+      break;
+  }
+
+  return ret;
+}
+
+
+/**
+* @brief  USBD_GetDescriptor
+*         Handle Get Descriptor requests
+* @param  pdev: device instance
+* @param  req: usb request
+* @retval status
+*/
+static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev,
+                               USBD_SetupReqTypedef *req)
+{
+  uint16_t len = 0U;
+  uint8_t *pbuf = NULL;
+  uint8_t err = 0U;
+
+  switch (req->wValue >> 8)
+  {
+#if (USBD_LPM_ENABLED == 1U)
+    case USB_DESC_TYPE_BOS:
+      if (pdev->pDesc->GetBOSDescriptor != NULL)
+      {
+        pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len);
+      }
+      else
+      {
+        USBD_CtlError(pdev, req);
+        err++;
+      }
+      break;
+#endif
+    case USB_DESC_TYPE_DEVICE:
+      pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len);
+      break;
+
+    case USB_DESC_TYPE_CONFIGURATION:
+      if (pdev->dev_speed == USBD_SPEED_HIGH)
+      {
+        pbuf = pdev->pClass->GetHSConfigDescriptor(&len);
+        pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
+      }
+      else
+      {
+        pbuf = pdev->pClass->GetFSConfigDescriptor(&len);
+        pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
+      }
+      break;
+
+    case USB_DESC_TYPE_STRING:
+      switch ((uint8_t)(req->wValue))
+      {
+        case USBD_IDX_LANGID_STR:
+          if (pdev->pDesc->GetLangIDStrDescriptor != NULL)
+          {
+            pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len);
+          }
+          else
+          {
+            USBD_CtlError(pdev, req);
+            err++;
+          }
+          break;
+
+        case USBD_IDX_MFC_STR:
+          if (pdev->pDesc->GetManufacturerStrDescriptor != NULL)
+          {
+            pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len);
+          }
+          else
+          {
+            USBD_CtlError(pdev, req);
+            err++;
+          }
+          break;
+
+        case USBD_IDX_PRODUCT_STR:
+          if (pdev->pDesc->GetProductStrDescriptor != NULL)
+          {
+            pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len);
+          }
+          else
+          {
+            USBD_CtlError(pdev, req);
+            err++;
+          }
+          break;
+
+        case USBD_IDX_SERIAL_STR:
+          if (pdev->pDesc->GetSerialStrDescriptor != NULL)
+          {
+            pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len);
+          }
+          else
+          {
+            USBD_CtlError(pdev, req);
+            err++;
+          }
+          break;
+
+        case USBD_IDX_CONFIG_STR:
+          if (pdev->pDesc->GetConfigurationStrDescriptor != NULL)
+          {
+            pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len);
+          }
+          else
+          {
+            USBD_CtlError(pdev, req);
+            err++;
+          }
+          break;
+
+        case USBD_IDX_INTERFACE_STR:
+          if (pdev->pDesc->GetInterfaceStrDescriptor != NULL)
+          {
+            pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len);
+          }
+          else
+          {
+            USBD_CtlError(pdev, req);
+            err++;
+          }
+          break;
+
+        default:
+#if (USBD_SUPPORT_USER_STRING_DESC == 1U)
+          if (pdev->pClass->GetUsrStrDescriptor != NULL)
+          {
+            pbuf = pdev->pClass->GetUsrStrDescriptor(pdev, (req->wValue), &len);
+          }
+          else
+          {
+            USBD_CtlError(pdev, req);
+            err++;
+          }
+          break;
+#else
+          USBD_CtlError(pdev, req);
+          err++;
+#endif
+      }
+      break;
+
+    case USB_DESC_TYPE_DEVICE_QUALIFIER:
+      if (pdev->dev_speed == USBD_SPEED_HIGH)
+      {
+        pbuf = pdev->pClass->GetDeviceQualifierDescriptor(&len);
+      }
+      else
+      {
+        USBD_CtlError(pdev, req);
+        err++;
+      }
+      break;
+
+    case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION:
+      if (pdev->dev_speed == USBD_SPEED_HIGH)
+      {
+        pbuf = pdev->pClass->GetOtherSpeedConfigDescriptor(&len);
+        pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION;
+      }
+      else
+      {
+        USBD_CtlError(pdev, req);
+        err++;
+      }
+      break;
+
+    default:
+      USBD_CtlError(pdev, req);
+      err++;
+      break;
+  }
+
+  if (err != 0U)
+  {
+    return;
+  }
+  else
+  {
+    if ((len != 0U) && (req->wLength != 0U))
+    {
+      len = MIN(len, req->wLength);
+      (void)USBD_CtlSendData(pdev, pbuf, len);
+    }
+
+    if (req->wLength == 0U)
+    {
+      (void)USBD_CtlSendStatus(pdev);
+    }
+  }
+}
+
+/**
+* @brief  USBD_SetAddress
+*         Set device address
+* @param  pdev: device instance
+* @param  req: usb request
+* @retval status
+*/
+static void USBD_SetAddress(USBD_HandleTypeDef *pdev,
+                            USBD_SetupReqTypedef *req)
+{
+  uint8_t  dev_addr;
+
+  if ((req->wIndex == 0U) && (req->wLength == 0U) && (req->wValue < 128U))
+  {
+    dev_addr = (uint8_t)(req->wValue) & 0x7FU;
+
+    if (pdev->dev_state == USBD_STATE_CONFIGURED)
+    {
+      USBD_CtlError(pdev, req);
+    }
+    else
+    {
+      pdev->dev_address = dev_addr;
+      USBD_LL_SetUSBAddress(pdev, dev_addr);
+      USBD_CtlSendStatus(pdev);
+
+      if (dev_addr != 0U)
+      {
+        pdev->dev_state = USBD_STATE_ADDRESSED;
+      }
+      else
+      {
+        pdev->dev_state = USBD_STATE_DEFAULT;
+      }
+    }
+  }
+  else
+  {
+    USBD_CtlError(pdev, req);
+  }
+}
+
+/**
+* @brief  USBD_SetConfig
+*         Handle Set device configuration request
+* @param  pdev: device instance
+* @param  req: usb request
+* @retval status
+*/
+static void USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
+{
+  static uint8_t cfgidx;
+
+  cfgidx = (uint8_t)(req->wValue);
+
+  if (cfgidx > USBD_MAX_NUM_CONFIGURATION)
+  {
+    USBD_CtlError(pdev, req);
+  }
+  else
+  {
+    switch (pdev->dev_state)
+    {
+      case USBD_STATE_ADDRESSED:
+        if (cfgidx)
+        {
+          pdev->dev_config = cfgidx;
+          pdev->dev_state = USBD_STATE_CONFIGURED;
+          if (USBD_SetClassConfig(pdev, cfgidx) == USBD_FAIL)
+          {
+            USBD_CtlError(pdev, req);
+            return;
+          }
+          USBD_CtlSendStatus(pdev);
+        }
+        else
+        {
+          USBD_CtlSendStatus(pdev);
+        }
+        break;
+
+      case USBD_STATE_CONFIGURED:
+        if (cfgidx == 0U)
+        {
+          pdev->dev_state = USBD_STATE_ADDRESSED;
+          pdev->dev_config = cfgidx;
+          USBD_ClrClassConfig(pdev, cfgidx);
+          USBD_CtlSendStatus(pdev);
+        }
+        else if (cfgidx != pdev->dev_config)
+        {
+          /* Clear old configuration */
+          USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config);
+
+          /* set new configuration */
+          pdev->dev_config = cfgidx;
+          if (USBD_SetClassConfig(pdev, cfgidx) == USBD_FAIL)
+          {
+            USBD_CtlError(pdev, req);
+            return;
+          }
+          USBD_CtlSendStatus(pdev);
+        }
+        else
+        {
+          USBD_CtlSendStatus(pdev);
+        }
+        break;
+
+      default:
+        USBD_CtlError(pdev, req);
+        USBD_ClrClassConfig(pdev, cfgidx);
+        break;
+    }
+  }
+}
+
+/**
+* @brief  USBD_GetConfig
+*         Handle Get device configuration request
+* @param  pdev: device instance
+* @param  req: usb request
+* @retval status
+*/
+static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
+{
+  if (req->wLength != 1U)
+  {
+    USBD_CtlError(pdev, req);
+  }
+  else
+  {
+    switch (pdev->dev_state)
+    {
+      case USBD_STATE_DEFAULT:
+      case USBD_STATE_ADDRESSED:
+        pdev->dev_default_config = 0U;
+        USBD_CtlSendData(pdev, (uint8_t *)(void *)&pdev->dev_default_config, 1U);
+        break;
+
+      case USBD_STATE_CONFIGURED:
+        USBD_CtlSendData(pdev, (uint8_t *)(void *)&pdev->dev_config, 1U);
+        break;
+
+      default:
+        USBD_CtlError(pdev, req);
+        break;
+    }
+  }
+}
+
+/**
+* @brief  USBD_GetStatus
+*         Handle Get Status request
+* @param  pdev: device instance
+* @param  req: usb request
+* @retval status
+*/
+static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
+{
+  switch (pdev->dev_state)
+  {
+    case USBD_STATE_DEFAULT:
+    case USBD_STATE_ADDRESSED:
+    case USBD_STATE_CONFIGURED:
+      if (req->wLength != 0x2U)
+      {
+        USBD_CtlError(pdev, req);
+        break;
+      }
+
+#if (USBD_SELF_POWERED == 1U)
+      pdev->dev_config_status = USB_CONFIG_SELF_POWERED;
+#else
+      pdev->dev_config_status = 0U;
+#endif
+
+      if (pdev->dev_remote_wakeup)
+      {
+        pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP;
+      }
+
+      USBD_CtlSendData(pdev, (uint8_t *)(void *)&pdev->dev_config_status, 2U);
+      break;
+
+    default:
+      USBD_CtlError(pdev, req);
+      break;
+  }
+}
+
+
+/**
+* @brief  USBD_SetFeature
+*         Handle Set device feature request
+* @param  pdev: device instance
+* @param  req: usb request
+* @retval status
+*/
+static void USBD_SetFeature(USBD_HandleTypeDef *pdev,
+                            USBD_SetupReqTypedef *req)
+{
+  if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
+  {
+    pdev->dev_remote_wakeup = 1U;
+    USBD_CtlSendStatus(pdev);
+  }
+}
+
+
+/**
+* @brief  USBD_ClrFeature
+*         Handle clear device feature request
+* @param  pdev: device instance
+* @param  req: usb request
+* @retval status
+*/
+static void USBD_ClrFeature(USBD_HandleTypeDef *pdev,
+                            USBD_SetupReqTypedef *req)
+{
+  switch (pdev->dev_state)
+  {
+    case USBD_STATE_DEFAULT:
+    case USBD_STATE_ADDRESSED:
+    case USBD_STATE_CONFIGURED:
+      if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
+      {
+        pdev->dev_remote_wakeup = 0U;
+        USBD_CtlSendStatus(pdev);
+      }
+      break;
+
+    default:
+      USBD_CtlError(pdev, req);
+      break;
+  }
+}
+
+/**
+* @brief  USBD_ParseSetupRequest
+*         Copy buffer into setup structure
+* @param  pdev: device instance
+* @param  req: usb request
+* @retval None
+*/
+
+void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata)
+{
+  req->bmRequest = *(uint8_t *)(pdata);
+  req->bRequest = *(uint8_t *)(pdata + 1U);
+  req->wValue = SWAPBYTE(pdata + 2U);
+  req->wIndex = SWAPBYTE(pdata + 4U);
+  req->wLength = SWAPBYTE(pdata + 6U);
+
+}
+
+/**
+* @brief  USBD_CtlError
+*         Handle USB low level Error
+* @param  pdev: device instance
+* @param  req: usb request
+* @retval None
+*/
+
+void USBD_CtlError(USBD_HandleTypeDef *pdev,
+                   USBD_SetupReqTypedef *req)
+{
+  USBD_LL_StallEP(pdev, 0x80U);
+  USBD_LL_StallEP(pdev, 0U);
+}
+
+
+/**
+  * @brief  USBD_GetString
+  *         Convert Ascii string into unicode one
+  * @param  desc : descriptor buffer
+  * @param  unicode : Formatted string buffer (unicode)
+  * @param  len : descriptor length
+  * @retval None
+  */
+void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len)
+{
+  uint8_t idx = 0U;
+
+  if (desc != NULL)
+  {
+    *len = (uint16_t)USBD_GetLen(desc) * 2U + 2U;
+    unicode[idx++] = *(uint8_t *)(void *)len;
+    unicode[idx++] = USB_DESC_TYPE_STRING;
+
+    while (*desc != '\0')
+    {
+      unicode[idx++] = *desc++;
+      unicode[idx++] =  0U;
+    }
+  }
+}
+
+/**
+  * @brief  USBD_GetLen
+  *         return the string length
+   * @param  buf : pointer to the ascii string buffer
+  * @retval string length
+  */
+static uint8_t USBD_GetLen(uint8_t *buf)
+{
+  uint8_t  len = 0U;
+
+  while (*buf != '\0')
+  {
+    len++;
+    buf++;
+  }
+
+  return len;
+}
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c
new file mode 100644
index 00000000..33519727
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c
@@ -0,0 +1,216 @@
+/**
+  ******************************************************************************
+  * @file    usbd_ioreq.c
+  * @author  MCD Application Team
+  * @brief   This file provides the IO requests APIs for control endpoints.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbd_ioreq.h"
+
+/** @addtogroup STM32_USB_DEVICE_LIBRARY
+  * @{
+  */
+
+
+/** @defgroup USBD_IOREQ
+  * @brief control I/O requests module
+  * @{
+  */
+
+/** @defgroup USBD_IOREQ_Private_TypesDefinitions
+  * @{
+  */
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_IOREQ_Private_Defines
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_IOREQ_Private_Macros
+  * @{
+  */
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_IOREQ_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_IOREQ_Private_FunctionPrototypes
+  * @{
+  */
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_IOREQ_Private_Functions
+  * @{
+  */
+
+/**
+* @brief  USBD_CtlSendData
+*         send data on the ctl pipe
+* @param  pdev: device instance
+* @param  buff: pointer to data buffer
+* @param  len: length of data to be sent
+* @retval status
+*/
+USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev,
+                                    uint8_t *pbuf, uint16_t len)
+{
+  /* Set EP0 State */
+  pdev->ep0_state = USBD_EP0_DATA_IN;
+  pdev->ep_in[0].total_length = len;
+  pdev->ep_in[0].rem_length   = len;
+
+  /* Start the transfer */
+  USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
+
+  return USBD_OK;
+}
+
+/**
+* @brief  USBD_CtlContinueSendData
+*         continue sending data on the ctl pipe
+* @param  pdev: device instance
+* @param  buff: pointer to data buffer
+* @param  len: length of data to be sent
+* @retval status
+*/
+USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev,
+                                            uint8_t *pbuf, uint16_t len)
+{
+  /* Start the next transfer */
+  USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
+
+  return USBD_OK;
+}
+
+/**
+* @brief  USBD_CtlPrepareRx
+*         receive data on the ctl pipe
+* @param  pdev: device instance
+* @param  buff: pointer to data buffer
+* @param  len: length of data to be received
+* @retval status
+*/
+USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef *pdev,
+                                     uint8_t *pbuf, uint16_t len)
+{
+  /* Set EP0 State */
+  pdev->ep0_state = USBD_EP0_DATA_OUT;
+  pdev->ep_out[0].total_length = len;
+  pdev->ep_out[0].rem_length   = len;
+
+  /* Start the transfer */
+  USBD_LL_PrepareReceive(pdev, 0U, pbuf, len);
+
+  return USBD_OK;
+}
+
+/**
+* @brief  USBD_CtlContinueRx
+*         continue receive data on the ctl pipe
+* @param  pdev: device instance
+* @param  buff: pointer to data buffer
+* @param  len: length of data to be received
+* @retval status
+*/
+USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev,
+                                      uint8_t *pbuf, uint16_t len)
+{
+  USBD_LL_PrepareReceive(pdev, 0U, pbuf, len);
+
+  return USBD_OK;
+}
+
+/**
+* @brief  USBD_CtlSendStatus
+*         send zero lzngth packet on the ctl pipe
+* @param  pdev: device instance
+* @retval status
+*/
+USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev)
+{
+  /* Set EP0 State */
+  pdev->ep0_state = USBD_EP0_STATUS_IN;
+
+  /* Start the transfer */
+  USBD_LL_Transmit(pdev, 0x00U, NULL, 0U);
+
+  return USBD_OK;
+}
+
+/**
+* @brief  USBD_CtlReceiveStatus
+*         receive zero lzngth packet on the ctl pipe
+* @param  pdev: device instance
+* @retval status
+*/
+USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev)
+{
+  /* Set EP0 State */
+  pdev->ep0_state = USBD_EP0_STATUS_OUT;
+
+  /* Start the transfer */
+  USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
+
+  return USBD_OK;
+}
+
+/**
+* @brief  USBD_GetRxCount
+*         returns the received data length
+* @param  pdev: device instance
+* @param  ep_addr: endpoint address
+* @retval Rx Data blength
+*/
+uint32_t USBD_GetRxCount(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+{
+  return USBD_LL_GetRxDataSize(pdev, ep_addr);
+}
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/stm32h7xx_hal_conf.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/stm32h7xx_hal_conf.h
new file mode 100644
index 00000000..50080dbc
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/stm32h7xx_hal_conf.h
@@ -0,0 +1,493 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32H7xx_HAL_CONF_H
+#define __STM32H7xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver 
+  */
+#define HAL_MODULE_ENABLED  
+
+  /* #define HAL_ADC_MODULE_ENABLED   */
+#define HAL_FDCAN_MODULE_ENABLED
+/* #define HAL_CEC_MODULE_ENABLED   */
+/* #define HAL_COMP_MODULE_ENABLED   */
+/* #define HAL_CRC_MODULE_ENABLED   */
+/* #define HAL_CRYP_MODULE_ENABLED   */
+/* #define HAL_DAC_MODULE_ENABLED   */
+/* #define HAL_DCMI_MODULE_ENABLED   */
+/* #define HAL_DMA2D_MODULE_ENABLED   */
+/* #define HAL_ETH_MODULE_ENABLED   */
+/* #define HAL_NAND_MODULE_ENABLED   */
+/* #define HAL_NOR_MODULE_ENABLED   */
+/* #define HAL_OTFDEC_MODULE_ENABLED   */
+/* #define HAL_SRAM_MODULE_ENABLED   */
+/* #define HAL_SDRAM_MODULE_ENABLED   */
+/* #define HAL_HASH_MODULE_ENABLED   */
+/* #define HAL_HRTIM_MODULE_ENABLED   */
+/* #define HAL_HSEM_MODULE_ENABLED   */
+/* #define HAL_GFXMMU_MODULE_ENABLED   */
+/* #define HAL_JPEG_MODULE_ENABLED   */
+/* #define HAL_OPAMP_MODULE_ENABLED   */
+/* #define HAL_OSPI_MODULE_ENABLED   */
+/* #define HAL_OSPI_MODULE_ENABLED   */
+/* #define HAL_I2S_MODULE_ENABLED   */
+/* #define HAL_SMBUS_MODULE_ENABLED   */
+/* #define HAL_IWDG_MODULE_ENABLED   */
+/* #define HAL_LPTIM_MODULE_ENABLED   */
+/* #define HAL_LTDC_MODULE_ENABLED   */
+/* #define HAL_QSPI_MODULE_ENABLED   */
+/* #define HAL_RNG_MODULE_ENABLED   */
+/* #define HAL_RTC_MODULE_ENABLED   */
+/* #define HAL_SAI_MODULE_ENABLED   */
+/* #define HAL_SD_MODULE_ENABLED   */
+/* #define HAL_MMC_MODULE_ENABLED   */
+/* #define HAL_SPDIFRX_MODULE_ENABLED   */
+/* #define HAL_SPI_MODULE_ENABLED   */
+/* #define HAL_SWPMI_MODULE_ENABLED   */
+/* #define HAL_TIM_MODULE_ENABLED   */
+/* #define HAL_UART_MODULE_ENABLED   */
+/* #define HAL_USART_MODULE_ENABLED   */
+/* #define HAL_IRDA_MODULE_ENABLED   */
+/* #define HAL_SMARTCARD_MODULE_ENABLED   */
+/* #define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_PCD_MODULE_ENABLED
+/* #define HAL_HCD_MODULE_ENABLED   */
+/* #define HAL_DFSDM_MODULE_ENABLED   */
+/* #define HAL_DSI_MODULE_ENABLED   */
+/* #define HAL_JPEG_MODULE_ENABLED   */
+/* #define HAL_MDIOS_MODULE_ENABLED   */
+/* #define HAL_PSSI_MODULE_ENABLED   */
+/* #define HAL_DTS_MODULE_ENABLED   */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_MDMA_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_HSEM_MODULE_ENABLED
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).  
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal  oscillator (CSI) default value.
+  *        This value is the default CSI value after Reset.
+  */
+#if !defined  (CSI_VALUE)
+  #define CSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* CSI_VALUE */
+   
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL). 
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for I2S peripheral
+  *        This value is used by the I2S HAL module to compute the I2S clock source 
+  *        frequency, this source is inserted directly through I2S_CKIN pad. 
+  */
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+  #define EXTERNAL_CLOCK_VALUE    12288000U /*!< Value of the External clock in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+#define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            ((uint32_t)0U) /*!< tick interrupt priority */
+#define  USE_RTOS                     0U
+#define  USE_SD_TRANSCEIVER           0U               /*!< use uSD Transceiver */
+
+#define  USE_HAL_ADC_REGISTER_CALLBACKS     0U /* ADC register callback disabled     */
+#define  USE_HAL_CEC_REGISTER_CALLBACKS     0U /* CEC register callback disabled     */
+#define  USE_HAL_COMP_REGISTER_CALLBACKS    0U /* COMP register callback disabled    */
+#define  USE_HAL_CRYP_REGISTER_CALLBACKS    0U /* CRYP register callback disabled    */
+#define  USE_HAL_DAC_REGISTER_CALLBACKS     0U /* DAC register callback disabled     */
+#define  USE_HAL_DCMI_REGISTER_CALLBACKS    0U /* DCMI register callback disabled    */
+#define  USE_HAL_DFSDM_REGISTER_CALLBACKS   0U /* DFSDM register callback disabled   */
+#define  USE_HAL_DMA2D_REGISTER_CALLBACKS   0U /* DMA2D register callback disabled   */
+#define  USE_HAL_DSI_REGISTER_CALLBACKS     0U /* DSI register callback disabled     */
+#define  USE_HAL_DTS_REGISTER_CALLBACKS     0U /* DTS register callback disabled     */
+#define  USE_HAL_ETH_REGISTER_CALLBACKS     0U /* ETH register callback disabled     */
+#define  USE_HAL_FDCAN_REGISTER_CALLBACKS   0U /* FDCAN register callback disabled   */
+#define  USE_HAL_NAND_REGISTER_CALLBACKS    0U /* NAND register callback disabled    */
+#define  USE_HAL_NOR_REGISTER_CALLBACKS     0U /* NOR register callback disabled     */
+#define  USE_HAL_SDRAM_REGISTER_CALLBACKS   0U /* SDRAM register callback disabled   */
+#define  USE_HAL_SRAM_REGISTER_CALLBACKS    0U /* SRAM register callback disabled    */
+#define  USE_HAL_HASH_REGISTER_CALLBACKS    0U /* HASH register callback disabled    */
+#define  USE_HAL_HCD_REGISTER_CALLBACKS     0U /* HCD register callback disabled     */
+#define  USE_HAL_GFXMMU_REGISTER_CALLBACKS  0U /* GFXMMU register callback disabled  */
+#define  USE_HAL_HRTIM_REGISTER_CALLBACKS   0U /* HRTIM register callback disabled   */
+#define  USE_HAL_I2C_REGISTER_CALLBACKS     0U /* I2C register callback disabled     */
+#define  USE_HAL_I2S_REGISTER_CALLBACKS     0U /* I2S register callback disabled     */
+#define  USE_HAL_IRDA_REGISTER_CALLBACKS    0U /* IRDA register callback disabled    */
+#define  USE_HAL_JPEG_REGISTER_CALLBACKS    0U /* JPEG register callback disabled    */
+#define  USE_HAL_LPTIM_REGISTER_CALLBACKS   0U /* LPTIM register callback disabled   */
+#define  USE_HAL_LTDC_REGISTER_CALLBACKS    0U /* LTDC register callback disabled    */
+#define  USE_HAL_MDIOS_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */
+#define  USE_HAL_MMC_REGISTER_CALLBACKS     0U /* MMC register callback disabled     */
+#define  USE_HAL_OPAMP_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */
+#define  USE_HAL_OSPI_REGISTER_CALLBACKS    0U /* OSPI register callback disabled    */
+#define  USE_HAL_OTFDEC_REGISTER_CALLBACKS  0U /* OTFDEC register callback disabled  */
+#define  USE_HAL_PCD_REGISTER_CALLBACKS     0U /* PCD register callback disabled     */
+#define  USE_HAL_QSPI_REGISTER_CALLBACKS    0U /* QSPI register callback disabled    */
+#define  USE_HAL_RNG_REGISTER_CALLBACKS     0U /* RNG register callback disabled     */
+#define  USE_HAL_RTC_REGISTER_CALLBACKS     0U /* RTC register callback disabled     */
+#define  USE_HAL_SAI_REGISTER_CALLBACKS     0U /* SAI register callback disabled     */
+#define  USE_HAL_SD_REGISTER_CALLBACKS      0U /* SD register callback disabled      */
+#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS  0U /* SMARTCARD register callback disabled */
+#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */
+#define  USE_HAL_SMBUS_REGISTER_CALLBACKS   0U /* SMBUS register callback disabled   */
+#define  USE_HAL_SPI_REGISTER_CALLBACKS     0U /* SPI register callback disabled     */
+#define  USE_HAL_SWPMI_REGISTER_CALLBACKS   0U /* SWPMI register callback disabled   */
+#define  USE_HAL_TIM_REGISTER_CALLBACKS     0U /* TIM register callback disabled     */
+#define  USE_HAL_UART_REGISTER_CALLBACKS    0U /* UART register callback disabled    */
+#define  USE_HAL_USART_REGISTER_CALLBACKS   0U /* USART register callback disabled   */
+#define  USE_HAL_WWDG_REGISTER_CALLBACKS    0U /* WWDG register callback disabled    */
+
+/* ########################### Ethernet Configuration ######################### */
+#define ETH_TX_DESC_CNT         4  /* number of Ethernet Tx DMA descriptors */
+#define ETH_RX_DESC_CNT         4  /* number of Ethernet Rx DMA descriptors */
+
+#define ETH_MAC_ADDR0    ((uint8_t)0x02)
+#define ETH_MAC_ADDR1    ((uint8_t)0x00)
+#define ETH_MAC_ADDR2    ((uint8_t)0x00)
+#define ETH_MAC_ADDR3    ((uint8_t)0x00)
+#define ETH_MAC_ADDR4    ((uint8_t)0x00)
+#define ETH_MAC_ADDR5    ((uint8_t)0x00)
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */ 
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file 
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32h7xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32h7xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32h7xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_MDMA_MODULE_ENABLED
+ #include "stm32h7xx_hal_mdma.h"
+#endif /* HAL_MDMA_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+  #include "stm32h7xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+  #include "stm32h7xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+  #include "stm32h7xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DSI_MODULE_ENABLED
+  #include "stm32h7xx_hal_dsi.h"
+#endif /* HAL_DSI_MODULE_ENABLED */
+
+#ifdef HAL_DFSDM_MODULE_ENABLED
+  #include "stm32h7xx_hal_dfsdm.h"
+#endif /* HAL_DFSDM_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+  #include "stm32h7xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32h7xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32h7xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32h7xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+  #include "stm32h7xx_hal_fdcan.h"
+#endif /* HAL_FDCAN_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+  #include "stm32h7xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32h7xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32h7xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32h7xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+  #include "stm32h7xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32h7xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GFXMMU_MODULE_ENABLED
+  #include "stm32h7xx_hal_gfxmmu.h"
+#endif /* HAL_GFXMMU_MODULE_ENABLED */
+
+#ifdef HAL_HRTIM_MODULE_ENABLED
+  #include "stm32h7xx_hal_hrtim.h"
+#endif /* HAL_HRTIM_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32h7xx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+  #include "stm32h7xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+  #include "stm32h7xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+  #include "stm32h7xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32h7xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32h7xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32h7xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_JPEG_MODULE_ENABLED
+ #include "stm32h7xx_hal_jpeg.h"
+#endif /* HAL_JPEG_MODULE_ENABLED */
+
+#ifdef HAL_MDIOS_MODULE_ENABLED
+ #include "stm32h7xx_hal_mdios.h"
+#endif /* HAL_MDIOS_MODULE_ENABLED */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+ #include "stm32h7xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+#include "stm32h7xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+#include "stm32h7xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_OPAMP_MODULE_ENABLED
+#include "stm32h7xx_hal_opamp.h"
+#endif /* HAL_OPAMP_MODULE_ENABLED */
+
+#ifdef HAL_OSPI_MODULE_ENABLED
+  #include "stm32h7xx_hal_ospi.h"
+#endif /* HAL_OSPI_MODULE_ENABLED */
+   
+#ifdef HAL_OTFDEC_MODULE_ENABLED
+#include "stm32h7xx_hal_otfdec.h"
+#endif /* HAL_OTFDEC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32h7xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32h7xx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RAMECC_MODULE_ENABLED
+ #include "stm32h7xx_hal_ramecc.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32h7xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32h7xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32h7xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32h7xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+ #include "stm32h7xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32h7xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_SPDIFRX_MODULE_ENABLED
+ #include "stm32h7xx_hal_spdifrx.h"
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */
+
+#ifdef HAL_SWPMI_MODULE_ENABLED
+ #include "stm32h7xx_hal_swpmi.h"
+#endif /* HAL_SWPMI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32h7xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32h7xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32h7xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32h7xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32h7xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32h7xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32h7xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32h7xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32h7xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_PSSI_MODULE_ENABLED
+  #include "stm32h7xx_hal_pssi.h"
+#endif /* HAL_PSSI_MODULE_ENABLED */
+
+#ifdef HAL_DTS_MODULE_ENABLED
+  #include "stm32h7xx_hal_dts.h"
+#endif /* HAL_DTS_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed. 
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32H7xx_HAL_CONF_H */
+ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/system_stm32h7xx.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/system_stm32h7xx.c
new file mode 100644
index 00000000..58da4c83
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/lib/system_stm32h7xx.c
@@ -0,0 +1,399 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32h7xx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-Mx Device Peripheral Access Layer System Source File.
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32h7xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock, it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32h7xx_system
+  * @{
+  */
+
+/** @addtogroup STM32H7xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32h7xx.h"
+#include <math.h>
+#if !defined  (HSE_VALUE)
+#define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (CSI_VALUE)
+  #define CSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* CSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Private_Defines
+  * @{
+  */
+
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to use initialized data in D2 domain SRAM (AHB SRAM) */
+/* #define DATA_IN_D2_SRAM */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00000000UL /*!< Vector Table base offset field.
+                                      This value must be a multiple of 0x200. */
+/******************************************************************************/
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Private_Variables
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock = 64000000;
+  uint32_t SystemD2Clock = 64000000;
+  const  uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the FPU setting and  vector table location
+  *         configuration.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+#if defined (DATA_IN_D2_SRAM)
+ __IO uint32_t tmpreg;
+#endif /* DATA_IN_D2_SRAM */
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2)));  /* set CP10 and CP11 Full Access */
+  #endif
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set HSION bit */
+  RCC->CR |= RCC_CR_HSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00000000;
+
+  /* Reset HSEON, CSSON , CSION,RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */
+  RCC->CR &= 0xEAF6ED7FU;
+
+#if defined(D3_SRAM_BASE)
+  /* Reset D1CFGR register */
+  RCC->D1CFGR = 0x00000000;
+
+  /* Reset D2CFGR register */
+  RCC->D2CFGR = 0x00000000;
+
+  /* Reset D3CFGR register */
+  RCC->D3CFGR = 0x00000000;
+#else
+  /* Reset CDCFGR1 register */
+  RCC->CDCFGR1 = 0x00000000;
+
+  /* Reset CDCFGR2 register */
+  RCC->CDCFGR2 = 0x00000000;
+
+  /* Reset SRDCFGR register */
+  RCC->SRDCFGR = 0x00000000;
+#endif
+  /* Reset PLLCKSELR register */
+  RCC->PLLCKSELR = 0x00000000;
+
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x00000000;
+  /* Reset PLL1DIVR register */
+  RCC->PLL1DIVR = 0x00000000;
+  /* Reset PLL1FRACR register */
+  RCC->PLL1FRACR = 0x00000000;
+
+  /* Reset PLL2DIVR register */
+  RCC->PLL2DIVR = 0x00000000;
+
+  /* Reset PLL2FRACR register */
+
+  RCC->PLL2FRACR = 0x00000000;
+  /* Reset PLL3DIVR register */
+  RCC->PLL3DIVR = 0x00000000;
+
+  /* Reset PLL3FRACR register */
+  RCC->PLL3FRACR = 0x00000000;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+
+#if (STM32H7_DEV_ID == 0x450UL)
+  /* dual core CM7 or single core line */
+  if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
+  {
+    /* if stm32h7 revY*/
+    /* Change  the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
+    *((__IO uint32_t*)0x51008108) = 0x000000001U;
+  }
+#endif
+
+#if defined (DATA_IN_D2_SRAM)
+  /* in case of initialized data in D2 SRAM (AHB SRAM) , enable the D2 SRAM clock (AHB SRAM clock) */
+#if defined(RCC_AHB2ENR_D2SRAM3EN)
+  RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);
+#elif defined(RCC_AHB2ENR_D2SRAM2EN)
+  RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN);
+#else
+  RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN);
+#endif /* RCC_AHB2ENR_D2SRAM3EN */
+
+  tmpreg = RCC->AHB2ENR;
+  (void) tmpreg;
+#endif /* DATA_IN_D2_SRAM */
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  /* Configure the Vector Table location add offset address for cortex-M4 ------------------*/
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = D2_AHBSRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+  SCB->VTOR = FLASH_BANK2_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif /* VECT_TAB_SRAM */
+
+#else
+
+  /* Configure the Vector Table location add offset address for cortex-M7 ------------------*/
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = D1_AXISRAM_BASE  | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal AXI-RAM */
+#else
+  SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+#endif /*DUAL_CORE && CORE_CM4*/
+
+}
+
+/**
+   * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock , it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*),
+  *             HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
+  *
+  *         (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *         (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+  *             64 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+  *              25 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
+  uint32_t common_system_clock;
+  float_t fracn1, pllvco;
+
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+  case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */
+    common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
+    break;
+
+  case RCC_CFGR_SWS_CSI:  /* CSI used as system clock  source */
+    common_system_clock = CSI_VALUE;
+    break;
+
+  case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
+    common_system_clock = HSE_VALUE;
+    break;
+
+  case RCC_CFGR_SWS_PLL1:  /* PLL1 used as system clock  source */
+
+    /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
+    SYSCLK = PLL_VCO / PLLR
+    */
+    pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+    pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4)  ;
+    pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
+    fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
+
+    if (pllm != 0U)
+    {
+      switch (pllsource)
+      {
+        case RCC_PLLCKSELR_PLLSRC_HSI:  /* HSI used as PLL clock source */
+
+        hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
+        pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+
+        break;
+
+        case RCC_PLLCKSELR_PLLSRC_CSI:  /* CSI used as PLL clock source */
+          pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+        break;
+
+        case RCC_PLLCKSELR_PLLSRC_HSE:  /* HSE used as PLL clock source */
+          pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+        break;
+
+      default:
+          pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+        break;
+      }
+      pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
+      common_system_clock =  (uint32_t)(float_t)(pllvco/(float_t)pllp);
+    }
+    else
+    {
+      common_system_clock = 0U;
+    }
+    break;
+
+  default:
+    common_system_clock = CSI_VALUE;
+    break;
+  }
+
+  /* Compute SystemClock frequency --------------------------------------------------*/
+#if defined (RCC_D1CFGR_D1CPRE)
+  tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];
+
+  /* common_system_clock frequency : CM7 CPU frequency  */
+  common_system_clock >>= tmp;
+
+  /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency  */
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+
+#else
+  tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos];
+
+  /* common_system_clock frequency : CM7 CPU frequency  */
+  common_system_clock >>= tmp;
+
+  /* SystemD2Clock frequency : AXI and AHBs Clock frequency  */
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+
+#endif
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  SystemCoreClock = SystemD2Clock;
+#else
+  SystemCoreClock = common_system_clock;
+#endif /* DUAL_CORE && CORE_CM4 */
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/main.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/main.c
new file mode 100644
index 00000000..8ec8b30d
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/main.c
@@ -0,0 +1,287 @@
+/************************************************************************************//**
+* \file         Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/main.c
+* \brief        Bootloader application source file.
+* \ingroup      Boot_ARMCM7_STM32H7_Nucleo_H743ZI_IAR
+* \internal
+*----------------------------------------------------------------------------------------
+*                          C O P Y R I G H T
+*----------------------------------------------------------------------------------------
+*   Copyright (c) 2020  by Feaser    http://www.feaser.com    All rights reserved
+*
+*----------------------------------------------------------------------------------------
+*                            L I C E N S E
+*----------------------------------------------------------------------------------------
+* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as published by the Free
+* Software Foundation, either version 3 of the License, or (at your option) any later
+* version.
+*
+* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+* PURPOSE. See the GNU General Public License for more details.
+*
+* You have received a copy of the GNU General Public License along with OpenBLT. It
+* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
+*
+* \endinternal
+****************************************************************************************/
+
+/****************************************************************************************
+* Include files
+****************************************************************************************/
+#include "boot.h"                                /* bootloader generic header          */
+#include "stm32h7xx.h"                           /* STM32 CPU and HAL header           */
+#include "stm32h7xx_ll_pwr.h"                    /* STM32 LL PWR header                */
+#include "stm32h7xx_ll_rcc.h"                    /* STM32 LL RCC header                */
+#include "stm32h7xx_ll_utils.h"                  /* STM32 LL UTILS header              */
+#include "stm32h7xx_ll_gpio.h"                   /* STM32 LL GPIO header               */
+
+
+/****************************************************************************************
+* Function prototypes
+****************************************************************************************/
+static void Init(void);
+static void SystemClock_Config(void);
+
+
+/************************************************************************************//**
+** \brief     This is the entry point for the bootloader application and is called
+**            by the reset interrupt vector after the C-startup routines executed.
+** \return    none.
+**
+****************************************************************************************/
+void main(void)
+{
+  /* initialize the microcontroller */
+  Init();
+  /* initialize the bootloader */
+  BootInit();
+
+  /* start the infinite program loop */
+  while (1)
+  {
+    /* run the bootloader task */
+    BootTask();
+  }
+} /*** end of main ***/
+
+
+/************************************************************************************//**
+** \brief     Initializes the microcontroller.
+** \return    none.
+**
+****************************************************************************************/
+static void Init(void)
+{
+  /* HAL library initialization */
+  HAL_Init();
+  /* configure system clock */
+  SystemClock_Config();
+} /*** end of Init ***/
+
+
+/************************************************************************************//**
+** \brief     System Clock Configuration. This code was created by CubeMX and configures
+**            the system clock to match the configuration in the bootloader's
+**            configuration (blt_conf.h), specifically the macros:
+**            BOOT_CPU_SYSTEM_SPEED_KHZ and BOOT_CPU_XTAL_SPEED_KHZ.
+**            Note that the Lower Layer drivers were selected in CubeMX for the RCC
+**            subsystem.
+** \return    none.
+**
+****************************************************************************************/
+static void SystemClock_Config(void)
+{
+  /* Set flash latency. */
+  LL_FLASH_SetLatency(LL_FLASH_LATENCY_4);
+  if (LL_FLASH_GetLatency() != LL_FLASH_LATENCY_4)
+  {
+    /* Error setting flash latency. */
+    ASSERT_RT(BLT_FALSE);
+  }
+
+  /* Configure the main internal regulator output voltage. */
+  LL_PWR_ConfigSupply(LL_PWR_LDO_SUPPLY);
+  LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE0);
+
+  /* Enable the HSE clock. */
+  LL_RCC_HSE_EnableBypass();
+  LL_RCC_HSE_Enable();
+
+  /* Wait till HSE is ready. */
+  while (LL_RCC_HSE_IsReady() != 1)
+  {
+    ;
+  }
+
+  /* Configure and enable the PLL. */
+  LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_HSE);
+  LL_RCC_PLL1P_Enable();
+  LL_RCC_PLL1Q_Enable();
+  LL_RCC_PLL1_SetVCOInputRange(LL_RCC_PLLINPUTRANGE_2_4);
+  LL_RCC_PLL1_SetVCOOutputRange(LL_RCC_PLLVCORANGE_WIDE);
+  LL_RCC_PLL1_SetM(4);
+  LL_RCC_PLL1_SetN(480);
+  LL_RCC_PLL1_SetP(2);
+  LL_RCC_PLL1_SetQ(20);
+  LL_RCC_PLL1_SetR(2);
+  LL_RCC_PLL1_Enable();
+  /* Wait till PLL is ready. */
+  while (LL_RCC_PLL1_IsReady() != 1)
+  {
+    ;
+  }
+
+  /* Intermediate AHB prescaler 2 when target frequency clock is higher than 80 MHz */
+  LL_RCC_SetAHBPrescaler(LL_RCC_AHB_DIV_2);
+
+  LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL1);
+  LL_RCC_SetSysPrescaler(LL_RCC_SYSCLK_DIV_1);
+  LL_RCC_SetAHBPrescaler(LL_RCC_AHB_DIV_2);
+  LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_2);
+  LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_2);
+  LL_RCC_SetAPB3Prescaler(LL_RCC_APB3_DIV_2);
+  LL_RCC_SetAPB4Prescaler(LL_RCC_APB4_DIV_2);
+
+  /* Configure peripheral clock sources. */
+  LL_RCC_SetUSARTClockSource(LL_RCC_USART234578_CLKSOURCE_PCLK1);
+  LL_RCC_SetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE_HSE);
+  LL_RCC_SetUSBClockSource(LL_RCC_USB_CLKSOURCE_PLL1Q);
+
+  /* Update the system clock speed setting. */
+  LL_SetSystemCoreClock(BOOT_CPU_SYSTEM_SPEED_KHZ * 1000u);
+} /*** end of SystemClock_Config ***/
+
+
+/************************************************************************************//**
+** \brief     Initializes the Global MSP. This function is called from HAL_Init()
+**            function to perform system level initialization (GPIOs, clock, DMA,
+**            interrupt).
+** \return    none.
+**
+****************************************************************************************/
+void HAL_MspInit(void)
+{
+  LL_GPIO_InitTypeDef GPIO_InitStruct;
+
+  /* SYSCFG clock enable. */
+  LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_SYSCFG);
+
+  /* GPIO ports clock enable. */
+  LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOA);
+  LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOB);
+  LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOC);
+  LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOD);
+
+#if (BOOT_COM_RS232_ENABLE > 0)
+  /* UART clock enable. */
+  LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USART3);
+#endif
+
+#if (BOOT_COM_CAN_ENABLE > 0)
+  /* CAN clock enable. */
+  LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_FDCAN);
+#endif
+
+  /* Configure GPIO pin for the LED. */
+  GPIO_InitStruct.Pin = LL_GPIO_PIN_7;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  LL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+  /* Configure GPIO pin for (optional) backdoor entry input. */
+  GPIO_InitStruct.Pin = LL_GPIO_PIN_13;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  LL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+#if (BOOT_COM_RS232_ENABLE > 0)
+  /* UART TX and RX GPIO pin configuration. */
+  GPIO_InitStruct.Pin = LL_GPIO_PIN_8 | LL_GPIO_PIN_9;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  GPIO_InitStruct.Alternate = LL_GPIO_AF_7;
+  LL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+#endif
+
+#if (BOOT_COM_CAN_ENABLE > 0)
+  /* CAN TX and RX GPIO pin configuration. */
+  GPIO_InitStruct.Pin = LL_GPIO_PIN_8 | LL_GPIO_PIN_9;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  GPIO_InitStruct.Alternate = LL_GPIO_AF_9;
+  LL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+#endif
+
+#if (BOOT_COM_USB_ENABLE > 0)
+  /* USB pin configuration. */
+  GPIO_InitStruct.Pin = LL_GPIO_PIN_11 | LL_GPIO_PIN_12;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  GPIO_InitStruct.Alternate = LL_GPIO_AF_10;
+  LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+#endif
+
+#if (BOOT_COM_USB_ENABLE > 0)
+  /* USB clock enable. */
+  LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_USB2OTGHS);
+#endif
+} /*** end of HAL_MspInit ***/
+
+
+/************************************************************************************//**
+** \brief     DeInitializes the Global MSP. This function is called from HAL_DeInit()
+**            function to perform system level de-initialization (GPIOs, clock, DMA,
+**            interrupt).
+** \return    none.
+**
+****************************************************************************************/
+void HAL_MspDeInit(void)
+{
+  /* Reset the RCC clock configuration to the default reset state. */
+  LL_RCC_DeInit();
+  
+  /* Reset GPIO pin for the LED to turn it off. */
+  LL_GPIO_ResetOutputPin(GPIOB, LL_GPIO_PIN_7);
+
+  /* Deinit used GPIOs. */
+  LL_GPIO_DeInit(GPIOD);
+  LL_GPIO_DeInit(GPIOC);
+  LL_GPIO_DeInit(GPIOB);
+  LL_GPIO_DeInit(GPIOA);
+
+#if (BOOT_COM_USB_ENABLE > 0)
+  /* USB clock disable. */
+  LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_USB2OTGHS);
+#endif
+
+#if (BOOT_COM_CAN_ENABLE > 0)
+  /* CAN clock disable. */
+  LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_FDCAN);
+#endif
+
+#if (BOOT_COM_RS232_ENABLE > 0)
+  /* UART clock disable. */
+  LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_USART3);
+#endif
+
+  /* GPIO ports clock disable. */
+  LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_GPIOD);
+  LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_GPIOC);
+  LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_GPIOB);
+  LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_GPIOA);
+
+  /* SYSCFG clock disable. */
+  LL_APB4_GRP1_DisableClock(LL_APB4_GRP1_PERIPH_SYSCFG);
+} /*** end of HAL_MspDeInit ***/
+
+
+/*********************************** end of main.c *************************************/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/startup_stm32h743xx.s b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/startup_stm32h743xx.s
new file mode 100644
index 00000000..2efde5fe
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/startup_stm32h743xx.s
@@ -0,0 +1,979 @@
+;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;* File Name          : startup_stm32h743xx.s
+;* Author             : MCD Application Team
+;* Description        : STM32H743xx devices vector table for EWARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR 
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;* @attention
+;*
+;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+                                                  
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog Interrupt ( wwdg1_it)                                                 
+        DCD     PVD_AVD_IRQHandler                ; PVD/AVD through EXTI Line detection                                  
+        DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line                      
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line                                 
+        DCD     FLASH_IRQHandler                  ; FLASH                                                
+        DCD     RCC_IRQHandler                    ; RCC                                                  
+        DCD     EXTI0_IRQHandler                  ; EXTI Line0                                                       
+        DCD     EXTI1_IRQHandler                  ; EXTI Line1                                                       
+        DCD     EXTI2_IRQHandler                  ; EXTI Line2                                                       
+        DCD     EXTI3_IRQHandler                  ; EXTI Line3                                                       
+        DCD     EXTI4_IRQHandler                  ; EXTI Line4             
+        DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0     
+        DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1                                        
+        DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2                                        
+        DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3                                        
+        DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4                                        
+        DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5                                        
+        DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6       
+        DCD     ADC_IRQHandler                    ; ADC1, ADC2                                  
+        DCD     FDCAN1_IT0_IRQHandler             ; FDCAN1 interrupt line 0                                    
+        DCD     FDCAN2_IT0_IRQHandler             ; FDCAN2 interrupt line 0                                           
+        DCD     FDCAN1_IT1_IRQHandler             ; FDCAN1 interrupt line 1                                    
+        DCD     FDCAN2_IT1_IRQHandler             ; FDCAN2 interrupt line 1                                           
+        DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s                                              
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break interrupt        
+        DCD     TIM1_UP_IRQHandler                ; TIM1 Update 
+        DCD     TIM1_TRG_COM_IRQHandler           ; TIM1 Trigger and Commutation Interrupt 
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare                                             
+        DCD     TIM2_IRQHandler                   ; TIM2                                                 
+        DCD     TIM3_IRQHandler                   ; TIM3                                                 
+        DCD     TIM4_IRQHandler                   ; TIM4                                                 
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event                                                       
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error                                                       
+        DCD     I2C2_EV_IRQHandler                ; I2C2 Event                                                       
+        DCD     I2C2_ER_IRQHandler                ; I2C2 Error                                                         
+        DCD     SPI1_IRQHandler                   ; SPI1                                                 
+        DCD     SPI2_IRQHandler                   ; SPI2                                                 
+        DCD     USART1_IRQHandler                 ; USART1                                               
+        DCD     USART2_IRQHandler                 ; USART2                                               
+        DCD     USART3_IRQHandler                 ; USART3                                               
+        DCD     EXTI15_10_IRQHandler              ; External Line[15:10]              
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line	            
+        DCD     0                                 ; Reserved                        
+        DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break Interrupt and TIM12 global interrupt      
+        DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update Interrupt and TIM13 global interrupt
+        DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation Interrupt and TIM14 glob
+        DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt            
+        DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7                                                     
+        DCD     FMC_IRQHandler                    ; FMC                                 
+        DCD     SDMMC1_IRQHandler                 ; SDMMC1                                   
+        DCD     TIM5_IRQHandler                   ; TIM5                                 
+        DCD     SPI3_IRQHandler                   ; SPI3                                 
+        DCD     UART4_IRQHandler                  ; UART4                                
+        DCD     UART5_IRQHandler                  ; UART5                                
+        DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors                  
+        DCD     TIM7_IRQHandler                   ; TIM7           
+        DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0                        
+        DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1                        
+        DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2                        
+        DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3                        
+        DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4                        
+        DCD     ETH_IRQHandler                    ; Ethernet                             
+        DCD     ETH_WKUP_IRQHandler               ; Ethernet Wakeup through EXTI line                          
+        DCD     FDCAN_CAL_IRQHandler              ; FDCAN calibration unit interrupt                                 
+        DCD     0                                 ; Reserved                                          
+        DCD     0                                 ; Reserved             
+        DCD     0                                 ; Reserved             
+        DCD     0                                 ; Reserved                           
+        DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5                        
+        DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6                        
+        DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7                        
+        DCD     USART6_IRQHandler                 ; USART6                                 
+        DCD     I2C3_EV_IRQHandler                ; I2C3 event                                         
+        DCD     I2C3_ER_IRQHandler                ; I2C3 error                                         
+        DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out                      
+        DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In                       
+        DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI                         
+        DCD     OTG_HS_IRQHandler                 ; USB OTG HS                         
+        DCD     DCMI_IRQHandler                   ; DCMI                                 
+        DCD     0                                 ; Reserved                                     
+        DCD     RNG_IRQHandler                    ; Rng
+        DCD     FPU_IRQHandler                    ; FPU
+        DCD     UART7_IRQHandler                  ; UART7
+        DCD     UART8_IRQHandler                  ; UART8
+        DCD     SPI4_IRQHandler                   ; SPI4
+        DCD     SPI5_IRQHandler                   ; SPI5
+        DCD     SPI6_IRQHandler                   ; SPI6
+        DCD     SAI1_IRQHandler                   ; SAI1
+        DCD     LTDC_IRQHandler                   ; LTDC
+        DCD     LTDC_ER_IRQHandler                ; LTDC error
+        DCD     DMA2D_IRQHandler                  ; DMA2D
+        DCD     SAI2_IRQHandler                   ; SAI2
+        DCD     QUADSPI_IRQHandler                ; QUADSPI
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1
+        DCD     CEC_IRQHandler                    ; HDMI_CEC
+        DCD     I2C4_EV_IRQHandler                ; I2C4 Event                                         
+        DCD     I2C4_ER_IRQHandler                ; I2C4 Error 
+        DCD     SPDIF_RX_IRQHandler               ; SPDIF_RX
+        DCD     OTG_FS_EP1_OUT_IRQHandler         ; USB OTG FS End Point 1 Out                      
+        DCD     OTG_FS_EP1_IN_IRQHandler          ; USB OTG FS End Point 1 In                       
+        DCD     OTG_FS_WKUP_IRQHandler            ; USB OTG FS Wakeup through EXTI                         
+        DCD     OTG_FS_IRQHandler                 ; USB OTG FS                  
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX1 Overrun interrupt  
+        DCD     HRTIM1_Master_IRQHandler          ; HRTIM Master Timer global Interrupts                
+        DCD     HRTIM1_TIMA_IRQHandler            ; HRTIM Timer A global Interrupt                      
+        DCD     HRTIM1_TIMB_IRQHandler            ; HRTIM Timer B global Interrupt                      
+        DCD     HRTIM1_TIMC_IRQHandler            ; HRTIM Timer C global Interrupt                      
+        DCD     HRTIM1_TIMD_IRQHandler            ; HRTIM Timer D global Interrupt                      
+        DCD     HRTIM1_TIME_IRQHandler            ; HRTIM Timer E global Interrupt                      
+        DCD     HRTIM1_FLT_IRQHandler             ; HRTIM Fault global Interrupt 
+        DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM Filter0 Interrupt   
+        DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM Filter1 Interrupt                              
+        DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM Filter2 Interrupt                              
+        DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM Filter3 Interrupt                              
+        DCD     SAI3_IRQHandler                   ; SAI3 global Interrupt                               
+        DCD     SWPMI1_IRQHandler                 ; Serial Wire Interface 1 global interrupt        
+        DCD     TIM15_IRQHandler                  ; TIM15 global Interrupt                          
+        DCD     TIM16_IRQHandler                  ; TIM16 global Interrupt                          
+        DCD     TIM17_IRQHandler                  ; TIM17 global Interrupt                          
+        DCD     MDIOS_WKUP_IRQHandler             ; MDIOS Wakeup  Interrupt                         
+        DCD     MDIOS_IRQHandler                  ; MDIOS global Interrupt                          
+        DCD     JPEG_IRQHandler                   ; JPEG global Interrupt                           
+        DCD     MDMA_IRQHandler                   ; MDMA global Interrupt                           
+        DCD     0                                 ; Reserved                            
+        DCD     SDMMC2_IRQHandler                 ; SDMMC2 global Interrupt                         
+        DCD     HSEM1_IRQHandler                  ; HSEM1 global Interrupt                          
+        DCD     0                                 ; Reserved                          
+        DCD     ADC3_IRQHandler                   ; ADC3 global Interrupt                           
+        DCD     DMAMUX2_OVR_IRQHandler            ; DMAMUX Overrun interrupt                         
+        DCD     BDMA_Channel0_IRQHandler          ; BDMA Channel 0 global Interrupt                  
+        DCD     BDMA_Channel1_IRQHandler          ; BDMA Channel 1 global Interrupt                  
+        DCD     BDMA_Channel2_IRQHandler          ; BDMA Channel 2 global Interrupt                  
+        DCD     BDMA_Channel3_IRQHandler          ; BDMA Channel 3 global Interrupt                  
+        DCD     BDMA_Channel4_IRQHandler          ; BDMA Channel 4 global Interrupt                  
+        DCD     BDMA_Channel5_IRQHandler          ; BDMA Channel 5 global Interrupt                  
+        DCD     BDMA_Channel6_IRQHandler          ; BDMA Channel 6 global Interrupt                  
+        DCD     BDMA_Channel7_IRQHandler          ; BDMA Channel 7 global Interrupt                  
+        DCD     COMP1_IRQHandler                  ; COMP1 global Interrupt                          
+        DCD     LPTIM2_IRQHandler                 ; LP TIM2 global interrupt                        
+        DCD     LPTIM3_IRQHandler                 ; LP TIM3 global interrupt                        
+        DCD     LPTIM4_IRQHandler                 ; LP TIM4 global interrupt                        
+        DCD     LPTIM5_IRQHandler                 ; LP TIM5 global interrupt                        
+        DCD     LPUART1_IRQHandler                ; LP UART1 interrupt                              
+        DCD     0                                 ; Reserved              
+        DCD     CRS_IRQHandler                    ; Clock Recovery Global Interrupt                 
+        DCD     ECC_IRQHandler                    ; ECC diagnostic Global Interrupt
+        DCD     SAI4_IRQHandler                   ; SAI4 global interrupt                           
+        DCD     0                                 ; Reserved              
+        DCD     0                                 ; Reserved                             
+        DCD     WAKEUP_PIN_IRQHandler             ; Interrupt for all 6 wake-up pins 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler  
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_AVD_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_AVD_IRQHandler  
+        B PVD_AVD_IRQHandler
+
+        PUBWEAK TAMP_STAMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+TAMP_STAMP_IRQHandler  
+        B TAMP_STAMP_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)  
+RTC_WKUP_IRQHandler  
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler  
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler  
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler  
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler  
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler  
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+EXTI4_IRQHandler  
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Stream0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA1_Stream0_IRQHandler  
+        B DMA1_Stream0_IRQHandler
+
+        PUBWEAK DMA1_Stream1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA1_Stream1_IRQHandler  
+        B DMA1_Stream1_IRQHandler
+
+        PUBWEAK DMA1_Stream2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA1_Stream2_IRQHandler  
+        B DMA1_Stream2_IRQHandler
+
+        PUBWEAK DMA1_Stream3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA1_Stream3_IRQHandler  
+        B DMA1_Stream3_IRQHandler
+
+        PUBWEAK DMA1_Stream4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA1_Stream4_IRQHandler  
+        B DMA1_Stream4_IRQHandler
+
+        PUBWEAK DMA1_Stream5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA1_Stream5_IRQHandler  
+        B DMA1_Stream5_IRQHandler
+
+        PUBWEAK DMA1_Stream6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA1_Stream6_IRQHandler  
+        B DMA1_Stream6_IRQHandler
+
+        PUBWEAK ADC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler  
+        B ADC_IRQHandler
+
+        PUBWEAK FDCAN1_IT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+FDCAN1_IT0_IRQHandler  
+        B FDCAN1_IT0_IRQHandler
+
+        PUBWEAK FDCAN2_IT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)  
+FDCAN2_IT0_IRQHandler  
+        B FDCAN2_IT0_IRQHandler
+
+        PUBWEAK FDCAN1_IT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)  
+FDCAN1_IT1_IRQHandler  
+        B FDCAN1_IT1_IRQHandler
+
+        PUBWEAK FDCAN2_IT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)  
+FDCAN2_IT1_IRQHandler  
+        B FDCAN2_IT1_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+EXTI9_5_IRQHandler  
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+TIM1_BRK_IRQHandler  
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+TIM1_UP_IRQHandler  
+        B TIM1_UP_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+TIM1_TRG_COM_IRQHandler  
+        B TIM1_TRG_COM_IRQHandler
+        
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+TIM1_CC_IRQHandler  
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler  
+        B TIM2_IRQHandler
+
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler  
+        B TIM3_IRQHandler
+
+        PUBWEAK TIM4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler  
+        B TIM4_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+I2C1_EV_IRQHandler  
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+I2C1_ER_IRQHandler  
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+I2C2_EV_IRQHandler  
+        B I2C2_EV_IRQHandler
+
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+I2C2_ER_IRQHandler  
+        B I2C2_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler  
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler  
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler  
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler  
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler  
+        B USART3_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)   
+EXTI15_10_IRQHandler  
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)   
+RTC_Alarm_IRQHandler  
+        B RTC_Alarm_IRQHandler
+      
+        PUBWEAK TIM8_BRK_TIM12_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+TIM8_BRK_TIM12_IRQHandler  
+        B TIM8_BRK_TIM12_IRQHandler
+
+        PUBWEAK TIM8_UP_TIM13_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+TIM8_UP_TIM13_IRQHandler  
+        B TIM8_UP_TIM13_IRQHandler
+
+        PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+TIM8_TRG_COM_TIM14_IRQHandler  
+        B TIM8_TRG_COM_TIM14_IRQHandler
+
+        PUBWEAK TIM8_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+TIM8_CC_IRQHandler  
+        B TIM8_CC_IRQHandler
+
+        PUBWEAK DMA1_Stream7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA1_Stream7_IRQHandler  
+        B DMA1_Stream7_IRQHandler
+
+        PUBWEAK FMC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler  
+        B FMC_IRQHandler
+
+        PUBWEAK SDMMC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler  
+        B SDMMC1_IRQHandler
+
+        PUBWEAK TIM5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler  
+        B TIM5_IRQHandler
+
+        PUBWEAK SPI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler  
+        B SPI3_IRQHandler
+
+        PUBWEAK UART4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler  
+        B UART4_IRQHandler
+
+        PUBWEAK UART5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler  
+        B UART5_IRQHandler
+
+        PUBWEAK TIM6_DAC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)   
+TIM6_DAC_IRQHandler  
+        B TIM6_DAC_IRQHandler
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)   
+TIM7_IRQHandler  
+        B TIM7_IRQHandler
+
+        PUBWEAK DMA2_Stream0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA2_Stream0_IRQHandler  
+        B DMA2_Stream0_IRQHandler
+
+        PUBWEAK DMA2_Stream1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA2_Stream1_IRQHandler  
+        B DMA2_Stream1_IRQHandler
+
+        PUBWEAK DMA2_Stream2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA2_Stream2_IRQHandler  
+        B DMA2_Stream2_IRQHandler
+
+        PUBWEAK DMA2_Stream3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA2_Stream3_IRQHandler  
+        B DMA2_Stream3_IRQHandler
+
+        PUBWEAK DMA2_Stream4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA2_Stream4_IRQHandler  
+        B DMA2_Stream4_IRQHandler
+
+        PUBWEAK ETH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ETH_IRQHandler  
+        B ETH_IRQHandler
+
+        PUBWEAK ETH_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)  
+ETH_WKUP_IRQHandler  
+        B ETH_WKUP_IRQHandler
+
+        PUBWEAK FDCAN_CAL_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+FDCAN_CAL_IRQHandler  
+        B FDCAN_CAL_IRQHandler
+
+        PUBWEAK DMA2_Stream5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA2_Stream5_IRQHandler  
+        B DMA2_Stream5_IRQHandler
+
+        PUBWEAK DMA2_Stream6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA2_Stream6_IRQHandler  
+        B DMA2_Stream6_IRQHandler
+
+        PUBWEAK DMA2_Stream7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA2_Stream7_IRQHandler  
+        B DMA2_Stream7_IRQHandler
+
+        PUBWEAK USART6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART6_IRQHandler  
+        B USART6_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+I2C3_EV_IRQHandler  
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+I2C3_ER_IRQHandler  
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK OTG_HS_EP1_OUT_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+OTG_HS_EP1_OUT_IRQHandler  
+        B OTG_HS_EP1_OUT_IRQHandler
+
+        PUBWEAK OTG_HS_EP1_IN_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+OTG_HS_EP1_IN_IRQHandler  
+        B OTG_HS_EP1_IN_IRQHandler
+
+        PUBWEAK OTG_HS_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_WKUP_IRQHandler  
+        B OTG_HS_WKUP_IRQHandler
+
+        PUBWEAK OTG_HS_IRQHandler                
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_IRQHandler                  
+        B OTG_HS_IRQHandler                
+
+        PUBWEAK DCMI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_IRQHandler  
+        B DCMI_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)  
+RNG_IRQHandler  
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)  
+FPU_IRQHandler  
+        B FPU_IRQHandler
+
+        PUBWEAK UART7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)      
+UART7_IRQHandler 
+        B UART7_IRQHandler  
+
+        PUBWEAK UART8_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+UART8_IRQHandler             
+        B UART8_IRQHandler
+        
+        PUBWEAK SPI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+SPI4_IRQHandler
+        B SPI4_IRQHandler                 
+
+        PUBWEAK SPI5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+SPI5_IRQHandler   
+        B SPI5_IRQHandler                  
+
+        PUBWEAK SPI6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+SPI6_IRQHandler 
+        B SPI6_IRQHandler                    
+
+        PUBWEAK SAI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+SAI1_IRQHandler  
+        B SAI1_IRQHandler                  
+
+        PUBWEAK LTDC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+LTDC_IRQHandler 
+        B LTDC_IRQHandler                     
+
+        PUBWEAK LTDC_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+LTDC_ER_IRQHandler 
+        B LTDC_ER_IRQHandler                 
+
+        PUBWEAK DMA2D_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+DMA2D_IRQHandler 
+        B DMA2D_IRQHandler                  
+
+       PUBWEAK SAI2_IRQHandler
+       SECTION .text:CODE:NOROOT:REORDER(1) 
+SAI2_IRQHandler 
+        B SAI2_IRQHandler          
+
+       PUBWEAK QUADSPI_IRQHandler
+       SECTION .text:CODE:NOROOT:REORDER(1) 
+QUADSPI_IRQHandler 
+        B QUADSPI_IRQHandler       
+        
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+LPTIM1_IRQHandler 
+        B LPTIM1_IRQHandler   
+        
+        PUBWEAK CEC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+CEC_IRQHandler 
+        B CEC_IRQHandler 
+
+        PUBWEAK I2C4_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+I2C4_EV_IRQHandler 
+        B I2C4_EV_IRQHandler   
+        
+        PUBWEAK I2C4_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+I2C4_ER_IRQHandler 
+        B I2C4_ER_IRQHandler 
+ 
+        PUBWEAK SPDIF_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+SPDIF_RX_IRQHandler 
+        B SPDIF_RX_IRQHandler 
+
+        PUBWEAK OTG_FS_EP1_OUT_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+OTG_FS_EP1_OUT_IRQHandler 
+        B OTG_FS_EP1_OUT_IRQHandler 
+
+        PUBWEAK OTG_FS_EP1_IN_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+OTG_FS_EP1_IN_IRQHandler 
+        B OTG_FS_EP1_IN_IRQHandler
+
+        PUBWEAK OTG_FS_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+OTG_FS_WKUP_IRQHandler 
+        B OTG_FS_WKUP_IRQHandler
+
+        PUBWEAK OTG_FS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+OTG_FS_IRQHandler 
+        B OTG_FS_IRQHandler 
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+DMAMUX1_OVR_IRQHandler 
+        B DMAMUX1_OVR_IRQHandler 
+
+        PUBWEAK HRTIM1_Master_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+HRTIM1_Master_IRQHandler 
+        B HRTIM1_Master_IRQHandler 
+
+        PUBWEAK HRTIM1_TIMA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+HRTIM1_TIMA_IRQHandler 
+        B HRTIM1_TIMA_IRQHandler 
+
+        PUBWEAK HRTIM1_TIMB_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+HRTIM1_TIMB_IRQHandler 
+        B HRTIM1_TIMB_IRQHandler 
+
+        PUBWEAK HRTIM1_TIMC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+HRTIM1_TIMC_IRQHandler 
+        B HRTIM1_TIMC_IRQHandler 
+
+        PUBWEAK HRTIM1_TIMD_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+HRTIM1_TIMD_IRQHandler 
+        B HRTIM1_TIMD_IRQHandler
+
+        PUBWEAK HRTIM1_TIME_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+HRTIM1_TIME_IRQHandler 
+        B HRTIM1_TIME_IRQHandler
+
+        PUBWEAK HRTIM1_FLT_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+HRTIM1_FLT_IRQHandler 
+        B HRTIM1_FLT_IRQHandler
+
+        PUBWEAK DFSDM1_FLT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+DFSDM1_FLT0_IRQHandler 
+        B DFSDM1_FLT0_IRQHandler 
+
+        PUBWEAK DFSDM1_FLT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+DFSDM1_FLT1_IRQHandler 
+        B DFSDM1_FLT1_IRQHandler
+
+        PUBWEAK DFSDM1_FLT2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+DFSDM1_FLT2_IRQHandler 
+        B DFSDM1_FLT2_IRQHandler
+
+        PUBWEAK DFSDM1_FLT3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+DFSDM1_FLT3_IRQHandler 
+        B DFSDM1_FLT3_IRQHandler	
+
+        PUBWEAK SAI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+SAI3_IRQHandler 
+        B SAI3_IRQHandler
+
+        PUBWEAK SWPMI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+SWPMI1_IRQHandler 
+        B SWPMI1_IRQHandler
+
+        PUBWEAK TIM15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+TIM15_IRQHandler 
+        B TIM15_IRQHandler
+
+        PUBWEAK TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+TIM16_IRQHandler 
+        B TIM16_IRQHandler
+
+        PUBWEAK TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+TIM17_IRQHandler 
+        B TIM17_IRQHandler
+
+        PUBWEAK MDIOS_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+MDIOS_WKUP_IRQHandler 
+        B MDIOS_WKUP_IRQHandler
+
+        PUBWEAK MDIOS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+MDIOS_IRQHandler 
+        B MDIOS_IRQHandler
+
+        PUBWEAK JPEG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+JPEG_IRQHandler 
+        B JPEG_IRQHandler
+
+        PUBWEAK MDMA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+MDMA_IRQHandler 
+        B MDMA_IRQHandler
+
+        PUBWEAK SDMMC2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+SDMMC2_IRQHandler 
+        B SDMMC2_IRQHandler
+
+        PUBWEAK HSEM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+HSEM1_IRQHandler 
+        B HSEM1_IRQHandler
+
+        PUBWEAK ADC3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+ADC3_IRQHandler 
+        B ADC3_IRQHandler
+
+        PUBWEAK DMAMUX2_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+DMAMUX2_OVR_IRQHandler 
+        B DMAMUX2_OVR_IRQHandler
+
+        PUBWEAK BDMA_Channel0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+BDMA_Channel0_IRQHandler 
+        B BDMA_Channel0_IRQHandler
+
+        PUBWEAK BDMA_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+BDMA_Channel1_IRQHandler 
+        B BDMA_Channel1_IRQHandler
+
+        PUBWEAK BDMA_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+BDMA_Channel2_IRQHandler 
+        B BDMA_Channel2_IRQHandler
+
+        PUBWEAK BDMA_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+BDMA_Channel3_IRQHandler 
+        B BDMA_Channel3_IRQHandler
+
+        PUBWEAK BDMA_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+BDMA_Channel4_IRQHandler 
+        B BDMA_Channel4_IRQHandler
+
+        PUBWEAK BDMA_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+BDMA_Channel5_IRQHandler 
+        B BDMA_Channel5_IRQHandler
+
+        PUBWEAK BDMA_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+BDMA_Channel6_IRQHandler 
+        B BDMA_Channel6_IRQHandler
+
+        PUBWEAK BDMA_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+BDMA_Channel7_IRQHandler 
+        B BDMA_Channel7_IRQHandler
+
+        PUBWEAK COMP1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+COMP1_IRQHandler 
+        B COMP1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+LPTIM2_IRQHandler 
+        B LPTIM2_IRQHandler
+
+        PUBWEAK LPTIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+LPTIM3_IRQHandler 
+        B LPTIM3_IRQHandler
+
+        PUBWEAK LPTIM4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+LPTIM4_IRQHandler 
+        B LPTIM4_IRQHandler
+
+        PUBWEAK LPTIM5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+LPTIM5_IRQHandler 
+        B LPTIM5_IRQHandler	
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+LPUART1_IRQHandler 
+        B LPUART1_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+CRS_IRQHandler 
+        B CRS_IRQHandler
+
+        PUBWEAK ECC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+ECC_IRQHandler 
+        B ECC_IRQHandler
+
+        PUBWEAK SAI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+SAI4_IRQHandler 
+        B SAI4_IRQHandler
+
+        PUBWEAK WAKEUP_PIN_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+WAKEUP_PIN_IRQHandler 
+        B WAKEUP_PIN_IRQHandler 
+        END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/stm32h743xx_flash.icf b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/stm32h743xx_flash.icf
new file mode 100644
index 00000000..e031e915
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/stm32h743xx_flash.icf
@@ -0,0 +1,34 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__     = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__       = 0x0801FFFF;
+define symbol __ICFEDIT_region_RAM_start__     = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__       = 0x2001FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__   = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region  = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/usbd_bulk.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/usbd_bulk.c
new file mode 100644
index 00000000..0a6a001c
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/usbd_bulk.c
@@ -0,0 +1,400 @@
+/**
+  ******************************************************************************
+  * @file    usbd_bulk.c
+  * @author  MCD Application Team
+  * @version V2.4.2
+  * @date    11-December-2015
+  * @brief   This file provides the high layer firmware functions to manage a
+  *          USB bulk device.
+  *                                  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbd_bulk.h"
+#include "usbd_desc.h"
+#include "usbd_ctlreq.h"
+
+
+/** @addtogroup STM32_USB_DEVICE_LIBRARY
+  * @{
+  */
+
+
+/** @defgroup USBD_Bulk
+  * @brief usbd core module
+  * @{
+  */ 
+
+/** @defgroup USBD_Bulk_Private_TypesDefinitions
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup USBD_Bulk_Private_Defines
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup USBD_Bulk_Private_Macros
+  * @{
+  */ 
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup USBD_Bulk_Private_FunctionPrototypes
+  * @{
+  */
+extern void UsbReceivePipeBulkOUT(uint8_t epnum);
+extern void UsbTransmitPipeBulkIN(void);
+
+
+static uint8_t  USBD_Bulk_Init (USBD_HandleTypeDef *pdev,
+                                uint8_t cfgidx);
+
+static uint8_t  USBD_Bulk_DeInit (USBD_HandleTypeDef *pdev,
+                                  uint8_t cfgidx);
+
+static uint8_t  USBD_Bulk_Setup (USBD_HandleTypeDef *pdev,
+                                 USBD_SetupReqTypedef *req);
+
+static uint8_t  USBD_Bulk_DataIn (USBD_HandleTypeDef *pdev,
+                                  uint8_t epnum);
+
+static uint8_t  USBD_Bulk_DataOut (USBD_HandleTypeDef *pdev,
+                                  uint8_t epnum);
+
+static uint8_t USBD_Bulk_SOF (USBD_HandleTypeDef *pdev);
+
+static uint8_t  *USBD_Bulk_GetFSCfgDesc (uint16_t *length);
+
+uint8_t  *USBD_Bulk_GetDeviceQualifierDescriptor (uint16_t *length);
+
+/* USB Standard Device Descriptor */
+__ALIGN_BEGIN static uint8_t USBD_Bulk_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END =
+{
+  USB_LEN_DEV_QUALIFIER_DESC,
+  USB_DESC_TYPE_DEVICE_QUALIFIER,
+  0x00,
+  0x02,
+  0x00,
+  0x00,
+  0x00,
+  0x40,
+  0x01,
+  0x00,
+};
+
+/**
+  * @}
+  */ 
+
+/** @defgroup USBD_Bulk_Private_Variables
+  * @{
+  */ 
+#if defined ( __ICCARM__ ) /* IAR Compiler */
+  #pragma data_alignment=4
+#endif /* defined ( __ICCARM__ ) */
+__ALIGN_BEGIN static volatile uint32_t  usbd_bulk_AltSet  __ALIGN_END = 0;
+__ALIGN_BEGIN uint8_t USB_Rx_Buffer[BULK_DATA_MAX_PACKET_SIZE] __ALIGN_END ;
+
+
+/* Bulk interface class callbacks structure */
+USBD_ClassTypeDef  USBD_Bulk =
+{
+  USBD_Bulk_Init,
+  USBD_Bulk_DeInit,
+  USBD_Bulk_Setup,
+  NULL,
+  NULL,
+  USBD_Bulk_DataIn,
+  USBD_Bulk_DataOut,
+  USBD_Bulk_SOF,
+  NULL,
+  NULL,     
+  NULL,
+  USBD_Bulk_GetFSCfgDesc,
+  NULL,
+  USBD_Bulk_GetDeviceQualifierDescriptor,
+};
+
+/* USB Bulk device Configuration Descriptor */
+__ALIGN_BEGIN uint8_t USBD_Bulk_CfgFSDesc[USB_BULK_CONFIG_DESC_SIZ] __ALIGN_END =
+{
+  /*Configuration Descriptor*/
+  0x09,   /* bLength: Configuration Descriptor size */
+  USB_DESC_TYPE_CONFIGURATION,      /* bDescriptorType: Configuration */
+  USB_BULK_CONFIG_DESC_SIZ,                /* wTotalLength:no of returned bytes */
+  0x00,
+  0x01,   /* bNumInterfaces: 1 interface */
+  0x01,   /* bConfigurationValue: Configuration value */
+  0x00,   /* iConfiguration: Index of string descriptor describing the configuration */
+  0xC0,   /* bmAttributes: self powered */
+  0x32,   /* MaxPower 100 mA */
+  
+  /*---------------------------------------------------------------------------*/
+  
+  /*Interface Descriptor */
+  0x09,   /* bLength: Interface Descriptor size */
+  USB_DESC_TYPE_INTERFACE,  /* bDescriptorType: Interface */
+  /* Interface descriptor type */
+  0x00,   /* bInterfaceNumber: Number of Interface */
+  0x00,   /* bAlternateSetting: Alternate setting */
+  0x02,   /* bNumEndpoints: One endpoints used */
+  0xFF,   /* bInterfaceClass: vendor specific */
+  0x00,   /* bInterfaceSubClass  */
+  0x00,   /* bInterfaceProtocol */
+  0x00,   /* iInterface: */
+
+  /*Endpoint IN Descriptor*/
+  0x07,   /* bLength: Endpoint Descriptor size */
+  USB_DESC_TYPE_ENDPOINT,      /* bDescriptorType: Endpoint */
+  BULK_IN_EP,                         /* bEndpointAddress */
+  0x02,                              /* bmAttributes: Bulk */
+  LOBYTE(BULK_DATA_MAX_PACKET_SIZE),  /* wMaxPacketSize: */
+  HIBYTE(BULK_DATA_MAX_PACKET_SIZE),
+  0xFF,                               /* bInterval: ignore for Bulk transfer */
+  
+  /*Endpoint OUT Descriptor*/
+  0x07,   /* bLength: Endpoint Descriptor size */
+  USB_DESC_TYPE_ENDPOINT,      /* bDescriptorType: Endpoint */
+  BULK_OUT_EP,                        /* bEndpointAddress */
+  0x02,                              /* bmAttributes: Bulk */
+  LOBYTE(BULK_DATA_MAX_PACKET_SIZE),  /* wMaxPacketSize: */
+  HIBYTE(BULK_DATA_MAX_PACKET_SIZE),
+  0xFF                              /* bInterval: ignore for Bulk transfer */
+} ;
+
+
+/**
+  * @}
+  */ 
+
+/** @defgroup USBD_Bulk_Private_Functions
+  * @{
+  */ 
+
+/**
+  * @brief  USBD_Bulk_Init
+  *         Initialize the Bulk interface
+  * @param  pdev: device instance
+  * @param  cfgidx: Configuration index
+  * @retval status
+  */
+static uint8_t  USBD_Bulk_Init (USBD_HandleTypeDef *pdev,
+                                uint8_t cfgidx)
+{
+  uint8_t ret = 0;
+  
+  /* Open EP IN */
+  USBD_LL_OpenEP(pdev,
+                 BULK_IN_EP,
+                 USBD_EP_TYPE_BULK,
+                 BULK_DATA_FS_IN_PACKET_SIZE);
+
+  /* Open EP OUT */
+  USBD_LL_OpenEP(pdev,
+                 BULK_OUT_EP,
+                 USBD_EP_TYPE_BULK,
+                 BULK_DATA_FS_OUT_PACKET_SIZE);
+
+  /* Prepare Out endpoint to receive next packet */
+  USBD_LL_PrepareReceive(pdev,
+                         BULK_OUT_EP,
+                         &USB_Rx_Buffer[0],
+                         BULK_DATA_FS_OUT_PACKET_SIZE);
+  
+  return ret;
+}
+
+/**
+  * @brief  USBD_Bulk_DeInit
+  *         DeInitialize the Bulk layer
+  * @param  pdev: device instance
+  * @param  cfgidx: Configuration index
+  * @retval status
+  */
+static uint8_t  USBD_Bulk_DeInit (USBD_HandleTypeDef *pdev,
+                                  uint8_t cfgidx)
+{
+  uint8_t ret = 0;
+  
+  /* Close EP IN */
+  USBD_LL_CloseEP(pdev, BULK_IN_EP);
+  
+  /* lose EP OUT */
+  USBD_LL_CloseEP(pdev, BULK_OUT_EP);
+  
+  return ret;
+}
+
+/**
+  * @brief  USBD_Bulk_Setup
+  *         Handle the bulk specific requests
+  * @param  pdev: instance
+  * @param  req: usb requests
+  * @retval status
+  */
+static uint8_t  USBD_Bulk_Setup (USBD_HandleTypeDef *pdev,
+                                 USBD_SetupReqTypedef *req)
+{
+  uint16_t len=USB_BULK_DESC_SIZ;
+  uint8_t  *pbuf=USBD_Bulk_CfgFSDesc + 9;
+
+  switch (req->bmRequest & USB_REQ_TYPE_MASK)
+  {
+  case USB_REQ_TYPE_STANDARD:
+    switch (req->bRequest)
+    {
+    case USB_REQ_GET_DESCRIPTOR :
+      if ( (req->wValue >> 8) == BULK_DESCRIPTOR_TYPE)
+      {
+        pbuf = USBD_Bulk_CfgFSDesc + 9 + (9 * USBD_MAX_NUM_INTERFACES);
+        len = MIN(USB_BULK_DESC_SIZ , req->wLength);
+        
+      }
+      USBD_CtlSendData (pdev, pbuf, len);
+      break;
+
+    case USB_REQ_GET_INTERFACE :
+      USBD_CtlSendData (pdev,
+                        (uint8_t *)&usbd_bulk_AltSet,
+                        1);
+      break;
+      
+    case USB_REQ_SET_INTERFACE :
+      if ((uint8_t)(req->wValue) < USBD_MAX_NUM_INTERFACES)
+      {
+        usbd_bulk_AltSet = (uint8_t)(req->wValue);
+      }
+      else
+      {
+        /* Call the error management function (command will be nacked */
+        USBD_CtlError (pdev, req);
+      }
+      break;
+    }
+ 
+  default: 
+    break;
+  }
+  return USBD_OK;
+}
+
+/**
+  * @brief  USBD_Bulk_DataIn
+  *         Data sent on non-control IN endpoint
+  * @param  pdev: device instance
+  * @param  epnum: endpoint number
+  * @retval status
+  */
+static uint8_t  USBD_Bulk_DataIn (USBD_HandleTypeDef *pdev, uint8_t epnum)
+{
+  /* endpoint finished the previous transmission so see if more data is left */
+  UsbTransmitPipeBulkIN();
+  return USBD_OK;
+}
+
+/**
+  * @brief  USBD_Bulk_DataOut
+  *         Data received on non-control Out endpoint
+  * @param  pdev: device instance
+  * @param  epnum: endpoint number
+  * @retval status
+  */
+static uint8_t  USBD_Bulk_DataOut (USBD_HandleTypeDef *pdev, uint8_t epnum)
+{
+  /* read the data from the bulk OUT pipe */
+  UsbReceivePipeBulkOUT(epnum);
+  return USBD_OK;
+}
+
+/**
+  * @brief  USBD_Bulk_SOF
+  *         Start Of Frame event management
+  * @param  pdev: device instance
+  * @retval status
+  */
+static uint8_t USBD_Bulk_SOF (USBD_HandleTypeDef *pdev)
+{
+  if (pdev->dev_state == USBD_STATE_CONFIGURED )
+  {
+    /* Check the data to be sent through IN pipe */
+    UsbTransmitPipeBulkIN();
+  }
+  return USBD_OK;
+
+}
+
+/**
+  * @brief  USBD_Bulk_GetFSCfgDesc
+  *         Return configuration descriptor
+  * @param  speed : current device speed
+  * @param  length : pointer data length
+  * @retval pointer to descriptor buffer
+  */
+static uint8_t  *USBD_Bulk_GetFSCfgDesc (uint16_t *length)
+{
+  *length = sizeof (USBD_Bulk_CfgFSDesc);
+  return USBD_Bulk_CfgFSDesc;
+}
+
+/**
+* @brief  DeviceQualifierDescriptor 
+*         return Device Qualifier descriptor
+* @param  length : pointer data length
+* @retval pointer to descriptor buffer
+*/
+uint8_t  *USBD_Bulk_GetDeviceQualifierDescriptor (uint16_t *length)
+{
+  *length = sizeof (USBD_Bulk_DeviceQualifierDesc);
+  return USBD_Bulk_DeviceQualifierDesc;
+}
+
+/**
+  * @brief  USBD_Bulk_GetRxBufferPtr
+  * @retval Pointer to reception buffer.
+  */
+uint8_t * USBD_Bulk_GetRxBufferPtr(void)
+{
+  return &USB_Rx_Buffer[0];
+}
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/usbd_bulk.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/usbd_bulk.h
new file mode 100644
index 00000000..ee1d83de
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/usbd_bulk.h
@@ -0,0 +1,113 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    usbd_cdc.h
+  * @author  MCD Application Team
+  * @brief   header file for the usbd_bulk.c file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      http://www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_BULK_H
+#define __USB_BULK_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include  "usbd_ioreq.h"
+
+/** @addtogroup STM32_USB_DEVICE_LIBRARY
+  * @{
+  */
+
+/** @defgroup usbd_cdc
+  * @brief This file is the Header file for usbd_cdc.c
+  * @{
+  */
+
+
+/** @defgroup usbd_cdc_Exported_Defines
+  * @{
+  */ 
+#define BULK_IN_EP                                  0x81  /* EP1 for data IN */
+#define BULK_OUT_EP                                 0x01  /* EP1 for data OUT */
+
+/* CDC Endpoints parameters: you can fine tune these values depending on the needed baudrates and performance. */
+#define BULK_DATA_MAX_PACKET_SIZE                   64  /* Endpoint IN & OUT Packet size */
+
+#define USB_BULK_CONFIG_DESC_SIZ                    32
+#define USB_BULK_DESC_SIZ                           (32-9)
+
+#define BULK_DESCRIPTOR_TYPE                        0x21
+
+
+#define BULK_DATA_FS_IN_PACKET_SIZE                 BULK_DATA_MAX_PACKET_SIZE
+#define BULK_DATA_FS_OUT_PACKET_SIZE                BULK_DATA_MAX_PACKET_SIZE
+
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup USBD_CORE_Exported_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup USBD_CORE_Exported_Macros
+  * @{
+  */ 
+  
+/**
+  * @}
+  */ 
+
+/** @defgroup USBD_CORE_Exported_Variables
+  * @{
+  */ 
+
+extern USBD_ClassTypeDef   USBD_Bulk;
+/**
+  * @}
+  */ 
+
+/** @defgroup USB_CORE_Exported_Functions
+  * @{
+  */
+uint8_t * USBD_Bulk_GetRxBufferPtr(void);
+/**
+  * @}
+  */ 
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* __USB_BULK_H */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/usbd_conf.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/usbd_conf.c
new file mode 100644
index 00000000..357bb1d2
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/usbd_conf.c
@@ -0,0 +1,591 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : usbd_conf.c
+  * @version        : v1.0_Cube
+  * @brief          : This file implements the board support package for the USB device library
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+#include "stm32h7xx_hal.h"
+#include "usbd_def.h"
+#include "usbd_core.h"
+#include "usbd_bulk.h"
+#include "boot.h"
+#include "usb.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE END PV */
+
+PCD_HandleTypeDef hpcd_USB_OTG_FS;
+
+/* External functions --------------------------------------------------------*/
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* USER CODE BEGIN PFP */
+/* Private function prototypes -----------------------------------------------*/
+USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status);
+
+/* USER CODE END PFP */
+
+/* Private functions ---------------------------------------------------------*/
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/**
+  * @brief  Setup stage callback
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
+#else
+void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup);
+}
+
+/**
+  * @brief  Data Out stage callback.
+  * @param  hpcd: PCD handle
+  * @param  epnum: Endpoint number
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#else
+void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff);
+}
+
+/**
+  * @brief  Data In stage callback.
+  * @param  hpcd: PCD handle
+  * @param  epnum: Endpoint number
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#else
+void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff);
+}
+
+/**
+  * @brief  SOF callback.
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
+#else
+void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData);
+}
+
+/**
+  * @brief  Reset callback.
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
+#else
+void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{ 
+  USBD_SpeedTypeDef speed = USBD_SPEED_FULL;
+
+  if ( hpcd->Init.speed == PCD_SPEED_HIGH)
+  {
+    speed = USBD_SPEED_HIGH;
+  }
+  else if ( hpcd->Init.speed == PCD_SPEED_FULL)
+  {
+    speed = USBD_SPEED_FULL;
+  }
+  else
+  {
+    ASSERT_RT(BLT_FALSE);
+  }
+    /* Set Speed. */
+  USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed);
+
+  /* Reset Device. */
+  USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData);
+}
+
+/**
+  * @brief  Suspend callback.
+  * When Low power mode is enabled the debug cannot be used (IAR, Keil doesn't support it)
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
+#else
+void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  /* Inform USB library that core enters in suspend Mode. */
+  USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData);
+  __HAL_PCD_GATE_PHYCLOCK(hpcd);
+  /* Enter in STOP mode. */
+  /* USER CODE BEGIN 2 */
+  if (hpcd->Init.low_power_enable)
+  {
+    /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */
+    SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
+  }
+  /* Inform application that the USB entered low power mode. */
+  UsbEnterLowPowerModeHook();
+  /* USER CODE END 2 */
+}
+
+/**
+  * @brief  Resume callback.
+  * When Low power mode is enabled the debug cannot be used (IAR, Keil doesn't support it)
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
+#else
+void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  /* USER CODE BEGIN 3 */
+  /* Inform application that the USB left low power mode. */
+  UsbLeaveLowPowerModeHook();
+  /* USER CODE END 3 */
+  USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData);
+}
+
+/**
+  * @brief  ISOOUTIncomplete callback.
+  * @param  hpcd: PCD handle
+  * @param  epnum: Endpoint number
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#else
+void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  USBD_LL_IsoOUTIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum);
+}
+
+/**
+  * @brief  ISOINIncomplete callback.
+  * @param  hpcd: PCD handle
+  * @param  epnum: Endpoint number
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#else
+void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  USBD_LL_IsoINIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum);
+}
+
+/**
+  * @brief  Connect callback.
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
+#else
+void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  /* Configure Low connection state. */
+  UsbConnectHook(BLT_TRUE);
+  /* Inform lower layer. */
+  USBD_LL_DevConnected((USBD_HandleTypeDef*)hpcd->pData);
+}
+
+/**
+  * @brief  Disconnect callback.
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
+#else
+void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  /* Configure High connection state. */
+  UsbConnectHook(BLT_FALSE);
+  /* Inform lower layer. */
+  USBD_LL_DevDisconnected((USBD_HandleTypeDef*)hpcd->pData);
+}
+
+/*******************************************************************************
+                       LL Driver Interface (USB Device Library --> PCD)
+*******************************************************************************/
+
+/**
+  * @brief  Initializes the low level portion of the device driver.
+  * @param  pdev: Device handle
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)
+{
+  /* Init USB Ip. */
+  if (pdev->id == DEVICE_FS) {
+  /* Link the driver to the stack. */
+  hpcd_USB_OTG_FS.pData = pdev;
+  pdev->pData = &hpcd_USB_OTG_FS;
+  
+  hpcd_USB_OTG_FS.Instance = USB_OTG_FS;
+  hpcd_USB_OTG_FS.Init.dev_endpoints = 9;
+  hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL;
+  hpcd_USB_OTG_FS.Init.dma_enable = DISABLE;
+  hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED;
+  hpcd_USB_OTG_FS.Init.Sof_enable = ENABLE;
+  hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE;
+  hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE;
+  hpcd_USB_OTG_FS.Init.battery_charging_enable = DISABLE;
+  hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE;
+  hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE;
+  if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK)
+  {
+    ASSERT_RT(BLT_FALSE);
+  }
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+  /* Register USB PCD CallBacks */
+  HAL_PCD_RegisterCallback(&hpcd_USB_OTG_FS, HAL_PCD_SOF_CB_ID, PCD_SOFCallback);
+  HAL_PCD_RegisterCallback(&hpcd_USB_OTG_FS, HAL_PCD_SETUPSTAGE_CB_ID, PCD_SetupStageCallback);
+  HAL_PCD_RegisterCallback(&hpcd_USB_OTG_FS, HAL_PCD_RESET_CB_ID, PCD_ResetCallback);
+  HAL_PCD_RegisterCallback(&hpcd_USB_OTG_FS, HAL_PCD_SUSPEND_CB_ID, PCD_SuspendCallback);
+  HAL_PCD_RegisterCallback(&hpcd_USB_OTG_FS, HAL_PCD_RESUME_CB_ID, PCD_ResumeCallback);
+  HAL_PCD_RegisterCallback(&hpcd_USB_OTG_FS, HAL_PCD_CONNECT_CB_ID, PCD_ConnectCallback);
+  HAL_PCD_RegisterCallback(&hpcd_USB_OTG_FS, HAL_PCD_DISCONNECT_CB_ID, PCD_DisconnectCallback);
+
+  HAL_PCD_RegisterDataOutStageCallback(&hpcd_USB_OTG_FS, PCD_DataOutStageCallback);
+  HAL_PCD_RegisterDataInStageCallback(&hpcd_USB_OTG_FS, PCD_DataInStageCallback);
+  HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOOUTIncompleteCallback);
+  HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOINIncompleteCallback);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+  HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_FS, 0x80);
+  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 0, 0x40);
+  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x80);
+  }
+  return USBD_OK;
+}
+
+/**
+  * @brief  De-Initializes the low level portion of the device driver.
+  * @param  pdev: Device handle
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_DeInit(USBD_HandleTypeDef *pdev)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+
+  hal_status = HAL_PCD_DeInit(pdev->pData);
+
+  usb_status =  USBD_Get_USB_Status(hal_status);
+  
+  return usb_status; 
+}
+
+/**
+  * @brief  Starts the low level portion of the device driver. 
+  * @param  pdev: Device handle
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+ 
+  hal_status = HAL_PCD_Start(pdev->pData);
+  
+  usb_status =  USBD_Get_USB_Status(hal_status);     
+  
+  return usb_status;
+}
+
+/**
+  * @brief  Stops the low level portion of the device driver.
+  * @param  pdev: Device handle
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_Stop(USBD_HandleTypeDef *pdev)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+
+  hal_status = HAL_PCD_Stop(pdev->pData);
+  
+  usb_status =  USBD_Get_USB_Status(hal_status);
+ 
+  return usb_status;
+}
+
+/**
+  * @brief  Opens an endpoint of the low level driver.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @param  ep_type: Endpoint type
+  * @param  ep_mps: Endpoint max packet size
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+
+  hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type);
+
+  usb_status =  USBD_Get_USB_Status(hal_status);
+  
+  return usb_status;
+}
+
+/**
+  * @brief  Closes an endpoint of the low level driver.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+  
+  hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr);
+  
+  usb_status =  USBD_Get_USB_Status(hal_status);    
+ 
+  return usb_status;  
+}
+
+/**
+  * @brief  Flushes an endpoint of the Low Level Driver.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_FlushEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+  
+  hal_status = HAL_PCD_EP_Flush(pdev->pData, ep_addr);
+  
+  usb_status =  USBD_Get_USB_Status(hal_status);   
+  
+  return usb_status;  
+}
+
+/**
+  * @brief  Sets a Stall condition on an endpoint of the Low Level Driver.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+  
+  hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr);
+
+  usb_status =  USBD_Get_USB_Status(hal_status);
+  
+  return usb_status;  
+}
+
+/**
+  * @brief  Clears a Stall condition on an endpoint of the Low Level Driver.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+  
+  hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr);
+    
+  usb_status =  USBD_Get_USB_Status(hal_status);  
+  
+  return usb_status; 
+}
+
+/**
+  * @brief  Returns Stall condition.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @retval Stall (1: Yes, 0: No)
+  */
+uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+{
+  PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData;
+  
+  if((ep_addr & 0x80) == 0x80)
+  {
+    return hpcd->IN_ep[ep_addr & 0x7F].is_stall; 
+  }
+  else
+  {
+    return hpcd->OUT_ep[ep_addr & 0x7F].is_stall; 
+  }
+}
+
+/**
+  * @brief  Assigns a USB address to the device.
+  * @param  pdev: Device handle
+  * @param  dev_addr: Device address
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+  
+  hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr);
+  
+  usb_status =  USBD_Get_USB_Status(hal_status);
+  
+  return usb_status;  
+}
+
+/**
+  * @brief  Transmits data over an endpoint.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @param  pbuf: Pointer to data to be sent
+  * @param  size: Data size    
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+
+  hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size);
+  
+  usb_status =  USBD_Get_USB_Status(hal_status); 
+  
+  return usb_status;    
+}
+
+/**
+  * @brief  Prepares an endpoint for reception.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @param  pbuf: Pointer to data to be received
+  * @param  size: Data size
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+
+  hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size);
+  
+  usb_status =  USBD_Get_USB_Status(hal_status);   
+  
+  return usb_status; 
+}
+
+/**
+  * @brief  Returns the last transfered packet size.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @retval Recived Data Size
+  */
+uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+{
+  return HAL_PCD_EP_GetRxCount((PCD_HandleTypeDef*) pdev->pData, ep_addr);
+}
+
+/**
+  * @brief  Delays routine for the USB Device Library.
+  * @param  Delay: Delay in ms
+  * @retval None
+  */
+void USBD_LL_Delay(uint32_t Delay)
+{
+  HAL_Delay(Delay);
+}
+
+/**
+  * @brief  Retuns the USB status depending on the HAL status:
+  * @param  hal_status: HAL status
+  * @retval USB status
+  */
+USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status)
+{
+  USBD_StatusTypeDef usb_status = USBD_OK;
+
+  switch (hal_status)
+  {
+    case HAL_OK :
+      usb_status = USBD_OK;
+    break;
+    case HAL_ERROR :
+      usb_status = USBD_FAIL;
+    break;
+    case HAL_BUSY :
+      usb_status = USBD_BUSY;
+    break;
+    case HAL_TIMEOUT :
+      usb_status = USBD_FAIL;
+    break;
+    default :
+      usb_status = USBD_FAIL;
+    break;
+  }
+  return usb_status;
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/usbd_conf.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/usbd_conf.h
new file mode 100644
index 00000000..cee15fdc
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/usbd_conf.h
@@ -0,0 +1,175 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : usbd_conf.h
+  * @version        : v1.0_Cube
+  * @brief          : Header for usbd_conf.c file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USBD_CONF__H__
+#define __USBD_CONF__H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include "stm32h7xx.h"
+#include "stm32h7xx_hal.h"
+
+/* USER CODE BEGIN INCLUDE */
+
+/* USER CODE END INCLUDE */
+
+/** @addtogroup USBD_OTG_DRIVER
+  * @{
+  */
+
+/** @defgroup USBD_CONF USBD_CONF
+  * @brief Configuration file for Usb otg low level driver.
+  * @{
+  */
+
+/** @defgroup USBD_CONF_Exported_Variables USBD_CONF_Exported_Variables
+  * @brief Public variables.
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_CONF_Exported_Defines USBD_CONF_Exported_Defines
+  * @brief Defines for configuration of the Usb device.
+  * @{
+  */
+
+/*---------- -----------*/
+#define USBD_MAX_NUM_INTERFACES     1U
+/*---------- -----------*/
+#define USBD_MAX_NUM_CONFIGURATION     1U
+/*---------- -----------*/
+#define USBD_MAX_STR_DESC_SIZ     512U
+/*---------- -----------*/
+#define USBD_DEBUG_LEVEL     0U
+/*---------- -----------*/
+#define USBD_LPM_ENABLED     0U
+/*---------- -----------*/
+#define USBD_SELF_POWERED     1U
+
+/****************************************/
+/* #define for FS and HS identification */
+#define DEVICE_FS 		0
+#define DEVICE_HS 		1
+
+/* Inform USB core that a full speed device is used. */
+#define USE_USB_FS
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_CONF_Exported_Macros USBD_CONF_Exported_Macros
+  * @brief Aliases.
+  * @{
+  */
+
+/* Memory management macros */
+
+/** Alias for memory allocation. */
+#define USBD_malloc         malloc
+
+/** Alias for memory release. */
+#define USBD_free           free
+
+/** Alias for memory set. */
+#define USBD_memset         memset
+
+/** Alias for memory copy. */
+#define USBD_memcpy         memcpy
+
+/** Alias for delay. */
+#define USBD_Delay          HAL_Delay
+
+/* DEBUG macros */
+
+#if (USBD_DEBUG_LEVEL > 0)
+#define USBD_UsrLog(...)    printf(__VA_ARGS__);\
+                            printf("\n");
+#else
+#define USBD_UsrLog(...)
+#endif
+
+#if (USBD_DEBUG_LEVEL > 1)
+
+#define USBD_ErrLog(...)    printf("ERROR: ") ;\
+                            printf(__VA_ARGS__);\
+                            printf("\n");
+#else
+#define USBD_ErrLog(...)
+#endif
+
+#if (USBD_DEBUG_LEVEL > 2)
+#define USBD_DbgLog(...)    printf("DEBUG : ") ;\
+                            printf(__VA_ARGS__);\
+                            printf("\n");
+#else
+#define USBD_DbgLog(...)
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_CONF_Exported_Types USBD_CONF_Exported_Types
+  * @brief Types.
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_CONF_Exported_FunctionsPrototype USBD_CONF_Exported_FunctionsPrototype
+  * @brief Declaration of public functions for Usb device.
+  * @{
+  */
+
+/* Exported functions -------------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USBD_CONF__H__ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/usbd_desc.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/usbd_desc.c
new file mode 100644
index 00000000..464ac5cc
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/usbd_desc.c
@@ -0,0 +1,395 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : usbd_desc.c
+  * @version        : v1.0_Cube
+  * @brief          : This file implements the USB device descriptors.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbd_core.h"
+#include "usbd_desc.h"
+#include "usbd_conf.h"
+
+/* USER CODE BEGIN INCLUDE */
+
+/* USER CODE END INCLUDE */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE END PV */
+
+/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
+  * @{
+  */
+
+/** @addtogroup USBD_DESC
+  * @{
+  */
+
+/** @defgroup USBD_DESC_Private_TypesDefinitions USBD_DESC_Private_TypesDefinitions
+  * @brief Private types.
+  * @{
+  */
+
+/* USER CODE BEGIN PRIVATE_TYPES */
+
+/* USER CODE END PRIVATE_TYPES */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Private_Defines USBD_DESC_Private_Defines
+  * @brief Private defines.
+  * @{
+  */
+
+#define USBD_VID     0x1d50
+#define USBD_LANGID_STRING     1033
+#define USBD_MANUFACTURER_STRING     "OpenBLT User"
+#define USBD_PID_FS     0x60ac
+#define USBD_PRODUCT_STRING_FS     "WinUSB Bulk Device"
+#define USBD_CONFIGURATION_STRING_FS     "Default"
+#define USBD_INTERFACE_STRING_FS     "WinUSB Bulk Interface"
+
+/* USER CODE BEGIN PRIVATE_DEFINES */
+
+/* USER CODE END PRIVATE_DEFINES */
+
+/**
+  * @}
+  */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/** @defgroup USBD_DESC_Private_Macros USBD_DESC_Private_Macros
+  * @brief Private macros.
+  * @{
+  */
+
+/* USER CODE BEGIN PRIVATE_MACRO */
+
+/* USER CODE END PRIVATE_MACRO */
+
+/**
+  * @}
+  */
+  
+/** @defgroup USBD_DESC_Private_FunctionPrototypes USBD_DESC_Private_FunctionPrototypes
+  * @brief Private functions declaration.
+  * @{
+  */
+  
+static void Get_SerialNum(void);
+static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len);
+  
+/**
+  * @}
+  */  
+  
+
+/** @defgroup USBD_DESC_Private_FunctionPrototypes USBD_DESC_Private_FunctionPrototypes
+  * @brief Private functions declaration for FS.
+  * @{
+  */
+
+uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Private_Variables USBD_DESC_Private_Variables
+  * @brief Private variables.
+  * @{
+  */
+
+USBD_DescriptorsTypeDef FS_Desc =
+{
+  USBD_FS_DeviceDescriptor
+, USBD_FS_LangIDStrDescriptor
+, USBD_FS_ManufacturerStrDescriptor
+, USBD_FS_ProductStrDescriptor
+, USBD_FS_SerialStrDescriptor
+, USBD_FS_ConfigStrDescriptor
+, USBD_FS_InterfaceStrDescriptor
+};
+
+#if defined ( __ICCARM__ ) /* IAR Compiler */
+  #pragma data_alignment=4
+#endif /* defined ( __ICCARM__ ) */
+/** USB standard device descriptor. */
+__ALIGN_BEGIN uint8_t USBD_FS_DeviceDesc[USB_LEN_DEV_DESC] __ALIGN_END =
+{
+  0x12,                       /*bLength */
+  USB_DESC_TYPE_DEVICE,       /*bDescriptorType*/
+  0x00,                       /*bcdUSB */
+  0x02,
+  0x00,                       /*bDeviceClass*/
+  0x00,                       /*bDeviceSubClass*/
+  0x00,                       /*bDeviceProtocol*/
+  USB_MAX_EP0_SIZE,           /*bMaxPacketSize*/
+  LOBYTE(USBD_VID),           /*idVendor*/
+  HIBYTE(USBD_VID),           /*idVendor*/
+  LOBYTE(USBD_PID_FS),        /*idProduct*/
+  HIBYTE(USBD_PID_FS),        /*idProduct*/
+  0x00,                       /*bcdDevice rel. 2.00*/
+  0x02,
+  USBD_IDX_MFC_STR,           /*Index of manufacturer  string*/
+  USBD_IDX_PRODUCT_STR,       /*Index of product string*/
+  USBD_IDX_SERIAL_STR,        /*Index of serial number string*/
+  USBD_MAX_NUM_CONFIGURATION  /*bNumConfigurations*/
+};
+
+/* USB_DeviceDescriptor */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Private_Variables USBD_DESC_Private_Variables
+  * @brief Private variables.
+  * @{
+  */
+
+#if defined ( __ICCARM__ ) /* IAR Compiler */
+  #pragma data_alignment=4
+#endif /* defined ( __ICCARM__ ) */
+
+/** USB lang indentifier descriptor. */
+__ALIGN_BEGIN uint8_t USBD_LangIDDesc[USB_LEN_LANGID_STR_DESC] __ALIGN_END =
+{
+     USB_LEN_LANGID_STR_DESC,
+     USB_DESC_TYPE_STRING,
+     LOBYTE(USBD_LANGID_STRING),
+     HIBYTE(USBD_LANGID_STRING)
+};
+
+#if defined ( __ICCARM__ ) /* IAR Compiler */
+  #pragma data_alignment=4
+#endif /* defined ( __ICCARM__ ) */
+/* Internal string descriptor. */
+__ALIGN_BEGIN uint8_t USBD_StrDesc[USBD_MAX_STR_DESC_SIZ] __ALIGN_END;
+
+#if defined ( __ICCARM__ ) /*!< IAR Compiler */
+  #pragma data_alignment=4   
+#endif
+__ALIGN_BEGIN uint8_t USBD_StringSerial[USB_SIZ_STRING_SERIAL] __ALIGN_END = {
+  USB_SIZ_STRING_SERIAL,
+  USB_DESC_TYPE_STRING,
+};
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Private_Functions USBD_DESC_Private_Functions
+  * @brief Private functions.
+  * @{
+  */
+
+/**
+  * @brief  Return the device descriptor
+  * @param  speed : Current device speed
+  * @param  length : Pointer to data length variable
+  * @retval Pointer to descriptor buffer
+  */
+uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+{
+  UNUSED(speed);
+  *length = sizeof(USBD_FS_DeviceDesc);
+  return USBD_FS_DeviceDesc;
+}
+
+/**
+  * @brief  Return the LangID string descriptor
+  * @param  speed : Current device speed
+  * @param  length : Pointer to data length variable
+  * @retval Pointer to descriptor buffer
+  */
+uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+{
+  UNUSED(speed);
+  *length = sizeof(USBD_LangIDDesc);
+  return USBD_LangIDDesc;
+}
+
+/**
+  * @brief  Return the product string descriptor
+  * @param  speed : Current device speed
+  * @param  length : Pointer to data length variable
+  * @retval Pointer to descriptor buffer
+  */
+uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+{
+  if(speed == 0)
+  {
+    USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length);
+  }
+  else
+  {
+    USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length);
+  }
+  return USBD_StrDesc;
+}
+
+/**
+  * @brief  Return the manufacturer string descriptor
+  * @param  speed : Current device speed
+  * @param  length : Pointer to data length variable
+  * @retval Pointer to descriptor buffer
+  */
+uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+{
+  UNUSED(speed);
+  USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length);
+  return USBD_StrDesc;
+}
+
+/**
+  * @brief  Return the serial number string descriptor
+  * @param  speed : Current device speed
+  * @param  length : Pointer to data length variable
+  * @retval Pointer to descriptor buffer
+  */
+uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+{
+  UNUSED(speed);
+  *length = USB_SIZ_STRING_SERIAL;
+
+  /* Update the serial number string descriptor with the data from the unique
+   * ID */
+  Get_SerialNum();
+  /* USER CODE BEGIN USBD_FS_SerialStrDescriptor */
+  
+  /* USER CODE END USBD_FS_SerialStrDescriptor */
+  return (uint8_t *) USBD_StringSerial;
+}
+
+/**
+  * @brief  Return the configuration string descriptor
+  * @param  speed : Current device speed
+  * @param  length : Pointer to data length variable
+  * @retval Pointer to descriptor buffer
+  */
+uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+{
+  if(speed == USBD_SPEED_HIGH)
+  {
+    USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length);
+  }
+  else
+  {
+    USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length);
+  }
+  return USBD_StrDesc;
+}
+
+/**
+  * @brief  Return the interface string descriptor
+  * @param  speed : Current device speed
+  * @param  length : Pointer to data length variable
+  * @retval Pointer to descriptor buffer
+  */
+uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+{
+  if(speed == 0)
+  {
+    USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length);
+  }
+  else
+  {
+    USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length);
+  }
+  return USBD_StrDesc;
+}
+
+/**
+  * @brief  Create the serial number string descriptor 
+  * @param  None 
+  * @retval None
+  */
+static void Get_SerialNum(void)
+{
+  uint32_t deviceserial0, deviceserial1, deviceserial2;
+
+  deviceserial0 = *(uint32_t *) DEVICE_ID1;
+  deviceserial1 = *(uint32_t *) DEVICE_ID2;
+  deviceserial2 = *(uint32_t *) DEVICE_ID3;
+
+  deviceserial0 += deviceserial2;
+
+  if (deviceserial0 != 0)
+  {
+    IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8);
+    IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4);
+  }
+}
+
+/**
+  * @brief  Convert Hex 32Bits value into char 
+  * @param  value: value to convert
+  * @param  pbuf: pointer to the buffer 
+  * @param  len: buffer length
+  * @retval None
+  */
+static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len)
+{
+  uint8_t idx = 0;
+
+  for (idx = 0; idx < len; idx++)
+  {
+    if (((value >> 28)) < 0xA)
+    {
+      pbuf[2 * idx] = (value >> 28) + '0';
+    }
+    else
+    {
+      pbuf[2 * idx] = (value >> 28) + 'A' - 10;
+    }
+
+    value = value << 4;
+
+    pbuf[2 * idx + 1] = 0;
+  }
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/usbd_desc.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/usbd_desc.h
new file mode 100644
index 00000000..0c6619fd
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Boot/usbd_desc.h
@@ -0,0 +1,145 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : usbd_desc.c
+  * @version        : v1.0_Cube
+  * @brief          : Header for usbd_conf.c file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */  
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USBD_DESC__C__
+#define __USBD_DESC__C__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbd_def.h"
+
+/* USER CODE BEGIN INCLUDE */
+
+/* USER CODE END INCLUDE */
+
+/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
+  * @{
+  */
+
+/** @defgroup USBD_DESC USBD_DESC
+  * @brief Usb device descriptors module.
+  * @{
+  */
+  
+/** @defgroup USBD_DESC_Exported_Constants USBD_DESC_Exported_Constants
+  * @brief Constants.
+  * @{
+  */
+#define         DEVICE_ID1          (UID_BASE)
+#define         DEVICE_ID2          (UID_BASE + 0x4)
+#define         DEVICE_ID3          (UID_BASE + 0x8)
+
+#define  USB_SIZ_STRING_SERIAL       0x1A
+
+/* USER CODE BEGIN EXPORTED_CONSTANTS */
+
+/* USER CODE END EXPORTED_CONSTANTS */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Exported_Defines USBD_DESC_Exported_Defines
+  * @brief Defines.
+  * @{
+  */
+
+/* USER CODE BEGIN EXPORTED_DEFINES */
+
+/* USER CODE END EXPORTED_DEFINES */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Exported_TypesDefinitions USBD_DESC_Exported_TypesDefinitions
+  * @brief Types.
+  * @{
+  */
+
+/* USER CODE BEGIN EXPORTED_TYPES */
+
+/* USER CODE END EXPORTED_TYPES */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Exported_Macros USBD_DESC_Exported_Macros
+  * @brief Aliases.
+  * @{
+  */
+
+/* USER CODE BEGIN EXPORTED_MACRO */
+
+/* USER CODE END EXPORTED_MACRO */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Exported_Variables USBD_DESC_Exported_Variables
+  * @brief Public variables.
+  * @{
+  */
+
+/** Descriptor for the Usb device. */
+extern USBD_DescriptorsTypeDef FS_Desc;
+
+/* USER CODE BEGIN EXPORTED_VARIABLES */
+
+/* USER CODE END EXPORTED_VARIABLES */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Exported_FunctionsPrototype USBD_DESC_Exported_FunctionsPrototype
+  * @brief Public functions declaration.
+  * @{
+  */
+
+/* USER CODE BEGIN EXPORTED_FUNCTIONS */
+
+/* USER CODE END EXPORTED_FUNCTIONS */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USBD_DESC__C__ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/bin/demoprog_stm32h743.out b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/bin/demoprog_stm32h743.out
new file mode 100644
index 00000000..d90dd3da
Binary files /dev/null and b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/bin/demoprog_stm32h743.out differ
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/bin/demoprog_stm32h743.srec b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/bin/demoprog_stm32h743.srec
new file mode 100644
index 00000000..7da8a6af
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/bin/demoprog_stm32h743.srec
@@ -0,0 +1,1167 @@
+S01A000064656D6F70726F675F73746D3332683734332E737265638F
+S3150802000090050020294602087D4602088146020814
+S3150802001085460208894602088D4602080000000045
+S3150802002000000000000000000000000091460208DF
+S31508020030954602080000000099460208B1360208F1
+S315080200409D460208A1460208A5460208A9460208D4
+S31508020050AD460208B1460208B5460208B946020884
+S31508020060BD460208C1460208C5460208C946020834
+S31508020070CD460208D1460208D5460208D9460208E4
+S31508020080DD460208E1460208E5460208E946020894
+S31508020090ED460208F1460208F5460208F946020844
+S315080200A0FD460208014702080547020809470208F1
+S315080200B00D470208114702081547020819470208A0
+S315080200C01D47020821470208254702082947020850
+S315080200D02D47020831470208354702083947020800
+S315080200E03D4702084147020800000000454702084A
+S315080200F0494702084D470208514702085547020870
+S31508020100594702085D47020861470208654702081F
+S31508020110694702086D4702087147020875470208CF
+S31508020120794702087D47020881470208854702087F
+S31508020130894702088D47020891470208954702082F
+S31508020140000000000000000000000000000000009F
+S31508020150994702089D470208A1470208A5470208CF
+S31508020160A9470208AD470208B1470208B54702087F
+S31508020170B9470208BD470208C14702080000000045
+S31508020180C5470208C9470208CD470208D1470208EF
+S31508020190D5470208D9470208DD470208E14702089F
+S315080201A0E5470208E9470208ED470208F14702084F
+S315080201B0F5470208F9470208FD47020801480208FE
+S315080201C005480208094802080D48020811480208AB
+S315080201D015480208194802081D480208214802085B
+S315080201E025480208294802082D480208314802080B
+S315080201F035480208394802083D48020841480208BB
+S3150802020045480208494802084D480208514802086A
+S3150802021055480208594802085D480208614802081A
+S3150802022065480208694802086D480208000000008D
+S315080202307148020875480208000000007948020859
+S315080202407D4802088148020885480208894802084A
+S315080202508D480208914802089548020899480208FA
+S315080202609D480208A1480208A5480208A9480208AA
+S31508020270AD480208B1480208B54802080000000065
+S31508020280B9480208BD480208C14802080000000031
+S3150802029000000000C5480208EE11AA5510B5040070
+S315080202A0002C01D1012037E0A0690028FFD1D4F83B
+S315080202B08000002805D1002084F87C00200001F087
+S315080202C0D1FC2420C4F88000206800684008400059
+S315080202D021680860200000F0B5F8012801D1012044
+S315080202E01AE0A06A002802D0200001F0B3FB2068B9
+S315080202F0406830F49040216848602068806830F091
+S315080203002A00216888602068006850F00100216888
+S315080203100860200001F00BFC10BD2DE9F843060029
+S315080203200D0014001F00D6F88400202840F08780AC
+S31508020330002D03D0200080B2002801D101207FE0E1
+S3150802034096F87C00012801D1022079E0012086F87E
+S315080203507C000020C6F888002220C6F8840001F036
+S315080203609FFC8046A6F85C40A6F85E40B068B0F5E9
+S31508020370805F0BD13069002804D140F2FF10A6F83D
+S31508020380600023E0FF20A6F860001FE0B06800289E
+S315080203900AD13069002803D1FF20A6F8600015E0CB
+S315080203A07F20A6F8600011E0B068B0F1805F0AD13C
+S315080203B03069002803D17F20A6F8600006E03F20B6
+S315080203C0A6F8600002E00020A6F86000B6F8609081
+S315080203D0B068B0F5805F04D13069002801D10024E5
+S315080203E016E02C00002513E03068406A19EA00007E
+S315080203F02070641C07E0002CF6D13068406A19EABE
+S3150802040000002880AD1CB6F85E00401EA6F85E0005
+S31508020410B6F85E0000280AD000974346002220213B
+S31508020420300001F0BBFB0028E5D0032008E02020BD
+S31508020430C6F88400002086F87C00002000E002202E
+S31508020440BDE8F283F8B586B0040000260025002030
+S31508020450DFF8A02221689142FFD0A36821690B43E5
+S3150802046061690B43E1690B43616E0B4321680F68AF
+S31508020470DFF884120F403B4321680B6021684B6802
+S3150802048033F44053E1680B4321684B60A369216842
+S31508020490914201D0216A0B4321688F68DFF85C120A
+S315080204A00F403B4321688B602168CB6A1B091B01FD
+S315080204B0616A0B432168CB622168914B99421ED12E
+S315080204C09049096811F0380100290AD008290AD08A
+S315080204D010290AD018290AD020290AD028290AD090
+S315080204E00BE001272FE104272DE108272BE110272E
+S315080204F029E1202727E1402725E1802723E12168F2
+S31508020500814B99421CD17F49096811F007010029DC
+S3150802051008D002290AD007D304290BD008D3052903
+S315080205200AD00BE000270EE104270CE108270AE1AE
+S31508020530102708E1202706E1402704E1802702E187
+S315080205402168724B99421CD16E49096811F007015C
+S31508020550002908D002290AD007D304290BD008D3C8
+S3150802056005290AD00BE00027EDE00427EBE008276F
+S31508020570E9E01027E7E02027E5E04027E3E08027C7
+S31508020580E1E02168624B99421CD15E49096811F083
+S315080205900701002908D002290AD007D304290BD05B
+S315080205A008D305290AD00BE00027CCE00427CAE0C5
+S315080205B00827C8E01027C6E02027C4E04027C2E083
+S315080205C08027C0E02168534B99421CD14D490968DE
+S315080205D011F00701002908D002290AD007D30429F5
+S315080205E00BD008D305290AD00BE00027ABE0042775
+S315080205F0A9E00827A7E01027A5E02027A3E04027BF
+S31508020600A1E080279FE02168434B99421ED13D49CC
+S31508020610096811F0380100290AD008290AD01029D8
+S315080206200AD018290AD020290AD028290AD00BE08C
+S31508020630012788E0042786E0082784E0102782E05D
+S31508020640202780E040277EE080277CE02168334B24
+S3150802065099421CD12B49096811F00701002908D0D3
+S3150802066002290AD007D304290BD008D305290AD0B0
+S315080206700BE0002767E0042765E0082763E01027F8
+S3150802068061E020275FE040275DE080275BE0216884
+S31508020690234B99421CD11B49096811F0070100290D
+S315080206A008D002290AD007D304290BD008D3052972
+S315080206B00AD00BE0002746E0042744E0082742E078
+S315080206C0102740E020273EE040273CE080273AE01A
+S315080206D02168914236D11349096811F007010029A8
+S315080206E022D0022924D021D3042925D022D30529B0
+S315080206F024D025E0000C0058F369FFCFFFF4FF1160
+S31508020700001001405444025800440040004800408A
+S31508020710004C0040005000400014014000780040A0
+S31508020720007C00405844025802270CE004270AE0DD
+S31508020730082708E0102706E0202704E0402702E001
+S31508020740802700E080272168914240F05F843900C3
+S31508020750C9B202290ED0042950D0082900F0938084
+S31508020760102900F0D580202900F06181402900F087
+S31508020770A181E2E101F09AFA0100606A002801D13A
+S31508020780012038E0606A012801D1022033E0606A5C
+S31508020790022801D104202EE0606A032801D106202E
+S315080207A029E0606A042801D1082024E0606A052845
+S315080207B001D10A201FE0606A062801D10C201AE03E
+S315080207C0606A072801D1102015E0606A082801D15D
+S315080207D0202010E0606A092801D140200BE0606AF7
+S315080207E00A2801D1802006E0606A0B2802D14FF45C
+S315080207F0807000E00120B1FBF0F09FE103A801F050
+S3150802080065FA606A002801D1012038E0606A012889
+S3150802081001D1022033E0606A022801D104202EE0C9
+S31508020820606A032801D1062029E0606A042801D1FA
+S31508020830082024E0606A052801D10A201FE0606AC0
+S31508020840062801D10C201AE0606A072801D1102077
+S3150802085015E0606A082801D1202010E0606A09289C
+S3150802086001D140200BE0606A0A2801D1802006E007
+S31508020870606A0B2802D14FF4807000E001200499C7
+S31508020880B1FBF0F05AE1684601F026FB606A0028DF
+S3150802089001D1012038E0606A012801D1022033E043
+S315080208A0606A022801D104202EE0606A032801D179
+S315080208B0062029E0606A042801D1082024E0606A3B
+S315080208C0052801D10A201FE0606A062801D10C20FA
+S315080208D01AE0606A072801D1102015E0606A082824
+S315080208E001D1202010E0606A092801D140200BE0DE
+S315080208F0606A0A2801D1802006E0606A0B2802D1C4
+S315080209004FF4807000E001200199B1FBF0F015E187
+S31508020910DFF8A4090168890646D50168606A0028D5
+S3150802092001D1012038E0606A012801D1022033E0B2
+S31508020930606A022801D104202EE0606A032801D1E8
+S31508020940062029E0606A042801D1082024E0606AAA
+S31508020950052801D10A201FE0606A062801D10C2069
+S315080209601AE0606A072801D1102015E0606A082893
+S3150802097001D1202010E0606A092801D140200BE04D
+S31508020980606A0A2801D1802006E0606A0B2802D133
+S315080209904FF4807000E00120DFF8442AC1F3C10158
+S315080209A0CA40B2FBF0F041E0606A002801D101209A
+S315080209B038E0606A012801D1022033E0606A022821
+S315080209C001D104202EE0606A032801D1062029E01D
+S315080209D0606A042801D1082024E0606A052801D14A
+S315080209E00A201FE0606A062801D10C201AE0606A14
+S315080209F0072801D1102015E0606A082801D12020B5
+S31508020A0010E0606A092801D140200BE0606A0A28D2
+S31508020A1001D1802006E0606A0B2802D14FF480706B
+S31508020A2000E00120DFF8B819B1FBF0F086E0606A51
+S31508020A30002801D1012038E0606A012801D102208C
+S31508020A4033E0606A022801D104202EE0606A032896
+S31508020A5001D1062029E0606A042801D1082024E091
+S31508020A60606A052801D10A201FE0606A062801D1BA
+S31508020A700C201AE0606A072801D1102015E0606A86
+S31508020A80082801D1202010E0606A092801D14020F7
+S31508020A900BE0606A0A2801D1802006E0606A0B280A
+S31508020AA002D14FF4807000E00120DFF8CC19B1FBC7
+S31508020AB0F0F043E0606A002801D1012038E0606A5C
+S31508020AC0012801D1022033E0606A022801D10420FC
+S31508020AD02EE0606A032801D1062029E0606A04280C
+S31508020AE001D1082024E0606A052801D10A201FE006
+S31508020AF0606A062801D10C201AE0606A072801D12B
+S31508020B00102015E0606A082801D1202010E0606AEA
+S31508020B10092801D140200BE0606A0A2801D1802009
+S31508020B2006E0606A0B2802D14FF4807000E00120CB
+S31508020B304FF40041B1FBF0F000E00125002800F077
+S31508020B407887626803214A43904205D362684FF464
+S31508020B5080514A43824202D2012500F06ABFFFB29F
+S31508020B60022F0ED0042F5CD0082F00F0AB80102F76
+S31508020B7000F0F980202F00F09D81402F00F0E981D6
+S31508020B8036E201F093F80100606A002801D10120DB
+S31508020B9038E0606A012801D1022033E0606A02283F
+S31508020BA001D104202EE0606A032801D1062029E03B
+S31508020BB0606A042801D1082024E0606A052801D168
+S31508020BC00A201FE0606A062801D10C201AE0606A32
+S31508020BD0072801D1102015E0606A082801D12020D3
+S31508020BE010E0606A092801D140200BE0606A0A28F1
+S31508020BF001D1802006E0606A0B2802D14FF480708A
+S31508020C0000E00120B1FBF0F24FF4807360684008FF
+S31508020C100021E3FB02016268002301F07BFA060069
+S31508020C20E7E103A801F052F8606A002801D1012021
+S31508020C3038E0606A012801D1022033E0606A02289E
+S31508020C4001D104202EE0606A032801D1062029E09A
+S31508020C50606A042801D1082024E0606A052801D1C7
+S31508020C600A201FE0606A062801D10C201AE0606A91
+S31508020C70072801D1102015E0606A082801D1202032
+S31508020C8010E0606A092801D140200BE0606A0A2850
+S31508020C9001D1802006E0606A0B2802D14FF48070E9
+S31508020CA000E001200499B1FBF0F24FF4807360680A
+S31508020CB040080021E3FB02016268002301F02AFAD8
+S31508020CC0060096E1684601F007F9606A002801D134
+S31508020CD0012038E0606A012801D1022033E0606A07
+S31508020CE0022801D104202EE0606A032801D10620D9
+S31508020CF029E0606A042801D1082024E0606A0528F0
+S31508020D0001D10A201FE0606A062801D10C201AE0E8
+S31508020D10606A072801D1102015E0606A082801D107
+S31508020D20202010E0606A092801D140200BE0606AA1
+S31508020D300A2801D1802006E0606A0B2802D14FF406
+S31508020D40807000E001200199B1FBF0F24FF4807344
+S31508020D50606840080021E3FB02016268002301F093
+S31508020D60D9F9060045E1DFF850050168890652D52A
+S31508020D700168606A002801D1012038E0606A01280A
+S31508020D8001D1022033E0606A022801D104202EE054
+S31508020D90606A032801D1062029E0606A042801D185
+S31508020DA0082024E0606A052801D10A201FE0606A4B
+S31508020DB0062801D10C201AE0606A072801D1102002
+S31508020DC015E0606A082801D1202010E0606A092827
+S31508020DD001D140200BE0606A0A2801D1802006E092
+S31508020DE0606A0B2802D14FF4807000E00120DFF818
+S31508020DF0F025C1F3C101CA40B2FBF0F24FF4807389
+S31508020E00606840080021E3FB02016268002301F0E2
+S31508020E1081F906004DE0606A002801D1012038E018
+S31508020E20606A012801D1022033E0606A022801D1F2
+S31508020E3004202EE0606A032801D1062029E0606AB0
+S31508020E40042801D1082024E0606A052801D10A2075
+S31508020E501FE0606A062801D10C201AE0606A07289A
+S31508020E6001D1102015E0606A082801D1202010E07F
+S31508020E70606A092801D140200BE0606A0A2801D17C
+S31508020E80802006E0606A0B2802D14FF4807000E0E9
+S31508020E900120DFF84C15B1FBF0F24FF4807360685D
+S31508020EA040080021E3FB02016268002301F032F9DF
+S31508020EB006009EE0606A002801D1012038E0606AD7
+S31508020EC0012801D1022033E0606A022801D10420F8
+S31508020ED02EE0606A032801D1062029E0606A042808
+S31508020EE001D1082024E0606A052801D10A201FE002
+S31508020EF0606A062801D10C201AE0606A072801D127
+S31508020F00102015E0606A082801D1202010E0606AE6
+S31508020F10092801D140200BE0606A0A2801D1802005
+S31508020F2006E0606A0B2802D14FF4807000E00120C7
+S31508020F30DFF84415B1FBF0F24FF48073606840089D
+S31508020F400021E3FB02016268002301F0E3F80600D0
+S31508020F504FE0606A002801D1012038E0606A012862
+S31508020F6001D1022033E0606A022801D104202EE072
+S31508020F70606A032801D1062029E0606A042801D1A3
+S31508020F80082024E0606A052801D10A201FE0606A69
+S31508020F90062801D10C201AE0606A072801D1102020
+S31508020FA015E0606A082801D1202010E0606A092845
+S31508020FB001D140200BE0606A0A2801D1802006E0B0
+S31508020FC0606A0B2802D14FF4807000E001204FF4CA
+S31508020FD00041B1FBF0F24FF48073606840080021CB
+S31508020FE0E3FB02016268002301F094F8060000E0C0
+S31508020FF00125B6F54070DFF8581A884203D22068F0
+S31508021000C66000F016BD012500F013BDE069B0F513
+S31508021010004F40F08F82FFB2002F11D0012F5BD014
+S31508021020042F00F0A580082F00F0EF80102F00F0A3
+S315080210303981202F00F0D681402F00F01F8268E206
+S3150802104001F0D5FB0100606A002801D1012038E0D1
+S31508021050606A012801D1022033E0606A022801D1C0
+S3150802106004202EE0606A032801D1062029E0606A7E
+S31508021070042801D1082024E0606A052801D10A2043
+S315080210801FE0606A062801D10C201AE0606A072868
+S3150802109001D1102015E0606A082801D1202010E04D
+S315080210A0606A092801D140200BE0606A0A2801D14A
+S315080210B0802006E0606A0B2802D14FF4807000E0B7
+S315080210C00120B1FBF0F06168490811EB4001606844
+S315080210D0B1FBF0F6B6B21DE201F096FB0100606ABA
+S315080210E0002801D1012038E0606A012801D10220D6
+S315080210F033E0606A022801D104202EE0606A0328E0
+S3150802110001D1062029E0606A042801D1082024E0DA
+S31508021110606A052801D10A201FE0606A062801D103
+S315080211200C201AE0606A072801D1102015E0606ACF
+S31508021130082801D1202010E0606A092801D1402040
+S315080211400BE0606A0A2801D1802006E0606A0B2853
+S3150802115002D14FF4807000E00120B1FBF0F0616823
+S31508021160490811EB40016068B1FBF0F6B6B2D1E16D
+S3150802117003A800F0ABFD606A002801D1012038E01F
+S31508021180606A012801D1022033E0606A022801D18F
+S3150802119004202EE0606A032801D1062029E0606A4D
+S315080211A0042801D1082024E0606A052801D10A2012
+S315080211B01FE0606A062801D10C201AE0606A072837
+S315080211C001D1102015E0606A082801D1202010E01C
+S315080211D0606A092801D140200BE0606A0A2801D119
+S315080211E0802006E0606A0B2802D14FF4807000E086
+S315080211F001200499B1FBF0F06168490811EB40013E
+S315080212006068B1FBF0F6B6B284E1684600F064FEA7
+S31508021210606A002801D1012038E0606A012801D1FC
+S31508021220022033E0606A022801D104202EE0606AB7
+S31508021230032801D1062029E0606A042801D1082082
+S3150802124024E0606A052801D10A201FE0606A0628A0
+S3150802125001D10C201AE0606A072801D1102015E096
+S31508021260606A082801D1202010E0606A092801D1A5
+S3150802127040200BE0606A0A2801D1802006E0606AF5
+S315080212800B2802D14FF4807000E001200199B1FBCE
+S31508021290F0F06168490811EB40016068B1FBF0F6AD
+S315080212A0B6B237E10448016889064FD50168606A13
+S315080212B0002803D101203AE000440258606A012856
+S315080212C001D1022033E0606A022801D104202EE00F
+S315080212D0606A032801D1062029E0606A042801D140
+S315080212E0082024E0606A052801D10A201FE0606A06
+S315080212F0062801D10C201AE0606A072801D11020BD
+S3150802130015E0606A082801D1202010E0606A0928E1
+S3150802131001D140200BE0606A0A2801D1802006E04C
+S31508021320606A0B2802D14FF4807000E001202C4A33
+S31508021330C1F3C101CA40B2FBF0F06168490811EB7A
+S3150802134040016068B1FBF0F6B6B248E0606A002870
+S3150802135001D1012038E0606A012801D1022033E078
+S31508021360606A022801D104202EE0606A032801D1AE
+S31508021370062029E0606A042801D1082024E0606A70
+S31508021380052801D10A201FE0606A062801D10C202F
+S315080213901AE0606A072801D1102015E0606A082859
+S315080213A001D1202010E0606A092801D140200BE013
+S315080213B0606A0A2801D1802006E0606A0B2802D1F9
+S315080213C04FF4807000E001200549B1FBF0F0616836
+S315080213D0490811EB40016068B1FBF0F6B6B299E034
+S315080213E00090D003606A002801D1012038E0606AC3
+S315080213F0012801D1022033E0606A022801D10420C3
+S315080214002EE0606A032801D1062029E0606A0428D2
+S3150802141001D1082024E0606A052801D10A201FE0CC
+S31508021420606A062801D10C201AE0606A072801D1F1
+S31508021430102015E0606A082801D1202010E0606AB1
+S31508021440092801D140200BE0606A0A2801D18020D0
+S3150802145006E0606A0B2802D14FF4807000E0012092
+S315080214600549B1FBF0F06168490811EB4001606873
+S31508021470B1FBF0F6B6B24DE000093D00606A0028FD
+S3150802148001D1012038E0606A012801D1022033E047
+S31508021490606A022801D104202EE0606A032801D17D
+S315080214A0062029E0606A042801D1082024E0606A3F
+S315080214B0052801D10A201FE0606A062801D10C20FE
+S315080214C01AE0606A072801D1102015E0606A082828
+S315080214D001D1202010E0606A092801D140200BE0E2
+S315080214E0606A0A2801D1802006E0606A0B2802D1C8
+S315080214F04FF4807000E001204FF40041B1FBF0F098
+S315080215006168490811EB40016068B1FBF0F6B6B2B2
+S3150802151000E001254FF6F071B6F11000884207D2B5
+S315080215203140C6F34200014389B22068C16080E2B5
+S3150802153001257EE2FFB2002F11D0012F5AD0042FC7
+S3150802154000F0A380082F00F0EC80102F00F0358100
+S31508021550202F00F0CF81402F00F016825EE201F0C4
+S3150802156046F90100606A002801D1012038E0606A64
+S31508021570012801D1022033E0606A022801D1042041
+S315080215802EE0606A032801D1062029E0606A042851
+S3150802159001D1082024E0606A052801D10A201FE04B
+S315080215A0606A062801D10C201AE0606A072801D170
+S315080215B0102015E0606A082801D1202010E0606A30
+S315080215C0092801D140200BE0606A0A2801D180204F
+S315080215D006E0606A0B2802D14FF4807000E0012011
+S315080215E0B1FBF0F0616810EB51006168B0FBF1F6EF
+S315080215F0B6B214E201F008F90100606A002801D1C6
+S31508021600012038E0606A012801D1022033E0606ACD
+S31508021610022801D104202EE0606A032801D106209F
+S3150802162029E0606A042801D1082024E0606A0528B6
+S3150802163001D10A201FE0606A062801D10C201AE0AF
+S31508021640606A072801D1102015E0606A082801D1CE
+S31508021650202010E0606A092801D140200BE0606A68
+S315080216600A2801D1802006E0606A0B2802D14FF4CD
+S31508021670807000E00120B1FBF0F0616810EB5100C8
+S315080216806168B0FBF1F6B6B2C9E103A800F01EFB29
+S31508021690606A002801D1012038E0606A012801D178
+S315080216A0022033E0606A022801D104202EE0606A33
+S315080216B0032801D1062029E0606A042801D10820FE
+S315080216C024E0606A052801D10A201FE0606A06281C
+S315080216D001D10C201AE0606A072801D1102015E012
+S315080216E0606A082801D1202010E0606A092801D121
+S315080216F040200BE0606A0A2801D1802006E0606A71
+S315080217000B2802D14FF4807000E001200499B1FB46
+S31508021710F0F0616810EB51006168B0FBF1F6B6B201
+S315080217207DE1684600F0D8FB606A002801D10120F5
+S3150802173038E0606A012801D1022033E0606A022893
+S3150802174001D104202EE0606A032801D1062029E08F
+S31508021750606A042801D1082024E0606A052801D1BC
+S315080217600A201FE0606A062801D10C201AE0606A86
+S31508021770072801D1102015E0606A082801D1202027
+S3150802178010E0606A092801D140200BE0606A0A2845
+S3150802179001D1802006E0606A0B2802D14FF48070DE
+S315080217A000E001200199B1FBF0F0616810EB5100ED
+S315080217B06168B0FBF1F6B6B231E1DFF89C04016864
+S315080217C089064DD50168606A002801D1012038E0F2
+S315080217D0606A012801D1022033E0606A022801D139
+S315080217E004202EE0606A032801D1062029E0606AF7
+S315080217F0042801D1082024E0606A052801D10A20BC
+S315080218001FE0606A062801D10C201AE0606A0728E0
+S3150802181001D1102015E0606A082801D1202010E0C5
+S31508021820606A092801D140200BE0606A0A2801D1C2
+S31508021830802006E0606A0B2802D14FF4807000E02F
+S315080218400120DFF81824C1F3C101CA40B2FBF0F047
+S31508021850616810EB51006168B0FBF1F6B6B248E078
+S31508021860606A002801D1012038E0606A012801D1A6
+S31508021870022033E0606A022801D104202EE0606A61
+S31508021880032801D1062029E0606A042801D108202C
+S3150802189024E0606A052801D10A201FE0606A06284A
+S315080218A001D10C201AE0606A072801D1102015E040
+S315080218B0606A082801D1202010E0606A092801D14F
+S315080218C040200BE0606A0A2801D1802006E0606A9F
+S315080218D00B2802D14FF4807000E00120DFF87C1358
+S315080218E0B1FBF0F0616810EB51006168B0FBF1F6EC
+S315080218F0B6B294E0606A002801D1012038E0606A35
+S31508021900012801D1022033E0606A022801D10420AD
+S315080219102EE0606A032801D1062029E0606A0428BD
+S3150802192001D1082024E0606A052801D10A201FE0B7
+S31508021930606A062801D10C201AE0606A072801D1DC
+S31508021940102015E0606A082801D1202010E0606A9C
+S31508021950092801D140200BE0606A0A2801D18020BB
+S3150802196006E0606A0B2802D14FF4807000E001207D
+S31508021970DFF8EC12B1FBF0F0616810EB5100616818
+S31508021980B0FBF1F6B6B24AE0606A002801D101203E
+S3150802199038E0606A012801D1022033E0606A022831
+S315080219A001D104202EE0606A032801D1062029E02D
+S315080219B0606A042801D1082024E0606A052801D15A
+S315080219C00A201FE0606A062801D10C201AE0606A24
+S315080219D0072801D1102015E0606A082801D12020C5
+S315080219E010E0606A092801D140200BE0606A0A28E3
+S315080219F001D1802006E0606A0B2802D14FF480707C
+S31508021A0000E001204FF40041B1FBF0F0616810EBF1
+S31508021A1051006168B0FBF1F6B6B200E00125B6F1F5
+S31508021A2010004FF6F071884202D22068C66000E0C4
+S31508021A3001250120A4F86A000120A4F86800002004
+S31508021A40E066002020672800C0B207B0F0BD00009B
+S31508021A5000FD0F0090F82810C90707D501684A68E3
+S31508021A6032F40032C16A0A4301684A6090F82810C3
+S31508021A70890707D501684A6832F48032016B0A433E
+S31508021A8001684A6090F82810490707D501684A682C
+S31508021A9032F48022416B0A4301684A6090F82810A2
+S31508021AA0090707D501684A6832F40042816B0A437E
+S31508021AB001684A6090F82810C90607D501688A683D
+S31508021AC032F48052C16B0A4301688A6090F8281082
+S31508021AD0890607D501688A6832F40052016C0A43FE
+S31508021AE001688A6090F82810490613D501684A6881
+S31508021AF032F48012416C0A4301684A60416CB1F5BE
+S31508021B00801F07D101684A6832F4C002816C0A4311
+S31508021B1001684A6090F82810090607D501684A68DC
+S31508021B2032F40022C16C0A4300684260704738B535
+S31508021B3004000020C4F8880000F0B2F80500206806
+S31508021B40006800070DD57FF07E4000902B0000222A
+S31508021B505FF40011200000F021F8002801D00320CC
+S31508021B601BE02068006840070DD57FF07E40009094
+S31508021B702B0000225FF48001200000F00FF80028F5
+S31508021B8001D0032009E02020C4F880002020C4F8F0
+S31508021B908400002084F87C00002032BD2DE9F04143
+S31508021BA005000E0090461F00069C2868C069304052
+S31508021BB0B04201D1012000E000204146C9B2884264
+S31508021BC046D114F1010FF0D000F06AF8C01B844226
+S31508021BD001D3002C16D12868006830F4D070296821
+S31508021BE008602868806840084000296888602020C4
+S31508021BF0C5F880002020C5F88400002085F87C00FE
+S31508021C00032026E0286800684007CED52868C06900
+S31508021C100005CAD54FF4006029680862286800687A
+S31508021C2030F4D07029680860286880684008400047
+S31508021C30296888602020C5F880002020C5F884001D
+S31508021C402020C5F88800002085F87C00032000E0E3
+S31508021C500020BDE8F0810000004402580090D0033D
+S31508021C6000093D00704730B4002513E050F8042BF4
+S31508021C70D30744BFA9F101039A18091F042942F898
+S31508021C80045BFAD213468C0744BF15809B1CC9070E
+S31508021C9048BF1D7050F8041B0029E7D130BC7047B5
+S31508021CA001480068704700BF8801002080B500F02F
+S31508021CB084FDDFF84414DFF844241268C2F30212E2
+S31508021CC0895C11F01F01C84002BD000010B4DFF89C
+S31508021CD01C140B6813F003030968C1F30531DFF816
+S31508021CE010241268C2F30014DFF814241268C2F32F
+S31508021CF0CC02544300EE104AB8EE400A002900F01E
+S31508021D00DE80002B03D0022B68D049D384E0DFF8AB
+S31508021D10F42313689B0625D5DFF8D8331268C2F375
+S31508021D20C102D34000EE903AF8EE600A01EE101AAC
+S31508021D30B8EE411AC0EE810ADFF8CC130968C90564
+S31508021D40C90D01EE101AB8EE411ADFED611A80EEDE
+S31508021D50210A31EE000AB7EE001A30EE010A20EE29
+S31508021D60800A1CE000EE901AF8EE600A9FED591AF6
+S31508021D70C1EE200ADFF890130968C905C90D01EEFC
+S31508021D80101AB8EE411ADFED521A80EE210A31EE28
+S31508021D90000AB7EE001A30EE010A20EE800A58E071
+S31508021DA000EE901AF8EE600A9FEDCC1AC1EE200AF0
+S31508021DB0DFF854130968C905C90D01EE101AB8EE01
+S31508021DC0411ADFED431A80EE210A31EE000AB7EE18
+S31508021DD0001A30EE010A20EE800A3AE000EE901A66
+S31508021DE0F8EE600A9FEDBE1AC1EE200ADFF8181354
+S31508021DF00968C905C90D01EE101AB8EE411ADFEDD8
+S31508021E00341A80EE210A31EE000AB7EE001A30EED5
+S31508021E10010A20EE800A1CE000EE901AF8EE600A2B
+S31508021E209FEDAE1AC1EE200ADFF8DC120968C90571
+S31508021E30C90D01EE101AB8EE411ADFED251A80EE29
+S31508021E40210A31EE000AB7EE001A30EE010A20EE38
+S31508021E50800ADFF8B4120A68C2F3462200EE902A14
+S31508021E60F8EE600AB7EE001A70EE810AC0EE200A92
+S31508021E70FCEEE00AC0ED000A0A68C2F3064200EE6A
+S31508021E80902AF8EE600AB7EE001A70EE810AC0EEE2
+S31508021E90200AFCEEE00AC0ED010A0968C1F30661F0
+S31508021EA000EE901AF8EE600AB7EE001A70EE810A92
+S31508021EB080EE200ABCEEC00A80ED020A05E0002187
+S31508021EC00160002141600021816010BC704700005A
+S31508021ED0000000460024744C10B4DFF810120B6898
+S31508021EE013F003030968C1F30551DFF804221268E7
+S31508021EF0C2F30024DFF814221268C2F3CC02544358
+S31508021F0000EE104AB8EE400A002900F0DE80002BE7
+S31508021F1003D0022B68D049D384E0DFF8E82113689E
+S31508021F209B0625D5DFF8CC311268C2F3C102D3402D
+S31508021F3000EE903AF8EE600A01EE101AB8EE411A6F
+S31508021F40C0EE810ADFF8C8110968C905C90D01EE94
+S31508021F50101AB8EE411ADFED631A80EE210A31EE45
+S31508021F60000AB7EE001A30EE010A20EE800A1CE0DB
+S31508021F7000EE901AF8EE600A9FED5B1AC1EE200A8F
+S31508021F80DFF88C110968C905C90D01EE101AB8EEF9
+S31508021F90411ADFED541A80EE210A31EE000AB7EE35
+S31508021FA0001A30EE010A20EE800A58E000EE901A76
+S31508021FB0F8EE600A9FED491AC1EE200ADFF85011C1
+S31508021FC00968C905C90D01EE101AB8EE411ADFED06
+S31508021FD0451A80EE210A31EE000AB7EE001A30EEF3
+S31508021FE0010A20EE800A3AE000EE901AF8EE600A3C
+S31508021FF09FED3B1AC1EE200ADFF814110968C905DC
+S31508022000C90D01EE101AB8EE411ADFED361A80EE46
+S31508022010210A31EE000AB7EE001A30EE010A20EE66
+S31508022020800A1CE000EE901AF8EE600A9FED2B1A61
+S31508022030C1EE200ADFF8D8100968C905C90D01EEF4
+S31508022040101AB8EE411ADFED271A80EE210A31EE90
+S31508022050000AB7EE001A30EE010A20EE800ADFF80F
+S31508022060B0100A68C2F3462200EE902AF8EE600A19
+S31508022070B7EE001A70EE810AC0EE200AFCEEE00AFC
+S31508022080C0ED000A0A68C2F3064200EE902AF8EE8C
+S31508022090600AB7EE001A70EE810AC0EE200AFCEE5C
+S315080220A0E00AC0ED010A0968C1F3066100EE901A5A
+S315080220B0F8EE600AB7EE001A70EE810A80EE200A80
+S315080220C0BCEEC00A80ED020A05E00021016000218B
+S315080220D041600021816010BC704700000024744AE8
+S315080220E00024F44A000000460024744C284402588E
+S315080220F02C4402580090D003504602082044025845
+S315080221003C4402580044025838440258444402588F
+S3150802211040440258BBBBE1B1B2F5803F80F07E80F5
+S31508022120022A1ED98C46B1FBF2F102FB11C31B042B
+S3150802213043EA1043B3FBF2FC02FB1C3380B240EACB
+S315080221400343B3FBF2F002FB103240EA0C400023D1
+S315080221507047022A05D98446B0FBF2F002FB10C288
+S3150802216070474AB105D100F0010249085FEA30001A
+S31508022170704700220023704700F072BE0B0002006F
+S31508022180002100207047904271EB030CF6D3B3F599
+S31508022190803F2FD2F0B5B3FA83F7B1FA81F4A7F1EB
+S315080221A00F0E3D1B5340CEF1200602FA0EF2F34102
+S315080221B05340B5F10F0746D80F3C2C444140C4F1B1
+S315080221C02006A040F1414140B1FBF3F603FB16118C
+S315080221D0A2FB0645001BA94102D2761E8018594168
+S315080221E080EA010221FA0EF362FA0EF200215A403F
+S315080221F03046F0BD30B4B1FBF3FC03FB1C11A2FB65
+S315080222000C45001BA94103D2ACF1010C80185941B7
+S3150802221030BC02460B46604600217047B2F1807F09
+S3150802222065D3F0B5B2FA82F7B1FA81F4C7F10F06AF
+S315080222303D1B22FA06F307F1110EF24120355A40E8
+S31508022240B5F10F07B8D94140C4F12006A040F141C3
+S315080222504140B1FBF3FC03FB1C11A2FB0C45001B1E
+S31508022260A94103D2BCF1010C801859410F2F12D390
+S315080222700F3FC90341EA5041B1FBF3F603FB1611BE
+S31508022280A2FB0645D4EBC030A94102D2761E8018BD
+S31508022290594146EACC3C07B34140C7F12006B8404B
+S315080222A0F1414140B1FBF3F603FB1611A2FB0645C9
+S315080222B0001BA94102D2761E8018594180EA010202
+S315080222C021FA0EF3C7F1200462FA0EF20CFA07F0AD
+S315080222D05A402CFA04F13043F0BD80EA010221FA91
+S315080222E00EF3002162FA0EF260465A40F0BD8C46A1
+S315080222F0B1FBF2F102FB11C31B0243EA1063B3FB03
+S31508022300F2FC02FB1C331B024CEA002043EA106370
+S31508022310B3FBF2FC02FB1C331B024CEA002043EA25
+S315080223201063B3FBF2FC02FB1C331B024CEA0020CF
+S3150802233043EA1063B3FBF2FC02FB1C324CEA0020B0
+S31508022340002370472DE9F04104000E00002C01D14C
+S3150802235001203AE1DFF8DC54286810F00F00B04299
+S315080223600BD228680009000130432860286810F05B
+S315080223700F00B04201D0012027E1207840070DD591
+S31508022380DFF8CC14086810F070002269904205D272
+S315080223900A6832F07002206902430A602078000750
+S315080223A00DD5DFF8B014086810F070006269904223
+S315080223B005D20A6832F07002606902430A60207820
+S315080223C0C0060DD5DFF88C14086810F4E060A2691F
+S315080223D0904205D20A6832F4E062A06902430A60B2
+S315080223E0207880060DD5DFF87014086810F07000A2
+S315080223F0E269904205D20A6832F07002E069024345
+S315080224000A60207880070DD5DFF84414086810F0B2
+S315080224100F00E268904205D20A6812091201E068C2
+S3150802242002430A602078C00748D5DFF824140A68F0
+S3150802243032F47062A06802430A606068022806D114
+S31508022440DFF8F403006880031CD40120BDE060684D
+S31508022450032806D1DFF8E0030068800112D40120C0
+S31508022460B3E06068012806D1DFF8CC030068C0052E
+S3150802247008D40120A9E0DFF8C0030068400701D4A8
+S315080224800120A2E0DFF8B4733968C908C900606898
+S3150802249001433960FFF704FC8046386810F03800BB
+S315080224A06168B0EBC10F09D0FFF7FAFBB0EB080081
+S315080224B041F289318842F0D3032086E020788007EA
+S315080224C00DD5DFF88C13E0680A6812F00F02904205
+S315080224D005D20A6812091201E06802430A602868EE
+S315080224E010F00F0086420BD228680009000130431B
+S315080224F02860286810F00F00B04201D0012064E07D
+S31508022500207840070DD5DFF8481320690A6812F0CB
+S315080225107002904205D20A6832F0700220690243BC
+S315080225200A60207800070DD5DFF8281360690A6863
+S3150802253012F07002904205D20A6832F0700260699F
+S3150802254002430A602078C0060DD5DFF80813A06991
+S315080225500A6812F4E062904205D20A6832F4E0622E
+S31508022560A06902430A60207880060DD5DFF8E812D2
+S31508022570E0690A6812F07002904205D20A6832F0DF
+S315080225807002E06902430A6000F022F8DFF8DC22F2
+S31508022590DFF8BC120B68C3F30323D35C13F01F03E3
+S315080225A0D840096811F00F01515C11F01F010200B1
+S315080225B0CA40DFF894120A60DFF888120860DFF86A
+S315080225C08C02006800F064FCC0B2BDE8F08100002D
+S315080225D0DFF86802006810F03800002806D00828DC
+S315080225E013D0102814D0182815D0E4E0DFF84812C2
+S315080225F00868800606D5DFF848020968C1F3C101F2
+S31508022600C84001E0DFF83802D6E0DFF86402D3E01A
+S31508022610DFF86002D0E0DFF84402026812F0030233
+S315080226200068C0F30510DFF838120B6813F00103CF
+S31508022630DFF834120968C1F3CC014B4300EE103AB5
+S31508022640B8EE400A002800F0B480002A03D0022A15
+S3150802265066D048D381E0DFF8E0110A68920625D5EC
+S31508022660DFF8DC210968C1F3C101CA4000EE902AED
+S31508022670F8EE600A01EE100AB8EE411AC0EE810AB7
+S31508022680DFF8E0010068C005C00D01EE100AB8EED9
+S31508022690411ADFED641A80EE210A31EE000AB7EE1E
+S315080226A0001A30EE010A60EE800A1BE000EE900A7C
+S315080226B0F8EE600A9FED5C1AC1EE200A69480068C6
+S315080226C0C005C00D01EE100AB8EE411ADFED551A23
+S315080226D080EE210A31EE000AB7EE001A30EE010A40
+S315080226E060EE800A55E000EE900AF8EE600A9FED69
+S315080226F04F1AC1EE200A5B480068C005C00D01EEFC
+S31508022700100AB8EE411ADFED471A80EE210A31EEB9
+S31508022710000AB7EE001A30EE010A60EE800A38E0C7
+S3150802272000EE900AF8EE600A9FED411AC1EE200A01
+S315080227304C480068C005C00D01EE100AB8EE411AF1
+S31508022740DFED381A80EE210A31EE000AB7EE001ADA
+S3150802275030EE010A60EE800A1BE000EE900AF8EEFF
+S31508022760600A9FED321AC1EE200A3E480068C0058B
+S31508022770C00D01EE100AB8EE411ADFED2A1A80EEF4
+S31508022780210A31EE000AB7EE001A30EE010A60EEAF
+S31508022790800A34480068C0F34620401C00EE100A3E
+S315080227A0B8EE400A80EE800ABCEEC00A10EE100AA5
+S315080227B000E0002000E02E48704780B5FFF708FFCA
+S315080227C023492A4A0B68C3F30323D35C13F01F0376
+S315080227D0D8401D4B096811F00F01515C11F01F0119
+S315080227E00200CA401A6017490860186802BD80B517
+S315080227F0FFF7E3FF1D49174A1268C2F30212895C02
+S3150802280011F01F01C84002BD80B5FFF7D6FF174970
+S31508022810104A1268C2F30222895C11F01F01C840ED
+S3150802282002BD0000000000460024744C0024744ACD
+S315080228300024F44A00200052004402581044025868
+S315080228400090D003040000200800002000000020A9
+S31508022850184402581C440258204402582844025874
+S315080228602C4402583044025834440258504602084E
+S3150802287000093D0000127A0070B50400002C01D14F
+S315080228800120D4E22078C0076CD5DFF8A4050068D9
+S3150802289010F03800DFF89C150968102805D01828AA
+S315080228A00DD111F00301022909D1DFF88C05006860
+S315080228B0800357D56068002854D10120B7E26068C2
+S315080228C0B0F5803F06D1DFF87005016851F4803112
+S315080228D0016026E0606800280AD1DFF85C05016815
+S315080228E031F480310160016831F48021016018E019
+S315080228F06068B0F5A02F0AD1DFF83C05016851F4EB
+S3150802290080210160016851F48031016009E0DFF835
+S315080229102805016831F480310160016831F48021AB
+S315080229200160606800280ED0FFF7BAF90500DFF8E3
+S3150802293008050068800315D4FFF7B2F9401B65281D
+S31508022940F5D3032073E2FFF7ABF90500DFF8E804D5
+S315080229500068800306D5FFF7A3F9401B6528F5D35F
+S31508022960032064E22078800731D5DFF8C4040068C2
+S3150802297010F03800DFF8BC140968002804D01828BB
+S3150802298044D111F0030F41D1DFF8AC0400684007C7
+S3150802299004D5E068002801D1012048E200F0CEFA09
+S315080229A041F20401884209D2DFF89004016831F441
+S315080229B07C31226951EA0231016008E0DFF87C04C1
+S315080229C0016831F0FE41226951EA0261016020780C
+S315080229D0C00679D5DFF85804006810F03800DFF829
+S315080229E054140968082807D0182840F0868011F080
+S315080229F00301012940F08180DFF83C040068C00524
+S31508022A0049D5E069802846D0012010E2E06800280E
+S31508022A102ED0DFF82464316831F01901E0680143E9
+S31508022A203160FFF73DF905003068400706D4FFF725
+S31508022A3037F9401B0328F7D30320F8E100F07EFAA2
+S31508022A4041F20401884209D2DFF8F003016831F441
+S31508022A507C31226951EA0231016008E0DFF8DC03C1
+S31508022A60016831F0FE41226951EA02610160AEE76E
+S31508022A70DFF8C4633068400840003060FFF710F999
+S31508022A80050030684007A2D5FFF70AF9401B03285C
+S31508022A90F7D30320CBE100F051FA41F20401884250
+S31508022AA009D2DFF89803016831F0F841226A51EA3F
+S31508022AB08261016008E0DFF88803016831F07C5121
+S31508022AC0226A51EA026101602078000767D56069C7
+S31508022AD0002852D0DFF86C63306850F0010030608D
+S31508022AE0FFF7DEF805003068800758D4FFF7D8F8F4
+S31508022AF0401B0328F7D3032099E1E06900282AD06E
+S31508022B00DFF83463306850F080003060FFF7C8F8A9
+S31508022B1005003068C00506D4FFF7C2F8401B032833
+S31508022B20F7D3032083E100F009FA41F2040188424F
+S31508022B3008D2C248016831F0F841226A51EA826134
+S31508022B40016007E0BE48016831F07C51226A51EA09
+S31508022B5002610160B8E7B84E306830F08000306034
+S31508022B60FFF79EF805003068C005ADD5FFF798F85F
+S31508022B70401B0328F7D3032059E1B24E30684008B8
+S31508022B8040003060FFF78CF805003068800706D5EC
+S31508022B90FFF786F8401B0328F7D3032047E120787E
+S31508022BA0800626D5A069002811D0A34E306850F4B5
+S31508022BB080503060FFF774F805003068800418D436
+S31508022BC0FFF76EF8401B0328F7D303202FE19A4E2E
+S31508022BD0306830F480503060FFF762F805003068DC
+S31508022BE0800406D5FFF75CF8401B0328F7D30320B9
+S31508022BF01DE12078400760D5934E306850F4807006
+S31508022C003060FFF74DF805003068C00506D4FFF7B7
+S31508022C1047F8401B6528F7D3032008E1A068012876
+S31508022C2005D18A48016851F00101016022E0A068D5
+S31508022C30002809D1854801684908490001600168E8
+S31508022C4031F00401016015E0A068052809D17F4822
+S31508022C50016851F004010160016851F00101016047
+S31508022C6008E07A480168490849000160016831F0BC
+S31508022C7004010160A06800280FD0FFF711F80500CB
+S31508022C8072480068800718D4FFF70AF8401B41F219
+S31508022C9089318842F4D30320C9E0FFF701F8050019
+S31508022CA06A480068800708D5FEF7FAFF401B41F21A
+S31508022CB089318842F4D30320B9E0606A002800F01B
+S31508022CC0B5805B48006810F03800182800F0838049
+S31508022CD0606A02286DD1584D286830F080702860E5
+S31508022CE0FEF7DEFF06002868800106D5FEF7D8FF44
+S31508022CF0801B0328F7D3032099E04E490A685448F3
+S31508022D000240A06A0243E06A52EA00120A60206B95
+S31508022D10401EC005C00D616B491E490211F47E4171
+S31508022D200843A16B491E090411F4FE010843E16B2D
+S31508022D30491E090611F0FE410843464908604649FC
+S31508022D400868400840000860444802686FF3CF02EA
+S31508022D50A36C52EAC30202600A6832F00C02206CC3
+S31508022D6002430A600A6832F00202606C02430A6091
+S31508022D70086850F480300860086850F4003008602B
+S31508022D80086850F480200860086850F0010008605E
+S31508022D90286850F080702860FEF782FF04002868D1
+S31508022DA0800143D4FEF77CFF001B0328F7D30320D8
+S31508022DB03DE0214D286830F080702860FEF770FFEC
+S31508022DC004002868800131D5FEF76AFF001B032834
+S31508022DD0F7D303202BE0174800681E490968626A80
+S31508022DE0012A21D010F00302A36A9A421CD1C0F329
+S31508022DF00510E26A904217D1C805C00D226B521E11
+S31508022E00904211D1C1F34620626B521E90420BD1F9
+S31508022E10C1F30640A26B521E904205D1C1F3066069
+S31508022E20E16B491E884201D0012000E0002070BDF6
+S31508022E3010440258284402580044025804440258CE
+S31508022E400C44025874440258004802587044025806
+S31508022E500CFCFFFF304402582C44025834440258F2
+S31508022E60704730B40EE00268436802440830DC0753
+S31508022E7044BFA9F10104E31852F8045B43F8045B62
+S31508022E80091FF9D150F8041B0029ECD130BC704750
+S31508022E9010B5040011490878002801D101201BE069
+S31508022EA04FF47A700978B0FBF1F00D490968B1FB65
+S31508022EB0F0F000F0C0F8002801D001200CE0102C38
+S31508022EC009D2002221005FF0FF3000F0A4F805487D
+S31508022ED00460002000E0012010BD00BF0C000020A5
+S31508022EE0040000200000002080B5032000F08FF8BF
+S31508022EF0FFF76EFBDFF85010DFF850200B68C3F3BC
+S31508022F000323D35C13F01F03D840096811F00F019D
+S31508022F10515C11F01F010200CA40DFF834100A6042
+S31508022F20DFF8301008600020FFF7B2FF002801D052
+S31508022F30012002E000F021F9002002BDDFF81800A6
+S31508022F400068000C704700001844025850460208F0
+S31508022F5008000020040000200010005C10F00700A2
+S31508022F603E4B1A684FF6FF010A403D4951EA0021D5
+S31508022F700A431A60704739480068C0F3022070474E
+S31508022F80020012B2002A04D40901364A00B21154C8
+S31508022F9007E00901344A00B210F00F00104400F8A5
+S31508022FA0041C704710B410F00700D0F10703052B74
+S31508022FB001D3042301E0D0F10703041D072C01D233
+S31508022FC0002000E0C01E012414FA03F35B1E194018
+S31508022FD0814014FA00F0401E1040084310BC7047A6
+S31508022FE080B5411EB1F1807F01D301200EE0401E5B
+S31508022FF01E4908600F215FF0FF30FFF7C1FF00206E
+S315080230001B49086007201B490860002002BD80B5DD
+S31508023010FFF7A4FF01BD70B504000D001600FFF707
+S31508023020AAFF32002900FFF7BDFF0100200000B207
+S31508023030FFF7A6FF70BD80B5FFF7D2FF02BD0428D1
+S3150802304005D10C48016851F00401016004E0094801
+S31508023050016831F004010160704700000CED00E0E0
+S315080230600000FA0500E400E018ED00E014E000E0D4
+S3150802307018E000E010E000E080B500F001F801BDBC
+S315080230807047000080B500F007F800F02CF900F050
+S31508023090CEFA00F02EF9FAE780B500F009F8FFF744
+S315080230A023FF00F009F800F0E7FA00F0B9FA01BDCB
+S315080230B07C487D490860704780B59CB04C22002147
+S315080230C009A800F0FBFA2022002101A800F0F6FA6E
+S315080230D0022000F0FDFA002000907448016851F4BD
+S315080230E040410160016811F44041009170490A6843
+S315080230F052F001020A60096811F001010091009973
+S3150802310001688904FCD5012009905FF4A0200A9081
+S315080231100220129002201390042014904FF4F070AB
+S315080231201590022016900420179002201890042069
+S31508023130199000201A9000201B9009A8FFF79CFB03
+S31508023140002800D0FEE73F200190032002900020CD
+S3150802315003900820049040200590402006904FF4E2
+S315080231608060079040200890042101A8FFF7EAF83A
+S31508023170002800D0FEE71DB000BD38B586B04D4820
+S31508023180016851F002010160006810F00200059022
+S3150802319005984948016851F002010160016811F079
+S315080231A0020105910599016851F00401016001685F
+S315080231B011F0040105910599016851F008010160B1
+S315080231C0006810F00800059005983C48016851F41B
+S315080231D080210160006810F480200590059838481F
+S315080231E0016851F480710160006810F480700590DE
+S315080231F005980320FFF70BFF002200217FF00B0042
+S31508023200FFF709FF002200217FF00A00FFF703FFFC
+S31508023210002200217FF00900FFF7FDFE00220021AF
+S315080232207FF00400FFF7F7FE002200217FF003007B
+S31508023230FFF7F1FE002200217FF00100FFF7EBFE07
+S31508023240002200215FF0FF30FFF7E5FE80200090A4
+S31508023250012001900020029000200390194C694633
+S31508023260200000F061FA4FF44075009502200190A3
+S315080232700020029000200390072004906946124815
+S3150802328000F052FA009502200190002002900020D8
+S315080232900390092004906946200000F045FA07B019
+S315080232A030BD00000000020808ED00E01848025888
+S315080232B02C040058F4440258E0440258E8440258E0
+S315080232C0EC44025800040258000C0258BFF34F8F10
+S315080232D0C8490A6812F4E062C74802430A60BFF3A3
+S315080232E04F8F00BFFDE780B500F00DF800F0C6F875
+S315080232F001BD80B500F021F800F041F901BD80B5A5
+S31508023300FFF7E4FF01BD80B5BC48BD4901604FF433
+S3150802331061414160002181600021C1600021016193
+S315080233200C214161002181610021C16100210162F4
+S3150802333000218162FCF7B2FF01BD70B5B14C20785D
+S31508023340002815D1B04D280000F037F8012833D1EE
+S315080233502878002830D0287841282DDA00F0A4F9F8
+S31508023360AA490860012020700020A949087023E0B4
+S31508023370A74DA54E28783044401C00F01EF80128B7
+S3150802338011D12878401C287028783178884213D1C0
+S31508023390002020707078FF280ED1287802280BD1D9
+S315080233A0FFF7ADFF08E000F07FF998490968643134
+S315080233B0814201D20020207070BD80B50100002331
+S315080233C001228E48FCF7A9FFC0B2002801D10120CC
+S315080233D000E0002002BDF0B504004FF4FA550026BD
+S315080233E000E0761C3000C0B2122845D2894F200070
+S315080233F080B2B4465FFA8CFC17F81CC0B6465FFA70
+S315080234008EFE07EB4E0E9EF801E01EEB0C0C1CF12D
+S31508023410010C0CFB00F0B5FBF0FC00FB1C5000286D
+S31508023420DFD1200080B2B4465FFA8CFC17F81CC0C4
+S31508023430B6465FFA8EFE07EB4E0E9EF801E01EEBCD
+S315080234400C0C1CF1010C0CFB00F0B5FBF0F008802B
+S3150802345008880028C5D0088840F2012C6045C0DAE1
+S315080234603000C0B217F810001070F6B207EB46002B
+S3150802347040781870012000E00020F0BD38B58AB007
+S315080234800020ADF8060000208DF8050000208DF812
+S31508023490040040F2676401AB0DF105020DF1060165
+S315080234A04FF4FA70FFF797FF5B4D5C4828600020DF
+S315080234B0A8600020E86001202874002068740020B3
+S315080234C0A874BDF8060068610120A8619DF8050088
+S315080234D0E8619DF804002862012068620120A8625A
+S315080234E00120E8620120286300206863002C04D4C6
+S315080234F00120A8630020E86303E00020A8630120F6
+S31508023500E86301202864042068640020A864042073
+S31508023510E86400202865042068650020A865002064
+S31508023520E86500202866002068660420A866280048
+S3150802353000F02EFA002C02D40020029004E05FF07C
+S315080235408040029024F00044002003900120049059
+S3150802355001200590069407940020089002A92800E5
+S3150802356000F080FB0120009001230222022128009C
+S3150802357000F0C7FB280000F0DEFB0BB030BDF8B543
+S315080235808CB040F2676500240126234F402138009B
+S3150802359000F0C4FC002806D06B4602AA4021380077
+S315080235A000F0E3FB0600F6B2002E21D1002D07D467
+S315080235B00298A8420ED1039800280BD1012409E0EB
+S315080235C025F000450298A84204D10398B0F1804F2D
+S315080235D000D10124E4B2012C0AD10598000C9DF809
+S315080235E00010FF2904D1C0B2022801D1FFF787FED5
+S315080235F00DB0F0BD0CED00E00400FA05B0000020A5
+S31508023600004800408D0100203C0100208001002076
+S315080236108C010020744502081000002000A000401A
+S3150802362080B500228021114800F08BF901BD38B51A
+S3150802363000F03AF804000E4D2868201AB0F5FA7F11
+S3150802364013D30C490878002807D1012008700122F3
+S315080236508021064800F075F906E00020087000226D
+S315080236608021024800F06DF92C6031BD0004025831
+S31508023670840100208E01002080B500F0ADFD0948C6
+S3150802368000684FF47A71B0FBF1F0FFF7D4FC04201E
+S31508023690FFF7D5FC002200215FF0FF30FFF7BBFCE5
+S315080236A001BD00000400002080B5FEF7F9FA02BD4C
+S315080236B080B500F0A1FEFFF7DFFC01BD10B5044698
+S315080236C010460A460146204600F0A2FE204610BDD4
+S315080236D010B5DFF84C100A68520708D4096811F0C9
+S315080236E00701814201D0012018E0002016E00A688D
+S315080236F0D208D20010430860FEF7D2FA0400DFF8B7
+S3150802370024000068800408D4FEF7CAFA001B40F2B7
+S31508023710E9318842F3D3012000E0002010BD000001
+S315080237200C48025804480258F8B402000025DFF88B
+S31508023730284236E05FF00A0C05E0DFF820329A42AA
+S31508023740F8D15FF0090C15F00303DBB29B001CFAF3
+S3150802375003FC5CEA07072B009B0846F823702368DC
+S3150802376083434E68F60300D50343236063688343A5
+S315080237704E68B60300D5034363605FF0B04633680C
+S3150802378083434F68FF0200D503433360DFF8D061F5
+S31508023790336883434F68BF0201D518430300336079
+S315080237A06D1C0868E840002800F0C98001260868F0
+S315080237B016FA05F318400028F2D04B68012B08D0F8
+S315080237C04B68022B05D04B68112B02D04B68122B83
+S315080237D01CD197685FF0030C2B00DBB25B001CFA66
+S315080237E003FC37EA0C07D1F80CC02B00DBB25B00EE
+S315080237F01CFA03FC5CEA070797605368AE40B343BA
+S315080238004E68C6F30016AE4033435360D7680326A4
+S315080238102B00DBB25B0016FA03F39F43D1F808C00C
+S315080238202B00DBB25B001CFA03FC5CEA0707D760D5
+S315080238304B68022B02D04B68122B1DD12B00DB08DA
+S3150802384002EB83031F6A5FF00F0C15F00703DBB266
+S315080238509B001CFA03FC37EA0C07D1F810C015F0D6
+S315080238600703DBB29B001CFA03FC5CEA07072B0082
+S31508023870DB0802EB83031F6217682B00DBB25B00CF
+S315080238809E40B7430E7916F003062B00DBB25B00A7
+S315080238909E40374317604B68DB007FF581AF314B9B
+S315080238A01E6856F002061E601B6813F00203009398
+S315080238B0009B2D4E2B009B0856F823705FF00F0CC9
+S315080238C015F00303DBB29B001CFA03FC37EA0C076C
+S315080238D0264B9A4202D15FF0000C34E7244B9A42F7
+S315080238E002D15FF0010C2EE7224B9A4202D15FF019
+S315080238F0020C28E7204B9A4202D15FF0030C22E71A
+S315080239001E4B9A4202D15FF0040C1CE71C4B9A42EA
+S3150802391002D15FF0050C16E71A4B9A4202D15FF004
+S31508023920060C10E7184B9A4202D15FF0070C0AE719
+S31508023930164B9A427FF401AF5FF0080C03E7F1BC1D
+S315080239407047D2B2002A02D089B2816102E089B2F6
+S31508023950090481617047000080000058002402585B
+S3150802396004000058F444025808040058000002589B
+S315080239700004025800080258000C025800100258A7
+S315080239800014025800180258001C02580020025857
+S3150802399078B593B004006846DFF878154C2200F033
+S315080239A06BFD002C01D101205AE1DFF86C55206825
+S315080239B0A84203D1206810F580706060A068B0F54F
+S315080239C0407F206C0028A06C0028206D0028206EFD
+S315080239D00028E06D216E0818002894F8980000283F
+S315080239E005D1002084F89900200000F0ABFB20687E
+S315080239F0806930F0100021688861FEF751F90600E7
+S31508023A002068806900070FD5FEF74AF9801B0B2844
+S31508023A10F6D3D4F89C0050F00100C4F89C000320A9
+S31508023A2084F8980001201BE12068806950F00100A3
+S31508023A3021688861FEF734F9060020688069C007A4
+S31508023A400FD4FEF72DF9801B0B28F6D3D4F89C0069
+S31508023A5050F00100C4F89C00032084F89800012065
+S31508023A60FEE02068806950F0020021688861207CA7
+S31508023A70012806D12068806930F0400021688861F3
+S31508023A8005E02068806950F0400021688861607C02
+S31508023A90012806D12068806950F48040216888612F
+S31508023AA005E02068806930F4804021688861A07C3E
+S31508023AB0012806D12068806930F48050216888611F
+S31508023AC005E02068806950F4805021688861206882
+S31508023AD0816931F44071A0680143206881612068D8
+S31508023AE0806930F0A400216888612068006930F096
+S31508023AF0100021680861E068012806D120688069FB
+S31508023B0050F004002168886121E0E06800281ED090
+S31508023B10E068022815D02068806950F08000216884
+S31508023B2088612068006950F0100021680861E06821
+S31508023B3003280CD12068806950F02000216888612A
+S31508023B4005E02068806950F0200021688861A06934
+S31508023B50401EE169491E090251EA4061206A401E77
+S31508023B6001436069401E51EA00412068C161A068AC
+S31508023B70B0F5407F0FD1A06A401EE16A491E50EA9D
+S31508023B800120216B491E50EA0110616A491E50EA5A
+S31508023B9001402168C860206E002807D02068D0F846
+S31508023BA0C010606E01432068C0F8C010E06D216E37
+S31508023BB0081800280CD02068D0F8C810C908C9000F
+S31508023BC06846A26E50F8220001432068C0F8C81061
+S31508023BD0206C00280CD02068D0F8BC10C908C9008F
+S31508023BE06846626C50F8220001432068C0F8BC108F
+S31508023BF0A06C00280DD02068D0F8BC0030F0700008
+S31508023C006946E26C51F8221050EA01102168C1F89F
+S31508023C10BC00206D00280DD02068D0F8BC0030F416
+S31508023C20E0606946626D51F8221050EA0120216867
+S31508023C30C1F8BC002068A84205D16068806880087F
+S31508023C408000616888600020C4F894000020C4F8E7
+S31508023C509C00012084F89800200000F06FF9C0B299
+S31508023C6014B070BD10B490F898201300DBB2012B83
+S31508023C7002D0D2B2022A3BD1CA68072A0A68002AA7
+S31508023C801ED1CA68072ACA68072A09D10A69CB69EE
+S31508023C901B0253EA02438A69134353F0605309E04D
+S31508023CA08A68CB68DB0653EA82730A6953EA0243D7
+S31508023CB04A691343C06E496810EB8100036015E038
+S31508023CC0CA68072ACB680A6952EA4372CB68072B85
+S31508023CD001D18B6903E08C684B6953EA8473006FE0
+S31508023CE0496810EBC1000260001D0360002006E06F
+S31508023CF0D0F89C1051F00201C0F89C10012010BCAB
+S31508023D00704710B490F89840012C0BD1019C920090
+S31508023D1052EA011252EA430222430068C0F880209E
+S31508023D20002006E0D0F89C1051F00401C0F89C105F
+S31508023D30012010BC704790F8981001290DD1022174
+S31508023D4080F89810016889694908490002689161F2
+S31508023D500021C0F89C10002006E0D0F89C1051F013
+S31508023D600401C0F89C1001207047F0B4002590F8B1
+S31508023D709840E4B2022C40F0C380402927D1046857
+S31508023D80D4F8A04014F4FE0F07D1D0F89C1051F0D5
+S31508023D902001C0F89C100120B9E00468D4F8A440B8
+S31508023DA014F07F0F07D1D0F89C1051F48071C0F837
+S31508023DB09C100120ABE00468D4F8A440C4F305259E
+S31508023DC0466F446C04FB05F416EB84063AE0412977
+S31508023DD027D10468D4F8B04014F4FE0F07D1D0F8FE
+S31508023DE09C1051F02001C0F89C1001208FE0046855
+S31508023DF0D4F8B44014F07F0F07D1D0F89C1051F4D0
+S31508023E008071C0F89C10012081E00468D4F8B4409F
+S31508023E10C4F30525866FC46C04FB05F416EB840609
+S31508023E2010E0046DA14207D3D0F89C1051F020018E
+S31508023E30C0F89C1001206AE0C66F446D04FB01F4C9
+S31508023E4016EB8406346814F0804454605468002CD7
+S31508023E5004D13468C4F38A44146003E0346824F055
+S31508023E6060441460346814F000549460346814F0A2
+S31508023E7000441461341D2668B6B2D661266816F463
+S31508023E807026D660266816F480165661266816F4D9
+S31508023E90001696612668C6F3066616622668F60F47
+S31508023EA05662241D002602E0A75D9F55761CDFF8A0
+S31508023EB08870D2F80CC05FEA1C4C17F80C70BE4228
+S31508023EC0F2D3402903D10068C0F8A85016E0412968
+S31508023ED003D10068C0F8B85010E0202906D20122A2
+S31508023EE012FA01F10068C0F8981007E0012211F0F1
+S31508023EF01F0112FA01F10068C0F89C10002006E0C2
+S31508023F00D0F89C1051F00801C0F89C100120F0BCB2
+S31508023F10704700000045020800A00040402905D16C
+S31508023F200068D0F8A40010F07F0004E00068D0F81A
+S31508023F30B40010F07F0070474046020810B4436B85
+S31508023F407D4A0168D1F88410114051EA8301046858
+S31508023F50C4F884100168D1F8841031F47F01846BA7
+S31508023F6051EA04410468C4F88410816BCB180168CD
+S31508023F70D1F88810114051EA83010468C4F8881000
+S31508023F800168D1F8881031F4FE01C46B51EA044184
+S31508023F900468C4F88810C16B13EB41030168D1F8B1
+S31508023FA0A010114051EA83010468C4F8A010016800
+S31508023FB0D1F8A01031F4FE01046C51EA04410468F8
+S31508023FC0C4F8A010046C416C01FB04330168D1F8F3
+S31508023FD0B010114051EA83010468C4F8B0100168B0
+S31508023FE0D1F8B01031F4FE01846C51EA0441046838
+S31508023FF0C4F8B010846CC16C01FB04330168D1F8B3
+S31508024000AC10114051EA83010468C4F8AC10046D7F
+S31508024010416D01FB04330168D1F8F010114051EAF1
+S3150802402083010468C4F8F0100168D1F8F01031F47D
+S315080240307C11846D51EA04410468C4F8F010816D5C
+S3150802404013EB41030168D1F8C0100A4052EA830211
+S315080240500168C1F8C0200168D1F8C01031F47C119A
+S31508024060C26D51EA02410268C2F8C0100168D1F86D
+S31508024070C01031F07C51026E51EA02610268C2F840
+S31508024080C010416B2D4A12EB8102C266C16E826B69
+S3150802409011EB82010167016FC26B11EBC201416725
+S315080240A0426F036C416C4B4312EB83028267826F49
+S315080240B0836CC16C4B4312EB8302C267C26F036DFA
+S315080240C0416D4B4312EB8302C0F88020D0F8801072
+S315080240D0826D11EBC201C0F88410D0F88420C36D3A
+S315080240E0816E4B4312EB8302C0F88820D0F88820F1
+S315080240F0036E816E4B4312EB8302C0F89020D0F810
+S3150802410090100F4A91420AD3D0F89C1051F0200120
+S31508024110C0F89C10032180F89810012009E0C16EAE
+S3150802412002E000220A60091DD0F890209142F8D3D5
+S31508024130002010BC704700000300FFFF00AC0040DF
+S31508024140FDD30040704700009248016851F470019F
+S3150802415001609149086850F00100086000208F4A02
+S3150802416010600A688E4802400A6000208D4A106074
+S3150802417000208D4A106000208C4A106000208C4A6C
+S31508024180106000208B4A106000208B4A10600020C5
+S315080241908A4A106000208A4A10600020894A106004
+S315080241A00020894A10600020884A1060086830F4A6
+S315080241B08020086000208649086086480068000C4E
+S315080241C00004B0F1005F02D20120834908605FF063
+S315080241D000608249086070477048006810F038002D
+S315080241E0002806D008280BD010280BD018280BD088
+S315080241F0B4E07B4968480068C0F3C100C140AEE03C
+S315080242007849ACE07849AAE06948026812F00302E4
+S315080242100068C0F3051067490B6813F00103674984
+S315080242200968C1F3CC014B4300EE103AF8EE400A96
+S31508024230002800F09180002A03D0022A43D025D311
+S315080242405EE06749544A1268C2F3C102D14000EEE1
+S31508024250101AB8EE400A01EE100AB8EE411A80EEBC
+S31508024260010A55480068C005C00D01EE100AB8EEED
+S31508024270411ADFED451AC0EEA10A71EE200AB7EE21
+S31508024280001A70EE810A60EE200A55E000EE100A66
+S31508024290B8EE400A9FED3D1A81EE000A46480068CC
+S315080242A0C005C00D01EE100AB8EE411ADFED361A46
+S315080242B0C0EEA10A71EE200AB7EE001A70EE810A64
+S315080242C060EE200A38E000EE100AB8EE400A9FEDCA
+S315080242D0301A81EE000A38480068C005C00D01EEA2
+S315080242E0100AB8EE411ADFED281AC0EEA10A71EEDD
+S315080242F0200AB7EE001A70EE810A60EE200A1BE069
+S3150802430000EE100AB8EE400A9FED201A81EE000A66
+S3150802431029480068C005C00D01EE100AB8EE411A18
+S31508024320DFED191AC0EEA10A71EE200AB7EE001ADD
+S3150802433070EE810A60EE200A1F480068C0F3462024
+S31508024340401C00EE100AB8EE400A80EE800ABCEE67
+S31508024350C00A10EE101A00E0002100E02149114AB5
+S31508024360224B1068C0F30320185CC140106810F095
+S315080243700F00185C10F01F000A00C2401C480260B9
+S315080243801C48016070470000000000460024744A79
+S315080243900024F44A88ED00E000440258104402580A
+S315080243A07FEDF6EA184402581C4402582044025883
+S315080243B0284402582C4402583044025834440258BD
+S315080243C0384402583C44025840440258444402586D
+S315080243D0604402580010005C0881005108ED00E0B4
+S315080243E00090D00300093D0000127A0050460208E8
+S315080243F0080000200400002003480168034A1278D6
+S3150802440089180160704700BF880100200C0000204F
+S3150802441062F30F2262F31F42401810F0030308D01A
+S31508024420C91A1FD3DB0748BF00F8012D28BF20F899
+S31508024430022D130030B414461546103928BF20E958
+S315080244403C00FAD8490728BF20E90C0048BF40F8C3
+S31508024450042D890028BF20F8022D48BF00F8012D37
+S3150802446030BC7047C91818BF00F8012DCB0728BF02
+S3150802447000F8012D70470000103A07D330B4B1E8AE
+S315080244803810103AA0E83810F9D230BC530724BFC6
+S31508024490B1E80810A0E8081044BF51F8043B40F8F8
+S315080244A0043BD20724BF31F8022B20F8022B44BF63
+S315080244B00B7803707047121F17D35B0009D151F8A6
+S315080244C0043B20F8023B1B0C121F20F8023BF6D2D3
+S315080244D00BE051F8043B00F8013B1B0A20F8023BAB
+S315080244E01B0C121F00F8013BF3D238BF121D521ED5
+S315080244F024BF11F8013B00F8013BF8D870470000C9
+S31508024500000000000000000000000000000000009B
+S315080245100000000001000000020000000300000085
+S315080245200400000000000000050000000000000072
+S315080245300000000000000000060000000000000065
+S3150802454000000000000000000700000010B507493F
+S3150802455079441831064C7C44163404E00A68081D6E
+S31508024560114488470146A142F8D110BD5000000007
+S315080245707000000005020602060307030803090382
+S3150802458009040A040B040C040C050D050E050F0597
+S315080245900F061006100710084EF68851CEF20001D3
+S315080245A0086840F470000860BFF34F8FBFF36F8F3F
+S315080245B04FF00070E1EE100A70470000ABD6FFFF1D
+S315080245C080010000100000200000000097E8FFFFAD
+S315080245D0100000008C00000000000020000000000F
+S315080245E000F00DF8002801D0FFF7B0FFAFF3008006
+S315080245F00020AFF30080FEF745FD00F002F8012027
+S31508024600704700F001B800000746384600F002F885
+S31508024610FBE7000080B5AFF30080024A11001820BC
+S31508024620ABBEFBE7260002000248854602488047E1
+S3150802463002480047900500204941020871460208CF
+S315080246400001020304050607080C1014182030405E
+S315080246500000000001020304010203040607080918
+S31508024660100000000090D0030090D0030100000063
+S31508024670AFF30080FFF790FFFFF7B2FFFFF7FEBF29
+S31508024680FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF4E
+S31508024690FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF3E
+S315080246A0FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF2E
+S315080246B0FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF1E
+S315080246C0FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF0E
+S315080246D0FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFFE
+S315080246E0FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFEE
+S315080246F0FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFDE
+S31508024700FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFCD
+S31508024710FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFBD
+S31508024720FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFAD
+S31508024730FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF9D
+S31508024740FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF8D
+S31508024750FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF7D
+S31508024760FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF6D
+S31508024770FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF5D
+S31508024780FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF4D
+S31508024790FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF3D
+S315080247A0FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF2D
+S315080247B0FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF1D
+S315080247C0FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF0D
+S315080247D0FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFFD
+S315080247E0FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFED
+S315080247F0FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFDD
+S31508024800FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFCC
+S31508024810FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFBC
+S31508024820FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBFAC
+S31508024830FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF9C
+S31508024840FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF8C
+S31508024850FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF7C
+S31508024860FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF6C
+S31508024870FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF5C
+S31508024880FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF4C
+S31508024890FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF3C
+S315080248A0FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF2C
+S315080248B0FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF1C
+S30D080248C0FFF7FEBFFFF7FEBF7A
+S7050802467139
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/boot.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/boot.c
new file mode 100644
index 00000000..161c1c4d
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/boot.c
@@ -0,0 +1,498 @@
+/************************************************************************************//**
+* \file         Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/boot.c
+* \brief        Demo program bootloader interface source file.
+* \ingroup      Prog_ARMCM7_STM32H7_Nucleo_H743ZI_IAR
+* \internal
+*----------------------------------------------------------------------------------------
+*                          C O P Y R I G H T
+*----------------------------------------------------------------------------------------
+*   Copyright (c) 2020  by Feaser    http://www.feaser.com    All rights reserved
+*
+*----------------------------------------------------------------------------------------
+*                            L I C E N S E
+*----------------------------------------------------------------------------------------
+* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as published by the Free
+* Software Foundation, either version 3 of the License, or (at your option) any later
+* version.
+*
+* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+* PURPOSE. See the GNU General Public License for more details.
+*
+* You have received a copy of the GNU General Public License along with OpenBLT. It
+* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
+*
+* \endinternal
+****************************************************************************************/
+
+/****************************************************************************************
+* Include files
+****************************************************************************************/
+#include "header.h"                                    /* generic header               */
+
+
+/****************************************************************************************
+* Function prototypes
+****************************************************************************************/
+#if (BOOT_COM_RS232_ENABLE > 0)
+static void BootComRs232Init(void);
+static void BootComRs232CheckActivationRequest(void);
+#endif
+#if (BOOT_COM_CAN_ENABLE > 0)
+static void BootComCanInit(void);
+static void BootComCanCheckActivationRequest(void);
+#endif
+
+
+/************************************************************************************//**
+** \brief     Initializes the communication interface.
+** \return    none.
+**
+****************************************************************************************/
+void BootComInit(void)
+{
+#if (BOOT_COM_RS232_ENABLE > 0)
+  BootComRs232Init();
+#endif
+#if (BOOT_COM_CAN_ENABLE > 0)
+  BootComCanInit();
+#endif
+} /*** end of BootComInit ***/
+
+
+/************************************************************************************//**
+** \brief     Receives the CONNECT request from the host, which indicates that the
+**            bootloader should be activated and, if so, activates it.
+** \return    none.
+**
+****************************************************************************************/
+void BootComCheckActivationRequest(void)
+{
+#if (BOOT_COM_RS232_ENABLE > 0)
+  BootComRs232CheckActivationRequest();
+#endif
+#if (BOOT_COM_CAN_ENABLE > 0)
+  BootComCanCheckActivationRequest();
+#endif
+} /*** end of BootComCheckActivationRequest ***/
+
+
+/************************************************************************************//**
+** \brief     Bootloader activation function.
+** \return    none.
+**
+****************************************************************************************/
+void BootActivate(void)
+{
+  /* perform software reset to activate the bootoader again */
+  NVIC_SystemReset();
+} /*** end of BootActivate ***/
+
+
+#if (BOOT_COM_RS232_ENABLE > 0)
+/****************************************************************************************
+*     U N I V E R S A L   A S Y N C H R O N O U S   R X   T X   I N T E R F A C E
+****************************************************************************************/
+
+/****************************************************************************************
+* Macro definitions
+****************************************************************************************/
+/** \brief Timeout time for the reception of a CTO packet. The timer is started upon
+ *         reception of the first packet byte.
+ */
+#define RS232_CTO_RX_PACKET_TIMEOUT_MS (100u)
+
+
+/****************************************************************************************
+* Local data declarations
+****************************************************************************************/
+/** \brief UART handle to be used in API calls. */
+static UART_HandleTypeDef rs232Handle;
+
+
+/****************************************************************************************
+* Function prototypes
+****************************************************************************************/
+static unsigned char Rs232ReceiveByte(unsigned char *data);
+
+
+/************************************************************************************//**
+** \brief     Initializes the UART communication interface.
+** \return    none.
+**
+****************************************************************************************/
+static void BootComRs232Init(void)
+{
+  /* Configure UART peripheral. */
+  rs232Handle.Instance        = USART3;
+  rs232Handle.Init.BaudRate   = BOOT_COM_RS232_BAUDRATE;
+  rs232Handle.Init.WordLength = UART_WORDLENGTH_8B;
+  rs232Handle.Init.StopBits = UART_STOPBITS_1;
+  rs232Handle.Init.Parity = UART_PARITY_NONE;
+  rs232Handle.Init.Mode = UART_MODE_TX_RX;
+  rs232Handle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  rs232Handle.Init.OverSampling = UART_OVERSAMPLING_16;
+  rs232Handle.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+  rs232Handle.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  /* Initialize the UART peripheral. */
+  HAL_UART_Init(&rs232Handle);
+} /*** end of BootComRs232Init ***/
+
+
+/************************************************************************************//**
+** \brief     Receives the CONNECT request from the host, which indicates that the
+**            bootloader should be activated and, if so, activates it.
+** \return    none.
+**
+****************************************************************************************/
+static void BootComRs232CheckActivationRequest(void)
+{
+  static unsigned char xcpCtoReqPacket[BOOT_COM_RS232_RX_MAX_DATA+1];
+  static unsigned char xcpCtoRxLength;
+  static unsigned char xcpCtoRxInProgress = 0;
+  static unsigned long xcpCtoRxStartTime = 0;
+
+  /* start of cto packet received? */
+  if (xcpCtoRxInProgress == 0)
+  {
+    /* store the message length when received */
+    if (Rs232ReceiveByte(&xcpCtoReqPacket[0]) == 1)
+    {
+      /* check that the length has a valid value. it should not be 0 */
+      if ( (xcpCtoReqPacket[0] > 0) &&
+           (xcpCtoReqPacket[0] <= BOOT_COM_RS232_RX_MAX_DATA) )
+      {
+        /* store the start time */
+        xcpCtoRxStartTime = TimerGet();
+        /* indicate that a cto packet is being received */
+        xcpCtoRxInProgress = 1;
+        /* reset packet data count */
+        xcpCtoRxLength = 0;
+      }
+    }
+  }
+  else
+  {
+    /* store the next packet byte */
+    if (Rs232ReceiveByte(&xcpCtoReqPacket[xcpCtoRxLength+1]) == 1)
+    {
+      /* increment the packet data count */
+      xcpCtoRxLength++;
+
+      /* check to see if the entire packet was received */
+      if (xcpCtoRxLength == xcpCtoReqPacket[0])
+      {
+        /* done with cto packet reception */
+        xcpCtoRxInProgress = 0;
+
+        /* check if this was an XCP CONNECT command */
+        if ((xcpCtoReqPacket[1] == 0xff) && (xcpCtoRxLength == 2))
+        {
+          /* connection request received so start the bootloader */
+          BootActivate();
+        }
+      }
+    }
+    else
+    {
+      /* check packet reception timeout */
+      if (TimerGet() > (xcpCtoRxStartTime + RS232_CTO_RX_PACKET_TIMEOUT_MS))
+      {
+        /* cancel cto packet reception due to timeout. note that this automatically
+         * discards the already received packet bytes, allowing the host to retry.
+         */
+        xcpCtoRxInProgress = 0;
+      }
+    }
+  }
+} /*** end of BootComRs232CheckActivationRequest ***/
+
+
+/************************************************************************************//**
+** \brief     Receives a communication interface byte if one is present.
+** \param     data Pointer to byte where the data is to be stored.
+** \return    1 if a byte was received, 0 otherwise.
+**
+****************************************************************************************/
+static unsigned char Rs232ReceiveByte(unsigned char *data)
+{
+  HAL_StatusTypeDef result;
+
+  /* receive a byte in a non-blocking manner */
+  result = HAL_UART_Receive(&rs232Handle, data, 1, 0);
+  /* process the result */
+  if (result == HAL_OK)
+  {
+    /* success */
+    return 1;
+  }
+  /* error occurred */
+  return 0;
+} /*** end of Rs232ReceiveByte ***/
+#endif /* BOOT_COM_RS232_ENABLE > 0 */
+
+
+#if (BOOT_COM_CAN_ENABLE > 0)
+/****************************************************************************************
+*        C O N T R O L L E R   A R E A   N E T W O R K   I N T E R F A C E
+****************************************************************************************/
+
+/****************************************************************************************
+* Type definitions
+****************************************************************************************/
+/** \brief Structure type for grouping CAN bus timing related information. */
+typedef struct t_can_bus_timing
+{
+  unsigned char tseg1;                                /**< CAN time segment 1          */
+  unsigned char tseg2;                                /**< CAN time segment 2          */
+} tCanBusTiming;
+
+
+/****************************************************************************************
+* Local constant declarations
+****************************************************************************************/
+/** \brief CAN bittiming table for dynamically calculating the bittiming settings.
+ *  \details According to the CAN protocol 1 bit-time can be made up of between 8..25
+ *           time quanta (TQ). The total TQ in a bit is SYNC + TSEG1 + TSEG2 with SYNC
+ *           always being 1. The sample point is (SYNC + TSEG1) / (SYNC + TSEG1 + SEG2) *
+ *           100%. This array contains possible and valid time quanta configurations with
+ *           a sample point between 68..78%.
+ */
+static const tCanBusTiming canTiming[] =
+{                       /*  TQ | TSEG1 | TSEG2 | SP  */
+                        /* ------------------------- */
+    {  5, 2 },          /*   8 |   5   |   2   | 75% */
+    {  6, 2 },          /*   9 |   6   |   2   | 78% */
+    {  6, 3 },          /*  10 |   6   |   3   | 70% */
+    {  7, 3 },          /*  11 |   7   |   3   | 73% */
+    {  8, 3 },          /*  12 |   8   |   3   | 75% */
+    {  9, 3 },          /*  13 |   9   |   3   | 77% */
+    {  9, 4 },          /*  14 |   9   |   4   | 71% */
+    { 10, 4 },          /*  15 |  10   |   4   | 73% */
+    { 11, 4 },          /*  16 |  11   |   4   | 75% */
+    { 12, 4 },          /*  17 |  12   |   4   | 76% */
+    { 12, 5 },          /*  18 |  12   |   5   | 72% */
+    { 13, 5 },          /*  19 |  13   |   5   | 74% */
+    { 14, 5 },          /*  20 |  14   |   5   | 75% */
+    { 15, 5 },          /*  21 |  15   |   5   | 76% */
+    { 15, 6 },          /*  22 |  15   |   6   | 73% */
+    { 16, 6 },          /*  23 |  16   |   6   | 74% */
+    { 16, 7 },          /*  24 |  16   |   7   | 71% */
+    { 16, 8 }           /*  25 |  16   |   8   | 68% */
+};
+
+
+/****************************************************************************************
+* Local data declarations
+****************************************************************************************/
+/** \brief CAN handle to be used in API calls. */
+static FDCAN_HandleTypeDef canHandle;
+
+
+/************************************************************************************//**
+** \brief     Search algorithm to match the desired baudrate to a possible bus
+**            timing configuration.
+** \param     baud The desired baudrate in kbps. Valid values are 10..1000.
+** \param     prescaler Pointer to where the value for the prescaler will be stored.
+** \param     tseg1 Pointer to where the value for TSEG2 will be stored.
+** \param     tseg2 Pointer to where the value for TSEG2 will be stored.
+** \return    1 if the CAN bustiming register values were found, 0 otherwise.
+**
+****************************************************************************************/
+static unsigned char CanGetSpeedConfig(unsigned short baud, unsigned short *prescaler,
+                                       unsigned char *tseg1, unsigned char *tseg2)
+{
+  unsigned char cnt;
+  unsigned long canClockFreqkHz;
+
+  /* store CAN peripheral clock speed in kHz */
+  canClockFreqkHz = BOOT_CPU_XTAL_SPEED_KHZ;
+
+  /* loop through all possible time quanta configurations to find a match */
+  for (cnt=0; cnt < sizeof(canTiming)/sizeof(canTiming[0]); cnt++)
+  {
+    if ((canClockFreqkHz % (baud*(canTiming[cnt].tseg1+canTiming[cnt].tseg2+1))) == 0)
+    {
+      /* compute the prescaler that goes with this TQ configuration */
+      *prescaler = canClockFreqkHz/(baud*(canTiming[cnt].tseg1+canTiming[cnt].tseg2+1));
+
+      /* make sure the prescaler is valid */
+      if ( (*prescaler > 0) && (*prescaler <= 512) )
+      {
+        /* store the bustiming configuration */
+        *tseg1 = canTiming[cnt].tseg1;
+        *tseg2 = canTiming[cnt].tseg2;
+        /* found a good bus timing configuration */
+        return 1;
+      }
+    }
+  }
+  /* could not find a good bus timing configuration */
+  return 0;
+} /*** end of CanGetSpeedConfig ***/
+
+
+/************************************************************************************//**
+** \brief     Initializes the CAN communication interface.
+** \return    none.
+**
+****************************************************************************************/
+static void BootComCanInit(void)
+{
+  unsigned short prescaler = 0;
+  unsigned char tseg1 = 0, tseg2 = 0;
+  FDCAN_FilterTypeDef filterConfig;
+  unsigned long rxMsgId = BOOT_COM_CAN_RX_MSG_ID;
+
+  /* obtain bittiming configuration information. */
+  CanGetSpeedConfig(BOOT_COM_CAN_BAUDRATE/1000, &prescaler, &tseg1, &tseg2);
+
+  /* set the CAN controller configuration. */
+  canHandle.Instance = FDCAN1;
+  canHandle.Init.FrameFormat = FDCAN_FRAME_CLASSIC;
+  canHandle.Init.Mode = FDCAN_MODE_NORMAL;
+  canHandle.Init.AutoRetransmission = ENABLE;
+  canHandle.Init.TransmitPause = DISABLE;
+  canHandle.Init.ProtocolException = DISABLE;
+  canHandle.Init.NominalPrescaler = prescaler;
+  canHandle.Init.NominalSyncJumpWidth = 1;
+  canHandle.Init.NominalTimeSeg1 = tseg1;
+  canHandle.Init.NominalTimeSeg2 = tseg2;
+  /* FD mode is not used by this driver, so the .Init.DataXxx values are don't care. */
+  canHandle.Init.DataPrescaler = 1;
+  canHandle.Init.DataSyncJumpWidth = 1;
+  canHandle.Init.DataTimeSeg1 = 1;
+  canHandle.Init.DataTimeSeg2 = 1;
+  canHandle.Init.MessageRAMOffset = 0;
+  /* does the message to be received have a standard 11-bit CAN identifier? */
+  if ((rxMsgId & 0x80000000) == 0)
+  {
+    canHandle.Init.StdFiltersNbr = 1;
+    canHandle.Init.ExtFiltersNbr = 0;
+  }
+  else
+  {
+    canHandle.Init.StdFiltersNbr = 0;
+    canHandle.Init.ExtFiltersNbr = 1;
+  }
+  /* only reception FIFO 0 is used. */
+  canHandle.Init.RxFifo0ElmtsNbr = 1;
+  canHandle.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_8;
+  canHandle.Init.RxFifo1ElmtsNbr = 0;
+  canHandle.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_8;
+  canHandle.Init.RxBuffersNbr = 0;
+  canHandle.Init.RxBufferSize = FDCAN_DATA_BYTES_8;
+  /* no transmit buffer is needed. transmit FIFO is not used. */
+  canHandle.Init.TxEventsNbr = 0;
+  canHandle.Init.TxBuffersNbr = 0;
+  canHandle.Init.TxFifoQueueElmtsNbr = 0;
+  canHandle.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION;
+  canHandle.Init.TxElmtSize = FDCAN_DATA_BYTES_8;
+  /* initialize the CAN controller. this only fails if the CAN controller hardware is
+   * faulty. no need to evaluate the return value as there is nothing we can do about
+   * a faulty CAN controller.
+   */
+  (void)HAL_FDCAN_Init(&canHandle);
+
+  /* configure the reception filter. note that the implementation of this function
+   * always returns HAL_OK as long as the CAN controller is initialized, so no need to
+   * evaluate the return value.
+   */
+  if ((rxMsgId & 0x80000000) == 0)
+  {
+    filterConfig.IdType = FDCAN_STANDARD_ID;
+  }
+  else
+  {
+    filterConfig.IdType = FDCAN_EXTENDED_ID;
+    /* negate the ID-type bit */
+    rxMsgId &= ~0x80000000;
+  }
+  filterConfig.FilterIndex = 0;
+  filterConfig.FilterType = FDCAN_FILTER_DUAL;
+  filterConfig.FilterConfig = FDCAN_FILTER_TO_RXFIFO0;
+  filterConfig.FilterID1 = rxMsgId;
+  filterConfig.FilterID2 = rxMsgId;
+  filterConfig.RxBufferIndex = 0;
+  (void)HAL_FDCAN_ConfigFilter(&canHandle, &filterConfig);
+
+  /* configure global filter to reject all non-matching frames. */
+  HAL_FDCAN_ConfigGlobalFilter(&canHandle, FDCAN_REJECT, FDCAN_REJECT, 
+                               FDCAN_REJECT_REMOTE, FDCAN_REJECT_REMOTE);
+  
+  /* start the CAN peripheral. no need to evaluate the return value as there is nothing
+   * we can do about a faulty CAN controller. */
+  (void)HAL_FDCAN_Start(&canHandle);
+} /*** end of BootComCanInit ***/
+
+
+/************************************************************************************//**
+** \brief     Receives the CONNECT request from the host, which indicates that the
+**            bootloader should be activated and, if so, activates it.
+** \return    none.
+**
+****************************************************************************************/
+static void BootComCanCheckActivationRequest(void)
+{
+  unsigned long rxMsgId = BOOT_COM_CAN_RX_MSG_ID;
+  unsigned char packetIdMatches = 0;
+  FDCAN_RxHeaderTypeDef rxMsgHeader;
+  unsigned char rxMsgData[8];
+  unsigned char rxMsgLen;
+  HAL_StatusTypeDef rxStatus = HAL_ERROR;
+
+
+  /* poll for received CAN messages that await processing. */
+  if (HAL_FDCAN_GetRxFifoFillLevel(&canHandle, FDCAN_RX_FIFO0) > 0)
+  {
+    /* attempt to read the newly received CAN message from its buffer. */
+    rxStatus = HAL_FDCAN_GetRxMessage(&canHandle, FDCAN_RX_FIFO0, &rxMsgHeader,
+                                      rxMsgData);
+  }
+
+  /* only continue processing the CAN message if something was received. */
+  if (rxStatus == HAL_OK)
+  {
+    /* check if this message has the configured CAN packet identifier. */
+    if ((rxMsgId & 0x80000000) == 0)
+    {
+      /* was an 11-bit CAN message received that matches? */
+      if ( (rxMsgHeader.Identifier == rxMsgId) &&
+           (rxMsgHeader.IdType == FDCAN_STANDARD_ID) )
+      {
+        /* set flag that a packet with a matching CAN identifier was received. */
+        packetIdMatches = 1;
+      }
+    }
+    else
+    {
+      /* negate the ID-type bit */
+      rxMsgId &= ~0x80000000;
+      /* was an 29-bit CAN message received that matches? */
+      if ( (rxMsgHeader.Identifier == rxMsgId) &&
+           (rxMsgHeader.IdType == FDCAN_EXTENDED_ID) )
+      {
+        /* set flag that a packet with a matching CAN identifier was received. */
+        packetIdMatches = 1;
+      }
+    }
+
+    /* only continue if a packet with a matching CAN identifier was received. */
+    if (packetIdMatches == 1)
+    {
+      /* obtain the CAN message length. */
+      rxMsgLen = (unsigned char)(rxMsgHeader.DataLength >> 16U);
+      /* check if this was an XCP CONNECT command */
+      if ((rxMsgData[0] == 0xff) && (rxMsgLen == 2))
+      {
+        /* connection request received so start the bootloader */
+        BootActivate();
+      }
+    }
+  }
+} /*** end of BootComCanCheckActivationRequest ***/
+#endif /* BOOT_COM_CAN_ENABLE > 0 */
+
+
+/*********************************** end of boot.c *************************************/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/boot.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/boot.h
new file mode 100644
index 00000000..1f275f86
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/boot.h
@@ -0,0 +1,40 @@
+/************************************************************************************//**
+* \file         Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/boot.h
+* \brief        Demo program bootloader interface header file.
+* \ingroup      Prog_ARMCM7_STM32H7_Nucleo_H743ZI_IAR
+* \internal
+*----------------------------------------------------------------------------------------
+*                          C O P Y R I G H T
+*----------------------------------------------------------------------------------------
+*   Copyright (c) 2020  by Feaser    http://www.feaser.com    All rights reserved
+*
+*----------------------------------------------------------------------------------------
+*                            L I C E N S E
+*----------------------------------------------------------------------------------------
+* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as published by the Free
+* Software Foundation, either version 3 of the License, or (at your option) any later
+* version.
+*
+* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+* PURPOSE. See the GNU General Public License for more details.
+*
+* You have received a copy of the GNU General Public License along with OpenBLT. It
+* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
+*
+* \endinternal
+****************************************************************************************/
+#ifndef BOOT_H
+#define BOOT_H
+
+/****************************************************************************************
+* Function prototypes
+****************************************************************************************/
+void BootComInit(void);
+void BootComCheckActivationRequest(void);
+void BootActivate(void);
+
+
+#endif /* BOOT_H */
+/*********************************** end of boot.h *************************************/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/header.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/header.h
new file mode 100644
index 00000000..301ba9ce
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/header.h
@@ -0,0 +1,42 @@
+/************************************************************************************//**
+* \file         Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/header.h
+* \brief        Generic header file.
+* \ingroup      Prog_ARMCM7_STM32H7_Nucleo_H743ZI_IAR
+* \internal
+*----------------------------------------------------------------------------------------
+*                          C O P Y R I G H T
+*----------------------------------------------------------------------------------------
+*   Copyright (c) 2020  by Feaser    http://www.feaser.com    All rights reserved
+*
+*----------------------------------------------------------------------------------------
+*                            L I C E N S E
+*----------------------------------------------------------------------------------------
+* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as published by the Free
+* Software Foundation, either version 3 of the License, or (at your option) any later
+* version.
+*
+* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+* PURPOSE. See the GNU General Public License for more details.
+*
+* You have received a copy of the GNU General Public License along with OpenBLT. It
+* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
+*
+* \endinternal
+****************************************************************************************/
+#ifndef HEADER_H
+#define HEADER_H
+
+/****************************************************************************************
+* Include files
+****************************************************************************************/
+#include "../Boot/blt_conf.h"                          /* bootloader configuration     */
+#include "stm32h7xx.h"                                 /* STM32 CPU and HAL header     */
+#include "boot.h"                                      /* bootloader interface driver  */
+#include "led.h"                                       /* LED driver                   */
+#include "timer.h"                                     /* Timer driver                 */
+
+
+#endif /* HEADER_H */
+/*********************************** end of header.h ***********************************/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/ide/stm32h743.dep b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/ide/stm32h743.dep
new file mode 100644
index 00000000..631deaf9
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/ide/stm32h743.dep
@@ -0,0 +1,807 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<project>
+    <fileVersion>4</fileVersion>
+    <fileChecksum>480814510</fileChecksum>
+    <configuration>
+        <name>stm32h743</name>
+        <outputs>
+            <file>$PROJ_DIR$\..\lib\CMSIS\Include\mpu_armv7.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cortex.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma_ex.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dma_ex.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash.c</file>
+            <file>$PROJ_DIR$\..\lib\CMSIS\Device\ST\STM32H7xx\Include\stm32h7xx.h</file>
+            <file>$PROJ_DIR$\..\lib\CMSIS\Device\ST\STM32H7xx\Include\system_stm32h7xx.h</file>
+            <file>$PROJ_DIR$\..\lib\CMSIS\Device\ST\STM32H7xx\Include\stm32h743xx.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h</file>
+            <file>$PROJ_DIR$\..\lib\CMSIS\Include\core_cm7.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_cortex.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_def.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dma.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_exti.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_exti.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_fdcan.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_fdcan.h</file>
+            <file>$PROJ_DIR$\..\lib\CMSIS\Include\cmsis_version.h</file>
+            <file>$PROJ_DIR$\..\lib\CMSIS\Include\cmsis_compiler.h</file>
+            <file>$PROJ_DIR$\..\lib\CMSIS\Include\cmsis_iccarm.h</file>
+            <file>$PROJ_DIR$\..\obj\startup_stm32h743xx.o</file>
+            <file>$TOOLKIT_DIR$\lib\m7M_tlv.a</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_gpio.o</file>
+            <file>$PROJ_DIR$\..\obj\main.o</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_hsem.o</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_i2c.o</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_rcc.o</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_pwr_ex.o</file>
+            <file>$PROJ_DIR$\..\obj\boot.xcl</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_exti.o</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_uart_ex.xcl</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_i2c_ex.xcl</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_fdcan.o</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_pwr.o</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_uart.o</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_flash_ex.o</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_tim.xcl</file>
+            <file>$PROJ_DIR$\..\obj\demoprog_stm32h743.map</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_tim.o</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_cortex.o</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_flash.o</file>
+            <file>$PROJ_DIR$\..\obj\system_stm32h7xx.o</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_cortex.xcl</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_tim_ex.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_tim_ex.o</file>
+            <file>$PROJ_DIR$\..\bin\demoprog_stm32h743.srec</file>
+            <file>$TOOLKIT_DIR$\lib\dl7M_tln.a</file>
+            <file>$PROJ_DIR$\..\obj\timer.o</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_flash.xcl</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal.xcl</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_cortex.__cstat.et</file>
+            <file>$PROJ_DIR$\..\bin\demoprog_stm32h743.out</file>
+            <file>$PROJ_DIR$\..\obj\boot.__cstat.et</file>
+            <file>$TOOLKIT_DIR$\lib\rt7M_tl.a</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_exti.xcl</file>
+            <file>$PROJ_DIR$\..\obj\system_stm32h7xx.xcl</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_rcc.xcl</file>
+            <file>$TOOLKIT_DIR$\inc\c\math.h</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_dma_ex.xcl</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_i2c.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_rcc_ex.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\led.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_fdcan.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_rcc_ex.xcl</file>
+            <file>$TOOLKIT_DIR$\inc\c\stdint.h</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_rcc.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_gpio.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_flash.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_uart_ex.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_i2c.xcl</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_pwr_ex.xcl</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_uart.xcl</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_tim_ex.xcl</file>
+            <file>$PROJ_DIR$\..\obj\timer.xcl</file>
+            <file>$PROJ_DIR$\..\obj\main.xcl</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_gpio.xcl</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_exti.__cstat.et</file>
+            <file>$TOOLKIT_DIR$\inc\c\stddef.h</file>
+            <file>$PROJ_DIR$\..\obj\timer.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\stm32h743.pbd</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_fdcan.xcl</file>
+            <file>$TOOLKIT_DIR$\inc\c\DLib_Product.h</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal.o</file>
+            <file>$PROJ_DIR$\..\obj\led.o</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_i2c_ex.o</file>
+            <file>$PROJ_DIR$\..\obj\led.xcl</file>
+            <file>$PROJ_DIR$\..\obj\boot.o</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_rcc_ex.o</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_dma.xcl</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_flash_ex.xcl</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_uart_ex.o</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_hsem.xcl</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_dma.o</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_mdma.o</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_mdma.xcl</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_pwr.xcl</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_dma_ex.o</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_hsem.__cstat.et</file>
+            <file>$TOOLKIT_DIR$\inc\c\yvals.h</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_mdma.__cstat.et</file>
+            <file>$TOOLKIT_DIR$\inc\c\DLib_Config_Full.h</file>
+            <file>$PROJ_DIR$\..\startup_stm32h743xx.s</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_uart.__cstat.et</file>
+            <file>$TOOLKIT_DIR$\inc\c\ycheck.h</file>
+            <file>$PROJ_DIR$\..\led.c</file>
+            <file>$PROJ_DIR$\..\timer.c</file>
+            <file>$PROJ_DIR$\..\led.h</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_pwr_ex.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\main.__cstat.et</file>
+            <file>$PROJ_DIR$\..\boot.c</file>
+            <file>$TOOLKIT_DIR$\inc\c\DLib_float_setup.h</file>
+            <file>$PROJ_DIR$\..\stm32h743xx_flash.icf</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_pwr.__cstat.et</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_i2c_ex.__cstat.et</file>
+            <file>$TOOLKIT_DIR$\inc\c\ysizet.h</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_flash_ex.__cstat.et</file>
+            <file>$TOOLKIT_DIR$\inc\c\iccarm_builtin.h</file>
+            <file>$PROJ_DIR$\..\header.h</file>
+            <file>$PROJ_DIR$\..\boot.h</file>
+            <file>$TOOLKIT_DIR$\inc\c\DLib_Defaults.h</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_tim.__cstat.et</file>
+            <file>$TOOLKIT_DIR$\lib\shb_l.a</file>
+            <file>$PROJ_DIR$\..\..\Boot\blt_conf.h</file>
+            <file>$PROJ_DIR$\..\obj\system_stm32h7xx.__cstat.et</file>
+            <file>$PROJ_DIR$\..\lib\system_stm32h7xx.c</file>
+            <file>$PROJ_DIR$\..\main.c</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_dma.__cstat.et</file>
+            <file>$PROJ_DIR$\..\timer.h</file>
+            <file>$PROJ_DIR$\..\obj\stm32h7xx_hal_dma_ex.__cstat.et</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_flash_ex.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pwr_ex.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_gpio.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_hsem.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_i2c_ex.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mdma.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pwr.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc_ex.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_mdma.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c_ex.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_rcc.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_uart.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_i2c.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_uart.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim_ex.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_uart_ex.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_rcc_ex.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_uart_ex.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash_ex.c</file>
+            <file>$PROJ_DIR$\..\lib\stm32h7xx_hal_conf.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_gpio.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_flash.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_gpio_ex.h</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hsem.c</file>
+            <file>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr_ex.c</file>
+        </outputs>
+        <file>
+            <name>[ROOT_NODE]</name>
+            <outputs>
+                <tool>
+                    <name>ILINK</name>
+                    <file> 55 40</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cortex.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 42</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 54</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 45</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 14 155 144 11 5 7 9 68 107 102 123 104 85 20 21 22 120 0 6 8 81 118 61 114 152 135 159 13 3 142 16 10 19 158 133 136 147 137 139 134 148 153</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma_ex.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 100</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 132</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 62</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 14 155 144 11 5 7 9 68 107 102 123 104 85 20 21 22 120 0 6 8 81 118 61 114 152 135 159 13 3 142 16 10 19 158 133 136 147 137 139 134 148 153</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 43</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 71</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 52</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 14 155 144 11 5 7 9 68 107 102 123 104 85 20 21 22 120 0 6 8 81 118 61 114 152 135 159 13 3 142 16 10 19 158 133 136 147 137 139 134 148 153</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 96</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 130</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 92</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 14 155 144 11 5 7 9 68 107 102 123 104 85 20 21 22 120 0 6 8 81 118 61 114 152 135 159 13 3 142 16 10 19 158 133 136 147 137 139 134 148 153</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 86</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 51</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 53</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 14 155 144 11 5 7 9 68 107 102 123 104 85 20 21 22 120 0 6 8 81 118 61 114 152 135 159 13 3 142 16 10 19 158 133 136 147 137 139 134 148 153</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_exti.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 32</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 80</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 58</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 14 155 144 11 5 7 9 68 107 102 123 104 85 20 21 22 120 0 6 8 81 118 61 114 152 135 159 13 3 142 16 10 19 158 133 136 147 137 139 134 148 153</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_fdcan.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 35</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 66</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 84</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 14 155 144 11 5 7 9 68 107 102 123 104 85 20 21 22 120 0 6 8 81 118 61 114 152 135 159 13 3 142 16 10 19 158 133 136 147 137 139 134 148 153</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\bin\demoprog_stm32h743.out</name>
+            <outputs>
+                <tool>
+                    <name>ILINK</name>
+                    <file> 40</file>
+                </tool>
+                <tool>
+                    <name>OBJCOPY</name>
+                    <file> 48</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ILINK</name>
+                    <file> 115 90 87 26 23 86 42 96 100 32 35 43 38 25 27 28 88 97 36 30 29 91 41 47 37 94 44 50 125 57 24 49</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\startup_stm32h743xx.s</name>
+            <outputs>
+                <tool>
+                    <name>AARM</name>
+                    <file> 23</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\led.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 87</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 65</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 89</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 121 126 5 7 9 68 107 102 123 104 85 20 21 22 120 0 6 14 155 144 11 8 81 118 61 114 152 135 159 13 3 142 16 10 19 158 133 136 147 137 139 134 148 153 122 110 131</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\timer.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 50</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 82</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 77</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 121 126 5 7 9 68 107 102 123 104 85 20 21 22 120 0 6 14 155 144 11 8 81 118 61 114 152 135 159 13 3 142 16 10 19 158 133 136 147 137 139 134 148 153 122 110 131</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\boot.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 90</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 56</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 31</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 121 126 5 7 9 68 107 102 123 104 85 20 21 22 120 0 6 14 155 144 11 8 81 118 61 114 152 135 159 13 3 142 16 10 19 158 133 136 147 137 139 134 148 153 122 110 131</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\system_stm32h7xx.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 44</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 127</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 59</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 5 7 9 68 107 102 123 104 85 20 21 22 120 0 6 14 155 144 11 8 81 118 61 114 152 135 159 13 3 142 16 10 19 158 133 136 147 137 139 134 148 153</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\main.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 26</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 112</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 78</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 121 126 5 7 9 68 107 102 123 104 85 20 21 22 120 0 6 14 155 144 11 8 81 118 61 114 152 135 159 13 3 142 16 10 19 158 133 136 147 137 139 134 148 153 122 110 131</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mdma.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 97</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 103</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 98</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 14 155 144 11 5 7 9 68 107 102 123 104 85 20 21 22 120 0 6 8 81 118 61 114 152 135 159 13 3 142 16 10 19 158 133 136 147 137 139 134 148 153</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc_ex.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 91</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 64</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 67</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 14 155 144 11 5 7 9 68 107 102 123 104 85 20 21 22 120 0 6 8 81 118 61 114 152 135 159 13 3 142 16 10 19 158 133 136 147 137 139 134 148 153</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 41</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 124</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 39</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 14 155 144 11 5 7 9 68 107 102 123 104 85 20 21 22 120 0 6 8 81 118 61 114 152 135 159 13 3 142 16 10 19 158 133 136 147 137 139 134 148 153</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c_ex.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 88</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 117</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 34</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 14 155 144 11 5 7 9 68 107 102 123 104 85 20 21 22 120 0 6 8 81 118 61 114 152 135 159 13 3 142 16 10 19 158 133 136 147 137 139 134 148 153</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 29</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 69</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 60</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 14 155 144 11 5 7 9 68 107 102 123 104 85 20 21 22 120 0 6 8 81 118 61 114 152 135 159 13 3 142 16 10 19 158 133 136 147 137 139 134 148 153</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_uart.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 37</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 106</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 75</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 14 155 144 11 5 7 9 68 107 102 123 104 85 20 21 22 120 0 6 8 81 118 61 114 152 135 159 13 3 142 16 10 19 158 133 136 147 137 139 134 148 153</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim_ex.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 47</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 46</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 76</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 14 155 144 11 5 7 9 68 107 102 123 104 85 20 21 22 120 0 6 8 81 118 61 114 152 135 159 13 3 142 16 10 19 158 133 136 147 137 139 134 148 153</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_uart_ex.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 94</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 72</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 33</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 14 155 144 11 5 7 9 68 107 102 123 104 85 20 21 22 120 0 6 8 81 118 61 114 152 135 159 13 3 142 16 10 19 158 133 136 147 137 139 134 148 153</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 28</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 63</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 73</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 14 155 144 11 5 7 9 68 107 102 123 104 85 20 21 22 120 0 6 8 81 118 61 114 152 135 159 13 3 142 16 10 19 158 133 136 147 137 139 134 148 153</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash_ex.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 38</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 119</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 93</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 14 155 144 11 5 7 9 68 107 102 123 104 85 20 21 22 120 0 6 8 81 118 61 114 152 135 159 13 3 142 16 10 19 158 133 136 147 137 139 134 148 153</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_gpio.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 25</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 70</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 79</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 14 155 144 11 5 7 9 68 107 102 123 104 85 20 21 22 120 0 6 8 81 118 61 114 152 135 159 13 3 142 16 10 19 158 133 136 147 137 139 134 148 153</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 36</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 116</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 99</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 14 155 144 11 5 7 9 68 107 102 123 104 85 20 21 22 120 0 6 8 81 118 61 114 152 135 159 13 3 142 16 10 19 158 133 136 147 137 139 134 148 153</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hsem.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 27</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 101</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 95</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 14 155 144 11 5 7 9 68 107 102 123 104 85 20 21 22 120 0 6 8 81 118 61 114 152 135 159 13 3 142 16 10 19 158 133 136 147 137 139 134 148 153</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr_ex.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 30</file>
+                </tool>
+                <tool>
+                    <name>__cstat</name>
+                    <file> 111</file>
+                </tool>
+                <tool>
+                    <name>BICOMP</name>
+                    <file> 74</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 14 155 144 11 5 7 9 68 107 102 123 104 85 20 21 22 120 0 6 8 81 118 61 114 152 135 159 13 3 142 16 10 19 158 133 136 147 137 139 134 148 153</file>
+                </tool>
+            </inputs>
+        </file>
+    </configuration>
+</project>
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/ide/stm32h743.ewd b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/ide/stm32h743.ewd
new file mode 100644
index 00000000..2bc76b4e
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/ide/stm32h743.ewd
@@ -0,0 +1,1419 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<project>
+	<fileVersion>3</fileVersion>
+	<configuration>
+		<name>stm32h743</name>
+		<toolchain>
+			<name>ARM</name>
+		</toolchain>
+		<debug>1</debug>
+		<settings>
+			<name>C-SPY</name>
+			<archiveVersion>2</archiveVersion>
+			<data>
+				<version>29</version>
+				<wantNonLocal>1</wantNonLocal>
+				<debug>1</debug>
+				<option>
+					<name>CInput</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>CEndian</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>CProcessor</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>OCVariant</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>MacOverride</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>MacFile</name>
+					<state />
+				</option>
+				<option>
+					<name>MemOverride</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>MemFile</name>
+					<state />
+				</option>
+				<option>
+					<name>RunToEnable</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>RunToName</name>
+					<state>main</state>
+				</option>
+				<option>
+					<name>CExtraOptionsCheck</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CExtraOptions</name>
+					<state />
+				</option>
+				<option>
+					<name>CFpuProcessor</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>OCDDFArgumentProducer</name>
+					<state />
+				</option>
+				<option>
+					<name>OCDownloadSuppressDownload</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>OCDownloadVerifyAll</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>OCProductVersion</name>
+					<state>7.10.3.6927</state>
+				</option>
+				<option>
+					<name>OCDynDriverList</name>
+					<state>STLINK_ID</state>
+				</option>
+				<option>
+					<name>OCLastSavedByProductVersion</name>
+					<state>8.20.1.14181</state>
+				</option>
+				<option>
+					<name>UseFlashLoader</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>CLowLevel</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>OCBE8Slave</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>MacFile2</name>
+					<state />
+				</option>
+				<option>
+					<name>CDevice</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>FlashLoadersV3</name>
+					<state />
+				</option>
+				<option>
+					<name>OCImagesSuppressCheck1</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>OCImagesPath1</name>
+					<state />
+				</option>
+				<option>
+					<name>OCImagesSuppressCheck2</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>OCImagesPath2</name>
+					<state />
+				</option>
+				<option>
+					<name>OCImagesSuppressCheck3</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>OCImagesPath3</name>
+					<state />
+				</option>
+				<option>
+					<name>OverrideDefFlashBoard</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>OCImagesOffset1</name>
+					<state />
+				</option>
+				<option>
+					<name>OCImagesOffset2</name>
+					<state />
+				</option>
+				<option>
+					<name>OCImagesOffset3</name>
+					<state />
+				</option>
+				<option>
+					<name>OCImagesUse1</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>OCImagesUse2</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>OCImagesUse3</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>OCDeviceConfigMacroFile</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>OCDebuggerExtraOption</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>OCAllMTBOptions</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>OCMulticoreNrOfCores</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>OCMulticoreMaster</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>OCMulticorePort</name>
+					<state>53461</state>
+				</option>
+				<option>
+					<name>OCMulticoreWorkspace</name>
+					<state />
+				</option>
+				<option>
+					<name>OCMulticoreSlaveProject</name>
+					<state />
+				</option>
+				<option>
+					<name>OCMulticoreSlaveConfiguration</name>
+					<state />
+				</option>
+				<option>
+					<name>OCDownloadExtraImage</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>OCAttachSlave</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>MassEraseBeforeFlashing</name>
+					<state>0</state>
+				</option>
+			</data>
+		</settings>
+		<settings>
+			<name>ARMSIM_ID</name>
+			<archiveVersion>2</archiveVersion>
+			<data>
+				<version>1</version>
+				<wantNonLocal>1</wantNonLocal>
+				<debug>1</debug>
+				<option>
+					<name>OCSimDriverInfo</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>OCSimEnablePSP</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>OCSimPspOverrideConfig</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>OCSimPspConfigFile</name>
+					<state />
+				</option>
+			</data>
+		</settings>
+		<settings>
+			<name>CADI_ID</name>
+			<archiveVersion>2</archiveVersion>
+			<data>
+				<version>0</version>
+				<wantNonLocal>1</wantNonLocal>
+				<debug>1</debug>
+				<option>
+					<name>CCadiMemory</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>Fast Model</name>
+					<state />
+				</option>
+				<option>
+					<name>CCADILogFileCheck</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCADILogFileEditB</name>
+					<state>$PROJ_DIR$\cspycomm.log</state>
+				</option>
+				<option>
+					<name>OCDriverInfo</name>
+					<state>1</state>
+				</option>
+			</data>
+		</settings>
+		<settings>
+			<name>CMSISDAP_ID</name>
+			<archiveVersion>2</archiveVersion>
+			<data>
+				<version>4</version>
+				<wantNonLocal>1</wantNonLocal>
+				<debug>1</debug>
+				<option>
+					<name>CatchSFERR</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>OCDriverInfo</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>OCIarProbeScriptFile</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>CMSISDAPResetList</name>
+					<version>1</version>
+					<state>10</state>
+				</option>
+				<option>
+					<name>CMSISDAPHWResetDuration</name>
+					<state>300</state>
+				</option>
+				<option>
+					<name>CMSISDAPHWResetDelay</name>
+					<state>200</state>
+				</option>
+				<option>
+					<name>CMSISDAPDoLogfile</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CMSISDAPLogFile</name>
+					<state>$PROJ_DIR$\cspycomm.log</state>
+				</option>
+				<option>
+					<name>CMSISDAPInterfaceRadio</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CMSISDAPInterfaceCmdLine</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CMSISDAPMultiTargetEnable</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CMSISDAPMultiTarget</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CMSISDAPJtagSpeedList</name>
+					<version>0</version>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CMSISDAPBreakpointRadio</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CMSISDAPRestoreBreakpointsCheck</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CMSISDAPUpdateBreakpointsEdit</name>
+					<state>_call_main</state>
+				</option>
+				<option>
+					<name>RDICatchReset</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>RDICatchUndef</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>RDICatchSWI</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>RDICatchData</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>RDICatchPrefetch</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>RDICatchIRQ</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>RDICatchFIQ</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CatchCORERESET</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CatchMMERR</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>CatchNOCPERR</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>CatchCHKERR</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>CatchSTATERR</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>CatchBUSERR</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>CatchINTERR</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>CatchHARDERR</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>CatchDummy</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CMSISDAPMultiCPUEnable</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CMSISDAPMultiCPUNumber</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>OCProbeCfgOverride</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>OCProbeConfig</name>
+					<state />
+				</option>
+				<option>
+					<name>CMSISDAPProbeConfigRadio</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CMSISDAPSelectedCPUBehaviour</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>ICpuName</name>
+					<state />
+				</option>
+				<option>
+					<name>OCJetEmuParams</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>CCCMSISDAPUsbSerialNo</name>
+					<state />
+				</option>
+				<option>
+					<name>CCCMSISDAPUsbSerialNoSelect</name>
+					<state>0</state>
+				</option>
+			</data>
+		</settings>
+		<settings>
+			<name>GDBSERVER_ID</name>
+			<archiveVersion>2</archiveVersion>
+			<data>
+				<version>0</version>
+				<wantNonLocal>1</wantNonLocal>
+				<debug>1</debug>
+				<option>
+					<name>OCDriverInfo</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>TCPIP</name>
+					<state>aaa.bbb.ccc.ddd</state>
+				</option>
+				<option>
+					<name>DoLogfile</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>LogFile</name>
+					<state>$PROJ_DIR$\cspycomm.log</state>
+				</option>
+				<option>
+					<name>CCJTagBreakpointRadio</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCJTagDoUpdateBreakpoints</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCJTagUpdateBreakpoints</name>
+					<state>_call_main</state>
+				</option>
+			</data>
+		</settings>
+		<settings>
+			<name>IJET_ID</name>
+			<archiveVersion>2</archiveVersion>
+			<data>
+				<version>8</version>
+				<wantNonLocal>1</wantNonLocal>
+				<debug>1</debug>
+				<option>
+					<name>CatchSFERR</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>OCDriverInfo</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>OCIarProbeScriptFile</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>IjetResetList</name>
+					<version>1</version>
+					<state>10</state>
+				</option>
+				<option>
+					<name>IjetHWResetDuration</name>
+					<state>300</state>
+				</option>
+				<option>
+					<name>IjetHWResetDelay</name>
+					<state>200</state>
+				</option>
+				<option>
+					<name>IjetPowerFromProbe</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>IjetPowerRadio</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IjetDoLogfile</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IjetLogFile</name>
+					<state>$PROJ_DIR$\cspycomm.log</state>
+				</option>
+				<option>
+					<name>IjetInterfaceRadio</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IjetInterfaceCmdLine</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IjetMultiTargetEnable</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IjetMultiTarget</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IjetScanChainNonARMDevices</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IjetIRLength</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IjetJtagSpeedList</name>
+					<version>0</version>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IjetProtocolRadio</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IjetSwoPin</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IjetCpuClockEdit</name>
+					<state>72.0</state>
+				</option>
+				<option>
+					<name>IjetSwoPrescalerList</name>
+					<version>1</version>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IjetBreakpointRadio</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IjetRestoreBreakpointsCheck</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IjetUpdateBreakpointsEdit</name>
+					<state>_call_main</state>
+				</option>
+				<option>
+					<name>RDICatchReset</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>RDICatchUndef</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>RDICatchSWI</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>RDICatchData</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>RDICatchPrefetch</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>RDICatchIRQ</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>RDICatchFIQ</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CatchCORERESET</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CatchMMERR</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>CatchNOCPERR</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>CatchCHKERR</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>CatchSTATERR</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>CatchBUSERR</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>CatchINTERR</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>CatchHARDERR</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>CatchDummy</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>OCProbeCfgOverride</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>OCProbeConfig</name>
+					<state />
+				</option>
+				<option>
+					<name>IjetProbeConfigRadio</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IjetMultiCPUEnable</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IjetMultiCPUNumber</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IjetSelectedCPUBehaviour</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>ICpuName</name>
+					<state />
+				</option>
+				<option>
+					<name>OCJetEmuParams</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>IjetPreferETB</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>IjetTraceSettingsList</name>
+					<version>0</version>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IjetTraceSizeList</name>
+					<version>0</version>
+					<state>4</state>
+				</option>
+				<option>
+					<name>FlashBoardPathSlave</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCIjetUsbSerialNo</name>
+					<state />
+				</option>
+				<option>
+					<name>CCIjetUsbSerialNoSelect</name>
+					<state>0</state>
+				</option>
+			</data>
+		</settings>
+		<settings>
+			<name>JLINK_ID</name>
+			<archiveVersion>2</archiveVersion>
+			<data>
+				<version>16</version>
+				<wantNonLocal>1</wantNonLocal>
+				<debug>1</debug>
+				<option>
+					<name>CCCatchSFERR</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>JLinkSpeed</name>
+					<state>1000</state>
+				</option>
+				<option>
+					<name>CCJLinkDoLogfile</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCJLinkLogFile</name>
+					<state>$PROJ_DIR$\cspycomm.log</state>
+				</option>
+				<option>
+					<name>CCJLinkHWResetDelay</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>OCDriverInfo</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>JLinkInitialSpeed</name>
+					<state>1000</state>
+				</option>
+				<option>
+					<name>CCDoJlinkMultiTarget</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCScanChainNonARMDevices</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCJLinkMultiTarget</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCJLinkIRLength</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCJLinkCommRadio</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCJLinkTCPIP</name>
+					<state>aaa.bbb.ccc.ddd</state>
+				</option>
+				<option>
+					<name>CCJLinkSpeedRadioV2</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCUSBDevice</name>
+					<version>1</version>
+					<state>1</state>
+				</option>
+				<option>
+					<name>CCRDICatchReset</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCRDICatchUndef</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCRDICatchSWI</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCRDICatchData</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCRDICatchPrefetch</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCRDICatchIRQ</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCRDICatchFIQ</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCJLinkBreakpointRadio</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCJLinkDoUpdateBreakpoints</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCJLinkUpdateBreakpoints</name>
+					<state>_call_main</state>
+				</option>
+				<option>
+					<name>CCJLinkInterfaceRadio</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCJLinkResetList</name>
+					<version>6</version>
+					<state>7</state>
+				</option>
+				<option>
+					<name>CCJLinkInterfaceCmdLine</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCCatchCORERESET</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCCatchMMERR</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCCatchNOCPERR</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCCatchCHRERR</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCCatchSTATERR</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCCatchBUSERR</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCCatchINTERR</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCCatchHARDERR</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCCatchDummy</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>OCJLinkScriptFile</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>CCJLinkUsbSerialNo</name>
+					<state />
+				</option>
+				<option>
+					<name>CCTcpIpAlt</name>
+					<version>0</version>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCJLinkTcpIpSerialNo</name>
+					<state />
+				</option>
+				<option>
+					<name>CCCpuClockEdit</name>
+					<state>72.0</state>
+				</option>
+				<option>
+					<name>CCSwoClockAuto</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCSwoClockEdit</name>
+					<state>2000</state>
+				</option>
+				<option>
+					<name>OCJLinkTraceSource</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>OCJLinkTraceSourceDummy</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>OCJLinkDeviceName</name>
+					<state>1</state>
+				</option>
+			</data>
+		</settings>
+		<settings>
+			<name>LMIFTDI_ID</name>
+			<archiveVersion>2</archiveVersion>
+			<data>
+				<version>2</version>
+				<wantNonLocal>1</wantNonLocal>
+				<debug>1</debug>
+				<option>
+					<name>OCDriverInfo</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>LmiftdiSpeed</name>
+					<state>500</state>
+				</option>
+				<option>
+					<name>CCLmiftdiDoLogfile</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCLmiftdiLogFile</name>
+					<state>$PROJ_DIR$\cspycomm.log</state>
+				</option>
+				<option>
+					<name>CCLmiFtdiInterfaceRadio</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCLmiFtdiInterfaceCmdLine</name>
+					<state>0</state>
+				</option>
+			</data>
+		</settings>
+		<settings>
+			<name>PEMICRO_ID</name>
+			<archiveVersion>2</archiveVersion>
+			<data>
+				<version>3</version>
+				<wantNonLocal>1</wantNonLocal>
+				<debug>1</debug>
+				<option>
+					<name>OCDriverInfo</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>CCJPEMicroShowSettings</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>DoLogfile</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>LogFile</name>
+					<state>$PROJ_DIR$\cspycomm.log</state>
+				</option>
+			</data>
+		</settings>
+		<settings>
+			<name>STLINK_ID</name>
+			<archiveVersion>2</archiveVersion>
+			<data>
+				<version>4</version>
+				<wantNonLocal>1</wantNonLocal>
+				<debug>1</debug>
+				<option>
+					<name>OCDriverInfo</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>CCSTLinkInterfaceRadio</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>CCSTLinkInterfaceCmdLine</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCSTLinkResetList</name>
+					<version>3</version>
+					<state>4</state>
+				</option>
+				<option>
+					<name>CCCpuClockEdit</name>
+					<state>240.0</state>
+				</option>
+				<option>
+					<name>CCSwoClockAuto</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCSwoClockEdit</name>
+					<state>2000</state>
+				</option>
+				<option>
+					<name>DoLogfile</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>LogFile</name>
+					<state>$PROJ_DIR$\cspycomm.log</state>
+				</option>
+				<option>
+					<name>CCSTLinkDoUpdateBreakpoints</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCSTLinkUpdateBreakpoints</name>
+					<state>_call_main</state>
+				</option>
+				<option>
+					<name>CCSTLinkCatchCORERESET</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCSTLinkCatchMMERR</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCSTLinkCatchNOCPERR</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCSTLinkCatchCHRERR</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCSTLinkCatchSTATERR</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCSTLinkCatchBUSERR</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCSTLinkCatchINTERR</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCSTLinkCatchSFERR</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCSTLinkCatchHARDERR</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCSTLinkCatchDummy</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCSTLinkUsbSerialNo</name>
+					<state />
+				</option>
+				<option>
+					<name>CCSTLinkUsbSerialNoSelect</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCSTLinkJtagSpeedList</name>
+					<version>0</version>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCSTLinkDAPNumber</name>
+					<state />
+				</option>
+				<option>
+					<name>CCSTLinkDebugAccessPortRadio</name>
+					<state>0</state>
+				</option>
+			</data>
+		</settings>
+		<settings>
+			<name>THIRDPARTY_ID</name>
+			<archiveVersion>2</archiveVersion>
+			<data>
+				<version>0</version>
+				<wantNonLocal>1</wantNonLocal>
+				<debug>1</debug>
+				<option>
+					<name>CThirdPartyDriverDll</name>
+					<state>###Uninitialized###</state>
+				</option>
+				<option>
+					<name>CThirdPartyLogFileCheck</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CThirdPartyLogFileEditB</name>
+					<state>$PROJ_DIR$\cspycomm.log</state>
+				</option>
+				<option>
+					<name>OCDriverInfo</name>
+					<state>1</state>
+				</option>
+			</data>
+		</settings>
+		<settings>
+			<name>TIFET_ID</name>
+			<archiveVersion>2</archiveVersion>
+			<data>
+				<version>1</version>
+				<wantNonLocal>1</wantNonLocal>
+				<debug>1</debug>
+				<option>
+					<name>OCDriverInfo</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>CCMSPFetResetList</name>
+					<version>0</version>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCMSPFetInterfaceRadio</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCMSPFetInterfaceCmdLine</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCMSPFetTargetVccTypeDefault</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCMSPFetTargetVoltage</name>
+					<state>###Uninitialized###</state>
+				</option>
+				<option>
+					<name>CCMSPFetVCCDefault</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>CCMSPFetTargetSettlingtime</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCMSPFetRadioJtagSpeedType</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>CCMSPFetConnection</name>
+					<version>0</version>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCMSPFetUsbComPort</name>
+					<state>Automatic</state>
+				</option>
+				<option>
+					<name>CCMSPFetAllowAccessToBSL</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCMSPFetDoLogfile</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCMSPFetLogFile</name>
+					<state>$PROJ_DIR$\cspycomm.log</state>
+				</option>
+				<option>
+					<name>CCMSPFetRadioEraseFlash</name>
+					<state>1</state>
+				</option>
+			</data>
+		</settings>
+		<settings>
+			<name>XDS100_ID</name>
+			<archiveVersion>2</archiveVersion>
+			<data>
+				<version>6</version>
+				<wantNonLocal>1</wantNonLocal>
+				<debug>1</debug>
+				<option>
+					<name>OCDriverInfo</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>TIPackageOverride</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>TIPackage</name>
+					<state />
+				</option>
+				<option>
+					<name>BoardFile</name>
+					<state />
+				</option>
+				<option>
+					<name>DoLogfile</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>LogFile</name>
+					<state>$PROJ_DIR$\cspycomm.log</state>
+				</option>
+				<option>
+					<name>CCXds100BreakpointRadio</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCXds100DoUpdateBreakpoints</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCXds100UpdateBreakpoints</name>
+					<state>_call_main</state>
+				</option>
+				<option>
+					<name>CCXds100CatchReset</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCXds100CatchUndef</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCXds100CatchSWI</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCXds100CatchData</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCXds100CatchPrefetch</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCXds100CatchIRQ</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCXds100CatchFIQ</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCXds100CatchCORERESET</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCXds100CatchMMERR</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCXds100CatchNOCPERR</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCXds100CatchCHRERR</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCXds100CatchSTATERR</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCXds100CatchBUSERR</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCXds100CatchINTERR</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCXds100CatchSFERR</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCXds100CatchHARDERR</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCXds100CatchDummy</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCXds100CpuClockEdit</name>
+					<state />
+				</option>
+				<option>
+					<name>CCXds100SwoClockAuto</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCXds100SwoClockEdit</name>
+					<state>1000</state>
+				</option>
+				<option>
+					<name>CCXds100HWResetDelay</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCXds100ResetList</name>
+					<version>0</version>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCXds100UsbSerialNo</name>
+					<state />
+				</option>
+				<option>
+					<name>CCXds100UsbSerialNoSelect</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCXds100JtagSpeedList</name>
+					<version>0</version>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCXds100InterfaceRadio</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCXds100InterfaceCmdLine</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCXds100ProbeList</name>
+					<version>0</version>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCXds100SWOPortRadio</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCXds100SWOPort</name>
+					<state>1</state>
+				</option>
+			</data>
+		</settings>
+		<debuggerPlugins>
+			<plugin>
+				<file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+				<loadFlag>0</loadFlag>
+			</plugin>
+			<plugin>
+				<file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+				<loadFlag>0</loadFlag>
+			</plugin>
+			<plugin>
+				<file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+				<loadFlag>0</loadFlag>
+			</plugin>
+			<plugin>
+				<file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin</file>
+				<loadFlag>0</loadFlag>
+			</plugin>
+			<plugin>
+				<file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+				<loadFlag>0</loadFlag>
+			</plugin>
+			<plugin>
+				<file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+				<loadFlag>0</loadFlag>
+			</plugin>
+			<plugin>
+				<file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+				<loadFlag>0</loadFlag>
+			</plugin>
+			<plugin>
+				<file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
+				<loadFlag>0</loadFlag>
+			</plugin>
+			<plugin>
+				<file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+				<loadFlag>0</loadFlag>
+			</plugin>
+			<plugin>
+				<file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+				<loadFlag>0</loadFlag>
+			</plugin>
+			<plugin>
+				<file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+				<loadFlag>0</loadFlag>
+			</plugin>
+			<plugin>
+				<file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
+				<loadFlag>1</loadFlag>
+			</plugin>
+			<plugin>
+				<file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+				<loadFlag>0</loadFlag>
+			</plugin>
+			<plugin>
+				<file>$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin</file>
+				<loadFlag>0</loadFlag>
+			</plugin>
+			<plugin>
+				<file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
+				<loadFlag>0</loadFlag>
+			</plugin>
+		</debuggerPlugins>
+	</configuration>
+</project>
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/ide/stm32h743.ewp b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/ide/stm32h743.ewp
new file mode 100644
index 00000000..4c3a9044
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/ide/stm32h743.ewp
@@ -0,0 +1,1317 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<project>
+    <fileVersion>3</fileVersion>
+    <configuration>
+        <name>stm32h743</name>
+        <toolchain>
+            <name>ARM</name>
+        </toolchain>
+        <debug>1</debug>
+        <settings>
+            <name>General</name>
+            <archiveVersion>3</archiveVersion>
+            <data>
+                <version>31</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>ExePath</name>
+                    <state>$PROJ_DIR$\..\bin</state>
+                </option>
+                <option>
+                    <name>ObjPath</name>
+                    <state>$PROJ_DIR$\..\obj</state>
+                </option>
+                <option>
+                    <name>ListPath</name>
+                    <state>$PROJ_DIR$\..\obj</state>
+                </option>
+                <option>
+                    <name>GEndianMode</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>Input description</name>
+                    <state>Full formatting, with multibyte support.</state>
+                </option>
+                <option>
+                    <name>Output description</name>
+                    <state>Full formatting, with multibyte support.</state>
+                </option>
+                <option>
+                    <name>GOutputBinary</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGCoreOrChip</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>GRuntimeLibSelect</name>
+                    <version>0</version>
+                    <state>2</state>
+                </option>
+                <option>
+                    <name>GRuntimeLibSelectSlave</name>
+                    <version>0</version>
+                    <state>2</state>
+                </option>
+                <option>
+                    <name>RTDescription</name>
+                    <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
+                </option>
+                <option>
+                    <name>OGProductVersion</name>
+                    <state>4.41A</state>
+                </option>
+                <option>
+                    <name>OGLastSavedByProductVersion</name>
+                    <state>8.50.4.26131</state>
+                </option>
+                <option>
+                    <name>GeneralEnableMisra</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GeneralMisraVerbose</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGChipSelectEditMenu</name>
+                    <state>STM32H743ZI	ST STM32H743ZI</state>
+                </option>
+                <option>
+                    <name>GenLowLevelInterface</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>GEndianModeBE</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OGBufferedTerminalOutput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenStdoutInterface</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GeneralMisraRules98</name>
+                    <version>0</version>
+                    <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+                </option>
+                <option>
+                    <name>GeneralMisraVer</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GeneralMisraRules04</name>
+                    <version>0</version>
+                    <state>011111111111111110111111111111011111111111111011110100111111111111111111111111111111111111111111101111111111111011111111111111111111111111111</state>
+                </option>
+                <option>
+                    <name>RTConfigPath2</name>
+                    <state>$TOOLKIT_DIR$\inc\c\DLib_Config_Full.h</state>
+                </option>
+                <option>
+                    <name>GBECoreSlave</name>
+                    <version>28</version>
+                    <state>41</state>
+                </option>
+                <option>
+                    <name>OGUseCmsis</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGUseCmsisDspLib</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GRuntimeLibThreads</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CoreVariant</name>
+                    <version>28</version>
+                    <state>41</state>
+                </option>
+                <option>
+                    <name>GFPUDeviceSlave</name>
+                    <state>STM32H743ZI	ST STM32H743ZI</state>
+                </option>
+                <option>
+                    <name>FPU2</name>
+                    <version>0</version>
+                    <state>7</state>
+                </option>
+                <option>
+                    <name>NrRegs</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>NEON</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GFPUCoreSlave2</name>
+                    <version>28</version>
+                    <state>41</state>
+                </option>
+                <option>
+                    <name>OGCMSISPackSelectDevice</name>
+                </option>
+                <option>
+                    <name>OgLibHeap</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGLibAdditionalLocale</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGPrintfVariant</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OGPrintfMultibyteSupport</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OGScanfVariant</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OGScanfMultibyteSupport</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>GenLocaleTags</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>GenLocaleDisplayOnly</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>DSPExtension</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>TrustZone</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>TrustZoneModes</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>ICCARM</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>36</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>CCOptimizationNoSizeConstraints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCDefines</name>
+                    <state>USE_HAL_DRIVER</state>
+                    <state>STM32H743xx</state>
+                </option>
+                <option>
+                    <name>CCPreprocFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPreprocComments</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPreprocLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListCFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListCMnemonics</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListCMessages</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListAssFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListAssSource</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCEnableRemarks</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCDiagSuppress</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCDiagRemark</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCDiagWarning</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCDiagError</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCObjPrefix</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCAllowList</name>
+                    <version>1</version>
+                    <state>00000000</state>
+                </option>
+                <option>
+                    <name>CCDebugInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IEndianMode</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IExtraOptionsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IExtraOptions</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCLangConformance</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSignedPlainChar</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCRequirePrototypes</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCDiagWarnAreErr</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCompilerRuntimeInfo</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IFpuProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OutputFile</name>
+                    <state>$FILE_BNAME$.o</state>
+                </option>
+                <option>
+                    <name>CCLibConfigHeader</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>PreInclude</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CompilerMisraOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCIncludePath2</name>
+                    <state>$PROJ_DIR$\..</state>
+                    <state>$PROJ_DIR$\..\lib</state>
+                    <state>$PROJ_DIR$\..\lib\CMSIS\Include</state>
+                    <state>$PROJ_DIR$\..\lib\CMSIS\Device\ST\STM32H7xx\Include</state>
+                    <state>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc</state>
+                    <state>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\Legacy</state>
+                </option>
+                <option>
+                    <name>CCStdIncCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCodeSection</name>
+                    <state>.text</state>
+                </option>
+                <option>
+                    <name>IProcessorMode2</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCOptLevel</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCOptStrategy</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCOptLevelSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CompilerMisraRules98</name>
+                    <version>0</version>
+                    <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+                </option>
+                <option>
+                    <name>CompilerMisraRules04</name>
+                    <version>0</version>
+                    <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+                </option>
+                <option>
+                    <name>CCPosIndRopi</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPosIndRwpi</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPosIndNoDynInit</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccLang</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccCDialect</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IccAllowVLA</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccStaticDestr</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccCppInlineSemantics</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccCmsis</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IccFloatSemantics</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCNoLiteralPool</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCOptStrategySlave</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCGuardCalls</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCEncSource</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCEncOutput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCEncOutputBom</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCEncInput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccExceptions2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccRTTI2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OICompilerExtraOption</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCStackProtection</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>AARM</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>10</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>AObjPrefix</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AEndian</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>ACaseSensitivity</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>MacroChars</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AWarnEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AWarnWhat</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AWarnOne</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AWarnRange1</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AWarnRange2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>ADebug</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AltRegisterNames</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>ADefines</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AList</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AListHeader</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AListing</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>Includes</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MacDefs</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MacExps</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>MacExec</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OnlyAssed</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MultiLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>PageLengthCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>PageLength</name>
+                    <state>80</state>
+                </option>
+                <option>
+                    <name>TabSpacing</name>
+                    <state>8</state>
+                </option>
+                <option>
+                    <name>AXRef</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AXRefDefines</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AXRefInternal</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AXRefDual</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AFpuProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AOutputFile</name>
+                    <state>$FILE_BNAME$.o</state>
+                </option>
+                <option>
+                    <name>ALimitErrorsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>ALimitErrorsEdit</name>
+                    <state>100</state>
+                </option>
+                <option>
+                    <name>AIgnoreStdInclude</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AUserIncludes</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AExtraOptionsCheckV2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AExtraOptionsV2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AsmNoLiteralPool</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>OBJCOPY</name>
+            <archiveVersion>0</archiveVersion>
+            <data>
+                <version>1</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OOCOutputFormat</name>
+                    <version>3</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCOutputOverride</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OOCOutputFile</name>
+                    <state>demoprog_stm32h743.srec</state>
+                </option>
+                <option>
+                    <name>OOCCommandLineProducer</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OOCObjCopyEnable</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>CUSTOM</name>
+            <archiveVersion>3</archiveVersion>
+            <data>
+                <extensions></extensions>
+                <cmdline></cmdline>
+                <hasPrio>0</hasPrio>
+            </data>
+        </settings>
+        <settings>
+            <name>BICOMP</name>
+            <archiveVersion>0</archiveVersion>
+            <data />
+        </settings>
+        <settings>
+            <name>BUILDACTION</name>
+            <archiveVersion>1</archiveVersion>
+            <data>
+                <prebuild></prebuild>
+                <postbuild></postbuild>
+            </data>
+        </settings>
+        <settings>
+            <name>ILINK</name>
+            <archiveVersion>0</archiveVersion>
+            <data>
+                <version>23</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>IlinkLibIOConfig</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>XLinkMisraHandler</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkInputFileSlave</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkOutputFile</name>
+                    <state>demoprog_stm32h743.out</state>
+                </option>
+                <option>
+                    <name>IlinkDebugInfoEnable</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkKeepSymbols</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySymbol</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySegment</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryAlign</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkDefines</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkConfigDefines</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkMapFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkLogFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogInitialization</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogModule</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogSection</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogVeneer</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIcfOverride</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkIcfFile</name>
+                    <state>$PROJ_DIR$\..\stm32h743xx_flash.icf</state>
+                </option>
+                <option>
+                    <name>IlinkIcfFileSlave</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkEnableRemarks</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkSuppressDiags</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkTreatAsRem</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkTreatAsWarn</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkTreatAsErr</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkWarningsAreErrors</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkUseExtraOptions</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkExtraOptions</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkLowLevelInterfaceSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkAutoLibEnable</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkAdditionalLibs</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkOverrideProgramEntryLabel</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkProgramEntryLabelSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkProgramEntryLabel</name>
+                    <state>__iar_program_start</state>
+                </option>
+                <option>
+                    <name>DoFill</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>FillerByte</name>
+                    <state>0xFF</state>
+                </option>
+                <option>
+                    <name>FillerStart</name>
+                    <state>0x0</state>
+                </option>
+                <option>
+                    <name>FillerEnd</name>
+                    <state>0x0</state>
+                </option>
+                <option>
+                    <name>CrcSize</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcAlign</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcPoly</name>
+                    <state>0x11021</state>
+                </option>
+                <option>
+                    <name>CrcCompl</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CrcBitOrder</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CrcInitialValue</name>
+                    <state>0x0</state>
+                </option>
+                <option>
+                    <name>DoCrc</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkBE8Slave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkBufferedTerminalOutput</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkStdoutInterfaceSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcFullSize</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIElfToolPostProcess</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogAutoLibSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogRedirSymbols</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogUnusedFragments</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCrcReverseByteOrder</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCrcUseAsInput</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptInline</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkOptExceptionsAllow</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptExceptionsForce</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCmsis</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptMergeDuplSections</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkOptUseVfe</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptForceVfe</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkStackAnalysisEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkStackControlFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkStackCallGraphFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CrcAlgorithm</name>
+                    <version>1</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcUnitSize</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkThreadsSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkLogCallGraph</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIcfFile_AltDefault</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkEncInput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkEncOutput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkEncOutputBom</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkHeapSelect</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkLocaleSelect</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkTrustzoneImportLibraryOut</name>
+                    <state>stm32h743_import_lib.o</state>
+                </option>
+                <option>
+                    <name>OILinkExtraOption</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryFile2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySymbol2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySegment2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryAlign2</name>
+                    <state></state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>IARCHIVE</name>
+            <archiveVersion>0</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>IarchiveInputs</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IarchiveOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IarchiveOutput</name>
+                    <state>###Unitialized###</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>BILINK</name>
+            <archiveVersion>0</archiveVersion>
+            <data />
+        </settings>
+    </configuration>
+    <group>
+        <name>Prog</name>
+        <group>
+            <name>lib</name>
+            <group>
+                <name>CMSIS</name>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\cmsis_armcc.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\cmsis_armclang.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\cmsis_compiler.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\cmsis_gcc.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\cmsis_iccarm.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\cmsis_version.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_armv8mbl.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_armv8mml.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_cm0.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_cm0plus.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_cm1.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_cm23.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_cm3.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_cm33.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_cm4.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_cm7.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_sc000.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_sc300.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\mpu_armv7.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\mpu_armv8.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Device\ST\STM32H7xx\Include\stm32h743xx.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Device\ST\STM32H7xx\Include\stm32h7xx.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Device\ST\STM32H7xx\Include\system_stm32h7xx.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\tz_context.h</name>
+                </file>
+            </group>
+            <group>
+                <name>HAL</name>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cortex.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_cortex.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_def.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dma.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma_ex.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dma_ex.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_exti.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_exti.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_fdcan.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_fdcan.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_flash.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash_ex.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_flash_ex.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_gpio.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_gpio.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_gpio_ex.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hsem.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_hsem.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_i2c.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c_ex.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_i2c_ex.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mdma.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_mdma.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pwr.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr_ex.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pwr_ex.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_rcc.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc_ex.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_rcc_ex.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_tim.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim_ex.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_tim_ex.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_uart.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_uart.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_uart_ex.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_uart_ex.h</name>
+                </file>
+            </group>
+            <file>
+                <name>$PROJ_DIR$\..\lib\stm32h7xx_hal_conf.h</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\..\lib\system_stm32h7xx.c</name>
+            </file>
+        </group>
+        <file>
+            <name>$PROJ_DIR$\..\boot.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\boot.h</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\header.h</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\led.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\led.h</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\main.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\startup_stm32h743xx.s</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\timer.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\timer.h</name>
+        </file>
+    </group>
+</project>
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/ide/stm32h743.ewt b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/ide/stm32h743.ewt
new file mode 100644
index 00000000..c298d29c
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/ide/stm32h743.ewt
@@ -0,0 +1,1675 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<project>
+    <fileVersion>3</fileVersion>
+    <configuration>
+        <name>stm32h743</name>
+        <toolchain>
+            <name>ARM</name>
+        </toolchain>
+        <debug>1</debug>
+        <settings>
+            <name>C-STAT</name>
+            <archiveVersion>264</archiveVersion>
+            <data>
+                <version>264</version>
+                <cstatargs>
+                    <useExtraArgs>0</useExtraArgs>
+                    <extraArgs></extraArgs>
+                    <analyzeTimeoutEnabled>1</analyzeTimeoutEnabled>
+                    <analyzeTimeout>600</analyzeTimeout>
+                    <enableParallel>1</enableParallel>
+                    <parallelThreads>2</parallelThreads>
+                    <enableFalsePositives>0</enableFalsePositives>
+                    <messagesLimitEnabled>1</messagesLimitEnabled>
+                    <messagesLimit>100</messagesLimit>
+                </cstatargs>
+                <cstat_settings>
+                    <cstat_version>1.8.1</cstat_version>
+                    <checks_tree>
+                        <package name="STDCHECKS" enabled="true">
+                            <group enabled="true" name="ARR">
+                                <check name="ARR-inv-index-pos" enabled="true" />
+                                <check name="ARR-inv-index-ptr-pos" enabled="true" />
+                                <check name="ARR-inv-index-ptr" enabled="true" />
+                                <check name="ARR-inv-index" enabled="true" />
+                                <check name="ARR-neg-index" enabled="true" />
+                                <check name="ARR-uninit-index" enabled="true" />
+                            </group>
+                            <group enabled="true" name="ATH">
+                                <check name="ATH-cmp-float" enabled="true" />
+                                <check name="ATH-cmp-unsign-neg" enabled="true" />
+                                <check name="ATH-cmp-unsign-pos" enabled="true" />
+                                <check name="ATH-div-0-assign" enabled="true" />
+                                <check name="ATH-div-0-cmp-aft" enabled="false" />
+                                <check name="ATH-div-0-cmp-bef" enabled="true" />
+                                <check name="ATH-div-0-interval" enabled="true" />
+                                <check name="ATH-div-0-pos" enabled="true" />
+                                <check name="ATH-div-0-unchk-global" enabled="true" />
+                                <check name="ATH-div-0-unchk-local" enabled="true" />
+                                <check name="ATH-div-0-unchk-param" enabled="true" />
+                                <check name="ATH-div-0" enabled="true" />
+                                <check name="ATH-inc-bool" enabled="true" />
+                                <check name="ATH-malloc-overrun" enabled="true" />
+                                <check name="ATH-neg-check-nonneg" enabled="true" />
+                                <check name="ATH-neg-check-pos" enabled="true" />
+                                <check name="ATH-new-overrun" enabled="true" />
+                                <check name="ATH-overflow-cast" enabled="false" />
+                                <check name="ATH-overflow" enabled="true" />
+                                <check name="ATH-shift-bounds" enabled="true" />
+                                <check name="ATH-shift-neg" enabled="true" />
+                                <check name="ATH-sizeof-by-sizeof" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CAST">
+                                <check name="CAST-old-style" enabled="false" />
+                            </group>
+                            <group enabled="true" name="CATCH">
+                                <check name="CATCH-object-slicing" enabled="true" />
+                                <check name="CATCH-xtor-bad-member" enabled="false" />
+                            </group>
+                            <group enabled="true" name="COMMA">
+                                <check name="COMMA-overload" enabled="false" />
+                            </group>
+                            <group enabled="true" name="COMMENT">
+                                <check name="COMMENT-nested" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CONST">
+                                <check name="CONST-member-ret" enabled="true" />
+                            </group>
+                            <group enabled="true" name="COP">
+                                <check name="COP-alloc-ctor" enabled="false" />
+                                <check name="COP-assign-op-ret" enabled="true" />
+                                <check name="COP-assign-op-self" enabled="true" />
+                                <check name="COP-assign-op" enabled="true" />
+                                <check name="COP-copy-ctor" enabled="true" />
+                                <check name="COP-dealloc-dtor" enabled="false" />
+                                <check name="COP-dtor-throw" enabled="true" />
+                                <check name="COP-dtor" enabled="true" />
+                                <check name="COP-init-order" enabled="false" />
+                                <check name="COP-init-uninit" enabled="true" />
+                                <check name="COP-member-uninit" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CPU">
+                                <check name="CPU-ctor-call-virt" enabled="true" />
+                                <check name="CPU-ctor-implicit" enabled="false" />
+                                <check name="CPU-delete-throw" enabled="true" />
+                                <check name="CPU-delete-void" enabled="true" />
+                                <check name="CPU-dtor-call-virt" enabled="true" />
+                                <check name="CPU-malloc-class" enabled="true" />
+                                <check name="CPU-nonvirt-dtor" enabled="true" />
+                                <check name="CPU-return-ref-to-class-data" enabled="true" />
+                            </group>
+                            <group enabled="true" name="DECL">
+                                <check name="DECL-implicit-int" enabled="false" />
+                            </group>
+                            <group enabled="true" name="DEFINE">
+                                <check name="DEFINE-hash-multiple" enabled="true" />
+                            </group>
+                            <group enabled="true" name="ENUM">
+                                <check name="ENUM-bounds" enabled="false" />
+                            </group>
+                            <group enabled="true" name="EXP">
+                                <check name="EXP-cond-assign" enabled="true" />
+                                <check name="EXP-dangling-else" enabled="true" />
+                                <check name="EXP-loop-exit" enabled="true" />
+                                <check name="EXP-main-ret-int" enabled="false" />
+                                <check name="EXP-null-stmt" enabled="false" />
+                                <check name="EXP-stray-semicolon" enabled="false" />
+                            </group>
+                            <group enabled="true" name="EXPR">
+                                <check name="EXPR-const-overflow" enabled="true" />
+                            </group>
+                            <group enabled="true" name="FPT">
+                                <check name="FPT-cmp-null" enabled="true" />
+                                <check name="FPT-literal" enabled="false" />
+                                <check name="FPT-misuse" enabled="true" />
+                            </group>
+                            <group enabled="true" name="FUNC">
+                                <check name="FUNC-implicit-decl" enabled="false" />
+                                <check name="FUNC-unprototyped-all" enabled="false" />
+                                <check name="FUNC-unprototyped-used" enabled="true" />
+                            </group>
+                            <group enabled="true" name="INCLUDE">
+                                <check name="INCLUDE-c-file" enabled="false" />
+                            </group>
+                            <group enabled="true" name="INT">
+                                <check name="INT-use-signed-as-unsigned-pos" enabled="false" />
+                                <check name="INT-use-signed-as-unsigned" enabled="true" />
+                            </group>
+                            <group enabled="true" name="ITR">
+                                <check name="ITR-end-cmp-aft" enabled="true" />
+                                <check name="ITR-end-cmp-bef" enabled="true" />
+                                <check name="ITR-invalidated" enabled="true" />
+                                <check name="ITR-mismatch-alg" enabled="false" />
+                                <check name="ITR-store" enabled="false" />
+                                <check name="ITR-uninit" enabled="true" />
+                            </group>
+                            <group enabled="true" name="LIB">
+                                <check name="LIB-bsearch-overrun-pos" enabled="false" />
+                                <check name="LIB-bsearch-overrun" enabled="false" />
+                                <check name="LIB-fn-unsafe" enabled="false" />
+                                <check name="LIB-fread-overrun-pos" enabled="false" />
+                                <check name="LIB-fread-overrun" enabled="true" />
+                                <check name="LIB-memchr-overrun-pos" enabled="false" />
+                                <check name="LIB-memchr-overrun" enabled="true" />
+                                <check name="LIB-memcpy-overrun-pos" enabled="false" />
+                                <check name="LIB-memcpy-overrun" enabled="true" />
+                                <check name="LIB-memset-overrun-pos" enabled="false" />
+                                <check name="LIB-memset-overrun" enabled="true" />
+                                <check name="LIB-putenv" enabled="false" />
+                                <check name="LIB-qsort-overrun-pos" enabled="false" />
+                                <check name="LIB-qsort-overrun" enabled="false" />
+                                <check name="LIB-return-const" enabled="true" />
+                                <check name="LIB-return-error" enabled="true" />
+                                <check name="LIB-return-leak" enabled="true" />
+                                <check name="LIB-return-neg" enabled="true" />
+                                <check name="LIB-return-null" enabled="true" />
+                                <check name="LIB-sprintf-overrun" enabled="false" />
+                                <check name="LIB-std-sort-overrun-pos" enabled="false" />
+                                <check name="LIB-std-sort-overrun" enabled="true" />
+                                <check name="LIB-strcat-overrun-pos" enabled="false" />
+                                <check name="LIB-strcat-overrun" enabled="true" />
+                                <check name="LIB-strcpy-overrun-pos" enabled="false" />
+                                <check name="LIB-strcpy-overrun" enabled="true" />
+                                <check name="LIB-strncat-overrun-pos" enabled="false" />
+                                <check name="LIB-strncat-overrun" enabled="true" />
+                                <check name="LIB-strncmp-overrun-pos" enabled="false" />
+                                <check name="LIB-strncmp-overrun" enabled="true" />
+                                <check name="LIB-strncpy-overrun-pos" enabled="false" />
+                                <check name="LIB-strncpy-overrun" enabled="true" />
+                            </group>
+                            <group enabled="true" name="LOGIC">
+                                <check name="LOGIC-overload" enabled="false" />
+                            </group>
+                            <group enabled="true" name="MEM">
+                                <check name="MEM-delete-array-op" enabled="true" />
+                                <check name="MEM-delete-op" enabled="true" />
+                                <check name="MEM-double-free-alias" enabled="true" />
+                                <check name="MEM-double-free-some" enabled="true" />
+                                <check name="MEM-double-free" enabled="true" />
+                                <check name="MEM-free-field" enabled="true" />
+                                <check name="MEM-free-fptr" enabled="true" />
+                                <check name="MEM-free-no-alloc-struct" enabled="false" />
+                                <check name="MEM-free-no-alloc" enabled="false" />
+                                <check name="MEM-free-no-use" enabled="true" />
+                                <check name="MEM-free-op" enabled="true" />
+                                <check name="MEM-free-struct-field" enabled="true" />
+                                <check name="MEM-free-variable-alias" enabled="true" />
+                                <check name="MEM-free-variable" enabled="true" />
+                                <check name="MEM-leak-alias" enabled="true" />
+                                <check name="MEM-leak" enabled="false" />
+                                <check name="MEM-malloc-arith" enabled="false" />
+                                <check name="MEM-malloc-diff-type" enabled="true" />
+                                <check name="MEM-malloc-sizeof-ptr" enabled="true" />
+                                <check name="MEM-malloc-sizeof" enabled="true" />
+                                <check name="MEM-malloc-strlen" enabled="false" />
+                                <check name="MEM-realloc-diff-type" enabled="true" />
+                                <check name="MEM-return-free" enabled="true" />
+                                <check name="MEM-return-no-assign" enabled="true" />
+                                <check name="MEM-stack-global-field" enabled="true" />
+                                <check name="MEM-stack-global" enabled="true" />
+                                <check name="MEM-stack-param-ref" enabled="true" />
+                                <check name="MEM-stack-param" enabled="true" />
+                                <check name="MEM-stack-pos" enabled="true" />
+                                <check name="MEM-stack-ref" enabled="true" />
+                                <check name="MEM-stack" enabled="true" />
+                                <check name="MEM-use-free-all" enabled="true" />
+                                <check name="MEM-use-free-some" enabled="true" />
+                            </group>
+                            <group enabled="true" name="PTR">
+                                <check name="PTR-arith-field" enabled="true" />
+                                <check name="PTR-arith-stack" enabled="true" />
+                                <check name="PTR-arith-var" enabled="true" />
+                                <check name="PTR-cmp-str-lit" enabled="true" />
+                                <check name="PTR-null-assign-fun-pos" enabled="false" />
+                                <check name="PTR-null-assign-pos" enabled="false" />
+                                <check name="PTR-null-assign" enabled="true" />
+                                <check name="PTR-null-cmp-aft" enabled="true" />
+                                <check name="PTR-null-cmp-bef-fun" enabled="true" />
+                                <check name="PTR-null-cmp-bef" enabled="true" />
+                                <check name="PTR-null-fun-pos" enabled="true" />
+                                <check name="PTR-null-literal-pos" enabled="false" />
+                                <check name="PTR-overload" enabled="false" />
+                                <check name="PTR-singleton-arith-pos" enabled="false" />
+                                <check name="PTR-singleton-arith" enabled="true" />
+                                <check name="PTR-unchk-param-some" enabled="true" />
+                                <check name="PTR-unchk-param" enabled="false" />
+                                <check name="PTR-uninit-pos" enabled="false" />
+                                <check name="PTR-uninit" enabled="true" />
+                            </group>
+                            <group enabled="true" name="RED">
+                                <check name="RED-alloc-zero-bytes" enabled="false" />
+                                <check name="RED-case-reach" enabled="false" />
+                                <check name="RED-cmp-always" enabled="false" />
+                                <check name="RED-cmp-never" enabled="false" />
+                                <check name="RED-cond-always" enabled="false" />
+                                <check name="RED-cond-const-assign" enabled="true" />
+                                <check name="RED-cond-const-expr" enabled="false" />
+                                <check name="RED-cond-const" enabled="false" />
+                                <check name="RED-cond-never" enabled="false" />
+                                <check name="RED-dead" enabled="true" />
+                                <check name="RED-expr" enabled="false" />
+                                <check name="RED-func-no-effect" enabled="false" />
+                                <check name="RED-local-hides-global" enabled="true" />
+                                <check name="RED-local-hides-local" enabled="false" />
+                                <check name="RED-local-hides-member" enabled="false" />
+                                <check name="RED-local-hides-param" enabled="true" />
+                                <check name="RED-no-effect" enabled="false" />
+                                <check name="RED-self-assign" enabled="true" />
+                                <check name="RED-unused-assign" enabled="true" />
+                                <check name="RED-unused-param" enabled="false" />
+                                <check name="RED-unused-return-val" enabled="false" />
+                                <check name="RED-unused-val" enabled="false" />
+                                <check name="RED-unused-var-all" enabled="true" />
+                            </group>
+                            <group enabled="true" name="RESOURCE">
+                                <check name="RESOURCE-deref-file" enabled="false" />
+                                <check name="RESOURCE-double-close" enabled="true" />
+                                <check name="RESOURCE-file-no-close-all" enabled="true" />
+                                <check name="RESOURCE-file-pos-neg" enabled="false" />
+                                <check name="RESOURCE-file-use-after-close" enabled="true" />
+                                <check name="RESOURCE-implicit-deref-file" enabled="false" />
+                                <check name="RESOURCE-write-ronly-file" enabled="true" />
+                            </group>
+                            <group enabled="true" name="SIZEOF">
+                                <check name="SIZEOF-side-effect" enabled="true" />
+                            </group>
+                            <group enabled="true" name="SPC">
+                                <check name="SPC-order" enabled="true" />
+                                <check name="SPC-uninit-arr-all" enabled="false" />
+                                <check name="SPC-uninit-struct-field-heap" enabled="true" />
+                                <check name="SPC-uninit-struct-field" enabled="false" />
+                                <check name="SPC-uninit-struct" enabled="true" />
+                                <check name="SPC-uninit-var-all" enabled="true" />
+                                <check name="SPC-uninit-var-some" enabled="true" />
+                                <check name="SPC-volatile-reads" enabled="false" />
+                                <check name="SPC-volatile-writes" enabled="false" />
+                            </group>
+                            <group enabled="true" name="STRUCT">
+                                <check name="STRUCT-signed-bit" enabled="false" />
+                            </group>
+                            <group enabled="true" name="SWITCH">
+                                <check name="SWITCH-fall-through" enabled="true" />
+                            </group>
+                            <group enabled="true" name="THROW">
+                                <check name="THROW-empty" enabled="false" />
+                                <check name="THROW-main" enabled="false" />
+                                <check name="THROW-null" enabled="true" />
+                                <check name="THROW-ptr" enabled="true" />
+                                <check name="THROW-static" enabled="true" />
+                                <check name="THROW-unhandled" enabled="true" />
+                            </group>
+                            <group enabled="true" name="UNION">
+                                <check name="UNION-overlap-assign" enabled="true" />
+                                <check name="UNION-type-punning" enabled="true" />
+                            </group>
+                        </package>
+                        <package name="CERT" enabled="false">
+                            <group enabled="true" name="CERT-ARR">
+                                <check name="CERT-ARR30-C_a" enabled="true" />
+                                <check name="CERT-ARR30-C_b" enabled="true" />
+                                <check name="CERT-ARR30-C_c" enabled="true" />
+                                <check name="CERT-ARR30-C_d" enabled="true" />
+                                <check name="CERT-ARR30-C_e" enabled="true" />
+                                <check name="CERT-ARR30-C_f" enabled="true" />
+                                <check name="CERT-ARR30-C_g" enabled="true" />
+                                <check name="CERT-ARR30-C_h" enabled="true" />
+                                <check name="CERT-ARR30-C_i" enabled="true" />
+                                <check name="CERT-ARR30-C_j" enabled="true" />
+                                <check name="CERT-ARR32-C" enabled="true" />
+                                <check name="CERT-ARR36-C_a" enabled="true" />
+                                <check name="CERT-ARR36-C_b" enabled="true" />
+                                <check name="CERT-ARR37-C" enabled="true" />
+                                <check name="CERT-ARR38-C_a" enabled="true" />
+                                <check name="CERT-ARR38-C_b" enabled="true" />
+                                <check name="CERT-ARR38-C_c" enabled="true" />
+                                <check name="CERT-ARR38-C_d" enabled="true" />
+                                <check name="CERT-ARR38-C_e" enabled="true" />
+                                <check name="CERT-ARR38-C_f" enabled="true" />
+                                <check name="CERT-ARR39-C" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-DCL">
+                                <check name="CERT-DCL30-C_a" enabled="true" />
+                                <check name="CERT-DCL30-C_b" enabled="true" />
+                                <check name="CERT-DCL30-C_c" enabled="true" />
+                                <check name="CERT-DCL30-C_d" enabled="true" />
+                                <check name="CERT-DCL30-C_e" enabled="true" />
+                                <check name="CERT-DCL31-C" enabled="true" />
+                                <check name="CERT-DCL36-C" enabled="true" />
+                                <check name="CERT-DCL37-C_a" enabled="true" />
+                                <check name="CERT-DCL37-C_b" enabled="true" />
+                                <check name="CERT-DCL37-C_c" enabled="false" />
+                                <check name="CERT-DCL38-C" enabled="true" />
+                                <check name="CERT-DCL39-C" enabled="true" />
+                                <check name="CERT-DCL40-C" enabled="true" />
+                                <check name="CERT-DCL41-C" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-ENV">
+                                <check name="CERT-ENV30-C" enabled="true" />
+                                <check name="CERT-ENV31-C" enabled="true" />
+                                <check name="CERT-ENV32-C" enabled="true" />
+                                <check name="CERT-ENV33-C" enabled="true" />
+                                <check name="CERT-ENV34-C" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-ERR">
+                                <check name="CERT-ERR30-C_a" enabled="true" />
+                                <check name="CERT-ERR30-C_b" enabled="true" />
+                                <check name="CERT-ERR30-C_c" enabled="true" />
+                                <check name="CERT-ERR30-C_d" enabled="true" />
+                                <check name="CERT-ERR32-C" enabled="true" />
+                                <check name="CERT-ERR33-C_a" enabled="true" />
+                                <check name="CERT-ERR33-C_b" enabled="true" />
+                                <check name="CERT-ERR33-C_c" enabled="true" />
+                                <check name="CERT-ERR33-C_d" enabled="true" />
+                                <check name="CERT-ERR34-C_a" enabled="true" />
+                                <check name="CERT-ERR34-C_b" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-EXP">
+                                <check name="CERT-EXP19-C" enabled="true" />
+                                <check name="CERT-EXP30-C_a" enabled="true" />
+                                <check name="CERT-EXP30-C_b" enabled="true" />
+                                <check name="CERT-EXP32-C" enabled="true" />
+                                <check name="CERT-EXP33-C_a" enabled="true" />
+                                <check name="CERT-EXP33-C_b" enabled="true" />
+                                <check name="CERT-EXP33-C_c" enabled="true" />
+                                <check name="CERT-EXP33-C_d" enabled="true" />
+                                <check name="CERT-EXP33-C_e" enabled="true" />
+                                <check name="CERT-EXP33-C_f" enabled="true" />
+                                <check name="CERT-EXP34-C_a" enabled="true" />
+                                <check name="CERT-EXP34-C_b" enabled="true" />
+                                <check name="CERT-EXP34-C_c" enabled="true" />
+                                <check name="CERT-EXP34-C_d" enabled="true" />
+                                <check name="CERT-EXP34-C_e" enabled="true" />
+                                <check name="CERT-EXP34-C_f" enabled="true" />
+                                <check name="CERT-EXP34-C_g" enabled="true" />
+                                <check name="CERT-EXP35-C" enabled="true" />
+                                <check name="CERT-EXP36-C_a" enabled="true" />
+                                <check name="CERT-EXP36-C_b" enabled="true" />
+                                <check name="CERT-EXP37-C_a" enabled="true" />
+                                <check name="CERT-EXP37-C_b" enabled="true" />
+                                <check name="CERT-EXP37-C_c" enabled="true" />
+                                <check name="CERT-EXP39-C_a" enabled="true" />
+                                <check name="CERT-EXP39-C_b" enabled="true" />
+                                <check name="CERT-EXP39-C_c" enabled="true" />
+                                <check name="CERT-EXP39-C_d" enabled="true" />
+                                <check name="CERT-EXP39-C_e" enabled="true" />
+                                <check name="CERT-EXP40-C_a" enabled="true" />
+                                <check name="CERT-EXP40-C_b" enabled="true" />
+                                <check name="CERT-EXP42-C" enabled="true" />
+                                <check name="CERT-EXP43-C_a" enabled="true" />
+                                <check name="CERT-EXP43-C_b" enabled="true" />
+                                <check name="CERT-EXP43-C_c" enabled="true" />
+                                <check name="CERT-EXP43-C_d" enabled="true" />
+                                <check name="CERT-EXP44-C" enabled="true" />
+                                <check name="CERT-EXP45-C" enabled="true" />
+                                <check name="CERT-EXP46-C" enabled="true" />
+                                <check name="CERT-EXP47-C_a" enabled="true" />
+                                <check name="CERT-EXP47-C_b" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-FIO">
+                                <check name="CERT-FIO30-C" enabled="true" />
+                                <check name="CERT-FIO32-C" enabled="true" />
+                                <check name="CERT-FIO34-C" enabled="true" />
+                                <check name="CERT-FIO37-C" enabled="true" />
+                                <check name="CERT-FIO38-C" enabled="true" />
+                                <check name="CERT-FIO39-C" enabled="true" />
+                                <check name="CERT-FIO40-C" enabled="true" />
+                                <check name="CERT-FIO41-C" enabled="true" />
+                                <check name="CERT-FIO42-C_a" enabled="true" />
+                                <check name="CERT-FIO42-C_b" enabled="false" />
+                                <check name="CERT-FIO44-C" enabled="true" />
+                                <check name="CERT-FIO45-C" enabled="true" />
+                                <check name="CERT-FIO46-C_a" enabled="true" />
+                                <check name="CERT-FIO46-C_b" enabled="true" />
+                                <check name="CERT-FIO46-C_c" enabled="true" />
+                                <check name="CERT-FIO47-C_a" enabled="true" />
+                                <check name="CERT-FIO47-C_b" enabled="true" />
+                                <check name="CERT-FIO47-C_c" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-FLP">
+                                <check name="CERT-FLP30-C_a" enabled="true" />
+                                <check name="CERT-FLP30-C_b" enabled="true" />
+                                <check name="CERT-FLP32-C_a" enabled="true" />
+                                <check name="CERT-FLP32-C_b" enabled="true" />
+                                <check name="CERT-FLP34-C" enabled="true" />
+                                <check name="CERT-FLP36-C" enabled="true" />
+                                <check name="CERT-FLP37-C" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-INT">
+                                <check name="CERT-INT30-C_a" enabled="true" />
+                                <check name="CERT-INT30-C_b" enabled="false" />
+                                <check name="CERT-INT31-C_a" enabled="true" />
+                                <check name="CERT-INT31-C_b" enabled="true" />
+                                <check name="CERT-INT31-C_c" enabled="true" />
+                                <check name="CERT-INT32-C_a" enabled="true" />
+                                <check name="CERT-INT32-C_b" enabled="false" />
+                                <check name="CERT-INT33-C_a" enabled="true" />
+                                <check name="CERT-INT33-C_b" enabled="true" />
+                                <check name="CERT-INT33-C_c" enabled="true" />
+                                <check name="CERT-INT33-C_d" enabled="true" />
+                                <check name="CERT-INT33-C_e" enabled="true" />
+                                <check name="CERT-INT33-C_f" enabled="true" />
+                                <check name="CERT-INT33-C_g" enabled="true" />
+                                <check name="CERT-INT33-C_h" enabled="true" />
+                                <check name="CERT-INT33-C_i" enabled="true" />
+                                <check name="CERT-INT34-C_a" enabled="true" />
+                                <check name="CERT-INT34-C_b" enabled="true" />
+                                <check name="CERT-INT34-C_c" enabled="true" />
+                                <check name="CERT-INT35-C" enabled="true" />
+                                <check name="CERT-INT36-C" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-MEM">
+                                <check name="CERT-MEM30-C_a" enabled="true" />
+                                <check name="CERT-MEM30-C_b" enabled="true" />
+                                <check name="CERT-MEM30-C_c" enabled="true" />
+                                <check name="CERT-MEM31-C" enabled="true" />
+                                <check name="CERT-MEM33-C_a" enabled="true" />
+                                <check name="CERT-MEM33-C_b" enabled="true" />
+                                <check name="CERT-MEM34-C_a" enabled="true" />
+                                <check name="CERT-MEM34-C_b" enabled="true" />
+                                <check name="CERT-MEM34-C_c" enabled="true" />
+                                <check name="CERT-MEM35-C_a" enabled="true" />
+                                <check name="CERT-MEM35-C_b" enabled="true" />
+                                <check name="CERT-MEM35-C_c" enabled="true" />
+                                <check name="CERT-MEM36-C" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-MSC">
+                                <check name="CERT-MSC30-C" enabled="true" />
+                                <check name="CERT-MSC32-C" enabled="true" />
+                                <check name="CERT-MSC33-C" enabled="false" />
+                                <check name="CERT-MSC37-C" enabled="true" />
+                                <check name="CERT-MSC38-C" enabled="true" />
+                                <check name="CERT-MSC39-C" enabled="true" />
+                                <check name="CERT-MSC40-C_a" enabled="true" />
+                                <check name="CERT-MSC40-C_b" enabled="true" />
+                                <check name="CERT-MSC40-C_c" enabled="true" />
+                                <check name="CERT-MSC40-C_d" enabled="true" />
+                                <check name="CERT-MSC40-C_e" enabled="false" />
+                                <check name="CERT-MSC41-C_a" enabled="true" />
+                                <check name="CERT-MSC41-C_b" enabled="true" />
+                                <check name="CERT-MSC41-C_c" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-PRE">
+                                <check name="CERT-PRE31-C" enabled="true" />
+                                <check name="CERT-PRE32-C_a" enabled="true" />
+                                <check name="CERT-PRE32-C_b" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-SIG">
+                                <check name="CERT-SIG30-C" enabled="true" />
+                                <check name="CERT-SIG31-C" enabled="true" />
+                                <check name="CERT-SIG34-C" enabled="true" />
+                                <check name="CERT-SIG35-C" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-STR">
+                                <check name="CERT-STR30-C" enabled="true" />
+                                <check name="CERT-STR31-C_a" enabled="true" />
+                                <check name="CERT-STR31-C_b" enabled="true" />
+                                <check name="CERT-STR31-C_c" enabled="true" />
+                                <check name="CERT-STR31-C_d" enabled="true" />
+                                <check name="CERT-STR31-C_e" enabled="true" />
+                                <check name="CERT-STR31-C_f" enabled="true" />
+                                <check name="CERT-STR31-C_g" enabled="true" />
+                                <check name="CERT-STR31-C_h" enabled="true" />
+                                <check name="CERT-STR32-C" enabled="true" />
+                                <check name="CERT-STR34-C" enabled="true" />
+                                <check name="CERT-STR37-C" enabled="true" />
+                            </group>
+                        </package>
+                        <package name="SECURITY" enabled="false">
+                            <group enabled="true" name="SEC-BUFFER">
+                                <check name="SEC-BUFFER-memory-leak-alias" enabled="true" />
+                                <check name="SEC-BUFFER-memory-leak" enabled="false" />
+                                <check name="SEC-BUFFER-memset-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-memset-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-qsort-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-qsort-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-sprintf-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-std-sort-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-std-sort-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-strcat-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-strcat-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-strcpy-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-strcpy-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-strncat-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-strncat-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-strncmp-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-strncmp-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-strncpy-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-strncpy-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-tainted-alloc-size" enabled="true" />
+                                <check name="SEC-BUFFER-tainted-copy-length" enabled="true" />
+                                <check name="SEC-BUFFER-tainted-copy" enabled="true" />
+                                <check name="SEC-BUFFER-tainted-index" enabled="true" />
+                                <check name="SEC-BUFFER-tainted-offset" enabled="true" />
+                                <check name="SEC-BUFFER-use-after-free-all" enabled="true" />
+                                <check name="SEC-BUFFER-use-after-free-some" enabled="true" />
+                            </group>
+                            <group enabled="true" name="SEC-DIV-0">
+                                <check name="SEC-DIV-0-compare-after" enabled="true" />
+                                <check name="SEC-DIV-0-compare-before" enabled="true" />
+                                <check name="SEC-DIV-0-tainted" enabled="true" />
+                            </group>
+                            <group enabled="true" name="SEC-FILEOP">
+                                <check name="SEC-FILEOP-open-no-close" enabled="true" />
+                                <check name="SEC-FILEOP-path-traversal" enabled="false" />
+                                <check name="SEC-FILEOP-use-after-close" enabled="true" />
+                            </group>
+                            <group enabled="true" name="SEC-INJECTION">
+                                <check name="SEC-INJECTION-sql" enabled="false" />
+                                <check name="SEC-INJECTION-xpath" enabled="false" />
+                            </group>
+                            <group enabled="true" name="SEC-LOOP">
+                                <check name="SEC-LOOP-tainted-bound" enabled="true" />
+                            </group>
+                            <group enabled="true" name="SEC-NULL">
+                                <check name="SEC-NULL-assignment-fun-pos" enabled="false" />
+                                <check name="SEC-NULL-assignment" enabled="true" />
+                                <check name="SEC-NULL-cmp-aft" enabled="true" />
+                                <check name="SEC-NULL-cmp-bef-fun" enabled="true" />
+                                <check name="SEC-NULL-cmp-bef" enabled="true" />
+                                <check name="SEC-NULL-literal-pos" enabled="false" />
+                            </group>
+                            <group enabled="true" name="SEC-STRING">
+                                <check name="SEC-STRING-format-string" enabled="true" />
+                                <check name="SEC-STRING-hard-coded-credentials" enabled="false" />
+                            </group>
+                        </package>
+                        <package name="MISRAC2004" enabled="false">
+                            <group enabled="true" name="MISRAC2004-1">
+                                <check name="MISRAC2004-1.1" enabled="true" />
+                                <check name="MISRAC2004-1.2_a" enabled="true" />
+                                <check name="MISRAC2004-1.2_b" enabled="true" />
+                                <check name="MISRAC2004-1.2_c" enabled="true" />
+                                <check name="MISRAC2004-1.2_d" enabled="true" />
+                                <check name="MISRAC2004-1.2_e" enabled="true" />
+                                <check name="MISRAC2004-1.2_f" enabled="true" />
+                                <check name="MISRAC2004-1.2_g" enabled="true" />
+                                <check name="MISRAC2004-1.2_h" enabled="true" />
+                                <check name="MISRAC2004-1.2_i" enabled="true" />
+                                <check name="MISRAC2004-1.2_j" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-2">
+                                <check name="MISRAC2004-2.1" enabled="true" />
+                                <check name="MISRAC2004-2.2" enabled="true" />
+                                <check name="MISRAC2004-2.3" enabled="true" />
+                                <check name="MISRAC2004-2.4" enabled="false" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-5">
+                                <check name="MISRAC2004-5.1" enabled="true" />
+                                <check name="MISRAC2004-5.2" enabled="true" />
+                                <check name="MISRAC2004-5.3" enabled="true" />
+                                <check name="MISRAC2004-5.4" enabled="true" />
+                                <check name="MISRAC2004-5.5" enabled="false" />
+                                <check name="MISRAC2004-5.6" enabled="false" />
+                                <check name="MISRAC2004-5.7" enabled="false" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-6">
+                                <check name="MISRAC2004-6.1" enabled="true" />
+                                <check name="MISRAC2004-6.2" enabled="true" />
+                                <check name="MISRAC2004-6.3" enabled="false" />
+                                <check name="MISRAC2004-6.4" enabled="true" />
+                                <check name="MISRAC2004-6.5" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-7">
+                                <check name="MISRAC2004-7.1" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-8">
+                                <check name="MISRAC2004-8.1" enabled="true" />
+                                <check name="MISRAC2004-8.2" enabled="true" />
+                                <check name="MISRAC2004-8.3" enabled="true" />
+                                <check name="MISRAC2004-8.5_a" enabled="true" />
+                                <check name="MISRAC2004-8.5_b" enabled="true" />
+                                <check name="MISRAC2004-8.6" enabled="true" />
+                                <check name="MISRAC2004-8.7" enabled="true" />
+                                <check name="MISRAC2004-8.8_a" enabled="true" />
+                                <check name="MISRAC2004-8.8_b" enabled="true" />
+                                <check name="MISRAC2004-8.10" enabled="true" />
+                                <check name="MISRAC2004-8.12" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-9">
+                                <check name="MISRAC2004-9.1_a" enabled="true" />
+                                <check name="MISRAC2004-9.1_b" enabled="true" />
+                                <check name="MISRAC2004-9.1_c" enabled="true" />
+                                <check name="MISRAC2004-9.2" enabled="true" />
+                                <check name="MISRAC2004-9.3" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-10">
+                                <check name="MISRAC2004-10.1_a" enabled="true" />
+                                <check name="MISRAC2004-10.1_b" enabled="true" />
+                                <check name="MISRAC2004-10.1_c" enabled="true" />
+                                <check name="MISRAC2004-10.1_d" enabled="true" />
+                                <check name="MISRAC2004-10.2_a" enabled="true" />
+                                <check name="MISRAC2004-10.2_b" enabled="true" />
+                                <check name="MISRAC2004-10.2_c" enabled="true" />
+                                <check name="MISRAC2004-10.2_d" enabled="true" />
+                                <check name="MISRAC2004-10.3" enabled="true" />
+                                <check name="MISRAC2004-10.4" enabled="true" />
+                                <check name="MISRAC2004-10.5" enabled="true" />
+                                <check name="MISRAC2004-10.6" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-11">
+                                <check name="MISRAC2004-11.1" enabled="true" />
+                                <check name="MISRAC2004-11.3" enabled="false" />
+                                <check name="MISRAC2004-11.4" enabled="false" />
+                                <check name="MISRAC2004-11.5" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-12">
+                                <check name="MISRAC2004-12.1" enabled="false" />
+                                <check name="MISRAC2004-12.2_a" enabled="true" />
+                                <check name="MISRAC2004-12.2_b" enabled="true" />
+                                <check name="MISRAC2004-12.2_c" enabled="true" />
+                                <check name="MISRAC2004-12.3" enabled="true" />
+                                <check name="MISRAC2004-12.4" enabled="true" />
+                                <check name="MISRAC2004-12.5" enabled="true" />
+                                <check name="MISRAC2004-12.6_a" enabled="false" />
+                                <check name="MISRAC2004-12.6_b" enabled="false" />
+                                <check name="MISRAC2004-12.7" enabled="true" />
+                                <check name="MISRAC2004-12.8" enabled="true" />
+                                <check name="MISRAC2004-12.9" enabled="true" />
+                                <check name="MISRAC2004-12.10" enabled="true" />
+                                <check name="MISRAC2004-12.11" enabled="false" />
+                                <check name="MISRAC2004-12.12_a" enabled="true" />
+                                <check name="MISRAC2004-12.12_b" enabled="true" />
+                                <check name="MISRAC2004-12.13" enabled="false" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-13">
+                                <check name="MISRAC2004-13.1" enabled="true" />
+                                <check name="MISRAC2004-13.2_a" enabled="false" />
+                                <check name="MISRAC2004-13.2_b" enabled="false" />
+                                <check name="MISRAC2004-13.2_c" enabled="false" />
+                                <check name="MISRAC2004-13.2_d" enabled="false" />
+                                <check name="MISRAC2004-13.2_e" enabled="false" />
+                                <check name="MISRAC2004-13.3" enabled="true" />
+                                <check name="MISRAC2004-13.4" enabled="true" />
+                                <check name="MISRAC2004-13.5" enabled="true" />
+                                <check name="MISRAC2004-13.6" enabled="true" />
+                                <check name="MISRAC2004-13.7_a" enabled="true" />
+                                <check name="MISRAC2004-13.7_b" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-14">
+                                <check name="MISRAC2004-14.1" enabled="true" />
+                                <check name="MISRAC2004-14.2" enabled="true" />
+                                <check name="MISRAC2004-14.3" enabled="true" />
+                                <check name="MISRAC2004-14.4" enabled="true" />
+                                <check name="MISRAC2004-14.5" enabled="true" />
+                                <check name="MISRAC2004-14.6" enabled="true" />
+                                <check name="MISRAC2004-14.7" enabled="true" />
+                                <check name="MISRAC2004-14.8_a" enabled="true" />
+                                <check name="MISRAC2004-14.8_b" enabled="true" />
+                                <check name="MISRAC2004-14.8_c" enabled="true" />
+                                <check name="MISRAC2004-14.8_d" enabled="true" />
+                                <check name="MISRAC2004-14.9" enabled="true" />
+                                <check name="MISRAC2004-14.10" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-15">
+                                <check name="MISRAC2004-15.0" enabled="true" />
+                                <check name="MISRAC2004-15.1" enabled="true" />
+                                <check name="MISRAC2004-15.2" enabled="true" />
+                                <check name="MISRAC2004-15.3" enabled="true" />
+                                <check name="MISRAC2004-15.4" enabled="true" />
+                                <check name="MISRAC2004-15.5" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-16">
+                                <check name="MISRAC2004-16.1" enabled="true" />
+                                <check name="MISRAC2004-16.2_a" enabled="true" />
+                                <check name="MISRAC2004-16.2_b" enabled="true" />
+                                <check name="MISRAC2004-16.3" enabled="true" />
+                                <check name="MISRAC2004-16.4" enabled="true" />
+                                <check name="MISRAC2004-16.5" enabled="true" />
+                                <check name="MISRAC2004-16.7" enabled="true" />
+                                <check name="MISRAC2004-16.8" enabled="true" />
+                                <check name="MISRAC2004-16.9" enabled="true" />
+                                <check name="MISRAC2004-16.10" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-17">
+                                <check name="MISRAC2004-17.1_a" enabled="true" />
+                                <check name="MISRAC2004-17.1_b" enabled="true" />
+                                <check name="MISRAC2004-17.1_c" enabled="true" />
+                                <check name="MISRAC2004-17.2" enabled="true" />
+                                <check name="MISRAC2004-17.3" enabled="true" />
+                                <check name="MISRAC2004-17.4_a" enabled="true" />
+                                <check name="MISRAC2004-17.4_b" enabled="true" />
+                                <check name="MISRAC2004-17.5" enabled="true" />
+                                <check name="MISRAC2004-17.6_a" enabled="true" />
+                                <check name="MISRAC2004-17.6_b" enabled="true" />
+                                <check name="MISRAC2004-17.6_c" enabled="true" />
+                                <check name="MISRAC2004-17.6_d" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-18">
+                                <check name="MISRAC2004-18.1" enabled="true" />
+                                <check name="MISRAC2004-18.2" enabled="true" />
+                                <check name="MISRAC2004-18.4" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-19">
+                                <check name="MISRAC2004-19.1" enabled="false" />
+                                <check name="MISRAC2004-19.2" enabled="false" />
+                                <check name="MISRAC2004-19.4" enabled="true" />
+                                <check name="MISRAC2004-19.5" enabled="true" />
+                                <check name="MISRAC2004-19.6" enabled="true" />
+                                <check name="MISRAC2004-19.7" enabled="false" />
+                                <check name="MISRAC2004-19.10" enabled="true" />
+                                <check name="MISRAC2004-19.12" enabled="true" />
+                                <check name="MISRAC2004-19.13" enabled="false" />
+                                <check name="MISRAC2004-19.15" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-20">
+                                <check name="MISRAC2004-20.1" enabled="true" />
+                                <check name="MISRAC2004-20.2" enabled="true" />
+                                <check name="MISRAC2004-20.3_a" enabled="true" />
+                                <check name="MISRAC2004-20.3_b" enabled="true" />
+                                <check name="MISRAC2004-20.3_c" enabled="true" />
+                                <check name="MISRAC2004-20.3_d" enabled="true" />
+                                <check name="MISRAC2004-20.3_e" enabled="true" />
+                                <check name="MISRAC2004-20.3_f" enabled="true" />
+                                <check name="MISRAC2004-20.3_g" enabled="true" />
+                                <check name="MISRAC2004-20.3_h" enabled="true" />
+                                <check name="MISRAC2004-20.3_i" enabled="true" />
+                                <check name="MISRAC2004-20.4" enabled="true" />
+                                <check name="MISRAC2004-20.5" enabled="true" />
+                                <check name="MISRAC2004-20.6" enabled="true" />
+                                <check name="MISRAC2004-20.7" enabled="true" />
+                                <check name="MISRAC2004-20.8" enabled="true" />
+                                <check name="MISRAC2004-20.9" enabled="true" />
+                                <check name="MISRAC2004-20.10" enabled="true" />
+                                <check name="MISRAC2004-20.11" enabled="true" />
+                                <check name="MISRAC2004-20.12" enabled="true" />
+                            </group>
+                        </package>
+                        <package name="MISRAC2012" enabled="false">
+                            <group enabled="true" name="MISRAC2012-Dir-4">
+                                <check name="MISRAC2012-Dir-4.3" enabled="true" />
+                                <check name="MISRAC2012-Dir-4.4" enabled="false" />
+                                <check name="MISRAC2012-Dir-4.5" enabled="false" />
+                                <check name="MISRAC2012-Dir-4.6_a" enabled="false" />
+                                <check name="MISRAC2012-Dir-4.6_b" enabled="false" />
+                                <check name="MISRAC2012-Dir-4.7_a" enabled="false" />
+                                <check name="MISRAC2012-Dir-4.7_b" enabled="false" />
+                                <check name="MISRAC2012-Dir-4.7_c" enabled="false" />
+                                <check name="MISRAC2012-Dir-4.8" enabled="false" />
+                                <check name="MISRAC2012-Dir-4.9" enabled="false" />
+                                <check name="MISRAC2012-Dir-4.10" enabled="true" />
+                                <check name="MISRAC2012-Dir-4.11_a" enabled="false" />
+                                <check name="MISRAC2012-Dir-4.11_b" enabled="false" />
+                                <check name="MISRAC2012-Dir-4.11_c" enabled="false" />
+                                <check name="MISRAC2012-Dir-4.11_d" enabled="false" />
+                                <check name="MISRAC2012-Dir-4.11_e" enabled="false" />
+                                <check name="MISRAC2012-Dir-4.11_f" enabled="false" />
+                                <check name="MISRAC2012-Dir-4.11_g" enabled="false" />
+                                <check name="MISRAC2012-Dir-4.11_h" enabled="false" />
+                                <check name="MISRAC2012-Dir-4.11_i" enabled="false" />
+                                <check name="MISRAC2012-Dir-4.12" enabled="false" />
+                                <check name="MISRAC2012-Dir-4.13_b" enabled="true" />
+                                <check name="MISRAC2012-Dir-4.13_c" enabled="true" />
+                                <check name="MISRAC2012-Dir-4.13_d" enabled="true" />
+                                <check name="MISRAC2012-Dir-4.13_e" enabled="true" />
+                                <check name="MISRAC2012-Dir-4.13_f" enabled="true" />
+                                <check name="MISRAC2012-Dir-4.13_g" enabled="true" />
+                                <check name="MISRAC2012-Dir-4.13_h" enabled="false" />
+                                <check name="MISRAC2012-Dir-4.14_a" enabled="true" />
+                                <check name="MISRAC2012-Dir-4.14_b" enabled="true" />
+                                <check name="MISRAC2012-Dir-4.14_c" enabled="true" />
+                                <check name="MISRAC2012-Dir-4.14_d" enabled="true" />
+                                <check name="MISRAC2012-Dir-4.14_e" enabled="true" />
+                                <check name="MISRAC2012-Dir-4.14_f" enabled="true" />
+                                <check name="MISRAC2012-Dir-4.14_g" enabled="true" />
+                                <check name="MISRAC2012-Dir-4.14_h" enabled="true" />
+                                <check name="MISRAC2012-Dir-4.14_i" enabled="true" />
+                                <check name="MISRAC2012-Dir-4.14_j" enabled="true" />
+                                <check name="MISRAC2012-Dir-4.14_l" enabled="true" />
+                                <check name="MISRAC2012-Dir-4.14_m" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2012-Rule-1">
+                                <check name="MISRAC2012-Rule-1.3_a" enabled="true" />
+                                <check name="MISRAC2012-Rule-1.3_b" enabled="true" />
+                                <check name="MISRAC2012-Rule-1.3_c" enabled="true" />
+                                <check name="MISRAC2012-Rule-1.3_d" enabled="true" />
+                                <check name="MISRAC2012-Rule-1.3_e" enabled="true" />
+                                <check name="MISRAC2012-Rule-1.3_f" enabled="true" />
+                                <check name="MISRAC2012-Rule-1.3_g" enabled="true" />
+                                <check name="MISRAC2012-Rule-1.3_h" enabled="true" />
+                                <check name="MISRAC2012-Rule-1.3_i" enabled="true" />
+                                <check name="MISRAC2012-Rule-1.3_j" enabled="true" />
+                                <check name="MISRAC2012-Rule-1.3_k" enabled="true" />
+                                <check name="MISRAC2012-Rule-1.3_m" enabled="true" />
+                                <check name="MISRAC2012-Rule-1.3_n" enabled="true" />
+                                <check name="MISRAC2012-Rule-1.3_o" enabled="true" />
+                                <check name="MISRAC2012-Rule-1.3_p" enabled="true" />
+                                <check name="MISRAC2012-Rule-1.3_q" enabled="true" />
+                                <check name="MISRAC2012-Rule-1.3_r" enabled="true" />
+                                <check name="MISRAC2012-Rule-1.3_s" enabled="true" />
+                                <check name="MISRAC2012-Rule-1.3_t" enabled="true" />
+                                <check name="MISRAC2012-Rule-1.3_u" enabled="true" />
+                                <check name="MISRAC2012-Rule-1.3_v" enabled="true" />
+                                <check name="MISRAC2012-Rule-1.3_w" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2012-Rule-2">
+                                <check name="MISRAC2012-Rule-2.1_a" enabled="true" />
+                                <check name="MISRAC2012-Rule-2.1_b" enabled="true" />
+                                <check name="MISRAC2012-Rule-2.2_a" enabled="true" />
+                                <check name="MISRAC2012-Rule-2.2_b" enabled="true" />
+                                <check name="MISRAC2012-Rule-2.2_c" enabled="true" />
+                                <check name="MISRAC2012-Rule-2.3" enabled="false" />
+                                <check name="MISRAC2012-Rule-2.4" enabled="false" />
+                                <check name="MISRAC2012-Rule-2.5" enabled="false" />
+                                <check name="MISRAC2012-Rule-2.6" enabled="false" />
+                                <check name="MISRAC2012-Rule-2.7" enabled="false" />
+                            </group>
+                            <group enabled="true" name="MISRAC2012-Rule-3">
+                                <check name="MISRAC2012-Rule-3.1" enabled="true" />
+                                <check name="MISRAC2012-Rule-3.2" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2012-Rule-5">
+                                <check name="MISRAC2012-Rule-5.1" enabled="true" />
+                                <check name="MISRAC2012-Rule-5.2_c89" enabled="true" />
+                                <check name="MISRAC2012-Rule-5.2_c99" enabled="true" />
+                                <check name="MISRAC2012-Rule-5.3_c89" enabled="true" />
+                                <check name="MISRAC2012-Rule-5.3_c99" enabled="true" />
+                                <check name="MISRAC2012-Rule-5.4_c89" enabled="true" />
+                                <check name="MISRAC2012-Rule-5.4_c99" enabled="true" />
+                                <check name="MISRAC2012-Rule-5.5_c89" enabled="true" />
+                                <check name="MISRAC2012-Rule-5.5_c99" enabled="true" />
+                                <check name="MISRAC2012-Rule-5.6" enabled="true" />
+                                <check name="MISRAC2012-Rule-5.7" enabled="true" />
+                                <check name="MISRAC2012-Rule-5.8" enabled="true" />
+                                <check name="MISRAC2012-Rule-5.9" enabled="false" />
+                            </group>
+                            <group enabled="true" name="MISRAC2012-Rule-6">
+                                <check name="MISRAC2012-Rule-6.1" enabled="true" />
+                                <check name="MISRAC2012-Rule-6.2" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2012-Rule-7">
+                                <check name="MISRAC2012-Rule-7.1" enabled="true" />
+                                <check name="MISRAC2012-Rule-7.2" enabled="true" />
+                                <check name="MISRAC2012-Rule-7.3" enabled="true" />
+                                <check name="MISRAC2012-Rule-7.4_a" enabled="true" />
+                                <check name="MISRAC2012-Rule-7.4_b" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2012-Rule-8">
+                                <check name="MISRAC2012-Rule-8.1" enabled="true" />
+                                <check name="MISRAC2012-Rule-8.2_a" enabled="true" />
+                                <check name="MISRAC2012-Rule-8.2_b" enabled="true" />
+                                <check name="MISRAC2012-Rule-8.3" enabled="true" />
+                                <check name="MISRAC2012-Rule-8.4" enabled="true" />
+                                <check name="MISRAC2012-Rule-8.5_a" enabled="true" />
+                                <check name="MISRAC2012-Rule-8.5_b" enabled="true" />
+                                <check name="MISRAC2012-Rule-8.7" enabled="false" />
+                                <check name="MISRAC2012-Rule-8.9_a" enabled="false" />
+                                <check name="MISRAC2012-Rule-8.9_b" enabled="false" />
+                                <check name="MISRAC2012-Rule-8.10" enabled="true" />
+                                <check name="MISRAC2012-Rule-8.11" enabled="false" />
+                                <check name="MISRAC2012-Rule-8.12" enabled="true" />
+                                <check name="MISRAC2012-Rule-8.13" enabled="false" />
+                                <check name="MISRAC2012-Rule-8.14" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2012-Rule-9">
+                                <check name="MISRAC2012-Rule-9.1_a" enabled="true" />
+                                <check name="MISRAC2012-Rule-9.1_b" enabled="true" />
+                                <check name="MISRAC2012-Rule-9.1_c" enabled="true" />
+                                <check name="MISRAC2012-Rule-9.1_d" enabled="true" />
+                                <check name="MISRAC2012-Rule-9.1_e" enabled="true" />
+                                <check name="MISRAC2012-Rule-9.1_f" enabled="true" />
+                                <check name="MISRAC2012-Rule-9.2" enabled="true" />
+                                <check name="MISRAC2012-Rule-9.3" enabled="true" />
+                                <check name="MISRAC2012-Rule-9.4" enabled="true" />
+                                <check name="MISRAC2012-Rule-9.5_a" enabled="true" />
+                                <check name="MISRAC2012-Rule-9.5_b" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2012-Rule-10">
+                                <check name="MISRAC2012-Rule-10.1_R2" enabled="true" />
+                                <check name="MISRAC2012-Rule-10.1_R3" enabled="true" />
+                                <check name="MISRAC2012-Rule-10.1_R4" enabled="true" />
+                                <check name="MISRAC2012-Rule-10.1_R5" enabled="true" />
+                                <check name="MISRAC2012-Rule-10.1_R6" enabled="true" />
+                                <check name="MISRAC2012-Rule-10.1_R7" enabled="true" />
+                                <check name="MISRAC2012-Rule-10.1_R8" enabled="true" />
+                                <check name="MISRAC2012-Rule-10.2" enabled="true" />
+                                <check name="MISRAC2012-Rule-10.3" enabled="true" />
+                                <check name="MISRAC2012-Rule-10.4_a" enabled="true" />
+                                <check name="MISRAC2012-Rule-10.4_b" enabled="true" />
+                                <check name="MISRAC2012-Rule-10.5" enabled="false" />
+                                <check name="MISRAC2012-Rule-10.6" enabled="true" />
+                                <check name="MISRAC2012-Rule-10.7" enabled="true" />
+                                <check name="MISRAC2012-Rule-10.8" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2012-Rule-11">
+                                <check name="MISRAC2012-Rule-11.1" enabled="true" />
+                                <check name="MISRAC2012-Rule-11.2" enabled="true" />
+                                <check name="MISRAC2012-Rule-11.3" enabled="true" />
+                                <check name="MISRAC2012-Rule-11.4" enabled="false" />
+                                <check name="MISRAC2012-Rule-11.5" enabled="false" />
+                                <check name="MISRAC2012-Rule-11.6" enabled="true" />
+                                <check name="MISRAC2012-Rule-11.7" enabled="true" />
+                                <check name="MISRAC2012-Rule-11.8" enabled="true" />
+                                <check name="MISRAC2012-Rule-11.9" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2012-Rule-12">
+                                <check name="MISRAC2012-Rule-12.1" enabled="false" />
+                                <check name="MISRAC2012-Rule-12.2" enabled="true" />
+                                <check name="MISRAC2012-Rule-12.3" enabled="false" />
+                                <check name="MISRAC2012-Rule-12.5" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2012-Rule-13">
+                                <check name="MISRAC2012-Rule-13.1" enabled="true" />
+                                <check name="MISRAC2012-Rule-13.2_a" enabled="true" />
+                                <check name="MISRAC2012-Rule-13.2_b" enabled="true" />
+                                <check name="MISRAC2012-Rule-13.2_c" enabled="true" />
+                                <check name="MISRAC2012-Rule-13.3" enabled="false" />
+                                <check name="MISRAC2012-Rule-13.4_a" enabled="false" />
+                                <check name="MISRAC2012-Rule-13.4_b" enabled="false" />
+                                <check name="MISRAC2012-Rule-13.5" enabled="true" />
+                                <check name="MISRAC2012-Rule-13.6" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2012-Rule-14">
+                                <check name="MISRAC2012-Rule-14.1_a" enabled="true" />
+                                <check name="MISRAC2012-Rule-14.1_b" enabled="true" />
+                                <check name="MISRAC2012-Rule-14.2" enabled="true" />
+                                <check name="MISRAC2012-Rule-14.3_a" enabled="true" />
+                                <check name="MISRAC2012-Rule-14.3_b" enabled="true" />
+                                <check name="MISRAC2012-Rule-14.4_a" enabled="true" />
+                                <check name="MISRAC2012-Rule-14.4_b" enabled="true" />
+                                <check name="MISRAC2012-Rule-14.4_c" enabled="true" />
+                                <check name="MISRAC2012-Rule-14.4_d" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2012-Rule-15">
+                                <check name="MISRAC2012-Rule-15.1" enabled="false" />
+                                <check name="MISRAC2012-Rule-15.2" enabled="true" />
+                                <check name="MISRAC2012-Rule-15.3" enabled="true" />
+                                <check name="MISRAC2012-Rule-15.4" enabled="false" />
+                                <check name="MISRAC2012-Rule-15.5" enabled="false" />
+                                <check name="MISRAC2012-Rule-15.6_a" enabled="true" />
+                                <check name="MISRAC2012-Rule-15.6_b" enabled="true" />
+                                <check name="MISRAC2012-Rule-15.6_c" enabled="true" />
+                                <check name="MISRAC2012-Rule-15.6_d" enabled="true" />
+                                <check name="MISRAC2012-Rule-15.6_e" enabled="true" />
+                                <check name="MISRAC2012-Rule-15.7" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2012-Rule-16">
+                                <check name="MISRAC2012-Rule-16.1" enabled="true" />
+                                <check name="MISRAC2012-Rule-16.2" enabled="true" />
+                                <check name="MISRAC2012-Rule-16.3" enabled="true" />
+                                <check name="MISRAC2012-Rule-16.4" enabled="true" />
+                                <check name="MISRAC2012-Rule-16.5" enabled="true" />
+                                <check name="MISRAC2012-Rule-16.6" enabled="true" />
+                                <check name="MISRAC2012-Rule-16.7" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2012-Rule-17">
+                                <check name="MISRAC2012-Rule-17.1" enabled="true" />
+                                <check name="MISRAC2012-Rule-17.2_a" enabled="true" />
+                                <check name="MISRAC2012-Rule-17.2_b" enabled="true" />
+                                <check name="MISRAC2012-Rule-17.3" enabled="true" />
+                                <check name="MISRAC2012-Rule-17.4" enabled="true" />
+                                <check name="MISRAC2012-Rule-17.5" enabled="false" />
+                                <check name="MISRAC2012-Rule-17.6" enabled="true" />
+                                <check name="MISRAC2012-Rule-17.7" enabled="true" />
+                                <check name="MISRAC2012-Rule-17.8" enabled="false" />
+                            </group>
+                            <group enabled="true" name="MISRAC2012-Rule-18">
+                                <check name="MISRAC2012-Rule-18.1_a" enabled="true" />
+                                <check name="MISRAC2012-Rule-18.1_b" enabled="true" />
+                                <check name="MISRAC2012-Rule-18.1_c" enabled="true" />
+                                <check name="MISRAC2012-Rule-18.1_d" enabled="true" />
+                                <check name="MISRAC2012-Rule-18.2" enabled="true" />
+                                <check name="MISRAC2012-Rule-18.3" enabled="true" />
+                                <check name="MISRAC2012-Rule-18.4" enabled="true" />
+                                <check name="MISRAC2012-Rule-18.5" enabled="false" />
+                                <check name="MISRAC2012-Rule-18.6_a" enabled="true" />
+                                <check name="MISRAC2012-Rule-18.6_b" enabled="true" />
+                                <check name="MISRAC2012-Rule-18.6_c" enabled="true" />
+                                <check name="MISRAC2012-Rule-18.6_d" enabled="true" />
+                                <check name="MISRAC2012-Rule-18.7" enabled="true" />
+                                <check name="MISRAC2012-Rule-18.8" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2012-Rule-19">
+                                <check name="MISRAC2012-Rule-19.1" enabled="true" />
+                                <check name="MISRAC2012-Rule-19.2" enabled="false" />
+                            </group>
+                            <group enabled="true" name="MISRAC2012-Rule-20">
+                                <check name="MISRAC2012-Rule-20.1" enabled="false" />
+                                <check name="MISRAC2012-Rule-20.2" enabled="true" />
+                                <check name="MISRAC2012-Rule-20.4_c89" enabled="true" />
+                                <check name="MISRAC2012-Rule-20.4_c99" enabled="true" />
+                                <check name="MISRAC2012-Rule-20.5" enabled="false" />
+                                <check name="MISRAC2012-Rule-20.6_a" enabled="true" />
+                                <check name="MISRAC2012-Rule-20.6_b" enabled="true" />
+                                <check name="MISRAC2012-Rule-20.7" enabled="true" />
+                                <check name="MISRAC2012-Rule-20.10" enabled="false" />
+                            </group>
+                            <group enabled="true" name="MISRAC2012-Rule-21">
+                                <check name="MISRAC2012-Rule-21.1" enabled="true" />
+                                <check name="MISRAC2012-Rule-21.2" enabled="true" />
+                                <check name="MISRAC2012-Rule-21.3" enabled="true" />
+                                <check name="MISRAC2012-Rule-21.4" enabled="true" />
+                                <check name="MISRAC2012-Rule-21.5" enabled="true" />
+                                <check name="MISRAC2012-Rule-21.6" enabled="true" />
+                                <check name="MISRAC2012-Rule-21.7" enabled="true" />
+                                <check name="MISRAC2012-Rule-21.8" enabled="true" />
+                                <check name="MISRAC2012-Rule-21.9" enabled="true" />
+                                <check name="MISRAC2012-Rule-21.10" enabled="true" />
+                                <check name="MISRAC2012-Rule-21.11" enabled="true" />
+                                <check name="MISRAC2012-Rule-21.12_a" enabled="false" />
+                                <check name="MISRAC2012-Rule-21.12_b" enabled="false" />
+                                <check name="MISRAC2012-Rule-21.13" enabled="true" />
+                                <check name="MISRAC2012-Rule-21.14" enabled="true" />
+                                <check name="MISRAC2012-Rule-21.15" enabled="true" />
+                                <check name="MISRAC2012-Rule-21.16" enabled="true" />
+                                <check name="MISRAC2012-Rule-21.17_a" enabled="true" />
+                                <check name="MISRAC2012-Rule-21.17_b" enabled="true" />
+                                <check name="MISRAC2012-Rule-21.17_c" enabled="true" />
+                                <check name="MISRAC2012-Rule-21.17_d" enabled="true" />
+                                <check name="MISRAC2012-Rule-21.17_e" enabled="true" />
+                                <check name="MISRAC2012-Rule-21.17_f" enabled="true" />
+                                <check name="MISRAC2012-Rule-21.18_a" enabled="true" />
+                                <check name="MISRAC2012-Rule-21.18_b" enabled="true" />
+                                <check name="MISRAC2012-Rule-21.19_a" enabled="true" />
+                                <check name="MISRAC2012-Rule-21.19_b" enabled="true" />
+                                <check name="MISRAC2012-Rule-21.20" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2012-Rule-22">
+                                <check name="MISRAC2012-Rule-22.1_a" enabled="true" />
+                                <check name="MISRAC2012-Rule-22.1_b" enabled="true" />
+                                <check name="MISRAC2012-Rule-22.2_a" enabled="true" />
+                                <check name="MISRAC2012-Rule-22.2_b" enabled="true" />
+                                <check name="MISRAC2012-Rule-22.2_c" enabled="true" />
+                                <check name="MISRAC2012-Rule-22.3" enabled="true" />
+                                <check name="MISRAC2012-Rule-22.4" enabled="true" />
+                                <check name="MISRAC2012-Rule-22.5_a" enabled="true" />
+                                <check name="MISRAC2012-Rule-22.5_b" enabled="true" />
+                                <check name="MISRAC2012-Rule-22.6" enabled="true" />
+                                <check name="MISRAC2012-Rule-22.7_a" enabled="true" />
+                                <check name="MISRAC2012-Rule-22.7_b" enabled="true" />
+                                <check name="MISRAC2012-Rule-22.8" enabled="true" />
+                                <check name="MISRAC2012-Rule-22.9" enabled="true" />
+                                <check name="MISRAC2012-Rule-22.10" enabled="true" />
+                            </group>
+                        </package>
+                        <package name="MISRAC++2008" enabled="false">
+                            <group enabled="true" name="MISRAC++2008-0-1">
+                                <check name="MISRAC++2008-0-1-1" enabled="true" />
+                                <check name="MISRAC++2008-0-1-2_a" enabled="true" />
+                                <check name="MISRAC++2008-0-1-2_b" enabled="true" />
+                                <check name="MISRAC++2008-0-1-2_c" enabled="true" />
+                                <check name="MISRAC++2008-0-1-3" enabled="true" />
+                                <check name="MISRAC++2008-0-1-4_a" enabled="true" />
+                                <check name="MISRAC++2008-0-1-4_b" enabled="true" />
+                                <check name="MISRAC++2008-0-1-6" enabled="true" />
+                                <check name="MISRAC++2008-0-1-7" enabled="true" />
+                                <check name="MISRAC++2008-0-1-8" enabled="false" />
+                                <check name="MISRAC++2008-0-1-9" enabled="true" />
+                                <check name="MISRAC++2008-0-1-11" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-0-2">
+                                <check name="MISRAC++2008-0-2-1" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-0-3">
+                                <check name="MISRAC++2008-0-3-2" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-2-7">
+                                <check name="MISRAC++2008-2-7-1" enabled="true" />
+                                <check name="MISRAC++2008-2-7-2" enabled="true" />
+                                <check name="MISRAC++2008-2-7-3" enabled="false" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-2-10">
+                                <check name="MISRAC++2008-2-10-1" enabled="true" />
+                                <check name="MISRAC++2008-2-10-2" enabled="true" />
+                                <check name="MISRAC++2008-2-10-3" enabled="true" />
+                                <check name="MISRAC++2008-2-10-4" enabled="true" />
+                                <check name="MISRAC++2008-2-10-5" enabled="false" />
+                                <check name="MISRAC++2008-2-10-6" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-2-13">
+                                <check name="MISRAC++2008-2-13-2" enabled="true" />
+                                <check name="MISRAC++2008-2-13-3" enabled="true" />
+                                <check name="MISRAC++2008-2-13-4_a" enabled="true" />
+                                <check name="MISRAC++2008-2-13-4_b" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-3-1">
+                                <check name="MISRAC++2008-3-1-1" enabled="true" />
+                                <check name="MISRAC++2008-3-1-3" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-3-9">
+                                <check name="MISRAC++2008-3-9-2" enabled="false" />
+                                <check name="MISRAC++2008-3-9-3" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-4-5">
+                                <check name="MISRAC++2008-4-5-1" enabled="true" />
+                                <check name="MISRAC++2008-4-5-2" enabled="true" />
+                                <check name="MISRAC++2008-4-5-3" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-5-0">
+                                <check name="MISRAC++2008-5-0-1_a" enabled="true" />
+                                <check name="MISRAC++2008-5-0-1_b" enabled="true" />
+                                <check name="MISRAC++2008-5-0-1_c" enabled="true" />
+                                <check name="MISRAC++2008-5-0-2" enabled="false" />
+                                <check name="MISRAC++2008-5-0-3" enabled="true" />
+                                <check name="MISRAC++2008-5-0-4" enabled="true" />
+                                <check name="MISRAC++2008-5-0-5" enabled="true" />
+                                <check name="MISRAC++2008-5-0-6" enabled="true" />
+                                <check name="MISRAC++2008-5-0-7" enabled="true" />
+                                <check name="MISRAC++2008-5-0-8" enabled="true" />
+                                <check name="MISRAC++2008-5-0-9" enabled="true" />
+                                <check name="MISRAC++2008-5-0-10" enabled="true" />
+                                <check name="MISRAC++2008-5-0-13_a" enabled="true" />
+                                <check name="MISRAC++2008-5-0-13_b" enabled="true" />
+                                <check name="MISRAC++2008-5-0-13_c" enabled="true" />
+                                <check name="MISRAC++2008-5-0-13_d" enabled="true" />
+                                <check name="MISRAC++2008-5-0-14" enabled="true" />
+                                <check name="MISRAC++2008-5-0-15_a" enabled="true" />
+                                <check name="MISRAC++2008-5-0-15_b" enabled="true" />
+                                <check name="MISRAC++2008-5-0-16_a" enabled="true" />
+                                <check name="MISRAC++2008-5-0-16_b" enabled="true" />
+                                <check name="MISRAC++2008-5-0-16_c" enabled="true" />
+                                <check name="MISRAC++2008-5-0-16_d" enabled="true" />
+                                <check name="MISRAC++2008-5-0-16_e" enabled="true" />
+                                <check name="MISRAC++2008-5-0-16_f" enabled="true" />
+                                <check name="MISRAC++2008-5-0-19" enabled="true" />
+                                <check name="MISRAC++2008-5-0-21" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-5-2">
+                                <check name="MISRAC++2008-5-2-4" enabled="true" />
+                                <check name="MISRAC++2008-5-2-5" enabled="true" />
+                                <check name="MISRAC++2008-5-2-6" enabled="true" />
+                                <check name="MISRAC++2008-5-2-7" enabled="true" />
+                                <check name="MISRAC++2008-5-2-9" enabled="false" />
+                                <check name="MISRAC++2008-5-2-10" enabled="false" />
+                                <check name="MISRAC++2008-5-2-11_a" enabled="true" />
+                                <check name="MISRAC++2008-5-2-11_b" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-5-3">
+                                <check name="MISRAC++2008-5-3-1" enabled="true" />
+                                <check name="MISRAC++2008-5-3-2_a" enabled="true" />
+                                <check name="MISRAC++2008-5-3-2_b" enabled="true" />
+                                <check name="MISRAC++2008-5-3-3" enabled="true" />
+                                <check name="MISRAC++2008-5-3-4" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-5-8">
+                                <check name="MISRAC++2008-5-8-1" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-5-14">
+                                <check name="MISRAC++2008-5-14-1" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-5-18">
+                                <check name="MISRAC++2008-5-18-1" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-5-19">
+                                <check name="MISRAC++2008-5-19-1" enabled="false" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-6-2">
+                                <check name="MISRAC++2008-6-2-1" enabled="true" />
+                                <check name="MISRAC++2008-6-2-2" enabled="true" />
+                                <check name="MISRAC++2008-6-2-3" enabled="false" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-6-3">
+                                <check name="MISRAC++2008-6-3-1_a" enabled="true" />
+                                <check name="MISRAC++2008-6-3-1_b" enabled="true" />
+                                <check name="MISRAC++2008-6-3-1_c" enabled="true" />
+                                <check name="MISRAC++2008-6-3-1_d" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-6-4">
+                                <check name="MISRAC++2008-6-4-1" enabled="true" />
+                                <check name="MISRAC++2008-6-4-2" enabled="true" />
+                                <check name="MISRAC++2008-6-4-3" enabled="true" />
+                                <check name="MISRAC++2008-6-4-4" enabled="true" />
+                                <check name="MISRAC++2008-6-4-5" enabled="true" />
+                                <check name="MISRAC++2008-6-4-6" enabled="true" />
+                                <check name="MISRAC++2008-6-4-7" enabled="true" />
+                                <check name="MISRAC++2008-6-4-8" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-6-5">
+                                <check name="MISRAC++2008-6-5-1_a" enabled="true" />
+                                <check name="MISRAC++2008-6-5-1_b" enabled="true" />
+                                <check name="MISRAC++2008-6-5-2" enabled="true" />
+                                <check name="MISRAC++2008-6-5-3" enabled="true" />
+                                <check name="MISRAC++2008-6-5-4" enabled="true" />
+                                <check name="MISRAC++2008-6-5-5" enabled="true" />
+                                <check name="MISRAC++2008-6-5-6" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-6-6">
+                                <check name="MISRAC++2008-6-6-1" enabled="true" />
+                                <check name="MISRAC++2008-6-6-2" enabled="true" />
+                                <check name="MISRAC++2008-6-6-4" enabled="true" />
+                                <check name="MISRAC++2008-6-6-5" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-7-1">
+                                <check name="MISRAC++2008-7-1-1" enabled="true" />
+                                <check name="MISRAC++2008-7-1-2" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-7-2">
+                                <check name="MISRAC++2008-7-2-1" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-7-4">
+                                <check name="MISRAC++2008-7-4-3" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-7-5">
+                                <check name="MISRAC++2008-7-5-1_a" enabled="true" />
+                                <check name="MISRAC++2008-7-5-1_b" enabled="true" />
+                                <check name="MISRAC++2008-7-5-2_a" enabled="true" />
+                                <check name="MISRAC++2008-7-5-2_b" enabled="true" />
+                                <check name="MISRAC++2008-7-5-2_c" enabled="true" />
+                                <check name="MISRAC++2008-7-5-2_d" enabled="true" />
+                                <check name="MISRAC++2008-7-5-4_a" enabled="false" />
+                                <check name="MISRAC++2008-7-5-4_b" enabled="false" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-8-0">
+                                <check name="MISRAC++2008-8-0-1" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-8-4">
+                                <check name="MISRAC++2008-8-4-1" enabled="true" />
+                                <check name="MISRAC++2008-8-4-3" enabled="true" />
+                                <check name="MISRAC++2008-8-4-4" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-8-5">
+                                <check name="MISRAC++2008-8-5-1_a" enabled="true" />
+                                <check name="MISRAC++2008-8-5-1_b" enabled="true" />
+                                <check name="MISRAC++2008-8-5-1_c" enabled="true" />
+                                <check name="MISRAC++2008-8-5-2" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-9-3">
+                                <check name="MISRAC++2008-9-3-1" enabled="true" />
+                                <check name="MISRAC++2008-9-3-2" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-9-5">
+                                <check name="MISRAC++2008-9-5-1" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-9-6">
+                                <check name="MISRAC++2008-9-6-2" enabled="true" />
+                                <check name="MISRAC++2008-9-6-3" enabled="true" />
+                                <check name="MISRAC++2008-9-6-4" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-12-1">
+                                <check name="MISRAC++2008-12-1-1_a" enabled="true" />
+                                <check name="MISRAC++2008-12-1-1_b" enabled="true" />
+                                <check name="MISRAC++2008-12-1-3" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-15-0">
+                                <check name="MISRAC++2008-15-0-2" enabled="false" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-15-1">
+                                <check name="MISRAC++2008-15-1-2" enabled="true" />
+                                <check name="MISRAC++2008-15-1-3" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-15-3">
+                                <check name="MISRAC++2008-15-3-1" enabled="true" />
+                                <check name="MISRAC++2008-15-3-2" enabled="false" />
+                                <check name="MISRAC++2008-15-3-3" enabled="true" />
+                                <check name="MISRAC++2008-15-3-4" enabled="true" />
+                                <check name="MISRAC++2008-15-3-5" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-15-5">
+                                <check name="MISRAC++2008-15-5-1" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-16-0">
+                                <check name="MISRAC++2008-16-0-3" enabled="true" />
+                                <check name="MISRAC++2008-16-0-4" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-16-2">
+                                <check name="MISRAC++2008-16-2-2" enabled="true" />
+                                <check name="MISRAC++2008-16-2-3" enabled="true" />
+                                <check name="MISRAC++2008-16-2-4" enabled="true" />
+                                <check name="MISRAC++2008-16-2-5" enabled="false" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-16-3">
+                                <check name="MISRAC++2008-16-3-1" enabled="true" />
+                                <check name="MISRAC++2008-16-3-2" enabled="false" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-17-0">
+                                <check name="MISRAC++2008-17-0-1" enabled="true" />
+                                <check name="MISRAC++2008-17-0-3" enabled="true" />
+                                <check name="MISRAC++2008-17-0-5" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-18-0">
+                                <check name="MISRAC++2008-18-0-1" enabled="true" />
+                                <check name="MISRAC++2008-18-0-2" enabled="true" />
+                                <check name="MISRAC++2008-18-0-3" enabled="true" />
+                                <check name="MISRAC++2008-18-0-4" enabled="true" />
+                                <check name="MISRAC++2008-18-0-5" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-18-2">
+                                <check name="MISRAC++2008-18-2-1" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-18-4">
+                                <check name="MISRAC++2008-18-4-1" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-18-7">
+                                <check name="MISRAC++2008-18-7-1" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-19-3">
+                                <check name="MISRAC++2008-19-3-1" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-27-0">
+                                <check name="MISRAC++2008-27-0-1" enabled="true" />
+                            </group>
+                        </package>
+                    </checks_tree>
+                </cstat_settings>
+            </data>
+        </settings>
+        <settings>
+            <name>RuntimeChecking</name>
+            <archiveVersion>0</archiveVersion>
+            <data>
+                <version>2</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>GenRtcDebugHeap</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcEnableBoundsChecking</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcCheckPtrsNonInstrMem</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>GenRtcTrackPointerBounds</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>GenRtcCheckAccesses</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>GenRtcGenerateEntries</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcNrTrackedPointers</name>
+                    <state>1000</state>
+                </option>
+                <option>
+                    <name>GenRtcIntOverflow</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcIncUnsigned</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcIntConversion</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcInclExplicit</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcIntShiftOverflow</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcInclUnsignedShiftOverflow</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcUnhandledCase</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcDivByZero</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcCheckPtrsNonInstrFunc</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+    </configuration>
+    <group>
+        <name>Prog</name>
+        <group>
+            <name>lib</name>
+            <group>
+                <name>CMSIS</name>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\cmsis_armcc.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\cmsis_armclang.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\cmsis_compiler.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\cmsis_gcc.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\cmsis_iccarm.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\cmsis_version.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_armv8mbl.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_armv8mml.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_cm0.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_cm0plus.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_cm1.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_cm23.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_cm3.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_cm33.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_cm4.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_cm7.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_sc000.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\core_sc300.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\mpu_armv7.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\mpu_armv8.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Device\ST\STM32H7xx\Include\stm32h743xx.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Device\ST\STM32H7xx\Include\stm32h7xx.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Device\ST\STM32H7xx\Include\system_stm32h7xx.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\CMSIS\Include\tz_context.h</name>
+                </file>
+            </group>
+            <group>
+                <name>HAL</name>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cortex.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_cortex.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_def.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dma.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma_ex.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dma_ex.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_exti.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_exti.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_fdcan.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_fdcan.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_flash.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash_ex.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_flash_ex.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_gpio.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_gpio.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_gpio_ex.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hsem.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_hsem.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_i2c.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c_ex.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_i2c_ex.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mdma.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_mdma.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pwr.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr_ex.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pwr_ex.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_rcc.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc_ex.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_rcc_ex.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_tim.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim_ex.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_tim_ex.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_uart.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_uart.h</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_uart_ex.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_uart_ex.h</name>
+                </file>
+            </group>
+            <file>
+                <name>$PROJ_DIR$\..\lib\stm32h7xx_hal_conf.h</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\..\lib\system_stm32h7xx.c</name>
+            </file>
+        </group>
+        <file>
+            <name>$PROJ_DIR$\..\boot.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\boot.h</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\header.h</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\led.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\led.h</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\main.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\startup_stm32h743xx.s</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\timer.c</name>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\..\timer.h</name>
+        </file>
+    </group>
+</project>
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/ide/stm32h743.eww b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/ide/stm32h743.eww
new file mode 100644
index 00000000..d3964b7d
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/ide/stm32h743.eww
@@ -0,0 +1,7 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<workspace>
+  <project>
+    <path>$WS_DIR$\stm32h743.ewp</path>
+  </project>
+  <batchBuild />
+</workspace>
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/led.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/led.c
new file mode 100644
index 00000000..451340dc
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/led.c
@@ -0,0 +1,94 @@
+/************************************************************************************//**
+* \file         Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/led.c
+* \brief        LED driver source file.
+* \ingroup      Prog_ARMCM7_STM32H7_Nucleo_H743ZI_IAR
+* \internal
+*----------------------------------------------------------------------------------------
+*                          C O P Y R I G H T
+*----------------------------------------------------------------------------------------
+*   Copyright (c) 2020  by Feaser    http://www.feaser.com    All rights reserved
+*
+*----------------------------------------------------------------------------------------
+*                            L I C E N S E
+*----------------------------------------------------------------------------------------
+* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as published by the Free
+* Software Foundation, either version 3 of the License, or (at your option) any later
+* version.
+*
+* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+* PURPOSE. See the GNU General Public License for more details.
+*
+* You have received a copy of the GNU General Public License along with OpenBLT. It
+* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
+*
+* \endinternal
+****************************************************************************************/
+
+/****************************************************************************************
+* Include files
+****************************************************************************************/
+#include "header.h"                                    /* generic header               */
+
+
+/****************************************************************************************
+* Macro definitions
+****************************************************************************************/
+/** \brief Toggle interval time in milliseconds. */
+#define LED_TOGGLE_MS  (500)
+
+
+/************************************************************************************//**
+** \brief     Initializes the LED. 
+** \return    none.
+**
+****************************************************************************************/
+void LedInit(void)
+{
+  /* Note that the initialization of the LED GPIO pin is done in HAL_MspInit(). All that
+   * is left to do here is to make sure the LED is turned off after initialization.
+   */
+  HAL_GPIO_WritePin(GPIOB, GPIO_PIN_7, GPIO_PIN_RESET);
+} /*** end of LedInit ***/
+
+
+/************************************************************************************//**
+** \brief     Toggles the LED at a fixed time interval.
+** \return    none.
+**
+****************************************************************************************/
+void LedToggle(void)
+{
+  static unsigned char led_toggle_state = 0;
+  static unsigned long timer_counter_last = 0;
+  unsigned long timer_counter_now;
+
+  /* check if toggle interval time passed */
+  timer_counter_now = TimerGet();
+  if ( (timer_counter_now - timer_counter_last) < LED_TOGGLE_MS)
+  {
+    /* not yet time to toggle */
+    return;
+  }
+
+  /* determine toggle action */
+  if (led_toggle_state == 0)
+  {
+    led_toggle_state = 1;
+    /* turn the LED on */
+    HAL_GPIO_WritePin(GPIOB, GPIO_PIN_7, GPIO_PIN_SET);
+  }
+  else
+  {
+    led_toggle_state = 0;
+    /* turn the LED off */
+    HAL_GPIO_WritePin(GPIOB, GPIO_PIN_7, GPIO_PIN_RESET);
+  }
+
+  /* store toggle time to determine next toggle interval */
+  timer_counter_last = timer_counter_now;
+} /*** end of LedToggle ***/
+
+
+/*********************************** end of led.c **************************************/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/led.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/led.h
new file mode 100644
index 00000000..863fbc5c
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/led.h
@@ -0,0 +1,39 @@
+/************************************************************************************//**
+* \file         Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/led.h
+* \brief        LED driver header file.
+* \ingroup      Prog_ARMCM7_STM32H7_Nucleo_H743ZI_IAR
+* \internal
+*----------------------------------------------------------------------------------------
+*                          C O P Y R I G H T
+*----------------------------------------------------------------------------------------
+*   Copyright (c) 2020  by Feaser    http://www.feaser.com    All rights reserved
+*
+*----------------------------------------------------------------------------------------
+*                            L I C E N S E
+*----------------------------------------------------------------------------------------
+* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as published by the Free
+* Software Foundation, either version 3 of the License, or (at your option) any later
+* version.
+*
+* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+* PURPOSE. See the GNU General Public License for more details.
+*
+* You have received a copy of the GNU General Public License along with OpenBLT. It
+* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
+*
+* \endinternal
+****************************************************************************************/
+#ifndef LED_H
+#define LED_H
+
+/****************************************************************************************
+* Function prototypes
+****************************************************************************************/
+void LedInit(void);
+void LedToggle(void);
+
+
+#endif /* LED_H */
+/*********************************** end of led.h **************************************/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h
new file mode 100644
index 00000000..cdcde7d9
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h
@@ -0,0 +1,26288 @@
+/**
+  ******************************************************************************
+  * @file    stm32h743xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32H743xx Device Peripheral Access Layer Header File.
+  *
+  *          This file contains:
+  *           - Data structures and the address mapping for all peripherals
+  *           - Peripheral's registers declarations and bits definition
+  *           - Macros to access peripheral's registers hardware
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS_Device
+  * @{
+  */
+
+/** @addtogroup stm32h743xx
+  * @{
+  */
+
+#ifndef STM32H743xx_H
+#define STM32H743xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+  * @{
+  */
+
+/**
+ * @brief STM32H7XX Interrupt Number Definition, according to the selected device
+ *        in @ref Library_configuration_section
+ */
+typedef enum
+{
+/******  Cortex-M Processor Exceptions Numbers *****************************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
+  HardFault_IRQn              = -13,    /*!< 4 Cortex-M Memory Management Interrupt                            */
+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M Memory Management Interrupt                            */
+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M Bus Fault Interrupt                                    */
+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M Usage Fault Interrupt                                  */
+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M SV Call Interrupt                                     */
+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M Debug Monitor Interrupt                               */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M Pend SV Interrupt                                     */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M System Tick Interrupt                                 */
+/******  STM32 specific Interrupt Numbers **********************************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it)                   */
+  PVD_AVD_IRQn                = 1,      /*!< PVD/AVD through EXTI Line detection Interrupt                     */
+  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
+  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
+  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
+  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
+  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
+  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
+  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
+  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
+  ADC_IRQn                    = 18,     /*!< ADC1 and  ADC2 global Interrupts                                  */
+  FDCAN1_IT0_IRQn             = 19,     /*!< FDCAN1 Interrupt line 0                                           */
+  FDCAN2_IT0_IRQn             = 20,     /*!< FDCAN2 Interrupt line 0                                           */
+  FDCAN1_IT1_IRQn             = 21,     /*!< FDCAN1 Interrupt line 1                                           */
+  FDCAN2_IT1_IRQn             = 22,     /*!< FDCAN2 Interrupt line 1                                           */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
+  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                              */
+  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                             */
+  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt                            */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
+  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
+  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
+  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
+  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
+  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
+  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */
+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
+  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
+  DMA2_Stream0_IRQn           = 56,     /*!<   DMA2 Stream 0 global Interrupt                                  */
+  DMA2_Stream1_IRQn           = 57,     /*!<   DMA2 Stream 1 global Interrupt                                  */
+  DMA2_Stream2_IRQn           = 58,     /*!<   DMA2 Stream 2 global Interrupt                                  */
+  DMA2_Stream3_IRQn           = 59,     /*!<   DMA2 Stream 3 global Interrupt                                  */
+  DMA2_Stream4_IRQn           = 60,     /*!<   DMA2 Stream 4 global Interrupt                                  */
+  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
+  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
+  FDCAN_CAL_IRQn              = 63,     /*!< FDCAN Calibration unit Interrupt                                  */
+  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
+  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
+  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
+  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
+  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
+  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
+  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
+  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
+  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
+  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
+  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
+  RNG_IRQn                    = 80,     /*!< RNG global interrupt                                              */
+  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
+  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */
+  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */
+  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
+  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */
+  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */
+  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */
+  LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                             */
+  LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                       */
+  DMA2D_IRQn                  = 90,     /*!< DMA2D global Interrupt                                            */
+  SAI2_IRQn                   = 91,     /*!< SAI2 global Interrupt                                             */
+  QUADSPI_IRQn                = 92,     /*!< Quad SPI global interrupt                                         */
+  LPTIM1_IRQn                 = 93,     /*!< LP TIM1 interrupt                                                 */
+  CEC_IRQn                    = 94,     /*!< HDMI-CEC global Interrupt                                         */
+  I2C4_EV_IRQn                = 95,     /*!< I2C4 Event Interrupt                                              */
+  I2C4_ER_IRQn                = 96,     /*!< I2C4 Error Interrupt                                              */
+  SPDIF_RX_IRQn               = 97,     /*!< SPDIF-RX global Interrupt                                         */
+  OTG_FS_EP1_OUT_IRQn         = 98,     /*!< USB OTG HS2 global interrupt                                      */
+  OTG_FS_EP1_IN_IRQn          = 99,     /*!< USB OTG HS2 End Point 1 Out global interrupt                      */
+  OTG_FS_WKUP_IRQn            = 100,    /*!< USB OTG HS2 End Point 1 In global interrupt                       */
+  OTG_FS_IRQn                 = 101,    /*!< USB OTG HS2 Wakeup through EXTI interrupt                         */
+  DMAMUX1_OVR_IRQn            = 102,    /*!<DMAMUX1 Overrun interrupt                                          */
+  HRTIM1_Master_IRQn          = 103,    /*!< HRTIM Master Timer global Interrupts                              */
+  HRTIM1_TIMA_IRQn            = 104,    /*!< HRTIM Timer A global Interrupt                                    */
+  HRTIM1_TIMB_IRQn            = 105,    /*!< HRTIM Timer B global Interrupt                                    */
+  HRTIM1_TIMC_IRQn            = 106,    /*!< HRTIM Timer C global Interrupt                                    */
+  HRTIM1_TIMD_IRQn            = 107,    /*!< HRTIM Timer D global Interrupt                                    */
+  HRTIM1_TIME_IRQn            = 108,    /*!< HRTIM Timer E global Interrupt                                    */
+  HRTIM1_FLT_IRQn             = 109,    /*!< HRTIM Fault global Interrupt                                      */
+  DFSDM1_FLT0_IRQn            = 110,    /*!<DFSDM Filter1 Interrupt                                            */
+  DFSDM1_FLT1_IRQn            = 111,    /*!<DFSDM Filter2 Interrupt                                            */
+  DFSDM1_FLT2_IRQn            = 112,    /*!<DFSDM Filter3 Interrupt                                            */
+  DFSDM1_FLT3_IRQn            = 113,    /*!<DFSDM Filter4 Interrupt                                            */
+  SAI3_IRQn                   = 114,    /*!< SAI3 global Interrupt                                             */
+  SWPMI1_IRQn                 = 115,    /*!< Serial Wire Interface 1 global interrupt                          */
+  TIM15_IRQn                  = 116,    /*!< TIM15 global Interrupt                                            */
+  TIM16_IRQn                  = 117,    /*!< TIM16 global Interrupt                                            */
+  TIM17_IRQn                  = 118,    /*!< TIM17 global Interrupt                                            */
+  MDIOS_WKUP_IRQn             = 119,    /*!< MDIOS Wakeup  Interrupt                                           */
+  MDIOS_IRQn                  = 120,    /*!< MDIOS global Interrupt                                            */
+  JPEG_IRQn                   = 121,    /*!< JPEG global Interrupt                                             */
+  MDMA_IRQn                   = 122,    /*!< MDMA global Interrupt                                             */
+  SDMMC2_IRQn                 = 124,    /*!< SDMMC2 global Interrupt                                           */
+  HSEM1_IRQn                  = 125,    /*!< HSEM1 global Interrupt                                            */
+  ADC3_IRQn                   = 127,    /*!< ADC3 global Interrupt                                             */
+  DMAMUX2_OVR_IRQn            = 128,    /*!<DMAMUX2 Overrun interrupt                                          */
+  BDMA_Channel0_IRQn          = 129,    /*!< BDMA Channel 0 global Interrupt                                   */
+  BDMA_Channel1_IRQn          = 130,    /*!< BDMA Channel 1 global Interrupt                                   */
+  BDMA_Channel2_IRQn          = 131,    /*!< BDMA Channel 2 global Interrupt                                   */
+  BDMA_Channel3_IRQn          = 132,    /*!< BDMA Channel 3 global Interrupt                                   */
+  BDMA_Channel4_IRQn          = 133,    /*!< BDMA Channel 4 global Interrupt                                   */
+  BDMA_Channel5_IRQn          = 134,    /*!< BDMA Channel 5 global Interrupt                                   */
+  BDMA_Channel6_IRQn          = 135,    /*!< BDMA Channel 6 global Interrupt                                   */
+  BDMA_Channel7_IRQn          = 136,    /*!< BDMA Channel 7 global Interrupt                                   */
+  COMP_IRQn                   = 137 ,   /*!< COMP global Interrupt                                             */
+  LPTIM2_IRQn                 = 138,    /*!< LP TIM2 global interrupt                                          */
+  LPTIM3_IRQn                 = 139,    /*!< LP TIM3 global interrupt                                          */
+  LPTIM4_IRQn                 = 140,    /*!< LP TIM4 global interrupt                                          */
+  LPTIM5_IRQn                 = 141,    /*!< LP TIM5 global interrupt                                          */
+  LPUART1_IRQn                = 142,    /*!< LP UART1 interrupt                                                */
+  CRS_IRQn                    = 144,    /*!< Clock Recovery Global Interrupt                                   */
+  ECC_IRQn                    = 145,    /*!< ECC diagnostic Global Interrupt                                   */
+  SAI4_IRQn                   = 146,    /*!< SAI4 global interrupt                                             */
+  WAKEUP_PIN_IRQn             = 149,    /*!< Interrupt for all 6 wake-up pins                                  */
+} IRQn_Type;
+
+/**
+  * @}
+  */
+
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+
+
+
+
+/**
+  * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
+   */
+#define __CM7_REV               0x0100U   /*!< Cortex-M7 revision r1p0                       */
+#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */
+#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */
+#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1       /*!< FPU present                                   */
+#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */
+#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */
+#include "core_cm7.h"                     /*!< Cortex-M7 processor and core peripherals      */
+
+/**
+  * @}
+  */
+
+
+
+
+#include "system_stm32h7xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+  * @{
+  */
+
+/**
+  * @brief Analog to Digital Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t ISR;              /*!< ADC Interrupt and Status Register,                          Address offset: 0x00 */
+  __IO uint32_t IER;              /*!< ADC Interrupt Enable Register,                              Address offset: 0x04 */
+  __IO uint32_t CR;               /*!< ADC control register,                                       Address offset: 0x08 */
+  __IO uint32_t CFGR;             /*!< ADC Configuration register,                                 Address offset: 0x0C */
+  __IO uint32_t CFGR2;            /*!< ADC Configuration register 2,                               Address offset: 0x10 */
+  __IO uint32_t SMPR1;            /*!< ADC sample time register 1,                                 Address offset: 0x14 */
+  __IO uint32_t SMPR2;            /*!< ADC sample time register 2,                                 Address offset: 0x18 */
+  __IO uint32_t PCSEL;            /*!< ADC pre-channel selection,                                  Address offset: 0x1C */
+  __IO uint32_t LTR1;             /*!< ADC watchdog Lower threshold register 1,                    Address offset: 0x20 */
+  __IO uint32_t HTR1;             /*!< ADC watchdog higher threshold register 1,                   Address offset: 0x24 */
+  uint32_t      RESERVED1;        /*!< Reserved, 0x028                                                                  */
+  uint32_t      RESERVED2;        /*!< Reserved, 0x02C                                                                  */
+  __IO uint32_t SQR1;             /*!< ADC regular sequence register 1,                            Address offset: 0x30 */
+  __IO uint32_t SQR2;             /*!< ADC regular sequence register 2,                            Address offset: 0x34 */
+  __IO uint32_t SQR3;             /*!< ADC regular sequence register 3,                            Address offset: 0x38 */
+  __IO uint32_t SQR4;             /*!< ADC regular sequence register 4,                            Address offset: 0x3C */
+  __IO uint32_t DR;               /*!< ADC regular data register,                                  Address offset: 0x40 */
+  uint32_t      RESERVED3;        /*!< Reserved, 0x044                                                                  */
+  uint32_t      RESERVED4;        /*!< Reserved, 0x048                                                                  */
+  __IO uint32_t JSQR;             /*!< ADC injected sequence register,                             Address offset: 0x4C */
+  uint32_t      RESERVED5[4];     /*!< Reserved, 0x050 - 0x05C                                                          */
+  __IO uint32_t OFR1;             /*!< ADC offset register 1,                                      Address offset: 0x60 */
+  __IO uint32_t OFR2;             /*!< ADC offset register 2,                                      Address offset: 0x64 */
+  __IO uint32_t OFR3;             /*!< ADC offset register 3,                                      Address offset: 0x68 */
+  __IO uint32_t OFR4;             /*!< ADC offset register 4,                                      Address offset: 0x6C */
+  uint32_t      RESERVED6[4];     /*!< Reserved, 0x070 - 0x07C                                                          */
+  __IO uint32_t JDR1;             /*!< ADC injected data register 1,                               Address offset: 0x80 */
+  __IO uint32_t JDR2;             /*!< ADC injected data register 2,                               Address offset: 0x84 */
+  __IO uint32_t JDR3;             /*!< ADC injected data register 3,                               Address offset: 0x88 */
+  __IO uint32_t JDR4;             /*!< ADC injected data register 4,                               Address offset: 0x8C */
+  uint32_t      RESERVED7[4];     /*!< Reserved, 0x090 - 0x09C                                                          */
+  __IO uint32_t AWD2CR;           /*!< ADC  Analog Watchdog 2 Configuration Register,              Address offset: 0xA0 */
+  __IO uint32_t AWD3CR;           /*!< ADC  Analog Watchdog 3 Configuration Register,              Address offset: 0xA4 */
+  uint32_t      RESERVED8;        /*!< Reserved, 0x0A8                                                                  */
+  uint32_t      RESERVED9;        /*!< Reserved, 0x0AC                                                                  */
+  __IO uint32_t LTR2;             /*!< ADC watchdog Lower threshold register 2,                    Address offset: 0xB0 */
+  __IO uint32_t HTR2;             /*!< ADC watchdog Higher threshold register 2,                   Address offset: 0xB4 */
+  __IO uint32_t LTR3;             /*!< ADC watchdog Lower threshold register 3,                    Address offset: 0xB8 */
+  __IO uint32_t HTR3;             /*!< ADC watchdog Higher threshold register 3,                   Address offset: 0xBC */
+  __IO uint32_t DIFSEL;           /*!< ADC  Differential Mode Selection Register,                  Address offset: 0xC0 */
+  __IO uint32_t CALFACT;          /*!< ADC  Calibration Factors,                                   Address offset: 0xC4 */
+  __IO uint32_t CALFACT2;         /*!< ADC  Linearity Calibration Factors,                         Address offset: 0xC8 */
+} ADC_TypeDef;
+
+
+typedef struct
+{
+__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
+uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
+__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
+__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */
+__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */
+
+} ADC_Common_TypeDef;
+
+
+/**
+  * @brief VREFBUF
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */
+  __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */
+} VREFBUF_TypeDef;
+
+
+/**
+  * @brief FD Controller Area Network
+  */
+
+typedef struct
+{
+  __IO uint32_t CREL;         /*!< FDCAN Core Release register,                                     Address offset: 0x000 */
+  __IO uint32_t ENDN;         /*!< FDCAN Endian register,                                           Address offset: 0x004 */
+  __IO uint32_t RESERVED1;    /*!< Reserved,                                                                        0x008 */
+  __IO uint32_t DBTP;         /*!< FDCAN Data Bit Timing & Prescaler register,                      Address offset: 0x00C */
+  __IO uint32_t TEST;         /*!< FDCAN Test register,                                             Address offset: 0x010 */
+  __IO uint32_t RWD;          /*!< FDCAN RAM Watchdog register,                                     Address offset: 0x014 */
+  __IO uint32_t CCCR;         /*!< FDCAN CC Control register,                                       Address offset: 0x018 */
+  __IO uint32_t NBTP;         /*!< FDCAN Nominal Bit Timing & Prescaler register,                   Address offset: 0x01C */
+  __IO uint32_t TSCC;         /*!< FDCAN Timestamp Counter Configuration register,                  Address offset: 0x020 */
+  __IO uint32_t TSCV;         /*!< FDCAN Timestamp Counter Value register,                          Address offset: 0x024 */
+  __IO uint32_t TOCC;         /*!< FDCAN Timeout Counter Configuration register,                    Address offset: 0x028 */
+  __IO uint32_t TOCV;         /*!< FDCAN Timeout Counter Value register,                            Address offset: 0x02C */
+  __IO uint32_t RESERVED2[4]; /*!< Reserved,                                                                0x030 - 0x03C */
+  __IO uint32_t ECR;          /*!< FDCAN Error Counter register,                                    Address offset: 0x040 */
+  __IO uint32_t PSR;          /*!< FDCAN Protocol Status register,                                  Address offset: 0x044 */
+  __IO uint32_t TDCR;         /*!< FDCAN Transmitter Delay Compensation register,                   Address offset: 0x048 */
+  __IO uint32_t RESERVED3;    /*!< Reserved,                                                                        0x04C */
+  __IO uint32_t IR;           /*!< FDCAN Interrupt register,                                        Address offset: 0x050 */
+  __IO uint32_t IE;           /*!< FDCAN Interrupt Enable register,                                 Address offset: 0x054 */
+  __IO uint32_t ILS;          /*!< FDCAN Interrupt Line Select register,                            Address offset: 0x058 */
+  __IO uint32_t ILE;          /*!< FDCAN Interrupt Line Enable register,                            Address offset: 0x05C */
+  __IO uint32_t RESERVED4[8]; /*!< Reserved,                                                                0x060 - 0x07C */
+  __IO uint32_t GFC;          /*!< FDCAN Global Filter Configuration register,                      Address offset: 0x080 */
+  __IO uint32_t SIDFC;        /*!< FDCAN Standard ID Filter Configuration register,                 Address offset: 0x084 */
+  __IO uint32_t XIDFC;        /*!< FDCAN Extended ID Filter Configuration register,                 Address offset: 0x088 */
+  __IO uint32_t RESERVED5;    /*!< Reserved,                                                                        0x08C */
+  __IO uint32_t XIDAM;        /*!< FDCAN Extended ID AND Mask register,                             Address offset: 0x090 */
+  __IO uint32_t HPMS;         /*!< FDCAN High Priority Message Status register,                     Address offset: 0x094 */
+  __IO uint32_t NDAT1;        /*!< FDCAN New Data 1 register,                                       Address offset: 0x098 */
+  __IO uint32_t NDAT2;        /*!< FDCAN New Data 2 register,                                       Address offset: 0x09C */
+  __IO uint32_t RXF0C;        /*!< FDCAN Rx FIFO 0 Configuration register,                          Address offset: 0x0A0 */
+  __IO uint32_t RXF0S;        /*!< FDCAN Rx FIFO 0 Status register,                                 Address offset: 0x0A4 */
+  __IO uint32_t RXF0A;        /*!< FDCAN Rx FIFO 0 Acknowledge register,                            Address offset: 0x0A8 */
+  __IO uint32_t RXBC;         /*!< FDCAN Rx Buffer Configuration register,                          Address offset: 0x0AC */
+  __IO uint32_t RXF1C;        /*!< FDCAN Rx FIFO 1 Configuration register,                          Address offset: 0x0B0 */
+  __IO uint32_t RXF1S;        /*!< FDCAN Rx FIFO 1 Status register,                                 Address offset: 0x0B4 */
+  __IO uint32_t RXF1A;        /*!< FDCAN Rx FIFO 1 Acknowledge register,                            Address offset: 0x0B8 */
+  __IO uint32_t RXESC;        /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register,        Address offset: 0x0BC */
+  __IO uint32_t TXBC;         /*!< FDCAN Tx Buffer Configuration register,                          Address offset: 0x0C0 */
+  __IO uint32_t TXFQS;        /*!< FDCAN Tx FIFO/Queue Status register,                             Address offset: 0x0C4 */
+  __IO uint32_t TXESC;        /*!< FDCAN Tx Buffer Element Size Configuration register,             Address offset: 0x0C8 */
+  __IO uint32_t TXBRP;        /*!< FDCAN Tx Buffer Request Pending register,                        Address offset: 0x0CC */
+  __IO uint32_t TXBAR;        /*!< FDCAN Tx Buffer Add Request register,                            Address offset: 0x0D0 */
+  __IO uint32_t TXBCR;        /*!< FDCAN Tx Buffer Cancellation Request register,                   Address offset: 0x0D4 */
+  __IO uint32_t TXBTO;        /*!< FDCAN Tx Buffer Transmission Occurred register,                  Address offset: 0x0D8 */
+  __IO uint32_t TXBCF;        /*!< FDCAN Tx Buffer Cancellation Finished register,                  Address offset: 0x0DC */
+  __IO uint32_t TXBTIE;       /*!< FDCAN Tx Buffer Transmission Interrupt Enable register,          Address offset: 0x0E0 */
+  __IO uint32_t TXBCIE;       /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */
+  __IO uint32_t RESERVED6[2]; /*!< Reserved,                                                                0x0E8 - 0x0EC */
+  __IO uint32_t TXEFC;        /*!< FDCAN Tx Event FIFO Configuration register,                      Address offset: 0x0F0 */
+  __IO uint32_t TXEFS;        /*!< FDCAN Tx Event FIFO Status register,                             Address offset: 0x0F4 */
+  __IO uint32_t TXEFA;        /*!< FDCAN Tx Event FIFO Acknowledge register,                        Address offset: 0x0F8 */
+  __IO uint32_t RESERVED7;    /*!< Reserved,                                                                        0x0FC */
+} FDCAN_GlobalTypeDef;
+
+/**
+  * @brief TTFD Controller Area Network
+  */
+
+typedef struct
+{
+  __IO uint32_t TTTMC;          /*!< TT Trigger Memory Configuration register,    Address offset: 0x100 */
+  __IO uint32_t TTRMC;          /*!< TT Reference Message Configuration register, Address offset: 0x104 */
+  __IO uint32_t TTOCF;          /*!< TT Operation Configuration register,         Address offset: 0x108 */
+  __IO uint32_t TTMLM;          /*!< TT Matrix Limits register,                   Address offset: 0x10C */
+  __IO uint32_t TURCF;          /*!< TUR Configuration register,                  Address offset: 0x110 */
+  __IO uint32_t TTOCN;          /*!< TT Operation Control register,               Address offset: 0x114 */
+  __IO uint32_t TTGTP;          /*!< TT Global Time Preset register,              Address offset: 0x118 */
+  __IO uint32_t TTTMK;          /*!< TT Time Mark register,                       Address offset: 0x11C */
+  __IO uint32_t TTIR;           /*!< TT Interrupt register,                       Address offset: 0x120 */
+  __IO uint32_t TTIE;           /*!< TT Interrupt Enable register,                Address offset: 0x124 */
+  __IO uint32_t TTILS;          /*!< TT Interrupt Line Select register,           Address offset: 0x128 */
+  __IO uint32_t TTOST;          /*!< TT Operation Status register,                Address offset: 0x12C */
+  __IO uint32_t TURNA;          /*!< TT TUR Numerator Actual register,            Address offset: 0x130 */
+  __IO uint32_t TTLGT;          /*!< TT Local and Global Time register,           Address offset: 0x134 */
+  __IO uint32_t TTCTC;          /*!< TT Cycle Time and Count register,            Address offset: 0x138 */
+  __IO uint32_t TTCPT;          /*!< TT Capture Time register,                    Address offset: 0x13C */
+  __IO uint32_t TTCSM;          /*!< TT Cycle Sync Mark register,                 Address offset: 0x140 */
+  __IO uint32_t RESERVED1[111]; /*!< Reserved,                                            0x144 - 0x2FC */
+  __IO uint32_t TTTS;           /*!< TT Trigger Select register,                  Address offset: 0x300 */
+} TTCAN_TypeDef;
+
+/**
+  * @brief FD Controller Area Network
+  */
+
+typedef struct
+{
+  __IO uint32_t CREL;  /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */
+  __IO uint32_t CCFG;  /*!< Calibration Configuration register,           Address offset: 0x04 */
+  __IO uint32_t CSTAT; /*!< Calibration Status register,                  Address offset: 0x08 */
+  __IO uint32_t CWD;   /*!< Calibration Watchdog register,                Address offset: 0x0C */
+  __IO uint32_t IR;    /*!< CCU Interrupt register,                       Address offset: 0x10 */
+  __IO uint32_t IE;    /*!< CCU Interrupt Enable register,                Address offset: 0x14 */
+} FDCAN_ClockCalibrationUnit_TypeDef;
+
+
+/**
+  * @brief Consumer Electronics Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;           /*!< CEC control register,              Address offset:0x00 */
+  __IO uint32_t CFGR;         /*!< CEC configuration register,        Address offset:0x04 */
+  __IO uint32_t TXDR;         /*!< CEC Tx data register ,             Address offset:0x08 */
+  __IO uint32_t RXDR;         /*!< CEC Rx Data Register,              Address offset:0x0C */
+  __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register, Address offset:0x10 */
+  __IO uint32_t IER;          /*!< CEC interrupt enable register,     Address offset:0x14 */
+}CEC_TypeDef;
+
+/**
+  * @brief CRC calculation unit
+  */
+
+typedef struct
+{
+  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
+  __IO uint32_t IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
+  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
+  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */
+  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
+  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
+} CRC_TypeDef;
+
+
+/**
+  * @brief Clock Recovery System
+  */
+typedef struct
+{
+__IO uint32_t CR;            /*!< CRS ccontrol register,              Address offset: 0x00 */
+__IO uint32_t CFGR;          /*!< CRS configuration register,         Address offset: 0x04 */
+__IO uint32_t ISR;           /*!< CRS interrupt and status register,  Address offset: 0x08 */
+__IO uint32_t ICR;           /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
+} CRS_TypeDef;
+
+
+/**
+  * @brief Digital to Analog Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
+  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
+  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
+  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
+  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
+  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
+  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
+  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
+  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
+  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
+  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
+  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
+  __IO uint32_t CCR;      /*!< DAC calibration control register,                        Address offset: 0x38 */
+  __IO uint32_t MCR;      /*!< DAC mode control register,                               Address offset: 0x3C */
+  __IO uint32_t SHSR1;    /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */
+  __IO uint32_t SHSR2;    /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */
+  __IO uint32_t SHHR;     /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */
+  __IO uint32_t SHRR;     /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */
+} DAC_TypeDef;
+
+/**
+  * @brief DFSDM module registers
+  */
+typedef struct
+{
+  __IO uint32_t FLTCR1;          /*!< DFSDM control register1,                          Address offset: 0x100 */
+  __IO uint32_t FLTCR2;          /*!< DFSDM control register2,                          Address offset: 0x104 */
+  __IO uint32_t FLTISR;          /*!< DFSDM interrupt and status register,              Address offset: 0x108 */
+  __IO uint32_t FLTICR;          /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */
+  __IO uint32_t FLTJCHGR;        /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */
+  __IO uint32_t FLTFCR;          /*!< DFSDM filter control register,                    Address offset: 0x114 */
+  __IO uint32_t FLTJDATAR;       /*!< DFSDM data register for injected group,           Address offset: 0x118 */
+  __IO uint32_t FLTRDATAR;       /*!< DFSDM data register for regular group,            Address offset: 0x11C */
+  __IO uint32_t FLTAWHTR;        /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */
+  __IO uint32_t FLTAWLTR;        /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */
+  __IO uint32_t FLTAWSR;         /*!< DFSDM analog watchdog status register             Address offset: 0x128 */
+  __IO uint32_t FLTAWCFR;        /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */
+  __IO uint32_t FLTEXMAX;        /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */
+  __IO uint32_t FLTEXMIN;        /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */
+  __IO uint32_t FLTCNVTIMR;      /*!< DFSDM conversion timer,                           Address offset: 0x138 */
+} DFSDM_Filter_TypeDef;
+
+/**
+  * @brief DFSDM channel configuration registers
+  */
+typedef struct
+{
+  __IO uint32_t CHCFGR1;      /*!< DFSDM channel configuration register1,            Address offset: 0x00 */
+  __IO uint32_t CHCFGR2;      /*!< DFSDM channel configuration register2,            Address offset: 0x04 */
+  __IO uint32_t CHAWSCDR;     /*!< DFSDM channel analog watchdog and
+                                   short circuit detector register,                  Address offset: 0x08 */
+  __IO uint32_t CHWDATAR;     /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */
+  __IO uint32_t CHDATINR;     /*!< DFSDM channel data input register,                Address offset: 0x10 */
+} DFSDM_Channel_TypeDef;
+
+/**
+  * @brief Debug MCU
+  */
+typedef struct
+{
+  __IO uint32_t IDCODE;        /*!< MCU device ID code,                     Address offset: 0x00 */
+  __IO uint32_t CR;            /*!< Debug MCU configuration register,       Address offset: 0x04 */
+  uint32_t RESERVED4[11];      /*!< Reserved,                             Address offset: 0x08 */
+  __IO uint32_t APB3FZ1;     /*!< Debug MCU APB3FZ1 freeze register,    Address offset: 0x34 */
+  uint32_t RESERVED5;          /*!< Reserved,                             Address offset: 0x38 */
+  __IO uint32_t APB1LFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x3C */
+  uint32_t RESERVED6;          /*!< Reserved,                             Address offset: 0x40 */
+  __IO uint32_t APB1HFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x44 */
+  uint32_t RESERVED7;          /*!< Reserved,                             Address offset: 0x48 */
+  __IO uint32_t APB2FZ1;     /*!< Debug MCU APB2FZ1 freeze register,    Address offset: 0x4C */
+  uint32_t RESERVED8;          /*!< Reserved,                             Address offset: 0x50 */
+  __IO uint32_t APB4FZ1;     /*!< Debug MCU APB4FZ1 freeze register,    Address offset: 0x54 */
+}DBGMCU_TypeDef;
+/**
+  * @brief DCMI
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
+  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
+  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
+  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
+  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
+  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
+  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
+  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
+  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
+  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
+} DCMI_TypeDef;
+
+/**
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
+  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
+  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
+  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
+  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
+  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
+  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
+  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
+  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CCR;          /*!< DMA channel x configuration register          */
+  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register         */
+  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register     */
+  __IO uint32_t CM0AR;        /*!< DMA channel x memory 0 address register       */
+  __IO uint32_t CM1AR;        /*!< DMA channel x memory 1 address register       */
+} BDMA_Channel_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
+  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
+} BDMA_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t  CCR;        /*!< DMA Multiplexer Channel x Control Register   */
+}DMAMUX_Channel_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t  CSR;      /*!< DMA Channel Status Register     */
+  __IO uint32_t  CFR;      /*!< DMA Channel Clear Flag Register */
+}DMAMUX_ChannelStatus_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t  RGCR;        /*!< DMA Request Generator x Control Register   */
+}DMAMUX_RequestGen_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t  RGSR;        /*!< DMA Request Generator Status Register       */
+  __IO uint32_t  RGCFR;       /*!< DMA Request Generator Clear Flag Register   */
+}DMAMUX_RequestGenStatus_TypeDef;
+
+/**
+  * @brief MDMA Controller
+  */
+typedef struct
+{
+  __IO uint32_t  GISR0;   /*!< MDMA Global Interrupt/Status Register 0,          Address offset: 0x00 */
+}MDMA_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t  CISR;      /*!< MDMA channel x interrupt/status register,             Address offset: 0x40 */
+  __IO uint32_t  CIFCR;     /*!< MDMA channel x interrupt flag clear register,         Address offset: 0x44 */
+  __IO uint32_t  CESR;      /*!< MDMA Channel x error status register,                 Address offset: 0x48 */
+  __IO uint32_t  CCR;       /*!< MDMA channel x control register,                      Address offset: 0x4C */
+  __IO uint32_t  CTCR;      /*!< MDMA channel x Transfer Configuration register,       Address offset: 0x50 */
+  __IO uint32_t  CBNDTR;    /*!< MDMA Channel x block number of data register,         Address offset: 0x54 */
+  __IO uint32_t  CSAR;      /*!< MDMA channel x source address register,               Address offset: 0x58 */
+  __IO uint32_t  CDAR;      /*!< MDMA channel x destination address register,          Address offset: 0x5C */
+  __IO uint32_t  CBRUR;     /*!< MDMA channel x Block Repeat address Update register,  Address offset: 0x60 */
+  __IO uint32_t  CLAR;      /*!< MDMA channel x Link Address register,                 Address offset: 0x64 */
+  __IO uint32_t  CTBR;      /*!< MDMA channel x Trigger and Bus selection Register,    Address offset: 0x68 */
+  uint32_t       RESERVED0; /*!< Reserved, 0x68                                                             */
+  __IO uint32_t  CMAR;      /*!< MDMA channel x Mask address register,                 Address offset: 0x70 */
+  __IO uint32_t  CMDR;      /*!< MDMA channel x Mask Data register,                    Address offset: 0x74 */
+}MDMA_Channel_TypeDef;
+
+/**
+  * @brief DMA2D Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */
+  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */
+  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */
+  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */
+  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */
+  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */
+  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */
+  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */
+  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */
+  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */
+  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */
+  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */
+  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */
+  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */
+  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */
+  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */
+  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */
+  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */
+  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */
+  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */
+  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
+  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */
+  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */
+} DMA2D_TypeDef;
+
+
+/**
+  * @brief Ethernet MAC
+  */
+typedef struct
+{
+  __IO uint32_t MACCR;
+  __IO uint32_t MACECR;
+  __IO uint32_t MACPFR;
+  __IO uint32_t MACWTR;
+  __IO uint32_t MACHT0R;
+  __IO uint32_t MACHT1R;
+  uint32_t      RESERVED1[14];
+  __IO uint32_t MACVTR;
+  uint32_t      RESERVED2;
+  __IO uint32_t MACVHTR;
+  uint32_t      RESERVED3;
+  __IO uint32_t MACVIR;
+  __IO uint32_t MACIVIR;
+  uint32_t      RESERVED4[2];
+  __IO uint32_t MACTFCR;
+  uint32_t      RESERVED5[7];
+  __IO uint32_t MACRFCR;
+  uint32_t      RESERVED6[7];
+  __IO uint32_t MACISR;
+  __IO uint32_t MACIER;
+  __IO uint32_t MACRXTXSR;
+  uint32_t      RESERVED7;
+  __IO uint32_t MACPCSR;
+  __IO uint32_t MACRWKPFR;
+  uint32_t      RESERVED8[2];
+  __IO uint32_t MACLCSR;
+  __IO uint32_t MACLTCR;
+  __IO uint32_t MACLETR;
+  __IO uint32_t MAC1USTCR;
+  uint32_t      RESERVED9[12];
+  __IO uint32_t MACVR;
+  __IO uint32_t MACDR;
+  uint32_t      RESERVED10;
+  __IO uint32_t MACHWF0R;
+  __IO uint32_t MACHWF1R;
+  __IO uint32_t MACHWF2R;
+  uint32_t      RESERVED11[54];
+  __IO uint32_t MACMDIOAR;
+  __IO uint32_t MACMDIODR;
+  uint32_t      RESERVED12[2];
+  __IO uint32_t MACARPAR;
+  uint32_t      RESERVED13[59];
+  __IO uint32_t MACA0HR;
+  __IO uint32_t MACA0LR;
+  __IO uint32_t MACA1HR;
+  __IO uint32_t MACA1LR;
+  __IO uint32_t MACA2HR;
+  __IO uint32_t MACA2LR;
+  __IO uint32_t MACA3HR;
+  __IO uint32_t MACA3LR;
+  uint32_t      RESERVED14[248];
+  __IO uint32_t MMCCR;
+  __IO uint32_t MMCRIR;
+  __IO uint32_t MMCTIR;
+  __IO uint32_t MMCRIMR;
+  __IO uint32_t MMCTIMR;
+  uint32_t      RESERVED15[14];
+  __IO uint32_t MMCTSCGPR;
+  __IO uint32_t MMCTMCGPR;
+  uint32_t      RESERVED16[5];
+  __IO uint32_t MMCTPCGR;
+  uint32_t      RESERVED17[10];
+  __IO uint32_t MMCRCRCEPR;
+  __IO uint32_t MMCRAEPR;
+  uint32_t      RESERVED18[10];
+  __IO uint32_t MMCRUPGR;
+  uint32_t      RESERVED19[9];
+  __IO uint32_t MMCTLPIMSTR;
+  __IO uint32_t MMCTLPITCR;
+  __IO uint32_t MMCRLPIMSTR;
+  __IO uint32_t MMCRLPITCR;
+  uint32_t      RESERVED20[65];
+  __IO uint32_t MACL3L4C0R;
+  __IO uint32_t MACL4A0R;
+  uint32_t      RESERVED21[2];
+  __IO uint32_t MACL3A0R0R;
+  __IO uint32_t MACL3A1R0R;
+  __IO uint32_t MACL3A2R0R;
+  __IO uint32_t MACL3A3R0R;
+  uint32_t      RESERVED22[4];
+  __IO uint32_t MACL3L4C1R;
+  __IO uint32_t MACL4A1R;
+  uint32_t      RESERVED23[2];
+  __IO uint32_t MACL3A0R1R;
+  __IO uint32_t MACL3A1R1R;
+  __IO uint32_t MACL3A2R1R;
+  __IO uint32_t MACL3A3R1R;
+  uint32_t      RESERVED24[108];
+  __IO uint32_t MACTSCR;
+  __IO uint32_t MACSSIR;
+  __IO uint32_t MACSTSR;
+  __IO uint32_t MACSTNR;
+  __IO uint32_t MACSTSUR;
+  __IO uint32_t MACSTNUR;
+  __IO uint32_t MACTSAR;
+  uint32_t      RESERVED25;
+  __IO uint32_t MACTSSR;
+  uint32_t      RESERVED26[3];
+  __IO uint32_t MACTTSSNR;
+  __IO uint32_t MACTTSSSR;
+  uint32_t      RESERVED27[2];
+  __IO uint32_t MACACR;
+  uint32_t      RESERVED28;
+  __IO uint32_t MACATSNR;
+  __IO uint32_t MACATSSR;
+  __IO uint32_t MACTSIACR;
+  __IO uint32_t MACTSEACR;
+  __IO uint32_t MACTSICNR;
+  __IO uint32_t MACTSECNR;
+  uint32_t      RESERVED29[4];
+  __IO uint32_t MACPPSCR;
+  uint32_t      RESERVED30[3];
+  __IO uint32_t MACPPSTTSR;
+  __IO uint32_t MACPPSTTNR;
+  __IO uint32_t MACPPSIR;
+  __IO uint32_t MACPPSWR;
+  uint32_t      RESERVED31[12];
+  __IO uint32_t MACPOCR;
+  __IO uint32_t MACSPI0R;
+  __IO uint32_t MACSPI1R;
+  __IO uint32_t MACSPI2R;
+  __IO uint32_t MACLMIR;
+  uint32_t      RESERVED32[11];
+  __IO uint32_t MTLOMR;
+  uint32_t      RESERVED33[7];
+  __IO uint32_t MTLISR;
+  uint32_t      RESERVED34[55];
+  __IO uint32_t MTLTQOMR;
+  __IO uint32_t MTLTQUR;
+  __IO uint32_t MTLTQDR;
+  uint32_t      RESERVED35[8];
+  __IO uint32_t MTLQICSR;
+  __IO uint32_t MTLRQOMR;
+  __IO uint32_t MTLRQMPOCR;
+  __IO uint32_t MTLRQDR;
+  uint32_t      RESERVED36[177];
+  __IO uint32_t DMAMR;
+  __IO uint32_t DMASBMR;
+  __IO uint32_t DMAISR;
+  __IO uint32_t DMADSR;
+  uint32_t      RESERVED37[60];
+  __IO uint32_t DMACCR;
+  __IO uint32_t DMACTCR;
+  __IO uint32_t DMACRCR;
+  uint32_t      RESERVED38[2];
+  __IO uint32_t DMACTDLAR;
+  uint32_t      RESERVED39;
+  __IO uint32_t DMACRDLAR;
+  __IO uint32_t DMACTDTPR;
+  uint32_t      RESERVED40;
+  __IO uint32_t DMACRDTPR;
+  __IO uint32_t DMACTDRLR;
+  __IO uint32_t DMACRDRLR;
+  __IO uint32_t DMACIER;
+  __IO uint32_t DMACRIWTR;
+__IO uint32_t DMACSFCSR;
+  uint32_t      RESERVED41;
+  __IO uint32_t DMACCATDR;
+  uint32_t      RESERVED42;
+  __IO uint32_t DMACCARDR;
+  uint32_t      RESERVED43;
+  __IO uint32_t DMACCATBR;
+  uint32_t      RESERVED44;
+  __IO uint32_t DMACCARBR;
+  __IO uint32_t DMACSR;
+uint32_t      RESERVED45[2];
+__IO uint32_t DMACMFCR;
+}ETH_TypeDef;
+/**
+  * @brief External Interrupt/Event Controller
+  */
+
+typedef struct
+{
+__IO uint32_t RTSR1;               /*!< EXTI Rising trigger selection register,          Address offset: 0x00 */
+__IO uint32_t FTSR1;               /*!< EXTI Falling trigger selection register,         Address offset: 0x04 */
+__IO uint32_t SWIER1;              /*!< EXTI Software interrupt event register,          Address offset: 0x08 */
+__IO uint32_t D3PMR1;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */
+__IO uint32_t D3PCR1L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L)     Address offset: 0x10 */
+__IO uint32_t D3PCR1H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H)   Address offset: 0x14 */
+uint32_t      RESERVED1[2];        /*!< Reserved,                                        0x18 to 0x1C         */
+__IO uint32_t RTSR2;               /*!< EXTI Rising trigger selection register,          Address offset: 0x20 */
+__IO uint32_t FTSR2;               /*!< EXTI Falling trigger selection register,         Address offset: 0x24 */
+__IO uint32_t SWIER2;              /*!< EXTI Software interrupt event register,          Address offset: 0x28 */
+__IO uint32_t D3PMR2;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */
+__IO uint32_t D3PCR2L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L)  Address offset: 0x30 */
+__IO uint32_t D3PCR2H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */
+uint32_t      RESERVED2[2];        /*!< Reserved,                                        0x38 to 0x3C         */
+__IO uint32_t RTSR3;               /*!< EXTI Rising trigger selection register,          Address offset: 0x40 */
+__IO uint32_t FTSR3;               /*!< EXTI Falling trigger selection register,         Address offset: 0x44 */
+__IO uint32_t SWIER3;              /*!< EXTI Software interrupt event register,          Address offset: 0x48 */
+__IO uint32_t D3PMR3;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */
+__IO uint32_t D3PCR3L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */
+__IO uint32_t D3PCR3H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */
+uint32_t      RESERVED3[10];       /*!< Reserved,                                        0x58 to 0x7C         */
+__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                    Address offset: 0x80 */
+__IO uint32_t EMR1;                /*!< EXTI Event mask register,                        Address offset: 0x84 */
+__IO uint32_t PR1;                 /*!< EXTI Pending register,                           Address offset: 0x88 */
+uint32_t      RESERVED4;           /*!< Reserved,                                        0x8C                 */
+__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                    Address offset: 0x90 */
+__IO uint32_t EMR2;                /*!< EXTI Event mask register,                        Address offset: 0x94 */
+__IO uint32_t PR2;                 /*!< EXTI Pending register,                           Address offset: 0x98 */
+uint32_t      RESERVED5;           /*!< Reserved,                                        0x9C                 */
+__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                    Address offset: 0xA0 */
+__IO uint32_t EMR3;                /*!< EXTI Event mask register,                        Address offset: 0xA4 */
+__IO uint32_t PR3;                 /*!< EXTI Pending register,                           Address offset: 0xA8 */
+}EXTI_TypeDef;
+
+typedef struct
+{
+__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                Address offset: 0x00 */
+__IO uint32_t EMR1;                /*!< EXTI Event mask register,                    Address offset: 0x04 */
+__IO uint32_t PR1;                 /*!< EXTI Pending register,                       Address offset: 0x08 */
+uint32_t      RESERVED1;           /*!< Reserved, 0x0C                                                    */
+__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                Address offset: 0x10 */
+__IO uint32_t EMR2;                /*!< EXTI Event mask register,                    Address offset: 0x14 */
+__IO uint32_t PR2;                 /*!< EXTI Pending register,                       Address offset: 0x18 */
+uint32_t      RESERVED2;           /*!< Reserved, 0x1C                                                    */
+__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                Address offset: 0x20 */
+__IO uint32_t EMR3;                /*!< EXTI Event mask register,                    Address offset: 0x24 */
+__IO uint32_t PR3;                 /*!< EXTI Pending register,                       Address offset: 0x28 */
+}EXTI_Core_TypeDef;
+
+
+/**
+  * @brief FLASH Registers
+  */
+
+typedef struct
+{
+  __IO uint32_t ACR;             /*!< FLASH access control register,                            Address offset: 0x00  */
+  __IO uint32_t KEYR1;           /*!< Flash Key Register for bank1,                             Address offset: 0x04  */
+  __IO uint32_t OPTKEYR;         /*!< Flash Option Key Register,                                Address offset: 0x08  */
+  __IO uint32_t CR1;             /*!< Flash Control Register for bank1,                         Address offset: 0x0C  */
+  __IO uint32_t SR1;             /*!< Flash Status Register for bank1,                          Address offset: 0x10  */
+  __IO uint32_t CCR1;            /*!< Flash Control Register for bank1,                         Address offset: 0x14  */
+  __IO uint32_t OPTCR;           /*!< Flash Option Control Register,                            Address offset: 0x18  */
+  __IO uint32_t OPTSR_CUR;       /*!< Flash Option Status Current Register,                     Address offset: 0x1C  */
+  __IO uint32_t OPTSR_PRG;       /*!< Flash Option Status to Program Register,                  Address offset: 0x20  */
+  __IO uint32_t OPTCCR;          /*!< Flash Option Clear Control Register,                      Address offset: 0x24  */
+  __IO uint32_t PRAR_CUR1;       /*!< Flash Current Protection Address Register for bank1,      Address offset: 0x28  */
+  __IO uint32_t PRAR_PRG1;       /*!< Flash Protection Address to Program Register for bank1,   Address offset: 0x2C  */
+  __IO uint32_t SCAR_CUR1;       /*!< Flash Current Secure Address Register for bank1,          Address offset: 0x30  */
+  __IO uint32_t SCAR_PRG1;       /*!< Flash Secure Address to Program Register for bank1,       Address offset: 0x34  */
+  __IO uint32_t WPSN_CUR1;       /*!< Flash Current Write Protection Register on bank1,         Address offset: 0x38  */
+  __IO uint32_t WPSN_PRG1;       /*!< Flash Write Protection to Program Register on bank1,      Address offset: 0x3C  */
+  __IO uint32_t BOOT_CUR;        /*!< Flash Current Boot Address for Pelican Core Register,     Address offset: 0x40  */
+  __IO uint32_t BOOT_PRG;        /*!< Flash Boot Address to Program for Pelican Core Register,  Address offset: 0x44  */
+  uint32_t      RESERVED0[2];    /*!< Reserved, 0x48 to 0x4C                                                          */
+  __IO uint32_t CRCCR1;          /*!< Flash CRC Control register For Bank1 Register ,           Address offset: 0x50  */
+  __IO uint32_t CRCSADD1;        /*!< Flash CRC Start Address Register for Bank1 ,              Address offset: 0x54  */
+  __IO uint32_t CRCEADD1;        /*!< Flash CRC End Address Register for Bank1 ,                Address offset: 0x58  */
+  __IO uint32_t CRCDATA;         /*!< Flash CRC Data Register for Bank1 ,                       Address offset: 0x5C  */
+  __IO uint32_t ECC_FA1;         /*!< Flash ECC Fail Address For Bank1 Register ,               Address offset: 0x60  */
+  uint32_t      RESERVED1[40];   /*!< Reserved, 0x64 to 0x100                                                         */
+  __IO uint32_t KEYR2;           /*!< Flash Key Register for bank2,                             Address offset: 0x104 */
+  uint32_t      RESERVED2;       /*!< Reserved, 0x108                                                                 */
+  __IO uint32_t CR2;             /*!< Flash Control Register for bank2,                         Address offset: 0x10C */
+  __IO uint32_t SR2;             /*!< Flash Status Register for bank2,                          Address offset: 0x110 */
+  __IO uint32_t CCR2;            /*!< Flash Status Register for bank2,                          Address offset: 0x114 */
+  uint32_t      RESERVED3[4];    /*!< Reserved, 0x118 to 0x124                                                        */
+  __IO uint32_t PRAR_CUR2;       /*!< Flash Current Protection Address Register for bank2,      Address offset: 0x128 */
+  __IO uint32_t PRAR_PRG2;       /*!< Flash Protection Address to Program Register for bank2,   Address offset: 0x12C */
+  __IO uint32_t SCAR_CUR2;       /*!< Flash Current Secure Address Register for bank2,          Address offset: 0x130 */
+  __IO uint32_t SCAR_PRG2;       /*!< Flash Secure Address Register for bank2,                  Address offset: 0x134 */
+  __IO uint32_t WPSN_CUR2;       /*!< Flash Current Write Protection Register on bank2,         Address offset: 0x138 */
+  __IO uint32_t WPSN_PRG2;       /*!< Flash Write Protection to Program Register on bank2,      Address offset: 0x13C */
+  uint32_t      RESERVED4[4];    /*!< Reserved, 0x140 to 0x14C                                                        */
+  __IO uint32_t CRCCR2;          /*!< Flash CRC Control register For Bank2 Register ,           Address offset: 0x150 */
+  __IO uint32_t CRCSADD2;        /*!< Flash CRC Start Address Register for Bank2 ,              Address offset: 0x154 */
+  __IO uint32_t CRCEADD2;        /*!< Flash CRC End Address Register for Bank2 ,                Address offset: 0x158 */
+  __IO uint32_t CRCDATA2;        /*!< Flash CRC Data Register for Bank2 ,                       Address offset: 0x15C */
+  __IO uint32_t ECC_FA2;         /*!< Flash ECC Fail Address For Bank2 Register ,               Address offset: 0x160 */
+} FLASH_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FMC_Bank1_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank1E
+  */
+
+typedef struct
+{
+  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank2
+  */
+
+typedef struct
+{
+  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */
+  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */
+  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */
+  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
+  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */
+  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */
+} FMC_Bank2_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank3
+  */
+
+typedef struct
+{
+  __IO uint32_t PCR;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */
+  __IO uint32_t SR;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */
+  __IO uint32_t PMEM;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */
+  __IO uint32_t PATT;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
+  uint32_t      RESERVED;  /*!< Reserved, 0x90                                                            */
+  __IO uint32_t ECCR;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */
+} FMC_Bank3_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank5 and 6
+  */
+
+
+typedef struct
+{
+  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */
+  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */
+  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */
+  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */
+  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */
+} FMC_Bank5_6_TypeDef;
+
+/**
+  * @brief General Purpose I/O
+  */
+
+typedef struct
+{
+  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
+  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
+  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
+  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
+  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
+  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
+  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset,               Address offset: 0x18      */
+  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
+  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+  * @brief Operational Amplifier (OPAMP)
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;          /*!< OPAMP control/status register,                      Address offset: 0x00 */
+  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,     Address offset: 0x04 */
+  __IO uint32_t HSOTR;        /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */
+} OPAMP_TypeDef;
+
+/**
+  * @brief System configuration controller
+  */
+
+typedef struct
+{
+ uint32_t RESERVED1;           /*!< Reserved,                                           Address offset: 0x00        */
+ __IO uint32_t PMCR;           /*!< SYSCFG peripheral mode configuration register,      Address offset: 0x04        */
+ __IO uint32_t EXTICR[4];      /*!< SYSCFG external interrupt configuration registers,  Address offset: 0x08-0x14   */
+ __IO uint32_t CFGR;           /*!< SYSCFG configuration registers,                     Address offset: 0x18        */
+ uint32_t RESERVED2;           /*!< Reserved,                                           Address offset: 0x1C        */
+ __IO uint32_t CCCSR;          /*!< SYSCFG compensation cell control/status register,   Address offset: 0x20        */
+ __IO uint32_t CCVR;           /*!< SYSCFG compensation cell value register,            Address offset: 0x24        */
+ __IO uint32_t CCCR;           /*!< SYSCFG compensation cell code register,             Address offset: 0x28        */
+ __IO uint32_t PWRCR;          /*!< PWR control register,                               Address offset: 0x2C        */
+  uint32_t     RESERVED3[61];  /*!< Reserved, 0x30-0x120                                                            */
+  __IO uint32_t PKGR;          /*!< SYSCFG package register,                            Address offset: 0x124       */
+  uint32_t     RESERVED4[118]; /*!< Reserved, 0x128-0x2FC                                                           */
+ __IO uint32_t UR0;            /*!< SYSCFG user register 0,                             Address offset: 0x300       */
+ __IO uint32_t UR1;            /*!< SYSCFG user register 1,                             Address offset: 0x304       */
+ __IO uint32_t UR2;            /*!< SYSCFG user register 2,                             Address offset: 0x308       */
+ __IO uint32_t UR3;            /*!< SYSCFG user register 3,                             Address offset: 0x30C       */
+ __IO uint32_t UR4;            /*!< SYSCFG user register 4,                             Address offset: 0x310       */
+ __IO uint32_t UR5;            /*!< SYSCFG user register 5,                             Address offset: 0x314       */
+ __IO uint32_t UR6;            /*!< SYSCFG user register 6,                             Address offset: 0x318       */
+ __IO uint32_t UR7;            /*!< SYSCFG user register 7,                             Address offset: 0x31C       */
+ __IO uint32_t UR8;            /*!< SYSCFG user register 8,                             Address offset: 0x320       */
+ __IO uint32_t UR9;            /*!< SYSCFG user register 9,                             Address offset: 0x324       */
+ __IO uint32_t UR10;           /*!< SYSCFG user register 10,                            Address offset: 0x328       */
+ __IO uint32_t UR11;           /*!< SYSCFG user register 11,                            Address offset: 0x32C       */
+ __IO uint32_t UR12;           /*!< SYSCFG user register 12,                            Address offset: 0x330       */
+ __IO uint32_t UR13;           /*!< SYSCFG user register 13,                            Address offset: 0x334       */
+ __IO uint32_t UR14;           /*!< SYSCFG user register 14,                            Address offset: 0x338       */
+ __IO uint32_t UR15;           /*!< SYSCFG user register 15,                            Address offset: 0x33C       */
+ __IO uint32_t UR16;           /*!< SYSCFG user register 16,                            Address offset: 0x340       */
+ __IO uint32_t UR17;           /*!< SYSCFG user register 17,                            Address offset: 0x344       */
+
+} SYSCFG_TypeDef;
+
+/**
+  * @brief Inter-integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
+  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
+  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
+  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
+  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
+  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
+  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
+  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
+  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
+  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
+  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
+} I2C_TypeDef;
+
+/**
+  * @brief Independent WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
+  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
+} IWDG_TypeDef;
+
+
+/**
+  * @brief JPEG Codec
+  */
+typedef struct
+{
+  __IO uint32_t CONFR0;          /*!< JPEG Codec Control Register (JPEG_CONFR0),        Address offset: 00h       */
+  __IO uint32_t CONFR1;          /*!< JPEG Codec Control Register (JPEG_CONFR1),        Address offset: 04h       */
+  __IO uint32_t CONFR2;          /*!< JPEG Codec Control Register (JPEG_CONFR2),        Address offset: 08h       */
+  __IO uint32_t CONFR3;          /*!< JPEG Codec Control Register (JPEG_CONFR3),        Address offset: 0Ch       */
+  __IO uint32_t CONFR4;          /*!< JPEG Codec Control Register (JPEG_CONFR4),        Address offset: 10h       */
+  __IO uint32_t CONFR5;          /*!< JPEG Codec Control Register (JPEG_CONFR5),        Address offset: 14h       */
+  __IO uint32_t CONFR6;          /*!< JPEG Codec Control Register (JPEG_CONFR6),        Address offset: 18h       */
+  __IO uint32_t CONFR7;          /*!< JPEG Codec Control Register (JPEG_CONFR7),        Address offset: 1Ch       */
+  uint32_t  Reserved20[4];       /* Reserved                                            Address offset: 20h-2Ch   */
+  __IO uint32_t CR;              /*!< JPEG Control Register (JPEG_CR),                  Address offset: 30h       */
+  __IO uint32_t SR;              /*!< JPEG Status Register (JPEG_SR),                   Address offset: 34h       */
+  __IO uint32_t CFR;             /*!< JPEG Clear Flag Register (JPEG_CFR),              Address offset: 38h       */
+  uint32_t  Reserved3c;          /* Reserved                                            Address offset: 3Ch       */
+  __IO uint32_t DIR;             /*!< JPEG Data Input Register (JPEG_DIR),              Address offset: 40h       */
+  __IO uint32_t DOR;             /*!< JPEG Data Output Register (JPEG_DOR),             Address offset: 44h       */
+  uint32_t  Reserved48[2];       /* Reserved                                            Address offset: 48h-4Ch   */
+  __IO uint32_t QMEM0[16];       /*!< JPEG quantization tables 0,                       Address offset: 50h-8Ch   */
+  __IO uint32_t QMEM1[16];       /*!< JPEG quantization tables 1,                       Address offset: 90h-CCh   */
+  __IO uint32_t QMEM2[16];       /*!< JPEG quantization tables 2,                       Address offset: D0h-10Ch  */
+  __IO uint32_t QMEM3[16];       /*!< JPEG quantization tables 3,                       Address offset: 110h-14Ch */
+  __IO uint32_t HUFFMIN[16];     /*!< JPEG HuffMin tables,                              Address offset: 150h-18Ch */
+  __IO uint32_t HUFFBASE[32];    /*!< JPEG HuffSymb tables,                             Address offset: 190h-20Ch */
+  __IO uint32_t HUFFSYMB[84];    /*!< JPEG HUFFSYMB tables,                             Address offset: 210h-35Ch */
+  __IO uint32_t DHTMEM[103];     /*!< JPEG DHTMem tables,                               Address offset: 360h-4F8h */
+  uint32_t  Reserved4FC;         /* Reserved                                            Address offset: 4FCh      */
+  __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0,                 Address offset: 500h-65Ch */
+  __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1,                 Address offset: 660h-7BCh */
+  __IO uint32_t HUFFENC_DC0[8];  /*!< JPEG encodor, DC Huffman table 0,                 Address offset: 7C0h-7DCh */
+  __IO uint32_t HUFFENC_DC1[8];  /*!< JPEG encodor, DC Huffman table 1,                 Address offset: 7E0h-7FCh */
+
+} JPEG_TypeDef;
+
+/**
+  * @brief LCD-TFT Display Controller
+  */
+
+typedef struct
+{
+  uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04                                                       */
+  __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */
+  __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */
+  __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */
+  __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */
+  __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */
+  uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20                                                       */
+  __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */
+  uint32_t      RESERVED2[1];  /*!< Reserved, 0x28                                                            */
+  __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */
+  uint32_t      RESERVED3[1];  /*!< Reserved, 0x30                                                            */
+  __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */
+  __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */
+  __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */
+  __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
+  __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */
+  __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                 Address offset: 0x48 */
+} LTDC_TypeDef;
+
+/**
+  * @brief LCD-TFT Display layer x Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */
+  __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
+  __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */
+  __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */
+  __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */
+  __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */
+  __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */
+  __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */
+  uint32_t      RESERVED0[2];  /*!< Reserved */
+  __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */
+  __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */
+  __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */
+  uint32_t      RESERVED1[3];  /*!< Reserved */
+  __IO uint32_t CLUTWR;         /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */
+
+} LTDC_Layer_TypeDef;
+
+/**
+  * @brief Power Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;       /*!< PWR power control register 1,            Address offset: 0x00 */
+  __IO uint32_t CSR1;      /*!< PWR power control status register 1,     Address offset: 0x04 */
+  __IO uint32_t CR2;       /*!< PWR power control register 2,            Address offset: 0x08 */
+  __IO uint32_t CR3;       /*!< PWR power control register 3,            Address offset: 0x0C */
+  __IO uint32_t CPUCR;     /*!< PWR CPU control register,                Address offset: 0x10 */
+       uint32_t RESERVED0; /*!< Reserved,                                Address offset: 0x14 */
+  __IO uint32_t D3CR;      /*!< PWR D3 domain control register,          Address offset: 0x18 */
+       uint32_t RESERVED1; /*!< Reserved,                                Address offset: 0x1C */
+  __IO uint32_t WKUPCR;    /*!< PWR wakeup clear register,               Address offset: 0x20 */
+  __IO uint32_t WKUPFR;    /*!< PWR wakeup flag register,                Address offset: 0x24 */
+  __IO uint32_t WKUPEPR;   /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */
+} PWR_TypeDef;
+
+/**
+  * @brief Reset and Clock Control
+  */
+
+typedef struct
+{
+ __IO uint32_t CR;             /*!< RCC clock control register,                                              Address offset: 0x00  */
+ __IO uint32_t HSICFGR;        /*!< HSI Clock Calibration Register,                                          Address offset: 0x04  */
+ __IO uint32_t CRRCR;          /*!< Clock Recovery RC  Register,                                             Address offset: 0x08  */
+ __IO uint32_t CSICFGR;        /*!< CSI Clock Calibration Register,                                          Address offset: 0x0C  */
+ __IO uint32_t CFGR;           /*!< RCC clock configuration register,                                        Address offset: 0x10  */
+ uint32_t     RESERVED1;       /*!< Reserved,                                                                Address offset: 0x14  */
+ __IO uint32_t D1CFGR;         /*!< RCC Domain 1 configuration register,                                     Address offset: 0x18  */
+ __IO uint32_t D2CFGR;         /*!< RCC Domain 2 configuration register,                                     Address offset: 0x1C  */
+ __IO uint32_t D3CFGR;         /*!< RCC Domain 3 configuration register,                                     Address offset: 0x20  */
+ uint32_t     RESERVED2;       /*!< Reserved,                                                                Address offset: 0x24  */
+ __IO uint32_t PLLCKSELR;      /*!< RCC PLLs Clock Source Selection Register,                                Address offset: 0x28  */
+ __IO uint32_t PLLCFGR;        /*!< RCC PLLs  Configuration Register,                                        Address offset: 0x2C  */
+ __IO uint32_t PLL1DIVR;       /*!< RCC PLL1 Dividers Configuration Register,                                Address offset: 0x30  */
+ __IO uint32_t PLL1FRACR;      /*!< RCC PLL1 Fractional Divider Configuration Register,                      Address offset: 0x34  */
+ __IO uint32_t PLL2DIVR;       /*!< RCC PLL2 Dividers Configuration Register,                                Address offset: 0x38  */
+ __IO uint32_t PLL2FRACR;      /*!< RCC PLL2 Fractional Divider Configuration Register,                      Address offset: 0x3C  */
+ __IO uint32_t PLL3DIVR;       /*!< RCC PLL3 Dividers Configuration Register,                                Address offset: 0x40  */
+ __IO uint32_t PLL3FRACR;      /*!< RCC PLL3 Fractional Divider Configuration Register,                      Address offset: 0x44  */
+ uint32_t      RESERVED3;      /*!< Reserved,                                                                Address offset: 0x48  */
+ __IO uint32_t  D1CCIPR;       /*!< RCC Domain 1 Kernel Clock Configuration Register                         Address offset: 0x4C  */
+ __IO uint32_t  D2CCIP1R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x50  */
+ __IO uint32_t  D2CCIP2R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x54  */
+ __IO uint32_t  D3CCIPR;       /*!< RCC Domain 3 Kernel Clock Configuration Register                         Address offset: 0x58  */
+ uint32_t      RESERVED4;      /*!< Reserved,                                                                Address offset: 0x5C  */
+ __IO uint32_t  CIER;          /*!< RCC Clock Source Interrupt Enable Register                               Address offset: 0x60  */
+ __IO uint32_t  CIFR;          /*!< RCC Clock Source Interrupt Flag Register                                 Address offset: 0x64  */
+ __IO uint32_t  CICR;          /*!< RCC Clock Source Interrupt Clear Register                                Address offset: 0x68  */
+ uint32_t     RESERVED5;       /*!< Reserved,                                                                Address offset: 0x6C  */
+ __IO uint32_t  BDCR;          /*!< RCC Vswitch Backup Domain Control Register,                              Address offset: 0x70  */
+ __IO uint32_t  CSR;           /*!< RCC clock control & status register,                                     Address offset: 0x74  */
+ uint32_t     RESERVED6;       /*!< Reserved,                                                                Address offset: 0x78  */
+ __IO uint32_t AHB3RSTR;       /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x7C  */
+ __IO uint32_t AHB1RSTR;       /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x80  */
+ __IO uint32_t AHB2RSTR;       /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x84  */
+ __IO uint32_t AHB4RSTR;       /*!< RCC AHB4 peripheral reset register,                                      Address offset: 0x88  */
+ __IO uint32_t APB3RSTR;       /*!< RCC APB3 peripheral reset register,                                      Address offset: 0x8C  */
+ __IO uint32_t APB1LRSTR;      /*!< RCC APB1 peripheral reset Low Word register,                             Address offset: 0x90  */
+ __IO uint32_t APB1HRSTR;      /*!< RCC APB1 peripheral reset High Word register,                            Address offset: 0x94  */
+ __IO uint32_t APB2RSTR;       /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x98  */
+ __IO uint32_t APB4RSTR;       /*!< RCC APB4 peripheral reset register,                                      Address offset: 0x9C  */
+ __IO uint32_t GCR;            /*!< RCC RCC Global Control  Register,                                        Address offset: 0xA0  */
+ uint32_t     RESERVED8;       /*!< Reserved,                                                                Address offset: 0xA4  */
+ __IO uint32_t D3AMR;          /*!< RCC Domain 3 Autonomous Mode Register,                                   Address offset: 0xA8  */
+ uint32_t     RESERVED11[9];    /*!< Reserved, 0xAC-0xCC                                                      Address offset: 0xAC  */
+ __IO uint32_t RSR;            /*!< RCC Reset status register,                                               Address offset: 0xD0  */
+ __IO uint32_t AHB3ENR;        /*!< RCC AHB3 peripheral clock  register,                                     Address offset: 0xD4  */
+ __IO uint32_t AHB1ENR;        /*!< RCC AHB1 peripheral clock  register,                                     Address offset: 0xD8  */
+ __IO uint32_t AHB2ENR;        /*!< RCC AHB2 peripheral clock  register,                                     Address offset: 0xDC  */
+ __IO uint32_t AHB4ENR;        /*!< RCC AHB4 peripheral clock  register,                                     Address offset: 0xE0  */
+ __IO uint32_t APB3ENR;        /*!< RCC APB3 peripheral clock  register,                                     Address offset: 0xE4  */
+ __IO uint32_t APB1LENR;       /*!< RCC APB1 peripheral clock  Low Word register,                            Address offset: 0xE8  */
+ __IO uint32_t APB1HENR;       /*!< RCC APB1 peripheral clock  High Word register,                           Address offset: 0xEC  */
+ __IO uint32_t APB2ENR;        /*!< RCC APB2 peripheral clock  register,                                     Address offset: 0xF0  */
+ __IO uint32_t APB4ENR;        /*!< RCC APB4 peripheral clock  register,                                     Address offset: 0xF4  */
+ uint32_t      RESERVED12;      /*!< Reserved,                                                                Address offset: 0xF8  */
+ __IO uint32_t AHB3LPENR;      /*!< RCC AHB3 peripheral sleep clock  register,                               Address offset: 0xFC  */
+ __IO uint32_t AHB1LPENR;      /*!< RCC AHB1 peripheral sleep clock  register,                               Address offset: 0x100 */
+ __IO uint32_t AHB2LPENR;      /*!< RCC AHB2 peripheral sleep clock  register,                               Address offset: 0x104 */
+ __IO uint32_t AHB4LPENR;      /*!< RCC AHB4 peripheral sleep clock  register,                               Address offset: 0x108 */
+ __IO uint32_t APB3LPENR;      /*!< RCC APB3 peripheral sleep clock  register,                               Address offset: 0x10C */
+ __IO uint32_t APB1LLPENR;     /*!< RCC APB1 peripheral sleep clock  Low Word register,                      Address offset: 0x110 */
+ __IO uint32_t APB1HLPENR;     /*!< RCC APB1 peripheral sleep clock  High Word register,                     Address offset: 0x114 */
+ __IO uint32_t APB2LPENR;      /*!< RCC APB2 peripheral sleep clock  register,                               Address offset: 0x118 */
+ __IO uint32_t APB4LPENR;      /*!< RCC APB4 peripheral sleep clock  register,                               Address offset: 0x11C */
+ uint32_t     RESERVED13[4];   /*!< Reserved, 0x120-0x12C                                                    Address offset: 0x120 */
+
+} RCC_TypeDef;
+
+
+/**
+  * @brief Real-Time Clock
+  */
+typedef struct
+{
+  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
+  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
+  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
+  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
+  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
+  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
+       uint32_t RESERVED;   /*!< Reserved,                                                  Address offset: 0x18 */
+  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
+  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
+  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
+  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
+  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
+  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
+  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
+  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
+  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
+  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */
+  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
+  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
+  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset: 0x4C */
+  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
+  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
+  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
+  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
+  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
+  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */
+  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */
+  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */
+  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */
+  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
+  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */
+  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */
+  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */
+  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */
+  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */
+  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */
+  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */
+  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */
+  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */
+  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */
+  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */
+  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */
+  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */
+  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */
+  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */
+  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */
+  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */
+  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */
+  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */
+  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */
+  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */
+  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */
+} RTC_TypeDef;
+
+/**
+  * @brief Serial Audio Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t GCR;           /*!< SAI global configuration register, Address offset: 0x00 */
+  uint32_t      RESERVED0[16]; /*!< Reserved, 0x04 - 0x43                                   */
+  __IO uint32_t PDMCR;         /*!< SAI PDM control register,          Address offset: 0x44 */
+  __IO uint32_t PDMDLY;        /*!< SAI PDM delay register,            Address offset: 0x48 */
+} SAI_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */
+  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */
+  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */
+  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */
+  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
+  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */
+  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */
+  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+/**
+  * @brief SPDIF-RX Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t   CR;           /*!< Control register,                   Address offset: 0x00 */
+  __IO uint32_t   IMR;          /*!< Interrupt mask register,            Address offset: 0x04 */
+  __IO uint32_t   SR;           /*!< Status register,                    Address offset: 0x08 */
+  __IO uint32_t   IFCR;         /*!< Interrupt Flag Clear register,      Address offset: 0x0C */
+  __IO uint32_t   DR;           /*!< Data input register,                Address offset: 0x10 */
+  __IO uint32_t   CSR;          /*!< Channel Status register,            Address offset: 0x14 */
+  __IO uint32_t   DIR;          /*!< Debug Information register,         Address offset: 0x18 */
+  uint32_t        RESERVED2;    /*!< Reserved,  0x1A                                          */
+} SPDIFRX_TypeDef;
+
+
+/**
+  * @brief Secure digital input/output Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t POWER;          /*!< SDMMC power control register,             Address offset: 0x00  */
+  __IO uint32_t CLKCR;          /*!< SDMMC clock control register,             Address offset: 0x04  */
+  __IO uint32_t ARG;            /*!< SDMMC argument register,                  Address offset: 0x08  */
+  __IO uint32_t CMD;            /*!< SDMMC command register,                   Address offset: 0x0C  */
+  __I uint32_t  RESPCMD;        /*!< SDMMC command response register,          Address offset: 0x10  */
+  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,                Address offset: 0x14  */
+  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,                Address offset: 0x18  */
+  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,                Address offset: 0x1C  */
+  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,                Address offset: 0x20  */
+  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,                Address offset: 0x24  */
+  __IO uint32_t DLEN;           /*!< SDMMC data length register,               Address offset: 0x28  */
+  __IO uint32_t DCTRL;          /*!< SDMMC data control register,              Address offset: 0x2C  */
+  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,              Address offset: 0x30  */
+  __I uint32_t  STA;            /*!< SDMMC status register,                    Address offset: 0x34  */
+  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,           Address offset: 0x38  */
+  __IO uint32_t MASK;           /*!< SDMMC mask register,                      Address offset: 0x3C  */
+  __IO uint32_t ACKTIME;        /*!< SDMMC Acknowledgement timer register,     Address offset: 0x40  */
+  uint32_t      RESERVED0[3];   /*!< Reserved, 0x44 - 0x4C - 0x4C                                    */
+  __IO uint32_t IDMACTRL;       /*!< SDMMC DMA control register,               Address offset: 0x50  */
+  __IO uint32_t IDMABSIZE;      /*!< SDMMC DMA buffer size register,           Address offset: 0x54  */
+  __IO uint32_t IDMABASE0;      /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58  */
+  __IO uint32_t IDMABASE1;      /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C  */
+  uint32_t      RESERVED1[8];   /*!< Reserved, 0x60-0x7C                                             */
+  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,                 Address offset: 0x80  */
+  uint32_t      RESERVED2[222]; /*!< Reserved, 0x84-0x3F8                                            */
+  __IO uint32_t IPVR;           /*!< SDMMC data FIFO register,                 Address offset: 0x3FC */
+} SDMMC_TypeDef;
+
+
+/**
+  * @brief Delay Block DLYB
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< DELAY BLOCK control register,  Address offset: 0x00 */
+  __IO uint32_t CFGR;        /*!< DELAY BLOCK configuration register,  Address offset: 0x04 */
+} DLYB_TypeDef;
+
+/**
+  * @brief HW Semaphore HSEM
+  */
+
+typedef struct
+{
+  __IO uint32_t R[32];      /*!< 2-step write lock and read back registers,     Address offset: 00h-7Ch  */
+  __IO uint32_t RLR[32];    /*!< 1-step read lock registers,                    Address offset: 80h-FCh  */
+  __IO uint32_t C1IER;      /*!< HSEM Interrupt enable register ,             Address offset: 100h     */
+  __IO uint32_t C1ICR;      /*!< HSEM Interrupt clear register ,              Address offset: 104h     */
+  __IO uint32_t C1ISR;      /*!< HSEM Interrupt Status register ,             Address offset: 108h     */
+  __IO uint32_t C1MISR;     /*!< HSEM Interrupt Masked Status register ,      Address offset: 10Ch     */
+  uint32_t  Reserved[12];   /* Reserved                                       Address offset: 110h-13Ch  */
+  __IO uint32_t CR;         /*!< HSEM Semaphore clear register ,                Address offset: 140h      */
+  __IO uint32_t KEYR;       /*!< HSEM Semaphore clear key register ,            Address offset: 144h      */
+
+} HSEM_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t IER;        /*!< HSEM interrupt enable register ,                Address offset:   0h     */
+  __IO uint32_t ICR;        /*!< HSEM interrupt clear register ,                 Address offset:   4h     */
+  __IO uint32_t ISR;        /*!< HSEM interrupt status register ,                Address offset:   8h     */
+  __IO uint32_t MISR;       /*!< HSEM masked interrupt status register ,         Address offset:   Ch     */
+} HSEM_Common_TypeDef;
+
+/**
+  * @brief Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;           /*!< SPI/I2S Control register 1,                      Address offset: 0x00 */
+  __IO uint32_t CR2;           /*!< SPI Control register 2,                          Address offset: 0x04 */
+  __IO uint32_t CFG1;          /*!< SPI Configuration register 1,                    Address offset: 0x08 */
+  __IO uint32_t CFG2;          /*!< SPI Configuration register 2,                    Address offset: 0x0C */
+  __IO uint32_t IER;           /*!< SPI/I2S Interrupt Enable register,               Address offset: 0x10 */
+  __IO uint32_t SR;            /*!< SPI/I2S Status register,                         Address offset: 0x14 */
+  __IO uint32_t IFCR;          /*!< SPI/I2S Interrupt/Status flags clear register,   Address offset: 0x18 */
+  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                        */
+  __IO uint32_t TXDR;          /*!< SPI/I2S Transmit data register,                  Address offset: 0x20 */
+  uint32_t      RESERVED1[3];  /*!< Reserved, 0x24-0x2C                                                   */
+  __IO uint32_t RXDR;          /*!< SPI/I2S Receive data register,                   Address offset: 0x30 */
+  uint32_t      RESERVED2[3];  /*!< Reserved, 0x34-0x3C                                                   */
+  __IO uint32_t CRCPOLY;       /*!< SPI CRC Polynomial register,                     Address offset: 0x40 */
+  __IO uint32_t TXCRC;         /*!< SPI Transmitter CRC register,                    Address offset: 0x44 */
+  __IO uint32_t RXCRC;         /*!< SPI Receiver CRC register,                       Address offset: 0x48 */
+  __IO uint32_t UDRDR;         /*!< SPI Underrun data register,                      Address offset: 0x4C */
+  __IO uint32_t I2SCFGR;       /*!< I2S Configuration register,                      Address offset: 0x50 */
+
+} SPI_TypeDef;
+/**
+  * @brief QUAD Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< QUADSPI Control register,                           Address offset: 0x00 */
+  __IO uint32_t DCR;      /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */
+  __IO uint32_t SR;       /*!< QUADSPI Status register,                            Address offset: 0x08 */
+  __IO uint32_t FCR;      /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */
+  __IO uint32_t DLR;      /*!< QUADSPI Data Length register,                       Address offset: 0x10 */
+  __IO uint32_t CCR;      /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */
+  __IO uint32_t AR;       /*!< QUADSPI Address register,                           Address offset: 0x18 */
+  __IO uint32_t ABR;      /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */
+  __IO uint32_t DR;       /*!< QUADSPI Data register,                              Address offset: 0x20 */
+  __IO uint32_t PSMKR;    /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */
+  __IO uint32_t PSMAR;    /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */
+  __IO uint32_t PIR;      /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */
+  __IO uint32_t LPTR;     /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */
+} QUADSPI_TypeDef;
+
+/**
+  * @brief TIM
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */
+  __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */
+  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */
+  __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */
+  __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */
+  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */
+  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */
+  __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */
+  __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */
+  __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */
+  __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */
+  __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */
+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */
+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */
+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */
+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */
+  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */
+  __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */
+  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */
+  uint32_t      RESERVED1;   /*!< Reserved, 0x50                                                 */
+  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */
+  __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */
+  __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */
+  __IO uint32_t AF1;         /*!< TIM alternate function option register 1, Address offset: 0x60 */
+  __IO uint32_t AF2;         /*!< TIM alternate function option register 2, Address offset: 0x64 */
+  __IO uint32_t TISEL;       /*!< TIM Input Selection register,             Address offset: 0x68 */
+} TIM_TypeDef;
+
+/**
+  * @brief LPTIMIMER
+  */
+typedef struct
+{
+  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,         Address offset: 0x00 */
+  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,              Address offset: 0x04 */
+  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,             Address offset: 0x08 */
+  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                Address offset: 0x0C */
+  __IO uint32_t CR;       /*!< LPTIM Control register,                      Address offset: 0x10 */
+  __IO uint32_t CMP;      /*!< LPTIM Compare register,                      Address offset: 0x14 */
+  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                   Address offset: 0x18 */
+  __IO uint32_t CNT;      /*!< LPTIM Counter register,                      Address offset: 0x1C */
+  uint32_t  RESERVED1;    /*!< Reserved, 0x20                                                    */
+  __IO uint32_t CFGR2;    /*!< LPTIM Configuration register,                Address offset: 0x24 */
+} LPTIM_TypeDef;
+
+/**
+  * @brief Comparator
+  */
+typedef struct
+{
+  __IO uint32_t SR;        /*!< Comparator status register,                    Address offset: 0x00 */
+  __IO uint32_t ICFR;      /*!< Comparator interrupt clear flag register,       Address offset: 0x04 */
+  __IO uint32_t OR;        /*!< Comparator option register,                  Address offset: 0x08 */
+} COMPOPT_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CFGR;      /*!< Comparator configuration register  ,           Address offset: 0x00 */
+} COMP_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CFGR;       /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
+} COMP_Common_TypeDef;
+/**
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */
+  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */
+  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
+  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */
+  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
+  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */
+  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
+  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
+  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
+  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
+  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
+  __IO uint32_t PRESC;  /*!< USART clock Prescaler register,           Address offset: 0x2C */
+} USART_TypeDef;
+
+/**
+  * @brief Single Wire Protocol Master Interface SPWMI
+  */
+typedef struct
+{
+  __IO uint32_t CR;          /*!< SWPMI Configuration/Control register,     Address offset: 0x00 */
+  __IO uint32_t BRR;         /*!< SWPMI bitrate register,                   Address offset: 0x04 */
+    uint32_t  RESERVED1;     /*!< Reserved, 0x08                                                 */
+  __IO uint32_t ISR;         /*!< SWPMI Interrupt and Status register,      Address offset: 0x0C */
+  __IO uint32_t ICR;         /*!< SWPMI Interrupt Flag Clear register,      Address offset: 0x10 */
+  __IO uint32_t IER;         /*!< SWPMI Interrupt Enable register,          Address offset: 0x14 */
+  __IO uint32_t RFL;         /*!< SWPMI Receive Frame Length register,      Address offset: 0x18 */
+  __IO uint32_t TDR;         /*!< SWPMI Transmit data register,             Address offset: 0x1C */
+  __IO uint32_t RDR;         /*!< SWPMI Receive data register,              Address offset: 0x20 */
+  __IO uint32_t OR;          /*!< SWPMI Option register,                    Address offset: 0x24 */
+} SWPMI_TypeDef;
+
+/**
+  * @brief Window WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
+} WWDG_TypeDef;
+
+
+/**
+  * @brief RAM_ECC_Specific_Registers
+  */
+typedef struct
+{
+  __IO uint32_t CR;           /*!< RAMECC monitor configuration register          */
+  __IO uint32_t SR;           /*!< RAMECC monitor status register                 */
+  __IO uint32_t FAR;          /*!< RAMECC monitor failing address register        */
+  __IO uint32_t FDRL;         /*!< RAMECC monitor failing data low register       */
+  __IO uint32_t FDRH;         /*!< RAMECC monitor failing data high register      */
+  __IO uint32_t FECR;         /*!< RAMECC monitor failing ECC error code register */
+} RAMECC_MonitorTypeDef;
+
+typedef struct
+{
+  __IO uint32_t IER;          /*!< RAMECC interrupt enable register */
+} RAMECC_TypeDef;
+/**
+  * @}
+  */
+
+
+
+/**
+  * @brief High resolution Timer (HRTIM)
+  */
+/* HRTIM master registers definition */
+typedef struct
+{
+  __IO uint32_t MCR;            /*!< HRTIM Master Timer control register,                     Address offset: 0x00 */
+  __IO uint32_t MISR;           /*!< HRTIM Master Timer interrupt status register,            Address offset: 0x04 */
+  __IO uint32_t MICR;           /*!< HRTIM Master Timer interupt clear register,              Address offset: 0x08 */
+  __IO uint32_t MDIER;          /*!< HRTIM Master Timer DMA/interrupt enable register         Address offset: 0x0C */
+  __IO uint32_t MCNTR;          /*!< HRTIM Master Timer counter register,                     Address offset: 0x10 */
+  __IO uint32_t MPER;           /*!< HRTIM Master Timer period register,                      Address offset: 0x14 */
+  __IO uint32_t MREP;           /*!< HRTIM Master Timer repetition register,                  Address offset: 0x18 */
+  __IO uint32_t MCMP1R;         /*!< HRTIM Master Timer compare 1 register,                   Address offset: 0x1C */
+  uint32_t      RESERVED0;     /*!< Reserved,                                                                 0x20 */
+  __IO uint32_t MCMP2R;         /*!< HRTIM Master Timer compare 2 register,                   Address offset: 0x24 */
+  __IO uint32_t MCMP3R;         /*!< HRTIM Master Timer compare 3 register,                   Address offset: 0x28 */
+  __IO uint32_t MCMP4R;         /*!< HRTIM Master Timer compare 4 register,                   Address offset: 0x2C */
+  uint32_t      RESERVED1[20];  /*!< Reserved,                                                          0x30..0x7C */
+}HRTIM_Master_TypeDef;
+
+/* HRTIM Timer A to E registers definition */
+typedef struct
+{
+  __IO uint32_t TIMxCR;     /*!< HRTIM Timerx control register,                              Address offset: 0x00 */
+  __IO uint32_t TIMxISR;    /*!< HRTIM Timerx interrupt status register,                     Address offset: 0x04 */
+  __IO uint32_t TIMxICR;    /*!< HRTIM Timerx interrupt clear register,                      Address offset: 0x08 */
+  __IO uint32_t TIMxDIER;   /*!< HRTIM Timerx DMA/interrupt enable register,                 Address offset: 0x0C */
+  __IO uint32_t CNTxR;      /*!< HRTIM Timerx counter register,                              Address offset: 0x10 */
+  __IO uint32_t PERxR;      /*!< HRTIM Timerx period register,                               Address offset: 0x14 */
+  __IO uint32_t REPxR;      /*!< HRTIM Timerx repetition register,                           Address offset: 0x18 */
+  __IO uint32_t CMP1xR;     /*!< HRTIM Timerx compare 1 register,                            Address offset: 0x1C */
+  __IO uint32_t CMP1CxR;    /*!< HRTIM Timerx compare 1 compound register,                   Address offset: 0x20 */
+  __IO uint32_t CMP2xR;     /*!< HRTIM Timerx compare 2 register,                            Address offset: 0x24 */
+  __IO uint32_t CMP3xR;     /*!< HRTIM Timerx compare 3 register,                            Address offset: 0x28 */
+  __IO uint32_t CMP4xR;     /*!< HRTIM Timerx compare 4 register,                            Address offset: 0x2C */
+  __IO uint32_t CPT1xR;     /*!< HRTIM Timerx capture 1 register,                            Address offset: 0x30 */
+  __IO uint32_t CPT2xR;     /*!< HRTIM Timerx capture 2 register,                            Address offset: 0x34 */
+  __IO uint32_t DTxR;       /*!< HRTIM Timerx dead time register,                            Address offset: 0x38 */
+  __IO uint32_t SETx1R;     /*!< HRTIM Timerx output 1 set register,                         Address offset: 0x3C */
+  __IO uint32_t RSTx1R;     /*!< HRTIM Timerx output 1 reset register,                       Address offset: 0x40 */
+  __IO uint32_t SETx2R;     /*!< HRTIM Timerx output 2 set register,                         Address offset: 0x44 */
+  __IO uint32_t RSTx2R;     /*!< HRTIM Timerx output 2 reset register,                       Address offset: 0x48 */
+  __IO uint32_t EEFxR1;     /*!< HRTIM Timerx external event filtering 1 register,           Address offset: 0x4C */
+  __IO uint32_t EEFxR2;     /*!< HRTIM Timerx external event filtering 2 register,           Address offset: 0x50 */
+  __IO uint32_t RSTxR;      /*!< HRTIM Timerx Reset register,                                Address offset: 0x54 */
+  __IO uint32_t CHPxR;      /*!< HRTIM Timerx Chopper register,                              Address offset: 0x58 */
+  __IO uint32_t CPT1xCR;    /*!< HRTIM Timerx Capture 1 register,                            Address offset: 0x5C */
+  __IO uint32_t CPT2xCR;    /*!< HRTIM Timerx Capture 2 register,                            Address offset: 0x60 */
+  __IO uint32_t OUTxR;      /*!< HRTIM Timerx Output register,                               Address offset: 0x64 */
+  __IO uint32_t FLTxR;      /*!< HRTIM Timerx Fault register,                                Address offset: 0x68 */
+  uint32_t      RESERVED0[5];  /*!< Reserved,                                                          0x6C..0x7C */
+}HRTIM_Timerx_TypeDef;
+
+/* HRTIM common register definition */
+typedef struct
+{
+  __IO uint32_t CR1;        /*!< HRTIM control register1,                                    Address offset: 0x00 */
+  __IO uint32_t CR2;        /*!< HRTIM control register2,                                    Address offset: 0x04 */
+  __IO uint32_t ISR;        /*!< HRTIM interrupt status register,                            Address offset: 0x08 */
+  __IO uint32_t ICR;        /*!< HRTIM interrupt clear register,                             Address offset: 0x0C */
+  __IO uint32_t IER;        /*!< HRTIM interrupt enable register,                            Address offset: 0x10 */
+  __IO uint32_t OENR;       /*!< HRTIM Output enable register,                               Address offset: 0x14 */
+  __IO uint32_t ODISR;      /*!< HRTIM Output disable register,                              Address offset: 0x18 */
+  __IO uint32_t ODSR;       /*!< HRTIM Output disable status register,                       Address offset: 0x1C */
+  __IO uint32_t BMCR;       /*!< HRTIM Burst mode control register,                          Address offset: 0x20 */
+  __IO uint32_t BMTRGR;     /*!< HRTIM Busrt mode trigger register,                          Address offset: 0x24 */
+  __IO uint32_t BMCMPR;     /*!< HRTIM Burst mode compare register,                          Address offset: 0x28 */
+  __IO uint32_t BMPER;      /*!< HRTIM Burst mode period register,                           Address offset: 0x2C */
+  __IO uint32_t EECR1;      /*!< HRTIM Timer external event control register1,               Address offset: 0x30 */
+  __IO uint32_t EECR2;      /*!< HRTIM Timer external event control register2,               Address offset: 0x34 */
+  __IO uint32_t EECR3;      /*!< HRTIM Timer external event control register3,               Address offset: 0x38 */
+  __IO uint32_t ADC1R;      /*!< HRTIM ADC Trigger 1 register,                               Address offset: 0x3C */
+  __IO uint32_t ADC2R;      /*!< HRTIM ADC Trigger 2 register,                               Address offset: 0x40 */
+  __IO uint32_t ADC3R;      /*!< HRTIM ADC Trigger 3 register,                               Address offset: 0x44 */
+  __IO uint32_t ADC4R;      /*!< HRTIM ADC Trigger 4 register,                               Address offset: 0x48 */
+  __IO uint32_t RESERVED0;  /*!< Reserved,                                                   Address offset: 0x4C */
+  __IO uint32_t FLTINR1;    /*!< HRTIM Fault input register1,                                Address offset: 0x50 */
+  __IO uint32_t FLTINR2;    /*!< HRTIM Fault input register2,                                Address offset: 0x54 */
+  __IO uint32_t BDMUPR;     /*!< HRTIM Burst DMA Master Timer update register,               Address offset: 0x58 */
+  __IO uint32_t BDTAUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x5C */
+  __IO uint32_t BDTBUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x60 */
+  __IO uint32_t BDTCUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x64 */
+  __IO uint32_t BDTDUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x68 */
+  __IO uint32_t BDTEUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x6C */
+  __IO uint32_t BDMADR;     /*!< HRTIM Burst DMA Master Data register,                       Address offset: 0x70 */
+}HRTIM_Common_TypeDef;
+
+/* HRTIM  register definition */
+typedef struct {
+  HRTIM_Master_TypeDef sMasterRegs;
+  HRTIM_Timerx_TypeDef sTimerxRegs[5];
+  uint32_t             RESERVED0[32];
+  HRTIM_Common_TypeDef sCommonRegs;
+}HRTIM_TypeDef;
+/**
+  * @brief RNG
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
+} RNG_TypeDef;
+
+/**
+  * @brief MDIOS
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;
+  __IO uint32_t WRFR;
+  __IO uint32_t CWRFR;
+  __IO uint32_t RDFR;
+  __IO uint32_t CRDFR;
+  __IO uint32_t SR;
+  __IO uint32_t CLRFR;
+  uint32_t RESERVED[57];
+  __IO uint32_t DINR0;
+  __IO uint32_t DINR1;
+  __IO uint32_t DINR2;
+  __IO uint32_t DINR3;
+  __IO uint32_t DINR4;
+  __IO uint32_t DINR5;
+  __IO uint32_t DINR6;
+  __IO uint32_t DINR7;
+  __IO uint32_t DINR8;
+  __IO uint32_t DINR9;
+  __IO uint32_t DINR10;
+  __IO uint32_t DINR11;
+  __IO uint32_t DINR12;
+  __IO uint32_t DINR13;
+  __IO uint32_t DINR14;
+  __IO uint32_t DINR15;
+  __IO uint32_t DINR16;
+  __IO uint32_t DINR17;
+  __IO uint32_t DINR18;
+  __IO uint32_t DINR19;
+  __IO uint32_t DINR20;
+  __IO uint32_t DINR21;
+  __IO uint32_t DINR22;
+  __IO uint32_t DINR23;
+  __IO uint32_t DINR24;
+  __IO uint32_t DINR25;
+  __IO uint32_t DINR26;
+  __IO uint32_t DINR27;
+  __IO uint32_t DINR28;
+  __IO uint32_t DINR29;
+  __IO uint32_t DINR30;
+  __IO uint32_t DINR31;
+  __IO uint32_t DOUTR0;
+  __IO uint32_t DOUTR1;
+  __IO uint32_t DOUTR2;
+  __IO uint32_t DOUTR3;
+  __IO uint32_t DOUTR4;
+  __IO uint32_t DOUTR5;
+  __IO uint32_t DOUTR6;
+  __IO uint32_t DOUTR7;
+  __IO uint32_t DOUTR8;
+  __IO uint32_t DOUTR9;
+  __IO uint32_t DOUTR10;
+  __IO uint32_t DOUTR11;
+  __IO uint32_t DOUTR12;
+  __IO uint32_t DOUTR13;
+  __IO uint32_t DOUTR14;
+  __IO uint32_t DOUTR15;
+  __IO uint32_t DOUTR16;
+  __IO uint32_t DOUTR17;
+  __IO uint32_t DOUTR18;
+  __IO uint32_t DOUTR19;
+  __IO uint32_t DOUTR20;
+  __IO uint32_t DOUTR21;
+  __IO uint32_t DOUTR22;
+  __IO uint32_t DOUTR23;
+  __IO uint32_t DOUTR24;
+  __IO uint32_t DOUTR25;
+  __IO uint32_t DOUTR26;
+  __IO uint32_t DOUTR27;
+  __IO uint32_t DOUTR28;
+  __IO uint32_t DOUTR29;
+  __IO uint32_t DOUTR30;
+  __IO uint32_t DOUTR31;
+} MDIOS_TypeDef;
+
+
+/**
+  * @brief USB_OTG_Core_Registers
+  */
+typedef struct
+{
+ __IO uint32_t GOTGCTL;               /*!< USB_OTG Control and Status Register          000h */
+  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */
+  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */
+  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */
+  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */
+  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */
+  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */
+  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */
+  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */
+  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */
+  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */
+  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */
+  uint32_t Reserved30[2];             /*!< Reserved                                     030h */
+  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */
+  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */
+  __IO uint32_t GSNPSID;              /* USB_OTG core ID                                040h*/
+  __IO uint32_t GHWCFG1;              /* User HW config1                                044h*/
+  __IO uint32_t GHWCFG2;              /* User HW config2                                048h*/
+  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */
+  uint32_t  Reserved6;                /*!< Reserved                                     050h */
+  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */
+  __IO uint32_t GPWRDN;               /*!< Power Down Register                          058h */
+  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */
+   __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register       60Ch */
+    uint32_t  Reserved43[39];         /*!< Reserved                                058h-0FFh */
+  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */
+  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */
+} USB_OTG_GlobalTypeDef;
+
+
+/**
+  * @brief USB_OTG_device_Registers
+  */
+typedef struct
+{
+  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */
+  __IO uint32_t DCTL;            /*!< dev Control Register         804h */
+  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */
+  uint32_t Reserved0C;           /*!< Reserved                     80Ch */
+  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */
+  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */
+  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */
+  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */
+  uint32_t  Reserved20;          /*!< Reserved                     820h */
+  uint32_t Reserved9;            /*!< Reserved                     824h */
+  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */
+  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */
+  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */
+  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */
+  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */
+  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */
+  uint32_t Reserved40;           /*!< dedicated EP mask            840h */
+  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */
+  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */
+  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */
+} USB_OTG_DeviceTypeDef;
+
+
+/**
+  * @brief USB_OTG_IN_Endpoint-Specific_Register
+  */
+typedef struct
+{
+  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */
+  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */
+  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */
+  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */
+  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */
+  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */
+  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+
+/**
+  * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+  */
+typedef struct
+{
+  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */
+  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */
+  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */
+  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */
+  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */
+  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */
+  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
+} USB_OTG_OUTEndpointTypeDef;
+
+
+/**
+  * @brief USB_OTG_Host_Mode_Register_Structures
+  */
+typedef struct
+{
+  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */
+  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */
+  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */
+  uint32_t Reserved40C;           /*!< Reserved                             40Ch */
+  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */
+  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */
+  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */
+} USB_OTG_HostTypeDef;
+
+/**
+  * @brief USB_OTG_Host_Channel_Specific_Registers
+  */
+typedef struct
+{
+  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */
+  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */
+  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */
+  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */
+  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */
+  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */
+  uint32_t Reserved[2];           /*!< Reserved                                      */
+} USB_OTG_HostChannelTypeDef;
+/**
+  * @}
+  */
+
+
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+#define D1_ITCMRAM_BASE           (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM  */
+#define D1_ITCMICP_BASE           (0x00100000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM         */
+#define D1_DTCMRAM_BASE           (0x20000000UL) /*!< Base address of : 128KB system data RAM accessible over DTCM                            */
+#define D1_AXIFLASH_BASE          (0x08000000UL) /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI                */
+#define D1_AXIICP_BASE            (0x1FF00000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI          */
+#define D1_AXISRAM_BASE           (0x24000000UL) /*!< Base address of : (up to 512KB) system data RAM accessible over over AXI                */
+
+#define D2_AXISRAM_BASE           (0x10000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI                */
+#define D2_AHBSRAM_BASE           (0x30000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI->AHB Bridge    */
+
+#define D3_BKPSRAM_BASE           (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge                                */
+#define D3_SRAM_BASE              (0x38000000UL) /*!< Base address of : Backup SRAM(64 KB) over AXI->AHB Bridge                               */
+
+#define PERIPH_BASE               (0x40000000UL) /*!< Base address of : AHB/APB Peripherals                                                   */
+#define QSPI_BASE                 (0x90000000UL) /*!< Base address of : QSPI memories  accessible over AXI                                    */
+
+#define FLASH_BANK1_BASE          (0x08000000UL) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI                          */
+#define FLASH_BANK2_BASE          (0x08100000UL) /*!< Base address of : (up to 1 MB) Flash Bank2 accessible over AXI                          */
+#define FLASH_END                 (0x081FFFFFUL) /*!< FLASH end address                                                                       */
+
+/* Legacy define */
+#define FLASH_BASE                FLASH_BANK1_BASE
+
+/*!< Device electronic signature memory map */
+#define UID_BASE                  (0x1FF1E800UL)            /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE            (0x1FF1E880UL)            /*!< FLASH Size register base address */
+
+
+/*!< Peripheral memory map */
+#define D2_APB1PERIPH_BASE        PERIPH_BASE
+#define D2_APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
+#define D2_AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
+#define D2_AHB2PERIPH_BASE       (PERIPH_BASE + 0x08020000UL)
+
+#define D1_APB1PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)
+#define D1_AHB1PERIPH_BASE       (PERIPH_BASE + 0x12000000UL)
+
+#define D3_APB1PERIPH_BASE       (PERIPH_BASE + 0x18000000UL)
+#define D3_AHB1PERIPH_BASE       (PERIPH_BASE + 0x18020000UL)
+
+/*!< Legacy Peripheral memory map */
+#define APB1PERIPH_BASE        PERIPH_BASE
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000UL)
+
+
+/*!< D1_AHB1PERIPH peripherals */
+
+#define MDMA_BASE             (D1_AHB1PERIPH_BASE + 0x0000UL)
+#define DMA2D_BASE            (D1_AHB1PERIPH_BASE + 0x1000UL)
+#define JPGDEC_BASE           (D1_AHB1PERIPH_BASE + 0x3000UL)
+#define FLASH_R_BASE          (D1_AHB1PERIPH_BASE + 0x2000UL)
+#define FMC_R_BASE            (D1_AHB1PERIPH_BASE + 0x4000UL)
+#define QSPI_R_BASE           (D1_AHB1PERIPH_BASE + 0x5000UL)
+#define DLYB_QSPI_BASE        (D1_AHB1PERIPH_BASE + 0x6000UL)
+#define SDMMC1_BASE           (D1_AHB1PERIPH_BASE + 0x7000UL)
+#define DLYB_SDMMC1_BASE      (D1_AHB1PERIPH_BASE + 0x8000UL)
+#define RAMECC1_BASE          (D1_AHB1PERIPH_BASE + 0x9000UL)
+
+/*!< D2_AHB1PERIPH peripherals */
+
+#define DMA1_BASE               (D2_AHB1PERIPH_BASE + 0x0000UL)
+#define DMA2_BASE               (D2_AHB1PERIPH_BASE + 0x0400UL)
+#define DMAMUX1_BASE            (D2_AHB1PERIPH_BASE + 0x0800UL)
+#define ADC1_BASE               (D2_AHB1PERIPH_BASE + 0x2000UL)
+#define ADC2_BASE               (D2_AHB1PERIPH_BASE + 0x2100UL)
+#define ADC12_COMMON_BASE       (D2_AHB1PERIPH_BASE + 0x2300UL)
+#define ETH_BASE                (D2_AHB1PERIPH_BASE + 0x8000UL)
+#define ETH_MAC_BASE            (ETH_BASE)
+
+/*!< USB registers base address */
+#define USB1_OTG_HS_PERIPH_BASE              (0x40040000UL)
+#define USB2_OTG_FS_PERIPH_BASE              (0x40080000UL)
+#define USB_OTG_GLOBAL_BASE                  (0x000UL)
+#define USB_OTG_DEVICE_BASE                  (0x800UL)
+#define USB_OTG_IN_ENDPOINT_BASE             (0x900UL)
+#define USB_OTG_OUT_ENDPOINT_BASE            (0xB00UL)
+#define USB_OTG_EP_REG_SIZE                  (0x20UL)
+#define USB_OTG_HOST_BASE                    (0x400UL)
+#define USB_OTG_HOST_PORT_BASE               (0x440UL)
+#define USB_OTG_HOST_CHANNEL_BASE            (0x500UL)
+#define USB_OTG_HOST_CHANNEL_SIZE            (0x20UL)
+#define USB_OTG_PCGCCTL_BASE                 (0xE00UL)
+#define USB_OTG_FIFO_BASE                    (0x1000UL)
+#define USB_OTG_FIFO_SIZE                    (0x1000UL)
+
+/*!< D2_AHB2PERIPH peripherals */
+
+#define DCMI_BASE              (D2_AHB2PERIPH_BASE + 0x0000UL)
+#define RNG_BASE               (D2_AHB2PERIPH_BASE + 0x1800UL)
+#define SDMMC2_BASE            (D2_AHB2PERIPH_BASE + 0x2400UL)
+#define DLYB_SDMMC2_BASE       (D2_AHB2PERIPH_BASE + 0x2800UL)
+#define RAMECC2_BASE           (D2_AHB2PERIPH_BASE + 0x3000UL)
+
+/*!< D3_AHB1PERIPH peripherals */
+#define GPIOA_BASE            (D3_AHB1PERIPH_BASE + 0x0000UL)
+#define GPIOB_BASE            (D3_AHB1PERIPH_BASE + 0x0400UL)
+#define GPIOC_BASE            (D3_AHB1PERIPH_BASE + 0x0800UL)
+#define GPIOD_BASE            (D3_AHB1PERIPH_BASE + 0x0C00UL)
+#define GPIOE_BASE            (D3_AHB1PERIPH_BASE + 0x1000UL)
+#define GPIOF_BASE            (D3_AHB1PERIPH_BASE + 0x1400UL)
+#define GPIOG_BASE            (D3_AHB1PERIPH_BASE + 0x1800UL)
+#define GPIOH_BASE            (D3_AHB1PERIPH_BASE + 0x1C00UL)
+#define GPIOI_BASE            (D3_AHB1PERIPH_BASE + 0x2000UL)
+#define GPIOJ_BASE            (D3_AHB1PERIPH_BASE + 0x2400UL)
+#define GPIOK_BASE            (D3_AHB1PERIPH_BASE + 0x2800UL)
+#define RCC_BASE              (D3_AHB1PERIPH_BASE + 0x4400UL)
+#define PWR_BASE              (D3_AHB1PERIPH_BASE + 0x4800UL)
+#define CRC_BASE              (D3_AHB1PERIPH_BASE + 0x4C00UL)
+#define BDMA_BASE             (D3_AHB1PERIPH_BASE + 0x5400UL)
+#define DMAMUX2_BASE          (D3_AHB1PERIPH_BASE + 0x5800UL)
+#define ADC3_BASE             (D3_AHB1PERIPH_BASE + 0x6000UL)
+#define ADC3_COMMON_BASE      (D3_AHB1PERIPH_BASE + 0x6300UL)
+#define HSEM_BASE             (D3_AHB1PERIPH_BASE + 0x6400UL)
+#define RAMECC3_BASE          (D3_AHB1PERIPH_BASE + 0x7000UL)
+
+/*!< D1_APB1PERIPH peripherals */
+#define LTDC_BASE             (D1_APB1PERIPH_BASE + 0x1000UL)
+#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84UL)
+#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104UL)
+#define WWDG1_BASE            (D1_APB1PERIPH_BASE + 0x3000UL)
+
+/*!< D2_APB1PERIPH peripherals */
+#define TIM2_BASE             (D2_APB1PERIPH_BASE + 0x0000UL)
+#define TIM3_BASE             (D2_APB1PERIPH_BASE + 0x0400UL)
+#define TIM4_BASE             (D2_APB1PERIPH_BASE + 0x0800UL)
+#define TIM5_BASE             (D2_APB1PERIPH_BASE + 0x0C00UL)
+#define TIM6_BASE             (D2_APB1PERIPH_BASE + 0x1000UL)
+#define TIM7_BASE             (D2_APB1PERIPH_BASE + 0x1400UL)
+#define TIM12_BASE            (D2_APB1PERIPH_BASE + 0x1800UL)
+#define TIM13_BASE            (D2_APB1PERIPH_BASE + 0x1C00UL)
+#define TIM14_BASE            (D2_APB1PERIPH_BASE + 0x2000UL)
+#define LPTIM1_BASE           (D2_APB1PERIPH_BASE + 0x2400UL)
+
+
+#define SPI2_BASE             (D2_APB1PERIPH_BASE + 0x3800UL)
+#define SPI3_BASE             (D2_APB1PERIPH_BASE + 0x3C00UL)
+#define SPDIFRX_BASE          (D2_APB1PERIPH_BASE + 0x4000UL)
+#define USART2_BASE           (D2_APB1PERIPH_BASE + 0x4400UL)
+#define USART3_BASE           (D2_APB1PERIPH_BASE + 0x4800UL)
+#define UART4_BASE            (D2_APB1PERIPH_BASE + 0x4C00UL)
+#define UART5_BASE            (D2_APB1PERIPH_BASE + 0x5000UL)
+#define I2C1_BASE             (D2_APB1PERIPH_BASE + 0x5400UL)
+#define I2C2_BASE             (D2_APB1PERIPH_BASE + 0x5800UL)
+#define I2C3_BASE             (D2_APB1PERIPH_BASE + 0x5C00UL)
+#define CEC_BASE              (D2_APB1PERIPH_BASE + 0x6C00UL)
+#define DAC1_BASE             (D2_APB1PERIPH_BASE + 0x7400UL)
+#define UART7_BASE            (D2_APB1PERIPH_BASE + 0x7800UL)
+#define UART8_BASE            (D2_APB1PERIPH_BASE + 0x7C00UL)
+#define CRS_BASE              (D2_APB1PERIPH_BASE + 0x8400UL)
+#define SWPMI1_BASE           (D2_APB1PERIPH_BASE + 0x8800UL)
+#define OPAMP_BASE            (D2_APB1PERIPH_BASE + 0x9000UL)
+#define OPAMP1_BASE           (D2_APB1PERIPH_BASE + 0x9000UL)
+#define OPAMP2_BASE           (D2_APB1PERIPH_BASE + 0x9010UL)
+#define MDIOS_BASE            (D2_APB1PERIPH_BASE + 0x9400UL)
+#define FDCAN1_BASE           (D2_APB1PERIPH_BASE + 0xA000UL)
+#define FDCAN2_BASE           (D2_APB1PERIPH_BASE + 0xA400UL)
+#define FDCAN_CCU_BASE        (D2_APB1PERIPH_BASE + 0xA800UL)
+#define SRAMCAN_BASE          (D2_APB1PERIPH_BASE + 0xAC00UL)
+
+/*!< D2_APB2PERIPH peripherals */
+
+#define TIM1_BASE             (D2_APB2PERIPH_BASE + 0x0000UL)
+#define TIM8_BASE             (D2_APB2PERIPH_BASE + 0x0400UL)
+#define USART1_BASE           (D2_APB2PERIPH_BASE + 0x1000UL)
+#define USART6_BASE           (D2_APB2PERIPH_BASE + 0x1400UL)
+#define SPI1_BASE             (D2_APB2PERIPH_BASE + 0x3000UL)
+#define SPI4_BASE             (D2_APB2PERIPH_BASE + 0x3400UL)
+#define TIM15_BASE            (D2_APB2PERIPH_BASE + 0x4000UL)
+#define TIM16_BASE            (D2_APB2PERIPH_BASE + 0x4400UL)
+#define TIM17_BASE            (D2_APB2PERIPH_BASE + 0x4800UL)
+#define SPI5_BASE             (D2_APB2PERIPH_BASE + 0x5000UL)
+#define SAI1_BASE             (D2_APB2PERIPH_BASE + 0x5800UL)
+#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004UL)
+#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024UL)
+#define SAI2_BASE             (D2_APB2PERIPH_BASE + 0x5C00UL)
+#define SAI2_Block_A_BASE     (SAI2_BASE + 0x004UL)
+#define SAI2_Block_B_BASE     (SAI2_BASE + 0x024UL)
+#define SAI3_BASE             (D2_APB2PERIPH_BASE + 0x6000UL)
+#define SAI3_Block_A_BASE     (SAI3_BASE + 0x004UL)
+#define SAI3_Block_B_BASE     (SAI3_BASE + 0x024UL)
+#define DFSDM1_BASE           (D2_APB2PERIPH_BASE + 0x7000UL)
+#define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x00UL)
+#define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x20UL)
+#define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x40UL)
+#define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x60UL)
+#define DFSDM1_Channel4_BASE  (DFSDM1_BASE + 0x80UL)
+#define DFSDM1_Channel5_BASE  (DFSDM1_BASE + 0xA0UL)
+#define DFSDM1_Channel6_BASE  (DFSDM1_BASE + 0xC0UL)
+#define DFSDM1_Channel7_BASE  (DFSDM1_BASE + 0xE0UL)
+#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100UL)
+#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180UL)
+#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200UL)
+#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280UL)
+#define HRTIM1_BASE           (D2_APB2PERIPH_BASE + 0x7400UL)
+#define HRTIM1_TIMA_BASE      (HRTIM1_BASE + 0x00000080UL)
+#define HRTIM1_TIMB_BASE      (HRTIM1_BASE + 0x00000100UL)
+#define HRTIM1_TIMC_BASE      (HRTIM1_BASE + 0x00000180UL)
+#define HRTIM1_TIMD_BASE      (HRTIM1_BASE + 0x00000200UL)
+#define HRTIM1_TIME_BASE      (HRTIM1_BASE + 0x00000280UL)
+#define HRTIM1_COMMON_BASE    (HRTIM1_BASE + 0x00000380UL)
+
+
+/*!< D3_APB1PERIPH peripherals */
+#define EXTI_BASE             (D3_APB1PERIPH_BASE + 0x0000UL)
+#define EXTI_D1_BASE          (EXTI_BASE + 0x0080UL)
+#define EXTI_D2_BASE          (EXTI_BASE + 0x00C0UL)
+#define SYSCFG_BASE           (D3_APB1PERIPH_BASE + 0x0400UL)
+#define LPUART1_BASE          (D3_APB1PERIPH_BASE + 0x0C00UL)
+#define SPI6_BASE             (D3_APB1PERIPH_BASE + 0x1400UL)
+#define I2C4_BASE             (D3_APB1PERIPH_BASE + 0x1C00UL)
+#define LPTIM2_BASE           (D3_APB1PERIPH_BASE + 0x2400UL)
+#define LPTIM3_BASE           (D3_APB1PERIPH_BASE + 0x2800UL)
+#define LPTIM4_BASE           (D3_APB1PERIPH_BASE + 0x2C00UL)
+#define LPTIM5_BASE           (D3_APB1PERIPH_BASE + 0x3000UL)
+#define COMP12_BASE           (D3_APB1PERIPH_BASE + 0x3800UL)
+#define COMP1_BASE            (COMP12_BASE + 0x0CUL)
+#define COMP2_BASE            (COMP12_BASE + 0x10UL)
+#define VREFBUF_BASE          (D3_APB1PERIPH_BASE + 0x3C00UL)
+#define RTC_BASE              (D3_APB1PERIPH_BASE + 0x4000UL)
+#define IWDG1_BASE            (D3_APB1PERIPH_BASE + 0x4800UL)
+
+
+#define SAI4_BASE             (D3_APB1PERIPH_BASE + 0x5400UL)
+#define SAI4_Block_A_BASE     (SAI4_BASE + 0x004UL)
+#define SAI4_Block_B_BASE     (SAI4_BASE + 0x024UL)
+
+
+
+
+#define BDMA_Channel0_BASE    (BDMA_BASE + 0x0008UL)
+#define BDMA_Channel1_BASE    (BDMA_BASE + 0x001CUL)
+#define BDMA_Channel2_BASE    (BDMA_BASE + 0x0030UL)
+#define BDMA_Channel3_BASE    (BDMA_BASE + 0x0044UL)
+#define BDMA_Channel4_BASE    (BDMA_BASE + 0x0058UL)
+#define BDMA_Channel5_BASE    (BDMA_BASE + 0x006CUL)
+#define BDMA_Channel6_BASE    (BDMA_BASE + 0x0080UL)
+#define BDMA_Channel7_BASE    (BDMA_BASE + 0x0094UL)
+
+#define DMAMUX2_Channel0_BASE    (DMAMUX2_BASE)
+#define DMAMUX2_Channel1_BASE    (DMAMUX2_BASE + 0x0004UL)
+#define DMAMUX2_Channel2_BASE    (DMAMUX2_BASE + 0x0008UL)
+#define DMAMUX2_Channel3_BASE    (DMAMUX2_BASE + 0x000CUL)
+#define DMAMUX2_Channel4_BASE    (DMAMUX2_BASE + 0x0010UL)
+#define DMAMUX2_Channel5_BASE    (DMAMUX2_BASE + 0x0014UL)
+#define DMAMUX2_Channel6_BASE    (DMAMUX2_BASE + 0x0018UL)
+#define DMAMUX2_Channel7_BASE    (DMAMUX2_BASE + 0x001CUL)
+
+#define DMAMUX2_RequestGenerator0_BASE  (DMAMUX2_BASE + 0x0100UL)
+#define DMAMUX2_RequestGenerator1_BASE  (DMAMUX2_BASE + 0x0104UL)
+#define DMAMUX2_RequestGenerator2_BASE  (DMAMUX2_BASE + 0x0108UL)
+#define DMAMUX2_RequestGenerator3_BASE  (DMAMUX2_BASE + 0x010CUL)
+#define DMAMUX2_RequestGenerator4_BASE  (DMAMUX2_BASE + 0x0110UL)
+#define DMAMUX2_RequestGenerator5_BASE  (DMAMUX2_BASE + 0x0114UL)
+#define DMAMUX2_RequestGenerator6_BASE  (DMAMUX2_BASE + 0x0118UL)
+#define DMAMUX2_RequestGenerator7_BASE  (DMAMUX2_BASE + 0x011CUL)
+
+#define DMAMUX2_ChannelStatus_BASE      (DMAMUX2_BASE + 0x0080UL)
+#define DMAMUX2_RequestGenStatus_BASE   (DMAMUX2_BASE + 0x0140UL)
+
+#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)
+#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)
+#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)
+#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)
+#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)
+#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)
+#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)
+#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)
+
+#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)
+#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)
+#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)
+#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)
+#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)
+#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)
+#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)
+#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)
+
+#define DMAMUX1_Channel0_BASE    (DMAMUX1_BASE)
+#define DMAMUX1_Channel1_BASE    (DMAMUX1_BASE + 0x0004UL)
+#define DMAMUX1_Channel2_BASE    (DMAMUX1_BASE + 0x0008UL)
+#define DMAMUX1_Channel3_BASE    (DMAMUX1_BASE + 0x000CUL)
+#define DMAMUX1_Channel4_BASE    (DMAMUX1_BASE + 0x0010UL)
+#define DMAMUX1_Channel5_BASE    (DMAMUX1_BASE + 0x0014UL)
+#define DMAMUX1_Channel6_BASE    (DMAMUX1_BASE + 0x0018UL)
+#define DMAMUX1_Channel7_BASE    (DMAMUX1_BASE + 0x001CUL)
+#define DMAMUX1_Channel8_BASE    (DMAMUX1_BASE + 0x0020UL)
+#define DMAMUX1_Channel9_BASE    (DMAMUX1_BASE + 0x0024UL)
+#define DMAMUX1_Channel10_BASE   (DMAMUX1_BASE + 0x0028UL)
+#define DMAMUX1_Channel11_BASE   (DMAMUX1_BASE + 0x002CUL)
+#define DMAMUX1_Channel12_BASE   (DMAMUX1_BASE + 0x0030UL)
+#define DMAMUX1_Channel13_BASE   (DMAMUX1_BASE + 0x0034UL)
+#define DMAMUX1_Channel14_BASE   (DMAMUX1_BASE + 0x0038UL)
+#define DMAMUX1_Channel15_BASE   (DMAMUX1_BASE + 0x003CUL)
+
+#define DMAMUX1_RequestGenerator0_BASE  (DMAMUX1_BASE + 0x0100UL)
+#define DMAMUX1_RequestGenerator1_BASE  (DMAMUX1_BASE + 0x0104UL)
+#define DMAMUX1_RequestGenerator2_BASE  (DMAMUX1_BASE + 0x0108UL)
+#define DMAMUX1_RequestGenerator3_BASE  (DMAMUX1_BASE + 0x010CUL)
+#define DMAMUX1_RequestGenerator4_BASE  (DMAMUX1_BASE + 0x0110UL)
+#define DMAMUX1_RequestGenerator5_BASE  (DMAMUX1_BASE + 0x0114UL)
+#define DMAMUX1_RequestGenerator6_BASE  (DMAMUX1_BASE + 0x0118UL)
+#define DMAMUX1_RequestGenerator7_BASE  (DMAMUX1_BASE + 0x011CUL)
+
+#define DMAMUX1_ChannelStatus_BASE      (DMAMUX1_BASE + 0x0080UL)
+#define DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x0140UL)
+
+/*!< FMC Banks registers base  address */
+#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000UL)
+#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104UL)
+#define FMC_Bank2_R_BASE      (FMC_R_BASE + 0x0060UL)
+#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080UL)
+#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140UL)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE           (0x5C001000UL)
+
+#define MDMA_Channel0_BASE    (MDMA_BASE + 0x00000040UL)
+#define MDMA_Channel1_BASE    (MDMA_BASE + 0x00000080UL)
+#define MDMA_Channel2_BASE    (MDMA_BASE + 0x000000C0UL)
+#define MDMA_Channel3_BASE    (MDMA_BASE + 0x00000100UL)
+#define MDMA_Channel4_BASE    (MDMA_BASE + 0x00000140UL)
+#define MDMA_Channel5_BASE    (MDMA_BASE + 0x00000180UL)
+#define MDMA_Channel6_BASE    (MDMA_BASE + 0x000001C0UL)
+#define MDMA_Channel7_BASE    (MDMA_BASE + 0x00000200UL)
+#define MDMA_Channel8_BASE    (MDMA_BASE + 0x00000240UL)
+#define MDMA_Channel9_BASE    (MDMA_BASE + 0x00000280UL)
+#define MDMA_Channel10_BASE   (MDMA_BASE + 0x000002C0UL)
+#define MDMA_Channel11_BASE   (MDMA_BASE + 0x00000300UL)
+#define MDMA_Channel12_BASE   (MDMA_BASE + 0x00000340UL)
+#define MDMA_Channel13_BASE   (MDMA_BASE + 0x00000380UL)
+#define MDMA_Channel14_BASE   (MDMA_BASE + 0x000003C0UL)
+#define MDMA_Channel15_BASE   (MDMA_BASE + 0x00000400UL)
+
+#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL)
+#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL)
+#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL)
+#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL)
+#define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL)
+
+#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL)
+#define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL)
+#define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL)
+#define RAMECC2_Monitor4_BASE (RAMECC2_BASE + 0x80UL)
+#define RAMECC2_Monitor5_BASE (RAMECC2_BASE + 0xA0UL)
+
+#define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL)
+#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_declaration
+  * @{
+  */
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
+#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
+#define VREFBUF             ((VREFBUF_TypeDef *) VREFBUF_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG1               ((WWDG_TypeDef *) WWDG1_BASE)
+
+
+#define IWDG1               ((IWDG_TypeDef *) IWDG1_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
+#define SPI4                ((SPI_TypeDef *) SPI4_BASE)
+#define SPI5                ((SPI_TypeDef *) SPI5_BASE)
+#define SPI6                ((SPI_TypeDef *) SPI6_BASE)
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define USART3              ((USART_TypeDef *) USART3_BASE)
+#define USART6              ((USART_TypeDef *) USART6_BASE)
+#define UART7               ((USART_TypeDef *) UART7_BASE)
+#define UART8               ((USART_TypeDef *) UART8_BASE)
+#define CRS                 ((CRS_TypeDef *) CRS_BASE)
+#define UART4               ((USART_TypeDef *) UART4_BASE)
+#define UART5               ((USART_TypeDef *) UART5_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
+#define I2C4                ((I2C_TypeDef *) I2C4_BASE)
+#define FDCAN1              ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
+#define FDCAN2              ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
+#define FDCAN_CCU           ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)
+#define CEC                 ((CEC_TypeDef *) CEC_BASE)
+#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+#define DAC1                ((DAC_TypeDef *) DAC1_BASE)
+#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
+#define SWPMI1              ((SWPMI_TypeDef *) SWPMI1_BASE)
+#define LPTIM2              ((LPTIM_TypeDef *) LPTIM2_BASE)
+#define LPTIM3              ((LPTIM_TypeDef *) LPTIM3_BASE)
+#define LPTIM4              ((LPTIM_TypeDef *) LPTIM4_BASE)
+#define LPTIM5              ((LPTIM_TypeDef *) LPTIM5_BASE)
+
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define COMP12              ((COMPOPT_TypeDef *) COMP12_BASE)
+#define COMP1               ((COMP_TypeDef *) COMP1_BASE)
+#define COMP2               ((COMP_TypeDef *) COMP2_BASE)
+#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP2_BASE)
+#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
+#define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)
+#define OPAMP2              ((OPAMP_TypeDef *) OPAMP2_BASE)
+
+
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define EXTI_D1             ((EXTI_Core_TypeDef *) EXTI_D1_BASE)
+#define EXTI_D2             ((EXTI_Core_TypeDef *) EXTI_D2_BASE)
+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17               ((TIM_TypeDef *) TIM17_BASE)
+#define HRTIM1              ((HRTIM_TypeDef *) HRTIM1_BASE)
+#define HRTIM1_TIMA         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE)
+#define HRTIM1_TIMB         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE)
+#define HRTIM1_TIMC         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE)
+#define HRTIM1_TIMD         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE)
+#define HRTIM1_TIME         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE)
+#define HRTIM1_COMMON       ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)
+#define SAI1                ((SAI_TypeDef *) SAI1_BASE)
+#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
+#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+#define SAI2                ((SAI_TypeDef *) SAI2_BASE)
+#define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
+#define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
+#define SAI3                ((SAI_TypeDef *) SAI3_BASE)
+#define SAI3_Block_A        ((SAI_Block_TypeDef *)SAI3_Block_A_BASE)
+#define SAI3_Block_B        ((SAI_Block_TypeDef *)SAI3_Block_B_BASE)
+#define SAI4                ((SAI_TypeDef *) SAI4_BASE)
+#define SAI4_Block_A        ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)
+#define SAI4_Block_B        ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)
+
+#define SPDIFRX             ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
+#define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
+#define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
+#define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
+#define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
+#define DFSDM1_Channel4     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
+#define DFSDM1_Channel5     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
+#define DFSDM1_Channel6     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
+#define DFSDM1_Channel7     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
+#define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
+#define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
+#define DFSDM1_Filter2      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
+#define DFSDM1_Filter3      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
+#define DMA2D               ((DMA2D_TypeDef *) DMA2D_BASE)
+#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
+#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)
+#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)
+
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
+#define ADC3_COMMON         ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)
+#define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
+
+#define RNG                 ((RNG_TypeDef *) RNG_BASE)
+#define SDMMC2              ((SDMMC_TypeDef *) SDMMC2_BASE)
+#define DLYB_SDMMC2         ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)
+
+#define BDMA                ((BDMA_TypeDef *) BDMA_BASE)
+#define BDMA_Channel0       ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)
+#define BDMA_Channel1       ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)
+#define BDMA_Channel2       ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)
+#define BDMA_Channel3       ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)
+#define BDMA_Channel4       ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)
+#define BDMA_Channel5       ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)
+#define BDMA_Channel6       ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)
+#define BDMA_Channel7       ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)
+
+#define RAMECC1              ((RAMECC_TypeDef *)RAMECC1_BASE)
+#define RAMECC1_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)
+#define RAMECC1_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)
+#define RAMECC1_Monitor3     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)
+#define RAMECC1_Monitor4     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)
+#define RAMECC1_Monitor5     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)
+
+#define RAMECC2              ((RAMECC_TypeDef *)RAMECC2_BASE)
+#define RAMECC2_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)
+#define RAMECC2_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)
+#define RAMECC2_Monitor3     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)
+#define RAMECC2_Monitor4     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor4_BASE)
+#define RAMECC2_Monitor5     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor5_BASE)
+
+#define RAMECC3              ((RAMECC_TypeDef *)RAMECC3_BASE)
+#define RAMECC3_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)
+#define RAMECC3_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)
+
+#define DMAMUX2                ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)
+#define DMAMUX2_Channel0       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)
+#define DMAMUX2_Channel1       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)
+#define DMAMUX2_Channel2       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)
+#define DMAMUX2_Channel3       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)
+#define DMAMUX2_Channel4       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)
+#define DMAMUX2_Channel5       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)
+#define DMAMUX2_Channel6       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)
+#define DMAMUX2_Channel7       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)
+
+
+#define DMAMUX2_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)
+#define DMAMUX2_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)
+#define DMAMUX2_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)
+#define DMAMUX2_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)
+#define DMAMUX2_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)
+#define DMAMUX2_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)
+#define DMAMUX2_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)
+#define DMAMUX2_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)
+
+#define DMAMUX2_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)
+#define DMAMUX2_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)
+
+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+
+
+#define DMAMUX1              ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
+#define DMAMUX1_Channel0     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
+#define DMAMUX1_Channel1     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
+#define DMAMUX1_Channel2     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
+#define DMAMUX1_Channel3     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
+#define DMAMUX1_Channel4     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
+#define DMAMUX1_Channel5     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
+#define DMAMUX1_Channel6     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
+#define DMAMUX1_Channel7     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
+#define DMAMUX1_Channel8     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
+#define DMAMUX1_Channel9     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
+#define DMAMUX1_Channel10    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
+#define DMAMUX1_Channel11    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
+#define DMAMUX1_Channel12    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
+#define DMAMUX1_Channel13    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
+#define DMAMUX1_Channel14    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
+#define DMAMUX1_Channel15    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
+
+#define DMAMUX1_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
+#define DMAMUX1_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
+#define DMAMUX1_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
+#define DMAMUX1_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
+#define DMAMUX1_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)
+#define DMAMUX1_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)
+#define DMAMUX1_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)
+#define DMAMUX1_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)
+
+#define DMAMUX1_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *)    DMAMUX1_ChannelStatus_BASE)
+#define DMAMUX1_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
+
+
+#define FMC_Bank1_R           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
+#define FMC_Bank1E_R          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
+#define FMC_Bank2_R           ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)
+#define FMC_Bank3_R           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
+#define FMC_Bank5_6_R         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
+
+
+#define QUADSPI               ((QUADSPI_TypeDef *) QSPI_R_BASE)
+#define DLYB_QUADSPI          ((DLYB_TypeDef *) DLYB_QSPI_BASE)
+#define SDMMC1                ((SDMMC_TypeDef *) SDMMC1_BASE)
+#define DLYB_SDMMC1           ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)
+
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define JPEG                ((JPEG_TypeDef *) JPGDEC_BASE)
+#define HSEM                ((HSEM_TypeDef *) HSEM_BASE)
+#define HSEM_COMMON         ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))
+
+#define LTDC                ((LTDC_TypeDef *)LTDC_BASE)
+#define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
+#define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
+
+#define MDIOS               ((MDIOS_TypeDef *) MDIOS_BASE)
+
+#define ETH                 ((ETH_TypeDef *)ETH_BASE)
+#define MDMA                ((MDMA_TypeDef *)MDMA_BASE)
+#define MDMA_Channel0       ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)
+#define MDMA_Channel1       ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)
+#define MDMA_Channel2       ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)
+#define MDMA_Channel3       ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)
+#define MDMA_Channel4       ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)
+#define MDMA_Channel5       ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)
+#define MDMA_Channel6       ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)
+#define MDMA_Channel7       ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)
+#define MDMA_Channel8       ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)
+#define MDMA_Channel9       ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)
+#define MDMA_Channel10      ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)
+#define MDMA_Channel11      ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)
+#define MDMA_Channel12      ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)
+#define MDMA_Channel13      ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)
+#define MDMA_Channel14      ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)
+#define MDMA_Channel15      ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)
+
+
+#define USB1_OTG_HS         ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)
+#define USB2_OTG_FS         ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE)
+
+/* Legacy defines */
+#define USB_OTG_HS                   USB1_OTG_HS
+#define USB_OTG_HS_PERIPH_BASE       USB1_OTG_HS_PERIPH_BASE
+#define USB_OTG_FS                   USB2_OTG_FS
+#define USB_OTG_FS_PERIPH_BASE       USB2_OTG_FS_PERIPH_BASE
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+
+  /** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+
+/******************************************************************************/
+/*                         Peripheral Registers_Bits_Definition               */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Analog to Digital Converter                         */
+/*                                                                            */
+/******************************************************************************/
+/*******************************  ADC VERSION  ********************************/
+#define ADC_VER_V5_X
+/********************  Bit definition for ADC_ISR register  ********************/
+#define ADC_ISR_ADRDY_Pos                 (0U)
+#define ADC_ISR_ADRDY_Msk                 (0x1UL << ADC_ISR_ADRDY_Pos)         /*!< 0x00000001 */
+#define ADC_ISR_ADRDY                     ADC_ISR_ADRDY_Msk                    /*!< ADC Ready (ADRDY) flag  */
+#define ADC_ISR_EOSMP_Pos                 (1U)
+#define ADC_ISR_EOSMP_Msk                 (0x1UL << ADC_ISR_EOSMP_Pos)         /*!< 0x00000002 */
+#define ADC_ISR_EOSMP                     ADC_ISR_EOSMP_Msk                    /*!< ADC End of Sampling flag */
+#define ADC_ISR_EOC_Pos                   (2U)
+#define ADC_ISR_EOC_Msk                   (0x1UL << ADC_ISR_EOC_Pos)           /*!< 0x00000004 */
+#define ADC_ISR_EOC                       ADC_ISR_EOC_Msk                      /*!< ADC End of Regular Conversion flag */
+#define ADC_ISR_EOS_Pos                   (3U)
+#define ADC_ISR_EOS_Msk                   (0x1UL << ADC_ISR_EOS_Pos)           /*!< 0x00000008 */
+#define ADC_ISR_EOS                       ADC_ISR_EOS_Msk                      /*!< ADC End of Regular sequence of Conversions flag */
+#define ADC_ISR_OVR_Pos                   (4U)
+#define ADC_ISR_OVR_Msk                   (0x1UL << ADC_ISR_OVR_Pos)           /*!< 0x00000010 */
+#define ADC_ISR_OVR                       ADC_ISR_OVR_Msk                      /*!< ADC overrun flag */
+#define ADC_ISR_JEOC_Pos                  (5U)
+#define ADC_ISR_JEOC_Msk                  (0x1UL << ADC_ISR_JEOC_Pos)          /*!< 0x00000020 */
+#define ADC_ISR_JEOC                      ADC_ISR_JEOC_Msk                     /*!< ADC End of Injected Conversion flag */
+#define ADC_ISR_JEOS_Pos                  (6U)
+#define ADC_ISR_JEOS_Msk                  (0x1UL << ADC_ISR_JEOS_Pos)          /*!< 0x00000040 */
+#define ADC_ISR_JEOS                      ADC_ISR_JEOS_Msk                     /*!< ADC End of Injected sequence of Conversions flag */
+#define ADC_ISR_AWD1_Pos                  (7U)
+#define ADC_ISR_AWD1_Msk                  (0x1UL << ADC_ISR_AWD1_Pos)          /*!< 0x00000080 */
+#define ADC_ISR_AWD1                      ADC_ISR_AWD1_Msk                     /*!< ADC Analog watchdog 1 flag */
+#define ADC_ISR_AWD2_Pos                  (8U)
+#define ADC_ISR_AWD2_Msk                  (0x1UL << ADC_ISR_AWD2_Pos)          /*!< 0x00000100 */
+#define ADC_ISR_AWD2                      ADC_ISR_AWD2_Msk                     /*!< ADC Analog watchdog 2 flag */
+#define ADC_ISR_AWD3_Pos                  (9U)
+#define ADC_ISR_AWD3_Msk                  (0x1UL << ADC_ISR_AWD3_Pos)          /*!< 0x00000200 */
+#define ADC_ISR_AWD3                      ADC_ISR_AWD3_Msk                     /*!< ADC Analog watchdog 3 flag */
+#define ADC_ISR_JQOVF_Pos                 (10U)
+#define ADC_ISR_JQOVF_Msk                 (0x1UL << ADC_ISR_JQOVF_Pos)         /*!< 0x00000400 */
+#define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                    /*!< ADC Injected Context Queue Overflow flag */
+
+/********************  Bit definition for ADC_IER register  ********************/
+#define ADC_IER_ADRDYIE_Pos               (0U)
+#define ADC_IER_ADRDYIE_Msk               (0x1UL << ADC_IER_ADRDYIE_Pos)       /*!< 0x00000001 */
+#define ADC_IER_ADRDYIE                   ADC_IER_ADRDYIE_Msk                  /*!< ADC Ready (ADRDY) interrupt source */
+#define ADC_IER_EOSMPIE_Pos               (1U)
+#define ADC_IER_EOSMPIE_Msk               (0x1UL << ADC_IER_EOSMPIE_Pos)       /*!< 0x00000002 */
+#define ADC_IER_EOSMPIE                   ADC_IER_EOSMPIE_Msk                  /*!< ADC End of Sampling interrupt source */
+#define ADC_IER_EOCIE_Pos                 (2U)
+#define ADC_IER_EOCIE_Msk                 (0x1UL << ADC_IER_EOCIE_Pos)         /*!< 0x00000004 */
+#define ADC_IER_EOCIE                     ADC_IER_EOCIE_Msk                    /*!< ADC End of Regular Conversion interrupt source */
+#define ADC_IER_EOSIE_Pos                 (3U)
+#define ADC_IER_EOSIE_Msk                 (0x1UL << ADC_IER_EOSIE_Pos)         /*!< 0x00000008 */
+#define ADC_IER_EOSIE                     ADC_IER_EOSIE_Msk                    /*!< ADC End of Regular sequence of Conversions interrupt source */
+#define ADC_IER_OVRIE_Pos                 (4U)
+#define ADC_IER_OVRIE_Msk                 (0x1UL << ADC_IER_OVRIE_Pos)         /*!< 0x00000010 */
+#define ADC_IER_OVRIE                     ADC_IER_OVRIE_Msk                    /*!< ADC overrun interrupt source */
+#define ADC_IER_JEOCIE_Pos                (5U)
+#define ADC_IER_JEOCIE_Msk                (0x1UL << ADC_IER_JEOCIE_Pos)        /*!< 0x00000020 */
+#define ADC_IER_JEOCIE                    ADC_IER_JEOCIE_Msk                   /*!< ADC End of Injected Conversion interrupt source */
+#define ADC_IER_JEOSIE_Pos                (6U)
+#define ADC_IER_JEOSIE_Msk                (0x1UL << ADC_IER_JEOSIE_Pos)        /*!< 0x00000040 */
+#define ADC_IER_JEOSIE                    ADC_IER_JEOSIE_Msk                   /*!< ADC End of Injected sequence of Conversions interrupt source */
+#define ADC_IER_AWD1IE_Pos                (7U)
+#define ADC_IER_AWD1IE_Msk                (0x1UL << ADC_IER_AWD1IE_Pos)        /*!< 0x00000080 */
+#define ADC_IER_AWD1IE                    ADC_IER_AWD1IE_Msk                   /*!< ADC Analog watchdog 1 interrupt source */
+#define ADC_IER_AWD2IE_Pos                (8U)
+#define ADC_IER_AWD2IE_Msk                (0x1UL << ADC_IER_AWD2IE_Pos)        /*!< 0x00000100 */
+#define ADC_IER_AWD2IE                    ADC_IER_AWD2IE_Msk                   /*!< ADC Analog watchdog 2 interrupt source */
+#define ADC_IER_AWD3IE_Pos                (9U)
+#define ADC_IER_AWD3IE_Msk                (0x1UL << ADC_IER_AWD3IE_Pos)        /*!< 0x00000200 */
+#define ADC_IER_AWD3IE                    ADC_IER_AWD3IE_Msk                   /*!< ADC Analog watchdog 3 interrupt source */
+#define ADC_IER_JQOVFIE_Pos               (10U)
+#define ADC_IER_JQOVFIE_Msk               (0x1UL << ADC_IER_JQOVFIE_Pos)       /*!< 0x00000400 */
+#define ADC_IER_JQOVFIE                   ADC_IER_JQOVFIE_Msk                  /*!< ADC Injected Context Queue Overflow interrupt source */
+
+/********************  Bit definition for ADC_CR register  ********************/
+#define ADC_CR_ADEN_Pos                   (0U)
+#define ADC_CR_ADEN_Msk                   (0x1UL << ADC_CR_ADEN_Pos)           /*!< 0x00000001 */
+#define ADC_CR_ADEN                       ADC_CR_ADEN_Msk                      /*!< ADC Enable control */
+#define ADC_CR_ADDIS_Pos                  (1U)
+#define ADC_CR_ADDIS_Msk                  (0x1UL << ADC_CR_ADDIS_Pos)          /*!< 0x00000002 */
+#define ADC_CR_ADDIS                      ADC_CR_ADDIS_Msk                     /*!< ADC Disable command */
+#define ADC_CR_ADSTART_Pos                (2U)
+#define ADC_CR_ADSTART_Msk                (0x1UL << ADC_CR_ADSTART_Pos)        /*!< 0x00000004 */
+#define ADC_CR_ADSTART                    ADC_CR_ADSTART_Msk                   /*!< ADC Start of Regular conversion */
+#define ADC_CR_JADSTART_Pos               (3U)
+#define ADC_CR_JADSTART_Msk               (0x1UL << ADC_CR_JADSTART_Pos)       /*!< 0x00000008 */
+#define ADC_CR_JADSTART                   ADC_CR_JADSTART_Msk                  /*!< ADC Start of injected conversion */
+#define ADC_CR_ADSTP_Pos                  (4U)
+#define ADC_CR_ADSTP_Msk                  (0x1UL << ADC_CR_ADSTP_Pos)          /*!< 0x00000010 */
+#define ADC_CR_ADSTP                      ADC_CR_ADSTP_Msk                     /*!< ADC Stop of Regular conversion */
+#define ADC_CR_JADSTP_Pos                 (5U)
+#define ADC_CR_JADSTP_Msk                 (0x1UL << ADC_CR_JADSTP_Pos)         /*!< 0x00000020 */
+#define ADC_CR_JADSTP                     ADC_CR_JADSTP_Msk                    /*!< ADC Stop of injected conversion */
+#define ADC_CR_BOOST_Pos                  (8U)
+#define ADC_CR_BOOST_Msk                  (0x3UL << ADC_CR_BOOST_Pos)          /*!< 0x00000300 */
+#define ADC_CR_BOOST                      ADC_CR_BOOST_Msk                     /*!< ADC Boost Mode configuration */
+#define ADC_CR_BOOST_0                    (0x1UL << ADC_CR_BOOST_Pos)           /*!< 0x00000100 */
+#define ADC_CR_BOOST_1                    (0x2UL << ADC_CR_BOOST_Pos)           /*!< 0x00000200 */
+#define ADC_CR_ADCALLIN_Pos               (16U)
+#define ADC_CR_ADCALLIN_Msk               (0x1UL << ADC_CR_ADCALLIN_Pos)       /*!< 0x00010000 */
+#define ADC_CR_ADCALLIN                   ADC_CR_ADCALLIN_Msk                  /*!< ADC Linearity calibration */
+#define ADC_CR_LINCALRDYW1_Pos            (22U)
+#define ADC_CR_LINCALRDYW1_Msk            (0x1UL << ADC_CR_LINCALRDYW1_Pos)    /*!< 0x00400000 */
+#define ADC_CR_LINCALRDYW1                ADC_CR_LINCALRDYW1_Msk               /*!< ADC Linearity calibration ready Word 1 */
+#define ADC_CR_LINCALRDYW2_Pos            (23U)
+#define ADC_CR_LINCALRDYW2_Msk            (0x1UL << ADC_CR_LINCALRDYW2_Pos)    /*!< 0x00800000 */
+#define ADC_CR_LINCALRDYW2                ADC_CR_LINCALRDYW2_Msk               /*!< ADC Linearity calibration ready Word 2 */
+#define ADC_CR_LINCALRDYW3_Pos            (24U)
+#define ADC_CR_LINCALRDYW3_Msk            (0x1UL << ADC_CR_LINCALRDYW3_Pos)    /*!< 0x01000000 */
+#define ADC_CR_LINCALRDYW3                ADC_CR_LINCALRDYW3_Msk               /*!< ADC Linearity calibration ready Word 3 */
+#define ADC_CR_LINCALRDYW4_Pos            (25U)
+#define ADC_CR_LINCALRDYW4_Msk            (0x1UL << ADC_CR_LINCALRDYW4_Pos)    /*!< 0x02000000 */
+#define ADC_CR_LINCALRDYW4                ADC_CR_LINCALRDYW4_Msk               /*!< ADC Linearity calibration ready Word 4 */
+#define ADC_CR_LINCALRDYW5_Pos            (26U)
+#define ADC_CR_LINCALRDYW5_Msk            (0x1UL << ADC_CR_LINCALRDYW5_Pos)    /*!< 0x04000000 */
+#define ADC_CR_LINCALRDYW5                ADC_CR_LINCALRDYW5_Msk               /*!< ADC Linearity calibration ready Word 5 */
+#define ADC_CR_LINCALRDYW6_Pos            (27U)
+#define ADC_CR_LINCALRDYW6_Msk            (0x1UL << ADC_CR_LINCALRDYW6_Pos)    /*!< 0x08000000 */
+#define ADC_CR_LINCALRDYW6                ADC_CR_LINCALRDYW6_Msk               /*!< ADC Linearity calibration ready Word 6 */
+#define ADC_CR_ADVREGEN_Pos               (28U)
+#define ADC_CR_ADVREGEN_Msk               (0x1UL << ADC_CR_ADVREGEN_Pos)       /*!< 0x10000000 */
+#define ADC_CR_ADVREGEN                   ADC_CR_ADVREGEN_Msk                  /*!< ADC Voltage regulator Enable */
+#define ADC_CR_DEEPPWD_Pos                (29U)
+#define ADC_CR_DEEPPWD_Msk                (0x1UL << ADC_CR_DEEPPWD_Pos)        /*!< 0x20000000 */
+#define ADC_CR_DEEPPWD                    ADC_CR_DEEPPWD_Msk                   /*!< ADC Deep power down Enable */
+#define ADC_CR_ADCALDIF_Pos               (30U)
+#define ADC_CR_ADCALDIF_Msk               (0x1UL << ADC_CR_ADCALDIF_Pos)       /*!< 0x40000000 */
+#define ADC_CR_ADCALDIF                   ADC_CR_ADCALDIF_Msk                  /*!< ADC Differential Mode for calibration */
+#define ADC_CR_ADCAL_Pos                  (31U)
+#define ADC_CR_ADCAL_Msk                  (0x1UL << ADC_CR_ADCAL_Pos)          /*!< 0x80000000 */
+#define ADC_CR_ADCAL                      ADC_CR_ADCAL_Msk                     /*!< ADC Calibration */
+
+/********************  Bit definition for ADC_CFGR register  ********************/
+#define ADC_CFGR_DMNGT_Pos                (0U)
+#define ADC_CFGR_DMNGT_Msk                (0x3UL << ADC_CFGR_DMNGT_Pos)        /*!< 0x00000003 */
+#define ADC_CFGR_DMNGT                    ADC_CFGR_DMNGT_Msk                   /*!< ADC Data Management configuration */
+#define ADC_CFGR_DMNGT_0                  (0x1UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000001 */
+#define ADC_CFGR_DMNGT_1                  (0x2UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000002 */
+
+#define ADC_CFGR_RES_Pos                  (2U)
+#define ADC_CFGR_RES_Msk                  (0x7UL << ADC_CFGR_RES_Pos)          /*!< 0x0000001C */
+#define ADC_CFGR_RES                      ADC_CFGR_RES_Msk                     /*!< ADC Data resolution */
+#define ADC_CFGR_RES_0                    (0x1UL << ADC_CFGR_RES_Pos)           /*!< 0x00000004 */
+#define ADC_CFGR_RES_1                    (0x2UL << ADC_CFGR_RES_Pos)           /*!< 0x00000008 */
+#define ADC_CFGR_RES_2                    (0x4UL << ADC_CFGR_RES_Pos)           /*!< 0x00000010 */
+
+#define ADC_CFGR_EXTSEL_Pos               (5U)
+#define ADC_CFGR_EXTSEL_Msk               (0x1FUL << ADC_CFGR_EXTSEL_Pos)      /*!< 0x000003E0 */
+#define ADC_CFGR_EXTSEL                   ADC_CFGR_EXTSEL_Msk                  /*!< ADC External trigger selection for regular group */
+#define ADC_CFGR_EXTSEL_0                 (0x01UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000020 */
+#define ADC_CFGR_EXTSEL_1                 (0x02UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000040 */
+#define ADC_CFGR_EXTSEL_2                 (0x04UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000080 */
+#define ADC_CFGR_EXTSEL_3                 (0x08UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000100 */
+#define ADC_CFGR_EXTSEL_4                 (0x10UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000200 */
+
+#define ADC_CFGR_EXTEN_Pos                (10U)
+#define ADC_CFGR_EXTEN_Msk                (0x3UL << ADC_CFGR_EXTEN_Pos)        /*!< 0x00000C00 */
+#define ADC_CFGR_EXTEN                    ADC_CFGR_EXTEN_Msk                   /*!< ADC External trigger enable and polarity selection for regular channels */
+#define ADC_CFGR_EXTEN_0                  (0x1UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000400 */
+#define ADC_CFGR_EXTEN_1                  (0x2UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000800 */
+
+#define ADC_CFGR_OVRMOD_Pos               (12U)
+#define ADC_CFGR_OVRMOD_Msk               (0x1UL << ADC_CFGR_OVRMOD_Pos)       /*!< 0x00001000 */
+#define ADC_CFGR_OVRMOD                   ADC_CFGR_OVRMOD_Msk                  /*!< ADC overrun mode */
+#define ADC_CFGR_CONT_Pos                 (13U)
+#define ADC_CFGR_CONT_Msk                 (0x1UL << ADC_CFGR_CONT_Pos)         /*!< 0x00002000 */
+#define ADC_CFGR_CONT                     ADC_CFGR_CONT_Msk                    /*!< ADC Single/continuous conversion mode for regular conversion */
+#define ADC_CFGR_AUTDLY_Pos               (14U)
+#define ADC_CFGR_AUTDLY_Msk               (0x1UL << ADC_CFGR_AUTDLY_Pos)       /*!< 0x00004000 */
+#define ADC_CFGR_AUTDLY                   ADC_CFGR_AUTDLY_Msk                  /*!< ADC Delayed conversion mode */
+
+#define ADC_CFGR_DISCEN_Pos               (16U)
+#define ADC_CFGR_DISCEN_Msk               (0x1UL << ADC_CFGR_DISCEN_Pos)       /*!< 0x00010000 */
+#define ADC_CFGR_DISCEN                   ADC_CFGR_DISCEN_Msk                  /*!< ADC Discontinuous mode for regular channels */
+
+#define ADC_CFGR_DISCNUM_Pos              (17U)
+#define ADC_CFGR_DISCNUM_Msk              (0x7UL << ADC_CFGR_DISCNUM_Pos)      /*!< 0x000E0000 */
+#define ADC_CFGR_DISCNUM                  ADC_CFGR_DISCNUM_Msk                 /*!< ADC Discontinuous mode channel count */
+#define ADC_CFGR_DISCNUM_0                (0x1UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00020000 */
+#define ADC_CFGR_DISCNUM_1                (0x2UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00040000 */
+#define ADC_CFGR_DISCNUM_2                (0x4UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00080000 */
+
+#define ADC_CFGR_JDISCEN_Pos              (20U)
+#define ADC_CFGR_JDISCEN_Msk              (0x1UL << ADC_CFGR_JDISCEN_Pos)      /*!< 0x00100000 */
+#define ADC_CFGR_JDISCEN                  ADC_CFGR_JDISCEN_Msk                 /*!< ADC Discontinuous mode on injected channels */
+#define ADC_CFGR_JQM_Pos                  (21U)
+#define ADC_CFGR_JQM_Msk                  (0x1UL << ADC_CFGR_JQM_Pos)          /*!< 0x00200000 */
+#define ADC_CFGR_JQM                      ADC_CFGR_JQM_Msk                     /*!< ADC JSQR Queue mode */
+#define ADC_CFGR_AWD1SGL_Pos              (22U)
+#define ADC_CFGR_AWD1SGL_Msk              (0x1UL << ADC_CFGR_AWD1SGL_Pos)      /*!< 0x00400000 */
+#define ADC_CFGR_AWD1SGL                  ADC_CFGR_AWD1SGL_Msk                 /*!< Enable the watchdog 1 on a single channel or on all channels */
+#define ADC_CFGR_AWD1EN_Pos               (23U)
+#define ADC_CFGR_AWD1EN_Msk               (0x1UL << ADC_CFGR_AWD1EN_Pos)       /*!< 0x00800000 */
+#define ADC_CFGR_AWD1EN                   ADC_CFGR_AWD1EN_Msk                  /*!< ADC Analog watchdog 1 enable on regular Channels */
+#define ADC_CFGR_JAWD1EN_Pos              (24U)
+#define ADC_CFGR_JAWD1EN_Msk              (0x1UL << ADC_CFGR_JAWD1EN_Pos)      /*!< 0x01000000 */
+#define ADC_CFGR_JAWD1EN                  ADC_CFGR_JAWD1EN_Msk                 /*!< ADC Analog watchdog 1 enable on injected Channels */
+#define ADC_CFGR_JAUTO_Pos                (25U)
+#define ADC_CFGR_JAUTO_Msk                (0x1UL << ADC_CFGR_JAUTO_Pos)        /*!< 0x02000000 */
+#define ADC_CFGR_JAUTO                    ADC_CFGR_JAUTO_Msk                   /*!< ADC Automatic injected group conversion */
+
+#define ADC_CFGR_AWD1CH_Pos               (26U)
+#define ADC_CFGR_AWD1CH_Msk               (0x1FUL << ADC_CFGR_AWD1CH_Pos)      /*!< 0x7C000000 */
+#define ADC_CFGR_AWD1CH                   ADC_CFGR_AWD1CH_Msk                  /*!< ADC Analog watchdog 1 Channel selection */
+#define ADC_CFGR_AWD1CH_0                 (0x01UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x04000000 */
+#define ADC_CFGR_AWD1CH_1                 (0x02UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x08000000 */
+#define ADC_CFGR_AWD1CH_2                 (0x04UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x10000000 */
+#define ADC_CFGR_AWD1CH_3                 (0x08UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x20000000 */
+#define ADC_CFGR_AWD1CH_4                 (0x10UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x40000000 */
+
+#define ADC_CFGR_JQDIS_Pos                (31U)
+#define ADC_CFGR_JQDIS_Msk                (0x1UL << ADC_CFGR_JQDIS_Pos)        /*!< 0x80000000 */
+#define ADC_CFGR_JQDIS                    ADC_CFGR_JQDIS_Msk                   /*!< ADC Injected queue disable */
+
+/********************  Bit definition for ADC_CFGR2 register  ********************/
+#define ADC_CFGR2_ROVSE_Pos               (0U)
+#define ADC_CFGR2_ROVSE_Msk               (0x1UL << ADC_CFGR2_ROVSE_Pos)       /*!< 0x00000001 */
+#define ADC_CFGR2_ROVSE                   ADC_CFGR2_ROVSE_Msk                  /*!< ADC Regular group oversampler enable */
+#define ADC_CFGR2_JOVSE_Pos               (1U)
+#define ADC_CFGR2_JOVSE_Msk               (0x1UL << ADC_CFGR2_JOVSE_Pos)       /*!< 0x00000002 */
+#define ADC_CFGR2_JOVSE                   ADC_CFGR2_JOVSE_Msk                  /*!< ADC Injected group oversampler enable */
+
+#define ADC_CFGR2_OVSS_Pos                (5U)
+#define ADC_CFGR2_OVSS_Msk                (0xFUL << ADC_CFGR2_OVSS_Pos)        /*!< 0x000001E0 */
+#define ADC_CFGR2_OVSS                    ADC_CFGR2_OVSS_Msk                   /*!< ADC Regular Oversampling shift */
+#define ADC_CFGR2_OVSS_0                  (0x1UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000020 */
+#define ADC_CFGR2_OVSS_1                  (0x2UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000040 */
+#define ADC_CFGR2_OVSS_2                  (0x4UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000080 */
+#define ADC_CFGR2_OVSS_3                  (0x8UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000100 */
+
+#define ADC_CFGR2_TROVS_Pos               (9U)
+#define ADC_CFGR2_TROVS_Msk               (0x1UL << ADC_CFGR2_TROVS_Pos)       /*!< 0x00000200 */
+#define ADC_CFGR2_TROVS                   ADC_CFGR2_TROVS_Msk                  /*!< ADC Triggered regular Oversampling */
+#define ADC_CFGR2_ROVSM_Pos               (10U)
+#define ADC_CFGR2_ROVSM_Msk               (0x1UL << ADC_CFGR2_ROVSM_Pos)       /*!< 0x00000400 */
+#define ADC_CFGR2_ROVSM                   ADC_CFGR2_ROVSM_Msk                  /*!< ADC Regular oversampling mode */
+
+#define ADC_CFGR2_RSHIFT1_Pos             (11U)
+#define ADC_CFGR2_RSHIFT1_Msk             (0x1UL << ADC_CFGR2_RSHIFT1_Pos)     /*!< 0x00000800 */
+#define ADC_CFGR2_RSHIFT1                 ADC_CFGR2_RSHIFT1_Msk                /*!< ADC Right-shift data after Offset 1 correction */
+#define ADC_CFGR2_RSHIFT2_Pos             (12U)
+#define ADC_CFGR2_RSHIFT2_Msk             (0x1UL << ADC_CFGR2_RSHIFT2_Pos)     /*!< 0x00001000 */
+#define ADC_CFGR2_RSHIFT2                 ADC_CFGR2_RSHIFT2_Msk                /*!< ADC Right-shift data after Offset 2 correction */
+#define ADC_CFGR2_RSHIFT3_Pos             (13U)
+#define ADC_CFGR2_RSHIFT3_Msk             (0x1UL << ADC_CFGR2_RSHIFT3_Pos)     /*!< 0x00002000 */
+#define ADC_CFGR2_RSHIFT3                 ADC_CFGR2_RSHIFT3_Msk                /*!< ADC Right-shift data after Offset 3 correction */
+#define ADC_CFGR2_RSHIFT4_Pos             (14U)
+#define ADC_CFGR2_RSHIFT4_Msk             (0x1UL << ADC_CFGR2_RSHIFT4_Pos)     /*!< 0x00004000 */
+#define ADC_CFGR2_RSHIFT4                 ADC_CFGR2_RSHIFT4_Msk                /*!< ADC Right-shift data after Offset 4 correction */
+
+#define ADC_CFGR2_OVSR_Pos                (16U)
+#define ADC_CFGR2_OVSR_Msk                (0x3FFUL << ADC_CFGR2_OVSR_Pos)      /*!< 0x03FF0000 */
+#define ADC_CFGR2_OVSR                    ADC_CFGR2_OVSR_Msk                   /*!< ADC oversampling Ratio */
+#define ADC_CFGR2_OVSR_0                  (0x001UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00010000 */
+#define ADC_CFGR2_OVSR_1                  (0x002UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00020000 */
+#define ADC_CFGR2_OVSR_2                  (0x004UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00040000 */
+#define ADC_CFGR2_OVSR_3                  (0x008UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00080000 */
+#define ADC_CFGR2_OVSR_4                  (0x010UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00100000 */
+#define ADC_CFGR2_OVSR_5                  (0x020UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00200000 */
+#define ADC_CFGR2_OVSR_6                  (0x040UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00400000 */
+#define ADC_CFGR2_OVSR_7                  (0x080UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00800000 */
+#define ADC_CFGR2_OVSR_8                  (0x100UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x01000000 */
+#define ADC_CFGR2_OVSR_9                  (0x200UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x02000000 */
+
+#define ADC_CFGR2_LSHIFT_Pos              (28U)
+#define ADC_CFGR2_LSHIFT_Msk              (0xFUL << ADC_CFGR2_LSHIFT_Pos)      /*!< 0xF0000000 */
+#define ADC_CFGR2_LSHIFT                  ADC_CFGR2_LSHIFT_Msk                 /*!< ADC Left shift factor */
+#define ADC_CFGR2_LSHIFT_0                (0x1UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x10000000 */
+#define ADC_CFGR2_LSHIFT_1                (0x2UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x20000000 */
+#define ADC_CFGR2_LSHIFT_2                (0x4UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x40000000 */
+#define ADC_CFGR2_LSHIFT_3                (0x8UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_SMPR1 register  ********************/
+#define ADC_SMPR1_SMP0_Pos                (0U)
+#define ADC_SMPR1_SMP0_Msk                (0x7UL << ADC_SMPR1_SMP0_Pos)        /*!< 0x00000007 */
+#define ADC_SMPR1_SMP0                    ADC_SMPR1_SMP0_Msk                   /*!< ADC Channel 0 Sampling time selection  */
+#define ADC_SMPR1_SMP0_0                  (0x1UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000001 */
+#define ADC_SMPR1_SMP0_1                  (0x2UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000002 */
+#define ADC_SMPR1_SMP0_2                  (0x4UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000004 */
+
+#define ADC_SMPR1_SMP1_Pos                (3U)
+#define ADC_SMPR1_SMP1_Msk                (0x7UL << ADC_SMPR1_SMP1_Pos)        /*!< 0x00000038 */
+#define ADC_SMPR1_SMP1                    ADC_SMPR1_SMP1_Msk                   /*!< ADC Channel 1 Sampling time selection  */
+#define ADC_SMPR1_SMP1_0                  (0x1UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000008 */
+#define ADC_SMPR1_SMP1_1                  (0x2UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000010 */
+#define ADC_SMPR1_SMP1_2                  (0x4UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000020 */
+
+#define ADC_SMPR1_SMP2_Pos                (6U)
+#define ADC_SMPR1_SMP2_Msk                (0x7UL << ADC_SMPR1_SMP2_Pos)        /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP2                    ADC_SMPR1_SMP2_Msk                   /*!< ADC Channel 2 Sampling time selection  */
+#define ADC_SMPR1_SMP2_0                  (0x1UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000040 */
+#define ADC_SMPR1_SMP2_1                  (0x2UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000080 */
+#define ADC_SMPR1_SMP2_2                  (0x4UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000100 */
+
+#define ADC_SMPR1_SMP3_Pos                (9U)
+#define ADC_SMPR1_SMP3_Msk                (0x7UL << ADC_SMPR1_SMP3_Pos)        /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP3                    ADC_SMPR1_SMP3_Msk                   /*!< ADC Channel 3 Sampling time selection  */
+#define ADC_SMPR1_SMP3_0                  (0x1UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000200 */
+#define ADC_SMPR1_SMP3_1                  (0x2UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000400 */
+#define ADC_SMPR1_SMP3_2                  (0x4UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000800 */
+
+#define ADC_SMPR1_SMP4_Pos                (12U)
+#define ADC_SMPR1_SMP4_Msk                (0x7UL << ADC_SMPR1_SMP4_Pos)        /*!< 0x00007000 */
+#define ADC_SMPR1_SMP4                    ADC_SMPR1_SMP4_Msk                   /*!< ADC Channel 4 Sampling time selection  */
+#define ADC_SMPR1_SMP4_0                  (0x1UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00001000 */
+#define ADC_SMPR1_SMP4_1                  (0x2UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00002000 */
+#define ADC_SMPR1_SMP4_2                  (0x4UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00004000 */
+
+#define ADC_SMPR1_SMP5_Pos                (15U)
+#define ADC_SMPR1_SMP5_Msk                (0x7UL << ADC_SMPR1_SMP5_Pos)        /*!< 0x00038000 */
+#define ADC_SMPR1_SMP5                    ADC_SMPR1_SMP5_Msk                   /*!< ADC Channel 5 Sampling time selection  */
+#define ADC_SMPR1_SMP5_0                  (0x1UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00008000 */
+#define ADC_SMPR1_SMP5_1                  (0x2UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00010000 */
+#define ADC_SMPR1_SMP5_2                  (0x4UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00020000 */
+
+#define ADC_SMPR1_SMP6_Pos                (18U)
+#define ADC_SMPR1_SMP6_Msk                (0x7UL << ADC_SMPR1_SMP6_Pos)        /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP6                    ADC_SMPR1_SMP6_Msk                   /*!< ADC Channel 6 Sampling time selection  */
+#define ADC_SMPR1_SMP6_0                  (0x1UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00040000 */
+#define ADC_SMPR1_SMP6_1                  (0x2UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00080000 */
+#define ADC_SMPR1_SMP6_2                  (0x4UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00100000 */
+
+#define ADC_SMPR1_SMP7_Pos                (21U)
+#define ADC_SMPR1_SMP7_Msk                (0x7UL << ADC_SMPR1_SMP7_Pos)        /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP7                    ADC_SMPR1_SMP7_Msk                   /*!< ADC Channel 7 Sampling time selection  */
+#define ADC_SMPR1_SMP7_0                  (0x1UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00200000 */
+#define ADC_SMPR1_SMP7_1                  (0x2UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00400000 */
+#define ADC_SMPR1_SMP7_2                  (0x4UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00800000 */
+
+#define ADC_SMPR1_SMP8_Pos                (24U)
+#define ADC_SMPR1_SMP8_Msk                (0x7UL << ADC_SMPR1_SMP8_Pos)        /*!< 0x07000000 */
+#define ADC_SMPR1_SMP8                    ADC_SMPR1_SMP8_Msk                   /*!< ADC Channel 8 Sampling time selection  */
+#define ADC_SMPR1_SMP8_0                  (0x1UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x01000000 */
+#define ADC_SMPR1_SMP8_1                  (0x2UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x02000000 */
+#define ADC_SMPR1_SMP8_2                  (0x4UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x04000000 */
+
+#define ADC_SMPR1_SMP9_Pos                (27U)
+#define ADC_SMPR1_SMP9_Msk                (0x7UL << ADC_SMPR1_SMP9_Pos)        /*!< 0x38000000 */
+#define ADC_SMPR1_SMP9                    ADC_SMPR1_SMP9_Msk                   /*!< ADC Channel 9 Sampling time selection  */
+#define ADC_SMPR1_SMP9_0                  (0x1UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x08000000 */
+#define ADC_SMPR1_SMP9_1                  (0x2UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x10000000 */
+#define ADC_SMPR1_SMP9_2                  (0x4UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x20000000 */
+
+/********************  Bit definition for ADC_SMPR2 register  ********************/
+#define ADC_SMPR2_SMP10_Pos               (0U)
+#define ADC_SMPR2_SMP10_Msk               (0x7UL << ADC_SMPR2_SMP10_Pos)       /*!< 0x00000007 */
+#define ADC_SMPR2_SMP10                   ADC_SMPR2_SMP10_Msk                  /*!< ADC Channel 10 Sampling time selection  */
+#define ADC_SMPR2_SMP10_0                 (0x1UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000001 */
+#define ADC_SMPR2_SMP10_1                 (0x2UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000002 */
+#define ADC_SMPR2_SMP10_2                 (0x4UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000004 */
+
+#define ADC_SMPR2_SMP11_Pos               (3U)
+#define ADC_SMPR2_SMP11_Msk               (0x7UL << ADC_SMPR2_SMP11_Pos)       /*!< 0x00000038 */
+#define ADC_SMPR2_SMP11                   ADC_SMPR2_SMP11_Msk                  /*!< ADC Channel 11 Sampling time selection  */
+#define ADC_SMPR2_SMP11_0                 (0x1UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000008 */
+#define ADC_SMPR2_SMP11_1                 (0x2UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000010 */
+#define ADC_SMPR2_SMP11_2                 (0x4UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000020 */
+
+#define ADC_SMPR2_SMP12_Pos               (6U)
+#define ADC_SMPR2_SMP12_Msk               (0x7UL << ADC_SMPR2_SMP12_Pos)       /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP12                   ADC_SMPR2_SMP12_Msk                  /*!< ADC Channel 12 Sampling time selection  */
+#define ADC_SMPR2_SMP12_0                 (0x1UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000040 */
+#define ADC_SMPR2_SMP12_1                 (0x2UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000080 */
+#define ADC_SMPR2_SMP12_2                 (0x4UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000100 */
+
+#define ADC_SMPR2_SMP13_Pos               (9U)
+#define ADC_SMPR2_SMP13_Msk               (0x7UL << ADC_SMPR2_SMP13_Pos)       /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP13                   ADC_SMPR2_SMP13_Msk                  /*!< ADC Channel 13 Sampling time selection  */
+#define ADC_SMPR2_SMP13_0                 (0x1UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000200 */
+#define ADC_SMPR2_SMP13_1                 (0x2UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000400 */
+#define ADC_SMPR2_SMP13_2                 (0x4UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000800 */
+
+#define ADC_SMPR2_SMP14_Pos               (12U)
+#define ADC_SMPR2_SMP14_Msk               (0x7UL << ADC_SMPR2_SMP14_Pos)       /*!< 0x00007000 */
+#define ADC_SMPR2_SMP14                   ADC_SMPR2_SMP14_Msk                  /*!< ADC Channel 14 Sampling time selection  */
+#define ADC_SMPR2_SMP14_0                 (0x1UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00001000 */
+#define ADC_SMPR2_SMP14_1                 (0x2UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00002000 */
+#define ADC_SMPR2_SMP14_2                 (0x4UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00004000 */
+
+#define ADC_SMPR2_SMP15_Pos               (15U)
+#define ADC_SMPR2_SMP15_Msk               (0x7UL << ADC_SMPR2_SMP15_Pos)       /*!< 0x00038000 */
+#define ADC_SMPR2_SMP15                   ADC_SMPR2_SMP15_Msk                  /*!< ADC Channel 15 Sampling time selection  */
+#define ADC_SMPR2_SMP15_0                 (0x1UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00008000 */
+#define ADC_SMPR2_SMP15_1                 (0x2UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00010000 */
+#define ADC_SMPR2_SMP15_2                 (0x4UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00020000 */
+
+#define ADC_SMPR2_SMP16_Pos               (18U)
+#define ADC_SMPR2_SMP16_Msk               (0x7UL << ADC_SMPR2_SMP16_Pos)       /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP16                   ADC_SMPR2_SMP16_Msk                  /*!< ADC Channel 16 Sampling time selection  */
+#define ADC_SMPR2_SMP16_0                 (0x1UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00040000 */
+#define ADC_SMPR2_SMP16_1                 (0x2UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00080000 */
+#define ADC_SMPR2_SMP16_2                 (0x4UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00100000 */
+
+#define ADC_SMPR2_SMP17_Pos               (21U)
+#define ADC_SMPR2_SMP17_Msk               (0x7UL << ADC_SMPR2_SMP17_Pos)       /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP17                   ADC_SMPR2_SMP17_Msk                  /*!< ADC Channel 17 Sampling time selection  */
+#define ADC_SMPR2_SMP17_0                 (0x1UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00200000 */
+#define ADC_SMPR2_SMP17_1                 (0x2UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00400000 */
+#define ADC_SMPR2_SMP17_2                 (0x4UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00800000 */
+
+#define ADC_SMPR2_SMP18_Pos               (24U)
+#define ADC_SMPR2_SMP18_Msk               (0x7UL << ADC_SMPR2_SMP18_Pos)       /*!< 0x07000000 */
+#define ADC_SMPR2_SMP18                   ADC_SMPR2_SMP18_Msk                  /*!< ADC Channel 18 Sampling time selection  */
+#define ADC_SMPR2_SMP18_0                 (0x1UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x01000000 */
+#define ADC_SMPR2_SMP18_1                 (0x2UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x02000000 */
+#define ADC_SMPR2_SMP18_2                 (0x4UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x04000000 */
+
+#define ADC_SMPR2_SMP19_Pos               (27U)
+#define ADC_SMPR2_SMP19_Msk               (0x7UL << ADC_SMPR2_SMP19_Pos)       /*!< 0x38000000 */
+#define ADC_SMPR2_SMP19                   ADC_SMPR2_SMP19_Msk                  /*!< ADC Channel 19 Sampling time selection  */
+#define ADC_SMPR2_SMP19_0                 (0x1UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x08000000 */
+#define ADC_SMPR2_SMP19_1                 (0x2UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x10000000 */
+#define ADC_SMPR2_SMP19_2                 (0x4UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x20000000 */
+
+/********************  Bit definition for ADC_PCSEL register  ********************/
+#define ADC_PCSEL_PCSEL_Pos               (0U)
+#define ADC_PCSEL_PCSEL_Msk               (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos)   /*!< 0x000FFFFF */
+#define ADC_PCSEL_PCSEL                   ADC_PCSEL_PCSEL_Msk                  /*!< ADC pre channel selection */
+#define ADC_PCSEL_PCSEL_0                 (0x00001UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000001 */
+#define ADC_PCSEL_PCSEL_1                 (0x00002UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000002 */
+#define ADC_PCSEL_PCSEL_2                 (0x00004UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000004 */
+#define ADC_PCSEL_PCSEL_3                 (0x00008UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000008 */
+#define ADC_PCSEL_PCSEL_4                 (0x00010UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000010 */
+#define ADC_PCSEL_PCSEL_5                 (0x00020UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000020 */
+#define ADC_PCSEL_PCSEL_6                 (0x00040UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000040 */
+#define ADC_PCSEL_PCSEL_7                 (0x00080UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000080 */
+#define ADC_PCSEL_PCSEL_8                 (0x00100UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000100 */
+#define ADC_PCSEL_PCSEL_9                 (0x00200UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000200 */
+#define ADC_PCSEL_PCSEL_10                (0x00400UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000400 */
+#define ADC_PCSEL_PCSEL_11                (0x00800UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000800 */
+#define ADC_PCSEL_PCSEL_12                (0x01000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00001000 */
+#define ADC_PCSEL_PCSEL_13                (0x02000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00002000 */
+#define ADC_PCSEL_PCSEL_14                (0x04000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00004000 */
+#define ADC_PCSEL_PCSEL_15                (0x08000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00008000 */
+#define ADC_PCSEL_PCSEL_16                (0x10000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00010000 */
+#define ADC_PCSEL_PCSEL_17                (0x20000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00020000 */
+#define ADC_PCSEL_PCSEL_18                (0x40000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00040000 */
+#define ADC_PCSEL_PCSEL_19                (0x80000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00080000 */
+
+/*****************  Bit definition for ADC_LTR1, 2, 3 registers *****************/
+#define ADC_LTR_LT_Pos                    (0U)
+#define ADC_LTR_LT_Msk                    (0x3FFFFFFUL << ADC_LTR_LT_Pos)      /*!< 0x03FFFFFF */
+#define ADC_LTR_LT                        ADC_LTR_LT_Msk                       /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */
+
+/*****************  Bit definition for ADC_HTR1, 2, 3 registers  ****************/
+#define ADC_HTR_HT_Pos                    (0U)
+#define ADC_HTR_HT_Msk                    (0x3FFFFFFUL << ADC_HTR_HT_Pos)      /*!< 0x03FFFFFF */
+#define ADC_HTR_HT                        ADC_HTR_HT_Msk                       /*!< ADC Analog watchdog 1,2 and 3 higher threshold */
+
+
+/********************  Bit definition for ADC_SQR1 register  ********************/
+#define ADC_SQR1_L_Pos                    (0U)
+#define ADC_SQR1_L_Msk                    (0xFUL << ADC_SQR1_L_Pos)            /*!< 0x0000000F */
+#define ADC_SQR1_L                        ADC_SQR1_L_Msk                       /*!< ADC regular channel sequence lenght */
+#define ADC_SQR1_L_0                      (0x1UL << ADC_SQR1_L_Pos)             /*!< 0x00000001 */
+#define ADC_SQR1_L_1                      (0x2UL << ADC_SQR1_L_Pos)             /*!< 0x00000002 */
+#define ADC_SQR1_L_2                      (0x4UL << ADC_SQR1_L_Pos)             /*!< 0x00000004 */
+#define ADC_SQR1_L_3                      (0x8UL << ADC_SQR1_L_Pos)             /*!< 0x00000008 */
+
+#define ADC_SQR1_SQ1_Pos                  (6U)
+#define ADC_SQR1_SQ1_Msk                  (0x1FUL << ADC_SQR1_SQ1_Pos)         /*!< 0x000007C0 */
+#define ADC_SQR1_SQ1                      ADC_SQR1_SQ1_Msk                     /*!< ADC 1st conversion in regular sequence */
+#define ADC_SQR1_SQ1_0                    (0x01UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000040 */
+#define ADC_SQR1_SQ1_1                    (0x02UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000080 */
+#define ADC_SQR1_SQ1_2                    (0x04UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000100 */
+#define ADC_SQR1_SQ1_3                    (0x08UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000200 */
+#define ADC_SQR1_SQ1_4                    (0x10UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000400 */
+
+#define ADC_SQR1_SQ2_Pos                  (12U)
+#define ADC_SQR1_SQ2_Msk                  (0x1FUL << ADC_SQR1_SQ2_Pos)         /*!< 0x0001F000 */
+#define ADC_SQR1_SQ2                      ADC_SQR1_SQ2_Msk                     /*!< ADC 2nd conversion in regular sequence */
+#define ADC_SQR1_SQ2_0                    (0x01UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00001000 */
+#define ADC_SQR1_SQ2_1                    (0x02UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00002000 */
+#define ADC_SQR1_SQ2_2                    (0x04UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00004000 */
+#define ADC_SQR1_SQ2_3                    (0x08UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00008000 */
+#define ADC_SQR1_SQ2_4                    (0x10UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00010000 */
+
+#define ADC_SQR1_SQ3_Pos                  (18U)
+#define ADC_SQR1_SQ3_Msk                  (0x1FUL << ADC_SQR1_SQ3_Pos)         /*!< 0x007C0000 */
+#define ADC_SQR1_SQ3                      ADC_SQR1_SQ3_Msk                     /*!< ADC 3rd conversion in regular sequence */
+#define ADC_SQR1_SQ3_0                    (0x01UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00040000 */
+#define ADC_SQR1_SQ3_1                    (0x02UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00080000 */
+#define ADC_SQR1_SQ3_2                    (0x04UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00100000 */
+#define ADC_SQR1_SQ3_3                    (0x08UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00200000 */
+#define ADC_SQR1_SQ3_4                    (0x10UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00400000 */
+
+#define ADC_SQR1_SQ4_Pos                  (24U)
+#define ADC_SQR1_SQ4_Msk                  (0x1FUL << ADC_SQR1_SQ4_Pos)         /*!< 0x1F000000 */
+#define ADC_SQR1_SQ4                      ADC_SQR1_SQ4_Msk                     /*!< ADC 4th conversion in regular sequence */
+#define ADC_SQR1_SQ4_0                    (0x01UL << ADC_SQR1_SQ4_Pos)          /*!< 0x01000000 */
+#define ADC_SQR1_SQ4_1                    (0x02UL << ADC_SQR1_SQ4_Pos)          /*!< 0x02000000 */
+#define ADC_SQR1_SQ4_2                    (0x04UL << ADC_SQR1_SQ4_Pos)          /*!< 0x04000000 */
+#define ADC_SQR1_SQ4_3                    (0x08UL << ADC_SQR1_SQ4_Pos)          /*!< 0x08000000 */
+#define ADC_SQR1_SQ4_4                    (0x10UL << ADC_SQR1_SQ4_Pos)          /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR2 register  ********************/
+#define ADC_SQR2_SQ5_Pos                  (0U)
+#define ADC_SQR2_SQ5_Msk                  (0x1FUL << ADC_SQR2_SQ5_Pos)         /*!< 0x0000001F */
+#define ADC_SQR2_SQ5                      ADC_SQR2_SQ5_Msk                     /*!< ADC 5th conversion in regular sequence */
+#define ADC_SQR2_SQ5_0                    (0x01UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000001 */
+#define ADC_SQR2_SQ5_1                    (0x02UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000002 */
+#define ADC_SQR2_SQ5_2                    (0x04UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000004 */
+#define ADC_SQR2_SQ5_3                    (0x08UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000008 */
+#define ADC_SQR2_SQ5_4                    (0x10UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000010 */
+
+#define ADC_SQR2_SQ6_Pos                  (6U)
+#define ADC_SQR2_SQ6_Msk                  (0x1FUL << ADC_SQR2_SQ6_Pos)         /*!< 0x000007C0 */
+#define ADC_SQR2_SQ6                      ADC_SQR2_SQ6_Msk                     /*!< ADC 6th conversion in regular sequence */
+#define ADC_SQR2_SQ6_0                    (0x01UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000040 */
+#define ADC_SQR2_SQ6_1                    (0x02UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000080 */
+#define ADC_SQR2_SQ6_2                    (0x04UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000100 */
+#define ADC_SQR2_SQ6_3                    (0x08UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000200 */
+#define ADC_SQR2_SQ6_4                    (0x10UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000400 */
+
+#define ADC_SQR2_SQ7_Pos                  (12U)
+#define ADC_SQR2_SQ7_Msk                  (0x1FUL << ADC_SQR2_SQ7_Pos)         /*!< 0x0001F000 */
+#define ADC_SQR2_SQ7                      ADC_SQR2_SQ7_Msk                     /*!< ADC 7th conversion in regular sequence */
+#define ADC_SQR2_SQ7_0                    (0x01UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00001000 */
+#define ADC_SQR2_SQ7_1                    (0x02UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00002000 */
+#define ADC_SQR2_SQ7_2                    (0x04UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00004000 */
+#define ADC_SQR2_SQ7_3                    (0x08UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00008000 */
+#define ADC_SQR2_SQ7_4                    (0x10UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00010000 */
+
+#define ADC_SQR2_SQ8_Pos                  (18U)
+#define ADC_SQR2_SQ8_Msk                  (0x1FUL << ADC_SQR2_SQ8_Pos)         /*!< 0x007C0000 */
+#define ADC_SQR2_SQ8                      ADC_SQR2_SQ8_Msk                     /*!< ADC 8th conversion in regular sequence */
+#define ADC_SQR2_SQ8_0                    (0x01UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00040000 */
+#define ADC_SQR2_SQ8_1                    (0x02UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00080000 */
+#define ADC_SQR2_SQ8_2                    (0x04UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00100000 */
+#define ADC_SQR2_SQ8_3                    (0x08UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00200000 */
+#define ADC_SQR2_SQ8_4                    (0x10UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00400000 */
+
+#define ADC_SQR2_SQ9_Pos                  (24U)
+#define ADC_SQR2_SQ9_Msk                  (0x1FUL << ADC_SQR2_SQ9_Pos)         /*!< 0x1F000000 */
+#define ADC_SQR2_SQ9                      ADC_SQR2_SQ9_Msk                     /*!< ADC 9th conversion in regular sequence */
+#define ADC_SQR2_SQ9_0                    (0x01UL << ADC_SQR2_SQ9_Pos)          /*!< 0x01000000 */
+#define ADC_SQR2_SQ9_1                    (0x02UL << ADC_SQR2_SQ9_Pos)          /*!< 0x02000000 */
+#define ADC_SQR2_SQ9_2                    (0x04UL << ADC_SQR2_SQ9_Pos)          /*!< 0x04000000 */
+#define ADC_SQR2_SQ9_3                    (0x08UL << ADC_SQR2_SQ9_Pos)          /*!< 0x08000000 */
+#define ADC_SQR2_SQ9_4                    (0x10UL << ADC_SQR2_SQ9_Pos)          /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR3 register  ********************/
+#define ADC_SQR3_SQ10_Pos                 (0U)
+#define ADC_SQR3_SQ10_Msk                 (0x1FUL << ADC_SQR3_SQ10_Pos)        /*!< 0x0000001F */
+#define ADC_SQR3_SQ10                     ADC_SQR3_SQ10_Msk                    /*!< ADC 10th conversion in regular sequence */
+#define ADC_SQR3_SQ10_0                   (0x01UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000001 */
+#define ADC_SQR3_SQ10_1                   (0x02UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000002 */
+#define ADC_SQR3_SQ10_2                   (0x04UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000004 */
+#define ADC_SQR3_SQ10_3                   (0x08UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000008 */
+#define ADC_SQR3_SQ10_4                   (0x10UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000010 */
+
+#define ADC_SQR3_SQ11_Pos                 (6U)
+#define ADC_SQR3_SQ11_Msk                 (0x1FUL << ADC_SQR3_SQ11_Pos)        /*!< 0x000007C0 */
+#define ADC_SQR3_SQ11                     ADC_SQR3_SQ11_Msk                    /*!< ADC 11th conversion in regular sequence */
+#define ADC_SQR3_SQ11_0                   (0x01UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000040 */
+#define ADC_SQR3_SQ11_1                   (0x02UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000080 */
+#define ADC_SQR3_SQ11_2                   (0x04UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000100 */
+#define ADC_SQR3_SQ11_3                   (0x08UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000200 */
+#define ADC_SQR3_SQ11_4                   (0x10UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000400 */
+
+#define ADC_SQR3_SQ12_Pos                 (12U)
+#define ADC_SQR3_SQ12_Msk                 (0x1FUL << ADC_SQR3_SQ12_Pos)        /*!< 0x0001F000 */
+#define ADC_SQR3_SQ12                     ADC_SQR3_SQ12_Msk                    /*!< ADC 12th conversion in regular sequence */
+#define ADC_SQR3_SQ12_0                   (0x01UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00001000 */
+#define ADC_SQR3_SQ12_1                   (0x02UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00002000 */
+#define ADC_SQR3_SQ12_2                   (0x04UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00004000 */
+#define ADC_SQR3_SQ12_3                   (0x08UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00008000 */
+#define ADC_SQR3_SQ12_4                   (0x10UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00010000 */
+
+#define ADC_SQR3_SQ13_Pos                 (18U)
+#define ADC_SQR3_SQ13_Msk                 (0x1FUL << ADC_SQR3_SQ13_Pos)        /*!< 0x007C0000 */
+#define ADC_SQR3_SQ13                     ADC_SQR3_SQ13_Msk                    /*!< ADC 13th conversion in regular sequence */
+#define ADC_SQR3_SQ13_0                   (0x01UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00040000 */
+#define ADC_SQR3_SQ13_1                   (0x02UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00080000 */
+#define ADC_SQR3_SQ13_2                   (0x04UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00100000 */
+#define ADC_SQR3_SQ13_3                   (0x08UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00200000 */
+#define ADC_SQR3_SQ13_4                   (0x10UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00400000 */
+
+#define ADC_SQR3_SQ14_Pos                 (24U)
+#define ADC_SQR3_SQ14_Msk                 (0x1FUL << ADC_SQR3_SQ14_Pos)        /*!< 0x1F000000 */
+#define ADC_SQR3_SQ14                     ADC_SQR3_SQ14_Msk                    /*!< ADC 14th conversion in regular sequence */
+#define ADC_SQR3_SQ14_0                   (0x01UL << ADC_SQR3_SQ14_Pos)         /*!< 0x01000000 */
+#define ADC_SQR3_SQ14_1                   (0x02UL << ADC_SQR3_SQ14_Pos)         /*!< 0x02000000 */
+#define ADC_SQR3_SQ14_2                   (0x04UL << ADC_SQR3_SQ14_Pos)         /*!< 0x04000000 */
+#define ADC_SQR3_SQ14_3                   (0x08UL << ADC_SQR3_SQ14_Pos)         /*!< 0x08000000 */
+#define ADC_SQR3_SQ14_4                   (0x10UL << ADC_SQR3_SQ14_Pos)         /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR4 register  ********************/
+#define ADC_SQR4_SQ15_Pos                 (0U)
+#define ADC_SQR4_SQ15_Msk                 (0x1FUL << ADC_SQR4_SQ15_Pos)        /*!< 0x0000001F */
+#define ADC_SQR4_SQ15                     ADC_SQR4_SQ15_Msk                    /*!< ADC 15th conversion in regular sequence */
+#define ADC_SQR4_SQ15_0                   (0x01UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000001 */
+#define ADC_SQR4_SQ15_1                   (0x02UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000002 */
+#define ADC_SQR4_SQ15_2                   (0x04UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000004 */
+#define ADC_SQR4_SQ15_3                   (0x08UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000008 */
+#define ADC_SQR4_SQ15_4                   (0x10UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000010 */
+
+#define ADC_SQR4_SQ16_Pos                 (6U)
+#define ADC_SQR4_SQ16_Msk                 (0x1FUL << ADC_SQR4_SQ16_Pos)        /*!< 0x000007C0 */
+#define ADC_SQR4_SQ16                     ADC_SQR4_SQ16_Msk                    /*!< ADC 16th conversion in regular sequence */
+#define ADC_SQR4_SQ16_0                   (0x01UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000040 */
+#define ADC_SQR4_SQ16_1                   (0x02UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000080 */
+#define ADC_SQR4_SQ16_2                   (0x04UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000100 */
+#define ADC_SQR4_SQ16_3                   (0x08UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000200 */
+#define ADC_SQR4_SQ16_4                   (0x10UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000400 */
+/********************  Bit definition for ADC_DR register  ********************/
+#define ADC_DR_RDATA_Pos                  (0U)
+#define ADC_DR_RDATA_Msk                  (0xFFFFFFFFUL << ADC_DR_RDATA_Pos)   /*!< 0xFFFFFFFF */
+#define ADC_DR_RDATA                      ADC_DR_RDATA_Msk                     /*!< ADC regular Data converted */
+
+/********************  Bit definition for ADC_JSQR register  ********************/
+#define ADC_JSQR_JL_Pos                   (0U)
+#define ADC_JSQR_JL_Msk                   (0x3UL << ADC_JSQR_JL_Pos)           /*!< 0x00000003 */
+#define ADC_JSQR_JL                       ADC_JSQR_JL_Msk                      /*!< ADC injected channel sequence length */
+#define ADC_JSQR_JL_0                     (0x1UL << ADC_JSQR_JL_Pos)           /*!< 0x00000001 */
+#define ADC_JSQR_JL_1                     (0x2UL << ADC_JSQR_JL_Pos)           /*!< 0x00000002 */
+
+#define ADC_JSQR_JEXTSEL_Pos              (2U)
+#define ADC_JSQR_JEXTSEL_Msk              (0x1FUL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x0000007C */
+#define ADC_JSQR_JEXTSEL                  ADC_JSQR_JEXTSEL_Msk                 /*!< ADC external trigger selection for injected group */
+#define ADC_JSQR_JEXTSEL_0                (0x01UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000004 */
+#define ADC_JSQR_JEXTSEL_1                (0x02UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000008 */
+#define ADC_JSQR_JEXTSEL_2                (0x04UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000010 */
+#define ADC_JSQR_JEXTSEL_3                (0x08UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000020 */
+#define ADC_JSQR_JEXTSEL_4                (0x10UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000040 */
+
+#define ADC_JSQR_JEXTEN_Pos               (7U)
+#define ADC_JSQR_JEXTEN_Msk               (0x3UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000180 */
+#define ADC_JSQR_JEXTEN                   ADC_JSQR_JEXTEN_Msk                  /*!< ADC external trigger enable and polarity selection for injected channels */
+#define ADC_JSQR_JEXTEN_0                 (0x1UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000080 */
+#define ADC_JSQR_JEXTEN_1                 (0x2UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000100 */
+
+#define ADC_JSQR_JSQ1_Pos                 (9U)
+#define ADC_JSQR_JSQ1_Msk                 (0x1FUL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00003E00 */
+#define ADC_JSQR_JSQ1                     ADC_JSQR_JSQ1_Msk                    /*!< ADC 1st conversion in injected sequence */
+#define ADC_JSQR_JSQ1_0                   (0x01UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000200 */
+#define ADC_JSQR_JSQ1_1                   (0x02UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000400 */
+#define ADC_JSQR_JSQ1_2                   (0x04UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000800 */
+#define ADC_JSQR_JSQ1_3                   (0x08UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00001000 */
+#define ADC_JSQR_JSQ1_4                   (0x10UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00002000 */
+
+#define ADC_JSQR_JSQ2_Pos                 (15U)
+#define ADC_JSQR_JSQ2_Msk                 (0x1FUL << ADC_JSQR_JSQ2_Pos)        /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ2                     ADC_JSQR_JSQ2_Msk                    /*!< ADC 2nd conversion in injected sequence */
+#define ADC_JSQR_JSQ2_0                   (0x01UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00008000 */
+#define ADC_JSQR_JSQ2_1                   (0x02UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00010000 */
+#define ADC_JSQR_JSQ2_2                   (0x04UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00020000 */
+#define ADC_JSQR_JSQ2_3                   (0x08UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00040000 */
+#define ADC_JSQR_JSQ2_4                   (0x10UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00080000 */
+
+#define ADC_JSQR_JSQ3_Pos                 (21U)
+#define ADC_JSQR_JSQ3_Msk                 (0x1FUL << ADC_JSQR_JSQ3_Pos)        /*!< 0x03E00000 */
+#define ADC_JSQR_JSQ3                     ADC_JSQR_JSQ3_Msk                    /*!< ADC 3rd conversion in injected sequence */
+#define ADC_JSQR_JSQ3_0                   (0x01UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00200000 */
+#define ADC_JSQR_JSQ3_1                   (0x02UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00400000 */
+#define ADC_JSQR_JSQ3_2                   (0x04UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00800000 */
+#define ADC_JSQR_JSQ3_3                   (0x08UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x01000000 */
+#define ADC_JSQR_JSQ3_4                   (0x10UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x02000000 */
+
+#define ADC_JSQR_JSQ4_Pos                 (27U)
+#define ADC_JSQR_JSQ4_Msk                 (0x1FUL << ADC_JSQR_JSQ4_Pos)        /*!< 0xF8000000 */
+#define ADC_JSQR_JSQ4                     ADC_JSQR_JSQ4_Msk                    /*!< ADC 4th conversion in injected sequence */
+#define ADC_JSQR_JSQ4_0                   (0x01UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x08000000 */
+#define ADC_JSQR_JSQ4_1                   (0x02UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x10000000 */
+#define ADC_JSQR_JSQ4_2                   (0x04UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x20000000 */
+#define ADC_JSQR_JSQ4_3                   (0x08UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x40000000 */
+#define ADC_JSQR_JSQ4_4                   (0x10UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_OFR1 register  ********************/
+#define ADC_OFR1_OFFSET1_Pos              (0U)
+#define ADC_OFR1_OFFSET1_Msk              (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */
+#define ADC_OFR1_OFFSET1                  ADC_OFR1_OFFSET1_Msk                  /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
+#define ADC_OFR1_OFFSET1_0                (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
+#define ADC_OFR1_OFFSET1_1                (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
+#define ADC_OFR1_OFFSET1_2                (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
+#define ADC_OFR1_OFFSET1_3                (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
+#define ADC_OFR1_OFFSET1_4                (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
+#define ADC_OFR1_OFFSET1_5                (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
+#define ADC_OFR1_OFFSET1_6                (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
+#define ADC_OFR1_OFFSET1_7                (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
+#define ADC_OFR1_OFFSET1_8                (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
+#define ADC_OFR1_OFFSET1_9                (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
+#define ADC_OFR1_OFFSET1_10               (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
+#define ADC_OFR1_OFFSET1_11               (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
+#define ADC_OFR1_OFFSET1_12               (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */
+#define ADC_OFR1_OFFSET1_13               (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */
+#define ADC_OFR1_OFFSET1_14               (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */
+#define ADC_OFR1_OFFSET1_15               (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */
+#define ADC_OFR1_OFFSET1_16               (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */
+#define ADC_OFR1_OFFSET1_17               (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */
+#define ADC_OFR1_OFFSET1_18               (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */
+#define ADC_OFR1_OFFSET1_19               (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */
+#define ADC_OFR1_OFFSET1_20               (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */
+#define ADC_OFR1_OFFSET1_21               (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */
+#define ADC_OFR1_OFFSET1_22               (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */
+#define ADC_OFR1_OFFSET1_23               (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */
+#define ADC_OFR1_OFFSET1_24               (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */
+#define ADC_OFR1_OFFSET1_25               (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */
+
+#define ADC_OFR1_OFFSET1_CH_Pos           (26U)
+#define ADC_OFR1_OFFSET1_CH_Msk           (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x7C000000 */
+#define ADC_OFR1_OFFSET1_CH               ADC_OFR1_OFFSET1_CH_Msk               /*!< ADC Channel selection for the data offset 1 */
+#define ADC_OFR1_OFFSET1_CH_0             (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x04000000 */
+#define ADC_OFR1_OFFSET1_CH_1             (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x08000000 */
+#define ADC_OFR1_OFFSET1_CH_2             (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x10000000 */
+#define ADC_OFR1_OFFSET1_CH_3             (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x20000000 */
+#define ADC_OFR1_OFFSET1_CH_4             (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x40000000 */
+
+#define ADC_OFR1_SSATE_Pos                (31U)
+#define ADC_OFR1_SSATE_Msk                (0x1UL << ADC_OFR1_SSATE_Pos)         /*!< 0x80000000 */
+#define ADC_OFR1_SSATE                    ADC_OFR1_SSATE_Msk                    /*!< ADC Signed saturation Enable */
+
+
+/********************  Bit definition for ADC_OFR2 register  ********************/
+#define ADC_OFR2_OFFSET2_Pos              (0U)
+#define ADC_OFR2_OFFSET2_Msk              (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */
+#define ADC_OFR2_OFFSET2                  ADC_OFR2_OFFSET2_Msk                  /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
+#define ADC_OFR2_OFFSET2_0                (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
+#define ADC_OFR2_OFFSET2_1                (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
+#define ADC_OFR2_OFFSET2_2                (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
+#define ADC_OFR2_OFFSET2_3                (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
+#define ADC_OFR2_OFFSET2_4                (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
+#define ADC_OFR2_OFFSET2_5                (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
+#define ADC_OFR2_OFFSET2_6                (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
+#define ADC_OFR2_OFFSET2_7                (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
+#define ADC_OFR2_OFFSET2_8                (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
+#define ADC_OFR2_OFFSET2_9                (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
+#define ADC_OFR2_OFFSET2_10               (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
+#define ADC_OFR2_OFFSET2_11               (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
+#define ADC_OFR2_OFFSET2_12               (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */
+#define ADC_OFR2_OFFSET2_13               (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */
+#define ADC_OFR2_OFFSET2_14               (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */
+#define ADC_OFR2_OFFSET2_15               (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */
+#define ADC_OFR2_OFFSET2_16               (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */
+#define ADC_OFR2_OFFSET2_17               (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */
+#define ADC_OFR2_OFFSET2_18               (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */
+#define ADC_OFR2_OFFSET2_19               (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */
+#define ADC_OFR2_OFFSET2_20               (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */
+#define ADC_OFR2_OFFSET2_21               (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */
+#define ADC_OFR2_OFFSET2_22               (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */
+#define ADC_OFR2_OFFSET2_23               (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */
+#define ADC_OFR2_OFFSET2_24               (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */
+#define ADC_OFR2_OFFSET2_25               (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */
+
+#define ADC_OFR2_OFFSET2_CH_Pos           (26U)
+#define ADC_OFR2_OFFSET2_CH_Msk           (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x7C000000 */
+#define ADC_OFR2_OFFSET2_CH               ADC_OFR2_OFFSET2_CH_Msk               /*!< ADC Channel selection for the data offset 2 */
+#define ADC_OFR2_OFFSET2_CH_0             (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x04000000 */
+#define ADC_OFR2_OFFSET2_CH_1             (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x08000000 */
+#define ADC_OFR2_OFFSET2_CH_2             (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x10000000 */
+#define ADC_OFR2_OFFSET2_CH_3             (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x20000000 */
+#define ADC_OFR2_OFFSET2_CH_4             (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x40000000 */
+
+#define ADC_OFR2_SSATE_Pos                (31U)
+#define ADC_OFR2_SSATE_Msk                (0x1UL << ADC_OFR2_SSATE_Pos)         /*!< 0x80000000 */
+#define ADC_OFR2_SSATE                    ADC_OFR2_SSATE_Msk                    /*!< ADC Signed saturation Enable */
+
+
+/********************  Bit definition for ADC_OFR3 register  ********************/
+#define ADC_OFR3_OFFSET3_Pos              (0U)
+#define ADC_OFR3_OFFSET3_Msk              (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */
+#define ADC_OFR3_OFFSET3                  ADC_OFR3_OFFSET3_Msk                  /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
+#define ADC_OFR3_OFFSET3_0                (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
+#define ADC_OFR3_OFFSET3_1                (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
+#define ADC_OFR3_OFFSET3_2                (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
+#define ADC_OFR3_OFFSET3_3                (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
+#define ADC_OFR3_OFFSET3_4                (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
+#define ADC_OFR3_OFFSET3_5                (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
+#define ADC_OFR3_OFFSET3_6                (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
+#define ADC_OFR3_OFFSET3_7                (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
+#define ADC_OFR3_OFFSET3_8                (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
+#define ADC_OFR3_OFFSET3_9                (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
+#define ADC_OFR3_OFFSET3_10               (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
+#define ADC_OFR3_OFFSET3_11               (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
+#define ADC_OFR3_OFFSET3_12               (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */
+#define ADC_OFR3_OFFSET3_13               (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */
+#define ADC_OFR3_OFFSET3_14               (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */
+#define ADC_OFR3_OFFSET3_15               (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */
+#define ADC_OFR3_OFFSET3_16               (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */
+#define ADC_OFR3_OFFSET3_17               (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */
+#define ADC_OFR3_OFFSET3_18               (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */
+#define ADC_OFR3_OFFSET3_19               (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */
+#define ADC_OFR3_OFFSET3_20               (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */
+#define ADC_OFR3_OFFSET3_21               (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */
+#define ADC_OFR3_OFFSET3_22               (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */
+#define ADC_OFR3_OFFSET3_23               (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */
+#define ADC_OFR3_OFFSET3_24               (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */
+#define ADC_OFR3_OFFSET3_25               (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */
+
+#define ADC_OFR3_OFFSET3_CH_Pos           (26U)
+#define ADC_OFR3_OFFSET3_CH_Msk           (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x7C000000 */
+#define ADC_OFR3_OFFSET3_CH               ADC_OFR3_OFFSET3_CH_Msk               /*!< ADC Channel selection for the data offset 3 */
+#define ADC_OFR3_OFFSET3_CH_0             (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x04000000 */
+#define ADC_OFR3_OFFSET3_CH_1             (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x08000000 */
+#define ADC_OFR3_OFFSET3_CH_2             (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x10000000 */
+#define ADC_OFR3_OFFSET3_CH_3             (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x20000000 */
+#define ADC_OFR3_OFFSET3_CH_4             (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x40000000 */
+
+#define ADC_OFR3_SSATE_Pos                (31U)
+#define ADC_OFR3_SSATE_Msk                (0x1UL << ADC_OFR3_SSATE_Pos)         /*!< 0x80000000 */
+#define ADC_OFR3_SSATE                    ADC_OFR3_SSATE_Msk                    /*!< ADC Signed saturation Enable */
+
+
+/********************  Bit definition for ADC_OFR4 register  ********************/
+#define ADC_OFR4_OFFSET4_Pos              (0U)
+#define ADC_OFR4_OFFSET4_Msk              (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */
+#define ADC_OFR4_OFFSET4                  ADC_OFR4_OFFSET4_Msk                  /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
+#define ADC_OFR4_OFFSET4_0                (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
+#define ADC_OFR4_OFFSET4_1                (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
+#define ADC_OFR4_OFFSET4_2                (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
+#define ADC_OFR4_OFFSET4_3                (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
+#define ADC_OFR4_OFFSET4_4                (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
+#define ADC_OFR4_OFFSET4_5                (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
+#define ADC_OFR4_OFFSET4_6                (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
+#define ADC_OFR4_OFFSET4_7                (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
+#define ADC_OFR4_OFFSET4_8                (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
+#define ADC_OFR4_OFFSET4_9                (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
+#define ADC_OFR4_OFFSET4_10               (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
+#define ADC_OFR4_OFFSET4_11               (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
+#define ADC_OFR4_OFFSET4_12               (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */
+#define ADC_OFR4_OFFSET4_13               (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */
+#define ADC_OFR4_OFFSET4_14               (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */
+#define ADC_OFR4_OFFSET4_15               (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */
+#define ADC_OFR4_OFFSET4_16               (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */
+#define ADC_OFR4_OFFSET4_17               (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */
+#define ADC_OFR4_OFFSET4_18               (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */
+#define ADC_OFR4_OFFSET4_19               (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */
+#define ADC_OFR4_OFFSET4_20               (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */
+#define ADC_OFR4_OFFSET4_21               (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */
+#define ADC_OFR4_OFFSET4_22               (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */
+#define ADC_OFR4_OFFSET4_23               (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */
+#define ADC_OFR4_OFFSET4_24               (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */
+#define ADC_OFR4_OFFSET4_25               (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */
+
+#define ADC_OFR4_OFFSET4_CH_Pos           (26U)
+#define ADC_OFR4_OFFSET4_CH_Msk           (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x7C000000 */
+#define ADC_OFR4_OFFSET4_CH               ADC_OFR4_OFFSET4_CH_Msk               /*!< ADC Channel selection for the data offset 4 */
+#define ADC_OFR4_OFFSET4_CH_0             (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x04000000 */
+#define ADC_OFR4_OFFSET4_CH_1             (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x08000000 */
+#define ADC_OFR4_OFFSET4_CH_2             (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x10000000 */
+#define ADC_OFR4_OFFSET4_CH_3             (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x20000000 */
+#define ADC_OFR4_OFFSET4_CH_4             (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x40000000 */
+
+#define ADC_OFR4_SSATE_Pos                (31U)
+#define ADC_OFR4_SSATE_Msk                (0x1UL << ADC_OFR4_SSATE_Pos)         /*!< 0x80000000 */
+#define ADC_OFR4_SSATE                    ADC_OFR4_SSATE_Msk                    /*!< ADC Signed saturation Enable */
+
+
+/********************  Bit definition for ADC_JDR1 register  ********************/
+#define ADC_JDR1_JDATA_Pos                (0U)
+#define ADC_JDR1_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos)  /*!< 0xFFFFFFFF */
+#define ADC_JDR1_JDATA                    ADC_JDR1_JDATA_Msk                    /*!< ADC Injected DATA */
+#define ADC_JDR1_JDATA_0                  (0x00000001UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000001 */
+#define ADC_JDR1_JDATA_1                  (0x00000002UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000002 */
+#define ADC_JDR1_JDATA_2                  (0x00000004UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000004 */
+#define ADC_JDR1_JDATA_3                  (0x00000008UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000008 */
+#define ADC_JDR1_JDATA_4                  (0x00000010UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000010 */
+#define ADC_JDR1_JDATA_5                  (0x00000020UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000020 */
+#define ADC_JDR1_JDATA_6                  (0x00000040UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000040 */
+#define ADC_JDR1_JDATA_7                  (0x00000080UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000080 */
+#define ADC_JDR1_JDATA_8                  (0x00000100UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000100 */
+#define ADC_JDR1_JDATA_9                  (0x00000200UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000200 */
+#define ADC_JDR1_JDATA_10                 (0x00000400UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000400 */
+#define ADC_JDR1_JDATA_11                 (0x00000800UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000800 */
+#define ADC_JDR1_JDATA_12                 (0x00001000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00001000 */
+#define ADC_JDR1_JDATA_13                 (0x00002000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00002000 */
+#define ADC_JDR1_JDATA_14                 (0x00004000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00004000 */
+#define ADC_JDR1_JDATA_15                 (0x00008000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00008000 */
+#define ADC_JDR1_JDATA_16                 (0x00010000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00010000 */
+#define ADC_JDR1_JDATA_17                 (0x00020000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00020000 */
+#define ADC_JDR1_JDATA_18                 (0x00040000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00040000 */
+#define ADC_JDR1_JDATA_19                 (0x00080000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00080000 */
+#define ADC_JDR1_JDATA_20                 (0x00100000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00100000 */
+#define ADC_JDR1_JDATA_21                 (0x00200000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00200000 */
+#define ADC_JDR1_JDATA_22                 (0x00400000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00400000 */
+#define ADC_JDR1_JDATA_23                 (0x00800000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00800000 */
+#define ADC_JDR1_JDATA_24                 (0x01000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x01000000 */
+#define ADC_JDR1_JDATA_25                 (0x02000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x02000000 */
+#define ADC_JDR1_JDATA_26                 (0x04000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x04000000 */
+#define ADC_JDR1_JDATA_27                 (0x08000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x08000000 */
+#define ADC_JDR1_JDATA_28                 (0x10000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x10000000 */
+#define ADC_JDR1_JDATA_29                 (0x20000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x20000000 */
+#define ADC_JDR1_JDATA_30                 (0x40000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x40000000 */
+#define ADC_JDR1_JDATA_31                 (0x80000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_JDR2 register  ********************/
+#define ADC_JDR2_JDATA_Pos                (0U)
+#define ADC_JDR2_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos)  /*!< 0xFFFFFFFF */
+#define ADC_JDR2_JDATA                    ADC_JDR2_JDATA_Msk                    /*!< ADC Injected DATA */
+#define ADC_JDR2_JDATA_0                  (0x00000001UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000001 */
+#define ADC_JDR2_JDATA_1                  (0x00000002UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000002 */
+#define ADC_JDR2_JDATA_2                  (0x00000004UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000004 */
+#define ADC_JDR2_JDATA_3                  (0x00000008UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000008 */
+#define ADC_JDR2_JDATA_4                  (0x00000010UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000010 */
+#define ADC_JDR2_JDATA_5                  (0x00000020UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000020 */
+#define ADC_JDR2_JDATA_6                  (0x00000040UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000040 */
+#define ADC_JDR2_JDATA_7                  (0x00000080UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000080 */
+#define ADC_JDR2_JDATA_8                  (0x00000100UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000100 */
+#define ADC_JDR2_JDATA_9                  (0x00000200UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000200 */
+#define ADC_JDR2_JDATA_10                 (0x00000400UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000400 */
+#define ADC_JDR2_JDATA_11                 (0x00000800UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000800 */
+#define ADC_JDR2_JDATA_12                 (0x00001000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00001000 */
+#define ADC_JDR2_JDATA_13                 (0x00002000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00002000 */
+#define ADC_JDR2_JDATA_14                 (0x00004000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00004000 */
+#define ADC_JDR2_JDATA_15                 (0x00008000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00008000 */
+#define ADC_JDR2_JDATA_16                 (0x00010000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00010000 */
+#define ADC_JDR2_JDATA_17                 (0x00020000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00020000 */
+#define ADC_JDR2_JDATA_18                 (0x00040000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00040000 */
+#define ADC_JDR2_JDATA_19                 (0x00080000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00080000 */
+#define ADC_JDR2_JDATA_20                 (0x00100000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00100000 */
+#define ADC_JDR2_JDATA_21                 (0x00200000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00200000 */
+#define ADC_JDR2_JDATA_22                 (0x00400000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00400000 */
+#define ADC_JDR2_JDATA_23                 (0x00800000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00800000 */
+#define ADC_JDR2_JDATA_24                 (0x01000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x01000000 */
+#define ADC_JDR2_JDATA_25                 (0x02000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x02000000 */
+#define ADC_JDR2_JDATA_26                 (0x04000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x04000000 */
+#define ADC_JDR2_JDATA_27                 (0x08000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x08000000 */
+#define ADC_JDR2_JDATA_28                 (0x10000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x10000000 */
+#define ADC_JDR2_JDATA_29                 (0x20000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x20000000 */
+#define ADC_JDR2_JDATA_30                 (0x40000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x40000000 */
+#define ADC_JDR2_JDATA_31                 (0x80000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_JDR3 register  ********************/
+#define ADC_JDR3_JDATA_Pos                (0U)
+#define ADC_JDR3_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos)  /*!< 0xFFFFFFFF */
+#define ADC_JDR3_JDATA                    ADC_JDR3_JDATA_Msk                    /*!< ADC Injected DATA */
+#define ADC_JDR3_JDATA_0                  (0x00000001UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000001 */
+#define ADC_JDR3_JDATA_1                  (0x00000002UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000002 */
+#define ADC_JDR3_JDATA_2                  (0x00000004UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000004 */
+#define ADC_JDR3_JDATA_3                  (0x00000008UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000008 */
+#define ADC_JDR3_JDATA_4                  (0x00000010UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000010 */
+#define ADC_JDR3_JDATA_5                  (0x00000020UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000020 */
+#define ADC_JDR3_JDATA_6                  (0x00000040UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000040 */
+#define ADC_JDR3_JDATA_7                  (0x00000080UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000080 */
+#define ADC_JDR3_JDATA_8                  (0x00000100UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000100 */
+#define ADC_JDR3_JDATA_9                  (0x00000200UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000200 */
+#define ADC_JDR3_JDATA_10                 (0x00000400UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000400 */
+#define ADC_JDR3_JDATA_11                 (0x00000800UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000800 */
+#define ADC_JDR3_JDATA_12                 (0x00001000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00001000 */
+#define ADC_JDR3_JDATA_13                 (0x00002000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00002000 */
+#define ADC_JDR3_JDATA_14                 (0x00004000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00004000 */
+#define ADC_JDR3_JDATA_15                 (0x00008000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00008000 */
+#define ADC_JDR3_JDATA_16                 (0x00010000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00010000 */
+#define ADC_JDR3_JDATA_17                 (0x00020000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00020000 */
+#define ADC_JDR3_JDATA_18                 (0x00040000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00040000 */
+#define ADC_JDR3_JDATA_19                 (0x00080000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00080000 */
+#define ADC_JDR3_JDATA_20                 (0x00100000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00100000 */
+#define ADC_JDR3_JDATA_21                 (0x00200000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00200000 */
+#define ADC_JDR3_JDATA_22                 (0x00400000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00400000 */
+#define ADC_JDR3_JDATA_23                 (0x00800000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00800000 */
+#define ADC_JDR3_JDATA_24                 (0x01000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x01000000 */
+#define ADC_JDR3_JDATA_25                 (0x02000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x02000000 */
+#define ADC_JDR3_JDATA_26                 (0x04000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x04000000 */
+#define ADC_JDR3_JDATA_27                 (0x08000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x08000000 */
+#define ADC_JDR3_JDATA_28                 (0x10000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x10000000 */
+#define ADC_JDR3_JDATA_29                 (0x20000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x20000000 */
+#define ADC_JDR3_JDATA_30                 (0x40000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x40000000 */
+#define ADC_JDR3_JDATA_31                 (0x80000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_JDR4 register  ********************/
+#define ADC_JDR4_JDATA_Pos                (0U)
+#define ADC_JDR4_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos)  /*!< 0xFFFFFFFF */
+#define ADC_JDR4_JDATA                    ADC_JDR4_JDATA_Msk                    /*!< ADC Injected DATA */
+#define ADC_JDR4_JDATA_0                  (0x00000001UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000001 */
+#define ADC_JDR4_JDATA_1                  (0x00000002UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000002 */
+#define ADC_JDR4_JDATA_2                  (0x00000004UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000004 */
+#define ADC_JDR4_JDATA_3                  (0x00000008UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000008 */
+#define ADC_JDR4_JDATA_4                  (0x00000010UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000010 */
+#define ADC_JDR4_JDATA_5                  (0x00000020UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000020 */
+#define ADC_JDR4_JDATA_6                  (0x00000040UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000040 */
+#define ADC_JDR4_JDATA_7                  (0x00000080UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000080 */
+#define ADC_JDR4_JDATA_8                  (0x00000100UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000100 */
+#define ADC_JDR4_JDATA_9                  (0x00000200UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000200 */
+#define ADC_JDR4_JDATA_10                 (0x00000400UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000400 */
+#define ADC_JDR4_JDATA_11                 (0x00000800UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000800 */
+#define ADC_JDR4_JDATA_12                 (0x00001000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00001000 */
+#define ADC_JDR4_JDATA_13                 (0x00002000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00002000 */
+#define ADC_JDR4_JDATA_14                 (0x00004000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00004000 */
+#define ADC_JDR4_JDATA_15                 (0x00008000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00008000 */
+#define ADC_JDR4_JDATA_16                 (0x00010000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00010000 */
+#define ADC_JDR4_JDATA_17                 (0x00020000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00020000 */
+#define ADC_JDR4_JDATA_18                 (0x00040000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00040000 */
+#define ADC_JDR4_JDATA_19                 (0x00080000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00080000 */
+#define ADC_JDR4_JDATA_20                 (0x00100000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00100000 */
+#define ADC_JDR4_JDATA_21                 (0x00200000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00200000 */
+#define ADC_JDR4_JDATA_22                 (0x00400000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00400000 */
+#define ADC_JDR4_JDATA_23                 (0x00800000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00800000 */
+#define ADC_JDR4_JDATA_24                 (0x01000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x01000000 */
+#define ADC_JDR4_JDATA_25                 (0x02000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x02000000 */
+#define ADC_JDR4_JDATA_26                 (0x04000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x04000000 */
+#define ADC_JDR4_JDATA_27                 (0x08000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x08000000 */
+#define ADC_JDR4_JDATA_28                 (0x10000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x10000000 */
+#define ADC_JDR4_JDATA_29                 (0x20000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x20000000 */
+#define ADC_JDR4_JDATA_30                 (0x40000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x40000000 */
+#define ADC_JDR4_JDATA_31                 (0x80000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_AWD2CR register  ********************/
+#define ADC_AWD2CR_AWD2CH_Pos             (0U)
+#define ADC_AWD2CR_AWD2CH_Msk             (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x000FFFFF */
+#define ADC_AWD2CR_AWD2CH                 ADC_AWD2CR_AWD2CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */
+#define ADC_AWD2CR_AWD2CH_0               (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000001 */
+#define ADC_AWD2CR_AWD2CH_1               (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000002 */
+#define ADC_AWD2CR_AWD2CH_2               (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000004 */
+#define ADC_AWD2CR_AWD2CH_3               (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000008 */
+#define ADC_AWD2CR_AWD2CH_4               (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000010 */
+#define ADC_AWD2CR_AWD2CH_5               (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000020 */
+#define ADC_AWD2CR_AWD2CH_6               (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000040 */
+#define ADC_AWD2CR_AWD2CH_7               (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000080 */
+#define ADC_AWD2CR_AWD2CH_8               (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000100 */
+#define ADC_AWD2CR_AWD2CH_9               (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000200 */
+#define ADC_AWD2CR_AWD2CH_10              (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000400 */
+#define ADC_AWD2CR_AWD2CH_11              (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000800 */
+#define ADC_AWD2CR_AWD2CH_12              (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00001000 */
+#define ADC_AWD2CR_AWD2CH_13              (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00002000 */
+#define ADC_AWD2CR_AWD2CH_14              (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00004000 */
+#define ADC_AWD2CR_AWD2CH_15              (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00008000 */
+#define ADC_AWD2CR_AWD2CH_16              (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00010000 */
+#define ADC_AWD2CR_AWD2CH_17              (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00020000 */
+#define ADC_AWD2CR_AWD2CH_18              (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00040000 */
+#define ADC_AWD2CR_AWD2CH_19              (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00080000 */
+
+/********************  Bit definition for ADC_AWD3CR register  ********************/
+#define ADC_AWD3CR_AWD3CH_Pos             (0U)
+#define ADC_AWD3CR_AWD3CH_Msk             (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x000FFFFF */
+#define ADC_AWD3CR_AWD3CH                 ADC_AWD3CR_AWD3CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */
+#define ADC_AWD3CR_AWD3CH_0               (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000001 */
+#define ADC_AWD3CR_AWD3CH_1               (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000002 */
+#define ADC_AWD3CR_AWD3CH_2               (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000004 */
+#define ADC_AWD3CR_AWD3CH_3               (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000008 */
+#define ADC_AWD3CR_AWD3CH_4               (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000010 */
+#define ADC_AWD3CR_AWD3CH_5               (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000020 */
+#define ADC_AWD3CR_AWD3CH_6               (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000040 */
+#define ADC_AWD3CR_AWD3CH_7               (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000080 */
+#define ADC_AWD3CR_AWD3CH_8               (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000100 */
+#define ADC_AWD3CR_AWD3CH_9               (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000200 */
+#define ADC_AWD3CR_AWD3CH_10              (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000400 */
+#define ADC_AWD3CR_AWD3CH_11              (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000800 */
+#define ADC_AWD3CR_AWD3CH_12              (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00001000 */
+#define ADC_AWD3CR_AWD3CH_13              (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00002000 */
+#define ADC_AWD3CR_AWD3CH_14              (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00004000 */
+#define ADC_AWD3CR_AWD3CH_15              (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00008000 */
+#define ADC_AWD3CR_AWD3CH_16              (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00010000 */
+#define ADC_AWD3CR_AWD3CH_17              (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00020000 */
+#define ADC_AWD3CR_AWD3CH_18              (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00040000 */
+#define ADC_AWD3CR_AWD3CH_19              (0x80000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00080000 */
+
+/********************  Bit definition for ADC_DIFSEL register  ********************/
+#define ADC_DIFSEL_DIFSEL_Pos             (0U)
+#define ADC_DIFSEL_DIFSEL_Msk             (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x000FFFFF */
+#define ADC_DIFSEL_DIFSEL                 ADC_DIFSEL_DIFSEL_Msk                 /*!< ADC differential modes for channels 1 to 18 */
+#define ADC_DIFSEL_DIFSEL_0               (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000001 */
+#define ADC_DIFSEL_DIFSEL_1               (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000002 */
+#define ADC_DIFSEL_DIFSEL_2               (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000004 */
+#define ADC_DIFSEL_DIFSEL_3               (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000008 */
+#define ADC_DIFSEL_DIFSEL_4               (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000010 */
+#define ADC_DIFSEL_DIFSEL_5               (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000020 */
+#define ADC_DIFSEL_DIFSEL_6               (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000040 */
+#define ADC_DIFSEL_DIFSEL_7               (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000080 */
+#define ADC_DIFSEL_DIFSEL_8               (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000100 */
+#define ADC_DIFSEL_DIFSEL_9               (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000200 */
+#define ADC_DIFSEL_DIFSEL_10              (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000400 */
+#define ADC_DIFSEL_DIFSEL_11              (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000800 */
+#define ADC_DIFSEL_DIFSEL_12              (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00001000 */
+#define ADC_DIFSEL_DIFSEL_13              (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00002000 */
+#define ADC_DIFSEL_DIFSEL_14              (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00004000 */
+#define ADC_DIFSEL_DIFSEL_15              (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00008000 */
+#define ADC_DIFSEL_DIFSEL_16              (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00010000 */
+#define ADC_DIFSEL_DIFSEL_17              (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00020000 */
+#define ADC_DIFSEL_DIFSEL_18              (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00040000 */
+#define ADC_DIFSEL_DIFSEL_19              (0x80000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00080000 */
+
+/********************  Bit definition for ADC_CALFACT register  ********************/
+#define ADC_CALFACT_CALFACT_S_Pos         (0U)
+#define ADC_CALFACT_CALFACT_S_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */
+#define ADC_CALFACT_CALFACT_S             ADC_CALFACT_CALFACT_S_Msk              /*!< ADC calibration factors in single-ended mode */
+#define ADC_CALFACT_CALFACT_S_0           (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
+#define ADC_CALFACT_CALFACT_S_1           (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
+#define ADC_CALFACT_CALFACT_S_2           (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
+#define ADC_CALFACT_CALFACT_S_3           (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
+#define ADC_CALFACT_CALFACT_S_4           (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
+#define ADC_CALFACT_CALFACT_S_5           (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
+#define ADC_CALFACT_CALFACT_S_6           (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
+#define ADC_CALFACT_CALFACT_S_7           (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */
+#define ADC_CALFACT_CALFACT_S_8           (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */
+#define ADC_CALFACT_CALFACT_S_9           (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */
+#define ADC_CALFACT_CALFACT_S_10          (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */
+#define ADC_CALFACT_CALFACT_D_Pos         (16U)
+#define ADC_CALFACT_CALFACT_D_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */
+#define ADC_CALFACT_CALFACT_D             ADC_CALFACT_CALFACT_D_Msk              /*!< ADC calibration factors in differential mode */
+#define ADC_CALFACT_CALFACT_D_0           (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
+#define ADC_CALFACT_CALFACT_D_1           (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
+#define ADC_CALFACT_CALFACT_D_2           (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
+#define ADC_CALFACT_CALFACT_D_3           (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
+#define ADC_CALFACT_CALFACT_D_4           (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
+#define ADC_CALFACT_CALFACT_D_5           (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
+#define ADC_CALFACT_CALFACT_D_6           (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
+#define ADC_CALFACT_CALFACT_D_7           (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */
+#define ADC_CALFACT_CALFACT_D_8           (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */
+#define ADC_CALFACT_CALFACT_D_9           (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */
+#define ADC_CALFACT_CALFACT_D_10          (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */
+
+/********************  Bit definition for ADC_CALFACT2 register  ********************/
+#define ADC_CALFACT2_LINCALFACT_Pos       (0U)
+#define ADC_CALFACT2_LINCALFACT_Msk       (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */
+#define ADC_CALFACT2_LINCALFACT           ADC_CALFACT2_LINCALFACT_Msk                   /*!< ADC Linearity calibration factors */
+#define ADC_CALFACT2_LINCALFACT_0         (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */
+#define ADC_CALFACT2_LINCALFACT_1         (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */
+#define ADC_CALFACT2_LINCALFACT_2         (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */
+#define ADC_CALFACT2_LINCALFACT_3         (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */
+#define ADC_CALFACT2_LINCALFACT_4         (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */
+#define ADC_CALFACT2_LINCALFACT_5         (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */
+#define ADC_CALFACT2_LINCALFACT_6         (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */
+#define ADC_CALFACT2_LINCALFACT_7         (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */
+#define ADC_CALFACT2_LINCALFACT_8         (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */
+#define ADC_CALFACT2_LINCALFACT_9         (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */
+#define ADC_CALFACT2_LINCALFACT_10        (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */
+#define ADC_CALFACT2_LINCALFACT_11        (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */
+#define ADC_CALFACT2_LINCALFACT_12        (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */
+#define ADC_CALFACT2_LINCALFACT_13        (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */
+#define ADC_CALFACT2_LINCALFACT_14        (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */
+#define ADC_CALFACT2_LINCALFACT_15        (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */
+#define ADC_CALFACT2_LINCALFACT_16        (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */
+#define ADC_CALFACT2_LINCALFACT_17        (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */
+#define ADC_CALFACT2_LINCALFACT_18        (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */
+#define ADC_CALFACT2_LINCALFACT_19        (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */
+#define ADC_CALFACT2_LINCALFACT_20        (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */
+#define ADC_CALFACT2_LINCALFACT_21        (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */
+#define ADC_CALFACT2_LINCALFACT_22        (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */
+#define ADC_CALFACT2_LINCALFACT_23        (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */
+#define ADC_CALFACT2_LINCALFACT_24        (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */
+#define ADC_CALFACT2_LINCALFACT_25        (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */
+#define ADC_CALFACT2_LINCALFACT_26        (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */
+#define ADC_CALFACT2_LINCALFACT_27        (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */
+#define ADC_CALFACT2_LINCALFACT_28        (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */
+#define ADC_CALFACT2_LINCALFACT_29        (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */
+
+/*************************  ADC Common registers  *****************************/
+/********************  Bit definition for ADC_CSR register  ********************/
+#define ADC_CSR_ADRDY_MST_Pos             (0U)
+#define ADC_CSR_ADRDY_MST_Msk             (0x1UL << ADC_CSR_ADRDY_MST_Pos)     /*!< 0x00000001 */
+#define ADC_CSR_ADRDY_MST                 ADC_CSR_ADRDY_MST_Msk                /*!< Master ADC ready */
+#define ADC_CSR_EOSMP_MST_Pos             (1U)
+#define ADC_CSR_EOSMP_MST_Msk             (0x1UL << ADC_CSR_EOSMP_MST_Pos)     /*!< 0x00000002 */
+#define ADC_CSR_EOSMP_MST                 ADC_CSR_EOSMP_MST_Msk                /*!< End of sampling phase flag of the master ADC */
+#define ADC_CSR_EOC_MST_Pos               (2U)
+#define ADC_CSR_EOC_MST_Msk               (0x1UL << ADC_CSR_EOC_MST_Pos)       /*!< 0x00000004 */
+#define ADC_CSR_EOC_MST                   ADC_CSR_EOC_MST_Msk                  /*!< End of regular conversion of the master ADC */
+#define ADC_CSR_EOS_MST_Pos               (3U)
+#define ADC_CSR_EOS_MST_Msk               (0x1UL << ADC_CSR_EOS_MST_Pos)       /*!< 0x00000008 */
+#define ADC_CSR_EOS_MST                   ADC_CSR_EOS_MST_Msk                  /*!< End of regular sequence flag of the master ADC */
+#define ADC_CSR_OVR_MST_Pos               (4U)
+#define ADC_CSR_OVR_MST_Msk               (0x1UL << ADC_CSR_OVR_MST_Pos)       /*!< 0x00000010 */
+#define ADC_CSR_OVR_MST                   ADC_CSR_OVR_MST_Msk                  /*!< Overrun flag of the master ADC */
+#define ADC_CSR_JEOC_MST_Pos              (5U)
+#define ADC_CSR_JEOC_MST_Msk              (0x1UL << ADC_CSR_JEOC_MST_Pos)      /*!< 0x00000020 */
+#define ADC_CSR_JEOC_MST                  ADC_CSR_JEOC_MST_Msk                 /*!< End of injected conversion of the master ADC */
+#define ADC_CSR_JEOS_MST_Pos              (6U)
+#define ADC_CSR_JEOS_MST_Msk              (0x1UL << ADC_CSR_JEOS_MST_Pos)      /*!< 0x00000040 */
+#define ADC_CSR_JEOS_MST                  ADC_CSR_JEOS_MST_Msk                 /*!< End of injected sequence flag of the master ADC */
+#define ADC_CSR_AWD1_MST_Pos              (7U)
+#define ADC_CSR_AWD1_MST_Msk              (0x1UL << ADC_CSR_AWD1_MST_Pos)      /*!< 0x00000080 */
+#define ADC_CSR_AWD1_MST                  ADC_CSR_AWD1_MST_Msk                 /*!< Analog watchdog 1 flag of the master ADC */
+#define ADC_CSR_AWD2_MST_Pos              (8U)
+#define ADC_CSR_AWD2_MST_Msk              (0x1UL << ADC_CSR_AWD2_MST_Pos)      /*!< 0x00000100 */
+#define ADC_CSR_AWD2_MST                  ADC_CSR_AWD2_MST_Msk                 /*!< Analog watchdog 2 flag of the master ADC */
+#define ADC_CSR_AWD3_MST_Pos              (9U)
+#define ADC_CSR_AWD3_MST_Msk              (0x1UL << ADC_CSR_AWD3_MST_Pos)      /*!< 0x00000200 */
+#define ADC_CSR_AWD3_MST                  ADC_CSR_AWD3_MST_Msk                 /*!< Analog watchdog 3 flag of the master ADC */
+#define ADC_CSR_JQOVF_MST_Pos             (10U)
+#define ADC_CSR_JQOVF_MST_Msk             (0x1UL << ADC_CSR_JQOVF_MST_Pos)     /*!< 0x00000400 */
+#define ADC_CSR_JQOVF_MST                 ADC_CSR_JQOVF_MST_Msk                /*!< Injected context queue overflow flag of the master ADC */
+#define ADC_CSR_ADRDY_SLV_Pos             (16U)
+#define ADC_CSR_ADRDY_SLV_Msk             (0x1UL << ADC_CSR_ADRDY_SLV_Pos)     /*!< 0x00010000 */
+#define ADC_CSR_ADRDY_SLV                 ADC_CSR_ADRDY_SLV_Msk                /*!< Slave ADC ready */
+#define ADC_CSR_EOSMP_SLV_Pos             (17U)
+#define ADC_CSR_EOSMP_SLV_Msk             (0x1UL << ADC_CSR_EOSMP_SLV_Pos)     /*!< 0x00020000 */
+#define ADC_CSR_EOSMP_SLV                 ADC_CSR_EOSMP_SLV_Msk                /*!< End of sampling phase flag of the slave ADC */
+#define ADC_CSR_EOC_SLV_Pos               (18U)
+#define ADC_CSR_EOC_SLV_Msk               (0x1UL << ADC_CSR_EOC_SLV_Pos)       /*!< 0x00040000 */
+#define ADC_CSR_EOC_SLV                   ADC_CSR_EOC_SLV_Msk                  /*!< End of regular conversion of the slave ADC */
+#define ADC_CSR_EOS_SLV_Pos               (19U)
+#define ADC_CSR_EOS_SLV_Msk               (0x1UL << ADC_CSR_EOS_SLV_Pos)       /*!< 0x00080000 */
+#define ADC_CSR_EOS_SLV                   ADC_CSR_EOS_SLV_Msk                  /*!< End of regular sequence flag of the slave ADC */
+#define ADC_CSR_OVR_SLV_Pos               (20U)
+#define ADC_CSR_OVR_SLV_Msk               (0x1UL << ADC_CSR_OVR_SLV_Pos)       /*!< 0x00100000 */
+#define ADC_CSR_OVR_SLV                   ADC_CSR_OVR_SLV_Msk                  /*!< Overrun flag of the slave ADC */
+#define ADC_CSR_JEOC_SLV_Pos              (21U)
+#define ADC_CSR_JEOC_SLV_Msk              (0x1UL << ADC_CSR_JEOC_SLV_Pos)      /*!< 0x00200000 */
+#define ADC_CSR_JEOC_SLV                  ADC_CSR_JEOC_SLV_Msk                 /*!< End of injected conversion of the slave ADC */
+#define ADC_CSR_JEOS_SLV_Pos              (22U)
+#define ADC_CSR_JEOS_SLV_Msk              (0x1UL << ADC_CSR_JEOS_SLV_Pos)      /*!< 0x00400000 */
+#define ADC_CSR_JEOS_SLV                  ADC_CSR_JEOS_SLV_Msk                 /*!< End of injected sequence flag of the slave ADC */
+#define ADC_CSR_AWD1_SLV_Pos              (23U)
+#define ADC_CSR_AWD1_SLV_Msk              (0x1UL << ADC_CSR_AWD1_SLV_Pos)      /*!< 0x00800000 */
+#define ADC_CSR_AWD1_SLV                  ADC_CSR_AWD1_SLV_Msk                 /*!< Analog watchdog 1 flag of the slave ADC */
+#define ADC_CSR_AWD2_SLV_Pos              (24U)
+#define ADC_CSR_AWD2_SLV_Msk              (0x1UL << ADC_CSR_AWD2_SLV_Pos)      /*!< 0x01000000 */
+#define ADC_CSR_AWD2_SLV                  ADC_CSR_AWD2_SLV_Msk                 /*!< Analog watchdog 2 flag of the slave ADC */
+#define ADC_CSR_AWD3_SLV_Pos              (25U)
+#define ADC_CSR_AWD3_SLV_Msk              (0x1UL << ADC_CSR_AWD3_SLV_Pos)      /*!< 0x02000000 */
+#define ADC_CSR_AWD3_SLV                  ADC_CSR_AWD3_SLV_Msk                 /*!< Analog watchdog 3 flag of the slave ADC */
+#define ADC_CSR_JQOVF_SLV_Pos             (26U)
+#define ADC_CSR_JQOVF_SLV_Msk             (0x1UL << ADC_CSR_JQOVF_SLV_Pos)     /*!< 0x04000000 */
+#define ADC_CSR_JQOVF_SLV                 ADC_CSR_JQOVF_SLV_Msk                /*!< Injected context queue overflow flag of the slave ADC */
+
+/********************  Bit definition for ADC_CCR register  ********************/
+#define ADC_CCR_DUAL_Pos                  (0U)
+#define ADC_CCR_DUAL_Msk                  (0x1FUL << ADC_CCR_DUAL_Pos)          /*!< 0x0000001F */
+#define ADC_CCR_DUAL                      ADC_CCR_DUAL_Msk                      /*!< Dual ADC mode selection */
+#define ADC_CCR_DUAL_0                    (0x01UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000001 */
+#define ADC_CCR_DUAL_1                    (0x02UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000002 */
+#define ADC_CCR_DUAL_2                    (0x04UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000004 */
+#define ADC_CCR_DUAL_3                    (0x08UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000008 */
+#define ADC_CCR_DUAL_4                    (0x10UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000010 */
+
+#define ADC_CCR_DELAY_Pos                 (8U)
+#define ADC_CCR_DELAY_Msk                 (0xFUL << ADC_CCR_DELAY_Pos)          /*!< 0x00000F00 */
+#define ADC_CCR_DELAY                     ADC_CCR_DELAY_Msk                     /*!< Delay between 2 sampling phases */
+#define ADC_CCR_DELAY_0                   (0x1UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000100 */
+#define ADC_CCR_DELAY_1                   (0x2UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000200 */
+#define ADC_CCR_DELAY_2                   (0x4UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000400 */
+#define ADC_CCR_DELAY_3                   (0x8UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000800 */
+
+
+#define ADC_CCR_DAMDF_Pos                 (14U)
+#define ADC_CCR_DAMDF_Msk                 (0x3UL << ADC_CCR_DAMDF_Pos)          /*!< 0x0000C000 */
+#define ADC_CCR_DAMDF                     ADC_CCR_DAMDF_Msk                     /*!< Dual ADC mode Data format */
+#define ADC_CCR_DAMDF_0                   (0x1UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00004000 */
+#define ADC_CCR_DAMDF_1                   (0x2UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00008000 */
+
+#define ADC_CCR_CKMODE_Pos                (16U)
+#define ADC_CCR_CKMODE_Msk                (0x3UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00030000 */
+#define ADC_CCR_CKMODE                    ADC_CCR_CKMODE_Msk                    /*!< ADC clock mode */
+#define ADC_CCR_CKMODE_0                  (0x1UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00010000 */
+#define ADC_CCR_CKMODE_1                  (0x2UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00020000 */
+
+#define ADC_CCR_PRESC_Pos                 (18U)
+#define ADC_CCR_PRESC_Msk                 (0xFUL << ADC_CCR_PRESC_Pos)          /*!< 0x003C0000 */
+#define ADC_CCR_PRESC                     ADC_CCR_PRESC_Msk                     /*!< ADC prescaler */
+#define ADC_CCR_PRESC_0                   (0x1UL << ADC_CCR_PRESC_Pos)          /*!< 0x00040000 */
+#define ADC_CCR_PRESC_1                   (0x2UL << ADC_CCR_PRESC_Pos)          /*!< 0x00080000 */
+#define ADC_CCR_PRESC_2                   (0x4UL << ADC_CCR_PRESC_Pos)          /*!< 0x00100000 */
+#define ADC_CCR_PRESC_3                   (0x8UL << ADC_CCR_PRESC_Pos)          /*!< 0x00200000 */
+
+#define ADC_CCR_VREFEN_Pos                (22U)
+#define ADC_CCR_VREFEN_Msk                (0x1UL << ADC_CCR_VREFEN_Pos)         /*!< 0x00400000 */
+#define ADC_CCR_VREFEN                    ADC_CCR_VREFEN_Msk                    /*!< VREFINT enable */
+#define ADC_CCR_TSEN_Pos                  (23U)
+#define ADC_CCR_TSEN_Msk                  (0x1UL << ADC_CCR_TSEN_Pos)           /*!< 0x00800000 */
+#define ADC_CCR_TSEN                      ADC_CCR_TSEN_Msk                      /*!< Temperature sensor enable */
+#define ADC_CCR_VBATEN_Pos                (24U)
+#define ADC_CCR_VBATEN_Msk                (0x1UL << ADC_CCR_VBATEN_Pos)         /*!< 0x01000000 */
+#define ADC_CCR_VBATEN                    ADC_CCR_VBATEN_Msk                    /*!< VBAT enable */
+
+/********************  Bit definition for ADC_CDR register  *******************/
+#define ADC_CDR_RDATA_MST_Pos             (0U)
+#define ADC_CDR_RDATA_MST_Msk             (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)   /*!< 0x0000FFFF */
+#define ADC_CDR_RDATA_MST                 ADC_CDR_RDATA_MST_Msk                 /*!< ADC multimode master group regular conversion data */
+
+#define ADC_CDR_RDATA_SLV_Pos             (16U)
+#define ADC_CDR_RDATA_SLV_Msk             (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)   /*!< 0xFFFF0000 */
+#define ADC_CDR_RDATA_SLV                 ADC_CDR_RDATA_SLV_Msk                 /*!< ADC multimode slave group regular conversion data */
+
+/********************  Bit definition for ADC_CDR2 register  ******************/
+#define ADC_CDR2_RDATA_ALT_Pos            (0U)
+#define ADC_CDR2_RDATA_ALT_Msk            (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */
+#define ADC_CDR2_RDATA_ALT                ADC_CDR2_RDATA_ALT_Msk                   /*!< Regular data of the master/slave alternated ADCs */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                   VREFBUF                                  */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for VREFBUF_CSR register  ****************/
+#define VREFBUF_CSR_ENVR_Pos        (0U)
+#define VREFBUF_CSR_ENVR_Msk        (0x1UL << VREFBUF_CSR_ENVR_Pos)            /*!< 0x00000001 */
+#define VREFBUF_CSR_ENVR            VREFBUF_CSR_ENVR_Msk                       /*!<Voltage reference buffer enable */
+#define VREFBUF_CSR_HIZ_Pos         (1U)
+#define VREFBUF_CSR_HIZ_Msk         (0x1UL << VREFBUF_CSR_HIZ_Pos)             /*!< 0x00000002 */
+#define VREFBUF_CSR_HIZ             VREFBUF_CSR_HIZ_Msk                        /*!<High impedance mode             */
+#define VREFBUF_CSR_VRR_Pos         (3U)
+#define VREFBUF_CSR_VRR_Msk         (0x1UL << VREFBUF_CSR_VRR_Pos)             /*!< 0x00000008 */
+#define VREFBUF_CSR_VRR             VREFBUF_CSR_VRR_Msk                        /*!<Voltage reference buffer ready  */
+#define VREFBUF_CSR_VRS_Pos         (4U)
+#define VREFBUF_CSR_VRS_Msk         (0x7UL << VREFBUF_CSR_VRS_Pos)             /*!< 0x00000070 */
+#define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */
+
+#define VREFBUF_CSR_VRS_OUT1        ((uint32_t)0x00000000)                     /*!<Voltage reference VREF_OUT1     */
+#define VREFBUF_CSR_VRS_OUT2_Pos    (4U)
+#define VREFBUF_CSR_VRS_OUT2_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)        /*!< 0x00000010 */
+#define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */
+#define VREFBUF_CSR_VRS_OUT3_Pos    (5U)
+#define VREFBUF_CSR_VRS_OUT3_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT3_Pos)        /*!< 0x00000020 */
+#define VREFBUF_CSR_VRS_OUT3        VREFBUF_CSR_VRS_OUT3_Msk                   /*!<Voltage reference VREF_OUT3     */
+#define VREFBUF_CSR_VRS_OUT4_Pos    (4U)
+#define VREFBUF_CSR_VRS_OUT4_Msk    (0x3UL << VREFBUF_CSR_VRS_OUT4_Pos)        /*!< 0x00000030 */
+#define VREFBUF_CSR_VRS_OUT4        VREFBUF_CSR_VRS_OUT4_Msk                   /*!<Voltage reference VREF_OUT4     */
+
+/*******************  Bit definition for VREFBUF_CCR register  ****************/
+#define VREFBUF_CCR_TRIM_Pos        (0U)
+#define VREFBUF_CCR_TRIM_Msk        (0x3FUL << VREFBUF_CCR_TRIM_Pos)           /*!< 0x0000003F */
+#define VREFBUF_CCR_TRIM            VREFBUF_CCR_TRIM_Msk                       /*!<TRIM[5:0] bits (Trimming code)  */
+
+/******************************************************************************/
+/*                                                                            */
+/*                 Flexible Datarate Controller Area Network                  */
+/*                                                                            */
+/******************************************************************************/
+/*!<FDCAN control and status registers */
+/*****************  Bit definition for FDCAN_CREL register  *******************/
+#define FDCAN_CREL_DAY_Pos        (0U)
+#define FDCAN_CREL_DAY_Msk        (0xFFUL << FDCAN_CREL_DAY_Pos)               /*!< 0x000000FF */
+#define FDCAN_CREL_DAY            FDCAN_CREL_DAY_Msk                           /*!<Timestamp Day                           */
+#define FDCAN_CREL_MON_Pos        (8U)
+#define FDCAN_CREL_MON_Msk        (0xFFUL << FDCAN_CREL_MON_Pos)               /*!< 0x0000FF00 */
+#define FDCAN_CREL_MON            FDCAN_CREL_MON_Msk                           /*!<Timestamp Month                         */
+#define FDCAN_CREL_YEAR_Pos       (16U)
+#define FDCAN_CREL_YEAR_Msk       (0xFUL << FDCAN_CREL_YEAR_Pos)               /*!< 0x000F0000 */
+#define FDCAN_CREL_YEAR           FDCAN_CREL_YEAR_Msk                          /*!<Timestamp Year                          */
+#define FDCAN_CREL_SUBSTEP_Pos    (20U)
+#define FDCAN_CREL_SUBSTEP_Msk    (0xFUL << FDCAN_CREL_SUBSTEP_Pos)            /*!< 0x00F00000 */
+#define FDCAN_CREL_SUBSTEP        FDCAN_CREL_SUBSTEP_Msk                       /*!<Sub-step of Core release                */
+#define FDCAN_CREL_STEP_Pos       (24U)
+#define FDCAN_CREL_STEP_Msk       (0xFUL << FDCAN_CREL_STEP_Pos)               /*!< 0x0F000000 */
+#define FDCAN_CREL_STEP           FDCAN_CREL_STEP_Msk                          /*!<Step of Core release                    */
+#define FDCAN_CREL_REL_Pos        (28U)
+#define FDCAN_CREL_REL_Msk        (0xFUL << FDCAN_CREL_REL_Pos)                /*!< 0xF0000000 */
+#define FDCAN_CREL_REL            FDCAN_CREL_REL_Msk                           /*!<Core release                            */
+
+/*****************  Bit definition for FDCAN_ENDN register  *******************/
+#define FDCAN_ENDN_ETV_Pos        (0U)
+#define FDCAN_ENDN_ETV_Msk        (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)         /*!< 0xFFFFFFFF */
+#define FDCAN_ENDN_ETV            FDCAN_ENDN_ETV_Msk                           /*!<Endiannes Test Value                    */
+
+/*****************  Bit definition for FDCAN_DBTP register  *******************/
+#define FDCAN_DBTP_DSJW_Pos       (0U)
+#define FDCAN_DBTP_DSJW_Msk       (0xFUL << FDCAN_DBTP_DSJW_Pos)               /*!< 0x0000000F */
+#define FDCAN_DBTP_DSJW           FDCAN_DBTP_DSJW_Msk                          /*!<Synchronization Jump Width              */
+#define FDCAN_DBTP_DTSEG2_Pos     (4U)
+#define FDCAN_DBTP_DTSEG2_Msk     (0xFUL << FDCAN_DBTP_DTSEG2_Pos)             /*!< 0x000000F0 */
+#define FDCAN_DBTP_DTSEG2         FDCAN_DBTP_DTSEG2_Msk                        /*!<Data time segment after sample point    */
+#define FDCAN_DBTP_DTSEG1_Pos     (8U)
+#define FDCAN_DBTP_DTSEG1_Msk     (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)            /*!< 0x00001F00 */
+#define FDCAN_DBTP_DTSEG1         FDCAN_DBTP_DTSEG1_Msk                        /*!<Data time segment before sample point   */
+#define FDCAN_DBTP_DBRP_Pos       (16U)
+#define FDCAN_DBTP_DBRP_Msk       (0x1FUL << FDCAN_DBTP_DBRP_Pos)              /*!< 0x001F0000 */
+#define FDCAN_DBTP_DBRP           FDCAN_DBTP_DBRP_Msk                          /*!<Data BIt Rate Prescaler                 */
+#define FDCAN_DBTP_TDC_Pos        (23U)
+#define FDCAN_DBTP_TDC_Msk        (0x1UL << FDCAN_DBTP_TDC_Pos)                /*!< 0x00800000 */
+#define FDCAN_DBTP_TDC            FDCAN_DBTP_TDC_Msk                           /*!<Transceiver Delay Compensation          */
+
+/*****************  Bit definition for FDCAN_TEST register  *******************/
+#define FDCAN_TEST_LBCK_Pos       (4U)
+#define FDCAN_TEST_LBCK_Msk       (0x1UL << FDCAN_TEST_LBCK_Pos)               /*!< 0x00000010 */
+#define FDCAN_TEST_LBCK           FDCAN_TEST_LBCK_Msk                          /*!<Loop Back mode                           */
+#define FDCAN_TEST_TX_Pos         (5U)
+#define FDCAN_TEST_TX_Msk         (0x3UL << FDCAN_TEST_TX_Pos)                 /*!< 0x00000060 */
+#define FDCAN_TEST_TX             FDCAN_TEST_TX_Msk                            /*!<Control of Transmit Pin                  */
+#define FDCAN_TEST_RX_Pos         (7U)
+#define FDCAN_TEST_RX_Msk         (0x1UL << FDCAN_TEST_RX_Pos)                 /*!< 0x00000080 */
+#define FDCAN_TEST_RX             FDCAN_TEST_RX_Msk                            /*!<Receive Pin                              */
+
+/*****************  Bit definition for FDCAN_RWD register  ********************/
+#define FDCAN_RWD_WDC_Pos         (0U)
+#define FDCAN_RWD_WDC_Msk         (0xFFUL << FDCAN_RWD_WDC_Pos)                /*!< 0x000000FF */
+#define FDCAN_RWD_WDC             FDCAN_RWD_WDC_Msk                            /*!<Watchdog configuration                   */
+#define FDCAN_RWD_WDV_Pos         (8U)
+#define FDCAN_RWD_WDV_Msk         (0xFFUL << FDCAN_RWD_WDV_Pos)                /*!< 0x0000FF00 */
+#define FDCAN_RWD_WDV             FDCAN_RWD_WDV_Msk                            /*!<Watchdog value                           */
+
+/*****************  Bit definition for FDCAN_CCCR register  ********************/
+#define FDCAN_CCCR_INIT_Pos       (0U)
+#define FDCAN_CCCR_INIT_Msk       (0x1UL << FDCAN_CCCR_INIT_Pos)               /*!< 0x00000001 */
+#define FDCAN_CCCR_INIT           FDCAN_CCCR_INIT_Msk                          /*!<Initialization                           */
+#define FDCAN_CCCR_CCE_Pos        (1U)
+#define FDCAN_CCCR_CCE_Msk        (0x1UL << FDCAN_CCCR_CCE_Pos)                /*!< 0x00000002 */
+#define FDCAN_CCCR_CCE            FDCAN_CCCR_CCE_Msk                           /*!<Configuration Change Enable              */
+#define FDCAN_CCCR_ASM_Pos        (2U)
+#define FDCAN_CCCR_ASM_Msk        (0x1UL << FDCAN_CCCR_ASM_Pos)                /*!< 0x00000004 */
+#define FDCAN_CCCR_ASM            FDCAN_CCCR_ASM_Msk                           /*!<ASM Restricted Operation Mode            */
+#define FDCAN_CCCR_CSA_Pos        (3U)
+#define FDCAN_CCCR_CSA_Msk        (0x1UL << FDCAN_CCCR_CSA_Pos)                /*!< 0x00000008 */
+#define FDCAN_CCCR_CSA            FDCAN_CCCR_CSA_Msk                           /*!<Clock Stop Acknowledge                   */
+#define FDCAN_CCCR_CSR_Pos        (4U)
+#define FDCAN_CCCR_CSR_Msk        (0x1UL << FDCAN_CCCR_CSR_Pos)                /*!< 0x00000010 */
+#define FDCAN_CCCR_CSR            FDCAN_CCCR_CSR_Msk                           /*!<Clock Stop Request                       */
+#define FDCAN_CCCR_MON_Pos        (5U)
+#define FDCAN_CCCR_MON_Msk        (0x1UL << FDCAN_CCCR_MON_Pos)                /*!< 0x00000020 */
+#define FDCAN_CCCR_MON            FDCAN_CCCR_MON_Msk                           /*!<Bus Monitoring Mode                      */
+#define FDCAN_CCCR_DAR_Pos        (6U)
+#define FDCAN_CCCR_DAR_Msk        (0x1UL << FDCAN_CCCR_DAR_Pos)                /*!< 0x00000040 */
+#define FDCAN_CCCR_DAR            FDCAN_CCCR_DAR_Msk                           /*!<Disable Automatic Retransmission         */
+#define FDCAN_CCCR_TEST_Pos       (7U)
+#define FDCAN_CCCR_TEST_Msk       (0x1UL << FDCAN_CCCR_TEST_Pos)               /*!< 0x00000080 */
+#define FDCAN_CCCR_TEST           FDCAN_CCCR_TEST_Msk                          /*!<Test Mode Enable                         */
+#define FDCAN_CCCR_FDOE_Pos       (8U)
+#define FDCAN_CCCR_FDOE_Msk       (0x1UL << FDCAN_CCCR_FDOE_Pos)               /*!< 0x00000100 */
+#define FDCAN_CCCR_FDOE           FDCAN_CCCR_FDOE_Msk                          /*!<FD Operation Enable                      */
+#define FDCAN_CCCR_BRSE_Pos       (9U)
+#define FDCAN_CCCR_BRSE_Msk       (0x1UL << FDCAN_CCCR_BRSE_Pos)               /*!< 0x00000200 */
+#define FDCAN_CCCR_BRSE           FDCAN_CCCR_BRSE_Msk                          /*!<FDCAN Bit Rate Switching                 */
+#define FDCAN_CCCR_PXHD_Pos       (12U)
+#define FDCAN_CCCR_PXHD_Msk       (0x1UL << FDCAN_CCCR_PXHD_Pos)               /*!< 0x00001000 */
+#define FDCAN_CCCR_PXHD           FDCAN_CCCR_PXHD_Msk                          /*!<Protocol Exception Handling Disable      */
+#define FDCAN_CCCR_EFBI_Pos       (13U)
+#define FDCAN_CCCR_EFBI_Msk       (0x1UL << FDCAN_CCCR_EFBI_Pos)               /*!< 0x00002000 */
+#define FDCAN_CCCR_EFBI           FDCAN_CCCR_EFBI_Msk                          /*!<Edge Filtering during Bus Integration    */
+#define FDCAN_CCCR_TXP_Pos        (14U)
+#define FDCAN_CCCR_TXP_Msk        (0x1UL << FDCAN_CCCR_TXP_Pos)                /*!< 0x00004000 */
+#define FDCAN_CCCR_TXP            FDCAN_CCCR_TXP_Msk                           /*!<Two CAN bit times Pause                  */
+#define FDCAN_CCCR_NISO_Pos       (15U)
+#define FDCAN_CCCR_NISO_Msk       (0x1UL << FDCAN_CCCR_NISO_Pos)               /*!< 0x00008000 */
+#define FDCAN_CCCR_NISO           FDCAN_CCCR_NISO_Msk                          /*!<Non ISO Operation                        */
+
+/*****************  Bit definition for FDCAN_NBTP register  ********************/
+#define FDCAN_NBTP_NTSEG2_Pos     (0U)
+#define FDCAN_NBTP_NTSEG2_Msk     (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)            /*!< 0x0000007F */
+#define FDCAN_NBTP_NTSEG2         FDCAN_NBTP_NTSEG2_Msk                        /*!<Nominal Time segment after sample point  */
+#define FDCAN_NBTP_NTSEG1_Pos     (8U)
+#define FDCAN_NBTP_NTSEG1_Msk     (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)            /*!< 0x0000FF00 */
+#define FDCAN_NBTP_NTSEG1         FDCAN_NBTP_NTSEG1_Msk                        /*!<Nominal Time segment before sample point */
+#define FDCAN_NBTP_NBRP_Pos       (16U)
+#define FDCAN_NBTP_NBRP_Msk       (0x1FFUL << FDCAN_NBTP_NBRP_Pos)             /*!< 0x01FF0000 */
+#define FDCAN_NBTP_NBRP           FDCAN_NBTP_NBRP_Msk                          /*!<Bit Rate Prescaler                       */
+#define FDCAN_NBTP_NSJW_Pos       (25U)
+#define FDCAN_NBTP_NSJW_Msk       (0x7FUL << FDCAN_NBTP_NSJW_Pos)              /*!< 0xFE000000 */
+#define FDCAN_NBTP_NSJW           FDCAN_NBTP_NSJW_Msk                          /*!<Nominal (Re)Synchronization Jump Width   */
+
+/*****************  Bit definition for FDCAN_TSCC register  ********************/
+#define FDCAN_TSCC_TSS_Pos        (0U)
+#define FDCAN_TSCC_TSS_Msk        (0x3UL << FDCAN_TSCC_TSS_Pos)                /*!< 0x00000003 */
+#define FDCAN_TSCC_TSS            FDCAN_TSCC_TSS_Msk                           /*!<Timestamp Select                         */
+#define FDCAN_TSCC_TCP_Pos        (16U)
+#define FDCAN_TSCC_TCP_Msk        (0xFUL << FDCAN_TSCC_TCP_Pos)                /*!< 0x000F0000 */
+#define FDCAN_TSCC_TCP            FDCAN_TSCC_TCP_Msk                           /*!<Timestamp Counter Prescaler              */
+
+/*****************  Bit definition for FDCAN_TSCV register  ********************/
+#define FDCAN_TSCV_TSC_Pos        (0U)
+#define FDCAN_TSCV_TSC_Msk        (0xFFFFUL << FDCAN_TSCV_TSC_Pos)             /*!< 0x0000FFFF */
+#define FDCAN_TSCV_TSC            FDCAN_TSCV_TSC_Msk                           /*!<Timestamp Counter                        */
+
+/*****************  Bit definition for FDCAN_TOCC register  ********************/
+#define FDCAN_TOCC_ETOC_Pos       (0U)
+#define FDCAN_TOCC_ETOC_Msk       (0x1UL << FDCAN_TOCC_ETOC_Pos)               /*!< 0x00000001 */
+#define FDCAN_TOCC_ETOC           FDCAN_TOCC_ETOC_Msk                          /*!<Enable Timeout Counter                   */
+#define FDCAN_TOCC_TOS_Pos        (1U)
+#define FDCAN_TOCC_TOS_Msk        (0x3UL << FDCAN_TOCC_TOS_Pos)                /*!< 0x00000006 */
+#define FDCAN_TOCC_TOS            FDCAN_TOCC_TOS_Msk                           /*!<Timeout Select                           */
+#define FDCAN_TOCC_TOP_Pos        (16U)
+#define FDCAN_TOCC_TOP_Msk        (0xFFFFUL << FDCAN_TOCC_TOP_Pos)             /*!< 0xFFFF0000 */
+#define FDCAN_TOCC_TOP            FDCAN_TOCC_TOP_Msk                           /*!<Timeout Period                           */
+
+/*****************  Bit definition for FDCAN_TOCV register  ********************/
+#define FDCAN_TOCV_TOC_Pos        (0U)
+#define FDCAN_TOCV_TOC_Msk        (0xFFFFUL << FDCAN_TOCV_TOC_Pos)             /*!< 0x0000FFFF */
+#define FDCAN_TOCV_TOC            FDCAN_TOCV_TOC_Msk                           /*!<Timeout Counter                          */
+
+/*****************  Bit definition for FDCAN_ECR register  *********************/
+#define FDCAN_ECR_TEC_Pos         (0U)
+#define FDCAN_ECR_TEC_Msk         (0xFUL << FDCAN_ECR_TEC_Pos)                 /*!< 0x0000000F */
+#define FDCAN_ECR_TEC             FDCAN_ECR_TEC_Msk                            /*!<Transmit Error Counter                   */
+#define FDCAN_ECR_REC_Pos         (8U)
+#define FDCAN_ECR_REC_Msk         (0x7FUL << FDCAN_ECR_REC_Pos)                /*!< 0x00007F00 */
+#define FDCAN_ECR_REC             FDCAN_ECR_REC_Msk                            /*!<Receive Error Counter                    */
+#define FDCAN_ECR_RP_Pos          (15U)
+#define FDCAN_ECR_RP_Msk          (0x1UL << FDCAN_ECR_RP_Pos)                  /*!< 0x00008000 */
+#define FDCAN_ECR_RP              FDCAN_ECR_RP_Msk                             /*!<Receive Error Passive                    */
+#define FDCAN_ECR_CEL_Pos         (16U)
+#define FDCAN_ECR_CEL_Msk         (0xFFUL << FDCAN_ECR_CEL_Pos)                /*!< 0x00FF0000 */
+#define FDCAN_ECR_CEL             FDCAN_ECR_CEL_Msk                            /*!<CAN Error Logging                        */
+
+/*****************  Bit definition for FDCAN_PSR register  *********************/
+#define FDCAN_PSR_LEC_Pos         (0U)
+#define FDCAN_PSR_LEC_Msk         (0x7UL << FDCAN_PSR_LEC_Pos)                 /*!< 0x00000007 */
+#define FDCAN_PSR_LEC             FDCAN_PSR_LEC_Msk                            /*!<Last Error Code                          */
+#define FDCAN_PSR_ACT_Pos         (3U)
+#define FDCAN_PSR_ACT_Msk         (0x3UL << FDCAN_PSR_ACT_Pos)                 /*!< 0x00000018 */
+#define FDCAN_PSR_ACT             FDCAN_PSR_ACT_Msk                            /*!<Activity                                 */
+#define FDCAN_PSR_EP_Pos          (5U)
+#define FDCAN_PSR_EP_Msk          (0x1UL << FDCAN_PSR_EP_Pos)                  /*!< 0x00000020 */
+#define FDCAN_PSR_EP              FDCAN_PSR_EP_Msk                             /*!<Error Passive                            */
+#define FDCAN_PSR_EW_Pos          (6U)
+#define FDCAN_PSR_EW_Msk          (0x1UL << FDCAN_PSR_EW_Pos)                  /*!< 0x00000040 */
+#define FDCAN_PSR_EW              FDCAN_PSR_EW_Msk                             /*!<Warning Status                           */
+#define FDCAN_PSR_BO_Pos          (7U)
+#define FDCAN_PSR_BO_Msk          (0x1UL << FDCAN_PSR_BO_Pos)                  /*!< 0x00000080 */
+#define FDCAN_PSR_BO              FDCAN_PSR_BO_Msk                             /*!<Bus_Off Status                           */
+#define FDCAN_PSR_DLEC_Pos        (8U)
+#define FDCAN_PSR_DLEC_Msk        (0x7UL << FDCAN_PSR_DLEC_Pos)                /*!< 0x00000700 */
+#define FDCAN_PSR_DLEC            FDCAN_PSR_DLEC_Msk                           /*!<Data Last Error Code                     */
+#define FDCAN_PSR_RESI_Pos        (11U)
+#define FDCAN_PSR_RESI_Msk        (0x1UL << FDCAN_PSR_RESI_Pos)                /*!< 0x00000800 */
+#define FDCAN_PSR_RESI            FDCAN_PSR_RESI_Msk                           /*!<ESI flag of last received FDCAN Message  */
+#define FDCAN_PSR_RBRS_Pos        (12U)
+#define FDCAN_PSR_RBRS_Msk        (0x1UL << FDCAN_PSR_RBRS_Pos)                /*!< 0x00001000 */
+#define FDCAN_PSR_RBRS            FDCAN_PSR_RBRS_Msk                           /*!<BRS flag of last received FDCAN Message  */
+#define FDCAN_PSR_REDL_Pos        (13U)
+#define FDCAN_PSR_REDL_Msk        (0x1UL << FDCAN_PSR_REDL_Pos)                /*!< 0x00002000 */
+#define FDCAN_PSR_REDL            FDCAN_PSR_REDL_Msk                           /*!<Received FDCAN Message                   */
+#define FDCAN_PSR_PXE_Pos         (14U)
+#define FDCAN_PSR_PXE_Msk         (0x1UL << FDCAN_PSR_PXE_Pos)                 /*!< 0x00004000 */
+#define FDCAN_PSR_PXE             FDCAN_PSR_PXE_Msk                            /*!<Protocol Exception Event                 */
+#define FDCAN_PSR_TDCV_Pos        (16U)
+#define FDCAN_PSR_TDCV_Msk        (0x7FUL << FDCAN_PSR_TDCV_Pos)               /*!< 0x007F0000 */
+#define FDCAN_PSR_TDCV            FDCAN_PSR_TDCV_Msk                           /*!<Transmitter Delay Compensation Value     */
+
+/*****************  Bit definition for FDCAN_TDCR register  ********************/
+#define FDCAN_TDCR_TDCF_Pos       (0U)
+#define FDCAN_TDCR_TDCF_Msk       (0x7FUL << FDCAN_TDCR_TDCF_Pos)              /*!< 0x0000007F */
+#define FDCAN_TDCR_TDCF           FDCAN_TDCR_TDCF_Msk                          /*!<Transmitter Delay Compensation Filter    */
+#define FDCAN_TDCR_TDCO_Pos       (8U)
+#define FDCAN_TDCR_TDCO_Msk       (0x7FUL << FDCAN_TDCR_TDCO_Pos)              /*!< 0x00007F00 */
+#define FDCAN_TDCR_TDCO           FDCAN_TDCR_TDCO_Msk                          /*!<Transmitter Delay Compensation Offset    */
+
+/*****************  Bit definition for FDCAN_IR register  **********************/
+#define FDCAN_IR_RF0N_Pos         (0U)
+#define FDCAN_IR_RF0N_Msk         (0x1UL << FDCAN_IR_RF0N_Pos)                 /*!< 0x00000001 */
+#define FDCAN_IR_RF0N             FDCAN_IR_RF0N_Msk                            /*!<Rx FIFO 0 New Message                    */
+#define FDCAN_IR_RF0W_Pos         (1U)
+#define FDCAN_IR_RF0W_Msk         (0x1UL << FDCAN_IR_RF0W_Pos)                 /*!< 0x00000002 */
+#define FDCAN_IR_RF0W             FDCAN_IR_RF0W_Msk                            /*!<Rx FIFO 0 Watermark Reached              */
+#define FDCAN_IR_RF0F_Pos         (2U)
+#define FDCAN_IR_RF0F_Msk         (0x1UL << FDCAN_IR_RF0F_Pos)                 /*!< 0x00000004 */
+#define FDCAN_IR_RF0F             FDCAN_IR_RF0F_Msk                            /*!<Rx FIFO 0 Full                           */
+#define FDCAN_IR_RF0L_Pos         (3U)
+#define FDCAN_IR_RF0L_Msk         (0x1UL << FDCAN_IR_RF0L_Pos)                 /*!< 0x00000008 */
+#define FDCAN_IR_RF0L             FDCAN_IR_RF0L_Msk                            /*!<Rx FIFO 0 Message Lost                   */
+#define FDCAN_IR_RF1N_Pos         (4U)
+#define FDCAN_IR_RF1N_Msk         (0x1UL << FDCAN_IR_RF1N_Pos)                 /*!< 0x00000010 */
+#define FDCAN_IR_RF1N             FDCAN_IR_RF1N_Msk                            /*!<Rx FIFO 1 New Message                    */
+#define FDCAN_IR_RF1W_Pos         (5U)
+#define FDCAN_IR_RF1W_Msk         (0x1UL << FDCAN_IR_RF1W_Pos)                 /*!< 0x00000020 */
+#define FDCAN_IR_RF1W             FDCAN_IR_RF1W_Msk                            /*!<Rx FIFO 1 Watermark Reached              */
+#define FDCAN_IR_RF1F_Pos         (6U)
+#define FDCAN_IR_RF1F_Msk         (0x1UL << FDCAN_IR_RF1F_Pos)                 /*!< 0x00000040 */
+#define FDCAN_IR_RF1F             FDCAN_IR_RF1F_Msk                            /*!<Rx FIFO 1 Full                           */
+#define FDCAN_IR_RF1L_Pos         (7U)
+#define FDCAN_IR_RF1L_Msk         (0x1UL << FDCAN_IR_RF1L_Pos)                 /*!< 0x00000080 */
+#define FDCAN_IR_RF1L             FDCAN_IR_RF1L_Msk                            /*!<Rx FIFO 1 Message Lost                   */
+#define FDCAN_IR_HPM_Pos          (8U)
+#define FDCAN_IR_HPM_Msk          (0x1UL << FDCAN_IR_HPM_Pos)                  /*!< 0x00000100 */
+#define FDCAN_IR_HPM              FDCAN_IR_HPM_Msk                             /*!<High Priority Message                    */
+#define FDCAN_IR_TC_Pos           (9U)
+#define FDCAN_IR_TC_Msk           (0x1UL << FDCAN_IR_TC_Pos)                   /*!< 0x00000200 */
+#define FDCAN_IR_TC               FDCAN_IR_TC_Msk                              /*!<Transmission Completed                   */
+#define FDCAN_IR_TCF_Pos          (10U)
+#define FDCAN_IR_TCF_Msk          (0x1UL << FDCAN_IR_TCF_Pos)                  /*!< 0x00000400 */
+#define FDCAN_IR_TCF              FDCAN_IR_TCF_Msk                             /*!<Transmission Cancellation Finished       */
+#define FDCAN_IR_TFE_Pos          (11U)
+#define FDCAN_IR_TFE_Msk          (0x1UL << FDCAN_IR_TFE_Pos)                  /*!< 0x00000800 */
+#define FDCAN_IR_TFE              FDCAN_IR_TFE_Msk                             /*!<Tx FIFO Empty                            */
+#define FDCAN_IR_TEFN_Pos         (12U)
+#define FDCAN_IR_TEFN_Msk         (0x1UL << FDCAN_IR_TEFN_Pos)                 /*!< 0x00001000 */
+#define FDCAN_IR_TEFN             FDCAN_IR_TEFN_Msk                            /*!<Tx Event FIFO New Entry                  */
+#define FDCAN_IR_TEFW_Pos         (13U)
+#define FDCAN_IR_TEFW_Msk         (0x1UL << FDCAN_IR_TEFW_Pos)                 /*!< 0x00002000 */
+#define FDCAN_IR_TEFW             FDCAN_IR_TEFW_Msk                            /*!<Tx Event FIFO Watermark Reached          */
+#define FDCAN_IR_TEFF_Pos         (14U)
+#define FDCAN_IR_TEFF_Msk         (0x1UL << FDCAN_IR_TEFF_Pos)                 /*!< 0x00004000 */
+#define FDCAN_IR_TEFF             FDCAN_IR_TEFF_Msk                            /*!<Tx Event FIFO Full                       */
+#define FDCAN_IR_TEFL_Pos         (15U)
+#define FDCAN_IR_TEFL_Msk         (0x1UL << FDCAN_IR_TEFL_Pos)                 /*!< 0x00008000 */
+#define FDCAN_IR_TEFL             FDCAN_IR_TEFL_Msk                            /*!<Tx Event FIFO Element Lost               */
+#define FDCAN_IR_TSW_Pos          (16U)
+#define FDCAN_IR_TSW_Msk          (0x1UL << FDCAN_IR_TSW_Pos)                  /*!< 0x00010000 */
+#define FDCAN_IR_TSW              FDCAN_IR_TSW_Msk                             /*!<Timestamp Wraparound                     */
+#define FDCAN_IR_MRAF_Pos         (17U)
+#define FDCAN_IR_MRAF_Msk         (0x1UL << FDCAN_IR_MRAF_Pos)                 /*!< 0x00020000 */
+#define FDCAN_IR_MRAF             FDCAN_IR_MRAF_Msk                            /*!<Message RAM Access Failure               */
+#define FDCAN_IR_TOO_Pos          (18U)
+#define FDCAN_IR_TOO_Msk          (0x1UL << FDCAN_IR_TOO_Pos)                  /*!< 0x00040000 */
+#define FDCAN_IR_TOO              FDCAN_IR_TOO_Msk                             /*!<Timeout Occurred                         */
+#define FDCAN_IR_DRX_Pos          (19U)
+#define FDCAN_IR_DRX_Msk          (0x1UL << FDCAN_IR_DRX_Pos)                  /*!< 0x00080000 */
+#define FDCAN_IR_DRX              FDCAN_IR_DRX_Msk                             /*!<Message stored to Dedicated Rx Buffer    */
+#define FDCAN_IR_ELO_Pos          (22U)
+#define FDCAN_IR_ELO_Msk          (0x1UL << FDCAN_IR_ELO_Pos)                  /*!< 0x00400000 */
+#define FDCAN_IR_ELO              FDCAN_IR_ELO_Msk                             /*!<Error Logging Overflow                   */
+#define FDCAN_IR_EP_Pos           (23U)
+#define FDCAN_IR_EP_Msk           (0x1UL << FDCAN_IR_EP_Pos)                   /*!< 0x00800000 */
+#define FDCAN_IR_EP               FDCAN_IR_EP_Msk                              /*!<Error Passive                            */
+#define FDCAN_IR_EW_Pos           (24U)
+#define FDCAN_IR_EW_Msk           (0x1UL << FDCAN_IR_EW_Pos)                   /*!< 0x01000000 */
+#define FDCAN_IR_EW               FDCAN_IR_EW_Msk                              /*!<Warning Status                           */
+#define FDCAN_IR_BO_Pos           (25U)
+#define FDCAN_IR_BO_Msk           (0x1UL << FDCAN_IR_BO_Pos)                   /*!< 0x02000000 */
+#define FDCAN_IR_BO               FDCAN_IR_BO_Msk                              /*!<Bus_Off Status                           */
+#define FDCAN_IR_WDI_Pos          (26U)
+#define FDCAN_IR_WDI_Msk          (0x1UL << FDCAN_IR_WDI_Pos)                  /*!< 0x04000000 */
+#define FDCAN_IR_WDI              FDCAN_IR_WDI_Msk                             /*!<Watchdog Interrupt                       */
+#define FDCAN_IR_PEA_Pos          (27U)
+#define FDCAN_IR_PEA_Msk          (0x1UL << FDCAN_IR_PEA_Pos)                  /*!< 0x08000000 */
+#define FDCAN_IR_PEA              FDCAN_IR_PEA_Msk                             /*!<Protocol Error in Arbitration Phase      */
+#define FDCAN_IR_PED_Pos          (28U)
+#define FDCAN_IR_PED_Msk          (0x1UL << FDCAN_IR_PED_Pos)                  /*!< 0x10000000 */
+#define FDCAN_IR_PED              FDCAN_IR_PED_Msk                             /*!<Protocol Error in Data Phase             */
+#define FDCAN_IR_ARA_Pos          (29U)
+#define FDCAN_IR_ARA_Msk          (0x1UL << FDCAN_IR_ARA_Pos)                  /*!< 0x20000000 */
+#define FDCAN_IR_ARA              FDCAN_IR_ARA_Msk                             /*!<Access to Reserved Address               */
+
+/*****************  Bit definition for FDCAN_IE register  **********************/
+#define FDCAN_IE_RF0NE_Pos        (0U)
+#define FDCAN_IE_RF0NE_Msk        (0x1UL << FDCAN_IE_RF0NE_Pos)                /*!< 0x00000001 */
+#define FDCAN_IE_RF0NE            FDCAN_IE_RF0NE_Msk                           /*!<Rx FIFO 0 New Message Enable                 */
+#define FDCAN_IE_RF0WE_Pos        (1U)
+#define FDCAN_IE_RF0WE_Msk        (0x1UL << FDCAN_IE_RF0WE_Pos)                /*!< 0x00000002 */
+#define FDCAN_IE_RF0WE            FDCAN_IE_RF0WE_Msk                           /*!<Rx FIFO 0 Watermark Reached Enable           */
+#define FDCAN_IE_RF0FE_Pos        (2U)
+#define FDCAN_IE_RF0FE_Msk        (0x1UL << FDCAN_IE_RF0FE_Pos)                /*!< 0x00000004 */
+#define FDCAN_IE_RF0FE            FDCAN_IE_RF0FE_Msk                           /*!<Rx FIFO 0 Full Enable                        */
+#define FDCAN_IE_RF0LE_Pos        (3U)
+#define FDCAN_IE_RF0LE_Msk        (0x1UL << FDCAN_IE_RF0LE_Pos)                /*!< 0x00000008 */
+#define FDCAN_IE_RF0LE            FDCAN_IE_RF0LE_Msk                           /*!<Rx FIFO 0 Message Lost Enable                */
+#define FDCAN_IE_RF1NE_Pos        (4U)
+#define FDCAN_IE_RF1NE_Msk        (0x1UL << FDCAN_IE_RF1NE_Pos)                /*!< 0x00000010 */
+#define FDCAN_IE_RF1NE            FDCAN_IE_RF1NE_Msk                           /*!<Rx FIFO 1 New Message Enable                 */
+#define FDCAN_IE_RF1WE_Pos        (5U)
+#define FDCAN_IE_RF1WE_Msk        (0x1UL << FDCAN_IE_RF1WE_Pos)                /*!< 0x00000020 */
+#define FDCAN_IE_RF1WE            FDCAN_IE_RF1WE_Msk                           /*!<Rx FIFO 1 Watermark Reached Enable           */
+#define FDCAN_IE_RF1FE_Pos        (6U)
+#define FDCAN_IE_RF1FE_Msk        (0x1UL << FDCAN_IE_RF1FE_Pos)                /*!< 0x00000040 */
+#define FDCAN_IE_RF1FE            FDCAN_IE_RF1FE_Msk                           /*!<Rx FIFO 1 Full Enable                        */
+#define FDCAN_IE_RF1LE_Pos        (7U)
+#define FDCAN_IE_RF1LE_Msk        (0x1UL << FDCAN_IE_RF1LE_Pos)                /*!< 0x00000080 */
+#define FDCAN_IE_RF1LE            FDCAN_IE_RF1LE_Msk                           /*!<Rx FIFO 1 Message Lost Enable                */
+#define FDCAN_IE_HPME_Pos         (8U)
+#define FDCAN_IE_HPME_Msk         (0x1UL << FDCAN_IE_HPME_Pos)                 /*!< 0x00000100 */
+#define FDCAN_IE_HPME             FDCAN_IE_HPME_Msk                            /*!<High Priority Message Enable                 */
+#define FDCAN_IE_TCE_Pos          (9U)
+#define FDCAN_IE_TCE_Msk          (0x1UL << FDCAN_IE_TCE_Pos)                  /*!< 0x00000200 */
+#define FDCAN_IE_TCE              FDCAN_IE_TCE_Msk                             /*!<Transmission Completed Enable                */
+#define FDCAN_IE_TCFE_Pos         (10U)
+#define FDCAN_IE_TCFE_Msk         (0x1UL << FDCAN_IE_TCFE_Pos)                 /*!< 0x00000400 */
+#define FDCAN_IE_TCFE             FDCAN_IE_TCFE_Msk                            /*!<Transmission Cancellation Finished Enable    */
+#define FDCAN_IE_TFEE_Pos         (11U)
+#define FDCAN_IE_TFEE_Msk         (0x1UL << FDCAN_IE_TFEE_Pos)                 /*!< 0x00000800 */
+#define FDCAN_IE_TFEE             FDCAN_IE_TFEE_Msk                            /*!<Tx FIFO Empty Enable                         */
+#define FDCAN_IE_TEFNE_Pos        (12U)
+#define FDCAN_IE_TEFNE_Msk        (0x1UL << FDCAN_IE_TEFNE_Pos)                /*!< 0x00001000 */
+#define FDCAN_IE_TEFNE            FDCAN_IE_TEFNE_Msk                           /*!<Tx Event FIFO New Entry Enable               */
+#define FDCAN_IE_TEFWE_Pos        (13U)
+#define FDCAN_IE_TEFWE_Msk        (0x1UL << FDCAN_IE_TEFWE_Pos)                /*!< 0x00002000 */
+#define FDCAN_IE_TEFWE            FDCAN_IE_TEFWE_Msk                           /*!<Tx Event FIFO Watermark Reached Enable       */
+#define FDCAN_IE_TEFFE_Pos        (14U)
+#define FDCAN_IE_TEFFE_Msk        (0x1UL << FDCAN_IE_TEFFE_Pos)                /*!< 0x00004000 */
+#define FDCAN_IE_TEFFE            FDCAN_IE_TEFFE_Msk                           /*!<Tx Event FIFO Full Enable                    */
+#define FDCAN_IE_TEFLE_Pos        (15U)
+#define FDCAN_IE_TEFLE_Msk        (0x1UL << FDCAN_IE_TEFLE_Pos)                /*!< 0x00008000 */
+#define FDCAN_IE_TEFLE            FDCAN_IE_TEFLE_Msk                           /*!<Tx Event FIFO Element Lost Enable            */
+#define FDCAN_IE_TSWE_Pos         (16U)
+#define FDCAN_IE_TSWE_Msk         (0x1UL << FDCAN_IE_TSWE_Pos)                 /*!< 0x00010000 */
+#define FDCAN_IE_TSWE             FDCAN_IE_TSWE_Msk                            /*!<Timestamp Wraparound Enable                  */
+#define FDCAN_IE_MRAFE_Pos        (17U)
+#define FDCAN_IE_MRAFE_Msk        (0x1UL << FDCAN_IE_MRAFE_Pos)                /*!< 0x00020000 */
+#define FDCAN_IE_MRAFE            FDCAN_IE_MRAFE_Msk                           /*!<Message RAM Access Failure Enable            */
+#define FDCAN_IE_TOOE_Pos         (18U)
+#define FDCAN_IE_TOOE_Msk         (0x1UL << FDCAN_IE_TOOE_Pos)                 /*!< 0x00040000 */
+#define FDCAN_IE_TOOE             FDCAN_IE_TOOE_Msk                            /*!<Timeout Occurred Enable                      */
+#define FDCAN_IE_DRXE_Pos         (19U)
+#define FDCAN_IE_DRXE_Msk         (0x1UL << FDCAN_IE_DRXE_Pos)                 /*!< 0x00080000 */
+#define FDCAN_IE_DRXE             FDCAN_IE_DRXE_Msk                            /*!<Message stored to Dedicated Rx Buffer Enable */
+#define FDCAN_IE_BECE_Pos         (20U)
+#define FDCAN_IE_BECE_Msk         (0x1UL << FDCAN_IE_BECE_Pos)                 /*!< 0x00100000 */
+#define FDCAN_IE_BECE             FDCAN_IE_BECE_Msk                            /*!<Bit Error Corrected Interrupt Enable         */
+#define FDCAN_IE_BEUE_Pos         (21U)
+#define FDCAN_IE_BEUE_Msk         (0x1UL << FDCAN_IE_BEUE_Pos)                 /*!< 0x00200000 */
+#define FDCAN_IE_BEUE             FDCAN_IE_BEUE_Msk                            /*!<Bit Error Uncorrected Interrupt Enable       */
+#define FDCAN_IE_ELOE_Pos         (22U)
+#define FDCAN_IE_ELOE_Msk         (0x1UL << FDCAN_IE_ELOE_Pos)                 /*!< 0x00400000 */
+#define FDCAN_IE_ELOE             FDCAN_IE_ELOE_Msk                            /*!<Error Logging Overflow Enable                */
+#define FDCAN_IE_EPE_Pos          (23U)
+#define FDCAN_IE_EPE_Msk          (0x1UL << FDCAN_IE_EPE_Pos)                  /*!< 0x00800000 */
+#define FDCAN_IE_EPE              FDCAN_IE_EPE_Msk                             /*!<Error Passive Enable                         */
+#define FDCAN_IE_EWE_Pos          (24U)
+#define FDCAN_IE_EWE_Msk          (0x1UL << FDCAN_IE_EWE_Pos)                  /*!< 0x01000000 */
+#define FDCAN_IE_EWE              FDCAN_IE_EWE_Msk                             /*!<Warning Status Enable                        */
+#define FDCAN_IE_BOE_Pos          (25U)
+#define FDCAN_IE_BOE_Msk          (0x1UL << FDCAN_IE_BOE_Pos)                  /*!< 0x02000000 */
+#define FDCAN_IE_BOE              FDCAN_IE_BOE_Msk                             /*!<Bus_Off Status Enable                        */
+#define FDCAN_IE_WDIE_Pos         (26U)
+#define FDCAN_IE_WDIE_Msk         (0x1UL << FDCAN_IE_WDIE_Pos)                 /*!< 0x04000000 */
+#define FDCAN_IE_WDIE             FDCAN_IE_WDIE_Msk                            /*!<Watchdog Interrupt Enable                    */
+#define FDCAN_IE_PEAE_Pos         (27U)
+#define FDCAN_IE_PEAE_Msk         (0x1UL << FDCAN_IE_PEAE_Pos)                 /*!< 0x08000000 */
+#define FDCAN_IE_PEAE             FDCAN_IE_PEAE_Msk                            /*!<Protocol Error in Arbitration Phase Enable   */
+#define FDCAN_IE_PEDE_Pos         (28U)
+#define FDCAN_IE_PEDE_Msk         (0x1UL << FDCAN_IE_PEDE_Pos)                 /*!< 0x10000000 */
+#define FDCAN_IE_PEDE             FDCAN_IE_PEDE_Msk                            /*!<Protocol Error in Data Phase Enable          */
+#define FDCAN_IE_ARAE_Pos         (29U)
+#define FDCAN_IE_ARAE_Msk         (0x1UL << FDCAN_IE_ARAE_Pos)                 /*!< 0x20000000 */
+#define FDCAN_IE_ARAE             FDCAN_IE_ARAE_Msk                            /*!<Access to Reserved Address Enable            */
+
+/*****************  Bit definition for FDCAN_ILS register  **********************/
+#define FDCAN_ILS_RF0NL_Pos       (0U)
+#define FDCAN_ILS_RF0NL_Msk       (0x1UL << FDCAN_ILS_RF0NL_Pos)               /*!< 0x00000001 */
+#define FDCAN_ILS_RF0NL           FDCAN_ILS_RF0NL_Msk                          /*!<Rx FIFO 0 New Message Line                  */
+#define FDCAN_ILS_RF0WL_Pos       (1U)
+#define FDCAN_ILS_RF0WL_Msk       (0x1UL << FDCAN_ILS_RF0WL_Pos)               /*!< 0x00000002 */
+#define FDCAN_ILS_RF0WL           FDCAN_ILS_RF0WL_Msk                          /*!<Rx FIFO 0 Watermark Reached Line            */
+#define FDCAN_ILS_RF0FL_Pos       (2U)
+#define FDCAN_ILS_RF0FL_Msk       (0x1UL << FDCAN_ILS_RF0FL_Pos)               /*!< 0x00000004 */
+#define FDCAN_ILS_RF0FL           FDCAN_ILS_RF0FL_Msk                          /*!<Rx FIFO 0 Full Line                         */
+#define FDCAN_ILS_RF0LL_Pos       (3U)
+#define FDCAN_ILS_RF0LL_Msk       (0x1UL << FDCAN_ILS_RF0LL_Pos)               /*!< 0x00000008 */
+#define FDCAN_ILS_RF0LL           FDCAN_ILS_RF0LL_Msk                          /*!<Rx FIFO 0 Message Lost Line                 */
+#define FDCAN_ILS_RF1NL_Pos       (4U)
+#define FDCAN_ILS_RF1NL_Msk       (0x1UL << FDCAN_ILS_RF1NL_Pos)               /*!< 0x00000010 */
+#define FDCAN_ILS_RF1NL           FDCAN_ILS_RF1NL_Msk                          /*!<Rx FIFO 1 New Message Line                  */
+#define FDCAN_ILS_RF1WL_Pos       (5U)
+#define FDCAN_ILS_RF1WL_Msk       (0x1UL << FDCAN_ILS_RF1WL_Pos)               /*!< 0x00000020 */
+#define FDCAN_ILS_RF1WL           FDCAN_ILS_RF1WL_Msk                          /*!<Rx FIFO 1 Watermark Reached Line            */
+#define FDCAN_ILS_RF1FL_Pos       (6U)
+#define FDCAN_ILS_RF1FL_Msk       (0x1UL << FDCAN_ILS_RF1FL_Pos)               /*!< 0x00000040 */
+#define FDCAN_ILS_RF1FL           FDCAN_ILS_RF1FL_Msk                          /*!<Rx FIFO 1 Full Line                         */
+#define FDCAN_ILS_RF1LL_Pos       (7U)
+#define FDCAN_ILS_RF1LL_Msk       (0x1UL << FDCAN_ILS_RF1LL_Pos)               /*!< 0x00000080 */
+#define FDCAN_ILS_RF1LL           FDCAN_ILS_RF1LL_Msk                          /*!<Rx FIFO 1 Message Lost Line                 */
+#define FDCAN_ILS_HPML_Pos        (8U)
+#define FDCAN_ILS_HPML_Msk        (0x1UL << FDCAN_ILS_HPML_Pos)                /*!< 0x00000100 */
+#define FDCAN_ILS_HPML            FDCAN_ILS_HPML_Msk                           /*!<High Priority Message Line                  */
+#define FDCAN_ILS_TCL_Pos         (9U)
+#define FDCAN_ILS_TCL_Msk         (0x1UL << FDCAN_ILS_TCL_Pos)                 /*!< 0x00000200 */
+#define FDCAN_ILS_TCL             FDCAN_ILS_TCL_Msk                            /*!<Transmission Completed Line                 */
+#define FDCAN_ILS_TCFL_Pos        (10U)
+#define FDCAN_ILS_TCFL_Msk        (0x1UL << FDCAN_ILS_TCFL_Pos)                /*!< 0x00000400 */
+#define FDCAN_ILS_TCFL            FDCAN_ILS_TCFL_Msk                           /*!<Transmission Cancellation Finished Line     */
+#define FDCAN_ILS_TFEL_Pos        (11U)
+#define FDCAN_ILS_TFEL_Msk        (0x1UL << FDCAN_ILS_TFEL_Pos)                /*!< 0x00000800 */
+#define FDCAN_ILS_TFEL            FDCAN_ILS_TFEL_Msk                           /*!<Tx FIFO Empty Line                          */
+#define FDCAN_ILS_TEFNL_Pos       (12U)
+#define FDCAN_ILS_TEFNL_Msk       (0x1UL << FDCAN_ILS_TEFNL_Pos)               /*!< 0x00001000 */
+#define FDCAN_ILS_TEFNL           FDCAN_ILS_TEFNL_Msk                          /*!<Tx Event FIFO New Entry Line                */
+#define FDCAN_ILS_TEFWL_Pos       (13U)
+#define FDCAN_ILS_TEFWL_Msk       (0x1UL << FDCAN_ILS_TEFWL_Pos)               /*!< 0x00002000 */
+#define FDCAN_ILS_TEFWL           FDCAN_ILS_TEFWL_Msk                          /*!<Tx Event FIFO Watermark Reached Line        */
+#define FDCAN_ILS_TEFFL_Pos       (14U)
+#define FDCAN_ILS_TEFFL_Msk       (0x1UL << FDCAN_ILS_TEFFL_Pos)               /*!< 0x00004000 */
+#define FDCAN_ILS_TEFFL           FDCAN_ILS_TEFFL_Msk                          /*!<Tx Event FIFO Full Line                     */
+#define FDCAN_ILS_TEFLL_Pos       (15U)
+#define FDCAN_ILS_TEFLL_Msk       (0x1UL << FDCAN_ILS_TEFLL_Pos)               /*!< 0x00008000 */
+#define FDCAN_ILS_TEFLL           FDCAN_ILS_TEFLL_Msk                          /*!<Tx Event FIFO Element Lost Line             */
+#define FDCAN_ILS_TSWL_Pos        (16U)
+#define FDCAN_ILS_TSWL_Msk        (0x1UL << FDCAN_ILS_TSWL_Pos)                /*!< 0x00010000 */
+#define FDCAN_ILS_TSWL            FDCAN_ILS_TSWL_Msk                           /*!<Timestamp Wraparound Line                   */
+#define FDCAN_ILS_MRAFE_Pos       (17U)
+#define FDCAN_ILS_MRAFE_Msk       (0x1UL << FDCAN_ILS_MRAFE_Pos)               /*!< 0x00020000 */
+#define FDCAN_ILS_MRAFE           FDCAN_ILS_MRAFE_Msk                          /*!<Message RAM Access Failure Line             */
+#define FDCAN_ILS_TOOE_Pos        (18U)
+#define FDCAN_ILS_TOOE_Msk        (0x1UL << FDCAN_ILS_TOOE_Pos)                /*!< 0x00040000 */
+#define FDCAN_ILS_TOOE            FDCAN_ILS_TOOE_Msk                           /*!<Timeout Occurred Line                       */
+#define FDCAN_ILS_DRXE_Pos        (19U)
+#define FDCAN_ILS_DRXE_Msk        (0x1UL << FDCAN_ILS_DRXE_Pos)                /*!< 0x00080000 */
+#define FDCAN_ILS_DRXE            FDCAN_ILS_DRXE_Msk                           /*!<Message stored to Dedicated Rx Buffer Line  */
+#define FDCAN_ILS_BECE_Pos        (20U)
+#define FDCAN_ILS_BECE_Msk        (0x1UL << FDCAN_ILS_BECE_Pos)                /*!< 0x00100000 */
+#define FDCAN_ILS_BECE            FDCAN_ILS_BECE_Msk                           /*!<Bit Error Corrected Interrupt Line          */
+#define FDCAN_ILS_BEUE_Pos        (21U)
+#define FDCAN_ILS_BEUE_Msk        (0x1UL << FDCAN_ILS_BEUE_Pos)                /*!< 0x00200000 */
+#define FDCAN_ILS_BEUE            FDCAN_ILS_BEUE_Msk                           /*!<Bit Error Uncorrected Interrupt Line        */
+#define FDCAN_ILS_ELOE_Pos        (22U)
+#define FDCAN_ILS_ELOE_Msk        (0x1UL << FDCAN_ILS_ELOE_Pos)                /*!< 0x00400000 */
+#define FDCAN_ILS_ELOE            FDCAN_ILS_ELOE_Msk                           /*!<Error Logging Overflow Line                 */
+#define FDCAN_ILS_EPE_Pos         (23U)
+#define FDCAN_ILS_EPE_Msk         (0x1UL << FDCAN_ILS_EPE_Pos)                 /*!< 0x00800000 */
+#define FDCAN_ILS_EPE             FDCAN_ILS_EPE_Msk                            /*!<Error Passive Line                          */
+#define FDCAN_ILS_EWE_Pos         (24U)
+#define FDCAN_ILS_EWE_Msk         (0x1UL << FDCAN_ILS_EWE_Pos)                 /*!< 0x01000000 */
+#define FDCAN_ILS_EWE             FDCAN_ILS_EWE_Msk                            /*!<Warning Status Line                         */
+#define FDCAN_ILS_BOE_Pos         (25U)
+#define FDCAN_ILS_BOE_Msk         (0x1UL << FDCAN_ILS_BOE_Pos)                 /*!< 0x02000000 */
+#define FDCAN_ILS_BOE             FDCAN_ILS_BOE_Msk                            /*!<Bus_Off Status Line                         */
+#define FDCAN_ILS_WDIE_Pos        (26U)
+#define FDCAN_ILS_WDIE_Msk        (0x1UL << FDCAN_ILS_WDIE_Pos)                /*!< 0x04000000 */
+#define FDCAN_ILS_WDIE            FDCAN_ILS_WDIE_Msk                           /*!<Watchdog Interrupt Line                     */
+#define FDCAN_ILS_PEAE_Pos        (27U)
+#define FDCAN_ILS_PEAE_Msk        (0x1UL << FDCAN_ILS_PEAE_Pos)                /*!< 0x08000000 */
+#define FDCAN_ILS_PEAE            FDCAN_ILS_PEAE_Msk                           /*!<Protocol Error in Arbitration Phase Line    */
+#define FDCAN_ILS_PEDE_Pos        (28U)
+#define FDCAN_ILS_PEDE_Msk        (0x1UL << FDCAN_ILS_PEDE_Pos)                /*!< 0x10000000 */
+#define FDCAN_ILS_PEDE            FDCAN_ILS_PEDE_Msk                           /*!<Protocol Error in Data Phase Line           */
+#define FDCAN_ILS_ARAE_Pos        (29U)
+#define FDCAN_ILS_ARAE_Msk        (0x1UL << FDCAN_ILS_ARAE_Pos)                /*!< 0x20000000 */
+#define FDCAN_ILS_ARAE            FDCAN_ILS_ARAE_Msk                           /*!<Access to Reserved Address Line             */
+
+/*****************  Bit definition for FDCAN_ILE register  **********************/
+#define FDCAN_ILE_EINT0_Pos       (0U)
+#define FDCAN_ILE_EINT0_Msk       (0x1UL << FDCAN_ILE_EINT0_Pos)               /*!< 0x00000001 */
+#define FDCAN_ILE_EINT0           FDCAN_ILE_EINT0_Msk                          /*!<Enable Interrupt Line 0                   */
+#define FDCAN_ILE_EINT1_Pos       (1U)
+#define FDCAN_ILE_EINT1_Msk       (0x1UL << FDCAN_ILE_EINT1_Pos)               /*!< 0x00000002 */
+#define FDCAN_ILE_EINT1           FDCAN_ILE_EINT1_Msk                          /*!<Enable Interrupt Line 1                   */
+
+/*****************  Bit definition for FDCAN_GFC register  **********************/
+#define FDCAN_GFC_RRFE_Pos        (0U)
+#define FDCAN_GFC_RRFE_Msk        (0x1UL << FDCAN_GFC_RRFE_Pos)                /*!< 0x00000001 */
+#define FDCAN_GFC_RRFE            FDCAN_GFC_RRFE_Msk                           /*!<Reject Remote Frames Extended             */
+#define FDCAN_GFC_RRFS_Pos        (1U)
+#define FDCAN_GFC_RRFS_Msk        (0x1UL << FDCAN_GFC_RRFS_Pos)                /*!< 0x00000002 */
+#define FDCAN_GFC_RRFS            FDCAN_GFC_RRFS_Msk                           /*!<Reject Remote Frames Standard             */
+#define FDCAN_GFC_ANFE_Pos        (2U)
+#define FDCAN_GFC_ANFE_Msk        (0x3UL << FDCAN_GFC_ANFE_Pos)                /*!< 0x0000000C */
+#define FDCAN_GFC_ANFE            FDCAN_GFC_ANFE_Msk                           /*!<Accept Non-matching Frames Extended       */
+#define FDCAN_GFC_ANFS_Pos        (4U)
+#define FDCAN_GFC_ANFS_Msk        (0x3UL << FDCAN_GFC_ANFS_Pos)                /*!< 0x00000030 */
+#define FDCAN_GFC_ANFS            FDCAN_GFC_ANFS_Msk                           /*!<Accept Non-matching Frames Standard       */
+
+/*****************  Bit definition for FDCAN_SIDFC register  ********************/
+#define FDCAN_SIDFC_FLSSA_Pos     (2U)
+#define FDCAN_SIDFC_FLSSA_Msk     (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos)          /*!< 0x0000FFFC */
+#define FDCAN_SIDFC_FLSSA         FDCAN_SIDFC_FLSSA_Msk                        /*!<Filter List Standard Start Address        */
+#define FDCAN_SIDFC_LSS_Pos       (16U)
+#define FDCAN_SIDFC_LSS_Msk       (0xFFUL << FDCAN_SIDFC_LSS_Pos)              /*!< 0x00FF0000 */
+#define FDCAN_SIDFC_LSS           FDCAN_SIDFC_LSS_Msk                          /*!<List Size Standard                        */
+
+/*****************  Bit definition for FDCAN_XIDFC register  ********************/
+#define FDCAN_XIDFC_FLESA_Pos     (2U)
+#define FDCAN_XIDFC_FLESA_Msk     (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos)          /*!< 0x0000FFFC */
+#define FDCAN_XIDFC_FLESA         FDCAN_XIDFC_FLESA_Msk                        /*!<Filter List Standard Start Address        */
+#define FDCAN_XIDFC_LSE_Pos       (16U)
+#define FDCAN_XIDFC_LSE_Msk       (0x7FUL << FDCAN_XIDFC_LSE_Pos)              /*!< 0x007F0000 */
+#define FDCAN_XIDFC_LSE           FDCAN_XIDFC_LSE_Msk                          /*!<List Size Extended                        */
+
+/*****************  Bit definition for FDCAN_XIDAM register  ********************/
+#define FDCAN_XIDAM_EIDM_Pos      (0U)
+#define FDCAN_XIDAM_EIDM_Msk      (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)       /*!< 0x1FFFFFFF */
+#define FDCAN_XIDAM_EIDM          FDCAN_XIDAM_EIDM_Msk                         /*!<Extended ID Mask                          */
+
+/*****************  Bit definition for FDCAN_HPMS register  *********************/
+#define FDCAN_HPMS_BIDX_Pos       (0U)
+#define FDCAN_HPMS_BIDX_Msk       (0x3FUL << FDCAN_HPMS_BIDX_Pos)              /*!< 0x0000003F */
+#define FDCAN_HPMS_BIDX           FDCAN_HPMS_BIDX_Msk                          /*!<Buffer Index                              */
+#define FDCAN_HPMS_MSI_Pos        (6U)
+#define FDCAN_HPMS_MSI_Msk        (0x3UL << FDCAN_HPMS_MSI_Pos)                /*!< 0x000000C0 */
+#define FDCAN_HPMS_MSI            FDCAN_HPMS_MSI_Msk                           /*!<Message Storage Indicator                 */
+#define FDCAN_HPMS_FIDX_Pos       (8U)
+#define FDCAN_HPMS_FIDX_Msk       (0x7FUL << FDCAN_HPMS_FIDX_Pos)              /*!< 0x00007F00 */
+#define FDCAN_HPMS_FIDX           FDCAN_HPMS_FIDX_Msk                          /*!<Filter Index                              */
+#define FDCAN_HPMS_FLST_Pos       (15U)
+#define FDCAN_HPMS_FLST_Msk       (0x1UL << FDCAN_HPMS_FLST_Pos)               /*!< 0x00008000 */
+#define FDCAN_HPMS_FLST           FDCAN_HPMS_FLST_Msk                          /*!<Filter List                               */
+
+/*****************  Bit definition for FDCAN_NDAT1 register  ********************/
+#define FDCAN_NDAT1_ND0_Pos       (0U)
+#define FDCAN_NDAT1_ND0_Msk       (0x1UL << FDCAN_NDAT1_ND0_Pos)               /*!< 0x00000001 */
+#define FDCAN_NDAT1_ND0           FDCAN_NDAT1_ND0_Msk                          /*!<New Data flag of Rx Buffer 0              */
+#define FDCAN_NDAT1_ND1_Pos       (1U)
+#define FDCAN_NDAT1_ND1_Msk       (0x1UL << FDCAN_NDAT1_ND1_Pos)               /*!< 0x00000002 */
+#define FDCAN_NDAT1_ND1           FDCAN_NDAT1_ND1_Msk                          /*!<New Data flag of Rx Buffer 1              */
+#define FDCAN_NDAT1_ND2_Pos       (2U)
+#define FDCAN_NDAT1_ND2_Msk       (0x1UL << FDCAN_NDAT1_ND2_Pos)               /*!< 0x00000004 */
+#define FDCAN_NDAT1_ND2           FDCAN_NDAT1_ND2_Msk                          /*!<New Data flag of Rx Buffer 2              */
+#define FDCAN_NDAT1_ND3_Pos       (3U)
+#define FDCAN_NDAT1_ND3_Msk       (0x1UL << FDCAN_NDAT1_ND3_Pos)               /*!< 0x00000008 */
+#define FDCAN_NDAT1_ND3           FDCAN_NDAT1_ND3_Msk                          /*!<New Data flag of Rx Buffer 3              */
+#define FDCAN_NDAT1_ND4_Pos       (4U)
+#define FDCAN_NDAT1_ND4_Msk       (0x1UL << FDCAN_NDAT1_ND4_Pos)               /*!< 0x00000010 */
+#define FDCAN_NDAT1_ND4           FDCAN_NDAT1_ND4_Msk                          /*!<New Data flag of Rx Buffer 4              */
+#define FDCAN_NDAT1_ND5_Pos       (5U)
+#define FDCAN_NDAT1_ND5_Msk       (0x1UL << FDCAN_NDAT1_ND5_Pos)               /*!< 0x00000020 */
+#define FDCAN_NDAT1_ND5           FDCAN_NDAT1_ND5_Msk                          /*!<New Data flag of Rx Buffer 5              */
+#define FDCAN_NDAT1_ND6_Pos       (6U)
+#define FDCAN_NDAT1_ND6_Msk       (0x1UL << FDCAN_NDAT1_ND6_Pos)               /*!< 0x00000040 */
+#define FDCAN_NDAT1_ND6           FDCAN_NDAT1_ND6_Msk                          /*!<New Data flag of Rx Buffer 6              */
+#define FDCAN_NDAT1_ND7_Pos       (7U)
+#define FDCAN_NDAT1_ND7_Msk       (0x1UL << FDCAN_NDAT1_ND7_Pos)               /*!< 0x00000080 */
+#define FDCAN_NDAT1_ND7           FDCAN_NDAT1_ND7_Msk                          /*!<New Data flag of Rx Buffer 7              */
+#define FDCAN_NDAT1_ND8_Pos       (8U)
+#define FDCAN_NDAT1_ND8_Msk       (0x1UL << FDCAN_NDAT1_ND8_Pos)               /*!< 0x00000100 */
+#define FDCAN_NDAT1_ND8           FDCAN_NDAT1_ND8_Msk                          /*!<New Data flag of Rx Buffer 8              */
+#define FDCAN_NDAT1_ND9_Pos       (9U)
+#define FDCAN_NDAT1_ND9_Msk       (0x1UL << FDCAN_NDAT1_ND9_Pos)               /*!< 0x00000200 */
+#define FDCAN_NDAT1_ND9           FDCAN_NDAT1_ND9_Msk                          /*!<New Data flag of Rx Buffer 9              */
+#define FDCAN_NDAT1_ND10_Pos      (10U)
+#define FDCAN_NDAT1_ND10_Msk      (0x1UL << FDCAN_NDAT1_ND10_Pos)              /*!< 0x00000400 */
+#define FDCAN_NDAT1_ND10          FDCAN_NDAT1_ND10_Msk                         /*!<New Data flag of Rx Buffer 10             */
+#define FDCAN_NDAT1_ND11_Pos      (11U)
+#define FDCAN_NDAT1_ND11_Msk      (0x1UL << FDCAN_NDAT1_ND11_Pos)              /*!< 0x00000800 */
+#define FDCAN_NDAT1_ND11          FDCAN_NDAT1_ND11_Msk                         /*!<New Data flag of Rx Buffer 11             */
+#define FDCAN_NDAT1_ND12_Pos      (12U)
+#define FDCAN_NDAT1_ND12_Msk      (0x1UL << FDCAN_NDAT1_ND12_Pos)              /*!< 0x00001000 */
+#define FDCAN_NDAT1_ND12          FDCAN_NDAT1_ND12_Msk                         /*!<New Data flag of Rx Buffer 12             */
+#define FDCAN_NDAT1_ND13_Pos      (13U)
+#define FDCAN_NDAT1_ND13_Msk      (0x1UL << FDCAN_NDAT1_ND13_Pos)              /*!< 0x00002000 */
+#define FDCAN_NDAT1_ND13          FDCAN_NDAT1_ND13_Msk                         /*!<New Data flag of Rx Buffer 13             */
+#define FDCAN_NDAT1_ND14_Pos      (14U)
+#define FDCAN_NDAT1_ND14_Msk      (0x1UL << FDCAN_NDAT1_ND14_Pos)              /*!< 0x00004000 */
+#define FDCAN_NDAT1_ND14          FDCAN_NDAT1_ND14_Msk                         /*!<New Data flag of Rx Buffer 14             */
+#define FDCAN_NDAT1_ND15_Pos      (15U)
+#define FDCAN_NDAT1_ND15_Msk      (0x1UL << FDCAN_NDAT1_ND15_Pos)              /*!< 0x00008000 */
+#define FDCAN_NDAT1_ND15          FDCAN_NDAT1_ND15_Msk                         /*!<New Data flag of Rx Buffer 15             */
+#define FDCAN_NDAT1_ND16_Pos      (16U)
+#define FDCAN_NDAT1_ND16_Msk      (0x1UL << FDCAN_NDAT1_ND16_Pos)              /*!< 0x00010000 */
+#define FDCAN_NDAT1_ND16          FDCAN_NDAT1_ND16_Msk                         /*!<New Data flag of Rx Buffer 16             */
+#define FDCAN_NDAT1_ND17_Pos      (17U)
+#define FDCAN_NDAT1_ND17_Msk      (0x1UL << FDCAN_NDAT1_ND17_Pos)              /*!< 0x00020000 */
+#define FDCAN_NDAT1_ND17          FDCAN_NDAT1_ND17_Msk                         /*!<New Data flag of Rx Buffer 17             */
+#define FDCAN_NDAT1_ND18_Pos      (18U)
+#define FDCAN_NDAT1_ND18_Msk      (0x1UL << FDCAN_NDAT1_ND18_Pos)              /*!< 0x00040000 */
+#define FDCAN_NDAT1_ND18          FDCAN_NDAT1_ND18_Msk                         /*!<New Data flag of Rx Buffer 18             */
+#define FDCAN_NDAT1_ND19_Pos      (19U)
+#define FDCAN_NDAT1_ND19_Msk      (0x1UL << FDCAN_NDAT1_ND19_Pos)              /*!< 0x00080000 */
+#define FDCAN_NDAT1_ND19          FDCAN_NDAT1_ND19_Msk                         /*!<New Data flag of Rx Buffer 19             */
+#define FDCAN_NDAT1_ND20_Pos      (20U)
+#define FDCAN_NDAT1_ND20_Msk      (0x1UL << FDCAN_NDAT1_ND20_Pos)              /*!< 0x00100000 */
+#define FDCAN_NDAT1_ND20          FDCAN_NDAT1_ND20_Msk                         /*!<New Data flag of Rx Buffer 20             */
+#define FDCAN_NDAT1_ND21_Pos      (21U)
+#define FDCAN_NDAT1_ND21_Msk      (0x1UL << FDCAN_NDAT1_ND21_Pos)              /*!< 0x00200000 */
+#define FDCAN_NDAT1_ND21          FDCAN_NDAT1_ND21_Msk                         /*!<New Data flag of Rx Buffer 21             */
+#define FDCAN_NDAT1_ND22_Pos      (22U)
+#define FDCAN_NDAT1_ND22_Msk      (0x1UL << FDCAN_NDAT1_ND22_Pos)              /*!< 0x00400000 */
+#define FDCAN_NDAT1_ND22          FDCAN_NDAT1_ND22_Msk                         /*!<New Data flag of Rx Buffer 22             */
+#define FDCAN_NDAT1_ND23_Pos      (23U)
+#define FDCAN_NDAT1_ND23_Msk      (0x1UL << FDCAN_NDAT1_ND23_Pos)              /*!< 0x00800000 */
+#define FDCAN_NDAT1_ND23          FDCAN_NDAT1_ND23_Msk                         /*!<New Data flag of Rx Buffer 23             */
+#define FDCAN_NDAT1_ND24_Pos      (24U)
+#define FDCAN_NDAT1_ND24_Msk      (0x1UL << FDCAN_NDAT1_ND24_Pos)              /*!< 0x01000000 */
+#define FDCAN_NDAT1_ND24          FDCAN_NDAT1_ND24_Msk                         /*!<New Data flag of Rx Buffer 24             */
+#define FDCAN_NDAT1_ND25_Pos      (25U)
+#define FDCAN_NDAT1_ND25_Msk      (0x1UL << FDCAN_NDAT1_ND25_Pos)              /*!< 0x02000000 */
+#define FDCAN_NDAT1_ND25          FDCAN_NDAT1_ND25_Msk                         /*!<New Data flag of Rx Buffer 25             */
+#define FDCAN_NDAT1_ND26_Pos      (26U)
+#define FDCAN_NDAT1_ND26_Msk      (0x1UL << FDCAN_NDAT1_ND26_Pos)              /*!< 0x04000000 */
+#define FDCAN_NDAT1_ND26          FDCAN_NDAT1_ND26_Msk                         /*!<New Data flag of Rx Buffer 26             */
+#define FDCAN_NDAT1_ND27_Pos      (27U)
+#define FDCAN_NDAT1_ND27_Msk      (0x1UL << FDCAN_NDAT1_ND27_Pos)              /*!< 0x08000000 */
+#define FDCAN_NDAT1_ND27          FDCAN_NDAT1_ND27_Msk                         /*!<New Data flag of Rx Buffer 27             */
+#define FDCAN_NDAT1_ND28_Pos      (28U)
+#define FDCAN_NDAT1_ND28_Msk      (0x1UL << FDCAN_NDAT1_ND28_Pos)              /*!< 0x10000000 */
+#define FDCAN_NDAT1_ND28          FDCAN_NDAT1_ND28_Msk                         /*!<New Data flag of Rx Buffer 28             */
+#define FDCAN_NDAT1_ND29_Pos      (29U)
+#define FDCAN_NDAT1_ND29_Msk      (0x1UL << FDCAN_NDAT1_ND29_Pos)              /*!< 0x20000000 */
+#define FDCAN_NDAT1_ND29          FDCAN_NDAT1_ND29_Msk                         /*!<New Data flag of Rx Buffer 29             */
+#define FDCAN_NDAT1_ND30_Pos      (30U)
+#define FDCAN_NDAT1_ND30_Msk      (0x1UL << FDCAN_NDAT1_ND30_Pos)              /*!< 0x40000000 */
+#define FDCAN_NDAT1_ND30          FDCAN_NDAT1_ND30_Msk                         /*!<New Data flag of Rx Buffer 30             */
+#define FDCAN_NDAT1_ND31_Pos      (31U)
+#define FDCAN_NDAT1_ND31_Msk      (0x1UL << FDCAN_NDAT1_ND31_Pos)              /*!< 0x80000000 */
+#define FDCAN_NDAT1_ND31          FDCAN_NDAT1_ND31_Msk                         /*!<New Data flag of Rx Buffer 31             */
+
+/*****************  Bit definition for FDCAN_NDAT2 register  ********************/
+#define FDCAN_NDAT2_ND32_Pos      (0U)
+#define FDCAN_NDAT2_ND32_Msk      (0x1UL << FDCAN_NDAT2_ND32_Pos)              /*!< 0x00000001 */
+#define FDCAN_NDAT2_ND32          FDCAN_NDAT2_ND32_Msk                         /*!<New Data flag of Rx Buffer 32             */
+#define FDCAN_NDAT2_ND33_Pos      (1U)
+#define FDCAN_NDAT2_ND33_Msk      (0x1UL << FDCAN_NDAT2_ND33_Pos)              /*!< 0x00000002 */
+#define FDCAN_NDAT2_ND33          FDCAN_NDAT2_ND33_Msk                         /*!<New Data flag of Rx Buffer 33             */
+#define FDCAN_NDAT2_ND34_Pos      (2U)
+#define FDCAN_NDAT2_ND34_Msk      (0x1UL << FDCAN_NDAT2_ND34_Pos)              /*!< 0x00000004 */
+#define FDCAN_NDAT2_ND34          FDCAN_NDAT2_ND34_Msk                         /*!<New Data flag of Rx Buffer 34             */
+#define FDCAN_NDAT2_ND35_Pos      (3U)
+#define FDCAN_NDAT2_ND35_Msk      (0x1UL << FDCAN_NDAT2_ND35_Pos)              /*!< 0x00000008 */
+#define FDCAN_NDAT2_ND35          FDCAN_NDAT2_ND35_Msk                         /*!<New Data flag of Rx Buffer 35             */
+#define FDCAN_NDAT2_ND36_Pos      (4U)
+#define FDCAN_NDAT2_ND36_Msk      (0x1UL << FDCAN_NDAT2_ND36_Pos)              /*!< 0x00000010 */
+#define FDCAN_NDAT2_ND36          FDCAN_NDAT2_ND36_Msk                         /*!<New Data flag of Rx Buffer 36             */
+#define FDCAN_NDAT2_ND37_Pos      (5U)
+#define FDCAN_NDAT2_ND37_Msk      (0x1UL << FDCAN_NDAT2_ND37_Pos)              /*!< 0x00000020 */
+#define FDCAN_NDAT2_ND37          FDCAN_NDAT2_ND37_Msk                         /*!<New Data flag of Rx Buffer 37             */
+#define FDCAN_NDAT2_ND38_Pos      (6U)
+#define FDCAN_NDAT2_ND38_Msk      (0x1UL << FDCAN_NDAT2_ND38_Pos)              /*!< 0x00000040 */
+#define FDCAN_NDAT2_ND38          FDCAN_NDAT2_ND38_Msk                         /*!<New Data flag of Rx Buffer 38             */
+#define FDCAN_NDAT2_ND39_Pos      (7U)
+#define FDCAN_NDAT2_ND39_Msk      (0x1UL << FDCAN_NDAT2_ND39_Pos)              /*!< 0x00000080 */
+#define FDCAN_NDAT2_ND39          FDCAN_NDAT2_ND39_Msk                         /*!<New Data flag of Rx Buffer 39             */
+#define FDCAN_NDAT2_ND40_Pos      (8U)
+#define FDCAN_NDAT2_ND40_Msk      (0x1UL << FDCAN_NDAT2_ND40_Pos)              /*!< 0x00000100 */
+#define FDCAN_NDAT2_ND40          FDCAN_NDAT2_ND40_Msk                         /*!<New Data flag of Rx Buffer 40             */
+#define FDCAN_NDAT2_ND41_Pos      (9U)
+#define FDCAN_NDAT2_ND41_Msk      (0x1UL << FDCAN_NDAT2_ND41_Pos)              /*!< 0x00000200 */
+#define FDCAN_NDAT2_ND41          FDCAN_NDAT2_ND41_Msk                         /*!<New Data flag of Rx Buffer 41             */
+#define FDCAN_NDAT2_ND42_Pos      (10U)
+#define FDCAN_NDAT2_ND42_Msk      (0x1UL << FDCAN_NDAT2_ND42_Pos)              /*!< 0x00000400 */
+#define FDCAN_NDAT2_ND42          FDCAN_NDAT2_ND42_Msk                         /*!<New Data flag of Rx Buffer 42             */
+#define FDCAN_NDAT2_ND43_Pos      (11U)
+#define FDCAN_NDAT2_ND43_Msk      (0x1UL << FDCAN_NDAT2_ND43_Pos)              /*!< 0x00000800 */
+#define FDCAN_NDAT2_ND43          FDCAN_NDAT2_ND43_Msk                         /*!<New Data flag of Rx Buffer 43             */
+#define FDCAN_NDAT2_ND44_Pos      (12U)
+#define FDCAN_NDAT2_ND44_Msk      (0x1UL << FDCAN_NDAT2_ND44_Pos)              /*!< 0x00001000 */
+#define FDCAN_NDAT2_ND44          FDCAN_NDAT2_ND44_Msk                         /*!<New Data flag of Rx Buffer 44             */
+#define FDCAN_NDAT2_ND45_Pos      (13U)
+#define FDCAN_NDAT2_ND45_Msk      (0x1UL << FDCAN_NDAT2_ND45_Pos)              /*!< 0x00002000 */
+#define FDCAN_NDAT2_ND45          FDCAN_NDAT2_ND45_Msk                         /*!<New Data flag of Rx Buffer 45             */
+#define FDCAN_NDAT2_ND46_Pos      (14U)
+#define FDCAN_NDAT2_ND46_Msk      (0x1UL << FDCAN_NDAT2_ND46_Pos)              /*!< 0x00004000 */
+#define FDCAN_NDAT2_ND46          FDCAN_NDAT2_ND46_Msk                         /*!<New Data flag of Rx Buffer 46             */
+#define FDCAN_NDAT2_ND47_Pos      (15U)
+#define FDCAN_NDAT2_ND47_Msk      (0x1UL << FDCAN_NDAT2_ND47_Pos)              /*!< 0x00008000 */
+#define FDCAN_NDAT2_ND47          FDCAN_NDAT2_ND47_Msk                         /*!<New Data flag of Rx Buffer 47             */
+#define FDCAN_NDAT2_ND48_Pos      (16U)
+#define FDCAN_NDAT2_ND48_Msk      (0x1UL << FDCAN_NDAT2_ND48_Pos)              /*!< 0x00010000 */
+#define FDCAN_NDAT2_ND48          FDCAN_NDAT2_ND48_Msk                         /*!<New Data flag of Rx Buffer 48             */
+#define FDCAN_NDAT2_ND49_Pos      (17U)
+#define FDCAN_NDAT2_ND49_Msk      (0x1UL << FDCAN_NDAT2_ND49_Pos)              /*!< 0x00020000 */
+#define FDCAN_NDAT2_ND49          FDCAN_NDAT2_ND49_Msk                         /*!<New Data flag of Rx Buffer 49             */
+#define FDCAN_NDAT2_ND50_Pos      (18U)
+#define FDCAN_NDAT2_ND50_Msk      (0x1UL << FDCAN_NDAT2_ND50_Pos)              /*!< 0x00040000 */
+#define FDCAN_NDAT2_ND50          FDCAN_NDAT2_ND50_Msk                         /*!<New Data flag of Rx Buffer 50             */
+#define FDCAN_NDAT2_ND51_Pos      (19U)
+#define FDCAN_NDAT2_ND51_Msk      (0x1UL << FDCAN_NDAT2_ND51_Pos)              /*!< 0x00080000 */
+#define FDCAN_NDAT2_ND51          FDCAN_NDAT2_ND51_Msk                         /*!<New Data flag of Rx Buffer 51             */
+#define FDCAN_NDAT2_ND52_Pos      (20U)
+#define FDCAN_NDAT2_ND52_Msk      (0x1UL << FDCAN_NDAT2_ND52_Pos)              /*!< 0x00100000 */
+#define FDCAN_NDAT2_ND52          FDCAN_NDAT2_ND52_Msk                         /*!<New Data flag of Rx Buffer 52             */
+#define FDCAN_NDAT2_ND53_Pos      (21U)
+#define FDCAN_NDAT2_ND53_Msk      (0x1UL << FDCAN_NDAT2_ND53_Pos)              /*!< 0x00200000 */
+#define FDCAN_NDAT2_ND53          FDCAN_NDAT2_ND53_Msk                         /*!<New Data flag of Rx Buffer 53             */
+#define FDCAN_NDAT2_ND54_Pos      (22U)
+#define FDCAN_NDAT2_ND54_Msk      (0x1UL << FDCAN_NDAT2_ND54_Pos)              /*!< 0x00400000 */
+#define FDCAN_NDAT2_ND54          FDCAN_NDAT2_ND54_Msk                         /*!<New Data flag of Rx Buffer 54             */
+#define FDCAN_NDAT2_ND55_Pos      (23U)
+#define FDCAN_NDAT2_ND55_Msk      (0x1UL << FDCAN_NDAT2_ND55_Pos)              /*!< 0x00800000 */
+#define FDCAN_NDAT2_ND55          FDCAN_NDAT2_ND55_Msk                         /*!<New Data flag of Rx Buffer 55             */
+#define FDCAN_NDAT2_ND56_Pos      (24U)
+#define FDCAN_NDAT2_ND56_Msk      (0x1UL << FDCAN_NDAT2_ND56_Pos)              /*!< 0x01000000 */
+#define FDCAN_NDAT2_ND56          FDCAN_NDAT2_ND56_Msk                         /*!<New Data flag of Rx Buffer 56             */
+#define FDCAN_NDAT2_ND57_Pos      (25U)
+#define FDCAN_NDAT2_ND57_Msk      (0x1UL << FDCAN_NDAT2_ND57_Pos)              /*!< 0x02000000 */
+#define FDCAN_NDAT2_ND57          FDCAN_NDAT2_ND57_Msk                         /*!<New Data flag of Rx Buffer 57             */
+#define FDCAN_NDAT2_ND58_Pos      (26U)
+#define FDCAN_NDAT2_ND58_Msk      (0x1UL << FDCAN_NDAT2_ND58_Pos)              /*!< 0x04000000 */
+#define FDCAN_NDAT2_ND58          FDCAN_NDAT2_ND58_Msk                         /*!<New Data flag of Rx Buffer 58             */
+#define FDCAN_NDAT2_ND59_Pos      (27U)
+#define FDCAN_NDAT2_ND59_Msk      (0x1UL << FDCAN_NDAT2_ND59_Pos)              /*!< 0x08000000 */
+#define FDCAN_NDAT2_ND59          FDCAN_NDAT2_ND59_Msk                         /*!<New Data flag of Rx Buffer 59             */
+#define FDCAN_NDAT2_ND60_Pos      (28U)
+#define FDCAN_NDAT2_ND60_Msk      (0x1UL << FDCAN_NDAT2_ND60_Pos)              /*!< 0x10000000 */
+#define FDCAN_NDAT2_ND60          FDCAN_NDAT2_ND60_Msk                         /*!<New Data flag of Rx Buffer 60             */
+#define FDCAN_NDAT2_ND61_Pos      (29U)
+#define FDCAN_NDAT2_ND61_Msk      (0x1UL << FDCAN_NDAT2_ND61_Pos)              /*!< 0x20000000 */
+#define FDCAN_NDAT2_ND61          FDCAN_NDAT2_ND61_Msk                         /*!<New Data flag of Rx Buffer 61             */
+#define FDCAN_NDAT2_ND62_Pos      (30U)
+#define FDCAN_NDAT2_ND62_Msk      (0x1UL << FDCAN_NDAT2_ND62_Pos)              /*!< 0x40000000 */
+#define FDCAN_NDAT2_ND62          FDCAN_NDAT2_ND62_Msk                         /*!<New Data flag of Rx Buffer 62             */
+#define FDCAN_NDAT2_ND63_Pos      (31U)
+#define FDCAN_NDAT2_ND63_Msk      (0x1UL << FDCAN_NDAT2_ND63_Pos)              /*!< 0x80000000 */
+#define FDCAN_NDAT2_ND63          FDCAN_NDAT2_ND63_Msk                         /*!<New Data flag of Rx Buffer 63             */
+
+/*****************  Bit definition for FDCAN_RXF0C register  ********************/
+#define FDCAN_RXF0C_F0SA_Pos      (2U)
+#define FDCAN_RXF0C_F0SA_Msk      (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos)           /*!< 0x0000FFFC */
+#define FDCAN_RXF0C_F0SA          FDCAN_RXF0C_F0SA_Msk                         /*!<Rx FIFO 0 Start Address                   */
+#define FDCAN_RXF0C_F0S_Pos       (16U)
+#define FDCAN_RXF0C_F0S_Msk       (0x7FUL << FDCAN_RXF0C_F0S_Pos)              /*!< 0x007F0000 */
+#define FDCAN_RXF0C_F0S           FDCAN_RXF0C_F0S_Msk                          /*!<Number of Rx FIFO 0 elements              */
+#define FDCAN_RXF0C_F0WM_Pos      (24U)
+#define FDCAN_RXF0C_F0WM_Msk      (0x7FUL << FDCAN_RXF0C_F0WM_Pos)             /*!< 0x7F000000 */
+#define FDCAN_RXF0C_F0WM          FDCAN_RXF0C_F0WM_Msk                         /*!<FIFO 0 Watermark                          */
+#define FDCAN_RXF0C_F0OM_Pos      (31U)
+#define FDCAN_RXF0C_F0OM_Msk      (0x1UL << FDCAN_RXF0C_F0OM_Pos)              /*!< 0x80000000 */
+#define FDCAN_RXF0C_F0OM          FDCAN_RXF0C_F0OM_Msk                         /*!<FIFO 0 Operation Mode                     */
+
+/*****************  Bit definition for FDCAN_RXF0S register  ********************/
+#define FDCAN_RXF0S_F0FL_Pos      (0U)
+#define FDCAN_RXF0S_F0FL_Msk      (0x7FUL << FDCAN_RXF0S_F0FL_Pos)             /*!< 0x0000007F */
+#define FDCAN_RXF0S_F0FL          FDCAN_RXF0S_F0FL_Msk                         /*!<Rx FIFO 0 Fill Level                      */
+#define FDCAN_RXF0S_F0GI_Pos      (8U)
+#define FDCAN_RXF0S_F0GI_Msk      (0x3FUL << FDCAN_RXF0S_F0GI_Pos)             /*!< 0x00003F00 */
+#define FDCAN_RXF0S_F0GI          FDCAN_RXF0S_F0GI_Msk                         /*!<Rx FIFO 0 Get Index                       */
+#define FDCAN_RXF0S_F0PI_Pos      (16U)
+#define FDCAN_RXF0S_F0PI_Msk      (0x3FUL << FDCAN_RXF0S_F0PI_Pos)             /*!< 0x003F0000 */
+#define FDCAN_RXF0S_F0PI          FDCAN_RXF0S_F0PI_Msk                         /*!<Rx FIFO 0 Put Index                       */
+#define FDCAN_RXF0S_F0F_Pos       (24U)
+#define FDCAN_RXF0S_F0F_Msk       (0x1UL << FDCAN_RXF0S_F0F_Pos)               /*!< 0x01000000 */
+#define FDCAN_RXF0S_F0F           FDCAN_RXF0S_F0F_Msk                          /*!<Rx FIFO 0 Full                            */
+#define FDCAN_RXF0S_RF0L_Pos      (25U)
+#define FDCAN_RXF0S_RF0L_Msk      (0x1UL << FDCAN_RXF0S_RF0L_Pos)              /*!< 0x02000000 */
+#define FDCAN_RXF0S_RF0L          FDCAN_RXF0S_RF0L_Msk                         /*!<Rx FIFO 0 Message Lost                    */
+
+/*****************  Bit definition for FDCAN_RXF0A register  ********************/
+#define FDCAN_RXF0A_F0AI_Pos      (0U)
+#define FDCAN_RXF0A_F0AI_Msk      (0x3FUL << FDCAN_RXF0A_F0AI_Pos)             /*!< 0x0000003F */
+#define FDCAN_RXF0A_F0AI          FDCAN_RXF0A_F0AI_Msk                         /*!<Rx FIFO 0 Acknowledge Index               */
+
+/*****************  Bit definition for FDCAN_RXBC register  ********************/
+#define FDCAN_RXBC_RBSA_Pos       (2U)
+#define FDCAN_RXBC_RBSA_Msk       (0x3FFFUL << FDCAN_RXBC_RBSA_Pos)            /*!< 0x0000FFFC */
+#define FDCAN_RXBC_RBSA           FDCAN_RXBC_RBSA_Msk                          /*!<Rx Buffer Start Address                   */
+
+/*****************  Bit definition for FDCAN_RXF1C register  ********************/
+#define FDCAN_RXF1C_F1SA_Pos      (2U)
+#define FDCAN_RXF1C_F1SA_Msk      (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos)           /*!< 0x0000FFFC */
+#define FDCAN_RXF1C_F1SA          FDCAN_RXF1C_F1SA_Msk                         /*!<Rx FIFO 1 Start Address                   */
+#define FDCAN_RXF1C_F1S_Pos       (16U)
+#define FDCAN_RXF1C_F1S_Msk       (0x7FUL << FDCAN_RXF1C_F1S_Pos)              /*!< 0x007F0000 */
+#define FDCAN_RXF1C_F1S           FDCAN_RXF1C_F1S_Msk                          /*!<Number of Rx FIFO 1 elements              */
+#define FDCAN_RXF1C_F1WM_Pos      (24U)
+#define FDCAN_RXF1C_F1WM_Msk      (0x7FUL << FDCAN_RXF1C_F1WM_Pos)             /*!< 0x7F000000 */
+#define FDCAN_RXF1C_F1WM          FDCAN_RXF1C_F1WM_Msk                         /*!<Rx FIFO 1 Watermark                       */
+#define FDCAN_RXF1C_F1OM_Pos      (31U)
+#define FDCAN_RXF1C_F1OM_Msk      (0x1UL << FDCAN_RXF1C_F1OM_Pos)              /*!< 0x80000000 */
+#define FDCAN_RXF1C_F1OM          FDCAN_RXF1C_F1OM_Msk                         /*!<FIFO 1 Operation Mode                     */
+
+/*****************  Bit definition for FDCAN_RXF1S register  ********************/
+#define FDCAN_RXF1S_F1FL_Pos      (0U)
+#define FDCAN_RXF1S_F1FL_Msk      (0x7FUL << FDCAN_RXF1S_F1FL_Pos)             /*!< 0x0000007F */
+#define FDCAN_RXF1S_F1FL          FDCAN_RXF1S_F1FL_Msk                         /*!<Rx FIFO 1 Fill Level                      */
+#define FDCAN_RXF1S_F1GI_Pos      (8U)
+#define FDCAN_RXF1S_F1GI_Msk      (0x3FUL << FDCAN_RXF1S_F1GI_Pos)             /*!< 0x00003F00 */
+#define FDCAN_RXF1S_F1GI          FDCAN_RXF1S_F1GI_Msk                         /*!<Rx FIFO 1 Get Index                       */
+#define FDCAN_RXF1S_F1PI_Pos      (16U)
+#define FDCAN_RXF1S_F1PI_Msk      (0x3FUL << FDCAN_RXF1S_F1PI_Pos)             /*!< 0x003F0000 */
+#define FDCAN_RXF1S_F1PI          FDCAN_RXF1S_F1PI_Msk                         /*!<Rx FIFO 1 Put Index                       */
+#define FDCAN_RXF1S_F1F_Pos       (24U)
+#define FDCAN_RXF1S_F1F_Msk       (0x1UL << FDCAN_RXF1S_F1F_Pos)               /*!< 0x01000000 */
+#define FDCAN_RXF1S_F1F           FDCAN_RXF1S_F1F_Msk                          /*!<Rx FIFO 1 Full                            */
+#define FDCAN_RXF1S_RF1L_Pos      (25U)
+#define FDCAN_RXF1S_RF1L_Msk      (0x1UL << FDCAN_RXF1S_RF1L_Pos)              /*!< 0x02000000 */
+#define FDCAN_RXF1S_RF1L          FDCAN_RXF1S_RF1L_Msk                         /*!<Rx FIFO 1 Message Lost                    */
+
+/*****************  Bit definition for FDCAN_RXF1A register  ********************/
+#define FDCAN_RXF1A_F1AI_Pos      (0U)
+#define FDCAN_RXF1A_F1AI_Msk      (0x3FUL << FDCAN_RXF1A_F1AI_Pos)             /*!< 0x0000003F */
+#define FDCAN_RXF1A_F1AI          FDCAN_RXF1A_F1AI_Msk                         /*!<Rx FIFO 1 Acknowledge Index               */
+
+/*****************  Bit definition for FDCAN_RXESC register  ********************/
+#define FDCAN_RXESC_F0DS_Pos      (0U)
+#define FDCAN_RXESC_F0DS_Msk      (0x7UL << FDCAN_RXESC_F0DS_Pos)              /*!< 0x00000007 */
+#define FDCAN_RXESC_F0DS          FDCAN_RXESC_F0DS_Msk                         /*!<Rx FIFO 1 Data Field Size                 */
+#define FDCAN_RXESC_F1DS_Pos      (4U)
+#define FDCAN_RXESC_F1DS_Msk      (0x7UL << FDCAN_RXESC_F1DS_Pos)              /*!< 0x00000070 */
+#define FDCAN_RXESC_F1DS          FDCAN_RXESC_F1DS_Msk                         /*!<Rx FIFO 0 Data Field Size                 */
+#define FDCAN_RXESC_RBDS_Pos      (8U)
+#define FDCAN_RXESC_RBDS_Msk      (0x7UL << FDCAN_RXESC_RBDS_Pos)              /*!< 0x00000700 */
+#define FDCAN_RXESC_RBDS          FDCAN_RXESC_RBDS_Msk                         /*!<Rx Buffer Data Field Size                 */
+
+/*****************  Bit definition for FDCAN_TXBC register  *********************/
+#define FDCAN_TXBC_TBSA_Pos       (2U)
+#define FDCAN_TXBC_TBSA_Msk       (0x3FFFUL << FDCAN_TXBC_TBSA_Pos)            /*!< 0x0000FFFC */
+#define FDCAN_TXBC_TBSA           FDCAN_TXBC_TBSA_Msk                          /*!<Tx Buffers Start Address                  */
+#define FDCAN_TXBC_NDTB_Pos       (16U)
+#define FDCAN_TXBC_NDTB_Msk       (0x3FUL << FDCAN_TXBC_NDTB_Pos)              /*!< 0x003F0000 */
+#define FDCAN_TXBC_NDTB           FDCAN_TXBC_NDTB_Msk                          /*!<Number of Dedicated Transmit Buffers      */
+#define FDCAN_TXBC_TFQS_Pos       (24U)
+#define FDCAN_TXBC_TFQS_Msk       (0x3FUL << FDCAN_TXBC_TFQS_Pos)              /*!< 0x3F000000 */
+#define FDCAN_TXBC_TFQS           FDCAN_TXBC_TFQS_Msk                          /*!<Transmit FIFO/Queue Size                  */
+#define FDCAN_TXBC_TFQM_Pos       (30U)
+#define FDCAN_TXBC_TFQM_Msk       (0x1UL << FDCAN_TXBC_TFQM_Pos)               /*!< 0x40000000 */
+#define FDCAN_TXBC_TFQM           FDCAN_TXBC_TFQM_Msk                          /*!<Tx FIFO/Queue Mode                        */
+
+/*****************  Bit definition for FDCAN_TXFQS register  *********************/
+#define FDCAN_TXFQS_TFFL_Pos      (0U)
+#define FDCAN_TXFQS_TFFL_Msk      (0x3FUL << FDCAN_TXFQS_TFFL_Pos)             /*!< 0x0000003F */
+#define FDCAN_TXFQS_TFFL          FDCAN_TXFQS_TFFL_Msk                         /*!<Tx FIFO Free Level                        */
+#define FDCAN_TXFQS_TFGI_Pos      (8U)
+#define FDCAN_TXFQS_TFGI_Msk      (0x1FUL << FDCAN_TXFQS_TFGI_Pos)             /*!< 0x00001F00 */
+#define FDCAN_TXFQS_TFGI          FDCAN_TXFQS_TFGI_Msk                         /*!<Tx FIFO Get Index                         */
+#define FDCAN_TXFQS_TFQPI_Pos     (16U)
+#define FDCAN_TXFQS_TFQPI_Msk     (0x1FUL << FDCAN_TXFQS_TFQPI_Pos)            /*!< 0x001F0000 */
+#define FDCAN_TXFQS_TFQPI         FDCAN_TXFQS_TFQPI_Msk                        /*!<Tx FIFO/Queue Put Index                   */
+#define FDCAN_TXFQS_TFQF_Pos      (21U)
+#define FDCAN_TXFQS_TFQF_Msk      (0x1UL << FDCAN_TXFQS_TFQF_Pos)              /*!< 0x00200000 */
+#define FDCAN_TXFQS_TFQF          FDCAN_TXFQS_TFQF_Msk                         /*!<Tx FIFO/Queue Full                        */
+
+/*****************  Bit definition for FDCAN_TXESC register  *********************/
+#define FDCAN_TXESC_TBDS_Pos      (0U)
+#define FDCAN_TXESC_TBDS_Msk      (0x7UL << FDCAN_TXESC_TBDS_Pos)              /*!< 0x00000007 */
+#define FDCAN_TXESC_TBDS          FDCAN_TXESC_TBDS_Msk                         /*!<Tx Buffer Data Field Size                 */
+
+/*****************  Bit definition for FDCAN_TXBRP register  *********************/
+#define FDCAN_TXBRP_TRP_Pos       (0U)
+#define FDCAN_TXBRP_TRP_Msk       (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos)        /*!< 0xFFFFFFFF */
+#define FDCAN_TXBRP_TRP           FDCAN_TXBRP_TRP_Msk                          /*!<Transmission Request Pending              */
+
+/*****************  Bit definition for FDCAN_TXBAR register  *********************/
+#define FDCAN_TXBAR_AR_Pos        (0U)
+#define FDCAN_TXBAR_AR_Msk        (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos)         /*!< 0xFFFFFFFF */
+#define FDCAN_TXBAR_AR            FDCAN_TXBAR_AR_Msk                           /*!<Add Request                               */
+
+/*****************  Bit definition for FDCAN_TXBCR register  *********************/
+#define FDCAN_TXBCR_CR_Pos        (0U)
+#define FDCAN_TXBCR_CR_Msk        (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos)         /*!< 0xFFFFFFFF */
+#define FDCAN_TXBCR_CR            FDCAN_TXBCR_CR_Msk                           /*!<Cancellation Request                      */
+
+/*****************  Bit definition for FDCAN_TXBTO register  *********************/
+#define FDCAN_TXBTO_TO_Pos        (0U)
+#define FDCAN_TXBTO_TO_Msk        (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos)         /*!< 0xFFFFFFFF */
+#define FDCAN_TXBTO_TO            FDCAN_TXBTO_TO_Msk                           /*!<Transmission Occurred                     */
+
+/*****************  Bit definition for FDCAN_TXBCF register  *********************/
+#define FDCAN_TXBCF_CF_Pos        (0U)
+#define FDCAN_TXBCF_CF_Msk        (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos)         /*!< 0xFFFFFFFF */
+#define FDCAN_TXBCF_CF            FDCAN_TXBCF_CF_Msk                           /*!<Cancellation Finished                     */
+
+/*****************  Bit definition for FDCAN_TXBTIE register  ********************/
+#define FDCAN_TXBTIE_TIE_Pos      (0U)
+#define FDCAN_TXBTIE_TIE_Msk      (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos)       /*!< 0xFFFFFFFF */
+#define FDCAN_TXBTIE_TIE          FDCAN_TXBTIE_TIE_Msk                         /*!<Transmission Interrupt Enable             */
+
+/*****************  Bit definition for FDCAN_ TXBCIE register  *******************/
+#define FDCAN_TXBCIE_CFIE_Pos     (0U)
+#define FDCAN_TXBCIE_CFIE_Msk     (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos)      /*!< 0xFFFFFFFF */
+#define FDCAN_TXBCIE_CFIE         FDCAN_TXBCIE_CFIE_Msk                        /*!<Cancellation Finished Interrupt Enable    */
+
+/*****************  Bit definition for FDCAN_TXEFC register  *********************/
+#define FDCAN_TXEFC_EFSA_Pos      (2U)
+#define FDCAN_TXEFC_EFSA_Msk      (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos)           /*!< 0x0000FFFC */
+#define FDCAN_TXEFC_EFSA          FDCAN_TXEFC_EFSA_Msk                         /*!<Event FIFO Start Address                  */
+#define FDCAN_TXEFC_EFS_Pos       (16U)
+#define FDCAN_TXEFC_EFS_Msk       (0x3FUL << FDCAN_TXEFC_EFS_Pos)              /*!< 0x003F0000 */
+#define FDCAN_TXEFC_EFS           FDCAN_TXEFC_EFS_Msk                          /*!<Event FIFO Size                           */
+#define FDCAN_TXEFC_EFWM_Pos      (24U)
+#define FDCAN_TXEFC_EFWM_Msk      (0x3FUL << FDCAN_TXEFC_EFWM_Pos)             /*!< 0x3F000000 */
+#define FDCAN_TXEFC_EFWM          FDCAN_TXEFC_EFWM_Msk                         /*!<Event FIFO Watermark                      */
+
+/*****************  Bit definition for FDCAN_TXEFS register  *********************/
+#define FDCAN_TXEFS_EFFL_Pos      (0U)
+#define FDCAN_TXEFS_EFFL_Msk      (0x3FUL << FDCAN_TXEFS_EFFL_Pos)             /*!< 0x0000003F */
+#define FDCAN_TXEFS_EFFL          FDCAN_TXEFS_EFFL_Msk                         /*!<Event FIFO Fill Level                     */
+#define FDCAN_TXEFS_EFGI_Pos      (8U)
+#define FDCAN_TXEFS_EFGI_Msk      (0x1FUL << FDCAN_TXEFS_EFGI_Pos)             /*!< 0x00001F00 */
+#define FDCAN_TXEFS_EFGI          FDCAN_TXEFS_EFGI_Msk                         /*!<Event FIFO Get Index                      */
+#define FDCAN_TXEFS_EFPI_Pos      (16U)
+#define FDCAN_TXEFS_EFPI_Msk      (0x1FUL << FDCAN_TXEFS_EFPI_Pos)             /*!< 0x001F0000 */
+#define FDCAN_TXEFS_EFPI          FDCAN_TXEFS_EFPI_Msk                         /*!<Event FIFO Put Index                      */
+#define FDCAN_TXEFS_EFF_Pos       (24U)
+#define FDCAN_TXEFS_EFF_Msk       (0x1UL << FDCAN_TXEFS_EFF_Pos)               /*!< 0x01000000 */
+#define FDCAN_TXEFS_EFF           FDCAN_TXEFS_EFF_Msk                          /*!<Event FIFO Full                           */
+#define FDCAN_TXEFS_TEFL_Pos      (25U)
+#define FDCAN_TXEFS_TEFL_Msk      (0x1UL << FDCAN_TXEFS_TEFL_Pos)              /*!< 0x02000000 */
+#define FDCAN_TXEFS_TEFL          FDCAN_TXEFS_TEFL_Msk                         /*!<Tx Event FIFO Element Lost                */
+
+/*****************  Bit definition for FDCAN_TXEFA register  *********************/
+#define FDCAN_TXEFA_EFAI_Pos      (0U)
+#define FDCAN_TXEFA_EFAI_Msk      (0x1FUL << FDCAN_TXEFA_EFAI_Pos)             /*!< 0x0000001F */
+#define FDCAN_TXEFA_EFAI          FDCAN_TXEFA_EFAI_Msk                         /*!<Event FIFO Acknowledge Index              */
+
+/*****************  Bit definition for FDCAN_TTTMC register  *********************/
+#define FDCAN_TTTMC_TMSA_Pos      (2U)
+#define FDCAN_TTTMC_TMSA_Msk      (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos)           /*!< 0x0000FFFC */
+#define FDCAN_TTTMC_TMSA          FDCAN_TTTMC_TMSA_Msk                         /*!<Trigger Memory Start Address              */
+#define FDCAN_TTTMC_TME_Pos       (16U)
+#define FDCAN_TTTMC_TME_Msk       (0x7FUL << FDCAN_TTTMC_TME_Pos)              /*!< 0x007F0000 */
+#define FDCAN_TTTMC_TME           FDCAN_TTTMC_TME_Msk                          /*!<Trigger Memory Elements                   */
+
+/*****************  Bit definition for FDCAN_TTRMC register  *********************/
+#define FDCAN_TTRMC_RID_Pos       (0U)
+#define FDCAN_TTRMC_RID_Msk       (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos)        /*!< 0x1FFFFFFF */
+#define FDCAN_TTRMC_RID           FDCAN_TTRMC_RID_Msk                          /*!<Reference Identifier                      */
+#define FDCAN_TTRMC_XTD_Pos       (30U)
+#define FDCAN_TTRMC_XTD_Msk       (0x1UL << FDCAN_TTRMC_XTD_Pos)               /*!< 0x40000000 */
+#define FDCAN_TTRMC_XTD           FDCAN_TTRMC_XTD_Msk                          /*!< Extended Identifier                      */
+#define FDCAN_TTRMC_RMPS_Pos      (31U)
+#define FDCAN_TTRMC_RMPS_Msk      (0x1UL << FDCAN_TTRMC_RMPS_Pos)              /*!< 0x80000000 */
+#define FDCAN_TTRMC_RMPS          FDCAN_TTRMC_RMPS_Msk                         /*!<Reference Message Payload Select          */
+
+/*****************  Bit definition for FDCAN_TTOCF register  *********************/
+#define FDCAN_TTOCF_OM_Pos        (0U)
+#define FDCAN_TTOCF_OM_Msk        (0x3UL << FDCAN_TTOCF_OM_Pos)                /*!< 0x00000003 */
+#define FDCAN_TTOCF_OM            FDCAN_TTOCF_OM_Msk                           /*!<Operation Mode                            */
+#define FDCAN_TTOCF_GEN_Pos       (3U)
+#define FDCAN_TTOCF_GEN_Msk       (0x1UL << FDCAN_TTOCF_GEN_Pos)               /*!< 0x00000008 */
+#define FDCAN_TTOCF_GEN           FDCAN_TTOCF_GEN_Msk                          /*!<Gap Enable                                */
+#define FDCAN_TTOCF_TM_Pos        (4U)
+#define FDCAN_TTOCF_TM_Msk        (0x1UL << FDCAN_TTOCF_TM_Pos)                /*!< 0x00000010 */
+#define FDCAN_TTOCF_TM            FDCAN_TTOCF_TM_Msk                           /*!<Time Master                               */
+#define FDCAN_TTOCF_LDSDL_Pos     (5U)
+#define FDCAN_TTOCF_LDSDL_Msk     (0x7UL << FDCAN_TTOCF_LDSDL_Pos)             /*!< 0x000000E0 */
+#define FDCAN_TTOCF_LDSDL         FDCAN_TTOCF_LDSDL_Msk                        /*!<LD of Synchronization Deviation Limit     */
+#define FDCAN_TTOCF_IRTO_Pos      (8U)
+#define FDCAN_TTOCF_IRTO_Msk      (0x7FUL << FDCAN_TTOCF_IRTO_Pos)             /*!< 0x00007F00 */
+#define FDCAN_TTOCF_IRTO          FDCAN_TTOCF_IRTO_Msk                         /*!<Initial Reference Trigger Offset          */
+#define FDCAN_TTOCF_EECS_Pos      (15U)
+#define FDCAN_TTOCF_EECS_Msk      (0x1UL << FDCAN_TTOCF_EECS_Pos)              /*!< 0x00008000 */
+#define FDCAN_TTOCF_EECS          FDCAN_TTOCF_EECS_Msk                         /*!<Enable External Clock Synchronization     */
+#define FDCAN_TTOCF_AWL_Pos       (16U)
+#define FDCAN_TTOCF_AWL_Msk       (0xFFUL << FDCAN_TTOCF_AWL_Pos)              /*!< 0x00FF0000 */
+#define FDCAN_TTOCF_AWL           FDCAN_TTOCF_AWL_Msk                          /*!<Application Watchdog Limit                */
+#define FDCAN_TTOCF_EGTF_Pos      (24U)
+#define FDCAN_TTOCF_EGTF_Msk      (0x1UL << FDCAN_TTOCF_EGTF_Pos)              /*!< 0x01000000 */
+#define FDCAN_TTOCF_EGTF          FDCAN_TTOCF_EGTF_Msk                         /*!<Enable Global Time Filtering              */
+#define FDCAN_TTOCF_ECC_Pos       (25U)
+#define FDCAN_TTOCF_ECC_Msk       (0x1UL << FDCAN_TTOCF_ECC_Pos)               /*!< 0x02000000 */
+#define FDCAN_TTOCF_ECC           FDCAN_TTOCF_ECC_Msk                          /*!<Enable Clock Calibration                  */
+#define FDCAN_TTOCF_EVTP_Pos      (26U)
+#define FDCAN_TTOCF_EVTP_Msk      (0x1UL << FDCAN_TTOCF_EVTP_Pos)              /*!< 0x04000000 */
+#define FDCAN_TTOCF_EVTP          FDCAN_TTOCF_EVTP_Msk                         /*!<Event Trigger Polarity                    */
+
+/*****************  Bit definition for FDCAN_TTMLM register  *********************/
+#define FDCAN_TTMLM_CCM_Pos       (0U)
+#define FDCAN_TTMLM_CCM_Msk       (0x3FUL << FDCAN_TTMLM_CCM_Pos)              /*!< 0x0000003F */
+#define FDCAN_TTMLM_CCM           FDCAN_TTMLM_CCM_Msk                          /*!<Cycle Count Max                           */
+#define FDCAN_TTMLM_CSS_Pos       (6U)
+#define FDCAN_TTMLM_CSS_Msk       (0x3UL << FDCAN_TTMLM_CSS_Pos)               /*!< 0x000000C0 */
+#define FDCAN_TTMLM_CSS           FDCAN_TTMLM_CSS_Msk                          /*!<Cycle Start Synchronization               */
+#define FDCAN_TTMLM_TXEW_Pos      (8U)
+#define FDCAN_TTMLM_TXEW_Msk      (0xFUL << FDCAN_TTMLM_TXEW_Pos)              /*!< 0x00000F00 */
+#define FDCAN_TTMLM_TXEW          FDCAN_TTMLM_TXEW_Msk                         /*!<Tx Enable Window                          */
+#define FDCAN_TTMLM_ENTT_Pos      (16U)
+#define FDCAN_TTMLM_ENTT_Msk      (0xFFFUL << FDCAN_TTMLM_ENTT_Pos)            /*!< 0x0FFF0000 */
+#define FDCAN_TTMLM_ENTT          FDCAN_TTMLM_ENTT_Msk                         /*!<Expected Number of Tx Triggers            */
+
+/*****************  Bit definition for FDCAN_TURCF register  *********************/
+#define FDCAN_TURCF_NCL_Pos       (0U)
+#define FDCAN_TURCF_NCL_Msk       (0xFFFFUL << FDCAN_TURCF_NCL_Pos)            /*!< 0x0000FFFF */
+#define FDCAN_TURCF_NCL           FDCAN_TURCF_NCL_Msk                          /*!<Numerator Configuration Low               */
+#define FDCAN_TURCF_DC_Pos        (16U)
+#define FDCAN_TURCF_DC_Msk        (0x3FFFUL << FDCAN_TURCF_DC_Pos)             /*!< 0x3FFF0000 */
+#define FDCAN_TURCF_DC            FDCAN_TURCF_DC_Msk                           /*!<Denominator Configuration                 */
+#define FDCAN_TURCF_ELT_Pos       (31U)
+#define FDCAN_TURCF_ELT_Msk       (0x1UL << FDCAN_TURCF_ELT_Pos)               /*!< 0x80000000 */
+#define FDCAN_TURCF_ELT           FDCAN_TURCF_ELT_Msk                          /*!<Enable Local Time                         */
+
+/*****************  Bit definition for FDCAN_TTOCN register  ********************/
+#define FDCAN_TTOCN_SGT_Pos       (0U)
+#define FDCAN_TTOCN_SGT_Msk       (0x1UL << FDCAN_TTOCN_SGT_Pos)               /*!< 0x00000001 */
+#define FDCAN_TTOCN_SGT           FDCAN_TTOCN_SGT_Msk                          /*!<Set Global time                           */
+#define FDCAN_TTOCN_ECS_Pos       (1U)
+#define FDCAN_TTOCN_ECS_Msk       (0x1UL << FDCAN_TTOCN_ECS_Pos)               /*!< 0x00000002 */
+#define FDCAN_TTOCN_ECS           FDCAN_TTOCN_ECS_Msk                          /*!<External Clock Synchronization            */
+#define FDCAN_TTOCN_SWP_Pos       (2U)
+#define FDCAN_TTOCN_SWP_Msk       (0x1UL << FDCAN_TTOCN_SWP_Pos)               /*!< 0x00000004 */
+#define FDCAN_TTOCN_SWP           FDCAN_TTOCN_SWP_Msk                          /*!<Stop Watch Polarity                       */
+#define FDCAN_TTOCN_SWS_Pos       (3U)
+#define FDCAN_TTOCN_SWS_Msk       (0x3UL << FDCAN_TTOCN_SWS_Pos)               /*!< 0x00000018 */
+#define FDCAN_TTOCN_SWS           FDCAN_TTOCN_SWS_Msk                          /*!<Stop Watch Source                         */
+#define FDCAN_TTOCN_RTIE_Pos      (5U)
+#define FDCAN_TTOCN_RTIE_Msk      (0x1UL << FDCAN_TTOCN_RTIE_Pos)              /*!< 0x00000020 */
+#define FDCAN_TTOCN_RTIE          FDCAN_TTOCN_RTIE_Msk                         /*!<Register Time Mark Interrupt Pulse Enable */
+#define FDCAN_TTOCN_TMC_Pos       (6U)
+#define FDCAN_TTOCN_TMC_Msk       (0x3UL << FDCAN_TTOCN_TMC_Pos)               /*!< 0x000000C0 */
+#define FDCAN_TTOCN_TMC           FDCAN_TTOCN_TMC_Msk                          /*!<Register Time Mark Compare                */
+#define FDCAN_TTOCN_TTIE_Pos      (8U)
+#define FDCAN_TTOCN_TTIE_Msk      (0x1UL << FDCAN_TTOCN_TTIE_Pos)              /*!< 0x00000100 */
+#define FDCAN_TTOCN_TTIE          FDCAN_TTOCN_TTIE_Msk                         /*!<Trigger Time Mark Interrupt Pulse Enable  */
+#define FDCAN_TTOCN_GCS_Pos       (9U)
+#define FDCAN_TTOCN_GCS_Msk       (0x1UL << FDCAN_TTOCN_GCS_Pos)               /*!< 0x00000200 */
+#define FDCAN_TTOCN_GCS           FDCAN_TTOCN_GCS_Msk                          /*!<Gap Control Select                        */
+#define FDCAN_TTOCN_FGP_Pos       (10U)
+#define FDCAN_TTOCN_FGP_Msk       (0x1UL << FDCAN_TTOCN_FGP_Pos)               /*!< 0x00000400 */
+#define FDCAN_TTOCN_FGP           FDCAN_TTOCN_FGP_Msk                          /*!<Finish Gap                                */
+#define FDCAN_TTOCN_TMG_Pos       (11U)
+#define FDCAN_TTOCN_TMG_Msk       (0x1UL << FDCAN_TTOCN_TMG_Pos)               /*!< 0x00000800 */
+#define FDCAN_TTOCN_TMG           FDCAN_TTOCN_TMG_Msk                          /*!<Time Mark Gap                             */
+#define FDCAN_TTOCN_NIG_Pos       (12U)
+#define FDCAN_TTOCN_NIG_Msk       (0x1UL << FDCAN_TTOCN_NIG_Pos)               /*!< 0x00001000 */
+#define FDCAN_TTOCN_NIG           FDCAN_TTOCN_NIG_Msk                          /*!<Next is Gap                               */
+#define FDCAN_TTOCN_ESCN_Pos      (13U)
+#define FDCAN_TTOCN_ESCN_Msk      (0x1UL << FDCAN_TTOCN_ESCN_Pos)              /*!< 0x00002000 */
+#define FDCAN_TTOCN_ESCN          FDCAN_TTOCN_ESCN_Msk                         /*!<External Synchronization Control          */
+#define FDCAN_TTOCN_LCKC_Pos      (15U)
+#define FDCAN_TTOCN_LCKC_Msk      (0x1UL << FDCAN_TTOCN_LCKC_Pos)              /*!< 0x00008000 */
+#define FDCAN_TTOCN_LCKC          FDCAN_TTOCN_LCKC_Msk                         /*!<TT Operation Control Register Locked      */
+
+/*****************  Bit definition for FDCAN_TTGTP register  ********************/
+#define FDCAN_TTGTP_TP_Pos        (0U)
+#define FDCAN_TTGTP_TP_Msk        (0xFFFFUL << FDCAN_TTGTP_TP_Pos)             /*!< 0x0000FFFF */
+#define FDCAN_TTGTP_TP            FDCAN_TTGTP_TP_Msk                           /*!<Time Preset                               */
+#define FDCAN_TTGTP_CTP_Pos       (16U)
+#define FDCAN_TTGTP_CTP_Msk       (0xFFFFUL << FDCAN_TTGTP_CTP_Pos)            /*!< 0xFFFF0000 */
+#define FDCAN_TTGTP_CTP           FDCAN_TTGTP_CTP_Msk                          /*!<Cycle Time Target Phase                   */
+
+/*****************  Bit definition for FDCAN_TTTMK register  ********************/
+#define FDCAN_TTTMK_TM_Pos        (0U)
+#define FDCAN_TTTMK_TM_Msk        (0xFFFFUL << FDCAN_TTTMK_TM_Pos)             /*!< 0x0000FFFF */
+#define FDCAN_TTTMK_TM            FDCAN_TTTMK_TM_Msk                           /*!<Time Mark                                 */
+#define FDCAN_TTTMK_TICC_Pos      (16U)
+#define FDCAN_TTTMK_TICC_Msk      (0x7FUL << FDCAN_TTTMK_TICC_Pos)             /*!< 0x007F0000 */
+#define FDCAN_TTTMK_TICC          FDCAN_TTTMK_TICC_Msk                         /*!<Time Mark Cycle Code                      */
+#define FDCAN_TTTMK_LCKM_Pos      (31U)
+#define FDCAN_TTTMK_LCKM_Msk      (0x1UL << FDCAN_TTTMK_LCKM_Pos)              /*!< 0x80000000 */
+#define FDCAN_TTTMK_LCKM          FDCAN_TTTMK_LCKM_Msk                         /*!<TT Time Mark Register Locked              */
+
+/*****************  Bit definition for FDCAN_TTIR register  ********************/
+#define FDCAN_TTIR_SBC_Pos        (0U)
+#define FDCAN_TTIR_SBC_Msk        (0x1UL << FDCAN_TTIR_SBC_Pos)                /*!< 0x00000001 */
+#define FDCAN_TTIR_SBC            FDCAN_TTIR_SBC_Msk                           /*!<Start of Basic Cycle                      */
+#define FDCAN_TTIR_SMC_Pos        (1U)
+#define FDCAN_TTIR_SMC_Msk        (0x1UL << FDCAN_TTIR_SMC_Pos)                /*!< 0x00000002 */
+#define FDCAN_TTIR_SMC            FDCAN_TTIR_SMC_Msk                           /*!<Start of Matrix Cycle                     */
+#define FDCAN_TTIR_CSM_Pos        (2U)
+#define FDCAN_TTIR_CSM_Msk        (0x1UL << FDCAN_TTIR_CSM_Pos)                /*!< 0x00000004 */
+#define FDCAN_TTIR_CSM            FDCAN_TTIR_CSM_Msk                           /*!<Change of Synchronization Mode            */
+#define FDCAN_TTIR_SOG_Pos        (3U)
+#define FDCAN_TTIR_SOG_Msk        (0x1UL << FDCAN_TTIR_SOG_Pos)                /*!< 0x00000008 */
+#define FDCAN_TTIR_SOG            FDCAN_TTIR_SOG_Msk                           /*!<Start of Gap                              */
+#define FDCAN_TTIR_RTMI_Pos       (4U)
+#define FDCAN_TTIR_RTMI_Msk       (0x1UL << FDCAN_TTIR_RTMI_Pos)               /*!< 0x00000010 */
+#define FDCAN_TTIR_RTMI           FDCAN_TTIR_RTMI_Msk                          /*!<Register Time Mark Interrupt              */
+#define FDCAN_TTIR_TTMI_Pos       (5U)
+#define FDCAN_TTIR_TTMI_Msk       (0x1UL << FDCAN_TTIR_TTMI_Pos)               /*!< 0x00000020 */
+#define FDCAN_TTIR_TTMI           FDCAN_TTIR_TTMI_Msk                          /*!<Trigger Time Mark Event Internal          */
+#define FDCAN_TTIR_SWE_Pos        (6U)
+#define FDCAN_TTIR_SWE_Msk        (0x1UL << FDCAN_TTIR_SWE_Pos)                /*!< 0x00000040 */
+#define FDCAN_TTIR_SWE            FDCAN_TTIR_SWE_Msk                           /*!<Stop Watch Event                          */
+#define FDCAN_TTIR_GTW_Pos        (7U)
+#define FDCAN_TTIR_GTW_Msk        (0x1UL << FDCAN_TTIR_GTW_Pos)                /*!< 0x00000080 */
+#define FDCAN_TTIR_GTW            FDCAN_TTIR_GTW_Msk                           /*!<Global Time Wrap                          */
+#define FDCAN_TTIR_GTD_Pos        (8U)
+#define FDCAN_TTIR_GTD_Msk        (0x1UL << FDCAN_TTIR_GTD_Pos)                /*!< 0x00000100 */
+#define FDCAN_TTIR_GTD            FDCAN_TTIR_GTD_Msk                           /*!<Global Time Discontinuity                 */
+#define FDCAN_TTIR_GTE_Pos        (9U)
+#define FDCAN_TTIR_GTE_Msk        (0x1UL << FDCAN_TTIR_GTE_Pos)                /*!< 0x00000200 */
+#define FDCAN_TTIR_GTE            FDCAN_TTIR_GTE_Msk                           /*!<Global Time Error                         */
+#define FDCAN_TTIR_TXU_Pos        (10U)
+#define FDCAN_TTIR_TXU_Msk        (0x1UL << FDCAN_TTIR_TXU_Pos)                /*!< 0x00000400 */
+#define FDCAN_TTIR_TXU            FDCAN_TTIR_TXU_Msk                           /*!<Tx Count Underflow                        */
+#define FDCAN_TTIR_TXO_Pos        (11U)
+#define FDCAN_TTIR_TXO_Msk        (0x1UL << FDCAN_TTIR_TXO_Pos)                /*!< 0x00000800 */
+#define FDCAN_TTIR_TXO            FDCAN_TTIR_TXO_Msk                           /*!<Tx Count Overflow                         */
+#define FDCAN_TTIR_SE1_Pos        (12U)
+#define FDCAN_TTIR_SE1_Msk        (0x1UL << FDCAN_TTIR_SE1_Pos)                /*!< 0x00001000 */
+#define FDCAN_TTIR_SE1            FDCAN_TTIR_SE1_Msk                           /*!<Scheduling Error 1                        */
+#define FDCAN_TTIR_SE2_Pos        (13U)
+#define FDCAN_TTIR_SE2_Msk        (0x1UL << FDCAN_TTIR_SE2_Pos)                /*!< 0x00002000 */
+#define FDCAN_TTIR_SE2            FDCAN_TTIR_SE2_Msk                           /*!<Scheduling Error 2                        */
+#define FDCAN_TTIR_ELC_Pos        (14U)
+#define FDCAN_TTIR_ELC_Msk        (0x1UL << FDCAN_TTIR_ELC_Pos)                /*!< 0x00004000 */
+#define FDCAN_TTIR_ELC            FDCAN_TTIR_ELC_Msk                           /*!<Error Level Changed                       */
+#define FDCAN_TTIR_IWT_Pos        (15U)
+#define FDCAN_TTIR_IWT_Msk        (0x1UL << FDCAN_TTIR_IWT_Pos)                /*!< 0x00008000 */
+#define FDCAN_TTIR_IWT            FDCAN_TTIR_IWT_Msk                           /*!<Initialization Watch Trigger              */
+#define FDCAN_TTIR_WT_Pos         (16U)
+#define FDCAN_TTIR_WT_Msk         (0x1UL << FDCAN_TTIR_WT_Pos)                 /*!< 0x00010000 */
+#define FDCAN_TTIR_WT             FDCAN_TTIR_WT_Msk                            /*!<Watch Trigger                             */
+#define FDCAN_TTIR_AW_Pos         (17U)
+#define FDCAN_TTIR_AW_Msk         (0x1UL << FDCAN_TTIR_AW_Pos)                 /*!< 0x00020000 */
+#define FDCAN_TTIR_AW             FDCAN_TTIR_AW_Msk                            /*!<Application Watchdog                      */
+#define FDCAN_TTIR_CER_Pos        (18U)
+#define FDCAN_TTIR_CER_Msk        (0x1UL << FDCAN_TTIR_CER_Pos)                /*!< 0x00040000 */
+#define FDCAN_TTIR_CER            FDCAN_TTIR_CER_Msk                           /*!<Configuration Error                       */
+
+/*****************  Bit definition for FDCAN_TTIE register  ********************/
+#define FDCAN_TTIE_SBCE_Pos       (0U)
+#define FDCAN_TTIE_SBCE_Msk       (0x1UL << FDCAN_TTIE_SBCE_Pos)               /*!< 0x00000001 */
+#define FDCAN_TTIE_SBCE           FDCAN_TTIE_SBCE_Msk                          /*!<Start of Basic Cycle Interrupt Enable             */
+#define FDCAN_TTIE_SMCE_Pos       (1U)
+#define FDCAN_TTIE_SMCE_Msk       (0x1UL << FDCAN_TTIE_SMCE_Pos)               /*!< 0x00000002 */
+#define FDCAN_TTIE_SMCE           FDCAN_TTIE_SMCE_Msk                          /*!<Start of Matrix Cycle Interrupt Enable            */
+#define FDCAN_TTIE_CSME_Pos       (2U)
+#define FDCAN_TTIE_CSME_Msk       (0x1UL << FDCAN_TTIE_CSME_Pos)               /*!< 0x00000004 */
+#define FDCAN_TTIE_CSME           FDCAN_TTIE_CSME_Msk                          /*!<Change of Synchronization Mode Interrupt Enable   */
+#define FDCAN_TTIE_SOGE_Pos       (3U)
+#define FDCAN_TTIE_SOGE_Msk       (0x1UL << FDCAN_TTIE_SOGE_Pos)               /*!< 0x00000008 */
+#define FDCAN_TTIE_SOGE           FDCAN_TTIE_SOGE_Msk                          /*!<Start of Gap Interrupt Enable                     */
+#define FDCAN_TTIE_RTMIE_Pos      (4U)
+#define FDCAN_TTIE_RTMIE_Msk      (0x1UL << FDCAN_TTIE_RTMIE_Pos)              /*!< 0x00000010 */
+#define FDCAN_TTIE_RTMIE          FDCAN_TTIE_RTMIE_Msk                         /*!<Register Time Mark Interrupt Interrupt Enable     */
+#define FDCAN_TTIE_TTMIE_Pos      (5U)
+#define FDCAN_TTIE_TTMIE_Msk      (0x1UL << FDCAN_TTIE_TTMIE_Pos)              /*!< 0x00000020 */
+#define FDCAN_TTIE_TTMIE          FDCAN_TTIE_TTMIE_Msk                         /*!<Trigger Time Mark Event Internal Interrupt Enable */
+#define FDCAN_TTIE_SWEE_Pos       (6U)
+#define FDCAN_TTIE_SWEE_Msk       (0x1UL << FDCAN_TTIE_SWEE_Pos)               /*!< 0x00000040 */
+#define FDCAN_TTIE_SWEE           FDCAN_TTIE_SWEE_Msk                          /*!<Stop Watch Event Interrupt Enable                 */
+#define FDCAN_TTIE_GTWE_Pos       (7U)
+#define FDCAN_TTIE_GTWE_Msk       (0x1UL << FDCAN_TTIE_GTWE_Pos)               /*!< 0x00000080 */
+#define FDCAN_TTIE_GTWE           FDCAN_TTIE_GTWE_Msk                          /*!<Global Time Wrap Interrupt Enable                 */
+#define FDCAN_TTIE_GTDE_Pos       (8U)
+#define FDCAN_TTIE_GTDE_Msk       (0x1UL << FDCAN_TTIE_GTDE_Pos)               /*!< 0x00000100 */
+#define FDCAN_TTIE_GTDE           FDCAN_TTIE_GTDE_Msk                          /*!<Global Time Discontinuity Interrupt Enable        */
+#define FDCAN_TTIE_GTEE_Pos       (9U)
+#define FDCAN_TTIE_GTEE_Msk       (0x1UL << FDCAN_TTIE_GTEE_Pos)               /*!< 0x00000200 */
+#define FDCAN_TTIE_GTEE           FDCAN_TTIE_GTEE_Msk                          /*!<Global Time Error Interrupt Enable                */
+#define FDCAN_TTIE_TXUE_Pos       (10U)
+#define FDCAN_TTIE_TXUE_Msk       (0x1UL << FDCAN_TTIE_TXUE_Pos)               /*!< 0x00000400 */
+#define FDCAN_TTIE_TXUE           FDCAN_TTIE_TXUE_Msk                          /*!<Tx Count Underflow Interrupt Enable               */
+#define FDCAN_TTIE_TXOE_Pos       (11U)
+#define FDCAN_TTIE_TXOE_Msk       (0x1UL << FDCAN_TTIE_TXOE_Pos)               /*!< 0x00000800 */
+#define FDCAN_TTIE_TXOE           FDCAN_TTIE_TXOE_Msk                          /*!<Tx Count Overflow Interrupt Enable                */
+#define FDCAN_TTIE_SE1E_Pos       (12U)
+#define FDCAN_TTIE_SE1E_Msk       (0x1UL << FDCAN_TTIE_SE1E_Pos)               /*!< 0x00001000 */
+#define FDCAN_TTIE_SE1E           FDCAN_TTIE_SE1E_Msk                          /*!<Scheduling Error 1 Interrupt Enable               */
+#define FDCAN_TTIE_SE2E_Pos       (13U)
+#define FDCAN_TTIE_SE2E_Msk       (0x1UL << FDCAN_TTIE_SE2E_Pos)               /*!< 0x00002000 */
+#define FDCAN_TTIE_SE2E           FDCAN_TTIE_SE2E_Msk                          /*!<Scheduling Error 2 Interrupt Enable               */
+#define FDCAN_TTIE_ELCE_Pos       (14U)
+#define FDCAN_TTIE_ELCE_Msk       (0x1UL << FDCAN_TTIE_ELCE_Pos)               /*!< 0x00004000 */
+#define FDCAN_TTIE_ELCE           FDCAN_TTIE_ELCE_Msk                          /*!<Error Level Changed Interrupt Enable              */
+#define FDCAN_TTIE_IWTE_Pos       (15U)
+#define FDCAN_TTIE_IWTE_Msk       (0x1UL << FDCAN_TTIE_IWTE_Pos)               /*!< 0x00008000 */
+#define FDCAN_TTIE_IWTE           FDCAN_TTIE_IWTE_Msk                          /*!<Initialization Watch Trigger Interrupt Enable     */
+#define FDCAN_TTIE_WTE_Pos        (16U)
+#define FDCAN_TTIE_WTE_Msk        (0x1UL << FDCAN_TTIE_WTE_Pos)                /*!< 0x00010000 */
+#define FDCAN_TTIE_WTE            FDCAN_TTIE_WTE_Msk                           /*!<Watch Trigger Interrupt Enable                    */
+#define FDCAN_TTIE_AWE_Pos        (17U)
+#define FDCAN_TTIE_AWE_Msk        (0x1UL << FDCAN_TTIE_AWE_Pos)                /*!< 0x00020000 */
+#define FDCAN_TTIE_AWE            FDCAN_TTIE_AWE_Msk                           /*!<Application Watchdog Interrupt Enable             */
+#define FDCAN_TTIE_CERE_Pos       (18U)
+#define FDCAN_TTIE_CERE_Msk       (0x1UL << FDCAN_TTIE_CERE_Pos)               /*!< 0x00040000 */
+#define FDCAN_TTIE_CERE           FDCAN_TTIE_CERE_Msk                          /*!<Configuration Error Interrupt Enable              */
+
+/*****************  Bit definition for FDCAN_TTILS register  ********************/
+#define FDCAN_TTILS_SBCS_Pos      (0U)
+#define FDCAN_TTILS_SBCS_Msk      (0x1UL << FDCAN_TTILS_SBCS_Pos)              /*!< 0x00000001 */
+#define FDCAN_TTILS_SBCS          FDCAN_TTILS_SBCS_Msk                         /*!<Start of Basic Cycle Interrupt Line               */
+#define FDCAN_TTILS_SMCS_Pos      (1U)
+#define FDCAN_TTILS_SMCS_Msk      (0x1UL << FDCAN_TTILS_SMCS_Pos)              /*!< 0x00000002 */
+#define FDCAN_TTILS_SMCS          FDCAN_TTILS_SMCS_Msk                         /*!<Start of Matrix Cycle Interrupt Line              */
+#define FDCAN_TTILS_CSMS_Pos      (2U)
+#define FDCAN_TTILS_CSMS_Msk      (0x1UL << FDCAN_TTILS_CSMS_Pos)              /*!< 0x00000004 */
+#define FDCAN_TTILS_CSMS          FDCAN_TTILS_CSMS_Msk                         /*!<Change of Synchronization Mode Interrupt Line     */
+#define FDCAN_TTILS_SOGS_Pos      (3U)
+#define FDCAN_TTILS_SOGS_Msk      (0x1UL << FDCAN_TTILS_SOGS_Pos)              /*!< 0x00000008 */
+#define FDCAN_TTILS_SOGS          FDCAN_TTILS_SOGS_Msk                         /*!<Start of Gap Interrupt Line                       */
+#define FDCAN_TTILS_RTMIS_Pos     (4U)
+#define FDCAN_TTILS_RTMIS_Msk     (0x1UL << FDCAN_TTILS_RTMIS_Pos)             /*!< 0x00000010 */
+#define FDCAN_TTILS_RTMIS         FDCAN_TTILS_RTMIS_Msk                        /*!<Register Time Mark Interrupt Interrupt Line       */
+#define FDCAN_TTILS_TTMIS_Pos     (5U)
+#define FDCAN_TTILS_TTMIS_Msk     (0x1UL << FDCAN_TTILS_TTMIS_Pos)             /*!< 0x00000020 */
+#define FDCAN_TTILS_TTMIS         FDCAN_TTILS_TTMIS_Msk                        /*!<Trigger Time Mark Event Internal Interrupt Line   */
+#define FDCAN_TTILS_SWES_Pos      (6U)
+#define FDCAN_TTILS_SWES_Msk      (0x1UL << FDCAN_TTILS_SWES_Pos)              /*!< 0x00000040 */
+#define FDCAN_TTILS_SWES          FDCAN_TTILS_SWES_Msk                         /*!<Stop Watch Event Interrupt Line                   */
+#define FDCAN_TTILS_GTWS_Pos      (7U)
+#define FDCAN_TTILS_GTWS_Msk      (0x1UL << FDCAN_TTILS_GTWS_Pos)              /*!< 0x00000080 */
+#define FDCAN_TTILS_GTWS          FDCAN_TTILS_GTWS_Msk                         /*!<Global Time Wrap Interrupt Line                   */
+#define FDCAN_TTILS_GTDS_Pos      (8U)
+#define FDCAN_TTILS_GTDS_Msk      (0x1UL << FDCAN_TTILS_GTDS_Pos)              /*!< 0x00000100 */
+#define FDCAN_TTILS_GTDS          FDCAN_TTILS_GTDS_Msk                         /*!<Global Time Discontinuity Interrupt Line          */
+#define FDCAN_TTILS_GTES_Pos      (9U)
+#define FDCAN_TTILS_GTES_Msk      (0x1UL << FDCAN_TTILS_GTES_Pos)              /*!< 0x00000200 */
+#define FDCAN_TTILS_GTES          FDCAN_TTILS_GTES_Msk                         /*!<Global Time Error Interrupt Line                  */
+#define FDCAN_TTILS_TXUS_Pos      (10U)
+#define FDCAN_TTILS_TXUS_Msk      (0x1UL << FDCAN_TTILS_TXUS_Pos)              /*!< 0x00000400 */
+#define FDCAN_TTILS_TXUS          FDCAN_TTILS_TXUS_Msk                         /*!<Tx Count Underflow Interrupt Line                 */
+#define FDCAN_TTILS_TXOS_Pos      (11U)
+#define FDCAN_TTILS_TXOS_Msk      (0x1UL << FDCAN_TTILS_TXOS_Pos)              /*!< 0x00000800 */
+#define FDCAN_TTILS_TXOS          FDCAN_TTILS_TXOS_Msk                         /*!<Tx Count Overflow Interrupt Line                  */
+#define FDCAN_TTILS_SE1S_Pos      (12U)
+#define FDCAN_TTILS_SE1S_Msk      (0x1UL << FDCAN_TTILS_SE1S_Pos)              /*!< 0x00001000 */
+#define FDCAN_TTILS_SE1S          FDCAN_TTILS_SE1S_Msk                         /*!<Scheduling Error 1 Interrupt Line                 */
+#define FDCAN_TTILS_SE2S_Pos      (13U)
+#define FDCAN_TTILS_SE2S_Msk      (0x1UL << FDCAN_TTILS_SE2S_Pos)              /*!< 0x00002000 */
+#define FDCAN_TTILS_SE2S          FDCAN_TTILS_SE2S_Msk                         /*!<Scheduling Error 2 Interrupt Line                 */
+#define FDCAN_TTILS_ELCS_Pos      (14U)
+#define FDCAN_TTILS_ELCS_Msk      (0x1UL << FDCAN_TTILS_ELCS_Pos)              /*!< 0x00004000 */
+#define FDCAN_TTILS_ELCS          FDCAN_TTILS_ELCS_Msk                         /*!<Error Level Changed Interrupt Line                */
+#define FDCAN_TTILS_IWTS_Pos      (15U)
+#define FDCAN_TTILS_IWTS_Msk      (0x1UL << FDCAN_TTILS_IWTS_Pos)              /*!< 0x00008000 */
+#define FDCAN_TTILS_IWTS          FDCAN_TTILS_IWTS_Msk                         /*!<Initialization Watch Trigger Interrupt Line       */
+#define FDCAN_TTILS_WTS_Pos       (16U)
+#define FDCAN_TTILS_WTS_Msk       (0x1UL << FDCAN_TTILS_WTS_Pos)               /*!< 0x00010000 */
+#define FDCAN_TTILS_WTS           FDCAN_TTILS_WTS_Msk                          /*!<Watch Trigger Interrupt Line                      */
+#define FDCAN_TTILS_AWS_Pos       (17U)
+#define FDCAN_TTILS_AWS_Msk       (0x1UL << FDCAN_TTILS_AWS_Pos)               /*!< 0x00020000 */
+#define FDCAN_TTILS_AWS           FDCAN_TTILS_AWS_Msk                          /*!<Application Watchdog Interrupt Line               */
+#define FDCAN_TTILS_CERS_Pos      (18U)
+#define FDCAN_TTILS_CERS_Msk      (0x1UL << FDCAN_TTILS_CERS_Pos)              /*!< 0x00040000 */
+#define FDCAN_TTILS_CERS          FDCAN_TTILS_CERS_Msk                         /*!<Configuration Error Interrupt Line                */
+
+/*****************  Bit definition for FDCAN_TTOST register  ********************/
+#define FDCAN_TTOST_EL_Pos        (0U)
+#define FDCAN_TTOST_EL_Msk        (0x3UL << FDCAN_TTOST_EL_Pos)                /*!< 0x00000003 */
+#define FDCAN_TTOST_EL            FDCAN_TTOST_EL_Msk                           /*!<Error Level                              */
+#define FDCAN_TTOST_MS_Pos        (2U)
+#define FDCAN_TTOST_MS_Msk        (0x3UL << FDCAN_TTOST_MS_Pos)                /*!< 0x0000000C */
+#define FDCAN_TTOST_MS            FDCAN_TTOST_MS_Msk                           /*!<Master State                             */
+#define FDCAN_TTOST_SYS_Pos       (4U)
+#define FDCAN_TTOST_SYS_Msk       (0x3UL << FDCAN_TTOST_SYS_Pos)               /*!< 0x00000030 */
+#define FDCAN_TTOST_SYS           FDCAN_TTOST_SYS_Msk                          /*!<Synchronization State                    */
+#define FDCAN_TTOST_QGTP_Pos      (6U)
+#define FDCAN_TTOST_QGTP_Msk      (0x1UL << FDCAN_TTOST_QGTP_Pos)              /*!< 0x00000040 */
+#define FDCAN_TTOST_QGTP          FDCAN_TTOST_QGTP_Msk                         /*!<Quality of Global Time Phase             */
+#define FDCAN_TTOST_QCS_Pos       (7U)
+#define FDCAN_TTOST_QCS_Msk       (0x1UL << FDCAN_TTOST_QCS_Pos)               /*!< 0x00000080 */
+#define FDCAN_TTOST_QCS           FDCAN_TTOST_QCS_Msk                          /*!<Quality of Clock Speed                   */
+#define FDCAN_TTOST_RTO_Pos       (8U)
+#define FDCAN_TTOST_RTO_Msk       (0xFFUL << FDCAN_TTOST_RTO_Pos)              /*!< 0x0000FF00 */
+#define FDCAN_TTOST_RTO           FDCAN_TTOST_RTO_Msk                          /*!<Reference Trigger Offset                 */
+#define FDCAN_TTOST_WGTD_Pos      (22U)
+#define FDCAN_TTOST_WGTD_Msk      (0x1UL << FDCAN_TTOST_WGTD_Pos)              /*!< 0x00400000 */
+#define FDCAN_TTOST_WGTD          FDCAN_TTOST_WGTD_Msk                         /*!<Wait for Global Time Discontinuity       */
+#define FDCAN_TTOST_GFI_Pos       (23U)
+#define FDCAN_TTOST_GFI_Msk       (0x1UL << FDCAN_TTOST_GFI_Pos)               /*!< 0x00800000 */
+#define FDCAN_TTOST_GFI           FDCAN_TTOST_GFI_Msk                          /*!<Gap Finished Indicator                   */
+#define FDCAN_TTOST_TMP_Pos       (24U)
+#define FDCAN_TTOST_TMP_Msk       (0x7UL << FDCAN_TTOST_TMP_Pos)               /*!< 0x07000000 */
+#define FDCAN_TTOST_TMP           FDCAN_TTOST_TMP_Msk                          /*!<Time Master Priority                     */
+#define FDCAN_TTOST_GSI_Pos       (27U)
+#define FDCAN_TTOST_GSI_Msk       (0x1UL << FDCAN_TTOST_GSI_Pos)               /*!< 0x08000000 */
+#define FDCAN_TTOST_GSI           FDCAN_TTOST_GSI_Msk                          /*!<Gap Started Indicator                    */
+#define FDCAN_TTOST_WFE_Pos       (28U)
+#define FDCAN_TTOST_WFE_Msk       (0x1UL << FDCAN_TTOST_WFE_Pos)               /*!< 0x10000000 */
+#define FDCAN_TTOST_WFE           FDCAN_TTOST_WFE_Msk                          /*!<Wait for Event                           */
+#define FDCAN_TTOST_AWE_Pos       (29U)
+#define FDCAN_TTOST_AWE_Msk       (0x1UL << FDCAN_TTOST_AWE_Pos)               /*!< 0x20000000 */
+#define FDCAN_TTOST_AWE           FDCAN_TTOST_AWE_Msk                          /*!<Application Watchdog Event               */
+#define FDCAN_TTOST_WECS_Pos      (30U)
+#define FDCAN_TTOST_WECS_Msk      (0x1UL << FDCAN_TTOST_WECS_Pos)              /*!< 0x40000000 */
+#define FDCAN_TTOST_WECS          FDCAN_TTOST_WECS_Msk                         /*!<Wait for External Clock Synchronization  */
+#define FDCAN_TTOST_SPL_Pos       (31U)
+#define FDCAN_TTOST_SPL_Msk       (0x1UL << FDCAN_TTOST_SPL_Pos)               /*!< 0x80000000 */
+#define FDCAN_TTOST_SPL           FDCAN_TTOST_SPL_Msk                          /*!<Schedule Phase Lock                      */
+
+/*****************  Bit definition for FDCAN_TURNA register  ********************/
+#define FDCAN_TURNA_NAV_Pos       (0U)
+#define FDCAN_TURNA_NAV_Msk       (0x3FFFFUL << FDCAN_TURNA_NAV_Pos)           /*!< 0x0003FFFF */
+#define FDCAN_TURNA_NAV           FDCAN_TURNA_NAV_Msk                          /*!<Numerator Actual Value                   */
+
+/*****************  Bit definition for FDCAN_TTLGT register  ********************/
+#define FDCAN_TTLGT_LT_Pos        (0U)
+#define FDCAN_TTLGT_LT_Msk        (0xFFFFUL << FDCAN_TTLGT_LT_Pos)             /*!< 0x0000FFFF */
+#define FDCAN_TTLGT_LT            FDCAN_TTLGT_LT_Msk                           /*!<Local Time                               */
+#define FDCAN_TTLGT_GT_Pos        (16U)
+#define FDCAN_TTLGT_GT_Msk        (0xFFFFUL << FDCAN_TTLGT_GT_Pos)             /*!< 0xFFFF0000 */
+#define FDCAN_TTLGT_GT            FDCAN_TTLGT_GT_Msk                           /*!<Global Time                              */
+
+/*****************  Bit definition for FDCAN_TTCTC register  ********************/
+#define FDCAN_TTCTC_CT_Pos        (0U)
+#define FDCAN_TTCTC_CT_Msk        (0xFFFFUL << FDCAN_TTCTC_CT_Pos)             /*!< 0x0000FFFF */
+#define FDCAN_TTCTC_CT            FDCAN_TTCTC_CT_Msk                           /*!<Cycle Time                               */
+#define FDCAN_TTCTC_CC_Pos        (16U)
+#define FDCAN_TTCTC_CC_Msk        (0x3FUL << FDCAN_TTCTC_CC_Pos)               /*!< 0x003F0000 */
+#define FDCAN_TTCTC_CC            FDCAN_TTCTC_CC_Msk                           /*!<Cycle Count                              */
+
+/*****************  Bit definition for FDCAN_TTCPT register  ********************/
+#define FDCAN_TTCPT_CCV_Pos       (0U)
+#define FDCAN_TTCPT_CCV_Msk       (0x3FUL << FDCAN_TTCPT_CCV_Pos)              /*!< 0x0000003F */
+#define FDCAN_TTCPT_CCV           FDCAN_TTCPT_CCV_Msk                          /*!<Cycle Count Value                        */
+#define FDCAN_TTCPT_SWV_Pos       (16U)
+#define FDCAN_TTCPT_SWV_Msk       (0xFFFFUL << FDCAN_TTCPT_SWV_Pos)            /*!< 0xFFFF0000 */
+#define FDCAN_TTCPT_SWV           FDCAN_TTCPT_SWV_Msk                          /*!<Stop Watch Value                         */
+
+/*****************  Bit definition for FDCAN_TTCSM register  ********************/
+#define FDCAN_TTCSM_CSM_Pos       (0U)
+#define FDCAN_TTCSM_CSM_Msk       (0xFFFFUL << FDCAN_TTCSM_CSM_Pos)            /*!< 0x0000FFFF */
+#define FDCAN_TTCSM_CSM           FDCAN_TTCSM_CSM_Msk                          /*!<Cycle Sync Mark                          */
+
+/*****************  Bit definition for FDCAN_TTTS register  *********************/
+#define FDCAN_TTTS_SWTSEL_Pos     (0U)
+#define FDCAN_TTTS_SWTSEL_Msk     (0x3UL << FDCAN_TTTS_SWTSEL_Pos)             /*!< 0x00000003 */
+#define FDCAN_TTTS_SWTSEL         FDCAN_TTTS_SWTSEL_Msk                        /*!<Stop watch trigger input selection       */
+#define FDCAN_TTTS_EVTSEL_Pos     (4U)
+#define FDCAN_TTTS_EVTSEL_Msk     (0x3UL << FDCAN_TTTS_EVTSEL_Pos)             /*!< 0x00000030 */
+#define FDCAN_TTTS_EVTSEL         FDCAN_TTTS_EVTSEL_Msk                        /*!<Event trigger input selection            */
+
+/********************************************************************************/
+/*                                                                              */
+/*                      FDCANCCU (Clock Calibration unit)                       */
+/*                                                                              */
+/********************************************************************************/
+
+/*****************  Bit definition for FDCANCCU_CREL register  ******************/
+#define FDCANCCU_CREL_DAY_Pos        (0U)
+#define FDCANCCU_CREL_DAY_Msk        (0xFFUL << FDCANCCU_CREL_DAY_Pos)         /*!< 0x000000FF */
+#define FDCANCCU_CREL_DAY            FDCANCCU_CREL_DAY_Msk                     /*!<Timestamp Day                           */
+#define FDCANCCU_CREL_MON_Pos        (8U)
+#define FDCANCCU_CREL_MON_Msk        (0xFFUL << FDCANCCU_CREL_MON_Pos)         /*!< 0x0000FF00 */
+#define FDCANCCU_CREL_MON            FDCANCCU_CREL_MON_Msk                     /*!<Timestamp Month                         */
+#define FDCANCCU_CREL_YEAR_Pos       (16U)
+#define FDCANCCU_CREL_YEAR_Msk       (0xFUL << FDCANCCU_CREL_YEAR_Pos)         /*!< 0x000F0000 */
+#define FDCANCCU_CREL_YEAR           FDCANCCU_CREL_YEAR_Msk                    /*!<Timestamp Year                          */
+#define FDCANCCU_CREL_SUBSTEP_Pos    (20U)
+#define FDCANCCU_CREL_SUBSTEP_Msk    (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos)      /*!< 0x00F00000 */
+#define FDCANCCU_CREL_SUBSTEP        FDCANCCU_CREL_SUBSTEP_Msk                 /*!<Sub-step of Core release                */
+#define FDCANCCU_CREL_STEP_Pos       (24U)
+#define FDCANCCU_CREL_STEP_Msk       (0xFUL << FDCANCCU_CREL_STEP_Pos)         /*!< 0x0F000000 */
+#define FDCANCCU_CREL_STEP           FDCANCCU_CREL_STEP_Msk                    /*!<Step of Core release                    */
+#define FDCANCCU_CREL_REL_Pos        (28U)
+#define FDCANCCU_CREL_REL_Msk        (0xFUL << FDCANCCU_CREL_REL_Pos)          /*!< 0xF0000000 */
+#define FDCANCCU_CREL_REL            FDCANCCU_CREL_REL_Msk                     /*!<Core release                            */
+
+/*****************  Bit definition for FDCANCCU_CCFG register  ******************/
+#define FDCANCCU_CCFG_TQBT_Pos       (0U)
+#define FDCANCCU_CCFG_TQBT_Msk       (0x1FUL << FDCANCCU_CCFG_TQBT_Pos)        /*!< 0x0000001F */
+#define FDCANCCU_CCFG_TQBT           FDCANCCU_CCFG_TQBT_Msk                    /*!<Time Quanta per Bit Time                */
+#define FDCANCCU_CCFG_BCC_Pos        (6U)
+#define FDCANCCU_CCFG_BCC_Msk        (0x1UL << FDCANCCU_CCFG_BCC_Pos)          /*!< 0x00000040 */
+#define FDCANCCU_CCFG_BCC            FDCANCCU_CCFG_BCC_Msk                     /*!<Bypass Clock Calibration                */
+#define FDCANCCU_CCFG_CFL_Pos        (7U)
+#define FDCANCCU_CCFG_CFL_Msk        (0x1UL << FDCANCCU_CCFG_CFL_Pos)          /*!< 0x00000080 */
+#define FDCANCCU_CCFG_CFL            FDCANCCU_CCFG_CFL_Msk                     /*!<Calibration Field Length                */
+#define FDCANCCU_CCFG_OCPM_Pos       (8U)
+#define FDCANCCU_CCFG_OCPM_Msk       (0xFFUL << FDCANCCU_CCFG_OCPM_Pos)        /*!< 0x0000FF00 */
+#define FDCANCCU_CCFG_OCPM           FDCANCCU_CCFG_OCPM_Msk                    /*!<Oscillator Clock Periods Minimum        */
+#define FDCANCCU_CCFG_CDIV_Pos       (16U)
+#define FDCANCCU_CCFG_CDIV_Msk       (0xFUL << FDCANCCU_CCFG_CDIV_Pos)         /*!< 0x000F0000 */
+#define FDCANCCU_CCFG_CDIV           FDCANCCU_CCFG_CDIV_Msk                    /*!<Clock Divider                           */
+#define FDCANCCU_CCFG_SWR_Pos        (31U)
+#define FDCANCCU_CCFG_SWR_Msk        (0x1UL << FDCANCCU_CCFG_SWR_Pos)          /*!< 0x80000000 */
+#define FDCANCCU_CCFG_SWR            FDCANCCU_CCFG_SWR_Msk                     /*!<Software Reset                          */
+
+/*****************  Bit definition for FDCANCCU_CSTAT register  *****************/
+#define FDCANCCU_CSTAT_OCPC_Pos      (0U)
+#define FDCANCCU_CSTAT_OCPC_Msk      (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos)    /*!< 0x0003FFFF */
+#define FDCANCCU_CSTAT_OCPC          FDCANCCU_CSTAT_OCPC_Msk                   /*!<Oscillator Clock Period Counter        */
+#define FDCANCCU_CSTAT_TQC_Pos       (18U)
+#define FDCANCCU_CSTAT_TQC_Msk       (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos)       /*!< 0x1FFC0000 */
+#define FDCANCCU_CSTAT_TQC           FDCANCCU_CSTAT_TQC_Msk                    /*!<Time Quanta Counter                    */
+#define FDCANCCU_CSTAT_CALS_Pos      (30U)
+#define FDCANCCU_CSTAT_CALS_Msk      (0x3UL << FDCANCCU_CSTAT_CALS_Pos)        /*!< 0xC0000000 */
+#define FDCANCCU_CSTAT_CALS          FDCANCCU_CSTAT_CALS_Msk                   /*!<Calibration State                      */
+
+/******************  Bit definition for FDCANCCU_CWD register  ******************/
+#define FDCANCCU_CWD_WDC_Pos         (0U)
+#define FDCANCCU_CWD_WDC_Msk         (0xFFFFUL << FDCANCCU_CWD_WDC_Pos)        /*!< 0x0000FFFF */
+#define FDCANCCU_CWD_WDC             FDCANCCU_CWD_WDC_Msk                      /*!<Watchdog Configuration                 */
+#define FDCANCCU_CWD_WDV_Pos         (16U)
+#define FDCANCCU_CWD_WDV_Msk         (0xFFFFUL << FDCANCCU_CWD_WDV_Pos)        /*!< 0xFFFF0000 */
+#define FDCANCCU_CWD_WDV             FDCANCCU_CWD_WDV_Msk                      /*!<Watchdog Value                         */
+
+/******************  Bit definition for FDCANCCU_IR register  *******************/
+#define FDCANCCU_IR_CWE_Pos          (0U)
+#define FDCANCCU_IR_CWE_Msk          (0x1UL << FDCANCCU_IR_CWE_Pos)            /*!< 0x00000001 */
+#define FDCANCCU_IR_CWE              FDCANCCU_IR_CWE_Msk                       /*!<Calibration Watchdog Event             */
+#define FDCANCCU_IR_CSC_Pos          (1U)
+#define FDCANCCU_IR_CSC_Msk          (0x1UL << FDCANCCU_IR_CSC_Pos)            /*!< 0x00000002 */
+#define FDCANCCU_IR_CSC              FDCANCCU_IR_CSC_Msk                       /*!<Calibration State Changed              */
+
+/******************  Bit definition for FDCANCCU_IE register  *******************/
+#define FDCANCCU_IE_CWEE_Pos         (0U)
+#define FDCANCCU_IE_CWEE_Msk         (0x1UL << FDCANCCU_IE_CWEE_Pos)           /*!< 0x00000001 */
+#define FDCANCCU_IE_CWEE             FDCANCCU_IE_CWEE_Msk                      /*!<Calibration Watchdog Event Enable      */
+#define FDCANCCU_IE_CSCE_Pos         (1U)
+#define FDCANCCU_IE_CSCE_Msk         (0x1UL << FDCANCCU_IE_CSCE_Pos)           /*!< 0x00000002 */
+#define FDCANCCU_IE_CSCE             FDCANCCU_IE_CSCE_Msk                      /*!<Calibration State Changed Enable       */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          HDMI-CEC (CEC)                                    */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for CEC_CR register  *********************/
+#define CEC_CR_CECEN_Pos         (0U)
+#define CEC_CR_CECEN_Msk         (0x1UL << CEC_CR_CECEN_Pos)                   /*!< 0x00000001 */
+#define CEC_CR_CECEN             CEC_CR_CECEN_Msk                              /*!< CEC Enable                                */
+#define CEC_CR_TXSOM_Pos         (1U)
+#define CEC_CR_TXSOM_Msk         (0x1UL << CEC_CR_TXSOM_Pos)                   /*!< 0x00000002 */
+#define CEC_CR_TXSOM             CEC_CR_TXSOM_Msk                              /*!< CEC Tx Start Of Message                   */
+#define CEC_CR_TXEOM_Pos         (2U)
+#define CEC_CR_TXEOM_Msk         (0x1UL << CEC_CR_TXEOM_Pos)                   /*!< 0x00000004 */
+#define CEC_CR_TXEOM             CEC_CR_TXEOM_Msk                              /*!< CEC Tx End Of Message                     */
+
+/*******************  Bit definition for CEC_CFGR register  *******************/
+#define CEC_CFGR_SFT_Pos         (0U)
+#define CEC_CFGR_SFT_Msk         (0x7UL << CEC_CFGR_SFT_Pos)                   /*!< 0x00000007 */
+#define CEC_CFGR_SFT             CEC_CFGR_SFT_Msk                              /*!< CEC Signal Free Time                      */
+#define CEC_CFGR_RXTOL_Pos       (3U)
+#define CEC_CFGR_RXTOL_Msk       (0x1UL << CEC_CFGR_RXTOL_Pos)                 /*!< 0x00000008 */
+#define CEC_CFGR_RXTOL           CEC_CFGR_RXTOL_Msk                            /*!< CEC Tolerance                             */
+#define CEC_CFGR_BRESTP_Pos      (4U)
+#define CEC_CFGR_BRESTP_Msk      (0x1UL << CEC_CFGR_BRESTP_Pos)                /*!< 0x00000010 */
+#define CEC_CFGR_BRESTP          CEC_CFGR_BRESTP_Msk                           /*!< CEC Rx Stop                               */
+#define CEC_CFGR_BREGEN_Pos      (5U)
+#define CEC_CFGR_BREGEN_Msk      (0x1UL << CEC_CFGR_BREGEN_Pos)                /*!< 0x00000020 */
+#define CEC_CFGR_BREGEN          CEC_CFGR_BREGEN_Msk                           /*!< CEC Bit Rising Error generation           */
+#define CEC_CFGR_LBPEGEN_Pos     (6U)
+#define CEC_CFGR_LBPEGEN_Msk     (0x1UL << CEC_CFGR_LBPEGEN_Pos)               /*!< 0x00000040 */
+#define CEC_CFGR_LBPEGEN         CEC_CFGR_LBPEGEN_Msk                          /*!< CEC Long Bit Period Error generation      */
+#define CEC_CFGR_SFTOPT_Pos      (8U)
+#define CEC_CFGR_SFTOPT_Msk      (0x1UL << CEC_CFGR_SFTOPT_Pos)                /*!< 0x00000100 */
+#define CEC_CFGR_SFTOPT          CEC_CFGR_SFTOPT_Msk                           /*!< CEC Signal Free Time optional             */
+#define CEC_CFGR_BRDNOGEN_Pos    (7U)
+#define CEC_CFGR_BRDNOGEN_Msk    (0x1UL << CEC_CFGR_BRDNOGEN_Pos)              /*!< 0x00000080 */
+#define CEC_CFGR_BRDNOGEN        CEC_CFGR_BRDNOGEN_Msk                         /*!< CEC Broadcast No error generation         */
+#define CEC_CFGR_OAR_Pos         (16U)
+#define CEC_CFGR_OAR_Msk         (0x7FFFUL << CEC_CFGR_OAR_Pos)                /*!< 0x7FFF0000 */
+#define CEC_CFGR_OAR             CEC_CFGR_OAR_Msk                              /*!< CEC Own Address                           */
+#define CEC_CFGR_LSTN_Pos        (31U)
+#define CEC_CFGR_LSTN_Msk        (0x1UL << CEC_CFGR_LSTN_Pos)                  /*!< 0x80000000 */
+#define CEC_CFGR_LSTN            CEC_CFGR_LSTN_Msk                             /*!< CEC Listen mode                           */
+
+/*******************  Bit definition for CEC_TXDR register  *******************/
+#define CEC_TXDR_TXD_Pos         (0U)
+#define CEC_TXDR_TXD_Msk         (0xFFUL << CEC_TXDR_TXD_Pos)                  /*!< 0x000000FF */
+#define CEC_TXDR_TXD             CEC_TXDR_TXD_Msk                              /*!< CEC Tx Data                               */
+
+/*******************  Bit definition for CEC_RXDR register  *******************/
+#define CEC_RXDR_RXD_Pos         (0U)
+#define CEC_RXDR_RXD_Msk         (0xFFUL << CEC_RXDR_RXD_Pos)                  /*!< 0x000000FF */
+#define CEC_RXDR_RXD             CEC_RXDR_RXD_Msk                              /*!< CEC Rx Data                               */
+
+/*******************  Bit definition for CEC_ISR register  ********************/
+#define CEC_ISR_RXBR_Pos         (0U)
+#define CEC_ISR_RXBR_Msk         (0x1UL << CEC_ISR_RXBR_Pos)                   /*!< 0x00000001 */
+#define CEC_ISR_RXBR             CEC_ISR_RXBR_Msk                              /*!< CEC Rx-Byte Received                      */
+#define CEC_ISR_RXEND_Pos        (1U)
+#define CEC_ISR_RXEND_Msk        (0x1UL << CEC_ISR_RXEND_Pos)                  /*!< 0x00000002 */
+#define CEC_ISR_RXEND            CEC_ISR_RXEND_Msk                             /*!< CEC End Of Reception                      */
+#define CEC_ISR_RXOVR_Pos        (2U)
+#define CEC_ISR_RXOVR_Msk        (0x1UL << CEC_ISR_RXOVR_Pos)                  /*!< 0x00000004 */
+#define CEC_ISR_RXOVR            CEC_ISR_RXOVR_Msk                             /*!< CEC Rx-Overrun                            */
+#define CEC_ISR_BRE_Pos          (3U)
+#define CEC_ISR_BRE_Msk          (0x1UL << CEC_ISR_BRE_Pos)                    /*!< 0x00000008 */
+#define CEC_ISR_BRE              CEC_ISR_BRE_Msk                               /*!< CEC Rx Bit Rising Error                   */
+#define CEC_ISR_SBPE_Pos         (4U)
+#define CEC_ISR_SBPE_Msk         (0x1UL << CEC_ISR_SBPE_Pos)                   /*!< 0x00000010 */
+#define CEC_ISR_SBPE             CEC_ISR_SBPE_Msk                              /*!< CEC Rx Short Bit period Error             */
+#define CEC_ISR_LBPE_Pos         (5U)
+#define CEC_ISR_LBPE_Msk         (0x1UL << CEC_ISR_LBPE_Pos)                   /*!< 0x00000020 */
+#define CEC_ISR_LBPE             CEC_ISR_LBPE_Msk                              /*!< CEC Rx Long Bit period Error              */
+#define CEC_ISR_RXACKE_Pos       (6U)
+#define CEC_ISR_RXACKE_Msk       (0x1UL << CEC_ISR_RXACKE_Pos)                 /*!< 0x00000040 */
+#define CEC_ISR_RXACKE           CEC_ISR_RXACKE_Msk                            /*!< CEC Rx Missing Acknowledge                */
+#define CEC_ISR_ARBLST_Pos       (7U)
+#define CEC_ISR_ARBLST_Msk       (0x1UL << CEC_ISR_ARBLST_Pos)                 /*!< 0x00000080 */
+#define CEC_ISR_ARBLST           CEC_ISR_ARBLST_Msk                            /*!< CEC Arbitration Lost                      */
+#define CEC_ISR_TXBR_Pos         (8U)
+#define CEC_ISR_TXBR_Msk         (0x1UL << CEC_ISR_TXBR_Pos)                   /*!< 0x00000100 */
+#define CEC_ISR_TXBR             CEC_ISR_TXBR_Msk                              /*!< CEC Tx Byte Request                       */
+#define CEC_ISR_TXEND_Pos        (9U)
+#define CEC_ISR_TXEND_Msk        (0x1UL << CEC_ISR_TXEND_Pos)                  /*!< 0x00000200 */
+#define CEC_ISR_TXEND            CEC_ISR_TXEND_Msk                             /*!< CEC End of Transmission                   */
+#define CEC_ISR_TXUDR_Pos        (10U)
+#define CEC_ISR_TXUDR_Msk        (0x1UL << CEC_ISR_TXUDR_Pos)                  /*!< 0x00000400 */
+#define CEC_ISR_TXUDR            CEC_ISR_TXUDR_Msk                             /*!< CEC Tx-Buffer Underrun                    */
+#define CEC_ISR_TXERR_Pos        (11U)
+#define CEC_ISR_TXERR_Msk        (0x1UL << CEC_ISR_TXERR_Pos)                  /*!< 0x00000800 */
+#define CEC_ISR_TXERR            CEC_ISR_TXERR_Msk                             /*!< CEC Tx-Error                              */
+#define CEC_ISR_TXACKE_Pos       (12U)
+#define CEC_ISR_TXACKE_Msk       (0x1UL << CEC_ISR_TXACKE_Pos)                 /*!< 0x00001000 */
+#define CEC_ISR_TXACKE           CEC_ISR_TXACKE_Msk                            /*!< CEC Tx Missing Acknowledge                */
+
+/*******************  Bit definition for CEC_IER register  ********************/
+#define CEC_IER_RXBRIE_Pos       (0U)
+#define CEC_IER_RXBRIE_Msk       (0x1UL << CEC_IER_RXBRIE_Pos)                 /*!< 0x00000001 */
+#define CEC_IER_RXBRIE           CEC_IER_RXBRIE_Msk                            /*!< CEC Rx-Byte Received IT Enable            */
+#define CEC_IER_RXENDIE_Pos      (1U)
+#define CEC_IER_RXENDIE_Msk      (0x1UL << CEC_IER_RXENDIE_Pos)                /*!< 0x00000002 */
+#define CEC_IER_RXENDIE          CEC_IER_RXENDIE_Msk                           /*!< CEC End Of Reception IT Enable            */
+#define CEC_IER_RXOVRIE_Pos      (2U)
+#define CEC_IER_RXOVRIE_Msk      (0x1UL << CEC_IER_RXOVRIE_Pos)                /*!< 0x00000004 */
+#define CEC_IER_RXOVRIE          CEC_IER_RXOVRIE_Msk                           /*!< CEC Rx-Overrun IT Enable                  */
+#define CEC_IER_BREIE_Pos        (3U)
+#define CEC_IER_BREIE_Msk        (0x1UL << CEC_IER_BREIE_Pos)                  /*!< 0x00000008 */
+#define CEC_IER_BREIE            CEC_IER_BREIE_Msk                             /*!< CEC Rx Bit Rising Error IT Enable         */
+#define CEC_IER_SBPEIE_Pos       (4U)
+#define CEC_IER_SBPEIE_Msk       (0x1UL << CEC_IER_SBPEIE_Pos)                 /*!< 0x00000010 */
+#define CEC_IER_SBPEIE           CEC_IER_SBPEIE_Msk                            /*!< CEC Rx Short Bit period Error IT Enable   */
+#define CEC_IER_LBPEIE_Pos       (5U)
+#define CEC_IER_LBPEIE_Msk       (0x1UL << CEC_IER_LBPEIE_Pos)                 /*!< 0x00000020 */
+#define CEC_IER_LBPEIE           CEC_IER_LBPEIE_Msk                            /*!< CEC Rx Long Bit period Error IT Enable    */
+#define CEC_IER_RXACKEIE_Pos     (6U)
+#define CEC_IER_RXACKEIE_Msk     (0x1UL << CEC_IER_RXACKEIE_Pos)               /*!< 0x00000040 */
+#define CEC_IER_RXACKEIE         CEC_IER_RXACKEIE_Msk                          /*!< CEC Rx Missing Acknowledge IT Enable      */
+#define CEC_IER_ARBLSTIE_Pos     (7U)
+#define CEC_IER_ARBLSTIE_Msk     (0x1UL << CEC_IER_ARBLSTIE_Pos)               /*!< 0x00000080 */
+#define CEC_IER_ARBLSTIE         CEC_IER_ARBLSTIE_Msk                          /*!< CEC Arbitration Lost IT Enable            */
+#define CEC_IER_TXBRIE_Pos       (8U)
+#define CEC_IER_TXBRIE_Msk       (0x1UL << CEC_IER_TXBRIE_Pos)                 /*!< 0x00000100 */
+#define CEC_IER_TXBRIE           CEC_IER_TXBRIE_Msk                            /*!< CEC Tx Byte Request  IT Enable            */
+#define CEC_IER_TXENDIE_Pos      (9U)
+#define CEC_IER_TXENDIE_Msk      (0x1UL << CEC_IER_TXENDIE_Pos)                /*!< 0x00000200 */
+#define CEC_IER_TXENDIE          CEC_IER_TXENDIE_Msk                           /*!< CEC End of Transmission IT Enable         */
+#define CEC_IER_TXUDRIE_Pos      (10U)
+#define CEC_IER_TXUDRIE_Msk      (0x1UL << CEC_IER_TXUDRIE_Pos)                /*!< 0x00000400 */
+#define CEC_IER_TXUDRIE          CEC_IER_TXUDRIE_Msk                           /*!< CEC Tx-Buffer Underrun IT Enable          */
+#define CEC_IER_TXERRIE_Pos      (11U)
+#define CEC_IER_TXERRIE_Msk      (0x1UL << CEC_IER_TXERRIE_Pos)                /*!< 0x00000800 */
+#define CEC_IER_TXERRIE          CEC_IER_TXERRIE_Msk                           /*!< CEC Tx-Error IT Enable                    */
+#define CEC_IER_TXACKEIE_Pos     (12U)
+#define CEC_IER_TXACKEIE_Msk     (0x1UL << CEC_IER_TXACKEIE_Pos)               /*!< 0x00001000 */
+#define CEC_IER_TXACKEIE         CEC_IER_TXACKEIE_Msk                          /*!< CEC Tx Missing Acknowledge IT Enable      */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRC calculation unit                              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CRC_DR register  *********************/
+#define CRC_DR_DR_Pos            (0U)
+#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)               /*!< 0xFFFFFFFF */
+#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define CRC_IDR_IDR_Pos          (0U)
+#define CRC_IDR_IDR_Msk          (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)             /*!< 0xFFFFFFFF */
+#define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 32-bit data register bits */
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define CRC_CR_RESET_Pos         (0U)
+#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                   /*!< 0x00000001 */
+#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE_Pos      (3U)
+#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000018 */
+#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
+#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
+#define CRC_CR_REV_IN_Pos        (5U)
+#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000060 */
+#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
+#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
+#define CRC_CR_REV_OUT_Pos       (7U)
+#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                 /*!< 0x00000080 */
+#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
+
+/*******************  Bit definition for CRC_INIT register  *******************/
+#define CRC_INIT_INIT_Pos        (0U)
+#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)           /*!< 0xFFFFFFFF */
+#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
+
+/*******************  Bit definition for CRC_POL register  ********************/
+#define CRC_POL_POL_Pos          (0U)
+#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)             /*!< 0xFFFFFFFF */
+#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRS Clock Recovery System                         */
+/******************************************************************************/
+
+/*******************  Bit definition for CRS_CR register  *********************/
+#define CRS_CR_SYNCOKIE_Pos       (0U)
+#define CRS_CR_SYNCOKIE_Msk       (0x1UL << CRS_CR_SYNCOKIE_Pos)               /*!< 0x00000001 */
+#define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /*!< SYNC event OK interrupt enable */
+#define CRS_CR_SYNCWARNIE_Pos     (1U)
+#define CRS_CR_SYNCWARNIE_Msk     (0x1UL << CRS_CR_SYNCWARNIE_Pos)             /*!< 0x00000002 */
+#define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /*!< SYNC warning interrupt enable */
+#define CRS_CR_ERRIE_Pos          (2U)
+#define CRS_CR_ERRIE_Msk          (0x1UL << CRS_CR_ERRIE_Pos)                  /*!< 0x00000004 */
+#define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /*!< SYNC error or trimming error interrupt enable */
+#define CRS_CR_ESYNCIE_Pos        (3U)
+#define CRS_CR_ESYNCIE_Msk        (0x1UL << CRS_CR_ESYNCIE_Pos)                /*!< 0x00000008 */
+#define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /*!< Expected SYNC interrupt enable */
+#define CRS_CR_CEN_Pos            (5U)
+#define CRS_CR_CEN_Msk            (0x1UL << CRS_CR_CEN_Pos)                    /*!< 0x00000020 */
+#define CRS_CR_CEN                CRS_CR_CEN_Msk                               /*!< Frequency error counter enable */
+#define CRS_CR_AUTOTRIMEN_Pos     (6U)
+#define CRS_CR_AUTOTRIMEN_Msk     (0x1UL << CRS_CR_AUTOTRIMEN_Pos)             /*!< 0x00000040 */
+#define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /*!< Automatic trimming enable */
+#define CRS_CR_SWSYNC_Pos         (7U)
+#define CRS_CR_SWSYNC_Msk         (0x1UL << CRS_CR_SWSYNC_Pos)                 /*!< 0x00000080 */
+#define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /*!< Generate software SYNC event */
+#define CRS_CR_TRIM_Pos           (8U)
+#define CRS_CR_TRIM_Msk           (0x3FUL << CRS_CR_TRIM_Pos)                  /*!< 0x00003F00 */
+#define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /*!< HSI48 oscillator smooth trimming */
+
+/*******************  Bit definition for CRS_CFGR register  *********************/
+#define CRS_CFGR_RELOAD_Pos       (0U)
+#define CRS_CFGR_RELOAD_Msk       (0xFFFFUL << CRS_CFGR_RELOAD_Pos)            /*!< 0x0000FFFF */
+#define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /*!< Counter reload value */
+#define CRS_CFGR_FELIM_Pos        (16U)
+#define CRS_CFGR_FELIM_Msk        (0xFFUL << CRS_CFGR_FELIM_Pos)               /*!< 0x00FF0000 */
+#define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /*!< Frequency error limit */
+
+#define CRS_CFGR_SYNCDIV_Pos      (24U)
+#define CRS_CFGR_SYNCDIV_Msk      (0x7UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x07000000 */
+#define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /*!< SYNC divider */
+#define CRS_CFGR_SYNCDIV_0        (0x1UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */
+#define CRS_CFGR_SYNCDIV_1        (0x2UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */
+#define CRS_CFGR_SYNCDIV_2        (0x4UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */
+
+#define CRS_CFGR_SYNCSRC_Pos      (28U)
+#define CRS_CFGR_SYNCSRC_Msk      (0x3UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x30000000 */
+#define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /*!< SYNC signal source selection */
+#define CRS_CFGR_SYNCSRC_0        (0x1UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */
+#define CRS_CFGR_SYNCSRC_1        (0x2UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */
+
+#define CRS_CFGR_SYNCPOL_Pos      (31U)
+#define CRS_CFGR_SYNCPOL_Msk      (0x1UL << CRS_CFGR_SYNCPOL_Pos)              /*!< 0x80000000 */
+#define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /*!< SYNC polarity selection */
+
+/*******************  Bit definition for CRS_ISR register  *********************/
+#define CRS_ISR_SYNCOKF_Pos       (0U)
+#define CRS_ISR_SYNCOKF_Msk       (0x1UL << CRS_ISR_SYNCOKF_Pos)               /*!< 0x00000001 */
+#define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /*!< SYNC event OK flag */
+#define CRS_ISR_SYNCWARNF_Pos     (1U)
+#define CRS_ISR_SYNCWARNF_Msk     (0x1UL << CRS_ISR_SYNCWARNF_Pos)             /*!< 0x00000002 */
+#define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /*!< SYNC warning flag */
+#define CRS_ISR_ERRF_Pos          (2U)
+#define CRS_ISR_ERRF_Msk          (0x1UL << CRS_ISR_ERRF_Pos)                  /*!< 0x00000004 */
+#define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /*!< Error flag */
+#define CRS_ISR_ESYNCF_Pos        (3U)
+#define CRS_ISR_ESYNCF_Msk        (0x1UL << CRS_ISR_ESYNCF_Pos)                /*!< 0x00000008 */
+#define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /*!< Expected SYNC flag */
+#define CRS_ISR_SYNCERR_Pos       (8U)
+#define CRS_ISR_SYNCERR_Msk       (0x1UL << CRS_ISR_SYNCERR_Pos)               /*!< 0x00000100 */
+#define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /*!< SYNC error */
+#define CRS_ISR_SYNCMISS_Pos      (9U)
+#define CRS_ISR_SYNCMISS_Msk      (0x1UL << CRS_ISR_SYNCMISS_Pos)              /*!< 0x00000200 */
+#define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /*!< SYNC missed */
+#define CRS_ISR_TRIMOVF_Pos       (10U)
+#define CRS_ISR_TRIMOVF_Msk       (0x1UL << CRS_ISR_TRIMOVF_Pos)               /*!< 0x00000400 */
+#define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /*!< Trimming overflow or underflow */
+#define CRS_ISR_FEDIR_Pos         (15U)
+#define CRS_ISR_FEDIR_Msk         (0x1UL << CRS_ISR_FEDIR_Pos)                 /*!< 0x00008000 */
+#define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /*!< Frequency error direction */
+#define CRS_ISR_FECAP_Pos         (16U)
+#define CRS_ISR_FECAP_Msk         (0xFFFFUL << CRS_ISR_FECAP_Pos)              /*!< 0xFFFF0000 */
+#define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /*!< Frequency error capture */
+
+/*******************  Bit definition for CRS_ICR register  *********************/
+#define CRS_ICR_SYNCOKC_Pos       (0U)
+#define CRS_ICR_SYNCOKC_Msk       (0x1UL << CRS_ICR_SYNCOKC_Pos)               /*!< 0x00000001 */
+#define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /*!< SYNC event OK clear flag */
+#define CRS_ICR_SYNCWARNC_Pos     (1U)
+#define CRS_ICR_SYNCWARNC_Msk     (0x1UL << CRS_ICR_SYNCWARNC_Pos)             /*!< 0x00000002 */
+#define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /*!< SYNC warning clear flag */
+#define CRS_ICR_ERRC_Pos          (2U)
+#define CRS_ICR_ERRC_Msk          (0x1UL << CRS_ICR_ERRC_Pos)                  /*!< 0x00000004 */
+#define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /*!< Error clear flag */
+#define CRS_ICR_ESYNCC_Pos        (3U)
+#define CRS_ICR_ESYNCC_Msk        (0x1UL << CRS_ICR_ESYNCC_Pos)                /*!< 0x00000008 */
+#define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /*!< Expected SYNC clear flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Digital to Analog Converter                           */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DAC_CR register  ********************/
+#define DAC_CR_EN1_Pos              (0U)
+#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                  /*!< 0x00000001 */
+#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */
+#define DAC_CR_TEN1_Pos             (1U)
+#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                 /*!< 0x00000002 */
+#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos            (2U)
+#define DAC_CR_TSEL1_Msk            (0xFUL << DAC_CR_TSEL1_Pos)                /*!< 0x0000003C */
+#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000004 */
+#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
+#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
+#define DAC_CR_TSEL1_3              (0x8UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
+
+
+#define DAC_CR_WAVE1_Pos            (6U)
+#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                /*!< 0x000000C0 */
+#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos            (8U)
+#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                /*!< 0x00000F00 */
+#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos           (12U)
+#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)               /*!< 0x00001000 */
+#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1_Pos        (13U)
+#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)            /*!< 0x00002000 */
+#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/
+#define DAC_CR_CEN1_Pos             (14U)
+#define DAC_CR_CEN1_Msk             (0x1UL << DAC_CR_CEN1_Pos)                 /*!< 0x00004000 */
+#define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/
+
+#define DAC_CR_EN2_Pos              (16U)
+#define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                  /*!< 0x00010000 */
+#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */
+#define DAC_CR_TEN2_Pos             (17U)
+#define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                 /*!< 0x00020000 */
+#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2_Pos            (18U)
+#define DAC_CR_TSEL2_Msk            (0xFUL << DAC_CR_TSEL2_Pos)                /*!< 0x003C0000 */
+#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00040000 */
+#define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */
+#define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */
+#define DAC_CR_TSEL2_3              (0x8UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */
+
+
+#define DAC_CR_WAVE2_Pos            (22U)
+#define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                /*!< 0x00C00000 */
+#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */
+#define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */
+
+#define DAC_CR_MAMP2_Pos            (24U)
+#define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                /*!< 0x0F000000 */
+#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */
+#define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */
+#define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */
+#define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */
+
+#define DAC_CR_DMAEN2_Pos           (28U)
+#define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)               /*!< 0x10000000 */
+#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2_Pos        (29U)
+#define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)            /*!< 0x20000000 */
+#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/
+#define DAC_CR_CEN2_Pos             (30U)
+#define DAC_CR_CEN2_Msk             (0x1UL << DAC_CR_CEN2_Pos)                 /*!< 0x40000000 */
+#define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/
+
+/*****************  Bit definition for DAC_SWTRIGR register  ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)
+#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)         /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)
+#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)         /*!< 0x00000002 */
+#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */
+
+/*****************  Bit definition for DAC_DHR12R1 register  ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos    (0U)
+#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)      /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L1 register  ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos    (4U)
+#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)      /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R1 register  ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos     (0U)
+#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)        /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12R2 register  ******************/
+#define DAC_DHR12R2_DACC2DHR_Pos    (0U)
+#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)      /*!< 0x00000FFF */
+#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L2 register  ******************/
+#define DAC_DHR12L2_DACC2DHR_Pos    (4U)
+#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)      /*!< 0x0000FFF0 */
+#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R2 register  ******************/
+#define DAC_DHR8R2_DACC2DHR_Pos     (0U)
+#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)        /*!< 0x000000FF */
+#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12RD register  ******************/
+#define DAC_DHR12RD_DACC1DHR_Pos    (0U)
+#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)      /*!< 0x00000FFF */
+#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR_Pos    (16U)
+#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)      /*!< 0x0FFF0000 */
+#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12LD register  ******************/
+#define DAC_DHR12LD_DACC1DHR_Pos    (4U)
+#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)      /*!< 0x0000FFF0 */
+#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR_Pos    (20U)
+#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)      /*!< 0xFFF00000 */
+#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8RD register  ******************/
+#define DAC_DHR8RD_DACC1DHR_Pos     (0U)
+#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)        /*!< 0x000000FF */
+#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR_Pos     (8U)
+#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)        /*!< 0x0000FF00 */
+#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
+
+/*******************  Bit definition for DAC_DOR1 register  *******************/
+#define DAC_DOR1_DACC1DOR_Pos       (0U)
+#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)         /*!< 0x00000FFF */
+#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */
+
+/*******************  Bit definition for DAC_DOR2 register  *******************/
+#define DAC_DOR2_DACC2DOR_Pos       (0U)
+#define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)         /*!< 0x00000FFF */
+#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */
+
+/********************  Bit definition for DAC_SR register  ********************/
+#define DAC_SR_DMAUDR1_Pos          (13U)
+#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)              /*!< 0x00002000 */
+#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_CAL_FLAG1_Pos        (14U)
+#define DAC_SR_CAL_FLAG1_Msk        (0x1UL << DAC_SR_CAL_FLAG1_Pos)            /*!< 0x00004000 */
+#define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */
+#define DAC_SR_BWST1_Pos            (15U)
+#define DAC_SR_BWST1_Msk            (0x4001UL << DAC_SR_BWST1_Pos)             /*!< 0x20008000 */
+#define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */
+
+#define DAC_SR_DMAUDR2_Pos          (29U)
+#define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)              /*!< 0x20000000 */
+#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */
+#define DAC_SR_CAL_FLAG2_Pos        (30U)
+#define DAC_SR_CAL_FLAG2_Msk        (0x1UL << DAC_SR_CAL_FLAG2_Pos)            /*!< 0x40000000 */
+#define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */
+#define DAC_SR_BWST2_Pos            (31U)
+#define DAC_SR_BWST2_Msk            (0x1UL << DAC_SR_BWST2_Pos)                /*!< 0x80000000 */
+#define DAC_SR_BWST2                DAC_SR_BWST2_Msk                           /*!<DAC channel2 busy writing sample time flag */
+
+/*******************  Bit definition for DAC_CCR register  ********************/
+#define DAC_CCR_OTRIM1_Pos          (0U)
+#define DAC_CCR_OTRIM1_Msk          (0x1FUL << DAC_CCR_OTRIM1_Pos)             /*!< 0x0000001F */
+#define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */
+#define DAC_CCR_OTRIM2_Pos          (16U)
+#define DAC_CCR_OTRIM2_Msk          (0x1FUL << DAC_CCR_OTRIM2_Pos)             /*!< 0x001F0000 */
+#define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */
+
+/*******************  Bit definition for DAC_MCR register  *******************/
+#define DAC_MCR_MODE1_Pos           (0U)
+#define DAC_MCR_MODE1_Msk           (0x7UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000007 */
+#define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */
+#define DAC_MCR_MODE1_0             (0x1UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000001 */
+#define DAC_MCR_MODE1_1             (0x2UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000002 */
+#define DAC_MCR_MODE1_2             (0x4UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000004 */
+
+#define DAC_MCR_MODE2_Pos           (16U)
+#define DAC_MCR_MODE2_Msk           (0x7UL << DAC_MCR_MODE2_Pos)               /*!< 0x00070000 */
+#define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */
+#define DAC_MCR_MODE2_0             (0x1UL << DAC_MCR_MODE2_Pos)                /*!< 0x00010000 */
+#define DAC_MCR_MODE2_1             (0x2UL << DAC_MCR_MODE2_Pos)                /*!< 0x00020000 */
+#define DAC_MCR_MODE2_2             (0x4UL << DAC_MCR_MODE2_Pos)                /*!< 0x00040000 */
+
+/******************  Bit definition for DAC_SHSR1 register  ******************/
+#define DAC_SHSR1_TSAMPLE1_Pos      (0U)
+#define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)        /*!< 0x000003FF */
+#define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */
+
+/******************  Bit definition for DAC_SHSR2 register  ******************/
+#define DAC_SHSR2_TSAMPLE2_Pos      (0U)
+#define DAC_SHSR2_TSAMPLE2_Msk      (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)        /*!< 0x000003FF */
+#define DAC_SHSR2_TSAMPLE2          DAC_SHSR2_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */
+
+/******************  Bit definition for DAC_SHHR register  ******************/
+#define DAC_SHHR_THOLD1_Pos         (0U)
+#define DAC_SHHR_THOLD1_Msk         (0x3FFUL << DAC_SHHR_THOLD1_Pos)           /*!< 0x000003FF */
+#define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */
+#define DAC_SHHR_THOLD2_Pos         (16U)
+#define DAC_SHHR_THOLD2_Msk         (0x3FFUL << DAC_SHHR_THOLD2_Pos)           /*!< 0x03FF0000 */
+#define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */
+
+/******************  Bit definition for DAC_SHRR register  ******************/
+#define DAC_SHRR_TREFRESH1_Pos      (0U)
+#define DAC_SHRR_TREFRESH1_Msk      (0xFFUL << DAC_SHRR_TREFRESH1_Pos)         /*!< 0x000000FF */
+#define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */
+#define DAC_SHRR_TREFRESH2_Pos      (16U)
+#define DAC_SHRR_TREFRESH2_Msk      (0xFFUL << DAC_SHRR_TREFRESH2_Pos)         /*!< 0x00FF0000 */
+#define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    DCMI                                    */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for DCMI_CR register  ******************/
+#define DCMI_CR_CAPTURE_Pos        (0U)
+#define DCMI_CR_CAPTURE_Msk        (0x1UL << DCMI_CR_CAPTURE_Pos)              /*!< 0x00000001 */
+#define DCMI_CR_CAPTURE            DCMI_CR_CAPTURE_Msk
+#define DCMI_CR_CM_Pos             (1U)
+#define DCMI_CR_CM_Msk             (0x1UL << DCMI_CR_CM_Pos)                   /*!< 0x00000002 */
+#define DCMI_CR_CM                 DCMI_CR_CM_Msk
+#define DCMI_CR_CROP_Pos           (2U)
+#define DCMI_CR_CROP_Msk           (0x1UL << DCMI_CR_CROP_Pos)                 /*!< 0x00000004 */
+#define DCMI_CR_CROP               DCMI_CR_CROP_Msk
+#define DCMI_CR_JPEG_Pos           (3U)
+#define DCMI_CR_JPEG_Msk           (0x1UL << DCMI_CR_JPEG_Pos)                 /*!< 0x00000008 */
+#define DCMI_CR_JPEG               DCMI_CR_JPEG_Msk
+#define DCMI_CR_ESS_Pos            (4U)
+#define DCMI_CR_ESS_Msk            (0x1UL << DCMI_CR_ESS_Pos)                  /*!< 0x00000010 */
+#define DCMI_CR_ESS                DCMI_CR_ESS_Msk
+#define DCMI_CR_PCKPOL_Pos         (5U)
+#define DCMI_CR_PCKPOL_Msk         (0x1UL << DCMI_CR_PCKPOL_Pos)               /*!< 0x00000020 */
+#define DCMI_CR_PCKPOL             DCMI_CR_PCKPOL_Msk
+#define DCMI_CR_HSPOL_Pos          (6U)
+#define DCMI_CR_HSPOL_Msk          (0x1UL << DCMI_CR_HSPOL_Pos)                /*!< 0x00000040 */
+#define DCMI_CR_HSPOL              DCMI_CR_HSPOL_Msk
+#define DCMI_CR_VSPOL_Pos          (7U)
+#define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                /*!< 0x00000080 */
+#define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk
+#define DCMI_CR_FCRC_0             ((uint32_t)0x00000100U)
+#define DCMI_CR_FCRC_1             ((uint32_t)0x00000200U)
+#define DCMI_CR_EDM_0              ((uint32_t)0x00000400U)
+#define DCMI_CR_EDM_1              ((uint32_t)0x00000800U)
+#define DCMI_CR_CRE_Pos            (12U)
+#define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                  /*!< 0x00001000 */
+#define DCMI_CR_CRE                DCMI_CR_CRE_Msk
+#define DCMI_CR_ENABLE_Pos         (14U)
+#define DCMI_CR_ENABLE_Msk         (0x1UL << DCMI_CR_ENABLE_Pos)               /*!< 0x00004000 */
+#define DCMI_CR_ENABLE             DCMI_CR_ENABLE_Msk
+#define DCMI_CR_BSM_Pos            (16U)
+#define DCMI_CR_BSM_Msk            (0x3UL << DCMI_CR_BSM_Pos)                  /*!< 0x00030000 */
+#define DCMI_CR_BSM                DCMI_CR_BSM_Msk
+#define DCMI_CR_BSM_0              (0x1UL << DCMI_CR_BSM_Pos)                   /*!< 0x00010000 */
+#define DCMI_CR_BSM_1              (0x2UL << DCMI_CR_BSM_Pos)                   /*!< 0x00020000 */
+#define DCMI_CR_OEBS_Pos           (18U)
+#define DCMI_CR_OEBS_Msk           (0x1UL << DCMI_CR_OEBS_Pos)                 /*!< 0x00040000 */
+#define DCMI_CR_OEBS               DCMI_CR_OEBS_Msk
+#define DCMI_CR_LSM_Pos            (19U)
+#define DCMI_CR_LSM_Msk            (0x1UL << DCMI_CR_LSM_Pos)                  /*!< 0x00080000 */
+#define DCMI_CR_LSM                DCMI_CR_LSM_Msk
+#define DCMI_CR_OELS_Pos           (20U)
+#define DCMI_CR_OELS_Msk           (0x1UL << DCMI_CR_OELS_Pos)                 /*!< 0x00100000 */
+#define DCMI_CR_OELS               DCMI_CR_OELS_Msk
+
+/********************  Bits definition for DCMI_SR register  ******************/
+#define DCMI_SR_HSYNC_Pos          (0U)
+#define DCMI_SR_HSYNC_Msk          (0x1UL << DCMI_SR_HSYNC_Pos)                /*!< 0x00000001 */
+#define DCMI_SR_HSYNC              DCMI_SR_HSYNC_Msk
+#define DCMI_SR_VSYNC_Pos          (1U)
+#define DCMI_SR_VSYNC_Msk          (0x1UL << DCMI_SR_VSYNC_Pos)                /*!< 0x00000002 */
+#define DCMI_SR_VSYNC              DCMI_SR_VSYNC_Msk
+#define DCMI_SR_FNE_Pos            (2U)
+#define DCMI_SR_FNE_Msk            (0x1UL << DCMI_SR_FNE_Pos)                  /*!< 0x00000004 */
+#define DCMI_SR_FNE                DCMI_SR_FNE_Msk
+
+/********************  Bits definition for DCMI_RIS register   ****************/
+#define DCMI_RIS_FRAME_RIS_Pos     (0U)
+#define DCMI_RIS_FRAME_RIS_Msk     (0x1UL << DCMI_RIS_FRAME_RIS_Pos)           /*!< 0x00000001 */
+#define DCMI_RIS_FRAME_RIS         DCMI_RIS_FRAME_RIS_Msk
+#define DCMI_RIS_OVR_RIS_Pos       (1U)
+#define DCMI_RIS_OVR_RIS_Msk       (0x1UL << DCMI_RIS_OVR_RIS_Pos)             /*!< 0x00000002 */
+#define DCMI_RIS_OVR_RIS           DCMI_RIS_OVR_RIS_Msk
+#define DCMI_RIS_ERR_RIS_Pos       (2U)
+#define DCMI_RIS_ERR_RIS_Msk       (0x1UL << DCMI_RIS_ERR_RIS_Pos)             /*!< 0x00000004 */
+#define DCMI_RIS_ERR_RIS           DCMI_RIS_ERR_RIS_Msk
+#define DCMI_RIS_VSYNC_RIS_Pos     (3U)
+#define DCMI_RIS_VSYNC_RIS_Msk     (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)           /*!< 0x00000008 */
+#define DCMI_RIS_VSYNC_RIS         DCMI_RIS_VSYNC_RIS_Msk
+#define DCMI_RIS_LINE_RIS_Pos      (4U)
+#define DCMI_RIS_LINE_RIS_Msk      (0x1UL << DCMI_RIS_LINE_RIS_Pos)            /*!< 0x00000010 */
+#define DCMI_RIS_LINE_RIS          DCMI_RIS_LINE_RIS_Msk
+
+/********************  Bits definition for DCMI_IER register  *****************/
+#define DCMI_IER_FRAME_IE_Pos      (0U)
+#define DCMI_IER_FRAME_IE_Msk      (0x1UL << DCMI_IER_FRAME_IE_Pos)            /*!< 0x00000001 */
+#define DCMI_IER_FRAME_IE          DCMI_IER_FRAME_IE_Msk
+#define DCMI_IER_OVR_IE_Pos        (1U)
+#define DCMI_IER_OVR_IE_Msk        (0x1UL << DCMI_IER_OVR_IE_Pos)              /*!< 0x00000002 */
+#define DCMI_IER_OVR_IE            DCMI_IER_OVR_IE_Msk
+#define DCMI_IER_ERR_IE_Pos        (2U)
+#define DCMI_IER_ERR_IE_Msk        (0x1UL << DCMI_IER_ERR_IE_Pos)              /*!< 0x00000004 */
+#define DCMI_IER_ERR_IE            DCMI_IER_ERR_IE_Msk
+#define DCMI_IER_VSYNC_IE_Pos      (3U)
+#define DCMI_IER_VSYNC_IE_Msk      (0x1UL << DCMI_IER_VSYNC_IE_Pos)            /*!< 0x00000008 */
+#define DCMI_IER_VSYNC_IE          DCMI_IER_VSYNC_IE_Msk
+#define DCMI_IER_LINE_IE_Pos       (4U)
+#define DCMI_IER_LINE_IE_Msk       (0x1UL << DCMI_IER_LINE_IE_Pos)             /*!< 0x00000010 */
+#define DCMI_IER_LINE_IE           DCMI_IER_LINE_IE_Msk
+
+
+/********************  Bits definition for DCMI_MIS register  *****************/
+#define DCMI_MIS_FRAME_MIS_Pos     (0U)
+#define DCMI_MIS_FRAME_MIS_Msk     (0x1UL << DCMI_MIS_FRAME_MIS_Pos)           /*!< 0x00000001 */
+#define DCMI_MIS_FRAME_MIS         DCMI_MIS_FRAME_MIS_Msk
+#define DCMI_MIS_OVR_MIS_Pos       (1U)
+#define DCMI_MIS_OVR_MIS_Msk       (0x1UL << DCMI_MIS_OVR_MIS_Pos)             /*!< 0x00000002 */
+#define DCMI_MIS_OVR_MIS           DCMI_MIS_OVR_MIS_Msk
+#define DCMI_MIS_ERR_MIS_Pos       (2U)
+#define DCMI_MIS_ERR_MIS_Msk       (0x1UL << DCMI_MIS_ERR_MIS_Pos)             /*!< 0x00000004 */
+#define DCMI_MIS_ERR_MIS           DCMI_MIS_ERR_MIS_Msk
+#define DCMI_MIS_VSYNC_MIS_Pos     (3U)
+#define DCMI_MIS_VSYNC_MIS_Msk     (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)           /*!< 0x00000008 */
+#define DCMI_MIS_VSYNC_MIS         DCMI_MIS_VSYNC_MIS_Msk
+#define DCMI_MIS_LINE_MIS_Pos      (4U)
+#define DCMI_MIS_LINE_MIS_Msk      (0x1UL << DCMI_MIS_LINE_MIS_Pos)            /*!< 0x00000010 */
+#define DCMI_MIS_LINE_MIS          DCMI_MIS_LINE_MIS_Msk
+
+
+/********************  Bits definition for DCMI_ICR register  *****************/
+#define DCMI_ICR_FRAME_ISC_Pos     (0U)
+#define DCMI_ICR_FRAME_ISC_Msk     (0x1UL << DCMI_ICR_FRAME_ISC_Pos)           /*!< 0x00000001 */
+#define DCMI_ICR_FRAME_ISC         DCMI_ICR_FRAME_ISC_Msk
+#define DCMI_ICR_OVR_ISC_Pos       (1U)
+#define DCMI_ICR_OVR_ISC_Msk       (0x1UL << DCMI_ICR_OVR_ISC_Pos)             /*!< 0x00000002 */
+#define DCMI_ICR_OVR_ISC           DCMI_ICR_OVR_ISC_Msk
+#define DCMI_ICR_ERR_ISC_Pos       (2U)
+#define DCMI_ICR_ERR_ISC_Msk       (0x1UL << DCMI_ICR_ERR_ISC_Pos)             /*!< 0x00000004 */
+#define DCMI_ICR_ERR_ISC           DCMI_ICR_ERR_ISC_Msk
+#define DCMI_ICR_VSYNC_ISC_Pos     (3U)
+#define DCMI_ICR_VSYNC_ISC_Msk     (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)           /*!< 0x00000008 */
+#define DCMI_ICR_VSYNC_ISC         DCMI_ICR_VSYNC_ISC_Msk
+#define DCMI_ICR_LINE_ISC_Pos      (4U)
+#define DCMI_ICR_LINE_ISC_Msk      (0x1UL << DCMI_ICR_LINE_ISC_Pos)            /*!< 0x00000010 */
+#define DCMI_ICR_LINE_ISC          DCMI_ICR_LINE_ISC_Msk
+
+
+/********************  Bits definition for DCMI_ESCR register  ******************/
+#define DCMI_ESCR_FSC_Pos          (0U)
+#define DCMI_ESCR_FSC_Msk          (0xFFUL << DCMI_ESCR_FSC_Pos)               /*!< 0x000000FF */
+#define DCMI_ESCR_FSC              DCMI_ESCR_FSC_Msk
+#define DCMI_ESCR_LSC_Pos          (8U)
+#define DCMI_ESCR_LSC_Msk          (0xFFUL << DCMI_ESCR_LSC_Pos)               /*!< 0x0000FF00 */
+#define DCMI_ESCR_LSC              DCMI_ESCR_LSC_Msk
+#define DCMI_ESCR_LEC_Pos          (16U)
+#define DCMI_ESCR_LEC_Msk          (0xFFUL << DCMI_ESCR_LEC_Pos)               /*!< 0x00FF0000 */
+#define DCMI_ESCR_LEC              DCMI_ESCR_LEC_Msk
+#define DCMI_ESCR_FEC_Pos          (24U)
+#define DCMI_ESCR_FEC_Msk          (0xFFUL << DCMI_ESCR_FEC_Pos)               /*!< 0xFF000000 */
+#define DCMI_ESCR_FEC              DCMI_ESCR_FEC_Msk
+
+/********************  Bits definition for DCMI_ESUR register  ******************/
+#define DCMI_ESUR_FSU_Pos          (0U)
+#define DCMI_ESUR_FSU_Msk          (0xFFUL << DCMI_ESUR_FSU_Pos)               /*!< 0x000000FF */
+#define DCMI_ESUR_FSU              DCMI_ESUR_FSU_Msk
+#define DCMI_ESUR_LSU_Pos          (8U)
+#define DCMI_ESUR_LSU_Msk          (0xFFUL << DCMI_ESUR_LSU_Pos)               /*!< 0x0000FF00 */
+#define DCMI_ESUR_LSU              DCMI_ESUR_LSU_Msk
+#define DCMI_ESUR_LEU_Pos          (16U)
+#define DCMI_ESUR_LEU_Msk          (0xFFUL << DCMI_ESUR_LEU_Pos)               /*!< 0x00FF0000 */
+#define DCMI_ESUR_LEU              DCMI_ESUR_LEU_Msk
+#define DCMI_ESUR_FEU_Pos          (24U)
+#define DCMI_ESUR_FEU_Msk          (0xFFUL << DCMI_ESUR_FEU_Pos)               /*!< 0xFF000000 */
+#define DCMI_ESUR_FEU              DCMI_ESUR_FEU_Msk
+
+/********************  Bits definition for DCMI_CWSTRT register  ******************/
+#define DCMI_CWSTRT_HOFFCNT_Pos    (0U)
+#define DCMI_CWSTRT_HOFFCNT_Msk    (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)       /*!< 0x00003FFF */
+#define DCMI_CWSTRT_HOFFCNT        DCMI_CWSTRT_HOFFCNT_Msk
+#define DCMI_CWSTRT_VST_Pos        (16U)
+#define DCMI_CWSTRT_VST_Msk        (0x1FFFUL << DCMI_CWSTRT_VST_Pos)           /*!< 0x1FFF0000 */
+#define DCMI_CWSTRT_VST            DCMI_CWSTRT_VST_Msk
+
+/********************  Bits definition for DCMI_CWSIZE register  ******************/
+#define DCMI_CWSIZE_CAPCNT_Pos     (0U)
+#define DCMI_CWSIZE_CAPCNT_Msk     (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)        /*!< 0x00003FFF */
+#define DCMI_CWSIZE_CAPCNT         DCMI_CWSIZE_CAPCNT_Msk
+#define DCMI_CWSIZE_VLINE_Pos      (16U)
+#define DCMI_CWSIZE_VLINE_Msk      (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)         /*!< 0x3FFF0000 */
+#define DCMI_CWSIZE_VLINE          DCMI_CWSIZE_VLINE_Msk
+
+/********************  Bits definition for DCMI_DR register  ******************/
+#define DCMI_DR_BYTE0_Pos          (0U)
+#define DCMI_DR_BYTE0_Msk          (0xFFUL << DCMI_DR_BYTE0_Pos)               /*!< 0x000000FF */
+#define DCMI_DR_BYTE0              DCMI_DR_BYTE0_Msk
+#define DCMI_DR_BYTE1_Pos          (8U)
+#define DCMI_DR_BYTE1_Msk          (0xFFUL << DCMI_DR_BYTE1_Pos)               /*!< 0x0000FF00 */
+#define DCMI_DR_BYTE1              DCMI_DR_BYTE1_Msk
+#define DCMI_DR_BYTE2_Pos          (16U)
+#define DCMI_DR_BYTE2_Msk          (0xFFUL << DCMI_DR_BYTE2_Pos)               /*!< 0x00FF0000 */
+#define DCMI_DR_BYTE2              DCMI_DR_BYTE2_Msk
+#define DCMI_DR_BYTE3_Pos          (24U)
+#define DCMI_DR_BYTE3_Msk          (0xFFUL << DCMI_DR_BYTE3_Pos)               /*!< 0xFF000000 */
+#define DCMI_DR_BYTE3              DCMI_DR_BYTE3_Msk
+
+/******************************************************************************/
+/*                                                                            */
+/*                 Digital Filter for Sigma Delta Modulators                  */
+/*                                                                            */
+/******************************************************************************/
+
+/****************   DFSDM channel configuration registers  ********************/
+
+/***************  Bit definition for DFSDM_CHCFGR1 register  ******************/
+#define DFSDM_CHCFGR1_DFSDMEN_Pos       (31U)
+#define DFSDM_CHCFGR1_DFSDMEN_Msk       (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos)   /*!< 0x80000000 */
+#define DFSDM_CHCFGR1_DFSDMEN           DFSDM_CHCFGR1_DFSDMEN_Msk              /*!< Global enable for DFSDM interface */
+#define DFSDM_CHCFGR1_CKOUTSRC_Pos      (30U)
+#define DFSDM_CHCFGR1_CKOUTSRC_Msk      (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos)  /*!< 0x40000000 */
+#define DFSDM_CHCFGR1_CKOUTSRC          DFSDM_CHCFGR1_CKOUTSRC_Msk             /*!< Output serial clock source selection */
+#define DFSDM_CHCFGR1_CKOUTDIV_Pos      (16U)
+#define DFSDM_CHCFGR1_CKOUTDIV_Msk      (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */
+#define DFSDM_CHCFGR1_CKOUTDIV          DFSDM_CHCFGR1_CKOUTDIV_Msk             /*!< CKOUTDIV[7:0] output serial clock divider */
+#define DFSDM_CHCFGR1_DATPACK_Pos       (14U)
+#define DFSDM_CHCFGR1_DATPACK_Msk       (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos)   /*!< 0x0000C000 */
+#define DFSDM_CHCFGR1_DATPACK           DFSDM_CHCFGR1_DATPACK_Msk              /*!< DATPACK[1:0] Data packing mode */
+#define DFSDM_CHCFGR1_DATPACK_1         (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00008000 */
+#define DFSDM_CHCFGR1_DATPACK_0         (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00004000 */
+#define DFSDM_CHCFGR1_DATMPX_Pos        (12U)
+#define DFSDM_CHCFGR1_DATMPX_Msk        (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos)    /*!< 0x00003000 */
+#define DFSDM_CHCFGR1_DATMPX            DFSDM_CHCFGR1_DATMPX_Msk               /*!< DATMPX[1:0] Input data multiplexer for channel y */
+#define DFSDM_CHCFGR1_DATMPX_1          (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00002000 */
+#define DFSDM_CHCFGR1_DATMPX_0          (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00001000 */
+#define DFSDM_CHCFGR1_CHINSEL_Pos       (8U)
+#define DFSDM_CHCFGR1_CHINSEL_Msk       (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos)   /*!< 0x00000100 */
+#define DFSDM_CHCFGR1_CHINSEL           DFSDM_CHCFGR1_CHINSEL_Msk              /*!< Serial inputs selection for channel y */
+#define DFSDM_CHCFGR1_CHEN_Pos          (7U)
+#define DFSDM_CHCFGR1_CHEN_Msk          (0x1UL << DFSDM_CHCFGR1_CHEN_Pos)      /*!< 0x00000080 */
+#define DFSDM_CHCFGR1_CHEN              DFSDM_CHCFGR1_CHEN_Msk                 /*!< Channel y enable */
+#define DFSDM_CHCFGR1_CKABEN_Pos        (6U)
+#define DFSDM_CHCFGR1_CKABEN_Msk        (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos)    /*!< 0x00000040 */
+#define DFSDM_CHCFGR1_CKABEN            DFSDM_CHCFGR1_CKABEN_Msk               /*!< Clock absence detector enable on channel y */
+#define DFSDM_CHCFGR1_SCDEN_Pos         (5U)
+#define DFSDM_CHCFGR1_SCDEN_Msk         (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos)     /*!< 0x00000020 */
+#define DFSDM_CHCFGR1_SCDEN             DFSDM_CHCFGR1_SCDEN_Msk                /*!< Short circuit detector enable on channel y */
+#define DFSDM_CHCFGR1_SPICKSEL_Pos      (2U)
+#define DFSDM_CHCFGR1_SPICKSEL_Msk      (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos)  /*!< 0x0000000C */
+#define DFSDM_CHCFGR1_SPICKSEL          DFSDM_CHCFGR1_SPICKSEL_Msk             /*!< SPICKSEL[1:0] SPI clock select for channel y */
+#define DFSDM_CHCFGR1_SPICKSEL_1        (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000008 */
+#define DFSDM_CHCFGR1_SPICKSEL_0        (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000004 */
+#define DFSDM_CHCFGR1_SITP_Pos          (0U)
+#define DFSDM_CHCFGR1_SITP_Msk          (0x3UL << DFSDM_CHCFGR1_SITP_Pos)      /*!< 0x00000003 */
+#define DFSDM_CHCFGR1_SITP              DFSDM_CHCFGR1_SITP_Msk                 /*!< SITP[1:0] Serial interface type for channel y */
+#define DFSDM_CHCFGR1_SITP_1            (0x2UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000002 */
+#define DFSDM_CHCFGR1_SITP_0            (0x1UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000001 */
+
+/***************  Bit definition for DFSDM_CHCFGR2 register  ******************/
+#define DFSDM_CHCFGR2_OFFSET_Pos        (8U)
+#define DFSDM_CHCFGR2_OFFSET_Msk        (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_CHCFGR2_OFFSET            DFSDM_CHCFGR2_OFFSET_Msk               /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
+#define DFSDM_CHCFGR2_DTRBS_Pos         (3U)
+#define DFSDM_CHCFGR2_DTRBS_Msk         (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos)    /*!< 0x000000F8 */
+#define DFSDM_CHCFGR2_DTRBS             DFSDM_CHCFGR2_DTRBS_Msk                /*!< DTRBS[4:0] Data right bit-shift for channel y */
+
+/******************  Bit definition for DFSDM_CHAWSCDR register *****************/
+#define DFSDM_CHAWSCDR_AWFORD_Pos       (22U)
+#define DFSDM_CHAWSCDR_AWFORD_Msk       (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos)   /*!< 0x00C00000 */
+#define DFSDM_CHAWSCDR_AWFORD           DFSDM_CHAWSCDR_AWFORD_Msk              /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
+#define DFSDM_CHAWSCDR_AWFORD_1         (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00800000 */
+#define DFSDM_CHAWSCDR_AWFORD_0         (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00400000 */
+#define DFSDM_CHAWSCDR_AWFOSR_Pos       (16U)
+#define DFSDM_CHAWSCDR_AWFOSR_Msk       (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos)  /*!< 0x001F0000 */
+#define DFSDM_CHAWSCDR_AWFOSR           DFSDM_CHAWSCDR_AWFOSR_Msk              /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
+#define DFSDM_CHAWSCDR_BKSCD_Pos        (12U)
+#define DFSDM_CHAWSCDR_BKSCD_Msk        (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos)    /*!< 0x0000F000 */
+#define DFSDM_CHAWSCDR_BKSCD            DFSDM_CHAWSCDR_BKSCD_Msk               /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
+#define DFSDM_CHAWSCDR_SCDT_Pos         (0U)
+#define DFSDM_CHAWSCDR_SCDT_Msk         (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos)    /*!< 0x000000FF */
+#define DFSDM_CHAWSCDR_SCDT             DFSDM_CHAWSCDR_SCDT_Msk                /*!< SCDT[7:0] Short circuit detector threshold for channel y */
+
+/****************  Bit definition for DFSDM_CHWDATR register *******************/
+#define DFSDM_CHWDATR_WDATA_Pos         (0U)
+#define DFSDM_CHWDATR_WDATA_Msk         (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos)  /*!< 0x0000FFFF */
+#define DFSDM_CHWDATR_WDATA             DFSDM_CHWDATR_WDATA_Msk                /*!< WDATA[15:0] Input channel y watchdog data */
+
+/****************  Bit definition for DFSDM_CHDATINR register *****************/
+#define DFSDM_CHDATINR_INDAT0_Pos       (0U)
+#define DFSDM_CHDATINR_INDAT0_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */
+#define DFSDM_CHDATINR_INDAT0           DFSDM_CHDATINR_INDAT0_Msk              /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
+#define DFSDM_CHDATINR_INDAT1_Pos       (16U)
+#define DFSDM_CHDATINR_INDAT1_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */
+#define DFSDM_CHDATINR_INDAT1           DFSDM_CHDATINR_INDAT1_Msk              /*!< INDAT0[15:0] Input data for channel y */
+
+/************************   DFSDM module registers  ****************************/
+
+/********************  Bit definition for DFSDM_FLTCR1 register *******************/
+#define DFSDM_FLTCR1_AWFSEL_Pos         (30U)
+#define DFSDM_FLTCR1_AWFSEL_Msk         (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos)     /*!< 0x40000000 */
+#define DFSDM_FLTCR1_AWFSEL             DFSDM_FLTCR1_AWFSEL_Msk                /*!< Analog watchdog fast mode select */
+#define DFSDM_FLTCR1_FAST_Pos           (29U)
+#define DFSDM_FLTCR1_FAST_Msk           (0x1UL << DFSDM_FLTCR1_FAST_Pos)       /*!< 0x20000000 */
+#define DFSDM_FLTCR1_FAST               DFSDM_FLTCR1_FAST_Msk                  /*!< Fast conversion mode selection */
+#define DFSDM_FLTCR1_RCH_Pos            (24U)
+#define DFSDM_FLTCR1_RCH_Msk            (0x7UL << DFSDM_FLTCR1_RCH_Pos)        /*!< 0x07000000 */
+#define DFSDM_FLTCR1_RCH                DFSDM_FLTCR1_RCH_Msk                   /*!< RCH[2:0] Regular channel selection */
+#define DFSDM_FLTCR1_RDMAEN_Pos         (21U)
+#define DFSDM_FLTCR1_RDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos)     /*!< 0x00200000 */
+#define DFSDM_FLTCR1_RDMAEN             DFSDM_FLTCR1_RDMAEN_Msk                /*!< DMA channel enabled to read data for the regular conversion */
+#define DFSDM_FLTCR1_RSYNC_Pos          (19U)
+#define DFSDM_FLTCR1_RSYNC_Msk          (0x1UL << DFSDM_FLTCR1_RSYNC_Pos)      /*!< 0x00080000 */
+#define DFSDM_FLTCR1_RSYNC              DFSDM_FLTCR1_RSYNC_Msk                 /*!< Launch regular conversion synchronously with DFSDMx */
+#define DFSDM_FLTCR1_RCONT_Pos          (18U)
+#define DFSDM_FLTCR1_RCONT_Msk          (0x1UL << DFSDM_FLTCR1_RCONT_Pos)      /*!< 0x00040000 */
+#define DFSDM_FLTCR1_RCONT              DFSDM_FLTCR1_RCONT_Msk                 /*!< Continuous mode selection for regular conversions */
+#define DFSDM_FLTCR1_RSWSTART_Pos       (17U)
+#define DFSDM_FLTCR1_RSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos)   /*!< 0x00020000 */
+#define DFSDM_FLTCR1_RSWSTART           DFSDM_FLTCR1_RSWSTART_Msk              /*!< Software start of a conversion on the regular channel */
+#define DFSDM_FLTCR1_JEXTEN_Pos         (13U)
+#define DFSDM_FLTCR1_JEXTEN_Msk         (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos)     /*!< 0x00006000 */
+#define DFSDM_FLTCR1_JEXTEN             DFSDM_FLTCR1_JEXTEN_Msk                /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
+#define DFSDM_FLTCR1_JEXTEN_1           (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00004000 */
+#define DFSDM_FLTCR1_JEXTEN_0           (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00002000 */
+#define DFSDM_FLTCR1_JEXTSEL_Pos        (8U)
+#define DFSDM_FLTCR1_JEXTSEL_Msk        (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos)   /*!< 0x00001F00 */
+#define DFSDM_FLTCR1_JEXTSEL            DFSDM_FLTCR1_JEXTSEL_Msk               /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */
+#define DFSDM_FLTCR1_JEXTSEL_0          (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000100 */
+#define DFSDM_FLTCR1_JEXTSEL_1          (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000200 */
+#define DFSDM_FLTCR1_JEXTSEL_2          (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000400 */
+#define DFSDM_FLTCR1_JEXTSEL_3          (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000800 */
+#define DFSDM_FLTCR1_JEXTSEL_4          (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00001000 */
+
+#define DFSDM_FLTCR1_JDMAEN_Pos         (5U)
+#define DFSDM_FLTCR1_JDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos)     /*!< 0x00000020 */
+#define DFSDM_FLTCR1_JDMAEN             DFSDM_FLTCR1_JDMAEN_Msk                /*!< DMA channel enabled to read data for the injected channel group */
+#define DFSDM_FLTCR1_JSCAN_Pos          (4U)
+#define DFSDM_FLTCR1_JSCAN_Msk          (0x1UL << DFSDM_FLTCR1_JSCAN_Pos)      /*!< 0x00000010 */
+#define DFSDM_FLTCR1_JSCAN              DFSDM_FLTCR1_JSCAN_Msk                 /*!< Scanning conversion in continuous mode selection for injected conversions */
+#define DFSDM_FLTCR1_JSYNC_Pos          (3U)
+#define DFSDM_FLTCR1_JSYNC_Msk          (0x1UL << DFSDM_FLTCR1_JSYNC_Pos)      /*!< 0x00000008 */
+#define DFSDM_FLTCR1_JSYNC              DFSDM_FLTCR1_JSYNC_Msk                 /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */
+#define DFSDM_FLTCR1_JSWSTART_Pos       (1U)
+#define DFSDM_FLTCR1_JSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos)   /*!< 0x00000002 */
+#define DFSDM_FLTCR1_JSWSTART           DFSDM_FLTCR1_JSWSTART_Msk              /*!< Start the conversion of the injected group of channels */
+#define DFSDM_FLTCR1_DFEN_Pos           (0U)
+#define DFSDM_FLTCR1_DFEN_Msk           (0x1UL << DFSDM_FLTCR1_DFEN_Pos)       /*!< 0x00000001 */
+#define DFSDM_FLTCR1_DFEN               DFSDM_FLTCR1_DFEN_Msk                  /*!< DFSDM enable */
+
+/********************  Bit definition for DFSDM_FLTCR2 register *******************/
+#define DFSDM_FLTCR2_AWDCH_Pos          (16U)
+#define DFSDM_FLTCR2_AWDCH_Msk          (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos)     /*!< 0x00FF0000 */
+#define DFSDM_FLTCR2_AWDCH              DFSDM_FLTCR2_AWDCH_Msk                 /*!< AWDCH[7:0] Analog watchdog channel selection */
+#define DFSDM_FLTCR2_EXCH_Pos           (8U)
+#define DFSDM_FLTCR2_EXCH_Msk           (0xFFUL << DFSDM_FLTCR2_EXCH_Pos)      /*!< 0x0000FF00 */
+#define DFSDM_FLTCR2_EXCH               DFSDM_FLTCR2_EXCH_Msk                  /*!< EXCH[7:0] Extreme detector channel selection */
+#define DFSDM_FLTCR2_CKABIE_Pos         (6U)
+#define DFSDM_FLTCR2_CKABIE_Msk         (0x1UL << DFSDM_FLTCR2_CKABIE_Pos)     /*!< 0x00000040 */
+#define DFSDM_FLTCR2_CKABIE             DFSDM_FLTCR2_CKABIE_Msk                /*!< Clock absence interrupt enable */
+#define DFSDM_FLTCR2_SCDIE_Pos          (5U)
+#define DFSDM_FLTCR2_SCDIE_Msk          (0x1UL << DFSDM_FLTCR2_SCDIE_Pos)      /*!< 0x00000020 */
+#define DFSDM_FLTCR2_SCDIE              DFSDM_FLTCR2_SCDIE_Msk                 /*!< Short circuit detector interrupt enable */
+#define DFSDM_FLTCR2_AWDIE_Pos          (4U)
+#define DFSDM_FLTCR2_AWDIE_Msk          (0x1UL << DFSDM_FLTCR2_AWDIE_Pos)      /*!< 0x00000010 */
+#define DFSDM_FLTCR2_AWDIE              DFSDM_FLTCR2_AWDIE_Msk                 /*!< Analog watchdog interrupt enable */
+#define DFSDM_FLTCR2_ROVRIE_Pos         (3U)
+#define DFSDM_FLTCR2_ROVRIE_Msk         (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos)     /*!< 0x00000008 */
+#define DFSDM_FLTCR2_ROVRIE             DFSDM_FLTCR2_ROVRIE_Msk                /*!< Regular data overrun interrupt enable */
+#define DFSDM_FLTCR2_JOVRIE_Pos         (2U)
+#define DFSDM_FLTCR2_JOVRIE_Msk         (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos)     /*!< 0x00000004 */
+#define DFSDM_FLTCR2_JOVRIE             DFSDM_FLTCR2_JOVRIE_Msk                /*!< Injected data overrun interrupt enable */
+#define DFSDM_FLTCR2_REOCIE_Pos         (1U)
+#define DFSDM_FLTCR2_REOCIE_Msk         (0x1UL << DFSDM_FLTCR2_REOCIE_Pos)     /*!< 0x00000002 */
+#define DFSDM_FLTCR2_REOCIE             DFSDM_FLTCR2_REOCIE_Msk                /*!< Regular end of conversion interrupt enable */
+#define DFSDM_FLTCR2_JEOCIE_Pos         (0U)
+#define DFSDM_FLTCR2_JEOCIE_Msk         (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos)     /*!< 0x00000001 */
+#define DFSDM_FLTCR2_JEOCIE             DFSDM_FLTCR2_JEOCIE_Msk                /*!< Injected end of conversion interrupt enable */
+
+/********************  Bit definition for DFSDM_FLTISR register *******************/
+#define DFSDM_FLTISR_SCDF_Pos           (24U)
+#define DFSDM_FLTISR_SCDF_Msk           (0xFFUL << DFSDM_FLTISR_SCDF_Pos)      /*!< 0xFF000000 */
+#define DFSDM_FLTISR_SCDF               DFSDM_FLTISR_SCDF_Msk                  /*!< SCDF[7:0] Short circuit detector flag */
+#define DFSDM_FLTISR_CKABF_Pos          (16U)
+#define DFSDM_FLTISR_CKABF_Msk          (0xFFUL << DFSDM_FLTISR_CKABF_Pos)     /*!< 0x00FF0000 */
+#define DFSDM_FLTISR_CKABF              DFSDM_FLTISR_CKABF_Msk                 /*!< CKABF[7:0] Clock absence flag */
+#define DFSDM_FLTISR_RCIP_Pos           (14U)
+#define DFSDM_FLTISR_RCIP_Msk           (0x1UL << DFSDM_FLTISR_RCIP_Pos)       /*!< 0x00004000 */
+#define DFSDM_FLTISR_RCIP               DFSDM_FLTISR_RCIP_Msk                  /*!< Regular conversion in progress status */
+#define DFSDM_FLTISR_JCIP_Pos           (13U)
+#define DFSDM_FLTISR_JCIP_Msk           (0x1UL << DFSDM_FLTISR_JCIP_Pos)       /*!< 0x00002000 */
+#define DFSDM_FLTISR_JCIP               DFSDM_FLTISR_JCIP_Msk                  /*!< Injected conversion in progress status */
+#define DFSDM_FLTISR_AWDF_Pos           (4U)
+#define DFSDM_FLTISR_AWDF_Msk           (0x1UL << DFSDM_FLTISR_AWDF_Pos)       /*!< 0x00000010 */
+#define DFSDM_FLTISR_AWDF               DFSDM_FLTISR_AWDF_Msk                  /*!< Analog watchdog */
+#define DFSDM_FLTISR_ROVRF_Pos          (3U)
+#define DFSDM_FLTISR_ROVRF_Msk          (0x1UL << DFSDM_FLTISR_ROVRF_Pos)      /*!< 0x00000008 */
+#define DFSDM_FLTISR_ROVRF              DFSDM_FLTISR_ROVRF_Msk                 /*!< Regular conversion overrun flag */
+#define DFSDM_FLTISR_JOVRF_Pos          (2U)
+#define DFSDM_FLTISR_JOVRF_Msk          (0x1UL << DFSDM_FLTISR_JOVRF_Pos)      /*!< 0x00000004 */
+#define DFSDM_FLTISR_JOVRF              DFSDM_FLTISR_JOVRF_Msk                 /*!< Injected conversion overrun flag */
+#define DFSDM_FLTISR_REOCF_Pos          (1U)
+#define DFSDM_FLTISR_REOCF_Msk          (0x1UL << DFSDM_FLTISR_REOCF_Pos)      /*!< 0x00000002 */
+#define DFSDM_FLTISR_REOCF              DFSDM_FLTISR_REOCF_Msk                 /*!< End of regular conversion flag */
+#define DFSDM_FLTISR_JEOCF_Pos          (0U)
+#define DFSDM_FLTISR_JEOCF_Msk          (0x1UL << DFSDM_FLTISR_JEOCF_Pos)      /*!< 0x00000001 */
+#define DFSDM_FLTISR_JEOCF              DFSDM_FLTISR_JEOCF_Msk                 /*!< End of injected conversion flag */
+
+/********************  Bit definition for DFSDM_FLTICR register *******************/
+#define DFSDM_FLTICR_CLRSCDF_Pos        (24U)
+#define DFSDM_FLTICR_CLRSCDF_Msk        (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos)   /*!< 0xFF000000 */
+#define DFSDM_FLTICR_CLRSCDF            DFSDM_FLTICR_CLRSCDF_Msk               /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
+#define DFSDM_FLTICR_CLRCKABF_Pos       (16U)
+#define DFSDM_FLTICR_CLRCKABF_Msk       (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos)  /*!< 0x00FF0000 */
+#define DFSDM_FLTICR_CLRCKABF           DFSDM_FLTICR_CLRCKABF_Msk              /*!< CLRCKABF[7:0] Clear the clock absence flag */
+#define DFSDM_FLTICR_CLRROVRF_Pos       (3U)
+#define DFSDM_FLTICR_CLRROVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos)   /*!< 0x00000008 */
+#define DFSDM_FLTICR_CLRROVRF           DFSDM_FLTICR_CLRROVRF_Msk              /*!< Clear the regular conversion overrun flag */
+#define DFSDM_FLTICR_CLRJOVRF_Pos       (2U)
+#define DFSDM_FLTICR_CLRJOVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos)   /*!< 0x00000004 */
+#define DFSDM_FLTICR_CLRJOVRF           DFSDM_FLTICR_CLRJOVRF_Msk              /*!< Clear the injected conversion overrun flag */
+
+/*******************  Bit definition for DFSDM_FLTJCHGR register ******************/
+#define DFSDM_FLTJCHGR_JCHG_Pos         (0U)
+#define DFSDM_FLTJCHGR_JCHG_Msk         (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos)    /*!< 0x000000FF */
+#define DFSDM_FLTJCHGR_JCHG             DFSDM_FLTJCHGR_JCHG_Msk                /*!< JCHG[7:0] Injected channel group selection */
+
+/********************  Bit definition for DFSDM_FLTFCR register *******************/
+#define DFSDM_FLTFCR_FORD_Pos           (29U)
+#define DFSDM_FLTFCR_FORD_Msk           (0x7UL << DFSDM_FLTFCR_FORD_Pos)       /*!< 0xE0000000 */
+#define DFSDM_FLTFCR_FORD               DFSDM_FLTFCR_FORD_Msk                  /*!< FORD[2:0] Sinc filter order */
+#define DFSDM_FLTFCR_FORD_2             (0x4UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x80000000 */
+#define DFSDM_FLTFCR_FORD_1             (0x2UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x40000000 */
+#define DFSDM_FLTFCR_FORD_0             (0x1UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x20000000 */
+#define DFSDM_FLTFCR_FOSR_Pos           (16U)
+#define DFSDM_FLTFCR_FOSR_Msk           (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos)     /*!< 0x03FF0000 */
+#define DFSDM_FLTFCR_FOSR               DFSDM_FLTFCR_FOSR_Msk                  /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
+#define DFSDM_FLTFCR_IOSR_Pos           (0U)
+#define DFSDM_FLTFCR_IOSR_Msk           (0xFFUL << DFSDM_FLTFCR_IOSR_Pos)      /*!< 0x000000FF */
+#define DFSDM_FLTFCR_IOSR               DFSDM_FLTFCR_IOSR_Msk                  /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
+
+/******************  Bit definition for DFSDM_FLTJDATAR register *****************/
+#define DFSDM_FLTJDATAR_JDATA_Pos       (8U)
+#define DFSDM_FLTJDATAR_JDATA_Msk       (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTJDATAR_JDATA           DFSDM_FLTJDATAR_JDATA_Msk              /*!< JDATA[23:0] Injected group conversion data */
+#define DFSDM_FLTJDATAR_JDATACH_Pos     (0U)
+#define DFSDM_FLTJDATAR_JDATACH_Msk     (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */
+#define DFSDM_FLTJDATAR_JDATACH         DFSDM_FLTJDATAR_JDATACH_Msk            /*!< JDATACH[2:0] Injected channel most recently converted */
+
+/******************  Bit definition for DFSDM_FLTRDATAR register *****************/
+#define DFSDM_FLTRDATAR_RDATA_Pos       (8U)
+#define DFSDM_FLTRDATAR_RDATA_Msk       (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTRDATAR_RDATA           DFSDM_FLTRDATAR_RDATA_Msk              /*!< RDATA[23:0] Regular channel conversion data */
+#define DFSDM_FLTRDATAR_RPEND_Pos       (4U)
+#define DFSDM_FLTRDATAR_RPEND_Msk       (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos)   /*!< 0x00000010 */
+#define DFSDM_FLTRDATAR_RPEND           DFSDM_FLTRDATAR_RPEND_Msk              /*!< RPEND Regular channel pending data */
+#define DFSDM_FLTRDATAR_RDATACH_Pos     (0U)
+#define DFSDM_FLTRDATAR_RDATACH_Msk     (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */
+#define DFSDM_FLTRDATAR_RDATACH         DFSDM_FLTRDATAR_RDATACH_Msk            /*!< RDATACH[2:0] Regular channel most recently converted */
+
+/******************  Bit definition for DFSDM_FLTAWHTR register ******************/
+#define DFSDM_FLTAWHTR_AWHT_Pos         (8U)
+#define DFSDM_FLTAWHTR_AWHT_Msk         (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTAWHTR_AWHT             DFSDM_FLTAWHTR_AWHT_Msk                /*!< AWHT[23:0] Analog watchdog high threshold */
+#define DFSDM_FLTAWHTR_BKAWH_Pos        (0U)
+#define DFSDM_FLTAWHTR_BKAWH_Msk        (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)    /*!< 0x0000000F */
+#define DFSDM_FLTAWHTR_BKAWH            DFSDM_FLTAWHTR_BKAWH_Msk               /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
+
+/******************  Bit definition for DFSDM_FLTAWLTR register ******************/
+#define DFSDM_FLTAWLTR_AWLT_Pos         (8U)
+#define DFSDM_FLTAWLTR_AWLT_Msk         (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTAWLTR_AWLT             DFSDM_FLTAWLTR_AWLT_Msk                /*!< AWHT[23:0] Analog watchdog low threshold */
+#define DFSDM_FLTAWLTR_BKAWL_Pos        (0U)
+#define DFSDM_FLTAWLTR_BKAWL_Msk        (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos)    /*!< 0x0000000F */
+#define DFSDM_FLTAWLTR_BKAWL            DFSDM_FLTAWLTR_BKAWL_Msk               /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
+
+/******************  Bit definition for DFSDM_FLTAWSR register ******************/
+#define DFSDM_FLTAWSR_AWHTF_Pos         (8U)
+#define DFSDM_FLTAWSR_AWHTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos)    /*!< 0x0000FF00 */
+#define DFSDM_FLTAWSR_AWHTF             DFSDM_FLTAWSR_AWHTF_Msk                /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
+#define DFSDM_FLTAWSR_AWLTF_Pos         (0U)
+#define DFSDM_FLTAWSR_AWLTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos)    /*!< 0x000000FF */
+#define DFSDM_FLTAWSR_AWLTF             DFSDM_FLTAWSR_AWLTF_Msk                /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
+
+/******************  Bit definition for DFSDM_FLTAWCFR) register *****************/
+#define DFSDM_FLTAWCFR_CLRAWHTF_Pos     (8U)
+#define DFSDM_FLTAWCFR_CLRAWHTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */
+#define DFSDM_FLTAWCFR_CLRAWHTF         DFSDM_FLTAWCFR_CLRAWHTF_Msk            /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
+#define DFSDM_FLTAWCFR_CLRAWLTF_Pos     (0U)
+#define DFSDM_FLTAWCFR_CLRAWLTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */
+#define DFSDM_FLTAWCFR_CLRAWLTF         DFSDM_FLTAWCFR_CLRAWLTF_Msk            /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
+
+/******************  Bit definition for DFSDM_FLTEXMAX register ******************/
+#define DFSDM_FLTEXMAX_EXMAX_Pos        (8U)
+#define DFSDM_FLTEXMAX_EXMAX_Msk        (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTEXMAX_EXMAX            DFSDM_FLTEXMAX_EXMAX_Msk               /*!< EXMAX[23:0] Extreme detector maximum value */
+#define DFSDM_FLTEXMAX_EXMAXCH_Pos      (0U)
+#define DFSDM_FLTEXMAX_EXMAXCH_Msk      (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos)  /*!< 0x00000007 */
+#define DFSDM_FLTEXMAX_EXMAXCH          DFSDM_FLTEXMAX_EXMAXCH_Msk             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
+
+/******************  Bit definition for DFSDM_FLTEXMIN register ******************/
+#define DFSDM_FLTEXMIN_EXMIN_Pos        (8U)
+#define DFSDM_FLTEXMIN_EXMIN_Msk        (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTEXMIN_EXMIN            DFSDM_FLTEXMIN_EXMIN_Msk               /*!< EXMIN[23:0] Extreme detector minimum value */
+#define DFSDM_FLTEXMIN_EXMINCH_Pos      (0U)
+#define DFSDM_FLTEXMIN_EXMINCH_Msk      (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos)  /*!< 0x00000007 */
+#define DFSDM_FLTEXMIN_EXMINCH          DFSDM_FLTEXMIN_EXMINCH_Msk             /*!< EXMINCH[2:0] Extreme detector minimum data channel */
+
+/******************  Bit definition for DFSDM_FLTCNVTIMR register ******************/
+#define DFSDM_FLTCNVTIMR_CNVCNT_Pos     (4U)
+#define DFSDM_FLTCNVTIMR_CNVCNT_Msk     (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */
+#define DFSDM_FLTCNVTIMR_CNVCNT         DFSDM_FLTCNVTIMR_CNVCNT_Msk            /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           BDMA Controller                                  */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for BDMA_ISR register  ********************/
+#define BDMA_ISR_GIF0_Pos       (0U)
+#define BDMA_ISR_GIF0_Msk       (0x1UL << BDMA_ISR_GIF0_Pos)                   /*!< 0x00000001 */
+#define BDMA_ISR_GIF0           BDMA_ISR_GIF0_Msk                              /*!< Channel 0 Global interrupt flag */
+#define BDMA_ISR_TCIF0_Pos      (1U)
+#define BDMA_ISR_TCIF0_Msk      (0x1UL << BDMA_ISR_TCIF0_Pos)                  /*!< 0x00000002 */
+#define BDMA_ISR_TCIF0          BDMA_ISR_TCIF0_Msk                             /*!< Channel 0 Transfer Complete flag */
+#define BDMA_ISR_HTIF0_Pos      (2U)
+#define BDMA_ISR_HTIF0_Msk      (0x1UL << BDMA_ISR_HTIF0_Pos)                  /*!< 0x00000004 */
+#define BDMA_ISR_HTIF0          BDMA_ISR_HTIF0_Msk                             /*!< Channel 0 Half Transfer flag */
+#define BDMA_ISR_TEIF0_Pos      (3U)
+#define BDMA_ISR_TEIF0_Msk      (0x1UL << BDMA_ISR_TEIF0_Pos)                  /*!< 0x00000008 */
+#define BDMA_ISR_TEIF0          BDMA_ISR_TEIF0_Msk                             /*!< Channel 0 Transfer Error flag */
+#define BDMA_ISR_GIF1_Pos       (4U)
+#define BDMA_ISR_GIF1_Msk       (0x1UL << BDMA_ISR_GIF1_Pos)                   /*!< 0x00000010 */
+#define BDMA_ISR_GIF1           BDMA_ISR_GIF1_Msk                              /*!< Channel 1 Global interrupt flag */
+#define BDMA_ISR_TCIF1_Pos      (5U)
+#define BDMA_ISR_TCIF1_Msk      (0x1UL << BDMA_ISR_TCIF1_Pos)                  /*!< 0x00000020 */
+#define BDMA_ISR_TCIF1          BDMA_ISR_TCIF1_Msk                             /*!< Channel 1 Transfer Complete flag */
+#define BDMA_ISR_HTIF1_Pos      (6U)
+#define BDMA_ISR_HTIF1_Msk      (0x1UL << BDMA_ISR_HTIF1_Pos)                  /*!< 0x00000040 */
+#define BDMA_ISR_HTIF1          BDMA_ISR_HTIF1_Msk                             /*!< Channel 1 Half Transfer flag */
+#define BDMA_ISR_TEIF1_Pos      (7U)
+#define BDMA_ISR_TEIF1_Msk      (0x1UL << BDMA_ISR_TEIF1_Pos)                  /*!< 0x00000080 */
+#define BDMA_ISR_TEIF1          BDMA_ISR_TEIF1_Msk                             /*!< Channel 1 Transfer Error flag */
+#define BDMA_ISR_GIF2_Pos       (8U)
+#define BDMA_ISR_GIF2_Msk       (0x1UL << BDMA_ISR_GIF2_Pos)                   /*!< 0x00000100 */
+#define BDMA_ISR_GIF2           BDMA_ISR_GIF2_Msk                              /*!< Channel 2 Global interrupt flag */
+#define BDMA_ISR_TCIF2_Pos      (9U)
+#define BDMA_ISR_TCIF2_Msk      (0x1UL << BDMA_ISR_TCIF2_Pos)                  /*!< 0x00000200 */
+#define BDMA_ISR_TCIF2          BDMA_ISR_TCIF2_Msk                             /*!< Channel 2 Transfer Complete flag */
+#define BDMA_ISR_HTIF2_Pos      (10U)
+#define BDMA_ISR_HTIF2_Msk      (0x1UL << BDMA_ISR_HTIF2_Pos)                  /*!< 0x00000400 */
+#define BDMA_ISR_HTIF2          BDMA_ISR_HTIF2_Msk                             /*!< Channel 2 Half Transfer flag */
+#define BDMA_ISR_TEIF2_Pos      (11U)
+#define BDMA_ISR_TEIF2_Msk      (0x1UL << BDMA_ISR_TEIF2_Pos)                  /*!< 0x00000800 */
+#define BDMA_ISR_TEIF2          BDMA_ISR_TEIF2_Msk                             /*!< Channel 2 Transfer Error flag */
+#define BDMA_ISR_GIF3_Pos       (12U)
+#define BDMA_ISR_GIF3_Msk       (0x1UL << BDMA_ISR_GIF3_Pos)                   /*!< 0x00001000 */
+#define BDMA_ISR_GIF3           BDMA_ISR_GIF3_Msk                              /*!< Channel 3 Global interrupt flag */
+#define BDMA_ISR_TCIF3_Pos      (13U)
+#define BDMA_ISR_TCIF3_Msk      (0x1UL << BDMA_ISR_TCIF3_Pos)                  /*!< 0x00002000 */
+#define BDMA_ISR_TCIF3          BDMA_ISR_TCIF3_Msk                             /*!< Channel 3 Transfer Complete flag */
+#define BDMA_ISR_HTIF3_Pos      (14U)
+#define BDMA_ISR_HTIF3_Msk      (0x1UL << BDMA_ISR_HTIF3_Pos)                  /*!< 0x00004000 */
+#define BDMA_ISR_HTIF3          BDMA_ISR_HTIF3_Msk                             /*!< Channel 3 Half Transfer flag */
+#define BDMA_ISR_TEIF3_Pos      (15U)
+#define BDMA_ISR_TEIF3_Msk      (0x1UL << BDMA_ISR_TEIF3_Pos)                  /*!< 0x00008000 */
+#define BDMA_ISR_TEIF3          BDMA_ISR_TEIF3_Msk                             /*!< Channel 3 Transfer Error flag */
+#define BDMA_ISR_GIF4_Pos       (16U)
+#define BDMA_ISR_GIF4_Msk       (0x1UL << BDMA_ISR_GIF4_Pos)                   /*!< 0x00010000 */
+#define BDMA_ISR_GIF4           BDMA_ISR_GIF4_Msk                              /*!< Channel 4 Global interrupt flag */
+#define BDMA_ISR_TCIF4_Pos      (17U)
+#define BDMA_ISR_TCIF4_Msk      (0x1UL << BDMA_ISR_TCIF4_Pos)                  /*!< 0x00020000 */
+#define BDMA_ISR_TCIF4          BDMA_ISR_TCIF4_Msk                             /*!< Channel 4 Transfer Complete flag */
+#define BDMA_ISR_HTIF4_Pos      (18U)
+#define BDMA_ISR_HTIF4_Msk      (0x1UL << BDMA_ISR_HTIF4_Pos)                  /*!< 0x00040000 */
+#define BDMA_ISR_HTIF4          BDMA_ISR_HTIF4_Msk                             /*!< Channel 4 Half Transfer flag */
+#define BDMA_ISR_TEIF4_Pos      (19U)
+#define BDMA_ISR_TEIF4_Msk      (0x1UL << BDMA_ISR_TEIF4_Pos)                  /*!< 0x00080000 */
+#define BDMA_ISR_TEIF4          BDMA_ISR_TEIF4_Msk                             /*!< Channel 4 Transfer Error flag */
+#define BDMA_ISR_GIF5_Pos       (20U)
+#define BDMA_ISR_GIF5_Msk       (0x1UL << BDMA_ISR_GIF5_Pos)                   /*!< 0x00100000 */
+#define BDMA_ISR_GIF5           BDMA_ISR_GIF5_Msk                              /*!< Channel 5 Global interrupt flag */
+#define BDMA_ISR_TCIF5_Pos      (21U)
+#define BDMA_ISR_TCIF5_Msk      (0x1UL << BDMA_ISR_TCIF5_Pos)                  /*!< 0x00200000 */
+#define BDMA_ISR_TCIF5          BDMA_ISR_TCIF5_Msk                             /*!< Channel 5 Transfer Complete flag */
+#define BDMA_ISR_HTIF5_Pos      (22U)
+#define BDMA_ISR_HTIF5_Msk      (0x1UL << BDMA_ISR_HTIF5_Pos)                  /*!< 0x00400000 */
+#define BDMA_ISR_HTIF5          BDMA_ISR_HTIF5_Msk                             /*!< Channel 5 Half Transfer flag */
+#define BDMA_ISR_TEIF5_Pos      (23U)
+#define BDMA_ISR_TEIF5_Msk      (0x1UL << BDMA_ISR_TEIF5_Pos)                  /*!< 0x00800000 */
+#define BDMA_ISR_TEIF5          BDMA_ISR_TEIF5_Msk                             /*!< Channel 5 Transfer Error flag */
+#define BDMA_ISR_GIF6_Pos       (24U)
+#define BDMA_ISR_GIF6_Msk       (0x1UL << BDMA_ISR_GIF6_Pos)                   /*!< 0x01000000 */
+#define BDMA_ISR_GIF6           BDMA_ISR_GIF6_Msk                              /*!< Channel 6 Global interrupt flag */
+#define BDMA_ISR_TCIF6_Pos      (25U)
+#define BDMA_ISR_TCIF6_Msk      (0x1UL << BDMA_ISR_TCIF6_Pos)                  /*!< 0x02000000 */
+#define BDMA_ISR_TCIF6          BDMA_ISR_TCIF6_Msk                             /*!< Channel 6 Transfer Complete flag */
+#define BDMA_ISR_HTIF6_Pos      (26U)
+#define BDMA_ISR_HTIF6_Msk      (0x1UL << BDMA_ISR_HTIF6_Pos)                  /*!< 0x04000000 */
+#define BDMA_ISR_HTIF6          BDMA_ISR_HTIF6_Msk                             /*!< Channel 6 Half Transfer flag */
+#define BDMA_ISR_TEIF6_Pos      (27U)
+#define BDMA_ISR_TEIF6_Msk      (0x1UL << BDMA_ISR_TEIF6_Pos)                  /*!< 0x08000000 */
+#define BDMA_ISR_TEIF6          BDMA_ISR_TEIF6_Msk                             /*!< Channel 6 Transfer Error flag */
+#define BDMA_ISR_GIF7_Pos       (28U)
+#define BDMA_ISR_GIF7_Msk       (0x1UL << BDMA_ISR_GIF7_Pos)                   /*!< 0x10000000 */
+#define BDMA_ISR_GIF7           BDMA_ISR_GIF7_Msk                              /*!< Channel 7 Global interrupt flag */
+#define BDMA_ISR_TCIF7_Pos      (29U)
+#define BDMA_ISR_TCIF7_Msk      (0x1UL << BDMA_ISR_TCIF7_Pos)                  /*!< 0x20000000 */
+#define BDMA_ISR_TCIF7          BDMA_ISR_TCIF7_Msk                             /*!< Channel 7 Transfer Complete flag */
+#define BDMA_ISR_HTIF7_Pos      (30U)
+#define BDMA_ISR_HTIF7_Msk      (0x1UL << BDMA_ISR_HTIF7_Pos)                  /*!< 0x40000000 */
+#define BDMA_ISR_HTIF7          BDMA_ISR_HTIF7_Msk                             /*!< Channel 7 Half Transfer flag */
+#define BDMA_ISR_TEIF7_Pos      (31U)
+#define BDMA_ISR_TEIF7_Msk      (0x1UL << BDMA_ISR_TEIF7_Pos)                  /*!< 0x80000000 */
+#define BDMA_ISR_TEIF7          BDMA_ISR_TEIF7_Msk                             /*!< Channel 7 Transfer Error flag */
+
+/*******************  Bit definition for BDMA_IFCR register  *******************/
+#define BDMA_IFCR_CGIF0_Pos     (0U)
+#define BDMA_IFCR_CGIF0_Msk     (0x1UL << BDMA_IFCR_CGIF0_Pos)                 /*!< 0x00000001 */
+#define BDMA_IFCR_CGIF0         BDMA_IFCR_CGIF0_Msk                            /*!< Channel 0 Global interrupt clearr */
+#define BDMA_IFCR_CTCIF0_Pos    (1U)
+#define BDMA_IFCR_CTCIF0_Msk    (0x1UL << BDMA_IFCR_CTCIF0_Pos)                /*!< 0x00000002 */
+#define BDMA_IFCR_CTCIF0        BDMA_IFCR_CTCIF0_Msk                           /*!< Channel 0 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF0_Pos    (2U)
+#define BDMA_IFCR_CHTIF0_Msk    (0x1UL << BDMA_IFCR_CHTIF0_Pos)                /*!< 0x00000004 */
+#define BDMA_IFCR_CHTIF0        BDMA_IFCR_CHTIF0_Msk                           /*!< Channel 0 Half Transfer clear */
+#define BDMA_IFCR_CTEIF0_Pos    (3U)
+#define BDMA_IFCR_CTEIF0_Msk    (0x1UL << BDMA_IFCR_CTEIF0_Pos)                /*!< 0x00000008 */
+#define BDMA_IFCR_CTEIF0        BDMA_IFCR_CTEIF0_Msk                           /*!< Channel 0 Transfer Error clear */
+#define BDMA_IFCR_CGIF1_Pos     (4U)
+#define BDMA_IFCR_CGIF1_Msk     (0x1UL << BDMA_IFCR_CGIF1_Pos)                 /*!< 0x00000010 */
+#define BDMA_IFCR_CGIF1         BDMA_IFCR_CGIF1_Msk                            /*!< Channel 1 Global interrupt clear */
+#define BDMA_IFCR_CTCIF1_Pos    (5U)
+#define BDMA_IFCR_CTCIF1_Msk    (0x1UL << BDMA_IFCR_CTCIF1_Pos)                /*!< 0x00000020 */
+#define BDMA_IFCR_CTCIF1        BDMA_IFCR_CTCIF1_Msk                           /*!< Channel 1 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF1_Pos    (6U)
+#define BDMA_IFCR_CHTIF1_Msk    (0x1UL << BDMA_IFCR_CHTIF1_Pos)                /*!< 0x00000040 */
+#define BDMA_IFCR_CHTIF1        BDMA_IFCR_CHTIF1_Msk                           /*!< Channel 1 Half Transfer clear */
+#define BDMA_IFCR_CTEIF1_Pos    (7U)
+#define BDMA_IFCR_CTEIF1_Msk    (0x1UL << BDMA_IFCR_CTEIF1_Pos)                /*!< 0x00000080 */
+#define BDMA_IFCR_CTEIF1        BDMA_IFCR_CTEIF1_Msk                           /*!< Channel 1 Transfer Error clear */
+#define BDMA_IFCR_CGIF2_Pos     (8U)
+#define BDMA_IFCR_CGIF2_Msk     (0x1UL << BDMA_IFCR_CGIF2_Pos)                 /*!< 0x00000100 */
+#define BDMA_IFCR_CGIF2         BDMA_IFCR_CGIF2_Msk                            /*!< Channel 2 Global interrupt clear */
+#define BDMA_IFCR_CTCIF2_Pos    (9U)
+#define BDMA_IFCR_CTCIF2_Msk    (0x1UL << BDMA_IFCR_CTCIF2_Pos)                /*!< 0x00000200 */
+#define BDMA_IFCR_CTCIF2        BDMA_IFCR_CTCIF2_Msk                           /*!< Channel 2 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF2_Pos    (10U)
+#define BDMA_IFCR_CHTIF2_Msk    (0x1UL << BDMA_IFCR_CHTIF2_Pos)                /*!< 0x00000400 */
+#define BDMA_IFCR_CHTIF2        BDMA_IFCR_CHTIF2_Msk                           /*!< Channel 2 Half Transfer clear */
+#define BDMA_IFCR_CTEIF2_Pos    (11U)
+#define BDMA_IFCR_CTEIF2_Msk    (0x1UL << BDMA_IFCR_CTEIF2_Pos)                /*!< 0x00000800 */
+#define BDMA_IFCR_CTEIF2        BDMA_IFCR_CTEIF2_Msk                           /*!< Channel 2 Transfer Error clear */
+#define BDMA_IFCR_CGIF3_Pos     (12U)
+#define BDMA_IFCR_CGIF3_Msk     (0x1UL << BDMA_IFCR_CGIF3_Pos)                 /*!< 0x00001000 */
+#define BDMA_IFCR_CGIF3         BDMA_IFCR_CGIF3_Msk                            /*!< Channel 3 Global interrupt clear */
+#define BDMA_IFCR_CTCIF3_Pos    (13U)
+#define BDMA_IFCR_CTCIF3_Msk    (0x1UL << BDMA_IFCR_CTCIF3_Pos)                /*!< 0x00002000 */
+#define BDMA_IFCR_CTCIF3        BDMA_IFCR_CTCIF3_Msk                           /*!< Channel 3 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF3_Pos    (14U)
+#define BDMA_IFCR_CHTIF3_Msk    (0x1UL << BDMA_IFCR_CHTIF3_Pos)                /*!< 0x00004000 */
+#define BDMA_IFCR_CHTIF3        BDMA_IFCR_CHTIF3_Msk                           /*!< Channel 3 Half Transfer clear */
+#define BDMA_IFCR_CTEIF3_Pos    (15U)
+#define BDMA_IFCR_CTEIF3_Msk    (0x1UL << BDMA_IFCR_CTEIF3_Pos)                /*!< 0x00008000 */
+#define BDMA_IFCR_CTEIF3        BDMA_IFCR_CTEIF3_Msk                           /*!< Channel 3 Transfer Error clear */
+#define BDMA_IFCR_CGIF4_Pos     (16U)
+#define BDMA_IFCR_CGIF4_Msk     (0x1UL << BDMA_IFCR_CGIF4_Pos)                 /*!< 0x00010000 */
+#define BDMA_IFCR_CGIF4         BDMA_IFCR_CGIF4_Msk                            /*!< Channel 4 Global interrupt clear */
+#define BDMA_IFCR_CTCIF4_Pos    (17U)
+#define BDMA_IFCR_CTCIF4_Msk    (0x1UL << BDMA_IFCR_CTCIF4_Pos)                /*!< 0x00020000 */
+#define BDMA_IFCR_CTCIF4        BDMA_IFCR_CTCIF4_Msk                           /*!< Channel 4 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF4_Pos    (18U)
+#define BDMA_IFCR_CHTIF4_Msk    (0x1UL << BDMA_IFCR_CHTIF4_Pos)                /*!< 0x00040000 */
+#define BDMA_IFCR_CHTIF4        BDMA_IFCR_CHTIF4_Msk                           /*!< Channel 4 Half Transfer clear */
+#define BDMA_IFCR_CTEIF4_Pos    (19U)
+#define BDMA_IFCR_CTEIF4_Msk    (0x1UL << BDMA_IFCR_CTEIF4_Pos)                /*!< 0x00080000 */
+#define BDMA_IFCR_CTEIF4        BDMA_IFCR_CTEIF4_Msk                           /*!< Channel 4 Transfer Error clear */
+#define BDMA_IFCR_CGIF5_Pos     (20U)
+#define BDMA_IFCR_CGIF5_Msk     (0x1UL << BDMA_IFCR_CGIF5_Pos)                 /*!< 0x00100000 */
+#define BDMA_IFCR_CGIF5         BDMA_IFCR_CGIF5_Msk                            /*!< Channel 5 Global interrupt clear */
+#define BDMA_IFCR_CTCIF5_Pos    (21U)
+#define BDMA_IFCR_CTCIF5_Msk    (0x1UL << BDMA_IFCR_CTCIF5_Pos)                /*!< 0x00200000 */
+#define BDMA_IFCR_CTCIF5        BDMA_IFCR_CTCIF5_Msk                           /*!< Channel 5 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF5_Pos    (22U)
+#define BDMA_IFCR_CHTIF5_Msk    (0x1UL << BDMA_IFCR_CHTIF5_Pos)                /*!< 0x00400000 */
+#define BDMA_IFCR_CHTIF5        BDMA_IFCR_CHTIF5_Msk                           /*!< Channel 5 Half Transfer clear */
+#define BDMA_IFCR_CTEIF5_Pos    (23U)
+#define BDMA_IFCR_CTEIF5_Msk    (0x1UL << BDMA_IFCR_CTEIF5_Pos)                /*!< 0x00800000 */
+#define BDMA_IFCR_CTEIF5        BDMA_IFCR_CTEIF5_Msk                           /*!< Channel 5 Transfer Error clear */
+#define BDMA_IFCR_CGIF6_Pos     (24U)
+#define BDMA_IFCR_CGIF6_Msk     (0x1UL << BDMA_IFCR_CGIF6_Pos)                 /*!< 0x01000000 */
+#define BDMA_IFCR_CGIF6         BDMA_IFCR_CGIF6_Msk                            /*!< Channel 6 Global interrupt clear */
+#define BDMA_IFCR_CTCIF6_Pos    (25U)
+#define BDMA_IFCR_CTCIF6_Msk    (0x1UL << BDMA_IFCR_CTCIF6_Pos)                /*!< 0x02000000 */
+#define BDMA_IFCR_CTCIF6        BDMA_IFCR_CTCIF6_Msk                           /*!< Channel 6 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF6_Pos    (26U)
+#define BDMA_IFCR_CHTIF6_Msk    (0x1UL << BDMA_IFCR_CHTIF6_Pos)                /*!< 0x04000000 */
+#define BDMA_IFCR_CHTIF6        BDMA_IFCR_CHTIF6_Msk                           /*!< Channel 6 Half Transfer clear */
+#define BDMA_IFCR_CTEIF6_Pos    (27U)
+#define BDMA_IFCR_CTEIF6_Msk    (0x1UL << BDMA_IFCR_CTEIF6_Pos)                /*!< 0x08000000 */
+#define BDMA_IFCR_CTEIF6        BDMA_IFCR_CTEIF6_Msk                           /*!< Channel 6 Transfer Error clear */
+#define BDMA_IFCR_CGIF7_Pos     (28U)
+#define BDMA_IFCR_CGIF7_Msk     (0x1UL << BDMA_IFCR_CGIF7_Pos)                 /*!< 0x10000000 */
+#define BDMA_IFCR_CGIF7         BDMA_IFCR_CGIF7_Msk                            /*!< Channel 7 Global interrupt clear */
+#define BDMA_IFCR_CTCIF7_Pos    (29U)
+#define BDMA_IFCR_CTCIF7_Msk    (0x1UL << BDMA_IFCR_CTCIF7_Pos)                /*!< 0x20000000 */
+#define BDMA_IFCR_CTCIF7        BDMA_IFCR_CTCIF7_Msk                           /*!< Channel 7 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF7_Pos    (30U)
+#define BDMA_IFCR_CHTIF7_Msk    (0x1UL << BDMA_IFCR_CHTIF7_Pos)                /*!< 0x40000000 */
+#define BDMA_IFCR_CHTIF7        BDMA_IFCR_CHTIF7_Msk                           /*!< Channel 7 Half Transfer clear */
+#define BDMA_IFCR_CTEIF7_Pos    (31U)
+#define BDMA_IFCR_CTEIF7_Msk    (0x1UL << BDMA_IFCR_CTEIF7_Pos)                /*!< 0x80000000 */
+#define BDMA_IFCR_CTEIF7        BDMA_IFCR_CTEIF7_Msk                           /*!< Channel 7 Transfer Error clear */
+
+/*******************  Bit definition for BDMA_CCR register  ********************/
+#define BDMA_CCR_EN_Pos         (0U)
+#define BDMA_CCR_EN_Msk         (0x1UL << BDMA_CCR_EN_Pos)                     /*!< 0x00000001 */
+#define BDMA_CCR_EN             BDMA_CCR_EN_Msk                                /*!< Channel enable                      */
+#define BDMA_CCR_TCIE_Pos       (1U)
+#define BDMA_CCR_TCIE_Msk       (0x1UL << BDMA_CCR_TCIE_Pos)                   /*!< 0x00000002 */
+#define BDMA_CCR_TCIE           BDMA_CCR_TCIE_Msk                              /*!< Transfer complete interrupt enable  */
+#define BDMA_CCR_HTIE_Pos       (2U)
+#define BDMA_CCR_HTIE_Msk       (0x1UL << BDMA_CCR_HTIE_Pos)                   /*!< 0x00000004 */
+#define BDMA_CCR_HTIE           BDMA_CCR_HTIE_Msk                              /*!< Half Transfer interrupt enable      */
+#define BDMA_CCR_TEIE_Pos       (3U)
+#define BDMA_CCR_TEIE_Msk       (0x1UL << BDMA_CCR_TEIE_Pos)                   /*!< 0x00000008 */
+#define BDMA_CCR_TEIE           BDMA_CCR_TEIE_Msk                              /*!< Transfer error interrupt enable     */
+#define BDMA_CCR_DIR_Pos        (4U)
+#define BDMA_CCR_DIR_Msk        (0x1UL << BDMA_CCR_DIR_Pos)                    /*!< 0x00000010 */
+#define BDMA_CCR_DIR            BDMA_CCR_DIR_Msk                               /*!< Data transfer direction             */
+#define BDMA_CCR_CIRC_Pos       (5U)
+#define BDMA_CCR_CIRC_Msk       (0x1UL << BDMA_CCR_CIRC_Pos)                   /*!< 0x00000020 */
+#define BDMA_CCR_CIRC           BDMA_CCR_CIRC_Msk                              /*!< Circular mode                       */
+#define BDMA_CCR_PINC_Pos       (6U)
+#define BDMA_CCR_PINC_Msk       (0x1UL << BDMA_CCR_PINC_Pos)                   /*!< 0x00000040 */
+#define BDMA_CCR_PINC           BDMA_CCR_PINC_Msk                              /*!< Peripheral increment mode           */
+#define BDMA_CCR_MINC_Pos       (7U)
+#define BDMA_CCR_MINC_Msk       (0x1UL << BDMA_CCR_MINC_Pos)                   /*!< 0x00000080 */
+#define BDMA_CCR_MINC           BDMA_CCR_MINC_Msk                              /*!< Memory increment mode               */
+
+#define BDMA_CCR_PSIZE_Pos      (8U)
+#define BDMA_CCR_PSIZE_Msk      (0x3UL << BDMA_CCR_PSIZE_Pos)                  /*!< 0x00000300 */
+#define BDMA_CCR_PSIZE          BDMA_CCR_PSIZE_Msk                             /*!< PSIZE[1:0] bits (Peripheral size)   */
+#define BDMA_CCR_PSIZE_0        (0x1UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000100 */
+#define BDMA_CCR_PSIZE_1        (0x2UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000200 */
+
+#define BDMA_CCR_MSIZE_Pos      (10U)
+#define BDMA_CCR_MSIZE_Msk      (0x3UL << BDMA_CCR_MSIZE_Pos)                  /*!< 0x00000C00 */
+#define BDMA_CCR_MSIZE          BDMA_CCR_MSIZE_Msk                             /*!< MSIZE[1:0] bits (Memory size)       */
+#define BDMA_CCR_MSIZE_0        (0x1UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000400 */
+#define BDMA_CCR_MSIZE_1        (0x2UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000800 */
+
+#define BDMA_CCR_PL_Pos         (12U)
+#define BDMA_CCR_PL_Msk         (0x3UL << BDMA_CCR_PL_Pos)                     /*!< 0x00003000 */
+#define BDMA_CCR_PL             BDMA_CCR_PL_Msk                                /*!< PL[1:0] bits(Channel Priority level)*/
+#define BDMA_CCR_PL_0           (0x1UL << BDMA_CCR_PL_Pos)                      /*!< 0x00001000 */
+#define BDMA_CCR_PL_1           (0x2UL << BDMA_CCR_PL_Pos)                      /*!< 0x00002000 */
+
+#define BDMA_CCR_MEM2MEM_Pos    (14U)
+#define BDMA_CCR_MEM2MEM_Msk    (0x1UL << BDMA_CCR_MEM2MEM_Pos)                /*!< 0x00004000 */
+#define BDMA_CCR_MEM2MEM        BDMA_CCR_MEM2MEM_Msk                           /*!< Memory to memory mode               */
+#define BDMA_CCR_DBM_Pos        (15U)
+#define BDMA_CCR_DBM_Msk        (0x1UL << BDMA_CCR_DBM_Pos)                    /*!< 0x0000A000 */
+#define BDMA_CCR_DBM            BDMA_CCR_DBM_Msk                               /*!< Memory to memory mode               */
+#define BDMA_CCR_CT_Pos         (16U)
+#define BDMA_CCR_CT_Msk         (0x1UL << BDMA_CCR_CT_Pos)                     /*!< 0x00010000 */
+#define BDMA_CCR_CT             BDMA_CCR_CT_Msk                                /*!< Memory to memory mode               */
+
+/******************  Bit definition for BDMA_CNDTR register  *******************/
+#define BDMA_CNDTR_NDT_Pos      (0U)
+#define BDMA_CNDTR_NDT_Msk      (0xFFFFUL << BDMA_CNDTR_NDT_Pos)               /*!< 0x0000FFFF */
+#define BDMA_CNDTR_NDT          BDMA_CNDTR_NDT_Msk                             /*!< Number of data to Transfer          */
+
+/******************  Bit definition for BDMA_CPAR register  ********************/
+#define BDMA_CPAR_PA_Pos        (0U)
+#define BDMA_CPAR_PA_Msk        (0xFFFFFFFFUL << BDMA_CPAR_PA_Pos)             /*!< 0xFFFFFFFF */
+#define BDMA_CPAR_PA            BDMA_CPAR_PA_Msk                               /*!< Peripheral Address                  */
+
+/******************  Bit definition for BDMA_CM0AR register  ********************/
+#define BDMA_CM0AR_MA_Pos        (0U)
+#define BDMA_CM0AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM0AR_MA_Pos)             /*!< 0xFFFFFFFF */
+#define BDMA_CM0AR_MA            BDMA_CM0AR_MA_Msk                               /*!< Memory Address                      */
+
+/******************  Bit definition for BDMA_CM1AR register  ********************/
+#define BDMA_CM1AR_MA_Pos        (0U)
+#define BDMA_CM1AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM1AR_MA_Pos)             /*!< 0xFFFFFFFF */
+#define BDMA_CM1AR_MA            BDMA_CM1AR_MA_Msk                               /*!< Memory Address                      */
+
+/******************************************************************************/
+/*                                                                            */
+/*                Ethernet MAC Registers bits definitions                     */
+/*                                                                            */
+/******************************************************************************/
+/* Bit definition for Ethernet MAC Configuration Register register */
+#define ETH_MACCR_ARP_Pos                             (31U)
+#define ETH_MACCR_ARP_Msk                             (0x1UL << ETH_MACCR_ARP_Pos) /*!< 0x80000000 */
+#define ETH_MACCR_ARP                                 ETH_MACCR_ARP_Msk        /* ARP Offload Enable */
+#define ETH_MACCR_SARC_Pos                            (28U)
+#define ETH_MACCR_SARC_Msk                            (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
+#define ETH_MACCR_SARC                                ETH_MACCR_SARC_Msk       /* Source Address Insertion or Replacement Control */
+#define ETH_MACCR_SARC_MTIATI                         ((uint32_t)0x00000000)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
+#define ETH_MACCR_SARC_INSADDR0_Pos                   (29U)
+#define ETH_MACCR_SARC_INSADDR0_Msk                   (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
+#define ETH_MACCR_SARC_INSADDR0                       ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
+#define ETH_MACCR_SARC_INSADDR1_Pos                   (29U)
+#define ETH_MACCR_SARC_INSADDR1_Msk                   (0x3UL << ETH_MACCR_SARC_INSADDR1_Pos) /*!< 0x60000000 */
+#define ETH_MACCR_SARC_INSADDR1                       ETH_MACCR_SARC_INSADDR1_Msk /* Insert MAC Address1 in the SA field of all transmitted packets. */
+#define ETH_MACCR_SARC_REPADDR0_Pos                   (28U)
+#define ETH_MACCR_SARC_REPADDR0_Msk                   (0x3UL << ETH_MACCR_SARC_REPADDR0_Pos) /*!< 0x30000000 */
+#define ETH_MACCR_SARC_REPADDR0                       ETH_MACCR_SARC_REPADDR0_Msk /* Replace MAC Address0 in the SA field of all transmitted packets. */
+#define ETH_MACCR_SARC_REPADDR1_Pos                   (28U)
+#define ETH_MACCR_SARC_REPADDR1_Msk                   (0x7UL << ETH_MACCR_SARC_REPADDR1_Pos) /*!< 0x70000000 */
+#define ETH_MACCR_SARC_REPADDR1                       ETH_MACCR_SARC_REPADDR1_Msk /* Replace MAC Address1 in the SA field of all transmitted packets. */
+#define ETH_MACCR_IPC_Pos                             (27U)
+#define ETH_MACCR_IPC_Msk                             (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */
+#define ETH_MACCR_IPC                                 ETH_MACCR_IPC_Msk        /* Checksum Offload */
+#define ETH_MACCR_IPG_Pos                             (24U)
+#define ETH_MACCR_IPG_Msk                             (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
+#define ETH_MACCR_IPG                                 ETH_MACCR_IPG_Msk        /* Inter-Packet Gap */
+#define ETH_MACCR_IPG_96BIT                           ((uint32_t)0x00000000)   /* Minimum IFG between Packets during transmission is 96Bit */
+#define ETH_MACCR_IPG_88BIT                           ((uint32_t)0x01000000)   /* Minimum IFG between Packets during transmission is 88Bit */
+#define ETH_MACCR_IPG_80BIT                           ((uint32_t)0x02000000)   /* Minimum IFG between Packets during transmission is 80Bit */
+#define ETH_MACCR_IPG_72BIT                           ((uint32_t)0x03000000)   /* Minimum IFG between Packets during transmission is 72Bit */
+#define ETH_MACCR_IPG_64BIT                           ((uint32_t)0x04000000)   /* Minimum IFG between Packets during transmission is 64Bit */
+#define ETH_MACCR_IPG_56BIT                           ((uint32_t)0x05000000)   /* Minimum IFG between Packets during transmission is 56Bit */
+#define ETH_MACCR_IPG_48BIT                           ((uint32_t)0x06000000)   /* Minimum IFG between Packets during transmission is 48Bit */
+#define ETH_MACCR_IPG_40BIT                           ((uint32_t)0x07000000)   /* Minimum IFG between Packets during transmission is 40Bit */
+#define ETH_MACCR_GPSLCE_Pos                          (23U)
+#define ETH_MACCR_GPSLCE_Msk                          (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
+#define ETH_MACCR_GPSLCE                              ETH_MACCR_GPSLCE_Msk     /* Giant Packet Size Limit Control Enable */
+#define ETH_MACCR_S2KP_Pos                            (22U)
+#define ETH_MACCR_S2KP_Msk                            (0x1UL << ETH_MACCR_S2KP_Pos) /*!< 0x00400000 */
+#define ETH_MACCR_S2KP                                ETH_MACCR_S2KP_Msk       /* IEEE 802.3as Support for 2K Packets */
+#define ETH_MACCR_CST_Pos                             (21U)
+#define ETH_MACCR_CST_Msk                             (0x1UL << ETH_MACCR_CST_Pos) /*!< 0x00200000 */
+#define ETH_MACCR_CST                                 ETH_MACCR_CST_Msk        /* CRC stripping for Type packets */
+#define ETH_MACCR_ACS_Pos                             (20U)
+#define ETH_MACCR_ACS_Msk                             (0x1UL << ETH_MACCR_ACS_Pos) /*!< 0x00100000 */
+#define ETH_MACCR_ACS                                 ETH_MACCR_ACS_Msk        /* Automatic Pad or CRC Stripping */
+#define ETH_MACCR_WD_Pos                              (19U)
+#define ETH_MACCR_WD_Msk                              (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00080000 */
+#define ETH_MACCR_WD                                  ETH_MACCR_WD_Msk         /* Watchdog disable */
+#define ETH_MACCR_JD_Pos                              (17U)
+#define ETH_MACCR_JD_Msk                              (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00020000 */
+#define ETH_MACCR_JD                                  ETH_MACCR_JD_Msk         /* Jabber disable */
+#define ETH_MACCR_JE_Pos                              (16U)
+#define ETH_MACCR_JE_Msk                              (0x1UL << ETH_MACCR_JE_Pos) /*!< 0x00010000 */
+#define ETH_MACCR_JE                                  ETH_MACCR_JE_Msk         /* Jumbo Packet Enable */
+#define ETH_MACCR_FES_Pos                             (14U)
+#define ETH_MACCR_FES_Msk                             (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
+#define ETH_MACCR_FES                                 ETH_MACCR_FES_Msk        /* Fast ethernet speed */
+#define ETH_MACCR_DM_Pos                              (13U)
+#define ETH_MACCR_DM_Msk                              (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00002000 */
+#define ETH_MACCR_DM                                  ETH_MACCR_DM_Msk         /* Duplex mode */
+#define ETH_MACCR_LM_Pos                              (12U)
+#define ETH_MACCR_LM_Msk                              (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
+#define ETH_MACCR_LM                                  ETH_MACCR_LM_Msk         /* loopback mode */
+#define ETH_MACCR_ECRSFD_Pos                          (11U)
+#define ETH_MACCR_ECRSFD_Msk                          (0x1UL << ETH_MACCR_ECRSFD_Pos) /*!< 0x00000800 */
+#define ETH_MACCR_ECRSFD                              ETH_MACCR_ECRSFD_Msk     /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */
+#define ETH_MACCR_DO_Pos                              (10U)
+#define ETH_MACCR_DO_Msk                              (0x1UL << ETH_MACCR_DO_Pos) /*!< 0x00000400 */
+#define ETH_MACCR_DO                                  ETH_MACCR_DO_Msk         /* Disable Receive own  */
+#define ETH_MACCR_DCRS_Pos                            (9U)
+#define ETH_MACCR_DCRS_Msk                            (0x1UL << ETH_MACCR_DCRS_Pos) /*!< 0x00000200 */
+#define ETH_MACCR_DCRS                                ETH_MACCR_DCRS_Msk       /* Disable Carrier Sense During Transmission */
+#define ETH_MACCR_DR_Pos                              (8U)
+#define ETH_MACCR_DR_Msk                              (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */
+#define ETH_MACCR_DR                                  ETH_MACCR_DR_Msk         /* Disable Retry */
+#define ETH_MACCR_BL_Pos                              (5U)
+#define ETH_MACCR_BL_Msk                              (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
+#define ETH_MACCR_BL                                  ETH_MACCR_BL_Msk         /* Back-off limit mask */
+#define ETH_MACCR_BL_10                               (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */
+#define ETH_MACCR_BL_8                                (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */
+#define ETH_MACCR_BL_4                                (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */
+#define ETH_MACCR_BL_1                                (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
+#define ETH_MACCR_DC_Pos                              (4U)
+#define ETH_MACCR_DC_Msk                              (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
+#define ETH_MACCR_DC                                  ETH_MACCR_DC_Msk         /* Defferal check */
+#define ETH_MACCR_PRELEN_Pos                          (2U)
+#define ETH_MACCR_PRELEN_Msk                          (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */
+#define ETH_MACCR_PRELEN                              ETH_MACCR_PRELEN_Msk     /* Preamble Length for Transmit packets */
+#define ETH_MACCR_PRELEN_7                            (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */
+#define ETH_MACCR_PRELEN_5                            (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */
+#define ETH_MACCR_PRELEN_3                            (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */
+#define ETH_MACCR_TE_Pos                              (1U)
+#define ETH_MACCR_TE_Msk                              (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000002 */
+#define ETH_MACCR_TE                                  ETH_MACCR_TE_Msk         /* Transmitter enable */
+#define ETH_MACCR_RE_Pos                              (0U)
+#define ETH_MACCR_RE_Msk                              (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000001 */
+#define ETH_MACCR_RE                                  ETH_MACCR_RE_Msk         /* Receiver enable */
+
+/* Bit definition for Ethernet MAC Extended Configuration Register register */
+#define ETH_MACECR_EIPG_Pos                           (25U)
+#define ETH_MACECR_EIPG_Msk                           (0x1FUL << ETH_MACECR_EIPG_Pos) /*!< 0x3E000000 */
+#define ETH_MACECR_EIPG                               ETH_MACECR_EIPG_Msk      /* Extended Inter-Packet Gap */
+#define ETH_MACECR_EIPGEN_Pos                         (24U)
+#define ETH_MACECR_EIPGEN_Msk                         (0x1UL << ETH_MACECR_EIPGEN_Pos) /*!< 0x01000000 */
+#define ETH_MACECR_EIPGEN                             ETH_MACECR_EIPGEN_Msk    /* Extended Inter-Packet Gap Enable */
+#define ETH_MACECR_USP_Pos                            (18U)
+#define ETH_MACECR_USP_Msk                            (0x1UL << ETH_MACECR_USP_Pos) /*!< 0x00040000 */
+#define ETH_MACECR_USP                                ETH_MACECR_USP_Msk       /* Unicast Slow Protocol Packet Detect */
+#define ETH_MACECR_SPEN_Pos                           (17U)
+#define ETH_MACECR_SPEN_Msk                           (0x1UL << ETH_MACECR_SPEN_Pos) /*!< 0x00020000 */
+#define ETH_MACECR_SPEN                               ETH_MACECR_SPEN_Msk      /* Slow Protocol Detection Enable */
+#define ETH_MACECR_DCRCC_Pos                          (16U)
+#define ETH_MACECR_DCRCC_Msk                          (0x1UL << ETH_MACECR_DCRCC_Pos) /*!< 0x00010000 */
+#define ETH_MACECR_DCRCC                              ETH_MACECR_DCRCC_Msk     /* Disable CRC Checking for Received Packets */
+#define ETH_MACECR_GPSL_Pos                           (0U)
+#define ETH_MACECR_GPSL_Msk                           (0x3FFFUL << ETH_MACECR_GPSL_Pos) /*!< 0x00003FFF */
+#define ETH_MACECR_GPSL                               ETH_MACECR_GPSL_Msk      /* Giant Packet Size Limit */
+
+/* Bit definition for Ethernet MAC Packet Filter Register */
+#define ETH_MACPFR_RA_Pos                             (31U)
+#define ETH_MACPFR_RA_Msk                             (0x1UL << ETH_MACPFR_RA_Pos) /*!< 0x80000000 */
+#define ETH_MACPFR_RA                                 ETH_MACPFR_RA_Msk        /* Receive all */
+#define ETH_MACPFR_DNTU_Pos                           (21U)
+#define ETH_MACPFR_DNTU_Msk                           (0x1UL << ETH_MACPFR_DNTU_Pos) /*!< 0x00200000 */
+#define ETH_MACPFR_DNTU                               ETH_MACPFR_DNTU_Msk      /* Drop Non-TCP/UDP over IP Packets */
+#define ETH_MACPFR_IPFE_Pos                           (20U)
+#define ETH_MACPFR_IPFE_Msk                           (0x1UL << ETH_MACPFR_IPFE_Pos) /*!< 0x00100000 */
+#define ETH_MACPFR_IPFE                               ETH_MACPFR_IPFE_Msk      /* Layer 3 and Layer 4 Filter Enable */
+#define ETH_MACPFR_VTFE_Pos                           (16U)
+#define ETH_MACPFR_VTFE_Msk                           (0x1UL << ETH_MACPFR_VTFE_Pos) /*!< 0x00010000 */
+#define ETH_MACPFR_VTFE                               ETH_MACPFR_VTFE_Msk      /* VLAN Tag Filter Enable */
+#define ETH_MACPFR_HPF_Pos                            (10U)
+#define ETH_MACPFR_HPF_Msk                            (0x1UL << ETH_MACPFR_HPF_Pos) /*!< 0x00000400 */
+#define ETH_MACPFR_HPF                                ETH_MACPFR_HPF_Msk       /* Hash or perfect filter */
+#define ETH_MACPFR_SAF_Pos                            (9U)
+#define ETH_MACPFR_SAF_Msk                            (0x1UL << ETH_MACPFR_SAF_Pos) /*!< 0x00000200 */
+#define ETH_MACPFR_SAF                                ETH_MACPFR_SAF_Msk       /* Source address filter enable */
+#define ETH_MACPFR_SAIF_Pos                           (8U)
+#define ETH_MACPFR_SAIF_Msk                           (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */
+#define ETH_MACPFR_SAIF                               ETH_MACPFR_SAIF_Msk      /* SA inverse filtering */
+#define ETH_MACPFR_PCF_Pos                            (6U)
+#define ETH_MACPFR_PCF_Msk                            (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
+#define ETH_MACPFR_PCF                                ETH_MACPFR_PCF_Msk       /* Pass control frames: 4 cases */
+#define ETH_MACPFR_PCF_BLOCKALL                       ((uint32_t)0x00000000)   /* MAC filters all control frames from reaching the application */
+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos         (6U)
+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk         (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA             ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
+#define ETH_MACPFR_PCF_FORWARDALL_Pos                 (7U)
+#define ETH_MACPFR_PCF_FORWARDALL_Msk                 (0x1UL << ETH_MACPFR_PCF_FORWARDALL_Pos) /*!< 0x00000080 */
+#define ETH_MACPFR_PCF_FORWARDALL                     ETH_MACPFR_PCF_FORWARDALL_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos    (6U)
+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk    (0x3UL << ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos) /*!< 0x000000C0 */
+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER        ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk /* MAC forwards control frames that pass the Address Filter. */
+#define ETH_MACPFR_DBF_Pos                            (5U)
+#define ETH_MACPFR_DBF_Msk                            (0x1UL << ETH_MACPFR_DBF_Pos) /*!< 0x00000020 */
+#define ETH_MACPFR_DBF                                ETH_MACPFR_DBF_Msk       /* Disable Broadcast Packets */
+#define ETH_MACPFR_PM_Pos                             (4U)
+#define ETH_MACPFR_PM_Msk                             (0x1UL << ETH_MACPFR_PM_Pos) /*!< 0x00000010 */
+#define ETH_MACPFR_PM                                 ETH_MACPFR_PM_Msk        /* Pass all mutlicast */
+#define ETH_MACPFR_DAIF_Pos                           (3U)
+#define ETH_MACPFR_DAIF_Msk                           (0x1UL << ETH_MACPFR_DAIF_Pos) /*!< 0x00000008 */
+#define ETH_MACPFR_DAIF                               ETH_MACPFR_DAIF_Msk      /* DA Inverse filtering */
+#define ETH_MACPFR_HMC_Pos                            (2U)
+#define ETH_MACPFR_HMC_Msk                            (0x1UL << ETH_MACPFR_HMC_Pos) /*!< 0x00000004 */
+#define ETH_MACPFR_HMC                                ETH_MACPFR_HMC_Msk       /* Hash multicast */
+#define ETH_MACPFR_HUC_Pos                            (1U)
+#define ETH_MACPFR_HUC_Msk                            (0x1UL << ETH_MACPFR_HUC_Pos) /*!< 0x00000002 */
+#define ETH_MACPFR_HUC                                ETH_MACPFR_HUC_Msk       /* Hash unicast */
+#define ETH_MACPFR_PR_Pos                             (0U)
+#define ETH_MACPFR_PR_Msk                             (0x1UL << ETH_MACPFR_PR_Pos) /*!< 0x00000001 */
+#define ETH_MACPFR_PR                                 ETH_MACPFR_PR_Msk        /* Promiscuous mode */
+
+/* Bit definition for Ethernet MAC Watchdog Timeout Register */
+#define ETH_MACWTR_PWE_Pos                            (8U)
+#define ETH_MACWTR_PWE_Msk                            (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */
+#define ETH_MACWTR_PWE                                ETH_MACWTR_PWE_Msk       /* Programmable Watchdog Enable */
+#define ETH_MACWTR_WTO_Pos                            (0U)
+#define ETH_MACWTR_WTO_Msk                            (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
+#define ETH_MACWTR_WTO                                ETH_MACWTR_WTO_Msk       /* Watchdog Timeout */
+#define ETH_MACWTR_WTO_2KB                            ((uint32_t)0x00000000)   /* Maximum received packet length 2KB*/
+#define ETH_MACWTR_WTO_3KB                            ((uint32_t)0x00000001)   /* Maximum received packet length 3KB */
+#define ETH_MACWTR_WTO_4KB                            ((uint32_t)0x00000002)   /* Maximum received packet length 4KB */
+#define ETH_MACWTR_WTO_5KB                            ((uint32_t)0x00000003)   /* Maximum received packet length 5KB */
+#define ETH_MACWTR_WTO_6KB                            ((uint32_t)0x00000004)   /* Maximum received packet length 6KB */
+#define ETH_MACWTR_WTO_7KB                            ((uint32_t)0x00000005)   /* Maximum received packet length 7KB */
+#define ETH_MACWTR_WTO_8KB                            ((uint32_t)0x00000006)   /* Maximum received packet length 8KB */
+#define ETH_MACWTR_WTO_9KB                            ((uint32_t)0x00000007)   /* Maximum received packet length 9KB */
+#define ETH_MACWTR_WTO_10KB                           ((uint32_t)0x00000008)   /* Maximum received packet length 10KB */
+#define ETH_MACWTR_WTO_11KB                           ((uint32_t)0x00000009)   /* Maximum received packet length 11KB */
+#define ETH_MACWTR_WTO_12KB                           ((uint32_t)0x0000000A)   /* Maximum received packet length 12KB */
+#define ETH_MACWTR_WTO_13KB                           ((uint32_t)0x0000000B)   /* Maximum received packet length 13KB */
+#define ETH_MACWTR_WTO_14KB                           ((uint32_t)0x0000000C)   /* Maximum received packet length 14KB */
+#define ETH_MACWTR_WTO_15KB                           ((uint32_t)0x0000000D)   /* Maximum received packet length 15KB */
+#define ETH_MACWTR_WTO_16KB                           ((uint32_t)0x0000000E)   /* Maximum received packet length 16KB */
+
+/* Bit definition for Ethernet MAC Hash Table High Register */
+#define ETH_MACHTHR_HTH_Pos                           (0U)
+#define ETH_MACHTHR_HTH_Msk                           (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACHTHR_HTH                               ETH_MACHTHR_HTH_Msk      /* Hash table high */
+
+/* Bit definition for Ethernet MAC Hash Table Low Register */
+#define ETH_MACHTLR_HTL_Pos                           (0U)
+#define ETH_MACHTLR_HTL_Msk                           (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACHTLR_HTL                               ETH_MACHTLR_HTL_Msk      /* Hash table low */
+
+/* Bit definition for Ethernet MAC VLAN Tag Register */
+#define ETH_MACVTR_EIVLRXS_Pos                        (31U)
+#define ETH_MACVTR_EIVLRXS_Msk                        (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */
+#define ETH_MACVTR_EIVLRXS                            ETH_MACVTR_EIVLRXS_Msk   /* Enable Inner VLAN Tag in Rx Status */
+#define ETH_MACVTR_EIVLS_Pos                          (28U)
+#define ETH_MACVTR_EIVLS_Msk                          (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
+#define ETH_MACVTR_EIVLS                              ETH_MACVTR_EIVLS_Msk     /* Enable Inner VLAN Tag Stripping on Receive */
+#define ETH_MACVTR_EIVLS_DONOTSTRIP                   ((uint32_t)0x00000000)   /* Do not strip */
+#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos              (28U)
+#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk              (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
+#define ETH_MACVTR_EIVLS_STRIPIFPASS                  ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
+#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos             (29U)
+#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk             (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */
+#define ETH_MACVTR_EIVLS_STRIPIFFAILS                 ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
+#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos              (28U)
+#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk              (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */
+#define ETH_MACVTR_EIVLS_ALWAYSSTRIP                  ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */
+#define ETH_MACVTR_ERIVLT_Pos                         (27U)
+#define ETH_MACVTR_ERIVLT_Msk                         (0x1UL << ETH_MACVTR_ERIVLT_Pos) /*!< 0x08000000 */
+#define ETH_MACVTR_ERIVLT                             ETH_MACVTR_ERIVLT_Msk    /* Enable Inner VLAN Tag */
+#define ETH_MACVTR_EDVLP_Pos                          (26U)
+#define ETH_MACVTR_EDVLP_Msk                          (0x1UL << ETH_MACVTR_EDVLP_Pos) /*!< 0x04000000 */
+#define ETH_MACVTR_EDVLP                              ETH_MACVTR_EDVLP_Msk     /* Enable Double VLAN Processing */
+#define ETH_MACVTR_VTHM_Pos                           (25U)
+#define ETH_MACVTR_VTHM_Msk                           (0x1UL << ETH_MACVTR_VTHM_Pos) /*!< 0x02000000 */
+#define ETH_MACVTR_VTHM                               ETH_MACVTR_VTHM_Msk      /* VLAN Tag Hash Table Match Enable */
+#define ETH_MACVTR_EVLRXS_Pos                         (24U)
+#define ETH_MACVTR_EVLRXS_Msk                         (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */
+#define ETH_MACVTR_EVLRXS                             ETH_MACVTR_EVLRXS_Msk    /* Enable VLAN Tag in Rx status */
+#define ETH_MACVTR_EVLS_Pos                           (21U)
+#define ETH_MACVTR_EVLS_Msk                           (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
+#define ETH_MACVTR_EVLS                               ETH_MACVTR_EVLS_Msk      /* Enable VLAN Tag Stripping on Receive */
+#define ETH_MACVTR_EVLS_DONOTSTRIP                    ((uint32_t)0x00000000)   /* Do not strip */
+#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos               (21U)
+#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk               (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
+#define ETH_MACVTR_EVLS_STRIPIFPASS                   ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
+#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos              (22U)
+#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk              (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */
+#define ETH_MACVTR_EVLS_STRIPIFFAILS                  ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
+#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos               (21U)
+#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk               (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */
+#define ETH_MACVTR_EVLS_ALWAYSSTRIP                   ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */
+#define ETH_MACVTR_DOVLTC_Pos                         (20U)
+#define ETH_MACVTR_DOVLTC_Msk                         (0x1UL << ETH_MACVTR_DOVLTC_Pos) /*!< 0x00100000 */
+#define ETH_MACVTR_DOVLTC                             ETH_MACVTR_DOVLTC_Msk    /* Disable VLAN Type Check */
+#define ETH_MACVTR_ERSVLM_Pos                         (19U)
+#define ETH_MACVTR_ERSVLM_Msk                         (0x1UL << ETH_MACVTR_ERSVLM_Pos) /*!< 0x00080000 */
+#define ETH_MACVTR_ERSVLM                             ETH_MACVTR_ERSVLM_Msk    /* Enable Receive S-VLAN Match */
+#define ETH_MACVTR_ESVL_Pos                           (18U)
+#define ETH_MACVTR_ESVL_Msk                           (0x1UL << ETH_MACVTR_ESVL_Pos) /*!< 0x00040000 */
+#define ETH_MACVTR_ESVL                               ETH_MACVTR_ESVL_Msk      /* Enable S-VLAN */
+#define ETH_MACVTR_VTIM_Pos                           (17U)
+#define ETH_MACVTR_VTIM_Msk                           (0x1UL << ETH_MACVTR_VTIM_Pos) /*!< 0x00020000 */
+#define ETH_MACVTR_VTIM                               ETH_MACVTR_VTIM_Msk      /* VLAN Tag Inverse Match Enable */
+#define ETH_MACVTR_ETV_Pos                            (16U)
+#define ETH_MACVTR_ETV_Msk                            (0x1UL << ETH_MACVTR_ETV_Pos) /*!< 0x00010000 */
+#define ETH_MACVTR_ETV                                ETH_MACVTR_ETV_Msk       /* Enable 12-Bit VLAN Tag Comparison */
+#define ETH_MACVTR_VL_Pos                             (0U)
+#define ETH_MACVTR_VL_Msk                             (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */
+#define ETH_MACVTR_VL                                 ETH_MACVTR_VL_Msk        /* VLAN Tag Identifier for Receive Packets */
+#define ETH_MACVTR_VL_UP_Pos                          (13U)
+#define ETH_MACVTR_VL_UP_Msk                          (0x7UL << ETH_MACVTR_VL_UP_Pos) /*!< 0x0000E000 */
+#define ETH_MACVTR_VL_UP                              ETH_MACVTR_VL_UP_Msk     /* User Priority */
+#define ETH_MACVTR_VL_CFIDEI_Pos                      (12U)
+#define ETH_MACVTR_VL_CFIDEI_Msk                      (0x1UL << ETH_MACVTR_VL_CFIDEI_Pos) /*!< 0x00001000 */
+#define ETH_MACVTR_VL_CFIDEI                          ETH_MACVTR_VL_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
+#define ETH_MACVTR_VL_VID_Pos                         (0U)
+#define ETH_MACVTR_VL_VID_Msk                         (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */
+#define ETH_MACVTR_VL_VID                             ETH_MACVTR_VL_VID_Msk    /* VLAN Identifier field of VLAN tag */
+
+/* Bit definition for Ethernet MAC VLAN Hash Table Register */
+#define ETH_MACVHTR_VLHT_Pos                          (0U)
+#define ETH_MACVHTR_VLHT_Msk                          (0xFFFFUL << ETH_MACVHTR_VLHT_Pos) /*!< 0x0000FFFF */
+#define ETH_MACVHTR_VLHT                              ETH_MACVHTR_VLHT_Msk     /* VLAN Hash Table */
+
+/* Bit definition for Ethernet MAC VLAN Incl Register */
+#define ETH_MACVIR_VLTI_Pos                           (20U)
+#define ETH_MACVIR_VLTI_Msk                           (0x1UL << ETH_MACVIR_VLTI_Pos) /*!< 0x00100000 */
+#define ETH_MACVIR_VLTI                               ETH_MACVIR_VLTI_Msk      /* VLAN Tag Input */
+#define ETH_MACVIR_CSVL_Pos                           (19U)
+#define ETH_MACVIR_CSVL_Msk                           (0x1UL << ETH_MACVIR_CSVL_Pos) /*!< 0x00080000 */
+#define ETH_MACVIR_CSVL                               ETH_MACVIR_CSVL_Msk      /* C-VLAN or S-VLAN */
+#define ETH_MACVIR_VLP_Pos                            (18U)
+#define ETH_MACVIR_VLP_Msk                            (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */
+#define ETH_MACVIR_VLP                                ETH_MACVIR_VLP_Msk       /* VLAN Priority Control */
+#define ETH_MACVIR_VLC_Pos                            (16U)
+#define ETH_MACVIR_VLC_Msk                            (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
+#define ETH_MACVIR_VLC                                ETH_MACVIR_VLC_Msk       /* VLAN Tag Control in Transmit Packets */
+#define ETH_MACVIR_VLC_NOVLANTAG                      ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos              (16U)
+#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
+#define ETH_MACVIR_VLC_VLANTAGDELETE                  ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
+#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos              (17U)
+#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */
+#define ETH_MACVIR_VLC_VLANTAGINSERT                  ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
+#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos             (16U)
+#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk             (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */
+#define ETH_MACVIR_VLC_VLANTAGREPLACE                 ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
+#define ETH_MACVIR_VLT_Pos                            (0U)
+#define ETH_MACVIR_VLT_Msk                            (0xFFFFUL << ETH_MACVIR_VLT_Pos) /*!< 0x0000FFFF */
+#define ETH_MACVIR_VLT                                ETH_MACVIR_VLT_Msk       /* VLAN Tag for Transmit Packets */
+#define ETH_MACVIR_VLT_UP_Pos                         (13U)
+#define ETH_MACVIR_VLT_UP_Msk                         (0x7UL << ETH_MACVIR_VLT_UP_Pos) /*!< 0x0000E000 */
+#define ETH_MACVIR_VLT_UP                             ETH_MACVIR_VLT_UP_Msk    /* User Priority */
+#define ETH_MACVIR_VLT_CFIDEI_Pos                     (12U)
+#define ETH_MACVIR_VLT_CFIDEI_Msk                     (0x1UL << ETH_MACVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */
+#define ETH_MACVIR_VLT_CFIDEI                         ETH_MACVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
+#define ETH_MACVIR_VLT_VID_Pos                        (0U)
+#define ETH_MACVIR_VLT_VID_Msk                        (0xFFFUL << ETH_MACVIR_VLT_VID_Pos) /*!< 0x00000FFF */
+#define ETH_MACVIR_VLT_VID                            ETH_MACVIR_VLT_VID_Msk   /* VLAN Identifier field of VLAN tag */
+
+/* Bit definition for Ethernet MAC Inner_VLAN Incl Register */
+#define ETH_MACIVIR_VLTI_Pos                          (20U)
+#define ETH_MACIVIR_VLTI_Msk                          (0x1UL << ETH_MACIVIR_VLTI_Pos) /*!< 0x00100000 */
+#define ETH_MACIVIR_VLTI                              ETH_MACIVIR_VLTI_Msk     /* VLAN Tag Input */
+#define ETH_MACIVIR_CSVL_Pos                          (19U)
+#define ETH_MACIVIR_CSVL_Msk                          (0x1UL << ETH_MACIVIR_CSVL_Pos) /*!< 0x00080000 */
+#define ETH_MACIVIR_CSVL                              ETH_MACIVIR_CSVL_Msk     /* C-VLAN or S-VLAN */
+#define ETH_MACIVIR_VLP_Pos                           (18U)
+#define ETH_MACIVIR_VLP_Msk                           (0x1UL << ETH_MACIVIR_VLP_Pos) /*!< 0x00040000 */
+#define ETH_MACIVIR_VLP                               ETH_MACIVIR_VLP_Msk      /* VLAN Priority Control */
+#define ETH_MACIVIR_VLC_Pos                           (16U)
+#define ETH_MACIVIR_VLC_Msk                           (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
+#define ETH_MACIVIR_VLC                               ETH_MACIVIR_VLC_Msk      /* VLAN Tag Control in Transmit Packets */
+#define ETH_MACIVIR_VLC_NOVLANTAG                     ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos             (16U)
+#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
+#define ETH_MACIVIR_VLC_VLANTAGDELETE                 ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
+#define ETH_MACIVIR_VLC_VLANTAGINSERT_Pos             (17U)
+#define ETH_MACIVIR_VLC_VLANTAGINSERT_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */
+#define ETH_MACIVIR_VLC_VLANTAGINSERT                 ETH_MACIVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
+#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos            (16U)
+#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk            (0x3UL << ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */
+#define ETH_MACIVIR_VLC_VLANTAGREPLACE                ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
+#define ETH_MACIVIR_VLT_Pos                           (0U)
+#define ETH_MACIVIR_VLT_Msk                           (0xFFFFUL << ETH_MACIVIR_VLT_Pos) /*!< 0x0000FFFF */
+#define ETH_MACIVIR_VLT                               ETH_MACIVIR_VLT_Msk      /* VLAN Tag for Transmit Packets */
+#define ETH_MACIVIR_VLT_UP_Pos                        (13U)
+#define ETH_MACIVIR_VLT_UP_Msk                        (0x7UL << ETH_MACIVIR_VLT_UP_Pos) /*!< 0x0000E000 */
+#define ETH_MACIVIR_VLT_UP                            ETH_MACIVIR_VLT_UP_Msk   /* User Priority */
+#define ETH_MACIVIR_VLT_CFIDEI_Pos                    (12U)
+#define ETH_MACIVIR_VLT_CFIDEI_Msk                    (0x1UL << ETH_MACIVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */
+#define ETH_MACIVIR_VLT_CFIDEI                        ETH_MACIVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
+#define ETH_MACIVIR_VLT_VID_Pos                       (0U)
+#define ETH_MACIVIR_VLT_VID_Msk                       (0xFFFUL << ETH_MACIVIR_VLT_VID_Pos) /*!< 0x00000FFF */
+#define ETH_MACIVIR_VLT_VID                           ETH_MACIVIR_VLT_VID_Msk  /* VLAN Identifier field of VLAN tag */
+
+/* Bit definition for Ethernet MAC Tx Flow Ctrl Register */
+#define ETH_MACTFCR_PT_Pos                            (16U)
+#define ETH_MACTFCR_PT_Msk                            (0xFFFFUL << ETH_MACTFCR_PT_Pos) /*!< 0xFFFF0000 */
+#define ETH_MACTFCR_PT                                ETH_MACTFCR_PT_Msk       /* Pause Time */
+#define ETH_MACTFCR_DZPQ_Pos                          (7U)
+#define ETH_MACTFCR_DZPQ_Msk                          (0x1UL << ETH_MACTFCR_DZPQ_Pos) /*!< 0x00000080 */
+#define ETH_MACTFCR_DZPQ                              ETH_MACTFCR_DZPQ_Msk     /* Disable Zero-Quanta Pause */
+#define ETH_MACTFCR_PLT_Pos                           (4U)
+#define ETH_MACTFCR_PLT_Msk                           (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */
+#define ETH_MACTFCR_PLT                               ETH_MACTFCR_PLT_Msk      /* Pause Low Threshold */
+#define ETH_MACTFCR_PLT_MINUS4                        ((uint32_t)0x00000000)   /* Pause time minus 4 slot times */
+#define ETH_MACTFCR_PLT_MINUS28_Pos                   (4U)
+#define ETH_MACTFCR_PLT_MINUS28_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
+#define ETH_MACTFCR_PLT_MINUS28                       ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
+#define ETH_MACTFCR_PLT_MINUS36_Pos                   (5U)
+#define ETH_MACTFCR_PLT_MINUS36_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS36_Pos) /*!< 0x00000020 */
+#define ETH_MACTFCR_PLT_MINUS36                       ETH_MACTFCR_PLT_MINUS36_Msk /* Pause time minus 36 slot times */
+#define ETH_MACTFCR_PLT_MINUS144_Pos                  (4U)
+#define ETH_MACTFCR_PLT_MINUS144_Msk                  (0x3UL << ETH_MACTFCR_PLT_MINUS144_Pos) /*!< 0x00000030 */
+#define ETH_MACTFCR_PLT_MINUS144                      ETH_MACTFCR_PLT_MINUS144_Msk /* Pause time minus 144 slot times */
+#define ETH_MACTFCR_PLT_MINUS256_Pos                  (6U)
+#define ETH_MACTFCR_PLT_MINUS256_Msk                  (0x1UL << ETH_MACTFCR_PLT_MINUS256_Pos) /*!< 0x00000040 */
+#define ETH_MACTFCR_PLT_MINUS256                      ETH_MACTFCR_PLT_MINUS256_Msk /* Pause time minus 256 slot times */
+#define ETH_MACTFCR_PLT_MINUS512_Pos                  (4U)
+#define ETH_MACTFCR_PLT_MINUS512_Msk                  (0x5UL << ETH_MACTFCR_PLT_MINUS512_Pos) /*!< 0x00000050 */
+#define ETH_MACTFCR_PLT_MINUS512                      ETH_MACTFCR_PLT_MINUS512_Msk /* Pause time minus 512 slot times */
+#define ETH_MACTFCR_TFE_Pos                           (1U)
+#define ETH_MACTFCR_TFE_Msk                           (0x1UL << ETH_MACTFCR_TFE_Pos) /*!< 0x00000002 */
+#define ETH_MACTFCR_TFE                               ETH_MACTFCR_TFE_Msk      /* Transmit Flow Control Enable */
+#define ETH_MACTFCR_FCB_Pos                           (0U)
+#define ETH_MACTFCR_FCB_Msk                           (0x1UL << ETH_MACTFCR_FCB_Pos) /*!< 0x00000001 */
+#define ETH_MACTFCR_FCB                               ETH_MACTFCR_FCB_Msk      /* Flow Control Busy or Backpressure Activate */
+
+/* Bit definition for Ethernet MAC Rx Flow Ctrl Register */
+#define ETH_MACRFCR_UP_Pos                            (1U)
+#define ETH_MACRFCR_UP_Msk                            (0x1UL << ETH_MACRFCR_UP_Pos) /*!< 0x00000002 */
+#define ETH_MACRFCR_UP                                ETH_MACRFCR_UP_Msk       /* Unicast Pause Packet Detect */
+#define ETH_MACRFCR_RFE_Pos                           (0U)
+#define ETH_MACRFCR_RFE_Msk                           (0x1UL << ETH_MACRFCR_RFE_Pos) /*!< 0x00000001 */
+#define ETH_MACRFCR_RFE                               ETH_MACRFCR_RFE_Msk      /* Receive Flow Control Enable */
+
+/* Bit definition for Ethernet MAC Interrupt Status Register */
+#define ETH_MACISR_RXSTSIS_Pos                        (14U)
+#define ETH_MACISR_RXSTSIS_Msk                        (0x1UL << ETH_MACISR_RXSTSIS_Pos) /*!< 0x00004000 */
+#define ETH_MACISR_RXSTSIS                            ETH_MACISR_RXSTSIS_Msk   /* Receive Status Interrupt */
+#define ETH_MACISR_TXSTSIS_Pos                        (13U)
+#define ETH_MACISR_TXSTSIS_Msk                        (0x1UL << ETH_MACISR_TXSTSIS_Pos) /*!< 0x00002000 */
+#define ETH_MACISR_TXSTSIS                            ETH_MACISR_TXSTSIS_Msk   /* Transmit Status Interrupt */
+#define ETH_MACISR_TSIS_Pos                           (12U)
+#define ETH_MACISR_TSIS_Msk                           (0x1UL << ETH_MACISR_TSIS_Pos) /*!< 0x00001000 */
+#define ETH_MACISR_TSIS                               ETH_MACISR_TSIS_Msk      /* Timestamp Interrupt Status */
+#define ETH_MACISR_MMCTXIS_Pos                        (10U)
+#define ETH_MACISR_MMCTXIS_Msk                        (0x1UL << ETH_MACISR_MMCTXIS_Pos) /*!< 0x00000400 */
+#define ETH_MACISR_MMCTXIS                            ETH_MACISR_MMCTXIS_Msk   /* MMC Transmit Interrupt Status */
+#define ETH_MACISR_MMCRXIS_Pos                        (9U)
+#define ETH_MACISR_MMCRXIS_Msk                        (0x1UL << ETH_MACISR_MMCRXIS_Pos) /*!< 0x00000200 */
+#define ETH_MACISR_MMCRXIS                            ETH_MACISR_MMCRXIS_Msk   /* MMC Receive Interrupt Status */
+#define ETH_MACISR_MMCIS_Pos                          (8U)
+#define ETH_MACISR_MMCIS_Msk                          (0x1UL << ETH_MACISR_MMCIS_Pos) /*!< 0x00000100 */
+#define ETH_MACISR_MMCIS                              ETH_MACISR_MMCIS_Msk     /* MMC Interrupt Status */
+#define ETH_MACISR_LPIIS_Pos                          (5U)
+#define ETH_MACISR_LPIIS_Msk                          (0x1UL << ETH_MACISR_LPIIS_Pos) /*!< 0x00000020 */
+#define ETH_MACISR_LPIIS                              ETH_MACISR_LPIIS_Msk     /* LPI Interrupt Status */
+#define ETH_MACISR_PMTIS_Pos                          (4U)
+#define ETH_MACISR_PMTIS_Msk                          (0x1UL << ETH_MACISR_PMTIS_Pos) /*!< 0x00000010 */
+#define ETH_MACISR_PMTIS                              ETH_MACISR_PMTIS_Msk     /* PMT Interrupt Status */
+#define ETH_MACISR_PHYIS_Pos                          (3U)
+#define ETH_MACISR_PHYIS_Msk                          (0x1UL << ETH_MACISR_PHYIS_Pos) /*!< 0x00000008 */
+#define ETH_MACISR_PHYIS                              ETH_MACISR_PHYIS_Msk     /* PHY Interrupt */
+
+/* Bit definition for Ethernet MAC Interrupt Enable Register */
+#define ETH_MACIER_RXSTSIE_Pos                        (14U)
+#define ETH_MACIER_RXSTSIE_Msk                        (0x1UL << ETH_MACIER_RXSTSIE_Pos) /*!< 0x00004000 */
+#define ETH_MACIER_RXSTSIE                            ETH_MACIER_RXSTSIE_Msk   /* Receive Status Interrupt Enable */
+#define ETH_MACIER_TXSTSIE_Pos                        (13U)
+#define ETH_MACIER_TXSTSIE_Msk                        (0x1UL << ETH_MACIER_TXSTSIE_Pos) /*!< 0x00002000 */
+#define ETH_MACIER_TXSTSIE                            ETH_MACIER_TXSTSIE_Msk   /* Transmit Status Interrupt Enable */
+#define ETH_MACIER_TSIE_Pos                           (12U)
+#define ETH_MACIER_TSIE_Msk                           (0x1UL << ETH_MACIER_TSIE_Pos) /*!< 0x00001000 */
+#define ETH_MACIER_TSIE                               ETH_MACIER_TSIE_Msk      /* Timestamp Interrupt Enable */
+#define ETH_MACIER_LPIIE_Pos                          (5U)
+#define ETH_MACIER_LPIIE_Msk                          (0x1UL << ETH_MACIER_LPIIE_Pos) /*!< 0x00000020 */
+#define ETH_MACIER_LPIIE                              ETH_MACIER_LPIIE_Msk     /* LPI Interrupt Enable */
+#define ETH_MACIER_PMTIE_Pos                          (4U)
+#define ETH_MACIER_PMTIE_Msk                          (0x1UL << ETH_MACIER_PMTIE_Pos) /*!< 0x00000010 */
+#define ETH_MACIER_PMTIE                              ETH_MACIER_PMTIE_Msk     /* PMT Interrupt Enable */
+#define ETH_MACIER_PHYIE_Pos                          (3U)
+#define ETH_MACIER_PHYIE_Msk                          (0x1UL << ETH_MACIER_PHYIE_Pos) /*!< 0x00000008 */
+#define ETH_MACIER_PHYIE                              ETH_MACIER_PHYIE_Msk     /* PHY Interrupt Enable */
+
+/* Bit definition for Ethernet MAC Rx Tx Status Register */
+#define ETH_MACRXTXSR_RWT_Pos                         (8U)
+#define ETH_MACRXTXSR_RWT_Msk                         (0x1UL << ETH_MACRXTXSR_RWT_Pos) /*!< 0x00000100 */
+#define ETH_MACRXTXSR_RWT                             ETH_MACRXTXSR_RWT_Msk    /* Receive Watchdog Timeout */
+#define ETH_MACRXTXSR_EXCOL_Pos                       (5U)
+#define ETH_MACRXTXSR_EXCOL_Msk                       (0x1UL << ETH_MACRXTXSR_EXCOL_Pos) /*!< 0x00000020 */
+#define ETH_MACRXTXSR_EXCOL                           ETH_MACRXTXSR_EXCOL_Msk  /* Excessive Collisions */
+#define ETH_MACRXTXSR_LCOL_Pos                        (4U)
+#define ETH_MACRXTXSR_LCOL_Msk                        (0x1UL << ETH_MACRXTXSR_LCOL_Pos) /*!< 0x00000010 */
+#define ETH_MACRXTXSR_LCOL                            ETH_MACRXTXSR_LCOL_Msk   /* Late Collision */
+#define ETH_MACRXTXSR_EXDEF_Pos                       (3U)
+#define ETH_MACRXTXSR_EXDEF_Msk                       (0x1UL << ETH_MACRXTXSR_EXDEF_Pos) /*!< 0x00000008 */
+#define ETH_MACRXTXSR_EXDEF                           ETH_MACRXTXSR_EXDEF_Msk  /* Excessive Deferral */
+#define ETH_MACRXTXSR_LCARR_Pos                       (2U)
+#define ETH_MACRXTXSR_LCARR_Msk                       (0x1UL << ETH_MACRXTXSR_LCARR_Pos) /*!< 0x00000004 */
+#define ETH_MACRXTXSR_LCARR                           ETH_MACRXTXSR_LCARR_Msk  /* Loss of Carrier */
+#define ETH_MACRXTXSR_NCARR_Pos                       (1U)
+#define ETH_MACRXTXSR_NCARR_Msk                       (0x1UL << ETH_MACRXTXSR_NCARR_Pos) /*!< 0x00000002 */
+#define ETH_MACRXTXSR_NCARR                           ETH_MACRXTXSR_NCARR_Msk  /* No Carrier */
+#define ETH_MACRXTXSR_TJT_Pos                         (0U)
+#define ETH_MACRXTXSR_TJT_Msk                         (0x1UL << ETH_MACRXTXSR_TJT_Pos) /*!< 0x00000001 */
+#define ETH_MACRXTXSR_TJT                             ETH_MACRXTXSR_TJT_Msk    /* Transmit Jabber Timeout */
+
+/* Bit definition for Ethernet MAC PMT Control Status Register */
+#define ETH_MACPCSR_RWKFILTRST_Pos                    (31U)
+#define ETH_MACPCSR_RWKFILTRST_Msk                    (0x1UL << ETH_MACPCSR_RWKFILTRST_Pos) /*!< 0x80000000 */
+#define ETH_MACPCSR_RWKFILTRST                        ETH_MACPCSR_RWKFILTRST_Msk /* Remote Wake-Up Packet Filter Register Pointer Reset */
+#define ETH_MACPCSR_RWKPTR_Pos                        (24U)
+#define ETH_MACPCSR_RWKPTR_Msk                        (0x1FUL << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x1F000000 */
+#define ETH_MACPCSR_RWKPTR                            ETH_MACPCSR_RWKPTR_Msk   /* Remote Wake-up FIFO Pointer */
+#define ETH_MACPCSR_RWKPFE_Pos                        (10U)
+#define ETH_MACPCSR_RWKPFE_Msk                        (0x1UL << ETH_MACPCSR_RWKPFE_Pos) /*!< 0x00000400 */
+#define ETH_MACPCSR_RWKPFE                            ETH_MACPCSR_RWKPFE_Msk   /* Remote Wake-up Packet Forwarding Enable */
+#define ETH_MACPCSR_GLBLUCAST_Pos                     (9U)
+#define ETH_MACPCSR_GLBLUCAST_Msk                     (0x1UL << ETH_MACPCSR_GLBLUCAST_Pos) /*!< 0x00000200 */
+#define ETH_MACPCSR_GLBLUCAST                         ETH_MACPCSR_GLBLUCAST_Msk /* Global Unicast */
+#define ETH_MACPCSR_RWKPRCVD_Pos                      (6U)
+#define ETH_MACPCSR_RWKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_RWKPRCVD_Pos) /*!< 0x00000040 */
+#define ETH_MACPCSR_RWKPRCVD                          ETH_MACPCSR_RWKPRCVD_Msk /* Remote Wake-Up Packet Received */
+#define ETH_MACPCSR_MGKPRCVD_Pos                      (5U)
+#define ETH_MACPCSR_MGKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_MGKPRCVD_Pos) /*!< 0x00000020 */
+#define ETH_MACPCSR_MGKPRCVD                          ETH_MACPCSR_MGKPRCVD_Msk /* Magic Packet Received */
+#define ETH_MACPCSR_RWKPKTEN_Pos                      (2U)
+#define ETH_MACPCSR_RWKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_RWKPKTEN_Pos) /*!< 0x00000004 */
+#define ETH_MACPCSR_RWKPKTEN                          ETH_MACPCSR_RWKPKTEN_Msk /* Remote Wake-Up Packet Enable */
+#define ETH_MACPCSR_MGKPKTEN_Pos                      (1U)
+#define ETH_MACPCSR_MGKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_MGKPKTEN_Pos) /*!< 0x00000002 */
+#define ETH_MACPCSR_MGKPKTEN                          ETH_MACPCSR_MGKPKTEN_Msk /* Magic Packet Enable */
+#define ETH_MACPCSR_PWRDWN_Pos                        (0U)
+#define ETH_MACPCSR_PWRDWN_Msk                        (0x1UL << ETH_MACPCSR_PWRDWN_Pos) /*!< 0x00000001 */
+#define ETH_MACPCSR_PWRDWN                            ETH_MACPCSR_PWRDWN_Msk   /* Power Down */
+
+/* Bit definition for Ethernet MAC Remote Wake-Up Packet Filter Register */
+#define ETH_MACRWUPFR_D_Pos                           (0U)
+#define ETH_MACRWUPFR_D_Msk                           (0xFFFFFFFFUL << ETH_MACRWUPFR_D_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACRWUPFR_D                               ETH_MACRWUPFR_D_Msk      /* Wake-up Packet filter register data */
+
+/* Bit definition for Ethernet MAC LPI Control Status Register */
+#define ETH_MACLCSR_LPITCSE_Pos                       (21U)
+#define ETH_MACLCSR_LPITCSE_Msk                       (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */
+#define ETH_MACLCSR_LPITCSE                           ETH_MACLCSR_LPITCSE_Msk  /* LPI Tx Clock Stop Enable */
+#define ETH_MACLCSR_LPITE_Pos                         (20U)
+#define ETH_MACLCSR_LPITE_Msk                         (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */
+#define ETH_MACLCSR_LPITE                             ETH_MACLCSR_LPITE_Msk    /* LPI Timer Enable */
+#define ETH_MACLCSR_LPITXA_Pos                        (19U)
+#define ETH_MACLCSR_LPITXA_Msk                        (0x1UL << ETH_MACLCSR_LPITXA_Pos) /*!< 0x00080000 */
+#define ETH_MACLCSR_LPITXA                            ETH_MACLCSR_LPITXA_Msk   /* LPI Tx Automate */
+#define ETH_MACLCSR_PLS_Pos                           (17U)
+#define ETH_MACLCSR_PLS_Msk                           (0x1UL << ETH_MACLCSR_PLS_Pos) /*!< 0x00020000 */
+#define ETH_MACLCSR_PLS                               ETH_MACLCSR_PLS_Msk      /* PHY Link Status */
+#define ETH_MACLCSR_LPIEN_Pos                         (16U)
+#define ETH_MACLCSR_LPIEN_Msk                         (0x1UL << ETH_MACLCSR_LPIEN_Pos) /*!< 0x00010000 */
+#define ETH_MACLCSR_LPIEN                             ETH_MACLCSR_LPIEN_Msk    /* LPI Enable */
+#define ETH_MACLCSR_RLPIST_Pos                        (9U)
+#define ETH_MACLCSR_RLPIST_Msk                        (0x1UL << ETH_MACLCSR_RLPIST_Pos) /*!< 0x00000200 */
+#define ETH_MACLCSR_RLPIST                            ETH_MACLCSR_RLPIST_Msk   /* Receive LPI State */
+#define ETH_MACLCSR_TLPIST_Pos                        (8U)
+#define ETH_MACLCSR_TLPIST_Msk                        (0x1UL << ETH_MACLCSR_TLPIST_Pos) /*!< 0x00000100 */
+#define ETH_MACLCSR_TLPIST                            ETH_MACLCSR_TLPIST_Msk   /* Transmit LPI State */
+#define ETH_MACLCSR_RLPIEX_Pos                        (3U)
+#define ETH_MACLCSR_RLPIEX_Msk                        (0x1UL << ETH_MACLCSR_RLPIEX_Pos) /*!< 0x00000008 */
+#define ETH_MACLCSR_RLPIEX                            ETH_MACLCSR_RLPIEX_Msk   /* Receive LPI Exit */
+#define ETH_MACLCSR_RLPIEN_Pos                        (2U)
+#define ETH_MACLCSR_RLPIEN_Msk                        (0x1UL << ETH_MACLCSR_RLPIEN_Pos) /*!< 0x00000004 */
+#define ETH_MACLCSR_RLPIEN                            ETH_MACLCSR_RLPIEN_Msk   /* Receive LPI Entry */
+#define ETH_MACLCSR_TLPIEX_Pos                        (1U)
+#define ETH_MACLCSR_TLPIEX_Msk                        (0x1UL << ETH_MACLCSR_TLPIEX_Pos) /*!< 0x00000002 */
+#define ETH_MACLCSR_TLPIEX                            ETH_MACLCSR_TLPIEX_Msk   /* Transmit LPI Exit */
+#define ETH_MACLCSR_TLPIEN_Pos                        (0U)
+#define ETH_MACLCSR_TLPIEN_Msk                        (0x1UL << ETH_MACLCSR_TLPIEN_Pos) /*!< 0x00000001 */
+#define ETH_MACLCSR_TLPIEN                            ETH_MACLCSR_TLPIEN_Msk   /* Transmit LPI Entry */
+
+/* Bit definition for Ethernet MAC LPI Timers Control Register */
+#define ETH_MACLTCR_LST_Pos                           (16U)
+#define ETH_MACLTCR_LST_Msk                           (0x3FFUL << ETH_MACLTCR_LST_Pos) /*!< 0x03FF0000 */
+#define ETH_MACLTCR_LST                               ETH_MACLTCR_LST_Msk      /* LPI LS TIMER */
+#define ETH_MACLTCR_TWT_Pos                           (0U)
+#define ETH_MACLTCR_TWT_Msk                           (0xFFFFUL << ETH_MACLTCR_TWT_Pos) /*!< 0x0000FFFF */
+#define ETH_MACLTCR_TWT                               ETH_MACLTCR_TWT_Msk      /* LPI TW TIMER */
+
+/* Bit definition for Ethernet MAC LPI Entry Timer Register */
+#define ETH_MACLETR_LPIET_Pos                         (0U)
+#define ETH_MACLETR_LPIET_Msk                         (0xFFFFFUL << ETH_MACLETR_LPIET_Pos) /*!< 0x000FFFFF */
+#define ETH_MACLETR_LPIET                             ETH_MACLETR_LPIET_Msk    /* LPI Entry Timer */
+
+/* Bit definition for Ethernet MAC 1US Tic Counter Register */
+#define ETH_MAC1USTCR_TIC1USCNTR_Pos                  (0U)
+#define ETH_MAC1USTCR_TIC1USCNTR_Msk                  (0xFFFUL << ETH_MAC1USTCR_TIC1USCNTR_Pos) /*!< 0x00000FFF */
+#define ETH_MAC1USTCR_TIC1USCNTR                      ETH_MAC1USTCR_TIC1USCNTR_Msk /* 1US TIC Counter */
+
+/* Bit definition for Ethernet MAC Version Register */
+#define ETH_MACVR_USERVER_Pos                         (8U)
+#define ETH_MACVR_USERVER_Msk                         (0xFFUL << ETH_MACVR_USERVER_Pos) /*!< 0x0000FF00 */
+#define ETH_MACVR_USERVER                             ETH_MACVR_USERVER_Msk    /* User-defined Version */
+#define ETH_MACVR_SNPSVER_Pos                         (0U)
+#define ETH_MACVR_SNPSVER_Msk                         (0xFFUL << ETH_MACVR_SNPSVER_Pos) /*!< 0x000000FF */
+#define ETH_MACVR_SNPSVER                             ETH_MACVR_SNPSVER_Msk    /* Synopsys-defined Version */
+
+/* Bit definition for Ethernet MAC Debug Register */
+#define ETH_MACDR_TFCSTS_Pos                          (17U)
+#define ETH_MACDR_TFCSTS_Msk                          (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
+#define ETH_MACDR_TFCSTS                              ETH_MACDR_TFCSTS_Msk     /* MAC Transmit Packet Controller Status */
+#define ETH_MACDR_TFCSTS_IDLE                         ((uint32_t)0x00000000)   /* Idle state */
+#define ETH_MACDR_TFCSTS_WAIT_Pos                     (17U)
+#define ETH_MACDR_TFCSTS_WAIT_Msk                     (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
+#define ETH_MACDR_TFCSTS_WAIT                         ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
+#define ETH_MACDR_TFCSTS_GENERATEPCP_Pos              (18U)
+#define ETH_MACDR_TFCSTS_GENERATEPCP_Msk              (0x1UL << ETH_MACDR_TFCSTS_GENERATEPCP_Pos) /*!< 0x00040000 */
+#define ETH_MACDR_TFCSTS_GENERATEPCP                  ETH_MACDR_TFCSTS_GENERATEPCP_Msk /* Generating and transmitting a Pause control packet */
+#define ETH_MACDR_TFCSTS_TRASFERIP_Pos                (17U)
+#define ETH_MACDR_TFCSTS_TRASFERIP_Msk                (0x3UL << ETH_MACDR_TFCSTS_TRASFERIP_Pos) /*!< 0x00060000 */
+#define ETH_MACDR_TFCSTS_TRASFERIP                    ETH_MACDR_TFCSTS_TRASFERIP_Msk /* Transferring input packet for transmission */
+#define ETH_MACDR_TPESTS_Pos                          (16U)
+#define ETH_MACDR_TPESTS_Msk                          (0x1UL << ETH_MACDR_TPESTS_Pos) /*!< 0x00010000 */
+#define ETH_MACDR_TPESTS                              ETH_MACDR_TPESTS_Msk     /* MAC Receive Packet Controller FIFO Status */
+#define ETH_MACDR_RFCFCSTS_Pos                        (1U)
+#define ETH_MACDR_RFCFCSTS_Msk                        (0x3UL << ETH_MACDR_RFCFCSTS_Pos) /*!< 0x00000006 */
+#define ETH_MACDR_RFCFCSTS                            ETH_MACDR_RFCFCSTS_Msk   /* MAC MII Transmit Protocol Engine Status */
+#define ETH_MACDR_RPESTS_Pos                          (0U)
+#define ETH_MACDR_RPESTS_Msk                          (0x1UL << ETH_MACDR_RPESTS_Pos) /*!< 0x00000001 */
+#define ETH_MACDR_RPESTS                              ETH_MACDR_RPESTS_Msk     /* MAC MII Receive Protocol Engine Status */
+
+/* Bit definition for Ethernet MAC HW Feature0 Register */
+#define ETH_MACHWF0R_ACTPHYSEL_Pos                    (28U)
+#define ETH_MACHWF0R_ACTPHYSEL_Msk                    (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
+#define ETH_MACHWF0R_ACTPHYSEL                        ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
+#define ETH_MACHWF0R_ACTPHYSEL_MII                    ((uint32_t)0x00000000)   /* MII */
+#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos               (30U)
+#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk               (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
+#define ETH_MACHWF0R_ACTPHYSEL_RMII                   ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
+#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos             (28U)
+#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk             (0x7UL << ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos) /*!< 0x70000000 */
+#define ETH_MACHWF0R_ACTPHYSEL_REVMII                 ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk /* RevMII */
+#define ETH_MACHWF0R_SAVLANINS_Pos                    (27U)
+#define ETH_MACHWF0R_SAVLANINS_Msk                    (0x1UL << ETH_MACHWF0R_SAVLANINS_Pos) /*!< 0x08000000 */
+#define ETH_MACHWF0R_SAVLANINS                        ETH_MACHWF0R_SAVLANINS_Msk /* Source Address or VLAN Insertion Enable */
+#define ETH_MACHWF0R_TSSTSSEL_Pos                     (25U)
+#define ETH_MACHWF0R_TSSTSSEL_Msk                     (0x3UL << ETH_MACHWF0R_TSSTSSEL_Pos) /*!< 0x06000000 */
+#define ETH_MACHWF0R_TSSTSSEL                         ETH_MACHWF0R_TSSTSSEL_Msk /* Timestamp System Time Source */
+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos            (25U)
+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos) /*!< 0x02000000 */
+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL                ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk /* Timestamp System Time Source: Internal */
+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos            (26U)
+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos) /*!< 0x04000000 */
+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL                ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk /* Timestamp System Time Source: External */
+#define ETH_MACHWF0R_TSSTSSEL_BOTH_Pos                (25U)
+#define ETH_MACHWF0R_TSSTSSEL_BOTH_Msk                (0x3UL << ETH_MACHWF0R_TSSTSSEL_BOTH_Pos) /*!< 0x06000000 */
+#define ETH_MACHWF0R_TSSTSSEL_BOTH                    ETH_MACHWF0R_TSSTSSEL_BOTH_Msk /* Timestamp System Time Source: Internal & External */
+#define ETH_MACHWF0R_MACADR64SEL_Pos                  (24U)
+#define ETH_MACHWF0R_MACADR64SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR64SEL_Pos) /*!< 0x01000000 */
+#define ETH_MACHWF0R_MACADR64SEL                      ETH_MACHWF0R_MACADR64SEL_Msk /* MAC Addresses 64-127 Selected */
+#define ETH_MACHWF0R_MACADR32SEL_Pos                  (23U)
+#define ETH_MACHWF0R_MACADR32SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR32SEL_Pos) /*!< 0x00800000 */
+#define ETH_MACHWF0R_MACADR32SEL                      ETH_MACHWF0R_MACADR32SEL_Msk /* MAC Addresses 32-63 Selected */
+#define ETH_MACHWF0R_ADDMACADRSEL_Pos                 (18U)
+#define ETH_MACHWF0R_ADDMACADRSEL_Msk                 (0x1FUL << ETH_MACHWF0R_ADDMACADRSEL_Pos) /*!< 0x007C0000 */
+#define ETH_MACHWF0R_ADDMACADRSEL                     ETH_MACHWF0R_ADDMACADRSEL_Msk /* MAC Addresses 1- 31 Selected */
+#define ETH_MACHWF0R_RXCOESEL_Pos                     (16U)
+#define ETH_MACHWF0R_RXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_RXCOESEL_Pos) /*!< 0x00010000 */
+#define ETH_MACHWF0R_RXCOESEL                         ETH_MACHWF0R_RXCOESEL_Msk /* Receive Checksum Offload Enabled */
+#define ETH_MACHWF0R_TXCOESEL_Pos                     (14U)
+#define ETH_MACHWF0R_TXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_TXCOESEL_Pos) /*!< 0x00004000 */
+#define ETH_MACHWF0R_TXCOESEL                         ETH_MACHWF0R_TXCOESEL_Msk /* Transmit Checksum Offload Enabled */
+#define ETH_MACHWF0R_EEESEL_Pos                       (13U)
+#define ETH_MACHWF0R_EEESEL_Msk                       (0x1UL << ETH_MACHWF0R_EEESEL_Pos) /*!< 0x00002000 */
+#define ETH_MACHWF0R_EEESEL                           ETH_MACHWF0R_EEESEL_Msk  /* Energy Efficient Ethernet Enabled */
+#define ETH_MACHWF0R_TSSEL_Pos                        (12U)
+#define ETH_MACHWF0R_TSSEL_Msk                        (0x1UL << ETH_MACHWF0R_TSSEL_Pos) /*!< 0x00001000 */
+#define ETH_MACHWF0R_TSSEL                            ETH_MACHWF0R_TSSEL_Msk   /* IEEE 1588-2008 Timestamp Enabled */
+#define ETH_MACHWF0R_ARPOFFSEL_Pos                    (9U)
+#define ETH_MACHWF0R_ARPOFFSEL_Msk                    (0x1UL << ETH_MACHWF0R_ARPOFFSEL_Pos) /*!< 0x00000200 */
+#define ETH_MACHWF0R_ARPOFFSEL                        ETH_MACHWF0R_ARPOFFSEL_Msk /* ARP Offload Enabled */
+#define ETH_MACHWF0R_MMCSEL_Pos                       (8U)
+#define ETH_MACHWF0R_MMCSEL_Msk                       (0x1UL << ETH_MACHWF0R_MMCSEL_Pos) /*!< 0x00000100 */
+#define ETH_MACHWF0R_MMCSEL                           ETH_MACHWF0R_MMCSEL_Msk  /* RMON Module Enable */
+#define ETH_MACHWF0R_MGKSEL_Pos                       (7U)
+#define ETH_MACHWF0R_MGKSEL_Msk                       (0x1UL << ETH_MACHWF0R_MGKSEL_Pos) /*!< 0x00000080 */
+#define ETH_MACHWF0R_MGKSEL                           ETH_MACHWF0R_MGKSEL_Msk  /* PMT Magic Packet Enable */
+#define ETH_MACHWF0R_RWKSEL_Pos                       (6U)
+#define ETH_MACHWF0R_RWKSEL_Msk                       (0x1UL << ETH_MACHWF0R_RWKSEL_Pos) /*!< 0x00000040 */
+#define ETH_MACHWF0R_RWKSEL                           ETH_MACHWF0R_RWKSEL_Msk  /* PMT Remote Wake-up Packet Enable */
+#define ETH_MACHWF0R_SMASEL_Pos                       (5U)
+#define ETH_MACHWF0R_SMASEL_Msk                       (0x1UL << ETH_MACHWF0R_SMASEL_Pos) /*!< 0x00000020 */
+#define ETH_MACHWF0R_SMASEL                           ETH_MACHWF0R_SMASEL_Msk  /* SMA (MDIO) Interface */
+#define ETH_MACHWF0R_VLHASH_Pos                       (4U)
+#define ETH_MACHWF0R_VLHASH_Msk                       (0x1UL << ETH_MACHWF0R_VLHASH_Pos) /*!< 0x00000010 */
+#define ETH_MACHWF0R_VLHASH                           ETH_MACHWF0R_VLHASH_Msk  /* VLAN Hash Filter Selected */
+#define ETH_MACHWF0R_PCSSEL_Pos                       (3U)
+#define ETH_MACHWF0R_PCSSEL_Msk                       (0x1UL << ETH_MACHWF0R_PCSSEL_Pos) /*!< 0x00000008 */
+#define ETH_MACHWF0R_PCSSEL                           ETH_MACHWF0R_PCSSEL_Msk  /* PCS Registers (TBI, SGMII, or RTBI PHY interface) */
+#define ETH_MACHWF0R_HDSEL_Pos                        (2U)
+#define ETH_MACHWF0R_HDSEL_Msk                        (0x1UL << ETH_MACHWF0R_HDSEL_Pos) /*!< 0x00000004 */
+#define ETH_MACHWF0R_HDSEL                            ETH_MACHWF0R_HDSEL_Msk   /* Half-duplex Support */
+#define ETH_MACHWF0R_GMIISEL_Pos                      (1U)
+#define ETH_MACHWF0R_GMIISEL_Msk                      (0x1UL << ETH_MACHWF0R_GMIISEL_Pos) /*!< 0x00000002 */
+#define ETH_MACHWF0R_GMIISEL                          ETH_MACHWF0R_GMIISEL_Msk /* 1000 Mbps Support */
+#define ETH_MACHWF0R_MIISEL_Pos                       (0U)
+#define ETH_MACHWF0R_MIISEL_Msk                       (0x1UL << ETH_MACHWF0R_MIISEL_Pos) /*!< 0x00000001 */
+#define ETH_MACHWF0R_MIISEL                           ETH_MACHWF0R_MIISEL_Msk  /* 10 or 100 Mbps Support */
+
+/* Bit definition for Ethernet MAC HW Feature1 Register */
+#define ETH_MACHWF1R_L3L4FNUM_Pos                     (27U)
+#define ETH_MACHWF1R_L3L4FNUM_Msk                     (0xFUL << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x78000000 */
+#define ETH_MACHWF1R_L3L4FNUM                         ETH_MACHWF1R_L3L4FNUM_Msk /* Total number of L3 or L4 Filters */
+#define ETH_MACHWF1R_HASHTBLSZ_Pos                    (24U)
+#define ETH_MACHWF1R_HASHTBLSZ_Msk                    (0x3UL << ETH_MACHWF1R_HASHTBLSZ_Pos) /*!< 0x03000000 */
+#define ETH_MACHWF1R_HASHTBLSZ                        ETH_MACHWF1R_HASHTBLSZ_Msk /* Hash Table Size */
+#define ETH_MACHWF1R_AVSEL_Pos                        (20U)
+#define ETH_MACHWF1R_AVSEL_Msk                        (0x1UL << ETH_MACHWF1R_AVSEL_Pos) /*!< 0x00100000 */
+#define ETH_MACHWF1R_AVSEL                            ETH_MACHWF1R_AVSEL_Msk   /* AV Feature Enabled */
+#define ETH_MACHWF1R_DBGMEMA_Pos                      (19U)
+#define ETH_MACHWF1R_DBGMEMA_Msk                      (0x1UL << ETH_MACHWF1R_DBGMEMA_Pos) /*!< 0x00080000 */
+#define ETH_MACHWF1R_DBGMEMA                          ETH_MACHWF1R_DBGMEMA_Msk /* Debug Memory Interface Enabled */
+#define ETH_MACHWF1R_TSOEN_Pos                        (18U)
+#define ETH_MACHWF1R_TSOEN_Msk                        (0x1UL << ETH_MACHWF1R_TSOEN_Pos) /*!< 0x00040000 */
+#define ETH_MACHWF1R_TSOEN                            ETH_MACHWF1R_TSOEN_Msk   /* TCP Segmentation Offload Enable */
+#define ETH_MACHWF1R_SPHEN_Pos                        (17U)
+#define ETH_MACHWF1R_SPHEN_Msk                        (0x1UL << ETH_MACHWF1R_SPHEN_Pos) /*!< 0x00020000 */
+#define ETH_MACHWF1R_SPHEN                            ETH_MACHWF1R_SPHEN_Msk   /* Split Header Feature Enable */
+#define ETH_MACHWF1R_DCBEN_Pos                        (16U)
+#define ETH_MACHWF1R_DCBEN_Msk                        (0x1UL << ETH_MACHWF1R_DCBEN_Pos) /*!< 0x00010000 */
+#define ETH_MACHWF1R_DCBEN                            ETH_MACHWF1R_DCBEN_Msk   /* DCB Feature Enable */
+#define ETH_MACHWF1R_ADDR64_Pos                       (14U)
+#define ETH_MACHWF1R_ADDR64_Msk                       (0x3UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x0000C000 */
+#define ETH_MACHWF1R_ADDR64                           ETH_MACHWF1R_ADDR64_Msk  /* Address Width */
+#define ETH_MACHWF1R_ADDR64_32                        (0x0UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00000000 */
+#define ETH_MACHWF1R_ADDR64_40                        (0x1UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00004000 */
+#define ETH_MACHWF1R_ADDR64_48                        (0x2UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00008000 */
+#define ETH_MACHWF1R_ADVTHWORD_Pos                    (13U)
+#define ETH_MACHWF1R_ADVTHWORD_Msk                    (0x1UL << ETH_MACHWF1R_ADVTHWORD_Pos) /*!< 0x00002000 */
+#define ETH_MACHWF1R_ADVTHWORD                        ETH_MACHWF1R_ADVTHWORD_Msk /* IEEE 1588 High Word Register Enable */
+#define ETH_MACHWF1R_PTOEN_Pos                        (12U)
+#define ETH_MACHWF1R_PTOEN_Msk                        (0x1UL << ETH_MACHWF1R_PTOEN_Pos) /*!< 0x00001000 */
+#define ETH_MACHWF1R_PTOEN                            ETH_MACHWF1R_PTOEN_Msk   /* PTP Offload Enable */
+#define ETH_MACHWF1R_OSTEN_Pos                        (11U)
+#define ETH_MACHWF1R_OSTEN_Msk                        (0x1UL << ETH_MACHWF1R_OSTEN_Pos) /*!< 0x00000800 */
+#define ETH_MACHWF1R_OSTEN                            ETH_MACHWF1R_OSTEN_Msk   /* One-Step Timestamping Enable */
+#define ETH_MACHWF1R_TXFIFOSIZE_Pos                   (6U)
+#define ETH_MACHWF1R_TXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x000007C0 */
+#define ETH_MACHWF1R_TXFIFOSIZE                       ETH_MACHWF1R_TXFIFOSIZE_Msk /* MTL Transmit FIFO Size */
+#define ETH_MACHWF1R_RXFIFOSIZE_Pos                   (0U)
+#define ETH_MACHWF1R_RXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x0000001F */
+#define ETH_MACHWF1R_RXFIFOSIZE                       ETH_MACHWF1R_RXFIFOSIZE_Msk /* MTL Receive FIFO Size */
+
+/* Bit definition for Ethernet MAC HW Feature2 Register */
+#define ETH_MACHWF2R_AUXSNAPNUM_Pos                   (28U)
+#define ETH_MACHWF2R_AUXSNAPNUM_Msk                   (0x7UL << ETH_MACHWF2R_AUXSNAPNUM_Pos) /*!< 0x70000000 */
+#define ETH_MACHWF2R_AUXSNAPNUM                       ETH_MACHWF2R_AUXSNAPNUM_Msk /* Number of Auxiliary Snapshot Inputs */
+#define ETH_MACHWF2R_PPSOUTNUM_Pos                    (24U)
+#define ETH_MACHWF2R_PPSOUTNUM_Msk                    (0x7UL << ETH_MACHWF2R_PPSOUTNUM_Pos) /*!< 0x07000000 */
+#define ETH_MACHWF2R_PPSOUTNUM                        ETH_MACHWF2R_PPSOUTNUM_Msk /*  Number of PPS Outputs */
+#define ETH_MACHWF2R_TXCHCNT_Pos                      (18U)
+#define ETH_MACHWF2R_TXCHCNT_Msk                      (0xFUL << ETH_MACHWF2R_TXCHCNT_Pos) /*!< 0x003C0000 */
+#define ETH_MACHWF2R_TXCHCNT                          ETH_MACHWF2R_TXCHCNT_Msk /* Number of DMA Transmit Channels */
+#define ETH_MACHWF2R_RXCHCNT_Pos                      (13U)
+#define ETH_MACHWF2R_RXCHCNT_Msk                      (0x7UL << ETH_MACHWF2R_RXCHCNT_Pos) /*!< 0x0000E000 */
+#define ETH_MACHWF2R_RXCHCNT                          ETH_MACHWF2R_RXCHCNT_Msk /* Number of DMA Receive Channels */
+#define ETH_MACHWF2R_TXQCNT_Pos                       (6U)
+#define ETH_MACHWF2R_TXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_TXQCNT_Pos) /*!< 0x000003C0 */
+#define ETH_MACHWF2R_TXQCNT                           ETH_MACHWF2R_TXQCNT_Msk  /* Number of MTL Transmit Queues */
+#define ETH_MACHWF2R_RXQCNT_Pos                       (0U)
+#define ETH_MACHWF2R_RXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_RXQCNT_Pos) /*!< 0x0000000F */
+#define ETH_MACHWF2R_RXQCNT                           ETH_MACHWF2R_RXQCNT_Msk  /* Number of MTL Receive Queues */
+
+/* Bit definition for Ethernet MAC MDIO Address Register */
+#define ETH_MACMDIOAR_PSE_Pos                         (27U)
+#define ETH_MACMDIOAR_PSE_Msk                         (0x1UL << ETH_MACMDIOAR_PSE_Pos) /*!< 0x08000000 */
+#define ETH_MACMDIOAR_PSE                             ETH_MACMDIOAR_PSE_Msk    /* Preamble Suppression Enable */
+#define ETH_MACMDIOAR_BTB_Pos                         (26U)
+#define ETH_MACMDIOAR_BTB_Msk                         (0x1UL << ETH_MACMDIOAR_BTB_Pos) /*!< 0x04000000 */
+#define ETH_MACMDIOAR_BTB                             ETH_MACMDIOAR_BTB_Msk    /* Back to Back transactions */
+#define ETH_MACMDIOAR_PA_Pos                          (21U)
+#define ETH_MACMDIOAR_PA_Msk                          (0x1FUL << ETH_MACMDIOAR_PA_Pos) /*!< 0x03E00000 */
+#define ETH_MACMDIOAR_PA                              ETH_MACMDIOAR_PA_Msk     /* Physical Layer Address */
+#define ETH_MACMDIOAR_RDA_Pos                         (16U)
+#define ETH_MACMDIOAR_RDA_Msk                         (0x1FUL << ETH_MACMDIOAR_RDA_Pos) /*!< 0x001F0000 */
+#define ETH_MACMDIOAR_RDA                             ETH_MACMDIOAR_RDA_Msk    /* Register/Device Address */
+#define ETH_MACMDIOAR_NTC_Pos                         (12U)
+#define ETH_MACMDIOAR_NTC_Msk                         (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */
+#define ETH_MACMDIOAR_NTC                             ETH_MACMDIOAR_NTC_Msk    /* Number of Trailing Clocks */
+#define ETH_MACMDIOAR_CR_Pos                          (8U)
+#define ETH_MACMDIOAR_CR_Msk                          (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
+#define ETH_MACMDIOAR_CR                              ETH_MACMDIOAR_CR_Msk     /* CSR Clock Range */
+#define ETH_MACMDIOAR_CR_DIV42                        ((uint32_t)0x00000000)   /* CSR clock/42 */
+#define ETH_MACMDIOAR_CR_DIV62_Pos                    (8U)
+#define ETH_MACMDIOAR_CR_DIV62_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
+#define ETH_MACMDIOAR_CR_DIV62                        ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
+#define ETH_MACMDIOAR_CR_DIV16_Pos                    (9U)
+#define ETH_MACMDIOAR_CR_DIV16_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV16_Pos) /*!< 0x00000200 */
+#define ETH_MACMDIOAR_CR_DIV16                        ETH_MACMDIOAR_CR_DIV16_Msk /* CSR clock/16 */
+#define ETH_MACMDIOAR_CR_DIV26_Pos                    (8U)
+#define ETH_MACMDIOAR_CR_DIV26_Msk                    (0x3UL << ETH_MACMDIOAR_CR_DIV26_Pos) /*!< 0x00000300 */
+#define ETH_MACMDIOAR_CR_DIV26                        ETH_MACMDIOAR_CR_DIV26_Msk /* CSR clock/26 */
+#define ETH_MACMDIOAR_CR_DIV102_Pos                   (10U)
+#define ETH_MACMDIOAR_CR_DIV102_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV102_Pos) /*!< 0x00000400 */
+#define ETH_MACMDIOAR_CR_DIV102                       ETH_MACMDIOAR_CR_DIV102_Msk /* CSR clock/102 */
+#define ETH_MACMDIOAR_CR_DIV124_Pos                   (8U)
+#define ETH_MACMDIOAR_CR_DIV124_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV124_Pos) /*!< 0x00000500 */
+#define ETH_MACMDIOAR_CR_DIV124                       ETH_MACMDIOAR_CR_DIV124_Msk /* CSR clock/124 */
+#define ETH_MACMDIOAR_CR_DIV4AR_Pos                   (11U)
+#define ETH_MACMDIOAR_CR_DIV4AR_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV4AR_Pos) /*!< 0x00000800 */
+#define ETH_MACMDIOAR_CR_DIV4AR                       ETH_MACMDIOAR_CR_DIV4AR_Msk /* CSR clock/4: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV6AR_Pos                   (8U)
+#define ETH_MACMDIOAR_CR_DIV6AR_Msk                   (0x9UL << ETH_MACMDIOAR_CR_DIV6AR_Pos) /*!< 0x00000900 */
+#define ETH_MACMDIOAR_CR_DIV6AR                       ETH_MACMDIOAR_CR_DIV6AR_Msk /* CSR clock/6: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV8AR_Pos                   (9U)
+#define ETH_MACMDIOAR_CR_DIV8AR_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV8AR_Pos) /*!< 0x00000A00 */
+#define ETH_MACMDIOAR_CR_DIV8AR                       ETH_MACMDIOAR_CR_DIV8AR_Msk /* CSR clock/8: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV10AR_Pos                  (8U)
+#define ETH_MACMDIOAR_CR_DIV10AR_Msk                  (0xBUL << ETH_MACMDIOAR_CR_DIV10AR_Pos) /*!< 0x00000B00 */
+#define ETH_MACMDIOAR_CR_DIV10AR                      ETH_MACMDIOAR_CR_DIV10AR_Msk /* CSR clock/10: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV12AR_Pos                  (10U)
+#define ETH_MACMDIOAR_CR_DIV12AR_Msk                  (0x3UL << ETH_MACMDIOAR_CR_DIV12AR_Pos) /*!< 0x00000C00 */
+#define ETH_MACMDIOAR_CR_DIV12AR                      ETH_MACMDIOAR_CR_DIV12AR_Msk /* CSR clock/12: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV14AR_Pos                  (8U)
+#define ETH_MACMDIOAR_CR_DIV14AR_Msk                  (0xDUL << ETH_MACMDIOAR_CR_DIV14AR_Pos) /*!< 0x00000D00 */
+#define ETH_MACMDIOAR_CR_DIV14AR                      ETH_MACMDIOAR_CR_DIV14AR_Msk /* CSR clock/14: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV16AR_Pos                  (9U)
+#define ETH_MACMDIOAR_CR_DIV16AR_Msk                  (0x7UL << ETH_MACMDIOAR_CR_DIV16AR_Pos) /*!< 0x00000E00 */
+#define ETH_MACMDIOAR_CR_DIV16AR                      ETH_MACMDIOAR_CR_DIV16AR_Msk /* CSR clock/16: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV18AR_Pos                  (8U)
+#define ETH_MACMDIOAR_CR_DIV18AR_Msk                  (0xFUL << ETH_MACMDIOAR_CR_DIV18AR_Pos) /*!< 0x00000F00 */
+#define ETH_MACMDIOAR_CR_DIV18AR                      ETH_MACMDIOAR_CR_DIV18AR_Msk /* CSR clock/18: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_SKAP_Pos                        (4U)
+#define ETH_MACMDIOAR_SKAP_Msk                        (0x1UL << ETH_MACMDIOAR_SKAP_Pos) /*!< 0x00000010 */
+#define ETH_MACMDIOAR_SKAP                            ETH_MACMDIOAR_SKAP_Msk   /* Skip Address Packet */
+#define ETH_MACMDIOAR_MOC_Pos                         (2U)
+#define ETH_MACMDIOAR_MOC_Msk                         (0x3UL << ETH_MACMDIOAR_MOC_Pos) /*!< 0x0000000C */
+#define ETH_MACMDIOAR_MOC                             ETH_MACMDIOAR_MOC_Msk    /* MII Operation Command */
+#define ETH_MACMDIOAR_MOC_WR_Pos                      (2U)
+#define ETH_MACMDIOAR_MOC_WR_Msk                      (0x1UL << ETH_MACMDIOAR_MOC_WR_Pos) /*!< 0x00000004 */
+#define ETH_MACMDIOAR_MOC_WR                          ETH_MACMDIOAR_MOC_WR_Msk /* Write */
+#define ETH_MACMDIOAR_MOC_PRDIA_Pos                   (3U)
+#define ETH_MACMDIOAR_MOC_PRDIA_Msk                   (0x1UL << ETH_MACMDIOAR_MOC_PRDIA_Pos) /*!< 0x00000008 */
+#define ETH_MACMDIOAR_MOC_PRDIA                       ETH_MACMDIOAR_MOC_PRDIA_Msk /* Post Read Increment Address for Clause 45 PHY */
+#define ETH_MACMDIOAR_MOC_RD_Pos                      (2U)
+#define ETH_MACMDIOAR_MOC_RD_Msk                      (0x3UL << ETH_MACMDIOAR_MOC_RD_Pos) /*!< 0x0000000C */
+#define ETH_MACMDIOAR_MOC_RD                          ETH_MACMDIOAR_MOC_RD_Msk /* Read */
+#define ETH_MACMDIOAR_C45E_Pos                        (1U)
+#define ETH_MACMDIOAR_C45E_Msk                        (0x1UL << ETH_MACMDIOAR_C45E_Pos) /*!< 0x00000002 */
+#define ETH_MACMDIOAR_C45E                            ETH_MACMDIOAR_C45E_Msk   /* Clause 45 PHY Enable */
+#define ETH_MACMDIOAR_MB_Pos                          (0U)
+#define ETH_MACMDIOAR_MB_Msk                          (0x1UL << ETH_MACMDIOAR_MB_Pos) /*!< 0x00000001 */
+#define ETH_MACMDIOAR_MB                              ETH_MACMDIOAR_MB_Msk     /* MII Busy */
+
+/* Bit definition for Ethernet MAC MDIO Data Register */
+#define ETH_MACMDIODR_RA_Pos                          (16U)
+#define ETH_MACMDIODR_RA_Msk                          (0xFFFFUL << ETH_MACMDIODR_RA_Pos) /*!< 0xFFFF0000 */
+#define ETH_MACMDIODR_RA                              ETH_MACMDIODR_RA_Msk     /* Register Address */
+#define ETH_MACMDIODR_MD_Pos                          (0U)
+#define ETH_MACMDIODR_MD_Msk                          (0xFFFFUL << ETH_MACMDIODR_MD_Pos) /*!< 0x0000FFFF */
+#define ETH_MACMDIODR_MD                              ETH_MACMDIODR_MD_Msk     /* MII Data */
+
+/* Bit definition for Ethernet ARP Address Register */
+#define ETH_MACARPAR_ARPPA_Pos                         (0U)
+#define ETH_MACARPAR_ARPPA_Msk                         (0xFFFFFFFFUL << ETH_MACARPAR_ARPPA_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACARPAR_ARPPA                             ETH_MACARPAR_ARPPA_Msk     /* ARP Protocol Address */
+
+/* Bit definition for Ethernet MAC Address 0 High Register */
+#define ETH_MACA0HR_AE_Pos                            (31U)
+#define ETH_MACA0HR_AE_Msk                            (0x1UL << ETH_MACA0HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA0HR_AE                                ETH_MACA0HR_AE_Msk /* Address Enable*/
+#define ETH_MACA0HR_ADDRHI_Pos                        (0U)
+#define ETH_MACA0HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA0HR_ADDRHI                            ETH_MACA0HR_ADDRHI_Msk   /* MAC Address 0*/
+
+/* Bit definition for Ethernet MAC Address 0 Low Register */
+#define ETH_MACA0LR_ADDRLO_Pos                        (0U)
+#define ETH_MACA0LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA0LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA0LR_ADDRLO                            ETH_MACA0LR_ADDRLO_Msk   /* MAC Address 0*/
+
+/* Bit definition for Ethernet MAC Address 1 High Register */
+#define ETH_MACA1HR_AE_Pos                            (31U)
+#define ETH_MACA1HR_AE_Msk                            (0x1UL << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA1HR_AE                                ETH_MACA1HR_AE_Msk /* Address Enable*/
+#define ETH_MACA1HR_SA_Pos                            (30U)
+#define ETH_MACA1HR_SA_Msk                            (0x1UL << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA1HR_SA                                ETH_MACA1HR_SA_Msk /* Source Address */
+#define ETH_MACA1HR_MBC_Pos                           (24U)
+#define ETH_MACA1HR_MBC_Msk                           (0x3FUL << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA1HR_MBC                               ETH_MACA1HR_MBC_Msk /* Mask Byte Control */
+#define ETH_MACA1HR_ADDRHI_Pos                        (0U)
+#define ETH_MACA1HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA1HR_ADDRHI                            ETH_MACA1HR_ADDRHI_Msk   /* MAC Address 1*/
+
+/* Bit definition for Ethernet MAC Address 1 Low Register */
+#define ETH_MACA1LR_ADDRLO_Pos                        (0U)
+#define ETH_MACA1LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA1LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA1LR_ADDRLO                            ETH_MACA1LR_ADDRLO_Msk   /* MAC Address 1*/
+
+/* Bit definition for Ethernet MAC Address 2 High Register */
+#define ETH_MACA2HR_AE_Pos                            (31U)
+#define ETH_MACA2HR_AE_Msk                            (0x1UL << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA2HR_AE                                ETH_MACA2HR_AE_Msk /* Address Enable*/
+#define ETH_MACA2HR_SA_Pos                            (30U)
+#define ETH_MACA2HR_SA_Msk                            (0x1UL << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA2HR_SA                                ETH_MACA2HR_SA_Msk /* Source Address */
+#define ETH_MACA2HR_MBC_Pos                           (24U)
+#define ETH_MACA2HR_MBC_Msk                           (0x3FUL << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA2HR_MBC                               ETH_MACA2HR_MBC_Msk /* Mask Byte Control */
+#define ETH_MACA2HR_ADDRHI_Pos                        (0U)
+#define ETH_MACA2HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA2HR_ADDRHI                            ETH_MACA2HR_ADDRHI_Msk   /* MAC Address 1*/
+
+/* Bit definition for Ethernet MAC Address 2 Low Register */
+#define ETH_MACA2LR_ADDRLO_Pos                        (0U)
+#define ETH_MACA2LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA2LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA2LR_ADDRLO                            ETH_MACA2LR_ADDRLO_Msk   /* MAC Address 2*/
+
+/* Bit definition for Ethernet MAC Address 3 High Register */
+#define ETH_MACA3HR_AE_Pos                            (31U)
+#define ETH_MACA3HR_AE_Msk                            (0x1UL << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA3HR_AE                                ETH_MACA3HR_AE_Msk /* Address Enable*/
+#define ETH_MACA3HR_SA_Pos                            (30U)
+#define ETH_MACA3HR_SA_Msk                            (0x1UL << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA3HR_SA                                ETH_MACA3HR_SA_Msk /* Source Address */
+#define ETH_MACA3HR_MBC_Pos                           (24U)
+#define ETH_MACA3HR_MBC_Msk                           (0x3FUL << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA3HR_MBC                               ETH_MACA3HR_MBC_Msk /* Mask Byte Control */
+#define ETH_MACA3HR_ADDRHI_Pos                        (0U)
+#define ETH_MACA3HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA3HR_ADDRHI                            ETH_MACA3HR_ADDRHI_Msk   /* MAC Address 1*/
+
+/* Bit definition for Ethernet MAC Address 3 Low Register */
+#define ETH_MACA3LR_ADDRLO_Pos                        (0U)
+#define ETH_MACA3LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA3LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA3LR_ADDRLO                            ETH_MACA3LR_ADDRLO_Msk   /* MAC Address 3*/
+
+/* Bit definition for Ethernet MAC Address High Register */
+#define ETH_MACAHR_AE_Pos                             (31U)
+#define ETH_MACAHR_AE_Msk                             (0x1UL << ETH_MACAHR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACAHR_AE                                 ETH_MACAHR_AE_Msk        /* Address enable */
+#define ETH_MACAHR_SA_Pos                             (30U)
+#define ETH_MACAHR_SA_Msk                             (0x1UL << ETH_MACAHR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACAHR_SA                                 ETH_MACAHR_SA_Msk        /* Source address */
+#define ETH_MACAHR_MBC_Pos                            (24U)
+#define ETH_MACAHR_MBC_Msk                            (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACAHR_MBC                                ETH_MACAHR_MBC_Msk       /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+#define ETH_MACAHR_MBC_HBITS15_8                      ((uint32_t)0x20000000)   /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACAHR_MBC_HBITS7_0                       ((uint32_t)0x10000000)   /* Mask MAC Address high reg bits [7:0] */
+#define ETH_MACAHR_MBC_LBITS31_24                     ((uint32_t)0x08000000)   /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACAHR_MBC_LBITS23_16                     ((uint32_t)0x04000000)   /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACAHR_MBC_LBITS15_8                      ((uint32_t)0x02000000)   /* Mask MAC Address low reg bits [15:8] */
+#define ETH_MACAHR_MBC_LBITS7_0                       ((uint32_t)0x01000000)   /* Mask MAC Address low reg bits [7:0] */
+#define ETH_MACAHR_MACAH_Pos                          (0U)
+#define ETH_MACAHR_MACAH_Msk                          (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */
+#define ETH_MACAHR_MACAH                              ETH_MACAHR_MACAH_Msk     /* MAC address high */
+
+/* Bit definition for Ethernet MAC Address Low Register */
+#define ETH_MACALR_MACAL_Pos                          (0U)
+#define ETH_MACALR_MACAL_Msk                          (0xFFFFFFFFUL << ETH_MACALR_MACAL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACALR_MACAL                              ETH_MACALR_MACAL_Msk     /* MAC address low */
+
+/* Bit definition for Ethernet MMC Control Register */
+#define ETH_MMCCR_UCDBC_Pos                           (8U)
+#define ETH_MMCCR_UCDBC_Msk                           (0x1UL << ETH_MMCCR_UCDBC_Pos) /*!< 0x00000100 */
+#define ETH_MMCCR_UCDBC                               ETH_MMCCR_UCDBC_Msk  /* Update MMC Counters for Dropped Broadcast Packets */
+#define ETH_MMCCR_CNTPRSTLVL_Pos                      (5U)
+#define ETH_MMCCR_CNTPRSTLVL_Msk                      (0x1UL << ETH_MMCCR_CNTPRSTLVL_Pos) /*!< 0x00000020 */
+#define ETH_MMCCR_CNTPRSTLVL                          ETH_MMCCR_CNTPRSTLVL_Msk  /* Full-Half Preset */
+#define ETH_MMCCR_CNTPRST_Pos                         (4U)
+#define ETH_MMCCR_CNTPRST_Msk                         (0x1UL << ETH_MMCCR_CNTPRST_Pos) /*!< 0x00000010 */
+#define ETH_MMCCR_CNTPRST                             ETH_MMCCR_CNTPRST_Msk  /* Counters Reset */
+#define ETH_MMCCR_CNTFREEZ_Pos                        (3U)
+#define ETH_MMCCR_CNTFREEZ_Msk                        (0x1UL << ETH_MMCCR_CNTFREEZ_Pos) /*!< 0x00000008 */
+#define ETH_MMCCR_CNTFREEZ                            ETH_MMCCR_CNTFREEZ_Msk  /* MMC Counter Freeze */
+#define ETH_MMCCR_RSTONRD_Pos                         (2U)
+#define ETH_MMCCR_RSTONRD_Msk                         (0x1UL << ETH_MMCCR_RSTONRD_Pos) /*!< 0x00000004 */
+#define ETH_MMCCR_RSTONRD                             ETH_MMCCR_RSTONRD_Msk  /* Reset On Read */
+#define ETH_MMCCR_CNTSTOPRO_Pos                       (1U)
+#define ETH_MMCCR_CNTSTOPRO_Msk                       (0x1UL << ETH_MMCCR_CNTSTOPRO_Pos) /*!< 0x00000002 */
+#define ETH_MMCCR_CNTSTOPRO                           ETH_MMCCR_CNTSTOPRO_Msk  /* Counter Stop Rollover */
+#define ETH_MMCCR_CNTRST_Pos                          (0U)
+#define ETH_MMCCR_CNTRST_Msk                          (0x1UL << ETH_MMCCR_CNTRST_Pos) /*!< 0x00000001 */
+#define ETH_MMCCR_CNTRST                              ETH_MMCCR_CNTRST_Msk  /* Counters Reset */
+
+/* Bit definition for Ethernet MMC Rx Interrupt Register */
+#define ETH_MMCRIR_RXLPITRCIS_Pos                     (27U)
+#define ETH_MMCRIR_RXLPITRCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPITRCIS_Pos) /*!< 0x08000000 */
+#define ETH_MMCRIR_RXLPITRCIS                         ETH_MMCRIR_RXLPITRCIS_Msk  /* MMC Receive LPI transition counter interrupt status */
+#define ETH_MMCRIR_RXLPIUSCIS_Pos                     (26U)
+#define ETH_MMCRIR_RXLPIUSCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPIUSCIS_Pos) /*!< 0x04000000 */
+#define ETH_MMCRIR_RXLPIUSCIS                         ETH_MMCRIR_RXLPIUSCIS_Msk  /* MMC Receive LPI microsecond counter interrupt status */
+#define ETH_MMCRIR_RXUCGPIS_Pos                       (17U)
+#define ETH_MMCRIR_RXUCGPIS_Msk                       (0x1UL << ETH_MMCRIR_RXUCGPIS_Pos) /*!< 0x00020000 */
+#define ETH_MMCRIR_RXUCGPIS                           ETH_MMCRIR_RXUCGPIS_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Status */
+#define ETH_MMCRIR_RXALGNERPIS_Pos                    (6U)
+#define ETH_MMCRIR_RXALGNERPIS_Msk                    (0x1UL << ETH_MMCRIR_RXALGNERPIS_Pos) /*!< 0x00000040 */
+#define ETH_MMCRIR_RXALGNERPIS                        ETH_MMCRIR_RXALGNERPIS_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Status */
+#define ETH_MMCRIR_RXCRCERPIS_Pos                     (5U)
+#define ETH_MMCRIR_RXCRCERPIS_Msk                     (0x1UL << ETH_MMCRIR_RXCRCERPIS_Pos) /*!< 0x00000020 */
+#define ETH_MMCRIR_RXCRCERPIS                         ETH_MMCRIR_RXCRCERPIS_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Status */
+
+/* Bit definition for Ethernet MMC Tx Interrupt Register */
+#define ETH_MMCTIR_TXLPITRCIS_Pos                     (27U)
+#define ETH_MMCTIR_TXLPITRCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPITRCIS_Pos) /*!< 0x08000000 */
+#define ETH_MMCTIR_TXLPITRCIS                         ETH_MMCTIR_TXLPITRCIS_Msk  /* MMC Transmit LPI transition counter interrupt status */
+#define ETH_MMCTIR_TXLPIUSCIS_Pos                     (26U)
+#define ETH_MMCTIR_TXLPIUSCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPIUSCIS_Pos) /*!< 0x04000000 */
+#define ETH_MMCTIR_TXLPIUSCIS                         ETH_MMCTIR_TXLPIUSCIS_Msk  /* MMC Transmit LPI microsecond counter interrupt status */
+#define ETH_MMCTIR_TXGPKTIS_Pos                       (21U)
+#define ETH_MMCTIR_TXGPKTIS_Msk                       (0x1UL << ETH_MMCTIR_TXGPKTIS_Pos) /*!< 0x00200000 */
+#define ETH_MMCTIR_TXGPKTIS                           ETH_MMCTIR_TXGPKTIS_Msk  /* MMC Transmit Good Packet Counter Interrupt Status */
+#define ETH_MMCTIR_TXMCOLGPIS_Pos                     (15U)
+#define ETH_MMCTIR_TXMCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXMCOLGPIS_Pos) /*!< 0x00008000 */
+#define ETH_MMCTIR_TXMCOLGPIS                         ETH_MMCTIR_TXMCOLGPIS_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Status */
+#define ETH_MMCTIR_TXSCOLGPIS_Pos                     (14U)
+#define ETH_MMCTIR_TXSCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXSCOLGPIS_Pos) /*!< 0x00004000 */
+#define ETH_MMCTIR_TXSCOLGPIS                         ETH_MMCTIR_TXSCOLGPIS_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Status */
+
+/* Bit definition for Ethernet MMC Rx interrupt Mask register */
+#define ETH_MMCRIMR_RXLPITRCIM_Pos                    (27U)
+#define ETH_MMCRIMR_RXLPITRCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPITRCIM_Pos) /*!< 0x08000000 */
+#define ETH_MMCRIMR_RXLPITRCIM                        ETH_MMCRIMR_RXLPITRCIM_Msk  /* MMC Receive LPI transition counter interrupt Mask */
+#define ETH_MMCRIMR_RXLPIUSCIM_Pos                    (26U)
+#define ETH_MMCRIMR_RXLPIUSCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPIUSCIM_Pos) /*!< 0x04000000 */
+#define ETH_MMCRIMR_RXLPIUSCIM                        ETH_MMCRIMR_RXLPIUSCIM_Msk  /* MMC Receive LPI microsecond counter interrupt Mask */
+#define ETH_MMCRIMR_RXUCGPIM_Pos                      (17U)
+#define ETH_MMCRIMR_RXUCGPIM_Msk                      (0x1UL << ETH_MMCRIMR_RXUCGPIM_Pos) /*!< 0x00020000 */
+#define ETH_MMCRIMR_RXUCGPIM                          ETH_MMCRIMR_RXUCGPIM_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Mask */
+#define ETH_MMCRIMR_RXALGNERPIM_Pos                   (6U)
+#define ETH_MMCRIMR_RXALGNERPIM_Msk                   (0x1UL << ETH_MMCRIMR_RXALGNERPIM_Pos) /*!< 0x00000040 */
+#define ETH_MMCRIMR_RXALGNERPIM                       ETH_MMCRIMR_RXALGNERPIM_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Mask */
+#define ETH_MMCRIMR_RXCRCERPIM_Pos                    (5U)
+#define ETH_MMCRIMR_RXCRCERPIM_Msk                    (0x1UL << ETH_MMCRIMR_RXCRCERPIM_Pos) /*!< 0x00000020 */
+#define ETH_MMCRIMR_RXCRCERPIM                        ETH_MMCRIMR_RXCRCERPIM_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Mask */
+
+/* Bit definition for Ethernet MMC Tx Interrupt Mask Register */
+#define ETH_MMCTIMR_TXLPITRCIM_Pos                    (27U)
+#define ETH_MMCTIMR_TXLPITRCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */
+#define ETH_MMCTIMR_TXLPITRCIM                        ETH_MMCTIMR_TXLPITRCIM_Msk  /* MMC Transmit LPI transition counter interrupt Mask*/
+#define ETH_MMCTIMR_TXLPIUSCIM_Pos                    (26U)
+#define ETH_MMCTIMR_TXLPIUSCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPIUSCIM_Pos) /*!< 0x04000000 */
+#define ETH_MMCTIMR_TXLPIUSCIM                        ETH_MMCTIMR_TXLPIUSCIM_Msk  /* MMC Transmit LPI microsecond counter interrupt Mask*/
+#define ETH_MMCTIMR_TXGPKTIM_Pos                      (21U)
+#define ETH_MMCTIMR_TXGPKTIM_Msk                      (0x1UL << ETH_MMCTIMR_TXGPKTIM_Pos) /*!< 0x00200000 */
+#define ETH_MMCTIMR_TXGPKTIM                          ETH_MMCTIMR_TXGPKTIM_Msk  /* MMC Transmit Good Packet Counter Interrupt Mask*/
+#define ETH_MMCTIMR_TXMCOLGPIM_Pos                    (15U)
+#define ETH_MMCTIMR_TXMCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXMCOLGPIM_Pos) /*!< 0x00008000 */
+#define ETH_MMCTIMR_TXMCOLGPIM                        ETH_MMCTIMR_TXMCOLGPIM_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask */
+#define ETH_MMCTIMR_TXSCOLGPIM_Pos                    (14U)
+#define ETH_MMCTIMR_TXSCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXSCOLGPIM_Pos) /*!< 0x00004000 */
+#define ETH_MMCTIMR_TXSCOLGPIM                        ETH_MMCTIMR_TXSCOLGPIM_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Mask */
+
+/* Bit definition for Ethernet MMC Tx Single Collision Good Packets Register */
+#define ETH_MMCTSCGPR_TXSNGLCOLG_Pos                  (0U)
+#define ETH_MMCTSCGPR_TXSNGLCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTSCGPR_TXSNGLCOLG_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTSCGPR_TXSNGLCOLG                      ETH_MMCTSCGPR_TXSNGLCOLG_msk /* Tx Single Collision Good Packets */
+
+/* Bit definition for Ethernet MMC Tx Multiple Collision Good Packets Register */
+#define ETH_MMCTMCGPR_TXMULTCOLG_Pos                  (0U)
+#define ETH_MMCTMCGPR_TXMULTCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTMCGPR_TXMULTCOLG_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTMCGPR_TXMULTCOLG                      ETH_MMCTMCGPR_TXMULTCOLG_msk /* Tx Multiple Collision Good Packets */
+
+/* Bit definition for Ethernet MMC Tx Packet Count Good Register */
+#define ETH_MMCTPCGR_TXPKTG_Pos                       (0U)
+#define ETH_MMCTPCGR_TXPKTG_msk                       (0xFFFFFFFFUL <<  ETH_MMCTPCGR_TXPKTG_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTPCGR_TXPKTG                           ETH_MMCTPCGR_TXPKTG_msk /* Tx Packet Count Good */
+
+/* Bit definition for Ethernet MMC Rx CRC Error Packets Register */
+#define ETH_MMCRCRCEPR_RXCRCERR_Pos                   (0U)
+#define ETH_MMCRCRCEPR_RXCRCERR_msk                   (0xFFFFFFFFUL <<  ETH_MMCRCRCEPR_RXCRCERR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRCRCEPR_RXCRCERR                       ETH_MMCRCRCEPR_RXCRCERR_msk /* Rx CRC Error Packets */
+
+/* Bit definition for Ethernet MMC Rx alignment error packets register */
+#define ETH_MMCRAEPR_RXALGNERR_Pos                    (0U)
+#define ETH_MMCRAEPR_RXALGNERR_msk                    (0xFFFFFFFFUL <<  ETH_MMCRAEPR_RXALGNERR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRAEPR_RXALGNERR                        ETH_MMCRAEPR_RXALGNERR_msk /* Rx Alignment Error Packets */
+
+/* Bit definition for Ethernet MMC Rx Unicast Packets Good Register */
+#define ETH_MMCRUPGR_RXUCASTG_Pos                     (0U)
+#define ETH_MMCRUPGR_RXUCASTG_msk                     (0xFFFFFFFFUL <<  ETH_MMCRUPGR_RXUCASTG_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRUPGR_RXUCASTG                         ETH_MMCRUPGR_RXUCASTG_msk /* Rx Unicast Packets Good */
+
+/* Bit definition for Ethernet MMC Tx LPI Microsecond Timer Register */
+#define ETH_MMCTLPIMSTR_TXLPIUSC_Pos                  (0U)
+#define ETH_MMCTLPIMSTR_TXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCTLPIMSTR_TXLPIUSC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTLPIMSTR_TXLPIUSC                      ETH_MMCTLPIMSTR_TXLPIUSC_msk /* Tx LPI Microseconds Counter */
+
+/* Bit definition for Ethernet MMC Tx LPI Transition Counter Register */
+#define ETH_MMCTLPITCR_TXLPITRC_Pos                   (0U)
+#define ETH_MMCTLPITCR_TXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCTLPITCR_TXLPITRC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTLPITCR_TXLPITRC                       ETH_MMCTLPITCR_TXLPITRC_msk /* Tx LPI Transition counter */
+
+/* Bit definition for Ethernet MMC Rx LPI Microsecond Counter Register */
+#define ETH_MMCRLPIMSTR_RXLPIUSC_Pos                  (0U)
+#define ETH_MMCRLPIMSTR_RXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCRLPIMSTR_RXLPIUSC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRLPIMSTR_RXLPIUSC                      ETH_MMCRLPIMSTR_RXLPIUSC_msk /* Rx LPI Microseconds Counter */
+
+/* Bit definition for Ethernet MMC Rx LPI Transition Counter Register */
+#define ETH_MMCRLPITCR_RXLPITRC_Pos                   (0U)
+#define ETH_MMCRLPITCR_RXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCRLPITCR_RXLPITRC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRLPITCR_RXLPITRC                       ETH_MMCRLPITCR_RXLPITRC_msk /* Rx LPI Transition counter */
+
+/* Bit definition for Ethernet MAC L3 L4 Control Register */
+#define ETH_MACL3L4CR_L4DPIM_Pos                      (21U)
+#define ETH_MACL3L4CR_L4DPIM_Msk                      (0x1UL << ETH_MACL3L4CR_L4DPIM_Pos) /*!< 0x00200000 */
+#define ETH_MACL3L4CR_L4DPIM                          ETH_MACL3L4CR_L4DPIM_Msk /* Layer 4 Destination Port Inverse Match Enable */
+#define ETH_MACL3L4CR_L4DPM_Pos                       (20U)
+#define ETH_MACL3L4CR_L4DPM_Msk                       (0x1UL << ETH_MACL3L4CR_L4DPM_Pos) /*!< 0x00100000 */
+#define ETH_MACL3L4CR_L4DPM                           ETH_MACL3L4CR_L4DPM_Msk  /* Layer 4 Destination Port Match Enable */
+#define ETH_MACL3L4CR_L4SPIM_Pos                      (19U)
+#define ETH_MACL3L4CR_L4SPIM_Msk                      (0x1UL << ETH_MACL3L4CR_L4SPIM_Pos) /*!< 0x00080000 */
+#define ETH_MACL3L4CR_L4SPIM                          ETH_MACL3L4CR_L4SPIM_Msk /* Layer 4 Source Port Inverse Match Enable */
+#define ETH_MACL3L4CR_L4SPM_Pos                       (18U)
+#define ETH_MACL3L4CR_L4SPM_Msk                       (0x1UL << ETH_MACL3L4CR_L4SPM_Pos) /*!< 0x00040000 */
+#define ETH_MACL3L4CR_L4SPM                           ETH_MACL3L4CR_L4SPM_Msk  /* Layer 4 Source Port Match Enable */
+#define ETH_MACL3L4CR_L4PEN_Pos                       (16U)
+#define ETH_MACL3L4CR_L4PEN_Msk                       (0x1UL << ETH_MACL3L4CR_L4PEN_Pos) /*!< 0x00010000 */
+#define ETH_MACL3L4CR_L4PEN                           ETH_MACL3L4CR_L4PEN_Msk  /* Layer 4 Protocol Enable */
+#define ETH_MACL3L4CR_L3HDBM_Pos                      (11U)
+#define ETH_MACL3L4CR_L3HDBM_Msk                      (0x1FUL << ETH_MACL3L4CR_L3HDBM_Pos) /*!< 0x0000F800 */
+#define ETH_MACL3L4CR_L3HDBM                          ETH_MACL3L4CR_L3HDBM_Msk /* Layer 3 IP DA Higher Bits Match */
+#define ETH_MACL3L4CR_L3HSBM_Pos                      (6U)
+#define ETH_MACL3L4CR_L3HSBM_Msk                      (0x1FUL << ETH_MACL3L4CR_L3HSBM_Pos) /*!< 0x000007C0 */
+#define ETH_MACL3L4CR_L3HSBM                          ETH_MACL3L4CR_L3HSBM_Msk /* Layer 3 IP SA Higher Bits Match */
+#define ETH_MACL3L4CR_L3DAIM_Pos                      (5U)
+#define ETH_MACL3L4CR_L3DAIM_Msk                      (0x1UL << ETH_MACL3L4CR_L3DAIM_Pos) /*!< 0x00000020 */
+#define ETH_MACL3L4CR_L3DAIM                          ETH_MACL3L4CR_L3DAIM_Msk /* Layer 3 IP DA Inverse Match Enable */
+#define ETH_MACL3L4CR_L3DAM_Pos                       (4U)
+#define ETH_MACL3L4CR_L3DAM_Msk                       (0x1UL << ETH_MACL3L4CR_L3DAM_Pos) /*!< 0x00000010 */
+#define ETH_MACL3L4CR_L3DAM                           ETH_MACL3L4CR_L3DAM_Msk  /* Layer 3 IP DA Match Enable */
+#define ETH_MACL3L4CR_L3SAIM_Pos                      (3U)
+#define ETH_MACL3L4CR_L3SAIM_Msk                      (0x1UL << ETH_MACL3L4CR_L3SAIM_Pos) /*!< 0x00000008 */
+#define ETH_MACL3L4CR_L3SAIM                          ETH_MACL3L4CR_L3SAIM_Msk /* Layer 3 IP SA Inverse Match Enable */
+#define ETH_MACL3L4CR_L3SAM_Pos                       (2U)
+#define ETH_MACL3L4CR_L3SAM_Msk                       (0x1UL << ETH_MACL3L4CR_L3SAM_Pos) /*!< 0x00000004 */
+#define ETH_MACL3L4CR_L3SAM                           ETH_MACL3L4CR_L3SAM_Msk  /* Layer 3 IP SA Match Enable*/
+#define ETH_MACL3L4CR_L3PEN_Pos                       (0U)
+#define ETH_MACL3L4CR_L3PEN_Msk                       (0x1UL << ETH_MACL3L4CR_L3PEN_Pos) /*!< 0x00000001 */
+#define ETH_MACL3L4CR_L3PEN                           ETH_MACL3L4CR_L3PEN_Msk  /* Layer 3 Protocol Enable */
+
+/* Bit definition for Ethernet MAC L4 Address Register */
+#define ETH_MACL4AR_L4DP_Pos                          (16U)
+#define ETH_MACL4AR_L4DP_Msk                          (0xFFFFUL << ETH_MACL4AR_L4DP_Pos) /*!< 0xFFFF0000 */
+#define ETH_MACL4AR_L4DP                              ETH_MACL4AR_L4DP_Msk     /* Layer 4 Destination Port Number Field */
+#define ETH_MACL4AR_L4SP_Pos                          (0U)
+#define ETH_MACL4AR_L4SP_Msk                          (0xFFFFUL << ETH_MACL4AR_L4SP_Pos) /*!< 0x0000FFFF */
+#define ETH_MACL4AR_L4SP                              ETH_MACL4AR_L4SP_Msk     /* Layer 4 Source Port Number Field */
+
+/* Bit definition for Ethernet MAC L3 Address0 Register */
+#define ETH_MACL3A0R_L3A0_Pos                         (0U)
+#define ETH_MACL3A0R_L3A0_Msk                         (0xFFFFFFFFUL << ETH_MACL3A0R_L3A0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A0R_L3A0                             ETH_MACL3A0R_L3A0_Msk    /* Layer 3 Address 0 Field */
+
+/* Bit definition for Ethernet MAC L4 Address1 Register */
+#define ETH_MACL3A1R_L3A1_Pos                         (0U)
+#define ETH_MACL3A1R_L3A1_Msk                         (0xFFFFFFFFUL << ETH_MACL3A1R_L3A1_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A1R_L3A1                             ETH_MACL3A1R_L3A1_Msk    /* Layer 3 Address 1 Field */
+
+/* Bit definition for Ethernet MAC L4 Address2 Register */
+#define ETH_MACL3A2R_L3A2_Pos                         (0U)
+#define ETH_MACL3A2R_L3A2_Msk                         (0xFFFFFFFFUL << ETH_MACL3A2R_L3A2_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A2R_L3A2                             ETH_MACL3A2R_L3A2_Msk    /* Layer 3 Address 2 Field */
+
+/* Bit definition for Ethernet MAC L4 Address3 Register */
+#define ETH_MACL3A3R_L3A3_Pos                         (0U)
+#define ETH_MACL3A3R_L3A3_Msk                         (0xFFFFFFFFUL << ETH_MACL3A3R_L3A3_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A3R_L3A3                             ETH_MACL3A3R_L3A3_Msk    /* Layer 3 Address 3 Field */
+
+/* Bit definition for Ethernet MAC Timestamp Control Register */
+#define ETH_MACTSCR_TXTSSTSM_Pos                      (24U)
+#define ETH_MACTSCR_TXTSSTSM_Msk                      (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */
+#define ETH_MACTSCR_TXTSSTSM                          ETH_MACTSCR_TXTSSTSM_Msk  /* Transmit Timestamp Status Mode */
+#define ETH_MACTSCR_CSC_Pos                           (19U)
+#define ETH_MACTSCR_CSC_Msk                           (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */
+#define ETH_MACTSCR_CSC                               ETH_MACTSCR_CSC_Msk  /* Enable checksum correction during OST for PTP over UDP/IPv4 packets */
+#define ETH_MACTSCR_TSENMACADDR_Pos                   (18U)
+#define ETH_MACTSCR_TSENMACADDR_Msk                   (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */
+#define ETH_MACTSCR_TSENMACADDR                       ETH_MACTSCR_TSENMACADDR_Msk  /* Enable MAC Address for PTP Packet Filtering */
+#define ETH_MACTSCR_SNAPTYPSEL_Pos                    (16U)
+#define ETH_MACTSCR_SNAPTYPSEL_Msk                    (0x3UL << ETH_MACTSCR_SNAPTYPSEL_Pos) /*!< 0x00030000 */
+#define ETH_MACTSCR_SNAPTYPSEL                        ETH_MACTSCR_SNAPTYPSEL_Msk  /* Select PTP packets for Taking Snapshots */
+#define ETH_MACTSCR_TSMSTRENA_Pos                     (15U)
+#define ETH_MACTSCR_TSMSTRENA_Msk                     (0x1UL << ETH_MACTSCR_TSMSTRENA_Pos) /*!< 0x00008000 */
+#define ETH_MACTSCR_TSMSTRENA                         ETH_MACTSCR_TSMSTRENA_Msk  /* Enable Snapshot for Messages Relevant to Master */
+#define ETH_MACTSCR_TSEVNTENA_Pos                     (14U)
+#define ETH_MACTSCR_TSEVNTENA_Msk                     (0x1UL << ETH_MACTSCR_TSEVNTENA_Pos) /*!< 0x00004000 */
+#define ETH_MACTSCR_TSEVNTENA                         ETH_MACTSCR_TSEVNTENA_Msk  /* Enable Timestamp Snapshot for Event Messages */
+#define ETH_MACTSCR_TSIPV4ENA_Pos                     (13U)
+#define ETH_MACTSCR_TSIPV4ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV4ENA_Pos) /*!< 0x00002000 */
+#define ETH_MACTSCR_TSIPV4ENA                         ETH_MACTSCR_TSIPV4ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv4-UDP */
+#define ETH_MACTSCR_TSIPV6ENA_Pos                     (12U)
+#define ETH_MACTSCR_TSIPV6ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV6ENA_Pos) /*!< 0x00001000 */
+#define ETH_MACTSCR_TSIPV6ENA                         ETH_MACTSCR_TSIPV6ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv6-UDP */
+#define ETH_MACTSCR_TSIPENA_Pos                       (11U)
+#define ETH_MACTSCR_TSIPENA_Msk                       (0x1UL << ETH_MACTSCR_TSIPENA_Pos) /*!< 0x00000800 */
+#define ETH_MACTSCR_TSIPENA                           ETH_MACTSCR_TSIPENA_Msk  /* Enable Processing of PTP over Ethernet Packets */
+#define ETH_MACTSCR_TSVER2ENA_Pos                     (10U)
+#define ETH_MACTSCR_TSVER2ENA_Msk                     (0x1UL << ETH_MACTSCR_TSVER2ENA_Pos) /*!< 0x00000400 */
+#define ETH_MACTSCR_TSVER2ENA                         ETH_MACTSCR_TSVER2ENA_Msk  /* Enable PTP Packet Processing for Version 2 Format */
+#define ETH_MACTSCR_TSCTRLSSR_Pos                     (9U)
+#define ETH_MACTSCR_TSCTRLSSR_Msk                     (0x1UL << ETH_MACTSCR_TSCTRLSSR_Pos) /*!< 0x00000200 */
+#define ETH_MACTSCR_TSCTRLSSR                         ETH_MACTSCR_TSCTRLSSR_Msk  /* Timestamp Digital or Binary Rollover Control */
+#define ETH_MACTSCR_TSENALL_Pos                       (8U)
+#define ETH_MACTSCR_TSENALL_Msk                       (0x1UL << ETH_MACTSCR_TSENALL_Pos) /*!< 0x00000100 */
+#define ETH_MACTSCR_TSENALL                           ETH_MACTSCR_TSENALL_Msk  /* Enable Timestamp for All Packets */
+#define ETH_MACTSCR_TSADDREG_Pos                      (5U)
+#define ETH_MACTSCR_TSADDREG_Msk                      (0x1UL << ETH_MACTSCR_TSADDREG_Pos) /*!< 0x00000020 */
+#define ETH_MACTSCR_TSADDREG                          ETH_MACTSCR_TSADDREG_Msk  /* Update Addend Register */
+#define ETH_MACTSCR_TSUPDT_Pos                        (3U)
+#define ETH_MACTSCR_TSUPDT_Msk                        (0x1UL << ETH_MACTSCR_TSUPDT_Pos) /*!< 0x00000008 */
+#define ETH_MACTSCR_TSUPDT                            ETH_MACTSCR_TSUPDT_Msk  /* Update Timestamp */
+#define ETH_MACTSCR_TSINIT_Pos                        (2U)
+#define ETH_MACTSCR_TSINIT_Msk                        (0x1UL << ETH_MACTSCR_TSINIT_Pos) /*!< 0x00000004 */
+#define ETH_MACTSCR_TSINIT                             ETH_MACTSCR_TSINIT_Msk  /* Initialize Timestamp */
+#define ETH_MACTSCR_TSCFUPDT_Pos                      (1U)
+#define ETH_MACTSCR_TSCFUPDT_Msk                      (0x1UL << ETH_MACTSCR_TSCFUPDT_Pos) /*!< 0x00000002 */
+#define ETH_MACTSCR_TSCFUPDT                          ETH_MACTSCR_TSCFUPDT_Msk  /* Fine or Coarse Timestamp Update*/
+#define ETH_MACTSCR_TSENA_Pos                         (0U)
+#define ETH_MACTSCR_TSENA_Msk                         (0x1UL << ETH_MACTSCR_TSENA_Pos) /*!< 0x00000001 */
+#define ETH_MACTSCR_TSENA                             ETH_MACTSCR_TSENA_Msk  /* Enable Timestamp */
+
+/* Bit definition for Ethernet MAC Sub-second Increment Register */
+#define ETH_MACMACSSIR_SSINC_Pos                      (16U)
+#define ETH_MACMACSSIR_SSINC_Msk                      (0xFFUL << ETH_MACMACSSIR_SSINC_Pos) /*!< 0x0000FF00 */
+#define ETH_MACMACSSIR_SSINC                          ETH_MACMACSSIR_SSINC_Msk  /* Sub-second Increment Value */
+#define ETH_MACMACSSIR_SNSINC_Pos                     (8U)
+#define ETH_MACMACSSIR_SNSINC_Msk                     (0xFFUL << ETH_MACMACSSIR_SNSINC_Pos) /*!< 0x000000FF */
+#define ETH_MACMACSSIR_SNSINC                         ETH_MACMACSSIR_SNSINC_Msk  /* Sub-nanosecond Increment Value */
+
+/* Bit definition for Ethernet MAC System Time Seconds Register */
+#define ETH_MACSTSR_TSS_Pos                           (0U)
+#define ETH_MACSTSR_TSS_Msk                           (0xFFFFFFFFUL << ETH_MACSTSR_TSS_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACSTSR_TSS                               ETH_MACSTSR_TSS_Msk  /* Timestamp Second */
+
+/* Bit definition for Ethernet MAC System Time Nanoseconds Register */
+#define ETH_MACSTNR_TSSS_Pos                          (0U)
+#define ETH_MACSTNR_TSSS_Msk                          (0x7FFFFFFFUL << ETH_MACSTNR_TSSS_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACSTNR_TSSS                              ETH_MACSTNR_TSSS_Msk  /* Timestamp Sub-seconds */
+
+/* Bit definition for Ethernet MAC System Time Seconds Update Register */
+#define ETH_MACSTSUR_TSS_Pos                          (0U)
+#define ETH_MACSTSUR_TSS_Msk                          (0xFFFFFFFFUL << ETH_MACSTSUR_TSS_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACSTSUR_TSS                              ETH_MACSTSUR_TSS_Msk  /* Timestamp Seconds */
+
+/* Bit definition for Ethernet MAC System Time Nanoseconds Update Register */
+#define ETH_MACSTNUR_ADDSUB_Pos                       (31U)
+#define ETH_MACSTNUR_ADDSUB_Msk                       (0x1UL << ETH_MACSTNUR_ADDSUB_Pos) /*!< 0x80000000 */
+#define ETH_MACSTNUR_ADDSUB                           ETH_MACSTNUR_ADDSUB_Msk  /* Add or Subtract Time */
+#define ETH_MACSTNUR_TSSS_Pos                         (0U)
+#define ETH_MACSTNUR_TSSS_Msk                         (0x7FFFFFFFUL << ETH_MACSTNUR_TSSS_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACSTNUR_TSSS                             ETH_MACSTNUR_TSSS_Msk  /* Timestamp Sub-seconds */
+
+/* Bit definition for Ethernet MAC Timestamp Addend Register */
+#define ETH_MACTSAR_TSAR_Pos                          (0U)
+#define ETH_MACTSAR_TSAR_Msk                          (0xFFFFFFFFUL << ETH_MACTSAR_TSAR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSAR_TSAR                              ETH_MACTSAR_TSAR_Msk  /* Timestamp Addend Register */
+
+/* Bit definition for Ethernet MAC Timestamp Status Register */
+#define ETH_MACTSSR_ATSNS_Pos                         (25U)
+#define ETH_MACTSSR_ATSNS_Msk                         (0x1FUL << ETH_MACTSSR_ATSNS_Pos) /*!< 0x3E000000 */
+#define ETH_MACTSSR_ATSNS                             ETH_MACTSSR_ATSNS_Msk  /* Number of Auxiliary Timestamp Snapshots */
+#define ETH_MACTSSR_ATSSTM_Pos                        (24U)
+#define ETH_MACTSSR_ATSSTM_Msk                        (0x1UL << ETH_MACTSSR_ATSSTM_Pos) /*!< 0x01000000 */
+#define ETH_MACTSSR_ATSSTM                            ETH_MACTSSR_ATSSTM_Msk  /* Auxiliary Timestamp Snapshot Trigger Missed */
+#define ETH_MACTSSR_ATSSTN_Pos                        (16U)
+#define ETH_MACTSSR_ATSSTN_Msk                        (0xFUL << ETH_MACTSSR_ATSSTN_Pos) /*!< 0x000F0000 */
+#define ETH_MACTSSR_ATSSTN                            ETH_MACTSSR_ATSSTN_Msk  /* Auxiliary Timestamp Snapshot Trigger Identifier */
+#define ETH_MACTSSR_TXTSSIS_Pos                       (15U)
+#define ETH_MACTSSR_TXTSSIS_Msk                       (0x1UL << ETH_MACTSSR_TXTSSIS_Pos) /*!< 0x00008000 */
+#define ETH_MACTSSR_TXTSSIS                           ETH_MACTSSR_TXTSSIS_Msk  /* Tx Timestamp Status Interrupt Status */
+#define ETH_MACTSSR_TSTRGTERR0_Pos                    (3U)
+#define ETH_MACTSSR_TSTRGTERR0_Msk                    (0x1UL << ETH_MACTSSR_TSTRGTERR0_Pos) /*!< 0x00000008 */
+#define ETH_MACTSSR_TSTRGTERR0                        ETH_MACTSSR_TSTRGTERR0_Msk  /* Timestamp Target Time Error */
+#define ETH_MACTSSR_AUXTSTRIG_Pos                     (2U)
+#define ETH_MACTSSR_AUXTSTRIG_Msk                     (0x1UL << ETH_MACTSSR_AUXTSTRIG_Pos) /*!< 0x00000004 */
+#define ETH_MACTSSR_AUXTSTRIG                         ETH_MACTSSR_AUXTSTRIG_Msk  /* Auxiliary Timestamp Trigger Snapshot*/
+#define ETH_MACTSSR_TSTARGT0_Pos                      (1U)
+#define ETH_MACTSSR_TSTARGT0_Msk                      (0x1UL << ETH_MACTSSR_TSTARGT0_Pos) /*!< 0x00000002 */
+#define ETH_MACTSSR_TSTARGT0                          ETH_MACTSSR_TSTARGT0_Msk  /* Timestamp Target Time Reached */
+#define ETH_MACTSSR_TSSOVF_Pos                        (0U)
+#define ETH_MACTSSR_TSSOVF_Msk                        (0x1UL << ETH_MACTSSR_TSSOVF_Pos) /*!< 0x00000001 */
+#define ETH_MACTSSR_TSSOVF                            ETH_MACTSSR_TSSOVF_Msk  /* Timestamp Seconds Overflow */
+
+/* Bit definition for Ethernet MAC Tx Timestamp Status Nanoseconds Register */
+#define ETH_MACTTSSNR_TXTSSMIS_Pos                    (31U)
+#define ETH_MACTTSSNR_TXTSSMIS_Msk                    (0x1UL << ETH_MACTTSSNR_TXTSSMIS_Pos) /*!< 0x80000000 */
+#define ETH_MACTTSSNR_TXTSSMIS                        ETH_MACTTSSNR_TXTSSMIS_Msk  /* Transmit Timestamp Status Missed */
+#define ETH_MACTTSSNR_TXTSSLO_Pos                     (0U)
+#define ETH_MACTTSSNR_TXTSSLO_Msk                     (0x7FFFFFFFUL << ETH_MACTTSSNR_TXTSSLO_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACTTSSNR_TXTSSLO                         ETH_MACTTSSNR_TXTSSLO_Msk  /* Transmit Timestamp Status Low */
+
+/* Bit definition for Ethernet MAC Tx Timestamp Status Seconds Register */
+#define ETH_MACTTSSSR_TXTSSHI_Pos                     (0U)
+#define ETH_MACTTSSSR_TXTSSHI_Msk                     (0xFFFFFFFFUL << ETH_MACTTSSSR_TXTSSHI_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTTSSSR_TXTSSHI                         ETH_MACTTSSSR_TXTSSHI_Msk  /* Transmit Timestamp Status High */
+
+/* Bit definition for Ethernet MAC Auxiliary Control Register*/
+#define ETH_MACACR_ATSEN3_Pos                         (7U)
+#define ETH_MACACR_ATSEN3_Msk                         (0x1UL << ETH_MACACR_ATSEN3_Pos) /*!< 0x00000080 */
+#define ETH_MACACR_ATSEN3                             ETH_MACACR_ATSEN3_Msk  /* Auxiliary Snapshot 3 Enable */
+#define ETH_MACACR_ATSEN2_Pos                         (6U)
+#define ETH_MACACR_ATSEN2_Msk                         (0x1UL << ETH_MACACR_ATSEN2_Pos) /*!< 0x00000040 */
+#define ETH_MACACR_ATSEN2                             ETH_MACACR_ATSEN2_Msk  /* Auxiliary Snapshot 2 Enable */
+#define ETH_MACACR_ATSEN1_Pos                         (5U)
+#define ETH_MACACR_ATSEN1_Msk                         (0x1UL << ETH_MACACR_ATSEN1_Pos) /*!< 0x00000020 */
+#define ETH_MACACR_ATSEN1                             ETH_MACACR_ATSEN1_Msk  /* Auxiliary Snapshot 1 Enable */
+#define ETH_MACACR_ATSEN0_Pos                         (4U)
+#define ETH_MACACR_ATSEN0_Msk                         (0x1UL << ETH_MACACR_ATSEN0_Pos) /*!< 0x00000010 */
+#define ETH_MACACR_ATSEN0                             ETH_MACACR_ATSEN0_Msk  /* Auxiliary Snapshot 0 Enable */
+#define ETH_MACACR_ATSFC_Pos                          (0U)
+#define ETH_MACACR_ATSFC_Msk                          (0x1UL << ETH_MACACR_ATSFC_Pos) /*!< 0x00000001 */
+#define ETH_MACACR_ATSFC                              ETH_MACACR_ATSFC_Msk  /* Auxiliary Snapshot FIFO Clear */
+
+/* Bit definition for Ethernet MAC Auxiliary Timestamp Nanoseconds Register */
+#define ETH_MACATSNR_AUXTSLO_Pos                      (0U)
+#define ETH_MACATSNR_AUXTSLO_Msk                      (0x7FFFFFFFUL << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACATSNR_AUXTSLO                          ETH_MACATSNR_AUXTSLO_Msk  /* Auxiliary Timestamp */
+
+/* Bit definition for Ethernet MAC Auxiliary Timestamp Seconds Register */
+#define ETH_MACATSSR_AUXTSHI_Pos                      (0U)
+#define ETH_MACATSSR_AUXTSHI_Msk                      (0xFFFFFFFFUL << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACATSSR_AUXTSHI                          ETH_MACATSSR_AUXTSHI_Msk  /* Auxiliary Timestamp */
+
+/* Bit definition for Ethernet MAC Timestamp Ingress Asymmetric Correction Register */
+#define ETH_MACTSIACR_OSTIAC_Pos                      (0U)
+#define ETH_MACTSIACR_OSTIAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSIACR_OSTIAC                          ETH_MACTSIACR_OSTIAC_Msk  /* One-Step Timestamp Ingress Asymmetry Correction */
+
+/* Bit definition for Ethernet MAC Timestamp Egress Asymmetric Correction Register */
+#define ETH_MACTSEACR_OSTEAC_Pos                      (0U)
+#define ETH_MACTSEACR_OSTEAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSEACR_OSTEAC                          ETH_MACTSEACR_OSTEAC_Msk  /* One-Step Timestamp Egress Asymmetry Correction */
+
+/* Bit definition for Ethernet MAC Timestamp Ingress Correction Nanosecond Register */
+#define ETH_MACTSICNR_TSIC_Pos                        (0U)
+#define ETH_MACTSICNR_TSIC_Msk                        (0xFFFFFFFFUL << ETH_MACTSICNR_TSIC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSICNR_TSIC                            ETH_MACTSICNR_TSIC_Msk  /* Timestamp Ingress Correction */
+
+/* Bit definition for Ethernet MAC Timestamp Egress correction Nanosecond Register */
+#define ETH_MACTSECNR_TSEC_Pos                        (0U)
+#define ETH_MACTSECNR_TSEC_Msk                        (0xFFFFFFFFUL << ETH_MACTSECNR_TSEC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSECNR_TSEC                            ETH_MACTSECNR_TSEC_Msk  /* Timestamp Egress Correction */
+
+/* Bit definition for Ethernet MAC PPS Control Register */
+#define ETH_MACPPSCR_TRGTMODSEL0_Pos                  (5U)
+#define ETH_MACPPSCR_TRGTMODSEL0_Msk                  (0x3UL << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000060 */
+#define ETH_MACPPSCR_TRGTMODSEL0                      ETH_MACPPSCR_TRGTMODSEL0_Msk  /* Target Time Register Mode for PPS Output */
+#define ETH_MACPPSCR_PPSEN0_Pos                       (4U)
+#define ETH_MACPPSCR_PPSEN0_Msk                       (0x1UL << ETH_MACPPSCR_PPSEN0_Pos) /*!< 0x00000010 */
+#define ETH_MACPPSCR_PPSEN0                           ETH_MACPPSCR_PPSEN0_Msk  /* Flexible PPS Output Mode Enable */
+#define ETH_MACPPSCR_PPSCTRL_Pos                      (0U)
+#define ETH_MACPPSCR_PPSCTRL_Msk                      (0xFUL << ETH_MACPPSCR_PPSCTRL_Pos) /*!< 0x0000000F */
+#define ETH_MACPPSCR_PPSCTRL                          ETH_MACPPSCR_PPSCTRL_Msk  /* PPS Output Frequency Control */
+
+/* Bit definition for Ethernet MAC PPS Target Time Seconds Register */
+#define ETH_MACPPSTTSR_TSTRH0_Pos                     (0U)
+#define ETH_MACPPSTTSR_TSTRH0_Msk                     (0xFFFFFFFFUL << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACPPSTTSR_TSTRH0                         ETH_MACPPSTTSR_TSTRH0_Msk  /* PPS Target Time Seconds Register */
+
+/* Bit definition for Ethernet MAC PPS Target Time Nanoseconds Register */
+#define ETH_MACPPSTTNR_TRGTBUSY0_Pos                  (31U)
+#define ETH_MACPPSTTNR_TRGTBUSY0_Msk                  (0x1UL << ETH_MACPPSTTNR_TRGTBUSY0_Pos) /*!< 0x80000000 */
+#define ETH_MACPPSTTNR_TRGTBUSY0                      ETH_MACPPSTTNR_TRGTBUSY0_Msk  /* PPS Target Time Register Busy */
+#define ETH_MACPPSTTNR_TTSL0_Pos                      (0U)
+#define ETH_MACPPSTTNR_TTSL0_Msk                      (0x7FFFFFFFUL << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACPPSTTNR_TTSL0                          ETH_MACPPSTTNR_TTSL0_Msk  /* Target Time Low for PPS Register */
+
+/* Bit definition for Ethernet MAC PPS Interval Register */
+#define ETH_MACPPSIR_PPSINT0_Pos                      (0U)
+#define ETH_MACPPSIR_PPSINT0_Msk                      (0xFFFFFFFFUL << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACPPSIR_PPSINT0                          ETH_MACPPSIR_PPSINT0_Msk  /* PPS Output Signal Interval */
+
+/* Bit definition for Ethernet MAC PPS Width Register */
+#define ETH_MACPPSWR_PPSWIDTH0_Pos                    (0U)
+#define ETH_MACPPSWR_PPSWIDTH0_Msk                    (0xFFFFFFFFUL << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACPPSWR_PPSWIDTH0                        ETH_MACPPSWR_PPSWIDTH0_Msk  /* PPS Output Signal Width */
+
+/* Bit definition for Ethernet MAC PTP Offload Control Register */
+#define ETH_MACPOCR_DN_Pos                            (8U)
+#define ETH_MACPOCR_DN_Msk                            (0xFFUL << ETH_MACPOCR_DN_Pos) /*!< 0x0000FF00 */
+#define ETH_MACPOCR_DN                                ETH_MACPOCR_DN_Msk  /* Domain Number */
+#define ETH_MACPOCR_DRRDIS_Pos                        (6U)
+#define ETH_MACPOCR_DRRDIS_Msk                        (0x1UL << ETH_MACPOCR_DRRDIS_Pos) /*!< 0x00000040 */
+#define ETH_MACPOCR_DRRDIS                            ETH_MACPOCR_DRRDIS_Msk  /* Disable PTO Delay Request/Response response generation */
+#define ETH_MACPOCR_APDREQTRIG_Pos                    (5U)
+#define ETH_MACPOCR_APDREQTRIG_Msk                    (0x1UL << ETH_MACPOCR_APDREQTRIG_Pos) /*!< 0x00000020 */
+#define ETH_MACPOCR_APDREQTRIG                        ETH_MACPOCR_APDREQTRIG_Msk  /* Automatic PTP Pdelay_Req message Trigger */
+#define ETH_MACPOCR_ASYNCTRIG_Pos                     (4U)
+#define ETH_MACPOCR_ASYNCTRIG_Msk                     (0x1UL << ETH_MACPOCR_ASYNCTRIG_Pos) /*!< 0x00000010 */
+#define ETH_MACPOCR_ASYNCTRIG                         ETH_MACPOCR_ASYNCTRIG_Msk  /* Automatic PTP SYNC message Trigger */
+#define ETH_MACPOCR_APDREQEN_Pos                      (2U)
+#define ETH_MACPOCR_APDREQEN_Msk                      (0x1UL << ETH_MACPOCR_APDREQEN_Pos) /*!< 0x00000004 */
+#define ETH_MACPOCR_APDREQEN                          ETH_MACPOCR_APDREQEN_Msk  /* Automatic PTP Pdelay_Req message Enable */
+#define ETH_MACPOCR_ASYNCEN_Pos                       (1U)
+#define ETH_MACPOCR_ASYNCEN_Msk                       (0x1UL << ETH_MACPOCR_ASYNCEN_Pos) /*!< 0x00000002 */
+#define ETH_MACPOCR_ASYNCEN                           ETH_MACPOCR_ASYNCEN_Msk  /* Automatic PTP SYNC message Enable */
+#define ETH_MACPOCR_PTOEN_Pos                         (0U)
+#define ETH_MACPOCR_PTOEN_Msk                         (0x1UL << ETH_MACPOCR_PTOEN_Pos) /*!< 0x00000001 */
+#define ETH_MACPOCR_PTOEN                             ETH_MACPOCR_PTOEN_Msk  /* PTP Offload Enable */
+
+/* Bit definition for Ethernet MAC PTP Source Port Identity 0 Register */
+#define ETH_MACSPI0R_SPI0_Pos                         (0U)
+#define ETH_MACSPI0R_SPI0_Msk                         (0xFFFFFFFFUL << ETH_MACSPI0R_SPI0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACSPI0R_SPI0                             ETH_MACSPI0R_SPI0_Msk  /* Source Port Identity 0 */
+
+/* Bit definition for Ethernet MAC PTP Source Port Identity 1 Register */
+#define ETH_MACSPI1R_SPI1_Pos                         (0U)
+#define ETH_MACSPI1R_SPI1_Msk                         (0xFFFFFFFFUL << ETH_MACSPI1R_SPI1_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACSPI1R_SPI1                             ETH_MACSPI1R_SPI1_Msk  /* Source Port Identity 1 */
+
+/* Bit definition for Ethernet MAC PTP Source Port Identity 2 Register */
+#define ETH_MACSPI2R_SPI2_Pos                         (0U)
+#define ETH_MACSPI2R_SPI2_Msk                         (0xFFFFUL << ETH_MACSPI2R_SPI2_Pos) /*!< 0x0000FFFF */
+#define ETH_MACSPI2R_SPI2                             ETH_MACSPI2R_SPI2_Msk  /* Source Port Identity 2 */
+
+/* Bit definition for Ethernet MAC Log Message Interval Register */
+#define ETH_MACLMIR_LMPDRI_Pos                        (24U)
+#define ETH_MACLMIR_LMPDRI_Msk                        (0xFFUL << ETH_MACLMIR_LMPDRI_Pos) /*!< 0xFF000000 */
+#define ETH_MACLMIR_LMPDRI                             ETH_MACLMIR_LMPDRI_Msk  /* Log Min Pdelay_Req Interval */
+#define ETH_MACLMIR_DRSYNCR_Pos                       (8U)
+#define ETH_MACLMIR_DRSYNCR_Msk                       (0x7UL << ETH_MACLMIR_DRSYNCR_Pos) /*!< 0x00000700 */
+#define ETH_MACLMIR_DRSYNCR                           ETH_MACLMIR_DRSYNCR_Msk  /* Delay_Req to SYNC Ratio */
+#define ETH_MACLMIR_LSI_Pos                           (0U)
+#define ETH_MACLMIR_LSI_Msk                           (0xFFUL << ETH_MACLMIR_LSI_Pos) /*!< 0x000000FF */
+#define ETH_MACLMIR_LSI                               ETH_MACLMIR_LSI_Msk  /* Log Sync Interval */
+
+/* Bit definition for Ethernet MTL Operation Mode Register */
+#define ETH_MTLOMR_CNTCLR_Pos                         (9U)
+#define ETH_MTLOMR_CNTCLR_Msk                         (0x1UL << ETH_MTLOMR_CNTCLR_Pos) /*!< 0x00000200 */
+#define ETH_MTLOMR_CNTCLR                             ETH_MTLOMR_CNTCLR_Msk    /* Counters Reset */
+#define ETH_MTLOMR_CNTPRST_Pos                        (8U)
+#define ETH_MTLOMR_CNTPRST_Msk                        (0x1UL << ETH_MTLOMR_CNTPRST_Pos) /*!< 0x00000100 */
+#define ETH_MTLOMR_CNTPRST                            ETH_MTLOMR_CNTPRST_Msk   /* Counters Preset */
+#define ETH_MTLOMR_DTXSTS_Pos                         (1U)
+#define ETH_MTLOMR_DTXSTS_Msk                         (0x1UL << ETH_MTLOMR_DTXSTS_Pos) /*!< 0x00000002 */
+#define ETH_MTLOMR_DTXSTS                             ETH_MTLOMR_DTXSTS_Msk  /* Drop Transmit Status */
+
+/* Bit definition for Ethernet MTL Interrupt Status Register */
+#define ETH_MTLISR_MACIS_Pos                          (16U)
+#define ETH_MTLISR_MACIS_Msk                          (0x1UL << ETH_MTLISR_MACIS_Pos) /*!< 0x00010000 */
+#define ETH_MTLISR_MACIS                              ETH_MTLISR_MACIS_Msk     /* MAC Interrupt Status */
+#define ETH_MTLISR_QIS_Pos                            (0U)
+#define ETH_MTLISR_QIS_Msk                            (0x1UL << ETH_MTLISR_QIS_Pos) /*!< 0x00000001 */
+#define ETH_MTLISR_QIS                                ETH_MTLISR_QIS_Msk       /* Queue Interrupt status */
+
+/* Bit definition for Ethernet MTL Tx Queue Operation Mode Register */
+#define ETH_MTLTQOMR_TTC_Pos                          (4U)
+#define ETH_MTLTQOMR_TTC_Msk                          (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */
+#define ETH_MTLTQOMR_TTC                              ETH_MTLTQOMR_TTC_Msk     /* Transmit Threshold Control */
+#define ETH_MTLTQOMR_TTC_32BITS                       ((uint32_t)0x00000000)   /* 32 bits Threshold */
+#define ETH_MTLTQOMR_TTC_64BITS                       ((uint32_t)0x00000010)   /* 64  bits Threshold */
+#define ETH_MTLTQOMR_TTC_96BITS                       ((uint32_t)0x00000020)   /* 96 bits Threshold */
+#define ETH_MTLTQOMR_TTC_128BITS                      ((uint32_t)0x00000030)   /* 128 bits Threshold */
+#define ETH_MTLTQOMR_TTC_192BITS                      ((uint32_t)0x00000040)   /* 192 bits Threshold */
+#define ETH_MTLTQOMR_TTC_256BITS                      ((uint32_t)0x00000050)   /* 256 bits Threshold */
+#define ETH_MTLTQOMR_TTC_384BITS                      ((uint32_t)0x00000060)   /* 384 bits Threshold */
+#define ETH_MTLTQOMR_TTC_512BITS                      ((uint32_t)0x00000070)   /* 512 bits Threshold */
+#define ETH_MTLTQOMR_TSF_Pos                          (1U)
+#define ETH_MTLTQOMR_TSF_Msk                          (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */
+#define ETH_MTLTQOMR_TSF                              ETH_MTLTQOMR_TSF_Msk     /* Transmit Store and Forward */
+#define ETH_MTLTQOMR_FTQ_Pos                          (0U)
+#define ETH_MTLTQOMR_FTQ_Msk                          (0x1UL << ETH_MTLTQOMR_FTQ_Pos) /*!< 0x00000001 */
+#define ETH_MTLTQOMR_FTQ                              ETH_MTLTQOMR_FTQ_Msk     /* Flush Transmit Queue */
+
+/* Bit definition for Ethernet MTL Tx Queue Underflow Register */
+#define ETH_MTLTQUR_UFCNTOVF_Pos                      (11U)
+#define ETH_MTLTQUR_UFCNTOVF_Msk                      (0x1UL << ETH_MTLTQUR_UFCNTOVF_Pos) /*!< 0x00000800 */
+#define ETH_MTLTQUR_UFCNTOVF                          ETH_MTLTQUR_UFCNTOVF_Msk /* Overflow Bit for Underflow Packet Counter */
+#define ETH_MTLTQUR_UFPKTCNT_Pos                      (0U)
+#define ETH_MTLTQUR_UFPKTCNT_Msk                      (0x7FFUL << ETH_MTLTQUR_UFPKTCNT_Pos) /*!< 0x000007FF */
+#define ETH_MTLTQUR_UFPKTCNT                          ETH_MTLTQUR_UFPKTCNT_Msk /* Underflow Packet Counter */
+
+/* Bit definition for Ethernet MTL Tx Queue Debug Register */
+#define ETH_MTLTQDR_STXSTSF_Pos                       (20U)
+#define ETH_MTLTQDR_STXSTSF_Msk                       (0x7UL << ETH_MTLTQDR_STXSTSF_Pos) /*!< 0x00700000 */
+#define ETH_MTLTQDR_STXSTSF                           ETH_MTLTQDR_STXSTSF_Msk  /* Number of Status Words in the Tx Status FIFO of Queue */
+#define ETH_MTLTQDR_PTXQ_Pos                          (16U)
+#define ETH_MTLTQDR_PTXQ_Msk                          (0x7UL << ETH_MTLTQDR_PTXQ_Pos) /*!< 0x00070000 */
+#define ETH_MTLTQDR_PTXQ                              ETH_MTLTQDR_PTXQ_Msk     /* Number of Packets in the Transmit Queue */
+#define ETH_MTLTQDR_TXSTSFSTS_Pos                     (5U)
+#define ETH_MTLTQDR_TXSTSFSTS_Msk                     (0x1UL << ETH_MTLTQDR_TXSTSFSTS_Pos) /*!< 0x00000020 */
+#define ETH_MTLTQDR_TXSTSFSTS                         ETH_MTLTQDR_TXSTSFSTS_Msk /* MTL Tx Status FIFO Full Status */
+#define ETH_MTLTQDR_TXQSTS_Pos                        (4U)
+#define ETH_MTLTQDR_TXQSTS_Msk                        (0x1UL << ETH_MTLTQDR_TXQSTS_Pos) /*!< 0x00000010 */
+#define ETH_MTLTQDR_TXQSTS                            ETH_MTLTQDR_TXQSTS_Msk   /* MTL Tx Queue Not Empty Status */
+#define ETH_MTLTQDR_TWCSTS_Pos                        (3U)
+#define ETH_MTLTQDR_TWCSTS_Msk                        (0x1UL << ETH_MTLTQDR_TWCSTS_Pos) /*!< 0x00000008 */
+#define ETH_MTLTQDR_TWCSTS                            ETH_MTLTQDR_TWCSTS_Msk   /* MTL Tx Queue Write Controller Status */
+#define ETH_MTLTQDR_TRCSTS_Pos                        (1U)
+#define ETH_MTLTQDR_TRCSTS_Msk                        (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */
+#define ETH_MTLTQDR_TRCSTS                            ETH_MTLTQDR_TRCSTS_Msk  /* MTL Tx Queue Read Controller Status */
+#define ETH_MTLTQDR_TRCSTS_IDLE                       ((uint32_t)0x00000000)  /* Idle state */
+#define ETH_MTLTQDR_TRCSTS_READ                       ((uint32_t)0x00000002)  /* Read state (transferring data to the MAC transmitter) */
+#define ETH_MTLTQDR_TRCSTS_WAITING                    ((uint32_t)0x00000004)  /* Waiting for pending Tx Status from the MAC transmitter */
+#define ETH_MTLTQDR_TRCSTS_FLUSHING                   ((uint32_t)0x00000006)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */
+#define ETH_MTLTQDR_TXQPAUSED_Pos                     (0U)
+#define ETH_MTLTQDR_TXQPAUSED_Msk                     (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */
+#define ETH_MTLTQDR_TXQPAUSED                         ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
+
+/* Bit definition for Ethernet MTL Queue Interrupt Control Status Register */
+#define ETH_MTLQICSR_RXOIE_Pos                        (24U)
+#define ETH_MTLQICSR_RXOIE_Msk                        (0x1UL << ETH_MTLQICSR_RXOIE_Pos) /*!< 0x01000000 */
+#define ETH_MTLQICSR_RXOIE                            ETH_MTLQICSR_RXOIE_Msk   /* Receive Queue Overflow Interrupt Enable */
+#define ETH_MTLQICSR_RXOVFIS_Pos                      (16U)
+#define ETH_MTLQICSR_RXOVFIS_Msk                      (0x1UL << ETH_MTLQICSR_RXOVFIS_Pos) /*!< 0x00010000 */
+#define ETH_MTLQICSR_RXOVFIS                          ETH_MTLQICSR_RXOVFIS_Msk /* Receive Queue Overflow Interrupt Status */
+#define ETH_MTLQICSR_TXUIE_Pos                        (8U)
+#define ETH_MTLQICSR_TXUIE_Msk                        (0x1UL << ETH_MTLQICSR_TXUIE_Pos) /*!< 0x00000100 */
+#define ETH_MTLQICSR_TXUIE                            ETH_MTLQICSR_TXUIE_Msk   /* Transmit Queue Underflow Interrupt Enable */
+#define ETH_MTLQICSR_TXUNFIS_Pos                      (0U)
+#define ETH_MTLQICSR_TXUNFIS_Msk                      (0x1UL << ETH_MTLQICSR_TXUNFIS_Pos) /*!< 0x00000001 */
+#define ETH_MTLQICSR_TXUNFIS                          ETH_MTLQICSR_TXUNFIS_Msk /* Transmit Queue Underflow Interrupt Status */
+
+/* Bit definition for Ethernet MTL Rx Queue Operation Mode Register */
+#define ETH_MTLRQOMR_RQS_Pos                          (20U)
+#define ETH_MTLRQOMR_RQS_Msk                          (0x7UL << ETH_MTLRQOMR_RQS_Pos) /*!< 0x00700000 */
+#define ETH_MTLRQOMR_RQS                              ETH_MTLRQOMR_RQS_Msk /* Receive Queue Size */
+#define ETH_MTLRQOMR_RFD_Pos                          (14U)
+#define ETH_MTLRQOMR_RFD_Msk                          (0x7UL << ETH_MTLRQOMR_RFD_Pos) /*!< 0x0001C000 */
+#define ETH_MTLRQOMR_RFD                              ETH_MTLRQOMR_RFD_Msk /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */
+#define ETH_MTLRQOMR_RFA_Pos                          (8U)
+#define ETH_MTLRQOMR_RFA_Msk                          (0x7UL << ETH_MTLRQOMR_RFA_Pos) /*!< 0x00000700 */
+#define ETH_MTLRQOMR_RFA                              ETH_MTLRQOMR_RFA_Msk /* Threshold for Activating Flow Control (in half-duplex and full-duplex */
+#define ETH_MTLRQOMR_EHFC_Pos                         (7U)
+#define ETH_MTLRQOMR_EHFC_Msk                         (0x1UL << ETH_MTLRQOMR_EHFC_Pos) /*!< 0x00000080 */
+#define ETH_MTLRQOMR_EHFC                             ETH_MTLRQOMR_EHFC_Msk /* DEnable Hardware Flow Control */
+#define ETH_MTLRQOMR_DISTCPEF_Pos                     (6U)
+#define ETH_MTLRQOMR_DISTCPEF_Msk                     (0x1UL << ETH_MTLRQOMR_DISTCPEF_Pos) /*!< 0x00000040 */
+#define ETH_MTLRQOMR_DISTCPEF                         ETH_MTLRQOMR_DISTCPEF_Msk /* Disable Dropping of TCP/IP Checksum Error Packets */
+#define ETH_MTLRQOMR_RSF_Pos                          (5U)
+#define ETH_MTLRQOMR_RSF_Msk                          (0x1UL << ETH_MTLRQOMR_RSF_Pos) /*!< 0x00000020 */
+#define ETH_MTLRQOMR_RSF                              ETH_MTLRQOMR_RSF_Msk     /* Receive Queue Store and Forward */
+#define ETH_MTLRQOMR_FEP_Pos                          (4U)
+#define ETH_MTLRQOMR_FEP_Msk                          (0x1UL << ETH_MTLRQOMR_FEP_Pos) /*!< 0x00000010 */
+#define ETH_MTLRQOMR_FEP                              ETH_MTLRQOMR_FEP_Msk     /* Forward Error Packets */
+#define ETH_MTLRQOMR_FUP_Pos                          (3U)
+#define ETH_MTLRQOMR_FUP_Msk                          (0x1UL << ETH_MTLRQOMR_FUP_Pos) /*!< 0x00000008 */
+#define ETH_MTLRQOMR_FUP                              ETH_MTLRQOMR_FUP_Msk     /* Forward Undersized Good Packets */
+#define ETH_MTLRQOMR_RTC_Pos                          (0U)
+#define ETH_MTLRQOMR_RTC_Msk                          (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */
+#define ETH_MTLRQOMR_RTC                              ETH_MTLRQOMR_RTC_Msk     /* Receive Queue Threshold Control */
+#define ETH_MTLRQOMR_RTC_64BITS                       ((uint32_t)0x00000000)   /* 64 bits Threshold */
+#define ETH_MTLRQOMR_RTC_32BITS                       ((uint32_t)0x00000001)   /* 32 bits Threshold */
+#define ETH_MTLRQOMR_RTC_96BITS                       ((uint32_t)0x00000002)   /* 96 bits Threshold */
+#define ETH_MTLRQOMR_RTC_128BITS                      ((uint32_t)0x00000003)   /* 128 bits Threshold */
+
+/* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
+#define ETH_MTLRQMPOCR_MISCNTOVF_Pos                  (27U)
+#define ETH_MTLRQMPOCR_MISCNTOVF_Msk                  (0x1UL << ETH_MTLRQMPOCR_MISCNTOVF_Pos) /*!< 0x08000000 */
+#define ETH_MTLRQMPOCR_MISCNTOVF                      ETH_MTLRQMPOCR_MISCNTOVF_Msk /* Missed Packet Counter Overflow Bit */
+#define ETH_MTLRQMPOCR_MISPKTCNT_Pos                  (16U)
+#define ETH_MTLRQMPOCR_MISPKTCNT_Msk                  (0x7FFUL << ETH_MTLRQMPOCR_MISPKTCNT_Pos) /*!< 0x07FF0000 */
+#define ETH_MTLRQMPOCR_MISPKTCNT                      ETH_MTLRQMPOCR_MISPKTCNT_Msk /* Missed Packet Counter */
+#define ETH_MTLRQMPOCR_OVFCNTOVF_Pos                  (11U)
+#define ETH_MTLRQMPOCR_OVFCNTOVF_Msk                  (0x1UL << ETH_MTLRQMPOCR_OVFCNTOVF_Pos) /*!< 0x00000800 */
+#define ETH_MTLRQMPOCR_OVFCNTOVF                      ETH_MTLRQMPOCR_OVFCNTOVF_Msk /* Overflow Counter Overflow Bit */
+#define ETH_MTLRQMPOCR_OVFPKTCNT_Pos                  (0U)
+#define ETH_MTLRQMPOCR_OVFPKTCNT_Msk                  (0x7FFUL << ETH_MTLRQMPOCR_OVFPKTCNT_Pos) /*!< 0x000007FF */
+#define ETH_MTLRQMPOCR_OVFPKTCNT                      ETH_MTLRQMPOCR_OVFPKTCNT_Msk /* Overflow Packet Counter */
+
+/* Bit definition for Ethernet MTL Rx Queue Debug Register */
+#define ETH_MTLRQDR_PRXQ_Pos                          (16U)
+#define ETH_MTLRQDR_PRXQ_Msk                          (0x3FFFUL << ETH_MTLRQDR_PRXQ_Pos) /*!< 0x3FFF0000 */
+#define ETH_MTLRQDR_PRXQ                              ETH_MTLRQDR_PRXQ_Msk     /* Number of Packets in Receive Queue */
+#define ETH_MTLRQDR_RXQSTS_Pos                        (4U)
+#define ETH_MTLRQDR_RXQSTS_Msk                        (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */
+#define ETH_MTLRQDR_RXQSTS                            ETH_MTLRQDR_RXQSTS_Msk   /* MTL Rx Queue Fill-Level Status */
+#define ETH_MTLRQDR_RXQSTS_EMPTY                      ((uint32_t)0x00000000)   /* Rx Queue empty */
+#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos         (4U)
+#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
+#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD             ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
+#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos         (5U)
+#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos) /*!< 0x00000020 */
+#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD             ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk /* Rx Queue fill-level above flow-control activate threshold */
+#define ETH_MTLRQDR_RXQSTS_FULL_Pos                   (4U)
+#define ETH_MTLRQDR_RXQSTS_FULL_Msk                   (0x3UL << ETH_MTLRQDR_RXQSTS_FULL_Pos) /*!< 0x00000030 */
+#define ETH_MTLRQDR_RXQSTS_FULL                       ETH_MTLRQDR_RXQSTS_FULL_Msk /* Rx Queue full */
+#define ETH_MTLRQDR_RRCSTS_Pos                        (1U)
+#define ETH_MTLRQDR_RRCSTS_Msk                        (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */
+#define ETH_MTLRQDR_RRCSTS                            ETH_MTLRQDR_RRCSTS_Msk   /* MTL Rx Queue Read Controller State */
+#define ETH_MTLRQDR_RRCSTS_IDLE                       ((uint32_t)0x00000000)   /* Idle state */
+#define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos            (1U)
+#define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk            (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
+#define ETH_MTLRQDR_RRCSTS_READINGDATA                ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
+#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos          (2U)
+#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk          (0x1UL << ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos) /*!< 0x00000004 */
+#define ETH_MTLRQDR_RRCSTS_READINGSTATUS              ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk /* Reading packet status (or timestamp) */
+#define ETH_MTLRQDR_RRCSTS_FLUSHING_Pos               (1U)
+#define ETH_MTLRQDR_RRCSTS_FLUSHING_Msk               (0x3UL << ETH_MTLRQDR_RRCSTS_FLUSHING_Pos) /*!< 0x00000006 */
+#define ETH_MTLRQDR_RRCSTS_FLUSHING                   ETH_MTLRQDR_RRCSTS_FLUSHING_Msk /* Flushing the packet data and status */
+#define ETH_MTLRQDR_RWCSTS_Pos                        (0U)
+#define ETH_MTLRQDR_RWCSTS_Msk                        (0x1UL << ETH_MTLRQDR_RWCSTS_Pos) /*!< 0x00000001 */
+#define ETH_MTLRQDR_RWCSTS                            ETH_MTLRQDR_RWCSTS_Msk   /* MTL Rx Queue Write Controller Active Status */
+
+/* Bit definition for Ethernet MTL Rx Queue Control Register */
+#define ETH_MTLRQCR_RQPA_Pos                          (3U)
+#define ETH_MTLRQCR_RQPA_Msk                          (0x1UL << ETH_MTLRQCR_RQPA_Pos) /*!< 0x00000008 */
+#define ETH_MTLRQCR_RQPA                              ETH_MTLRQCR_RQPA_Msk     /* Receive Queue Packet Arbitration */
+#define ETH_MTLRQCR_RQW_Pos                           (0U)
+#define ETH_MTLRQCR_RQW_Msk                           (0x7UL << ETH_MTLRQCR_RQW_Pos) /*!< 0x00000007 */
+#define ETH_MTLRQCR_RQW                               ETH_MTLRQCR_RQW_Msk      /* Receive Queue Weight */
+
+/* Bit definition for Ethernet DMA Mode Register */
+#define ETH_DMAMR_INTM_Pos                            (16U)
+#define ETH_DMAMR_INTM_Msk                            (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */
+#define ETH_DMAMR_INTM                                ETH_DMAMR_INTM_Msk       /* This field defines the interrupt mode */
+#define ETH_DMAMR_INTM_0                              (0x0UL << ETH_DMAMR_INTM_Pos) /*!< 0x00000000 */
+#define ETH_DMAMR_INTM_1                              (0x1UL << ETH_DMAMR_INTM_Pos) /*!< 0x00010000 */
+#define ETH_DMAMR_INTM_2                              (0x2UL << ETH_DMAMR_INTM_Pos) /*!< 0x00020000 */
+#define ETH_DMAMR_PR_Pos                              (12U)
+#define ETH_DMAMR_PR_Msk                              (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
+#define ETH_DMAMR_PR                                  ETH_DMAMR_PR_Msk         /* Priority Ratio */
+#define ETH_DMAMR_PR_1_1                              ((uint32_t)0x00000000)   /* The priority ratio is 1:1 */
+#define ETH_DMAMR_PR_2_1                              ((uint32_t)0x00001000)   /* The priority ratio is 2:1 */
+#define ETH_DMAMR_PR_3_1                              ((uint32_t)0x00002000)   /* The priority ratio is 3:1 */
+#define ETH_DMAMR_PR_4_1                              ((uint32_t)0x00003000)   /* The priority ratio is 4:1 */
+#define ETH_DMAMR_PR_5_1                              ((uint32_t)0x00004000)   /* The priority ratio is 5:1 */
+#define ETH_DMAMR_PR_6_1                              ((uint32_t)0x00005000)   /* The priority ratio is 6:1 */
+#define ETH_DMAMR_PR_7_1                              ((uint32_t)0x00006000)   /* The priority ratio is 7:1 */
+#define ETH_DMAMR_PR_8_1                              ((uint32_t)0x00007000)   /* The priority ratio is 8:1 */
+#define ETH_DMAMR_TXPR_Pos                            (11U)
+#define ETH_DMAMR_TXPR_Msk                            (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
+#define ETH_DMAMR_TXPR                                ETH_DMAMR_TXPR_Msk       /* Transmit Priority */
+#define ETH_DMAMR_DA_Pos                              (1U)
+#define ETH_DMAMR_DA_Msk                              (0x1UL << ETH_DMAMR_DA_Pos) /*!< 0x00000002 */
+#define ETH_DMAMR_DA                                  ETH_DMAMR_DA_Msk         /* DMA Tx or Rx Arbitration Scheme */
+#define ETH_DMAMR_SWR_Pos                             (0U)
+#define ETH_DMAMR_SWR_Msk                             (0x1UL << ETH_DMAMR_SWR_Pos) /*!< 0x00000001 */
+#define ETH_DMAMR_SWR                                 ETH_DMAMR_SWR_Msk        /* Software Reset */
+
+/* Bit definition for Ethernet DMA SysBus Mode Register */
+#define ETH_DMASBMR_RB_Pos                            (15U)
+#define ETH_DMASBMR_RB_Msk                            (0x1UL << ETH_DMASBMR_RB_Pos) /*!< 0x00008000 */
+#define ETH_DMASBMR_RB                                ETH_DMASBMR_RB_Msk       /* Rebuild INCRx Burst */
+#define ETH_DMASBMR_MB_Pos                            (14U)
+#define ETH_DMASBMR_MB_Msk                            (0x1UL << ETH_DMASBMR_MB_Pos) /*!< 0x00004000 */
+#define ETH_DMASBMR_MB                                ETH_DMASBMR_MB_Msk       /* Mixed Burst */
+#define ETH_DMASBMR_AAL_Pos                           (12U)
+#define ETH_DMASBMR_AAL_Msk                           (0x1UL << ETH_DMASBMR_AAL_Pos) /*!< 0x00001000 */
+#define ETH_DMASBMR_AAL                               ETH_DMASBMR_AAL_Msk      /* Address-Aligned Beats */
+#define ETH_DMASBMR_FB_Pos                            (0U)
+#define ETH_DMASBMR_FB_Msk                            (0x1UL << ETH_DMASBMR_FB_Pos) /*!< 0x00000001 */
+#define ETH_DMASBMR_FB                                ETH_DMASBMR_FB_Msk       /* Fixed Burst Length */
+
+/* Bit definition for Ethernet DMA Interrupt Status Register */
+#define ETH_DMAISR_MACIS_Pos                          (17U)
+#define ETH_DMAISR_MACIS_Msk                          (0x1UL << ETH_DMAISR_MACIS_Pos) /*!< 0x00020000 */
+#define ETH_DMAISR_MACIS                              ETH_DMAISR_MACIS_Msk     /* MAC Interrupt Status */
+#define ETH_DMAISR_MTLIS_Pos                          (16U)
+#define ETH_DMAISR_MTLIS_Msk                          (0x1UL << ETH_DMAISR_MTLIS_Pos) /*!< 0x00010000 */
+#define ETH_DMAISR_MTLIS                              ETH_DMAISR_MTLIS_Msk     /* MAC Interrupt Status */
+#define ETH_DMAISR_DMACIS_Pos                         (0U)
+#define ETH_DMAISR_DMACIS_Msk                         (0x1UL << ETH_DMAISR_DMACIS_Pos) /*!< 0x00000001 */
+#define ETH_DMAISR_DMACIS                             ETH_DMAISR_DMACIS_Msk    /* DMA Channel Interrupt Status */
+
+/* Bit definition for Ethernet DMA Debug Status Register */
+#define ETH_DMADSR_TPS_Pos                            (12U)
+#define ETH_DMADSR_TPS_Msk                            (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */
+#define ETH_DMADSR_TPS                                ETH_DMADSR_TPS_Msk       /* DMA Channel Transmit Process State */
+#define ETH_DMADSR_TPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Transmit Command issued) */
+#define ETH_DMADSR_TPS_FETCHING_Pos                   (12U)
+#define ETH_DMADSR_TPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */
+#define ETH_DMADSR_TPS_FETCHING                       ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
+#define ETH_DMADSR_TPS_WAITING_Pos                    (13U)
+#define ETH_DMADSR_TPS_WAITING_Msk                    (0x1UL << ETH_DMADSR_TPS_WAITING_Pos) /*!< 0x00002000 */
+#define ETH_DMADSR_TPS_WAITING                        ETH_DMADSR_TPS_WAITING_Msk /* Running (Waiting for status) */
+#define ETH_DMADSR_TPS_READING_Pos                    (12U)
+#define ETH_DMADSR_TPS_READING_Msk                    (0x3UL << ETH_DMADSR_TPS_READING_Pos) /*!< 0x00003000 */
+#define ETH_DMADSR_TPS_READING                        ETH_DMADSR_TPS_READING_Msk /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */
+#define ETH_DMADSR_TPS_TIMESTAMP_WR_Pos               (14U)
+#define ETH_DMADSR_TPS_TIMESTAMP_WR_Msk               (0x1UL << ETH_DMADSR_TPS_TIMESTAMP_WR_Pos) /*!< 0x00004000 */
+#define ETH_DMADSR_TPS_TIMESTAMP_WR                   ETH_DMADSR_TPS_TIMESTAMP_WR_Msk /* Timestamp write state */
+#define ETH_DMADSR_TPS_SUSPENDED_Pos                  (13U)
+#define ETH_DMADSR_TPS_SUSPENDED_Msk                  (0x3UL << ETH_DMADSR_TPS_SUSPENDED_Pos) /*!< 0x00006000 */
+#define ETH_DMADSR_TPS_SUSPENDED                      ETH_DMADSR_TPS_SUSPENDED_Msk /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */
+#define ETH_DMADSR_TPS_CLOSING_Pos                    (12U)
+#define ETH_DMADSR_TPS_CLOSING_Msk                    (0x7UL << ETH_DMADSR_TPS_CLOSING_Pos) /*!< 0x00007000 */
+#define ETH_DMADSR_TPS_CLOSING                        ETH_DMADSR_TPS_CLOSING_Msk /* Running (Closing Tx Descriptor) */
+#define ETH_DMADSR_RPS_Pos                            (8U)
+#define ETH_DMADSR_RPS_Msk                            (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */
+#define ETH_DMADSR_RPS                                ETH_DMADSR_RPS_Msk       /* DMA Channel Receive Process State */
+#define ETH_DMADSR_RPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Receive Command issued) */
+#define ETH_DMADSR_RPS_FETCHING_Pos                   (12U)
+#define ETH_DMADSR_RPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */
+#define ETH_DMADSR_RPS_FETCHING                       ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
+#define ETH_DMADSR_RPS_WAITING_Pos                    (12U)
+#define ETH_DMADSR_RPS_WAITING_Msk                    (0x3UL << ETH_DMADSR_RPS_WAITING_Pos) /*!< 0x00003000 */
+#define ETH_DMADSR_RPS_WAITING                        ETH_DMADSR_RPS_WAITING_Msk /* Running (Waiting for status) */
+#define ETH_DMADSR_RPS_SUSPENDED_Pos                  (14U)
+#define ETH_DMADSR_RPS_SUSPENDED_Msk                  (0x1UL << ETH_DMADSR_RPS_SUSPENDED_Pos) /*!< 0x00004000 */
+#define ETH_DMADSR_RPS_SUSPENDED                      ETH_DMADSR_RPS_SUSPENDED_Msk /* Suspended (Rx Descriptor Unavailable) */
+#define ETH_DMADSR_RPS_CLOSING_Pos                    (12U)
+#define ETH_DMADSR_RPS_CLOSING_Msk                    (0x5UL << ETH_DMADSR_RPS_CLOSING_Pos) /*!< 0x00005000 */
+#define ETH_DMADSR_RPS_CLOSING                        ETH_DMADSR_RPS_CLOSING_Msk /* Running (Closing the Rx Descriptor) */
+#define ETH_DMADSR_RPS_TIMESTAMP_WR_Pos               (13U)
+#define ETH_DMADSR_RPS_TIMESTAMP_WR_Msk               (0x3UL << ETH_DMADSR_RPS_TIMESTAMP_WR_Pos) /*!< 0x00006000 */
+#define ETH_DMADSR_RPS_TIMESTAMP_WR                   ETH_DMADSR_RPS_TIMESTAMP_WR_Msk /* Timestamp write state */
+#define ETH_DMADSR_RPS_TRANSFERRING_Pos               (12U)
+#define ETH_DMADSR_RPS_TRANSFERRING_Msk               (0x7UL << ETH_DMADSR_RPS_TRANSFERRING_Pos) /*!< 0x00007000 */
+#define ETH_DMADSR_RPS_TRANSFERRING                   ETH_DMADSR_RPS_TRANSFERRING_Msk /* Running (Transferring the received packet data from the Rx buffer to the system memory) */
+
+/* Bit definition for Ethernet DMA Channel Control Register */
+#define ETH_DMACCR_DSL_Pos                            (18U)
+#define ETH_DMACCR_DSL_Msk                            (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */
+#define ETH_DMACCR_DSL                                ETH_DMACCR_DSL_Msk       /* Descriptor Skip Length */
+#define ETH_DMACCR_DSL_0BIT                           ((uint32_t)0x00000000)
+#define ETH_DMACCR_DSL_32BIT                          ((uint32_t)0x00040000)
+#define ETH_DMACCR_DSL_64BIT                          ((uint32_t)0x00080000)
+#define ETH_DMACCR_DSL_128BIT                         ((uint32_t)0x00100000)
+#define ETH_DMACCR_8PBL                               ((uint32_t)0x00010000)   /* 8xPBL mode */
+#define ETH_DMACCR_MSS_Pos                            (0U)
+#define ETH_DMACCR_MSS_Msk                            (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */
+#define ETH_DMACCR_MSS                                ETH_DMACCR_MSS_Msk       /* Maximum Segment Size */
+
+/* Bit definition for Ethernet DMA Channel Tx Control Register */
+#define ETH_DMACTCR_TPBL_Pos                          (16U)
+#define ETH_DMACTCR_TPBL_Msk                          (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */
+#define ETH_DMACTCR_TPBL                              ETH_DMACTCR_TPBL_Msk     /* Transmit Programmable Burst Length */
+#define ETH_DMACTCR_TPBL_1PBL                         ((uint32_t)0x00010000)   /* Transmit Programmable Burst Length 1 */
+#define ETH_DMACTCR_TPBL_2PBL                         ((uint32_t)0x00020000)   /* Transmit Programmable Burst Length 2 */
+#define ETH_DMACTCR_TPBL_4PBL                         ((uint32_t)0x00040000)   /* Transmit Programmable Burst Length 4 */
+#define ETH_DMACTCR_TPBL_8PBL                         ((uint32_t)0x00080000)   /* Transmit Programmable Burst Length 8 */
+#define ETH_DMACTCR_TPBL_16PBL                        ((uint32_t)0x00100000)   /* Transmit Programmable Burst Length 16 */
+#define ETH_DMACTCR_TPBL_32PBL                        ((uint32_t)0x00200000)   /* Transmit Programmable Burst Length 32 */
+#define ETH_DMACTCR_TSE_Pos                           (12U)
+#define ETH_DMACTCR_TSE_Msk                           (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */
+#define ETH_DMACTCR_TSE                               ETH_DMACTCR_TSE_Msk      /* TCP Segmentation Enabled */
+#define ETH_DMACTCR_OSP_Pos                           (4U)
+#define ETH_DMACTCR_OSP_Msk                           (0x1UL << ETH_DMACTCR_OSP_Pos) /*!< 0x00000010 */
+#define ETH_DMACTCR_OSP                               ETH_DMACTCR_OSP_Msk      /* Operate on Second Packet */
+#define ETH_DMACTCR_ST_Pos                            (0U)
+#define ETH_DMACTCR_ST_Msk                            (0x1UL << ETH_DMACTCR_ST_Pos) /*!< 0x00000001 */
+#define ETH_DMACTCR_ST                                ETH_DMACTCR_ST_Msk       /* Start or Stop Transmission Command */
+
+/* Bit definition for Ethernet DMA Channel Rx Control Register */
+#define ETH_DMACRCR_RPF_Pos                           (31U)
+#define ETH_DMACRCR_RPF_Msk                           (0x1UL << ETH_DMACRCR_RPF_Pos) /*!< 0x80000000 */
+#define ETH_DMACRCR_RPF                               ETH_DMACRCR_RPF_Msk      /* Rx Packet Flush */
+#define ETH_DMACRCR_RPBL_Pos                          (16U)
+#define ETH_DMACRCR_RPBL_Msk                          (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */
+#define ETH_DMACRCR_RPBL                              ETH_DMACRCR_RPBL_Msk     /* Receive Programmable Burst Length */
+#define ETH_DMACRCR_RPBL_1PBL                         ((uint32_t)0x00010000)   /* Receive Programmable Burst Length 1 */
+#define ETH_DMACRCR_RPBL_2PBL                         ((uint32_t)0x00020000)   /* Receive Programmable Burst Length 2 */
+#define ETH_DMACRCR_RPBL_4PBL                         ((uint32_t)0x00040000)   /* Receive Programmable Burst Length 4 */
+#define ETH_DMACRCR_RPBL_8PBL                         ((uint32_t)0x00080000)   /* Receive Programmable Burst Length 8 */
+#define ETH_DMACRCR_RPBL_16PBL                        ((uint32_t)0x00100000)   /* Receive Programmable Burst Length 16 */
+#define ETH_DMACRCR_RPBL_32PBL                        ((uint32_t)0x00200000)   /* Receive Programmable Burst Length 32 */
+#define ETH_DMACRCR_RBSZ_Pos                          (1U)
+#define ETH_DMACRCR_RBSZ_Msk                          (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */
+#define ETH_DMACRCR_RBSZ                              ETH_DMACRCR_RBSZ_Msk     /* Receive Buffer size */
+#define ETH_DMACRCR_SR_Pos                            (0U)
+#define ETH_DMACRCR_SR_Msk                            (0x1UL << ETH_DMACRCR_SR_Pos) /*!< 0x00000001 */
+#define ETH_DMACRCR_SR                                ETH_DMACRCR_SR_Msk       /* Start or Stop Receive */
+
+/* Bit definition for Ethernet DMA CH Tx Desc List Address Register */
+#define ETH_DMACTDLAR_TDESLA_Pos                      (2U)
+#define ETH_DMACTDLAR_TDESLA_Msk                      (0x3FFFFFFFUL << ETH_DMACTDLAR_TDESLA_Pos) /*!< 0xFFFFFFFC */
+#define ETH_DMACTDLAR_TDESLA                          ETH_DMACTDLAR_TDESLA_Msk /* Start of Transmit List */
+
+/* Bit definition for Ethernet DMA CH Rx Desc List Address Register */
+#define ETH_DMACRDLAR_RDESLA_Pos                      (2U)
+#define ETH_DMACRDLAR_RDESLA_Msk                      (0x3FFFFFFFUL << ETH_DMACRDLAR_RDESLA_Pos) /*!< 0xFFFFFFFC */
+#define ETH_DMACRDLAR_RDESLA                          ETH_DMACRDLAR_RDESLA_Msk /* Start of Receive List */
+
+/* Bit definition for Ethernet DMA CH Tx Desc Tail Pointer Register */
+#define ETH_DMACTDTPR_TDT_Pos                         (2U)
+#define ETH_DMACTDTPR_TDT_Msk                         (0x3FFFFFFFUL << ETH_DMACTDTPR_TDT_Pos) /*!< 0xFFFFFFFC */
+#define ETH_DMACTDTPR_TDT                             ETH_DMACTDTPR_TDT_Msk    /* Transmit Descriptor Tail Pointer */
+
+/* Bit definition for Ethernet DMA CH Rx Desc Tail Pointer Register */
+#define ETH_DMACRDTPR_RDT_Pos                         (2U)
+#define ETH_DMACRDTPR_RDT_Msk                         (0x3FFFFFFFUL << ETH_DMACRDTPR_RDT_Pos) /*!< 0xFFFFFFFC */
+#define ETH_DMACRDTPR_RDT                             ETH_DMACRDTPR_RDT_Msk    /* Receive Descriptor Tail Pointer */
+
+/* Bit definition for Ethernet DMA CH Tx Desc Ring Length Register */
+#define ETH_DMACTDRLR_TDRL_Pos                        (0U)
+#define ETH_DMACTDRLR_TDRL_Msk                        (0x3FFUL << ETH_DMACTDRLR_TDRL_Pos) /*!< 0x000003FF */
+#define ETH_DMACTDRLR_TDRL                            ETH_DMACTDRLR_TDRL_Msk   /* Transmit Descriptor Ring Length */
+
+/* Bit definition for Ethernet DMA CH Rx Desc Ring Length Register */
+#define ETH_DMACRDRLR_RDRL_Pos                        (0U)
+#define ETH_DMACRDRLR_RDRL_Msk                        (0x3FFUL << ETH_DMACRDRLR_RDRL_Pos) /*!< 0x000003FF */
+#define ETH_DMACRDRLR_RDRL                            ETH_DMACRDRLR_RDRL_Msk   /* Receive Descriptor Ring Length */
+
+/* Bit definition for Ethernet DMA Channel Interrupt Enable Register */
+#define ETH_DMACIER_NIE_Pos                           (15U)
+#define ETH_DMACIER_NIE_Msk                           (0x1UL << ETH_DMACIER_NIE_Pos) /*!< 0x00008000 */
+#define ETH_DMACIER_NIE                               ETH_DMACIER_NIE_Msk      /* Normal Interrupt Summary Enable */
+#define ETH_DMACIER_AIE_Pos                           (14U)
+#define ETH_DMACIER_AIE_Msk                           (0x1UL << ETH_DMACIER_AIE_Pos) /*!< 0x00004000 */
+#define ETH_DMACIER_AIE                               ETH_DMACIER_AIE_Msk      /* Abnormal Interrupt Summary Enable */
+#define ETH_DMACIER_CDEE_Pos                          (13U)
+#define ETH_DMACIER_CDEE_Msk                          (0x1UL << ETH_DMACIER_CDEE_Pos) /*!< 0x00002000 */
+#define ETH_DMACIER_CDEE                              ETH_DMACIER_CDEE_Msk     /* Context Descriptor Error Enable */
+#define ETH_DMACIER_FBEE_Pos                          (12U)
+#define ETH_DMACIER_FBEE_Msk                          (0x1UL << ETH_DMACIER_FBEE_Pos) /*!< 0x00001000 */
+#define ETH_DMACIER_FBEE                              ETH_DMACIER_FBEE_Msk     /* Fatal Bus Error Enable */
+#define ETH_DMACIER_ERIE_Pos                          (11U)
+#define ETH_DMACIER_ERIE_Msk                          (0x1UL << ETH_DMACIER_ERIE_Pos) /*!< 0x00000800 */
+#define ETH_DMACIER_ERIE                              ETH_DMACIER_ERIE_Msk     /* Early Receive Interrupt Enable */
+#define ETH_DMACIER_ETIE_Pos                          (10U)
+#define ETH_DMACIER_ETIE_Msk                          (0x1UL << ETH_DMACIER_ETIE_Pos) /*!< 0x00000400 */
+#define ETH_DMACIER_ETIE                              ETH_DMACIER_ETIE_Msk     /* Early Transmit Interrupt Enable */
+#define ETH_DMACIER_RWTE_Pos                          (9U)
+#define ETH_DMACIER_RWTE_Msk                          (0x1UL << ETH_DMACIER_RWTE_Pos) /*!< 0x00000200 */
+#define ETH_DMACIER_RWTE                              ETH_DMACIER_RWTE_Msk     /* Receive Watchdog Timeout Enable */
+#define ETH_DMACIER_RSE_Pos                           (8U)
+#define ETH_DMACIER_RSE_Msk                           (0x1UL << ETH_DMACIER_RSE_Pos) /*!< 0x00000100 */
+#define ETH_DMACIER_RSE                               ETH_DMACIER_RSE_Msk      /* Receive Stopped Enable */
+#define ETH_DMACIER_RBUE_Pos                          (7U)
+#define ETH_DMACIER_RBUE_Msk                          (0x1UL << ETH_DMACIER_RBUE_Pos) /*!< 0x00000080 */
+#define ETH_DMACIER_RBUE                              ETH_DMACIER_RBUE_Msk     /* Receive Buffer Unavailable Enable */
+#define ETH_DMACIER_RIE_Pos                           (6U)
+#define ETH_DMACIER_RIE_Msk                           (0x1UL << ETH_DMACIER_RIE_Pos) /*!< 0x00000040 */
+#define ETH_DMACIER_RIE                               ETH_DMACIER_RIE_Msk      /* Receive Interrupt Enable */
+#define ETH_DMACIER_TBUE_Pos                          (2U)
+#define ETH_DMACIER_TBUE_Msk                          (0x1UL << ETH_DMACIER_TBUE_Pos) /*!< 0x00000004 */
+#define ETH_DMACIER_TBUE                              ETH_DMACIER_TBUE_Msk     /* Transmit Buffer Unavailable Enable */
+#define ETH_DMACIER_TXSE_Pos                          (1U)
+#define ETH_DMACIER_TXSE_Msk                          (0x1UL << ETH_DMACIER_TXSE_Pos) /*!< 0x00000002 */
+#define ETH_DMACIER_TXSE                              ETH_DMACIER_TXSE_Msk     /* Transmit Stopped Enable */
+#define ETH_DMACIER_TIE_Pos                           (0U)
+#define ETH_DMACIER_TIE_Msk                           (0x1UL << ETH_DMACIER_TIE_Pos) /*!< 0x00000001 */
+#define ETH_DMACIER_TIE                               ETH_DMACIER_TIE_Msk      /* Transmit Interrupt Enable */
+
+/* Bit definition for Ethernet DMA Channel Rx Interrupt Watchdog Timer Register */
+#define ETH_DMACRIWTR_RWT_Pos                         (0U)
+#define ETH_DMACRIWTR_RWT_Msk                         (0xFFUL << ETH_DMACRIWTR_RWT_Pos) /*!< 0x000000FF */
+#define ETH_DMACRIWTR_RWT                             ETH_DMACRIWTR_RWT_Msk    /* Receive Interrupt Watchdog Timer Count */
+
+/* Bit definition for Ethernet DMA Channel Current App Tx Desc Register */
+#define ETH_DMACCATDR_CURTDESAPTR_Pos                 (0U)
+#define ETH_DMACCATDR_CURTDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCATDR_CURTDESAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACCATDR_CURTDESAPTR                     ETH_DMACCATDR_CURTDESAPTR_Msk /* Application Transmit Descriptor Address Pointer */
+
+/* Bit definition for Ethernet DMA Channel Current App Rx Desc Register */
+#define ETH_DMACCARDR_CURRDESAPTR_Pos                 (0U)
+#define ETH_DMACCARDR_CURRDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCARDR_CURRDESAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACCARDR_CURRDESAPTR                     ETH_DMACCARDR_CURRDESAPTR_Msk /* Application Receive Descriptor Address Pointer */
+
+/* Bit definition for Ethernet DMA Channel Current App Tx Buffer Register */
+#define ETH_DMACCATBR_CURTBUFAPTR_Pos                 (0U)
+#define ETH_DMACCATBR_CURTBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCATBR_CURTBUFAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACCATBR_CURTBUFAPTR                     ETH_DMACCATBR_CURTBUFAPTR_Msk /* Application Transmit Buffer Address Pointer */
+
+/* Bit definition for Ethernet DMA Channel Current App Rx Buffer Register */
+#define ETH_DMACCARBR_CURRBUFAPTR_Pos                 (0U)
+#define ETH_DMACCARBR_CURRBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCARBR_CURRBUFAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACCARBR_CURRBUFAPTR                     ETH_DMACCARBR_CURRBUFAPTR_Msk /* Application Receive Buffer Address Pointer */
+
+/* Bit definition for Ethernet DMA Channel Status Register */
+#define ETH_DMACSR_REB_Pos                            (19U)
+#define ETH_DMACSR_REB_Msk                            (0x7UL << ETH_DMACSR_REB_Pos) /*!< 0x00380000 */
+#define ETH_DMACSR_REB                                ETH_DMACSR_REB_Msk       /* Rx DMA Error Bits */
+#define ETH_DMACSR_TEB_Pos                            (16U)
+#define ETH_DMACSR_TEB_Msk                            (0x7UL << ETH_DMACSR_TEB_Pos) /*!< 0x00070000 */
+#define ETH_DMACSR_TEB                                ETH_DMACSR_TEB_Msk       /* Tx DMA Error Bits */
+#define ETH_DMACSR_NIS_Pos                            (15U)
+#define ETH_DMACSR_NIS_Msk                            (0x1UL << ETH_DMACSR_NIS_Pos) /*!< 0x00008000 */
+#define ETH_DMACSR_NIS                                ETH_DMACSR_NIS_Msk       /* Normal Interrupt Summary */
+#define ETH_DMACSR_AIS_Pos                            (14U)
+#define ETH_DMACSR_AIS_Msk                            (0x1UL << ETH_DMACSR_AIS_Pos) /*!< 0x00004000 */
+#define ETH_DMACSR_AIS                                ETH_DMACSR_AIS_Msk       /* Abnormal Interrupt Summary */
+#define ETH_DMACSR_CDE_Pos                            (13U)
+#define ETH_DMACSR_CDE_Msk                            (0x1UL << ETH_DMACSR_CDE_Pos) /*!< 0x00002000 */
+#define ETH_DMACSR_CDE                                ETH_DMACSR_CDE_Msk       /* Context Descriptor Error */
+#define ETH_DMACSR_FBE_Pos                            (12U)
+#define ETH_DMACSR_FBE_Msk                            (0x1UL << ETH_DMACSR_FBE_Pos) /*!< 0x00001000 */
+#define ETH_DMACSR_FBE                                ETH_DMACSR_FBE_Msk       /* Fatal Bus Error */
+#define ETH_DMACSR_ERI_Pos                            (11U)
+#define ETH_DMACSR_ERI_Msk                            (0x1UL << ETH_DMACSR_ERI_Pos) /*!< 0x00000800 */
+#define ETH_DMACSR_ERI                                ETH_DMACSR_ERI_Msk       /* Early Receive Interrupt */
+#define ETH_DMACSR_ETI_Pos                            (10U)
+#define ETH_DMACSR_ETI_Msk                            (0x1UL << ETH_DMACSR_ETI_Pos) /*!< 0x00000400 */
+#define ETH_DMACSR_ETI                                ETH_DMACSR_ETI_Msk       /* Early Transmit Interrupt */
+#define ETH_DMACSR_RWT_Pos                            (9U)
+#define ETH_DMACSR_RWT_Msk                            (0x1UL << ETH_DMACSR_RWT_Pos) /*!< 0x00000200 */
+#define ETH_DMACSR_RWT                                ETH_DMACSR_RWT_Msk       /* Receive Watchdog Timeout */
+#define ETH_DMACSR_RPS_Pos                            (8U)
+#define ETH_DMACSR_RPS_Msk                            (0x1UL << ETH_DMACSR_RPS_Pos) /*!< 0x00000100 */
+#define ETH_DMACSR_RPS                                ETH_DMACSR_RPS_Msk       /* Receive Process Stopped */
+#define ETH_DMACSR_RBU_Pos                            (7U)
+#define ETH_DMACSR_RBU_Msk                            (0x1UL << ETH_DMACSR_RBU_Pos) /*!< 0x00000080 */
+#define ETH_DMACSR_RBU                                ETH_DMACSR_RBU_Msk       /* Receive Buffer Unavailable */
+#define ETH_DMACSR_RI_Pos                             (6U)
+#define ETH_DMACSR_RI_Msk                             (0x1UL << ETH_DMACSR_RI_Pos) /*!< 0x00000040 */
+#define ETH_DMACSR_RI                                 ETH_DMACSR_RI_Msk        /* Receive Interrupt */
+#define ETH_DMACSR_TBU_Pos                            (2U)
+#define ETH_DMACSR_TBU_Msk                            (0x1UL << ETH_DMACSR_TBU_Pos) /*!< 0x00000004 */
+#define ETH_DMACSR_TBU                                ETH_DMACSR_TBU_Msk       /* Transmit Buffer Unavailable */
+#define ETH_DMACSR_TPS_Pos                            (1U)
+#define ETH_DMACSR_TPS_Msk                            (0x1UL << ETH_DMACSR_TPS_Pos) /*!< 0x00000002 */
+#define ETH_DMACSR_TPS                                ETH_DMACSR_TPS_Msk       /* Transmit Process Stopped */
+#define ETH_DMACSR_TI_Pos                             (0U)
+#define ETH_DMACSR_TI_Msk                             (0x1UL << ETH_DMACSR_TI_Pos) /*!< 0x00000001 */
+#define ETH_DMACSR_TI                                 ETH_DMACSR_TI_Msk        /* Transmit Interrupt */
+
+/* Bit definition for Ethernet DMA Channel missed frame count register */
+#define ETH_DMACMFCR_MFCO_Pos                         (15U)
+#define ETH_DMACMFCR_MFCO_Msk                         (0x1UL << ETH_DMACMFCR_MFCO_Pos) /*!< 0x00008000 */
+#define ETH_DMACMFCR_MFCO                             ETH_DMACMFCR_MFCO_Msk    /* Overflow status of the MFC Counter */
+#define ETH_DMACMFCR_MFC_Pos                          (0U)
+#define ETH_DMACMFCR_MFC_Msk                          (0x7FFUL << ETH_DMACMFCR_MFC_Pos) /*!< 0x000007FF */
+#define ETH_DMACMFCR_MFC                              ETH_DMACMFCR_MFC_Msk     /* The number of packet counters dropped by the DMA */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             DMA Controller                                 */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for DMA_SxCR register  *****************/
+#define DMA_SxCR_MBURST_Pos      (23U)
+#define DMA_SxCR_MBURST_Msk      (0x3UL << DMA_SxCR_MBURST_Pos)                /*!< 0x01800000 */
+#define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk                           /*!< Memory burst transfer configuration */
+#define DMA_SxCR_MBURST_0        (0x1UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */
+#define DMA_SxCR_MBURST_1        (0x2UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */
+#define DMA_SxCR_PBURST_Pos      (21U)
+#define DMA_SxCR_PBURST_Msk      (0x3UL << DMA_SxCR_PBURST_Pos)                /*!< 0x00600000 */
+#define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk                           /*!< Peripheral burst transfer configuration */
+#define DMA_SxCR_PBURST_0        (0x1UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */
+#define DMA_SxCR_PBURST_1        (0x2UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */
+#define DMA_SxCR_TRBUFF_Pos      (20U)
+#define DMA_SxCR_TRBUFF_Msk      (0x1UL << DMA_SxCR_TRBUFF_Pos)                 /*!< 0x00100000 */
+#define DMA_SxCR_TRBUFF          DMA_SxCR_TRBUFF_Msk                            /*!< bufferable transfers enabled/disable */
+#define DMA_SxCR_CT_Pos          (19U)
+#define DMA_SxCR_CT_Msk          (0x1UL << DMA_SxCR_CT_Pos)                    /*!< 0x00080000 */
+#define DMA_SxCR_CT              DMA_SxCR_CT_Msk                               /*!< Current target (only in double buffer mode) */
+#define DMA_SxCR_DBM_Pos         (18U)
+#define DMA_SxCR_DBM_Msk         (0x1UL << DMA_SxCR_DBM_Pos)                   /*!< 0x00040000 */
+#define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk                              /*!< Double buffer mode */
+#define DMA_SxCR_PL_Pos          (16U)
+#define DMA_SxCR_PL_Msk          (0x3UL << DMA_SxCR_PL_Pos)                    /*!< 0x00030000 */
+#define DMA_SxCR_PL              DMA_SxCR_PL_Msk                               /*!< Priority level */
+#define DMA_SxCR_PL_0            (0x1UL << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */
+#define DMA_SxCR_PL_1            (0x2UL << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */
+#define DMA_SxCR_PINCOS_Pos      (15U)
+#define DMA_SxCR_PINCOS_Msk      (0x1UL << DMA_SxCR_PINCOS_Pos)                /*!< 0x00008000 */
+#define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk                           /*!< Peripheral increment offset size */
+#define DMA_SxCR_MSIZE_Pos       (13U)
+#define DMA_SxCR_MSIZE_Msk       (0x3UL << DMA_SxCR_MSIZE_Pos)                 /*!< 0x00006000 */
+#define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk                            /*!< Memory data size */
+#define DMA_SxCR_MSIZE_0         (0x1UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */
+#define DMA_SxCR_MSIZE_1         (0x2UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */
+#define DMA_SxCR_PSIZE_Pos       (11U)
+#define DMA_SxCR_PSIZE_Msk       (0x3UL << DMA_SxCR_PSIZE_Pos)                 /*!< 0x00001800 */
+#define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk                            /*< Peripheral data size */
+#define DMA_SxCR_PSIZE_0         (0x1UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */
+#define DMA_SxCR_PSIZE_1         (0x2UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */
+#define DMA_SxCR_MINC_Pos        (10U)
+#define DMA_SxCR_MINC_Msk        (0x1UL << DMA_SxCR_MINC_Pos)                  /*!< 0x00000400 */
+#define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk                             /*!< Memory increment mode */
+#define DMA_SxCR_PINC_Pos        (9U)
+#define DMA_SxCR_PINC_Msk        (0x1UL << DMA_SxCR_PINC_Pos)                  /*!< 0x00000200 */
+#define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk                             /*!< Peripheral increment mode */
+#define DMA_SxCR_CIRC_Pos        (8U)
+#define DMA_SxCR_CIRC_Msk        (0x1UL << DMA_SxCR_CIRC_Pos)                  /*!< 0x00000100 */
+#define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk                             /*!< Circular mode */
+#define DMA_SxCR_DIR_Pos         (6U)
+#define DMA_SxCR_DIR_Msk         (0x3UL << DMA_SxCR_DIR_Pos)                   /*!< 0x000000C0 */
+#define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk                              /*!< Data transfer direction */
+#define DMA_SxCR_DIR_0           (0x1UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */
+#define DMA_SxCR_DIR_1           (0x2UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */
+#define DMA_SxCR_PFCTRL_Pos      (5U)
+#define DMA_SxCR_PFCTRL_Msk      (0x1UL << DMA_SxCR_PFCTRL_Pos)                /*!< 0x00000020 */
+#define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk                           /*!< Peripheral flow controller */
+#define DMA_SxCR_TCIE_Pos        (4U)
+#define DMA_SxCR_TCIE_Msk        (0x1UL << DMA_SxCR_TCIE_Pos)                  /*!< 0x00000010 */
+#define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk                             /*!< Transfer complete interrupt enable */
+#define DMA_SxCR_HTIE_Pos        (3U)
+#define DMA_SxCR_HTIE_Msk        (0x1UL << DMA_SxCR_HTIE_Pos)                  /*!< 0x00000008 */
+#define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk                             /*!< Half transfer interrupt enable */
+#define DMA_SxCR_TEIE_Pos        (2U)
+#define DMA_SxCR_TEIE_Msk        (0x1UL << DMA_SxCR_TEIE_Pos)                  /*!< 0x00000004 */
+#define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk                             /*!< Transfer error interrupt enable */
+#define DMA_SxCR_DMEIE_Pos       (1U)
+#define DMA_SxCR_DMEIE_Msk       (0x1UL << DMA_SxCR_DMEIE_Pos)                 /*!< 0x00000002 */
+#define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk                            /*!< Direct mode error interrupt enable */
+#define DMA_SxCR_EN_Pos          (0U)
+#define DMA_SxCR_EN_Msk          (0x1UL << DMA_SxCR_EN_Pos)                    /*!< 0x00000001 */
+#define DMA_SxCR_EN              DMA_SxCR_EN_Msk                               /*!< Stream enable / flag stream ready when read low */
+
+/********************  Bits definition for DMA_SxCNDTR register  **************/
+#define DMA_SxNDT_Pos            (0U)
+#define DMA_SxNDT_Msk            (0xFFFFUL << DMA_SxNDT_Pos)                   /*!< 0x0000FFFF */
+#define DMA_SxNDT                DMA_SxNDT_Msk                                 /*!< Number of data items to transfer */
+#define DMA_SxNDT_0              (0x0001UL << DMA_SxNDT_Pos)                    /*!< 0x00000001 */
+#define DMA_SxNDT_1              (0x0002UL << DMA_SxNDT_Pos)                    /*!< 0x00000002 */
+#define DMA_SxNDT_2              (0x0004UL << DMA_SxNDT_Pos)                    /*!< 0x00000004 */
+#define DMA_SxNDT_3              (0x0008UL << DMA_SxNDT_Pos)                    /*!< 0x00000008 */
+#define DMA_SxNDT_4              (0x0010UL << DMA_SxNDT_Pos)                    /*!< 0x00000010 */
+#define DMA_SxNDT_5              (0x0020UL << DMA_SxNDT_Pos)                    /*!< 0x00000020 */
+#define DMA_SxNDT_6              (0x0040UL << DMA_SxNDT_Pos)                    /*!< 0x00000040 */
+#define DMA_SxNDT_7              (0x0080UL << DMA_SxNDT_Pos)                    /*!< 0x00000080 */
+#define DMA_SxNDT_8              (0x0100UL << DMA_SxNDT_Pos)                    /*!< 0x00000100 */
+#define DMA_SxNDT_9              (0x0200UL << DMA_SxNDT_Pos)                    /*!< 0x00000200 */
+#define DMA_SxNDT_10             (0x0400UL << DMA_SxNDT_Pos)                    /*!< 0x00000400 */
+#define DMA_SxNDT_11             (0x0800UL << DMA_SxNDT_Pos)                    /*!< 0x00000800 */
+#define DMA_SxNDT_12             (0x1000UL << DMA_SxNDT_Pos)                    /*!< 0x00001000 */
+#define DMA_SxNDT_13             (0x2000UL << DMA_SxNDT_Pos)                    /*!< 0x00002000 */
+#define DMA_SxNDT_14             (0x4000UL << DMA_SxNDT_Pos)                    /*!< 0x00004000 */
+#define DMA_SxNDT_15             (0x8000UL << DMA_SxNDT_Pos)                    /*!< 0x00008000 */
+
+/********************  Bits definition for DMA_SxFCR register  ****************/
+#define DMA_SxFCR_FEIE_Pos       (7U)
+#define DMA_SxFCR_FEIE_Msk       (0x1UL << DMA_SxFCR_FEIE_Pos)                 /*!< 0x00000080 */
+#define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk                            /*!< FIFO error interrupt enable */
+#define DMA_SxFCR_FS_Pos         (3U)
+#define DMA_SxFCR_FS_Msk         (0x7UL << DMA_SxFCR_FS_Pos)                   /*!< 0x00000038 */
+#define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk                              /*!< FIFO status */
+#define DMA_SxFCR_FS_0           (0x1UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */
+#define DMA_SxFCR_FS_1           (0x2UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */
+#define DMA_SxFCR_FS_2           (0x4UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */
+#define DMA_SxFCR_DMDIS_Pos      (2U)
+#define DMA_SxFCR_DMDIS_Msk      (0x1UL << DMA_SxFCR_DMDIS_Pos)                /*!< 0x00000004 */
+#define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk                           /*!< Direct mode disable */
+#define DMA_SxFCR_FTH_Pos        (0U)
+#define DMA_SxFCR_FTH_Msk        (0x3UL << DMA_SxFCR_FTH_Pos)                  /*!< 0x00000003 */
+#define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk                             /*!< FIFO threshold selection */
+#define DMA_SxFCR_FTH_0          (0x1UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */
+#define DMA_SxFCR_FTH_1          (0x2UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */
+
+/********************  Bits definition for DMA_LISR register  *****************/
+#define DMA_LISR_TCIF3_Pos       (27U)
+#define DMA_LISR_TCIF3_Msk       (0x1UL << DMA_LISR_TCIF3_Pos)                 /*!< 0x08000000 */
+#define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk                            /*!<  Stream 3 transfer complete interrupt flag */
+#define DMA_LISR_HTIF3_Pos       (26U)
+#define DMA_LISR_HTIF3_Msk       (0x1UL << DMA_LISR_HTIF3_Pos)                 /*!< 0x04000000 */
+#define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk                            /*!<  Stream 3 half transfer interrupt flag */
+#define DMA_LISR_TEIF3_Pos       (25U)
+#define DMA_LISR_TEIF3_Msk       (0x1UL << DMA_LISR_TEIF3_Pos)                 /*!< 0x02000000 */
+#define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk                            /*!<  Stream 3 transfer error interrupt flag */
+#define DMA_LISR_DMEIF3_Pos      (24U)
+#define DMA_LISR_DMEIF3_Msk      (0x1UL << DMA_LISR_DMEIF3_Pos)                /*!< 0x01000000 */
+#define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk                           /*!<  Stream 3 direct mode error interrupt flag */
+#define DMA_LISR_FEIF3_Pos       (22U)
+#define DMA_LISR_FEIF3_Msk       (0x1UL << DMA_LISR_FEIF3_Pos)                 /*!< 0x00400000 */
+#define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk                            /*!<  Stream 3 FIFO error interrupt flag */
+#define DMA_LISR_TCIF2_Pos       (21U)
+#define DMA_LISR_TCIF2_Msk       (0x1UL << DMA_LISR_TCIF2_Pos)                 /*!< 0x00200000 */
+#define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk                            /*!<  Stream 2 transfer complete interrupt flag */
+#define DMA_LISR_HTIF2_Pos       (20U)
+#define DMA_LISR_HTIF2_Msk       (0x1UL << DMA_LISR_HTIF2_Pos)                 /*!< 0x00100000 */
+#define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk                            /*!<  Stream 2 half transfer interrupt flag */
+#define DMA_LISR_TEIF2_Pos       (19U)
+#define DMA_LISR_TEIF2_Msk       (0x1UL << DMA_LISR_TEIF2_Pos)                 /*!< 0x00080000 */
+#define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk                            /*!<  Stream 2 transfer error interrupt flag */
+#define DMA_LISR_DMEIF2_Pos      (18U)
+#define DMA_LISR_DMEIF2_Msk      (0x1UL << DMA_LISR_DMEIF2_Pos)                /*!< 0x00040000 */
+#define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk                           /*!<  Stream 2 direct mode error interrupt flag */
+#define DMA_LISR_FEIF2_Pos       (16U)
+#define DMA_LISR_FEIF2_Msk       (0x1UL << DMA_LISR_FEIF2_Pos)                 /*!< 0x00010000 */
+#define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk                            /*!<  Stream 2 FIFO error interrupt flag */
+#define DMA_LISR_TCIF1_Pos       (11U)
+#define DMA_LISR_TCIF1_Msk       (0x1UL << DMA_LISR_TCIF1_Pos)                 /*!< 0x00000800 */
+#define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk                            /*!<  Stream 1 transfer complete interrupt flag */
+#define DMA_LISR_HTIF1_Pos       (10U)
+#define DMA_LISR_HTIF1_Msk       (0x1UL << DMA_LISR_HTIF1_Pos)                 /*!< 0x00000400 */
+#define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk                            /*!<  Stream 1 half transfer interrupt flag */
+#define DMA_LISR_TEIF1_Pos       (9U)
+#define DMA_LISR_TEIF1_Msk       (0x1UL << DMA_LISR_TEIF1_Pos)                 /*!< 0x00000200 */
+#define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk                            /*!<  Stream 1 transfer error interrupt flag */
+#define DMA_LISR_DMEIF1_Pos      (8U)
+#define DMA_LISR_DMEIF1_Msk      (0x1UL << DMA_LISR_DMEIF1_Pos)                /*!< 0x00000100 */
+#define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk                           /*!<  Stream 1 direct mode error interrupt flag */
+#define DMA_LISR_FEIF1_Pos       (6U)
+#define DMA_LISR_FEIF1_Msk       (0x1UL << DMA_LISR_FEIF1_Pos)                 /*!< 0x00000040 */
+#define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk                            /*!<  Stream 1 FIFO error interrupt flag */
+#define DMA_LISR_TCIF0_Pos       (5U)
+#define DMA_LISR_TCIF0_Msk       (0x1UL << DMA_LISR_TCIF0_Pos)                 /*!< 0x00000020 */
+#define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk                            /*!<  Stream 0 transfer complete interrupt flag */
+#define DMA_LISR_HTIF0_Pos       (4U)
+#define DMA_LISR_HTIF0_Msk       (0x1UL << DMA_LISR_HTIF0_Pos)                 /*!< 0x00000010 */
+#define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk                            /*!<  Stream 0 half transfer interrupt flag */
+#define DMA_LISR_TEIF0_Pos       (3U)
+#define DMA_LISR_TEIF0_Msk       (0x1UL << DMA_LISR_TEIF0_Pos)                 /*!< 0x00000008 */
+#define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk                            /*!<  Stream 0 transfer error interrupt flag */
+#define DMA_LISR_DMEIF0_Pos      (2U)
+#define DMA_LISR_DMEIF0_Msk      (0x1UL << DMA_LISR_DMEIF0_Pos)                /*!< 0x00000004 */
+#define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk                           /*!<  Stream 0 direct mode error interrupt flag */
+#define DMA_LISR_FEIF0_Pos       (0U)
+#define DMA_LISR_FEIF0_Msk       (0x1UL << DMA_LISR_FEIF0_Pos)                 /*!< 0x00000001 */
+#define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk                            /*!<  Stream 0 FIFO error interrupt flag */
+
+/********************  Bits definition for DMA_HISR register  *****************/
+#define DMA_HISR_TCIF7_Pos       (27U)
+#define DMA_HISR_TCIF7_Msk       (0x1UL << DMA_HISR_TCIF7_Pos)                 /*!< 0x08000000 */
+#define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk                            /*!<  Stream 7 transfer complete interrupt flag */
+#define DMA_HISR_HTIF7_Pos       (26U)
+#define DMA_HISR_HTIF7_Msk       (0x1UL << DMA_HISR_HTIF7_Pos)                 /*!< 0x04000000 */
+#define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk                            /*!<  Stream 7 half transfer interrupt flag */
+#define DMA_HISR_TEIF7_Pos       (25U)
+#define DMA_HISR_TEIF7_Msk       (0x1UL << DMA_HISR_TEIF7_Pos)                 /*!< 0x02000000 */
+#define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk                            /*!<  Stream 7 transfer error interrupt flag */
+#define DMA_HISR_DMEIF7_Pos      (24U)
+#define DMA_HISR_DMEIF7_Msk      (0x1UL << DMA_HISR_DMEIF7_Pos)                /*!< 0x01000000 */
+#define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk                           /*!<  Stream 7 direct mode error interrupt flag */
+#define DMA_HISR_FEIF7_Pos       (22U)
+#define DMA_HISR_FEIF7_Msk       (0x1UL << DMA_HISR_FEIF7_Pos)                 /*!< 0x00400000 */
+#define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk                            /*!<  Stream 7 FIFO error interrupt flag */
+#define DMA_HISR_TCIF6_Pos       (21U)
+#define DMA_HISR_TCIF6_Msk       (0x1UL << DMA_HISR_TCIF6_Pos)                 /*!< 0x00200000 */
+#define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk                            /*!<  Stream 6 transfer complete interrupt flag */
+#define DMA_HISR_HTIF6_Pos       (20U)
+#define DMA_HISR_HTIF6_Msk       (0x1UL << DMA_HISR_HTIF6_Pos)                 /*!< 0x00100000 */
+#define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk                            /*!<  Stream 6 half transfer interrupt flag */
+#define DMA_HISR_TEIF6_Pos       (19U)
+#define DMA_HISR_TEIF6_Msk       (0x1UL << DMA_HISR_TEIF6_Pos)                 /*!< 0x00080000 */
+#define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk                            /*!<  Stream 6 transfer error interrupt flag */
+#define DMA_HISR_DMEIF6_Pos      (18U)
+#define DMA_HISR_DMEIF6_Msk      (0x1UL << DMA_HISR_DMEIF6_Pos)                /*!< 0x00040000 */
+#define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk                           /*!<  Stream 6 direct mode error interrupt flag */
+#define DMA_HISR_FEIF6_Pos       (16U)
+#define DMA_HISR_FEIF6_Msk       (0x1UL << DMA_HISR_FEIF6_Pos)                 /*!< 0x00010000 */
+#define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk                            /*!<  Stream 6 FIFO error interrupt flag */
+#define DMA_HISR_TCIF5_Pos       (11U)
+#define DMA_HISR_TCIF5_Msk       (0x1UL << DMA_HISR_TCIF5_Pos)                 /*!< 0x00000800 */
+#define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk                            /*!<  Stream 5 transfer complete interrupt flag */
+#define DMA_HISR_HTIF5_Pos       (10U)
+#define DMA_HISR_HTIF5_Msk       (0x1UL << DMA_HISR_HTIF5_Pos)                 /*!< 0x00000400 */
+#define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk                            /*!<  Stream 5 half transfer interrupt flag */
+#define DMA_HISR_TEIF5_Pos       (9U)
+#define DMA_HISR_TEIF5_Msk       (0x1UL << DMA_HISR_TEIF5_Pos)                 /*!< 0x00000200 */
+#define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk                            /*!<  Stream 5 transfer error interrupt flag */
+#define DMA_HISR_DMEIF5_Pos      (8U)
+#define DMA_HISR_DMEIF5_Msk      (0x1UL << DMA_HISR_DMEIF5_Pos)                /*!< 0x00000100 */
+#define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk                           /*!<  Stream 5 direct mode error interrupt flag */
+#define DMA_HISR_FEIF5_Pos       (6U)
+#define DMA_HISR_FEIF5_Msk       (0x1UL << DMA_HISR_FEIF5_Pos)                 /*!< 0x00000040 */
+#define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk                            /*!<  Stream 5 FIFO error interrupt flag */
+#define DMA_HISR_TCIF4_Pos       (5U)
+#define DMA_HISR_TCIF4_Msk       (0x1UL << DMA_HISR_TCIF4_Pos)                 /*!< 0x00000020 */
+#define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk                            /*!<  Stream 4 transfer complete interrupt flag */
+#define DMA_HISR_HTIF4_Pos       (4U)
+#define DMA_HISR_HTIF4_Msk       (0x1UL << DMA_HISR_HTIF4_Pos)                 /*!< 0x00000010 */
+#define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk                            /*!<  Stream 4 half transfer interrupt flag */
+#define DMA_HISR_TEIF4_Pos       (3U)
+#define DMA_HISR_TEIF4_Msk       (0x1UL << DMA_HISR_TEIF4_Pos)                 /*!< 0x00000008 */
+#define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk                            /*!<  Stream 4 transfer error interrupt flag */
+#define DMA_HISR_DMEIF4_Pos      (2U)
+#define DMA_HISR_DMEIF4_Msk      (0x1UL << DMA_HISR_DMEIF4_Pos)                /*!< 0x00000004 */
+#define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk                           /*!<  Stream 4 direct mode error interrupt flag */
+#define DMA_HISR_FEIF4_Pos       (0U)
+#define DMA_HISR_FEIF4_Msk       (0x1UL << DMA_HISR_FEIF4_Pos)                 /*!< 0x00000001 */
+#define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk                            /*!<  Stream 4 FIFO error interrupt flag */
+
+/********************  Bits definition for DMA_LIFCR register  ****************/
+#define DMA_LIFCR_CTCIF3_Pos     (27U)
+#define DMA_LIFCR_CTCIF3_Msk     (0x1UL << DMA_LIFCR_CTCIF3_Pos)               /*!< 0x08000000 */
+#define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk                          /*!<  Stream 3 clear transfer complete interrupt flag */
+#define DMA_LIFCR_CHTIF3_Pos     (26U)
+#define DMA_LIFCR_CHTIF3_Msk     (0x1UL << DMA_LIFCR_CHTIF3_Pos)               /*!< 0x04000000 */
+#define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk                          /*!<  Stream 3 clear half transfer interrupt flag */
+#define DMA_LIFCR_CTEIF3_Pos     (25U)
+#define DMA_LIFCR_CTEIF3_Msk     (0x1UL << DMA_LIFCR_CTEIF3_Pos)               /*!< 0x02000000 */
+#define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk                          /*!<  Stream 3 clear transfer error interrupt flag */
+#define DMA_LIFCR_CDMEIF3_Pos    (24U)
+#define DMA_LIFCR_CDMEIF3_Msk    (0x1UL << DMA_LIFCR_CDMEIF3_Pos)              /*!< 0x01000000 */
+#define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk                         /*!<  Stream 3 clear direct mode error interrupt flag */
+#define DMA_LIFCR_CFEIF3_Pos     (22U)
+#define DMA_LIFCR_CFEIF3_Msk     (0x1UL << DMA_LIFCR_CFEIF3_Pos)               /*!< 0x00400000 */
+#define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk                          /*!<  Stream 3 clear FIFO error interrupt flag */
+#define DMA_LIFCR_CTCIF2_Pos     (21U)
+#define DMA_LIFCR_CTCIF2_Msk     (0x1UL << DMA_LIFCR_CTCIF2_Pos)               /*!< 0x00200000 */
+#define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk                          /*!<  Stream 2 clear transfer complete interrupt flag */
+#define DMA_LIFCR_CHTIF2_Pos     (20U)
+#define DMA_LIFCR_CHTIF2_Msk     (0x1UL << DMA_LIFCR_CHTIF2_Pos)               /*!< 0x00100000 */
+#define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk                          /*!<  Stream 2 clear half transfer interrupt flag */
+#define DMA_LIFCR_CTEIF2_Pos     (19U)
+#define DMA_LIFCR_CTEIF2_Msk     (0x1UL << DMA_LIFCR_CTEIF2_Pos)               /*!< 0x00080000 */
+#define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk                          /*!<  Stream 2 clear transfer error interrupt flag */
+#define DMA_LIFCR_CDMEIF2_Pos    (18U)
+#define DMA_LIFCR_CDMEIF2_Msk    (0x1UL << DMA_LIFCR_CDMEIF2_Pos)              /*!< 0x00040000 */
+#define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk                         /*!<  Stream 2 clear direct mode error interrupt flag */
+#define DMA_LIFCR_CFEIF2_Pos     (16U)
+#define DMA_LIFCR_CFEIF2_Msk     (0x1UL << DMA_LIFCR_CFEIF2_Pos)               /*!< 0x00010000 */
+#define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk                          /*!<  Stream 2 clear FIFO error interrupt flag */
+#define DMA_LIFCR_CTCIF1_Pos     (11U)
+#define DMA_LIFCR_CTCIF1_Msk     (0x1UL << DMA_LIFCR_CTCIF1_Pos)               /*!< 0x00000800 */
+#define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk                          /*!<  Stream 1 clear transfer complete interrupt flag */
+#define DMA_LIFCR_CHTIF1_Pos     (10U)
+#define DMA_LIFCR_CHTIF1_Msk     (0x1UL << DMA_LIFCR_CHTIF1_Pos)               /*!< 0x00000400 */
+#define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk                          /*!<  Stream 1 clear half transfer interrupt flag */
+#define DMA_LIFCR_CTEIF1_Pos     (9U)
+#define DMA_LIFCR_CTEIF1_Msk     (0x1UL << DMA_LIFCR_CTEIF1_Pos)               /*!< 0x00000200 */
+#define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk                          /*!<  Stream 1 clear transfer error interrupt flag */
+#define DMA_LIFCR_CDMEIF1_Pos    (8U)
+#define DMA_LIFCR_CDMEIF1_Msk    (0x1UL << DMA_LIFCR_CDMEIF1_Pos)              /*!< 0x00000100 */
+#define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk                         /*!<  Stream 1 clear direct mode error interrupt flag */
+#define DMA_LIFCR_CFEIF1_Pos     (6U)
+#define DMA_LIFCR_CFEIF1_Msk     (0x1UL << DMA_LIFCR_CFEIF1_Pos)               /*!< 0x00000040 */
+#define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk                          /*!<  Stream 1 clear FIFO error interrupt flag */
+#define DMA_LIFCR_CTCIF0_Pos     (5U)
+#define DMA_LIFCR_CTCIF0_Msk     (0x1UL << DMA_LIFCR_CTCIF0_Pos)               /*!< 0x00000020 */
+#define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk                          /*!<  Stream 0 clear transfer complete interrupt flag */
+#define DMA_LIFCR_CHTIF0_Pos     (4U)
+#define DMA_LIFCR_CHTIF0_Msk     (0x1UL << DMA_LIFCR_CHTIF0_Pos)               /*!< 0x00000010 */
+#define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk                          /*!<  Stream 0 clear half transfer interrupt flag */
+#define DMA_LIFCR_CTEIF0_Pos     (3U)
+#define DMA_LIFCR_CTEIF0_Msk     (0x1UL << DMA_LIFCR_CTEIF0_Pos)               /*!< 0x00000008 */
+#define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk                          /*!<  Stream 0 clear transfer error interrupt flag */
+#define DMA_LIFCR_CDMEIF0_Pos    (2U)
+#define DMA_LIFCR_CDMEIF0_Msk    (0x1UL << DMA_LIFCR_CDMEIF0_Pos)              /*!< 0x00000004 */
+#define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk                         /*!<  Stream 0 clear direct mode error interrupt flag */
+#define DMA_LIFCR_CFEIF0_Pos     (0U)
+#define DMA_LIFCR_CFEIF0_Msk     (0x1UL << DMA_LIFCR_CFEIF0_Pos)               /*!< 0x00000001 */
+#define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk                          /*!<  Stream 0 clear FIFO error interrupt flag */
+
+/********************  Bits definition for DMA_HIFCR  register  ****************/
+#define DMA_HIFCR_CTCIF7_Pos     (27U)
+#define DMA_HIFCR_CTCIF7_Msk     (0x1UL << DMA_HIFCR_CTCIF7_Pos)               /*!< 0x08000000 */
+#define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk                          /*!<  Stream 7 clear transfer complete interrupt flag */
+#define DMA_HIFCR_CHTIF7_Pos     (26U)
+#define DMA_HIFCR_CHTIF7_Msk     (0x1UL << DMA_HIFCR_CHTIF7_Pos)               /*!< 0x04000000 */
+#define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk                          /*!<  Stream 7 clear half transfer interrupt flag */
+#define DMA_HIFCR_CTEIF7_Pos     (25U)
+#define DMA_HIFCR_CTEIF7_Msk     (0x1UL << DMA_HIFCR_CTEIF7_Pos)               /*!< 0x02000000 */
+#define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk                          /*!<  Stream 7 clear transfer error interrupt flag */
+#define DMA_HIFCR_CDMEIF7_Pos    (24U)
+#define DMA_HIFCR_CDMEIF7_Msk    (0x1UL << DMA_HIFCR_CDMEIF7_Pos)              /*!< 0x01000000 */
+#define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk                         /*!<  Stream 7 clear direct mode error interrupt flag */
+#define DMA_HIFCR_CFEIF7_Pos     (22U)
+#define DMA_HIFCR_CFEIF7_Msk     (0x1UL << DMA_HIFCR_CFEIF7_Pos)               /*!< 0x00400000 */
+#define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk                          /*!<  Stream 7 clear FIFO error interrupt flag */
+#define DMA_HIFCR_CTCIF6_Pos     (21U)
+#define DMA_HIFCR_CTCIF6_Msk     (0x1UL << DMA_HIFCR_CTCIF6_Pos)               /*!< 0x00200000 */
+#define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk                          /*!<  Stream 6 clear transfer complete interrupt flag */
+#define DMA_HIFCR_CHTIF6_Pos     (20U)
+#define DMA_HIFCR_CHTIF6_Msk     (0x1UL << DMA_HIFCR_CHTIF6_Pos)               /*!< 0x00100000 */
+#define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk                          /*!<  Stream 6 clear half transfer interrupt flag */
+#define DMA_HIFCR_CTEIF6_Pos     (19U)
+#define DMA_HIFCR_CTEIF6_Msk     (0x1UL << DMA_HIFCR_CTEIF6_Pos)               /*!< 0x00080000 */
+#define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk                          /*!<  Stream 6 clear transfer error interrupt flag */
+#define DMA_HIFCR_CDMEIF6_Pos    (18U)
+#define DMA_HIFCR_CDMEIF6_Msk    (0x1UL << DMA_HIFCR_CDMEIF6_Pos)              /*!< 0x00040000 */
+#define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk                         /*!<  Stream 6 clear direct mode error interrupt flag */
+#define DMA_HIFCR_CFEIF6_Pos     (16U)
+#define DMA_HIFCR_CFEIF6_Msk     (0x1UL << DMA_HIFCR_CFEIF6_Pos)               /*!< 0x00010000 */
+#define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk                          /*!<  Stream 6 clear FIFO error interrupt flag */
+#define DMA_HIFCR_CTCIF5_Pos     (11U)
+#define DMA_HIFCR_CTCIF5_Msk     (0x1UL << DMA_HIFCR_CTCIF5_Pos)               /*!< 0x00000800 */
+#define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk                          /*!<  Stream 5 clear transfer complete interrupt flag */
+#define DMA_HIFCR_CHTIF5_Pos     (10U)
+#define DMA_HIFCR_CHTIF5_Msk     (0x1UL << DMA_HIFCR_CHTIF5_Pos)               /*!< 0x00000400 */
+#define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk                          /*!<  Stream 5 clear half transfer interrupt flag */
+#define DMA_HIFCR_CTEIF5_Pos     (9U)
+#define DMA_HIFCR_CTEIF5_Msk     (0x1UL << DMA_HIFCR_CTEIF5_Pos)               /*!< 0x00000200 */
+#define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk                          /*!<  Stream 5 clear transfer error interrupt flag */
+#define DMA_HIFCR_CDMEIF5_Pos    (8U)
+#define DMA_HIFCR_CDMEIF5_Msk    (0x1UL << DMA_HIFCR_CDMEIF5_Pos)              /*!< 0x00000100 */
+#define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk                         /*!<  Stream 5 clear direct mode error interrupt flag */
+#define DMA_HIFCR_CFEIF5_Pos     (6U)
+#define DMA_HIFCR_CFEIF5_Msk     (0x1UL << DMA_HIFCR_CFEIF5_Pos)               /*!< 0x00000040 */
+#define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk                          /*!<  Stream 5 clear FIFO error interrupt flag */
+#define DMA_HIFCR_CTCIF4_Pos     (5U)
+#define DMA_HIFCR_CTCIF4_Msk     (0x1UL << DMA_HIFCR_CTCIF4_Pos)               /*!< 0x00000020 */
+#define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk                          /*!<  Stream 4 clear transfer complete interrupt flag */
+#define DMA_HIFCR_CHTIF4_Pos     (4U)
+#define DMA_HIFCR_CHTIF4_Msk     (0x1UL << DMA_HIFCR_CHTIF4_Pos)               /*!< 0x00000010 */
+#define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk                          /*!<  Stream 4 clear half transfer interrupt flag */
+#define DMA_HIFCR_CTEIF4_Pos     (3U)
+#define DMA_HIFCR_CTEIF4_Msk     (0x1UL << DMA_HIFCR_CTEIF4_Pos)               /*!< 0x00000008 */
+#define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk                          /*!<  Stream 4 clear transfer error interrupt flag */
+#define DMA_HIFCR_CDMEIF4_Pos    (2U)
+#define DMA_HIFCR_CDMEIF4_Msk    (0x1UL << DMA_HIFCR_CDMEIF4_Pos)              /*!< 0x00000004 */
+#define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk                         /*!<  Stream 4 clear direct mode error interrupt flag */
+#define DMA_HIFCR_CFEIF4_Pos     (0U)
+#define DMA_HIFCR_CFEIF4_Msk     (0x1UL << DMA_HIFCR_CFEIF4_Pos)               /*!< 0x00000001 */
+#define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk                          /*!<  Stream 4 clear FIFO error interrupt flag */
+
+/******************  Bit definition for DMA_SxPAR register  ********************/
+#define DMA_SxPAR_PA_Pos         (0U)
+#define DMA_SxPAR_PA_Msk         (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)            /*!< 0xFFFFFFFF */
+#define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_SxM0AR register  ********************/
+#define DMA_SxM0AR_M0A_Pos       (0U)
+#define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)          /*!< 0xFFFFFFFF */
+#define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory 0 Address */
+
+/******************  Bit definition for DMA_SxM1AR register  ********************/
+#define DMA_SxM1AR_M1A_Pos       (0U)
+#define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)          /*!< 0xFFFFFFFF */
+#define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory 1 Address */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             DMAMUX Controller                              */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for DMAMUX_CxCR register  **************/
+#define DMAMUX_CxCR_DMAREQ_ID_Pos      (0U)
+#define DMAMUX_CxCR_DMAREQ_ID_Msk      (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)   /*!< 0x000000FF */
+#define DMAMUX_CxCR_DMAREQ_ID          DMAMUX_CxCR_DMAREQ_ID_Msk               /*!<  DMA request identification */
+#define DMAMUX_CxCR_DMAREQ_ID_0        (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000001 */
+#define DMAMUX_CxCR_DMAREQ_ID_1        (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000002 */
+#define DMAMUX_CxCR_DMAREQ_ID_2        (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000004 */
+#define DMAMUX_CxCR_DMAREQ_ID_3        (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000008 */
+#define DMAMUX_CxCR_DMAREQ_ID_4        (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000010 */
+#define DMAMUX_CxCR_DMAREQ_ID_5        (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000020 */
+#define DMAMUX_CxCR_DMAREQ_ID_6        (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000040 */
+#define DMAMUX_CxCR_DMAREQ_ID_7        (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000080 */
+#define DMAMUX_CxCR_SOIE_Pos           (8U)
+#define DMAMUX_CxCR_SOIE_Msk           (0x1UL << DMAMUX_CxCR_SOIE_Pos)         /*!< 0x00000100 */
+#define DMAMUX_CxCR_SOIE               DMAMUX_CxCR_SOIE_Msk                    /*!<  Synchronization overrun interrupt enable */
+#define DMAMUX_CxCR_EGE_Pos            (9U)
+#define DMAMUX_CxCR_EGE_Msk            (0x1UL << DMAMUX_CxCR_EGE_Pos)          /*!< 0x00000200 */
+#define DMAMUX_CxCR_EGE                DMAMUX_CxCR_EGE_Msk                     /*!<  Event generation enable */
+#define DMAMUX_CxCR_SE_Pos             (16U)
+#define DMAMUX_CxCR_SE_Msk             (0x1UL << DMAMUX_CxCR_SE_Pos)           /*!< 0x00010000 */
+#define DMAMUX_CxCR_SE                 DMAMUX_CxCR_SE_Msk                      /*!<  Synchronization enable */
+#define DMAMUX_CxCR_SPOL_Pos           (17U)
+#define DMAMUX_CxCR_SPOL_Msk           (0x3UL << DMAMUX_CxCR_SPOL_Pos)         /*!< 0x00060000 */
+#define DMAMUX_CxCR_SPOL               DMAMUX_CxCR_SPOL_Msk                    /*!<  Synchronization polarity */
+#define DMAMUX_CxCR_SPOL_0             (0x1UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00020000 */
+#define DMAMUX_CxCR_SPOL_1             (0x2UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00040000 */
+#define DMAMUX_CxCR_NBREQ_Pos          (19U)
+#define DMAMUX_CxCR_NBREQ_Msk          (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)       /*!< 0x00F80000 */
+#define DMAMUX_CxCR_NBREQ              DMAMUX_CxCR_NBREQ_Msk                   /*!<  Number of DMA requests minus 1 to forward */
+#define DMAMUX_CxCR_NBREQ_0            (0x01UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00080000 */
+#define DMAMUX_CxCR_NBREQ_1            (0x02UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00100000 */
+#define DMAMUX_CxCR_NBREQ_2            (0x04UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00200000 */
+#define DMAMUX_CxCR_NBREQ_3            (0x08UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00400000 */
+#define DMAMUX_CxCR_NBREQ_4            (0x10UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00800000 */
+#define DMAMUX_CxCR_SYNC_ID_Pos        (24U)
+#define DMAMUX_CxCR_SYNC_ID_Msk        (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)     /*!< 0x1F000000 */
+#define DMAMUX_CxCR_SYNC_ID            DMAMUX_CxCR_SYNC_ID_Msk                 /*!<  Synchronization identification */
+#define DMAMUX_CxCR_SYNC_ID_0          (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x01000000 */
+#define DMAMUX_CxCR_SYNC_ID_1          (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x02000000 */
+#define DMAMUX_CxCR_SYNC_ID_2          (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x04000000 */
+#define DMAMUX_CxCR_SYNC_ID_3          (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x08000000 */
+#define DMAMUX_CxCR_SYNC_ID_4          (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x10000000 */
+
+/********************  Bits definition for DMAMUX_CSR register  **************/
+#define DMAMUX_CSR_SOF0_Pos            (0U)
+#define DMAMUX_CSR_SOF0_Msk            (0x1UL << DMAMUX_CSR_SOF0_Pos)          /*!< 0x00000001 */
+#define DMAMUX_CSR_SOF0                DMAMUX_CSR_SOF0_Msk                     /*!< Channel 0 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF1_Pos            (1U)
+#define DMAMUX_CSR_SOF1_Msk            (0x1UL << DMAMUX_CSR_SOF1_Pos)          /*!< 0x00000002 */
+#define DMAMUX_CSR_SOF1                DMAMUX_CSR_SOF1_Msk                     /*!< Channel 1 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF2_Pos            (2U)
+#define DMAMUX_CSR_SOF2_Msk            (0x1UL << DMAMUX_CSR_SOF2_Pos)          /*!< 0x00000004 */
+#define DMAMUX_CSR_SOF2                DMAMUX_CSR_SOF2_Msk                     /*!< Channel 2 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF3_Pos            (3U)
+#define DMAMUX_CSR_SOF3_Msk            (0x1UL << DMAMUX_CSR_SOF3_Pos)          /*!< 0x00000008 */
+#define DMAMUX_CSR_SOF3                DMAMUX_CSR_SOF3_Msk                     /*!< Channel 3 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF4_Pos            (4U)
+#define DMAMUX_CSR_SOF4_Msk            (0x1UL << DMAMUX_CSR_SOF4_Pos)          /*!< 0x00000010 */
+#define DMAMUX_CSR_SOF4                DMAMUX_CSR_SOF4_Msk                     /*!< Channel 4 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF5_Pos            (5U)
+#define DMAMUX_CSR_SOF5_Msk            (0x1UL << DMAMUX_CSR_SOF5_Pos)          /*!< 0x00000020 */
+#define DMAMUX_CSR_SOF5                DMAMUX_CSR_SOF5_Msk                     /*!< Channel 5 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF6_Pos            (6U)
+#define DMAMUX_CSR_SOF6_Msk            (0x1UL << DMAMUX_CSR_SOF6_Pos)          /*!< 0x00000040 */
+#define DMAMUX_CSR_SOF6                DMAMUX_CSR_SOF6_Msk                     /*!< Channel 6 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF7_Pos            (7U)
+#define DMAMUX_CSR_SOF7_Msk            (0x1UL << DMAMUX_CSR_SOF7_Pos)          /*!< 0x00000080 */
+#define DMAMUX_CSR_SOF7                DMAMUX_CSR_SOF7_Msk                     /*!< Channel 7 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF8_Pos            (8U)
+#define DMAMUX_CSR_SOF8_Msk            (0x1UL << DMAMUX_CSR_SOF8_Pos)          /*!< 0x00000100 */
+#define DMAMUX_CSR_SOF8                DMAMUX_CSR_SOF8_Msk                     /*!< Channel 8 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF9_Pos            (9U)
+#define DMAMUX_CSR_SOF9_Msk            (0x1UL << DMAMUX_CSR_SOF9_Pos)          /*!< 0x00000200 */
+#define DMAMUX_CSR_SOF9                DMAMUX_CSR_SOF9_Msk                     /*!< Channel 9 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF10_Pos           (10U)
+#define DMAMUX_CSR_SOF10_Msk           (0x1UL << DMAMUX_CSR_SOF10_Pos)         /*!< 0x00000400 */
+#define DMAMUX_CSR_SOF10               DMAMUX_CSR_SOF10_Msk                    /*!< Channel 10 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF11_Pos           (11U)
+#define DMAMUX_CSR_SOF11_Msk           (0x1UL << DMAMUX_CSR_SOF11_Pos)         /*!< 0x00000800 */
+#define DMAMUX_CSR_SOF11               DMAMUX_CSR_SOF11_Msk                    /*!< Channel 11 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF12_Pos           (12U)
+#define DMAMUX_CSR_SOF12_Msk           (0x1UL << DMAMUX_CSR_SOF12_Pos)         /*!< 0x00001000 */
+#define DMAMUX_CSR_SOF12               DMAMUX_CSR_SOF12_Msk                    /*!< Channel 12 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF13_Pos           (13U)
+#define DMAMUX_CSR_SOF13_Msk           (0x1UL << DMAMUX_CSR_SOF13_Pos)         /*!< 0x00002000 */
+#define DMAMUX_CSR_SOF13               DMAMUX_CSR_SOF13_Msk                    /*!< Channel 13 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF14_Pos           (14U)
+#define DMAMUX_CSR_SOF14_Msk           (0x1UL << DMAMUX_CSR_SOF14_Pos)         /*!< 0x00004000 */
+#define DMAMUX_CSR_SOF14               DMAMUX_CSR_SOF14_Msk                    /*!< Channel 14 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF15_Pos           (15U)
+#define DMAMUX_CSR_SOF15_Msk           (0x1UL << DMAMUX_CSR_SOF15_Pos)         /*!< 0x00008000 */
+#define DMAMUX_CSR_SOF15               DMAMUX_CSR_SOF15_Msk                    /*!< Channel 15 Synchronization overrun event flag */
+
+/********************  Bits definition for DMAMUX_CFR register  **************/
+#define DMAMUX_CFR_CSOF0_Pos           (0U)
+#define DMAMUX_CFR_CSOF0_Msk           (0x1UL << DMAMUX_CFR_CSOF0_Pos)         /*!< 0x00000001 */
+#define DMAMUX_CFR_CSOF0               DMAMUX_CFR_CSOF0_Msk                    /*!< Channel 0 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF1_Pos           (1U)
+#define DMAMUX_CFR_CSOF1_Msk           (0x1UL << DMAMUX_CFR_CSOF1_Pos)         /*!< 0x00000002 */
+#define DMAMUX_CFR_CSOF1               DMAMUX_CFR_CSOF1_Msk                    /*!< Channel 1 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF2_Pos           (2U)
+#define DMAMUX_CFR_CSOF2_Msk           (0x1UL << DMAMUX_CFR_CSOF2_Pos)         /*!< 0x00000004 */
+#define DMAMUX_CFR_CSOF2               DMAMUX_CFR_CSOF2_Msk                    /*!< Channel 2 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF3_Pos           (3U)
+#define DMAMUX_CFR_CSOF3_Msk           (0x1UL << DMAMUX_CFR_CSOF3_Pos)         /*!< 0x00000008 */
+#define DMAMUX_CFR_CSOF3               DMAMUX_CFR_CSOF3_Msk                    /*!< Channel 3 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF4_Pos           (4U)
+#define DMAMUX_CFR_CSOF4_Msk           (0x1UL << DMAMUX_CFR_CSOF4_Pos)         /*!< 0x00000010 */
+#define DMAMUX_CFR_CSOF4               DMAMUX_CFR_CSOF4_Msk                    /*!< Channel 4 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF5_Pos           (5U)
+#define DMAMUX_CFR_CSOF5_Msk           (0x1UL << DMAMUX_CFR_CSOF5_Pos)         /*!< 0x00000020 */
+#define DMAMUX_CFR_CSOF5               DMAMUX_CFR_CSOF5_Msk                    /*!< Channel 5 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF6_Pos           (6U)
+#define DMAMUX_CFR_CSOF6_Msk           (0x1UL << DMAMUX_CFR_CSOF6_Pos)         /*!< 0x00000040 */
+#define DMAMUX_CFR_CSOF6               DMAMUX_CFR_CSOF6_Msk                    /*!< Channel 6 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF7_Pos           (7U)
+#define DMAMUX_CFR_CSOF7_Msk           (0x1UL << DMAMUX_CFR_CSOF7_Pos)         /*!< 0x00000080 */
+#define DMAMUX_CFR_CSOF7               DMAMUX_CFR_CSOF7_Msk                    /*!< Channel 7 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF8_Pos           (8U)
+#define DMAMUX_CFR_CSOF8_Msk           (0x1UL << DMAMUX_CFR_CSOF8_Pos)         /*!< 0x00000100 */
+#define DMAMUX_CFR_CSOF8               DMAMUX_CFR_CSOF8_Msk                    /*!< Channel 8 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF9_Pos           (9U)
+#define DMAMUX_CFR_CSOF9_Msk           (0x1UL << DMAMUX_CFR_CSOF9_Pos)         /*!< 0x00000200 */
+#define DMAMUX_CFR_CSOF9               DMAMUX_CFR_CSOF9_Msk                    /*!< Channel 9 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF10_Pos          (10U)
+#define DMAMUX_CFR_CSOF10_Msk          (0x1UL << DMAMUX_CFR_CSOF10_Pos)        /*!< 0x00000400 */
+#define DMAMUX_CFR_CSOF10              DMAMUX_CFR_CSOF10_Msk                   /*!< Channel 10 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF11_Pos          (11U)
+#define DMAMUX_CFR_CSOF11_Msk          (0x1UL << DMAMUX_CFR_CSOF11_Pos)        /*!< 0x00000800 */
+#define DMAMUX_CFR_CSOF11              DMAMUX_CFR_CSOF11_Msk                   /*!< Channel 11 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF12_Pos          (12U)
+#define DMAMUX_CFR_CSOF12_Msk          (0x1UL << DMAMUX_CFR_CSOF12_Pos)        /*!< 0x00001000 */
+#define DMAMUX_CFR_CSOF12              DMAMUX_CFR_CSOF12_Msk                   /*!< Channel 12 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF13_Pos          (13U)
+#define DMAMUX_CFR_CSOF13_Msk          (0x1UL << DMAMUX_CFR_CSOF13_Pos)        /*!< 0x00002000 */
+#define DMAMUX_CFR_CSOF13              DMAMUX_CFR_CSOF13_Msk                   /*!< Channel 13 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF14_Pos          (14U)
+#define DMAMUX_CFR_CSOF14_Msk          (0x1UL << DMAMUX_CFR_CSOF14_Pos)        /*!< 0x00004000 */
+#define DMAMUX_CFR_CSOF14              DMAMUX_CFR_CSOF14_Msk                   /*!< Channel 14 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF15_Pos          (15U)
+#define DMAMUX_CFR_CSOF15_Msk          (0x1UL << DMAMUX_CFR_CSOF15_Pos)        /*!< 0x00008000 */
+#define DMAMUX_CFR_CSOF15              DMAMUX_CFR_CSOF15_Msk                   /*!< Channel 15 Clear synchronization overrun event flag */
+
+/********************  Bits definition for DMAMUX_RGxCR register  ************/
+#define DMAMUX_RGxCR_SIG_ID_Pos        (0U)
+#define DMAMUX_RGxCR_SIG_ID_Msk        (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)     /*!< 0x0000001F */
+#define DMAMUX_RGxCR_SIG_ID            DMAMUX_RGxCR_SIG_ID_Msk                 /*!< Signal identification */
+#define DMAMUX_RGxCR_SIG_ID_0          (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000001 */
+#define DMAMUX_RGxCR_SIG_ID_1          (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000002 */
+#define DMAMUX_RGxCR_SIG_ID_2          (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000004 */
+#define DMAMUX_RGxCR_SIG_ID_3          (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000008 */
+#define DMAMUX_RGxCR_SIG_ID_4          (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000010 */
+#define DMAMUX_RGxCR_OIE_Pos           (8U)
+#define DMAMUX_RGxCR_OIE_Msk           (0x1UL << DMAMUX_RGxCR_OIE_Pos)         /*!< 0x00000100 */
+#define DMAMUX_RGxCR_OIE               DMAMUX_RGxCR_OIE_Msk                    /*!< Trigger overrun interrupt enable */
+#define DMAMUX_RGxCR_GE_Pos            (16U)
+#define DMAMUX_RGxCR_GE_Msk            (0x1UL << DMAMUX_RGxCR_GE_Pos)          /*!< 0x00010000 */
+#define DMAMUX_RGxCR_GE                DMAMUX_RGxCR_GE_Msk                     /*!< DMA request generator enable */
+#define DMAMUX_RGxCR_GPOL_Pos          (17U)
+#define DMAMUX_RGxCR_GPOL_Msk          (0x3UL << DMAMUX_RGxCR_GPOL_Pos)        /*!< 0x00060000 */
+#define DMAMUX_RGxCR_GPOL              DMAMUX_RGxCR_GPOL_Msk                   /*!< DMA request generator trigger polarity */
+#define DMAMUX_RGxCR_GPOL_0            (0x1UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00020000 */
+#define DMAMUX_RGxCR_GPOL_1            (0x2UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00040000 */
+#define DMAMUX_RGxCR_GNBREQ_Pos        (19U)
+#define DMAMUX_RGxCR_GNBREQ_Msk        (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)     /*!< 0x00F80000 */
+#define DMAMUX_RGxCR_GNBREQ            DMAMUX_RGxCR_GNBREQ_Msk                 /*!< Number of DMA requests to be generated */
+#define DMAMUX_RGxCR_GNBREQ_0          (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00080000 */
+#define DMAMUX_RGxCR_GNBREQ_1          (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00100000 */
+#define DMAMUX_RGxCR_GNBREQ_2          (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00200000 */
+#define DMAMUX_RGxCR_GNBREQ_3          (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00400000 */
+#define DMAMUX_RGxCR_GNBREQ_4          (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00800000 */
+
+/********************  Bits definition for DMAMUX_RGSR register  **************/
+#define DMAMUX_RGSR_OF0_Pos            (0U)
+#define DMAMUX_RGSR_OF0_Msk            (0x1UL << DMAMUX_RGSR_OF0_Pos)          /*!< 0x00000001 */
+#define DMAMUX_RGSR_OF0                DMAMUX_RGSR_OF0_Msk                     /*!< Request generator channel 0 Trigger overrun event flag */
+#define DMAMUX_RGSR_OF1_Pos            (1U)
+#define DMAMUX_RGSR_OF1_Msk            (0x1UL << DMAMUX_RGSR_OF1_Pos)          /*!< 0x00000002 */
+#define DMAMUX_RGSR_OF1                DMAMUX_RGSR_OF1_Msk                     /*!< Request generator channel 1 Trigger overrun event flag */
+#define DMAMUX_RGSR_OF2_Pos            (2U)
+#define DMAMUX_RGSR_OF2_Msk            (0x1UL << DMAMUX_RGSR_OF2_Pos)          /*!< 0x00000004 */
+#define DMAMUX_RGSR_OF2                DMAMUX_RGSR_OF2_Msk                     /*!< Request generator channel 2 Trigger overrun event flag */
+#define DMAMUX_RGSR_OF3_Pos            (3U)
+#define DMAMUX_RGSR_OF3_Msk            (0x1UL << DMAMUX_RGSR_OF3_Pos)          /*!< 0x00000008 */
+#define DMAMUX_RGSR_OF3                DMAMUX_RGSR_OF3_Msk                     /*!< Request generator channel 3 Trigger overrun event flag */
+#define DMAMUX_RGSR_OF4_Pos            (4U)
+#define DMAMUX_RGSR_OF4_Msk            (0x1UL << DMAMUX_RGSR_OF4_Pos)          /*!< 0x00000010 */
+#define DMAMUX_RGSR_OF4                DMAMUX_RGSR_OF4_Msk                     /*!< Request generator channel 4 Trigger overrun event flag */
+#define DMAMUX_RGSR_OF5_Pos            (5U)
+#define DMAMUX_RGSR_OF5_Msk            (0x1UL << DMAMUX_RGSR_OF5_Pos)          /*!< 0x00000020 */
+#define DMAMUX_RGSR_OF5                DMAMUX_RGSR_OF5_Msk                     /*!< Request generator channel 5 Trigger overrun event flag */
+#define DMAMUX_RGSR_OF6_Pos            (6U)
+#define DMAMUX_RGSR_OF6_Msk            (0x1UL << DMAMUX_RGSR_OF6_Pos)          /*!< 0x00000040 */
+#define DMAMUX_RGSR_OF6                DMAMUX_RGSR_OF6_Msk                     /*!< Request generator channel 6 Trigger overrun event flag */
+#define DMAMUX_RGSR_OF7_Pos            (7U)
+#define DMAMUX_RGSR_OF7_Msk            (0x1UL << DMAMUX_RGSR_OF7_Pos)          /*!< 0x00000080 */
+#define DMAMUX_RGSR_OF7                DMAMUX_RGSR_OF7_Msk                     /*!< Request generator channel 7 Trigger overrun event flag */
+
+/********************  Bits definition for DMAMUX_RGCFR register  **************/
+#define DMAMUX_RGCFR_COF0_Pos          (0U)
+#define DMAMUX_RGCFR_COF0_Msk          (0x1UL << DMAMUX_RGCFR_COF0_Pos)        /*!< 0x00000001 */
+#define DMAMUX_RGCFR_COF0              DMAMUX_RGCFR_COF0_Msk                   /*!< Request generator channel 0 Clear trigger overrun event flag */
+#define DMAMUX_RGCFR_COF1_Pos          (1U)
+#define DMAMUX_RGCFR_COF1_Msk          (0x1UL << DMAMUX_RGCFR_COF1_Pos)        /*!< 0x00000002 */
+#define DMAMUX_RGCFR_COF1              DMAMUX_RGCFR_COF1_Msk                   /*!< Request generator channel 1 Clear trigger overrun event flag */
+#define DMAMUX_RGCFR_COF2_Pos          (2U)
+#define DMAMUX_RGCFR_COF2_Msk          (0x1UL << DMAMUX_RGCFR_COF2_Pos)        /*!< 0x00000004 */
+#define DMAMUX_RGCFR_COF2              DMAMUX_RGCFR_COF2_Msk                   /*!< Request generator channel 2 Clear trigger overrun event flag */
+#define DMAMUX_RGCFR_COF3_Pos          (3U)
+#define DMAMUX_RGCFR_COF3_Msk          (0x1UL << DMAMUX_RGCFR_COF3_Pos)        /*!< 0x00000008 */
+#define DMAMUX_RGCFR_COF3              DMAMUX_RGCFR_COF3_Msk                   /*!< Request generator channel 3 Clear trigger overrun event flag */
+#define DMAMUX_RGCFR_COF4_Pos          (4U)
+#define DMAMUX_RGCFR_COF4_Msk          (0x1UL << DMAMUX_RGCFR_COF4_Pos)        /*!< 0x00000010 */
+#define DMAMUX_RGCFR_COF4              DMAMUX_RGCFR_COF4_Msk                   /*!< Request generator channel 4 Clear trigger overrun event flag */
+#define DMAMUX_RGCFR_COF5_Pos          (5U)
+#define DMAMUX_RGCFR_COF5_Msk          (0x1UL << DMAMUX_RGCFR_COF5_Pos)        /*!< 0x00000020 */
+#define DMAMUX_RGCFR_COF5              DMAMUX_RGCFR_COF5_Msk                   /*!< Request generator channel 5 Clear trigger overrun event flag */
+#define DMAMUX_RGCFR_COF6_Pos          (6U)
+#define DMAMUX_RGCFR_COF6_Msk          (0x1UL << DMAMUX_RGCFR_COF6_Pos)        /*!< 0x00000040 */
+#define DMAMUX_RGCFR_COF6              DMAMUX_RGCFR_COF6_Msk                   /*!< Request generator channel 6 Clear trigger overrun event flag */
+#define DMAMUX_RGCFR_COF7_Pos          (7U)
+#define DMAMUX_RGCFR_COF7_Msk          (0x1UL << DMAMUX_RGCFR_COF7_Pos)        /*!< 0x00000080 */
+#define DMAMUX_RGCFR_COF7              DMAMUX_RGCFR_COF7_Msk                   /*!< Request generator channel 7 Clear trigger overrun event flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         AHB Master DMA2D Controller (DMA2D)                */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for DMA2D_CR register  ******************/
+
+#define DMA2D_CR_START_Pos         (0U)
+#define DMA2D_CR_START_Msk         (0x1UL << DMA2D_CR_START_Pos)               /*!< 0x00000001 */
+#define DMA2D_CR_START             DMA2D_CR_START_Msk                          /*!< Start transfer                          */
+#define DMA2D_CR_SUSP_Pos          (1U)
+#define DMA2D_CR_SUSP_Msk          (0x1UL << DMA2D_CR_SUSP_Pos)                /*!< 0x00000002 */
+#define DMA2D_CR_SUSP              DMA2D_CR_SUSP_Msk                           /*!< Suspend transfer                        */
+#define DMA2D_CR_ABORT_Pos         (2U)
+#define DMA2D_CR_ABORT_Msk         (0x1UL << DMA2D_CR_ABORT_Pos)               /*!< 0x00000004 */
+#define DMA2D_CR_ABORT             DMA2D_CR_ABORT_Msk                          /*!< Abort transfer                          */
+#define DMA2D_CR_LOM_Pos           (6U)
+#define DMA2D_CR_LOM_Msk           (0x1UL << DMA2D_CR_LOM_Pos)                 /*!< 0x00000040 */
+#define DMA2D_CR_LOM               DMA2D_CR_LOM_Msk                            /*!< Line Offset Mode                         */
+#define DMA2D_CR_TEIE_Pos          (8U)
+#define DMA2D_CR_TEIE_Msk          (0x1UL << DMA2D_CR_TEIE_Pos)                /*!< 0x00000100 */
+#define DMA2D_CR_TEIE              DMA2D_CR_TEIE_Msk                           /*!< Transfer Error Interrupt Enable         */
+#define DMA2D_CR_TCIE_Pos          (9U)
+#define DMA2D_CR_TCIE_Msk          (0x1UL << DMA2D_CR_TCIE_Pos)                /*!< 0x00000200 */
+#define DMA2D_CR_TCIE              DMA2D_CR_TCIE_Msk                           /*!< Transfer Complete Interrupt Enable      */
+#define DMA2D_CR_TWIE_Pos          (10U)
+#define DMA2D_CR_TWIE_Msk          (0x1UL << DMA2D_CR_TWIE_Pos)                /*!< 0x00000400 */
+#define DMA2D_CR_TWIE              DMA2D_CR_TWIE_Msk                           /*!< Transfer Watermark Interrupt Enable     */
+#define DMA2D_CR_CAEIE_Pos         (11U)
+#define DMA2D_CR_CAEIE_Msk         (0x1UL << DMA2D_CR_CAEIE_Pos)               /*!< 0x00000800 */
+#define DMA2D_CR_CAEIE             DMA2D_CR_CAEIE_Msk                          /*!< CLUT Access Error Interrupt Enable      */
+#define DMA2D_CR_CTCIE_Pos         (12U)
+#define DMA2D_CR_CTCIE_Msk         (0x1UL << DMA2D_CR_CTCIE_Pos)               /*!< 0x00001000 */
+#define DMA2D_CR_CTCIE             DMA2D_CR_CTCIE_Msk                          /*!< CLUT Transfer Complete Interrupt Enable */
+#define DMA2D_CR_CEIE_Pos          (13U)
+#define DMA2D_CR_CEIE_Msk          (0x1UL << DMA2D_CR_CEIE_Pos)                /*!< 0x00002000 */
+#define DMA2D_CR_CEIE              DMA2D_CR_CEIE_Msk                           /*!< Configuration Error Interrupt Enable    */
+#define DMA2D_CR_MODE_Pos          (16U)
+#define DMA2D_CR_MODE_Msk          (0x7UL << DMA2D_CR_MODE_Pos)                /*!< 0x00070000 */
+#define DMA2D_CR_MODE              DMA2D_CR_MODE_Msk                           /*!< DMA2D Mode[2:0]                         */
+#define DMA2D_CR_MODE_0            (0x1UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00010000 */
+#define DMA2D_CR_MODE_1            (0x2UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00020000 */
+#define DMA2D_CR_MODE_2            (0x4UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00040000 */
+
+/********************  Bit definition for DMA2D_ISR register  *****************/
+
+#define DMA2D_ISR_TEIF_Pos         (0U)
+#define DMA2D_ISR_TEIF_Msk         (0x1UL << DMA2D_ISR_TEIF_Pos)               /*!< 0x00000001 */
+#define DMA2D_ISR_TEIF             DMA2D_ISR_TEIF_Msk                          /*!< Transfer Error Interrupt Flag         */
+#define DMA2D_ISR_TCIF_Pos         (1U)
+#define DMA2D_ISR_TCIF_Msk         (0x1UL << DMA2D_ISR_TCIF_Pos)               /*!< 0x00000002 */
+#define DMA2D_ISR_TCIF             DMA2D_ISR_TCIF_Msk                          /*!< Transfer Complete Interrupt Flag      */
+#define DMA2D_ISR_TWIF_Pos         (2U)
+#define DMA2D_ISR_TWIF_Msk         (0x1UL << DMA2D_ISR_TWIF_Pos)               /*!< 0x00000004 */
+#define DMA2D_ISR_TWIF             DMA2D_ISR_TWIF_Msk                          /*!< Transfer Watermark Interrupt Flag     */
+#define DMA2D_ISR_CAEIF_Pos        (3U)
+#define DMA2D_ISR_CAEIF_Msk        (0x1UL << DMA2D_ISR_CAEIF_Pos)              /*!< 0x00000008 */
+#define DMA2D_ISR_CAEIF            DMA2D_ISR_CAEIF_Msk                         /*!< CLUT Access Error Interrupt Flag      */
+#define DMA2D_ISR_CTCIF_Pos        (4U)
+#define DMA2D_ISR_CTCIF_Msk        (0x1UL << DMA2D_ISR_CTCIF_Pos)              /*!< 0x00000010 */
+#define DMA2D_ISR_CTCIF            DMA2D_ISR_CTCIF_Msk                         /*!< CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_CEIF_Pos         (5U)
+#define DMA2D_ISR_CEIF_Msk         (0x1UL << DMA2D_ISR_CEIF_Pos)               /*!< 0x00000020 */
+#define DMA2D_ISR_CEIF             DMA2D_ISR_CEIF_Msk                          /*!< Configuration Error Interrupt Flag    */
+
+/********************  Bit definition for DMA2D_IFCR register  ****************/
+
+#define DMA2D_IFCR_CTEIF_Pos       (0U)
+#define DMA2D_IFCR_CTEIF_Msk       (0x1UL << DMA2D_IFCR_CTEIF_Pos)             /*!< 0x00000001 */
+#define DMA2D_IFCR_CTEIF           DMA2D_IFCR_CTEIF_Msk                        /*!< Clears Transfer Error Interrupt Flag         */
+#define DMA2D_IFCR_CTCIF_Pos       (1U)
+#define DMA2D_IFCR_CTCIF_Msk       (0x1UL << DMA2D_IFCR_CTCIF_Pos)             /*!< 0x00000002 */
+#define DMA2D_IFCR_CTCIF           DMA2D_IFCR_CTCIF_Msk                        /*!< Clears Transfer Complete Interrupt Flag      */
+#define DMA2D_IFCR_CTWIF_Pos       (2U)
+#define DMA2D_IFCR_CTWIF_Msk       (0x1UL << DMA2D_IFCR_CTWIF_Pos)             /*!< 0x00000004 */
+#define DMA2D_IFCR_CTWIF           DMA2D_IFCR_CTWIF_Msk                        /*!< Clears Transfer Watermark Interrupt Flag     */
+#define DMA2D_IFCR_CAECIF_Pos      (3U)
+#define DMA2D_IFCR_CAECIF_Msk      (0x1UL << DMA2D_IFCR_CAECIF_Pos)            /*!< 0x00000008 */
+#define DMA2D_IFCR_CAECIF          DMA2D_IFCR_CAECIF_Msk                       /*!< Clears CLUT Access Error Interrupt Flag      */
+#define DMA2D_IFCR_CCTCIF_Pos      (4U)
+#define DMA2D_IFCR_CCTCIF_Msk      (0x1UL << DMA2D_IFCR_CCTCIF_Pos)            /*!< 0x00000010 */
+#define DMA2D_IFCR_CCTCIF          DMA2D_IFCR_CCTCIF_Msk                       /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CCEIF_Pos       (5U)
+#define DMA2D_IFCR_CCEIF_Msk       (0x1UL << DMA2D_IFCR_CCEIF_Pos)             /*!< 0x00000020 */
+#define DMA2D_IFCR_CCEIF           DMA2D_IFCR_CCEIF_Msk                        /*!< Clears Configuration Error Interrupt Flag    */
+
+/********************  Bit definition for DMA2D_FGMAR register  ***************/
+
+#define DMA2D_FGMAR_MA_Pos         (0U)
+#define DMA2D_FGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)        /*!< 0xFFFFFFFF */
+#define DMA2D_FGMAR_MA             DMA2D_FGMAR_MA_Msk                          /*!< Foreground Memory Address */
+
+/********************  Bit definition for DMA2D_FGOR register  ****************/
+
+#define DMA2D_FGOR_LO_Pos          (0U)
+#define DMA2D_FGOR_LO_Msk          (0xFFFFUL << DMA2D_FGOR_LO_Pos)             /*!< 0x0000FFFF */
+#define DMA2D_FGOR_LO              DMA2D_FGOR_LO_Msk                           /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_BGMAR register  ***************/
+
+#define DMA2D_BGMAR_MA_Pos         (0U)
+#define DMA2D_BGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)        /*!< 0xFFFFFFFF */
+#define DMA2D_BGMAR_MA             DMA2D_BGMAR_MA_Msk                          /*!< Background Memory Address */
+
+/********************  Bit definition for DMA2D_BGOR register  ****************/
+
+#define DMA2D_BGOR_LO_Pos          (0U)
+#define DMA2D_BGOR_LO_Msk          (0xFFFFUL << DMA2D_BGOR_LO_Pos)             /*!< 0x0000FFFF */
+#define DMA2D_BGOR_LO              DMA2D_BGOR_LO_Msk                           /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_FGPFCCR register  *************/
+
+#define DMA2D_FGPFCCR_CM_Pos       (0U)
+#define DMA2D_FGPFCCR_CM_Msk       (0xFUL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x0000000F */
+#define DMA2D_FGPFCCR_CM           DMA2D_FGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */
+#define DMA2D_FGPFCCR_CM_0         (0x1UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000001 */
+#define DMA2D_FGPFCCR_CM_1         (0x2UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000002 */
+#define DMA2D_FGPFCCR_CM_2         (0x4UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000004 */
+#define DMA2D_FGPFCCR_CM_3         (0x8UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000008 */
+#define DMA2D_FGPFCCR_CCM_Pos      (4U)
+#define DMA2D_FGPFCCR_CCM_Msk      (0x1UL << DMA2D_FGPFCCR_CCM_Pos)            /*!< 0x00000010 */
+#define DMA2D_FGPFCCR_CCM          DMA2D_FGPFCCR_CCM_Msk                       /*!< CLUT Color mode */
+#define DMA2D_FGPFCCR_START_Pos    (5U)
+#define DMA2D_FGPFCCR_START_Msk    (0x1UL << DMA2D_FGPFCCR_START_Pos)          /*!< 0x00000020 */
+#define DMA2D_FGPFCCR_START        DMA2D_FGPFCCR_START_Msk                     /*!< Start */
+#define DMA2D_FGPFCCR_CS_Pos       (8U)
+#define DMA2D_FGPFCCR_CS_Msk       (0xFFUL << DMA2D_FGPFCCR_CS_Pos)            /*!< 0x0000FF00 */
+#define DMA2D_FGPFCCR_CS           DMA2D_FGPFCCR_CS_Msk                        /*!< CLUT size */
+#define DMA2D_FGPFCCR_AM_Pos       (16U)
+#define DMA2D_FGPFCCR_AM_Msk       (0x3UL << DMA2D_FGPFCCR_AM_Pos)             /*!< 0x00030000 */
+#define DMA2D_FGPFCCR_AM           DMA2D_FGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */
+#define DMA2D_FGPFCCR_AM_0         (0x1UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00010000 */
+#define DMA2D_FGPFCCR_AM_1         (0x2UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00020000 */
+#define DMA2D_FGPFCCR_CSS_Pos      (18U)
+#define DMA2D_FGPFCCR_CSS_Msk      (0x3UL << DMA2D_FGPFCCR_CSS_Pos)            /*!< 0x000C0000 */
+#define DMA2D_FGPFCCR_CSS          DMA2D_FGPFCCR_CSS_Msk                       /* !< Chroma Sub-Sampling */
+#define DMA2D_FGPFCCR_CSS_0        (0x1UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00040000 */
+#define DMA2D_FGPFCCR_CSS_1        (0x2UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00080000 */
+#define DMA2D_FGPFCCR_AI_Pos       (20U)
+#define DMA2D_FGPFCCR_AI_Msk       (0x1UL << DMA2D_FGPFCCR_AI_Pos)             /*!< 0x00100000 */
+#define DMA2D_FGPFCCR_AI           DMA2D_FGPFCCR_AI_Msk                        /*!< Foreground Input Alpha Inverted */
+#define DMA2D_FGPFCCR_RBS_Pos      (21U)
+#define DMA2D_FGPFCCR_RBS_Msk      (0x1UL << DMA2D_FGPFCCR_RBS_Pos)            /*!< 0x00200000 */
+#define DMA2D_FGPFCCR_RBS          DMA2D_FGPFCCR_RBS_Msk                       /*!< Foreground Input Red Blue Swap */
+#define DMA2D_FGPFCCR_ALPHA_Pos    (24U)
+#define DMA2D_FGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */
+#define DMA2D_FGPFCCR_ALPHA        DMA2D_FGPFCCR_ALPHA_Msk                     /*!< Alpha value */
+
+/********************  Bit definition for DMA2D_FGCOLR register  **************/
+
+#define DMA2D_FGCOLR_BLUE_Pos      (0U)
+#define DMA2D_FGCOLR_BLUE_Msk      (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)           /*!< 0x000000FF */
+#define DMA2D_FGCOLR_BLUE          DMA2D_FGCOLR_BLUE_Msk                       /*!< Foreground Blue Value */
+#define DMA2D_FGCOLR_GREEN_Pos     (8U)
+#define DMA2D_FGCOLR_GREEN_Msk     (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */
+#define DMA2D_FGCOLR_GREEN         DMA2D_FGCOLR_GREEN_Msk                      /*!< Foreground Green Value */
+#define DMA2D_FGCOLR_RED_Pos       (16U)
+#define DMA2D_FGCOLR_RED_Msk       (0xFFUL << DMA2D_FGCOLR_RED_Pos)            /*!< 0x00FF0000 */
+#define DMA2D_FGCOLR_RED           DMA2D_FGCOLR_RED_Msk                        /*!< Foreground Red Value */
+
+/********************  Bit definition for DMA2D_BGPFCCR register  *************/
+
+#define DMA2D_BGPFCCR_CM_Pos       (0U)
+#define DMA2D_BGPFCCR_CM_Msk       (0xFUL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x0000000F */
+#define DMA2D_BGPFCCR_CM           DMA2D_BGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */
+#define DMA2D_BGPFCCR_CM_0         (0x1UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000001 */
+#define DMA2D_BGPFCCR_CM_1         (0x2UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000002 */
+#define DMA2D_BGPFCCR_CM_2         (0x4UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000004 */
+#define DMA2D_BGPFCCR_CM_3         (0x8UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000008 */
+#define DMA2D_BGPFCCR_CCM_Pos      (4U)
+#define DMA2D_BGPFCCR_CCM_Msk      (0x1UL << DMA2D_BGPFCCR_CCM_Pos)            /*!< 0x00000010 */
+#define DMA2D_BGPFCCR_CCM          DMA2D_BGPFCCR_CCM_Msk                       /*!< CLUT Color mode */
+#define DMA2D_BGPFCCR_START_Pos    (5U)
+#define DMA2D_BGPFCCR_START_Msk    (0x1UL << DMA2D_BGPFCCR_START_Pos)          /*!< 0x00000020 */
+#define DMA2D_BGPFCCR_START        DMA2D_BGPFCCR_START_Msk                     /*!< Start */
+#define DMA2D_BGPFCCR_CS_Pos       (8U)
+#define DMA2D_BGPFCCR_CS_Msk       (0xFFUL << DMA2D_BGPFCCR_CS_Pos)            /*!< 0x0000FF00 */
+#define DMA2D_BGPFCCR_CS           DMA2D_BGPFCCR_CS_Msk                        /*!< CLUT size */
+#define DMA2D_BGPFCCR_AM_Pos       (16U)
+#define DMA2D_BGPFCCR_AM_Msk       (0x3UL << DMA2D_BGPFCCR_AM_Pos)             /*!< 0x00030000 */
+#define DMA2D_BGPFCCR_AM           DMA2D_BGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */
+#define DMA2D_BGPFCCR_AM_0         (0x1UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00010000 */
+#define DMA2D_BGPFCCR_AM_1         (0x2UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00020000 */
+#define DMA2D_BGPFCCR_AI_Pos       (20U)
+#define DMA2D_BGPFCCR_AI_Msk       (0x1UL << DMA2D_BGPFCCR_AI_Pos)             /*!< 0x00100000 */
+#define DMA2D_BGPFCCR_AI           DMA2D_BGPFCCR_AI_Msk                        /*!< background Input Alpha Inverted */
+#define DMA2D_BGPFCCR_RBS_Pos      (21U)
+#define DMA2D_BGPFCCR_RBS_Msk      (0x1UL << DMA2D_BGPFCCR_RBS_Pos)            /*!< 0x00200000 */
+#define DMA2D_BGPFCCR_RBS          DMA2D_BGPFCCR_RBS_Msk                       /*!< Background Input Red Blue Swap */
+#define DMA2D_BGPFCCR_ALPHA_Pos    (24U)
+#define DMA2D_BGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */
+#define DMA2D_BGPFCCR_ALPHA        DMA2D_BGPFCCR_ALPHA_Msk                     /*!< background Input Alpha value */
+
+/********************  Bit definition for DMA2D_BGCOLR register  **************/
+
+#define DMA2D_BGCOLR_BLUE_Pos      (0U)
+#define DMA2D_BGCOLR_BLUE_Msk      (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)           /*!< 0x000000FF */
+#define DMA2D_BGCOLR_BLUE          DMA2D_BGCOLR_BLUE_Msk                       /*!< Background Blue Value */
+#define DMA2D_BGCOLR_GREEN_Pos     (8U)
+#define DMA2D_BGCOLR_GREEN_Msk     (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */
+#define DMA2D_BGCOLR_GREEN         DMA2D_BGCOLR_GREEN_Msk                      /*!< Background Green Value */
+#define DMA2D_BGCOLR_RED_Pos       (16U)
+#define DMA2D_BGCOLR_RED_Msk       (0xFFUL << DMA2D_BGCOLR_RED_Pos)            /*!< 0x00FF0000 */
+#define DMA2D_BGCOLR_RED           DMA2D_BGCOLR_RED_Msk                        /*!< Background Red Value */
+
+/********************  Bit definition for DMA2D_FGCMAR register  **************/
+
+#define DMA2D_FGCMAR_MA_Pos        (0U)
+#define DMA2D_FGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */
+#define DMA2D_FGCMAR_MA            DMA2D_FGCMAR_MA_Msk                         /*!< Foreground CLUT Memory Address */
+
+/********************  Bit definition for DMA2D_BGCMAR register  **************/
+
+#define DMA2D_BGCMAR_MA_Pos        (0U)
+#define DMA2D_BGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */
+#define DMA2D_BGCMAR_MA            DMA2D_BGCMAR_MA_Msk                         /*!< Background CLUT Memory Address */
+
+/********************  Bit definition for DMA2D_OPFCCR register  **************/
+
+#define DMA2D_OPFCCR_CM_Pos        (0U)
+#define DMA2D_OPFCCR_CM_Msk        (0x7UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000007 */
+#define DMA2D_OPFCCR_CM            DMA2D_OPFCCR_CM_Msk                         /*!< Output Color mode CM[2:0] */
+#define DMA2D_OPFCCR_CM_0          (0x1UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000001 */
+#define DMA2D_OPFCCR_CM_1          (0x2UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000002 */
+#define DMA2D_OPFCCR_CM_2          (0x4UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000004 */
+#define DMA2D_OPFCCR_SB_Pos        (8U)
+#define DMA2D_OPFCCR_SB_Msk        (0x1UL << DMA2D_OPFCCR_SB_Pos)              /*!< 0x00000100 */
+#define DMA2D_OPFCCR_SB            DMA2D_OPFCCR_SB_Msk                         /*!< Swap Bytes */
+#define DMA2D_OPFCCR_AI_Pos        (20U)
+#define DMA2D_OPFCCR_AI_Msk        (0x1UL << DMA2D_OPFCCR_AI_Pos)              /*!< 0x00100000 */
+#define DMA2D_OPFCCR_AI            DMA2D_OPFCCR_AI_Msk                         /*!< Output Alpha Inverted */
+#define DMA2D_OPFCCR_RBS_Pos       (21U)
+#define DMA2D_OPFCCR_RBS_Msk       (0x1UL << DMA2D_OPFCCR_RBS_Pos)             /*!< 0x00200000 */
+#define DMA2D_OPFCCR_RBS           DMA2D_OPFCCR_RBS_Msk                        /*!< Output Red Blue Swap */
+
+/********************  Bit definition for DMA2D_OCOLR register  ***************/
+
+/*!<Mode_ARGB8888/RGB888 */
+
+#define DMA2D_OCOLR_BLUE_1_Pos     (0U)
+#define DMA2D_OCOLR_BLUE_1_Msk     (0xFFUL <<DMA2D_OCOLR_BLUE_1_Pos)            /*0x000000FFU*/
+#define DMA2D_OCOLR_BLUE_1         DMA2D_OCOLR_BLUE_1_Msk                      /*!< Output BLUE Value */
+#define DMA2D_OCOLR_GREEN_1_Pos    (8U)
+#define DMA2D_OCOLR_GREEN_1_Msk    (0xFFUL<<DMA2D_OCOLR_GREEN_1_Pos)            /*0x0000FF00U)*/
+#define DMA2D_OCOLR_GREEN_1        DMA2D_OCOLR_GREEN_1_Msk                     /*!< Output GREEN Value  */
+#define DMA2D_OCOLR_RED_1_Pos      (16U)
+#define DMA2D_OCOLR_RED_1_Msk      (0xFFUL << DMA2D_OCOLR_RED_1_Pos)            /*0x00FF0000U */
+#define DMA2D_OCOLR_RED_1          DMA2D_OCOLR_RED_1_Msk                       /*!< Output Red Value */
+#define DMA2D_OCOLR_ALPHA_1_Pos    (24U)
+#define DMA2D_OCOLR_ALPHA_1_Msk    (0xFFUL << DMA2D_OCOLR_ALPHA_1_Pos)          /*0xFF000000U*/
+#define DMA2D_OCOLR_ALPHA_1        DMA2D_OCOLR_ALPHA_1_Msk                     /*!< Output Alpha Channel Value */
+
+/*!<Mode_RGB565 */
+#define DMA2D_OCOLR_BLUE_2_Pos     (0U)
+#define DMA2D_OCOLR_BLUE_2_Msk     (0x1FUL <<DMA2D_OCOLR_BLUE_2_Pos)            /*0x0000001FU*/
+#define DMA2D_OCOLR_BLUE_2         DMA2D_OCOLR_BLUE_2_Msk                      /*!< Output BLUE Value */
+#define DMA2D_OCOLR_GREEN_2_Pos    (5U)
+#define DMA2D_OCOLR_GREEN_2_Msk    (0x7EUL << DMA2D_OCOLR_GREEN_2_Pos)          /* 0x000007E0U */
+#define DMA2D_OCOLR_GREEN_2        DMA2D_OCOLR_GREEN_2_Msk                     /*!< Output GREEN Value  */
+#define DMA2D_OCOLR_RED_2_Pos      (11U)
+#define DMA2D_OCOLR_RED_2_Msk      (0xF8UL<<DMA2D_OCOLR_RED_2_Pos)              /*0x0000F800U*/
+#define DMA2D_OCOLR_RED_2          DMA2D_OCOLR_RED_2_Msk                       /*!< Output Red Value */
+
+/*!<Mode_ARGB1555 */
+#define DMA2D_OCOLR_BLUE_3_Pos     (0U)
+#define DMA2D_OCOLR_BLUE_3_Msk     (0x1FUL << DMA2D_OCOLR_BLUE_3_Pos)           /*0x0000001FU*/
+#define DMA2D_OCOLR_BLUE_3         DMA2D_OCOLR_BLUE_3_Msk                      /*!< Output BLUE Value */
+#define DMA2D_OCOLR_GREEN_3_Pos    (5U)
+#define DMA2D_OCOLR_GREEN_3_Msk    (0x3EUL << DMA2D_OCOLR_GREEN_3_Pos)          /*0x000003E0U*/
+#define DMA2D_OCOLR_GREEN_3        DMA2D_OCOLR_GREEN_3_Msk                     /*!< Output GREEN Value  */
+#define DMA2D_OCOLR_RED_3_Pos      (10U)
+#define DMA2D_OCOLR_RED_3_Msk      (0x7CUL << DMA2D_OCOLR_RED_3_Pos)            /* 0x00007C00U*/
+#define DMA2D_OCOLR_RED_3          DMA2D_OCOLR_RED_3_Msk                       /*!< Output Red Value */
+#define DMA2D_OCOLR_ALPHA_3_Pos    (15U)
+#define DMA2D_OCOLR_ALPHA_3_Msk    (0x1UL << DMA2D_OCOLR_ALPHA_3_Pos)           /*0x00008000U*/
+#define DMA2D_OCOLR_ALPHA_3        DMA2D_OCOLR_ALPHA_3_Msk                     /*!< Output Alpha Channel Value */
+
+/*!<Mode_ARGB4444 */
+#define DMA2D_OCOLR_BLUE_4_Pos     (0U)
+#define DMA2D_OCOLR_BLUE_4_Msk     (0xFUL << DMA2D_OCOLR_BLUE_4_Pos)            /*0x0000000FU*/
+#define DMA2D_OCOLR_BLUE_4         DMA2D_OCOLR_BLUE_4_Msk                      /*!< Output BLUE Value */
+#define DMA2D_OCOLR_GREEN_4_Pos    (4U)
+#define DMA2D_OCOLR_GREEN_4_Msk    (0xFUL << DMA2D_OCOLR_GREEN_4_Pos)           /*0x000000F0U*/
+#define DMA2D_OCOLR_GREEN_4        DMA2D_OCOLR_GREEN_4_Msk                     /*!< Output GREEN Value  */
+#define DMA2D_OCOLR_RED_4_Pos      (8U)
+#define DMA2D_OCOLR_RED_4_Msk      (0xFUL << DMA2D_OCOLR_RED_4_Pos)             /*0x00000F00U*/
+#define DMA2D_OCOLR_RED_4          DMA2D_OCOLR_RED_4_Msk                       /*!< Output Red Value */
+#define DMA2D_OCOLR_ALPHA_4_Pos    (12U)
+#define DMA2D_OCOLR_ALPHA_4_Msk    (0xFUL << DMA2D_OCOLR_ALPHA_4_Pos)            /*0x0000F000U*/
+#define DMA2D_OCOLR_ALPHA_4        DMA2D_OCOLR_ALPHA_4_Msk                     /*!< Output Alpha Channel Value */
+
+/********************  Bit definition for DMA2D_OMAR register  ****************/
+
+#define DMA2D_OMAR_MA_Pos          (0U)
+#define DMA2D_OMAR_MA_Msk          (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)         /*!< 0xFFFFFFFF */
+#define DMA2D_OMAR_MA              DMA2D_OMAR_MA_Msk                           /*!< Output Memory Address */
+
+/********************  Bit definition for DMA2D_OOR register  *****************/
+
+#define DMA2D_OOR_LO_Pos           (0U)
+#define DMA2D_OOR_LO_Msk           (0xFFFFUL << DMA2D_OOR_LO_Pos)              /*!< 0x0000FFFF */
+#define DMA2D_OOR_LO               DMA2D_OOR_LO_Msk                            /*!< Output Line Offset */
+
+/********************  Bit definition for DMA2D_NLR register  *****************/
+
+#define DMA2D_NLR_NL_Pos           (0U)
+#define DMA2D_NLR_NL_Msk           (0xFFFFUL << DMA2D_NLR_NL_Pos)              /*!< 0x0000FFFF */
+#define DMA2D_NLR_NL               DMA2D_NLR_NL_Msk                            /*!< Number of Lines */
+#define DMA2D_NLR_PL_Pos           (16U)
+#define DMA2D_NLR_PL_Msk           (0x3FFFUL << DMA2D_NLR_PL_Pos)              /*!< 0x3FFF0000 */
+#define DMA2D_NLR_PL               DMA2D_NLR_PL_Msk                            /*!< Pixel per Lines */
+
+/********************  Bit definition for DMA2D_LWR register  *****************/
+
+#define DMA2D_LWR_LW_Pos           (0U)
+#define DMA2D_LWR_LW_Msk           (0xFFFFUL << DMA2D_LWR_LW_Pos)              /*!< 0x0000FFFF */
+#define DMA2D_LWR_LW               DMA2D_LWR_LW_Msk                            /*!< Line Watermark */
+
+/********************  Bit definition for DMA2D_AMTCR register  ***************/
+
+#define DMA2D_AMTCR_EN_Pos         (0U)
+#define DMA2D_AMTCR_EN_Msk         (0x1UL << DMA2D_AMTCR_EN_Pos)               /*!< 0x00000001 */
+#define DMA2D_AMTCR_EN             DMA2D_AMTCR_EN_Msk                          /*!< Enable */
+#define DMA2D_AMTCR_DT_Pos         (8U)
+#define DMA2D_AMTCR_DT_Msk         (0xFFUL << DMA2D_AMTCR_DT_Pos)              /*!< 0x0000FF00 */
+#define DMA2D_AMTCR_DT             DMA2D_AMTCR_DT_Msk                          /*!< Dead Time */
+
+
+/********************  Bit definition for DMA2D_FGCLUT register  **************/
+
+/********************  Bit definition for DMA2D_BGCLUT register  **************/
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                    External Interrupt/Event Controller                     */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for EXTI_RTSR1 register  *******************/
+#define EXTI_RTSR1_TR_Pos          (0U)
+#define EXTI_RTSR1_TR_Msk          (0x3FFFFFUL << EXTI_RTSR1_TR_Pos)           /*!< 0x003FFFFF */
+#define EXTI_RTSR1_TR              EXTI_RTSR1_TR_Msk                           /*!< Rising trigger event configuration bit */
+#define EXTI_RTSR1_TR0_Pos         (0U)
+#define EXTI_RTSR1_TR0_Msk         (0x1UL << EXTI_RTSR1_TR0_Pos)               /*!< 0x00000001 */
+#define EXTI_RTSR1_TR0             EXTI_RTSR1_TR0_Msk                          /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR1_TR1_Pos         (1U)
+#define EXTI_RTSR1_TR1_Msk         (0x1UL << EXTI_RTSR1_TR1_Pos)               /*!< 0x00000002 */
+#define EXTI_RTSR1_TR1             EXTI_RTSR1_TR1_Msk                          /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR1_TR2_Pos         (2U)
+#define EXTI_RTSR1_TR2_Msk         (0x1UL << EXTI_RTSR1_TR2_Pos)               /*!< 0x00000004 */
+#define EXTI_RTSR1_TR2             EXTI_RTSR1_TR2_Msk                          /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR1_TR3_Pos         (3U)
+#define EXTI_RTSR1_TR3_Msk         (0x1UL << EXTI_RTSR1_TR3_Pos)               /*!< 0x00000008 */
+#define EXTI_RTSR1_TR3             EXTI_RTSR1_TR3_Msk                          /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR1_TR4_Pos         (4U)
+#define EXTI_RTSR1_TR4_Msk         (0x1UL << EXTI_RTSR1_TR4_Pos)               /*!< 0x00000010 */
+#define EXTI_RTSR1_TR4             EXTI_RTSR1_TR4_Msk                          /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR1_TR5_Pos         (5U)
+#define EXTI_RTSR1_TR5_Msk         (0x1UL << EXTI_RTSR1_TR5_Pos)               /*!< 0x00000020 */
+#define EXTI_RTSR1_TR5             EXTI_RTSR1_TR5_Msk                          /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR1_TR6_Pos         (6U)
+#define EXTI_RTSR1_TR6_Msk         (0x1UL << EXTI_RTSR1_TR6_Pos)               /*!< 0x00000040 */
+#define EXTI_RTSR1_TR6             EXTI_RTSR1_TR6_Msk                          /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR1_TR7_Pos         (7U)
+#define EXTI_RTSR1_TR7_Msk         (0x1UL << EXTI_RTSR1_TR7_Pos)               /*!< 0x00000080 */
+#define EXTI_RTSR1_TR7             EXTI_RTSR1_TR7_Msk                          /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR1_TR8_Pos         (8U)
+#define EXTI_RTSR1_TR8_Msk         (0x1UL << EXTI_RTSR1_TR8_Pos)               /*!< 0x00000100 */
+#define EXTI_RTSR1_TR8             EXTI_RTSR1_TR8_Msk                          /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR1_TR9_Pos         (9U)
+#define EXTI_RTSR1_TR9_Msk         (0x1UL << EXTI_RTSR1_TR9_Pos)               /*!< 0x00000200 */
+#define EXTI_RTSR1_TR9             EXTI_RTSR1_TR9_Msk                          /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR1_TR10_Pos        (10U)
+#define EXTI_RTSR1_TR10_Msk        (0x1UL << EXTI_RTSR1_TR10_Pos)              /*!< 0x00000400 */
+#define EXTI_RTSR1_TR10            EXTI_RTSR1_TR10_Msk                         /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR1_TR11_Pos        (11U)
+#define EXTI_RTSR1_TR11_Msk        (0x1UL << EXTI_RTSR1_TR11_Pos)              /*!< 0x00000800 */
+#define EXTI_RTSR1_TR11            EXTI_RTSR1_TR11_Msk                         /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR1_TR12_Pos        (12U)
+#define EXTI_RTSR1_TR12_Msk        (0x1UL << EXTI_RTSR1_TR12_Pos)              /*!< 0x00001000 */
+#define EXTI_RTSR1_TR12            EXTI_RTSR1_TR12_Msk                         /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR1_TR13_Pos        (13U)
+#define EXTI_RTSR1_TR13_Msk        (0x1UL << EXTI_RTSR1_TR13_Pos)              /*!< 0x00002000 */
+#define EXTI_RTSR1_TR13            EXTI_RTSR1_TR13_Msk                         /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR1_TR14_Pos        (14U)
+#define EXTI_RTSR1_TR14_Msk        (0x1UL << EXTI_RTSR1_TR14_Pos)              /*!< 0x00004000 */
+#define EXTI_RTSR1_TR14            EXTI_RTSR1_TR14_Msk                         /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR1_TR15_Pos        (15U)
+#define EXTI_RTSR1_TR15_Msk        (0x1UL << EXTI_RTSR1_TR15_Pos)              /*!< 0x00008000 */
+#define EXTI_RTSR1_TR15            EXTI_RTSR1_TR15_Msk                         /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR1_TR16_Pos        (16U)
+#define EXTI_RTSR1_TR16_Msk        (0x1UL << EXTI_RTSR1_TR16_Pos)              /*!< 0x00010000 */
+#define EXTI_RTSR1_TR16            EXTI_RTSR1_TR16_Msk                         /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR1_TR17_Pos        (17U)
+#define EXTI_RTSR1_TR17_Msk        (0x1UL << EXTI_RTSR1_TR17_Pos)              /*!< 0x00020000 */
+#define EXTI_RTSR1_TR17            EXTI_RTSR1_TR17_Msk                         /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR1_TR18_Pos        (18U)
+#define EXTI_RTSR1_TR18_Msk        (0x1UL << EXTI_RTSR1_TR18_Pos)              /*!< 0x00040000 */
+#define EXTI_RTSR1_TR18            EXTI_RTSR1_TR18_Msk                         /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR1_TR19_Pos        (19U)
+#define EXTI_RTSR1_TR19_Msk        (0x1UL << EXTI_RTSR1_TR19_Pos)              /*!< 0x00080000 */
+#define EXTI_RTSR1_TR19            EXTI_RTSR1_TR19_Msk                         /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR1_TR20_Pos        (20U)
+#define EXTI_RTSR1_TR20_Msk        (0x1UL << EXTI_RTSR1_TR20_Pos)              /*!< 0x00100000 */
+#define EXTI_RTSR1_TR20            EXTI_RTSR1_TR20_Msk                         /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR1_TR21_Pos        (21U)
+#define EXTI_RTSR1_TR21_Msk        (0x1UL << EXTI_RTSR1_TR21_Pos)              /*!< 0x00200000 */
+#define EXTI_RTSR1_TR21            EXTI_RTSR1_TR21_Msk                         /*!< Rising trigger event configuration bit of line 21 */
+
+/******************  Bit definition for EXTI_FTSR1 register  *******************/
+#define EXTI_FTSR1_TR_Pos          (0U)
+#define EXTI_FTSR1_TR_Msk          (0x3FFFFFUL << EXTI_FTSR1_TR_Pos)           /*!< 0x003FFFFF */
+#define EXTI_FTSR1_TR              EXTI_FTSR1_TR_Msk                           /*!< Falling trigger event configuration bit */
+#define EXTI_FTSR1_TR0_Pos         (0U)
+#define EXTI_FTSR1_TR0_Msk         (0x1UL << EXTI_FTSR1_TR0_Pos)               /*!< 0x00000001 */
+#define EXTI_FTSR1_TR0             EXTI_FTSR1_TR0_Msk                          /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR1_TR1_Pos         (1U)
+#define EXTI_FTSR1_TR1_Msk         (0x1UL << EXTI_FTSR1_TR1_Pos)               /*!< 0x00000002 */
+#define EXTI_FTSR1_TR1             EXTI_FTSR1_TR1_Msk                          /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR1_TR2_Pos         (2U)
+#define EXTI_FTSR1_TR2_Msk         (0x1UL << EXTI_FTSR1_TR2_Pos)               /*!< 0x00000004 */
+#define EXTI_FTSR1_TR2             EXTI_FTSR1_TR2_Msk                          /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR1_TR3_Pos         (3U)
+#define EXTI_FTSR1_TR3_Msk         (0x1UL << EXTI_FTSR1_TR3_Pos)               /*!< 0x00000008 */
+#define EXTI_FTSR1_TR3             EXTI_FTSR1_TR3_Msk                          /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR1_TR4_Pos         (4U)
+#define EXTI_FTSR1_TR4_Msk         (0x1UL << EXTI_FTSR1_TR4_Pos)               /*!< 0x00000010 */
+#define EXTI_FTSR1_TR4             EXTI_FTSR1_TR4_Msk                          /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR1_TR5_Pos         (5U)
+#define EXTI_FTSR1_TR5_Msk         (0x1UL << EXTI_FTSR1_TR5_Pos)               /*!< 0x00000020 */
+#define EXTI_FTSR1_TR5             EXTI_FTSR1_TR5_Msk                          /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR1_TR6_Pos         (6U)
+#define EXTI_FTSR1_TR6_Msk         (0x1UL << EXTI_FTSR1_TR6_Pos)               /*!< 0x00000040 */
+#define EXTI_FTSR1_TR6             EXTI_FTSR1_TR6_Msk                          /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR1_TR7_Pos         (7U)
+#define EXTI_FTSR1_TR7_Msk         (0x1UL << EXTI_FTSR1_TR7_Pos)               /*!< 0x00000080 */
+#define EXTI_FTSR1_TR7             EXTI_FTSR1_TR7_Msk                          /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR1_TR8_Pos         (8U)
+#define EXTI_FTSR1_TR8_Msk         (0x1UL << EXTI_FTSR1_TR8_Pos)               /*!< 0x00000100 */
+#define EXTI_FTSR1_TR8             EXTI_FTSR1_TR8_Msk                          /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR1_TR9_Pos         (9U)
+#define EXTI_FTSR1_TR9_Msk         (0x1UL << EXTI_FTSR1_TR9_Pos)               /*!< 0x00000200 */
+#define EXTI_FTSR1_TR9             EXTI_FTSR1_TR9_Msk                          /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR1_TR10_Pos        (10U)
+#define EXTI_FTSR1_TR10_Msk        (0x1UL << EXTI_FTSR1_TR10_Pos)              /*!< 0x00000400 */
+#define EXTI_FTSR1_TR10            EXTI_FTSR1_TR10_Msk                         /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR1_TR11_Pos        (11U)
+#define EXTI_FTSR1_TR11_Msk        (0x1UL << EXTI_FTSR1_TR11_Pos)              /*!< 0x00000800 */
+#define EXTI_FTSR1_TR11            EXTI_FTSR1_TR11_Msk                         /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR1_TR12_Pos        (12U)
+#define EXTI_FTSR1_TR12_Msk        (0x1UL << EXTI_FTSR1_TR12_Pos)              /*!< 0x00001000 */
+#define EXTI_FTSR1_TR12            EXTI_FTSR1_TR12_Msk                         /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR1_TR13_Pos        (13U)
+#define EXTI_FTSR1_TR13_Msk        (0x1UL << EXTI_FTSR1_TR13_Pos)              /*!< 0x00002000 */
+#define EXTI_FTSR1_TR13            EXTI_FTSR1_TR13_Msk                         /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR1_TR14_Pos        (14U)
+#define EXTI_FTSR1_TR14_Msk        (0x1UL << EXTI_FTSR1_TR14_Pos)              /*!< 0x00004000 */
+#define EXTI_FTSR1_TR14            EXTI_FTSR1_TR14_Msk                         /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR1_TR15_Pos        (15U)
+#define EXTI_FTSR1_TR15_Msk        (0x1UL << EXTI_FTSR1_TR15_Pos)              /*!< 0x00008000 */
+#define EXTI_FTSR1_TR15            EXTI_FTSR1_TR15_Msk                         /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR1_TR16_Pos        (16U)
+#define EXTI_FTSR1_TR16_Msk        (0x1UL << EXTI_FTSR1_TR16_Pos)              /*!< 0x00010000 */
+#define EXTI_FTSR1_TR16            EXTI_FTSR1_TR16_Msk                         /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR1_TR17_Pos        (17U)
+#define EXTI_FTSR1_TR17_Msk        (0x1UL << EXTI_FTSR1_TR17_Pos)              /*!< 0x00020000 */
+#define EXTI_FTSR1_TR17            EXTI_FTSR1_TR17_Msk                         /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR1_TR18_Pos        (18U)
+#define EXTI_FTSR1_TR18_Msk        (0x1UL << EXTI_FTSR1_TR18_Pos)              /*!< 0x00040000 */
+#define EXTI_FTSR1_TR18            EXTI_FTSR1_TR18_Msk                         /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR1_TR19_Pos        (19U)
+#define EXTI_FTSR1_TR19_Msk        (0x1UL << EXTI_FTSR1_TR19_Pos)              /*!< 0x00080000 */
+#define EXTI_FTSR1_TR19            EXTI_FTSR1_TR19_Msk                         /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR1_TR20_Pos        (20U)
+#define EXTI_FTSR1_TR20_Msk        (0x1UL << EXTI_FTSR1_TR20_Pos)              /*!< 0x00100000 */
+#define EXTI_FTSR1_TR20            EXTI_FTSR1_TR20_Msk                         /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR1_TR21_Pos        (21U)
+#define EXTI_FTSR1_TR21_Msk        (0x1UL << EXTI_FTSR1_TR21_Pos)              /*!< 0x00200000 */
+#define EXTI_FTSR1_TR21            EXTI_FTSR1_TR21_Msk                         /*!< Falling trigger event configuration bit of line 21 */
+
+/******************  Bit definition for EXTI_SWIER1 register  ******************/
+#define EXTI_SWIER1_SWIER0_Pos     (0U)
+#define EXTI_SWIER1_SWIER0_Msk     (0x1UL << EXTI_SWIER1_SWIER0_Pos)           /*!< 0x00000001 */
+#define EXTI_SWIER1_SWIER0         EXTI_SWIER1_SWIER0_Msk                      /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER1_SWIER1_Pos     (1U)
+#define EXTI_SWIER1_SWIER1_Msk     (0x1UL << EXTI_SWIER1_SWIER1_Pos)           /*!< 0x00000002 */
+#define EXTI_SWIER1_SWIER1         EXTI_SWIER1_SWIER1_Msk                      /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER1_SWIER2_Pos     (2U)
+#define EXTI_SWIER1_SWIER2_Msk     (0x1UL << EXTI_SWIER1_SWIER2_Pos)           /*!< 0x00000004 */
+#define EXTI_SWIER1_SWIER2         EXTI_SWIER1_SWIER2_Msk                      /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER1_SWIER3_Pos     (3U)
+#define EXTI_SWIER1_SWIER3_Msk     (0x1UL << EXTI_SWIER1_SWIER3_Pos)           /*!< 0x00000008 */
+#define EXTI_SWIER1_SWIER3         EXTI_SWIER1_SWIER3_Msk                      /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER1_SWIER4_Pos     (4U)
+#define EXTI_SWIER1_SWIER4_Msk     (0x1UL << EXTI_SWIER1_SWIER4_Pos)           /*!< 0x00000010 */
+#define EXTI_SWIER1_SWIER4         EXTI_SWIER1_SWIER4_Msk                      /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER1_SWIER5_Pos     (5U)
+#define EXTI_SWIER1_SWIER5_Msk     (0x1UL << EXTI_SWIER1_SWIER5_Pos)           /*!< 0x00000020 */
+#define EXTI_SWIER1_SWIER5         EXTI_SWIER1_SWIER5_Msk                      /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER1_SWIER6_Pos     (6U)
+#define EXTI_SWIER1_SWIER6_Msk     (0x1UL << EXTI_SWIER1_SWIER6_Pos)           /*!< 0x00000040 */
+#define EXTI_SWIER1_SWIER6         EXTI_SWIER1_SWIER6_Msk                      /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER1_SWIER7_Pos     (7U)
+#define EXTI_SWIER1_SWIER7_Msk     (0x1UL << EXTI_SWIER1_SWIER7_Pos)           /*!< 0x00000080 */
+#define EXTI_SWIER1_SWIER7         EXTI_SWIER1_SWIER7_Msk                      /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER1_SWIER8_Pos     (8U)
+#define EXTI_SWIER1_SWIER8_Msk     (0x1UL << EXTI_SWIER1_SWIER8_Pos)           /*!< 0x00000100 */
+#define EXTI_SWIER1_SWIER8         EXTI_SWIER1_SWIER8_Msk                      /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER1_SWIER9_Pos     (9U)
+#define EXTI_SWIER1_SWIER9_Msk     (0x1UL << EXTI_SWIER1_SWIER9_Pos)           /*!< 0x00000200 */
+#define EXTI_SWIER1_SWIER9         EXTI_SWIER1_SWIER9_Msk                      /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER1_SWIER10_Pos    (10U)
+#define EXTI_SWIER1_SWIER10_Msk    (0x1UL << EXTI_SWIER1_SWIER10_Pos)          /*!< 0x00000400 */
+#define EXTI_SWIER1_SWIER10        EXTI_SWIER1_SWIER10_Msk                     /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER1_SWIER11_Pos    (11U)
+#define EXTI_SWIER1_SWIER11_Msk    (0x1UL << EXTI_SWIER1_SWIER11_Pos)          /*!< 0x00000800 */
+#define EXTI_SWIER1_SWIER11        EXTI_SWIER1_SWIER11_Msk                     /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER1_SWIER12_Pos    (12U)
+#define EXTI_SWIER1_SWIER12_Msk    (0x1UL << EXTI_SWIER1_SWIER12_Pos)          /*!< 0x00001000 */
+#define EXTI_SWIER1_SWIER12        EXTI_SWIER1_SWIER12_Msk                     /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER1_SWIER13_Pos    (13U)
+#define EXTI_SWIER1_SWIER13_Msk    (0x1UL << EXTI_SWIER1_SWIER13_Pos)          /*!< 0x00002000 */
+#define EXTI_SWIER1_SWIER13        EXTI_SWIER1_SWIER13_Msk                     /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER1_SWIER14_Pos    (14U)
+#define EXTI_SWIER1_SWIER14_Msk    (0x1UL << EXTI_SWIER1_SWIER14_Pos)          /*!< 0x00004000 */
+#define EXTI_SWIER1_SWIER14        EXTI_SWIER1_SWIER14_Msk                     /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER1_SWIER15_Pos    (15U)
+#define EXTI_SWIER1_SWIER15_Msk    (0x1UL << EXTI_SWIER1_SWIER15_Pos)          /*!< 0x00008000 */
+#define EXTI_SWIER1_SWIER15        EXTI_SWIER1_SWIER15_Msk                     /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER1_SWIER16_Pos    (16U)
+#define EXTI_SWIER1_SWIER16_Msk    (0x1UL << EXTI_SWIER1_SWIER16_Pos)          /*!< 0x00010000 */
+#define EXTI_SWIER1_SWIER16        EXTI_SWIER1_SWIER16_Msk                     /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER1_SWIER17_Pos    (17U)
+#define EXTI_SWIER1_SWIER17_Msk    (0x1UL << EXTI_SWIER1_SWIER17_Pos)          /*!< 0x00020000 */
+#define EXTI_SWIER1_SWIER17        EXTI_SWIER1_SWIER17_Msk                     /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER1_SWIER18_Pos    (18U)
+#define EXTI_SWIER1_SWIER18_Msk    (0x1UL << EXTI_SWIER1_SWIER18_Pos)          /*!< 0x00040000 */
+#define EXTI_SWIER1_SWIER18        EXTI_SWIER1_SWIER18_Msk                     /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER1_SWIER19_Pos    (19U)
+#define EXTI_SWIER1_SWIER19_Msk    (0x1UL << EXTI_SWIER1_SWIER19_Pos)          /*!< 0x00080000 */
+#define EXTI_SWIER1_SWIER19        EXTI_SWIER1_SWIER19_Msk                     /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER1_SWIER20_Pos    (20U)
+#define EXTI_SWIER1_SWIER20_Msk    (0x1UL << EXTI_SWIER1_SWIER20_Pos)          /*!< 0x00100000 */
+#define EXTI_SWIER1_SWIER20        EXTI_SWIER1_SWIER20_Msk                     /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER1_SWIER21_Pos    (21U)
+#define EXTI_SWIER1_SWIER21_Msk    (0x1UL << EXTI_SWIER1_SWIER21_Pos)          /*!< 0x00200000 */
+#define EXTI_SWIER1_SWIER21        EXTI_SWIER1_SWIER21_Msk                     /*!< Software Interrupt on line 21 */
+
+/******************  Bit definition for EXTI_D3PMR1 register  ******************/
+#define EXTI_D3PMR1_MR0_Pos        (0U)
+#define EXTI_D3PMR1_MR0_Msk        (0x1UL << EXTI_D3PMR1_MR0_Pos)              /*!< 0x00000001 */
+#define EXTI_D3PMR1_MR0            EXTI_D3PMR1_MR0_Msk                         /*!< Pending Mask Event for line 0  */
+#define EXTI_D3PMR1_MR1_Pos        (1U)
+#define EXTI_D3PMR1_MR1_Msk        (0x1UL << EXTI_D3PMR1_MR1_Pos)              /*!< 0x00000002 */
+#define EXTI_D3PMR1_MR1            EXTI_D3PMR1_MR1_Msk                         /*!< Pending Mask Event for line 1  */
+#define EXTI_D3PMR1_MR2_Pos        (2U)
+#define EXTI_D3PMR1_MR2_Msk        (0x1UL << EXTI_D3PMR1_MR2_Pos)              /*!< 0x00000004 */
+#define EXTI_D3PMR1_MR2            EXTI_D3PMR1_MR2_Msk                         /*!< Pending Mask Event for line 2  */
+#define EXTI_D3PMR1_MR3_Pos        (3U)
+#define EXTI_D3PMR1_MR3_Msk        (0x1UL << EXTI_D3PMR1_MR3_Pos)              /*!< 0x00000008 */
+#define EXTI_D3PMR1_MR3            EXTI_D3PMR1_MR3_Msk                         /*!< Pending Mask Event for line 3  */
+#define EXTI_D3PMR1_MR4_Pos        (4U)
+#define EXTI_D3PMR1_MR4_Msk        (0x1UL << EXTI_D3PMR1_MR4_Pos)              /*!< 0x00000010 */
+#define EXTI_D3PMR1_MR4            EXTI_D3PMR1_MR4_Msk                         /*!< Pending Mask Event for line 4  */
+#define EXTI_D3PMR1_MR5_Pos        (5U)
+#define EXTI_D3PMR1_MR5_Msk        (0x1UL << EXTI_D3PMR1_MR5_Pos)              /*!< 0x00000020 */
+#define EXTI_D3PMR1_MR5            EXTI_D3PMR1_MR5_Msk                         /*!< Pending Mask Event for line 5  */
+#define EXTI_D3PMR1_MR6_Pos        (6U)
+#define EXTI_D3PMR1_MR6_Msk        (0x1UL << EXTI_D3PMR1_MR6_Pos)              /*!< 0x00000040 */
+#define EXTI_D3PMR1_MR6            EXTI_D3PMR1_MR6_Msk                         /*!< Pending Mask Event for line 6  */
+#define EXTI_D3PMR1_MR7_Pos        (7U)
+#define EXTI_D3PMR1_MR7_Msk        (0x1UL << EXTI_D3PMR1_MR7_Pos)              /*!< 0x00000080 */
+#define EXTI_D3PMR1_MR7            EXTI_D3PMR1_MR7_Msk                         /*!< Pending Mask Event for line 7  */
+#define EXTI_D3PMR1_MR8_Pos        (8U)
+#define EXTI_D3PMR1_MR8_Msk        (0x1UL << EXTI_D3PMR1_MR8_Pos)              /*!< 0x00000100 */
+#define EXTI_D3PMR1_MR8            EXTI_D3PMR1_MR8_Msk                         /*!< Pending Mask Event for line 8  */
+#define EXTI_D3PMR1_MR9_Pos        (9U)
+#define EXTI_D3PMR1_MR9_Msk        (0x1UL << EXTI_D3PMR1_MR9_Pos)              /*!< 0x00000200 */
+#define EXTI_D3PMR1_MR9            EXTI_D3PMR1_MR9_Msk                         /*!< Pending Mask Event for line 9  */
+#define EXTI_D3PMR1_MR10_Pos       (10U)
+#define EXTI_D3PMR1_MR10_Msk       (0x1UL << EXTI_D3PMR1_MR10_Pos)             /*!< 0x00000400 */
+#define EXTI_D3PMR1_MR10           EXTI_D3PMR1_MR10_Msk                        /*!< Pending Mask Event for line 10 */
+#define EXTI_D3PMR1_MR11_Pos       (11U)
+#define EXTI_D3PMR1_MR11_Msk       (0x1UL << EXTI_D3PMR1_MR11_Pos)             /*!< 0x00000800 */
+#define EXTI_D3PMR1_MR11           EXTI_D3PMR1_MR11_Msk                        /*!< Pending Mask Event for line 11 */
+#define EXTI_D3PMR1_MR12_Pos       (12U)
+#define EXTI_D3PMR1_MR12_Msk       (0x1UL << EXTI_D3PMR1_MR12_Pos)             /*!< 0x00001000 */
+#define EXTI_D3PMR1_MR12           EXTI_D3PMR1_MR12_Msk                        /*!< Pending Mask Event for line 12 */
+#define EXTI_D3PMR1_MR13_Pos       (13U)
+#define EXTI_D3PMR1_MR13_Msk       (0x1UL << EXTI_D3PMR1_MR13_Pos)             /*!< 0x00002000 */
+#define EXTI_D3PMR1_MR13           EXTI_D3PMR1_MR13_Msk                        /*!< Pending Mask Event for line 13 */
+#define EXTI_D3PMR1_MR14_Pos       (14U)
+#define EXTI_D3PMR1_MR14_Msk       (0x1UL << EXTI_D3PMR1_MR14_Pos)             /*!< 0x00004000 */
+#define EXTI_D3PMR1_MR14           EXTI_D3PMR1_MR14_Msk                        /*!< Pending Mask Event for line 14 */
+#define EXTI_D3PMR1_MR15_Pos       (15U)
+#define EXTI_D3PMR1_MR15_Msk       (0x1UL << EXTI_D3PMR1_MR15_Pos)             /*!< 0x00008000 */
+#define EXTI_D3PMR1_MR15           EXTI_D3PMR1_MR15_Msk                        /*!< Pending Mask Event for line 15 */
+#define EXTI_D3PMR1_MR19_Pos       (19U)
+#define EXTI_D3PMR1_MR19_Msk       (0x1UL << EXTI_D3PMR1_MR19_Pos)             /*!< 0x00080000 */
+#define EXTI_D3PMR1_MR19           EXTI_D3PMR1_MR19_Msk                        /*!< Pending Mask Event for line 19 */
+#define EXTI_D3PMR1_MR20_Pos       (20U)
+#define EXTI_D3PMR1_MR20_Msk       (0x1UL << EXTI_D3PMR1_MR20_Pos)             /*!< 0x00100000 */
+#define EXTI_D3PMR1_MR20           EXTI_D3PMR1_MR20_Msk                        /*!< Pending Mask Event for line 20 */
+#define EXTI_D3PMR1_MR21_Pos       (21U)
+#define EXTI_D3PMR1_MR21_Msk       (0x1UL << EXTI_D3PMR1_MR21_Pos)             /*!< 0x00200000 */
+#define EXTI_D3PMR1_MR21           EXTI_D3PMR1_MR21_Msk                        /*!< Pending Mask Event for line 21 */
+#define EXTI_D3PMR1_MR25_Pos       (24U)
+#define EXTI_D3PMR1_MR25_Msk       (0x1UL << EXTI_D3PMR1_MR25_Pos)             /*!< 0x01000000 */
+#define EXTI_D3PMR1_MR25           EXTI_D3PMR1_MR25_Msk                        /*!< Pending Mask Event for line 25 */
+
+/*******************  Bit definition for EXTI_D3PCR1L register  ****************/
+#define EXTI_D3PCR1L_PCS0_Pos       (0U)
+#define EXTI_D3PCR1L_PCS0_Msk       (0x3UL << EXTI_D3PCR1L_PCS0_Pos)           /*!< 0x00000003 */
+#define EXTI_D3PCR1L_PCS0           EXTI_D3PCR1L_PCS0_Msk                      /*!< D3 Pending request clear input signal selection on line 0 */
+#define EXTI_D3PCR1L_PCS1_Pos       (2U)
+#define EXTI_D3PCR1L_PCS1_Msk       (0x3UL << EXTI_D3PCR1L_PCS1_Pos)           /*!< 0x000000C0 */
+#define EXTI_D3PCR1L_PCS1           EXTI_D3PCR1L_PCS1_Msk                      /*!< D3 Pending request clear input signal selection on line 1 */
+#define EXTI_D3PCR1L_PCS2_Pos       (4U)
+#define EXTI_D3PCR1L_PCS2_Msk       (0x3UL << EXTI_D3PCR1L_PCS2_Pos)           /*!< 0x00000030 */
+#define EXTI_D3PCR1L_PCS2           EXTI_D3PCR1L_PCS2_Msk                      /*!< D3 Pending request clear input signal selection on line 2 */
+#define EXTI_D3PCR1L_PCS3_Pos       (6U)
+#define EXTI_D3PCR1L_PCS3_Msk       (0x3UL << EXTI_D3PCR1L_PCS3_Pos)           /*!< 0x000000C0 */
+#define EXTI_D3PCR1L_PCS3           EXTI_D3PCR1L_PCS3_Msk                      /*!< D3 Pending request clear input signal selection on line 3 */
+#define EXTI_D3PCR1L_PCS4_Pos       (8U)
+#define EXTI_D3PCR1L_PCS4_Msk       (0x3UL << EXTI_D3PCR1L_PCS4_Pos)           /*!< 0x00000300 */
+#define EXTI_D3PCR1L_PCS4           EXTI_D3PCR1L_PCS4_Msk                      /*!< D3 Pending request clear input signal selection on line 4 */
+#define EXTI_D3PCR1L_PCS5_Pos       (10U)
+#define EXTI_D3PCR1L_PCS5_Msk       (0x3UL << EXTI_D3PCR1L_PCS5_Pos)           /*!< 0x00000C00 */
+#define EXTI_D3PCR1L_PCS5           EXTI_D3PCR1L_PCS5_Msk                      /*!< D3 Pending request clear input signal selection on line 5 */
+#define EXTI_D3PCR1L_PCS6_Pos       (12U)
+#define EXTI_D3PCR1L_PCS6_Msk       (0x3UL << EXTI_D3PCR1L_PCS6_Pos)           /*!< 0x00003000 */
+#define EXTI_D3PCR1L_PCS6           EXTI_D3PCR1L_PCS6_Msk                      /*!< D3 Pending request clear input signal selection on line 6 */
+#define EXTI_D3PCR1L_PCS7_Pos       (14U)
+#define EXTI_D3PCR1L_PCS7_Msk       (0x3UL << EXTI_D3PCR1L_PCS7_Pos)           /*!< 0x0000C000 */
+#define EXTI_D3PCR1L_PCS7           EXTI_D3PCR1L_PCS7_Msk                      /*!< D3 Pending request clear input signal selection on line 7 */
+#define EXTI_D3PCR1L_PCS8_Pos       (16U)
+#define EXTI_D3PCR1L_PCS8_Msk       (0x3UL << EXTI_D3PCR1L_PCS8_Pos)           /*!< 0x00030000 */
+#define EXTI_D3PCR1L_PCS8           EXTI_D3PCR1L_PCS8_Msk                      /*!< D3 Pending request clear input signal selection on line 8 */
+#define EXTI_D3PCR1L_PCS9_Pos       (18U)
+#define EXTI_D3PCR1L_PCS9_Msk       (0x3UL << EXTI_D3PCR1L_PCS9_Pos)           /*!< 0x000C0000 */
+#define EXTI_D3PCR1L_PCS9           EXTI_D3PCR1L_PCS9_Msk                      /*!< D3 Pending request clear input signal selection on line 9 */
+#define EXTI_D3PCR1L_PCS10_Pos      (20U)
+#define EXTI_D3PCR1L_PCS10_Msk      (0x3UL << EXTI_D3PCR1L_PCS10_Pos)          /*!< 0x00300000 */
+#define EXTI_D3PCR1L_PCS10          EXTI_D3PCR1L_PCS10_Msk                     /*!< D3 Pending request clear input signal selection on line 10*/
+#define EXTI_D3PCR1L_PCS11_Pos      (22U)
+#define EXTI_D3PCR1L_PCS11_Msk      (0x3UL << EXTI_D3PCR1L_PCS11_Pos)          /*!< 0x00C00000 */
+#define EXTI_D3PCR1L_PCS11          EXTI_D3PCR1L_PCS11_Msk                     /*!< D3 Pending request clear input signal selection on line 11*/
+#define EXTI_D3PCR1L_PCS12_Pos      (24U)
+#define EXTI_D3PCR1L_PCS12_Msk      (0x3UL << EXTI_D3PCR1L_PCS12_Pos)          /*!< 0x03000000 */
+#define EXTI_D3PCR1L_PCS12          EXTI_D3PCR1L_PCS12_Msk                     /*!< D3 Pending request clear input signal selection on line 12*/
+#define EXTI_D3PCR1L_PCS13_Pos      (26U)
+#define EXTI_D3PCR1L_PCS13_Msk      (0x3UL << EXTI_D3PCR1L_PCS13_Pos)          /*!< 0x0C000000 */
+#define EXTI_D3PCR1L_PCS13          EXTI_D3PCR1L_PCS13_Msk                     /*!< D3 Pending request clear input signal selection on line 13*/
+#define EXTI_D3PCR1L_PCS14_Pos      (28U)
+#define EXTI_D3PCR1L_PCS14_Msk      (0x3UL << EXTI_D3PCR1L_PCS14_Pos)          /*!< 0x30000000 */
+#define EXTI_D3PCR1L_PCS14          EXTI_D3PCR1L_PCS14_Msk                     /*!< D3 Pending request clear input signal selection on line 14*/
+#define EXTI_D3PCR1L_PCS15_Pos      (30U)
+#define EXTI_D3PCR1L_PCS15_Msk      (0x3UL << EXTI_D3PCR1L_PCS15_Pos)          /*!< 0xC0000000 */
+#define EXTI_D3PCR1L_PCS15          EXTI_D3PCR1L_PCS15_Msk                     /*!< D3 Pending request clear input signal selection on line 15*/
+
+/*******************  Bit definition for EXTI_D3PCR1H register  ****************/
+#define EXTI_D3PCR1H_PCS19_Pos       (6U)
+#define EXTI_D3PCR1H_PCS19_Msk       (0x3UL << EXTI_D3PCR1H_PCS19_Pos)         /*!< 0x000000C0 */
+#define EXTI_D3PCR1H_PCS19           EXTI_D3PCR1H_PCS19_Msk                    /*!< D3 Pending request clear input signal selection on line 19 */
+#define EXTI_D3PCR1H_PCS20_Pos       (8U)
+#define EXTI_D3PCR1H_PCS20_Msk       (0x3UL << EXTI_D3PCR1H_PCS20_Pos)         /*!< 0x00000300 */
+#define EXTI_D3PCR1H_PCS20           EXTI_D3PCR1H_PCS20_Msk                    /*!< D3 Pending request clear input signal selection on line 20 */
+#define EXTI_D3PCR1H_PCS21_Pos       (10U)
+#define EXTI_D3PCR1H_PCS21_Msk       (0x3UL << EXTI_D3PCR1H_PCS21_Pos)         /*!< 0x00000C00 */
+#define EXTI_D3PCR1H_PCS21           EXTI_D3PCR1H_PCS21_Msk                    /*!< D3 Pending request clear input signal selection on line 21 */
+#define EXTI_D3PCR1H_PCS25_Pos       (18U)
+#define EXTI_D3PCR1H_PCS25_Msk       (0x3UL << EXTI_D3PCR1H_PCS25_Pos)         /*!< 0x000C0000 */
+#define EXTI_D3PCR1H_PCS25           EXTI_D3PCR1H_PCS25_Msk                    /*!< D3 Pending request clear input signal selection on line 25 */
+
+/******************  Bit definition for EXTI_RTSR2 register  *******************/
+#define EXTI_RTSR2_TR_Pos          (17U)
+#define EXTI_RTSR2_TR_Msk          (0x5UL << EXTI_RTSR2_TR_Pos)                /*!< 0x000A0000 */
+#define EXTI_RTSR2_TR              EXTI_RTSR2_TR_Msk                           /*!< Rising trigger event configuration bit */
+#define EXTI_RTSR2_TR49_Pos        (17U)
+#define EXTI_RTSR2_TR49_Msk        (0x1UL << EXTI_RTSR2_TR49_Pos)              /*!< 0x00020000 */
+#define EXTI_RTSR2_TR49            EXTI_RTSR2_TR49_Msk                         /*!< Rising trigger event configuration bit of line 49 */
+#define EXTI_RTSR2_TR51_Pos        (19U)
+#define EXTI_RTSR2_TR51_Msk        (0x1UL << EXTI_RTSR2_TR51_Pos)              /*!< 0x00080000 */
+#define EXTI_RTSR2_TR51            EXTI_RTSR2_TR51_Msk                         /*!< Rising trigger event configuration bit of line 51 */
+
+/******************  Bit definition for EXTI_FTSR2 register  *******************/
+#define EXTI_FTSR2_TR_Pos          (17U)
+#define EXTI_FTSR2_TR_Msk          (0x5UL << EXTI_FTSR2_TR_Pos)                /*!< 0x000A0000 */
+#define EXTI_FTSR2_TR              EXTI_FTSR2_TR_Msk                           /*!< Falling trigger event configuration bit */
+#define EXTI_FTSR2_TR49_Pos        (17U)
+#define EXTI_FTSR2_TR49_Msk        (0x1UL << EXTI_FTSR2_TR49_Pos)              /*!< 0x00020000 */
+#define EXTI_FTSR2_TR49            EXTI_FTSR2_TR49_Msk                         /*!< Falling trigger event configuration bit of line 49 */
+#define EXTI_FTSR2_TR51_Pos        (19U)
+#define EXTI_FTSR2_TR51_Msk        (0x1UL << EXTI_FTSR2_TR51_Pos)              /*!< 0x00080000 */
+#define EXTI_FTSR2_TR51            EXTI_FTSR2_TR51_Msk                         /*!< Falling trigger event configuration bit of line 51 */
+
+/******************  Bit definition for EXTI_SWIER2 register  ******************/
+#define EXTI_SWIER2_SWIER49_Pos    (17U)
+#define EXTI_SWIER2_SWIER49_Msk    (0x1UL << EXTI_SWIER2_SWIER49_Pos)          /*!< 0x00020000 */
+#define EXTI_SWIER2_SWIER49        EXTI_SWIER2_SWIER49_Msk                     /*!< Software Interrupt on line 49 */
+#define EXTI_SWIER2_SWIER51_Pos    (19U)
+#define EXTI_SWIER2_SWIER51_Msk    (0x1UL << EXTI_SWIER2_SWIER51_Pos)          /*!< 0x00080000 */
+#define EXTI_SWIER2_SWIER51        EXTI_SWIER2_SWIER51_Msk                     /*!< Software Interrupt on line 51 */
+
+/******************  Bit definition for EXTI_D3PMR2 register  ******************/
+#define EXTI_D3PMR2_MR34_Pos       (2U)
+#define EXTI_D3PMR2_MR34_Msk       (0x1UL << EXTI_D3PMR2_MR34_Pos)             /*!< 0x00000004 */
+#define EXTI_D3PMR2_MR34           EXTI_D3PMR2_MR34_Msk                        /*!< Pending Mask Event for line 34  */
+#define EXTI_D3PMR2_MR35_Pos       (3U)
+#define EXTI_D3PMR2_MR35_Msk       (0x1UL << EXTI_D3PMR2_MR35_Pos)             /*!< 0x00000008 */
+#define EXTI_D3PMR2_MR35           EXTI_D3PMR2_MR35_Msk                        /*!< Pending Mask Event for line 35  */
+#define EXTI_D3PMR2_MR41_Pos       (9U)
+#define EXTI_D3PMR2_MR41_Msk       (0x1UL << EXTI_D3PMR2_MR41_Pos)             /*!< 0x00000200 */
+#define EXTI_D3PMR2_MR41           EXTI_D3PMR2_MR41_Msk                        /*!< Pending Mask Event for line 41  */
+#define EXTI_D3PMR2_MR48_Pos       (16U)
+#define EXTI_D3PMR2_MR48_Msk       (0x1UL << EXTI_D3PMR2_MR48_Pos)             /*!< 0x00010000 */
+#define EXTI_D3PMR2_MR48           EXTI_D3PMR2_MR48_Msk                        /*!< Pending Mask Event for line 48  */
+#define EXTI_D3PMR2_MR49_Pos       (17U)
+#define EXTI_D3PMR2_MR49_Msk       (0x1UL << EXTI_D3PMR2_MR49_Pos)             /*!< 0x00020000 */
+#define EXTI_D3PMR2_MR49           EXTI_D3PMR2_MR49_Msk                        /*!< Pending Mask Event for line 49  */
+#define EXTI_D3PMR2_MR50_Pos       (18U)
+#define EXTI_D3PMR2_MR50_Msk       (0x1UL << EXTI_D3PMR2_MR50_Pos)             /*!< 0x00040000 */
+#define EXTI_D3PMR2_MR50           EXTI_D3PMR2_MR50_Msk                        /*!< Pending Mask Event for line 50  */
+#define EXTI_D3PMR2_MR51_Pos       (19U)
+#define EXTI_D3PMR2_MR51_Msk       (0x1UL << EXTI_D3PMR2_MR51_Pos)             /*!< 0x00080000 */
+#define EXTI_D3PMR2_MR51           EXTI_D3PMR2_MR51_Msk                        /*!< Pending Mask Event for line 51  */
+#define EXTI_D3PMR2_MR52_Pos       (20U)
+#define EXTI_D3PMR2_MR52_Msk       (0x1UL << EXTI_D3PMR2_MR52_Pos)             /*!< 0x00100000 */
+#define EXTI_D3PMR2_MR52           EXTI_D3PMR2_MR52_Msk                        /*!< Pending Mask Event for line 52  */
+#define EXTI_D3PMR2_MR53_Pos       (21U)
+#define EXTI_D3PMR2_MR53_Msk       (0x1UL << EXTI_D3PMR2_MR53_Pos)             /*!< 0x00200000 */
+#define EXTI_D3PMR2_MR53           EXTI_D3PMR2_MR53_Msk                        /*!< Pending Mask Event for line 53  */
+/*******************  Bit definition for EXTI_D3PCR2L register  ****************/
+#define EXTI_D3PCR2L_PCS34_Pos       (4U)
+#define EXTI_D3PCR2L_PCS34_Msk       (0x3UL << EXTI_D3PCR2L_PCS34_Pos)         /*!< 0x00000030 */
+#define EXTI_D3PCR2L_PCS34           EXTI_D3PCR2L_PCS34_Msk                    /*!< D3 Pending request clear input signal selection on line 34 */
+#define EXTI_D3PCR2L_PCS35_Pos       (6U)
+#define EXTI_D3PCR2L_PCS35_Msk       (0x3UL << EXTI_D3PCR2L_PCS35_Pos)         /*!< 0x000000C0 */
+#define EXTI_D3PCR2L_PCS35           EXTI_D3PCR2L_PCS35_Msk                    /*!< D3 Pending request clear input signal selection on line 35 */
+#define EXTI_D3PCR2L_PCS41_Pos       (18U)
+#define EXTI_D3PCR2L_PCS41_Msk       (0x3UL << EXTI_D3PCR2L_PCS41_Pos)         /*!< 0x000C0000 */
+#define EXTI_D3PCR2L_PCS41           EXTI_D3PCR2L_PCS41_Msk                    /*!< D3 Pending request clear input signal selection on line 41 */
+
+
+/*******************  Bit definition for EXTI_D3PCR2H register  ****************/
+#define EXTI_D3PCR2H_PCS48_Pos       (0U)
+#define EXTI_D3PCR2H_PCS48_Msk       (0x3UL << EXTI_D3PCR2H_PCS48_Pos)         /*!< 0x00000003 */
+#define EXTI_D3PCR2H_PCS48           EXTI_D3PCR2H_PCS48_Msk                    /*!< D3 Pending request clear input signal selection on line 48 */
+#define EXTI_D3PCR2H_PCS49_Pos       (2U)
+#define EXTI_D3PCR2H_PCS49_Msk       (0x3UL << EXTI_D3PCR2H_PCS49_Pos)         /*!< 0x0000000C */
+#define EXTI_D3PCR2H_PCS49           EXTI_D3PCR2H_PCS49_Msk                    /*!< D3 Pending request clear input signal selection on line 49 */
+#define EXTI_D3PCR2H_PCS50_Pos       (4U)
+#define EXTI_D3PCR2H_PCS50_Msk       (0x3UL << EXTI_D3PCR2H_PCS50_Pos)         /*!< 0x00000030 */
+#define EXTI_D3PCR2H_PCS50           EXTI_D3PCR2H_PCS50_Msk                    /*!< D3 Pending request clear input signal selection on line 50 */
+#define EXTI_D3PCR2H_PCS51_Pos       (6U)
+#define EXTI_D3PCR2H_PCS51_Msk       (0x3UL << EXTI_D3PCR2H_PCS51_Pos)         /*!< 0x000000C0 */
+#define EXTI_D3PCR2H_PCS51           EXTI_D3PCR2H_PCS51_Msk                    /*!< D3 Pending request clear input signal selection on line 51 */
+#define EXTI_D3PCR2H_PCS52_Pos       (8U)
+#define EXTI_D3PCR2H_PCS52_Msk       (0x3UL << EXTI_D3PCR2H_PCS52_Pos)         /*!< 0x00000300 */
+#define EXTI_D3PCR2H_PCS52           EXTI_D3PCR2H_PCS52_Msk                    /*!< D3 Pending request clear input signal selection on line 52 */
+#define EXTI_D3PCR2H_PCS53_Pos       (10U)
+#define EXTI_D3PCR2H_PCS53_Msk       (0x3UL << EXTI_D3PCR2H_PCS53_Pos)         /*!< 0x00000C00 */
+#define EXTI_D3PCR2H_PCS53           EXTI_D3PCR2H_PCS53_Msk                    /*!< D3 Pending request clear input signal selection on line 53 */
+/******************  Bit definition for EXTI_RTSR3 register  *******************/
+#define EXTI_RTSR3_TR_Pos          (18U)
+#define EXTI_RTSR3_TR_Msk          (0x1DUL << EXTI_RTSR3_TR_Pos)               /*!< 0x00740000 */
+#define EXTI_RTSR3_TR              EXTI_RTSR3_TR_Msk                           /*!< Rising trigger event configuration bit */
+#define EXTI_RTSR3_TR82_Pos        (18U)
+#define EXTI_RTSR3_TR82_Msk        (0x1UL << EXTI_RTSR3_TR82_Pos)              /*!< 0x00040000 */
+#define EXTI_RTSR3_TR82            EXTI_RTSR3_TR82_Msk                         /*!< Rising trigger event configuration bit of line 82 */
+#define EXTI_RTSR3_TR84_Pos        (20U)
+#define EXTI_RTSR3_TR84_Msk        (0x1UL << EXTI_RTSR3_TR84_Pos)              /*!< 0x00100000 */
+#define EXTI_RTSR3_TR84            EXTI_RTSR3_TR84_Msk                         /*!< Rising trigger event configuration bit of line 84 */
+#define EXTI_RTSR3_TR85_Pos        (21U)
+#define EXTI_RTSR3_TR85_Msk        (0x1UL << EXTI_RTSR3_TR85_Pos)              /*!< 0x00200000 */
+#define EXTI_RTSR3_TR85            EXTI_RTSR3_TR85_Msk                         /*!< Rising trigger event configuration bit of line 85 */
+#define EXTI_RTSR3_TR86_Pos        (22U)
+#define EXTI_RTSR3_TR86_Msk        (0x1UL << EXTI_RTSR3_TR86_Pos)              /*!< 0x00400000 */
+#define EXTI_RTSR3_TR86            EXTI_RTSR3_TR86_Msk                         /*!< Rising trigger event configuration bit of line 86 */
+
+/******************  Bit definition for EXTI_FTSR3 register  *******************/
+#define EXTI_FTSR3_TR_Pos          (18U)
+#define EXTI_FTSR3_TR_Msk          (0x1DUL << EXTI_FTSR3_TR_Pos)               /*!< 0x00740000 */
+#define EXTI_FTSR3_TR              EXTI_FTSR3_TR_Msk                           /*!< Falling trigger event configuration bit */
+#define EXTI_FTSR3_TR82_Pos        (18U)
+#define EXTI_FTSR3_TR82_Msk        (0x1UL << EXTI_FTSR3_TR82_Pos)              /*!< 0x00040000 */
+#define EXTI_FTSR3_TR82            EXTI_FTSR3_TR82_Msk                         /*!< Falling trigger event configuration bit of line 82 */
+#define EXTI_FTSR3_TR84_Pos        (20U)
+#define EXTI_FTSR3_TR84_Msk        (0x1UL << EXTI_FTSR3_TR84_Pos)              /*!< 0x00100000 */
+#define EXTI_FTSR3_TR84            EXTI_FTSR3_TR84_Msk                         /*!< Falling trigger event configuration bit of line 84 */
+#define EXTI_FTSR3_TR85_Pos        (21U)
+#define EXTI_FTSR3_TR85_Msk        (0x1UL << EXTI_FTSR3_TR85_Pos)              /*!< 0x00200000 */
+#define EXTI_FTSR3_TR85            EXTI_FTSR3_TR85_Msk                         /*!< Falling trigger event configuration bit of line 85 */
+#define EXTI_FTSR3_TR86_Pos        (22U)
+#define EXTI_FTSR3_TR86_Msk        (0x1UL << EXTI_FTSR3_TR86_Pos)              /*!< 0x00400000 */
+#define EXTI_FTSR3_TR86            EXTI_FTSR3_TR86_Msk                         /*!< Falling trigger event configuration bit of line 86 */
+
+/******************  Bit definition for EXTI_SWIER3 register  ******************/
+#define EXTI_SWIER3_SWI_Pos        (18U)
+#define EXTI_SWIER3_SWI_Msk        (0x1DUL << EXTI_SWIER3_SWI_Pos)             /*!< 0x00740000 */
+#define EXTI_SWIER3_SWI            EXTI_SWIER3_SWI_Msk                         /*!< Software Interrupt event bit */
+#define EXTI_SWIER3_SWIER82_Pos    (18U)
+#define EXTI_SWIER3_SWIER82_Msk    (0x1UL << EXTI_SWIER3_SWIER82_Pos)          /*!< 0x00040000 */
+#define EXTI_SWIER3_SWIER82        EXTI_SWIER3_SWIER82_Msk                     /*!< Software Interrupt on line 82 */
+#define EXTI_SWIER3_SWIER84_Pos    (20U)
+#define EXTI_SWIER3_SWIER84_Msk    (0x1UL << EXTI_SWIER3_SWIER84_Pos)          /*!< 0x00100000 */
+#define EXTI_SWIER3_SWIER84        EXTI_SWIER3_SWIER84_Msk                     /*!< Software Interrupt on line 84 */
+#define EXTI_SWIER3_SWIER85_Pos    (21U)
+#define EXTI_SWIER3_SWIER85_Msk    (0x1UL << EXTI_SWIER3_SWIER85_Pos)          /*!< 0x00200000 */
+#define EXTI_SWIER3_SWIER85        EXTI_SWIER3_SWIER85_Msk                     /*!< Software Interrupt on line 85 */
+#define EXTI_SWIER3_SWIER86_Pos    (22U)
+#define EXTI_SWIER3_SWIER86_Msk    (0x1UL << EXTI_SWIER3_SWIER86_Pos)          /*!< 0x00400000 */
+#define EXTI_SWIER3_SWIER86        EXTI_SWIER3_SWIER86_Msk                     /*!< Software Interrupt on line 86 */
+
+/*******************  Bit definition for EXTI_IMR1 register  *******************/
+#define EXTI_IMR1_IM_Pos           (0U)
+#define EXTI_IMR1_IM_Msk           (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos)          /*!< 0xFFFFFFFF */
+#define EXTI_IMR1_IM               EXTI_IMR1_IM_Msk                            /*!< Interrupt Mask */
+#define EXTI_IMR1_IM0_Pos          (0U)
+#define EXTI_IMR1_IM0_Msk          (0x1UL << EXTI_IMR1_IM0_Pos)                /*!< 0x00000001 */
+#define EXTI_IMR1_IM0              EXTI_IMR1_IM0_Msk                           /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR1_IM1_Pos          (1U)
+#define EXTI_IMR1_IM1_Msk          (0x1UL << EXTI_IMR1_IM1_Pos)                /*!< 0x00000002 */
+#define EXTI_IMR1_IM1              EXTI_IMR1_IM1_Msk                           /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR1_IM2_Pos          (2U)
+#define EXTI_IMR1_IM2_Msk          (0x1UL << EXTI_IMR1_IM2_Pos)                /*!< 0x00000004 */
+#define EXTI_IMR1_IM2              EXTI_IMR1_IM2_Msk                           /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR1_IM3_Pos          (3U)
+#define EXTI_IMR1_IM3_Msk          (0x1UL << EXTI_IMR1_IM3_Pos)                /*!< 0x00000008 */
+#define EXTI_IMR1_IM3              EXTI_IMR1_IM3_Msk                           /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR1_IM4_Pos          (4U)
+#define EXTI_IMR1_IM4_Msk          (0x1UL << EXTI_IMR1_IM4_Pos)                /*!< 0x00000010 */
+#define EXTI_IMR1_IM4              EXTI_IMR1_IM4_Msk                           /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR1_IM5_Pos          (5U)
+#define EXTI_IMR1_IM5_Msk          (0x1UL << EXTI_IMR1_IM5_Pos)                /*!< 0x00000020 */
+#define EXTI_IMR1_IM5              EXTI_IMR1_IM5_Msk                           /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR1_IM6_Pos          (6U)
+#define EXTI_IMR1_IM6_Msk          (0x1UL << EXTI_IMR1_IM6_Pos)                /*!< 0x00000040 */
+#define EXTI_IMR1_IM6              EXTI_IMR1_IM6_Msk                           /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR1_IM7_Pos          (7U)
+#define EXTI_IMR1_IM7_Msk          (0x1UL << EXTI_IMR1_IM7_Pos)                /*!< 0x00000080 */
+#define EXTI_IMR1_IM7              EXTI_IMR1_IM7_Msk                           /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR1_IM8_Pos          (8U)
+#define EXTI_IMR1_IM8_Msk          (0x1UL << EXTI_IMR1_IM8_Pos)                /*!< 0x00000100 */
+#define EXTI_IMR1_IM8              EXTI_IMR1_IM8_Msk                           /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR1_IM9_Pos          (9U)
+#define EXTI_IMR1_IM9_Msk          (0x1UL << EXTI_IMR1_IM9_Pos)                /*!< 0x00000200 */
+#define EXTI_IMR1_IM9              EXTI_IMR1_IM9_Msk                           /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR1_IM10_Pos         (10U)
+#define EXTI_IMR1_IM10_Msk         (0x1UL << EXTI_IMR1_IM10_Pos)               /*!< 0x00000400 */
+#define EXTI_IMR1_IM10             EXTI_IMR1_IM10_Msk                          /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR1_IM11_Pos         (11U)
+#define EXTI_IMR1_IM11_Msk         (0x1UL << EXTI_IMR1_IM11_Pos)               /*!< 0x00000800 */
+#define EXTI_IMR1_IM11             EXTI_IMR1_IM11_Msk                          /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR1_IM12_Pos         (12U)
+#define EXTI_IMR1_IM12_Msk         (0x1UL << EXTI_IMR1_IM12_Pos)               /*!< 0x00001000 */
+#define EXTI_IMR1_IM12             EXTI_IMR1_IM12_Msk                          /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR1_IM13_Pos         (13U)
+#define EXTI_IMR1_IM13_Msk         (0x1UL << EXTI_IMR1_IM13_Pos)               /*!< 0x00002000 */
+#define EXTI_IMR1_IM13             EXTI_IMR1_IM13_Msk                          /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR1_IM14_Pos         (14U)
+#define EXTI_IMR1_IM14_Msk         (0x1UL << EXTI_IMR1_IM14_Pos)               /*!< 0x00004000 */
+#define EXTI_IMR1_IM14             EXTI_IMR1_IM14_Msk                          /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR1_IM15_Pos         (15U)
+#define EXTI_IMR1_IM15_Msk         (0x1UL << EXTI_IMR1_IM15_Pos)               /*!< 0x00008000 */
+#define EXTI_IMR1_IM15             EXTI_IMR1_IM15_Msk                          /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR1_IM16_Pos         (16U)
+#define EXTI_IMR1_IM16_Msk         (0x1UL << EXTI_IMR1_IM16_Pos)               /*!< 0x00010000 */
+#define EXTI_IMR1_IM16             EXTI_IMR1_IM16_Msk                          /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR1_IM17_Pos         (17U)
+#define EXTI_IMR1_IM17_Msk         (0x1UL << EXTI_IMR1_IM17_Pos)               /*!< 0x00020000 */
+#define EXTI_IMR1_IM17             EXTI_IMR1_IM17_Msk                          /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR1_IM18_Pos         (18U)
+#define EXTI_IMR1_IM18_Msk         (0x1UL << EXTI_IMR1_IM18_Pos)               /*!< 0x00040000 */
+#define EXTI_IMR1_IM18             EXTI_IMR1_IM18_Msk                          /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR1_IM19_Pos         (19U)
+#define EXTI_IMR1_IM19_Msk         (0x1UL << EXTI_IMR1_IM19_Pos)               /*!< 0x00080000 */
+#define EXTI_IMR1_IM19             EXTI_IMR1_IM19_Msk                          /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR1_IM20_Pos         (20U)
+#define EXTI_IMR1_IM20_Msk         (0x1UL << EXTI_IMR1_IM20_Pos)               /*!< 0x00100000 */
+#define EXTI_IMR1_IM20             EXTI_IMR1_IM20_Msk                          /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR1_IM21_Pos         (21U)
+#define EXTI_IMR1_IM21_Msk         (0x1UL << EXTI_IMR1_IM21_Pos)               /*!< 0x00200000 */
+#define EXTI_IMR1_IM21             EXTI_IMR1_IM21_Msk                          /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR1_IM22_Pos         (22U)
+#define EXTI_IMR1_IM22_Msk         (0x1UL << EXTI_IMR1_IM22_Pos)               /*!< 0x00400000 */
+#define EXTI_IMR1_IM22             EXTI_IMR1_IM22_Msk                          /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR1_IM23_Pos         (23U)
+#define EXTI_IMR1_IM23_Msk         (0x1UL << EXTI_IMR1_IM23_Pos)               /*!< 0x00800000 */
+#define EXTI_IMR1_IM23             EXTI_IMR1_IM23_Msk                          /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR1_IM24_Pos         (24U)
+#define EXTI_IMR1_IM24_Msk         (0x1UL << EXTI_IMR1_IM24_Pos)               /*!< 0x01000000 */
+#define EXTI_IMR1_IM24             EXTI_IMR1_IM24_Msk                          /*!< Interrupt Mask on line 24 */
+#define EXTI_IMR1_IM25_Pos         (25U)
+#define EXTI_IMR1_IM25_Msk         (0x1UL << EXTI_IMR1_IM25_Pos)               /*!< 0x02000000 */
+#define EXTI_IMR1_IM25             EXTI_IMR1_IM25_Msk                          /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR1_IM26_Pos         (26U)
+#define EXTI_IMR1_IM26_Msk         (0x1UL << EXTI_IMR1_IM26_Pos)               /*!< 0x04000000 */
+#define EXTI_IMR1_IM26             EXTI_IMR1_IM26_Msk                          /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR1_IM27_Pos         (27U)
+#define EXTI_IMR1_IM27_Msk         (0x1UL << EXTI_IMR1_IM27_Pos)               /*!< 0x08000000 */
+#define EXTI_IMR1_IM27             EXTI_IMR1_IM27_Msk                          /*!< Interrupt Mask on line 27 */
+#define EXTI_IMR1_IM28_Pos         (28U)
+#define EXTI_IMR1_IM28_Msk         (0x1UL << EXTI_IMR1_IM28_Pos)               /*!< 0x10000000 */
+#define EXTI_IMR1_IM28             EXTI_IMR1_IM28_Msk                          /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR1_IM29_Pos         (29U)
+#define EXTI_IMR1_IM29_Msk         (0x1UL << EXTI_IMR1_IM29_Pos)               /*!< 0x20000000 */
+#define EXTI_IMR1_IM29             EXTI_IMR1_IM29_Msk                          /*!< Interrupt Mask on line 29 */
+#define EXTI_IMR1_IM30_Pos         (30U)
+#define EXTI_IMR1_IM30_Msk         (0x1UL << EXTI_IMR1_IM30_Pos)               /*!< 0x40000000 */
+#define EXTI_IMR1_IM30             EXTI_IMR1_IM30_Msk                          /*!< Interrupt Mask on line 30 */
+#define EXTI_IMR1_IM31_Pos         (31U)
+#define EXTI_IMR1_IM31_Msk         (0x1UL << EXTI_IMR1_IM31_Pos)               /*!< 0x80000000 */
+#define EXTI_IMR1_IM31             EXTI_IMR1_IM31_Msk                          /*!< Interrupt Mask on line 31 */
+
+/*******************  Bit definition for EXTI_EMR1 register  *******************/
+#define EXTI_EMR1_EM_Pos           (0U)
+#define EXTI_EMR1_EM_Msk           (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos)          /*!< 0xFFFFFFFF */
+#define EXTI_EMR1_EM               EXTI_EMR1_EM_Msk                            /*!< Event Mask */
+#define EXTI_EMR1_EM0_Pos          (0U)
+#define EXTI_EMR1_EM0_Msk          (0x1UL << EXTI_EMR1_EM0_Pos)                /*!< 0x00000001 */
+#define EXTI_EMR1_EM0              EXTI_EMR1_EM0_Msk                           /*!< Event Mask on line 0 */
+#define EXTI_EMR1_EM1_Pos          (1U)
+#define EXTI_EMR1_EM1_Msk          (0x1UL << EXTI_EMR1_EM1_Pos)                /*!< 0x00000002 */
+#define EXTI_EMR1_EM1              EXTI_EMR1_EM1_Msk                           /*!< Event Mask on line 1 */
+#define EXTI_EMR1_EM2_Pos          (2U)
+#define EXTI_EMR1_EM2_Msk          (0x1UL << EXTI_EMR1_EM2_Pos)                /*!< 0x00000004 */
+#define EXTI_EMR1_EM2              EXTI_EMR1_EM2_Msk                           /*!< Event Mask on line 2 */
+#define EXTI_EMR1_EM3_Pos          (3U)
+#define EXTI_EMR1_EM3_Msk          (0x1UL << EXTI_EMR1_EM3_Pos)                /*!< 0x00000008 */
+#define EXTI_EMR1_EM3              EXTI_EMR1_EM3_Msk                           /*!< Event Mask on line 3 */
+#define EXTI_EMR1_EM4_Pos          (4U)
+#define EXTI_EMR1_EM4_Msk          (0x1UL << EXTI_EMR1_EM4_Pos)                /*!< 0x00000010 */
+#define EXTI_EMR1_EM4              EXTI_EMR1_EM4_Msk                           /*!< Event Mask on line 4 */
+#define EXTI_EMR1_EM5_Pos          (5U)
+#define EXTI_EMR1_EM5_Msk          (0x1UL << EXTI_EMR1_EM5_Pos)                /*!< 0x00000020 */
+#define EXTI_EMR1_EM5              EXTI_EMR1_EM5_Msk                           /*!< Event Mask on line 5 */
+#define EXTI_EMR1_EM6_Pos          (6U)
+#define EXTI_EMR1_EM6_Msk          (0x1UL << EXTI_EMR1_EM6_Pos)                /*!< 0x00000040 */
+#define EXTI_EMR1_EM6              EXTI_EMR1_EM6_Msk                           /*!< Event Mask on line 6 */
+#define EXTI_EMR1_EM7_Pos          (7U)
+#define EXTI_EMR1_EM7_Msk          (0x1UL << EXTI_EMR1_EM7_Pos)                /*!< 0x00000080 */
+#define EXTI_EMR1_EM7              EXTI_EMR1_EM7_Msk                           /*!< Event Mask on line 7 */
+#define EXTI_EMR1_EM8_Pos          (8U)
+#define EXTI_EMR1_EM8_Msk          (0x1UL << EXTI_EMR1_EM8_Pos)                /*!< 0x00000100 */
+#define EXTI_EMR1_EM8              EXTI_EMR1_EM8_Msk                           /*!< Event Mask on line 8 */
+#define EXTI_EMR1_EM9_Pos          (9U)
+#define EXTI_EMR1_EM9_Msk          (0x1UL << EXTI_EMR1_EM9_Pos)                /*!< 0x00000200 */
+#define EXTI_EMR1_EM9              EXTI_EMR1_EM9_Msk                           /*!< Event Mask on line 9 */
+#define EXTI_EMR1_EM10_Pos         (10U)
+#define EXTI_EMR1_EM10_Msk         (0x1UL << EXTI_EMR1_EM10_Pos)               /*!< 0x00000400 */
+#define EXTI_EMR1_EM10             EXTI_EMR1_EM10_Msk                          /*!< Event Mask on line 10 */
+#define EXTI_EMR1_EM11_Pos         (11U)
+#define EXTI_EMR1_EM11_Msk         (0x1UL << EXTI_EMR1_EM11_Pos)               /*!< 0x00000800 */
+#define EXTI_EMR1_EM11             EXTI_EMR1_EM11_Msk                          /*!< Event Mask on line 11 */
+#define EXTI_EMR1_EM12_Pos         (12U)
+#define EXTI_EMR1_EM12_Msk         (0x1UL << EXTI_EMR1_EM12_Pos)               /*!< 0x00001000 */
+#define EXTI_EMR1_EM12             EXTI_EMR1_EM12_Msk                          /*!< Event Mask on line 12 */
+#define EXTI_EMR1_EM13_Pos         (13U)
+#define EXTI_EMR1_EM13_Msk         (0x1UL << EXTI_EMR1_EM13_Pos)               /*!< 0x00002000 */
+#define EXTI_EMR1_EM13             EXTI_EMR1_EM13_Msk                          /*!< Event Mask on line 13 */
+#define EXTI_EMR1_EM14_Pos         (14U)
+#define EXTI_EMR1_EM14_Msk         (0x1UL << EXTI_EMR1_EM14_Pos)               /*!< 0x00004000 */
+#define EXTI_EMR1_EM14             EXTI_EMR1_EM14_Msk                          /*!< Event Mask on line 14 */
+#define EXTI_EMR1_EM15_Pos         (15U)
+#define EXTI_EMR1_EM15_Msk         (0x1UL << EXTI_EMR1_EM15_Pos)               /*!< 0x00008000 */
+#define EXTI_EMR1_EM15             EXTI_EMR1_EM15_Msk                          /*!< Event Mask on line 15 */
+#define EXTI_EMR1_EM16_Pos         (16U)
+#define EXTI_EMR1_EM16_Msk         (0x1UL << EXTI_EMR1_EM16_Pos)               /*!< 0x00010000 */
+#define EXTI_EMR1_EM16             EXTI_EMR1_EM16_Msk                          /*!< Event Mask on line 16 */
+#define EXTI_EMR1_EM17_Pos         (17U)
+#define EXTI_EMR1_EM17_Msk         (0x1UL << EXTI_EMR1_EM17_Pos)               /*!< 0x00020000 */
+#define EXTI_EMR1_EM17             EXTI_EMR1_EM17_Msk                          /*!< Event Mask on line 17 */
+#define EXTI_EMR1_EM18_Pos         (18U)
+#define EXTI_EMR1_EM18_Msk         (0x1UL << EXTI_EMR1_EM18_Pos)               /*!< 0x00040000 */
+#define EXTI_EMR1_EM18             EXTI_EMR1_EM18_Msk                          /*!< Event Mask on line 18 */
+#define EXTI_EMR1_EM20_Pos         (20U)
+#define EXTI_EMR1_EM20_Msk         (0x1UL << EXTI_EMR1_EM20_Pos)               /*!< 0x00100000 */
+#define EXTI_EMR1_EM20             EXTI_EMR1_EM20_Msk                          /*!< Event Mask on line 20 */
+#define EXTI_EMR1_EM21_Pos         (21U)
+#define EXTI_EMR1_EM21_Msk         (0x1UL << EXTI_EMR1_EM21_Pos)               /*!< 0x00200000 */
+#define EXTI_EMR1_EM21             EXTI_EMR1_EM21_Msk                          /*!< Event Mask on line 21 */
+#define EXTI_EMR1_EM22_Pos         (22U)
+#define EXTI_EMR1_EM22_Msk         (0x1UL << EXTI_EMR1_EM22_Pos)               /*!< 0x00400000 */
+#define EXTI_EMR1_EM22             EXTI_EMR1_EM22_Msk                          /*!< Event Mask on line 22 */
+#define EXTI_EMR1_EM23_Pos         (23U)
+#define EXTI_EMR1_EM23_Msk         (0x1UL << EXTI_EMR1_EM23_Pos)               /*!< 0x00800000 */
+#define EXTI_EMR1_EM23             EXTI_EMR1_EM23_Msk                          /*!< Event Mask on line 23 */
+#define EXTI_EMR1_EM24_Pos         (24U)
+#define EXTI_EMR1_EM24_Msk         (0x1UL << EXTI_EMR1_EM24_Pos)               /*!< 0x01000000 */
+#define EXTI_EMR1_EM24             EXTI_EMR1_EM24_Msk                          /*!< Event Mask on line 24 */
+#define EXTI_EMR1_EM25_Pos         (25U)
+#define EXTI_EMR1_EM25_Msk         (0x1UL << EXTI_EMR1_EM25_Pos)               /*!< 0x02000000 */
+#define EXTI_EMR1_EM25             EXTI_EMR1_EM25_Msk                          /*!< Event Mask on line 25 */
+#define EXTI_EMR1_EM26_Pos         (26U)
+#define EXTI_EMR1_EM26_Msk         (0x1UL << EXTI_EMR1_EM26_Pos)               /*!< 0x04000000 */
+#define EXTI_EMR1_EM26             EXTI_EMR1_EM26_Msk                          /*!< Event Mask on line 26 */
+#define EXTI_EMR1_EM27_Pos         (27U)
+#define EXTI_EMR1_EM27_Msk         (0x1UL << EXTI_EMR1_EM27_Pos)               /*!< 0x08000000 */
+#define EXTI_EMR1_EM27             EXTI_EMR1_EM27_Msk                          /*!< Event Mask on line 27 */
+#define EXTI_EMR1_EM28_Pos         (28U)
+#define EXTI_EMR1_EM28_Msk         (0x1UL << EXTI_EMR1_EM28_Pos)               /*!< 0x10000000 */
+#define EXTI_EMR1_EM28             EXTI_EMR1_EM28_Msk                          /*!< Event Mask on line 28 */
+#define EXTI_EMR1_EM29_Pos         (29U)
+#define EXTI_EMR1_EM29_Msk         (0x1UL << EXTI_EMR1_EM29_Pos)               /*!< 0x20000000 */
+#define EXTI_EMR1_EM29             EXTI_EMR1_EM29_Msk                          /*!< Event Mask on line 29 */
+#define EXTI_EMR1_EM30_Pos         (30U)
+#define EXTI_EMR1_EM30_Msk         (0x1UL << EXTI_EMR1_EM30_Pos)               /*!< 0x40000000 */
+#define EXTI_EMR1_EM30             EXTI_EMR1_EM30_Msk                          /*!< Event Mask on line 30 */
+#define EXTI_EMR1_EM31_Pos         (31U)
+#define EXTI_EMR1_EM31_Msk         (0x1UL << EXTI_EMR1_EM31_Pos)               /*!< 0x80000000 */
+#define EXTI_EMR1_EM31             EXTI_EMR1_EM31_Msk                          /*!< Event Mask on line 31 */
+
+/*******************  Bit definition for EXTI_PR1 register  ********************/
+#define EXTI_PR1_PR_Pos            (0U)
+#define EXTI_PR1_PR_Msk            (0x3FFFFFUL << EXTI_PR1_PR_Pos)             /*!< 0x003FFFFF */
+#define EXTI_PR1_PR                EXTI_PR1_PR_Msk                             /*!< Pending bit */
+#define EXTI_PR1_PR0_Pos           (0U)
+#define EXTI_PR1_PR0_Msk           (0x1UL << EXTI_PR1_PR0_Pos)                 /*!< 0x00000001 */
+#define EXTI_PR1_PR0               EXTI_PR1_PR0_Msk                            /*!< Pending bit for line 0 */
+#define EXTI_PR1_PR1_Pos           (1U)
+#define EXTI_PR1_PR1_Msk           (0x1UL << EXTI_PR1_PR1_Pos)                 /*!< 0x00000002 */
+#define EXTI_PR1_PR1               EXTI_PR1_PR1_Msk                            /*!< Pending bit for line 1 */
+#define EXTI_PR1_PR2_Pos           (2U)
+#define EXTI_PR1_PR2_Msk           (0x1UL << EXTI_PR1_PR2_Pos)                 /*!< 0x00000004 */
+#define EXTI_PR1_PR2               EXTI_PR1_PR2_Msk                            /*!< Pending bit for line 2 */
+#define EXTI_PR1_PR3_Pos           (3U)
+#define EXTI_PR1_PR3_Msk           (0x1UL << EXTI_PR1_PR3_Pos)                 /*!< 0x00000008 */
+#define EXTI_PR1_PR3               EXTI_PR1_PR3_Msk                            /*!< Pending bit for line 3 */
+#define EXTI_PR1_PR4_Pos           (4U)
+#define EXTI_PR1_PR4_Msk           (0x1UL << EXTI_PR1_PR4_Pos)                 /*!< 0x00000010 */
+#define EXTI_PR1_PR4               EXTI_PR1_PR4_Msk                            /*!< Pending bit for line 4 */
+#define EXTI_PR1_PR5_Pos           (5U)
+#define EXTI_PR1_PR5_Msk           (0x1UL << EXTI_PR1_PR5_Pos)                 /*!< 0x00000020 */
+#define EXTI_PR1_PR5               EXTI_PR1_PR5_Msk                            /*!< Pending bit for line 5 */
+#define EXTI_PR1_PR6_Pos           (6U)
+#define EXTI_PR1_PR6_Msk           (0x1UL << EXTI_PR1_PR6_Pos)                 /*!< 0x00000040 */
+#define EXTI_PR1_PR6               EXTI_PR1_PR6_Msk                            /*!< Pending bit for line 6 */
+#define EXTI_PR1_PR7_Pos           (7U)
+#define EXTI_PR1_PR7_Msk           (0x1UL << EXTI_PR1_PR7_Pos)                 /*!< 0x00000080 */
+#define EXTI_PR1_PR7               EXTI_PR1_PR7_Msk                            /*!< Pending bit for line 7 */
+#define EXTI_PR1_PR8_Pos           (8U)
+#define EXTI_PR1_PR8_Msk           (0x1UL << EXTI_PR1_PR8_Pos)                 /*!< 0x00000100 */
+#define EXTI_PR1_PR8               EXTI_PR1_PR8_Msk                            /*!< Pending bit for line 8 */
+#define EXTI_PR1_PR9_Pos           (9U)
+#define EXTI_PR1_PR9_Msk           (0x1UL << EXTI_PR1_PR9_Pos)                 /*!< 0x00000200 */
+#define EXTI_PR1_PR9               EXTI_PR1_PR9_Msk                            /*!< Pending bit for line 9 */
+#define EXTI_PR1_PR10_Pos          (10U)
+#define EXTI_PR1_PR10_Msk          (0x1UL << EXTI_PR1_PR10_Pos)                /*!< 0x00000400 */
+#define EXTI_PR1_PR10              EXTI_PR1_PR10_Msk                           /*!< Pending bit for line 10 */
+#define EXTI_PR1_PR11_Pos          (11U)
+#define EXTI_PR1_PR11_Msk          (0x1UL << EXTI_PR1_PR11_Pos)                /*!< 0x00000800 */
+#define EXTI_PR1_PR11              EXTI_PR1_PR11_Msk                           /*!< Pending bit for line 11 */
+#define EXTI_PR1_PR12_Pos          (12U)
+#define EXTI_PR1_PR12_Msk          (0x1UL << EXTI_PR1_PR12_Pos)                /*!< 0x00001000 */
+#define EXTI_PR1_PR12              EXTI_PR1_PR12_Msk                           /*!< Pending bit for line 12 */
+#define EXTI_PR1_PR13_Pos          (13U)
+#define EXTI_PR1_PR13_Msk          (0x1UL << EXTI_PR1_PR13_Pos)                /*!< 0x00002000 */
+#define EXTI_PR1_PR13              EXTI_PR1_PR13_Msk                           /*!< Pending bit for line 13 */
+#define EXTI_PR1_PR14_Pos          (14U)
+#define EXTI_PR1_PR14_Msk          (0x1UL << EXTI_PR1_PR14_Pos)                /*!< 0x00004000 */
+#define EXTI_PR1_PR14              EXTI_PR1_PR14_Msk                           /*!< Pending bit for line 14 */
+#define EXTI_PR1_PR15_Pos          (15U)
+#define EXTI_PR1_PR15_Msk          (0x1UL << EXTI_PR1_PR15_Pos)                /*!< 0x00008000 */
+#define EXTI_PR1_PR15              EXTI_PR1_PR15_Msk                           /*!< Pending bit for line 15 */
+#define EXTI_PR1_PR16_Pos          (16U)
+#define EXTI_PR1_PR16_Msk          (0x1UL << EXTI_PR1_PR16_Pos)                /*!< 0x00010000 */
+#define EXTI_PR1_PR16              EXTI_PR1_PR16_Msk                           /*!< Pending bit for line 16 */
+#define EXTI_PR1_PR17_Pos          (17U)
+#define EXTI_PR1_PR17_Msk          (0x1UL << EXTI_PR1_PR17_Pos)                /*!< 0x00020000 */
+#define EXTI_PR1_PR17              EXTI_PR1_PR17_Msk                           /*!< Pending bit for line 17 */
+#define EXTI_PR1_PR18_Pos          (18U)
+#define EXTI_PR1_PR18_Msk          (0x1UL << EXTI_PR1_PR18_Pos)                /*!< 0x00040000 */
+#define EXTI_PR1_PR18              EXTI_PR1_PR18_Msk                           /*!< Pending bit for line 18 */
+#define EXTI_PR1_PR19_Pos          (19U)
+#define EXTI_PR1_PR19_Msk          (0x1UL << EXTI_PR1_PR19_Pos)                /*!< 0x00080000 */
+#define EXTI_PR1_PR19              EXTI_PR1_PR19_Msk                           /*!< Pending bit for line 19 */
+#define EXTI_PR1_PR20_Pos          (20U)
+#define EXTI_PR1_PR20_Msk          (0x1UL << EXTI_PR1_PR20_Pos)                /*!< 0x00100000 */
+#define EXTI_PR1_PR20              EXTI_PR1_PR20_Msk                           /*!< Pending bit for line 20 */
+#define EXTI_PR1_PR21_Pos          (21U)
+#define EXTI_PR1_PR21_Msk          (0x1UL << EXTI_PR1_PR21_Pos)                /*!< 0x00200000 */
+#define EXTI_PR1_PR21              EXTI_PR1_PR21_Msk                           /*!< Pending bit for line 21 */
+
+/*******************  Bit definition for EXTI_IMR2 register  *******************/
+#define EXTI_IMR2_IM_Pos           (0U)
+#define EXTI_IMR2_IM_Msk           (0xFFFFDFFFUL << EXTI_IMR2_IM_Pos)          /*!< 0xFFFFDFFF */
+#define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            /*!< Interrupt Mask */
+#define EXTI_IMR2_IM32_Pos         (0U)
+#define EXTI_IMR2_IM32_Msk         (0x1UL << EXTI_IMR2_IM32_Pos)               /*!< 0x00000001 */
+#define EXTI_IMR2_IM32             EXTI_IMR2_IM32_Msk                          /*!< Interrupt Mask on line 32 */
+#define EXTI_IMR2_IM33_Pos         (1U)
+#define EXTI_IMR2_IM33_Msk         (0x1UL << EXTI_IMR2_IM33_Pos)               /*!< 0x00000002 */
+#define EXTI_IMR2_IM33             EXTI_IMR2_IM33_Msk                          /*!< Interrupt Mask on line 33 */
+#define EXTI_IMR2_IM34_Pos         (2U)
+#define EXTI_IMR2_IM34_Msk         (0x1UL << EXTI_IMR2_IM34_Pos)               /*!< 0x00000004 */
+#define EXTI_IMR2_IM34             EXTI_IMR2_IM34_Msk                          /*!< Interrupt Mask on line 34 */
+#define EXTI_IMR2_IM35_Pos         (3U)
+#define EXTI_IMR2_IM35_Msk         (0x1UL << EXTI_IMR2_IM35_Pos)               /*!< 0x00000008 */
+#define EXTI_IMR2_IM35             EXTI_IMR2_IM35_Msk                          /*!< Interrupt Mask on line 35 */
+#define EXTI_IMR2_IM36_Pos         (4U)
+#define EXTI_IMR2_IM36_Msk         (0x1UL << EXTI_IMR2_IM36_Pos)               /*!< 0x00000010 */
+#define EXTI_IMR2_IM36             EXTI_IMR2_IM36_Msk                          /*!< Interrupt Mask on line 36 */
+#define EXTI_IMR2_IM37_Pos         (5U)
+#define EXTI_IMR2_IM37_Msk         (0x1UL << EXTI_IMR2_IM37_Pos)               /*!< 0x00000020 */
+#define EXTI_IMR2_IM37             EXTI_IMR2_IM37_Msk                          /*!< Interrupt Mask on line 37 */
+#define EXTI_IMR2_IM38_Pos         (6U)
+#define EXTI_IMR2_IM38_Msk         (0x1UL << EXTI_IMR2_IM38_Pos)               /*!< 0x00000040 */
+#define EXTI_IMR2_IM38             EXTI_IMR2_IM38_Msk                          /*!< Interrupt Mask on line 38 */
+#define EXTI_IMR2_IM39_Pos         (7U)
+#define EXTI_IMR2_IM39_Msk         (0x1UL << EXTI_IMR2_IM39_Pos)               /*!< 0x00000080 */
+#define EXTI_IMR2_IM39             EXTI_IMR2_IM39_Msk                          /*!< Interrupt Mask on line 39 */
+#define EXTI_IMR2_IM40_Pos         (8U)
+#define EXTI_IMR2_IM40_Msk         (0x1UL << EXTI_IMR2_IM40_Pos)               /*!< 0x00000100 */
+#define EXTI_IMR2_IM40             EXTI_IMR2_IM40_Msk                          /*!< Interrupt Mask on line 40 */
+#define EXTI_IMR2_IM41_Pos         (9U)
+#define EXTI_IMR2_IM41_Msk         (0x1UL << EXTI_IMR2_IM41_Pos)               /*!< 0x00000200 */
+#define EXTI_IMR2_IM41             EXTI_IMR2_IM41_Msk                          /*!< Interrupt Mask on line 41 */
+#define EXTI_IMR2_IM42_Pos         (10U)
+#define EXTI_IMR2_IM42_Msk         (0x1UL << EXTI_IMR2_IM42_Pos)               /*!< 0x00000400 */
+#define EXTI_IMR2_IM42             EXTI_IMR2_IM42_Msk                          /*!< Interrupt Mask on line 42 */
+#define EXTI_IMR2_IM43_Pos         (11U)
+#define EXTI_IMR2_IM43_Msk         (0x1UL << EXTI_IMR2_IM43_Pos)               /*!< 0x00000800 */
+#define EXTI_IMR2_IM43             EXTI_IMR2_IM43_Msk                          /*!< Interrupt Mask on line 43 */
+#define EXTI_IMR2_IM44_Pos         (12U)
+#define EXTI_IMR2_IM44_Msk         (0x1UL << EXTI_IMR2_IM44_Pos)               /*!< 0x00001000 */
+#define EXTI_IMR2_IM44             EXTI_IMR2_IM44_Msk                          /*!< Interrupt Mask on line 44 */
+#define EXTI_IMR2_IM46_Pos         (14U)
+#define EXTI_IMR2_IM46_Msk         (0x1UL << EXTI_IMR2_IM46_Pos)               /*!< 0x00004000 */
+#define EXTI_IMR2_IM46             EXTI_IMR2_IM46_Msk                          /*!< Interrupt Mask on line 46 */
+#define EXTI_IMR2_IM47_Pos         (15U)
+#define EXTI_IMR2_IM47_Msk         (0x1UL << EXTI_IMR2_IM47_Pos)               /*!< 0x00008000 */
+#define EXTI_IMR2_IM47             EXTI_IMR2_IM47_Msk                          /*!< Interrupt Mask on line 47 */
+#define EXTI_IMR2_IM48_Pos         (16U)
+#define EXTI_IMR2_IM48_Msk         (0x1UL << EXTI_IMR2_IM48_Pos)               /*!< 0x00010000 */
+#define EXTI_IMR2_IM48             EXTI_IMR2_IM48_Msk                          /*!< Interrupt Mask on line 48 */
+#define EXTI_IMR2_IM49_Pos         (17U)
+#define EXTI_IMR2_IM49_Msk         (0x1UL << EXTI_IMR2_IM49_Pos)               /*!< 0x00020000 */
+#define EXTI_IMR2_IM49             EXTI_IMR2_IM49_Msk                          /*!< Interrupt Mask on line 49 */
+#define EXTI_IMR2_IM50_Pos         (18U)
+#define EXTI_IMR2_IM50_Msk         (0x1UL << EXTI_IMR2_IM50_Pos)               /*!< 0x00040000 */
+#define EXTI_IMR2_IM50             EXTI_IMR2_IM50_Msk                          /*!< Interrupt Mask on line 50 */
+#define EXTI_IMR2_IM51_Pos         (19U)
+#define EXTI_IMR2_IM51_Msk         (0x1UL << EXTI_IMR2_IM51_Pos)               /*!< 0x00080000 */
+#define EXTI_IMR2_IM51             EXTI_IMR2_IM51_Msk                          /*!< Interrupt Mask on line 51 */
+#define EXTI_IMR2_IM52_Pos         (20U)
+#define EXTI_IMR2_IM52_Msk         (0x1UL << EXTI_IMR2_IM52_Pos)               /*!< 0x00100000 */
+#define EXTI_IMR2_IM52             EXTI_IMR2_IM52_Msk                          /*!< Interrupt Mask on line 52 */
+#define EXTI_IMR2_IM53_Pos         (21U)
+#define EXTI_IMR2_IM53_Msk         (0x1UL << EXTI_IMR2_IM53_Pos)               /*!< 0x00200000 */
+#define EXTI_IMR2_IM53             EXTI_IMR2_IM53_Msk                          /*!< Interrupt Mask on line 53 */
+#define EXTI_IMR2_IM54_Pos         (22U)
+#define EXTI_IMR2_IM54_Msk         (0x1UL << EXTI_IMR2_IM54_Pos)               /*!< 0x00400000 */
+#define EXTI_IMR2_IM54             EXTI_IMR2_IM54_Msk                          /*!< Interrupt Mask on line 54 */
+#define EXTI_IMR2_IM55_Pos         (23U)
+#define EXTI_IMR2_IM55_Msk         (0x1UL << EXTI_IMR2_IM55_Pos)               /*!< 0x00800000 */
+#define EXTI_IMR2_IM55             EXTI_IMR2_IM55_Msk                          /*!< Interrupt Mask on line 55 */
+#define EXTI_IMR2_IM56_Pos         (24U)
+#define EXTI_IMR2_IM56_Msk         (0x1UL << EXTI_IMR2_IM56_Pos)               /*!< 0x01000000 */
+#define EXTI_IMR2_IM56             EXTI_IMR2_IM56_Msk                          /*!< Interrupt Mask on line 56 */
+#define EXTI_IMR2_IM57_Pos         (25U)
+#define EXTI_IMR2_IM57_Msk         (0x1UL << EXTI_IMR2_IM57_Pos)               /*!< 0x02000000 */
+#define EXTI_IMR2_IM57             EXTI_IMR2_IM57_Msk                          /*!< Interrupt Mask on line 57 */
+#define EXTI_IMR2_IM58_Pos         (26U)
+#define EXTI_IMR2_IM58_Msk         (0x1UL << EXTI_IMR2_IM58_Pos)               /*!< 0x04000000 */
+#define EXTI_IMR2_IM58             EXTI_IMR2_IM58_Msk                          /*!< Interrupt Mask on line 58 */
+#define EXTI_IMR2_IM59_Pos         (27U)
+#define EXTI_IMR2_IM59_Msk         (0x1UL << EXTI_IMR2_IM59_Pos)               /*!< 0x08000000 */
+#define EXTI_IMR2_IM59             EXTI_IMR2_IM59_Msk                          /*!< Interrupt Mask on line 59 */
+#define EXTI_IMR2_IM60_Pos         (28U)
+#define EXTI_IMR2_IM60_Msk         (0x1UL << EXTI_IMR2_IM60_Pos)               /*!< 0x10000000 */
+#define EXTI_IMR2_IM60             EXTI_IMR2_IM60_Msk                          /*!< Interrupt Mask on line 60 */
+#define EXTI_IMR2_IM61_Pos         (29U)
+#define EXTI_IMR2_IM61_Msk         (0x1UL << EXTI_IMR2_IM61_Pos)               /*!< 0x20000000 */
+#define EXTI_IMR2_IM61             EXTI_IMR2_IM61_Msk                          /*!< Interrupt Mask on line 61 */
+#define EXTI_IMR2_IM62_Pos         (30U)
+#define EXTI_IMR2_IM62_Msk         (0x1UL << EXTI_IMR2_IM62_Pos)               /*!< 0x40000000 */
+#define EXTI_IMR2_IM62             EXTI_IMR2_IM62_Msk                          /*!< Interrupt Mask on line 62 */
+#define EXTI_IMR2_IM63_Pos         (31U)
+#define EXTI_IMR2_IM63_Msk         (0x1UL << EXTI_IMR2_IM63_Pos)               /*!< 0x80000000 */
+#define EXTI_IMR2_IM63             EXTI_IMR2_IM63_Msk                          /*!< Interrupt Mask on line 63 */
+
+/*******************  Bit definition for EXTI_EMR2 register  *******************/
+#define EXTI_EMR2_EM_Pos           (0U)
+#define EXTI_EMR2_EM_Msk           (0xFFFFDFFFUL << EXTI_EMR2_EM_Pos)          /*!< 0xFFFFDFFF */
+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            /*!< Event Mask */
+#define EXTI_EMR2_EM32_Pos         (0U)
+#define EXTI_EMR2_EM32_Msk         (0x1UL << EXTI_EMR2_EM32_Pos)               /*!< 0x00000001 */
+#define EXTI_EMR2_EM32             EXTI_EMR2_EM32_Msk                          /*!< Event Mask on line 32*/
+#define EXTI_EMR2_EM33_Pos         (1U)
+#define EXTI_EMR2_EM33_Msk         (0x1UL << EXTI_EMR2_EM33_Pos)               /*!< 0x00000002 */
+#define EXTI_EMR2_EM33             EXTI_EMR2_EM33_Msk                          /*!< Event Mask on line 33*/
+#define EXTI_EMR2_EM34_Pos         (2U)
+#define EXTI_EMR2_EM34_Msk         (0x1UL << EXTI_EMR2_EM34_Pos)               /*!< 0x00000004 */
+#define EXTI_EMR2_EM34             EXTI_EMR2_EM34_Msk                          /*!< Event Mask on line 34*/
+#define EXTI_EMR2_EM35_Pos         (3U)
+#define EXTI_EMR2_EM35_Msk         (0x1UL << EXTI_EMR2_EM35_Pos)               /*!< 0x00000008 */
+#define EXTI_EMR2_EM35             EXTI_EMR2_EM35_Msk                          /*!< Event Mask on line 35*/
+#define EXTI_EMR2_EM36_Pos         (4U)
+#define EXTI_EMR2_EM36_Msk         (0x1UL << EXTI_EMR2_EM36_Pos)               /*!< 0x00000010 */
+#define EXTI_EMR2_EM36             EXTI_EMR2_EM36_Msk                          /*!< Event Mask on line 36*/
+#define EXTI_EMR2_EM37_Pos         (5U)
+#define EXTI_EMR2_EM37_Msk         (0x1UL << EXTI_EMR2_EM37_Pos)               /*!< 0x00000020 */
+#define EXTI_EMR2_EM37             EXTI_EMR2_EM37_Msk                          /*!< Event Mask on line 37*/
+#define EXTI_EMR2_EM38_Pos         (6U)
+#define EXTI_EMR2_EM38_Msk         (0x1UL << EXTI_EMR2_EM38_Pos)               /*!< 0x00000040 */
+#define EXTI_EMR2_EM38             EXTI_EMR2_EM38_Msk                          /*!< Event Mask on line 38*/
+#define EXTI_EMR2_EM39_Pos         (7U)
+#define EXTI_EMR2_EM39_Msk         (0x1UL << EXTI_EMR2_EM39_Pos)               /*!< 0x00000080 */
+#define EXTI_EMR2_EM39             EXTI_EMR2_EM39_Msk                          /*!< Event Mask on line 39*/
+#define EXTI_EMR2_EM40_Pos         (8U)
+#define EXTI_EMR2_EM40_Msk         (0x1UL << EXTI_EMR2_EM40_Pos)               /*!< 0x00000100 */
+#define EXTI_EMR2_EM40             EXTI_EMR2_EM40_Msk                          /*!< Event Mask on line 40*/
+#define EXTI_EMR2_EM41_Pos         (9U)
+#define EXTI_EMR2_EM41_Msk         (0x1UL << EXTI_EMR2_EM41_Pos)               /*!< 0x00000200 */
+#define EXTI_EMR2_EM41             EXTI_EMR2_EM41_Msk                          /*!< Event Mask on line 41*/
+#define EXTI_EMR2_EM42_Pos         (10U)
+#define EXTI_EMR2_EM42_Msk         (0x1UL << EXTI_EMR2_EM42_Pos)               /*!< 0x00000400 */
+#define EXTI_EMR2_EM42             EXTI_EMR2_EM42_Msk                          /*!< Event Mask on line 42 */
+#define EXTI_EMR2_EM43_Pos         (11U)
+#define EXTI_EMR2_EM43_Msk         (0x1UL << EXTI_EMR2_EM43_Pos)               /*!< 0x00000800 */
+#define EXTI_EMR2_EM43             EXTI_EMR2_EM43_Msk                          /*!< Event Mask on line 43 */
+#define EXTI_EMR2_EM44_Pos         (12U)
+#define EXTI_EMR2_EM44_Msk         (0x1UL << EXTI_EMR2_EM44_Pos)               /*!< 0x00001000 */
+#define EXTI_EMR2_EM44             EXTI_EMR2_EM44_Msk                          /*!< Event Mask on line 44 */
+#define EXTI_EMR2_EM46_Pos         (14U)
+#define EXTI_EMR2_EM46_Msk         (0x1UL << EXTI_EMR2_EM46_Pos)               /*!< 0x00004000 */
+#define EXTI_EMR2_EM46             EXTI_EMR2_EM46_Msk                          /*!< Event Mask on line 46 */
+#define EXTI_EMR2_EM47_Pos         (15U)
+#define EXTI_EMR2_EM47_Msk         (0x1UL << EXTI_EMR2_EM47_Pos)               /*!< 0x00008000 */
+#define EXTI_EMR2_EM47             EXTI_EMR2_EM47_Msk                          /*!< Event Mask on line 47 */
+#define EXTI_EMR2_EM48_Pos         (16U)
+#define EXTI_EMR2_EM48_Msk         (0x1UL << EXTI_EMR2_EM48_Pos)               /*!< 0x00010000 */
+#define EXTI_EMR2_EM48             EXTI_EMR2_EM48_Msk                          /*!< Event Mask on line 48 */
+#define EXTI_EMR2_EM49_Pos         (17U)
+#define EXTI_EMR2_EM49_Msk         (0x1UL << EXTI_EMR2_EM49_Pos)               /*!< 0x00020000 */
+#define EXTI_EMR2_EM49             EXTI_EMR2_EM49_Msk                          /*!< Event Mask on line 49 */
+#define EXTI_EMR2_EM50_Pos         (18U)
+#define EXTI_EMR2_EM50_Msk         (0x1UL << EXTI_EMR2_EM50_Pos)               /*!< 0x00040000 */
+#define EXTI_EMR2_EM50             EXTI_EMR2_EM50_Msk                          /*!< Event Mask on line 50 */
+#define EXTI_EMR2_EM51_Pos         (19U)
+#define EXTI_EMR2_EM51_Msk         (0x1UL << EXTI_EMR2_EM51_Pos)               /*!< 0x00080000 */
+#define EXTI_EMR2_EM51             EXTI_EMR2_EM51_Msk                          /*!< Event Mask on line 51 */
+#define EXTI_EMR2_EM52_Pos         (20U)
+#define EXTI_EMR2_EM52_Msk         (0x1UL << EXTI_EMR2_EM52_Pos)               /*!< 0x00100000 */
+#define EXTI_EMR2_EM52             EXTI_EMR2_EM52_Msk                          /*!< Event Mask on line 52 */
+#define EXTI_EMR2_EM53_Pos         (21U)
+#define EXTI_EMR2_EM53_Msk         (0x1UL << EXTI_EMR2_EM53_Pos)               /*!< 0x00200000 */
+#define EXTI_EMR2_EM53             EXTI_EMR2_EM53_Msk                          /*!< Event Mask on line 53 */
+#define EXTI_EMR2_EM54_Pos         (22U)
+#define EXTI_EMR2_EM54_Msk         (0x1UL << EXTI_EMR2_EM54_Pos)               /*!< 0x00400000 */
+#define EXTI_EMR2_EM54             EXTI_EMR2_EM54_Msk                          /*!< Event Mask on line 54 */
+#define EXTI_EMR2_EM55_Pos         (23U)
+#define EXTI_EMR2_EM55_Msk         (0x1UL << EXTI_EMR2_EM55_Pos)               /*!< 0x00800000 */
+#define EXTI_EMR2_EM55             EXTI_EMR2_EM55_Msk                          /*!< Event Mask on line 55 */
+#define EXTI_EMR2_EM56_Pos         (24U)
+#define EXTI_EMR2_EM56_Msk         (0x1UL << EXTI_EMR2_EM56_Pos)               /*!< 0x01000000 */
+#define EXTI_EMR2_EM56             EXTI_EMR2_EM56_Msk                          /*!< Event Mask on line 56 */
+#define EXTI_EMR2_EM57_Pos         (25U)
+#define EXTI_EMR2_EM57_Msk         (0x1UL << EXTI_EMR2_EM57_Pos)               /*!< 0x02000000 */
+#define EXTI_EMR2_EM57             EXTI_EMR2_EM57_Msk                          /*!< Event Mask on line 57 */
+#define EXTI_EMR2_EM58_Pos         (26U)
+#define EXTI_EMR2_EM58_Msk         (0x1UL << EXTI_EMR2_EM58_Pos)               /*!< 0x04000000 */
+#define EXTI_EMR2_EM58             EXTI_EMR2_EM58_Msk                          /*!< Event Mask on line 58 */
+#define EXTI_EMR2_EM59_Pos         (27U)
+#define EXTI_EMR2_EM59_Msk         (0x1UL << EXTI_EMR2_EM59_Pos)               /*!< 0x08000000 */
+#define EXTI_EMR2_EM59             EXTI_EMR2_EM59_Msk                          /*!< Event Mask on line 59 */
+#define EXTI_EMR2_EM60_Pos         (28U)
+#define EXTI_EMR2_EM60_Msk         (0x1UL << EXTI_EMR2_EM60_Pos)               /*!< 0x10000000 */
+#define EXTI_EMR2_EM60             EXTI_EMR2_EM60_Msk                          /*!< Event Mask on line 60 */
+#define EXTI_EMR2_EM61_Pos         (29U)
+#define EXTI_EMR2_EM61_Msk         (0x1UL << EXTI_EMR2_EM61_Pos)               /*!< 0x20000000 */
+#define EXTI_EMR2_EM61             EXTI_EMR2_EM61_Msk                          /*!< Event Mask on line 61 */
+#define EXTI_EMR2_EM62_Pos         (30U)
+#define EXTI_EMR2_EM62_Msk         (0x1UL << EXTI_EMR2_EM62_Pos)               /*!< 0x40000000 */
+#define EXTI_EMR2_EM62             EXTI_EMR2_EM62_Msk                          /*!< Event Mask on line 62 */
+#define EXTI_EMR2_EM63_Pos         (31U)
+#define EXTI_EMR2_EM63_Msk         (0x1UL << EXTI_EMR2_EM63_Pos)               /*!< 0x80000000 */
+#define EXTI_EMR2_EM63             EXTI_EMR2_EM63_Msk                          /*!< Event Mask on line 63 */
+
+/*******************  Bit definition for EXTI_PR2 register  ********************/
+#define EXTI_PR2_PR_Pos            (17U)
+#define EXTI_PR2_PR_Msk            (0x5UL << EXTI_PR2_PR_Pos)                  /*!< 0x000A0000 */
+#define EXTI_PR2_PR                EXTI_PR2_PR_Msk                             /*!< Pending bit */
+#define EXTI_PR2_PR49_Pos          (17U)
+#define EXTI_PR2_PR49_Msk          (0x1UL << EXTI_PR2_PR49_Pos)                /*!< 0x00020000 */
+#define EXTI_PR2_PR49              EXTI_PR2_PR49_Msk                           /*!< Pending bit for line 49 */
+#define EXTI_PR2_PR51_Pos          (19U)
+#define EXTI_PR2_PR51_Msk          (0x1UL << EXTI_PR2_PR51_Pos)                /*!< 0x00080000 */
+#define EXTI_PR2_PR51              EXTI_PR2_PR51_Msk                           /*!< Pending bit for line 51 */
+
+/*******************  Bit definition for EXTI_IMR3 register  *******************/
+#define EXTI_IMR3_IM_Pos           (0U)
+#define EXTI_IMR3_IM_Msk           (0x00F5FFFFUL << EXTI_IMR3_IM_Pos)          /*!< 0x00F5FFFF */
+#define EXTI_IMR3_IM               EXTI_IMR3_IM_Msk                            /*!< Interrupt Mask */
+#define EXTI_IMR3_IM64_Pos         (0U)
+#define EXTI_IMR3_IM64_Msk         (0x1UL << EXTI_IMR3_IM64_Pos)               /*!< 0x00000001 */
+#define EXTI_IMR3_IM64             EXTI_IMR3_IM64_Msk                          /*!< Interrupt Mask on line 64 */
+#define EXTI_IMR3_IM65_Pos         (1U)
+#define EXTI_IMR3_IM65_Msk         (0x1UL << EXTI_IMR3_IM65_Pos)               /*!< 0x00000002 */
+#define EXTI_IMR3_IM65             EXTI_IMR3_IM65_Msk                          /*!< Interrupt Mask on line 65 */
+#define EXTI_IMR3_IM66_Pos         (2U)
+#define EXTI_IMR3_IM66_Msk         (0x1UL << EXTI_IMR3_IM66_Pos)               /*!< 0x00000004 */
+#define EXTI_IMR3_IM66             EXTI_IMR3_IM66_Msk                          /*!< Interrupt Mask on line 66 */
+#define EXTI_IMR3_IM67_Pos         (3U)
+#define EXTI_IMR3_IM67_Msk         (0x1UL << EXTI_IMR3_IM67_Pos)               /*!< 0x00000008 */
+#define EXTI_IMR3_IM67             EXTI_IMR3_IM67_Msk                          /*!< Interrupt Mask on line 67 */
+#define EXTI_IMR3_IM68_Pos         (4U)
+#define EXTI_IMR3_IM68_Msk         (0x1UL << EXTI_IMR3_IM68_Pos)               /*!< 0x00000010 */
+#define EXTI_IMR3_IM68             EXTI_IMR3_IM68_Msk                          /*!< Interrupt Mask on line 68 */
+#define EXTI_IMR3_IM69_Pos         (5U)
+#define EXTI_IMR3_IM69_Msk         (0x1UL << EXTI_IMR3_IM69_Pos)               /*!< 0x00000020 */
+#define EXTI_IMR3_IM69             EXTI_IMR3_IM69_Msk                          /*!< Interrupt Mask on line 69 */
+#define EXTI_IMR3_IM70_Pos         (6U)
+#define EXTI_IMR3_IM70_Msk         (0x1UL << EXTI_IMR3_IM70_Pos)               /*!< 0x00000040 */
+#define EXTI_IMR3_IM70             EXTI_IMR3_IM70_Msk                          /*!< Interrupt Mask on line 70 */
+#define EXTI_IMR3_IM71_Pos         (7U)
+#define EXTI_IMR3_IM71_Msk         (0x1UL << EXTI_IMR3_IM71_Pos)               /*!< 0x00000080 */
+#define EXTI_IMR3_IM71             EXTI_IMR3_IM71_Msk                          /*!< Interrupt Mask on line 71 */
+#define EXTI_IMR3_IM72_Pos         (8U)
+#define EXTI_IMR3_IM72_Msk         (0x1UL << EXTI_IMR3_IM72_Pos)               /*!< 0x00000100 */
+#define EXTI_IMR3_IM72             EXTI_IMR3_IM72_Msk                          /*!< Interrupt Mask on line 72 */
+#define EXTI_IMR3_IM73_Pos         (9U)
+#define EXTI_IMR3_IM73_Msk         (0x1UL << EXTI_IMR3_IM73_Pos)               /*!< 0x00000200 */
+#define EXTI_IMR3_IM73             EXTI_IMR3_IM73_Msk                          /*!< Interrupt Mask on line 73 */
+#define EXTI_IMR3_IM74_Pos         (10U)
+#define EXTI_IMR3_IM74_Msk         (0x1UL << EXTI_IMR3_IM74_Pos)               /*!< 0x00000400 */
+#define EXTI_IMR3_IM74             EXTI_IMR3_IM74_Msk                          /*!< Interrupt Mask on line 74 */
+#define EXTI_IMR3_IM75_Pos         (11U)
+#define EXTI_IMR3_IM75_Msk         (0x1UL << EXTI_IMR3_IM75_Pos)               /*!< 0x00000800 */
+#define EXTI_IMR3_IM75             EXTI_IMR3_IM75_Msk                          /*!< Interrupt Mask on line 75 */
+#define EXTI_IMR3_IM76_Pos         (12U)
+#define EXTI_IMR3_IM76_Msk         (0x1UL << EXTI_IMR3_IM76_Pos)               /*!< 0x00001000 */
+#define EXTI_IMR3_IM76             EXTI_IMR3_IM76_Msk                          /*!< Interrupt Mask on line 76 */
+#define EXTI_IMR3_IM77_Pos         (13U)
+#define EXTI_IMR3_IM77_Msk         (0x1UL << EXTI_IMR3_IM77_Pos)               /*!< 0x00002000 */
+#define EXTI_IMR3_IM77             EXTI_IMR3_IM77_Msk                          /*!< Interrupt Mask on line 77 */
+#define EXTI_IMR3_IM78_Pos         (14U)
+#define EXTI_IMR3_IM78_Msk         (0x1UL << EXTI_IMR3_IM78_Pos)               /*!< 0x00004000 */
+#define EXTI_IMR3_IM78             EXTI_IMR3_IM78_Msk                          /*!< Interrupt Mask on line 78 */
+#define EXTI_IMR3_IM79_Pos         (15U)
+#define EXTI_IMR3_IM79_Msk         (0x1UL << EXTI_IMR3_IM79_Pos)               /*!< 0x00008000 */
+#define EXTI_IMR3_IM79             EXTI_IMR3_IM79_Msk                          /*!< Interrupt Mask on line 79 */
+#define EXTI_IMR3_IM80_Pos         (16U)
+#define EXTI_IMR3_IM80_Msk         (0x1UL << EXTI_IMR3_IM80_Pos)               /*!< 0x00010000 */
+#define EXTI_IMR3_IM80             EXTI_IMR3_IM80_Msk                          /*!< Interrupt Mask on line 80 */
+#define EXTI_IMR3_IM82_Pos         (18U)
+#define EXTI_IMR3_IM82_Msk         (0x1UL << EXTI_IMR3_IM82_Pos)               /*!< 0x00040000 */
+#define EXTI_IMR3_IM82             EXTI_IMR3_IM82_Msk                          /*!< Interrupt Mask on line 82 */
+#define EXTI_IMR3_IM84_Pos         (20U)
+#define EXTI_IMR3_IM84_Msk         (0x1UL << EXTI_IMR3_IM84_Pos)               /*!< 0x00100000 */
+#define EXTI_IMR3_IM84             EXTI_IMR3_IM84_Msk                          /*!< Interrupt Mask on line 84 */
+#define EXTI_IMR3_IM85_Pos         (21U)
+#define EXTI_IMR3_IM85_Msk         (0x1UL << EXTI_IMR3_IM85_Pos)               /*!< 0x00200000 */
+#define EXTI_IMR3_IM85             EXTI_IMR3_IM85_Msk                          /*!< Interrupt Mask on line 85 */
+#define EXTI_IMR3_IM86_Pos         (22U)
+#define EXTI_IMR3_IM86_Msk         (0x1UL << EXTI_IMR3_IM86_Pos)               /*!< 0x00400000 */
+#define EXTI_IMR3_IM86             EXTI_IMR3_IM86_Msk                          /*!< Interrupt Mask on line 86 */
+#define EXTI_IMR3_IM87_Pos         (23U)
+#define EXTI_IMR3_IM87_Msk         (0x1UL << EXTI_IMR3_IM87_Pos)               /*!< 0x00800000 */
+#define EXTI_IMR3_IM87             EXTI_IMR3_IM87_Msk                          /*!< Interrupt Mask on line 87 */
+
+
+/*******************  Bit definition for EXTI_EMR3 register  *******************/
+#define EXTI_EMR3_EM_Pos           (0U)
+#define EXTI_EMR3_EM_Msk           (0x00F5FFFFUL << EXTI_EMR3_EM_Pos)          /*!< 0x00F5FFFF */
+#define EXTI_EMR3_EM               EXTI_EMR3_EM_Msk                            /*!< Event Mask           */
+#define EXTI_EMR3_EM64_Pos         (0U)
+#define EXTI_EMR3_EM64_Msk         (0x1UL << EXTI_EMR3_EM64_Pos)               /*!< 0x00000001 */
+#define EXTI_EMR3_EM64             EXTI_EMR3_EM64_Msk                          /*!< Event Mask on line 64*/
+#define EXTI_EMR3_EM65_Pos         (1U)
+#define EXTI_EMR3_EM65_Msk         (0x1UL << EXTI_EMR3_EM65_Pos)               /*!< 0x00000002 */
+#define EXTI_EMR3_EM65             EXTI_EMR3_EM65_Msk                          /*!< Event Mask on line 65*/
+#define EXTI_EMR3_EM66_Pos         (2U)
+#define EXTI_EMR3_EM66_Msk         (0x1UL << EXTI_EMR3_EM66_Pos)               /*!< 0x00000004 */
+#define EXTI_EMR3_EM66             EXTI_EMR3_EM66_Msk                          /*!< Event Mask on line 66*/
+#define EXTI_EMR3_EM67_Pos         (3U)
+#define EXTI_EMR3_EM67_Msk         (0x1UL << EXTI_EMR3_EM67_Pos)               /*!< 0x00000008 */
+#define EXTI_EMR3_EM67             EXTI_EMR3_EM67_Msk                          /*!< Event Mask on line 67*/
+#define EXTI_EMR3_EM68_Pos         (4U)
+#define EXTI_EMR3_EM68_Msk         (0x1UL << EXTI_EMR3_EM68_Pos)               /*!< 0x00000010 */
+#define EXTI_EMR3_EM68             EXTI_EMR3_EM68_Msk                          /*!< Event Mask on line 68*/
+#define EXTI_EMR3_EM69_Pos         (5U)
+#define EXTI_EMR3_EM69_Msk         (0x1UL << EXTI_EMR3_EM69_Pos)               /*!< 0x00000020 */
+#define EXTI_EMR3_EM69             EXTI_EMR3_EM69_Msk                          /*!< Event Mask on line 69*/
+#define EXTI_EMR3_EM70_Pos         (6U)
+#define EXTI_EMR3_EM70_Msk         (0x1UL << EXTI_EMR3_EM70_Pos)               /*!< 0x00000040 */
+#define EXTI_EMR3_EM70             EXTI_EMR3_EM70_Msk                          /*!< Event Mask on line 70*/
+#define EXTI_EMR3_EM71_Pos         (7U)
+#define EXTI_EMR3_EM71_Msk         (0x1UL << EXTI_EMR3_EM71_Pos)               /*!< 0x00000080 */
+#define EXTI_EMR3_EM71             EXTI_EMR3_EM71_Msk                          /*!< Event Mask on line 71*/
+#define EXTI_EMR3_EM72_Pos         (8U)
+#define EXTI_EMR3_EM72_Msk         (0x1UL << EXTI_EMR3_EM72_Pos)               /*!< 0x00000100 */
+#define EXTI_EMR3_EM72             EXTI_EMR3_EM72_Msk                          /*!< Event Mask on line 72*/
+#define EXTI_EMR3_EM73_Pos         (9U)
+#define EXTI_EMR3_EM73_Msk         (0x1UL << EXTI_EMR3_EM73_Pos)               /*!< 0x00000200 */
+#define EXTI_EMR3_EM73             EXTI_EMR3_EM73_Msk                          /*!< Event Mask on line 73*/
+#define EXTI_EMR3_EM74_Pos         (10U)
+#define EXTI_EMR3_EM74_Msk         (0x1UL << EXTI_EMR3_EM74_Pos)               /*!< 0x00000400 */
+#define EXTI_EMR3_EM74             EXTI_EMR3_EM74_Msk                          /*!< Event Mask on line 74 */
+#define EXTI_EMR3_EM75_Pos         (11U)
+#define EXTI_EMR3_EM75_Msk         (0x1UL << EXTI_EMR3_EM75_Pos)               /*!< 0x00000800 */
+#define EXTI_EMR3_EM75             EXTI_EMR3_EM75_Msk                          /*!< Event Mask on line 75 */
+#define EXTI_EMR3_EM76_Pos         (12U)
+#define EXTI_EMR3_EM76_Msk         (0x1UL << EXTI_EMR3_EM76_Pos)               /*!< 0x00001000 */
+#define EXTI_EMR3_EM76             EXTI_EMR3_EM76_Msk                          /*!< Event Mask on line 76 */
+#define EXTI_EMR3_EM77_Pos         (13U)
+#define EXTI_EMR3_EM77_Msk         (0x1UL << EXTI_EMR3_EM77_Pos)               /*!< 0x00002000 */
+#define EXTI_EMR3_EM77             EXTI_EMR3_EM77_Msk                          /*!< Event Mask on line 77 */
+#define EXTI_EMR3_EM78_Pos         (14U)
+#define EXTI_EMR3_EM78_Msk         (0x1UL << EXTI_EMR3_EM78_Pos)               /*!< 0x00004000 */
+#define EXTI_EMR3_EM78             EXTI_EMR3_EM78_Msk                          /*!< Event Mask on line 78 */
+#define EXTI_EMR3_EM79_Pos         (15U)
+#define EXTI_EMR3_EM79_Msk         (0x1UL << EXTI_EMR3_EM79_Pos)               /*!< 0x00008000 */
+#define EXTI_EMR3_EM79             EXTI_EMR3_EM79_Msk                          /*!< Event Mask on line 79 */
+#define EXTI_EMR3_EM80_Pos         (16U)
+#define EXTI_EMR3_EM80_Msk         (0x1UL << EXTI_EMR3_EM80_Pos)               /*!< 0x00010000 */
+#define EXTI_EMR3_EM80             EXTI_EMR3_EM80_Msk                          /*!< Event Mask on line 80 */
+#define EXTI_EMR3_EM81_Pos         (17U)
+#define EXTI_EMR3_EM81_Msk         (0x1UL << EXTI_EMR3_EM81_Pos)               /*!< 0x00020000 */
+#define EXTI_EMR3_EM81             EXTI_EMR3_EM81_Msk                          /*!< Event Mask on line 81 */
+#define EXTI_EMR3_EM82_Pos         (18U)
+#define EXTI_EMR3_EM82_Msk         (0x1UL << EXTI_EMR3_EM82_Pos)               /*!< 0x00040000 */
+#define EXTI_EMR3_EM82             EXTI_EMR3_EM82_Msk                          /*!< Event Mask on line 82 */
+#define EXTI_EMR3_EM84_Pos         (20U)
+#define EXTI_EMR3_EM84_Msk         (0x1UL << EXTI_EMR3_EM84_Pos)               /*!< 0x00100000 */
+#define EXTI_EMR3_EM84             EXTI_EMR3_EM84_Msk                          /*!< Event Mask on line 84 */
+#define EXTI_EMR3_EM85_Pos         (21U)
+#define EXTI_EMR3_EM85_Msk         (0x1UL << EXTI_EMR3_EM85_Pos)               /*!< 0x00200000 */
+#define EXTI_EMR3_EM85             EXTI_EMR3_EM85_Msk                          /*!< Event Mask on line 85 */
+#define EXTI_EMR3_EM86_Pos         (22U)
+#define EXTI_EMR3_EM86_Msk         (0x1UL << EXTI_EMR3_EM86_Pos)               /*!< 0x00400000 */
+#define EXTI_EMR3_EM86             EXTI_EMR3_EM86_Msk                          /*!< Event Mask on line 86 */
+#define EXTI_EMR3_EM87_Pos         (23U)
+#define EXTI_EMR3_EM87_Msk         (0x1UL << EXTI_EMR3_EM87_Pos)               /*!< 0x00800000 */
+#define EXTI_EMR3_EM87             EXTI_EMR3_EM87_Msk                          /*!< Event Mask on line 87 */
+
+/*******************  Bit definition for EXTI_PR3 register  ********************/
+#define EXTI_PR3_PR_Pos            (18U)
+#define EXTI_PR3_PR_Msk            (0x1DUL << EXTI_PR3_PR_Pos)                 /*!< 0x00740000 */
+#define EXTI_PR3_PR                EXTI_PR3_PR_Msk                             /*!< Pending bit */
+#define EXTI_PR3_PR82_Pos          (18U)
+#define EXTI_PR3_PR82_Msk          (0x1UL << EXTI_PR3_PR82_Pos)                /*!< 0x00040000 */
+#define EXTI_PR3_PR82              EXTI_PR3_PR82_Msk                           /*!< Pending bit for line 82 */
+#define EXTI_PR3_PR84_Pos          (20U)
+#define EXTI_PR3_PR84_Msk          (0x1UL << EXTI_PR3_PR84_Pos)                /*!< 0x00100000 */
+#define EXTI_PR3_PR84              EXTI_PR3_PR84_Msk                           /*!< Pending bit for line 84 */
+#define EXTI_PR3_PR85_Pos          (21U)
+#define EXTI_PR3_PR85_Msk          (0x1UL << EXTI_PR3_PR85_Pos)                /*!< 0x00200000 */
+#define EXTI_PR3_PR85              EXTI_PR3_PR85_Msk                           /*!< Pending bit for line 85 */
+#define EXTI_PR3_PR86_Pos          (22U)
+#define EXTI_PR3_PR86_Msk          (0x1UL << EXTI_PR3_PR86_Pos)                /*!< 0x00400000 */
+#define EXTI_PR3_PR86              EXTI_PR3_PR86_Msk                           /*!< Pending bit for line 86 */
+/******************************************************************************/
+/*                                                                            */
+/*                                    FLASH                                   */
+/*                                                                            */
+/******************************************************************************/
+/*
+* @brief FLASH Global Defines
+*/
+#define FLASH_SECTOR_TOTAL                   8U                    /* 8 sectors */
+#define FLASH_SIZE                           0x200000UL            /* 2 MB   */
+#define FLASH_BANK_SIZE                      (FLASH_SIZE >> 1)     /* 1 MB   */
+#define FLASH_SECTOR_SIZE                    0x00020000UL          /* 128 KB */
+#define FLASH_LATENCY_DEFAULT                FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */
+#define FLASH_NB_32BITWORD_IN_FLASHWORD      8U                    /* 256 bits */
+#define DUAL_BANK                                                  /* Dual-bank Flash */
+
+/*******************  Bits definition for FLASH_ACR register  **********************/
+#define FLASH_ACR_LATENCY_Pos                (0U)
+#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Read Latency */
+#define FLASH_ACR_LATENCY_0WS                (0x00000000UL)
+#define FLASH_ACR_LATENCY_1WS                (0x00000001UL)
+#define FLASH_ACR_LATENCY_2WS                (0x00000002UL)
+#define FLASH_ACR_LATENCY_3WS                (0x00000003UL)
+#define FLASH_ACR_LATENCY_4WS                (0x00000004UL)
+#define FLASH_ACR_LATENCY_5WS                (0x00000005UL)
+#define FLASH_ACR_LATENCY_6WS                (0x00000006UL)
+#define FLASH_ACR_LATENCY_7WS                (0x00000007UL)
+#define FLASH_ACR_LATENCY_8WS                (0x00000008UL)
+#define FLASH_ACR_LATENCY_9WS                (0x00000009UL)
+#define FLASH_ACR_LATENCY_10WS               (0x0000000AUL)
+#define FLASH_ACR_LATENCY_11WS               (0x0000000BUL)
+#define FLASH_ACR_LATENCY_12WS               (0x0000000CUL)
+#define FLASH_ACR_LATENCY_13WS               (0x0000000DUL)
+#define FLASH_ACR_LATENCY_14WS               (0x0000000EUL)
+#define FLASH_ACR_LATENCY_15WS               (0x0000000FUL)
+#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
+#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
+#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
+#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
+#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
+
+/*******************  Bits definition for FLASH_CR register  ***********************/
+#define FLASH_CR_LOCK_Pos                    (0U)
+#define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)      /*!< 0x00000001 */
+#define FLASH_CR_LOCK                        FLASH_CR_LOCK_Msk                 /*!< Configuration lock bit */
+#define FLASH_CR_PG_Pos                      (1U)
+#define FLASH_CR_PG_Msk                      (0x1UL << FLASH_CR_PG_Pos)        /*!< 0x00000002 */
+#define FLASH_CR_PG                          FLASH_CR_PG_Msk                   /*!< Internal buffer control bit */
+#define FLASH_CR_SER_Pos                     (2U)
+#define FLASH_CR_SER_Msk                     (0x1UL << FLASH_CR_SER_Pos)       /*!< 0x00000004 */
+#define FLASH_CR_SER                         FLASH_CR_SER_Msk                  /*!< Sector erase request */
+#define FLASH_CR_BER_Pos                     (3U)
+#define FLASH_CR_BER_Msk                     (0x1UL << FLASH_CR_BER_Pos)       /*!< 0x00000008 */
+#define FLASH_CR_BER                         FLASH_CR_BER_Msk                  /*!< Bank erase request */
+#define FLASH_CR_PSIZE_Pos                   (4U)
+#define FLASH_CR_PSIZE_Msk                   (0x3UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000030 */
+#define FLASH_CR_PSIZE                       FLASH_CR_PSIZE_Msk                /*!< Program size */
+#define FLASH_CR_PSIZE_0                     (0x1UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000010 */
+#define FLASH_CR_PSIZE_1                     (0x2UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000020 */
+#define FLASH_CR_FW_Pos                      (6U)
+#define FLASH_CR_FW_Msk                      (0x1UL << FLASH_CR_FW_Pos)        /*!< 0x00000040 */
+#define FLASH_CR_FW                          FLASH_CR_FW_Msk                   /*!< Write forcing control bit */
+#define FLASH_CR_START_Pos                   (7U)
+#define FLASH_CR_START_Msk                   (0x1UL << FLASH_CR_START_Pos)     /*!< 0x00000080 */
+#define FLASH_CR_START                       FLASH_CR_START_Msk                /*!< Erase start control bit */
+#define FLASH_CR_SNB_Pos                     (8U)
+#define FLASH_CR_SNB_Msk                     (0x7UL << FLASH_CR_SNB_Pos)       /*!< 0x00000700 */
+#define FLASH_CR_SNB                         FLASH_CR_SNB_Msk                  /*!< Sector erase selection number */
+#define FLASH_CR_SNB_0                       (0x1UL << FLASH_CR_SNB_Pos)       /*!< 0x00000100 */
+#define FLASH_CR_SNB_1                       (0x2UL << FLASH_CR_SNB_Pos)       /*!< 0x00000200 */
+#define FLASH_CR_SNB_2                       (0x4UL << FLASH_CR_SNB_Pos)       /*!< 0x00000400 */
+#define FLASH_CR_CRC_EN_Pos                  (15U)
+#define FLASH_CR_CRC_EN_Msk                  (0x1UL << FLASH_CR_CRC_EN_Pos)    /*!< 0x00008000 */
+#define FLASH_CR_CRC_EN                      FLASH_CR_CRC_EN_Msk               /*!< CRC control bit */
+#define FLASH_CR_EOPIE_Pos                   (16U)
+#define FLASH_CR_EOPIE_Msk                   (0x1UL << FLASH_CR_EOPIE_Pos)     /*!< 0x00010000 */
+#define FLASH_CR_EOPIE                       FLASH_CR_EOPIE_Msk                /*!< End-of-program interrupt control bit */
+#define FLASH_CR_WRPERRIE_Pos                (17U)
+#define FLASH_CR_WRPERRIE_Msk                (0x1UL << FLASH_CR_WRPERRIE_Pos)  /*!< 0x00020000 */
+#define FLASH_CR_WRPERRIE                    FLASH_CR_WRPERRIE_Msk             /*!< Write protection error interrupt enable bit */
+#define FLASH_CR_PGSERRIE_Pos                (18U)
+#define FLASH_CR_PGSERRIE_Msk                (0x1UL << FLASH_CR_PGSERRIE_Pos)  /*!< 0x00040000 */
+#define FLASH_CR_PGSERRIE                    FLASH_CR_PGSERRIE_Msk             /*!< Programming sequence error interrupt enable bit */
+#define FLASH_CR_STRBERRIE_Pos               (19U)
+#define FLASH_CR_STRBERRIE_Msk               (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */
+#define FLASH_CR_STRBERRIE                   FLASH_CR_STRBERRIE_Msk            /*!< Strobe error interrupt enable bit */
+#define FLASH_CR_INCERRIE_Pos                (21U)
+#define FLASH_CR_INCERRIE_Msk                (0x1UL << FLASH_CR_INCERRIE_Pos)  /*!< 0x00200000 */
+#define FLASH_CR_INCERRIE                    FLASH_CR_INCERRIE_Msk             /*!< Inconsistency error interrupt enable bit */
+#define FLASH_CR_OPERRIE_Pos                 (22U)
+#define FLASH_CR_OPERRIE_Msk                 (0x1UL << FLASH_CR_OPERRIE_Pos)   /*!< 0x00400000 */
+#define FLASH_CR_OPERRIE                     FLASH_CR_OPERRIE_Msk              /*!< Write/erase error interrupt enable bit */
+#define FLASH_CR_RDPERRIE_Pos                (23U)
+#define FLASH_CR_RDPERRIE_Msk                (0x1UL << FLASH_CR_RDPERRIE_Pos)  /*!< 0x00800000 */
+#define FLASH_CR_RDPERRIE                    FLASH_CR_RDPERRIE_Msk             /*!< Read protection error interrupt enable bit */
+#define FLASH_CR_RDSERRIE_Pos                (24U)
+#define FLASH_CR_RDSERRIE_Msk                (0x1UL << FLASH_CR_RDSERRIE_Pos)  /*!< 0x01000000 */
+#define FLASH_CR_RDSERRIE                    FLASH_CR_RDSERRIE_Msk             /*!< Secure error interrupt enable bit */
+#define FLASH_CR_SNECCERRIE_Pos              (25U)
+#define FLASH_CR_SNECCERRIE_Msk              (0x1UL << FLASH_CR_SNECCERRIE_Pos) /*!< 0x02000000 */
+#define FLASH_CR_SNECCERRIE                  FLASH_CR_SNECCERRIE_Msk            /*!< ECC single correction error interrupt enable bit */
+#define FLASH_CR_DBECCERRIE_Pos              (26U)
+#define FLASH_CR_DBECCERRIE_Msk              (0x1UL << FLASH_CR_DBECCERRIE_Pos) /*!< 0x04000000 */
+#define FLASH_CR_DBECCERRIE                  FLASH_CR_DBECCERRIE_Msk            /*!< ECC double detection error interrupt enable bit */
+#define FLASH_CR_CRCENDIE_Pos                (27U)
+#define FLASH_CR_CRCENDIE_Msk                (0x1UL << FLASH_CR_CRCENDIE_Pos)  /*!< 0x08000000 */
+#define FLASH_CR_CRCENDIE                    FLASH_CR_CRCENDIE_Msk             /*!< CRC end of calculation interrupt enable bit */
+#define FLASH_CR_CRCRDERRIE_Pos              (28U)
+#define FLASH_CR_CRCRDERRIE_Msk              (0x1UL << FLASH_CR_CRCRDERRIE_Pos) /*!< 0x10000000 */
+#define FLASH_CR_CRCRDERRIE                  FLASH_CR_CRCRDERRIE_Msk            /*!< CRC read error interrupt enable bit */
+
+/*******************  Bits definition for FLASH_SR register  ***********************/
+#define FLASH_SR_BSY_Pos                     (0U)
+#define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)       /*!< 0x00000001 */
+#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy flag */
+#define FLASH_SR_WBNE_Pos                    (1U)
+#define FLASH_SR_WBNE_Msk                    (0x1UL << FLASH_SR_WBNE_Pos)      /*!< 0x00000002 */
+#define FLASH_SR_WBNE                        FLASH_SR_WBNE_Msk                 /*!< Write buffer not empty flag */
+#define FLASH_SR_QW_Pos                      (2U)
+#define FLASH_SR_QW_Msk                      (0x1UL << FLASH_SR_QW_Pos)        /*!< 0x00000004 */
+#define FLASH_SR_QW                          FLASH_SR_QW_Msk                   /*!< Wait queue flag */
+#define FLASH_SR_CRC_BUSY_Pos                (3U)
+#define FLASH_SR_CRC_BUSY_Msk                (0x1UL << FLASH_SR_CRC_BUSY_Pos)  /*!< 0x00000008 */
+#define FLASH_SR_CRC_BUSY                    FLASH_SR_CRC_BUSY_Msk             /*!< CRC busy flag */
+#define FLASH_SR_EOP_Pos                     (16U)
+#define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)       /*!< 0x00010000 */
+#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End-of-program flag */
+#define FLASH_SR_WRPERR_Pos                  (17U)
+#define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)    /*!< 0x00020000 */
+#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protection error flag */
+#define FLASH_SR_PGSERR_Pos                  (18U)
+#define FLASH_SR_PGSERR_Msk                  (0x1UL << FLASH_SR_PGSERR_Pos)    /*!< 0x00040000 */
+#define FLASH_SR_PGSERR                      FLASH_SR_PGSERR_Msk               /*!< Programming sequence error flag */
+#define FLASH_SR_STRBERR_Pos                 (19U)
+#define FLASH_SR_STRBERR_Msk                 (0x1UL << FLASH_SR_STRBERR_Pos)   /*!< 0x00080000 */
+#define FLASH_SR_STRBERR                     FLASH_SR_STRBERR_Msk              /*!< Strobe error flag */
+#define FLASH_SR_INCERR_Pos                  (21U)
+#define FLASH_SR_INCERR_Msk                  (0x1UL << FLASH_SR_INCERR_Pos)    /*!< 0x00200000 */
+#define FLASH_SR_INCERR                      FLASH_SR_INCERR_Msk               /*!< Inconsistency error flag */
+#define FLASH_SR_OPERR_Pos                   (22U)
+#define FLASH_SR_OPERR_Msk                   (0x1UL << FLASH_SR_OPERR_Pos)     /*!< 0x00400000 */
+#define FLASH_SR_OPERR                       FLASH_SR_OPERR_Msk                /*!< Write/erase error flag */
+#define FLASH_SR_RDPERR_Pos                  (23U)
+#define FLASH_SR_RDPERR_Msk                  (0x1UL << FLASH_SR_RDPERR_Pos)    /*!< 0x00800000 */
+#define FLASH_SR_RDPERR                      FLASH_SR_RDPERR_Msk               /*!< Read protection error flag */
+#define FLASH_SR_RDSERR_Pos                  (24U)
+#define FLASH_SR_RDSERR_Msk                  (0x1UL << FLASH_SR_RDSERR_Pos)    /*!< 0x01000000 */
+#define FLASH_SR_RDSERR                      FLASH_SR_RDSERR_Msk               /*!< Secure error flag */
+#define FLASH_SR_SNECCERR_Pos                (25U)
+#define FLASH_SR_SNECCERR_Msk                (0x1UL << FLASH_SR_SNECCERR_Pos)  /*!< 0x02000000 */
+#define FLASH_SR_SNECCERR                    FLASH_SR_SNECCERR_Msk             /*!< Single correction error flag */
+#define FLASH_SR_DBECCERR_Pos                (26U)
+#define FLASH_SR_DBECCERR_Msk                (0x1UL << FLASH_SR_DBECCERR_Pos)  /*!< 0x04000000 */
+#define FLASH_SR_DBECCERR                    FLASH_SR_DBECCERR_Msk             /*!< ECC double detection error flag */
+#define FLASH_SR_CRCEND_Pos                  (27U)
+#define FLASH_SR_CRCEND_Msk                  (0x1UL << FLASH_SR_CRCEND_Pos)    /*!< 0x08000000 */
+#define FLASH_SR_CRCEND                      FLASH_SR_CRCEND_Msk               /*!< CRC end of calculation flag */
+#define FLASH_SR_CRCRDERR_Pos                (28U)
+#define FLASH_SR_CRCRDERR_Msk                (0x1UL << FLASH_SR_CRCRDERR_Pos)  /*!< 0x10000000 */
+#define FLASH_SR_CRCRDERR                    FLASH_SR_CRCRDERR_Msk             /*!< CRC read error flag */
+
+/*******************  Bits definition for FLASH_CCR register  *******************/
+#define FLASH_CCR_CLR_EOP_Pos                (16U)
+#define FLASH_CCR_CLR_EOP_Msk                (0x1UL << FLASH_CCR_CLR_EOP_Pos)  /*!< 0x00010000 */
+#define FLASH_CCR_CLR_EOP                    FLASH_CCR_CLR_EOP_Msk             /*!< EOP flag clear bit */
+#define FLASH_CCR_CLR_WRPERR_Pos             (17U)
+#define FLASH_CCR_CLR_WRPERR_Msk             (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */
+#define FLASH_CCR_CLR_WRPERR                 FLASH_CCR_CLR_WRPERR_Msk            /*!< WRPERR flag clear bit */
+#define FLASH_CCR_CLR_PGSERR_Pos             (18U)
+#define FLASH_CCR_CLR_PGSERR_Msk             (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */
+#define FLASH_CCR_CLR_PGSERR                 FLASH_CCR_CLR_PGSERR_Msk            /*!< PGSERR flag clear bit */
+#define FLASH_CCR_CLR_STRBERR_Pos            (19U)
+#define FLASH_CCR_CLR_STRBERR_Msk            (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */
+#define FLASH_CCR_CLR_STRBERR                FLASH_CCR_CLR_STRBERR_Msk            /*!< STRBERR flag clear bit */
+#define FLASH_CCR_CLR_INCERR_Pos             (21U)
+#define FLASH_CCR_CLR_INCERR_Msk             (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00200000 */
+#define FLASH_CCR_CLR_INCERR                 FLASH_CCR_CLR_INCERR_Msk            /*!< INCERR flag clear bit */
+#define FLASH_CCR_CLR_OPERR_Pos              (22U)
+#define FLASH_CCR_CLR_OPERR_Msk              (0x1UL << FLASH_CCR_CLR_OPERR_Pos) /*!< 0x00400000 */
+#define FLASH_CCR_CLR_OPERR                  FLASH_CCR_CLR_OPERR_Msk            /*!< OPERR flag clear bit */
+#define FLASH_CCR_CLR_RDPERR_Pos             (23U)
+#define FLASH_CCR_CLR_RDPERR_Msk             (0x1UL << FLASH_CCR_CLR_RDPERR_Pos) /*!< 0x00800000 */
+#define FLASH_CCR_CLR_RDPERR                 FLASH_CCR_CLR_RDPERR_Msk            /*!< RDPERR flag clear bit */
+#define FLASH_CCR_CLR_RDSERR_Pos             (24U)
+#define FLASH_CCR_CLR_RDSERR_Msk             (0x1UL << FLASH_CCR_CLR_RDSERR_Pos) /*!< 0x01000000 */
+#define FLASH_CCR_CLR_RDSERR                 FLASH_CCR_CLR_RDSERR_Msk            /*!< RDSERR flag clear bit */
+#define FLASH_CCR_CLR_SNECCERR_Pos           (25U)
+#define FLASH_CCR_CLR_SNECCERR_Msk           (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos) /*!< 0x02000000 */
+#define FLASH_CCR_CLR_SNECCERR               FLASH_CCR_CLR_SNECCERR_Msk            /*!< SNECCERR flag clear bit */
+#define FLASH_CCR_CLR_DBECCERR_Pos           (26U)
+#define FLASH_CCR_CLR_DBECCERR_Msk           (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos) /*!< 0x04000000 */
+#define FLASH_CCR_CLR_DBECCERR               FLASH_CCR_CLR_DBECCERR_Msk            /*!< DBECCERR flag clear bit */
+#define FLASH_CCR_CLR_CRCEND_Pos             (27U)
+#define FLASH_CCR_CLR_CRCEND_Msk             (0x1UL << FLASH_CCR_CLR_CRCEND_Pos) /*!< 0x08000000 */
+#define FLASH_CCR_CLR_CRCEND                 FLASH_CCR_CLR_CRCEND_Msk            /*!< CRCEND flag clear bit */
+#define FLASH_CCR_CLR_CRCRDERR_Pos           (28U)
+#define FLASH_CCR_CLR_CRCRDERR_Msk           (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos) /*!< 0x10000000 */
+#define FLASH_CCR_CLR_CRCRDERR               FLASH_CCR_CLR_CRCRDERR_Msk            /*!< CRCRDERR flag clear bit */
+
+/*******************  Bits definition for FLASH_OPTCR register  *******************/
+#define FLASH_OPTCR_OPTLOCK_Pos              (0U)
+#define FLASH_OPTCR_OPTLOCK_Msk              (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)  /*!< 0x00000001 */
+#define FLASH_OPTCR_OPTLOCK                  FLASH_OPTCR_OPTLOCK_Msk             /*!< FLASH_OPTCR lock option configuration bit */
+#define FLASH_OPTCR_OPTSTART_Pos             (1U)
+#define FLASH_OPTCR_OPTSTART_Msk             (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */
+#define FLASH_OPTCR_OPTSTART                 FLASH_OPTCR_OPTSTART_Msk            /*!< Option byte start change option configuration bit */
+#define FLASH_OPTCR_MER_Pos                  (4U)
+#define FLASH_OPTCR_MER_Msk                  (0x1UL << FLASH_OPTCR_MER_Pos)      /*!< 0x00000010 */
+#define FLASH_OPTCR_MER                      FLASH_OPTCR_MER_Msk                 /*!< Mass erase request */
+#define FLASH_OPTCR_OPTCHANGEERRIE_Pos       (30U)
+#define FLASH_OPTCR_OPTCHANGEERRIE_Msk       (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) /*!< 0x40000000 */
+#define FLASH_OPTCR_OPTCHANGEERRIE           FLASH_OPTCR_OPTCHANGEERRIE_Msk            /*!< Option byte change error interrupt enable bit */
+#define FLASH_OPTCR_SWAP_BANK_Pos            (31U)
+#define FLASH_OPTCR_SWAP_BANK_Msk            (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */
+#define FLASH_OPTCR_SWAP_BANK                FLASH_OPTCR_SWAP_BANK_Msk            /*!< Bank swapping option configuration bit */
+
+/*******************  Bits definition for FLASH_OPTSR register  ***************/
+#define FLASH_OPTSR_OPT_BUSY_Pos             (0U)
+#define FLASH_OPTSR_OPT_BUSY_Msk             (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos) /*!< 0x00000001 */
+#define FLASH_OPTSR_OPT_BUSY                 FLASH_OPTSR_OPT_BUSY_Msk            /*!< Option byte change ongoing flag */
+#define FLASH_OPTSR_BOR_LEV_Pos              (2U)
+#define FLASH_OPTSR_BOR_LEV_Msk              (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x0000000C */
+#define FLASH_OPTSR_BOR_LEV                  FLASH_OPTSR_BOR_LEV_Msk            /*!< Brownout level option status bit */
+#define FLASH_OPTSR_BOR_LEV_0                (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000004 */
+#define FLASH_OPTSR_BOR_LEV_1                (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000008 */
+#define FLASH_OPTSR_IWDG1_SW_Pos             (4U)
+#define FLASH_OPTSR_IWDG1_SW_Msk             (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos) /*!< 0x00000010 */
+#define FLASH_OPTSR_IWDG1_SW                 FLASH_OPTSR_IWDG1_SW_Msk            /*!< IWDG1 control mode option status bit */
+#define FLASH_OPTSR_NRST_STOP_D1_Pos         (6U)
+#define FLASH_OPTSR_NRST_STOP_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos) /*!< 0x00000040 */
+#define FLASH_OPTSR_NRST_STOP_D1             FLASH_OPTSR_NRST_STOP_D1_Msk            /*!< D1 domain DStop entry reset option status bit */
+#define FLASH_OPTSR_NRST_STBY_D1_Pos         (7U)
+#define FLASH_OPTSR_NRST_STBY_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos) /*!< 0x00000080 */
+#define FLASH_OPTSR_NRST_STBY_D1             FLASH_OPTSR_NRST_STBY_D1_Msk            /*!< D1 domain DStandby entry reset option status bit */
+#define FLASH_OPTSR_RDP_Pos                  (8U)
+#define FLASH_OPTSR_RDP_Msk                  (0xFFUL << FLASH_OPTSR_RDP_Pos)   /*!< 0x0000FF00 */
+#define FLASH_OPTSR_RDP                      FLASH_OPTSR_RDP_Msk               /*!< Readout protection level option status byte */
+#define FLASH_OPTSR_FZ_IWDG_STOP_Pos         (17U)
+#define FLASH_OPTSR_FZ_IWDG_STOP_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos) /*!< 0x00020000 */
+#define FLASH_OPTSR_FZ_IWDG_STOP             FLASH_OPTSR_FZ_IWDG_STOP_Msk            /*!< IWDG Stop mode freeze option status bit */
+#define FLASH_OPTSR_FZ_IWDG_SDBY_Pos         (18U)
+#define FLASH_OPTSR_FZ_IWDG_SDBY_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos) /*!< 0x00040000 */
+#define FLASH_OPTSR_FZ_IWDG_SDBY             FLASH_OPTSR_FZ_IWDG_SDBY_Msk            /*!< IWDG Standby mode freeze option status bit */
+#define FLASH_OPTSR_ST_RAM_SIZE_Pos          (19U)
+#define FLASH_OPTSR_ST_RAM_SIZE_Msk          (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00180000 */
+#define FLASH_OPTSR_ST_RAM_SIZE              FLASH_OPTSR_ST_RAM_SIZE_Msk            /*!< ST RAM size option status */
+#define FLASH_OPTSR_ST_RAM_SIZE_0            (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00080000 */
+#define FLASH_OPTSR_ST_RAM_SIZE_1            (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00100000 */
+#define FLASH_OPTSR_SECURITY_Pos             (21U)
+#define FLASH_OPTSR_SECURITY_Msk             (0x1UL << FLASH_OPTSR_SECURITY_Pos) /*!< 0x00200000 */
+#define FLASH_OPTSR_SECURITY                 FLASH_OPTSR_SECURITY_Msk            /*!< Security enable option status bit */
+#define FLASH_OPTSR_IO_HSLV_Pos              (29U)
+#define FLASH_OPTSR_IO_HSLV_Msk              (0x1UL << FLASH_OPTSR_IO_HSLV_Pos) /*!< 0x20000000 */
+#define FLASH_OPTSR_IO_HSLV                  FLASH_OPTSR_IO_HSLV_Msk            /*!< I/O high-speed at low-voltage status bit */
+#define FLASH_OPTSR_OPTCHANGEERR_Pos         (30U)
+#define FLASH_OPTSR_OPTCHANGEERR_Msk         (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) /*!< 0x40000000 */
+#define FLASH_OPTSR_OPTCHANGEERR             FLASH_OPTSR_OPTCHANGEERR_Msk            /*!< Option byte change error flag */
+#define FLASH_OPTSR_SWAP_BANK_OPT_Pos        (31U)
+#define FLASH_OPTSR_SWAP_BANK_OPT_Msk        (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos) /*!< 0x80000000 */
+#define FLASH_OPTSR_SWAP_BANK_OPT            FLASH_OPTSR_SWAP_BANK_OPT_Msk            /*!< Bank swapping option status bit */
+
+/*******************  Bits definition for FLASH_OPTCCR register  *******************/
+#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos    (30U)
+#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk    (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos) /*!< 0x40000000 */
+#define FLASH_OPTCCR_CLR_OPTCHANGEERR        FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk            /*!< OPTCHANGEERR reset bit */
+
+/*******************  Bits definition for FLASH_PRAR register  *********************/
+#define FLASH_PRAR_PROT_AREA_START_Pos       (0U)
+#define FLASH_PRAR_PROT_AREA_START_Msk       (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos) /*!< 0x00000FFF */
+#define FLASH_PRAR_PROT_AREA_START           FLASH_PRAR_PROT_AREA_START_Msk              /*!< PCROP area start status bits */
+#define FLASH_PRAR_PROT_AREA_END_Pos         (16U)
+#define FLASH_PRAR_PROT_AREA_END_Msk         (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos) /*!< 0x0FFF0000 */
+#define FLASH_PRAR_PROT_AREA_END             FLASH_PRAR_PROT_AREA_END_Msk              /*!< PCROP area end status bits */
+#define FLASH_PRAR_DMEP_Pos                  (31U)
+#define FLASH_PRAR_DMEP_Msk                  (0x1UL << FLASH_PRAR_DMEP_Pos)    /*!< 0x80000000 */
+#define FLASH_PRAR_DMEP                      FLASH_PRAR_DMEP_Msk               /*!< PCROP protected erase enable option status bit */
+
+/*******************  Bits definition for FLASH_SCAR register  *********************/
+#define FLASH_SCAR_SEC_AREA_START_Pos        (0U)
+#define FLASH_SCAR_SEC_AREA_START_Msk        (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos) /*!< 0x00000FFF */
+#define FLASH_SCAR_SEC_AREA_START            FLASH_SCAR_SEC_AREA_START_Msk              /*!< Secure-only area start status bits */
+#define FLASH_SCAR_SEC_AREA_END_Pos          (16U)
+#define FLASH_SCAR_SEC_AREA_END_Msk          (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos) /*!< 0x0FFF0000 */
+#define FLASH_SCAR_SEC_AREA_END              FLASH_SCAR_SEC_AREA_END_Msk              /*!< Secure-only area end status bits */
+#define FLASH_SCAR_DMES_Pos                  (31U)
+#define FLASH_SCAR_DMES_Msk                  (0x1UL << FLASH_SCAR_DMES_Pos)    /*!< 0x80000000 */
+#define FLASH_SCAR_DMES                      FLASH_SCAR_DMES_Msk               /*!< Secure access protected erase enable option status bit */
+
+/*******************  Bits definition for FLASH_WPSN register  *********************/
+#define FLASH_WPSN_WRPSN_Pos                 (0U)
+#define FLASH_WPSN_WRPSN_Msk                 (0xFFUL << FLASH_WPSN_WRPSN_Pos)  /*!< 0x000000FF */
+#define FLASH_WPSN_WRPSN                     FLASH_WPSN_WRPSN_Msk              /*!< Sector write protection option status byte */
+
+/*******************  Bits definition for FLASH_BOOT_CUR register  ****************/
+#define FLASH_BOOT_ADD0_Pos                  (0U)
+#define FLASH_BOOT_ADD0_Msk                  (0xFFFFUL << FLASH_BOOT_ADD0_Pos) /*!< 0x0000FFFF */
+#define FLASH_BOOT_ADD0                      FLASH_BOOT_ADD0_Msk               /*!< Arm Cortex-M7 boot address 0 */
+#define FLASH_BOOT_ADD1_Pos                  (16U)
+#define FLASH_BOOT_ADD1_Msk                  (0xFFFFUL << FLASH_BOOT_ADD1_Pos) /*!< 0xFFFF0000 */
+#define FLASH_BOOT_ADD1                      FLASH_BOOT_ADD1_Msk               /*!< Arm Cortex-M7 boot address 1 */
+
+
+/*******************  Bits definition for FLASH_CRCCR register  ********************/
+#define FLASH_CRCCR_CRC_SECT_Pos             (0U)
+#define FLASH_CRCCR_CRC_SECT_Msk             (0x7UL << FLASH_CRCCR_CRC_SECT_Pos) /*!< 0x00000007 */
+#define FLASH_CRCCR_CRC_SECT                 FLASH_CRCCR_CRC_SECT_Msk            /*!< CRC sector number */
+#define FLASH_CRCCR_CRC_BY_SECT_Pos          (8U)
+#define FLASH_CRCCR_CRC_BY_SECT_Msk          (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos) /*!< 0x00000100 */
+#define FLASH_CRCCR_CRC_BY_SECT              FLASH_CRCCR_CRC_BY_SECT_Msk            /*!< CRC sector mode select bit */
+#define FLASH_CRCCR_ADD_SECT_Pos             (9U)
+#define FLASH_CRCCR_ADD_SECT_Msk             (0x1UL << FLASH_CRCCR_ADD_SECT_Pos) /*!< 0x00000200 */
+#define FLASH_CRCCR_ADD_SECT                 FLASH_CRCCR_ADD_SECT_Msk            /*!< CRC sector select bit */
+#define FLASH_CRCCR_CLEAN_SECT_Pos           (10U)
+#define FLASH_CRCCR_CLEAN_SECT_Msk           (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos) /*!< 0x00000400 */
+#define FLASH_CRCCR_CLEAN_SECT               FLASH_CRCCR_CLEAN_SECT_Msk            /*!< CRC sector list clear bit */
+#define FLASH_CRCCR_START_CRC_Pos            (16U)
+#define FLASH_CRCCR_START_CRC_Msk            (0x1UL << FLASH_CRCCR_START_CRC_Pos) /*!< 0x00010000 */
+#define FLASH_CRCCR_START_CRC                FLASH_CRCCR_START_CRC_Msk            /*!< CRC start bit */
+#define FLASH_CRCCR_CLEAN_CRC_Pos            (17U)
+#define FLASH_CRCCR_CLEAN_CRC_Msk            (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos) /*!< 0x00020000 */
+#define FLASH_CRCCR_CLEAN_CRC                FLASH_CRCCR_CLEAN_CRC_Msk            /*!< CRC clear bit */
+#define FLASH_CRCCR_CRC_BURST_Pos            (20U)
+#define FLASH_CRCCR_CRC_BURST_Msk            (0x3UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00300000 */
+#define FLASH_CRCCR_CRC_BURST                FLASH_CRCCR_CRC_BURST_Msk            /*!< CRC burst size */
+#define FLASH_CRCCR_CRC_BURST_0              (0x1UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00100000 */
+#define FLASH_CRCCR_CRC_BURST_1              (0x2UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00200000 */
+#define FLASH_CRCCR_ALL_BANK_Pos             (22U)
+#define FLASH_CRCCR_ALL_BANK_Msk             (0x1UL << FLASH_CRCCR_ALL_BANK_Pos) /*!< 0x00400000 */
+#define FLASH_CRCCR_ALL_BANK                 FLASH_CRCCR_ALL_BANK_Msk            /*!< CRC select bit */
+
+/*******************  Bits definition for FLASH_CRCSADD register  ****************/
+#define FLASH_CRCSADD_CRC_START_ADDR_Pos     (0U)
+#define FLASH_CRCSADD_CRC_START_ADDR_Msk     (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_CRCSADD_CRC_START_ADDR         FLASH_CRCSADD_CRC_START_ADDR_Msk                   /*!< CRC start address */
+
+/*******************  Bits definition for FLASH_CRCEADD register  ****************/
+#define FLASH_CRCEADD_CRC_END_ADDR_Pos       (0U)
+#define FLASH_CRCEADD_CRC_END_ADDR_Msk       (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_CRCEADD_CRC_END_ADDR           FLASH_CRCEADD_CRC_END_ADDR_Msk                   /*!< CRC end address */
+
+/*******************  Bits definition for FLASH_CRCDATA register  ***************/
+#define FLASH_CRCDATA_CRC_DATA_Pos           (0U)
+#define FLASH_CRCDATA_CRC_DATA_Msk           (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_CRCDATA_CRC_DATA               FLASH_CRCDATA_CRC_DATA_Msk                   /*!< CRC result */
+
+/*******************  Bits definition for FLASH_ECC_FA register  *******************/
+#define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos       (0U)
+#define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk       (0x7FFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos) /*!< 0x00007FFF */
+#define FLASH_ECC_FA_FAIL_ECC_ADDR           FLASH_ECC_FA_FAIL_ECC_ADDR_Msk               /*!< ECC error address */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Flexible Memory Controller                        */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for FMC_BCR1 register  *******************/
+#define FMC_BCR1_CCLKEN_Pos        (20U)
+#define FMC_BCR1_CCLKEN_Msk        (0x1UL << FMC_BCR1_CCLKEN_Pos)              /*!< 0x00100000 */
+#define FMC_BCR1_CCLKEN            FMC_BCR1_CCLKEN_Msk                         /*!<Continous clock enable     */
+#define FMC_BCR1_WFDIS_Pos         (21U)
+#define FMC_BCR1_WFDIS_Msk         (0x1UL << FMC_BCR1_WFDIS_Pos)               /*!< 0x00200000 */
+#define FMC_BCR1_WFDIS             FMC_BCR1_WFDIS_Msk                          /*!<Write FIFO Disable         */
+
+#define FMC_BCR1_BMAP_Pos          (24U)
+#define FMC_BCR1_BMAP_Msk          (0x3UL << FMC_BCR1_BMAP_Pos)                /*!< 0x03000000 */
+#define FMC_BCR1_BMAP              FMC_BCR1_BMAP_Msk                           /*!<BMAP[1:0] FMC bank mapping */
+#define FMC_BCR1_BMAP_0            (0x1UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x01000000 */
+#define FMC_BCR1_BMAP_1            (0x2UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x02000000 */
+
+#define FMC_BCR1_FMCEN_Pos         (31U)
+#define FMC_BCR1_FMCEN_Msk         (0x1UL << FMC_BCR1_FMCEN_Pos)               /*!< 0x80000000 */
+#define FMC_BCR1_FMCEN             FMC_BCR1_FMCEN_Msk                          /*!<FMC controller Enable */
+/******************  Bit definition for FMC_BCRx registers (x=1..4)  *********/
+#define FMC_BCRx_MBKEN_Pos         (0U)
+#define FMC_BCRx_MBKEN_Msk         (0x1UL << FMC_BCRx_MBKEN_Pos)               /*!< 0x00000001 */
+#define FMC_BCRx_MBKEN             FMC_BCRx_MBKEN_Msk                          /*!<Memory bank enable bit                 */
+#define FMC_BCRx_MUXEN_Pos         (1U)
+#define FMC_BCRx_MUXEN_Msk         (0x1UL << FMC_BCRx_MUXEN_Pos)               /*!< 0x00000002 */
+#define FMC_BCRx_MUXEN             FMC_BCRx_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */
+
+#define FMC_BCRx_MTYP_Pos          (2U)
+#define FMC_BCRx_MTYP_Msk          (0x3UL << FMC_BCRx_MTYP_Pos)                /*!< 0x0000000C */
+#define FMC_BCRx_MTYP              FMC_BCRx_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */
+#define FMC_BCRx_MTYP_0            (0x1UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000004 */
+#define FMC_BCRx_MTYP_1            (0x2UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000008 */
+
+#define FMC_BCRx_MWID_Pos          (4U)
+#define FMC_BCRx_MWID_Msk          (0x3UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000030 */
+#define FMC_BCRx_MWID              FMC_BCRx_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCRx_MWID_0            (0x1UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000010 */
+#define FMC_BCRx_MWID_1            (0x2UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000020 */
+
+#define FMC_BCRx_FACCEN_Pos        (6U)
+#define FMC_BCRx_FACCEN_Msk        (0x1UL << FMC_BCRx_FACCEN_Pos)              /*!< 0x00000040 */
+#define FMC_BCRx_FACCEN            FMC_BCRx_FACCEN_Msk                         /*!<Flash access enable        */
+#define FMC_BCRx_BURSTEN_Pos       (8U)
+#define FMC_BCRx_BURSTEN_Msk       (0x1UL << FMC_BCRx_BURSTEN_Pos)             /*!< 0x00000100 */
+#define FMC_BCRx_BURSTEN           FMC_BCRx_BURSTEN_Msk                        /*!<Burst enable bit           */
+#define FMC_BCRx_WAITPOL_Pos       (9U)
+#define FMC_BCRx_WAITPOL_Msk       (0x1UL << FMC_BCRx_WAITPOL_Pos)             /*!< 0x00000200 */
+#define FMC_BCRx_WAITPOL           FMC_BCRx_WAITPOL_Msk                        /*!<Wait signal polarity bit   */
+#define FMC_BCRx_WAITCFG_Pos       (11U)
+#define FMC_BCRx_WAITCFG_Msk       (0x1UL << FMC_BCRx_WAITCFG_Pos)             /*!< 0x00000800 */
+#define FMC_BCRx_WAITCFG           FMC_BCRx_WAITCFG_Msk                        /*!<Wait timing configuration  */
+#define FMC_BCRx_WREN_Pos          (12U)
+#define FMC_BCRx_WREN_Msk          (0x1UL << FMC_BCRx_WREN_Pos)                /*!< 0x00001000 */
+#define FMC_BCRx_WREN              FMC_BCRx_WREN_Msk                           /*!<Write enable bit           */
+#define FMC_BCRx_WAITEN_Pos        (13U)
+#define FMC_BCRx_WAITEN_Msk        (0x1UL << FMC_BCRx_WAITEN_Pos)              /*!< 0x00002000 */
+#define FMC_BCRx_WAITEN            FMC_BCRx_WAITEN_Msk                         /*!<Wait enable bit            */
+#define FMC_BCRx_EXTMOD_Pos        (14U)
+#define FMC_BCRx_EXTMOD_Msk        (0x1UL << FMC_BCRx_EXTMOD_Pos)              /*!< 0x00004000 */
+#define FMC_BCRx_EXTMOD            FMC_BCRx_EXTMOD_Msk                         /*!<Extended mode enable       */
+#define FMC_BCRx_ASYNCWAIT_Pos     (15U)
+#define FMC_BCRx_ASYNCWAIT_Msk     (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)           /*!< 0x00008000 */
+#define FMC_BCRx_ASYNCWAIT         FMC_BCRx_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */
+
+#define FMC_BCRx_CPSIZE_Pos        (16U)
+#define FMC_BCRx_CPSIZE_Msk        (0x7UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00070000 */
+#define FMC_BCRx_CPSIZE            FMC_BCRx_CPSIZE_Msk                         /*!<PSIZE[2:0] bits CRAM Page Size */
+#define FMC_BCRx_CPSIZE_0          (0x1UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00010000 */
+#define FMC_BCRx_CPSIZE_1          (0x2UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00020000 */
+#define FMC_BCRx_CPSIZE_2          (0x4UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00040000 */
+
+#define FMC_BCRx_CBURSTRW_Pos      (19U)
+#define FMC_BCRx_CBURSTRW_Msk      (0x1UL << FMC_BCRx_CBURSTRW_Pos)            /*!< 0x00080000 */
+#define FMC_BCRx_CBURSTRW          FMC_BCRx_CBURSTRW_Msk                       /*!<Write burst enable         */
+
+/******************  Bit definition for FMC_BTRx registers (x=1..4)  *********/
+#define FMC_BTRx_ADDSET_Pos        (0U)
+#define FMC_BTRx_ADDSET_Msk        (0xFUL << FMC_BTRx_ADDSET_Pos)              /*!< 0x0000000F */
+#define FMC_BTRx_ADDSET            FMC_BTRx_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTRx_ADDSET_0          (0x1UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000001 */
+#define FMC_BTRx_ADDSET_1          (0x2UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000002 */
+#define FMC_BTRx_ADDSET_2          (0x4UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000004 */
+#define FMC_BTRx_ADDSET_3          (0x8UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000008 */
+
+#define FMC_BTRx_ADDHLD_Pos        (4U)
+#define FMC_BTRx_ADDHLD_Msk        (0xFUL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x000000F0 */
+#define FMC_BTRx_ADDHLD            FMC_BTRx_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
+#define FMC_BTRx_ADDHLD_0          (0x1UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000010 */
+#define FMC_BTRx_ADDHLD_1          (0x2UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000020 */
+#define FMC_BTRx_ADDHLD_2          (0x4UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000040 */
+#define FMC_BTRx_ADDHLD_3          (0x8UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000080 */
+
+#define FMC_BTRx_DATAST_Pos        (8U)
+#define FMC_BTRx_DATAST_Msk        (0xFFUL << FMC_BTRx_DATAST_Pos)             /*!< 0x0000FF00 */
+#define FMC_BTRx_DATAST            FMC_BTRx_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTRx_DATAST_0          (0x01UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000100 */
+#define FMC_BTRx_DATAST_1          (0x02UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000200 */
+#define FMC_BTRx_DATAST_2          (0x04UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000400 */
+#define FMC_BTRx_DATAST_3          (0x08UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000800 */
+#define FMC_BTRx_DATAST_4          (0x10UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00001000 */
+#define FMC_BTRx_DATAST_5          (0x20UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00002000 */
+#define FMC_BTRx_DATAST_6          (0x40UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00004000 */
+#define FMC_BTRx_DATAST_7          (0x80UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00008000 */
+
+#define FMC_BTRx_BUSTURN_Pos       (16U)
+#define FMC_BTRx_BUSTURN_Msk       (0xFUL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x000F0000 */
+#define FMC_BTRx_BUSTURN           FMC_BTRx_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTRx_BUSTURN_0         (0x1UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00010000 */
+#define FMC_BTRx_BUSTURN_1         (0x2UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00020000 */
+#define FMC_BTRx_BUSTURN_2         (0x4UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00040000 */
+#define FMC_BTRx_BUSTURN_3         (0x8UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00080000 */
+
+#define FMC_BTRx_CLKDIV_Pos        (20U)
+#define FMC_BTRx_CLKDIV_Msk        (0xFUL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00F00000 */
+#define FMC_BTRx_CLKDIV            FMC_BTRx_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTRx_CLKDIV_0          (0x1UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00100000 */
+#define FMC_BTRx_CLKDIV_1          (0x2UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00200000 */
+#define FMC_BTRx_CLKDIV_2          (0x4UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00400000 */
+#define FMC_BTRx_CLKDIV_3          (0x8UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00800000 */
+
+#define FMC_BTRx_DATLAT_Pos        (24U)
+#define FMC_BTRx_DATLAT_Msk        (0xFUL << FMC_BTRx_DATLAT_Pos)              /*!< 0x0F000000 */
+#define FMC_BTRx_DATLAT            FMC_BTRx_DATLAT_Msk                         /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTRx_DATLAT_0          (0x1UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x01000000 */
+#define FMC_BTRx_DATLAT_1          (0x2UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x02000000 */
+#define FMC_BTRx_DATLAT_2          (0x4UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x04000000 */
+#define FMC_BTRx_DATLAT_3          (0x8UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x08000000 */
+
+#define FMC_BTRx_ACCMOD_Pos        (28U)
+#define FMC_BTRx_ACCMOD_Msk        (0x3UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x30000000 */
+#define FMC_BTRx_ACCMOD            FMC_BTRx_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTRx_ACCMOD_0          (0x1UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x10000000 */
+#define FMC_BTRx_ACCMOD_1          (0x2UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x20000000 */
+
+/******************  Bit definition for FMC_BWTRx registers (x=1..4)  *********/
+#define FMC_BWTRx_ADDSET_Pos       (0U)
+#define FMC_BWTRx_ADDSET_Msk       (0xFUL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x0000000F */
+#define FMC_BWTRx_ADDSET           FMC_BWTRx_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTRx_ADDSET_0         (0x1UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000001 */
+#define FMC_BWTRx_ADDSET_1         (0x2UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000002 */
+#define FMC_BWTRx_ADDSET_2         (0x4UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000004 */
+#define FMC_BWTRx_ADDSET_3         (0x8UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000008 */
+
+#define FMC_BWTRx_ADDHLD_Pos       (4U)
+#define FMC_BWTRx_ADDHLD_Msk       (0xFUL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x000000F0 */
+#define FMC_BWTRx_ADDHLD           FMC_BWTRx_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTRx_ADDHLD_0         (0x1UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000010 */
+#define FMC_BWTRx_ADDHLD_1         (0x2UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000020 */
+#define FMC_BWTRx_ADDHLD_2         (0x4UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000040 */
+#define FMC_BWTRx_ADDHLD_3         (0x8UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000080 */
+
+#define FMC_BWTRx_DATAST_Pos       (8U)
+#define FMC_BWTRx_DATAST_Msk       (0xFFUL << FMC_BWTRx_DATAST_Pos)            /*!< 0x0000FF00 */
+#define FMC_BWTRx_DATAST           FMC_BWTRx_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTRx_DATAST_0         (0x01UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000100 */
+#define FMC_BWTRx_DATAST_1         (0x02UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000200 */
+#define FMC_BWTRx_DATAST_2         (0x04UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000400 */
+#define FMC_BWTRx_DATAST_3         (0x08UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000800 */
+#define FMC_BWTRx_DATAST_4         (0x10UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00001000 */
+#define FMC_BWTRx_DATAST_5         (0x20UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00002000 */
+#define FMC_BWTRx_DATAST_6         (0x40UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00004000 */
+#define FMC_BWTRx_DATAST_7         (0x80UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00008000 */
+
+#define FMC_BWTRx_BUSTURN_Pos      (16U)
+#define FMC_BWTRx_BUSTURN_Msk      (0xFUL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x000F0000 */
+#define FMC_BWTRx_BUSTURN          FMC_BWTRx_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BWTRx_BUSTURN_0        (0x1UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00010000 */
+#define FMC_BWTRx_BUSTURN_1        (0x2UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00020000 */
+#define FMC_BWTRx_BUSTURN_2        (0x4UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00040000 */
+#define FMC_BWTRx_BUSTURN_3        (0x8UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00080000 */
+
+#define FMC_BWTRx_ACCMOD_Pos       (28U)
+#define FMC_BWTRx_ACCMOD_Msk       (0x3UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x30000000 */
+#define FMC_BWTRx_ACCMOD           FMC_BWTRx_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTRx_ACCMOD_0         (0x1UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x10000000 */
+#define FMC_BWTRx_ACCMOD_1         (0x2UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x20000000 */
+
+/******************  Bit definition for FMC_PCR register  *******************/
+#define FMC_PCR_PWAITEN_Pos        (1U)
+#define FMC_PCR_PWAITEN_Msk        (0x1UL << FMC_PCR_PWAITEN_Pos)              /*!< 0x00000002 */
+#define FMC_PCR_PWAITEN            FMC_PCR_PWAITEN_Msk                         /*!<Wait feature enable bit                   */
+#define FMC_PCR_PBKEN_Pos          (2U)
+#define FMC_PCR_PBKEN_Msk          (0x1UL << FMC_PCR_PBKEN_Pos)                /*!< 0x00000004 */
+#define FMC_PCR_PBKEN              FMC_PCR_PBKEN_Msk                           /*!<NAND Flash memory bank enable bit */
+
+#define FMC_PCR_PWID_Pos           (4U)
+#define FMC_PCR_PWID_Msk           (0x3UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000030 */
+#define FMC_PCR_PWID               FMC_PCR_PWID_Msk                            /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR_PWID_0             (0x1UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000010 */
+#define FMC_PCR_PWID_1             (0x2UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000020 */
+
+#define FMC_PCR_ECCEN_Pos          (6U)
+#define FMC_PCR_ECCEN_Msk          (0x1UL << FMC_PCR_ECCEN_Pos)                /*!< 0x00000040 */
+#define FMC_PCR_ECCEN              FMC_PCR_ECCEN_Msk                           /*!<ECC computation logic enable bit          */
+
+#define FMC_PCR_TCLR_Pos           (9U)
+#define FMC_PCR_TCLR_Msk           (0xFUL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001E00 */
+#define FMC_PCR_TCLR               FMC_PCR_TCLR_Msk                            /*!<TCLR[3:0] bits (CLE to RE delay)          */
+#define FMC_PCR_TCLR_0             (0x1UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000200 */
+#define FMC_PCR_TCLR_1             (0x2UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000400 */
+#define FMC_PCR_TCLR_2             (0x4UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000800 */
+#define FMC_PCR_TCLR_3             (0x8UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00001000 */
+
+#define FMC_PCR_TAR_Pos            (13U)
+#define FMC_PCR_TAR_Msk            (0xFUL << FMC_PCR_TAR_Pos)                  /*!< 0x0001E000 */
+#define FMC_PCR_TAR                FMC_PCR_TAR_Msk                             /*!<TAR[3:0] bits (ALE to RE delay)           */
+#define FMC_PCR_TAR_0              (0x1UL << FMC_PCR_TAR_Pos)                   /*!< 0x00002000 */
+#define FMC_PCR_TAR_1              (0x2UL << FMC_PCR_TAR_Pos)                   /*!< 0x00004000 */
+#define FMC_PCR_TAR_2              (0x4UL << FMC_PCR_TAR_Pos)                   /*!< 0x00008000 */
+#define FMC_PCR_TAR_3              (0x8UL << FMC_PCR_TAR_Pos)                   /*!< 0x00010000 */
+
+#define FMC_PCR_ECCPS_Pos          (17U)
+#define FMC_PCR_ECCPS_Msk          (0x7UL << FMC_PCR_ECCPS_Pos)                /*!< 0x000E0000 */
+#define FMC_PCR_ECCPS              FMC_PCR_ECCPS_Msk                           /*!<ECCPS[1:0] bits (ECC page size)           */
+#define FMC_PCR_ECCPS_0            (0x1UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00020000 */
+#define FMC_PCR_ECCPS_1            (0x2UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00040000 */
+#define FMC_PCR_ECCPS_2            (0x4UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00080000 */
+
+/*******************  Bit definition for FMC_SR register  *******************/
+#define FMC_SR_IRS_Pos             (0U)
+#define FMC_SR_IRS_Msk             (0x1UL << FMC_SR_IRS_Pos)                   /*!< 0x00000001 */
+#define FMC_SR_IRS                 FMC_SR_IRS_Msk                              /*!<Interrupt Rising Edge status                */
+#define FMC_SR_ILS_Pos             (1U)
+#define FMC_SR_ILS_Msk             (0x1UL << FMC_SR_ILS_Pos)                   /*!< 0x00000002 */
+#define FMC_SR_ILS                 FMC_SR_ILS_Msk                              /*!<Interrupt Level status                      */
+#define FMC_SR_IFS_Pos             (2U)
+#define FMC_SR_IFS_Msk             (0x1UL << FMC_SR_IFS_Pos)                   /*!< 0x00000004 */
+#define FMC_SR_IFS                 FMC_SR_IFS_Msk                              /*!<Interrupt Falling Edge status               */
+#define FMC_SR_IREN_Pos            (3U)
+#define FMC_SR_IREN_Msk            (0x1UL << FMC_SR_IREN_Pos)                  /*!< 0x00000008 */
+#define FMC_SR_IREN                FMC_SR_IREN_Msk                             /*!<Interrupt Rising Edge detection Enable bit  */
+#define FMC_SR_ILEN_Pos            (4U)
+#define FMC_SR_ILEN_Msk            (0x1UL << FMC_SR_ILEN_Pos)                  /*!< 0x00000010 */
+#define FMC_SR_ILEN                FMC_SR_ILEN_Msk                             /*!<Interrupt Level detection Enable bit        */
+#define FMC_SR_IFEN_Pos            (5U)
+#define FMC_SR_IFEN_Msk            (0x1UL << FMC_SR_IFEN_Pos)                  /*!< 0x00000020 */
+#define FMC_SR_IFEN                FMC_SR_IFEN_Msk                             /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR_FEMPT_Pos           (6U)
+#define FMC_SR_FEMPT_Msk           (0x1UL << FMC_SR_FEMPT_Pos)                 /*!< 0x00000040 */
+#define FMC_SR_FEMPT               FMC_SR_FEMPT_Msk                            /*!<FIFO empty                                  */
+
+/******************  Bit definition for FMC_PMEM register  ******************/
+#define FMC_PMEM_MEMSET_Pos       (0U)
+#define FMC_PMEM_MEMSET_Msk       (0xFFUL << FMC_PMEM_MEMSET_Pos)            /*!< 0x000000FF */
+#define FMC_PMEM_MEMSET           FMC_PMEM_MEMSET_Msk                        /*!<MEMSET[7:0] bits (Common memory setup time) */
+#define FMC_PMEM_MEMSET_0         (0x01UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000001 */
+#define FMC_PMEM_MEMSET_1         (0x02UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000002 */
+#define FMC_PMEM_MEMSET_2         (0x04UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000004 */
+#define FMC_PMEM_MEMSET_3         (0x08UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000008 */
+#define FMC_PMEM_MEMSET_4         (0x10UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000010 */
+#define FMC_PMEM_MEMSET_5         (0x20UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000020 */
+#define FMC_PMEM_MEMSET_6         (0x40UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000040 */
+#define FMC_PMEM_MEMSET_7         (0x80UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000080 */
+
+#define FMC_PMEM_MEMWAIT_Pos      (8U)
+#define FMC_PMEM_MEMWAIT_Msk      (0xFFUL << FMC_PMEM_MEMWAIT_Pos)           /*!< 0x0000FF00 */
+#define FMC_PMEM_MEMWAIT          FMC_PMEM_MEMWAIT_Msk                       /*!<MEMWAIT[7:0] bits (Common memory wait time) */
+#define FMC_PMEM_MEMWAIT_0        (0x01UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000100 */
+#define FMC_PMEM_MEMWAIT_1        (0x02UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000200 */
+#define FMC_PMEM_MEMWAIT_2        (0x04UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000400 */
+#define FMC_PMEM_MEMWAIT_3        (0x08UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000800 */
+#define FMC_PMEM_MEMWAIT_4        (0x10UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00001000 */
+#define FMC_PMEM_MEMWAIT_5        (0x20UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00002000 */
+#define FMC_PMEM_MEMWAIT_6        (0x40UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00004000 */
+#define FMC_PMEM_MEMWAIT_7        (0x80UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00008000 */
+
+#define FMC_PMEM_MEMHOLD_Pos      (16U)
+#define FMC_PMEM_MEMHOLD_Msk      (0xFFUL << FMC_PMEM_MEMHOLD_Pos)           /*!< 0x00FF0000 */
+#define FMC_PMEM_MEMHOLD          FMC_PMEM_MEMHOLD_Msk                       /*!<MEMHOLD[7:0] bits (Common memory hold time) */
+#define FMC_PMEM_MEMHOLD_0        (0x01UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00010000 */
+#define FMC_PMEM_MEMHOLD_1        (0x02UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00020000 */
+#define FMC_PMEM_MEMHOLD_2        (0x04UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00040000 */
+#define FMC_PMEM_MEMHOLD_3        (0x08UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00080000 */
+#define FMC_PMEM_MEMHOLD_4        (0x10UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00100000 */
+#define FMC_PMEM_MEMHOLD_5        (0x20UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00200000 */
+#define FMC_PMEM_MEMHOLD_6        (0x40UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00400000 */
+#define FMC_PMEM_MEMHOLD_7        (0x80UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00800000 */
+
+#define FMC_PMEM_MEMHIZ_Pos       (24U)
+#define FMC_PMEM_MEMHIZ_Msk       (0xFFUL << FMC_PMEM_MEMHIZ_Pos)            /*!< 0xFF000000 */
+#define FMC_PMEM_MEMHIZ           FMC_PMEM_MEMHIZ_Msk                        /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */
+#define FMC_PMEM_MEMHIZ_0         (0x01UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x01000000 */
+#define FMC_PMEM_MEMHIZ_1         (0x02UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x02000000 */
+#define FMC_PMEM_MEMHIZ_2         (0x04UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x04000000 */
+#define FMC_PMEM_MEMHIZ_3         (0x08UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x08000000 */
+#define FMC_PMEM_MEMHIZ_4         (0x10UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x10000000 */
+#define FMC_PMEM_MEMHIZ_5         (0x20UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x20000000 */
+#define FMC_PMEM_MEMHIZ_6         (0x40UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x40000000 */
+#define FMC_PMEM_MEMHIZ_7         (0x80UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_PATT register  ******************/
+#define FMC_PATT_ATTSET_Pos       (0U)
+#define FMC_PATT_ATTSET_Msk       (0xFFUL << FMC_PATT_ATTSET_Pos)            /*!< 0x000000FF */
+#define FMC_PATT_ATTSET           FMC_PATT_ATTSET_Msk                        /*!<ATTSET[7:0] bits (Attribute memory setup time) */
+#define FMC_PATT_ATTSET_0         (0x01UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000001 */
+#define FMC_PATT_ATTSET_1         (0x02UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000002 */
+#define FMC_PATT_ATTSET_2         (0x04UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000004 */
+#define FMC_PATT_ATTSET_3         (0x08UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000008 */
+#define FMC_PATT_ATTSET_4         (0x10UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000010 */
+#define FMC_PATT_ATTSET_5         (0x20UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000020 */
+#define FMC_PATT_ATTSET_6         (0x40UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000040 */
+#define FMC_PATT_ATTSET_7         (0x80UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000080 */
+
+#define FMC_PATT_ATTWAIT_Pos      (8U)
+#define FMC_PATT_ATTWAIT_Msk      (0xFFUL << FMC_PATT_ATTWAIT_Pos)           /*!< 0x0000FF00 */
+#define FMC_PATT_ATTWAIT          FMC_PATT_ATTWAIT_Msk                       /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */
+#define FMC_PATT_ATTWAIT_0        (0x01UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000100 */
+#define FMC_PATT_ATTWAIT_1        (0x02UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000200 */
+#define FMC_PATT_ATTWAIT_2        (0x04UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000400 */
+#define FMC_PATT_ATTWAIT_3        (0x08UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000800 */
+#define FMC_PATT_ATTWAIT_4        (0x10UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00001000 */
+#define FMC_PATT_ATTWAIT_5        (0x20UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00002000 */
+#define FMC_PATT_ATTWAIT_6        (0x40UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00004000 */
+#define FMC_PATT_ATTWAIT_7        (0x80UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00008000 */
+
+#define FMC_PATT_ATTHOLD_Pos      (16U)
+#define FMC_PATT_ATTHOLD_Msk      (0xFFUL << FMC_PATT_ATTHOLD_Pos)           /*!< 0x00FF0000 */
+#define FMC_PATT_ATTHOLD          FMC_PATT_ATTHOLD_Msk                       /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */
+#define FMC_PATT_ATTHOLD_0        (0x01UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00010000 */
+#define FMC_PATT_ATTHOLD_1        (0x02UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00020000 */
+#define FMC_PATT_ATTHOLD_2        (0x04UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00040000 */
+#define FMC_PATT_ATTHOLD_3        (0x08UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00080000 */
+#define FMC_PATT_ATTHOLD_4        (0x10UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00100000 */
+#define FMC_PATT_ATTHOLD_5        (0x20UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00200000 */
+#define FMC_PATT_ATTHOLD_6        (0x40UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00400000 */
+#define FMC_PATT_ATTHOLD_7        (0x80UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00800000 */
+
+#define FMC_PATT_ATTHIZ_Pos       (24U)
+#define FMC_PATT_ATTHIZ_Msk       (0xFFUL << FMC_PATT_ATTHIZ_Pos)            /*!< 0xFF000000 */
+#define FMC_PATT_ATTHIZ           FMC_PATT_ATTHIZ_Msk                        /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */
+#define FMC_PATT_ATTHIZ_0         (0x01UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x01000000 */
+#define FMC_PATT_ATTHIZ_1         (0x02UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x02000000 */
+#define FMC_PATT_ATTHIZ_2         (0x04UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x04000000 */
+#define FMC_PATT_ATTHIZ_3         (0x08UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x08000000 */
+#define FMC_PATT_ATTHIZ_4         (0x10UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x10000000 */
+#define FMC_PATT_ATTHIZ_5         (0x20UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x20000000 */
+#define FMC_PATT_ATTHIZ_6         (0x40UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x40000000 */
+#define FMC_PATT_ATTHIZ_7         (0x80UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_ECCR3 register  ******************/
+#define FMC_ECCR3_ECC3_Pos         (0U)
+#define FMC_ECCR3_ECC3_Msk         (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos)        /*!< 0xFFFFFFFF */
+#define FMC_ECCR3_ECC3             FMC_ECCR3_ECC3_Msk                          /*!<ECC result */
+
+/******************  Bit definition for FMC_SDCRx registers (x=1..4)  *********/
+#define FMC_SDCRx_NC_Pos           (0U)
+#define FMC_SDCRx_NC_Msk           (0x3UL << FMC_SDCRx_NC_Pos)                 /*!< 0x00000003 */
+#define FMC_SDCRx_NC               FMC_SDCRx_NC_Msk                            /*!<NC[1:0] bits (Number of column bits) */
+#define FMC_SDCRx_NC_0             (0x1UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000001 */
+#define FMC_SDCRx_NC_1             (0x2UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000002 */
+
+#define FMC_SDCRx_NR_Pos           (2U)
+#define FMC_SDCRx_NR_Msk           (0x3UL << FMC_SDCRx_NR_Pos)                 /*!< 0x0000000C */
+#define FMC_SDCRx_NR               FMC_SDCRx_NR_Msk                            /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCRx_NR_0             (0x1UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000004 */
+#define FMC_SDCRx_NR_1             (0x2UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000008 */
+
+#define FMC_SDCRx_MWID_Pos         (4U)
+#define FMC_SDCRx_MWID_Msk         (0x3UL << FMC_SDCRx_MWID_Pos)               /*!< 0x00000030 */
+#define FMC_SDCRx_MWID             FMC_SDCRx_MWID_Msk                          /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCRx_MWID_0           (0x1UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000010 */
+#define FMC_SDCRx_MWID_1           (0x2UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000020 */
+
+#define FMC_SDCRx_NB_Pos           (6U)
+#define FMC_SDCRx_NB_Msk           (0x1UL << FMC_SDCRx_NB_Pos)                 /*!< 0x00000040 */
+#define FMC_SDCRx_NB               FMC_SDCRx_NB_Msk                            /*!<Number of internal bank */
+
+#define FMC_SDCRx_CAS_Pos          (7U)
+#define FMC_SDCRx_CAS_Msk          (0x3UL << FMC_SDCRx_CAS_Pos)                /*!< 0x00000180 */
+#define FMC_SDCRx_CAS              FMC_SDCRx_CAS_Msk                           /*!<CAS[1:0] bits (CAS latency) */
+#define FMC_SDCRx_CAS_0            (0x1UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000080 */
+#define FMC_SDCRx_CAS_1            (0x2UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000100 */
+
+#define FMC_SDCRx_WP_Pos           (9U)
+#define FMC_SDCRx_WP_Msk           (0x1UL << FMC_SDCRx_WP_Pos)                 /*!< 0x00000200 */
+#define FMC_SDCRx_WP               FMC_SDCRx_WP_Msk                            /*!<Write protection */
+
+#define FMC_SDCRx_SDCLK_Pos        (10U)
+#define FMC_SDCRx_SDCLK_Msk        (0x3UL << FMC_SDCRx_SDCLK_Pos)              /*!< 0x00000C00 */
+#define FMC_SDCRx_SDCLK            FMC_SDCRx_SDCLK_Msk                         /*!<SDRAM clock configuration */
+#define FMC_SDCRx_SDCLK_0          (0x1UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000400 */
+#define FMC_SDCRx_SDCLK_1          (0x2UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000800 */
+
+#define FMC_SDCRx_RBURST_Pos       (12U)
+#define FMC_SDCRx_RBURST_Msk       (0x1UL << FMC_SDCRx_RBURST_Pos)             /*!< 0x00001000 */
+#define FMC_SDCRx_RBURST           FMC_SDCRx_RBURST_Msk                        /*!<Read burst */
+
+#define FMC_SDCRx_RPIPE_Pos        (13U)
+#define FMC_SDCRx_RPIPE_Msk        (0x3UL << FMC_SDCRx_RPIPE_Pos)              /*!< 0x00006000 */
+#define FMC_SDCRx_RPIPE            FMC_SDCRx_RPIPE_Msk                         /*!<Write protection */
+#define FMC_SDCRx_RPIPE_0          (0x1UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00002000 */
+#define FMC_SDCRx_RPIPE_1          (0x2UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00004000 */
+
+/******************  Bit definition for FMC_SDTRx(1,2) register  ******************/
+#define FMC_SDTRx_TMRD_Pos         (0U)
+#define FMC_SDTRx_TMRD_Msk         (0xFUL << FMC_SDTRx_TMRD_Pos)               /*!< 0x0000000F */
+#define FMC_SDTRx_TMRD             FMC_SDTRx_TMRD_Msk                          /*!<TMRD[3:0] bits (Load mode register to active) */
+#define FMC_SDTRx_TMRD_0           (0x1UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000001 */
+#define FMC_SDTRx_TMRD_1           (0x2UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000002 */
+#define FMC_SDTRx_TMRD_2           (0x4UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000004 */
+#define FMC_SDTRx_TMRD_3           (0x8UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000008 */
+
+#define FMC_SDTRx_TXSR_Pos         (4U)
+#define FMC_SDTRx_TXSR_Msk         (0xFUL << FMC_SDTRx_TXSR_Pos)               /*!< 0x000000F0 */
+#define FMC_SDTRx_TXSR             FMC_SDTRx_TXSR_Msk                          /*!<TXSR[3:0] bits (Exit self refresh) */
+#define FMC_SDTRx_TXSR_0           (0x1UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000010 */
+#define FMC_SDTRx_TXSR_1           (0x2UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000020 */
+#define FMC_SDTRx_TXSR_2           (0x4UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000040 */
+#define FMC_SDTRx_TXSR_3           (0x8UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000080 */
+
+#define FMC_SDTRx_TRAS_Pos         (8U)
+#define FMC_SDTRx_TRAS_Msk         (0xFUL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000F00 */
+#define FMC_SDTRx_TRAS             FMC_SDTRx_TRAS_Msk                          /*!<TRAS[3:0] bits (Self refresh time) */
+#define FMC_SDTRx_TRAS_0           (0x1UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000100 */
+#define FMC_SDTRx_TRAS_1           (0x2UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000200 */
+#define FMC_SDTRx_TRAS_2           (0x4UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000400 */
+#define FMC_SDTRx_TRAS_3           (0x8UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000800 */
+
+#define FMC_SDTRx_TRC_Pos          (12U)
+#define FMC_SDTRx_TRC_Msk          (0xFUL << FMC_SDTRx_TRC_Pos)                /*!< 0x0000F000 */
+#define FMC_SDTRx_TRC              FMC_SDTRx_TRC_Msk                           /*!<TRC[2:0] bits (Row cycle delay) */
+#define FMC_SDTRx_TRC_0            (0x1UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00001000 */
+#define FMC_SDTRx_TRC_1            (0x2UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00002000 */
+#define FMC_SDTRx_TRC_2            (0x4UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00004000 */
+
+#define FMC_SDTRx_TWR_Pos          (16U)
+#define FMC_SDTRx_TWR_Msk          (0xFUL << FMC_SDTRx_TWR_Pos)                /*!< 0x000F0000 */
+#define FMC_SDTRx_TWR              FMC_SDTRx_TWR_Msk                           /*!<TRC[2:0] bits (Write recovery delay) */
+#define FMC_SDTRx_TWR_0            (0x1UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00010000 */
+#define FMC_SDTRx_TWR_1            (0x2UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00020000 */
+#define FMC_SDTRx_TWR_2            (0x4UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00040000 */
+
+#define FMC_SDTRx_TRP_Pos          (20U)
+#define FMC_SDTRx_TRP_Msk          (0xFUL << FMC_SDTRx_TRP_Pos)                /*!< 0x00F00000 */
+#define FMC_SDTRx_TRP              FMC_SDTRx_TRP_Msk                           /*!<TRP[2:0] bits (Row precharge delay) */
+#define FMC_SDTRx_TRP_0            (0x1UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00100000 */
+#define FMC_SDTRx_TRP_1            (0x2UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00200000 */
+#define FMC_SDTRx_TRP_2            (0x4UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00400000 */
+
+#define FMC_SDTRx_TRCD_Pos         (24U)
+#define FMC_SDTRx_TRCD_Msk         (0xFUL << FMC_SDTRx_TRCD_Pos)               /*!< 0x0F000000 */
+#define FMC_SDTRx_TRCD             FMC_SDTRx_TRCD_Msk                          /*!<TRP[2:0] bits (Row to column delay) */
+#define FMC_SDTRx_TRCD_0           (0x1UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x01000000 */
+#define FMC_SDTRx_TRCD_1           (0x2UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x02000000 */
+#define FMC_SDTRx_TRCD_2           (0x4UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x04000000 */
+
+/******************  Bit definition for FMC_SDCMR register  ******************/
+#define FMC_SDCMR_MODE_Pos         (0U)
+#define FMC_SDCMR_MODE_Msk         (0x7UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000007 */
+#define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */
+#define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */
+#define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */
+#define FMC_SDCMR_MODE_2           (0x3UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000003 */
+
+#define FMC_SDCMR_CTB2_Pos         (3U)
+#define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */
+#define FMC_SDCMR_CTB2             FMC_SDCMR_CTB2_Msk                          /*!<Command target 2 */
+
+#define FMC_SDCMR_CTB1_Pos         (4U)
+#define FMC_SDCMR_CTB1_Msk         (0x1UL << FMC_SDCMR_CTB1_Pos)               /*!< 0x00000010 */
+#define FMC_SDCMR_CTB1             FMC_SDCMR_CTB1_Msk                          /*!<Command target 1 */
+
+#define FMC_SDCMR_NRFS_Pos         (5U)
+#define FMC_SDCMR_NRFS_Msk         (0xFUL << FMC_SDCMR_NRFS_Pos)               /*!< 0x000001E0 */
+#define FMC_SDCMR_NRFS             FMC_SDCMR_NRFS_Msk                          /*!<NRFS[3:0] bits (Number of auto-refresh) */
+#define FMC_SDCMR_NRFS_0           (0x1UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000020 */
+#define FMC_SDCMR_NRFS_1           (0x2UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000040 */
+#define FMC_SDCMR_NRFS_2           (0x4UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000080 */
+#define FMC_SDCMR_NRFS_3           (0x8UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000100 */
+
+#define FMC_SDCMR_MRD_Pos          (9U)
+#define FMC_SDCMR_MRD_Msk          (0x1FFFUL << FMC_SDCMR_MRD_Pos)             /*!< 0x003FFE00 */
+#define FMC_SDCMR_MRD              FMC_SDCMR_MRD_Msk                           /*!<MRD[12:0] bits (Mode register definition) */
+
+/******************  Bit definition for FMC_SDRTR register  ******************/
+#define FMC_SDRTR_CRE_Pos          (0U)
+#define FMC_SDRTR_CRE_Msk          (0x1UL << FMC_SDRTR_CRE_Pos)                /*!< 0x00000001 */
+#define FMC_SDRTR_CRE              FMC_SDRTR_CRE_Msk                           /*!<Clear refresh error flag */
+
+#define FMC_SDRTR_COUNT_Pos        (1U)
+#define FMC_SDRTR_COUNT_Msk        (0x1FFFUL << FMC_SDRTR_COUNT_Pos)           /*!< 0x00003FFE */
+#define FMC_SDRTR_COUNT            FMC_SDRTR_COUNT_Msk                         /*!<COUNT[12:0] bits (Refresh timer count) */
+
+#define FMC_SDRTR_REIE_Pos         (14U)
+#define FMC_SDRTR_REIE_Msk         (0x1UL << FMC_SDRTR_REIE_Pos)               /*!< 0x00004000 */
+#define FMC_SDRTR_REIE             FMC_SDRTR_REIE_Msk                          /*!<RES interupt enable */
+
+/******************  Bit definition for FMC_SDSR register  ******************/
+#define FMC_SDSR_RE_Pos            (0U)
+#define FMC_SDSR_RE_Msk            (0x1UL << FMC_SDSR_RE_Pos)                  /*!< 0x00000001 */
+#define FMC_SDSR_RE                FMC_SDSR_RE_Msk                             /*!<Refresh error flag */
+
+#define FMC_SDSR_MODES1_Pos        (1U)
+#define FMC_SDSR_MODES1_Msk        (0x3UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000006 */
+#define FMC_SDSR_MODES1            FMC_SDSR_MODES1_Msk                         /*!<MODES1[1:0]bits (Status mode for bank 1) */
+#define FMC_SDSR_MODES1_0          (0x1UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000002 */
+#define FMC_SDSR_MODES1_1          (0x2UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000004 */
+
+#define FMC_SDSR_MODES2_Pos        (3U)
+#define FMC_SDSR_MODES2_Msk        (0x3UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000018 */
+#define FMC_SDSR_MODES2            FMC_SDSR_MODES2_Msk                         /*!<MODES2[1:0]bits (Status mode for bank 2) */
+#define FMC_SDSR_MODES2_0          (0x1UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000008 */
+#define FMC_SDSR_MODES2_1          (0x2UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000010 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            General Purpose I/O                             */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bits definition for GPIO_MODER register  *****************/
+#define GPIO_MODER_MODE0_Pos           (0U)
+#define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
+#define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000002 */
+
+#define GPIO_MODER_MODE1_Pos           (2U)
+#define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
+#define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000008 */
+
+#define GPIO_MODER_MODE2_Pos           (4U)
+#define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
+#define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000020 */
+
+#define GPIO_MODER_MODE3_Pos           (6U)
+#define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000080 */
+
+#define GPIO_MODER_MODE4_Pos           (8U)
+#define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
+#define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000200 */
+
+#define GPIO_MODER_MODE5_Pos           (10U)
+#define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000800 */
+
+#define GPIO_MODER_MODE6_Pos           (12U)
+#define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
+#define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00002000 */
+
+#define GPIO_MODER_MODE7_Pos           (14U)
+#define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00008000 */
+
+#define GPIO_MODER_MODE8_Pos           (16U)
+#define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
+#define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00020000 */
+
+#define GPIO_MODER_MODE9_Pos           (18U)
+#define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00080000 */
+
+#define GPIO_MODER_MODE10_Pos          (20U)
+#define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
+#define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00200000 */
+
+#define GPIO_MODER_MODE11_Pos          (22U)
+#define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00800000 */
+
+#define GPIO_MODER_MODE12_Pos          (24U)
+#define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
+#define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)         /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)         /*!< 0x02000000 */
+
+#define GPIO_MODER_MODE13_Pos          (26U)
+#define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)         /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)         /*!< 0x08000000 */
+
+#define GPIO_MODER_MODE14_Pos          (28U)
+#define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
+#define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)         /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)         /*!< 0x20000000 */
+
+#define GPIO_MODER_MODE15_Pos          (30U)
+#define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)         /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)         /*!< 0x80000000 */
+
+/******************  Bits definition for GPIO_OTYPER register  ****************/
+#define GPIO_OTYPER_OT0_Pos            (0U)
+#define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */
+#define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk
+#define GPIO_OTYPER_OT1_Pos            (1U)
+#define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */
+#define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk
+#define GPIO_OTYPER_OT2_Pos            (2U)
+#define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */
+#define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk
+#define GPIO_OTYPER_OT3_Pos            (3U)
+#define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */
+#define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk
+#define GPIO_OTYPER_OT4_Pos            (4U)
+#define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */
+#define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk
+#define GPIO_OTYPER_OT5_Pos            (5U)
+#define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */
+#define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk
+#define GPIO_OTYPER_OT6_Pos            (6U)
+#define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */
+#define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk
+#define GPIO_OTYPER_OT7_Pos            (7U)
+#define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */
+#define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk
+#define GPIO_OTYPER_OT8_Pos            (8U)
+#define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */
+#define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk
+#define GPIO_OTYPER_OT9_Pos            (9U)
+#define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */
+#define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk
+#define GPIO_OTYPER_OT10_Pos           (10U)
+#define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */
+#define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk
+#define GPIO_OTYPER_OT11_Pos           (11U)
+#define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */
+#define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk
+#define GPIO_OTYPER_OT12_Pos           (12U)
+#define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */
+#define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk
+#define GPIO_OTYPER_OT13_Pos           (13U)
+#define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */
+#define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk
+#define GPIO_OTYPER_OT14_Pos           (14U)
+#define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */
+#define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk
+#define GPIO_OTYPER_OT15_Pos           (15U)
+#define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */
+#define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk
+
+/******************  Bits definition for GPIO_OSPEEDR register  ***************/
+#define GPIO_OSPEEDR_OSPEED0_Pos       (0U)
+#define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */
+#define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk
+#define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000001 */
+#define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000002 */
+
+#define GPIO_OSPEEDR_OSPEED1_Pos       (2U)
+#define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */
+#define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk
+#define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000004 */
+#define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000008 */
+
+#define GPIO_OSPEEDR_OSPEED2_Pos       (4U)
+#define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */
+#define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk
+#define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000010 */
+#define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000020 */
+
+#define GPIO_OSPEEDR_OSPEED3_Pos       (6U)
+#define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */
+#define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk
+#define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000040 */
+#define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000080 */
+
+#define GPIO_OSPEEDR_OSPEED4_Pos       (8U)
+#define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */
+#define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk
+#define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000100 */
+#define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000200 */
+
+#define GPIO_OSPEEDR_OSPEED5_Pos       (10U)
+#define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */
+#define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk
+#define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000400 */
+#define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000800 */
+
+#define GPIO_OSPEEDR_OSPEED6_Pos       (12U)
+#define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */
+#define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk
+#define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00001000 */
+#define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00002000 */
+
+#define GPIO_OSPEEDR_OSPEED7_Pos       (14U)
+#define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */
+#define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk
+#define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00004000 */
+#define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00008000 */
+
+#define GPIO_OSPEEDR_OSPEED8_Pos       (16U)
+#define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */
+#define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk
+#define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00010000 */
+#define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00020000 */
+
+#define GPIO_OSPEEDR_OSPEED9_Pos       (18U)
+#define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */
+#define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk
+#define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00040000 */
+#define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00080000 */
+
+#define GPIO_OSPEEDR_OSPEED10_Pos      (20U)
+#define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */
+#define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk
+#define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00100000 */
+#define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00200000 */
+
+#define GPIO_OSPEEDR_OSPEED11_Pos      (22U)
+#define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */
+#define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk
+#define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00400000 */
+#define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00800000 */
+
+#define GPIO_OSPEEDR_OSPEED12_Pos      (24U)
+#define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */
+#define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk
+#define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x01000000 */
+#define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x02000000 */
+
+#define GPIO_OSPEEDR_OSPEED13_Pos      (26U)
+#define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */
+#define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk
+#define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x04000000 */
+#define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x08000000 */
+
+#define GPIO_OSPEEDR_OSPEED14_Pos      (28U)
+#define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */
+#define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk
+#define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x10000000 */
+#define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x20000000 */
+
+#define GPIO_OSPEEDR_OSPEED15_Pos      (30U)
+#define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */
+#define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk
+#define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x40000000 */
+#define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x80000000 */
+
+/******************  Bits definition for GPIO_PUPDR register  *****************/
+#define GPIO_PUPDR_PUPD0_Pos           (0U)
+#define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000002 */
+
+#define GPIO_PUPDR_PUPD1_Pos           (2U)
+#define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000008 */
+
+#define GPIO_PUPDR_PUPD2_Pos           (4U)
+#define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000020 */
+
+#define GPIO_PUPDR_PUPD3_Pos           (6U)
+#define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000080 */
+
+#define GPIO_PUPDR_PUPD4_Pos           (8U)
+#define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000200 */
+
+#define GPIO_PUPDR_PUPD5_Pos           (10U)
+#define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000800 */
+
+#define GPIO_PUPDR_PUPD6_Pos           (12U)
+#define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00002000 */
+
+#define GPIO_PUPDR_PUPD7_Pos           (14U)
+#define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00008000 */
+
+#define GPIO_PUPDR_PUPD8_Pos           (16U)
+#define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00020000 */
+
+#define GPIO_PUPDR_PUPD9_Pos           (18U)
+#define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00080000 */
+
+#define GPIO_PUPDR_PUPD10_Pos          (20U)
+#define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00200000 */
+
+#define GPIO_PUPDR_PUPD11_Pos          (22U)
+#define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00800000 */
+
+#define GPIO_PUPDR_PUPD12_Pos          (24U)
+#define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x02000000 */
+
+#define GPIO_PUPDR_PUPD13_Pos          (26U)
+#define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x08000000 */
+
+#define GPIO_PUPDR_PUPD14_Pos          (28U)
+#define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x20000000 */
+
+#define GPIO_PUPDR_PUPD15_Pos          (30U)
+#define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x80000000 */
+
+/******************  Bits definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_ID0_Pos               (0U)
+#define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
+#define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos               (1U)
+#define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
+#define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos               (2U)
+#define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
+#define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos               (3U)
+#define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
+#define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos               (4U)
+#define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
+#define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos               (5U)
+#define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
+#define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos               (6U)
+#define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
+#define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos               (7U)
+#define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
+#define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos               (8U)
+#define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
+#define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos               (9U)
+#define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
+#define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos              (10U)
+#define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
+#define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos              (11U)
+#define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
+#define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos              (12U)
+#define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
+#define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos              (13U)
+#define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
+#define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos              (14U)
+#define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
+#define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos              (15U)
+#define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
+#define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk
+
+/******************  Bits definition for GPIO_ODR register  *******************/
+#define GPIO_ODR_OD0_Pos               (0U)
+#define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
+#define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos               (1U)
+#define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
+#define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos               (2U)
+#define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
+#define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos               (3U)
+#define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
+#define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos               (4U)
+#define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
+#define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos               (5U)
+#define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
+#define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos               (6U)
+#define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
+#define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos               (7U)
+#define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
+#define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos               (8U)
+#define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
+#define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos               (9U)
+#define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
+#define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos              (10U)
+#define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
+#define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos              (11U)
+#define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
+#define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos              (12U)
+#define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
+#define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos              (13U)
+#define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
+#define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos              (14U)
+#define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
+#define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos              (15U)
+#define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
+#define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk
+
+/******************  Bits definition for GPIO_BSRR register  ******************/
+#define GPIO_BSRR_BS0_Pos              (0U)
+#define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */
+#define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk
+#define GPIO_BSRR_BS1_Pos              (1U)
+#define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */
+#define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk
+#define GPIO_BSRR_BS2_Pos              (2U)
+#define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */
+#define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk
+#define GPIO_BSRR_BS3_Pos              (3U)
+#define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */
+#define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk
+#define GPIO_BSRR_BS4_Pos              (4U)
+#define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */
+#define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk
+#define GPIO_BSRR_BS5_Pos              (5U)
+#define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */
+#define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk
+#define GPIO_BSRR_BS6_Pos              (6U)
+#define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */
+#define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk
+#define GPIO_BSRR_BS7_Pos              (7U)
+#define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */
+#define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk
+#define GPIO_BSRR_BS8_Pos              (8U)
+#define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */
+#define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk
+#define GPIO_BSRR_BS9_Pos              (9U)
+#define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */
+#define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk
+#define GPIO_BSRR_BS10_Pos             (10U)
+#define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */
+#define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk
+#define GPIO_BSRR_BS11_Pos             (11U)
+#define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */
+#define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk
+#define GPIO_BSRR_BS12_Pos             (12U)
+#define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */
+#define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk
+#define GPIO_BSRR_BS13_Pos             (13U)
+#define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */
+#define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk
+#define GPIO_BSRR_BS14_Pos             (14U)
+#define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */
+#define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk
+#define GPIO_BSRR_BS15_Pos             (15U)
+#define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */
+#define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk
+#define GPIO_BSRR_BR0_Pos              (16U)
+#define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */
+#define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk
+#define GPIO_BSRR_BR1_Pos              (17U)
+#define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */
+#define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk
+#define GPIO_BSRR_BR2_Pos              (18U)
+#define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */
+#define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk
+#define GPIO_BSRR_BR3_Pos              (19U)
+#define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */
+#define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk
+#define GPIO_BSRR_BR4_Pos              (20U)
+#define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */
+#define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk
+#define GPIO_BSRR_BR5_Pos              (21U)
+#define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */
+#define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk
+#define GPIO_BSRR_BR6_Pos              (22U)
+#define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */
+#define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk
+#define GPIO_BSRR_BR7_Pos              (23U)
+#define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */
+#define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk
+#define GPIO_BSRR_BR8_Pos              (24U)
+#define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */
+#define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk
+#define GPIO_BSRR_BR9_Pos              (25U)
+#define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */
+#define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk
+#define GPIO_BSRR_BR10_Pos             (26U)
+#define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */
+#define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk
+#define GPIO_BSRR_BR11_Pos             (27U)
+#define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */
+#define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk
+#define GPIO_BSRR_BR12_Pos             (28U)
+#define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */
+#define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk
+#define GPIO_BSRR_BR13_Pos             (29U)
+#define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */
+#define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk
+#define GPIO_BSRR_BR14_Pos             (30U)
+#define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */
+#define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk
+#define GPIO_BSRR_BR15_Pos             (31U)
+#define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */
+#define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0_Pos             (0U)
+#define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos             (1U)
+#define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos             (2U)
+#define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos             (3U)
+#define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos             (4U)
+#define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos             (5U)
+#define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos             (6U)
+#define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos             (7U)
+#define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos             (8U)
+#define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos             (9U)
+#define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos            (10U)
+#define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos            (11U)
+#define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos            (12U)
+#define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos            (13U)
+#define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos            (14U)
+#define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos            (15U)
+#define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos             (16U)
+#define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk
+
+/****************** Bit definition for GPIO_AFRL register  ********************/
+#define GPIO_AFRL_AFSEL0_Pos           (0U)
+#define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000001 */
+#define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000002 */
+#define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000004 */
+#define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000008 */
+#define GPIO_AFRL_AFSEL1_Pos           (4U)
+#define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000010 */
+#define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000020 */
+#define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000040 */
+#define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000080 */
+#define GPIO_AFRL_AFSEL2_Pos           (8U)
+#define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000100 */
+#define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000200 */
+#define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000400 */
+#define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000800 */
+#define GPIO_AFRL_AFSEL3_Pos           (12U)
+#define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00001000 */
+#define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00002000 */
+#define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00004000 */
+#define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00008000 */
+#define GPIO_AFRL_AFSEL4_Pos           (16U)
+#define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00010000 */
+#define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00020000 */
+#define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00040000 */
+#define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00080000 */
+#define GPIO_AFRL_AFSEL5_Pos           (20U)
+#define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00100000 */
+#define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00200000 */
+#define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00400000 */
+#define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00800000 */
+#define GPIO_AFRL_AFSEL6_Pos           (24U)
+#define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x01000000 */
+#define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x02000000 */
+#define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x04000000 */
+#define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x08000000 */
+#define GPIO_AFRL_AFSEL7_Pos           (28U)
+#define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk
+#define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x10000000 */
+#define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x20000000 */
+#define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x40000000 */
+#define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0
+#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1
+#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2
+#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3
+#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4
+#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5
+#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6
+#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7
+
+/****************** Bit definition for GPIO_AFRH register  ********************/
+#define GPIO_AFRH_AFSEL8_Pos           (0U)
+#define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000001 */
+#define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000002 */
+#define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000004 */
+#define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000008 */
+#define GPIO_AFRH_AFSEL9_Pos           (4U)
+#define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000010 */
+#define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000020 */
+#define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000040 */
+#define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000080 */
+#define GPIO_AFRH_AFSEL10_Pos          (8U)
+#define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000100 */
+#define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000200 */
+#define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000400 */
+#define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000800 */
+#define GPIO_AFRH_AFSEL11_Pos          (12U)
+#define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00001000 */
+#define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00002000 */
+#define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00004000 */
+#define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00008000 */
+#define GPIO_AFRH_AFSEL12_Pos          (16U)
+#define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00010000 */
+#define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00020000 */
+#define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00040000 */
+#define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00080000 */
+#define GPIO_AFRH_AFSEL13_Pos          (20U)
+#define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00100000 */
+#define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00200000 */
+#define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00400000 */
+#define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00800000 */
+#define GPIO_AFRH_AFSEL14_Pos          (24U)
+#define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x01000000 */
+#define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x02000000 */
+#define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x04000000 */
+#define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x08000000 */
+#define GPIO_AFRH_AFSEL15_Pos          (28U)
+#define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk
+#define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x10000000 */
+#define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x20000000 */
+#define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x40000000 */
+#define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8
+#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9
+#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10
+#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11
+#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12
+#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13
+#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14
+#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15
+
+/******************************************************************************/
+/*                                                                            */
+/*                        HSEM HW Semaphore                                   */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for HSEM_R register  ********************/
+#define HSEM_R_PROCID_Pos         (0U)
+#define HSEM_R_PROCID_Msk         (0xFFUL << HSEM_R_PROCID_Pos)                /*!< 0x000000FF */
+#define HSEM_R_PROCID             HSEM_R_PROCID_Msk                            /*!<Semaphore ProcessID */
+#define HSEM_R_COREID_Pos         (8U)
+#define HSEM_R_COREID_Msk         (0xFFUL << HSEM_R_COREID_Pos)                /*!< 0x0000FF00 */
+#define HSEM_R_COREID             HSEM_R_COREID_Msk                            /*!<Semaphore CoreID.   */
+#define HSEM_R_LOCK_Pos           (31U)
+#define HSEM_R_LOCK_Msk           (0x1UL << HSEM_R_LOCK_Pos)                   /*!< 0x80000000 */
+#define HSEM_R_LOCK               HSEM_R_LOCK_Msk                              /*!<Lock indication.    */
+
+/********************  Bit definition for HSEM_RLR register  ******************/
+#define HSEM_RLR_PROCID_Pos       (0U)
+#define HSEM_RLR_PROCID_Msk       (0xFFUL << HSEM_RLR_PROCID_Pos)              /*!< 0x000000FF */
+#define HSEM_RLR_PROCID           HSEM_RLR_PROCID_Msk                          /*!<Semaphore ProcessID */
+#define HSEM_RLR_COREID_Pos       (8U)
+#define HSEM_RLR_COREID_Msk       (0xFFUL << HSEM_RLR_COREID_Pos)              /*!< 0x0000FF00 */
+#define HSEM_RLR_COREID           HSEM_RLR_COREID_Msk                          /*!<Semaphore CoreID.   */
+#define HSEM_RLR_LOCK_Pos         (31U)
+#define HSEM_RLR_LOCK_Msk         (0x1UL << HSEM_RLR_LOCK_Pos)                 /*!< 0x80000000 */
+#define HSEM_RLR_LOCK             HSEM_RLR_LOCK_Msk                            /*!<Lock indication.    */
+
+/********************  Bit definition for HSEM_C1IER register  *****************/
+#define HSEM_C1IER_ISE0_Pos       (0U)
+#define HSEM_C1IER_ISE0_Msk       (0x1UL << HSEM_C1IER_ISE0_Pos)               /*!< 0x00000001 */
+#define HSEM_C1IER_ISE0           HSEM_C1IER_ISE0_Msk                          /*!<semaphore 0 , interrupt 0 enable bit.  */
+#define HSEM_C1IER_ISE1_Pos       (1U)
+#define HSEM_C1IER_ISE1_Msk       (0x1UL << HSEM_C1IER_ISE1_Pos)               /*!< 0x00000002 */
+#define HSEM_C1IER_ISE1           HSEM_C1IER_ISE1_Msk                          /*!<semaphore 1 , interrupt 0 enable bit.  */
+#define HSEM_C1IER_ISE2_Pos       (2U)
+#define HSEM_C1IER_ISE2_Msk       (0x1UL << HSEM_C1IER_ISE2_Pos)               /*!< 0x00000004 */
+#define HSEM_C1IER_ISE2           HSEM_C1IER_ISE2_Msk                          /*!<semaphore 2 , interrupt 0 enable bit.  */
+#define HSEM_C1IER_ISE3_Pos       (3U)
+#define HSEM_C1IER_ISE3_Msk       (0x1UL << HSEM_C1IER_ISE3_Pos)               /*!< 0x00000008 */
+#define HSEM_C1IER_ISE3           HSEM_C1IER_ISE3_Msk                          /*!<semaphore 3 , interrupt 0 enable bit.  */
+#define HSEM_C1IER_ISE4_Pos       (4U)
+#define HSEM_C1IER_ISE4_Msk       (0x1UL << HSEM_C1IER_ISE4_Pos)               /*!< 0x00000010 */
+#define HSEM_C1IER_ISE4           HSEM_C1IER_ISE4_Msk                          /*!<semaphore 4 , interrupt 0 enable bit.  */
+#define HSEM_C1IER_ISE5_Pos       (5U)
+#define HSEM_C1IER_ISE5_Msk       (0x1UL << HSEM_C1IER_ISE5_Pos)               /*!< 0x00000020 */
+#define HSEM_C1IER_ISE5           HSEM_C1IER_ISE5_Msk                          /*!<semaphore 5 interrupt 0 enable bit.    */
+#define HSEM_C1IER_ISE6_Pos       (6U)
+#define HSEM_C1IER_ISE6_Msk       (0x1UL << HSEM_C1IER_ISE6_Pos)               /*!< 0x00000040 */
+#define HSEM_C1IER_ISE6           HSEM_C1IER_ISE6_Msk                          /*!<semaphore 6 interrupt 0 enable bit.    */
+#define HSEM_C1IER_ISE7_Pos       (7U)
+#define HSEM_C1IER_ISE7_Msk       (0x1UL << HSEM_C1IER_ISE7_Pos)               /*!< 0x00000080 */
+#define HSEM_C1IER_ISE7           HSEM_C1IER_ISE7_Msk                          /*!<semaphore 7 interrupt 0 enable bit.    */
+#define HSEM_C1IER_ISE8_Pos       (8U)
+#define HSEM_C1IER_ISE8_Msk       (0x1UL << HSEM_C1IER_ISE8_Pos)               /*!< 0x00000100 */
+#define HSEM_C1IER_ISE8           HSEM_C1IER_ISE8_Msk                          /*!<semaphore 8 interrupt 0 enable bit.    */
+#define HSEM_C1IER_ISE9_Pos       (9U)
+#define HSEM_C1IER_ISE9_Msk       (0x1UL << HSEM_C1IER_ISE9_Pos)               /*!< 0x00000200 */
+#define HSEM_C1IER_ISE9           HSEM_C1IER_ISE9_Msk                          /*!<semaphore 9 interrupt 0 enable bit.    */
+#define HSEM_C1IER_ISE10_Pos      (10U)
+#define HSEM_C1IER_ISE10_Msk      (0x1UL << HSEM_C1IER_ISE10_Pos)              /*!< 0x00000400 */
+#define HSEM_C1IER_ISE10          HSEM_C1IER_ISE10_Msk                         /*!<semaphore 10 interrupt 0 enable bit.   */
+#define HSEM_C1IER_ISE11_Pos      (11U)
+#define HSEM_C1IER_ISE11_Msk      (0x1UL << HSEM_C1IER_ISE11_Pos)              /*!< 0x00000800 */
+#define HSEM_C1IER_ISE11          HSEM_C1IER_ISE11_Msk                         /*!<semaphore 11 interrupt 0 enable bit.   */
+#define HSEM_C1IER_ISE12_Pos      (12U)
+#define HSEM_C1IER_ISE12_Msk      (0x1UL << HSEM_C1IER_ISE12_Pos)              /*!< 0x00001000 */
+#define HSEM_C1IER_ISE12          HSEM_C1IER_ISE12_Msk                         /*!<semaphore 12 interrupt 0 enable bit.   */
+#define HSEM_C1IER_ISE13_Pos      (13U)
+#define HSEM_C1IER_ISE13_Msk      (0x1UL << HSEM_C1IER_ISE13_Pos)              /*!< 0x00002000 */
+#define HSEM_C1IER_ISE13          HSEM_C1IER_ISE13_Msk                         /*!<semaphore 13 interrupt 0 enable bit.   */
+#define HSEM_C1IER_ISE14_Pos      (14U)
+#define HSEM_C1IER_ISE14_Msk      (0x1UL << HSEM_C1IER_ISE14_Pos)              /*!< 0x00004000 */
+#define HSEM_C1IER_ISE14          HSEM_C1IER_ISE14_Msk                         /*!<semaphore 14 interrupt 0 enable bit.   */
+#define HSEM_C1IER_ISE15_Pos      (15U)
+#define HSEM_C1IER_ISE15_Msk      (0x1UL << HSEM_C1IER_ISE15_Pos)              /*!< 0x00008000 */
+#define HSEM_C1IER_ISE15          HSEM_C1IER_ISE15_Msk                         /*!<semaphore 15 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE16_Pos      (16U)
+#define HSEM_C1IER_ISE16_Msk      (0x1UL << HSEM_C1IER_ISE16_Pos)              /*!< 0x00010000 */
+#define HSEM_C1IER_ISE16          HSEM_C1IER_ISE16_Msk                         /*!<semaphore 16 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE17_Pos      (17U)
+#define HSEM_C1IER_ISE17_Msk      (0x1UL << HSEM_C1IER_ISE17_Pos)              /*!< 0x00020000 */
+#define HSEM_C1IER_ISE17          HSEM_C1IER_ISE17_Msk                         /*!<semaphore 17 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE18_Pos      (18U)
+#define HSEM_C1IER_ISE18_Msk      (0x1UL << HSEM_C1IER_ISE18_Pos)              /*!< 0x00040000 */
+#define HSEM_C1IER_ISE18          HSEM_C1IER_ISE18_Msk                         /*!<semaphore 18 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE19_Pos      (19U)
+#define HSEM_C1IER_ISE19_Msk      (0x1UL << HSEM_C1IER_ISE19_Pos)              /*!< 0x00080000 */
+#define HSEM_C1IER_ISE19          HSEM_C1IER_ISE19_Msk                         /*!<semaphore 19 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE20_Pos      (20U)
+#define HSEM_C1IER_ISE20_Msk      (0x1UL << HSEM_C1IER_ISE20_Pos)              /*!< 0x00100000 */
+#define HSEM_C1IER_ISE20          HSEM_C1IER_ISE20_Msk                         /*!<semaphore 20 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE21_Pos      (21U)
+#define HSEM_C1IER_ISE21_Msk      (0x1UL << HSEM_C1IER_ISE21_Pos)              /*!< 0x00200000 */
+#define HSEM_C1IER_ISE21          HSEM_C1IER_ISE21_Msk                         /*!<semaphore 21 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE22_Pos      (22U)
+#define HSEM_C1IER_ISE22_Msk      (0x1UL << HSEM_C1IER_ISE22_Pos)              /*!< 0x00400000 */
+#define HSEM_C1IER_ISE22          HSEM_C1IER_ISE22_Msk                         /*!<semaphore 22 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE23_Pos      (23U)
+#define HSEM_C1IER_ISE23_Msk      (0x1UL << HSEM_C1IER_ISE23_Pos)              /*!< 0x00800000 */
+#define HSEM_C1IER_ISE23          HSEM_C1IER_ISE23_Msk                         /*!<semaphore 23 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE24_Pos      (24U)
+#define HSEM_C1IER_ISE24_Msk      (0x1UL << HSEM_C1IER_ISE24_Pos)              /*!< 0x01000000 */
+#define HSEM_C1IER_ISE24          HSEM_C1IER_ISE24_Msk                         /*!<semaphore 24 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE25_Pos      (25U)
+#define HSEM_C1IER_ISE25_Msk      (0x1UL << HSEM_C1IER_ISE25_Pos)              /*!< 0x02000000 */
+#define HSEM_C1IER_ISE25          HSEM_C1IER_ISE25_Msk                         /*!<semaphore 25 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE26_Pos      (26U)
+#define HSEM_C1IER_ISE26_Msk      (0x1UL << HSEM_C1IER_ISE26_Pos)              /*!< 0x04000000 */
+#define HSEM_C1IER_ISE26          HSEM_C1IER_ISE26_Msk                         /*!<semaphore 26 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE27_Pos      (27U)
+#define HSEM_C1IER_ISE27_Msk      (0x1UL << HSEM_C1IER_ISE27_Pos)              /*!< 0x08000000 */
+#define HSEM_C1IER_ISE27          HSEM_C1IER_ISE27_Msk                         /*!<semaphore 27 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE28_Pos      (28U)
+#define HSEM_C1IER_ISE28_Msk      (0x1UL << HSEM_C1IER_ISE28_Pos)              /*!< 0x10000000 */
+#define HSEM_C1IER_ISE28          HSEM_C1IER_ISE28_Msk                         /*!<semaphore 28 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE29_Pos      (29U)
+#define HSEM_C1IER_ISE29_Msk      (0x1UL << HSEM_C1IER_ISE29_Pos)              /*!< 0x20000000 */
+#define HSEM_C1IER_ISE29          HSEM_C1IER_ISE29_Msk                         /*!<semaphore 29 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE30_Pos      (30U)
+#define HSEM_C1IER_ISE30_Msk      (0x1UL << HSEM_C1IER_ISE30_Pos)              /*!< 0x40000000 */
+#define HSEM_C1IER_ISE30          HSEM_C1IER_ISE30_Msk                         /*!<semaphore 30 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE31_Pos      (31U)
+#define HSEM_C1IER_ISE31_Msk      (0x1UL << HSEM_C1IER_ISE31_Pos)              /*!< 0x80000000 */
+#define HSEM_C1IER_ISE31          HSEM_C1IER_ISE31_Msk                         /*!<semaphore 31 interrupt 0 enable bit. */
+
+/********************  Bit definition for HSEM_C1ICR register  *****************/
+#define HSEM_C1ICR_ISC0_Pos       (0U)
+#define HSEM_C1ICR_ISC0_Msk       (0x1UL << HSEM_C1ICR_ISC0_Pos)               /*!< 0x00000001 */
+#define HSEM_C1ICR_ISC0           HSEM_C1ICR_ISC0_Msk                          /*!<semaphore 0 , interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC1_Pos       (1U)
+#define HSEM_C1ICR_ISC1_Msk       (0x1UL << HSEM_C1ICR_ISC1_Pos)               /*!< 0x00000002 */
+#define HSEM_C1ICR_ISC1           HSEM_C1ICR_ISC1_Msk                          /*!<semaphore 1 , interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC2_Pos       (2U)
+#define HSEM_C1ICR_ISC2_Msk       (0x1UL << HSEM_C1ICR_ISC2_Pos)               /*!< 0x00000004 */
+#define HSEM_C1ICR_ISC2           HSEM_C1ICR_ISC2_Msk                          /*!<semaphore 2 , interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC3_Pos       (3U)
+#define HSEM_C1ICR_ISC3_Msk       (0x1UL << HSEM_C1ICR_ISC3_Pos)               /*!< 0x00000008 */
+#define HSEM_C1ICR_ISC3           HSEM_C1ICR_ISC3_Msk                          /*!<semaphore 3 , interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC4_Pos       (4U)
+#define HSEM_C1ICR_ISC4_Msk       (0x1UL << HSEM_C1ICR_ISC4_Pos)               /*!< 0x00000010 */
+#define HSEM_C1ICR_ISC4           HSEM_C1ICR_ISC4_Msk                          /*!<semaphore 4 , interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC5_Pos       (5U)
+#define HSEM_C1ICR_ISC5_Msk       (0x1UL << HSEM_C1ICR_ISC5_Pos)               /*!< 0x00000020 */
+#define HSEM_C1ICR_ISC5           HSEM_C1ICR_ISC5_Msk                          /*!<semaphore 5 interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC6_Pos       (6U)
+#define HSEM_C1ICR_ISC6_Msk       (0x1UL << HSEM_C1ICR_ISC6_Pos)               /*!< 0x00000040 */
+#define HSEM_C1ICR_ISC6           HSEM_C1ICR_ISC6_Msk                          /*!<semaphore 6 interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC7_Pos       (7U)
+#define HSEM_C1ICR_ISC7_Msk       (0x1UL << HSEM_C1ICR_ISC7_Pos)               /*!< 0x00000080 */
+#define HSEM_C1ICR_ISC7           HSEM_C1ICR_ISC7_Msk                          /*!<semaphore 7 interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC8_Pos       (8U)
+#define HSEM_C1ICR_ISC8_Msk       (0x1UL << HSEM_C1ICR_ISC8_Pos)               /*!< 0x00000100 */
+#define HSEM_C1ICR_ISC8           HSEM_C1ICR_ISC8_Msk                          /*!<semaphore 8 interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC9_Pos       (9U)
+#define HSEM_C1ICR_ISC9_Msk       (0x1UL << HSEM_C1ICR_ISC9_Pos)               /*!< 0x00000200 */
+#define HSEM_C1ICR_ISC9           HSEM_C1ICR_ISC9_Msk                          /*!<semaphore 9 interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC10_Pos      (10U)
+#define HSEM_C1ICR_ISC10_Msk      (0x1UL << HSEM_C1ICR_ISC10_Pos)              /*!< 0x00000400 */
+#define HSEM_C1ICR_ISC10          HSEM_C1ICR_ISC10_Msk                         /*!<semaphore 10 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC11_Pos      (11U)
+#define HSEM_C1ICR_ISC11_Msk      (0x1UL << HSEM_C1ICR_ISC11_Pos)              /*!< 0x00000800 */
+#define HSEM_C1ICR_ISC11          HSEM_C1ICR_ISC11_Msk                         /*!<semaphore 11 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC12_Pos      (12U)
+#define HSEM_C1ICR_ISC12_Msk      (0x1UL << HSEM_C1ICR_ISC12_Pos)              /*!< 0x00001000 */
+#define HSEM_C1ICR_ISC12          HSEM_C1ICR_ISC12_Msk                         /*!<semaphore 12 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC13_Pos      (13U)
+#define HSEM_C1ICR_ISC13_Msk      (0x1UL << HSEM_C1ICR_ISC13_Pos)              /*!< 0x00002000 */
+#define HSEM_C1ICR_ISC13          HSEM_C1ICR_ISC13_Msk                         /*!<semaphore 13 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC14_Pos      (14U)
+#define HSEM_C1ICR_ISC14_Msk      (0x1UL << HSEM_C1ICR_ISC14_Pos)              /*!< 0x00004000 */
+#define HSEM_C1ICR_ISC14          HSEM_C1ICR_ISC14_Msk                         /*!<semaphore 14 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC15_Pos      (15U)
+#define HSEM_C1ICR_ISC15_Msk      (0x1UL << HSEM_C1ICR_ISC15_Pos)              /*!< 0x00008000 */
+#define HSEM_C1ICR_ISC15          HSEM_C1ICR_ISC15_Msk                         /*!<semaphore 15 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC16_Pos      (16U)
+#define HSEM_C1ICR_ISC16_Msk      (0x1UL << HSEM_C1ICR_ISC16_Pos)              /*!< 0x00010000 */
+#define HSEM_C1ICR_ISC16          HSEM_C1ICR_ISC16_Msk                         /*!<semaphore 16 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC17_Pos      (17U)
+#define HSEM_C1ICR_ISC17_Msk      (0x1UL << HSEM_C1ICR_ISC17_Pos)              /*!< 0x00020000 */
+#define HSEM_C1ICR_ISC17          HSEM_C1ICR_ISC17_Msk                         /*!<semaphore 17 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC18_Pos      (18U)
+#define HSEM_C1ICR_ISC18_Msk      (0x1UL << HSEM_C1ICR_ISC18_Pos)              /*!< 0x00040000 */
+#define HSEM_C1ICR_ISC18          HSEM_C1ICR_ISC18_Msk                         /*!<semaphore 18 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC19_Pos      (19U)
+#define HSEM_C1ICR_ISC19_Msk      (0x1UL << HSEM_C1ICR_ISC19_Pos)              /*!< 0x00080000 */
+#define HSEM_C1ICR_ISC19          HSEM_C1ICR_ISC19_Msk                         /*!<semaphore 19 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC20_Pos      (20U)
+#define HSEM_C1ICR_ISC20_Msk      (0x1UL << HSEM_C1ICR_ISC20_Pos)              /*!< 0x00100000 */
+#define HSEM_C1ICR_ISC20          HSEM_C1ICR_ISC20_Msk                         /*!<semaphore 20 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC21_Pos      (21U)
+#define HSEM_C1ICR_ISC21_Msk      (0x1UL << HSEM_C1ICR_ISC21_Pos)              /*!< 0x00200000 */
+#define HSEM_C1ICR_ISC21          HSEM_C1ICR_ISC21_Msk                         /*!<semaphore 21 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC22_Pos      (22U)
+#define HSEM_C1ICR_ISC22_Msk      (0x1UL << HSEM_C1ICR_ISC22_Pos)              /*!< 0x00400000 */
+#define HSEM_C1ICR_ISC22          HSEM_C1ICR_ISC22_Msk                         /*!<semaphore 22 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC23_Pos      (23U)
+#define HSEM_C1ICR_ISC23_Msk      (0x1UL << HSEM_C1ICR_ISC23_Pos)              /*!< 0x00800000 */
+#define HSEM_C1ICR_ISC23          HSEM_C1ICR_ISC23_Msk                         /*!<semaphore 23 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC24_Pos      (24U)
+#define HSEM_C1ICR_ISC24_Msk      (0x1UL << HSEM_C1ICR_ISC24_Pos)              /*!< 0x01000000 */
+#define HSEM_C1ICR_ISC24          HSEM_C1ICR_ISC24_Msk                         /*!<semaphore 24 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC25_Pos      (25U)
+#define HSEM_C1ICR_ISC25_Msk      (0x1UL << HSEM_C1ICR_ISC25_Pos)              /*!< 0x02000000 */
+#define HSEM_C1ICR_ISC25          HSEM_C1ICR_ISC25_Msk                         /*!<semaphore 25 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC26_Pos      (26U)
+#define HSEM_C1ICR_ISC26_Msk      (0x1UL << HSEM_C1ICR_ISC26_Pos)              /*!< 0x04000000 */
+#define HSEM_C1ICR_ISC26          HSEM_C1ICR_ISC26_Msk                         /*!<semaphore 26 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC27_Pos      (27U)
+#define HSEM_C1ICR_ISC27_Msk      (0x1UL << HSEM_C1ICR_ISC27_Pos)              /*!< 0x08000000 */
+#define HSEM_C1ICR_ISC27          HSEM_C1ICR_ISC27_Msk                         /*!<semaphore 27 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC28_Pos      (28U)
+#define HSEM_C1ICR_ISC28_Msk      (0x1UL << HSEM_C1ICR_ISC28_Pos)              /*!< 0x10000000 */
+#define HSEM_C1ICR_ISC28          HSEM_C1ICR_ISC28_Msk                         /*!<semaphore 28 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC29_Pos      (29U)
+#define HSEM_C1ICR_ISC29_Msk      (0x1UL << HSEM_C1ICR_ISC29_Pos)              /*!< 0x20000000 */
+#define HSEM_C1ICR_ISC29          HSEM_C1ICR_ISC29_Msk                         /*!<semaphore 29 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC30_Pos      (30U)
+#define HSEM_C1ICR_ISC30_Msk      (0x1UL << HSEM_C1ICR_ISC30_Pos)              /*!< 0x40000000 */
+#define HSEM_C1ICR_ISC30          HSEM_C1ICR_ISC30_Msk                         /*!<semaphore 30 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC31_Pos      (31U)
+#define HSEM_C1ICR_ISC31_Msk      (0x1UL << HSEM_C1ICR_ISC31_Pos)              /*!< 0x80000000 */
+#define HSEM_C1ICR_ISC31          HSEM_C1ICR_ISC31_Msk                         /*!<semaphore 31 interrupt 0 clear bit. */
+
+/********************  Bit definition for HSEM_C1ISR register  *****************/
+#define HSEM_C1ISR_ISF0_Pos       (0U)
+#define HSEM_C1ISR_ISF0_Msk       (0x1UL << HSEM_C1ISR_ISF0_Pos)               /*!< 0x00000001 */
+#define HSEM_C1ISR_ISF0           HSEM_C1ISR_ISF0_Msk                          /*!<semaphore 0 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF1_Pos       (1U)
+#define HSEM_C1ISR_ISF1_Msk       (0x1UL << HSEM_C1ISR_ISF1_Pos)               /*!< 0x00000002 */
+#define HSEM_C1ISR_ISF1           HSEM_C1ISR_ISF1_Msk                          /*!<semaphore 1 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF2_Pos       (2U)
+#define HSEM_C1ISR_ISF2_Msk       (0x1UL << HSEM_C1ISR_ISF2_Pos)               /*!< 0x00000004 */
+#define HSEM_C1ISR_ISF2           HSEM_C1ISR_ISF2_Msk                          /*!<semaphore 2 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF3_Pos       (3U)
+#define HSEM_C1ISR_ISF3_Msk       (0x1UL << HSEM_C1ISR_ISF3_Pos)               /*!< 0x00000008 */
+#define HSEM_C1ISR_ISF3           HSEM_C1ISR_ISF3_Msk                          /*!<semaphore 3 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF4_Pos       (4U)
+#define HSEM_C1ISR_ISF4_Msk       (0x1UL << HSEM_C1ISR_ISF4_Pos)               /*!< 0x00000010 */
+#define HSEM_C1ISR_ISF4           HSEM_C1ISR_ISF4_Msk                          /*!<semaphore 4 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF5_Pos       (5U)
+#define HSEM_C1ISR_ISF5_Msk       (0x1UL << HSEM_C1ISR_ISF5_Pos)               /*!< 0x00000020 */
+#define HSEM_C1ISR_ISF5           HSEM_C1ISR_ISF5_Msk                          /*!<semaphore 5 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF6_Pos       (6U)
+#define HSEM_C1ISR_ISF6_Msk       (0x1UL << HSEM_C1ISR_ISF6_Pos)               /*!< 0x00000040 */
+#define HSEM_C1ISR_ISF6           HSEM_C1ISR_ISF6_Msk                          /*!<semaphore 6 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF7_Pos       (7U)
+#define HSEM_C1ISR_ISF7_Msk       (0x1UL << HSEM_C1ISR_ISF7_Pos)               /*!< 0x00000080 */
+#define HSEM_C1ISR_ISF7           HSEM_C1ISR_ISF7_Msk                          /*!<semaphore 7 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF8_Pos       (8U)
+#define HSEM_C1ISR_ISF8_Msk       (0x1UL << HSEM_C1ISR_ISF8_Pos)               /*!< 0x00000100 */
+#define HSEM_C1ISR_ISF8           HSEM_C1ISR_ISF8_Msk                          /*!<semaphore 8 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF9_Pos       (9U)
+#define HSEM_C1ISR_ISF9_Msk       (0x1UL << HSEM_C1ISR_ISF9_Pos)               /*!< 0x00000200 */
+#define HSEM_C1ISR_ISF9           HSEM_C1ISR_ISF9_Msk                          /*!<semaphore 9 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF10_Pos      (10U)
+#define HSEM_C1ISR_ISF10_Msk      (0x1UL << HSEM_C1ISR_ISF10_Pos)              /*!< 0x00000400 */
+#define HSEM_C1ISR_ISF10          HSEM_C1ISR_ISF10_Msk                         /*!<semaphore 10 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF11_Pos      (11U)
+#define HSEM_C1ISR_ISF11_Msk      (0x1UL << HSEM_C1ISR_ISF11_Pos)              /*!< 0x00000800 */
+#define HSEM_C1ISR_ISF11          HSEM_C1ISR_ISF11_Msk                         /*!<semaphore 11 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF12_Pos      (12U)
+#define HSEM_C1ISR_ISF12_Msk      (0x1UL << HSEM_C1ISR_ISF12_Pos)              /*!< 0x00001000 */
+#define HSEM_C1ISR_ISF12          HSEM_C1ISR_ISF12_Msk                         /*!<semaphore 12 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF13_Pos      (13U)
+#define HSEM_C1ISR_ISF13_Msk      (0x1UL << HSEM_C1ISR_ISF13_Pos)              /*!< 0x00002000 */
+#define HSEM_C1ISR_ISF13          HSEM_C1ISR_ISF13_Msk                         /*!<semaphore 13 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF14_Pos      (14U)
+#define HSEM_C1ISR_ISF14_Msk      (0x1UL << HSEM_C1ISR_ISF14_Pos)              /*!< 0x00004000 */
+#define HSEM_C1ISR_ISF14          HSEM_C1ISR_ISF14_Msk                         /*!<semaphore 14 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF15_Pos      (15U)
+#define HSEM_C1ISR_ISF15_Msk      (0x1UL << HSEM_C1ISR_ISF15_Pos)              /*!< 0x00008000 */
+#define HSEM_C1ISR_ISF15          HSEM_C1ISR_ISF15_Msk                         /*!<semaphore 15 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF16_Pos      (16U)
+#define HSEM_C1ISR_ISF16_Msk      (0x1UL << HSEM_C1ISR_ISF16_Pos)              /*!< 0x00010000 */
+#define HSEM_C1ISR_ISF16          HSEM_C1ISR_ISF16_Msk                         /*!<semaphore 16 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF17_Pos      (17U)
+#define HSEM_C1ISR_ISF17_Msk      (0x1UL << HSEM_C1ISR_ISF17_Pos)              /*!< 0x00020000 */
+#define HSEM_C1ISR_ISF17          HSEM_C1ISR_ISF17_Msk                         /*!<semaphore 17 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF18_Pos      (18U)
+#define HSEM_C1ISR_ISF18_Msk      (0x1UL << HSEM_C1ISR_ISF18_Pos)              /*!< 0x00040000 */
+#define HSEM_C1ISR_ISF18          HSEM_C1ISR_ISF18_Msk                         /*!<semaphore 18 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF19_Pos      (19U)
+#define HSEM_C1ISR_ISF19_Msk      (0x1UL << HSEM_C1ISR_ISF19_Pos)              /*!< 0x00080000 */
+#define HSEM_C1ISR_ISF19          HSEM_C1ISR_ISF19_Msk                         /*!<semaphore 19 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF20_Pos      (20U)
+#define HSEM_C1ISR_ISF20_Msk      (0x1UL << HSEM_C1ISR_ISF20_Pos)              /*!< 0x00100000 */
+#define HSEM_C1ISR_ISF20          HSEM_C1ISR_ISF20_Msk                         /*!<semaphore 20 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF21_Pos      (21U)
+#define HSEM_C1ISR_ISF21_Msk      (0x1UL << HSEM_C1ISR_ISF21_Pos)              /*!< 0x00200000 */
+#define HSEM_C1ISR_ISF21          HSEM_C1ISR_ISF21_Msk                         /*!<semaphore 21 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF22_Pos      (22U)
+#define HSEM_C1ISR_ISF22_Msk      (0x1UL << HSEM_C1ISR_ISF22_Pos)              /*!< 0x00400000 */
+#define HSEM_C1ISR_ISF22          HSEM_C1ISR_ISF22_Msk                         /*!<semaphore 22 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF23_Pos      (23U)
+#define HSEM_C1ISR_ISF23_Msk      (0x1UL << HSEM_C1ISR_ISF23_Pos)              /*!< 0x00800000 */
+#define HSEM_C1ISR_ISF23          HSEM_C1ISR_ISF23_Msk                         /*!<semaphore 23 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF24_Pos      (24U)
+#define HSEM_C1ISR_ISF24_Msk      (0x1UL << HSEM_C1ISR_ISF24_Pos)              /*!< 0x01000000 */
+#define HSEM_C1ISR_ISF24          HSEM_C1ISR_ISF24_Msk                         /*!<semaphore 24 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF25_Pos      (25U)
+#define HSEM_C1ISR_ISF25_Msk      (0x1UL << HSEM_C1ISR_ISF25_Pos)              /*!< 0x02000000 */
+#define HSEM_C1ISR_ISF25          HSEM_C1ISR_ISF25_Msk                         /*!<semaphore 25 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF26_Pos      (26U)
+#define HSEM_C1ISR_ISF26_Msk      (0x1UL << HSEM_C1ISR_ISF26_Pos)              /*!< 0x04000000 */
+#define HSEM_C1ISR_ISF26          HSEM_C1ISR_ISF26_Msk                         /*!<semaphore 26 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF27_Pos      (27U)
+#define HSEM_C1ISR_ISF27_Msk      (0x1UL << HSEM_C1ISR_ISF27_Pos)              /*!< 0x08000000 */
+#define HSEM_C1ISR_ISF27          HSEM_C1ISR_ISF27_Msk                         /*!<semaphore 27 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF28_Pos      (28U)
+#define HSEM_C1ISR_ISF28_Msk      (0x1UL << HSEM_C1ISR_ISF28_Pos)              /*!< 0x10000000 */
+#define HSEM_C1ISR_ISF28          HSEM_C1ISR_ISF28_Msk                         /*!<semaphore 28 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF29_Pos      (29U)
+#define HSEM_C1ISR_ISF29_Msk      (0x1UL << HSEM_C1ISR_ISF29_Pos)              /*!< 0x20000000 */
+#define HSEM_C1ISR_ISF29          HSEM_C1ISR_ISF29_Msk                         /*!<semaphore 29 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF30_Pos      (30U)
+#define HSEM_C1ISR_ISF30_Msk      (0x1UL << HSEM_C1ISR_ISF30_Pos)              /*!< 0x40000000 */
+#define HSEM_C1ISR_ISF30          HSEM_C1ISR_ISF30_Msk                         /*!<semaphore 30 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF31_Pos      (31U)
+#define HSEM_C1ISR_ISF31_Msk      (0x1UL << HSEM_C1ISR_ISF31_Pos)              /*!< 0x80000000 */
+#define HSEM_C1ISR_ISF31          HSEM_C1ISR_ISF31_Msk                         /*!<semaphore 31 interrupt 0 status bit. */
+
+/********************  Bit definition for HSEM_C1MISR register  *****************/
+#define HSEM_C1MISR_MISF0_Pos     (0U)
+#define HSEM_C1MISR_MISF0_Msk     (0x1UL << HSEM_C1MISR_MISF0_Pos)             /*!< 0x00000001 */
+#define HSEM_C1MISR_MISF0         HSEM_C1MISR_MISF0_Msk                        /*!<semaphore 0 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF1_Pos     (1U)
+#define HSEM_C1MISR_MISF1_Msk     (0x1UL << HSEM_C1MISR_MISF1_Pos)             /*!< 0x00000002 */
+#define HSEM_C1MISR_MISF1         HSEM_C1MISR_MISF1_Msk                        /*!<semaphore 1 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF2_Pos     (2U)
+#define HSEM_C1MISR_MISF2_Msk     (0x1UL << HSEM_C1MISR_MISF2_Pos)             /*!< 0x00000004 */
+#define HSEM_C1MISR_MISF2         HSEM_C1MISR_MISF2_Msk                        /*!<semaphore 2 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF3_Pos     (3U)
+#define HSEM_C1MISR_MISF3_Msk     (0x1UL << HSEM_C1MISR_MISF3_Pos)             /*!< 0x00000008 */
+#define HSEM_C1MISR_MISF3         HSEM_C1MISR_MISF3_Msk                        /*!<semaphore 3 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF4_Pos     (4U)
+#define HSEM_C1MISR_MISF4_Msk     (0x1UL << HSEM_C1MISR_MISF4_Pos)             /*!< 0x00000010 */
+#define HSEM_C1MISR_MISF4         HSEM_C1MISR_MISF4_Msk                        /*!<semaphore 4 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF5_Pos     (5U)
+#define HSEM_C1MISR_MISF5_Msk     (0x1UL << HSEM_C1MISR_MISF5_Pos)             /*!< 0x00000020 */
+#define HSEM_C1MISR_MISF5         HSEM_C1MISR_MISF5_Msk                        /*!<semaphore 5 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF6_Pos     (6U)
+#define HSEM_C1MISR_MISF6_Msk     (0x1UL << HSEM_C1MISR_MISF6_Pos)             /*!< 0x00000040 */
+#define HSEM_C1MISR_MISF6         HSEM_C1MISR_MISF6_Msk                        /*!<semaphore 6 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF7_Pos     (7U)
+#define HSEM_C1MISR_MISF7_Msk     (0x1UL << HSEM_C1MISR_MISF7_Pos)             /*!< 0x00000080 */
+#define HSEM_C1MISR_MISF7         HSEM_C1MISR_MISF7_Msk                        /*!<semaphore 7 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF8_Pos     (8U)
+#define HSEM_C1MISR_MISF8_Msk     (0x1UL << HSEM_C1MISR_MISF8_Pos)             /*!< 0x00000100 */
+#define HSEM_C1MISR_MISF8         HSEM_C1MISR_MISF8_Msk                        /*!<semaphore 8 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF9_Pos     (9U)
+#define HSEM_C1MISR_MISF9_Msk     (0x1UL << HSEM_C1MISR_MISF9_Pos)             /*!< 0x00000200 */
+#define HSEM_C1MISR_MISF9         HSEM_C1MISR_MISF9_Msk                        /*!<semaphore 9 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF10_Pos    (10U)
+#define HSEM_C1MISR_MISF10_Msk    (0x1UL << HSEM_C1MISR_MISF10_Pos)            /*!< 0x00000400 */
+#define HSEM_C1MISR_MISF10        HSEM_C1MISR_MISF10_Msk                       /*!<semaphore 10 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF11_Pos    (11U)
+#define HSEM_C1MISR_MISF11_Msk    (0x1UL << HSEM_C1MISR_MISF11_Pos)            /*!< 0x00000800 */
+#define HSEM_C1MISR_MISF11        HSEM_C1MISR_MISF11_Msk                       /*!<semaphore 11 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF12_Pos    (12U)
+#define HSEM_C1MISR_MISF12_Msk    (0x1UL << HSEM_C1MISR_MISF12_Pos)            /*!< 0x00001000 */
+#define HSEM_C1MISR_MISF12        HSEM_C1MISR_MISF12_Msk                       /*!<semaphore 12 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF13_Pos    (13U)
+#define HSEM_C1MISR_MISF13_Msk    (0x1UL << HSEM_C1MISR_MISF13_Pos)            /*!< 0x00002000 */
+#define HSEM_C1MISR_MISF13        HSEM_C1MISR_MISF13_Msk                       /*!<semaphore 13 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF14_Pos    (14U)
+#define HSEM_C1MISR_MISF14_Msk    (0x1UL << HSEM_C1MISR_MISF14_Pos)            /*!< 0x00004000 */
+#define HSEM_C1MISR_MISF14        HSEM_C1MISR_MISF14_Msk                       /*!<semaphore 14 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF15_Pos    (15U)
+#define HSEM_C1MISR_MISF15_Msk    (0x1UL << HSEM_C1MISR_MISF15_Pos)            /*!< 0x00008000 */
+#define HSEM_C1MISR_MISF15        HSEM_C1MISR_MISF15_Msk                       /*!<semaphore 15 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF16_Pos    (16U)
+#define HSEM_C1MISR_MISF16_Msk    (0x1UL << HSEM_C1MISR_MISF16_Pos)            /*!< 0x00010000 */
+#define HSEM_C1MISR_MISF16        HSEM_C1MISR_MISF16_Msk                       /*!<semaphore 16 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF17_Pos    (17U)
+#define HSEM_C1MISR_MISF17_Msk    (0x1UL << HSEM_C1MISR_MISF17_Pos)            /*!< 0x00020000 */
+#define HSEM_C1MISR_MISF17        HSEM_C1MISR_MISF17_Msk                       /*!<semaphore 17 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF18_Pos    (18U)
+#define HSEM_C1MISR_MISF18_Msk    (0x1UL << HSEM_C1MISR_MISF18_Pos)            /*!< 0x00040000 */
+#define HSEM_C1MISR_MISF18        HSEM_C1MISR_MISF18_Msk                       /*!<semaphore 18 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF19_Pos    (19U)
+#define HSEM_C1MISR_MISF19_Msk    (0x1UL << HSEM_C1MISR_MISF19_Pos)            /*!< 0x00080000 */
+#define HSEM_C1MISR_MISF19        HSEM_C1MISR_MISF19_Msk                       /*!<semaphore 19 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF20_Pos    (20U)
+#define HSEM_C1MISR_MISF20_Msk    (0x1UL << HSEM_C1MISR_MISF20_Pos)            /*!< 0x00100000 */
+#define HSEM_C1MISR_MISF20        HSEM_C1MISR_MISF20_Msk                       /*!<semaphore 20 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF21_Pos    (21U)
+#define HSEM_C1MISR_MISF21_Msk    (0x1UL << HSEM_C1MISR_MISF21_Pos)            /*!< 0x00200000 */
+#define HSEM_C1MISR_MISF21        HSEM_C1MISR_MISF21_Msk                       /*!<semaphore 21 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF22_Pos    (22U)
+#define HSEM_C1MISR_MISF22_Msk    (0x1UL << HSEM_C1MISR_MISF22_Pos)            /*!< 0x00400000 */
+#define HSEM_C1MISR_MISF22        HSEM_C1MISR_MISF22_Msk                       /*!<semaphore 22 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF23_Pos    (23U)
+#define HSEM_C1MISR_MISF23_Msk    (0x1UL << HSEM_C1MISR_MISF23_Pos)            /*!< 0x00800000 */
+#define HSEM_C1MISR_MISF23        HSEM_C1MISR_MISF23_Msk                       /*!<semaphore 23 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF24_Pos    (24U)
+#define HSEM_C1MISR_MISF24_Msk    (0x1UL << HSEM_C1MISR_MISF24_Pos)            /*!< 0x01000000 */
+#define HSEM_C1MISR_MISF24        HSEM_C1MISR_MISF24_Msk                       /*!<semaphore 24 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF25_Pos    (25U)
+#define HSEM_C1MISR_MISF25_Msk    (0x1UL << HSEM_C1MISR_MISF25_Pos)            /*!< 0x02000000 */
+#define HSEM_C1MISR_MISF25        HSEM_C1MISR_MISF25_Msk                       /*!<semaphore 25 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF26_Pos    (26U)
+#define HSEM_C1MISR_MISF26_Msk    (0x1UL << HSEM_C1MISR_MISF26_Pos)            /*!< 0x04000000 */
+#define HSEM_C1MISR_MISF26        HSEM_C1MISR_MISF26_Msk                       /*!<semaphore 26 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF27_Pos    (27U)
+#define HSEM_C1MISR_MISF27_Msk    (0x1UL << HSEM_C1MISR_MISF27_Pos)            /*!< 0x08000000 */
+#define HSEM_C1MISR_MISF27        HSEM_C1MISR_MISF27_Msk                       /*!<semaphore 27 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF28_Pos    (28U)
+#define HSEM_C1MISR_MISF28_Msk    (0x1UL << HSEM_C1MISR_MISF28_Pos)            /*!< 0x10000000 */
+#define HSEM_C1MISR_MISF28        HSEM_C1MISR_MISF28_Msk                       /*!<semaphore 28 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF29_Pos    (29U)
+#define HSEM_C1MISR_MISF29_Msk    (0x1UL << HSEM_C1MISR_MISF29_Pos)            /*!< 0x20000000 */
+#define HSEM_C1MISR_MISF29        HSEM_C1MISR_MISF29_Msk                       /*!<semaphore 29 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF30_Pos    (30U)
+#define HSEM_C1MISR_MISF30_Msk    (0x1UL << HSEM_C1MISR_MISF30_Pos)            /*!< 0x40000000 */
+#define HSEM_C1MISR_MISF30        HSEM_C1MISR_MISF30_Msk                       /*!<semaphore 30 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF31_Pos    (31U)
+#define HSEM_C1MISR_MISF31_Msk    (0x1UL << HSEM_C1MISR_MISF31_Pos)            /*!< 0x80000000 */
+#define HSEM_C1MISR_MISF31        HSEM_C1MISR_MISF31_Msk                       /*!<semaphore 31 interrupt 0 masked status bit. */
+
+/********************  Bit definition for HSEM_CR register  *****************/
+#define HSEM_CR_COREID_Pos        (8U)
+#define HSEM_CR_COREID_Msk        (0xFFUL << HSEM_CR_COREID_Pos)               /*!< 0x0000FF00 */
+#define HSEM_CR_COREID            HSEM_CR_COREID_Msk                           /*!<CoreID of semaphores to be cleared. */
+#define HSEM_CR_KEY_Pos           (16U)
+#define HSEM_CR_KEY_Msk           (0xFFFFUL << HSEM_CR_KEY_Pos)                /*!< 0xFFFF0000 */
+#define HSEM_CR_KEY               HSEM_CR_KEY_Msk                              /*!<semaphores clear key. */
+
+/********************  Bit definition for HSEM_KEYR register  *****************/
+#define HSEM_KEYR_KEY_Pos         (16U)
+#define HSEM_KEYR_KEY_Msk         (0xFFFFUL << HSEM_KEYR_KEY_Pos)              /*!< 0xFFFF0000 */
+#define HSEM_KEYR_KEY             HSEM_KEYR_KEY_Msk                            /*!<semaphores clear key. */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Inter-integrated Circuit Interface (I2C)              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for I2C_CR1 register  *******************/
+#define I2C_CR1_PE_Pos               (0U)
+#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                 /*!< 0x00000001 */
+#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */
+#define I2C_CR1_TXIE_Pos             (1U)
+#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)               /*!< 0x00000002 */
+#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */
+#define I2C_CR1_RXIE_Pos             (2U)
+#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)               /*!< 0x00000004 */
+#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE_Pos           (3U)
+#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)             /*!< 0x00000008 */
+#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE_Pos           (4U)
+#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)             /*!< 0x00000010 */
+#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE_Pos           (5U)
+#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)             /*!< 0x00000020 */
+#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE_Pos             (6U)
+#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)               /*!< 0x00000040 */
+#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE_Pos            (7U)
+#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)              /*!< 0x00000080 */
+#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */
+#define I2C_CR1_DNF_Pos              (8U)
+#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                /*!< 0x00000F00 */
+#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF_Pos           (12U)
+#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)             /*!< 0x00001000 */
+#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */
+#define I2C_CR1_TXDMAEN_Pos          (14U)
+#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)            /*!< 0x00004000 */
+#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN_Pos          (15U)
+#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)            /*!< 0x00008000 */
+#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */
+#define I2C_CR1_SBC_Pos              (16U)
+#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                /*!< 0x00010000 */
+#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH_Pos        (17U)
+#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)          /*!< 0x00020000 */
+#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN_Pos            (18U)
+#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)              /*!< 0x00040000 */
+#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN_Pos             (19U)
+#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)               /*!< 0x00080000 */
+#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */
+#define I2C_CR1_SMBHEN_Pos           (20U)
+#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)             /*!< 0x00100000 */
+#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN_Pos           (21U)
+#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)             /*!< 0x00200000 */
+#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN_Pos          (22U)
+#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)            /*!< 0x00400000 */
+#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */
+#define I2C_CR1_PECEN_Pos            (23U)
+#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)              /*!< 0x00800000 */
+#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */
+
+/******************  Bit definition for I2C_CR2 register  ********************/
+#define I2C_CR2_SADD_Pos             (0U)
+#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)             /*!< 0x000003FF */
+#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN_Pos           (10U)
+#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)             /*!< 0x00000400 */
+#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10_Pos            (11U)
+#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)              /*!< 0x00000800 */
+#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R_Pos          (12U)
+#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)            /*!< 0x00001000 */
+#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START_Pos            (13U)
+#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)              /*!< 0x00002000 */
+#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */
+#define I2C_CR2_STOP_Pos             (14U)
+#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)               /*!< 0x00004000 */
+#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK_Pos             (15U)
+#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)               /*!< 0x00008000 */
+#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES_Pos           (16U)
+#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)            /*!< 0x00FF0000 */
+#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */
+#define I2C_CR2_RELOAD_Pos           (24U)
+#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)             /*!< 0x01000000 */
+#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND_Pos          (25U)
+#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)            /*!< 0x02000000 */
+#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE_Pos          (26U)
+#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)            /*!< 0x04000000 */
+#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */
+
+/*******************  Bit definition for I2C_OAR1 register  ******************/
+#define I2C_OAR1_OA1_Pos             (0U)
+#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)             /*!< 0x000003FF */
+#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE_Pos         (10U)
+#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)           /*!< 0x00000400 */
+#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN_Pos           (15U)
+#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)             /*!< 0x00008000 */
+#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */
+
+/*******************  Bit definition for I2C_OAR2 register  ******************/
+#define I2C_OAR2_OA2_Pos             (1U)
+#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)              /*!< 0x000000FE */
+#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK_Pos          (8U)
+#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)            /*!< 0x00000700 */
+#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK           0x00000000UL                              /*!< No mask */
+#define I2C_OAR2_OA2MASK01_Pos       (8U)
+#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)         /*!< 0x00000100 */
+#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02_Pos       (9U)
+#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)         /*!< 0x00000200 */
+#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03_Pos       (8U)
+#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)         /*!< 0x00000300 */
+#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04_Pos       (10U)
+#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)         /*!< 0x00000400 */
+#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05_Pos       (8U)
+#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)         /*!< 0x00000500 */
+#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06_Pos       (9U)
+#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)         /*!< 0x00000600 */
+#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07_Pos       (8U)
+#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)         /*!< 0x00000700 */
+#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN_Pos           (15U)
+#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)             /*!< 0x00008000 */
+#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable */
+
+/*******************  Bit definition for I2C_TIMINGR register *******************/
+#define I2C_TIMINGR_SCLL_Pos         (0U)
+#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)          /*!< 0x000000FF */
+#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH_Pos         (8U)
+#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)          /*!< 0x0000FF00 */
+#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL_Pos       (16U)
+#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)         /*!< 0x000F0000 */
+#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL_Pos       (20U)
+#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)         /*!< 0x00F00000 */
+#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */
+#define I2C_TIMINGR_PRESC_Pos        (28U)
+#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)          /*!< 0xF0000000 */
+#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)
+#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)    /*!< 0x00000FFF */
+#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE_Pos       (12U)
+#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)         /*!< 0x00001000 */
+#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)
+#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)      /*!< 0x00008000 */
+#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)
+#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)    /*!< 0x0FFF0000 */
+#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)
+#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)        /*!< 0x80000000 */
+#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
+
+/******************  Bit definition for I2C_ISR register  *********************/
+#define I2C_ISR_TXE_Pos              (0U)
+#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                /*!< 0x00000001 */
+#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */
+#define I2C_ISR_TXIS_Pos             (1U)
+#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)               /*!< 0x00000002 */
+#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE_Pos             (2U)
+#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)               /*!< 0x00000004 */
+#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
+#define I2C_ISR_ADDR_Pos             (3U)
+#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)               /*!< 0x00000008 */
+#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF_Pos            (4U)
+#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)              /*!< 0x00000010 */
+#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */
+#define I2C_ISR_STOPF_Pos            (5U)
+#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)              /*!< 0x00000020 */
+#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */
+#define I2C_ISR_TC_Pos               (6U)
+#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                 /*!< 0x00000040 */
+#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR_Pos              (7U)
+#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                /*!< 0x00000080 */
+#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */
+#define I2C_ISR_BERR_Pos             (8U)
+#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)               /*!< 0x00000100 */
+#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */
+#define I2C_ISR_ARLO_Pos             (9U)
+#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)               /*!< 0x00000200 */
+#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */
+#define I2C_ISR_OVR_Pos              (10U)
+#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                /*!< 0x00000400 */
+#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR_Pos           (11U)
+#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)             /*!< 0x00000800 */
+#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT_Pos          (12U)
+#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)            /*!< 0x00001000 */
+#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT_Pos            (13U)
+#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)              /*!< 0x00002000 */
+#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */
+#define I2C_ISR_BUSY_Pos             (15U)
+#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)               /*!< 0x00008000 */
+#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */
+#define I2C_ISR_DIR_Pos              (16U)
+#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                /*!< 0x00010000 */
+#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE_Pos          (17U)
+#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)           /*!< 0x00FE0000 */
+#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
+
+/******************  Bit definition for I2C_ICR register  *********************/
+#define I2C_ICR_ADDRCF_Pos           (3U)
+#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)             /*!< 0x00000008 */
+#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF_Pos           (4U)
+#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)             /*!< 0x00000010 */
+#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */
+#define I2C_ICR_STOPCF_Pos           (5U)
+#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)             /*!< 0x00000020 */
+#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF_Pos           (8U)
+#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)             /*!< 0x00000100 */
+#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF_Pos           (9U)
+#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)             /*!< 0x00000200 */
+#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF_Pos            (10U)
+#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)              /*!< 0x00000400 */
+#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF_Pos            (11U)
+#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)              /*!< 0x00000800 */
+#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF_Pos         (12U)
+#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)           /*!< 0x00001000 */
+#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF_Pos          (13U)
+#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)            /*!< 0x00002000 */
+#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */
+
+/******************  Bit definition for I2C_PECR register  *********************/
+#define I2C_PECR_PEC_Pos             (0U)
+#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)              /*!< 0x000000FF */
+#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
+
+/******************  Bit definition for I2C_RXDR register  *********************/
+#define I2C_RXDR_RXDATA_Pos          (0U)
+#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)           /*!< 0x000000FF */
+#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
+
+/******************  Bit definition for I2C_TXDR register  *********************/
+#define I2C_TXDR_TXDATA_Pos          (0U)
+#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)           /*!< 0x000000FF */
+#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Independent WATCHDOG                             */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define IWDG_KR_KEY_Pos      (0U)
+#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                     /*!< 0x0000FFFF */
+#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define IWDG_PR_PR_Pos       (0U)
+#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                         /*!< 0x00000007 */
+#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */
+#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */
+#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */
+#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define IWDG_RLR_RL_Pos      (0U)
+#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                      /*!< 0x00000FFF */
+#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define IWDG_SR_PVU_Pos      (0U)
+#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                        /*!< 0x00000001 */
+#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos      (1U)
+#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                        /*!< 0x00000002 */
+#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU_Pos      (2U)
+#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                        /*!< 0x00000004 */
+#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
+
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define IWDG_WINR_WIN_Pos    (0U)
+#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                    /*!< 0x00000FFF */
+#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        JPEG Encoder/Decoder                                */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for CONFR0 register  ********************/
+#define JPEG_CONFR0_START_Pos           (0U)
+#define JPEG_CONFR0_START_Msk           (0x1UL << JPEG_CONFR0_START_Pos)       /*!< 0x00000001 */
+#define JPEG_CONFR0_START               JPEG_CONFR0_START_Msk                  /*!<Start/Stop bit */
+
+/********************  Bit definition for CONFR1 register  ********************/
+#define JPEG_CONFR1_NF_Pos              (0U)
+#define JPEG_CONFR1_NF_Msk              (0x3UL << JPEG_CONFR1_NF_Pos)          /*!< 0x00000003 */
+#define JPEG_CONFR1_NF                  JPEG_CONFR1_NF_Msk                     /*!<Number of color components */
+#define JPEG_CONFR1_NF_0                (0x1UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000001 */
+#define JPEG_CONFR1_NF_1                (0x2UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000002 */
+#define JPEG_CONFR1_DE_Pos              (3U)
+#define JPEG_CONFR1_DE_Msk              (0x1UL << JPEG_CONFR1_DE_Pos)          /*!< 0x00000008 */
+#define JPEG_CONFR1_DE                  JPEG_CONFR1_DE_Msk                     /*!<Decoding Enable */
+#define JPEG_CONFR1_COLORSPACE_Pos      (4U)
+#define JPEG_CONFR1_COLORSPACE_Msk      (0x3UL << JPEG_CONFR1_COLORSPACE_Pos)  /*!< 0x00000030 */
+#define JPEG_CONFR1_COLORSPACE          JPEG_CONFR1_COLORSPACE_Msk             /*!<Color Space */
+#define JPEG_CONFR1_COLORSPACE_0        (0x1UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000010 */
+#define JPEG_CONFR1_COLORSPACE_1        (0x2UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000020 */
+#define JPEG_CONFR1_NS_Pos              (6U)
+#define JPEG_CONFR1_NS_Msk              (0x3UL << JPEG_CONFR1_NS_Pos)          /*!< 0x000000C0 */
+#define JPEG_CONFR1_NS                  JPEG_CONFR1_NS_Msk                     /*!<Number of components for Scan */
+#define JPEG_CONFR1_NS_0                (0x1UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000040 */
+#define JPEG_CONFR1_NS_1                (0x2UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000080 */
+#define JPEG_CONFR1_HDR_Pos             (8U)
+#define JPEG_CONFR1_HDR_Msk             (0x1UL << JPEG_CONFR1_HDR_Pos)         /*!< 0x00000100 */
+#define JPEG_CONFR1_HDR                 JPEG_CONFR1_HDR_Msk                    /*!<Header Processing On/Off */
+#define JPEG_CONFR1_YSIZE_Pos           (16U)
+#define JPEG_CONFR1_YSIZE_Msk           (0xFFFFUL << JPEG_CONFR1_YSIZE_Pos)    /*!< 0xFFFF0000 */
+#define JPEG_CONFR1_YSIZE               JPEG_CONFR1_YSIZE_Msk                  /*!<Number of lines in source image */
+
+/********************  Bit definition for CONFR2 register  ********************/
+#define JPEG_CONFR2_NMCU_Pos            (0U)
+#define JPEG_CONFR2_NMCU_Msk            (0x3FFFFFFUL << JPEG_CONFR2_NMCU_Pos)  /*!< 0x03FFFFFF */
+#define JPEG_CONFR2_NMCU                JPEG_CONFR2_NMCU_Msk                   /*!<Number of MCU units minus 1 to encode */
+
+/********************  Bit definition for CONFR3 register  ********************/
+#define JPEG_CONFR3_XSIZE_Pos           (16U)
+#define JPEG_CONFR3_XSIZE_Msk           (0xFFFFUL << JPEG_CONFR3_XSIZE_Pos)    /*!< 0xFFFF0000 */
+#define JPEG_CONFR3_XSIZE               JPEG_CONFR3_XSIZE_Msk                  /*!<Number of pixels per line */
+
+/********************  Bit definition for CONFR4 register  ********************/
+#define JPEG_CONFR4_HD_Pos              (0U)
+#define JPEG_CONFR4_HD_Msk              (0x1UL << JPEG_CONFR4_HD_Pos)          /*!< 0x00000001 */
+#define JPEG_CONFR4_HD                  JPEG_CONFR4_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */
+#define JPEG_CONFR4_HA_Pos              (1U)
+#define JPEG_CONFR4_HA_Msk              (0x1UL << JPEG_CONFR4_HA_Pos)          /*!< 0x00000002 */
+#define JPEG_CONFR4_HA                  JPEG_CONFR4_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */
+#define JPEG_CONFR4_QT_Pos              (2U)
+#define JPEG_CONFR4_QT_Msk              (0x3UL << JPEG_CONFR4_QT_Pos)          /*!< 0x0000000C */
+#define JPEG_CONFR4_QT                  JPEG_CONFR4_QT_Msk                     /*!<Selects quantization table associated with a color component */
+#define JPEG_CONFR4_QT_0                (0x1UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000004 */
+#define JPEG_CONFR4_QT_1                (0x2UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000008 */
+#define JPEG_CONFR4_NB_Pos              (4U)
+#define JPEG_CONFR4_NB_Msk              (0xFUL << JPEG_CONFR4_NB_Pos)          /*!< 0x000000F0 */
+#define JPEG_CONFR4_NB                  JPEG_CONFR4_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */
+#define JPEG_CONFR4_NB_0                (0x1UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000010 */
+#define JPEG_CONFR4_NB_1                (0x2UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000020 */
+#define JPEG_CONFR4_NB_2                (0x4UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000040 */
+#define JPEG_CONFR4_NB_3                (0x8UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000080 */
+#define JPEG_CONFR4_VSF_Pos             (8U)
+#define JPEG_CONFR4_VSF_Msk             (0xFUL << JPEG_CONFR4_VSF_Pos)         /*!< 0x00000F00 */
+#define JPEG_CONFR4_VSF                 JPEG_CONFR4_VSF_Msk                    /*!<Vertical sampling factor for component 1 */
+#define JPEG_CONFR4_VSF_0               (0x1UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000100 */
+#define JPEG_CONFR4_VSF_1               (0x2UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000200 */
+#define JPEG_CONFR4_VSF_2               (0x4UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000400 */
+#define JPEG_CONFR4_VSF_3               (0x8UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000800 */
+#define JPEG_CONFR4_HSF_Pos             (12U)
+#define JPEG_CONFR4_HSF_Msk             (0xFUL << JPEG_CONFR4_HSF_Pos)         /*!< 0x0000F000 */
+#define JPEG_CONFR4_HSF                 JPEG_CONFR4_HSF_Msk                    /*!<Horizontal sampling factor for component 1 */
+#define JPEG_CONFR4_HSF_0               (0x1UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00001000 */
+#define JPEG_CONFR4_HSF_1               (0x2UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00002000 */
+#define JPEG_CONFR4_HSF_2               (0x4UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00004000 */
+#define JPEG_CONFR4_HSF_3               (0x8UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00008000 */
+
+/********************  Bit definition for CONFR5 register  ********************/
+#define JPEG_CONFR5_HD_Pos              (0U)
+#define JPEG_CONFR5_HD_Msk              (0x1UL << JPEG_CONFR5_HD_Pos)          /*!< 0x00000001 */
+#define JPEG_CONFR5_HD                  JPEG_CONFR5_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */
+#define JPEG_CONFR5_HA_Pos              (1U)
+#define JPEG_CONFR5_HA_Msk              (0x1UL << JPEG_CONFR5_HA_Pos)          /*!< 0x00000002 */
+#define JPEG_CONFR5_HA                  JPEG_CONFR5_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */
+#define JPEG_CONFR5_QT_Pos              (2U)
+#define JPEG_CONFR5_QT_Msk              (0x3UL << JPEG_CONFR5_QT_Pos)          /*!< 0x0000000C */
+#define JPEG_CONFR5_QT                  JPEG_CONFR5_QT_Msk                     /*!<Selects quantization table associated with a color component */
+#define JPEG_CONFR5_QT_0                (0x1UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000004 */
+#define JPEG_CONFR5_QT_1                (0x2UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000008 */
+#define JPEG_CONFR5_NB_Pos              (4U)
+#define JPEG_CONFR5_NB_Msk              (0xFUL << JPEG_CONFR5_NB_Pos)          /*!< 0x000000F0 */
+#define JPEG_CONFR5_NB                  JPEG_CONFR5_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */
+#define JPEG_CONFR5_NB_0                (0x1UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000010 */
+#define JPEG_CONFR5_NB_1                (0x2UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000020 */
+#define JPEG_CONFR5_NB_2                (0x4UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000040 */
+#define JPEG_CONFR5_NB_3                (0x8UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000080 */
+#define JPEG_CONFR5_VSF_Pos             (8U)
+#define JPEG_CONFR5_VSF_Msk             (0xFUL << JPEG_CONFR5_VSF_Pos)         /*!< 0x00000F00 */
+#define JPEG_CONFR5_VSF                 JPEG_CONFR5_VSF_Msk                    /*!<Vertical sampling factor for component 2 */
+#define JPEG_CONFR5_VSF_0               (0x1UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000100 */
+#define JPEG_CONFR5_VSF_1               (0x2UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000200 */
+#define JPEG_CONFR5_VSF_2               (0x4UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000400 */
+#define JPEG_CONFR5_VSF_3               (0x8UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000800 */
+#define JPEG_CONFR5_HSF_Pos             (12U)
+#define JPEG_CONFR5_HSF_Msk             (0xFUL << JPEG_CONFR5_HSF_Pos)         /*!< 0x0000F000 */
+#define JPEG_CONFR5_HSF                 JPEG_CONFR5_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */
+#define JPEG_CONFR5_HSF_0               (0x1UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00001000 */
+#define JPEG_CONFR5_HSF_1               (0x2UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00002000 */
+#define JPEG_CONFR5_HSF_2               (0x4UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00004000 */
+#define JPEG_CONFR5_HSF_3               (0x8UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00008000 */
+
+/********************  Bit definition for CONFR6 register  ********************/
+#define JPEG_CONFR6_HD_Pos              (0U)
+#define JPEG_CONFR6_HD_Msk              (0x1UL << JPEG_CONFR6_HD_Pos)          /*!< 0x00000001 */
+#define JPEG_CONFR6_HD                  JPEG_CONFR6_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */
+#define JPEG_CONFR6_HA_Pos              (1U)
+#define JPEG_CONFR6_HA_Msk              (0x1UL << JPEG_CONFR6_HA_Pos)          /*!< 0x00000002 */
+#define JPEG_CONFR6_HA                  JPEG_CONFR6_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */
+#define JPEG_CONFR6_QT_Pos              (2U)
+#define JPEG_CONFR6_QT_Msk              (0x3UL << JPEG_CONFR6_QT_Pos)          /*!< 0x0000000C */
+#define JPEG_CONFR6_QT                  JPEG_CONFR6_QT_Msk                     /*!<Selects quantization table associated with a color component */
+#define JPEG_CONFR6_QT_0                (0x1UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000004 */
+#define JPEG_CONFR6_QT_1                (0x2UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000008 */
+#define JPEG_CONFR6_NB_Pos              (4U)
+#define JPEG_CONFR6_NB_Msk              (0xFUL << JPEG_CONFR6_NB_Pos)          /*!< 0x000000F0 */
+#define JPEG_CONFR6_NB                  JPEG_CONFR6_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */
+#define JPEG_CONFR6_NB_0                (0x1UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000010 */
+#define JPEG_CONFR6_NB_1                (0x2UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000020 */
+#define JPEG_CONFR6_NB_2                (0x4UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000040 */
+#define JPEG_CONFR6_NB_3                (0x8UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000080 */
+#define JPEG_CONFR6_VSF_Pos             (8U)
+#define JPEG_CONFR6_VSF_Msk             (0xFUL << JPEG_CONFR6_VSF_Pos)         /*!< 0x00000F00 */
+#define JPEG_CONFR6_VSF                 JPEG_CONFR6_VSF_Msk                    /*!<Vertical sampling factor for component 2 */
+#define JPEG_CONFR6_VSF_0               (0x1UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000100 */
+#define JPEG_CONFR6_VSF_1               (0x2UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000200 */
+#define JPEG_CONFR6_VSF_2               (0x4UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000400 */
+#define JPEG_CONFR6_VSF_3               (0x8UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000800 */
+#define JPEG_CONFR6_HSF_Pos             (12U)
+#define JPEG_CONFR6_HSF_Msk             (0xFUL << JPEG_CONFR6_HSF_Pos)         /*!< 0x0000F000 */
+#define JPEG_CONFR6_HSF                 JPEG_CONFR6_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */
+#define JPEG_CONFR6_HSF_0               (0x1UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00001000 */
+#define JPEG_CONFR6_HSF_1               (0x2UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00002000 */
+#define JPEG_CONFR6_HSF_2               (0x4UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00004000 */
+#define JPEG_CONFR6_HSF_3               (0x8UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00008000 */
+
+/********************  Bit definition for CONFR7 register  ********************/
+#define JPEG_CONFR7_HD_Pos              (0U)
+#define JPEG_CONFR7_HD_Msk              (0x1UL << JPEG_CONFR7_HD_Pos)          /*!< 0x00000001 */
+#define JPEG_CONFR7_HD                  JPEG_CONFR7_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */
+#define JPEG_CONFR7_HA_Pos              (1U)
+#define JPEG_CONFR7_HA_Msk              (0x1UL << JPEG_CONFR7_HA_Pos)          /*!< 0x00000002 */
+#define JPEG_CONFR7_HA                  JPEG_CONFR7_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */
+#define JPEG_CONFR7_QT_Pos              (2U)
+#define JPEG_CONFR7_QT_Msk              (0x3UL << JPEG_CONFR7_QT_Pos)          /*!< 0x0000000C */
+#define JPEG_CONFR7_QT                  JPEG_CONFR7_QT_Msk                     /*!<Selects quantization table associated with a color component */
+#define JPEG_CONFR7_QT_0                (0x1UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000004 */
+#define JPEG_CONFR7_QT_1                (0x2UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000008 */
+#define JPEG_CONFR7_NB_Pos              (4U)
+#define JPEG_CONFR7_NB_Msk              (0xFUL << JPEG_CONFR7_NB_Pos)          /*!< 0x000000F0 */
+#define JPEG_CONFR7_NB                  JPEG_CONFR7_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */
+#define JPEG_CONFR7_NB_0                (0x1UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000010 */
+#define JPEG_CONFR7_NB_1                (0x2UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000020 */
+#define JPEG_CONFR7_NB_2                (0x4UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000040 */
+#define JPEG_CONFR7_NB_3                (0x8UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000080 */
+#define JPEG_CONFR7_VSF_Pos             (8U)
+#define JPEG_CONFR7_VSF_Msk             (0xFUL << JPEG_CONFR7_VSF_Pos)         /*!< 0x00000F00 */
+#define JPEG_CONFR7_VSF                 JPEG_CONFR7_VSF_Msk                    /*!<Vertical sampling factor for component 2 */
+#define JPEG_CONFR7_VSF_0               (0x1UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000100 */
+#define JPEG_CONFR7_VSF_1               (0x2UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000200 */
+#define JPEG_CONFR7_VSF_2               (0x4UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000400 */
+#define JPEG_CONFR7_VSF_3               (0x8UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000800 */
+#define JPEG_CONFR7_HSF_Pos             (12U)
+#define JPEG_CONFR7_HSF_Msk             (0xFUL << JPEG_CONFR7_HSF_Pos)         /*!< 0x0000F000 */
+#define JPEG_CONFR7_HSF                 JPEG_CONFR7_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */
+#define JPEG_CONFR7_HSF_0               (0x1UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00001000 */
+#define JPEG_CONFR7_HSF_1               (0x2UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00002000 */
+#define JPEG_CONFR7_HSF_2               (0x4UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00004000 */
+#define JPEG_CONFR7_HSF_3               (0x8UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00008000 */
+
+/********************  Bit definition for CR register  ********************/
+#define JPEG_CR_JCEN_Pos                (0U)
+#define JPEG_CR_JCEN_Msk                (0x1UL << JPEG_CR_JCEN_Pos)            /*!< 0x00000001 */
+#define JPEG_CR_JCEN                    JPEG_CR_JCEN_Msk                       /*!<Enable the JPEG Codec Core */
+#define JPEG_CR_IFTIE_Pos               (1U)
+#define JPEG_CR_IFTIE_Msk               (0x1UL << JPEG_CR_IFTIE_Pos)           /*!< 0x00000002 */
+#define JPEG_CR_IFTIE                   JPEG_CR_IFTIE_Msk                      /*!<Input FIFO Threshold Interrupt Enable */
+#define JPEG_CR_IFNFIE_Pos              (2U)
+#define JPEG_CR_IFNFIE_Msk              (0x1UL << JPEG_CR_IFNFIE_Pos)          /*!< 0x00000004 */
+#define JPEG_CR_IFNFIE                  JPEG_CR_IFNFIE_Msk                     /*!<Input FIFO Not Full Interrupt Enable */
+#define JPEG_CR_OFTIE_Pos               (3U)
+#define JPEG_CR_OFTIE_Msk               (0x1UL << JPEG_CR_OFTIE_Pos)           /*!< 0x00000008 */
+#define JPEG_CR_OFTIE                   JPEG_CR_OFTIE_Msk                      /*!<Output FIFO Threshold Interrupt Enable */
+#define JPEG_CR_OFNEIE_Pos              (4U)
+#define JPEG_CR_OFNEIE_Msk              (0x1UL << JPEG_CR_OFNEIE_Pos)          /*!< 0x00000010 */
+#define JPEG_CR_OFNEIE                  JPEG_CR_OFNEIE_Msk                     /*!<Output FIFO Not Empty Interrupt Enable */
+#define JPEG_CR_EOCIE_Pos               (5U)
+#define JPEG_CR_EOCIE_Msk               (0x1UL << JPEG_CR_EOCIE_Pos)           /*!< 0x00000020 */
+#define JPEG_CR_EOCIE                   JPEG_CR_EOCIE_Msk                      /*!<End of Conversion Interrupt Enable */
+#define JPEG_CR_HPDIE_Pos               (6U)
+#define JPEG_CR_HPDIE_Msk               (0x1UL << JPEG_CR_HPDIE_Pos)           /*!< 0x00000040 */
+#define JPEG_CR_HPDIE                   JPEG_CR_HPDIE_Msk                      /*!<Header Parsing Done Interrupt Enable */
+#define JPEG_CR_IFF_Pos                 (13U)
+#define JPEG_CR_IFF_Msk                 (0x1UL << JPEG_CR_IFF_Pos)             /*!< 0x00002000 */
+#define JPEG_CR_IFF                     JPEG_CR_IFF_Msk                        /*!<Flush the input FIFO */
+#define JPEG_CR_OFF_Pos                 (14U)
+#define JPEG_CR_OFF_Msk                 (0x1UL << JPEG_CR_OFF_Pos)             /*!< 0x00004000 */
+#define JPEG_CR_OFF                     JPEG_CR_OFF_Msk                        /*!<Flush the output FIFO */
+
+/********************  Bit definition for SR register  ********************/
+#define JPEG_SR_IFTF_Pos                (1U)
+#define JPEG_SR_IFTF_Msk                (0x1UL << JPEG_SR_IFTF_Pos)            /*!< 0x00000002 */
+#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is bellow its threshold flag */
+#define JPEG_SR_IFNFF_Pos               (2U)
+#define JPEG_SR_IFNFF_Msk               (0x1UL << JPEG_SR_IFNFF_Pos)           /*!< 0x00000004 */
+#define JPEG_SR_IFNFF                   JPEG_SR_IFNFF_Msk                      /*!<Input FIFO Not Full Flag, a data can be written */
+#define JPEG_SR_OFTF_Pos                (3U)
+#define JPEG_SR_OFTF_Msk                (0x1UL << JPEG_SR_OFTF_Pos)            /*!< 0x00000008 */
+#define JPEG_SR_OFTF                    JPEG_SR_OFTF_Msk                       /*!<Output FIFO is not empty and has reach its threshold */
+#define JPEG_SR_OFNEF_Pos               (4U)
+#define JPEG_SR_OFNEF_Msk               (0x1UL << JPEG_SR_OFNEF_Pos)           /*!< 0x00000010 */
+#define JPEG_SR_OFNEF                   JPEG_SR_OFNEF_Msk                      /*!<Output FIFO is not empty, a data is available */
+#define JPEG_SR_EOCF_Pos                (5U)
+#define JPEG_SR_EOCF_Msk                (0x1UL << JPEG_SR_EOCF_Pos)            /*!< 0x00000020 */
+#define JPEG_SR_EOCF                    JPEG_SR_EOCF_Msk                       /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */
+#define JPEG_SR_HPDF_Pos                (6U)
+#define JPEG_SR_HPDF_Msk                (0x1UL << JPEG_SR_HPDF_Pos)            /*!< 0x00000040 */
+#define JPEG_SR_HPDF                    JPEG_SR_HPDF_Msk                       /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */
+#define JPEG_SR_COF_Pos                 (7U)
+#define JPEG_SR_COF_Msk                 (0x1UL << JPEG_SR_COF_Pos)             /*!< 0x00000080 */
+#define JPEG_SR_COF                     JPEG_SR_COF_Msk                        /*!<JPEG Codec operation on going flag */
+
+/********************  Bit definition for CFR register  ********************/
+#define JPEG_CFR_CEOCF_Pos              (4U)
+#define JPEG_CFR_CEOCF_Msk              (0x1UL << JPEG_CFR_CEOCF_Pos)          /*!< 0x00000010 */
+#define JPEG_CFR_CEOCF                  JPEG_CFR_CEOCF_Msk                     /*!<Clear End of Conversion Flag */
+#define JPEG_CFR_CHPDF_Pos              (5U)
+#define JPEG_CFR_CHPDF_Msk              (0x1UL << JPEG_CFR_CHPDF_Pos)          /*!< 0x00000020 */
+#define JPEG_CFR_CHPDF                  JPEG_CFR_CHPDF_Msk                     /*!<Clear Header Parsing Done Flag */
+
+/********************  Bit definition for DIR register  ********************/
+#define JPEG_DIR_DATAIN_Pos             (0U)
+#define JPEG_DIR_DATAIN_Msk             (0xFFFFFFFFUL << JPEG_DIR_DATAIN_Pos)  /*!< 0xFFFFFFFF */
+#define JPEG_DIR_DATAIN                 JPEG_DIR_DATAIN_Msk                    /*!<Data Input FIFO */
+
+/********************  Bit definition for DOR register  ********************/
+#define JPEG_DOR_DATAOUT_Pos            (0U)
+#define JPEG_DOR_DATAOUT_Msk            (0xFFFFFFFFUL << JPEG_DOR_DATAOUT_Pos) /*!< 0xFFFFFFFF */
+#define JPEG_DOR_DATAOUT                JPEG_DOR_DATAOUT_Msk                   /*!<Data Output FIFO */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      LCD-TFT Display Controller (LTDC)                     */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for LTDC_SSCR register  *****************/
+
+#define LTDC_SSCR_VSH_Pos            (0U)
+#define LTDC_SSCR_VSH_Msk            (0x7FFUL << LTDC_SSCR_VSH_Pos)            /*!< 0x000007FF */
+#define LTDC_SSCR_VSH                LTDC_SSCR_VSH_Msk                         /*!< Vertical Synchronization Height  */
+#define LTDC_SSCR_HSW_Pos            (16U)
+#define LTDC_SSCR_HSW_Msk            (0xFFFUL << LTDC_SSCR_HSW_Pos)            /*!< 0x0FFF0000 */
+#define LTDC_SSCR_HSW                LTDC_SSCR_HSW_Msk                         /*!< Horizontal Synchronization Width */
+
+/********************  Bit definition for LTDC_BPCR register  *****************/
+
+#define LTDC_BPCR_AVBP_Pos           (0U)
+#define LTDC_BPCR_AVBP_Msk           (0x7FFUL << LTDC_BPCR_AVBP_Pos)           /*!< 0x000007FF */
+#define LTDC_BPCR_AVBP               LTDC_BPCR_AVBP_Msk                        /*!< Accumulated Vertical Back Porch   */
+#define LTDC_BPCR_AHBP_Pos           (16U)
+#define LTDC_BPCR_AHBP_Msk           (0xFFFUL << LTDC_BPCR_AHBP_Pos)           /*!< 0x0FFF0000 */
+#define LTDC_BPCR_AHBP               LTDC_BPCR_AHBP_Msk                        /*!< Accumulated Horizontal Back Porch */
+
+/********************  Bit definition for LTDC_AWCR register  *****************/
+
+#define LTDC_AWCR_AAH_Pos            (0U)
+#define LTDC_AWCR_AAH_Msk            (0x7FFUL << LTDC_AWCR_AAH_Pos)            /*!< 0x000007FF */
+#define LTDC_AWCR_AAH                LTDC_AWCR_AAH_Msk                         /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAW_Pos            (16U)
+#define LTDC_AWCR_AAW_Msk            (0xFFFUL << LTDC_AWCR_AAW_Pos)            /*!< 0x0FFF0000 */
+#define LTDC_AWCR_AAW                LTDC_AWCR_AAW_Msk                         /*!< Accumulated Active Width */
+
+/********************  Bit definition for LTDC_TWCR register  *****************/
+
+#define LTDC_TWCR_TOTALH_Pos         (0U)
+#define LTDC_TWCR_TOTALH_Msk         (0x7FFUL << LTDC_TWCR_TOTALH_Pos)         /*!< 0x000007FF */
+#define LTDC_TWCR_TOTALH             LTDC_TWCR_TOTALH_Msk                      /*!< Total Heigh */
+#define LTDC_TWCR_TOTALW_Pos         (16U)
+#define LTDC_TWCR_TOTALW_Msk         (0xFFFUL << LTDC_TWCR_TOTALW_Pos)         /*!< 0x0FFF0000 */
+#define LTDC_TWCR_TOTALW             LTDC_TWCR_TOTALW_Msk                      /*!< Total Width */
+
+/********************  Bit definition for LTDC_GCR register  ******************/
+
+#define LTDC_GCR_LTDCEN_Pos          (0U)
+#define LTDC_GCR_LTDCEN_Msk          (0x1UL << LTDC_GCR_LTDCEN_Pos)            /*!< 0x00000001 */
+#define LTDC_GCR_LTDCEN              LTDC_GCR_LTDCEN_Msk                       /*!< LCD-TFT controller enable bit       */
+#define LTDC_GCR_DBW_Pos             (4U)
+#define LTDC_GCR_DBW_Msk             (0x7UL << LTDC_GCR_DBW_Pos)               /*!< 0x00000070 */
+#define LTDC_GCR_DBW                 LTDC_GCR_DBW_Msk                          /*!< Dither Blue Width                   */
+#define LTDC_GCR_DGW_Pos             (8U)
+#define LTDC_GCR_DGW_Msk             (0x7UL << LTDC_GCR_DGW_Pos)               /*!< 0x00000700 */
+#define LTDC_GCR_DGW                 LTDC_GCR_DGW_Msk                          /*!< Dither Green Width                  */
+#define LTDC_GCR_DRW_Pos             (12U)
+#define LTDC_GCR_DRW_Msk             (0x7UL << LTDC_GCR_DRW_Pos)               /*!< 0x00007000 */
+#define LTDC_GCR_DRW                 LTDC_GCR_DRW_Msk                          /*!< Dither Red Width                    */
+#define LTDC_GCR_DEN_Pos             (16U)
+#define LTDC_GCR_DEN_Msk             (0x1UL << LTDC_GCR_DEN_Pos)               /*!< 0x00010000 */
+#define LTDC_GCR_DEN                 LTDC_GCR_DEN_Msk                          /*!< Dither Enable                       */
+#define LTDC_GCR_PCPOL_Pos           (28U)
+#define LTDC_GCR_PCPOL_Msk           (0x1UL << LTDC_GCR_PCPOL_Pos)             /*!< 0x10000000 */
+#define LTDC_GCR_PCPOL               LTDC_GCR_PCPOL_Msk                        /*!< Pixel Clock Polarity                */
+#define LTDC_GCR_DEPOL_Pos           (29U)
+#define LTDC_GCR_DEPOL_Msk           (0x1UL << LTDC_GCR_DEPOL_Pos)             /*!< 0x20000000 */
+#define LTDC_GCR_DEPOL               LTDC_GCR_DEPOL_Msk                        /*!< Data Enable Polarity                */
+#define LTDC_GCR_VSPOL_Pos           (30U)
+#define LTDC_GCR_VSPOL_Msk           (0x1UL << LTDC_GCR_VSPOL_Pos)             /*!< 0x40000000 */
+#define LTDC_GCR_VSPOL               LTDC_GCR_VSPOL_Msk                        /*!< Vertical Synchronization Polarity   */
+#define LTDC_GCR_HSPOL_Pos           (31U)
+#define LTDC_GCR_HSPOL_Msk           (0x1UL << LTDC_GCR_HSPOL_Pos)             /*!< 0x80000000 */
+#define LTDC_GCR_HSPOL               LTDC_GCR_HSPOL_Msk                        /*!< Horizontal Synchronization Polarity */
+
+
+/********************  Bit definition for LTDC_SRCR register  *****************/
+
+#define LTDC_SRCR_IMR_Pos            (0U)
+#define LTDC_SRCR_IMR_Msk            (0x1UL << LTDC_SRCR_IMR_Pos)              /*!< 0x00000001 */
+#define LTDC_SRCR_IMR                LTDC_SRCR_IMR_Msk                         /*!< Immediate Reload         */
+#define LTDC_SRCR_VBR_Pos            (1U)
+#define LTDC_SRCR_VBR_Msk            (0x1UL << LTDC_SRCR_VBR_Pos)              /*!< 0x00000002 */
+#define LTDC_SRCR_VBR                LTDC_SRCR_VBR_Msk                         /*!< Vertical Blanking Reload */
+
+/********************  Bit definition for LTDC_BCCR register  *****************/
+
+#define LTDC_BCCR_BCBLUE_Pos         (0U)
+#define LTDC_BCCR_BCBLUE_Msk         (0xFFUL << LTDC_BCCR_BCBLUE_Pos)          /*!< 0x000000FF */
+#define LTDC_BCCR_BCBLUE             LTDC_BCCR_BCBLUE_Msk                      /*!< Background Blue value  */
+#define LTDC_BCCR_BCGREEN_Pos        (8U)
+#define LTDC_BCCR_BCGREEN_Msk        (0xFFUL << LTDC_BCCR_BCGREEN_Pos)         /*!< 0x0000FF00 */
+#define LTDC_BCCR_BCGREEN            LTDC_BCCR_BCGREEN_Msk                     /*!< Background Green value */
+#define LTDC_BCCR_BCRED_Pos          (16U)
+#define LTDC_BCCR_BCRED_Msk          (0xFFUL << LTDC_BCCR_BCRED_Pos)           /*!< 0x00FF0000 */
+#define LTDC_BCCR_BCRED              LTDC_BCCR_BCRED_Msk                       /*!< Background Red value   */
+
+/********************  Bit definition for LTDC_IER register  ******************/
+
+#define LTDC_IER_LIE_Pos             (0U)
+#define LTDC_IER_LIE_Msk             (0x1UL << LTDC_IER_LIE_Pos)               /*!< 0x00000001 */
+#define LTDC_IER_LIE                 LTDC_IER_LIE_Msk                          /*!< Line Interrupt Enable            */
+#define LTDC_IER_FUIE_Pos            (1U)
+#define LTDC_IER_FUIE_Msk            (0x1UL << LTDC_IER_FUIE_Pos)              /*!< 0x00000002 */
+#define LTDC_IER_FUIE                LTDC_IER_FUIE_Msk                         /*!< FIFO Underrun Interrupt Enable   */
+#define LTDC_IER_TERRIE_Pos          (2U)
+#define LTDC_IER_TERRIE_Msk          (0x1UL << LTDC_IER_TERRIE_Pos)            /*!< 0x00000004 */
+#define LTDC_IER_TERRIE              LTDC_IER_TERRIE_Msk                       /*!< Transfer Error Interrupt Enable  */
+#define LTDC_IER_RRIE_Pos            (3U)
+#define LTDC_IER_RRIE_Msk            (0x1UL << LTDC_IER_RRIE_Pos)              /*!< 0x00000008 */
+#define LTDC_IER_RRIE                LTDC_IER_RRIE_Msk                         /*!< Register Reload interrupt enable */
+
+/********************  Bit definition for LTDC_ISR register  ******************/
+
+#define LTDC_ISR_LIF_Pos             (0U)
+#define LTDC_ISR_LIF_Msk             (0x1UL << LTDC_ISR_LIF_Pos)               /*!< 0x00000001 */
+#define LTDC_ISR_LIF                 LTDC_ISR_LIF_Msk                          /*!< Line Interrupt Flag */
+#define LTDC_ISR_FUIF_Pos            (1U)
+#define LTDC_ISR_FUIF_Msk            (0x1UL << LTDC_ISR_FUIF_Pos)              /*!< 0x00000002 */
+#define LTDC_ISR_FUIF                LTDC_ISR_FUIF_Msk                         /*!< FIFO Underrun Interrupt Flag */
+#define LTDC_ISR_TERRIF_Pos          (2U)
+#define LTDC_ISR_TERRIF_Msk          (0x1UL << LTDC_ISR_TERRIF_Pos)            /*!< 0x00000004 */
+#define LTDC_ISR_TERRIF              LTDC_ISR_TERRIF_Msk                       /*!< Transfer Error Interrupt Flag */
+#define LTDC_ISR_RRIF_Pos            (3U)
+#define LTDC_ISR_RRIF_Msk            (0x1UL << LTDC_ISR_RRIF_Pos)              /*!< 0x00000008 */
+#define LTDC_ISR_RRIF                LTDC_ISR_RRIF_Msk                         /*!< Register Reload interrupt Flag */
+
+/********************  Bit definition for LTDC_ICR register  ******************/
+
+#define LTDC_ICR_CLIF_Pos            (0U)
+#define LTDC_ICR_CLIF_Msk            (0x1UL << LTDC_ICR_CLIF_Pos)              /*!< 0x00000001 */
+#define LTDC_ICR_CLIF                LTDC_ICR_CLIF_Msk                         /*!< Clears the Line Interrupt Flag */
+#define LTDC_ICR_CFUIF_Pos           (1U)
+#define LTDC_ICR_CFUIF_Msk           (0x1UL << LTDC_ICR_CFUIF_Pos)             /*!< 0x00000002 */
+#define LTDC_ICR_CFUIF               LTDC_ICR_CFUIF_Msk                        /*!< Clears the FIFO Underrun Interrupt Flag */
+#define LTDC_ICR_CTERRIF_Pos         (2U)
+#define LTDC_ICR_CTERRIF_Msk         (0x1UL << LTDC_ICR_CTERRIF_Pos)           /*!< 0x00000004 */
+#define LTDC_ICR_CTERRIF             LTDC_ICR_CTERRIF_Msk                      /*!< Clears the Transfer Error Interrupt Flag */
+#define LTDC_ICR_CRRIF_Pos           (3U)
+#define LTDC_ICR_CRRIF_Msk           (0x1UL << LTDC_ICR_CRRIF_Pos)             /*!< 0x00000008 */
+#define LTDC_ICR_CRRIF               LTDC_ICR_CRRIF_Msk                        /*!< Clears Register Reload interrupt Flag */
+
+/********************  Bit definition for LTDC_LIPCR register  ****************/
+
+#define LTDC_LIPCR_LIPOS_Pos         (0U)
+#define LTDC_LIPCR_LIPOS_Msk         (0x7FFUL << LTDC_LIPCR_LIPOS_Pos)         /*!< 0x000007FF */
+#define LTDC_LIPCR_LIPOS             LTDC_LIPCR_LIPOS_Msk                      /*!< Line Interrupt Position */
+
+/********************  Bit definition for LTDC_CPSR register  *****************/
+
+#define LTDC_CPSR_CYPOS_Pos          (0U)
+#define LTDC_CPSR_CYPOS_Msk          (0xFFFFUL << LTDC_CPSR_CYPOS_Pos)         /*!< 0x0000FFFF */
+#define LTDC_CPSR_CYPOS              LTDC_CPSR_CYPOS_Msk                       /*!< Current Y Position */
+#define LTDC_CPSR_CXPOS_Pos          (16U)
+#define LTDC_CPSR_CXPOS_Msk          (0xFFFFUL << LTDC_CPSR_CXPOS_Pos)         /*!< 0xFFFF0000 */
+#define LTDC_CPSR_CXPOS              LTDC_CPSR_CXPOS_Msk                       /*!< Current X Position */
+
+/********************  Bit definition for LTDC_CDSR register  *****************/
+
+#define LTDC_CDSR_VDES_Pos           (0U)
+#define LTDC_CDSR_VDES_Msk           (0x1UL << LTDC_CDSR_VDES_Pos)             /*!< 0x00000001 */
+#define LTDC_CDSR_VDES               LTDC_CDSR_VDES_Msk                        /*!< Vertical Data Enable Status       */
+#define LTDC_CDSR_HDES_Pos           (1U)
+#define LTDC_CDSR_HDES_Msk           (0x1UL << LTDC_CDSR_HDES_Pos)             /*!< 0x00000002 */
+#define LTDC_CDSR_HDES               LTDC_CDSR_HDES_Msk                        /*!< Horizontal Data Enable Status     */
+#define LTDC_CDSR_VSYNCS_Pos         (2U)
+#define LTDC_CDSR_VSYNCS_Msk         (0x1UL << LTDC_CDSR_VSYNCS_Pos)           /*!< 0x00000004 */
+#define LTDC_CDSR_VSYNCS             LTDC_CDSR_VSYNCS_Msk                      /*!< Vertical Synchronization Status   */
+#define LTDC_CDSR_HSYNCS_Pos         (3U)
+#define LTDC_CDSR_HSYNCS_Msk         (0x1UL << LTDC_CDSR_HSYNCS_Pos)           /*!< 0x00000008 */
+#define LTDC_CDSR_HSYNCS             LTDC_CDSR_HSYNCS_Msk                      /*!< Horizontal Synchronization Status */
+
+/********************  Bit definition for LTDC_LxCR register  *****************/
+
+#define LTDC_LxCR_LEN_Pos            (0U)
+#define LTDC_LxCR_LEN_Msk            (0x1UL << LTDC_LxCR_LEN_Pos)              /*!< 0x00000001 */
+#define LTDC_LxCR_LEN                LTDC_LxCR_LEN_Msk                         /*!< Layer Enable              */
+#define LTDC_LxCR_COLKEN_Pos         (1U)
+#define LTDC_LxCR_COLKEN_Msk         (0x1UL << LTDC_LxCR_COLKEN_Pos)           /*!< 0x00000002 */
+#define LTDC_LxCR_COLKEN             LTDC_LxCR_COLKEN_Msk                      /*!< Color Keying Enable       */
+#define LTDC_LxCR_CLUTEN_Pos         (4U)
+#define LTDC_LxCR_CLUTEN_Msk         (0x1UL << LTDC_LxCR_CLUTEN_Pos)           /*!< 0x00000010 */
+#define LTDC_LxCR_CLUTEN             LTDC_LxCR_CLUTEN_Msk                      /*!< Color Lockup Table Enable */
+
+/********************  Bit definition for LTDC_LxWHPCR register  **************/
+
+#define LTDC_LxWHPCR_WHSTPOS_Pos     (0U)
+#define LTDC_LxWHPCR_WHSTPOS_Msk     (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos)     /*!< 0x00000FFF */
+#define LTDC_LxWHPCR_WHSTPOS         LTDC_LxWHPCR_WHSTPOS_Msk                  /*!< Window Horizontal Start Position */
+#define LTDC_LxWHPCR_WHSPPOS_Pos     (16U)
+#define LTDC_LxWHPCR_WHSPPOS_Msk     (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos)    /*!< 0xFFFF0000 */
+#define LTDC_LxWHPCR_WHSPPOS         LTDC_LxWHPCR_WHSPPOS_Msk                  /*!< Window Horizontal Stop Position  */
+
+/********************  Bit definition for LTDC_LxWVPCR register  **************/
+
+#define LTDC_LxWVPCR_WVSTPOS_Pos     (0U)
+#define LTDC_LxWVPCR_WVSTPOS_Msk     (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos)     /*!< 0x00000FFF */
+#define LTDC_LxWVPCR_WVSTPOS         LTDC_LxWVPCR_WVSTPOS_Msk                  /*!< Window Vertical Start Position */
+#define LTDC_LxWVPCR_WVSPPOS_Pos     (16U)
+#define LTDC_LxWVPCR_WVSPPOS_Msk     (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos)    /*!< 0xFFFF0000 */
+#define LTDC_LxWVPCR_WVSPPOS         LTDC_LxWVPCR_WVSPPOS_Msk                  /*!< Window Vertical Stop Position  */
+
+/********************  Bit definition for LTDC_LxCKCR register  ***************/
+
+#define LTDC_LxCKCR_CKBLUE_Pos       (0U)
+#define LTDC_LxCKCR_CKBLUE_Msk       (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos)        /*!< 0x000000FF */
+#define LTDC_LxCKCR_CKBLUE           LTDC_LxCKCR_CKBLUE_Msk                    /*!< Color Key Blue value  */
+#define LTDC_LxCKCR_CKGREEN_Pos      (8U)
+#define LTDC_LxCKCR_CKGREEN_Msk      (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos)       /*!< 0x0000FF00 */
+#define LTDC_LxCKCR_CKGREEN          LTDC_LxCKCR_CKGREEN_Msk                   /*!< Color Key Green value */
+#define LTDC_LxCKCR_CKRED_Pos        (16U)
+#define LTDC_LxCKCR_CKRED_Msk        (0xFFUL << LTDC_LxCKCR_CKRED_Pos)         /*!< 0x00FF0000 */
+#define LTDC_LxCKCR_CKRED            LTDC_LxCKCR_CKRED_Msk                     /*!< Color Key Red value   */
+
+/********************  Bit definition for LTDC_LxPFCR register  ***************/
+
+#define LTDC_LxPFCR_PF_Pos           (0U)
+#define LTDC_LxPFCR_PF_Msk           (0x7UL << LTDC_LxPFCR_PF_Pos)             /*!< 0x00000007 */
+#define LTDC_LxPFCR_PF               LTDC_LxPFCR_PF_Msk                        /*!< Pixel Format */
+
+/********************  Bit definition for LTDC_LxCACR register  ***************/
+
+#define LTDC_LxCACR_CONSTA_Pos       (0U)
+#define LTDC_LxCACR_CONSTA_Msk       (0xFFUL << LTDC_LxCACR_CONSTA_Pos)        /*!< 0x000000FF */
+#define LTDC_LxCACR_CONSTA           LTDC_LxCACR_CONSTA_Msk                    /*!< Constant Alpha */
+
+/********************  Bit definition for LTDC_LxDCCR register  ***************/
+
+#define LTDC_LxDCCR_DCBLUE_Pos       (0U)
+#define LTDC_LxDCCR_DCBLUE_Msk       (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos)        /*!< 0x000000FF */
+#define LTDC_LxDCCR_DCBLUE           LTDC_LxDCCR_DCBLUE_Msk                    /*!< Default Color Blue  */
+#define LTDC_LxDCCR_DCGREEN_Pos      (8U)
+#define LTDC_LxDCCR_DCGREEN_Msk      (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos)       /*!< 0x0000FF00 */
+#define LTDC_LxDCCR_DCGREEN          LTDC_LxDCCR_DCGREEN_Msk                   /*!< Default Color Green */
+#define LTDC_LxDCCR_DCRED_Pos        (16U)
+#define LTDC_LxDCCR_DCRED_Msk        (0xFFUL << LTDC_LxDCCR_DCRED_Pos)         /*!< 0x00FF0000 */
+#define LTDC_LxDCCR_DCRED            LTDC_LxDCCR_DCRED_Msk                     /*!< Default Color Red   */
+#define LTDC_LxDCCR_DCALPHA_Pos      (24U)
+#define LTDC_LxDCCR_DCALPHA_Msk      (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos)       /*!< 0xFF000000 */
+#define LTDC_LxDCCR_DCALPHA          LTDC_LxDCCR_DCALPHA_Msk                   /*!< Default Color Alpha */
+
+/********************  Bit definition for LTDC_LxBFCR register  ***************/
+
+#define LTDC_LxBFCR_BF2_Pos          (0U)
+#define LTDC_LxBFCR_BF2_Msk          (0x7UL << LTDC_LxBFCR_BF2_Pos)            /*!< 0x00000007 */
+#define LTDC_LxBFCR_BF2              LTDC_LxBFCR_BF2_Msk                       /*!< Blending Factor 2 */
+#define LTDC_LxBFCR_BF1_Pos          (8U)
+#define LTDC_LxBFCR_BF1_Msk          (0x7UL << LTDC_LxBFCR_BF1_Pos)            /*!< 0x00000700 */
+#define LTDC_LxBFCR_BF1              LTDC_LxBFCR_BF1_Msk                       /*!< Blending Factor 1 */
+
+/********************  Bit definition for LTDC_LxCFBAR register  **************/
+
+#define LTDC_LxCFBAR_CFBADD_Pos      (0U)
+#define LTDC_LxCFBAR_CFBADD_Msk      (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */
+#define LTDC_LxCFBAR_CFBADD          LTDC_LxCFBAR_CFBADD_Msk                   /*!< Color Frame Buffer Start Address */
+
+/********************  Bit definition for LTDC_LxCFBLR register  **************/
+
+#define LTDC_LxCFBLR_CFBLL_Pos       (0U)
+#define LTDC_LxCFBLR_CFBLL_Msk       (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos)      /*!< 0x00001FFF */
+#define LTDC_LxCFBLR_CFBLL           LTDC_LxCFBLR_CFBLL_Msk                    /*!< Color Frame Buffer Line Length    */
+#define LTDC_LxCFBLR_CFBP_Pos        (16U)
+#define LTDC_LxCFBLR_CFBP_Msk        (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos)       /*!< 0x1FFF0000 */
+#define LTDC_LxCFBLR_CFBP            LTDC_LxCFBLR_CFBP_Msk                     /*!< Color Frame Buffer Pitch in bytes */
+
+/********************  Bit definition for LTDC_LxCFBLNR register  *************/
+
+#define LTDC_LxCFBLNR_CFBLNBR_Pos    (0U)
+#define LTDC_LxCFBLNR_CFBLNBR_Msk    (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos)    /*!< 0x000007FF */
+#define LTDC_LxCFBLNR_CFBLNBR        LTDC_LxCFBLNR_CFBLNBR_Msk                 /*!< Frame Buffer Line Number */
+
+/********************  Bit definition for LTDC_LxCLUTWR register  *************/
+
+#define LTDC_LxCLUTWR_BLUE_Pos       (0U)
+#define LTDC_LxCLUTWR_BLUE_Msk       (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos)        /*!< 0x000000FF */
+#define LTDC_LxCLUTWR_BLUE           LTDC_LxCLUTWR_BLUE_Msk                    /*!< Blue value   */
+#define LTDC_LxCLUTWR_GREEN_Pos      (8U)
+#define LTDC_LxCLUTWR_GREEN_Msk      (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos)       /*!< 0x0000FF00 */
+#define LTDC_LxCLUTWR_GREEN          LTDC_LxCLUTWR_GREEN_Msk                   /*!< Green value  */
+#define LTDC_LxCLUTWR_RED_Pos        (16U)
+#define LTDC_LxCLUTWR_RED_Msk        (0xFFUL << LTDC_LxCLUTWR_RED_Pos)         /*!< 0x00FF0000 */
+#define LTDC_LxCLUTWR_RED            LTDC_LxCLUTWR_RED_Msk                     /*!< Red value    */
+#define LTDC_LxCLUTWR_CLUTADD_Pos    (24U)
+#define LTDC_LxCLUTWR_CLUTADD_Msk    (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos)     /*!< 0xFF000000 */
+#define LTDC_LxCLUTWR_CLUTADD        LTDC_LxCLUTWR_CLUTADD_Msk                 /*!< CLUT address */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                     MDMA                                   */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for MDMA_GISR0 register  ****************/
+#define MDMA_GISR0_GIF0_Pos       (0U)
+#define MDMA_GISR0_GIF0_Msk       (0x1UL << MDMA_GISR0_GIF0_Pos)               /*!< 0x00000001 */
+#define MDMA_GISR0_GIF0           MDMA_GISR0_GIF0_Msk                          /*!< Channel 0 global interrupt flag */
+#define MDMA_GISR0_GIF1_Pos       (1U)
+#define MDMA_GISR0_GIF1_Msk       (0x1UL << MDMA_GISR0_GIF1_Pos)               /*!< 0x00000002 */
+#define MDMA_GISR0_GIF1           MDMA_GISR0_GIF1_Msk                          /*!< Channel 1 global interrupt flag */
+#define MDMA_GISR0_GIF2_Pos       (2U)
+#define MDMA_GISR0_GIF2_Msk       (0x1UL << MDMA_GISR0_GIF2_Pos)               /*!< 0x00000004 */
+#define MDMA_GISR0_GIF2           MDMA_GISR0_GIF2_Msk                          /*!< Channel 2 global interrupt flag */
+#define MDMA_GISR0_GIF3_Pos       (3U)
+#define MDMA_GISR0_GIF3_Msk       (0x1UL << MDMA_GISR0_GIF3_Pos)               /*!< 0x00000008 */
+#define MDMA_GISR0_GIF3           MDMA_GISR0_GIF3_Msk                          /*!< Channel 3 global interrupt flag */
+#define MDMA_GISR0_GIF4_Pos       (4U)
+#define MDMA_GISR0_GIF4_Msk       (0x1UL << MDMA_GISR0_GIF4_Pos)               /*!< 0x00000010 */
+#define MDMA_GISR0_GIF4           MDMA_GISR0_GIF4_Msk                          /*!< Channel 4 global interrupt flag */
+#define MDMA_GISR0_GIF5_Pos       (5U)
+#define MDMA_GISR0_GIF5_Msk       (0x1UL << MDMA_GISR0_GIF5_Pos)               /*!< 0x00000020 */
+#define MDMA_GISR0_GIF5           MDMA_GISR0_GIF5_Msk                          /*!< Channel 5 global interrupt flag */
+#define MDMA_GISR0_GIF6_Pos       (6U)
+#define MDMA_GISR0_GIF6_Msk       (0x1UL << MDMA_GISR0_GIF6_Pos)               /*!< 0x00000040 */
+#define MDMA_GISR0_GIF6           MDMA_GISR0_GIF6_Msk                          /*!< Channel 6 global interrupt flag */
+#define MDMA_GISR0_GIF7_Pos       (7U)
+#define MDMA_GISR0_GIF7_Msk       (0x1UL << MDMA_GISR0_GIF7_Pos)               /*!< 0x00000080 */
+#define MDMA_GISR0_GIF7           MDMA_GISR0_GIF7_Msk                          /*!< Channel 7 global interrupt flag */
+#define MDMA_GISR0_GIF8_Pos       (8U)
+#define MDMA_GISR0_GIF8_Msk       (0x1UL << MDMA_GISR0_GIF8_Pos)               /*!< 0x00000100 */
+#define MDMA_GISR0_GIF8           MDMA_GISR0_GIF8_Msk                          /*!< Channel 8 global interrupt flag */
+#define MDMA_GISR0_GIF9_Pos       (9U)
+#define MDMA_GISR0_GIF9_Msk       (0x1UL << MDMA_GISR0_GIF9_Pos)               /*!< 0x00000200 */
+#define MDMA_GISR0_GIF9           MDMA_GISR0_GIF9_Msk                          /*!< Channel 9 global interrupt flag */
+#define MDMA_GISR0_GIF10_Pos      (10U)
+#define MDMA_GISR0_GIF10_Msk      (0x1UL << MDMA_GISR0_GIF10_Pos)              /*!< 0x00000400 */
+#define MDMA_GISR0_GIF10          MDMA_GISR0_GIF10_Msk                         /*!< Channel 10 global interrupt flag */
+#define MDMA_GISR0_GIF11_Pos      (11U)
+#define MDMA_GISR0_GIF11_Msk      (0x1UL << MDMA_GISR0_GIF11_Pos)              /*!< 0x00000800 */
+#define MDMA_GISR0_GIF11          MDMA_GISR0_GIF11_Msk                         /*!< Channel 11 global interrupt flag */
+#define MDMA_GISR0_GIF12_Pos      (12U)
+#define MDMA_GISR0_GIF12_Msk      (0x1UL << MDMA_GISR0_GIF12_Pos)              /*!< 0x00001000 */
+#define MDMA_GISR0_GIF12          MDMA_GISR0_GIF12_Msk                         /*!< Channel 12 global interrupt flag */
+#define MDMA_GISR0_GIF13_Pos      (13U)
+#define MDMA_GISR0_GIF13_Msk      (0x1UL << MDMA_GISR0_GIF13_Pos)              /*!< 0x00002000 */
+#define MDMA_GISR0_GIF13          MDMA_GISR0_GIF13_Msk                         /*!< Channel 13 global interrupt flag */
+#define MDMA_GISR0_GIF14_Pos      (14U)
+#define MDMA_GISR0_GIF14_Msk      (0x1UL << MDMA_GISR0_GIF14_Pos)              /*!< 0x00004000 */
+#define MDMA_GISR0_GIF14          MDMA_GISR0_GIF14_Msk                         /*!< Channel 14 global interrupt flag */
+#define MDMA_GISR0_GIF15_Pos      (15U)
+#define MDMA_GISR0_GIF15_Msk      (0x1UL << MDMA_GISR0_GIF15_Pos)              /*!< 0x00008000 */
+#define MDMA_GISR0_GIF15          MDMA_GISR0_GIF15_Msk                         /*!< Channel 15 global interrupt flag */
+
+/********************  Bit definition for MDMA_CxISR register  ****************/
+#define MDMA_CISR_TEIF_Pos        (0U)
+#define MDMA_CISR_TEIF_Msk        (0x1UL << MDMA_CISR_TEIF_Pos)                /*!< 0x00000001 */
+#define MDMA_CISR_TEIF            MDMA_CISR_TEIF_Msk                           /*!< Channel x transfer error interrupt flag */
+#define MDMA_CISR_CTCIF_Pos       (1U)
+#define MDMA_CISR_CTCIF_Msk       (0x1UL << MDMA_CISR_CTCIF_Pos)               /*!< 0x00000002 */
+#define MDMA_CISR_CTCIF           MDMA_CISR_CTCIF_Msk                          /*!< Channel x Channel Transfer Complete interrupt flag */
+#define MDMA_CISR_BRTIF_Pos       (2U)
+#define MDMA_CISR_BRTIF_Msk       (0x1UL << MDMA_CISR_BRTIF_Pos)               /*!< 0x00000004 */
+#define MDMA_CISR_BRTIF           MDMA_CISR_BRTIF_Msk                          /*!< Channel x block repeat transfer complete interrupt flag */
+#define MDMA_CISR_BTIF_Pos        (3U)
+#define MDMA_CISR_BTIF_Msk        (0x1UL << MDMA_CISR_BTIF_Pos)                /*!< 0x00000008 */
+#define MDMA_CISR_BTIF            MDMA_CISR_BTIF_Msk                           /*!< Channel x block transfer complete interrupt flag */
+#define MDMA_CISR_TCIF_Pos        (4U)
+#define MDMA_CISR_TCIF_Msk        (0x1UL << MDMA_CISR_TCIF_Pos)                /*!< 0x00000010 */
+#define MDMA_CISR_TCIF            MDMA_CISR_TCIF_Msk                           /*!< Channel x buffer transfer complete interrupt flag */
+#define MDMA_CISR_CRQA_Pos        (16U)
+#define MDMA_CISR_CRQA_Msk        (0x1UL << MDMA_CISR_CRQA_Pos)                /*!< 0x00010000 */
+#define MDMA_CISR_CRQA            MDMA_CISR_CRQA_Msk                           /*!< Channel x ReQest Active flag */
+
+/********************  Bit definition for MDMA_CxIFCR register  ****************/
+#define MDMA_CIFCR_CTEIF_Pos      (0U)
+#define MDMA_CIFCR_CTEIF_Msk      (0x1UL << MDMA_CIFCR_CTEIF_Pos)              /*!< 0x00000001 */
+#define MDMA_CIFCR_CTEIF          MDMA_CIFCR_CTEIF_Msk                         /*!< Channel x clear transfer error interrupt flag */
+#define MDMA_CIFCR_CCTCIF_Pos     (1U)
+#define MDMA_CIFCR_CCTCIF_Msk     (0x1UL << MDMA_CIFCR_CCTCIF_Pos)             /*!< 0x00000002 */
+#define MDMA_CIFCR_CCTCIF         MDMA_CIFCR_CCTCIF_Msk                        /*!< Clear Channel transfer complete interrupt flag for channel x */
+#define MDMA_CIFCR_CBRTIF_Pos     (2U)
+#define MDMA_CIFCR_CBRTIF_Msk     (0x1UL << MDMA_CIFCR_CBRTIF_Pos)             /*!< 0x00000004 */
+#define MDMA_CIFCR_CBRTIF         MDMA_CIFCR_CBRTIF_Msk                        /*!< Channel x clear block repeat transfer complete interrupt flag */
+#define MDMA_CIFCR_CBTIF_Pos      (3U)
+#define MDMA_CIFCR_CBTIF_Msk      (0x1UL << MDMA_CIFCR_CBTIF_Pos)              /*!< 0x00000008 */
+#define MDMA_CIFCR_CBTIF          MDMA_CIFCR_CBTIF_Msk                         /*!< Channel x Clear block transfer complete interrupt flag */
+#define MDMA_CIFCR_CLTCIF_Pos     (4U)
+#define MDMA_CIFCR_CLTCIF_Msk     (0x1UL << MDMA_CIFCR_CLTCIF_Pos)             /*!< 0x00000010 */
+#define MDMA_CIFCR_CLTCIF         MDMA_CIFCR_CLTCIF_Msk                        /*!< CLear Transfer buffer Complete Interrupt Flag for channel */
+
+/********************  Bit definition for MDMA_CxESR register  ****************/
+#define MDMA_CESR_TEA_Pos         (0U)
+#define MDMA_CESR_TEA_Msk         (0x7FUL << MDMA_CESR_TEA_Pos)                /*!< 0x0000007F */
+#define MDMA_CESR_TEA             MDMA_CESR_TEA_Msk                            /*!< Transfer Error Address */
+#define MDMA_CESR_TED_Pos         (7U)
+#define MDMA_CESR_TED_Msk         (0x1UL << MDMA_CESR_TED_Pos)                 /*!< 0x00000080 */
+#define MDMA_CESR_TED             MDMA_CESR_TED_Msk                            /*!< Transfer Error Direction */
+#define MDMA_CESR_TELD_Pos        (8U)
+#define MDMA_CESR_TELD_Msk        (0x1UL << MDMA_CESR_TELD_Pos)                /*!< 0x00000100 */
+#define MDMA_CESR_TELD            MDMA_CESR_TELD_Msk                           /*!< Transfer Error Link Data */
+#define MDMA_CESR_TEMD_Pos        (9U)
+#define MDMA_CESR_TEMD_Msk        (0x1UL << MDMA_CESR_TEMD_Pos)                /*!< 0x00000200 */
+#define MDMA_CESR_TEMD            MDMA_CESR_TEMD_Msk                           /*!< Transfer Error Mask Data */
+#define MDMA_CESR_ASE_Pos         (10U)
+#define MDMA_CESR_ASE_Msk         (0x1UL << MDMA_CESR_ASE_Pos)                 /*!< 0x00000400 */
+#define MDMA_CESR_ASE             MDMA_CESR_ASE_Msk                            /*!< Address/Size Error       */
+#define MDMA_CESR_BSE_Pos         (11U)
+#define MDMA_CESR_BSE_Msk         (0x1UL << MDMA_CESR_BSE_Pos)                 /*!< 0x00000800 */
+#define MDMA_CESR_BSE             MDMA_CESR_BSE_Msk                            /*!< Block Size Error         */
+
+/********************  Bit definition for MDMA_CxCR register  ****************/
+#define MDMA_CCR_EN_Pos           (0U)
+#define MDMA_CCR_EN_Msk           (0x1UL << MDMA_CCR_EN_Pos)                   /*!< 0x00000001 */
+#define MDMA_CCR_EN               MDMA_CCR_EN_Msk                              /*!< Channel enable / flag channel ready when read low */
+#define MDMA_CCR_TEIE_Pos         (1U)
+#define MDMA_CCR_TEIE_Msk         (0x1UL << MDMA_CCR_TEIE_Pos)                 /*!< 0x00000002 */
+#define MDMA_CCR_TEIE             MDMA_CCR_TEIE_Msk                            /*!< Transfer error interrupt enable */
+#define MDMA_CCR_CTCIE_Pos        (2U)
+#define MDMA_CCR_CTCIE_Msk        (0x1UL << MDMA_CCR_CTCIE_Pos)                /*!< 0x00000004 */
+#define MDMA_CCR_CTCIE            MDMA_CCR_CTCIE_Msk                           /*!< Channel Transfer Complete interrupt enable */
+#define MDMA_CCR_BRTIE_Pos        (3U)
+#define MDMA_CCR_BRTIE_Msk        (0x1UL << MDMA_CCR_BRTIE_Pos)                /*!< 0x00000008 */
+#define MDMA_CCR_BRTIE            MDMA_CCR_BRTIE_Msk                           /*!< Block Repeat transfer interrupt enable */
+#define MDMA_CCR_BTIE_Pos         (4U)
+#define MDMA_CCR_BTIE_Msk         (0x1UL << MDMA_CCR_BTIE_Pos)                 /*!< 0x00000010 */
+#define MDMA_CCR_BTIE             MDMA_CCR_BTIE_Msk                            /*!< Block Transfer interrupt enable */
+#define MDMA_CCR_TCIE_Pos         (5U)
+#define MDMA_CCR_TCIE_Msk         (0x1UL << MDMA_CCR_TCIE_Pos)                 /*!< 0x00000020 */
+#define MDMA_CCR_TCIE             MDMA_CCR_TCIE_Msk                            /*!< buffer Transfer Complete interrupt enable */
+#define MDMA_CCR_PL_Pos           (6U)
+#define MDMA_CCR_PL_Msk           (0x3UL << MDMA_CCR_PL_Pos)                   /*!< 0x000000C0 */
+#define MDMA_CCR_PL               MDMA_CCR_PL_Msk                              /*!< Priority level */
+#define MDMA_CCR_PL_0             (0x1UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000040 */
+#define MDMA_CCR_PL_1             (0x2UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000080 */
+#define MDMA_CCR_BEX_Pos          (12U)
+#define MDMA_CCR_BEX_Msk          (0x1UL << MDMA_CCR_BEX_Pos)                  /*!< 0x00001000 */
+#define MDMA_CCR_BEX              MDMA_CCR_BEX_Msk                             /*!< Byte Endianess eXchange */
+#define MDMA_CCR_HEX_Pos          (13U)
+#define MDMA_CCR_HEX_Msk          (0x1UL << MDMA_CCR_HEX_Pos)                  /*!< 0x00002000 */
+#define MDMA_CCR_HEX              MDMA_CCR_HEX_Msk                             /*!< Half word Endianess eXchange */
+#define MDMA_CCR_WEX_Pos          (14U)
+#define MDMA_CCR_WEX_Msk          (0x1UL << MDMA_CCR_WEX_Pos)                  /*!< 0x00004000 */
+#define MDMA_CCR_WEX              MDMA_CCR_WEX_Msk                             /*!< Word Endianess eXchange */
+#define MDMA_CCR_SWRQ_Pos         (16U)
+#define MDMA_CCR_SWRQ_Msk         (0x1UL << MDMA_CCR_SWRQ_Pos)                 /*!< 0x00010000 */
+#define MDMA_CCR_SWRQ             MDMA_CCR_SWRQ_Msk                            /*!< SW ReQuest */
+
+/********************  Bit definition for MDMA_CxTCR register  ****************/
+#define MDMA_CTCR_SINC_Pos        (0U)
+#define MDMA_CTCR_SINC_Msk        (0x3UL << MDMA_CTCR_SINC_Pos)                /*!< 0x00000003 */
+#define MDMA_CTCR_SINC            MDMA_CTCR_SINC_Msk                           /*!< Source increment mode */
+#define MDMA_CTCR_SINC_0          (0x1UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000001 */
+#define MDMA_CTCR_SINC_1          (0x2UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000002 */
+#define MDMA_CTCR_DINC_Pos        (2U)
+#define MDMA_CTCR_DINC_Msk        (0x3UL << MDMA_CTCR_DINC_Pos)                /*!< 0x0000000C */
+#define MDMA_CTCR_DINC            MDMA_CTCR_DINC_Msk                           /*!< Source increment mode */
+#define MDMA_CTCR_DINC_0          (0x1UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000004 */
+#define MDMA_CTCR_DINC_1          (0x2UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000008 */
+#define MDMA_CTCR_SSIZE_Pos       (4U)
+#define MDMA_CTCR_SSIZE_Msk       (0x3UL << MDMA_CTCR_SSIZE_Pos)               /*!< 0x00000030 */
+#define MDMA_CTCR_SSIZE           MDMA_CTCR_SSIZE_Msk                          /*!< Source data size */
+#define MDMA_CTCR_SSIZE_0         (0x1UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000010 */
+#define MDMA_CTCR_SSIZE_1         (0x2UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000020 */
+#define MDMA_CTCR_DSIZE_Pos       (6U)
+#define MDMA_CTCR_DSIZE_Msk       (0x3UL << MDMA_CTCR_DSIZE_Pos)               /*!< 0x000000C0 */
+#define MDMA_CTCR_DSIZE           MDMA_CTCR_DSIZE_Msk                          /*!< Destination data size */
+#define MDMA_CTCR_DSIZE_0         (0x1UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000040 */
+#define MDMA_CTCR_DSIZE_1         (0x2UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000080 */
+#define MDMA_CTCR_SINCOS_Pos      (8U)
+#define MDMA_CTCR_SINCOS_Msk      (0x3UL << MDMA_CTCR_SINCOS_Pos)              /*!< 0x00000300 */
+#define MDMA_CTCR_SINCOS          MDMA_CTCR_SINCOS_Msk                         /*!< Source increment offset size */
+#define MDMA_CTCR_SINCOS_0        (0x1UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000100 */
+#define MDMA_CTCR_SINCOS_1        (0x2UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000200 */
+#define MDMA_CTCR_DINCOS_Pos      (10U)
+#define MDMA_CTCR_DINCOS_Msk      (0x3UL << MDMA_CTCR_DINCOS_Pos)              /*!< 0x00000C00 */
+#define MDMA_CTCR_DINCOS          MDMA_CTCR_DINCOS_Msk                         /*!< Destination increment offset size */
+#define MDMA_CTCR_DINCOS_0        (0x1UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000400 */
+#define MDMA_CTCR_DINCOS_1        (0x2UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000800 */
+#define MDMA_CTCR_SBURST_Pos      (12U)
+#define MDMA_CTCR_SBURST_Msk      (0x7UL << MDMA_CTCR_SBURST_Pos)              /*!< 0x00007000 */
+#define MDMA_CTCR_SBURST          MDMA_CTCR_SBURST_Msk                         /*!< Source burst transfer configuration */
+#define MDMA_CTCR_SBURST_0        (0x1UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00001000 */
+#define MDMA_CTCR_SBURST_1        (0x2UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00002000 */
+#define MDMA_CTCR_SBURST_2        (0x4UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00004000 */
+#define MDMA_CTCR_DBURST_Pos      (15U)
+#define MDMA_CTCR_DBURST_Msk      (0x7UL << MDMA_CTCR_DBURST_Pos)              /*!< 0x00038000 */
+#define MDMA_CTCR_DBURST          MDMA_CTCR_DBURST_Msk                         /*!< Destination burst transfer configuration */
+#define MDMA_CTCR_DBURST_0        (0x1UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00008000 */
+#define MDMA_CTCR_DBURST_1        (0x2UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00010000 */
+#define MDMA_CTCR_DBURST_2        (0x4UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00020000 */
+#define MDMA_CTCR_TLEN_Pos        (18U)
+#define MDMA_CTCR_TLEN_Msk        (0x7FUL << MDMA_CTCR_TLEN_Pos)               /*!< 0x01FC0000 */
+#define MDMA_CTCR_TLEN            MDMA_CTCR_TLEN_Msk                           /*!< buffer Transfer Length (number of bytes - 1) */
+#define MDMA_CTCR_PKE_Pos         (25U)
+#define MDMA_CTCR_PKE_Msk         (0x1UL << MDMA_CTCR_PKE_Pos)                 /*!< 0x02000000 */
+#define MDMA_CTCR_PKE             MDMA_CTCR_PKE_Msk                            /*!< PacK Enable */
+#define MDMA_CTCR_PAM_Pos         (26U)
+#define MDMA_CTCR_PAM_Msk         (0x3UL << MDMA_CTCR_PAM_Pos)                 /*!< 0x0C000000 */
+#define MDMA_CTCR_PAM             MDMA_CTCR_PAM_Msk                            /*!< Padding/Alignement Mode */
+#define MDMA_CTCR_PAM_0           (0x1UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x4000000 */
+#define MDMA_CTCR_PAM_1           (0x2UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x8000000 */
+#define MDMA_CTCR_TRGM_Pos        (28U)
+#define MDMA_CTCR_TRGM_Msk        (0x3UL << MDMA_CTCR_TRGM_Pos)                /*!< 0x30000000 */
+#define MDMA_CTCR_TRGM            MDMA_CTCR_TRGM_Msk                           /*!< Trigger Mode */
+#define MDMA_CTCR_TRGM_0          (0x1UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x10000000 */
+#define MDMA_CTCR_TRGM_1          (0x2UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x20000000 */
+#define MDMA_CTCR_SWRM_Pos        (30U)
+#define MDMA_CTCR_SWRM_Msk        (0x1UL << MDMA_CTCR_SWRM_Pos)                /*!< 0x40000000 */
+#define MDMA_CTCR_SWRM            MDMA_CTCR_SWRM_Msk                           /*!< SW Request Mode */
+#define MDMA_CTCR_BWM_Pos         (31U)
+#define MDMA_CTCR_BWM_Msk         (0x1UL << MDMA_CTCR_BWM_Pos)                 /*!< 0x80000000 */
+#define MDMA_CTCR_BWM             MDMA_CTCR_BWM_Msk                            /*!< Bufferable Write Mode */
+
+/********************  Bit definition for MDMA_CxBNDTR register  ****************/
+#define MDMA_CBNDTR_BNDT_Pos      (0U)
+#define MDMA_CBNDTR_BNDT_Msk      (0x1FFFFUL << MDMA_CBNDTR_BNDT_Pos)          /*!< 0x0001FFFF */
+#define MDMA_CBNDTR_BNDT          MDMA_CBNDTR_BNDT_Msk                         /*!< Block Number of data bytes to transfer */
+#define MDMA_CBNDTR_BRSUM_Pos     (18U)
+#define MDMA_CBNDTR_BRSUM_Msk     (0x1UL << MDMA_CBNDTR_BRSUM_Pos)             /*!< 0x00040000 */
+#define MDMA_CBNDTR_BRSUM         MDMA_CBNDTR_BRSUM_Msk                        /*!< Block Repeat Source address Update Mode */
+#define MDMA_CBNDTR_BRDUM_Pos     (19U)
+#define MDMA_CBNDTR_BRDUM_Msk     (0x1UL << MDMA_CBNDTR_BRDUM_Pos)             /*!< 0x00080000 */
+#define MDMA_CBNDTR_BRDUM         MDMA_CBNDTR_BRDUM_Msk                        /*!< Block Repeat Destination address Update Mode */
+#define MDMA_CBNDTR_BRC_Pos       (20U)
+#define MDMA_CBNDTR_BRC_Msk       (0xFFFUL << MDMA_CBNDTR_BRC_Pos)             /*!< 0xFFF00000 */
+#define MDMA_CBNDTR_BRC           MDMA_CBNDTR_BRC_Msk                          /*!< Block Repeat Count */
+
+/********************  Bit definition for MDMA_CxSAR register  ****************/
+#define MDMA_CSAR_SAR_Pos         (0U)
+#define MDMA_CSAR_SAR_Msk         (0xFFFFFFFFUL << MDMA_CSAR_SAR_Pos)          /*!< 0xFFFFFFFF */
+#define MDMA_CSAR_SAR             MDMA_CSAR_SAR_Msk                            /*!< Source address */
+
+/********************  Bit definition for MDMA_CxDAR register  ****************/
+#define MDMA_CDAR_DAR_Pos         (0U)
+#define MDMA_CDAR_DAR_Msk         (0xFFFFFFFFUL << MDMA_CDAR_DAR_Pos)          /*!< 0xFFFFFFFF */
+#define MDMA_CDAR_DAR             MDMA_CDAR_DAR_Msk                            /*!< Destination address */
+
+/********************  Bit definition for MDMA_CxBRUR  ************************/
+#define MDMA_CBRUR_SUV_Pos        (0U)
+#define MDMA_CBRUR_SUV_Msk        (0xFFFFUL << MDMA_CBRUR_SUV_Pos)             /*!< 0x0000FFFF */
+#define MDMA_CBRUR_SUV            MDMA_CBRUR_SUV_Msk                           /*!< Source address Update Value */
+#define MDMA_CBRUR_DUV_Pos        (16U)
+#define MDMA_CBRUR_DUV_Msk        (0xFFFFUL << MDMA_CBRUR_DUV_Pos)             /*!< 0xFFFF0000 */
+#define MDMA_CBRUR_DUV            MDMA_CBRUR_DUV_Msk                           /*!< Destination address Update Value */
+
+/********************  Bit definition for MDMA_CxLAR  *************************/
+#define MDMA_CLAR_LAR_Pos         (0U)
+#define MDMA_CLAR_LAR_Msk         (0xFFFFFFFFUL << MDMA_CLAR_LAR_Pos)          /*!< 0xFFFFFFFF */
+#define MDMA_CLAR_LAR             MDMA_CLAR_LAR_Msk                            /*!< Link Address Register */
+
+/********************  Bit definition for MDMA_CxTBR)  ************************/
+#define MDMA_CTBR_TSEL_Pos        (0U)
+#define MDMA_CTBR_TSEL_Msk        (0xFFUL << MDMA_CTBR_TSEL_Pos)               /*!< 0x000000FF */
+#define MDMA_CTBR_TSEL            MDMA_CTBR_TSEL_Msk                           /*!< Trigger SELection */
+#define MDMA_CTBR_SBUS_Pos        (16U)
+#define MDMA_CTBR_SBUS_Msk        (0x1UL << MDMA_CTBR_SBUS_Pos)                /*!< 0x00010000 */
+#define MDMA_CTBR_SBUS            MDMA_CTBR_SBUS_Msk                           /*!< Source BUS select */
+#define MDMA_CTBR_DBUS_Pos        (17U)
+#define MDMA_CTBR_DBUS_Msk        (0x1UL << MDMA_CTBR_DBUS_Pos)                /*!< 0x00020000 */
+#define MDMA_CTBR_DBUS            MDMA_CTBR_DBUS_Msk                           /*!< Destination BUS select */
+
+/********************  Bit definition for MDMA_CxMAR)  ************************/
+#define MDMA_CMAR_MAR_Pos         (0U)
+#define MDMA_CMAR_MAR_Msk         (0xFFFFFFFFUL << MDMA_CMAR_MAR_Pos)          /*!< 0xFFFFFFFF */
+#define MDMA_CMAR_MAR             MDMA_CMAR_MAR_Msk                            /*!< Mask address */
+
+/********************  Bit definition for MDMA_CxMDR)  ************************/
+#define MDMA_CMDR_MDR_Pos         (0U)
+#define MDMA_CMDR_MDR_Msk         (0xFFFFFFFFUL << MDMA_CMDR_MDR_Pos)          /*!< 0xFFFFFFFF */
+#define MDMA_CMDR_MDR             MDMA_CMDR_MDR_Msk                            /*!< Mask Data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Operational Amplifier (OPAMP)                      */
+/*                                                                            */
+/******************************************************************************/
+/*********************  Bit definition for OPAMPx_CSR register  ***************/
+#define OPAMP_CSR_OPAMPxEN_Pos           (0U)
+#define OPAMP_CSR_OPAMPxEN_Msk           (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)     /*!< 0x00000001 */
+#define OPAMP_CSR_OPAMPxEN               OPAMP_CSR_OPAMPxEN_Msk                /*!< OPAMP enable */
+#define OPAMP_CSR_FORCEVP_Pos            (1U)
+#define OPAMP_CSR_FORCEVP_Msk            (0x1UL << OPAMP_CSR_FORCEVP_Pos)      /*!< 0x00000002 */
+#define OPAMP_CSR_FORCEVP                OPAMP_CSR_FORCEVP_Msk                 /*!< Force internal reference on VP */
+
+#define OPAMP_CSR_VPSEL_Pos              (2U)
+#define OPAMP_CSR_VPSEL_Msk              (0x3UL << OPAMP_CSR_VPSEL_Pos)        /*!< 0x0000000C */
+#define OPAMP_CSR_VPSEL                  OPAMP_CSR_VPSEL_Msk                   /*!< Non inverted input selection */
+#define OPAMP_CSR_VPSEL_0                (0x1UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000004 */
+#define OPAMP_CSR_VPSEL_1                (0x2UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000008 */
+
+#define OPAMP_CSR_VMSEL_Pos              (5U)
+#define OPAMP_CSR_VMSEL_Msk              (0x3UL << OPAMP_CSR_VMSEL_Pos)        /*!< 0x00000060 */
+#define OPAMP_CSR_VMSEL                  OPAMP_CSR_VMSEL_Msk                   /*!< Inverting input selection */
+#define OPAMP_CSR_VMSEL_0                (0x1UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000020 */
+#define OPAMP_CSR_VMSEL_1                (0x2UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000040 */
+
+#define OPAMP_CSR_OPAHSM_Pos             (8U)
+#define OPAMP_CSR_OPAHSM_Msk             (0x1UL << OPAMP_CSR_OPAHSM_Pos)       /*!< 0x00000100 */
+#define OPAMP_CSR_OPAHSM                 OPAMP_CSR_OPAHSM_Msk                  /*!< Operational amplifier high speed mode */
+#define OPAMP_CSR_CALON_Pos              (11U)
+#define OPAMP_CSR_CALON_Msk              (0x1UL << OPAMP_CSR_CALON_Pos)        /*!< 0x00000800 */
+#define OPAMP_CSR_CALON                  OPAMP_CSR_CALON_Msk                   /*!< Calibration mode enable */
+
+#define OPAMP_CSR_CALSEL_Pos             (12U)
+#define OPAMP_CSR_CALSEL_Msk             (0x3UL << OPAMP_CSR_CALSEL_Pos)       /*!< 0x00003000 */
+#define OPAMP_CSR_CALSEL                 OPAMP_CSR_CALSEL_Msk                  /*!< Calibration selection */
+#define OPAMP_CSR_CALSEL_0               (0x1UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00001000 */
+#define OPAMP_CSR_CALSEL_1               (0x2UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00002000 */
+
+#define OPAMP_CSR_PGGAIN_Pos             (14U)
+#define OPAMP_CSR_PGGAIN_Msk             (0xFUL << OPAMP_CSR_PGGAIN_Pos)       /*!< 0x0003C000 */
+#define OPAMP_CSR_PGGAIN                 OPAMP_CSR_PGGAIN_Msk                  /*!< Operational amplifier Programmable amplifier gain value */
+#define OPAMP_CSR_PGGAIN_0               (0x1UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00004000 */
+#define OPAMP_CSR_PGGAIN_1               (0x2UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00008000 */
+#define OPAMP_CSR_PGGAIN_2               (0x4UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00010000 */
+#define OPAMP_CSR_PGGAIN_3               (0x8UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00020000 */
+
+#define OPAMP_CSR_USERTRIM_Pos           (18U)
+#define OPAMP_CSR_USERTRIM_Msk           (0x1UL << OPAMP_CSR_USERTRIM_Pos)     /*!< 0x00040000 */
+#define OPAMP_CSR_USERTRIM               OPAMP_CSR_USERTRIM_Msk                /*!< User trimming enable */
+#define OPAMP_CSR_TSTREF_Pos             (29U)
+#define OPAMP_CSR_TSTREF_Msk             (0x1UL << OPAMP_CSR_TSTREF_Pos)       /*!< 0x20000000 */
+#define OPAMP_CSR_TSTREF                 OPAMP_CSR_TSTREF_Msk                  /*!< OpAmp calibration reference voltage output control */
+#define OPAMP_CSR_CALOUT_Pos             (30U)
+#define OPAMP_CSR_CALOUT_Msk             (0x1UL << OPAMP_CSR_CALOUT_Pos)       /*!< 0x40000000 */
+#define OPAMP_CSR_CALOUT                 OPAMP_CSR_CALOUT_Msk                  /*!< Operational amplifier calibration output */
+
+/*********************  Bit definition for OPAMP1_CSR register  ***************/
+#define OPAMP1_CSR_OPAEN_Pos              (0U)
+#define OPAMP1_CSR_OPAEN_Msk              (0x1UL << OPAMP1_CSR_OPAEN_Pos)      /*!< 0x00000001 */
+#define OPAMP1_CSR_OPAEN                  OPAMP1_CSR_OPAEN_Msk                 /*!< Operational amplifier1 Enable */
+#define OPAMP1_CSR_FORCEVP_Pos            (1U)
+#define OPAMP1_CSR_FORCEVP_Msk            (0x1UL << OPAMP1_CSR_FORCEVP_Pos)    /*!< 0x00000002 */
+#define OPAMP1_CSR_FORCEVP                OPAMP1_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */
+
+#define OPAMP1_CSR_VPSEL_Pos              (2U)
+#define OPAMP1_CSR_VPSEL_Msk              (0x3UL << OPAMP1_CSR_VPSEL_Pos)      /*!< 0x0000000C */
+#define OPAMP1_CSR_VPSEL                  OPAMP1_CSR_VPSEL_Msk                 /*!< Non inverted input selection */
+#define OPAMP1_CSR_VPSEL_0                (0x1UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000004 */
+#define OPAMP1_CSR_VPSEL_1                (0x2UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000008 */
+
+#define OPAMP1_CSR_VMSEL_Pos              (5U)
+#define OPAMP1_CSR_VMSEL_Msk              (0x3UL << OPAMP1_CSR_VMSEL_Pos)      /*!< 0x00000060 */
+#define OPAMP1_CSR_VMSEL                  OPAMP1_CSR_VMSEL_Msk                 /*!< Inverting input selection */
+#define OPAMP1_CSR_VMSEL_0                (0x1UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000020 */
+#define OPAMP1_CSR_VMSEL_1                (0x2UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000040 */
+
+#define OPAMP1_CSR_OPAHSM_Pos             (8U)
+#define OPAMP1_CSR_OPAHSM_Msk             (0x1UL << OPAMP1_CSR_OPAHSM_Pos)     /*!< 0x00000100 */
+#define OPAMP1_CSR_OPAHSM                 OPAMP1_CSR_OPAHSM_Msk                /*!< Operational amplifier1 high speed mode */
+#define OPAMP1_CSR_CALON_Pos              (11U)
+#define OPAMP1_CSR_CALON_Msk              (0x1UL << OPAMP1_CSR_CALON_Pos)      /*!< 0x00000800 */
+#define OPAMP1_CSR_CALON                  OPAMP1_CSR_CALON_Msk                 /*!< Calibration mode enable */
+
+#define OPAMP1_CSR_CALSEL_Pos             (12U)
+#define OPAMP1_CSR_CALSEL_Msk             (0x3UL << OPAMP1_CSR_CALSEL_Pos)     /*!< 0x00003000 */
+#define OPAMP1_CSR_CALSEL                 OPAMP1_CSR_CALSEL_Msk                /*!< Calibration selection */
+#define OPAMP1_CSR_CALSEL_0               (0x1UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00001000 */
+#define OPAMP1_CSR_CALSEL_1               (0x2UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00002000 */
+
+#define OPAMP1_CSR_PGGAIN_Pos             (14U)
+#define OPAMP1_CSR_PGGAIN_Msk             (0xFUL << OPAMP1_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */
+#define OPAMP1_CSR_PGGAIN                 OPAMP1_CSR_PGGAIN_Msk                /*!< Operational amplifier1 Programmable amplifier gain value */
+#define OPAMP1_CSR_PGGAIN_0               (0x1UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00004000 */
+#define OPAMP1_CSR_PGGAIN_1               (0x2UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00008000 */
+#define OPAMP1_CSR_PGGAIN_2               (0x4UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00010000 */
+#define OPAMP1_CSR_PGGAIN_3               (0x8UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00020000 */
+
+#define OPAMP1_CSR_USERTRIM_Pos           (18U)
+#define OPAMP1_CSR_USERTRIM_Msk           (0x1UL << OPAMP1_CSR_USERTRIM_Pos)   /*!< 0x00040000 */
+#define OPAMP1_CSR_USERTRIM               OPAMP1_CSR_USERTRIM_Msk              /*!< User trimming enable */
+#define OPAMP1_CSR_TSTREF_Pos             (29U)
+#define OPAMP1_CSR_TSTREF_Msk             (0x1UL << OPAMP1_CSR_TSTREF_Pos)     /*!< 0x20000000 */
+#define OPAMP1_CSR_TSTREF                 OPAMP1_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */
+#define OPAMP1_CSR_CALOUT_Pos             (30U)
+#define OPAMP1_CSR_CALOUT_Msk             (0x1UL << OPAMP1_CSR_CALOUT_Pos)     /*!< 0x40000000 */
+#define OPAMP1_CSR_CALOUT                 OPAMP1_CSR_CALOUT_Msk                /*!< Operational amplifier1 calibration output */
+
+/*********************  Bit definition for OPAMP2_CSR register  ***************/
+#define OPAMP2_CSR_OPAEN_Pos              (0U)
+#define OPAMP2_CSR_OPAEN_Msk              (0x1UL << OPAMP2_CSR_OPAEN_Pos)      /*!< 0x00000001 */
+#define OPAMP2_CSR_OPAEN                  OPAMP2_CSR_OPAEN_Msk                 /*!< Operational amplifier2 Enable */
+#define OPAMP2_CSR_FORCEVP_Pos            (1U)
+#define OPAMP2_CSR_FORCEVP_Msk            (0x1UL << OPAMP2_CSR_FORCEVP_Pos)    /*!< 0x00000002 */
+#define OPAMP2_CSR_FORCEVP                OPAMP2_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */
+
+#define OPAMP2_CSR_VPSEL_Pos              (2U)
+#define OPAMP2_CSR_VPSEL_Msk              (0x3UL << OPAMP2_CSR_VPSEL_Pos)      /*!< 0x0000000C */
+#define OPAMP2_CSR_VPSEL                  OPAMP2_CSR_VPSEL_Msk                 /*!< Non inverted input selection */
+#define OPAMP2_CSR_VPSEL_0                (0x1UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000004 */
+#define OPAMP2_CSR_VPSEL_1                (0x2UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000008 */
+
+#define OPAMP2_CSR_VMSEL_Pos              (5U)
+#define OPAMP2_CSR_VMSEL_Msk              (0x3UL << OPAMP2_CSR_VMSEL_Pos)      /*!< 0x00000060 */
+#define OPAMP2_CSR_VMSEL                  OPAMP2_CSR_VMSEL_Msk                 /*!< Inverting input selection */
+#define OPAMP2_CSR_VMSEL_0                (0x1UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000020 */
+#define OPAMP2_CSR_VMSEL_1                (0x2UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000040 */
+
+#define OPAMP2_CSR_OPAHSM_Pos             (8U)
+#define OPAMP2_CSR_OPAHSM_Msk             (0x1UL << OPAMP2_CSR_OPAHSM_Pos)     /*!< 0x00000100 */
+#define OPAMP2_CSR_OPAHSM                 OPAMP2_CSR_OPAHSM_Msk                /*!< Operational amplifier2 high speed mode */
+#define OPAMP2_CSR_CALON_Pos              (11U)
+#define OPAMP2_CSR_CALON_Msk              (0x1UL << OPAMP2_CSR_CALON_Pos)      /*!< 0x00000800 */
+#define OPAMP2_CSR_CALON                  OPAMP2_CSR_CALON_Msk                 /*!< Calibration mode enable */
+
+#define OPAMP2_CSR_CALSEL_Pos             (12U)
+#define OPAMP2_CSR_CALSEL_Msk             (0x3UL << OPAMP2_CSR_CALSEL_Pos)     /*!< 0x00003000 */
+#define OPAMP2_CSR_CALSEL                 OPAMP2_CSR_CALSEL_Msk                /*!< Calibration selection */
+#define OPAMP2_CSR_CALSEL_0               (0x1UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00001000 */
+#define OPAMP2_CSR_CALSEL_1               (0x2UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00002000 */
+
+#define OPAMP2_CSR_PGGAIN_Pos             (14U)
+#define OPAMP2_CSR_PGGAIN_Msk             (0xFUL << OPAMP2_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */
+#define OPAMP2_CSR_PGGAIN                 OPAMP2_CSR_PGGAIN_Msk                /*!< Operational amplifier2 Programmable amplifier gain value */
+#define OPAMP2_CSR_PGGAIN_0               (0x1UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00004000 */
+#define OPAMP2_CSR_PGGAIN_1               (0x2UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00008000 */
+#define OPAMP2_CSR_PGGAIN_2               (0x4UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00010000 */
+#define OPAMP2_CSR_PGGAIN_3               (0x8UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00020000 */
+
+#define OPAMP2_CSR_USERTRIM_Pos           (18U)
+#define OPAMP2_CSR_USERTRIM_Msk           (0x1UL << OPAMP2_CSR_USERTRIM_Pos)   /*!< 0x00040000 */
+#define OPAMP2_CSR_USERTRIM               OPAMP2_CSR_USERTRIM_Msk              /*!< User trimming enable */
+#define OPAMP2_CSR_TSTREF_Pos             (29U)
+#define OPAMP2_CSR_TSTREF_Msk             (0x1UL << OPAMP2_CSR_TSTREF_Pos)     /*!< 0x20000000 */
+#define OPAMP2_CSR_TSTREF                 OPAMP2_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */
+#define OPAMP2_CSR_CALOUT_Pos             (30U)
+#define OPAMP2_CSR_CALOUT_Msk             (0x1UL << OPAMP2_CSR_CALOUT_Pos)     /*!< 0x40000000 */
+#define OPAMP2_CSR_CALOUT                 OPAMP2_CSR_CALOUT_Msk                /*!< Operational amplifier2 calibration output */
+
+/*******************  Bit definition for OPAMP_OTR register  ******************/
+#define OPAMP_OTR_TRIMOFFSETN_Pos        (0U)
+#define OPAMP_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP_OTR_TRIMOFFSETN            OPAMP_OTR_TRIMOFFSETN_Msk             /*!< Trim for NMOS differential pairs */
+#define OPAMP_OTR_TRIMOFFSETP_Pos        (8U)
+#define OPAMP_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP_OTR_TRIMOFFSETP            OPAMP_OTR_TRIMOFFSETP_Msk             /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP1_OTR register  ******************/
+#define OPAMP1_OTR_TRIMOFFSETN_Pos        (0U)
+#define OPAMP1_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP1_OTR_TRIMOFFSETN            OPAMP1_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */
+#define OPAMP1_OTR_TRIMOFFSETP_Pos        (8U)
+#define OPAMP1_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP1_OTR_TRIMOFFSETP            OPAMP1_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP2_OTR register  ******************/
+#define OPAMP2_OTR_TRIMOFFSETN_Pos        (0U)
+#define OPAMP2_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP2_OTR_TRIMOFFSETN            OPAMP2_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */
+#define OPAMP2_OTR_TRIMOFFSETP_Pos        (8U)
+#define OPAMP2_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP2_OTR_TRIMOFFSETP            OPAMP2_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP_HSOTR register  ****************/
+#define OPAMP_HSOTR_TRIMHSOFFSETN_Pos    (0U)
+#define OPAMP_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP_HSOTR_TRIMHSOFFSETN        OPAMP_HSOTR_TRIMHSOFFSETN_Msk         /*!< Trim for NMOS differential pairs */
+#define OPAMP_HSOTR_TRIMHSOFFSETP_Pos    (8U)
+#define OPAMP_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP_HSOTR_TRIMHSOFFSETP        OPAMP_HSOTR_TRIMHSOFFSETP_Msk         /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP1_HSOTR register  ****************/
+#define OPAMP1_HSOTR_TRIMHSOFFSETN_Pos    (0U)
+#define OPAMP1_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP1_HSOTR_TRIMHSOFFSETN        OPAMP1_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */
+#define OPAMP1_HSOTR_TRIMHSOFFSETP_Pos    (8U)
+#define OPAMP1_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP1_HSOTR_TRIMHSOFFSETP        OPAMP1_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP2_HSOTR register  ****************/
+#define OPAMP2_HSOTR_TRIMHSOFFSETN_Pos    (0U)
+#define OPAMP2_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP2_HSOTR_TRIMHSOFFSETN        OPAMP2_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */
+#define OPAMP2_HSOTR_TRIMHSOFFSETP_Pos    (8U)
+#define OPAMP2_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP2_HSOTR_TRIMHSOFFSETP        OPAMP2_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             Power Control                                  */
+/*                                                                            */
+/******************************************************************************/
+/*************************  NUMBER OF POWER DOMAINS  **************************/
+#define POWER_DOMAINS_NUMBER           3U                                      /*!< 3 Domains */
+
+/********************  Bit definition for PWR_CR1 register  *******************/
+#define PWR_CR1_ALS_Pos                (17U)
+#define PWR_CR1_ALS_Msk                (0x3UL << PWR_CR1_ALS_Pos)              /*!< 0x00060000 */
+#define PWR_CR1_ALS                    PWR_CR1_ALS_Msk                         /*!< Analog Voltage Detector level selection */
+#define PWR_CR1_ALS_0                  (0x1UL << PWR_CR1_ALS_Pos)              /*!< 0x00020000 */
+#define PWR_CR1_ALS_1                  (0x2UL << PWR_CR1_ALS_Pos)              /*!< 0x00040000 */
+#define PWR_CR1_AVDEN_Pos              (16U)
+#define PWR_CR1_AVDEN_Msk              (0x1UL << PWR_CR1_AVDEN_Pos)            /*!< 0x00010000 */
+#define PWR_CR1_AVDEN                  PWR_CR1_AVDEN_Msk                       /*!< Analog Voltage Detector Enable */
+#define PWR_CR1_SVOS_Pos               (14U)
+#define PWR_CR1_SVOS_Msk               (0x3UL << PWR_CR1_SVOS_Pos)             /*!< 0x0000C000 */
+#define PWR_CR1_SVOS                   PWR_CR1_SVOS_Msk                        /*!< System STOP mode Voltage Scaling selection */
+#define PWR_CR1_SVOS_0                 (0x1UL << PWR_CR1_SVOS_Pos)             /*!< 0x00004000 */
+#define PWR_CR1_SVOS_1                 (0x2UL << PWR_CR1_SVOS_Pos)             /*!< 0x00008000 */
+#define PWR_CR1_FLPS_Pos               (9U)
+#define PWR_CR1_FLPS_Msk               (0x1UL << PWR_CR1_FLPS_Pos)             /*!< 0x00000200 */
+#define PWR_CR1_FLPS                   PWR_CR1_FLPS_Msk                        /*!< Flash low power mode in DSTOP */
+#define PWR_CR1_DBP_Pos                (8U)
+#define PWR_CR1_DBP_Msk                (0x1UL << PWR_CR1_DBP_Pos)              /*!< 0x00000100 */
+#define PWR_CR1_DBP                    PWR_CR1_DBP_Msk                         /*!< Disable Back-up domain Protection */
+#define PWR_CR1_PLS_Pos                (5U)
+#define PWR_CR1_PLS_Msk                (0x7UL << PWR_CR1_PLS_Pos)              /*!< 0x000000E0 */
+#define PWR_CR1_PLS                    PWR_CR1_PLS_Msk                         /*!< Programmable Voltage Detector level selection */
+#define PWR_CR1_PLS_0                  (0x1UL << PWR_CR1_PLS_Pos)              /*!< 0x00000020 */
+#define PWR_CR1_PLS_1                  (0x2UL << PWR_CR1_PLS_Pos)              /*!< 0x00000040 */
+#define PWR_CR1_PLS_2                  (0x4UL << PWR_CR1_PLS_Pos)              /*!< 0x00000080 */
+#define PWR_CR1_PVDEN_Pos              (4U)
+#define PWR_CR1_PVDEN_Msk              (0x1UL << PWR_CR1_PVDEN_Pos)            /*!< 0x00000010 */
+#define PWR_CR1_PVDEN                  PWR_CR1_PVDEN_Msk                       /*!< Programmable Voltage detector enable */
+#define PWR_CR1_LPDS_Pos               (0U)
+#define PWR_CR1_LPDS_Msk               (0x1UL << PWR_CR1_LPDS_Pos)             /*!< 0x00000001 */
+#define PWR_CR1_LPDS                   PWR_CR1_LPDS_Msk                        /*!< Low Power Deepsleep with SVOS3 */
+
+/*!< PVD level configuration */
+#define PWR_CR1_PLS_LEV0               (0UL)                                   /*!< PVD level 0 */
+#define PWR_CR1_PLS_LEV1_Pos           (5U)
+#define PWR_CR1_PLS_LEV1_Msk           (0x1UL << PWR_CR1_PLS_LEV1_Pos)         /*!< 0x00000020 */
+#define PWR_CR1_PLS_LEV1               PWR_CR1_PLS_LEV1_Msk                    /*!< PVD level 1 */
+#define PWR_CR1_PLS_LEV2_Pos           (6U)
+#define PWR_CR1_PLS_LEV2_Msk           (0x1UL << PWR_CR1_PLS_LEV2_Pos)         /*!< 0x00000040 */
+#define PWR_CR1_PLS_LEV2               PWR_CR1_PLS_LEV2_Msk                    /*!< PVD level 2 */
+#define PWR_CR1_PLS_LEV3_Pos           (5U)
+#define PWR_CR1_PLS_LEV3_Msk           (0x3UL << PWR_CR1_PLS_LEV3_Pos)         /*!< 0x00000060 */
+#define PWR_CR1_PLS_LEV3               PWR_CR1_PLS_LEV3_Msk                    /*!< PVD level 3 */
+#define PWR_CR1_PLS_LEV4_Pos           (7U)
+#define PWR_CR1_PLS_LEV4_Msk           (0x1UL << PWR_CR1_PLS_LEV4_Pos)         /*!< 0x00000080 */
+#define PWR_CR1_PLS_LEV4               PWR_CR1_PLS_LEV4_Msk                    /*!< PVD level 4 */
+#define PWR_CR1_PLS_LEV5_Pos           (5U)
+#define PWR_CR1_PLS_LEV5_Msk           (0x5UL << PWR_CR1_PLS_LEV5_Pos)         /*!< 0x000000A0 */
+#define PWR_CR1_PLS_LEV5               PWR_CR1_PLS_LEV5_Msk                    /*!< PVD level 5 */
+#define PWR_CR1_PLS_LEV6_Pos           (6U)
+#define PWR_CR1_PLS_LEV6_Msk           (0x3UL << PWR_CR1_PLS_LEV6_Pos)         /*!< 0x000000C0 */
+#define PWR_CR1_PLS_LEV6               PWR_CR1_PLS_LEV6_Msk                    /*!< PVD level 6 */
+#define PWR_CR1_PLS_LEV7_Pos           (5U)
+#define PWR_CR1_PLS_LEV7_Msk           (0x7UL << PWR_CR1_PLS_LEV7_Pos)         /*!< 0x000000E0 */
+#define PWR_CR1_PLS_LEV7               PWR_CR1_PLS_LEV7_Msk                    /*!< PVD level 7 */
+
+/*!< AVD level configuration */
+#define PWR_CR1_ALS_LEV0               (0UL)                                   /*!< AVD level 0 */
+#define PWR_CR1_ALS_LEV1_Pos           (17U)
+#define PWR_CR1_ALS_LEV1_Msk           (0x1UL << PWR_CR1_ALS_LEV1_Pos)         /*!< 0x00020000 */
+#define PWR_CR1_ALS_LEV1               PWR_CR1_ALS_LEV1_Msk                    /*!< AVD level 1 */
+#define PWR_CR1_ALS_LEV2_Pos           (18U)
+#define PWR_CR1_ALS_LEV2_Msk           (0x1UL << PWR_CR1_ALS_LEV2_Pos)         /*!< 0x00040000 */
+#define PWR_CR1_ALS_LEV2               PWR_CR1_ALS_LEV2_Msk                    /*!< AVD level 2 */
+#define PWR_CR1_ALS_LEV3_Pos           (17U)
+#define PWR_CR1_ALS_LEV3_Msk           (0x3UL << PWR_CR1_ALS_LEV3_Pos)         /*!< 0x00060000 */
+#define PWR_CR1_ALS_LEV3               PWR_CR1_ALS_LEV3_Msk                    /*!< AVD level 3 */
+
+/********************  Bit definition for PWR_CSR1 register  ******************/
+#define PWR_CSR1_AVDO_Pos              (16U)
+#define PWR_CSR1_AVDO_Msk              (0x1UL << PWR_CSR1_AVDO_Pos)            /*!< 0x00010000 */
+#define PWR_CSR1_AVDO                  PWR_CSR1_AVDO_Msk                       /*!< Analog Voltage Detect Output */
+#define PWR_CSR1_ACTVOS_Pos            (14U)
+#define PWR_CSR1_ACTVOS_Msk            (0x3UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x0000C000 */
+#define PWR_CSR1_ACTVOS                PWR_CSR1_ACTVOS_Msk                     /*!< Current actual used VOS for VDD11 Voltage Scaling */
+#define PWR_CSR1_ACTVOS_0              (0x1UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00004000 */
+#define PWR_CSR1_ACTVOS_1              (0x2UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00008000 */
+#define PWR_CSR1_ACTVOSRDY_Pos         (13U)
+#define PWR_CSR1_ACTVOSRDY_Msk         (0x1UL << PWR_CSR1_ACTVOSRDY_Pos)       /*!< 0x00002000 */
+#define PWR_CSR1_ACTVOSRDY             PWR_CSR1_ACTVOSRDY_Msk                  /*!< Ready bit for current actual used VOS for VDD11 Voltage Scaling  */
+#define PWR_CSR1_PVDO_Pos              (4U)
+#define PWR_CSR1_PVDO_Msk              (0x1UL << PWR_CSR1_PVDO_Pos)            /*!< 0x00000010 */
+#define PWR_CSR1_PVDO                  PWR_CSR1_PVDO_Msk                       /*!< Programmable Voltage Detect Output */
+
+/********************  Bit definition for PWR_CR2 register  *******************/
+#define PWR_CR2_TEMPH_Pos              (23U)
+#define PWR_CR2_TEMPH_Msk              (0x1UL << PWR_CR2_TEMPH_Pos)            /*!< 0x00800000 */
+#define PWR_CR2_TEMPH                  PWR_CR2_TEMPH_Msk                       /*!< Monitored temperature level above high threshold */
+#define PWR_CR2_TEMPL_Pos              (22U)
+#define PWR_CR2_TEMPL_Msk              (0x1UL << PWR_CR2_TEMPL_Pos)            /*!< 0x00400000 */
+#define PWR_CR2_TEMPL                  PWR_CR2_TEMPL_Msk                       /*!< Monitored temperature level above low threshold */
+#define PWR_CR2_VBATH_Pos              (21U)
+#define PWR_CR2_VBATH_Msk              (0x1UL << PWR_CR2_VBATH_Pos)            /*!< 0x00200000 */
+#define PWR_CR2_VBATH                  PWR_CR2_VBATH_Msk                       /*!< Monitored VBAT level above high threshold */
+#define PWR_CR2_VBATL_Pos              (20U)
+#define PWR_CR2_VBATL_Msk              (0x1UL << PWR_CR2_VBATL_Pos)            /*!< 0x00100000 */
+#define PWR_CR2_VBATL                  PWR_CR2_VBATL_Msk                       /*!< Monitored VBAT level above low threshold */
+#define PWR_CR2_BRRDY_Pos              (16U)
+#define PWR_CR2_BRRDY_Msk              (0x1UL << PWR_CR2_BRRDY_Pos)            /*!< 0x00010000 */
+#define PWR_CR2_BRRDY                  PWR_CR2_BRRDY_Msk                       /*!< Backup regulator ready */
+#define PWR_CR2_MONEN_Pos              (4U)
+#define PWR_CR2_MONEN_Msk              (0x1UL << PWR_CR2_MONEN_Pos)            /*!< 0x00000010 */
+#define PWR_CR2_MONEN                  PWR_CR2_MONEN_Msk                       /*!< VBAT and temperature monitoring enable */
+#define PWR_CR2_BREN_Pos               (0U)
+#define PWR_CR2_BREN_Msk               (0x1UL << PWR_CR2_BREN_Pos)             /*!< 0x00000001 */
+#define PWR_CR2_BREN                   PWR_CR2_BREN_Msk                        /*!< Backup regulator enable */
+
+/********************  Bit definition for PWR_CR3 register  *******************/
+#define PWR_CR3_USB33RDY_Pos           (26U)
+#define PWR_CR3_USB33RDY_Msk           (0x1UL << PWR_CR3_USB33RDY_Pos)         /*!< 0x04000000 */
+#define PWR_CR3_USB33RDY               PWR_CR3_USB33RDY_Msk                    /*!< USB supply ready */
+#define PWR_CR3_USBREGEN_Pos           (25U)
+#define PWR_CR3_USBREGEN_Msk           (0x1UL << PWR_CR3_USBREGEN_Pos)         /*!< 0x02000000 */
+#define PWR_CR3_USBREGEN               PWR_CR3_USBREGEN_Msk                    /*!< USB regulator enable */
+#define PWR_CR3_USB33DEN_Pos           (24U)
+#define PWR_CR3_USB33DEN_Msk           (0x1UL << PWR_CR3_USB33DEN_Pos)         /*!< 0x01000000 */
+#define PWR_CR3_USB33DEN               PWR_CR3_USB33DEN_Msk                    /*!< VDD33_USB voltage level detector enable */
+#define PWR_CR3_VBRS_Pos               (9U)
+#define PWR_CR3_VBRS_Msk               (0x1UL << PWR_CR3_VBRS_Pos)             /*!< 0x00000200 */
+#define PWR_CR3_VBRS                   PWR_CR3_VBRS_Msk                        /*!< VBAT charging resistor selection */
+#define PWR_CR3_VBE_Pos                (8U)
+#define PWR_CR3_VBE_Msk                (0x1UL << PWR_CR3_VBE_Pos)              /*!< 0x00000100 */
+#define PWR_CR3_VBE                    PWR_CR3_VBE_Msk                         /*!< VBAT charging enable */
+#define PWR_CR3_SCUEN_Pos              (2U)
+#define PWR_CR3_SCUEN_Msk              (0x1UL << PWR_CR3_SCUEN_Pos)            /*!< 0x00000004 */
+#define PWR_CR3_SCUEN                  PWR_CR3_SCUEN_Msk                       /*!< Supply configuration update enable */
+#define PWR_CR3_LDOEN_Pos              (1U)
+#define PWR_CR3_LDOEN_Msk              (0x1UL << PWR_CR3_LDOEN_Pos)            /*!< 0x00000002 */
+#define PWR_CR3_LDOEN                  PWR_CR3_LDOEN_Msk                       /*!< Low Drop Output regulator enable */
+#define PWR_CR3_BYPASS_Pos             (0U)
+#define PWR_CR3_BYPASS_Msk             (0x1UL << PWR_CR3_BYPASS_Pos)           /*!< 0x00000001 */
+#define PWR_CR3_BYPASS                 PWR_CR3_BYPASS_Msk                      /*!< Power Management Unit bypass */
+
+/********************  Bit definition for PWR_CPUCR register  *****************/
+#define PWR_CPUCR_RUN_D3_Pos           (11U)
+#define PWR_CPUCR_RUN_D3_Msk           (0x1UL << PWR_CPUCR_RUN_D3_Pos)         /*!< 0x00000800 */
+#define PWR_CPUCR_RUN_D3               PWR_CPUCR_RUN_D3_Msk                    /*!< Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes */
+#define PWR_CPUCR_CSSF_Pos             (9U)
+#define PWR_CPUCR_CSSF_Msk             (0x1UL << PWR_CPUCR_CSSF_Pos)           /*!< 0x00000200 */
+#define PWR_CPUCR_CSSF                 PWR_CPUCR_CSSF_Msk                      /*!< Clear D1 domain CPU1 STANDBY, STOP and HOLD flags */
+#define PWR_CPUCR_SBF_D2_Pos           (8U)
+#define PWR_CPUCR_SBF_D2_Msk           (0x1UL << PWR_CPUCR_SBF_D2_Pos)         /*!< 0x00000100 */
+#define PWR_CPUCR_SBF_D2               PWR_CPUCR_SBF_D2_Msk                    /*!< D2 domain DSTANDBY Flag */
+#define PWR_CPUCR_SBF_D1_Pos           (7U)
+#define PWR_CPUCR_SBF_D1_Msk           (0x1UL << PWR_CPUCR_SBF_D1_Pos)         /*!< 0x00000080 */
+#define PWR_CPUCR_SBF_D1               PWR_CPUCR_SBF_D1_Msk                    /*!< D1 domain DSTANDBY Flag */
+#define PWR_CPUCR_SBF_Pos              (6U)
+#define PWR_CPUCR_SBF_Msk              (0x1UL << PWR_CPUCR_SBF_Pos)            /*!< 0x00000040 */
+#define PWR_CPUCR_SBF                  PWR_CPUCR_SBF_Msk                       /*!< System STANDBY Flag */
+#define PWR_CPUCR_STOPF_Pos            (5U)
+#define PWR_CPUCR_STOPF_Msk            (0x1UL << PWR_CPUCR_STOPF_Pos)          /*!< 0x00000020 */
+#define PWR_CPUCR_STOPF                PWR_CPUCR_STOPF_Msk                     /*!< STOP Flag */
+#define PWR_CPUCR_PDDS_D3_Pos          (2U)
+#define PWR_CPUCR_PDDS_D3_Msk          (0x1UL << PWR_CPUCR_PDDS_D3_Pos)        /*!< 0x00000004 */
+#define PWR_CPUCR_PDDS_D3              PWR_CPUCR_PDDS_D3_Msk                   /*!< System D3 domain Power Down Deepsleep */
+#define PWR_CPUCR_PDDS_D2_Pos          (1U)
+#define PWR_CPUCR_PDDS_D2_Msk          (0x1UL << PWR_CPUCR_PDDS_D2_Pos)        /*!< 0x00000002 */
+#define PWR_CPUCR_PDDS_D2              PWR_CPUCR_PDDS_D2_Msk                   /*!< D2 domain Power Down Deepsleep */
+#define PWR_CPUCR_PDDS_D1_Pos          (0U)
+#define PWR_CPUCR_PDDS_D1_Msk          (0x1UL << PWR_CPUCR_PDDS_D1_Pos)        /*!< 0x00000001 */
+#define PWR_CPUCR_PDDS_D1              PWR_CPUCR_PDDS_D1_Msk                   /*!< D1 domain Power Down Deepsleep selection */
+
+
+/********************  Bit definition for PWR_D3CR register  ******************/
+#define PWR_D3CR_VOS_Pos               (14U)
+#define PWR_D3CR_VOS_Msk               (0x3UL << PWR_D3CR_VOS_Pos)             /*!< 0x0000C000 */
+#define PWR_D3CR_VOS                   PWR_D3CR_VOS_Msk                        /*!< Voltage Scaling selection according performance */
+#define PWR_D3CR_VOS_0                 (0x1UL << PWR_D3CR_VOS_Pos)             /*!< 0x00004000 */
+#define PWR_D3CR_VOS_1                 (0x2UL << PWR_D3CR_VOS_Pos)             /*!< 0x00008000 */
+#define PWR_D3CR_VOSRDY_Pos            (13U)
+#define PWR_D3CR_VOSRDY_Msk            (0x1UL << PWR_D3CR_VOSRDY_Pos)          /*!< 0x00002000 */
+#define PWR_D3CR_VOSRDY                PWR_D3CR_VOSRDY_Msk                     /*!< VOS Ready bit for VDD11 Voltage Scaling output selection */
+
+/******************  Bit definition for PWR_WKUPCR register  ******************/
+#define PWR_WKUPCR_WKUPC6_Pos          (5U)
+#define PWR_WKUPCR_WKUPC6_Msk          (0x1UL << PWR_WKUPCR_WKUPC6_Pos)        /*!< 0x00000020 */
+#define PWR_WKUPCR_WKUPC6              PWR_WKUPCR_WKUPC6_Msk                   /*!< Clear Wakeup Pin Flag 6 */
+#define PWR_WKUPCR_WKUPC5_Pos          (4U)
+#define PWR_WKUPCR_WKUPC5_Msk          (0x1UL << PWR_WKUPCR_WKUPC5_Pos)        /*!< 0x00000010 */
+#define PWR_WKUPCR_WKUPC5              PWR_WKUPCR_WKUPC5_Msk                   /*!< Clear Wakeup Pin Flag 5 */
+#define PWR_WKUPCR_WKUPC4_Pos          (3U)
+#define PWR_WKUPCR_WKUPC4_Msk          (0x1UL << PWR_WKUPCR_WKUPC4_Pos)        /*!< 0x00000008 */
+#define PWR_WKUPCR_WKUPC4              PWR_WKUPCR_WKUPC4_Msk                   /*!< Clear Wakeup Pin Flag 4 */
+#define PWR_WKUPCR_WKUPC3_Pos          (2U)
+#define PWR_WKUPCR_WKUPC3_Msk          (0x1UL << PWR_WKUPCR_WKUPC3_Pos)        /*!< 0x00000004 */
+#define PWR_WKUPCR_WKUPC3              PWR_WKUPCR_WKUPC3_Msk                   /*!< Clear Wakeup Pin Flag 3 */
+#define PWR_WKUPCR_WKUPC2_Pos          (1U)
+#define PWR_WKUPCR_WKUPC2_Msk          (0x1UL << PWR_WKUPCR_WKUPC2_Pos)        /*!< 0x00000002 */
+#define PWR_WKUPCR_WKUPC2              PWR_WKUPCR_WKUPC2_Msk                   /*!< Clear Wakeup Pin Flag 2 */
+#define PWR_WKUPCR_WKUPC1_Pos          (0U)
+#define PWR_WKUPCR_WKUPC1_Msk          (0x1UL << PWR_WKUPCR_WKUPC1_Pos)        /*!< 0x00000001 */
+#define PWR_WKUPCR_WKUPC1              PWR_WKUPCR_WKUPC1_Msk                   /*!< Clear Wakeup Pin Flag 1 */
+
+/********************  Bit definition for PWR_WKUPFR register  ****************/
+#define PWR_WKUPFR_WKUPF6_Pos          (5U)
+#define PWR_WKUPFR_WKUPF6_Msk          (0x1UL << PWR_WKUPFR_WKUPF6_Pos)        /*!< 0x00000020 */
+#define PWR_WKUPFR_WKUPF6              PWR_WKUPFR_WKUPF6_Msk                   /*!< Wakeup Pin Flag 6 */
+#define PWR_WKUPFR_WKUPF5_Pos          (4U)
+#define PWR_WKUPFR_WKUPF5_Msk          (0x1UL << PWR_WKUPFR_WKUPF5_Pos)        /*!< 0x00000010 */
+#define PWR_WKUPFR_WKUPF5              PWR_WKUPFR_WKUPF5_Msk                   /*!< Wakeup Pin Flag 5 */
+#define PWR_WKUPFR_WKUPF4_Pos          (3U)
+#define PWR_WKUPFR_WKUPF4_Msk          (0x1UL << PWR_WKUPFR_WKUPF4_Pos)        /*!< 0x00000008 */
+#define PWR_WKUPFR_WKUPF4              PWR_WKUPFR_WKUPF4_Msk                   /*!< Wakeup Pin Flag 4 */
+#define PWR_WKUPFR_WKUPF3_Pos          (2U)
+#define PWR_WKUPFR_WKUPF3_Msk          (0x1UL << PWR_WKUPFR_WKUPF3_Pos)        /*!< 0x00000004 */
+#define PWR_WKUPFR_WKUPF3              PWR_WKUPFR_WKUPF3_Msk                   /*!< Wakeup Pin Flag 3 */
+#define PWR_WKUPFR_WKUPF2_Pos          (1U)
+#define PWR_WKUPFR_WKUPF2_Msk          (0x1UL << PWR_WKUPFR_WKUPF2_Pos)        /*!< 0x00000002 */
+#define PWR_WKUPFR_WKUPF2              PWR_WKUPFR_WKUPF2_Msk                   /*!< Wakeup Pin Flag 2 */
+#define PWR_WKUPFR_WKUPF1_Pos          (0U)
+#define PWR_WKUPFR_WKUPF1_Msk          (0x1UL << PWR_WKUPFR_WKUPF1_Pos)        /*!< 0x00000001 */
+#define PWR_WKUPFR_WKUPF1              PWR_WKUPFR_WKUPF1_Msk                   /*!< Wakeup Pin Flag 1 */
+
+/******************  Bit definition for PWR_WKUPEPR register  *****************/
+#define PWR_WKUPEPR_WKUPPUPD6_Pos      (26U)
+#define PWR_WKUPEPR_WKUPPUPD6_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x0C000000 */
+#define PWR_WKUPEPR_WKUPPUPD6          PWR_WKUPEPR_WKUPPUPD6_Msk               /*!< Wakeup Pin pull configuration for WKUP6 */
+#define PWR_WKUPEPR_WKUPPUPD6_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x04000000 */
+#define PWR_WKUPEPR_WKUPPUPD6_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x08000000 */
+#define PWR_WKUPEPR_WKUPPUPD5_Pos      (24U)
+#define PWR_WKUPEPR_WKUPPUPD5_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x03000000 */
+#define PWR_WKUPEPR_WKUPPUPD5          PWR_WKUPEPR_WKUPPUPD5_Msk               /*!< Wakeup Pin pull configuration for WKUP5 */
+#define PWR_WKUPEPR_WKUPPUPD5_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x01000000 */
+#define PWR_WKUPEPR_WKUPPUPD5_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x02000000 */
+#define PWR_WKUPEPR_WKUPPUPD4_Pos      (22U)
+#define PWR_WKUPEPR_WKUPPUPD4_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00C00000 */
+#define PWR_WKUPEPR_WKUPPUPD4          PWR_WKUPEPR_WKUPPUPD4_Msk               /*!< Wakeup Pin pull configuration for WKUP4 */
+#define PWR_WKUPEPR_WKUPPUPD4_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00400000 */
+#define PWR_WKUPEPR_WKUPPUPD4_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00800000 */
+#define PWR_WKUPEPR_WKUPPUPD3_Pos      (20U)
+#define PWR_WKUPEPR_WKUPPUPD3_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00300000 */
+#define PWR_WKUPEPR_WKUPPUPD3          PWR_WKUPEPR_WKUPPUPD3_Msk               /*!< Wakeup Pin pull configuration for WKUP3 */
+#define PWR_WKUPEPR_WKUPPUPD3_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00100000 */
+#define PWR_WKUPEPR_WKUPPUPD3_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00200000 */
+#define PWR_WKUPEPR_WKUPPUPD2_Pos      (18U)
+#define PWR_WKUPEPR_WKUPPUPD2_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x000C0000 */
+#define PWR_WKUPEPR_WKUPPUPD2          PWR_WKUPEPR_WKUPPUPD2_Msk               /*!< Wakeup Pin pull configuration for WKUP2 */
+#define PWR_WKUPEPR_WKUPPUPD2_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00040000 */
+#define PWR_WKUPEPR_WKUPPUPD2_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00080000 */
+#define PWR_WKUPEPR_WKUPPUPD1_Pos      (16U)
+#define PWR_WKUPEPR_WKUPPUPD1_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00030000 */
+#define PWR_WKUPEPR_WKUPPUPD1          PWR_WKUPEPR_WKUPPUPD1_Msk               /*!< Wakeup Pin pull configuration for WKUP1 */
+#define PWR_WKUPEPR_WKUPPUPD1_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00010000 */
+#define PWR_WKUPEPR_WKUPPUPD1_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00020000 */
+#define PWR_WKUPEPR_WKUPP6_Pos         (13U)
+#define PWR_WKUPEPR_WKUPP6_Msk         (0x1UL << PWR_WKUPEPR_WKUPP6_Pos)       /*!< 0x00002000 */
+#define PWR_WKUPEPR_WKUPP6             PWR_WKUPEPR_WKUPP6_Msk                  /*!< Wakeup Pin Polarity for WKUP6 */
+#define PWR_WKUPEPR_WKUPP5_Pos         (12U)
+#define PWR_WKUPEPR_WKUPP5_Msk         (0x1UL << PWR_WKUPEPR_WKUPP5_Pos)       /*!< 0x00001000 */
+#define PWR_WKUPEPR_WKUPP5             PWR_WKUPEPR_WKUPP5_Msk                  /*!< Wakeup Pin Polarity for WKUP5 */
+#define PWR_WKUPEPR_WKUPP4_Pos         (11U)
+#define PWR_WKUPEPR_WKUPP4_Msk         (0x1UL << PWR_WKUPEPR_WKUPP4_Pos)       /*!< 0x00000800 */
+#define PWR_WKUPEPR_WKUPP4             PWR_WKUPEPR_WKUPP4_Msk                  /*!< Wakeup Pin Polarity for WKUP4 */
+#define PWR_WKUPEPR_WKUPP3_Pos         (10U)
+#define PWR_WKUPEPR_WKUPP3_Msk         (0x1UL << PWR_WKUPEPR_WKUPP3_Pos)       /*!< 0x00000400 */
+#define PWR_WKUPEPR_WKUPP3             PWR_WKUPEPR_WKUPP3_Msk                  /*!< Wakeup Pin Polarity for WKUP3 */
+#define PWR_WKUPEPR_WKUPP2_Pos         (9U)
+#define PWR_WKUPEPR_WKUPP2_Msk         (0x1UL << PWR_WKUPEPR_WKUPP2_Pos)       /*!< 0x00000200 */
+#define PWR_WKUPEPR_WKUPP2             PWR_WKUPEPR_WKUPP2_Msk                  /*!< Wakeup Pin Polarity for WKUP2 */
+#define PWR_WKUPEPR_WKUPP1_Pos         (8U)
+#define PWR_WKUPEPR_WKUPP1_Msk         (0x1UL << PWR_WKUPEPR_WKUPP1_Pos)       /*!< 0x00000100 */
+#define PWR_WKUPEPR_WKUPP1             PWR_WKUPEPR_WKUPP1_Msk                  /*!< Wakeup Pin Polarity for WKUP1 */
+#define PWR_WKUPEPR_WKUPEN6_Pos        (5U)
+#define PWR_WKUPEPR_WKUPEN6_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN6_Pos)      /*!< 0x00000020 */
+#define PWR_WKUPEPR_WKUPEN6            PWR_WKUPEPR_WKUPEN6_Msk                 /*!< Enable Wakeup Pin WKUP6 */
+#define PWR_WKUPEPR_WKUPEN5_Pos        (4U)
+#define PWR_WKUPEPR_WKUPEN5_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN5_Pos)      /*!< 0x00000010 */
+#define PWR_WKUPEPR_WKUPEN5            PWR_WKUPEPR_WKUPEN5_Msk                 /*!< Enable Wakeup Pin WKUP5 */
+#define PWR_WKUPEPR_WKUPEN4_Pos        (3U)
+#define PWR_WKUPEPR_WKUPEN4_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos)      /*!< 0x00000008 */
+#define PWR_WKUPEPR_WKUPEN4            PWR_WKUPEPR_WKUPEN4_Msk                 /*!< Enable Wakeup Pin WKUP4 */
+#define PWR_WKUPEPR_WKUPEN3_Pos        (2U)
+#define PWR_WKUPEPR_WKUPEN3_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos)      /*!< 0x00000004 */
+#define PWR_WKUPEPR_WKUPEN3            PWR_WKUPEPR_WKUPEN3_Msk                 /*!< Enable Wakeup Pin WKUP3 */
+#define PWR_WKUPEPR_WKUPEN2_Pos        (1U)
+#define PWR_WKUPEPR_WKUPEN2_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos)      /*!< 0x00000002 */
+#define PWR_WKUPEPR_WKUPEN2            PWR_WKUPEPR_WKUPEN2_Msk                 /*!< Enable Wakeup Pin WKUP2 */
+#define PWR_WKUPEPR_WKUPEN1_Pos        (0U)
+#define PWR_WKUPEPR_WKUPEN1_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos)      /*!< 0x00000001 */
+#define PWR_WKUPEPR_WKUPEN1            PWR_WKUPEPR_WKUPEN1_Msk                 /*!< Enable Wakeup Pin WKUP1 */
+#define PWR_WKUPEPR_WKUPEN_Pos         (0U)
+#define PWR_WKUPEPR_WKUPEN_Msk         (0x3FUL << PWR_WKUPEPR_WKUPEN_Pos)      /*!< 0x0000003F */
+#define PWR_WKUPEPR_WKUPEN             PWR_WKUPEPR_WKUPEN_Msk                  /*!< Enable all Wakeup Pin */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Reset and Clock Control                            */
+/*                                                                            */
+/******************************************************************************/
+/*******************************  RCC VERSION  ********************************/
+#define RCC_VER_X
+
+/********************  Bit definition for RCC_CR register  ********************/
+#define RCC_CR_HSION_Pos                       (0U)
+#define RCC_CR_HSION_Msk                       (0x1UL << RCC_CR_HSION_Pos)     /*!< 0x00000001 */
+#define RCC_CR_HSION                           RCC_CR_HSION_Msk                /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIKERON_Pos                    (1U)
+#define RCC_CR_HSIKERON_Msk                    (0x1UL << RCC_CR_HSIKERON_Pos)  /*!< 0x00000002 */
+#define RCC_CR_HSIKERON                        RCC_CR_HSIKERON_Msk             /*!< Internal High Speed clock enable for some IPs Kernel */
+#define RCC_CR_HSIRDY_Pos                      (2U)
+#define RCC_CR_HSIRDY_Msk                      (0x1UL << RCC_CR_HSIRDY_Pos)    /*!< 0x00000004 */
+#define RCC_CR_HSIRDY                          RCC_CR_HSIRDY_Msk               /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSIDIV_Pos                      (3U)
+#define RCC_CR_HSIDIV_Msk                      (0x3UL << RCC_CR_HSIDIV_Pos)    /*!< 0x00000018 */
+#define RCC_CR_HSIDIV                          RCC_CR_HSIDIV_Msk               /*!< Internal High Speed clock divider selection */
+#define RCC_CR_HSIDIV_1                        (0x0UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000000 */
+#define RCC_CR_HSIDIV_2                        (0x1UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000008 */
+#define RCC_CR_HSIDIV_4                        (0x2UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000010 */
+#define RCC_CR_HSIDIV_8                        (0x3UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000018 */
+
+#define RCC_CR_HSIDIVF_Pos                     (5U)
+#define RCC_CR_HSIDIVF_Msk                     (0x1UL << RCC_CR_HSIDIVF_Pos)   /*!< 0x00000020 */
+#define RCC_CR_HSIDIVF                         RCC_CR_HSIDIVF_Msk              /*!< HSI Divider flag */
+#define RCC_CR_CSION_Pos                       (7U)
+#define RCC_CR_CSION_Msk                       (0x1UL << RCC_CR_CSION_Pos)     /*!< 0x00000080 */
+#define RCC_CR_CSION                           RCC_CR_CSION_Msk                /*!< The Internal RC 4MHz oscillator clock enable */
+#define RCC_CR_CSIRDY_Pos                      (8U)
+#define RCC_CR_CSIRDY_Msk                      (0x1UL << RCC_CR_CSIRDY_Pos)    /*!< 0x00000100 */
+#define RCC_CR_CSIRDY                          RCC_CR_CSIRDY_Msk               /*!< The Internal RC 4MHz oscillator clock ready */
+#define RCC_CR_CSIKERON_Pos                    (9U)
+#define RCC_CR_CSIKERON_Msk                    (0x1UL << RCC_CR_CSIKERON_Pos)  /*!< 0x00000200 */
+#define RCC_CR_CSIKERON                        RCC_CR_CSIKERON_Msk             /*!< Internal RC 4MHz oscillator clock enable for some IPs Kernel */
+#define RCC_CR_HSI48ON_Pos                     (12U)
+#define RCC_CR_HSI48ON_Msk                     (0x1UL << RCC_CR_HSI48ON_Pos)   /*!< 0x00001000 */
+#define RCC_CR_HSI48ON                         RCC_CR_HSI48ON_Msk              /*!< HSI48 clock enable clock enable  */
+#define RCC_CR_HSI48RDY_Pos                    (13U)
+#define RCC_CR_HSI48RDY_Msk                    (0x1UL << RCC_CR_HSI48RDY_Pos)  /*!< 0x00002000 */
+#define RCC_CR_HSI48RDY                        RCC_CR_HSI48RDY_Msk             /*!< HSI48 clock ready */
+
+#define RCC_CR_D1CKRDY_Pos                     (14U)
+#define RCC_CR_D1CKRDY_Msk                     (0x1UL << RCC_CR_D1CKRDY_Pos)   /*!< 0x00004000 */
+#define RCC_CR_D1CKRDY                         RCC_CR_D1CKRDY_Msk              /*!< D1 domain clocks ready flag  */
+#define RCC_CR_D2CKRDY_Pos                     (15U)
+#define RCC_CR_D2CKRDY_Msk                     (0x1UL << RCC_CR_D2CKRDY_Pos)   /*!< 0x00008000 */
+#define RCC_CR_D2CKRDY                         RCC_CR_D2CKRDY_Msk              /*!< D2 domain clocks ready flag */
+
+#define RCC_CR_HSEON_Pos                       (16U)
+#define RCC_CR_HSEON_Msk                       (0x1UL << RCC_CR_HSEON_Pos)     /*!< 0x00010000 */
+#define RCC_CR_HSEON                           RCC_CR_HSEON_Msk                /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY_Pos                      (17U)
+#define RCC_CR_HSERDY_Msk                      (0x1UL << RCC_CR_HSERDY_Pos)    /*!< 0x00020000 */
+#define RCC_CR_HSERDY                          RCC_CR_HSERDY_Msk               /*!< External High Speed clock ready */
+#define RCC_CR_HSEBYP_Pos                      (18U)
+#define RCC_CR_HSEBYP_Msk                      (0x1UL << RCC_CR_HSEBYP_Pos)    /*!< 0x00040000 */
+#define RCC_CR_HSEBYP                          RCC_CR_HSEBYP_Msk               /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSHSEON_Pos                    (19U)
+#define RCC_CR_CSSHSEON_Msk                    (0x1UL << RCC_CR_CSSHSEON_Pos)  /*!< 0x00080000 */
+#define RCC_CR_CSSHSEON                        RCC_CR_CSSHSEON_Msk             /*!< HSE Clock security System enable */
+
+
+#define RCC_CR_PLL1ON_Pos                      (24U)
+#define RCC_CR_PLL1ON_Msk                      (0x1UL << RCC_CR_PLL1ON_Pos)    /*!< 0x01000000 */
+#define RCC_CR_PLL1ON                          RCC_CR_PLL1ON_Msk               /*!< System PLL1 clock enable */
+#define RCC_CR_PLL1RDY_Pos                     (25U)
+#define RCC_CR_PLL1RDY_Msk                     (0x1UL << RCC_CR_PLL1RDY_Pos)   /*!< 0x02000000 */
+#define RCC_CR_PLL1RDY                         RCC_CR_PLL1RDY_Msk              /*!< System PLL1 clock ready */
+#define RCC_CR_PLL2ON_Pos                      (26U)
+#define RCC_CR_PLL2ON_Msk                      (0x1UL << RCC_CR_PLL2ON_Pos)    /*!< 0x04000000 */
+#define RCC_CR_PLL2ON                          RCC_CR_PLL2ON_Msk               /*!< System PLL2 clock enable */
+#define RCC_CR_PLL2RDY_Pos                     (27U)
+#define RCC_CR_PLL2RDY_Msk                     (0x1UL << RCC_CR_PLL2RDY_Pos)   /*!< 0x08000000 */
+#define RCC_CR_PLL2RDY                         RCC_CR_PLL2RDY_Msk              /*!< System PLL2 clock ready */
+#define RCC_CR_PLL3ON_Pos                      (28U)
+#define RCC_CR_PLL3ON_Msk                      (0x1UL << RCC_CR_PLL3ON_Pos)    /*!< 0x10000000 */
+#define RCC_CR_PLL3ON                          RCC_CR_PLL3ON_Msk               /*!< System PLL3 clock enable */
+#define RCC_CR_PLL3RDY_Pos                     (29U)
+#define RCC_CR_PLL3RDY_Msk                     (0x1UL << RCC_CR_PLL3RDY_Pos)   /*!< 0x20000000 */
+#define RCC_CR_PLL3RDY                         RCC_CR_PLL3RDY_Msk              /*!< System PLL3 clock ready */
+
+/*Legacy */
+#define RCC_CR_PLLON_Pos                       (24U)
+#define RCC_CR_PLLON_Msk                       (0x1UL << RCC_CR_PLLON_Pos)     /*!< 0x01000000 */
+#define RCC_CR_PLLON                           RCC_CR_PLLON_Msk                /*!< System PLL clock enable */
+#define RCC_CR_PLLRDY_Pos                      (25U)
+#define RCC_CR_PLLRDY_Msk                      (0x1UL << RCC_CR_PLLRDY_Pos)    /*!< 0x02000000 */
+#define RCC_CR_PLLRDY                          RCC_CR_PLLRDY_Msk               /*!< System PLL clock ready */
+
+/********************  Bit definition for RCC_HSICFGR register  ***************/
+/*!< HSICAL configuration */
+#define RCC_HSICFGR_HSICAL_Pos                 (0U)
+#define RCC_HSICFGR_HSICAL_Msk                 (0xFFFUL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000FFF */
+#define RCC_HSICFGR_HSICAL                     RCC_HSICFGR_HSICAL_Msk          /*!< HSICAL[11:0] bits */
+#define RCC_HSICFGR_HSICAL_0                   (0x001UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000001 */
+#define RCC_HSICFGR_HSICAL_1                   (0x002UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000002 */
+#define RCC_HSICFGR_HSICAL_2                   (0x004UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000004 */
+#define RCC_HSICFGR_HSICAL_3                   (0x008UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000008 */
+#define RCC_HSICFGR_HSICAL_4                   (0x010UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000010 */
+#define RCC_HSICFGR_HSICAL_5                   (0x020UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000020 */
+#define RCC_HSICFGR_HSICAL_6                   (0x040UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000040 */
+#define RCC_HSICFGR_HSICAL_7                   (0x080UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000080 */
+#define RCC_HSICFGR_HSICAL_8                   (0x100UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000100 */
+#define RCC_HSICFGR_HSICAL_9                   (0x200UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000200 */
+#define RCC_HSICFGR_HSICAL_10                  (0x400UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000400 */
+#define RCC_HSICFGR_HSICAL_11                  (0x800UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000800 */
+
+/*!< HSITRIM configuration */
+#define RCC_HSICFGR_HSITRIM_Pos                (24U)
+#define RCC_HSICFGR_HSITRIM_Msk                (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x7F000000 */
+#define RCC_HSICFGR_HSITRIM                    RCC_HSICFGR_HSITRIM_Msk         /*!< HSITRIM[6:0] bits */
+#define RCC_HSICFGR_HSITRIM_0                  (0x01UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x01000000 */
+#define RCC_HSICFGR_HSITRIM_1                  (0x02UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x02000000 */
+#define RCC_HSICFGR_HSITRIM_2                  (0x04UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x04000000 */
+#define RCC_HSICFGR_HSITRIM_3                  (0x08UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x08000000 */
+#define RCC_HSICFGR_HSITRIM_4                  (0x10UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x10000000 */
+#define RCC_HSICFGR_HSITRIM_5                  (0x20UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x20000000 */
+#define RCC_HSICFGR_HSITRIM_6                  (0x40UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x40000000 */
+
+
+/********************  Bit definition for RCC_CRRCR register  *****************/
+
+/*!< HSI48CAL configuration */
+#define RCC_CRRCR_HSI48CAL_Pos                 (0U)
+#define RCC_CRRCR_HSI48CAL_Msk                 (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x000003FF */
+#define RCC_CRRCR_HSI48CAL                     RCC_CRRCR_HSI48CAL_Msk          /*!< HSI48CAL[9:0] bits */
+#define RCC_CRRCR_HSI48CAL_0                   (0x001UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000001 */
+#define RCC_CRRCR_HSI48CAL_1                   (0x002UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000002 */
+#define RCC_CRRCR_HSI48CAL_2                   (0x004UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000004 */
+#define RCC_CRRCR_HSI48CAL_3                   (0x008UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000008 */
+#define RCC_CRRCR_HSI48CAL_4                   (0x010UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000010 */
+#define RCC_CRRCR_HSI48CAL_5                   (0x020UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000020 */
+#define RCC_CRRCR_HSI48CAL_6                   (0x040UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000040 */
+#define RCC_CRRCR_HSI48CAL_7                   (0x080UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */
+#define RCC_CRRCR_HSI48CAL_8                   (0x100UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */
+#define RCC_CRRCR_HSI48CAL_9                   (0x200UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */
+
+
+/********************  Bit definition for RCC_CSICFGR register  *****************/
+/*!< CSICAL configuration */
+#define RCC_CSICFGR_CSICAL_Pos                 (0U)
+#define RCC_CSICFGR_CSICAL_Msk                 (0xFFUL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x000000FF */
+#define RCC_CSICFGR_CSICAL                     RCC_CSICFGR_CSICAL_Msk          /*!< CSICAL[7:0] bits */
+#define RCC_CSICFGR_CSICAL_0                   (0x01UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000001 */
+#define RCC_CSICFGR_CSICAL_1                   (0x02UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000002 */
+#define RCC_CSICFGR_CSICAL_2                   (0x04UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000004 */
+#define RCC_CSICFGR_CSICAL_3                   (0x08UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000008 */
+#define RCC_CSICFGR_CSICAL_4                   (0x10UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000010 */
+#define RCC_CSICFGR_CSICAL_5                   (0x20UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000020 */
+#define RCC_CSICFGR_CSICAL_6                   (0x40UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000040 */
+#define RCC_CSICFGR_CSICAL_7                   (0x80UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000080 */
+
+/*!< CSITRIM configuration */
+#define RCC_CSICFGR_CSITRIM_Pos                (24U)
+#define RCC_CSICFGR_CSITRIM_Msk                (0x3FUL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x3F000000 */
+#define RCC_CSICFGR_CSITRIM                    RCC_CSICFGR_CSITRIM_Msk         /*!< CSITRIM[5:0] bits */
+#define RCC_CSICFGR_CSITRIM_0                  (0x01UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x01000000 */
+#define RCC_CSICFGR_CSITRIM_1                  (0x02UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x02000000 */
+#define RCC_CSICFGR_CSITRIM_2                  (0x04UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x04000000 */
+#define RCC_CSICFGR_CSITRIM_3                  (0x08UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x08000000 */
+#define RCC_CSICFGR_CSITRIM_4                  (0x10UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x10000000 */
+#define RCC_CSICFGR_CSITRIM_5                  (0x20UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x20000000 */
+
+/********************  Bit definition for RCC_CFGR register  ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos                        (0U)
+#define RCC_CFGR_SW_Msk                        (0x7UL << RCC_CFGR_SW_Pos)           /*!< 0x00000007 */
+#define RCC_CFGR_SW                            RCC_CFGR_SW_Msk                     /*!< SW[2:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0                          (0x1UL << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */
+#define RCC_CFGR_SW_1                          (0x2UL << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */
+#define RCC_CFGR_SW_2                          (0x4UL << RCC_CFGR_SW_Pos)           /*!< 0x00000004 */
+
+#define RCC_CFGR_SW_HSI                        (0x00000000UL)                       /*!< HSI selection as system clock */
+#define RCC_CFGR_SW_CSI                        (0x00000001UL)                       /*!< CSI selection as system clock */
+#define RCC_CFGR_SW_HSE                        (0x00000002UL)                       /*!< HSE selection as system clock */
+#define RCC_CFGR_SW_PLL1                       (0x00000003UL)                       /*!< PLL1 selection as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos                       (3U)
+#define RCC_CFGR_SWS_Msk                       (0x7UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000038 */
+#define RCC_CFGR_SWS                           RCC_CFGR_SWS_Msk                    /*!< SWS[2:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0                         (0x1UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */
+#define RCC_CFGR_SWS_1                         (0x2UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000010 */
+#define RCC_CFGR_SWS_2                         (0x4UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000020 */
+
+#define RCC_CFGR_SWS_HSI                       (0x00000000UL)                       /*!< HSI used as system clock */
+#define RCC_CFGR_SWS_CSI                       (0x00000008UL)                       /*!< CSI used as system clock */
+#define RCC_CFGR_SWS_HSE                       (0x00000010UL)                       /*!< HSE used as system clock */
+#define RCC_CFGR_SWS_PLL1                      (0x00000018UL)                       /*!< PLL1 used as system clock */
+
+#define RCC_CFGR_STOPWUCK_Pos                  (6U)
+#define RCC_CFGR_STOPWUCK_Msk                  (0x1UL << RCC_CFGR_STOPWUCK_Pos)     /*!< 0x00000040 */
+#define RCC_CFGR_STOPWUCK                      RCC_CFGR_STOPWUCK_Msk                /*!< Wake Up from stop and CSS backup clock selection */
+
+#define RCC_CFGR_STOPKERWUCK_Pos               (7U)
+#define RCC_CFGR_STOPKERWUCK_Msk               (0x1UL << RCC_CFGR_STOPKERWUCK_Pos)  /*!< 0x00000080 */
+#define RCC_CFGR_STOPKERWUCK                   RCC_CFGR_STOPKERWUCK_Msk             /*!< Kernel Clock Selection after a Wake Up from STOP */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE_Pos                    (8U)
+#define RCC_CFGR_RTCPRE_Msk                    (0x3FUL << RCC_CFGR_RTCPRE_Pos)
+#define RCC_CFGR_RTCPRE                        RCC_CFGR_RTCPRE_Msk                  /*!< 0x00003F00 */
+#define RCC_CFGR_RTCPRE_0                      (0x1UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000100 */
+#define RCC_CFGR_RTCPRE_1                      (0x2UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000200 */
+#define RCC_CFGR_RTCPRE_2                      (0x4UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000400 */
+#define RCC_CFGR_RTCPRE_3                      (0x8UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000800 */
+#define RCC_CFGR_RTCPRE_4                      (0x10UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00001000 */
+#define RCC_CFGR_RTCPRE_5                      (0x20UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00002000 */
+
+/*!< HRTIMSEL configuration */
+#define RCC_CFGR_HRTIMSEL_Pos                  (14U)
+#define RCC_CFGR_HRTIMSEL_Msk                  (0x1UL << RCC_CFGR_HRTIMSEL_Pos)
+#define RCC_CFGR_HRTIMSEL                      RCC_CFGR_HRTIMSEL_Msk                /*!< 0x00004000 */
+
+/*!< TIMPRE configuration */
+#define RCC_CFGR_TIMPRE_Pos                    (15U)
+#define RCC_CFGR_TIMPRE_Msk                    (0x1UL << RCC_CFGR_TIMPRE_Pos)
+#define RCC_CFGR_TIMPRE                        RCC_CFGR_TIMPRE_Msk                  /*!< 0x00008000 */
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1_Pos                      (22U)
+#define RCC_CFGR_MCO1_Msk                      (0x7UL << RCC_CFGR_MCO1_Pos)
+#define RCC_CFGR_MCO1                          RCC_CFGR_MCO1_Msk                       /*!< 0x01C00000 */
+#define RCC_CFGR_MCO1_0                        (0x1UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00400000 */
+#define RCC_CFGR_MCO1_1                        (0x2UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00800000 */
+#define RCC_CFGR_MCO1_2                        (0x4UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x01000000 */
+
+#define RCC_CFGR_MCO1PRE_Pos                   (18U)
+#define RCC_CFGR_MCO1PRE_Msk                   (0xFUL << RCC_CFGR_MCO1PRE_Pos)
+#define RCC_CFGR_MCO1PRE                       RCC_CFGR_MCO1PRE_Msk                    /*!< 0x003C0000 */
+#define RCC_CFGR_MCO1PRE_0                     (0x1UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00040000 */
+#define RCC_CFGR_MCO1PRE_1                     (0x2UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00080000 */
+#define RCC_CFGR_MCO1PRE_2                     (0x4UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00100000 */
+#define RCC_CFGR_MCO1PRE_3                     (0x8UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00200000 */
+
+#define RCC_CFGR_MCO2PRE_Pos                   (25U)
+#define RCC_CFGR_MCO2PRE_Msk                   (0xFUL << RCC_CFGR_MCO2PRE_Pos)
+#define RCC_CFGR_MCO2PRE                       RCC_CFGR_MCO2PRE_Msk                    /*!< 0x1E000000 */
+#define RCC_CFGR_MCO2PRE_0                     (0x1UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x02000000 */
+#define RCC_CFGR_MCO2PRE_1                     (0x2UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x04000000 */
+#define RCC_CFGR_MCO2PRE_2                     (0x4UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x08000000 */
+#define RCC_CFGR_MCO2PRE_3                     (0x8UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x10000000 */
+
+#define RCC_CFGR_MCO2_Pos                      (29U)
+#define RCC_CFGR_MCO2_Msk                      (0x7UL << RCC_CFGR_MCO2_Pos)
+#define RCC_CFGR_MCO2                          RCC_CFGR_MCO2_Msk                       /*!< 0xE0000000 */
+#define RCC_CFGR_MCO2_0                        (0x1UL << RCC_CFGR_MCO2_Pos)             /*!< 0x20000000 */
+#define RCC_CFGR_MCO2_1                        (0x2UL << RCC_CFGR_MCO2_Pos)             /*!< 0x40000000 */
+#define RCC_CFGR_MCO2_2                        (0x4UL << RCC_CFGR_MCO2_Pos)             /*!< 0x80000000 */
+
+/********************  Bit definition for RCC_D1CFGR register  ******************/
+/*!< D1HPRE configuration */
+#define RCC_D1CFGR_HPRE_Pos                    (0U)
+#define RCC_D1CFGR_HPRE_Msk                    (0xFUL << RCC_D1CFGR_HPRE_Pos)  /*!< 0x0000000F */
+#define RCC_D1CFGR_HPRE                        RCC_D1CFGR_HPRE_Msk             /*!< HPRE[3:0] bits (AHB3 prescaler) */
+#define RCC_D1CFGR_HPRE_0                      (0x1UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000001 */
+#define RCC_D1CFGR_HPRE_1                      (0x2UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000002 */
+#define RCC_D1CFGR_HPRE_2                      (0x4UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000004 */
+#define RCC_D1CFGR_HPRE_3                      (0x8UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000008 */
+
+
+#define RCC_D1CFGR_HPRE_DIV1                   ((uint32_t)0x00000000)          /*!< AHB3 Clock not divided */
+#define RCC_D1CFGR_HPRE_DIV2_Pos               (3U)
+#define RCC_D1CFGR_HPRE_DIV2_Msk               (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */
+#define RCC_D1CFGR_HPRE_DIV2                   RCC_D1CFGR_HPRE_DIV2_Msk        /*!< AHB3 Clock divided by 2 */
+#define RCC_D1CFGR_HPRE_DIV4_Pos               (0U)
+#define RCC_D1CFGR_HPRE_DIV4_Msk               (0x9UL << RCC_D1CFGR_HPRE_DIV4_Pos) /*!< 0x00000009 */
+#define RCC_D1CFGR_HPRE_DIV4                   RCC_D1CFGR_HPRE_DIV4_Msk        /*!< AHB3 Clock divided by 4 */
+#define RCC_D1CFGR_HPRE_DIV8_Pos               (1U)
+#define RCC_D1CFGR_HPRE_DIV8_Msk               (0x5UL << RCC_D1CFGR_HPRE_DIV8_Pos) /*!< 0x0000000A */
+#define RCC_D1CFGR_HPRE_DIV8                   RCC_D1CFGR_HPRE_DIV8_Msk        /*!< AHB3 Clock divided by 8 */
+#define RCC_D1CFGR_HPRE_DIV16_Pos              (0U)
+#define RCC_D1CFGR_HPRE_DIV16_Msk              (0xBUL << RCC_D1CFGR_HPRE_DIV16_Pos) /*!< 0x0000000B */
+#define RCC_D1CFGR_HPRE_DIV16                  RCC_D1CFGR_HPRE_DIV16_Msk       /*!< AHB3 Clock divided by 16 */
+#define RCC_D1CFGR_HPRE_DIV64_Pos              (2U)
+#define RCC_D1CFGR_HPRE_DIV64_Msk              (0x3UL << RCC_D1CFGR_HPRE_DIV64_Pos) /*!< 0x0000000C */
+#define RCC_D1CFGR_HPRE_DIV64                  RCC_D1CFGR_HPRE_DIV64_Msk       /*!< AHB3 Clock divided by 64 */
+#define RCC_D1CFGR_HPRE_DIV128_Pos             (0U)
+#define RCC_D1CFGR_HPRE_DIV128_Msk             (0xDUL << RCC_D1CFGR_HPRE_DIV128_Pos) /*!< 0x0000000D */
+#define RCC_D1CFGR_HPRE_DIV128                 RCC_D1CFGR_HPRE_DIV128_Msk      /*!< AHB3 Clock divided by 128 */
+#define RCC_D1CFGR_HPRE_DIV256_Pos             (1U)
+#define RCC_D1CFGR_HPRE_DIV256_Msk             (0x7UL << RCC_D1CFGR_HPRE_DIV256_Pos) /*!< 0x0000000E */
+#define RCC_D1CFGR_HPRE_DIV256                 RCC_D1CFGR_HPRE_DIV256_Msk      /*!< AHB3 Clock divided by 256 */
+#define RCC_D1CFGR_HPRE_DIV512_Pos             (0U)
+#define RCC_D1CFGR_HPRE_DIV512_Msk             (0xFUL << RCC_D1CFGR_HPRE_DIV512_Pos) /*!< 0x0000000F */
+#define RCC_D1CFGR_HPRE_DIV512                 RCC_D1CFGR_HPRE_DIV512_Msk      /*!< AHB3 Clock divided by 512 */
+
+/*!< D1PPRE configuration */
+#define RCC_D1CFGR_D1PPRE_Pos                  (4U)
+#define RCC_D1CFGR_D1PPRE_Msk                  (0x7UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000070 */
+#define RCC_D1CFGR_D1PPRE                      RCC_D1CFGR_D1PPRE_Msk           /*!< D1PRE[2:0] bits (APB3 prescaler) */
+#define RCC_D1CFGR_D1PPRE_0                    (0x1UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000010 */
+#define RCC_D1CFGR_D1PPRE_1                    (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */
+#define RCC_D1CFGR_D1PPRE_2                    (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */
+
+#define RCC_D1CFGR_D1PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB3 clock not divided */
+#define RCC_D1CFGR_D1PPRE_DIV2_Pos             (6U)
+#define RCC_D1CFGR_D1PPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */
+#define RCC_D1CFGR_D1PPRE_DIV2                 RCC_D1CFGR_D1PPRE_DIV2_Msk      /*!< APB3 clock divided by 2 */
+#define RCC_D1CFGR_D1PPRE_DIV4_Pos             (4U)
+#define RCC_D1CFGR_D1PPRE_DIV4_Msk             (0x5UL << RCC_D1CFGR_D1PPRE_DIV4_Pos) /*!< 0x00000050 */
+#define RCC_D1CFGR_D1PPRE_DIV4                 RCC_D1CFGR_D1PPRE_DIV4_Msk      /*!< APB3 clock divided by 4 */
+#define RCC_D1CFGR_D1PPRE_DIV8_Pos             (5U)
+#define RCC_D1CFGR_D1PPRE_DIV8_Msk             (0x3UL << RCC_D1CFGR_D1PPRE_DIV8_Pos) /*!< 0x00000060 */
+#define RCC_D1CFGR_D1PPRE_DIV8                 RCC_D1CFGR_D1PPRE_DIV8_Msk      /*!< APB3 clock divided by 8 */
+#define RCC_D1CFGR_D1PPRE_DIV16_Pos            (4U)
+#define RCC_D1CFGR_D1PPRE_DIV16_Msk            (0x7UL << RCC_D1CFGR_D1PPRE_DIV16_Pos) /*!< 0x00000070 */
+#define RCC_D1CFGR_D1PPRE_DIV16                RCC_D1CFGR_D1PPRE_DIV16_Msk     /*!< APB3 clock divided by 16 */
+
+#define RCC_D1CFGR_D1CPRE_Pos                  (8U)
+#define RCC_D1CFGR_D1CPRE_Msk                  (0xFUL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000F00 */
+#define RCC_D1CFGR_D1CPRE                      RCC_D1CFGR_D1CPRE_Msk           /*!< D1CPRE[2:0] bits (Domain 1 Core prescaler) */
+#define RCC_D1CFGR_D1CPRE_0                    (0x1UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000100 */
+#define RCC_D1CFGR_D1CPRE_1                    (0x2UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000200 */
+#define RCC_D1CFGR_D1CPRE_2                    (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */
+#define RCC_D1CFGR_D1CPRE_3                    (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */
+
+#define RCC_D1CFGR_D1CPRE_DIV1                 ((uint32_t)0x00000000)          /*!< Domain 1 Core clock not divided */
+#define RCC_D1CFGR_D1CPRE_DIV2_Pos             (11U)
+#define RCC_D1CFGR_D1CPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */
+#define RCC_D1CFGR_D1CPRE_DIV2                 RCC_D1CFGR_D1CPRE_DIV2_Msk      /*!< Domain 1 Core clock divided by 2 */
+#define RCC_D1CFGR_D1CPRE_DIV4_Pos             (8U)
+#define RCC_D1CFGR_D1CPRE_DIV4_Msk             (0x9UL << RCC_D1CFGR_D1CPRE_DIV4_Pos) /*!< 0x00000900 */
+#define RCC_D1CFGR_D1CPRE_DIV4                 RCC_D1CFGR_D1CPRE_DIV4_Msk      /*!< Domain 1 Core clock divided by 4 */
+#define RCC_D1CFGR_D1CPRE_DIV8_Pos             (9U)
+#define RCC_D1CFGR_D1CPRE_DIV8_Msk             (0x5UL << RCC_D1CFGR_D1CPRE_DIV8_Pos) /*!< 0x00000A00 */
+#define RCC_D1CFGR_D1CPRE_DIV8                 RCC_D1CFGR_D1CPRE_DIV8_Msk      /*!< Domain 1 Core clock divided by 8 */
+#define RCC_D1CFGR_D1CPRE_DIV16_Pos            (8U)
+#define RCC_D1CFGR_D1CPRE_DIV16_Msk            (0xBUL << RCC_D1CFGR_D1CPRE_DIV16_Pos) /*!< 0x00000B00 */
+#define RCC_D1CFGR_D1CPRE_DIV16                RCC_D1CFGR_D1CPRE_DIV16_Msk     /*!< Domain 1 Core clock divided by 16 */
+#define RCC_D1CFGR_D1CPRE_DIV64_Pos            (10U)
+#define RCC_D1CFGR_D1CPRE_DIV64_Msk            (0x3UL << RCC_D1CFGR_D1CPRE_DIV64_Pos) /*!< 0x00000C00 */
+#define RCC_D1CFGR_D1CPRE_DIV64                RCC_D1CFGR_D1CPRE_DIV64_Msk     /*!< Domain 1 Core clock divided by 64 */
+#define RCC_D1CFGR_D1CPRE_DIV128_Pos           (8U)
+#define RCC_D1CFGR_D1CPRE_DIV128_Msk           (0xDUL << RCC_D1CFGR_D1CPRE_DIV128_Pos) /*!< 0x00000D00 */
+#define RCC_D1CFGR_D1CPRE_DIV128               RCC_D1CFGR_D1CPRE_DIV128_Msk    /*!< Domain 1 Core clock divided by 128 */
+#define RCC_D1CFGR_D1CPRE_DIV256_Pos           (9U)
+#define RCC_D1CFGR_D1CPRE_DIV256_Msk           (0x7UL << RCC_D1CFGR_D1CPRE_DIV256_Pos) /*!< 0x00000E00 */
+#define RCC_D1CFGR_D1CPRE_DIV256               RCC_D1CFGR_D1CPRE_DIV256_Msk    /*!< Domain 1 Core clock divided by 256 */
+#define RCC_D1CFGR_D1CPRE_DIV512_Pos           (8U)
+#define RCC_D1CFGR_D1CPRE_DIV512_Msk           (0xFUL << RCC_D1CFGR_D1CPRE_DIV512_Pos) /*!< 0x00000F00 */
+#define RCC_D1CFGR_D1CPRE_DIV512               RCC_D1CFGR_D1CPRE_DIV512_Msk    /*!< Domain 1 Core clock divided by 512 */
+
+/********************  Bit definition for RCC_D2CFGR register  ******************/
+/*!< D2PPRE1 configuration */
+#define RCC_D2CFGR_D2PPRE1_Pos                 (4U)
+#define RCC_D2CFGR_D2PPRE1_Msk                 (0x7UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000070 */
+#define RCC_D2CFGR_D2PPRE1                     RCC_D2CFGR_D2PPRE1_Msk          /*!< D1PPRE1[2:0] bits (APB1 prescaler) */
+#define RCC_D2CFGR_D2PPRE1_0                   (0x1UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000010 */
+#define RCC_D2CFGR_D2PPRE1_1                   (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */
+#define RCC_D2CFGR_D2PPRE1_2                   (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */
+
+#define RCC_D2CFGR_D2PPRE1_DIV1                ((uint32_t)0x00000000)          /*!< APB1 clock not divided */
+#define RCC_D2CFGR_D2PPRE1_DIV2_Pos            (6U)
+#define RCC_D2CFGR_D2PPRE1_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */
+#define RCC_D2CFGR_D2PPRE1_DIV2                RCC_D2CFGR_D2PPRE1_DIV2_Msk     /*!< APB1 clock divided by 2 */
+#define RCC_D2CFGR_D2PPRE1_DIV4_Pos            (4U)
+#define RCC_D2CFGR_D2PPRE1_DIV4_Msk            (0x5UL << RCC_D2CFGR_D2PPRE1_DIV4_Pos) /*!< 0x00000050 */
+#define RCC_D2CFGR_D2PPRE1_DIV4                RCC_D2CFGR_D2PPRE1_DIV4_Msk     /*!< APB1 clock divided by 4 */
+#define RCC_D2CFGR_D2PPRE1_DIV8_Pos            (5U)
+#define RCC_D2CFGR_D2PPRE1_DIV8_Msk            (0x3UL << RCC_D2CFGR_D2PPRE1_DIV8_Pos) /*!< 0x00000060 */
+#define RCC_D2CFGR_D2PPRE1_DIV8                RCC_D2CFGR_D2PPRE1_DIV8_Msk     /*!< APB1 clock divided by 8 */
+#define RCC_D2CFGR_D2PPRE1_DIV16_Pos           (4U)
+#define RCC_D2CFGR_D2PPRE1_DIV16_Msk           (0x7UL << RCC_D2CFGR_D2PPRE1_DIV16_Pos) /*!< 0x00000070 */
+#define RCC_D2CFGR_D2PPRE1_DIV16               RCC_D2CFGR_D2PPRE1_DIV16_Msk    /*!< APB1 clock divided by 16 */
+
+/*!< D2PPRE2 configuration */
+#define RCC_D2CFGR_D2PPRE2_Pos                 (8U)
+#define RCC_D2CFGR_D2PPRE2_Msk                 (0x7UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000700 */
+#define RCC_D2CFGR_D2PPRE2                     RCC_D2CFGR_D2PPRE2_Msk          /*!< D2PPRE2[2:0] bits (APB2 prescaler) */
+#define RCC_D2CFGR_D2PPRE2_0                   (0x1UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000100 */
+#define RCC_D2CFGR_D2PPRE2_1                   (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */
+#define RCC_D2CFGR_D2PPRE2_2                   (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */
+
+#define RCC_D2CFGR_D2PPRE2_DIV1                ((uint32_t)0x00000000)          /*!< APB2 clock not divided */
+#define RCC_D2CFGR_D2PPRE2_DIV2_Pos            (10U)
+#define RCC_D2CFGR_D2PPRE2_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */
+#define RCC_D2CFGR_D2PPRE2_DIV2                RCC_D2CFGR_D2PPRE2_DIV2_Msk     /*!< APB2 clock divided by 2 */
+#define RCC_D2CFGR_D2PPRE2_DIV4_Pos            (8U)
+#define RCC_D2CFGR_D2PPRE2_DIV4_Msk            (0x5UL << RCC_D2CFGR_D2PPRE2_DIV4_Pos) /*!< 0x00000500 */
+#define RCC_D2CFGR_D2PPRE2_DIV4                RCC_D2CFGR_D2PPRE2_DIV4_Msk     /*!< APB2 clock divided by 4 */
+#define RCC_D2CFGR_D2PPRE2_DIV8_Pos            (9U)
+#define RCC_D2CFGR_D2PPRE2_DIV8_Msk            (0x3UL << RCC_D2CFGR_D2PPRE2_DIV8_Pos) /*!< 0x00000600 */
+#define RCC_D2CFGR_D2PPRE2_DIV8                RCC_D2CFGR_D2PPRE2_DIV8_Msk     /*!< APB2 clock divided by 8 */
+#define RCC_D2CFGR_D2PPRE2_DIV16_Pos           (8U)
+#define RCC_D2CFGR_D2PPRE2_DIV16_Msk           (0x7UL << RCC_D2CFGR_D2PPRE2_DIV16_Pos) /*!< 0x00000700 */
+#define RCC_D2CFGR_D2PPRE2_DIV16               RCC_D2CFGR_D2PPRE2_DIV16_Msk    /*!< APB2 clock divided by 16 */
+
+/********************  Bit definition for RCC_D3CFGR register  ******************/
+/*!< D3PPRE configuration */
+#define RCC_D3CFGR_D3PPRE_Pos                  (4U)
+#define RCC_D3CFGR_D3PPRE_Msk                  (0x7UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000070 */
+#define RCC_D3CFGR_D3PPRE                      RCC_D3CFGR_D3PPRE_Msk           /*!< D3PPRE1[2:0] bits (APB4 prescaler) */
+#define RCC_D3CFGR_D3PPRE_0                    (0x1UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000010 */
+#define RCC_D3CFGR_D3PPRE_1                    (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */
+#define RCC_D3CFGR_D3PPRE_2                    (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */
+
+#define RCC_D3CFGR_D3PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB4 clock not divided */
+#define RCC_D3CFGR_D3PPRE_DIV2_Pos             (6U)
+#define RCC_D3CFGR_D3PPRE_DIV2_Msk             (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */
+#define RCC_D3CFGR_D3PPRE_DIV2                 RCC_D3CFGR_D3PPRE_DIV2_Msk      /*!< APB4 clock divided by 2 */
+#define RCC_D3CFGR_D3PPRE_DIV4_Pos             (4U)
+#define RCC_D3CFGR_D3PPRE_DIV4_Msk             (0x5UL << RCC_D3CFGR_D3PPRE_DIV4_Pos) /*!< 0x00000050 */
+#define RCC_D3CFGR_D3PPRE_DIV4                 RCC_D3CFGR_D3PPRE_DIV4_Msk      /*!< APB4 clock divided by 4 */
+#define RCC_D3CFGR_D3PPRE_DIV8_Pos             (5U)
+#define RCC_D3CFGR_D3PPRE_DIV8_Msk             (0x3UL << RCC_D3CFGR_D3PPRE_DIV8_Pos) /*!< 0x00000060 */
+#define RCC_D3CFGR_D3PPRE_DIV8                 RCC_D3CFGR_D3PPRE_DIV8_Msk      /*!< APB4 clock divided by 8 */
+#define RCC_D3CFGR_D3PPRE_DIV16_Pos            (4U)
+#define RCC_D3CFGR_D3PPRE_DIV16_Msk            (0x7UL << RCC_D3CFGR_D3PPRE_DIV16_Pos) /*!< 0x00000070 */
+#define RCC_D3CFGR_D3PPRE_DIV16                RCC_D3CFGR_D3PPRE_DIV16_Msk     /*!< APB4 clock divided by 16 */
+
+/********************  Bit definition for RCC_PLLCKSELR register  *************/
+
+#define RCC_PLLCKSELR_PLLSRC_Pos               (0U)
+#define RCC_PLLCKSELR_PLLSRC_Msk               (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
+#define RCC_PLLCKSELR_PLLSRC                   RCC_PLLCKSELR_PLLSRC_Msk
+
+#define RCC_PLLCKSELR_PLLSRC_HSI               ((uint32_t)0x00000000)          /*!< HSI source clock selected */
+#define RCC_PLLCKSELR_PLLSRC_CSI_Pos           (0U)
+#define RCC_PLLCKSELR_PLLSRC_CSI_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
+#define RCC_PLLCKSELR_PLLSRC_CSI               RCC_PLLCKSELR_PLLSRC_CSI_Msk    /*!< CSI source clock selected */
+#define RCC_PLLCKSELR_PLLSRC_HSE_Pos           (1U)
+#define RCC_PLLCKSELR_PLLSRC_HSE_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_HSE_Pos) /*!< 0x00000002 */
+#define RCC_PLLCKSELR_PLLSRC_HSE               RCC_PLLCKSELR_PLLSRC_HSE_Msk    /*!< HSE source clock selected */
+#define RCC_PLLCKSELR_PLLSRC_NONE_Pos          (0U)
+#define RCC_PLLCKSELR_PLLSRC_NONE_Msk          (0x3UL << RCC_PLLCKSELR_PLLSRC_NONE_Pos) /*!< 0x00000003 */
+#define RCC_PLLCKSELR_PLLSRC_NONE              RCC_PLLCKSELR_PLLSRC_NONE_Msk   /*!< No source clock selected  */
+
+#define RCC_PLLCKSELR_DIVM1_Pos                (4U)
+#define RCC_PLLCKSELR_DIVM1_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x000003F0 */
+#define RCC_PLLCKSELR_DIVM1                    RCC_PLLCKSELR_DIVM1_Msk
+#define RCC_PLLCKSELR_DIVM1_0                  (0x01UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000010 */
+#define RCC_PLLCKSELR_DIVM1_1                  (0x02UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000020 */
+#define RCC_PLLCKSELR_DIVM1_2                  (0x04UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000040 */
+#define RCC_PLLCKSELR_DIVM1_3                  (0x08UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000080 */
+#define RCC_PLLCKSELR_DIVM1_4                  (0x10UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000100 */
+#define RCC_PLLCKSELR_DIVM1_5                  (0x20UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000200 */
+
+#define RCC_PLLCKSELR_DIVM2_Pos                (12U)
+#define RCC_PLLCKSELR_DIVM2_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x0003F000 */
+#define RCC_PLLCKSELR_DIVM2                    RCC_PLLCKSELR_DIVM2_Msk
+#define RCC_PLLCKSELR_DIVM2_0                  (0x01UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00001000 */
+#define RCC_PLLCKSELR_DIVM2_1                  (0x02UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00002000 */
+#define RCC_PLLCKSELR_DIVM2_2                  (0x04UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00004000 */
+#define RCC_PLLCKSELR_DIVM2_3                  (0x08UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00008000 */
+#define RCC_PLLCKSELR_DIVM2_4                  (0x10UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00010000 */
+#define RCC_PLLCKSELR_DIVM2_5                  (0x20UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00020000 */
+
+#define RCC_PLLCKSELR_DIVM3_Pos                (20U)
+#define RCC_PLLCKSELR_DIVM3_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x03F00000 */
+#define RCC_PLLCKSELR_DIVM3                    RCC_PLLCKSELR_DIVM3_Msk
+#define RCC_PLLCKSELR_DIVM3_0                  (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00100000 */
+#define RCC_PLLCKSELR_DIVM3_1                  (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00200000 */
+#define RCC_PLLCKSELR_DIVM3_2                  (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00400000 */
+#define RCC_PLLCKSELR_DIVM3_3                  (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00800000 */
+#define RCC_PLLCKSELR_DIVM3_4                  (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x01000000 */
+#define RCC_PLLCKSELR_DIVM3_5                  (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 */
+
+/********************  Bit definition for RCC_PLLCFGR register  ***************/
+
+#define RCC_PLLCFGR_PLL1FRACEN_Pos             (0U)
+#define RCC_PLLCFGR_PLL1FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos) /*!< 0x00000001 */
+#define RCC_PLLCFGR_PLL1FRACEN                 RCC_PLLCFGR_PLL1FRACEN_Msk
+#define RCC_PLLCFGR_PLL1VCOSEL_Pos             (1U)
+#define RCC_PLLCFGR_PLL1VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos) /*!< 0x00000002 */
+#define RCC_PLLCFGR_PLL1VCOSEL                 RCC_PLLCFGR_PLL1VCOSEL_Msk
+#define RCC_PLLCFGR_PLL1RGE_Pos                (2U)
+#define RCC_PLLCFGR_PLL1RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
+#define RCC_PLLCFGR_PLL1RGE                    RCC_PLLCFGR_PLL1RGE_Msk
+#define RCC_PLLCFGR_PLL1RGE_0                  (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */
+#define RCC_PLLCFGR_PLL1RGE_1                  (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */
+#define RCC_PLLCFGR_PLL1RGE_2                  (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */
+#define RCC_PLLCFGR_PLL1RGE_3                  (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
+
+#define RCC_PLLCFGR_PLL2FRACEN_Pos             (4U)
+#define RCC_PLLCFGR_PLL2FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos) /*!< 0x00000010 */
+#define RCC_PLLCFGR_PLL2FRACEN                 RCC_PLLCFGR_PLL2FRACEN_Msk
+#define RCC_PLLCFGR_PLL2VCOSEL_Pos             (5U)
+#define RCC_PLLCFGR_PLL2VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos) /*!< 0x00000020 */
+#define RCC_PLLCFGR_PLL2VCOSEL                 RCC_PLLCFGR_PLL2VCOSEL_Msk
+#define RCC_PLLCFGR_PLL2RGE_Pos                (6U)
+#define RCC_PLLCFGR_PLL2RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */
+#define RCC_PLLCFGR_PLL2RGE                    RCC_PLLCFGR_PLL2RGE_Msk
+#define RCC_PLLCFGR_PLL2RGE_0                  (0x0UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000000 */
+#define RCC_PLLCFGR_PLL2RGE_1                  (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000040 */
+#define RCC_PLLCFGR_PLL2RGE_2                  (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000080 */
+#define RCC_PLLCFGR_PLL2RGE_3                  (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */
+
+#define RCC_PLLCFGR_PLL3FRACEN_Pos             (8U)
+#define RCC_PLLCFGR_PLL3FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos) /*!< 0x00000100 */
+#define RCC_PLLCFGR_PLL3FRACEN                 RCC_PLLCFGR_PLL3FRACEN_Msk
+#define RCC_PLLCFGR_PLL3VCOSEL_Pos             (9U)
+#define RCC_PLLCFGR_PLL3VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos) /*!< 0x00000200 */
+#define RCC_PLLCFGR_PLL3VCOSEL                 RCC_PLLCFGR_PLL3VCOSEL_Msk
+#define RCC_PLLCFGR_PLL3RGE_Pos                (10U)
+#define RCC_PLLCFGR_PLL3RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */
+#define RCC_PLLCFGR_PLL3RGE                    RCC_PLLCFGR_PLL3RGE_Msk
+#define RCC_PLLCFGR_PLL3RGE_0                  (0x0UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000000 */
+#define RCC_PLLCFGR_PLL3RGE_1                  (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000400 */
+#define RCC_PLLCFGR_PLL3RGE_2                  (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000800 */
+#define RCC_PLLCFGR_PLL3RGE_3                  (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */
+
+#define RCC_PLLCFGR_DIVP1EN_Pos                (16U)
+#define RCC_PLLCFGR_DIVP1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP1EN_Pos) /*!< 0x00010000 */
+#define RCC_PLLCFGR_DIVP1EN                    RCC_PLLCFGR_DIVP1EN_Msk
+#define RCC_PLLCFGR_DIVQ1EN_Pos                (17U)
+#define RCC_PLLCFGR_DIVQ1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ1EN_Pos) /*!< 0x00020000 */
+#define RCC_PLLCFGR_DIVQ1EN                    RCC_PLLCFGR_DIVQ1EN_Msk
+#define RCC_PLLCFGR_DIVR1EN_Pos                (18U)
+#define RCC_PLLCFGR_DIVR1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR1EN_Pos) /*!< 0x00040000 */
+#define RCC_PLLCFGR_DIVR1EN                    RCC_PLLCFGR_DIVR1EN_Msk
+
+#define RCC_PLLCFGR_DIVP2EN_Pos                (19U)
+#define RCC_PLLCFGR_DIVP2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP2EN_Pos) /*!< 0x00080000 */
+#define RCC_PLLCFGR_DIVP2EN                    RCC_PLLCFGR_DIVP2EN_Msk
+#define RCC_PLLCFGR_DIVQ2EN_Pos                (20U)
+#define RCC_PLLCFGR_DIVQ2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ2EN_Pos) /*!< 0x00100000 */
+#define RCC_PLLCFGR_DIVQ2EN                    RCC_PLLCFGR_DIVQ2EN_Msk
+#define RCC_PLLCFGR_DIVR2EN_Pos                (21U)
+#define RCC_PLLCFGR_DIVR2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR2EN_Pos) /*!< 0x00200000 */
+#define RCC_PLLCFGR_DIVR2EN                    RCC_PLLCFGR_DIVR2EN_Msk
+
+#define RCC_PLLCFGR_DIVP3EN_Pos                (22U)
+#define RCC_PLLCFGR_DIVP3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP3EN_Pos) /*!< 0x00400000 */
+#define RCC_PLLCFGR_DIVP3EN                    RCC_PLLCFGR_DIVP3EN_Msk
+#define RCC_PLLCFGR_DIVQ3EN_Pos                (23U)
+#define RCC_PLLCFGR_DIVQ3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ3EN_Pos) /*!< 0x00800000 */
+#define RCC_PLLCFGR_DIVQ3EN                    RCC_PLLCFGR_DIVQ3EN_Msk
+#define RCC_PLLCFGR_DIVR3EN_Pos                (24U)
+#define RCC_PLLCFGR_DIVR3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR3EN_Pos) /*!< 0x01000000 */
+#define RCC_PLLCFGR_DIVR3EN                    RCC_PLLCFGR_DIVR3EN_Msk
+
+
+/********************  Bit definition for RCC_PLL1DIVR register  ***************/
+#define RCC_PLL1DIVR_N1_Pos                    (0U)
+#define RCC_PLL1DIVR_N1_Msk                    (0x1FFUL << RCC_PLL1DIVR_N1_Pos) /*!< 0x000001FF */
+#define RCC_PLL1DIVR_N1                        RCC_PLL1DIVR_N1_Msk
+#define RCC_PLL1DIVR_P1_Pos                    (9U)
+#define RCC_PLL1DIVR_P1_Msk                    (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */
+#define RCC_PLL1DIVR_P1                        RCC_PLL1DIVR_P1_Msk
+#define RCC_PLL1DIVR_Q1_Pos                    (16U)
+#define RCC_PLL1DIVR_Q1_Msk                    (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */
+#define RCC_PLL1DIVR_Q1                        RCC_PLL1DIVR_Q1_Msk
+#define RCC_PLL1DIVR_R1_Pos                    (24U)
+#define RCC_PLL1DIVR_R1_Msk                    (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
+#define RCC_PLL1DIVR_R1                        RCC_PLL1DIVR_R1_Msk
+
+/********************  Bit definition for RCC_PLL1FRACR register  ***************/
+#define RCC_PLL1FRACR_FRACN1_Pos               (3U)
+#define RCC_PLL1FRACR_FRACN1_Msk               (0x1FFFUL << RCC_PLL1FRACR_FRACN1_Pos) /*!< 0x0000FFF8 */
+#define RCC_PLL1FRACR_FRACN1                   RCC_PLL1FRACR_FRACN1_Msk
+
+/********************  Bit definition for RCC_PLL2DIVR register  ***************/
+#define RCC_PLL2DIVR_N2_Pos                    (0U)
+#define RCC_PLL2DIVR_N2_Msk                    (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */
+#define RCC_PLL2DIVR_N2                        RCC_PLL2DIVR_N2_Msk
+#define RCC_PLL2DIVR_P2_Pos                    (9U)
+#define RCC_PLL2DIVR_P2_Msk                    (0x7FUL << RCC_PLL2DIVR_P2_Pos) /*!< 0x0000FE00 */
+#define RCC_PLL2DIVR_P2                        RCC_PLL2DIVR_P2_Msk
+#define RCC_PLL2DIVR_Q2_Pos                    (16U)
+#define RCC_PLL2DIVR_Q2_Msk                    (0x7FUL << RCC_PLL2DIVR_Q2_Pos) /*!< 0x007F0000 */
+#define RCC_PLL2DIVR_Q2                        RCC_PLL2DIVR_Q2_Msk
+#define RCC_PLL2DIVR_R2_Pos                    (24U)
+#define RCC_PLL2DIVR_R2_Msk                    (0x7FUL << RCC_PLL2DIVR_R2_Pos) /*!< 0x7F000000 */
+#define RCC_PLL2DIVR_R2                        RCC_PLL2DIVR_R2_Msk
+
+/********************  Bit definition for RCC_PLL2FRACR register  ***************/
+#define RCC_PLL2FRACR_FRACN2_Pos               (3U)
+#define RCC_PLL2FRACR_FRACN2_Msk               (0x1FFFUL << RCC_PLL2FRACR_FRACN2_Pos) /*!< 0x0000FFF8 */
+#define RCC_PLL2FRACR_FRACN2                   RCC_PLL2FRACR_FRACN2_Msk
+
+/********************  Bit definition for RCC_PLL3DIVR register  ***************/
+#define RCC_PLL3DIVR_N3_Pos                    (0U)
+#define RCC_PLL3DIVR_N3_Msk                    (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */
+#define RCC_PLL3DIVR_N3                        RCC_PLL3DIVR_N3_Msk
+#define RCC_PLL3DIVR_P3_Pos                    (9U)
+#define RCC_PLL3DIVR_P3_Msk                    (0x7FUL << RCC_PLL3DIVR_P3_Pos) /*!< 0x0000FE00 */
+#define RCC_PLL3DIVR_P3                        RCC_PLL3DIVR_P3_Msk
+#define RCC_PLL3DIVR_Q3_Pos                    (16U)
+#define RCC_PLL3DIVR_Q3_Msk                    (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */
+#define RCC_PLL3DIVR_Q3                        RCC_PLL3DIVR_Q3_Msk
+#define RCC_PLL3DIVR_R3_Pos                    (24U)
+#define RCC_PLL3DIVR_R3_Msk                    (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */
+#define RCC_PLL3DIVR_R3                        RCC_PLL3DIVR_R3_Msk
+
+/********************  Bit definition for RCC_PLL3FRACR register  ***************/
+#define RCC_PLL3FRACR_FRACN3_Pos               (3U)
+#define RCC_PLL3FRACR_FRACN3_Msk               (0x1FFFUL << RCC_PLL3FRACR_FRACN3_Pos) /*!< 0x0000FFF8 */
+#define RCC_PLL3FRACR_FRACN3                   RCC_PLL3FRACR_FRACN3_Msk
+
+/********************  Bit definition for RCC_D1CCIPR register  ***************/
+#define RCC_D1CCIPR_FMCSEL_Pos                 (0U)
+#define RCC_D1CCIPR_FMCSEL_Msk                 (0x3UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000003 */
+#define RCC_D1CCIPR_FMCSEL                     RCC_D1CCIPR_FMCSEL_Msk
+#define RCC_D1CCIPR_FMCSEL_0                   (0x1UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000001 */
+#define RCC_D1CCIPR_FMCSEL_1                   (0x2UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000002 */
+#define RCC_D1CCIPR_QSPISEL_Pos                (4U)
+#define RCC_D1CCIPR_QSPISEL_Msk                (0x3UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000030 */
+#define RCC_D1CCIPR_QSPISEL                    RCC_D1CCIPR_QSPISEL_Msk
+#define RCC_D1CCIPR_QSPISEL_0                  (0x1UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000010 */
+#define RCC_D1CCIPR_QSPISEL_1                  (0x2UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000020 */
+#define RCC_D1CCIPR_SDMMCSEL_Pos               (16U)
+#define RCC_D1CCIPR_SDMMCSEL_Msk               (0x1UL << RCC_D1CCIPR_SDMMCSEL_Pos) /*!< 0x00010000 */
+#define RCC_D1CCIPR_SDMMCSEL                   RCC_D1CCIPR_SDMMCSEL_Msk
+#define RCC_D1CCIPR_CKPERSEL_Pos               (28U)
+#define RCC_D1CCIPR_CKPERSEL_Msk               (0x3UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x30000000 */
+#define RCC_D1CCIPR_CKPERSEL                   RCC_D1CCIPR_CKPERSEL_Msk
+#define RCC_D1CCIPR_CKPERSEL_0                 (0x1UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x10000000 */
+#define RCC_D1CCIPR_CKPERSEL_1                 (0x2UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x20000000 */
+
+/********************  Bit definition for RCC_D2CCIP1R register  ***************/
+#define RCC_D2CCIP1R_SAI1SEL_Pos               (0U)
+#define RCC_D2CCIP1R_SAI1SEL_Msk               (0x7UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000007 */
+#define RCC_D2CCIP1R_SAI1SEL                   RCC_D2CCIP1R_SAI1SEL_Msk
+#define RCC_D2CCIP1R_SAI1SEL_0                 (0x1UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000001 */
+#define RCC_D2CCIP1R_SAI1SEL_1                 (0x2UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000002 */
+#define RCC_D2CCIP1R_SAI1SEL_2                 (0x4UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000004 */
+
+#define RCC_D2CCIP1R_SAI23SEL_Pos              (6U)
+#define RCC_D2CCIP1R_SAI23SEL_Msk              (0x7UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x000001C0 */
+#define RCC_D2CCIP1R_SAI23SEL                  RCC_D2CCIP1R_SAI23SEL_Msk
+#define RCC_D2CCIP1R_SAI23SEL_0                (0x1UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000040 */
+#define RCC_D2CCIP1R_SAI23SEL_1                (0x2UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000080 */
+#define RCC_D2CCIP1R_SAI23SEL_2                (0x4UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000100 */
+
+#define RCC_D2CCIP1R_SPI123SEL_Pos             (12U)
+#define RCC_D2CCIP1R_SPI123SEL_Msk             (0x7UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00007000 */
+#define RCC_D2CCIP1R_SPI123SEL                 RCC_D2CCIP1R_SPI123SEL_Msk
+#define RCC_D2CCIP1R_SPI123SEL_0               (0x1UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00001000 */
+#define RCC_D2CCIP1R_SPI123SEL_1               (0x2UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00002000 */
+#define RCC_D2CCIP1R_SPI123SEL_2               (0x4UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00004000 */
+
+#define RCC_D2CCIP1R_SPI45SEL_Pos              (16U)
+#define RCC_D2CCIP1R_SPI45SEL_Msk              (0x7UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00070000 */
+#define RCC_D2CCIP1R_SPI45SEL                  RCC_D2CCIP1R_SPI45SEL_Msk
+#define RCC_D2CCIP1R_SPI45SEL_0                (0x1UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00010000 */
+#define RCC_D2CCIP1R_SPI45SEL_1                (0x2UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00020000 */
+#define RCC_D2CCIP1R_SPI45SEL_2                (0x4UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00040000 */
+
+#define RCC_D2CCIP1R_SPDIFSEL_Pos              (20U)
+#define RCC_D2CCIP1R_SPDIFSEL_Msk              (0x3UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00300000 */
+#define RCC_D2CCIP1R_SPDIFSEL                  RCC_D2CCIP1R_SPDIFSEL_Msk
+#define RCC_D2CCIP1R_SPDIFSEL_0                (0x1UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00100000 */
+#define RCC_D2CCIP1R_SPDIFSEL_1                (0x2UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00200000 */
+
+#define RCC_D2CCIP1R_DFSDM1SEL_Pos             (24U)
+#define RCC_D2CCIP1R_DFSDM1SEL_Msk             (0x1UL << RCC_D2CCIP1R_DFSDM1SEL_Pos) /*!< 0x01000000 */
+#define RCC_D2CCIP1R_DFSDM1SEL                 RCC_D2CCIP1R_DFSDM1SEL_Msk
+
+#define RCC_D2CCIP1R_FDCANSEL_Pos              (28U)
+#define RCC_D2CCIP1R_FDCANSEL_Msk              (0x3UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x30000000 */
+#define RCC_D2CCIP1R_FDCANSEL                  RCC_D2CCIP1R_FDCANSEL_Msk
+#define RCC_D2CCIP1R_FDCANSEL_0                (0x1UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x10000000 */
+#define RCC_D2CCIP1R_FDCANSEL_1                (0x2UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x20000000 */
+
+#define RCC_D2CCIP1R_SWPSEL_Pos                (31U)
+#define RCC_D2CCIP1R_SWPSEL_Msk                (0x1UL << RCC_D2CCIP1R_SWPSEL_Pos) /*!< 0x80000000 */
+#define RCC_D2CCIP1R_SWPSEL                    RCC_D2CCIP1R_SWPSEL_Msk
+
+/********************  Bit definition for RCC_D2CCIP2R register  ***************/
+#define RCC_D2CCIP2R_USART16SEL_Pos            (3U)
+#define RCC_D2CCIP2R_USART16SEL_Msk            (0x7UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000038 */
+#define RCC_D2CCIP2R_USART16SEL                RCC_D2CCIP2R_USART16SEL_Msk
+#define RCC_D2CCIP2R_USART16SEL_0              (0x1UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000008 */
+#define RCC_D2CCIP2R_USART16SEL_1              (0x2UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000010 */
+#define RCC_D2CCIP2R_USART16SEL_2              (0x4UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000020 */
+
+#define RCC_D2CCIP2R_USART28SEL_Pos            (0U)
+#define RCC_D2CCIP2R_USART28SEL_Msk            (0x7UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000007 */
+#define RCC_D2CCIP2R_USART28SEL                RCC_D2CCIP2R_USART28SEL_Msk
+#define RCC_D2CCIP2R_USART28SEL_0              (0x1UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000001 */
+#define RCC_D2CCIP2R_USART28SEL_1              (0x2UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000002 */
+#define RCC_D2CCIP2R_USART28SEL_2              (0x4UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000004 */
+
+#define RCC_D2CCIP2R_RNGSEL_Pos                (8U)
+#define RCC_D2CCIP2R_RNGSEL_Msk                (0x3UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000300 */
+#define RCC_D2CCIP2R_RNGSEL                    RCC_D2CCIP2R_RNGSEL_Msk
+#define RCC_D2CCIP2R_RNGSEL_0                  (0x1UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000100 */
+#define RCC_D2CCIP2R_RNGSEL_1                  (0x2UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000200 */
+
+#define RCC_D2CCIP2R_I2C123SEL_Pos             (12U)
+#define RCC_D2CCIP2R_I2C123SEL_Msk             (0x3UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00003000 */
+#define RCC_D2CCIP2R_I2C123SEL                 RCC_D2CCIP2R_I2C123SEL_Msk
+#define RCC_D2CCIP2R_I2C123SEL_0               (0x1UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00001000 */
+#define RCC_D2CCIP2R_I2C123SEL_1               (0x2UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00002000 */
+
+#define RCC_D2CCIP2R_USBSEL_Pos                (20U)
+#define RCC_D2CCIP2R_USBSEL_Msk                (0x3UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00300000 */
+#define RCC_D2CCIP2R_USBSEL                    RCC_D2CCIP2R_USBSEL_Msk
+#define RCC_D2CCIP2R_USBSEL_0                  (0x1UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00100000 */
+#define RCC_D2CCIP2R_USBSEL_1                  (0x2UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00200000 */
+
+#define RCC_D2CCIP2R_CECSEL_Pos                (22U)
+#define RCC_D2CCIP2R_CECSEL_Msk                (0x3UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00C00000 */
+#define RCC_D2CCIP2R_CECSEL                    RCC_D2CCIP2R_CECSEL_Msk
+#define RCC_D2CCIP2R_CECSEL_0                  (0x1UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00400000 */
+#define RCC_D2CCIP2R_CECSEL_1                  (0x2UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00800000 */
+
+#define RCC_D2CCIP2R_LPTIM1SEL_Pos             (28U)
+#define RCC_D2CCIP2R_LPTIM1SEL_Msk             (0x7UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x70000000 */
+#define RCC_D2CCIP2R_LPTIM1SEL                 RCC_D2CCIP2R_LPTIM1SEL_Msk
+#define RCC_D2CCIP2R_LPTIM1SEL_0               (0x1UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x10000000 */
+#define RCC_D2CCIP2R_LPTIM1SEL_1               (0x2UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x20000000 */
+#define RCC_D2CCIP2R_LPTIM1SEL_2               (0x4UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for RCC_D3CCIPR register  ***************/
+#define RCC_D3CCIPR_LPUART1SEL_Pos             (0U)
+#define RCC_D3CCIPR_LPUART1SEL_Msk             (0x7UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000007 */
+#define RCC_D3CCIPR_LPUART1SEL                 RCC_D3CCIPR_LPUART1SEL_Msk
+#define RCC_D3CCIPR_LPUART1SEL_0               (0x1UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000001 */
+#define RCC_D3CCIPR_LPUART1SEL_1               (0x2UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000002 */
+#define RCC_D3CCIPR_LPUART1SEL_2               (0x4UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000004 */
+
+#define RCC_D3CCIPR_I2C4SEL_Pos                (8U)
+#define RCC_D3CCIPR_I2C4SEL_Msk                (0x3UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000300 */
+#define RCC_D3CCIPR_I2C4SEL                    RCC_D3CCIPR_I2C4SEL_Msk
+#define RCC_D3CCIPR_I2C4SEL_0                  (0x1UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000100 */
+#define RCC_D3CCIPR_I2C4SEL_1                  (0x2UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000200 */
+
+#define RCC_D3CCIPR_LPTIM2SEL_Pos              (10U)
+#define RCC_D3CCIPR_LPTIM2SEL_Msk              (0x7UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001C00 */
+#define RCC_D3CCIPR_LPTIM2SEL                  RCC_D3CCIPR_LPTIM2SEL_Msk
+#define RCC_D3CCIPR_LPTIM2SEL_0                (0x1UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000400 */
+#define RCC_D3CCIPR_LPTIM2SEL_1                (0x2UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000800 */
+#define RCC_D3CCIPR_LPTIM2SEL_2                (0x4UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001000 */
+
+#define RCC_D3CCIPR_LPTIM345SEL_Pos            (13U)
+#define RCC_D3CCIPR_LPTIM345SEL_Msk            (0x7UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x0000E000 */
+#define RCC_D3CCIPR_LPTIM345SEL                RCC_D3CCIPR_LPTIM345SEL_Msk
+#define RCC_D3CCIPR_LPTIM345SEL_0              (0x1UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00002000 */
+#define RCC_D3CCIPR_LPTIM345SEL_1              (0x2UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00004000 */
+#define RCC_D3CCIPR_LPTIM345SEL_2              (0x4UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00008000 */
+
+#define RCC_D3CCIPR_SAI4ASEL_Pos               (21U)
+#define RCC_D3CCIPR_SAI4ASEL_Msk               (0x7UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00E00000 */
+#define RCC_D3CCIPR_SAI4ASEL                   RCC_D3CCIPR_SAI4ASEL_Msk
+#define RCC_D3CCIPR_SAI4ASEL_0                 (0x1UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00200000 */
+#define RCC_D3CCIPR_SAI4ASEL_1                 (0x2UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00400000 */
+#define RCC_D3CCIPR_SAI4ASEL_2                 (0x4UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00800000 */
+
+#define RCC_D3CCIPR_SAI4BSEL_Pos               (24U)
+#define RCC_D3CCIPR_SAI4BSEL_Msk               (0x7UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x07000000 */
+#define RCC_D3CCIPR_SAI4BSEL                   RCC_D3CCIPR_SAI4BSEL_Msk
+#define RCC_D3CCIPR_SAI4BSEL_0                 (0x1UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x01000000 */
+#define RCC_D3CCIPR_SAI4BSEL_1                 (0x2UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x02000000 */
+#define RCC_D3CCIPR_SAI4BSEL_2                 (0x4UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x04000000 */
+
+#define RCC_D3CCIPR_ADCSEL_Pos                 (16U)
+#define RCC_D3CCIPR_ADCSEL_Msk                 (0x3UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00030000 */
+#define RCC_D3CCIPR_ADCSEL                     RCC_D3CCIPR_ADCSEL_Msk
+#define RCC_D3CCIPR_ADCSEL_0                   (0x1UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00010000 */
+#define RCC_D3CCIPR_ADCSEL_1                   (0x2UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00020000 */
+
+#define RCC_D3CCIPR_SPI6SEL_Pos                (28U)
+#define RCC_D3CCIPR_SPI6SEL_Msk                (0x7UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x70000000 */
+#define RCC_D3CCIPR_SPI6SEL                    RCC_D3CCIPR_SPI6SEL_Msk
+#define RCC_D3CCIPR_SPI6SEL_0                  (0x1UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x10000000 */
+#define RCC_D3CCIPR_SPI6SEL_1                  (0x2UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x20000000 */
+#define RCC_D3CCIPR_SPI6SEL_2                  (0x4UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x40000000 */
+/********************  Bit definition for RCC_CIER register  ******************/
+#define RCC_CIER_LSIRDYIE_Pos                  (0U)
+#define RCC_CIER_LSIRDYIE_Msk                  (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
+#define RCC_CIER_LSIRDYIE                      RCC_CIER_LSIRDYIE_Msk
+#define RCC_CIER_LSERDYIE_Pos                  (1U)
+#define RCC_CIER_LSERDYIE_Msk                  (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
+#define RCC_CIER_LSERDYIE                      RCC_CIER_LSERDYIE_Msk
+#define RCC_CIER_HSIRDYIE_Pos                  (2U)
+#define RCC_CIER_HSIRDYIE_Msk                  (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
+#define RCC_CIER_HSIRDYIE                      RCC_CIER_HSIRDYIE_Msk
+#define RCC_CIER_HSERDYIE_Pos                  (3U)
+#define RCC_CIER_HSERDYIE_Msk                  (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
+#define RCC_CIER_HSERDYIE                      RCC_CIER_HSERDYIE_Msk
+#define RCC_CIER_CSIRDYIE_Pos                  (4U)
+#define RCC_CIER_CSIRDYIE_Msk                  (0x1UL << RCC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */
+#define RCC_CIER_CSIRDYIE                      RCC_CIER_CSIRDYIE_Msk
+#define RCC_CIER_HSI48RDYIE_Pos                (5U)
+#define RCC_CIER_HSI48RDYIE_Msk                (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000020 */
+#define RCC_CIER_HSI48RDYIE                    RCC_CIER_HSI48RDYIE_Msk
+#define RCC_CIER_PLL1RDYIE_Pos                 (6U)
+#define RCC_CIER_PLL1RDYIE_Msk                 (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000040 */
+#define RCC_CIER_PLL1RDYIE                     RCC_CIER_PLL1RDYIE_Msk
+#define RCC_CIER_PLL2RDYIE_Pos                 (7U)
+#define RCC_CIER_PLL2RDYIE_Msk                 (0x1UL << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000080 */
+#define RCC_CIER_PLL2RDYIE                     RCC_CIER_PLL2RDYIE_Msk
+#define RCC_CIER_PLL3RDYIE_Pos                 (8U)
+#define RCC_CIER_PLL3RDYIE_Msk                 (0x1UL << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000100 */
+#define RCC_CIER_PLL3RDYIE                     RCC_CIER_PLL3RDYIE_Msk
+#define RCC_CIER_LSECSSIE_Pos                  (9U)
+#define RCC_CIER_LSECSSIE_Msk                  (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */
+#define RCC_CIER_LSECSSIE                      RCC_CIER_LSECSSIE_Msk
+
+/********************  Bit definition for RCC_CIFR register  ******************/
+#define RCC_CIFR_LSIRDYF_Pos                   (0U)
+#define RCC_CIFR_LSIRDYF_Msk                   (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIFR_LSIRDYF                       RCC_CIFR_LSIRDYF_Msk
+#define RCC_CIFR_LSERDYF_Pos                   (1U)
+#define RCC_CIFR_LSERDYF_Msk                   (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIFR_LSERDYF                       RCC_CIFR_LSERDYF_Msk
+#define RCC_CIFR_HSIRDYF_Pos                   (2U)
+#define RCC_CIFR_HSIRDYF_Msk                   (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIFR_HSIRDYF                       RCC_CIFR_HSIRDYF_Msk
+#define RCC_CIFR_HSERDYF_Pos                   (3U)
+#define RCC_CIFR_HSERDYF_Msk                   (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIFR_HSERDYF                       RCC_CIFR_HSERDYF_Msk
+#define RCC_CIFR_CSIRDYF_Pos                   (4U)
+#define RCC_CIFR_CSIRDYF_Msk                   (0x1UL << RCC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIFR_CSIRDYF                       RCC_CIFR_CSIRDYF_Msk
+#define RCC_CIFR_HSI48RDYF_Pos                 (5U)
+#define RCC_CIFR_HSI48RDYF_Msk                 (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000020 */
+#define RCC_CIFR_HSI48RDYF                     RCC_CIFR_HSI48RDYF_Msk
+#define RCC_CIFR_PLLRDYF_Pos                   (6U)
+#define RCC_CIFR_PLLRDYF_Msk                   (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000040 */
+#define RCC_CIFR_PLLRDYF                       RCC_CIFR_PLLRDYF_Msk
+#define RCC_CIFR_PLL2RDYF_Pos                  (7U)
+#define RCC_CIFR_PLL2RDYF_Msk                  (0x1UL << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000080 */
+#define RCC_CIFR_PLL2RDYF                      RCC_CIFR_PLL2RDYF_Msk
+#define RCC_CIFR_PLL3RDYF_Pos                  (8U)
+#define RCC_CIFR_PLL3RDYF_Msk                  (0x1UL << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000100 */
+#define RCC_CIFR_PLL3RDYF                      RCC_CIFR_PLL3RDYF_Msk
+#define RCC_CIFR_LSECSSF_Pos                   (9U)
+#define RCC_CIFR_LSECSSF_Msk                   (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */
+#define RCC_CIFR_LSECSSF                       RCC_CIFR_LSECSSF_Msk
+#define RCC_CIFR_HSECSSF_Pos                   (10U)
+#define RCC_CIFR_HSECSSF_Msk                   (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */
+#define RCC_CIFR_HSECSSF                       RCC_CIFR_HSECSSF_Msk
+
+/********************  Bit definition for RCC_CICR register  ******************/
+#define RCC_CICR_LSIRDYC_Pos                   (0U)
+#define RCC_CICR_LSIRDYC_Msk                   (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
+#define RCC_CICR_LSIRDYC                       RCC_CICR_LSIRDYC_Msk
+#define RCC_CICR_LSERDYC_Pos                   (1U)
+#define RCC_CICR_LSERDYC_Msk                   (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
+#define RCC_CICR_LSERDYC                       RCC_CICR_LSERDYC_Msk
+#define RCC_CICR_HSIRDYC_Pos                   (2U)
+#define RCC_CICR_HSIRDYC_Msk                   (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */
+#define RCC_CICR_HSIRDYC                       RCC_CICR_HSIRDYC_Msk
+#define RCC_CICR_HSERDYC_Pos                   (3U)
+#define RCC_CICR_HSERDYC_Msk                   (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */
+#define RCC_CICR_HSERDYC                       RCC_CICR_HSERDYC_Msk
+#define RCC_CICR_CSIRDYC_Pos                   (4U)
+#define RCC_CICR_CSIRDYC_Msk                   (0x1UL << RCC_CICR_CSIRDYC_Pos) /*!< 0x00000010 */
+#define RCC_CICR_CSIRDYC                       RCC_CICR_CSIRDYC_Msk
+#define RCC_CICR_HSI48RDYC_Pos                 (5U)
+#define RCC_CICR_HSI48RDYC_Msk                 (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000020 */
+#define RCC_CICR_HSI48RDYC                     RCC_CICR_HSI48RDYC_Msk
+#define RCC_CICR_PLLRDYC_Pos                   (6U)
+#define RCC_CICR_PLLRDYC_Msk                   (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000040 */
+#define RCC_CICR_PLLRDYC                       RCC_CICR_PLLRDYC_Msk
+#define RCC_CICR_PLL2RDYC_Pos                  (7U)
+#define RCC_CICR_PLL2RDYC_Msk                  (0x1UL << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000080 */
+#define RCC_CICR_PLL2RDYC                      RCC_CICR_PLL2RDYC_Msk
+#define RCC_CICR_PLL3RDYC_Pos                  (8U)
+#define RCC_CICR_PLL3RDYC_Msk                  (0x1UL << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000100 */
+#define RCC_CICR_PLL3RDYC                      RCC_CICR_PLL3RDYC_Msk
+#define RCC_CICR_LSECSSC_Pos                   (9U)
+#define RCC_CICR_LSECSSC_Msk                   (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */
+#define RCC_CICR_LSECSSC                       RCC_CICR_LSECSSC_Msk
+#define RCC_CICR_HSECSSC_Pos                   (10U)
+#define RCC_CICR_HSECSSC_Msk                   (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */
+#define RCC_CICR_HSECSSC                       RCC_CICR_HSECSSC_Msk
+
+/********************  Bit definition for RCC_BDCR register  ******************/
+#define RCC_BDCR_LSEON_Pos                     (0U)
+#define RCC_BDCR_LSEON_Msk                     (0x1UL << RCC_BDCR_LSEON_Pos)   /*!< 0x00000001 */
+#define RCC_BDCR_LSEON                         RCC_BDCR_LSEON_Msk
+#define RCC_BDCR_LSERDY_Pos                    (1U)
+#define RCC_BDCR_LSERDY_Msk                    (0x1UL << RCC_BDCR_LSERDY_Pos)  /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY                        RCC_BDCR_LSERDY_Msk
+#define RCC_BDCR_LSEBYP_Pos                    (2U)
+#define RCC_BDCR_LSEBYP_Msk                    (0x1UL << RCC_BDCR_LSEBYP_Pos)  /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP                        RCC_BDCR_LSEBYP_Msk
+
+#define RCC_BDCR_LSEDRV_Pos                    (3U)
+#define RCC_BDCR_LSEDRV_Msk                    (0x3UL << RCC_BDCR_LSEDRV_Pos)  /*!< 0x00000018 */
+#define RCC_BDCR_LSEDRV                        RCC_BDCR_LSEDRV_Msk
+#define RCC_BDCR_LSEDRV_0                      (0x1UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000008 */
+#define RCC_BDCR_LSEDRV_1                      (0x2UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000010 */
+
+#define RCC_BDCR_LSECSSON_Pos                  (5U)
+#define RCC_BDCR_LSECSSON_Msk                  (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */
+#define RCC_BDCR_LSECSSON                      RCC_BDCR_LSECSSON_Msk
+#define RCC_BDCR_LSECSSD_Pos                   (6U)
+#define RCC_BDCR_LSECSSD_Msk                   (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */
+#define RCC_BDCR_LSECSSD                       RCC_BDCR_LSECSSD_Msk
+
+#define RCC_BDCR_RTCSEL_Pos                    (8U)
+#define RCC_BDCR_RTCSEL_Msk                    (0x3UL << RCC_BDCR_RTCSEL_Pos)  /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL                        RCC_BDCR_RTCSEL_Msk
+#define RCC_BDCR_RTCSEL_0                      (0x1UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1                      (0x2UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000200 */
+
+#define RCC_BDCR_RTCEN_Pos                     (15U)
+#define RCC_BDCR_RTCEN_Msk                     (0x1UL << RCC_BDCR_RTCEN_Pos)   /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN                         RCC_BDCR_RTCEN_Msk
+#define RCC_BDCR_BDRST_Pos                     (16U)
+#define RCC_BDCR_BDRST_Msk                     (0x1UL << RCC_BDCR_BDRST_Pos)   /*!< 0x00010000 */
+#define RCC_BDCR_BDRST                         RCC_BDCR_BDRST_Msk
+/********************  Bit definition for RCC_CSR register  *******************/
+#define RCC_CSR_LSION_Pos                      (0U)
+#define RCC_CSR_LSION_Msk                      (0x1UL << RCC_CSR_LSION_Pos)    /*!< 0x00000001 */
+#define RCC_CSR_LSION                          RCC_CSR_LSION_Msk
+#define RCC_CSR_LSIRDY_Pos                     (1U)
+#define RCC_CSR_LSIRDY_Msk                     (0x1UL << RCC_CSR_LSIRDY_Pos)   /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY                         RCC_CSR_LSIRDY_Msk
+
+
+/********************  Bit definition for RCC_AHB3ENR register  **************/
+#define RCC_AHB3ENR_MDMAEN_Pos                 (0U)
+#define RCC_AHB3ENR_MDMAEN_Msk                 (0x1UL << RCC_AHB3ENR_MDMAEN_Pos)       /*!< 0x00000001 */
+#define RCC_AHB3ENR_MDMAEN                     RCC_AHB3ENR_MDMAEN_Msk
+#define RCC_AHB3ENR_DMA2DEN_Pos                (4U)
+#define RCC_AHB3ENR_DMA2DEN_Msk                (0x1UL << RCC_AHB3ENR_DMA2DEN_Pos)      /*!< 0x00000010 */
+#define RCC_AHB3ENR_DMA2DEN                    RCC_AHB3ENR_DMA2DEN_Msk
+#define RCC_AHB3ENR_JPGDECEN_Pos               (5U)
+#define RCC_AHB3ENR_JPGDECEN_Msk               (0x1UL << RCC_AHB3ENR_JPGDECEN_Pos)     /*!< 0x00000020 */
+#define RCC_AHB3ENR_JPGDECEN                   RCC_AHB3ENR_JPGDECEN_Msk
+#define RCC_AHB3ENR_FMCEN_Pos                  (12U)
+#define RCC_AHB3ENR_FMCEN_Msk                  (0x1UL << RCC_AHB3ENR_FMCEN_Pos)        /*!< 0x00001000 */
+#define RCC_AHB3ENR_FMCEN                      RCC_AHB3ENR_FMCEN_Msk
+#define RCC_AHB3ENR_QSPIEN_Pos                 (14U)
+#define RCC_AHB3ENR_QSPIEN_Msk                 (0x1UL << RCC_AHB3ENR_QSPIEN_Pos)       /*!< 0x00004000 */
+#define RCC_AHB3ENR_QSPIEN                     RCC_AHB3ENR_QSPIEN_Msk
+#define RCC_AHB3ENR_SDMMC1EN_Pos               (16U)
+#define RCC_AHB3ENR_SDMMC1EN_Msk               (0x1UL << RCC_AHB3ENR_SDMMC1EN_Pos)     /*!< 0x00010000 */
+#define RCC_AHB3ENR_SDMMC1EN                   RCC_AHB3ENR_SDMMC1EN_Msk
+
+/********************  Bit definition for RCC_AHB1ENR register  ***************/
+#define RCC_AHB1ENR_DMA1EN_Pos                 (0U)
+#define RCC_AHB1ENR_DMA1EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)          /*!< 0x00000001 */
+#define RCC_AHB1ENR_DMA1EN                     RCC_AHB1ENR_DMA1EN_Msk
+#define RCC_AHB1ENR_DMA2EN_Pos                 (1U)
+#define RCC_AHB1ENR_DMA2EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)          /*!< 0x00000002 */
+#define RCC_AHB1ENR_DMA2EN                     RCC_AHB1ENR_DMA2EN_Msk
+#define RCC_AHB1ENR_ADC12EN_Pos                (5U)
+#define RCC_AHB1ENR_ADC12EN_Msk                (0x1UL << RCC_AHB1ENR_ADC12EN_Pos)         /*!< 0x00000020 */
+#define RCC_AHB1ENR_ADC12EN                    RCC_AHB1ENR_ADC12EN_Msk
+#define RCC_AHB1ENR_ETH1MACEN_Pos              (15U)
+#define RCC_AHB1ENR_ETH1MACEN_Msk              (0x1UL << RCC_AHB1ENR_ETH1MACEN_Pos)       /*!< 0x00008000 */
+#define RCC_AHB1ENR_ETH1MACEN                  RCC_AHB1ENR_ETH1MACEN_Msk
+#define RCC_AHB1ENR_ETH1TXEN_Pos               (16U)
+#define RCC_AHB1ENR_ETH1TXEN_Msk               (0x1UL << RCC_AHB1ENR_ETH1TXEN_Pos)        /*!< 0x00010000 */
+#define RCC_AHB1ENR_ETH1TXEN                   RCC_AHB1ENR_ETH1TXEN_Msk
+#define RCC_AHB1ENR_ETH1RXEN_Pos               (17U)
+#define RCC_AHB1ENR_ETH1RXEN_Msk               (0x1UL << RCC_AHB1ENR_ETH1RXEN_Pos)        /*!< 0x00020000 */
+#define RCC_AHB1ENR_ETH1RXEN                   RCC_AHB1ENR_ETH1RXEN_Msk
+#define RCC_AHB1ENR_USB1OTGHSEN_Pos            (25U)
+#define RCC_AHB1ENR_USB1OTGHSEN_Msk            (0x1UL << RCC_AHB1ENR_USB1OTGHSEN_Pos)     /*!< 0x02000000 */
+#define RCC_AHB1ENR_USB1OTGHSEN                RCC_AHB1ENR_USB1OTGHSEN_Msk
+#define RCC_AHB1ENR_USB1OTGHSULPIEN_Pos        (26U)
+#define RCC_AHB1ENR_USB1OTGHSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_USB1OTGHSULPIEN_Pos) /*!< 0x04000000 */
+#define RCC_AHB1ENR_USB1OTGHSULPIEN            RCC_AHB1ENR_USB1OTGHSULPIEN_Msk
+#define RCC_AHB1ENR_USB2OTGFSEN_Pos            (27U)
+#define RCC_AHB1ENR_USB2OTGFSEN_Msk            (0x1UL << RCC_AHB1ENR_USB2OTGFSEN_Pos)     /*!< 0x08000000 */
+#define RCC_AHB1ENR_USB2OTGFSEN                RCC_AHB1ENR_USB2OTGFSEN_Msk
+#define RCC_AHB1ENR_USB2OTGFSULPIEN_Pos        (28U)
+#define RCC_AHB1ENR_USB2OTGFSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_USB2OTGFSULPIEN_Pos) /*!< 0x10000000 */
+#define RCC_AHB1ENR_USB2OTGFSULPIEN            RCC_AHB1ENR_USB2OTGFSULPIEN_Msk
+
+/* Legacy define */
+#define RCC_AHB1ENR_USB2OTGHSEN_Pos            RCC_AHB1ENR_USB2OTGFSEN_Pos
+#define RCC_AHB1ENR_USB2OTGHSEN_Msk            RCC_AHB1ENR_USB2OTGFSEN_Msk
+#define RCC_AHB1ENR_USB2OTGHSEN                RCC_AHB1ENR_USB2OTGFSEN
+#define RCC_AHB1ENR_USB2OTGHSULPIEN_Pos        RCC_AHB1ENR_USB2OTGFSULPIEN_Pos
+#define RCC_AHB1ENR_USB2OTGHSULPIEN_Msk        RCC_AHB1ENR_USB2OTGFSULPIEN_Msk
+#define RCC_AHB1ENR_USB2OTGHSULPIEN            RCC_AHB1ENR_USB2OTGFSULPIEN
+
+
+/********************  Bit definition for RCC_AHB2ENR register  ***************/
+#define RCC_AHB2ENR_DCMIEN_Pos                 (0U)
+#define RCC_AHB2ENR_DCMIEN_Msk                 (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)          /*!< 0x00000001 */
+#define RCC_AHB2ENR_DCMIEN                     RCC_AHB2ENR_DCMIEN_Msk
+#define RCC_AHB2ENR_RNGEN_Pos                  (6U)
+#define RCC_AHB2ENR_RNGEN_Msk                  (0x1UL << RCC_AHB2ENR_RNGEN_Pos)           /*!< 0x00000040 */
+#define RCC_AHB2ENR_RNGEN                      RCC_AHB2ENR_RNGEN_Msk
+#define RCC_AHB2ENR_SDMMC2EN_Pos               (9U)
+#define RCC_AHB2ENR_SDMMC2EN_Msk               (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos)        /*!< 0x00000200 */
+#define RCC_AHB2ENR_SDMMC2EN                   RCC_AHB2ENR_SDMMC2EN_Msk
+#define RCC_AHB2ENR_SRAM1EN_Pos                (29U)
+#define RCC_AHB2ENR_SRAM1EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM1EN_Pos)       /*!< 0x20000000 */
+#define RCC_AHB2ENR_SRAM1EN                    RCC_AHB2ENR_SRAM1EN_Msk
+#define RCC_AHB2ENR_SRAM2EN_Pos                (30U)
+#define RCC_AHB2ENR_SRAM2EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos)       /*!< 0x40000000 */
+#define RCC_AHB2ENR_SRAM2EN                    RCC_AHB2ENR_SRAM2EN_Msk
+#define RCC_AHB2ENR_SRAM3EN_Pos                (31U)
+#define RCC_AHB2ENR_SRAM3EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM3EN_Pos)       /*!< 0x80000000 */
+#define RCC_AHB2ENR_SRAM3EN                    RCC_AHB2ENR_SRAM3EN_Msk
+
+/* Legacy define */
+#define RCC_AHB2ENR_D2SRAM1EN_Pos              RCC_AHB2ENR_SRAM1EN_Pos
+#define RCC_AHB2ENR_D2SRAM1EN_Msk              RCC_AHB2ENR_SRAM1EN_Msk
+#define RCC_AHB2ENR_D2SRAM1EN                  RCC_AHB2ENR_SRAM1EN
+#define RCC_AHB2ENR_D2SRAM2EN_Pos              RCC_AHB2ENR_SRAM2EN_Pos
+#define RCC_AHB2ENR_D2SRAM2EN_Msk              RCC_AHB2ENR_SRAM2EN_Msk
+#define RCC_AHB2ENR_D2SRAM2EN                  RCC_AHB2ENR_SRAM2EN
+#define RCC_AHB2ENR_D2SRAM3EN_Pos              RCC_AHB2ENR_SRAM3EN_Pos
+#define RCC_AHB2ENR_D2SRAM3EN_Msk              RCC_AHB2ENR_SRAM3EN_Msk
+#define RCC_AHB2ENR_D2SRAM3EN                  RCC_AHB2ENR_SRAM3EN
+
+/********************  Bit definition for RCC_AHB4ENR register  ******************/
+#define RCC_AHB4ENR_GPIOAEN_Pos                (0U)
+#define RCC_AHB4ENR_GPIOAEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos)         /*!< 0x00000001 */
+#define RCC_AHB4ENR_GPIOAEN                    RCC_AHB4ENR_GPIOAEN_Msk
+#define RCC_AHB4ENR_GPIOBEN_Pos                (1U)
+#define RCC_AHB4ENR_GPIOBEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos)         /*!< 0x00000002 */
+#define RCC_AHB4ENR_GPIOBEN                    RCC_AHB4ENR_GPIOBEN_Msk
+#define RCC_AHB4ENR_GPIOCEN_Pos                (2U)
+#define RCC_AHB4ENR_GPIOCEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos)         /*!< 0x00000004 */
+#define RCC_AHB4ENR_GPIOCEN                    RCC_AHB4ENR_GPIOCEN_Msk
+#define RCC_AHB4ENR_GPIODEN_Pos                (3U)
+#define RCC_AHB4ENR_GPIODEN_Msk                (0x1UL << RCC_AHB4ENR_GPIODEN_Pos)         /*!< 0x00000008 */
+#define RCC_AHB4ENR_GPIODEN                    RCC_AHB4ENR_GPIODEN_Msk
+#define RCC_AHB4ENR_GPIOEEN_Pos                (4U)
+#define RCC_AHB4ENR_GPIOEEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos)         /*!< 0x00000010 */
+#define RCC_AHB4ENR_GPIOEEN                    RCC_AHB4ENR_GPIOEEN_Msk
+#define RCC_AHB4ENR_GPIOFEN_Pos                (5U)
+#define RCC_AHB4ENR_GPIOFEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos)         /*!< 0x00000020 */
+#define RCC_AHB4ENR_GPIOFEN                    RCC_AHB4ENR_GPIOFEN_Msk
+#define RCC_AHB4ENR_GPIOGEN_Pos                (6U)
+#define RCC_AHB4ENR_GPIOGEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos)         /*!< 0x00000040 */
+#define RCC_AHB4ENR_GPIOGEN                    RCC_AHB4ENR_GPIOGEN_Msk
+#define RCC_AHB4ENR_GPIOHEN_Pos                (7U)
+#define RCC_AHB4ENR_GPIOHEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos)         /*!< 0x00000080 */
+#define RCC_AHB4ENR_GPIOHEN                    RCC_AHB4ENR_GPIOHEN_Msk
+#define RCC_AHB4ENR_GPIOIEN_Pos                (8U)
+#define RCC_AHB4ENR_GPIOIEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOIEN_Pos)         /*!< 0x00000100 */
+#define RCC_AHB4ENR_GPIOIEN                    RCC_AHB4ENR_GPIOIEN_Msk
+#define RCC_AHB4ENR_GPIOJEN_Pos                (9U)
+#define RCC_AHB4ENR_GPIOJEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOJEN_Pos)         /*!< 0x00000200 */
+#define RCC_AHB4ENR_GPIOJEN                    RCC_AHB4ENR_GPIOJEN_Msk
+#define RCC_AHB4ENR_GPIOKEN_Pos                (10U)
+#define RCC_AHB4ENR_GPIOKEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOKEN_Pos)         /*!< 0x00000400 */
+#define RCC_AHB4ENR_GPIOKEN                    RCC_AHB4ENR_GPIOKEN_Msk
+#define RCC_AHB4ENR_CRCEN_Pos                  (19U)
+#define RCC_AHB4ENR_CRCEN_Msk                  (0x1UL << RCC_AHB4ENR_CRCEN_Pos)           /*!< 0x00080000 */
+#define RCC_AHB4ENR_CRCEN                      RCC_AHB4ENR_CRCEN_Msk
+#define RCC_AHB4ENR_BDMAEN_Pos                 (21U)
+#define RCC_AHB4ENR_BDMAEN_Msk                 (0x1UL << RCC_AHB4ENR_BDMAEN_Pos)          /*!< 0x00200000 */
+#define RCC_AHB4ENR_BDMAEN                     RCC_AHB4ENR_BDMAEN_Msk
+#define RCC_AHB4ENR_ADC3EN_Pos                 (24U)
+#define RCC_AHB4ENR_ADC3EN_Msk                 (0x1UL << RCC_AHB4ENR_ADC3EN_Pos)          /*!< 0x01000000 */
+#define RCC_AHB4ENR_ADC3EN                     RCC_AHB4ENR_ADC3EN_Msk
+#define RCC_AHB4ENR_HSEMEN_Pos                 (25U)
+#define RCC_AHB4ENR_HSEMEN_Msk                 (0x1UL << RCC_AHB4ENR_HSEMEN_Pos)          /*!< 0x02000000 */
+#define RCC_AHB4ENR_HSEMEN                     RCC_AHB4ENR_HSEMEN_Msk
+#define RCC_AHB4ENR_BKPRAMEN_Pos               (28U)
+#define RCC_AHB4ENR_BKPRAMEN_Msk               (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos)        /*!< 0x10000000 */
+#define RCC_AHB4ENR_BKPRAMEN                   RCC_AHB4ENR_BKPRAMEN_Msk
+
+/********************  Bit definition for RCC_APB3ENR register  ******************/
+#define RCC_APB3ENR_LTDCEN_Pos                 (3U)
+#define RCC_APB3ENR_LTDCEN_Msk                 (0x1UL << RCC_APB3ENR_LTDCEN_Pos) /*!< 0x00000008 */
+#define RCC_APB3ENR_LTDCEN                     RCC_APB3ENR_LTDCEN_Msk
+#define RCC_APB3ENR_WWDG1EN_Pos                (6U)
+#define RCC_APB3ENR_WWDG1EN_Msk                (0x1UL << RCC_APB3ENR_WWDG1EN_Pos) /*!< 0x00000040 */
+#define RCC_APB3ENR_WWDG1EN                    RCC_APB3ENR_WWDG1EN_Msk
+
+/********************  Bit definition for RCC_APB1LENR register  ******************/
+
+#define RCC_APB1LENR_TIM2EN_Pos                (0U)
+#define RCC_APB1LENR_TIM2EN_Msk                (0x1UL << RCC_APB1LENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1LENR_TIM2EN                    RCC_APB1LENR_TIM2EN_Msk
+#define RCC_APB1LENR_TIM3EN_Pos                (1U)
+#define RCC_APB1LENR_TIM3EN_Msk                (0x1UL << RCC_APB1LENR_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1LENR_TIM3EN                    RCC_APB1LENR_TIM3EN_Msk
+#define RCC_APB1LENR_TIM4EN_Pos                (2U)
+#define RCC_APB1LENR_TIM4EN_Msk                (0x1UL << RCC_APB1LENR_TIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1LENR_TIM4EN                    RCC_APB1LENR_TIM4EN_Msk
+#define RCC_APB1LENR_TIM5EN_Pos                (3U)
+#define RCC_APB1LENR_TIM5EN_Msk                (0x1UL << RCC_APB1LENR_TIM5EN_Pos) /*!< 0x00000008 */
+#define RCC_APB1LENR_TIM5EN                    RCC_APB1LENR_TIM5EN_Msk
+#define RCC_APB1LENR_TIM6EN_Pos                (4U)
+#define RCC_APB1LENR_TIM6EN_Msk                (0x1UL << RCC_APB1LENR_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_APB1LENR_TIM6EN                    RCC_APB1LENR_TIM6EN_Msk
+#define RCC_APB1LENR_TIM7EN_Pos                (5U)
+#define RCC_APB1LENR_TIM7EN_Msk                (0x1UL << RCC_APB1LENR_TIM7EN_Pos) /*!< 0x00000020 */
+#define RCC_APB1LENR_TIM7EN                    RCC_APB1LENR_TIM7EN_Msk
+#define RCC_APB1LENR_TIM12EN_Pos               (6U)
+#define RCC_APB1LENR_TIM12EN_Msk               (0x1UL << RCC_APB1LENR_TIM12EN_Pos) /*!< 0x00000040 */
+#define RCC_APB1LENR_TIM12EN                   RCC_APB1LENR_TIM12EN_Msk
+#define RCC_APB1LENR_TIM13EN_Pos               (7U)
+#define RCC_APB1LENR_TIM13EN_Msk               (0x1UL << RCC_APB1LENR_TIM13EN_Pos) /*!< 0x00000080 */
+#define RCC_APB1LENR_TIM13EN                   RCC_APB1LENR_TIM13EN_Msk
+#define RCC_APB1LENR_TIM14EN_Pos               (8U)
+#define RCC_APB1LENR_TIM14EN_Msk               (0x1UL << RCC_APB1LENR_TIM14EN_Pos) /*!< 0x00000100 */
+#define RCC_APB1LENR_TIM14EN                   RCC_APB1LENR_TIM14EN_Msk
+#define RCC_APB1LENR_LPTIM1EN_Pos              (9U)
+#define RCC_APB1LENR_LPTIM1EN_Msk              (0x1UL << RCC_APB1LENR_LPTIM1EN_Pos) /*!< 0x00000200 */
+#define RCC_APB1LENR_LPTIM1EN                  RCC_APB1LENR_LPTIM1EN_Msk
+
+
+#define RCC_APB1LENR_SPI2EN_Pos                (14U)
+#define RCC_APB1LENR_SPI2EN_Msk                (0x1UL << RCC_APB1LENR_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1LENR_SPI2EN                    RCC_APB1LENR_SPI2EN_Msk
+#define RCC_APB1LENR_SPI3EN_Pos                (15U)
+#define RCC_APB1LENR_SPI3EN_Msk                (0x1UL << RCC_APB1LENR_SPI3EN_Pos) /*!< 0x00008000 */
+#define RCC_APB1LENR_SPI3EN                    RCC_APB1LENR_SPI3EN_Msk
+#define RCC_APB1LENR_SPDIFRXEN_Pos             (16U)
+#define RCC_APB1LENR_SPDIFRXEN_Msk             (0x1UL << RCC_APB1LENR_SPDIFRXEN_Pos) /*!< 0x00010000 */
+#define RCC_APB1LENR_SPDIFRXEN                 RCC_APB1LENR_SPDIFRXEN_Msk
+#define RCC_APB1LENR_USART2EN_Pos              (17U)
+#define RCC_APB1LENR_USART2EN_Msk              (0x1UL << RCC_APB1LENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1LENR_USART2EN                  RCC_APB1LENR_USART2EN_Msk
+#define RCC_APB1LENR_USART3EN_Pos              (18U)
+#define RCC_APB1LENR_USART3EN_Msk              (0x1UL << RCC_APB1LENR_USART3EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1LENR_USART3EN                  RCC_APB1LENR_USART3EN_Msk
+#define RCC_APB1LENR_UART4EN_Pos               (19U)
+#define RCC_APB1LENR_UART4EN_Msk               (0x1UL << RCC_APB1LENR_UART4EN_Pos) /*!< 0x00080000 */
+#define RCC_APB1LENR_UART4EN                   RCC_APB1LENR_UART4EN_Msk
+#define RCC_APB1LENR_UART5EN_Pos               (20U)
+#define RCC_APB1LENR_UART5EN_Msk               (0x1UL << RCC_APB1LENR_UART5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB1LENR_UART5EN                   RCC_APB1LENR_UART5EN_Msk
+#define RCC_APB1LENR_I2C1EN_Pos                (21U)
+#define RCC_APB1LENR_I2C1EN_Msk                (0x1UL << RCC_APB1LENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1LENR_I2C1EN                    RCC_APB1LENR_I2C1EN_Msk
+#define RCC_APB1LENR_I2C2EN_Pos                (22U)
+#define RCC_APB1LENR_I2C2EN_Msk                (0x1UL << RCC_APB1LENR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1LENR_I2C2EN                    RCC_APB1LENR_I2C2EN_Msk
+#define RCC_APB1LENR_I2C3EN_Pos                (23U)
+#define RCC_APB1LENR_I2C3EN_Msk                (0x1UL << RCC_APB1LENR_I2C3EN_Pos) /*!< 0x00800000 */
+#define RCC_APB1LENR_I2C3EN                    RCC_APB1LENR_I2C3EN_Msk
+#define RCC_APB1LENR_CECEN_Pos                 (27U)
+#define RCC_APB1LENR_CECEN_Msk                 (0x1UL << RCC_APB1LENR_CECEN_Pos) /*!< 0x08000000 */
+#define RCC_APB1LENR_CECEN                     RCC_APB1LENR_CECEN_Msk
+#define RCC_APB1LENR_DAC12EN_Pos               (29U)
+#define RCC_APB1LENR_DAC12EN_Msk               (0x1UL << RCC_APB1LENR_DAC12EN_Pos) /*!< 0x20000000 */
+#define RCC_APB1LENR_DAC12EN                   RCC_APB1LENR_DAC12EN_Msk
+#define RCC_APB1LENR_UART7EN_Pos               (30U)
+#define RCC_APB1LENR_UART7EN_Msk               (0x1UL << RCC_APB1LENR_UART7EN_Pos) /*!< 0x40000000 */
+#define RCC_APB1LENR_UART7EN                   RCC_APB1LENR_UART7EN_Msk
+#define RCC_APB1LENR_UART8EN_Pos               (31U)
+#define RCC_APB1LENR_UART8EN_Msk               (0x1UL << RCC_APB1LENR_UART8EN_Pos) /*!< 0x80000000 */
+#define RCC_APB1LENR_UART8EN                   RCC_APB1LENR_UART8EN_Msk
+
+/* Legacy define */
+#define RCC_APB1LENR_HDMICECEN_Pos             RCC_APB1LENR_CECEN_Pos
+#define RCC_APB1LENR_HDMICECEN_Msk             RCC_APB1LENR_CECEN_Msk
+#define RCC_APB1LENR_HDMICECEN                 RCC_APB1LENR_CECEN
+/********************  Bit definition for RCC_APB1HENR register  ******************/
+#define RCC_APB1HENR_CRSEN_Pos                 (1U)
+#define RCC_APB1HENR_CRSEN_Msk                 (0x1UL << RCC_APB1HENR_CRSEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1HENR_CRSEN                     RCC_APB1HENR_CRSEN_Msk
+#define RCC_APB1HENR_SWPMIEN_Pos               (2U)
+#define RCC_APB1HENR_SWPMIEN_Msk               (0x1UL << RCC_APB1HENR_SWPMIEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1HENR_SWPMIEN                   RCC_APB1HENR_SWPMIEN_Msk
+#define RCC_APB1HENR_OPAMPEN_Pos               (4U)
+#define RCC_APB1HENR_OPAMPEN_Msk               (0x1UL << RCC_APB1HENR_OPAMPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1HENR_OPAMPEN                   RCC_APB1HENR_OPAMPEN_Msk
+#define RCC_APB1HENR_MDIOSEN_Pos               (5U)
+#define RCC_APB1HENR_MDIOSEN_Msk               (0x1UL << RCC_APB1HENR_MDIOSEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1HENR_MDIOSEN                   RCC_APB1HENR_MDIOSEN_Msk
+#define RCC_APB1HENR_FDCANEN_Pos               (8U)
+#define RCC_APB1HENR_FDCANEN_Msk               (0x1UL << RCC_APB1HENR_FDCANEN_Pos) /*!< 0x00000100 */
+#define RCC_APB1HENR_FDCANEN                   RCC_APB1HENR_FDCANEN_Msk
+
+/********************  Bit definition for RCC_APB2ENR register  ******************/
+#define RCC_APB2ENR_TIM1EN_Pos                 (0U)
+#define RCC_APB2ENR_TIM1EN_Msk                 (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_TIM1EN                     RCC_APB2ENR_TIM1EN_Msk
+#define RCC_APB2ENR_TIM8EN_Pos                 (1U)
+#define RCC_APB2ENR_TIM8EN_Msk                 (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
+#define RCC_APB2ENR_TIM8EN                     RCC_APB2ENR_TIM8EN_Msk
+#define RCC_APB2ENR_USART1EN_Pos               (4U)
+#define RCC_APB2ENR_USART1EN_Msk               (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
+#define RCC_APB2ENR_USART1EN                   RCC_APB2ENR_USART1EN_Msk
+#define RCC_APB2ENR_USART6EN_Pos               (5U)
+#define RCC_APB2ENR_USART6EN_Msk               (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_USART6EN                   RCC_APB2ENR_USART6EN_Msk
+#define RCC_APB2ENR_SPI1EN_Pos                 (12U)
+#define RCC_APB2ENR_SPI1EN_Msk                 (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN                     RCC_APB2ENR_SPI1EN_Msk
+#define RCC_APB2ENR_SPI4EN_Pos                 (13U)
+#define RCC_APB2ENR_SPI4EN_Msk                 (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
+#define RCC_APB2ENR_SPI4EN                     RCC_APB2ENR_SPI4EN_Msk
+#define RCC_APB2ENR_TIM15EN_Pos                (16U)
+#define RCC_APB2ENR_TIM15EN_Msk                (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
+#define RCC_APB2ENR_TIM15EN                    RCC_APB2ENR_TIM15EN_Msk
+#define RCC_APB2ENR_TIM16EN_Pos                (17U)
+#define RCC_APB2ENR_TIM16EN_Msk                (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
+#define RCC_APB2ENR_TIM16EN                    RCC_APB2ENR_TIM16EN_Msk
+#define RCC_APB2ENR_TIM17EN_Pos                (18U)
+#define RCC_APB2ENR_TIM17EN_Msk                (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
+#define RCC_APB2ENR_TIM17EN                    RCC_APB2ENR_TIM17EN_Msk
+#define RCC_APB2ENR_SPI5EN_Pos                 (20U)
+#define RCC_APB2ENR_SPI5EN_Msk                 (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB2ENR_SPI5EN                     RCC_APB2ENR_SPI5EN_Msk
+#define RCC_APB2ENR_SAI1EN_Pos                 (22U)
+#define RCC_APB2ENR_SAI1EN_Msk                 (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */
+#define RCC_APB2ENR_SAI1EN                     RCC_APB2ENR_SAI1EN_Msk
+#define RCC_APB2ENR_SAI2EN_Pos                 (23U)
+#define RCC_APB2ENR_SAI2EN_Msk                 (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */
+#define RCC_APB2ENR_SAI2EN                     RCC_APB2ENR_SAI2EN_Msk
+#define RCC_APB2ENR_SAI3EN_Pos                 (24U)
+#define RCC_APB2ENR_SAI3EN_Msk                 (0x1UL << RCC_APB2ENR_SAI3EN_Pos) /*!< 0x01000000 */
+#define RCC_APB2ENR_SAI3EN                     RCC_APB2ENR_SAI3EN_Msk
+#define RCC_APB2ENR_DFSDM1EN_Pos               (28U)
+#define RCC_APB2ENR_DFSDM1EN_Msk               (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x10000000 */
+#define RCC_APB2ENR_DFSDM1EN                   RCC_APB2ENR_DFSDM1EN_Msk
+#define RCC_APB2ENR_HRTIMEN_Pos                (29U)
+#define RCC_APB2ENR_HRTIMEN_Msk                (0x1UL << RCC_APB2ENR_HRTIMEN_Pos) /*!< 0x20000000 */
+#define RCC_APB2ENR_HRTIMEN                    RCC_APB2ENR_HRTIMEN_Msk
+
+/********************  Bit definition for RCC_APB4ENR register  ******************/
+#define RCC_APB4ENR_SYSCFGEN_Pos               (1U)
+#define RCC_APB4ENR_SYSCFGEN_Msk               (0x1UL << RCC_APB4ENR_SYSCFGEN_Pos) /*!< 0x00000002 */
+#define RCC_APB4ENR_SYSCFGEN                   RCC_APB4ENR_SYSCFGEN_Msk
+#define RCC_APB4ENR_LPUART1EN_Pos              (3U)
+#define RCC_APB4ENR_LPUART1EN_Msk              (0x1UL << RCC_APB4ENR_LPUART1EN_Pos) /*!< 0x00000008 */
+#define RCC_APB4ENR_LPUART1EN                  RCC_APB4ENR_LPUART1EN_Msk
+#define RCC_APB4ENR_SPI6EN_Pos                 (5U)
+#define RCC_APB4ENR_SPI6EN_Msk                 (0x1UL << RCC_APB4ENR_SPI6EN_Pos) /*!< 0x00000020 */
+#define RCC_APB4ENR_SPI6EN                     RCC_APB4ENR_SPI6EN_Msk
+#define RCC_APB4ENR_I2C4EN_Pos                 (7U)
+#define RCC_APB4ENR_I2C4EN_Msk                 (0x1UL << RCC_APB4ENR_I2C4EN_Pos) /*!< 0x00000080 */
+#define RCC_APB4ENR_I2C4EN                     RCC_APB4ENR_I2C4EN_Msk
+#define RCC_APB4ENR_LPTIM2EN_Pos               (9U)
+#define RCC_APB4ENR_LPTIM2EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos) /*!< 0x00000200 */
+#define RCC_APB4ENR_LPTIM2EN                   RCC_APB4ENR_LPTIM2EN_Msk
+#define RCC_APB4ENR_LPTIM3EN_Pos               (10U)
+#define RCC_APB4ENR_LPTIM3EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos) /*!< 0x00000400 */
+#define RCC_APB4ENR_LPTIM3EN                   RCC_APB4ENR_LPTIM3EN_Msk
+#define RCC_APB4ENR_LPTIM4EN_Pos               (11U)
+#define RCC_APB4ENR_LPTIM4EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM4EN_Pos) /*!< 0x00000800 */
+#define RCC_APB4ENR_LPTIM4EN                   RCC_APB4ENR_LPTIM4EN_Msk
+#define RCC_APB4ENR_LPTIM5EN_Pos               (12U)
+#define RCC_APB4ENR_LPTIM5EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM5EN_Pos) /*!< 0x00001000 */
+#define RCC_APB4ENR_LPTIM5EN                   RCC_APB4ENR_LPTIM5EN_Msk
+#define RCC_APB4ENR_COMP12EN_Pos               (14U)
+#define RCC_APB4ENR_COMP12EN_Msk               (0x1UL << RCC_APB4ENR_COMP12EN_Pos) /*!< 0x00004000 */
+#define RCC_APB4ENR_COMP12EN                   RCC_APB4ENR_COMP12EN_Msk
+#define RCC_APB4ENR_VREFEN_Pos                 (15U)
+#define RCC_APB4ENR_VREFEN_Msk                 (0x1UL << RCC_APB4ENR_VREFEN_Pos) /*!< 0x00008000 */
+#define RCC_APB4ENR_VREFEN                     RCC_APB4ENR_VREFEN_Msk
+#define RCC_APB4ENR_RTCAPBEN_Pos               (16U)
+#define RCC_APB4ENR_RTCAPBEN_Msk               (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos) /*!< 0x00010000 */
+#define RCC_APB4ENR_RTCAPBEN                   RCC_APB4ENR_RTCAPBEN_Msk
+#define RCC_APB4ENR_SAI4EN_Pos                 (21U)
+#define RCC_APB4ENR_SAI4EN_Msk                 (0x1UL << RCC_APB4ENR_SAI4EN_Pos) /*!< 0x00200000 */
+#define RCC_APB4ENR_SAI4EN                     RCC_APB4ENR_SAI4EN_Msk
+
+
+/********************  Bit definition for RCC_AHB3RSTR register  ***************/
+#define RCC_AHB3RSTR_MDMARST_Pos               (0U)
+#define RCC_AHB3RSTR_MDMARST_Msk               (0x1UL << RCC_AHB3RSTR_MDMARST_Pos)      /*!< 0x00000001 */
+#define RCC_AHB3RSTR_MDMARST                   RCC_AHB3RSTR_MDMARST_Msk
+#define RCC_AHB3RSTR_DMA2DRST_Pos              (4U)
+#define RCC_AHB3RSTR_DMA2DRST_Msk              (0x1UL << RCC_AHB3RSTR_DMA2DRST_Pos)     /*!< 0x00000010 */
+#define RCC_AHB3RSTR_DMA2DRST                  RCC_AHB3RSTR_DMA2DRST_Msk
+#define RCC_AHB3RSTR_JPGDECRST_Pos             (5U)
+#define RCC_AHB3RSTR_JPGDECRST_Msk             (0x1UL << RCC_AHB3RSTR_JPGDECRST_Pos)    /*!< 0x00000020 */
+#define RCC_AHB3RSTR_JPGDECRST                 RCC_AHB3RSTR_JPGDECRST_Msk
+#define RCC_AHB3RSTR_FMCRST_Pos                (12U)
+#define RCC_AHB3RSTR_FMCRST_Msk                (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)      /*!< 0x00001000 */
+#define RCC_AHB3RSTR_FMCRST                    RCC_AHB3RSTR_FMCRST_Msk
+#define RCC_AHB3RSTR_QSPIRST_Pos               (14U)
+#define RCC_AHB3RSTR_QSPIRST_Msk               (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)     /*!< 0x00004000 */
+#define RCC_AHB3RSTR_QSPIRST                   RCC_AHB3RSTR_QSPIRST_Msk
+#define RCC_AHB3RSTR_SDMMC1RST_Pos             (16U)
+#define RCC_AHB3RSTR_SDMMC1RST_Msk             (0x1UL << RCC_AHB3RSTR_SDMMC1RST_Pos)   /*!< 0x00010000 */
+#define RCC_AHB3RSTR_SDMMC1RST                 RCC_AHB3RSTR_SDMMC1RST_Msk
+
+
+/********************  Bit definition for RCC_AHB1RSTR register  ***************/
+#define RCC_AHB1RSTR_DMA1RST_Pos               (0U)
+#define RCC_AHB1RSTR_DMA1RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)      /*!< 0x00000001 */
+#define RCC_AHB1RSTR_DMA1RST                   RCC_AHB1RSTR_DMA1RST_Msk
+#define RCC_AHB1RSTR_DMA2RST_Pos               (1U)
+#define RCC_AHB1RSTR_DMA2RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)      /*!< 0x00000002 */
+#define RCC_AHB1RSTR_DMA2RST                   RCC_AHB1RSTR_DMA2RST_Msk
+#define RCC_AHB1RSTR_ADC12RST_Pos              (5U)
+#define RCC_AHB1RSTR_ADC12RST_Msk              (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos)     /*!< 0x00000020 */
+#define RCC_AHB1RSTR_ADC12RST                  RCC_AHB1RSTR_ADC12RST_Msk
+#define RCC_AHB1RSTR_ETH1MACRST_Pos            (15U)
+#define RCC_AHB1RSTR_ETH1MACRST_Msk            (0x1UL << RCC_AHB1RSTR_ETH1MACRST_Pos)   /*!< 0x00008000 */
+#define RCC_AHB1RSTR_ETH1MACRST                RCC_AHB1RSTR_ETH1MACRST_Msk
+#define RCC_AHB1RSTR_USB1OTGHSRST_Pos          (25U)
+#define RCC_AHB1RSTR_USB1OTGHSRST_Msk          (0x1UL << RCC_AHB1RSTR_USB1OTGHSRST_Pos) /*!< 0x02000000 */
+#define RCC_AHB1RSTR_USB1OTGHSRST              RCC_AHB1RSTR_USB1OTGHSRST_Msk
+#define RCC_AHB1RSTR_USB2OTGFSRST_Pos          (27U)
+#define RCC_AHB1RSTR_USB2OTGFSRST_Msk          (0x1UL << RCC_AHB1RSTR_USB2OTGFSRST_Pos) /*!< 0x08000000 */
+#define RCC_AHB1RSTR_USB2OTGFSRST              RCC_AHB1RSTR_USB2OTGFSRST_Msk
+
+/* Legacy define */
+#define RCC_AHB1RSTR_USB2OTGHSRST_Pos          RCC_AHB1RSTR_USB2OTGFSRST_Pos
+#define RCC_AHB1RSTR_USB2OTGHSRST_Msk          RCC_AHB1RSTR_USB2OTGFSRST_Msk
+#define RCC_AHB1RSTR_USB2OTGHSRST              RCC_AHB1RSTR_USB2OTGFSRST
+
+/********************  Bit definition for RCC_AHB2RSTR register  ***************/
+#define RCC_AHB2RSTR_DCMIRST_Pos               (0U)
+#define RCC_AHB2RSTR_DCMIRST_Msk               (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)       /*!< 0x00000001 */
+#define RCC_AHB2RSTR_DCMIRST                   RCC_AHB2RSTR_DCMIRST_Msk
+#define RCC_AHB2RSTR_RNGRST_Pos                (6U)
+#define RCC_AHB2RSTR_RNGRST_Msk                (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)        /*!< 0x00000040 */
+#define RCC_AHB2RSTR_RNGRST                    RCC_AHB2RSTR_RNGRST_Msk
+#define RCC_AHB2RSTR_SDMMC2RST_Pos             (9U)
+#define RCC_AHB2RSTR_SDMMC2RST_Msk             (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos)     /*!< 0x00000200 */
+#define RCC_AHB2RSTR_SDMMC2RST                 RCC_AHB2RSTR_SDMMC2RST_Msk
+
+/********************  Bit definition for RCC_AHB4RSTR register  ******************/
+#define RCC_AHB4RSTR_GPIOARST_Pos              (0U)
+#define RCC_AHB4RSTR_GPIOARST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos)      /*!< 0x00000001 */
+#define RCC_AHB4RSTR_GPIOARST                  RCC_AHB4RSTR_GPIOARST_Msk
+#define RCC_AHB4RSTR_GPIOBRST_Pos              (1U)
+#define RCC_AHB4RSTR_GPIOBRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos)      /*!< 0x00000002 */
+#define RCC_AHB4RSTR_GPIOBRST                  RCC_AHB4RSTR_GPIOBRST_Msk
+#define RCC_AHB4RSTR_GPIOCRST_Pos              (2U)
+#define RCC_AHB4RSTR_GPIOCRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos)      /*!< 0x00000004 */
+#define RCC_AHB4RSTR_GPIOCRST                  RCC_AHB4RSTR_GPIOCRST_Msk
+#define RCC_AHB4RSTR_GPIODRST_Pos              (3U)
+#define RCC_AHB4RSTR_GPIODRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos)      /*!< 0x00000008 */
+#define RCC_AHB4RSTR_GPIODRST                  RCC_AHB4RSTR_GPIODRST_Msk
+#define RCC_AHB4RSTR_GPIOERST_Pos              (4U)
+#define RCC_AHB4RSTR_GPIOERST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos)      /*!< 0x00000010 */
+#define RCC_AHB4RSTR_GPIOERST                  RCC_AHB4RSTR_GPIOERST_Msk
+#define RCC_AHB4RSTR_GPIOFRST_Pos              (5U)
+#define RCC_AHB4RSTR_GPIOFRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos)       /*!< 0x00000020 */
+#define RCC_AHB4RSTR_GPIOFRST                  RCC_AHB4RSTR_GPIOFRST_Msk
+#define RCC_AHB4RSTR_GPIOGRST_Pos              (6U)
+#define RCC_AHB4RSTR_GPIOGRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos)       /*!< 0x00000040 */
+#define RCC_AHB4RSTR_GPIOGRST                  RCC_AHB4RSTR_GPIOGRST_Msk
+#define RCC_AHB4RSTR_GPIOHRST_Pos              (7U)
+#define RCC_AHB4RSTR_GPIOHRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos)       /*!< 0x00000080 */
+#define RCC_AHB4RSTR_GPIOHRST                  RCC_AHB4RSTR_GPIOHRST_Msk
+#define RCC_AHB4RSTR_GPIOIRST_Pos              (8U)
+#define RCC_AHB4RSTR_GPIOIRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOIRST_Pos)       /*!< 0x00000100 */
+#define RCC_AHB4RSTR_GPIOIRST                  RCC_AHB4RSTR_GPIOIRST_Msk
+#define RCC_AHB4RSTR_GPIOJRST_Pos              (9U)
+#define RCC_AHB4RSTR_GPIOJRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOJRST_Pos)       /*!< 0x00000200 */
+#define RCC_AHB4RSTR_GPIOJRST                  RCC_AHB4RSTR_GPIOJRST_Msk
+#define RCC_AHB4RSTR_GPIOKRST_Pos              (10U)
+#define RCC_AHB4RSTR_GPIOKRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOKRST_Pos)       /*!< 0x00000400 */
+#define RCC_AHB4RSTR_GPIOKRST                  RCC_AHB4RSTR_GPIOKRST_Msk
+#define RCC_AHB4RSTR_CRCRST_Pos                (19U)
+#define RCC_AHB4RSTR_CRCRST_Msk                (0x1UL << RCC_AHB4RSTR_CRCRST_Pos)         /*!< 0x00080000 */
+#define RCC_AHB4RSTR_CRCRST                    RCC_AHB4RSTR_CRCRST_Msk
+#define RCC_AHB4RSTR_BDMARST_Pos               (21U)
+#define RCC_AHB4RSTR_BDMARST_Msk               (0x1UL << RCC_AHB4RSTR_BDMARST_Pos)        /*!< 0x00200000 */
+#define RCC_AHB4RSTR_BDMARST                   RCC_AHB4RSTR_BDMARST_Msk
+#define RCC_AHB4RSTR_ADC3RST_Pos               (24U)
+#define RCC_AHB4RSTR_ADC3RST_Msk               (0x1UL << RCC_AHB4RSTR_ADC3RST_Pos)        /*!< 0x01000000 */
+#define RCC_AHB4RSTR_ADC3RST                   RCC_AHB4RSTR_ADC3RST_Msk
+#define RCC_AHB4RSTR_HSEMRST_Pos               (25U)
+#define RCC_AHB4RSTR_HSEMRST_Msk               (0x1UL << RCC_AHB4RSTR_HSEMRST_Pos)        /*!< 0x02000000 */
+#define RCC_AHB4RSTR_HSEMRST                   RCC_AHB4RSTR_HSEMRST_Msk
+
+
+/********************  Bit definition for RCC_APB3RSTR register  ******************/
+#define RCC_APB3RSTR_LTDCRST_Pos               (3U)
+#define RCC_APB3RSTR_LTDCRST_Msk               (0x1UL << RCC_APB3RSTR_LTDCRST_Pos) /*!< 0x00000008 */
+#define RCC_APB3RSTR_LTDCRST                   RCC_APB3RSTR_LTDCRST_Msk
+
+/********************  Bit definition for RCC_APB1LRSTR register  ******************/
+
+#define RCC_APB1LRSTR_TIM2RST_Pos              (0U)
+#define RCC_APB1LRSTR_TIM2RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1LRSTR_TIM2RST                  RCC_APB1LRSTR_TIM2RST_Msk
+#define RCC_APB1LRSTR_TIM3RST_Pos              (1U)
+#define RCC_APB1LRSTR_TIM3RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1LRSTR_TIM3RST                  RCC_APB1LRSTR_TIM3RST_Msk
+#define RCC_APB1LRSTR_TIM4RST_Pos              (2U)
+#define RCC_APB1LRSTR_TIM4RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1LRSTR_TIM4RST                  RCC_APB1LRSTR_TIM4RST_Msk
+#define RCC_APB1LRSTR_TIM5RST_Pos              (3U)
+#define RCC_APB1LRSTR_TIM5RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos) /*!< 0x00000008 */
+#define RCC_APB1LRSTR_TIM5RST                  RCC_APB1LRSTR_TIM5RST_Msk
+#define RCC_APB1LRSTR_TIM6RST_Pos              (4U)
+#define RCC_APB1LRSTR_TIM6RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1LRSTR_TIM6RST                  RCC_APB1LRSTR_TIM6RST_Msk
+#define RCC_APB1LRSTR_TIM7RST_Pos              (5U)
+#define RCC_APB1LRSTR_TIM7RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1LRSTR_TIM7RST                  RCC_APB1LRSTR_TIM7RST_Msk
+#define RCC_APB1LRSTR_TIM12RST_Pos             (6U)
+#define RCC_APB1LRSTR_TIM12RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos) /*!< 0x00000040 */
+#define RCC_APB1LRSTR_TIM12RST                 RCC_APB1LRSTR_TIM12RST_Msk
+#define RCC_APB1LRSTR_TIM13RST_Pos             (7U)
+#define RCC_APB1LRSTR_TIM13RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM13RST_Pos) /*!< 0x00000080 */
+#define RCC_APB1LRSTR_TIM13RST                 RCC_APB1LRSTR_TIM13RST_Msk
+#define RCC_APB1LRSTR_TIM14RST_Pos             (8U)
+#define RCC_APB1LRSTR_TIM14RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM14RST_Pos) /*!< 0x00000100 */
+#define RCC_APB1LRSTR_TIM14RST                 RCC_APB1LRSTR_TIM14RST_Msk
+#define RCC_APB1LRSTR_LPTIM1RST_Pos            (9U)
+#define RCC_APB1LRSTR_LPTIM1RST_Msk            (0x1UL << RCC_APB1LRSTR_LPTIM1RST_Pos) /*!< 0x00000200 */
+#define RCC_APB1LRSTR_LPTIM1RST                RCC_APB1LRSTR_LPTIM1RST_Msk
+#define RCC_APB1LRSTR_SPI2RST_Pos              (14U)
+#define RCC_APB1LRSTR_SPI2RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1LRSTR_SPI2RST                  RCC_APB1LRSTR_SPI2RST_Msk
+#define RCC_APB1LRSTR_SPI3RST_Pos              (15U)
+#define RCC_APB1LRSTR_SPI3RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos) /*!< 0x00008000 */
+#define RCC_APB1LRSTR_SPI3RST                  RCC_APB1LRSTR_SPI3RST_Msk
+#define RCC_APB1LRSTR_SPDIFRXRST_Pos           (16U)
+#define RCC_APB1LRSTR_SPDIFRXRST_Msk           (0x1UL << RCC_APB1LRSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */
+#define RCC_APB1LRSTR_SPDIFRXRST               RCC_APB1LRSTR_SPDIFRXRST_Msk
+#define RCC_APB1LRSTR_USART2RST_Pos            (17U)
+#define RCC_APB1LRSTR_USART2RST_Msk            (0x1UL << RCC_APB1LRSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1LRSTR_USART2RST                RCC_APB1LRSTR_USART2RST_Msk
+#define RCC_APB1LRSTR_USART3RST_Pos            (18U)
+#define RCC_APB1LRSTR_USART3RST_Msk            (0x1UL << RCC_APB1LRSTR_USART3RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1LRSTR_USART3RST                RCC_APB1LRSTR_USART3RST_Msk
+#define RCC_APB1LRSTR_UART4RST_Pos             (19U)
+#define RCC_APB1LRSTR_UART4RST_Msk             (0x1UL << RCC_APB1LRSTR_UART4RST_Pos) /*!< 0x00080000 */
+#define RCC_APB1LRSTR_UART4RST                 RCC_APB1LRSTR_UART4RST_Msk
+#define RCC_APB1LRSTR_UART5RST_Pos             (20U)
+#define RCC_APB1LRSTR_UART5RST_Msk             (0x1UL << RCC_APB1LRSTR_UART5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB1LRSTR_UART5RST                 RCC_APB1LRSTR_UART5RST_Msk
+#define RCC_APB1LRSTR_I2C1RST_Pos              (21U)
+#define RCC_APB1LRSTR_I2C1RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1LRSTR_I2C1RST                  RCC_APB1LRSTR_I2C1RST_Msk
+#define RCC_APB1LRSTR_I2C2RST_Pos              (22U)
+#define RCC_APB1LRSTR_I2C2RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1LRSTR_I2C2RST                  RCC_APB1LRSTR_I2C2RST_Msk
+#define RCC_APB1LRSTR_I2C3RST_Pos              (23U)
+#define RCC_APB1LRSTR_I2C3RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C3RST_Pos) /*!< 0x00800000 */
+#define RCC_APB1LRSTR_I2C3RST                  RCC_APB1LRSTR_I2C3RST_Msk
+#define RCC_APB1LRSTR_CECRST_Pos               (27U)
+#define RCC_APB1LRSTR_CECRST_Msk               (0x1UL << RCC_APB1LRSTR_CECRST_Pos) /*!< 0x08000000 */
+#define RCC_APB1LRSTR_CECRST                   RCC_APB1LRSTR_CECRST_Msk
+#define RCC_APB1LRSTR_DAC12RST_Pos             (29U)
+#define RCC_APB1LRSTR_DAC12RST_Msk             (0x1UL << RCC_APB1LRSTR_DAC12RST_Pos) /*!< 0x20000000 */
+#define RCC_APB1LRSTR_DAC12RST                 RCC_APB1LRSTR_DAC12RST_Msk
+#define RCC_APB1LRSTR_UART7RST_Pos             (30U)
+#define RCC_APB1LRSTR_UART7RST_Msk             (0x1UL << RCC_APB1LRSTR_UART7RST_Pos) /*!< 0x40000000 */
+#define RCC_APB1LRSTR_UART7RST                 RCC_APB1LRSTR_UART7RST_Msk
+#define RCC_APB1LRSTR_UART8RST_Pos             (31U)
+#define RCC_APB1LRSTR_UART8RST_Msk             (0x1UL << RCC_APB1LRSTR_UART8RST_Pos) /*!< 0x80000000 */
+#define RCC_APB1LRSTR_UART8RST                 RCC_APB1LRSTR_UART8RST_Msk
+
+/* Legacy define */
+#define RCC_APB1LRSTR_HDMICECRST_Pos           RCC_APB1LRSTR_CECRST_Pos
+#define RCC_APB1LRSTR_HDMICECRST_Msk           RCC_APB1LRSTR_CECRST_Msk
+#define RCC_APB1LRSTR_HDMICECRST               RCC_APB1LRSTR_CECRST
+/********************  Bit definition for RCC_APB1HRSTR register  ******************/
+#define RCC_APB1HRSTR_CRSRST_Pos               (1U)
+#define RCC_APB1HRSTR_CRSRST_Msk               (0x1UL << RCC_APB1HRSTR_CRSRST_Pos) /*!< 0x00000002 */
+#define RCC_APB1HRSTR_CRSRST                   RCC_APB1HRSTR_CRSRST_Msk
+#define RCC_APB1HRSTR_SWPMIRST_Pos             (2U)
+#define RCC_APB1HRSTR_SWPMIRST_Msk             (0x1UL << RCC_APB1HRSTR_SWPMIRST_Pos) /*!< 0x00000004 */
+#define RCC_APB1HRSTR_SWPMIRST                 RCC_APB1HRSTR_SWPMIRST_Msk
+#define RCC_APB1HRSTR_OPAMPRST_Pos             (4U)
+#define RCC_APB1HRSTR_OPAMPRST_Msk             (0x1UL << RCC_APB1HRSTR_OPAMPRST_Pos) /*!< 0x00000010 */
+#define RCC_APB1HRSTR_OPAMPRST                 RCC_APB1HRSTR_OPAMPRST_Msk
+#define RCC_APB1HRSTR_MDIOSRST_Pos             (5U)
+#define RCC_APB1HRSTR_MDIOSRST_Msk             (0x1UL << RCC_APB1HRSTR_MDIOSRST_Pos) /*!< 0x00000020 */
+#define RCC_APB1HRSTR_MDIOSRST                 RCC_APB1HRSTR_MDIOSRST_Msk
+#define RCC_APB1HRSTR_FDCANRST_Pos             (8U)
+#define RCC_APB1HRSTR_FDCANRST_Msk             (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos) /*!< 0x00000100 */
+#define RCC_APB1HRSTR_FDCANRST                 RCC_APB1HRSTR_FDCANRST_Msk
+
+/********************  Bit definition for RCC_APB2RSTR register  ******************/
+#define RCC_APB2RSTR_TIM1RST_Pos               (0U)
+#define RCC_APB2RSTR_TIM1RST_Msk               (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_TIM1RST                   RCC_APB2RSTR_TIM1RST_Msk
+#define RCC_APB2RSTR_TIM8RST_Pos               (1U)
+#define RCC_APB2RSTR_TIM8RST_Msk               (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
+#define RCC_APB2RSTR_TIM8RST                   RCC_APB2RSTR_TIM8RST_Msk
+#define RCC_APB2RSTR_USART1RST_Pos             (4U)
+#define RCC_APB2RSTR_USART1RST_Msk             (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTR_USART1RST                 RCC_APB2RSTR_USART1RST_Msk
+#define RCC_APB2RSTR_USART6RST_Pos             (5U)
+#define RCC_APB2RSTR_USART6RST_Msk             (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_USART6RST                 RCC_APB2RSTR_USART6RST_Msk
+#define RCC_APB2RSTR_SPI1RST_Pos               (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk               (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST                   RCC_APB2RSTR_SPI1RST_Msk
+#define RCC_APB2RSTR_SPI4RST_Pos               (13U)
+#define RCC_APB2RSTR_SPI4RST_Msk               (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
+#define RCC_APB2RSTR_SPI4RST                   RCC_APB2RSTR_SPI4RST_Msk
+#define RCC_APB2RSTR_TIM15RST_Pos              (16U)
+#define RCC_APB2RSTR_TIM15RST_Msk              (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
+#define RCC_APB2RSTR_TIM15RST                  RCC_APB2RSTR_TIM15RST_Msk
+#define RCC_APB2RSTR_TIM16RST_Pos              (17U)
+#define RCC_APB2RSTR_TIM16RST_Msk              (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
+#define RCC_APB2RSTR_TIM16RST                  RCC_APB2RSTR_TIM16RST_Msk
+#define RCC_APB2RSTR_TIM17RST_Pos              (18U)
+#define RCC_APB2RSTR_TIM17RST_Msk              (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
+#define RCC_APB2RSTR_TIM17RST                  RCC_APB2RSTR_TIM17RST_Msk
+#define RCC_APB2RSTR_SPI5RST_Pos               (20U)
+#define RCC_APB2RSTR_SPI5RST_Msk               (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB2RSTR_SPI5RST                   RCC_APB2RSTR_SPI5RST_Msk
+#define RCC_APB2RSTR_SAI1RST_Pos               (22U)
+#define RCC_APB2RSTR_SAI1RST_Msk               (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */
+#define RCC_APB2RSTR_SAI1RST                   RCC_APB2RSTR_SAI1RST_Msk
+#define RCC_APB2RSTR_SAI2RST_Pos               (23U)
+#define RCC_APB2RSTR_SAI2RST_Msk               (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */
+#define RCC_APB2RSTR_SAI2RST                   RCC_APB2RSTR_SAI2RST_Msk
+#define RCC_APB2RSTR_SAI3RST_Pos               (24U)
+#define RCC_APB2RSTR_SAI3RST_Msk               (0x1UL << RCC_APB2RSTR_SAI3RST_Pos) /*!< 0x01000000 */
+#define RCC_APB2RSTR_SAI3RST                   RCC_APB2RSTR_SAI3RST_Msk
+#define RCC_APB2RSTR_DFSDM1RST_Pos             (28U)
+#define RCC_APB2RSTR_DFSDM1RST_Msk             (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x10000000 */
+#define RCC_APB2RSTR_DFSDM1RST                 RCC_APB2RSTR_DFSDM1RST_Msk
+#define RCC_APB2RSTR_HRTIMRST_Pos              (29U)
+#define RCC_APB2RSTR_HRTIMRST_Msk              (0x1UL << RCC_APB2RSTR_HRTIMRST_Pos) /*!< 0x20000000 */
+#define RCC_APB2RSTR_HRTIMRST                  RCC_APB2RSTR_HRTIMRST_Msk
+
+/********************  Bit definition for RCC_APB4RSTR register  ******************/
+#define RCC_APB4RSTR_SYSCFGRST_Pos             (1U)
+#define RCC_APB4RSTR_SYSCFGRST_Msk             (0x1UL << RCC_APB4RSTR_SYSCFGRST_Pos) /*!< 0x00000002 */
+#define RCC_APB4RSTR_SYSCFGRST                 RCC_APB4RSTR_SYSCFGRST_Msk
+#define RCC_APB4RSTR_LPUART1RST_Pos            (3U)
+#define RCC_APB4RSTR_LPUART1RST_Msk            (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos) /*!< 0x00000008 */
+#define RCC_APB4RSTR_LPUART1RST                RCC_APB4RSTR_LPUART1RST_Msk
+#define RCC_APB4RSTR_SPI6RST_Pos               (5U)
+#define RCC_APB4RSTR_SPI6RST_Msk               (0x1UL << RCC_APB4RSTR_SPI6RST_Pos) /*!< 0x00000020 */
+#define RCC_APB4RSTR_SPI6RST                   RCC_APB4RSTR_SPI6RST_Msk
+#define RCC_APB4RSTR_I2C4RST_Pos               (7U)
+#define RCC_APB4RSTR_I2C4RST_Msk               (0x1UL << RCC_APB4RSTR_I2C4RST_Pos) /*!< 0x00000080 */
+#define RCC_APB4RSTR_I2C4RST                   RCC_APB4RSTR_I2C4RST_Msk
+#define RCC_APB4RSTR_LPTIM2RST_Pos             (9U)
+#define RCC_APB4RSTR_LPTIM2RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos) /*!< 0x00000200 */
+#define RCC_APB4RSTR_LPTIM2RST                 RCC_APB4RSTR_LPTIM2RST_Msk
+#define RCC_APB4RSTR_LPTIM3RST_Pos             (10U)
+#define RCC_APB4RSTR_LPTIM3RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos) /*!< 0x00000400 */
+#define RCC_APB4RSTR_LPTIM3RST                 RCC_APB4RSTR_LPTIM3RST_Msk
+#define RCC_APB4RSTR_LPTIM4RST_Pos             (11U)
+#define RCC_APB4RSTR_LPTIM4RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM4RST_Pos) /*!< 0x00000800 */
+#define RCC_APB4RSTR_LPTIM4RST                 RCC_APB4RSTR_LPTIM4RST_Msk
+#define RCC_APB4RSTR_LPTIM5RST_Pos             (12U)
+#define RCC_APB4RSTR_LPTIM5RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM5RST_Pos) /*!< 0x00001000 */
+#define RCC_APB4RSTR_LPTIM5RST                 RCC_APB4RSTR_LPTIM5RST_Msk
+#define RCC_APB4RSTR_COMP12RST_Pos             (14U)
+#define RCC_APB4RSTR_COMP12RST_Msk             (0x1UL << RCC_APB4RSTR_COMP12RST_Pos) /*!< 0x00004000 */
+#define RCC_APB4RSTR_COMP12RST                 RCC_APB4RSTR_COMP12RST_Msk
+#define RCC_APB4RSTR_VREFRST_Pos               (15U)
+#define RCC_APB4RSTR_VREFRST_Msk               (0x1UL << RCC_APB4RSTR_VREFRST_Pos) /*!< 0x00008000 */
+#define RCC_APB4RSTR_VREFRST                   RCC_APB4RSTR_VREFRST_Msk
+#define RCC_APB4RSTR_SAI4RST_Pos               (21U)
+#define RCC_APB4RSTR_SAI4RST_Msk               (0x1UL << RCC_APB4RSTR_SAI4RST_Pos) /*!< 0x00200000 */
+#define RCC_APB4RSTR_SAI4RST                   RCC_APB4RSTR_SAI4RST_Msk
+
+
+/********************  Bit definition for RCC_GCR register  ********************/
+#define RCC_GCR_WW1RSC_Pos                     (0U)
+#define RCC_GCR_WW1RSC_Msk                     (0x1UL << RCC_GCR_WW1RSC_Pos)   /*!< 0x00000001 */
+#define RCC_GCR_WW1RSC                         RCC_GCR_WW1RSC_Msk
+
+/********************  Bit definition for RCC_D3AMR register  ********************/
+#define RCC_D3AMR_BDMAAMEN_Pos                 (0U)
+#define RCC_D3AMR_BDMAAMEN_Msk                 (0x1UL << RCC_D3AMR_BDMAAMEN_Pos) /*!< 0x00000001 */
+#define RCC_D3AMR_BDMAAMEN                     RCC_D3AMR_BDMAAMEN_Msk
+#define RCC_D3AMR_LPUART1AMEN_Pos              (3U)
+#define RCC_D3AMR_LPUART1AMEN_Msk              (0x1UL << RCC_D3AMR_LPUART1AMEN_Pos) /*!< 0x00000008 */
+#define RCC_D3AMR_LPUART1AMEN                  RCC_D3AMR_LPUART1AMEN_Msk
+#define RCC_D3AMR_SPI6AMEN_Pos                 (5U)
+#define RCC_D3AMR_SPI6AMEN_Msk                 (0x1UL << RCC_D3AMR_SPI6AMEN_Pos) /*!< 0x00000020 */
+#define RCC_D3AMR_SPI6AMEN                     RCC_D3AMR_SPI6AMEN_Msk
+#define RCC_D3AMR_I2C4AMEN_Pos                 (7U)
+#define RCC_D3AMR_I2C4AMEN_Msk                 (0x1UL << RCC_D3AMR_I2C4AMEN_Pos) /*!< 0x00000080 */
+#define RCC_D3AMR_I2C4AMEN                     RCC_D3AMR_I2C4AMEN_Msk
+#define RCC_D3AMR_LPTIM2AMEN_Pos               (9U)
+#define RCC_D3AMR_LPTIM2AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM2AMEN_Pos) /*!< 0x00000200 */
+#define RCC_D3AMR_LPTIM2AMEN                   RCC_D3AMR_LPTIM2AMEN_Msk
+#define RCC_D3AMR_LPTIM3AMEN_Pos               (10U)
+#define RCC_D3AMR_LPTIM3AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM3AMEN_Pos) /*!< 0x00000400 */
+#define RCC_D3AMR_LPTIM3AMEN                   RCC_D3AMR_LPTIM3AMEN_Msk
+#define RCC_D3AMR_LPTIM4AMEN_Pos               (11U)
+#define RCC_D3AMR_LPTIM4AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM4AMEN_Pos) /*!< 0x00000800 */
+#define RCC_D3AMR_LPTIM4AMEN                   RCC_D3AMR_LPTIM4AMEN_Msk
+#define RCC_D3AMR_LPTIM5AMEN_Pos               (12U)
+#define RCC_D3AMR_LPTIM5AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM5AMEN_Pos) /*!< 0x00001000 */
+#define RCC_D3AMR_LPTIM5AMEN                   RCC_D3AMR_LPTIM5AMEN_Msk
+#define RCC_D3AMR_COMP12AMEN_Pos               (14U)
+#define RCC_D3AMR_COMP12AMEN_Msk               (0x1UL << RCC_D3AMR_COMP12AMEN_Pos) /*!< 0x00004000 */
+#define RCC_D3AMR_COMP12AMEN                   RCC_D3AMR_COMP12AMEN_Msk
+#define RCC_D3AMR_VREFAMEN_Pos                 (15U)
+#define RCC_D3AMR_VREFAMEN_Msk                 (0x1UL << RCC_D3AMR_VREFAMEN_Pos) /*!< 0x00008000 */
+#define RCC_D3AMR_VREFAMEN                     RCC_D3AMR_VREFAMEN_Msk
+#define RCC_D3AMR_RTCAMEN_Pos                  (16U)
+#define RCC_D3AMR_RTCAMEN_Msk                  (0x1UL << RCC_D3AMR_RTCAMEN_Pos) /*!< 0x00010000 */
+#define RCC_D3AMR_RTCAMEN                      RCC_D3AMR_RTCAMEN_Msk
+#define RCC_D3AMR_CRCAMEN_Pos                  (19U)
+#define RCC_D3AMR_CRCAMEN_Msk                  (0x1UL << RCC_D3AMR_CRCAMEN_Pos) /*!< 0x00080000 */
+#define RCC_D3AMR_CRCAMEN                      RCC_D3AMR_CRCAMEN_Msk
+#define RCC_D3AMR_SAI4AMEN_Pos                 (21U)
+#define RCC_D3AMR_SAI4AMEN_Msk                 (0x1UL << RCC_D3AMR_SAI4AMEN_Pos) /*!< 0x00200000 */
+#define RCC_D3AMR_SAI4AMEN                     RCC_D3AMR_SAI4AMEN_Msk
+#define RCC_D3AMR_ADC3AMEN_Pos                 (24U)
+#define RCC_D3AMR_ADC3AMEN_Msk                 (0x1UL << RCC_D3AMR_ADC3AMEN_Pos) /*!< 0x01000000 */
+#define RCC_D3AMR_ADC3AMEN                     RCC_D3AMR_ADC3AMEN_Msk
+
+
+#define RCC_D3AMR_BKPRAMAMEN_Pos               (28U)
+#define RCC_D3AMR_BKPRAMAMEN_Msk               (0x1UL << RCC_D3AMR_BKPRAMAMEN_Pos) /*!< 0x10000000 */
+#define RCC_D3AMR_BKPRAMAMEN                   RCC_D3AMR_BKPRAMAMEN_Msk
+#define RCC_D3AMR_SRAM4AMEN_Pos                (29U)
+#define RCC_D3AMR_SRAM4AMEN_Msk                (0x1UL << RCC_D3AMR_SRAM4AMEN_Pos) /*!< 0x20000000 */
+#define RCC_D3AMR_SRAM4AMEN                    RCC_D3AMR_SRAM4AMEN_Msk
+/********************  Bit definition for RCC_AHB3LPENR register  **************/
+#define RCC_AHB3LPENR_MDMALPEN_Pos             (0U)
+#define RCC_AHB3LPENR_MDMALPEN_Msk             (0x1UL << RCC_AHB3LPENR_MDMALPEN_Pos)         /*!< 0x00000001 */
+#define RCC_AHB3LPENR_MDMALPEN                 RCC_AHB3LPENR_MDMALPEN_Msk
+#define RCC_AHB3LPENR_DMA2DLPEN_Pos            (4U)
+#define RCC_AHB3LPENR_DMA2DLPEN_Msk            (0x1UL << RCC_AHB3LPENR_DMA2DLPEN_Pos)        /*!< 0x00000010 */
+#define RCC_AHB3LPENR_DMA2DLPEN                RCC_AHB3LPENR_DMA2DLPEN_Msk
+#define RCC_AHB3LPENR_JPGDECLPEN_Pos           (5U)
+#define RCC_AHB3LPENR_JPGDECLPEN_Msk           (0x1UL << RCC_AHB3LPENR_JPGDECLPEN_Pos)       /*!< 0x00000020 */
+#define RCC_AHB3LPENR_JPGDECLPEN               RCC_AHB3LPENR_JPGDECLPEN_Msk
+#define RCC_AHB3LPENR_FLASHLPEN_Pos            (8U)
+#define RCC_AHB3LPENR_FLASHLPEN_Msk            (0x1UL << RCC_AHB3LPENR_FLASHLPEN_Pos)        /*!< 0x00000100 */
+#define RCC_AHB3LPENR_FLASHLPEN                RCC_AHB3LPENR_FLASHLPEN_Msk
+#define RCC_AHB3LPENR_FMCLPEN_Pos              (12U)
+#define RCC_AHB3LPENR_FMCLPEN_Msk              (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos)          /*!< 0x00001000 */
+#define RCC_AHB3LPENR_FMCLPEN                  RCC_AHB3LPENR_FMCLPEN_Msk
+#define RCC_AHB3LPENR_QSPILPEN_Pos             (14U)
+#define RCC_AHB3LPENR_QSPILPEN_Msk             (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos)         /*!< 0x00004000 */
+#define RCC_AHB3LPENR_QSPILPEN                 RCC_AHB3LPENR_QSPILPEN_Msk
+#define RCC_AHB3LPENR_SDMMC1LPEN_Pos           (16U)
+#define RCC_AHB3LPENR_SDMMC1LPEN_Msk           (0x1UL << RCC_AHB3LPENR_SDMMC1LPEN_Pos)       /*!< 0x00010000 */
+#define RCC_AHB3LPENR_SDMMC1LPEN               RCC_AHB3LPENR_SDMMC1LPEN_Msk
+#define RCC_AHB3LPENR_DTCM1LPEN_Pos            (28U)
+#define RCC_AHB3LPENR_DTCM1LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM1LPEN_Pos)        /*!< 0x10000000 */
+#define RCC_AHB3LPENR_DTCM1LPEN                RCC_AHB3LPENR_DTCM1LPEN_Msk
+#define RCC_AHB3LPENR_DTCM2LPEN_Pos            (29U)
+#define RCC_AHB3LPENR_DTCM2LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM2LPEN_Pos)        /*!< 0x20000000 */
+#define RCC_AHB3LPENR_DTCM2LPEN                RCC_AHB3LPENR_DTCM2LPEN_Msk
+#define RCC_AHB3LPENR_ITCMLPEN_Pos             (30U)
+#define RCC_AHB3LPENR_ITCMLPEN_Msk             (0x1UL << RCC_AHB3LPENR_ITCMLPEN_Pos)         /*!< 0x40000000 */
+#define RCC_AHB3LPENR_ITCMLPEN                 RCC_AHB3LPENR_ITCMLPEN_Msk
+#define RCC_AHB3LPENR_AXISRAMLPEN_Pos          (31U)
+#define RCC_AHB3LPENR_AXISRAMLPEN_Msk          (0x1UL << RCC_AHB3LPENR_AXISRAMLPEN_Pos)      /*!< 0x80000000 */
+#define RCC_AHB3LPENR_AXISRAMLPEN              RCC_AHB3LPENR_AXISRAMLPEN_Msk
+
+
+/********************  Bit definition for RCC_AHB1LPENR register  ***************/
+#define RCC_AHB1LPENR_DMA1LPEN_Pos             (0U)
+#define RCC_AHB1LPENR_DMA1LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1LPENR_DMA1LPEN                 RCC_AHB1LPENR_DMA1LPEN_Msk
+#define RCC_AHB1LPENR_DMA2LPEN_Pos             (1U)
+#define RCC_AHB1LPENR_DMA2LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1LPENR_DMA2LPEN                 RCC_AHB1LPENR_DMA2LPEN_Msk
+#define RCC_AHB1LPENR_ADC12LPEN_Pos            (5U)
+#define RCC_AHB1LPENR_ADC12LPEN_Msk            (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB1LPENR_ADC12LPEN                RCC_AHB1LPENR_ADC12LPEN_Msk
+#define RCC_AHB1LPENR_ETH1MACLPEN_Pos          (15U)
+#define RCC_AHB1LPENR_ETH1MACLPEN_Msk          (0x1UL << RCC_AHB1LPENR_ETH1MACLPEN_Pos) /*!< 0x00008000 */
+#define RCC_AHB1LPENR_ETH1MACLPEN              RCC_AHB1LPENR_ETH1MACLPEN_Msk
+#define RCC_AHB1LPENR_ETH1TXLPEN_Pos           (16U)
+#define RCC_AHB1LPENR_ETH1TXLPEN_Msk           (0x1UL << RCC_AHB1LPENR_ETH1TXLPEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB1LPENR_ETH1TXLPEN               RCC_AHB1LPENR_ETH1TXLPEN_Msk
+#define RCC_AHB1LPENR_ETH1RXLPEN_Pos           (17U)
+#define RCC_AHB1LPENR_ETH1RXLPEN_Msk           (0x1UL << RCC_AHB1LPENR_ETH1RXLPEN_Pos) /*!< 0x00020000 */
+#define RCC_AHB1LPENR_ETH1RXLPEN               RCC_AHB1LPENR_ETH1RXLPEN_Msk
+#define RCC_AHB1LPENR_USB1OTGHSLPEN_Pos        (25U)
+#define RCC_AHB1LPENR_USB1OTGHSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_USB1OTGHSLPEN_Pos) /*!< 0x02000000 */
+#define RCC_AHB1LPENR_USB1OTGHSLPEN            RCC_AHB1LPENR_USB1OTGHSLPEN_Msk
+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos    (26U)
+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos) /*!< 0x04000000 */
+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN        RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk
+#define RCC_AHB1LPENR_USB2OTGFSLPEN_Pos        (27U)
+#define RCC_AHB1LPENR_USB2OTGFSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_USB2OTGFSLPEN_Pos) /*!< 0x08000000 */
+#define RCC_AHB1LPENR_USB2OTGFSLPEN            RCC_AHB1LPENR_USB2OTGFSLPEN_Msk
+#define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos    (28U)
+#define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos) /*!< 0x10000000 */
+#define RCC_AHB1LPENR_USB2OTGFSULPILPEN        RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk
+
+/* Legacy define */
+#define RCC_AHB1LPENR_USB2OTGHSLPEN_Pos        RCC_AHB1LPENR_USB2OTGFSLPEN_Pos
+#define RCC_AHB1LPENR_USB2OTGHSLPEN_Msk        RCC_AHB1LPENR_USB2OTGFSLPEN_Msk
+#define RCC_AHB1LPENR_USB2OTGHSLPEN            RCC_AHB1LPENR_USB2OTGFSLPEN
+#define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Pos    RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos
+#define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Msk    RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk
+#define RCC_AHB1LPENR_USB2OTGHSULPILPEN        RCC_AHB1LPENR_USB2OTGFSULPILPEN
+
+/********************  Bit definition for RCC_AHB2LPENR register  ***************/
+#define RCC_AHB2LPENR_DCMILPEN_Pos             (0U)
+#define RCC_AHB2LPENR_DCMILPEN_Msk             (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB2LPENR_DCMILPEN                 RCC_AHB2LPENR_DCMILPEN_Msk
+#define RCC_AHB2LPENR_RNGLPEN_Pos              (6U)
+#define RCC_AHB2LPENR_RNGLPEN_Msk              (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB2LPENR_RNGLPEN                  RCC_AHB2LPENR_RNGLPEN_Msk
+#define RCC_AHB2LPENR_SDMMC2LPEN_Pos           (9U)
+#define RCC_AHB2LPENR_SDMMC2LPEN_Msk           (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000200 */
+#define RCC_AHB2LPENR_SDMMC2LPEN               RCC_AHB2LPENR_SDMMC2LPEN_Msk
+#define RCC_AHB2LPENR_SRAM1LPEN_Pos          (29U)
+#define RCC_AHB2LPENR_SRAM1LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM1LPEN_Pos) /*!< 0x20000000 */
+#define RCC_AHB2LPENR_SRAM1LPEN              RCC_AHB2LPENR_SRAM1LPEN_Msk
+#define RCC_AHB2LPENR_SRAM2LPEN_Pos          (30U)
+#define RCC_AHB2LPENR_SRAM2LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM2LPEN_Pos) /*!< 0x40000000 */
+#define RCC_AHB2LPENR_SRAM2LPEN              RCC_AHB2LPENR_SRAM2LPEN_Msk
+#define RCC_AHB2LPENR_SRAM3LPEN_Pos          (31U)
+#define RCC_AHB2LPENR_SRAM3LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM3LPEN_Pos) /*!< 0x80000000 */
+#define RCC_AHB2LPENR_SRAM3LPEN              RCC_AHB2LPENR_SRAM3LPEN_Msk
+
+/* Legacy define */
+#define RCC_AHB2LPENR_D2SRAM1LPEN_Pos          RCC_AHB2LPENR_SRAM1LPEN_Pos
+#define RCC_AHB2LPENR_D2SRAM1LPEN_Msk          RCC_AHB2LPENR_SRAM1LPEN_Msk
+#define RCC_AHB2LPENR_D2SRAM1LPEN              RCC_AHB2LPENR_SRAM1LPEN
+#define RCC_AHB2LPENR_D2SRAM2LPEN_Pos          RCC_AHB2LPENR_SRAM2LPEN_Pos
+#define RCC_AHB2LPENR_D2SRAM2LPEN_Msk          RCC_AHB2LPENR_SRAM2LPEN_Msk
+#define RCC_AHB2LPENR_D2SRAM2LPEN              RCC_AHB2LPENR_SRAM2LPEN
+#define RCC_AHB2LPENR_D2SRAM3LPEN_Pos          RCC_AHB2LPENR_SRAM3LPEN_Pos
+#define RCC_AHB2LPENR_D2SRAM3LPEN_Msk          RCC_AHB2LPENR_SRAM3LPEN_Msk
+#define RCC_AHB2LPENR_D2SRAM3LPEN              RCC_AHB2LPENR_SRAM3LPEN
+
+/********************  Bit definition for RCC_AHB4LPENR register  ******************/
+#define RCC_AHB4LPENR_GPIOALPEN_Pos            (0U)
+#define RCC_AHB4LPENR_GPIOALPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB4LPENR_GPIOALPEN                RCC_AHB4LPENR_GPIOALPEN_Msk
+#define RCC_AHB4LPENR_GPIOBLPEN_Pos            (1U)
+#define RCC_AHB4LPENR_GPIOBLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB4LPENR_GPIOBLPEN                RCC_AHB4LPENR_GPIOBLPEN_Msk
+#define RCC_AHB4LPENR_GPIOCLPEN_Pos            (2U)
+#define RCC_AHB4LPENR_GPIOCLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB4LPENR_GPIOCLPEN                RCC_AHB4LPENR_GPIOCLPEN_Msk
+#define RCC_AHB4LPENR_GPIODLPEN_Pos            (3U)
+#define RCC_AHB4LPENR_GPIODLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB4LPENR_GPIODLPEN                RCC_AHB4LPENR_GPIODLPEN_Msk
+#define RCC_AHB4LPENR_GPIOELPEN_Pos            (4U)
+#define RCC_AHB4LPENR_GPIOELPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB4LPENR_GPIOELPEN                RCC_AHB4LPENR_GPIOELPEN_Msk
+#define RCC_AHB4LPENR_GPIOFLPEN_Pos            (5U)
+#define RCC_AHB4LPENR_GPIOFLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB4LPENR_GPIOFLPEN                RCC_AHB4LPENR_GPIOFLPEN_Msk
+#define RCC_AHB4LPENR_GPIOGLPEN_Pos            (6U)
+#define RCC_AHB4LPENR_GPIOGLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB4LPENR_GPIOGLPEN                RCC_AHB4LPENR_GPIOGLPEN_Msk
+#define RCC_AHB4LPENR_GPIOHLPEN_Pos            (7U)
+#define RCC_AHB4LPENR_GPIOHLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB4LPENR_GPIOHLPEN                RCC_AHB4LPENR_GPIOHLPEN_Msk
+#define RCC_AHB4LPENR_GPIOILPEN_Pos            (8U)
+#define RCC_AHB4LPENR_GPIOILPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB4LPENR_GPIOILPEN                RCC_AHB4LPENR_GPIOILPEN_Msk
+#define RCC_AHB4LPENR_GPIOJLPEN_Pos            (9U)
+#define RCC_AHB4LPENR_GPIOJLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */
+#define RCC_AHB4LPENR_GPIOJLPEN                RCC_AHB4LPENR_GPIOJLPEN_Msk
+#define RCC_AHB4LPENR_GPIOKLPEN_Pos            (10U)
+#define RCC_AHB4LPENR_GPIOKLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */
+#define RCC_AHB4LPENR_GPIOKLPEN                RCC_AHB4LPENR_GPIOKLPEN_Msk
+#define RCC_AHB4LPENR_CRCLPEN_Pos              (19U)
+#define RCC_AHB4LPENR_CRCLPEN_Msk              (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos) /*!< 0x00080000 */
+#define RCC_AHB4LPENR_CRCLPEN                  RCC_AHB4LPENR_CRCLPEN_Msk
+#define RCC_AHB4LPENR_BDMALPEN_Pos             (21U)
+#define RCC_AHB4LPENR_BDMALPEN_Msk             (0x1UL << RCC_AHB4LPENR_BDMALPEN_Pos) /*!< 0x00200000 */
+#define RCC_AHB4LPENR_BDMALPEN                 RCC_AHB4LPENR_BDMALPEN_Msk
+#define RCC_AHB4LPENR_ADC3LPEN_Pos             (24U)
+#define RCC_AHB4LPENR_ADC3LPEN_Msk             (0x1UL << RCC_AHB4LPENR_ADC3LPEN_Pos) /*!< 0x01000000 */
+#define RCC_AHB4LPENR_ADC3LPEN                 RCC_AHB4LPENR_ADC3LPEN_Msk
+#define RCC_AHB4LPENR_BKPRAMLPEN_Pos           (28U)
+#define RCC_AHB4LPENR_BKPRAMLPEN_Msk           (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos) /*!< 0x10000000 */
+#define RCC_AHB4LPENR_BKPRAMLPEN               RCC_AHB4LPENR_BKPRAMLPEN_Msk
+#define RCC_AHB4LPENR_SRAM4LPEN_Pos            (29U)
+#define RCC_AHB4LPENR_SRAM4LPEN_Msk            (0x1UL << RCC_AHB4LPENR_SRAM4LPEN_Pos) /*!< 0x20000000 */
+#define RCC_AHB4LPENR_SRAM4LPEN                RCC_AHB4LPENR_SRAM4LPEN_Msk
+
+/* Legacy define */
+#define RCC_AHB4LPENR_D3SRAM1LPEN_Pos          RCC_AHB4LPENR_SRAM4LPEN_Pos
+#define RCC_AHB4LPENR_D3SRAM1LPEN_Msk          RCC_AHB4LPENR_SRAM4LPEN_Msk
+#define RCC_AHB4LPENR_D3SRAM1LPEN              RCC_AHB4LPENR_SRAM4LPEN
+/********************  Bit definition for RCC_APB3LPENR register  ******************/
+#define RCC_APB3LPENR_LTDCLPEN_Pos             (3U)
+#define RCC_APB3LPENR_LTDCLPEN_Msk             (0x1UL << RCC_APB3LPENR_LTDCLPEN_Pos) /*!< 0x00000008 */
+#define RCC_APB3LPENR_LTDCLPEN                 RCC_APB3LPENR_LTDCLPEN_Msk
+#define RCC_APB3LPENR_WWDG1LPEN_Pos            (6U)
+#define RCC_APB3LPENR_WWDG1LPEN_Msk            (0x1UL << RCC_APB3LPENR_WWDG1LPEN_Pos) /*!< 0x00000040 */
+#define RCC_APB3LPENR_WWDG1LPEN                RCC_APB3LPENR_WWDG1LPEN_Msk
+
+/********************  Bit definition for RCC_APB1LLPENR register  ******************/
+
+#define RCC_APB1LLPENR_TIM2LPEN_Pos            (0U)
+#define RCC_APB1LLPENR_TIM2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1LLPENR_TIM2LPEN                RCC_APB1LLPENR_TIM2LPEN_Msk
+#define RCC_APB1LLPENR_TIM3LPEN_Pos            (1U)
+#define RCC_APB1LLPENR_TIM3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1LLPENR_TIM3LPEN                RCC_APB1LLPENR_TIM3LPEN_Msk
+#define RCC_APB1LLPENR_TIM4LPEN_Pos            (2U)
+#define RCC_APB1LLPENR_TIM4LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1LLPENR_TIM4LPEN                RCC_APB1LLPENR_TIM4LPEN_Msk
+#define RCC_APB1LLPENR_TIM5LPEN_Pos            (3U)
+#define RCC_APB1LLPENR_TIM5LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
+#define RCC_APB1LLPENR_TIM5LPEN                RCC_APB1LLPENR_TIM5LPEN_Msk
+#define RCC_APB1LLPENR_TIM6LPEN_Pos            (4U)
+#define RCC_APB1LLPENR_TIM6LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1LLPENR_TIM6LPEN                RCC_APB1LLPENR_TIM6LPEN_Msk
+#define RCC_APB1LLPENR_TIM7LPEN_Pos            (5U)
+#define RCC_APB1LLPENR_TIM7LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1LLPENR_TIM7LPEN                RCC_APB1LLPENR_TIM7LPEN_Msk
+#define RCC_APB1LLPENR_TIM12LPEN_Pos           (6U)
+#define RCC_APB1LLPENR_TIM12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
+#define RCC_APB1LLPENR_TIM12LPEN               RCC_APB1LLPENR_TIM12LPEN_Msk
+#define RCC_APB1LLPENR_TIM13LPEN_Pos           (7U)
+#define RCC_APB1LLPENR_TIM13LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
+#define RCC_APB1LLPENR_TIM13LPEN               RCC_APB1LLPENR_TIM13LPEN_Msk
+#define RCC_APB1LLPENR_TIM14LPEN_Pos           (8U)
+#define RCC_APB1LLPENR_TIM14LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB1LLPENR_TIM14LPEN               RCC_APB1LLPENR_TIM14LPEN_Msk
+#define RCC_APB1LLPENR_LPTIM1LPEN_Pos          (9U)
+#define RCC_APB1LLPENR_LPTIM1LPEN_Msk          (0x1UL << RCC_APB1LLPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */
+#define RCC_APB1LLPENR_LPTIM1LPEN              RCC_APB1LLPENR_LPTIM1LPEN_Msk
+
+
+#define RCC_APB1LLPENR_SPI2LPEN_Pos            (14U)
+#define RCC_APB1LLPENR_SPI2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB1LLPENR_SPI2LPEN                RCC_APB1LLPENR_SPI2LPEN_Msk
+#define RCC_APB1LLPENR_SPI3LPEN_Pos            (15U)
+#define RCC_APB1LLPENR_SPI3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
+#define RCC_APB1LLPENR_SPI3LPEN                RCC_APB1LLPENR_SPI3LPEN_Msk
+#define RCC_APB1LLPENR_SPDIFRXLPEN_Pos         (16U)
+#define RCC_APB1LLPENR_SPDIFRXLPEN_Msk         (0x1UL << RCC_APB1LLPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */
+#define RCC_APB1LLPENR_SPDIFRXLPEN             RCC_APB1LLPENR_SPDIFRXLPEN_Msk
+#define RCC_APB1LLPENR_USART2LPEN_Pos          (17U)
+#define RCC_APB1LLPENR_USART2LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1LLPENR_USART2LPEN              RCC_APB1LLPENR_USART2LPEN_Msk
+#define RCC_APB1LLPENR_USART3LPEN_Pos          (18U)
+#define RCC_APB1LLPENR_USART3LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1LLPENR_USART3LPEN              RCC_APB1LLPENR_USART3LPEN_Msk
+#define RCC_APB1LLPENR_UART4LPEN_Pos           (19U)
+#define RCC_APB1LLPENR_UART4LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos) /*!< 0x00080000 */
+#define RCC_APB1LLPENR_UART4LPEN               RCC_APB1LLPENR_UART4LPEN_Msk
+#define RCC_APB1LLPENR_UART5LPEN_Pos           (20U)
+#define RCC_APB1LLPENR_UART5LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos) /*!< 0x00100000 */
+#define RCC_APB1LLPENR_UART5LPEN               RCC_APB1LLPENR_UART5LPEN_Msk
+#define RCC_APB1LLPENR_I2C1LPEN_Pos            (21U)
+#define RCC_APB1LLPENR_I2C1LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1LLPENR_I2C1LPEN                RCC_APB1LLPENR_I2C1LPEN_Msk
+#define RCC_APB1LLPENR_I2C2LPEN_Pos            (22U)
+#define RCC_APB1LLPENR_I2C2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_APB1LLPENR_I2C2LPEN                RCC_APB1LLPENR_I2C2LPEN_Msk
+#define RCC_APB1LLPENR_I2C3LPEN_Pos            (23U)
+#define RCC_APB1LLPENR_I2C3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1LLPENR_I2C3LPEN                RCC_APB1LLPENR_I2C3LPEN_Msk
+#define RCC_APB1LLPENR_CECLPEN_Pos             (27U)
+#define RCC_APB1LLPENR_CECLPEN_Msk             (0x1UL << RCC_APB1LLPENR_CECLPEN_Pos) /*!< 0x08000000 */
+#define RCC_APB1LLPENR_CECLPEN                 RCC_APB1LLPENR_CECLPEN_Msk
+#define RCC_APB1LLPENR_DAC12LPEN_Pos           (29U)
+#define RCC_APB1LLPENR_DAC12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_DAC12LPEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1LLPENR_DAC12LPEN               RCC_APB1LLPENR_DAC12LPEN_Msk
+#define RCC_APB1LLPENR_UART7LPEN_Pos           (30U)
+#define RCC_APB1LLPENR_UART7LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART7LPEN_Pos) /*!< 0x40000000 */
+#define RCC_APB1LLPENR_UART7LPEN               RCC_APB1LLPENR_UART7LPEN_Msk
+#define RCC_APB1LLPENR_UART8LPEN_Pos           (31U)
+#define RCC_APB1LLPENR_UART8LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART8LPEN_Pos) /*!< 0x80000000 */
+#define RCC_APB1LLPENR_UART8LPEN               RCC_APB1LLPENR_UART8LPEN_Msk
+
+/* Legacy define */
+#define RCC_APB1LLPENR_HDMICECEN_Pos           RCC_APB1LLPENR_CECLPEN_Pos
+#define RCC_APB1LLPENR_HDMICECEN_Msk           RCC_APB1LLPENR_CECLPEN_Msk
+#define RCC_APB1LLPENR_HDMICECEN               RCC_APB1LLPENR_CECLPEN
+/********************  Bit definition for RCC_APB1HLPENR register  ******************/
+#define RCC_APB1HLPENR_CRSLPEN_Pos             (1U)
+#define RCC_APB1HLPENR_CRSLPEN_Msk             (0x1UL << RCC_APB1HLPENR_CRSLPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1HLPENR_CRSLPEN                 RCC_APB1HLPENR_CRSLPEN_Msk
+#define RCC_APB1HLPENR_SWPMILPEN_Pos           (2U)
+#define RCC_APB1HLPENR_SWPMILPEN_Msk           (0x1UL << RCC_APB1HLPENR_SWPMILPEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1HLPENR_SWPMILPEN               RCC_APB1HLPENR_SWPMILPEN_Msk
+#define RCC_APB1HLPENR_OPAMPLPEN_Pos           (4U)
+#define RCC_APB1HLPENR_OPAMPLPEN_Msk           (0x1UL << RCC_APB1HLPENR_OPAMPLPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1HLPENR_OPAMPLPEN               RCC_APB1HLPENR_OPAMPLPEN_Msk
+#define RCC_APB1HLPENR_MDIOSLPEN_Pos           (5U)
+#define RCC_APB1HLPENR_MDIOSLPEN_Msk           (0x1UL << RCC_APB1HLPENR_MDIOSLPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1HLPENR_MDIOSLPEN               RCC_APB1HLPENR_MDIOSLPEN_Msk
+#define RCC_APB1HLPENR_FDCANLPEN_Pos           (8U)
+#define RCC_APB1HLPENR_FDCANLPEN_Msk           (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB1HLPENR_FDCANLPEN               RCC_APB1HLPENR_FDCANLPEN_Msk
+
+/********************  Bit definition for RCC_APB2LPENR register  ******************/
+#define RCC_APB2LPENR_TIM1LPEN_Pos             (0U)
+#define RCC_APB2LPENR_TIM1LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2LPENR_TIM1LPEN                 RCC_APB2LPENR_TIM1LPEN_Msk
+#define RCC_APB2LPENR_TIM8LPEN_Pos             (1U)
+#define RCC_APB2LPENR_TIM8LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB2LPENR_TIM8LPEN                 RCC_APB2LPENR_TIM8LPEN_Msk
+#define RCC_APB2LPENR_USART1LPEN_Pos           (4U)
+#define RCC_APB2LPENR_USART1LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB2LPENR_USART1LPEN               RCC_APB2LPENR_USART1LPEN_Msk
+#define RCC_APB2LPENR_USART6LPEN_Pos           (5U)
+#define RCC_APB2LPENR_USART6LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2LPENR_USART6LPEN               RCC_APB2LPENR_USART6LPEN_Msk
+#define RCC_APB2LPENR_SPI1LPEN_Pos             (12U)
+#define RCC_APB2LPENR_SPI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2LPENR_SPI1LPEN                 RCC_APB2LPENR_SPI1LPEN_Msk
+#define RCC_APB2LPENR_SPI4LPEN_Pos             (13U)
+#define RCC_APB2LPENR_SPI4LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
+#define RCC_APB2LPENR_SPI4LPEN                 RCC_APB2LPENR_SPI4LPEN_Msk
+#define RCC_APB2LPENR_TIM15LPEN_Pos            (16U)
+#define RCC_APB2LPENR_TIM15LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */
+#define RCC_APB2LPENR_TIM15LPEN                RCC_APB2LPENR_TIM15LPEN_Msk
+#define RCC_APB2LPENR_TIM16LPEN_Pos            (17U)
+#define RCC_APB2LPENR_TIM16LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB2LPENR_TIM16LPEN                RCC_APB2LPENR_TIM16LPEN_Msk
+#define RCC_APB2LPENR_TIM17LPEN_Pos            (18U)
+#define RCC_APB2LPENR_TIM17LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB2LPENR_TIM17LPEN                RCC_APB2LPENR_TIM17LPEN_Msk
+#define RCC_APB2LPENR_SPI5LPEN_Pos             (20U)
+#define RCC_APB2LPENR_SPI5LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
+#define RCC_APB2LPENR_SPI5LPEN                 RCC_APB2LPENR_SPI5LPEN_Msk
+#define RCC_APB2LPENR_SAI1LPEN_Pos             (22U)
+#define RCC_APB2LPENR_SAI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2LPENR_SAI1LPEN                 RCC_APB2LPENR_SAI1LPEN_Msk
+#define RCC_APB2LPENR_SAI2LPEN_Pos             (23U)
+#define RCC_APB2LPENR_SAI2LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */
+#define RCC_APB2LPENR_SAI2LPEN                 RCC_APB2LPENR_SAI2LPEN_Msk
+#define RCC_APB2LPENR_SAI3LPEN_Pos             (24U)
+#define RCC_APB2LPENR_SAI3LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI3LPEN_Pos) /*!< 0x01000000 */
+#define RCC_APB2LPENR_SAI3LPEN                 RCC_APB2LPENR_SAI3LPEN_Msk
+#define RCC_APB2LPENR_DFSDM1LPEN_Pos           (28U)
+#define RCC_APB2LPENR_DFSDM1LPEN_Msk           (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x10000000 */
+#define RCC_APB2LPENR_DFSDM1LPEN               RCC_APB2LPENR_DFSDM1LPEN_Msk
+#define RCC_APB2LPENR_HRTIMLPEN_Pos            (29U)
+#define RCC_APB2LPENR_HRTIMLPEN_Msk            (0x1UL << RCC_APB2LPENR_HRTIMLPEN_Pos) /*!< 0x20000000 */
+#define RCC_APB2LPENR_HRTIMLPEN                RCC_APB2LPENR_HRTIMLPEN_Msk
+
+/********************  Bit definition for RCC_APB4LPENR register  ******************/
+#define RCC_APB4LPENR_SYSCFGLPEN_Pos           (1U)
+#define RCC_APB4LPENR_SYSCFGLPEN_Msk           (0x1UL << RCC_APB4LPENR_SYSCFGLPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB4LPENR_SYSCFGLPEN               RCC_APB4LPENR_SYSCFGLPEN_Msk
+#define RCC_APB4LPENR_LPUART1LPEN_Pos          (3U)
+#define RCC_APB4LPENR_LPUART1LPEN_Msk          (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos) /*!< 0x00000008 */
+#define RCC_APB4LPENR_LPUART1LPEN              RCC_APB4LPENR_LPUART1LPEN_Msk
+#define RCC_APB4LPENR_SPI6LPEN_Pos             (5U)
+#define RCC_APB4LPENR_SPI6LPEN_Msk             (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB4LPENR_SPI6LPEN                 RCC_APB4LPENR_SPI6LPEN_Msk
+#define RCC_APB4LPENR_I2C4LPEN_Pos             (7U)
+#define RCC_APB4LPENR_I2C4LPEN_Msk             (0x1UL << RCC_APB4LPENR_I2C4LPEN_Pos) /*!< 0x00000080 */
+#define RCC_APB4LPENR_I2C4LPEN                 RCC_APB4LPENR_I2C4LPEN_Msk
+#define RCC_APB4LPENR_LPTIM2LPEN_Pos           (9U)
+#define RCC_APB4LPENR_LPTIM2LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos) /*!< 0x00000200 */
+#define RCC_APB4LPENR_LPTIM2LPEN               RCC_APB4LPENR_LPTIM2LPEN_Msk
+#define RCC_APB4LPENR_LPTIM3LPEN_Pos           (10U)
+#define RCC_APB4LPENR_LPTIM3LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos) /*!< 0x00000400 */
+#define RCC_APB4LPENR_LPTIM3LPEN               RCC_APB4LPENR_LPTIM3LPEN_Msk
+#define RCC_APB4LPENR_LPTIM4LPEN_Pos           (11U)
+#define RCC_APB4LPENR_LPTIM4LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM4LPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB4LPENR_LPTIM4LPEN               RCC_APB4LPENR_LPTIM4LPEN_Msk
+#define RCC_APB4LPENR_LPTIM5LPEN_Pos           (12U)
+#define RCC_APB4LPENR_LPTIM5LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM5LPEN_Pos) /*!< 0x00001000 */
+#define RCC_APB4LPENR_LPTIM5LPEN               RCC_APB4LPENR_LPTIM5LPEN_Msk
+#define RCC_APB4LPENR_COMP12LPEN_Pos           (14U)
+#define RCC_APB4LPENR_COMP12LPEN_Msk           (0x1UL << RCC_APB4LPENR_COMP12LPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB4LPENR_COMP12LPEN               RCC_APB4LPENR_COMP12LPEN_Msk
+#define RCC_APB4LPENR_VREFLPEN_Pos             (15U)
+#define RCC_APB4LPENR_VREFLPEN_Msk             (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos) /*!< 0x00008000 */
+#define RCC_APB4LPENR_VREFLPEN                 RCC_APB4LPENR_VREFLPEN_Msk
+#define RCC_APB4LPENR_RTCAPBLPEN_Pos           (16U)
+#define RCC_APB4LPENR_RTCAPBLPEN_Msk           (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos) /*!< 0x00010000 */
+#define RCC_APB4LPENR_RTCAPBLPEN               RCC_APB4LPENR_RTCAPBLPEN_Msk
+#define RCC_APB4LPENR_SAI4LPEN_Pos             (21U)
+#define RCC_APB4LPENR_SAI4LPEN_Msk             (0x1UL << RCC_APB4LPENR_SAI4LPEN_Pos) /*!< 0x00200000 */
+#define RCC_APB4LPENR_SAI4LPEN                 RCC_APB4LPENR_SAI4LPEN_Msk
+
+
+/********************  Bit definition for RCC_RSR register  *******************/
+#define RCC_RSR_RMVF_Pos                       (16U)
+#define RCC_RSR_RMVF_Msk                       (0x1UL << RCC_RSR_RMVF_Pos)     /*!< 0x00010000 */
+#define RCC_RSR_RMVF                           RCC_RSR_RMVF_Msk
+#define RCC_RSR_CPURSTF_Pos                    (17U)
+#define RCC_RSR_CPURSTF_Msk                    (0x1UL << RCC_RSR_CPURSTF_Pos)  /*!< 0x00020000 */
+#define RCC_RSR_CPURSTF                        RCC_RSR_CPURSTF_Msk
+#define RCC_RSR_D1RSTF_Pos                     (19U)
+#define RCC_RSR_D1RSTF_Msk                     (0x1UL << RCC_RSR_D1RSTF_Pos)   /*!< 0x00080000 */
+#define RCC_RSR_D1RSTF                         RCC_RSR_D1RSTF_Msk
+#define RCC_RSR_D2RSTF_Pos                     (20U)
+#define RCC_RSR_D2RSTF_Msk                     (0x1UL << RCC_RSR_D2RSTF_Pos)   /*!< 0x00100000 */
+#define RCC_RSR_D2RSTF                         RCC_RSR_D2RSTF_Msk
+#define RCC_RSR_BORRSTF_Pos                    (21U)
+#define RCC_RSR_BORRSTF_Msk                    (0x1UL << RCC_RSR_BORRSTF_Pos)  /*!< 0x00200000 */
+#define RCC_RSR_BORRSTF                        RCC_RSR_BORRSTF_Msk
+#define RCC_RSR_PINRSTF_Pos                    (22U)
+#define RCC_RSR_PINRSTF_Msk                    (0x1UL << RCC_RSR_PINRSTF_Pos)  /*!< 0x00400000 */
+#define RCC_RSR_PINRSTF                        RCC_RSR_PINRSTF_Msk
+#define RCC_RSR_PORRSTF_Pos                    (23U)
+#define RCC_RSR_PORRSTF_Msk                    (0x1UL << RCC_RSR_PORRSTF_Pos)  /*!< 0x00800000 */
+#define RCC_RSR_PORRSTF                        RCC_RSR_PORRSTF_Msk
+#define RCC_RSR_SFTRSTF_Pos                    (24U)
+#define RCC_RSR_SFTRSTF_Msk                    (0x1UL << RCC_RSR_SFTRSTF_Pos)  /*!< 0x01000000 */
+#define RCC_RSR_SFTRSTF                        RCC_RSR_SFTRSTF_Msk
+#define RCC_RSR_IWDG1RSTF_Pos                  (26U)
+#define RCC_RSR_IWDG1RSTF_Msk                  (0x1UL << RCC_RSR_IWDG1RSTF_Pos) /*!< 0x04000000 */
+#define RCC_RSR_IWDG1RSTF                      RCC_RSR_IWDG1RSTF_Msk
+#define RCC_RSR_WWDG1RSTF_Pos                  (28U)
+#define RCC_RSR_WWDG1RSTF_Msk                  (0x1UL << RCC_RSR_WWDG1RSTF_Pos) /*!< 0x10000000 */
+#define RCC_RSR_WWDG1RSTF                      RCC_RSR_WWDG1RSTF_Msk
+
+#define RCC_RSR_LPWRRSTF_Pos                   (30U)
+#define RCC_RSR_LPWRRSTF_Msk                   (0x1UL << RCC_RSR_LPWRRSTF_Pos) /*!< 0x40000000 */
+#define RCC_RSR_LPWRRSTF                       RCC_RSR_LPWRRSTF_Msk
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    RNG                                     */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RNG_CR register  *******************/
+#define RNG_CR_RNGEN_Pos    (2U)
+#define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                        /*!< 0x00000004 */
+#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk
+#define RNG_CR_IE_Pos       (3U)
+#define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                           /*!< 0x00000008 */
+#define RNG_CR_IE           RNG_CR_IE_Msk
+#define RNG_CR_CED_Pos      (5U)
+#define RNG_CR_CED_Msk      (0x1UL << RNG_CR_CED_Pos)                          /*!< 0x00000020 */
+#define RNG_CR_CED          RNG_CR_CED_Msk
+
+/********************  Bits definition for RNG_SR register  *******************/
+#define RNG_SR_DRDY_Pos     (0U)
+#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                         /*!< 0x00000001 */
+#define RNG_SR_DRDY         RNG_SR_DRDY_Msk
+#define RNG_SR_CECS_Pos     (1U)
+#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                         /*!< 0x00000002 */
+#define RNG_SR_CECS         RNG_SR_CECS_Msk
+#define RNG_SR_SECS_Pos     (2U)
+#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                         /*!< 0x00000004 */
+#define RNG_SR_SECS         RNG_SR_SECS_Msk
+#define RNG_SR_CEIS_Pos     (5U)
+#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                         /*!< 0x00000020 */
+#define RNG_SR_CEIS         RNG_SR_CEIS_Msk
+#define RNG_SR_SEIS_Pos     (6U)
+#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                         /*!< 0x00000040 */
+#define RNG_SR_SEIS         RNG_SR_SEIS_Msk
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RTC_TR register  *******************/
+#define RTC_TR_PM_Pos                  (22U)
+#define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                /*!< 0x00400000 */
+#define RTC_TR_PM                      RTC_TR_PM_Msk
+#define RTC_TR_HT_Pos                  (20U)
+#define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                /*!< 0x00300000 */
+#define RTC_TR_HT                      RTC_TR_HT_Msk
+#define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                 /*!< 0x00100000 */
+#define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                 /*!< 0x00200000 */
+#define RTC_TR_HU_Pos                  (16U)
+#define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                /*!< 0x000F0000 */
+#define RTC_TR_HU                      RTC_TR_HU_Msk
+#define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                 /*!< 0x00010000 */
+#define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                 /*!< 0x00020000 */
+#define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                 /*!< 0x00040000 */
+#define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                 /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos                 (12U)
+#define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)               /*!< 0x00007000 */
+#define RTC_TR_MNT                     RTC_TR_MNT_Msk
+#define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)                /*!< 0x00001000 */
+#define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)                /*!< 0x00002000 */
+#define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)                /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos                 (8U)
+#define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)               /*!< 0x00000F00 */
+#define RTC_TR_MNU                     RTC_TR_MNU_Msk
+#define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)                /*!< 0x00000100 */
+#define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)                /*!< 0x00000200 */
+#define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)                /*!< 0x00000400 */
+#define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)                /*!< 0x00000800 */
+#define RTC_TR_ST_Pos                  (4U)
+#define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                /*!< 0x00000070 */
+#define RTC_TR_ST                      RTC_TR_ST_Msk
+#define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                 /*!< 0x00000010 */
+#define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                 /*!< 0x00000020 */
+#define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                 /*!< 0x00000040 */
+#define RTC_TR_SU_Pos                  (0U)
+#define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                /*!< 0x0000000F */
+#define RTC_TR_SU                      RTC_TR_SU_Msk
+#define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                 /*!< 0x00000001 */
+#define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                 /*!< 0x00000002 */
+#define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                 /*!< 0x00000004 */
+#define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                 /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_DR register  *******************/
+#define RTC_DR_YT_Pos                  (20U)
+#define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                /*!< 0x00F00000 */
+#define RTC_DR_YT                      RTC_DR_YT_Msk
+#define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                 /*!< 0x00100000 */
+#define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                 /*!< 0x00200000 */
+#define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                 /*!< 0x00400000 */
+#define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                 /*!< 0x00800000 */
+#define RTC_DR_YU_Pos                  (16U)
+#define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                /*!< 0x000F0000 */
+#define RTC_DR_YU                      RTC_DR_YU_Msk
+#define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                 /*!< 0x00010000 */
+#define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                 /*!< 0x00020000 */
+#define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                 /*!< 0x00040000 */
+#define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                 /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos                 (13U)
+#define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)               /*!< 0x0000E000 */
+#define RTC_DR_WDU                     RTC_DR_WDU_Msk
+#define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)                /*!< 0x00002000 */
+#define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)                /*!< 0x00004000 */
+#define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)                /*!< 0x00008000 */
+#define RTC_DR_MT_Pos                  (12U)
+#define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                /*!< 0x00001000 */
+#define RTC_DR_MT                      RTC_DR_MT_Msk
+#define RTC_DR_MU_Pos                  (8U)
+#define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                /*!< 0x00000F00 */
+#define RTC_DR_MU                      RTC_DR_MU_Msk
+#define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                 /*!< 0x00000100 */
+#define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                 /*!< 0x00000200 */
+#define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                 /*!< 0x00000400 */
+#define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                 /*!< 0x00000800 */
+#define RTC_DR_DT_Pos                  (4U)
+#define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                /*!< 0x00000030 */
+#define RTC_DR_DT                      RTC_DR_DT_Msk
+#define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                 /*!< 0x00000010 */
+#define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                 /*!< 0x00000020 */
+#define RTC_DR_DU_Pos                  (0U)
+#define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                /*!< 0x0000000F */
+#define RTC_DR_DU                      RTC_DR_DU_Msk
+#define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                 /*!< 0x00000001 */
+#define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                 /*!< 0x00000002 */
+#define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                 /*!< 0x00000004 */
+#define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                 /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_CR register  *******************/
+#define RTC_CR_ITSE_Pos                (24U)
+#define RTC_CR_ITSE_Msk                (0x1UL << RTC_CR_ITSE_Pos)              /*!< 0x01000000 */
+#define RTC_CR_ITSE                    RTC_CR_ITSE_Msk
+#define RTC_CR_COE_Pos                 (23U)
+#define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)               /*!< 0x00800000 */
+#define RTC_CR_COE                     RTC_CR_COE_Msk
+#define RTC_CR_OSEL_Pos                (21U)
+#define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)              /*!< 0x00600000 */
+#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk
+#define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */
+#define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */
+#define RTC_CR_POL_Pos                 (20U)
+#define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)               /*!< 0x00100000 */
+#define RTC_CR_POL                     RTC_CR_POL_Msk
+#define RTC_CR_COSEL_Pos               (19U)
+#define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)             /*!< 0x00080000 */
+#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk
+#define RTC_CR_BKP_Pos                 (18U)
+#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)               /*!< 0x00040000 */
+#define RTC_CR_BKP                     RTC_CR_BKP_Msk
+#define RTC_CR_SUB1H_Pos               (17U)
+#define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)             /*!< 0x00020000 */
+#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk
+#define RTC_CR_ADD1H_Pos               (16U)
+#define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)             /*!< 0x00010000 */
+#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk
+#define RTC_CR_TSIE_Pos                (15U)
+#define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)              /*!< 0x00008000 */
+#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk
+#define RTC_CR_WUTIE_Pos               (14U)
+#define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)             /*!< 0x00004000 */
+#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk
+#define RTC_CR_ALRBIE_Pos              (13U)
+#define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)            /*!< 0x00002000 */
+#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk
+#define RTC_CR_ALRAIE_Pos              (12U)
+#define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)            /*!< 0x00001000 */
+#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk
+#define RTC_CR_TSE_Pos                 (11U)
+#define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)               /*!< 0x00000800 */
+#define RTC_CR_TSE                     RTC_CR_TSE_Msk
+#define RTC_CR_WUTE_Pos                (10U)
+#define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)              /*!< 0x00000400 */
+#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk
+#define RTC_CR_ALRBE_Pos               (9U)
+#define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)             /*!< 0x00000200 */
+#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk
+#define RTC_CR_ALRAE_Pos               (8U)
+#define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)             /*!< 0x00000100 */
+#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk
+#define RTC_CR_FMT_Pos                 (6U)
+#define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)               /*!< 0x00000040 */
+#define RTC_CR_FMT                     RTC_CR_FMT_Msk
+#define RTC_CR_BYPSHAD_Pos             (5U)
+#define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)           /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk
+#define RTC_CR_REFCKON_Pos             (4U)
+#define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)           /*!< 0x00000010 */
+#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk
+#define RTC_CR_TSEDGE_Pos              (3U)
+#define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)            /*!< 0x00000008 */
+#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk
+#define RTC_CR_WUCKSEL_Pos             (0U)
+#define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk
+#define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */
+
+/********************  Bits definition for RTC_ISR register  ******************/
+#define RTC_ISR_ITSF_Pos               (17U)
+#define RTC_ISR_ITSF_Msk               (0x1UL << RTC_ISR_ITSF_Pos)             /*!< 0x00020000 */
+#define RTC_ISR_ITSF                   RTC_ISR_ITSF_Msk
+#define RTC_ISR_RECALPF_Pos            (16U)
+#define RTC_ISR_RECALPF_Msk            (0x1UL << RTC_ISR_RECALPF_Pos)          /*!< 0x00010000 */
+#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk
+#define RTC_ISR_TAMP3F_Pos             (15U)
+#define RTC_ISR_TAMP3F_Msk             (0x1UL << RTC_ISR_TAMP3F_Pos)           /*!< 0x00008000 */
+#define RTC_ISR_TAMP3F                 RTC_ISR_TAMP3F_Msk
+#define RTC_ISR_TAMP2F_Pos             (14U)
+#define RTC_ISR_TAMP2F_Msk             (0x1UL << RTC_ISR_TAMP2F_Pos)           /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk
+#define RTC_ISR_TAMP1F_Pos             (13U)
+#define RTC_ISR_TAMP1F_Msk             (0x1UL << RTC_ISR_TAMP1F_Pos)           /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk
+#define RTC_ISR_TSOVF_Pos              (12U)
+#define RTC_ISR_TSOVF_Msk              (0x1UL << RTC_ISR_TSOVF_Pos)            /*!< 0x00001000 */
+#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk
+#define RTC_ISR_TSF_Pos                (11U)
+#define RTC_ISR_TSF_Msk                (0x1UL << RTC_ISR_TSF_Pos)              /*!< 0x00000800 */
+#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk
+#define RTC_ISR_WUTF_Pos               (10U)
+#define RTC_ISR_WUTF_Msk               (0x1UL << RTC_ISR_WUTF_Pos)             /*!< 0x00000400 */
+#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk
+#define RTC_ISR_ALRBF_Pos              (9U)
+#define RTC_ISR_ALRBF_Msk              (0x1UL << RTC_ISR_ALRBF_Pos)            /*!< 0x00000200 */
+#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk
+#define RTC_ISR_ALRAF_Pos              (8U)
+#define RTC_ISR_ALRAF_Msk              (0x1UL << RTC_ISR_ALRAF_Pos)            /*!< 0x00000100 */
+#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk
+#define RTC_ISR_INIT_Pos               (7U)
+#define RTC_ISR_INIT_Msk               (0x1UL << RTC_ISR_INIT_Pos)             /*!< 0x00000080 */
+#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk
+#define RTC_ISR_INITF_Pos              (6U)
+#define RTC_ISR_INITF_Msk              (0x1UL << RTC_ISR_INITF_Pos)            /*!< 0x00000040 */
+#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk
+#define RTC_ISR_RSF_Pos                (5U)
+#define RTC_ISR_RSF_Msk                (0x1UL << RTC_ISR_RSF_Pos)              /*!< 0x00000020 */
+#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk
+#define RTC_ISR_INITS_Pos              (4U)
+#define RTC_ISR_INITS_Msk              (0x1UL << RTC_ISR_INITS_Pos)            /*!< 0x00000010 */
+#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk
+#define RTC_ISR_SHPF_Pos               (3U)
+#define RTC_ISR_SHPF_Msk               (0x1UL << RTC_ISR_SHPF_Pos)             /*!< 0x00000008 */
+#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk
+#define RTC_ISR_WUTWF_Pos              (2U)
+#define RTC_ISR_WUTWF_Msk              (0x1UL << RTC_ISR_WUTWF_Pos)            /*!< 0x00000004 */
+#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk
+#define RTC_ISR_ALRBWF_Pos             (1U)
+#define RTC_ISR_ALRBWF_Msk             (0x1UL << RTC_ISR_ALRBWF_Pos)           /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk
+#define RTC_ISR_ALRAWF_Pos             (0U)
+#define RTC_ISR_ALRAWF_Msk             (0x1UL << RTC_ISR_ALRAWF_Pos)           /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk
+
+/********************  Bits definition for RTC_PRER register  *****************/
+#define RTC_PRER_PREDIV_A_Pos          (16U)
+#define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)       /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk
+#define RTC_PRER_PREDIV_S_Pos          (0U)
+#define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)     /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk
+
+/********************  Bits definition for RTC_WUTR register  *****************/
+#define RTC_WUTR_WUT_Pos               (0U)
+#define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)          /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk
+
+/********************  Bits definition for RTC_ALRMAR register  ***************/
+#define RTC_ALRMAR_MSK4_Pos            (31U)
+#define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)          /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk
+#define RTC_ALRMAR_WDSEL_Pos           (30U)
+#define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)         /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk
+#define RTC_ALRMAR_DT_Pos              (28U)
+#define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)            /*!< 0x30000000 */
+#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk
+#define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos              (24U)
+#define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)            /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk
+#define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos            (23U)
+#define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)          /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk
+#define RTC_ALRMAR_PM_Pos              (22U)
+#define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)            /*!< 0x00400000 */
+#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk
+#define RTC_ALRMAR_HT_Pos              (20U)
+#define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00300000 */
+#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk
+#define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos              (16U)
+#define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)            /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk
+#define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos            (15U)
+#define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)          /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk
+#define RTC_ALRMAR_MNT_Pos             (12U)
+#define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk
+#define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos             (8U)
+#define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk
+#define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos            (7U)
+#define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)          /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk
+#define RTC_ALRMAR_ST_Pos              (4U)
+#define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000070 */
+#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk
+#define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos              (0U)
+#define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)            /*!< 0x0000000F */
+#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk
+#define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_ALRMBR register  ***************/
+#define RTC_ALRMBR_MSK4_Pos            (31U)
+#define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)          /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk
+#define RTC_ALRMBR_WDSEL_Pos           (30U)
+#define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)         /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk
+#define RTC_ALRMBR_DT_Pos              (28U)
+#define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)            /*!< 0x30000000 */
+#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk
+#define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos              (24U)
+#define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)            /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk
+#define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos            (23U)
+#define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)          /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk
+#define RTC_ALRMBR_PM_Pos              (22U)
+#define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)            /*!< 0x00400000 */
+#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk
+#define RTC_ALRMBR_HT_Pos              (20U)
+#define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00300000 */
+#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk
+#define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos              (16U)
+#define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)            /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk
+#define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos            (15U)
+#define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)          /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk
+#define RTC_ALRMBR_MNT_Pos             (12U)
+#define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk
+#define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos             (8U)
+#define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk
+#define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos            (7U)
+#define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)          /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk
+#define RTC_ALRMBR_ST_Pos              (4U)
+#define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000070 */
+#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk
+#define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos              (0U)
+#define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)            /*!< 0x0000000F */
+#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk
+#define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_WPR register  ******************/
+#define RTC_WPR_KEY_Pos                (0U)
+#define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)             /*!< 0x000000FF */
+#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk
+
+/********************  Bits definition for RTC_SSR register  ******************/
+#define RTC_SSR_SS_Pos                 (0U)
+#define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)            /*!< 0x0000FFFF */
+#define RTC_SSR_SS                     RTC_SSR_SS_Msk
+
+/********************  Bits definition for RTC_SHIFTR register  ***************/
+#define RTC_SHIFTR_SUBFS_Pos           (0U)
+#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)      /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk
+#define RTC_SHIFTR_ADD1S_Pos           (31U)
+#define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)         /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk
+
+/********************  Bits definition for RTC_TSTR register  *****************/
+#define RTC_TSTR_PM_Pos                (22U)
+#define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)              /*!< 0x00400000 */
+#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk
+#define RTC_TSTR_HT_Pos                (20U)
+#define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)              /*!< 0x00300000 */
+#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk
+#define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */
+#define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos                (16U)
+#define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)              /*!< 0x000F0000 */
+#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk
+#define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */
+#define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */
+#define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */
+#define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos               (12U)
+#define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)             /*!< 0x00007000 */
+#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk
+#define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos               (8U)
+#define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)             /*!< 0x00000F00 */
+#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk
+#define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos                (4U)
+#define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)              /*!< 0x00000070 */
+#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk
+#define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */
+#define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */
+#define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos                (0U)
+#define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)              /*!< 0x0000000F */
+#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk
+#define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */
+#define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */
+#define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */
+#define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_TSDR register  *****************/
+#define RTC_TSDR_WDU_Pos               (13U)
+#define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)             /*!< 0x0000E000 */
+#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk
+#define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos                (12U)
+#define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)              /*!< 0x00001000 */
+#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk
+#define RTC_TSDR_MU_Pos                (8U)
+#define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)              /*!< 0x00000F00 */
+#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk
+#define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */
+#define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */
+#define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */
+#define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos                (4U)
+#define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)              /*!< 0x00000030 */
+#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk
+#define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */
+#define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos                (0U)
+#define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)              /*!< 0x0000000F */
+#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk
+#define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */
+#define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */
+#define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */
+#define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_TSSSR register  ****************/
+#define RTC_TSSSR_SS_Pos               (0U)
+#define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)          /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk
+
+/********************  Bits definition for RTC_CALR register  *****************/
+#define RTC_CALR_CALP_Pos              (15U)
+#define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)            /*!< 0x00008000 */
+#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk
+#define RTC_CALR_CALW8_Pos             (14U)
+#define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)           /*!< 0x00004000 */
+#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk
+#define RTC_CALR_CALW16_Pos            (13U)
+#define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)          /*!< 0x00002000 */
+#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk
+#define RTC_CALR_CALM_Pos              (0U)
+#define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)          /*!< 0x000001FF */
+#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk
+#define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */
+#define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */
+#define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */
+#define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */
+#define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */
+#define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */
+#define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */
+#define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */
+#define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */
+
+/********************  Bits definition for RTC_TAMPCR register  ***************/
+#define RTC_TAMPCR_TAMP3MF_Pos         (24U)
+#define RTC_TAMPCR_TAMP3MF_Msk         (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)       /*!< 0x01000000 */
+#define RTC_TAMPCR_TAMP3MF             RTC_TAMPCR_TAMP3MF_Msk
+#define RTC_TAMPCR_TAMP3NOERASE_Pos    (23U)
+#define RTC_TAMPCR_TAMP3NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)  /*!< 0x00800000 */
+#define RTC_TAMPCR_TAMP3NOERASE        RTC_TAMPCR_TAMP3NOERASE_Msk
+#define RTC_TAMPCR_TAMP3IE_Pos         (22U)
+#define RTC_TAMPCR_TAMP3IE_Msk         (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)       /*!< 0x00400000 */
+#define RTC_TAMPCR_TAMP3IE             RTC_TAMPCR_TAMP3IE_Msk
+#define RTC_TAMPCR_TAMP2MF_Pos         (21U)
+#define RTC_TAMPCR_TAMP2MF_Msk         (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)       /*!< 0x00200000 */
+#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk
+#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)
+#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)  /*!< 0x00100000 */
+#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk
+#define RTC_TAMPCR_TAMP2IE_Pos         (19U)
+#define RTC_TAMPCR_TAMP2IE_Msk         (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)       /*!< 0x00080000 */
+#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk
+#define RTC_TAMPCR_TAMP1MF_Pos         (18U)
+#define RTC_TAMPCR_TAMP1MF_Msk         (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)       /*!< 0x00040000 */
+#define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk
+#define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)
+#define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)  /*!< 0x00020000 */
+#define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk
+#define RTC_TAMPCR_TAMP1IE_Pos         (16U)
+#define RTC_TAMPCR_TAMP1IE_Msk         (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)       /*!< 0x00010000 */
+#define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk
+#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)
+#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)     /*!< 0x00008000 */
+#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk
+#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)
+#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)      /*!< 0x00006000 */
+#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk
+#define RTC_TAMPCR_TAMPPRCH_0          (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */
+#define RTC_TAMPCR_TAMPPRCH_1          (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */
+#define RTC_TAMPCR_TAMPFLT_Pos         (11U)
+#define RTC_TAMPCR_TAMPFLT_Msk         (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)       /*!< 0x00001800 */
+#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk
+#define RTC_TAMPCR_TAMPFLT_0           (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */
+#define RTC_TAMPCR_TAMPFLT_1           (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */
+#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)
+#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)      /*!< 0x00000700 */
+#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk
+#define RTC_TAMPCR_TAMPFREQ_0          (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */
+#define RTC_TAMPCR_TAMPFREQ_1          (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */
+#define RTC_TAMPCR_TAMPFREQ_2          (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */
+#define RTC_TAMPCR_TAMPTS_Pos          (7U)
+#define RTC_TAMPCR_TAMPTS_Msk          (0x1UL << RTC_TAMPCR_TAMPTS_Pos)        /*!< 0x00000080 */
+#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk
+#define RTC_TAMPCR_TAMP3TRG_Pos        (6U)
+#define RTC_TAMPCR_TAMP3TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)      /*!< 0x00000040 */
+#define RTC_TAMPCR_TAMP3TRG            RTC_TAMPCR_TAMP3TRG_Msk
+#define RTC_TAMPCR_TAMP3E_Pos          (5U)
+#define RTC_TAMPCR_TAMP3E_Msk          (0x1UL << RTC_TAMPCR_TAMP3E_Pos)        /*!< 0x00000020 */
+#define RTC_TAMPCR_TAMP3E              RTC_TAMPCR_TAMP3E_Msk
+#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)
+#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)      /*!< 0x00000010 */
+#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk
+#define RTC_TAMPCR_TAMP2E_Pos          (3U)
+#define RTC_TAMPCR_TAMP2E_Msk          (0x1UL << RTC_TAMPCR_TAMP2E_Pos)        /*!< 0x00000008 */
+#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk
+#define RTC_TAMPCR_TAMPIE_Pos          (2U)
+#define RTC_TAMPCR_TAMPIE_Msk          (0x1UL << RTC_TAMPCR_TAMPIE_Pos)        /*!< 0x00000004 */
+#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk
+#define RTC_TAMPCR_TAMP1TRG_Pos        (1U)
+#define RTC_TAMPCR_TAMP1TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)      /*!< 0x00000002 */
+#define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk
+#define RTC_TAMPCR_TAMP1E_Pos          (0U)
+#define RTC_TAMPCR_TAMP1E_Msk          (0x1UL << RTC_TAMPCR_TAMP1E_Pos)        /*!< 0x00000001 */
+#define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk
+
+/********************  Bits definition for RTC_ALRMASSR register  *************/
+#define RTC_ALRMASSR_MASKSS_Pos        (24U)
+#define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos            (0U)
+#define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)       /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk
+
+/********************  Bits definition for RTC_ALRMBSSR register  *************/
+#define RTC_ALRMBSSR_MASKSS_Pos        (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos            (0U)
+#define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)       /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk
+
+/********************  Bits definition for RTC_OR register  *******************/
+#define RTC_OR_OUT_RMP_Pos             (1U)
+#define RTC_OR_OUT_RMP_Msk             (0x1UL << RTC_OR_OUT_RMP_Pos)           /*!< 0x00000002 */
+#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk
+#define RTC_OR_ALARMOUTTYPE_Pos        (0U)
+#define RTC_OR_ALARMOUTTYPE_Msk        (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)      /*!< 0x00000001 */
+#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk
+
+/********************  Bits definition for RTC_BKP0R register  ****************/
+#define RTC_BKP0R_Pos                  (0U)
+#define RTC_BKP0R_Msk                  (0xFFFFFFFFUL << RTC_BKP0R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP0R                      RTC_BKP0R_Msk
+
+/********************  Bits definition for RTC_BKP1R register  ****************/
+#define RTC_BKP1R_Pos                  (0U)
+#define RTC_BKP1R_Msk                  (0xFFFFFFFFUL << RTC_BKP1R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP1R                      RTC_BKP1R_Msk
+
+/********************  Bits definition for RTC_BKP2R register  ****************/
+#define RTC_BKP2R_Pos                  (0U)
+#define RTC_BKP2R_Msk                  (0xFFFFFFFFUL << RTC_BKP2R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP2R                      RTC_BKP2R_Msk
+
+/********************  Bits definition for RTC_BKP3R register  ****************/
+#define RTC_BKP3R_Pos                  (0U)
+#define RTC_BKP3R_Msk                  (0xFFFFFFFFUL << RTC_BKP3R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP3R                      RTC_BKP3R_Msk
+
+/********************  Bits definition for RTC_BKP4R register  ****************/
+#define RTC_BKP4R_Pos                  (0U)
+#define RTC_BKP4R_Msk                  (0xFFFFFFFFUL << RTC_BKP4R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP4R                      RTC_BKP4R_Msk
+
+/********************  Bits definition for RTC_BKP5R register  ****************/
+#define RTC_BKP5R_Pos                  (0U)
+#define RTC_BKP5R_Msk                  (0xFFFFFFFFUL << RTC_BKP5R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP5R                      RTC_BKP5R_Msk
+
+/********************  Bits definition for RTC_BKP6R register  ****************/
+#define RTC_BKP6R_Pos                  (0U)
+#define RTC_BKP6R_Msk                  (0xFFFFFFFFUL << RTC_BKP6R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP6R                      RTC_BKP6R_Msk
+
+/********************  Bits definition for RTC_BKP7R register  ****************/
+#define RTC_BKP7R_Pos                  (0U)
+#define RTC_BKP7R_Msk                  (0xFFFFFFFFUL << RTC_BKP7R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP7R                      RTC_BKP7R_Msk
+
+/********************  Bits definition for RTC_BKP8R register  ****************/
+#define RTC_BKP8R_Pos                  (0U)
+#define RTC_BKP8R_Msk                  (0xFFFFFFFFUL << RTC_BKP8R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP8R                      RTC_BKP8R_Msk
+
+/********************  Bits definition for RTC_BKP9R register  ****************/
+#define RTC_BKP9R_Pos                  (0U)
+#define RTC_BKP9R_Msk                  (0xFFFFFFFFUL << RTC_BKP9R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP9R                      RTC_BKP9R_Msk
+
+/********************  Bits definition for RTC_BKP10R register  ***************/
+#define RTC_BKP10R_Pos                 (0U)
+#define RTC_BKP10R_Msk                 (0xFFFFFFFFUL << RTC_BKP10R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP10R                     RTC_BKP10R_Msk
+
+/********************  Bits definition for RTC_BKP11R register  ***************/
+#define RTC_BKP11R_Pos                 (0U)
+#define RTC_BKP11R_Msk                 (0xFFFFFFFFUL << RTC_BKP11R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP11R                     RTC_BKP11R_Msk
+
+/********************  Bits definition for RTC_BKP12R register  ***************/
+#define RTC_BKP12R_Pos                 (0U)
+#define RTC_BKP12R_Msk                 (0xFFFFFFFFUL << RTC_BKP12R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP12R                     RTC_BKP12R_Msk
+
+/********************  Bits definition for RTC_BKP13R register  ***************/
+#define RTC_BKP13R_Pos                 (0U)
+#define RTC_BKP13R_Msk                 (0xFFFFFFFFUL << RTC_BKP13R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP13R                     RTC_BKP13R_Msk
+
+/********************  Bits definition for RTC_BKP14R register  ***************/
+#define RTC_BKP14R_Pos                 (0U)
+#define RTC_BKP14R_Msk                 (0xFFFFFFFFUL << RTC_BKP14R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP14R                     RTC_BKP14R_Msk
+
+/********************  Bits definition for RTC_BKP15R register  ***************/
+#define RTC_BKP15R_Pos                 (0U)
+#define RTC_BKP15R_Msk                 (0xFFFFFFFFUL << RTC_BKP15R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP15R                     RTC_BKP15R_Msk
+
+/********************  Bits definition for RTC_BKP16R register  ***************/
+#define RTC_BKP16R_Pos                 (0U)
+#define RTC_BKP16R_Msk                 (0xFFFFFFFFUL << RTC_BKP16R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP16R                     RTC_BKP16R_Msk
+
+/********************  Bits definition for RTC_BKP17R register  ***************/
+#define RTC_BKP17R_Pos                 (0U)
+#define RTC_BKP17R_Msk                 (0xFFFFFFFFUL << RTC_BKP17R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP17R                     RTC_BKP17R_Msk
+
+/********************  Bits definition for RTC_BKP18R register  ***************/
+#define RTC_BKP18R_Pos                 (0U)
+#define RTC_BKP18R_Msk                 (0xFFFFFFFFUL << RTC_BKP18R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP18R                     RTC_BKP18R_Msk
+
+/********************  Bits definition for RTC_BKP19R register  ***************/
+#define RTC_BKP19R_Pos                 (0U)
+#define RTC_BKP19R_Msk                 (0xFFFFFFFFUL << RTC_BKP19R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP19R                     RTC_BKP19R_Msk
+
+/********************  Bits definition for RTC_BKP20R register  ***************/
+#define RTC_BKP20R_Pos                 (0U)
+#define RTC_BKP20R_Msk                 (0xFFFFFFFFUL << RTC_BKP20R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP20R                     RTC_BKP20R_Msk
+
+/********************  Bits definition for RTC_BKP21R register  ***************/
+#define RTC_BKP21R_Pos                 (0U)
+#define RTC_BKP21R_Msk                 (0xFFFFFFFFUL << RTC_BKP21R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP21R                     RTC_BKP21R_Msk
+
+/********************  Bits definition for RTC_BKP22R register  ***************/
+#define RTC_BKP22R_Pos                 (0U)
+#define RTC_BKP22R_Msk                 (0xFFFFFFFFUL << RTC_BKP22R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP22R                     RTC_BKP22R_Msk
+
+/********************  Bits definition for RTC_BKP23R register  ***************/
+#define RTC_BKP23R_Pos                 (0U)
+#define RTC_BKP23R_Msk                 (0xFFFFFFFFUL << RTC_BKP23R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP23R                     RTC_BKP23R_Msk
+
+/********************  Bits definition for RTC_BKP24R register  ***************/
+#define RTC_BKP24R_Pos                 (0U)
+#define RTC_BKP24R_Msk                 (0xFFFFFFFFUL << RTC_BKP24R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP24R                     RTC_BKP24R_Msk
+
+/********************  Bits definition for RTC_BKP25R register  ***************/
+#define RTC_BKP25R_Pos                 (0U)
+#define RTC_BKP25R_Msk                 (0xFFFFFFFFUL << RTC_BKP25R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP25R                     RTC_BKP25R_Msk
+
+/********************  Bits definition for RTC_BKP26R register  ***************/
+#define RTC_BKP26R_Pos                 (0U)
+#define RTC_BKP26R_Msk                 (0xFFFFFFFFUL << RTC_BKP26R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP26R                     RTC_BKP26R_Msk
+
+/********************  Bits definition for RTC_BKP27R register  ***************/
+#define RTC_BKP27R_Pos                 (0U)
+#define RTC_BKP27R_Msk                 (0xFFFFFFFFUL << RTC_BKP27R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP27R                     RTC_BKP27R_Msk
+
+/********************  Bits definition for RTC_BKP28R register  ***************/
+#define RTC_BKP28R_Pos                 (0U)
+#define RTC_BKP28R_Msk                 (0xFFFFFFFFUL << RTC_BKP28R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP28R                     RTC_BKP28R_Msk
+
+/********************  Bits definition for RTC_BKP29R register  ***************/
+#define RTC_BKP29R_Pos                 (0U)
+#define RTC_BKP29R_Msk                 (0xFFFFFFFFUL << RTC_BKP29R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP29R                     RTC_BKP29R_Msk
+
+/********************  Bits definition for RTC_BKP30R register  ***************/
+#define RTC_BKP30R_Pos                 (0U)
+#define RTC_BKP30R_Msk                 (0xFFFFFFFFUL << RTC_BKP30R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP30R                     RTC_BKP30R_Msk
+
+/********************  Bits definition for RTC_BKP31R register  ***************/
+#define RTC_BKP31R_Pos                 (0U)
+#define RTC_BKP31R_Msk                 (0xFFFFFFFFUL << RTC_BKP31R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP31R                     RTC_BKP31R_Msk
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER_Pos             (5U)
+#define RTC_BKP_NUMBER_Msk             (0x1UL << RTC_BKP_NUMBER_Pos)           /*!< 0x00000020 */
+#define RTC_BKP_NUMBER                 RTC_BKP_NUMBER_Msk
+
+/******************************************************************************/
+/*                                                                            */
+/*                              SPDIF-RX Interface                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for SPDIF_CR register  ******************/
+#define SPDIFRX_CR_SPDIFEN_Pos      (0U)
+#define SPDIFRX_CR_SPDIFEN_Msk      (0x3UL << SPDIFRX_CR_SPDIFEN_Pos)          /*!< 0x00000003 */
+#define SPDIFRX_CR_SPDIFEN          SPDIFRX_CR_SPDIFEN_Msk                     /*!<Peripheral Block Enable                      */
+#define SPDIFRX_CR_RXDMAEN_Pos      (2U)
+#define SPDIFRX_CR_RXDMAEN_Msk      (0x1UL << SPDIFRX_CR_RXDMAEN_Pos)          /*!< 0x00000004 */
+#define SPDIFRX_CR_RXDMAEN          SPDIFRX_CR_RXDMAEN_Msk                     /*!<Receiver DMA Enable for data flow            */
+#define SPDIFRX_CR_RXSTEO_Pos       (3U)
+#define SPDIFRX_CR_RXSTEO_Msk       (0x1UL << SPDIFRX_CR_RXSTEO_Pos)           /*!< 0x00000008 */
+#define SPDIFRX_CR_RXSTEO           SPDIFRX_CR_RXSTEO_Msk                      /*!<Stereo Mode                                  */
+#define SPDIFRX_CR_DRFMT_Pos        (4U)
+#define SPDIFRX_CR_DRFMT_Msk        (0x3UL << SPDIFRX_CR_DRFMT_Pos)            /*!< 0x00000030 */
+#define SPDIFRX_CR_DRFMT            SPDIFRX_CR_DRFMT_Msk                       /*!<RX Data format                               */
+#define SPDIFRX_CR_PMSK_Pos         (6U)
+#define SPDIFRX_CR_PMSK_Msk         (0x1UL << SPDIFRX_CR_PMSK_Pos)             /*!< 0x00000040 */
+#define SPDIFRX_CR_PMSK             SPDIFRX_CR_PMSK_Msk                        /*!<Mask Parity error bit                        */
+#define SPDIFRX_CR_VMSK_Pos         (7U)
+#define SPDIFRX_CR_VMSK_Msk         (0x1UL << SPDIFRX_CR_VMSK_Pos)             /*!< 0x00000080 */
+#define SPDIFRX_CR_VMSK             SPDIFRX_CR_VMSK_Msk                        /*!<Mask of Validity bit                         */
+#define SPDIFRX_CR_CUMSK_Pos        (8U)
+#define SPDIFRX_CR_CUMSK_Msk        (0x1UL << SPDIFRX_CR_CUMSK_Pos)            /*!< 0x00000100 */
+#define SPDIFRX_CR_CUMSK            SPDIFRX_CR_CUMSK_Msk                       /*!<Mask of channel status and user bits         */
+#define SPDIFRX_CR_PTMSK_Pos        (9U)
+#define SPDIFRX_CR_PTMSK_Msk        (0x1UL << SPDIFRX_CR_PTMSK_Pos)            /*!< 0x00000200 */
+#define SPDIFRX_CR_PTMSK            SPDIFRX_CR_PTMSK_Msk                       /*!<Mask of Preamble Type bits                   */
+#define SPDIFRX_CR_CBDMAEN_Pos      (10U)
+#define SPDIFRX_CR_CBDMAEN_Msk      (0x1UL << SPDIFRX_CR_CBDMAEN_Pos)          /*!< 0x00000400 */
+#define SPDIFRX_CR_CBDMAEN          SPDIFRX_CR_CBDMAEN_Msk                     /*!<Control Buffer DMA ENable for control flow   */
+#define SPDIFRX_CR_CHSEL_Pos        (11U)
+#define SPDIFRX_CR_CHSEL_Msk        (0x1UL << SPDIFRX_CR_CHSEL_Pos)            /*!< 0x00000800 */
+#define SPDIFRX_CR_CHSEL            SPDIFRX_CR_CHSEL_Msk                       /*!<Channel Selection                            */
+#define SPDIFRX_CR_NBTR_Pos         (12U)
+#define SPDIFRX_CR_NBTR_Msk         (0x3UL << SPDIFRX_CR_NBTR_Pos)             /*!< 0x00003000 */
+#define SPDIFRX_CR_NBTR             SPDIFRX_CR_NBTR_Msk                        /*!<Maximum allowed re-tries during synchronization phase */
+#define SPDIFRX_CR_WFA_Pos          (14U)
+#define SPDIFRX_CR_WFA_Msk          (0x1UL << SPDIFRX_CR_WFA_Pos)              /*!< 0x00004000 */
+#define SPDIFRX_CR_WFA              SPDIFRX_CR_WFA_Msk                         /*!<Wait For Activity     */
+#define SPDIFRX_CR_INSEL_Pos        (16U)
+#define SPDIFRX_CR_INSEL_Msk        (0x7UL << SPDIFRX_CR_INSEL_Pos)            /*!< 0x00070000 */
+#define SPDIFRX_CR_INSEL            SPDIFRX_CR_INSEL_Msk                       /*!<SPDIF input selection */
+#define SPDIFRX_CR_CKSEN_Pos        (20U)
+#define SPDIFRX_CR_CKSEN_Msk        (0x1UL << SPDIFRX_CR_CKSEN_Pos)            /*!< 0x00100000 */
+#define SPDIFRX_CR_CKSEN            SPDIFRX_CR_CKSEN_Msk                       /*!<Symbol Clock Enable */
+#define SPDIFRX_CR_CKSBKPEN_Pos     (21U)
+#define SPDIFRX_CR_CKSBKPEN_Msk     (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos)         /*!< 0x00200000 */
+#define SPDIFRX_CR_CKSBKPEN         SPDIFRX_CR_CKSBKPEN_Msk                    /*!<Backup Symbol Clock Enable */
+
+/*******************  Bit definition for SPDIFRX_IMR register  *******************/
+#define SPDIFRX_IMR_RXNEIE_Pos      (0U)
+#define SPDIFRX_IMR_RXNEIE_Msk      (0x1UL << SPDIFRX_IMR_RXNEIE_Pos)          /*!< 0x00000001 */
+#define SPDIFRX_IMR_RXNEIE          SPDIFRX_IMR_RXNEIE_Msk                     /*!<RXNE interrupt enable                              */
+#define SPDIFRX_IMR_CSRNEIE_Pos     (1U)
+#define SPDIFRX_IMR_CSRNEIE_Msk     (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos)         /*!< 0x00000002 */
+#define SPDIFRX_IMR_CSRNEIE         SPDIFRX_IMR_CSRNEIE_Msk                    /*!<Control Buffer Ready Interrupt Enable              */
+#define SPDIFRX_IMR_PERRIE_Pos      (2U)
+#define SPDIFRX_IMR_PERRIE_Msk      (0x1UL << SPDIFRX_IMR_PERRIE_Pos)          /*!< 0x00000004 */
+#define SPDIFRX_IMR_PERRIE          SPDIFRX_IMR_PERRIE_Msk                     /*!<Parity error interrupt enable                      */
+#define SPDIFRX_IMR_OVRIE_Pos       (3U)
+#define SPDIFRX_IMR_OVRIE_Msk       (0x1UL << SPDIFRX_IMR_OVRIE_Pos)           /*!< 0x00000008 */
+#define SPDIFRX_IMR_OVRIE           SPDIFRX_IMR_OVRIE_Msk                      /*!<Overrun error Interrupt Enable                     */
+#define SPDIFRX_IMR_SBLKIE_Pos      (4U)
+#define SPDIFRX_IMR_SBLKIE_Msk      (0x1UL << SPDIFRX_IMR_SBLKIE_Pos)          /*!< 0x00000010 */
+#define SPDIFRX_IMR_SBLKIE          SPDIFRX_IMR_SBLKIE_Msk                     /*!<Synchronization Block Detected Interrupt Enable    */
+#define SPDIFRX_IMR_SYNCDIE_Pos     (5U)
+#define SPDIFRX_IMR_SYNCDIE_Msk     (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos)         /*!< 0x00000020 */
+#define SPDIFRX_IMR_SYNCDIE         SPDIFRX_IMR_SYNCDIE_Msk                    /*!<Synchronization Done                               */
+#define SPDIFRX_IMR_IFEIE_Pos       (6U)
+#define SPDIFRX_IMR_IFEIE_Msk       (0x1UL << SPDIFRX_IMR_IFEIE_Pos)           /*!< 0x00000040 */
+#define SPDIFRX_IMR_IFEIE           SPDIFRX_IMR_IFEIE_Msk                      /*!<Serial Interface Error Interrupt Enable            */
+
+/*******************  Bit definition for SPDIFRX_SR register  *******************/
+#define SPDIFRX_SR_RXNE_Pos         (0U)
+#define SPDIFRX_SR_RXNE_Msk         (0x1UL << SPDIFRX_SR_RXNE_Pos)             /*!< 0x00000001 */
+#define SPDIFRX_SR_RXNE             SPDIFRX_SR_RXNE_Msk                        /*!<Read data register not empty                          */
+#define SPDIFRX_SR_CSRNE_Pos        (1U)
+#define SPDIFRX_SR_CSRNE_Msk        (0x1UL << SPDIFRX_SR_CSRNE_Pos)            /*!< 0x00000002 */
+#define SPDIFRX_SR_CSRNE            SPDIFRX_SR_CSRNE_Msk                       /*!<The Control Buffer register is not empty              */
+#define SPDIFRX_SR_PERR_Pos         (2U)
+#define SPDIFRX_SR_PERR_Msk         (0x1UL << SPDIFRX_SR_PERR_Pos)             /*!< 0x00000004 */
+#define SPDIFRX_SR_PERR             SPDIFRX_SR_PERR_Msk                        /*!<Parity error                                          */
+#define SPDIFRX_SR_OVR_Pos          (3U)
+#define SPDIFRX_SR_OVR_Msk          (0x1UL << SPDIFRX_SR_OVR_Pos)              /*!< 0x00000008 */
+#define SPDIFRX_SR_OVR              SPDIFRX_SR_OVR_Msk                         /*!<Overrun error                                         */
+#define SPDIFRX_SR_SBD_Pos          (4U)
+#define SPDIFRX_SR_SBD_Msk          (0x1UL << SPDIFRX_SR_SBD_Pos)              /*!< 0x00000010 */
+#define SPDIFRX_SR_SBD              SPDIFRX_SR_SBD_Msk                         /*!<Synchronization Block Detected                        */
+#define SPDIFRX_SR_SYNCD_Pos        (5U)
+#define SPDIFRX_SR_SYNCD_Msk        (0x1UL << SPDIFRX_SR_SYNCD_Pos)            /*!< 0x00000020 */
+#define SPDIFRX_SR_SYNCD            SPDIFRX_SR_SYNCD_Msk                       /*!<Synchronization Done                                  */
+#define SPDIFRX_SR_FERR_Pos         (6U)
+#define SPDIFRX_SR_FERR_Msk         (0x1UL << SPDIFRX_SR_FERR_Pos)             /*!< 0x00000040 */
+#define SPDIFRX_SR_FERR             SPDIFRX_SR_FERR_Msk                        /*!<Framing error                                         */
+#define SPDIFRX_SR_SERR_Pos         (7U)
+#define SPDIFRX_SR_SERR_Msk         (0x1UL << SPDIFRX_SR_SERR_Pos)             /*!< 0x00000080 */
+#define SPDIFRX_SR_SERR             SPDIFRX_SR_SERR_Msk                        /*!<Synchronization error                                 */
+#define SPDIFRX_SR_TERR_Pos         (8U)
+#define SPDIFRX_SR_TERR_Msk         (0x1UL << SPDIFRX_SR_TERR_Pos)             /*!< 0x00000100 */
+#define SPDIFRX_SR_TERR             SPDIFRX_SR_TERR_Msk                        /*!<Time-out error                                        */
+#define SPDIFRX_SR_WIDTH5_Pos       (16U)
+#define SPDIFRX_SR_WIDTH5_Msk       (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos)        /*!< 0x7FFF0000 */
+#define SPDIFRX_SR_WIDTH5           SPDIFRX_SR_WIDTH5_Msk                      /*!<Duration of 5 symbols counted with spdif_clk          */
+
+/*******************  Bit definition for SPDIFRX_IFCR register  *******************/
+#define SPDIFRX_IFCR_PERRCF_Pos     (2U)
+#define SPDIFRX_IFCR_PERRCF_Msk     (0x1UL << SPDIFRX_IFCR_PERRCF_Pos)         /*!< 0x00000004 */
+#define SPDIFRX_IFCR_PERRCF         SPDIFRX_IFCR_PERRCF_Msk                    /*!<Clears the Parity error flag                         */
+#define SPDIFRX_IFCR_OVRCF_Pos      (3U)
+#define SPDIFRX_IFCR_OVRCF_Msk      (0x1UL << SPDIFRX_IFCR_OVRCF_Pos)          /*!< 0x00000008 */
+#define SPDIFRX_IFCR_OVRCF          SPDIFRX_IFCR_OVRCF_Msk                     /*!<Clears the Overrun error flag                        */
+#define SPDIFRX_IFCR_SBDCF_Pos      (4U)
+#define SPDIFRX_IFCR_SBDCF_Msk      (0x1UL << SPDIFRX_IFCR_SBDCF_Pos)          /*!< 0x00000010 */
+#define SPDIFRX_IFCR_SBDCF          SPDIFRX_IFCR_SBDCF_Msk                     /*!<Clears the Synchronization Block Detected flag       */
+#define SPDIFRX_IFCR_SYNCDCF_Pos    (5U)
+#define SPDIFRX_IFCR_SYNCDCF_Msk    (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos)        /*!< 0x00000020 */
+#define SPDIFRX_IFCR_SYNCDCF        SPDIFRX_IFCR_SYNCDCF_Msk                   /*!<Clears the Synchronization Done flag                 */
+
+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b00 case) *******************/
+#define SPDIFRX_DR0_DR_Pos          (0U)
+#define SPDIFRX_DR0_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos)         /*!< 0x00FFFFFF */
+#define SPDIFRX_DR0_DR              SPDIFRX_DR0_DR_Msk                         /*!<Data value            */
+#define SPDIFRX_DR0_PE_Pos          (24U)
+#define SPDIFRX_DR0_PE_Msk          (0x1UL << SPDIFRX_DR0_PE_Pos)              /*!< 0x01000000 */
+#define SPDIFRX_DR0_PE              SPDIFRX_DR0_PE_Msk                         /*!<Parity Error bit      */
+#define SPDIFRX_DR0_V_Pos           (25U)
+#define SPDIFRX_DR0_V_Msk           (0x1UL << SPDIFRX_DR0_V_Pos)               /*!< 0x02000000 */
+#define SPDIFRX_DR0_V               SPDIFRX_DR0_V_Msk                          /*!<Validity bit          */
+#define SPDIFRX_DR0_U_Pos           (26U)
+#define SPDIFRX_DR0_U_Msk           (0x1UL << SPDIFRX_DR0_U_Pos)               /*!< 0x04000000 */
+#define SPDIFRX_DR0_U               SPDIFRX_DR0_U_Msk                          /*!<User bit              */
+#define SPDIFRX_DR0_C_Pos           (27U)
+#define SPDIFRX_DR0_C_Msk           (0x1UL << SPDIFRX_DR0_C_Pos)               /*!< 0x08000000 */
+#define SPDIFRX_DR0_C               SPDIFRX_DR0_C_Msk                          /*!<Channel Status bit    */
+#define SPDIFRX_DR0_PT_Pos          (28U)
+#define SPDIFRX_DR0_PT_Msk          (0x3UL << SPDIFRX_DR0_PT_Pos)              /*!< 0x30000000 */
+#define SPDIFRX_DR0_PT              SPDIFRX_DR0_PT_Msk                         /*!<Preamble Type         */
+
+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b01 case) *******************/
+#define SPDIFRX_DR1_DR_Pos          (8U)
+#define SPDIFRX_DR1_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos)         /*!< 0xFFFFFF00 */
+#define SPDIFRX_DR1_DR              SPDIFRX_DR1_DR_Msk                         /*!<Data value            */
+#define SPDIFRX_DR1_PT_Pos          (4U)
+#define SPDIFRX_DR1_PT_Msk          (0x3UL << SPDIFRX_DR1_PT_Pos)              /*!< 0x00000030 */
+#define SPDIFRX_DR1_PT              SPDIFRX_DR1_PT_Msk                         /*!<Preamble Type         */
+#define SPDIFRX_DR1_C_Pos           (3U)
+#define SPDIFRX_DR1_C_Msk           (0x1UL << SPDIFRX_DR1_C_Pos)               /*!< 0x00000008 */
+#define SPDIFRX_DR1_C               SPDIFRX_DR1_C_Msk                          /*!<Channel Status bit    */
+#define SPDIFRX_DR1_U_Pos           (2U)
+#define SPDIFRX_DR1_U_Msk           (0x1UL << SPDIFRX_DR1_U_Pos)               /*!< 0x00000004 */
+#define SPDIFRX_DR1_U               SPDIFRX_DR1_U_Msk                          /*!<User bit              */
+#define SPDIFRX_DR1_V_Pos           (1U)
+#define SPDIFRX_DR1_V_Msk           (0x1UL << SPDIFRX_DR1_V_Pos)               /*!< 0x00000002 */
+#define SPDIFRX_DR1_V               SPDIFRX_DR1_V_Msk                          /*!<Validity bit          */
+#define SPDIFRX_DR1_PE_Pos          (0U)
+#define SPDIFRX_DR1_PE_Msk          (0x1UL << SPDIFRX_DR1_PE_Pos)              /*!< 0x00000001 */
+#define SPDIFRX_DR1_PE              SPDIFRX_DR1_PE_Msk                         /*!<Parity Error bit      */
+
+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b10 case) *******************/
+#define SPDIFRX_DR1_DRNL1_Pos       (16U)
+#define SPDIFRX_DR1_DRNL1_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos)        /*!< 0xFFFF0000 */
+#define SPDIFRX_DR1_DRNL1           SPDIFRX_DR1_DRNL1_Msk                      /*!<Data value Channel B      */
+#define SPDIFRX_DR1_DRNL2_Pos       (0U)
+#define SPDIFRX_DR1_DRNL2_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos)        /*!< 0x0000FFFF */
+#define SPDIFRX_DR1_DRNL2           SPDIFRX_DR1_DRNL2_Msk                      /*!<Data value Channel A      */
+
+/*******************  Bit definition for SPDIFRX_CSR register   *******************/
+#define SPDIFRX_CSR_USR_Pos         (0U)
+#define SPDIFRX_CSR_USR_Msk         (0xFFFFUL << SPDIFRX_CSR_USR_Pos)          /*!< 0x0000FFFF */
+#define SPDIFRX_CSR_USR             SPDIFRX_CSR_USR_Msk                        /*!<User data information           */
+#define SPDIFRX_CSR_CS_Pos          (16U)
+#define SPDIFRX_CSR_CS_Msk          (0xFFUL << SPDIFRX_CSR_CS_Pos)             /*!< 0x00FF0000 */
+#define SPDIFRX_CSR_CS              SPDIFRX_CSR_CS_Msk                         /*!<Channel A status information    */
+#define SPDIFRX_CSR_SOB_Pos         (24U)
+#define SPDIFRX_CSR_SOB_Msk         (0x1UL << SPDIFRX_CSR_SOB_Pos)             /*!< 0x01000000 */
+#define SPDIFRX_CSR_SOB             SPDIFRX_CSR_SOB_Msk                        /*!<Start Of Block                  */
+
+/*******************  Bit definition for SPDIFRX_DIR register    *******************/
+#define SPDIFRX_DIR_THI_Pos         (0U)
+#define SPDIFRX_DIR_THI_Msk         (0x1FFFUL << SPDIFRX_DIR_THI_Pos)          /*!< 0x00001FFF */
+#define SPDIFRX_DIR_THI             SPDIFRX_DIR_THI_Msk                        /*!<Threshold LOW      */
+#define SPDIFRX_DIR_TLO_Pos         (16U)
+#define SPDIFRX_DIR_TLO_Msk         (0x1FFFUL << SPDIFRX_DIR_TLO_Pos)          /*!< 0x1FFF0000 */
+#define SPDIFRX_DIR_TLO             SPDIFRX_DIR_TLO_Msk                        /*!<Threshold HIGH     */
+
+/*******************  Bit definition for SPDIFRX_VERR register    *******************/
+#define SPDIFRX_VERR_MINREV_Pos     (0U)
+#define SPDIFRX_VERR_MINREV_Msk     (0xFUL << SPDIFRX_VERR_MINREV_Pos)         /*!< 0x0000000F */
+#define SPDIFRX_VERR_MINREV         SPDIFRX_VERR_MINREV_Msk                    /*!<SPDIFRX Minor revision     */
+#define SPDIFRX_VERR_MAJREV_Pos     (4U)
+#define SPDIFRX_VERR_MAJREV_Msk     (0xFUL << SPDIFRX_VERR_MAJREV_Pos)         /*!< 0x000000F0 */
+#define SPDIFRX_VERR_MAJREV         SPDIFRX_VERR_MAJREV_Msk                    /*!<SPDIFRX Major revision     */
+
+/*******************  Bit definition for SPDIFRX_IDR register    *******************/
+#define SPDIFRX_IDR_ID_Pos          (0U)
+#define SPDIFRX_IDR_ID_Msk          (0xFFFFFFFFUL << SPDIFRX_IDR_ID_Pos)       /*!< 0xFFFFFFFF */
+#define SPDIFRX_IDR_ID              SPDIFRX_IDR_ID_Msk                         /*!<SPDIFRX identifier     */
+
+/*******************  Bit definition for SPDIFRX_SIDR register    *******************/
+#define SPDIFRX_SIDR_SID_Pos        (0U)
+#define SPDIFRX_SIDR_SID_Msk        (0xFFFFFFFFUL << SPDIFRX_SIDR_SID_Pos)     /*!< 0xFFFFFFFF */
+#define SPDIFRX_SIDR_SID            SPDIFRX_SIDR_SID_Msk                       /*!<Size of the memory region allocated to SPDIFRX registers */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Serial Audio Interface                            */
+/*                                                                            */
+/******************************************************************************/
+/*******************************  SAI VERSION  ********************************/
+#define SAI_VER_V2_X
+
+/********************  Bit definition for SAI_GCR register  *******************/
+#define SAI_GCR_SYNCIN_Pos         (0U)
+#define SAI_GCR_SYNCIN_Msk         (0x3UL << SAI_GCR_SYNCIN_Pos)               /*!< 0x00000003 */
+#define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
+#define SAI_GCR_SYNCIN_0           (0x1UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */
+#define SAI_GCR_SYNCIN_1           (0x2UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */
+
+#define SAI_GCR_SYNCOUT_Pos        (4U)
+#define SAI_GCR_SYNCOUT_Msk        (0x3UL << SAI_GCR_SYNCOUT_Pos)              /*!< 0x00000030 */
+#define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define SAI_GCR_SYNCOUT_0          (0x1UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */
+#define SAI_GCR_SYNCOUT_1          (0x2UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */
+
+/*******************  Bit definition for SAI_xCR1 register  *******************/
+#define SAI_xCR1_MODE_Pos          (0U)
+#define SAI_xCR1_MODE_Msk          (0x3UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000003 */
+#define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */
+#define SAI_xCR1_MODE_0            (0x1UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */
+#define SAI_xCR1_MODE_1            (0x2UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */
+
+#define SAI_xCR1_PRTCFG_Pos        (2U)
+#define SAI_xCR1_PRTCFG_Msk        (0x3UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x0000000C */
+#define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
+#define SAI_xCR1_PRTCFG_0          (0x1UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */
+#define SAI_xCR1_PRTCFG_1          (0x2UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */
+
+#define SAI_xCR1_DS_Pos            (5U)
+#define SAI_xCR1_DS_Msk            (0x7UL << SAI_xCR1_DS_Pos)                  /*!< 0x000000E0 */
+#define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */
+#define SAI_xCR1_DS_0              (0x1UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */
+#define SAI_xCR1_DS_1              (0x2UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */
+#define SAI_xCR1_DS_2              (0x4UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */
+
+#define SAI_xCR1_LSBFIRST_Pos      (8U)
+#define SAI_xCR1_LSBFIRST_Msk      (0x1UL << SAI_xCR1_LSBFIRST_Pos)            /*!< 0x00000100 */
+#define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */
+#define SAI_xCR1_CKSTR_Pos         (9U)
+#define SAI_xCR1_CKSTR_Msk         (0x1UL << SAI_xCR1_CKSTR_Pos)               /*!< 0x00000200 */
+#define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */
+
+#define SAI_xCR1_SYNCEN_Pos        (10U)
+#define SAI_xCR1_SYNCEN_Msk        (0x3UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000C00 */
+#define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define SAI_xCR1_SYNCEN_0          (0x1UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */
+#define SAI_xCR1_SYNCEN_1          (0x2UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */
+
+#define SAI_xCR1_MONO_Pos          (12U)
+#define SAI_xCR1_MONO_Msk          (0x1UL << SAI_xCR1_MONO_Pos)                /*!< 0x00001000 */
+#define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */
+#define SAI_xCR1_OUTDRIV_Pos       (13U)
+#define SAI_xCR1_OUTDRIV_Msk       (0x1UL << SAI_xCR1_OUTDRIV_Pos)             /*!< 0x00002000 */
+#define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */
+#define SAI_xCR1_SAIEN_Pos         (16U)
+#define SAI_xCR1_SAIEN_Msk         (0x1UL << SAI_xCR1_SAIEN_Pos)               /*!< 0x00010000 */
+#define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */
+#define SAI_xCR1_DMAEN_Pos         (17U)
+#define SAI_xCR1_DMAEN_Msk         (0x1UL << SAI_xCR1_DMAEN_Pos)               /*!< 0x00020000 */
+#define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */
+#define SAI_xCR1_NODIV_Pos         (19U)
+#define SAI_xCR1_NODIV_Msk         (0x1UL << SAI_xCR1_NODIV_Pos)               /*!< 0x00080000 */
+#define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */
+
+#define SAI_xCR1_MCKDIV_Pos        (20U)
+#define SAI_xCR1_MCKDIV_Msk        (0x3FUL << SAI_xCR1_MCKDIV_Pos)             /*!< 0x03F00000 */
+#define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[5:0] (Master ClocK Divider)  */
+#define SAI_xCR1_MCKDIV_0          (0x01UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00100000 */
+#define SAI_xCR1_MCKDIV_1          (0x02UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00200000 */
+#define SAI_xCR1_MCKDIV_2          (0x04UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00400000 */
+#define SAI_xCR1_MCKDIV_3          (0x08UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00800000 */
+#define SAI_xCR1_MCKDIV_4          (0x10UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x01000000 */
+#define SAI_xCR1_MCKDIV_5          (0x20UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x02000000 */
+
+#define SAI_xCR1_MCKEN_Pos         (27U)
+#define SAI_xCR1_MCKEN_Msk         (0x1UL << SAI_xCR1_MCKEN_Pos)               /*!< 0x08000000 */
+#define SAI_xCR1_MCKEN             SAI_xCR1_MCKEN_Msk                          /*!<Master ClocK enable */
+
+#define SAI_xCR1_OSR_Pos           (26U)
+#define SAI_xCR1_OSR_Msk           (0x1UL << SAI_xCR1_OSR_Pos)                 /*!< 0x04000000 */
+#define SAI_xCR1_OSR               SAI_xCR1_OSR_Msk                            /*!<OverSampling Ratio for master clock  */
+
+/* Legacy define */
+#define  SAI_xCR1_NOMCK               SAI_xCR1_NODIV
+
+/*******************  Bit definition for SAI_xCR2 register  *******************/
+#define SAI_xCR2_FTH_Pos           (0U)
+#define SAI_xCR2_FTH_Msk           (0x7UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000007 */
+#define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */
+#define SAI_xCR2_FTH_0             (0x1UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */
+#define SAI_xCR2_FTH_1             (0x2UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */
+#define SAI_xCR2_FTH_2             (0x4UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */
+
+#define SAI_xCR2_FFLUSH_Pos        (3U)
+#define SAI_xCR2_FFLUSH_Msk        (0x1UL << SAI_xCR2_FFLUSH_Pos)              /*!< 0x00000008 */
+#define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */
+#define SAI_xCR2_TRIS_Pos          (4U)
+#define SAI_xCR2_TRIS_Msk          (0x1UL << SAI_xCR2_TRIS_Pos)                /*!< 0x00000010 */
+#define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */
+#define SAI_xCR2_MUTE_Pos          (5U)
+#define SAI_xCR2_MUTE_Msk          (0x1UL << SAI_xCR2_MUTE_Pos)                /*!< 0x00000020 */
+#define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */
+#define SAI_xCR2_MUTEVAL_Pos       (6U)
+#define SAI_xCR2_MUTEVAL_Msk       (0x1UL << SAI_xCR2_MUTEVAL_Pos)             /*!< 0x00000040 */
+#define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */
+
+#define SAI_xCR2_MUTECNT_Pos       (7U)
+#define SAI_xCR2_MUTECNT_Msk       (0x3FUL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00001F80 */
+#define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */
+#define SAI_xCR2_MUTECNT_0         (0x01UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */
+#define SAI_xCR2_MUTECNT_1         (0x02UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */
+#define SAI_xCR2_MUTECNT_2         (0x04UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */
+#define SAI_xCR2_MUTECNT_3         (0x08UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */
+#define SAI_xCR2_MUTECNT_4         (0x10UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */
+#define SAI_xCR2_MUTECNT_5         (0x20UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */
+
+#define SAI_xCR2_CPL_Pos           (13U)
+#define SAI_xCR2_CPL_Msk           (0x1UL << SAI_xCR2_CPL_Pos)                 /*!< 0x00002000 */
+#define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!< Complement Bit             */
+
+#define SAI_xCR2_COMP_Pos          (14U)
+#define SAI_xCR2_COMP_Msk          (0x3UL << SAI_xCR2_COMP_Pos)                /*!< 0x0000C000 */
+#define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */
+#define SAI_xCR2_COMP_0            (0x1UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */
+#define SAI_xCR2_COMP_1            (0x2UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */
+
+/******************  Bit definition for SAI_xFRCR register  *******************/
+#define SAI_xFRCR_FRL_Pos          (0U)
+#define SAI_xFRCR_FRL_Msk          (0xFFUL << SAI_xFRCR_FRL_Pos)               /*!< 0x000000FF */
+#define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](FRame Length)  */
+#define SAI_xFRCR_FRL_0            (0x01UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */
+#define SAI_xFRCR_FRL_1            (0x02UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */
+#define SAI_xFRCR_FRL_2            (0x04UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */
+#define SAI_xFRCR_FRL_3            (0x08UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */
+#define SAI_xFRCR_FRL_4            (0x10UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */
+#define SAI_xFRCR_FRL_5            (0x20UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */
+#define SAI_xFRCR_FRL_6            (0x40UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */
+#define SAI_xFRCR_FRL_7            (0x80UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */
+
+#define SAI_xFRCR_FSALL_Pos        (8U)
+#define SAI_xFRCR_FSALL_Msk        (0x7FUL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00007F00 */
+#define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FSALL[6:0] (Frame Synchronization Active Level Length)  */
+#define SAI_xFRCR_FSALL_0          (0x01UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */
+#define SAI_xFRCR_FSALL_1          (0x02UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */
+#define SAI_xFRCR_FSALL_2          (0x04UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */
+#define SAI_xFRCR_FSALL_3          (0x08UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */
+#define SAI_xFRCR_FSALL_4          (0x10UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */
+#define SAI_xFRCR_FSALL_5          (0x20UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */
+#define SAI_xFRCR_FSALL_6          (0x40UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */
+
+#define SAI_xFRCR_FSDEF_Pos        (16U)
+#define SAI_xFRCR_FSDEF_Msk        (0x1UL << SAI_xFRCR_FSDEF_Pos)              /*!< 0x00010000 */
+#define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!<Frame Synchronization Definition  */
+#define SAI_xFRCR_FSPOL_Pos        (17U)
+#define SAI_xFRCR_FSPOL_Msk        (0x1UL << SAI_xFRCR_FSPOL_Pos)              /*!< 0x00020000 */
+#define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */
+#define SAI_xFRCR_FSOFF_Pos        (18U)
+#define SAI_xFRCR_FSOFF_Msk        (0x1UL << SAI_xFRCR_FSOFF_Pos)              /*!< 0x00040000 */
+#define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */
+
+/* Legacy define */
+#define  SAI_xFRCR_FSPO                      SAI_xFRCR_FSPOL
+
+/******************  Bit definition for SAI_xSLOTR register  *******************/
+#define SAI_xSLOTR_FBOFF_Pos       (0U)
+#define SAI_xSLOTR_FBOFF_Msk       (0x1FUL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x0000001F */
+#define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FBOFF[4:0](First Bit Offset)  */
+#define SAI_xSLOTR_FBOFF_0         (0x01UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */
+#define SAI_xSLOTR_FBOFF_1         (0x02UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */
+#define SAI_xSLOTR_FBOFF_2         (0x04UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */
+#define SAI_xSLOTR_FBOFF_3         (0x08UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */
+#define SAI_xSLOTR_FBOFF_4         (0x10UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */
+
+#define SAI_xSLOTR_SLOTSZ_Pos      (6U)
+#define SAI_xSLOTR_SLOTSZ_Msk      (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x000000C0 */
+#define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */
+#define SAI_xSLOTR_SLOTSZ_0        (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */
+#define SAI_xSLOTR_SLOTSZ_1        (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */
+
+#define SAI_xSLOTR_NBSLOT_Pos      (8U)
+#define SAI_xSLOTR_NBSLOT_Msk      (0xFUL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000F00 */
+#define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
+#define SAI_xSLOTR_NBSLOT_0        (0x1UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */
+#define SAI_xSLOTR_NBSLOT_1        (0x2UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */
+#define SAI_xSLOTR_NBSLOT_2        (0x4UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */
+#define SAI_xSLOTR_NBSLOT_3        (0x8UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */
+
+#define SAI_xSLOTR_SLOTEN_Pos      (16U)
+#define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)         /*!< 0xFFFF0000 */
+#define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */
+
+/*******************  Bit definition for SAI_xIMR register  *******************/
+#define SAI_xIMR_OVRUDRIE_Pos      (0U)
+#define SAI_xIMR_OVRUDRIE_Msk      (0x1UL << SAI_xIMR_OVRUDRIE_Pos)            /*!< 0x00000001 */
+#define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */
+#define SAI_xIMR_MUTEDETIE_Pos     (1U)
+#define SAI_xIMR_MUTEDETIE_Msk     (0x1UL << SAI_xIMR_MUTEDETIE_Pos)           /*!< 0x00000002 */
+#define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */
+#define SAI_xIMR_WCKCFGIE_Pos      (2U)
+#define SAI_xIMR_WCKCFGIE_Msk      (0x1UL << SAI_xIMR_WCKCFGIE_Pos)            /*!< 0x00000004 */
+#define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */
+#define SAI_xIMR_FREQIE_Pos        (3U)
+#define SAI_xIMR_FREQIE_Msk        (0x1UL << SAI_xIMR_FREQIE_Pos)              /*!< 0x00000008 */
+#define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */
+#define SAI_xIMR_CNRDYIE_Pos       (4U)
+#define SAI_xIMR_CNRDYIE_Msk       (0x1UL << SAI_xIMR_CNRDYIE_Pos)             /*!< 0x00000010 */
+#define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */
+#define SAI_xIMR_AFSDETIE_Pos      (5U)
+#define SAI_xIMR_AFSDETIE_Msk      (0x1UL << SAI_xIMR_AFSDETIE_Pos)            /*!< 0x00000020 */
+#define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */
+#define SAI_xIMR_LFSDETIE_Pos      (6U)
+#define SAI_xIMR_LFSDETIE_Msk      (0x1UL << SAI_xIMR_LFSDETIE_Pos)            /*!< 0x00000040 */
+#define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */
+
+/********************  Bit definition for SAI_xSR register  *******************/
+#define SAI_xSR_OVRUDR_Pos         (0U)
+#define SAI_xSR_OVRUDR_Msk         (0x1UL << SAI_xSR_OVRUDR_Pos)               /*!< 0x00000001 */
+#define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */
+#define SAI_xSR_MUTEDET_Pos        (1U)
+#define SAI_xSR_MUTEDET_Msk        (0x1UL << SAI_xSR_MUTEDET_Pos)              /*!< 0x00000002 */
+#define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */
+#define SAI_xSR_WCKCFG_Pos         (2U)
+#define SAI_xSR_WCKCFG_Msk         (0x1UL << SAI_xSR_WCKCFG_Pos)               /*!< 0x00000004 */
+#define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */
+#define SAI_xSR_FREQ_Pos           (3U)
+#define SAI_xSR_FREQ_Msk           (0x1UL << SAI_xSR_FREQ_Pos)                 /*!< 0x00000008 */
+#define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */
+#define SAI_xSR_CNRDY_Pos          (4U)
+#define SAI_xSR_CNRDY_Msk          (0x1UL << SAI_xSR_CNRDY_Pos)                /*!< 0x00000010 */
+#define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */
+#define SAI_xSR_AFSDET_Pos         (5U)
+#define SAI_xSR_AFSDET_Msk         (0x1UL << SAI_xSR_AFSDET_Pos)               /*!< 0x00000020 */
+#define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */
+#define SAI_xSR_LFSDET_Pos         (6U)
+#define SAI_xSR_LFSDET_Msk         (0x1UL << SAI_xSR_LFSDET_Pos)               /*!< 0x00000040 */
+#define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */
+
+#define SAI_xSR_FLVL_Pos           (16U)
+#define SAI_xSR_FLVL_Msk           (0x7UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00070000 */
+#define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */
+#define SAI_xSR_FLVL_0             (0x1UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */
+#define SAI_xSR_FLVL_1             (0x2UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */
+#define SAI_xSR_FLVL_2             (0x4UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */
+
+/******************  Bit definition for SAI_xCLRFR register  ******************/
+#define SAI_xCLRFR_COVRUDR_Pos     (0U)
+#define SAI_xCLRFR_COVRUDR_Msk     (0x1UL << SAI_xCLRFR_COVRUDR_Pos)           /*!< 0x00000001 */
+#define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */
+#define SAI_xCLRFR_CMUTEDET_Pos    (1U)
+#define SAI_xCLRFR_CMUTEDET_Msk    (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)          /*!< 0x00000002 */
+#define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */
+#define SAI_xCLRFR_CWCKCFG_Pos     (2U)
+#define SAI_xCLRFR_CWCKCFG_Msk     (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)           /*!< 0x00000004 */
+#define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */
+#define SAI_xCLRFR_CFREQ_Pos       (3U)
+#define SAI_xCLRFR_CFREQ_Msk       (0x1UL << SAI_xCLRFR_CFREQ_Pos)             /*!< 0x00000008 */
+#define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */
+#define SAI_xCLRFR_CCNRDY_Pos      (4U)
+#define SAI_xCLRFR_CCNRDY_Msk      (0x1UL << SAI_xCLRFR_CCNRDY_Pos)            /*!< 0x00000010 */
+#define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */
+#define SAI_xCLRFR_CAFSDET_Pos     (5U)
+#define SAI_xCLRFR_CAFSDET_Msk     (0x1UL << SAI_xCLRFR_CAFSDET_Pos)           /*!< 0x00000020 */
+#define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */
+#define SAI_xCLRFR_CLFSDET_Pos     (6U)
+#define SAI_xCLRFR_CLFSDET_Msk     (0x1UL << SAI_xCLRFR_CLFSDET_Pos)           /*!< 0x00000040 */
+#define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */
+
+/******************  Bit definition for SAI_xDR register  *********************/
+#define SAI_xDR_DATA_Pos           (0U)
+#define SAI_xDR_DATA_Msk           (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)          /*!< 0xFFFFFFFF */
+#define SAI_xDR_DATA               SAI_xDR_DATA_Msk
+
+/*******************  Bit definition for SAI_PDMCR register  ******************/
+#define SAI_PDMCR_PDMEN_Pos        (0U)
+#define SAI_PDMCR_PDMEN_Msk        (0x1UL << SAI_PDMCR_PDMEN_Pos)              /*!< 0x00000001 */
+#define SAI_PDMCR_PDMEN            SAI_PDMCR_PDMEN_Msk                         /*!<PDM Enable                                          */
+
+#define SAI_PDMCR_MICNBR_Pos       (4U)
+#define SAI_PDMCR_MICNBR_Msk       (0x3UL << SAI_PDMCR_MICNBR_Pos)             /*!< 0x00000030 */
+#define SAI_PDMCR_MICNBR           SAI_PDMCR_MICNBR_Msk                        /*!<Number of microphones                               */
+#define SAI_PDMCR_MICNBR_0         (0x1UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000010 */
+#define SAI_PDMCR_MICNBR_1         (0x2UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000020 */
+
+#define SAI_PDMCR_CKEN1_Pos        (8U)
+#define SAI_PDMCR_CKEN1_Msk        (0x1UL << SAI_PDMCR_CKEN1_Pos)              /*!< 0x00000100 */
+#define SAI_PDMCR_CKEN1            SAI_PDMCR_CKEN1_Msk                         /*!<Clock enable of bitstream clock number 1            */
+#define SAI_PDMCR_CKEN2_Pos        (9U)
+#define SAI_PDMCR_CKEN2_Msk        (0x1UL << SAI_PDMCR_CKEN2_Pos)              /*!< 0x00000200 */
+#define SAI_PDMCR_CKEN2            SAI_PDMCR_CKEN2_Msk                         /*!<Clock enable of bitstream clock number 2            */
+#define SAI_PDMCR_CKEN3_Pos        (10U)
+#define SAI_PDMCR_CKEN3_Msk        (0x1UL << SAI_PDMCR_CKEN3_Pos)              /*!< 0x00000400 */
+#define SAI_PDMCR_CKEN3            SAI_PDMCR_CKEN3_Msk                         /*!<Clock enable of bitstream clock number 3            */
+#define SAI_PDMCR_CKEN4_Pos        (11U)
+#define SAI_PDMCR_CKEN4_Msk        (0x1UL << SAI_PDMCR_CKEN4_Pos)              /*!< 0x00000800 */
+#define SAI_PDMCR_CKEN4            SAI_PDMCR_CKEN4_Msk                         /*!<Clock enable of bitstream clock number 4            */
+
+/******************  Bit definition for SAI_PDMDLY register  ******************/
+#define SAI_PDMDLY_DLYM1L_Pos      (0U)
+#define SAI_PDMDLY_DLYM1L_Msk      (0x7UL << SAI_PDMDLY_DLYM1L_Pos)            /*!< 0x00000007 */
+#define SAI_PDMDLY_DLYM1L          SAI_PDMDLY_DLYM1L_Msk                       /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */
+#define SAI_PDMDLY_DLYM1L_0        (0x1UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000001 */
+#define SAI_PDMDLY_DLYM1L_1        (0x2UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000002 */
+#define SAI_PDMDLY_DLYM1L_2        (0x4UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000004 */
+
+#define SAI_PDMDLY_DLYM1R_Pos      (4U)
+#define SAI_PDMDLY_DLYM1R_Msk      (0x7UL << SAI_PDMDLY_DLYM1R_Pos)            /*!< 0x00000070 */
+#define SAI_PDMDLY_DLYM1R          SAI_PDMDLY_DLYM1R_Msk                       /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */
+#define SAI_PDMDLY_DLYM1R_0        (0x1UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000010 */
+#define SAI_PDMDLY_DLYM1R_1        (0x2UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000020 */
+#define SAI_PDMDLY_DLYM1R_2        (0x4UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000040 */
+
+#define SAI_PDMDLY_DLYM2L_Pos      (8U)
+#define SAI_PDMDLY_DLYM2L_Msk      (0x7UL << SAI_PDMDLY_DLYM2L_Pos)            /*!< 0x00000700 */
+#define SAI_PDMDLY_DLYM2L          SAI_PDMDLY_DLYM2L_Msk                       /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */
+#define SAI_PDMDLY_DLYM2L_0        (0x1UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000100 */
+#define SAI_PDMDLY_DLYM2L_1        (0x2UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000200 */
+#define SAI_PDMDLY_DLYM2L_2        (0x4UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000400 */
+
+#define SAI_PDMDLY_DLYM2R_Pos      (12U)
+#define SAI_PDMDLY_DLYM2R_Msk      (0x7UL << SAI_PDMDLY_DLYM2R_Pos)            /*!< 0x00007000 */
+#define SAI_PDMDLY_DLYM2R          SAI_PDMDLY_DLYM2R_Msk                       /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2)*/
+#define SAI_PDMDLY_DLYM2R_0        (0x1UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00001000 */
+#define SAI_PDMDLY_DLYM2R_1        (0x2UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00002000 */
+#define SAI_PDMDLY_DLYM2R_2        (0x4UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00004000 */
+
+#define SAI_PDMDLY_DLYM3L_Pos      (16U)
+#define SAI_PDMDLY_DLYM3L_Msk      (0x7UL << SAI_PDMDLY_DLYM3L_Pos)            /*!< 0x00070000 */
+#define SAI_PDMDLY_DLYM3L          SAI_PDMDLY_DLYM3L_Msk                       /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3)*/
+#define SAI_PDMDLY_DLYM3L_0        (0x1UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00010000 */
+#define SAI_PDMDLY_DLYM3L_1        (0x2UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00020000 */
+#define SAI_PDMDLY_DLYM3L_2        (0x4UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00040000 */
+
+#define SAI_PDMDLY_DLYM3R_Pos      (20U)
+#define SAI_PDMDLY_DLYM3R_Msk      (0x7UL << SAI_PDMDLY_DLYM3R_Pos)            /*!< 0x00700000 */
+#define SAI_PDMDLY_DLYM3R          SAI_PDMDLY_DLYM3R_Msk                       /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3)*/
+#define SAI_PDMDLY_DLYM3R_0        (0x1UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00100000 */
+#define SAI_PDMDLY_DLYM3R_1        (0x2UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00200000 */
+#define SAI_PDMDLY_DLYM3R_2        (0x4UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00400000 */
+
+#define SAI_PDMDLY_DLYM4L_Pos      (24U)
+#define SAI_PDMDLY_DLYM4L_Msk      (0x7UL << SAI_PDMDLY_DLYM4L_Pos)            /*!< 0x07000000 */
+#define SAI_PDMDLY_DLYM4L          SAI_PDMDLY_DLYM4L_Msk                       /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4)*/
+#define SAI_PDMDLY_DLYM4L_0        (0x1UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x01000000 */
+#define SAI_PDMDLY_DLYM4L_1        (0x2UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x02000000 */
+#define SAI_PDMDLY_DLYM4L_2        (0x4UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x04000000 */
+
+#define SAI_PDMDLY_DLYM4R_Pos      (28U)
+#define SAI_PDMDLY_DLYM4R_Msk      (0x7UL << SAI_PDMDLY_DLYM4R_Pos)            /*!< 0x70000000 */
+#define SAI_PDMDLY_DLYM4R          SAI_PDMDLY_DLYM4R_Msk                       /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4)*/
+#define SAI_PDMDLY_DLYM4R_0        (0x1UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x10000000 */
+#define SAI_PDMDLY_DLYM4R_1        (0x2UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x20000000 */
+#define SAI_PDMDLY_DLYM4R_2        (0x4UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x40000000 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           SDMMC Interface                                  */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SDMMC_POWER register  ******************/
+#define SDMMC_POWER_PWRCTRL_Pos          (0U)
+#define SDMMC_POWER_PWRCTRL_Msk          (0x3UL << SDMMC_POWER_PWRCTRL_Pos)    /*!< 0x00000003 */
+#define SDMMC_POWER_PWRCTRL              SDMMC_POWER_PWRCTRL_Msk               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDMMC_POWER_PWRCTRL_0            (0x1UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000001 */
+#define SDMMC_POWER_PWRCTRL_1            (0x2UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000002 */
+#define SDMMC_POWER_VSWITCH_Pos          (2U)
+#define SDMMC_POWER_VSWITCH_Msk          (0x1UL << SDMMC_POWER_VSWITCH_Pos)    /*!< 0x00000004 */
+#define SDMMC_POWER_VSWITCH              SDMMC_POWER_VSWITCH_Msk               /*!<Voltage switch sequence start */
+#define SDMMC_POWER_VSWITCHEN_Pos        (3U)
+#define SDMMC_POWER_VSWITCHEN_Msk        (0x1UL << SDMMC_POWER_VSWITCHEN_Pos)  /*!< 0x00000008 */
+#define SDMMC_POWER_VSWITCHEN            SDMMC_POWER_VSWITCHEN_Msk             /*!<Voltage switch procedure enable */
+#define SDMMC_POWER_DIRPOL_Pos           (4U)
+#define SDMMC_POWER_DIRPOL_Msk           (0x1UL << SDMMC_POWER_DIRPOL_Pos)     /*!< 0x00000010 */
+#define SDMMC_POWER_DIRPOL               SDMMC_POWER_DIRPOL_Msk                /*!<Data and Command direction signals polarity selection */
+
+/******************  Bit definition for SDMMC_CLKCR register  ******************/
+#define SDMMC_CLKCR_CLKDIV_Pos           (0U)
+#define SDMMC_CLKCR_CLKDIV_Msk           (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos)   /*!< 0x000003FF */
+#define SDMMC_CLKCR_CLKDIV               SDMMC_CLKCR_CLKDIV_Msk                /*!<Clock divide factor             */
+#define SDMMC_CLKCR_PWRSAV_Pos           (12U)
+#define SDMMC_CLKCR_PWRSAV_Msk           (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)     /*!< 0x00001000 */
+#define SDMMC_CLKCR_PWRSAV               SDMMC_CLKCR_PWRSAV_Msk                /*!<Power saving configuration bit  */
+
+#define SDMMC_CLKCR_WIDBUS_Pos           (14U)
+#define SDMMC_CLKCR_WIDBUS_Msk           (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)     /*!< 0x0000C000 */
+#define SDMMC_CLKCR_WIDBUS               SDMMC_CLKCR_WIDBUS_Msk                /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDMMC_CLKCR_WIDBUS_0             (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00004000 */
+#define SDMMC_CLKCR_WIDBUS_1             (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00008000 */
+
+#define SDMMC_CLKCR_NEGEDGE_Pos          (16U)
+#define SDMMC_CLKCR_NEGEDGE_Msk          (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)    /*!< 0x00010000 */
+#define SDMMC_CLKCR_NEGEDGE              SDMMC_CLKCR_NEGEDGE_Msk               /*!<SDMMC_CK dephasing selection bit */
+#define SDMMC_CLKCR_HWFC_EN_Pos          (17U)
+#define SDMMC_CLKCR_HWFC_EN_Msk          (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)    /*!< 0x00020000 */
+#define SDMMC_CLKCR_HWFC_EN              SDMMC_CLKCR_HWFC_EN_Msk               /*!<HW Flow Control enable           */
+#define SDMMC_CLKCR_DDR_Pos              (18U)
+#define SDMMC_CLKCR_DDR_Msk              (0x1UL << SDMMC_CLKCR_DDR_Pos)        /*!< 0x00040000 */
+#define SDMMC_CLKCR_DDR                  SDMMC_CLKCR_DDR_Msk                   /*!<Data rate signaling selection    */
+#define SDMMC_CLKCR_BUSSPEED_Pos         (19U)
+#define SDMMC_CLKCR_BUSSPEED_Msk         (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos)   /*!< 0x00080000 */
+#define SDMMC_CLKCR_BUSSPEED             SDMMC_CLKCR_BUSSPEED_Msk              /*!<Bus speed mode selection         */
+#define SDMMC_CLKCR_SELCLKRX_Pos         (20U)
+#define SDMMC_CLKCR_SELCLKRX_Msk         (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos)   /*!< 0x00300000 */
+#define SDMMC_CLKCR_SELCLKRX             SDMMC_CLKCR_SELCLKRX_Msk              /*!<SELCLKRX[1:0] bits (Receive clock selection) */
+#define SDMMC_CLKCR_SELCLKRX_0           (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00100000 */
+#define SDMMC_CLKCR_SELCLKRX_1           (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00200000 */
+
+/*******************  Bit definition for SDMMC_ARG register  *******************/
+#define SDMMC_ARG_CMDARG_Pos             (0U)
+#define SDMMC_ARG_CMDARG_Msk             (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_ARG_CMDARG                 SDMMC_ARG_CMDARG_Msk                  /*!<Command argument */
+
+/*******************  Bit definition for SDMMC_CMD register  *******************/
+#define SDMMC_CMD_CMDINDEX_Pos           (0U)
+#define SDMMC_CMD_CMDINDEX_Msk           (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)    /*!< 0x0000003F */
+#define SDMMC_CMD_CMDINDEX               SDMMC_CMD_CMDINDEX_Msk                /*!<Command Index                               */
+#define SDMMC_CMD_CMDTRANS_Pos           (6U)
+#define SDMMC_CMD_CMDTRANS_Msk           (0x1UL << SDMMC_CMD_CMDTRANS_Pos)     /*!< 0x00000040 */
+#define SDMMC_CMD_CMDTRANS               SDMMC_CMD_CMDTRANS_Msk                /*!<CPSM Treats command as a Data Transfer      */
+#define SDMMC_CMD_CMDSTOP_Pos            (7U)
+#define SDMMC_CMD_CMDSTOP_Msk            (0x1UL << SDMMC_CMD_CMDSTOP_Pos)      /*!< 0x00000080 */
+#define SDMMC_CMD_CMDSTOP                SDMMC_CMD_CMDSTOP_Msk                 /*!<CPSM Treats command as a Stop               */
+
+#define SDMMC_CMD_WAITRESP_Pos           (8U)
+#define SDMMC_CMD_WAITRESP_Msk           (0x3UL << SDMMC_CMD_WAITRESP_Pos)     /*!< 0x00000300 */
+#define SDMMC_CMD_WAITRESP               SDMMC_CMD_WAITRESP_Msk                /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDMMC_CMD_WAITRESP_0             (0x1UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000100 */
+#define SDMMC_CMD_WAITRESP_1             (0x2UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000200 */
+
+#define SDMMC_CMD_WAITINT_Pos            (10U)
+#define SDMMC_CMD_WAITINT_Msk            (0x1UL << SDMMC_CMD_WAITINT_Pos)      /*!< 0x00000400 */
+#define SDMMC_CMD_WAITINT                SDMMC_CMD_WAITINT_Msk                 /*!<CPSM Waits for Interrupt Request                               */
+#define SDMMC_CMD_WAITPEND_Pos           (11U)
+#define SDMMC_CMD_WAITPEND_Msk           (0x1UL << SDMMC_CMD_WAITPEND_Pos)     /*!< 0x00000800 */
+#define SDMMC_CMD_WAITPEND               SDMMC_CMD_WAITPEND_Msk                /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDMMC_CMD_CPSMEN_Pos             (12U)
+#define SDMMC_CMD_CPSMEN_Msk             (0x1UL << SDMMC_CMD_CPSMEN_Pos)       /*!< 0x00001000 */
+#define SDMMC_CMD_CPSMEN                 SDMMC_CMD_CPSMEN_Msk                  /*!<Command path state machine (CPSM) Enable bit                   */
+#define SDMMC_CMD_DTHOLD_Pos             (13U)
+#define SDMMC_CMD_DTHOLD_Msk             (0x1UL << SDMMC_CMD_DTHOLD_Pos)       /*!< 0x00002000 */
+#define SDMMC_CMD_DTHOLD                 SDMMC_CMD_DTHOLD_Msk                  /*!<Hold new data block transmission and reception in the DPSM     */
+#define SDMMC_CMD_BOOTMODE_Pos           (14U)
+#define SDMMC_CMD_BOOTMODE_Msk           (0x1UL << SDMMC_CMD_BOOTMODE_Pos)     /*!< 0x00004000 */
+#define SDMMC_CMD_BOOTMODE               SDMMC_CMD_BOOTMODE_Msk                /*!<Boot mode                                                      */
+#define SDMMC_CMD_BOOTEN_Pos             (15U)
+#define SDMMC_CMD_BOOTEN_Msk             (0x1UL << SDMMC_CMD_BOOTEN_Pos)       /*!< 0x00008000 */
+#define SDMMC_CMD_BOOTEN                 SDMMC_CMD_BOOTEN_Msk                  /*!<Enable Boot mode procedure                                     */
+#define SDMMC_CMD_CMDSUSPEND_Pos         (16U)
+#define SDMMC_CMD_CMDSUSPEND_Msk         (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos)   /*!< 0x00010000 */
+#define SDMMC_CMD_CMDSUSPEND             SDMMC_CMD_CMDSUSPEND_Msk              /*!<CPSM Treats command as a Suspend or Resume command             */
+
+/*****************  Bit definition for SDMMC_RESPCMD register  *****************/
+#define SDMMC_RESPCMD_RESPCMD_Pos        (0U)
+#define SDMMC_RESPCMD_RESPCMD_Msk        (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
+#define SDMMC_RESPCMD_RESPCMD            SDMMC_RESPCMD_RESPCMD_Msk             /*!<Response command index */
+
+/******************  Bit definition for SDMMC_RESP0 register  ******************/
+#define SDMMC_RESP0_CARDSTATUS0_Pos      (0U)
+#define SDMMC_RESP0_CARDSTATUS0_Msk      (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP0_CARDSTATUS0          SDMMC_RESP0_CARDSTATUS0_Msk           /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP1 register  ******************/
+#define SDMMC_RESP1_CARDSTATUS1_Pos      (0U)
+#define SDMMC_RESP1_CARDSTATUS1_Msk      (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP1_CARDSTATUS1          SDMMC_RESP1_CARDSTATUS1_Msk           /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP2 register  ******************/
+#define SDMMC_RESP2_CARDSTATUS2_Pos      (0U)
+#define SDMMC_RESP2_CARDSTATUS2_Msk      (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP2_CARDSTATUS2          SDMMC_RESP2_CARDSTATUS2_Msk           /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP3 register  ******************/
+#define SDMMC_RESP3_CARDSTATUS3_Pos      (0U)
+#define SDMMC_RESP3_CARDSTATUS3_Msk      (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP3_CARDSTATUS3          SDMMC_RESP3_CARDSTATUS3_Msk           /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP4 register  ******************/
+#define SDMMC_RESP4_CARDSTATUS4_Pos      (0U)
+#define SDMMC_RESP4_CARDSTATUS4_Msk      (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP4_CARDSTATUS4          SDMMC_RESP4_CARDSTATUS4_Msk           /*!<Card Status */
+
+/******************  Bit definition for SDMMC_DTIMER register  *****************/
+#define SDMMC_DTIMER_DATATIME_Pos        (0U)
+#define SDMMC_DTIMER_DATATIME_Msk        (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_DTIMER_DATATIME            SDMMC_DTIMER_DATATIME_Msk             /*!<Data timeout period. */
+
+/******************  Bit definition for SDMMC_DLEN register  *******************/
+#define SDMMC_DLEN_DATALENGTH_Pos        (0U)
+#define SDMMC_DLEN_DATALENGTH_Msk        (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_DLEN_DATALENGTH            SDMMC_DLEN_DATALENGTH_Msk             /*!<Data length value    */
+
+/******************  Bit definition for SDMMC_DCTRL register  ******************/
+#define SDMMC_DCTRL_DTEN_Pos             (0U)
+#define SDMMC_DCTRL_DTEN_Msk             (0x1UL << SDMMC_DCTRL_DTEN_Pos)       /*!< 0x00000001 */
+#define SDMMC_DCTRL_DTEN                 SDMMC_DCTRL_DTEN_Msk                  /*!<Data transfer enabled bit                */
+#define SDMMC_DCTRL_DTDIR_Pos            (1U)
+#define SDMMC_DCTRL_DTDIR_Msk            (0x1UL << SDMMC_DCTRL_DTDIR_Pos)      /*!< 0x00000002 */
+#define SDMMC_DCTRL_DTDIR                SDMMC_DCTRL_DTDIR_Msk                 /*!<Data transfer direction selection        */
+#define SDMMC_DCTRL_DTMODE_Pos           (2U)
+#define SDMMC_DCTRL_DTMODE_Msk           (0x3UL << SDMMC_DCTRL_DTMODE_Pos)     /*!< 0x0000000C */
+#define SDMMC_DCTRL_DTMODE               SDMMC_DCTRL_DTMODE_Msk                /*!<DTMODE[1:0] Data transfer mode selection */
+#define SDMMC_DCTRL_DTMODE_0             (0x1UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000004 */
+#define SDMMC_DCTRL_DTMODE_1             (0x2UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000008 */
+
+#define SDMMC_DCTRL_DBLOCKSIZE_Pos       (4U)
+#define SDMMC_DCTRL_DBLOCKSIZE_Msk       (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
+#define SDMMC_DCTRL_DBLOCKSIZE           SDMMC_DCTRL_DBLOCKSIZE_Msk            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDMMC_DCTRL_DBLOCKSIZE_0         (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000010 */
+#define SDMMC_DCTRL_DBLOCKSIZE_1         (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000020 */
+#define SDMMC_DCTRL_DBLOCKSIZE_2         (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000040 */
+#define SDMMC_DCTRL_DBLOCKSIZE_3         (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000080 */
+
+#define SDMMC_DCTRL_RWSTART_Pos          (8U)
+#define SDMMC_DCTRL_RWSTART_Msk          (0x1UL << SDMMC_DCTRL_RWSTART_Pos)    /*!< 0x00000100 */
+#define SDMMC_DCTRL_RWSTART              SDMMC_DCTRL_RWSTART_Msk               /*!<Read wait start                                 */
+#define SDMMC_DCTRL_RWSTOP_Pos           (9U)
+#define SDMMC_DCTRL_RWSTOP_Msk           (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)     /*!< 0x00000200 */
+#define SDMMC_DCTRL_RWSTOP               SDMMC_DCTRL_RWSTOP_Msk                /*!<Read wait stop                                  */
+#define SDMMC_DCTRL_RWMOD_Pos            (10U)
+#define SDMMC_DCTRL_RWMOD_Msk            (0x1UL << SDMMC_DCTRL_RWMOD_Pos)      /*!< 0x00000400 */
+#define SDMMC_DCTRL_RWMOD                SDMMC_DCTRL_RWMOD_Msk                 /*!<Read wait mode                                  */
+#define SDMMC_DCTRL_SDIOEN_Pos           (11U)
+#define SDMMC_DCTRL_SDIOEN_Msk           (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)     /*!< 0x00000800 */
+#define SDMMC_DCTRL_SDIOEN               SDMMC_DCTRL_SDIOEN_Msk                /*!<SD I/O enable functions                         */
+#define SDMMC_DCTRL_BOOTACKEN_Pos        (12U)
+#define SDMMC_DCTRL_BOOTACKEN_Msk        (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos)  /*!< 0x00001000 */
+#define SDMMC_DCTRL_BOOTACKEN            SDMMC_DCTRL_BOOTACKEN_Msk             /*!<Enable the reception of the Boot Acknowledgment */
+#define SDMMC_DCTRL_FIFORST_Pos          (13U)
+#define SDMMC_DCTRL_FIFORST_Msk          (0x1UL << SDMMC_DCTRL_FIFORST_Pos)    /*!< 0x00002000 */
+#define SDMMC_DCTRL_FIFORST              SDMMC_DCTRL_FIFORST_Msk               /*!<FIFO reset                                      */
+
+/******************  Bit definition for SDMMC_DCOUNT register  *****************/
+#define SDMMC_DCOUNT_DATACOUNT_Pos       (0U)
+#define SDMMC_DCOUNT_DATACOUNT_Msk       (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_DCOUNT_DATACOUNT           SDMMC_DCOUNT_DATACOUNT_Msk            /*!<Data count value */
+
+/******************  Bit definition for SDMMC_STA register  ********************/
+#define SDMMC_STA_CCRCFAIL_Pos           (0U)
+#define SDMMC_STA_CCRCFAIL_Msk           (0x1UL << SDMMC_STA_CCRCFAIL_Pos)     /*!< 0x00000001 */
+#define SDMMC_STA_CCRCFAIL               SDMMC_STA_CCRCFAIL_Msk                /*!<Command response received (CRC check failed)  */
+#define SDMMC_STA_DCRCFAIL_Pos           (1U)
+#define SDMMC_STA_DCRCFAIL_Msk           (0x1UL << SDMMC_STA_DCRCFAIL_Pos)     /*!< 0x00000002 */
+#define SDMMC_STA_DCRCFAIL               SDMMC_STA_DCRCFAIL_Msk                /*!<Data block sent/received (CRC check failed)   */
+#define SDMMC_STA_CTIMEOUT_Pos           (2U)
+#define SDMMC_STA_CTIMEOUT_Msk           (0x1UL << SDMMC_STA_CTIMEOUT_Pos)     /*!< 0x00000004 */
+#define SDMMC_STA_CTIMEOUT               SDMMC_STA_CTIMEOUT_Msk                /*!<Command response timeout                      */
+#define SDMMC_STA_DTIMEOUT_Pos           (3U)
+#define SDMMC_STA_DTIMEOUT_Msk           (0x1UL << SDMMC_STA_DTIMEOUT_Pos)     /*!< 0x00000008 */
+#define SDMMC_STA_DTIMEOUT               SDMMC_STA_DTIMEOUT_Msk                /*!<Data timeout                                  */
+#define SDMMC_STA_TXUNDERR_Pos           (4U)
+#define SDMMC_STA_TXUNDERR_Msk           (0x1UL << SDMMC_STA_TXUNDERR_Pos)     /*!< 0x00000010 */
+#define SDMMC_STA_TXUNDERR               SDMMC_STA_TXUNDERR_Msk                /*!<Transmit FIFO underrun error                  */
+#define SDMMC_STA_RXOVERR_Pos            (5U)
+#define SDMMC_STA_RXOVERR_Msk            (0x1UL << SDMMC_STA_RXOVERR_Pos)      /*!< 0x00000020 */
+#define SDMMC_STA_RXOVERR                SDMMC_STA_RXOVERR_Msk                 /*!<Received FIFO overrun error                   */
+#define SDMMC_STA_CMDREND_Pos            (6U)
+#define SDMMC_STA_CMDREND_Msk            (0x1UL << SDMMC_STA_CMDREND_Pos)      /*!< 0x00000040 */
+#define SDMMC_STA_CMDREND                SDMMC_STA_CMDREND_Msk                 /*!<Command response received (CRC check passed)  */
+#define SDMMC_STA_CMDSENT_Pos            (7U)
+#define SDMMC_STA_CMDSENT_Msk            (0x1UL << SDMMC_STA_CMDSENT_Pos)      /*!< 0x00000080 */
+#define SDMMC_STA_CMDSENT                SDMMC_STA_CMDSENT_Msk                 /*!<Command sent (no response required)           */
+#define SDMMC_STA_DATAEND_Pos            (8U)
+#define SDMMC_STA_DATAEND_Msk            (0x1UL << SDMMC_STA_DATAEND_Pos)      /*!< 0x00000100 */
+#define SDMMC_STA_DATAEND                SDMMC_STA_DATAEND_Msk                 /*!<Data end (data counter, SDIDCOUNT, is zero)   */
+#define SDMMC_STA_DHOLD_Pos              (9U)
+#define SDMMC_STA_DHOLD_Msk              (0x1UL << SDMMC_STA_DHOLD_Pos)        /*!< 0x00000200 */
+#define SDMMC_STA_DHOLD                  SDMMC_STA_DHOLD_Msk                   /*!<Data transfer Hold                                                      */
+#define SDMMC_STA_DBCKEND_Pos            (10U)
+#define SDMMC_STA_DBCKEND_Msk            (0x1UL << SDMMC_STA_DBCKEND_Pos)      /*!< 0x00000400 */
+#define SDMMC_STA_DBCKEND                SDMMC_STA_DBCKEND_Msk                 /*!<Data block sent/received (CRC check passed)   */
+#define SDMMC_STA_DABORT_Pos             (11U)
+#define SDMMC_STA_DABORT_Msk             (0x1UL << SDMMC_STA_DABORT_Pos)       /*!< 0x00000800 */
+#define SDMMC_STA_DABORT                 SDMMC_STA_DABORT_Msk                  /*!<Data transfer aborted by CMD12                                          */
+#define SDMMC_STA_DPSMACT_Pos            (12U)
+#define SDMMC_STA_DPSMACT_Msk            (0x1UL << SDMMC_STA_DPSMACT_Pos)      /*!< 0x00001000 */
+#define SDMMC_STA_DPSMACT                SDMMC_STA_DPSMACT_Msk                 /*!<Data path state machine active                                       */
+#define SDMMC_STA_CPSMACT_Pos            (13U)
+#define SDMMC_STA_CPSMACT_Msk            (0x1UL << SDMMC_STA_CPSMACT_Pos)      /*!< 0x00002000 */
+#define SDMMC_STA_CPSMACT                SDMMC_STA_CPSMACT_Msk                 /*!<Command path state machine active                                          */
+#define SDMMC_STA_TXFIFOHE_Pos           (14U)
+#define SDMMC_STA_TXFIFOHE_Msk           (0x1UL << SDMMC_STA_TXFIFOHE_Pos)     /*!< 0x00004000 */
+#define SDMMC_STA_TXFIFOHE               SDMMC_STA_TXFIFOHE_Msk                /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDMMC_STA_RXFIFOHF_Pos           (15U)
+#define SDMMC_STA_RXFIFOHF_Msk           (0x1UL << SDMMC_STA_RXFIFOHF_Pos)     /*!< 0x00008000 */
+#define SDMMC_STA_RXFIFOHF               SDMMC_STA_RXFIFOHF_Msk                /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDMMC_STA_TXFIFOF_Pos            (16U)
+#define SDMMC_STA_TXFIFOF_Msk            (0x1UL << SDMMC_STA_TXFIFOF_Pos)      /*!< 0x00010000 */
+#define SDMMC_STA_TXFIFOF                SDMMC_STA_TXFIFOF_Msk                 /*!<Transmit FIFO full                            */
+#define SDMMC_STA_RXFIFOF_Pos            (17U)
+#define SDMMC_STA_RXFIFOF_Msk            (0x1UL << SDMMC_STA_RXFIFOF_Pos)      /*!< 0x00020000 */
+#define SDMMC_STA_RXFIFOF                SDMMC_STA_RXFIFOF_Msk                 /*!<Receive FIFO full                             */
+#define SDMMC_STA_TXFIFOE_Pos            (18U)
+#define SDMMC_STA_TXFIFOE_Msk            (0x1UL << SDMMC_STA_TXFIFOE_Pos)      /*!< 0x00040000 */
+#define SDMMC_STA_TXFIFOE                SDMMC_STA_TXFIFOE_Msk                 /*!<Transmit FIFO empty                           */
+#define SDMMC_STA_RXFIFOE_Pos            (19U)
+#define SDMMC_STA_RXFIFOE_Msk            (0x1UL << SDMMC_STA_RXFIFOE_Pos)      /*!< 0x00080000 */
+#define SDMMC_STA_RXFIFOE                SDMMC_STA_RXFIFOE_Msk                 /*!<Receive FIFO empty                            */
+#define SDMMC_STA_BUSYD0_Pos             (20U)
+#define SDMMC_STA_BUSYD0_Msk             (0x1UL << SDMMC_STA_BUSYD0_Pos)       /*!< 0x00100000 */
+#define SDMMC_STA_BUSYD0                 SDMMC_STA_BUSYD0_Msk                  /*!<Inverted value of SDMMC_D0 line (Busy)                                  */
+#define SDMMC_STA_BUSYD0END_Pos          (21U)
+#define SDMMC_STA_BUSYD0END_Msk          (0x1UL << SDMMC_STA_BUSYD0END_Pos)    /*!< 0x00200000 */
+#define SDMMC_STA_BUSYD0END              SDMMC_STA_BUSYD0END_Msk               /*!<End of SDMMC_D0 Busy following a CMD response detected                  */
+#define SDMMC_STA_SDIOIT_Pos             (22U)
+#define SDMMC_STA_SDIOIT_Msk             (0x1UL << SDMMC_STA_SDIOIT_Pos)       /*!< 0x00400000 */
+#define SDMMC_STA_SDIOIT                 SDMMC_STA_SDIOIT_Msk                  /*!<SDIO interrupt received                                                 */
+#define SDMMC_STA_ACKFAIL_Pos            (23U)
+#define SDMMC_STA_ACKFAIL_Msk            (0x1UL << SDMMC_STA_ACKFAIL_Pos)      /*!< 0x00800000 */
+#define SDMMC_STA_ACKFAIL                SDMMC_STA_ACKFAIL_Msk                 /*!<Boot Acknowledgment received (BootAck check fail)                       */
+#define SDMMC_STA_ACKTIMEOUT_Pos         (24U)
+#define SDMMC_STA_ACKTIMEOUT_Msk         (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos)   /*!< 0x01000000 */
+#define SDMMC_STA_ACKTIMEOUT             SDMMC_STA_ACKTIMEOUT_Msk              /*!<Boot Acknowledgment timeout                                             */
+#define SDMMC_STA_VSWEND_Pos             (25U)
+#define SDMMC_STA_VSWEND_Msk             (0x1UL << SDMMC_STA_VSWEND_Pos)       /*!< 0x02000000 */
+#define SDMMC_STA_VSWEND                 SDMMC_STA_VSWEND_Msk                  /*!<Voltage switch critical timing section completion                       */
+#define SDMMC_STA_CKSTOP_Pos             (26U)
+#define SDMMC_STA_CKSTOP_Msk             (0x1UL << SDMMC_STA_CKSTOP_Pos)       /*!< 0x04000000 */
+#define SDMMC_STA_CKSTOP                 SDMMC_STA_CKSTOP_Msk                  /*!<SDMMC_CK stopped in Voltage switch procedure                            */
+#define SDMMC_STA_IDMATE_Pos             (27U)
+#define SDMMC_STA_IDMATE_Msk             (0x1UL << SDMMC_STA_IDMATE_Pos)       /*!< 0x08000000 */
+#define SDMMC_STA_IDMATE                 SDMMC_STA_IDMATE_Msk                  /*!<IDMA transfer error                                                     */
+#define SDMMC_STA_IDMABTC_Pos            (28U)
+#define SDMMC_STA_IDMABTC_Msk            (0x1UL << SDMMC_STA_IDMABTC_Pos)      /*!< 0x10000000 */
+#define SDMMC_STA_IDMABTC                SDMMC_STA_IDMABTC_Msk                 /*!<IDMA buffer transfer complete                                           */
+
+/*******************  Bit definition for SDMMC_ICR register  *******************/
+#define SDMMC_ICR_CCRCFAILC_Pos          (0U)
+#define SDMMC_ICR_CCRCFAILC_Msk          (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)    /*!< 0x00000001 */
+#define SDMMC_ICR_CCRCFAILC              SDMMC_ICR_CCRCFAILC_Msk               /*!<CCRCFAIL flag clear bit */
+#define SDMMC_ICR_DCRCFAILC_Pos          (1U)
+#define SDMMC_ICR_DCRCFAILC_Msk          (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)    /*!< 0x00000002 */
+#define SDMMC_ICR_DCRCFAILC              SDMMC_ICR_DCRCFAILC_Msk               /*!<DCRCFAIL flag clear bit */
+#define SDMMC_ICR_CTIMEOUTC_Pos          (2U)
+#define SDMMC_ICR_CTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)    /*!< 0x00000004 */
+#define SDMMC_ICR_CTIMEOUTC              SDMMC_ICR_CTIMEOUTC_Msk               /*!<CTIMEOUT flag clear bit */
+#define SDMMC_ICR_DTIMEOUTC_Pos          (3U)
+#define SDMMC_ICR_DTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)    /*!< 0x00000008 */
+#define SDMMC_ICR_DTIMEOUTC              SDMMC_ICR_DTIMEOUTC_Msk               /*!<DTIMEOUT flag clear bit */
+#define SDMMC_ICR_TXUNDERRC_Pos          (4U)
+#define SDMMC_ICR_TXUNDERRC_Msk          (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)    /*!< 0x00000010 */
+#define SDMMC_ICR_TXUNDERRC              SDMMC_ICR_TXUNDERRC_Msk               /*!<TXUNDERR flag clear bit */
+#define SDMMC_ICR_RXOVERRC_Pos           (5U)
+#define SDMMC_ICR_RXOVERRC_Msk           (0x1UL << SDMMC_ICR_RXOVERRC_Pos)     /*!< 0x00000020 */
+#define SDMMC_ICR_RXOVERRC               SDMMC_ICR_RXOVERRC_Msk                /*!<RXOVERR flag clear bit  */
+#define SDMMC_ICR_CMDRENDC_Pos           (6U)
+#define SDMMC_ICR_CMDRENDC_Msk           (0x1UL << SDMMC_ICR_CMDRENDC_Pos)     /*!< 0x00000040 */
+#define SDMMC_ICR_CMDRENDC               SDMMC_ICR_CMDRENDC_Msk                /*!<CMDREND flag clear bit  */
+#define SDMMC_ICR_CMDSENTC_Pos           (7U)
+#define SDMMC_ICR_CMDSENTC_Msk           (0x1UL << SDMMC_ICR_CMDSENTC_Pos)     /*!< 0x00000080 */
+#define SDMMC_ICR_CMDSENTC               SDMMC_ICR_CMDSENTC_Msk                /*!<CMDSENT flag clear bit  */
+#define SDMMC_ICR_DATAENDC_Pos           (8U)
+#define SDMMC_ICR_DATAENDC_Msk           (0x1UL << SDMMC_ICR_DATAENDC_Pos)     /*!< 0x00000100 */
+#define SDMMC_ICR_DATAENDC               SDMMC_ICR_DATAENDC_Msk                /*!<DATAEND flag clear bit  */
+#define SDMMC_ICR_DHOLDC_Pos             (9U)
+#define SDMMC_ICR_DHOLDC_Msk             (0x1UL << SDMMC_ICR_DHOLDC_Pos)       /*!< 0x00000200 */
+#define SDMMC_ICR_DHOLDC                 SDMMC_ICR_DHOLDC_Msk                  /*!<DHOLD flag clear bit       */
+#define SDMMC_ICR_DBCKENDC_Pos           (10U)
+#define SDMMC_ICR_DBCKENDC_Msk           (0x1UL << SDMMC_ICR_DBCKENDC_Pos)     /*!< 0x00000400 */
+#define SDMMC_ICR_DBCKENDC               SDMMC_ICR_DBCKENDC_Msk                /*!<DBCKEND flag clear bit  */
+#define SDMMC_ICR_DABORTC_Pos            (11U)
+#define SDMMC_ICR_DABORTC_Msk            (0x1UL << SDMMC_ICR_DABORTC_Pos)      /*!< 0x00000800 */
+#define SDMMC_ICR_DABORTC                SDMMC_ICR_DABORTC_Msk                 /*!<DABORTC flag clear bit     */
+#define SDMMC_ICR_BUSYD0ENDC_Pos         (21U)
+#define SDMMC_ICR_BUSYD0ENDC_Msk         (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos)   /*!< 0x00200000 */
+#define SDMMC_ICR_BUSYD0ENDC             SDMMC_ICR_BUSYD0ENDC_Msk              /*!<BUSYD0ENDC flag clear bit  */
+#define SDMMC_ICR_SDIOITC_Pos            (22U)
+#define SDMMC_ICR_SDIOITC_Msk            (0x1UL << SDMMC_ICR_SDIOITC_Pos)      /*!< 0x00400000 */
+#define SDMMC_ICR_SDIOITC                SDMMC_ICR_SDIOITC_Msk                 /*!<SDIOIT flag clear bit      */
+#define SDMMC_ICR_ACKFAILC_Pos           (23U)
+#define SDMMC_ICR_ACKFAILC_Msk           (0x1UL << SDMMC_ICR_ACKFAILC_Pos)     /*!< 0x00800000 */
+#define SDMMC_ICR_ACKFAILC               SDMMC_ICR_ACKFAILC_Msk                /*!<ACKFAILC flag clear bit    */
+#define SDMMC_ICR_ACKTIMEOUTC_Pos        (24U)
+#define SDMMC_ICR_ACKTIMEOUTC_Msk        (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos)  /*!< 0x01000000 */
+#define SDMMC_ICR_ACKTIMEOUTC            SDMMC_ICR_ACKTIMEOUTC_Msk             /*!<ACKTIMEOUTC flag clear bit */
+#define SDMMC_ICR_VSWENDC_Pos            (25U)
+#define SDMMC_ICR_VSWENDC_Msk            (0x1UL << SDMMC_ICR_VSWENDC_Pos)      /*!< 0x02000000 */
+#define SDMMC_ICR_VSWENDC                SDMMC_ICR_VSWENDC_Msk                 /*!<VSWENDC flag clear bit     */
+#define SDMMC_ICR_CKSTOPC_Pos            (26U)
+#define SDMMC_ICR_CKSTOPC_Msk            (0x1UL << SDMMC_ICR_CKSTOPC_Pos)      /*!< 0x04000000 */
+#define SDMMC_ICR_CKSTOPC                SDMMC_ICR_CKSTOPC_Msk                 /*!<CKSTOPC flag clear bit     */
+#define SDMMC_ICR_IDMATEC_Pos            (27U)
+#define SDMMC_ICR_IDMATEC_Msk            (0x1UL << SDMMC_ICR_IDMATEC_Pos)      /*!< 0x08000000 */
+#define SDMMC_ICR_IDMATEC                SDMMC_ICR_IDMATEC_Msk                 /*!<IDMATEC flag clear bit     */
+#define SDMMC_ICR_IDMABTCC_Pos           (28U)
+#define SDMMC_ICR_IDMABTCC_Msk           (0x1UL << SDMMC_ICR_IDMABTCC_Pos)     /*!< 0x10000000 */
+#define SDMMC_ICR_IDMABTCC               SDMMC_ICR_IDMABTCC_Msk                /*!<IDMABTCC flag clear bit    */
+
+/******************  Bit definition for SDMMC_MASK register  *******************/
+#define SDMMC_MASK_CCRCFAILIE_Pos        (0U)
+#define SDMMC_MASK_CCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)  /*!< 0x00000001 */
+#define SDMMC_MASK_CCRCFAILIE            SDMMC_MASK_CCRCFAILIE_Msk             /*!<Command CRC Fail Interrupt Enable          */
+#define SDMMC_MASK_DCRCFAILIE_Pos        (1U)
+#define SDMMC_MASK_DCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)  /*!< 0x00000002 */
+#define SDMMC_MASK_DCRCFAILIE            SDMMC_MASK_DCRCFAILIE_Msk             /*!<Data CRC Fail Interrupt Enable             */
+#define SDMMC_MASK_CTIMEOUTIE_Pos        (2U)
+#define SDMMC_MASK_CTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)  /*!< 0x00000004 */
+#define SDMMC_MASK_CTIMEOUTIE            SDMMC_MASK_CTIMEOUTIE_Msk             /*!<Command TimeOut Interrupt Enable           */
+#define SDMMC_MASK_DTIMEOUTIE_Pos        (3U)
+#define SDMMC_MASK_DTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)  /*!< 0x00000008 */
+#define SDMMC_MASK_DTIMEOUTIE            SDMMC_MASK_DTIMEOUTIE_Msk             /*!<Data TimeOut Interrupt Enable              */
+#define SDMMC_MASK_TXUNDERRIE_Pos        (4U)
+#define SDMMC_MASK_TXUNDERRIE_Msk        (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)  /*!< 0x00000010 */
+#define SDMMC_MASK_TXUNDERRIE            SDMMC_MASK_TXUNDERRIE_Msk             /*!<Tx FIFO UnderRun Error Interrupt Enable    */
+#define SDMMC_MASK_RXOVERRIE_Pos         (5U)
+#define SDMMC_MASK_RXOVERRIE_Msk         (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)   /*!< 0x00000020 */
+#define SDMMC_MASK_RXOVERRIE             SDMMC_MASK_RXOVERRIE_Msk              /*!<Rx FIFO OverRun Error Interrupt Enable     */
+#define SDMMC_MASK_CMDRENDIE_Pos         (6U)
+#define SDMMC_MASK_CMDRENDIE_Msk         (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)   /*!< 0x00000040 */
+#define SDMMC_MASK_CMDRENDIE             SDMMC_MASK_CMDRENDIE_Msk              /*!<Command Response Received Interrupt Enable */
+#define SDMMC_MASK_CMDSENTIE_Pos         (7U)
+#define SDMMC_MASK_CMDSENTIE_Msk         (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)   /*!< 0x00000080 */
+#define SDMMC_MASK_CMDSENTIE             SDMMC_MASK_CMDSENTIE_Msk              /*!<Command Sent Interrupt Enable              */
+#define SDMMC_MASK_DATAENDIE_Pos         (8U)
+#define SDMMC_MASK_DATAENDIE_Msk         (0x1UL << SDMMC_MASK_DATAENDIE_Pos)   /*!< 0x00000100 */
+#define SDMMC_MASK_DATAENDIE             SDMMC_MASK_DATAENDIE_Msk              /*!<Data End Interrupt Enable                  */
+#define SDMMC_MASK_DHOLDIE_Pos           (9U)
+#define SDMMC_MASK_DHOLDIE_Msk           (0x1UL << SDMMC_MASK_DHOLDIE_Pos)     /*!< 0x00000200 */
+#define SDMMC_MASK_DHOLDIE               SDMMC_MASK_DHOLDIE_Msk                /*!<Data Hold Interrupt Enable                 */
+#define SDMMC_MASK_DBCKENDIE_Pos         (10U)
+#define SDMMC_MASK_DBCKENDIE_Msk         (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)   /*!< 0x00000400 */
+#define SDMMC_MASK_DBCKENDIE             SDMMC_MASK_DBCKENDIE_Msk              /*!<Data Block End Interrupt Enable            */
+#define SDMMC_MASK_DABORTIE_Pos          (11U)
+#define SDMMC_MASK_DABORTIE_Msk          (0x1UL << SDMMC_MASK_DABORTIE_Pos)    /*!< 0x00000800 */
+#define SDMMC_MASK_DABORTIE              SDMMC_MASK_DABORTIE_Msk               /*!<Data transfer aborted interrupt enable     */
+
+#define SDMMC_MASK_TXFIFOHEIE_Pos        (14U)
+#define SDMMC_MASK_TXFIFOHEIE_Msk        (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)  /*!< 0x00004000 */
+#define SDMMC_MASK_TXFIFOHEIE            SDMMC_MASK_TXFIFOHEIE_Msk             /*!<Tx FIFO Half Empty interrupt Enable        */
+#define SDMMC_MASK_RXFIFOHFIE_Pos        (15U)
+#define SDMMC_MASK_RXFIFOHFIE_Msk        (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)  /*!< 0x00008000 */
+#define SDMMC_MASK_RXFIFOHFIE            SDMMC_MASK_RXFIFOHFIE_Msk             /*!<Rx FIFO Half Full interrupt Enable         */
+
+#define SDMMC_MASK_RXFIFOFIE_Pos         (17U)
+#define SDMMC_MASK_RXFIFOFIE_Msk         (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)   /*!< 0x00020000 */
+#define SDMMC_MASK_RXFIFOFIE             SDMMC_MASK_RXFIFOFIE_Msk              /*!<Rx FIFO Full interrupt Enable              */
+#define SDMMC_MASK_TXFIFOEIE_Pos         (18U)
+#define SDMMC_MASK_TXFIFOEIE_Msk         (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)   /*!< 0x00040000 */
+#define SDMMC_MASK_TXFIFOEIE             SDMMC_MASK_TXFIFOEIE_Msk              /*!<Tx FIFO Empty interrupt Enable             */
+
+#define SDMMC_MASK_BUSYD0ENDIE_Pos       (21U)
+#define SDMMC_MASK_BUSYD0ENDIE_Msk       (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */
+#define SDMMC_MASK_BUSYD0ENDIE           SDMMC_MASK_BUSYD0ENDIE_Msk            /*!<BUSYD0ENDIE interrupt Enable */
+#define SDMMC_MASK_SDIOITIE_Pos           (22U)
+#define SDMMC_MASK_SDIOITIE_Msk           (0x1UL << SDMMC_MASK_SDIOITIE_Pos)     /*!< 0x00400000 */
+#define SDMMC_MASK_SDIOITIE               SDMMC_MASK_SDIOITIE_Msk                /*!<SDMMC Mode Interrupt Received interrupt Enable */
+#define SDMMC_MASK_ACKFAILIE_Pos         (23U)
+#define SDMMC_MASK_ACKFAILIE_Msk         (0x1UL << SDMMC_MASK_ACKFAILIE_Pos)   /*!< 0x00800000 */
+#define SDMMC_MASK_ACKFAILIE             SDMMC_MASK_ACKFAILIE_Msk              /*!<Acknowledgment Fail Interrupt Enable */
+#define SDMMC_MASK_ACKTIMEOUTIE_Pos      (24U)
+#define SDMMC_MASK_ACKTIMEOUTIE_Msk      (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */
+#define SDMMC_MASK_ACKTIMEOUTIE          SDMMC_MASK_ACKTIMEOUTIE_Msk           /*!<Acknowledgment timeout Interrupt Enable */
+#define SDMMC_MASK_VSWENDIE_Pos          (25U)
+#define SDMMC_MASK_VSWENDIE_Msk          (0x1UL << SDMMC_MASK_VSWENDIE_Pos)    /*!< 0x02000000 */
+#define SDMMC_MASK_VSWENDIE              SDMMC_MASK_VSWENDIE_Msk               /*!<Voltage switch critical timing section completion Interrupt Enable */
+#define SDMMC_MASK_CKSTOPIE_Pos          (26U)
+#define SDMMC_MASK_CKSTOPIE_Msk          (0x1UL << SDMMC_MASK_CKSTOPIE_Pos)    /*!< 0x04000000 */
+#define SDMMC_MASK_CKSTOPIE              SDMMC_MASK_CKSTOPIE_Msk               /*!<Voltage Switch clock stopped Interrupt Enable */
+#define SDMMC_MASK_IDMABTCIE_Pos         (28U)
+#define SDMMC_MASK_IDMABTCIE_Msk         (0x1UL << SDMMC_MASK_IDMABTCIE_Pos)   /*!< 0x10000000 */
+#define SDMMC_MASK_IDMABTCIE             SDMMC_MASK_IDMABTCIE_Msk              /*!<IDMA buffer transfer complete Interrupt Enable */
+
+/*****************  Bit definition for SDMMC_ACKTIME register  *****************/
+#define SDMMC_ACKTIME_ACKTIME_Pos        (0U)
+#define SDMMC_ACKTIME_ACKTIME_Msk        (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_ACKTIME_ACKTIME            SDMMC_ACKTIME_ACKTIME_Msk             /*!<Boot acknowledgment timeout period */
+
+/******************  Bit definition for SDMMC_FIFO register  *******************/
+#define SDMMC_FIFO_FIFODATA_Pos          (0U)
+#define SDMMC_FIFO_FIFODATA_Msk          (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_FIFO_FIFODATA              SDMMC_FIFO_FIFODATA_Msk               /*!<Receive and transmit FIFO data */
+
+/******************  Bit definition for SDMMC_IDMACTRL register ****************/
+#define SDMMC_IDMA_IDMAEN_Pos            (0U)
+#define SDMMC_IDMA_IDMAEN_Msk            (0x1UL << SDMMC_IDMA_IDMAEN_Pos)      /*!< 0x00000001 */
+#define SDMMC_IDMA_IDMAEN                SDMMC_IDMA_IDMAEN_Msk                 /*!< Enable the internal DMA of the SDMMC peripheral */
+#define SDMMC_IDMA_IDMABMODE_Pos         (1U)
+#define SDMMC_IDMA_IDMABMODE_Msk         (0x1UL << SDMMC_IDMA_IDMABMODE_Pos)   /*!< 0x00000002 */
+#define SDMMC_IDMA_IDMABMODE             SDMMC_IDMA_IDMABMODE_Msk              /*!< Enable double buffer mode for IDMA */
+#define SDMMC_IDMA_IDMABACT_Pos          (2U)
+#define SDMMC_IDMA_IDMABACT_Msk          (0x1UL << SDMMC_IDMA_IDMABACT_Pos)    /*!< 0x00000004 */
+#define SDMMC_IDMA_IDMABACT              SDMMC_IDMA_IDMABACT_Msk               /*!< Uses buffer 1 when double buffer mode is selected */
+
+/*****************  Bit definition for SDMMC_IDMABSIZE register  ***************/
+#define SDMMC_IDMABSIZE_IDMABNDT_Pos     (5U)
+#define SDMMC_IDMABSIZE_IDMABNDT_Msk     (0xFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos) /*!< 0x00001FE0 */
+#define SDMMC_IDMABSIZE_IDMABNDT         SDMMC_IDMABSIZE_IDMABNDT_Msk          /*!< Number of transfers per buffer */
+
+/*****************  Bit definition for SDMMC_IDMABASE0 register  ***************/
+#define SDMMC_IDMABASE0_IDMABASE0        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 0 memory base address */
+
+/*****************  Bit definition for SDMMC_IDMABASE1 register  ***************/
+#define SDMMC_IDMABASE1_IDMABASE1        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 1 memory base address */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Delay Block Interface (DLYB)                        */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for DLYB_CR register  ********************/
+#define DLYB_CR_DEN_Pos         (0U)
+#define DLYB_CR_DEN_Msk         (0x1UL << DLYB_CR_DEN_Pos)                     /*!< 0x00000001 */
+#define DLYB_CR_DEN             DLYB_CR_DEN_Msk                                /*!<Delay Block enable */
+#define DLYB_CR_SEN_Pos         (1U)
+#define DLYB_CR_SEN_Msk         (0x1UL << DLYB_CR_SEN_Pos)                     /*!< 0x00000002 */
+#define DLYB_CR_SEN             DLYB_CR_SEN_Msk                                /*!<Sampler length enable */
+
+
+/*******************  Bit definition for DLYB_CFGR register  ********************/
+#define DLYB_CFGR_SEL_Pos       (0U)
+#define DLYB_CFGR_SEL_Msk       (0xFUL << DLYB_CFGR_SEL_Pos)                   /*!< 0x0000000F */
+#define DLYB_CFGR_SEL           DLYB_CFGR_SEL_Msk                              /*!<Select the phase for the Output clock[3:0] */
+#define DLYB_CFGR_SEL_0         (0x1UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000001 */
+#define DLYB_CFGR_SEL_1         (0x2UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000002 */
+#define DLYB_CFGR_SEL_2         (0x3UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000003 */
+#define DLYB_CFGR_SEL_3         (0x8UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000008 */
+
+#define DLYB_CFGR_UNIT_Pos      (8U)
+#define DLYB_CFGR_UNIT_Msk      (0x7FUL << DLYB_CFGR_UNIT_Pos)                 /*!< 0x00007F00 */
+#define DLYB_CFGR_UNIT          DLYB_CFGR_UNIT_Msk                             /*!<Delay Defines the delay of a Unit delay cell[6:0] */
+#define DLYB_CFGR_UNIT_0        (0x01UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000100 */
+#define DLYB_CFGR_UNIT_1        (0x02UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000200 */
+#define DLYB_CFGR_UNIT_2        (0x04UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000400 */
+#define DLYB_CFGR_UNIT_3        (0x08UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000800 */
+#define DLYB_CFGR_UNIT_4        (0x10UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00001000 */
+#define DLYB_CFGR_UNIT_5        (0x20UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00002000 */
+#define DLYB_CFGR_UNIT_6        (0x40UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00004000 */
+
+#define DLYB_CFGR_LNG_Pos       (16U)
+#define DLYB_CFGR_LNG_Msk       (0xFFFUL << DLYB_CFGR_LNG_Pos)                 /*!< 0x0FFF0000 */
+#define DLYB_CFGR_LNG           DLYB_CFGR_LNG_Msk                              /*!<Delay line length value[11:0] */
+#define DLYB_CFGR_LNG_0         (0x001UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00010000 */
+#define DLYB_CFGR_LNG_1         (0x002UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00020000 */
+#define DLYB_CFGR_LNG_2         (0x004UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00040000 */
+#define DLYB_CFGR_LNG_3         (0x008UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00080000 */
+#define DLYB_CFGR_LNG_4         (0x010UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00100000 */
+#define DLYB_CFGR_LNG_5         (0x020UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00200000 */
+#define DLYB_CFGR_LNG_6         (0x040UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00400000 */
+#define DLYB_CFGR_LNG_7         (0x080UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00800000 */
+#define DLYB_CFGR_LNG_8         (0x100UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x01000000 */
+#define DLYB_CFGR_LNG_9         (0x200UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x02000000 */
+#define DLYB_CFGR_LNG_10        (0x400UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x04000000 */
+#define DLYB_CFGR_LNG_11        (0x800UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x08000000 */
+
+#define DLYB_CFGR_LNGF_Pos      (31U)
+#define DLYB_CFGR_LNGF_Msk      (0x1UL << DLYB_CFGR_LNGF_Pos)                  /*!< 0x80000000 */
+#define DLYB_CFGR_LNGF          DLYB_CFGR_LNGF_Msk                             /*!<Length valid flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                   Serial Peripheral Interface (SPI/I2S)                    */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define SPI_CR1_SPE_Pos             (0U)
+#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000001 */
+#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<Serial Peripheral Enable                         */
+#define SPI_CR1_MASRX_Pos           (8U)
+#define SPI_CR1_MASRX_Msk           (0x1UL << SPI_CR1_MASRX_Pos)               /*!< 0x00000100 */
+#define SPI_CR1_MASRX               SPI_CR1_MASRX_Msk                          /*!<Master automatic SUSP in Receive mode            */
+#define SPI_CR1_CSTART_Pos          (9U)
+#define SPI_CR1_CSTART_Msk          (0x1UL << SPI_CR1_CSTART_Pos)              /*!< 0x00000200 */
+#define SPI_CR1_CSTART              SPI_CR1_CSTART_Msk                         /*!<Master transfer start                            */
+#define SPI_CR1_CSUSP_Pos           (10U)
+#define SPI_CR1_CSUSP_Msk           (0x1UL << SPI_CR1_CSUSP_Pos)               /*!< 0x00000400 */
+#define SPI_CR1_CSUSP               SPI_CR1_CSUSP_Msk                          /*!<Master SUSPend request                           */
+#define SPI_CR1_HDDIR_Pos           (11U)
+#define SPI_CR1_HDDIR_Msk           (0x1UL << SPI_CR1_HDDIR_Pos)               /*!< 0x00000800 */
+#define SPI_CR1_HDDIR               SPI_CR1_HDDIR_Msk                          /*!<Rx/Tx direction at Half-duplex mode              */
+#define SPI_CR1_SSI_Pos             (12U)
+#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                 /*!< 0x00001000 */
+#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal SS signal input level                   */
+#define SPI_CR1_CRC33_17_Pos        (13U)
+#define SPI_CR1_CRC33_17_Msk        (0x1UL << SPI_CR1_CRC33_17_Pos)            /*!< 0x00002000 */
+#define SPI_CR1_CRC33_17             SPI_CR1_CRC33_17_Msk                      /*!<32-bit CRC polynomial configuration              */
+#define SPI_CR1_RCRCINI_Pos         (14U)
+#define SPI_CR1_RCRCINI_Msk         (0x1UL << SPI_CR1_RCRCINI_Pos)             /*!< 0x00004000 */
+#define SPI_CR1_RCRCINI             SPI_CR1_RCRCINI_Msk                        /*!<CRC init pattern control for receiver            */
+#define SPI_CR1_TCRCINI_Pos         (15U)
+#define SPI_CR1_TCRCINI_Msk         (0x1UL << SPI_CR1_TCRCINI_Pos)             /*!< 0x00008000 */
+#define SPI_CR1_TCRCINI             SPI_CR1_TCRCINI_Msk                        /*!<CRC init pattern control for transmitter         */
+#define SPI_CR1_IOLOCK_Pos          (16U)
+#define SPI_CR1_IOLOCK_Msk          (0x1UL << SPI_CR1_IOLOCK_Pos)              /*!< 0x00010000 */
+#define SPI_CR1_IOLOCK              SPI_CR1_IOLOCK_Msk                         /*!<Locking the AF configuration of associated IOs   */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define SPI_CR2_TSER_Pos            (16U)
+#define SPI_CR2_TSER_Msk            (0xFFFFUL << SPI_CR2_TSER_Pos)             /*!< 0xFFFF0000 */
+#define SPI_CR2_TSER                SPI_CR2_TSER_Msk                           /*!<Number of data transfer extension                */
+#define SPI_CR2_TSIZE_Pos           (0U)
+#define SPI_CR2_TSIZE_Msk           (0xFFFFUL << SPI_CR2_TSIZE_Pos)            /*!< 0x0000FFFF */
+#define SPI_CR2_TSIZE               SPI_CR2_TSIZE_Msk                          /*!<Number of data at current transfer               */
+
+/*******************  Bit definition for SPI_CFG1 register  ********************/
+#define SPI_CFG1_DSIZE_Pos          (0U)
+#define SPI_CFG1_DSIZE_Msk          (0x1FUL << SPI_CFG1_DSIZE_Pos)             /*!< 0x0000001F */
+#define SPI_CFG1_DSIZE              SPI_CFG1_DSIZE_Msk                         /*!<DSIZE[4:0]: Bits number in single SPI data frame */
+#define SPI_CFG1_DSIZE_0            (0x01UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000001 */
+#define SPI_CFG1_DSIZE_1            (0x02UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000002 */
+#define SPI_CFG1_DSIZE_2            (0x04UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000004 */
+#define SPI_CFG1_DSIZE_3            (0x08UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000008 */
+#define SPI_CFG1_DSIZE_4            (0x10UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000010 */
+
+#define SPI_CFG1_FTHLV_Pos          (5U)
+#define SPI_CFG1_FTHLV_Msk          (0xFUL << SPI_CFG1_FTHLV_Pos)              /*!< 0x000001E0 */
+#define SPI_CFG1_FTHLV              SPI_CFG1_FTHLV_Msk                         /*!<FTHVL [3:0]: FIFO threshold level*/
+#define SPI_CFG1_FTHLV_0            (0x1UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000020 */
+#define SPI_CFG1_FTHLV_1            (0x2UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000040 */
+#define SPI_CFG1_FTHLV_2            (0x4UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000080 */
+#define SPI_CFG1_FTHLV_3            (0x8UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000100 */
+
+#define SPI_CFG1_UDRCFG_Pos         (9U)
+#define SPI_CFG1_UDRCFG_Msk         (0x3UL << SPI_CFG1_UDRCFG_Pos)             /*!< 0x00000600 */
+#define SPI_CFG1_UDRCFG             SPI_CFG1_UDRCFG_Msk                        /*!<UDRCFG[1:0]: Behavior of transmitter at underrun */
+#define SPI_CFG1_UDRCFG_0           (0x1UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000200 */
+#define SPI_CFG1_UDRCFG_1           (0x2UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000400 */
+
+
+#define SPI_CFG1_UDRDET_Pos         (11U)
+#define SPI_CFG1_UDRDET_Msk         (0x3UL << SPI_CFG1_UDRDET_Pos)             /*!< 0x00001800 */
+#define SPI_CFG1_UDRDET             SPI_CFG1_UDRDET_Msk                        /*!<UDRDET[1:0]: Detection of underrun condition     */
+#define SPI_CFG1_UDRDET_0           (0x1UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00000800 */
+#define SPI_CFG1_UDRDET_1           (0x2UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00001000 */
+
+#define SPI_CFG1_RXDMAEN_Pos        (14U)
+#define SPI_CFG1_RXDMAEN_Msk        (0x1UL << SPI_CFG1_RXDMAEN_Pos)            /*!< 0x00004000 */
+#define SPI_CFG1_RXDMAEN            SPI_CFG1_RXDMAEN_Msk                       /*!<Rx DMA stream enable                */
+#define SPI_CFG1_TXDMAEN_Pos        (15U)
+#define SPI_CFG1_TXDMAEN_Msk        (0x1UL << SPI_CFG1_TXDMAEN_Pos)            /*!< 0x00008000 */
+#define SPI_CFG1_TXDMAEN            SPI_CFG1_TXDMAEN_Msk                       /*!<Tx DMA stream enable                */
+
+#define SPI_CFG1_CRCSIZE_Pos        (16U)
+#define SPI_CFG1_CRCSIZE_Msk        (0x1FUL << SPI_CFG1_CRCSIZE_Pos)           /*!< 0x001F0000 */
+#define SPI_CFG1_CRCSIZE            SPI_CFG1_CRCSIZE_Msk                       /*!<CRCSIZE [4:0]: Length of CRC frame*/
+#define SPI_CFG1_CRCSIZE_0          (0x01UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00010000 */
+#define SPI_CFG1_CRCSIZE_1          (0x02UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00020000 */
+#define SPI_CFG1_CRCSIZE_2          (0x04UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00040000 */
+#define SPI_CFG1_CRCSIZE_3          (0x08UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00080000 */
+#define SPI_CFG1_CRCSIZE_4          (0x10UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00100000 */
+
+#define SPI_CFG1_CRCEN_Pos          (22U)
+#define SPI_CFG1_CRCEN_Msk          (0x1UL << SPI_CFG1_CRCEN_Pos)              /*!< 0x00400000 */
+#define SPI_CFG1_CRCEN              SPI_CFG1_CRCEN_Msk                         /*!<Hardware CRC computation enable */
+
+#define SPI_CFG1_MBR_Pos            (28U)
+#define SPI_CFG1_MBR_Msk            (0x7UL << SPI_CFG1_MBR_Pos)                /*!< 0x70000000 */
+#define SPI_CFG1_MBR                SPI_CFG1_MBR_Msk                           /*!<Master baud rate                */
+#define SPI_CFG1_MBR_0              (0x1UL << SPI_CFG1_MBR_Pos)                 /*!< 0x10000000 */
+#define SPI_CFG1_MBR_1              (0x2UL << SPI_CFG1_MBR_Pos)                 /*!< 0x20000000 */
+#define SPI_CFG1_MBR_2              (0x4UL << SPI_CFG1_MBR_Pos)                 /*!< 0x40000000 */
+
+/*******************  Bit definition for SPI_CFG2 register  ********************/
+#define SPI_CFG2_MSSI_Pos           (0U)
+#define SPI_CFG2_MSSI_Msk           (0xFUL << SPI_CFG2_MSSI_Pos)               /*!< 0x0000000F */
+#define SPI_CFG2_MSSI               SPI_CFG2_MSSI_Msk                          /*!<Master SS Idleness */
+#define SPI_CFG2_MSSI_0             (0x1UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000001 */
+#define SPI_CFG2_MSSI_1             (0x2UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000002 */
+#define SPI_CFG2_MSSI_2             (0x4UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000004 */
+#define SPI_CFG2_MSSI_3             (0x8UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000008 */
+
+#define SPI_CFG2_MIDI_Pos           (4U)
+#define SPI_CFG2_MIDI_Msk           (0xFUL << SPI_CFG2_MIDI_Pos)               /*!< 0x000000F0 */
+#define SPI_CFG2_MIDI               SPI_CFG2_MIDI_Msk                          /*!<Master Inter-Data Idleness */
+#define SPI_CFG2_MIDI_0             (0x1UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000010 */
+#define SPI_CFG2_MIDI_1             (0x2UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000020 */
+#define SPI_CFG2_MIDI_2             (0x4UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000040 */
+#define SPI_CFG2_MIDI_3             (0x8UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000080 */
+
+#define SPI_CFG2_IOSWP_Pos          (15U)
+#define SPI_CFG2_IOSWP_Msk          (0x1UL << SPI_CFG2_IOSWP_Pos)              /*!< 0x00008000 */
+#define SPI_CFG2_IOSWP              SPI_CFG2_IOSWP_Msk                         /*!<Swap functionality of MISO and MOSI pins */
+
+#define SPI_CFG2_COMM_Pos           (17U)
+#define SPI_CFG2_COMM_Msk           (0x3UL << SPI_CFG2_COMM_Pos)               /*!< 0x00060000 */
+#define SPI_CFG2_COMM               SPI_CFG2_COMM_Msk                          /*!<COMM [1:0]: SPI Communication Mode*/
+#define SPI_CFG2_COMM_0             (0x1UL << SPI_CFG2_COMM_Pos)                /*!< 0x00020000 */
+#define SPI_CFG2_COMM_1             (0x2UL << SPI_CFG2_COMM_Pos)                /*!< 0x00040000 */
+
+#define SPI_CFG2_SP_Pos             (19U)
+#define SPI_CFG2_SP_Msk             (0x7UL << SPI_CFG2_SP_Pos)                 /*!< 0x00380000 */
+#define SPI_CFG2_SP                 SPI_CFG2_SP_Msk                            /*!<SP[2:0]: Serial Protocol */
+#define SPI_CFG2_SP_0               (0x1UL << SPI_CFG2_SP_Pos)                  /*!< 0x00080000 */
+#define SPI_CFG2_SP_1               (0x2UL << SPI_CFG2_SP_Pos)                  /*!< 0x00100000 */
+#define SPI_CFG2_SP_2               (0x4UL << SPI_CFG2_SP_Pos)                  /*!< 0x00200000 */
+
+#define SPI_CFG2_MASTER_Pos         (22U)
+#define SPI_CFG2_MASTER_Msk         (0x1UL << SPI_CFG2_MASTER_Pos)             /*!< 0x00400000 */
+#define SPI_CFG2_MASTER             SPI_CFG2_MASTER_Msk                        /*!<SPI Master           */
+#define SPI_CFG2_LSBFRST_Pos        (23U)
+#define SPI_CFG2_LSBFRST_Msk        (0x1UL << SPI_CFG2_LSBFRST_Pos)            /*!< 0x00800000 */
+#define SPI_CFG2_LSBFRST            SPI_CFG2_LSBFRST_Msk                       /*!<Data frame format               */
+#define SPI_CFG2_CPHA_Pos           (24U)
+#define SPI_CFG2_CPHA_Msk           (0x1UL << SPI_CFG2_CPHA_Pos)               /*!< 0x01000000 */
+#define SPI_CFG2_CPHA               SPI_CFG2_CPHA_Msk                          /*!<Clock Phase      */
+#define SPI_CFG2_CPOL_Pos           (25U)
+#define SPI_CFG2_CPOL_Msk           (0x1UL << SPI_CFG2_CPOL_Pos)               /*!< 0x02000000 */
+#define SPI_CFG2_CPOL               SPI_CFG2_CPOL_Msk                          /*!<Clock Polarity   */
+#define SPI_CFG2_SSM_Pos            (26U)
+#define SPI_CFG2_SSM_Msk            (0x1UL << SPI_CFG2_SSM_Pos)                /*!< 0x04000000 */
+#define SPI_CFG2_SSM                SPI_CFG2_SSM_Msk                           /*!<Software slave management */
+
+#define SPI_CFG2_SSIOP_Pos          (28U)
+#define SPI_CFG2_SSIOP_Msk          (0x1UL << SPI_CFG2_SSIOP_Pos)              /*!< 0x10000000 */
+#define SPI_CFG2_SSIOP              SPI_CFG2_SSIOP_Msk                         /*!<SS input/output polarity */
+#define SPI_CFG2_SSOE_Pos           (29U)
+#define SPI_CFG2_SSOE_Msk           (0x1UL << SPI_CFG2_SSOE_Pos)               /*!< 0x20000000 */
+#define SPI_CFG2_SSOE               SPI_CFG2_SSOE_Msk                          /*!<SS output enable */
+#define SPI_CFG2_SSOM_Pos           (30U)
+#define SPI_CFG2_SSOM_Msk           (0x1UL << SPI_CFG2_SSOM_Pos)               /*!< 0x40000000 */
+#define SPI_CFG2_SSOM               SPI_CFG2_SSOM_Msk                          /*!<SS output management in master mode */
+
+#define SPI_CFG2_AFCNTR_Pos         (31U)
+#define SPI_CFG2_AFCNTR_Msk         (0x1UL << SPI_CFG2_AFCNTR_Pos)             /*!< 0x80000000 */
+#define SPI_CFG2_AFCNTR             SPI_CFG2_AFCNTR_Msk                        /*!<Alternate function GPIOs control */
+
+/*******************  Bit definition for SPI_IER register  ********************/
+#define SPI_IER_RXPIE_Pos           (0U)
+#define SPI_IER_RXPIE_Msk           (0x1UL << SPI_IER_RXPIE_Pos)               /*!< 0x00000001 */
+#define SPI_IER_RXPIE               SPI_IER_RXPIE_Msk                          /*!<RXP Interrupt Enable            */
+#define SPI_IER_TXPIE_Pos           (1U)
+#define SPI_IER_TXPIE_Msk           (0x1UL << SPI_IER_TXPIE_Pos)               /*!< 0x00000002 */
+#define SPI_IER_TXPIE               SPI_IER_TXPIE_Msk                          /*!<TXP interrupt enable            */
+#define SPI_IER_DXPIE_Pos           (2U)
+#define SPI_IER_DXPIE_Msk           (0x1UL << SPI_IER_DXPIE_Pos)               /*!< 0x00000004 */
+#define SPI_IER_DXPIE               SPI_IER_DXPIE_Msk                          /*!<DXP interrupt enable            */
+#define SPI_IER_EOTIE_Pos           (3U)
+#define SPI_IER_EOTIE_Msk           (0x1UL << SPI_IER_EOTIE_Pos)               /*!< 0x00000008 */
+#define SPI_IER_EOTIE               SPI_IER_EOTIE_Msk                          /*!<EOT/SUSP/TXC interrupt enable   */
+#define SPI_IER_TXTFIE_Pos          (4U)
+#define SPI_IER_TXTFIE_Msk          (0x1UL << SPI_IER_TXTFIE_Pos)              /*!< 0x00000010 */
+#define SPI_IER_TXTFIE              SPI_IER_TXTFIE_Msk                         /*!<TXTF interrupt enable           */
+#define SPI_IER_UDRIE_Pos           (5U)
+#define SPI_IER_UDRIE_Msk           (0x1UL << SPI_IER_UDRIE_Pos)               /*!< 0x00000020 */
+#define SPI_IER_UDRIE               SPI_IER_UDRIE_Msk                          /*!<UDR interrupt enable            */
+#define SPI_IER_OVRIE_Pos           (6U)
+#define SPI_IER_OVRIE_Msk           (0x1UL << SPI_IER_OVRIE_Pos)               /*!< 0x00000040 */
+#define SPI_IER_OVRIE               SPI_IER_OVRIE_Msk                          /*!<OVR interrupt enable            */
+#define SPI_IER_CRCEIE_Pos          (7U)
+#define SPI_IER_CRCEIE_Msk          (0x1UL << SPI_IER_CRCEIE_Pos)               /*!< 0x00000080 */
+#define SPI_IER_CRCEIE              SPI_IER_CRCEIE_Msk                          /*!<CRCE interrupt enable           */
+#define SPI_IER_TIFREIE_Pos         (8U)
+#define SPI_IER_TIFREIE_Msk         (0x1UL << SPI_IER_TIFREIE_Pos)             /*!< 0x00000100 */
+#define SPI_IER_TIFREIE             SPI_IER_TIFREIE_Msk                        /*!<TI Frame Error interrupt enable */
+#define SPI_IER_MODFIE_Pos          (9U)
+#define SPI_IER_MODFIE_Msk          (0x1UL << SPI_IER_MODFIE_Pos)              /*!< 0x00000200 */
+#define SPI_IER_MODFIE              SPI_IER_MODFIE_Msk                         /*!<MODF interrupt enable           */
+#define SPI_IER_TSERFIE_Pos         (10U)
+#define SPI_IER_TSERFIE_Msk         (0x1UL << SPI_IER_TSERFIE_Pos)              /*!< 0x00000400 */
+#define SPI_IER_TSERFIE             SPI_IER_TSERFIE_Msk                        /*!<TSERF interrupt enable          */
+
+/*******************  Bit definition for SPI_SR register  ********************/
+#define SPI_SR_RXP_Pos              (0U)
+#define SPI_SR_RXP_Msk              (0x1UL << SPI_SR_RXP_Pos)                  /*!< 0x00000001 */
+#define SPI_SR_RXP                  SPI_SR_RXP_Msk                             /*!<Rx-Packet available             */
+#define SPI_SR_TXP_Pos              (1U)
+#define SPI_SR_TXP_Msk              (0x1UL << SPI_SR_TXP_Pos)                  /*!< 0x00000002 */
+#define SPI_SR_TXP                  SPI_SR_TXP_Msk                             /*!<Tx-Packet space available       */
+#define SPI_SR_DXP_Pos              (2U)
+#define SPI_SR_DXP_Msk              (0x1UL << SPI_SR_DXP_Pos)                  /*!< 0x00000004 */
+#define SPI_SR_DXP                  SPI_SR_DXP_Msk                             /*!<Duplex Packet available         */
+#define SPI_SR_EOT_Pos              (3U)
+#define SPI_SR_EOT_Msk              (0x1UL << SPI_SR_EOT_Pos)                  /*!< 0x00000008 */
+#define SPI_SR_EOT                  SPI_SR_EOT_Msk                             /*!<Duplex Packet available         */
+#define SPI_SR_TXTF_Pos             (4U)
+#define SPI_SR_TXTF_Msk             (0x1UL << SPI_SR_TXTF_Pos)                 /*!< 0x00000010 */
+#define SPI_SR_TXTF                 SPI_SR_TXTF_Msk                            /*!<Transmission Transfer Filled    */
+#define SPI_SR_UDR_Pos              (5U)
+#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                  /*!< 0x00000020 */
+#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<UDR at Slave transmission       */
+#define SPI_SR_OVR_Pos              (6U)
+#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                  /*!< 0x00000040 */
+#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Rx-Packet available             */
+#define SPI_SR_CRCE_Pos             (7U)
+#define SPI_SR_CRCE_Msk             (0x1UL << SPI_SR_CRCE_Pos)                 /*!< 0x00000080 */
+#define SPI_SR_CRCE                 SPI_SR_CRCE_Msk                            /*!<CRC Error Detected              */
+#define SPI_SR_TIFRE_Pos            (8U)
+#define SPI_SR_TIFRE_Msk            (0x1UL << SPI_SR_TIFRE_Pos)                /*!< 0x00000100 */
+#define SPI_SR_TIFRE                SPI_SR_TIFRE_Msk                           /*!<TI frame format error Detected  */
+#define SPI_SR_MODF_Pos             (9U)
+#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                 /*!< 0x00000200 */
+#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode Fault Detected             */
+#define SPI_SR_TSERF_Pos            (10U)
+#define SPI_SR_TSERF_Msk            (0x1UL << SPI_SR_TSERF_Pos)                /*!< 0x00000400 */
+#define SPI_SR_TSERF                SPI_SR_TSERF_Msk                           /*!<Number of SPI data to be transacted reloaded     */
+#define SPI_SR_SUSP_Pos             (11U)
+#define SPI_SR_SUSP_Msk             (0x1UL << SPI_SR_SUSP_Pos)                 /*!< 0x00000800 */
+#define SPI_SR_SUSP                 SPI_SR_SUSP_Msk                            /*!<SUSP is set by hardware  */
+#define SPI_SR_TXC_Pos              (12U)
+#define SPI_SR_TXC_Msk              (0x1UL << SPI_SR_TXC_Pos)                  /*!< 0x00001000 */
+#define SPI_SR_TXC                  SPI_SR_TXC_Msk                             /*!<TxFIFO transmission complete */
+#define SPI_SR_RXPLVL_Pos           (13U)
+#define SPI_SR_RXPLVL_Msk           (0x3UL << SPI_SR_RXPLVL_Pos)               /*!< 0x00006000 */
+#define SPI_SR_RXPLVL               SPI_SR_RXPLVL_Msk                          /*!<RxFIFO Packing Level                             */
+#define SPI_SR_RXPLVL_0             (0x1UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00002000 */
+#define SPI_SR_RXPLVL_1             (0x2UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00004000 */
+#define SPI_SR_RXWNE_Pos            (15U)
+#define SPI_SR_RXWNE_Msk            (0x1UL << SPI_SR_RXWNE_Pos)                /*!< 0x00008000 */
+#define SPI_SR_RXWNE                SPI_SR_RXWNE_Msk                           /*!<Rx FIFO Word Not Empty                           */
+#define SPI_SR_CTSIZE_Pos           (16U)
+#define SPI_SR_CTSIZE_Msk           (0xFFFFUL << SPI_SR_CTSIZE_Pos)            /*!< 0xFFFF0000 */
+#define SPI_SR_CTSIZE               SPI_SR_CTSIZE_Msk                          /*!<Number of data frames remaining in TSIZE         */
+
+/*******************  Bit definition for SPI_IFCR register  ********************/
+#define SPI_IFCR_EOTC_Pos           (3U)
+#define SPI_IFCR_EOTC_Msk           (0x1UL << SPI_IFCR_EOTC_Pos)               /*!< 0x00000008 */
+#define SPI_IFCR_EOTC               SPI_IFCR_EOTC_Msk                          /*!<End Of Transfer flag clear              */
+#define SPI_IFCR_TXTFC_Pos          (4U)
+#define SPI_IFCR_TXTFC_Msk          (0x1UL << SPI_IFCR_TXTFC_Pos)              /*!< 0x00000010 */
+#define SPI_IFCR_TXTFC              SPI_IFCR_TXTFC_Msk                         /*!<Transmission Transfer Filled flag clear */
+#define SPI_IFCR_UDRC_Pos           (5U)
+#define SPI_IFCR_UDRC_Msk           (0x1UL << SPI_IFCR_UDRC_Pos)               /*!< 0x00000020 */
+#define SPI_IFCR_UDRC               SPI_IFCR_UDRC_Msk                          /*!<Underrun flag clear                     */
+#define SPI_IFCR_OVRC_Pos           (6U)
+#define SPI_IFCR_OVRC_Msk           (0x1UL << SPI_IFCR_OVRC_Pos)               /*!< 0x00000040 */
+#define SPI_IFCR_OVRC               SPI_IFCR_OVRC_Msk                          /*!<Overrun flag clear                      */
+#define SPI_IFCR_CRCEC_Pos          (7U)
+#define SPI_IFCR_CRCEC_Msk          (0x1UL << SPI_IFCR_CRCEC_Pos)              /*!< 0x00000080 */
+#define SPI_IFCR_CRCEC              SPI_IFCR_CRCEC_Msk                         /*!<CRC Error flag clear                    */
+#define SPI_IFCR_TIFREC_Pos         (8U)
+#define SPI_IFCR_TIFREC_Msk         (0x1UL << SPI_IFCR_TIFREC_Pos)             /*!< 0x00000100 */
+#define SPI_IFCR_TIFREC             SPI_IFCR_TIFREC_Msk                        /*!<TI frame format error flag clear        */
+#define SPI_IFCR_MODFC_Pos          (9U)
+#define SPI_IFCR_MODFC_Msk          (0x1UL << SPI_IFCR_MODFC_Pos)              /*!< 0x00000200 */
+#define SPI_IFCR_MODFC              SPI_IFCR_MODFC_Msk                         /*!<Mode Fault flag clear                   */
+#define SPI_IFCR_TSERFC_Pos         (10U)
+#define SPI_IFCR_TSERFC_Msk         (0x1UL << SPI_IFCR_TSERFC_Pos)             /*!< 0x00000400 */
+#define SPI_IFCR_TSERFC             SPI_IFCR_TSERFC_Msk                        /*!<TSERFC flag clear                       */
+#define SPI_IFCR_SUSPC_Pos          (11U)
+#define SPI_IFCR_SUSPC_Msk          (0x1UL << SPI_IFCR_SUSPC_Pos)              /*!< 0x00000800 */
+#define SPI_IFCR_SUSPC              SPI_IFCR_SUSPC_Msk                         /*!<SUSPend flag clear                      */
+
+/*******************  Bit definition for SPI_TXDR register  ********************/
+#define SPI_TXDR_TXDR_Pos           (0U)
+#define SPI_TXDR_TXDR_Msk           (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos)        /*!< 0xFFFFFFFF */
+#define SPI_TXDR_TXDR               SPI_TXDR_TXDR_Msk                          /* Transmit Data Register */
+
+/*******************  Bit definition for SPI_RXDR register  ********************/
+#define SPI_RXDR_RXDR_Pos           (0U)
+#define SPI_RXDR_RXDR_Msk           (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos)        /*!< 0xFFFFFFFF */
+#define SPI_RXDR_RXDR               SPI_RXDR_RXDR_Msk                          /* Receive Data Register  */
+
+/*******************  Bit definition for SPI_CRCPOLY register  ********************/
+#define SPI_CRCPOLY_CRCPOLY_Pos     (0U)
+#define SPI_CRCPOLY_CRCPOLY_Msk     (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos)  /*!< 0xFFFFFFFF */
+#define SPI_CRCPOLY_CRCPOLY         SPI_CRCPOLY_CRCPOLY_Msk                    /* CRC Polynomial register  */
+
+/*******************  Bit definition for SPI_TXCRC register  ********************/
+#define SPI_TXCRC_TXCRC_Pos         (0U)
+#define SPI_TXCRC_TXCRC_Msk         (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos)      /*!< 0xFFFFFFFF */
+#define SPI_TXCRC_TXCRC             SPI_TXCRC_TXCRC_Msk                        /* CRCRegister for transmitter */
+
+/*******************  Bit definition for SPI_RXCRC register  ********************/
+#define SPI_RXCRC_RXCRC_Pos         (0U)
+#define SPI_RXCRC_RXCRC_Msk         (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos)      /*!< 0xFFFFFFFF */
+#define SPI_RXCRC_RXCRC             SPI_RXCRC_RXCRC_Msk                        /* CRCRegister for receiver */
+
+/*******************  Bit definition for SPI_UDRDR register  ********************/
+#define SPI_UDRDR_UDRDR_Pos         (0U)
+#define SPI_UDRDR_UDRDR_Msk         (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos)      /*!< 0xFFFFFFFF */
+#define SPI_UDRDR_UDRDR             SPI_UDRDR_UDRDR_Msk                        /* Data at slave underrun condition */
+
+/******************  Bit definition for SPI_I2SCFGR register  *****************/
+#define SPI_I2SCFGR_I2SMOD_Pos      (0U)
+#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)          /*!< 0x00000001 */
+#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
+#define SPI_I2SCFGR_I2SCFG_Pos      (1U)
+#define SPI_I2SCFGR_I2SCFG_Msk      (0x7UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x0000000E */
+#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[2:0] I2S configuration mode                */
+#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000002 */
+#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000004 */
+#define SPI_I2SCFGR_I2SCFG_2        (0x4UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000008 */
+#define SPI_I2SCFGR_I2SSTD_Pos      (4U)
+#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] I2S standard selection                */
+#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */
+#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)
+#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)         /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                         */
+#define SPI_I2SCFGR_DATLEN_Pos      (8U)
+#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000300 */
+#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] Data length to be transferred         */
+#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000100 */
+#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000200 */
+#define SPI_I2SCFGR_CHLEN_Pos       (10U)
+#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)           /*!< 0x00000400 */
+#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
+#define SPI_I2SCFGR_CKPOL_Pos       (11U)
+#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)           /*!< 0x00000800 */
+#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<Steady state clock polarity                       */
+#define SPI_I2SCFGR_FIXCH_Pos       (12U)
+#define SPI_I2SCFGR_FIXCH_Msk       (0x1UL << SPI_I2SCFGR_FIXCH_Pos)           /*!< 0x00001000 */
+#define SPI_I2SCFGR_FIXCH           SPI_I2SCFGR_FIXCH_Msk                      /*!<Fixed channel length in SLAVE                     */
+#define SPI_I2SCFGR_WSINV_Pos       (13U)
+#define SPI_I2SCFGR_WSINV_Msk       (0x1UL << SPI_I2SCFGR_WSINV_Pos)           /*!< 0x00002000 */
+#define SPI_I2SCFGR_WSINV           SPI_I2SCFGR_WSINV_Msk                      /*!<Word select inversion                             */
+#define SPI_I2SCFGR_DATFMT_Pos      (14U)
+#define SPI_I2SCFGR_DATFMT_Msk      (0x1UL << SPI_I2SCFGR_DATFMT_Pos)          /*!< 0x00004000 */
+#define SPI_I2SCFGR_DATFMT          SPI_I2SCFGR_DATFMT_Msk                     /*!<Data format                                       */
+#define SPI_I2SCFGR_I2SDIV_Pos      (16U)
+#define SPI_I2SCFGR_I2SDIV_Msk      (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos)         /*!< 0x00FF0000 */
+#define SPI_I2SCFGR_I2SDIV          SPI_I2SCFGR_I2SDIV_Msk                     /*!<I2S Linear prescaler */
+#define SPI_I2SCFGR_ODD_Pos         (24U)
+#define SPI_I2SCFGR_ODD_Msk         (0x1UL << SPI_I2SCFGR_ODD_Pos)             /*!< 0x01000000 */
+#define SPI_I2SCFGR_ODD             SPI_I2SCFGR_ODD_Msk                        /*!<Odd factor for the prescaler */
+#define SPI_I2SCFGR_MCKOE_Pos       (25U)
+#define SPI_I2SCFGR_MCKOE_Msk       (0x1UL << SPI_I2SCFGR_MCKOE_Pos)           /*!< 0x02000000 */
+#define SPI_I2SCFGR_MCKOE           SPI_I2SCFGR_MCKOE_Msk                      /*!<Master Clock Output Enable */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    QUADSPI                                 */
+/*                                                                            */
+/******************************************************************************/
+/*****************  Bit definition for QUADSPI_CR register  *******************/
+#define QUADSPI_CR_EN_Pos                (0U)
+#define QUADSPI_CR_EN_Msk                (0x1UL << QUADSPI_CR_EN_Pos)          /*!< 0x00000001 */
+#define QUADSPI_CR_EN                    QUADSPI_CR_EN_Msk                     /*!< Enable */
+#define QUADSPI_CR_ABORT_Pos             (1U)
+#define QUADSPI_CR_ABORT_Msk             (0x1UL << QUADSPI_CR_ABORT_Pos)       /*!< 0x00000002 */
+#define QUADSPI_CR_ABORT                 QUADSPI_CR_ABORT_Msk                  /*!< Abort request */
+#define QUADSPI_CR_DMAEN_Pos             (2U)
+#define QUADSPI_CR_DMAEN_Msk             (0x1UL << QUADSPI_CR_DMAEN_Pos)       /*!< 0x00000004 */
+#define QUADSPI_CR_DMAEN                 QUADSPI_CR_DMAEN_Msk                  /*!< DMA Enable */
+#define QUADSPI_CR_TCEN_Pos              (3U)
+#define QUADSPI_CR_TCEN_Msk              (0x1UL << QUADSPI_CR_TCEN_Pos)        /*!< 0x00000008 */
+#define QUADSPI_CR_TCEN                  QUADSPI_CR_TCEN_Msk                   /*!< Timeout Counter Enable */
+#define QUADSPI_CR_SSHIFT_Pos            (4U)
+#define QUADSPI_CR_SSHIFT_Msk            (0x1UL << QUADSPI_CR_SSHIFT_Pos)      /*!< 0x00000010 */
+#define QUADSPI_CR_SSHIFT                QUADSPI_CR_SSHIFT_Msk                 /*!< SSHIFT Sample Shift */
+#define QUADSPI_CR_DFM_Pos               (6U)
+#define QUADSPI_CR_DFM_Msk               (0x1UL << QUADSPI_CR_DFM_Pos)         /*!< 0x00000040 */
+#define QUADSPI_CR_DFM                   QUADSPI_CR_DFM_Msk                    /*!< Dual Flash Mode */
+#define QUADSPI_CR_FSEL_Pos              (7U)
+#define QUADSPI_CR_FSEL_Msk              (0x1UL << QUADSPI_CR_FSEL_Pos)        /*!< 0x00000080 */
+#define QUADSPI_CR_FSEL                  QUADSPI_CR_FSEL_Msk                   /*!< Flash Select */
+#define QUADSPI_CR_FTHRES_Pos            (8U)
+#define QUADSPI_CR_FTHRES_Msk            (0xFUL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000F00 */
+#define QUADSPI_CR_FTHRES                QUADSPI_CR_FTHRES_Msk                 /*!< FTHRES[3:0] FIFO Level */
+#define QUADSPI_CR_FTHRES_0              (0x1UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000100 */
+#define QUADSPI_CR_FTHRES_1              (0x2UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000200 */
+#define QUADSPI_CR_FTHRES_2              (0x4UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000400 */
+#define QUADSPI_CR_FTHRES_3              (0x8UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000800 */
+#define QUADSPI_CR_TEIE_Pos              (16U)
+#define QUADSPI_CR_TEIE_Msk              (0x1UL << QUADSPI_CR_TEIE_Pos)        /*!< 0x00010000 */
+#define QUADSPI_CR_TEIE                  QUADSPI_CR_TEIE_Msk                   /*!< Transfer Error Interrupt Enable */
+#define QUADSPI_CR_TCIE_Pos              (17U)
+#define QUADSPI_CR_TCIE_Msk              (0x1UL << QUADSPI_CR_TCIE_Pos)        /*!< 0x00020000 */
+#define QUADSPI_CR_TCIE                  QUADSPI_CR_TCIE_Msk                   /*!< Transfer Complete Interrupt Enable */
+#define QUADSPI_CR_FTIE_Pos              (18U)
+#define QUADSPI_CR_FTIE_Msk              (0x1UL << QUADSPI_CR_FTIE_Pos)        /*!< 0x00040000 */
+#define QUADSPI_CR_FTIE                  QUADSPI_CR_FTIE_Msk                   /*!< FIFO Threshold Interrupt Enable */
+#define QUADSPI_CR_SMIE_Pos              (19U)
+#define QUADSPI_CR_SMIE_Msk              (0x1UL << QUADSPI_CR_SMIE_Pos)        /*!< 0x00080000 */
+#define QUADSPI_CR_SMIE                  QUADSPI_CR_SMIE_Msk                   /*!< Status Match Interrupt Enable */
+#define QUADSPI_CR_TOIE_Pos              (20U)
+#define QUADSPI_CR_TOIE_Msk              (0x1UL << QUADSPI_CR_TOIE_Pos)        /*!< 0x00100000 */
+#define QUADSPI_CR_TOIE                  QUADSPI_CR_TOIE_Msk                   /*!< TimeOut Interrupt Enable */
+#define QUADSPI_CR_APMS_Pos              (22U)
+#define QUADSPI_CR_APMS_Msk              (0x1UL << QUADSPI_CR_APMS_Pos)        /*!< 0x00400000 */
+#define QUADSPI_CR_APMS                  QUADSPI_CR_APMS_Msk                   /*!< Bit 1 */
+#define QUADSPI_CR_PMM_Pos               (23U)
+#define QUADSPI_CR_PMM_Msk               (0x1UL << QUADSPI_CR_PMM_Pos)         /*!< 0x00800000 */
+#define QUADSPI_CR_PMM                   QUADSPI_CR_PMM_Msk                    /*!< Polling Match Mode */
+#define QUADSPI_CR_PRESCALER_Pos         (24U)
+#define QUADSPI_CR_PRESCALER_Msk         (0xFFUL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0xFF000000 */
+#define QUADSPI_CR_PRESCALER             QUADSPI_CR_PRESCALER_Msk              /*!< PRESCALER[7:0] Clock prescaler */
+#define QUADSPI_CR_PRESCALER_0           (0x01UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x01000000 */
+#define QUADSPI_CR_PRESCALER_1           (0x02UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x02000000 */
+#define QUADSPI_CR_PRESCALER_2           (0x04UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x04000000 */
+#define QUADSPI_CR_PRESCALER_3           (0x08UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x08000000 */
+#define QUADSPI_CR_PRESCALER_4           (0x10UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x10000000 */
+#define QUADSPI_CR_PRESCALER_5           (0x20UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x20000000 */
+#define QUADSPI_CR_PRESCALER_6           (0x40UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x40000000 */
+#define QUADSPI_CR_PRESCALER_7           (0x80UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x80000000 */
+
+/*****************  Bit definition for QUADSPI_DCR register  ******************/
+#define QUADSPI_DCR_CKMODE_Pos           (0U)
+#define QUADSPI_DCR_CKMODE_Msk           (0x1UL << QUADSPI_DCR_CKMODE_Pos)     /*!< 0x00000001 */
+#define QUADSPI_DCR_CKMODE               QUADSPI_DCR_CKMODE_Msk                /*!< Mode 0 / Mode 3 */
+#define QUADSPI_DCR_CSHT_Pos             (8U)
+#define QUADSPI_DCR_CSHT_Msk             (0x7UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000700 */
+#define QUADSPI_DCR_CSHT                 QUADSPI_DCR_CSHT_Msk                  /*!< CSHT[2:0]: ChipSelect High Time */
+#define QUADSPI_DCR_CSHT_0               (0x1UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000100 */
+#define QUADSPI_DCR_CSHT_1               (0x2UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000200 */
+#define QUADSPI_DCR_CSHT_2               (0x4UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000400 */
+#define QUADSPI_DCR_FSIZE_Pos            (16U)
+#define QUADSPI_DCR_FSIZE_Msk            (0x1FUL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x001F0000 */
+#define QUADSPI_DCR_FSIZE                QUADSPI_DCR_FSIZE_Msk                 /*!< FSIZE[4:0]: Flash Size */
+#define QUADSPI_DCR_FSIZE_0              (0x01UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00010000 */
+#define QUADSPI_DCR_FSIZE_1              (0x02UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00020000 */
+#define QUADSPI_DCR_FSIZE_2              (0x04UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00040000 */
+#define QUADSPI_DCR_FSIZE_3              (0x08UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00080000 */
+#define QUADSPI_DCR_FSIZE_4              (0x10UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00100000 */
+
+/******************  Bit definition for QUADSPI_SR register  *******************/
+#define QUADSPI_SR_TEF_Pos               (0U)
+#define QUADSPI_SR_TEF_Msk               (0x1UL << QUADSPI_SR_TEF_Pos)         /*!< 0x00000001 */
+#define QUADSPI_SR_TEF                   QUADSPI_SR_TEF_Msk                    /*!< Transfer Error Flag */
+#define QUADSPI_SR_TCF_Pos               (1U)
+#define QUADSPI_SR_TCF_Msk               (0x1UL << QUADSPI_SR_TCF_Pos)         /*!< 0x00000002 */
+#define QUADSPI_SR_TCF                   QUADSPI_SR_TCF_Msk                    /*!< Transfer Complete Flag */
+#define QUADSPI_SR_FTF_Pos               (2U)
+#define QUADSPI_SR_FTF_Msk               (0x1UL << QUADSPI_SR_FTF_Pos)         /*!< 0x00000004 */
+#define QUADSPI_SR_FTF                   QUADSPI_SR_FTF_Msk                    /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_SMF_Pos               (3U)
+#define QUADSPI_SR_SMF_Msk               (0x1UL << QUADSPI_SR_SMF_Pos)         /*!< 0x00000008 */
+#define QUADSPI_SR_SMF                   QUADSPI_SR_SMF_Msk                    /*!< Status Match Flag */
+#define QUADSPI_SR_TOF_Pos               (4U)
+#define QUADSPI_SR_TOF_Msk               (0x1UL << QUADSPI_SR_TOF_Pos)         /*!< 0x00000010 */
+#define QUADSPI_SR_TOF                   QUADSPI_SR_TOF_Msk                    /*!< Timeout Flag */
+#define QUADSPI_SR_BUSY_Pos              (5U)
+#define QUADSPI_SR_BUSY_Msk              (0x1UL << QUADSPI_SR_BUSY_Pos)        /*!< 0x00000020 */
+#define QUADSPI_SR_BUSY                  QUADSPI_SR_BUSY_Msk                   /*!< Busy */
+#define QUADSPI_SR_FLEVEL_Pos            (8U)
+#define QUADSPI_SR_FLEVEL_Msk            (0x3FUL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00003F00 */
+#define QUADSPI_SR_FLEVEL                QUADSPI_SR_FLEVEL_Msk                 /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_FLEVEL_0              (0x01UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000100 */
+#define QUADSPI_SR_FLEVEL_1              (0x02UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000200 */
+#define QUADSPI_SR_FLEVEL_2              (0x04UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000400 */
+#define QUADSPI_SR_FLEVEL_3              (0x08UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000800 */
+#define QUADSPI_SR_FLEVEL_4              (0x10UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00001000 */
+#define QUADSPI_SR_FLEVEL_5              (0x20UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00002000 */
+
+/******************  Bit definition for QUADSPI_FCR register  ******************/
+#define QUADSPI_FCR_CTEF_Pos             (0U)
+#define QUADSPI_FCR_CTEF_Msk             (0x1UL << QUADSPI_FCR_CTEF_Pos)       /*!< 0x00000001 */
+#define QUADSPI_FCR_CTEF                 QUADSPI_FCR_CTEF_Msk                  /*!< Clear Transfer Error Flag */
+#define QUADSPI_FCR_CTCF_Pos             (1U)
+#define QUADSPI_FCR_CTCF_Msk             (0x1UL << QUADSPI_FCR_CTCF_Pos)       /*!< 0x00000002 */
+#define QUADSPI_FCR_CTCF                 QUADSPI_FCR_CTCF_Msk                  /*!< Clear Transfer Complete Flag */
+#define QUADSPI_FCR_CSMF_Pos             (3U)
+#define QUADSPI_FCR_CSMF_Msk             (0x1UL << QUADSPI_FCR_CSMF_Pos)       /*!< 0x00000008 */
+#define QUADSPI_FCR_CSMF                 QUADSPI_FCR_CSMF_Msk                  /*!< Clear Status Match Flag */
+#define QUADSPI_FCR_CTOF_Pos             (4U)
+#define QUADSPI_FCR_CTOF_Msk             (0x1UL << QUADSPI_FCR_CTOF_Pos)       /*!< 0x00000010 */
+#define QUADSPI_FCR_CTOF                 QUADSPI_FCR_CTOF_Msk                  /*!< Clear Timeout Flag */
+
+/******************  Bit definition for QUADSPI_DLR register  ******************/
+#define QUADSPI_DLR_DL_Pos               (0U)
+#define QUADSPI_DLR_DL_Msk               (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)  /*!< 0xFFFFFFFF */
+#define QUADSPI_DLR_DL                   QUADSPI_DLR_DL_Msk                    /*!< DL[31:0]: Data Length */
+
+/******************  Bit definition for QUADSPI_CCR register  ******************/
+#define QUADSPI_CCR_INSTRUCTION_Pos      (0U)
+#define QUADSPI_CCR_INSTRUCTION_Msk      (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
+#define QUADSPI_CCR_INSTRUCTION          QUADSPI_CCR_INSTRUCTION_Msk             /*!< INSTRUCTION[7:0]: Instruction */
+#define QUADSPI_CCR_INSTRUCTION_0        (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */
+#define QUADSPI_CCR_INSTRUCTION_1        (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */
+#define QUADSPI_CCR_INSTRUCTION_2        (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */
+#define QUADSPI_CCR_INSTRUCTION_3        (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */
+#define QUADSPI_CCR_INSTRUCTION_4        (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */
+#define QUADSPI_CCR_INSTRUCTION_5        (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */
+#define QUADSPI_CCR_INSTRUCTION_6        (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */
+#define QUADSPI_CCR_INSTRUCTION_7        (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */
+#define QUADSPI_CCR_IMODE_Pos            (8U)
+#define QUADSPI_CCR_IMODE_Msk            (0x3UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000300 */
+#define QUADSPI_CCR_IMODE                QUADSPI_CCR_IMODE_Msk                   /*!< IMODE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_IMODE_0              (0x1UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000100 */
+#define QUADSPI_CCR_IMODE_1              (0x2UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000200 */
+#define QUADSPI_CCR_ADMODE_Pos           (10U)
+#define QUADSPI_CCR_ADMODE_Msk           (0x3UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000C00 */
+#define QUADSPI_CCR_ADMODE               QUADSPI_CCR_ADMODE_Msk                  /*!< ADMODE[1:0]: Address Mode */
+#define QUADSPI_CCR_ADMODE_0             (0x1UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000400 */
+#define QUADSPI_CCR_ADMODE_1             (0x2UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000800 */
+#define QUADSPI_CCR_ADSIZE_Pos           (12U)
+#define QUADSPI_CCR_ADSIZE_Msk           (0x3UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00003000 */
+#define QUADSPI_CCR_ADSIZE               QUADSPI_CCR_ADSIZE_Msk                  /*!< ADSIZE[1:0]: Address Size */
+#define QUADSPI_CCR_ADSIZE_0             (0x1UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00001000 */
+#define QUADSPI_CCR_ADSIZE_1             (0x2UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00002000 */
+#define QUADSPI_CCR_ABMODE_Pos           (14U)
+#define QUADSPI_CCR_ABMODE_Msk           (0x3UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x0000C000 */
+#define QUADSPI_CCR_ABMODE               QUADSPI_CCR_ABMODE_Msk                  /*!< ABMODE[1:0]: Alternate Bytes Mode */
+#define QUADSPI_CCR_ABMODE_0             (0x1UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00004000 */
+#define QUADSPI_CCR_ABMODE_1             (0x2UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00008000 */
+#define QUADSPI_CCR_ABSIZE_Pos           (16U)
+#define QUADSPI_CCR_ABSIZE_Msk           (0x3UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00030000 */
+#define QUADSPI_CCR_ABSIZE               QUADSPI_CCR_ABSIZE_Msk                  /*!< ABSIZE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_ABSIZE_0             (0x1UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00010000 */
+#define QUADSPI_CCR_ABSIZE_1             (0x2UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00020000 */
+#define QUADSPI_CCR_DCYC_Pos             (18U)
+#define QUADSPI_CCR_DCYC_Msk             (0x1FUL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x007C0000 */
+#define QUADSPI_CCR_DCYC                 QUADSPI_CCR_DCYC_Msk                    /*!< DCYC[4:0]: Dummy Cycles */
+#define QUADSPI_CCR_DCYC_0               (0x01UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00040000 */
+#define QUADSPI_CCR_DCYC_1               (0x02UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00080000 */
+#define QUADSPI_CCR_DCYC_2               (0x04UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00100000 */
+#define QUADSPI_CCR_DCYC_3               (0x08UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00200000 */
+#define QUADSPI_CCR_DCYC_4               (0x10UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00400000 */
+#define QUADSPI_CCR_DMODE_Pos            (24U)
+#define QUADSPI_CCR_DMODE_Msk            (0x3UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x03000000 */
+#define QUADSPI_CCR_DMODE                QUADSPI_CCR_DMODE_Msk                   /*!< DMODE[1:0]: Data Mode */
+#define QUADSPI_CCR_DMODE_0              (0x1UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x01000000 */
+#define QUADSPI_CCR_DMODE_1              (0x2UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x02000000 */
+#define QUADSPI_CCR_FMODE_Pos            (26U)
+#define QUADSPI_CCR_FMODE_Msk            (0x3UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x0C000000 */
+#define QUADSPI_CCR_FMODE                QUADSPI_CCR_FMODE_Msk                   /*!< FMODE[1:0]: Functional Mode */
+#define QUADSPI_CCR_FMODE_0              (0x1UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x04000000 */
+#define QUADSPI_CCR_FMODE_1              (0x2UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x08000000 */
+#define QUADSPI_CCR_SIOO_Pos             (28U)
+#define QUADSPI_CCR_SIOO_Msk             (0x1UL << QUADSPI_CCR_SIOO_Pos)         /*!< 0x10000000 */
+#define QUADSPI_CCR_SIOO                 QUADSPI_CCR_SIOO_Msk                    /*!< SIOO: Send Instruction Only Once Mode */
+#define QUADSPI_CCR_DHHC_Pos             (30U)
+#define QUADSPI_CCR_DHHC_Msk             (0x1UL << QUADSPI_CCR_DHHC_Pos)         /*!< 0x40000000 */
+#define QUADSPI_CCR_DHHC                 QUADSPI_CCR_DHHC_Msk                    /*!< DHHC: DDR hold half cycle */
+#define QUADSPI_CCR_DDRM_Pos             (31U)
+#define QUADSPI_CCR_DDRM_Msk             (0x1UL << QUADSPI_CCR_DDRM_Pos)         /*!< 0x80000000 */
+#define QUADSPI_CCR_DDRM                 QUADSPI_CCR_DDRM_Msk                    /*!< DDRM: Double Data Rate Mode */
+
+/******************  Bit definition for QUADSPI_AR register  *******************/
+#define QUADSPI_AR_ADDRESS_Pos           (0U)
+#define QUADSPI_AR_ADDRESS_Msk           (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_AR_ADDRESS               QUADSPI_AR_ADDRESS_Msk                /*!< ADDRESS[31:0]: Address */
+
+/******************  Bit definition for QUADSPI_ABR register  ******************/
+#define QUADSPI_ABR_ALTERNATE_Pos        (0U)
+#define QUADSPI_ABR_ALTERNATE_Msk        (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_ABR_ALTERNATE            QUADSPI_ABR_ALTERNATE_Msk             /*!< ALTERNATE[31:0]: Alternate Bytes */
+
+/******************  Bit definition for QUADSPI_DR register  *******************/
+#define QUADSPI_DR_DATA_Pos              (0U)
+#define QUADSPI_DR_DATA_Msk              (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_DR_DATA                  QUADSPI_DR_DATA_Msk                   /*!< DATA[31:0]: Data */
+
+/******************  Bit definition for QUADSPI_PSMKR register  ****************/
+#define QUADSPI_PSMKR_MASK_Pos           (0U)
+#define QUADSPI_PSMKR_MASK_Msk           (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_PSMKR_MASK               QUADSPI_PSMKR_MASK_Msk                /*!< MASK[31:0]: Status Mask */
+
+/******************  Bit definition for QUADSPI_PSMAR register  ****************/
+#define QUADSPI_PSMAR_MATCH_Pos          (0U)
+#define QUADSPI_PSMAR_MATCH_Msk          (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_PSMAR_MATCH              QUADSPI_PSMAR_MATCH_Msk               /*!< MATCH[31:0]: Status Match */
+
+/******************  Bit definition for QUADSPI_PIR register  *****************/
+#define QUADSPI_PIR_INTERVAL_Pos         (0U)
+#define QUADSPI_PIR_INTERVAL_Msk         (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
+#define QUADSPI_PIR_INTERVAL             QUADSPI_PIR_INTERVAL_Msk              /*!< INTERVAL[15:0]: Polling Interval */
+
+/******************  Bit definition for QUADSPI_LPTR register  *****************/
+#define QUADSPI_LPTR_TIMEOUT_Pos         (0U)
+#define QUADSPI_LPTR_TIMEOUT_Msk         (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
+#define QUADSPI_LPTR_TIMEOUT             QUADSPI_LPTR_TIMEOUT_Msk              /*!< TIMEOUT[15:0]: Timeout period */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 SYSCFG                                     */
+/*                                                                            */
+/******************************************************************************/
+
+/******************  Bit definition for SYSCFG_PMCR register  ******************/
+#define SYSCFG_PMCR_I2C1_FMP_Pos        (0U)
+#define SYSCFG_PMCR_I2C1_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C1_FMP_Pos)    /*!< 0x00000001 */
+#define SYSCFG_PMCR_I2C1_FMP            SYSCFG_PMCR_I2C1_FMP_Msk               /*!< I2C1 Fast mode plus */
+#define SYSCFG_PMCR_I2C2_FMP_Pos        (1U)
+#define SYSCFG_PMCR_I2C2_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C2_FMP_Pos)    /*!< 0x00000002 */
+#define SYSCFG_PMCR_I2C2_FMP            SYSCFG_PMCR_I2C2_FMP_Msk               /*!< I2C2 Fast mode plus */
+#define SYSCFG_PMCR_I2C3_FMP_Pos        (2U)
+#define SYSCFG_PMCR_I2C3_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C3_FMP_Pos)    /*!< 0x00000004 */
+#define SYSCFG_PMCR_I2C3_FMP            SYSCFG_PMCR_I2C3_FMP_Msk               /*!< I2C3 Fast mode plus */
+#define SYSCFG_PMCR_I2C4_FMP_Pos        (3U)
+#define SYSCFG_PMCR_I2C4_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C4_FMP_Pos)    /*!< 0x00000008 */
+#define SYSCFG_PMCR_I2C4_FMP            SYSCFG_PMCR_I2C4_FMP_Msk               /*!< I2C4 Fast mode plus */
+#define SYSCFG_PMCR_I2C_PB6_FMP_Pos     (4U)
+#define SYSCFG_PMCR_I2C_PB6_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB6_FMP_Pos) /*!< 0x00000010 */
+#define SYSCFG_PMCR_I2C_PB6_FMP         SYSCFG_PMCR_I2C_PB6_FMP_Msk            /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_PMCR_I2C_PB7_FMP_Pos     (5U)
+#define SYSCFG_PMCR_I2C_PB7_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB7_FMP_Pos) /*!< 0x00000020 */
+#define SYSCFG_PMCR_I2C_PB7_FMP         SYSCFG_PMCR_I2C_PB7_FMP_Msk            /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_PMCR_I2C_PB8_FMP_Pos     (6U)
+#define SYSCFG_PMCR_I2C_PB8_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB8_FMP_Pos) /*!< 0x00000040 */
+#define SYSCFG_PMCR_I2C_PB8_FMP         SYSCFG_PMCR_I2C_PB8_FMP_Msk            /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_PMCR_I2C_PB9_FMP_Pos     (7U)
+#define SYSCFG_PMCR_I2C_PB9_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB9_FMP_Pos) /*!< 0x00000080 */
+#define SYSCFG_PMCR_I2C_PB9_FMP         SYSCFG_PMCR_I2C_PB9_FMP_Msk            /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_PMCR_BOOSTEN_Pos         (8U)
+#define SYSCFG_PMCR_BOOSTEN_Msk         (0x1UL << SYSCFG_PMCR_BOOSTEN_Pos)     /*!< 0x00000100 */
+#define SYSCFG_PMCR_BOOSTEN             SYSCFG_PMCR_BOOSTEN_Msk                /*!< I/O analog switch voltage booster enable */
+
+#define SYSCFG_PMCR_BOOSTVDDSEL_Pos     (9U)
+#define SYSCFG_PMCR_BOOSTVDDSEL_Msk     (0x1UL << SYSCFG_PMCR_BOOSTVDDSEL_Pos) /*!< 0x00000200 */
+#define SYSCFG_PMCR_BOOSTVDDSEL         SYSCFG_PMCR_BOOSTVDDSEL_Msk            /*!< Analog switch supply source selection : VDD/VDDA */
+
+#define SYSCFG_PMCR_EPIS_SEL_Pos        (21U)
+#define SYSCFG_PMCR_EPIS_SEL_Msk        (0x7UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00E00000 */
+#define SYSCFG_PMCR_EPIS_SEL            SYSCFG_PMCR_EPIS_SEL_Msk               /*!< Ethernet PHY Interface Selection */
+#define SYSCFG_PMCR_EPIS_SEL_0          (0x1UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00200000 */
+#define SYSCFG_PMCR_EPIS_SEL_1          (0x2UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00400000 */
+#define SYSCFG_PMCR_EPIS_SEL_2          (0x4UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00800000 */
+#define SYSCFG_PMCR_PA0SO_Pos           (24U)
+#define SYSCFG_PMCR_PA0SO_Msk           (0x1UL << SYSCFG_PMCR_PA0SO_Pos)       /*!< 0x01000000 */
+#define SYSCFG_PMCR_PA0SO               SYSCFG_PMCR_PA0SO_Msk                  /*!< PA0 Switch Open */
+#define SYSCFG_PMCR_PA1SO_Pos           (25U)
+#define SYSCFG_PMCR_PA1SO_Msk           (0x1UL << SYSCFG_PMCR_PA1SO_Pos)       /*!< 0x02000000 */
+#define SYSCFG_PMCR_PA1SO               SYSCFG_PMCR_PA1SO_Msk                  /*!< PA1 Switch Open */
+#define SYSCFG_PMCR_PC2SO_Pos           (26U)
+#define SYSCFG_PMCR_PC2SO_Msk           (0x1UL << SYSCFG_PMCR_PC2SO_Pos)       /*!< 0x04000000 */
+#define SYSCFG_PMCR_PC2SO               SYSCFG_PMCR_PC2SO_Msk                  /*!< PC2 Switch Open */
+#define SYSCFG_PMCR_PC3SO_Pos           (27U)
+#define SYSCFG_PMCR_PC3SO_Msk           (0x1UL << SYSCFG_PMCR_PC3SO_Pos)       /*!< 0x08000000 */
+#define SYSCFG_PMCR_PC3SO               SYSCFG_PMCR_PC3SO_Msk                  /*!< PC3 Switch Open */
+
+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)
+#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)    /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)
+#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)    /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)
+#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)    /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)
+#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)    /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */
+/**
+  * @brief   EXTI0 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000)                 /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001)                 /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002)                 /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003)                 /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004)                 /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x00000005)                 /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x00000006)                 /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000007)                 /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI         ((uint32_t)0x00000008)                 /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x00000009)                 /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x0000000A)                 /*!<PK[0] pin */
+
+/**
+  * @brief   EXTI1 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000)                 /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010)                 /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020)                 /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030)                 /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040)                 /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x00000050)                 /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x00000060)                 /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000070)                 /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI         ((uint32_t)0x00000080)                 /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x00000090)                 /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x000000A0)                 /*!<PK[1] pin */
+/**
+  * @brief   EXTI2 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000)                 /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100)                 /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200)                 /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300)                 /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400)                 /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x00000500)                 /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x00000600)                 /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x00000700)                 /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI         ((uint32_t)0x00000800)                 /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x00000900)                 /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x00000A00)                 /*!<PK[2] pin */
+
+/**
+  * @brief   EXTI3 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000)                 /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000)                 /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000)                 /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000)                 /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000)                 /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x00005000)                 /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x00006000)                 /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x00007000)                 /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI         ((uint32_t)0x00008000)                 /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x00009000)                 /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0x0000A000)                 /*!<PK[3] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
+#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)
+#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)    /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)
+#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)    /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)
+#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)    /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)
+#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)    /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */
+/**
+  * @brief   EXTI4 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000)                 /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001)                 /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002)                 /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003)                 /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004)                 /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x00000005)                 /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x00000006)                 /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x00000007)                 /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI         ((uint32_t)0x00000008)                 /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x00000009)                 /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x0000000A)                 /*!<PK[4] pin */
+/**
+  * @brief   EXTI5 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000)                 /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010)                 /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020)                 /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030)                 /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040)                 /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x00000050)                 /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x00000060)                 /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x00000070)                 /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI         ((uint32_t)0x00000080)                 /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x00000090)                 /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x000000A0)                 /*!<PK[5] pin */
+/**
+  * @brief   EXTI6 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000)                 /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100)                 /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200)                 /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300)                 /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400)                 /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x00000500)                 /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x00000600)                 /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x00000700)                 /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI         ((uint32_t)0x00000800)                 /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x00000900)                 /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x00000A00)                 /*!<PK[6] pin */
+
+/**
+  * @brief   EXTI7 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000)                 /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000)                 /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000)                 /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000)                 /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000)                 /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x00005000)                 /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x00006000)                 /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x00007000)                 /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI         ((uint32_t)0x00008000)                 /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x00009000)                 /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0x0000A000)                 /*!<PK[7] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
+#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)
+#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)    /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)
+#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)    /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)
+#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)   /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)
+#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)   /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */
+
+/**
+  * @brief   EXTI8 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000)                 /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001)                 /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002)                 /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003)                 /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004)                 /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x00000005)                 /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x00000006)                 /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x00000007)                 /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI         ((uint32_t)0x00000008)                 /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x00000009)                 /*!<PJ[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PK         ((uint32_t)0x0000000A)                 /*!<PK[8] pin */
+
+/**
+  * @brief   EXTI9 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000)                 /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010)                 /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020)                 /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030)                 /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040)                 /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x00000050)                 /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x00000060)                 /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x00000070)                 /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI         ((uint32_t)0x00000080)                 /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x00000090)                 /*!<PJ[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PK         ((uint32_t)0x000000A0)                 /*!<PK[9] pin */
+
+/**
+  * @brief   EXTI10 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000)                 /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100)                 /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200)                 /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300)                 /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400)                 /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x00000500)                 /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x00000600)                 /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x00000700)                 /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI        ((uint32_t)0x00000800)                 /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x00000900)                 /*!<PJ[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PK        ((uint32_t)0x00000A00)                 /*!<PK[10] pin */
+
+/**
+  * @brief   EXTI11 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000)                 /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000)                 /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000)                 /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000)                 /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000)                 /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x00005000)                 /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x00006000)                 /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x00007000)                 /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI        ((uint32_t)0x00008000)                 /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x00009000)                 /*!<PJ[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PK        ((uint32_t)0x0000A000)                 /*!<PK[11] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
+#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)
+#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)   /*!< 0x0000000F */
+#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)
+#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)   /*!< 0x000000F0 */
+#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)
+#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)   /*!< 0x00000F00 */
+#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)
+#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)   /*!< 0x0000F000 */
+#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */
+/**
+  * @brief   EXTI12 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000)                 /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001)                 /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002)                 /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003)                 /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004)                 /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x00000005)                 /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x00000006)                 /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x00000007)                 /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI        ((uint32_t)0x00000008)                 /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x00000009)                 /*!<PJ[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PK        ((uint32_t)0x0000000A)                 /*!<PK[12] pin */
+/**
+  * @brief   EXTI13 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000)                 /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010)                 /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020)                 /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030)                 /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040)                 /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x00000050)                 /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x00000060)                 /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x00000070)                 /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI        ((uint32_t)0x00000080)                 /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x00000090)                 /*!<PJ[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PK        ((uint32_t)0x000000A0)                 /*!<PK[13] pin */
+/**
+  * @brief   EXTI14 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000)                 /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100)                 /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200)                 /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300)                 /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400)                 /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x00000500)                 /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x00000600)                 /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x00000700)                 /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI        ((uint32_t)0x00000800)                 /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x00000900)                 /*!<PJ[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PK        ((uint32_t)0x00000A00)                 /*!<PK[14] pin */
+/**
+  * @brief   EXTI15 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000)                 /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000)                 /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000)                 /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000)                 /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000)                 /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x00005000)                 /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x00006000)                 /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x00007000)                 /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI        ((uint32_t)0x00008000)                 /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x00009000)                 /*!<PJ[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PK        ((uint32_t)0x0000A000)                 /*!<PK[15] pin */
+
+/******************  Bit definition for SYSCFG_CFGR register  ******************/
+#define SYSCFG_CFGR_PVDL_Pos            (2U)
+#define SYSCFG_CFGR_PVDL_Msk            (0x1UL << SYSCFG_CFGR_PVDL_Pos)        /*!< 0x00000004 */
+#define SYSCFG_CFGR_PVDL                SYSCFG_CFGR_PVDL_Msk                   /*!<PVD lock enable bit */
+#define SYSCFG_CFGR_FLASHL_Pos          (3U)
+#define SYSCFG_CFGR_FLASHL_Msk          (0x1UL << SYSCFG_CFGR_FLASHL_Pos)      /*!< 0x00000008 */
+#define SYSCFG_CFGR_FLASHL              SYSCFG_CFGR_FLASHL_Msk                 /*!<FLASH double ECC error lock bit */
+#define SYSCFG_CFGR_CM7L_Pos            (6U)
+#define SYSCFG_CFGR_CM7L_Msk            (0x1UL << SYSCFG_CFGR_CM7L_Pos)        /*!< 0x00000040 */
+#define SYSCFG_CFGR_CM7L                SYSCFG_CFGR_CM7L_Msk                   /*!<Cortex-M7 LOCKUP (Hardfault) output enable bit */
+#define SYSCFG_CFGR_BKRAML_Pos          (7U)
+#define SYSCFG_CFGR_BKRAML_Msk          (0x1UL << SYSCFG_CFGR_BKRAML_Pos)      /*!< 0x00000080 */
+#define SYSCFG_CFGR_BKRAML              SYSCFG_CFGR_BKRAML_Msk                 /*!<Backup SRAM double ECC error lock bit */
+#define SYSCFG_CFGR_SRAM4L_Pos          (9U)
+#define SYSCFG_CFGR_SRAM4L_Msk          (0x1UL << SYSCFG_CFGR_SRAM4L_Pos)      /*!< 0x00000200 */
+#define SYSCFG_CFGR_SRAM4L              SYSCFG_CFGR_SRAM4L_Msk                 /*!<SRAM4 double ECC error lock bit */
+#define SYSCFG_CFGR_SRAM3L_Pos          (10U)
+#define SYSCFG_CFGR_SRAM3L_Msk          (0x1UL << SYSCFG_CFGR_SRAM3L_Pos)      /*!< 0x00000400 */
+#define SYSCFG_CFGR_SRAM3L              SYSCFG_CFGR_SRAM3L_Msk                 /*!<SRAM3 double ECC error lock bit */
+#define SYSCFG_CFGR_SRAM2L_Pos          (11U)
+#define SYSCFG_CFGR_SRAM2L_Msk          (0x1UL << SYSCFG_CFGR_SRAM2L_Pos)      /*!< 0x00000800 */
+#define SYSCFG_CFGR_SRAM2L              SYSCFG_CFGR_SRAM2L_Msk                 /*!<SRAM2 double ECC error lock bit */
+#define SYSCFG_CFGR_SRAM1L_Pos          (12U)
+#define SYSCFG_CFGR_SRAM1L_Msk          (0x1UL << SYSCFG_CFGR_SRAM1L_Pos)      /*!< 0x00001000 */
+#define SYSCFG_CFGR_SRAM1L              SYSCFG_CFGR_SRAM1L_Msk                 /*!<SRAM1 double ECC error lock bit */
+#define SYSCFG_CFGR_DTCML_Pos           (13U)
+#define SYSCFG_CFGR_DTCML_Msk           (0x1UL << SYSCFG_CFGR_DTCML_Pos)       /*!< 0x00002000 */
+#define SYSCFG_CFGR_DTCML               SYSCFG_CFGR_DTCML_Msk                  /*!<DTCM double ECC error lock bit */
+#define SYSCFG_CFGR_ITCML_Pos           (14U)
+#define SYSCFG_CFGR_ITCML_Msk           (0x1UL << SYSCFG_CFGR_ITCML_Pos)       /*!< 0x00004000 */
+#define SYSCFG_CFGR_ITCML               SYSCFG_CFGR_ITCML_Msk                  /*!<ITCM double ECC error lock bit */
+#define SYSCFG_CFGR_AXISRAML_Pos        (15U)
+#define SYSCFG_CFGR_AXISRAML_Msk        (0x1UL << SYSCFG_CFGR_AXISRAML_Pos)    /*!< 0x00008000 */
+#define SYSCFG_CFGR_AXISRAML            SYSCFG_CFGR_AXISRAML_Msk               /*!<AXISRAM double ECC error lock bit */
+
+/******************  Bit definition for SYSCFG_CCCSR register  ******************/
+#define SYSCFG_CCCSR_EN_Pos             (0U)
+#define SYSCFG_CCCSR_EN_Msk             (0x1UL << SYSCFG_CCCSR_EN_Pos)         /*!< 0x00000001 */
+#define SYSCFG_CCCSR_EN                 SYSCFG_CCCSR_EN_Msk                    /*!< I/O compensation cell enable */
+#define SYSCFG_CCCSR_CS_Pos             (1U)
+#define SYSCFG_CCCSR_CS_Msk             (0x1UL << SYSCFG_CCCSR_CS_Pos)         /*!< 0x00000002 */
+#define SYSCFG_CCCSR_CS                 SYSCFG_CCCSR_CS_Msk                    /*!< I/O compensation cell code selection */
+#define SYSCFG_CCCSR_READY_Pos          (8U)
+#define SYSCFG_CCCSR_READY_Msk          (0x1UL << SYSCFG_CCCSR_READY_Pos)      /*!< 0x00000100 */
+#define SYSCFG_CCCSR_READY              SYSCFG_CCCSR_READY_Msk                 /*!< I/O compensation cell ready flag */
+#define SYSCFG_CCCSR_HSLV_Pos           (16U)
+#define SYSCFG_CCCSR_HSLV_Msk           (0x1UL << SYSCFG_CCCSR_HSLV_Pos)       /*!< 0x00010000 */
+#define SYSCFG_CCCSR_HSLV               SYSCFG_CCCSR_HSLV_Msk                  /*!< High-speed at low-voltage */
+
+/******************  Bit definition for SYSCFG_CCVR register  *******************/
+#define SYSCFG_CCVR_NCV_Pos             (0U)
+#define SYSCFG_CCVR_NCV_Msk             (0xFUL << SYSCFG_CCVR_NCV_Pos)         /*!< 0x0000000F */
+#define SYSCFG_CCVR_NCV                 SYSCFG_CCVR_NCV_Msk                    /*!< NMOS compensation value */
+#define SYSCFG_CCVR_PCV_Pos             (4U)
+#define SYSCFG_CCVR_PCV_Msk             (0xFUL << SYSCFG_CCVR_PCV_Pos)         /*!< 0x000000F0 */
+#define SYSCFG_CCVR_PCV                 SYSCFG_CCVR_PCV_Msk                    /*!< PMOS compensation value */
+
+/******************  Bit definition for SYSCFG_CCCR register  *******************/
+#define SYSCFG_CCCR_NCC_Pos             (0U)
+#define SYSCFG_CCCR_NCC_Msk             (0xFUL << SYSCFG_CCCR_NCC_Pos)         /*!< 0x0000000F */
+#define SYSCFG_CCCR_NCC                 SYSCFG_CCCR_NCC_Msk                    /*!< NMOS compensation code */
+#define SYSCFG_CCCR_PCC_Pos             (4U)
+#define SYSCFG_CCCR_PCC_Msk             (0xFUL << SYSCFG_CCCR_PCC_Pos)         /*!< 0x000000F0 */
+#define SYSCFG_CCCR_PCC                 SYSCFG_CCCR_PCC_Msk                    /*!< PMOS compensation code */
+/******************  Bit definition for SYSCFG_PWRCR register  *******************/
+#define SYSCFG_PWRCR_ODEN_Pos           (0U)
+#define SYSCFG_PWRCR_ODEN_Msk           (0x1UL << SYSCFG_PWRCR_ODEN_Pos)         /*!< 0x00000001 */
+#define SYSCFG_PWRCR_ODEN               SYSCFG_PWRCR_ODEN_Msk                    /*!< PWR overdrive enable */
+
+/******************  Bit definition for SYSCFG_PKGR register  *******************/
+#define SYSCFG_PKGR_PKG_Pos             (0U)
+#define SYSCFG_PKGR_PKG_Msk             (0xFUL << SYSCFG_PKGR_PKG_Pos)         /*!< 0x0000000F */
+#define SYSCFG_PKGR_PKG                 SYSCFG_PKGR_PKG_Msk                    /*!< Package type */
+
+/******************  Bit definition for SYSCFG_UR0 register  *******************/
+#define SYSCFG_UR0_BKS_Pos              (0U)
+#define SYSCFG_UR0_BKS_Msk              (0x1UL << SYSCFG_UR0_BKS_Pos)          /*!< 0x00000001 */
+#define SYSCFG_UR0_BKS                  SYSCFG_UR0_BKS_Msk                     /*!< Bank Swap */
+#define SYSCFG_UR0_RDP_Pos              (16U)
+#define SYSCFG_UR0_RDP_Msk              (0xFFUL << SYSCFG_UR0_RDP_Pos)         /*!< 0x00FF0000 */
+#define SYSCFG_UR0_RDP                  SYSCFG_UR0_RDP_Msk                     /*!< Readout protection */
+
+/******************  Bit definition for SYSCFG_UR2 register  *******************/
+#define SYSCFG_UR2_BORH_Pos             (0U)
+#define SYSCFG_UR2_BORH_Msk             (0x3UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000003 */
+#define SYSCFG_UR2_BORH                 SYSCFG_UR2_BORH_Msk                    /*!< Brown Out Reset High level */
+#define SYSCFG_UR2_BORH_0               (0x1UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000001 */
+#define SYSCFG_UR2_BORH_1               (0x2UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000002 */
+#define SYSCFG_UR2_BOOT_ADD0_Pos        (16U)
+#define SYSCFG_UR2_BOOT_ADD0_Msk        (0xFFFFUL << SYSCFG_UR2_BOOT_ADD0_Pos) /*!< 0xFFFF0000 */
+#define SYSCFG_UR2_BOOT_ADD0            SYSCFG_UR2_BOOT_ADD0_Msk               /*!< Core Boot Address 0 */
+/******************  Bit definition for SYSCFG_UR3 register  *******************/
+#define SYSCFG_UR3_BOOT_ADD1_Pos        (0U)
+#define SYSCFG_UR3_BOOT_ADD1_Msk        (0xFFFFUL << SYSCFG_UR3_BOOT_ADD1_Pos) /*!< 0x0000FFFF */
+#define SYSCFG_UR3_BOOT_ADD1            SYSCFG_UR3_BOOT_ADD1_Msk               /*!< Core Boot Address 1 */
+
+  /******************  Bit definition for SYSCFG_UR4 register  *******************/
+
+#define SYSCFG_UR4_MEPAD_BANK1_Pos      (16U)
+#define SYSCFG_UR4_MEPAD_BANK1_Msk      (0x1UL << SYSCFG_UR4_MEPAD_BANK1_Pos)  /*!< 0x00010000 */
+#define SYSCFG_UR4_MEPAD_BANK1          SYSCFG_UR4_MEPAD_BANK1_Msk             /*!< Mass Erase Protected Area Disabled for bank 1 */
+
+/******************  Bit definition for SYSCFG_UR5 register  *******************/
+#define SYSCFG_UR5_MESAD_BANK1_Pos      (0U)
+#define SYSCFG_UR5_MESAD_BANK1_Msk      (0x1UL << SYSCFG_UR5_MESAD_BANK1_Pos)  /*!< 0x00000001 */
+#define SYSCFG_UR5_MESAD_BANK1          SYSCFG_UR5_MESAD_BANK1_Msk             /*!< Mass erase secured area disabled for bank 1 */
+#define SYSCFG_UR5_WRPN_BANK1_Pos       (16U)
+#define SYSCFG_UR5_WRPN_BANK1_Msk       (0xFFUL << SYSCFG_UR5_WRPN_BANK1_Pos)  /*!< 0x00FF0000 */
+#define SYSCFG_UR5_WRPN_BANK1           SYSCFG_UR5_WRPN_BANK1_Msk              /*!< Write protection for flash bank 1 */
+
+/******************  Bit definition for SYSCFG_UR6 register  *******************/
+#define SYSCFG_UR6_PABEG_BANK1_Pos      (0U)
+#define SYSCFG_UR6_PABEG_BANK1_Msk      (0xFFFUL << SYSCFG_UR6_PABEG_BANK1_Pos) /*!< 0x00000FFF */
+#define SYSCFG_UR6_PABEG_BANK1          SYSCFG_UR6_PABEG_BANK1_Msk             /*!< Protected area start address for bank 1 */
+#define SYSCFG_UR6_PAEND_BANK1_Pos      (16U)
+#define SYSCFG_UR6_PAEND_BANK1_Msk      (0xFFFUL << SYSCFG_UR6_PAEND_BANK1_Pos) /*!< 0x0FFF0000 */
+#define SYSCFG_UR6_PAEND_BANK1          SYSCFG_UR6_PAEND_BANK1_Msk             /*!< Protected area end address for bank 1 */
+
+/******************  Bit definition for SYSCFG_UR7 register  *******************/
+#define SYSCFG_UR7_SABEG_BANK1_Pos      (0U)
+#define SYSCFG_UR7_SABEG_BANK1_Msk      (0xFFFUL << SYSCFG_UR7_SABEG_BANK1_Pos) /*!< 0x00000FFF */
+#define SYSCFG_UR7_SABEG_BANK1          SYSCFG_UR7_SABEG_BANK1_Msk             /*!< Secured area start address for bank 1 */
+#define SYSCFG_UR7_SAEND_BANK1_Pos      (16U)
+#define SYSCFG_UR7_SAEND_BANK1_Msk      (0xFFFUL << SYSCFG_UR7_SAEND_BANK1_Pos) /*!< 0x0FFF0000 */
+#define SYSCFG_UR7_SAEND_BANK1          SYSCFG_UR7_SAEND_BANK1_Msk             /*!< Secured area end address for bank 1 */
+
+/******************  Bit definition for SYSCFG_UR8 register  *******************/
+#define SYSCFG_UR8_MEPAD_BANK2_Pos      (0U)
+#define SYSCFG_UR8_MEPAD_BANK2_Msk      (0x1UL << SYSCFG_UR8_MEPAD_BANK2_Pos)  /*!< 0x00000001 */
+#define SYSCFG_UR8_MEPAD_BANK2          SYSCFG_UR8_MEPAD_BANK2_Msk             /*!< Mass erase Protected area disabled for bank 2 */
+#define SYSCFG_UR8_MESAD_BANK2_Pos      (16U)
+#define SYSCFG_UR8_MESAD_BANK2_Msk      (0x1UL << SYSCFG_UR8_MESAD_BANK2_Pos)  /*!< 0x00010000 */
+#define SYSCFG_UR8_MESAD_BANK2          SYSCFG_UR8_MESAD_BANK2_Msk             /*!< Mass Erase Secured Area Disabled for bank 2 */
+
+/******************  Bit definition for SYSCFG_UR9 register  *******************/
+#define SYSCFG_UR9_WRPN_BANK2_Pos       (0U)
+#define SYSCFG_UR9_WRPN_BANK2_Msk       (0xFFUL << SYSCFG_UR9_WRPN_BANK2_Pos)  /*!< 0x000000FF */
+#define SYSCFG_UR9_WRPN_BANK2           SYSCFG_UR9_WRPN_BANK2_Msk              /*!< Write protection for flash bank 2 */
+#define SYSCFG_UR9_PABEG_BANK2_Pos      (16U)
+#define SYSCFG_UR9_PABEG_BANK2_Msk      (0xFFFUL << SYSCFG_UR9_PABEG_BANK2_Pos) /*!< 0x0FFF0000 */
+#define SYSCFG_UR9_PABEG_BANK2          SYSCFG_UR9_PABEG_BANK2_Msk             /*!< Protected area start address for bank 2 */
+
+/******************  Bit definition for SYSCFG_UR10 register  *******************/
+#define SYSCFG_UR10_PAEND_BANK2_Pos     (0U)
+#define SYSCFG_UR10_PAEND_BANK2_Msk     (0xFFFUL << SYSCFG_UR10_PAEND_BANK2_Pos) /*!< 0x00000FFF */
+#define SYSCFG_UR10_PAEND_BANK2         SYSCFG_UR10_PAEND_BANK2_Msk            /*!< Protected area end address for bank 2 */
+#define SYSCFG_UR10_SABEG_BANK2_Pos     (16U)
+#define SYSCFG_UR10_SABEG_BANK2_Msk     (0xFFFUL << SYSCFG_UR10_SABEG_BANK2_Pos) /*!< 0x0FFF0000 */
+#define SYSCFG_UR10_SABEG_BANK2         SYSCFG_UR10_SABEG_BANK2_Msk            /*!< Secured area start address for bank 2 */
+
+/******************  Bit definition for SYSCFG_UR11 register  *******************/
+#define SYSCFG_UR11_SAEND_BANK2_Pos     (0U)
+#define SYSCFG_UR11_SAEND_BANK2_Msk     (0xFFFUL << SYSCFG_UR11_SAEND_BANK2_Pos) /*!< 0x00000FFF */
+#define SYSCFG_UR11_SAEND_BANK2         SYSCFG_UR11_SAEND_BANK2_Msk            /*!< Secured area end address for bank 2 */
+#define SYSCFG_UR11_IWDG1M_Pos          (16U)
+#define SYSCFG_UR11_IWDG1M_Msk          (0x1UL << SYSCFG_UR11_IWDG1M_Pos)      /*!< 0x00010000 */
+#define SYSCFG_UR11_IWDG1M              SYSCFG_UR11_IWDG1M_Msk                 /*!< Independent Watchdog 1 mode (SW or HW) */
+
+/******************  Bit definition for SYSCFG_UR12 register  *******************/
+
+#define SYSCFG_UR12_SECURE_Pos          (16U)
+#define SYSCFG_UR12_SECURE_Msk          (0x1UL << SYSCFG_UR12_SECURE_Pos)      /*!< 0x00010000 */
+#define SYSCFG_UR12_SECURE              SYSCFG_UR12_SECURE_Msk                 /*!< Secure mode status */
+
+/******************  Bit definition for SYSCFG_UR13 register  *******************/
+#define SYSCFG_UR13_SDRS_Pos            (0U)
+#define SYSCFG_UR13_SDRS_Msk            (0x3UL << SYSCFG_UR13_SDRS_Pos)        /*!< 0x00000003 */
+#define SYSCFG_UR13_SDRS                SYSCFG_UR13_SDRS_Msk                   /*!< Secured DTCM RAM Size */
+#define SYSCFG_UR13_D1SBRST_Pos         (16U)
+#define SYSCFG_UR13_D1SBRST_Msk         (0x1UL << SYSCFG_UR13_D1SBRST_Pos)     /*!< 0x00010000 */
+#define SYSCFG_UR13_D1SBRST             SYSCFG_UR13_D1SBRST_Msk                /*!< D1 Standby reset */
+
+/******************  Bit definition for SYSCFG_UR14 register  *******************/
+#define SYSCFG_UR14_D1STPRST_Pos        (0U)
+#define SYSCFG_UR14_D1STPRST_Msk        (0x1UL << SYSCFG_UR14_D1STPRST_Pos)    /*!< 0x00000001 */
+#define SYSCFG_UR14_D1STPRST            SYSCFG_UR14_D1STPRST_Msk               /*!< D1 Stop Reset */
+
+/******************  Bit definition for SYSCFG_UR15 register  *******************/
+#define SYSCFG_UR15_FZIWDGSTB_Pos       (16U)
+#define SYSCFG_UR15_FZIWDGSTB_Msk       (0x1UL << SYSCFG_UR15_FZIWDGSTB_Pos)   /*!< 0x00010000 */
+#define SYSCFG_UR15_FZIWDGSTB           SYSCFG_UR15_FZIWDGSTB_Msk              /*!< Freeze independent watchdogs in Standby mode */
+
+/******************  Bit definition for SYSCFG_UR16 register  *******************/
+#define SYSCFG_UR16_FZIWDGSTP_Pos       (0U)
+#define SYSCFG_UR16_FZIWDGSTP_Msk       (0x1UL << SYSCFG_UR16_FZIWDGSTP_Pos)   /*!< 0x00000001 */
+#define SYSCFG_UR16_FZIWDGSTP           SYSCFG_UR16_FZIWDGSTP_Msk              /*!< Freeze independent watchdogs in Stop mode */
+#define SYSCFG_UR16_PKP_Pos             (16U)
+#define SYSCFG_UR16_PKP_Msk             (0x1UL << SYSCFG_UR16_PKP_Pos)         /*!< 0x00010000 */
+#define SYSCFG_UR16_PKP                 SYSCFG_UR16_PKP_Msk                    /*!< Private key programmed */
+
+/******************  Bit definition for SYSCFG_UR17 register  *******************/
+#define SYSCFG_UR17_IOHSLV_Pos          (0U)
+#define SYSCFG_UR17_IOHSLV_Msk          (0x1UL << SYSCFG_UR17_IOHSLV_Pos)      /*!< 0x00000001 */
+#define SYSCFG_UR17_IOHSLV              SYSCFG_UR17_IOHSLV_Msk                 /*!< I/O high speed / low voltage */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    TIM                                     */
+/*                                                                            */
+/******************************************************************************/
+#define TIM_BREAK_INPUT_SUPPORT             /*!<TIM Break input feature */
+
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define TIM_CR1_CEN_Pos           (0U)
+#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */
+#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos          (1U)
+#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */
+#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
+#define TIM_CR1_URS_Pos           (2U)
+#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */
+#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
+#define TIM_CR1_OPM_Pos           (3U)
+#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */
+#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos           (4U)
+#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */
+#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
+
+#define TIM_CR1_CMS_Pos           (5U)
+#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */
+#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
+#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos          (7U)
+#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */
+#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos           (8U)
+#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */
+#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
+#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
+
+#define TIM_CR1_UIFREMAP_Pos      (11U)
+#define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */
+#define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define TIM_CR2_CCPC_Pos          (0U)
+#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */
+#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos          (2U)
+#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */
+#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos          (3U)
+#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */
+#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos           (4U)
+#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000070 */
+#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
+#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
+#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos          (7U)
+#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */
+#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos          (8U)
+#define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */
+#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos         (9U)
+#define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */
+#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos          (10U)
+#define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */
+#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos         (11U)
+#define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */
+#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos          (12U)
+#define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */
+#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos         (13U)
+#define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */
+#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos          (14U)
+#define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */
+#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
+#define TIM_CR2_OIS5_Pos          (16U)
+#define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
+#define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */
+#define TIM_CR2_OIS6_Pos          (17U)
+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00020000 */
+#define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */
+
+#define TIM_CR2_MMS2_Pos          (20U)
+#define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */
+#define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00100000 */
+#define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00200000 */
+#define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00400000 */
+#define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00800000 */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define TIM_SMCR_SMS_Pos          (0U)
+#define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */
+#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000004 */
+#define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)               /*!< 0x00010000 */
+
+#define TIM_SMCR_TS_Pos           (4U)
+#define TIM_SMCR_TS_Msk           (0x30007UL << TIM_SMCR_TS_Pos)               /*!< 0x00300070 */
+#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[4:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0             (0x00001UL << TIM_SMCR_TS_Pos)                /*!< 0x00000010 */
+#define TIM_SMCR_TS_1             (0x00002UL << TIM_SMCR_TS_Pos)                /*!< 0x00000020 */
+#define TIM_SMCR_TS_2             (0x00004UL << TIM_SMCR_TS_Pos)                /*!< 0x00000040 */
+#define TIM_SMCR_TS_3             (0x10000UL << TIM_SMCR_TS_Pos)                /*!< 0x00100000 */
+#define TIM_SMCR_TS_4             (0x20000UL << TIM_SMCR_TS_Pos)                /*!< 0x00200000 */
+
+#define TIM_SMCR_MSM_Pos          (7U)
+#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */
+#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos          (8U)
+#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */
+#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos         (12U)
+#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */
+#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos          (14U)
+#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */
+#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos          (15U)
+#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */
+#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define TIM_DIER_UIE_Pos          (0U)
+#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */
+#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos        (1U)
+#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */
+#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos        (2U)
+#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */
+#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos        (3U)
+#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */
+#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos        (4U)
+#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */
+#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos        (5U)
+#define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */
+#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos          (6U)
+#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */
+#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos          (7U)
+#define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */
+#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos          (8U)
+#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */
+#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos        (9U)
+#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */
+#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos        (10U)
+#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */
+#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos        (11U)
+#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */
+#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos        (12U)
+#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */
+#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos        (13U)
+#define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */
+#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos          (14U)
+#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */
+#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define TIM_SR_UIF_Pos            (0U)
+#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */
+#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos          (1U)
+#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */
+#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos          (2U)
+#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */
+#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos          (3U)
+#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */
+#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos          (4U)
+#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */
+#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos          (5U)
+#define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */
+#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos            (6U)
+#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */
+#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos            (7U)
+#define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */
+#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
+#define TIM_SR_B2IF_Pos           (8U)
+#define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */
+#define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break2 interrupt Flag */
+#define TIM_SR_CC1OF_Pos          (9U)
+#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */
+#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos          (10U)
+#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */
+#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos          (11U)
+#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */
+#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos          (12U)
+#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */
+#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
+#define TIM_SR_CC5IF_Pos          (16U)
+#define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */
+#define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */
+#define TIM_SR_CC6IF_Pos          (17U)
+#define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */
+#define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */
+#define TIM_SR_SBIF_Pos           (13U)
+#define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */
+#define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!< System Break Flag */
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define TIM_EGR_UG_Pos            (0U)
+#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */
+#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos          (1U)
+#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */
+#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos          (2U)
+#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */
+#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos          (3U)
+#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */
+#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos          (4U)
+#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */
+#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos          (5U)
+#define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */
+#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos            (6U)
+#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */
+#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos            (7U)
+#define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */
+#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */
+#define TIM_EGR_B2G_Pos           (8U)
+#define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */
+#define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break Generation */
+
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define TIM_CCMR1_CC1S_Pos        (0U)
+#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos       (2U)
+#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos       (3U)
+#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos        (4U)
+#define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */
+#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000040 */
+#define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010000 */
+
+#define TIM_CCMR1_OC1CE_Pos       (7U)
+#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos        (8U)
+#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos       (10U)
+#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos       (11U)
+#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos        (12U)
+#define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */
+#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00004000 */
+#define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x01000000 */
+
+#define TIM_CCMR1_OC2CE_Pos       (15U)
+#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos      (2U)
+#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos        (4U)
+#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos      (10U)
+#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos        (12U)
+#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define TIM_CCMR2_CC3S_Pos        (0U)
+#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos       (2U)
+#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos       (3U)
+#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos        (4U)
+#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
+#define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010000 */
+
+#define TIM_CCMR2_OC3CE_Pos       (7U)
+#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos        (8U)
+#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos       (10U)
+#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos       (11U)
+#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos        (12U)
+#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
+#define TIM_CCMR2_OC4M_3          (0x100UL << TIM_CCMR2_OC4M_Pos)               /*!< 0x00100000 */
+
+#define TIM_CCMR2_OC4CE_Pos       (15U)
+#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos      (2U)
+#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos        (4U)
+#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos      (10U)
+#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos        (12U)
+#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define TIM_CCER_CC1E_Pos         (0U)
+#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */
+#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos         (1U)
+#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */
+#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos        (2U)
+#define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */
+#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos        (3U)
+#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */
+#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos         (4U)
+#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */
+#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos         (5U)
+#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */
+#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos        (6U)
+#define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */
+#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos        (7U)
+#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */
+#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos         (8U)
+#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */
+#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos         (9U)
+#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */
+#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos        (10U)
+#define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */
+#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos        (11U)
+#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */
+#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos         (12U)
+#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */
+#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos         (13U)
+#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */
+#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos        (15U)
+#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */
+#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
+#define TIM_CCER_CC5E_Pos         (16U)
+#define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */
+#define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */
+#define TIM_CCER_CC5P_Pos         (17U)
+#define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */
+#define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */
+#define TIM_CCER_CC6E_Pos         (20U)
+#define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */
+#define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */
+#define TIM_CCER_CC6P_Pos         (21U)
+#define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */
+#define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define TIM_CNT_CNT_Pos           (0U)
+#define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
+#define TIM_CNT_UIFCPY_Pos        (31U)
+#define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */
+#define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy */
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define TIM_PSC_PSC_Pos           (0U)
+#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */
+#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define TIM_ARR_ARR_Pos           (0U)
+#define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RCR register  ********************/
+#define TIM_RCR_REP_Pos           (0U)
+#define TIM_RCR_REP_Msk           (0xFFUL << TIM_RCR_REP_Pos)                  /*!< 0x000000FF */
+#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define TIM_CCR1_CCR1_Pos         (0U)
+#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)              /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define TIM_CCR2_CCR2_Pos         (0U)
+#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)              /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define TIM_CCR3_CCR3_Pos         (0U)
+#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)              /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define TIM_CCR4_CCR4_Pos         (0U)
+#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)              /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_CCR5 register  *******************/
+#define TIM_CCR5_CCR5_Pos         (0U)
+#define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)          /*!< 0xFFFFFFFF */
+#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */
+#define TIM_CCR5_GC5C1_Pos        (29U)
+#define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */
+#define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */
+#define TIM_CCR5_GC5C2_Pos        (30U)
+#define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */
+#define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */
+#define TIM_CCR5_GC5C3_Pos        (31U)
+#define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */
+#define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */
+
+/*******************  Bit definition for TIM_CCR6 register  *******************/
+#define TIM_CCR6_CCR6_Pos         (0U)
+#define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */
+#define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define TIM_BDTR_DTG_Pos          (0U)
+#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */
+#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000001 */
+#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000002 */
+#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000004 */
+#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000008 */
+#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000010 */
+#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000020 */
+#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000040 */
+#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000080 */
+
+#define TIM_BDTR_LOCK_Pos         (8U)
+#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */
+#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000100 */
+#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000200 */
+
+#define TIM_BDTR_OSSI_Pos         (10U)
+#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */
+#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos         (11U)
+#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */
+#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos          (12U)
+#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */
+#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break1 */
+#define TIM_BDTR_BKP_Pos          (13U)
+#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */
+#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break1 */
+#define TIM_BDTR_AOE_Pos          (14U)
+#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */
+#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos          (15U)
+#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */
+#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
+
+#define TIM_BDTR_BKF_Pos          (16U)
+#define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */
+#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break1 */
+#define TIM_BDTR_BK2F_Pos         (20U)
+#define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */
+#define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break2 */
+
+#define TIM_BDTR_BK2E_Pos         (24U)
+#define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */
+#define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break2 */
+#define TIM_BDTR_BK2P_Pos         (25U)
+#define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */
+#define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break2 */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define TIM_DCR_DBA_Pos           (0U)
+#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */
+#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
+#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
+#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
+#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
+#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos           (8U)
+#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */
+#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
+#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
+#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
+#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
+#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define TIM_DMAR_DMAB_Pos         (0U)
+#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)              /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
+
+/******************  Bit definition for TIM_CCMR3 register  *******************/
+#define TIM_CCMR3_OC5FE_Pos       (2U)
+#define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */
+#define TIM_CCMR3_OC5PE_Pos       (3U)
+#define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */
+#define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
+
+#define TIM_CCMR3_OC5M_Pos        (4U)
+#define TIM_CCMR3_OC5M_Msk        (0x7UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00000070 */
+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_0          (0x1UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000010 */
+#define TIM_CCMR3_OC5M_1          (0x2UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000020 */
+#define TIM_CCMR3_OC5M_2          (0x4UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000040 */
+#define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010000 */
+
+#define TIM_CCMR3_OC5CE_Pos       (7U)
+#define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */
+#define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */
+
+#define TIM_CCMR3_OC6FE_Pos       (10U)
+#define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR3_OC6PE_Pos       (11U)
+#define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */
+#define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR3_OC6M_Pos        (12U)
+#define TIM_CCMR3_OC6M_Msk        (0x7UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x00007000 */
+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR3_OC6M_0          (0x1UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00001000 */
+#define TIM_CCMR3_OC6M_1          (0x2UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00002000 */
+#define TIM_CCMR3_OC6M_2          (0x4UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00004000 */
+#define TIM_CCMR3_OC6M_3          (0x100UL << TIM_CCMR3_OC6M_Pos)               /*!< 0x00100000 */
+
+#define TIM_CCMR3_OC6CE_Pos       (15U)
+#define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
+#define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 4 Clear Enable */
+/*******************  Bit definition for TIM1_AF1 register  *********************/
+#define TIM1_AF1_BKINE_Pos        (0U)
+#define TIM1_AF1_BKINE_Msk        (0x1UL << TIM1_AF1_BKINE_Pos)                /*!< 0x00000001 */
+#define TIM1_AF1_BKINE            TIM1_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */
+#define TIM1_AF1_BKCMP1E_Pos      (1U)
+#define TIM1_AF1_BKCMP1E_Msk      (0x1UL << TIM1_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */
+#define TIM1_AF1_BKCMP1E          TIM1_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */
+#define TIM1_AF1_BKCMP2E_Pos      (2U)
+#define TIM1_AF1_BKCMP2E_Msk      (0x1UL << TIM1_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */
+#define TIM1_AF1_BKCMP2E          TIM1_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit */
+#define TIM1_AF1_BKDF1BK0E_Pos    (8U)
+#define TIM1_AF1_BKDF1BK0E_Msk    (0x1UL << TIM1_AF1_BKDF1BK0E_Pos)            /*!< 0x00000100 */
+#define TIM1_AF1_BKDF1BK0E        TIM1_AF1_BKDF1BK0E_Msk                       /*!<BKDF1BK0E Break input DFSDM Break 0 */
+#define TIM1_AF1_BKINP_Pos        (9U)
+#define TIM1_AF1_BKINP_Msk        (0x1UL << TIM1_AF1_BKINP_Pos)                /*!< 0x00000200 */
+#define TIM1_AF1_BKINP            TIM1_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */
+#define TIM1_AF1_BKCMP1P_Pos      (10U)
+#define TIM1_AF1_BKCMP1P_Msk      (0x1UL << TIM1_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */
+#define TIM1_AF1_BKCMP1P          TIM1_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */
+#define TIM1_AF1_BKCMP2P_Pos      (11U)
+#define TIM1_AF1_BKCMP2P_Msk      (0x1UL << TIM1_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */
+#define TIM1_AF1_BKCMP2P          TIM1_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */
+
+#define TIM1_AF1_ETRSEL_Pos       (14U)
+#define TIM1_AF1_ETRSEL_Msk       (0xFUL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */
+#define TIM1_AF1_ETRSEL           TIM1_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM1 ETRSEL) */
+#define TIM1_AF1_ETRSEL_0         (0x1UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00004000 */
+#define TIM1_AF1_ETRSEL_1         (0x2UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00008000 */
+#define TIM1_AF1_ETRSEL_2         (0x4UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00010000 */
+#define TIM1_AF1_ETRSEL_3         (0x8UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00020000 */
+
+/*******************  Bit definition for TIM1_AF2 register  *********************/
+#define TIM1_AF2_BK2INE_Pos       (0U)
+#define TIM1_AF2_BK2INE_Msk       (0x1UL << TIM1_AF2_BK2INE_Pos)               /*!< 0x00000001 */
+#define TIM1_AF2_BK2INE           TIM1_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */
+#define TIM1_AF2_BK2CMP1E_Pos     (1U)
+#define TIM1_AF2_BK2CMP1E_Msk     (0x1UL << TIM1_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */
+#define TIM1_AF2_BK2CMP1E         TIM1_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */
+#define TIM1_AF2_BK2CMP2E_Pos     (2U)
+#define TIM1_AF2_BK2CMP2E_Msk     (0x1UL << TIM1_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */
+#define TIM1_AF2_BK2CMP2E         TIM1_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */
+#define TIM1_AF2_BK2DFBK1E_Pos    (8U)
+#define TIM1_AF2_BK2DFBK1E_Msk    (0x1UL << TIM1_AF2_BK2DFBK1E_Pos)            /*!< 0x00000100 */
+#define TIM1_AF2_BK2DFBK1E        TIM1_AF2_BK2DFBK1E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 1 */
+#define TIM1_AF2_BK2INP_Pos       (9U)
+#define TIM1_AF2_BK2INP_Msk       (0x1UL << TIM1_AF2_BK2INP_Pos)               /*!< 0x00000200 */
+#define TIM1_AF2_BK2INP           TIM1_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */
+#define TIM1_AF2_BK2CMP1P_Pos     (10U)
+#define TIM1_AF2_BK2CMP1P_Msk     (0x1UL << TIM1_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */
+#define TIM1_AF2_BK2CMP1P         TIM1_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */
+#define TIM1_AF2_BK2CMP2P_Pos     (11U)
+#define TIM1_AF2_BK2CMP2P_Msk     (0x1UL << TIM1_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */
+#define TIM1_AF2_BK2CMP2P         TIM1_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */
+
+/*******************  Bit definition for TIM_TISEL register  *********************/
+#define TIM_TISEL_TI1SEL_Pos      (0U)
+#define TIM_TISEL_TI1SEL_Msk      (0xFUL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x0000000F */
+#define TIM_TISEL_TI1SEL          TIM_TISEL_TI1SEL_Msk                         /*!<TI1SEL[3:0] bits (TIM TI1 SEL)*/
+#define TIM_TISEL_TI1SEL_0        (0x1UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000001 */
+#define TIM_TISEL_TI1SEL_1        (0x2UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000002 */
+#define TIM_TISEL_TI1SEL_2        (0x4UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000004 */
+#define TIM_TISEL_TI1SEL_3        (0x8UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000008 */
+
+#define TIM_TISEL_TI2SEL_Pos      (8U)
+#define TIM_TISEL_TI2SEL_Msk      (0xFUL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000F00 */
+#define TIM_TISEL_TI2SEL          TIM_TISEL_TI2SEL_Msk                         /*!<TI2SEL[3:0] bits (TIM TI2 SEL)*/
+#define TIM_TISEL_TI2SEL_0        (0x1UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000100 */
+#define TIM_TISEL_TI2SEL_1        (0x2UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000200 */
+#define TIM_TISEL_TI2SEL_2        (0x4UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000400 */
+#define TIM_TISEL_TI2SEL_3        (0x8UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000800 */
+
+#define TIM_TISEL_TI3SEL_Pos      (16U)
+#define TIM_TISEL_TI3SEL_Msk      (0xFUL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x000F0000 */
+#define TIM_TISEL_TI3SEL          TIM_TISEL_TI3SEL_Msk                         /*!<TI3SEL[3:0] bits (TIM TI3 SEL)*/
+#define TIM_TISEL_TI3SEL_0        (0x1UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00010000 */
+#define TIM_TISEL_TI3SEL_1        (0x2UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00020000 */
+#define TIM_TISEL_TI3SEL_2        (0x4UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00040000 */
+#define TIM_TISEL_TI3SEL_3        (0x8UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00080000 */
+
+#define TIM_TISEL_TI4SEL_Pos      (24U)
+#define TIM_TISEL_TI4SEL_Msk      (0xFUL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x0F000000 */
+#define TIM_TISEL_TI4SEL          TIM_TISEL_TI4SEL_Msk                         /*!<TI4SEL[3:0] bits (TIM TI4 SEL)*/
+#define TIM_TISEL_TI4SEL_0        (0x1UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x01000000 */
+#define TIM_TISEL_TI4SEL_1        (0x2UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x02000000 */
+#define TIM_TISEL_TI4SEL_2        (0x4UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x04000000 */
+#define TIM_TISEL_TI4SEL_3        (0x8UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x08000000 */
+
+/*******************  Bit definition for TIM8_AF1 register  *********************/
+#define TIM8_AF1_BKINE_Pos        (0U)
+#define TIM8_AF1_BKINE_Msk        (0x1UL << TIM8_AF1_BKINE_Pos)                /*!< 0x00000001 */
+#define TIM8_AF1_BKINE            TIM8_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */
+#define TIM8_AF1_BKCMP1E_Pos      (1U)
+#define TIM8_AF1_BKCMP1E_Msk      (0x1UL << TIM8_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */
+#define TIM8_AF1_BKCMP1E          TIM8_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */
+#define TIM8_AF1_BKCMP2E_Pos      (2U)
+#define TIM8_AF1_BKCMP2E_Msk      (0x1UL << TIM8_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */
+#define TIM8_AF1_BKCMP2E          TIM8_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit  */
+#define TIM8_AF1_BKDFBK2E_Pos     (8U)
+#define TIM8_AF1_BKDFBK2E_Msk     (0x1UL << TIM8_AF1_BKDFBK2E_Pos)             /*!< 0x00000100 */
+#define TIM8_AF1_BKDFBK2E         TIM8_AF1_BKDFBK2E_Msk                        /*!<BKDFBK2E Break input DFSDM Break 2 */
+#define TIM8_AF1_BKINP_Pos        (9U)
+#define TIM8_AF1_BKINP_Msk        (0x1UL << TIM8_AF1_BKINP_Pos)                /*!< 0x00000200 */
+#define TIM8_AF1_BKINP            TIM8_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */
+#define TIM8_AF1_BKCMP1P_Pos      (10U)
+#define TIM8_AF1_BKCMP1P_Msk      (0x1UL << TIM8_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */
+#define TIM8_AF1_BKCMP1P          TIM8_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */
+#define TIM8_AF1_BKCMP2P_Pos      (11U)
+#define TIM8_AF1_BKCMP2P_Msk      (0x1UL << TIM8_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */
+#define TIM8_AF1_BKCMP2P          TIM8_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */
+
+#define TIM8_AF1_ETRSEL_Pos       (14U)
+#define TIM8_AF1_ETRSEL_Msk       (0xFUL << TIM8_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */
+#define TIM8_AF1_ETRSEL           TIM8_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM8 ETRSEL) */
+#define TIM8_AF1_ETRSEL_0         (0x1UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00004000 */
+#define TIM8_AF1_ETRSEL_1         (0x2UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00008000 */
+#define TIM8_AF1_ETRSEL_2         (0x4UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00010000 */
+#define TIM8_AF1_ETRSEL_3         (0x8UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00020000 */
+/*******************  Bit definition for TIM8_AF2 register  *********************/
+#define TIM8_AF2_BK2INE_Pos       (0U)
+#define TIM8_AF2_BK2INE_Msk       (0x1UL << TIM8_AF2_BK2INE_Pos)               /*!< 0x00000001 */
+#define TIM8_AF2_BK2INE           TIM8_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */
+#define TIM8_AF2_BK2CMP1E_Pos     (1U)
+#define TIM8_AF2_BK2CMP1E_Msk     (0x1UL << TIM8_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */
+#define TIM8_AF2_BK2CMP1E         TIM8_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */
+#define TIM8_AF2_BK2CMP2E_Pos     (2U)
+#define TIM8_AF2_BK2CMP2E_Msk     (0x1UL << TIM8_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */
+#define TIM8_AF2_BK2CMP2E         TIM8_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */
+#define TIM8_AF2_BK2DFBK3E_Pos    (8U)
+#define TIM8_AF2_BK2DFBK3E_Msk    (0x1UL << TIM8_AF2_BK2DFBK3E_Pos)            /*!< 0x00000100 */
+#define TIM8_AF2_BK2DFBK3E        TIM8_AF2_BK2DFBK3E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 3 */
+#define TIM8_AF2_BK2INP_Pos       (9U)
+#define TIM8_AF2_BK2INP_Msk       (0x1UL << TIM8_AF2_BK2INP_Pos)               /*!< 0x00000200 */
+#define TIM8_AF2_BK2INP           TIM8_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */
+#define TIM8_AF2_BK2CMP1P_Pos     (10U)
+#define TIM8_AF2_BK2CMP1P_Msk     (0x1UL << TIM8_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */
+#define TIM8_AF2_BK2CMP1P         TIM8_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */
+#define TIM8_AF2_BK2CMP2P_Pos     (11U)
+#define TIM8_AF2_BK2CMP2P_Msk     (0x1UL << TIM8_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */
+#define TIM8_AF2_BK2CMP2P         TIM8_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */
+
+/*******************  Bit definition for TIM2_AF1 register  *********************/
+#define TIM2_AF1_ETRSEL_Pos      (14U)
+#define TIM2_AF1_ETRSEL_Msk      (0xFUL << TIM2_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */
+#define TIM2_AF1_ETRSEL          TIM2_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM2 ETRSEL) */
+#define TIM2_AF1_ETRSEL_0        (0x1UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */
+#define TIM2_AF1_ETRSEL_1        (0x2UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */
+#define TIM2_AF1_ETRSEL_2        (0x4UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */
+#define TIM2_AF1_ETRSEL_3        (0x8UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */
+
+/*******************  Bit definition for TIM3_AF1 register  *********************/
+#define TIM3_AF1_ETRSEL_Pos      (14U)
+#define TIM3_AF1_ETRSEL_Msk      (0xFUL << TIM3_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */
+#define TIM3_AF1_ETRSEL          TIM3_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM3 ETRSEL) */
+#define TIM3_AF1_ETRSEL_0        (0x1UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */
+#define TIM3_AF1_ETRSEL_1        (0x2UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */
+#define TIM3_AF1_ETRSEL_2        (0x4UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */
+#define TIM3_AF1_ETRSEL_3        (0x8UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */
+
+/*******************  Bit definition for TIM5_AF1 register  *********************/
+#define TIM5_AF1_ETRSEL_Pos      (14U)
+#define TIM5_AF1_ETRSEL_Msk      (0xFUL << TIM5_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */
+#define TIM5_AF1_ETRSEL          TIM5_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM5 ETRSEL) */
+#define TIM5_AF1_ETRSEL_0        (0x1UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */
+#define TIM5_AF1_ETRSEL_1        (0x2UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */
+#define TIM5_AF1_ETRSEL_2        (0x4UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */
+#define TIM5_AF1_ETRSEL_3        (0x8UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */
+
+/*******************  Bit definition for TIM15_AF1 register  *********************/
+#define TIM15_AF1_BKINE_Pos        (0U)
+#define TIM15_AF1_BKINE_Msk        (0x1UL << TIM15_AF1_BKINE_Pos)              /*!< 0x00000001 */
+#define TIM15_AF1_BKINE            TIM15_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */
+#define TIM15_AF1_BKCMP1E_Pos      (1U)
+#define TIM15_AF1_BKCMP1E_Msk      (0x1UL << TIM15_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */
+#define TIM15_AF1_BKCMP1E          TIM15_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */
+#define TIM15_AF1_BKCMP2E_Pos      (2U)
+#define TIM15_AF1_BKCMP2E_Msk      (0x1UL << TIM15_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */
+#define TIM15_AF1_BKCMP2E          TIM15_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */
+#define TIM15_AF1_BKDF1BK2E_Pos    (8U)
+#define TIM15_AF1_BKDF1BK2E_Msk    (0x1UL << TIM15_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */
+#define TIM15_AF1_BKDF1BK2E        TIM15_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[0] enable */
+#define TIM15_AF1_BKINP_Pos        (9U)
+#define TIM15_AF1_BKINP_Msk        (0x1UL << TIM15_AF1_BKINP_Pos)              /*!< 0x00000200 */
+#define TIM15_AF1_BKINP            TIM15_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */
+#define TIM15_AF1_BKCMP1P_Pos      (10U)
+#define TIM15_AF1_BKCMP1P_Msk      (0x1UL << TIM15_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */
+#define TIM15_AF1_BKCMP1P          TIM15_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */
+#define TIM15_AF1_BKCMP2P_Pos      (11U)
+#define TIM15_AF1_BKCMP2P_Msk      (0x1UL << TIM15_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */
+#define TIM15_AF1_BKCMP2P          TIM15_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */
+
+/*******************  Bit definition for TIM16_ register  *********************/
+#define TIM16_AF1_BKINE_Pos        (0U)
+#define TIM16_AF1_BKINE_Msk        (0x1UL << TIM16_AF1_BKINE_Pos)              /*!< 0x00000001 */
+#define TIM16_AF1_BKINE            TIM16_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */
+#define TIM16_AF1_BKCMP1E_Pos      (1U)
+#define TIM16_AF1_BKCMP1E_Msk      (0x1UL << TIM16_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */
+#define TIM16_AF1_BKCMP1E          TIM16_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */
+#define TIM16_AF1_BKCMP2E_Pos      (2U)
+#define TIM16_AF1_BKCMP2E_Msk      (0x1UL << TIM16_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */
+#define TIM16_AF1_BKCMP2E          TIM16_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */
+#define TIM16_AF1_BKDF1BK2E_Pos    (8U)
+#define TIM16_AF1_BKDF1BK2E_Msk    (0x1UL << TIM16_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */
+#define TIM16_AF1_BKDF1BK2E        TIM16_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[1] enable */
+#define TIM16_AF1_BKINP_Pos        (9U)
+#define TIM16_AF1_BKINP_Msk        (0x1UL << TIM16_AF1_BKINP_Pos)              /*!< 0x00000200 */
+#define TIM16_AF1_BKINP            TIM16_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */
+#define TIM16_AF1_BKCMP1P_Pos      (10U)
+#define TIM16_AF1_BKCMP1P_Msk      (0x1UL << TIM16_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */
+#define TIM16_AF1_BKCMP1P          TIM16_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */
+#define TIM16_AF1_BKCMP2P_Pos      (11U)
+#define TIM16_AF1_BKCMP2P_Msk      (0x1UL << TIM16_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */
+#define TIM16_AF1_BKCMP2P          TIM16_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */
+
+/*******************  Bit definition for TIM17_AF1 register  *********************/
+#define TIM17_AF1_BKINE_Pos        (0U)
+#define TIM17_AF1_BKINE_Msk        (0x1UL << TIM17_AF1_BKINE_Pos)              /*!< 0x00000001 */
+#define TIM17_AF1_BKINE            TIM17_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */
+#define TIM17_AF1_BKCMP1E_Pos      (1U)
+#define TIM17_AF1_BKCMP1E_Msk      (0x1UL << TIM17_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */
+#define TIM17_AF1_BKCMP1E          TIM17_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */
+#define TIM17_AF1_BKCMP2E_Pos      (2U)
+#define TIM17_AF1_BKCMP2E_Msk      (0x1UL << TIM17_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */
+#define TIM17_AF1_BKCMP2E          TIM17_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */
+#define TIM17_AF1_BKDF1BK2E_Pos    (8U)
+#define TIM17_AF1_BKDF1BK2E_Msk    (0x1UL << TIM17_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */
+#define TIM17_AF1_BKDF1BK2E        TIM17_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[2] enable */
+#define TIM17_AF1_BKINP_Pos        (9U)
+#define TIM17_AF1_BKINP_Msk        (0x1UL << TIM17_AF1_BKINP_Pos)              /*!< 0x00000200 */
+#define TIM17_AF1_BKINP            TIM17_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */
+#define TIM17_AF1_BKCMP1P_Pos      (10U)
+#define TIM17_AF1_BKCMP1P_Msk      (0x1UL << TIM17_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */
+#define TIM17_AF1_BKCMP1P          TIM17_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */
+#define TIM17_AF1_BKCMP2P_Pos      (11U)
+#define TIM17_AF1_BKCMP2P_Msk      (0x1UL << TIM17_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */
+#define TIM17_AF1_BKCMP2P          TIM17_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Low Power Timer (LPTTIM)                           */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for LPTIM_ISR register  *******************/
+#define LPTIM_ISR_CMPM_Pos          (0U)
+#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)              /*!< 0x00000001 */
+#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
+#define LPTIM_ISR_ARRM_Pos          (1U)
+#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */
+#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG_Pos       (2U)
+#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */
+#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK_Pos         (3U)
+#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)             /*!< 0x00000008 */
+#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK_Pos         (4U)
+#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */
+#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP_Pos            (5U)
+#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */
+#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN_Pos          (6U)
+#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */
+#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
+
+/******************  Bit definition for LPTIM_ICR register  *******************/
+#define LPTIM_ICR_CMPMCF_Pos        (0U)
+#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)            /*!< 0x00000001 */
+#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF_Pos        (1U)
+#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */
+#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)
+#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */
+#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF_Pos       (3U)
+#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)           /*!< 0x00000008 */
+#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF_Pos       (4U)
+#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */
+#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF_Pos          (5U)
+#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */
+#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF_Pos        (6U)
+#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */
+#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
+
+/******************  Bit definition for LPTIM_IER register ********************/
+#define LPTIM_IER_CMPMIE_Pos        (0U)
+#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)            /*!< 0x00000001 */
+#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE_Pos        (1U)
+#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)            /*!< 0x00000002 */
+#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE_Pos     (2U)
+#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)         /*!< 0x00000004 */
+#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE_Pos       (3U)
+#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)           /*!< 0x00000008 */
+#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE_Pos       (4U)
+#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)           /*!< 0x00000010 */
+#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE_Pos          (5U)
+#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)              /*!< 0x00000020 */
+#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE_Pos        (6U)
+#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)            /*!< 0x00000040 */
+#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
+
+/******************  Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL_Pos        (0U)
+#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */
+#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL_Pos        (1U)
+#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */
+#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */
+#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */
+
+#define LPTIM_CFGR_CKFLT_Pos        (3U)
+#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */
+#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */
+#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */
+
+#define LPTIM_CFGR_TRGFLT_Pos       (6U)
+#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */
+#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */
+#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */
+
+#define LPTIM_CFGR_PRESC_Pos        (9U)
+#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */
+#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */
+#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */
+#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */
+
+#define LPTIM_CFGR_TRIGSEL_Pos      (13U)
+#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x0000E000 */
+#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */
+#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */
+#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */
+
+#define LPTIM_CFGR_TRIGEN_Pos       (17U)
+#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */
+#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */
+#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */
+
+#define LPTIM_CFGR_TIMOUT_Pos       (19U)
+#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */
+#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
+#define LPTIM_CFGR_WAVE_Pos         (20U)
+#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */
+#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL_Pos       (21U)
+#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */
+#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD_Pos      (22U)
+#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */
+#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE_Pos    (23U)
+#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */
+#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC_Pos          (24U)
+#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */
+#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
+
+/******************  Bit definition for LPTIM_CR register  ********************/
+#define LPTIM_CR_ENABLE_Pos         (0U)
+#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */
+#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT_Pos        (1U)
+#define LPTIM_CR_SNGSTRT_Msk        (0x40001UL << LPTIM_CR_SNGSTRT_Pos)        /*!< 0x00080002 */
+#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT_Pos        (2U)
+#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */
+#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
+#define LPTIM_CR_COUNTRST_Pos       (3U)
+#define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */
+#define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Timer Counter reset in synchronous mode*/
+#define LPTIM_CR_RSTARE_Pos         (4U)
+#define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */
+#define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Timer Counter reset after read enable (asynchronously)*/
+
+
+/******************  Bit definition for LPTIM_CMP register  *******************/
+#define LPTIM_CMP_CMP_Pos           (0U)
+#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)            /*!< 0x0000FFFF */
+#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
+
+/******************  Bit definition for LPTIM_ARR register  *******************/
+#define LPTIM_ARR_ARR_Pos           (0U)
+#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */
+#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
+
+/******************  Bit definition for LPTIM_CNT register  *******************/
+#define LPTIM_CNT_CNT_Pos           (0U)
+#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */
+#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
+
+/******************  Bit definition for LPTIM_CFGR2 register  *****************/
+#define LPTIM_CFGR2_IN1SEL_Pos      (0U)
+#define LPTIM_CFGR2_IN1SEL_Msk      (0x3UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000003 */
+#define LPTIM_CFGR2_IN1SEL          LPTIM_CFGR2_IN1SEL_Msk                     /*!< IN1SEL[1:0] bits (Remap selection) */
+#define LPTIM_CFGR2_IN1SEL_0        (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000001 */
+#define LPTIM_CFGR2_IN1SEL_1        (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000002 */
+#define LPTIM_CFGR2_IN2SEL_Pos      (4U)
+#define LPTIM_CFGR2_IN2SEL_Msk      (0x3UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000030 */
+#define LPTIM_CFGR2_IN2SEL          LPTIM_CFGR2_IN2SEL_Msk                     /*!< IN2SEL[5:4] bits (Remap selection) */
+#define LPTIM_CFGR2_IN2SEL_0        (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000010 */
+#define LPTIM_CFGR2_IN2SEL_1        (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000020 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Analog Comparators (COMP)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for COMP_SR register  ********************/
+#define COMP_SR_C1VAL_Pos            (0U)
+#define COMP_SR_C1VAL_Msk            (0x1UL << COMP_SR_C1VAL_Pos)              /*!< 0x00000001 */
+#define COMP_SR_C1VAL                COMP_SR_C1VAL_Msk
+#define COMP_SR_C2VAL_Pos            (1U)
+#define COMP_SR_C2VAL_Msk            (0x1UL << COMP_SR_C2VAL_Pos)              /*!< 0x00000002 */
+#define COMP_SR_C2VAL                COMP_SR_C2VAL_Msk
+#define COMP_SR_C1IF_Pos             (16U)
+#define COMP_SR_C1IF_Msk             (0x1UL << COMP_SR_C1IF_Pos)               /*!< 0x00010000 */
+#define COMP_SR_C1IF                 COMP_SR_C1IF_Msk
+#define COMP_SR_C2IF_Pos             (17U)
+#define COMP_SR_C2IF_Msk             (0x1UL << COMP_SR_C2IF_Pos)               /*!< 0x00020000 */
+#define COMP_SR_C2IF                 COMP_SR_C2IF_Msk
+/*******************  Bit definition for COMP_ICFR register  ********************/
+#define COMP_ICFR_C1IF_Pos           (16U)
+#define COMP_ICFR_C1IF_Msk           (0x1UL << COMP_ICFR_C1IF_Pos)             /*!< 0x00010000 */
+#define COMP_ICFR_C1IF               COMP_ICFR_C1IF_Msk
+#define COMP_ICFR_C2IF_Pos           (17U)
+#define COMP_ICFR_C2IF_Msk           (0x1UL << COMP_ICFR_C2IF_Pos)             /*!< 0x00020000 */
+#define COMP_ICFR_C2IF               COMP_ICFR_C2IF_Msk
+/*******************  Bit definition for COMP_OR register  ********************/
+#define COMP_OR_AFOPA6_Pos           (0U)
+#define COMP_OR_AFOPA6_Msk           (0x1UL << COMP_OR_AFOPA6_Pos)             /*!< 0x00000001 */
+#define COMP_OR_AFOPA6               COMP_OR_AFOPA6_Msk
+#define COMP_OR_AFOPA8_Pos           (1U)
+#define COMP_OR_AFOPA8_Msk           (0x1UL << COMP_OR_AFOPA8_Pos)             /*!< 0x00000002 */
+#define COMP_OR_AFOPA8               COMP_OR_AFOPA8_Msk
+#define COMP_OR_AFOPB12_Pos          (2U)
+#define COMP_OR_AFOPB12_Msk          (0x1UL << COMP_OR_AFOPB12_Pos)            /*!< 0x00000004 */
+#define COMP_OR_AFOPB12              COMP_OR_AFOPB12_Msk
+#define COMP_OR_AFOPE6_Pos           (3U)
+#define COMP_OR_AFOPE6_Msk           (0x1UL << COMP_OR_AFOPE6_Pos)             /*!< 0x00000008 */
+#define COMP_OR_AFOPE6               COMP_OR_AFOPE6_Msk
+#define COMP_OR_AFOPE15_Pos          (4U)
+#define COMP_OR_AFOPE15_Msk          (0x1UL << COMP_OR_AFOPE15_Pos)            /*!< 0x00000010 */
+#define COMP_OR_AFOPE15              COMP_OR_AFOPE15_Msk
+#define COMP_OR_AFOPG2_Pos           (5U)
+#define COMP_OR_AFOPG2_Msk           (0x1UL << COMP_OR_AFOPG2_Pos)             /*!< 0x00000020 */
+#define COMP_OR_AFOPG2               COMP_OR_AFOPG2_Msk
+#define COMP_OR_AFOPG3_Pos           (6U)
+#define COMP_OR_AFOPG3_Msk           (0x1UL << COMP_OR_AFOPG3_Pos)             /*!< 0x00000040 */
+#define COMP_OR_AFOPG3               COMP_OR_AFOPG3_Msk
+#define COMP_OR_AFOPG4_Pos           (7U)
+#define COMP_OR_AFOPG4_Msk           (0x1UL << COMP_OR_AFOPG4_Pos)             /*!< 0x00000080 */
+#define COMP_OR_AFOPG4               COMP_OR_AFOPG4_Msk
+#define COMP_OR_AFOPI1_Pos           (8U)
+#define COMP_OR_AFOPI1_Msk           (0x1UL << COMP_OR_AFOPI1_Pos)             /*!< 0x00000100 */
+#define COMP_OR_AFOPI1               COMP_OR_AFOPI1_Msk
+#define COMP_OR_AFOPI4_Pos           (9U)
+#define COMP_OR_AFOPI4_Msk           (0x1UL << COMP_OR_AFOPI4_Pos)             /*!< 0x00000200 */
+#define COMP_OR_AFOPI4               COMP_OR_AFOPI4_Msk
+#define COMP_OR_AFOPK2_Pos           (10U)
+#define COMP_OR_AFOPK2_Msk           (0x1UL << COMP_OR_AFOPK2_Pos)             /*!< 0x00000400 */
+#define COMP_OR_AFOPK2               COMP_OR_AFOPK2_Msk
+
+/*!< ******************  Bit definition for COMP_CFGRx register  ********************/
+#define COMP_CFGRx_EN_Pos            (0U)
+#define COMP_CFGRx_EN_Msk            (0x1UL << COMP_CFGRx_EN_Pos)              /*!< 0x00000001 */
+#define COMP_CFGRx_EN                COMP_CFGRx_EN_Msk                         /*!< COMPx enable bit                     */
+#define COMP_CFGRx_BRGEN_Pos         (1U)
+#define COMP_CFGRx_BRGEN_Msk         (0x1UL << COMP_CFGRx_BRGEN_Pos)           /*!< 0x00000002 */
+#define COMP_CFGRx_BRGEN             COMP_CFGRx_BRGEN_Msk                      /*!< COMPx Scaler bridge enable           */
+#define COMP_CFGRx_SCALEN_Pos        (2U)
+#define COMP_CFGRx_SCALEN_Msk        (0x1UL << COMP_CFGRx_SCALEN_Pos)          /*!< 0x00000004 */
+#define COMP_CFGRx_SCALEN            COMP_CFGRx_SCALEN_Msk                     /*!< COMPx Voltage scaler enable bit      */
+#define COMP_CFGRx_POLARITY_Pos      (3U)
+#define COMP_CFGRx_POLARITY_Msk      (0x1UL << COMP_CFGRx_POLARITY_Pos)        /*!< 0x00000008 */
+#define COMP_CFGRx_POLARITY          COMP_CFGRx_POLARITY_Msk                   /*!< COMPx  polarity selection bit        */
+#define COMP_CFGRx_WINMODE_Pos       (4U)
+#define COMP_CFGRx_WINMODE_Msk       (0x1UL << COMP_CFGRx_WINMODE_Pos)         /*!< 0x00000010 */
+#define COMP_CFGRx_WINMODE           COMP_CFGRx_WINMODE_Msk                    /*!< COMPx Windows mode selection bit     */
+#define COMP_CFGRx_ITEN_Pos          (6U)
+#define COMP_CFGRx_ITEN_Msk          (0x1UL << COMP_CFGRx_ITEN_Pos)            /*!< 0x00000040 */
+#define COMP_CFGRx_ITEN              COMP_CFGRx_ITEN_Msk                       /*!< COMPx  interrupt enable              */
+#define COMP_CFGRx_HYST_Pos          (8U)
+#define COMP_CFGRx_HYST_Msk          (0x3UL << COMP_CFGRx_HYST_Pos)            /*!< 0x00000300 */
+#define COMP_CFGRx_HYST              COMP_CFGRx_HYST_Msk                       /*!< COMPx  hysteresis selection bits     */
+#define COMP_CFGRx_HYST_0            (0x1UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000100 */
+#define COMP_CFGRx_HYST_1            (0x2UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000200 */
+#define COMP_CFGRx_PWRMODE_Pos       (12U)
+#define COMP_CFGRx_PWRMODE_Msk       (0x3UL << COMP_CFGRx_PWRMODE_Pos)         /*!< 0x00003000 */
+#define COMP_CFGRx_PWRMODE           COMP_CFGRx_PWRMODE_Msk                    /*!< COMPx Power Mode of the comparator   */
+#define COMP_CFGRx_PWRMODE_0         (0x1UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00001000 */
+#define COMP_CFGRx_PWRMODE_1         (0x2UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00002000 */
+#define COMP_CFGRx_INMSEL_Pos        (16U)
+#define COMP_CFGRx_INMSEL_Msk        (0x7UL << COMP_CFGRx_INMSEL_Pos)          /*!< 0x00070000 */
+#define COMP_CFGRx_INMSEL            COMP_CFGRx_INMSEL_Msk                     /*!< COMPx  input minus selection bit  */
+#define COMP_CFGRx_INMSEL_0          (0x1UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00010000 */
+#define COMP_CFGRx_INMSEL_1          (0x2UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00020000 */
+#define COMP_CFGRx_INMSEL_2          (0x4UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00040000 */
+#define COMP_CFGRx_INPSEL_Pos        (20U)
+#define COMP_CFGRx_INPSEL_Msk        (0x1UL << COMP_CFGRx_INPSEL_Pos)          /*!< 0x00100000 */
+#define COMP_CFGRx_INPSEL            COMP_CFGRx_INPSEL_Msk                     /*!< COMPx  input plus selection bit       */
+#define COMP_CFGRx_BLANKING_Pos      (24U)
+#define COMP_CFGRx_BLANKING_Msk      (0xFUL << COMP_CFGRx_BLANKING_Pos)        /*!< 0x0F000000 */
+#define COMP_CFGRx_BLANKING          COMP_CFGRx_BLANKING_Msk                   /*!< COMPx  blanking source selection bits */
+#define COMP_CFGRx_BLANKING_0        (0x1UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x01000000 */
+#define COMP_CFGRx_BLANKING_1        (0x2UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x02000000 */
+#define COMP_CFGRx_BLANKING_2        (0x4UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x04000000 */
+#define COMP_CFGRx_LOCK_Pos          (31U)
+#define COMP_CFGRx_LOCK_Msk          (0x1UL << COMP_CFGRx_LOCK_Pos)            /*!< 0x80000000 */
+#define COMP_CFGRx_LOCK              COMP_CFGRx_LOCK_Msk                       /*!< COMPx Lock Bit                        */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for USART_CR1 register  *******************/
+#define USART_CR1_UE_Pos                (0U)
+#define USART_CR1_UE_Msk                (0x1UL << USART_CR1_UE_Pos)            /*!< 0x00000001 */
+#define USART_CR1_UE                    USART_CR1_UE_Msk                       /*!< USART Enable */
+#define USART_CR1_UESM_Pos              (1U)
+#define USART_CR1_UESM_Msk              (0x1UL << USART_CR1_UESM_Pos)          /*!< 0x00000002 */
+#define USART_CR1_UESM                  USART_CR1_UESM_Msk                     /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE_Pos                (2U)
+#define USART_CR1_RE_Msk                (0x1UL << USART_CR1_RE_Pos)            /*!< 0x00000004 */
+#define USART_CR1_RE                    USART_CR1_RE_Msk                       /*!< Receiver Enable */
+#define USART_CR1_TE_Pos                (3U)
+#define USART_CR1_TE_Msk                (0x1UL << USART_CR1_TE_Pos)            /*!< 0x00000008 */
+#define USART_CR1_TE                    USART_CR1_TE_Msk                       /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos            (4U)
+#define USART_CR1_IDLEIE_Msk            (0x1UL << USART_CR1_IDLEIE_Pos)        /*!< 0x00000010 */
+#define USART_CR1_IDLEIE                USART_CR1_IDLEIE_Msk                   /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_RXFNEIE_Pos    (5U)
+#define USART_CR1_RXNEIE_RXFNEIE_Msk    (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE_RXFNEIE        USART_CR1_RXNEIE_RXFNEIE_Msk           /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
+#define USART_CR1_TCIE_Pos              (6U)
+#define USART_CR1_TCIE_Msk              (0x1UL << USART_CR1_TCIE_Pos)          /*!< 0x00000040 */
+#define USART_CR1_TCIE                  USART_CR1_TCIE_Msk                     /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_TXFNFIE_Pos     (7U)
+#define USART_CR1_TXEIE_TXFNFIE_Msk     (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE_TXFNFIE         USART_CR1_TXEIE_TXFNFIE_Msk            /*!< TXE and TX FIFO Not Full Interrupt Enable */
+#define USART_CR1_PEIE_Pos              (8U)
+#define USART_CR1_PEIE_Msk              (0x1UL << USART_CR1_PEIE_Pos)          /*!< 0x00000100 */
+#define USART_CR1_PEIE                  USART_CR1_PEIE_Msk                     /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos                (9U)
+#define USART_CR1_PS_Msk                (0x1UL << USART_CR1_PS_Pos)            /*!< 0x00000200 */
+#define USART_CR1_PS                    USART_CR1_PS_Msk                       /*!< Parity Selection */
+#define USART_CR1_PCE_Pos               (10U)
+#define USART_CR1_PCE_Msk               (0x1UL << USART_CR1_PCE_Pos)           /*!< 0x00000400 */
+#define USART_CR1_PCE                   USART_CR1_PCE_Msk                      /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos              (11U)
+#define USART_CR1_WAKE_Msk              (0x1UL << USART_CR1_WAKE_Pos)          /*!< 0x00000800 */
+#define USART_CR1_WAKE                  USART_CR1_WAKE_Msk                     /*!< Receiver Wakeup method */
+#define USART_CR1_M_Pos                 (12U)
+#define USART_CR1_M_Msk                 (0x10001UL << USART_CR1_M_Pos)         /*!< 0x10001000 */
+#define USART_CR1_M                     USART_CR1_M_Msk                        /*!< Word length */
+#define USART_CR1_M0_Pos                (12U)
+#define USART_CR1_M0_Msk                (0x1UL << USART_CR1_M0_Pos)            /*!< 0x00001000 */
+#define USART_CR1_M0                    USART_CR1_M0_Msk                       /*!< Word length - Bit 0 */
+#define USART_CR1_MME_Pos               (13U)
+#define USART_CR1_MME_Msk               (0x1UL << USART_CR1_MME_Pos)           /*!< 0x00002000 */
+#define USART_CR1_MME                   USART_CR1_MME_Msk                      /*!< Mute Mode Enable */
+#define USART_CR1_CMIE_Pos              (14U)
+#define USART_CR1_CMIE_Msk              (0x1UL << USART_CR1_CMIE_Pos)          /*!< 0x00004000 */
+#define USART_CR1_CMIE                  USART_CR1_CMIE_Msk                     /*!< Character match interrupt enable */
+#define USART_CR1_OVER8_Pos             (15U)
+#define USART_CR1_OVER8_Msk             (0x1UL << USART_CR1_OVER8_Pos)         /*!< 0x00008000 */
+#define USART_CR1_OVER8                 USART_CR1_OVER8_Msk                    /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT_Pos              (16U)
+#define USART_CR1_DEDT_Msk              (0x1FUL << USART_CR1_DEDT_Pos)         /*!< 0x001F0000 */
+#define USART_CR1_DEDT                  USART_CR1_DEDT_Msk                     /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0                (0x01UL << USART_CR1_DEDT_Pos)          /*!< 0x00010000 */
+#define USART_CR1_DEDT_1                (0x02UL << USART_CR1_DEDT_Pos)          /*!< 0x00020000 */
+#define USART_CR1_DEDT_2                (0x04UL << USART_CR1_DEDT_Pos)          /*!< 0x00040000 */
+#define USART_CR1_DEDT_3                (0x08UL << USART_CR1_DEDT_Pos)          /*!< 0x00080000 */
+#define USART_CR1_DEDT_4                (0x10UL << USART_CR1_DEDT_Pos)          /*!< 0x00100000 */
+#define USART_CR1_DEAT_Pos              (21U)
+#define USART_CR1_DEAT_Msk              (0x1FUL << USART_CR1_DEAT_Pos)         /*!< 0x03E00000 */
+#define USART_CR1_DEAT                  USART_CR1_DEAT_Msk                     /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0                (0x01UL << USART_CR1_DEAT_Pos)          /*!< 0x00200000 */
+#define USART_CR1_DEAT_1                (0x02UL << USART_CR1_DEAT_Pos)          /*!< 0x00400000 */
+#define USART_CR1_DEAT_2                (0x04UL << USART_CR1_DEAT_Pos)          /*!< 0x00800000 */
+#define USART_CR1_DEAT_3                (0x08UL << USART_CR1_DEAT_Pos)          /*!< 0x01000000 */
+#define USART_CR1_DEAT_4                (0x10UL << USART_CR1_DEAT_Pos)          /*!< 0x02000000 */
+#define USART_CR1_RTOIE_Pos             (26U)
+#define USART_CR1_RTOIE_Msk             (0x1UL << USART_CR1_RTOIE_Pos)         /*!< 0x04000000 */
+#define USART_CR1_RTOIE                 USART_CR1_RTOIE_Msk                    /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE_Pos             (27U)
+#define USART_CR1_EOBIE_Msk             (0x1UL << USART_CR1_EOBIE_Pos)         /*!< 0x08000000 */
+#define USART_CR1_EOBIE                 USART_CR1_EOBIE_Msk                    /*!< End of Block interrupt enable */
+#define USART_CR1_M1_Pos                (28U)
+#define USART_CR1_M1_Msk                (0x1UL << USART_CR1_M1_Pos)            /*!< 0x10000000 */
+#define USART_CR1_M1                    USART_CR1_M1_Msk                       /*!< Word length - Bit 1 */
+#define USART_CR1_FIFOEN_Pos            (29U)
+#define USART_CR1_FIFOEN_Msk            (0x1UL << USART_CR1_FIFOEN_Pos)        /*!< 0x20000000 */
+#define USART_CR1_FIFOEN                USART_CR1_FIFOEN_Msk                   /*!< FIFO mode enable */
+#define USART_CR1_TXFEIE_Pos            (30U)
+#define USART_CR1_TXFEIE_Msk            (0x1UL << USART_CR1_TXFEIE_Pos)        /*!< 0x40000000 */
+#define USART_CR1_TXFEIE                USART_CR1_TXFEIE_Msk                   /*!< TXFIFO empty interrupt enable */
+#define USART_CR1_RXFFIE_Pos            (31U)
+#define USART_CR1_RXFFIE_Msk            (0x1UL << USART_CR1_RXFFIE_Pos)        /*!< 0x80000000 */
+#define USART_CR1_RXFFIE                USART_CR1_RXFFIE_Msk                   /*!< RXFIFO Full interrupt enable */
+
+/* Legacy define */
+#define  USART_CR1_RXNEIE  USART_CR1_RXNEIE_RXFNEIE
+#define  USART_CR1_TXEIE   USART_CR1_TXEIE_TXFNFIE
+
+/******************  Bit definition for USART_CR2 register  *******************/
+#define USART_CR2_SLVEN_Pos             (0U)
+#define USART_CR2_SLVEN_Msk             (0x1UL << USART_CR2_SLVEN_Pos)         /*!< 0x00000001 */
+#define USART_CR2_SLVEN                 USART_CR2_SLVEN_Msk                    /*!< Synchronous Slave mode Enable */
+#define USART_CR2_DIS_NSS_Pos           (3U)
+#define USART_CR2_DIS_NSS_Msk           (0x1UL << USART_CR2_DIS_NSS_Pos)       /*!< 0x00000008 */
+#define USART_CR2_DIS_NSS               USART_CR2_DIS_NSS_Msk                  /*!< Negative Slave Select (NSS) pin management */
+#define USART_CR2_ADDM7_Pos             (4U)
+#define USART_CR2_ADDM7_Msk             (0x1UL << USART_CR2_ADDM7_Pos)         /*!< 0x00000010 */
+#define USART_CR2_ADDM7                 USART_CR2_ADDM7_Msk                    /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL_Pos              (5U)
+#define USART_CR2_LBDL_Msk              (0x1UL << USART_CR2_LBDL_Pos)          /*!< 0x00000020 */
+#define USART_CR2_LBDL                  USART_CR2_LBDL_Msk                     /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos             (6U)
+#define USART_CR2_LBDIE_Msk             (0x1UL << USART_CR2_LBDIE_Pos)         /*!< 0x00000040 */
+#define USART_CR2_LBDIE                 USART_CR2_LBDIE_Msk                    /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos              (8U)
+#define USART_CR2_LBCL_Msk              (0x1UL << USART_CR2_LBCL_Pos)          /*!< 0x00000100 */
+#define USART_CR2_LBCL                  USART_CR2_LBCL_Msk                     /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos              (9U)
+#define USART_CR2_CPHA_Msk              (0x1UL << USART_CR2_CPHA_Pos)          /*!< 0x00000200 */
+#define USART_CR2_CPHA                  USART_CR2_CPHA_Msk                     /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos              (10U)
+#define USART_CR2_CPOL_Msk              (0x1UL << USART_CR2_CPOL_Pos)          /*!< 0x00000400 */
+#define USART_CR2_CPOL                  USART_CR2_CPOL_Msk                     /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos             (11U)
+#define USART_CR2_CLKEN_Msk             (0x1UL << USART_CR2_CLKEN_Pos)         /*!< 0x00000800 */
+#define USART_CR2_CLKEN                 USART_CR2_CLKEN_Msk                    /*!< Clock Enable */
+#define USART_CR2_STOP_Pos              (12U)
+#define USART_CR2_STOP_Msk              (0x3UL << USART_CR2_STOP_Pos)          /*!< 0x00003000 */
+#define USART_CR2_STOP                  USART_CR2_STOP_Msk                     /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0                (0x1UL << USART_CR2_STOP_Pos)           /*!< 0x00001000 */
+#define USART_CR2_STOP_1                (0x2UL << USART_CR2_STOP_Pos)           /*!< 0x00002000 */
+#define USART_CR2_LINEN_Pos             (14U)
+#define USART_CR2_LINEN_Msk             (0x1UL << USART_CR2_LINEN_Pos)         /*!< 0x00004000 */
+#define USART_CR2_LINEN                 USART_CR2_LINEN_Msk                    /*!< LIN mode enable */
+#define USART_CR2_SWAP_Pos              (15U)
+#define USART_CR2_SWAP_Msk              (0x1UL << USART_CR2_SWAP_Pos)          /*!< 0x00008000 */
+#define USART_CR2_SWAP                  USART_CR2_SWAP_Msk                     /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV_Pos             (16U)
+#define USART_CR2_RXINV_Msk             (0x1UL << USART_CR2_RXINV_Pos)         /*!< 0x00010000 */
+#define USART_CR2_RXINV                 USART_CR2_RXINV_Msk                    /*!< RX pin active level inversion */
+#define USART_CR2_TXINV_Pos             (17U)
+#define USART_CR2_TXINV_Msk             (0x1UL << USART_CR2_TXINV_Pos)         /*!< 0x00020000 */
+#define USART_CR2_TXINV                 USART_CR2_TXINV_Msk                    /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV_Pos           (18U)
+#define USART_CR2_DATAINV_Msk           (0x1UL << USART_CR2_DATAINV_Pos)       /*!< 0x00040000 */
+#define USART_CR2_DATAINV               USART_CR2_DATAINV_Msk                  /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST_Pos          (19U)
+#define USART_CR2_MSBFIRST_Msk          (0x1UL << USART_CR2_MSBFIRST_Pos)      /*!< 0x00080000 */
+#define USART_CR2_MSBFIRST              USART_CR2_MSBFIRST_Msk                 /*!< Most Significant Bit First */
+#define USART_CR2_ABREN_Pos             (20U)
+#define USART_CR2_ABREN_Msk             (0x1UL << USART_CR2_ABREN_Pos)         /*!< 0x00100000 */
+#define USART_CR2_ABREN                 USART_CR2_ABREN_Msk                    /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE_Pos           (21U)
+#define USART_CR2_ABRMODE_Msk           (0x3UL << USART_CR2_ABRMODE_Pos)       /*!< 0x00600000 */
+#define USART_CR2_ABRMODE               USART_CR2_ABRMODE_Msk                  /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0             (0x1UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00200000 */
+#define USART_CR2_ABRMODE_1             (0x2UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00400000 */
+#define USART_CR2_RTOEN_Pos             (23U)
+#define USART_CR2_RTOEN_Msk             (0x1UL << USART_CR2_RTOEN_Pos)         /*!< 0x00800000 */
+#define USART_CR2_RTOEN                 USART_CR2_RTOEN_Msk                    /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD_Pos               (24U)
+#define USART_CR2_ADD_Msk               (0xFFUL << USART_CR2_ADD_Pos)          /*!< 0xFF000000 */
+#define USART_CR2_ADD                   USART_CR2_ADD_Msk                      /*!< Address of the USART node */
+
+/******************  Bit definition for USART_CR3 register  *******************/
+#define USART_CR3_EIE_Pos               (0U)
+#define USART_CR3_EIE_Msk               (0x1UL << USART_CR3_EIE_Pos)           /*!< 0x00000001 */
+#define USART_CR3_EIE                   USART_CR3_EIE_Msk                      /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos              (1U)
+#define USART_CR3_IREN_Msk              (0x1UL << USART_CR3_IREN_Pos)          /*!< 0x00000002 */
+#define USART_CR3_IREN                  USART_CR3_IREN_Msk                     /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos              (2U)
+#define USART_CR3_IRLP_Msk              (0x1UL << USART_CR3_IRLP_Pos)          /*!< 0x00000004 */
+#define USART_CR3_IRLP                  USART_CR3_IRLP_Msk                     /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos             (3U)
+#define USART_CR3_HDSEL_Msk             (0x1UL << USART_CR3_HDSEL_Pos)         /*!< 0x00000008 */
+#define USART_CR3_HDSEL                 USART_CR3_HDSEL_Msk                    /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos              (4U)
+#define USART_CR3_NACK_Msk              (0x1UL << USART_CR3_NACK_Pos)          /*!< 0x00000010 */
+#define USART_CR3_NACK                  USART_CR3_NACK_Msk                     /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN_Pos              (5U)
+#define USART_CR3_SCEN_Msk              (0x1UL << USART_CR3_SCEN_Pos)          /*!< 0x00000020 */
+#define USART_CR3_SCEN                  USART_CR3_SCEN_Msk                     /*!< SmartCard mode enable */
+#define USART_CR3_DMAR_Pos              (6U)
+#define USART_CR3_DMAR_Msk              (0x1UL << USART_CR3_DMAR_Pos)          /*!< 0x00000040 */
+#define USART_CR3_DMAR                  USART_CR3_DMAR_Msk                     /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos              (7U)
+#define USART_CR3_DMAT_Msk              (0x1UL << USART_CR3_DMAT_Pos)          /*!< 0x00000080 */
+#define USART_CR3_DMAT                  USART_CR3_DMAT_Msk                     /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos              (8U)
+#define USART_CR3_RTSE_Msk              (0x1UL << USART_CR3_RTSE_Pos)          /*!< 0x00000100 */
+#define USART_CR3_RTSE                  USART_CR3_RTSE_Msk                     /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos              (9U)
+#define USART_CR3_CTSE_Msk              (0x1UL << USART_CR3_CTSE_Pos)          /*!< 0x00000200 */
+#define USART_CR3_CTSE                  USART_CR3_CTSE_Msk                     /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos             (10U)
+#define USART_CR3_CTSIE_Msk             (0x1UL << USART_CR3_CTSIE_Pos)         /*!< 0x00000400 */
+#define USART_CR3_CTSIE                 USART_CR3_CTSIE_Msk                    /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos            (11U)
+#define USART_CR3_ONEBIT_Msk            (0x1UL << USART_CR3_ONEBIT_Pos)        /*!< 0x00000800 */
+#define USART_CR3_ONEBIT                USART_CR3_ONEBIT_Msk                   /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS_Pos            (12U)
+#define USART_CR3_OVRDIS_Msk            (0x1UL << USART_CR3_OVRDIS_Pos)        /*!< 0x00001000 */
+#define USART_CR3_OVRDIS                USART_CR3_OVRDIS_Msk                   /*!< Overrun Disable */
+#define USART_CR3_DDRE_Pos              (13U)
+#define USART_CR3_DDRE_Msk              (0x1UL << USART_CR3_DDRE_Pos)          /*!< 0x00002000 */
+#define USART_CR3_DDRE                  USART_CR3_DDRE_Msk                     /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM_Pos               (14U)
+#define USART_CR3_DEM_Msk               (0x1UL << USART_CR3_DEM_Pos)           /*!< 0x00004000 */
+#define USART_CR3_DEM                   USART_CR3_DEM_Msk                      /*!< Driver Enable Mode */
+#define USART_CR3_DEP_Pos               (15U)
+#define USART_CR3_DEP_Msk               (0x1UL << USART_CR3_DEP_Pos)           /*!< 0x00008000 */
+#define USART_CR3_DEP                   USART_CR3_DEP_Msk                      /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT_Pos           (17U)
+#define USART_CR3_SCARCNT_Msk           (0x7UL << USART_CR3_SCARCNT_Pos)       /*!< 0x000E0000 */
+#define USART_CR3_SCARCNT               USART_CR3_SCARCNT_Msk                  /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0             (0x1UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00020000 */
+#define USART_CR3_SCARCNT_1             (0x2UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00040000 */
+#define USART_CR3_SCARCNT_2             (0x4UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00080000 */
+#define USART_CR3_WUS_Pos               (20U)
+#define USART_CR3_WUS_Msk               (0x3UL << USART_CR3_WUS_Pos)           /*!< 0x00300000 */
+#define USART_CR3_WUS                   USART_CR3_WUS_Msk                      /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0                 (0x1UL << USART_CR3_WUS_Pos)            /*!< 0x00100000 */
+#define USART_CR3_WUS_1                 (0x2UL << USART_CR3_WUS_Pos)            /*!< 0x00200000 */
+#define USART_CR3_WUFIE_Pos             (22U)
+#define USART_CR3_WUFIE_Msk             (0x1UL << USART_CR3_WUFIE_Pos)         /*!< 0x00400000 */
+#define USART_CR3_WUFIE                 USART_CR3_WUFIE_Msk                    /*!< Wake Up Interrupt Enable */
+#define USART_CR3_TXFTIE_Pos            (23U)
+#define USART_CR3_TXFTIE_Msk            (0x1UL << USART_CR3_TXFTIE_Pos)        /*!< 0x00800000 */
+#define USART_CR3_TXFTIE                USART_CR3_TXFTIE_Msk                   /*!< TXFIFO threshold interrupt enable */
+#define USART_CR3_TCBGTIE_Pos           (24U)
+#define USART_CR3_TCBGTIE_Msk           (0x1UL << USART_CR3_TCBGTIE_Pos)       /*!< 0x01000000 */
+#define USART_CR3_TCBGTIE               USART_CR3_TCBGTIE_Msk                  /*!< Transmission Complete before guard time, interrupt enable */
+#define USART_CR3_RXFTCFG_Pos           (25U)
+#define USART_CR3_RXFTCFG_Msk           (0x7UL << USART_CR3_RXFTCFG_Pos)       /*!< 0x0E000000 */
+#define USART_CR3_RXFTCFG               USART_CR3_RXFTCFG_Msk                  /*!< RXFTCFG [2:0]Receive FIFO threshold configuration */
+#define USART_CR3_RXFTCFG_0             (0x1UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x02000000 */
+#define USART_CR3_RXFTCFG_1             (0x2UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x04000000 */
+#define USART_CR3_RXFTCFG_2             (0x4UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x08000000 */
+#define USART_CR3_RXFTIE_Pos            (28U)
+#define USART_CR3_RXFTIE_Msk            (0x1UL << USART_CR3_RXFTIE_Pos)        /*!< 0x10000000 */
+#define USART_CR3_RXFTIE                USART_CR3_RXFTIE_Msk                   /*!< RXFIFO threshold interrupt enable */
+#define USART_CR3_TXFTCFG_Pos           (29U)
+#define USART_CR3_TXFTCFG_Msk           (0x7UL << USART_CR3_TXFTCFG_Pos)       /*!< 0xE0000000 */
+#define USART_CR3_TXFTCFG               USART_CR3_TXFTCFG_Msk                  /*!< TXFIFO [2:0] threshold configuration */
+#define USART_CR3_TXFTCFG_0             (0x1UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x20000000 */
+#define USART_CR3_TXFTCFG_1             (0x2UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x40000000 */
+#define USART_CR3_TXFTCFG_2             (0x4UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x80000000 */
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define USART_BRR_DIV_FRACTION_Pos      (0U)
+#define USART_BRR_DIV_FRACTION_Msk      (0xFUL << USART_BRR_DIV_FRACTION_Pos)  /*!< 0x0000000F */
+#define USART_BRR_DIV_FRACTION          USART_BRR_DIV_FRACTION_Msk             /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA_Pos      (4U)
+#define USART_BRR_DIV_MANTISSA_Msk      (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_MANTISSA          USART_BRR_DIV_MANTISSA_Msk             /*!< Mantissa of USARTDIV */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define USART_GTPR_PSC_Pos              (0U)
+#define USART_GTPR_PSC_Msk              (0xFFUL << USART_GTPR_PSC_Pos)         /*!< 0x000000FF */
+#define USART_GTPR_PSC                  USART_GTPR_PSC_Msk                     /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT_Pos               (8U)
+#define USART_GTPR_GT_Msk               (0xFFUL << USART_GTPR_GT_Pos)          /*!< 0x0000FF00 */
+#define USART_GTPR_GT                   USART_GTPR_GT_Msk                      /*!< GT[7:0] bits (Guard time value) */
+
+/*******************  Bit definition for USART_RTOR register  *****************/
+#define USART_RTOR_RTO_Pos              (0U)
+#define USART_RTOR_RTO_Msk              (0xFFFFFFUL << USART_RTOR_RTO_Pos)     /*!< 0x00FFFFFF */
+#define USART_RTOR_RTO                  USART_RTOR_RTO_Msk                     /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN_Pos             (24U)
+#define USART_RTOR_BLEN_Msk             (0xFFUL << USART_RTOR_BLEN_Pos)        /*!< 0xFF000000 */
+#define USART_RTOR_BLEN                 USART_RTOR_BLEN_Msk                    /*!< Block Length */
+
+/*******************  Bit definition for USART_RQR register  ******************/
+#define USART_RQR_ABRRQ_Pos             (0U)
+#define USART_RQR_ABRRQ_Msk             (0x1UL << USART_RQR_ABRRQ_Pos)         /*!< 0x00000001 */
+#define USART_RQR_ABRRQ                 USART_RQR_ABRRQ_Msk                    /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ_Pos             (1U)
+#define USART_RQR_SBKRQ_Msk             (0x1UL << USART_RQR_SBKRQ_Pos)         /*!< 0x00000002 */
+#define USART_RQR_SBKRQ                 USART_RQR_SBKRQ_Msk                    /*!< Send Break Request */
+#define USART_RQR_MMRQ_Pos              (2U)
+#define USART_RQR_MMRQ_Msk              (0x1UL << USART_RQR_MMRQ_Pos)          /*!< 0x00000004 */
+#define USART_RQR_MMRQ                  USART_RQR_MMRQ_Msk                     /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ_Pos             (3U)
+#define USART_RQR_RXFRQ_Msk             (0x1UL << USART_RQR_RXFRQ_Pos)         /*!< 0x00000008 */
+#define USART_RQR_RXFRQ                 USART_RQR_RXFRQ_Msk                    /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ_Pos             (4U)
+#define USART_RQR_TXFRQ_Msk             (0x1UL << USART_RQR_TXFRQ_Pos)         /*!< 0x00000010 */
+#define USART_RQR_TXFRQ                 USART_RQR_TXFRQ_Msk                    /*!< Transmit data flush Request */
+
+/*******************  Bit definition for USART_ISR register  ******************/
+#define USART_ISR_PE_Pos                (0U)
+#define USART_ISR_PE_Msk                (0x1UL << USART_ISR_PE_Pos)            /*!< 0x00000001 */
+#define USART_ISR_PE                    USART_ISR_PE_Msk                       /*!< Parity Error */
+#define USART_ISR_FE_Pos                (1U)
+#define USART_ISR_FE_Msk                (0x1UL << USART_ISR_FE_Pos)            /*!< 0x00000002 */
+#define USART_ISR_FE                    USART_ISR_FE_Msk                       /*!< Framing Error */
+#define USART_ISR_NE_Pos                (2U)
+#define USART_ISR_NE_Msk                (0x1UL << USART_ISR_NE_Pos)            /*!< 0x00000004 */
+#define USART_ISR_NE                    USART_ISR_NE_Msk                       /*!< Noise detected Flag */
+#define USART_ISR_ORE_Pos               (3U)
+#define USART_ISR_ORE_Msk               (0x1UL << USART_ISR_ORE_Pos)           /*!< 0x00000008 */
+#define USART_ISR_ORE                   USART_ISR_ORE_Msk                      /*!< OverRun Error */
+#define USART_ISR_IDLE_Pos              (4U)
+#define USART_ISR_IDLE_Msk              (0x1UL << USART_ISR_IDLE_Pos)          /*!< 0x00000010 */
+#define USART_ISR_IDLE                  USART_ISR_IDLE_Msk                     /*!< IDLE line detected */
+#define USART_ISR_RXNE_RXFNE_Pos        (5U)
+#define USART_ISR_RXNE_RXFNE_Msk        (0x1UL << USART_ISR_RXNE_RXFNE_Pos)    /*!< 0x00000020 */
+#define USART_ISR_RXNE_RXFNE            USART_ISR_RXNE_RXFNE_Msk               /*!< Read Data Register or RX FIFO Not Empty */
+#define USART_ISR_TC_Pos                (6U)
+#define USART_ISR_TC_Msk                (0x1UL << USART_ISR_TC_Pos)            /*!< 0x00000040 */
+#define USART_ISR_TC                    USART_ISR_TC_Msk                       /*!< Transmission Complete */
+#define USART_ISR_TXE_TXFNF_Pos         (7U)
+#define USART_ISR_TXE_TXFNF_Msk         (0x1UL << USART_ISR_TXE_TXFNF_Pos)     /*!< 0x00000080 */
+#define USART_ISR_TXE_TXFNF             USART_ISR_TXE_TXFNF_Msk                /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
+#define USART_ISR_LBDF_Pos              (8U)
+#define USART_ISR_LBDF_Msk              (0x1UL << USART_ISR_LBDF_Pos)          /*!< 0x00000100 */
+#define USART_ISR_LBDF                  USART_ISR_LBDF_Msk                     /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF_Pos             (9U)
+#define USART_ISR_CTSIF_Msk             (0x1UL << USART_ISR_CTSIF_Pos)         /*!< 0x00000200 */
+#define USART_ISR_CTSIF                 USART_ISR_CTSIF_Msk                    /*!< CTS interrupt flag */
+#define USART_ISR_CTS_Pos               (10U)
+#define USART_ISR_CTS_Msk               (0x1UL << USART_ISR_CTS_Pos)           /*!< 0x00000400 */
+#define USART_ISR_CTS                   USART_ISR_CTS_Msk                      /*!< CTS flag */
+#define USART_ISR_RTOF_Pos              (11U)
+#define USART_ISR_RTOF_Msk              (0x1UL << USART_ISR_RTOF_Pos)          /*!< 0x00000800 */
+#define USART_ISR_RTOF                  USART_ISR_RTOF_Msk                     /*!< Receiver Time Out */
+#define USART_ISR_EOBF_Pos              (12U)
+#define USART_ISR_EOBF_Msk              (0x1UL << USART_ISR_EOBF_Pos)          /*!< 0x00001000 */
+#define USART_ISR_EOBF                  USART_ISR_EOBF_Msk                     /*!< End Of Block Flag */
+#define USART_ISR_UDR_Pos               (13U)
+#define USART_ISR_UDR_Msk               (0x1UL << USART_ISR_UDR_Pos)           /*!< 0x00002000 */
+#define USART_ISR_UDR                   USART_ISR_UDR_Msk                      /*!< SPI slave underrun error flag */
+#define USART_ISR_ABRE_Pos              (14U)
+#define USART_ISR_ABRE_Msk              (0x1UL << USART_ISR_ABRE_Pos)          /*!< 0x00004000 */
+#define USART_ISR_ABRE                  USART_ISR_ABRE_Msk                     /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF_Pos              (15U)
+#define USART_ISR_ABRF_Msk              (0x1UL << USART_ISR_ABRF_Pos)          /*!< 0x00008000 */
+#define USART_ISR_ABRF                  USART_ISR_ABRF_Msk                     /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY_Pos              (16U)
+#define USART_ISR_BUSY_Msk              (0x1UL << USART_ISR_BUSY_Pos)          /*!< 0x00010000 */
+#define USART_ISR_BUSY                  USART_ISR_BUSY_Msk                     /*!< Busy Flag */
+#define USART_ISR_CMF_Pos               (17U)
+#define USART_ISR_CMF_Msk               (0x1UL << USART_ISR_CMF_Pos)           /*!< 0x00020000 */
+#define USART_ISR_CMF                   USART_ISR_CMF_Msk                      /*!< Character Match Flag */
+#define USART_ISR_SBKF_Pos              (18U)
+#define USART_ISR_SBKF_Msk              (0x1UL << USART_ISR_SBKF_Pos)          /*!< 0x00040000 */
+#define USART_ISR_SBKF                  USART_ISR_SBKF_Msk                     /*!< Send Break Flag */
+#define USART_ISR_RWU_Pos               (19U)
+#define USART_ISR_RWU_Msk               (0x1UL << USART_ISR_RWU_Pos)           /*!< 0x00080000 */
+#define USART_ISR_RWU                   USART_ISR_RWU_Msk                      /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF_Pos               (20U)
+#define USART_ISR_WUF_Msk               (0x1UL << USART_ISR_WUF_Pos)           /*!< 0x00100000 */
+#define USART_ISR_WUF                   USART_ISR_WUF_Msk                      /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK_Pos             (21U)
+#define USART_ISR_TEACK_Msk             (0x1UL << USART_ISR_TEACK_Pos)         /*!< 0x00200000 */
+#define USART_ISR_TEACK                 USART_ISR_TEACK_Msk                    /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK_Pos             (22U)
+#define USART_ISR_REACK_Msk             (0x1UL << USART_ISR_REACK_Pos)         /*!< 0x00400000 */
+#define USART_ISR_REACK                 USART_ISR_REACK_Msk                    /*!< Receive Enable Acknowledge Flag */
+#define USART_ISR_TXFE_Pos              (23U)
+#define USART_ISR_TXFE_Msk              (0x1UL << USART_ISR_TXFE_Pos)          /*!< 0x00800000 */
+#define USART_ISR_TXFE                  USART_ISR_TXFE_Msk                     /*!< TXFIFO Empty */
+#define USART_ISR_RXFF_Pos              (24U)
+#define USART_ISR_RXFF_Msk              (0x1UL << USART_ISR_RXFF_Pos)          /*!< 0x01000000 */
+#define USART_ISR_RXFF                  USART_ISR_RXFF_Msk                     /*!< RXFIFO Full Flag */
+#define USART_ISR_TCBGT_Pos             (25U)
+#define USART_ISR_TCBGT_Msk             (0x1UL << USART_ISR_TCBGT_Pos)         /*!< 0x02000000 */
+#define USART_ISR_TCBGT                 USART_ISR_TCBGT_Msk                    /*!< Transmission complete before guard time Flag */
+#define USART_ISR_RXFT_Pos              (26U)
+#define USART_ISR_RXFT_Msk              (0x1UL << USART_ISR_RXFT_Pos)          /*!< 0x04000000 */
+#define USART_ISR_RXFT                  USART_ISR_RXFT_Msk                     /*!< RXFIFO threshold Flag */
+#define USART_ISR_TXFT_Pos              (27U)
+#define USART_ISR_TXFT_Msk              (0x1UL << USART_ISR_TXFT_Pos)          /*!< 0x08000000 */
+#define USART_ISR_TXFT                  USART_ISR_TXFT_Msk                     /*!< TXFIFO threshold Flag */
+
+/*******************  Bit definition for USART_ICR register  ******************/
+#define USART_ICR_PECF_Pos              (0U)
+#define USART_ICR_PECF_Msk              (0x1UL << USART_ICR_PECF_Pos)          /*!< 0x00000001 */
+#define USART_ICR_PECF                  USART_ICR_PECF_Msk                     /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF_Pos              (1U)
+#define USART_ICR_FECF_Msk              (0x1UL << USART_ICR_FECF_Pos)          /*!< 0x00000002 */
+#define USART_ICR_FECF                  USART_ICR_FECF_Msk                     /*!< Framing Error Clear Flag */
+#define USART_ICR_NECF_Pos              (2U)
+#define USART_ICR_NECF_Msk              (0x1UL << USART_ICR_NECF_Pos)          /*!< 0x00000004 */
+#define USART_ICR_NECF                  USART_ICR_NECF_Msk                     /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF_Pos             (3U)
+#define USART_ICR_ORECF_Msk             (0x1UL << USART_ICR_ORECF_Pos)         /*!< 0x00000008 */
+#define USART_ICR_ORECF                 USART_ICR_ORECF_Msk                    /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF_Pos            (4U)
+#define USART_ICR_IDLECF_Msk            (0x1UL << USART_ICR_IDLECF_Pos)        /*!< 0x00000010 */
+#define USART_ICR_IDLECF                USART_ICR_IDLECF_Msk                   /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TXFECF_Pos            (5U)
+#define USART_ICR_TXFECF_Msk            (0x1UL << USART_ICR_TXFECF_Pos)        /*!< 0x00000020 */
+#define USART_ICR_TXFECF                USART_ICR_TXFECF_Msk                   /*!< TXFIFO empty clear flag */
+#define USART_ICR_TCCF_Pos              (6U)
+#define USART_ICR_TCCF_Msk              (0x1UL << USART_ICR_TCCF_Pos)          /*!< 0x00000040 */
+#define USART_ICR_TCCF                  USART_ICR_TCCF_Msk                     /*!< Transmission Complete Clear Flag */
+#define USART_ICR_TCBGTCF_Pos           (7U)
+#define USART_ICR_TCBGTCF_Msk           (0x1UL << USART_ICR_TCBGTCF_Pos)       /*!< 0x00000080 */
+#define USART_ICR_TCBGTCF               USART_ICR_TCBGTCF_Msk                  /*!< Transmission complete before guard time Clear Flag */
+#define USART_ICR_LBDCF_Pos             (8U)
+#define USART_ICR_LBDCF_Msk             (0x1UL << USART_ICR_LBDCF_Pos)         /*!< 0x00000100 */
+#define USART_ICR_LBDCF                 USART_ICR_LBDCF_Msk                    /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF_Pos             (9U)
+#define USART_ICR_CTSCF_Msk             (0x1UL << USART_ICR_CTSCF_Pos)         /*!< 0x00000200 */
+#define USART_ICR_CTSCF                 USART_ICR_CTSCF_Msk                    /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF_Pos             (11U)
+#define USART_ICR_RTOCF_Msk             (0x1UL << USART_ICR_RTOCF_Pos)         /*!< 0x00000800 */
+#define USART_ICR_RTOCF                 USART_ICR_RTOCF_Msk                    /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF_Pos             (12U)
+#define USART_ICR_EOBCF_Msk             (0x1UL << USART_ICR_EOBCF_Pos)         /*!< 0x00001000 */
+#define USART_ICR_EOBCF                 USART_ICR_EOBCF_Msk                    /*!< End Of Block Clear Flag */
+#define USART_ICR_UDRCF_Pos             (13U)
+#define USART_ICR_UDRCF_Msk             (0x1UL << USART_ICR_UDRCF_Pos)         /*!< 0x00002000 */
+#define USART_ICR_UDRCF                 USART_ICR_UDRCF_Msk                    /*!< SPI slave underrun clear flag */
+#define USART_ICR_CMCF_Pos              (17U)
+#define USART_ICR_CMCF_Msk              (0x1UL << USART_ICR_CMCF_Pos)          /*!< 0x00020000 */
+#define USART_ICR_CMCF                  USART_ICR_CMCF_Msk                     /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF_Pos              (20U)
+#define USART_ICR_WUCF_Msk              (0x1UL << USART_ICR_WUCF_Pos)          /*!< 0x00100000 */
+#define USART_ICR_WUCF                  USART_ICR_WUCF_Msk                     /*!< Wake Up from stop mode Clear Flag */
+
+/*******************  Bit definition for USART_RDR register  ******************/
+#define USART_RDR_RDR_Pos               (0U)
+#define USART_RDR_RDR_Msk               (0x1FFUL << USART_RDR_RDR_Pos)         /*!< 0x000001FF */
+#define USART_RDR_RDR                   USART_RDR_RDR_Msk                      /*!< RDR[8:0] bits (Receive Data value) */
+
+/*******************  Bit definition for USART_TDR register  ******************/
+#define USART_TDR_TDR_Pos               (0U)
+#define USART_TDR_TDR_Msk               (0x1FFUL << USART_TDR_TDR_Pos)         /*!< 0x000001FF */
+#define USART_TDR_TDR                   USART_TDR_TDR_Msk                      /*!< TDR[8:0] bits (Transmit Data value) */
+
+/*******************  Bit definition for USART_PRESC register  ******************/
+#define USART_PRESC_PRESCALER_Pos       (0U)
+#define USART_PRESC_PRESCALER_Msk       (0xFUL << USART_PRESC_PRESCALER_Pos)   /*!< 0x0000000F */
+#define USART_PRESC_PRESCALER           USART_PRESC_PRESCALER_Msk              /*!< PRESCALER[3:0] bits (Clock prescaler) */
+#define USART_PRESC_PRESCALER_0         (0x1UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000001 */
+#define USART_PRESC_PRESCALER_1         (0x2UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000002 */
+#define USART_PRESC_PRESCALER_2         (0x4UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000004 */
+#define USART_PRESC_PRESCALER_3         (0x8UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000008 */
+
+/******************************************************************************/
+/*                                                                            */
+/*           Single Wire Protocol Master Interface (SWPMI)                    */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for SWPMI_CR register   ********************/
+#define SWPMI_CR_RXDMA_Pos       (0U)
+#define SWPMI_CR_RXDMA_Msk       (0x1UL << SWPMI_CR_RXDMA_Pos)                 /*!< 0x00000001 */
+#define SWPMI_CR_RXDMA           SWPMI_CR_RXDMA_Msk                            /*!<Reception DMA enable                                 */
+#define SWPMI_CR_TXDMA_Pos       (1U)
+#define SWPMI_CR_TXDMA_Msk       (0x1UL << SWPMI_CR_TXDMA_Pos)                 /*!< 0x00000002 */
+#define SWPMI_CR_TXDMA           SWPMI_CR_TXDMA_Msk                            /*!<Transmission DMA enable                              */
+#define SWPMI_CR_RXMODE_Pos      (2U)
+#define SWPMI_CR_RXMODE_Msk      (0x1UL << SWPMI_CR_RXMODE_Pos)                /*!< 0x00000004 */
+#define SWPMI_CR_RXMODE          SWPMI_CR_RXMODE_Msk                           /*!<Reception buffering mode                             */
+#define SWPMI_CR_TXMODE_Pos      (3U)
+#define SWPMI_CR_TXMODE_Msk      (0x1UL << SWPMI_CR_TXMODE_Pos)                /*!< 0x00000008 */
+#define SWPMI_CR_TXMODE          SWPMI_CR_TXMODE_Msk                           /*!<Transmission buffering mode                          */
+#define SWPMI_CR_LPBK_Pos        (4U)
+#define SWPMI_CR_LPBK_Msk        (0x1UL << SWPMI_CR_LPBK_Pos)                  /*!< 0x00000010 */
+#define SWPMI_CR_LPBK            SWPMI_CR_LPBK_Msk                             /*!<Loopback mode enable                                 */
+#define SWPMI_CR_SWPACT_Pos      (5U)
+#define SWPMI_CR_SWPACT_Msk      (0x1UL << SWPMI_CR_SWPACT_Pos)                /*!< 0x00000020 */
+#define SWPMI_CR_SWPACT          SWPMI_CR_SWPACT_Msk                           /*!<Single wire protocol master interface activate       */
+#define SWPMI_CR_DEACT_Pos       (10U)
+#define SWPMI_CR_DEACT_Msk       (0x1UL << SWPMI_CR_DEACT_Pos)                 /*!< 0x00000400 */
+#define SWPMI_CR_DEACT           SWPMI_CR_DEACT_Msk                            /*!<Single wire protocol master interface deactivate     */
+#define SWPMI_CR_SWPEN_Pos       (11U)
+#define SWPMI_CR_SWPEN_Msk       (0x1UL << SWPMI_CR_SWPEN_Pos)                 /*!< 0x00000800 */
+#define SWPMI_CR_SWPEN           SWPMI_CR_SWPEN_Msk                            /*!<Single wire protocol master transceiver enable       */
+
+/*******************  Bit definition for SWPMI_BRR register  ********************/
+#define SWPMI_BRR_BR_Pos         (0U)
+#define SWPMI_BRR_BR_Msk         (0xFFUL << SWPMI_BRR_BR_Pos)                  /*!< 0x000000FF */
+#define SWPMI_BRR_BR             SWPMI_BRR_BR_Msk                              /*!<BR[7:0] bits (Bitrate prescaler) */
+
+/*******************  Bit definition for SWPMI_ISR register  ********************/
+#define SWPMI_ISR_RXBFF_Pos      (0U)
+#define SWPMI_ISR_RXBFF_Msk      (0x1UL << SWPMI_ISR_RXBFF_Pos)                /*!< 0x00000001 */
+#define SWPMI_ISR_RXBFF          SWPMI_ISR_RXBFF_Msk                           /*!<Receive buffer full flag        */
+#define SWPMI_ISR_TXBEF_Pos      (1U)
+#define SWPMI_ISR_TXBEF_Msk      (0x1UL << SWPMI_ISR_TXBEF_Pos)                /*!< 0x00000002 */
+#define SWPMI_ISR_TXBEF          SWPMI_ISR_TXBEF_Msk                           /*!<Transmit buffer empty flag      */
+#define SWPMI_ISR_RXBERF_Pos     (2U)
+#define SWPMI_ISR_RXBERF_Msk     (0x1UL << SWPMI_ISR_RXBERF_Pos)               /*!< 0x00000004 */
+#define SWPMI_ISR_RXBERF         SWPMI_ISR_RXBERF_Msk                          /*!<Receive CRC error flag          */
+#define SWPMI_ISR_RXOVRF_Pos     (3U)
+#define SWPMI_ISR_RXOVRF_Msk     (0x1UL << SWPMI_ISR_RXOVRF_Pos)               /*!< 0x00000008 */
+#define SWPMI_ISR_RXOVRF         SWPMI_ISR_RXOVRF_Msk                          /*!<Receive overrun error flag      */
+#define SWPMI_ISR_TXUNRF_Pos     (4U)
+#define SWPMI_ISR_TXUNRF_Msk     (0x1UL << SWPMI_ISR_TXUNRF_Pos)               /*!< 0x00000010 */
+#define SWPMI_ISR_TXUNRF         SWPMI_ISR_TXUNRF_Msk                          /*!<Transmit underrun error flag    */
+#define SWPMI_ISR_RXNE_Pos       (5U)
+#define SWPMI_ISR_RXNE_Msk       (0x1UL << SWPMI_ISR_RXNE_Pos)                 /*!< 0x00000020 */
+#define SWPMI_ISR_RXNE           SWPMI_ISR_RXNE_Msk                            /*!<Receive data register not empty */
+#define SWPMI_ISR_TXE_Pos        (6U)
+#define SWPMI_ISR_TXE_Msk        (0x1UL << SWPMI_ISR_TXE_Pos)                  /*!< 0x00000040 */
+#define SWPMI_ISR_TXE            SWPMI_ISR_TXE_Msk                             /*!<Transmit data register empty    */
+#define SWPMI_ISR_TCF_Pos        (7U)
+#define SWPMI_ISR_TCF_Msk        (0x1UL << SWPMI_ISR_TCF_Pos)                  /*!< 0x00000080 */
+#define SWPMI_ISR_TCF            SWPMI_ISR_TCF_Msk                             /*!<Transfer complete flag          */
+#define SWPMI_ISR_SRF_Pos        (8U)
+#define SWPMI_ISR_SRF_Msk        (0x1UL << SWPMI_ISR_SRF_Pos)                  /*!< 0x00000100 */
+#define SWPMI_ISR_SRF            SWPMI_ISR_SRF_Msk                             /*!<Slave resume flag               */
+#define SWPMI_ISR_SUSP_Pos       (9U)
+#define SWPMI_ISR_SUSP_Msk       (0x1UL << SWPMI_ISR_SUSP_Pos)                 /*!< 0x00000200 */
+#define SWPMI_ISR_SUSP           SWPMI_ISR_SUSP_Msk                            /*!<SUSPEND flag                    */
+#define SWPMI_ISR_DEACTF_Pos     (10U)
+#define SWPMI_ISR_DEACTF_Msk     (0x1UL << SWPMI_ISR_DEACTF_Pos)               /*!< 0x00000400 */
+#define SWPMI_ISR_DEACTF         SWPMI_ISR_DEACTF_Msk                          /*!<DEACTIVATED flag                */
+#define SWPMI_ISR_RDYF_Pos       (11U)
+#define SWPMI_ISR_RDYF_Msk       (0x1UL << SWPMI_ISR_RDYF_Pos)                 /*!< 0x00000800 */
+#define SWPMI_ISR_RDYF           SWPMI_ISR_RDYF_Msk                            /*!<Transceiver ready flag          */
+
+/*******************  Bit definition for SWPMI_ICR register  ********************/
+#define SWPMI_ICR_CRXBFF_Pos     (0U)
+#define SWPMI_ICR_CRXBFF_Msk     (0x1UL << SWPMI_ICR_CRXBFF_Pos)               /*!< 0x00000001 */
+#define SWPMI_ICR_CRXBFF         SWPMI_ICR_CRXBFF_Msk                          /*!<Clear receive buffer full flag       */
+#define SWPMI_ICR_CTXBEF_Pos     (1U)
+#define SWPMI_ICR_CTXBEF_Msk     (0x1UL << SWPMI_ICR_CTXBEF_Pos)               /*!< 0x00000002 */
+#define SWPMI_ICR_CTXBEF         SWPMI_ICR_CTXBEF_Msk                          /*!<Clear transmit buffer empty flag     */
+#define SWPMI_ICR_CRXBERF_Pos    (2U)
+#define SWPMI_ICR_CRXBERF_Msk    (0x1UL << SWPMI_ICR_CRXBERF_Pos)              /*!< 0x00000004 */
+#define SWPMI_ICR_CRXBERF        SWPMI_ICR_CRXBERF_Msk                         /*!<Clear receive CRC error flag         */
+#define SWPMI_ICR_CRXOVRF_Pos    (3U)
+#define SWPMI_ICR_CRXOVRF_Msk    (0x1UL << SWPMI_ICR_CRXOVRF_Pos)              /*!< 0x00000008 */
+#define SWPMI_ICR_CRXOVRF        SWPMI_ICR_CRXOVRF_Msk                         /*!<Clear receive overrun error flag     */
+#define SWPMI_ICR_CTXUNRF_Pos    (4U)
+#define SWPMI_ICR_CTXUNRF_Msk    (0x1UL << SWPMI_ICR_CTXUNRF_Pos)              /*!< 0x00000010 */
+#define SWPMI_ICR_CTXUNRF        SWPMI_ICR_CTXUNRF_Msk                         /*!<Clear transmit underrun error flag   */
+#define SWPMI_ICR_CTCF_Pos       (7U)
+#define SWPMI_ICR_CTCF_Msk       (0x1UL << SWPMI_ICR_CTCF_Pos)                 /*!< 0x00000080 */
+#define SWPMI_ICR_CTCF           SWPMI_ICR_CTCF_Msk                            /*!<Clear transfer complete flag         */
+#define SWPMI_ICR_CSRF_Pos       (8U)
+#define SWPMI_ICR_CSRF_Msk       (0x1UL << SWPMI_ICR_CSRF_Pos)                 /*!< 0x00000100 */
+#define SWPMI_ICR_CSRF           SWPMI_ICR_CSRF_Msk                            /*!<Clear slave resume flag              */
+#define SWPMI_ICR_CRDYF_Pos      (11U)
+#define SWPMI_ICR_CRDYF_Msk      (0x1UL << SWPMI_ICR_CRDYF_Pos)                /*!< 0x00000800 */
+#define SWPMI_ICR_CRDYF          SWPMI_ICR_CRDYF_Msk                           /*!<Clear transceiver ready flag         */
+
+/*******************  Bit definition for SWPMI_IER register  ********************/
+#define SWPMI_IER_RXBFIE_Pos     (0U)
+#define SWPMI_IER_RXBFIE_Msk     (0x1UL << SWPMI_IER_RXBFIE_Pos)               /*!< 0x00000001 */
+#define SWPMI_IER_RXBFIE         SWPMI_IER_RXBFIE_Msk                          /*!<Receive buffer full interrupt enable        */
+#define SWPMI_IER_TXBEIE_Pos     (1U)
+#define SWPMI_IER_TXBEIE_Msk     (0x1UL << SWPMI_IER_TXBEIE_Pos)               /*!< 0x00000002 */
+#define SWPMI_IER_TXBEIE         SWPMI_IER_TXBEIE_Msk                          /*!<Transmit buffer empty interrupt enable      */
+#define SWPMI_IER_RXBERIE_Pos    (2U)
+#define SWPMI_IER_RXBERIE_Msk    (0x1UL << SWPMI_IER_RXBERIE_Pos)              /*!< 0x00000004 */
+#define SWPMI_IER_RXBERIE        SWPMI_IER_RXBERIE_Msk                         /*!<Receive CRC error interrupt enable          */
+#define SWPMI_IER_RXOVRIE_Pos    (3U)
+#define SWPMI_IER_RXOVRIE_Msk    (0x1UL << SWPMI_IER_RXOVRIE_Pos)              /*!< 0x00000008 */
+#define SWPMI_IER_RXOVRIE        SWPMI_IER_RXOVRIE_Msk                         /*!<Receive overrun error interrupt enable      */
+#define SWPMI_IER_TXUNRIE_Pos    (4U)
+#define SWPMI_IER_TXUNRIE_Msk    (0x1UL << SWPMI_IER_TXUNRIE_Pos)              /*!< 0x00000010 */
+#define SWPMI_IER_TXUNRIE        SWPMI_IER_TXUNRIE_Msk                         /*!<Transmit underrun error interrupt enable    */
+#define SWPMI_IER_RIE_Pos        (5U)
+#define SWPMI_IER_RIE_Msk        (0x1UL << SWPMI_IER_RIE_Pos)                  /*!< 0x00000020 */
+#define SWPMI_IER_RIE            SWPMI_IER_RIE_Msk                             /*!<Receive interrupt enable                    */
+#define SWPMI_IER_TIE_Pos        (6U)
+#define SWPMI_IER_TIE_Msk        (0x1UL << SWPMI_IER_TIE_Pos)                  /*!< 0x00000040 */
+#define SWPMI_IER_TIE            SWPMI_IER_TIE_Msk                             /*!<Transmit interrupt enable                   */
+#define SWPMI_IER_TCIE_Pos       (7U)
+#define SWPMI_IER_TCIE_Msk       (0x1UL << SWPMI_IER_TCIE_Pos)                 /*!< 0x00000080 */
+#define SWPMI_IER_TCIE           SWPMI_IER_TCIE_Msk                            /*!<Transmit complete interrupt enable          */
+#define SWPMI_IER_SRIE_Pos       (8U)
+#define SWPMI_IER_SRIE_Msk       (0x1UL << SWPMI_IER_SRIE_Pos)                 /*!< 0x00000100 */
+#define SWPMI_IER_SRIE           SWPMI_IER_SRIE_Msk                            /*!<Slave resume interrupt enable               */
+#define SWPMI_IER_RDYIE_Pos      (11U)
+#define SWPMI_IER_RDYIE_Msk      (0x1UL << SWPMI_IER_RDYIE_Pos)                /*!< 0x00000800 */
+#define SWPMI_IER_RDYIE          SWPMI_IER_RDYIE_Msk                           /*!<Transceiver ready interrupt enable          */
+
+/*******************  Bit definition for SWPMI_RFL register  ********************/
+#define SWPMI_RFL_RFL_Pos        (0U)
+#define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */
+#define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */
+#define SWPMI_RFL_RFL_0_1        ((uint32_t)0x00000003)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
+
+/*******************  Bit definition for SWPMI_TDR register  ********************/
+#define SWPMI_TDR_TD_Pos         (0U)
+#define SWPMI_TDR_TD_Msk         (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos)            /*!< 0xFFFFFFFF */
+#define SWPMI_TDR_TD             SWPMI_TDR_TD_Msk                              /*!<Transmit Data Register         */
+
+/*******************  Bit definition for SWPMI_RDR register  ********************/
+#define SWPMI_RDR_RD_Pos         (0U)
+#define SWPMI_RDR_RD_Msk         (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos)            /*!< 0xFFFFFFFF */
+#define SWPMI_RDR_RD             SWPMI_RDR_RD_Msk                              /*!<Recive Data Register           */
+
+
+/*******************  Bit definition for SWPMI_OR register  ********************/
+#define SWPMI_OR_TBYP_Pos        (0U)
+#define SWPMI_OR_TBYP_Msk        (0x1UL << SWPMI_OR_TBYP_Pos)                  /*!< 0x00000001 */
+#define SWPMI_OR_TBYP            SWPMI_OR_TBYP_Msk                             /*!<SWP Transceiver Bypass */
+#define SWPMI_OR_CLASS_Pos       (1U)
+#define SWPMI_OR_CLASS_Msk       (0x1UL << SWPMI_OR_CLASS_Pos)                 /*!< 0x00000002 */
+#define SWPMI_OR_CLASS           SWPMI_OR_CLASS_Msk                            /*!<SWP CLASS selection */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Window WATCHDOG                                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define WWDG_CR_T_Pos           (0U)
+#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                      /*!< 0x0000007F */
+#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
+#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
+#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
+#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
+#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
+#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
+#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
+
+#define WWDG_CR_WDGA_Pos        (7U)
+#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                    /*!< 0x00000080 */
+#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define WWDG_CFR_W_Pos          (0U)
+#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                     /*!< 0x0000007F */
+#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
+#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
+#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
+#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
+#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
+#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
+#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
+
+#define WWDG_CFR_EWI_Pos        (9U)
+#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                    /*!< 0x00000200 */
+#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
+
+#define WWDG_CFR_WDGTB_Pos      (11U)
+#define WWDG_CFR_WDGTB_Msk      (0x7UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00003800 */
+#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[2:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000800 */
+#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00001000 */
+#define WWDG_CFR_WDGTB_2        (0x4UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00002000 */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define WWDG_SR_EWIF_Pos        (0U)
+#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                    /*!< 0x00000001 */
+#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                DBG                                         */
+/*                                                                            */
+/******************************************************************************/
+/*********************************  DEVICE ID  ********************************/
+#define STM32H7_DEV_ID           0x450UL
+
+/********************  Bit definition for DBGMCU_IDCODE register  *************/
+#define DBGMCU_IDCODE_DEV_ID_Pos          (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk          (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID              DBGMCU_IDCODE_DEV_ID_Msk
+#define DBGMCU_IDCODE_REV_ID_Pos          (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk          (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID              DBGMCU_IDCODE_REV_ID_Msk
+
+/********************  Bit definition for DBGMCU_CR register  *****************/
+#define DBGMCU_CR_DBG_SLEEPD1_Pos         (0U)
+#define DBGMCU_CR_DBG_SLEEPD1_Msk         (0x1UL << DBGMCU_CR_DBG_SLEEPD1_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEPD1             DBGMCU_CR_DBG_SLEEPD1_Msk
+#define DBGMCU_CR_DBG_STOPD1_Pos          (1U)
+#define DBGMCU_CR_DBG_STOPD1_Msk          (0x1UL << DBGMCU_CR_DBG_STOPD1_Pos)  /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOPD1              DBGMCU_CR_DBG_STOPD1_Msk
+#define DBGMCU_CR_DBG_STANDBYD1_Pos       (2U)
+#define DBGMCU_CR_DBG_STANDBYD1_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYD1_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBYD1           DBGMCU_CR_DBG_STANDBYD1_Msk
+#define DBGMCU_CR_DBG_STOPD3_Pos          (7U)
+#define DBGMCU_CR_DBG_STOPD3_Msk          (0x1UL << DBGMCU_CR_DBG_STOPD3_Pos)  /*!< 0x00000080 */
+#define DBGMCU_CR_DBG_STOPD3              DBGMCU_CR_DBG_STOPD3_Msk
+#define DBGMCU_CR_DBG_STANDBYD3_Pos       (8U)
+#define DBGMCU_CR_DBG_STANDBYD3_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYD3_Pos) /*!< 0x00000100 */
+#define DBGMCU_CR_DBG_STANDBYD3           DBGMCU_CR_DBG_STANDBYD3_Msk
+#define DBGMCU_CR_DBG_TRACECKEN_Pos       (20U)
+#define DBGMCU_CR_DBG_TRACECKEN_Msk       (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos) /*!< 0x00100000 */
+#define DBGMCU_CR_DBG_TRACECKEN           DBGMCU_CR_DBG_TRACECKEN_Msk
+#define DBGMCU_CR_DBG_CKD1EN_Pos          (21U)
+#define DBGMCU_CR_DBG_CKD1EN_Msk          (0x1UL << DBGMCU_CR_DBG_CKD1EN_Pos)  /*!< 0x00200000 */
+#define DBGMCU_CR_DBG_CKD1EN              DBGMCU_CR_DBG_CKD1EN_Msk
+#define DBGMCU_CR_DBG_CKD3EN_Pos          (22U)
+#define DBGMCU_CR_DBG_CKD3EN_Msk          (0x1UL << DBGMCU_CR_DBG_CKD3EN_Pos)  /*!< 0x00400000 */
+#define DBGMCU_CR_DBG_CKD3EN              DBGMCU_CR_DBG_CKD3EN_Msk
+#define DBGMCU_CR_DBG_TRGOEN_Pos          (28U)
+#define DBGMCU_CR_DBG_TRGOEN_Msk          (0x1UL << DBGMCU_CR_DBG_TRGOEN_Pos)  /*!< 0x10000000 */
+#define DBGMCU_CR_DBG_TRGOEN              DBGMCU_CR_DBG_TRGOEN_Msk
+
+/********************  Bit definition for APB3FZ1 register  ************/
+#define DBGMCU_APB3FZ1_DBG_WWDG1_Pos      (6U)
+#define DBGMCU_APB3FZ1_DBG_WWDG1_Msk      (0x1UL << DBGMCU_APB3FZ1_DBG_WWDG1_Pos) /*!< 0x00000040 */
+#define DBGMCU_APB3FZ1_DBG_WWDG1          DBGMCU_APB3FZ1_DBG_WWDG1_Msk
+/********************  Bit definition for APB1LFZ1 register  ************/
+#define DBGMCU_APB1LFZ1_DBG_TIM2_Pos      (0U)
+#define DBGMCU_APB1LFZ1_DBG_TIM2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1LFZ1_DBG_TIM2          DBGMCU_APB1LFZ1_DBG_TIM2_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM3_Pos      (1U)
+#define DBGMCU_APB1LFZ1_DBG_TIM3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB1LFZ1_DBG_TIM3          DBGMCU_APB1LFZ1_DBG_TIM3_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM4_Pos      (2U)
+#define DBGMCU_APB1LFZ1_DBG_TIM4_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB1LFZ1_DBG_TIM4          DBGMCU_APB1LFZ1_DBG_TIM4_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM5_Pos      (3U)
+#define DBGMCU_APB1LFZ1_DBG_TIM5_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_Pos) /*!< 0x00000008 */
+#define DBGMCU_APB1LFZ1_DBG_TIM5          DBGMCU_APB1LFZ1_DBG_TIM5_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM6_Pos      (4U)
+#define DBGMCU_APB1LFZ1_DBG_TIM6_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB1LFZ1_DBG_TIM6          DBGMCU_APB1LFZ1_DBG_TIM6_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM7_Pos      (5U)
+#define DBGMCU_APB1LFZ1_DBG_TIM7_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB1LFZ1_DBG_TIM7          DBGMCU_APB1LFZ1_DBG_TIM7_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM12_Pos     (6U)
+#define DBGMCU_APB1LFZ1_DBG_TIM12_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_Pos) /*!< 0x00000040 */
+#define DBGMCU_APB1LFZ1_DBG_TIM12         DBGMCU_APB1LFZ1_DBG_TIM12_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM13_Pos     (7U)
+#define DBGMCU_APB1LFZ1_DBG_TIM13_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_Pos) /*!< 0x00000080 */
+#define DBGMCU_APB1LFZ1_DBG_TIM13         DBGMCU_APB1LFZ1_DBG_TIM13_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM14_Pos     (8U)
+#define DBGMCU_APB1LFZ1_DBG_TIM14_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_Pos) /*!< 0x00000100 */
+#define DBGMCU_APB1LFZ1_DBG_TIM14         DBGMCU_APB1LFZ1_DBG_TIM14_Msk
+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos    (9U)
+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos) /*!< 0x00000200 */
+#define DBGMCU_APB1LFZ1_DBG_LPTIM1        DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk
+#define DBGMCU_APB1LFZ1_DBG_I2C1_Pos      (21U)
+#define DBGMCU_APB1LFZ1_DBG_I2C1_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1LFZ1_DBG_I2C1          DBGMCU_APB1LFZ1_DBG_I2C1_Msk
+#define DBGMCU_APB1LFZ1_DBG_I2C2_Pos      (22U)
+#define DBGMCU_APB1LFZ1_DBG_I2C2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1LFZ1_DBG_I2C2          DBGMCU_APB1LFZ1_DBG_I2C2_Msk
+#define DBGMCU_APB1LFZ1_DBG_I2C3_Pos      (23U)
+#define DBGMCU_APB1LFZ1_DBG_I2C3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_Pos) /*!< 0x00800000 */
+#define DBGMCU_APB1LFZ1_DBG_I2C3          DBGMCU_APB1LFZ1_DBG_I2C3_Msk
+
+/********************  Bit definition for APB1HFZ1 register  ************/
+#define DBGMCU_APB1HFZ1_DBG_FDCAN_Pos     (8U)
+#define DBGMCU_APB1HFZ1_DBG_FDCAN_Msk     (0x1UL << DBGMCU_APB1HFZ1_DBG_FDCAN_Pos) /*!< 0x00000100 */
+#define DBGMCU_APB1HFZ1_DBG_FDCAN         DBGMCU_APB1HFZ1_DBG_FDCAN_Msk
+/********************  Bit definition for APB2FZ1 register  ************/
+#define DBGMCU_APB2FZ1_DBG_TIM1_Pos       (0U)
+#define DBGMCU_APB2FZ1_DBG_TIM1_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB2FZ1_DBG_TIM1           DBGMCU_APB2FZ1_DBG_TIM1_Msk
+#define DBGMCU_APB2FZ1_DBG_TIM8_Pos       (1U)
+#define DBGMCU_APB2FZ1_DBG_TIM8_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB2FZ1_DBG_TIM8           DBGMCU_APB2FZ1_DBG_TIM8_Msk
+#define DBGMCU_APB2FZ1_DBG_TIM15_Pos      (16U)
+#define DBGMCU_APB2FZ1_DBG_TIM15_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_Pos) /*!< 0x00010000 */
+#define DBGMCU_APB2FZ1_DBG_TIM15          DBGMCU_APB2FZ1_DBG_TIM15_Msk
+#define DBGMCU_APB2FZ1_DBG_TIM16_Pos      (17U)
+#define DBGMCU_APB2FZ1_DBG_TIM16_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_Pos) /*!< 0x00020000 */
+#define DBGMCU_APB2FZ1_DBG_TIM16          DBGMCU_APB2FZ1_DBG_TIM16_Msk
+#define DBGMCU_APB2FZ1_DBG_TIM17_Pos      (18U)
+#define DBGMCU_APB2FZ1_DBG_TIM17_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_Pos) /*!< 0x00040000 */
+#define DBGMCU_APB2FZ1_DBG_TIM17          DBGMCU_APB2FZ1_DBG_TIM17_Msk
+#define DBGMCU_APB2FZ1_DBG_HRTIM_Pos      (29U)
+#define DBGMCU_APB2FZ1_DBG_HRTIM_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_HRTIM_Pos) /*!< 0x20000000 */
+#define DBGMCU_APB2FZ1_DBG_HRTIM          DBGMCU_APB2FZ1_DBG_HRTIM_Msk
+
+/********************  Bit definition for APB4FZ1 register  ************/
+#define DBGMCU_APB4FZ1_DBG_I2C4_Pos       (7U)
+#define DBGMCU_APB4FZ1_DBG_I2C4_Msk       (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_Pos) /*!< 0x00000080 */
+#define DBGMCU_APB4FZ1_DBG_I2C4           DBGMCU_APB4FZ1_DBG_I2C4_Msk
+#define DBGMCU_APB4FZ1_DBG_LPTIM2_Pos     (9U)
+#define DBGMCU_APB4FZ1_DBG_LPTIM2_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_Pos) /*!< 0x00000200 */
+#define DBGMCU_APB4FZ1_DBG_LPTIM2         DBGMCU_APB4FZ1_DBG_LPTIM2_Msk
+#define DBGMCU_APB4FZ1_DBG_LPTIM3_Pos     (10U)
+#define DBGMCU_APB4FZ1_DBG_LPTIM3_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB4FZ1_DBG_LPTIM3         DBGMCU_APB4FZ1_DBG_LPTIM3_Msk
+#define DBGMCU_APB4FZ1_DBG_LPTIM4_Pos     (11U)
+#define DBGMCU_APB4FZ1_DBG_LPTIM4_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM4_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB4FZ1_DBG_LPTIM4         DBGMCU_APB4FZ1_DBG_LPTIM4_Msk
+#define DBGMCU_APB4FZ1_DBG_LPTIM5_Pos     (12U)
+#define DBGMCU_APB4FZ1_DBG_LPTIM5_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM5_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB4FZ1_DBG_LPTIM5         DBGMCU_APB4FZ1_DBG_LPTIM5_Msk
+#define DBGMCU_APB4FZ1_DBG_RTC_Pos        (16U)
+#define DBGMCU_APB4FZ1_DBG_RTC_Msk        (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_Pos) /*!< 0x00010000 */
+#define DBGMCU_APB4FZ1_DBG_RTC            DBGMCU_APB4FZ1_DBG_RTC_Msk
+#define DBGMCU_APB4FZ1_DBG_IWDG1_Pos      (18U)
+#define DBGMCU_APB4FZ1_DBG_IWDG1_Msk      (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG1_Pos) /*!< 0x00040000 */
+#define DBGMCU_APB4FZ1_DBG_IWDG1          DBGMCU_APB4FZ1_DBG_IWDG1_Msk
+/******************************************************************************/
+/*                                                                            */
+/*                        High Resolution Timer (HRTIM)                       */
+/*                                                                            */
+/******************************************************************************/
+/******************** Master Timer control register ***************************/
+#define HRTIM_MCR_CK_PSC_Pos          (0U)
+#define HRTIM_MCR_CK_PSC_Msk          (0x7UL << HRTIM_MCR_CK_PSC_Pos)          /*!< 0x00000007 */
+#define HRTIM_MCR_CK_PSC              HRTIM_MCR_CK_PSC_Msk                     /*!< Prescaler mask */
+#define HRTIM_MCR_CK_PSC_0            (0x1UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000001 */
+#define HRTIM_MCR_CK_PSC_1            (0x2UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000002 */
+#define HRTIM_MCR_CK_PSC_2            (0x4UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000004 */
+
+#define HRTIM_MCR_CONT_Pos            (3U)
+#define HRTIM_MCR_CONT_Msk            (0x1UL << HRTIM_MCR_CONT_Pos)            /*!< 0x00000008 */
+#define HRTIM_MCR_CONT                HRTIM_MCR_CONT_Msk                       /*!< Continuous mode */
+#define HRTIM_MCR_RETRIG_Pos          (4U)
+#define HRTIM_MCR_RETRIG_Msk          (0x1UL << HRTIM_MCR_RETRIG_Pos)          /*!< 0x00000010 */
+#define HRTIM_MCR_RETRIG              HRTIM_MCR_RETRIG_Msk                     /*!< Rettrigreable mode */
+#define HRTIM_MCR_HALF_Pos            (5U)
+#define HRTIM_MCR_HALF_Msk            (0x1UL << HRTIM_MCR_HALF_Pos)            /*!< 0x00000020 */
+#define HRTIM_MCR_HALF                HRTIM_MCR_HALF_Msk                       /*!< Half mode */
+
+#define HRTIM_MCR_SYNC_IN_Pos         (8U)
+#define HRTIM_MCR_SYNC_IN_Msk         (0x3UL << HRTIM_MCR_SYNC_IN_Pos)         /*!< 0x00000300 */
+#define HRTIM_MCR_SYNC_IN             HRTIM_MCR_SYNC_IN_Msk                    /*!< Synchronization input master */
+#define HRTIM_MCR_SYNC_IN_0           (0x1UL << HRTIM_MCR_SYNC_IN_Pos)          /*!< 0x00000100 */
+#define HRTIM_MCR_SYNC_IN_1           (0x2UL << HRTIM_MCR_SYNC_IN_Pos)          /*!< 0x00000200 */
+#define HRTIM_MCR_SYNCRSTM_Pos        (10U)
+#define HRTIM_MCR_SYNCRSTM_Msk        (0x1UL << HRTIM_MCR_SYNCRSTM_Pos)        /*!< 0x00000400 */
+#define HRTIM_MCR_SYNCRSTM            HRTIM_MCR_SYNCRSTM_Msk                   /*!< Synchronization reset master */
+#define HRTIM_MCR_SYNCSTRTM_Pos       (11U)
+#define HRTIM_MCR_SYNCSTRTM_Msk       (0x1UL << HRTIM_MCR_SYNCSTRTM_Pos)       /*!< 0x00000800 */
+#define HRTIM_MCR_SYNCSTRTM           HRTIM_MCR_SYNCSTRTM_Msk                  /*!< Synchronization start master */
+#define HRTIM_MCR_SYNC_OUT_Pos        (12U)
+#define HRTIM_MCR_SYNC_OUT_Msk        (0x3UL << HRTIM_MCR_SYNC_OUT_Pos)        /*!< 0x00003000 */
+#define HRTIM_MCR_SYNC_OUT            HRTIM_MCR_SYNC_OUT_Msk                   /*!< Synchronization output master */
+#define HRTIM_MCR_SYNC_OUT_0          (0x1UL << HRTIM_MCR_SYNC_OUT_Pos)         /*!< 0x00001000 */
+#define HRTIM_MCR_SYNC_OUT_1          (0x2UL << HRTIM_MCR_SYNC_OUT_Pos)         /*!< 0x00002000 */
+#define HRTIM_MCR_SYNC_SRC_Pos        (14U)
+#define HRTIM_MCR_SYNC_SRC_Msk        (0x3UL << HRTIM_MCR_SYNC_SRC_Pos)        /*!< 0x0000C000 */
+#define HRTIM_MCR_SYNC_SRC            HRTIM_MCR_SYNC_SRC_Msk                   /*!< Synchronization source */
+#define HRTIM_MCR_SYNC_SRC_0          (0x1UL << HRTIM_MCR_SYNC_SRC_Pos)         /*!< 0x00004000 */
+#define HRTIM_MCR_SYNC_SRC_1          (0x2UL << HRTIM_MCR_SYNC_SRC_Pos)         /*!< 0x00008000 */
+
+#define HRTIM_MCR_MCEN_Pos            (16U)
+#define HRTIM_MCR_MCEN_Msk            (0x1UL << HRTIM_MCR_MCEN_Pos)            /*!< 0x00010000 */
+#define HRTIM_MCR_MCEN                HRTIM_MCR_MCEN_Msk                       /*!< Master counter enable */
+#define HRTIM_MCR_TACEN_Pos           (17U)
+#define HRTIM_MCR_TACEN_Msk           (0x1UL << HRTIM_MCR_TACEN_Pos)           /*!< 0x00020000 */
+#define HRTIM_MCR_TACEN               HRTIM_MCR_TACEN_Msk                      /*!< Timer A counter enable */
+#define HRTIM_MCR_TBCEN_Pos           (18U)
+#define HRTIM_MCR_TBCEN_Msk           (0x1UL << HRTIM_MCR_TBCEN_Pos)           /*!< 0x00040000 */
+#define HRTIM_MCR_TBCEN               HRTIM_MCR_TBCEN_Msk                      /*!< Timer B counter enable */
+#define HRTIM_MCR_TCCEN_Pos           (19U)
+#define HRTIM_MCR_TCCEN_Msk           (0x1UL << HRTIM_MCR_TCCEN_Pos)           /*!< 0x00080000 */
+#define HRTIM_MCR_TCCEN               HRTIM_MCR_TCCEN_Msk                      /*!< Timer C counter enable */
+#define HRTIM_MCR_TDCEN_Pos           (20U)
+#define HRTIM_MCR_TDCEN_Msk           (0x1UL << HRTIM_MCR_TDCEN_Pos)           /*!< 0x00100000 */
+#define HRTIM_MCR_TDCEN               HRTIM_MCR_TDCEN_Msk                      /*!< Timer D counter enable */
+#define HRTIM_MCR_TECEN_Pos           (21U)
+#define HRTIM_MCR_TECEN_Msk           (0x1UL << HRTIM_MCR_TECEN_Pos)           /*!< 0x00200000 */
+#define HRTIM_MCR_TECEN               HRTIM_MCR_TECEN_Msk                      /*!< Timer E counter enable */
+
+#define HRTIM_MCR_DACSYNC_Pos         (25U)
+#define HRTIM_MCR_DACSYNC_Msk         (0x3UL << HRTIM_MCR_DACSYNC_Pos)         /*!< 0x06000000 */
+#define HRTIM_MCR_DACSYNC             HRTIM_MCR_DACSYNC_Msk                    /*!< DAC sychronization mask */
+#define HRTIM_MCR_DACSYNC_0           (0x1UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x02000000 */
+#define HRTIM_MCR_DACSYNC_1           (0x2UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x04000000 */
+
+#define HRTIM_MCR_PREEN_Pos           (27U)
+#define HRTIM_MCR_PREEN_Msk           (0x1UL << HRTIM_MCR_PREEN_Pos)           /*!< 0x08000000 */
+#define HRTIM_MCR_PREEN               HRTIM_MCR_PREEN_Msk                      /*!< Master preload enable */
+#define HRTIM_MCR_MREPU_Pos           (29U)
+#define HRTIM_MCR_MREPU_Msk           (0x1UL << HRTIM_MCR_MREPU_Pos)           /*!< 0x20000000 */
+#define HRTIM_MCR_MREPU               HRTIM_MCR_MREPU_Msk                      /*!< Master repetition update */
+
+#define HRTIM_MCR_BRSTDMA_Pos         (30U)
+#define HRTIM_MCR_BRSTDMA_Msk         (0x3UL << HRTIM_MCR_BRSTDMA_Pos)         /*!< 0xC0000000 */
+#define HRTIM_MCR_BRSTDMA             HRTIM_MCR_BRSTDMA_Msk                    /*!< Burst DMA update */
+#define HRTIM_MCR_BRSTDMA_0           (0x1UL << HRTIM_MCR_BRSTDMA_Pos)          /*!< 0x40000000 */
+#define HRTIM_MCR_BRSTDMA_1           (0x2UL << HRTIM_MCR_BRSTDMA_Pos)          /*!< 0x80000000 */
+
+/******************** Master Timer Interrupt status register ******************/
+#define HRTIM_MISR_MCMP1_Pos          (0U)
+#define HRTIM_MISR_MCMP1_Msk          (0x1UL << HRTIM_MISR_MCMP1_Pos)          /*!< 0x00000001 */
+#define HRTIM_MISR_MCMP1              HRTIM_MISR_MCMP1_Msk                     /*!< Master compare 1 interrupt flag */
+#define HRTIM_MISR_MCMP2_Pos          (1U)
+#define HRTIM_MISR_MCMP2_Msk          (0x1UL << HRTIM_MISR_MCMP2_Pos)          /*!< 0x00000002 */
+#define HRTIM_MISR_MCMP2              HRTIM_MISR_MCMP2_Msk                     /*!< Master compare 2 interrupt flag */
+#define HRTIM_MISR_MCMP3_Pos          (2U)
+#define HRTIM_MISR_MCMP3_Msk          (0x1UL << HRTIM_MISR_MCMP3_Pos)          /*!< 0x00000004 */
+#define HRTIM_MISR_MCMP3              HRTIM_MISR_MCMP3_Msk                     /*!< Master compare 3 interrupt flag */
+#define HRTIM_MISR_MCMP4_Pos          (3U)
+#define HRTIM_MISR_MCMP4_Msk          (0x1UL << HRTIM_MISR_MCMP4_Pos)          /*!< 0x00000008 */
+#define HRTIM_MISR_MCMP4              HRTIM_MISR_MCMP4_Msk                     /*!< Master compare 4 interrupt flag */
+#define HRTIM_MISR_MREP_Pos           (4U)
+#define HRTIM_MISR_MREP_Msk           (0x1UL << HRTIM_MISR_MREP_Pos)           /*!< 0x00000010 */
+#define HRTIM_MISR_MREP               HRTIM_MISR_MREP_Msk                      /*!< Master Repetition interrupt flag */
+#define HRTIM_MISR_SYNC_Pos           (5U)
+#define HRTIM_MISR_SYNC_Msk           (0x1UL << HRTIM_MISR_SYNC_Pos)           /*!< 0x00000020 */
+#define HRTIM_MISR_SYNC               HRTIM_MISR_SYNC_Msk                      /*!< Synchronization input interrupt flag */
+#define HRTIM_MISR_MUPD_Pos           (6U)
+#define HRTIM_MISR_MUPD_Msk           (0x1UL << HRTIM_MISR_MUPD_Pos)           /*!< 0x00000040 */
+#define HRTIM_MISR_MUPD               HRTIM_MISR_MUPD_Msk                      /*!< Master update interrupt flag */
+
+/******************** Master Timer Interrupt clear register *******************/
+#define HRTIM_MICR_MCMP1_Pos          (0U)
+#define HRTIM_MICR_MCMP1_Msk          (0x1UL << HRTIM_MICR_MCMP1_Pos)          /*!< 0x00000001 */
+#define HRTIM_MICR_MCMP1              HRTIM_MICR_MCMP1_Msk                     /*!< Master compare 1 interrupt flag clear */
+#define HRTIM_MICR_MCMP2_Pos          (1U)
+#define HRTIM_MICR_MCMP2_Msk          (0x1UL << HRTIM_MICR_MCMP2_Pos)          /*!< 0x00000002 */
+#define HRTIM_MICR_MCMP2              HRTIM_MICR_MCMP2_Msk                     /*!< Master compare 2 interrupt flag clear */
+#define HRTIM_MICR_MCMP3_Pos          (2U)
+#define HRTIM_MICR_MCMP3_Msk          (0x1UL << HRTIM_MICR_MCMP3_Pos)          /*!< 0x00000004 */
+#define HRTIM_MICR_MCMP3              HRTIM_MICR_MCMP3_Msk                     /*!< Master compare 3 interrupt flag clear */
+#define HRTIM_MICR_MCMP4_Pos          (3U)
+#define HRTIM_MICR_MCMP4_Msk          (0x1UL << HRTIM_MICR_MCMP4_Pos)          /*!< 0x00000008 */
+#define HRTIM_MICR_MCMP4              HRTIM_MICR_MCMP4_Msk                     /*!< Master compare 4 interrupt flag clear */
+#define HRTIM_MICR_MREP_Pos           (4U)
+#define HRTIM_MICR_MREP_Msk           (0x1UL << HRTIM_MICR_MREP_Pos)           /*!< 0x00000010 */
+#define HRTIM_MICR_MREP               HRTIM_MICR_MREP_Msk                      /*!< Master Repetition interrupt flag clear */
+#define HRTIM_MICR_SYNC_Pos           (5U)
+#define HRTIM_MICR_SYNC_Msk           (0x1UL << HRTIM_MICR_SYNC_Pos)           /*!< 0x00000020 */
+#define HRTIM_MICR_SYNC               HRTIM_MICR_SYNC_Msk                      /*!< Synchronization input interrupt flag clear */
+#define HRTIM_MICR_MUPD_Pos           (6U)
+#define HRTIM_MICR_MUPD_Msk           (0x1UL << HRTIM_MICR_MUPD_Pos)           /*!< 0x00000040 */
+#define HRTIM_MICR_MUPD               HRTIM_MICR_MUPD_Msk                      /*!< Master update interrupt flag clear */
+
+/******************** Master Timer DMA/Interrupt enable register **************/
+#define HRTIM_MDIER_MCMP1IE_Pos       (0U)
+#define HRTIM_MDIER_MCMP1IE_Msk       (0x1UL << HRTIM_MDIER_MCMP1IE_Pos)       /*!< 0x00000001 */
+#define HRTIM_MDIER_MCMP1IE           HRTIM_MDIER_MCMP1IE_Msk                  /*!< Master compare 1 interrupt enable */
+#define HRTIM_MDIER_MCMP2IE_Pos       (1U)
+#define HRTIM_MDIER_MCMP2IE_Msk       (0x1UL << HRTIM_MDIER_MCMP2IE_Pos)       /*!< 0x00000002 */
+#define HRTIM_MDIER_MCMP2IE           HRTIM_MDIER_MCMP2IE_Msk                  /*!< Master compare 2 interrupt enable */
+#define HRTIM_MDIER_MCMP3IE_Pos       (2U)
+#define HRTIM_MDIER_MCMP3IE_Msk       (0x1UL << HRTIM_MDIER_MCMP3IE_Pos)       /*!< 0x00000004 */
+#define HRTIM_MDIER_MCMP3IE           HRTIM_MDIER_MCMP3IE_Msk                  /*!< Master compare 3 interrupt enable */
+#define HRTIM_MDIER_MCMP4IE_Pos       (3U)
+#define HRTIM_MDIER_MCMP4IE_Msk       (0x1UL << HRTIM_MDIER_MCMP4IE_Pos)       /*!< 0x00000008 */
+#define HRTIM_MDIER_MCMP4IE           HRTIM_MDIER_MCMP4IE_Msk                  /*!< Master compare 4 interrupt enable */
+#define HRTIM_MDIER_MREPIE_Pos        (4U)
+#define HRTIM_MDIER_MREPIE_Msk        (0x1UL << HRTIM_MDIER_MREPIE_Pos)        /*!< 0x00000010 */
+#define HRTIM_MDIER_MREPIE            HRTIM_MDIER_MREPIE_Msk                   /*!< Master Repetition interrupt enable */
+#define HRTIM_MDIER_SYNCIE_Pos        (5U)
+#define HRTIM_MDIER_SYNCIE_Msk        (0x1UL << HRTIM_MDIER_SYNCIE_Pos)        /*!< 0x00000020 */
+#define HRTIM_MDIER_SYNCIE            HRTIM_MDIER_SYNCIE_Msk                   /*!< Synchronization input interrupt enable */
+#define HRTIM_MDIER_MUPDIE_Pos        (6U)
+#define HRTIM_MDIER_MUPDIE_Msk        (0x1UL << HRTIM_MDIER_MUPDIE_Pos)        /*!< 0x00000040 */
+#define HRTIM_MDIER_MUPDIE            HRTIM_MDIER_MUPDIE_Msk                   /*!< Master update interrupt enable */
+
+#define HRTIM_MDIER_MCMP1DE_Pos       (16U)
+#define HRTIM_MDIER_MCMP1DE_Msk       (0x1UL << HRTIM_MDIER_MCMP1DE_Pos)       /*!< 0x00010000 */
+#define HRTIM_MDIER_MCMP1DE           HRTIM_MDIER_MCMP1DE_Msk                  /*!< Master compare 1 DMA enable */
+#define HRTIM_MDIER_MCMP2DE_Pos       (17U)
+#define HRTIM_MDIER_MCMP2DE_Msk       (0x1UL << HRTIM_MDIER_MCMP2DE_Pos)       /*!< 0x00020000 */
+#define HRTIM_MDIER_MCMP2DE           HRTIM_MDIER_MCMP2DE_Msk                  /*!< Master compare 2 DMA enable */
+#define HRTIM_MDIER_MCMP3DE_Pos       (18U)
+#define HRTIM_MDIER_MCMP3DE_Msk       (0x1UL << HRTIM_MDIER_MCMP3DE_Pos)       /*!< 0x00040000 */
+#define HRTIM_MDIER_MCMP3DE           HRTIM_MDIER_MCMP3DE_Msk                  /*!< Master compare 3 DMA enable */
+#define HRTIM_MDIER_MCMP4DE_Pos       (19U)
+#define HRTIM_MDIER_MCMP4DE_Msk       (0x1UL << HRTIM_MDIER_MCMP4DE_Pos)       /*!< 0x00080000 */
+#define HRTIM_MDIER_MCMP4DE           HRTIM_MDIER_MCMP4DE_Msk                  /*!< Master compare 4 DMA enable */
+#define HRTIM_MDIER_MREPDE_Pos        (20U)
+#define HRTIM_MDIER_MREPDE_Msk        (0x1UL << HRTIM_MDIER_MREPDE_Pos)        /*!< 0x00100000 */
+#define HRTIM_MDIER_MREPDE            HRTIM_MDIER_MREPDE_Msk                   /*!< Master Repetition DMA enable */
+#define HRTIM_MDIER_SYNCDE_Pos        (21U)
+#define HRTIM_MDIER_SYNCDE_Msk        (0x1UL << HRTIM_MDIER_SYNCDE_Pos)        /*!< 0x00200000 */
+#define HRTIM_MDIER_SYNCDE            HRTIM_MDIER_SYNCDE_Msk                   /*!< Synchronization input DMA enable */
+#define HRTIM_MDIER_MUPDDE_Pos        (22U)
+#define HRTIM_MDIER_MUPDDE_Msk        (0x1UL << HRTIM_MDIER_MUPDDE_Pos)        /*!< 0x00400000 */
+#define HRTIM_MDIER_MUPDDE            HRTIM_MDIER_MUPDDE_Msk                   /*!< Master update DMA enable */
+
+/*******************  Bit definition for HRTIM_MCNTR register  ****************/
+#define HRTIM_MCNTR_MCNTR_Pos         (0U)
+#define HRTIM_MCNTR_MCNTR_Msk         (0xFFFFUL << HRTIM_MCNTR_MCNTR_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_MCNTR_MCNTR             HRTIM_MCNTR_MCNTR_Msk                    /*!<Counter Value */
+
+/*******************  Bit definition for HRTIM_MPER register  *****************/
+#define HRTIM_MPER_MPER_Pos           (0U)
+#define HRTIM_MPER_MPER_Msk           (0xFFFFUL << HRTIM_MPER_MPER_Pos)        /*!< 0x0000FFFF */
+#define HRTIM_MPER_MPER               HRTIM_MPER_MPER_Msk                      /*!< Period Value */
+
+/*******************  Bit definition for HRTIM_MREP register  *****************/
+#define HRTIM_MREP_MREP_Pos           (0U)
+#define HRTIM_MREP_MREP_Msk           (0xFFUL << HRTIM_MREP_MREP_Pos)          /*!< 0x000000FF */
+#define HRTIM_MREP_MREP               HRTIM_MREP_MREP_Msk                      /*!<Repetition Value */
+
+/*******************  Bit definition for HRTIM_MCMP1R register  *****************/
+#define HRTIM_MCMP1R_MCMP1R_Pos       (0U)
+#define HRTIM_MCMP1R_MCMP1R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP1R_Pos)    /*!< 0x0000FFFF */
+#define HRTIM_MCMP1R_MCMP1R           HRTIM_MCMP1R_MCMP1R_Msk                  /*!<Compare Value */
+
+/*******************  Bit definition for HRTIM_MCMP2R register  *****************/
+#define HRTIM_MCMP1R_MCMP2R_Pos       (0U)
+#define HRTIM_MCMP1R_MCMP2R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP2R_Pos)    /*!< 0x0000FFFF */
+#define HRTIM_MCMP1R_MCMP2R           HRTIM_MCMP1R_MCMP2R_Msk                  /*!<Compare Value */
+
+/*******************  Bit definition for HRTIM_MCMP3R register  *****************/
+#define HRTIM_MCMP1R_MCMP3R_Pos       (0U)
+#define HRTIM_MCMP1R_MCMP3R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP3R_Pos)    /*!< 0x0000FFFF */
+#define HRTIM_MCMP1R_MCMP3R           HRTIM_MCMP1R_MCMP3R_Msk                  /*!<Compare Value */
+
+/*******************  Bit definition for HRTIM_MCMP4R register  *****************/
+#define HRTIM_MCMP1R_MCMP4R_Pos       (0U)
+#define HRTIM_MCMP1R_MCMP4R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP4R_Pos)    /*!< 0x0000FFFF */
+#define HRTIM_MCMP1R_MCMP4R           HRTIM_MCMP1R_MCMP4R_Msk                  /*!<Compare Value */
+
+/******************** Slave control register **********************************/
+#define HRTIM_TIMCR_CK_PSC_Pos        (0U)
+#define HRTIM_TIMCR_CK_PSC_Msk        (0x7UL << HRTIM_TIMCR_CK_PSC_Pos)        /*!< 0x00000007 */
+#define HRTIM_TIMCR_CK_PSC            HRTIM_TIMCR_CK_PSC_Msk                   /*!< Slave prescaler mask*/
+#define HRTIM_TIMCR_CK_PSC_0          (0x1UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000001 */
+#define HRTIM_TIMCR_CK_PSC_1          (0x2UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000002 */
+#define HRTIM_TIMCR_CK_PSC_2          (0x4UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000004 */
+
+#define HRTIM_TIMCR_CONT_Pos          (3U)
+#define HRTIM_TIMCR_CONT_Msk          (0x1UL << HRTIM_TIMCR_CONT_Pos)          /*!< 0x00000008 */
+#define HRTIM_TIMCR_CONT              HRTIM_TIMCR_CONT_Msk                     /*!< Slave continuous mode */
+#define HRTIM_TIMCR_RETRIG_Pos        (4U)
+#define HRTIM_TIMCR_RETRIG_Msk        (0x1UL << HRTIM_TIMCR_RETRIG_Pos)        /*!< 0x00000010 */
+#define HRTIM_TIMCR_RETRIG            HRTIM_TIMCR_RETRIG_Msk                   /*!< Slave Retrigreable mode */
+#define HRTIM_TIMCR_HALF_Pos          (5U)
+#define HRTIM_TIMCR_HALF_Msk          (0x1UL << HRTIM_TIMCR_HALF_Pos)          /*!< 0x00000020 */
+#define HRTIM_TIMCR_HALF              HRTIM_TIMCR_HALF_Msk                     /*!< Slave Half mode */
+#define HRTIM_TIMCR_PSHPLL_Pos        (6U)
+#define HRTIM_TIMCR_PSHPLL_Msk        (0x1UL << HRTIM_TIMCR_PSHPLL_Pos)        /*!< 0x00000040 */
+#define HRTIM_TIMCR_PSHPLL            HRTIM_TIMCR_PSHPLL_Msk                   /*!< Slave push-pull mode */
+
+#define HRTIM_TIMCR_SYNCRST_Pos       (10U)
+#define HRTIM_TIMCR_SYNCRST_Msk       (0x1UL << HRTIM_TIMCR_SYNCRST_Pos)       /*!< 0x00000400 */
+#define HRTIM_TIMCR_SYNCRST           HRTIM_TIMCR_SYNCRST_Msk                  /*!< Slave synchronization resets */
+#define HRTIM_TIMCR_SYNCSTRT_Pos      (11U)
+#define HRTIM_TIMCR_SYNCSTRT_Msk      (0x1UL << HRTIM_TIMCR_SYNCSTRT_Pos)      /*!< 0x00000800 */
+#define HRTIM_TIMCR_SYNCSTRT          HRTIM_TIMCR_SYNCSTRT_Msk                 /*!< Slave synchronization starts */
+
+#define HRTIM_TIMCR_DELCMP2_Pos       (12U)
+#define HRTIM_TIMCR_DELCMP2_Msk       (0x3UL << HRTIM_TIMCR_DELCMP2_Pos)       /*!< 0x00003000 */
+#define HRTIM_TIMCR_DELCMP2           HRTIM_TIMCR_DELCMP2_Msk                  /*!< Slave delayed compartor 2 mode mask */
+#define HRTIM_TIMCR_DELCMP2_0         (0x1UL << HRTIM_TIMCR_DELCMP2_Pos)        /*!< 0x00001000 */
+#define HRTIM_TIMCR_DELCMP2_1         (0x2UL << HRTIM_TIMCR_DELCMP2_Pos)        /*!< 0x00002000 */
+#define HRTIM_TIMCR_DELCMP4_Pos       (14U)
+#define HRTIM_TIMCR_DELCMP4_Msk       (0x3UL << HRTIM_TIMCR_DELCMP4_Pos)       /*!< 0x0000C000 */
+#define HRTIM_TIMCR_DELCMP4           HRTIM_TIMCR_DELCMP4_Msk                  /*!< Slave delayed compartor 4 mode mask */
+#define HRTIM_TIMCR_DELCMP4_0         (0x1UL << HRTIM_TIMCR_DELCMP4_Pos)        /*!< 0x00004000 */
+#define HRTIM_TIMCR_DELCMP4_1         (0x2UL << HRTIM_TIMCR_DELCMP4_Pos)        /*!< 0x00008000 */
+
+#define HRTIM_TIMCR_TREPU_Pos         (17U)
+#define HRTIM_TIMCR_TREPU_Msk         (0x1UL << HRTIM_TIMCR_TREPU_Pos)         /*!< 0x00020000 */
+#define HRTIM_TIMCR_TREPU             HRTIM_TIMCR_TREPU_Msk                    /*!< Slave repetition update */
+#define HRTIM_TIMCR_TRSTU_Pos         (18U)
+#define HRTIM_TIMCR_TRSTU_Msk         (0x1UL << HRTIM_TIMCR_TRSTU_Pos)         /*!< 0x00040000 */
+#define HRTIM_TIMCR_TRSTU             HRTIM_TIMCR_TRSTU_Msk                    /*!< Slave reset update */
+#define HRTIM_TIMCR_TAU_Pos           (19U)
+#define HRTIM_TIMCR_TAU_Msk           (0x1UL << HRTIM_TIMCR_TAU_Pos)           /*!< 0x00080000 */
+#define HRTIM_TIMCR_TAU               HRTIM_TIMCR_TAU_Msk                      /*!< Slave Timer A update reserved for TIM A */
+#define HRTIM_TIMCR_TBU_Pos           (20U)
+#define HRTIM_TIMCR_TBU_Msk           (0x1UL << HRTIM_TIMCR_TBU_Pos)           /*!< 0x00100000 */
+#define HRTIM_TIMCR_TBU               HRTIM_TIMCR_TBU_Msk                      /*!< Slave Timer B update reserved for TIM B */
+#define HRTIM_TIMCR_TCU_Pos           (21U)
+#define HRTIM_TIMCR_TCU_Msk           (0x1UL << HRTIM_TIMCR_TCU_Pos)           /*!< 0x00200000 */
+#define HRTIM_TIMCR_TCU               HRTIM_TIMCR_TCU_Msk                      /*!< Slave Timer C update reserved for TIM C */
+#define HRTIM_TIMCR_TDU_Pos           (22U)
+#define HRTIM_TIMCR_TDU_Msk           (0x1UL << HRTIM_TIMCR_TDU_Pos)           /*!< 0x00400000 */
+#define HRTIM_TIMCR_TDU               HRTIM_TIMCR_TDU_Msk                      /*!< Slave Timer D update reserved for TIM D */
+#define HRTIM_TIMCR_TEU_Pos           (23U)
+#define HRTIM_TIMCR_TEU_Msk           (0x1UL << HRTIM_TIMCR_TEU_Pos)           /*!< 0x00800000 */
+#define HRTIM_TIMCR_TEU               HRTIM_TIMCR_TEU_Msk                      /*!< Slave Timer E update reserved for TIM E */
+#define HRTIM_TIMCR_MSTU_Pos          (24U)
+#define HRTIM_TIMCR_MSTU_Msk          (0x1UL << HRTIM_TIMCR_MSTU_Pos)          /*!< 0x01000000 */
+#define HRTIM_TIMCR_MSTU              HRTIM_TIMCR_MSTU_Msk                     /*!< Master Update */
+
+#define HRTIM_TIMCR_DACSYNC_Pos       (25U)
+#define HRTIM_TIMCR_DACSYNC_Msk       (0x3UL << HRTIM_TIMCR_DACSYNC_Pos)       /*!< 0x06000000 */
+#define HRTIM_TIMCR_DACSYNC           HRTIM_TIMCR_DACSYNC_Msk                  /*!< DAC sychronization mask */
+#define HRTIM_TIMCR_DACSYNC_0         (0x1UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x02000000 */
+#define HRTIM_TIMCR_DACSYNC_1         (0x2UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x04000000 */
+#define HRTIM_TIMCR_PREEN_Pos         (27U)
+#define HRTIM_TIMCR_PREEN_Msk         (0x1UL << HRTIM_TIMCR_PREEN_Pos)         /*!< 0x08000000 */
+#define HRTIM_TIMCR_PREEN             HRTIM_TIMCR_PREEN_Msk                    /*!< Slave preload enable */
+
+#define HRTIM_TIMCR_UPDGAT_Pos        (28U)
+#define HRTIM_TIMCR_UPDGAT_Msk        (0xFUL << HRTIM_TIMCR_UPDGAT_Pos)        /*!< 0xF0000000 */
+#define HRTIM_TIMCR_UPDGAT            HRTIM_TIMCR_UPDGAT_Msk                   /*!< Slave update gating mask */
+#define HRTIM_TIMCR_UPDGAT_0          (0x1UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x10000000 */
+#define HRTIM_TIMCR_UPDGAT_1          (0x2UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x20000000 */
+#define HRTIM_TIMCR_UPDGAT_2          (0x4UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x40000000 */
+#define HRTIM_TIMCR_UPDGAT_3          (0x8UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x80000000 */
+
+/******************** Slave Interrupt status register **************************/
+#define HRTIM_TIMISR_CMP1_Pos         (0U)
+#define HRTIM_TIMISR_CMP1_Msk         (0x1UL << HRTIM_TIMISR_CMP1_Pos)         /*!< 0x00000001 */
+#define HRTIM_TIMISR_CMP1             HRTIM_TIMISR_CMP1_Msk                    /*!< Slave compare 1 interrupt flag */
+#define HRTIM_TIMISR_CMP2_Pos         (1U)
+#define HRTIM_TIMISR_CMP2_Msk         (0x1UL << HRTIM_TIMISR_CMP2_Pos)         /*!< 0x00000002 */
+#define HRTIM_TIMISR_CMP2             HRTIM_TIMISR_CMP2_Msk                    /*!< Slave compare 2 interrupt flag */
+#define HRTIM_TIMISR_CMP3_Pos         (2U)
+#define HRTIM_TIMISR_CMP3_Msk         (0x1UL << HRTIM_TIMISR_CMP3_Pos)         /*!< 0x00000004 */
+#define HRTIM_TIMISR_CMP3             HRTIM_TIMISR_CMP3_Msk                    /*!< Slave compare 3 interrupt flag */
+#define HRTIM_TIMISR_CMP4_Pos         (3U)
+#define HRTIM_TIMISR_CMP4_Msk         (0x1UL << HRTIM_TIMISR_CMP4_Pos)         /*!< 0x00000008 */
+#define HRTIM_TIMISR_CMP4             HRTIM_TIMISR_CMP4_Msk                    /*!< Slave compare 4 interrupt flag */
+#define HRTIM_TIMISR_REP_Pos          (4U)
+#define HRTIM_TIMISR_REP_Msk          (0x1UL << HRTIM_TIMISR_REP_Pos)          /*!< 0x00000010 */
+#define HRTIM_TIMISR_REP              HRTIM_TIMISR_REP_Msk                     /*!< Slave repetition interrupt flag */
+#define HRTIM_TIMISR_UPD_Pos          (6U)
+#define HRTIM_TIMISR_UPD_Msk          (0x1UL << HRTIM_TIMISR_UPD_Pos)          /*!< 0x00000040 */
+#define HRTIM_TIMISR_UPD              HRTIM_TIMISR_UPD_Msk                     /*!< Slave update interrupt flag */
+#define HRTIM_TIMISR_CPT1_Pos         (7U)
+#define HRTIM_TIMISR_CPT1_Msk         (0x1UL << HRTIM_TIMISR_CPT1_Pos)         /*!< 0x00000080 */
+#define HRTIM_TIMISR_CPT1             HRTIM_TIMISR_CPT1_Msk                    /*!< Slave capture 1 interrupt flag */
+#define HRTIM_TIMISR_CPT2_Pos         (8U)
+#define HRTIM_TIMISR_CPT2_Msk         (0x1UL << HRTIM_TIMISR_CPT2_Pos)         /*!< 0x00000100 */
+#define HRTIM_TIMISR_CPT2             HRTIM_TIMISR_CPT2_Msk                    /*!< Slave capture 2 interrupt flag */
+#define HRTIM_TIMISR_SET1_Pos         (9U)
+#define HRTIM_TIMISR_SET1_Msk         (0x1UL << HRTIM_TIMISR_SET1_Pos)         /*!< 0x00000200 */
+#define HRTIM_TIMISR_SET1             HRTIM_TIMISR_SET1_Msk                    /*!< Slave output 1 set interrupt flag */
+#define HRTIM_TIMISR_RST1_Pos         (10U)
+#define HRTIM_TIMISR_RST1_Msk         (0x1UL << HRTIM_TIMISR_RST1_Pos)         /*!< 0x00000400 */
+#define HRTIM_TIMISR_RST1             HRTIM_TIMISR_RST1_Msk                    /*!< Slave output 1 reset interrupt flag */
+#define HRTIM_TIMISR_SET2_Pos         (11U)
+#define HRTIM_TIMISR_SET2_Msk         (0x1UL << HRTIM_TIMISR_SET2_Pos)         /*!< 0x00000800 */
+#define HRTIM_TIMISR_SET2             HRTIM_TIMISR_SET2_Msk                    /*!< Slave output 2 set interrupt flag */
+#define HRTIM_TIMISR_RST2_Pos         (12U)
+#define HRTIM_TIMISR_RST2_Msk         (0x1UL << HRTIM_TIMISR_RST2_Pos)         /*!< 0x00001000 */
+#define HRTIM_TIMISR_RST2             HRTIM_TIMISR_RST2_Msk                    /*!< Slave output 2 reset interrupt flag */
+#define HRTIM_TIMISR_RST_Pos          (13U)
+#define HRTIM_TIMISR_RST_Msk          (0x1UL << HRTIM_TIMISR_RST_Pos)          /*!< 0x00002000 */
+#define HRTIM_TIMISR_RST              HRTIM_TIMISR_RST_Msk                     /*!< Slave reset interrupt flag */
+#define HRTIM_TIMISR_DLYPRT_Pos       (14U)
+#define HRTIM_TIMISR_DLYPRT_Msk       (0x1UL << HRTIM_TIMISR_DLYPRT_Pos)       /*!< 0x00004000 */
+#define HRTIM_TIMISR_DLYPRT           HRTIM_TIMISR_DLYPRT_Msk                  /*!< Slave output 1 delay protection interrupt flag */
+#define HRTIM_TIMISR_CPPSTAT_Pos      (16U)
+#define HRTIM_TIMISR_CPPSTAT_Msk      (0x1UL << HRTIM_TIMISR_CPPSTAT_Pos)      /*!< 0x00010000 */
+#define HRTIM_TIMISR_CPPSTAT          HRTIM_TIMISR_CPPSTAT_Msk                 /*!< Slave current push-pull flag */
+#define HRTIM_TIMISR_IPPSTAT_Pos      (17U)
+#define HRTIM_TIMISR_IPPSTAT_Msk      (0x1UL << HRTIM_TIMISR_IPPSTAT_Pos)      /*!< 0x00020000 */
+#define HRTIM_TIMISR_IPPSTAT          HRTIM_TIMISR_IPPSTAT_Msk                 /*!< Slave idle push-pull flag */
+#define HRTIM_TIMISR_O1STAT_Pos       (18U)
+#define HRTIM_TIMISR_O1STAT_Msk       (0x1UL << HRTIM_TIMISR_O1STAT_Pos)       /*!< 0x00040000 */
+#define HRTIM_TIMISR_O1STAT           HRTIM_TIMISR_O1STAT_Msk                  /*!< Slave output 1 state flag */
+#define HRTIM_TIMISR_O2STAT_Pos       (19U)
+#define HRTIM_TIMISR_O2STAT_Msk       (0x1UL << HRTIM_TIMISR_O2STAT_Pos)       /*!< 0x00080000 */
+#define HRTIM_TIMISR_O2STAT           HRTIM_TIMISR_O2STAT_Msk                  /*!< Slave output 2 state flag */
+#define HRTIM_TIMISR_O1CPY_Pos        (20U)
+#define HRTIM_TIMISR_O1CPY_Msk        (0x1UL << HRTIM_TIMISR_O1CPY_Pos)        /*!< 0x00100000 */
+#define HRTIM_TIMISR_O1CPY            HRTIM_TIMISR_O1CPY_Msk                   /*!< Slave output 1 copy flag */
+#define HRTIM_TIMISR_O2CPY_Pos        (21U)
+#define HRTIM_TIMISR_O2CPY_Msk        (0x1UL << HRTIM_TIMISR_O2CPY_Pos)        /*!< 0x00200000 */
+#define HRTIM_TIMISR_O2CPY            HRTIM_TIMISR_O2CPY_Msk                   /*!< Slave output 2 copy flag */
+
+/******************** Slave Interrupt clear register **************************/
+#define HRTIM_TIMICR_CMP1C_Pos        (0U)
+#define HRTIM_TIMICR_CMP1C_Msk        (0x1UL << HRTIM_TIMICR_CMP1C_Pos)        /*!< 0x00000001 */
+#define HRTIM_TIMICR_CMP1C            HRTIM_TIMICR_CMP1C_Msk                   /*!< Slave compare 1 clear flag */
+#define HRTIM_TIMICR_CMP2C_Pos        (1U)
+#define HRTIM_TIMICR_CMP2C_Msk        (0x1UL << HRTIM_TIMICR_CMP2C_Pos)        /*!< 0x00000002 */
+#define HRTIM_TIMICR_CMP2C            HRTIM_TIMICR_CMP2C_Msk                   /*!< Slave compare 2 clear flag */
+#define HRTIM_TIMICR_CMP3C_Pos        (2U)
+#define HRTIM_TIMICR_CMP3C_Msk        (0x1UL << HRTIM_TIMICR_CMP3C_Pos)        /*!< 0x00000004 */
+#define HRTIM_TIMICR_CMP3C            HRTIM_TIMICR_CMP3C_Msk                   /*!< Slave compare 3 clear flag */
+#define HRTIM_TIMICR_CMP4C_Pos        (3U)
+#define HRTIM_TIMICR_CMP4C_Msk        (0x1UL << HRTIM_TIMICR_CMP4C_Pos)        /*!< 0x00000008 */
+#define HRTIM_TIMICR_CMP4C            HRTIM_TIMICR_CMP4C_Msk                   /*!< Slave compare 4 clear flag */
+#define HRTIM_TIMICR_REPC_Pos         (4U)
+#define HRTIM_TIMICR_REPC_Msk         (0x1UL << HRTIM_TIMICR_REPC_Pos)         /*!< 0x00000010 */
+#define HRTIM_TIMICR_REPC             HRTIM_TIMICR_REPC_Msk                    /*!< Slave repetition clear flag */
+#define HRTIM_TIMICR_UPDC_Pos         (6U)
+#define HRTIM_TIMICR_UPDC_Msk         (0x1UL << HRTIM_TIMICR_UPDC_Pos)         /*!< 0x00000040 */
+#define HRTIM_TIMICR_UPDC             HRTIM_TIMICR_UPDC_Msk                    /*!< Slave update clear flag */
+#define HRTIM_TIMICR_CPT1C_Pos        (7U)
+#define HRTIM_TIMICR_CPT1C_Msk        (0x1UL << HRTIM_TIMICR_CPT1C_Pos)        /*!< 0x00000080 */
+#define HRTIM_TIMICR_CPT1C            HRTIM_TIMICR_CPT1C_Msk                   /*!< Slave capture 1 clear flag */
+#define HRTIM_TIMICR_CPT2C_Pos        (8U)
+#define HRTIM_TIMICR_CPT2C_Msk        (0x1UL << HRTIM_TIMICR_CPT2C_Pos)        /*!< 0x00000100 */
+#define HRTIM_TIMICR_CPT2C            HRTIM_TIMICR_CPT2C_Msk                   /*!< Slave capture 2 clear flag */
+#define HRTIM_TIMICR_SET1C_Pos        (9U)
+#define HRTIM_TIMICR_SET1C_Msk        (0x1UL << HRTIM_TIMICR_SET1C_Pos)        /*!< 0x00000200 */
+#define HRTIM_TIMICR_SET1C            HRTIM_TIMICR_SET1C_Msk                   /*!< Slave output 1 set clear flag */
+#define HRTIM_TIMICR_RST1C_Pos        (10U)
+#define HRTIM_TIMICR_RST1C_Msk        (0x1UL << HRTIM_TIMICR_RST1C_Pos)        /*!< 0x00000400 */
+#define HRTIM_TIMICR_RST1C            HRTIM_TIMICR_RST1C_Msk                   /*!< Slave output 1 reset clear flag */
+#define HRTIM_TIMICR_SET2C_Pos        (11U)
+#define HRTIM_TIMICR_SET2C_Msk        (0x1UL << HRTIM_TIMICR_SET2C_Pos)        /*!< 0x00000800 */
+#define HRTIM_TIMICR_SET2C            HRTIM_TIMICR_SET2C_Msk                   /*!< Slave output 2 set clear flag */
+#define HRTIM_TIMICR_RST2C_Pos        (12U)
+#define HRTIM_TIMICR_RST2C_Msk        (0x1UL << HRTIM_TIMICR_RST2C_Pos)        /*!< 0x00001000 */
+#define HRTIM_TIMICR_RST2C            HRTIM_TIMICR_RST2C_Msk                   /*!< Slave output 2 reset clear flag */
+#define HRTIM_TIMICR_RSTC_Pos         (13U)
+#define HRTIM_TIMICR_RSTC_Msk         (0x1UL << HRTIM_TIMICR_RSTC_Pos)         /*!< 0x00002000 */
+#define HRTIM_TIMICR_RSTC             HRTIM_TIMICR_RSTC_Msk                    /*!< Slave reset clear flag */
+#define HRTIM_TIMICR_DLYPRTC_Pos      (14U)
+#define HRTIM_TIMICR_DLYPRTC_Msk      (0x1UL << HRTIM_TIMICR_DLYPRTC_Pos)      /*!< 0x00004000 */
+#define HRTIM_TIMICR_DLYPRTC          HRTIM_TIMICR_DLYPRTC_Msk                 /*!< Slave output 1 delay protection clear flag */
+
+/******************** Slave DMA/Interrupt enable register *********************/
+#define HRTIM_TIMDIER_CMP1IE_Pos      (0U)
+#define HRTIM_TIMDIER_CMP1IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP1IE_Pos)      /*!< 0x00000001 */
+#define HRTIM_TIMDIER_CMP1IE          HRTIM_TIMDIER_CMP1IE_Msk                 /*!< Slave compare 1 interrupt enable */
+#define HRTIM_TIMDIER_CMP2IE_Pos      (1U)
+#define HRTIM_TIMDIER_CMP2IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP2IE_Pos)      /*!< 0x00000002 */
+#define HRTIM_TIMDIER_CMP2IE          HRTIM_TIMDIER_CMP2IE_Msk                 /*!< Slave compare 2 interrupt enable */
+#define HRTIM_TIMDIER_CMP3IE_Pos      (2U)
+#define HRTIM_TIMDIER_CMP3IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP3IE_Pos)      /*!< 0x00000004 */
+#define HRTIM_TIMDIER_CMP3IE          HRTIM_TIMDIER_CMP3IE_Msk                 /*!< Slave compare 3 interrupt enable */
+#define HRTIM_TIMDIER_CMP4IE_Pos      (3U)
+#define HRTIM_TIMDIER_CMP4IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP4IE_Pos)      /*!< 0x00000008 */
+#define HRTIM_TIMDIER_CMP4IE          HRTIM_TIMDIER_CMP4IE_Msk                 /*!< Slave compare 4 interrupt enable */
+#define HRTIM_TIMDIER_REPIE_Pos       (4U)
+#define HRTIM_TIMDIER_REPIE_Msk       (0x1UL << HRTIM_TIMDIER_REPIE_Pos)       /*!< 0x00000010 */
+#define HRTIM_TIMDIER_REPIE           HRTIM_TIMDIER_REPIE_Msk                  /*!< Slave repetition interrupt enable */
+#define HRTIM_TIMDIER_UPDIE_Pos       (6U)
+#define HRTIM_TIMDIER_UPDIE_Msk       (0x1UL << HRTIM_TIMDIER_UPDIE_Pos)       /*!< 0x00000040 */
+#define HRTIM_TIMDIER_UPDIE           HRTIM_TIMDIER_UPDIE_Msk                  /*!< Slave update interrupt enable */
+#define HRTIM_TIMDIER_CPT1IE_Pos      (7U)
+#define HRTIM_TIMDIER_CPT1IE_Msk      (0x1UL << HRTIM_TIMDIER_CPT1IE_Pos)      /*!< 0x00000080 */
+#define HRTIM_TIMDIER_CPT1IE          HRTIM_TIMDIER_CPT1IE_Msk                 /*!< Slave capture 1 interrupt enable */
+#define HRTIM_TIMDIER_CPT2IE_Pos      (8U)
+#define HRTIM_TIMDIER_CPT2IE_Msk      (0x1UL << HRTIM_TIMDIER_CPT2IE_Pos)      /*!< 0x00000100 */
+#define HRTIM_TIMDIER_CPT2IE          HRTIM_TIMDIER_CPT2IE_Msk                 /*!< Slave capture 2 interrupt enable */
+#define HRTIM_TIMDIER_SET1IE_Pos      (9U)
+#define HRTIM_TIMDIER_SET1IE_Msk      (0x1UL << HRTIM_TIMDIER_SET1IE_Pos)      /*!< 0x00000200 */
+#define HRTIM_TIMDIER_SET1IE          HRTIM_TIMDIER_SET1IE_Msk                 /*!< Slave output 1 set interrupt enable */
+#define HRTIM_TIMDIER_RST1IE_Pos      (10U)
+#define HRTIM_TIMDIER_RST1IE_Msk      (0x1UL << HRTIM_TIMDIER_RST1IE_Pos)      /*!< 0x00000400 */
+#define HRTIM_TIMDIER_RST1IE          HRTIM_TIMDIER_RST1IE_Msk                 /*!< Slave output 1 reset interrupt enable */
+#define HRTIM_TIMDIER_SET2IE_Pos      (11U)
+#define HRTIM_TIMDIER_SET2IE_Msk      (0x1UL << HRTIM_TIMDIER_SET2IE_Pos)      /*!< 0x00000800 */
+#define HRTIM_TIMDIER_SET2IE          HRTIM_TIMDIER_SET2IE_Msk                 /*!< Slave output 2 set interrupt enable */
+#define HRTIM_TIMDIER_RST2IE_Pos      (12U)
+#define HRTIM_TIMDIER_RST2IE_Msk      (0x1UL << HRTIM_TIMDIER_RST2IE_Pos)      /*!< 0x00001000 */
+#define HRTIM_TIMDIER_RST2IE          HRTIM_TIMDIER_RST2IE_Msk                 /*!< Slave output 2 reset interrupt enable */
+#define HRTIM_TIMDIER_RSTIE_Pos       (13U)
+#define HRTIM_TIMDIER_RSTIE_Msk       (0x1UL << HRTIM_TIMDIER_RSTIE_Pos)       /*!< 0x00002000 */
+#define HRTIM_TIMDIER_RSTIE           HRTIM_TIMDIER_RSTIE_Msk                  /*!< Slave reset interrupt enable */
+#define HRTIM_TIMDIER_DLYPRTIE_Pos    (14U)
+#define HRTIM_TIMDIER_DLYPRTIE_Msk    (0x1UL << HRTIM_TIMDIER_DLYPRTIE_Pos)    /*!< 0x00004000 */
+#define HRTIM_TIMDIER_DLYPRTIE        HRTIM_TIMDIER_DLYPRTIE_Msk               /*!< Slave delay protection interrupt enable */
+
+#define HRTIM_TIMDIER_CMP1DE_Pos      (16U)
+#define HRTIM_TIMDIER_CMP1DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP1DE_Pos)      /*!< 0x00010000 */
+#define HRTIM_TIMDIER_CMP1DE          HRTIM_TIMDIER_CMP1DE_Msk                 /*!< Slave compare 1 request enable */
+#define HRTIM_TIMDIER_CMP2DE_Pos      (17U)
+#define HRTIM_TIMDIER_CMP2DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP2DE_Pos)      /*!< 0x00020000 */
+#define HRTIM_TIMDIER_CMP2DE          HRTIM_TIMDIER_CMP2DE_Msk                 /*!< Slave compare 2 request enable */
+#define HRTIM_TIMDIER_CMP3DE_Pos      (18U)
+#define HRTIM_TIMDIER_CMP3DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP3DE_Pos)      /*!< 0x00040000 */
+#define HRTIM_TIMDIER_CMP3DE          HRTIM_TIMDIER_CMP3DE_Msk                 /*!< Slave compare 3 request enable */
+#define HRTIM_TIMDIER_CMP4DE_Pos      (19U)
+#define HRTIM_TIMDIER_CMP4DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP4DE_Pos)      /*!< 0x00080000 */
+#define HRTIM_TIMDIER_CMP4DE          HRTIM_TIMDIER_CMP4DE_Msk                 /*!< Slave compare 4 request enable */
+#define HRTIM_TIMDIER_REPDE_Pos       (20U)
+#define HRTIM_TIMDIER_REPDE_Msk       (0x1UL << HRTIM_TIMDIER_REPDE_Pos)       /*!< 0x00100000 */
+#define HRTIM_TIMDIER_REPDE           HRTIM_TIMDIER_REPDE_Msk                  /*!< Slave repetition request enable */
+#define HRTIM_TIMDIER_UPDDE_Pos       (22U)
+#define HRTIM_TIMDIER_UPDDE_Msk       (0x1UL << HRTIM_TIMDIER_UPDDE_Pos)       /*!< 0x00400000 */
+#define HRTIM_TIMDIER_UPDDE           HRTIM_TIMDIER_UPDDE_Msk                  /*!< Slave update request enable */
+#define HRTIM_TIMDIER_CPT1DE_Pos      (23U)
+#define HRTIM_TIMDIER_CPT1DE_Msk      (0x1UL << HRTIM_TIMDIER_CPT1DE_Pos)      /*!< 0x00800000 */
+#define HRTIM_TIMDIER_CPT1DE          HRTIM_TIMDIER_CPT1DE_Msk                 /*!< Slave capture 1 request enable */
+#define HRTIM_TIMDIER_CPT2DE_Pos      (24U)
+#define HRTIM_TIMDIER_CPT2DE_Msk      (0x1UL << HRTIM_TIMDIER_CPT2DE_Pos)      /*!< 0x01000000 */
+#define HRTIM_TIMDIER_CPT2DE          HRTIM_TIMDIER_CPT2DE_Msk                 /*!< Slave capture 2 request enable */
+#define HRTIM_TIMDIER_SET1DE_Pos      (25U)
+#define HRTIM_TIMDIER_SET1DE_Msk      (0x1UL << HRTIM_TIMDIER_SET1DE_Pos)      /*!< 0x02000000 */
+#define HRTIM_TIMDIER_SET1DE          HRTIM_TIMDIER_SET1DE_Msk                 /*!< Slave output 1 set request enable */
+#define HRTIM_TIMDIER_RST1DE_Pos      (26U)
+#define HRTIM_TIMDIER_RST1DE_Msk      (0x1UL << HRTIM_TIMDIER_RST1DE_Pos)      /*!< 0x04000000 */
+#define HRTIM_TIMDIER_RST1DE          HRTIM_TIMDIER_RST1DE_Msk                 /*!< Slave output 1 reset request enable */
+#define HRTIM_TIMDIER_SET2DE_Pos      (27U)
+#define HRTIM_TIMDIER_SET2DE_Msk      (0x1UL << HRTIM_TIMDIER_SET2DE_Pos)      /*!< 0x08000000 */
+#define HRTIM_TIMDIER_SET2DE          HRTIM_TIMDIER_SET2DE_Msk                 /*!< Slave output 2 set request enable */
+#define HRTIM_TIMDIER_RST2DE_Pos      (28U)
+#define HRTIM_TIMDIER_RST2DE_Msk      (0x1UL << HRTIM_TIMDIER_RST2DE_Pos)      /*!< 0x10000000 */
+#define HRTIM_TIMDIER_RST2DE          HRTIM_TIMDIER_RST2DE_Msk                 /*!< Slave output 2 reset request enable */
+#define HRTIM_TIMDIER_RSTDE_Pos       (29U)
+#define HRTIM_TIMDIER_RSTDE_Msk       (0x1UL << HRTIM_TIMDIER_RSTDE_Pos)       /*!< 0x20000000 */
+#define HRTIM_TIMDIER_RSTDE           HRTIM_TIMDIER_RSTDE_Msk                  /*!< Slave reset request enable */
+#define HRTIM_TIMDIER_DLYPRTDE_Pos    (30U)
+#define HRTIM_TIMDIER_DLYPRTDE_Msk    (0x1UL << HRTIM_TIMDIER_DLYPRTDE_Pos)    /*!< 0x40000000 */
+#define HRTIM_TIMDIER_DLYPRTDE        HRTIM_TIMDIER_DLYPRTDE_Msk               /*!< Slavedelay protection request enable */
+
+/******************  Bit definition for HRTIM_CNTR register  ****************/
+#define HRTIM_CNTR_CNTR_Pos           (0U)
+#define HRTIM_CNTR_CNTR_Msk           (0xFFFFUL << HRTIM_CNTR_CNTR_Pos)        /*!< 0x0000FFFF */
+#define HRTIM_CNTR_CNTR               HRTIM_CNTR_CNTR_Msk                      /*!< Counter Value */
+
+/*******************  Bit definition for HRTIM_PER register  *****************/
+#define HRTIM_PER_PER_Pos             (0U)
+#define HRTIM_PER_PER_Msk             (0xFFFFUL << HRTIM_PER_PER_Pos)          /*!< 0x0000FFFF */
+#define HRTIM_PER_PER                 HRTIM_PER_PER_Msk                        /*!< Period Value */
+
+/*******************  Bit definition for HRTIM_REP register  *****************/
+#define HRTIM_REP_REP_Pos             (0U)
+#define HRTIM_REP_REP_Msk             (0xFFUL << HRTIM_REP_REP_Pos)            /*!< 0x000000FF */
+#define HRTIM_REP_REP                 HRTIM_REP_REP_Msk                        /*!< Repetition Value */
+
+/*******************  Bit definition for HRTIM_CMP1R register  *****************/
+#define HRTIM_CMP1R_CMP1R_Pos         (0U)
+#define HRTIM_CMP1R_CMP1R_Msk         (0xFFFFUL << HRTIM_CMP1R_CMP1R_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_CMP1R_CMP1R             HRTIM_CMP1R_CMP1R_Msk                    /*!< Compare Value */
+
+/*******************  Bit definition for HRTIM_CMP1CR register  *****************/
+#define HRTIM_CMP1CR_CMP1CR_Pos       (0U)
+#define HRTIM_CMP1CR_CMP1CR_Msk       (0xFFFFFFFFUL << HRTIM_CMP1CR_CMP1CR_Pos) /*!< 0xFFFFFFFF */
+#define HRTIM_CMP1CR_CMP1CR           HRTIM_CMP1CR_CMP1CR_Msk                  /*!< Compare Value */
+
+/*******************  Bit definition for HRTIM_CMP2R register  *****************/
+#define HRTIM_CMP2R_CMP2R_Pos         (0U)
+#define HRTIM_CMP2R_CMP2R_Msk         (0xFFFFUL << HRTIM_CMP2R_CMP2R_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_CMP2R_CMP2R             HRTIM_CMP2R_CMP2R_Msk                    /*!< Compare Value */
+
+/*******************  Bit definition for HRTIM_CMP3R register  *****************/
+#define HRTIM_CMP3R_CMP3R_Pos         (0U)
+#define HRTIM_CMP3R_CMP3R_Msk         (0xFFFFUL << HRTIM_CMP3R_CMP3R_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_CMP3R_CMP3R             HRTIM_CMP3R_CMP3R_Msk                    /*!< Compare Value */
+
+/*******************  Bit definition for HRTIM_CMP4R register  *****************/
+#define HRTIM_CMP4R_CMP4R_Pos         (0U)
+#define HRTIM_CMP4R_CMP4R_Msk         (0xFFFFUL << HRTIM_CMP4R_CMP4R_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_CMP4R_CMP4R             HRTIM_CMP4R_CMP4R_Msk                    /*!< Compare Value */
+
+/*******************  Bit definition for HRTIM_CPT1R register  ****************/
+#define HRTIM_CPT1R_CPT1R_Pos         (0U)
+#define HRTIM_CPT1R_CPT1R_Msk         (0xFFFFUL << HRTIM_CPT1R_CPT1R_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_CPT1R_CPT1R             HRTIM_CPT1R_CPT1R_Msk                    /*!< Capture Value */
+
+/*******************  Bit definition for HRTIM_CPT2R register  ****************/
+#define HRTIM_CPT2R_CPT2R_Pos         (0U)
+#define HRTIM_CPT2R_CPT2R_Msk         (0xFFFFUL << HRTIM_CPT2R_CPT2R_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_CPT2R_CPT2R             HRTIM_CPT2R_CPT2R_Msk                    /*!< Capture Value */
+
+/******************** Bit definition for Slave Deadtime register **************/
+#define HRTIM_DTR_DTR_Pos             (0U)
+#define HRTIM_DTR_DTR_Msk             (0x1FFUL << HRTIM_DTR_DTR_Pos)           /*!< 0x000001FF */
+#define HRTIM_DTR_DTR                 HRTIM_DTR_DTR_Msk                        /*!< Dead time rising value */
+#define HRTIM_DTR_DTR_0               (0x001UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000001 */
+#define HRTIM_DTR_DTR_1               (0x002UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000002 */
+#define HRTIM_DTR_DTR_2               (0x004UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000004 */
+#define HRTIM_DTR_DTR_3               (0x008UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000008 */
+#define HRTIM_DTR_DTR_4               (0x010UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000010 */
+#define HRTIM_DTR_DTR_5               (0x020UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000020 */
+#define HRTIM_DTR_DTR_6               (0x040UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000040 */
+#define HRTIM_DTR_DTR_7               (0x080UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000080 */
+#define HRTIM_DTR_DTR_8               (0x100UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000100 */
+#define HRTIM_DTR_SDTR_Pos            (9U)
+#define HRTIM_DTR_SDTR_Msk            (0x1UL << HRTIM_DTR_SDTR_Pos)            /*!< 0x00000200 */
+#define HRTIM_DTR_SDTR                HRTIM_DTR_SDTR_Msk                       /*!< Sign dead time rising value */
+#define HRTIM_DTR_DTPRSC_Pos          (10U)
+#define HRTIM_DTR_DTPRSC_Msk          (0x7UL << HRTIM_DTR_DTPRSC_Pos)          /*!< 0x00001C00 */
+#define HRTIM_DTR_DTPRSC              HRTIM_DTR_DTPRSC_Msk                     /*!< Dead time prescaler */
+#define HRTIM_DTR_DTPRSC_0            (0x1UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00000400 */
+#define HRTIM_DTR_DTPRSC_1            (0x2UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00000800 */
+#define HRTIM_DTR_DTPRSC_2            (0x4UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00001000 */
+#define HRTIM_DTR_DTRSLK_Pos          (14U)
+#define HRTIM_DTR_DTRSLK_Msk          (0x1UL << HRTIM_DTR_DTRSLK_Pos)          /*!< 0x00004000 */
+#define HRTIM_DTR_DTRSLK              HRTIM_DTR_DTRSLK_Msk                     /*!< Dead time rising sign lock */
+#define HRTIM_DTR_DTRLK_Pos           (15U)
+#define HRTIM_DTR_DTRLK_Msk           (0x1UL << HRTIM_DTR_DTRLK_Pos)           /*!< 0x00008000 */
+#define HRTIM_DTR_DTRLK               HRTIM_DTR_DTRLK_Msk                      /*!< Dead time rising lock */
+#define HRTIM_DTR_DTF_Pos             (16U)
+#define HRTIM_DTR_DTF_Msk             (0x1FFUL << HRTIM_DTR_DTF_Pos)           /*!< 0x01FF0000 */
+#define HRTIM_DTR_DTF                 HRTIM_DTR_DTF_Msk                        /*!< Dead time falling value */
+#define HRTIM_DTR_DTF_0               (0x001UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00010000 */
+#define HRTIM_DTR_DTF_1               (0x002UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00020000 */
+#define HRTIM_DTR_DTF_2               (0x004UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00040000 */
+#define HRTIM_DTR_DTF_3               (0x008UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00080000 */
+#define HRTIM_DTR_DTF_4               (0x010UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00100000 */
+#define HRTIM_DTR_DTF_5               (0x020UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00200000 */
+#define HRTIM_DTR_DTF_6               (0x040UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00400000 */
+#define HRTIM_DTR_DTF_7               (0x080UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00800000 */
+#define HRTIM_DTR_DTF_8               (0x100UL << HRTIM_DTR_DTF_Pos)            /*!< 0x01000000 */
+#define HRTIM_DTR_SDTF_Pos            (25U)
+#define HRTIM_DTR_SDTF_Msk            (0x1UL << HRTIM_DTR_SDTF_Pos)            /*!< 0x02000000 */
+#define HRTIM_DTR_SDTF                HRTIM_DTR_SDTF_Msk                       /*!< Sign dead time falling value */
+#define HRTIM_DTR_DTFSLK_Pos          (30U)
+#define HRTIM_DTR_DTFSLK_Msk          (0x1UL << HRTIM_DTR_DTFSLK_Pos)          /*!< 0x40000000 */
+#define HRTIM_DTR_DTFSLK              HRTIM_DTR_DTFSLK_Msk                     /*!< Dead time falling sign lock */
+#define HRTIM_DTR_DTFLK_Pos           (31U)
+#define HRTIM_DTR_DTFLK_Msk           (0x1UL << HRTIM_DTR_DTFLK_Pos)           /*!< 0x80000000 */
+#define HRTIM_DTR_DTFLK               HRTIM_DTR_DTFLK_Msk                      /*!< Dead time falling lock */
+
+/**** Bit definition for Slave Output 1 set register **************************/
+#define HRTIM_SET1R_SST_Pos           (0U)
+#define HRTIM_SET1R_SST_Msk           (0x1UL << HRTIM_SET1R_SST_Pos)           /*!< 0x00000001 */
+#define HRTIM_SET1R_SST               HRTIM_SET1R_SST_Msk                      /*!< software set trigger */
+#define HRTIM_SET1R_RESYNC_Pos        (1U)
+#define HRTIM_SET1R_RESYNC_Msk        (0x1UL << HRTIM_SET1R_RESYNC_Pos)        /*!< 0x00000002 */
+#define HRTIM_SET1R_RESYNC            HRTIM_SET1R_RESYNC_Msk                   /*!< Timer A resynchronization */
+#define HRTIM_SET1R_PER_Pos           (2U)
+#define HRTIM_SET1R_PER_Msk           (0x1UL << HRTIM_SET1R_PER_Pos)           /*!< 0x00000004 */
+#define HRTIM_SET1R_PER               HRTIM_SET1R_PER_Msk                      /*!< Timer A period */
+#define HRTIM_SET1R_CMP1_Pos          (3U)
+#define HRTIM_SET1R_CMP1_Msk          (0x1UL << HRTIM_SET1R_CMP1_Pos)          /*!< 0x00000008 */
+#define HRTIM_SET1R_CMP1              HRTIM_SET1R_CMP1_Msk                     /*!< Timer A compare 1 */
+#define HRTIM_SET1R_CMP2_Pos          (4U)
+#define HRTIM_SET1R_CMP2_Msk          (0x1UL << HRTIM_SET1R_CMP2_Pos)          /*!< 0x00000010 */
+#define HRTIM_SET1R_CMP2              HRTIM_SET1R_CMP2_Msk                     /*!< Timer A compare 2 */
+#define HRTIM_SET1R_CMP3_Pos          (5U)
+#define HRTIM_SET1R_CMP3_Msk          (0x1UL << HRTIM_SET1R_CMP3_Pos)          /*!< 0x00000020 */
+#define HRTIM_SET1R_CMP3              HRTIM_SET1R_CMP3_Msk                     /*!< Timer A compare 3 */
+#define HRTIM_SET1R_CMP4_Pos          (6U)
+#define HRTIM_SET1R_CMP4_Msk          (0x1UL << HRTIM_SET1R_CMP4_Pos)          /*!< 0x00000040 */
+#define HRTIM_SET1R_CMP4              HRTIM_SET1R_CMP4_Msk                     /*!< Timer A compare 4 */
+
+#define HRTIM_SET1R_MSTPER_Pos        (7U)
+#define HRTIM_SET1R_MSTPER_Msk        (0x1UL << HRTIM_SET1R_MSTPER_Pos)        /*!< 0x00000080 */
+#define HRTIM_SET1R_MSTPER            HRTIM_SET1R_MSTPER_Msk                   /*!< Master period */
+#define HRTIM_SET1R_MSTCMP1_Pos       (8U)
+#define HRTIM_SET1R_MSTCMP1_Msk       (0x1UL << HRTIM_SET1R_MSTCMP1_Pos)       /*!< 0x00000100 */
+#define HRTIM_SET1R_MSTCMP1           HRTIM_SET1R_MSTCMP1_Msk                  /*!< Master compare 1 */
+#define HRTIM_SET1R_MSTCMP2_Pos       (9U)
+#define HRTIM_SET1R_MSTCMP2_Msk       (0x1UL << HRTIM_SET1R_MSTCMP2_Pos)       /*!< 0x00000200 */
+#define HRTIM_SET1R_MSTCMP2           HRTIM_SET1R_MSTCMP2_Msk                  /*!< Master compare 2 */
+#define HRTIM_SET1R_MSTCMP3_Pos       (10U)
+#define HRTIM_SET1R_MSTCMP3_Msk       (0x1UL << HRTIM_SET1R_MSTCMP3_Pos)       /*!< 0x00000400 */
+#define HRTIM_SET1R_MSTCMP3           HRTIM_SET1R_MSTCMP3_Msk                  /*!< Master compare 3 */
+#define HRTIM_SET1R_MSTCMP4_Pos       (11U)
+#define HRTIM_SET1R_MSTCMP4_Msk       (0x1UL << HRTIM_SET1R_MSTCMP4_Pos)       /*!< 0x00000800 */
+#define HRTIM_SET1R_MSTCMP4           HRTIM_SET1R_MSTCMP4_Msk                  /*!< Master compare 4 */
+
+#define HRTIM_SET1R_TIMEVNT1_Pos      (12U)
+#define HRTIM_SET1R_TIMEVNT1_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT1_Pos)      /*!< 0x00001000 */
+#define HRTIM_SET1R_TIMEVNT1          HRTIM_SET1R_TIMEVNT1_Msk                 /*!< Timer event 1 */
+#define HRTIM_SET1R_TIMEVNT2_Pos      (13U)
+#define HRTIM_SET1R_TIMEVNT2_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT2_Pos)      /*!< 0x00002000 */
+#define HRTIM_SET1R_TIMEVNT2          HRTIM_SET1R_TIMEVNT2_Msk                 /*!< Timer event 2 */
+#define HRTIM_SET1R_TIMEVNT3_Pos      (14U)
+#define HRTIM_SET1R_TIMEVNT3_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT3_Pos)      /*!< 0x00004000 */
+#define HRTIM_SET1R_TIMEVNT3          HRTIM_SET1R_TIMEVNT3_Msk                 /*!< Timer event 3 */
+#define HRTIM_SET1R_TIMEVNT4_Pos      (15U)
+#define HRTIM_SET1R_TIMEVNT4_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT4_Pos)      /*!< 0x00008000 */
+#define HRTIM_SET1R_TIMEVNT4          HRTIM_SET1R_TIMEVNT4_Msk                 /*!< Timer event 4 */
+#define HRTIM_SET1R_TIMEVNT5_Pos      (16U)
+#define HRTIM_SET1R_TIMEVNT5_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT5_Pos)      /*!< 0x00010000 */
+#define HRTIM_SET1R_TIMEVNT5          HRTIM_SET1R_TIMEVNT5_Msk                 /*!< Timer event 5 */
+#define HRTIM_SET1R_TIMEVNT6_Pos      (17U)
+#define HRTIM_SET1R_TIMEVNT6_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT6_Pos)      /*!< 0x00020000 */
+#define HRTIM_SET1R_TIMEVNT6          HRTIM_SET1R_TIMEVNT6_Msk                 /*!< Timer event 6 */
+#define HRTIM_SET1R_TIMEVNT7_Pos      (18U)
+#define HRTIM_SET1R_TIMEVNT7_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT7_Pos)      /*!< 0x00040000 */
+#define HRTIM_SET1R_TIMEVNT7          HRTIM_SET1R_TIMEVNT7_Msk                 /*!< Timer event 7 */
+#define HRTIM_SET1R_TIMEVNT8_Pos      (19U)
+#define HRTIM_SET1R_TIMEVNT8_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT8_Pos)      /*!< 0x00080000 */
+#define HRTIM_SET1R_TIMEVNT8          HRTIM_SET1R_TIMEVNT8_Msk                 /*!< Timer event 8 */
+#define HRTIM_SET1R_TIMEVNT9_Pos      (20U)
+#define HRTIM_SET1R_TIMEVNT9_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT9_Pos)      /*!< 0x00100000 */
+#define HRTIM_SET1R_TIMEVNT9          HRTIM_SET1R_TIMEVNT9_Msk                 /*!< Timer event 9 */
+
+#define HRTIM_SET1R_EXTVNT1_Pos       (21U)
+#define HRTIM_SET1R_EXTVNT1_Msk       (0x1UL << HRTIM_SET1R_EXTVNT1_Pos)       /*!< 0x00200000 */
+#define HRTIM_SET1R_EXTVNT1           HRTIM_SET1R_EXTVNT1_Msk                  /*!< External event 1 */
+#define HRTIM_SET1R_EXTVNT2_Pos       (22U)
+#define HRTIM_SET1R_EXTVNT2_Msk       (0x1UL << HRTIM_SET1R_EXTVNT2_Pos)       /*!< 0x00400000 */
+#define HRTIM_SET1R_EXTVNT2           HRTIM_SET1R_EXTVNT2_Msk                  /*!< External event 2 */
+#define HRTIM_SET1R_EXTVNT3_Pos       (23U)
+#define HRTIM_SET1R_EXTVNT3_Msk       (0x1UL << HRTIM_SET1R_EXTVNT3_Pos)       /*!< 0x00800000 */
+#define HRTIM_SET1R_EXTVNT3           HRTIM_SET1R_EXTVNT3_Msk                  /*!< External event 3 */
+#define HRTIM_SET1R_EXTVNT4_Pos       (24U)
+#define HRTIM_SET1R_EXTVNT4_Msk       (0x1UL << HRTIM_SET1R_EXTVNT4_Pos)       /*!< 0x01000000 */
+#define HRTIM_SET1R_EXTVNT4           HRTIM_SET1R_EXTVNT4_Msk                  /*!< External event 4 */
+#define HRTIM_SET1R_EXTVNT5_Pos       (25U)
+#define HRTIM_SET1R_EXTVNT5_Msk       (0x1UL << HRTIM_SET1R_EXTVNT5_Pos)       /*!< 0x02000000 */
+#define HRTIM_SET1R_EXTVNT5           HRTIM_SET1R_EXTVNT5_Msk                  /*!< External event 5 */
+#define HRTIM_SET1R_EXTVNT6_Pos       (26U)
+#define HRTIM_SET1R_EXTVNT6_Msk       (0x1UL << HRTIM_SET1R_EXTVNT6_Pos)       /*!< 0x04000000 */
+#define HRTIM_SET1R_EXTVNT6           HRTIM_SET1R_EXTVNT6_Msk                  /*!< External event 6 */
+#define HRTIM_SET1R_EXTVNT7_Pos       (27U)
+#define HRTIM_SET1R_EXTVNT7_Msk       (0x1UL << HRTIM_SET1R_EXTVNT7_Pos)       /*!< 0x08000000 */
+#define HRTIM_SET1R_EXTVNT7           HRTIM_SET1R_EXTVNT7_Msk                  /*!< External event 7 */
+#define HRTIM_SET1R_EXTVNT8_Pos       (28U)
+#define HRTIM_SET1R_EXTVNT8_Msk       (0x1UL << HRTIM_SET1R_EXTVNT8_Pos)       /*!< 0x10000000 */
+#define HRTIM_SET1R_EXTVNT8           HRTIM_SET1R_EXTVNT8_Msk                  /*!< External event 8 */
+#define HRTIM_SET1R_EXTVNT9_Pos       (29U)
+#define HRTIM_SET1R_EXTVNT9_Msk       (0x1UL << HRTIM_SET1R_EXTVNT9_Pos)       /*!< 0x20000000 */
+#define HRTIM_SET1R_EXTVNT9           HRTIM_SET1R_EXTVNT9_Msk                  /*!< External event 9 */
+#define HRTIM_SET1R_EXTVNT10_Pos      (30U)
+#define HRTIM_SET1R_EXTVNT10_Msk      (0x1UL << HRTIM_SET1R_EXTVNT10_Pos)      /*!< 0x40000000 */
+#define HRTIM_SET1R_EXTVNT10          HRTIM_SET1R_EXTVNT10_Msk                 /*!< External event 10 */
+
+#define HRTIM_SET1R_UPDATE_Pos        (31U)
+#define HRTIM_SET1R_UPDATE_Msk        (0x1UL << HRTIM_SET1R_UPDATE_Pos)        /*!< 0x80000000 */
+#define HRTIM_SET1R_UPDATE            HRTIM_SET1R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */
+
+/**** Bit definition for Slave Output 1 reset register ************************/
+#define HRTIM_RST1R_SRT_Pos           (0U)
+#define HRTIM_RST1R_SRT_Msk           (0x1UL << HRTIM_RST1R_SRT_Pos)           /*!< 0x00000001 */
+#define HRTIM_RST1R_SRT               HRTIM_RST1R_SRT_Msk                      /*!< software reset trigger */
+#define HRTIM_RST1R_RESYNC_Pos        (1U)
+#define HRTIM_RST1R_RESYNC_Msk        (0x1UL << HRTIM_RST1R_RESYNC_Pos)        /*!< 0x00000002 */
+#define HRTIM_RST1R_RESYNC            HRTIM_RST1R_RESYNC_Msk                   /*!< Timer A resynchronization */
+#define HRTIM_RST1R_PER_Pos           (2U)
+#define HRTIM_RST1R_PER_Msk           (0x1UL << HRTIM_RST1R_PER_Pos)           /*!< 0x00000004 */
+#define HRTIM_RST1R_PER               HRTIM_RST1R_PER_Msk                      /*!< Timer A period */
+#define HRTIM_RST1R_CMP1_Pos          (3U)
+#define HRTIM_RST1R_CMP1_Msk          (0x1UL << HRTIM_RST1R_CMP1_Pos)          /*!< 0x00000008 */
+#define HRTIM_RST1R_CMP1              HRTIM_RST1R_CMP1_Msk                     /*!< Timer A compare 1 */
+#define HRTIM_RST1R_CMP2_Pos          (4U)
+#define HRTIM_RST1R_CMP2_Msk          (0x1UL << HRTIM_RST1R_CMP2_Pos)          /*!< 0x00000010 */
+#define HRTIM_RST1R_CMP2              HRTIM_RST1R_CMP2_Msk                     /*!< Timer A compare 2 */
+#define HRTIM_RST1R_CMP3_Pos          (5U)
+#define HRTIM_RST1R_CMP3_Msk          (0x1UL << HRTIM_RST1R_CMP3_Pos)          /*!< 0x00000020 */
+#define HRTIM_RST1R_CMP3              HRTIM_RST1R_CMP3_Msk                     /*!< Timer A compare 3 */
+#define HRTIM_RST1R_CMP4_Pos          (6U)
+#define HRTIM_RST1R_CMP4_Msk          (0x1UL << HRTIM_RST1R_CMP4_Pos)          /*!< 0x00000040 */
+#define HRTIM_RST1R_CMP4              HRTIM_RST1R_CMP4_Msk                     /*!< Timer A compare 4 */
+
+#define HRTIM_RST1R_MSTPER_Pos        (7U)
+#define HRTIM_RST1R_MSTPER_Msk        (0x1UL << HRTIM_RST1R_MSTPER_Pos)        /*!< 0x00000080 */
+#define HRTIM_RST1R_MSTPER            HRTIM_RST1R_MSTPER_Msk                   /*!< Master period */
+#define HRTIM_RST1R_MSTCMP1_Pos       (8U)
+#define HRTIM_RST1R_MSTCMP1_Msk       (0x1UL << HRTIM_RST1R_MSTCMP1_Pos)       /*!< 0x00000100 */
+#define HRTIM_RST1R_MSTCMP1           HRTIM_RST1R_MSTCMP1_Msk                  /*!< Master compare 1 */
+#define HRTIM_RST1R_MSTCMP2_Pos       (9U)
+#define HRTIM_RST1R_MSTCMP2_Msk       (0x1UL << HRTIM_RST1R_MSTCMP2_Pos)       /*!< 0x00000200 */
+#define HRTIM_RST1R_MSTCMP2           HRTIM_RST1R_MSTCMP2_Msk                  /*!< Master compare 2 */
+#define HRTIM_RST1R_MSTCMP3_Pos       (10U)
+#define HRTIM_RST1R_MSTCMP3_Msk       (0x1UL << HRTIM_RST1R_MSTCMP3_Pos)       /*!< 0x00000400 */
+#define HRTIM_RST1R_MSTCMP3           HRTIM_RST1R_MSTCMP3_Msk                  /*!< Master compare 3 */
+#define HRTIM_RST1R_MSTCMP4_Pos       (11U)
+#define HRTIM_RST1R_MSTCMP4_Msk       (0x1UL << HRTIM_RST1R_MSTCMP4_Pos)       /*!< 0x00000800 */
+#define HRTIM_RST1R_MSTCMP4           HRTIM_RST1R_MSTCMP4_Msk                  /*!< Master compare 4 */
+
+#define HRTIM_RST1R_TIMEVNT1_Pos      (12U)
+#define HRTIM_RST1R_TIMEVNT1_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT1_Pos)      /*!< 0x00001000 */
+#define HRTIM_RST1R_TIMEVNT1          HRTIM_RST1R_TIMEVNT1_Msk                 /*!< Timer event 1 */
+#define HRTIM_RST1R_TIMEVNT2_Pos      (13U)
+#define HRTIM_RST1R_TIMEVNT2_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT2_Pos)      /*!< 0x00002000 */
+#define HRTIM_RST1R_TIMEVNT2          HRTIM_RST1R_TIMEVNT2_Msk                 /*!< Timer event 2 */
+#define HRTIM_RST1R_TIMEVNT3_Pos      (14U)
+#define HRTIM_RST1R_TIMEVNT3_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT3_Pos)      /*!< 0x00004000 */
+#define HRTIM_RST1R_TIMEVNT3          HRTIM_RST1R_TIMEVNT3_Msk                 /*!< Timer event 3 */
+#define HRTIM_RST1R_TIMEVNT4_Pos      (15U)
+#define HRTIM_RST1R_TIMEVNT4_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT4_Pos)      /*!< 0x00008000 */
+#define HRTIM_RST1R_TIMEVNT4          HRTIM_RST1R_TIMEVNT4_Msk                 /*!< Timer event 4 */
+#define HRTIM_RST1R_TIMEVNT5_Pos      (16U)
+#define HRTIM_RST1R_TIMEVNT5_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT5_Pos)      /*!< 0x00010000 */
+#define HRTIM_RST1R_TIMEVNT5          HRTIM_RST1R_TIMEVNT5_Msk                 /*!< Timer event 5 */
+#define HRTIM_RST1R_TIMEVNT6_Pos      (17U)
+#define HRTIM_RST1R_TIMEVNT6_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT6_Pos)      /*!< 0x00020000 */
+#define HRTIM_RST1R_TIMEVNT6          HRTIM_RST1R_TIMEVNT6_Msk                 /*!< Timer event 6 */
+#define HRTIM_RST1R_TIMEVNT7_Pos      (18U)
+#define HRTIM_RST1R_TIMEVNT7_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT7_Pos)      /*!< 0x00040000 */
+#define HRTIM_RST1R_TIMEVNT7          HRTIM_RST1R_TIMEVNT7_Msk                 /*!< Timer event 7 */
+#define HRTIM_RST1R_TIMEVNT8_Pos      (19U)
+#define HRTIM_RST1R_TIMEVNT8_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT8_Pos)      /*!< 0x00080000 */
+#define HRTIM_RST1R_TIMEVNT8          HRTIM_RST1R_TIMEVNT8_Msk                 /*!< Timer event 8 */
+#define HRTIM_RST1R_TIMEVNT9_Pos      (20U)
+#define HRTIM_RST1R_TIMEVNT9_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT9_Pos)      /*!< 0x00100000 */
+#define HRTIM_RST1R_TIMEVNT9          HRTIM_RST1R_TIMEVNT9_Msk                 /*!< Timer event 9 */
+
+#define HRTIM_RST1R_EXTVNT1_Pos       (21U)
+#define HRTIM_RST1R_EXTVNT1_Msk       (0x1UL << HRTIM_RST1R_EXTVNT1_Pos)       /*!< 0x00200000 */
+#define HRTIM_RST1R_EXTVNT1           HRTIM_RST1R_EXTVNT1_Msk                  /*!< External event 1 */
+#define HRTIM_RST1R_EXTVNT2_Pos       (22U)
+#define HRTIM_RST1R_EXTVNT2_Msk       (0x1UL << HRTIM_RST1R_EXTVNT2_Pos)       /*!< 0x00400000 */
+#define HRTIM_RST1R_EXTVNT2           HRTIM_RST1R_EXTVNT2_Msk                  /*!< External event 2 */
+#define HRTIM_RST1R_EXTVNT3_Pos       (23U)
+#define HRTIM_RST1R_EXTVNT3_Msk       (0x1UL << HRTIM_RST1R_EXTVNT3_Pos)       /*!< 0x00800000 */
+#define HRTIM_RST1R_EXTVNT3           HRTIM_RST1R_EXTVNT3_Msk                  /*!< External event 3 */
+#define HRTIM_RST1R_EXTVNT4_Pos       (24U)
+#define HRTIM_RST1R_EXTVNT4_Msk       (0x1UL << HRTIM_RST1R_EXTVNT4_Pos)       /*!< 0x01000000 */
+#define HRTIM_RST1R_EXTVNT4           HRTIM_RST1R_EXTVNT4_Msk                  /*!< External event 4 */
+#define HRTIM_RST1R_EXTVNT5_Pos       (25U)
+#define HRTIM_RST1R_EXTVNT5_Msk       (0x1UL << HRTIM_RST1R_EXTVNT5_Pos)       /*!< 0x02000000 */
+#define HRTIM_RST1R_EXTVNT5           HRTIM_RST1R_EXTVNT5_Msk                  /*!< External event 5 */
+#define HRTIM_RST1R_EXTVNT6_Pos       (26U)
+#define HRTIM_RST1R_EXTVNT6_Msk       (0x1UL << HRTIM_RST1R_EXTVNT6_Pos)       /*!< 0x04000000 */
+#define HRTIM_RST1R_EXTVNT6           HRTIM_RST1R_EXTVNT6_Msk                  /*!< External event 6 */
+#define HRTIM_RST1R_EXTVNT7_Pos       (27U)
+#define HRTIM_RST1R_EXTVNT7_Msk       (0x1UL << HRTIM_RST1R_EXTVNT7_Pos)       /*!< 0x08000000 */
+#define HRTIM_RST1R_EXTVNT7           HRTIM_RST1R_EXTVNT7_Msk                  /*!< External event 7 */
+#define HRTIM_RST1R_EXTVNT8_Pos       (28U)
+#define HRTIM_RST1R_EXTVNT8_Msk       (0x1UL << HRTIM_RST1R_EXTVNT8_Pos)       /*!< 0x10000000 */
+#define HRTIM_RST1R_EXTVNT8           HRTIM_RST1R_EXTVNT8_Msk                  /*!< External event 8 */
+#define HRTIM_RST1R_EXTVNT9_Pos       (29U)
+#define HRTIM_RST1R_EXTVNT9_Msk       (0x1UL << HRTIM_RST1R_EXTVNT9_Pos)       /*!< 0x20000000 */
+#define HRTIM_RST1R_EXTVNT9           HRTIM_RST1R_EXTVNT9_Msk                  /*!< External event 9 */
+#define HRTIM_RST1R_EXTVNT10_Pos      (30U)
+#define HRTIM_RST1R_EXTVNT10_Msk      (0x1UL << HRTIM_RST1R_EXTVNT10_Pos)      /*!< 0x40000000 */
+#define HRTIM_RST1R_EXTVNT10          HRTIM_RST1R_EXTVNT10_Msk                 /*!< External event 10 */
+
+#define HRTIM_RST1R_UPDATE_Pos        (31U)
+#define HRTIM_RST1R_UPDATE_Msk        (0x1UL << HRTIM_RST1R_UPDATE_Pos)        /*!< 0x80000000 */
+#define HRTIM_RST1R_UPDATE            HRTIM_RST1R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */
+
+
+/**** Bit definition for Slave Output 2 set register **************************/
+#define HRTIM_SET2R_SST_Pos           (0U)
+#define HRTIM_SET2R_SST_Msk           (0x1UL << HRTIM_SET2R_SST_Pos)           /*!< 0x00000001 */
+#define HRTIM_SET2R_SST               HRTIM_SET2R_SST_Msk                      /*!< software set trigger */
+#define HRTIM_SET2R_RESYNC_Pos        (1U)
+#define HRTIM_SET2R_RESYNC_Msk        (0x1UL << HRTIM_SET2R_RESYNC_Pos)        /*!< 0x00000002 */
+#define HRTIM_SET2R_RESYNC            HRTIM_SET2R_RESYNC_Msk                   /*!< Timer A resynchronization */
+#define HRTIM_SET2R_PER_Pos           (2U)
+#define HRTIM_SET2R_PER_Msk           (0x1UL << HRTIM_SET2R_PER_Pos)           /*!< 0x00000004 */
+#define HRTIM_SET2R_PER               HRTIM_SET2R_PER_Msk                      /*!< Timer A period */
+#define HRTIM_SET2R_CMP1_Pos          (3U)
+#define HRTIM_SET2R_CMP1_Msk          (0x1UL << HRTIM_SET2R_CMP1_Pos)          /*!< 0x00000008 */
+#define HRTIM_SET2R_CMP1              HRTIM_SET2R_CMP1_Msk                     /*!< Timer A compare 1 */
+#define HRTIM_SET2R_CMP2_Pos          (4U)
+#define HRTIM_SET2R_CMP2_Msk          (0x1UL << HRTIM_SET2R_CMP2_Pos)          /*!< 0x00000010 */
+#define HRTIM_SET2R_CMP2              HRTIM_SET2R_CMP2_Msk                     /*!< Timer A compare 2 */
+#define HRTIM_SET2R_CMP3_Pos          (5U)
+#define HRTIM_SET2R_CMP3_Msk          (0x1UL << HRTIM_SET2R_CMP3_Pos)          /*!< 0x00000020 */
+#define HRTIM_SET2R_CMP3              HRTIM_SET2R_CMP3_Msk                     /*!< Timer A compare 3 */
+#define HRTIM_SET2R_CMP4_Pos          (6U)
+#define HRTIM_SET2R_CMP4_Msk          (0x1UL << HRTIM_SET2R_CMP4_Pos)          /*!< 0x00000040 */
+#define HRTIM_SET2R_CMP4              HRTIM_SET2R_CMP4_Msk                     /*!< Timer A compare 4 */
+
+#define HRTIM_SET2R_MSTPER_Pos        (7U)
+#define HRTIM_SET2R_MSTPER_Msk        (0x1UL << HRTIM_SET2R_MSTPER_Pos)        /*!< 0x00000080 */
+#define HRTIM_SET2R_MSTPER            HRTIM_SET2R_MSTPER_Msk                   /*!< Master period */
+#define HRTIM_SET2R_MSTCMP1_Pos       (8U)
+#define HRTIM_SET2R_MSTCMP1_Msk       (0x1UL << HRTIM_SET2R_MSTCMP1_Pos)       /*!< 0x00000100 */
+#define HRTIM_SET2R_MSTCMP1           HRTIM_SET2R_MSTCMP1_Msk                  /*!< Master compare 1 */
+#define HRTIM_SET2R_MSTCMP2_Pos       (9U)
+#define HRTIM_SET2R_MSTCMP2_Msk       (0x1UL << HRTIM_SET2R_MSTCMP2_Pos)       /*!< 0x00000200 */
+#define HRTIM_SET2R_MSTCMP2           HRTIM_SET2R_MSTCMP2_Msk                  /*!< Master compare 2 */
+#define HRTIM_SET2R_MSTCMP3_Pos       (10U)
+#define HRTIM_SET2R_MSTCMP3_Msk       (0x1UL << HRTIM_SET2R_MSTCMP3_Pos)       /*!< 0x00000400 */
+#define HRTIM_SET2R_MSTCMP3           HRTIM_SET2R_MSTCMP3_Msk                  /*!< Master compare 3 */
+#define HRTIM_SET2R_MSTCMP4_Pos       (11U)
+#define HRTIM_SET2R_MSTCMP4_Msk       (0x1UL << HRTIM_SET2R_MSTCMP4_Pos)       /*!< 0x00000800 */
+#define HRTIM_SET2R_MSTCMP4           HRTIM_SET2R_MSTCMP4_Msk                  /*!< Master compare 4 */
+
+#define HRTIM_SET2R_TIMEVNT1_Pos      (12U)
+#define HRTIM_SET2R_TIMEVNT1_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT1_Pos)      /*!< 0x00001000 */
+#define HRTIM_SET2R_TIMEVNT1          HRTIM_SET2R_TIMEVNT1_Msk                 /*!< Timer event 1 */
+#define HRTIM_SET2R_TIMEVNT2_Pos      (13U)
+#define HRTIM_SET2R_TIMEVNT2_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT2_Pos)      /*!< 0x00002000 */
+#define HRTIM_SET2R_TIMEVNT2          HRTIM_SET2R_TIMEVNT2_Msk                 /*!< Timer event 2 */
+#define HRTIM_SET2R_TIMEVNT3_Pos      (14U)
+#define HRTIM_SET2R_TIMEVNT3_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT3_Pos)      /*!< 0x00004000 */
+#define HRTIM_SET2R_TIMEVNT3          HRTIM_SET2R_TIMEVNT3_Msk                 /*!< Timer event 3 */
+#define HRTIM_SET2R_TIMEVNT4_Pos      (15U)
+#define HRTIM_SET2R_TIMEVNT4_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT4_Pos)      /*!< 0x00008000 */
+#define HRTIM_SET2R_TIMEVNT4          HRTIM_SET2R_TIMEVNT4_Msk                 /*!< Timer event 4 */
+#define HRTIM_SET2R_TIMEVNT5_Pos      (16U)
+#define HRTIM_SET2R_TIMEVNT5_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT5_Pos)      /*!< 0x00010000 */
+#define HRTIM_SET2R_TIMEVNT5          HRTIM_SET2R_TIMEVNT5_Msk                 /*!< Timer event 5 */
+#define HRTIM_SET2R_TIMEVNT6_Pos      (17U)
+#define HRTIM_SET2R_TIMEVNT6_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT6_Pos)      /*!< 0x00020000 */
+#define HRTIM_SET2R_TIMEVNT6          HRTIM_SET2R_TIMEVNT6_Msk                 /*!< Timer event 6 */
+#define HRTIM_SET2R_TIMEVNT7_Pos      (18U)
+#define HRTIM_SET2R_TIMEVNT7_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT7_Pos)      /*!< 0x00040000 */
+#define HRTIM_SET2R_TIMEVNT7          HRTIM_SET2R_TIMEVNT7_Msk                 /*!< Timer event 7 */
+#define HRTIM_SET2R_TIMEVNT8_Pos      (19U)
+#define HRTIM_SET2R_TIMEVNT8_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT8_Pos)      /*!< 0x00080000 */
+#define HRTIM_SET2R_TIMEVNT8          HRTIM_SET2R_TIMEVNT8_Msk                 /*!< Timer event 8 */
+#define HRTIM_SET2R_TIMEVNT9_Pos      (20U)
+#define HRTIM_SET2R_TIMEVNT9_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT9_Pos)      /*!< 0x00100000 */
+#define HRTIM_SET2R_TIMEVNT9          HRTIM_SET2R_TIMEVNT9_Msk                 /*!< Timer event 9 */
+
+#define HRTIM_SET2R_EXTVNT1_Pos       (21U)
+#define HRTIM_SET2R_EXTVNT1_Msk       (0x1UL << HRTIM_SET2R_EXTVNT1_Pos)       /*!< 0x00200000 */
+#define HRTIM_SET2R_EXTVNT1           HRTIM_SET2R_EXTVNT1_Msk                  /*!< External event 1 */
+#define HRTIM_SET2R_EXTVNT2_Pos       (22U)
+#define HRTIM_SET2R_EXTVNT2_Msk       (0x1UL << HRTIM_SET2R_EXTVNT2_Pos)       /*!< 0x00400000 */
+#define HRTIM_SET2R_EXTVNT2           HRTIM_SET2R_EXTVNT2_Msk                  /*!< External event 2 */
+#define HRTIM_SET2R_EXTVNT3_Pos       (23U)
+#define HRTIM_SET2R_EXTVNT3_Msk       (0x1UL << HRTIM_SET2R_EXTVNT3_Pos)       /*!< 0x00800000 */
+#define HRTIM_SET2R_EXTVNT3           HRTIM_SET2R_EXTVNT3_Msk                  /*!< External event 3 */
+#define HRTIM_SET2R_EXTVNT4_Pos       (24U)
+#define HRTIM_SET2R_EXTVNT4_Msk       (0x1UL << HRTIM_SET2R_EXTVNT4_Pos)       /*!< 0x01000000 */
+#define HRTIM_SET2R_EXTVNT4           HRTIM_SET2R_EXTVNT4_Msk                  /*!< External event 4 */
+#define HRTIM_SET2R_EXTVNT5_Pos       (25U)
+#define HRTIM_SET2R_EXTVNT5_Msk       (0x1UL << HRTIM_SET2R_EXTVNT5_Pos)       /*!< 0x02000000 */
+#define HRTIM_SET2R_EXTVNT5           HRTIM_SET2R_EXTVNT5_Msk                  /*!< External event 5 */
+#define HRTIM_SET2R_EXTVNT6_Pos       (26U)
+#define HRTIM_SET2R_EXTVNT6_Msk       (0x1UL << HRTIM_SET2R_EXTVNT6_Pos)       /*!< 0x04000000 */
+#define HRTIM_SET2R_EXTVNT6           HRTIM_SET2R_EXTVNT6_Msk                  /*!< External event 6 */
+#define HRTIM_SET2R_EXTVNT7_Pos       (27U)
+#define HRTIM_SET2R_EXTVNT7_Msk       (0x1UL << HRTIM_SET2R_EXTVNT7_Pos)       /*!< 0x08000000 */
+#define HRTIM_SET2R_EXTVNT7           HRTIM_SET2R_EXTVNT7_Msk                  /*!< External event 7 */
+#define HRTIM_SET2R_EXTVNT8_Pos       (28U)
+#define HRTIM_SET2R_EXTVNT8_Msk       (0x1UL << HRTIM_SET2R_EXTVNT8_Pos)       /*!< 0x10000000 */
+#define HRTIM_SET2R_EXTVNT8           HRTIM_SET2R_EXTVNT8_Msk                  /*!< External event 8 */
+#define HRTIM_SET2R_EXTVNT9_Pos       (29U)
+#define HRTIM_SET2R_EXTVNT9_Msk       (0x1UL << HRTIM_SET2R_EXTVNT9_Pos)       /*!< 0x20000000 */
+#define HRTIM_SET2R_EXTVNT9           HRTIM_SET2R_EXTVNT9_Msk                  /*!< External event 9 */
+#define HRTIM_SET2R_EXTVNT10_Pos      (30U)
+#define HRTIM_SET2R_EXTVNT10_Msk      (0x1UL << HRTIM_SET2R_EXTVNT10_Pos)      /*!< 0x40000000 */
+#define HRTIM_SET2R_EXTVNT10          HRTIM_SET2R_EXTVNT10_Msk                 /*!< External event 10 */
+
+#define HRTIM_SET2R_UPDATE_Pos        (31U)
+#define HRTIM_SET2R_UPDATE_Msk        (0x1UL << HRTIM_SET2R_UPDATE_Pos)        /*!< 0x80000000 */
+#define HRTIM_SET2R_UPDATE            HRTIM_SET2R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */
+
+/**** Bit definition for Slave Output 2 reset register ************************/
+#define HRTIM_RST2R_SRT_Pos           (0U)
+#define HRTIM_RST2R_SRT_Msk           (0x1UL << HRTIM_RST2R_SRT_Pos)           /*!< 0x00000001 */
+#define HRTIM_RST2R_SRT               HRTIM_RST2R_SRT_Msk                      /*!< software reset trigger */
+#define HRTIM_RST2R_RESYNC_Pos        (1U)
+#define HRTIM_RST2R_RESYNC_Msk        (0x1UL << HRTIM_RST2R_RESYNC_Pos)        /*!< 0x00000002 */
+#define HRTIM_RST2R_RESYNC            HRTIM_RST2R_RESYNC_Msk                   /*!< Timer A resynchronization */
+#define HRTIM_RST2R_PER_Pos           (2U)
+#define HRTIM_RST2R_PER_Msk           (0x1UL << HRTIM_RST2R_PER_Pos)           /*!< 0x00000004 */
+#define HRTIM_RST2R_PER               HRTIM_RST2R_PER_Msk                      /*!< Timer A period */
+#define HRTIM_RST2R_CMP1_Pos          (3U)
+#define HRTIM_RST2R_CMP1_Msk          (0x1UL << HRTIM_RST2R_CMP1_Pos)          /*!< 0x00000008 */
+#define HRTIM_RST2R_CMP1              HRTIM_RST2R_CMP1_Msk                     /*!< Timer A compare 1 */
+#define HRTIM_RST2R_CMP2_Pos          (4U)
+#define HRTIM_RST2R_CMP2_Msk          (0x1UL << HRTIM_RST2R_CMP2_Pos)          /*!< 0x00000010 */
+#define HRTIM_RST2R_CMP2              HRTIM_RST2R_CMP2_Msk                     /*!< Timer A compare 2 */
+#define HRTIM_RST2R_CMP3_Pos          (5U)
+#define HRTIM_RST2R_CMP3_Msk          (0x1UL << HRTIM_RST2R_CMP3_Pos)          /*!< 0x00000020 */
+#define HRTIM_RST2R_CMP3              HRTIM_RST2R_CMP3_Msk                     /*!< Timer A compare 3 */
+#define HRTIM_RST2R_CMP4_Pos          (6U)
+#define HRTIM_RST2R_CMP4_Msk          (0x1UL << HRTIM_RST2R_CMP4_Pos)          /*!< 0x00000040 */
+#define HRTIM_RST2R_CMP4              HRTIM_RST2R_CMP4_Msk                     /*!< Timer A compare 4 */
+
+#define HRTIM_RST2R_MSTPER_Pos        (7U)
+#define HRTIM_RST2R_MSTPER_Msk        (0x1UL << HRTIM_RST2R_MSTPER_Pos)        /*!< 0x00000080 */
+#define HRTIM_RST2R_MSTPER            HRTIM_RST2R_MSTPER_Msk                   /*!< Master period */
+#define HRTIM_RST2R_MSTCMP1_Pos       (8U)
+#define HRTIM_RST2R_MSTCMP1_Msk       (0x1UL << HRTIM_RST2R_MSTCMP1_Pos)       /*!< 0x00000100 */
+#define HRTIM_RST2R_MSTCMP1           HRTIM_RST2R_MSTCMP1_Msk                  /*!< Master compare 1 */
+#define HRTIM_RST2R_MSTCMP2_Pos       (9U)
+#define HRTIM_RST2R_MSTCMP2_Msk       (0x1UL << HRTIM_RST2R_MSTCMP2_Pos)       /*!< 0x00000200 */
+#define HRTIM_RST2R_MSTCMP2           HRTIM_RST2R_MSTCMP2_Msk                  /*!< Master compare 2 */
+#define HRTIM_RST2R_MSTCMP3_Pos       (10U)
+#define HRTIM_RST2R_MSTCMP3_Msk       (0x1UL << HRTIM_RST2R_MSTCMP3_Pos)       /*!< 0x00000400 */
+#define HRTIM_RST2R_MSTCMP3           HRTIM_RST2R_MSTCMP3_Msk                  /*!< Master compare 3 */
+#define HRTIM_RST2R_MSTCMP4_Pos       (11U)
+#define HRTIM_RST2R_MSTCMP4_Msk       (0x1UL << HRTIM_RST2R_MSTCMP4_Pos)       /*!< 0x00000800 */
+#define HRTIM_RST2R_MSTCMP4           HRTIM_RST2R_MSTCMP4_Msk                  /*!< Master compare 4 */
+
+#define HRTIM_RST2R_TIMEVNT1_Pos      (12U)
+#define HRTIM_RST2R_TIMEVNT1_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT1_Pos)      /*!< 0x00001000 */
+#define HRTIM_RST2R_TIMEVNT1          HRTIM_RST2R_TIMEVNT1_Msk                 /*!< Timer event 1 */
+#define HRTIM_RST2R_TIMEVNT2_Pos      (13U)
+#define HRTIM_RST2R_TIMEVNT2_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT2_Pos)      /*!< 0x00002000 */
+#define HRTIM_RST2R_TIMEVNT2          HRTIM_RST2R_TIMEVNT2_Msk                 /*!< Timer event 2 */
+#define HRTIM_RST2R_TIMEVNT3_Pos      (14U)
+#define HRTIM_RST2R_TIMEVNT3_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT3_Pos)      /*!< 0x00004000 */
+#define HRTIM_RST2R_TIMEVNT3          HRTIM_RST2R_TIMEVNT3_Msk                 /*!< Timer event 3 */
+#define HRTIM_RST2R_TIMEVNT4_Pos      (15U)
+#define HRTIM_RST2R_TIMEVNT4_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT4_Pos)      /*!< 0x00008000 */
+#define HRTIM_RST2R_TIMEVNT4          HRTIM_RST2R_TIMEVNT4_Msk                 /*!< Timer event 4 */
+#define HRTIM_RST2R_TIMEVNT5_Pos      (16U)
+#define HRTIM_RST2R_TIMEVNT5_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT5_Pos)      /*!< 0x00010000 */
+#define HRTIM_RST2R_TIMEVNT5          HRTIM_RST2R_TIMEVNT5_Msk                 /*!< Timer event 5 */
+#define HRTIM_RST2R_TIMEVNT6_Pos      (17U)
+#define HRTIM_RST2R_TIMEVNT6_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT6_Pos)      /*!< 0x00020000 */
+#define HRTIM_RST2R_TIMEVNT6          HRTIM_RST2R_TIMEVNT6_Msk                 /*!< Timer event 6 */
+#define HRTIM_RST2R_TIMEVNT7_Pos      (18U)
+#define HRTIM_RST2R_TIMEVNT7_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT7_Pos)      /*!< 0x00040000 */
+#define HRTIM_RST2R_TIMEVNT7          HRTIM_RST2R_TIMEVNT7_Msk                 /*!< Timer event 7 */
+#define HRTIM_RST2R_TIMEVNT8_Pos      (19U)
+#define HRTIM_RST2R_TIMEVNT8_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT8_Pos)      /*!< 0x00080000 */
+#define HRTIM_RST2R_TIMEVNT8          HRTIM_RST2R_TIMEVNT8_Msk                 /*!< Timer event 8 */
+#define HRTIM_RST2R_TIMEVNT9_Pos      (20U)
+#define HRTIM_RST2R_TIMEVNT9_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT9_Pos)      /*!< 0x00100000 */
+#define HRTIM_RST2R_TIMEVNT9          HRTIM_RST2R_TIMEVNT9_Msk                 /*!< Timer event 9 */
+
+#define HRTIM_RST2R_EXTVNT1_Pos       (21U)
+#define HRTIM_RST2R_EXTVNT1_Msk       (0x1UL << HRTIM_RST2R_EXTVNT1_Pos)       /*!< 0x00200000 */
+#define HRTIM_RST2R_EXTVNT1           HRTIM_RST2R_EXTVNT1_Msk                  /*!< External event 1 */
+#define HRTIM_RST2R_EXTVNT2_Pos       (22U)
+#define HRTIM_RST2R_EXTVNT2_Msk       (0x1UL << HRTIM_RST2R_EXTVNT2_Pos)       /*!< 0x00400000 */
+#define HRTIM_RST2R_EXTVNT2           HRTIM_RST2R_EXTVNT2_Msk                  /*!< External event 2 */
+#define HRTIM_RST2R_EXTVNT3_Pos       (23U)
+#define HRTIM_RST2R_EXTVNT3_Msk       (0x1UL << HRTIM_RST2R_EXTVNT3_Pos)       /*!< 0x00800000 */
+#define HRTIM_RST2R_EXTVNT3           HRTIM_RST2R_EXTVNT3_Msk                  /*!< External event 3 */
+#define HRTIM_RST2R_EXTVNT4_Pos       (24U)
+#define HRTIM_RST2R_EXTVNT4_Msk       (0x1UL << HRTIM_RST2R_EXTVNT4_Pos)       /*!< 0x01000000 */
+#define HRTIM_RST2R_EXTVNT4           HRTIM_RST2R_EXTVNT4_Msk                  /*!< External event 4 */
+#define HRTIM_RST2R_EXTVNT5_Pos       (25U)
+#define HRTIM_RST2R_EXTVNT5_Msk       (0x1UL << HRTIM_RST2R_EXTVNT5_Pos)       /*!< 0x02000000 */
+#define HRTIM_RST2R_EXTVNT5           HRTIM_RST2R_EXTVNT5_Msk                  /*!< External event 5 */
+#define HRTIM_RST2R_EXTVNT6_Pos       (26U)
+#define HRTIM_RST2R_EXTVNT6_Msk       (0x1UL << HRTIM_RST2R_EXTVNT6_Pos)       /*!< 0x04000000 */
+#define HRTIM_RST2R_EXTVNT6           HRTIM_RST2R_EXTVNT6_Msk                  /*!< External event 6 */
+#define HRTIM_RST2R_EXTVNT7_Pos       (27U)
+#define HRTIM_RST2R_EXTVNT7_Msk       (0x1UL << HRTIM_RST2R_EXTVNT7_Pos)       /*!< 0x08000000 */
+#define HRTIM_RST2R_EXTVNT7           HRTIM_RST2R_EXTVNT7_Msk                  /*!< External event 7 */
+#define HRTIM_RST2R_EXTVNT8_Pos       (28U)
+#define HRTIM_RST2R_EXTVNT8_Msk       (0x1UL << HRTIM_RST2R_EXTVNT8_Pos)       /*!< 0x10000000 */
+#define HRTIM_RST2R_EXTVNT8           HRTIM_RST2R_EXTVNT8_Msk                  /*!< External event 8 */
+#define HRTIM_RST2R_EXTVNT9_Pos       (29U)
+#define HRTIM_RST2R_EXTVNT9_Msk       (0x1UL << HRTIM_RST2R_EXTVNT9_Pos)       /*!< 0x20000000 */
+#define HRTIM_RST2R_EXTVNT9           HRTIM_RST2R_EXTVNT9_Msk                  /*!< External event 9 */
+#define HRTIM_RST2R_EXTVNT10_Pos      (30U)
+#define HRTIM_RST2R_EXTVNT10_Msk      (0x1UL << HRTIM_RST2R_EXTVNT10_Pos)      /*!< 0x40000000 */
+#define HRTIM_RST2R_EXTVNT10          HRTIM_RST2R_EXTVNT10_Msk                 /*!< External event 10 */
+
+#define HRTIM_RST2R_UPDATE_Pos        (31U)
+#define HRTIM_RST2R_UPDATE_Msk        (0x1UL << HRTIM_RST2R_UPDATE_Pos)        /*!< 0x80000000 */
+#define HRTIM_RST2R_UPDATE            HRTIM_RST2R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */
+
+/**** Bit definition for Slave external event filtering  register 1 ***********/
+#define HRTIM_EEFR1_EE1LTCH_Pos       (0U)
+#define HRTIM_EEFR1_EE1LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE1LTCH_Pos)       /*!< 0x00000001 */
+#define HRTIM_EEFR1_EE1LTCH           HRTIM_EEFR1_EE1LTCH_Msk                  /*!< External Event 1 latch */
+#define HRTIM_EEFR1_EE1FLTR_Pos       (1U)
+#define HRTIM_EEFR1_EE1FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE1FLTR_Pos)       /*!< 0x0000001E */
+#define HRTIM_EEFR1_EE1FLTR           HRTIM_EEFR1_EE1FLTR_Msk                  /*!< External Event 1 filter mask */
+#define HRTIM_EEFR1_EE1FLTR_0         (0x1UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000002 */
+#define HRTIM_EEFR1_EE1FLTR_1         (0x2UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000004 */
+#define HRTIM_EEFR1_EE1FLTR_2         (0x4UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000008 */
+#define HRTIM_EEFR1_EE1FLTR_3         (0x8UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000010 */
+
+#define HRTIM_EEFR1_EE2LTCH_Pos       (6U)
+#define HRTIM_EEFR1_EE2LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE2LTCH_Pos)       /*!< 0x00000040 */
+#define HRTIM_EEFR1_EE2LTCH           HRTIM_EEFR1_EE2LTCH_Msk                  /*!< External Event 2 latch */
+#define HRTIM_EEFR1_EE2FLTR_Pos       (7U)
+#define HRTIM_EEFR1_EE2FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE2FLTR_Pos)       /*!< 0x00000780 */
+#define HRTIM_EEFR1_EE2FLTR           HRTIM_EEFR1_EE2FLTR_Msk                  /*!< External Event 2 filter mask */
+#define HRTIM_EEFR1_EE2FLTR_0         (0x1UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000080 */
+#define HRTIM_EEFR1_EE2FLTR_1         (0x2UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000100 */
+#define HRTIM_EEFR1_EE2FLTR_2         (0x4UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000200 */
+#define HRTIM_EEFR1_EE2FLTR_3         (0x8UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000400 */
+
+#define HRTIM_EEFR1_EE3LTCH_Pos       (12U)
+#define HRTIM_EEFR1_EE3LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE3LTCH_Pos)       /*!< 0x00001000 */
+#define HRTIM_EEFR1_EE3LTCH           HRTIM_EEFR1_EE3LTCH_Msk                  /*!< External Event 3 latch */
+#define HRTIM_EEFR1_EE3FLTR_Pos       (13U)
+#define HRTIM_EEFR1_EE3FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE3FLTR_Pos)       /*!< 0x0001E000 */
+#define HRTIM_EEFR1_EE3FLTR           HRTIM_EEFR1_EE3FLTR_Msk                  /*!< External Event 3 filter mask */
+#define HRTIM_EEFR1_EE3FLTR_0         (0x1UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00002000 */
+#define HRTIM_EEFR1_EE3FLTR_1         (0x2UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00004000 */
+#define HRTIM_EEFR1_EE3FLTR_2         (0x4UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00008000 */
+#define HRTIM_EEFR1_EE3FLTR_3         (0x8UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00010000 */
+
+#define HRTIM_EEFR1_EE4LTCH_Pos       (18U)
+#define HRTIM_EEFR1_EE4LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE4LTCH_Pos)       /*!< 0x00040000 */
+#define HRTIM_EEFR1_EE4LTCH           HRTIM_EEFR1_EE4LTCH_Msk                  /*!< External Event 4 latch */
+#define HRTIM_EEFR1_EE4FLTR_Pos       (19U)
+#define HRTIM_EEFR1_EE4FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE4FLTR_Pos)       /*!< 0x00780000 */
+#define HRTIM_EEFR1_EE4FLTR           HRTIM_EEFR1_EE4FLTR_Msk                  /*!< External Event 4 filter mask */
+#define HRTIM_EEFR1_EE4FLTR_0         (0x1UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00080000 */
+#define HRTIM_EEFR1_EE4FLTR_1         (0x2UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00100000 */
+#define HRTIM_EEFR1_EE4FLTR_2         (0x4UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00200000 */
+#define HRTIM_EEFR1_EE4FLTR_3         (0x8UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00400000 */
+
+#define HRTIM_EEFR1_EE5LTCH_Pos       (24U)
+#define HRTIM_EEFR1_EE5LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE5LTCH_Pos)       /*!< 0x01000000 */
+#define HRTIM_EEFR1_EE5LTCH           HRTIM_EEFR1_EE5LTCH_Msk                  /*!< External Event 5 latch */
+#define HRTIM_EEFR1_EE5FLTR_Pos       (25U)
+#define HRTIM_EEFR1_EE5FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE5FLTR_Pos)       /*!< 0x1E000000 */
+#define HRTIM_EEFR1_EE5FLTR           HRTIM_EEFR1_EE5FLTR_Msk                  /*!< External Event 5 filter mask */
+#define HRTIM_EEFR1_EE5FLTR_0         (0x1UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x02000000 */
+#define HRTIM_EEFR1_EE5FLTR_1         (0x2UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x04000000 */
+#define HRTIM_EEFR1_EE5FLTR_2         (0x4UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x08000000 */
+#define HRTIM_EEFR1_EE5FLTR_3         (0x8UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x10000000 */
+
+/**** Bit definition for Slave external event filtering  register 2 ***********/
+#define HRTIM_EEFR2_EE6LTCH_Pos       (0U)
+#define HRTIM_EEFR2_EE6LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE6LTCH_Pos)       /*!< 0x00000001 */
+#define HRTIM_EEFR2_EE6LTCH           HRTIM_EEFR2_EE6LTCH_Msk                  /*!< External Event 6 latch */
+#define HRTIM_EEFR2_EE6FLTR_Pos       (1U)
+#define HRTIM_EEFR2_EE6FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE6FLTR_Pos)       /*!< 0x0000001E */
+#define HRTIM_EEFR2_EE6FLTR           HRTIM_EEFR2_EE6FLTR_Msk                  /*!< External Event 6 filter mask */
+#define HRTIM_EEFR2_EE6FLTR_0         (0x1UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000002 */
+#define HRTIM_EEFR2_EE6FLTR_1         (0x2UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000004 */
+#define HRTIM_EEFR2_EE6FLTR_2         (0x4UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000008 */
+#define HRTIM_EEFR2_EE6FLTR_3         (0x8UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000010 */
+
+#define HRTIM_EEFR2_EE7LTCH_Pos       (6U)
+#define HRTIM_EEFR2_EE7LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE7LTCH_Pos)       /*!< 0x00000040 */
+#define HRTIM_EEFR2_EE7LTCH           HRTIM_EEFR2_EE7LTCH_Msk                  /*!< External Event 7 latch */
+#define HRTIM_EEFR2_EE7FLTR_Pos       (7U)
+#define HRTIM_EEFR2_EE7FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE7FLTR_Pos)       /*!< 0x00000780 */
+#define HRTIM_EEFR2_EE7FLTR           HRTIM_EEFR2_EE7FLTR_Msk                  /*!< External Event 7 filter mask */
+#define HRTIM_EEFR2_EE7FLTR_0         (0x1UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000080 */
+#define HRTIM_EEFR2_EE7FLTR_1         (0x2UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000100 */
+#define HRTIM_EEFR2_EE7FLTR_2         (0x4UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000200 */
+#define HRTIM_EEFR2_EE7FLTR_3         (0x8UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000400 */
+
+#define HRTIM_EEFR2_EE8LTCH_Pos       (12U)
+#define HRTIM_EEFR2_EE8LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE8LTCH_Pos)       /*!< 0x00001000 */
+#define HRTIM_EEFR2_EE8LTCH           HRTIM_EEFR2_EE8LTCH_Msk                  /*!< External Event 8 latch */
+#define HRTIM_EEFR2_EE8FLTR_Pos       (13U)
+#define HRTIM_EEFR2_EE8FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE8FLTR_Pos)       /*!< 0x0001E000 */
+#define HRTIM_EEFR2_EE8FLTR           HRTIM_EEFR2_EE8FLTR_Msk                  /*!< External Event 8 filter mask */
+#define HRTIM_EEFR2_EE8FLTR_0         (0x1UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00002000 */
+#define HRTIM_EEFR2_EE8FLTR_1         (0x2UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00004000 */
+#define HRTIM_EEFR2_EE8FLTR_2         (0x4UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00008000 */
+#define HRTIM_EEFR2_EE8FLTR_3         (0x8UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00010000 */
+
+#define HRTIM_EEFR2_EE9LTCH_Pos       (18U)
+#define HRTIM_EEFR2_EE9LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE9LTCH_Pos)       /*!< 0x00040000 */
+#define HRTIM_EEFR2_EE9LTCH           HRTIM_EEFR2_EE9LTCH_Msk                  /*!< External Event 9 latch */
+#define HRTIM_EEFR2_EE9FLTR_Pos       (19U)
+#define HRTIM_EEFR2_EE9FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE9FLTR_Pos)       /*!< 0x00780000 */
+#define HRTIM_EEFR2_EE9FLTR           HRTIM_EEFR2_EE9FLTR_Msk                  /*!< External Event 9 filter mask */
+#define HRTIM_EEFR2_EE9FLTR_0         (0x1UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00080000 */
+#define HRTIM_EEFR2_EE9FLTR_1         (0x2UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00100000 */
+#define HRTIM_EEFR2_EE9FLTR_2         (0x4UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00200000 */
+#define HRTIM_EEFR2_EE9FLTR_3         (0x8UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00400000 */
+
+#define HRTIM_EEFR2_EE10LTCH_Pos      (24U)
+#define HRTIM_EEFR2_EE10LTCH_Msk      (0x1UL << HRTIM_EEFR2_EE10LTCH_Pos)      /*!< 0x01000000 */
+#define HRTIM_EEFR2_EE10LTCH          HRTIM_EEFR2_EE10LTCH_Msk                 /*!< External Event 10 latch */
+#define HRTIM_EEFR2_EE10FLTR_Pos      (25U)
+#define HRTIM_EEFR2_EE10FLTR_Msk      (0xFUL << HRTIM_EEFR2_EE10FLTR_Pos)      /*!< 0x1E000000 */
+#define HRTIM_EEFR2_EE10FLTR          HRTIM_EEFR2_EE10FLTR_Msk                 /*!< External Event 10 filter mask */
+#define HRTIM_EEFR2_EE10FLTR_0        (0x1UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x02000000 */
+#define HRTIM_EEFR2_EE10FLTR_1        (0x2UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x04000000 */
+#define HRTIM_EEFR2_EE10FLTR_2        (0x4UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x08000000 */
+#define HRTIM_EEFR2_EE10FLTR_3        (0x8UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x10000000 */
+
+/**** Bit definition for Slave Timer reset register ***************************/
+#define HRTIM_RSTR_UPDATE_Pos         (1U)
+#define HRTIM_RSTR_UPDATE_Msk         (0x1UL << HRTIM_RSTR_UPDATE_Pos)         /*!< 0x00000002 */
+#define HRTIM_RSTR_UPDATE             HRTIM_RSTR_UPDATE_Msk                    /*!< Timer update */
+#define HRTIM_RSTR_CMP2_Pos           (2U)
+#define HRTIM_RSTR_CMP2_Msk           (0x1UL << HRTIM_RSTR_CMP2_Pos)           /*!< 0x00000004 */
+#define HRTIM_RSTR_CMP2               HRTIM_RSTR_CMP2_Msk                      /*!< Timer compare2 */
+#define HRTIM_RSTR_CMP4_Pos           (3U)
+#define HRTIM_RSTR_CMP4_Msk           (0x1UL << HRTIM_RSTR_CMP4_Pos)           /*!< 0x00000008 */
+#define HRTIM_RSTR_CMP4               HRTIM_RSTR_CMP4_Msk                      /*!< Timer compare4 */
+
+#define HRTIM_RSTR_MSTPER_Pos         (4U)
+#define HRTIM_RSTR_MSTPER_Msk         (0x1UL << HRTIM_RSTR_MSTPER_Pos)         /*!< 0x00000010 */
+#define HRTIM_RSTR_MSTPER             HRTIM_RSTR_MSTPER_Msk                    /*!< Master period */
+#define HRTIM_RSTR_MSTCMP1_Pos        (5U)
+#define HRTIM_RSTR_MSTCMP1_Msk        (0x1UL << HRTIM_RSTR_MSTCMP1_Pos)        /*!< 0x00000020 */
+#define HRTIM_RSTR_MSTCMP1            HRTIM_RSTR_MSTCMP1_Msk                   /*!< Master compare1 */
+#define HRTIM_RSTR_MSTCMP2_Pos        (6U)
+#define HRTIM_RSTR_MSTCMP2_Msk        (0x1UL << HRTIM_RSTR_MSTCMP2_Pos)        /*!< 0x00000040 */
+#define HRTIM_RSTR_MSTCMP2            HRTIM_RSTR_MSTCMP2_Msk                   /*!< Master compare2 */
+#define HRTIM_RSTR_MSTCMP3_Pos        (7U)
+#define HRTIM_RSTR_MSTCMP3_Msk        (0x1UL << HRTIM_RSTR_MSTCMP3_Pos)        /*!< 0x00000080 */
+#define HRTIM_RSTR_MSTCMP3            HRTIM_RSTR_MSTCMP3_Msk                   /*!< Master compare3 */
+#define HRTIM_RSTR_MSTCMP4_Pos        (8U)
+#define HRTIM_RSTR_MSTCMP4_Msk        (0x1UL << HRTIM_RSTR_MSTCMP4_Pos)        /*!< 0x00000100 */
+#define HRTIM_RSTR_MSTCMP4            HRTIM_RSTR_MSTCMP4_Msk                   /*!< Master compare4 */
+
+#define HRTIM_RSTR_EXTEVNT1_Pos       (9U)
+#define HRTIM_RSTR_EXTEVNT1_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT1_Pos)       /*!< 0x00000200 */
+#define HRTIM_RSTR_EXTEVNT1           HRTIM_RSTR_EXTEVNT1_Msk                  /*!< External event 1 */
+#define HRTIM_RSTR_EXTEVNT2_Pos       (10U)
+#define HRTIM_RSTR_EXTEVNT2_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT2_Pos)       /*!< 0x00000400 */
+#define HRTIM_RSTR_EXTEVNT2           HRTIM_RSTR_EXTEVNT2_Msk                  /*!< External event 2 */
+#define HRTIM_RSTR_EXTEVNT3_Pos       (11U)
+#define HRTIM_RSTR_EXTEVNT3_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT3_Pos)       /*!< 0x00000800 */
+#define HRTIM_RSTR_EXTEVNT3           HRTIM_RSTR_EXTEVNT3_Msk                  /*!< External event 3 */
+#define HRTIM_RSTR_EXTEVNT4_Pos       (12U)
+#define HRTIM_RSTR_EXTEVNT4_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT4_Pos)       /*!< 0x00001000 */
+#define HRTIM_RSTR_EXTEVNT4           HRTIM_RSTR_EXTEVNT4_Msk                  /*!< External event 4 */
+#define HRTIM_RSTR_EXTEVNT5_Pos       (13U)
+#define HRTIM_RSTR_EXTEVNT5_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT5_Pos)       /*!< 0x00002000 */
+#define HRTIM_RSTR_EXTEVNT5           HRTIM_RSTR_EXTEVNT5_Msk                  /*!< External event 5 */
+#define HRTIM_RSTR_EXTEVNT6_Pos       (14U)
+#define HRTIM_RSTR_EXTEVNT6_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT6_Pos)       /*!< 0x00004000 */
+#define HRTIM_RSTR_EXTEVNT6           HRTIM_RSTR_EXTEVNT6_Msk                  /*!< External event 6 */
+#define HRTIM_RSTR_EXTEVNT7_Pos       (15U)
+#define HRTIM_RSTR_EXTEVNT7_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT7_Pos)       /*!< 0x00008000 */
+#define HRTIM_RSTR_EXTEVNT7           HRTIM_RSTR_EXTEVNT7_Msk                  /*!< External event 7 */
+#define HRTIM_RSTR_EXTEVNT8_Pos       (16U)
+#define HRTIM_RSTR_EXTEVNT8_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT8_Pos)       /*!< 0x00010000 */
+#define HRTIM_RSTR_EXTEVNT8           HRTIM_RSTR_EXTEVNT8_Msk                  /*!< External event 8 */
+#define HRTIM_RSTR_EXTEVNT9_Pos       (17U)
+#define HRTIM_RSTR_EXTEVNT9_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT9_Pos)       /*!< 0x00020000 */
+#define HRTIM_RSTR_EXTEVNT9           HRTIM_RSTR_EXTEVNT9_Msk                  /*!< External event 9 */
+#define HRTIM_RSTR_EXTEVNT10_Pos      (18U)
+#define HRTIM_RSTR_EXTEVNT10_Msk      (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos)      /*!< 0x00040000 */
+#define HRTIM_RSTR_EXTEVNT10          HRTIM_RSTR_EXTEVNT10_Msk                 /*!< External event 10 */
+
+#define HRTIM_RSTR_TIMBCMP1_Pos       (19U)
+#define HRTIM_RSTR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos)       /*!< 0x00080000 */
+#define HRTIM_RSTR_TIMBCMP1           HRTIM_RSTR_TIMBCMP1_Msk                  /*!< Timer B compare 1 */
+#define HRTIM_RSTR_TIMBCMP2_Pos       (20U)
+#define HRTIM_RSTR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP2_Pos)       /*!< 0x00100000 */
+#define HRTIM_RSTR_TIMBCMP2           HRTIM_RSTR_TIMBCMP2_Msk                  /*!< Timer B compare 2 */
+#define HRTIM_RSTR_TIMBCMP4_Pos       (21U)
+#define HRTIM_RSTR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP4_Pos)       /*!< 0x00200000 */
+#define HRTIM_RSTR_TIMBCMP4           HRTIM_RSTR_TIMBCMP4_Msk                  /*!< Timer B compare 4 */
+
+#define HRTIM_RSTR_TIMCCMP1_Pos       (22U)
+#define HRTIM_RSTR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP1_Pos)       /*!< 0x00400000 */
+#define HRTIM_RSTR_TIMCCMP1           HRTIM_RSTR_TIMCCMP1_Msk                  /*!< Timer C compare 1 */
+#define HRTIM_RSTR_TIMCCMP2_Pos       (23U)
+#define HRTIM_RSTR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP2_Pos)       /*!< 0x00800000 */
+#define HRTIM_RSTR_TIMCCMP2           HRTIM_RSTR_TIMCCMP2_Msk                  /*!< Timer C compare 2 */
+#define HRTIM_RSTR_TIMCCMP4_Pos       (24U)
+#define HRTIM_RSTR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP4_Pos)       /*!< 0x01000000 */
+#define HRTIM_RSTR_TIMCCMP4           HRTIM_RSTR_TIMCCMP4_Msk                  /*!< Timer C compare 4 */
+
+#define HRTIM_RSTR_TIMDCMP1_Pos       (25U)
+#define HRTIM_RSTR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP1_Pos)       /*!< 0x02000000 */
+#define HRTIM_RSTR_TIMDCMP1           HRTIM_RSTR_TIMDCMP1_Msk                  /*!< Timer D compare 1 */
+#define HRTIM_RSTR_TIMDCMP2_Pos       (26U)
+#define HRTIM_RSTR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP2_Pos)       /*!< 0x04000000 */
+#define HRTIM_RSTR_TIMDCMP2           HRTIM_RSTR_TIMDCMP2_Msk                  /*!< Timer D compare 2 */
+#define HRTIM_RSTR_TIMDCMP4_Pos       (27U)
+#define HRTIM_RSTR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP4_Pos)       /*!< 0x08000000 */
+#define HRTIM_RSTR_TIMDCMP4           HRTIM_RSTR_TIMDCMP4_Msk                  /*!< Timer D compare 4 */
+
+#define HRTIM_RSTR_TIMECMP1_Pos       (28U)
+#define HRTIM_RSTR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTR_TIMECMP1_Pos)       /*!< 0x10000000 */
+#define HRTIM_RSTR_TIMECMP1           HRTIM_RSTR_TIMECMP1_Msk                  /*!< Timer E compare 1 */
+#define HRTIM_RSTR_TIMECMP2_Pos       (29U)
+#define HRTIM_RSTR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTR_TIMECMP2_Pos)       /*!< 0x20000000 */
+#define HRTIM_RSTR_TIMECMP2           HRTIM_RSTR_TIMECMP2_Msk                  /*!< Timer E compare 2 */
+#define HRTIM_RSTR_TIMECMP4_Pos       (30U)
+#define HRTIM_RSTR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTR_TIMECMP4_Pos)       /*!< 0x40000000 */
+#define HRTIM_RSTR_TIMECMP4           HRTIM_RSTR_TIMECMP4_Msk                  /*!< Timer E compare 4 */
+
+/**** Bit definition for Slave Timer Chopper register *************************/
+#define HRTIM_CHPR_CARFRQ_Pos         (0U)
+#define HRTIM_CHPR_CARFRQ_Msk         (0xFUL << HRTIM_CHPR_CARFRQ_Pos)         /*!< 0x0000000F */
+#define HRTIM_CHPR_CARFRQ             HRTIM_CHPR_CARFRQ_Msk                    /*!< Timer carrier frequency value */
+#define HRTIM_CHPR_CARFRQ_0           (0x1UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000001 */
+#define HRTIM_CHPR_CARFRQ_1           (0x2UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000002 */
+#define HRTIM_CHPR_CARFRQ_2           (0x4UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000004 */
+#define HRTIM_CHPR_CARFRQ_3           (0x8UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000008 */
+
+#define HRTIM_CHPR_CARDTY_Pos         (4U)
+#define HRTIM_CHPR_CARDTY_Msk         (0x7UL << HRTIM_CHPR_CARDTY_Pos)         /*!< 0x00000070 */
+#define HRTIM_CHPR_CARDTY             HRTIM_CHPR_CARDTY_Msk                    /*!< Timer chopper duty cycle value */
+#define HRTIM_CHPR_CARDTY_0           (0x1UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000010 */
+#define HRTIM_CHPR_CARDTY_1           (0x2UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000020 */
+#define HRTIM_CHPR_CARDTY_2           (0x4UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000040 */
+
+#define HRTIM_CHPR_STRPW_Pos          (7U)
+#define HRTIM_CHPR_STRPW_Msk          (0xFUL << HRTIM_CHPR_STRPW_Pos)          /*!< 0x00000780 */
+#define HRTIM_CHPR_STRPW              HRTIM_CHPR_STRPW_Msk                     /*!< Timer start pulse width value */
+#define HRTIM_CHPR_STRPW_0            (0x1UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000080 */
+#define HRTIM_CHPR_STRPW_1            (0x2UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000100 */
+#define HRTIM_CHPR_STRPW_2            (0x4UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000200 */
+#define HRTIM_CHPR_STRPW_3            (0x8UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000400 */
+
+/**** Bit definition for Slave Timer Capture 1 control register ***************/
+#define HRTIM_CPT1CR_SWCPT_Pos        (0U)
+#define HRTIM_CPT1CR_SWCPT_Msk        (0x1UL << HRTIM_CPT1CR_SWCPT_Pos)        /*!< 0x00000001 */
+#define HRTIM_CPT1CR_SWCPT            HRTIM_CPT1CR_SWCPT_Msk                   /*!< Software capture */
+#define HRTIM_CPT1CR_UPDCPT_Pos       (1U)
+#define HRTIM_CPT1CR_UPDCPT_Msk       (0x1UL << HRTIM_CPT1CR_UPDCPT_Pos)       /*!< 0x00000002 */
+#define HRTIM_CPT1CR_UPDCPT           HRTIM_CPT1CR_UPDCPT_Msk                  /*!< Update capture */
+#define HRTIM_CPT1CR_EXEV1CPT_Pos     (2U)
+#define HRTIM_CPT1CR_EXEV1CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV1CPT_Pos)     /*!< 0x00000004 */
+#define HRTIM_CPT1CR_EXEV1CPT         HRTIM_CPT1CR_EXEV1CPT_Msk                /*!< External event 1 capture */
+#define HRTIM_CPT1CR_EXEV2CPT_Pos     (3U)
+#define HRTIM_CPT1CR_EXEV2CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV2CPT_Pos)     /*!< 0x00000008 */
+#define HRTIM_CPT1CR_EXEV2CPT         HRTIM_CPT1CR_EXEV2CPT_Msk                /*!< External event 2 capture */
+#define HRTIM_CPT1CR_EXEV3CPT_Pos     (4U)
+#define HRTIM_CPT1CR_EXEV3CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV3CPT_Pos)     /*!< 0x00000010 */
+#define HRTIM_CPT1CR_EXEV3CPT         HRTIM_CPT1CR_EXEV3CPT_Msk                /*!< External event 3 capture */
+#define HRTIM_CPT1CR_EXEV4CPT_Pos     (5U)
+#define HRTIM_CPT1CR_EXEV4CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV4CPT_Pos)     /*!< 0x00000020 */
+#define HRTIM_CPT1CR_EXEV4CPT         HRTIM_CPT1CR_EXEV4CPT_Msk                /*!< External event 4 capture */
+#define HRTIM_CPT1CR_EXEV5CPT_Pos     (6U)
+#define HRTIM_CPT1CR_EXEV5CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV5CPT_Pos)     /*!< 0x00000040 */
+#define HRTIM_CPT1CR_EXEV5CPT         HRTIM_CPT1CR_EXEV5CPT_Msk                /*!< External event 5 capture */
+#define HRTIM_CPT1CR_EXEV6CPT_Pos     (7U)
+#define HRTIM_CPT1CR_EXEV6CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV6CPT_Pos)     /*!< 0x00000080 */
+#define HRTIM_CPT1CR_EXEV6CPT         HRTIM_CPT1CR_EXEV6CPT_Msk                /*!< External event 6 capture */
+#define HRTIM_CPT1CR_EXEV7CPT_Pos     (8U)
+#define HRTIM_CPT1CR_EXEV7CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV7CPT_Pos)     /*!< 0x00000100 */
+#define HRTIM_CPT1CR_EXEV7CPT         HRTIM_CPT1CR_EXEV7CPT_Msk                /*!< External event 7 capture */
+#define HRTIM_CPT1CR_EXEV8CPT_Pos     (9U)
+#define HRTIM_CPT1CR_EXEV8CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV8CPT_Pos)     /*!< 0x00000200 */
+#define HRTIM_CPT1CR_EXEV8CPT         HRTIM_CPT1CR_EXEV8CPT_Msk                /*!< External event 8 capture */
+#define HRTIM_CPT1CR_EXEV9CPT_Pos     (10U)
+#define HRTIM_CPT1CR_EXEV9CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV9CPT_Pos)     /*!< 0x00000400 */
+#define HRTIM_CPT1CR_EXEV9CPT         HRTIM_CPT1CR_EXEV9CPT_Msk                /*!< External event 9 capture */
+#define HRTIM_CPT1CR_EXEV10CPT_Pos    (11U)
+#define HRTIM_CPT1CR_EXEV10CPT_Msk    (0x1UL << HRTIM_CPT1CR_EXEV10CPT_Pos)    /*!< 0x00000800 */
+#define HRTIM_CPT1CR_EXEV10CPT        HRTIM_CPT1CR_EXEV10CPT_Msk               /*!< External event 10 capture */
+
+#define HRTIM_CPT1CR_TA1SET_Pos       (12U)
+#define HRTIM_CPT1CR_TA1SET_Msk       (0x1UL << HRTIM_CPT1CR_TA1SET_Pos)       /*!< 0x00001000 */
+#define HRTIM_CPT1CR_TA1SET           HRTIM_CPT1CR_TA1SET_Msk                  /*!< Timer A output 1 set */
+#define HRTIM_CPT1CR_TA1RST_Pos       (13U)
+#define HRTIM_CPT1CR_TA1RST_Msk       (0x1UL << HRTIM_CPT1CR_TA1RST_Pos)       /*!< 0x00002000 */
+#define HRTIM_CPT1CR_TA1RST           HRTIM_CPT1CR_TA1RST_Msk                  /*!< Timer A output 1 reset */
+#define HRTIM_CPT1CR_TIMACMP1_Pos     (14U)
+#define HRTIM_CPT1CR_TIMACMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMACMP1_Pos)     /*!< 0x00004000 */
+#define HRTIM_CPT1CR_TIMACMP1         HRTIM_CPT1CR_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_CPT1CR_TIMACMP2_Pos     (15U)
+#define HRTIM_CPT1CR_TIMACMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMACMP2_Pos)     /*!< 0x00008000 */
+#define HRTIM_CPT1CR_TIMACMP2         HRTIM_CPT1CR_TIMACMP2_Msk                /*!< Timer A compare 2 */
+
+#define HRTIM_CPT1CR_TB1SET_Pos       (16U)
+#define HRTIM_CPT1CR_TB1SET_Msk       (0x1UL << HRTIM_CPT1CR_TB1SET_Pos)       /*!< 0x00010000 */
+#define HRTIM_CPT1CR_TB1SET           HRTIM_CPT1CR_TB1SET_Msk                  /*!< Timer B output 1 set */
+#define HRTIM_CPT1CR_TB1RST_Pos       (17U)
+#define HRTIM_CPT1CR_TB1RST_Msk       (0x1UL << HRTIM_CPT1CR_TB1RST_Pos)       /*!< 0x00020000 */
+#define HRTIM_CPT1CR_TB1RST           HRTIM_CPT1CR_TB1RST_Msk                  /*!< Timer B output 1 reset */
+#define HRTIM_CPT1CR_TIMBCMP1_Pos     (18U)
+#define HRTIM_CPT1CR_TIMBCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMBCMP1_Pos)     /*!< 0x00040000 */
+#define HRTIM_CPT1CR_TIMBCMP1         HRTIM_CPT1CR_TIMBCMP1_Msk                /*!< Timer B compare 1 */
+#define HRTIM_CPT1CR_TIMBCMP2_Pos     (19U)
+#define HRTIM_CPT1CR_TIMBCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMBCMP2_Pos)     /*!< 0x00080000 */
+#define HRTIM_CPT1CR_TIMBCMP2         HRTIM_CPT1CR_TIMBCMP2_Msk                /*!< Timer B compare 2 */
+
+#define HRTIM_CPT1CR_TC1SET_Pos       (20U)
+#define HRTIM_CPT1CR_TC1SET_Msk       (0x1UL << HRTIM_CPT1CR_TC1SET_Pos)       /*!< 0x00100000 */
+#define HRTIM_CPT1CR_TC1SET           HRTIM_CPT1CR_TC1SET_Msk                  /*!< Timer C output 1 set */
+#define HRTIM_CPT1CR_TC1RST_Pos       (21U)
+#define HRTIM_CPT1CR_TC1RST_Msk       (0x1UL << HRTIM_CPT1CR_TC1RST_Pos)       /*!< 0x00200000 */
+#define HRTIM_CPT1CR_TC1RST           HRTIM_CPT1CR_TC1RST_Msk                  /*!< Timer C output 1 reset */
+#define HRTIM_CPT1CR_TIMCCMP1_Pos     (22U)
+#define HRTIM_CPT1CR_TIMCCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMCCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_CPT1CR_TIMCCMP1         HRTIM_CPT1CR_TIMCCMP1_Msk                /*!< Timer C compare 1 */
+#define HRTIM_CPT1CR_TIMCCMP2_Pos     (23U)
+#define HRTIM_CPT1CR_TIMCCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMCCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_CPT1CR_TIMCCMP2         HRTIM_CPT1CR_TIMCCMP2_Msk                /*!< Timer C compare 2 */
+
+#define HRTIM_CPT1CR_TD1SET_Pos       (24U)
+#define HRTIM_CPT1CR_TD1SET_Msk       (0x1UL << HRTIM_CPT1CR_TD1SET_Pos)       /*!< 0x01000000 */
+#define HRTIM_CPT1CR_TD1SET           HRTIM_CPT1CR_TD1SET_Msk                  /*!< Timer D output 1 set */
+#define HRTIM_CPT1CR_TD1RST_Pos       (25U)
+#define HRTIM_CPT1CR_TD1RST_Msk       (0x1UL << HRTIM_CPT1CR_TD1RST_Pos)       /*!< 0x02000000 */
+#define HRTIM_CPT1CR_TD1RST           HRTIM_CPT1CR_TD1RST_Msk                  /*!< Timer D output 1 reset */
+#define HRTIM_CPT1CR_TIMDCMP1_Pos     (26U)
+#define HRTIM_CPT1CR_TIMDCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMDCMP1_Pos)     /*!< 0x04000000 */
+#define HRTIM_CPT1CR_TIMDCMP1         HRTIM_CPT1CR_TIMDCMP1_Msk                /*!< Timer D compare 1 */
+#define HRTIM_CPT1CR_TIMDCMP2_Pos     (27U)
+#define HRTIM_CPT1CR_TIMDCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMDCMP2_Pos)     /*!< 0x08000000 */
+#define HRTIM_CPT1CR_TIMDCMP2         HRTIM_CPT1CR_TIMDCMP2_Msk                /*!< Timer D compare 2 */
+
+#define HRTIM_CPT1CR_TE1SET_Pos       (28U)
+#define HRTIM_CPT1CR_TE1SET_Msk       (0x1UL << HRTIM_CPT1CR_TE1SET_Pos)       /*!< 0x10000000 */
+#define HRTIM_CPT1CR_TE1SET           HRTIM_CPT1CR_TE1SET_Msk                  /*!< Timer E output 1 set */
+#define HRTIM_CPT1CR_TE1RST_Pos       (29U)
+#define HRTIM_CPT1CR_TE1RST_Msk       (0x1UL << HRTIM_CPT1CR_TE1RST_Pos)       /*!< 0x20000000 */
+#define HRTIM_CPT1CR_TE1RST           HRTIM_CPT1CR_TE1RST_Msk                  /*!< Timer E output 1 reset */
+#define HRTIM_CPT1CR_TIMECMP1_Pos     (30U)
+#define HRTIM_CPT1CR_TIMECMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMECMP1_Pos)     /*!< 0x40000000 */
+#define HRTIM_CPT1CR_TIMECMP1         HRTIM_CPT1CR_TIMECMP1_Msk                /*!< Timer E compare 1 */
+#define HRTIM_CPT1CR_TIMECMP2_Pos     (31U)
+#define HRTIM_CPT1CR_TIMECMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMECMP2_Pos)     /*!< 0x80000000 */
+#define HRTIM_CPT1CR_TIMECMP2         HRTIM_CPT1CR_TIMECMP2_Msk                /*!< Timer E compare 2 */
+
+/**** Bit definition for Slave Timer Capture 2 control register ***************/
+#define HRTIM_CPT2CR_SWCPT_Pos        (0U)
+#define HRTIM_CPT2CR_SWCPT_Msk        (0x1UL << HRTIM_CPT2CR_SWCPT_Pos)        /*!< 0x00000001 */
+#define HRTIM_CPT2CR_SWCPT            HRTIM_CPT2CR_SWCPT_Msk                   /*!< Software capture */
+#define HRTIM_CPT2CR_UPDCPT_Pos       (1U)
+#define HRTIM_CPT2CR_UPDCPT_Msk       (0x1UL << HRTIM_CPT2CR_UPDCPT_Pos)       /*!< 0x00000002 */
+#define HRTIM_CPT2CR_UPDCPT           HRTIM_CPT2CR_UPDCPT_Msk                  /*!< Update capture */
+#define HRTIM_CPT2CR_EXEV1CPT_Pos     (2U)
+#define HRTIM_CPT2CR_EXEV1CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV1CPT_Pos)     /*!< 0x00000004 */
+#define HRTIM_CPT2CR_EXEV1CPT         HRTIM_CPT2CR_EXEV1CPT_Msk                /*!< External event 1 capture */
+#define HRTIM_CPT2CR_EXEV2CPT_Pos     (3U)
+#define HRTIM_CPT2CR_EXEV2CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV2CPT_Pos)     /*!< 0x00000008 */
+#define HRTIM_CPT2CR_EXEV2CPT         HRTIM_CPT2CR_EXEV2CPT_Msk                /*!< External event 2 capture */
+#define HRTIM_CPT2CR_EXEV3CPT_Pos     (4U)
+#define HRTIM_CPT2CR_EXEV3CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV3CPT_Pos)     /*!< 0x00000010 */
+#define HRTIM_CPT2CR_EXEV3CPT         HRTIM_CPT2CR_EXEV3CPT_Msk                /*!< External event 3 capture */
+#define HRTIM_CPT2CR_EXEV4CPT_Pos     (5U)
+#define HRTIM_CPT2CR_EXEV4CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV4CPT_Pos)     /*!< 0x00000020 */
+#define HRTIM_CPT2CR_EXEV4CPT         HRTIM_CPT2CR_EXEV4CPT_Msk                /*!< External event 4 capture */
+#define HRTIM_CPT2CR_EXEV5CPT_Pos     (6U)
+#define HRTIM_CPT2CR_EXEV5CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV5CPT_Pos)     /*!< 0x00000040 */
+#define HRTIM_CPT2CR_EXEV5CPT         HRTIM_CPT2CR_EXEV5CPT_Msk                /*!< External event 5 capture */
+#define HRTIM_CPT2CR_EXEV6CPT_Pos     (7U)
+#define HRTIM_CPT2CR_EXEV6CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV6CPT_Pos)     /*!< 0x00000080 */
+#define HRTIM_CPT2CR_EXEV6CPT         HRTIM_CPT2CR_EXEV6CPT_Msk                /*!< External event 6 capture */
+#define HRTIM_CPT2CR_EXEV7CPT_Pos     (8U)
+#define HRTIM_CPT2CR_EXEV7CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV7CPT_Pos)     /*!< 0x00000100 */
+#define HRTIM_CPT2CR_EXEV7CPT         HRTIM_CPT2CR_EXEV7CPT_Msk                /*!< External event 7 capture */
+#define HRTIM_CPT2CR_EXEV8CPT_Pos     (9U)
+#define HRTIM_CPT2CR_EXEV8CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV8CPT_Pos)     /*!< 0x00000200 */
+#define HRTIM_CPT2CR_EXEV8CPT         HRTIM_CPT2CR_EXEV8CPT_Msk                /*!< External event 8 capture */
+#define HRTIM_CPT2CR_EXEV9CPT_Pos     (10U)
+#define HRTIM_CPT2CR_EXEV9CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV9CPT_Pos)     /*!< 0x00000400 */
+#define HRTIM_CPT2CR_EXEV9CPT         HRTIM_CPT2CR_EXEV9CPT_Msk                /*!< External event 9 capture */
+#define HRTIM_CPT2CR_EXEV10CPT_Pos    (11U)
+#define HRTIM_CPT2CR_EXEV10CPT_Msk    (0x1UL << HRTIM_CPT2CR_EXEV10CPT_Pos)    /*!< 0x00000800 */
+#define HRTIM_CPT2CR_EXEV10CPT        HRTIM_CPT2CR_EXEV10CPT_Msk               /*!< External event 10 capture */
+
+#define HRTIM_CPT2CR_TA1SET_Pos       (12U)
+#define HRTIM_CPT2CR_TA1SET_Msk       (0x1UL << HRTIM_CPT2CR_TA1SET_Pos)       /*!< 0x00001000 */
+#define HRTIM_CPT2CR_TA1SET           HRTIM_CPT2CR_TA1SET_Msk                  /*!< Timer A output 1 set */
+#define HRTIM_CPT2CR_TA1RST_Pos       (13U)
+#define HRTIM_CPT2CR_TA1RST_Msk       (0x1UL << HRTIM_CPT2CR_TA1RST_Pos)       /*!< 0x00002000 */
+#define HRTIM_CPT2CR_TA1RST           HRTIM_CPT2CR_TA1RST_Msk                  /*!< Timer A output 1 reset */
+#define HRTIM_CPT2CR_TIMACMP1_Pos     (14U)
+#define HRTIM_CPT2CR_TIMACMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMACMP1_Pos)     /*!< 0x00004000 */
+#define HRTIM_CPT2CR_TIMACMP1         HRTIM_CPT2CR_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_CPT2CR_TIMACMP2_Pos     (15U)
+#define HRTIM_CPT2CR_TIMACMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMACMP2_Pos)     /*!< 0x00008000 */
+#define HRTIM_CPT2CR_TIMACMP2         HRTIM_CPT2CR_TIMACMP2_Msk                /*!< Timer A compare 2 */
+
+#define HRTIM_CPT2CR_TB1SET_Pos       (16U)
+#define HRTIM_CPT2CR_TB1SET_Msk       (0x1UL << HRTIM_CPT2CR_TB1SET_Pos)       /*!< 0x00010000 */
+#define HRTIM_CPT2CR_TB1SET           HRTIM_CPT2CR_TB1SET_Msk                  /*!< Timer B output 1 set */
+#define HRTIM_CPT2CR_TB1RST_Pos       (17U)
+#define HRTIM_CPT2CR_TB1RST_Msk       (0x1UL << HRTIM_CPT2CR_TB1RST_Pos)       /*!< 0x00020000 */
+#define HRTIM_CPT2CR_TB1RST           HRTIM_CPT2CR_TB1RST_Msk                  /*!< Timer B output 1 reset */
+#define HRTIM_CPT2CR_TIMBCMP1_Pos     (18U)
+#define HRTIM_CPT2CR_TIMBCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMBCMP1_Pos)     /*!< 0x00040000 */
+#define HRTIM_CPT2CR_TIMBCMP1         HRTIM_CPT2CR_TIMBCMP1_Msk                /*!< Timer B compare 1 */
+#define HRTIM_CPT2CR_TIMBCMP2_Pos     (19U)
+#define HRTIM_CPT2CR_TIMBCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMBCMP2_Pos)     /*!< 0x00080000 */
+#define HRTIM_CPT2CR_TIMBCMP2         HRTIM_CPT2CR_TIMBCMP2_Msk                /*!< Timer B compare 2 */
+
+#define HRTIM_CPT2CR_TC1SET_Pos       (20U)
+#define HRTIM_CPT2CR_TC1SET_Msk       (0x1UL << HRTIM_CPT2CR_TC1SET_Pos)       /*!< 0x00100000 */
+#define HRTIM_CPT2CR_TC1SET           HRTIM_CPT2CR_TC1SET_Msk                  /*!< Timer C output 1 set */
+#define HRTIM_CPT2CR_TC1RST_Pos       (21U)
+#define HRTIM_CPT2CR_TC1RST_Msk       (0x1UL << HRTIM_CPT2CR_TC1RST_Pos)       /*!< 0x00200000 */
+#define HRTIM_CPT2CR_TC1RST           HRTIM_CPT2CR_TC1RST_Msk                  /*!< Timer C output 1 reset */
+#define HRTIM_CPT2CR_TIMCCMP1_Pos     (22U)
+#define HRTIM_CPT2CR_TIMCCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMCCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_CPT2CR_TIMCCMP1         HRTIM_CPT2CR_TIMCCMP1_Msk                /*!< Timer C compare 1 */
+#define HRTIM_CPT2CR_TIMCCMP2_Pos     (23U)
+#define HRTIM_CPT2CR_TIMCCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMCCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_CPT2CR_TIMCCMP2         HRTIM_CPT2CR_TIMCCMP2_Msk                /*!< Timer C compare 2 */
+
+#define HRTIM_CPT2CR_TD1SET_Pos       (24U)
+#define HRTIM_CPT2CR_TD1SET_Msk       (0x1UL << HRTIM_CPT2CR_TD1SET_Pos)       /*!< 0x01000000 */
+#define HRTIM_CPT2CR_TD1SET           HRTIM_CPT2CR_TD1SET_Msk                  /*!< Timer D output 1 set */
+#define HRTIM_CPT2CR_TD1RST_Pos       (25U)
+#define HRTIM_CPT2CR_TD1RST_Msk       (0x1UL << HRTIM_CPT2CR_TD1RST_Pos)       /*!< 0x02000000 */
+#define HRTIM_CPT2CR_TD1RST           HRTIM_CPT2CR_TD1RST_Msk                  /*!< Timer D output 1 reset */
+#define HRTIM_CPT2CR_TIMDCMP1_Pos     (26U)
+#define HRTIM_CPT2CR_TIMDCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMDCMP1_Pos)     /*!< 0x04000000 */
+#define HRTIM_CPT2CR_TIMDCMP1         HRTIM_CPT2CR_TIMDCMP1_Msk                /*!< Timer D compare 1 */
+#define HRTIM_CPT2CR_TIMDCMP2_Pos     (27U)
+#define HRTIM_CPT2CR_TIMDCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMDCMP2_Pos)     /*!< 0x08000000 */
+#define HRTIM_CPT2CR_TIMDCMP2         HRTIM_CPT2CR_TIMDCMP2_Msk                /*!< Timer D compare 2 */
+
+#define HRTIM_CPT2CR_TE1SET_Pos       (28U)
+#define HRTIM_CPT2CR_TE1SET_Msk       (0x1UL << HRTIM_CPT2CR_TE1SET_Pos)       /*!< 0x10000000 */
+#define HRTIM_CPT2CR_TE1SET           HRTIM_CPT2CR_TE1SET_Msk                  /*!< Timer E output 1 set */
+#define HRTIM_CPT2CR_TE1RST_Pos       (29U)
+#define HRTIM_CPT2CR_TE1RST_Msk       (0x1UL << HRTIM_CPT2CR_TE1RST_Pos)       /*!< 0x20000000 */
+#define HRTIM_CPT2CR_TE1RST           HRTIM_CPT2CR_TE1RST_Msk                  /*!< Timer E output 1 reset */
+#define HRTIM_CPT2CR_TIMECMP1_Pos     (30U)
+#define HRTIM_CPT2CR_TIMECMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMECMP1_Pos)     /*!< 0x40000000 */
+#define HRTIM_CPT2CR_TIMECMP1         HRTIM_CPT2CR_TIMECMP1_Msk                /*!< Timer E compare 1 */
+#define HRTIM_CPT2CR_TIMECMP2_Pos     (31U)
+#define HRTIM_CPT2CR_TIMECMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMECMP2_Pos)     /*!< 0x80000000 */
+#define HRTIM_CPT2CR_TIMECMP2         HRTIM_CPT2CR_TIMECMP2_Msk                /*!< Timer E compare 2 */
+
+/**** Bit definition for Slave Timer Output register **************************/
+#define HRTIM_OUTR_POL1_Pos           (1U)
+#define HRTIM_OUTR_POL1_Msk           (0x1UL << HRTIM_OUTR_POL1_Pos)           /*!< 0x00000002 */
+#define HRTIM_OUTR_POL1               HRTIM_OUTR_POL1_Msk                      /*!< Slave output 1 polarity */
+#define HRTIM_OUTR_IDLM1_Pos          (2U)
+#define HRTIM_OUTR_IDLM1_Msk          (0x1UL << HRTIM_OUTR_IDLM1_Pos)          /*!< 0x00000004 */
+#define HRTIM_OUTR_IDLM1              HRTIM_OUTR_IDLM1_Msk                     /*!< Slave output 1 idle mode */
+#define HRTIM_OUTR_IDLES1_Pos         (3U)
+#define HRTIM_OUTR_IDLES1_Msk         (0x1UL << HRTIM_OUTR_IDLES1_Pos)         /*!< 0x00000008 */
+#define HRTIM_OUTR_IDLES1             HRTIM_OUTR_IDLES1_Msk                    /*!< Slave output 1 idle state */
+#define HRTIM_OUTR_FAULT1_Pos         (4U)
+#define HRTIM_OUTR_FAULT1_Msk         (0x3UL << HRTIM_OUTR_FAULT1_Pos)         /*!< 0x00000030 */
+#define HRTIM_OUTR_FAULT1             HRTIM_OUTR_FAULT1_Msk                    /*!< Slave output 1 fault state */
+#define HRTIM_OUTR_FAULT1_0           (0x1UL << HRTIM_OUTR_FAULT1_Pos)          /*!< 0x00000010 */
+#define HRTIM_OUTR_FAULT1_1           (0x2UL << HRTIM_OUTR_FAULT1_Pos)          /*!< 0x00000020 */
+#define HRTIM_OUTR_CHP1_Pos           (6U)
+#define HRTIM_OUTR_CHP1_Msk           (0x1UL << HRTIM_OUTR_CHP1_Pos)           /*!< 0x00000040 */
+#define HRTIM_OUTR_CHP1               HRTIM_OUTR_CHP1_Msk                      /*!< Slave output 1 chopper enable */
+#define HRTIM_OUTR_DIDL1_Pos          (7U)
+#define HRTIM_OUTR_DIDL1_Msk          (0x1UL << HRTIM_OUTR_DIDL1_Pos)          /*!< 0x00000080 */
+#define HRTIM_OUTR_DIDL1              HRTIM_OUTR_DIDL1_Msk                     /*!< Slave output 1 dead time idle */
+
+#define HRTIM_OUTR_DTEN_Pos           (8U)
+#define HRTIM_OUTR_DTEN_Msk           (0x1UL << HRTIM_OUTR_DTEN_Pos)           /*!< 0x00000100 */
+#define HRTIM_OUTR_DTEN               HRTIM_OUTR_DTEN_Msk                      /*!< Slave output deadtime enable */
+#define HRTIM_OUTR_DLYPRTEN_Pos       (9U)
+#define HRTIM_OUTR_DLYPRTEN_Msk       (0x1UL << HRTIM_OUTR_DLYPRTEN_Pos)       /*!< 0x00000200 */
+#define HRTIM_OUTR_DLYPRTEN           HRTIM_OUTR_DLYPRTEN_Msk                  /*!< Slave output delay protection enable */
+#define HRTIM_OUTR_DLYPRT_Pos         (10U)
+#define HRTIM_OUTR_DLYPRT_Msk         (0x7UL << HRTIM_OUTR_DLYPRT_Pos)         /*!< 0x00001C00 */
+#define HRTIM_OUTR_DLYPRT             HRTIM_OUTR_DLYPRT_Msk                    /*!< Slave output delay protection */
+#define HRTIM_OUTR_DLYPRT_0           (0x1UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00000400 */
+#define HRTIM_OUTR_DLYPRT_1           (0x2UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00000800 */
+#define HRTIM_OUTR_DLYPRT_2           (0x4UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00001000 */
+
+#define HRTIM_OUTR_POL2_Pos           (17U)
+#define HRTIM_OUTR_POL2_Msk           (0x1UL << HRTIM_OUTR_POL2_Pos)           /*!< 0x00020000 */
+#define HRTIM_OUTR_POL2               HRTIM_OUTR_POL2_Msk                      /*!< Slave output 2 polarity */
+#define HRTIM_OUTR_IDLM2_Pos          (18U)
+#define HRTIM_OUTR_IDLM2_Msk          (0x1UL << HRTIM_OUTR_IDLM2_Pos)          /*!< 0x00040000 */
+#define HRTIM_OUTR_IDLM2              HRTIM_OUTR_IDLM2_Msk                     /*!< Slave output 2 idle mode */
+#define HRTIM_OUTR_IDLES2_Pos         (19U)
+#define HRTIM_OUTR_IDLES2_Msk         (0x1UL << HRTIM_OUTR_IDLES2_Pos)         /*!< 0x00080000 */
+#define HRTIM_OUTR_IDLES2             HRTIM_OUTR_IDLES2_Msk                    /*!< Slave output 2 idle state */
+#define HRTIM_OUTR_FAULT2_Pos         (20U)
+#define HRTIM_OUTR_FAULT2_Msk         (0x3UL << HRTIM_OUTR_FAULT2_Pos)         /*!< 0x00300000 */
+#define HRTIM_OUTR_FAULT2             HRTIM_OUTR_FAULT2_Msk                    /*!< Slave output 2 fault state */
+#define HRTIM_OUTR_FAULT2_0           (0x1UL << HRTIM_OUTR_FAULT2_Pos)          /*!< 0x00100000 */
+#define HRTIM_OUTR_FAULT2_1           (0x2UL << HRTIM_OUTR_FAULT2_Pos)          /*!< 0x00200000 */
+#define HRTIM_OUTR_CHP2_Pos           (22U)
+#define HRTIM_OUTR_CHP2_Msk           (0x1UL << HRTIM_OUTR_CHP2_Pos)           /*!< 0x00400000 */
+#define HRTIM_OUTR_CHP2               HRTIM_OUTR_CHP2_Msk                      /*!< Slave output 2 chopper enable */
+#define HRTIM_OUTR_DIDL2_Pos          (23U)
+#define HRTIM_OUTR_DIDL2_Msk          (0x1UL << HRTIM_OUTR_DIDL2_Pos)          /*!< 0x00800000 */
+#define HRTIM_OUTR_DIDL2              HRTIM_OUTR_DIDL2_Msk                     /*!< Slave output 2 dead time idle */
+
+/**** Bit definition for Slave Timer Fault register ***************************/
+#define HRTIM_FLTR_FLT1EN_Pos         (0U)
+#define HRTIM_FLTR_FLT1EN_Msk         (0x1UL << HRTIM_FLTR_FLT1EN_Pos)         /*!< 0x00000001 */
+#define HRTIM_FLTR_FLT1EN             HRTIM_FLTR_FLT1EN_Msk                    /*!< Fault 1 enable */
+#define HRTIM_FLTR_FLT2EN_Pos         (1U)
+#define HRTIM_FLTR_FLT2EN_Msk         (0x1UL << HRTIM_FLTR_FLT2EN_Pos)         /*!< 0x00000002 */
+#define HRTIM_FLTR_FLT2EN             HRTIM_FLTR_FLT2EN_Msk                    /*!< Fault 2 enable */
+#define HRTIM_FLTR_FLT3EN_Pos         (2U)
+#define HRTIM_FLTR_FLT3EN_Msk         (0x1UL << HRTIM_FLTR_FLT3EN_Pos)         /*!< 0x00000004 */
+#define HRTIM_FLTR_FLT3EN             HRTIM_FLTR_FLT3EN_Msk                    /*!< Fault 3 enable */
+#define HRTIM_FLTR_FLT4EN_Pos         (3U)
+#define HRTIM_FLTR_FLT4EN_Msk         (0x1UL << HRTIM_FLTR_FLT4EN_Pos)         /*!< 0x00000008 */
+#define HRTIM_FLTR_FLT4EN             HRTIM_FLTR_FLT4EN_Msk                    /*!< Fault 4 enable */
+#define HRTIM_FLTR_FLT5EN_Pos         (4U)
+#define HRTIM_FLTR_FLT5EN_Msk         (0x1UL << HRTIM_FLTR_FLT5EN_Pos)         /*!< 0x00000010 */
+#define HRTIM_FLTR_FLT5EN             HRTIM_FLTR_FLT5EN_Msk                    /*!< Fault 5 enable */
+#define HRTIM_FLTR_FLTLCK_Pos         (31U)
+#define HRTIM_FLTR_FLTLCK_Msk         (0x1UL << HRTIM_FLTR_FLTLCK_Pos)         /*!< 0x80000000 */
+#define HRTIM_FLTR_FLTLCK             HRTIM_FLTR_FLTLCK_Msk                    /*!< Fault sources lock */
+
+/**** Bit definition for Common HRTIM Timer control register 1 ****************/
+#define HRTIM_CR1_MUDIS_Pos           (0U)
+#define HRTIM_CR1_MUDIS_Msk           (0x1UL << HRTIM_CR1_MUDIS_Pos)           /*!< 0x00000001 */
+#define HRTIM_CR1_MUDIS               HRTIM_CR1_MUDIS_Msk                      /*!< Master update disable*/
+#define HRTIM_CR1_TAUDIS_Pos          (1U)
+#define HRTIM_CR1_TAUDIS_Msk          (0x1UL << HRTIM_CR1_TAUDIS_Pos)          /*!< 0x00000002 */
+#define HRTIM_CR1_TAUDIS              HRTIM_CR1_TAUDIS_Msk                     /*!< Timer A update disable*/
+#define HRTIM_CR1_TBUDIS_Pos          (2U)
+#define HRTIM_CR1_TBUDIS_Msk          (0x1UL << HRTIM_CR1_TBUDIS_Pos)          /*!< 0x00000004 */
+#define HRTIM_CR1_TBUDIS              HRTIM_CR1_TBUDIS_Msk                     /*!< Timer B update disable*/
+#define HRTIM_CR1_TCUDIS_Pos          (3U)
+#define HRTIM_CR1_TCUDIS_Msk          (0x1UL << HRTIM_CR1_TCUDIS_Pos)          /*!< 0x00000008 */
+#define HRTIM_CR1_TCUDIS              HRTIM_CR1_TCUDIS_Msk                     /*!< Timer C update disable*/
+#define HRTIM_CR1_TDUDIS_Pos          (4U)
+#define HRTIM_CR1_TDUDIS_Msk          (0x1UL << HRTIM_CR1_TDUDIS_Pos)          /*!< 0x00000010 */
+#define HRTIM_CR1_TDUDIS              HRTIM_CR1_TDUDIS_Msk                     /*!< Timer D update disable*/
+#define HRTIM_CR1_TEUDIS_Pos          (5U)
+#define HRTIM_CR1_TEUDIS_Msk          (0x1UL << HRTIM_CR1_TEUDIS_Pos)          /*!< 0x00000020 */
+#define HRTIM_CR1_TEUDIS              HRTIM_CR1_TEUDIS_Msk                     /*!< Timer E update disable*/
+#define HRTIM_CR1_ADC1USRC_Pos        (16U)
+#define HRTIM_CR1_ADC1USRC_Msk        (0x7UL << HRTIM_CR1_ADC1USRC_Pos)        /*!< 0x00070000 */
+#define HRTIM_CR1_ADC1USRC            HRTIM_CR1_ADC1USRC_Msk                   /*!< ADC Trigger 1 update source */
+#define HRTIM_CR1_ADC1USRC_0          (0x1UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00010000 */
+#define HRTIM_CR1_ADC1USRC_1          (0x2UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00020000 */
+#define HRTIM_CR1_ADC1USRC_2          (0x4UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00040000 */
+#define HRTIM_CR1_ADC2USRC_Pos        (19U)
+#define HRTIM_CR1_ADC2USRC_Msk        (0x7UL << HRTIM_CR1_ADC2USRC_Pos)        /*!< 0x00380000 */
+#define HRTIM_CR1_ADC2USRC            HRTIM_CR1_ADC2USRC_Msk                   /*!< ADC Trigger 2 update source */
+#define HRTIM_CR1_ADC2USRC_0          (0x1UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00080000 */
+#define HRTIM_CR1_ADC2USRC_1          (0x2UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00100000 */
+#define HRTIM_CR1_ADC2USRC_2          (0x4UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00200000 */
+#define HRTIM_CR1_ADC3USRC_Pos        (22U)
+#define HRTIM_CR1_ADC3USRC_Msk        (0x7UL << HRTIM_CR1_ADC3USRC_Pos)        /*!< 0x01C00000 */
+#define HRTIM_CR1_ADC3USRC            HRTIM_CR1_ADC3USRC_Msk                   /*!< ADC Trigger 3 update source */
+#define HRTIM_CR1_ADC3USRC_0          (0x1UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x00400000 */
+#define HRTIM_CR1_ADC3USRC_1          (0x2UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x00800000 */
+#define HRTIM_CR1_ADC3USRC_2          (0x4UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x01000000 */
+#define HRTIM_CR1_ADC4USRC_Pos        (25U)
+#define HRTIM_CR1_ADC4USRC_Msk        (0x7UL << HRTIM_CR1_ADC4USRC_Pos)        /*!< 0x0E000000 */
+#define HRTIM_CR1_ADC4USRC            HRTIM_CR1_ADC4USRC_Msk                   /*!< ADC Trigger 4 update source */
+#define HRTIM_CR1_ADC4USRC_0          (0x1UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x02000000 */
+#define HRTIM_CR1_ADC4USRC_1          (0x2UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x04000000 */
+#define HRTIM_CR1_ADC4USRC_2          (0x0UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x0800000 */
+
+/**** Bit definition for Common HRTIM Timer control register 2 ****************/
+#define HRTIM_CR2_MSWU_Pos            (0U)
+#define HRTIM_CR2_MSWU_Msk            (0x1UL << HRTIM_CR2_MSWU_Pos)            /*!< 0x00000001 */
+#define HRTIM_CR2_MSWU                HRTIM_CR2_MSWU_Msk                       /*!< Master software update */
+#define HRTIM_CR2_TASWU_Pos           (1U)
+#define HRTIM_CR2_TASWU_Msk           (0x1UL << HRTIM_CR2_TASWU_Pos)           /*!< 0x00000002 */
+#define HRTIM_CR2_TASWU               HRTIM_CR2_TASWU_Msk                      /*!< Timer A software update */
+#define HRTIM_CR2_TBSWU_Pos           (2U)
+#define HRTIM_CR2_TBSWU_Msk           (0x1UL << HRTIM_CR2_TBSWU_Pos)           /*!< 0x00000004 */
+#define HRTIM_CR2_TBSWU               HRTIM_CR2_TBSWU_Msk                      /*!< Timer B software update */
+#define HRTIM_CR2_TCSWU_Pos           (3U)
+#define HRTIM_CR2_TCSWU_Msk           (0x1UL << HRTIM_CR2_TCSWU_Pos)           /*!< 0x00000008 */
+#define HRTIM_CR2_TCSWU               HRTIM_CR2_TCSWU_Msk                      /*!< Timer C software update */
+#define HRTIM_CR2_TDSWU_Pos           (4U)
+#define HRTIM_CR2_TDSWU_Msk           (0x1UL << HRTIM_CR2_TDSWU_Pos)           /*!< 0x00000010 */
+#define HRTIM_CR2_TDSWU               HRTIM_CR2_TDSWU_Msk                      /*!< Timer D software update */
+#define HRTIM_CR2_TESWU_Pos           (5U)
+#define HRTIM_CR2_TESWU_Msk           (0x1UL << HRTIM_CR2_TESWU_Pos)           /*!< 0x00000020 */
+#define HRTIM_CR2_TESWU               HRTIM_CR2_TESWU_Msk                      /*!< Timer E software update */
+#define HRTIM_CR2_MRST_Pos            (8U)
+#define HRTIM_CR2_MRST_Msk            (0x1UL << HRTIM_CR2_MRST_Pos)            /*!< 0x00000100 */
+#define HRTIM_CR2_MRST                HRTIM_CR2_MRST_Msk                       /*!< Master count software reset */
+#define HRTIM_CR2_TARST_Pos           (9U)
+#define HRTIM_CR2_TARST_Msk           (0x1UL << HRTIM_CR2_TARST_Pos)           /*!< 0x00000200 */
+#define HRTIM_CR2_TARST               HRTIM_CR2_TARST_Msk                      /*!< Timer A count software reset */
+#define HRTIM_CR2_TBRST_Pos           (10U)
+#define HRTIM_CR2_TBRST_Msk           (0x1UL << HRTIM_CR2_TBRST_Pos)           /*!< 0x00000400 */
+#define HRTIM_CR2_TBRST               HRTIM_CR2_TBRST_Msk                      /*!< Timer B count software reset */
+#define HRTIM_CR2_TCRST_Pos           (11U)
+#define HRTIM_CR2_TCRST_Msk           (0x1UL << HRTIM_CR2_TCRST_Pos)           /*!< 0x00000800 */
+#define HRTIM_CR2_TCRST               HRTIM_CR2_TCRST_Msk                      /*!< Timer C count software reset */
+#define HRTIM_CR2_TDRST_Pos           (12U)
+#define HRTIM_CR2_TDRST_Msk           (0x1UL << HRTIM_CR2_TDRST_Pos)           /*!< 0x00001000 */
+#define HRTIM_CR2_TDRST               HRTIM_CR2_TDRST_Msk                      /*!< Timer D count software reset */
+#define HRTIM_CR2_TERST_Pos           (13U)
+#define HRTIM_CR2_TERST_Msk           (0x1UL << HRTIM_CR2_TERST_Pos)           /*!< 0x00002000 */
+#define HRTIM_CR2_TERST               HRTIM_CR2_TERST_Msk                      /*!< Timer E count software reset */
+
+/**** Bit definition for Common HRTIM Timer interrupt status register *********/
+#define HRTIM_ISR_FLT1_Pos            (0U)
+#define HRTIM_ISR_FLT1_Msk            (0x1UL << HRTIM_ISR_FLT1_Pos)            /*!< 0x00000001 */
+#define HRTIM_ISR_FLT1                HRTIM_ISR_FLT1_Msk                       /*!< Fault 1 interrupt flag */
+#define HRTIM_ISR_FLT2_Pos            (1U)
+#define HRTIM_ISR_FLT2_Msk            (0x1UL << HRTIM_ISR_FLT2_Pos)            /*!< 0x00000002 */
+#define HRTIM_ISR_FLT2                HRTIM_ISR_FLT2_Msk                       /*!< Fault 2 interrupt flag */
+#define HRTIM_ISR_FLT3_Pos            (2U)
+#define HRTIM_ISR_FLT3_Msk            (0x1UL << HRTIM_ISR_FLT3_Pos)            /*!< 0x00000004 */
+#define HRTIM_ISR_FLT3                HRTIM_ISR_FLT3_Msk                       /*!< Fault 3 interrupt flag */
+#define HRTIM_ISR_FLT4_Pos            (3U)
+#define HRTIM_ISR_FLT4_Msk            (0x1UL << HRTIM_ISR_FLT4_Pos)            /*!< 0x00000008 */
+#define HRTIM_ISR_FLT4                HRTIM_ISR_FLT4_Msk                       /*!< Fault 4 interrupt flag */
+#define HRTIM_ISR_FLT5_Pos            (4U)
+#define HRTIM_ISR_FLT5_Msk            (0x1UL << HRTIM_ISR_FLT5_Pos)            /*!< 0x00000010 */
+#define HRTIM_ISR_FLT5                HRTIM_ISR_FLT5_Msk                       /*!< Fault 5 interrupt flag */
+#define HRTIM_ISR_SYSFLT_Pos          (5U)
+#define HRTIM_ISR_SYSFLT_Msk          (0x1UL << HRTIM_ISR_SYSFLT_Pos)          /*!< 0x00000020 */
+#define HRTIM_ISR_SYSFLT              HRTIM_ISR_SYSFLT_Msk                     /*!< System Fault interrupt flag */
+#define HRTIM_ISR_BMPER_Pos           (17U)
+#define HRTIM_ISR_BMPER_Msk           (0x1UL << HRTIM_ISR_BMPER_Pos)           /*!< 0x00020000 */
+#define HRTIM_ISR_BMPER               HRTIM_ISR_BMPER_Msk                      /*!<  Burst mode period interrupt flag */
+
+/**** Bit definition for Common HRTIM Timer interrupt clear register **********/
+#define HRTIM_ICR_FLT1C_Pos           (0U)
+#define HRTIM_ICR_FLT1C_Msk           (0x1UL << HRTIM_ICR_FLT1C_Pos)           /*!< 0x00000001 */
+#define HRTIM_ICR_FLT1C               HRTIM_ICR_FLT1C_Msk                      /*!< Fault 1 interrupt flag clear */
+#define HRTIM_ICR_FLT2C_Pos           (1U)
+#define HRTIM_ICR_FLT2C_Msk           (0x1UL << HRTIM_ICR_FLT2C_Pos)           /*!< 0x00000002 */
+#define HRTIM_ICR_FLT2C               HRTIM_ICR_FLT2C_Msk                      /*!< Fault 2 interrupt flag clear */
+#define HRTIM_ICR_FLT3C_Pos           (2U)
+#define HRTIM_ICR_FLT3C_Msk           (0x1UL << HRTIM_ICR_FLT3C_Pos)           /*!< 0x00000004 */
+#define HRTIM_ICR_FLT3C               HRTIM_ICR_FLT3C_Msk                      /*!< Fault 3 interrupt flag clear */
+#define HRTIM_ICR_FLT4C_Pos           (3U)
+#define HRTIM_ICR_FLT4C_Msk           (0x1UL << HRTIM_ICR_FLT4C_Pos)           /*!< 0x00000008 */
+#define HRTIM_ICR_FLT4C               HRTIM_ICR_FLT4C_Msk                      /*!< Fault 4 interrupt flag clear */
+#define HRTIM_ICR_FLT5C_Pos           (4U)
+#define HRTIM_ICR_FLT5C_Msk           (0x1UL << HRTIM_ICR_FLT5C_Pos)           /*!< 0x00000010 */
+#define HRTIM_ICR_FLT5C               HRTIM_ICR_FLT5C_Msk                      /*!< Fault 5 interrupt flag clear */
+#define HRTIM_ICR_SYSFLTC_Pos         (5U)
+#define HRTIM_ICR_SYSFLTC_Msk         (0x1UL << HRTIM_ICR_SYSFLTC_Pos)         /*!< 0x00000020 */
+#define HRTIM_ICR_SYSFLTC             HRTIM_ICR_SYSFLTC_Msk                    /*!< System Fault interrupt flag clear */
+#define HRTIM_ICR_BMPERC_Pos          (17U)
+#define HRTIM_ICR_BMPERC_Msk          (0x1UL << HRTIM_ICR_BMPERC_Pos)          /*!< 0x00020000 */
+#define HRTIM_ICR_BMPERC              HRTIM_ICR_BMPERC_Msk                     /*!<  Burst mode period interrupt flag clear */
+
+/**** Bit definition for Common HRTIM Timer interrupt enable register *********/
+#define HRTIM_IER_FLT1_Pos            (0U)
+#define HRTIM_IER_FLT1_Msk            (0x1UL << HRTIM_IER_FLT1_Pos)            /*!< 0x00000001 */
+#define HRTIM_IER_FLT1                HRTIM_IER_FLT1_Msk                       /*!< Fault 1 interrupt enable */
+#define HRTIM_IER_FLT2_Pos            (1U)
+#define HRTIM_IER_FLT2_Msk            (0x1UL << HRTIM_IER_FLT2_Pos)            /*!< 0x00000002 */
+#define HRTIM_IER_FLT2                HRTIM_IER_FLT2_Msk                       /*!< Fault 2 interrupt enable */
+#define HRTIM_IER_FLT3_Pos            (2U)
+#define HRTIM_IER_FLT3_Msk            (0x1UL << HRTIM_IER_FLT3_Pos)            /*!< 0x00000004 */
+#define HRTIM_IER_FLT3                HRTIM_IER_FLT3_Msk                       /*!< Fault 3 interrupt enable */
+#define HRTIM_IER_FLT4_Pos            (3U)
+#define HRTIM_IER_FLT4_Msk            (0x1UL << HRTIM_IER_FLT4_Pos)            /*!< 0x00000008 */
+#define HRTIM_IER_FLT4                HRTIM_IER_FLT4_Msk                       /*!< Fault 4 interrupt enable */
+#define HRTIM_IER_FLT5_Pos            (4U)
+#define HRTIM_IER_FLT5_Msk            (0x1UL << HRTIM_IER_FLT5_Pos)            /*!< 0x00000010 */
+#define HRTIM_IER_FLT5                HRTIM_IER_FLT5_Msk                       /*!< Fault 5 interrupt enable */
+#define HRTIM_IER_SYSFLT_Pos          (5U)
+#define HRTIM_IER_SYSFLT_Msk          (0x1UL << HRTIM_IER_SYSFLT_Pos)          /*!< 0x00000020 */
+#define HRTIM_IER_SYSFLT              HRTIM_IER_SYSFLT_Msk                     /*!< System Fault interrupt enable */
+#define HRTIM_IER_BMPER_Pos           (17U)
+#define HRTIM_IER_BMPER_Msk           (0x1UL << HRTIM_IER_BMPER_Pos)           /*!< 0x00020000 */
+#define HRTIM_IER_BMPER               HRTIM_IER_BMPER_Msk                      /*!<  Burst mode period interrupt enable */
+
+/**** Bit definition for Common HRTIM Timer output enable register ************/
+#define HRTIM_OENR_TA1OEN_Pos         (0U)
+#define HRTIM_OENR_TA1OEN_Msk         (0x1UL << HRTIM_OENR_TA1OEN_Pos)         /*!< 0x00000001 */
+#define HRTIM_OENR_TA1OEN             HRTIM_OENR_TA1OEN_Msk                    /*!< Timer A Output 1 enable */
+#define HRTIM_OENR_TA2OEN_Pos         (1U)
+#define HRTIM_OENR_TA2OEN_Msk         (0x1UL << HRTIM_OENR_TA2OEN_Pos)         /*!< 0x00000002 */
+#define HRTIM_OENR_TA2OEN             HRTIM_OENR_TA2OEN_Msk                    /*!< Timer A Output 2 enable */
+#define HRTIM_OENR_TB1OEN_Pos         (2U)
+#define HRTIM_OENR_TB1OEN_Msk         (0x1UL << HRTIM_OENR_TB1OEN_Pos)         /*!< 0x00000004 */
+#define HRTIM_OENR_TB1OEN             HRTIM_OENR_TB1OEN_Msk                    /*!< Timer B Output 1 enable */
+#define HRTIM_OENR_TB2OEN_Pos         (3U)
+#define HRTIM_OENR_TB2OEN_Msk         (0x1UL << HRTIM_OENR_TB2OEN_Pos)         /*!< 0x00000008 */
+#define HRTIM_OENR_TB2OEN             HRTIM_OENR_TB2OEN_Msk                    /*!< Timer B Output 2 enable */
+#define HRTIM_OENR_TC1OEN_Pos         (4U)
+#define HRTIM_OENR_TC1OEN_Msk         (0x1UL << HRTIM_OENR_TC1OEN_Pos)         /*!< 0x00000010 */
+#define HRTIM_OENR_TC1OEN             HRTIM_OENR_TC1OEN_Msk                    /*!< Timer C Output 1 enable */
+#define HRTIM_OENR_TC2OEN_Pos         (5U)
+#define HRTIM_OENR_TC2OEN_Msk         (0x1UL << HRTIM_OENR_TC2OEN_Pos)         /*!< 0x00000020 */
+#define HRTIM_OENR_TC2OEN             HRTIM_OENR_TC2OEN_Msk                    /*!< Timer C Output 2 enable */
+#define HRTIM_OENR_TD1OEN_Pos         (6U)
+#define HRTIM_OENR_TD1OEN_Msk         (0x1UL << HRTIM_OENR_TD1OEN_Pos)         /*!< 0x00000040 */
+#define HRTIM_OENR_TD1OEN             HRTIM_OENR_TD1OEN_Msk                    /*!< Timer D Output 1 enable */
+#define HRTIM_OENR_TD2OEN_Pos         (7U)
+#define HRTIM_OENR_TD2OEN_Msk         (0x1UL << HRTIM_OENR_TD2OEN_Pos)         /*!< 0x00000080 */
+#define HRTIM_OENR_TD2OEN             HRTIM_OENR_TD2OEN_Msk                    /*!< Timer D Output 2 enable */
+#define HRTIM_OENR_TE1OEN_Pos         (8U)
+#define HRTIM_OENR_TE1OEN_Msk         (0x1UL << HRTIM_OENR_TE1OEN_Pos)         /*!< 0x00000100 */
+#define HRTIM_OENR_TE1OEN             HRTIM_OENR_TE1OEN_Msk                    /*!< Timer E Output 1 enable */
+#define HRTIM_OENR_TE2OEN_Pos         (9U)
+#define HRTIM_OENR_TE2OEN_Msk         (0x1UL << HRTIM_OENR_TE2OEN_Pos)         /*!< 0x00000200 */
+#define HRTIM_OENR_TE2OEN             HRTIM_OENR_TE2OEN_Msk                    /*!< Timer E Output 2 enable */
+
+/**** Bit definition for Common HRTIM Timer output disable register ***********/
+#define HRTIM_ODISR_TA1ODIS_Pos       (0U)
+#define HRTIM_ODISR_TA1ODIS_Msk       (0x1UL << HRTIM_ODISR_TA1ODIS_Pos)       /*!< 0x00000001 */
+#define HRTIM_ODISR_TA1ODIS           HRTIM_ODISR_TA1ODIS_Msk                  /*!< Timer A Output 1 disable */
+#define HRTIM_ODISR_TA2ODIS_Pos       (1U)
+#define HRTIM_ODISR_TA2ODIS_Msk       (0x1UL << HRTIM_ODISR_TA2ODIS_Pos)       /*!< 0x00000002 */
+#define HRTIM_ODISR_TA2ODIS           HRTIM_ODISR_TA2ODIS_Msk                  /*!< Timer A Output 2 disable */
+#define HRTIM_ODISR_TB1ODIS_Pos       (2U)
+#define HRTIM_ODISR_TB1ODIS_Msk       (0x1UL << HRTIM_ODISR_TB1ODIS_Pos)       /*!< 0x00000004 */
+#define HRTIM_ODISR_TB1ODIS           HRTIM_ODISR_TB1ODIS_Msk                  /*!< Timer B Output 1 disable */
+#define HRTIM_ODISR_TB2ODIS_Pos       (3U)
+#define HRTIM_ODISR_TB2ODIS_Msk       (0x1UL << HRTIM_ODISR_TB2ODIS_Pos)       /*!< 0x00000008 */
+#define HRTIM_ODISR_TB2ODIS           HRTIM_ODISR_TB2ODIS_Msk                  /*!< Timer B Output 2 disable */
+#define HRTIM_ODISR_TC1ODIS_Pos       (4U)
+#define HRTIM_ODISR_TC1ODIS_Msk       (0x1UL << HRTIM_ODISR_TC1ODIS_Pos)       /*!< 0x00000010 */
+#define HRTIM_ODISR_TC1ODIS           HRTIM_ODISR_TC1ODIS_Msk                  /*!< Timer C Output 1 disable */
+#define HRTIM_ODISR_TC2ODIS_Pos       (5U)
+#define HRTIM_ODISR_TC2ODIS_Msk       (0x1UL << HRTIM_ODISR_TC2ODIS_Pos)       /*!< 0x00000020 */
+#define HRTIM_ODISR_TC2ODIS           HRTIM_ODISR_TC2ODIS_Msk                  /*!< Timer C Output 2 disable */
+#define HRTIM_ODISR_TD1ODIS_Pos       (6U)
+#define HRTIM_ODISR_TD1ODIS_Msk       (0x1UL << HRTIM_ODISR_TD1ODIS_Pos)       /*!< 0x00000040 */
+#define HRTIM_ODISR_TD1ODIS           HRTIM_ODISR_TD1ODIS_Msk                  /*!< Timer D Output 1 disable */
+#define HRTIM_ODISR_TD2ODIS_Pos       (7U)
+#define HRTIM_ODISR_TD2ODIS_Msk       (0x1UL << HRTIM_ODISR_TD2ODIS_Pos)       /*!< 0x00000080 */
+#define HRTIM_ODISR_TD2ODIS           HRTIM_ODISR_TD2ODIS_Msk                  /*!< Timer D Output 2 disable */
+#define HRTIM_ODISR_TE1ODIS_Pos       (8U)
+#define HRTIM_ODISR_TE1ODIS_Msk       (0x1UL << HRTIM_ODISR_TE1ODIS_Pos)       /*!< 0x00000100 */
+#define HRTIM_ODISR_TE1ODIS           HRTIM_ODISR_TE1ODIS_Msk                  /*!< Timer E Output 1 disable */
+#define HRTIM_ODISR_TE2ODIS_Pos       (9U)
+#define HRTIM_ODISR_TE2ODIS_Msk       (0x1UL << HRTIM_ODISR_TE2ODIS_Pos)       /*!< 0x00000200 */
+#define HRTIM_ODISR_TE2ODIS           HRTIM_ODISR_TE2ODIS_Msk                  /*!< Timer E Output 2 disable */
+
+/**** Bit definition for Common HRTIM Timer output disable status register *****/
+#define HRTIM_ODSR_TA1ODS_Pos         (0U)
+#define HRTIM_ODSR_TA1ODS_Msk         (0x1UL << HRTIM_ODSR_TA1ODS_Pos)         /*!< 0x00000001 */
+#define HRTIM_ODSR_TA1ODS             HRTIM_ODSR_TA1ODS_Msk                    /*!< Timer A Output 1 disable status */
+#define HRTIM_ODSR_TA2ODS_Pos         (1U)
+#define HRTIM_ODSR_TA2ODS_Msk         (0x1UL << HRTIM_ODSR_TA2ODS_Pos)         /*!< 0x00000002 */
+#define HRTIM_ODSR_TA2ODS             HRTIM_ODSR_TA2ODS_Msk                    /*!< Timer A Output 2 disable status */
+#define HRTIM_ODSR_TB1ODS_Pos         (2U)
+#define HRTIM_ODSR_TB1ODS_Msk         (0x1UL << HRTIM_ODSR_TB1ODS_Pos)         /*!< 0x00000004 */
+#define HRTIM_ODSR_TB1ODS             HRTIM_ODSR_TB1ODS_Msk                    /*!< Timer B Output 1 disable status */
+#define HRTIM_ODSR_TB2ODS_Pos         (3U)
+#define HRTIM_ODSR_TB2ODS_Msk         (0x1UL << HRTIM_ODSR_TB2ODS_Pos)         /*!< 0x00000008 */
+#define HRTIM_ODSR_TB2ODS             HRTIM_ODSR_TB2ODS_Msk                    /*!< Timer B Output 2 disable status */
+#define HRTIM_ODSR_TC1ODS_Pos         (4U)
+#define HRTIM_ODSR_TC1ODS_Msk         (0x1UL << HRTIM_ODSR_TC1ODS_Pos)         /*!< 0x00000010 */
+#define HRTIM_ODSR_TC1ODS             HRTIM_ODSR_TC1ODS_Msk                    /*!< Timer C Output 1 disable status */
+#define HRTIM_ODSR_TC2ODS_Pos         (5U)
+#define HRTIM_ODSR_TC2ODS_Msk         (0x1UL << HRTIM_ODSR_TC2ODS_Pos)         /*!< 0x00000020 */
+#define HRTIM_ODSR_TC2ODS             HRTIM_ODSR_TC2ODS_Msk                    /*!< Timer C Output 2 disable status */
+#define HRTIM_ODSR_TD1ODS_Pos         (6U)
+#define HRTIM_ODSR_TD1ODS_Msk         (0x1UL << HRTIM_ODSR_TD1ODS_Pos)         /*!< 0x00000040 */
+#define HRTIM_ODSR_TD1ODS             HRTIM_ODSR_TD1ODS_Msk                    /*!< Timer D Output 1 disable status */
+#define HRTIM_ODSR_TD2ODS_Pos         (7U)
+#define HRTIM_ODSR_TD2ODS_Msk         (0x1UL << HRTIM_ODSR_TD2ODS_Pos)         /*!< 0x00000080 */
+#define HRTIM_ODSR_TD2ODS             HRTIM_ODSR_TD2ODS_Msk                    /*!< Timer D Output 2 disable status */
+#define HRTIM_ODSR_TE1ODS_Pos         (8U)
+#define HRTIM_ODSR_TE1ODS_Msk         (0x1UL << HRTIM_ODSR_TE1ODS_Pos)         /*!< 0x00000100 */
+#define HRTIM_ODSR_TE1ODS             HRTIM_ODSR_TE1ODS_Msk                    /*!< Timer E Output 1 disable status */
+#define HRTIM_ODSR_TE2ODS_Pos         (9U)
+#define HRTIM_ODSR_TE2ODS_Msk         (0x1UL << HRTIM_ODSR_TE2ODS_Pos)         /*!< 0x00000200 */
+#define HRTIM_ODSR_TE2ODS             HRTIM_ODSR_TE2ODS_Msk                    /*!< Timer E Output 2 disable status */
+
+/**** Bit definition for Common HRTIM Timer Burst mode control register ********/
+#define HRTIM_BMCR_BME_Pos            (0U)
+#define HRTIM_BMCR_BME_Msk            (0x1UL << HRTIM_BMCR_BME_Pos)            /*!< 0x00000001 */
+#define HRTIM_BMCR_BME                HRTIM_BMCR_BME_Msk                       /*!< Burst mode enbale */
+#define HRTIM_BMCR_BMOM_Pos           (1U)
+#define HRTIM_BMCR_BMOM_Msk           (0x1UL << HRTIM_BMCR_BMOM_Pos)           /*!< 0x00000002 */
+#define HRTIM_BMCR_BMOM               HRTIM_BMCR_BMOM_Msk                      /*!< Burst mode operating mode */
+#define HRTIM_BMCR_BMCLK_Pos          (2U)
+#define HRTIM_BMCR_BMCLK_Msk          (0xFUL << HRTIM_BMCR_BMCLK_Pos)          /*!< 0x0000003C */
+#define HRTIM_BMCR_BMCLK              HRTIM_BMCR_BMCLK_Msk                     /*!< Burst mode clock source */
+#define HRTIM_BMCR_BMCLK_0            (0x1UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000004 */
+#define HRTIM_BMCR_BMCLK_1            (0x2UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000008 */
+#define HRTIM_BMCR_BMCLK_2            (0x4UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000010 */
+#define HRTIM_BMCR_BMCLK_3            (0x8UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000020 */
+#define HRTIM_BMCR_BMPRSC_Pos         (6U)
+#define HRTIM_BMCR_BMPRSC_Msk         (0xFUL << HRTIM_BMCR_BMPRSC_Pos)         /*!< 0x000003C0 */
+#define HRTIM_BMCR_BMPRSC             HRTIM_BMCR_BMPRSC_Msk                    /*!< Burst mode prescaler */
+#define HRTIM_BMCR_BMPRSC_0           (0x1UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000040 */
+#define HRTIM_BMCR_BMPRSC_1           (0x2UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000080 */
+#define HRTIM_BMCR_BMPRSC_2           (0x4UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000100 */
+#define HRTIM_BMCR_BMPRSC_3           (0x8UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000200 */
+#define HRTIM_BMCR_BMPREN_Pos         (10U)
+#define HRTIM_BMCR_BMPREN_Msk         (0x1UL << HRTIM_BMCR_BMPREN_Pos)         /*!< 0x00000400 */
+#define HRTIM_BMCR_BMPREN             HRTIM_BMCR_BMPREN_Msk                    /*!< Burst mode Preload bit */
+#define HRTIM_BMCR_MTBM_Pos           (16U)
+#define HRTIM_BMCR_MTBM_Msk           (0x1UL << HRTIM_BMCR_MTBM_Pos)           /*!< 0x00010000 */
+#define HRTIM_BMCR_MTBM               HRTIM_BMCR_MTBM_Msk                      /*!< Master Timer Burst mode */
+#define HRTIM_BMCR_TABM_Pos           (17U)
+#define HRTIM_BMCR_TABM_Msk           (0x1UL << HRTIM_BMCR_TABM_Pos)           /*!< 0x00020000 */
+#define HRTIM_BMCR_TABM               HRTIM_BMCR_TABM_Msk                      /*!< Timer A Burst mode */
+#define HRTIM_BMCR_TBBM_Pos           (18U)
+#define HRTIM_BMCR_TBBM_Msk           (0x1UL << HRTIM_BMCR_TBBM_Pos)           /*!< 0x00040000 */
+#define HRTIM_BMCR_TBBM               HRTIM_BMCR_TBBM_Msk                      /*!< Timer B Burst mode */
+#define HRTIM_BMCR_TCBM_Pos           (19U)
+#define HRTIM_BMCR_TCBM_Msk           (0x1UL << HRTIM_BMCR_TCBM_Pos)           /*!< 0x00080000 */
+#define HRTIM_BMCR_TCBM               HRTIM_BMCR_TCBM_Msk                      /*!< Timer C Burst mode */
+#define HRTIM_BMCR_TDBM_Pos           (20U)
+#define HRTIM_BMCR_TDBM_Msk           (0x1UL << HRTIM_BMCR_TDBM_Pos)           /*!< 0x00100000 */
+#define HRTIM_BMCR_TDBM               HRTIM_BMCR_TDBM_Msk                      /*!< Timer D Burst mode */
+#define HRTIM_BMCR_TEBM_Pos           (21U)
+#define HRTIM_BMCR_TEBM_Msk           (0x1UL << HRTIM_BMCR_TEBM_Pos)           /*!< 0x00200000 */
+#define HRTIM_BMCR_TEBM               HRTIM_BMCR_TEBM_Msk                      /*!< Timer E Burst mode */
+#define HRTIM_BMCR_BMSTAT_Pos         (31U)
+#define HRTIM_BMCR_BMSTAT_Msk         (0x1UL << HRTIM_BMCR_BMSTAT_Pos)         /*!< 0x80000000 */
+#define HRTIM_BMCR_BMSTAT             HRTIM_BMCR_BMSTAT_Msk                    /*!< Burst mode status */
+
+/**** Bit definition for Common HRTIM Timer Burst mode Trigger register *******/
+#define HRTIM_BMTRGR_SW_Pos           (0U)
+#define HRTIM_BMTRGR_SW_Msk           (0x1UL << HRTIM_BMTRGR_SW_Pos)           /*!< 0x00000001 */
+#define HRTIM_BMTRGR_SW               HRTIM_BMTRGR_SW_Msk                      /*!< Software start */
+#define HRTIM_BMTRGR_MSTRST_Pos       (1U)
+#define HRTIM_BMTRGR_MSTRST_Msk       (0x1UL << HRTIM_BMTRGR_MSTRST_Pos)       /*!< 0x00000002 */
+#define HRTIM_BMTRGR_MSTRST           HRTIM_BMTRGR_MSTRST_Msk                  /*!<  Master reset */
+#define HRTIM_BMTRGR_MSTREP_Pos       (2U)
+#define HRTIM_BMTRGR_MSTREP_Msk       (0x1UL << HRTIM_BMTRGR_MSTREP_Pos)       /*!< 0x00000004 */
+#define HRTIM_BMTRGR_MSTREP           HRTIM_BMTRGR_MSTREP_Msk                  /*!<  Master repetition */
+#define HRTIM_BMTRGR_MSTCMP1_Pos      (3U)
+#define HRTIM_BMTRGR_MSTCMP1_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP1_Pos)      /*!< 0x00000008 */
+#define HRTIM_BMTRGR_MSTCMP1          HRTIM_BMTRGR_MSTCMP1_Msk                 /*!<  Master compare 1 */
+#define HRTIM_BMTRGR_MSTCMP2_Pos      (4U)
+#define HRTIM_BMTRGR_MSTCMP2_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP2_Pos)      /*!< 0x00000010 */
+#define HRTIM_BMTRGR_MSTCMP2          HRTIM_BMTRGR_MSTCMP2_Msk                 /*!< Master compare 2  */
+#define HRTIM_BMTRGR_MSTCMP3_Pos      (5U)
+#define HRTIM_BMTRGR_MSTCMP3_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP3_Pos)      /*!< 0x00000020 */
+#define HRTIM_BMTRGR_MSTCMP3          HRTIM_BMTRGR_MSTCMP3_Msk                 /*!< Master compare 3 */
+#define HRTIM_BMTRGR_MSTCMP4_Pos      (6U)
+#define HRTIM_BMTRGR_MSTCMP4_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP4_Pos)      /*!< 0x00000040 */
+#define HRTIM_BMTRGR_MSTCMP4          HRTIM_BMTRGR_MSTCMP4_Msk                 /*!< Master compare 4 */
+#define HRTIM_BMTRGR_TARST_Pos        (7U)
+#define HRTIM_BMTRGR_TARST_Msk        (0x1UL << HRTIM_BMTRGR_TARST_Pos)        /*!< 0x00000080 */
+#define HRTIM_BMTRGR_TARST            HRTIM_BMTRGR_TARST_Msk                   /*!< Timer A reset  */
+#define HRTIM_BMTRGR_TAREP_Pos        (8U)
+#define HRTIM_BMTRGR_TAREP_Msk        (0x1UL << HRTIM_BMTRGR_TAREP_Pos)        /*!< 0x00000100 */
+#define HRTIM_BMTRGR_TAREP            HRTIM_BMTRGR_TAREP_Msk                   /*!< Timer A repetition  */
+#define HRTIM_BMTRGR_TACMP1_Pos       (9U)
+#define HRTIM_BMTRGR_TACMP1_Msk       (0x1UL << HRTIM_BMTRGR_TACMP1_Pos)       /*!< 0x00000200 */
+#define HRTIM_BMTRGR_TACMP1           HRTIM_BMTRGR_TACMP1_Msk                  /*!< Timer A compare 1  */
+#define HRTIM_BMTRGR_TACMP2_Pos       (10U)
+#define HRTIM_BMTRGR_TACMP2_Msk       (0x1UL << HRTIM_BMTRGR_TACMP2_Pos)       /*!< 0x00000400 */
+#define HRTIM_BMTRGR_TACMP2           HRTIM_BMTRGR_TACMP2_Msk                  /*!< Timer A compare 2  */
+#define HRTIM_BMTRGR_TBRST_Pos        (11U)
+#define HRTIM_BMTRGR_TBRST_Msk        (0x1UL << HRTIM_BMTRGR_TBRST_Pos)        /*!< 0x00000800 */
+#define HRTIM_BMTRGR_TBRST            HRTIM_BMTRGR_TBRST_Msk                   /*!< Timer B reset  */
+#define HRTIM_BMTRGR_TBREP_Pos        (12U)
+#define HRTIM_BMTRGR_TBREP_Msk        (0x1UL << HRTIM_BMTRGR_TBREP_Pos)        /*!< 0x00001000 */
+#define HRTIM_BMTRGR_TBREP            HRTIM_BMTRGR_TBREP_Msk                   /*!< Timer B repetition  */
+#define HRTIM_BMTRGR_TBCMP1_Pos       (13U)
+#define HRTIM_BMTRGR_TBCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TBCMP1_Pos)       /*!< 0x00002000 */
+#define HRTIM_BMTRGR_TBCMP1           HRTIM_BMTRGR_TBCMP1_Msk                  /*!< Timer B compare 1 */
+#define HRTIM_BMTRGR_TBCMP2_Pos       (14U)
+#define HRTIM_BMTRGR_TBCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TBCMP2_Pos)       /*!< 0x00004000 */
+#define HRTIM_BMTRGR_TBCMP2           HRTIM_BMTRGR_TBCMP2_Msk                  /*!< Timer B compare 2 */
+#define HRTIM_BMTRGR_TCRST_Pos        (15U)
+#define HRTIM_BMTRGR_TCRST_Msk        (0x1UL << HRTIM_BMTRGR_TCRST_Pos)        /*!< 0x00008000 */
+#define HRTIM_BMTRGR_TCRST            HRTIM_BMTRGR_TCRST_Msk                   /*!< Timer C reset  */
+#define HRTIM_BMTRGR_TCREP_Pos        (16U)
+#define HRTIM_BMTRGR_TCREP_Msk        (0x1UL << HRTIM_BMTRGR_TCREP_Pos)        /*!< 0x00010000 */
+#define HRTIM_BMTRGR_TCREP            HRTIM_BMTRGR_TCREP_Msk                   /*!< Timer C repetition */
+#define HRTIM_BMTRGR_TCCMP1_Pos       (17U)
+#define HRTIM_BMTRGR_TCCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TCCMP1_Pos)       /*!< 0x00020000 */
+#define HRTIM_BMTRGR_TCCMP1           HRTIM_BMTRGR_TCCMP1_Msk                  /*!< Timer C compare 1 */
+#define HRTIM_BMTRGR_TCCMP2_Pos       (18U)
+#define HRTIM_BMTRGR_TCCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TCCMP2_Pos)       /*!< 0x00040000 */
+#define HRTIM_BMTRGR_TCCMP2           HRTIM_BMTRGR_TCCMP2_Msk                  /*!< Timer C compare 2 */
+#define HRTIM_BMTRGR_TDRST_Pos        (19U)
+#define HRTIM_BMTRGR_TDRST_Msk        (0x1UL << HRTIM_BMTRGR_TDRST_Pos)        /*!< 0x00080000 */
+#define HRTIM_BMTRGR_TDRST            HRTIM_BMTRGR_TDRST_Msk                   /*!< Timer D reset  */
+#define HRTIM_BMTRGR_TDREP_Pos        (20U)
+#define HRTIM_BMTRGR_TDREP_Msk        (0x1UL << HRTIM_BMTRGR_TDREP_Pos)        /*!< 0x00100000 */
+#define HRTIM_BMTRGR_TDREP            HRTIM_BMTRGR_TDREP_Msk                   /*!< Timer D repetition  */
+#define HRTIM_BMTRGR_TDCMP1_Pos       (21U)
+#define HRTIM_BMTRGR_TDCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TDCMP1_Pos)       /*!< 0x00200000 */
+#define HRTIM_BMTRGR_TDCMP1           HRTIM_BMTRGR_TDCMP1_Msk                  /*!< Timer D compare 1 */
+#define HRTIM_BMTRGR_TDCMP2_Pos       (22U)
+#define HRTIM_BMTRGR_TDCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TDCMP2_Pos)       /*!< 0x00400000 */
+#define HRTIM_BMTRGR_TDCMP2           HRTIM_BMTRGR_TDCMP2_Msk                  /*!< Timer D compare 2 */
+#define HRTIM_BMTRGR_TERST_Pos        (23U)
+#define HRTIM_BMTRGR_TERST_Msk        (0x1UL << HRTIM_BMTRGR_TERST_Pos)        /*!< 0x00800000 */
+#define HRTIM_BMTRGR_TERST            HRTIM_BMTRGR_TERST_Msk                   /*!< Timer E reset  */
+#define HRTIM_BMTRGR_TEREP_Pos        (24U)
+#define HRTIM_BMTRGR_TEREP_Msk        (0x1UL << HRTIM_BMTRGR_TEREP_Pos)        /*!< 0x01000000 */
+#define HRTIM_BMTRGR_TEREP            HRTIM_BMTRGR_TEREP_Msk                   /*!< Timer E repetition  */
+#define HRTIM_BMTRGR_TECMP1_Pos       (25U)
+#define HRTIM_BMTRGR_TECMP1_Msk       (0x1UL << HRTIM_BMTRGR_TECMP1_Pos)       /*!< 0x02000000 */
+#define HRTIM_BMTRGR_TECMP1           HRTIM_BMTRGR_TECMP1_Msk                  /*!< Timer E compare 1 */
+#define HRTIM_BMTRGR_TECMP2_Pos       (26U)
+#define HRTIM_BMTRGR_TECMP2_Msk       (0x1UL << HRTIM_BMTRGR_TECMP2_Pos)       /*!< 0x04000000 */
+#define HRTIM_BMTRGR_TECMP2           HRTIM_BMTRGR_TECMP2_Msk                  /*!< Timer E compare 2 */
+#define HRTIM_BMTRGR_TAEEV7_Pos       (27U)
+#define HRTIM_BMTRGR_TAEEV7_Msk       (0x1UL << HRTIM_BMTRGR_TAEEV7_Pos)       /*!< 0x08000000 */
+#define HRTIM_BMTRGR_TAEEV7           HRTIM_BMTRGR_TAEEV7_Msk                  /*!< Timer A period following External Event7  */
+#define HRTIM_BMTRGR_TDEEV8_Pos       (28U)
+#define HRTIM_BMTRGR_TDEEV8_Msk       (0x1UL << HRTIM_BMTRGR_TDEEV8_Pos)       /*!< 0x10000000 */
+#define HRTIM_BMTRGR_TDEEV8           HRTIM_BMTRGR_TDEEV8_Msk                  /*!< Timer D period following External Event8  */
+#define HRTIM_BMTRGR_EEV7_Pos         (29U)
+#define HRTIM_BMTRGR_EEV7_Msk         (0x1UL << HRTIM_BMTRGR_EEV7_Pos)         /*!< 0x20000000 */
+#define HRTIM_BMTRGR_EEV7             HRTIM_BMTRGR_EEV7_Msk                    /*!< External Event 7 */
+#define HRTIM_BMTRGR_EEV8_Pos         (30U)
+#define HRTIM_BMTRGR_EEV8_Msk         (0x1UL << HRTIM_BMTRGR_EEV8_Pos)         /*!< 0x40000000 */
+#define HRTIM_BMTRGR_EEV8             HRTIM_BMTRGR_EEV8_Msk                    /*!< External Event 8 */
+#define HRTIM_BMTRGR_OCHPEV_Pos       (31U)
+#define HRTIM_BMTRGR_OCHPEV_Msk       (0x1UL << HRTIM_BMTRGR_OCHPEV_Pos)       /*!< 0x80000000 */
+#define HRTIM_BMTRGR_OCHPEV           HRTIM_BMTRGR_OCHPEV_Msk                  /*!< on-chip Event */
+
+/*******************  Bit definition for HRTIM_BMCMPR register  ***************/
+#define HRTIM_BMCMPR_BMCMPR_Pos       (0U)
+#define HRTIM_BMCMPR_BMCMPR_Msk       (0xFFFFUL << HRTIM_BMCMPR_BMCMPR_Pos)    /*!< 0x0000FFFF */
+#define HRTIM_BMCMPR_BMCMPR           HRTIM_BMCMPR_BMCMPR_Msk                  /*!<!<Burst Compare Value */
+
+/*******************  Bit definition for HRTIM_BMPER register  ****************/
+#define HRTIM_BMPER_BMPER_Pos         (0U)
+#define HRTIM_BMPER_BMPER_Msk         (0xFFFFUL << HRTIM_BMPER_BMPER_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_BMPER_BMPER             HRTIM_BMPER_BMPER_Msk                    /*!<!<Burst period Value */
+
+/*******************  Bit definition for HRTIM_EECR1 register  ****************/
+#define HRTIM_EECR1_EE1SRC_Pos        (0U)
+#define HRTIM_EECR1_EE1SRC_Msk        (0x3UL << HRTIM_EECR1_EE1SRC_Pos)        /*!< 0x00000003 */
+#define HRTIM_EECR1_EE1SRC            HRTIM_EECR1_EE1SRC_Msk                   /*!< External event 1 source */
+#define HRTIM_EECR1_EE1SRC_0          (0x1UL << HRTIM_EECR1_EE1SRC_Pos)         /*!< 0x00000001 */
+#define HRTIM_EECR1_EE1SRC_1          (0x2UL << HRTIM_EECR1_EE1SRC_Pos)         /*!< 0x00000002 */
+#define HRTIM_EECR1_EE1POL_Pos        (2U)
+#define HRTIM_EECR1_EE1POL_Msk        (0x1UL << HRTIM_EECR1_EE1POL_Pos)        /*!< 0x00000004 */
+#define HRTIM_EECR1_EE1POL            HRTIM_EECR1_EE1POL_Msk                   /*!< External event 1 Polarity */
+#define HRTIM_EECR1_EE1SNS_Pos        (3U)
+#define HRTIM_EECR1_EE1SNS_Msk        (0x3UL << HRTIM_EECR1_EE1SNS_Pos)        /*!< 0x00000018 */
+#define HRTIM_EECR1_EE1SNS            HRTIM_EECR1_EE1SNS_Msk                   /*!< External event 1 sensitivity */
+#define HRTIM_EECR1_EE1SNS_0          (0x1UL << HRTIM_EECR1_EE1SNS_Pos)         /*!< 0x00000008 */
+#define HRTIM_EECR1_EE1SNS_1          (0x2UL << HRTIM_EECR1_EE1SNS_Pos)         /*!< 0x00000010 */
+#define HRTIM_EECR1_EE1FAST_Pos       (5U)
+#define HRTIM_EECR1_EE1FAST_Msk       (0x1UL << HRTIM_EECR1_EE1FAST_Pos)       /*!< 0x00000020 */
+#define HRTIM_EECR1_EE1FAST           HRTIM_EECR1_EE1FAST_Msk                  /*!< External event 1 Fast mode */
+
+#define HRTIM_EECR1_EE2SRC_Pos        (6U)
+#define HRTIM_EECR1_EE2SRC_Msk        (0x3UL << HRTIM_EECR1_EE2SRC_Pos)        /*!< 0x000000C0 */
+#define HRTIM_EECR1_EE2SRC            HRTIM_EECR1_EE2SRC_Msk                   /*!< External event 2 source */
+#define HRTIM_EECR1_EE2SRC_0          (0x1UL << HRTIM_EECR1_EE2SRC_Pos)         /*!< 0x00000040 */
+#define HRTIM_EECR1_EE2SRC_1          (0x2UL << HRTIM_EECR1_EE2SRC_Pos)         /*!< 0x00000080 */
+#define HRTIM_EECR1_EE2POL_Pos        (8U)
+#define HRTIM_EECR1_EE2POL_Msk        (0x1UL << HRTIM_EECR1_EE2POL_Pos)        /*!< 0x00000100 */
+#define HRTIM_EECR1_EE2POL            HRTIM_EECR1_EE2POL_Msk                   /*!< External event 2 Polarity */
+#define HRTIM_EECR1_EE2SNS_Pos        (9U)
+#define HRTIM_EECR1_EE2SNS_Msk        (0x3UL << HRTIM_EECR1_EE2SNS_Pos)        /*!< 0x00000600 */
+#define HRTIM_EECR1_EE2SNS            HRTIM_EECR1_EE2SNS_Msk                   /*!< External event 2 sensitivity */
+#define HRTIM_EECR1_EE2SNS_0          (0x1UL << HRTIM_EECR1_EE2SNS_Pos)         /*!< 0x00000200 */
+#define HRTIM_EECR1_EE2SNS_1          (0x2UL << HRTIM_EECR1_EE2SNS_Pos)         /*!< 0x00000400 */
+#define HRTIM_EECR1_EE2FAST_Pos       (11U)
+#define HRTIM_EECR1_EE2FAST_Msk       (0x1UL << HRTIM_EECR1_EE2FAST_Pos)       /*!< 0x00000800 */
+#define HRTIM_EECR1_EE2FAST           HRTIM_EECR1_EE2FAST_Msk                  /*!< External event 2 Fast mode */
+
+#define HRTIM_EECR1_EE3SRC_Pos        (12U)
+#define HRTIM_EECR1_EE3SRC_Msk        (0x3UL << HRTIM_EECR1_EE3SRC_Pos)        /*!< 0x00003000 */
+#define HRTIM_EECR1_EE3SRC            HRTIM_EECR1_EE3SRC_Msk                   /*!< External event 3 source */
+#define HRTIM_EECR1_EE3SRC_0          (0x1UL << HRTIM_EECR1_EE3SRC_Pos)         /*!< 0x00001000 */
+#define HRTIM_EECR1_EE3SRC_1          (0x2UL << HRTIM_EECR1_EE3SRC_Pos)         /*!< 0x00002000 */
+#define HRTIM_EECR1_EE3POL_Pos        (14U)
+#define HRTIM_EECR1_EE3POL_Msk        (0x1UL << HRTIM_EECR1_EE3POL_Pos)        /*!< 0x00004000 */
+#define HRTIM_EECR1_EE3POL            HRTIM_EECR1_EE3POL_Msk                   /*!< External event 3 Polarity */
+#define HRTIM_EECR1_EE3SNS_Pos        (15U)
+#define HRTIM_EECR1_EE3SNS_Msk        (0x3UL << HRTIM_EECR1_EE3SNS_Pos)        /*!< 0x00018000 */
+#define HRTIM_EECR1_EE3SNS            HRTIM_EECR1_EE3SNS_Msk                   /*!< External event 3 sensitivity */
+#define HRTIM_EECR1_EE3SNS_0          (0x1UL << HRTIM_EECR1_EE3SNS_Pos)         /*!< 0x00008000 */
+#define HRTIM_EECR1_EE3SNS_1          (0x2UL << HRTIM_EECR1_EE3SNS_Pos)         /*!< 0x00010000 */
+#define HRTIM_EECR1_EE3FAST_Pos       (17U)
+#define HRTIM_EECR1_EE3FAST_Msk       (0x1UL << HRTIM_EECR1_EE3FAST_Pos)       /*!< 0x00020000 */
+#define HRTIM_EECR1_EE3FAST           HRTIM_EECR1_EE3FAST_Msk                  /*!< External event 3 Fast mode */
+
+#define HRTIM_EECR1_EE4SRC_Pos        (18U)
+#define HRTIM_EECR1_EE4SRC_Msk        (0x3UL << HRTIM_EECR1_EE4SRC_Pos)        /*!< 0x000C0000 */
+#define HRTIM_EECR1_EE4SRC            HRTIM_EECR1_EE4SRC_Msk                   /*!< External event 4 source */
+#define HRTIM_EECR1_EE4SRC_0          (0x1UL << HRTIM_EECR1_EE4SRC_Pos)         /*!< 0x00040000 */
+#define HRTIM_EECR1_EE4SRC_1          (0x2UL << HRTIM_EECR1_EE4SRC_Pos)         /*!< 0x00080000 */
+#define HRTIM_EECR1_EE4POL_Pos        (20U)
+#define HRTIM_EECR1_EE4POL_Msk        (0x1UL << HRTIM_EECR1_EE4POL_Pos)        /*!< 0x00100000 */
+#define HRTIM_EECR1_EE4POL            HRTIM_EECR1_EE4POL_Msk                   /*!< External event 4 Polarity */
+#define HRTIM_EECR1_EE4SNS_Pos        (21U)
+#define HRTIM_EECR1_EE4SNS_Msk        (0x3UL << HRTIM_EECR1_EE4SNS_Pos)        /*!< 0x00600000 */
+#define HRTIM_EECR1_EE4SNS            HRTIM_EECR1_EE4SNS_Msk                   /*!< External event 4 sensitivity */
+#define HRTIM_EECR1_EE4SNS_0          (0x1UL << HRTIM_EECR1_EE4SNS_Pos)         /*!< 0x00200000 */
+#define HRTIM_EECR1_EE4SNS_1          (0x2UL << HRTIM_EECR1_EE4SNS_Pos)         /*!< 0x00400000 */
+#define HRTIM_EECR1_EE4FAST_Pos       (23U)
+#define HRTIM_EECR1_EE4FAST_Msk       (0x1UL << HRTIM_EECR1_EE4FAST_Pos)       /*!< 0x00800000 */
+#define HRTIM_EECR1_EE4FAST           HRTIM_EECR1_EE4FAST_Msk                  /*!< External event 4 Fast mode */
+
+#define HRTIM_EECR1_EE5SRC_Pos        (24U)
+#define HRTIM_EECR1_EE5SRC_Msk        (0x3UL << HRTIM_EECR1_EE5SRC_Pos)        /*!< 0x03000000 */
+#define HRTIM_EECR1_EE5SRC            HRTIM_EECR1_EE5SRC_Msk                   /*!< External event 5 source */
+#define HRTIM_EECR1_EE5SRC_0          (0x1UL << HRTIM_EECR1_EE5SRC_Pos)         /*!< 0x01000000 */
+#define HRTIM_EECR1_EE5SRC_1          (0x2UL << HRTIM_EECR1_EE5SRC_Pos)         /*!< 0x02000000 */
+#define HRTIM_EECR1_EE5POL_Pos        (26U)
+#define HRTIM_EECR1_EE5POL_Msk        (0x1UL << HRTIM_EECR1_EE5POL_Pos)        /*!< 0x04000000 */
+#define HRTIM_EECR1_EE5POL            HRTIM_EECR1_EE5POL_Msk                   /*!< External event 5 Polarity */
+#define HRTIM_EECR1_EE5SNS_Pos        (27U)
+#define HRTIM_EECR1_EE5SNS_Msk        (0x3UL << HRTIM_EECR1_EE5SNS_Pos)        /*!< 0x18000000 */
+#define HRTIM_EECR1_EE5SNS            HRTIM_EECR1_EE5SNS_Msk                   /*!< External event 5 sensitivity */
+#define HRTIM_EECR1_EE5SNS_0          (0x1UL << HRTIM_EECR1_EE5SNS_Pos)         /*!< 0x08000000 */
+#define HRTIM_EECR1_EE5SNS_1          (0x2UL << HRTIM_EECR1_EE5SNS_Pos)         /*!< 0x10000000 */
+#define HRTIM_EECR1_EE5FAST_Pos       (29U)
+#define HRTIM_EECR1_EE5FAST_Msk       (0x1UL << HRTIM_EECR1_EE5FAST_Pos)       /*!< 0x20000000 */
+#define HRTIM_EECR1_EE5FAST           HRTIM_EECR1_EE5FAST_Msk                  /*!< External event 5 Fast mode */
+
+/*******************  Bit definition for HRTIM_EECR2 register  ****************/
+#define HRTIM_EECR2_EE6SRC_Pos        (0U)
+#define HRTIM_EECR2_EE6SRC_Msk        (0x3UL << HRTIM_EECR2_EE6SRC_Pos)        /*!< 0x00000003 */
+#define HRTIM_EECR2_EE6SRC            HRTIM_EECR2_EE6SRC_Msk                   /*!< External event 6 source */
+#define HRTIM_EECR2_EE6SRC_0          (0x1UL << HRTIM_EECR2_EE6SRC_Pos)         /*!< 0x00000001 */
+#define HRTIM_EECR2_EE6SRC_1          (0x2UL << HRTIM_EECR2_EE6SRC_Pos)         /*!< 0x00000002 */
+#define HRTIM_EECR2_EE6POL_Pos        (2U)
+#define HRTIM_EECR2_EE6POL_Msk        (0x1UL << HRTIM_EECR2_EE6POL_Pos)        /*!< 0x00000004 */
+#define HRTIM_EECR2_EE6POL            HRTIM_EECR2_EE6POL_Msk                   /*!< External event 6 Polarity */
+#define HRTIM_EECR2_EE6SNS_Pos        (3U)
+#define HRTIM_EECR2_EE6SNS_Msk        (0x3UL << HRTIM_EECR2_EE6SNS_Pos)        /*!< 0x00000018 */
+#define HRTIM_EECR2_EE6SNS            HRTIM_EECR2_EE6SNS_Msk                   /*!< External event 6 sensitivity */
+#define HRTIM_EECR2_EE6SNS_0          (0x1UL << HRTIM_EECR2_EE6SNS_Pos)         /*!< 0x00000008 */
+#define HRTIM_EECR2_EE6SNS_1          (0x2UL << HRTIM_EECR2_EE6SNS_Pos)         /*!< 0x00000010 */
+
+#define HRTIM_EECR2_EE7SRC_Pos        (6U)
+#define HRTIM_EECR2_EE7SRC_Msk        (0x3UL << HRTIM_EECR2_EE7SRC_Pos)        /*!< 0x000000C0 */
+#define HRTIM_EECR2_EE7SRC            HRTIM_EECR2_EE7SRC_Msk                   /*!< External event 7 source */
+#define HRTIM_EECR2_EE7SRC_0          (0x1UL << HRTIM_EECR2_EE7SRC_Pos)         /*!< 0x00000040 */
+#define HRTIM_EECR2_EE7SRC_1          (0x2UL << HRTIM_EECR2_EE7SRC_Pos)         /*!< 0x00000080 */
+#define HRTIM_EECR2_EE7POL_Pos        (8U)
+#define HRTIM_EECR2_EE7POL_Msk        (0x1UL << HRTIM_EECR2_EE7POL_Pos)        /*!< 0x00000100 */
+#define HRTIM_EECR2_EE7POL            HRTIM_EECR2_EE7POL_Msk                   /*!< External event 7 Polarity */
+#define HRTIM_EECR2_EE7SNS_Pos        (9U)
+#define HRTIM_EECR2_EE7SNS_Msk        (0x3UL << HRTIM_EECR2_EE7SNS_Pos)        /*!< 0x00000600 */
+#define HRTIM_EECR2_EE7SNS            HRTIM_EECR2_EE7SNS_Msk                   /*!< External event 7 sensitivity */
+#define HRTIM_EECR2_EE7SNS_0          (0x1UL << HRTIM_EECR2_EE7SNS_Pos)         /*!< 0x00000200 */
+#define HRTIM_EECR2_EE7SNS_1          (0x2UL << HRTIM_EECR2_EE7SNS_Pos)         /*!< 0x00000400 */
+
+#define HRTIM_EECR2_EE8SRC_Pos        (12U)
+#define HRTIM_EECR2_EE8SRC_Msk        (0x3UL << HRTIM_EECR2_EE8SRC_Pos)        /*!< 0x00003000 */
+#define HRTIM_EECR2_EE8SRC            HRTIM_EECR2_EE8SRC_Msk                   /*!< External event 8 source */
+#define HRTIM_EECR2_EE8SRC_0          (0x1UL << HRTIM_EECR2_EE8SRC_Pos)         /*!< 0x00001000 */
+#define HRTIM_EECR2_EE8SRC_1          (0x2UL << HRTIM_EECR2_EE8SRC_Pos)         /*!< 0x00002000 */
+#define HRTIM_EECR2_EE8POL_Pos        (14U)
+#define HRTIM_EECR2_EE8POL_Msk        (0x1UL << HRTIM_EECR2_EE8POL_Pos)        /*!< 0x00004000 */
+#define HRTIM_EECR2_EE8POL            HRTIM_EECR2_EE8POL_Msk                   /*!< External event 8 Polarity */
+#define HRTIM_EECR2_EE8SNS_Pos        (15U)
+#define HRTIM_EECR2_EE8SNS_Msk        (0x3UL << HRTIM_EECR2_EE8SNS_Pos)        /*!< 0x00018000 */
+#define HRTIM_EECR2_EE8SNS            HRTIM_EECR2_EE8SNS_Msk                   /*!< External event 8 sensitivity */
+#define HRTIM_EECR2_EE8SNS_0          (0x1UL << HRTIM_EECR2_EE8SNS_Pos)         /*!< 0x00008000 */
+#define HRTIM_EECR2_EE8SNS_1          (0x2UL << HRTIM_EECR2_EE8SNS_Pos)         /*!< 0x00010000 */
+
+#define HRTIM_EECR2_EE9SRC_Pos        (18U)
+#define HRTIM_EECR2_EE9SRC_Msk        (0x3UL << HRTIM_EECR2_EE9SRC_Pos)        /*!< 0x000C0000 */
+#define HRTIM_EECR2_EE9SRC            HRTIM_EECR2_EE9SRC_Msk                   /*!< External event 9 source */
+#define HRTIM_EECR2_EE9SRC_0          (0x1UL << HRTIM_EECR2_EE9SRC_Pos)         /*!< 0x00040000 */
+#define HRTIM_EECR2_EE9SRC_1          (0x2UL << HRTIM_EECR2_EE9SRC_Pos)         /*!< 0x00080000 */
+#define HRTIM_EECR2_EE9POL_Pos        (20U)
+#define HRTIM_EECR2_EE9POL_Msk        (0x1UL << HRTIM_EECR2_EE9POL_Pos)        /*!< 0x00100000 */
+#define HRTIM_EECR2_EE9POL            HRTIM_EECR2_EE9POL_Msk                   /*!< External event 9 Polarity */
+#define HRTIM_EECR2_EE9SNS_Pos        (21U)
+#define HRTIM_EECR2_EE9SNS_Msk        (0x3UL << HRTIM_EECR2_EE9SNS_Pos)        /*!< 0x00600000 */
+#define HRTIM_EECR2_EE9SNS            HRTIM_EECR2_EE9SNS_Msk                   /*!< External event 9 sensitivity */
+#define HRTIM_EECR2_EE9SNS_0          (0x1UL << HRTIM_EECR2_EE9SNS_Pos)         /*!< 0x00200000 */
+#define HRTIM_EECR2_EE9SNS_1          (0x2UL << HRTIM_EECR2_EE9SNS_Pos)         /*!< 0x00400000 */
+
+#define HRTIM_EECR2_EE10SRC_Pos       (24U)
+#define HRTIM_EECR2_EE10SRC_Msk       (0x3UL << HRTIM_EECR2_EE10SRC_Pos)       /*!< 0x03000000 */
+#define HRTIM_EECR2_EE10SRC           HRTIM_EECR2_EE10SRC_Msk                  /*!< External event 10 source */
+#define HRTIM_EECR2_EE10SRC_0         (0x1UL << HRTIM_EECR2_EE10SRC_Pos)        /*!< 0x01000000 */
+#define HRTIM_EECR2_EE10SRC_1         (0x2UL << HRTIM_EECR2_EE10SRC_Pos)        /*!< 0x02000000 */
+#define HRTIM_EECR2_EE10POL_Pos       (26U)
+#define HRTIM_EECR2_EE10POL_Msk       (0x1UL << HRTIM_EECR2_EE10POL_Pos)       /*!< 0x04000000 */
+#define HRTIM_EECR2_EE10POL           HRTIM_EECR2_EE10POL_Msk                  /*!< External event 10 Polarity */
+#define HRTIM_EECR2_EE10SNS_Pos       (27U)
+#define HRTIM_EECR2_EE10SNS_Msk       (0x3UL << HRTIM_EECR2_EE10SNS_Pos)       /*!< 0x18000000 */
+#define HRTIM_EECR2_EE10SNS           HRTIM_EECR2_EE10SNS_Msk                  /*!< External event 10 sensitivity */
+#define HRTIM_EECR2_EE10SNS_0         (0x1UL << HRTIM_EECR2_EE10SNS_Pos)        /*!< 0x08000000 */
+#define HRTIM_EECR2_EE10SNS_1         (0x2UL << HRTIM_EECR2_EE10SNS_Pos)        /*!< 0x10000000 */
+
+/*******************  Bit definition for HRTIM_EECR3 register  ****************/
+#define HRTIM_EECR3_EE6F_Pos          (0U)
+#define HRTIM_EECR3_EE6F_Msk          (0xFUL << HRTIM_EECR3_EE6F_Pos)          /*!< 0x0000000F */
+#define HRTIM_EECR3_EE6F              HRTIM_EECR3_EE6F_Msk                     /*!< External event 6 filter */
+#define HRTIM_EECR3_EE6F_0            (0x1UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000001 */
+#define HRTIM_EECR3_EE6F_1            (0x2UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000002 */
+#define HRTIM_EECR3_EE6F_2            (0x4UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000004 */
+#define HRTIM_EECR3_EE6F_3            (0x8UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000008 */
+#define HRTIM_EECR3_EE7F_Pos          (6U)
+#define HRTIM_EECR3_EE7F_Msk          (0xFUL << HRTIM_EECR3_EE7F_Pos)          /*!< 0x000003C0 */
+#define HRTIM_EECR3_EE7F              HRTIM_EECR3_EE7F_Msk                     /*!< External event 7 filter */
+#define HRTIM_EECR3_EE7F_0            (0x1UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000040 */
+#define HRTIM_EECR3_EE7F_1            (0x2UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000080 */
+#define HRTIM_EECR3_EE7F_2            (0x4UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000100 */
+#define HRTIM_EECR3_EE7F_3            (0x8UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000200 */
+#define HRTIM_EECR3_EE8F_Pos          (12U)
+#define HRTIM_EECR3_EE8F_Msk          (0xFUL << HRTIM_EECR3_EE8F_Pos)          /*!< 0x0000F000 */
+#define HRTIM_EECR3_EE8F              HRTIM_EECR3_EE8F_Msk                     /*!< External event 8 filter */
+#define HRTIM_EECR3_EE8F_0            (0x1UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00001000 */
+#define HRTIM_EECR3_EE8F_1            (0x2UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00002000 */
+#define HRTIM_EECR3_EE8F_2            (0x4UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00004000 */
+#define HRTIM_EECR3_EE8F_3            (0x8UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00008000 */
+#define HRTIM_EECR3_EE9F_Pos          (18U)
+#define HRTIM_EECR3_EE9F_Msk          (0xFUL << HRTIM_EECR3_EE9F_Pos)          /*!< 0x003C0000 */
+#define HRTIM_EECR3_EE9F              HRTIM_EECR3_EE9F_Msk                     /*!< External event 9 filter */
+#define HRTIM_EECR3_EE9F_0            (0x1UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00040000 */
+#define HRTIM_EECR3_EE9F_1            (0x2UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00080000 */
+#define HRTIM_EECR3_EE9F_2            (0x4UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00100000 */
+#define HRTIM_EECR3_EE9F_3            (0x8UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00200000 */
+#define HRTIM_EECR3_EE10F_Pos         (24U)
+#define HRTIM_EECR3_EE10F_Msk         (0xFUL << HRTIM_EECR3_EE10F_Pos)         /*!< 0x0F000000 */
+#define HRTIM_EECR3_EE10F             HRTIM_EECR3_EE10F_Msk                    /*!< External event 10 filter */
+#define HRTIM_EECR3_EE10F_0           (0x1UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x01000000 */
+#define HRTIM_EECR3_EE10F_1           (0x2UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x02000000 */
+#define HRTIM_EECR3_EE10F_2           (0x4UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x04000000 */
+#define HRTIM_EECR3_EE10F_3           (0x8UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x08000000 */
+#define HRTIM_EECR3_EEVSD_Pos         (30U)
+#define HRTIM_EECR3_EEVSD_Msk         (0x3UL << HRTIM_EECR3_EEVSD_Pos)         /*!< 0xC0000000 */
+#define HRTIM_EECR3_EEVSD             HRTIM_EECR3_EEVSD_Msk                    /*!< External event sampling clock division */
+#define HRTIM_EECR3_EEVSD_0           (0x1UL << HRTIM_EECR3_EEVSD_Pos)          /*!< 0x40000000 */
+#define HRTIM_EECR3_EEVSD_1           (0x2UL << HRTIM_EECR3_EEVSD_Pos)          /*!< 0x80000000 */
+
+/*******************  Bit definition for HRTIM_ADC1R register  ****************/
+#define HRTIM_ADC1R_AD1MC1_Pos        (0U)
+#define HRTIM_ADC1R_AD1MC1_Msk        (0x1UL << HRTIM_ADC1R_AD1MC1_Pos)        /*!< 0x00000001 */
+#define HRTIM_ADC1R_AD1MC1            HRTIM_ADC1R_AD1MC1_Msk                   /*!< ADC Trigger 1 on master compare 1 */
+#define HRTIM_ADC1R_AD1MC2_Pos        (1U)
+#define HRTIM_ADC1R_AD1MC2_Msk        (0x1UL << HRTIM_ADC1R_AD1MC2_Pos)        /*!< 0x00000002 */
+#define HRTIM_ADC1R_AD1MC2            HRTIM_ADC1R_AD1MC2_Msk                   /*!< ADC Trigger 1 on master compare 2 */
+#define HRTIM_ADC1R_AD1MC3_Pos        (2U)
+#define HRTIM_ADC1R_AD1MC3_Msk        (0x1UL << HRTIM_ADC1R_AD1MC3_Pos)        /*!< 0x00000004 */
+#define HRTIM_ADC1R_AD1MC3            HRTIM_ADC1R_AD1MC3_Msk                   /*!< ADC Trigger 1 on master compare 3 */
+#define HRTIM_ADC1R_AD1MC4_Pos        (3U)
+#define HRTIM_ADC1R_AD1MC4_Msk        (0x1UL << HRTIM_ADC1R_AD1MC4_Pos)        /*!< 0x00000008 */
+#define HRTIM_ADC1R_AD1MC4            HRTIM_ADC1R_AD1MC4_Msk                   /*!< ADC Trigger 1 on master compare 4 */
+#define HRTIM_ADC1R_AD1MPER_Pos       (4U)
+#define HRTIM_ADC1R_AD1MPER_Msk       (0x1UL << HRTIM_ADC1R_AD1MPER_Pos)       /*!< 0x00000010 */
+#define HRTIM_ADC1R_AD1MPER           HRTIM_ADC1R_AD1MPER_Msk                  /*!< ADC Trigger 1 on master period */
+#define HRTIM_ADC1R_AD1EEV1_Pos       (5U)
+#define HRTIM_ADC1R_AD1EEV1_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV1_Pos)       /*!< 0x00000020 */
+#define HRTIM_ADC1R_AD1EEV1           HRTIM_ADC1R_AD1EEV1_Msk                  /*!< ADC Trigger 1 on external event 1 */
+#define HRTIM_ADC1R_AD1EEV2_Pos       (6U)
+#define HRTIM_ADC1R_AD1EEV2_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV2_Pos)       /*!< 0x00000040 */
+#define HRTIM_ADC1R_AD1EEV2           HRTIM_ADC1R_AD1EEV2_Msk                  /*!< ADC Trigger 1 on external event 2 */
+#define HRTIM_ADC1R_AD1EEV3_Pos       (7U)
+#define HRTIM_ADC1R_AD1EEV3_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV3_Pos)       /*!< 0x00000080 */
+#define HRTIM_ADC1R_AD1EEV3           HRTIM_ADC1R_AD1EEV3_Msk                  /*!< ADC Trigger 1 on external event 3 */
+#define HRTIM_ADC1R_AD1EEV4_Pos       (8U)
+#define HRTIM_ADC1R_AD1EEV4_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV4_Pos)       /*!< 0x00000100 */
+#define HRTIM_ADC1R_AD1EEV4           HRTIM_ADC1R_AD1EEV4_Msk                  /*!< ADC Trigger 1 on external event 4 */
+#define HRTIM_ADC1R_AD1EEV5_Pos       (9U)
+#define HRTIM_ADC1R_AD1EEV5_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV5_Pos)       /*!< 0x00000200 */
+#define HRTIM_ADC1R_AD1EEV5           HRTIM_ADC1R_AD1EEV5_Msk                  /*!< ADC Trigger 1 on external event 5 */
+#define HRTIM_ADC1R_AD1TAC2_Pos       (10U)
+#define HRTIM_ADC1R_AD1TAC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC2_Pos)       /*!< 0x00000400 */
+#define HRTIM_ADC1R_AD1TAC2           HRTIM_ADC1R_AD1TAC2_Msk                  /*!< ADC Trigger 1 on Timer A compare 2 */
+#define HRTIM_ADC1R_AD1TAC3_Pos       (11U)
+#define HRTIM_ADC1R_AD1TAC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC3_Pos)       /*!< 0x00000800 */
+#define HRTIM_ADC1R_AD1TAC3           HRTIM_ADC1R_AD1TAC3_Msk                  /*!< ADC Trigger 1 on Timer A compare 3 */
+#define HRTIM_ADC1R_AD1TAC4_Pos       (12U)
+#define HRTIM_ADC1R_AD1TAC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC4_Pos)       /*!< 0x00001000 */
+#define HRTIM_ADC1R_AD1TAC4           HRTIM_ADC1R_AD1TAC4_Msk                  /*!< ADC Trigger 1 on Timer A compare 4 */
+#define HRTIM_ADC1R_AD1TAPER_Pos      (13U)
+#define HRTIM_ADC1R_AD1TAPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TAPER_Pos)      /*!< 0x00002000 */
+#define HRTIM_ADC1R_AD1TAPER          HRTIM_ADC1R_AD1TAPER_Msk                 /*!< ADC Trigger 1 on Timer A period */
+#define HRTIM_ADC1R_AD1TARST_Pos      (14U)
+#define HRTIM_ADC1R_AD1TARST_Msk      (0x1UL << HRTIM_ADC1R_AD1TARST_Pos)      /*!< 0x00004000 */
+#define HRTIM_ADC1R_AD1TARST          HRTIM_ADC1R_AD1TARST_Msk                 /*!< ADC Trigger 1 on Timer A reset */
+#define HRTIM_ADC1R_AD1TBC2_Pos       (15U)
+#define HRTIM_ADC1R_AD1TBC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC2_Pos)       /*!< 0x00008000 */
+#define HRTIM_ADC1R_AD1TBC2           HRTIM_ADC1R_AD1TBC2_Msk                  /*!< ADC Trigger 1 on Timer B compare 2 */
+#define HRTIM_ADC1R_AD1TBC3_Pos       (16U)
+#define HRTIM_ADC1R_AD1TBC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC3_Pos)       /*!< 0x00010000 */
+#define HRTIM_ADC1R_AD1TBC3           HRTIM_ADC1R_AD1TBC3_Msk                  /*!< ADC Trigger 1 on Timer B compare 3 */
+#define HRTIM_ADC1R_AD1TBC4_Pos       (17U)
+#define HRTIM_ADC1R_AD1TBC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC4_Pos)       /*!< 0x00020000 */
+#define HRTIM_ADC1R_AD1TBC4           HRTIM_ADC1R_AD1TBC4_Msk                  /*!< ADC Trigger 1 on Timer B compare 4 */
+#define HRTIM_ADC1R_AD1TBPER_Pos      (18U)
+#define HRTIM_ADC1R_AD1TBPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TBPER_Pos)      /*!< 0x00040000 */
+#define HRTIM_ADC1R_AD1TBPER          HRTIM_ADC1R_AD1TBPER_Msk                 /*!< ADC Trigger 1 on Timer B period */
+#define HRTIM_ADC1R_AD1TBRST_Pos      (19U)
+#define HRTIM_ADC1R_AD1TBRST_Msk      (0x1UL << HRTIM_ADC1R_AD1TBRST_Pos)      /*!< 0x00080000 */
+#define HRTIM_ADC1R_AD1TBRST          HRTIM_ADC1R_AD1TBRST_Msk                 /*!< ADC Trigger 1 on Timer B reset */
+#define HRTIM_ADC1R_AD1TCC2_Pos       (20U)
+#define HRTIM_ADC1R_AD1TCC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC2_Pos)       /*!< 0x00100000 */
+#define HRTIM_ADC1R_AD1TCC2           HRTIM_ADC1R_AD1TCC2_Msk                  /*!< ADC Trigger 1 on Timer C compare 2 */
+#define HRTIM_ADC1R_AD1TCC3_Pos       (21U)
+#define HRTIM_ADC1R_AD1TCC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC3_Pos)       /*!< 0x00200000 */
+#define HRTIM_ADC1R_AD1TCC3           HRTIM_ADC1R_AD1TCC3_Msk                  /*!< ADC Trigger 1 on Timer C compare 3 */
+#define HRTIM_ADC1R_AD1TCC4_Pos       (22U)
+#define HRTIM_ADC1R_AD1TCC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC4_Pos)       /*!< 0x00400000 */
+#define HRTIM_ADC1R_AD1TCC4           HRTIM_ADC1R_AD1TCC4_Msk                  /*!< ADC Trigger 1 on Timer C compare 4 */
+#define HRTIM_ADC1R_AD1TCPER_Pos      (23U)
+#define HRTIM_ADC1R_AD1TCPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TCPER_Pos)      /*!< 0x00800000 */
+#define HRTIM_ADC1R_AD1TCPER          HRTIM_ADC1R_AD1TCPER_Msk                 /*!< ADC Trigger 1 on Timer C period */
+#define HRTIM_ADC1R_AD1TDC2_Pos       (24U)
+#define HRTIM_ADC1R_AD1TDC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC2_Pos)       /*!< 0x01000000 */
+#define HRTIM_ADC1R_AD1TDC2           HRTIM_ADC1R_AD1TDC2_Msk                  /*!< ADC Trigger 1 on Timer D compare 2 */
+#define HRTIM_ADC1R_AD1TDC3_Pos       (25U)
+#define HRTIM_ADC1R_AD1TDC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC3_Pos)       /*!< 0x02000000 */
+#define HRTIM_ADC1R_AD1TDC3           HRTIM_ADC1R_AD1TDC3_Msk                  /*!< ADC Trigger 1 on Timer D compare 3 */
+#define HRTIM_ADC1R_AD1TDC4_Pos       (26U)
+#define HRTIM_ADC1R_AD1TDC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC4_Pos)       /*!< 0x04000000 */
+#define HRTIM_ADC1R_AD1TDC4           HRTIM_ADC1R_AD1TDC4_Msk                  /*!< ADC Trigger 1 on Timer D compare 4 */
+#define HRTIM_ADC1R_AD1TDPER_Pos      (27U)
+#define HRTIM_ADC1R_AD1TDPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TDPER_Pos)      /*!< 0x08000000 */
+#define HRTIM_ADC1R_AD1TDPER          HRTIM_ADC1R_AD1TDPER_Msk                 /*!< ADC Trigger 1 on Timer D period */
+#define HRTIM_ADC1R_AD1TEC2_Pos       (28U)
+#define HRTIM_ADC1R_AD1TEC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC2_Pos)       /*!< 0x10000000 */
+#define HRTIM_ADC1R_AD1TEC2           HRTIM_ADC1R_AD1TEC2_Msk                  /*!< ADC Trigger 1 on Timer E compare 2 */
+#define HRTIM_ADC1R_AD1TEC3_Pos       (29U)
+#define HRTIM_ADC1R_AD1TEC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC3_Pos)       /*!< 0x20000000 */
+#define HRTIM_ADC1R_AD1TEC3           HRTIM_ADC1R_AD1TEC3_Msk                  /*!< ADC Trigger 1 on Timer E compare 3 */
+#define HRTIM_ADC1R_AD1TEC4_Pos       (30U)
+#define HRTIM_ADC1R_AD1TEC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC4_Pos)       /*!< 0x40000000 */
+#define HRTIM_ADC1R_AD1TEC4           HRTIM_ADC1R_AD1TEC4_Msk                  /*!< ADC Trigger 1 on Timer E compare 4 */
+#define HRTIM_ADC1R_AD1TEPER_Pos      (31U)
+#define HRTIM_ADC1R_AD1TEPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TEPER_Pos)      /*!< 0x80000000 */
+#define HRTIM_ADC1R_AD1TEPER          HRTIM_ADC1R_AD1TEPER_Msk                 /*!< ADC Trigger 1 on Timer E period */
+
+/*******************  Bit definition for HRTIM_ADC2R register  ****************/
+#define HRTIM_ADC2R_AD2MC1_Pos        (0U)
+#define HRTIM_ADC2R_AD2MC1_Msk        (0x1UL << HRTIM_ADC2R_AD2MC1_Pos)        /*!< 0x00000001 */
+#define HRTIM_ADC2R_AD2MC1            HRTIM_ADC2R_AD2MC1_Msk                   /*!< ADC Trigger 2 on master compare 1 */
+#define HRTIM_ADC2R_AD2MC2_Pos        (1U)
+#define HRTIM_ADC2R_AD2MC2_Msk        (0x1UL << HRTIM_ADC2R_AD2MC2_Pos)        /*!< 0x00000002 */
+#define HRTIM_ADC2R_AD2MC2            HRTIM_ADC2R_AD2MC2_Msk                   /*!< ADC Trigger 2 on master compare 2 */
+#define HRTIM_ADC2R_AD2MC3_Pos        (2U)
+#define HRTIM_ADC2R_AD2MC3_Msk        (0x1UL << HRTIM_ADC2R_AD2MC3_Pos)        /*!< 0x00000004 */
+#define HRTIM_ADC2R_AD2MC3            HRTIM_ADC2R_AD2MC3_Msk                   /*!< ADC Trigger 2 on master compare 3 */
+#define HRTIM_ADC2R_AD2MC4_Pos        (3U)
+#define HRTIM_ADC2R_AD2MC4_Msk        (0x1UL << HRTIM_ADC2R_AD2MC4_Pos)        /*!< 0x00000008 */
+#define HRTIM_ADC2R_AD2MC4            HRTIM_ADC2R_AD2MC4_Msk                   /*!< ADC Trigger 2 on master compare 4 */
+#define HRTIM_ADC2R_AD2MPER_Pos       (4U)
+#define HRTIM_ADC2R_AD2MPER_Msk       (0x1UL << HRTIM_ADC2R_AD2MPER_Pos)       /*!< 0x00000010 */
+#define HRTIM_ADC2R_AD2MPER           HRTIM_ADC2R_AD2MPER_Msk                  /*!< ADC Trigger 2 on master period */
+#define HRTIM_ADC2R_AD2EEV6_Pos       (5U)
+#define HRTIM_ADC2R_AD2EEV6_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV6_Pos)       /*!< 0x00000020 */
+#define HRTIM_ADC2R_AD2EEV6           HRTIM_ADC2R_AD2EEV6_Msk                  /*!< ADC Trigger 2 on external event 6 */
+#define HRTIM_ADC2R_AD2EEV7_Pos       (6U)
+#define HRTIM_ADC2R_AD2EEV7_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV7_Pos)       /*!< 0x00000040 */
+#define HRTIM_ADC2R_AD2EEV7           HRTIM_ADC2R_AD2EEV7_Msk                  /*!< ADC Trigger 2 on external event 7 */
+#define HRTIM_ADC2R_AD2EEV8_Pos       (7U)
+#define HRTIM_ADC2R_AD2EEV8_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV8_Pos)       /*!< 0x00000080 */
+#define HRTIM_ADC2R_AD2EEV8           HRTIM_ADC2R_AD2EEV8_Msk                  /*!< ADC Trigger 2 on external event 8 */
+#define HRTIM_ADC2R_AD2EEV9_Pos       (8U)
+#define HRTIM_ADC2R_AD2EEV9_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV9_Pos)       /*!< 0x00000100 */
+#define HRTIM_ADC2R_AD2EEV9           HRTIM_ADC2R_AD2EEV9_Msk                  /*!< ADC Trigger 2 on external event 9 */
+#define HRTIM_ADC2R_AD2EEV10_Pos      (9U)
+#define HRTIM_ADC2R_AD2EEV10_Msk      (0x1UL << HRTIM_ADC2R_AD2EEV10_Pos)      /*!< 0x00000200 */
+#define HRTIM_ADC2R_AD2EEV10          HRTIM_ADC2R_AD2EEV10_Msk                 /*!< ADC Trigger 2 on external event 10 */
+#define HRTIM_ADC2R_AD2TAC2_Pos       (10U)
+#define HRTIM_ADC2R_AD2TAC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC2_Pos)       /*!< 0x00000400 */
+#define HRTIM_ADC2R_AD2TAC2           HRTIM_ADC2R_AD2TAC2_Msk                  /*!< ADC Trigger 2 on Timer A compare 2 */
+#define HRTIM_ADC2R_AD2TAC3_Pos       (11U)
+#define HRTIM_ADC2R_AD2TAC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC3_Pos)       /*!< 0x00000800 */
+#define HRTIM_ADC2R_AD2TAC3           HRTIM_ADC2R_AD2TAC3_Msk                  /*!< ADC Trigger 2 on Timer A compare 3 */
+#define HRTIM_ADC2R_AD2TAC4_Pos       (12U)
+#define HRTIM_ADC2R_AD2TAC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC4_Pos)       /*!< 0x00001000 */
+#define HRTIM_ADC2R_AD2TAC4           HRTIM_ADC2R_AD2TAC4_Msk                  /*!< ADC Trigger 2 on Timer A compare 4*/
+#define HRTIM_ADC2R_AD2TAPER_Pos      (13U)
+#define HRTIM_ADC2R_AD2TAPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TAPER_Pos)      /*!< 0x00002000 */
+#define HRTIM_ADC2R_AD2TAPER          HRTIM_ADC2R_AD2TAPER_Msk                 /*!< ADC Trigger 2 on Timer A period */
+#define HRTIM_ADC2R_AD2TBC2_Pos       (14U)
+#define HRTIM_ADC2R_AD2TBC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC2_Pos)       /*!< 0x00004000 */
+#define HRTIM_ADC2R_AD2TBC2           HRTIM_ADC2R_AD2TBC2_Msk                  /*!< ADC Trigger 2 on Timer B compare 2 */
+#define HRTIM_ADC2R_AD2TBC3_Pos       (15U)
+#define HRTIM_ADC2R_AD2TBC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC3_Pos)       /*!< 0x00008000 */
+#define HRTIM_ADC2R_AD2TBC3           HRTIM_ADC2R_AD2TBC3_Msk                  /*!< ADC Trigger 2 on Timer B compare 3 */
+#define HRTIM_ADC2R_AD2TBC4_Pos       (16U)
+#define HRTIM_ADC2R_AD2TBC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC4_Pos)       /*!< 0x00010000 */
+#define HRTIM_ADC2R_AD2TBC4           HRTIM_ADC2R_AD2TBC4_Msk                  /*!< ADC Trigger 2 on Timer B compare 4 */
+#define HRTIM_ADC2R_AD2TBPER_Pos      (17U)
+#define HRTIM_ADC2R_AD2TBPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TBPER_Pos)      /*!< 0x00020000 */
+#define HRTIM_ADC2R_AD2TBPER          HRTIM_ADC2R_AD2TBPER_Msk                 /*!< ADC Trigger 2 on Timer B period */
+#define HRTIM_ADC2R_AD2TCC2_Pos       (18U)
+#define HRTIM_ADC2R_AD2TCC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC2_Pos)       /*!< 0x00040000 */
+#define HRTIM_ADC2R_AD2TCC2           HRTIM_ADC2R_AD2TCC2_Msk                  /*!< ADC Trigger 2 on Timer C compare 2 */
+#define HRTIM_ADC2R_AD2TCC3_Pos       (19U)
+#define HRTIM_ADC2R_AD2TCC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC3_Pos)       /*!< 0x00080000 */
+#define HRTIM_ADC2R_AD2TCC3           HRTIM_ADC2R_AD2TCC3_Msk                  /*!< ADC Trigger 2 on Timer C compare 3 */
+#define HRTIM_ADC2R_AD2TCC4_Pos       (20U)
+#define HRTIM_ADC2R_AD2TCC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC4_Pos)       /*!< 0x00100000 */
+#define HRTIM_ADC2R_AD2TCC4           HRTIM_ADC2R_AD2TCC4_Msk                  /*!< ADC Trigger 2 on Timer C compare 4 */
+#define HRTIM_ADC2R_AD2TCPER_Pos      (21U)
+#define HRTIM_ADC2R_AD2TCPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TCPER_Pos)      /*!< 0x00200000 */
+#define HRTIM_ADC2R_AD2TCPER          HRTIM_ADC2R_AD2TCPER_Msk                 /*!< ADC Trigger 2 on Timer C period */
+#define HRTIM_ADC2R_AD2TCRST_Pos      (22U)
+#define HRTIM_ADC2R_AD2TCRST_Msk      (0x1UL << HRTIM_ADC2R_AD2TCRST_Pos)      /*!< 0x00400000 */
+#define HRTIM_ADC2R_AD2TCRST          HRTIM_ADC2R_AD2TCRST_Msk                 /*!< ADC Trigger 2 on Timer C reset */
+#define HRTIM_ADC2R_AD2TDC2_Pos       (23U)
+#define HRTIM_ADC2R_AD2TDC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC2_Pos)       /*!< 0x00800000 */
+#define HRTIM_ADC2R_AD2TDC2           HRTIM_ADC2R_AD2TDC2_Msk                  /*!< ADC Trigger 2 on Timer D compare 2 */
+#define HRTIM_ADC2R_AD2TDC3_Pos       (24U)
+#define HRTIM_ADC2R_AD2TDC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC3_Pos)       /*!< 0x01000000 */
+#define HRTIM_ADC2R_AD2TDC3           HRTIM_ADC2R_AD2TDC3_Msk                  /*!< ADC Trigger 2 on Timer D compare 3 */
+#define HRTIM_ADC2R_AD2TDC4_Pos       (25U)
+#define HRTIM_ADC2R_AD2TDC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC4_Pos)       /*!< 0x02000000 */
+#define HRTIM_ADC2R_AD2TDC4           HRTIM_ADC2R_AD2TDC4_Msk                  /*!< ADC Trigger 2 on Timer D compare 4*/
+#define HRTIM_ADC2R_AD2TDPER_Pos      (26U)
+#define HRTIM_ADC2R_AD2TDPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TDPER_Pos)      /*!< 0x04000000 */
+#define HRTIM_ADC2R_AD2TDPER          HRTIM_ADC2R_AD2TDPER_Msk                 /*!< ADC Trigger 2 on Timer D period */
+#define HRTIM_ADC2R_AD2TDRST_Pos      (27U)
+#define HRTIM_ADC2R_AD2TDRST_Msk      (0x1UL << HRTIM_ADC2R_AD2TDRST_Pos)      /*!< 0x08000000 */
+#define HRTIM_ADC2R_AD2TDRST          HRTIM_ADC2R_AD2TDRST_Msk                 /*!< ADC Trigger 2 on Timer D reset */
+#define HRTIM_ADC2R_AD2TEC2_Pos       (28U)
+#define HRTIM_ADC2R_AD2TEC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC2_Pos)       /*!< 0x10000000 */
+#define HRTIM_ADC2R_AD2TEC2           HRTIM_ADC2R_AD2TEC2_Msk                  /*!< ADC Trigger 2 on Timer E compare 2 */
+#define HRTIM_ADC2R_AD2TEC3_Pos       (29U)
+#define HRTIM_ADC2R_AD2TEC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC3_Pos)       /*!< 0x20000000 */
+#define HRTIM_ADC2R_AD2TEC3           HRTIM_ADC2R_AD2TEC3_Msk                  /*!< ADC Trigger 2 on Timer E compare 3 */
+#define HRTIM_ADC2R_AD2TEC4_Pos       (30U)
+#define HRTIM_ADC2R_AD2TEC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC4_Pos)       /*!< 0x40000000 */
+#define HRTIM_ADC2R_AD2TEC4           HRTIM_ADC2R_AD2TEC4_Msk                  /*!< ADC Trigger 2 on Timer E compare 4 */
+#define HRTIM_ADC2R_AD2TERST_Pos      (31U)
+#define HRTIM_ADC2R_AD2TERST_Msk      (0x1UL << HRTIM_ADC2R_AD2TERST_Pos)      /*!< 0x80000000 */
+#define HRTIM_ADC2R_AD2TERST          HRTIM_ADC2R_AD2TERST_Msk                 /*!< ADC Trigger 2 on Timer E reset */
+
+/*******************  Bit definition for HRTIM_ADC3R register  ****************/
+#define HRTIM_ADC3R_AD3MC1_Pos        (0U)
+#define HRTIM_ADC3R_AD3MC1_Msk        (0x1UL << HRTIM_ADC3R_AD3MC1_Pos)        /*!< 0x00000001 */
+#define HRTIM_ADC3R_AD3MC1            HRTIM_ADC3R_AD3MC1_Msk                   /*!< ADC Trigger 3 on master compare 1 */
+#define HRTIM_ADC3R_AD3MC2_Pos        (1U)
+#define HRTIM_ADC3R_AD3MC2_Msk        (0x1UL << HRTIM_ADC3R_AD3MC2_Pos)        /*!< 0x00000002 */
+#define HRTIM_ADC3R_AD3MC2            HRTIM_ADC3R_AD3MC2_Msk                   /*!< ADC Trigger 3 on master compare 2 */
+#define HRTIM_ADC3R_AD3MC3_Pos        (2U)
+#define HRTIM_ADC3R_AD3MC3_Msk        (0x1UL << HRTIM_ADC3R_AD3MC3_Pos)        /*!< 0x00000004 */
+#define HRTIM_ADC3R_AD3MC3            HRTIM_ADC3R_AD3MC3_Msk                   /*!< ADC Trigger 3 on master compare 3 */
+#define HRTIM_ADC3R_AD3MC4_Pos        (3U)
+#define HRTIM_ADC3R_AD3MC4_Msk        (0x1UL << HRTIM_ADC3R_AD3MC4_Pos)        /*!< 0x00000008 */
+#define HRTIM_ADC3R_AD3MC4            HRTIM_ADC3R_AD3MC4_Msk                   /*!< ADC Trigger 3 on master compare 4 */
+#define HRTIM_ADC3R_AD3MPER_Pos       (4U)
+#define HRTIM_ADC3R_AD3MPER_Msk       (0x1UL << HRTIM_ADC3R_AD3MPER_Pos)       /*!< 0x00000010 */
+#define HRTIM_ADC3R_AD3MPER           HRTIM_ADC3R_AD3MPER_Msk                  /*!< ADC Trigger 3 on master period */
+#define HRTIM_ADC3R_AD3EEV1_Pos       (5U)
+#define HRTIM_ADC3R_AD3EEV1_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV1_Pos)       /*!< 0x00000020 */
+#define HRTIM_ADC3R_AD3EEV1           HRTIM_ADC3R_AD3EEV1_Msk                  /*!< ADC Trigger 3 on external event 1 */
+#define HRTIM_ADC3R_AD3EEV2_Pos       (6U)
+#define HRTIM_ADC3R_AD3EEV2_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV2_Pos)       /*!< 0x00000040 */
+#define HRTIM_ADC3R_AD3EEV2           HRTIM_ADC3R_AD3EEV2_Msk                  /*!< ADC Trigger 3 on external event 2 */
+#define HRTIM_ADC3R_AD3EEV3_Pos       (7U)
+#define HRTIM_ADC3R_AD3EEV3_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV3_Pos)       /*!< 0x00000080 */
+#define HRTIM_ADC3R_AD3EEV3           HRTIM_ADC3R_AD3EEV3_Msk                  /*!< ADC Trigger 3 on external event 3 */
+#define HRTIM_ADC3R_AD3EEV4_Pos       (8U)
+#define HRTIM_ADC3R_AD3EEV4_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV4_Pos)       /*!< 0x00000100 */
+#define HRTIM_ADC3R_AD3EEV4           HRTIM_ADC3R_AD3EEV4_Msk                  /*!< ADC Trigger 3 on external event 4 */
+#define HRTIM_ADC3R_AD3EEV5_Pos       (9U)
+#define HRTIM_ADC3R_AD3EEV5_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV5_Pos)       /*!< 0x00000200 */
+#define HRTIM_ADC3R_AD3EEV5           HRTIM_ADC3R_AD3EEV5_Msk                  /*!< ADC Trigger 3 on external event 5 */
+#define HRTIM_ADC3R_AD3TAC2_Pos       (10U)
+#define HRTIM_ADC3R_AD3TAC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC2_Pos)       /*!< 0x00000400 */
+#define HRTIM_ADC3R_AD3TAC2           HRTIM_ADC3R_AD3TAC2_Msk                  /*!< ADC Trigger 3 on Timer A compare 2 */
+#define HRTIM_ADC3R_AD3TAC3_Pos       (11U)
+#define HRTIM_ADC3R_AD3TAC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC3_Pos)       /*!< 0x00000800 */
+#define HRTIM_ADC3R_AD3TAC3           HRTIM_ADC3R_AD3TAC3_Msk                  /*!< ADC Trigger 3 on Timer A compare 3 */
+#define HRTIM_ADC3R_AD3TAC4_Pos       (12U)
+#define HRTIM_ADC3R_AD3TAC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC4_Pos)       /*!< 0x00001000 */
+#define HRTIM_ADC3R_AD3TAC4           HRTIM_ADC3R_AD3TAC4_Msk                  /*!< ADC Trigger 3 on Timer A compare 4 */
+#define HRTIM_ADC3R_AD3TAPER_Pos      (13U)
+#define HRTIM_ADC3R_AD3TAPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TAPER_Pos)      /*!< 0x00002000 */
+#define HRTIM_ADC3R_AD3TAPER          HRTIM_ADC3R_AD3TAPER_Msk                 /*!< ADC Trigger 3 on Timer A period */
+#define HRTIM_ADC3R_AD3TARST_Pos      (14U)
+#define HRTIM_ADC3R_AD3TARST_Msk      (0x1UL << HRTIM_ADC3R_AD3TARST_Pos)      /*!< 0x00004000 */
+#define HRTIM_ADC3R_AD3TARST          HRTIM_ADC3R_AD3TARST_Msk                 /*!< ADC Trigger 3 on Timer A reset */
+#define HRTIM_ADC3R_AD3TBC2_Pos       (15U)
+#define HRTIM_ADC3R_AD3TBC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC2_Pos)       /*!< 0x00008000 */
+#define HRTIM_ADC3R_AD3TBC2           HRTIM_ADC3R_AD3TBC2_Msk                  /*!< ADC Trigger 3 on Timer B compare 2 */
+#define HRTIM_ADC3R_AD3TBC3_Pos       (16U)
+#define HRTIM_ADC3R_AD3TBC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC3_Pos)       /*!< 0x00010000 */
+#define HRTIM_ADC3R_AD3TBC3           HRTIM_ADC3R_AD3TBC3_Msk                  /*!< ADC Trigger 3 on Timer B compare 3 */
+#define HRTIM_ADC3R_AD3TBC4_Pos       (17U)
+#define HRTIM_ADC3R_AD3TBC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC4_Pos)       /*!< 0x00020000 */
+#define HRTIM_ADC3R_AD3TBC4           HRTIM_ADC3R_AD3TBC4_Msk                  /*!< ADC Trigger 3 on Timer B compare 4 */
+#define HRTIM_ADC3R_AD3TBPER_Pos      (18U)
+#define HRTIM_ADC3R_AD3TBPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TBPER_Pos)      /*!< 0x00040000 */
+#define HRTIM_ADC3R_AD3TBPER          HRTIM_ADC3R_AD3TBPER_Msk                 /*!< ADC Trigger 3 on Timer B period */
+#define HRTIM_ADC3R_AD3TBRST_Pos      (19U)
+#define HRTIM_ADC3R_AD3TBRST_Msk      (0x1UL << HRTIM_ADC3R_AD3TBRST_Pos)      /*!< 0x00080000 */
+#define HRTIM_ADC3R_AD3TBRST          HRTIM_ADC3R_AD3TBRST_Msk                 /*!< ADC Trigger 3 on Timer B reset */
+#define HRTIM_ADC3R_AD3TCC2_Pos       (20U)
+#define HRTIM_ADC3R_AD3TCC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC2_Pos)       /*!< 0x00100000 */
+#define HRTIM_ADC3R_AD3TCC2           HRTIM_ADC3R_AD3TCC2_Msk                  /*!< ADC Trigger 3 on Timer C compare 2 */
+#define HRTIM_ADC3R_AD3TCC3_Pos       (21U)
+#define HRTIM_ADC3R_AD3TCC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC3_Pos)       /*!< 0x00200000 */
+#define HRTIM_ADC3R_AD3TCC3           HRTIM_ADC3R_AD3TCC3_Msk                  /*!< ADC Trigger 3 on Timer C compare 3 */
+#define HRTIM_ADC3R_AD3TCC4_Pos       (22U)
+#define HRTIM_ADC3R_AD3TCC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC4_Pos)       /*!< 0x00400000 */
+#define HRTIM_ADC3R_AD3TCC4           HRTIM_ADC3R_AD3TCC4_Msk                  /*!< ADC Trigger 3 on Timer C compare 4 */
+#define HRTIM_ADC3R_AD3TCPER_Pos      (23U)
+#define HRTIM_ADC3R_AD3TCPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TCPER_Pos)      /*!< 0x00800000 */
+#define HRTIM_ADC3R_AD3TCPER          HRTIM_ADC3R_AD3TCPER_Msk                 /*!< ADC Trigger 3 on Timer C period */
+#define HRTIM_ADC3R_AD3TDC2_Pos       (24U)
+#define HRTIM_ADC3R_AD3TDC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC2_Pos)       /*!< 0x01000000 */
+#define HRTIM_ADC3R_AD3TDC2           HRTIM_ADC3R_AD3TDC2_Msk                  /*!< ADC Trigger 3 on Timer D compare 2 */
+#define HRTIM_ADC3R_AD3TDC3_Pos       (25U)
+#define HRTIM_ADC3R_AD3TDC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC3_Pos)       /*!< 0x02000000 */
+#define HRTIM_ADC3R_AD3TDC3           HRTIM_ADC3R_AD3TDC3_Msk                  /*!< ADC Trigger 3 on Timer D compare 3 */
+#define HRTIM_ADC3R_AD3TDC4_Pos       (26U)
+#define HRTIM_ADC3R_AD3TDC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC4_Pos)       /*!< 0x04000000 */
+#define HRTIM_ADC3R_AD3TDC4           HRTIM_ADC3R_AD3TDC4_Msk                  /*!< ADC Trigger 3 on Timer D compare 4 */
+#define HRTIM_ADC3R_AD3TDPER_Pos      (27U)
+#define HRTIM_ADC3R_AD3TDPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TDPER_Pos)      /*!< 0x08000000 */
+#define HRTIM_ADC3R_AD3TDPER          HRTIM_ADC3R_AD3TDPER_Msk                 /*!< ADC Trigger 3 on Timer D period */
+#define HRTIM_ADC3R_AD3TEC2_Pos       (28U)
+#define HRTIM_ADC3R_AD3TEC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC2_Pos)       /*!< 0x10000000 */
+#define HRTIM_ADC3R_AD3TEC2           HRTIM_ADC3R_AD3TEC2_Msk                  /*!< ADC Trigger 3 on Timer E compare 2 */
+#define HRTIM_ADC3R_AD3TEC3_Pos       (29U)
+#define HRTIM_ADC3R_AD3TEC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC3_Pos)       /*!< 0x20000000 */
+#define HRTIM_ADC3R_AD3TEC3           HRTIM_ADC3R_AD3TEC3_Msk                  /*!< ADC Trigger 3 on Timer E compare 3 */
+#define HRTIM_ADC3R_AD3TEC4_Pos       (30U)
+#define HRTIM_ADC3R_AD3TEC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC4_Pos)       /*!< 0x40000000 */
+#define HRTIM_ADC3R_AD3TEC4           HRTIM_ADC3R_AD3TEC4_Msk                  /*!< ADC Trigger 3 on Timer E compare 4 */
+#define HRTIM_ADC3R_AD3TEPER_Pos      (31U)
+#define HRTIM_ADC3R_AD3TEPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TEPER_Pos)      /*!< 0x80000000 */
+#define HRTIM_ADC3R_AD3TEPER          HRTIM_ADC3R_AD3TEPER_Msk                 /*!< ADC Trigger 3 on Timer E period */
+
+/*******************  Bit definition for HRTIM_ADC4R register  ****************/
+#define HRTIM_ADC4R_AD4MC1_Pos        (0U)
+#define HRTIM_ADC4R_AD4MC1_Msk        (0x1UL << HRTIM_ADC4R_AD4MC1_Pos)        /*!< 0x00000001 */
+#define HRTIM_ADC4R_AD4MC1            HRTIM_ADC4R_AD4MC1_Msk                   /*!< ADC Trigger 4 on master compare 1 */
+#define HRTIM_ADC4R_AD4MC2_Pos        (1U)
+#define HRTIM_ADC4R_AD4MC2_Msk        (0x1UL << HRTIM_ADC4R_AD4MC2_Pos)        /*!< 0x00000002 */
+#define HRTIM_ADC4R_AD4MC2            HRTIM_ADC4R_AD4MC2_Msk                   /*!< ADC Trigger 4 on master compare 2 */
+#define HRTIM_ADC4R_AD4MC3_Pos        (2U)
+#define HRTIM_ADC4R_AD4MC3_Msk        (0x1UL << HRTIM_ADC4R_AD4MC3_Pos)        /*!< 0x00000004 */
+#define HRTIM_ADC4R_AD4MC3            HRTIM_ADC4R_AD4MC3_Msk                   /*!< ADC Trigger 4 on master compare 3 */
+#define HRTIM_ADC4R_AD4MC4_Pos        (3U)
+#define HRTIM_ADC4R_AD4MC4_Msk        (0x1UL << HRTIM_ADC4R_AD4MC4_Pos)        /*!< 0x00000008 */
+#define HRTIM_ADC4R_AD4MC4            HRTIM_ADC4R_AD4MC4_Msk                   /*!< ADC Trigger 4 on master compare 4 */
+#define HRTIM_ADC4R_AD4MPER_Pos       (4U)
+#define HRTIM_ADC4R_AD4MPER_Msk       (0x1UL << HRTIM_ADC4R_AD4MPER_Pos)       /*!< 0x00000010 */
+#define HRTIM_ADC4R_AD4MPER           HRTIM_ADC4R_AD4MPER_Msk                  /*!< ADC Trigger 4 on master period */
+#define HRTIM_ADC4R_AD4EEV6_Pos       (5U)
+#define HRTIM_ADC4R_AD4EEV6_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV6_Pos)       /*!< 0x00000020 */
+#define HRTIM_ADC4R_AD4EEV6           HRTIM_ADC4R_AD4EEV6_Msk                  /*!< ADC Trigger 4 on external event 6 */
+#define HRTIM_ADC4R_AD4EEV7_Pos       (6U)
+#define HRTIM_ADC4R_AD4EEV7_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV7_Pos)       /*!< 0x00000040 */
+#define HRTIM_ADC4R_AD4EEV7           HRTIM_ADC4R_AD4EEV7_Msk                  /*!< ADC Trigger 4 on external event 7 */
+#define HRTIM_ADC4R_AD4EEV8_Pos       (7U)
+#define HRTIM_ADC4R_AD4EEV8_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV8_Pos)       /*!< 0x00000080 */
+#define HRTIM_ADC4R_AD4EEV8           HRTIM_ADC4R_AD4EEV8_Msk                  /*!< ADC Trigger 4 on external event 8 */
+#define HRTIM_ADC4R_AD4EEV9_Pos       (8U)
+#define HRTIM_ADC4R_AD4EEV9_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV9_Pos)       /*!< 0x00000100 */
+#define HRTIM_ADC4R_AD4EEV9           HRTIM_ADC4R_AD4EEV9_Msk                  /*!< ADC Trigger 4 on external event 9 */
+#define HRTIM_ADC4R_AD4EEV10_Pos      (9U)
+#define HRTIM_ADC4R_AD4EEV10_Msk      (0x1UL << HRTIM_ADC4R_AD4EEV10_Pos)      /*!< 0x00000200 */
+#define HRTIM_ADC4R_AD4EEV10          HRTIM_ADC4R_AD4EEV10_Msk                 /*!< ADC Trigger 4 on external event 10 */
+#define HRTIM_ADC4R_AD4TAC2_Pos       (10U)
+#define HRTIM_ADC4R_AD4TAC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC2_Pos)       /*!< 0x00000400 */
+#define HRTIM_ADC4R_AD4TAC2           HRTIM_ADC4R_AD4TAC2_Msk                  /*!< ADC Trigger 4 on Timer A compare 2 */
+#define HRTIM_ADC4R_AD4TAC3_Pos       (11U)
+#define HRTIM_ADC4R_AD4TAC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC3_Pos)       /*!< 0x00000800 */
+#define HRTIM_ADC4R_AD4TAC3           HRTIM_ADC4R_AD4TAC3_Msk                  /*!< ADC Trigger 4 on Timer A compare 3 */
+#define HRTIM_ADC4R_AD4TAC4_Pos       (12U)
+#define HRTIM_ADC4R_AD4TAC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC4_Pos)       /*!< 0x00001000 */
+#define HRTIM_ADC4R_AD4TAC4           HRTIM_ADC4R_AD4TAC4_Msk                  /*!< ADC Trigger 4 on Timer A compare 4*/
+#define HRTIM_ADC4R_AD4TAPER_Pos      (13U)
+#define HRTIM_ADC4R_AD4TAPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TAPER_Pos)      /*!< 0x00002000 */
+#define HRTIM_ADC4R_AD4TAPER          HRTIM_ADC4R_AD4TAPER_Msk                 /*!< ADC Trigger 4 on Timer A period */
+#define HRTIM_ADC4R_AD4TBC2_Pos       (14U)
+#define HRTIM_ADC4R_AD4TBC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC2_Pos)       /*!< 0x00004000 */
+#define HRTIM_ADC4R_AD4TBC2           HRTIM_ADC4R_AD4TBC2_Msk                  /*!< ADC Trigger 4 on Timer B compare 2 */
+#define HRTIM_ADC4R_AD4TBC3_Pos       (15U)
+#define HRTIM_ADC4R_AD4TBC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC3_Pos)       /*!< 0x00008000 */
+#define HRTIM_ADC4R_AD4TBC3           HRTIM_ADC4R_AD4TBC3_Msk                  /*!< ADC Trigger 4 on Timer B compare 3 */
+#define HRTIM_ADC4R_AD4TBC4_Pos       (16U)
+#define HRTIM_ADC4R_AD4TBC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC4_Pos)       /*!< 0x00010000 */
+#define HRTIM_ADC4R_AD4TBC4           HRTIM_ADC4R_AD4TBC4_Msk                  /*!< ADC Trigger 4 on Timer B compare 4 */
+#define HRTIM_ADC4R_AD4TBPER_Pos      (17U)
+#define HRTIM_ADC4R_AD4TBPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TBPER_Pos)      /*!< 0x00020000 */
+#define HRTIM_ADC4R_AD4TBPER          HRTIM_ADC4R_AD4TBPER_Msk                 /*!< ADC Trigger 4 on Timer B period */
+#define HRTIM_ADC4R_AD4TCC2_Pos       (18U)
+#define HRTIM_ADC4R_AD4TCC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC2_Pos)       /*!< 0x00040000 */
+#define HRTIM_ADC4R_AD4TCC2           HRTIM_ADC4R_AD4TCC2_Msk                  /*!< ADC Trigger 4 on Timer C compare 2 */
+#define HRTIM_ADC4R_AD4TCC3_Pos       (19U)
+#define HRTIM_ADC4R_AD4TCC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC3_Pos)       /*!< 0x00080000 */
+#define HRTIM_ADC4R_AD4TCC3           HRTIM_ADC4R_AD4TCC3_Msk                  /*!< ADC Trigger 4 on Timer C compare 3 */
+#define HRTIM_ADC4R_AD4TCC4_Pos       (20U)
+#define HRTIM_ADC4R_AD4TCC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC4_Pos)       /*!< 0x00100000 */
+#define HRTIM_ADC4R_AD4TCC4           HRTIM_ADC4R_AD4TCC4_Msk                  /*!< ADC Trigger 4 on Timer C compare 4 */
+#define HRTIM_ADC4R_AD4TCPER_Pos      (21U)
+#define HRTIM_ADC4R_AD4TCPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TCPER_Pos)      /*!< 0x00200000 */
+#define HRTIM_ADC4R_AD4TCPER          HRTIM_ADC4R_AD4TCPER_Msk                 /*!< ADC Trigger 4 on Timer C period */
+#define HRTIM_ADC4R_AD4TCRST_Pos      (22U)
+#define HRTIM_ADC4R_AD4TCRST_Msk      (0x1UL << HRTIM_ADC4R_AD4TCRST_Pos)      /*!< 0x00400000 */
+#define HRTIM_ADC4R_AD4TCRST          HRTIM_ADC4R_AD4TCRST_Msk                 /*!< ADC Trigger 4 on Timer C reset */
+#define HRTIM_ADC4R_AD4TDC2_Pos       (23U)
+#define HRTIM_ADC4R_AD4TDC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC2_Pos)       /*!< 0x00800000 */
+#define HRTIM_ADC4R_AD4TDC2           HRTIM_ADC4R_AD4TDC2_Msk                  /*!< ADC Trigger 4 on Timer D compare 2 */
+#define HRTIM_ADC4R_AD4TDC3_Pos       (24U)
+#define HRTIM_ADC4R_AD4TDC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC3_Pos)       /*!< 0x01000000 */
+#define HRTIM_ADC4R_AD4TDC3           HRTIM_ADC4R_AD4TDC3_Msk                  /*!< ADC Trigger 4 on Timer D compare 3 */
+#define HRTIM_ADC4R_AD4TDC4_Pos       (25U)
+#define HRTIM_ADC4R_AD4TDC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC4_Pos)       /*!< 0x02000000 */
+#define HRTIM_ADC4R_AD4TDC4           HRTIM_ADC4R_AD4TDC4_Msk                  /*!< ADC Trigger 4 on Timer D compare 4*/
+#define HRTIM_ADC4R_AD4TDPER_Pos      (26U)
+#define HRTIM_ADC4R_AD4TDPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TDPER_Pos)      /*!< 0x04000000 */
+#define HRTIM_ADC4R_AD4TDPER          HRTIM_ADC4R_AD4TDPER_Msk                 /*!< ADC Trigger 4 on Timer D period */
+#define HRTIM_ADC4R_AD4TDRST_Pos      (27U)
+#define HRTIM_ADC4R_AD4TDRST_Msk      (0x1UL << HRTIM_ADC4R_AD4TDRST_Pos)      /*!< 0x08000000 */
+#define HRTIM_ADC4R_AD4TDRST          HRTIM_ADC4R_AD4TDRST_Msk                 /*!< ADC Trigger 4 on Timer D reset */
+#define HRTIM_ADC4R_AD4TEC2_Pos       (28U)
+#define HRTIM_ADC4R_AD4TEC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC2_Pos)       /*!< 0x10000000 */
+#define HRTIM_ADC4R_AD4TEC2           HRTIM_ADC4R_AD4TEC2_Msk                  /*!< ADC Trigger 4 on Timer E compare 2 */
+#define HRTIM_ADC4R_AD4TEC3_Pos       (29U)
+#define HRTIM_ADC4R_AD4TEC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC3_Pos)       /*!< 0x20000000 */
+#define HRTIM_ADC4R_AD4TEC3           HRTIM_ADC4R_AD4TEC3_Msk                  /*!< ADC Trigger 4 on Timer E compare 3 */
+#define HRTIM_ADC4R_AD4TEC4_Pos       (30U)
+#define HRTIM_ADC4R_AD4TEC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC4_Pos)       /*!< 0x40000000 */
+#define HRTIM_ADC4R_AD4TEC4           HRTIM_ADC4R_AD4TEC4_Msk                  /*!< ADC Trigger 4 on Timer E compare 4 */
+#define HRTIM_ADC4R_AD4TERST_Pos      (31U)
+#define HRTIM_ADC4R_AD4TERST_Msk      (0x1UL << HRTIM_ADC4R_AD4TERST_Pos)      /*!< 0x80000000 */
+#define HRTIM_ADC4R_AD4TERST          HRTIM_ADC4R_AD4TERST_Msk                 /*!< ADC Trigger 4 on Timer E reset */
+
+/*******************  Bit definition for HRTIM_FLTINR1 register  ***************/
+#define HRTIM_FLTINR1_FLT1E_Pos       (0U)
+#define HRTIM_FLTINR1_FLT1E_Msk       (0x1UL << HRTIM_FLTINR1_FLT1E_Pos)       /*!< 0x00000001 */
+#define HRTIM_FLTINR1_FLT1E           HRTIM_FLTINR1_FLT1E_Msk                  /*!< Fault 1 enable */
+#define HRTIM_FLTINR1_FLT1P_Pos       (1U)
+#define HRTIM_FLTINR1_FLT1P_Msk       (0x1UL << HRTIM_FLTINR1_FLT1P_Pos)       /*!< 0x00000002 */
+#define HRTIM_FLTINR1_FLT1P           HRTIM_FLTINR1_FLT1P_Msk                  /*!< Fault 1 polarity */
+#define HRTIM_FLTINR1_FLT1SRC_Pos     (2U)
+#define HRTIM_FLTINR1_FLT1SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT1SRC_Pos)     /*!< 0x00000004 */
+#define HRTIM_FLTINR1_FLT1SRC         HRTIM_FLTINR1_FLT1SRC_Msk                /*!< Fault 1 source */
+#define HRTIM_FLTINR1_FLT1F_Pos       (3U)
+#define HRTIM_FLTINR1_FLT1F_Msk       (0xFUL << HRTIM_FLTINR1_FLT1F_Pos)       /*!< 0x00000078 */
+#define HRTIM_FLTINR1_FLT1F           HRTIM_FLTINR1_FLT1F_Msk                  /*!< Fault 1 filter */
+#define HRTIM_FLTINR1_FLT1F_0         (0x1UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000008 */
+#define HRTIM_FLTINR1_FLT1F_1         (0x2UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000010 */
+#define HRTIM_FLTINR1_FLT1F_2         (0x4UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000020 */
+#define HRTIM_FLTINR1_FLT1F_3         (0x8UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000040 */
+#define HRTIM_FLTINR1_FLT1LCK_Pos     (7U)
+#define HRTIM_FLTINR1_FLT1LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT1LCK_Pos)     /*!< 0x00000080 */
+#define HRTIM_FLTINR1_FLT1LCK         HRTIM_FLTINR1_FLT1LCK_Msk                /*!< Fault 1 lock */
+
+#define HRTIM_FLTINR1_FLT2E_Pos       (8U)
+#define HRTIM_FLTINR1_FLT2E_Msk       (0x1UL << HRTIM_FLTINR1_FLT2E_Pos)       /*!< 0x00000100 */
+#define HRTIM_FLTINR1_FLT2E           HRTIM_FLTINR1_FLT2E_Msk                  /*!< Fault 2 enable */
+#define HRTIM_FLTINR1_FLT2P_Pos       (9U)
+#define HRTIM_FLTINR1_FLT2P_Msk       (0x1UL << HRTIM_FLTINR1_FLT2P_Pos)       /*!< 0x00000200 */
+#define HRTIM_FLTINR1_FLT2P           HRTIM_FLTINR1_FLT2P_Msk                  /*!< Fault 2 polarity */
+#define HRTIM_FLTINR1_FLT2SRC_Pos     (10U)
+#define HRTIM_FLTINR1_FLT2SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT2SRC_Pos)     /*!< 0x00000400 */
+#define HRTIM_FLTINR1_FLT2SRC         HRTIM_FLTINR1_FLT2SRC_Msk                /*!< Fault 2 source */
+#define HRTIM_FLTINR1_FLT2F_Pos       (11U)
+#define HRTIM_FLTINR1_FLT2F_Msk       (0xFUL << HRTIM_FLTINR1_FLT2F_Pos)       /*!< 0x00007800 */
+#define HRTIM_FLTINR1_FLT2F           HRTIM_FLTINR1_FLT2F_Msk                  /*!< Fault 2 filter */
+#define HRTIM_FLTINR1_FLT2F_0         (0x1UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00000800 */
+#define HRTIM_FLTINR1_FLT2F_1         (0x2UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00001000 */
+#define HRTIM_FLTINR1_FLT2F_2         (0x4UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00002000 */
+#define HRTIM_FLTINR1_FLT2F_3         (0x8UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00004000 */
+#define HRTIM_FLTINR1_FLT2LCK_Pos     (15U)
+#define HRTIM_FLTINR1_FLT2LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT2LCK_Pos)     /*!< 0x00008000 */
+#define HRTIM_FLTINR1_FLT2LCK         HRTIM_FLTINR1_FLT2LCK_Msk                /*!< Fault 2 lock */
+
+#define HRTIM_FLTINR1_FLT3E_Pos       (16U)
+#define HRTIM_FLTINR1_FLT3E_Msk       (0x1UL << HRTIM_FLTINR1_FLT3E_Pos)       /*!< 0x00010000 */
+#define HRTIM_FLTINR1_FLT3E           HRTIM_FLTINR1_FLT3E_Msk                  /*!< Fault 3 enable */
+#define HRTIM_FLTINR1_FLT3P_Pos       (17U)
+#define HRTIM_FLTINR1_FLT3P_Msk       (0x1UL << HRTIM_FLTINR1_FLT3P_Pos)       /*!< 0x00020000 */
+#define HRTIM_FLTINR1_FLT3P           HRTIM_FLTINR1_FLT3P_Msk                  /*!< Fault 3 polarity */
+#define HRTIM_FLTINR1_FLT3SRC_Pos     (18U)
+#define HRTIM_FLTINR1_FLT3SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT3SRC_Pos)     /*!< 0x00040000 */
+#define HRTIM_FLTINR1_FLT3SRC         HRTIM_FLTINR1_FLT3SRC_Msk                /*!< Fault 3 source */
+#define HRTIM_FLTINR1_FLT3F_Pos       (19U)
+#define HRTIM_FLTINR1_FLT3F_Msk       (0xFUL << HRTIM_FLTINR1_FLT3F_Pos)       /*!< 0x00780000 */
+#define HRTIM_FLTINR1_FLT3F           HRTIM_FLTINR1_FLT3F_Msk                  /*!< Fault 3 filter */
+#define HRTIM_FLTINR1_FLT3F_0         (0x1UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00080000 */
+#define HRTIM_FLTINR1_FLT3F_1         (0x2UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00100000 */
+#define HRTIM_FLTINR1_FLT3F_2         (0x4UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00200000 */
+#define HRTIM_FLTINR1_FLT3F_3         (0x8UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00400000 */
+#define HRTIM_FLTINR1_FLT3LCK_Pos     (23U)
+#define HRTIM_FLTINR1_FLT3LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT3LCK_Pos)     /*!< 0x00800000 */
+#define HRTIM_FLTINR1_FLT3LCK         HRTIM_FLTINR1_FLT3LCK_Msk                /*!< Fault 3 lock */
+
+#define HRTIM_FLTINR1_FLT4E_Pos       (24U)
+#define HRTIM_FLTINR1_FLT4E_Msk       (0x1UL << HRTIM_FLTINR1_FLT4E_Pos)       /*!< 0x01000000 */
+#define HRTIM_FLTINR1_FLT4E           HRTIM_FLTINR1_FLT4E_Msk                  /*!< Fault 4 enable */
+#define HRTIM_FLTINR1_FLT4P_Pos       (25U)
+#define HRTIM_FLTINR1_FLT4P_Msk       (0x1UL << HRTIM_FLTINR1_FLT4P_Pos)       /*!< 0x02000000 */
+#define HRTIM_FLTINR1_FLT4P           HRTIM_FLTINR1_FLT4P_Msk                  /*!< Fault 4 polarity */
+#define HRTIM_FLTINR1_FLT4SRC_Pos     (26U)
+#define HRTIM_FLTINR1_FLT4SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT4SRC_Pos)     /*!< 0x04000000 */
+#define HRTIM_FLTINR1_FLT4SRC         HRTIM_FLTINR1_FLT4SRC_Msk                /*!< Fault 4 source */
+#define HRTIM_FLTINR1_FLT4F_Pos       (27U)
+#define HRTIM_FLTINR1_FLT4F_Msk       (0xFUL << HRTIM_FLTINR1_FLT4F_Pos)       /*!< 0x78000000 */
+#define HRTIM_FLTINR1_FLT4F           HRTIM_FLTINR1_FLT4F_Msk                  /*!< Fault 4 filter */
+#define HRTIM_FLTINR1_FLT4F_0         (0x1UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x08000000 */
+#define HRTIM_FLTINR1_FLT4F_1         (0x2UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x10000000 */
+#define HRTIM_FLTINR1_FLT4F_2         (0x4UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x20000000 */
+#define HRTIM_FLTINR1_FLT4F_3         (0x8UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x40000000 */
+#define HRTIM_FLTINR1_FLT4LCK_Pos     (31U)
+#define HRTIM_FLTINR1_FLT4LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT4LCK_Pos)     /*!< 0x80000000 */
+#define HRTIM_FLTINR1_FLT4LCK         HRTIM_FLTINR1_FLT4LCK_Msk                /*!< Fault 4 lock */
+
+/*******************  Bit definition for HRTIM_FLTINR2 register  ***************/
+#define HRTIM_FLTINR2_FLT5E_Pos       (0U)
+#define HRTIM_FLTINR2_FLT5E_Msk       (0x1UL << HRTIM_FLTINR2_FLT5E_Pos)       /*!< 0x00000001 */
+#define HRTIM_FLTINR2_FLT5E           HRTIM_FLTINR2_FLT5E_Msk                  /*!< Fault 5 enable */
+#define HRTIM_FLTINR2_FLT5P_Pos       (1U)
+#define HRTIM_FLTINR2_FLT5P_Msk       (0x1UL << HRTIM_FLTINR2_FLT5P_Pos)       /*!< 0x00000002 */
+#define HRTIM_FLTINR2_FLT5P           HRTIM_FLTINR2_FLT5P_Msk                  /*!< Fault 5 polarity */
+#define HRTIM_FLTINR2_FLT5SRC_Pos     (2U)
+#define HRTIM_FLTINR2_FLT5SRC_Msk     (0x1UL << HRTIM_FLTINR2_FLT5SRC_Pos)     /*!< 0x00000004 */
+#define HRTIM_FLTINR2_FLT5SRC         HRTIM_FLTINR2_FLT5SRC_Msk                /*!< Fault 5 source */
+#define HRTIM_FLTINR2_FLT5F_Pos       (3U)
+#define HRTIM_FLTINR2_FLT5F_Msk       (0xFUL << HRTIM_FLTINR2_FLT5F_Pos)       /*!< 0x00000078 */
+#define HRTIM_FLTINR2_FLT5F           HRTIM_FLTINR2_FLT5F_Msk                  /*!< Fault 5 filter */
+#define HRTIM_FLTINR2_FLT5F_0         (0x1UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000008 */
+#define HRTIM_FLTINR2_FLT5F_1         (0x2UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000010 */
+#define HRTIM_FLTINR2_FLT5F_2         (0x4UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000020 */
+#define HRTIM_FLTINR2_FLT5F_3         (0x8UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000040 */
+#define HRTIM_FLTINR2_FLT5LCK_Pos     (7U)
+#define HRTIM_FLTINR2_FLT5LCK_Msk     (0x1UL << HRTIM_FLTINR2_FLT5LCK_Pos)     /*!< 0x00000080 */
+#define HRTIM_FLTINR2_FLT5LCK         HRTIM_FLTINR2_FLT5LCK_Msk                /*!< Fault 5 lock */
+#define HRTIM_FLTINR2_FLTSD_Pos       (24U)
+#define HRTIM_FLTINR2_FLTSD_Msk       (0x3UL << HRTIM_FLTINR2_FLTSD_Pos)       /*!< 0x03000000 */
+#define HRTIM_FLTINR2_FLTSD           HRTIM_FLTINR2_FLTSD_Msk                  /*!< Fault sampling clock division */
+#define HRTIM_FLTINR2_FLTSD_0         (0x1UL << HRTIM_FLTINR2_FLTSD_Pos)        /*!< 0x01000000 */
+#define HRTIM_FLTINR2_FLTSD_1         (0x2UL << HRTIM_FLTINR2_FLTSD_Pos)        /*!< 0x02000000 */
+
+/*******************  Bit definition for HRTIM_BDMUPR register  ***************/
+#define HRTIM_BDMUPR_MCR_Pos          (0U)
+#define HRTIM_BDMUPR_MCR_Msk          (0x1UL << HRTIM_BDMUPR_MCR_Pos)          /*!< 0x00000001 */
+#define HRTIM_BDMUPR_MCR              HRTIM_BDMUPR_MCR_Msk                     /*!< MCR register update enable */
+#define HRTIM_BDMUPR_MICR_Pos         (1U)
+#define HRTIM_BDMUPR_MICR_Msk         (0x1UL << HRTIM_BDMUPR_MICR_Pos)         /*!< 0x00000002 */
+#define HRTIM_BDMUPR_MICR             HRTIM_BDMUPR_MICR_Msk                    /*!< MICR register update enable */
+#define HRTIM_BDMUPR_MDIER_Pos        (2U)
+#define HRTIM_BDMUPR_MDIER_Msk        (0x1UL << HRTIM_BDMUPR_MDIER_Pos)        /*!< 0x00000004 */
+#define HRTIM_BDMUPR_MDIER            HRTIM_BDMUPR_MDIER_Msk                   /*!< MDIER register update enable */
+#define HRTIM_BDMUPR_MCNT_Pos         (3U)
+#define HRTIM_BDMUPR_MCNT_Msk         (0x1UL << HRTIM_BDMUPR_MCNT_Pos)         /*!< 0x00000008 */
+#define HRTIM_BDMUPR_MCNT             HRTIM_BDMUPR_MCNT_Msk                    /*!< MCNT register update enable */
+#define HRTIM_BDMUPR_MPER_Pos         (4U)
+#define HRTIM_BDMUPR_MPER_Msk         (0x1UL << HRTIM_BDMUPR_MPER_Pos)         /*!< 0x00000010 */
+#define HRTIM_BDMUPR_MPER             HRTIM_BDMUPR_MPER_Msk                    /*!< MPER register update enable */
+#define HRTIM_BDMUPR_MREP_Pos         (5U)
+#define HRTIM_BDMUPR_MREP_Msk         (0x1UL << HRTIM_BDMUPR_MREP_Pos)         /*!< 0x00000020 */
+#define HRTIM_BDMUPR_MREP             HRTIM_BDMUPR_MREP_Msk                    /*!< MREP register update enable */
+#define HRTIM_BDMUPR_MCMP1_Pos        (6U)
+#define HRTIM_BDMUPR_MCMP1_Msk        (0x1UL << HRTIM_BDMUPR_MCMP1_Pos)        /*!< 0x00000040 */
+#define HRTIM_BDMUPR_MCMP1            HRTIM_BDMUPR_MCMP1_Msk                   /*!< MCMP1 register update enable */
+#define HRTIM_BDMUPR_MCMP2_Pos        (7U)
+#define HRTIM_BDMUPR_MCMP2_Msk        (0x1UL << HRTIM_BDMUPR_MCMP2_Pos)        /*!< 0x00000080 */
+#define HRTIM_BDMUPR_MCMP2            HRTIM_BDMUPR_MCMP2_Msk                   /*!< MCMP2 register update enable */
+#define HRTIM_BDMUPR_MCMP3_Pos        (8U)
+#define HRTIM_BDMUPR_MCMP3_Msk        (0x1UL << HRTIM_BDMUPR_MCMP3_Pos)        /*!< 0x00000100 */
+#define HRTIM_BDMUPR_MCMP3            HRTIM_BDMUPR_MCMP3_Msk                   /*!< MCMP3 register update enable */
+#define HRTIM_BDMUPR_MCMP4_Pos        (9U)
+#define HRTIM_BDMUPR_MCMP4_Msk        (0x1UL << HRTIM_BDMUPR_MCMP4_Pos)        /*!< 0x00000200 */
+#define HRTIM_BDMUPR_MCMP4            HRTIM_BDMUPR_MCMP4_Msk                   /*!< MPCMP4 register update enable */
+
+/*******************  Bit definition for HRTIM_BDTUPR register  ***************/
+#define HRTIM_BDTUPR_TIMCR_Pos        (0U)
+#define HRTIM_BDTUPR_TIMCR_Msk        (0x1UL << HRTIM_BDTUPR_TIMCR_Pos)        /*!< 0x00000001 */
+#define HRTIM_BDTUPR_TIMCR            HRTIM_BDTUPR_TIMCR_Msk                   /*!<  TIMCR register update enable */
+#define HRTIM_BDTUPR_TIMICR_Pos       (1U)
+#define HRTIM_BDTUPR_TIMICR_Msk       (0x1UL << HRTIM_BDTUPR_TIMICR_Pos)       /*!< 0x00000002 */
+#define HRTIM_BDTUPR_TIMICR           HRTIM_BDTUPR_TIMICR_Msk                  /*!<  TIMICR register update enable */
+#define HRTIM_BDTUPR_TIMDIER_Pos      (2U)
+#define HRTIM_BDTUPR_TIMDIER_Msk      (0x1UL << HRTIM_BDTUPR_TIMDIER_Pos)      /*!< 0x00000004 */
+#define HRTIM_BDTUPR_TIMDIER          HRTIM_BDTUPR_TIMDIER_Msk                 /*!<  TIMDIER register update enable */
+#define HRTIM_BDTUPR_TIMCNT_Pos       (3U)
+#define HRTIM_BDTUPR_TIMCNT_Msk       (0x1UL << HRTIM_BDTUPR_TIMCNT_Pos)       /*!< 0x00000008 */
+#define HRTIM_BDTUPR_TIMCNT           HRTIM_BDTUPR_TIMCNT_Msk                  /*!<  TIMCNT register update enable */
+#define HRTIM_BDTUPR_TIMPER_Pos       (4U)
+#define HRTIM_BDTUPR_TIMPER_Msk       (0x1UL << HRTIM_BDTUPR_TIMPER_Pos)       /*!< 0x00000010 */
+#define HRTIM_BDTUPR_TIMPER           HRTIM_BDTUPR_TIMPER_Msk                  /*!<  TIMPER register update enable */
+#define HRTIM_BDTUPR_TIMREP_Pos       (5U)
+#define HRTIM_BDTUPR_TIMREP_Msk       (0x1UL << HRTIM_BDTUPR_TIMREP_Pos)       /*!< 0x00000020 */
+#define HRTIM_BDTUPR_TIMREP           HRTIM_BDTUPR_TIMREP_Msk                  /*!<  TIMREP register update enable */
+#define HRTIM_BDTUPR_TIMCMP1_Pos      (6U)
+#define HRTIM_BDTUPR_TIMCMP1_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP1_Pos)      /*!< 0x00000040 */
+#define HRTIM_BDTUPR_TIMCMP1          HRTIM_BDTUPR_TIMCMP1_Msk                 /*!<  TIMCMP1 register update enable */
+#define HRTIM_BDTUPR_TIMCMP2_Pos      (7U)
+#define HRTIM_BDTUPR_TIMCMP2_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP2_Pos)      /*!< 0x00000080 */
+#define HRTIM_BDTUPR_TIMCMP2          HRTIM_BDTUPR_TIMCMP2_Msk                 /*!<  TIMCMP2 register update enable */
+#define HRTIM_BDTUPR_TIMCMP3_Pos      (8U)
+#define HRTIM_BDTUPR_TIMCMP3_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP3_Pos)      /*!< 0x00000100 */
+#define HRTIM_BDTUPR_TIMCMP3          HRTIM_BDTUPR_TIMCMP3_Msk                 /*!<  TIMCMP3 register update enable */
+#define HRTIM_BDTUPR_TIMCMP4_Pos      (9U)
+#define HRTIM_BDTUPR_TIMCMP4_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP4_Pos)      /*!< 0x00000200 */
+#define HRTIM_BDTUPR_TIMCMP4          HRTIM_BDTUPR_TIMCMP4_Msk                 /*!<  TIMCMP4 register update enable */
+#define HRTIM_BDTUPR_TIMDTR_Pos       (10U)
+#define HRTIM_BDTUPR_TIMDTR_Msk       (0x1UL << HRTIM_BDTUPR_TIMDTR_Pos)       /*!< 0x00000400 */
+#define HRTIM_BDTUPR_TIMDTR           HRTIM_BDTUPR_TIMDTR_Msk                  /*!<  TIMDTR register update enable */
+#define HRTIM_BDTUPR_TIMSET1R_Pos     (11U)
+#define HRTIM_BDTUPR_TIMSET1R_Msk     (0x1UL << HRTIM_BDTUPR_TIMSET1R_Pos)     /*!< 0x00000800 */
+#define HRTIM_BDTUPR_TIMSET1R         HRTIM_BDTUPR_TIMSET1R_Msk                /*!<  TIMSET1R register update enable */
+#define HRTIM_BDTUPR_TIMRST1R_Pos     (12U)
+#define HRTIM_BDTUPR_TIMRST1R_Msk     (0x1UL << HRTIM_BDTUPR_TIMRST1R_Pos)     /*!< 0x00001000 */
+#define HRTIM_BDTUPR_TIMRST1R         HRTIM_BDTUPR_TIMRST1R_Msk                /*!<  TIMRST1R register update enable */
+#define HRTIM_BDTUPR_TIMSET2R_Pos     (13U)
+#define HRTIM_BDTUPR_TIMSET2R_Msk     (0x1UL << HRTIM_BDTUPR_TIMSET2R_Pos)     /*!< 0x00002000 */
+#define HRTIM_BDTUPR_TIMSET2R         HRTIM_BDTUPR_TIMSET2R_Msk                /*!<  TIMSET2R register update enable */
+#define HRTIM_BDTUPR_TIMRST2R_Pos     (14U)
+#define HRTIM_BDTUPR_TIMRST2R_Msk     (0x1UL << HRTIM_BDTUPR_TIMRST2R_Pos)     /*!< 0x00004000 */
+#define HRTIM_BDTUPR_TIMRST2R         HRTIM_BDTUPR_TIMRST2R_Msk                /*!<  TIMRST2R register update enable */
+#define HRTIM_BDTUPR_TIMEEFR1_Pos     (15U)
+#define HRTIM_BDTUPR_TIMEEFR1_Msk     (0x1UL << HRTIM_BDTUPR_TIMEEFR1_Pos)     /*!< 0x00008000 */
+#define HRTIM_BDTUPR_TIMEEFR1         HRTIM_BDTUPR_TIMEEFR1_Msk                /*!<  TIMEEFR1 register update enable */
+#define HRTIM_BDTUPR_TIMEEFR2_Pos     (16U)
+#define HRTIM_BDTUPR_TIMEEFR2_Msk     (0x1UL << HRTIM_BDTUPR_TIMEEFR2_Pos)     /*!< 0x00010000 */
+#define HRTIM_BDTUPR_TIMEEFR2         HRTIM_BDTUPR_TIMEEFR2_Msk                /*!<  TIMEEFR2 register update enable */
+#define HRTIM_BDTUPR_TIMRSTR_Pos      (17U)
+#define HRTIM_BDTUPR_TIMRSTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMRSTR_Pos)      /*!< 0x00020000 */
+#define HRTIM_BDTUPR_TIMRSTR          HRTIM_BDTUPR_TIMRSTR_Msk                 /*!<  TIMRSTR register update enable */
+#define HRTIM_BDTUPR_TIMCHPR_Pos      (18U)
+#define HRTIM_BDTUPR_TIMCHPR_Msk      (0x1UL << HRTIM_BDTUPR_TIMCHPR_Pos)      /*!< 0x00040000 */
+#define HRTIM_BDTUPR_TIMCHPR          HRTIM_BDTUPR_TIMCHPR_Msk                 /*!<  TIMCHPR register update enable */
+#define HRTIM_BDTUPR_TIMOUTR_Pos      (19U)
+#define HRTIM_BDTUPR_TIMOUTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMOUTR_Pos)      /*!< 0x00080000 */
+#define HRTIM_BDTUPR_TIMOUTR          HRTIM_BDTUPR_TIMOUTR_Msk                 /*!<  TIMOUTR register update enable */
+#define HRTIM_BDTUPR_TIMFLTR_Pos      (20U)
+#define HRTIM_BDTUPR_TIMFLTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMFLTR_Pos)      /*!< 0x00100000 */
+#define HRTIM_BDTUPR_TIMFLTR          HRTIM_BDTUPR_TIMFLTR_Msk                 /*!<  TIMFLTR register update enable */
+
+/*******************  Bit definition for HRTIM_BDMADR register  ***************/
+#define HRTIM_BDMADR_BDMADR_Pos       (0U)
+#define HRTIM_BDMADR_BDMADR_Msk       (0xFFFFFFFFUL << HRTIM_BDMADR_BDMADR_Pos) /*!< 0xFFFFFFFF */
+#define HRTIM_BDMADR_BDMADR           HRTIM_BDMADR_BDMADR_Msk                  /*!<  Burst DMA Data register */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             RAM ECC monitoring                             */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for RAMECC_IER register  ******************/
+#define RAMECC_IER_GECCDEBWIE_Pos         (3U)
+#define RAMECC_IER_GECCDEBWIE_Msk         (0x1UL << RAMECC_IER_GECCDEBWIE_Pos)  /*!< 0x00000008 */
+#define RAMECC_IER_GECCDEBWIE             RAMECC_IER_GECCDEBWIE_Msk             /*!< Global ECC double error on byte write (BW) interrupt enable */
+#define RAMECC_IER_GECCDEIE_Pos           (2U)
+#define RAMECC_IER_GECCDEIE_Msk           (0x1UL << RAMECC_IER_GECCDEIE_Pos)    /*!< 0x00000004 */
+#define RAMECC_IER_GECCDEIE               RAMECC_IER_GECCDEIE_Msk               /*!< Global ECC double error interrupt enable */
+#define RAMECC_IER_GECCSEIE_Pos           (1U)
+#define RAMECC_IER_GECCSEIE_Msk           (0x1UL << RAMECC_IER_GECCSEIE_Pos)    /*!< 0x00000002 */
+#define RAMECC_IER_GECCSEIE               RAMECC_IER_GECCSEIE_Msk               /*!< Global ECC single error interrupt enable */
+#define RAMECC_IER_GIE_Pos                (0U)
+#define RAMECC_IER_GIE_Msk                (0x1UL << RAMECC_IER_GIE_Pos)         /*!< 0x00000001 */
+#define RAMECC_IER_GIE                    RAMECC_IER_GIE_Msk                    /*!< Global interrupt enable */
+
+/*******************  Bit definition for RAMECC_CR register  ******************/
+#define RAMECC_CR_ECCELEN_Pos             (5U)
+#define RAMECC_CR_ECCELEN_Msk             (0x1UL << RAMECC_CR_ECCELEN_Pos)      /*!< 0x00000020 */
+#define RAMECC_CR_ECCELEN                 RAMECC_CR_ECCELEN_Msk                 /*!< ECC error latching enable */
+#define RAMECC_CR_ECCDEBWIE_Pos           (4U)
+#define RAMECC_CR_ECCDEBWIE_Msk           (0x1UL << RAMECC_CR_ECCDEBWIE_Pos)    /*!< 0x00000010 */
+#define RAMECC_CR_ECCDEBWIE               RAMECC_CR_ECCDEBWIE_Msk               /*!< ECC double error on byte write (BW) interrupt enable */
+#define RAMECC_CR_ECCDEIE_Pos             (3U)
+#define RAMECC_CR_ECCDEIE_Msk             (0x1UL << RAMECC_CR_ECCDEIE_Pos)      /*!< 0x00000008 */
+#define RAMECC_CR_ECCDEIE                 RAMECC_CR_ECCDEIE_Msk                 /*!< ECC double error interrupt enable */
+#define RAMECC_CR_ECCSEIE_Pos             (2U)
+#define RAMECC_CR_ECCSEIE_Msk             (0x1UL << RAMECC_CR_ECCSEIE_Pos)      /*!< 0x00000004 */
+#define RAMECC_CR_ECCSEIE                 RAMECC_CR_ECCSEIE_Msk                 /*!< ECC single error interrupt enable */
+
+/*******************  Bit definition for RAMECC_SR register  ******************/
+#define RAMECC_SR_DEBWDF_Pos             (2U)
+#define RAMECC_SR_DEBWDF_Msk             (0x1UL << RAMECC_SR_DEBWDF_Pos)        /*!< 0x00000004 */
+#define RAMECC_SR_DEBWDF                 RAMECC_SR_DEBWDF_Msk                   /*!< ECC double error on byte write (BW) detected flag */
+#define RAMECC_SR_DEDF_Pos               (1U)
+#define RAMECC_SR_DEDF_Msk               (0x1UL << RAMECC_SR_DEDF_Pos)          /*!< 0x00000002 */
+#define RAMECC_SR_DEDF                   RAMECC_SR_DEDF_Msk                     /*!< ECC double error detected flag */
+#define RAMECC_SR_SEDCF_Pos              (0U)
+#define RAMECC_SR_SEDCF_Msk              (0x1UL << RAMECC_SR_SEDCF_Pos)         /*!< 0x00000001 */
+#define RAMECC_SR_SEDCF                  RAMECC_SR_SEDCF_Msk                    /*!< ECC single error detected and corrected flag */
+
+/******************  Bit definition for RAMECC_FAR register  ******************/
+#define RAMECC_FAR_FADD_Pos              (0U)
+#define RAMECC_FAR_FADD_Msk              (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos)  /*!< 0xFFFFFFFF */
+#define RAMECC_FAR_FADD                  RAMECC_FAR_FADD_Msk                    /*!< ECC error failing address */
+
+/******************  Bit definition for RAMECC_FDRL register  *****************/
+#define RAMECC_FAR_FDATAL_Pos            (0U)
+#define RAMECC_FAR_FDATAL_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAL_Pos)/*!< 0xFFFFFFFF */
+#define RAMECC_FAR_FDATAL                RAMECC_FAR_FDATAL_Msk                  /*!< ECC error failing address */
+
+/******************  Bit definition for RAMECC_FDRH register  *****************/
+#define RAMECC_FAR_FDATAH_Pos            (0U)
+#define RAMECC_FAR_FDATAH_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAH_Pos)/*!< 0xFFFFFFFF */
+#define RAMECC_FAR_FDATAH                RAMECC_FAR_FDATAH_Msk                  /* Failing data high (64-bit memory) */
+
+/*****************  Bit definition for RAMECC_FECR register  ******************/
+#define RAMECC_FECR_FEC_Pos              (0U)
+#define RAMECC_FECR_FEC_Msk              (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos)  /*!< 0xFFFFFFFF */
+#define RAMECC_FECR_FEC                  RAMECC_FECR_FEC_Msk                    /*!< Failing error code */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                MDIOS                                        */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for MDIOS_CR register  *******************/
+#define MDIOS_CR_EN_Pos                (0U)
+#define MDIOS_CR_EN_Msk                (0x1UL << MDIOS_CR_EN_Pos)              /*!< 0x00000001 */
+#define MDIOS_CR_EN                    MDIOS_CR_EN_Msk                         /*!<  MDIOS slave peripheral enable */
+#define MDIOS_CR_WRIE_Pos              (1U)
+#define MDIOS_CR_WRIE_Msk              (0x1UL << MDIOS_CR_WRIE_Pos)            /*!< 0x00000002 */
+#define MDIOS_CR_WRIE                  MDIOS_CR_WRIE_Msk                       /*!<  MDIOS slave register write interrupt enable. */
+#define MDIOS_CR_RDIE_Pos              (2U)
+#define MDIOS_CR_RDIE_Msk              (0x1UL << MDIOS_CR_RDIE_Pos)            /*!< 0x00000004 */
+#define MDIOS_CR_RDIE                  MDIOS_CR_RDIE_Msk                       /*!<  MDIOS slave register read interrupt enable. */
+#define MDIOS_CR_EIE_Pos               (3U)
+#define MDIOS_CR_EIE_Msk               (0x1UL << MDIOS_CR_EIE_Pos)             /*!< 0x00000008 */
+#define MDIOS_CR_EIE                   MDIOS_CR_EIE_Msk                        /*!<  MDIOS slave register error interrupt enable. */
+#define MDIOS_CR_DPC_Pos               (7U)
+#define MDIOS_CR_DPC_Msk               (0x1UL << MDIOS_CR_DPC_Pos)             /*!< 0x00000080 */
+#define MDIOS_CR_DPC                   MDIOS_CR_DPC_Msk                        /*!<  MDIOS slave disable preamble check. */
+#define MDIOS_CR_PORT_ADDRESS_Pos      (8U)
+#define MDIOS_CR_PORT_ADDRESS_Msk      (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos)   /*!< 0x00001F00 */
+#define MDIOS_CR_PORT_ADDRESS          MDIOS_CR_PORT_ADDRESS_Msk               /*!<  MDIOS slave port address mask. */
+#define MDIOS_CR_PORT_ADDRESS_0        (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000100 */
+#define MDIOS_CR_PORT_ADDRESS_1        (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000200 */
+#define MDIOS_CR_PORT_ADDRESS_2        (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000400 */
+#define MDIOS_CR_PORT_ADDRESS_3        (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000800 */
+#define MDIOS_CR_PORT_ADDRESS_4        (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00001000 */
+
+/********************  Bit definition for MDIOS_SR register  *******************/
+#define MDIOS_SR_PERF_Pos              (0U)
+#define MDIOS_SR_PERF_Msk              (0x1UL << MDIOS_SR_PERF_Pos)            /*!< 0x00000001 */
+#define MDIOS_SR_PERF                  MDIOS_SR_PERF_Msk                       /*!<  MDIOS slave turnaround error flag*/
+#define MDIOS_SR_SERF_Pos              (1U)
+#define MDIOS_SR_SERF_Msk              (0x1UL << MDIOS_SR_SERF_Pos)            /*!< 0x00000002 */
+#define MDIOS_SR_SERF                  MDIOS_SR_SERF_Msk                       /*!<  MDIOS slave start error flag */
+#define MDIOS_SR_TERF_Pos              (2U)
+#define MDIOS_SR_TERF_Msk              (0x1UL << MDIOS_SR_TERF_Pos)            /*!< 0x00000004 */
+#define MDIOS_SR_TERF                  MDIOS_SR_TERF_Msk                       /*!<  MDIOS slave preamble error flag */
+
+/********************  Bit definition for MDIOS_CLRFR register  *******************/
+#define MDIOS_SR_CPERF_Pos             (0U)
+#define MDIOS_SR_CPERF_Msk             (0x1UL << MDIOS_SR_CPERF_Pos)           /*!< 0x00000001 */
+#define MDIOS_SR_CPERF                 MDIOS_SR_CPERF_Msk                      /*!<  MDIOS slave Clear the turnaround error flag */
+#define MDIOS_SR_CSERF_Pos             (1U)
+#define MDIOS_SR_CSERF_Msk             (0x1UL << MDIOS_SR_CSERF_Pos)           /*!< 0x00000002 */
+#define MDIOS_SR_CSERF                 MDIOS_SR_CSERF_Msk                      /*!<  MDIOS slave Clear the start error flag */
+#define MDIOS_SR_CTERF_Pos             (2U)
+#define MDIOS_SR_CTERF_Msk             (0x1UL << MDIOS_SR_CTERF_Pos)           /*!< 0x00000004 */
+#define MDIOS_SR_CTERF                 MDIOS_SR_CTERF_Msk                      /*!<  MDIOS slave Clear the preamble error flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                       USB_OTG                              */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/
+#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)
+#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)
+#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
+#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */
+#define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)
+#define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */
+#define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)
+#define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
+#define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
+#define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)
+#define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)
+#define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
+#define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)
+#define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)
+#define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */
+#define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)
+#define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)
+#define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)
+#define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)
+#define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
+#define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_EHEN_Pos                 (12U)
+#define USB_OTG_GOTGCTL_EHEN_Msk                 (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
+#define USB_OTG_GOTGCTL_EHEN                     USB_OTG_GOTGCTL_EHEN_Msk      /*!< Embedded host enable */
+#define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)
+#define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
+#define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)
+#define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)
+#define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */
+#define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)
+#define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!< B-session valid */
+#define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)
+#define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
+#define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */
+
+/********************  Bit definition forUSB_OTG_HCFG register  ********************/
+
+#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)
+#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
+#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */
+#define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCFG_FSLSS_Pos                   (2U)
+#define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */
+
+/********************  Bit definition forUSB_OTG_DCFG register  ********************/
+
+#define USB_OTG_DCFG_DSPD_Pos                    (0U)
+#define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
+#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)
+#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD_Pos                     (4U)
+#define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */
+#define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
+
+#define USB_OTG_DCFG_PFIVL_Pos                   (11U)
+#define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
+
+#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)
+#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
+#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
+
+/********************  Bit definition forUSB_OTG_PCGCR register  ********************/
+#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)
+#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)
+#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)
+#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */
+
+/********************  Bit definition forUSB_OTG_GOTGINT register  ********************/
+#define USB_OTG_GOTGINT_SEDET_Pos                (2U)
+#define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */
+#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)
+#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */
+#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)
+#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)
+#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */
+#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)
+#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */
+#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)
+#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */
+
+/********************  Bit definition forUSB_OTG_DCTL register  ********************/
+#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)
+#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS_Pos                    (1U)
+#define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */
+#define USB_OTG_DCTL_GINSTS_Pos                  (2U)
+#define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */
+#define USB_OTG_DCTL_GONSTS_Pos                  (3U)
+#define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
+#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */
+
+#define USB_OTG_DCTL_TCTL_Pos                    (4U)
+#define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
+#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCTL_SGINAK_Pos                  (7U)
+#define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */
+#define USB_OTG_DCTL_CGINAK_Pos                  (8U)
+#define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */
+#define USB_OTG_DCTL_SGONAK_Pos                  (9U)
+#define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */
+#define USB_OTG_DCTL_CGONAK_Pos                  (10U)
+#define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */
+#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)
+#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
+
+/********************  Bit definition forUSB_OTG_HFIR register  ********************/
+#define USB_OTG_HFIR_FRIVL_Pos                   (0U)
+#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */
+
+/********************  Bit definition forUSB_OTG_HFNUM register  ********************/
+#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)
+#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */
+#define USB_OTG_HFNUM_FTREM_Pos                  (16U)
+#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */
+
+/********************  Bit definition forUSB_OTG_DSTS register  ********************/
+#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)
+#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */
+
+#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)
+#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
+#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
+#define USB_OTG_DSTS_EERR_Pos                    (3U)
+#define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
+#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */
+#define USB_OTG_DSTS_FNSOF_Pos                   (8U)
+#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
+#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */
+
+/********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/
+#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)
+#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
+#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */
+
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)
+#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
+#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
+#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
+#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
+#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
+#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)
+#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)
+#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)
+#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
+#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */
+
+/********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)
+#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
+#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
+#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
+#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
+#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)
+#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
+#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)
+#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
+#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)
+#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
+#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */
+
+#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)
+#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
+#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
+#define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
+#define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
+#define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)
+#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)
+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
+#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */
+#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)
+#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
+#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */
+#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)
+#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
+#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */
+#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)
+#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
+#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)
+#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
+#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */
+#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)
+#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
+#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)
+#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
+#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */
+#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)
+#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
+#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */
+#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)
+#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
+#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */
+#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)
+#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */
+
+/********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
+#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)
+#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
+#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */
+#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)
+#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
+#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */
+#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)
+#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
+#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)
+#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
+#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)
+#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
+#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */
+
+#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)
+#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
+#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
+#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
+#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)
+#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
+#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)
+#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
+#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */
+
+/********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/
+#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)
+#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */
+#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)
+#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */
+#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)
+#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
+#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)
+#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */
+#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)
+#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */
+#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)
+#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */
+#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)
+#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */
+
+/********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)
+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */
+
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)
+#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)
+#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
+
+/********************  Bit definition forUSB_OTG_HAINT register  ********************/
+#define USB_OTG_HAINT_HAINT_Pos                  (0U)
+#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */
+
+/********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/
+#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)
+#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)
+#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */
+#define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)
+#define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
+#define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk      /*!< OUT transaction AHB Error interrupt mask               */
+#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)
+#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */
+#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)
+#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)
+#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)
+#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */
+#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)
+#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */
+#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)
+#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */
+#define USB_OTG_DOEPMSK_BERRM_Pos                (12U)
+#define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask               */
+#define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)
+#define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask               */
+#define USB_OTG_DOEPMSK_NYETM_Pos                (14U)
+#define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk      /*!< NYET interrupt mask                */
+
+/********************  Bit definition forUSB_OTG_GINTSTS register  ********************/
+#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)
+#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
+#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */
+#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)
+#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */
+#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)
+#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */
+#define USB_OTG_GINTSTS_SOF_Pos                  (3U)
+#define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */
+#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)
+#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */
+#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)
+#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */
+#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)
+#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */
+#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)
+#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */
+#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)
+#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */
+#define USB_OTG_GINTSTS_USBRST_Pos               (12U)
+#define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */
+#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)
+#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */
+#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)
+#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */
+#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)
+#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */
+#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)
+#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */
+#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)
+#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */
+#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)
+#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)
+#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */
+#define USB_OTG_GINTSTS_RSTDET_Pos               (23U)
+#define USB_OTG_GINTSTS_RSTDET_Msk               (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
+#define USB_OTG_GINTSTS_RSTDET                   USB_OTG_GINTSTS_RSTDET_Msk    /*!< Reset detected interrupt                       */
+#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)
+#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */
+#define USB_OTG_GINTSTS_HCINT_Pos                (25U)
+#define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */
+#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)
+#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */
+#define USB_OTG_GINTSTS_LPMINT_Pos               (27U)
+#define USB_OTG_GINTSTS_LPMINT_Msk               (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt                                  */
+#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)
+#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */
+#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)
+#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */
+#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)
+#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)
+#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */
+
+/********************  Bit definition forUSB_OTG_GINTMSK register  ********************/
+#define USB_OTG_GINTMSK_MMISM_Pos                (1U)
+#define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */
+#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)
+#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */
+#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)
+#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */
+#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)
+#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */
+#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)
+#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)
+#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)
+#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */
+#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)
+#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */
+#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)
+#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */
+#define USB_OTG_GINTMSK_USBRST_Pos               (12U)
+#define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)
+#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */
+#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)
+#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */
+#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)
+#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */
+#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)
+#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
+#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */
+#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)
+#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */
+#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)
+#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)
+#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */
+#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)
+#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */
+#define USB_OTG_GINTMSK_RSTDEM_Pos               (23U)
+#define USB_OTG_GINTMSK_RSTDEM_Msk               (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */
+#define USB_OTG_GINTMSK_RSTDEM                   USB_OTG_GINTMSK_RSTDEM_Msk    /*!< Reset detected interrupt mask                      */
+#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)
+#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */
+#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)
+#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */
+#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)
+#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */
+#define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)
+#define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask                                  */
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)
+#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */
+#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)
+#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */
+#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)
+#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)
+#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */
+
+/********************  Bit definition forUSB_OTG_DAINT register  ********************/
+#define USB_OTG_DAINT_IEPINT_Pos                 (0U)
+#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */
+#define USB_OTG_DAINT_OEPINT_Pos                 (16U)
+#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */
+
+/********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/
+#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)
+#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */
+
+/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
+#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)
+#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */
+#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)
+#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)
+#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)
+#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/
+#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)
+#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)
+#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition for OTG register  ********************/
+
+#define USB_OTG_CHNUM_Pos                        (0U)
+#define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)  /*!< 0x0000000F */
+#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */
+#define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos                         (4U)
+#define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */
+
+#define USB_OTG_DPID_Pos                         (15U)
+#define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)   /*!< 0x00018000 */
+#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */
+#define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */
+#define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */
+
+#define USB_OTG_PKTSTS_Pos                       (17U)
+#define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */
+
+#define USB_OTG_EPNUM_Pos                        (0U)
+#define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)  /*!< 0x0000000F */
+#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */
+
+#define USB_OTG_FRMNUM_Pos                       (21U)
+#define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */
+
+/********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/
+#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)
+#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */
+
+/********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)
+#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */
+
+/********************  Bit definition for OTG register  ********************/
+#define USB_OTG_NPTXFSA_Pos                      (0U)
+#define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD_Pos                       (16U)
+#define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */
+#define USB_OTG_TX0FSA_Pos                       (0U)
+#define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */
+#define USB_OTG_TX0FD_Pos                        (16U)
+#define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */
+
+/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)
+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
+#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
+
+/********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
+#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
+#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)
+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
+#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)
+#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
+#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)
+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
+#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)
+#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
+#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */
+
+/********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/********************  Bit definition forUSB_OTG_DEACHINT register  ********************/
+#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)
+#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */
+#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)
+#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */
+
+/********************  Bit definition forUSB_OTG_GCCFG register  ********************/
+#define USB_OTG_GCCFG_DCDET_Pos                  (0U)
+#define USB_OTG_GCCFG_DCDET_Msk                  (0x1UL << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */
+#define USB_OTG_GCCFG_DCDET                      USB_OTG_GCCFG_DCDET_Msk       /*!< Data contact detection (DCD) status */
+#define USB_OTG_GCCFG_PDET_Pos                   (1U)
+#define USB_OTG_GCCFG_PDET_Msk                   (0x1UL << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_GCCFG_PDET                       USB_OTG_GCCFG_PDET_Msk        /*!< Primary detection (PD) status */
+#define USB_OTG_GCCFG_SDET_Pos                   (2U)
+#define USB_OTG_GCCFG_SDET_Msk                   (0x1UL << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GCCFG_SDET                       USB_OTG_GCCFG_SDET_Msk        /*!< Secondary detection (SD) status */
+#define USB_OTG_GCCFG_PS2DET_Pos                 (3U)
+#define USB_OTG_GCCFG_PS2DET_Msk                 (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */
+#define USB_OTG_GCCFG_PS2DET                     USB_OTG_GCCFG_PS2DET_Msk      /*!< DM pull-up detection status */
+#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)
+#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
+#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */
+#define USB_OTG_GCCFG_BCDEN_Pos                  (17U)
+#define USB_OTG_GCCFG_BCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_GCCFG_BCDEN                      USB_OTG_GCCFG_BCDEN_Msk       /*!< Battery charging detector (BCD) enable */
+#define USB_OTG_GCCFG_DCDEN_Pos                  (18U)
+#define USB_OTG_GCCFG_DCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_GCCFG_DCDEN                      USB_OTG_GCCFG_DCDEN_Msk       /*!< Data contact detection (DCD) mode enable*/
+#define USB_OTG_GCCFG_PDEN_Pos                   (19U)
+#define USB_OTG_GCCFG_PDEN_Msk                   (0x1UL << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_GCCFG_PDEN                       USB_OTG_GCCFG_PDEN_Msk        /*!< Primary detection (PD) mode enable*/
+#define USB_OTG_GCCFG_SDEN_Pos                   (20U)
+#define USB_OTG_GCCFG_SDEN_Msk                   (0x1UL << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_GCCFG_SDEN                       USB_OTG_GCCFG_SDEN_Msk        /*!< Secondary detection (SD) mode enable */
+#define USB_OTG_GCCFG_VBDEN_Pos                  (21U)
+#define USB_OTG_GCCFG_VBDEN_Msk                  (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk       /*!< Secondary detection (SD) mode enable */
+
+/********************  Bit definition forUSB_OTG_GPWRDN) register  ********************/
+#define USB_OTG_GPWRDN_ADPMEN_Pos                (0U)
+#define USB_OTG_GPWRDN_ADPMEN_Msk                (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */
+#define USB_OTG_GPWRDN_ADPMEN                    USB_OTG_GPWRDN_ADPMEN_Msk     /*!< ADP module enable */
+#define USB_OTG_GPWRDN_ADPIF_Pos                 (23U)
+#define USB_OTG_GPWRDN_ADPIF_Msk                 (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */
+#define USB_OTG_GPWRDN_ADPIF                     USB_OTG_GPWRDN_ADPIF_Msk      /*!< ADP Interrupt flag */
+
+/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
+
+/********************  Bit definition forUSB_OTG_CID register  ********************/
+#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)
+#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */
+
+/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/
+#define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)
+#define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
+#define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /*!< LPM support enable                                     */
+#define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)
+#define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
+#define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /*!< LPM Token acknowledge enable                           */
+#define USB_OTG_GLPMCFG_BESL_Pos                 (2U)
+#define USB_OTG_GLPMCFG_BESL_Msk                 (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
+#define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /*!< BESL value received with last ACKed LPM Token          */
+#define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)
+#define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
+#define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /*!< bRemoteWake value received with last ACKed LPM Token   */
+#define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)
+#define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /*!< L1 shallow sleep enable                                */
+#define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)
+#define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
+#define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /*!< BESL threshold                                         */
+#define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)
+#define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
+#define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /*!< L1 deep sleep enable                                   */
+#define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)
+#define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
+#define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /*!< LPM response                                           */
+#define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)
+#define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /*!< Port sleep status                                      */
+#define USB_OTG_GLPMCFG_L1RSMOK_Pos              (16U)
+#define USB_OTG_GLPMCFG_L1RSMOK_Msk              (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
+#define USB_OTG_GLPMCFG_L1RSMOK                  USB_OTG_GLPMCFG_L1RSMOK_Msk   /*!< Sleep State Resume OK                                  */
+#define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)
+#define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /*!< LPM Channel Index                                      */
+#define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)
+#define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
+#define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /*!< LPM retry count                                        */
+#define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)
+#define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /*!< Send LPM transaction                                   */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status                                 */
+#define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)
+#define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
+#define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /*!< Enable best effort service latency                     */
+
+/********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)
+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)
+#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)
+#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)
+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+
+/********************  Bit definition forUSB_OTG_HPRT register  ********************/
+#define USB_OTG_HPRT_PCSTS_Pos                   (0U)
+#define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */
+#define USB_OTG_HPRT_PCDET_Pos                   (1U)
+#define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */
+#define USB_OTG_HPRT_PENA_Pos                    (2U)
+#define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
+#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */
+#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)
+#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
+#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA_Pos                    (4U)
+#define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
+#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */
+#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)
+#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
+#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */
+#define USB_OTG_HPRT_PRES_Pos                    (6U)
+#define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
+#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume   */
+#define USB_OTG_HPRT_PSUSP_Pos                   (7U)
+#define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
+#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend  */
+#define USB_OTG_HPRT_PRST_Pos                    (8U)
+#define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
+#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset    */
+
+#define USB_OTG_HPRT_PLSTS_Pos                   (10U)
+#define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
+#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
+#define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_HPRT_PPWR_Pos                    (12U)
+#define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL_Pos                   (13U)
+#define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
+#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
+#define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
+#define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
+#define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_HPRT_PSPD_Pos                    (17U)
+#define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
+#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
+
+/********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)
+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)
+#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)
+#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)
+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)
+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)
+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
+
+/********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)
+#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)
+#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth */
+
+/********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/
+#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)
+#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)
+#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)
+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)
+#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)
+#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DIEPCTL_STALL_Pos                (21U)
+#define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)
+#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
+#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
+#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
+#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)
+#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)
+#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)
+#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)
+#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)
+#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable */
+
+/********************  Bit definition forUSB_OTG_HCCHAR register  ********************/
+#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)
+#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)
+#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
+#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
+#define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)
+#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)
+#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)
+#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
+
+#define USB_OTG_HCCHAR_MC_Pos                    (20U)
+#define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
+#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
+#define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
+
+#define USB_OTG_HCCHAR_DAD_Pos                   (22U)
+#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
+#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
+#define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
+#define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
+#define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
+#define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
+#define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
+#define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
+#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)
+#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)
+#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)
+#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */
+
+/********************  Bit definition forUSB_OTG_HCSPLT register  ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)
+#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
+#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
+
+#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)
+#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
+#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
+
+#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)
+#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
+#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)
+#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
+#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)
+#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */
+
+/********************  Bit definition forUSB_OTG_HCINT register  ********************/
+#define USB_OTG_HCINT_XFRC_Pos                   (0U)
+#define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH_Pos                    (1U)
+#define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR_Pos                 (2U)
+#define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */
+#define USB_OTG_HCINT_STALL_Pos                  (3U)
+#define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK_Pos                    (4U)
+#define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK_Pos                    (5U)
+#define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET_Pos                   (6U)
+#define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR_Pos                  (7U)
+#define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR_Pos                  (8U)
+#define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR_Pos                  (9U)
+#define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR_Pos                  (10U)
+#define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */
+
+/********************  Bit definition forUSB_OTG_DIEPINT register  ********************/
+#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)
+#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)
+#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_AHBERR_Pos               (2U)
+#define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */
+#define USB_OTG_DIEPINT_TOC_Pos                  (3U)
+#define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)
+#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNM_Pos               (5U)
+#define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */
+#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)
+#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)
+#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
+#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA_Pos                  (9U)
+#define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)
+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR_Pos                 (12U)
+#define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK_Pos                  (13U)
+#define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */
+
+/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/
+#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)
+#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)
+#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)
+#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)
+#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)
+#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)
+#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET_Pos                (6U)
+#define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)
+#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)
+#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)
+#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)
+#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */
+
+/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)
+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)
+#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */
+/********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)
+#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)
+#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)
+#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)
+#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
+#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/
+#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)
+#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */
+
+/********************  Bit definition forUSB_OTG_HCDMA register  ********************/
+#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)
+#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */
+
+/********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)
+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
+
+/********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)
+#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)
+#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */
+
+/********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)
+#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)
+#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)
+#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)
+#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)
+#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)
+#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
+#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL_Pos                (21U)
+#define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)
+#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)
+#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)
+#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)
+#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */
+
+/********************  Bit definition forUSB_OTG_DOEPINT register  ********************/
+#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)
+#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)
+#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_AHBERR_Pos               (2U)
+#define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */
+#define USB_OTG_DOEPINT_STUP_Pos                 (3U)
+#define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)
+#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)
+#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< OUT Status Phase Received interrupt */
+#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)
+#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)
+#define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */
+#define USB_OTG_DOEPINT_BERR_Pos                 (12U)
+#define USB_OTG_DOEPINT_BERR_Msk                 (0x1UL << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPINT_BERR                      USB_OTG_DOEPINT_BERR_Msk   /*!< Babble error interrupt */
+#define USB_OTG_DOEPINT_NAK_Pos                  (13U)
+#define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */
+#define USB_OTG_DOEPINT_NYET_Pos                 (14U)
+#define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */
+#define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)
+#define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */
+
+/********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)
+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for PCGCCTL register  ********************/
+#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)
+#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)
+#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)
+#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+                                       ((INSTANCE) == ADC2) || \
+                                       ((INSTANCE) == ADC3))
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON) ||\
+                                          ((INSTANCE) == ADC3_COMMON))
+
+/******************************** COMP Instances ******************************/
+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
+                                       ((INSTANCE) == COMP2))
+
+#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
+/******************** COMP Instances with window mode capability **************/
+#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
+
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
+/******************************* DCMI Instances *******************************/
+#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
+
+/******************************* DELAYBLOCK Instances *******************************/
+#define IS_DLYB_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DLYB_SDMMC1) || \
+                                         ((INSTANCE) == DLYB_SDMMC2) || \
+                                         ((INSTANCE) == DLYB_QUADSPI))
+/****************************** DFSDM Instances *******************************/
+#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
+                                               ((INSTANCE) == DFSDM1_Filter1) || \
+                                               ((INSTANCE) == DFSDM1_Filter2) || \
+                                               ((INSTANCE) == DFSDM1_Filter3))
+
+#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
+                                                 ((INSTANCE) == DFSDM1_Channel1) || \
+                                                 ((INSTANCE) == DFSDM1_Channel2) || \
+                                                 ((INSTANCE) == DFSDM1_Channel3) || \
+                                                 ((INSTANCE) == DFSDM1_Channel4) || \
+                                                 ((INSTANCE) == DFSDM1_Channel5) || \
+                                                 ((INSTANCE) == DFSDM1_Channel6) || \
+                                                 ((INSTANCE) == DFSDM1_Channel7))
+/****************************** RAMECC Instances ******************************/
+#define IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMECC1_Monitor1)   || \
+                                                  ((INSTANCE) == RAMECC1_Monitor2)   || \
+                                                  ((INSTANCE) == RAMECC1_Monitor3)   || \
+                                                  ((INSTANCE) == RAMECC1_Monitor4)   || \
+                                                  ((INSTANCE) == RAMECC1_Monitor5)   || \
+                                                  ((INSTANCE) == RAMECC2_Monitor1)   || \
+                                                  ((INSTANCE) == RAMECC2_Monitor2)   || \
+                                                  ((INSTANCE) == RAMECC2_Monitor3)   || \
+                                                  ((INSTANCE) == RAMECC2_Monitor4)   || \
+                                                  ((INSTANCE) == RAMECC2_Monitor5)   || \
+                                                  ((INSTANCE) == RAMECC3_Monitor1)   || \
+                                                  ((INSTANCE) == RAMECC3_Monitor2))
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \
+                                       ((INSTANCE) == DMA1_Stream1)   || \
+                                       ((INSTANCE) == DMA1_Stream2)   || \
+                                       ((INSTANCE) == DMA1_Stream3)   || \
+                                       ((INSTANCE) == DMA1_Stream4)   || \
+                                       ((INSTANCE) == DMA1_Stream5)   || \
+                                       ((INSTANCE) == DMA1_Stream6)   || \
+                                       ((INSTANCE) == DMA1_Stream7)   || \
+                                       ((INSTANCE) == DMA2_Stream0)   || \
+                                       ((INSTANCE) == DMA2_Stream1)   || \
+                                       ((INSTANCE) == DMA2_Stream2)   || \
+                                       ((INSTANCE) == DMA2_Stream3)   || \
+                                       ((INSTANCE) == DMA2_Stream4)   || \
+                                       ((INSTANCE) == DMA2_Stream5)   || \
+                                       ((INSTANCE) == DMA2_Stream6)   || \
+                                       ((INSTANCE) == DMA2_Stream7)   || \
+                                       ((INSTANCE) == BDMA_Channel0) || \
+                                       ((INSTANCE) == BDMA_Channel1) || \
+                                       ((INSTANCE) == BDMA_Channel2) || \
+                                       ((INSTANCE) == BDMA_Channel3) || \
+                                       ((INSTANCE) == BDMA_Channel4) || \
+                                       ((INSTANCE) == BDMA_Channel5) || \
+                                       ((INSTANCE) == BDMA_Channel6) || \
+                                       ((INSTANCE) == BDMA_Channel7))
+
+/****************************** BDMA CHANNEL Instances ***************************/
+#define IS_BDMA_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == BDMA_Channel0) || \
+                                            ((INSTANCE) == BDMA_Channel1) || \
+                                            ((INSTANCE) == BDMA_Channel2) || \
+                                            ((INSTANCE) == BDMA_Channel3) || \
+                                            ((INSTANCE) == BDMA_Channel4) || \
+                                            ((INSTANCE) == BDMA_Channel5) || \
+                                            ((INSTANCE) == BDMA_Channel6) || \
+                                            ((INSTANCE) == BDMA_Channel7))
+
+/****************************** DMA DMAMUX ALL Instances ***************************/
+#define IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)    || \
+                                               ((INSTANCE) == DMA1_Stream1)    || \
+                                               ((INSTANCE) == DMA1_Stream2)    || \
+                                               ((INSTANCE) == DMA1_Stream3)    || \
+                                               ((INSTANCE) == DMA1_Stream4)    || \
+                                               ((INSTANCE) == DMA1_Stream5)    || \
+                                               ((INSTANCE) == DMA1_Stream6)    || \
+                                               ((INSTANCE) == DMA1_Stream7)    || \
+                                               ((INSTANCE) == DMA2_Stream0)    || \
+                                               ((INSTANCE) == DMA2_Stream1)    || \
+                                               ((INSTANCE) == DMA2_Stream2)    || \
+                                               ((INSTANCE) == DMA2_Stream3)    || \
+                                               ((INSTANCE) == DMA2_Stream4)    || \
+                                               ((INSTANCE) == DMA2_Stream5)    || \
+                                               ((INSTANCE) == DMA2_Stream6)    || \
+                                               ((INSTANCE) == DMA2_Stream7)    || \
+                                               ((INSTANCE) == BDMA_Channel0)   || \
+                                               ((INSTANCE) == BDMA_Channel1)   || \
+                                               ((INSTANCE) == BDMA_Channel2)   || \
+                                               ((INSTANCE) == BDMA_Channel3)   || \
+                                               ((INSTANCE) == BDMA_Channel4)   || \
+                                               ((INSTANCE) == BDMA_Channel5)   || \
+                                               ((INSTANCE) == BDMA_Channel6)   || \
+                                               ((INSTANCE) == BDMA_Channel7))
+
+/****************************** BDMA DMAMUX Instances ***************************/
+#define IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == BDMA_Channel0) || \
+                                                    ((INSTANCE) == BDMA_Channel1) || \
+                                                    ((INSTANCE) == BDMA_Channel2) || \
+                                                    ((INSTANCE) == BDMA_Channel3) || \
+                                                    ((INSTANCE) == BDMA_Channel4) || \
+                                                    ((INSTANCE) == BDMA_Channel5) || \
+                                                    ((INSTANCE) == BDMA_Channel6) || \
+                                                    ((INSTANCE) == BDMA_Channel7))
+
+/****************************** DMA STREAM Instances ***************************/
+#define IS_DMA_STREAM_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \
+                                          ((INSTANCE) == DMA1_Stream1)   || \
+                                          ((INSTANCE) == DMA1_Stream2)   || \
+                                          ((INSTANCE) == DMA1_Stream3)   || \
+                                          ((INSTANCE) == DMA1_Stream4)   || \
+                                          ((INSTANCE) == DMA1_Stream5)   || \
+                                          ((INSTANCE) == DMA1_Stream6)   || \
+                                          ((INSTANCE) == DMA1_Stream7)   || \
+                                          ((INSTANCE) == DMA2_Stream0)   || \
+                                          ((INSTANCE) == DMA2_Stream1)   || \
+                                          ((INSTANCE) == DMA2_Stream2)   || \
+                                          ((INSTANCE) == DMA2_Stream3)   || \
+                                          ((INSTANCE) == DMA2_Stream4)   || \
+                                          ((INSTANCE) == DMA2_Stream5)   || \
+                                          ((INSTANCE) == DMA2_Stream6)   || \
+                                          ((INSTANCE) == DMA2_Stream7))
+
+/****************************** DMA DMAMUX Instances ***************************/
+#define IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)   || \
+                                                  ((INSTANCE) == DMA1_Stream1)   || \
+                                                  ((INSTANCE) == DMA1_Stream2)   || \
+                                                  ((INSTANCE) == DMA1_Stream3)   || \
+                                                  ((INSTANCE) == DMA1_Stream4)   || \
+                                                  ((INSTANCE) == DMA1_Stream5)   || \
+                                                  ((INSTANCE) == DMA1_Stream6)   || \
+                                                  ((INSTANCE) == DMA1_Stream7)   || \
+                                                  ((INSTANCE) == DMA2_Stream0)   || \
+                                                  ((INSTANCE) == DMA2_Stream1)   || \
+                                                  ((INSTANCE) == DMA2_Stream2)   || \
+                                                  ((INSTANCE) == DMA2_Stream3)   || \
+                                                  ((INSTANCE) == DMA2_Stream4)   || \
+                                                  ((INSTANCE) == DMA2_Stream5)   || \
+                                                  ((INSTANCE) == DMA2_Stream6)   || \
+                                                  ((INSTANCE) == DMA2_Stream7))
+
+/******************************** DMA Request Generator Instances **************/
+#define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator1) || \
+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator2) || \
+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator3) || \
+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator4) || \
+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator5) || \
+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator6) || \
+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator7) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator0) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator1) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator2) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator3) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator4) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator5) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator6) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator7))
+
+/******************************* DMA2D Instances *******************************/
+#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
+
+/******************************** MDMA Request Generator Instances **************/
+#define IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDMA_Channel0)  || \
+                                               ((INSTANCE) == MDMA_Channel1)  || \
+                                               ((INSTANCE) == MDMA_Channel2)  || \
+                                               ((INSTANCE) == MDMA_Channel3)  || \
+                                               ((INSTANCE) == MDMA_Channel4)  || \
+                                               ((INSTANCE) == MDMA_Channel5)  || \
+                                               ((INSTANCE) == MDMA_Channel6)  || \
+                                               ((INSTANCE) == MDMA_Channel7)  || \
+                                               ((INSTANCE) == MDMA_Channel8)  || \
+                                               ((INSTANCE) == MDMA_Channel9)  || \
+                                               ((INSTANCE) == MDMA_Channel10) || \
+                                               ((INSTANCE) == MDMA_Channel11) || \
+                                               ((INSTANCE) == MDMA_Channel12) || \
+                                               ((INSTANCE) == MDMA_Channel13) || \
+                                               ((INSTANCE) == MDMA_Channel14) || \
+                                               ((INSTANCE) == MDMA_Channel15))
+
+/******************************* QUADSPI Instances *******************************/
+#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
+
+/******************************* FDCAN Instances ******************************/
+#define IS_FDCAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == FDCAN1) || \
+                                             ((__INSTANCE__) == FDCAN2))
+
+#define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1)
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+                                        ((INSTANCE) == GPIOB) || \
+                                        ((INSTANCE) == GPIOC) || \
+                                        ((INSTANCE) == GPIOD) || \
+                                        ((INSTANCE) == GPIOE) || \
+                                        ((INSTANCE) == GPIOF) || \
+                                        ((INSTANCE) == GPIOG) || \
+                                        ((INSTANCE) == GPIOH) || \
+                                        ((INSTANCE) == GPIOI) || \
+                                        ((INSTANCE) == GPIOJ) || \
+                                        ((INSTANCE) == GPIOK))
+
+/******************************* GPIO AF Instances ****************************/
+#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/**************************** GPIO Lock Instances *****************************/
+/* On H7, all GPIO Bank support the Lock mechanism */
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/******************************** HSEM Instances *******************************/
+#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)
+#define HSEM_CPU1_COREID         (0x00000003U) /* Semaphore Core CM7 ID */
+#define HSEM_CR_COREID_CPU1      (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
+#define HSEM_CR_COREID_CURRENT   (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
+
+#define HSEM_SEMID_MIN     (0U)       /* HSEM ID Min*/
+#define HSEM_SEMID_MAX     (31U)      /* HSEM ID Max */
+
+#define HSEM_PROCESSID_MIN (0U)       /* HSEM Process ID Min */
+#define HSEM_PROCESSID_MAX (255U)     /* HSEM Process ID Max */
+
+#define HSEM_CLEAR_KEY_MIN (0U)       /* HSEM clear Key Min value */
+#define HSEM_CLEAR_KEY_MAX (0xFFFFU)  /* HSEM clear Key Max value */
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+                                       ((INSTANCE) == I2C2) || \
+                                       ((INSTANCE) == I2C3) || \
+                                       ((INSTANCE) == I2C4))
+/************** I2C Instances : wakeup capability from stop modes *************/
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
+
+/****************************** SMBUS Instances *******************************/
+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+                                         ((INSTANCE) == I2C2) || \
+                                         ((INSTANCE) == I2C3) || \
+                                         ((INSTANCE) == I2C4))
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE)   (((INSTANCE) == SPI1) || \
+                                         ((INSTANCE) == SPI2) || \
+                                         ((INSTANCE) == SPI3))
+
+/****************************** LTDC Instances ********************************/
+#define IS_LTDC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == LTDC)
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
+
+/****************************** SDMMC Instances *********************************/
+#define IS_SDMMC_ALL_INSTANCE(_INSTANCE_) (((_INSTANCE_) == SDMMC1) || \
+                                           ((_INSTANCE_) == SDMMC2))
+
+/******************************** SMBUS Instances *****************************/
+#define IS_SMBUS_INSTANCE(INSTANCE)  ((INSTANCE) == I2C1)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+                                       ((INSTANCE) == SPI2) || \
+                                       ((INSTANCE) == SPI3) || \
+                                       ((INSTANCE) == SPI4) || \
+                                       ((INSTANCE) == SPI5) || \
+                                       ((INSTANCE) == SPI6))
+
+#define IS_SPI_HIGHEND_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+                                           ((INSTANCE) == SPI2) || \
+                                           ((INSTANCE) == SPI3))
+
+/******************************** SWPMI Instances *****************************/
+#define IS_SWPMI_INSTANCE(INSTANCE)  ((INSTANCE) == SWPMI1)
+
+/****************** LPTIM Instances : All supported instances *****************/
+#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \
+                                         ((INSTANCE) == LPTIM2) || \
+                                         ((INSTANCE) == LPTIM3) || \
+                                         ((INSTANCE) == LPTIM4) || \
+                                         ((INSTANCE) == LPTIM5))
+
+/****************** LPTIM Instances : supporting encoder interface **************/
+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \
+                                                           ((INSTANCE) == LPTIM2))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM6)   || \
+                                         ((INSTANCE) == TIM7)   || \
+                                         ((INSTANCE) == TIM8)   || \
+                                         ((INSTANCE) == TIM12)  || \
+                                         ((INSTANCE) == TIM13)  || \
+                                         ((INSTANCE) == TIM14)  || \
+                                         ((INSTANCE) == TIM15)  || \
+                                         ((INSTANCE) == TIM16)  || \
+                                         ((INSTANCE) == TIM17))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8)   || \
+                                         ((INSTANCE) == TIM12)  || \
+                                         ((INSTANCE) == TIM13)  || \
+                                         ((INSTANCE) == TIM14)  || \
+                                         ((INSTANCE) == TIM15)  || \
+                                         ((INSTANCE) == TIM16)  || \
+                                         ((INSTANCE) == TIM17))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8)   || \
+                                         ((INSTANCE) == TIM12)  || \
+                                         ((INSTANCE) == TIM15))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 5 capture/compare channels *************/
+#define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM8))
+/************ TIM Instances : at least 6 capture/compare channels *************/
+#define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
+                                                ((__INSTANCE__) == TIM8))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8)   || \
+                                         ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \
+                                           ((INSTANCE) == TIM2)   || \
+                                           ((INSTANCE) == TIM3)   || \
+                                           ((INSTANCE) == TIM4)   || \
+                                           ((INSTANCE) == TIM5)   || \
+                                           ((INSTANCE) == TIM6)   || \
+                                           ((INSTANCE) == TIM7)   || \
+                                           ((INSTANCE) == TIM8)   || \
+                                           ((INSTANCE) == TIM15)  || \
+                                           ((INSTANCE) == TIM16)  || \
+                                           ((INSTANCE) == TIM17))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM5)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15)  || \
+                                            ((INSTANCE) == TIM16)  || \
+                                            ((INSTANCE) == TIM17))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM5)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM5)   || \
+                                            ((INSTANCE) == TIM8))
+
+/*************** TIM Instances : external trigger reamp input available *******/
+#define IS_TIM_ETR_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \
+                                           ((INSTANCE) == TIM2)   || \
+                                           ((INSTANCE) == TIM3)   || \
+                                           ((INSTANCE) == TIM4)   || \
+                                           ((INSTANCE) == TIM5)   || \
+                                           ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
+                                          ((INSTANCE) == TIM2)  || \
+                                          ((INSTANCE) == TIM3)  || \
+                                          ((INSTANCE) == TIM5)  || \
+                                          ((INSTANCE) == TIM8)  || \
+                                          ((INSTANCE) == TIM16) || \
+                                          ((INSTANCE) == TIM17))
+
+/*************** TIM Instances : external trigger reamp input available *******/
+#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \
+                                              ((INSTANCE) == TIM2)   || \
+                                              ((INSTANCE) == TIM3)   || \
+                                              ((INSTANCE) == TIM5)   || \
+                                              ((INSTANCE) == TIM8))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM5)   || \
+                                            ((INSTANCE) == TIM6)   || \
+                                            ((INSTANCE) == TIM7)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15))
+
+/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                           ((INSTANCE) == TIM2)   || \
+                                           ((INSTANCE) == TIM3)   || \
+                                           ((INSTANCE) == TIM4)   || \
+                                           ((INSTANCE) == TIM5)   || \
+                                           ((INSTANCE) == TIM8)   || \
+                                           ((INSTANCE) == TIM12))
+
+/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
+#define IS_TIM_TRGO2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                           ((INSTANCE) == TIM8))
+
+/****** TIM Instances : TISEL available (TIMx_TISEL available )*********/
+#define IS_TIM_TISEL_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)   || \
+                                          ((INSTANCE) == TIM2)   || \
+                                          ((INSTANCE) == TIM3)   || \
+                                          ((INSTANCE) == TIM4)   || \
+                                          ((INSTANCE) == TIM5)   || \
+                                          ((INSTANCE) == TIM8)   || \
+                                          ((INSTANCE) == TIM15)  || \
+                                          ((INSTANCE) == TIM16)  || \
+                                          ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting commutation event *************/
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)    || \
+                                                     ((INSTANCE) == TIM8)    || \
+                                                     ((INSTANCE) == TIM15)   || \
+                                                     ((INSTANCE) == TIM16)   || \
+                                                     ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1)  || \
+                                                      ((__INSTANCE__) == TIM2)      || \
+                                                      ((__INSTANCE__) == TIM3)      || \
+                                                      ((__INSTANCE__) == TIM4)      || \
+                                                      ((__INSTANCE__) == TIM5)      || \
+                                                      ((__INSTANCE__) == TIM8))
+
+/****** TIM Instances : TIM_CCR5_GC5C available (TIMx_CCR5.GC5C available )*********/
+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                                       ((INSTANCE) == TIM8))
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+    ((((INSTANCE) == TIM1) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4) ||          \
+      ((CHANNEL) == TIM_CHANNEL_5) ||          \
+      ((CHANNEL) == TIM_CHANNEL_6)))           \
+     ||                                        \
+     (((INSTANCE) == TIM2) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+  ||                                           \
+      (((INSTANCE) == TIM3) &&                 \
+      (((CHANNEL) == TIM_CHANNEL_1)||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+  ||                                           \
+      (((INSTANCE) == TIM4) &&                 \
+      (((CHANNEL) == TIM_CHANNEL_1) ||         \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+  ||                                           \
+      (((INSTANCE) == TIM5) &&                 \
+      (((CHANNEL) == TIM_CHANNEL_1) ||         \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+  ||                                           \
+      (((INSTANCE) == TIM8) &&                 \
+      (((CHANNEL) == TIM_CHANNEL_1) ||         \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4) ||          \
+      ((CHANNEL) == TIM_CHANNEL_5) ||          \
+      ((CHANNEL) == TIM_CHANNEL_6)))           \
+  ||                                           \
+     (((INSTANCE) == TIM12) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2)))           \
+  ||                                           \
+     (((INSTANCE) == TIM13) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+  ||                                           \
+     (((INSTANCE) == TIM14) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+  ||                                           \
+     (((INSTANCE) == TIM15) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+     ((CHANNEL) == TIM_CHANNEL_2)))            \
+  ||                                           \
+     (((INSTANCE) == TIM16) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+  ||                                           \
+     (((INSTANCE) == TIM17) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1))))
+
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
+      (((INSTANCE) == TIM1)    || \
+      ((INSTANCE) == TIM8)     || \
+       ((INSTANCE) == TIM15)   || \
+       ((INSTANCE) == TIM16)   || \
+       ((INSTANCE) == TIM17))
+
+/************** TIM Instances : supporting Break source selection *************/
+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                               ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting complementary output(s) ********/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+   ((((INSTANCE) == TIM1) &&                    \
+     (((CHANNEL) == TIM_CHANNEL_1) ||           \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3)))            \
+ ||                                             \
+      (((INSTANCE) == TIM8) &&                  \
+      (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3)))            \
+    ||                                          \
+    (((INSTANCE) == TIM15) &&                   \
+      ((CHANNEL) == TIM_CHANNEL_1))             \
+    ||                                          \
+    (((INSTANCE) == TIM16) &&                   \
+     ((CHANNEL) == TIM_CHANNEL_1))              \
+    ||                                          \
+    (((INSTANCE) == TIM17) &&                   \
+     ((CHANNEL) == TIM_CHANNEL_1)))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM5)    || \
+   ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM15)   || \
+   ((INSTANCE) == TIM16)   || \
+   ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting synchronization ****************/
+#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
+    (((__INSTANCE__) == TIM1)    || \
+     ((__INSTANCE__) == TIM2)    || \
+     ((__INSTANCE__) == TIM3)    || \
+     ((__INSTANCE__) == TIM4)    || \
+     ((__INSTANCE__) == TIM5)    || \
+     ((__INSTANCE__) == TIM6)    || \
+     ((__INSTANCE__) == TIM8)    || \
+     ((__INSTANCE__) == TIM12)   || \
+     ((__INSTANCE__) == TIM15))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM5)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM15)   || \
+   ((INSTANCE) == TIM16)   || \
+   ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting external clock mode 1 for ETRF input */
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM5)    || \
+   ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting external clock mode 2 **********/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1)     || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM5)    || \
+   ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM5)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM5)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3))
+
+/****************** TIM Instances : TIM_32B_COUNTER ***************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : TIM_BKIN2 ***************************/
+#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting Hall sensor interface **********/
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1)  || \
+                                                             ((__INSTANCE__) == TIM2)  || \
+                                                             ((__INSTANCE__) == TIM3)  || \
+                                                             ((__INSTANCE__) == TIM4)  || \
+                                                             ((__INSTANCE__) == TIM5)  || \
+                                                             ((__INSTANCE__) == TIM15) || \
+                                                             ((__INSTANCE__) == TIM8))
+
+/****************************** HRTIM Instances *******************************/
+#define IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                     ((INSTANCE) == USART2) || \
+                                     ((INSTANCE) == USART3) || \
+                                     ((INSTANCE) == USART6))
+
+/******************** USART Instances : SPI slave mode ************************/
+#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                              ((INSTANCE) == USART2) || \
+                                              ((INSTANCE) == USART3) || \
+                                              ((INSTANCE) == USART6))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                    ((INSTANCE) == USART2) || \
+                                    ((INSTANCE) == USART3) || \
+                                    ((INSTANCE) == UART4)  || \
+                                    ((INSTANCE) == UART5)  || \
+                                    ((INSTANCE) == USART6) || \
+                                    ((INSTANCE) == UART7)  || \
+                                    ((INSTANCE) == UART8))
+
+/******************** UART Instances : FIFO mode.******************************/
+#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                         ((INSTANCE) == USART2) || \
+                                         ((INSTANCE) == USART3) || \
+                                         ((INSTANCE) == UART4)  || \
+                                         ((INSTANCE) == UART5)  || \
+                                         ((INSTANCE) == USART6) || \
+                                         ((INSTANCE) == UART7)  || \
+                                         ((INSTANCE) == UART8))
+
+/****************** UART Instances : Auto Baud Rate detection *****************/
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                                            ((INSTANCE) == USART2) || \
+                                                            ((INSTANCE) == USART3) || \
+                                                            ((INSTANCE) == UART4)  || \
+                                                            ((INSTANCE) == UART5)  || \
+                                                            ((INSTANCE) == USART6) || \
+                                                            ((INSTANCE) == UART7)  || \
+                                                            ((INSTANCE) == UART8))
+
+/*********************** UART Instances : Driver Enable ***********************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                                  ((INSTANCE) == USART2) || \
+                                                  ((INSTANCE) == USART3) || \
+                                                  ((INSTANCE) == UART4)  || \
+                                                  ((INSTANCE) == UART5)  || \
+                                                  ((INSTANCE) == USART6) || \
+                                                  ((INSTANCE) == UART7)  || \
+                                                  ((INSTANCE) == UART8)  || \
+                                                  ((INSTANCE) == LPUART1))
+
+/********************* UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                               ((INSTANCE) == USART2) || \
+                                               ((INSTANCE) == USART3) || \
+                                               ((INSTANCE) == UART4)  || \
+                                               ((INSTANCE) == UART5)  || \
+                                               ((INSTANCE) == USART6) || \
+                                               ((INSTANCE) == UART7)  || \
+                                               ((INSTANCE) == UART8)  || \
+                                               ((INSTANCE) == LPUART1))
+
+/******************* UART Instances : Hardware Flow control *******************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                           ((INSTANCE) == USART2) || \
+                                           ((INSTANCE) == USART3) || \
+                                           ((INSTANCE) == UART4)  || \
+                                           ((INSTANCE) == UART5)  || \
+                                           ((INSTANCE) == USART6) || \
+                                           ((INSTANCE) == UART7)  || \
+                                           ((INSTANCE) == UART8)  || \
+                                           ((INSTANCE) == LPUART1))
+
+/************************* UART Instances : LIN mode **************************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                        ((INSTANCE) == USART2) || \
+                                        ((INSTANCE) == USART3) || \
+                                        ((INSTANCE) == UART4)  || \
+                                        ((INSTANCE) == UART5)  || \
+                                        ((INSTANCE) == USART6) || \
+                                        ((INSTANCE) == UART7)  || \
+                                        ((INSTANCE) == UART8))
+
+/****************** UART Instances : Wake-up from Stop mode *******************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                                    ((INSTANCE) == USART2) || \
+                                                    ((INSTANCE) == USART3) || \
+                                                    ((INSTANCE) == UART4)  || \
+                                                    ((INSTANCE) == UART5)  || \
+                                                    ((INSTANCE) == USART6) || \
+                                                    ((INSTANCE) == UART7)  || \
+                                                    ((INSTANCE) == UART8)  || \
+                                                    ((INSTANCE) == LPUART1))
+
+/************************* UART Instances : IRDA mode *************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                    ((INSTANCE) == USART2) || \
+                                    ((INSTANCE) == USART3) || \
+                                    ((INSTANCE) == UART4)  || \
+                                    ((INSTANCE) == UART5)  || \
+                                    ((INSTANCE) == USART6) || \
+                                    ((INSTANCE) == UART7)  || \
+                                    ((INSTANCE) == UART8))
+
+/********************* USART Instances : Smard card mode **********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                         ((INSTANCE) == USART2) || \
+                                         ((INSTANCE) == USART3) || \
+                                         ((INSTANCE) == USART6))
+
+/****************************** LPUART Instance *******************************/
+#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG1)
+/****************************** USB Instances ********************************/
+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG1)
+/****************************** MDIOS Instances ********************************/
+#define IS_MDIOS_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == MDIOS)
+
+/****************************** CEC Instances *********************************/
+#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
+
+/****************************** SAI Instances ********************************/
+#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
+                    ((INSTANCE) == SAI1_Block_B) || \
+                     ((INSTANCE) == SAI2_Block_A) || \
+                     ((INSTANCE) == SAI2_Block_B) || \
+                     ((INSTANCE) == SAI3_Block_A) || \
+                     ((INSTANCE) == SAI3_Block_B) || \
+                     ((INSTANCE) == SAI4_Block_A) || \
+                     ((INSTANCE) == SAI4_Block_B))
+
+/****************************** SPDIFRX Instances ********************************/
+#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)
+
+/****************************** OPAMP Instances *******************************/
+#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
+                                         ((INSTANCE) == OPAMP2))
+
+#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
+
+/*********************** USB OTG PCD Instances ********************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+                                        ((INSTANCE) == USB_OTG_HS))
+
+/*********************** USB OTG HCD Instances ********************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+                                       ((INSTANCE) == USB_OTG_HS))
+
+/******************************************************************************/
+/*  For a painless codes migration between the STM32H7xx device product       */
+/*  lines, or with STM32F7xx devices the aliases defined below are put        */
+/*   in place to overcome the differences in the interrupt handlers and IRQn  */
+/*   definitions. No need to update developed interrupt code when moving      */
+/*  across product lines within the same STM32H7 Family                       */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define  HASH_RNG_IRQn                  RNG_IRQn
+#define  TIM1_BRK_TIM9_IRQn             TIM1_BRK_IRQn
+#define  TIM1_UP_TIM10_IRQn             TIM1_UP_IRQn
+#define  TIM1_TRG_COM_TIM11_IRQn        TIM1_TRG_COM_IRQn
+#define  PVD_IRQn                       PVD_AVD_IRQn
+
+
+
+/* Aliases for __IRQHandler */
+#define  HASH_RNG_IRQHandler           RNG_IRQHandler
+#define TIM1_BRK_TIM9_IRQHandler       TIM1_BRK_IRQHandler
+#define TIM1_UP_TIM9_IRQHandler        TIM1_UP_IRQHandler
+#define TIM1_TRG_COM_TIM11_IRQHandler  TIM1_TRG_COM_IRQHandler
+#define PVD_IRQHandler                 PVD_AVD_IRQHandler
+
+/* Aliases for COMP __IRQHandler */
+#define COMP_IRQHandler                COMP1_IRQHandler
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* STM32H743xx_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h
new file mode 100644
index 00000000..f6296181
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h
@@ -0,0 +1,224 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32H7xx Device Peripheral Access Layer Header File.
+  *
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The STM32H7xx device used in the target application
+  *              - To use or not the peripheral�s drivers in application code(i.e.
+  *                code will be based on direct access to peripheral�s registers
+  *                rather than drivers API), this option is controlled by
+  *                "#define USE_HAL_DRIVER"
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32h7xx
+  * @{
+  */
+
+#ifndef STM32H7xx_H
+#define STM32H7xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+
+/**
+  * @brief STM32 Family
+  */
+#if !defined  (STM32H7)
+#define STM32H7
+#endif /* STM32H7 */
+
+
+/* Uncomment the line below according to the target STM32H7 device used in your
+   application
+  */
+
+#if !defined (STM32H743xx) && !defined (STM32H753xx)  && !defined (STM32H750xx) && !defined (STM32H742xx) && \
+    !defined (STM32H745xx) && !defined (STM32H755xx)  && !defined (STM32H747xx) && !defined (STM32H757xx) && \
+    !defined (STM32H7A3xx) && !defined (STM32H7A3xxQ) && !defined (STM32H7B3xx) && !defined (STM32H7B3xxQ) && !defined (STM32H7B0xx)  && !defined (STM32H7B0xxQ)
+  /* #define STM32H742xx */   /*!< STM32H742VI, STM32H742ZI, STM32H742AI, STM32H742II, STM32H742BI, STM32H742XI Devices */
+  /* #define STM32H743xx */   /*!< STM32H743VI, STM32H743ZI, STM32H743AI, STM32H743II, STM32H743BI, STM32H743XI Devices */
+  /* #define STM32H753xx */   /*!< STM32H753VI, STM32H753ZI, STM32H753AI, STM32H753II, STM32H753BI, STM32H753XI Devices */
+  /* #define STM32H750xx */   /*!< STM32H750V, STM32H750I, STM32H750X Devices */
+  /* #define STM32H747xx */   /*!< STM32H747ZI, STM32H747AI, STM32H747II, STM32H747BI, STM32H747XI Devices */
+  /* #define STM32H757xx */   /*!< STM32H757ZI, STM32H757AI, STM32H757II, STM32H757BI, STM32H757XI Devices */
+  /* #define STM32H745xx */   /*!< STM32H745ZI, STM32H745II, STM32H745BI, STM32H745XI Devices  */
+  /* #define STM32H755xx */   /*!< STM32H755ZI, STM32H755II, STM32H755BI, STM32H755XI Devices  */
+  /* #define STM32H7B0xx */   /*!< STM32H7B0ABIxQ, STM32H7B0IBTx, STM32H7B0RBTx, STM32H7B0VBTx, STM32H7B0ZBTx, STM32H7B0IBKxQ */
+  /* #define STM32H7A3xx */   /*!< STM32H7A3IIK6, STM32H7A3IIT6, STM32H7A3NIH6, STM32H7A3RIT6, STM32H7A3VIH6, STM32H7A3VIT6, STM32H7A3ZIT6 */
+  /* #define STM32H7A3xxQ */  /*!< STM32H7A3QIY6Q, STM32H7A3IIK6Q, STM32H7A3IIT6Q, STM32H7A3LIH6Q, STM32H7A3VIH6Q, STM32H7A3VIT6Q, STM32H7A3AII6Q, STM32H7A3ZIT6Q */
+  /* #define STM32H7B3xx */   /*!< STM32H7B3IIK6, STM32H7B3IIT6, STM32H7B3NIH6, STM32H7B3RIT6, STM32H7B3VIH6, STM32H7B3VIT6, STM32H7B3ZIT6 */
+  /* #define STM32H7B3xxQ */  /*!< STM32H7B3QIY6Q, STM32H7B3IIK6Q, STM32H7B3IIT6Q, STM32H7B3LIH6Q, STM32H7B3VIH6Q, STM32H7B3VIT6Q, STM32H7B3AII6Q, STM32H7B3ZIT6Q */
+#endif
+
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+
+#if defined(DUAL_CORE) && !defined(CORE_CM4) && !defined(CORE_CM7)
+ #error "Dual core device, please select CORE_CM4 or CORE_CM7"
+#endif
+
+#if !defined  (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will
+   be based on direct access to peripherals registers
+   */
+  /*#define USE_HAL_DRIVER */
+#endif /* USE_HAL_DRIVER */
+
+/**
+  * @brief CMSIS Device version number V1.8.0
+  */
+#define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN   (0x01) /*!< [31:24] main version */
+#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1   (0x08) /*!< [23:16] sub1 version */
+#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __STM32H7xx_CMSIS_DEVICE_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
+#define __STM32H7xx_CMSIS_DEVICE_VERSION        ((__CMSIS_DEVICE_VERSION_MAIN     << 24)\
+                                      |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
+                                      |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
+                                      |(__CMSIS_DEVICE_HAL_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Device_Included
+  * @{
+  */
+
+#if defined(STM32H743xx)
+  #include "stm32h743xx.h"
+#elif defined(STM32H753xx)
+  #include "stm32h753xx.h"
+#elif defined(STM32H750xx)
+  #include "stm32h750xx.h"
+#elif defined(STM32H742xx)
+  #include "stm32h742xx.h"
+#elif defined(STM32H745xx)
+  #include "stm32h745xx.h"
+#elif defined(STM32H755xx)
+  #include "stm32h755xx.h"
+#elif defined(STM32H747xx)
+  #include "stm32h747xx.h"
+#elif defined(STM32H757xx)
+  #include "stm32h757xx.h"
+#elif defined(STM32H7B0xx)
+  #include "stm32h7b0xx.h"
+#elif defined(STM32H7B0xxQ)
+  #include "stm32h7b0xxq.h"
+#elif defined(STM32H7A3xx)
+  #include "stm32h7a3xx.h"
+#elif defined(STM32H7B3xx)
+  #include "stm32h7b3xx.h"
+#elif defined(STM32H7A3xxQ)
+  #include "stm32h7a3xxq.h"
+#elif defined(STM32H7B3xxQ)
+  #include "stm32h7b3xxq.h"
+#else
+ #error "Please select first the target STM32H7xx device used in your application (in stm32h7xx.h file)"
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_types
+  * @{
+  */
+typedef enum
+{
+  RESET = 0,
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+  DISABLE = 0,
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+  SUCCESS = 0,
+  ERROR = !SUCCESS
+} ErrorStatus;
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL)))
+
+
+/**
+  * @}
+  */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32h7xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* STM32H7xx_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h
new file mode 100644
index 00000000..dd75af67
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h
@@ -0,0 +1,105 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32h7xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-Mx Device System Source File for STM32H7xx devices.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32h7xx_system
+  * @{
+  */
+
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef SYSTEM_STM32H7XX_H
+#define SYSTEM_STM32H7XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32H7xx_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32H7xx_System_Exported_types
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+extern uint32_t SystemCoreClock;             /*!< System Domain1 Clock Frequency  */
+extern uint32_t SystemD2Clock;               /*!< System Domain2 Clock Frequency  */
+extern const  uint8_t D1CorePrescTable[16] ; /*!< D1CorePrescTable prescalers table values */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Exported_Functions
+  * @{
+  */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_STM32H7XX_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/cmsis_armcc.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/cmsis_armcc.h
new file mode 100644
index 00000000..7d751fb3
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/cmsis_armcc.h
@@ -0,0 +1,865 @@
+/**************************************************************************//**
+ * @file     cmsis_armcc.h
+ * @brief    CMSIS compiler ARMCC (Arm Compiler 5) header file
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+  #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \
+     (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )
+  #define __ARM_ARCH_6M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))
+  #define __ARM_ARCH_7M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+  #define __ARM_ARCH_7EM__          1
+#endif
+
+  /* __ARM_ARCH_8M_BASE__  not applicable */
+  /* __ARM_ARCH_8M_MAIN__  not applicable */
+
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE                 
+  #define __STATIC_FORCEINLINE                   static __forceinline
+#endif           
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __declspec(noreturn)
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        __packed struct
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         __packed union
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #define __UNALIGNED_UINT32(x)                  (*((__packed uint32_t *)(x)))
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();     */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();    */
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  register uint32_t __regBasePriMax      __ASM("basepri_max");
+  __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#else
+  (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB() do {\
+                   __schedule_barrier();\
+                   __isb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+                   __schedule_barrier();\
+                   __dsb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+                   __schedule_barrier();\
+                   __dmb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+                  
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+  #define __RBIT                          __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value != 0U; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+  return result;
+}
+#endif
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
+#else
+  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
+#else
+  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
+#else
+  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXB(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX                           __clrex
+
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#else  /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/cmsis_armclang.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/cmsis_armclang.h
new file mode 100644
index 00000000..d8031b03
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/cmsis_armclang.h
@@ -0,0 +1,1869 @@
+/**************************************************************************//**
+ * @file     cmsis_armclang.h
+ * @brief    CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header   /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include <arm_compat.h>    /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE                 
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline
+#endif                                           
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+  
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+  
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+  return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#define __get_FPSCR      (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR()      ((uint32_t)0U)
+#endif
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#define __set_FPSCR      __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x)      ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP          __builtin_arm_nop
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI          __builtin_arm_wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE          __builtin_arm_wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV          __builtin_arm_sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB()        __builtin_arm_isb(0xF);
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()        __builtin_arm_dsb(0xF);
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB()        __builtin_arm_dmb(0xF);
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV(value)   __builtin_bswap32(value)
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U)
+  {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)     __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __RBIT            __builtin_arm_rbit
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ             (uint8_t)__builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB        (uint8_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH        (uint16_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW        (uint32_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXB        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXH        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXW        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX             __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT             __builtin_arm_ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT             __builtin_arm_usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXB                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXH                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEX                  (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+  int32_t result;
+
+  __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/cmsis_compiler.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/cmsis_compiler.h
new file mode 100644
index 00000000..79a2cac3
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/cmsis_compiler.h
@@ -0,0 +1,266 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/cmsis_gcc.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/cmsis_gcc.h
new file mode 100644
index 00000000..1bd41a49
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/cmsis_gcc.h
@@ -0,0 +1,2085 @@
+/**************************************************************************//**
+ * @file     cmsis_gcc.h
+ * @brief    CMSIS compiler GCC header file
+ * @version  V5.0.4
+ * @date     09. April 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+  #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static inline
+#endif
+#ifndef   __STATIC_FORCEINLINE                 
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
+#endif                                           
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+  
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+  
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+  return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_get_fpscr) 
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+  return __builtin_arm_get_fpscr();
+#else
+  uint32_t result;
+
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  return(result);
+#endif
+#else
+  return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_set_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+  __builtin_arm_set_fpscr(fpscr);
+#else
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#endif
+#else
+  (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP()                             __ASM volatile ("nop")
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI()                             __ASM volatile ("wfi")
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE()                             __ASM volatile ("wfe")
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV()                             __ASM volatile ("sev")
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE void __ISB(void)
+{
+  __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+  __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+  __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (int16_t)__builtin_bswap16(value);
+#else
+  int16_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U)
+  {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value != 0U; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+#endif
+  return result;
+}
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ             (uint8_t)__builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  ARG1  Value to be saturated
+  \param [in]  ARG2  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+__extension__ \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  ARG1  Value to be saturated
+  \param [in]  ARG2  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+ __extension__ \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/cmsis_iccarm.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/cmsis_iccarm.h
new file mode 100644
index 00000000..3c90a2cd
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/cmsis_iccarm.h
@@ -0,0 +1,935 @@
+/**************************************************************************//**
+ * @file     cmsis_iccarm.h
+ * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version  V5.0.7
+ * @date     19. June 2018
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2018 IAR Systems
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+  #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+  #define __ICCARM_V8 1
+#else
+  #define __ICCARM_V8 0
+#endif
+
+#ifndef __ALIGNED
+  #if __ICCARM_V8
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #elif (__VER__ >= 7080000)
+    /* Needs IAR language extensions */
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #else
+    #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
+/* Macros already defined */
+#else
+  #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
+    #if __ARM_ARCH == 6
+      #define __ARM_ARCH_6M__ 1
+    #elif __ARM_ARCH == 7
+      #if __ARM_FEATURE_DSP
+        #define __ARM_ARCH_7EM__ 1
+      #else
+        #define __ARM_ARCH_7M__ 1
+      #endif
+    #endif /* __ARM_ARCH */
+  #endif /* __ARM_ARCH_PROFILE == 'M' */
+#endif
+
+/* Alternativ core deduction for older ICCARM's */
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
+    !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
+  #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
+    #define __ARM_ARCH_6M__ 1
+  #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
+    #define __ARM_ARCH_7M__ 1
+  #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
+    #define __ARM_ARCH_7EM__  1
+  #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #else
+    #error "Unknown target."
+  #endif
+#endif
+
+
+
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
+  #define __IAR_M0_FAMILY  1
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
+  #define __IAR_M0_FAMILY  1
+#else
+  #define __IAR_M0_FAMILY  0
+#endif
+
+
+#ifndef __ASM
+  #define __ASM __asm
+#endif
+
+#ifndef __INLINE
+  #define __INLINE inline
+#endif
+
+#ifndef   __NO_RETURN
+  #if __ICCARM_V8
+    #define __NO_RETURN __attribute__((__noreturn__))
+  #else
+    #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+  #endif
+#endif
+
+#ifndef   __PACKED
+  #if __ICCARM_V8
+    #define __PACKED __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED __packed
+  #endif
+#endif
+
+#ifndef   __PACKED_STRUCT
+  #if __ICCARM_V8
+    #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_STRUCT __packed struct
+  #endif
+#endif
+
+#ifndef   __PACKED_UNION
+  #if __ICCARM_V8
+    #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_UNION __packed union
+  #endif
+#endif
+
+#ifndef   __RESTRICT
+  #define __RESTRICT            __restrict
+#endif
+
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE       static inline
+#endif
+
+#ifndef   __FORCEINLINE
+  #define __FORCEINLINE         _Pragma("inline=forced")
+#endif
+
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE  __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+{
+  return *(__packed uint16_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+{
+  *(__packed uint16_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+{
+  return *(__packed uint32_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+{
+  *(__packed uint32_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32   /* deprecated */
+#pragma language=save
+#pragma language=extended
+__packed struct  __iar_u32 { uint32_t v; };
+#pragma language=restore
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+
+#ifndef   __USED
+  #if __ICCARM_V8
+    #define __USED __attribute__((used))
+  #else
+    #define __USED _Pragma("__root")
+  #endif
+#endif
+
+#ifndef   __WEAK
+  #if __ICCARM_V8
+    #define __WEAK __attribute__((weak))
+  #else
+    #define __WEAK _Pragma("__weak")
+  #endif
+#endif
+
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+  #define __ICCARM_INTRINSICS_VERSION__  0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+  #if defined(__CLZ)
+    #undef __CLZ
+  #endif
+  #if defined(__REVSH)
+    #undef __REVSH
+  #endif
+  #if defined(__RBIT)
+    #undef __RBIT
+  #endif
+  #if defined(__SSAT)
+    #undef __SSAT
+  #endif
+  #if defined(__USAT)
+    #undef __USAT
+  #endif
+
+  #include "iccarm_builtin.h"
+
+  #define __disable_fault_irq __iar_builtin_disable_fiq
+  #define __disable_irq       __iar_builtin_disable_interrupt
+  #define __enable_fault_irq  __iar_builtin_enable_fiq
+  #define __enable_irq        __iar_builtin_enable_interrupt
+  #define __arm_rsr           __iar_builtin_rsr
+  #define __arm_wsr           __iar_builtin_wsr
+
+
+  #define __get_APSR()                (__arm_rsr("APSR"))
+  #define __get_BASEPRI()             (__arm_rsr("BASEPRI"))
+  #define __get_CONTROL()             (__arm_rsr("CONTROL"))
+  #define __get_FAULTMASK()           (__arm_rsr("FAULTMASK"))
+
+  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+    #define __get_FPSCR()             (__arm_rsr("FPSCR"))
+    #define __set_FPSCR(VALUE)        (__arm_wsr("FPSCR", (VALUE)))
+  #else
+    #define __get_FPSCR()             ( 0 )
+    #define __set_FPSCR(VALUE)        ((void)VALUE)
+  #endif
+
+  #define __get_IPSR()                (__arm_rsr("IPSR"))
+  #define __get_MSP()                 (__arm_rsr("MSP"))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __get_MSPLIM()            (0U)
+  #else
+    #define __get_MSPLIM()            (__arm_rsr("MSPLIM"))
+  #endif
+  #define __get_PRIMASK()             (__arm_rsr("PRIMASK"))
+  #define __get_PSP()                 (__arm_rsr("PSP"))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __get_PSPLIM()            (0U)
+  #else
+    #define __get_PSPLIM()            (__arm_rsr("PSPLIM"))
+  #endif
+
+  #define __get_xPSR()                (__arm_rsr("xPSR"))
+
+  #define __set_BASEPRI(VALUE)        (__arm_wsr("BASEPRI", (VALUE)))
+  #define __set_BASEPRI_MAX(VALUE)    (__arm_wsr("BASEPRI_MAX", (VALUE)))
+  #define __set_CONTROL(VALUE)        (__arm_wsr("CONTROL", (VALUE)))
+  #define __set_FAULTMASK(VALUE)      (__arm_wsr("FAULTMASK", (VALUE)))
+  #define __set_MSP(VALUE)            (__arm_wsr("MSP", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __set_MSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_MSPLIM(VALUE)       (__arm_wsr("MSPLIM", (VALUE)))
+  #endif
+  #define __set_PRIMASK(VALUE)        (__arm_wsr("PRIMASK", (VALUE)))
+  #define __set_PSP(VALUE)            (__arm_wsr("PSP", (VALUE)))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __set_PSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_PSPLIM(VALUE)       (__arm_wsr("PSPLIM", (VALUE)))
+  #endif
+
+  #define __TZ_get_CONTROL_NS()       (__arm_rsr("CONTROL_NS"))
+  #define __TZ_set_CONTROL_NS(VALUE)  (__arm_wsr("CONTROL_NS", (VALUE)))
+  #define __TZ_get_PSP_NS()           (__arm_rsr("PSP_NS"))
+  #define __TZ_set_PSP_NS(VALUE)      (__arm_wsr("PSP_NS", (VALUE)))
+  #define __TZ_get_MSP_NS()           (__arm_rsr("MSP_NS"))
+  #define __TZ_set_MSP_NS(VALUE)      (__arm_wsr("MSP_NS", (VALUE)))
+  #define __TZ_get_SP_NS()            (__arm_rsr("SP_NS"))
+  #define __TZ_set_SP_NS(VALUE)       (__arm_wsr("SP_NS", (VALUE)))
+  #define __TZ_get_PRIMASK_NS()       (__arm_rsr("PRIMASK_NS"))
+  #define __TZ_set_PRIMASK_NS(VALUE)  (__arm_wsr("PRIMASK_NS", (VALUE)))
+  #define __TZ_get_BASEPRI_NS()       (__arm_rsr("BASEPRI_NS"))
+  #define __TZ_set_BASEPRI_NS(VALUE)  (__arm_wsr("BASEPRI_NS", (VALUE)))
+  #define __TZ_get_FAULTMASK_NS()     (__arm_rsr("FAULTMASK_NS"))
+  #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __TZ_get_PSPLIM_NS()      (0U)
+    #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+  #else
+    #define __TZ_get_PSPLIM_NS()      (__arm_rsr("PSPLIM_NS"))
+    #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+  #endif
+
+  #define __TZ_get_MSPLIM_NS()        (__arm_rsr("MSPLIM_NS"))
+  #define __TZ_set_MSPLIM_NS(VALUE)   (__arm_wsr("MSPLIM_NS", (VALUE)))
+
+  #define __NOP     __iar_builtin_no_operation
+
+  #define __CLZ     __iar_builtin_CLZ
+  #define __CLREX   __iar_builtin_CLREX
+
+  #define __DMB     __iar_builtin_DMB
+  #define __DSB     __iar_builtin_DSB
+  #define __ISB     __iar_builtin_ISB
+
+  #define __LDREXB  __iar_builtin_LDREXB
+  #define __LDREXH  __iar_builtin_LDREXH
+  #define __LDREXW  __iar_builtin_LDREX
+
+  #define __RBIT    __iar_builtin_RBIT
+  #define __REV     __iar_builtin_REV
+  #define __REV16   __iar_builtin_REV16
+
+  __IAR_FT int16_t __REVSH(int16_t val)
+  {
+    return (int16_t) __iar_builtin_REVSH(val);
+  }
+
+  #define __ROR     __iar_builtin_ROR
+  #define __RRX     __iar_builtin_RRX
+
+  #define __SEV     __iar_builtin_SEV
+
+  #if !__IAR_M0_FAMILY
+    #define __SSAT    __iar_builtin_SSAT
+  #endif
+
+  #define __STREXB  __iar_builtin_STREXB
+  #define __STREXH  __iar_builtin_STREXH
+  #define __STREXW  __iar_builtin_STREX
+
+  #if !__IAR_M0_FAMILY
+    #define __USAT    __iar_builtin_USAT
+  #endif
+
+  #define __WFE     __iar_builtin_WFE
+  #define __WFI     __iar_builtin_WFI
+
+  #if __ARM_MEDIA__
+    #define __SADD8   __iar_builtin_SADD8
+    #define __QADD8   __iar_builtin_QADD8
+    #define __SHADD8  __iar_builtin_SHADD8
+    #define __UADD8   __iar_builtin_UADD8
+    #define __UQADD8  __iar_builtin_UQADD8
+    #define __UHADD8  __iar_builtin_UHADD8
+    #define __SSUB8   __iar_builtin_SSUB8
+    #define __QSUB8   __iar_builtin_QSUB8
+    #define __SHSUB8  __iar_builtin_SHSUB8
+    #define __USUB8   __iar_builtin_USUB8
+    #define __UQSUB8  __iar_builtin_UQSUB8
+    #define __UHSUB8  __iar_builtin_UHSUB8
+    #define __SADD16  __iar_builtin_SADD16
+    #define __QADD16  __iar_builtin_QADD16
+    #define __SHADD16 __iar_builtin_SHADD16
+    #define __UADD16  __iar_builtin_UADD16
+    #define __UQADD16 __iar_builtin_UQADD16
+    #define __UHADD16 __iar_builtin_UHADD16
+    #define __SSUB16  __iar_builtin_SSUB16
+    #define __QSUB16  __iar_builtin_QSUB16
+    #define __SHSUB16 __iar_builtin_SHSUB16
+    #define __USUB16  __iar_builtin_USUB16
+    #define __UQSUB16 __iar_builtin_UQSUB16
+    #define __UHSUB16 __iar_builtin_UHSUB16
+    #define __SASX    __iar_builtin_SASX
+    #define __QASX    __iar_builtin_QASX
+    #define __SHASX   __iar_builtin_SHASX
+    #define __UASX    __iar_builtin_UASX
+    #define __UQASX   __iar_builtin_UQASX
+    #define __UHASX   __iar_builtin_UHASX
+    #define __SSAX    __iar_builtin_SSAX
+    #define __QSAX    __iar_builtin_QSAX
+    #define __SHSAX   __iar_builtin_SHSAX
+    #define __USAX    __iar_builtin_USAX
+    #define __UQSAX   __iar_builtin_UQSAX
+    #define __UHSAX   __iar_builtin_UHSAX
+    #define __USAD8   __iar_builtin_USAD8
+    #define __USADA8  __iar_builtin_USADA8
+    #define __SSAT16  __iar_builtin_SSAT16
+    #define __USAT16  __iar_builtin_USAT16
+    #define __UXTB16  __iar_builtin_UXTB16
+    #define __UXTAB16 __iar_builtin_UXTAB16
+    #define __SXTB16  __iar_builtin_SXTB16
+    #define __SXTAB16 __iar_builtin_SXTAB16
+    #define __SMUAD   __iar_builtin_SMUAD
+    #define __SMUADX  __iar_builtin_SMUADX
+    #define __SMMLA   __iar_builtin_SMMLA
+    #define __SMLAD   __iar_builtin_SMLAD
+    #define __SMLADX  __iar_builtin_SMLADX
+    #define __SMLALD  __iar_builtin_SMLALD
+    #define __SMLALDX __iar_builtin_SMLALDX
+    #define __SMUSD   __iar_builtin_SMUSD
+    #define __SMUSDX  __iar_builtin_SMUSDX
+    #define __SMLSD   __iar_builtin_SMLSD
+    #define __SMLSDX  __iar_builtin_SMLSDX
+    #define __SMLSLD  __iar_builtin_SMLSLD
+    #define __SMLSLDX __iar_builtin_SMLSLDX
+    #define __SEL     __iar_builtin_SEL
+    #define __QADD    __iar_builtin_QADD
+    #define __QSUB    __iar_builtin_QSUB
+    #define __PKHBT   __iar_builtin_PKHBT
+    #define __PKHTB   __iar_builtin_PKHTB
+  #endif
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #define __CLZ  __cmsis_iar_clz_not_active
+    #define __SSAT __cmsis_iar_ssat_not_active
+    #define __USAT __cmsis_iar_usat_not_active
+    #define __RBIT __cmsis_iar_rbit_not_active
+    #define __get_APSR  __cmsis_iar_get_APSR_not_active
+  #endif
+
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+    #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
+  #endif
+
+  #ifdef __INTRINSICS_INCLUDED
+  #error intrinsics.h is already included previously!
+  #endif
+
+  #include <intrinsics.h>
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #undef __CLZ
+    #undef __SSAT
+    #undef __USAT
+    #undef __RBIT
+    #undef __get_APSR
+
+    __STATIC_INLINE uint8_t __CLZ(uint32_t data)
+    {
+      if (data == 0U) { return 32U; }
+
+      uint32_t count = 0U;
+      uint32_t mask = 0x80000000U;
+
+      while ((data & mask) == 0U)
+      {
+        count += 1U;
+        mask = mask >> 1U;
+      }
+      return count;
+    }
+
+    __STATIC_INLINE uint32_t __RBIT(uint32_t v)
+    {
+      uint8_t sc = 31U;
+      uint32_t r = v;
+      for (v >>= 1U; v; v >>= 1U)
+      {
+        r <<= 1U;
+        r |= v & 1U;
+        sc--;
+      }
+      return (r << sc);
+    }
+
+    __STATIC_INLINE  uint32_t __get_APSR(void)
+    {
+      uint32_t res;
+      __asm("MRS      %0,APSR" : "=r" (res));
+      return res;
+    }
+
+  #endif
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #undef __get_FPSCR
+    #undef __set_FPSCR
+    #define __get_FPSCR()       (0)
+    #define __set_FPSCR(VALUE)  ((void)VALUE)
+  #endif
+
+  #pragma diag_suppress=Pe940
+  #pragma diag_suppress=Pe177
+
+  #define __enable_irq    __enable_interrupt
+  #define __disable_irq   __disable_interrupt
+  #define __NOP           __no_operation
+
+  #define __get_xPSR      __get_PSR
+
+  #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
+
+    __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+    {
+      return __LDREX((unsigned long *)ptr);
+    }
+
+    __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+    {
+      return __STREX(value, (unsigned long *)ptr);
+    }
+  #endif
+
+
+  /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+  #if (__CORTEX_M >= 0x03)
+
+    __IAR_FT uint32_t __RRX(uint32_t value)
+    {
+      uint32_t result;
+      __ASM("RRX      %0, %1" : "=r"(result) : "r" (value) : "cc");
+      return(result);
+    }
+
+    __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_MAX,%0"::"r" (value));
+    }
+
+
+    #define __enable_fault_irq  __enable_fiq
+    #define __disable_fault_irq __disable_fiq
+
+
+  #endif /* (__CORTEX_M >= 0x03) */
+
+  __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+  {
+    return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+  }
+
+  #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+       (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+   __IAR_FT uint32_t __get_MSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,MSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_MSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      MSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __get_PSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,PSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_PSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      PSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,CONTROL_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_CONTROL_NS(uint32_t value)
+    {
+      __asm volatile("MSR      CONTROL_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_SP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,SP_NS" : "=r" (res));
+      return res;
+    }
+    __IAR_FT void   __TZ_set_SP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      SP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PRIMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PRIMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PRIMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PRIMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_BASEPRI_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,BASEPRI_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_BASEPRI_NS(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_FAULTMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,FAULTMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_FAULTMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      FAULTMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSPLIM_NS(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,PSPLIM_NS" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PSPLIM_NS(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      PSPLIM_NS,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSPLIM_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSPLIM_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSPLIM_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSPLIM_NS,%0" :: "r" (value));
+    }
+
+  #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#endif   /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value)    __asm volatile ("BKPT     %0" : : "i"(value))
+
+#if __IAR_M0_FAMILY
+  __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+  {
+    if ((sat >= 1U) && (sat <= 32U))
+    {
+      const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+      const int32_t min = -1 - max ;
+      if (val > max)
+      {
+        return max;
+      }
+      else if (val < min)
+      {
+        return min;
+      }
+    }
+    return val;
+  }
+
+  __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+  {
+    if (sat <= 31U)
+    {
+      const uint32_t max = ((1U << sat) - 1U);
+      if (val > (int32_t)max)
+      {
+        return max;
+      }
+      else if (val < 0)
+      {
+        return 0U;
+      }
+    }
+    return (uint32_t)val;
+  }
+#endif
+
+#if (__CORTEX_M >= 0x03)   /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+  __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
+  {
+    __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
+  {
+    __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
+  {
+    __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+  }
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+
+  __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
+  {
+    __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
+  {
+    __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
+  {
+    __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#undef __IAR_FT
+#undef __IAR_M0_FAMILY
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#endif /* __CMSIS_ICCARM_H__ */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/cmsis_version.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/cmsis_version.h
new file mode 100644
index 00000000..ae3f2e33
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/cmsis_version.h
@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 1U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/core_armv8mbl.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/core_armv8mbl.h
new file mode 100644
index 00000000..ec76ab21
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/core_armv8mbl.h
@@ -0,0 +1,1918 @@
+/**************************************************************************//**
+ * @file     core_armv8mbl.h
+ * @brief    CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File
+ * @version  V5.0.7
+ * @date     22. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MBL_H_GENERIC
+#define __CORE_ARMV8MBL_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_ARMv8MBL
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS definitions */
+#define __ARMv8MBL_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __ARMv8MBL_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __ARMv8MBL_CMSIS_VERSION       ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
+                                         __ARMv8MBL_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                     ( 2U)                                            /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MBL_H_DEPENDANT
+#define __CORE_ARMV8MBL_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __ARMv8MBL_REV
+    #define __ARMv8MBL_REV               0x0000U
+    #warning "__ARMv8MBL_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ETM_PRESENT
+    #define __ETM_PRESENT             0U
+    #warning "__ETM_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MTB_PRESENT
+    #define __MTB_PRESENT             0U
+    #warning "__MTB_PRESENT not defined in device header file; using default!"
+  #endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MBL */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+        uint32_t RESERVED0[6U];
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Sizes Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Sizes Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
+        uint32_t RESERVED3[809U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  Software Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  Software Lock Status Register */
+        uint32_t RESERVED4[4U];
+  __IM  uint32_t TYPE;                   /*!< Offset: 0xFC8 (R/ )  Device Identifier Register */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos              0U                                         /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk             (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)    /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos                0U                                         /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk               (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)        /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos                     1U                                         /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk                    (0x1UL << TPI_LSR_nTT_Pos)                  /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos                     1U                                         /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk                    (0x1UL << TPI_LSR_SLK_Pos)                  /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos                     0U                                         /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk                    (0x1UL /*<< TPI_LSR_SLI_Pos*/)              /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+        uint32_t RESERVED0[7U];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
+#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
+#else
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
+#endif
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/core_armv8mml.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/core_armv8mml.h
new file mode 100644
index 00000000..2d0f1067
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/core_armv8mml.h
@@ -0,0 +1,2927 @@
+/**************************************************************************//**
+ * @file     core_armv8mml.h
+ * @brief    CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File
+ * @version  V5.0.7
+ * @date     06. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MML_H_GENERIC
+#define __CORE_ARMV8MML_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_ARMv8MML
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS Armv8MML definitions */
+#define __ARMv8MML_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __ARMv8MML_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __ARMv8MML_CMSIS_VERSION       ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
+                                         __ARMv8MML_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                     (81U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MML_H_DEPENDANT
+#define __CORE_ARMV8MML_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __ARMv8MML_REV
+    #define __ARMv8MML_REV               0x0000U
+    #warning "__ARMv8MML_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DSP_PRESENT
+    #define __DSP_PRESENT             0U
+    #warning "__DSP_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MML */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */
+    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */
+    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED6[580U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
+        uint32_t RESERVED3[92U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+        uint32_t RESERVED7[6U];
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
+        uint32_t RESERVED6[4U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+        uint32_t RESERVED32[934U];
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+        uint32_t RESERVED33[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Sizes Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Sizes Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
+        uint32_t RESERVED3[809U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  Software Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  Software Lock Status Register */
+        uint32_t RESERVED4[4U];
+  __IM  uint32_t TYPE;                   /*!< Offset: 0xFC8 (R/ )  Device Identifier Register */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos              0U                                         /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk             (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)    /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos                0U                                         /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk               (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)        /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos                     1U                                         /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk                    (0x1UL << TPI_LSR_nTT_Pos)                  /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos                     1U                                         /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk                    (0x1UL << TPI_LSR_SLK_Pos)                  /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos                     0U                                         /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk                    (0x1UL /*<< TPI_LSR_SLI_Pos*/)              /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
+  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
+  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
+  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
+        uint32_t RESERVED0[1];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#else
+        uint32_t RESERVED0[3];
+#endif
+  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
+  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
+  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
+  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
+#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
+#else
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
+#endif
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Priority Grouping (non-secure)
+  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB_NS->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB_NS->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping (non-secure)
+  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/core_cm0.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/core_cm0.h
new file mode 100644
index 00000000..6f82227c
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/core_cm0.h
@@ -0,0 +1,949 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V5.0.5
+ * @date     28. May 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M0
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM0_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (0U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000U
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+        uint32_t RESERVED0;
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           Address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/core_cm0plus.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/core_cm0plus.h
new file mode 100644
index 00000000..b9377e8c
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/core_cm0plus.h
@@ -0,0 +1,1083 @@
+/**************************************************************************//**
+ * @file     core_cm0plus.h
+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version  V5.0.6
+ * @date     28. May 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex-M0+
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM0+ definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB  (__CM_CMSIS_VERSION_SUB)                   /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
+                                       __CM0PLUS_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                   (0U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0PLUS_REV
+    #define __CM0PLUS_REV             0x0000U
+    #warning "__CM0PLUS_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 8U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0+ header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0+ */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+    uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/core_cm1.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/core_cm1.h
new file mode 100644
index 00000000..fd1c4077
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/core_cm1.h
@@ -0,0 +1,976 @@
+/**************************************************************************//**
+ * @file     core_cm1.h
+ * @brief    CMSIS Cortex-M1 Core Peripheral Access Layer Header File
+ * @version  V1.0.0
+ * @date     23. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM1_H_GENERIC
+#define __CORE_CM1_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M1
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM1 definitions */
+#define __CM1_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM1_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM1_CMSIS_VERSION       ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM1_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (1U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM1_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM1_H_DEPENDANT
+#define __CORE_CM1_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM1_REV
+    #define __CM1_REV               0x0100U
+    #warning "__CM1_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M1 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+        uint32_t RESERVED0;
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_ITCMUAEN_Pos            4U                                        /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMUAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos)         /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
+
+#define SCnSCB_ACTLR_ITCMLAEN_Pos            3U                                        /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMLAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos)         /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M1 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M1 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           Address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM1_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/core_cm23.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/core_cm23.h
new file mode 100644
index 00000000..8202a8dd
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/core_cm23.h
@@ -0,0 +1,1993 @@
+/**************************************************************************//**
+ * @file     core_cm23.h
+ * @brief    CMSIS Cortex-M23 Core Peripheral Access Layer Header File
+ * @version  V5.0.7
+ * @date     22. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM23_H_GENERIC
+#define __CORE_CM23_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M23
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS definitions */
+#define __CM23_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM23_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM23_CMSIS_VERSION       ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
+                                     __CM23_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                 (23U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM23_H_DEPENDANT
+#define __CORE_CM23_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM23_REV
+    #define __CM23_REV                0x0000U
+    #warning "__CM23_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ETM_PRESENT
+    #define __ETM_PRESENT             0U
+    #warning "__ETM_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MTB_PRESENT
+    #define __MTB_PRESENT             0U
+    #warning "__MTB_PRESENT not defined in device header file; using default!"
+  #endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M23 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+        uint32_t RESERVED0[6U];
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t ITFTTD0;                /*!< Offset: 0xEEC (R/ )  Integration Test FIFO Test Data 0 Register */
+  __IOM uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/W)  Integration Test ATB Control Register 2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  Integration Test ATB Control Register 0 */
+  __IM  uint32_t ITFTTD1;                /*!< Offset: 0xEFC (R/ )  Integration Test FIFO Test Data 1 Register */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  Device Configuration Register */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos      16U                                         /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos       8U                                         /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos       0U                                          /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk      (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)      /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)      /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos      16U                                         /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos       8U                                         /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos       0U                                          /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk      (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)      /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)      /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+        uint32_t RESERVED0[7U];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M23 */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M23 */
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */ 
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
+#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
+#else 
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
+#endif
+
+	
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/core_cm3.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/core_cm3.h
new file mode 100644
index 00000000..b0dfbd3d
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/core_cm3.h
@@ -0,0 +1,1941 @@
+/**************************************************************************//**
+ * @file     core_cm3.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version  V5.0.8
+ * @date     04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M3
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM3_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (3U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM3_REV
+    #define __CM3_REV               0x0200U
+    #warning "__CM3_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if defined (__CM3_REV) && (__CM3_REV < 0x0201U)                   /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+#else
+        uint32_t RESERVED1[1U];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) );               /* Insert write key and priority group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/core_cm33.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/core_cm33.h
new file mode 100644
index 00000000..02f82e29
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/core_cm33.h
@@ -0,0 +1,3002 @@
+/**************************************************************************//**
+ * @file     core_cm33.h
+ * @brief    CMSIS Cortex-M33 Core Peripheral Access Layer Header File
+ * @version  V5.0.9
+ * @date     06. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM33_H_GENERIC
+#define __CORE_CM33_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M33
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS CM33 definitions */
+#define __CM33_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM33_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM33_CMSIS_VERSION       ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
+                                     __CM33_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                 (33U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined (__TARGET_FPU_VFP)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined (__ARM_PCS_VFP)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined (__ARMVFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined (__TI_VFP_SUPPORT__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined (__FPU_VFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM33_H_DEPENDANT
+#define __CORE_CM33_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM33_REV
+    #define __CM33_REV                0x0000U
+    #warning "__CM33_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DSP_PRESENT
+    #define __DSP_PRESENT             0U
+    #warning "__DSP_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M33 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */
+    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */
+    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED6[580U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
+        uint32_t RESERVED3[92U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+        uint32_t RESERVED7[6U];
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
+        uint32_t RESERVED6[4U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+        uint32_t RESERVED32[934U];
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+        uint32_t RESERVED33[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t ITFTTD0;                /*!< Offset: 0xEEC (R/ )  Integration Test FIFO Test Data 0 Register */
+  __IOM uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/W)  Integration Test ATB Control Register 2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  Integration Test ATB Control Register 0 */
+  __IM  uint32_t ITFTTD1;                /*!< Offset: 0xEFC (R/ )  Integration Test FIFO Test Data 1 Register */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  Device Configuration Register */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos      16U                                         /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos       8U                                         /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos       0U                                          /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk      (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)      /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)      /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos      16U                                         /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos       8U                                         /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos       0U                                          /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk      (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)      /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)      /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
+  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
+  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
+  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
+        uint32_t RESERVED0[1];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#else
+        uint32_t RESERVED0[3];
+#endif
+  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
+  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
+  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
+  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */ 
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
+#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
+#else 
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
+#endif
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priority group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Priority Grouping (non-secure)
+  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB_NS->AIRCR;                                                /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
+  SCB_NS->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping (non-secure)
+  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/core_cm4.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/core_cm4.h
new file mode 100644
index 00000000..308b8681
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/core_cm4.h
@@ -0,0 +1,2129 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V5.0.8
+ * @date     04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M4
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM4_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (4U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000U
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
+#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+#define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after return, restore floating-point state  */
+#define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after return, restore floating-point state  */
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/core_cm7.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/core_cm7.h
new file mode 100644
index 00000000..ada6c2a5
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/core_cm7.h
@@ -0,0 +1,2671 @@
+/**************************************************************************//**
+ * @file     core_cm7.h
+ * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File
+ * @version  V5.0.8
+ * @date     04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM7_H_GENERIC
+#define __CORE_CM7_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M7
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM7 definitions */
+#define __CM7_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM7_CMSIS_VERSION_SUB   ( __CM_CMSIS_VERSION_SUB)                  /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM7_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (7U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM7_H_DEPENDANT
+#define __CORE_CM7_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM7_REV
+    #define __CM7_REV               0x0000U
+    #warning "__CM7_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ICACHE_PRESENT
+    #define __ICACHE_PRESENT          0U
+    #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DCACHE_PRESENT
+    #define __DCACHE_PRESENT          0U
+    #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DTCM_PRESENT
+    #define __DTCM_PRESENT            0U
+    #warning "__DTCM_PRESENT        not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M7 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MFR[4U];             /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[5U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+        uint32_t RESERVED3[93U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+        uint32_t RESERVED7[6U];
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                      18U                                           /*!< SCB CCR: Branch prediction enable bit Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: Branch prediction enable bit Mask */
+
+#define SCB_CCR_IC_Pos                      17U                                           /*!< SCB CCR: Instruction cache enable bit Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: Instruction cache enable bit Mask */
+
+#define SCB_CCR_DC_Pos                      16U                                           /*!< SCB CCR: Cache enable bit Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: Cache enable bit Mask */
+
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12U                                         /*!< ACTLR: DISITMATBFLUSH Position */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define SCnSCB_ACTLR_DISRAMODE_Pos         11U                                         /*!< ACTLR: DISRAMODE Position */
+#define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: DISRAMODE Mask */
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos         10U                                         /*!< ACTLR: FPEXCODIS Position */
+#define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: FPEXCODIS Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED3[981U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 (  W)  Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
+#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+#define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after return, restore floating-point state  */
+#define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after return, restore floating-point state  */
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)IRQn)]                = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]                >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = SCB->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################  Cache functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_CacheFunctions Cache Functions
+  \brief    Functions that configure Instruction and Data cache.
+  @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )
+
+
+/**
+  \brief   Enable I-Cache
+  \details Turns on I-Cache
+  */
+__STATIC_INLINE void SCB_EnableICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+    __DSB();
+    __ISB();
+    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Disable I-Cache
+  \details Turns off I-Cache
+  */
+__STATIC_INLINE void SCB_DisableICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  /* disable I-Cache */
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Invalidate I-Cache
+  \details Invalidates I-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Enable D-Cache
+  \details Turns on D-Cache
+  */
+__STATIC_INLINE void SCB_EnableDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+    __DSB();
+
+    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Disable D-Cache
+  \details Turns off D-Cache
+  */
+__STATIC_INLINE void SCB_DisableDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  /* disable D-Cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean & invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Invalidate D-Cache
+  \details Invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Clean D-Cache
+  \details Cleans D-Cache
+  */
+__STATIC_INLINE void SCB_CleanDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+     SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+   __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
+                      ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Clean & Invalidate D-Cache
+  \details Cleans and Invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean & invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Invalidate by address
+  \details Invalidates D-Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+     int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t)addr;
+     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCIMVAC = op_addr;
+      op_addr += (uint32_t)linesize;
+      op_size -=           linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Clean by address
+  \details Cleans D-Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+     int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t) addr;
+     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCCMVAC = op_addr;
+      op_addr += (uint32_t)linesize;
+      op_size -=           linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Clean and Invalidate by address
+  \details Cleans and invalidates D_Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+     int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t) addr;
+     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCCIMVAC = op_addr;
+      op_addr += (uint32_t)linesize;
+      op_size -=           linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/core_sc000.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/core_sc000.h
new file mode 100644
index 00000000..9086c642
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/core_sc000.h
@@ -0,0 +1,1022 @@
+/**************************************************************************//**
+ * @file     core_sc000.h
+ * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version  V5.0.5
+ * @date     28. May 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup SC000
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                 /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
+                                      __SC000_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_SC                 (000U)                                   /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC000_REV
+    #define __SC000_REV             0x0000U
+    #warning "__SC000_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+        uint32_t RESERVED1[154U];
+  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the SC000 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for SC000 */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for SC000 */
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for SC000 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/core_sc300.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/core_sc300.h
new file mode 100644
index 00000000..665822da
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/core_sc300.h
@@ -0,0 +1,1915 @@
+/**************************************************************************//**
+ * @file     core_sc300.h
+ * @brief    CMSIS SC300 Core Peripheral Access Layer Header File
+ * @version  V5.0.6
+ * @date     04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup SC3000
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                 /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
+                                      __SC300_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_SC                 (300U)                                   /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC300_H_DEPENDANT
+#define __CORE_SC300_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC300_REV
+    #define __SC300_REV               0x0000U
+    #warning "__SC300_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+        uint32_t RESERVED1[129U];
+  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+        uint32_t RESERVED1[1U];
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/mpu_armv7.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/mpu_armv7.h
new file mode 100644
index 00000000..7d4b600c
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/mpu_armv7.h
@@ -0,0 +1,270 @@
+/******************************************************************************
+ * @file     mpu_armv7.h
+ * @brief    CMSIS MPU API for Armv7-M MPU
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+ 
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
+#define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
+#define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
+#define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
+#define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
+#define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
+#define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
+#define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
+#define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
+#define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
+#define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
+#define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
+#define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
+#define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
+#define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
+#define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
+#define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
+#define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
+#define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
+#define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
+#define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
+#define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
+#define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
+#define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
+#define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
+#define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
+#define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
+#define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
+
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
+#define ARM_MPU_AP_URO  2U ///!< MPU Access Permission unprivileged access read-only
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
+#define ARM_MPU_AP_PRO  5U ///!< MPU Access Permission privileged access read-only
+#define ARM_MPU_AP_RO   6U ///!< MPU Access Permission read-only access
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+  (((BaseAddress) & MPU_RBAR_ADDR_Msk) |  \
+   ((Region) & MPU_RBAR_REGION_Msk)    |  \
+   (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Memory Access Attributes
+* 
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+*/  
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)   \
+  ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk)                 | \
+   (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk)                      | \
+   (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk)                      | \
+   (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param AccessAttributes  Memory access attribution, see \ref ARM_MPU_ACCESS_.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)      \
+  ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk)                                          | \
+   (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)                                      | \
+   (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
+  
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/                         
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+  ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
+
+/**
+* MPU Memory Access Attribute for strongly ordered memory.
+*  - TEX: 000b
+*  - Shareable
+*  - Non-cacheable
+*  - Non-bufferable
+*/ 
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
+
+/**
+* MPU Memory Access Attribute for device memory.
+*  - TEX: 000b (if non-shareable) or 010b (if shareable)
+*  - Shareable or non-shareable
+*  - Non-cacheable
+*  - Bufferable (if shareable) or non-bufferable (if non-shareable)
+*
+* \param IsShareable Configures the device memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
+
+/**
+* MPU Memory Access Attribute for normal memory.
+*  - TEX: 1BBb (reflecting outer cacheability rules)
+*  - Shareable or non-shareable
+*  - Cacheable or non-cacheable (reflecting inner cacheability rules)
+*  - Bufferable or non-bufferable (reflecting inner cacheability rules)
+*
+* \param OuterCp Configures the outer cache policy.
+* \param InnerCp Configures the inner cache policy.
+* \param IsShareable Configures the memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
+
+/**
+* MPU Memory Access Attribute non-cacheable policy.
+*/
+#define ARM_MPU_CACHEP_NOCACHE 0U
+
+/**
+* MPU Memory Access Attribute write-back, write and read allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_WRA 1U
+
+/**
+* MPU Memory Access Attribute write-through, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WT_NWA 2U
+
+/**
+* MPU Memory Access Attribute write-back, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_NWA 3U
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR; //!< The region base address register value (RBAR)
+  uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  MPU->RNR = rnr;
+  MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+  MPU->RNR = rnr;
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  while (cnt > MPU_TYPE_RALIASES) {
+    orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+    table += MPU_TYPE_RALIASES;
+    cnt -= MPU_TYPE_RALIASES;
+  }
+  orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/mpu_armv8.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/mpu_armv8.h
new file mode 100644
index 00000000..99ee9f99
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/mpu_armv8.h
@@ -0,0 +1,333 @@
+/******************************************************************************
+ * @file     mpu_armv8.h
+ * @brief    CMSIS MPU API for Armv8-M MPU
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV8_H
+#define ARM_MPU_ARMV8_H
+
+/** \brief Attribute for device memory (outer only) */
+#define ARM_MPU_ATTR_DEVICE                           ( 0U )
+
+/** \brief Attribute for non-cacheable, normal memory */
+#define ARM_MPU_ATTR_NON_CACHEABLE                    ( 4U )
+
+/** \brief Attribute for normal memory (outer and inner)
+* \param NT Non-Transient: Set to 1 for non-transient data.
+* \param WB Write-Back: Set to 1 to use write-back update policy.
+* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
+* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
+*/
+#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
+  (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
+
+/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
+
+/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRE  (1U)
+
+/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGRE   (2U)
+
+/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_GRE    (3U)
+
+/** \brief Memory Attribute
+* \param O Outer memory attributes
+* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
+*/
+#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
+
+/** \brief Normal memory non-shareable  */
+#define ARM_MPU_SH_NON   (0U)
+
+/** \brief Normal memory outer shareable  */
+#define ARM_MPU_SH_OUTER (2U)
+
+/** \brief Normal memory inner shareable  */
+#define ARM_MPU_SH_INNER (3U)
+
+/** \brief Memory access permissions
+* \param RO Read-Only: Set to 1 for read-only memory.
+* \param NP Non-Privileged: Set to 1 for non-privileged memory.
+*/
+#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
+
+/** \brief Region Base Address Register value
+* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
+* \param SH Defines the Shareability domain for this memory region.
+* \param RO Read-Only: Set to 1 for a read-only memory region.
+* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
+* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
+*/
+#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
+  ((BASE & MPU_RBAR_BASE_Msk) | \
+  ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
+  ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
+  ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
+
+/** \brief Region Limit Address Register value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR(LIMIT, IDX) \
+  ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
+  ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+  (MPU_RLAR_EN_Msk))
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR;                   /*!< Region Base Address Register value */
+  uint32_t RLAR;                   /*!< Region Limit Address Register value */
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+#ifdef MPU_NS
+/** Enable the Non-secure MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the Non-secure MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable_NS(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU_NS->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+#endif
+
+/** Set the memory attribute encoding to the given MPU.
+* \param mpu Pointer to the MPU to be configured.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
+{
+  const uint8_t reg = idx / 4U;
+  const uint32_t pos = ((idx % 4U) * 8U);
+  const uint32_t mask = 0xFFU << pos;
+  
+  if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
+    return; // invalid index
+  }
+  
+  mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
+}
+
+/** Set the memory attribute encoding.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU, idx, attr);
+}
+
+#ifdef MPU_NS
+/** Set the memory attribute encoding to the Non-secure MPU.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
+}
+#endif
+
+/** Clear and disable the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
+{
+  mpu->RNR = rnr;
+  mpu->RLAR = 0U;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  ARM_MPU_ClrRegionEx(MPU, rnr);
+}
+
+#ifdef MPU_NS
+/** Clear and disable the given Non-secure MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
+{  
+  ARM_MPU_ClrRegionEx(MPU_NS, rnr);
+}
+#endif
+
+/** Configure the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  mpu->RNR = rnr;
+  mpu->RBAR = rbar;
+  mpu->RLAR = rlar;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
+}
+
+#ifdef MPU_NS
+/** Configure the given Non-secure MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);  
+}
+#endif
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table to the given MPU.
+* \param mpu Pointer to the MPU registers to be used.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  if (cnt == 1U) {
+    mpu->RNR = rnr;
+    orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
+  } else {
+    uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);
+    uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
+    
+    mpu->RNR = rnrBase;
+    while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
+      uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
+      orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
+      table += c;
+      cnt -= c;
+      rnrOffset = 0U;
+      rnrBase += MPU_TYPE_RALIASES;
+      mpu->RNR = rnrBase;
+    }
+    
+    orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU, rnr, table, cnt);
+}
+
+#ifdef MPU_NS
+/** Load the given number of MPU regions from a table to the Non-secure MPU.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
+}
+#endif
+
+#endif
+
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/tz_context.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/tz_context.h
new file mode 100644
index 00000000..d4c1474f
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/CMSIS/Include/tz_context.h
@@ -0,0 +1,70 @@
+/******************************************************************************
+ * @file     tz_context.h
+ * @brief    Context Management for Armv8-M TrustZone
+ * @version  V1.0.1
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef TZ_CONTEXT_H
+#define TZ_CONTEXT_H
+ 
+#include <stdint.h>
+ 
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+ 
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+  
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+ 
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in]  module   identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0    no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+ 
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+ 
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+ 
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+ 
+#endif  // TZ_CONTEXT_H
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
new file mode 100644
index 00000000..7b859e37
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
@@ -0,0 +1,3775 @@
+/**
+  ******************************************************************************
+  * @file    stm32_hal_legacy.h
+  * @author  MCD Application Team
+  * @brief   This file contains aliases definition for the STM32Cube HAL constants
+  *          macros and functions maintained for legacy purpose.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32_HAL_LEGACY
+#define STM32_HAL_LEGACY
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define AES_FLAG_RDERR                  CRYP_FLAG_RDERR
+#define AES_FLAG_WRERR                  CRYP_FLAG_WRERR
+#define AES_CLEARFLAG_CCF               CRYP_CLEARFLAG_CCF
+#define AES_CLEARFLAG_RDERR             CRYP_CLEARFLAG_RDERR
+#define AES_CLEARFLAG_WRERR             CRYP_CLEARFLAG_WRERR
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define ADC_RESOLUTION12b               ADC_RESOLUTION_12B
+#define ADC_RESOLUTION10b               ADC_RESOLUTION_10B
+#define ADC_RESOLUTION8b                ADC_RESOLUTION_8B
+#define ADC_RESOLUTION6b                ADC_RESOLUTION_6B
+#define OVR_DATA_OVERWRITTEN            ADC_OVR_DATA_OVERWRITTEN
+#define OVR_DATA_PRESERVED              ADC_OVR_DATA_PRESERVED
+#define EOC_SINGLE_CONV                 ADC_EOC_SINGLE_CONV
+#define EOC_SEQ_CONV                    ADC_EOC_SEQ_CONV
+#define EOC_SINGLE_SEQ_CONV             ADC_EOC_SINGLE_SEQ_CONV
+#define REGULAR_GROUP                   ADC_REGULAR_GROUP
+#define INJECTED_GROUP                  ADC_INJECTED_GROUP
+#define REGULAR_INJECTED_GROUP          ADC_REGULAR_INJECTED_GROUP
+#define AWD_EVENT                       ADC_AWD_EVENT
+#define AWD1_EVENT                      ADC_AWD1_EVENT
+#define AWD2_EVENT                      ADC_AWD2_EVENT
+#define AWD3_EVENT                      ADC_AWD3_EVENT
+#define OVR_EVENT                       ADC_OVR_EVENT
+#define JQOVF_EVENT                     ADC_JQOVF_EVENT
+#define ALL_CHANNELS                    ADC_ALL_CHANNELS
+#define REGULAR_CHANNELS                ADC_REGULAR_CHANNELS
+#define INJECTED_CHANNELS               ADC_INJECTED_CHANNELS
+#define SYSCFG_FLAG_SENSOR_ADC          ADC_FLAG_SENSOR
+#define SYSCFG_FLAG_VREF_ADC            ADC_FLAG_VREFINT
+#define ADC_CLOCKPRESCALER_PCLK_DIV1    ADC_CLOCK_SYNC_PCLK_DIV1
+#define ADC_CLOCKPRESCALER_PCLK_DIV2    ADC_CLOCK_SYNC_PCLK_DIV2
+#define ADC_CLOCKPRESCALER_PCLK_DIV4    ADC_CLOCK_SYNC_PCLK_DIV4
+#define ADC_CLOCKPRESCALER_PCLK_DIV6    ADC_CLOCK_SYNC_PCLK_DIV6
+#define ADC_CLOCKPRESCALER_PCLK_DIV8    ADC_CLOCK_SYNC_PCLK_DIV8
+#define ADC_EXTERNALTRIG0_T6_TRGO       ADC_EXTERNALTRIGCONV_T6_TRGO
+#define ADC_EXTERNALTRIG1_T21_CC2       ADC_EXTERNALTRIGCONV_T21_CC2
+#define ADC_EXTERNALTRIG2_T2_TRGO       ADC_EXTERNALTRIGCONV_T2_TRGO
+#define ADC_EXTERNALTRIG3_T2_CC4        ADC_EXTERNALTRIGCONV_T2_CC4
+#define ADC_EXTERNALTRIG4_T22_TRGO      ADC_EXTERNALTRIGCONV_T22_TRGO
+#define ADC_EXTERNALTRIG7_EXT_IT11      ADC_EXTERNALTRIGCONV_EXT_IT11
+#define ADC_CLOCK_ASYNC                 ADC_CLOCK_ASYNC_DIV1
+#define ADC_EXTERNALTRIG_EDGE_NONE      ADC_EXTERNALTRIGCONVEDGE_NONE
+#define ADC_EXTERNALTRIG_EDGE_RISING    ADC_EXTERNALTRIGCONVEDGE_RISING
+#define ADC_EXTERNALTRIG_EDGE_FALLING   ADC_EXTERNALTRIGCONVEDGE_FALLING
+#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
+#define ADC_SAMPLETIME_2CYCLE_5         ADC_SAMPLETIME_2CYCLES_5
+
+#define HAL_ADC_STATE_BUSY_REG          HAL_ADC_STATE_REG_BUSY
+#define HAL_ADC_STATE_BUSY_INJ          HAL_ADC_STATE_INJ_BUSY
+#define HAL_ADC_STATE_EOC_REG           HAL_ADC_STATE_REG_EOC
+#define HAL_ADC_STATE_EOC_INJ           HAL_ADC_STATE_INJ_EOC
+#define HAL_ADC_STATE_ERROR             HAL_ADC_STATE_ERROR_INTERNAL
+#define HAL_ADC_STATE_BUSY              HAL_ADC_STATE_BUSY_INTERNAL
+#define HAL_ADC_STATE_AWD               HAL_ADC_STATE_AWD1
+
+#if defined(STM32H7)
+#define ADC_CHANNEL_VBAT_DIV4           ADC_CHANNEL_VBAT
+#endif /* STM32H7 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define COMP_WINDOWMODE_DISABLED       COMP_WINDOWMODE_DISABLE
+#define COMP_WINDOWMODE_ENABLED        COMP_WINDOWMODE_ENABLE
+#define COMP_EXTI_LINE_COMP1_EVENT     COMP_EXTI_LINE_COMP1
+#define COMP_EXTI_LINE_COMP2_EVENT     COMP_EXTI_LINE_COMP2
+#define COMP_EXTI_LINE_COMP3_EVENT     COMP_EXTI_LINE_COMP3
+#define COMP_EXTI_LINE_COMP4_EVENT     COMP_EXTI_LINE_COMP4
+#define COMP_EXTI_LINE_COMP5_EVENT     COMP_EXTI_LINE_COMP5
+#define COMP_EXTI_LINE_COMP6_EVENT     COMP_EXTI_LINE_COMP6
+#define COMP_EXTI_LINE_COMP7_EVENT     COMP_EXTI_LINE_COMP7
+#if defined(STM32L0)
+#define COMP_LPTIMCONNECTION_ENABLED   ((uint32_t)0x00000003U)    /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
+#endif
+#define COMP_OUTPUT_COMP6TIM2OCREFCLR  COMP_OUTPUT_COMP6_TIM2OCREFCLR
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define COMP_OUTPUT_TIM3IC1            COMP_OUTPUT_COMP1_TIM3IC1
+#define COMP_OUTPUT_TIM3OCREFCLR       COMP_OUTPUT_COMP1_TIM3OCREFCLR
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32L0) || defined(STM32L4)
+#define COMP_WINDOWMODE_ENABLE         COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
+
+#define COMP_NONINVERTINGINPUT_IO1      COMP_INPUT_PLUS_IO1
+#define COMP_NONINVERTINGINPUT_IO2      COMP_INPUT_PLUS_IO2
+#define COMP_NONINVERTINGINPUT_IO3      COMP_INPUT_PLUS_IO3
+#define COMP_NONINVERTINGINPUT_IO4      COMP_INPUT_PLUS_IO4
+#define COMP_NONINVERTINGINPUT_IO5      COMP_INPUT_PLUS_IO5
+#define COMP_NONINVERTINGINPUT_IO6      COMP_INPUT_PLUS_IO6
+
+#define COMP_INVERTINGINPUT_1_4VREFINT  COMP_INPUT_MINUS_1_4VREFINT
+#define COMP_INVERTINGINPUT_1_2VREFINT  COMP_INPUT_MINUS_1_2VREFINT
+#define COMP_INVERTINGINPUT_3_4VREFINT  COMP_INPUT_MINUS_3_4VREFINT
+#define COMP_INVERTINGINPUT_VREFINT     COMP_INPUT_MINUS_VREFINT
+#define COMP_INVERTINGINPUT_DAC1_CH1    COMP_INPUT_MINUS_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC1_CH2    COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_DAC1        COMP_INPUT_MINUS_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC2        COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_IO1         COMP_INPUT_MINUS_IO1
+#if defined(STM32L0)
+/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2),     */
+/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding   */
+/* to the second dedicated IO (only for COMP2).                               */
+#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO2
+#else
+#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_IO2
+#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO3
+#endif
+#define COMP_INVERTINGINPUT_IO4         COMP_INPUT_MINUS_IO4
+#define COMP_INVERTINGINPUT_IO5         COMP_INPUT_MINUS_IO5
+
+#define COMP_OUTPUTLEVEL_LOW            COMP_OUTPUT_LEVEL_LOW
+#define COMP_OUTPUTLEVEL_HIGH           COMP_OUTPUT_LEVEL_HIGH
+
+/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose.                    */
+/*       To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()".        */
+#if defined(COMP_CSR_LOCK)
+#define COMP_FLAG_LOCK                 COMP_CSR_LOCK
+#elif defined(COMP_CSR_COMP1LOCK)
+#define COMP_FLAG_LOCK                 COMP_CSR_COMP1LOCK
+#elif defined(COMP_CSR_COMPxLOCK)
+#define COMP_FLAG_LOCK                 COMP_CSR_COMPxLOCK
+#endif
+
+#if defined(STM32L4)
+#define COMP_BLANKINGSRCE_TIM1OC5        COMP_BLANKINGSRC_TIM1_OC5_COMP1
+#define COMP_BLANKINGSRCE_TIM2OC3        COMP_BLANKINGSRC_TIM2_OC3_COMP1
+#define COMP_BLANKINGSRCE_TIM3OC3        COMP_BLANKINGSRC_TIM3_OC3_COMP1
+#define COMP_BLANKINGSRCE_TIM3OC4        COMP_BLANKINGSRC_TIM3_OC4_COMP2
+#define COMP_BLANKINGSRCE_TIM8OC5        COMP_BLANKINGSRC_TIM8_OC5_COMP2
+#define COMP_BLANKINGSRCE_TIM15OC1       COMP_BLANKINGSRC_TIM15_OC1_COMP2
+#define COMP_BLANKINGSRCE_NONE           COMP_BLANKINGSRC_NONE
+#endif
+
+#if defined(STM32L0)
+#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_MEDIUMSPEED
+#define COMP_MODE_LOWSPEED               COMP_POWERMODE_ULTRALOWPOWER
+#else
+#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_HIGHSPEED
+#define COMP_MODE_MEDIUMSPEED            COMP_POWERMODE_MEDIUMSPEED
+#define COMP_MODE_LOWPOWER               COMP_POWERMODE_LOWPOWER
+#define COMP_MODE_ULTRALOWPOWER          COMP_POWERMODE_ULTRALOWPOWER
+#endif
+
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
+/**
+  * @}
+  */
+
+/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define CRC_OUTPUTDATA_INVERSION_DISABLED    CRC_OUTPUTDATA_INVERSION_DISABLE
+#define CRC_OUTPUTDATA_INVERSION_ENABLED     CRC_OUTPUTDATA_INVERSION_ENABLE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define DAC1_CHANNEL_1                                  DAC_CHANNEL_1
+#define DAC1_CHANNEL_2                                  DAC_CHANNEL_2
+#define DAC2_CHANNEL_1                                  DAC_CHANNEL_1
+#define DAC_WAVE_NONE                                   0x00000000U
+#define DAC_WAVE_NOISE                                  DAC_CR_WAVE1_0
+#define DAC_WAVE_TRIANGLE                               DAC_CR_WAVE1_1
+#define DAC_WAVEGENERATION_NONE                         DAC_WAVE_NONE
+#define DAC_WAVEGENERATION_NOISE                        DAC_WAVE_NOISE
+#define DAC_WAVEGENERATION_TRIANGLE                     DAC_WAVE_TRIANGLE
+
+#if defined(STM32G4) || defined(STM32H7)
+#define DAC_CHIPCONNECT_DISABLE       DAC_CHIPCONNECT_EXTERNAL
+#define DAC_CHIPCONNECT_ENABLE        DAC_CHIPCONNECT_INTERNAL
+#endif
+
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
+#define HAL_DAC_MSP_INIT_CB_ID       HAL_DAC_MSPINIT_CB_ID
+#define HAL_DAC_MSP_DEINIT_CB_ID     HAL_DAC_MSPDEINIT_CB_ID
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define HAL_REMAPDMA_ADC_DMA_CH2                DMA_REMAP_ADC_DMA_CH2
+#define HAL_REMAPDMA_USART1_TX_DMA_CH4          DMA_REMAP_USART1_TX_DMA_CH4
+#define HAL_REMAPDMA_USART1_RX_DMA_CH5          DMA_REMAP_USART1_RX_DMA_CH5
+#define HAL_REMAPDMA_TIM16_DMA_CH4              DMA_REMAP_TIM16_DMA_CH4
+#define HAL_REMAPDMA_TIM17_DMA_CH2              DMA_REMAP_TIM17_DMA_CH2
+#define HAL_REMAPDMA_USART3_DMA_CH32            DMA_REMAP_USART3_DMA_CH32
+#define HAL_REMAPDMA_TIM16_DMA_CH6              DMA_REMAP_TIM16_DMA_CH6
+#define HAL_REMAPDMA_TIM17_DMA_CH7              DMA_REMAP_TIM17_DMA_CH7
+#define HAL_REMAPDMA_SPI2_DMA_CH67              DMA_REMAP_SPI2_DMA_CH67
+#define HAL_REMAPDMA_USART2_DMA_CH67            DMA_REMAP_USART2_DMA_CH67
+#define HAL_REMAPDMA_I2C1_DMA_CH76              DMA_REMAP_I2C1_DMA_CH76
+#define HAL_REMAPDMA_TIM1_DMA_CH6               DMA_REMAP_TIM1_DMA_CH6
+#define HAL_REMAPDMA_TIM2_DMA_CH7               DMA_REMAP_TIM2_DMA_CH7
+#define HAL_REMAPDMA_TIM3_DMA_CH6               DMA_REMAP_TIM3_DMA_CH6
+
+#define IS_HAL_REMAPDMA                          IS_DMA_REMAP
+#define __HAL_REMAPDMA_CHANNEL_ENABLE            __HAL_DMA_REMAP_CHANNEL_ENABLE
+#define __HAL_REMAPDMA_CHANNEL_DISABLE           __HAL_DMA_REMAP_CHANNEL_DISABLE
+
+#if defined(STM32L4)
+
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI0            HAL_DMAMUX1_REQ_GEN_EXTI0
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI1            HAL_DMAMUX1_REQ_GEN_EXTI1
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI2            HAL_DMAMUX1_REQ_GEN_EXTI2
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI3            HAL_DMAMUX1_REQ_GEN_EXTI3
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI4            HAL_DMAMUX1_REQ_GEN_EXTI4
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI5            HAL_DMAMUX1_REQ_GEN_EXTI5
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI6            HAL_DMAMUX1_REQ_GEN_EXTI6
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI7            HAL_DMAMUX1_REQ_GEN_EXTI7
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI8            HAL_DMAMUX1_REQ_GEN_EXTI8
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI9            HAL_DMAMUX1_REQ_GEN_EXTI9
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI10           HAL_DMAMUX1_REQ_GEN_EXTI10
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI11           HAL_DMAMUX1_REQ_GEN_EXTI11
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI12           HAL_DMAMUX1_REQ_GEN_EXTI12
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI13           HAL_DMAMUX1_REQ_GEN_EXTI13
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI14           HAL_DMAMUX1_REQ_GEN_EXTI14
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI15           HAL_DMAMUX1_REQ_GEN_EXTI15
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT       HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT       HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE           HAL_DMAMUX1_REQ_GEN_DSI_TE
+#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT          HAL_DMAMUX1_REQ_GEN_DSI_EOT
+#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT        HAL_DMAMUX1_REQ_GEN_DMA2D_EOT
+#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT          HAL_DMAMUX1_REQ_GEN_LTDC_IT
+
+#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT          HAL_DMAMUX_REQ_GEN_NO_EVENT
+#define HAL_DMAMUX_REQUEST_GEN_RISING            HAL_DMAMUX_REQ_GEN_RISING
+#define HAL_DMAMUX_REQUEST_GEN_FALLING           HAL_DMAMUX_REQ_GEN_FALLING
+#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING    HAL_DMAMUX_REQ_GEN_RISING_FALLING
+
+#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+#define DMA_REQUEST_DCMI_PSSI                    DMA_REQUEST_DCMI
+#endif
+
+#endif /* STM32L4 */
+
+#if defined(STM32G0)
+#define DMA_REQUEST_DAC1_CHANNEL1                DMA_REQUEST_DAC1_CH1
+#define DMA_REQUEST_DAC1_CHANNEL2                DMA_REQUEST_DAC1_CH2
+#endif
+
+#if defined(STM32H7)
+
+#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
+#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
+
+#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
+#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
+
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI0              HAL_DMAMUX1_REQ_GEN_EXTI0
+#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO         HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
+
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP          HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP          HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT          HAL_DMAMUX2_REQ_GEN_COMP1_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT          HAL_DMAMUX2_REQ_GEN_COMP2_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP           HAL_DMAMUX2_REQ_GEN_RTC_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_EXTI0              HAL_DMAMUX2_REQ_GEN_EXTI0
+#define HAL_DMAMUX2_REQUEST_GEN_EXTI2              HAL_DMAMUX2_REQ_GEN_EXTI2
+#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT        HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT            HAL_DMAMUX2_REQ_GEN_SPI6_IT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
+#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT            HAL_DMAMUX2_REQ_GEN_ADC3_IT
+#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT      HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
+#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
+
+#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT            HAL_DMAMUX_REQ_GEN_NO_EVENT
+#define HAL_DMAMUX_REQUEST_GEN_RISING              HAL_DMAMUX_REQ_GEN_RISING
+#define HAL_DMAMUX_REQUEST_GEN_FALLING             HAL_DMAMUX_REQ_GEN_FALLING
+#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING      HAL_DMAMUX_REQ_GEN_RISING_FALLING
+
+#define DFSDM_FILTER_EXT_TRIG_LPTIM1               DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT
+#define DFSDM_FILTER_EXT_TRIG_LPTIM2               DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
+#define DFSDM_FILTER_EXT_TRIG_LPTIM3               DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
+
+#define DAC_TRIGGER_LP1_OUT                        DAC_TRIGGER_LPTIM1_OUT
+#define DAC_TRIGGER_LP2_OUT                        DAC_TRIGGER_LPTIM2_OUT
+
+#endif /* STM32H7 */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define TYPEPROGRAM_BYTE              FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_HALFWORD          FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_WORD              FLASH_TYPEPROGRAM_WORD
+#define TYPEPROGRAM_DOUBLEWORD        FLASH_TYPEPROGRAM_DOUBLEWORD
+#define TYPEERASE_SECTORS             FLASH_TYPEERASE_SECTORS
+#define TYPEERASE_PAGES               FLASH_TYPEERASE_PAGES
+#define TYPEERASE_PAGEERASE           FLASH_TYPEERASE_PAGES
+#define TYPEERASE_MASSERASE           FLASH_TYPEERASE_MASSERASE
+#define WRPSTATE_DISABLE              OB_WRPSTATE_DISABLE
+#define WRPSTATE_ENABLE               OB_WRPSTATE_ENABLE
+#define HAL_FLASH_TIMEOUT_VALUE       FLASH_TIMEOUT_VALUE
+#define OBEX_PCROP                    OPTIONBYTE_PCROP
+#define OBEX_BOOTCONFIG               OPTIONBYTE_BOOTCONFIG
+#define PCROPSTATE_DISABLE            OB_PCROP_STATE_DISABLE
+#define PCROPSTATE_ENABLE             OB_PCROP_STATE_ENABLE
+#define TYPEERASEDATA_BYTE            FLASH_TYPEERASEDATA_BYTE
+#define TYPEERASEDATA_HALFWORD        FLASH_TYPEERASEDATA_HALFWORD
+#define TYPEERASEDATA_WORD            FLASH_TYPEERASEDATA_WORD
+#define TYPEPROGRAMDATA_BYTE          FLASH_TYPEPROGRAMDATA_BYTE
+#define TYPEPROGRAMDATA_HALFWORD      FLASH_TYPEPROGRAMDATA_HALFWORD
+#define TYPEPROGRAMDATA_WORD          FLASH_TYPEPROGRAMDATA_WORD
+#define TYPEPROGRAMDATA_FASTBYTE      FLASH_TYPEPROGRAMDATA_FASTBYTE
+#define TYPEPROGRAMDATA_FASTHALFWORD  FLASH_TYPEPROGRAMDATA_FASTHALFWORD
+#define TYPEPROGRAMDATA_FASTWORD      FLASH_TYPEPROGRAMDATA_FASTWORD
+#define PAGESIZE                      FLASH_PAGE_SIZE
+#define TYPEPROGRAM_FASTBYTE          FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_FASTHALFWORD      FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_FASTWORD          FLASH_TYPEPROGRAM_WORD
+#define VOLTAGE_RANGE_1               FLASH_VOLTAGE_RANGE_1
+#define VOLTAGE_RANGE_2               FLASH_VOLTAGE_RANGE_2
+#define VOLTAGE_RANGE_3               FLASH_VOLTAGE_RANGE_3
+#define VOLTAGE_RANGE_4               FLASH_VOLTAGE_RANGE_4
+#define TYPEPROGRAM_FAST              FLASH_TYPEPROGRAM_FAST
+#define TYPEPROGRAM_FAST_AND_LAST     FLASH_TYPEPROGRAM_FAST_AND_LAST
+#define WRPAREA_BANK1_AREAA           OB_WRPAREA_BANK1_AREAA
+#define WRPAREA_BANK1_AREAB           OB_WRPAREA_BANK1_AREAB
+#define WRPAREA_BANK2_AREAA           OB_WRPAREA_BANK2_AREAA
+#define WRPAREA_BANK2_AREAB           OB_WRPAREA_BANK2_AREAB
+#define IWDG_STDBY_FREEZE             OB_IWDG_STDBY_FREEZE
+#define IWDG_STDBY_ACTIVE             OB_IWDG_STDBY_RUN
+#define IWDG_STOP_FREEZE              OB_IWDG_STOP_FREEZE
+#define IWDG_STOP_ACTIVE              OB_IWDG_STOP_RUN
+#define FLASH_ERROR_NONE              HAL_FLASH_ERROR_NONE
+#define FLASH_ERROR_RD                HAL_FLASH_ERROR_RD
+#define FLASH_ERROR_PG                HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_PGP               HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_WRP               HAL_FLASH_ERROR_WRP
+#define FLASH_ERROR_OPTV              HAL_FLASH_ERROR_OPTV
+#define FLASH_ERROR_OPTVUSR           HAL_FLASH_ERROR_OPTVUSR
+#define FLASH_ERROR_PROG              HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_OP                HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_PGA               HAL_FLASH_ERROR_PGA
+#define FLASH_ERROR_SIZE              HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_SIZ               HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_PGS               HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_MIS               HAL_FLASH_ERROR_MIS
+#define FLASH_ERROR_FAST              HAL_FLASH_ERROR_FAST
+#define FLASH_ERROR_FWWERR            HAL_FLASH_ERROR_FWWERR
+#define FLASH_ERROR_NOTZERO           HAL_FLASH_ERROR_NOTZERO
+#define FLASH_ERROR_OPERATION         HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_ERS               HAL_FLASH_ERROR_ERS
+#define OB_WDG_SW                     OB_IWDG_SW
+#define OB_WDG_HW                     OB_IWDG_HW
+#define OB_SDADC12_VDD_MONITOR_SET    OB_SDACD_VDD_MONITOR_SET
+#define OB_SDADC12_VDD_MONITOR_RESET  OB_SDACD_VDD_MONITOR_RESET
+#define OB_RAM_PARITY_CHECK_SET       OB_SRAM_PARITY_SET
+#define OB_RAM_PARITY_CHECK_RESET     OB_SRAM_PARITY_RESET
+#define IS_OB_SDADC12_VDD_MONITOR     IS_OB_SDACD_VDD_MONITOR
+#define OB_RDP_LEVEL0                 OB_RDP_LEVEL_0
+#define OB_RDP_LEVEL1                 OB_RDP_LEVEL_1
+#define OB_RDP_LEVEL2                 OB_RDP_LEVEL_2
+#if defined(STM32G0)
+#define OB_BOOT_LOCK_DISABLE          OB_BOOT_ENTRY_FORCED_NONE
+#define OB_BOOT_LOCK_ENABLE           OB_BOOT_ENTRY_FORCED_FLASH
+#else
+#define OB_BOOT_ENTRY_FORCED_NONE     OB_BOOT_LOCK_DISABLE
+#define OB_BOOT_ENTRY_FORCED_FLASH    OB_BOOT_LOCK_ENABLE
+#endif
+#if defined(STM32H7)
+#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1
+#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1
+#define FLASH_FLAG_STRBER_BANK1R  FLASH_FLAG_STRBERR_BANK1
+#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
+#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
+#define FLASH_FLAG_STRBER_BANK2R  FLASH_FLAG_STRBERR_BANK2
+#define FLASH_FLAG_WDW            FLASH_FLAG_WBNE
+#define OB_WRP_SECTOR_All         OB_WRP_SECTOR_ALL
+#endif /* STM32H7 */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#if defined(STM32H7)
+#define __HAL_RCC_JPEG_CLK_ENABLE               __HAL_RCC_JPGDECEN_CLK_ENABLE
+#define __HAL_RCC_JPEG_CLK_DISABLE              __HAL_RCC_JPGDECEN_CLK_DISABLE
+#define __HAL_RCC_JPEG_FORCE_RESET              __HAL_RCC_JPGDECRST_FORCE_RESET
+#define __HAL_RCC_JPEG_RELEASE_RESET            __HAL_RCC_JPGDECRST_RELEASE_RESET
+#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE         __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
+#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE        __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
+#endif /* STM32H7 */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9    I2C_FASTMODEPLUS_PA9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10   I2C_FASTMODEPLUS_PA10
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6    I2C_FASTMODEPLUS_PB6
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7    I2C_FASTMODEPLUS_PB7
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8    I2C_FASTMODEPLUS_PB8
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9    I2C_FASTMODEPLUS_PB9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C1       I2C_FASTMODEPLUS_I2C1
+#define HAL_SYSCFG_FASTMODEPLUS_I2C2       I2C_FASTMODEPLUS_I2C2
+#define HAL_SYSCFG_FASTMODEPLUS_I2C3       I2C_FASTMODEPLUS_I2C3
+#if defined(STM32G4)
+
+#define HAL_SYSCFG_EnableIOAnalogSwitchBooster    HAL_SYSCFG_EnableIOSwitchBooster
+#define HAL_SYSCFG_DisableIOAnalogSwitchBooster   HAL_SYSCFG_DisableIOSwitchBooster
+#define HAL_SYSCFG_EnableIOAnalogSwitchVDD        HAL_SYSCFG_EnableIOSwitchVDD
+#define HAL_SYSCFG_DisableIOAnalogSwitchVDD       HAL_SYSCFG_DisableIOSwitchVDD
+#endif /* STM32G4 */
+/**
+  * @}
+  */
+
+
+/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
+  * @{
+  */
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
+#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE       FMC_NAND_WAIT_FEATURE_DISABLE
+#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE        FMC_NAND_WAIT_FEATURE_ENABLE
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_8            FMC_NAND_MEM_BUS_WIDTH_8
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_16           FMC_NAND_MEM_BUS_WIDTH_16
+#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4)
+#define FMC_NAND_WAIT_FEATURE_DISABLE           FMC_NAND_PCC_WAIT_FEATURE_DISABLE
+#define FMC_NAND_WAIT_FEATURE_ENABLE            FMC_NAND_PCC_WAIT_FEATURE_ENABLE
+#define FMC_NAND_MEM_BUS_WIDTH_8                FMC_NAND_PCC_MEM_BUS_WIDTH_8
+#define FMC_NAND_MEM_BUS_WIDTH_16               FMC_NAND_PCC_MEM_BUS_WIDTH_16
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define FSMC_NORSRAM_TYPEDEF                      FSMC_NORSRAM_TypeDef
+#define FSMC_NORSRAM_EXTENDED_TYPEDEF             FSMC_NORSRAM_EXTENDED_TypeDef
+/**
+  * @}
+  */
+
+/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define GET_GPIO_SOURCE                           GPIO_GET_INDEX
+#define GET_GPIO_INDEX                            GPIO_GET_INDEX
+
+#if defined(STM32F4)
+#define GPIO_AF12_SDMMC                           GPIO_AF12_SDIO
+#define GPIO_AF12_SDMMC1                          GPIO_AF12_SDIO
+#endif
+
+#if defined(STM32F7)
+#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1
+#endif
+
+#if defined(STM32L4)
+#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1
+#endif
+
+#if defined(STM32H7)
+#define GPIO_AF7_SDIO1                            GPIO_AF7_SDMMC1
+#define GPIO_AF8_SDIO1                            GPIO_AF8_SDMMC1
+#define GPIO_AF12_SDIO1                           GPIO_AF12_SDMMC1
+#define GPIO_AF9_SDIO2                            GPIO_AF9_SDMMC2
+#define GPIO_AF10_SDIO2                           GPIO_AF10_SDMMC2
+#define GPIO_AF11_SDIO2                           GPIO_AF11_SDMMC2
+
+#if defined (STM32H743xx) || defined (STM32H753xx)  || defined (STM32H750xx) || defined (STM32H742xx) || \
+    defined (STM32H745xx) || defined (STM32H755xx)  || defined (STM32H747xx) || defined (STM32H757xx)
+#define GPIO_AF10_OTG2_HS  GPIO_AF10_OTG2_FS
+#define GPIO_AF10_OTG1_FS  GPIO_AF10_OTG1_HS
+#define GPIO_AF12_OTG2_FS  GPIO_AF12_OTG1_FS
+#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
+#endif /* STM32H7 */
+
+#define GPIO_AF0_LPTIM                            GPIO_AF0_LPTIM1
+#define GPIO_AF1_LPTIM                            GPIO_AF1_LPTIM1
+#define GPIO_AF2_LPTIM                            GPIO_AF2_LPTIM1
+
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7)
+#define  GPIO_SPEED_LOW                           GPIO_SPEED_FREQ_LOW
+#define  GPIO_SPEED_MEDIUM                        GPIO_SPEED_FREQ_MEDIUM
+#define  GPIO_SPEED_FAST                          GPIO_SPEED_FREQ_HIGH
+#define  GPIO_SPEED_HIGH                          GPIO_SPEED_FREQ_VERY_HIGH
+#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/
+
+#if defined(STM32L1)
+ #define  GPIO_SPEED_VERY_LOW    GPIO_SPEED_FREQ_LOW
+ #define  GPIO_SPEED_LOW         GPIO_SPEED_FREQ_MEDIUM
+ #define  GPIO_SPEED_MEDIUM      GPIO_SPEED_FREQ_HIGH
+ #define  GPIO_SPEED_HIGH        GPIO_SPEED_FREQ_VERY_HIGH
+#endif /* STM32L1 */
+
+#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
+ #define  GPIO_SPEED_LOW    GPIO_SPEED_FREQ_LOW
+ #define  GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
+ #define  GPIO_SPEED_HIGH   GPIO_SPEED_FREQ_HIGH
+#endif /* STM32F0 || STM32F3 || STM32F1 */
+
+#define GPIO_AF6_DFSDM                            GPIO_AF6_DFSDM1
+/**
+  * @}
+  */
+
+/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define HRTIM_TIMDELAYEDPROTECTION_DISABLED           HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
+
+#define __HAL_HRTIM_SetCounter        __HAL_HRTIM_SETCOUNTER
+#define __HAL_HRTIM_GetCounter        __HAL_HRTIM_GETCOUNTER
+#define __HAL_HRTIM_SetPeriod         __HAL_HRTIM_SETPERIOD
+#define __HAL_HRTIM_GetPeriod         __HAL_HRTIM_GETPERIOD
+#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
+#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
+#define __HAL_HRTIM_SetCompare        __HAL_HRTIM_SETCOMPARE
+#define __HAL_HRTIM_GetCompare        __HAL_HRTIM_GETCOMPARE
+
+#if defined(STM32G4)
+#define HAL_HRTIM_ExternalEventCounterConfig    HAL_HRTIM_ExtEventCounterConfig
+#define HAL_HRTIM_ExternalEventCounterEnable    HAL_HRTIM_ExtEventCounterEnable
+#define HAL_HRTIM_ExternalEventCounterDisable   HAL_HRTIM_ExtEventCounterDisable
+#define HAL_HRTIM_ExternalEventCounterReset     HAL_HRTIM_ExtEventCounterReset
+#endif /* STM32G4 */
+
+#if defined(STM32H7)
+#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
+
+#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
+#endif /* STM32H7 */
+
+#if defined(STM32F3)
+/** @brief Constants defining available sources associated to external events.
+  */
+#define HRTIM_EVENTSRC_1              (0x00000000U)
+#define HRTIM_EVENTSRC_2              (HRTIM_EECR1_EE1SRC_0)
+#define HRTIM_EVENTSRC_3              (HRTIM_EECR1_EE1SRC_1)
+#define HRTIM_EVENTSRC_4              (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
+
+/** @brief Constants defining the events that can be selected to configure the
+  *        set/reset crossbar of a timer output
+  */
+#define HRTIM_OUTPUTSET_TIMEV_1       (HRTIM_SET1R_TIMEVNT1)
+#define HRTIM_OUTPUTSET_TIMEV_2       (HRTIM_SET1R_TIMEVNT2)
+#define HRTIM_OUTPUTSET_TIMEV_3       (HRTIM_SET1R_TIMEVNT3)
+#define HRTIM_OUTPUTSET_TIMEV_4       (HRTIM_SET1R_TIMEVNT4)
+#define HRTIM_OUTPUTSET_TIMEV_5       (HRTIM_SET1R_TIMEVNT5)
+#define HRTIM_OUTPUTSET_TIMEV_6       (HRTIM_SET1R_TIMEVNT6)
+#define HRTIM_OUTPUTSET_TIMEV_7       (HRTIM_SET1R_TIMEVNT7)
+#define HRTIM_OUTPUTSET_TIMEV_8       (HRTIM_SET1R_TIMEVNT8)
+#define HRTIM_OUTPUTSET_TIMEV_9       (HRTIM_SET1R_TIMEVNT9)
+
+#define HRTIM_OUTPUTRESET_TIMEV_1     (HRTIM_RST1R_TIMEVNT1)
+#define HRTIM_OUTPUTRESET_TIMEV_2     (HRTIM_RST1R_TIMEVNT2)
+#define HRTIM_OUTPUTRESET_TIMEV_3     (HRTIM_RST1R_TIMEVNT3)
+#define HRTIM_OUTPUTRESET_TIMEV_4     (HRTIM_RST1R_TIMEVNT4)
+#define HRTIM_OUTPUTRESET_TIMEV_5     (HRTIM_RST1R_TIMEVNT5)
+#define HRTIM_OUTPUTRESET_TIMEV_6     (HRTIM_RST1R_TIMEVNT6)
+#define HRTIM_OUTPUTRESET_TIMEV_7     (HRTIM_RST1R_TIMEVNT7)
+#define HRTIM_OUTPUTRESET_TIMEV_8     (HRTIM_RST1R_TIMEVNT8)
+#define HRTIM_OUTPUTRESET_TIMEV_9     (HRTIM_RST1R_TIMEVNT9)
+
+/** @brief Constants defining the event filtering applied to external events
+  *        by a timer
+  */
+#define HRTIM_TIMEVENTFILTER_NONE             (0x00000000U)
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1     (HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2     (HRTIM_EEFR1_EE1FLTR_1)
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3     (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4     (HRTIM_EEFR1_EE1FLTR_2)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4    (HRTIM_EEFR1_EE1FLTR_3)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)
+#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
+#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM     (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
+
+/** @brief Constants defining the DLL calibration periods (in micro seconds)
+  */
+#define HRTIM_CALIBRATIONRATE_7300             0x00000000U
+#define HRTIM_CALIBRATIONRATE_910              (HRTIM_DLLCR_CALRTE_0)
+#define HRTIM_CALIBRATIONRATE_114              (HRTIM_DLLCR_CALRTE_1)
+#define HRTIM_CALIBRATIONRATE_14               (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
+
+#endif /* STM32F3 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define I2C_DUALADDRESS_DISABLED                I2C_DUALADDRESS_DISABLE
+#define I2C_DUALADDRESS_ENABLED                 I2C_DUALADDRESS_ENABLE
+#define I2C_GENERALCALL_DISABLED                I2C_GENERALCALL_DISABLE
+#define I2C_GENERALCALL_ENABLED                 I2C_GENERALCALL_ENABLE
+#define I2C_NOSTRETCH_DISABLED                  I2C_NOSTRETCH_DISABLE
+#define I2C_NOSTRETCH_ENABLED                   I2C_NOSTRETCH_ENABLE
+#define I2C_ANALOGFILTER_ENABLED                I2C_ANALOGFILTER_ENABLE
+#define I2C_ANALOGFILTER_DISABLED               I2C_ANALOGFILTER_DISABLE
+#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
+#define HAL_I2C_STATE_MEM_BUSY_TX               HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_MEM_BUSY_RX               HAL_I2C_STATE_BUSY_RX
+#define HAL_I2C_STATE_MASTER_BUSY_TX            HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_MASTER_BUSY_RX            HAL_I2C_STATE_BUSY_RX
+#define HAL_I2C_STATE_SLAVE_BUSY_TX             HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_SLAVE_BUSY_RX             HAL_I2C_STATE_BUSY_RX
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define IRDA_ONE_BIT_SAMPLE_DISABLED            IRDA_ONE_BIT_SAMPLE_DISABLE
+#define IRDA_ONE_BIT_SAMPLE_ENABLED             IRDA_ONE_BIT_SAMPLE_ENABLE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define KR_KEY_RELOAD                   IWDG_KEY_RELOAD
+#define KR_KEY_ENABLE                   IWDG_KEY_ENABLE
+#define KR_KEY_EWA                      IWDG_KEY_WRITE_ACCESS_ENABLE
+#define KR_KEY_DWA                      IWDG_KEY_WRITE_ACCESS_DISABLE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
+
+#define LPTIM_CLOCKPOLARITY_RISINGEDGE          LPTIM_CLOCKPOLARITY_RISING
+#define LPTIM_CLOCKPOLARITY_FALLINGEDGE         LPTIM_CLOCKPOLARITY_FALLING
+#define LPTIM_CLOCKPOLARITY_BOTHEDGES           LPTIM_CLOCKPOLARITY_RISING_FALLING
+
+#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION  LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS      LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS      LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS      LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+/* The following 3 definition have also been present in a temporary version of lptim.h */
+/* They need to be renamed also to the right name, just in case */
+#define LPTIM_TRIGSAMPLETIME_2TRANSITION        LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSITION        LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSITION        LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define HAL_NAND_Read_Page              HAL_NAND_Read_Page_8b
+#define HAL_NAND_Write_Page             HAL_NAND_Write_Page_8b
+#define HAL_NAND_Read_SpareArea         HAL_NAND_Read_SpareArea_8b
+#define HAL_NAND_Write_SpareArea        HAL_NAND_Write_SpareArea_8b
+
+#define NAND_AddressTypedef             NAND_AddressTypeDef
+
+#define __ARRAY_ADDRESS                 ARRAY_ADDRESS
+#define __ADDR_1st_CYCLE                ADDR_1ST_CYCLE
+#define __ADDR_2nd_CYCLE                ADDR_2ND_CYCLE
+#define __ADDR_3rd_CYCLE                ADDR_3RD_CYCLE
+#define __ADDR_4th_CYCLE                ADDR_4TH_CYCLE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define NOR_StatusTypedef              HAL_NOR_StatusTypeDef
+#define NOR_SUCCESS                    HAL_NOR_STATUS_SUCCESS
+#define NOR_ONGOING                    HAL_NOR_STATUS_ONGOING
+#define NOR_ERROR                      HAL_NOR_STATUS_ERROR
+#define NOR_TIMEOUT                    HAL_NOR_STATUS_TIMEOUT
+
+#define __NOR_WRITE                    NOR_WRITE
+#define __NOR_ADDR_SHIFT               NOR_ADDR_SHIFT
+/**
+  * @}
+  */
+
+/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define OPAMP_NONINVERTINGINPUT_VP0           OPAMP_NONINVERTINGINPUT_IO0
+#define OPAMP_NONINVERTINGINPUT_VP1           OPAMP_NONINVERTINGINPUT_IO1
+#define OPAMP_NONINVERTINGINPUT_VP2           OPAMP_NONINVERTINGINPUT_IO2
+#define OPAMP_NONINVERTINGINPUT_VP3           OPAMP_NONINVERTINGINPUT_IO3
+
+#define OPAMP_SEC_NONINVERTINGINPUT_VP0       OPAMP_SEC_NONINVERTINGINPUT_IO0
+#define OPAMP_SEC_NONINVERTINGINPUT_VP1       OPAMP_SEC_NONINVERTINGINPUT_IO1
+#define OPAMP_SEC_NONINVERTINGINPUT_VP2       OPAMP_SEC_NONINVERTINGINPUT_IO2
+#define OPAMP_SEC_NONINVERTINGINPUT_VP3       OPAMP_SEC_NONINVERTINGINPUT_IO3
+
+#define OPAMP_INVERTINGINPUT_VM0              OPAMP_INVERTINGINPUT_IO0
+#define OPAMP_INVERTINGINPUT_VM1              OPAMP_INVERTINGINPUT_IO1
+
+#define IOPAMP_INVERTINGINPUT_VM0             OPAMP_INVERTINGINPUT_IO0
+#define IOPAMP_INVERTINGINPUT_VM1             OPAMP_INVERTINGINPUT_IO1
+
+#define OPAMP_SEC_INVERTINGINPUT_VM0          OPAMP_SEC_INVERTINGINPUT_IO0
+#define OPAMP_SEC_INVERTINGINPUT_VM1          OPAMP_SEC_INVERTINGINPUT_IO1
+
+#define OPAMP_INVERTINGINPUT_VINM             OPAMP_SEC_INVERTINGINPUT_IO1
+
+#define OPAMP_PGACONNECT_NO                   OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
+#define OPAMP_PGACONNECT_VM0                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
+#define OPAMP_PGACONNECT_VM1                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
+
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
+#define HAL_OPAMP_MSP_INIT_CB_ID       HAL_OPAMP_MSPINIT_CB_ID
+#define HAL_OPAMP_MSP_DEINIT_CB_ID     HAL_OPAMP_MSPDEINIT_CB_ID
+#endif
+
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define I2S_STANDARD_PHILLIPS      I2S_STANDARD_PHILIPS
+
+#if defined(STM32H7)
+  #define I2S_IT_TXE               I2S_IT_TXP
+  #define I2S_IT_RXNE              I2S_IT_RXP
+
+  #define I2S_FLAG_TXE             I2S_FLAG_TXP
+  #define I2S_FLAG_RXNE            I2S_FLAG_RXP
+#endif
+
+#if defined(STM32F7)
+  #define I2S_CLOCK_SYSCLK           I2S_CLOCK_PLL
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+/* Compact Flash-ATA registers description */
+#define CF_DATA                       ATA_DATA
+#define CF_SECTOR_COUNT               ATA_SECTOR_COUNT
+#define CF_SECTOR_NUMBER              ATA_SECTOR_NUMBER
+#define CF_CYLINDER_LOW               ATA_CYLINDER_LOW
+#define CF_CYLINDER_HIGH              ATA_CYLINDER_HIGH
+#define CF_CARD_HEAD                  ATA_CARD_HEAD
+#define CF_STATUS_CMD                 ATA_STATUS_CMD
+#define CF_STATUS_CMD_ALTERNATE       ATA_STATUS_CMD_ALTERNATE
+#define CF_COMMON_DATA_AREA           ATA_COMMON_DATA_AREA
+
+/* Compact Flash-ATA commands */
+#define CF_READ_SECTOR_CMD            ATA_READ_SECTOR_CMD
+#define CF_WRITE_SECTOR_CMD           ATA_WRITE_SECTOR_CMD
+#define CF_ERASE_SECTOR_CMD           ATA_ERASE_SECTOR_CMD
+#define CF_IDENTIFY_CMD               ATA_IDENTIFY_CMD
+
+#define PCCARD_StatusTypedef          HAL_PCCARD_StatusTypeDef
+#define PCCARD_SUCCESS                HAL_PCCARD_STATUS_SUCCESS
+#define PCCARD_ONGOING                HAL_PCCARD_STATUS_ONGOING
+#define PCCARD_ERROR                  HAL_PCCARD_STATUS_ERROR
+#define PCCARD_TIMEOUT                HAL_PCCARD_STATUS_TIMEOUT
+/**
+  * @}
+  */
+  
+/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define FORMAT_BIN                  RTC_FORMAT_BIN
+#define FORMAT_BCD                  RTC_FORMAT_BCD
+
+#define RTC_ALARMSUBSECONDMASK_None     RTC_ALARMSUBSECONDMASK_NONE
+#define RTC_TAMPERERASEBACKUP_DISABLED  RTC_TAMPER_ERASE_BACKUP_DISABLE
+#define RTC_TAMPERMASK_FLAG_DISABLED    RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_TAMPERMASK_FLAG_ENABLED     RTC_TAMPERMASK_FLAG_ENABLE
+
+#define RTC_MASKTAMPERFLAG_DISABLED     RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE
+#define RTC_TAMPERERASEBACKUP_ENABLED   RTC_TAMPER_ERASE_BACKUP_ENABLE
+#define RTC_TAMPER1_2_INTERRUPT         RTC_ALL_TAMPER_INTERRUPT
+#define RTC_TAMPER1_2_3_INTERRUPT       RTC_ALL_TAMPER_INTERRUPT
+
+#define RTC_TIMESTAMPPIN_PC13  RTC_TIMESTAMPPIN_DEFAULT
+#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PC1   RTC_TIMESTAMPPIN_POS2
+
+#define RTC_OUTPUT_REMAP_PC13  RTC_OUTPUT_REMAP_NONE
+#define RTC_OUTPUT_REMAP_PB14  RTC_OUTPUT_REMAP_POS1
+#define RTC_OUTPUT_REMAP_PB2   RTC_OUTPUT_REMAP_POS1
+
+#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
+#define RTC_TAMPERPIN_PA0  RTC_TAMPERPIN_POS1
+#define RTC_TAMPERPIN_PI8  RTC_TAMPERPIN_POS1
+
+#if defined(STM32H7)
+#define RTC_TAMPCR_TAMPXE          RTC_TAMPER_X
+#define RTC_TAMPCR_TAMPXIE         RTC_TAMPER_X_INTERRUPT
+
+#define RTC_TAMPER1_INTERRUPT      RTC_IT_TAMP1
+#define RTC_TAMPER2_INTERRUPT      RTC_IT_TAMP2
+#define RTC_TAMPER3_INTERRUPT      RTC_IT_TAMP3
+#define RTC_ALL_TAMPER_INTERRUPT   RTC_IT_TAMPALL
+#endif /* STM32H7 */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define SMARTCARD_NACK_ENABLED                  SMARTCARD_NACK_ENABLE
+#define SMARTCARD_NACK_DISABLED                 SMARTCARD_NACK_DISABLE
+
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLED      SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLED       SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLE       SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLE        SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+
+#define SMARTCARD_TIMEOUT_DISABLED              SMARTCARD_TIMEOUT_DISABLE
+#define SMARTCARD_TIMEOUT_ENABLED               SMARTCARD_TIMEOUT_ENABLE
+
+#define SMARTCARD_LASTBIT_DISABLED              SMARTCARD_LASTBIT_DISABLE
+#define SMARTCARD_LASTBIT_ENABLED               SMARTCARD_LASTBIT_ENABLE
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define SMBUS_DUALADDRESS_DISABLED      SMBUS_DUALADDRESS_DISABLE
+#define SMBUS_DUALADDRESS_ENABLED       SMBUS_DUALADDRESS_ENABLE
+#define SMBUS_GENERALCALL_DISABLED      SMBUS_GENERALCALL_DISABLE
+#define SMBUS_GENERALCALL_ENABLED       SMBUS_GENERALCALL_ENABLE
+#define SMBUS_NOSTRETCH_DISABLED        SMBUS_NOSTRETCH_DISABLE
+#define SMBUS_NOSTRETCH_ENABLED         SMBUS_NOSTRETCH_ENABLE
+#define SMBUS_ANALOGFILTER_ENABLED      SMBUS_ANALOGFILTER_ENABLE
+#define SMBUS_ANALOGFILTER_DISABLED     SMBUS_ANALOGFILTER_DISABLE
+#define SMBUS_PEC_DISABLED              SMBUS_PEC_DISABLE
+#define SMBUS_PEC_ENABLED               SMBUS_PEC_ENABLE
+#define HAL_SMBUS_STATE_SLAVE_LISTEN    HAL_SMBUS_STATE_LISTEN
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define SPI_TIMODE_DISABLED             SPI_TIMODE_DISABLE
+#define SPI_TIMODE_ENABLED              SPI_TIMODE_ENABLE
+
+#define SPI_CRCCALCULATION_DISABLED     SPI_CRCCALCULATION_DISABLE
+#define SPI_CRCCALCULATION_ENABLED      SPI_CRCCALCULATION_ENABLE
+
+#define SPI_NSS_PULSE_DISABLED          SPI_NSS_PULSE_DISABLE
+#define SPI_NSS_PULSE_ENABLED           SPI_NSS_PULSE_ENABLE
+
+#if defined(STM32H7)
+
+ #define SPI_FLAG_TXE                    SPI_FLAG_TXP
+ #define SPI_FLAG_RXNE                   SPI_FLAG_RXP
+
+ #define SPI_IT_TXE                      SPI_IT_TXP
+ #define SPI_IT_RXNE                     SPI_IT_RXP
+
+ #define SPI_FRLVL_EMPTY                 SPI_RX_FIFO_0PACKET
+ #define SPI_FRLVL_QUARTER_FULL          SPI_RX_FIFO_1PACKET
+ #define SPI_FRLVL_HALF_FULL             SPI_RX_FIFO_2PACKET
+ #define SPI_FRLVL_FULL                  SPI_RX_FIFO_3PACKET
+
+#endif /* STM32H7 */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define CCER_CCxE_MASK                   TIM_CCER_CCxE_MASK
+#define CCER_CCxNE_MASK                  TIM_CCER_CCxNE_MASK
+
+#define TIM_DMABase_CR1                  TIM_DMABASE_CR1
+#define TIM_DMABase_CR2                  TIM_DMABASE_CR2
+#define TIM_DMABase_SMCR                 TIM_DMABASE_SMCR
+#define TIM_DMABase_DIER                 TIM_DMABASE_DIER
+#define TIM_DMABase_SR                   TIM_DMABASE_SR
+#define TIM_DMABase_EGR                  TIM_DMABASE_EGR
+#define TIM_DMABase_CCMR1                TIM_DMABASE_CCMR1
+#define TIM_DMABase_CCMR2                TIM_DMABASE_CCMR2
+#define TIM_DMABase_CCER                 TIM_DMABASE_CCER
+#define TIM_DMABase_CNT                  TIM_DMABASE_CNT
+#define TIM_DMABase_PSC                  TIM_DMABASE_PSC
+#define TIM_DMABase_ARR                  TIM_DMABASE_ARR
+#define TIM_DMABase_RCR                  TIM_DMABASE_RCR
+#define TIM_DMABase_CCR1                 TIM_DMABASE_CCR1
+#define TIM_DMABase_CCR2                 TIM_DMABASE_CCR2
+#define TIM_DMABase_CCR3                 TIM_DMABASE_CCR3
+#define TIM_DMABase_CCR4                 TIM_DMABASE_CCR4
+#define TIM_DMABase_BDTR                 TIM_DMABASE_BDTR
+#define TIM_DMABase_DCR                  TIM_DMABASE_DCR
+#define TIM_DMABase_DMAR                 TIM_DMABASE_DMAR
+#define TIM_DMABase_OR1                  TIM_DMABASE_OR1
+#define TIM_DMABase_CCMR3                TIM_DMABASE_CCMR3
+#define TIM_DMABase_CCR5                 TIM_DMABASE_CCR5
+#define TIM_DMABase_CCR6                 TIM_DMABASE_CCR6
+#define TIM_DMABase_OR2                  TIM_DMABASE_OR2
+#define TIM_DMABase_OR3                  TIM_DMABASE_OR3
+#define TIM_DMABase_OR                   TIM_DMABASE_OR
+
+#define TIM_EventSource_Update           TIM_EVENTSOURCE_UPDATE
+#define TIM_EventSource_CC1              TIM_EVENTSOURCE_CC1
+#define TIM_EventSource_CC2              TIM_EVENTSOURCE_CC2
+#define TIM_EventSource_CC3              TIM_EVENTSOURCE_CC3
+#define TIM_EventSource_CC4              TIM_EVENTSOURCE_CC4
+#define TIM_EventSource_COM              TIM_EVENTSOURCE_COM
+#define TIM_EventSource_Trigger          TIM_EVENTSOURCE_TRIGGER
+#define TIM_EventSource_Break            TIM_EVENTSOURCE_BREAK
+#define TIM_EventSource_Break2           TIM_EVENTSOURCE_BREAK2
+
+#define TIM_DMABurstLength_1Transfer     TIM_DMABURSTLENGTH_1TRANSFER
+#define TIM_DMABurstLength_2Transfers    TIM_DMABURSTLENGTH_2TRANSFERS
+#define TIM_DMABurstLength_3Transfers    TIM_DMABURSTLENGTH_3TRANSFERS
+#define TIM_DMABurstLength_4Transfers    TIM_DMABURSTLENGTH_4TRANSFERS
+#define TIM_DMABurstLength_5Transfers    TIM_DMABURSTLENGTH_5TRANSFERS
+#define TIM_DMABurstLength_6Transfers    TIM_DMABURSTLENGTH_6TRANSFERS
+#define TIM_DMABurstLength_7Transfers    TIM_DMABURSTLENGTH_7TRANSFERS
+#define TIM_DMABurstLength_8Transfers    TIM_DMABURSTLENGTH_8TRANSFERS
+#define TIM_DMABurstLength_9Transfers    TIM_DMABURSTLENGTH_9TRANSFERS
+#define TIM_DMABurstLength_10Transfers   TIM_DMABURSTLENGTH_10TRANSFERS
+#define TIM_DMABurstLength_11Transfers   TIM_DMABURSTLENGTH_11TRANSFERS
+#define TIM_DMABurstLength_12Transfers   TIM_DMABURSTLENGTH_12TRANSFERS
+#define TIM_DMABurstLength_13Transfers   TIM_DMABURSTLENGTH_13TRANSFERS
+#define TIM_DMABurstLength_14Transfers   TIM_DMABURSTLENGTH_14TRANSFERS
+#define TIM_DMABurstLength_15Transfers   TIM_DMABURSTLENGTH_15TRANSFERS
+#define TIM_DMABurstLength_16Transfers   TIM_DMABURSTLENGTH_16TRANSFERS
+#define TIM_DMABurstLength_17Transfers   TIM_DMABURSTLENGTH_17TRANSFERS
+#define TIM_DMABurstLength_18Transfers   TIM_DMABURSTLENGTH_18TRANSFERS
+
+#if defined(STM32L0)
+#define TIM22_TI1_GPIO1   TIM22_TI1_GPIO
+#define TIM22_TI1_GPIO2   TIM22_TI1_GPIO
+#endif
+
+#if defined(STM32F3)
+#define IS_TIM_HALL_INTERFACE_INSTANCE   IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
+#endif
+
+#if defined(STM32H7)
+#define TIM_TIM1_ETR_COMP1_OUT        TIM_TIM1_ETR_COMP1
+#define TIM_TIM1_ETR_COMP2_OUT        TIM_TIM1_ETR_COMP2
+#define TIM_TIM8_ETR_COMP1_OUT        TIM_TIM8_ETR_COMP1
+#define TIM_TIM8_ETR_COMP2_OUT        TIM_TIM8_ETR_COMP2
+#define TIM_TIM2_ETR_COMP1_OUT        TIM_TIM2_ETR_COMP1
+#define TIM_TIM2_ETR_COMP2_OUT        TIM_TIM2_ETR_COMP2
+#define TIM_TIM3_ETR_COMP1_OUT        TIM_TIM3_ETR_COMP1
+#define TIM_TIM1_TI1_COMP1_OUT        TIM_TIM1_TI1_COMP1
+#define TIM_TIM8_TI1_COMP2_OUT        TIM_TIM8_TI1_COMP2
+#define TIM_TIM2_TI4_COMP1_OUT        TIM_TIM2_TI4_COMP1
+#define TIM_TIM2_TI4_COMP2_OUT        TIM_TIM2_TI4_COMP2
+#define TIM_TIM2_TI4_COMP1COMP2_OUT   TIM_TIM2_TI4_COMP1_COMP2
+#define TIM_TIM3_TI1_COMP1_OUT        TIM_TIM3_TI1_COMP1
+#define TIM_TIM3_TI1_COMP2_OUT        TIM_TIM3_TI1_COMP2
+#define TIM_TIM3_TI1_COMP1COMP2_OUT   TIM_TIM3_TI1_COMP1_COMP2
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define TSC_SYNC_POL_FALL        TSC_SYNC_POLARITY_FALLING
+#define TSC_SYNC_POL_RISE_HIGH   TSC_SYNC_POLARITY_RISING
+/**
+  * @}
+  */
+
+/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define UART_ONEBIT_SAMPLING_DISABLED   UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONEBIT_SAMPLING_ENABLED    UART_ONE_BIT_SAMPLE_ENABLE
+#define UART_ONE_BIT_SAMPLE_DISABLED    UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONE_BIT_SAMPLE_ENABLED     UART_ONE_BIT_SAMPLE_ENABLE
+
+#define __HAL_UART_ONEBIT_ENABLE        __HAL_UART_ONE_BIT_SAMPLE_ENABLE
+#define __HAL_UART_ONEBIT_DISABLE       __HAL_UART_ONE_BIT_SAMPLE_DISABLE
+
+#define __DIV_SAMPLING16                UART_DIV_SAMPLING16
+#define __DIVMANT_SAMPLING16            UART_DIVMANT_SAMPLING16
+#define __DIVFRAQ_SAMPLING16            UART_DIVFRAQ_SAMPLING16
+#define __UART_BRR_SAMPLING16           UART_BRR_SAMPLING16
+
+#define __DIV_SAMPLING8                 UART_DIV_SAMPLING8
+#define __DIVMANT_SAMPLING8             UART_DIVMANT_SAMPLING8
+#define __DIVFRAQ_SAMPLING8             UART_DIVFRAQ_SAMPLING8
+#define __UART_BRR_SAMPLING8            UART_BRR_SAMPLING8
+
+#define __DIV_LPUART                    UART_DIV_LPUART
+
+#define UART_WAKEUPMETHODE_IDLELINE     UART_WAKEUPMETHOD_IDLELINE
+#define UART_WAKEUPMETHODE_ADDRESSMARK  UART_WAKEUPMETHOD_ADDRESSMARK
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define USART_CLOCK_DISABLED            USART_CLOCK_DISABLE
+#define USART_CLOCK_ENABLED             USART_CLOCK_ENABLE
+
+#define USARTNACK_ENABLED               USART_NACK_ENABLE
+#define USARTNACK_DISABLED              USART_NACK_DISABLE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define CFR_BASE                    WWDG_CFR_BASE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define CAN_FilterFIFO0             CAN_FILTER_FIFO0
+#define CAN_FilterFIFO1             CAN_FILTER_FIFO1
+#define CAN_IT_RQCP0                CAN_IT_TME
+#define CAN_IT_RQCP1                CAN_IT_TME
+#define CAN_IT_RQCP2                CAN_IT_TME
+#define INAK_TIMEOUT                CAN_TIMEOUT_VALUE
+#define SLAK_TIMEOUT                CAN_TIMEOUT_VALUE
+#define CAN_TXSTATUS_FAILED         ((uint8_t)0x00U)
+#define CAN_TXSTATUS_OK             ((uint8_t)0x01U)
+#define CAN_TXSTATUS_PENDING        ((uint8_t)0x02U)
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define VLAN_TAG                ETH_VLAN_TAG
+#define MIN_ETH_PAYLOAD         ETH_MIN_ETH_PAYLOAD
+#define MAX_ETH_PAYLOAD         ETH_MAX_ETH_PAYLOAD
+#define JUMBO_FRAME_PAYLOAD     ETH_JUMBO_FRAME_PAYLOAD
+#define MACMIIAR_CR_MASK        ETH_MACMIIAR_CR_MASK
+#define MACCR_CLEAR_MASK        ETH_MACCR_CLEAR_MASK
+#define MACFCR_CLEAR_MASK       ETH_MACFCR_CLEAR_MASK
+#define DMAOMR_CLEAR_MASK       ETH_DMAOMR_CLEAR_MASK
+
+#define ETH_MMCCR              0x00000100U
+#define ETH_MMCRIR             0x00000104U
+#define ETH_MMCTIR             0x00000108U
+#define ETH_MMCRIMR            0x0000010CU
+#define ETH_MMCTIMR            0x00000110U
+#define ETH_MMCTGFSCCR         0x0000014CU
+#define ETH_MMCTGFMSCCR        0x00000150U
+#define ETH_MMCTGFCR           0x00000168U
+#define ETH_MMCRFCECR          0x00000194U
+#define ETH_MMCRFAECR          0x00000198U
+#define ETH_MMCRGUFCR          0x000001C4U
+
+#define ETH_MAC_TXFIFO_FULL                             0x02000000U  /* Tx FIFO full */
+#define ETH_MAC_TXFIFONOT_EMPTY                         0x01000000U  /* Tx FIFO not empty */
+#define ETH_MAC_TXFIFO_WRITE_ACTIVE                     0x00400000U  /* Tx FIFO write active */
+#define ETH_MAC_TXFIFO_IDLE                             0x00000000U  /* Tx FIFO read status: Idle */
+#define ETH_MAC_TXFIFO_READ                             0x00100000U  /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
+#define ETH_MAC_TXFIFO_WAITING                          0x00200000U  /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
+#define ETH_MAC_TXFIFO_WRITING                          0x00300000U  /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
+#define ETH_MAC_TRANSMISSION_PAUSE                      0x00080000U  /* MAC transmitter in pause */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE            0x00000000U  /* MAC transmit frame controller: Idle */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING         0x00020000U  /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF   0x00040000U  /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING    0x00060000U  /* MAC transmit frame controller: Transferring input frame for transmission */
+#define ETH_MAC_MII_TRANSMIT_ACTIVE           0x00010000U  /* MAC MII transmit engine active */
+#define ETH_MAC_RXFIFO_EMPTY                  0x00000000U  /* Rx FIFO fill level: empty */
+#define ETH_MAC_RXFIFO_BELOW_THRESHOLD        0x00000100U  /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
+#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD        0x00000200U  /* Rx FIFO fill level: fill-level above flow-control activate threshold */
+#define ETH_MAC_RXFIFO_FULL                   0x00000300U  /* Rx FIFO fill level: full */
+#if defined(STM32F1)
+#else
+#define ETH_MAC_READCONTROLLER_IDLE           0x00000000U  /* Rx FIFO read controller IDLE state */
+#define ETH_MAC_READCONTROLLER_READING_DATA   0x00000020U  /* Rx FIFO read controller Reading frame data */
+#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U  /* Rx FIFO read controller Reading frame status (or time-stamp) */
+#endif
+#define ETH_MAC_READCONTROLLER_FLUSHING       0x00000060U  /* Rx FIFO read controller Flushing the frame data and status */
+#define ETH_MAC_RXFIFO_WRITE_ACTIVE           0x00000010U  /* Rx FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_NOTACTIVE          0x00000000U  /* MAC small FIFO read / write controllers not active */
+#define ETH_MAC_SMALL_FIFO_READ_ACTIVE        0x00000002U  /* MAC small FIFO read controller active */
+#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE       0x00000004U  /* MAC small FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_RW_ACTIVE          0x00000006U  /* MAC small FIFO read / write controllers active */
+#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE   0x00000001U  /* MAC MII receive protocol engine active */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define HAL_DCMI_ERROR_OVF      HAL_DCMI_ERROR_OVR
+#define DCMI_IT_OVF             DCMI_IT_OVR
+#define DCMI_FLAG_OVFRI         DCMI_FLAG_OVRRI
+#define DCMI_FLAG_OVFMI         DCMI_FLAG_OVRMI
+
+#define HAL_DCMI_ConfigCROP     HAL_DCMI_ConfigCrop
+#define HAL_DCMI_EnableCROP     HAL_DCMI_EnableCrop
+#define HAL_DCMI_DisableCROP    HAL_DCMI_DisableCrop
+
+/**
+  * @}
+  */
+
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
+  || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
+  || defined(STM32H7)
+/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define DMA2D_ARGB8888          DMA2D_OUTPUT_ARGB8888
+#define DMA2D_RGB888            DMA2D_OUTPUT_RGB888
+#define DMA2D_RGB565            DMA2D_OUTPUT_RGB565
+#define DMA2D_ARGB1555          DMA2D_OUTPUT_ARGB1555
+#define DMA2D_ARGB4444          DMA2D_OUTPUT_ARGB4444
+
+#define CM_ARGB8888             DMA2D_INPUT_ARGB8888
+#define CM_RGB888               DMA2D_INPUT_RGB888
+#define CM_RGB565               DMA2D_INPUT_RGB565
+#define CM_ARGB1555             DMA2D_INPUT_ARGB1555
+#define CM_ARGB4444             DMA2D_INPUT_ARGB4444
+#define CM_L8                   DMA2D_INPUT_L8
+#define CM_AL44                 DMA2D_INPUT_AL44
+#define CM_AL88                 DMA2D_INPUT_AL88
+#define CM_L4                   DMA2D_INPUT_L4
+#define CM_A8                   DMA2D_INPUT_A8
+#define CM_A4                   DMA2D_INPUT_A4
+/**
+  * @}
+  */
+#endif  /* STM32L4 ||  STM32F7 ||  STM32F4 ||  STM32H7 */
+
+/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_CRYP_ComputationCpltCallback     HAL_CRYPEx_ComputationCpltCallback
+/**
+  * @}
+  */
+
+/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_HASH_STATETypeDef        HAL_HASH_StateTypeDef
+#define HAL_HASHPhaseTypeDef         HAL_HASH_PhaseTypeDef
+#define HAL_HMAC_MD5_Finish          HAL_HASH_MD5_Finish
+#define HAL_HMAC_SHA1_Finish         HAL_HASH_SHA1_Finish
+#define HAL_HMAC_SHA224_Finish       HAL_HASH_SHA224_Finish
+#define HAL_HMAC_SHA256_Finish       HAL_HASH_SHA256_Finish
+
+/*HASH Algorithm Selection*/
+
+#define HASH_AlgoSelection_SHA1      HASH_ALGOSELECTION_SHA1
+#define HASH_AlgoSelection_SHA224    HASH_ALGOSELECTION_SHA224
+#define HASH_AlgoSelection_SHA256    HASH_ALGOSELECTION_SHA256
+#define HASH_AlgoSelection_MD5       HASH_ALGOSELECTION_MD5
+
+#define HASH_AlgoMode_HASH         HASH_ALGOMODE_HASH
+#define HASH_AlgoMode_HMAC         HASH_ALGOMODE_HMAC
+
+#define HASH_HMACKeyType_ShortKey  HASH_HMAC_KEYTYPE_SHORTKEY
+#define HASH_HMACKeyType_LongKey   HASH_HMAC_KEYTYPE_LONGKEY
+
+#if defined(STM32L4) || defined(STM32L5) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
+
+#define HAL_HASH_MD5_Accumulate                HAL_HASH_MD5_Accmlt
+#define HAL_HASH_MD5_Accumulate_End            HAL_HASH_MD5_Accmlt_End
+#define HAL_HASH_MD5_Accumulate_IT             HAL_HASH_MD5_Accmlt_IT
+#define HAL_HASH_MD5_Accumulate_End_IT         HAL_HASH_MD5_Accmlt_End_IT
+
+#define HAL_HASH_SHA1_Accumulate               HAL_HASH_SHA1_Accmlt
+#define HAL_HASH_SHA1_Accumulate_End           HAL_HASH_SHA1_Accmlt_End
+#define HAL_HASH_SHA1_Accumulate_IT            HAL_HASH_SHA1_Accmlt_IT
+#define HAL_HASH_SHA1_Accumulate_End_IT        HAL_HASH_SHA1_Accmlt_End_IT
+
+#define HAL_HASHEx_SHA224_Accumulate           HAL_HASHEx_SHA224_Accmlt
+#define HAL_HASHEx_SHA224_Accumulate_End       HAL_HASHEx_SHA224_Accmlt_End
+#define HAL_HASHEx_SHA224_Accumulate_IT        HAL_HASHEx_SHA224_Accmlt_IT
+#define HAL_HASHEx_SHA224_Accumulate_End_IT    HAL_HASHEx_SHA224_Accmlt_End_IT
+
+#define HAL_HASHEx_SHA256_Accumulate           HAL_HASHEx_SHA256_Accmlt
+#define HAL_HASHEx_SHA256_Accumulate_End       HAL_HASHEx_SHA256_Accmlt_End
+#define HAL_HASHEx_SHA256_Accumulate_IT        HAL_HASHEx_SHA256_Accmlt_IT
+#define HAL_HASHEx_SHA256_Accumulate_End_IT    HAL_HASHEx_SHA256_Accmlt_End_IT
+
+#endif  /* STM32L4 || STM32L5 || STM32F4 || STM32F7 || STM32H7 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
+#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
+#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
+#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
+#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
+#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
+#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
+#define HAL_VREFINT_OutputSelect  HAL_SYSCFG_VREFINT_OutputSelect
+#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
+#if defined(STM32L0)
+#else
+#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
+#endif
+#define HAL_ADC_EnableBuffer_Cmd(cmd)  (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
+#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ?  HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
+#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
+#define HAL_EnableSRDomainDBGStopMode      HAL_EnableDomain3DBGStopMode
+#define HAL_DisableSRDomainDBGStopMode     HAL_DisableDomain3DBGStopMode
+#define HAL_EnableSRDomainDBGStandbyMode   HAL_EnableDomain3DBGStandbyMode
+#define HAL_DisableSRDomainDBGStandbyMode  HAL_DisableDomain3DBGStandbyMode
+#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ  || STM32H7B0xxQ */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define FLASH_HalfPageProgram      HAL_FLASHEx_HalfPageProgram
+#define FLASH_EnableRunPowerDown   HAL_FLASHEx_EnableRunPowerDown
+#define FLASH_DisableRunPowerDown  HAL_FLASHEx_DisableRunPowerDown
+#define HAL_DATA_EEPROMEx_Unlock   HAL_FLASHEx_DATAEEPROM_Unlock
+#define HAL_DATA_EEPROMEx_Lock     HAL_FLASHEx_DATAEEPROM_Lock
+#define HAL_DATA_EEPROMEx_Erase    HAL_FLASHEx_DATAEEPROM_Erase
+#define HAL_DATA_EEPROMEx_Program  HAL_FLASHEx_DATAEEPROM_Program
+
+ /**
+  * @}
+  */
+
+/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_I2CEx_AnalogFilter_Config         HAL_I2CEx_ConfigAnalogFilter
+#define HAL_I2CEx_DigitalFilter_Config        HAL_I2CEx_ConfigDigitalFilter
+#define HAL_FMPI2CEx_AnalogFilter_Config      HAL_FMPI2CEx_ConfigAnalogFilter
+#define HAL_FMPI2CEx_DigitalFilter_Config     HAL_FMPI2CEx_ConfigDigitalFilter
+
+#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
+
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)
+#define HAL_I2C_Master_Sequential_Transmit_IT  HAL_I2C_Master_Seq_Transmit_IT
+#define HAL_I2C_Master_Sequential_Receive_IT   HAL_I2C_Master_Seq_Receive_IT
+#define HAL_I2C_Slave_Sequential_Transmit_IT   HAL_I2C_Slave_Seq_Transmit_IT
+#define HAL_I2C_Slave_Sequential_Receive_IT    HAL_I2C_Slave_Seq_Receive_IT
+#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)
+#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
+#define HAL_I2C_Master_Sequential_Receive_DMA  HAL_I2C_Master_Seq_Receive_DMA
+#define HAL_I2C_Slave_Sequential_Transmit_DMA  HAL_I2C_Slave_Seq_Transmit_DMA
+#define HAL_I2C_Slave_Sequential_Receive_DMA   HAL_I2C_Slave_Seq_Receive_DMA
+#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */
+
+#if defined(STM32F4)
+#define HAL_FMPI2C_Master_Sequential_Transmit_IT  HAL_FMPI2C_Master_Seq_Transmit_IT
+#define HAL_FMPI2C_Master_Sequential_Receive_IT   HAL_FMPI2C_Master_Seq_Receive_IT
+#define HAL_FMPI2C_Slave_Sequential_Transmit_IT   HAL_FMPI2C_Slave_Seq_Transmit_IT
+#define HAL_FMPI2C_Slave_Sequential_Receive_IT    HAL_FMPI2C_Slave_Seq_Receive_IT
+#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA
+#define HAL_FMPI2C_Master_Sequential_Receive_DMA  HAL_FMPI2C_Master_Seq_Receive_DMA
+#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA  HAL_FMPI2C_Slave_Seq_Transmit_DMA
+#define HAL_FMPI2C_Slave_Sequential_Receive_DMA   HAL_FMPI2C_Slave_Seq_Receive_DMA
+#endif /* STM32F4 */
+ /**
+  * @}
+  */
+
+/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
+  * @{
+  */
+
+#if defined(STM32G0)
+#define HAL_PWR_ConfigPVD                             HAL_PWREx_ConfigPVD
+#define HAL_PWR_EnablePVD                             HAL_PWREx_EnablePVD
+#define HAL_PWR_DisablePVD                            HAL_PWREx_DisablePVD
+#define HAL_PWR_PVD_IRQHandler                        HAL_PWREx_PVD_IRQHandler
+#endif
+#define HAL_PWR_PVDConfig                             HAL_PWR_ConfigPVD
+#define HAL_PWR_DisableBkUpReg                        HAL_PWREx_DisableBkUpReg
+#define HAL_PWR_DisableFlashPowerDown                 HAL_PWREx_DisableFlashPowerDown
+#define HAL_PWR_DisableVddio2Monitor                  HAL_PWREx_DisableVddio2Monitor
+#define HAL_PWR_EnableBkUpReg                         HAL_PWREx_EnableBkUpReg
+#define HAL_PWR_EnableFlashPowerDown                  HAL_PWREx_EnableFlashPowerDown
+#define HAL_PWR_EnableVddio2Monitor                   HAL_PWREx_EnableVddio2Monitor
+#define HAL_PWR_PVD_PVM_IRQHandler                    HAL_PWREx_PVD_PVM_IRQHandler
+#define HAL_PWR_PVDLevelConfig                        HAL_PWR_ConfigPVD
+#define HAL_PWR_Vddio2Monitor_IRQHandler              HAL_PWREx_Vddio2Monitor_IRQHandler
+#define HAL_PWR_Vddio2MonitorCallback                 HAL_PWREx_Vddio2MonitorCallback
+#define HAL_PWREx_ActivateOverDrive                   HAL_PWREx_EnableOverDrive
+#define HAL_PWREx_DeactivateOverDrive                 HAL_PWREx_DisableOverDrive
+#define HAL_PWREx_DisableSDADCAnalog                  HAL_PWREx_DisableSDADC
+#define HAL_PWREx_EnableSDADCAnalog                   HAL_PWREx_EnableSDADC
+#define HAL_PWREx_PVMConfig                           HAL_PWREx_ConfigPVM
+
+#define PWR_MODE_NORMAL                               PWR_PVD_MODE_NORMAL
+#define PWR_MODE_IT_RISING                            PWR_PVD_MODE_IT_RISING
+#define PWR_MODE_IT_FALLING                           PWR_PVD_MODE_IT_FALLING
+#define PWR_MODE_IT_RISING_FALLING                    PWR_PVD_MODE_IT_RISING_FALLING
+#define PWR_MODE_EVENT_RISING                         PWR_PVD_MODE_EVENT_RISING
+#define PWR_MODE_EVENT_FALLING                        PWR_PVD_MODE_EVENT_FALLING
+#define PWR_MODE_EVENT_RISING_FALLING                 PWR_PVD_MODE_EVENT_RISING_FALLING
+
+#define CR_OFFSET_BB                                  PWR_CR_OFFSET_BB
+#define CSR_OFFSET_BB                                 PWR_CSR_OFFSET_BB
+#define PMODE_BIT_NUMBER                              VOS_BIT_NUMBER
+#define CR_PMODE_BB                                   CR_VOS_BB
+
+#define DBP_BitNumber                                 DBP_BIT_NUMBER
+#define PVDE_BitNumber                                PVDE_BIT_NUMBER
+#define PMODE_BitNumber                               PMODE_BIT_NUMBER
+#define EWUP_BitNumber                                EWUP_BIT_NUMBER
+#define FPDS_BitNumber                                FPDS_BIT_NUMBER
+#define ODEN_BitNumber                                ODEN_BIT_NUMBER
+#define ODSWEN_BitNumber                              ODSWEN_BIT_NUMBER
+#define MRLVDS_BitNumber                              MRLVDS_BIT_NUMBER
+#define LPLVDS_BitNumber                              LPLVDS_BIT_NUMBER
+#define BRE_BitNumber                                 BRE_BIT_NUMBER
+
+#define PWR_MODE_EVT                                  PWR_PVD_MODE_NORMAL
+
+ /**
+  * @}
+  */
+
+/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_SMBUS_Slave_Listen_IT          HAL_SMBUS_EnableListen_IT
+#define HAL_SMBUS_SlaveAddrCallback        HAL_SMBUS_AddrCallback
+#define HAL_SMBUS_SlaveListenCpltCallback  HAL_SMBUS_ListenCpltCallback
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_SPI_FlushRxFifo                HAL_SPIEx_FlushRxFifo
+/**
+  * @}
+  */
+
+/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_TIM_DMADelayPulseCplt                       TIM_DMADelayPulseCplt
+#define HAL_TIM_DMAError                                TIM_DMAError
+#define HAL_TIM_DMACaptureCplt                          TIM_DMACaptureCplt
+#define HAL_TIMEx_DMACommutationCplt                    TIMEx_DMACommutationCplt
+#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
+#define HAL_TIM_SlaveConfigSynchronization              HAL_TIM_SlaveConfigSynchro
+#define HAL_TIM_SlaveConfigSynchronization_IT           HAL_TIM_SlaveConfigSynchro_IT
+#define HAL_TIMEx_CommutationCallback                   HAL_TIMEx_CommutCallback
+#define HAL_TIMEx_ConfigCommutationEvent                HAL_TIMEx_ConfigCommutEvent
+#define HAL_TIMEx_ConfigCommutationEvent_IT             HAL_TIMEx_ConfigCommutEvent_IT
+#define HAL_TIMEx_ConfigCommutationEvent_DMA            HAL_TIMEx_ConfigCommutEvent_DMA
+#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
+/**
+  * @}
+  */
+
+/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
+#define HAL_LTDC_Relaod           HAL_LTDC_Reload
+#define HAL_LTDC_StructInitFromVideoConfig  HAL_LTDCEx_StructInitFromVideoConfig
+#define HAL_LTDC_StructInitFromAdaptedCommandConfig  HAL_LTDCEx_StructInitFromAdaptedCommandConfig
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros ------------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define AES_IT_CC                      CRYP_IT_CC
+#define AES_IT_ERR                     CRYP_IT_ERR
+#define AES_FLAG_CCF                   CRYP_FLAG_CCF
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_GET_BOOT_MODE                   __HAL_SYSCFG_GET_BOOT_MODE
+#define __HAL_REMAPMEMORY_FLASH               __HAL_SYSCFG_REMAPMEMORY_FLASH
+#define __HAL_REMAPMEMORY_SYSTEMFLASH         __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
+#define __HAL_REMAPMEMORY_SRAM                __HAL_SYSCFG_REMAPMEMORY_SRAM
+#define __HAL_REMAPMEMORY_FMC                 __HAL_SYSCFG_REMAPMEMORY_FMC
+#define __HAL_REMAPMEMORY_FMC_SDRAM           __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
+#define __HAL_REMAPMEMORY_FSMC                __HAL_SYSCFG_REMAPMEMORY_FSMC
+#define __HAL_REMAPMEMORY_QUADSPI             __HAL_SYSCFG_REMAPMEMORY_QUADSPI
+#define __HAL_FMC_BANK                        __HAL_SYSCFG_FMC_BANK
+#define __HAL_GET_FLAG                        __HAL_SYSCFG_GET_FLAG
+#define __HAL_CLEAR_FLAG                      __HAL_SYSCFG_CLEAR_FLAG
+#define __HAL_VREFINT_OUT_ENABLE              __HAL_SYSCFG_VREFINT_OUT_ENABLE
+#define __HAL_VREFINT_OUT_DISABLE             __HAL_SYSCFG_VREFINT_OUT_DISABLE
+#define __HAL_SYSCFG_SRAM2_WRP_ENABLE         __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
+
+#define SYSCFG_FLAG_VREF_READY                SYSCFG_FLAG_VREFINT_READY
+#define SYSCFG_FLAG_RC48                      RCC_FLAG_HSI48
+#define IS_SYSCFG_FASTMODEPLUS_CONFIG         IS_I2C_FASTMODEPLUS
+#define UFB_MODE_BitNumber                    UFB_MODE_BIT_NUMBER
+#define CMP_PD_BitNumber                      CMP_PD_BIT_NUMBER
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __ADC_ENABLE                                     __HAL_ADC_ENABLE
+#define __ADC_DISABLE                                    __HAL_ADC_DISABLE
+#define __HAL_ADC_ENABLING_CONDITIONS                    ADC_ENABLING_CONDITIONS
+#define __HAL_ADC_DISABLING_CONDITIONS                   ADC_DISABLING_CONDITIONS
+#define __HAL_ADC_IS_ENABLED                             ADC_IS_ENABLE
+#define __ADC_IS_ENABLED                                 ADC_IS_ENABLE
+#define __HAL_ADC_IS_SOFTWARE_START_REGULAR              ADC_IS_SOFTWARE_START_REGULAR
+#define __HAL_ADC_IS_SOFTWARE_START_INJECTED             ADC_IS_SOFTWARE_START_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR          ADC_IS_CONVERSION_ONGOING_REGULAR
+#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED         ADC_IS_CONVERSION_ONGOING_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING                  ADC_IS_CONVERSION_ONGOING
+#define __HAL_ADC_CLEAR_ERRORCODE                        ADC_CLEAR_ERRORCODE
+
+#define __HAL_ADC_GET_RESOLUTION                         ADC_GET_RESOLUTION
+#define __HAL_ADC_JSQR_RK                                ADC_JSQR_RK
+#define __HAL_ADC_CFGR_AWD1CH                            ADC_CFGR_AWD1CH_SHIFT
+#define __HAL_ADC_CFGR_AWD23CR                           ADC_CFGR_AWD23CR
+#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION            ADC_CFGR_INJECT_AUTO_CONVERSION
+#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE              ADC_CFGR_INJECT_CONTEXT_QUEUE
+#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS             ADC_CFGR_INJECT_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS                ADC_CFGR_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM                 ADC_CFGR_DISCONTINUOUS_NUM
+#define __HAL_ADC_CFGR_AUTOWAIT                          ADC_CFGR_AUTOWAIT
+#define __HAL_ADC_CFGR_CONTINUOUS                        ADC_CFGR_CONTINUOUS
+#define __HAL_ADC_CFGR_OVERRUN                           ADC_CFGR_OVERRUN
+#define __HAL_ADC_CFGR_DMACONTREQ                        ADC_CFGR_DMACONTREQ
+#define __HAL_ADC_CFGR_EXTSEL                            ADC_CFGR_EXTSEL_SET
+#define __HAL_ADC_JSQR_JEXTSEL                           ADC_JSQR_JEXTSEL_SET
+#define __HAL_ADC_OFR_CHANNEL                            ADC_OFR_CHANNEL
+#define __HAL_ADC_DIFSEL_CHANNEL                         ADC_DIFSEL_CHANNEL
+#define __HAL_ADC_CALFACT_DIFF_SET                       ADC_CALFACT_DIFF_SET
+#define __HAL_ADC_CALFACT_DIFF_GET                       ADC_CALFACT_DIFF_GET
+#define __HAL_ADC_TRX_HIGHTHRESHOLD                      ADC_TRX_HIGHTHRESHOLD
+
+#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION                ADC_OFFSET_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION         ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION        ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_COMMON_REGISTER                        ADC_COMMON_REGISTER
+#define __HAL_ADC_COMMON_CCR_MULTI                       ADC_COMMON_CCR_MULTI
+#define __HAL_ADC_MULTIMODE_IS_ENABLED                   ADC_MULTIMODE_IS_ENABLE
+#define __ADC_MULTIMODE_IS_ENABLED                       ADC_MULTIMODE_IS_ENABLE
+#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER        ADC_NONMULTIMODE_OR_MULTIMODEMASTER
+#define __HAL_ADC_COMMON_ADC_OTHER                       ADC_COMMON_ADC_OTHER
+#define __HAL_ADC_MULTI_SLAVE                            ADC_MULTI_SLAVE
+
+#define __HAL_ADC_SQR1_L                                 ADC_SQR1_L_SHIFT
+#define __HAL_ADC_JSQR_JL                                ADC_JSQR_JL_SHIFT
+#define __HAL_ADC_JSQR_RK_JL                             ADC_JSQR_RK_JL
+#define __HAL_ADC_CR1_DISCONTINUOUS_NUM                  ADC_CR1_DISCONTINUOUS_NUM
+#define __HAL_ADC_CR1_SCAN                               ADC_CR1_SCAN_SET
+#define __HAL_ADC_CONVCYCLES_MAX_RANGE                   ADC_CONVCYCLES_MAX_RANGE
+#define __HAL_ADC_CLOCK_PRESCALER_RANGE                  ADC_CLOCK_PRESCALER_RANGE
+#define __HAL_ADC_GET_CLOCK_PRESCALER                    ADC_GET_CLOCK_PRESCALER
+
+#define __HAL_ADC_SQR1                                   ADC_SQR1
+#define __HAL_ADC_SMPR1                                  ADC_SMPR1
+#define __HAL_ADC_SMPR2                                  ADC_SMPR2
+#define __HAL_ADC_SQR3_RK                                ADC_SQR3_RK
+#define __HAL_ADC_SQR2_RK                                ADC_SQR2_RK
+#define __HAL_ADC_SQR1_RK                                ADC_SQR1_RK
+#define __HAL_ADC_CR2_CONTINUOUS                         ADC_CR2_CONTINUOUS
+#define __HAL_ADC_CR1_DISCONTINUOUS                      ADC_CR1_DISCONTINUOUS
+#define __HAL_ADC_CR1_SCANCONV                           ADC_CR1_SCANCONV
+#define __HAL_ADC_CR2_EOCSelection                       ADC_CR2_EOCSelection
+#define __HAL_ADC_CR2_DMAContReq                         ADC_CR2_DMAContReq
+#define __HAL_ADC_JSQR                                   ADC_JSQR
+
+#define __HAL_ADC_CHSELR_CHANNEL                         ADC_CHSELR_CHANNEL
+#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS               ADC_CFGR1_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR1_AUTOOFF                          ADC_CFGR1_AUTOOFF
+#define __HAL_ADC_CFGR1_AUTOWAIT                         ADC_CFGR1_AUTOWAIT
+#define __HAL_ADC_CFGR1_CONTINUOUS                       ADC_CFGR1_CONTINUOUS
+#define __HAL_ADC_CFGR1_OVERRUN                          ADC_CFGR1_OVERRUN
+#define __HAL_ADC_CFGR1_SCANDIR                          ADC_CFGR1_SCANDIR
+#define __HAL_ADC_CFGR1_DMACONTREQ                       ADC_CFGR1_DMACONTREQ
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_DHR12R1_ALIGNEMENT                        DAC_DHR12R1_ALIGNMENT
+#define __HAL_DHR12R2_ALIGNEMENT                        DAC_DHR12R2_ALIGNMENT
+#define __HAL_DHR12RD_ALIGNEMENT                        DAC_DHR12RD_ALIGNMENT
+#define IS_DAC_GENERATE_WAVE                            IS_DAC_WAVE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
+#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
+#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
+#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
+#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
+#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
+#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
+#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
+#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
+#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
+#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
+#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
+#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
+#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
+#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
+#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
+
+#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
+#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
+#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
+#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
+#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
+#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
+#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
+#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
+#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
+#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
+#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
+#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
+#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
+#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
+
+
+#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
+#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
+#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
+#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
+#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
+#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
+#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
+#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
+#if defined(STM32H7)
+  #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
+  #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
+  #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
+  #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
+#else
+  #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
+  #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
+  #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
+  #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
+#endif /* STM32H7 */
+#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
+#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
+#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
+#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
+#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
+#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
+#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
+#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
+#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
+#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
+#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
+#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#if defined(STM32F3)
+#define COMP_START                                       __HAL_COMP_ENABLE
+#define COMP_STOP                                        __HAL_COMP_DISABLE
+#define COMP_LOCK                                        __HAL_COMP_LOCK
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F302xE) || defined(STM32F302xC)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP7_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP7_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP7_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F373xC) ||defined(STM32F378xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+# endif
+#else
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+#endif
+
+#define __HAL_COMP_GET_EXTI_LINE  COMP_GET_EXTI_LINE
+
+#if defined(STM32L0) || defined(STM32L4)
+/* Note: On these STM32 families, the only argument of this macro             */
+/*       is COMP_FLAG_LOCK.                                                   */
+/*       This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle  */
+/*       argument.                                                            */
+#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__)  (__HAL_COMP_IS_LOCKED(__HANDLE__))
+#endif
+/**
+  * @}
+  */
+
+#if defined(STM32L0) || defined(STM32L4)
+/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_COMP_Start_IT       HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
+#define HAL_COMP_Stop_IT        HAL_COMP_Stop  /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
+/**
+  * @}
+  */
+#endif
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
+                          ((WAVE) == DAC_WAVE_NOISE)|| \
+                          ((WAVE) == DAC_WAVE_TRIANGLE))
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define IS_WRPAREA          IS_OB_WRPAREA
+#define IS_TYPEPROGRAM      IS_FLASH_TYPEPROGRAM
+#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
+#define IS_TYPEERASE        IS_FLASH_TYPEERASE
+#define IS_NBSECTORS        IS_FLASH_NBSECTORS
+#define IS_OB_WDG_SOURCE    IS_OB_IWDG_SOURCE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_I2C_RESET_CR2             I2C_RESET_CR2
+#define __HAL_I2C_GENERATE_START        I2C_GENERATE_START
+#if defined(STM32F1)
+#define __HAL_I2C_FREQ_RANGE            I2C_FREQRANGE
+#else
+#define __HAL_I2C_FREQ_RANGE            I2C_FREQ_RANGE
+#endif /* STM32F1 */
+#define __HAL_I2C_RISE_TIME             I2C_RISE_TIME
+#define __HAL_I2C_SPEED_STANDARD        I2C_SPEED_STANDARD
+#define __HAL_I2C_SPEED_FAST            I2C_SPEED_FAST
+#define __HAL_I2C_SPEED                 I2C_SPEED
+#define __HAL_I2C_7BIT_ADD_WRITE        I2C_7BIT_ADD_WRITE
+#define __HAL_I2C_7BIT_ADD_READ         I2C_7BIT_ADD_READ
+#define __HAL_I2C_10BIT_ADDRESS         I2C_10BIT_ADDRESS
+#define __HAL_I2C_10BIT_HEADER_WRITE    I2C_10BIT_HEADER_WRITE
+#define __HAL_I2C_10BIT_HEADER_READ     I2C_10BIT_HEADER_READ
+#define __HAL_I2C_MEM_ADD_MSB           I2C_MEM_ADD_MSB
+#define __HAL_I2C_MEM_ADD_LSB           I2C_MEM_ADD_LSB
+#define __HAL_I2C_FREQRANGE             I2C_FREQRANGE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define IS_I2S_INSTANCE                 IS_I2S_ALL_INSTANCE
+#define IS_I2S_INSTANCE_EXT             IS_I2S_ALL_INSTANCE_EXT
+
+#if defined(STM32H7)
+  #define __HAL_I2S_CLEAR_FREFLAG       __HAL_I2S_CLEAR_TIFREFLAG
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __IRDA_DISABLE                  __HAL_IRDA_DISABLE
+#define __IRDA_ENABLE                   __HAL_IRDA_ENABLE
+
+#define __HAL_IRDA_GETCLOCKSOURCE       IRDA_GETCLOCKSOURCE
+#define __HAL_IRDA_MASK_COMPUTATION     IRDA_MASK_COMPUTATION
+#define __IRDA_GETCLOCKSOURCE           IRDA_GETCLOCKSOURCE
+#define __IRDA_MASK_COMPUTATION         IRDA_MASK_COMPUTATION
+
+#define IS_IRDA_ONEBIT_SAMPLE           IS_IRDA_ONE_BIT_SAMPLE
+
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_IWDG_ENABLE_WRITE_ACCESS  IWDG_ENABLE_WRITE_ACCESS
+#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_LPTIM_ENABLE_INTERRUPT    __HAL_LPTIM_ENABLE_IT
+#define __HAL_LPTIM_DISABLE_INTERRUPT   __HAL_LPTIM_DISABLE_IT
+#define __HAL_LPTIM_GET_ITSTATUS        __HAL_LPTIM_GET_IT_SOURCE
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __OPAMP_CSR_OPAXPD                OPAMP_CSR_OPAXPD
+#define __OPAMP_CSR_S3SELX                OPAMP_CSR_S3SELX
+#define __OPAMP_CSR_S4SELX                OPAMP_CSR_S4SELX
+#define __OPAMP_CSR_S5SELX                OPAMP_CSR_S5SELX
+#define __OPAMP_CSR_S6SELX                OPAMP_CSR_S6SELX
+#define __OPAMP_CSR_OPAXCAL_L             OPAMP_CSR_OPAXCAL_L
+#define __OPAMP_CSR_OPAXCAL_H             OPAMP_CSR_OPAXCAL_H
+#define __OPAMP_CSR_OPAXLPM               OPAMP_CSR_OPAXLPM
+#define __OPAMP_CSR_ALL_SWITCHES          OPAMP_CSR_ALL_SWITCHES
+#define __OPAMP_CSR_ANAWSELX              OPAMP_CSR_ANAWSELX
+#define __OPAMP_CSR_OPAXCALOUT            OPAMP_CSR_OPAXCALOUT
+#define __OPAMP_OFFSET_TRIM_BITSPOSITION  OPAMP_OFFSET_TRIM_BITSPOSITION
+#define __OPAMP_OFFSET_TRIM_SET           OPAMP_OFFSET_TRIM_SET
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_PVD_EVENT_DISABLE                                  __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PVD_EVENT_ENABLE                                   __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PVM_EVENT_DISABLE                                  __HAL_PWR_PVM_EVENT_DISABLE
+#define __HAL_PVM_EVENT_ENABLE                                   __HAL_PWR_PVM_EVENT_ENABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
+#define __HAL_PWR_INTERNALWAKEUP_DISABLE                         HAL_PWREx_DisableInternalWakeUpLine
+#define __HAL_PWR_INTERNALWAKEUP_ENABLE                          HAL_PWREx_EnableInternalWakeUpLine
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE                    HAL_PWREx_DisablePullUpPullDownConfig
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE                     HAL_PWREx_EnablePullUpPullDownConfig
+#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER()                  do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
+#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE                         __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE                          __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE                __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE                 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE                 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE                  __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER              __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER               __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVM_DISABLE()                                  do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
+#define __HAL_PWR_PVM_ENABLE()                                   do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE                  HAL_PWREx_DisableSRAM2ContentRetention
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE                   HAL_PWREx_EnableSRAM2ContentRetention
+#define __HAL_PWR_VDDIO2_DISABLE                                 HAL_PWREx_DisableVddIO2
+#define __HAL_PWR_VDDIO2_ENABLE                                  HAL_PWREx_EnableVddIO2
+#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER                 __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER           __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_VDDUSB_DISABLE                                 HAL_PWREx_DisableVddUSB
+#define __HAL_PWR_VDDUSB_ENABLE                                  HAL_PWREx_EnableVddUSB
+
+#if defined (STM32F4)
+#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD)         __HAL_PWR_PVD_EXTI_ENABLE_IT()
+#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_DISABLE_IT()
+#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD)          __HAL_PWR_PVD_EXTI_GET_FLAG()
+#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
+#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD)     __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
+#else
+#define __HAL_PVD_EXTI_CLEAR_FLAG                                __HAL_PWR_PVD_EXTI_CLEAR_FLAG
+#define __HAL_PVD_EXTI_DISABLE_IT                                __HAL_PWR_PVD_EXTI_DISABLE_IT
+#define __HAL_PVD_EXTI_ENABLE_IT                                 __HAL_PWR_PVD_EXTI_ENABLE_IT
+#define __HAL_PVD_EXTI_GENERATE_SWIT                             __HAL_PWR_PVD_EXTI_GENERATE_SWIT
+#define __HAL_PVD_EXTI_GET_FLAG                                  __HAL_PWR_PVD_EXTI_GET_FLAG
+#endif /* STM32F4 */
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
+  * @{
+  */
+
+#define RCC_StopWakeUpClock_MSI     RCC_STOP_WAKEUPCLOCK_MSI
+#define RCC_StopWakeUpClock_HSI     RCC_STOP_WAKEUPCLOCK_HSI
+
+#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
+#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
+
+#define __ADC_CLK_DISABLE          __HAL_RCC_ADC_CLK_DISABLE
+#define __ADC_CLK_ENABLE           __HAL_RCC_ADC_CLK_ENABLE
+#define __ADC_CLK_SLEEP_DISABLE    __HAL_RCC_ADC_CLK_SLEEP_DISABLE
+#define __ADC_CLK_SLEEP_ENABLE     __HAL_RCC_ADC_CLK_SLEEP_ENABLE
+#define __ADC_FORCE_RESET          __HAL_RCC_ADC_FORCE_RESET
+#define __ADC_RELEASE_RESET        __HAL_RCC_ADC_RELEASE_RESET
+#define __ADC1_CLK_DISABLE         __HAL_RCC_ADC1_CLK_DISABLE
+#define __ADC1_CLK_ENABLE          __HAL_RCC_ADC1_CLK_ENABLE
+#define __ADC1_FORCE_RESET         __HAL_RCC_ADC1_FORCE_RESET
+#define __ADC1_RELEASE_RESET       __HAL_RCC_ADC1_RELEASE_RESET
+#define __ADC1_CLK_SLEEP_ENABLE    __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
+#define __ADC1_CLK_SLEEP_DISABLE   __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_DISABLE         __HAL_RCC_ADC2_CLK_DISABLE
+#define __ADC2_CLK_ENABLE          __HAL_RCC_ADC2_CLK_ENABLE
+#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
+#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
+#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
+#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
+#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
+#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
+#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
+#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
+#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
+#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
+#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
+#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
+#define __CRYP_CLK_SLEEP_ENABLE      __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
+#define __CRYP_CLK_SLEEP_DISABLE  __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
+#define __CRYP_CLK_ENABLE  __HAL_RCC_CRYP_CLK_ENABLE
+#define __CRYP_CLK_DISABLE  __HAL_RCC_CRYP_CLK_DISABLE
+#define __CRYP_FORCE_RESET       __HAL_RCC_CRYP_FORCE_RESET
+#define __CRYP_RELEASE_RESET  __HAL_RCC_CRYP_RELEASE_RESET
+#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
+#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
+#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
+#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
+#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
+#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
+#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
+#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
+#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
+#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
+#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
+#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
+#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
+#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
+#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
+#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
+#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
+#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
+#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
+#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
+#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
+#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
+#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN_CLK_DISABLE         __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN_CLK_ENABLE          __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN_FORCE_RESET         __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN_RELEASE_RESET       __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
+#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
+#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
+#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
+#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
+#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
+#define __COMP_CLK_DISABLE        __HAL_RCC_COMP_CLK_DISABLE
+#define __COMP_CLK_ENABLE         __HAL_RCC_COMP_CLK_ENABLE
+#define __COMP_FORCE_RESET        __HAL_RCC_COMP_FORCE_RESET
+#define __COMP_RELEASE_RESET      __HAL_RCC_COMP_RELEASE_RESET
+#define __COMP_CLK_SLEEP_ENABLE   __HAL_RCC_COMP_CLK_SLEEP_ENABLE
+#define __COMP_CLK_SLEEP_DISABLE  __HAL_RCC_COMP_CLK_SLEEP_DISABLE
+#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
+#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
+#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
+#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
+#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
+#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
+#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
+#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
+#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
+#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
+#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
+#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
+#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
+#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
+#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
+#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
+#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
+#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
+#define __DBGMCU_CLK_ENABLE     __HAL_RCC_DBGMCU_CLK_ENABLE
+#define __DBGMCU_CLK_DISABLE     __HAL_RCC_DBGMCU_CLK_DISABLE
+#define __DBGMCU_FORCE_RESET    __HAL_RCC_DBGMCU_FORCE_RESET
+#define __DBGMCU_RELEASE_RESET  __HAL_RCC_DBGMCU_RELEASE_RESET
+#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
+#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
+#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
+#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
+#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
+#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
+#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
+#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
+#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
+#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
+#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
+#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
+#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
+#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
+#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
+#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
+#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
+#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
+#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
+#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
+#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
+#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
+#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
+#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
+#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
+#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
+#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
+#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
+#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
+#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
+#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
+#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
+#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
+#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
+#define __FLITF_CLK_DISABLE       __HAL_RCC_FLITF_CLK_DISABLE
+#define __FLITF_CLK_ENABLE        __HAL_RCC_FLITF_CLK_ENABLE
+#define __FLITF_FORCE_RESET       __HAL_RCC_FLITF_FORCE_RESET
+#define __FLITF_RELEASE_RESET     __HAL_RCC_FLITF_RELEASE_RESET
+#define __FLITF_CLK_SLEEP_ENABLE  __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
+#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
+#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
+#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
+#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
+#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
+#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
+#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
+#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
+#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
+#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
+#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
+#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
+#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
+#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
+#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
+#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
+#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
+#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
+#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
+#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
+#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
+#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
+#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
+#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
+#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
+#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
+#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
+#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
+#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
+#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
+#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
+#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
+#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
+#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
+#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
+#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
+#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
+#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
+#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
+#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
+#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
+#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
+#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
+#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
+#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
+#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
+#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
+#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
+#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
+#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
+#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
+#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
+#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
+#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
+#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
+#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
+#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
+#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
+#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
+#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
+#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
+#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
+#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
+#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
+#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
+#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
+#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
+#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
+#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
+#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
+#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
+#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
+#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
+#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
+#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
+#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
+#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
+#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
+#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
+#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
+#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
+#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
+#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
+#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
+#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
+#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
+#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
+#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
+#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
+#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
+#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
+#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
+#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
+#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
+#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
+#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
+#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
+#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
+#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
+#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
+#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
+#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
+#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
+#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
+#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
+#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
+#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
+#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
+#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
+#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
+#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
+#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
+#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
+#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
+#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
+#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
+#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
+#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
+#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
+#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
+#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
+#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
+#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
+
+#if defined(STM32WB)
+#define __HAL_RCC_QSPI_CLK_DISABLE            __HAL_RCC_QUADSPI_CLK_DISABLE
+#define __HAL_RCC_QSPI_CLK_ENABLE             __HAL_RCC_QUADSPI_CLK_ENABLE
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE      __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE       __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_QSPI_FORCE_RESET            __HAL_RCC_QUADSPI_FORCE_RESET
+#define __HAL_RCC_QSPI_RELEASE_RESET          __HAL_RCC_QUADSPI_RELEASE_RESET
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED         __HAL_RCC_QUADSPI_IS_CLK_ENABLED
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED        __HAL_RCC_QUADSPI_IS_CLK_DISABLED
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED   __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED  __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED
+#define QSPI_IRQHandler QUADSPI_IRQHandler
+#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */
+
+#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
+#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
+#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
+#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
+#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
+#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
+#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
+#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
+#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
+#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
+#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
+#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
+#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
+#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
+#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
+#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
+#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
+#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
+#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
+#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
+#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
+#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
+#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
+#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
+#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
+#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
+#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
+#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
+#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
+#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
+#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
+#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
+#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
+#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
+#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
+#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
+#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
+#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
+#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
+#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
+#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
+#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
+#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
+#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
+#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
+#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
+#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
+#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
+#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
+#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
+#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
+#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
+#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
+#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
+#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
+#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
+#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
+#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
+#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
+#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
+#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
+#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
+#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
+#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
+#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
+#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
+#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
+#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
+#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
+#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
+#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
+#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
+#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
+#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
+#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
+#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
+#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
+#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
+#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
+#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
+#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
+#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
+#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
+#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
+#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
+#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
+#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
+#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
+#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
+#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
+#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
+#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
+#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
+#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
+#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
+#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
+#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
+#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
+#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
+#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
+#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
+#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
+#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
+#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
+#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
+#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
+#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
+#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
+#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
+#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
+#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
+#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
+#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
+#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
+#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
+#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
+#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
+#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
+#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
+#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
+#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
+#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
+#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
+#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
+#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
+#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
+#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
+#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
+#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
+#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
+#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
+#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
+#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
+#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
+#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
+#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
+#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
+#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
+#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
+#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
+#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
+#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
+#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
+#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
+#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
+#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
+#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
+#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
+#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
+#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
+#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
+#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
+#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
+#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
+#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
+#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
+#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
+#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
+#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
+#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
+#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
+#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
+#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
+#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
+#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
+#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
+#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
+#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
+#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
+#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
+#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
+#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
+#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
+#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
+#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
+#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
+#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
+#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
+#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
+#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
+#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
+#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
+#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
+#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
+#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
+#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
+#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
+#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
+#define __USART4_CLK_DISABLE        __HAL_RCC_UART4_CLK_DISABLE
+#define __USART4_CLK_ENABLE         __HAL_RCC_UART4_CLK_ENABLE
+#define __USART4_CLK_SLEEP_ENABLE   __HAL_RCC_UART4_CLK_SLEEP_ENABLE
+#define __USART4_CLK_SLEEP_DISABLE  __HAL_RCC_UART4_CLK_SLEEP_DISABLE
+#define __USART4_FORCE_RESET        __HAL_RCC_UART4_FORCE_RESET
+#define __USART4_RELEASE_RESET      __HAL_RCC_UART4_RELEASE_RESET
+#define __USART5_CLK_DISABLE        __HAL_RCC_UART5_CLK_DISABLE
+#define __USART5_CLK_ENABLE         __HAL_RCC_UART5_CLK_ENABLE
+#define __USART5_CLK_SLEEP_ENABLE   __HAL_RCC_UART5_CLK_SLEEP_ENABLE
+#define __USART5_CLK_SLEEP_DISABLE  __HAL_RCC_UART5_CLK_SLEEP_DISABLE
+#define __USART5_FORCE_RESET        __HAL_RCC_UART5_FORCE_RESET
+#define __USART5_RELEASE_RESET      __HAL_RCC_UART5_RELEASE_RESET
+#define __USART7_CLK_DISABLE        __HAL_RCC_UART7_CLK_DISABLE
+#define __USART7_CLK_ENABLE         __HAL_RCC_UART7_CLK_ENABLE
+#define __USART7_FORCE_RESET        __HAL_RCC_UART7_FORCE_RESET
+#define __USART7_RELEASE_RESET      __HAL_RCC_UART7_RELEASE_RESET
+#define __USART8_CLK_DISABLE        __HAL_RCC_UART8_CLK_DISABLE
+#define __USART8_CLK_ENABLE         __HAL_RCC_UART8_CLK_ENABLE
+#define __USART8_FORCE_RESET        __HAL_RCC_UART8_FORCE_RESET
+#define __USART8_RELEASE_RESET      __HAL_RCC_UART8_RELEASE_RESET
+#define __USB_CLK_DISABLE         __HAL_RCC_USB_CLK_DISABLE
+#define __USB_CLK_ENABLE          __HAL_RCC_USB_CLK_ENABLE
+#define __USB_FORCE_RESET         __HAL_RCC_USB_FORCE_RESET
+#define __USB_CLK_SLEEP_ENABLE    __HAL_RCC_USB_CLK_SLEEP_ENABLE
+#define __USB_CLK_SLEEP_DISABLE   __HAL_RCC_USB_CLK_SLEEP_DISABLE
+#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
+#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
+#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
+
+#if defined(STM32H7)
+#define __HAL_RCC_WWDG_CLK_DISABLE   __HAL_RCC_WWDG1_CLK_DISABLE
+#define __HAL_RCC_WWDG_CLK_ENABLE   __HAL_RCC_WWDG1_CLK_ENABLE
+#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE  __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE  __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE
+
+#define __HAL_RCC_WWDG_FORCE_RESET    ((void)0U)  /* Not available on the STM32H7*/
+#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/
+
+
+#define  __HAL_RCC_WWDG_IS_CLK_ENABLED    __HAL_RCC_WWDG1_IS_CLK_ENABLED
+#define  __HAL_RCC_WWDG_IS_CLK_DISABLED  __HAL_RCC_WWDG1_IS_CLK_DISABLED
+#endif
+
+#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
+#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
+#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
+#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
+#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
+#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
+
+#define __TIM21_CLK_ENABLE   __HAL_RCC_TIM21_CLK_ENABLE
+#define __TIM21_CLK_DISABLE   __HAL_RCC_TIM21_CLK_DISABLE
+#define __TIM21_FORCE_RESET   __HAL_RCC_TIM21_FORCE_RESET
+#define __TIM21_RELEASE_RESET  __HAL_RCC_TIM21_RELEASE_RESET
+#define __TIM21_CLK_SLEEP_ENABLE   __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
+#define __TIM21_CLK_SLEEP_DISABLE   __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
+#define __TIM22_CLK_ENABLE   __HAL_RCC_TIM22_CLK_ENABLE
+#define __TIM22_CLK_DISABLE   __HAL_RCC_TIM22_CLK_DISABLE
+#define __TIM22_FORCE_RESET   __HAL_RCC_TIM22_FORCE_RESET
+#define __TIM22_RELEASE_RESET  __HAL_RCC_TIM22_RELEASE_RESET
+#define __TIM22_CLK_SLEEP_ENABLE   __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
+#define __TIM22_CLK_SLEEP_DISABLE   __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
+#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
+#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
+#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
+#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
+#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
+#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
+#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
+#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
+
+#define __USB_OTG_FS_FORCE_RESET  __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __USB_OTG_FS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+#define __USB_OTG_FS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
+#define __USB_OTG_FS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
+#define __USB_OTG_HS_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_DISABLE
+#define __USB_OTG_HS_CLK_ENABLE          __HAL_RCC_USB_OTG_HS_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
+#define __TIM9_CLK_SLEEP_ENABLE          __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
+#define __TIM9_CLK_SLEEP_DISABLE  __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
+#define __TIM10_CLK_SLEEP_ENABLE  __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
+#define __TIM10_CLK_SLEEP_DISABLE  __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
+#define __TIM11_CLK_SLEEP_ENABLE  __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
+#define __TIM11_CLK_SLEEP_DISABLE  __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
+#define __ETHMACPTP_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
+#define __ETHMACPTP_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
+#define __ETHMACPTP_CLK_ENABLE          __HAL_RCC_ETHMACPTP_CLK_ENABLE
+#define __ETHMACPTP_CLK_DISABLE          __HAL_RCC_ETHMACPTP_CLK_DISABLE
+#define __HASH_CLK_ENABLE          __HAL_RCC_HASH_CLK_ENABLE
+#define __HASH_FORCE_RESET          __HAL_RCC_HASH_FORCE_RESET
+#define __HASH_RELEASE_RESET          __HAL_RCC_HASH_RELEASE_RESET
+#define __HASH_CLK_SLEEP_ENABLE          __HAL_RCC_HASH_CLK_SLEEP_ENABLE
+#define __HASH_CLK_SLEEP_DISABLE  __HAL_RCC_HASH_CLK_SLEEP_DISABLE
+#define __HASH_CLK_DISABLE            __HAL_RCC_HASH_CLK_DISABLE
+#define __SPI5_CLK_ENABLE          __HAL_RCC_SPI5_CLK_ENABLE
+#define __SPI5_CLK_DISABLE              __HAL_RCC_SPI5_CLK_DISABLE
+#define __SPI5_FORCE_RESET          __HAL_RCC_SPI5_FORCE_RESET
+#define __SPI5_RELEASE_RESET          __HAL_RCC_SPI5_RELEASE_RESET
+#define __SPI5_CLK_SLEEP_ENABLE          __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
+#define __SPI5_CLK_SLEEP_DISABLE  __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
+#define __SPI6_CLK_ENABLE          __HAL_RCC_SPI6_CLK_ENABLE
+#define __SPI6_CLK_DISABLE          __HAL_RCC_SPI6_CLK_DISABLE
+#define __SPI6_FORCE_RESET          __HAL_RCC_SPI6_FORCE_RESET
+#define __SPI6_RELEASE_RESET         __HAL_RCC_SPI6_RELEASE_RESET
+#define __SPI6_CLK_SLEEP_ENABLE          __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
+#define __SPI6_CLK_SLEEP_DISABLE  __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
+#define __LTDC_CLK_ENABLE          __HAL_RCC_LTDC_CLK_ENABLE
+#define __LTDC_CLK_DISABLE          __HAL_RCC_LTDC_CLK_DISABLE
+#define __LTDC_FORCE_RESET          __HAL_RCC_LTDC_FORCE_RESET
+#define __LTDC_RELEASE_RESET          __HAL_RCC_LTDC_RELEASE_RESET
+#define __LTDC_CLK_SLEEP_ENABLE          __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
+#define __ETHMAC_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
+#define __ETHMAC_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
+#define __ETHMACTX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
+#define __ETHMACTX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
+#define __ETHMACRX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
+#define __ETHMACRX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
+#define __TIM12_CLK_SLEEP_ENABLE  __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
+#define __TIM12_CLK_SLEEP_DISABLE  __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
+#define __TIM13_CLK_SLEEP_ENABLE  __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
+#define __TIM13_CLK_SLEEP_DISABLE  __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
+#define __TIM14_CLK_SLEEP_ENABLE  __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
+#define __TIM14_CLK_SLEEP_DISABLE  __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
+#define __BKPSRAM_CLK_ENABLE          __HAL_RCC_BKPSRAM_CLK_ENABLE
+#define __BKPSRAM_CLK_DISABLE          __HAL_RCC_BKPSRAM_CLK_DISABLE
+#define __BKPSRAM_CLK_SLEEP_ENABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
+#define __BKPSRAM_CLK_SLEEP_DISABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
+#define __CCMDATARAMEN_CLK_ENABLE  __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
+#define __CCMDATARAMEN_CLK_DISABLE  __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
+#define __USART6_CLK_ENABLE          __HAL_RCC_USART6_CLK_ENABLE
+#define __USART6_CLK_DISABLE          __HAL_RCC_USART6_CLK_DISABLE
+#define __USART6_FORCE_RESET        __HAL_RCC_USART6_FORCE_RESET
+#define __USART6_RELEASE_RESET        __HAL_RCC_USART6_RELEASE_RESET
+#define __USART6_CLK_SLEEP_ENABLE  __HAL_RCC_USART6_CLK_SLEEP_ENABLE
+#define __USART6_CLK_SLEEP_DISABLE  __HAL_RCC_USART6_CLK_SLEEP_DISABLE
+#define __SPI4_CLK_ENABLE          __HAL_RCC_SPI4_CLK_ENABLE
+#define __SPI4_CLK_DISABLE          __HAL_RCC_SPI4_CLK_DISABLE
+#define __SPI4_FORCE_RESET          __HAL_RCC_SPI4_FORCE_RESET
+#define __SPI4_RELEASE_RESET        __HAL_RCC_SPI4_RELEASE_RESET
+#define __SPI4_CLK_SLEEP_ENABLE   __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
+#define __SPI4_CLK_SLEEP_DISABLE  __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
+#define __GPIOI_CLK_ENABLE          __HAL_RCC_GPIOI_CLK_ENABLE
+#define __GPIOI_CLK_DISABLE          __HAL_RCC_GPIOI_CLK_DISABLE
+#define __GPIOI_FORCE_RESET          __HAL_RCC_GPIOI_FORCE_RESET
+#define __GPIOI_RELEASE_RESET          __HAL_RCC_GPIOI_RELEASE_RESET
+#define __GPIOI_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
+#define __GPIOI_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
+#define __GPIOJ_CLK_ENABLE          __HAL_RCC_GPIOJ_CLK_ENABLE
+#define __GPIOJ_CLK_DISABLE          __HAL_RCC_GPIOJ_CLK_DISABLE
+#define __GPIOJ_FORCE_RESET         __HAL_RCC_GPIOJ_FORCE_RESET
+#define __GPIOJ_RELEASE_RESET          __HAL_RCC_GPIOJ_RELEASE_RESET
+#define __GPIOJ_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
+#define __GPIOJ_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
+#define __GPIOK_CLK_ENABLE          __HAL_RCC_GPIOK_CLK_ENABLE
+#define __GPIOK_CLK_DISABLE          __HAL_RCC_GPIOK_CLK_DISABLE
+#define __GPIOK_RELEASE_RESET          __HAL_RCC_GPIOK_RELEASE_RESET
+#define __GPIOK_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
+#define __GPIOK_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
+#define __ETH_CLK_ENABLE          __HAL_RCC_ETH_CLK_ENABLE
+#define __ETH_CLK_DISABLE          __HAL_RCC_ETH_CLK_DISABLE
+#define __DCMI_CLK_ENABLE          __HAL_RCC_DCMI_CLK_ENABLE
+#define __DCMI_CLK_DISABLE          __HAL_RCC_DCMI_CLK_DISABLE
+#define __DCMI_FORCE_RESET          __HAL_RCC_DCMI_FORCE_RESET
+#define __DCMI_RELEASE_RESET          __HAL_RCC_DCMI_RELEASE_RESET
+#define __DCMI_CLK_SLEEP_ENABLE   __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
+#define __DCMI_CLK_SLEEP_DISABLE  __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
+#define __UART7_CLK_ENABLE          __HAL_RCC_UART7_CLK_ENABLE
+#define __UART7_CLK_DISABLE          __HAL_RCC_UART7_CLK_DISABLE
+#define __UART7_RELEASE_RESET       __HAL_RCC_UART7_RELEASE_RESET
+#define __UART7_FORCE_RESET       __HAL_RCC_UART7_FORCE_RESET
+#define __UART7_CLK_SLEEP_ENABLE  __HAL_RCC_UART7_CLK_SLEEP_ENABLE
+#define __UART7_CLK_SLEEP_DISABLE  __HAL_RCC_UART7_CLK_SLEEP_DISABLE
+#define __UART8_CLK_ENABLE          __HAL_RCC_UART8_CLK_ENABLE
+#define __UART8_CLK_DISABLE          __HAL_RCC_UART8_CLK_DISABLE
+#define __UART8_FORCE_RESET          __HAL_RCC_UART8_FORCE_RESET
+#define __UART8_RELEASE_RESET          __HAL_RCC_UART8_RELEASE_RESET
+#define __UART8_CLK_SLEEP_ENABLE  __HAL_RCC_UART8_CLK_SLEEP_ENABLE
+#define __UART8_CLK_SLEEP_DISABLE  __HAL_RCC_UART8_CLK_SLEEP_DISABLE
+#define __OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __OTGHSULPI_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __OTGHSULPI_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
+#define __HAL_RCC_OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __HAL_RCC_OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE      __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE     __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED  __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
+#define __SRAM3_CLK_SLEEP_ENABLE       __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_ENABLE        __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_DISABLE       __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
+#define __DAC_CLK_SLEEP_ENABLE         __HAL_RCC_DAC_CLK_SLEEP_ENABLE
+#define __DAC_CLK_SLEEP_DISABLE        __HAL_RCC_DAC_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_SLEEP_ENABLE        __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
+#define __ADC2_CLK_SLEEP_DISABLE       __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
+#define __ADC3_CLK_SLEEP_ENABLE        __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
+#define __ADC3_CLK_SLEEP_DISABLE       __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
+#define __FSMC_FORCE_RESET             __HAL_RCC_FSMC_FORCE_RESET
+#define __FSMC_RELEASE_RESET           __HAL_RCC_FSMC_RELEASE_RESET
+#define __FSMC_CLK_SLEEP_ENABLE        __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
+#define __FSMC_CLK_SLEEP_DISABLE       __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
+#define __SDIO_FORCE_RESET             __HAL_RCC_SDIO_FORCE_RESET
+#define __SDIO_RELEASE_RESET           __HAL_RCC_SDIO_RELEASE_RESET
+#define __SDIO_CLK_SLEEP_DISABLE       __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __SDIO_CLK_SLEEP_ENABLE        __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_ENABLE             __HAL_RCC_DMA2D_CLK_ENABLE
+#define __DMA2D_CLK_DISABLE            __HAL_RCC_DMA2D_CLK_DISABLE
+#define __DMA2D_FORCE_RESET            __HAL_RCC_DMA2D_FORCE_RESET
+#define __DMA2D_RELEASE_RESET          __HAL_RCC_DMA2D_RELEASE_RESET
+#define __DMA2D_CLK_SLEEP_ENABLE       __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_SLEEP_DISABLE      __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
+
+/* alias define maintained for legacy */
+#define __HAL_RCC_OTGFS_FORCE_RESET    __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __HAL_RCC_OTGFS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+
+#define __ADC12_CLK_ENABLE          __HAL_RCC_ADC12_CLK_ENABLE
+#define __ADC12_CLK_DISABLE         __HAL_RCC_ADC12_CLK_DISABLE
+#define __ADC34_CLK_ENABLE          __HAL_RCC_ADC34_CLK_ENABLE
+#define __ADC34_CLK_DISABLE         __HAL_RCC_ADC34_CLK_DISABLE
+#define __DAC2_CLK_ENABLE           __HAL_RCC_DAC2_CLK_ENABLE
+#define __DAC2_CLK_DISABLE          __HAL_RCC_DAC2_CLK_DISABLE
+#define __TIM18_CLK_ENABLE          __HAL_RCC_TIM18_CLK_ENABLE
+#define __TIM18_CLK_DISABLE         __HAL_RCC_TIM18_CLK_DISABLE
+#define __TIM19_CLK_ENABLE          __HAL_RCC_TIM19_CLK_ENABLE
+#define __TIM19_CLK_DISABLE         __HAL_RCC_TIM19_CLK_DISABLE
+#define __TIM20_CLK_ENABLE          __HAL_RCC_TIM20_CLK_ENABLE
+#define __TIM20_CLK_DISABLE         __HAL_RCC_TIM20_CLK_DISABLE
+#define __HRTIM1_CLK_ENABLE         __HAL_RCC_HRTIM1_CLK_ENABLE
+#define __HRTIM1_CLK_DISABLE        __HAL_RCC_HRTIM1_CLK_DISABLE
+#define __SDADC1_CLK_ENABLE         __HAL_RCC_SDADC1_CLK_ENABLE
+#define __SDADC2_CLK_ENABLE         __HAL_RCC_SDADC2_CLK_ENABLE
+#define __SDADC3_CLK_ENABLE         __HAL_RCC_SDADC3_CLK_ENABLE
+#define __SDADC1_CLK_DISABLE        __HAL_RCC_SDADC1_CLK_DISABLE
+#define __SDADC2_CLK_DISABLE        __HAL_RCC_SDADC2_CLK_DISABLE
+#define __SDADC3_CLK_DISABLE        __HAL_RCC_SDADC3_CLK_DISABLE
+
+#define __ADC12_FORCE_RESET         __HAL_RCC_ADC12_FORCE_RESET
+#define __ADC12_RELEASE_RESET       __HAL_RCC_ADC12_RELEASE_RESET
+#define __ADC34_FORCE_RESET         __HAL_RCC_ADC34_FORCE_RESET
+#define __ADC34_RELEASE_RESET       __HAL_RCC_ADC34_RELEASE_RESET
+#define __DAC2_FORCE_RESET          __HAL_RCC_DAC2_FORCE_RESET
+#define __DAC2_RELEASE_RESET        __HAL_RCC_DAC2_RELEASE_RESET
+#define __TIM18_FORCE_RESET         __HAL_RCC_TIM18_FORCE_RESET
+#define __TIM18_RELEASE_RESET       __HAL_RCC_TIM18_RELEASE_RESET
+#define __TIM19_FORCE_RESET         __HAL_RCC_TIM19_FORCE_RESET
+#define __TIM19_RELEASE_RESET       __HAL_RCC_TIM19_RELEASE_RESET
+#define __TIM20_FORCE_RESET         __HAL_RCC_TIM20_FORCE_RESET
+#define __TIM20_RELEASE_RESET       __HAL_RCC_TIM20_RELEASE_RESET
+#define __HRTIM1_FORCE_RESET        __HAL_RCC_HRTIM1_FORCE_RESET
+#define __HRTIM1_RELEASE_RESET      __HAL_RCC_HRTIM1_RELEASE_RESET
+#define __SDADC1_FORCE_RESET        __HAL_RCC_SDADC1_FORCE_RESET
+#define __SDADC2_FORCE_RESET        __HAL_RCC_SDADC2_FORCE_RESET
+#define __SDADC3_FORCE_RESET        __HAL_RCC_SDADC3_FORCE_RESET
+#define __SDADC1_RELEASE_RESET      __HAL_RCC_SDADC1_RELEASE_RESET
+#define __SDADC2_RELEASE_RESET      __HAL_RCC_SDADC2_RELEASE_RESET
+#define __SDADC3_RELEASE_RESET      __HAL_RCC_SDADC3_RELEASE_RESET
+
+#define __ADC1_IS_CLK_ENABLED       __HAL_RCC_ADC1_IS_CLK_ENABLED
+#define __ADC1_IS_CLK_DISABLED      __HAL_RCC_ADC1_IS_CLK_DISABLED
+#define __ADC12_IS_CLK_ENABLED      __HAL_RCC_ADC12_IS_CLK_ENABLED
+#define __ADC12_IS_CLK_DISABLED     __HAL_RCC_ADC12_IS_CLK_DISABLED
+#define __ADC34_IS_CLK_ENABLED      __HAL_RCC_ADC34_IS_CLK_ENABLED
+#define __ADC34_IS_CLK_DISABLED     __HAL_RCC_ADC34_IS_CLK_DISABLED
+#define __CEC_IS_CLK_ENABLED        __HAL_RCC_CEC_IS_CLK_ENABLED
+#define __CEC_IS_CLK_DISABLED       __HAL_RCC_CEC_IS_CLK_DISABLED
+#define __CRC_IS_CLK_ENABLED        __HAL_RCC_CRC_IS_CLK_ENABLED
+#define __CRC_IS_CLK_DISABLED       __HAL_RCC_CRC_IS_CLK_DISABLED
+#define __DAC1_IS_CLK_ENABLED       __HAL_RCC_DAC1_IS_CLK_ENABLED
+#define __DAC1_IS_CLK_DISABLED      __HAL_RCC_DAC1_IS_CLK_DISABLED
+#define __DAC2_IS_CLK_ENABLED       __HAL_RCC_DAC2_IS_CLK_ENABLED
+#define __DAC2_IS_CLK_DISABLED      __HAL_RCC_DAC2_IS_CLK_DISABLED
+#define __DMA1_IS_CLK_ENABLED       __HAL_RCC_DMA1_IS_CLK_ENABLED
+#define __DMA1_IS_CLK_DISABLED      __HAL_RCC_DMA1_IS_CLK_DISABLED
+#define __DMA2_IS_CLK_ENABLED       __HAL_RCC_DMA2_IS_CLK_ENABLED
+#define __DMA2_IS_CLK_DISABLED      __HAL_RCC_DMA2_IS_CLK_DISABLED
+#define __FLITF_IS_CLK_ENABLED      __HAL_RCC_FLITF_IS_CLK_ENABLED
+#define __FLITF_IS_CLK_DISABLED     __HAL_RCC_FLITF_IS_CLK_DISABLED
+#define __FMC_IS_CLK_ENABLED        __HAL_RCC_FMC_IS_CLK_ENABLED
+#define __FMC_IS_CLK_DISABLED       __HAL_RCC_FMC_IS_CLK_DISABLED
+#define __GPIOA_IS_CLK_ENABLED      __HAL_RCC_GPIOA_IS_CLK_ENABLED
+#define __GPIOA_IS_CLK_DISABLED     __HAL_RCC_GPIOA_IS_CLK_DISABLED
+#define __GPIOB_IS_CLK_ENABLED      __HAL_RCC_GPIOB_IS_CLK_ENABLED
+#define __GPIOB_IS_CLK_DISABLED     __HAL_RCC_GPIOB_IS_CLK_DISABLED
+#define __GPIOC_IS_CLK_ENABLED      __HAL_RCC_GPIOC_IS_CLK_ENABLED
+#define __GPIOC_IS_CLK_DISABLED     __HAL_RCC_GPIOC_IS_CLK_DISABLED
+#define __GPIOD_IS_CLK_ENABLED      __HAL_RCC_GPIOD_IS_CLK_ENABLED
+#define __GPIOD_IS_CLK_DISABLED     __HAL_RCC_GPIOD_IS_CLK_DISABLED
+#define __GPIOE_IS_CLK_ENABLED      __HAL_RCC_GPIOE_IS_CLK_ENABLED
+#define __GPIOE_IS_CLK_DISABLED     __HAL_RCC_GPIOE_IS_CLK_DISABLED
+#define __GPIOF_IS_CLK_ENABLED      __HAL_RCC_GPIOF_IS_CLK_ENABLED
+#define __GPIOF_IS_CLK_DISABLED     __HAL_RCC_GPIOF_IS_CLK_DISABLED
+#define __GPIOG_IS_CLK_ENABLED      __HAL_RCC_GPIOG_IS_CLK_ENABLED
+#define __GPIOG_IS_CLK_DISABLED     __HAL_RCC_GPIOG_IS_CLK_DISABLED
+#define __GPIOH_IS_CLK_ENABLED      __HAL_RCC_GPIOH_IS_CLK_ENABLED
+#define __GPIOH_IS_CLK_DISABLED     __HAL_RCC_GPIOH_IS_CLK_DISABLED
+#define __HRTIM1_IS_CLK_ENABLED     __HAL_RCC_HRTIM1_IS_CLK_ENABLED
+#define __HRTIM1_IS_CLK_DISABLED    __HAL_RCC_HRTIM1_IS_CLK_DISABLED
+#define __I2C1_IS_CLK_ENABLED       __HAL_RCC_I2C1_IS_CLK_ENABLED
+#define __I2C1_IS_CLK_DISABLED      __HAL_RCC_I2C1_IS_CLK_DISABLED
+#define __I2C2_IS_CLK_ENABLED       __HAL_RCC_I2C2_IS_CLK_ENABLED
+#define __I2C2_IS_CLK_DISABLED      __HAL_RCC_I2C2_IS_CLK_DISABLED
+#define __I2C3_IS_CLK_ENABLED       __HAL_RCC_I2C3_IS_CLK_ENABLED
+#define __I2C3_IS_CLK_DISABLED      __HAL_RCC_I2C3_IS_CLK_DISABLED
+#define __PWR_IS_CLK_ENABLED        __HAL_RCC_PWR_IS_CLK_ENABLED
+#define __PWR_IS_CLK_DISABLED       __HAL_RCC_PWR_IS_CLK_DISABLED
+#define __SYSCFG_IS_CLK_ENABLED     __HAL_RCC_SYSCFG_IS_CLK_ENABLED
+#define __SYSCFG_IS_CLK_DISABLED    __HAL_RCC_SYSCFG_IS_CLK_DISABLED
+#define __SPI1_IS_CLK_ENABLED       __HAL_RCC_SPI1_IS_CLK_ENABLED
+#define __SPI1_IS_CLK_DISABLED      __HAL_RCC_SPI1_IS_CLK_DISABLED
+#define __SPI2_IS_CLK_ENABLED       __HAL_RCC_SPI2_IS_CLK_ENABLED
+#define __SPI2_IS_CLK_DISABLED      __HAL_RCC_SPI2_IS_CLK_DISABLED
+#define __SPI3_IS_CLK_ENABLED       __HAL_RCC_SPI3_IS_CLK_ENABLED
+#define __SPI3_IS_CLK_DISABLED      __HAL_RCC_SPI3_IS_CLK_DISABLED
+#define __SPI4_IS_CLK_ENABLED       __HAL_RCC_SPI4_IS_CLK_ENABLED
+#define __SPI4_IS_CLK_DISABLED      __HAL_RCC_SPI4_IS_CLK_DISABLED
+#define __SDADC1_IS_CLK_ENABLED     __HAL_RCC_SDADC1_IS_CLK_ENABLED
+#define __SDADC1_IS_CLK_DISABLED    __HAL_RCC_SDADC1_IS_CLK_DISABLED
+#define __SDADC2_IS_CLK_ENABLED     __HAL_RCC_SDADC2_IS_CLK_ENABLED
+#define __SDADC2_IS_CLK_DISABLED    __HAL_RCC_SDADC2_IS_CLK_DISABLED
+#define __SDADC3_IS_CLK_ENABLED     __HAL_RCC_SDADC3_IS_CLK_ENABLED
+#define __SDADC3_IS_CLK_DISABLED    __HAL_RCC_SDADC3_IS_CLK_DISABLED
+#define __SRAM_IS_CLK_ENABLED       __HAL_RCC_SRAM_IS_CLK_ENABLED
+#define __SRAM_IS_CLK_DISABLED      __HAL_RCC_SRAM_IS_CLK_DISABLED
+#define __TIM1_IS_CLK_ENABLED       __HAL_RCC_TIM1_IS_CLK_ENABLED
+#define __TIM1_IS_CLK_DISABLED      __HAL_RCC_TIM1_IS_CLK_DISABLED
+#define __TIM2_IS_CLK_ENABLED       __HAL_RCC_TIM2_IS_CLK_ENABLED
+#define __TIM2_IS_CLK_DISABLED      __HAL_RCC_TIM2_IS_CLK_DISABLED
+#define __TIM3_IS_CLK_ENABLED       __HAL_RCC_TIM3_IS_CLK_ENABLED
+#define __TIM3_IS_CLK_DISABLED      __HAL_RCC_TIM3_IS_CLK_DISABLED
+#define __TIM4_IS_CLK_ENABLED       __HAL_RCC_TIM4_IS_CLK_ENABLED
+#define __TIM4_IS_CLK_DISABLED      __HAL_RCC_TIM4_IS_CLK_DISABLED
+#define __TIM5_IS_CLK_ENABLED       __HAL_RCC_TIM5_IS_CLK_ENABLED
+#define __TIM5_IS_CLK_DISABLED      __HAL_RCC_TIM5_IS_CLK_DISABLED
+#define __TIM6_IS_CLK_ENABLED       __HAL_RCC_TIM6_IS_CLK_ENABLED
+#define __TIM6_IS_CLK_DISABLED      __HAL_RCC_TIM6_IS_CLK_DISABLED
+#define __TIM7_IS_CLK_ENABLED       __HAL_RCC_TIM7_IS_CLK_ENABLED
+#define __TIM7_IS_CLK_DISABLED      __HAL_RCC_TIM7_IS_CLK_DISABLED
+#define __TIM8_IS_CLK_ENABLED       __HAL_RCC_TIM8_IS_CLK_ENABLED
+#define __TIM8_IS_CLK_DISABLED      __HAL_RCC_TIM8_IS_CLK_DISABLED
+#define __TIM12_IS_CLK_ENABLED      __HAL_RCC_TIM12_IS_CLK_ENABLED
+#define __TIM12_IS_CLK_DISABLED     __HAL_RCC_TIM12_IS_CLK_DISABLED
+#define __TIM13_IS_CLK_ENABLED      __HAL_RCC_TIM13_IS_CLK_ENABLED
+#define __TIM13_IS_CLK_DISABLED     __HAL_RCC_TIM13_IS_CLK_DISABLED
+#define __TIM14_IS_CLK_ENABLED      __HAL_RCC_TIM14_IS_CLK_ENABLED
+#define __TIM14_IS_CLK_DISABLED     __HAL_RCC_TIM14_IS_CLK_DISABLED
+#define __TIM15_IS_CLK_ENABLED      __HAL_RCC_TIM15_IS_CLK_ENABLED
+#define __TIM15_IS_CLK_DISABLED     __HAL_RCC_TIM15_IS_CLK_DISABLED
+#define __TIM16_IS_CLK_ENABLED      __HAL_RCC_TIM16_IS_CLK_ENABLED
+#define __TIM16_IS_CLK_DISABLED     __HAL_RCC_TIM16_IS_CLK_DISABLED
+#define __TIM17_IS_CLK_ENABLED      __HAL_RCC_TIM17_IS_CLK_ENABLED
+#define __TIM17_IS_CLK_DISABLED     __HAL_RCC_TIM17_IS_CLK_DISABLED
+#define __TIM18_IS_CLK_ENABLED      __HAL_RCC_TIM18_IS_CLK_ENABLED
+#define __TIM18_IS_CLK_DISABLED     __HAL_RCC_TIM18_IS_CLK_DISABLED
+#define __TIM19_IS_CLK_ENABLED      __HAL_RCC_TIM19_IS_CLK_ENABLED
+#define __TIM19_IS_CLK_DISABLED     __HAL_RCC_TIM19_IS_CLK_DISABLED
+#define __TIM20_IS_CLK_ENABLED      __HAL_RCC_TIM20_IS_CLK_ENABLED
+#define __TIM20_IS_CLK_DISABLED     __HAL_RCC_TIM20_IS_CLK_DISABLED
+#define __TSC_IS_CLK_ENABLED        __HAL_RCC_TSC_IS_CLK_ENABLED
+#define __TSC_IS_CLK_DISABLED       __HAL_RCC_TSC_IS_CLK_DISABLED
+#define __UART4_IS_CLK_ENABLED      __HAL_RCC_UART4_IS_CLK_ENABLED
+#define __UART4_IS_CLK_DISABLED     __HAL_RCC_UART4_IS_CLK_DISABLED
+#define __UART5_IS_CLK_ENABLED      __HAL_RCC_UART5_IS_CLK_ENABLED
+#define __UART5_IS_CLK_DISABLED     __HAL_RCC_UART5_IS_CLK_DISABLED
+#define __USART1_IS_CLK_ENABLED     __HAL_RCC_USART1_IS_CLK_ENABLED
+#define __USART1_IS_CLK_DISABLED    __HAL_RCC_USART1_IS_CLK_DISABLED
+#define __USART2_IS_CLK_ENABLED     __HAL_RCC_USART2_IS_CLK_ENABLED
+#define __USART2_IS_CLK_DISABLED    __HAL_RCC_USART2_IS_CLK_DISABLED
+#define __USART3_IS_CLK_ENABLED     __HAL_RCC_USART3_IS_CLK_ENABLED
+#define __USART3_IS_CLK_DISABLED    __HAL_RCC_USART3_IS_CLK_DISABLED
+#define __USB_IS_CLK_ENABLED        __HAL_RCC_USB_IS_CLK_ENABLED
+#define __USB_IS_CLK_DISABLED       __HAL_RCC_USB_IS_CLK_DISABLED
+#define __WWDG_IS_CLK_ENABLED       __HAL_RCC_WWDG_IS_CLK_ENABLED
+#define __WWDG_IS_CLK_DISABLED      __HAL_RCC_WWDG_IS_CLK_DISABLED
+
+#if defined(STM32L1)
+#define __HAL_RCC_CRYP_CLK_DISABLE         __HAL_RCC_AES_CLK_DISABLE
+#define __HAL_RCC_CRYP_CLK_ENABLE          __HAL_RCC_AES_CLK_ENABLE
+#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE   __HAL_RCC_AES_CLK_SLEEP_DISABLE
+#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE    __HAL_RCC_AES_CLK_SLEEP_ENABLE
+#define __HAL_RCC_CRYP_FORCE_RESET         __HAL_RCC_AES_FORCE_RESET
+#define __HAL_RCC_CRYP_RELEASE_RESET       __HAL_RCC_AES_RELEASE_RESET
+#endif /* STM32L1 */
+
+#if defined(STM32F4)
+#define __HAL_RCC_SDMMC1_FORCE_RESET       __HAL_RCC_SDIO_FORCE_RESET
+#define __HAL_RCC_SDMMC1_RELEASE_RESET     __HAL_RCC_SDIO_RELEASE_RESET
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE  __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDMMC1_CLK_ENABLE        __HAL_RCC_SDIO_CLK_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_DISABLE       __HAL_RCC_SDIO_CLK_DISABLE
+#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED    __HAL_RCC_SDIO_IS_CLK_ENABLED
+#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED   __HAL_RCC_SDIO_IS_CLK_DISABLED
+#define Sdmmc1ClockSelection               SdioClockSelection
+#define RCC_PERIPHCLK_SDMMC1               RCC_PERIPHCLK_SDIO
+#define RCC_SDMMC1CLKSOURCE_CLK48          RCC_SDIOCLKSOURCE_CK48
+#define RCC_SDMMC1CLKSOURCE_SYSCLK         RCC_SDIOCLKSOURCE_SYSCLK
+#define __HAL_RCC_SDMMC1_CONFIG            __HAL_RCC_SDIO_CONFIG
+#define __HAL_RCC_GET_SDMMC1_SOURCE        __HAL_RCC_GET_SDIO_SOURCE
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define __HAL_RCC_SDIO_FORCE_RESET         __HAL_RCC_SDMMC1_FORCE_RESET
+#define __HAL_RCC_SDIO_RELEASE_RESET       __HAL_RCC_SDMMC1_RELEASE_RESET
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE    __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE   __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDIO_CLK_ENABLE          __HAL_RCC_SDMMC1_CLK_ENABLE
+#define __HAL_RCC_SDIO_CLK_DISABLE         __HAL_RCC_SDMMC1_CLK_DISABLE
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED      __HAL_RCC_SDMMC1_IS_CLK_ENABLED
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED     __HAL_RCC_SDMMC1_IS_CLK_DISABLED
+#define SdioClockSelection                 Sdmmc1ClockSelection
+#define RCC_PERIPHCLK_SDIO                 RCC_PERIPHCLK_SDMMC1
+#define __HAL_RCC_SDIO_CONFIG              __HAL_RCC_SDMMC1_CONFIG
+#define __HAL_RCC_GET_SDIO_SOURCE          __HAL_RCC_GET_SDMMC1_SOURCE
+#endif
+
+#if defined(STM32F7)
+#define RCC_SDIOCLKSOURCE_CLK48             RCC_SDMMC1CLKSOURCE_CLK48
+#define RCC_SDIOCLKSOURCE_SYSCLK           RCC_SDMMC1CLKSOURCE_SYSCLK
+#endif
+
+#if defined(STM32H7)
+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()              __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()         __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()             __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE()        __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET()             __HAL_RCC_USB1_OTG_HS_FORCE_RESET()
+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()           __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()        __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()   __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()       __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE()  __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
+
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()             __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE()        __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE()            __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE()       __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()            __HAL_RCC_USB2_OTG_FS_FORCE_RESET()
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET()          __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()       __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE()  __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE()      __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()
+#endif
+
+#define __HAL_RCC_I2SCLK            __HAL_RCC_I2S_CONFIG
+#define __HAL_RCC_I2SCLK_CONFIG     __HAL_RCC_I2S_CONFIG
+
+#define __RCC_PLLSRC                RCC_GET_PLL_OSCSOURCE
+
+#define IS_RCC_MSIRANGE             IS_RCC_MSI_CLOCK_RANGE
+#define IS_RCC_RTCCLK_SOURCE        IS_RCC_RTCCLKSOURCE
+#define IS_RCC_SYSCLK_DIV           IS_RCC_HCLK
+#define IS_RCC_HCLK_DIV             IS_RCC_PCLK
+#define IS_RCC_PERIPHCLK            IS_RCC_PERIPHCLOCK
+
+#define RCC_IT_HSI14                RCC_IT_HSI14RDY
+
+#define RCC_IT_CSSLSE               RCC_IT_LSECSS
+#define RCC_IT_CSSHSE               RCC_IT_CSS
+
+#define RCC_PLLMUL_3                RCC_PLL_MUL3
+#define RCC_PLLMUL_4                RCC_PLL_MUL4
+#define RCC_PLLMUL_6                RCC_PLL_MUL6
+#define RCC_PLLMUL_8                RCC_PLL_MUL8
+#define RCC_PLLMUL_12               RCC_PLL_MUL12
+#define RCC_PLLMUL_16               RCC_PLL_MUL16
+#define RCC_PLLMUL_24               RCC_PLL_MUL24
+#define RCC_PLLMUL_32               RCC_PLL_MUL32
+#define RCC_PLLMUL_48               RCC_PLL_MUL48
+
+#define RCC_PLLDIV_2                RCC_PLL_DIV2
+#define RCC_PLLDIV_3                RCC_PLL_DIV3
+#define RCC_PLLDIV_4                RCC_PLL_DIV4
+
+#define IS_RCC_MCOSOURCE            IS_RCC_MCO1SOURCE
+#define __HAL_RCC_MCO_CONFIG        __HAL_RCC_MCO1_CONFIG
+#define RCC_MCO_NODIV               RCC_MCODIV_1
+#define RCC_MCO_DIV1                RCC_MCODIV_1
+#define RCC_MCO_DIV2                RCC_MCODIV_2
+#define RCC_MCO_DIV4                RCC_MCODIV_4
+#define RCC_MCO_DIV8                RCC_MCODIV_8
+#define RCC_MCO_DIV16               RCC_MCODIV_16
+#define RCC_MCO_DIV32               RCC_MCODIV_32
+#define RCC_MCO_DIV64               RCC_MCODIV_64
+#define RCC_MCO_DIV128              RCC_MCODIV_128
+#define RCC_MCOSOURCE_NONE          RCC_MCO1SOURCE_NOCLOCK
+#define RCC_MCOSOURCE_LSI           RCC_MCO1SOURCE_LSI
+#define RCC_MCOSOURCE_LSE           RCC_MCO1SOURCE_LSE
+#define RCC_MCOSOURCE_SYSCLK        RCC_MCO1SOURCE_SYSCLK
+#define RCC_MCOSOURCE_HSI           RCC_MCO1SOURCE_HSI
+#define RCC_MCOSOURCE_HSI14         RCC_MCO1SOURCE_HSI14
+#define RCC_MCOSOURCE_HSI48         RCC_MCO1SOURCE_HSI48
+#define RCC_MCOSOURCE_HSE           RCC_MCO1SOURCE_HSE
+#define RCC_MCOSOURCE_PLLCLK_DIV1   RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_NODIV  RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_DIV2   RCC_MCO1SOURCE_PLLCLK_DIV2
+
+#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
+#define RCC_RTCCLKSOURCE_NO_CLK     RCC_RTCCLKSOURCE_NONE
+#else
+#define RCC_RTCCLKSOURCE_NONE       RCC_RTCCLKSOURCE_NO_CLK
+#endif
+
+#define RCC_USBCLK_PLLSAI1          RCC_USBCLKSOURCE_PLLSAI1
+#define RCC_USBCLK_PLL              RCC_USBCLKSOURCE_PLL
+#define RCC_USBCLK_MSI              RCC_USBCLKSOURCE_MSI
+#define RCC_USBCLKSOURCE_PLLCLK     RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1          RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1_5        RCC_USBCLKSOURCE_PLL_DIV1_5
+#define RCC_USBPLLCLK_DIV2          RCC_USBCLKSOURCE_PLL_DIV2
+#define RCC_USBPLLCLK_DIV3          RCC_USBCLKSOURCE_PLL_DIV3
+
+#define HSION_BitNumber        RCC_HSION_BIT_NUMBER
+#define HSION_BITNUMBER        RCC_HSION_BIT_NUMBER
+#define HSEON_BitNumber        RCC_HSEON_BIT_NUMBER
+#define HSEON_BITNUMBER        RCC_HSEON_BIT_NUMBER
+#define MSION_BITNUMBER        RCC_MSION_BIT_NUMBER
+#define CSSON_BitNumber        RCC_CSSON_BIT_NUMBER
+#define CSSON_BITNUMBER        RCC_CSSON_BIT_NUMBER
+#define PLLON_BitNumber        RCC_PLLON_BIT_NUMBER
+#define PLLON_BITNUMBER        RCC_PLLON_BIT_NUMBER
+#define PLLI2SON_BitNumber     RCC_PLLI2SON_BIT_NUMBER
+#define I2SSRC_BitNumber       RCC_I2SSRC_BIT_NUMBER
+#define RTCEN_BitNumber        RCC_RTCEN_BIT_NUMBER
+#define RTCEN_BITNUMBER        RCC_RTCEN_BIT_NUMBER
+#define BDRST_BitNumber        RCC_BDRST_BIT_NUMBER
+#define BDRST_BITNUMBER        RCC_BDRST_BIT_NUMBER
+#define RTCRST_BITNUMBER       RCC_RTCRST_BIT_NUMBER
+#define LSION_BitNumber        RCC_LSION_BIT_NUMBER
+#define LSION_BITNUMBER        RCC_LSION_BIT_NUMBER
+#define LSEON_BitNumber        RCC_LSEON_BIT_NUMBER
+#define LSEON_BITNUMBER        RCC_LSEON_BIT_NUMBER
+#define LSEBYP_BITNUMBER       RCC_LSEBYP_BIT_NUMBER
+#define PLLSAION_BitNumber     RCC_PLLSAION_BIT_NUMBER
+#define TIMPRE_BitNumber       RCC_TIMPRE_BIT_NUMBER
+#define RMVF_BitNumber         RCC_RMVF_BIT_NUMBER
+#define RMVF_BITNUMBER         RCC_RMVF_BIT_NUMBER
+#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
+#define CR_BYTE2_ADDRESS       RCC_CR_BYTE2_ADDRESS
+#define CIR_BYTE1_ADDRESS      RCC_CIR_BYTE1_ADDRESS
+#define CIR_BYTE2_ADDRESS      RCC_CIR_BYTE2_ADDRESS
+#define BDCR_BYTE0_ADDRESS     RCC_BDCR_BYTE0_ADDRESS
+#define DBP_TIMEOUT_VALUE      RCC_DBP_TIMEOUT_VALUE
+#define LSE_TIMEOUT_VALUE      RCC_LSE_TIMEOUT_VALUE
+
+#define CR_HSION_BB            RCC_CR_HSION_BB
+#define CR_CSSON_BB            RCC_CR_CSSON_BB
+#define CR_PLLON_BB            RCC_CR_PLLON_BB
+#define CR_PLLI2SON_BB         RCC_CR_PLLI2SON_BB
+#define CR_MSION_BB            RCC_CR_MSION_BB
+#define CSR_LSION_BB           RCC_CSR_LSION_BB
+#define CSR_LSEON_BB           RCC_CSR_LSEON_BB
+#define CSR_LSEBYP_BB          RCC_CSR_LSEBYP_BB
+#define CSR_RTCEN_BB           RCC_CSR_RTCEN_BB
+#define CSR_RTCRST_BB          RCC_CSR_RTCRST_BB
+#define CFGR_I2SSRC_BB         RCC_CFGR_I2SSRC_BB
+#define BDCR_RTCEN_BB          RCC_BDCR_RTCEN_BB
+#define BDCR_BDRST_BB          RCC_BDCR_BDRST_BB
+#define CR_HSEON_BB            RCC_CR_HSEON_BB
+#define CSR_RMVF_BB            RCC_CSR_RMVF_BB
+#define CR_PLLSAION_BB         RCC_CR_PLLSAION_BB
+#define DCKCFGR_TIMPRE_BB      RCC_DCKCFGR_TIMPRE_BB
+
+#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER     __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
+#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER    __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
+#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB        __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
+#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB       __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
+#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE         __HAL_RCC_CRS_RELOADVALUE_CALCULATE
+
+#define __HAL_RCC_GET_IT_SOURCE                     __HAL_RCC_GET_IT
+
+#define RCC_CRS_SYNCWARM       RCC_CRS_SYNCWARN
+#define RCC_CRS_TRIMOV         RCC_CRS_TRIMOVF
+
+#define RCC_PERIPHCLK_CK48               RCC_PERIPHCLK_CLK48
+#define RCC_CK48CLKSOURCE_PLLQ           RCC_CLK48CLKSOURCE_PLLQ
+#define RCC_CK48CLKSOURCE_PLLSAIP        RCC_CLK48CLKSOURCE_PLLSAIP
+#define RCC_CK48CLKSOURCE_PLLI2SQ        RCC_CLK48CLKSOURCE_PLLI2SQ
+#define IS_RCC_CK48CLKSOURCE             IS_RCC_CLK48CLKSOURCE
+#define RCC_SDIOCLKSOURCE_CK48           RCC_SDIOCLKSOURCE_CLK48
+
+#define __HAL_RCC_DFSDM_CLK_ENABLE             __HAL_RCC_DFSDM1_CLK_ENABLE
+#define __HAL_RCC_DFSDM_CLK_DISABLE            __HAL_RCC_DFSDM1_CLK_DISABLE
+#define __HAL_RCC_DFSDM_IS_CLK_ENABLED         __HAL_RCC_DFSDM1_IS_CLK_ENABLED
+#define __HAL_RCC_DFSDM_IS_CLK_DISABLED        __HAL_RCC_DFSDM1_IS_CLK_DISABLED
+#define __HAL_RCC_DFSDM_FORCE_RESET            __HAL_RCC_DFSDM1_FORCE_RESET
+#define __HAL_RCC_DFSDM_RELEASE_RESET          __HAL_RCC_DFSDM1_RELEASE_RESET
+#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE       __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
+#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE      __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED   __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED  __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
+#define DfsdmClockSelection         Dfsdm1ClockSelection
+#define RCC_PERIPHCLK_DFSDM         RCC_PERIPHCLK_DFSDM1
+#define RCC_DFSDMCLKSOURCE_PCLK     RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_DFSDMCLKSOURCE_SYSCLK   RCC_DFSDM1CLKSOURCE_SYSCLK
+#define __HAL_RCC_DFSDM_CONFIG      __HAL_RCC_DFSDM1_CONFIG
+#define __HAL_RCC_GET_DFSDM_SOURCE  __HAL_RCC_GET_DFSDM1_SOURCE
+#define RCC_DFSDM1CLKSOURCE_PCLK    RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_SWPMI1CLKSOURCE_PCLK    RCC_SWPMI1CLKSOURCE_PCLK1
+#define RCC_LPTIM1CLKSOURCE_PCLK    RCC_LPTIM1CLKSOURCE_PCLK1
+#define RCC_LPTIM2CLKSOURCE_PCLK    RCC_LPTIM2CLKSOURCE_PCLK1
+
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM1AUDIOCLKSOURCE_I2S1
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM1AUDIOCLKSOURCE_I2S2
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM2AUDIOCLKSOURCE_I2S1
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM2AUDIOCLKSOURCE_I2S2
+#define RCC_DFSDM1CLKSOURCE_APB2            RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_DFSDM2CLKSOURCE_APB2            RCC_DFSDM2CLKSOURCE_PCLK2
+#define RCC_FMPI2C1CLKSOURCE_APB            RCC_FMPI2C1CLKSOURCE_PCLK1
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define  HAL_RNG_ReadyCallback(__HANDLE__)  HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4)
+#else
+#define __HAL_RTC_CLEAR_FLAG                      __HAL_RTC_EXTI_CLEAR_FLAG
+#endif
+#define __HAL_RTC_DISABLE_IT                      __HAL_RTC_EXTI_DISABLE_IT
+#define __HAL_RTC_ENABLE_IT                       __HAL_RTC_EXTI_ENABLE_IT
+
+#if defined (STM32F1)
+#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
+
+#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_ENABLE_IT()
+
+#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_DISABLE_IT()
+
+#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT)    __HAL_RTC_ALARM_EXTI_GET_FLAG()
+
+#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
+#else
+#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
+                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
+                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
+#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__)   (((__EXTI_LINE__)  == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
+                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
+                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
+#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
+                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
+                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
+#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__)    (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
+                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
+                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
+#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__)   (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
+                                                      (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() :  \
+                                                          __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
+#endif   /* STM32F1 */
+
+#define IS_ALARM                                  IS_RTC_ALARM
+#define IS_ALARM_MASK                             IS_RTC_ALARM_MASK
+#define IS_TAMPER                                 IS_RTC_TAMPER
+#define IS_TAMPER_ERASE_MODE                      IS_RTC_TAMPER_ERASE_MODE
+#define IS_TAMPER_FILTER                          IS_RTC_TAMPER_FILTER
+#define IS_TAMPER_INTERRUPT                       IS_RTC_TAMPER_INTERRUPT
+#define IS_TAMPER_MASKFLAG_STATE                  IS_RTC_TAMPER_MASKFLAG_STATE
+#define IS_TAMPER_PRECHARGE_DURATION              IS_RTC_TAMPER_PRECHARGE_DURATION
+#define IS_TAMPER_PULLUP_STATE                    IS_RTC_TAMPER_PULLUP_STATE
+#define IS_TAMPER_SAMPLING_FREQ                   IS_RTC_TAMPER_SAMPLING_FREQ
+#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION     IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
+#define IS_TAMPER_TRIGGER                         IS_RTC_TAMPER_TRIGGER
+#define IS_WAKEUP_CLOCK                           IS_RTC_WAKEUP_CLOCK
+#define IS_WAKEUP_COUNTER                         IS_RTC_WAKEUP_COUNTER
+
+#define __RTC_WRITEPROTECTION_ENABLE  __HAL_RTC_WRITEPROTECTION_ENABLE
+#define __RTC_WRITEPROTECTION_DISABLE  __HAL_RTC_WRITEPROTECTION_DISABLE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define SD_OCR_CID_CSD_OVERWRIETE   SD_OCR_CID_CSD_OVERWRITE
+#define SD_CMD_SD_APP_STAUS         SD_CMD_SD_APP_STATUS
+
+#if defined(STM32F4) || defined(STM32F2)
+#define  SD_SDMMC_DISABLED          SD_SDIO_DISABLED
+#define  SD_SDMMC_FUNCTION_BUSY     SD_SDIO_FUNCTION_BUSY
+#define  SD_SDMMC_FUNCTION_FAILED   SD_SDIO_FUNCTION_FAILED
+#define  SD_SDMMC_UNKNOWN_FUNCTION  SD_SDIO_UNKNOWN_FUNCTION
+#define  SD_CMD_SDMMC_SEN_OP_COND   SD_CMD_SDIO_SEN_OP_COND
+#define  SD_CMD_SDMMC_RW_DIRECT     SD_CMD_SDIO_RW_DIRECT
+#define  SD_CMD_SDMMC_RW_EXTENDED   SD_CMD_SDIO_RW_EXTENDED
+#define  __HAL_SD_SDMMC_ENABLE      __HAL_SD_SDIO_ENABLE
+#define  __HAL_SD_SDMMC_DISABLE     __HAL_SD_SDIO_DISABLE
+#define  __HAL_SD_SDMMC_DMA_ENABLE  __HAL_SD_SDIO_DMA_ENABLE
+#define  __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
+#define  __HAL_SD_SDMMC_ENABLE_IT   __HAL_SD_SDIO_ENABLE_IT
+#define  __HAL_SD_SDMMC_DISABLE_IT  __HAL_SD_SDIO_DISABLE_IT
+#define  __HAL_SD_SDMMC_GET_FLAG    __HAL_SD_SDIO_GET_FLAG
+#define  __HAL_SD_SDMMC_CLEAR_FLAG  __HAL_SD_SDIO_CLEAR_FLAG
+#define  __HAL_SD_SDMMC_GET_IT      __HAL_SD_SDIO_GET_IT
+#define  __HAL_SD_SDMMC_CLEAR_IT    __HAL_SD_SDIO_CLEAR_IT
+#define  SDMMC_STATIC_FLAGS         SDIO_STATIC_FLAGS
+#define  SDMMC_CMD0TIMEOUT          SDIO_CMD0TIMEOUT
+#define  SD_SDMMC_SEND_IF_COND      SD_SDIO_SEND_IF_COND
+/* alias CMSIS */
+#define  SDMMC1_IRQn                SDIO_IRQn
+#define  SDMMC1_IRQHandler          SDIO_IRQHandler
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define  SD_SDIO_DISABLED           SD_SDMMC_DISABLED
+#define  SD_SDIO_FUNCTION_BUSY      SD_SDMMC_FUNCTION_BUSY
+#define  SD_SDIO_FUNCTION_FAILED    SD_SDMMC_FUNCTION_FAILED
+#define  SD_SDIO_UNKNOWN_FUNCTION   SD_SDMMC_UNKNOWN_FUNCTION
+#define  SD_CMD_SDIO_SEN_OP_COND    SD_CMD_SDMMC_SEN_OP_COND
+#define  SD_CMD_SDIO_RW_DIRECT      SD_CMD_SDMMC_RW_DIRECT
+#define  SD_CMD_SDIO_RW_EXTENDED    SD_CMD_SDMMC_RW_EXTENDED
+#define  __HAL_SD_SDIO_ENABLE       __HAL_SD_SDMMC_ENABLE
+#define  __HAL_SD_SDIO_DISABLE      __HAL_SD_SDMMC_DISABLE
+#define  __HAL_SD_SDIO_DMA_ENABLE   __HAL_SD_SDMMC_DMA_ENABLE
+#define  __HAL_SD_SDIO_DMA_DISABL   __HAL_SD_SDMMC_DMA_DISABLE
+#define  __HAL_SD_SDIO_ENABLE_IT    __HAL_SD_SDMMC_ENABLE_IT
+#define  __HAL_SD_SDIO_DISABLE_IT   __HAL_SD_SDMMC_DISABLE_IT
+#define  __HAL_SD_SDIO_GET_FLAG     __HAL_SD_SDMMC_GET_FLAG
+#define  __HAL_SD_SDIO_CLEAR_FLAG   __HAL_SD_SDMMC_CLEAR_FLAG
+#define  __HAL_SD_SDIO_GET_IT       __HAL_SD_SDMMC_GET_IT
+#define  __HAL_SD_SDIO_CLEAR_IT     __HAL_SD_SDMMC_CLEAR_IT
+#define  SDIO_STATIC_FLAGS          SDMMC_STATIC_FLAGS
+#define  SDIO_CMD0TIMEOUT           SDMMC_CMD0TIMEOUT
+#define  SD_SDIO_SEND_IF_COND       SD_SDMMC_SEND_IF_COND
+/* alias CMSIS for compatibilities */
+#define  SDIO_IRQn                  SDMMC1_IRQn
+#define  SDIO_IRQHandler            SDMMC1_IRQHandler
+#endif
+
+#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7)
+#define  HAL_SD_CardCIDTypedef       HAL_SD_CardCIDTypeDef
+#define  HAL_SD_CardCSDTypedef       HAL_SD_CardCSDTypeDef
+#define  HAL_SD_CardStatusTypedef    HAL_SD_CardStatusTypeDef
+#define  HAL_SD_CardStateTypedef     HAL_SD_CardStateTypeDef
+#endif
+
+#if defined(STM32H7) || defined(STM32L5)
+#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback   HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
+#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback   HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
+#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback  HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
+#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback  HAL_MMCEx_Write_DMADoubleBuf1CpltCallback
+#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback    HAL_SDEx_Read_DMADoubleBuf0CpltCallback
+#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback    HAL_SDEx_Read_DMADoubleBuf1CpltCallback
+#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback   HAL_SDEx_Write_DMADoubleBuf0CpltCallback
+#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback   HAL_SDEx_Write_DMADoubleBuf1CpltCallback
+#define HAL_SD_DriveTransciver_1_8V_Callback          HAL_SD_DriveTransceiver_1_8V_Callback
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __SMARTCARD_ENABLE_IT           __HAL_SMARTCARD_ENABLE_IT
+#define __SMARTCARD_DISABLE_IT          __HAL_SMARTCARD_DISABLE_IT
+#define __SMARTCARD_ENABLE              __HAL_SMARTCARD_ENABLE
+#define __SMARTCARD_DISABLE             __HAL_SMARTCARD_DISABLE
+#define __SMARTCARD_DMA_REQUEST_ENABLE  __HAL_SMARTCARD_DMA_REQUEST_ENABLE
+#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
+
+#define __HAL_SMARTCARD_GETCLOCKSOURCE  SMARTCARD_GETCLOCKSOURCE
+#define __SMARTCARD_GETCLOCKSOURCE      SMARTCARD_GETCLOCKSOURCE
+
+#define IS_SMARTCARD_ONEBIT_SAMPLING    IS_SMARTCARD_ONE_BIT_SAMPLE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_SMBUS_RESET_CR1           SMBUS_RESET_CR1
+#define __HAL_SMBUS_RESET_CR2           SMBUS_RESET_CR2
+#define __HAL_SMBUS_GENERATE_START      SMBUS_GENERATE_START
+#define __HAL_SMBUS_GET_ADDR_MATCH      SMBUS_GET_ADDR_MATCH
+#define __HAL_SMBUS_GET_DIR             SMBUS_GET_DIR
+#define __HAL_SMBUS_GET_STOP_MODE       SMBUS_GET_STOP_MODE
+#define __HAL_SMBUS_GET_PEC_MODE        SMBUS_GET_PEC_MODE
+#define __HAL_SMBUS_GET_ALERT_ENABLED   SMBUS_GET_ALERT_ENABLED
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_SPI_1LINE_TX              SPI_1LINE_TX
+#define __HAL_SPI_1LINE_RX              SPI_1LINE_RX
+#define __HAL_SPI_RESET_CRC             SPI_RESET_CRC
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_UART_GETCLOCKSOURCE       UART_GETCLOCKSOURCE
+#define __HAL_UART_MASK_COMPUTATION     UART_MASK_COMPUTATION
+#define __UART_GETCLOCKSOURCE           UART_GETCLOCKSOURCE
+#define __UART_MASK_COMPUTATION         UART_MASK_COMPUTATION
+
+#define IS_UART_WAKEUPMETHODE           IS_UART_WAKEUPMETHOD
+
+#define IS_UART_ONEBIT_SAMPLE           IS_UART_ONE_BIT_SAMPLE
+#define IS_UART_ONEBIT_SAMPLING         IS_UART_ONE_BIT_SAMPLE
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __USART_ENABLE_IT               __HAL_USART_ENABLE_IT
+#define __USART_DISABLE_IT              __HAL_USART_DISABLE_IT
+#define __USART_ENABLE                  __HAL_USART_ENABLE
+#define __USART_DISABLE                 __HAL_USART_DISABLE
+
+#define __HAL_USART_GETCLOCKSOURCE      USART_GETCLOCKSOURCE
+#define __USART_GETCLOCKSOURCE          USART_GETCLOCKSOURCE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define USB_EXTI_LINE_WAKEUP                               USB_WAKEUP_EXTI_LINE
+
+#define USB_FS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
+#define USB_FS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_FS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_FS_EXTI_LINE_WAKEUP                            USB_OTG_FS_WAKEUP_EXTI_LINE
+
+#define USB_HS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
+#define USB_HS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_HS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_HS_EXTI_LINE_WAKEUP                            USB_OTG_HS_WAKEUP_EXTI_LINE
+
+#define __HAL_USB_EXTI_ENABLE_IT                           __HAL_USB_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_EXTI_DISABLE_IT                          __HAL_USB_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_EXTI_GET_FLAG                            __HAL_USB_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_EXTI_CLEAR_FLAG                          __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER             __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER            __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER           __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+
+#define __HAL_USB_FS_EXTI_ENABLE_IT                        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_FS_EXTI_DISABLE_IT                       __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_FS_EXTI_GET_FLAG                         __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_FS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define __HAL_USB_HS_EXTI_ENABLE_IT                        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_HS_EXTI_DISABLE_IT                       __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_HS_EXTI_GET_FLAG                         __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_HS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define HAL_PCD_ActiveRemoteWakeup                         HAL_PCD_ActivateRemoteWakeup
+#define HAL_PCD_DeActiveRemoteWakeup                       HAL_PCD_DeActivateRemoteWakeup
+
+#define HAL_PCD_SetTxFiFo                                  HAL_PCDEx_SetTxFiFo
+#define HAL_PCD_SetRxFiFo                                  HAL_PCDEx_SetRxFiFo
+/**
+  * @}
+  */
+
+/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_TIM_SetICPrescalerValue   TIM_SET_ICPRESCALERVALUE
+#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
+
+#define TIM_GET_ITSTATUS                __HAL_TIM_GET_IT_SOURCE
+#define TIM_GET_CLEAR_IT                __HAL_TIM_CLEAR_IT
+
+#define __HAL_TIM_GET_ITSTATUS          __HAL_TIM_GET_IT_SOURCE
+
+#define __HAL_TIM_DIRECTION_STATUS      __HAL_TIM_IS_TIM_COUNTING_DOWN
+#define __HAL_TIM_PRESCALER             __HAL_TIM_SET_PRESCALER
+#define __HAL_TIM_SetCounter            __HAL_TIM_SET_COUNTER
+#define __HAL_TIM_GetCounter            __HAL_TIM_GET_COUNTER
+#define __HAL_TIM_SetAutoreload         __HAL_TIM_SET_AUTORELOAD
+#define __HAL_TIM_GetAutoreload         __HAL_TIM_GET_AUTORELOAD
+#define __HAL_TIM_SetClockDivision      __HAL_TIM_SET_CLOCKDIVISION
+#define __HAL_TIM_GetClockDivision      __HAL_TIM_GET_CLOCKDIVISION
+#define __HAL_TIM_SetICPrescaler        __HAL_TIM_SET_ICPRESCALER
+#define __HAL_TIM_GetICPrescaler        __HAL_TIM_GET_ICPRESCALER
+#define __HAL_TIM_SetCompare            __HAL_TIM_SET_COMPARE
+#define __HAL_TIM_GetCompare            __HAL_TIM_GET_COMPARE
+
+#define TIM_BREAKINPUTSOURCE_DFSDM  TIM_BREAKINPUTSOURCE_DFSDM1
+/**
+  * @}
+  */
+
+/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_ETH_EXTI_ENABLE_IT                   __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_ETH_EXTI_DISABLE_IT                  __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_ETH_EXTI_GET_FLAG                    __HAL_ETH_WAKEUP_EXTI_GET_FLAG
+#define __HAL_ETH_EXTI_CLEAR_FLAG                  __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER     __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER    __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER   __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
+
+#define ETH_PROMISCIOUSMODE_ENABLE   ETH_PROMISCUOUS_MODE_ENABLE
+#define ETH_PROMISCIOUSMODE_DISABLE  ETH_PROMISCUOUS_MODE_DISABLE
+#define IS_ETH_PROMISCIOUS_MODE      IS_ETH_PROMISCUOUS_MODE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_LTDC_LAYER LTDC_LAYER
+#define __HAL_LTDC_RELOAD_CONFIG  __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define SAI_OUTPUTDRIVE_DISABLED          SAI_OUTPUTDRIVE_DISABLE
+#define SAI_OUTPUTDRIVE_ENABLED           SAI_OUTPUTDRIVE_ENABLE
+#define SAI_MASTERDIVIDER_ENABLED         SAI_MASTERDIVIDER_ENABLE
+#define SAI_MASTERDIVIDER_DISABLED        SAI_MASTERDIVIDER_DISABLE
+#define SAI_STREOMODE                     SAI_STEREOMODE
+#define SAI_FIFOStatus_Empty              SAI_FIFOSTATUS_EMPTY
+#define SAI_FIFOStatus_Less1QuarterFull   SAI_FIFOSTATUS_LESS1QUARTERFULL
+#define SAI_FIFOStatus_1QuarterFull       SAI_FIFOSTATUS_1QUARTERFULL
+#define SAI_FIFOStatus_HalfFull           SAI_FIFOSTATUS_HALFFULL
+#define SAI_FIFOStatus_3QuartersFull      SAI_FIFOSTATUS_3QUARTERFULL
+#define SAI_FIFOStatus_Full               SAI_FIFOSTATUS_FULL
+#define IS_SAI_BLOCK_MONO_STREO_MODE      IS_SAI_BLOCK_MONO_STEREO_MODE
+#define SAI_SYNCHRONOUS_EXT               SAI_SYNCHRONOUS_EXT_SAI1
+#define SAI_SYNCEXT_IN_ENABLE             SAI_SYNCEXT_OUTBLOCKA_ENABLE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#if defined(STM32H7)
+#define HAL_SPDIFRX_ReceiveControlFlow      HAL_SPDIFRX_ReceiveCtrlFlow
+#define HAL_SPDIFRX_ReceiveControlFlow_IT   HAL_SPDIFRX_ReceiveCtrlFlow_IT
+#define HAL_SPDIFRX_ReceiveControlFlow_DMA  HAL_SPDIFRX_ReceiveCtrlFlow_DMA
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
+#define HAL_HRTIM_WaveformCounterStart_IT      HAL_HRTIM_WaveformCountStart_IT
+#define HAL_HRTIM_WaveformCounterStart_DMA     HAL_HRTIM_WaveformCountStart_DMA
+#define HAL_HRTIM_WaveformCounterStart         HAL_HRTIM_WaveformCountStart
+#define HAL_HRTIM_WaveformCounterStop_IT       HAL_HRTIM_WaveformCountStop_IT
+#define HAL_HRTIM_WaveformCounterStop_DMA      HAL_HRTIM_WaveformCountStop_DMA
+#define HAL_HRTIM_WaveformCounterStop          HAL_HRTIM_WaveformCountStop
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)
+#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
+#endif /* STM32L4 || STM32F4 || STM32F7 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32_HAL_LEGACY */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h
new file mode 100644
index 00000000..2ee957c3
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h
@@ -0,0 +1,1078 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal.h
+  * @author  MCD Application Team
+  * @brief   This file contains all the functions prototypes for the HAL
+  *          module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_H
+#define STM32H7xx_HAL_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_conf.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup HAL
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup HAL_TICK_FREQ Tick Frequency
+  * @{
+  */
+typedef enum
+{
+  HAL_TICK_FREQ_10HZ         = 100U,
+  HAL_TICK_FREQ_100HZ        = 10U,
+  HAL_TICK_FREQ_1KHZ         = 1U,
+  HAL_TICK_FREQ_DEFAULT      = HAL_TICK_FREQ_1KHZ
+} HAL_TickFreqTypeDef;
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup REV_ID device revision ID
+  * @{
+  */
+#define REV_ID_Y ((uint32_t)0x1003)  /*!< STM32H7 rev.Y */
+#define REV_ID_B ((uint32_t)0x2000)  /*!< STM32H7 rev.B */
+#define REV_ID_X ((uint32_t)0x2001)  /*!< STM32H7 rev.X */
+#define REV_ID_V ((uint32_t)0x2003)  /*!< STM32H7 rev.V */
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
+  * @{
+  */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE0   VREFBUF_CSR_VRS_OUT2   /*!< Voltage reference scale 0 (VREF_OUT2) */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE1   VREFBUF_CSR_VRS_OUT1   /*!< Voltage reference scale 1 (VREF_OUT1) */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE2   VREFBUF_CSR_VRS_OUT4   /*!< Voltage reference scale 2 (VREF_OUT4) */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE3   VREFBUF_CSR_VRS_OUT3   /*!< Voltage reference scale 3 (VREF_OUT3) */
+
+
+#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__)  (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
+                                                     ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1) || \
+                                                     ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE2) || \
+                                                     ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE3))
+
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance
+  * @{
+  */
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE  ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to Voltage reference buffer output */
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE   VREFBUF_CSR_HIZ        /*!< VREF_plus pin is high impedance */
+
+#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__)  (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
+                                                      ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
+
+#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__)  (((__VALUE__) > 0UL) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
+
+/**
+  * @}
+  */
+
+#if !defined(SYSCFG_PMCR_BOOSTEN)
+/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
+  * @{
+  */
+
+/** @brief  Fast-mode Plus driving capability on a specific GPIO
+  */
+#define SYSCFG_FASTMODEPLUS_PB6        SYSCFG_PMCR_I2C_PB6_FMP  /*!< Enable Fast-mode Plus on PB6 */
+#define SYSCFG_FASTMODEPLUS_PB7        SYSCFG_PMCR_I2C_PB7_FMP  /*!< Enable Fast-mode Plus on PB7 */
+#define SYSCFG_FASTMODEPLUS_PB8        SYSCFG_PMCR_I2C_PB8_FMP  /*!< Enable Fast-mode Plus on PB8 */
+#define SYSCFG_FASTMODEPLUS_PB9        SYSCFG_PMCR_I2C_PB9_FMP  /*!< Enable Fast-mode Plus on PB9 */
+
+#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
+
+#endif /* ! SYSCFG_PMCR_BOOSTEN */
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_Ethernet_Config  Ethernet Config
+  * @{
+  */
+#define SYSCFG_ETH_MII                      ((uint32_t)0x00000000)  /*!< Select the Media Independent Interface */
+#define SYSCFG_ETH_RMII                     SYSCFG_PMCR_EPIS_SEL_2  /*!< Select the Reduced Media Independent Interface */
+
+#define IS_SYSCFG_ETHERNET_CONFIG(CONFIG) (((CONFIG) == SYSCFG_ETH_MII)        || \
+                                          ((CONFIG) == SYSCFG_ETH_RMII))
+
+/**
+  * @}
+  */
+
+
+/** @defgroup SYSCFG_Analog_Switch_Config  Analog Switch Config
+  * @{
+  */
+#define SYSCFG_SWITCH_PA0                       SYSCFG_PMCR_PA0SO  /*!< Select PA0 analog switch */
+#define SYSCFG_SWITCH_PA1                       SYSCFG_PMCR_PA1SO  /*!< Select PA1 analog switch */
+#define SYSCFG_SWITCH_PC2                       SYSCFG_PMCR_PC2SO  /*!< Select PC2 analog switch */
+#define SYSCFG_SWITCH_PC3                       SYSCFG_PMCR_PC3SO  /*!< Select PC3 analog switch */
+
+
+#define IS_SYSCFG_ANALOG_SWITCH(SWITCH)    ((((SWITCH) & SYSCFG_SWITCH_PA0) == SYSCFG_SWITCH_PA0)|| \
+                                           (((SWITCH) & SYSCFG_SWITCH_PA1) == SYSCFG_SWITCH_PA1) || \
+                                           (((SWITCH) & SYSCFG_SWITCH_PC2) == SYSCFG_SWITCH_PC2) || \
+                                           (((SWITCH) & SYSCFG_SWITCH_PC3) == SYSCFG_SWITCH_PC3))
+
+
+#define SYSCFG_SWITCH_PA0_OPEN                       SYSCFG_PMCR_PA0SO       /*!< PA0 analog switch opened */
+#define SYSCFG_SWITCH_PA0_CLOSE                      ((uint32_t)0x00000000)  /*!< PA0 analog switch closed */
+#define SYSCFG_SWITCH_PA1_OPEN                       SYSCFG_PMCR_PA1SO       /*!< PA1 analog switch opened */
+#define SYSCFG_SWITCH_PA1_CLOSE                      ((uint32_t)0x00000000)  /*!< PA1 analog switch closed*/
+#define SYSCFG_SWITCH_PC2_OPEN                       SYSCFG_PMCR_PC2SO       /*!< PC2 analog switch opened */
+#define SYSCFG_SWITCH_PC2_CLOSE                      ((uint32_t)0x00000000)  /*!< PC2 analog switch closed */
+#define SYSCFG_SWITCH_PC3_OPEN                       SYSCFG_PMCR_PC3SO       /*!< PC3 analog switch opened */
+#define SYSCFG_SWITCH_PC3_CLOSE                      ((uint32_t)0x00000000)  /*!< PC3 analog switch closed */
+
+#define IS_SYSCFG_SWITCH_STATE(STATE)      ((((STATE) & SYSCFG_SWITCH_PA0_OPEN) == SYSCFG_SWITCH_PA0_OPEN)    || \
+                                           (((STATE) & SYSCFG_SWITCH_PA0_CLOSE) == SYSCFG_SWITCH_PA0_CLOSE)   || \
+                                           (((STATE) & SYSCFG_SWITCH_PA1_OPEN) == SYSCFG_SWITCH_PA1_OPEN)     || \
+                                           (((STATE) & SYSCFG_SWITCH_PA1_CLOSE) == SYSCFG_SWITCH_PA1_CLOSE)   || \
+                                           (((STATE) & SYSCFG_SWITCH_PC2_OPEN) == SYSCFG_SWITCH_PC2_OPEN)     || \
+                                           (((STATE) & SYSCFG_SWITCH_PC2_CLOSE) == SYSCFG_SWITCH_PC2_CLOSE)   || \
+                                           (((STATE) & SYSCFG_SWITCH_PC3_OPEN) == SYSCFG_SWITCH_PC3_OPEN)     || \
+                                           (((STATE) & SYSCFG_SWITCH_PC3_CLOSE) == SYSCFG_SWITCH_PC3_CLOSE))
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_Boot_Config  Boot Config
+  * @{
+  */
+#define SYSCFG_BOOT_ADDR0                    ((uint32_t)0x00000000)  /*!< Select Boot address0 */
+#define SYSCFG_BOOT_ADDR1                    ((uint32_t)0x00000001)  /*!< Select Boot address1 */
+
+#define IS_SYSCFG_BOOT_REGISTER(REGISTER) (((REGISTER) == SYSCFG_BOOT_ADDR0)|| \
+                                          ((REGISTER) == SYSCFG_BOOT_ADDR1))
+
+#define IS_SYSCFG_BOOT_ADDRESS(ADDRESS) ((ADDRESS) < PERIPH_BASE)
+
+/**
+  * @}
+  */
+
+
+/** @defgroup SYSCFG_IOCompenstionCell_Config  IOCompenstionCell Config
+  * @{
+  */
+#define SYSCFG_CELL_CODE                    ((uint32_t)0x00000000)  /*!< Select Code from the cell */
+#define SYSCFG_REGISTER_CODE                 SYSCFG_CCCSR_CS        /*!< Code from the SYSCFG compensation cell code register */
+
+#define IS_SYSCFG_CODE_SELECT(SELECT) (((SELECT) == SYSCFG_CELL_CODE)|| \
+                                        ((SELECT) == SYSCFG_REGISTER_CODE))
+
+#define IS_SYSCFG_CODE_CONFIG(CONFIG) ((CONFIG) < (0x10UL))
+
+/**
+  * @}
+  */
+
+
+
+
+/** @defgroup EXTI_Event_Input_Config  Event Input Config
+  * @{
+  */
+
+#define EXTI_MODE_IT          ((uint32_t)0x00010000)
+#define EXTI_MODE_EVT         ((uint32_t)0x00020000)
+#define EXTI_RISING_EDGE      ((uint32_t)0x00100000)
+#define EXTI_FALLING_EDGE     ((uint32_t)0x00200000)
+
+#define IS_EXTI_EDGE_LINE(EDGE) (((EDGE) == EXTI_RISING_EDGE) || ((EDGE) == EXTI_FALLING_EDGE))
+#define IS_EXTI_MODE_LINE(MODE) (((MODE) == EXTI_MODE_IT) || ((MODE) == EXTI_MODE_EVT))
+
+#define EXTI_LINE0       ((uint32_t)0x00)  /*!< External interrupt LINE 0  */
+#define EXTI_LINE1       ((uint32_t)0x01)  /*!< External interrupt LINE 1  */
+#define EXTI_LINE2       ((uint32_t)0x02)  /*!< External interrupt LINE 2  */
+#define EXTI_LINE3       ((uint32_t)0x03)  /*!< External interrupt LINE 3  */
+#define EXTI_LINE4       ((uint32_t)0x04)  /*!< External interrupt LINE 4  */
+#define EXTI_LINE5       ((uint32_t)0x05)  /*!< External interrupt LINE 5  */
+#define EXTI_LINE6       ((uint32_t)0x06)  /*!< External interrupt LINE 6  */
+#define EXTI_LINE7       ((uint32_t)0x07)  /*!< External interrupt LINE 7  */
+#define EXTI_LINE8       ((uint32_t)0x08)  /*!< External interrupt LINE 8  */
+#define EXTI_LINE9       ((uint32_t)0x09)  /*!< External interrupt LINE 9  */
+#define EXTI_LINE10      ((uint32_t)0x0A)  /*!< External interrupt LINE 10 */
+#define EXTI_LINE11      ((uint32_t)0x0B)  /*!< External interrupt LINE 11 */
+#define EXTI_LINE12      ((uint32_t)0x0C)  /*!< External interrupt LINE 12 */
+#define EXTI_LINE13      ((uint32_t)0x0D)  /*!< External interrupt LINE 13 */
+#define EXTI_LINE14      ((uint32_t)0x0E)  /*!< External interrupt LINE 14 */
+#define EXTI_LINE15      ((uint32_t)0x0F)  /*!< External interrupt LINE 15 */
+#define EXTI_LINE16      ((uint32_t)0x10)
+#define EXTI_LINE17      ((uint32_t)0x11)
+#define EXTI_LINE18      ((uint32_t)0x12)
+#define EXTI_LINE19      ((uint32_t)0x13)
+#define EXTI_LINE20      ((uint32_t)0x14)
+#define EXTI_LINE21      ((uint32_t)0x15)
+#define EXTI_LINE22      ((uint32_t)0x16)
+#define EXTI_LINE23      ((uint32_t)0x17)
+#define EXTI_LINE24      ((uint32_t)0x18)
+#define EXTI_LINE25      ((uint32_t)0x19)
+#define EXTI_LINE26      ((uint32_t)0x1A)
+#define EXTI_LINE27      ((uint32_t)0x1B)
+#define EXTI_LINE28      ((uint32_t)0x1C)
+#define EXTI_LINE29      ((uint32_t)0x1D)
+#define EXTI_LINE30      ((uint32_t)0x1E)
+#define EXTI_LINE31      ((uint32_t)0x1F)
+#define EXTI_LINE32      ((uint32_t)0x20)
+#define EXTI_LINE33      ((uint32_t)0x21)
+#define EXTI_LINE34      ((uint32_t)0x22)
+#define EXTI_LINE35      ((uint32_t)0x23)
+#define EXTI_LINE36      ((uint32_t)0x24)
+#define EXTI_LINE37      ((uint32_t)0x25)
+#define EXTI_LINE38      ((uint32_t)0x26)
+#define EXTI_LINE39      ((uint32_t)0x27)
+
+#define EXTI_LINE40      ((uint32_t)0x28)
+#define EXTI_LINE41      ((uint32_t)0x29)
+#define EXTI_LINE42      ((uint32_t)0x2A)
+#define EXTI_LINE43      ((uint32_t)0x2B)
+#define EXTI_LINE44      ((uint32_t)0x2C)  /* Not available in all family lines */
+/* EXTI_LINE45 Reserved */
+#if defined(DUAL_CORE)
+#define EXTI_LINE46      ((uint32_t)0x2E)
+#else
+/* EXTI_LINE46 Reserved */
+#endif /* DUAL_CORE */
+#define EXTI_LINE47      ((uint32_t)0x2F)
+#define EXTI_LINE48      ((uint32_t)0x30)
+#define EXTI_LINE49      ((uint32_t)0x31)
+#define EXTI_LINE50      ((uint32_t)0x32)
+#define EXTI_LINE51      ((uint32_t)0x33)
+#define EXTI_LINE52      ((uint32_t)0x34)
+#define EXTI_LINE53      ((uint32_t)0x35)
+#define EXTI_LINE54      ((uint32_t)0x36)
+#define EXTI_LINE55      ((uint32_t)0x37)
+#define EXTI_LINE56      ((uint32_t)0x38)
+#define EXTI_LINE57      ((uint32_t)0x39)
+#define EXTI_LINE58      ((uint32_t)0x3A)
+#define EXTI_LINE59      ((uint32_t)0x3B)
+#define EXTI_LINE60      ((uint32_t)0x3C)
+#define EXTI_LINE61      ((uint32_t)0x3D)
+#define EXTI_LINE62      ((uint32_t)0x3E)
+#define EXTI_LINE63      ((uint32_t)0x3F)
+#define EXTI_LINE64      ((uint32_t)0x40)
+#define EXTI_LINE65      ((uint32_t)0x41)
+#define EXTI_LINE66      ((uint32_t)0x42)
+#define EXTI_LINE67      ((uint32_t)0x43)
+#define EXTI_LINE68      ((uint32_t)0x44)
+#define EXTI_LINE69      ((uint32_t)0x45)
+#define EXTI_LINE70      ((uint32_t)0x46)
+#define EXTI_LINE71      ((uint32_t)0x47)
+#define EXTI_LINE72      ((uint32_t)0x48)
+#define EXTI_LINE73      ((uint32_t)0x49)
+#define EXTI_LINE74      ((uint32_t)0x4A)
+#define EXTI_LINE75      ((uint32_t)0x4B)  /* Not available in all family lines */
+#define EXTI_LINE76      ((uint32_t)0x4C)  /* Not available in all family lines */
+#if defined(DUAL_CORE)
+#define EXTI_LINE77      ((uint32_t)0x4D)
+#define EXTI_LINE78      ((uint32_t)0x4E)
+#define EXTI_LINE79      ((uint32_t)0x4F)
+#define EXTI_LINE80      ((uint32_t)0x50)
+#else
+/* EXTI_LINE77 Reserved */
+/* EXTI_LINE78 Reserved */
+/* EXTI_LINE79 Reserved */
+/* EXTI_LINE80 Reserved */
+#endif /* DUAL_CORE */
+/* EXTI_LINE81   Reserved */
+#if defined(DUAL_CORE)
+#define EXTI_LINE82      ((uint32_t)0x52)
+#else
+/* EXTI_LINE82 Reserved */
+#endif /* DUAL_CORE */
+/* EXTI_LINE83   Reserved */
+#if defined(DUAL_CORE)
+#define EXTI_LINE84      ((uint32_t)0x54)
+#else
+/* EXTI_LINE84 Reserved */
+#endif /* DUAL_CORE */
+#define EXTI_LINE85      ((uint32_t)0x55)
+#define EXTI_LINE86      ((uint32_t)0x56)  /* Not available in all family lines */
+#define EXTI_LINE87      ((uint32_t)0x57)
+#define EXTI_LINE88      ((uint32_t)0x58)  /* Not available in all family lines */
+
+#if defined(DUAL_CORE)
+#define IS_HAL_EXTI_CONFIG_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \
+                                ((LINE) == EXTI_LINE2)  || ((LINE) == EXTI_LINE3)   || \
+                                ((LINE) == EXTI_LINE4)  || ((LINE) == EXTI_LINE5)   || \
+                                ((LINE) == EXTI_LINE6)  || ((LINE) == EXTI_LINE7)   || \
+                                ((LINE) == EXTI_LINE8)  || ((LINE) == EXTI_LINE9)   || \
+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11)  || \
+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13)  || \
+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15)  || \
+                                ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17)  || \
+                                ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19)  || \
+                                ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21)  || \
+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE51)  || \
+                                ((LINE) == EXTI_LINE82) || ((LINE) == EXTI_LINE84)  || \
+                                ((LINE) == EXTI_LINE85) || ((LINE) == EXTI_LINE86))
+#else
+#define IS_HAL_EXTI_CONFIG_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1)|| \
+                                ((LINE) == EXTI_LINE2)  || ((LINE) == EXTI_LINE3)   || \
+                                ((LINE) == EXTI_LINE4)  || ((LINE) == EXTI_LINE5)   || \
+                                ((LINE) == EXTI_LINE6)  || ((LINE) == EXTI_LINE7)   || \
+                                ((LINE) == EXTI_LINE8)  || ((LINE) == EXTI_LINE9)   || \
+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
+                                ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
+                                ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
+                                ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE51) || \
+                                ((LINE) == EXTI_LINE85) || ((LINE) == EXTI_LINE86))
+#endif /* DUAL_CORE */
+
+#if defined(DUAL_CORE)
+#define IS_EXTI_ALL_LINE(LINE) (((LINE) == EXTI_LINE0)  || ((LINE) == EXTI_LINE1)  || \
+                                ((LINE) == EXTI_LINE2)  || ((LINE) == EXTI_LINE3)  || \
+                                ((LINE) == EXTI_LINE4)  || ((LINE) == EXTI_LINE5)  || \
+                                ((LINE) == EXTI_LINE6)  || ((LINE) == EXTI_LINE7)  || \
+                                ((LINE) == EXTI_LINE8)  || ((LINE) == EXTI_LINE9)  || \
+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
+                                ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
+                                ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
+                                ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
+                                ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \
+                                ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \
+                                ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \
+                                ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \
+                                ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \
+                                ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \
+                                ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
+                                ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \
+                                ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \
+                                ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \
+                                ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \
+                                ((LINE) == EXTI_LINE44) || ((LINE) == EXTI_LINE46) || \
+                                ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \
+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
+                                ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
+                                ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \
+                                ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \
+                                ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \
+                                ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \
+                                ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \
+                                ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \
+                                ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \
+                                ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \
+                                ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \
+                                ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \
+                                ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \
+                                ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
+                                ((LINE) == EXTI_LINE77) || ((LINE) == EXTI_LINE79) || \
+                                ((LINE) == EXTI_LINE84) || ((LINE) == EXTI_LINE85) || \
+                                ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87) || \
+                                ((LINE) == EXTI_LINE78) || \
+                                ((LINE) == EXTI_LINE80) || ((LINE) == EXTI_LINE82))
+#else
+#define IS_EXTI_ALL_LINE(LINE) (((LINE) == EXTI_LINE0)  || ((LINE) == EXTI_LINE1)  || \
+                                ((LINE) == EXTI_LINE2)  || ((LINE) == EXTI_LINE3)  || \
+                                ((LINE) == EXTI_LINE4)  || ((LINE) == EXTI_LINE5)  || \
+                                ((LINE) == EXTI_LINE6)  || ((LINE) == EXTI_LINE7)  || \
+                                ((LINE) == EXTI_LINE8)  || ((LINE) == EXTI_LINE9)  || \
+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
+                                ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
+                                ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
+                                ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
+                                ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \
+                                ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \
+                                ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \
+                                ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \
+                                ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \
+                                ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \
+                                ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
+                                ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \
+                                ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \
+                                ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \
+                                ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \
+                                ((LINE) == EXTI_LINE44) || \
+                                ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \
+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
+                                ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
+                                ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \
+                                ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \
+                                ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \
+                                ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \
+                                ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \
+                                ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \
+                                ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \
+                                ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \
+                                ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \
+                                ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \
+                                ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \
+                                ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
+                                ((LINE) == EXTI_LINE85) || \
+                                ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87) || \
+                                ((LINE) == EXTI_LINE88))
+#endif /*DUAL_CORE*/
+
+#if defined(DUAL_CORE)
+#define IS_EXTI_D1_LINE(LINE) (((LINE) == EXTI_LINE0)  || ((LINE) == EXTI_LINE1)  || \
+                                ((LINE) == EXTI_LINE2)  || ((LINE) == EXTI_LINE3)  || \
+                                ((LINE) == EXTI_LINE4)  || ((LINE) == EXTI_LINE5)  || \
+                                ((LINE) == EXTI_LINE6)  || ((LINE) == EXTI_LINE7)  || \
+                                ((LINE) == EXTI_LINE8)  || ((LINE) == EXTI_LINE9)  || \
+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
+                                ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
+                                ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
+                                ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
+                                ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \
+                                ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \
+                                ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \
+                                ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \
+                                ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \
+                                ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \
+                                ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
+                                ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \
+                                ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \
+                                ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \
+                                ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \
+                                ((LINE) == EXTI_LINE44) || ((LINE) == EXTI_LINE46) || \
+                                ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \
+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
+                                ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
+                                ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \
+                                ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \
+                                ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \
+                                ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \
+                                ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \
+                                ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \
+                                ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \
+                                ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \
+                                ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \
+                                ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \
+                                ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \
+                                ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
+                                ((LINE) == EXTI_LINE77) || ((LINE) == EXTI_LINE79) || \
+                                ((LINE) == EXTI_LINE84) || ((LINE) == EXTI_LINE85) || \
+                                ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87))
+#else
+#define IS_EXTI_D1_LINE(LINE) (((LINE) == EXTI_LINE0)  || ((LINE) == EXTI_LINE1)  || \
+                                ((LINE) == EXTI_LINE2)  || ((LINE) == EXTI_LINE3)  || \
+                                ((LINE) == EXTI_LINE4)  || ((LINE) == EXTI_LINE5)  || \
+                                ((LINE) == EXTI_LINE6)  || ((LINE) == EXTI_LINE7)  || \
+                                ((LINE) == EXTI_LINE8)  || ((LINE) == EXTI_LINE9)  || \
+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
+                                ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
+                                ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
+                                ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
+                                ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \
+                                ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \
+                                ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \
+                                ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \
+                                ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \
+                                ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \
+                                ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
+                                ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \
+                                ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \
+                                ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \
+                                ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \
+                                ((LINE) == EXTI_LINE44) || \
+                                ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \
+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
+                                ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
+                                ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \
+                                ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \
+                                ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \
+                                ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \
+                                ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \
+                                ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \
+                                ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \
+                                ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \
+                                ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \
+                                ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \
+                                ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \
+                                ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
+                                ((LINE) == EXTI_LINE85) || \
+                                ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87) || \
+                                ((LINE) == EXTI_LINE88))
+#endif /*DUAL_CORE*/
+
+#if defined(DUAL_CORE)
+#define IS_EXTI_D2_LINE(LINE) (((LINE) == EXTI_LINE0)  || ((LINE) == EXTI_LINE1)    || \
+                                ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3)   || \
+                                ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5)   || \
+                                ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7)   || \
+                                ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9)   || \
+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
+                                ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
+                                ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
+                                ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
+                                ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \
+                                ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \
+                                ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \
+                                ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \
+                                ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \
+                                ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \
+                                ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
+                                ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \
+                                ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \
+                                ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \
+                                ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \
+                                ((LINE) == EXTI_LINE44) || ((LINE) == EXTI_LINE46) || \
+                                ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \
+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
+                                ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
+                                ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \
+                                ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \
+                                ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \
+                                ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \
+                                ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \
+                                ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \
+                                ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \
+                                ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \
+                                ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \
+                                ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \
+                                ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \
+                                ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
+                                ((LINE) == EXTI_LINE78) || ((LINE) == EXTI_LINE80) || \
+                                ((LINE) == EXTI_LINE82) || ((LINE) == EXTI_LINE85) || \
+                                ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87))
+#endif /*DUAL_CORE*/
+
+#if defined(DUAL_CORE)
+#define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1)    || \
+                                ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3)   || \
+                                ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5)   || \
+                                ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7)   || \
+                                ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9)   || \
+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
+                                ((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || \
+                                ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE25) || \
+                                ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
+                                ((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || \
+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
+                                ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
+                                ((LINE) == EXTI_LINE53))
+#elif (POWER_DOMAINS_NUMBER == 3U)
+#define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1)    || \
+                                ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3)   || \
+                                ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5)   || \
+                                ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7)   || \
+                                ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9)   || \
+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
+                                ((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || \
+                                ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE25) || \
+                                ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
+                                ((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || \
+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
+                                ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
+                                ((LINE) == EXTI_LINE53))
+#else
+#define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1)    || \
+                                ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3)   || \
+                                ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5)   || \
+                                ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7)   || \
+                                ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9)   || \
+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
+                                ((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || \
+                                ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE25) || \
+                                ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
+                                ((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || \
+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
+                                ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE88))
+#endif /*DUAL_CORE*/
+
+
+#define  BDMA_CH6_CLEAR           ((uint32_t)0x00000000)   /*!< BDMA ch6 event selected as D3 domain pendclear source*/
+#define  BDMA_CH7_CLEAR           ((uint32_t)0x00000001)   /*!< BDMA ch7 event selected as D3 domain pendclear source*/
+#if defined (LPTIM4)
+#define  LPTIM4_OUT_CLEAR         ((uint32_t)0x00000002)   /*!< LPTIM4 out selected as D3 domain pendclear source*/
+#else
+#define  LPTIM2_OUT_CLEAR         ((uint32_t)0x00000002)   /*!< LPTIM2 out selected as D3 domain pendclear source*/
+#endif /* LPTIM4 */
+#if defined (LPTIM5)
+#define  LPTIM5_OUT_CLEAR         ((uint32_t)0x00000003)   /*!< LPTIM5 out selected as D3 domain pendclear source*/
+#else
+#define  LPTIM3_OUT_CLEAR         ((uint32_t)0x00000003)   /*!< LPTIM3 out selected as D3 domain pendclear source*/
+#endif /* LPTIM5 */
+#if defined (LPTIM4) && defined (LPTIM5)
+#define IS_EXTI_D3_CLEAR(SOURCE) (((SOURCE) == BDMA_CH6_CLEAR) || ((SOURCE) == BDMA_CH7_CLEAR)    || \
+                                 ((SOURCE) == LPTIM4_OUT_CLEAR) || ((SOURCE) == LPTIM5_OUT_CLEAR))
+#else
+#define IS_EXTI_D3_CLEAR(SOURCE) (((SOURCE) == BDMA_CH6_CLEAR) || ((SOURCE) == BDMA_CH7_CLEAR)    || \
+                                 ((SOURCE) == LPTIM2_OUT_CLEAR) || ((SOURCE) == LPTIM3_OUT_CLEAR))
+#endif /* LPTIM4 LPTIM5 */
+/**
+  * @}
+  */
+
+
+/** @defgroup FMC_SwapBankMapping_Config  SwapBankMapping Config
+  * @{
+  */
+#define FMC_SWAPBMAP_DISABLE             (0x00000000U)
+#define FMC_SWAPBMAP_SDRAM_SRAM          FMC_BCR1_BMAP_0
+#define FMC_SWAPBMAP_SDRAMB2             FMC_BCR1_BMAP_1
+
+#define IS_FMC_SWAPBMAP_MODE(__MODE__) (((__MODE__) == FMC_SWAPBMAP_DISABLE)    || \
+                                        ((__MODE__) == FMC_SWAPBMAP_SDRAM_SRAM) || \
+                                        ((__MODE__) == FMC_SWAPBMAP_SDRAMB2))
+/**
+  * @}
+  */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup ART_Exported_Macros ART Exported Macros
+  * @{
+  */
+#if defined(DUAL_CORE)
+
+/** @brief  ART Enable Macro.
+  *         Enable the Cortex-M4 ART cache.
+  */
+#define __HAL_ART_ENABLE()   SET_BIT(ART->CTR, ART_CTR_EN)
+
+/** @brief  ART Disable Macro.
+  *         Disable the Cortex-M4 ART cache.
+  */
+#define __HAL_ART_DISABLE()   CLEAR_BIT(ART->CTR, ART_CTR_EN)
+
+/** @brief  ART Cache BaseAddress Config.
+  *         Configure the Cortex-M4 ART cache Base Address.
+  */
+#define __HAL_ART_CONFIG_BASE_ADDRESS(__BASE_ADDRESS__)   MODIFY_REG(ART->CTR, ART_CTR_PCACHEADDR, (((__BASE_ADDRESS__) >> 12U) & 0x000FFF00UL))
+
+#endif /* DUAL_CORE */
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
+  * @{
+  */
+
+/** @brief  SYSCFG Break AXIRAM double ECC lock.
+  *         Enable and lock the connection of AXIRAM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_AXISRAM_DBL_ECC_LOCK()     SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML)
+
+/** @brief  SYSCFG Break ITCM double ECC lock.
+  *         Enable and lock the connection of ITCM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_ITCM_DBL_ECC_LOCK()        SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_ITCML)
+
+/** @brief  SYSCFG Break DTCM double ECC lock.
+  *         Enable and lock the connection of DTCM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_DTCM_DBL_ECC_LOCK()        SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_DTCML)
+
+/** @brief  SYSCFG Break SRAM1 double ECC lock.
+  *         Enable and lock the connection of SRAM1 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_SRAM1_DBL_ECC_LOCK()       SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM1L)
+
+/** @brief  SYSCFG Break SRAM2 double ECC lock.
+  *         Enable and lock the connection of SRAM2 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_SRAM2_DBL_ECC_LOCK()       SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM2L)
+
+/** @brief  SYSCFG Break SRAM3 double ECC lock.
+  *         Enable and lock the connection of SRAM3 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_SRAM3_DBL_ECC_LOCK()       SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM3L)
+
+/** @brief  SYSCFG Break SRAM4 double ECC lock.
+  *         Enable and lock the connection of SRAM4 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_SRAM4_DBL_ECC_LOCK()       SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM4L)
+
+/** @brief  SYSCFG Break Backup SRAM double ECC lock.
+  *         Enable and lock the connection of Backup SRAM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_BKRAM_DBL_ECC_LOCK()       SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_BKRAML)
+
+/** @brief  SYSCFG Break Cortex-M7 Lockup lock.
+  *         Enable and lock the connection of Cortex-M7 LOCKUP output to TIM1/8/15/16/17 and HRTIMER Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_CM7_LOCKUP_LOCK()          SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_CM7L)
+
+/** @brief  SYSCFG Break FLASH double ECC lock.
+  *         Enable and lock the connection of Flash double ECC error connection to TIM1/8/15/16/17 and HRTIMER Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_FLASH_DBL_ECC_LOCK()       SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_FLASHL)
+
+/** @brief  SYSCFG Break PVD lock.
+  *         Enable and lock the PVD connection to Timer1/8/15/16/17 and HRTIMER Break input, as well as the PVDE and PLS[2:0] in the PWR_CR1 register.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_PVD_LOCK()                 SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_PVDL)
+
+#if defined(DUAL_CORE)
+/** @brief  SYSCFG Break Cortex-M4 Lockup lock.
+  *         Enable and lock the connection of Cortex-M4 LOCKUP output to TIM1/8/15/16/17 and HRTIMER Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_CM4_LOCKUP_LOCK()          SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_CM4L)
+#endif /* DUAL_CORE */
+
+#if !defined(SYSCFG_PMCR_BOOSTEN)
+/** @brief  Fast-mode Plus driving capability enable/disable macros
+  * @param __FASTMODEPLUS__  This parameter can be a value of :
+  *     @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6
+  *     @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7
+  *     @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8
+  *     @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9
+  */
+#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)  do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
+                                                                SET_BIT(SYSCFG->PMCR, (__FASTMODEPLUS__));\
+                                                               }while(0)
+
+#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
+                                                                CLEAR_BIT(SYSCFG->PMCR, (__FASTMODEPLUS__));\
+                                                               }while(0)
+
+#endif /* !SYSCFG_PMCR_BOOSTEN */
+/**
+  * @}
+  */
+
+/** @brief  Freeze/Unfreeze Peripherals in Debug mode
+  */
+#define __HAL_DBGMCU_FREEZE_WWDG1()          (DBGMCU->APB3FZ1 |= (DBGMCU_APB3FZ1_DBG_WWDG1))
+
+#define __HAL_DBGMCU_FREEZE_TIM2()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM2))
+#define __HAL_DBGMCU_FREEZE_TIM3()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM3))
+#define __HAL_DBGMCU_FREEZE_TIM4()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM4))
+#define __HAL_DBGMCU_FREEZE_TIM5()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM5))
+#define __HAL_DBGMCU_FREEZE_TIM6()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM6))
+#define __HAL_DBGMCU_FREEZE_TIM7()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM7))
+#define __HAL_DBGMCU_FREEZE_TIM12()          (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM12))
+#define __HAL_DBGMCU_FREEZE_TIM13()          (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM13))
+#define __HAL_DBGMCU_FREEZE_TIM14()          (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM14))
+#define __HAL_DBGMCU_FREEZE_LPTIM1()         (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_LPTIM1))
+#define __HAL_DBGMCU_FREEZE_I2C1()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C1))
+#define __HAL_DBGMCU_FREEZE_I2C2()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C2))
+#define __HAL_DBGMCU_FREEZE_I2C3()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C3))
+#define __HAL_DBGMCU_FREEZE_FDCAN()          (DBGMCU->APB1HFZ1 |= (DBGMCU_APB1HFZ1_DBG_FDCAN))
+
+
+#define __HAL_DBGMCU_FREEZE_TIM1()           (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM1))
+#define __HAL_DBGMCU_FREEZE_TIM8()           (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM8))
+#define __HAL_DBGMCU_FREEZE_TIM15()          (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM15))
+#define __HAL_DBGMCU_FREEZE_TIM16()          (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM16))
+#define __HAL_DBGMCU_FREEZE_TIM17()          (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM17))
+#define __HAL_DBGMCU_FREEZE_HRTIM()          (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_HRTIM))
+
+#define __HAL_DBGMCU_FREEZE_I2C4()           (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_I2C4))
+#define __HAL_DBGMCU_FREEZE_LPTIM2()         (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM2))
+#define __HAL_DBGMCU_FREEZE_LPTIM3()         (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM3))
+#define __HAL_DBGMCU_FREEZE_LPTIM4()         (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM4))
+#define __HAL_DBGMCU_FREEZE_LPTIM5()         (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM5))
+#define __HAL_DBGMCU_FREEZE_RTC()            (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_RTC))
+#define __HAL_DBGMCU_FREEZE_IWDG1()          (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_IWDG1))
+
+
+#define __HAL_DBGMCU_UnFreeze_WWDG1()          (DBGMCU->APB3FZ1  &= ~ (DBGMCU_APB3FZ1_DBG_WWDG1))
+
+#define __HAL_DBGMCU_UnFreeze_TIM2()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM2))
+#define __HAL_DBGMCU_UnFreeze_TIM3()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM3))
+#define __HAL_DBGMCU_UnFreeze_TIM4()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM4))
+#define __HAL_DBGMCU_UnFreeze_TIM5()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM5))
+#define __HAL_DBGMCU_UnFreeze_TIM6()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM6))
+#define __HAL_DBGMCU_UnFreeze_TIM7()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM7))
+#define __HAL_DBGMCU_UnFreeze_TIM12()          (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM12))
+#define __HAL_DBGMCU_UnFreeze_TIM13()          (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM13))
+#define __HAL_DBGMCU_UnFreeze_TIM14()          (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM14))
+#define __HAL_DBGMCU_UnFreeze_LPTIM1()         (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_LPTIM1))
+#define __HAL_DBGMCU_UnFreeze_I2C1()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_I2C1))
+#define __HAL_DBGMCU_UnFreeze_I2C2()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_I2C2))
+#define __HAL_DBGMCU_UnFreeze_I2C3()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_I2C3))
+#define __HAL_DBGMCU_UnFreeze_FDCAN()          (DBGMCU->APB1HFZ1  &= ~ (DBGMCU_APB1HFZ1_DBG_FDCAN))
+
+
+#define __HAL_DBGMCU_UnFreeze_TIM1()           (DBGMCU->APB2FZ1  &= ~ (DBGMCU_APB2FZ1_DBG_TIM1))
+#define __HAL_DBGMCU_UnFreeze_TIM8()           (DBGMCU->APB2FZ1  &= ~ (DBGMCU_APB2FZ1_DBG_TIM8))
+#define __HAL_DBGMCU_UnFreeze_TIM15()          (DBGMCU->APB2FZ1  &= ~ (DBGMCU_APB2FZ1_DBG_TIM15))
+#define __HAL_DBGMCU_UnFreeze_TIM16()          (DBGMCU->APB2FZ1  &= ~ (DBGMCU_APB2FZ1_DBG_TIM16))
+#define __HAL_DBGMCU_UnFreeze_TIM17()          (DBGMCU->APB2FZ1  &= ~ (DBGMCU_APB2FZ1_DBG_TIM17))
+#define __HAL_DBGMCU_UnFreeze_HRTIM()          (DBGMCU->APB2FZ1  &= ~ (DBGMCU_APB2FZ1_DBG_HRTIM))
+
+#define __HAL_DBGMCU_UnFreeze_I2C4()           (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_I2C4))
+#define __HAL_DBGMCU_UnFreeze_LPTIM2()         (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM2))
+#define __HAL_DBGMCU_UnFreeze_LPTIM3()         (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM3))
+#define __HAL_DBGMCU_UnFreeze_LPTIM4()         (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM4))
+#define __HAL_DBGMCU_UnFreeze_LPTIM5()         (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM5))
+#define __HAL_DBGMCU_UnFreeze_RTC()            (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_RTC))
+#define __HAL_DBGMCU_UnFreeze_IWDG1()          (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_IWDG1))
+
+
+#if defined(DUAL_CORE)
+#define __HAL_DBGMCU_FREEZE2_IWDG2()          (DBGMCU->APB4FZ2  |= (DBGMCU_APB4FZ2_DBG_IWDG2))
+#define __HAL_DBGMCU_FREEZE2_WWDG2()          (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_WWDG2))
+
+#define __HAL_DBGMCU_UnFreeze2_IWDG2()        (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_IWDG2))
+#define __HAL_DBGMCU_UnFreeze2_WWDG2()        (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_WWDG2))
+
+
+#define __HAL_DBGMCU_FREEZE2_WWDG1()          (DBGMCU->APB3FZ2 |= (DBGMCU_APB3FZ2_DBG_WWDG1))
+
+#define __HAL_DBGMCU_FREEZE2_TIM2()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM2))
+#define __HAL_DBGMCU_FREEZE2_TIM3()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM3))
+#define __HAL_DBGMCU_FREEZE2_TIM4()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM4))
+#define __HAL_DBGMCU_FREEZE2_TIM5()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM5))
+#define __HAL_DBGMCU_FREEZE2_TIM6()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM6))
+#define __HAL_DBGMCU_FREEZE2_TIM7()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM7))
+#define __HAL_DBGMCU_FREEZE2_TIM12()          (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM12))
+#define __HAL_DBGMCU_FREEZE2_TIM13()          (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM13))
+#define __HAL_DBGMCU_FREEZE2_TIM14()          (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM14))
+#define __HAL_DBGMCU_FREEZE2_LPTIM1()         (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_LPTIM1))
+#define __HAL_DBGMCU_FREEZE2_I2C1()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_I2C1))
+#define __HAL_DBGMCU_FREEZE2_I2C2()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_I2C2))
+#define __HAL_DBGMCU_FREEZE2_I2C3()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_I2C3))
+#define __HAL_DBGMCU_FREEZE2_FDCAN()          (DBGMCU->APB1HFZ2 |= (DBGMCU_APB1HFZ2_DBG_FDCAN))
+
+
+#define __HAL_DBGMCU_FREEZE2_TIM1()           (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM1))
+#define __HAL_DBGMCU_FREEZE2_TIM8()           (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM8))
+#define __HAL_DBGMCU_FREEZE2_TIM15()          (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM15))
+#define __HAL_DBGMCU_FREEZE2_TIM16()          (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM16))
+#define __HAL_DBGMCU_FREEZE2_TIM17()          (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM17))
+#define __HAL_DBGMCU_FREEZE2_HRTIM()          (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_HRTIM))
+
+#define __HAL_DBGMCU_FREEZE2_I2C4()           (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_I2C4))
+#define __HAL_DBGMCU_FREEZE2_LPTIM2()         (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM2))
+#define __HAL_DBGMCU_FREEZE2_LPTIM3()         (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM3))
+#define __HAL_DBGMCU_FREEZE2_LPTIM4()         (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM4))
+#define __HAL_DBGMCU_FREEZE2_LPTIM5()         (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM5))
+#define __HAL_DBGMCU_FREEZE2_RTC()            (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_RTC))
+#define __HAL_DBGMCU_FREEZE2_IWDG1()          (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_IWDG1))
+
+#define __HAL_DBGMCU_UnFreeze2_WWDG1()          (DBGMCU->APB3FZ2  &= ~ (DBGMCU_APB3FZ2_DBG_WWDG1))
+
+#define __HAL_DBGMCU_UnFreeze2_TIM2()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM2))
+#define __HAL_DBGMCU_UnFreeze2_TIM3()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM3))
+#define __HAL_DBGMCU_UnFreeze2_TIM4()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM4))
+#define __HAL_DBGMCU_UnFreeze2_TIM5()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM5))
+#define __HAL_DBGMCU_UnFreeze2_TIM6()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM6))
+#define __HAL_DBGMCU_UnFreeze2_TIM7()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM7))
+#define __HAL_DBGMCU_UnFreeze2_TIM12()          (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM12))
+#define __HAL_DBGMCU_UnFreeze2_TIM13()          (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM13))
+#define __HAL_DBGMCU_UnFreeze2_TIM14()          (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM14))
+#define __HAL_DBGMCU_UnFreeze2_LPTIM1()         (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_LPTIM1))
+#define __HAL_DBGMCU_UnFreeze2_I2C1()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_I2C1))
+#define __HAL_DBGMCU_UnFreeze2_I2C2()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_I2C2))
+#define __HAL_DBGMCU_UnFreeze2_I2C3()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_I2C3))
+#define __HAL_DBGMCU_UnFreeze2_FDCAN()          (DBGMCU->APB1HFZ2  &= ~ (DBGMCU_APB1HFZ2_DBG_FDCAN))
+
+
+#define __HAL_DBGMCU_UnFreeze2_TIM1()           (DBGMCU->APB2FZ2  &= ~ (DBGMCU_APB2FZ2_DBG_TIM1))
+#define __HAL_DBGMCU_UnFreeze2_TIM8()           (DBGMCU->APB2FZ2  &= ~ (DBGMCU_APB2FZ2_DBG_TIM8))
+#define __HAL_DBGMCU_UnFreeze2_TIM15()          (DBGMCU->APB2FZ2  &= ~ (DBGMCU_APB2FZ2_DBG_TIM15))
+#define __HAL_DBGMCU_UnFreeze2_TIM16()          (DBGMCU->APB2FZ2  &= ~ (DBGMCU_APB2FZ2_DBG_TIM16))
+#define __HAL_DBGMCU_UnFreeze2_TIM17()          (DBGMCU->APB2FZ2  &= ~ (DBGMCU_APB2FZ2_DBG_TIM17))
+#define __HAL_DBGMCU_UnFreeze2_HRTIM()          (DBGMCU->APB2FZ2  &= ~ (DBGMCU_APB2FZ2_DBG_HRTIM))
+
+#define __HAL_DBGMCU_UnFreeze2_I2C4()           (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_I2C4))
+#define __HAL_DBGMCU_UnFreeze2_LPTIM2()         (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM2))
+#define __HAL_DBGMCU_UnFreeze2_LPTIM3()         (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM3))
+#define __HAL_DBGMCU_UnFreeze2_LPTIM4()         (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM4))
+#define __HAL_DBGMCU_UnFreeze2_LPTIM5()         (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM5))
+#define __HAL_DBGMCU_UnFreeze2_RTC()            (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_RTC))
+#define __HAL_DBGMCU_UnFreeze2_IWDG1()          (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_IWDG1))
+
+#endif /*DUAL_CORE*/
+
+/** @defgroup HAL_Private_Macros HAL Private Macros
+  * @{
+  */
+#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ)  || \
+                           ((FREQ) == HAL_TICK_FREQ_100HZ) || \
+                           ((FREQ) == HAL_TICK_FREQ_1KHZ))
+/**
+  * @}
+  */
+
+/* Exported variables --------------------------------------------------------*/
+
+/** @addtogroup HAL_Exported_Variables
+  * @{
+  */
+extern __IO uint32_t uwTick;
+extern uint32_t uwTickPrio;
+extern HAL_TickFreqTypeDef uwTickFreq;
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization and de-initialization functions  ******************************/
+HAL_StatusTypeDef HAL_Init(void);
+HAL_StatusTypeDef HAL_DeInit(void);
+void HAL_MspInit(void);
+void HAL_MspDeInit(void);
+HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
+
+/* Peripheral Control functions  ************************************************/
+void HAL_IncTick(void);
+void HAL_Delay(uint32_t Delay);
+uint32_t HAL_GetTick(void);
+uint32_t HAL_GetTickPrio(void);
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
+HAL_TickFreqTypeDef HAL_GetTickFreq(void);
+void HAL_SuspendTick(void);
+void HAL_ResumeTick(void);
+uint32_t HAL_GetHalVersion(void);
+uint32_t HAL_GetREVID(void);
+uint32_t HAL_GetDEVID(void);
+uint32_t HAL_GetUIDw0(void);
+uint32_t HAL_GetUIDw1(void);
+uint32_t HAL_GetUIDw2(void);
+#if defined(SYSCFG_PMCR_EPIS_SEL)
+void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface);
+#endif /* SYSCFG_PMCR_EPIS_SEL */
+void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState );
+#if defined(SYSCFG_PMCR_BOOSTEN)
+void HAL_SYSCFG_EnableBOOST(void);
+void HAL_SYSCFG_DisableBOOST(void);
+#endif /* SYSCFG_PMCR_BOOSTEN */
+
+#if defined (SYSCFG_UR2_BOOT_ADD0) ||  defined (SYSCFG_UR2_BCM7_ADD0)
+void HAL_SYSCFG_CM7BootAddConfig(uint32_t BootRegister, uint32_t BootAddress);
+#endif /* SYSCFG_UR2_BOOT_ADD0 || SYSCFG_UR2_BCM7_ADD0*/
+
+#if defined(DUAL_CORE)
+void HAL_SYSCFG_CM4BootAddConfig(uint32_t BootRegister, uint32_t BootAddress);
+void HAL_SYSCFG_EnableCM7BOOT(void);
+void HAL_SYSCFG_DisableCM7BOOT(void);
+void HAL_SYSCFG_EnableCM4BOOT(void);
+void HAL_SYSCFG_DisableCM4BOOT(void);
+#endif /*DUAL_CORE*/
+void HAL_EnableCompensationCell(void);
+void HAL_DisableCompensationCell(void);
+void HAL_SYSCFG_EnableIOSpeedOptimize(void);
+void HAL_SYSCFG_DisableIOSpeedOptimize(void);
+void HAL_SYSCFG_CompensationCodeSelect(uint32_t SYSCFG_CompCode);
+void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode);
+#if defined(SYSCFG_CCCR_NCC_MMC)
+void HAL_SYSCFG_VDDMMC_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode);
+#endif /* SYSCFG_CCCR_NCC_MMC */
+void HAL_EnableDBGSleepMode(void);
+void HAL_DisableDBGSleepMode(void);
+void HAL_EnableDBGStopMode(void);
+void HAL_DisableDBGStopMode(void);
+void HAL_EnableDBGStandbyMode(void);
+void HAL_DisableDBGStandbyMode(void);
+#if defined(DUAL_CORE)
+void HAL_EnableDomain2DBGSleepMode(void);
+void HAL_DisableDomain2DBGSleepMode(void);
+void HAL_EnableDomain2DBGStopMode(void);
+void HAL_DisableDomain2DBGStopMode(void);
+void HAL_EnableDomain2DBGStandbyMode(void);
+void HAL_DisableDomain2DBGStandbyMode(void);
+#endif /*DUAL_CORE*/
+void HAL_EnableDomain3DBGStopMode(void);
+void HAL_DisableDomain3DBGStopMode(void);
+void HAL_EnableDomain3DBGStandbyMode(void);
+void HAL_DisableDomain3DBGStandbyMode(void);
+void HAL_EXTI_EdgeConfig(uint32_t EXTI_Line , uint32_t EXTI_Edge );
+void HAL_EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
+#if defined(DUAL_CORE)
+void HAL_EXTI_D2_ClearFlag(uint32_t EXTI_Line);
+#endif /*DUAL_CORE*/
+void HAL_EXTI_D1_ClearFlag(uint32_t EXTI_Line);
+void HAL_EXTI_D1_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode,  uint32_t EXTI_LineCmd);
+#if defined(DUAL_CORE)
+void HAL_EXTI_D2_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode,  uint32_t EXTI_LineCmd);
+#endif /*DUAL_CORE*/
+void HAL_EXTI_D3_EventInputConfig(uint32_t EXTI_Line, uint32_t EXTI_LineCmd , uint32_t EXTI_ClearSrc);
+void HAL_SetFMCMemorySwappingConfig(uint32_t BankMapConfig);
+uint32_t HAL_GetFMCMemorySwappingConfig(void);
+void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
+void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
+void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
+HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
+void HAL_SYSCFG_DisableVREFBUF(void);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h
new file mode 100644
index 00000000..4eca4390
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h
@@ -0,0 +1,461 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_cortex.h
+  * @author  MCD Application Team
+  * @brief   Header file of CORTEX HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_CORTEX_H
+#define STM32H7xx_HAL_CORTEX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup CORTEX
+  * @{
+  */
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Types Cortex Exported Types
+  * @{
+  */
+
+#if (__MPU_PRESENT == 1)
+/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
+  * @brief  MPU Region initialization structure
+  * @{
+  */
+typedef struct
+{
+  uint8_t                Enable;                /*!< Specifies the status of the region.
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */
+  uint8_t                Number;                /*!< Specifies the number of the region to protect.
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */
+  uint32_t               BaseAddress;           /*!< Specifies the base address of the region to protect.                           */
+  uint8_t                Size;                  /*!< Specifies the size of the region to protect.
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Size                   */
+  uint8_t                SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable.
+                                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */
+  uint8_t                TypeExtField;          /*!< Specifies the TEX field level.
+                                                     This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                    */
+  uint8_t                AccessPermission;      /*!< Specifies the region access permission type.
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */
+  uint8_t                DisableExec;           /*!< Specifies the instruction access status.
+                                                     This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */
+  uint8_t                IsShareable;           /*!< Specifies the shareability status of the protected region.
+                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */
+  uint8_t                IsCacheable;           /*!< Specifies the cacheable status of the region protected.
+                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable              */
+  uint8_t                IsBufferable;          /*!< Specifies the bufferable status of the protected region.
+                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable             */
+}MPU_Region_InitTypeDef;
+/**
+  * @}
+  */
+#endif /* __MPU_PRESENT */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
+  * @{
+  */
+
+/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
+  * @{
+  */
+#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority
+                                                                 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority
+                                                                 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority
+                                                                 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority
+                                                                 1 bits for subpriority */
+#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority
+                                                                 0 bits for subpriority */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
+  * @{
+  */
+#define SYSTICK_CLKSOURCE_HCLK_DIV8    ((uint32_t)0x00000000)
+#define SYSTICK_CLKSOURCE_HCLK         ((uint32_t)0x00000004)
+
+/**
+  * @}
+  */
+
+#if (__MPU_PRESENT == 1)
+/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
+  * @{
+  */
+#define  MPU_HFNMI_PRIVDEF_NONE      ((uint32_t)0x00000000)
+#define  MPU_HARDFAULT_NMI           ((uint32_t)0x00000002)
+#define  MPU_PRIVILEGED_DEFAULT      ((uint32_t)0x00000004)
+#define  MPU_HFNMI_PRIVDEF           ((uint32_t)0x00000006)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
+  * @{
+  */
+#define  MPU_REGION_ENABLE     ((uint8_t)0x01)
+#define  MPU_REGION_DISABLE    ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
+  * @{
+  */
+#define  MPU_INSTRUCTION_ACCESS_ENABLE      ((uint8_t)0x00)
+#define  MPU_INSTRUCTION_ACCESS_DISABLE     ((uint8_t)0x01)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
+  * @{
+  */
+#define  MPU_ACCESS_SHAREABLE        ((uint8_t)0x01)
+#define  MPU_ACCESS_NOT_SHAREABLE    ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
+  * @{
+  */
+#define  MPU_ACCESS_CACHEABLE         ((uint8_t)0x01)
+#define  MPU_ACCESS_NOT_CACHEABLE     ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
+  * @{
+  */
+#define  MPU_ACCESS_BUFFERABLE         ((uint8_t)0x01)
+#define  MPU_ACCESS_NOT_BUFFERABLE     ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
+  * @{
+  */
+#define  MPU_TEX_LEVEL0    ((uint8_t)0x00)
+#define  MPU_TEX_LEVEL1    ((uint8_t)0x01)
+#define  MPU_TEX_LEVEL2    ((uint8_t)0x02)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
+  * @{
+  */
+#define   MPU_REGION_SIZE_32B      ((uint8_t)0x04)
+#define   MPU_REGION_SIZE_64B      ((uint8_t)0x05)
+#define   MPU_REGION_SIZE_128B     ((uint8_t)0x06)
+#define   MPU_REGION_SIZE_256B     ((uint8_t)0x07)
+#define   MPU_REGION_SIZE_512B     ((uint8_t)0x08)
+#define   MPU_REGION_SIZE_1KB      ((uint8_t)0x09)
+#define   MPU_REGION_SIZE_2KB      ((uint8_t)0x0A)
+#define   MPU_REGION_SIZE_4KB      ((uint8_t)0x0B)
+#define   MPU_REGION_SIZE_8KB      ((uint8_t)0x0C)
+#define   MPU_REGION_SIZE_16KB     ((uint8_t)0x0D)
+#define   MPU_REGION_SIZE_32KB     ((uint8_t)0x0E)
+#define   MPU_REGION_SIZE_64KB     ((uint8_t)0x0F)
+#define   MPU_REGION_SIZE_128KB    ((uint8_t)0x10)
+#define   MPU_REGION_SIZE_256KB    ((uint8_t)0x11)
+#define   MPU_REGION_SIZE_512KB    ((uint8_t)0x12)
+#define   MPU_REGION_SIZE_1MB      ((uint8_t)0x13)
+#define   MPU_REGION_SIZE_2MB      ((uint8_t)0x14)
+#define   MPU_REGION_SIZE_4MB      ((uint8_t)0x15)
+#define   MPU_REGION_SIZE_8MB      ((uint8_t)0x16)
+#define   MPU_REGION_SIZE_16MB     ((uint8_t)0x17)
+#define   MPU_REGION_SIZE_32MB     ((uint8_t)0x18)
+#define   MPU_REGION_SIZE_64MB     ((uint8_t)0x19)
+#define   MPU_REGION_SIZE_128MB    ((uint8_t)0x1A)
+#define   MPU_REGION_SIZE_256MB    ((uint8_t)0x1B)
+#define   MPU_REGION_SIZE_512MB    ((uint8_t)0x1C)
+#define   MPU_REGION_SIZE_1GB      ((uint8_t)0x1D)
+#define   MPU_REGION_SIZE_2GB      ((uint8_t)0x1E)
+#define   MPU_REGION_SIZE_4GB      ((uint8_t)0x1F)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
+  * @{
+  */
+#define  MPU_REGION_NO_ACCESS      ((uint8_t)0x00)
+#define  MPU_REGION_PRIV_RW        ((uint8_t)0x01)
+#define  MPU_REGION_PRIV_RW_URO    ((uint8_t)0x02)
+#define  MPU_REGION_FULL_ACCESS    ((uint8_t)0x03)
+#define  MPU_REGION_PRIV_RO        ((uint8_t)0x05)
+#define  MPU_REGION_PRIV_RO_URO    ((uint8_t)0x06)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
+  * @{
+  */
+#define  MPU_REGION_NUMBER0    ((uint8_t)0x00)
+#define  MPU_REGION_NUMBER1    ((uint8_t)0x01)
+#define  MPU_REGION_NUMBER2    ((uint8_t)0x02)
+#define  MPU_REGION_NUMBER3    ((uint8_t)0x03)
+#define  MPU_REGION_NUMBER4    ((uint8_t)0x04)
+#define  MPU_REGION_NUMBER5    ((uint8_t)0x05)
+#define  MPU_REGION_NUMBER6    ((uint8_t)0x06)
+#define  MPU_REGION_NUMBER7    ((uint8_t)0x07)
+#if !defined(CORE_CM4)
+#define  MPU_REGION_NUMBER8    ((uint8_t)0x08)
+#define  MPU_REGION_NUMBER9    ((uint8_t)0x09)
+#define  MPU_REGION_NUMBER10   ((uint8_t)0x0A)
+#define  MPU_REGION_NUMBER11   ((uint8_t)0x0B)
+#define  MPU_REGION_NUMBER12   ((uint8_t)0x0C)
+#define  MPU_REGION_NUMBER13   ((uint8_t)0x0D)
+#define  MPU_REGION_NUMBER14   ((uint8_t)0x0E)
+#define  MPU_REGION_NUMBER15   ((uint8_t)0x0F)
+#endif /* !defined(CORE_CM4) */
+
+/**
+  * @}
+  */
+#endif /* __MPU_PRESENT */
+
+/**
+  * @}
+  */
+
+
+/* Exported Macros -----------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+
+/** @defgroup CORTEX_CPU_Identifier CORTEX_CPU_Identifier
+  * @{
+  */
+#define CM7_CPUID        ((uint32_t)0x00000003)
+
+#if defined(DUAL_CORE)
+#define CM4_CPUID        ((uint32_t)0x00000001)
+#endif /*DUAL_CORE*/
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CORTEX_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup CORTEX_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SystemReset(void);
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
+/**
+  * @}
+  */
+
+/** @addtogroup CORTEX_Exported_Functions_Group2
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+#if (__MPU_PRESENT == 1)
+void HAL_MPU_Enable(uint32_t MPU_Control);
+void HAL_MPU_Disable(void);
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
+#endif /* __MPU_PRESENT */
+uint32_t HAL_NVIC_GetPriorityGrouping(void);
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
+void HAL_SYSTICK_IRQHandler(void);
+void HAL_SYSTICK_Callback(void);
+uint32_t HAL_GetCurrentCPUID(void);
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
+  * @{
+  */
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_1) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_2) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_3) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10UL)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY)         ((PRIORITY) < 0x10UL)
+
+#define IS_NVIC_DEVICE_IRQ(IRQ)                (((int32_t)IRQ) >= 0x00)
+
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
+                                       ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
+
+#if (__MPU_PRESENT == 1)
+#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
+                                     ((STATE) == MPU_REGION_DISABLE))
+
+#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
+                                          ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
+
+#define IS_MPU_ACCESS_SHAREABLE(STATE)   (((STATE) == MPU_ACCESS_SHAREABLE) || \
+                                          ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
+
+#define IS_MPU_ACCESS_CACHEABLE(STATE)   (((STATE) == MPU_ACCESS_CACHEABLE) || \
+                                          ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
+
+#define IS_MPU_ACCESS_BUFFERABLE(STATE)   (((STATE) == MPU_ACCESS_BUFFERABLE) || \
+                                          ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
+
+#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0)  || \
+                                ((TYPE) == MPU_TEX_LEVEL1)  || \
+                                ((TYPE) == MPU_TEX_LEVEL2))
+
+#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS)   || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RW)     || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
+                                                  ((TYPE) == MPU_REGION_FULL_ACCESS) || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RO)     || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RO_URO))
+
+#if !defined(CORE_CM4)
+#define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER1)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER2)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER3)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER4)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER5)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER6)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER7)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER8)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER9)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER10) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER11) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER12) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER13) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER14) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER15))
+#else
+#define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER1)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER2)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER3)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER4)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER5)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER6)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER7))
+#endif /* !defined(CORE_CM4) */
+
+#define IS_MPU_REGION_SIZE(SIZE)    (((SIZE) == MPU_REGION_SIZE_32B)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_64B)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_128B)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_256B)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_512B)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_1KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_2KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_4KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_8KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_16KB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_32KB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_64KB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_128KB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_256KB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_512KB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_1MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_2MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_4MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_8MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_16MB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_32MB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_64MB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_128MB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_256MB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_512MB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_1GB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_2GB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_4GB))
+
+#define IS_MPU_SUB_REGION_DISABLE(SUBREGION)  ((SUBREGION) < (uint16_t)0x00FF)
+#endif /* __MPU_PRESENT */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_CORTEX_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h
new file mode 100644
index 00000000..fce605de
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h
@@ -0,0 +1,188 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_def.h
+  * @author  MCD Application Team
+  * @brief   This file contains HAL common defines, enumeration, macros and
+  *          structures definitions.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_DEF
+#define STM32H7xx_HAL_DEF
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+#include "Legacy/stm32_hal_legacy.h"
+#include <stddef.h>
+#include <math.h>
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+  * @brief  HAL Status structures definition
+  */
+typedef enum
+{
+  HAL_OK       = 0x00,
+  HAL_ERROR    = 0x01,
+  HAL_BUSY     = 0x02,
+  HAL_TIMEOUT  = 0x03
+} HAL_StatusTypeDef;
+
+/**
+  * @brief  HAL Lock structures definition
+  */
+typedef enum
+{
+  HAL_UNLOCKED = 0x00,
+  HAL_LOCKED   = 0x01
+} HAL_LockTypeDef;
+
+/* Exported macro ------------------------------------------------------------*/
+
+#define HAL_MAX_DELAY      0xFFFFFFFFU
+
+#define HAL_IS_BIT_SET(REG, BIT)         (((REG) & (BIT)) == (BIT))
+#define HAL_IS_BIT_CLR(REG, BIT)         (((REG) & (BIT)) == 0U)
+
+#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__)               \
+                        do{                                                      \
+                              (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
+                              (__DMA_HANDLE__).Parent = (__HANDLE__);             \
+                          } while(0)
+
+#define UNUSED(x) ((void)(x))
+
+/** @brief Reset the Handle's State field.
+  * @param __HANDLE__: specifies the Peripheral Handle.
+  * @note  This macro can be used for the following purpose: 
+  *          - When the Handle is declared as local variable; before passing it as parameter
+  *            to HAL_PPP_Init() for the first time, it is mandatory to use this macro 
+  *            to set to 0 the Handle's "State" field.
+  *            Otherwise, "State" field may have any random value and the first time the function 
+  *            HAL_PPP_Init() is called, the low level hardware initialization will be missed
+  *            (i.e. HAL_PPP_MspInit() will not be executed).
+  *          - When there is a need to reconfigure the low level hardware: instead of calling
+  *            HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
+  *            In this later function, when the Handle's "State" field is set to 0, it will execute the function
+  *            HAL_PPP_MspInit() which will reconfigure the low level hardware.
+  * @retval None
+  */
+#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
+
+#if (USE_RTOS == 1)
+  #error " USE_RTOS should be 0 in the current HAL release "
+#else
+  #define __HAL_LOCK(__HANDLE__)                                           \
+                                do{                                        \
+                                    if((__HANDLE__)->Lock == HAL_LOCKED)   \
+                                    {                                      \
+                                       return HAL_BUSY;                    \
+                                    }                                      \
+                                    else                                   \
+                                    {                                      \
+                                       (__HANDLE__)->Lock = HAL_LOCKED;    \
+                                    }                                      \
+                                  }while (0)
+
+  #define __HAL_UNLOCK(__HANDLE__)                                          \
+                                  do{                                       \
+                                      (__HANDLE__)->Lock = HAL_UNLOCKED;    \
+                                    }while (0)
+#endif /* USE_RTOS */
+
+#if  defined ( __GNUC__ )
+  #ifndef __weak
+    #define __weak   __attribute__((weak))
+  #endif /* __weak */
+  #ifndef __packed
+    #define __packed __attribute__((__packed__))
+  #endif /* __packed */
+#endif /* __GNUC__ */
+
+
+/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
+#if defined   (__GNUC__)        /* GNU Compiler */
+  #ifndef __ALIGN_END
+    #define __ALIGN_END    __attribute__ ((aligned (4)))
+  #endif /* __ALIGN_END */
+  #ifndef __ALIGN_BEGIN
+    #define __ALIGN_BEGIN
+  #endif /* __ALIGN_BEGIN */
+#else
+  #ifndef __ALIGN_END
+    #define __ALIGN_END
+  #endif /* __ALIGN_END */
+  #ifndef __ALIGN_BEGIN
+    #if defined   (__CC_ARM)      /* ARM Compiler */
+      #define __ALIGN_BEGIN    __align(4)
+    #elif defined (__ICCARM__)    /* IAR Compiler */
+      #define __ALIGN_BEGIN
+    #endif /* __CC_ARM */
+  #endif /* __ALIGN_BEGIN */
+#endif /* __GNUC__ */
+
+/* Macro to get variable aligned on 32-bytes,needed for cache maintenance purpose */
+#if defined   (__GNUC__)        /* GNU Compiler */
+  #define ALIGN_32BYTES(buf)  buf __attribute__ ((aligned (32)))                                    
+#elif defined (__ICCARM__)    /* IAR Compiler */
+  #define ALIGN_32BYTES(buf) _Pragma("data_alignment=32") buf  
+#elif defined   (__CC_ARM)      /* ARM Compiler */
+  #define ALIGN_32BYTES(buf) __align(32) buf  
+#endif
+
+/**
+  * @brief  __RAM_FUNC definition
+  */
+#if defined ( __CC_ARM   )
+/* ARM Compiler
+   ------------
+   RAM functions are defined using the toolchain options.
+   Functions that are executed in RAM should reside in a separate source module.
+   Using the 'Options for File' dialog you can simply change the 'Code / Const'
+   area of a module to a memory space in physical RAM.
+   Available memory areas are declared in the 'Target' tab of the 'Options for Target'
+   dialog.
+*/
+#define __RAM_FUNC
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+   ---------------
+   RAM functions are defined using a specific toolchain keyword "__ramfunc".
+*/
+#define __RAM_FUNC __ramfunc
+
+#elif defined   (  __GNUC__  )
+/* GNU Compiler
+   ------------
+  RAM functions are defined using a specific toolchain attribute
+   "__attribute__((section(".RamFunc")))".
+*/
+#define __RAM_FUNC __attribute__((section(".RamFunc")))
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_DEF */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h
new file mode 100644
index 00000000..36d553b0
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h
@@ -0,0 +1,1290 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_dma.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMA HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_DMA_H
+#define STM32H7xx_HAL_DMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DMA
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Types DMA Exported Types
+  * @brief    DMA Exported Types
+  * @{
+  */
+
+/**
+  * @brief  DMA Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t Request;               /*!< Specifies the request selected for the specified stream.
+                                           This parameter can be a value of @ref DMA_Request_selection              */
+
+  uint32_t Direction;            /*!< Specifies if the data will be transferred from memory to peripheral,
+                                      from memory to memory or from peripheral to memory.
+                                      This parameter can be a value of @ref DMA_Data_transfer_direction              */
+
+  uint32_t PeriphInc;            /*!< Specifies whether the Peripheral address register should be incremented or not.
+                                      This parameter can be a value of @ref DMA_Peripheral_incremented_mode          */
+
+  uint32_t MemInc;               /*!< Specifies whether the memory address register should be incremented or not.
+                                      This parameter can be a value of @ref DMA_Memory_incremented_mode              */
+
+  uint32_t PeriphDataAlignment;  /*!< Specifies the Peripheral data width.
+                                      This parameter can be a value of @ref DMA_Peripheral_data_size                 */
+
+  uint32_t MemDataAlignment;     /*!< Specifies the Memory data width.
+                                      This parameter can be a value of @ref DMA_Memory_data_size                     */
+
+  uint32_t Mode;                 /*!< Specifies the operation mode of the DMAy Streamx.
+                                      This parameter can be a value of @ref DMA_mode
+                                      @note The circular buffer mode cannot be used if the memory-to-memory
+                                            data transfer is configured on the selected Stream                        */
+
+  uint32_t Priority;             /*!< Specifies the software priority for the DMAy Streamx.
+                                      This parameter can be a value of @ref DMA_Priority_level                        */
+
+  uint32_t FIFOMode;             /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
+                                      This parameter can be a value of @ref DMA_FIFO_direct_mode
+                                      @note The Direct mode (FIFO mode disabled) cannot be used if the
+                                            memory-to-memory data transfer is configured on the selected stream       */
+
+  uint32_t FIFOThreshold;        /*!< Specifies the FIFO threshold level.
+                                      This parameter can be a value of @ref DMA_FIFO_threshold_level                  */
+
+  uint32_t MemBurst;             /*!< Specifies the Burst transfer configuration for the memory transfers.
+                                      It specifies the amount of data to be transferred in a single non interruptible
+                                      transaction.
+                                      This parameter can be a value of @ref DMA_Memory_burst
+                                      @note The burst mode is possible only if the address Increment mode is enabled. */
+
+  uint32_t PeriphBurst;          /*!< Specifies the Burst transfer configuration for the peripheral transfers.
+                                      It specifies the amount of data to be transferred in a single non interruptible
+                                      transaction.
+                                      This parameter can be a value of @ref DMA_Peripheral_burst
+                                      @note The burst mode is possible only if the address Increment mode is enabled. */
+}DMA_InitTypeDef;
+
+/**
+  * @brief  HAL DMA State structures definition
+  */
+typedef enum
+{
+  HAL_DMA_STATE_RESET             = 0x00U,  /*!< DMA not yet initialized or disabled */
+  HAL_DMA_STATE_READY             = 0x01U,  /*!< DMA initialized and ready for use   */
+  HAL_DMA_STATE_BUSY              = 0x02U,  /*!< DMA process is ongoing              */
+  HAL_DMA_STATE_ERROR             = 0x03U,  /*!< DMA error state                     */
+  HAL_DMA_STATE_ABORT             = 0x04U,  /*!< DMA Abort state                     */
+}HAL_DMA_StateTypeDef;
+
+/**
+  * @brief  HAL DMA Transfer complete level structure definition
+  */
+typedef enum
+{
+  HAL_DMA_FULL_TRANSFER      = 0x00U,    /*!< Full transfer     */
+  HAL_DMA_HALF_TRANSFER      = 0x01U,    /*!< Half Transfer     */
+}HAL_DMA_LevelCompleteTypeDef;
+
+/**
+  * @brief  HAL DMA Callbacks IDs structure definition
+  */
+typedef enum
+{
+  HAL_DMA_XFER_CPLT_CB_ID          = 0x00U,    /*!< Full transfer     */
+  HAL_DMA_XFER_HALFCPLT_CB_ID      = 0x01U,    /*!< Half Transfer     */
+  HAL_DMA_XFER_M1CPLT_CB_ID        = 0x02U,    /*!< M1 Full Transfer  */
+  HAL_DMA_XFER_M1HALFCPLT_CB_ID    = 0x03U,    /*!< M1 Half Transfer  */
+  HAL_DMA_XFER_ERROR_CB_ID         = 0x04U,    /*!< Error             */
+  HAL_DMA_XFER_ABORT_CB_ID         = 0x05U,    /*!< Abort             */
+  HAL_DMA_XFER_ALL_CB_ID           = 0x06U     /*!< All               */
+}HAL_DMA_CallbackIDTypeDef;
+
+/**
+  * @brief  DMA handle Structure definition
+  */
+typedef struct __DMA_HandleTypeDef
+{
+  void                            *Instance;                                                        /*!< Register base address                         */
+
+  DMA_InitTypeDef                 Init;                                                             /*!< DMA communication parameters                  */
+
+  HAL_LockTypeDef                 Lock;                                                             /*!< DMA locking object                            */
+
+  __IO HAL_DMA_StateTypeDef       State;                                                            /*!< DMA transfer state                            */
+
+  void                            *Parent;                                                          /*!< Parent object state                           */
+
+  void                            (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);         /*!< DMA transfer complete callback                */
+
+  void                            (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);     /*!< DMA Half transfer complete callback           */
+
+  void                            (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma);       /*!< DMA transfer complete Memory1 callback        */
+
+  void                            (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);   /*!< DMA transfer Half complete Memory1 callback   */
+
+  void                            (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);        /*!< DMA transfer error callback                   */
+
+  void                            (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma);        /*!< DMA transfer Abort callback                   */
+
+ __IO uint32_t                    ErrorCode;                                                        /*!< DMA Error code                                */
+
+ uint32_t                         StreamBaseAddress;                                                /*!< DMA Stream Base Address                       */
+
+ uint32_t                         StreamIndex;                                                      /*!< DMA Stream Index                              */
+
+ DMAMUX_Channel_TypeDef           *DMAmuxChannel;                                                   /*!< DMAMUX Channel Base Address                   */
+
+ DMAMUX_ChannelStatus_TypeDef     *DMAmuxChannelStatus;                                             /*!< DMAMUX Channels Status Base Address           */
+
+ uint32_t                         DMAmuxChannelStatusMask;                                          /*!< DMAMUX Channel Status Mask                    */
+
+
+ DMAMUX_RequestGen_TypeDef        *DMAmuxRequestGen;                                                /*!< DMAMUX request generator Base Address         */
+
+ DMAMUX_RequestGenStatus_TypeDef  *DMAmuxRequestGenStatus;                                          /*!< DMAMUX request generator Status Address       */
+
+ uint32_t                         DMAmuxRequestGenStatusMask;                                       /*!< DMAMUX request generator Status mask          */
+
+}DMA_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Constants DMA Exported Constants
+  * @brief    DMA Exported constants
+  * @{
+  */
+
+/** @defgroup DMA_Error_Code DMA Error Code
+  * @brief    DMA Error Code
+  * @{
+  */
+#define HAL_DMA_ERROR_NONE            (0x00000000U)    /*!< No error                                */
+#define HAL_DMA_ERROR_TE              (0x00000001U)    /*!< Transfer error                          */
+#define HAL_DMA_ERROR_FE              (0x00000002U)    /*!< FIFO error                              */
+#define HAL_DMA_ERROR_DME             (0x00000004U)    /*!< Direct Mode error                       */
+#define HAL_DMA_ERROR_TIMEOUT         (0x00000020U)    /*!< Timeout error                           */
+#define HAL_DMA_ERROR_PARAM           (0x00000040U)    /*!< Parameter error                         */
+#define HAL_DMA_ERROR_NO_XFER         (0x00000080U)    /*!< Abort requested with no Xfer ongoing    */
+#define HAL_DMA_ERROR_NOT_SUPPORTED   (0x00000100U)    /*!< Not supported mode                      */
+#define HAL_DMA_ERROR_SYNC            (0x00000200U)    /*!< DMAMUX sync overrun  error              */
+#define HAL_DMA_ERROR_REQGEN          (0x00000400U)    /*!< DMAMUX request generator overrun  error */
+#define HAL_DMA_ERROR_BUSY            (0x00000800U)    /*!< DMA Busy                          error */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Request_selection DMA Request selection
+  * @brief    DMA Request selection
+  * @{
+  */
+/* DMAMUX1 requests */
+#define DMA_REQUEST_MEM2MEM          0U  /*!< memory to memory transfer   */
+
+#define DMA_REQUEST_GENERATOR0       1U  /*!< DMAMUX1 request generator 0 */
+#define DMA_REQUEST_GENERATOR1       2U  /*!< DMAMUX1 request generator 1 */
+#define DMA_REQUEST_GENERATOR2       3U  /*!< DMAMUX1 request generator 2 */
+#define DMA_REQUEST_GENERATOR3       4U  /*!< DMAMUX1 request generator 3 */
+#define DMA_REQUEST_GENERATOR4       5U  /*!< DMAMUX1 request generator 4 */
+#define DMA_REQUEST_GENERATOR5       6U  /*!< DMAMUX1 request generator 5 */
+#define DMA_REQUEST_GENERATOR6       7U  /*!< DMAMUX1 request generator 6 */
+#define DMA_REQUEST_GENERATOR7       8U  /*!< DMAMUX1 request generator 7 */
+
+#define DMA_REQUEST_ADC1             9U  /*!< DMAMUX1 ADC1 request */
+#define DMA_REQUEST_ADC2             10U /*!< DMAMUX1 ADC2 request */
+
+#define DMA_REQUEST_TIM1_CH1         11U  /*!< DMAMUX1 TIM1 CH1 request  */
+#define DMA_REQUEST_TIM1_CH2         12U  /*!< DMAMUX1 TIM1 CH2 request  */
+#define DMA_REQUEST_TIM1_CH3         13U  /*!< DMAMUX1 TIM1 CH3 request  */
+#define DMA_REQUEST_TIM1_CH4         14U  /*!< DMAMUX1 TIM1 CH4 request  */
+#define DMA_REQUEST_TIM1_UP          15U  /*!< DMAMUX1 TIM1 UP request   */
+#define DMA_REQUEST_TIM1_TRIG        16U  /*!< DMAMUX1 TIM1 TRIG request */
+#define DMA_REQUEST_TIM1_COM         17U  /*!< DMAMUX1 TIM1 COM request  */
+
+#define DMA_REQUEST_TIM2_CH1         18U  /*!< DMAMUX1 TIM2 CH1 request  */
+#define DMA_REQUEST_TIM2_CH2         19U  /*!< DMAMUX1 TIM2 CH2 request  */
+#define DMA_REQUEST_TIM2_CH3         20U  /*!< DMAMUX1 TIM2 CH3 request  */
+#define DMA_REQUEST_TIM2_CH4         21U  /*!< DMAMUX1 TIM2 CH4 request  */
+#define DMA_REQUEST_TIM2_UP          22U  /*!< DMAMUX1 TIM2 UP request   */
+
+#define DMA_REQUEST_TIM3_CH1         23U  /*!< DMAMUX1 TIM3 CH1 request  */
+#define DMA_REQUEST_TIM3_CH2         24U  /*!< DMAMUX1 TIM3 CH2 request  */
+#define DMA_REQUEST_TIM3_CH3         25U  /*!< DMAMUX1 TIM3 CH3 request  */
+#define DMA_REQUEST_TIM3_CH4         26U  /*!< DMAMUX1 TIM3 CH4 request  */
+#define DMA_REQUEST_TIM3_UP          27U  /*!< DMAMUX1 TIM3 UP request   */
+#define DMA_REQUEST_TIM3_TRIG        28U  /*!< DMAMUX1 TIM3 TRIG request */
+
+#define DMA_REQUEST_TIM4_CH1         29U  /*!< DMAMUX1 TIM4 CH1 request  */
+#define DMA_REQUEST_TIM4_CH2         30U  /*!< DMAMUX1 TIM4 CH2 request  */
+#define DMA_REQUEST_TIM4_CH3         31U  /*!< DMAMUX1 TIM4 CH3 request  */
+#define DMA_REQUEST_TIM4_UP          32U  /*!< DMAMUX1 TIM4 UP request   */
+
+#define DMA_REQUEST_I2C1_RX          33U  /*!< DMAMUX1 I2C1 RX request   */
+#define DMA_REQUEST_I2C1_TX          34U  /*!< DMAMUX1 I2C1 TX request   */
+#define DMA_REQUEST_I2C2_RX          35U  /*!< DMAMUX1 I2C2 RX request   */
+#define DMA_REQUEST_I2C2_TX          36U  /*!< DMAMUX1 I2C2 TX request   */
+
+#define DMA_REQUEST_SPI1_RX          37U  /*!< DMAMUX1 SPI1 RX request   */
+#define DMA_REQUEST_SPI1_TX          38U  /*!< DMAMUX1 SPI1 TX request   */
+#define DMA_REQUEST_SPI2_RX          39U  /*!< DMAMUX1 SPI2 RX request   */
+#define DMA_REQUEST_SPI2_TX          40U  /*!< DMAMUX1 SPI2 TX request   */
+
+#define DMA_REQUEST_USART1_RX        41U  /*!< DMAMUX1 USART1 RX request */
+#define DMA_REQUEST_USART1_TX        42U  /*!< DMAMUX1 USART1 TX request */
+#define DMA_REQUEST_USART2_RX        43U  /*!< DMAMUX1 USART2 RX request */
+#define DMA_REQUEST_USART2_TX        44U  /*!< DMAMUX1 USART2 TX request */
+#define DMA_REQUEST_USART3_RX        45U  /*!< DMAMUX1 USART3 RX request */
+#define DMA_REQUEST_USART3_TX        46U  /*!< DMAMUX1 USART3 TX request */
+
+#define DMA_REQUEST_TIM8_CH1         47U  /*!< DMAMUX1 TIM8 CH1 request  */
+#define DMA_REQUEST_TIM8_CH2         48U  /*!< DMAMUX1 TIM8 CH2 request  */
+#define DMA_REQUEST_TIM8_CH3         49U  /*!< DMAMUX1 TIM8 CH3 request  */
+#define DMA_REQUEST_TIM8_CH4         50U  /*!< DMAMUX1 TIM8 CH4 request  */
+#define DMA_REQUEST_TIM8_UP          51U  /*!< DMAMUX1 TIM8 UP request   */
+#define DMA_REQUEST_TIM8_TRIG        52U  /*!< DMAMUX1 TIM8 TRIG request */
+#define DMA_REQUEST_TIM8_COM         53U  /*!< DMAMUX1 TIM8 COM request  */
+
+#define DMA_REQUEST_TIM5_CH1         55U  /*!< DMAMUX1 TIM5 CH1 request  */
+#define DMA_REQUEST_TIM5_CH2         56U  /*!< DMAMUX1 TIM5 CH2 request  */
+#define DMA_REQUEST_TIM5_CH3         57U  /*!< DMAMUX1 TIM5 CH3 request  */
+#define DMA_REQUEST_TIM5_CH4         58U  /*!< DMAMUX1 TIM5 CH4 request  */
+#define DMA_REQUEST_TIM5_UP          59U  /*!< DMAMUX1 TIM5 UP request   */
+#define DMA_REQUEST_TIM5_TRIG        60U  /*!< DMAMUX1 TIM5 TRIG request */
+
+#define DMA_REQUEST_SPI3_RX          61U  /*!< DMAMUX1 SPI3 RX request   */
+#define DMA_REQUEST_SPI3_TX          62U  /*!< DMAMUX1 SPI3 TX request   */
+
+#define DMA_REQUEST_UART4_RX         63U  /*!< DMAMUX1 UART4 RX request */
+#define DMA_REQUEST_UART4_TX         64U  /*!< DMAMUX1 UART4 TX request */
+#define DMA_REQUEST_UART5_RX         65U  /*!< DMAMUX1 UART5 RX request */
+#define DMA_REQUEST_UART5_TX         66U  /*!< DMAMUX1 UART5 TX request */
+
+#define DMA_REQUEST_DAC1_CH1         67U  /*!< DMAMUX1 DAC1 Channel 1 request */
+#define DMA_REQUEST_DAC1_CH2         68U  /*!< DMAMUX1 DAC1 Channel 2 request */
+
+#define DMA_REQUEST_TIM6_UP          69U  /*!< DMAMUX1 TIM6 UP request   */
+#define DMA_REQUEST_TIM7_UP          70U  /*!< DMAMUX1 TIM7 UP request   */
+
+#define DMA_REQUEST_USART6_RX        71U  /*!< DMAMUX1 USART6 RX request */
+#define DMA_REQUEST_USART6_TX        72U  /*!< DMAMUX1 USART6 TX request */
+
+#define DMA_REQUEST_I2C3_RX          73U  /*!< DMAMUX1 I2C3 RX request   */
+#define DMA_REQUEST_I2C3_TX          74U  /*!< DMAMUX1 I2C3 TX request   */
+
+#if defined (PSSI)
+#define DMA_REQUEST_DCMI_PSSI        75U  /*!< DMAMUX1 DCMI/PSSI request    */
+#define DMA_REQUEST_DCMI             DMA_REQUEST_DCMI_PSSI /* Legacy define */
+#else
+#define DMA_REQUEST_DCMI             75U  /*!< DMAMUX1 DCMI request         */
+#endif /* PSSI */
+
+#define DMA_REQUEST_CRYP_IN          76U  /*!< DMAMUX1 CRYP IN request   */
+#define DMA_REQUEST_CRYP_OUT         77U  /*!< DMAMUX1 CRYP OUT request  */
+
+#define DMA_REQUEST_HASH_IN          78U  /*!< DMAMUX1 HASH IN request   */
+
+#define DMA_REQUEST_UART7_RX         79U  /*!< DMAMUX1 UART7 RX request  */
+#define DMA_REQUEST_UART7_TX         80U  /*!< DMAMUX1 UART7 TX request  */
+#define DMA_REQUEST_UART8_RX         81U  /*!< DMAMUX1 UART8 RX request  */
+#define DMA_REQUEST_UART8_TX         82U  /*!< DMAMUX1 UART8 TX request  */
+
+#define DMA_REQUEST_SPI4_RX          83U  /*!< DMAMUX1 SPI4 RX request   */
+#define DMA_REQUEST_SPI4_TX          84U  /*!< DMAMUX1 SPI4 TX request   */
+#define DMA_REQUEST_SPI5_RX          85U  /*!< DMAMUX1 SPI5 RX request   */
+#define DMA_REQUEST_SPI5_TX          86U  /*!< DMAMUX1 SPI5 TX request   */
+
+#define DMA_REQUEST_SAI1_A           87U  /*!< DMAMUX1 SAI1 A request    */
+#define DMA_REQUEST_SAI1_B           88U  /*!< DMAMUX1 SAI1 B request    */
+#define DMA_REQUEST_SAI2_A           89U  /*!< DMAMUX1 SAI2 A request    */
+#define DMA_REQUEST_SAI2_B           90U  /*!< DMAMUX1 SAI2 B request    */
+
+#define DMA_REQUEST_SWPMI_RX         91U  /*!< DMAMUX1 SWPMI RX request  */
+#define DMA_REQUEST_SWPMI_TX         92U  /*!< DMAMUX1 SWPMI TX request  */
+
+#define DMA_REQUEST_SPDIF_RX_DT      93U  /*!< DMAMUX1 SPDIF RXDT request*/
+#define DMA_REQUEST_SPDIF_RX_CS      94U  /*!< DMAMUX1 SPDIF RXCS request*/
+
+#if defined(HRTIM1)
+#define DMA_REQUEST_HRTIM_MASTER     95U  /*!< DMAMUX1 HRTIM1 Master request 1 */
+#define DMA_REQUEST_HRTIM_TIMER_A    96U  /*!< DMAMUX1 HRTIM1 TimerA request 2 */
+#define DMA_REQUEST_HRTIM_TIMER_B    97U  /*!< DMAMUX1 HRTIM1 TimerB request 3 */
+#define DMA_REQUEST_HRTIM_TIMER_C    98U  /*!< DMAMUX1 HRTIM1 TimerC request 4 */
+#define DMA_REQUEST_HRTIM_TIMER_D    99U  /*!< DMAMUX1 HRTIM1 TimerD request 5 */
+#define DMA_REQUEST_HRTIM_TIMER_E   100U  /*!< DMAMUX1 HRTIM1 TimerE request 6 */
+#endif /* HRTIM1 */
+
+#define DMA_REQUEST_DFSDM1_FLT0     101U  /*!< DMAMUX1 DFSDM Filter0 request */
+#define DMA_REQUEST_DFSDM1_FLT1     102U  /*!< DMAMUX1 DFSDM Filter1 request */
+#define DMA_REQUEST_DFSDM1_FLT2     103U  /*!< DMAMUX1 DFSDM Filter2 request */
+#define DMA_REQUEST_DFSDM1_FLT3     104U  /*!< DMAMUX1 DFSDM Filter3 request */
+
+#define DMA_REQUEST_TIM15_CH1       105U  /*!< DMAMUX1 TIM15 CH1 request  */
+#define DMA_REQUEST_TIM15_UP        106U  /*!< DMAMUX1 TIM15 UP request   */
+#define DMA_REQUEST_TIM15_TRIG      107U  /*!< DMAMUX1 TIM15 TRIG request */
+#define DMA_REQUEST_TIM15_COM       108U  /*!< DMAMUX1 TIM15 COM request  */
+
+#define DMA_REQUEST_TIM16_CH1       109U  /*!< DMAMUX1 TIM16 CH1 request  */
+#define DMA_REQUEST_TIM16_UP        110U  /*!< DMAMUX1 TIM16 UP request   */
+
+#define DMA_REQUEST_TIM17_CH1       111U  /*!< DMAMUX1 TIM17 CH1 request  */
+#define DMA_REQUEST_TIM17_UP        112U  /*!< DMAMUX1 TIM17 UP request   */
+
+#if defined(SAI3)
+#define DMA_REQUEST_SAI3_A          113U  /*!< DMAMUX1 SAI3 A request  */
+#define DMA_REQUEST_SAI3_B          114U  /*!< DMAMUX1 SAI3 B request  */
+#endif /* SAI3 */
+
+#if defined(ADC3)
+#define DMA_REQUEST_ADC3            115U  /*!< DMAMUX1 ADC3 request  */
+#endif /* ADC3 */
+
+#if defined(UART9)
+#define DMA_REQUEST_UART9_RX        116U  /*!< DMAMUX1 UART9 request  */
+#define DMA_REQUEST_UART9_TX        117U  /*!< DMAMUX1 UART9 request  */
+#endif /* UART9 */
+
+#if defined(USART10)
+#define DMA_REQUEST_USART10_RX      118U  /*!< DMAMUX1 USART10 request  */
+#define DMA_REQUEST_USART10_TX      119U  /*!< DMAMUX1 USART10 request  */
+#endif /* USART10 */
+
+
+/* DMAMUX2 requests */
+#define BDMA_REQUEST_MEM2MEM          0U  /*!< memory to memory transfer   */
+#define BDMA_REQUEST_GENERATOR0       1U  /*!< DMAMUX2 request generator 0 */
+#define BDMA_REQUEST_GENERATOR1       2U  /*!< DMAMUX2 request generator 1 */
+#define BDMA_REQUEST_GENERATOR2       3U  /*!< DMAMUX2 request generator 2 */
+#define BDMA_REQUEST_GENERATOR3       4U  /*!< DMAMUX2 request generator 3 */
+#define BDMA_REQUEST_GENERATOR4       5U  /*!< DMAMUX2 request generator 4 */
+#define BDMA_REQUEST_GENERATOR5       6U  /*!< DMAMUX2 request generator 5 */
+#define BDMA_REQUEST_GENERATOR6       7U  /*!< DMAMUX2 request generator 6 */
+#define BDMA_REQUEST_GENERATOR7       8U  /*!< DMAMUX2 request generator 7 */
+#define BDMA_REQUEST_LPUART1_RX       9U  /*!< DMAMUX2 LP_UART1_RX request */
+#define BDMA_REQUEST_LPUART1_TX      10U  /*!< DMAMUX2 LP_UART1_TX request */
+#define BDMA_REQUEST_SPI6_RX         11U  /*!< DMAMUX2 SPI6 RX request     */
+#define BDMA_REQUEST_SPI6_TX         12U  /*!< DMAMUX2 SPI6 TX request     */
+#define BDMA_REQUEST_I2C4_RX         13U  /*!< DMAMUX2 I2C4 RX request     */
+#define BDMA_REQUEST_I2C4_TX         14U  /*!< DMAMUX2 I2C4 TX request     */
+#if defined(SAI4)
+#define BDMA_REQUEST_SAI4_A          15U  /*!< DMAMUX2 SAI4 A request      */
+#define BDMA_REQUEST_SAI4_B          16U  /*!< DMAMUX2 SAI4 B request      */
+#endif /* SAI4 */
+#if defined(ADC3)
+#define BDMA_REQUEST_ADC3            17U  /*!< DMAMUX2 ADC3 request        */
+#endif /* ADC3 */
+#if defined(DAC2)
+#define BDMA_REQUEST_DAC2_CH1        17U  /*!< DMAMUX2 DAC2 CH1 request    */
+#endif /* DAC2 */
+#if defined(DFSDM2_Channel0)
+#define BDMA_REQUEST_DFSDM2_FLT0     18U  /*!< DMAMUX2 DFSDM2 request      */
+#endif /* DFSDM1_Channel0 */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
+  * @brief    DMA data transfer direction
+  * @{
+  */
+#define DMA_PERIPH_TO_MEMORY         ((uint32_t)0x00000000U)      /*!< Peripheral to memory direction */
+#define DMA_MEMORY_TO_PERIPH         ((uint32_t)DMA_SxCR_DIR_0)  /*!< Memory to peripheral direction */
+#define DMA_MEMORY_TO_MEMORY         ((uint32_t)DMA_SxCR_DIR_1)  /*!< Memory to memory direction     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
+  * @brief    DMA peripheral incremented mode
+  * @{
+  */
+#define DMA_PINC_ENABLE        ((uint32_t)DMA_SxCR_PINC)  /*!< Peripheral increment mode enable  */
+#define DMA_PINC_DISABLE       ((uint32_t)0x00000000U)     /*!< Peripheral increment mode disable */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
+  * @brief    DMA memory incremented mode
+  * @{
+  */
+#define DMA_MINC_ENABLE         ((uint32_t)DMA_SxCR_MINC)  /*!< Memory increment mode enable  */
+#define DMA_MINC_DISABLE        ((uint32_t)0x00000000U)     /*!< Memory increment mode disable */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
+  * @brief    DMA peripheral data size
+  * @{
+  */
+#define DMA_PDATAALIGN_BYTE          ((uint32_t)0x00000000U)       /*!< Peripheral data alignment: Byte      */
+#define DMA_PDATAALIGN_HALFWORD      ((uint32_t)DMA_SxCR_PSIZE_0)  /*!< Peripheral data alignment: HalfWord  */
+#define DMA_PDATAALIGN_WORD          ((uint32_t)DMA_SxCR_PSIZE_1)  /*!< Peripheral data alignment: Word      */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Memory_data_size DMA Memory data size
+  * @brief    DMA memory data size
+  * @{
+  */
+#define DMA_MDATAALIGN_BYTE          ((uint32_t)0x00000000U)       /*!< Memory data alignment: Byte     */
+#define DMA_MDATAALIGN_HALFWORD      ((uint32_t)DMA_SxCR_MSIZE_0)  /*!< Memory data alignment: HalfWord */
+#define DMA_MDATAALIGN_WORD          ((uint32_t)DMA_SxCR_MSIZE_1)  /*!< Memory data alignment: Word     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_mode DMA mode
+  * @brief    DMA mode
+  * @{
+  */
+#define DMA_NORMAL              ((uint32_t)0x00000000U)                  /*!< Normal mode                                    */
+#define DMA_CIRCULAR            ((uint32_t)DMA_SxCR_CIRC)                /*!< Circular mode                                  */
+#define DMA_PFCTRL              ((uint32_t)DMA_SxCR_PFCTRL)              /*!< Peripheral flow control mode                   */
+#define DMA_DOUBLE_BUFFER_M0    ((uint32_t)DMA_SxCR_DBM)                 /*!< Double buffer mode with first target memory M0 */
+#define DMA_DOUBLE_BUFFER_M1    ((uint32_t)(DMA_SxCR_DBM | DMA_SxCR_CT)) /*!< Double buffer mode with first target memory M1 */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Priority_level DMA Priority level
+  * @brief    DMA priority levels
+  * @{
+  */
+#define DMA_PRIORITY_LOW             ((uint32_t)0x00000000U)    /*!< Priority level: Low       */
+#define DMA_PRIORITY_MEDIUM          ((uint32_t)DMA_SxCR_PL_0)  /*!< Priority level: Medium    */
+#define DMA_PRIORITY_HIGH            ((uint32_t)DMA_SxCR_PL_1)  /*!< Priority level: High      */
+#define DMA_PRIORITY_VERY_HIGH       ((uint32_t)DMA_SxCR_PL)    /*!< Priority level: Very High */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
+  * @brief    DMA FIFO direct mode
+  * @{
+  */
+#define DMA_FIFOMODE_DISABLE        ((uint32_t)0x00000000U)       /*!< FIFO mode disable */
+#define DMA_FIFOMODE_ENABLE         ((uint32_t)DMA_SxFCR_DMDIS)  /*!< FIFO mode enable  */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
+  * @brief    DMA FIFO level
+  * @{
+  */
+#define DMA_FIFO_THRESHOLD_1QUARTERFULL       ((uint32_t)0x00000000U)       /*!< FIFO threshold 1 quart full configuration  */
+#define DMA_FIFO_THRESHOLD_HALFFULL           ((uint32_t)DMA_SxFCR_FTH_0)  /*!< FIFO threshold half full configuration     */
+#define DMA_FIFO_THRESHOLD_3QUARTERSFULL      ((uint32_t)DMA_SxFCR_FTH_1)  /*!< FIFO threshold 3 quarts full configuration */
+#define DMA_FIFO_THRESHOLD_FULL               ((uint32_t)DMA_SxFCR_FTH)    /*!< FIFO threshold full configuration          */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Memory_burst DMA Memory burst
+  * @brief    DMA memory burst
+  * @{
+  */
+#define DMA_MBURST_SINGLE       ((uint32_t)0x00000000U)
+#define DMA_MBURST_INC4         ((uint32_t)DMA_SxCR_MBURST_0)
+#define DMA_MBURST_INC8         ((uint32_t)DMA_SxCR_MBURST_1)
+#define DMA_MBURST_INC16        ((uint32_t)DMA_SxCR_MBURST)
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Peripheral_burst DMA Peripheral burst
+  * @brief    DMA peripheral burst
+  * @{
+  */
+#define DMA_PBURST_SINGLE       ((uint32_t)0x00000000U)
+#define DMA_PBURST_INC4         ((uint32_t)DMA_SxCR_PBURST_0)
+#define DMA_PBURST_INC8         ((uint32_t)DMA_SxCR_PBURST_1)
+#define DMA_PBURST_INC16        ((uint32_t)DMA_SxCR_PBURST)
+/**
+  * @}
+  */
+
+/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
+  * @brief    DMA interrupts definition
+  * @{
+  */
+#define DMA_IT_TC                         ((uint32_t)DMA_SxCR_TCIE)
+#define DMA_IT_HT                         ((uint32_t)DMA_SxCR_HTIE)
+#define DMA_IT_TE                         ((uint32_t)DMA_SxCR_TEIE)
+#define DMA_IT_DME                        ((uint32_t)DMA_SxCR_DMEIE)
+#define DMA_IT_FE                         ((uint32_t)0x00000080U)
+/**
+  * @}
+  */
+
+/** @defgroup DMA_flag_definitions DMA flag definitions
+  * @brief    DMA flag definitions
+  * @{
+  */
+#define DMA_FLAG_FEIF0_4                    ((uint32_t)0x00000001U)
+#define DMA_FLAG_DMEIF0_4                   ((uint32_t)0x00000004U)
+#define DMA_FLAG_TEIF0_4                    ((uint32_t)0x00000008U)
+#define DMA_FLAG_HTIF0_4                    ((uint32_t)0x00000010U)
+#define DMA_FLAG_TCIF0_4                    ((uint32_t)0x00000020U)
+#define DMA_FLAG_FEIF1_5                    ((uint32_t)0x00000040U)
+#define DMA_FLAG_DMEIF1_5                   ((uint32_t)0x00000100U)
+#define DMA_FLAG_TEIF1_5                    ((uint32_t)0x00000200U)
+#define DMA_FLAG_HTIF1_5                    ((uint32_t)0x00000400U)
+#define DMA_FLAG_TCIF1_5                    ((uint32_t)0x00000800U)
+#define DMA_FLAG_FEIF2_6                    ((uint32_t)0x00010000U)
+#define DMA_FLAG_DMEIF2_6                   ((uint32_t)0x00040000U)
+#define DMA_FLAG_TEIF2_6                    ((uint32_t)0x00080000U)
+#define DMA_FLAG_HTIF2_6                    ((uint32_t)0x00100000U)
+#define DMA_FLAG_TCIF2_6                    ((uint32_t)0x00200000U)
+#define DMA_FLAG_FEIF3_7                    ((uint32_t)0x00400000U)
+#define DMA_FLAG_DMEIF3_7                   ((uint32_t)0x01000000U)
+#define DMA_FLAG_TEIF3_7                    ((uint32_t)0x02000000U)
+#define DMA_FLAG_HTIF3_7                    ((uint32_t)0x04000000U)
+#define DMA_FLAG_TCIF3_7                    ((uint32_t)0x08000000U)
+/**
+  * @}
+  */
+
+/** @defgroup BDMA_flag_definitions BDMA flag definitions
+  * @brief    BDMA flag definitions
+  * @{
+  */
+#define BDMA_FLAG_GL0                      ((uint32_t)0x00000001)
+#define BDMA_FLAG_TC0                      ((uint32_t)0x00000002)
+#define BDMA_FLAG_HT0                      ((uint32_t)0x00000004)
+#define BDMA_FLAG_TE0                      ((uint32_t)0x00000008)
+#define BDMA_FLAG_GL1                      ((uint32_t)0x00000010)
+#define BDMA_FLAG_TC1                      ((uint32_t)0x00000020)
+#define BDMA_FLAG_HT1                      ((uint32_t)0x00000040)
+#define BDMA_FLAG_TE1                      ((uint32_t)0x00000080)
+#define BDMA_FLAG_GL2                      ((uint32_t)0x00000100)
+#define BDMA_FLAG_TC2                      ((uint32_t)0x00000200)
+#define BDMA_FLAG_HT2                      ((uint32_t)0x00000400)
+#define BDMA_FLAG_TE2                      ((uint32_t)0x00000800)
+#define BDMA_FLAG_GL3                      ((uint32_t)0x00001000)
+#define BDMA_FLAG_TC3                      ((uint32_t)0x00002000)
+#define BDMA_FLAG_HT3                      ((uint32_t)0x00004000)
+#define BDMA_FLAG_TE3                      ((uint32_t)0x00008000)
+#define BDMA_FLAG_GL4                      ((uint32_t)0x00010000)
+#define BDMA_FLAG_TC4                      ((uint32_t)0x00020000)
+#define BDMA_FLAG_HT4                      ((uint32_t)0x00040000)
+#define BDMA_FLAG_TE4                      ((uint32_t)0x00080000)
+#define BDMA_FLAG_GL5                      ((uint32_t)0x00100000)
+#define BDMA_FLAG_TC5                      ((uint32_t)0x00200000)
+#define BDMA_FLAG_HT5                      ((uint32_t)0x00400000)
+#define BDMA_FLAG_TE5                      ((uint32_t)0x00800000)
+#define BDMA_FLAG_GL6                      ((uint32_t)0x01000000)
+#define BDMA_FLAG_TC6                      ((uint32_t)0x02000000)
+#define BDMA_FLAG_HT6                      ((uint32_t)0x04000000)
+#define BDMA_FLAG_TE6                      ((uint32_t)0x08000000)
+#define BDMA_FLAG_GL7                      ((uint32_t)0x10000000)
+#define BDMA_FLAG_TC7                      ((uint32_t)0x20000000)
+#define BDMA_FLAG_HT7                      ((uint32_t)0x40000000)
+#define BDMA_FLAG_TE7                      ((uint32_t)0x80000000)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DMA_Exported_Macros DMA Exported Macros
+  * @{
+  */
+
+/** @brief Reset DMA handle state
+  * @param  __HANDLE__: specifies the DMA handle.
+  * @retval None
+  */
+#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
+
+/**
+  * @brief  Return the current DMA Stream FIFO filled level.
+  * @param  __HANDLE__: DMA handle
+  * @retval The FIFO filling state.
+  *           - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
+  *                                              and not empty.
+  *           - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
+  *           - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
+  *           - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
+  *           - DMA_FIFOStatus_Empty: when FIFO is empty
+  *           - DMA_FIFOStatus_Full: when FIFO is full
+  */
+#define __HAL_DMA_GET_FS(__HANDLE__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (DMA_SxFCR_FS)) : 0)
+
+/**
+  * @brief  Enable the specified DMA Stream.
+  * @param  __HANDLE__: DMA handle
+  * @retval None
+  */
+#define __HAL_DMA_ENABLE(__HANDLE__) \
+((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |=  DMA_SxCR_EN) : \
+(((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |=  BDMA_CCR_EN))
+
+/**
+  * @brief  Disable the specified DMA Stream.
+  * @param  __HANDLE__: DMA handle
+  * @retval None
+  */
+#define __HAL_DMA_DISABLE(__HANDLE__) \
+((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &=  ~DMA_SxCR_EN) : \
+(((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &=  ~BDMA_CCR_EN))
+
+/* Interrupt & Flag management */
+
+/**
+  * @brief  Return the current DMA Stream transfer complete flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified transfer complete flag index.
+  */
+#if defined(BDMA1)
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TCIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TCIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TCIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TCIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_TC0  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_TC0  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_TC1  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_TC1  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_TC2  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_TC2  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_TC3  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_TC3  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_TC4  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_TC4  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_TC5  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_TC5  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_TC6  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_TC6  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_TC7  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_TC7  :\
+ (uint32_t)0x00000000)
+#else
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TCIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TCIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TCIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TCIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_TC0   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_TC1   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_TC2   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_TC3   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_TC4   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_TC5   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TC6   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TC7   :\
+ (uint32_t)0x00000000)
+#endif /* BDMA1 */
+
+/**
+  * @brief  Return the current DMA Stream half transfer complete flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified half transfer complete flag index.
+  */
+#if defined(BDMA1)
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_HTIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_HTIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_HTIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_HTIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_HT0  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_HT0  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_HT1  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_HT1  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_HT2  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_HT2  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_HT3  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_HT3  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_HT4  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_HT4  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_HT5  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_HT5  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_HT6  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_HT6  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_HT7  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_HT7  :\
+ (uint32_t)0x00000000)
+#else
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_HTIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_HTIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_HTIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_HTIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_HT0   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_HT1   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_HT2   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_HT3   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_HT4   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_HT5   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_HT6   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_HT7   :\
+ (uint32_t)0x00000000)
+#endif /* BDMA1 */
+
+/**
+  * @brief  Return the current DMA Stream transfer error flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified transfer error flag index.
+  */
+#if defined(BDMA1)
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_TE0  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_TE0  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_TE1  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_TE1  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_TE2  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_TE2  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_TE3  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_TE3  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_TE4  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_TE4  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_TE5  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_TE5  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_TE6  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_TE6  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_TE7  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_TE7  :\
+ (uint32_t)0x00000000)
+#else
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_TE0   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_TE1   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_TE2   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_TE3   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_TE4   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_TE5   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TE6   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TE7   :\
+ (uint32_t)0x00000000)
+#endif /* BDMA1 */
+
+/**
+  * @brief  Return the current DMA Stream FIFO error flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified FIFO error flag index.
+  */
+#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_FEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_FEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_FEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_FEIF3_7 :\
+  (uint32_t)0x00000000)
+
+/**
+  * @brief  Return the current DMA Stream direct mode error flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified direct mode error flag index.
+  */
+#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_DMEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_DMEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_DMEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_DMEIF3_7 :\
+  (uint32_t)0x00000000)
+
+/**
+  * @brief  Returns the current BDMA Channel Global interrupt flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified transfer error flag index.
+  */
+#if defined(BDMA1)
+#define __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_ISR_GIF0 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_ISR_GIF0 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_ISR_GIF1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_ISR_GIF1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_ISR_GIF2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_ISR_GIF2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_ISR_GIF3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_ISR_GIF3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_ISR_GIF4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_ISR_GIF4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_ISR_GIF5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_ISR_GIF5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_ISR_GIF6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_ISR_GIF6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_ISR_GIF7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_ISR_GIF7 :\
+ (uint32_t)0x00000000)
+#else
+#define __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_ISR_GIF0 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_ISR_GIF1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_ISR_GIF2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_ISR_GIF3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_ISR_GIF4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_ISR_GIF5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_ISR_GIF6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_ISR_GIF7 :\
+  (uint32_t)0x00000000)
+#endif /* BDMA1 */
+
+/**
+  * @brief  Get the DMA Stream pending flags.
+  * @param  __HANDLE__: DMA handle
+  * @param  __FLAG__: Get the specified flag.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
+  *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
+  *            @arg DMA_FLAG_TEIFx: Transfer error flag.
+  *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.
+  *            @arg DMA_FLAG_FEIFx: FIFO error flag.
+  *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
+  * @retval The state of FLAG (SET or RESET).
+  */
+#if defined(BDMA1)
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)BDMA1_Channel7)?  (BDMA2->ISR & (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7  )?  (BDMA1->ISR & (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3  )?  (DMA2->HISR & (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7  )?  (DMA2->LISR & (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3  )?  (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
+#else
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->ISR & (__FLAG__))  :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
+#endif /* BDMA1 */
+
+/**
+  * @brief  Clear the DMA Stream pending flags.
+  * @param  __HANDLE__: DMA handle
+  * @param  __FLAG__: specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
+  *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
+  *            @arg DMA_FLAG_TEIFx: Transfer error flag.
+  *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.
+  *            @arg DMA_FLAG_FEIFx: FIFO error flag.
+  *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
+  * @retval None
+  */
+#if defined(BDMA1)
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)BDMA1_Channel7)? (BDMA2->IFCR = (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)?  (BDMA1->IFCR = (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)?  (DMA2->HIFCR = (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)?  (DMA2->LIFCR = (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)?  (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
+#else
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->IFCR = (__FLAG__))  :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
+#endif /* BDMA1 */
+
+#define DMA_TO_BDMA_IT(__DMA_IT__) \
+((((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE |BDMA_CCR_TEIE) :\
+ (((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT)) == (DMA_IT_TC | DMA_IT_HT)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE) :\
+ (((__DMA_IT__) & (DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_HTIE |BDMA_CCR_TEIE)  :\
+ (((__DMA_IT__) & (DMA_IT_TC | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_TE)) ? (BDMA_CCR_TCIE |BDMA_CCR_TEIE)  :\
+ ((__DMA_IT__) == DMA_IT_TC) ? BDMA_CCR_TCIE :\
+ ((__DMA_IT__) == DMA_IT_HT) ? BDMA_CCR_HTIE :\
+ ((__DMA_IT__) == DMA_IT_TE) ? BDMA_CCR_TEIE :\
+ (uint32_t)0x00000000)
+
+
+#define __HAL_BDMA_CHANNEL_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
+(((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |= (DMA_TO_BDMA_IT(__INTERRUPT__)))
+
+#define __HAL_DMA_STREAM_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((__INTERRUPT__) != DMA_IT_FE)? \
+(((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |= (__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR |= (__INTERRUPT__)))
+
+/**
+  * @brief  Enable the specified DMA Stream interrupts.
+  * @param  __HANDLE__: DMA handle
+  * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+  *        This parameter can be one of the following values:
+  *           @arg DMA_IT_TC: Transfer complete interrupt mask.
+  *           @arg DMA_IT_HT: Half transfer complete interrupt mask.
+  *           @arg DMA_IT_TE: Transfer error interrupt mask.
+  *           @arg DMA_IT_FE: FIFO error interrupt mask.
+  *           @arg DMA_IT_DME: Direct mode error interrupt.
+  * @retval None
+  */
+#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))?\
+                                                        (__HAL_DMA_STREAM_ENABLE_IT((__HANDLE__), (__INTERRUPT__))) :\
+                                                        (__HAL_BDMA_CHANNEL_ENABLE_IT((__HANDLE__), (__INTERRUPT__))))
+
+
+#define __HAL_BDMA_CHANNEL_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &= ~(DMA_TO_BDMA_IT(__INTERRUPT__)))
+
+#define __HAL_DMA_STREAM_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \
+(((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &= ~(__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR &= ~(__INTERRUPT__)))
+
+/**
+  * @brief  Disable the specified DMA Stream interrupts.
+  * @param  __HANDLE__: DMA handle
+  * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+  *         This parameter can be one of the following values:
+  *            @arg DMA_IT_TC: Transfer complete interrupt mask.
+  *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
+  *            @arg DMA_IT_TE: Transfer error interrupt mask.
+  *            @arg DMA_IT_FE: FIFO error interrupt mask.
+  *            @arg DMA_IT_DME: Direct mode error interrupt.
+  * @retval None
+  */
+#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))?\
+                                                         (__HAL_DMA_STREAM_DISABLE_IT((__HANDLE__), (__INTERRUPT__))) :\
+                                                         (__HAL_BDMA_CHANNEL_DISABLE_IT((__HANDLE__), (__INTERRUPT__))))
+
+
+#define __HAL_BDMA_CHANNEL_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  ((((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR & (DMA_TO_BDMA_IT(__INTERRUPT__))))
+
+#define __HAL_DMA_STREAM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \
+                                                        (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR & (__INTERRUPT__)) : \
+                                                        (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (__INTERRUPT__)))
+
+/**
+  * @brief  Check whether the specified DMA Stream interrupt is enabled or not.
+  * @param  __HANDLE__: DMA handle
+  * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
+  *         This parameter can be one of the following values:
+  *            @arg DMA_IT_TC: Transfer complete interrupt mask.
+  *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
+  *            @arg DMA_IT_TE: Transfer error interrupt mask.
+  *            @arg DMA_IT_FE: FIFO error interrupt mask.
+  *            @arg DMA_IT_DME: Direct mode error interrupt.
+  * @retval The state of DMA_IT.
+  */
+#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \
+                                                            (__HAL_DMA_STREAM_GET_IT_SOURCE((__HANDLE__), (__INTERRUPT__))) :\
+                                                            (__HAL_BDMA_CHANNEL_GET_IT_SOURCE((__HANDLE__), (__INTERRUPT__))))
+
+/**
+  * @brief  Writes the number of data units to be transferred on the DMA Stream.
+  * @param  __HANDLE__: DMA handle
+  * @param  __COUNTER__: Number of data units to be transferred (from 0 to 65535)
+  *          Number of data items depends only on the Peripheral data format.
+  *
+  * @note   If Peripheral data format is Bytes: number of data units is equal
+  *         to total number of bytes to be transferred.
+  *
+  * @note   If Peripheral data format is Half-Word: number of data units is
+  *         equal to total number of bytes to be transferred / 2.
+  *
+  * @note   If Peripheral data format is Word: number of data units is equal
+  *         to total  number of bytes to be transferred / 4.
+  *
+  * @retval The number of remaining data units in the current DMAy Streamx transfer.
+  */
+#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \
+                                                        (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR = (uint16_t)(__COUNTER__)) :\
+                                                        (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CNDTR = (uint16_t)(__COUNTER__)))
+
+/**
+  * @brief  Returns the number of remaining data units in the current DMAy Streamx transfer.
+  * @param  __HANDLE__: DMA handle
+  *
+  * @retval The number of remaining data units in the current DMA Stream transfer.
+  */
+#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \
+                                           (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR) :\
+                                           (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CNDTR))
+
+/**
+  * @}
+  */
+
+/* Include DMA HAL Extension module */
+#include "stm32h7xx_hal_dma_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Functions DMA Exported Functions
+  * @brief    DMA Exported functions
+  * @{
+  */
+
+/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief   Initialization and de-initialization functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
+  * @brief   I/O operation functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
+void              HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
+  * @brief    Peripheral State functions
+  * @{
+  */
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
+uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+/* Private Constants -------------------------------------------------------------*/
+/** @defgroup DMA_Private_Constants DMA Private Constants
+  * @brief    DMA private defines and constants
+  * @{
+  */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DMA_Private_Macros DMA Private Macros
+  * @brief    DMA private macros
+  * @{
+  */
+
+#if defined(ADC3)
+#define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_ADC3))
+#else
+#define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_USART10_TX))
+#endif /* ADC3 */
+
+#if defined(ADC3)
+#define IS_BDMA_REQUEST(REQUEST) (((REQUEST) <= BDMA_REQUEST_ADC3))
+#else
+#define IS_BDMA_REQUEST(REQUEST) (((REQUEST) <= BDMA_REQUEST_DFSDM2_FLT0))
+#endif /* ADC3 */
+
+#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
+                                     ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
+                                     ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
+
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
+
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
+                                            ((STATE) == DMA_PINC_DISABLE))
+
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
+                                        ((STATE) == DMA_MINC_DISABLE))
+
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
+                                           ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
+                                           ((SIZE) == DMA_PDATAALIGN_WORD))
+
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
+                                       ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
+                                       ((SIZE) == DMA_MDATAALIGN_WORD ))
+
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )           || \
+                           ((MODE) == DMA_CIRCULAR)          || \
+                           ((MODE) == DMA_PFCTRL)            || \
+                           ((MODE) == DMA_DOUBLE_BUFFER_M0)  || \
+                           ((MODE) == DMA_DOUBLE_BUFFER_M1))
+
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
+                                   ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
+                                   ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
+                                   ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
+
+#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
+                                       ((STATE) == DMA_FIFOMODE_ENABLE))
+
+#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
+                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL)      || \
+                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
+                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
+
+#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
+                                    ((BURST) == DMA_MBURST_INC4)   || \
+                                    ((BURST) == DMA_MBURST_INC8)   || \
+                                    ((BURST) == DMA_MBURST_INC16))
+
+#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
+                                        ((BURST) == DMA_PBURST_INC4)   || \
+                                        ((BURST) == DMA_PBURST_INC8)   || \
+                                        ((BURST) == DMA_PBURST_INC16))
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DMA_Private_Functions DMA Private Functions
+  * @brief    DMA private  functions
+  * @{
+  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h
new file mode 100644
index 00000000..4125ae7e
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h
@@ -0,0 +1,312 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_dma_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMA HAL extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_DMA_EX_H
+#define STM32H7xx_HAL_DMA_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DMAEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DMAEx_Exported_Types DMAEx Exported Types
+  * @brief DMAEx Exported types
+  * @{
+  */
+
+/**
+  * @brief  HAL DMA Memory definition
+  */
+typedef enum
+{
+  MEMORY0      = 0x00U,    /*!< Memory 0     */
+  MEMORY1      = 0x01U,    /*!< Memory 1     */
+
+}HAL_DMA_MemoryTypeDef;
+
+/**
+  * @brief  HAL DMAMUX Synchronization configuration structure definition
+  */
+typedef struct
+{
+  uint32_t SyncSignalID;  /*!< Specifies the synchronization signal gating the DMA request in periodic mode.
+                              This parameter can be a value of @ref DMAEx_MUX_SyncSignalID_selection */
+
+  uint32_t SyncPolarity;  /*!< Specifies the polarity of the signal on which the DMA request is synchronized.
+                              This parameter can be a value of @ref DMAEx_MUX_SyncPolarity_selection */
+
+  FunctionalState SyncEnable;  /*!< Specifies if the synchronization shall be enabled or disabled
+                                    This parameter can take the value ENABLE or DISABLE*/
+
+
+  FunctionalState EventEnable;    /*!< Specifies if an event shall be generated once the RequestNumber is reached.
+                                       This parameter can take the value ENABLE or DISABLE */
+
+  uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be authorized after a sync event.
+                               This parameters can be in the range 1 to 32 */
+
+}HAL_DMA_MuxSyncConfigTypeDef;
+
+
+/**
+  * @brief  HAL DMAMUX request generator parameters structure definition
+  */
+typedef struct
+{
+ uint32_t SignalID;      /*!< Specifies the ID of the signal used for DMAMUX request generator
+                              This parameter can be a value of @ref DMAEx_MUX_SignalGeneratorID_selection */
+
+  uint32_t Polarity;       /*!< Specifies the polarity of the signal on which the request is generated.
+                             This parameter can be a value of @ref DMAEx_MUX_RequestGeneneratorPolarity_selection */
+
+  uint32_t RequestNumber;  /*!< Specifies the number of DMA request that will be generated after a signal event.
+                                This parameters can be in the range 1 to 32 */
+
+}HAL_DMA_MuxRequestGeneratorConfigTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMAEx_Exported_Constants DMA Exported Constants
+  * @brief    DMAEx Exported constants
+  * @{
+  */
+
+/** @defgroup DMAEx_MUX_SyncSignalID_selection DMAEx MUX SyncSignalID selection
+  * @brief    DMAEx MUX SyncSignalID selection
+  * @{
+  */
+#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT   0U   /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel0 Event */
+#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT   1U   /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel1 Event */
+#define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT   2U   /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel2 Event */
+#define HAL_DMAMUX1_SYNC_LPTIM1_OUT        3U   /*!< DMAMUX1 synchronization Signal is LPTIM1 OUT             */
+#define HAL_DMAMUX1_SYNC_LPTIM2_OUT        4U   /*!< DMAMUX1 synchronization Signal is LPTIM2 OUT             */
+#define HAL_DMAMUX1_SYNC_LPTIM3_OUT        5U   /*!< DMAMUX1 synchronization Signal is LPTIM3 OUT             */
+#define HAL_DMAMUX1_SYNC_EXTI0             6U   /*!< DMAMUX1 synchronization Signal is EXTI0 IT               */
+#define HAL_DMAMUX1_SYNC_TIM12_TRGO        7U   /*!< DMAMUX1 synchronization Signal is TIM12 TRGO             */
+
+#define HAL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT   0U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel0 Event */
+#define HAL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT   1U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel1 Event */
+#define HAL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT   2U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel2 Event */
+#define HAL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT   3U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel3 Event */
+#define HAL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT   4U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel4 Event */
+#define HAL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT   5U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel5 Event */
+#define HAL_DMAMUX2_SYNC_LPUART1_RX_WKUP   6U   /*!< DMAMUX2 synchronization Signal is LPUART1 RX Wakeup      */
+#define HAL_DMAMUX2_SYNC_LPUART1_TX_WKUP   7U   /*!< DMAMUX2 synchronization Signal is LPUART1 TX Wakeup      */
+#define HAL_DMAMUX2_SYNC_LPTIM2_OUT        8U   /*!< DMAMUX2 synchronization Signal is LPTIM2 output          */
+#define HAL_DMAMUX2_SYNC_LPTIM3_OUT        9U   /*!< DMAMUX2 synchronization Signal is LPTIM3 output          */
+#define HAL_DMAMUX2_SYNC_I2C4_WKUP        10U   /*!< DMAMUX2 synchronization Signal is I2C4 Wakeup            */
+#define HAL_DMAMUX2_SYNC_SPI6_WKUP        11U   /*!< DMAMUX2 synchronization Signal is SPI6 Wakeup            */
+#define HAL_DMAMUX2_SYNC_COMP1_OUT        12U   /*!< DMAMUX2 synchronization Signal is Comparator 1 output    */
+#define HAL_DMAMUX2_SYNC_RTC_WKUP         13U   /*!< DMAMUX2 synchronization Signal is RTC Wakeup             */
+#define HAL_DMAMUX2_SYNC_EXTI0            14U   /*!< DMAMUX2 synchronization Signal is EXTI0 IT               */
+#define HAL_DMAMUX2_SYNC_EXTI2            15U   /*!< DMAMUX2 synchronization Signal is EXTI2 IT               */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMAEx_MUX_SyncPolarity_selection DMAEx MUX SyncPolarity selection
+  * @brief    DMAEx MUX SyncPolarity selection
+  * @{
+  */
+#define HAL_DMAMUX_SYNC_NO_EVENT        0x00000000U             /*!< block synchronization events                    */
+#define HAL_DMAMUX_SYNC_RISING          DMAMUX_CxCR_SPOL_0      /*!< synchronize with rising edge events             */
+#define HAL_DMAMUX_SYNC_FALLING         DMAMUX_CxCR_SPOL_1      /*!< synchronize with falling edge events            */
+#define HAL_DMAMUX_SYNC_RISING_FALLING  DMAMUX_CxCR_SPOL        /*!< synchronize with rising and falling edge events */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup DMAEx_MUX_SignalGeneratorID_selection DMAEx MUX SignalGeneratorID selection
+  * @brief    DMAEx MUX SignalGeneratorID selection
+  * @{
+  */
+#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT   0U   /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel0 Event */
+#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT   1U   /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel1 Event */
+#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT   2U   /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel2 Event */
+#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT        3U   /*!< DMAMUX1 Request generator Signal is LPTIM1 OUT             */
+#define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT        4U   /*!< DMAMUX1 Request generator Signal is LPTIM2 OUT             */
+#define HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT        5U   /*!< DMAMUX1 Request generator Signal is LPTIM3 OUT             */
+#define HAL_DMAMUX1_REQ_GEN_EXTI0             6U   /*!< DMAMUX1 Request generator Signal is EXTI0 IT               */
+#define HAL_DMAMUX1_REQ_GEN_TIM12_TRGO        7U   /*!< DMAMUX1 Request generator Signal is TIM12 TRGO             */
+
+#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT   0U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel0 Event */
+#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT   1U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel1 Event */
+#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT   2U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel2 Event */
+#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT   3U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel3 Event */
+#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT   4U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel4 Event */
+#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT   5U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel5 Event */
+#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT   6U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel6 Event */
+#define HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP   7U   /*!< DMAMUX2 Request generator Signal is LPUART1 RX Wakeup      */
+#define HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP   8U   /*!< DMAMUX2 Request generator Signal is LPUART1 TX Wakeup      */
+#define HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP       9U   /*!< DMAMUX2 Request generator Signal is LPTIM2 Wakeup          */
+#define HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT       10U   /*!< DMAMUX2 Request generator Signal is LPTIM2 OUT             */
+#define HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP      11U   /*!< DMAMUX2 Request generator Signal is LPTIM3 Wakeup          */
+#define HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT       12U   /*!< DMAMUX2 Request generator Signal is LPTIM3 OUT             */
+#if defined(LPTIM4)
+#define HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP      13U   /*!< DMAMUX2 Request generator Signal is LPTIM4 Wakeup          */
+#endif /* LPTIM4 */
+#if defined(LPTIM5)
+#define HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP      14U   /*!< DMAMUX2 Request generator Signal is LPTIM5 Wakeup          */
+#endif /* LPTIM5 */
+#define HAL_DMAMUX2_REQ_GEN_I2C4_WKUP        15U   /*!< DMAMUX2 Request generator Signal is I2C4 Wakeup            */
+#define HAL_DMAMUX2_REQ_GEN_SPI6_WKUP        16U   /*!< DMAMUX2 Request generator Signal is SPI6 Wakeup            */
+#define HAL_DMAMUX2_REQ_GEN_COMP1_OUT        17U   /*!< DMAMUX2 Request generator Signal is Comparator 1 output    */
+#define HAL_DMAMUX2_REQ_GEN_COMP2_OUT        18U   /*!< DMAMUX2 Request generator Signal is Comparator 2 output    */
+#define HAL_DMAMUX2_REQ_GEN_RTC_WKUP         19U   /*!< DMAMUX2 Request generator Signal is RTC Wakeup             */
+#define HAL_DMAMUX2_REQ_GEN_EXTI0            20U   /*!< DMAMUX2 Request generator Signal is EXTI0                  */
+#define HAL_DMAMUX2_REQ_GEN_EXTI2            21U   /*!< DMAMUX2 Request generator Signal is EXTI2                  */
+#define HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT      22U   /*!< DMAMUX2 Request generator Signal is I2C4 IT Event          */
+#define HAL_DMAMUX2_REQ_GEN_SPI6_IT          23U   /*!< DMAMUX2 Request generator Signal is SPI6 IT                */
+#define HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT    24U   /*!< DMAMUX2 Request generator Signal is LPUART1 Tx IT          */
+#define HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT    25U   /*!< DMAMUX2 Request generator Signal is LPUART1 Rx IT          */
+#if defined(ADC3)
+#define HAL_DMAMUX2_REQ_GEN_ADC3_IT          26U   /*!< DMAMUX2 Request generator Signal is ADC3 IT                */
+#define HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT    27U   /*!< DMAMUX2 Request generator Signal is ADC3 Analog Watchdog 1 output */
+#endif /* ADC3 */
+#define HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT      28U   /*!< DMAMUX2 Request generator Signal is BDMA Channel 0 IT      */
+#define HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT      29U   /*!< DMAMUX2 Request generator Signal is BDMA Channel 1 IT      */
+
+
+/**
+  * @}
+  */
+
+/** @defgroup DMAEx_MUX_RequestGeneneratorPolarity_selection DMAEx MUX RequestGeneneratorPolarity selection
+  * @brief    DMAEx MUX RequestGeneneratorPolarity selection
+  * @{
+  */
+#define HAL_DMAMUX_REQ_GEN_NO_EVENT        0x00000000U           /*!< block request generator events                     */
+#define HAL_DMAMUX_REQ_GEN_RISING          DMAMUX_RGxCR_GPOL_0  /*!< generate request on rising edge events             */
+#define HAL_DMAMUX_REQ_GEN_FALLING         DMAMUX_RGxCR_GPOL_1  /*!< generate request on falling edge events            */
+#define HAL_DMAMUX_REQ_GEN_RISING_FALLING  DMAMUX_RGxCR_GPOL    /*!< generate request on rising and falling edge events */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
+  * @brief   DMAEx Exported functions
+  * @{
+  */
+
+/** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions
+  * @brief   Extended features functions
+  * @{
+  */
+
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory);
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig);
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig);
+HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma);
+
+void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DMAEx_Private_Macros DMA Private Macros
+  * @brief    DMAEx private macros
+  * @{
+  */
+
+#define IS_DMA_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_TIM12_TRGO)
+#define IS_BDMA_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX2_SYNC_EXTI2)
+
+#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
+
+#define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT)    || \
+                                           ((POLARITY) == HAL_DMAMUX_SYNC_RISING)   || \
+                                           ((POLARITY) == HAL_DMAMUX_SYNC_FALLING)  || \
+                                           ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING))
+
+#define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE)   || ((SYNC) == ENABLE))
+
+#define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE)   || \
+                                     ((EVENT) == ENABLE))
+
+#define IS_DMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_TIM12_TRGO)
+#define IS_BDMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT)
+
+#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
+
+#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT) || \
+                                                  ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING)   || \
+                                                  ((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING)   || \
+                                                  ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING))
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DMAEx_Private_Functions DMAEx Private Functions
+  * @brief DMAEx Private functions
+  * @{
+  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h
new file mode 100644
index 00000000..6273f3c3
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h
@@ -0,0 +1,507 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_exti.h
+  * @author  MCD Application Team
+  * @brief   Header file of EXTI HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_EXTI_H
+#define STM32H7xx_HAL_EXTI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup EXTI EXTI
+  * @brief EXTI HAL module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup EXTI_Exported_Types EXTI Exported Types
+  * @{
+  */
+typedef enum
+{
+  HAL_EXTI_COMMON_CB_ID          = 0x00U,
+} EXTI_CallbackIDTypeDef;
+
+
+/**
+  * @brief  EXTI Handle structure definition
+  */
+typedef struct
+{
+  uint32_t Line;                    /*!<  Exti line number */
+  void (* PendingCallback)(void);   /*!<  Exti pending callback */
+} EXTI_HandleTypeDef;
+
+/**
+  * @brief  EXTI Configuration structure definition
+  */
+typedef struct
+{
+  uint32_t Line;           /*!< The Exti line to be configured. This parameter
+                                can be a value of @ref EXTI_Line */
+  uint32_t Mode;           /*!< The Exit Mode to be configured for a core.
+                                This parameter can be a combination of @ref EXTI_Mode */
+  uint32_t Trigger;        /*!< The Exti Trigger to be configured. This parameter
+                                can be a value of @ref EXTI_Trigger */
+  uint32_t GPIOSel;        /*!< The Exti GPIO multiplexer selection to be configured.
+                                This parameter is only possible for line 0 to 15. It
+                                can be a value of @ref EXTI_GPIOSel */
+
+  uint32_t PendClearSource; /*!< Specifies the event pending clear source for D3/SRD
+                                 domain. This parameter can be a value of @ref
+                                 EXTI_PendClear_Source */
+
+} EXTI_ConfigTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
+  * @{
+  */
+
+/** @defgroup EXTI_Line  EXTI Line
+  * @{
+  */
+#define EXTI_LINE_0                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x00U)
+#define EXTI_LINE_1                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x01U)
+#define EXTI_LINE_2                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x02U)
+#define EXTI_LINE_3                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x03U)
+#define EXTI_LINE_4                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x04U)
+#define EXTI_LINE_5                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x05U)
+#define EXTI_LINE_6                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x06U)
+#define EXTI_LINE_7                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x07U)
+#define EXTI_LINE_8                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x08U)
+#define EXTI_LINE_9                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x09U)
+#define EXTI_LINE_10                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x0AU)
+#define EXTI_LINE_11                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x0BU)
+#define EXTI_LINE_12                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x0CU)
+#define EXTI_LINE_13                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x0DU)
+#define EXTI_LINE_14                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x0EU)
+#define EXTI_LINE_15                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x0FU)
+#define EXTI_LINE_16                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x10U)
+#define EXTI_LINE_17                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x11U)
+#define EXTI_LINE_18                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x12U)
+#define EXTI_LINE_19                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x13U)
+#define EXTI_LINE_20                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x14U)
+#define EXTI_LINE_21                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x15U)
+#define EXTI_LINE_22                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x16U)
+#define EXTI_LINE_23                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x17U)
+#define EXTI_LINE_24                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x18U)
+#define EXTI_LINE_25                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x19U)
+#define EXTI_LINE_26                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1AU)
+#define EXTI_LINE_27                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1BU)
+#define EXTI_LINE_28                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1CU)
+#define EXTI_LINE_29                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1DU)
+#define EXTI_LINE_30                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1EU)
+#define EXTI_LINE_31                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1FU)
+#define EXTI_LINE_32                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x00U)
+#define EXTI_LINE_33                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x01U)
+#define EXTI_LINE_34                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x02U)
+#define EXTI_LINE_35                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x03U)
+#define EXTI_LINE_36                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x04U)
+#define EXTI_LINE_37                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x05U)
+#define EXTI_LINE_38                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x06U)
+#define EXTI_LINE_39                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x07U)
+#define EXTI_LINE_40                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x08U)
+#define EXTI_LINE_41                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x09U)
+#define EXTI_LINE_42                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0AU)
+#define EXTI_LINE_43                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0BU)
+#if !defined(USB2_OTG_FS)
+#define EXTI_LINE_44                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE    | 0x0CU)
+#else
+#define EXTI_LINE_44                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0CU)
+#endif /* USB2_OTG_FS */
+#define EXTI_LINE_45                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE    | 0x0DU)
+#if defined(DSI)
+#define EXTI_LINE_46                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0EU)
+#else
+#define EXTI_LINE_46                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE    | 0x0EU)
+#endif /* DSI */
+#define EXTI_LINE_47                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0FU)
+#define EXTI_LINE_48                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x10U)
+#define EXTI_LINE_49                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x11U)
+#define EXTI_LINE_50                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x12U)
+#define EXTI_LINE_51                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x13U)
+#if !defined(UART9)
+#define EXTI_LINE_52                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x14U)
+#else
+#define EXTI_LINE_52                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x14U)
+#endif /* UART9 */
+#if !defined(USART10)
+#define EXTI_LINE_53                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x15U)
+#else
+#define EXTI_LINE_53                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x15U)
+#endif /* USART10 */
+#define EXTI_LINE_54                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x16U)
+#define EXTI_LINE_55                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x17U)
+#define EXTI_LINE_56                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x18U)
+#define EXTI_LINE_57                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x19U)
+#define EXTI_LINE_58                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1AU)
+#define EXTI_LINE_59                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1BU)
+#define EXTI_LINE_60                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1CU)
+#define EXTI_LINE_61                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1DU)
+#define EXTI_LINE_62                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1EU)
+#define EXTI_LINE_63                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1FU)
+#define EXTI_LINE_64                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x00U)
+#define EXTI_LINE_65                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x01U)
+#define EXTI_LINE_66                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x02U)
+#define EXTI_LINE_67                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x03U)
+#define EXTI_LINE_68                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x04U)
+#define EXTI_LINE_69                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x05U)
+#define EXTI_LINE_70                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x06U)
+#define EXTI_LINE_71                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x07U)
+#define EXTI_LINE_72                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x08U)
+#define EXTI_LINE_73                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x09U)
+#define EXTI_LINE_74                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0AU)
+#if defined(ADC3)
+#define EXTI_LINE_75                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0BU)
+#else
+#define EXTI_LINE_75                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 |  EXTI_TARGET_MSK_NONE   | 0x0BU)
+#endif /* ADC3 */
+#if defined(SAI4)
+#define EXTI_LINE_76                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0CU)
+#else
+#define EXTI_LINE_76                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 |  EXTI_TARGET_MSK_NONE   | 0x0CU)
+#endif /* SAI4 */
+#if defined (DUAL_CORE)
+#define EXTI_LINE_77                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x0DU)
+#define EXTI_LINE_78                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU2| 0x0EU)
+#define EXTI_LINE_79                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x0FU)
+#define EXTI_LINE_80                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU2| 0x10U)
+#else
+#define EXTI_LINE_77                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0DU)
+#define EXTI_LINE_78                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0EU)
+#define EXTI_LINE_79                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0FU)
+#define EXTI_LINE_80                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x10U)
+#endif /* DUAL_CORE */
+
+#define EXTI_LINE_81                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x11U)
+
+#if defined (DUAL_CORE)
+#define EXTI_LINE_82                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU2| 0x12U)
+#else
+#define EXTI_LINE_82                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x12U)
+#endif /* DUAL_CORE */
+
+#define EXTI_LINE_83                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x13U)
+#if defined (DUAL_CORE)
+#define EXTI_LINE_84                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x14U)
+#else
+#define EXTI_LINE_84                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x14U)
+#endif /* DUAL_CORE */
+#define EXTI_LINE_85                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x15U)
+#if defined(ETH)
+#define EXTI_LINE_86                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x16U)
+#else
+#define EXTI_LINE_86                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x16U)
+#endif /* ETH */
+#define EXTI_LINE_87                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x17U)
+#if defined(DTS)
+#define EXTI_LINE_88                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL | 0x18U)
+#endif /* DTS */
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Mode  EXTI Mode
+  * @{
+  */
+#define EXTI_MODE_NONE                      0x00000000U
+#define EXTI_MODE_INTERRUPT                 0x00000001U
+#define EXTI_MODE_EVENT                     0x00000002U
+#if defined(DUAL_CORE)
+#define EXTI_MODE_CORE1_INTERRUPT           EXTI_MODE_INTERRUPT
+#define EXTI_MODE_CORE1_EVENT               EXTI_MODE_EVENT
+#define EXTI_MODE_CORE2_INTERRUPT           0x00000010U
+#define EXTI_MODE_CORE2_EVENT               0x00000020U
+#endif /* DUAL_CORE */
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Trigger  EXTI Trigger
+  * @{
+  */
+#define EXTI_TRIGGER_NONE                   0x00000000U
+#define EXTI_TRIGGER_RISING                 0x00000001U
+#define EXTI_TRIGGER_FALLING                0x00000002U
+#define EXTI_TRIGGER_RISING_FALLING         (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_GPIOSel  EXTI GPIOSel
+  * @brief
+  * @{
+  */
+#define EXTI_GPIOA                          0x00000000U
+#define EXTI_GPIOB                          0x00000001U
+#define EXTI_GPIOC                          0x00000002U
+#define EXTI_GPIOD                          0x00000003U
+#define EXTI_GPIOE                          0x00000004U
+#define EXTI_GPIOF                          0x00000005U
+#define EXTI_GPIOG                          0x00000006U
+#define EXTI_GPIOH                          0x00000007U
+#define EXTI_GPIOI                          0x00000008U
+#define EXTI_GPIOJ                          0x00000009U
+#define EXTI_GPIOK                          0x0000000AU
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_PendClear_Source  EXTI PendClear Source
+  * @brief
+  * @{
+  */
+#define EXTI_D3_PENDCLR_SRC_NONE       0x00000000U /*!< No D3 domain pendclear source , PMRx register to be set to zero  */
+#define EXTI_D3_PENDCLR_SRC_DMACH6     0x00000001U /*!< DMA ch6 event selected as D3 domain pendclear source, PMRx register to be set to 1 */
+#define EXTI_D3_PENDCLR_SRC_DMACH7     0x00000002U /*!< DMA ch7 event selected as D3 domain pendclear source, PMRx register to be set to 1*/
+#if defined (LPTIM4)
+#define EXTI_D3_PENDCLR_SRC_LPTIM4     0x00000003U /*!< LPTIM4 out selected as D3 domain pendclear source, PMRx register to be set to 1    */
+#else
+#define EXTI_D3_PENDCLR_SRC_LPTIM2     0x00000003U /*!< LPTIM2 out selected as D3 domain pendclear source, PMRx register to be set to 1    */
+#endif
+#if defined (LPTIM5)
+#define EXTI_D3_PENDCLR_SRC_LPTIM5     0x00000004U /*!< LPTIM5 out selected as D3 domain pendclear source, PMRx register to be set to 1    */
+#else
+#define EXTI_D3_PENDCLR_SRC_LPTIM3     0x00000004U /*!< LPTIM3 out selected as D3 domain pendclear source, PMRx register to be set to 1    */
+#endif
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants --------------------------------------------------------*/
+/** @defgroup EXTI_Private_Constants EXTI Private Constants
+  * @{
+  */
+/**
+  * @brief  EXTI Line property definition
+  */
+#define EXTI_PROPERTY_SHIFT                 24U
+#define EXTI_DIRECT                         (0x01UL << EXTI_PROPERTY_SHIFT)
+#define EXTI_CONFIG                         (0x02UL << EXTI_PROPERTY_SHIFT)
+#define EXTI_GPIO                           ((0x04UL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
+#define EXTI_RESERVED                       (0x08UL << EXTI_PROPERTY_SHIFT)
+#define EXTI_PROPERTY_MASK                  (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
+
+/**
+  * @brief  EXTI Event presence definition
+  */
+#define EXTI_EVENT_PRESENCE_SHIFT           28U
+#define EXTI_EVENT                          (0x01UL << EXTI_EVENT_PRESENCE_SHIFT)
+#define EXTI_EVENT_PRESENCE_MASK            (EXTI_EVENT)
+
+/**
+  * @brief  EXTI Register and bit usage
+  */
+#define EXTI_REG_SHIFT                      16U
+#define EXTI_REG1                           (0x00UL << EXTI_REG_SHIFT)
+#define EXTI_REG2                           (0x01UL << EXTI_REG_SHIFT)
+#define EXTI_REG3                           (0x02UL << EXTI_REG_SHIFT)
+#define EXTI_REG_MASK                       (EXTI_REG1 | EXTI_REG2 | EXTI_REG3)
+#define EXTI_PIN_MASK                       0x0000001FUL
+
+/**
+  * @brief  EXTI Target and bit usage
+  */
+#define EXTI_TARGET_SHIFT                   20U
+#define EXTI_TARGET_MSK_NONE                (0x00UL << EXTI_TARGET_SHIFT)
+#define EXTI_TARGET_MSK_D3SRD               (0x01UL << EXTI_TARGET_SHIFT)
+#define EXTI_TARGET_MSK_CPU1                (0x02UL << EXTI_TARGET_SHIFT)
+#if defined (DUAL_CORE)
+#define EXTI_TARGET_MSK_CPU2                (0x04UL << EXTI_TARGET_SHIFT)
+#define EXTI_TARGET_MASK                    (EXTI_TARGET_MSK_D3SRD | EXTI_TARGET_MSK_CPU1 | EXTI_TARGET_MSK_CPU2)
+#define EXTI_TARGET_MSK_ALL_CPU             (EXTI_TARGET_MSK_CPU1 | EXTI_TARGET_MSK_CPU2)
+#else
+#define EXTI_TARGET_MASK                    (EXTI_TARGET_MSK_D3SRD | EXTI_TARGET_MSK_CPU1)
+#define EXTI_TARGET_MSK_ALL_CPU              EXTI_TARGET_MSK_CPU1
+#endif /* DUAL_CORE */
+#define EXTI_TARGET_MSK_ALL                  EXTI_TARGET_MASK
+
+/**
+  * @brief  EXTI Mask for interrupt & event mode
+  */
+#if defined (DUAL_CORE)
+#define EXTI_MODE_MASK                      (EXTI_MODE_CORE1_EVENT | EXTI_MODE_CORE1_INTERRUPT | EXTI_MODE_CORE2_INTERRUPT | EXTI_MODE_CORE2_EVENT)
+#else
+#define EXTI_MODE_MASK                      (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
+#endif /* DUAL_CORE */
+
+/**
+  * @brief  EXTI Mask for trigger possibilities
+  */
+#define EXTI_TRIGGER_MASK                   (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
+
+/**
+  * @brief  EXTI Line number
+  */
+#if defined (EXTI_LINE_88)
+#define EXTI_LINE_NB                        89UL
+#else
+#define EXTI_LINE_NB                        88UL
+#endif /* EXTI_LINE_88 */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup EXTI_Private_Macros EXTI Private Macros
+  * @{
+  */
+#define IS_EXTI_PROPERTY(__LINE__)      ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
+                                         (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG)          || \
+                                         (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO))
+#if defined (DUAL_CORE)
+#define IS_EXTI_TARGET(__LINE__)        ((((__LINE__) & EXTI_TARGET_MASK)   == EXTI_TARGET_MSK_CPU1)      || \
+                                         (((__LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_CPU2)    || \
+                                         (((__LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL_CPU) || \
+                                         (((__LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL))
+#else
+#define IS_EXTI_TARGET(__LINE__)        ((((__LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_CPU1)   || \
+                                         (((__LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL))
+#endif
+
+#define IS_EXTI_LINE(__LINE__)          ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_EVENT_PRESENCE_MASK | EXTI_REG_MASK | EXTI_PIN_MASK | EXTI_TARGET_MASK)) == 0x00UL) && \
+                                         IS_EXTI_PROPERTY(__LINE__) && IS_EXTI_TARGET(__LINE__) && \
+                                         (((__LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK))      < \
+                                         (((EXTI_LINE_NB / 32UL) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32UL))))
+
+#define IS_EXTI_MODE(__MODE__)          (((__MODE__) & ~EXTI_MODE_MASK) == 0x00UL)
+
+#define IS_EXTI_TRIGGER(__LINE__)       (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00UL)
+
+#define IS_EXTI_PENDING_EDGE(__LINE__)  (((__LINE__) == EXTI_TRIGGER_RISING) || \
+                                         ((__LINE__) == EXTI_TRIGGER_FALLING)|| \
+                                         ((__LINE__) == EXTI_TRIGGER_RISING_FALLING))
+
+#define IS_EXTI_CONFIG_LINE(__LINE__)   (((__LINE__) & EXTI_CONFIG) != 0x00UL)
+
+#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \
+                                         ((__PORT__) == EXTI_GPIOB) || \
+                                         ((__PORT__) == EXTI_GPIOC) || \
+                                         ((__PORT__) == EXTI_GPIOD) || \
+                                         ((__PORT__) == EXTI_GPIOE) || \
+                                         ((__PORT__) == EXTI_GPIOF) || \
+                                         ((__PORT__) == EXTI_GPIOG) || \
+                                         ((__PORT__) == EXTI_GPIOH) || \
+                                         ((__PORT__) == EXTI_GPIOI) || \
+                                         ((__PORT__) == EXTI_GPIOJ) || \
+                                         ((__PORT__) == EXTI_GPIOK))
+
+#define IS_EXTI_GPIO_PIN(__PIN__)       ((__PIN__) < 16UL)
+#if defined (LPTIM4) && defined (LPTIM5)
+#define IS_EXTI_D3_PENDCLR_SRC(__SRC__) (((__SRC__) == EXTI_D3_PENDCLR_SRC_NONE) || \
+                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH6) || \
+                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH7) || \
+                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM4) || \
+                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM5))
+#else
+#define IS_EXTI_D3_PENDCLR_SRC(__SRC__) (((__SRC__) == EXTI_D3_PENDCLR_SRC_NONE) || \
+                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH6) || \
+                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH7) || \
+                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM2) || \
+                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM3))
+#endif /* LPTIM4 && LPTIM5 */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
+  * @brief    EXTI Exported Functions
+  * @{
+  */
+
+/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
+  * @brief    Configuration functions
+  * @{
+  */
+/* Configuration functions ****************************************************/
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
+HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
+HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
+HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
+HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
+  * @brief    IO operation functions
+  * @{
+  */
+/* IO operation functions *****************************************************/
+void              HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
+uint32_t          HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
+void              HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
+void              HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_EXTI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h
new file mode 100644
index 00000000..cfe58cf7
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h
@@ -0,0 +1,2414 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_fdcan.h
+  * @author  MCD Application Team
+  * @brief   Header file of FDCAN HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_FDCAN_H
+#define STM32H7xx_HAL_FDCAN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FDCAN
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FDCAN_Exported_Types FDCAN Exported Types
+  * @{
+  */
+
+/**
+  * @brief HAL State structures definition
+  */
+typedef enum
+{
+  HAL_FDCAN_STATE_RESET      = 0x00U, /*!< FDCAN not yet initialized or disabled */
+  HAL_FDCAN_STATE_READY      = 0x01U, /*!< FDCAN initialized and ready for use   */
+  HAL_FDCAN_STATE_BUSY       = 0x02U, /*!< FDCAN process is ongoing              */
+  HAL_FDCAN_STATE_ERROR      = 0x03U  /*!< FDCAN error state                     */
+} HAL_FDCAN_StateTypeDef;
+
+/**
+  * @brief FDCAN Init structure definition
+  */
+typedef struct
+{
+  uint32_t FrameFormat;                  /*!< Specifies the FDCAN frame format.
+                                              This parameter can be a value of @ref FDCAN_frame_format     */
+
+  uint32_t Mode;                         /*!< Specifies the FDCAN mode.
+                                              This parameter can be a value of @ref FDCAN_operating_mode   */
+
+  FunctionalState AutoRetransmission;    /*!< Enable or disable the automatic retransmission mode.
+                                              This parameter can be set to ENABLE or DISABLE               */
+
+  FunctionalState TransmitPause;         /*!< Enable or disable the Transmit Pause feature.
+                                              This parameter can be set to ENABLE or DISABLE               */
+
+  FunctionalState ProtocolException;      /*!< Enable or disable the Protocol Exception Handling.
+                                              This parameter can be set to ENABLE or DISABLE               */
+
+  uint32_t NominalPrescaler;             /*!< Specifies the value by which the oscillator frequency is
+                                              divided for generating the nominal bit time quanta.
+                                              This parameter must be a number between 1 and 512            */
+
+  uint32_t NominalSyncJumpWidth;         /*!< Specifies the maximum number of time quanta the FDCAN
+                                              hardware is allowed to lengthen or shorten a bit to perform
+                                              resynchronization.
+                                              This parameter must be a number between 1 and 128            */
+
+  uint32_t NominalTimeSeg1;              /*!< Specifies the number of time quanta in Bit Segment 1.
+                                              This parameter must be a number between 2 and 256            */
+
+  uint32_t NominalTimeSeg2;              /*!< Specifies the number of time quanta in Bit Segment 2.
+                                              This parameter must be a number between 2 and 128            */
+
+  uint32_t DataPrescaler;                /*!< Specifies the value by which the oscillator frequency is
+                                              divided for generating the data bit time quanta.
+                                              This parameter must be a number between 1 and 32             */
+
+  uint32_t DataSyncJumpWidth;            /*!< Specifies the maximum number of time quanta the FDCAN
+                                              hardware is allowed to lengthen or shorten a data bit to
+                                              perform resynchronization.
+                                              This parameter must be a number between 1 and 16             */
+
+  uint32_t DataTimeSeg1;                 /*!< Specifies the number of time quanta in Data Bit Segment 1.
+                                              This parameter must be a number between 1 and 32             */
+
+  uint32_t DataTimeSeg2;                 /*!< Specifies the number of time quanta in Data Bit Segment 2.
+                                              This parameter must be a number between 1 and 16             */
+
+  uint32_t MessageRAMOffset;             /*!< Specifies the message RAM start address.
+                                              This parameter must be a number between 0 and 2560           */
+
+  uint32_t StdFiltersNbr;                /*!< Specifies the number of standard Message ID filters.
+                                              This parameter must be a number between 0 and 128            */
+
+  uint32_t ExtFiltersNbr;                /*!< Specifies the number of extended Message ID filters.
+                                              This parameter must be a number between 0 and 64             */
+
+  uint32_t RxFifo0ElmtsNbr;              /*!< Specifies the number of Rx FIFO0 Elements.
+                                              This parameter must be a number between 0 and 64             */
+
+  uint32_t RxFifo0ElmtSize;              /*!< Specifies the Data Field Size in an Rx FIFO 0 element.
+                                              This parameter can be a value of @ref FDCAN_data_field_size  */
+
+  uint32_t RxFifo1ElmtsNbr;              /*!< Specifies the number of Rx FIFO 1 Elements.
+                                              This parameter must be a number between 0 and 64             */
+
+  uint32_t RxFifo1ElmtSize;              /*!< Specifies the Data Field Size in an Rx FIFO 1 element.
+                                              This parameter can be a value of @ref FDCAN_data_field_size  */
+
+  uint32_t RxBuffersNbr;                 /*!< Specifies the number of Dedicated Rx Buffer elements.
+                                              This parameter must be a number between 0 and 64             */
+
+  uint32_t RxBufferSize;                 /*!< Specifies the Data Field Size in an Rx Buffer element.
+                                              This parameter can be a value of @ref FDCAN_data_field_size  */
+
+  uint32_t TxEventsNbr;                  /*!< Specifies the number of Tx Event FIFO elements.
+                                              This parameter must be a number between 0 and 32             */
+
+  uint32_t TxBuffersNbr;                 /*!< Specifies the number of Dedicated Tx Buffers.
+                                              This parameter must be a number between 0 and 32             */
+
+  uint32_t TxFifoQueueElmtsNbr;          /*!< Specifies the number of Tx Buffers used for Tx FIFO/Queue.
+                                              This parameter must be a number between 0 and 32             */
+
+  uint32_t TxFifoQueueMode;              /*!< Tx FIFO/Queue Mode selection.
+                                              This parameter can be a value of @ref FDCAN_txFifoQueue_Mode */
+
+  uint32_t TxElmtSize;                   /*!< Specifies the Data Field Size in a Tx Element.
+                                              This parameter can be a value of @ref FDCAN_data_field_size  */
+
+} FDCAN_InitTypeDef;
+
+/**
+  * @brief  FDCAN clock calibration unit structure definition
+  */
+typedef struct
+{
+  uint32_t ClockCalibration;     /*!< Enable or disable the clock calibration.
+                                      This parameter can be a value of @ref FDCAN_clock_calibration.       */
+
+  uint32_t ClockDivider;         /*!< Specifies the FDCAN kernel clock divider when the clock calibration
+                                      is bypassed.
+                                      This parameter can be a value of @ref FDCAN_clock_divider            */
+
+  uint32_t MinOscClkPeriods;     /*!< Configures the minimum number of periods in two CAN bit times. The
+                                      actual configured number of periods is MinOscClkPeriods x 32.
+                                      This parameter must be a number between 0x00 and 0xFF                */
+
+  uint32_t CalFieldLength;       /*!< Specifies the calibration field length.
+                                      This parameter can be a value of @ref FDCAN_calibration_field_length */
+
+  uint32_t TimeQuantaPerBitTime; /*!< Configures the number of time quanta per bit time.
+                                      This parameter must be a number between 4 and 25                     */
+
+  uint32_t WatchdogStartValue;   /*!< Start value of the Calibration Watchdog Counter.
+                                      If set to zero the counter is disabled.
+                                      This parameter must be a number between 0x0000 and 0xFFFF            */
+
+} FDCAN_ClkCalUnitTypeDef;
+
+/**
+  * @brief  FDCAN filter structure definition
+  */
+typedef struct
+{
+  uint32_t IdType;           /*!< Specifies the identifier type.
+                                  This parameter can be a value of @ref FDCAN_id_type       */
+
+  uint32_t FilterIndex;      /*!< Specifies the filter which will be initialized.
+                                  This parameter must be a number between:
+                                   - 0 and 127, if IdType is FDCAN_STANDARD_ID
+                                   - 0 and 63, if IdType is FDCAN_EXTENDED_ID               */
+
+  uint32_t FilterType;       /*!< Specifies the filter type.
+                                  This parameter can be a value of @ref FDCAN_filter_type.
+                                  The value FDCAN_EXT_FILTER_RANGE_NO_EIDM is permitted
+                                  only when IdType is FDCAN_EXTENDED_ID.
+                                  This parameter is ignored if FilterConfig is set to
+                                  FDCAN_FILTER_TO_RXBUFFER                                  */
+
+  uint32_t FilterConfig;     /*!< Specifies the filter configuration.
+                                  This parameter can be a value of @ref FDCAN_filter_config */
+
+  uint32_t FilterID1;        /*!< Specifies the filter identification 1.
+                                  This parameter must be a number between:
+                                   - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+                                   - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID       */
+
+  uint32_t FilterID2;        /*!< Specifies the filter identification 2.
+                                  This parameter is ignored if FilterConfig is set to
+                                  FDCAN_FILTER_TO_RXBUFFER.
+                                  This parameter must be a number between:
+                                   - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+                                   - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID       */
+
+  uint32_t RxBufferIndex;    /*!< Contains the index of the Rx buffer in which the
+                                  matching message will be stored.
+                                  This parameter must be a number between 0 and 63.
+                                  This parameter is ignored if FilterConfig is different
+                                  from FDCAN_FILTER_TO_RXBUFFER                             */
+
+  uint32_t IsCalibrationMsg; /*!< Specifies whether the filter is configured for
+                                  calibration messages.
+                                  This parameter is ignored if FilterConfig is different
+                                  from FDCAN_FILTER_TO_RXBUFFER.
+                                  This parameter can be:
+                                   - 0 : ordinary message
+                                   - 1 : calibration message                                */
+
+} FDCAN_FilterTypeDef;
+
+/**
+  * @brief  FDCAN Tx header structure definition
+  */
+typedef struct
+{
+  uint32_t Identifier;          /*!< Specifies the identifier.
+                                     This parameter must be a number between:
+                                      - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+                                      - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID               */
+
+  uint32_t IdType;              /*!< Specifies the identifier type for the message that will be
+                                     transmitted.
+                                     This parameter can be a value of @ref FDCAN_id_type               */
+
+  uint32_t TxFrameType;         /*!< Specifies the frame type of the message that will be transmitted.
+                                     This parameter can be a value of @ref FDCAN_frame_type            */
+
+  uint32_t DataLength;          /*!< Specifies the length of the frame that will be transmitted.
+                                      This parameter can be a value of @ref FDCAN_data_length_code     */
+
+  uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
+                                     This parameter can be a value of @ref FDCAN_error_state_indicator */
+
+  uint32_t BitRateSwitch;       /*!< Specifies whether the Tx frame will be transmitted with or without
+                                     bit rate switching.
+                                     This parameter can be a value of @ref FDCAN_bit_rate_switching    */
+
+  uint32_t FDFormat;            /*!< Specifies whether the Tx frame will be transmitted in classic or
+                                     FD format.
+                                     This parameter can be a value of @ref FDCAN_format                */
+
+  uint32_t TxEventFifoControl;  /*!< Specifies the event FIFO control.
+                                     This parameter can be a value of @ref FDCAN_EFC                   */
+
+  uint32_t MessageMarker;       /*!< Specifies the message marker to be copied into Tx Event FIFO
+                                     element for identification of Tx message status.
+                                     This parameter must be a number between 0 and 0xFF                */
+
+} FDCAN_TxHeaderTypeDef;
+
+/**
+  * @brief  FDCAN Rx header structure definition
+  */
+typedef struct
+{
+  uint32_t Identifier;            /*!< Specifies the identifier.
+                                       This parameter must be a number between:
+                                        - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+                                        - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID               */
+
+  uint32_t IdType;                /*!< Specifies the identifier type of the received message.
+                                       This parameter can be a value of @ref FDCAN_id_type               */
+
+  uint32_t RxFrameType;           /*!< Specifies the the received message frame type.
+                                       This parameter can be a value of @ref FDCAN_frame_type            */
+
+  uint32_t DataLength;            /*!< Specifies the received frame length.
+                                        This parameter can be a value of @ref FDCAN_data_length_code     */
+
+  uint32_t ErrorStateIndicator;   /*!< Specifies the error state indicator.
+                                       This parameter can be a value of @ref FDCAN_error_state_indicator */
+
+  uint32_t BitRateSwitch;         /*!< Specifies whether the Rx frame is received with or without bit
+                                       rate switching.
+                                       This parameter can be a value of @ref FDCAN_bit_rate_switching    */
+
+  uint32_t FDFormat;              /*!< Specifies whether the Rx frame is received in classic or FD
+                                       format.
+                                       This parameter can be a value of @ref FDCAN_format                */
+
+  uint32_t RxTimestamp;           /*!< Specifies the timestamp counter value captured on start of frame
+                                       reception.
+                                       This parameter must be a number between 0 and 0xFFFF              */
+
+  uint32_t FilterIndex;           /*!< Specifies the index of matching Rx acceptance filter element.
+                                       This parameter must be a number between:
+                                        - 0 and 127, if IdType is FDCAN_STANDARD_ID
+                                        - 0 and 63, if IdType is FDCAN_EXTENDED_ID                       */
+
+  uint32_t IsFilterMatchingFrame; /*!< Specifies whether the accepted frame did not match any Rx filter.
+                                         Acceptance of non-matching frames may be enabled via
+                                         HAL_FDCAN_ConfigGlobalFilter().
+                                         This parameter can be 0 or 1                                    */
+
+} FDCAN_RxHeaderTypeDef;
+
+/**
+  * @brief  FDCAN Tx event FIFO structure definition
+  */
+typedef struct
+{
+  uint32_t Identifier;          /*!< Specifies the identifier.
+                                     This parameter must be a number between:
+                                      - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+                                      - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID               */
+
+  uint32_t IdType;              /*!< Specifies the identifier type for the transmitted message.
+                                     This parameter can be a value of @ref FDCAN_id_type               */
+
+  uint32_t TxFrameType;         /*!< Specifies the frame type of the transmitted message.
+                                     This parameter can be a value of @ref FDCAN_frame_type            */
+
+  uint32_t DataLength;          /*!< Specifies the length of the transmitted frame.
+                                     This parameter can be a value of @ref FDCAN_data_length_code      */
+
+  uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
+                                     This parameter can be a value of @ref FDCAN_error_state_indicator */
+
+  uint32_t BitRateSwitch;       /*!< Specifies whether the Tx frame is transmitted with or without bit
+                                     rate switching.
+                                     This parameter can be a value of @ref FDCAN_bit_rate_switching    */
+
+  uint32_t FDFormat;            /*!< Specifies whether the Tx frame is transmitted in classic or FD
+                                     format.
+                                     This parameter can be a value of @ref FDCAN_format                */
+
+  uint32_t TxTimestamp;         /*!< Specifies the timestamp counter value captured on start of frame
+                                     transmission.
+                                     This parameter must be a number between 0 and 0xFFFF              */
+
+  uint32_t MessageMarker;       /*!< Specifies the message marker copied into Tx Event FIFO element
+                                     for identification of Tx message status.
+                                     This parameter must be a number between 0 and 0xFF                */
+
+  uint32_t EventType;           /*!< Specifies the event type.
+                                     This parameter can be a value of @ref FDCAN_event_type            */
+
+} FDCAN_TxEventFifoTypeDef;
+
+/**
+  * @brief  FDCAN High Priority Message Status structure definition
+  */
+typedef struct
+{
+  uint32_t FilterList;     /*!< Specifies the filter list of the matching filter element.
+                                This parameter can be:
+                                 - 0 : Standard Filter List
+                                 - 1 : Extended Filter List                                */
+
+  uint32_t FilterIndex;    /*!< Specifies the index of matching filter element.
+                                This parameter can be a number between:
+                                - 0 and 127, if FilterList is 0 (Standard)
+                                - 0 and 63, if FilterList is 1 (Extended)                  */
+
+  uint32_t MessageStorage; /*!< Specifies the HP Message Storage.
+                                This parameter can be a value of @ref FDCAN_hp_msg_storage */
+
+  uint32_t MessageIndex;   /*!< Specifies the Index of Rx FIFO element to which the
+                                message was stored.
+                                This parameter is valid only when MessageStorage is:
+                                  FDCAN_HP_STORAGE_RXFIFO0
+                                 or
+                                  FDCAN_HP_STORAGE_RXFIFO1                                 */
+
+} FDCAN_HpMsgStatusTypeDef;
+
+/**
+  * @brief FDCAN Protocol Status structure definition
+  */
+typedef struct
+{
+  uint32_t LastErrorCode;     /*!< Specifies the type of the last error that occurred on the FDCAN bus.
+                                   This parameter can be a value of @ref FDCAN_protocol_error_code                           */
+
+  uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase of a CAN FD format
+                                   frame with its BRS flag set.
+                                   This parameter can be a value of @ref FDCAN_protocol_error_code                           */
+
+  uint32_t Activity;          /*!< Specifies the FDCAN module communication state.
+                                   This parameter can be a value of @ref FDCAN_communication_state                           */
+
+  uint32_t ErrorPassive;      /*!< Specifies the FDCAN module error status.
+                                   This parameter can be:
+                                    - 0 : The FDCAN is in Error_Active state
+                                    - 1 : The FDCAN is in Error_Passive state                                                */
+
+  uint32_t Warning;           /*!< Specifies the FDCAN module warning status.
+                                   This parameter can be:
+                                    - 0 : error counters (RxErrorCnt and TxErrorCnt) are below the Error_Warning limit of 96
+                                    - 1 : at least one of error counters has reached the Error_Warning limit of 96           */
+
+  uint32_t BusOff;            /*!< Specifies the FDCAN module Bus_Off status.
+                                   This parameter can be:
+                                    - 0 : The FDCAN is not in Bus_Off state
+                                    - 1 : The FDCAN is in Bus_Off state                                                      */
+
+  uint32_t RxESIflag;         /*!< Specifies ESI flag of last received CAN FD message.
+                                   This parameter can be:
+                                    - 0 : Last received CAN FD message did not have its ESI flag set
+                                    - 1 : Last received CAN FD message had its ESI flag set                                  */
+
+  uint32_t RxBRSflag;         /*!< Specifies BRS flag of last received CAN FD message.
+                                   This parameter can be:
+                                    - 0 : Last received CAN FD message did not have its BRS flag set
+                                    - 1 : Last received CAN FD message had its BRS flag set                                  */
+
+  uint32_t RxFDFflag;         /*!< Specifies if CAN FD message (FDF flag set) has been received since last protocol status.
+                                   This parameter can be:
+                                    - 0 : no CAN FD message received
+                                    - 1 : CAN FD message received                                                            */
+
+  uint32_t ProtocolException; /*!< Specifies the FDCAN module Protocol Exception status.
+                                   This parameter can be:
+                                    - 0 : No protocol exception event occurred since last read access
+                                    - 1 : Protocol exception event occurred                                                  */
+
+  uint32_t TDCvalue;          /*!< Specifies the Transmitter Delay Compensation Value.
+                                   This parameter can be a number between 0 and 127                                          */
+
+} FDCAN_ProtocolStatusTypeDef;
+
+/**
+  * @brief FDCAN Error Counters structure definition
+  */
+typedef struct
+{
+  uint32_t TxErrorCnt;     /*!< Specifies the Transmit Error Counter Value.
+                                This parameter can be a number between 0 and 255                                         */
+
+  uint32_t RxErrorCnt;     /*!< Specifies the Receive Error Counter Value.
+                                This parameter can be a number between 0 and 127                                         */
+
+  uint32_t RxErrorPassive; /*!< Specifies the Receive Error Passive status.
+                                This parameter can be:
+                                 - 0 : The Receive Error Counter (RxErrorCnt) is below the error passive level of 128
+                                 - 1 : The Receive Error Counter (RxErrorCnt) has reached the error passive level of 128 */
+
+  uint32_t ErrorLogging;   /*!< Specifies the Transmit/Receive error logging counter value.
+                                This parameter can be a number between 0 and 255.
+                                This counter is incremented each time when a FDCAN protocol error causes the TxErrorCnt
+                                or the RxErrorCnt to be incremented. The counter stops at 255; the next increment of
+                                TxErrorCnt or RxErrorCnt sets interrupt flag FDCAN_FLAG_ERROR_LOGGING_OVERFLOW           */
+
+} FDCAN_ErrorCountersTypeDef;
+
+/**
+  * @brief FDCAN TT Init structure definition
+  */
+typedef struct
+{
+  uint32_t OperationMode;     /*!< Specifies the FDCAN Operation Mode.
+                                   This parameter can be a value of @ref FDCAN_operation_mode               */
+
+  uint32_t GapEnable;         /*!< Specifies the FDCAN TT Operation.
+                                   This parameter can be a value of @ref FDCAN_TT_operation.
+                                   This parameter is ignored if OperationMode is set to
+                                   FDCAN_TT_COMMUNICATION_LEVEL0                                            */
+
+  uint32_t TimeMaster;        /*!< Specifies whether the instance is a slave or a potential master.
+                                   This parameter can be a value of @ref FDCAN_TT_time_master               */
+
+  uint32_t SyncDevLimit;      /*!< Specifies the Synchronization Deviation Limit SDL of the TUR
+                                   numerator : TUR = (Numerator � SDL) / Denominator.
+                                   With : SDL = 2^(SyncDevLimit+5).
+                                   This parameter must be a number between 0 and 7                          */
+
+  uint32_t InitRefTrigOffset; /*!< Specifies the Initial Reference Trigger Offset.
+                                   This parameter must be a number between 0 and 127                        */
+
+  uint32_t ExternalClkSync;   /*!< Enable or disable External Clock Synchronization.
+                                   This parameter can be a value of @ref FDCAN_TT_external_clk_sync.
+                                   This parameter is ignored if OperationMode is set to
+                                   FDCAN_TT_COMMUNICATION_LEVEL1                                            */
+
+  uint32_t AppWdgLimit;       /*!< Specifies the Application Watchdog Limit : maximum time after
+                                   which the application has to serve the application watchdog.
+                                   The application watchdog is incremented once each 256 NTUs.
+                                   The application watchdog can be disabled by setting AppWdgLimit to 0.
+                                   This parameter must be a number between 0 and 255.
+                                   This parameter is ignored if OperationMode is set to
+                                   FDCAN_TT_COMMUNICATION_LEVEL0                                            */
+
+  uint32_t GlobalTimeFilter;  /*!< Enable or disable Global Time Filtering.
+                                   This parameter can be a value of @ref FDCAN_TT_global_time_filtering.
+                                   This parameter is ignored if OperationMode is set to
+                                   FDCAN_TT_COMMUNICATION_LEVEL1                                            */
+
+  uint32_t ClockCalibration;  /*!< Enable or disable Automatic Clock Calibration.
+                                   This parameter can be a value of @ref FDCAN_TT_auto_clk_calibration.
+                                   This parameter is ignored if OperationMode is set to
+                                   FDCAN_TT_COMMUNICATION_LEVEL1                                            */
+
+  uint32_t EvtTrigPolarity;   /*!< Specifies the Event Trigger Polarity.
+                                   This parameter can be a value of @ref FDCAN_TT_event_trig_polarity.
+                                   This parameter is ignored if OperationMode is set to
+                                   FDCAN_TT_COMMUNICATION_LEVEL0                                            */
+
+  uint32_t BasicCyclesNbr;    /*!< Specifies the nubmer of basic cycles in the system matrix.
+                                   This parameter can be a value of @ref FDCAN_TT_basic_cycle_number        */
+
+  uint32_t CycleStartSync;    /*!< Enable or disable synchronization pulse output at pin fdcan1_soc.
+                                   This parameter can be a value of @ref FDCAN_TT_cycle_start_sync          */
+
+  uint32_t TxEnableWindow;    /*!< Specifies the length of Tx enable window in NTUs.
+                                   This parameter must be a number between 1 and 16                         */
+
+  uint32_t ExpTxTrigNbr;      /*!< Specifies the number of expected Tx_Triggers in the system matrix.
+                                   This is the sum of Tx_Triggers for exclusive, single arbitrating and
+                                   merged arbitrating windows.
+                                   This parameter must be a number between 0 and 4095                       */
+
+  uint32_t TURNumerator;      /*!< Specifies the TUR (Time Unit Ratio) numerator.
+                                   It is adviced to set this parameter to the largest applicable value.
+                                   This parameter must be a number between 0x10000 and 0x1FFFF              */
+
+  uint32_t TURDenominator;    /*!< Specifies the TUR (Time Unit Ratio) denominator.
+                                   This parameter must be a number between 0x0001 and 0x3FFF                */
+
+  uint32_t TriggerMemoryNbr;  /*!< Specifies the number of trigger memory elements.
+                                   This parameter must be a number between 0 and 64                         */
+
+  uint32_t StopWatchTrigSel;  /*!< Specifies the input to be used as stop watch trigger.
+                                   This parameter can be a value of @ref FDCAN_TT_stop_watch_trig_selection */
+
+  uint32_t EventTrigSel;      /*!< Specifies the input to be used as event trigger.
+                                   This parameter can be a value of @ref FDCAN_TT_event_trig_selection      */
+
+} FDCAN_TT_ConfigTypeDef;
+
+/**
+  * @brief  FDCAN Trigger structure definition
+  */
+typedef struct
+{
+  uint32_t TriggerIndex;  /*!< Specifies the trigger which will be configured.
+                               This parameter must be a number between 0 and 63                                 */
+
+  uint32_t TimeMark;      /*!< Specifies the cycle time for which the trigger becomes active.
+                               This parameter must be a number between 0 and 0xFFFF                             */
+
+  uint32_t RepeatFactor;  /*!< Specifies the trigger repeat factor.
+                               This parameter can be a value of @ref FDCAN_TT_Repeat_Factor                     */
+
+  uint32_t StartCycle;    /*!< Specifies the index of the first cycle in which the trigger becomes active.
+                               This parameter is ignored if RepeatFactor is set to FDCAN_TT_REPEAT_EVERY_CYCLE.
+                               This parameter must be a number between 0 and RepeatFactor                       */
+
+  uint32_t TmEventInt;    /*!< Enable or disable the internal time mark event.
+                               If enabled, FDCAN_TT_FLAG_TRIG_TIME_MARK flag is set when trigger memory element
+                               becomes active.
+                               This parameter can be a value of @ref FDCAN_TT_Time_Mark_Event_Internal          */
+
+  uint32_t TmEventExt;    /*!< Enable or disable the external time mark event.
+                               If enabled, and if TTOCN.TTIE is set, a pulse is generated at fdcan1_tmp when
+                               trigger memory element becomes active.
+                               This parameter can be a value of @ref FDCAN_TT_Time_Mark_Event_External          */
+
+  uint32_t TriggerType;   /*!< Specifies the trigger type.
+                               This parameter can be a value of @ref FDCAN_TT_Trigger_Type                      */
+
+  uint32_t FilterType;    /*!< Specifies the filter identifier type.
+                               This parameter can be a value of @ref FDCAN_id_type                              */
+
+  uint32_t TxBufferIndex; /*!< Specifies the index of the Tx buffer for which the trigger is valid.
+                               This parameter can be a value of @ref FDCAN_Tx_location.
+                               This parameter is taken in consideration only if the trigger is configured for
+                               transmission.                                                                    */
+
+  uint32_t FilterIndex;   /*!< Specifies the filter for which the trigger is valid.
+                               This parameter is taken in consideration only if the trigger is configured for
+                               reception.
+                               This parameter must be a number between:
+                                - 0 and 127, if FilterType is FDCAN_STANDARD_ID
+                                - 0 and 63, if FilterType is FDCAN_EXTENDED_ID                                  */
+
+} FDCAN_TriggerTypeDef;
+
+/**
+  * @brief  FDCAN TT Operation Status structure definition
+  */
+typedef struct
+{
+  uint32_t ErrorLevel;       /*!< Specifies the type of the TT operation error level.
+                                  This parameter can be a value of @ref FDCAN_TT_error_level                    */
+
+  uint32_t MasterState;      /*!< Specifies the type of the TT master state.
+                                  This parameter can be a value of @ref FDCAN_TT_master_state                   */
+
+  uint32_t SyncState;        /*!< Specifies the type of the TT synchronization state.
+                                  This parameter can be a value of @ref FDCAN_TT_sync_state                     */
+
+  uint32_t GTimeQuality;     /*!< Specifies the Quality of Global Time Phase.
+                                  This parameter is only relevant in Level 0 and Level 2, otherwise fixed to 0.
+                                  This parameter can be:
+                                   - 0 : Global time not valid
+                                   - 1 : Global time in phase with Time Master                                  */
+
+  uint32_t ClockQuality;     /*!< Specifies the Quality of Clock Speed.
+                                  This parameter is only relevant in Level 0 and Level 2, otherwise fixed to 1.
+                                  This parameter can be:
+                                   - 0 : Local clock speed not synchronized to Time Master clock speed
+                                   - 1 : Synchronization Deviation = SDL                                        */
+
+  uint32_t RefTrigOffset;    /*!< Specifies the Actual Reference Trigger Offset Value.
+                                  This parameter can be a number between 0 and 0xFF                             */
+
+  uint32_t GTimeDiscPending; /*!< Specifies the Global Time Discontinuity State.
+                                  This parameter can be:
+                                   - 0 : No global time preset pending
+                                   - 1 : Node waits for the global time preset to take effect                   */
+
+  uint32_t GapFinished;      /*!< Specifies whether a Gap is finished.
+                                  This parameter can be:
+                                   - 0 : Reset at the end of each reference message
+                                   - 1 : Gap finished                                                           */
+
+  uint32_t MasterPriority;   /*!< Specifies the Priority of actual Time Master.
+                                  This parameter can be a number between 0 and 0x7                              */
+
+  uint32_t GapStarted;       /*!< Specifies whether a Gap is started.
+                                  This parameter can be:
+                                   - 0 : No Gap in schedule
+                                   - 1 : Gap time after Basic Cycle has started                                 */
+
+  uint32_t WaitForEvt;       /*!< Specifies whether a Gap is annouced.
+                                  This parameter can be:
+                                   - 0 : No Gap announced, reset by a reference message with Next_is_Gap = 0
+                                   - 1 : Reference message with Next_is_Gap = 1 received                        */
+
+  uint32_t AppWdgEvt;        /*!< Specifies the Application Watchdog State.
+                                  This parameter can be:
+                                   - 0 : Application Watchdog served in time
+                                   - 1 : Failed to serve Application Watchdog in time                           */
+
+  uint32_t ECSPending;       /*!< Specifies the External Clock Synchronization State.
+                                  This parameter can be:
+                                   - 0 : No external clock synchronization pending
+                                   - 1 : Node waits for external clock synchronization to take effect           */
+
+  uint32_t PhaseLock;        /*!< Specifies the Phase Lock State.
+                                  This parameter can be:
+                                   - 0 : Phase outside range
+                                   - 1 : Phase inside range                                                     */
+
+} FDCAN_TTOperationStatusTypeDef;
+
+/**
+  * @brief  FDCAN Message RAM blocks
+  */
+typedef struct
+{
+  uint32_t StandardFilterSA; /*!< Specifies the Standard Filter List Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t ExtendedFilterSA; /*!< Specifies the Extended Filter List Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t RxFIFO0SA;        /*!< Specifies the Rx FIFO 0 Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t RxFIFO1SA;        /*!< Specifies the Rx FIFO 1 Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t RxBufferSA;       /*!< Specifies the Rx Buffer Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t TxEventFIFOSA;    /*!< Specifies the Tx Event FIFO Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t TxBufferSA;       /*!< Specifies the Tx Buffers Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t TxFIFOQSA;        /*!< Specifies the Tx FIFO/Queue Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t TTMemorySA;       /*!< Specifies the Trigger Memory Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t EndAddress;       /*!< Specifies the End Address of the allocated RAM.
+                                  This parameter must be a 32-bit word address      */
+
+} FDCAN_MsgRamAddressTypeDef;
+
+/**
+  * @brief  FDCAN handle structure definition
+  */
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+typedef struct __FDCAN_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+{
+  FDCAN_GlobalTypeDef         *Instance;        /*!< Register base address     */
+
+  TTCAN_TypeDef               *ttcan;           /*!< TT register base address  */
+
+  FDCAN_InitTypeDef           Init;             /*!< FDCAN required parameters */
+
+  FDCAN_MsgRamAddressTypeDef  msgRam;           /*!< FDCAN Message RAM blocks  */
+
+  uint32_t                    LatestTxFifoQRequest; /*!< FDCAN Tx buffer index
+                                               of latest Tx FIFO/Queue request */
+
+  __IO HAL_FDCAN_StateTypeDef State;            /*!< FDCAN communication state */
+
+  HAL_LockTypeDef             Lock;             /*!< FDCAN locking object      */
+
+  __IO uint32_t               ErrorCode;        /*!< FDCAN Error code          */
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+  void (* ClockCalibrationCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs);         /*!< FDCAN Clock Calibration callback          */
+  void (* TxEventFifoCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs);                 /*!< FDCAN Tx Event Fifo callback              */
+  void (* RxFifo0Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs);                         /*!< FDCAN Rx Fifo 0 callback                  */
+  void (* RxFifo1Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs);                         /*!< FDCAN Rx Fifo 1 callback                  */
+  void (* TxFifoEmptyCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                          /*!< FDCAN Tx Fifo Empty callback              */
+  void (* TxBufferCompleteCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);             /*!< FDCAN Tx Buffer complete callback         */
+  void (* TxBufferAbortCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);                /*!< FDCAN Tx Buffer abort callback            */
+  void (* RxBufferNewMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                   /*!< FDCAN Rx Buffer New Message callback      */
+  void (* HighPriorityMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                  /*!< FDCAN High priority message callback      */
+  void (* TimestampWraparoundCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                  /*!< FDCAN Timestamp wraparound callback       */
+  void (* TimeoutOccurredCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                      /*!< FDCAN Timeout occurred callback           */
+  void (* ErrorCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                                /*!< FDCAN Error callback                      */
+  void (* ErrorStatusCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs);                 /*!< FDCAN Error status callback               */
+  void (* TT_ScheduleSyncCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs);             /*!< FDCAN T Schedule Synchronization callback */
+  void (* TT_TimeMarkCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs);                  /*!< FDCAN TT Time Mark callback               */
+  void (* TT_StopWatchCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount); /*!< FDCAN TT Stop Watch callback              */
+  void (* TT_GlobalTimeCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs);                /*!< FDCAN TT Global Time callback             */
+
+  void (* MspInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                              /*!< FDCAN Msp Init callback                   */
+  void (* MspDeInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                            /*!< FDCAN Msp DeInit callback                 */
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+} FDCAN_HandleTypeDef;
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+/**
+  * @brief  HAL FDCAN common Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_FDCAN_TX_FIFO_EMPTY_CB_ID        = 0x00U, /*!< FDCAN Tx Fifo Empty callback ID         */
+  HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID    = 0x01U, /*!< FDCAN Rx buffer new message callback ID */
+  HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID    = 0x02U, /*!< FDCAN High priority message callback ID */
+  HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID = 0x03U, /*!< FDCAN Timestamp wraparound callback ID  */
+  HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID     = 0x04U, /*!< FDCAN Timeout occurred callback ID      */
+  HAL_FDCAN_ERROR_CALLBACK_CB_ID       = 0x05U, /*!< FDCAN Error callback ID                 */
+
+  HAL_FDCAN_MSPINIT_CB_ID              = 0x06U, /*!< FDCAN MspInit callback ID               */
+  HAL_FDCAN_MSPDEINIT_CB_ID            = 0x07U, /*!< FDCAN MspDeInit callback ID             */
+
+} HAL_FDCAN_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL FDCAN Callback pointer definition
+  */
+typedef  void (*pFDCAN_CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan);                                                     /*!< pointer to a common FDCAN callback function                    */
+typedef  void (*pFDCAN_ClockCalibrationCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs);         /*!< pointer to Clock Calibration FDCAN callback function           */
+typedef  void (*pFDCAN_TxEventFifoCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs);                 /*!< pointer to Tx event Fifo FDCAN callback function               */
+typedef  void (*pFDCAN_RxFifo0CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs);                         /*!< pointer to Rx Fifo 0 FDCAN callback function                   */
+typedef  void (*pFDCAN_RxFifo1CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs);                         /*!< pointer to Rx Fifo 1 FDCAN callback function                   */
+typedef  void (*pFDCAN_TxBufferCompleteCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);             /*!< pointer to Tx Buffer complete FDCAN callback function          */
+typedef  void (*pFDCAN_TxBufferAbortCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);                /*!< pointer to Tx Buffer abort FDCAN callback function             */
+typedef  void (*pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs);                 /*!< pointer to Error Status callback function                      */
+typedef  void (*pFDCAN_TT_ScheduleSyncCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs);             /*!< pointer to TT Schedule Synchronization FDCAN callback function */
+typedef  void (*pFDCAN_TT_TimeMarkCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs);                  /*!< pointer to TT Time Mark FDCAN callback function                */
+typedef  void (*pFDCAN_TT_StopWatchCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount); /*!< pointer to TT Stop Watch FDCAN callback function               */
+typedef  void (*pFDCAN_TT_GlobalTimeCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs);                /*!< pointer to TT Global Time FDCAN callback function              */
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FDCAN_Exported_Constants FDCAN Exported Constants
+  * @{
+  */
+
+/** @defgroup HAL_FDCAN_Error_Code HAL FDCAN Error Code
+  * @{
+  */
+#define HAL_FDCAN_ERROR_NONE            ((uint32_t)0x00000000U) /*!< No error                                                               */
+#define HAL_FDCAN_ERROR_TIMEOUT         ((uint32_t)0x00000001U) /*!< Timeout error                                                          */
+#define HAL_FDCAN_ERROR_NOT_INITIALIZED ((uint32_t)0x00000002U) /*!< Peripheral not initialized                                             */
+#define HAL_FDCAN_ERROR_NOT_READY       ((uint32_t)0x00000004U) /*!< Peripheral not ready                                                   */
+#define HAL_FDCAN_ERROR_NOT_STARTED     ((uint32_t)0x00000008U) /*!< Peripheral not started                                                 */
+#define HAL_FDCAN_ERROR_NOT_SUPPORTED   ((uint32_t)0x00000010U) /*!< Mode not supported                                                     */
+#define HAL_FDCAN_ERROR_PARAM           ((uint32_t)0x00000020U) /*!< Parameter error                                                        */
+#define HAL_FDCAN_ERROR_PENDING         ((uint32_t)0x00000040U) /*!< Pending operation                                                      */
+#define HAL_FDCAN_ERROR_RAM_ACCESS      ((uint32_t)0x00000080U) /*!< Message RAM Access Failure                                             */
+#define HAL_FDCAN_ERROR_FIFO_EMPTY      ((uint32_t)0x00000100U) /*!< Put element in full FIFO                                               */
+#define HAL_FDCAN_ERROR_FIFO_FULL       ((uint32_t)0x00000200U) /*!< Get element from empty FIFO                                            */
+#define HAL_FDCAN_ERROR_LOG_OVERFLOW    FDCAN_IR_ELO            /*!< Overflow of CAN Error Logging Counter                                  */
+#define HAL_FDCAN_ERROR_RAM_WDG         FDCAN_IR_WDI            /*!< Message RAM Watchdog event occurred                                    */
+#define HAL_FDCAN_ERROR_PROTOCOL_ARBT   FDCAN_IR_PEA            /*!< Protocol Error in Arbitration Phase (Nominal Bit Time is used)         */
+#define HAL_FDCAN_ERROR_PROTOCOL_DATA   FDCAN_IR_PED            /*!< Protocol Error in Data Phase (Data Bit Time is used)                   */
+#define HAL_FDCAN_ERROR_RESERVED_AREA   FDCAN_IR_ARA            /*!< Access to Reserved Address                                             */
+#define HAL_FDCAN_ERROR_TT_GLOBAL_TIME  FDCAN_TTIR_GTE          /*!< Global Time Error : Synchronization deviation exceeded limit           */
+#define HAL_FDCAN_ERROR_TT_TX_UNDERFLOW FDCAN_TTIR_TXU          /*!< Tx Count Underflow : Less Tx trigger than expected in one matrix cycle */
+#define HAL_FDCAN_ERROR_TT_TX_OVERFLOW  FDCAN_TTIR_TXO          /*!< Tx Count Overflow : More Tx trigger than expected in one matrix cycle  */
+#define HAL_FDCAN_ERROR_TT_SCHEDULE1    FDCAN_TTIR_SE1          /*!< Scheduling error 1                                                     */
+#define HAL_FDCAN_ERROR_TT_SCHEDULE2    FDCAN_TTIR_SE2          /*!< Scheduling error 2                                                     */
+#define HAL_FDCAN_ERROR_TT_NO_INIT_REF  FDCAN_TTIR_IWT          /*!< No system startup due to missing reference message                     */
+#define HAL_FDCAN_ERROR_TT_NO_REF       FDCAN_TTIR_WT           /*!< Missing reference message                                              */
+#define HAL_FDCAN_ERROR_TT_APPL_WDG     FDCAN_TTIR_AW           /*!< Application watchdog not served in time                                */
+#define HAL_FDCAN_ERROR_TT_CONFIG       FDCAN_TTIR_CER          /*!< Error found in trigger list                                            */
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+#define HAL_FDCAN_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100U) /*!< Invalid Callback error                                                */
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_frame_format FDCAN Frame Format
+  * @{
+  */
+#define FDCAN_FRAME_CLASSIC   ((uint32_t)0x00000000U)                         /*!< Classic mode                      */
+#define FDCAN_FRAME_FD_NO_BRS ((uint32_t)FDCAN_CCCR_FDOE)                     /*!< FD mode without BitRate Switching */
+#define FDCAN_FRAME_FD_BRS    ((uint32_t)(FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE)) /*!< FD mode with BitRate Switching    */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_operating_mode FDCAN Operating Mode
+  * @{
+  */
+#define FDCAN_MODE_NORMAL               ((uint32_t)0x00000000U) /*!< Normal mode               */
+#define FDCAN_MODE_RESTRICTED_OPERATION ((uint32_t)0x00000001U) /*!< Restricted Operation mode */
+#define FDCAN_MODE_BUS_MONITORING       ((uint32_t)0x00000002U) /*!< Bus Monitoring mode       */
+#define FDCAN_MODE_INTERNAL_LOOPBACK    ((uint32_t)0x00000003U) /*!< Internal LoopBack mode    */
+#define FDCAN_MODE_EXTERNAL_LOOPBACK    ((uint32_t)0x00000004U) /*!< External LoopBack mode    */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_clock_calibration FDCAN Clock Calibration
+  * @{
+  */
+#define FDCAN_CLOCK_CALIBRATION_DISABLE ((uint32_t)0x00000000U) /*!< Disable Clock Calibration */
+#define FDCAN_CLOCK_CALIBRATION_ENABLE  ((uint32_t)0x00000001U) /*!< Enable Clock Calibration  */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_clock_divider FDCAN Clock Divider
+  * @{
+  */
+#define FDCAN_CLOCK_DIV1  ((uint32_t)0x00000000U) /*!< Divide kernel clock by 1  */
+#define FDCAN_CLOCK_DIV2  ((uint32_t)0x00010000U) /*!< Divide kernel clock by 2  */
+#define FDCAN_CLOCK_DIV4  ((uint32_t)0x00020000U) /*!< Divide kernel clock by 4  */
+#define FDCAN_CLOCK_DIV6  ((uint32_t)0x00030000U) /*!< Divide kernel clock by 6  */
+#define FDCAN_CLOCK_DIV8  ((uint32_t)0x00040000U) /*!< Divide kernel clock by 8  */
+#define FDCAN_CLOCK_DIV10 ((uint32_t)0x00050000U) /*!< Divide kernel clock by 10 */
+#define FDCAN_CLOCK_DIV12 ((uint32_t)0x00060000U) /*!< Divide kernel clock by 12 */
+#define FDCAN_CLOCK_DIV14 ((uint32_t)0x00070000U) /*!< Divide kernel clock by 14 */
+#define FDCAN_CLOCK_DIV16 ((uint32_t)0x00080000U) /*!< Divide kernel clock by 16 */
+#define FDCAN_CLOCK_DIV18 ((uint32_t)0x00090000U) /*!< Divide kernel clock by 18 */
+#define FDCAN_CLOCK_DIV20 ((uint32_t)0x000A0000U) /*!< Divide kernel clock by 20 */
+#define FDCAN_CLOCK_DIV22 ((uint32_t)0x000B0000U) /*!< Divide kernel clock by 22 */
+#define FDCAN_CLOCK_DIV24 ((uint32_t)0x000C0000U) /*!< Divide kernel clock by 24 */
+#define FDCAN_CLOCK_DIV26 ((uint32_t)0x000D0000U) /*!< Divide kernel clock by 26 */
+#define FDCAN_CLOCK_DIV28 ((uint32_t)0x000E0000U) /*!< Divide kernel clock by 28 */
+#define FDCAN_CLOCK_DIV30 ((uint32_t)0x000F0000U) /*!< Divide kernel clock by 30 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_calibration_field_length FDCAN Calibration Field Length
+  * @{
+  */
+#define FDCAN_CALIB_FIELD_LENGTH_32 ((uint32_t)0x00000000U)       /*!< Calibration field length is 32 bits */
+#define FDCAN_CALIB_FIELD_LENGTH_64 ((uint32_t)FDCANCCU_CCFG_CFL) /*!< Calibration field length is 64 bits */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_calibration_state FDCAN Calibration State
+  * @{
+  */
+#define FDCAN_CLOCK_NOT_CALIBRATED       ((uint32_t)0x00000000U) /*!< Clock not calibrated       */
+#define FDCAN_CLOCK_BASIC_CALIBRATED     ((uint32_t)0x40000000U) /*!< Clock basic calibrated     */
+#define FDCAN_CLOCK_PRECISION_CALIBRATED ((uint32_t)0x80000000U) /*!< Clock precision calibrated */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_calibration_counter FDCAN Calibration Counter
+  * @{
+  */
+#define FDCAN_CALIB_TIME_QUANTA_COUNTER  ((uint32_t)0x00000000U) /*!< Time Quanta Counter             */
+#define FDCAN_CALIB_CLOCK_PERIOD_COUNTER ((uint32_t)0x00000001U) /*!< Oscillator Clock Period Counter */
+#define FDCAN_CALIB_WATCHDOG_COUNTER     ((uint32_t)0x00000002U) /*!< Calibration Watchdog Counter    */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_data_field_size FDCAN Data Field Size
+  * @{
+  */
+#define FDCAN_DATA_BYTES_8  ((uint32_t)0x00000004U) /*!< 8 bytes data field  */
+#define FDCAN_DATA_BYTES_12 ((uint32_t)0x00000005U) /*!< 12 bytes data field */
+#define FDCAN_DATA_BYTES_16 ((uint32_t)0x00000006U) /*!< 16 bytes data field */
+#define FDCAN_DATA_BYTES_20 ((uint32_t)0x00000007U) /*!< 20 bytes data field */
+#define FDCAN_DATA_BYTES_24 ((uint32_t)0x00000008U) /*!< 24 bytes data field */
+#define FDCAN_DATA_BYTES_32 ((uint32_t)0x0000000AU) /*!< 32 bytes data field */
+#define FDCAN_DATA_BYTES_48 ((uint32_t)0x0000000EU) /*!< 48 bytes data field */
+#define FDCAN_DATA_BYTES_64 ((uint32_t)0x00000012U) /*!< 64 bytes data field */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_txFifoQueue_Mode FDCAN Tx FIFO/Queue Mode
+  * @{
+  */
+#define FDCAN_TX_FIFO_OPERATION  ((uint32_t)0x00000000U)     /*!< FIFO mode  */
+#define FDCAN_TX_QUEUE_OPERATION ((uint32_t)FDCAN_TXBC_TFQM) /*!< Queue mode */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_id_type FDCAN ID Type
+  * @{
+  */
+#define FDCAN_STANDARD_ID ((uint32_t)0x00000000U) /*!< Standard ID element */
+#define FDCAN_EXTENDED_ID ((uint32_t)0x40000000U) /*!< Extended ID element */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_frame_type FDCAN Frame Type
+  * @{
+  */
+#define FDCAN_DATA_FRAME   ((uint32_t)0x00000000U)  /*!< Data frame   */
+#define FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U)  /*!< Remote frame */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_data_length_code FDCAN Data Length Code
+  * @{
+  */
+#define FDCAN_DLC_BYTES_0  ((uint32_t)0x00000000U) /*!< 0 bytes data field  */
+#define FDCAN_DLC_BYTES_1  ((uint32_t)0x00010000U) /*!< 1 bytes data field  */
+#define FDCAN_DLC_BYTES_2  ((uint32_t)0x00020000U) /*!< 2 bytes data field  */
+#define FDCAN_DLC_BYTES_3  ((uint32_t)0x00030000U) /*!< 3 bytes data field  */
+#define FDCAN_DLC_BYTES_4  ((uint32_t)0x00040000U) /*!< 4 bytes data field  */
+#define FDCAN_DLC_BYTES_5  ((uint32_t)0x00050000U) /*!< 5 bytes data field  */
+#define FDCAN_DLC_BYTES_6  ((uint32_t)0x00060000U) /*!< 6 bytes data field  */
+#define FDCAN_DLC_BYTES_7  ((uint32_t)0x00070000U) /*!< 7 bytes data field  */
+#define FDCAN_DLC_BYTES_8  ((uint32_t)0x00080000U) /*!< 8 bytes data field  */
+#define FDCAN_DLC_BYTES_12 ((uint32_t)0x00090000U) /*!< 12 bytes data field */
+#define FDCAN_DLC_BYTES_16 ((uint32_t)0x000A0000U) /*!< 16 bytes data field */
+#define FDCAN_DLC_BYTES_20 ((uint32_t)0x000B0000U) /*!< 20 bytes data field */
+#define FDCAN_DLC_BYTES_24 ((uint32_t)0x000C0000U) /*!< 24 bytes data field */
+#define FDCAN_DLC_BYTES_32 ((uint32_t)0x000D0000U) /*!< 32 bytes data field */
+#define FDCAN_DLC_BYTES_48 ((uint32_t)0x000E0000U) /*!< 48 bytes data field */
+#define FDCAN_DLC_BYTES_64 ((uint32_t)0x000F0000U) /*!< 64 bytes data field */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_error_state_indicator FDCAN Error State Indicator
+  * @{
+  */
+#define FDCAN_ESI_ACTIVE  ((uint32_t)0x00000000U) /*!< Transmitting node is error active  */
+#define FDCAN_ESI_PASSIVE ((uint32_t)0x80000000U) /*!< Transmitting node is error passive */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_bit_rate_switching FDCAN Bit Rate Switching
+  * @{
+  */
+#define FDCAN_BRS_OFF ((uint32_t)0x00000000U) /*!< FDCAN frames transmitted/received without bit rate switching */
+#define FDCAN_BRS_ON  ((uint32_t)0x00100000U) /*!< FDCAN frames transmitted/received with bit rate switching    */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_format FDCAN format
+  * @{
+  */
+#define FDCAN_CLASSIC_CAN ((uint32_t)0x00000000U) /*!< Frame transmitted/received in Classic CAN format */
+#define FDCAN_FD_CAN      ((uint32_t)0x00200000U) /*!< Frame transmitted/received in FDCAN format       */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_EFC FDCAN Event FIFO control
+  * @{
+  */
+#define FDCAN_NO_TX_EVENTS    ((uint32_t)0x00000000U) /*!< Do not store Tx events */
+#define FDCAN_STORE_TX_EVENTS ((uint32_t)0x00800000U) /*!< Store Tx events        */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_filter_type FDCAN Filter Type
+  * @{
+  */
+#define FDCAN_FILTER_RANGE         ((uint32_t)0x00000000U) /*!< Range filter from FilterID1 to FilterID2                        */
+#define FDCAN_FILTER_DUAL          ((uint32_t)0x00000001U) /*!< Dual ID filter for FilterID1 or FilterID2                       */
+#define FDCAN_FILTER_MASK          ((uint32_t)0x00000002U) /*!< Classic filter: FilterID1 = filter, FilterID2 = mask            */
+#define FDCAN_FILTER_RANGE_NO_EIDM ((uint32_t)0x00000003U) /*!< Range filter from FilterID1 to FilterID2, EIDM mask not applied */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_filter_config FDCAN Filter Configuration
+  * @{
+  */
+#define FDCAN_FILTER_DISABLE       ((uint32_t)0x00000000U) /*!< Disable filter element                                    */
+#define FDCAN_FILTER_TO_RXFIFO0    ((uint32_t)0x00000001U) /*!< Store in Rx FIFO 0 if filter matches                      */
+#define FDCAN_FILTER_TO_RXFIFO1    ((uint32_t)0x00000002U) /*!< Store in Rx FIFO 1 if filter matches                      */
+#define FDCAN_FILTER_REJECT        ((uint32_t)0x00000003U) /*!< Reject ID if filter matches                               */
+#define FDCAN_FILTER_HP            ((uint32_t)0x00000004U) /*!< Set high priority if filter matches                       */
+#define FDCAN_FILTER_TO_RXFIFO0_HP ((uint32_t)0x00000005U) /*!< Set high priority and store in FIFO 0 if filter matches   */
+#define FDCAN_FILTER_TO_RXFIFO1_HP ((uint32_t)0x00000006U) /*!< Set high priority and store in FIFO 1 if filter matches   */
+#define FDCAN_FILTER_TO_RXBUFFER   ((uint32_t)0x00000007U) /*!< Store into Rx Buffer, configuration of FilterType ignored */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Tx_location FDCAN Tx Location
+  * @{
+  */
+#define FDCAN_TX_BUFFER0  ((uint32_t)0x00000001U) /*!< Add message to Tx Buffer 0  */
+#define FDCAN_TX_BUFFER1  ((uint32_t)0x00000002U) /*!< Add message to Tx Buffer 1  */
+#define FDCAN_TX_BUFFER2  ((uint32_t)0x00000004U) /*!< Add message to Tx Buffer 2  */
+#define FDCAN_TX_BUFFER3  ((uint32_t)0x00000008U) /*!< Add message to Tx Buffer 3  */
+#define FDCAN_TX_BUFFER4  ((uint32_t)0x00000010U) /*!< Add message to Tx Buffer 4  */
+#define FDCAN_TX_BUFFER5  ((uint32_t)0x00000020U) /*!< Add message to Tx Buffer 5  */
+#define FDCAN_TX_BUFFER6  ((uint32_t)0x00000040U) /*!< Add message to Tx Buffer 6  */
+#define FDCAN_TX_BUFFER7  ((uint32_t)0x00000080U) /*!< Add message to Tx Buffer 7  */
+#define FDCAN_TX_BUFFER8  ((uint32_t)0x00000100U) /*!< Add message to Tx Buffer 8  */
+#define FDCAN_TX_BUFFER9  ((uint32_t)0x00000200U) /*!< Add message to Tx Buffer 9  */
+#define FDCAN_TX_BUFFER10 ((uint32_t)0x00000400U) /*!< Add message to Tx Buffer 10 */
+#define FDCAN_TX_BUFFER11 ((uint32_t)0x00000800U) /*!< Add message to Tx Buffer 11 */
+#define FDCAN_TX_BUFFER12 ((uint32_t)0x00001000U) /*!< Add message to Tx Buffer 12 */
+#define FDCAN_TX_BUFFER13 ((uint32_t)0x00002000U) /*!< Add message to Tx Buffer 13 */
+#define FDCAN_TX_BUFFER14 ((uint32_t)0x00004000U) /*!< Add message to Tx Buffer 14 */
+#define FDCAN_TX_BUFFER15 ((uint32_t)0x00008000U) /*!< Add message to Tx Buffer 15 */
+#define FDCAN_TX_BUFFER16 ((uint32_t)0x00010000U) /*!< Add message to Tx Buffer 16 */
+#define FDCAN_TX_BUFFER17 ((uint32_t)0x00020000U) /*!< Add message to Tx Buffer 17 */
+#define FDCAN_TX_BUFFER18 ((uint32_t)0x00040000U) /*!< Add message to Tx Buffer 18 */
+#define FDCAN_TX_BUFFER19 ((uint32_t)0x00080000U) /*!< Add message to Tx Buffer 19 */
+#define FDCAN_TX_BUFFER20 ((uint32_t)0x00100000U) /*!< Add message to Tx Buffer 20 */
+#define FDCAN_TX_BUFFER21 ((uint32_t)0x00200000U) /*!< Add message to Tx Buffer 21 */
+#define FDCAN_TX_BUFFER22 ((uint32_t)0x00400000U) /*!< Add message to Tx Buffer 22 */
+#define FDCAN_TX_BUFFER23 ((uint32_t)0x00800000U) /*!< Add message to Tx Buffer 23 */
+#define FDCAN_TX_BUFFER24 ((uint32_t)0x01000000U) /*!< Add message to Tx Buffer 24 */
+#define FDCAN_TX_BUFFER25 ((uint32_t)0x02000000U) /*!< Add message to Tx Buffer 25 */
+#define FDCAN_TX_BUFFER26 ((uint32_t)0x04000000U) /*!< Add message to Tx Buffer 26 */
+#define FDCAN_TX_BUFFER27 ((uint32_t)0x08000000U) /*!< Add message to Tx Buffer 27 */
+#define FDCAN_TX_BUFFER28 ((uint32_t)0x10000000U) /*!< Add message to Tx Buffer 28 */
+#define FDCAN_TX_BUFFER29 ((uint32_t)0x20000000U) /*!< Add message to Tx Buffer 29 */
+#define FDCAN_TX_BUFFER30 ((uint32_t)0x40000000U) /*!< Add message to Tx Buffer 30 */
+#define FDCAN_TX_BUFFER31 ((uint32_t)0x80000000U) /*!< Add message to Tx Buffer 31 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Rx_location FDCAN Rx Location
+  * @{
+  */
+#define FDCAN_RX_FIFO0    ((uint32_t)0x00000040U) /*!< Get received message from Rx FIFO 0    */
+#define FDCAN_RX_FIFO1    ((uint32_t)0x00000041U) /*!< Get received message from Rx FIFO 1    */
+#define FDCAN_RX_BUFFER0  ((uint32_t)0x00000000U) /*!< Get received message from Rx Buffer 0  */
+#define FDCAN_RX_BUFFER1  ((uint32_t)0x00000001U) /*!< Get received message from Rx Buffer 1  */
+#define FDCAN_RX_BUFFER2  ((uint32_t)0x00000002U) /*!< Get received message from Rx Buffer 2  */
+#define FDCAN_RX_BUFFER3  ((uint32_t)0x00000003U) /*!< Get received message from Rx Buffer 3  */
+#define FDCAN_RX_BUFFER4  ((uint32_t)0x00000004U) /*!< Get received message from Rx Buffer 4  */
+#define FDCAN_RX_BUFFER5  ((uint32_t)0x00000005U) /*!< Get received message from Rx Buffer 5  */
+#define FDCAN_RX_BUFFER6  ((uint32_t)0x00000006U) /*!< Get received message from Rx Buffer 6  */
+#define FDCAN_RX_BUFFER7  ((uint32_t)0x00000007U) /*!< Get received message from Rx Buffer 7  */
+#define FDCAN_RX_BUFFER8  ((uint32_t)0x00000008U) /*!< Get received message from Rx Buffer 8  */
+#define FDCAN_RX_BUFFER9  ((uint32_t)0x00000009U) /*!< Get received message from Rx Buffer 9  */
+#define FDCAN_RX_BUFFER10 ((uint32_t)0x0000000AU) /*!< Get received message from Rx Buffer 10 */
+#define FDCAN_RX_BUFFER11 ((uint32_t)0x0000000BU) /*!< Get received message from Rx Buffer 11 */
+#define FDCAN_RX_BUFFER12 ((uint32_t)0x0000000CU) /*!< Get received message from Rx Buffer 12 */
+#define FDCAN_RX_BUFFER13 ((uint32_t)0x0000000DU) /*!< Get received message from Rx Buffer 13 */
+#define FDCAN_RX_BUFFER14 ((uint32_t)0x0000000EU) /*!< Get received message from Rx Buffer 14 */
+#define FDCAN_RX_BUFFER15 ((uint32_t)0x0000000FU) /*!< Get received message from Rx Buffer 15 */
+#define FDCAN_RX_BUFFER16 ((uint32_t)0x00000010U) /*!< Get received message from Rx Buffer 16 */
+#define FDCAN_RX_BUFFER17 ((uint32_t)0x00000011U) /*!< Get received message from Rx Buffer 17 */
+#define FDCAN_RX_BUFFER18 ((uint32_t)0x00000012U) /*!< Get received message from Rx Buffer 18 */
+#define FDCAN_RX_BUFFER19 ((uint32_t)0x00000013U) /*!< Get received message from Rx Buffer 19 */
+#define FDCAN_RX_BUFFER20 ((uint32_t)0x00000014U) /*!< Get received message from Rx Buffer 20 */
+#define FDCAN_RX_BUFFER21 ((uint32_t)0x00000015U) /*!< Get received message from Rx Buffer 21 */
+#define FDCAN_RX_BUFFER22 ((uint32_t)0x00000016U) /*!< Get received message from Rx Buffer 22 */
+#define FDCAN_RX_BUFFER23 ((uint32_t)0x00000017U) /*!< Get received message from Rx Buffer 23 */
+#define FDCAN_RX_BUFFER24 ((uint32_t)0x00000018U) /*!< Get received message from Rx Buffer 24 */
+#define FDCAN_RX_BUFFER25 ((uint32_t)0x00000019U) /*!< Get received message from Rx Buffer 25 */
+#define FDCAN_RX_BUFFER26 ((uint32_t)0x0000001AU) /*!< Get received message from Rx Buffer 26 */
+#define FDCAN_RX_BUFFER27 ((uint32_t)0x0000001BU) /*!< Get received message from Rx Buffer 27 */
+#define FDCAN_RX_BUFFER28 ((uint32_t)0x0000001CU) /*!< Get received message from Rx Buffer 28 */
+#define FDCAN_RX_BUFFER29 ((uint32_t)0x0000001DU) /*!< Get received message from Rx Buffer 29 */
+#define FDCAN_RX_BUFFER30 ((uint32_t)0x0000001EU) /*!< Get received message from Rx Buffer 30 */
+#define FDCAN_RX_BUFFER31 ((uint32_t)0x0000001FU) /*!< Get received message from Rx Buffer 31 */
+#define FDCAN_RX_BUFFER32 ((uint32_t)0x00000020U) /*!< Get received message from Rx Buffer 32 */
+#define FDCAN_RX_BUFFER33 ((uint32_t)0x00000021U) /*!< Get received message from Rx Buffer 33 */
+#define FDCAN_RX_BUFFER34 ((uint32_t)0x00000022U) /*!< Get received message from Rx Buffer 34 */
+#define FDCAN_RX_BUFFER35 ((uint32_t)0x00000023U) /*!< Get received message from Rx Buffer 35 */
+#define FDCAN_RX_BUFFER36 ((uint32_t)0x00000024U) /*!< Get received message from Rx Buffer 36 */
+#define FDCAN_RX_BUFFER37 ((uint32_t)0x00000025U) /*!< Get received message from Rx Buffer 37 */
+#define FDCAN_RX_BUFFER38 ((uint32_t)0x00000026U) /*!< Get received message from Rx Buffer 38 */
+#define FDCAN_RX_BUFFER39 ((uint32_t)0x00000027U) /*!< Get received message from Rx Buffer 39 */
+#define FDCAN_RX_BUFFER40 ((uint32_t)0x00000028U) /*!< Get received message from Rx Buffer 40 */
+#define FDCAN_RX_BUFFER41 ((uint32_t)0x00000029U) /*!< Get received message from Rx Buffer 41 */
+#define FDCAN_RX_BUFFER42 ((uint32_t)0x0000002AU) /*!< Get received message from Rx Buffer 42 */
+#define FDCAN_RX_BUFFER43 ((uint32_t)0x0000002BU) /*!< Get received message from Rx Buffer 43 */
+#define FDCAN_RX_BUFFER44 ((uint32_t)0x0000002CU) /*!< Get received message from Rx Buffer 44 */
+#define FDCAN_RX_BUFFER45 ((uint32_t)0x0000002DU) /*!< Get received message from Rx Buffer 45 */
+#define FDCAN_RX_BUFFER46 ((uint32_t)0x0000002EU) /*!< Get received message from Rx Buffer 46 */
+#define FDCAN_RX_BUFFER47 ((uint32_t)0x0000002FU) /*!< Get received message from Rx Buffer 47 */
+#define FDCAN_RX_BUFFER48 ((uint32_t)0x00000030U) /*!< Get received message from Rx Buffer 48 */
+#define FDCAN_RX_BUFFER49 ((uint32_t)0x00000031U) /*!< Get received message from Rx Buffer 49 */
+#define FDCAN_RX_BUFFER50 ((uint32_t)0x00000032U) /*!< Get received message from Rx Buffer 50 */
+#define FDCAN_RX_BUFFER51 ((uint32_t)0x00000033U) /*!< Get received message from Rx Buffer 51 */
+#define FDCAN_RX_BUFFER52 ((uint32_t)0x00000034U) /*!< Get received message from Rx Buffer 52 */
+#define FDCAN_RX_BUFFER53 ((uint32_t)0x00000035U) /*!< Get received message from Rx Buffer 53 */
+#define FDCAN_RX_BUFFER54 ((uint32_t)0x00000036U) /*!< Get received message from Rx Buffer 54 */
+#define FDCAN_RX_BUFFER55 ((uint32_t)0x00000037U) /*!< Get received message from Rx Buffer 55 */
+#define FDCAN_RX_BUFFER56 ((uint32_t)0x00000038U) /*!< Get received message from Rx Buffer 56 */
+#define FDCAN_RX_BUFFER57 ((uint32_t)0x00000039U) /*!< Get received message from Rx Buffer 57 */
+#define FDCAN_RX_BUFFER58 ((uint32_t)0x0000003AU) /*!< Get received message from Rx Buffer 58 */
+#define FDCAN_RX_BUFFER59 ((uint32_t)0x0000003BU) /*!< Get received message from Rx Buffer 59 */
+#define FDCAN_RX_BUFFER60 ((uint32_t)0x0000003CU) /*!< Get received message from Rx Buffer 60 */
+#define FDCAN_RX_BUFFER61 ((uint32_t)0x0000003DU) /*!< Get received message from Rx Buffer 61 */
+#define FDCAN_RX_BUFFER62 ((uint32_t)0x0000003EU) /*!< Get received message from Rx Buffer 62 */
+#define FDCAN_RX_BUFFER63 ((uint32_t)0x0000003FU) /*!< Get received message from Rx Buffer 63 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_event_type FDCAN Event Type
+  * @{
+  */
+#define FDCAN_TX_EVENT             ((uint32_t)0x00400000U) /*!< Tx event                              */
+#define FDCAN_TX_IN_SPITE_OF_ABORT ((uint32_t)0x00800000U) /*!< Transmission in spite of cancellation */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_hp_msg_storage FDCAN High Priority Message Storage
+  * @{
+  */
+#define FDCAN_HP_STORAGE_NO_FIFO  ((uint32_t)0x00000000U) /*!< No FIFO selected         */
+#define FDCAN_HP_STORAGE_MSG_LOST ((uint32_t)0x00000040U) /*!< FIFO message lost        */
+#define FDCAN_HP_STORAGE_RXFIFO0  ((uint32_t)0x00000080U) /*!< Message stored in FIFO 0 */
+#define FDCAN_HP_STORAGE_RXFIFO1  ((uint32_t)0x000000C0U) /*!< Message stored in FIFO 1 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_protocol_error_code FDCAN protocol error code
+  * @{
+  */
+#define FDCAN_PROTOCOL_ERROR_NONE      ((uint32_t)0x00000000U) /*!< No error occurred         */
+#define FDCAN_PROTOCOL_ERROR_STUFF     ((uint32_t)0x00000001U) /*!< Stuff error               */
+#define FDCAN_PROTOCOL_ERROR_FORM      ((uint32_t)0x00000002U) /*!< Form error                */
+#define FDCAN_PROTOCOL_ERROR_ACK       ((uint32_t)0x00000003U) /*!< Acknowledge error         */
+#define FDCAN_PROTOCOL_ERROR_BIT1      ((uint32_t)0x00000004U) /*!< Bit 1 (recessive) error   */
+#define FDCAN_PROTOCOL_ERROR_BIT0      ((uint32_t)0x00000005U) /*!< Bit 0 (dominant) error    */
+#define FDCAN_PROTOCOL_ERROR_CRC       ((uint32_t)0x00000006U) /*!< CRC check sum error       */
+#define FDCAN_PROTOCOL_ERROR_NO_CHANGE ((uint32_t)0x00000007U) /*!< No change since last read */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_communication_state FDCAN communication state
+  * @{
+  */
+#define FDCAN_COM_STATE_SYNC ((uint32_t)0x00000000U) /*!< Node is synchronizing on CAN communication */
+#define FDCAN_COM_STATE_IDLE ((uint32_t)0x00000008U) /*!< Node is neither receiver nor transmitter   */
+#define FDCAN_COM_STATE_RX   ((uint32_t)0x00000010U) /*!< Node is operating as receiver              */
+#define FDCAN_COM_STATE_TX   ((uint32_t)0x00000018U) /*!< Node is operating as transmitter           */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_FIFO_watermark FDCAN FIFO watermark
+  * @{
+  */
+#define FDCAN_CFG_TX_EVENT_FIFO ((uint32_t)0x00000000U) /*!< Tx event FIFO */
+#define FDCAN_CFG_RX_FIFO0      ((uint32_t)0x00000001U) /*!< Rx FIFO0      */
+#define FDCAN_CFG_RX_FIFO1      ((uint32_t)0x00000002U) /*!< Rx FIFO1      */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Rx_FIFO_operation_mode FDCAN FIFO operation mode
+  * @{
+  */
+#define FDCAN_RX_FIFO_BLOCKING  ((uint32_t)0x00000000U) /*!< Rx FIFO blocking mode  */
+#define FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x80000000U) /*!< Rx FIFO overwrite mode */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Non_Matching_Frames FDCAN non-matching frames
+  * @{
+  */
+#define FDCAN_ACCEPT_IN_RX_FIFO0 ((uint32_t)0x00000000U) /*!< Accept in Rx FIFO 0 */
+#define FDCAN_ACCEPT_IN_RX_FIFO1 ((uint32_t)0x00000001U) /*!< Accept in Rx FIFO 1 */
+#define FDCAN_REJECT             ((uint32_t)0x00000002U) /*!< Reject              */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Reject_Remote_Frames FDCAN reject remote frames
+  * @{
+  */
+#define FDCAN_FILTER_REMOTE ((uint32_t)0x00000000U) /*!< Filter remote frames */
+#define FDCAN_REJECT_REMOTE ((uint32_t)0x00000001U) /*!< Reject all remote frames */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Interrupt_Line FDCAN interrupt line
+  * @{
+  */
+#define FDCAN_INTERRUPT_LINE0 ((uint32_t)0x00000001U) /*!< Interrupt Line 0 */
+#define FDCAN_INTERRUPT_LINE1 ((uint32_t)0x00000002U) /*!< Interrupt Line 1 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Timestamp FDCAN timestamp
+  * @{
+  */
+#define FDCAN_TIMESTAMP_INTERNAL ((uint32_t)0x00000001U) /*!< Timestamp counter value incremented according to TCP */
+#define FDCAN_TIMESTAMP_EXTERNAL ((uint32_t)0x00000002U) /*!< External timestamp counter value used                */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Timestamp_Prescaler FDCAN timestamp prescaler
+  * @{
+  */
+#define FDCAN_TIMESTAMP_PRESC_1  ((uint32_t)0x00000000U) /*!< Timestamp counter time unit in equal to CAN bit time                 */
+#define FDCAN_TIMESTAMP_PRESC_2  ((uint32_t)0x00010000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 2  */
+#define FDCAN_TIMESTAMP_PRESC_3  ((uint32_t)0x00020000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 3  */
+#define FDCAN_TIMESTAMP_PRESC_4  ((uint32_t)0x00030000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 4  */
+#define FDCAN_TIMESTAMP_PRESC_5  ((uint32_t)0x00040000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 5  */
+#define FDCAN_TIMESTAMP_PRESC_6  ((uint32_t)0x00050000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 6  */
+#define FDCAN_TIMESTAMP_PRESC_7  ((uint32_t)0x00060000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 7  */
+#define FDCAN_TIMESTAMP_PRESC_8  ((uint32_t)0x00070000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 8  */
+#define FDCAN_TIMESTAMP_PRESC_9  ((uint32_t)0x00080000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 9  */
+#define FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 10 */
+#define FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 11 */
+#define FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 12 */
+#define FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 13 */
+#define FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 14 */
+#define FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 15 */
+#define FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 16 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Timeout_Operation FDCAN timeout operation
+  * @{
+  */
+#define FDCAN_TIMEOUT_CONTINUOUS    ((uint32_t)0x00000000U) /*!< Timeout continuous operation        */
+#define FDCAN_TIMEOUT_TX_EVENT_FIFO ((uint32_t)0x00000002U) /*!< Timeout controlled by Tx Event FIFO */
+#define FDCAN_TIMEOUT_RX_FIFO0      ((uint32_t)0x00000004U) /*!< Timeout controlled by Rx FIFO 0     */
+#define FDCAN_TIMEOUT_RX_FIFO1      ((uint32_t)0x00000006U) /*!< Timeout controlled by Rx FIFO 1     */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_Reference_Message_Payload FDCAN TT reference message payload
+  * @{
+  */
+#define FDCAN_TT_REF_MESSAGE_NO_PAYLOAD  ((uint32_t)0x00000000U)      /*!< Reference message has no additional payload  */
+#define FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD ((uint32_t)FDCAN_TTRMC_RMPS) /*!< Additional payload is taken from Tx Buffer 0 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_Repeat_Factor FDCAN TT repeat factor
+  * @{
+  */
+#define FDCAN_TT_REPEAT_EVERY_CYCLE      ((uint32_t)0x00000000U) /*!< Trigger valid for all cycles   */
+#define FDCAN_TT_REPEAT_EVERY_2ND_CYCLE  ((uint32_t)0x00000002U) /*!< Trigger valid every 2dn cycle  */
+#define FDCAN_TT_REPEAT_EVERY_4TH_CYCLE  ((uint32_t)0x00000004U) /*!< Trigger valid every 4th cycle  */
+#define FDCAN_TT_REPEAT_EVERY_8TH_CYCLE  ((uint32_t)0x00000008U) /*!< Trigger valid every 8th cycle  */
+#define FDCAN_TT_REPEAT_EVERY_16TH_CYCLE ((uint32_t)0x00000010U) /*!< Trigger valid every 16th cycle */
+#define FDCAN_TT_REPEAT_EVERY_32ND_CYCLE ((uint32_t)0x00000020U) /*!< Trigger valid every 32nd cycle */
+#define FDCAN_TT_REPEAT_EVERY_64TH_CYCLE ((uint32_t)0x00000040U) /*!< Trigger valid every 64th cycle */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_Trigger_Type FDCAN TT trigger type
+  * @{
+  */
+#define FDCAN_TT_TX_REF_TRIGGER         ((uint32_t)0x00000000U) /*!< Transmit reference message in strictly time-triggered operation                                                     */
+#define FDCAN_TT_TX_REF_TRIGGER_GAP     ((uint32_t)0x00000001U) /*!< Transmit reference message in external event-synchronized time-triggered operation                                  */
+#define FDCAN_TT_TX_TRIGGER_SINGLE      ((uint32_t)0x00000002U) /*!< Start a single transmission in an exclusive time window                                                             */
+#define FDCAN_TT_TX_TRIGGER_CONTINUOUS  ((uint32_t)0x00000003U) /*!< Start a continuous transmission in an exclusive time window                                                         */
+#define FDCAN_TT_TX_TRIGGER_ARBITRATION ((uint32_t)0x00000004U) /*!< Start a transmission in an arbitration time window                                                                  */
+#define FDCAN_TT_TX_TRIGGER_MERGED      ((uint32_t)0x00000005U) /*!< Start a merged arbitration window                                                                                   */
+#define FDCAN_TT_WATCH_TRIGGER          ((uint32_t)0x00000006U) /*!< Check for missing reference messages in strictly time-triggered operation                                           */
+#define FDCAN_TT_WATCH_TRIGGER_GAP      ((uint32_t)0x00000007U) /*!< Check for missing reference messages in external event-synchronized time-triggered operation                        */
+#define FDCAN_TT_RX_TRIGGER             ((uint32_t)0x00000008U) /*!< Check for the reception of periodic messages in exclusive time windows                                              */
+#define FDCAN_TT_TIME_BASE_TRIGGER      ((uint32_t)0x00000009U) /*!< Generate internal/external events depending on TmEventInt/TmEventExt configuration                                  */
+#define FDCAN_TT_END_OF_LIST            ((uint32_t)0x0000000AU) /*!< Illegal trigger, to be assigned to the unused triggers after a FDCAN_TT_WATCH_TRIGGER or FDCAN_TT_WATCH_TRIGGER_GAP */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_Time_Mark_Event_Internal FDCAN TT time mark event internal
+  * @{
+  */
+#define FDCAN_TT_TM_NO_INTERNAL_EVENT  ((uint32_t)0x00000000U) /*!< No action                                               */
+#define FDCAN_TT_TM_GEN_INTERNAL_EVENT ((uint32_t)0x00000020U) /*!< Internal event is generated when trigger becomes active */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_Time_Mark_Event_External FDCAN TT time mark event external
+  * @{
+  */
+#define FDCAN_TT_TM_NO_EXTERNAL_EVENT  ((uint32_t)0x00000000U) /*!< No action                                                       */
+#define FDCAN_TT_TM_GEN_EXTERNAL_EVENT ((uint32_t)0x00000010U) /*!< External event (pulse) is generated when trigger becomes active */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_operation_mode FDCAN Operation Mode
+  * @{
+  */
+#define FDCAN_TT_COMMUNICATION_LEVEL1    ((uint32_t)0x00000001U) /*!< Time triggered communication, level 1 */
+#define FDCAN_TT_COMMUNICATION_LEVEL2    ((uint32_t)0x00000002U) /*!< Time triggered communication, level 2 */
+#define FDCAN_TT_COMMUNICATION_LEVEL0    ((uint32_t)0x00000003U) /*!< Time triggered communication, level 0 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_operation FDCAN TT Operation
+  * @{
+  */
+#define FDCAN_STRICTLY_TT_OPERATION     ((uint32_t)0x00000000U)     /*!< Strictly time-triggered operation                    */
+#define FDCAN_EXT_EVT_SYNC_TT_OPERATION ((uint32_t)FDCAN_TTOCF_GEN) /*!< External event-synchronized time-triggered operation */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_time_master FDCAN TT Time Master
+  * @{
+  */
+#define FDCAN_TT_SLAVE            ((uint32_t)0x00000000U)    /*!< Time slave            */
+#define FDCAN_TT_POTENTIAL_MASTER ((uint32_t)FDCAN_TTOCF_TM) /*!< Potential time master */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_external_clk_sync FDCAN TT External Clock Synchronization
+  * @{
+  */
+#define FDCAN_TT_EXT_CLK_SYNC_DISABLE ((uint32_t)0x00000000U)      /*!< External clock synchronization in Level 0,2 disabled */
+#define FDCAN_TT_EXT_CLK_SYNC_ENABLE  ((uint32_t)FDCAN_TTOCF_EECS) /*!< External clock synchronization in Level 0,2 enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_global_time_filtering FDCAN TT Global Time Filtering
+  * @{
+  */
+#define FDCAN_TT_GLOB_TIME_FILT_DISABLE ((uint32_t)0x00000000U)      /*!< Global time filtering in Level 0,2 disabled */
+#define FDCAN_TT_GLOB_TIME_FILT_ENABLE  ((uint32_t)FDCAN_TTOCF_EGTF) /*!< Global time filtering in Level 0,2 enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_auto_clk_calibration FDCAN TT Automatic Clock Calibration
+  * @{
+  */
+#define FDCAN_TT_AUTO_CLK_CALIB_DISABLE ((uint32_t)0x00000000U)     /*!< Automatic clock calibration in Level 0,2 disabled */
+#define FDCAN_TT_AUTO_CLK_CALIB_ENABLE  ((uint32_t)FDCAN_TTOCF_ECC) /*!< Automatic clock calibration in Level 0,2 enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_event_trig_polarity FDCAN TT Event Trigger Polarity
+  * @{
+  */
+#define FDCAN_TT_EVT_TRIG_POL_RISING  ((uint32_t)0x00000000U)      /*!< Rising edge trigger  */
+#define FDCAN_TT_EVT_TRIG_POL_FALLING ((uint32_t)FDCAN_TTOCF_EVTP) /*!< Falling edge trigger */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_basic_cycle_number FDCAN TT Basic Cycle Number
+  * @{
+  */
+#define FDCAN_TT_CYCLES_PER_MATRIX_1  ((uint32_t)0x00000000U) /*!< 1 Basic Cycle per Matrix   */
+#define FDCAN_TT_CYCLES_PER_MATRIX_2  ((uint32_t)0x00000001U) /*!< 2 Basic Cycles per Matrix  */
+#define FDCAN_TT_CYCLES_PER_MATRIX_4  ((uint32_t)0x00000003U) /*!< 4 Basic Cycles per Matrix  */
+#define FDCAN_TT_CYCLES_PER_MATRIX_8  ((uint32_t)0x00000007U) /*!< 8 Basic Cycles per Matrix  */
+#define FDCAN_TT_CYCLES_PER_MATRIX_16 ((uint32_t)0x0000000FU) /*!< 16 Basic Cycles per Matrix */
+#define FDCAN_TT_CYCLES_PER_MATRIX_32 ((uint32_t)0x0000001FU) /*!< 32 Basic Cycles per Matrix */
+#define FDCAN_TT_CYCLES_PER_MATRIX_64 ((uint32_t)0x0000003FU) /*!< 64 Basic Cycles per Matrix */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_cycle_start_sync FDCAN TT Cycle Start Sync
+  * @{
+  */
+#define FDCAN_TT_NO_SYNC_PULSE          ((uint32_t)0x00000000U) /*!< No sync pulse                      */
+#define FDCAN_TT_SYNC_BASIC_CYCLE_START ((uint32_t)0x00000040U) /*!< Sync pulse at start of basic cycle */
+#define FDCAN_TT_SYNC_MATRIX_START      ((uint32_t)0x00000080U) /*!< Sync pulse at start of matrix      */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_stop_watch_trig_selection FDCAN TT Stop Watch Trigger Selection
+  * @{
+  */
+#define FDCAN_TT_STOP_WATCH_TRIGGER_0 ((uint32_t)0x00000000U) /*!< TIM2 selected as stop watch trigger  */
+#define FDCAN_TT_STOP_WATCH_TRIGGER_1 ((uint32_t)0x00000001U) /*!< TIM3 selected as stop watch trigger  */
+#define FDCAN_TT_STOP_WATCH_TRIGGER_2 ((uint32_t)0x00000002U) /*!< ETH selected as stop watch trigger   */
+#define FDCAN_TT_STOP_WATCH_TRIGGER_3 ((uint32_t)0x00000003U) /*!< HRTIM selected as stop watch trigger */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_event_trig_selection FDCAN TT Event Trigger Selection
+  * @{
+  */
+#define FDCAN_TT_EVENT_TRIGGER_0 ((uint32_t)0x00000000U) /*!< TIM2 selected as event trigger  */
+#define FDCAN_TT_EVENT_TRIGGER_1 ((uint32_t)0x00000010U) /*!< TIM3 selected as event trigger  */
+#define FDCAN_TT_EVENT_TRIGGER_2 ((uint32_t)0x00000020U) /*!< ETH selected as event trigger   */
+#define FDCAN_TT_EVENT_TRIGGER_3 ((uint32_t)0x00000030U) /*!< HRTIM selected as event trigger */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_stop_watch_source FDCAN TT Stop Watch Source
+  * @{
+  */
+#define FDCAN_TT_STOP_WATCH_DISABLED    ((uint32_t)0x00000000U) /*!< Stop Watch disabled                                                        */
+#define FDCAN_TT_STOP_WATCH_CYCLE_TIME  ((uint32_t)0x00000008U) /*!< Actual value of cycle time is copied to Capture Time register (TTCPT.SWV)  */
+#define FDCAN_TT_STOP_WATCH_LOCAL_TIME  ((uint32_t)0x00000010U) /*!< Actual value of local time is copied to Capture Time register (TTCPT.SWV)  */
+#define FDCAN_TT_STOP_WATCH_GLOBAL_TIME ((uint32_t)0x00000018U) /*!< Actual value of global time is copied to Capture Time register (TTCPT.SWV) */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_stop_watch_polarity FDCAN TT Stop Watch Polarity
+  * @{
+  */
+#define FDCAN_TT_STOP_WATCH_RISING  ((uint32_t)0x00000000U) /*!< Selected stop watch source is captured at rising edge of fdcan1_swt  */
+#define FDCAN_TT_STOP_WATCH_FALLING ((uint32_t)0x00000004U) /*!< Selected stop watch source is captured at falling edge of fdcan1_swt */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_time_mark_source FDCAN TT Time Mark Source
+  * @{
+  */
+#define FDCAN_TT_REG_TIMEMARK_DIABLED  ((uint32_t)0x00000000U) /*!< No Register Time Mark Interrupt generated               */
+#define FDCAN_TT_REG_TIMEMARK_CYC_TIME ((uint32_t)0x00000040U) /*!< Register Time Mark Interrupt if Time Mark = cycle time  */
+#define FDCAN_TT_REG_TIMEMARK_LOC_TIME ((uint32_t)0x00000080U) /*!< Register Time Mark Interrupt if Time Mark = local time  */
+#define FDCAN_TT_REG_TIMEMARK_GLO_TIME ((uint32_t)0x000000C0U) /*!< Register Time Mark Interrupt if Time Mark = global time */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_error_level FDCAN TT Error Level
+  * @{
+  */
+#define FDCAN_TT_NO_ERROR     ((uint32_t)0x00000000U) /*!< Severity 0 - No Error     */
+#define FDCAN_TT_WARNING      ((uint32_t)0x00000001U) /*!< Severity 1 - Warning      */
+#define FDCAN_TT_ERROR        ((uint32_t)0x00000002U) /*!< Severity 2 - Error        */
+#define FDCAN_TT_SEVERE_ERROR ((uint32_t)0x00000003U) /*!< Severity 3 - Severe Error */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_master_state FDCAN TT Master State
+  * @{
+  */
+#define FDCAN_TT_MASTER_OFF          ((uint32_t)0x00000000U) /*!< Master_Off, no master properties relevant */
+#define FDCAN_TT_TIME_SLAVE          ((uint32_t)0x00000004U) /*!< Operating as Time Slave                   */
+#define FDCAN_TT_BACKUP_TIME_MASTER  ((uint32_t)0x00000008U) /*!< Operating as Backup Time Master           */
+#define FDCAN_TT_CURRENT_TIME_MASTER ((uint32_t)0x0000000CU) /*!< Operating as current Time Master          */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_sync_state FDCAN TT Synchronization State
+  * @{
+  */
+#define FDCAN_TT_OUT_OF_SYNC   ((uint32_t)0x00000000U) /*!< Out of Synchronization         */
+#define FDCAN_TT_SYNCHRONIZING ((uint32_t)0x00000010U) /*!< Synchronizing to communication */
+#define FDCAN_TT_IN_GAP        ((uint32_t)0x00000020U) /*!< Schedule suspended by Gap      */
+#define FDCAN_TT_IN_SCHEDULE   ((uint32_t)0x00000030U) /*!< Synchronized to schedule       */
+/**
+  * @}
+  */
+
+/** @defgroup Interrupt_Masks Interrupt masks
+  * @{
+  */
+#define FDCAN_IR_MASK ((uint32_t)0x3FCFFFFFU) /*!< FDCAN interrupts mask */
+#define CCU_IR_MASK   ((uint32_t)0xC0000000U) /*!< CCU interrupts mask   */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_flags FDCAN Flags
+  * @{
+  */
+#define FDCAN_FLAG_TX_COMPLETE             FDCAN_IR_TC             /*!< Transmission Completed                                */
+#define FDCAN_FLAG_TX_ABORT_COMPLETE       FDCAN_IR_TCF            /*!< Transmission Cancellation Finished                    */
+#define FDCAN_FLAG_TX_FIFO_EMPTY           FDCAN_IR_TFE            /*!< Tx FIFO Empty                                         */
+#define FDCAN_FLAG_RX_HIGH_PRIORITY_MSG    FDCAN_IR_HPM            /*!< High priority message received                        */
+#define FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE   FDCAN_IR_DRX            /*!< At least one received message stored into a Rx Buffer */
+#define FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST    FDCAN_IR_TEFL           /*!< Tx Event FIFO element lost                            */
+#define FDCAN_FLAG_TX_EVT_FIFO_FULL        FDCAN_IR_TEFF           /*!< Tx Event FIFO full                                    */
+#define FDCAN_FLAG_TX_EVT_FIFO_WATERMARK   FDCAN_IR_TEFW           /*!< Tx Event FIFO fill level reached watermark            */
+#define FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA    FDCAN_IR_TEFN           /*!< Tx Handler wrote Tx Event FIFO element                */
+#define FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST   FDCAN_IR_RF0L           /*!< Rx FIFO 0 message lost                                */
+#define FDCAN_FLAG_RX_FIFO0_FULL           FDCAN_IR_RF0F           /*!< Rx FIFO 0 full                                        */
+#define FDCAN_FLAG_RX_FIFO0_WATERMARK      FDCAN_IR_RF0W           /*!< Rx FIFO 0 fill level reached watermark                */
+#define FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE    FDCAN_IR_RF0N           /*!< New message written to Rx FIFO 0                      */
+#define FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST   FDCAN_IR_RF1L           /*!< Rx FIFO 1 message lost                                */
+#define FDCAN_FLAG_RX_FIFO1_FULL           FDCAN_IR_RF1F           /*!< Rx FIFO 1 full                                        */
+#define FDCAN_FLAG_RX_FIFO1_WATERMARK      FDCAN_IR_RF1W           /*!< Rx FIFO 1 fill level reached watermark                */
+#define FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE    FDCAN_IR_RF1N           /*!< New message written to Rx FIFO 1                      */
+#define FDCAN_FLAG_RAM_ACCESS_FAILURE      FDCAN_IR_MRAF           /*!< Message RAM access failure occurred                   */
+#define FDCAN_FLAG_ERROR_LOGGING_OVERFLOW  FDCAN_IR_ELO            /*!< Overflow of FDCAN Error Logging Counter occurred      */
+#define FDCAN_FLAG_ERROR_PASSIVE           FDCAN_IR_EP             /*!< Error_Passive status changed                          */
+#define FDCAN_FLAG_ERROR_WARNING           FDCAN_IR_EW             /*!< Error_Warning status changed                          */
+#define FDCAN_FLAG_BUS_OFF                 FDCAN_IR_BO             /*!< Bus_Off status changed                                */
+#define FDCAN_FLAG_RAM_WATCHDOG            FDCAN_IR_WDI            /*!< Message RAM Watchdog event due to missing READY       */
+#define FDCAN_FLAG_ARB_PROTOCOL_ERROR      FDCAN_IR_PEA            /*!< Protocol error in arbitration phase detected          */
+#define FDCAN_FLAG_DATA_PROTOCOL_ERROR     FDCAN_IR_PED            /*!< Protocol error in data phase detected                 */
+#define FDCAN_FLAG_RESERVED_ADDRESS_ACCESS FDCAN_IR_ARA            /*!< Access to reserved address occurred                   */
+#define FDCAN_FLAG_TIMESTAMP_WRAPAROUND    FDCAN_IR_TSW            /*!< Timestamp counter wrapped around                      */
+#define FDCAN_FLAG_TIMEOUT_OCCURRED        FDCAN_IR_TOO            /*!< Timeout reached                                       */
+#define FDCAN_FLAG_CALIB_STATE_CHANGED     (FDCANCCU_IR_CSC << 30) /*!< Clock calibration state changed                       */
+#define FDCAN_FLAG_CALIB_WATCHDOG_EVENT    (FDCANCCU_IR_CWE << 30) /*!< Clock calibration watchdog event occurred             */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Interrupts FDCAN Interrupts
+  * @{
+  */
+
+/** @defgroup FDCAN_Tx_Interrupts FDCAN Tx Interrupts
+  * @{
+  */
+#define FDCAN_IT_TX_COMPLETE           FDCAN_IE_TCE   /*!< Transmission Completed                                */
+#define FDCAN_IT_TX_ABORT_COMPLETE     FDCAN_IE_TCFE  /*!< Transmission Cancellation Finished                    */
+#define FDCAN_IT_TX_FIFO_EMPTY         FDCAN_IE_TFEE  /*!< Tx FIFO Empty                                         */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Rx_Interrupts FDCAN Rx Interrupts
+  * @{
+  */
+#define FDCAN_IT_RX_HIGH_PRIORITY_MSG  FDCAN_IE_HPME  /*!< High priority message received                        */
+#define FDCAN_IT_RX_BUFFER_NEW_MESSAGE FDCAN_IE_DRXE  /*!< At least one received message stored into a Rx Buffer */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Counter_Interrupts FDCAN Counter Interrupts
+  * @{
+  */
+#define FDCAN_IT_TIMESTAMP_WRAPAROUND  FDCAN_IE_TSWE  /*!< Timestamp counter wrapped around                      */
+#define FDCAN_IT_TIMEOUT_OCCURRED      FDCAN_IE_TOOE  /*!< Timeout reached                                       */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Clock_Calibration_Interrupts Clock Calibration Interrupts
+  * @{
+  */
+#define FDCAN_IT_CALIB_STATE_CHANGED  (FDCANCCU_IE_CSCE << 30) /*!< Clock calibration state changed           */
+#define FDCAN_IT_CALIB_WATCHDOG_EVENT (FDCANCCU_IE_CWEE << 30) /*!< Clock calibration watchdog event occurred */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Tx_Event_Fifo_Interrupts FDCAN Tx Event FIFO Interrupts
+  * @{
+  */
+#define FDCAN_IT_TX_EVT_FIFO_ELT_LOST  FDCAN_IE_TEFLE /*!< Tx Event FIFO element lost                 */
+#define FDCAN_IT_TX_EVT_FIFO_FULL      FDCAN_IE_TEFFE /*!< Tx Event FIFO full                         */
+#define FDCAN_IT_TX_EVT_FIFO_WATERMARK FDCAN_IE_TEFWE /*!< Tx Event FIFO fill level reached watermark */
+#define FDCAN_IT_TX_EVT_FIFO_NEW_DATA  FDCAN_IE_TEFNE /*!< Tx Handler wrote Tx Event FIFO element     */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Rx_Fifo0_Interrupts FDCAN Rx FIFO 0 Interrupts
+  * @{
+  */
+#define FDCAN_IT_RX_FIFO0_MESSAGE_LOST FDCAN_IE_RF0LE /*!< Rx FIFO 0 message lost                 */
+#define FDCAN_IT_RX_FIFO0_FULL         FDCAN_IE_RF0FE /*!< Rx FIFO 0 full                         */
+#define FDCAN_IT_RX_FIFO0_WATERMARK    FDCAN_IE_RF0WE /*!< Rx FIFO 0 fill level reached watermark */
+#define FDCAN_IT_RX_FIFO0_NEW_MESSAGE  FDCAN_IE_RF0NE /*!< New message written to Rx FIFO 0       */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Rx_Fifo1_Interrupts FDCAN Rx FIFO 1 Interrupts
+  * @{
+  */
+#define FDCAN_IT_RX_FIFO1_MESSAGE_LOST FDCAN_IE_RF1LE /*!< Rx FIFO 1 message lost                 */
+#define FDCAN_IT_RX_FIFO1_FULL         FDCAN_IE_RF1FE /*!< Rx FIFO 1 full                         */
+#define FDCAN_IT_RX_FIFO1_WATERMARK    FDCAN_IE_RF1WE /*!< Rx FIFO 1 fill level reached watermark */
+#define FDCAN_IT_RX_FIFO1_NEW_MESSAGE  FDCAN_IE_RF1NE /*!< New message written to Rx FIFO 1       */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Error_Interrupts FDCAN Error Interrupts
+  * @{
+  */
+#define FDCAN_IT_RAM_ACCESS_FAILURE      FDCAN_IE_MRAFE /*!< Message RAM access failure occurred              */
+#define FDCAN_IT_ERROR_LOGGING_OVERFLOW  FDCAN_IE_ELOE  /*!< Overflow of FDCAN Error Logging Counter occurred */
+#define FDCAN_IT_RAM_WATCHDOG            FDCAN_IE_WDIE  /*!< Message RAM Watchdog event due to missing READY  */
+#define FDCAN_IT_ARB_PROTOCOL_ERROR      FDCAN_IE_PEAE  /*!< Protocol error in arbitration phase detected     */
+#define FDCAN_IT_DATA_PROTOCOL_ERROR     FDCAN_IE_PEDE  /*!< Protocol error in data phase detected            */
+#define FDCAN_IT_RESERVED_ADDRESS_ACCESS FDCAN_IE_ARAE  /*!< Access to reserved address occurred              */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Error_Status_Interrupts FDCAN Error Status Interrupts
+  * @{
+  */
+#define FDCAN_IT_ERROR_PASSIVE FDCAN_IE_EPE /*!< Error_Passive status changed */
+#define FDCAN_IT_ERROR_WARNING FDCAN_IE_EWE /*!< Error_Warning status changed */
+#define FDCAN_IT_BUS_OFF       FDCAN_IE_BOE /*!< Bus_Off status changed       */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TTflags FDCAN TT Flags
+  * @{
+  */
+#define FDCAN_TT_FLAG_BASIC_CYCLE_START    FDCAN_TTIR_SBC  /*!< Start of Basic Cycle             */
+#define FDCAN_TT_FLAG_MATRIX_CYCLE_START   FDCAN_TTIR_SMC  /*!< Start of Matrix Cycle            */
+#define FDCAN_TT_FLAG_SYNC_MODE_CHANGE     FDCAN_TTIR_CSM  /*!< Change of Synchronization Mode   */
+#define FDCAN_TT_FLAG_START_OF_GAP         FDCAN_TTIR_SOG  /*!< Start of Gap                     */
+#define FDCAN_TT_FLAG_REG_TIME_MARK        FDCAN_TTIR_RTMI /*!< Register Time Mark Interrupt     */
+#define FDCAN_TT_FLAG_TRIG_TIME_MARK       FDCAN_TTIR_TTMI /*!< Trigger Time Mark Event Internal */
+#define FDCAN_TT_FLAG_STOP_WATCH           FDCAN_TTIR_SWE  /*!< Stop Watch Event                 */
+#define FDCAN_TT_FLAG_GLOBAL_TIME_WRAP     FDCAN_TTIR_GTW  /*!< Global Time Wrap                 */
+#define FDCAN_TT_FLAG_GLOBAL_TIME_DISC     FDCAN_TTIR_GTD  /*!< Global Time Discontinuity        */
+#define FDCAN_TT_FLAG_GLOBAL_TIME_ERROR    FDCAN_TTIR_GTE  /*!< Global Time Error                */
+#define FDCAN_TT_FLAG_TX_COUNT_UNDERFLOW   FDCAN_TTIR_TXU  /*!< Tx Count Underflow               */
+#define FDCAN_TT_FLAG_TX_COUNT_OVERFLOW    FDCAN_TTIR_TXO  /*!< Tx Count Overflow                */
+#define FDCAN_TT_FLAG_SCHEDULING_ERROR_1   FDCAN_TTIR_SE1  /*!< Scheduling Error 1               */
+#define FDCAN_TT_FLAG_SCHEDULING_ERROR_2   FDCAN_TTIR_SE2  /*!< Scheduling Error 2               */
+#define FDCAN_TT_FLAG_ERROR_LEVEL_CHANGE   FDCAN_TTIR_ELC  /*!< Error Level Changed              */
+#define FDCAN_TT_FLAG_INIT_WATCH_TRIGGER   FDCAN_TTIR_IWT  /*!< Initialization Watch Trigger     */
+#define FDCAN_TT_FLAG_WATCH_TRIGGER        FDCAN_TTIR_WT   /*!< Watch Trigger                    */
+#define FDCAN_TT_FLAG_APPLICATION_WATCHDOG FDCAN_TTIR_AW   /*!< Application Watchdog             */
+#define FDCAN_TT_FLAG_CONFIG_ERROR         FDCAN_TTIR_CER  /*!< Configuration Error              */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TTInterrupts FDCAN TT Interrupts
+  * @{
+  */
+
+/** @defgroup FDCAN_TTScheduleSynchronization_Interrupts FDCAN TT Schedule Synchronization Interrupts
+  * @{
+  */
+#define FDCAN_TT_IT_BASIC_CYCLE_START  FDCAN_TTIE_SBCE /*!< Start of Basic Cycle           */
+#define FDCAN_TT_IT_MATRIX_CYCLE_START FDCAN_TTIE_SMCE /*!< Start of Matrix Cycle          */
+#define FDCAN_TT_IT_SYNC_MODE_CHANGE   FDCAN_TTIE_CSME /*!< Change of Synchronization Mode */
+#define FDCAN_TT_IT_START_OF_GAP       FDCAN_TTIE_SOGE /*!< Start of Gap                   */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TTTimeMark_Interrupts FDCAN TT Time Mark Interrupts
+  * @{
+  */
+#define FDCAN_TT_IT_REG_TIME_MARK  FDCAN_TTIE_RTMIE /*!< Register Time Mark Interrupt     */
+#define FDCAN_TT_IT_TRIG_TIME_MARK FDCAN_TTIE_TTMIE /*!< Trigger Time Mark Event Internal */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TTStopWatch_Interrupt FDCAN TT Stop Watch Interrupt
+  * @{
+  */
+#define FDCAN_TT_IT_STOP_WATCH FDCAN_TTIE_SWEE /*!< Stop Watch Event */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TTGlobalTime_Interrupts FDCAN TT Global Time Interrupts
+  * @{
+  */
+#define FDCAN_TT_IT_GLOBAL_TIME_WRAP FDCAN_TTIE_GTWE  /*!< Global Time Wrap          */
+#define FDCAN_TT_IT_GLOBAL_TIME_DISC FDCAN_TTIE_GTDE  /*!< Global Time Discontinuity */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TTDisturbingError_Interrupts FDCAN TT Disturbing Error Interrupts
+  * @{
+  */
+#define FDCAN_TT_IT_GLOBAL_TIME_ERROR  FDCAN_TTIE_GTEE /*!< Global Time Error   */
+#define FDCAN_TT_IT_TX_COUNT_UNDERFLOW FDCAN_TTIE_TXUE /*!< Tx Count Underflow  */
+#define FDCAN_TT_IT_TX_COUNT_OVERFLOW  FDCAN_TTIE_TXOE /*!< Tx Count Overflow   */
+#define FDCAN_TT_IT_SCHEDULING_ERROR_1 FDCAN_TTIE_SE1E /*!< Scheduling Error 1  */
+#define FDCAN_TT_IT_SCHEDULING_ERROR_2 FDCAN_TTIE_SE2E /*!< Scheduling Error 2  */
+#define FDCAN_TT_IT_ERROR_LEVEL_CHANGE FDCAN_TTIE_ELCE /*!< Error Level Changed */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TTFatalError_Interrupts FDCAN TT Fatal Error Interrupts
+  * @{
+  */
+#define FDCAN_TT_IT_INIT_WATCH_TRIGGER   FDCAN_TTIE_IWTE /*!< Initialization Watch Trigger */
+#define FDCAN_TT_IT_WATCH_TRIGGER        FDCAN_TTIE_WTE  /*!< Watch Trigger                */
+#define FDCAN_TT_IT_APPLICATION_WATCHDOG FDCAN_TTIE_AWE  /*!< Application Watchdog         */
+#define FDCAN_TT_IT_CONFIG_ERROR         FDCAN_TTIE_CERE /*!< Configuration Error          */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup FDCAN_Exported_Macros FDCAN Exported Macros
+  * @{
+  */
+
+/** @brief  Reset FDCAN handle state.
+  * @param  __HANDLE__ FDCAN handle.
+  * @retval None
+  */
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) do{                                                \
+                                                      (__HANDLE__)->State = HAL_FDCAN_STATE_RESET;    \
+                                                      (__HANDLE__)->MspInitCallback = NULL;           \
+                                                      (__HANDLE__)->MspDeInitCallback = NULL;         \
+                                                     } while(0)
+#else
+#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FDCAN_STATE_RESET)
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+/**
+  * @brief  Enable the specified FDCAN interrupts.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ FDCAN interrupt.
+  *         This parameter can be any combination of @arg FDCAN_Interrupts
+  * @retval None
+  */
+#define __HAL_FDCAN_ENABLE_IT(__HANDLE__, __INTERRUPT__)             \
+  do{                                                                \
+    (__HANDLE__)->Instance->IE |= ((__INTERRUPT__) & FDCAN_IR_MASK); \
+    FDCAN_CCU->IE |= (((__INTERRUPT__) & CCU_IR_MASK) >> 30);        \
+  }while(0)
+
+
+/**
+  * @brief  Disable the specified FDCAN interrupts.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ FDCAN interrupt.
+  *         This parameter can be any combination of @arg FDCAN_Interrupts
+  * @retval None
+  */
+#define __HAL_FDCAN_DISABLE_IT(__HANDLE__, __INTERRUPT__)               \
+  do{                                                                   \
+    ((__HANDLE__)->Instance->IE) &= ~((__INTERRUPT__) & FDCAN_IR_MASK); \
+    FDCAN_CCU->IE &= ~(((__INTERRUPT__) & CCU_IR_MASK) >> 30);          \
+  }while(0)
+
+/**
+  * @brief  Check whether the specified FDCAN interrupt is set or not.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ FDCAN interrupt.
+  *         This parameter can be one of @arg FDCAN_Interrupts
+  * @retval ITStatus
+  */
+#define __HAL_FDCAN_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__INTERRUPT__)) : ((FDCAN_CCU->IR << 30) & (__INTERRUPT__)))
+
+/**
+  * @brief  Clear the specified FDCAN interrupts.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ specifies the interrupts to clear.
+  *         This parameter can be any combination of @arg FDCAN_Interrupts
+  * @retval None
+  */
+#define __HAL_FDCAN_CLEAR_IT(__HANDLE__, __INTERRUPT__)               \
+do{                                                                   \
+    ((__HANDLE__)->Instance->IR) = ((__INTERRUPT__) & FDCAN_IR_MASK); \
+    FDCAN_CCU->IR = (((__INTERRUPT__) & CCU_IR_MASK) >> 30);          \
+  }while(0)
+
+/**
+  * @brief  Check whether the specified FDCAN flag is set or not.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __FLAG__ FDCAN flag.
+  *         This parameter can be one of @arg FDCAN_flags
+  * @retval FlagStatus
+  */
+#define __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) < FDCAN_FLAG_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__FLAG__)) : ((FDCAN_CCU->IR << 30) & (__FLAG__)))
+
+/**
+  * @brief  Clear the specified FDCAN flags.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __FLAG__ specifies the flags to clear.
+  *         This parameter can be any combination of @arg FDCAN_flags
+  * @retval None
+  */
+#define __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__)             \
+do{                                                              \
+    ((__HANDLE__)->Instance->IR) = ((__FLAG__) & FDCAN_IR_MASK); \
+    FDCAN_CCU->IR = (((__FLAG__) & CCU_IR_MASK) >> 30);          \
+  }while(0)
+
+/** @brief  Check if the specified FDCAN interrupt source is enabled or disabled.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ specifies the FDCAN interrupt source to check.
+  *         This parameter can be a value of @arg FDCAN_Interrupts
+  * @retval ITStatus
+  */
+#define __HAL_FDCAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IE & (__INTERRUPT__)) : ((FDCAN_CCU->IE << 30) & (__INTERRUPT__)))
+
+/**
+  * @brief  Enable the specified FDCAN TT interrupts.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ FDCAN TT interrupt.
+  *         This parameter can be any combination of @arg FDCAN_TTInterrupts
+  * @retval None
+  */
+#define __HAL_FDCAN_TT_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the specified FDCAN TT interrupts.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ FDCAN TT interrupt.
+  *         This parameter can be any combination of @arg FDCAN_TTInterrupts
+  * @retval None
+  */
+#define __HAL_FDCAN_TT_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified FDCAN TT interrupt is set or not.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ FDCAN TT interrupt.
+  *         This parameter can be one of @arg FDCAN_TTInterrupts
+  * @retval ITStatus
+  */
+#define __HAL_FDCAN_TT_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) & (__INTERRUPT__))
+
+/**
+  * @brief  Clear the specified FDCAN TT interrupts.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ specifies the TT interrupts to clear.
+  *         This parameter can be any combination of @arg FDCAN_TTInterrupts
+  * @retval None
+  */
+#define __HAL_FDCAN_TT_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) = (__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified FDCAN TT flag is set or not.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __FLAG__ FDCAN TT flag.
+  *         This parameter can be one of @arg FDCAN_TTflags
+  * @retval FlagStatus
+  */
+#define __HAL_FDCAN_TT_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) & (__FLAG__))
+
+/**
+  * @brief  Clear the specified FDCAN TT flags.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __FLAG__ specifies the TT flags to clear.
+  *         This parameter can be any combination of @arg FDCAN_TTflags
+  * @retval None
+  */
+#define __HAL_FDCAN_TT_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) = (__FLAG__))
+
+/** @brief  Check if the specified FDCAN TT interrupt source is enabled or disabled.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ specifies the FDCAN TT interrupt source to check.
+  *         This parameter can be a value of @arg FDCAN_TTInterrupts
+  * @retval ITStatus
+  */
+#define __HAL_FDCAN_TT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) & (__INTERRUPT__))
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FDCAN_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup FDCAN_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan);
+void              HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan);
+void              HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+/* Callbacks Register/UnRegister functions  ***********************************/
+HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, pFDCAN_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID);
+HAL_StatusTypeDef HAL_FDCAN_RegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ClockCalibrationCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxEventFifoCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo0CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo1CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferCompleteCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferAbortCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ErrorStatusCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_ScheduleSyncCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_TimeMarkCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_StopWatchCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_GlobalTimeCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @addtogroup FDCAN_Exported_Functions_Group2
+  * @{
+  */
+/* Configuration functions ****************************************************/
+HAL_StatusTypeDef HAL_FDCAN_ConfigClockCalibration(FDCAN_HandleTypeDef *hfdcan, FDCAN_ClkCalUnitTypeDef *sCcuConfig);
+uint32_t          HAL_FDCAN_GetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ResetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan);
+uint32_t          HAL_FDCAN_GetClockCalibrationCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t Counter);
+HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig);
+HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd, uint32_t NonMatchingExt, uint32_t RejectRemoteStd, uint32_t RejectRemoteExt);
+HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask);
+HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode);
+HAL_StatusTypeDef HAL_FDCAN_ConfigFifoWatermark(FDCAN_HandleTypeDef *hfdcan, uint32_t FIFO, uint32_t Watermark);
+HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue);
+HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler);
+HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation);
+HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
+uint16_t          HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod);
+HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
+uint16_t          HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter);
+HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan);
+/**
+  * @}
+  */
+
+/** @addtogroup FDCAN_Exported_Functions_Group3
+  * @{
+  */
+/* Control functions **********************************************************/
+HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData);
+HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxBuffer(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex);
+HAL_StatusTypeDef HAL_FDCAN_EnableTxBufferRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex);
+uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex);
+HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData);
+HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent);
+HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus);
+HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus);
+HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters);
+uint32_t HAL_FDCAN_IsRxBufferMessageAvailable(FDCAN_HandleTypeDef *hfdcan, uint32_t RxBufferIndex);
+uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex);
+uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo);
+uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan);
+uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan);
+/**
+  * @}
+  */
+
+/** @addtogroup FDCAN_Exported_Functions_Group4
+  * @{
+  */
+/* TT Configuration and control functions**************************************/
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigOperation(FDCAN_HandleTypeDef *hfdcan, FDCAN_TT_ConfigTypeDef *pTTParams);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigReferenceMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t IdType, uint32_t Identifier, uint32_t Payload);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigTrigger(FDCAN_HandleTypeDef *hfdcan, FDCAN_TriggerTypeDef *sTriggerConfig);
+HAL_StatusTypeDef HAL_FDCAN_TT_SetGlobalTime(FDCAN_HandleTypeDef *hfdcan, uint32_t TimePreset);
+HAL_StatusTypeDef HAL_FDCAN_TT_SetClockSynchronization(FDCAN_HandleTypeDef *hfdcan, uint32_t NewTURNumerator);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigStopWatch(FDCAN_HandleTypeDef *hfdcan, uint32_t Source, uint32_t Polarity);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigRegisterTimeMark(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeMarkSource, uint32_t TimeMarkValue, uint32_t RepeatFactor, uint32_t StartCycle);
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_SetNextIsGap(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_SetEndOfGap(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigExternalSyncPhase(FDCAN_HandleTypeDef *hfdcan, uint32_t TargetPhase);
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_GetOperationStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_TTOperationStatusTypeDef *TTOpStatus);
+/**
+  * @}
+  */
+
+/** @addtogroup FDCAN_Exported_Functions_Group5
+  * @{
+  */
+/* Interrupts management ******************************************************/
+HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t TTITList, uint32_t InterruptLine);
+HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes);
+HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs);
+HAL_StatusTypeDef HAL_FDCAN_TT_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveTTITs);
+HAL_StatusTypeDef HAL_FDCAN_TT_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveTTITs);
+void              HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan);
+/**
+  * @}
+  */
+
+/** @addtogroup FDCAN_Exported_Functions_Group6
+  * @{
+  */
+/* Callback functions *********************************************************/
+void HAL_FDCAN_ClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs);
+void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs);
+void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs);
+void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs);
+void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);
+void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);
+void HAL_FDCAN_RxBufferNewMessageCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs);
+void HAL_FDCAN_TT_ScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs);
+void HAL_FDCAN_TT_TimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs);
+void HAL_FDCAN_TT_StopWatchCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount);
+void HAL_FDCAN_TT_GlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs);
+/**
+  * @}
+  */
+
+/** @addtogroup FDCAN_Exported_Functions_Group7
+  * @{
+  */
+/* Peripheral State functions *************************************************/
+uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan);
+HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup FDCAN_Private_Types FDCAN Private Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup FDCAN_Private_Variables FDCAN Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup FDCAN_Private_Constants FDCAN Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FDCAN_Private_Macros FDCAN Private Macros
+  * @{
+  */
+#define IS_FDCAN_FRAME_FORMAT(FORMAT) (((FORMAT) == FDCAN_FRAME_CLASSIC  ) || \
+                                       ((FORMAT) == FDCAN_FRAME_FD_NO_BRS) || \
+                                       ((FORMAT) == FDCAN_FRAME_FD_BRS   ))
+#define IS_FDCAN_MODE(MODE) (((MODE) == FDCAN_MODE_NORMAL              ) || \
+                             ((MODE) == FDCAN_MODE_RESTRICTED_OPERATION) || \
+                             ((MODE) == FDCAN_MODE_BUS_MONITORING      ) || \
+                             ((MODE) == FDCAN_MODE_INTERNAL_LOOPBACK   ) || \
+                             ((MODE) == FDCAN_MODE_EXTERNAL_LOOPBACK   ))
+
+#define IS_FDCAN_CLOCK_CALIBRATION(CALIBRATION) (((CALIBRATION) == FDCAN_CLOCK_CALIBRATION_DISABLE) || \
+                                                 ((CALIBRATION) == FDCAN_CLOCK_CALIBRATION_ENABLE ))
+
+#define IS_FDCAN_CKDIV(CKDIV) (((CKDIV) == FDCAN_CLOCK_DIV1 ) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV2 ) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV4 ) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV6 ) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV8 ) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV10) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV12) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV14) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV16) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV18) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV20) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV22) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV24) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV26) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV28) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV30))
+#define IS_FDCAN_NOMINAL_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 512U))
+#define IS_FDCAN_NOMINAL_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 128U))
+#define IS_FDCAN_NOMINAL_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 256U))
+#define IS_FDCAN_NOMINAL_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 128U))
+#define IS_FDCAN_DATA_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 32U))
+#define IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 16U))
+#define IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 32U))
+#define IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 16U))
+#define IS_FDCAN_MAX_VALUE(VALUE, MAX) ((VALUE) <= (MAX))
+#define IS_FDCAN_MIN_VALUE(VALUE, MIN) ((VALUE) >= (MIN))
+#define IS_FDCAN_DATA_SIZE(SIZE) (((SIZE) == FDCAN_DATA_BYTES_8 ) || \
+                                  ((SIZE) == FDCAN_DATA_BYTES_12) || \
+                                  ((SIZE) == FDCAN_DATA_BYTES_16) || \
+                                  ((SIZE) == FDCAN_DATA_BYTES_20) || \
+                                  ((SIZE) == FDCAN_DATA_BYTES_24) || \
+                                  ((SIZE) == FDCAN_DATA_BYTES_32) || \
+                                  ((SIZE) == FDCAN_DATA_BYTES_48) || \
+                                  ((SIZE) == FDCAN_DATA_BYTES_64))
+#define IS_FDCAN_TX_FIFO_QUEUE_MODE(MODE) (((MODE) == FDCAN_TX_FIFO_OPERATION ) || \
+                                           ((MODE) == FDCAN_TX_QUEUE_OPERATION))
+#define IS_FDCAN_ID_TYPE(ID_TYPE) (((ID_TYPE) == FDCAN_STANDARD_ID) || \
+                                   ((ID_TYPE) == FDCAN_EXTENDED_ID))
+#define IS_FDCAN_FILTER_CFG(CONFIG) (((CONFIG) == FDCAN_FILTER_DISABLE      ) || \
+                                     ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0   ) || \
+                                     ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1   ) || \
+                                     ((CONFIG) == FDCAN_FILTER_REJECT       ) || \
+                                     ((CONFIG) == FDCAN_FILTER_HP           ) || \
+                                     ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0_HP) || \
+                                     ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1_HP) || \
+                                     ((CONFIG) == FDCAN_FILTER_TO_RXBUFFER  ))
+#define IS_FDCAN_TX_LOCATION(LOCATION) (((LOCATION) == FDCAN_TX_BUFFER0 ) || ((LOCATION) == FDCAN_TX_BUFFER1 ) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER2 ) || ((LOCATION) == FDCAN_TX_BUFFER3 ) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER4 ) || ((LOCATION) == FDCAN_TX_BUFFER5 ) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER6 ) || ((LOCATION) == FDCAN_TX_BUFFER7 ) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER8 ) || ((LOCATION) == FDCAN_TX_BUFFER9 ) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER10) || ((LOCATION) == FDCAN_TX_BUFFER11) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER12) || ((LOCATION) == FDCAN_TX_BUFFER13) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER14) || ((LOCATION) == FDCAN_TX_BUFFER15) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER16) || ((LOCATION) == FDCAN_TX_BUFFER17) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER18) || ((LOCATION) == FDCAN_TX_BUFFER19) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER20) || ((LOCATION) == FDCAN_TX_BUFFER21) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER22) || ((LOCATION) == FDCAN_TX_BUFFER23) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER24) || ((LOCATION) == FDCAN_TX_BUFFER25) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER26) || ((LOCATION) == FDCAN_TX_BUFFER27) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER28) || ((LOCATION) == FDCAN_TX_BUFFER29) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER30) || ((LOCATION) == FDCAN_TX_BUFFER31))
+#define IS_FDCAN_RX_FIFO(FIFO) (((FIFO) == FDCAN_RX_FIFO0) || \
+                                ((FIFO) == FDCAN_RX_FIFO1))
+#define IS_FDCAN_RX_FIFO_MODE(MODE) (((MODE) == FDCAN_RX_FIFO_BLOCKING ) || \
+                                     ((MODE) == FDCAN_RX_FIFO_OVERWRITE))
+#define IS_FDCAN_STD_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE) || \
+                                        ((TYPE) == FDCAN_FILTER_DUAL ) || \
+                                        ((TYPE) == FDCAN_FILTER_MASK ))
+#define IS_FDCAN_EXT_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE        ) || \
+                                        ((TYPE) == FDCAN_FILTER_DUAL         ) || \
+                                        ((TYPE) == FDCAN_FILTER_MASK         ) || \
+                                        ((TYPE) == FDCAN_FILTER_RANGE_NO_EIDM))
+#define IS_FDCAN_FRAME_TYPE(TYPE) (((TYPE) == FDCAN_DATA_FRAME  ) || \
+                                   ((TYPE) == FDCAN_REMOTE_FRAME))
+#define IS_FDCAN_DLC(DLC) (((DLC) == FDCAN_DLC_BYTES_0 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_1 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_2 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_3 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_4 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_5 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_6 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_7 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_8 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_12) || \
+                           ((DLC) == FDCAN_DLC_BYTES_16) || \
+                           ((DLC) == FDCAN_DLC_BYTES_20) || \
+                           ((DLC) == FDCAN_DLC_BYTES_24) || \
+                           ((DLC) == FDCAN_DLC_BYTES_32) || \
+                           ((DLC) == FDCAN_DLC_BYTES_48) || \
+                           ((DLC) == FDCAN_DLC_BYTES_64))
+#define IS_FDCAN_ESI(ESI) (((ESI) == FDCAN_ESI_ACTIVE ) || \
+                           ((ESI) == FDCAN_ESI_PASSIVE))
+#define IS_FDCAN_BRS(BRS) (((BRS) == FDCAN_BRS_OFF) || \
+                           ((BRS) == FDCAN_BRS_ON ))
+#define IS_FDCAN_FDF(FDF) (((FDF) == FDCAN_CLASSIC_CAN) || \
+                           ((FDF) == FDCAN_FD_CAN     ))
+#define IS_FDCAN_EFC(EFC) (((EFC) == FDCAN_NO_TX_EVENTS   ) || \
+                           ((EFC) == FDCAN_STORE_TX_EVENTS))
+#define IS_FDCAN_IT(IT) (((IT) & ~(FDCAN_IR_MASK | CCU_IR_MASK)) == 0U)
+#define IS_FDCAN_TT_IT(IT) (((IT) & 0xFFF80000U) == 0U)
+#define IS_FDCAN_FIFO_WATERMARK(FIFO) (((FIFO) == FDCAN_CFG_TX_EVENT_FIFO) || \
+                                       ((FIFO) == FDCAN_CFG_RX_FIFO0     ) || \
+                                       ((FIFO) == FDCAN_CFG_RX_FIFO1     ))
+#define IS_FDCAN_NON_MATCHING(DESTINATION) (((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO0) || \
+                                            ((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO1) || \
+                                            ((DESTINATION) == FDCAN_REJECT            ))
+#define IS_FDCAN_REJECT_REMOTE(DESTINATION) (((DESTINATION) == FDCAN_FILTER_REMOTE) || \
+                                             ((DESTINATION) == FDCAN_REJECT_REMOTE))
+#define IS_FDCAN_IT_LINE(IT_LINE) (((IT_LINE) == FDCAN_INTERRUPT_LINE0) || \
+                                   ((IT_LINE) == FDCAN_INTERRUPT_LINE1))
+#define IS_FDCAN_TIMESTAMP(OPERATION) (((OPERATION) == FDCAN_TIMESTAMP_INTERNAL) || \
+                                       ((OPERATION) == FDCAN_TIMESTAMP_EXTERNAL))
+#define IS_FDCAN_TIMESTAMP_PRESCALER(PRESCALER) (((PRESCALER) == FDCAN_TIMESTAMP_PRESC_1 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_2 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_3 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_4 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_5 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_6 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_7 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_8 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_9 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_10) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_11) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_12) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_13) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_14) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_15) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_16))
+#define IS_FDCAN_TIMEOUT(OPERATION) (((OPERATION) == FDCAN_TIMEOUT_CONTINUOUS   ) || \
+                                     ((OPERATION) == FDCAN_TIMEOUT_TX_EVENT_FIFO) || \
+                                     ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO0     ) || \
+                                     ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO1     ))
+#define IS_FDCAN_CALIBRATION_FIELD_LENGTH(LENGTH) (((LENGTH) == FDCAN_CALIB_FIELD_LENGTH_32) || \
+                                                   ((LENGTH) == FDCAN_CALIB_FIELD_LENGTH_64))
+#define IS_FDCAN_CALIBRATION_COUNTER(COUNTER) (((COUNTER) == FDCAN_CALIB_TIME_QUANTA_COUNTER ) || \
+                                               ((COUNTER) == FDCAN_CALIB_CLOCK_PERIOD_COUNTER) || \
+                                               ((COUNTER) == FDCAN_CALIB_WATCHDOG_COUNTER    ))
+#define IS_FDCAN_TT_REFERENCE_MESSAGE_PAYLOAD(PAYLOAD) (((PAYLOAD) == FDCAN_TT_REF_MESSAGE_NO_PAYLOAD ) || \
+                                                        ((PAYLOAD) == FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD))
+#define IS_FDCAN_TT_REPEAT_FACTOR(FACTOR) (((FACTOR) == FDCAN_TT_REPEAT_EVERY_CYCLE     ) || \
+                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_2ND_CYCLE ) || \
+                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_4TH_CYCLE ) || \
+                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_8TH_CYCLE ) || \
+                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_16TH_CYCLE) || \
+                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_32ND_CYCLE) || \
+                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_64TH_CYCLE))
+#define IS_FDCAN_TT_TRIGGER_TYPE(TYPE) (((TYPE) == FDCAN_TT_TX_REF_TRIGGER        ) || \
+                                        ((TYPE) == FDCAN_TT_TX_REF_TRIGGER_GAP    ) || \
+                                        ((TYPE) == FDCAN_TT_TX_TRIGGER_SINGLE     ) || \
+                                        ((TYPE) == FDCAN_TT_TX_TRIGGER_CONTINUOUS ) || \
+                                        ((TYPE) == FDCAN_TT_TX_TRIGGER_ARBITRATION) || \
+                                        ((TYPE) == FDCAN_TT_TX_TRIGGER_MERGED     ) || \
+                                        ((TYPE) == FDCAN_TT_WATCH_TRIGGER         ) || \
+                                        ((TYPE) == FDCAN_TT_WATCH_TRIGGER_GAP     ) || \
+                                        ((TYPE) == FDCAN_TT_RX_TRIGGER            ) || \
+                                        ((TYPE) == FDCAN_TT_TIME_BASE_TRIGGER     ) || \
+                                        ((TYPE) == FDCAN_TT_END_OF_LIST           ))
+#define IS_FDCAN_TT_TM_EVENT_INTERNAL(EVENT) (((EVENT) == FDCAN_TT_TM_NO_INTERNAL_EVENT ) || \
+                                              ((EVENT) == FDCAN_TT_TM_GEN_INTERNAL_EVENT))
+#define IS_FDCAN_TT_TM_EVENT_EXTERNAL(EVENT) (((EVENT) == FDCAN_TT_TM_NO_EXTERNAL_EVENT ) || \
+                                              ((EVENT) == FDCAN_TT_TM_GEN_EXTERNAL_EVENT))
+#define IS_FDCAN_OPERATION_MODE(MODE) (((MODE) == FDCAN_TT_COMMUNICATION_LEVEL1 ) || \
+                                       ((MODE) == FDCAN_TT_COMMUNICATION_LEVEL2 ) || \
+                                       ((MODE) == FDCAN_TT_COMMUNICATION_LEVEL0 ))
+#define IS_FDCAN_TT_OPERATION(OPERATION) (((OPERATION) == FDCAN_STRICTLY_TT_OPERATION      ) || \
+                                          ((OPERATION) == FDCAN_EXT_EVT_SYNC_TT_OPERATION))
+#define IS_FDCAN_TT_TIME_MASTER(FUNCTION) (((FUNCTION) == FDCAN_TT_SLAVE           ) || \
+                                           ((FUNCTION) == FDCAN_TT_POTENTIAL_MASTER))
+#define IS_FDCAN_TT_EXTERNAL_CLK_SYNC(SYNC) (((SYNC) == FDCAN_TT_EXT_CLK_SYNC_DISABLE) || \
+                                             ((SYNC) == FDCAN_TT_EXT_CLK_SYNC_ENABLE ))
+#define IS_FDCAN_TT_GLOBAL_TIME_FILTERING(FILTERING) (((FILTERING) == FDCAN_TT_GLOB_TIME_FILT_DISABLE) || \
+                                                      ((FILTERING) == FDCAN_TT_GLOB_TIME_FILT_ENABLE ))
+#define IS_FDCAN_TT_AUTO_CLK_CALIBRATION(CALIBRATION) (((CALIBRATION) == FDCAN_TT_AUTO_CLK_CALIB_DISABLE) || \
+                                                       ((CALIBRATION) == FDCAN_TT_AUTO_CLK_CALIB_ENABLE ))
+#define IS_FDCAN_TT_EVENT_TRIGGER_POLARITY(POLARITY) (((POLARITY) == FDCAN_TT_EVT_TRIG_POL_RISING ) || \
+                                                      ((POLARITY) == FDCAN_TT_EVT_TRIG_POL_FALLING))
+#define IS_FDCAN_TT_BASIC_CYCLES_NUMBER(NUMBER) (((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_1 ) || \
+                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_2 ) || \
+                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_4 ) || \
+                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_8 ) || \
+                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_16) || \
+                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_32) || \
+                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_64))
+#define IS_FDCAN_TT_CYCLE_START_SYNC(SYNC) (((SYNC) == FDCAN_TT_NO_SYNC_PULSE         ) || \
+                                            ((SYNC) == FDCAN_TT_SYNC_BASIC_CYCLE_START) || \
+                                            ((SYNC) == FDCAN_TT_SYNC_MATRIX_START     ))
+#define IS_FDCAN_TT_TX_ENABLE_WINDOW(NTU) (((NTU) >= 1U) && ((NTU) <= 16U))
+#define IS_FDCAN_TT_TUR_NUMERATOR(NUMERATOR) (((NUMERATOR) >= 0x10000U) && ((NUMERATOR) <= 0x1FFFFU))
+#define IS_FDCAN_TT_TUR_DENOMINATOR(DENOMINATOR) (((DENOMINATOR) >= 0x0001U) && ((DENOMINATOR) <= 0x3FFFU))
+#define IS_FDCAN_TT_TUR_LEVEL_1(NC,DC) ((NC) >= (4U * (DC)))
+#define IS_FDCAN_TT_TUR_LEVEL_0_2(NC,DC) ((NC) >= (8U * (DC)))
+#define IS_FDCAN_TT_STOP_WATCH_TRIGGER(TRIGGER) (((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_0) || \
+                                                 ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_1) || \
+                                                 ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_2) || \
+                                                 ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_3))
+#define IS_FDCAN_TT_EVENT_TRIGGER(TRIGGER) (((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_0) || \
+                                            ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_1) || \
+                                            ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_2) || \
+                                            ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_3))
+#define IS_FDCAN_TT_TIME_PRESET(TIME) (((TIME) <= 0xFFFFU) && ((TIME) != 0x8000U))
+#define IS_FDCAN_TT_STOP_WATCH_SOURCE(SOURCE) (((SOURCE) == FDCAN_TT_STOP_WATCH_DISABLED   ) || \
+                                               ((SOURCE) == FDCAN_TT_STOP_WATCH_CYCLE_TIME ) || \
+                                               ((SOURCE) == FDCAN_TT_STOP_WATCH_LOCAL_TIME ) || \
+                                               ((SOURCE) == FDCAN_TT_STOP_WATCH_GLOBAL_TIME))
+#define IS_FDCAN_TT_STOP_WATCH_POLARITY(POLARITY) (((POLARITY) == FDCAN_TT_STOP_WATCH_RISING ) || \
+                                                   ((POLARITY) == FDCAN_TT_STOP_WATCH_FALLING))
+#define IS_FDCAN_TT_REGISTER_TIME_MARK_SOURCE(SOURCE) (((SOURCE) == FDCAN_TT_REG_TIMEMARK_DIABLED ) || \
+                                                       ((SOURCE) == FDCAN_TT_REG_TIMEMARK_CYC_TIME) || \
+                                                       ((SOURCE) == FDCAN_TT_REG_TIMEMARK_LOC_TIME) || \
+                                                       ((SOURCE) == FDCAN_TT_REG_TIMEMARK_GLO_TIME))
+/**
+  * @}
+  */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup FDCAN_Private_Functions_Prototypes FDCAN Private Functions Prototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup FDCAN_Private_Functions FDCAN Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_FDCAN_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h
new file mode 100644
index 00000000..6bda249e
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h
@@ -0,0 +1,829 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_flash.h
+  * @author  MCD Application Team
+  * @brief   Header file of FLASH HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_FLASH_H
+#define STM32H7xx_HAL_FLASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FLASH
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Types FLASH Exported Types
+  * @{
+  */
+
+/**
+  * @brief  FLASH Procedure structure definition
+  */
+typedef enum
+{
+  FLASH_PROC_NONE = 0U,
+  FLASH_PROC_SECTERASE_BANK1,
+  FLASH_PROC_MASSERASE_BANK1,
+  FLASH_PROC_PROGRAM_BANK1,
+  FLASH_PROC_SECTERASE_BANK2,
+  FLASH_PROC_MASSERASE_BANK2,
+  FLASH_PROC_PROGRAM_BANK2,
+  FLASH_PROC_ALLBANK_MASSERASE
+} FLASH_ProcedureTypeDef;
+
+
+/**
+  * @brief  FLASH handle Structure definition
+  */
+typedef struct
+{
+  __IO FLASH_ProcedureTypeDef ProcedureOnGoing;   /*!< Internal variable to indicate which procedure is ongoing or not in IT context */
+
+  __IO uint32_t               NbSectorsToErase;   /*!< Internal variable to save the remaining sectors to erase in IT context        */
+
+  __IO uint32_t               VoltageForErase;    /*!< Internal variable to provide voltage range selected by user in IT context     */
+
+  __IO uint32_t               Sector;             /*!< Internal variable to define the current sector which is erasing               */
+
+  __IO uint32_t               Address;            /*!< Internal variable to save address selected for program                        */
+
+  HAL_LockTypeDef             Lock;               /*!< FLASH locking object                                                          */
+
+  __IO uint32_t               ErrorCode;          /*!< FLASH error code                                                              */
+
+}FLASH_ProcessTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
+  * @{
+  */
+
+/** @defgroup FLASH_Error_Code FLASH Error Code
+  * @brief    FLASH Error Code
+  * @{
+  */
+#define HAL_FLASH_ERROR_NONE         0x00000000U               /*!< No error                              */
+
+#define HAL_FLASH_ERROR_WRP          FLASH_FLAG_WRPERR         /*!< Write Protection Error                */
+#define HAL_FLASH_ERROR_PGS          FLASH_FLAG_PGSERR         /*!< Program Sequence Error                */
+#define HAL_FLASH_ERROR_STRB         FLASH_FLAG_STRBERR        /*!< Strobe Error                          */
+#define HAL_FLASH_ERROR_INC          FLASH_FLAG_INCERR         /*!< Inconsistency Error                   */
+#if defined (FLASH_SR_OPERR)
+#define HAL_FLASH_ERROR_OPE          FLASH_FLAG_OPERR          /*!< Operation Error                       */
+#endif /* FLASH_SR_OPERR */
+#define HAL_FLASH_ERROR_RDP          FLASH_FLAG_RDPERR         /*!< Read Protection Error                 */
+#define HAL_FLASH_ERROR_RDS          FLASH_FLAG_RDSERR         /*!< Read Secured Error                    */
+#define HAL_FLASH_ERROR_SNECC        FLASH_FLAG_SNECCERR       /*!< ECC Single Correction Error           */
+#define HAL_FLASH_ERROR_DBECC        FLASH_FLAG_DBECCERR       /*!< ECC Double Detection Error            */
+#define HAL_FLASH_ERROR_CRCRD        FLASH_FLAG_CRCRDERR       /*!< CRC Read Error                        */
+
+#define HAL_FLASH_ERROR_WRP_BANK1    FLASH_FLAG_WRPERR_BANK1   /*!< Write Protection Error on Bank 1      */
+#define HAL_FLASH_ERROR_PGS_BANK1    FLASH_FLAG_PGSERR_BANK1   /*!< Program Sequence Error on Bank 1      */
+#define HAL_FLASH_ERROR_STRB_BANK1   FLASH_FLAG_STRBERR_BANK1  /*!< Strobe Error on Bank 1                */
+#define HAL_FLASH_ERROR_INC_BANK1    FLASH_FLAG_INCERR_BANK1   /*!< Inconsistency Error on Bank 1         */
+#if defined (FLASH_SR_OPERR)
+#define HAL_FLASH_ERROR_OPE_BANK1    FLASH_FLAG_OPERR_BANK1    /*!< Operation Error on Bank 1             */
+#endif /* FLASH_SR_OPERR */
+#define HAL_FLASH_ERROR_RDP_BANK1    FLASH_FLAG_RDPERR_BANK1   /*!< Read Protection Error on Bank 1       */
+#define HAL_FLASH_ERROR_RDS_BANK1    FLASH_FLAG_RDSERR_BANK1   /*!< Read Secured Error on Bank 1          */
+#define HAL_FLASH_ERROR_SNECC_BANK1  FLASH_FLAG_SNECCERR_BANK1 /*!< ECC Single Correction Error on Bank 1 */
+#define HAL_FLASH_ERROR_DBECC_BANK1  FLASH_FLAG_DBECCERR_BANK1 /*!< ECC Double Detection Error on Bank 1  */
+#define HAL_FLASH_ERROR_CRCRD_BANK1  FLASH_FLAG_CRCRDERR_BANK1 /*!< CRC Read Error on Bank1               */
+
+#define HAL_FLASH_ERROR_WRP_BANK2    FLASH_FLAG_WRPERR_BANK2    /*!< Write Protection Error on Bank 2      */
+#define HAL_FLASH_ERROR_PGS_BANK2    FLASH_FLAG_PGSERR_BANK2    /*!< Program Sequence Error on Bank 2      */
+#define HAL_FLASH_ERROR_STRB_BANK2   FLASH_FLAG_STRBERR_BANK2   /*!< Strobe Error on Bank 2                */
+#define HAL_FLASH_ERROR_INC_BANK2    FLASH_FLAG_INCERR_BANK2    /*!< Inconsistency Error on Bank 2         */
+#if defined (FLASH_SR_OPERR)
+#define HAL_FLASH_ERROR_OPE_BANK2    FLASH_FLAG_OPERR_BANK2     /*!< Operation Error on Bank 2             */
+#endif /* FLASH_SR_OPERR */
+#define HAL_FLASH_ERROR_RDP_BANK2    FLASH_FLAG_RDPERR_BANK2    /*!< Read Protection Error on Bank 2       */
+#define HAL_FLASH_ERROR_RDS_BANK2    FLASH_FLAG_RDSERR_BANK2    /*!< Read Secured Error on Bank 2          */
+#define HAL_FLASH_ERROR_SNECC_BANK2  FLASH_FLAG_SNECCERR_BANK2  /*!< ECC Single Correction Error on Bank 2 */
+#define HAL_FLASH_ERROR_DBECC_BANK2  FLASH_FLAG_DBECCERR_BANK2  /*!< ECC Double Detection Error on Bank 2  */
+#define HAL_FLASH_ERROR_CRCRD_BANK2  FLASH_FLAG_CRCRDERR_BANK2  /*!< CRC Read Error on Bank2               */
+
+#define HAL_FLASH_ERROR_OB_CHANGE    FLASH_OPTSR_OPTCHANGEERR   /*!< Option Byte Change Error              */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Type_Program FLASH Type Program
+  * @{
+  */
+#define FLASH_TYPEPROGRAM_FLASHWORD  0x01U        /*!< Program a flash word at a specified address */
+#if defined (FLASH_OPTCR_PG_OTP)
+#define FLASH_TYPEPROGRAM_OTPWORD    0x02U        /*!< Program an OTP word at a specified address  */
+#endif /* FLASH_OPTCR_PG_OTP */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Flag_definition FLASH Flag definition
+  * @brief Flag definition
+  * @{
+  */
+#define FLASH_FLAG_BSY                     FLASH_SR_BSY             /*!< FLASH Busy flag */
+#define FLASH_FLAG_WBNE                    FLASH_SR_WBNE            /*!< Write Buffer Not Empty flag */
+#define FLASH_FLAG_QW                      FLASH_SR_QW              /*!< Wait Queue on flag */
+#define FLASH_FLAG_CRC_BUSY                FLASH_SR_CRC_BUSY        /*!< CRC Busy flag */
+#define FLASH_FLAG_EOP                     FLASH_SR_EOP             /*!< End Of Program on flag */
+#define FLASH_FLAG_WRPERR                  FLASH_SR_WRPERR          /*!< Write Protection Error on flag */
+#define FLASH_FLAG_PGSERR                  FLASH_SR_PGSERR          /*!< Program Sequence Error on flag */
+#define FLASH_FLAG_STRBERR                 FLASH_SR_STRBERR         /*!< Strobe Error flag */
+#define FLASH_FLAG_INCERR                  FLASH_SR_INCERR          /*!< Inconsistency Error on flag */
+#if defined (FLASH_SR_OPERR)
+#define FLASH_FLAG_OPERR                   FLASH_SR_OPERR           /*!< Operation Error on flag */
+#endif /* FLASH_SR_OPERR */
+#define FLASH_FLAG_RDPERR                  FLASH_SR_RDPERR          /*!< Read Protection Error on flag */
+#define FLASH_FLAG_RDSERR                  FLASH_SR_RDSERR          /*!< Read Secured Error on flag */
+#define FLASH_FLAG_SNECCERR                FLASH_SR_SNECCERR        /*!< Single ECC Error Correction on flag */
+#define FLASH_FLAG_DBECCERR                FLASH_SR_DBECCERR        /*!< Double Detection ECC Error on flag */
+#define FLASH_FLAG_CRCEND                  FLASH_SR_CRCEND          /*!< CRC End of Calculation flag */
+#define FLASH_FLAG_CRCRDERR                FLASH_SR_CRCRDERR        /*!< CRC Read Error on bank flag */
+
+#define FLASH_FLAG_BSY_BANK1               FLASH_SR_BSY             /*!< FLASH Bank 1 Busy flag */
+#define FLASH_FLAG_WBNE_BANK1              FLASH_SR_WBNE            /*!< Write Buffer Not Empty on Bank 1 flag */
+#define FLASH_FLAG_QW_BANK1                FLASH_SR_QW              /*!< Wait Queue on Bank 1 flag */
+#define FLASH_FLAG_CRC_BUSY_BANK1          FLASH_SR_CRC_BUSY        /*!< CRC Busy on Bank 1 flag */
+#define FLASH_FLAG_EOP_BANK1               FLASH_SR_EOP             /*!< End Of Program on Bank 1 flag */
+#define FLASH_FLAG_WRPERR_BANK1            FLASH_SR_WRPERR          /*!< Write Protection Error on Bank 1 flag */
+#define FLASH_FLAG_PGSERR_BANK1            FLASH_SR_PGSERR          /*!< Program Sequence Error on Bank 1 flag */
+#define FLASH_FLAG_STRBERR_BANK1           FLASH_SR_STRBERR         /*!< Strobe Error on Bank 1 flag */
+#define FLASH_FLAG_INCERR_BANK1            FLASH_SR_INCERR          /*!< Inconsistency Error on Bank 1 flag */
+#if defined (FLASH_SR_OPERR)
+#define FLASH_FLAG_OPERR_BANK1             FLASH_SR_OPERR           /*!< Operation Error on Bank 1 flag */
+#endif /* FLASH_SR_OPERR */
+#define FLASH_FLAG_RDPERR_BANK1            FLASH_SR_RDPERR          /*!< Read Protection Error on Bank 1 flag */
+#define FLASH_FLAG_RDSERR_BANK1            FLASH_SR_RDSERR          /*!< Read Secured Error on Bank 1 flag */
+#define FLASH_FLAG_SNECCERR_BANK1          FLASH_SR_SNECCERR        /*!< Single ECC Error Correction on Bank 1 flag */
+#define FLASH_FLAG_DBECCERR_BANK1          FLASH_SR_DBECCERR        /*!< Double Detection ECC Error on Bank 1 flag */
+#define FLASH_FLAG_CRCEND_BANK1            FLASH_SR_CRCEND          /*!< CRC End of Calculation on Bank 1 flag */
+#define FLASH_FLAG_CRCRDERR_BANK1          FLASH_SR_CRCRDERR        /*!< CRC Read error on Bank 1 flag */
+
+#if defined (FLASH_SR_OPERR)
+#define FLASH_FLAG_ALL_ERRORS_BANK1       (FLASH_FLAG_WRPERR_BANK1   | FLASH_FLAG_PGSERR_BANK1   | \
+                                           FLASH_FLAG_STRBERR_BANK1  | FLASH_FLAG_INCERR_BANK1   | \
+                                           FLASH_FLAG_OPERR_BANK1    | FLASH_FLAG_RDPERR_BANK1   | \
+                                           FLASH_FLAG_RDSERR_BANK1   | FLASH_FLAG_SNECCERR_BANK1 | \
+                                           FLASH_FLAG_DBECCERR_BANK1 | FLASH_FLAG_CRCRDERR_BANK1) /*!< All Bank 1 error flags */
+#else
+#define FLASH_FLAG_ALL_ERRORS_BANK1       (FLASH_FLAG_WRPERR_BANK1   | FLASH_FLAG_PGSERR_BANK1   | \
+                                           FLASH_FLAG_STRBERR_BANK1  | FLASH_FLAG_INCERR_BANK1   | \
+                                           FLASH_FLAG_RDPERR_BANK1   | FLASH_FLAG_RDSERR_BANK1   | \
+                                           FLASH_FLAG_SNECCERR_BANK1 | FLASH_FLAG_DBECCERR_BANK1 | \
+                                           FLASH_FLAG_CRCRDERR_BANK1) /*!< All Bank 1 error flags */
+#endif /* FLASH_SR_OPERR */
+
+#define FLASH_FLAG_ALL_BANK1              (FLASH_FLAG_BSY_BANK1      | FLASH_FLAG_WBNE_BANK1     | \
+                                           FLASH_FLAG_QW_BANK1       | FLASH_FLAG_CRC_BUSY_BANK1 | \
+                                           FLASH_FLAG_EOP_BANK1      | FLASH_FLAG_CRCEND_BANK1   | \
+                                           FLASH_FLAG_ALL_ERRORS_BANK1) /*!< All Bank 1 flags */
+
+#define FLASH_FLAG_BSY_BANK2               (FLASH_SR_BSY      | 0x80000000U)        /*!< FLASH Bank 2 Busy flag */
+#define FLASH_FLAG_WBNE_BANK2              (FLASH_SR_WBNE     | 0x80000000U)        /*!< Write Buffer Not Empty on Bank 2 flag */
+#define FLASH_FLAG_QW_BANK2                (FLASH_SR_QW       | 0x80000000U)        /*!< Wait Queue on Bank 2 flag */
+#define FLASH_FLAG_CRC_BUSY_BANK2          (FLASH_SR_CRC_BUSY | 0x80000000U)        /*!< CRC Busy on Bank 2 flag */
+#define FLASH_FLAG_EOP_BANK2               (FLASH_SR_EOP      | 0x80000000U)        /*!< End Of Program on Bank 2 flag */
+#define FLASH_FLAG_WRPERR_BANK2            (FLASH_SR_WRPERR   | 0x80000000U)        /*!< Write Protection Error on Bank 2 flag */
+#define FLASH_FLAG_PGSERR_BANK2            (FLASH_SR_PGSERR   | 0x80000000U)        /*!< Program Sequence Error on Bank 2 flag */
+#define FLASH_FLAG_STRBERR_BANK2           (FLASH_SR_STRBERR  | 0x80000000U)        /*!< Strobe Error on Bank 2 flag */
+#define FLASH_FLAG_INCERR_BANK2            (FLASH_SR_INCERR   | 0x80000000U)        /*!< Inconsistency Error on Bank 2 flag */
+#if defined (FLASH_SR_OPERR)
+#define FLASH_FLAG_OPERR_BANK2             (FLASH_SR_OPERR    | 0x80000000U)        /*!< Operation Error on Bank 2 flag */
+#endif /* FLASH_SR_OPERR */
+#define FLASH_FLAG_RDPERR_BANK2            (FLASH_SR_RDPERR   | 0x80000000U)        /*!< Read Protection Error on Bank 2 flag */
+#define FLASH_FLAG_RDSERR_BANK2            (FLASH_SR_RDSERR   | 0x80000000U)        /*!< Read Secured Error on Bank 2 flag */
+#define FLASH_FLAG_SNECCERR_BANK2          (FLASH_SR_SNECCERR | 0x80000000U)        /*!< Single ECC Error Correction on Bank 2 flag */
+#define FLASH_FLAG_DBECCERR_BANK2          (FLASH_SR_DBECCERR | 0x80000000U)        /*!< Double Detection ECC Error on Bank 2 flag */
+#define FLASH_FLAG_CRCEND_BANK2            (FLASH_SR_CRCEND   | 0x80000000U)        /*!< CRC End of Calculation on Bank 2 flag */
+#define FLASH_FLAG_CRCRDERR_BANK2          (FLASH_SR_CRCRDERR | 0x80000000U)        /*!< CRC Read error on Bank 2 flag */
+
+#if defined (FLASH_SR_OPERR)
+#define FLASH_FLAG_ALL_ERRORS_BANK2       (FLASH_FLAG_WRPERR_BANK2   | FLASH_FLAG_PGSERR_BANK2   | \
+                                           FLASH_FLAG_STRBERR_BANK2  | FLASH_FLAG_INCERR_BANK2   | \
+                                           FLASH_FLAG_OPERR_BANK2    | FLASH_FLAG_RDPERR_BANK2   | \
+                                           FLASH_FLAG_RDSERR_BANK2   | FLASH_FLAG_SNECCERR_BANK2 | \
+                                           FLASH_FLAG_DBECCERR_BANK2 | FLASH_FLAG_CRCRDERR_BANK2) /*!< All Bank 2 error flags */
+#else
+#define FLASH_FLAG_ALL_ERRORS_BANK2       (FLASH_FLAG_WRPERR_BANK2   | FLASH_FLAG_PGSERR_BANK2   | \
+                                           FLASH_FLAG_STRBERR_BANK2  | FLASH_FLAG_INCERR_BANK2   | \
+                                           FLASH_FLAG_RDPERR_BANK2   | FLASH_FLAG_RDSERR_BANK2   | \
+                                           FLASH_FLAG_SNECCERR_BANK2 | FLASH_FLAG_DBECCERR_BANK2 | \
+                                           FLASH_FLAG_CRCRDERR_BANK2) /*!< All Bank 2 error flags */
+#endif /* FLASH_SR_OPERR */
+
+#define FLASH_FLAG_ALL_BANK2              (FLASH_FLAG_BSY_BANK2      | FLASH_FLAG_WBNE_BANK2     | \
+                                           FLASH_FLAG_QW_BANK2       | FLASH_FLAG_CRC_BUSY_BANK2 | \
+                                           FLASH_FLAG_EOP_BANK2      | FLASH_FLAG_CRCEND_BANK2   | \
+                                           FLASH_FLAG_ALL_ERRORS_BANK2) /*!< All Bank 2 flags */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition
+  * @brief FLASH Interrupt definition
+  * @{
+  */
+#define FLASH_IT_EOP_BANK1                  FLASH_CR_EOPIE       /*!< End of FLASH Bank 1 Operation Interrupt source */
+#define FLASH_IT_WRPERR_BANK1               FLASH_CR_WRPERRIE    /*!< Write Protection Error on Bank 1 Interrupt source */
+#define FLASH_IT_PGSERR_BANK1               FLASH_CR_PGSERRIE    /*!< Program Sequence Error on Bank 1 Interrupt source */
+#define FLASH_IT_STRBERR_BANK1              FLASH_CR_STRBERRIE   /*!< Strobe Error on Bank 1 Interrupt source */
+#define FLASH_IT_INCERR_BANK1               FLASH_CR_INCERRIE    /*!< Inconsistency Error on Bank 1 Interrupt source */
+#if defined (FLASH_CR_OPERRIE)
+#define FLASH_IT_OPERR_BANK1                FLASH_CR_OPERRIE     /*!< Operation Error on Bank 1 Interrupt source */
+#endif /* FLASH_CR_OPERRIE */
+#define FLASH_IT_RDPERR_BANK1               FLASH_CR_RDPERRIE    /*!< Read protection Error on Bank 1 Interrupt source */
+#define FLASH_IT_RDSERR_BANK1               FLASH_CR_RDSERRIE    /*!< Read Secured Error on Bank 1 Interrupt source */
+#define FLASH_IT_SNECCERR_BANK1             FLASH_CR_SNECCERRIE  /*!< Single ECC Error Correction on Bank 1 Interrupt source */
+#define FLASH_IT_DBECCERR_BANK1             FLASH_CR_DBECCERRIE  /*!< Double Detection ECC Error on Bank 1 Interrupt source */
+#define FLASH_IT_CRCEND_BANK1               FLASH_CR_CRCENDIE    /*!< CRC End on Bank 1 Interrupt source */
+#define FLASH_IT_CRCRDERR_BANK1             FLASH_CR_CRCRDERRIE  /*!< CRC Read error on Bank 1 Interrupt source */
+
+#if defined (FLASH_CR_OPERRIE)
+#define FLASH_IT_ALL_BANK1                 (FLASH_IT_EOP_BANK1       | FLASH_IT_WRPERR_BANK1    | \
+                                            FLASH_IT_PGSERR_BANK1    | FLASH_IT_STRBERR_BANK1   | \
+                                            FLASH_IT_INCERR_BANK1    | FLASH_IT_OPERR_BANK1     | \
+                                            FLASH_IT_RDPERR_BANK1    | FLASH_IT_RDSERR_BANK1    | \
+                                            FLASH_IT_SNECCERR_BANK1  | FLASH_IT_DBECCERR_BANK1  | \
+                                            FLASH_IT_CRCEND_BANK1    | FLASH_IT_CRCRDERR_BANK1) /*!< All Bank 1 Interrupt sources */
+#else
+#define FLASH_IT_ALL_BANK1                 (FLASH_IT_EOP_BANK1       | FLASH_IT_WRPERR_BANK1    | \
+                                            FLASH_IT_PGSERR_BANK1    | FLASH_IT_STRBERR_BANK1   | \
+                                            FLASH_IT_INCERR_BANK1    | FLASH_IT_RDPERR_BANK1    | \
+                                            FLASH_IT_RDSERR_BANK1    | FLASH_IT_SNECCERR_BANK1  | \
+                                            FLASH_IT_DBECCERR_BANK1  | FLASH_IT_CRCEND_BANK1    | \
+                                            FLASH_IT_CRCRDERR_BANK1) /*!< All Bank 1 Interrupt sources */
+#endif /* FLASH_CR_OPERRIE */
+
+#define FLASH_IT_EOP_BANK2                 (FLASH_CR_EOPIE      | 0x80000000U)  /*!< End of FLASH Bank 2 Operation Interrupt source */
+#define FLASH_IT_WRPERR_BANK2              (FLASH_CR_WRPERRIE   | 0x80000000U)  /*!< Write Protection Error on Bank 2 Interrupt source */
+#define FLASH_IT_PGSERR_BANK2              (FLASH_CR_PGSERRIE   | 0x80000000U)  /*!< Program Sequence Error on Bank 2 Interrupt source */
+#define FLASH_IT_STRBERR_BANK2             (FLASH_CR_STRBERRIE  | 0x80000000U)  /*!< Strobe Error on Bank 2 Interrupt source */
+#define FLASH_IT_INCERR_BANK2              (FLASH_CR_INCERRIE   | 0x80000000U)  /*!< Inconsistency Error on Bank 2 Interrupt source */
+#if defined (FLASH_CR_OPERRIE)
+#define FLASH_IT_OPERR_BANK2               (FLASH_CR_OPERRIE    | 0x80000000U)  /*!< Operation Error on Bank 2 Interrupt source */
+#endif /* FLASH_CR_OPERRIE */
+#define FLASH_IT_RDPERR_BANK2              (FLASH_CR_RDPERRIE   | 0x80000000U)  /*!< Read protection Error on Bank 2 Interrupt source */
+#define FLASH_IT_RDSERR_BANK2              (FLASH_CR_RDSERRIE   | 0x80000000U)  /*!< Read Secured Error on Bank 2 Interrupt source */
+#define FLASH_IT_SNECCERR_BANK2            (FLASH_CR_SNECCERRIE | 0x80000000U)  /*!< Single ECC Error Correction on Bank 2 Interrupt source */
+#define FLASH_IT_DBECCERR_BANK2            (FLASH_CR_DBECCERRIE | 0x80000000U)  /*!< Double Detection ECC Error on Bank 2 Interrupt source */
+#define FLASH_IT_CRCEND_BANK2              (FLASH_CR_CRCENDIE   | 0x80000000U)  /*!< CRC End on Bank 2 Interrupt source */
+#define FLASH_IT_CRCRDERR_BANK2            (FLASH_CR_CRCRDERRIE | 0x80000000U)  /*!< CRC Read Error on Bank 2 Interrupt source */
+
+#if defined (FLASH_CR_OPERRIE)
+#define FLASH_IT_ALL_BANK2                 (FLASH_IT_EOP_BANK2       | FLASH_IT_WRPERR_BANK2    | \
+                                            FLASH_IT_PGSERR_BANK2    | FLASH_IT_STRBERR_BANK2   | \
+                                            FLASH_IT_INCERR_BANK2    | FLASH_IT_OPERR_BANK2     | \
+                                            FLASH_IT_RDPERR_BANK2    | FLASH_IT_RDSERR_BANK2    | \
+                                            FLASH_IT_SNECCERR_BANK2  | FLASH_IT_DBECCERR_BANK2  | \
+                                            FLASH_IT_CRCEND_BANK2    | FLASH_IT_CRCRDERR_BANK2) /*!< All Bank 2 Interrupt sources */
+#else
+#define FLASH_IT_ALL_BANK2                 (FLASH_IT_EOP_BANK2       | FLASH_IT_WRPERR_BANK2    | \
+                                            FLASH_IT_PGSERR_BANK2    | FLASH_IT_STRBERR_BANK2   | \
+                                            FLASH_IT_INCERR_BANK2    | FLASH_IT_RDPERR_BANK2    | \
+                                            FLASH_IT_RDSERR_BANK2    | FLASH_IT_SNECCERR_BANK2  | \
+                                            FLASH_IT_DBECCERR_BANK2  | FLASH_IT_CRCEND_BANK2    | \
+                                            FLASH_IT_CRCRDERR_BANK2) /*!< All Bank 2 Interrupt sources */
+#endif /* FLASH_CR_OPERRIE */
+/**
+  * @}
+  */
+
+#if defined (FLASH_CR_PSIZE)
+/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism
+  * @{
+  */
+#define FLASH_PSIZE_BYTE           0x00000000U       /*!< Flash program/erase by 8 bits  */
+#define FLASH_PSIZE_HALF_WORD      FLASH_CR_PSIZE_0  /*!< Flash program/erase by 16 bits */
+#define FLASH_PSIZE_WORD           FLASH_CR_PSIZE_1  /*!< Flash program/erase by 32 bits */
+#define FLASH_PSIZE_DOUBLE_WORD    FLASH_CR_PSIZE    /*!< Flash program/erase by 64 bits */
+/**
+  * @}
+  */
+#endif /* FLASH_CR_PSIZE */
+
+
+/** @defgroup FLASH_Keys FLASH Keys
+  * @{
+  */
+#define FLASH_KEY1                 0x45670123U
+#define FLASH_KEY2                 0xCDEF89ABU
+#define FLASH_OPT_KEY1             0x08192A3BU
+#define FLASH_OPT_KEY2             0x4C5D6E7FU
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Sectors FLASH Sectors
+  * @{
+  */
+#define FLASH_SECTOR_0             0U       /*!< Sector Number 0   */
+#define FLASH_SECTOR_1             1U       /*!< Sector Number 1   */
+#define FLASH_SECTOR_2             2U       /*!< Sector Number 2   */
+#define FLASH_SECTOR_3             3U       /*!< Sector Number 3   */
+#define FLASH_SECTOR_4             4U       /*!< Sector Number 4   */
+#define FLASH_SECTOR_5             5U       /*!< Sector Number 5   */
+#define FLASH_SECTOR_6             6U       /*!< Sector Number 6   */
+#define FLASH_SECTOR_7             7U       /*!< Sector Number 7   */
+#if (FLASH_SECTOR_TOTAL == 128)
+#define FLASH_SECTOR_8             8U       /*!< Sector Number 8   */
+#define FLASH_SECTOR_9             9U       /*!< Sector Number 9   */
+#define FLASH_SECTOR_10            10U      /*!< Sector Number 10  */
+#define FLASH_SECTOR_11            11U      /*!< Sector Number 11  */
+#define FLASH_SECTOR_12            12U      /*!< Sector Number 12  */
+#define FLASH_SECTOR_13            13U      /*!< Sector Number 13  */
+#define FLASH_SECTOR_14            14U      /*!< Sector Number 14  */
+#define FLASH_SECTOR_15            15U      /*!< Sector Number 15  */
+#define FLASH_SECTOR_16            16U      /*!< Sector Number 16  */
+#define FLASH_SECTOR_17            17U      /*!< Sector Number 17  */
+#define FLASH_SECTOR_18            18U      /*!< Sector Number 18  */
+#define FLASH_SECTOR_19            19U      /*!< Sector Number 19  */
+#define FLASH_SECTOR_20            20U      /*!< Sector Number 20  */
+#define FLASH_SECTOR_21            21U      /*!< Sector Number 21  */
+#define FLASH_SECTOR_22            22U      /*!< Sector Number 22  */
+#define FLASH_SECTOR_23            23U      /*!< Sector Number 23  */
+#define FLASH_SECTOR_24            24U      /*!< Sector Number 24  */
+#define FLASH_SECTOR_25            25U      /*!< Sector Number 25  */
+#define FLASH_SECTOR_26            26U      /*!< Sector Number 26  */
+#define FLASH_SECTOR_27            27U      /*!< Sector Number 27  */
+#define FLASH_SECTOR_28            28U      /*!< Sector Number 28  */
+#define FLASH_SECTOR_29            29U      /*!< Sector Number 29  */
+#define FLASH_SECTOR_30            30U      /*!< Sector Number 30  */
+#define FLASH_SECTOR_31            31U      /*!< Sector Number 31  */
+#define FLASH_SECTOR_32            32U      /*!< Sector Number 32  */
+#define FLASH_SECTOR_33            33U      /*!< Sector Number 33  */
+#define FLASH_SECTOR_34            34U      /*!< Sector Number 34  */
+#define FLASH_SECTOR_35            35U      /*!< Sector Number 35  */
+#define FLASH_SECTOR_36            36U      /*!< Sector Number 36  */
+#define FLASH_SECTOR_37            37U      /*!< Sector Number 37  */
+#define FLASH_SECTOR_38            38U      /*!< Sector Number 38  */
+#define FLASH_SECTOR_39            39U      /*!< Sector Number 39  */
+#define FLASH_SECTOR_40            40U      /*!< Sector Number 40  */
+#define FLASH_SECTOR_41            41U      /*!< Sector Number 41  */
+#define FLASH_SECTOR_42            42U      /*!< Sector Number 42  */
+#define FLASH_SECTOR_43            43U      /*!< Sector Number 43  */
+#define FLASH_SECTOR_44            44U      /*!< Sector Number 44  */
+#define FLASH_SECTOR_45            45U      /*!< Sector Number 45  */
+#define FLASH_SECTOR_46            46U      /*!< Sector Number 46  */
+#define FLASH_SECTOR_47            47U      /*!< Sector Number 47  */
+#define FLASH_SECTOR_48            48U      /*!< Sector Number 48  */
+#define FLASH_SECTOR_49            49U      /*!< Sector Number 49  */
+#define FLASH_SECTOR_50            50U      /*!< Sector Number 50  */
+#define FLASH_SECTOR_51            51U      /*!< Sector Number 51  */
+#define FLASH_SECTOR_52            52U      /*!< Sector Number 52  */
+#define FLASH_SECTOR_53            53U      /*!< Sector Number 53  */
+#define FLASH_SECTOR_54            54U      /*!< Sector Number 54  */
+#define FLASH_SECTOR_55            55U      /*!< Sector Number 55  */
+#define FLASH_SECTOR_56            56U      /*!< Sector Number 56  */
+#define FLASH_SECTOR_57            57U      /*!< Sector Number 57  */
+#define FLASH_SECTOR_58            58U      /*!< Sector Number 58  */
+#define FLASH_SECTOR_59            59U      /*!< Sector Number 59  */
+#define FLASH_SECTOR_60            60U      /*!< Sector Number 60  */
+#define FLASH_SECTOR_61            61U      /*!< Sector Number 61  */
+#define FLASH_SECTOR_62            62U      /*!< Sector Number 62  */
+#define FLASH_SECTOR_63            63U      /*!< Sector Number 63  */
+#define FLASH_SECTOR_64            64U      /*!< Sector Number 64  */
+#define FLASH_SECTOR_65            65U      /*!< Sector Number 65  */
+#define FLASH_SECTOR_66            66U      /*!< Sector Number 66  */
+#define FLASH_SECTOR_67            67U      /*!< Sector Number 67  */
+#define FLASH_SECTOR_68            68U      /*!< Sector Number 68  */
+#define FLASH_SECTOR_69            69U      /*!< Sector Number 69  */
+#define FLASH_SECTOR_70            70U      /*!< Sector Number 70  */
+#define FLASH_SECTOR_71            71U      /*!< Sector Number 71  */
+#define FLASH_SECTOR_72            72U      /*!< Sector Number 72  */
+#define FLASH_SECTOR_73            73U      /*!< Sector Number 73  */
+#define FLASH_SECTOR_74            74U      /*!< Sector Number 74  */
+#define FLASH_SECTOR_75            75U      /*!< Sector Number 75  */
+#define FLASH_SECTOR_76            76U      /*!< Sector Number 76  */
+#define FLASH_SECTOR_77            77U      /*!< Sector Number 77  */
+#define FLASH_SECTOR_78            78U      /*!< Sector Number 78  */
+#define FLASH_SECTOR_79            79U      /*!< Sector Number 79  */
+#define FLASH_SECTOR_80            80U      /*!< Sector Number 80  */
+#define FLASH_SECTOR_81            81U      /*!< Sector Number 81  */
+#define FLASH_SECTOR_82            82U      /*!< Sector Number 82  */
+#define FLASH_SECTOR_83            83U      /*!< Sector Number 83  */
+#define FLASH_SECTOR_84            84U      /*!< Sector Number 84  */
+#define FLASH_SECTOR_85            85U      /*!< Sector Number 85  */
+#define FLASH_SECTOR_86            86U      /*!< Sector Number 86  */
+#define FLASH_SECTOR_87            87U      /*!< Sector Number 87  */
+#define FLASH_SECTOR_88            88U      /*!< Sector Number 88  */
+#define FLASH_SECTOR_89            89U      /*!< Sector Number 89  */
+#define FLASH_SECTOR_90            90U      /*!< Sector Number 90  */
+#define FLASH_SECTOR_91            91U      /*!< Sector Number 91  */
+#define FLASH_SECTOR_92            92U      /*!< Sector Number 92  */
+#define FLASH_SECTOR_93            93U      /*!< Sector Number 93  */
+#define FLASH_SECTOR_94            94U      /*!< Sector Number 94  */
+#define FLASH_SECTOR_95            95U      /*!< Sector Number 95  */
+#define FLASH_SECTOR_96            96U      /*!< Sector Number 96  */
+#define FLASH_SECTOR_97            97U      /*!< Sector Number 97  */
+#define FLASH_SECTOR_98            98U      /*!< Sector Number 98  */
+#define FLASH_SECTOR_99            99U      /*!< Sector Number 99  */
+#define FLASH_SECTOR_100           100U     /*!< Sector Number 100 */
+#define FLASH_SECTOR_101           101U     /*!< Sector Number 101 */
+#define FLASH_SECTOR_102           102U     /*!< Sector Number 102 */
+#define FLASH_SECTOR_103           103U     /*!< Sector Number 103 */
+#define FLASH_SECTOR_104           104U     /*!< Sector Number 104 */
+#define FLASH_SECTOR_105           105U     /*!< Sector Number 105 */
+#define FLASH_SECTOR_106           106U     /*!< Sector Number 106 */
+#define FLASH_SECTOR_107           107U     /*!< Sector Number 107 */
+#define FLASH_SECTOR_108           108U     /*!< Sector Number 108 */
+#define FLASH_SECTOR_109           109U     /*!< Sector Number 109 */
+#define FLASH_SECTOR_110           110U     /*!< Sector Number 110 */
+#define FLASH_SECTOR_111           111U     /*!< Sector Number 111 */
+#define FLASH_SECTOR_112           112U     /*!< Sector Number 112 */
+#define FLASH_SECTOR_113           113U     /*!< Sector Number 113 */
+#define FLASH_SECTOR_114           114U     /*!< Sector Number 114 */
+#define FLASH_SECTOR_115           115U     /*!< Sector Number 115 */
+#define FLASH_SECTOR_116           116U     /*!< Sector Number 116 */
+#define FLASH_SECTOR_117           117U     /*!< Sector Number 117 */
+#define FLASH_SECTOR_118           118U     /*!< Sector Number 118 */
+#define FLASH_SECTOR_119           119U     /*!< Sector Number 119 */
+#define FLASH_SECTOR_120           120U     /*!< Sector Number 120 */
+#define FLASH_SECTOR_121           121U     /*!< Sector Number 121 */
+#define FLASH_SECTOR_122           122U     /*!< Sector Number 122 */
+#define FLASH_SECTOR_123           123U     /*!< Sector Number 123 */
+#define FLASH_SECTOR_124           124U     /*!< Sector Number 124 */
+#define FLASH_SECTOR_125           125U     /*!< Sector Number 125 */
+#define FLASH_SECTOR_126           126U     /*!< Sector Number 126 */
+#define FLASH_SECTOR_127           127U     /*!< Sector Number 127 */
+#endif /* FLASH_SECTOR_TOTAL == 128 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
+  * @{
+  */
+/**
+  * @brief  Set the FLASH Latency.
+  * @param  __LATENCY__: FLASH Latency
+  *         The value of this parameter depend on device used within the same series
+  * @retval none
+  */
+#define __HAL_FLASH_SET_LATENCY(__LATENCY__) \
+                  MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__))
+
+/**
+  * @brief  Get the FLASH Latency.
+  * @retval FLASH Latency
+  *          The value of this parameter depend on device used within the same series
+  */
+#define __HAL_FLASH_GET_LATENCY()     (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
+
+/**
+  * @brief  Enable the specified FLASH interrupt.
+  * @param  __INTERRUPT__ : FLASH interrupt
+  *   In case of Bank 1 This parameter can be any combination of the following values:
+  *     @arg FLASH_IT_EOP_BANK1       : End of FLASH Bank 1 Operation Interrupt source
+  *     @arg FLASH_IT_WRPERR_BANK1    : Write Protection Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_PGSERR_BANK1    : Program Sequence Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_STRBERR_BANK1   : Strobe Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_INCERR_BANK1    : Inconsistency Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_OPERR_BANK1     : Operation Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_RDPERR_BANK1    : Read protection Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_RDSERR_BANK1    : Read secure Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_SNECCERR_BANK1  : Single ECC Error Correction on Bank 1 Interrupt source
+  *     @arg FLASH_IT_DBECCERR_BANK1  : Double Detection ECC Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_CRCEND_BANK1    : CRC End on Bank 1 Interrupt source
+  *     @arg FLASH_IT_CRCRDERR_BANK1  : CRC Read error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_ALL_BANK1       : All Bank 1 Interrupt sources
+  *
+  *   In case of Bank 2, this parameter can be any combination of the following values:
+  *     @arg FLASH_IT_EOP_BANK2       : End of FLASH Bank 2 Operation Interrupt source
+  *     @arg FLASH_IT_WRPERR_BANK2    : Write Protection Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_PGSERR_BANK2    : Program Sequence Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_STRBERR_BANK2   : Strobe Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_INCERR_BANK2    : Inconsistency Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_OPERR_BANK2     : Operation Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_RDPERR_BANK2    : Read protection Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_RDSERR_BANK2    : Read secure Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_SNECCERR_BANK2  : Single ECC Error Correction on Bank 2 Interrupt source
+  *     @arg FLASH_IT_DBECCERR_BANK2  : Double Detection ECC Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_CRCEND_BANK2    : CRC End on Bank 2 Interrupt source
+  *     @arg FLASH_IT_CRCRDERR_BANK2  : CRC Read error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_ALL_BANK2       : All Bank 2 Interrupt sources
+  * @retval none
+  */
+
+#define __HAL_FLASH_ENABLE_IT_BANK1(__INTERRUPT__)      (FLASH->CR1 |= (__INTERRUPT__))
+
+#define __HAL_FLASH_ENABLE_IT_BANK2(__INTERRUPT__)      (FLASH->CR2 |= ((__INTERRUPT__) & 0x7FFFFFFFU))
+
+#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)    (IS_FLASH_IT_BANK1(__INTERRUPT__) ? \
+                                                 __HAL_FLASH_ENABLE_IT_BANK1(__INTERRUPT__) : \
+                                                 __HAL_FLASH_ENABLE_IT_BANK2(__INTERRUPT__))
+
+
+/**
+  * @brief  Disable the specified FLASH interrupt.
+  * @param  __INTERRUPT__ : FLASH interrupt
+  *   In case of Bank 1 This parameter can be any combination of the following values:
+  *     @arg FLASH_IT_EOP_BANK1       : End of FLASH Bank 1 Operation Interrupt source
+  *     @arg FLASH_IT_WRPERR_BANK1    : Write Protection Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_PGSERR_BANK1    : Program Sequence Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_STRBERR_BANK1   : Strobe Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_INCERR_BANK1    : Inconsistency Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_OPERR_BANK1     : Operation Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_RDPERR_BANK1    : Read protection Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_RDSERR_BANK1    : Read secure Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_SNECCERR_BANK1  : Single ECC Error Correction on Bank 1 Interrupt source
+  *     @arg FLASH_IT_DBECCERR_BANK1  : Double Detection ECC Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_CRCEND_BANK1    : CRC End on Bank 1 Interrupt source
+  *     @arg FLASH_IT_CRCRDERR_BANK1  : CRC Read error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_ALL_BANK1       : All Bank 1 Interrupt sources
+  *
+  *   In case of Bank 2, this parameter can be any combination of the following values:
+  *     @arg FLASH_IT_EOP_BANK2       : End of FLASH Bank 2 Operation Interrupt source
+  *     @arg FLASH_IT_WRPERR_BANK2    : Write Protection Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_PGSERR_BANK2    : Program Sequence Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_STRBERR_BANK2   : Strobe Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_INCERR_BANK2    : Inconsistency Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_OPERR_BANK2     : Operation Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_RDPERR_BANK2    : Read protection Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_RDSERR_BANK2    : Read secure Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_SNECCERR_BANK2  : Single ECC Error Correction on Bank 2 Interrupt source
+  *     @arg FLASH_IT_DBECCERR_BANK2  : Double Detection ECC Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_CRCEND_BANK2    : CRC End on Bank 2 Interrupt source
+  *     @arg FLASH_IT_CRCRDERR_BANK2  : CRC Read error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_ALL_BANK2       : All Bank 2 Interrupt sources
+  * @retval none
+  */
+
+#define __HAL_FLASH_DISABLE_IT_BANK1(__INTERRUPT__)  (FLASH->CR1 &= ~(uint32_t)(__INTERRUPT__))
+
+#define __HAL_FLASH_DISABLE_IT_BANK2(__INTERRUPT__)  (FLASH->CR2 &= ~(uint32_t)((__INTERRUPT__) & 0x7FFFFFFFU))
+
+#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)  (IS_FLASH_IT_BANK1(__INTERRUPT__) ? \
+                                                __HAL_FLASH_DISABLE_IT_BANK1(__INTERRUPT__) : \
+                                                __HAL_FLASH_DISABLE_IT_BANK2(__INTERRUPT__))
+
+
+/**
+  * @brief  Checks whether the specified FLASH flag is set or not.
+  * @param  __FLAG__: specifies the FLASH flag to check.
+  *   In case of Bank 1 This parameter can be one of the following values :
+  *     @arg FLASH_FLAG_BSY_BANK1      : FLASH Bank 1 Busy flag
+  *     @arg FLASH_FLAG_WBNE_BANK1     : Write Buffer Not Empty on Bank 1 flag
+  *     @arg FLASH_FLAG_QW_BANK1       : Wait Queue on Bank 1 flag
+  *     @arg FLASH_FLAG_CRC_BUSY_BANK1 : CRC module is working on Bank 1 flag
+  *     @arg FLASH_FLAG_EOP_BANK1      : End Of Program on Bank 1 flag
+  *     @arg FLASH_FLAG_WRPERR_BANK1   : Write Protection Error on Bank 1 flag
+  *     @arg FLASH_FLAG_PGSERR_BANK1   : Program Sequence Error on Bank 1 flag
+  *     @arg FLASH_FLAG_STRBER_BANK1   : Program Alignment Error on Bank 1 flag
+  *     @arg FLASH_FLAG_INCERR_BANK1   : Inconsistency Error on Bank 1 flag
+  *     @arg FLASH_FLAG_OPERR_BANK1    : Operation Error on Bank 1 flag
+  *     @arg FLASH_FLAG_RDPERR_BANK1   : Read Protection Error on Bank 1 flag
+  *     @arg FLASH_FLAG_RDSERR_BANK1   : Read secure  Error on Bank 1 flag
+  *     @arg FLASH_FLAG_SNECCE_BANK1   : Single ECC Error Correction on Bank 1 flag
+  *     @arg FLASH_FLAG_DBECCE_BANK1   : Double Detection ECC Error on Bank 1 flag
+  *     @arg FLASH_FLAG_CRCEND_BANK1   : CRC End on Bank 1 flag
+  *     @arg FLASH_FLAG_CRCRDERR_BANK1 : CRC Read error on Bank 1 flag
+  *
+  *   In case of Bank 2 This parameter can be one of the following values :
+  *     @arg FLASH_FLAG_BSY_BANK2      : FLASH Bank 2 Busy flag
+  *     @arg FLASH_FLAG_WBNE_BANK2     : Write Buffer Not Empty on Bank 2 flag
+  *     @arg FLASH_FLAG_QW_BANK2       : Wait Queue on Bank 2 flag
+  *     @arg FLASH_FLAG_CRC_BUSY_BANK2 : CRC module is working on Bank 2 flag
+  *     @arg FLASH_FLAG_EOP_BANK2      : End Of Program on Bank 2 flag
+  *     @arg FLASH_FLAG_WRPERR_BANK2   : Write Protection Error on Bank 2 flag
+  *     @arg FLASH_FLAG_PGSERR_BANK2   : Program Sequence Error on Bank 2 flag
+  *     @arg FLASH_FLAG_STRBER_BANK2   : Program Alignment Error on Bank 2 flag
+  *     @arg FLASH_FLAG_INCERR_BANK2   : Inconsistency Error on Bank 2 flag
+  *     @arg FLASH_FLAG_OPERR_BANK2    : Operation Error on Bank 2 flag
+  *     @arg FLASH_FLAG_RDPERR_BANK2   : Read Protection Error on Bank 2 flag
+  *     @arg FLASH_FLAG_RDSERR_BANK2   : Read secure  Error on Bank 2 flag
+  *     @arg FLASH_FLAG_SNECCE_BANK2   : Single ECC Error Correction on Bank 2 flag
+  *     @arg FLASH_FLAG_DBECCE_BANK2   : Double Detection ECC Error on Bank 2 flag
+  *     @arg FLASH_FLAG_CRCEND_BANK2   : CRC End on Bank 2 flag
+  *     @arg FLASH_FLAG_CRCRDERR_BANK2 : CRC Read error on Bank 2 flag
+  * @retval The new state of FLASH_FLAG (SET or RESET).
+  */
+#define __HAL_FLASH_GET_FLAG_BANK1(__FLAG__)     (READ_BIT(FLASH->SR1, (__FLAG__)) == (__FLAG__))
+
+#define __HAL_FLASH_GET_FLAG_BANK2(__FLAG__)     (READ_BIT(FLASH->SR2, ((__FLAG__) & 0x7FFFFFFFU)) == (((__FLAG__) & 0x7FFFFFFFU)))
+
+#define __HAL_FLASH_GET_FLAG(__FLAG__)           (IS_FLASH_FLAG_BANK1(__FLAG__) ?  __HAL_FLASH_GET_FLAG_BANK1(__FLAG__) : \
+                                                  __HAL_FLASH_GET_FLAG_BANK2(__FLAG__))
+
+
+/**
+  * @brief  Clear the specified FLASH flag.
+  * @param  __FLAG__: specifies the FLASH flags to clear.
+  *    In case of Bank 1, this parameter can be any combination of the following values:
+  *     @arg FLASH_FLAG_EOP_BANK1        : End Of Program on Bank 1 flag
+  *     @arg FLASH_FLAG_WRPERR_BANK1     : Write Protection Error on Bank 1 flag
+  *     @arg FLASH_FLAG_PGSERR_BANK1     : Program Sequence Error on Bank 1 flag
+  *     @arg FLASH_FLAG_STRBER_BANK1     : Program Alignment Error on Bank 1 flag
+  *     @arg FLASH_FLAG_INCERR_BANK1     : Inconsistency Error on Bank 1 flag
+  *     @arg FLASH_FLAG_OPERR_BANK1      : Operation Error on Bank 1 flag
+  *     @arg FLASH_FLAG_RDPERR_BANK1     : Read Protection Error on Bank 1 flag
+  *     @arg FLASH_FLAG_RDSERR_BANK1     : Read secure  Error on Bank 1 flag
+  *     @arg FLASH_FLAG_SNECCE_BANK1     : Single ECC Error Correction on Bank 1 flag
+  *     @arg FLASH_FLAG_DBECCE_BANK1     : Double Detection ECC Error on Bank 1 flag
+  *     @arg FLASH_FLAG_CRCEND_BANK1     : CRC End on Bank 1 flag
+  *     @arg FLASH_FLAG_CRCRDERR_BANK1   : CRC Read error on Bank 1 flag
+  *     @arg FLASH_FLAG_ALL_ERRORS_BANK1 : All Bank 1 error flags
+  *     @arg FLASH_FLAG_ALL_BANK1        : All Bank 1 flags
+  *
+  *   In case of Bank 2, this parameter can be any combination of the following values :
+  *     @arg FLASH_FLAG_EOP_BANK2        : End Of Program on Bank 2 flag
+  *     @arg FLASH_FLAG_WRPERR_BANK2     : Write Protection Error on Bank 2 flag
+  *     @arg FLASH_FLAG_PGSERR_BANK2     : Program Sequence Error on Bank 2 flag
+  *     @arg FLASH_FLAG_STRBER_BANK2     : Program Alignment Error on Bank 2 flag
+  *     @arg FLASH_FLAG_INCERR_BANK2     : Inconsistency Error on Bank 2 flag
+  *     @arg FLASH_FLAG_OPERR_BANK2      : Operation Error on Bank 2 flag
+  *     @arg FLASH_FLAG_RDPERR_BANK2     : Read Protection Error on Bank 2 flag
+  *     @arg FLASH_FLAG_RDSERR_BANK2     : Read secure  Error on Bank 2 flag
+  *     @arg FLASH_FLAG_SNECCE_BANK2     : Single ECC Error Correction on Bank 2 flag
+  *     @arg FLASH_FLAG_DBECCE_BANK2     : Double Detection ECC Error on Bank 2 flag
+  *     @arg FLASH_FLAG_CRCEND_BANK2     : CRC End on Bank 2 flag
+  *     @arg FLASH_FLAG_CRCRDERR_BANK2   : CRC Read error on Bank 2 flag
+  *     @arg FLASH_FLAG_ALL_ERRORS_BANK2 : All Bank 2 error flags
+  *     @arg FLASH_FLAG_ALL_BANK2        : All Bank 2 flags
+  * @retval none
+  */
+
+#define __HAL_FLASH_CLEAR_FLAG_BANK1(__FLAG__)    WRITE_REG(FLASH->CCR1, (__FLAG__))
+
+#define __HAL_FLASH_CLEAR_FLAG_BANK2(__FLAG__)    WRITE_REG(FLASH->CCR2, ((__FLAG__) & 0x7FFFFFFFU))
+
+#define __HAL_FLASH_CLEAR_FLAG(__FLAG__)         (IS_FLASH_FLAG_BANK1(__FLAG__) ?  __HAL_FLASH_CLEAR_FLAG_BANK1(__FLAG__) : \
+                                                   __HAL_FLASH_CLEAR_FLAG_BANK2(__FLAG__))
+
+/**
+  * @}
+  */
+
+/* Include FLASH HAL Extension module */
+#include "stm32h7xx_hal_flash_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASH_Exported_Functions
+  * @{
+  */
+/** @addtogroup FLASH_Exported_Functions_Group1
+  * @{
+  */
+/* Program operation functions  ***********************************************/
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress);
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress);
+/* FLASH IRQ handler method */
+void HAL_FLASH_IRQHandler(void);
+/* Callbacks in non blocking modes */
+void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
+void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
+/**
+  * @}
+  */
+
+/** @addtogroup FLASH_Exported_Functions_Group2
+  * @{
+  */
+/* Peripheral Control functions  **********************************************/
+HAL_StatusTypeDef HAL_FLASH_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_Lock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
+/* Option bytes control */
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
+/**
+  * @}
+  */
+
+/** @addtogroup FLASH_Exported_Functions_Group3
+  * @{
+  */
+/* Peripheral State functions  ************************************************/
+uint32_t HAL_FLASH_GetError(void);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup FLASH_Private_Variables FLASH Private Variables
+  * @{
+  */
+extern FLASH_ProcessTypeDef pFlash;
+/**
+  * @}
+  */
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup FLASH_Private_Constants FLASH Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FLASH_Private_Macros FLASH Private Macros
+  * @{
+  */
+
+#if defined (FLASH_OPTCR_PG_OTP)
+#define IS_FLASH_TYPEPROGRAM(VALUE)      (((VALUE) == FLASH_TYPEPROGRAM_FLASHWORD) || \
+                                          ((VALUE) == FLASH_TYPEPROGRAM_OTPWORD))
+#else
+#define IS_FLASH_TYPEPROGRAM(VALUE)      ((VALUE) == FLASH_TYPEPROGRAM_FLASHWORD)
+#endif /* FLASH_OPTCR_PG_OTP */
+
+#define IS_FLASH_IT_BANK1(IT)            (((IT) & FLASH_IT_ALL_BANK1) == (IT))
+
+#define IS_FLASH_IT_BANK2(IT)            (((IT) & FLASH_IT_ALL_BANK2) == (IT))
+
+#define IS_FLASH_FLAG_BANK1(FLAG)        (((FLAG) & FLASH_FLAG_ALL_BANK1) == (FLAG))
+
+#define IS_FLASH_FLAG_BANK2(FLAG)        (((FLAG) & FLASH_FLAG_ALL_BANK2) == (FLAG))
+
+#define IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) (((ADDRESS) >= FLASH_BANK1_BASE) && ((ADDRESS) < FLASH_BANK2_BASE))
+#define IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS) (((ADDRESS) >= FLASH_BANK2_BASE ) && ((ADDRESS) <= FLASH_END))
+
+#if defined (FLASH_OPTCR_PG_OTP)
+#define IS_FLASH_PROGRAM_ADDRESS_OTP(ADDRESS)   (((ADDRESS) >= 0x08FFF000U) && ((ADDRESS) <= 0x08FFF3FFU))
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS)       (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || \
+                                                 IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS) || \
+                                                 IS_FLASH_PROGRAM_ADDRESS_OTP(ADDRESS))
+#else
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS)       (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || \
+                                                 IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS))
+#endif /* FLASH_OPTCR_PG_OTP */
+
+#define IS_BOOT_ADDRESS(ADDRESS)           ((ADDRESS) <= (0x3FFF0000U))
+
+#define IS_FLASH_BANK(BANK)                (((BANK) == FLASH_BANK_1)  || \
+                                            ((BANK) == FLASH_BANK_2)  || \
+                                            ((BANK) == FLASH_BANK_BOTH))
+
+#define IS_FLASH_BANK_EXCLUSIVE(BANK)      (((BANK) == FLASH_BANK_1)  || \
+                                            ((BANK) == FLASH_BANK_2))
+
+
+/**
+  * @}
+  */
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup FLASH_Private_Functions FLASH Private functions
+  * @{
+  */
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout, uint32_t Bank);
+HAL_StatusTypeDef FLASH_OB_WaitForLastOperation(uint32_t Timeout);
+HAL_StatusTypeDef FLASH_CRC_WaitForLastOperation(uint32_t Timeout, uint32_t Bank);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_FLASH_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h
new file mode 100644
index 00000000..834c5d23
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h
@@ -0,0 +1,910 @@
+/**
+  ******************************************************************************
+  * @file    stm32H7xx_hal_flash_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of FLASH HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_FLASH_EX_H
+#define STM32H7xx_HAL_FLASH_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FLASHEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Types FLASH Exported Types
+  * @{
+  */
+
+/**
+  * @brief  FLASH Erase structure definition
+  */
+typedef struct
+{
+  uint32_t TypeErase;   /*!< Mass erase or sector Erase.
+                             This parameter can be a value of @ref FLASHEx_Type_Erase */
+
+  uint32_t Banks;       /*!< Select banks to erase when Mass erase is enabled.
+                             This parameter must be a value of @ref FLASHEx_Banks */
+
+  uint32_t Sector;      /*!< Initial FLASH sector to erase when Mass erase is disabled
+                             This parameter must be a value of @ref FLASH_Sectors */
+
+  uint32_t NbSectors;   /*!< Number of sectors to be erased.
+                             This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
+
+  uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism
+                             This parameter must be a value of @ref FLASHEx_Voltage_Range */
+
+} FLASH_EraseInitTypeDef;
+
+
+/**
+  * @brief  FLASH Option Bytes Program structure definition
+  */
+typedef struct
+{
+  uint32_t OptionType;     /*!< Option byte to be configured.
+                                This parameter can be a value of @ref FLASHEx_Option_Type */
+
+  uint32_t WRPState;       /*!< Write protection activation or deactivation.
+                                This parameter can be a value of @ref FLASHEx_WRP_State */
+
+  uint32_t WRPSector;      /*!< Specifies the sector(s) to be write protected.
+                                The value of this parameter depend on device used within the same series */
+
+  uint32_t RDPLevel;       /*!< Set the read protection level.
+                                This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
+
+  uint32_t BORLevel;       /*!< Set the BOR Level.
+                                This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */
+
+  uint32_t USERType;       /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER).
+                                This parameter can be a combination of @ref FLASHEx_OB_USER_Type */
+
+  uint32_t USERConfig;     /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY /
+                                IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / IO_HSLV / SWAP_BANK_OPT */
+
+  uint32_t Banks;          /*!< Select banks for WRP , PCROP and secure area config .
+                                This parameter must be a value of @ref FLASHEx_Banks */
+
+  uint32_t PCROPConfig;    /*!< specifies if the PCROP area shall be erased or not
+                                when RDP level decreased from Level 1 to Level 0 or during a mass erase.
+                                This parameter must be a value of @ref FLASHEx_OB_PCROP_RDP enumeration */
+
+  uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP).
+                                This parameter must be a value between begin and end of a bank */
+
+  uint32_t PCROPEndAddr;   /*!< PCROP End address (used for OPTIONBYTE_PCROP).
+                                This parameter must be a value between PCROP Start address and end of a bank */
+
+  uint32_t BootConfig;     /*!< Specifies if the Boot Address to be configured BOOT_ADD0, BOOT_ADD1
+                                or both. This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION enumeration */
+
+  uint32_t BootAddr0;      /*!< Boot Address 0.
+                                This parameter must be a value between begin and end of a bank */
+
+  uint32_t BootAddr1;      /*!< Boot Address 1.
+                                This parameter must be a value between begin and end of a bank */
+#if defined(DUAL_CORE)
+  uint32_t CM4BootConfig;  /*!< specifies if the CM4 boot Address to be configured BOOT_ADD0, BOOT_ADD1
+                                or both.
+                                This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION enumeration */
+
+  uint32_t CM4BootAddr0;   /*!< CM4 Boot Address 0.
+                                This parameter must be a value between begin and end of a bank */
+
+  uint32_t CM4BootAddr1;   /*!< CM4 Boot Address 1.
+                                This parameter must be a value between begin and end of a bank */
+#endif /*DUAL_CORE*/
+
+  uint32_t SecureAreaConfig;    /*!< specifies if the bank secured area shall be erased or not
+                                     when RDP level decreased from Level 1 to Level 0 or during a mass erase.
+                                     This parameter must be a value of @ref FLASHEx_OB_SECURE_RDP enumeration */
+
+  uint32_t SecureAreaStartAddr; /*!< Bank Secure area Start address.
+                                     This parameter must be a value between begin address and end address of bank1 */
+
+  uint32_t SecureAreaEndAddr;   /*!< Bank Secure area End address.
+                                     This parameter must be a value between Secure Area Start address and end address of a bank1 */
+
+#if defined (FLASH_OTPBL_LOCKBL)
+  uint32_t OTPBlockLock;   /*!< Specifies the OTP block(s) to be locked.
+                                This parameter must be a value of @ref FLASHEx_OTP_Blocks */
+#endif /* FLASH_OTPBL_LOCKBL */
+
+} FLASH_OBProgramInitTypeDef;
+
+/**
+  * @brief  FLASH Erase structure definition
+  */
+typedef struct
+{
+  uint32_t TypeCRC;      /*!< CRC Selection Type.
+                              This parameter can be a value of @ref FLASHEx_CRC_Selection_Type */
+
+  uint32_t BurstSize;    /*!< CRC Burst Size.
+                              This parameter can be a value of @ref FLASHEx_CRC_Burst_Size */
+
+  uint32_t Bank;         /*!< Select bank where CRC computation is enabled.
+                              This parameter must be FLASH_BANK_1 or FLASH_BANK_2 */
+
+  uint32_t Sector;       /*!< Initial FLASH sector from which starts the CRC computation
+                              This parameter must be a value of @ref FLASH_Sectors */
+
+  uint32_t NbSectors;    /*!< Number of sectors to be computed.
+                              This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
+
+  uint32_t CRCStartAddr; /*!< CRC Start address.
+                              This parameter must be a value between begin address and end address of a bank */
+
+  uint32_t CRCEndAddr;   /*!< CRC End address.
+                              This parameter must be a value between CRC Start address and end address of a bank */
+
+} FLASH_CRCInitTypeDef;
+
+/**
+  * @}
+  */
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants
+  * @{
+  */
+
+/** @defgroup FLASHEx_Type_Erase FLASH Type Erase
+  * @{
+  */
+#define FLASH_TYPEERASE_SECTORS      0x00U  /*!< Sectors erase only          */
+#define FLASH_TYPEERASE_MASSERASE    0x01U  /*!< Flash Mass erase activation */
+/**
+  * @}
+  */
+
+#if defined (FLASH_CR_PSIZE)
+/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range
+  * @{
+  */
+#define FLASH_VOLTAGE_RANGE_1        0x00000000U       /*!< Flash program/erase by 8 bits  */
+#define FLASH_VOLTAGE_RANGE_2        FLASH_CR_PSIZE_0  /*!< Flash program/erase by 16 bits */
+#define FLASH_VOLTAGE_RANGE_3        FLASH_CR_PSIZE_1  /*!< Flash program/erase by 32 bits */
+#define FLASH_VOLTAGE_RANGE_4        FLASH_CR_PSIZE    /*!< Flash program/erase by 64 bits */
+/**
+  * @}
+  */
+#endif /* FLASH_CR_PSIZE */
+
+/** @defgroup FLASHEx_WRP_State FLASH WRP State
+  * @{
+  */
+#define OB_WRPSTATE_DISABLE          0x00000000U  /*!< Disable the write protection of the desired bank 1 sectors */
+#define OB_WRPSTATE_ENABLE           0x00000001U  /*!< Enable the write protection of the desired bank 1 sectors  */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Option_Type FLASH Option Type
+  * @{
+  */
+#define OPTIONBYTE_WRP           0x01U  /*!< WRP option byte configuration  */
+#define OPTIONBYTE_RDP           0x02U  /*!< RDP option byte configuration  */
+#define OPTIONBYTE_USER          0x04U  /*!< USER option byte configuration */
+#define OPTIONBYTE_PCROP         0x08U  /*!< PCROP option byte configuration */
+#define OPTIONBYTE_BOR           0x10U  /*!< BOR option byte configuration */
+#define OPTIONBYTE_SECURE_AREA   0x20U  /*!< secure area option byte configuration */
+#if defined (DUAL_CORE)
+#define OPTIONBYTE_CM7_BOOTADD   0x40U  /*!< CM7 BOOT ADD option byte configuration */
+#define OPTIONBYTE_CM4_BOOTADD   0x80U  /*!< CM4 BOOT ADD option byte configuration */
+#define OPTIONBYTE_BOOTADD       OPTIONBYTE_CM7_BOOTADD  /*!< BOOT ADD option byte configuration */
+#else /* Single core */
+#define OPTIONBYTE_BOOTADD       0x40U  /*!< BOOT ADD option byte configuration */
+#endif /*DUAL_CORE*/
+#if defined (FLASH_OTPBL_LOCKBL)
+#define OPTIONBYTE_OTP_LOCK      0x80U  /*!< OTP Lock option byte configuration */
+#endif /* FLASH_OTPBL_LOCKBL */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection
+  * @{
+  */
+#define OB_RDP_LEVEL_0       0xAA00U
+#define OB_RDP_LEVEL_1       0x5500U
+#define OB_RDP_LEVEL_2       0xCC00U   /*!< Warning: When enabling read protection level 2
+                                            it s no more possible to go back to level 1 or 0 */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Option_Bytes_WWatchdog FLASH Option Bytes WWatchdog
+  * @{
+  */
+#define OB_WWDG_SW           0x10U  /*!< Software WWDG selected */
+#define OB_WWDG_HW           0x00U  /*!< Hardware WWDG selected */
+/**
+  * @}
+  */
+
+
+/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog
+  * @{
+  */
+#define OB_IWDG_SW           0x20U  /*!< Software IWDG selected */
+#define OB_IWDG_HW           0x00U  /*!< Hardware IWDG selected */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP
+  * @{
+  */
+#define OB_STOP_NO_RST       0x40U /*!< No reset generated when entering in STOP */
+#define OB_STOP_RST          0x00U /*!< Reset generated when entering in STOP    */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY
+  * @{
+  */
+#define OB_STDBY_NO_RST      0x80U /*!< No reset generated when entering in STANDBY */
+#define OB_STDBY_RST         0x00U /*!< Reset generated when entering in STANDBY    */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP
+  * @{
+  */
+#define OB_IWDG_STOP_FREEZE  0x00000000U /*!< Freeze IWDG counter in STOP mode */
+#define OB_IWDG_STOP_ACTIVE  FLASH_OPTSR_FZ_IWDG_STOP /*!< IWDG counter active in STOP mode */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY
+  * @{
+  */
+#define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Freeze IWDG counter in STANDBY mode */
+#define OB_IWDG_STDBY_ACTIVE FLASH_OPTSR_FZ_IWDG_SDBY  /*!< IWDG counter active in STANDBY mode */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level
+  * @{
+  */
+#define OB_BOR_LEVEL0        0x00000000U                /*!< Reset level threshold is set to 1.6V */
+#define OB_BOR_LEVEL1        FLASH_OPTSR_BOR_LEV_0      /*!< Reset level threshold is set to 2.1V */
+#define OB_BOR_LEVEL2        FLASH_OPTSR_BOR_LEV_1      /*!< Reset level threshold is set to 2.4V */
+#define OB_BOR_LEVEL3        (FLASH_OPTSR_BOR_LEV_1 | FLASH_OPTSR_BOR_LEV_0) /*!< Reset level threshold is set to 2.7V  */
+/**
+  * @}
+  */
+
+
+
+/** @defgroup FLASHEx_Boot_Address FLASH Boot Address
+  * @{
+  */
+#define OB_BOOTADDR_ITCM_RAM     0x0000U  /*!< Boot from ITCM RAM (0x00000000)                 */
+#define OB_BOOTADDR_SYSTEM       0x0040U  /*!< Boot from System memory bootloader (0x00100000) */
+#define OB_BOOTADDR_ITCM_FLASH   0x0080U  /*!< Boot from Flash on ITCM interface (0x00200000)  */
+#define OB_BOOTADDR_AXIM_FLASH   0x2000U  /*!< Boot from Flash on AXIM interface (0x08000000)  */
+#define OB_BOOTADDR_DTCM_RAM     0x8000U  /*!< Boot from DTCM RAM (0x20000000)                 */
+#define OB_BOOTADDR_SRAM1        0x8004U  /*!< Boot from SRAM1 (0x20010000)                    */
+#define OB_BOOTADDR_SRAM2        0x8013U  /*!< Boot from SRAM2 (0x2004C000)                    */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Latency FLASH Latency
+  * @{
+  */
+#define FLASH_LATENCY_0          FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero Latency cycle      */
+#define FLASH_LATENCY_1          FLASH_ACR_LATENCY_1WS   /*!< FLASH One Latency cycle       */
+#define FLASH_LATENCY_2          FLASH_ACR_LATENCY_2WS   /*!< FLASH Two Latency cycles      */
+#define FLASH_LATENCY_3          FLASH_ACR_LATENCY_3WS   /*!< FLASH Three Latency cycles    */
+#define FLASH_LATENCY_4          FLASH_ACR_LATENCY_4WS   /*!< FLASH Four Latency cycles     */
+#define FLASH_LATENCY_5          FLASH_ACR_LATENCY_5WS   /*!< FLASH Five Latency cycles     */
+#define FLASH_LATENCY_6          FLASH_ACR_LATENCY_6WS   /*!< FLASH Six Latency cycles      */
+#define FLASH_LATENCY_7          FLASH_ACR_LATENCY_7WS   /*!< FLASH Seven Latency cycles    */
+#define FLASH_LATENCY_8          FLASH_ACR_LATENCY_8WS   /*!< FLASH Eight Latency cycle     */
+#define FLASH_LATENCY_9          FLASH_ACR_LATENCY_9WS   /*!< FLASH Nine Latency cycle      */
+#define FLASH_LATENCY_10         FLASH_ACR_LATENCY_10WS  /*!< FLASH Ten Latency cycles      */
+#define FLASH_LATENCY_11         FLASH_ACR_LATENCY_11WS  /*!< FLASH Eleven Latency cycles   */
+#define FLASH_LATENCY_12         FLASH_ACR_LATENCY_12WS  /*!< FLASH Twelve Latency cycles   */
+#define FLASH_LATENCY_13         FLASH_ACR_LATENCY_13WS  /*!< FLASH Thirteen Latency cycles */
+#define FLASH_LATENCY_14         FLASH_ACR_LATENCY_14WS  /*!< FLASH Fourteen Latency cycles */
+#define FLASH_LATENCY_15         FLASH_ACR_LATENCY_15WS  /*!< FLASH Fifteen Latency cycles  */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Banks FLASH Banks
+  * @{
+  */
+#define FLASH_BANK_1             0x01U                         /*!< Bank 1   */
+#define FLASH_BANK_2             0x02U                         /*!< Bank 2   */
+#define FLASH_BANK_BOTH          (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2  */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_OB_PCROP_RDP  FLASHEx OB PCROP RDP
+  * @{
+  */
+#define OB_PCROP_RDP_NOT_ERASE   0x00000000U     /*!< PCROP area is not erased when the RDP level
+                                                      is decreased from Level 1 to Level 0 or during a mass erase */
+#define OB_PCROP_RDP_ERASE       FLASH_PRAR_DMEP /*!< PCROP area is erased when the RDP level is
+                                                      decreased from Level 1 to Level 0 (full mass erase) */
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
+  * @{
+  */
+#if (FLASH_SECTOR_TOTAL == 128)
+#define OB_WRP_SECTOR_0TO3       0x00000001U /*!< Write protection of Sector0  to Sector3    */
+#define OB_WRP_SECTOR_4TO7       0x00000002U /*!< Write protection of Sector4  to Sector7    */
+#define OB_WRP_SECTOR_8TO11      0x00000004U /*!< Write protection of Sector8  to Sector11   */
+#define OB_WRP_SECTOR_12TO15     0x00000008U /*!< Write protection of Sector12 to Sector15   */
+#define OB_WRP_SECTOR_16TO19     0x00000010U /*!< Write protection of Sector16 to Sector19   */
+#define OB_WRP_SECTOR_20TO23     0x00000020U /*!< Write protection of Sector20 to Sector23   */
+#define OB_WRP_SECTOR_24TO27     0x00000040U /*!< Write protection of Sector24 to Sector27   */
+#define OB_WRP_SECTOR_28TO31     0x00000080U /*!< Write protection of Sector28 to Sector31   */
+#define OB_WRP_SECTOR_32TO35     0x00000100U /*!< Write protection of Sector32 to Sector35   */
+#define OB_WRP_SECTOR_36TO39     0x00000200U /*!< Write protection of Sector36 to Sector39   */
+#define OB_WRP_SECTOR_40TO43     0x00000400U /*!< Write protection of Sector40 to Sector43   */
+#define OB_WRP_SECTOR_44TO47     0x00000800U /*!< Write protection of Sector44 to Sector47   */
+#define OB_WRP_SECTOR_48TO51     0x00001000U /*!< Write protection of Sector48 to Sector51   */
+#define OB_WRP_SECTOR_52TO55     0x00002000U /*!< Write protection of Sector52 to Sector55   */
+#define OB_WRP_SECTOR_56TO59     0x00004000U /*!< Write protection of Sector56 to Sector59   */
+#define OB_WRP_SECTOR_60TO63     0x00008000U /*!< Write protection of Sector60 to Sector63   */
+#define OB_WRP_SECTOR_64TO67     0x00010000U /*!< Write protection of Sector64 to Sector67   */
+#define OB_WRP_SECTOR_68TO71     0x00020000U /*!< Write protection of Sector68 to Sector71   */
+#define OB_WRP_SECTOR_72TO75     0x00040000U /*!< Write protection of Sector72 to Sector75   */
+#define OB_WRP_SECTOR_76TO79     0x00080000U /*!< Write protection of Sector76 to Sector79   */
+#define OB_WRP_SECTOR_80TO83     0x00100000U /*!< Write protection of Sector80 to Sector83   */
+#define OB_WRP_SECTOR_84TO87     0x00200000U /*!< Write protection of Sector84 to Sector87   */
+#define OB_WRP_SECTOR_88TO91     0x00400000U /*!< Write protection of Sector88 to Sector91   */
+#define OB_WRP_SECTOR_92TO95     0x00800000U /*!< Write protection of Sector92 to Sector95   */
+#define OB_WRP_SECTOR_96TO99     0x01000000U /*!< Write protection of Sector96  to Sector99  */
+#define OB_WRP_SECTOR_100TO103   0x02000000U /*!< Write protection of Sector100 to Sector103 */
+#define OB_WRP_SECTOR_104TO107   0x04000000U /*!< Write protection of Sector104 to Sector107 */
+#define OB_WRP_SECTOR_108TO111   0x08000000U /*!< Write protection of Sector108 to Sector111 */
+#define OB_WRP_SECTOR_112TO115   0x10000000U /*!< Write protection of Sector112 to Sector115 */
+#define OB_WRP_SECTOR_116TO119   0x20000000U /*!< Write protection of Sector116 to Sector119 */
+#define OB_WRP_SECTOR_120TO123   0x40000000U /*!< Write protection of Sector120 to Sector123 */
+#define OB_WRP_SECTOR_124TO127   0x80000000U /*!< Write protection of Sector124 to Sector127 */
+#define OB_WRP_SECTOR_ALL        0xFFFFFFFFU /*!< Write protection of all Sectors            */
+#else
+#define OB_WRP_SECTOR_0          0x00000001U /*!< Write protection of Sector0                */
+#define OB_WRP_SECTOR_1          0x00000002U /*!< Write protection of Sector1                */
+#define OB_WRP_SECTOR_2          0x00000004U /*!< Write protection of Sector2                */
+#define OB_WRP_SECTOR_3          0x00000008U /*!< Write protection of Sector3                */
+#define OB_WRP_SECTOR_4          0x00000010U /*!< Write protection of Sector4                */
+#define OB_WRP_SECTOR_5          0x00000020U /*!< Write protection of Sector5                */
+#define OB_WRP_SECTOR_6          0x00000040U /*!< Write protection of Sector6                */
+#define OB_WRP_SECTOR_7          0x00000080U /*!< Write protection of Sector7                */
+#define OB_WRP_SECTOR_ALL        0x000000FFU /*!< Write protection of all Sectors            */
+#endif /* FLASH_SECTOR_TOTAL == 128 */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_OB_SECURITY  FLASHEx OB SECURITY
+  * @{
+  */
+#define OB_SECURITY_DISABLE   0x00000000U             /*!< security enabled */
+#define OB_SECURITY_ENABLE    FLASH_OPTSR_SECURITY    /*!< security disabled */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_OB_ST_RAM_SIZE  FLASHEx OB ST RAM SIZE
+  * @{
+  */
+#define OB_ST_RAM_SIZE_2KB    0x00000000U               /*!< 2 Kbytes reserved to ST code */
+#define OB_ST_RAM_SIZE_4KB    FLASH_OPTSR_ST_RAM_SIZE_0 /*!< 4 Kbytes reserved to ST code */
+#define OB_ST_RAM_SIZE_8KB    FLASH_OPTSR_ST_RAM_SIZE_1 /*!< 8 Kbytes reserved to ST code */
+#define OB_ST_RAM_SIZE_16KB   FLASH_OPTSR_ST_RAM_SIZE   /*!< 16 Kbytes reserved to ST code */
+/**
+  * @}
+  */
+
+#if defined(DUAL_CORE)
+/** @defgroup FLASHEx_OB_BCM7  FLASHEx OB BCM7
+  * @{
+  */
+#define OB_BCM7_DISABLE       0x00000000U              /*!< CM7 Boot disabled */
+#define OB_BCM7_ENABLE        FLASH_OPTSR_BCM7         /*!< CM7 Boot enabled */
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_OB_BCM4  FLASHEx OB BCM4
+  * @{
+  */
+#define OB_BCM4_DISABLE       0x00000000U              /*!< CM4 Boot disabled */
+#define OB_BCM4_ENABLE        FLASH_OPTSR_BCM4         /*!< CM4 Boot enabled */
+/**
+  * @}
+  */
+#endif /* DUAL_CORE */
+
+/** @defgroup FLASHEx_OB_IWDG1_SW  FLASHEx OB IWDG1 SW
+  * @{
+  */
+#define OB_IWDG1_SW            FLASH_OPTSR_IWDG1_SW /*!< Hardware independent watchdog 1 */
+#define OB_IWDG1_HW            0x00000000U          /*!< Software independent watchdog 1 */
+/**
+  * @}
+  */
+
+#if defined(DUAL_CORE)
+/** @defgroup FLASHEx_OB_IWDG2_SW  FLASHEx OB IWDG2 SW
+  * @{
+  */
+#define OB_IWDG2_SW            FLASH_OPTSR_IWDG2_SW  /*!< Hardware independent watchdog 2*/
+#define OB_IWDG2_HW            0x00000000U           /*!< Software independent watchdog 2*/
+/**
+  * @}
+  */
+#endif
+
+/** @defgroup FLASHEx_OB_NRST_STOP_D1  FLASHEx OB NRST STOP D1
+  * @{
+  */
+#define OB_STOP_RST_D1         0x00000000U              /*!< Reset generated when entering the D1 to stop mode */
+#define OB_STOP_NO_RST_D1      FLASH_OPTSR_NRST_STOP_D1 /*!< No reset generated when entering the D1 to stop mode */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_OB_NRST_STDBY_D1  FLASHEx OB NRST STDBY D1
+  * @{
+  */
+#define OB_STDBY_RST_D1        0x00000000U              /*!< Reset generated when entering the D1 to standby mode */
+#define OB_STDBY_NO_RST_D1     FLASH_OPTSR_NRST_STBY_D1 /*!< No reset generated when entering the D1 to standby mode */
+/**
+  * @}
+  */
+
+#if defined (DUAL_CORE)
+/** @defgroup FLASHEx_OB_NRST_STOP_D2  FLASHEx OB NRST STOP D2
+  * @{
+  */
+#define OB_STOP_RST_D2         0x00000000U              /*!< Reset generated when entering the D2 to stop mode */
+#define OB_STOP_NO_RST_D2      FLASH_OPTSR_NRST_STOP_D2 /*!< No reset generated when entering the D2 to stop mode */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_OB_NRST_STDBY_D2  FLASHEx OB NRST STDBY D2
+  * @{
+  */
+#define OB_STDBY_RST_D2        0x00000000U              /*!< Reset generated when entering the D2 to standby mode */
+#define OB_STDBY_NO_RST_D2     FLASH_OPTSR_NRST_STBY_D2 /*!< No reset generated when entering the D2 to standby mode */
+/**
+  * @}
+  */
+#endif /* DUAL_CORE */
+
+/** @defgroup FLASHEx_OB_SWAP_BANK  FLASHEx OB SWAP BANK
+  * @{
+  */
+#define OB_SWAP_BANK_DISABLE   0x00000000U               /*!< Bank swap disabled */
+#define OB_SWAP_BANK_ENABLE    FLASH_OPTSR_SWAP_BANK_OPT /*!< Bank swap enabled */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_OB_IOHSLV FLASHEx OB IOHSLV
+  * @{
+  */
+#define OB_IOHSLV_DISABLE      0x00000000U         /*!< IOHSLV disabled */
+#define OB_IOHSLV_ENABLE       FLASH_OPTSR_IO_HSLV /*!< IOHSLV enabled */
+/**
+  * @}
+  */
+
+#if defined (FLASH_OPTSR_VDDMMC_HSLV)
+/** @defgroup FLASHEx_OB_VDDMMC_HSLV FLASHEx OB VDDMMC HSLV
+  * @{
+  */
+#define OB_VDDMMC_HSLV_DISABLE 0x00000000U             /*!< VDDMMC HSLV disabled */
+#define OB_VDDMMC_HSLV_ENABLE  FLASH_OPTSR_VDDMMC_HSLV /*!< VDDMMC HSLV enabled */
+/**
+  * @}
+  */
+#endif /* FLASH_OPTSR_VDDMMC_HSLV */
+
+/** @defgroup FLASHEx_OB_BOOT_OPTION  FLASHEx OB BOOT OPTION
+  * @{
+  */
+#define OB_BOOT_ADD0           0x01U       /*!< Select Boot Address 0 */
+#define OB_BOOT_ADD1           0x02U       /*!< Select Boot Address 1 */
+#define OB_BOOT_ADD_BOTH       0x03U       /*!< Select Boot Address 0 and 1 */
+/**
+  * @}
+  */
+
+ /** @defgroup FLASHEx_OB_USER_Type  FLASHEx OB USER Type
+  * @{
+  */
+#define OB_USER_IWDG1_SW          0x0001U /*!< Independent watchdog selection */
+#define OB_USER_NRST_STOP_D1      0x0002U /*!< Reset when entering Stop mode selection*/
+#define OB_USER_NRST_STDBY_D1     0x0004U /*!< Reset when entering standby mode selection*/
+#define OB_USER_IWDG_STOP         0x0008U /*!< Independent watchdog counter freeze in stop mode */
+#define OB_USER_IWDG_STDBY        0x0010U /*!< Independent watchdog counter freeze in standby mode */
+#define OB_USER_ST_RAM_SIZE       0x0020U /*!< dedicated DTCM Ram size selection */
+#define OB_USER_SECURITY          0x0040U /*!< security selection */
+#define OB_USER_IOHSLV            0x0080U /*!< IO HSLV selection */
+#define OB_USER_SWAP_BANK         0x0100U /*!< Bank swap selection */
+#if defined (FLASH_OPTSR_VDDMMC_HSLV)
+#define OB_USER_VDDMMC_HSLV       0x0200U /*!< VDDMMC HSLV selection */
+#endif /* FLASH_OPTSR_VDDMMC_HSLV */
+#if defined (DUAL_CORE)
+#define OB_USER_IWDG2_SW          0x0200U /*!< Window watchdog selection */
+#define OB_USER_BCM4              0x0400U /*!< CM4 boot selection */
+#define OB_USER_BCM7              0x0800U /*!< CM7 boot selection */
+#define OB_USER_NRST_STOP_D2      0x1000U /*!< Reset when entering Stop mode selection*/
+#define OB_USER_NRST_STDBY_D2     0x2000U /*!< Reset when entering standby mode selection*/
+#endif /*DUAL_CORE*/
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_OB_SECURE_RDP  FLASHEx OB SECURE RDP
+  * @{
+  */
+#define OB_SECURE_RDP_NOT_ERASE   0x00000000U     /*!< Secure area is not erased when the RDP level
+                                                       is decreased from Level 1 to Level 0 or during a mass erase */
+#define OB_SECURE_RDP_ERASE       FLASH_SCAR_DMES /*!< Secure area is erased when the RDP level is
+                                                       decreased from Level 1 to Level 0 (full mass erase) */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_CRC_Selection_Type FLASH CRC Selection Type
+  * @{
+  */
+#define FLASH_CRC_ADDR         0x00000000U              /*!< CRC selection type by address  */
+#define FLASH_CRC_SECTORS      FLASH_CRCCR_CRC_BY_SECT  /*!< CRC selection type by sectors  */
+#define FLASH_CRC_BANK         (FLASH_CRCCR_ALL_BANK | FLASH_CRCCR_CRC_BY_SECT) /*!< CRC selection type by bank */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_CRC_Burst_Size FLASH CRC Burst Size
+  * @{
+  */
+#define FLASH_CRC_BURST_SIZE_4    0x00000000U              /*!< Every burst has a size of 4 Flash words (256-bit)  */
+#define FLASH_CRC_BURST_SIZE_16   FLASH_CRCCR_CRC_BURST_0  /*!< Every burst has a size of 16 Flash words (256-bit)   */
+#define FLASH_CRC_BURST_SIZE_64   FLASH_CRCCR_CRC_BURST_1  /*!< Every burst has a size of 64 Flash words (256-bit)   */
+#define FLASH_CRC_BURST_SIZE_256  FLASH_CRCCR_CRC_BURST    /*!< Every burst has a size of 256 Flash words (256-bit) */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Programming_Delay FLASH Programming Delay
+  * @{
+  */
+#define FLASH_PROGRAMMING_DELAY_0   0x00000000U            /*!< programming delay set for Flash running at 70 MHz or below          */
+#define FLASH_PROGRAMMING_DELAY_1   FLASH_ACR_WRHIGHFREQ_0 /*!< programming delay set for Flash running between 70 MHz and 185 MHz  */
+#define FLASH_PROGRAMMING_DELAY_2   FLASH_ACR_WRHIGHFREQ_1 /*!< programming delay set for Flash running between 185 MHz and 225 MHz */
+#define FLASH_PROGRAMMING_DELAY_3   FLASH_ACR_WRHIGHFREQ   /*!< programming delay set for Flash at startup */
+/**
+  * @}
+  */
+
+#if defined (FLASH_OTPBL_LOCKBL)
+/** @defgroup FLASHEx_OTP_Blocks FLASH OTP blocks
+  * @{
+  */
+#define FLASH_OTP_BLOCK_0          0x00000001U /*!< OTP Block0     */
+#define FLASH_OTP_BLOCK_1          0x00000002U /*!< OTP Block1     */
+#define FLASH_OTP_BLOCK_2          0x00000004U /*!< OTP Block2     */
+#define FLASH_OTP_BLOCK_3          0x00000008U /*!< OTP Block3     */
+#define FLASH_OTP_BLOCK_4          0x00000010U /*!< OTP Block4     */
+#define FLASH_OTP_BLOCK_5          0x00000020U /*!< OTP Block5     */
+#define FLASH_OTP_BLOCK_6          0x00000040U /*!< OTP Block6     */
+#define FLASH_OTP_BLOCK_7          0x00000080U /*!< OTP Block7     */
+#define FLASH_OTP_BLOCK_8          0x00000100U /*!< OTP Block8     */
+#define FLASH_OTP_BLOCK_9          0x00000200U /*!< OTP Block9     */
+#define FLASH_OTP_BLOCK_10         0x00000400U /*!< OTP Block10    */
+#define FLASH_OTP_BLOCK_11         0x00000800U /*!< OTP Block11    */
+#define FLASH_OTP_BLOCK_12         0x00001000U /*!< OTP Block12    */
+#define FLASH_OTP_BLOCK_13         0x00002000U /*!< OTP Block13    */
+#define FLASH_OTP_BLOCK_14         0x00004000U /*!< OTP Block14    */
+#define FLASH_OTP_BLOCK_15         0x00008000U /*!< OTP Block15    */
+#define FLASH_OTP_BLOCK_ALL        0x0000FFFFU /*!< OTP All Blocks */
+/**
+  * @}
+  */
+#endif /* FLASH_OTPBL_LOCKBL */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Macros FLASH Exported Macros
+  * @{
+  */
+/**
+  * @brief  Calculate the FLASH Boot Base Adress (BOOT_ADD0 or BOOT_ADD1)
+  * @note   Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14].
+  * @param  __ADDRESS__: FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB)
+  * @retval The FLASH Boot Base Adress
+  */
+#define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14U)
+ /**
+  * @}
+  */
+
+#if defined (FLASH_CR_PSIZE)
+/**
+  * @brief  Set the FLASH Program/Erase parallelism.
+  * @param  __PSIZE__ FLASH Program/Erase parallelism
+  *         This parameter can be a value of @ref FLASH_Program_Parallelism
+  * @param  __BANK__: Flash bank (FLASH_BANK_1 or FLASH_BANK_2)
+  * @retval none
+  */
+#define __HAL_FLASH_SET_PSIZE(__PSIZE__, __BANK__) (((__BANK__) == FLASH_BANK_1)  ? \
+                              MODIFY_REG(FLASH->CR1, FLASH_CR_PSIZE, (__PSIZE__)) : \
+                              MODIFY_REG(FLASH->CR2, FLASH_CR_PSIZE, (__PSIZE__)))
+
+/**
+  * @brief  Get the FLASH Program/Erase parallelism.
+  * @param  __BANK__ Flash bank (FLASH_BANK_1 or FLASH_BANK_2)
+  * @retval FLASH Program/Erase parallelism
+  *         This return value can be a value of @ref FLASH_Program_Parallelism
+  */
+#define __HAL_FLASH_GET_PSIZE(__BANK__) (((__BANK__) == FLASH_BANK_1) ? \
+                              READ_BIT((FLASH->CR1), FLASH_CR_PSIZE)  : \
+                              READ_BIT((FLASH->CR2), FLASH_CR_PSIZE))
+#endif /* FLASH_CR_PSIZE */
+
+/**
+  * @brief  Set the FLASH Programming Delay.
+  * @param  __DELAY__ FLASH Programming Delay
+  *         This parameter can be a value of @ref FLASHEx_Programming_Delay
+  * @retval none
+  */
+#define __HAL_FLASH_SET_PROGRAM_DELAY(__DELAY__)  MODIFY_REG(FLASH->ACR, FLASH_ACR_WRHIGHFREQ, (__DELAY__))
+
+/**
+  * @brief  Get the FLASH Programming Delay.
+  * @retval FLASH Programming Delay
+  *         This return value can be a value of @ref FLASHEx_Programming_Delay
+  */
+#define __HAL_FLASH_GET_PROGRAM_DELAY()     READ_BIT(FLASH->ACR, FLASH_ACR_WRHIGHFREQ)
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASHEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup FLASHEx_Exported_Functions_Group1
+  * @{
+  */
+/* Extension Program operation functions  *************************************/
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError);
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
+void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
+
+HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank1(void);
+HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1(void);
+HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank2(void);
+HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank2(void);
+
+HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_t *CRC_Result);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros
+  * @{
+  */
+
+/** @defgroup FLASHEx_IS_FLASH_Definitions FLASHEx Private macros to check input parameters
+  * @{
+  */
+
+#define IS_FLASH_TYPEERASE(VALUE)        (((VALUE) == FLASH_TYPEERASE_SECTORS) || \
+                                          ((VALUE) == FLASH_TYPEERASE_MASSERASE))
+
+#if defined (FLASH_CR_PSIZE)
+#define IS_VOLTAGERANGE(RANGE)           (((RANGE) == FLASH_VOLTAGE_RANGE_1) || \
+                                          ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \
+                                          ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \
+                                          ((RANGE) == FLASH_VOLTAGE_RANGE_4))
+#endif /* FLASH_CR_PSIZE */
+
+#define IS_WRPSTATE(VALUE)               (((VALUE) == OB_WRPSTATE_DISABLE) || \
+                                          ((VALUE) == OB_WRPSTATE_ENABLE))
+
+#if defined (FLASH_OPTSR_VDDMMC_HSLV)
+#define IS_OPTIONBYTE(VALUE)             (((VALUE) <= 0x03FFU) && ((VALUE) != 0U))
+#elif defined (DUAL_CORE)
+#define IS_OPTIONBYTE(VALUE)             (((VALUE) <= 0x3FFFU) && ((VALUE) != 0U))
+#else
+#define IS_OPTIONBYTE(VALUE)             (((VALUE) <= 0x01FFU) && ((VALUE) != 0U))
+#endif /*DUAL_CORE*/
+
+#define IS_OB_BOOT_ADDRESS(ADDRESS)      ((ADDRESS) <= 0x8013U)
+
+#define IS_OB_RDP_LEVEL(LEVEL)           (((LEVEL) == OB_RDP_LEVEL_0)   ||\
+                                          ((LEVEL) == OB_RDP_LEVEL_1)   ||\
+                                          ((LEVEL) == OB_RDP_LEVEL_2))
+
+#define IS_OB_WWDG_SOURCE(SOURCE)        (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW))
+
+#define IS_OB_IWDG_SOURCE(SOURCE)        (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+
+#define IS_OB_STOP_SOURCE(SOURCE)        (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
+
+#define IS_OB_STDBY_SOURCE(SOURCE)       (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
+
+#define IS_OB_IWDG_STOP_FREEZE(FREEZE)   (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE))
+
+#define IS_OB_IWDG_STDBY_FREEZE(FREEZE)  (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE))
+
+#define IS_OB_BOR_LEVEL(LEVEL)           (((LEVEL) == OB_BOR_LEVEL0) || ((LEVEL) == OB_BOR_LEVEL1) || \
+                                          ((LEVEL) == OB_BOR_LEVEL2) || ((LEVEL) == OB_BOR_LEVEL3))
+
+#define IS_FLASH_LATENCY(LATENCY)        (((LATENCY) == FLASH_LATENCY_0)  || \
+                                          ((LATENCY) == FLASH_LATENCY_1)  || \
+                                          ((LATENCY) == FLASH_LATENCY_2)  || \
+                                          ((LATENCY) == FLASH_LATENCY_3)  || \
+                                          ((LATENCY) == FLASH_LATENCY_4)  || \
+                                          ((LATENCY) == FLASH_LATENCY_5)  || \
+                                          ((LATENCY) == FLASH_LATENCY_6)  || \
+                                          ((LATENCY) == FLASH_LATENCY_7)  || \
+                                          ((LATENCY) == FLASH_LATENCY_8)  || \
+                                          ((LATENCY) == FLASH_LATENCY_9)  || \
+                                          ((LATENCY) == FLASH_LATENCY_10) || \
+                                          ((LATENCY) == FLASH_LATENCY_11) || \
+                                          ((LATENCY) == FLASH_LATENCY_12) || \
+                                          ((LATENCY) == FLASH_LATENCY_13) || \
+                                          ((LATENCY) == FLASH_LATENCY_14) || \
+                                          ((LATENCY) == FLASH_LATENCY_15))
+
+#define IS_FLASH_SECTOR(SECTOR)          ((SECTOR) < FLASH_SECTOR_TOTAL)
+
+#if (FLASH_SECTOR_TOTAL == 8U)
+#define IS_OB_WRP_SECTOR(SECTOR)         ((((SECTOR) & 0xFFFFFF00U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
+#else
+#define IS_OB_WRP_SECTOR(SECTOR)         ((SECTOR) != 0x00000000U)
+#endif /* FLASH_SECTOR_TOTAL == 8U */
+
+#define IS_OB_PCROP_RDP(CONFIG)          (((CONFIG) == OB_PCROP_RDP_NOT_ERASE) || \
+                                          ((CONFIG) == OB_PCROP_RDP_ERASE))
+
+#define IS_OB_SECURE_RDP(CONFIG)         (((CONFIG) == OB_SECURE_RDP_NOT_ERASE) || \
+                                          ((CONFIG) == OB_SECURE_RDP_ERASE))
+
+#define IS_OB_USER_SWAP_BANK(VALUE)      (((VALUE) == OB_SWAP_BANK_DISABLE) || ((VALUE) == OB_SWAP_BANK_ENABLE))
+
+#define IS_OB_USER_IOHSLV(VALUE)         (((VALUE) == OB_IOHSLV_DISABLE) || ((VALUE) == OB_IOHSLV_ENABLE))
+
+#if defined (FLASH_OPTSR_VDDMMC_HSLV)
+#define IS_OB_USER_VDDMMC_HSLV(VALUE)    (((VALUE) == OB_VDDMMC_HSLV_DISABLE) || ((VALUE) == OB_VDDMMC_HSLV_ENABLE))
+#endif /* FLASH_OPTSR_VDDMMC_HSLV */
+
+#define IS_OB_IWDG1_SOURCE(SOURCE)       (((SOURCE) == OB_IWDG1_SW) || ((SOURCE) == OB_IWDG1_HW))
+#if defined (DUAL_CORE)
+#define IS_OB_IWDG2_SOURCE(SOURCE)       (((SOURCE) == OB_IWDG2_SW) || ((SOURCE) == OB_IWDG2_HW))
+#endif /* DUAL_CORE */
+#define IS_OB_STOP_D1_RESET(VALUE)       (((VALUE) == OB_STOP_NO_RST_D1) || ((VALUE) == OB_STOP_RST_D1))
+
+#define IS_OB_STDBY_D1_RESET(VALUE)      (((VALUE) == OB_STDBY_NO_RST_D1) || ((VALUE) == OB_STDBY_RST_D1))
+
+#define IS_OB_USER_IWDG_STOP(VALUE)      (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_ACTIVE))
+
+#define IS_OB_USER_IWDG_STDBY(VALUE)     (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_ACTIVE))
+
+#define IS_OB_USER_ST_RAM_SIZE(VALUE)    (((VALUE) == OB_ST_RAM_SIZE_2KB) || ((VALUE) == OB_ST_RAM_SIZE_4KB) || \
+                                          ((VALUE) == OB_ST_RAM_SIZE_8KB) || ((VALUE) == OB_ST_RAM_SIZE_16KB))
+
+#define IS_OB_USER_SECURITY(VALUE)       (((VALUE) == OB_SECURITY_ENABLE) || ((VALUE) == OB_SECURITY_DISABLE))
+
+#if defined (DUAL_CORE)
+#define IS_OB_USER_BCM4(VALUE)           (((VALUE) == OB_BCM4_DISABLE) || ((VALUE) == OB_BCM4_ENABLE))
+
+#define IS_OB_USER_BCM7(VALUE)           (((VALUE) == OB_BCM7_DISABLE) || ((VALUE) == OB_BCM7_ENABLE))
+
+#define IS_OB_STOP_D2_RESET(VALUE)       (((VALUE) == OB_STOP_NO_RST_D2) || ((VALUE) == OB_STOP_RST_D2))
+
+#define IS_OB_STDBY_D2_RESET(VALUE)      (((VALUE) == OB_STDBY_NO_RST_D2) || ((VALUE) == OB_STDBY_RST_D2))
+#endif /* DUAL_CORE */
+#if defined (DUAL_CORE)
+#define IS_OB_USER_TYPE(TYPE)            (((TYPE) <= (uint32_t)0x3FFFU) && ((TYPE) != 0U))
+#else
+#define IS_OB_USER_TYPE(TYPE)            (((TYPE) <= (uint32_t)0x73FU) && ((TYPE) != 0U))
+#endif /* DUAL_CORE */
+
+#define IS_OB_BOOT_ADD_OPTION(VALUE)     (((VALUE) == OB_BOOT_ADD0)  || \
+                                          ((VALUE) == OB_BOOT_ADD1)  || \
+                                          ((VALUE) == OB_BOOT_ADD_BOTH))
+
+#define IS_FLASH_TYPECRC(VALUE)          (((VALUE) == FLASH_CRC_ADDR)    || \
+                                          ((VALUE) == FLASH_CRC_SECTORS) || \
+                                          ((VALUE) == FLASH_CRC_BANK))
+
+#if defined (FLASH_OTPBL_LOCKBL)
+#define IS_OTP_BLOCK(VALUE)              ((((VALUE) & 0xFFFF0000U) == 0x00000000U) && ((VALUE) != 0x00000000U))
+#endif /* FLASH_OTPBL_LOCKBL */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
+  * @{
+  */
+void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_FLASH_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h
new file mode 100644
index 00000000..c1855665
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h
@@ -0,0 +1,346 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_gpio.h
+  * @author  MCD Application Team
+  * @brief   Header file of GPIO HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_GPIO_H
+#define STM32H7xx_HAL_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup GPIO
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Types GPIO Exported Types
+  * @{
+  */
+
+/**
+  * @brief   GPIO Init structure definition
+  */
+typedef struct
+{
+  uint32_t Pin;       /*!< Specifies the GPIO pins to be configured.
+                           This parameter can be any value of @ref GPIO_pins_define */
+
+  uint32_t Mode;      /*!< Specifies the operating mode for the selected pins.
+                           This parameter can be a value of @ref GPIO_mode_define */
+
+  uint32_t Pull;      /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
+                           This parameter can be a value of @ref GPIO_pull_define */
+
+  uint32_t Speed;     /*!< Specifies the speed for the selected pins.
+                           This parameter can be a value of @ref GPIO_speed_define */
+
+  uint32_t Alternate;  /*!< Peripheral to be connected to the selected pins.
+                            This parameter can be a value of @ref GPIO_Alternate_function_selection */
+} GPIO_InitTypeDef;
+
+/**
+  * @brief  GPIO Bit SET and Bit RESET enumeration
+  */
+typedef enum
+{
+  GPIO_PIN_RESET = 0U,
+  GPIO_PIN_SET
+} GPIO_PinState;
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Constants  GPIO Exported Constants
+  * @{
+  */
+
+/** @defgroup GPIO_pins_define  GPIO pins define
+  * @{
+  */
+#define GPIO_PIN_0                 ((uint16_t)0x0001)  /* Pin 0 selected    */
+#define GPIO_PIN_1                 ((uint16_t)0x0002)  /* Pin 1 selected    */
+#define GPIO_PIN_2                 ((uint16_t)0x0004)  /* Pin 2 selected    */
+#define GPIO_PIN_3                 ((uint16_t)0x0008)  /* Pin 3 selected    */
+#define GPIO_PIN_4                 ((uint16_t)0x0010)  /* Pin 4 selected    */
+#define GPIO_PIN_5                 ((uint16_t)0x0020)  /* Pin 5 selected    */
+#define GPIO_PIN_6                 ((uint16_t)0x0040)  /* Pin 6 selected    */
+#define GPIO_PIN_7                 ((uint16_t)0x0080)  /* Pin 7 selected    */
+#define GPIO_PIN_8                 ((uint16_t)0x0100)  /* Pin 8 selected    */
+#define GPIO_PIN_9                 ((uint16_t)0x0200)  /* Pin 9 selected    */
+#define GPIO_PIN_10                ((uint16_t)0x0400)  /* Pin 10 selected   */
+#define GPIO_PIN_11                ((uint16_t)0x0800)  /* Pin 11 selected   */
+#define GPIO_PIN_12                ((uint16_t)0x1000)  /* Pin 12 selected   */
+#define GPIO_PIN_13                ((uint16_t)0x2000)  /* Pin 13 selected   */
+#define GPIO_PIN_14                ((uint16_t)0x4000)  /* Pin 14 selected   */
+#define GPIO_PIN_15                ((uint16_t)0x8000)  /* Pin 15 selected   */
+#define GPIO_PIN_All               ((uint16_t)0xFFFF)  /* All pins selected */
+
+#define GPIO_PIN_MASK              (0x0000FFFFU) /* PIN mask for assert test */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_mode_define  GPIO mode define
+  * @brief GPIO Configuration Mode
+  *        Elements values convention: 0xX0yz00YZ
+  *           - X  : GPIO mode or EXTI Mode
+  *           - y  : External IT or Event trigger detection
+  *           - z  : IO configuration on External IT or Event
+  *           - Y  : Output type (Push Pull or Open Drain)
+  *           - Z  : IO Direction mode (Input, Output, Alternate or Analog)
+  * @{
+  */
+#define  GPIO_MODE_INPUT                        (0x00000000U)   /*!< Input Floating Mode                   */
+#define  GPIO_MODE_OUTPUT_PP                    (0x00000001U)   /*!< Output Push Pull Mode                 */
+#define  GPIO_MODE_OUTPUT_OD                    (0x00000011U)   /*!< Output Open Drain Mode                */
+#define  GPIO_MODE_AF_PP                        (0x00000002U)   /*!< Alternate Function Push Pull Mode     */
+#define  GPIO_MODE_AF_OD                        (0x00000012U)   /*!< Alternate Function Open Drain Mode    */
+
+#define  GPIO_MODE_ANALOG                       (0x00000003U)   /*!< Analog Mode  */
+
+#define  GPIO_MODE_IT_RISING                    (0x11110000U)   /*!< External Interrupt Mode with Rising edge trigger detection          */
+#define  GPIO_MODE_IT_FALLING                   (0x11210000U)   /*!< External Interrupt Mode with Falling edge trigger detection         */
+#define  GPIO_MODE_IT_RISING_FALLING            (0x11310000U)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */
+
+#define  GPIO_MODE_EVT_RISING                   (0x11120000U)   /*!< External Event Mode with Rising edge trigger detection               */
+#define  GPIO_MODE_EVT_FALLING                  (0x11220000U)   /*!< External Event Mode with Falling edge trigger detection              */
+#define  GPIO_MODE_EVT_RISING_FALLING           (0x11320000U)   /*!< External Event Mode with Rising/Falling edge trigger detection       */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_speed_define  GPIO speed define
+  * @brief GPIO Output Maximum frequency
+  * @{
+  */
+#define  GPIO_SPEED_FREQ_LOW         (0x00000000U)  /*!< Low speed     */
+#define  GPIO_SPEED_FREQ_MEDIUM      (0x00000001U)  /*!< Medium speed  */
+#define  GPIO_SPEED_FREQ_HIGH        (0x00000002U)  /*!< Fast speed    */
+#define  GPIO_SPEED_FREQ_VERY_HIGH   (0x00000003U)  /*!< High speed    */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_pull_define  GPIO pull define
+  * @brief GPIO Pull-Up or Pull-Down Activation
+  * @{
+  */
+#define  GPIO_NOPULL        (0x00000000U)   /*!< No Pull-up or Pull-down activation  */
+#define  GPIO_PULLUP        (0x00000001U)   /*!< Pull-up activation                  */
+#define  GPIO_PULLDOWN      (0x00000002U)   /*!< Pull-down activation                */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
+  * @{
+  */
+
+/**
+  * @brief  Checks whether the specified EXTI line flag is set or not.
+  * @param  __EXTI_LINE__: specifies the EXTI line flag to check.
+  *         This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval The new state of __EXTI_LINE__ (SET or RESET).
+  */
+#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
+
+/**
+  * @brief  Clears the EXTI's line pending flags.
+  * @param  __EXTI_LINE__: specifies the EXTI lines flags to clear.
+  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
+
+/**
+  * @brief  Checks whether the specified EXTI line is asserted or not.
+  * @param  __EXTI_LINE__: specifies the EXTI line to check.
+  *          This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval The new state of __EXTI_LINE__ (SET or RESET).
+  */
+#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
+
+/**
+  * @brief  Clears the EXTI's line pending bits.
+  * @param  __EXTI_LINE__: specifies the EXTI lines to clear.
+  *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Checks whether the specified EXTI line flag is set or not.
+  * @param  __EXTI_LINE__: specifies the EXTI line flag to check.
+  *         This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval The new state of __EXTI_LINE__ (SET or RESET).
+  */
+#define __HAL_GPIO_EXTID2_GET_FLAG(__EXTI_LINE__) (EXTI->C2PR1 & (__EXTI_LINE__))
+
+/**
+  * @brief  Clears the EXTI's line pending flags.
+  * @param  __EXTI_LINE__: specifies the EXTI lines flags to clear.
+  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTID2_CLEAR_FLAG(__EXTI_LINE__) (EXTI->C2PR1 = (__EXTI_LINE__))
+
+/**
+  * @brief  Checks whether the specified EXTI line is asserted or not.
+  * @param  __EXTI_LINE__: specifies the EXTI line to check.
+  *          This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval The new state of __EXTI_LINE__ (SET or RESET).
+  */
+#define __HAL_GPIO_EXTID2_GET_IT(__EXTI_LINE__) (EXTI->C2PR1 & (__EXTI_LINE__))
+
+/**
+  * @brief  Clears the EXTI's line pending bits.
+  * @param  __EXTI_LINE__: specifies the EXTI lines to clear.
+  *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTID2_CLEAR_IT(__EXTI_LINE__) (EXTI->C2PR1 = (__EXTI_LINE__))
+#endif
+
+/**
+  * @brief  Generates a Software interrupt on selected EXTI line.
+  * @param  __EXTI_LINE__: specifies the EXTI line to check.
+  *          This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__))
+/**
+  * @}
+  */
+
+/* Include GPIO HAL Extension module */
+#include "stm32h7xx_hal_gpio_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup GPIO_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup GPIO_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de-initialization functions *****************************/
+void  HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init);
+void  HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin);
+/**
+  * @}
+  */
+
+/** @addtogroup GPIO_Exported_Functions_Group2
+  * @{
+  */
+/* IO operation functions *****************************************************/
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
+void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup GPIO_Private_Constants GPIO Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup GPIO_Private_Macros GPIO Private Macros
+  * @{
+  */
+#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
+#define IS_GPIO_PIN(__PIN__)        ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
+                                     (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT)              ||\
+                            ((MODE) == GPIO_MODE_OUTPUT_PP)          ||\
+                            ((MODE) == GPIO_MODE_OUTPUT_OD)          ||\
+                            ((MODE) == GPIO_MODE_AF_PP)              ||\
+                            ((MODE) == GPIO_MODE_AF_OD)              ||\
+                            ((MODE) == GPIO_MODE_IT_RISING)          ||\
+                            ((MODE) == GPIO_MODE_IT_FALLING)         ||\
+                            ((MODE) == GPIO_MODE_IT_RISING_FALLING)  ||\
+                            ((MODE) == GPIO_MODE_EVT_RISING)         ||\
+                            ((MODE) == GPIO_MODE_EVT_FALLING)        ||\
+                            ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
+                            ((MODE) == GPIO_MODE_ANALOG))
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW)  || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \
+                              ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH))
+
+#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
+                            ((PULL) == GPIO_PULLDOWN))
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup GPIO_Private_Functions GPIO Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_GPIO_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h
new file mode 100644
index 00000000..ff2efb3c
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h
@@ -0,0 +1,428 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_gpio_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of GPIO HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_GPIO_EX_H
+#define STM32H7xx_HAL_GPIO_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup GPIOEx GPIOEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants
+  * @{
+  */
+
+/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection
+  * @{
+  */
+
+/**
+  * @brief   AF 0 selection
+  */
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                                                     */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping                                          */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping                                           */
+#define GPIO_AF0_LCDBIAS       ((uint8_t)0x00)  /* LCDBIAS Alternate Function mapping                                                      */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                                                        */
+#if defined (PWR_CPUCR_PDDS_D2) /* PWR D1 and D2 domains exists */
+#define GPIO_AF0_C1DSLEEP      ((uint8_t)0x00)  /* Cortex-M7 Deep Sleep Alternate Function mapping : available on STM32H7 Rev.B and above  */
+#define GPIO_AF0_C1SLEEP       ((uint8_t)0x00)  /* Cortex-M7 Sleep Alternate Function mapping : available on STM32H7 Rev.B and above       */
+#define GPIO_AF0_D1PWREN       ((uint8_t)0x00)  /* Domain 1 PWR enable Alternate Function mapping : available on STM32H7 Rev.B and above   */
+#define GPIO_AF0_D2PWREN       ((uint8_t)0x00)  /* Domain 2 PWR enable Alternate Function mapping : available on STM32H7 Rev.B and above   */
+#if defined(DUAL_CORE)
+#define GPIO_AF0_C2DSLEEP      ((uint8_t)0x00)  /* Cortex-M4 Deep Sleep Alternate Function mapping : available on STM32H7 Rev.B and above  */
+#define GPIO_AF0_C2SLEEP       ((uint8_t)0x00)  /* Cortex-M4 Sleep Alternate Function mapping : available on STM32H7 Rev.B and above       */
+#endif /* DUAL_CORE */
+#endif /* PWR_CPUCR_PDDS_D2 */
+
+/**
+  * @brief   AF 1 selection
+  */
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping   */
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping   */
+#define GPIO_AF1_TIM16         ((uint8_t)0x01)  /* TIM16 Alternate Function mapping  */
+#define GPIO_AF1_TIM17         ((uint8_t)0x01)  /* TIM17 Alternate Function mapping  */
+#define GPIO_AF1_LPTIM1        ((uint8_t)0x01)  /* LPTIM1 Alternate Function mapping */
+#if defined(HRTIM1)
+#define GPIO_AF1_HRTIM1        ((uint8_t)0x01)  /* HRTIM1 Alternate Function mapping */
+#endif /* HRTIM1 */
+
+/**
+  * @brief   AF 2 selection
+  */
+#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping   */
+#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping   */
+#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping   */
+#define GPIO_AF2_TIM12         ((uint8_t)0x02)  /* TIM12 Alternate Function mapping  */
+#define GPIO_AF2_SAI1          ((uint8_t)0x02)  /* SAI1 Alternate Function mapping   */
+#if defined(HRTIM1)
+#define GPIO_AF2_HRTIM1        ((uint8_t)0x02)  /* HRTIM1 Alternate Function mapping */
+#endif /* HRTIM1 */
+#define GPIO_AF2_TIM15         ((uint8_t)0x02)  /* TIM15 Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx */
+
+/**
+  * @brief   AF 3 selection
+  */
+#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping   */
+#define GPIO_AF3_LPTIM2        ((uint8_t)0x03)  /* LPTIM2 Alternate Function mapping */
+#define GPIO_AF3_DFSDM1        ((uint8_t)0x03)  /* DFSDM Alternate Function mapping  */
+#define GPIO_AF3_LPTIM3        ((uint8_t)0x03)  /* LPTIM3 Alternate Function mapping */
+#define GPIO_AF3_LPTIM4        ((uint8_t)0x03)  /* LPTIM4 Alternate Function mapping */
+#define GPIO_AF3_LPTIM5        ((uint8_t)0x03)  /* LPTIM5 Alternate Function mapping */
+#define GPIO_AF3_LPUART        ((uint8_t)0x03)  /* LPUART Alternate Function mapping */
+#if defined(OCTOSPIM)
+#define GPIO_AF3_OCTOSPIM_P1   ((uint8_t)0x03)  /* OCTOSPI Manager Port 1 Alternate Function mapping */
+#define GPIO_AF3_OCTOSPIM_P2   ((uint8_t)0x03)  /* OCTOSPI Manager Port 2 Alternate Function mapping */
+#endif /* OCTOSPIM */
+#if defined(HRTIM1)
+#define GPIO_AF3_HRTIM1        ((uint8_t)0x03)  /* HRTIM1 Alternate Function mapping */
+#endif /* HRTIM1 */
+
+/**
+  * @brief   AF 4 selection
+  */
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping   */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping   */
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping   */
+#define GPIO_AF4_I2C4          ((uint8_t)0x04)  /* I2C4 Alternate Function mapping   */
+#define GPIO_AF4_TIM15         ((uint8_t)0x04)  /* TIM15 Alternate Function mapping  */
+#define GPIO_AF4_CEC           ((uint8_t)0x04)  /* CEC Alternate Function mapping    */
+#define GPIO_AF4_LPTIM2        ((uint8_t)0x04)  /* LPTIM2 Alternate Function mapping */
+#define GPIO_AF4_USART1        ((uint8_t)0x04)  /* USART1 Alternate Function mapping */
+#define GPIO_AF4_DFSDM1        ((uint8_t)0x04)  /* DFSDM  Alternate Function mapping */
+#if defined(DFSDM2_BASE)
+#define GPIO_AF4_DFSDM2        ((uint8_t)0x04)  /* DFSDM2 Alternate Function mapping */
+#endif /* DFSDM2_BASE */
+#if defined(PSSI)
+#define GPIO_AF4_PSSI          ((uint8_t)0x04)  /* PSSI Alternate Function mapping   */
+#endif /* PSSI */
+
+/**
+  * @brief   AF 5 selection
+  */
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping   */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2 Alternate Function mapping   */
+#define GPIO_AF5_SPI3          ((uint8_t)0x05)  /* SPI3 Alternate Function mapping   */
+#define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4 Alternate Function mapping   */
+#define GPIO_AF5_SPI5          ((uint8_t)0x05)  /* SPI5 Alternate Function mapping   */
+#define GPIO_AF5_SPI6          ((uint8_t)0x05)  /* SPI6 Alternate Function mapping   */
+#define GPIO_AF5_CEC           ((uint8_t)0x05)  /* CEC  Alternate Function mapping   */
+
+/**
+  * @brief   AF 6 selection
+  */
+#define GPIO_AF6_SPI2          ((uint8_t)0x06)  /* SPI2 Alternate Function mapping   */
+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3 Alternate Function mapping   */
+#define GPIO_AF6_SAI1          ((uint8_t)0x06)  /* SAI1 Alternate Function mapping   */
+#define GPIO_AF6_I2C4          ((uint8_t)0x06)  /* I2C4 Alternate Function mapping   */
+#define GPIO_AF6_DFSDM1        ((uint8_t)0x06)  /* DFSDM Alternate Function mapping  */
+#define GPIO_AF6_UART4         ((uint8_t)0x06)  /* UART4 Alternate Function mapping  */
+#if defined(DFSDM2_BASE)
+#define GPIO_AF6_DFSDM2        ((uint8_t)0x06)  /* DFSDM2 Alternate Function mapping */
+#endif /* DFSDM2_BASE */
+#if defined(SAI3)
+#define GPIO_AF6_SAI3          ((uint8_t)0x06)  /* SAI3 Alternate Function mapping   */
+#endif /* SAI3 */
+#if defined(OCTOSPIM)
+#define GPIO_AF6_OCTOSPIM_P1   ((uint8_t)0x06)  /* OCTOSPI Manager Port 1 Alternate Function mapping */
+#endif /* OCTOSPIM */
+
+/**
+  * @brief   AF 7 selection
+  */
+#define GPIO_AF7_SPI2          ((uint8_t)0x07)  /* SPI2 Alternate Function mapping   */
+#define GPIO_AF7_SPI3          ((uint8_t)0x07)  /* SPI3 Alternate Function mapping   */
+#define GPIO_AF7_SPI6          ((uint8_t)0x07)  /* SPI6 Alternate Function mapping   */
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping */
+#define GPIO_AF7_USART6        ((uint8_t)0x07)  /* USART6 Alternate Function mapping */
+#define GPIO_AF7_UART7         ((uint8_t)0x07)  /* UART7 Alternate Function mapping  */
+#define GPIO_AF7_DFSDM1        ((uint8_t)0x07)  /* DFSDM Alternate Function mapping  */
+#define GPIO_AF7_SDMMC1        ((uint8_t)0x07)  /* SDMMC1 Alternate Function mapping */
+
+/**
+  * @brief   AF 8 selection
+  */
+#define GPIO_AF8_SPI6          ((uint8_t)0x08)  /* SPI6 Alternate Function mapping   */
+#define GPIO_AF8_SAI2          ((uint8_t)0x08)  /* SAI2 Alternate Function mapping   */
+#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */
+#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */
+#define GPIO_AF8_UART8         ((uint8_t)0x08)  /* UART8 Alternate Function mapping  */
+#define GPIO_AF8_SPDIF         ((uint8_t)0x08)  /* SPDIF Alternate Function mapping  */
+#define GPIO_AF8_LPUART        ((uint8_t)0x08)  /* LPUART Alternate Function mapping */
+#define GPIO_AF8_SDMMC1        ((uint8_t)0x08)  /* SDMMC1 Alternate Function mapping */
+#if defined(SAI4)
+#define GPIO_AF8_SAI4          ((uint8_t)0x08)  /* SAI4 Alternate Function mapping   */
+#endif /* SAI4 */
+
+/**
+  * @brief   AF 9 selection
+  */
+#define GPIO_AF9_FDCAN1        ((uint8_t)0x09)  /* FDCAN1 Alternate Function mapping   */
+#define GPIO_AF9_FDCAN2        ((uint8_t)0x09)  /* FDCAN2 Alternate Function mapping   */
+#define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping    */
+#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping    */
+#define GPIO_AF9_SDMMC2        ((uint8_t)0x09)  /* SDMMC2 Alternate Function mapping   */
+#define GPIO_AF9_LTDC          ((uint8_t)0x09)  /* LTDC Alternate Function mapping     */
+#define GPIO_AF9_SPDIF         ((uint8_t)0x09)  /* SPDIF Alternate Function mapping    */
+#define GPIO_AF9_FMC           ((uint8_t)0x09)  /* FMC Alternate Function mapping      */
+#if defined(QUADSPI)
+#define GPIO_AF9_QUADSPI       ((uint8_t)0x09)  /* QUADSPI Alternate Function mapping  */
+#endif /* QUADSPI */
+#if defined(SAI4)
+#define GPIO_AF9_SAI4          ((uint8_t)0x09)  /* SAI4 Alternate Function mapping     */
+#endif /* SAI4 */
+#if defined(OCTOSPIM)
+#define GPIO_AF9_OCTOSPIM_P1   ((uint8_t)0x09)  /* OCTOSPI Manager Port 1 Alternate Function mapping */
+#define GPIO_AF9_OCTOSPIM_P2   ((uint8_t)0x09)  /* OCTOSPI Manager Port 2 Alternate Function mapping */
+#endif /* OCTOSPIM */
+
+/**
+  * @brief   AF 10 selection
+  */
+#define GPIO_AF10_SAI2          ((uint8_t)0x0A)  /* SAI2 Alternate Function mapping                                             */
+#define GPIO_AF10_SDMMC2        ((uint8_t)0x0A)  /* SDMMC2 Alternate Function mapping                                           */
+#if defined(USB2_OTG_FS)
+#define GPIO_AF10_OTG2_FS       ((uint8_t)0x0A)  /* OTG2_FS Alternate Function mapping                                          */
+#endif /*USB2_OTG_FS*/
+#define GPIO_AF10_COMP1         ((uint8_t)0x0A)  /* COMP1 Alternate Function mapping                                            */
+#define GPIO_AF10_COMP2         ((uint8_t)0x0A)  /* COMP2 Alternate Function mapping                                            */
+#if defined(LTDC)
+#define GPIO_AF10_LTDC          ((uint8_t)0x0A)  /* LTDC Alternate Function mapping                                             */
+#endif /*LTDC*/
+#define GPIO_AF10_CRS_SYNC      ((uint8_t)0x0A)  /* CRS Sync Alternate Function mapping : available on STM32H7 Rev.B and above  */
+#if defined(QUADSPI)
+#define GPIO_AF10_QUADSPI       ((uint8_t)0x0A)  /* QUADSPI Alternate Function mapping                                          */
+#endif /* QUADSPI */
+#if defined(SAI4)
+#define GPIO_AF10_SAI4          ((uint8_t)0x0A)  /* SAI4 Alternate Function mapping                                             */
+#endif /* SAI4 */
+#if !defined(USB2_OTG_FS)
+#define GPIO_AF10_OTG1_FS       ((uint8_t)0x0A)  /* OTG1_FS Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx */
+#endif /* !USB2_OTG_FS */
+#define GPIO_AF10_OTG1_HS       ((uint8_t)0x0A)  /* OTG1_HS Alternate Function mapping                                          */
+#if defined(OCTOSPIM)
+#define GPIO_AF10_OCTOSPIM_P1   ((uint8_t)0x0A)  /* OCTOSPI Manager Port 1 Alternate Function mapping */
+#endif /* OCTOSPIM */
+#define GPIO_AF10_TIM8          ((uint8_t)0x0A)  /* TIM8 Alternate Function mapping                                             */
+
+/**
+  * @brief   AF 11 selection
+  */
+#define GPIO_AF11_SWP           ((uint8_t)0x0B)  /* SWP Alternate Function mapping     */
+#define GPIO_AF11_MDIOS         ((uint8_t)0x0B)  /* MDIOS Alternate Function mapping   */
+#define GPIO_AF11_UART7         ((uint8_t)0x0B)  /* UART7 Alternate Function mapping   */
+#define GPIO_AF11_SDMMC2        ((uint8_t)0x0B)  /* SDMMC2 Alternate Function mapping  */
+#define GPIO_AF11_DFSDM1        ((uint8_t)0x0B)  /* DFSDM1 Alternate Function mapping  */
+#define GPIO_AF11_COMP1         ((uint8_t)0x0B)  /* COMP1 Alternate Function mapping   */
+#define GPIO_AF11_COMP2         ((uint8_t)0x0B)  /* COMP2 Alternate Function mapping   */
+#define GPIO_AF11_TIM1          ((uint8_t)0x0B)  /* TIM1 Alternate Function mapping    */
+#define GPIO_AF11_TIM8          ((uint8_t)0x0B)  /* TIM8 Alternate Function mapping    */
+#define GPIO_AF11_I2C4          ((uint8_t)0x0B)  /* I2C4 Alternate Function mapping    */
+#if defined(DFSDM2_BASE)
+#define GPIO_AF11_DFSDM2        ((uint8_t)0x0B)  /* DFSDM2 Alternate Function mapping  */
+#endif /* DFSDM2_BASE */
+#if defined(USART10)
+#define GPIO_AF11_USART10       ((uint8_t)0x0B)  /* USART10 Alternate Function mapping */
+#endif /* USART10 */
+#if defined(UART9)
+#define GPIO_AF11_UART9         ((uint8_t)0x0B)  /* UART9 Alternate Function mapping   */
+#endif /* UART9 */
+#if defined(ETH)
+#define GPIO_AF11_ETH           ((uint8_t)0x0B)  /* ETH Alternate Function mapping     */
+#endif /* ETH */
+#if defined(LTDC)
+#define GPIO_AF11_LTDC          ((uint8_t)0x0B)  /* LTDC Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx  */
+#endif /*LTDC*/
+#if defined(OCTOSPIM)
+#define GPIO_AF11_OCTOSPIM_P1   ((uint8_t)0x0B)  /* OCTOSPI Manager Port 1 Alternate Function mapping */
+#endif /* OCTOSPIM */
+
+/**
+  * @brief   AF 12 selection
+  */
+#define GPIO_AF12_FMC           ((uint8_t)0x0C)  /* FMC Alternate Function mapping     */
+#define GPIO_AF12_SDMMC1        ((uint8_t)0x0C)  /* SDMMC1 Alternate Function mapping  */
+#define GPIO_AF12_MDIOS         ((uint8_t)0x0C)  /* MDIOS Alternate Function mapping   */
+#define GPIO_AF12_COMP1         ((uint8_t)0x0C)  /* COMP1 Alternate Function mapping   */
+#define GPIO_AF12_COMP2         ((uint8_t)0x0C)  /* COMP2 Alternate Function mapping   */
+#define GPIO_AF12_TIM1          ((uint8_t)0x0C)  /* TIM1 Alternate Function mapping    */
+#define GPIO_AF12_TIM8          ((uint8_t)0x0C)  /* TIM8 Alternate Function mapping    */
+#if defined(LTDC)
+#define GPIO_AF12_LTDC          ((uint8_t)0x0C)  /* LTDC Alternate Function mapping    */
+#endif /*LTDC*/
+#if defined(USB2_OTG_FS)
+#define GPIO_AF12_OTG1_FS       ((uint8_t)0x0C)  /* OTG1_FS Alternate Function mapping */
+#endif /* USB2_OTG_FS */
+
+/**
+  * @brief   AF 13 selection
+  */
+#define GPIO_AF13_DCMI          ((uint8_t)0x0D)   /* DCMI Alternate Function mapping  */
+#define GPIO_AF13_COMP1         ((uint8_t)0x0D)   /* COMP1 Alternate Function mapping */
+#define GPIO_AF13_COMP2         ((uint8_t)0x0D)   /* COMP2 Alternate Function mapping */
+#if defined(LTDC)
+#define GPIO_AF13_LTDC          ((uint8_t)0x0D)   /* LTDC Alternate Function mapping  */
+#endif /*LTDC*/
+#if defined(DSI)
+#define GPIO_AF13_DSI           ((uint8_t)0x0D)   /* DSI Alternate Function mapping   */
+#endif /* DSI */
+#if defined(PSSI)
+#define GPIO_AF13_PSSI          ((uint8_t)0x0D)   /* PSSI Alternate Function mapping  */
+#endif /* PSSI */
+#define GPIO_AF13_TIM1          ((uint8_t)0x0D)    /* TIM1 Alternate Function mapping */
+
+/**
+  * @brief   AF 14 selection
+  */
+#define GPIO_AF14_LTDC         ((uint8_t)0x0E)   /* LTDC Alternate Function mapping  */
+#define GPIO_AF14_UART5        ((uint8_t)0x0E)   /* UART5 Alternate Function mapping */
+
+/**
+  * @brief   AF 15 selection
+  */
+#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF)   ((AF) <= (uint8_t)0x0F)
+
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros
+  * @{
+  */
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions
+  * @{
+  */
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup GPIOEx_Private_Constants GPIO Private Constants
+  * @{
+  */
+
+/**
+  * @brief   GPIO pin available on the platform
+  */
+/* Defines the available pins per GPIOs */
+#define GPIOA_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOB_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOC_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOD_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOE_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOF_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOG_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOI_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOJ_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOH_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOK_PIN_AVAILABLE  (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | \
+                              GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7)
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup GPIOEx_Private_Macros GPIO Private Macros
+  * @{
+  */
+/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index
+  * @{
+  */
+#define GPIO_GET_INDEX(__GPIOx__)  (((__GPIOx__) == (GPIOA))? 0UL :\
+                                    ((__GPIOx__) == (GPIOB))? 1UL :\
+                                    ((__GPIOx__) == (GPIOC))? 2UL :\
+                                    ((__GPIOx__) == (GPIOD))? 3UL :\
+                                    ((__GPIOx__) == (GPIOE))? 4UL :\
+                                    ((__GPIOx__) == (GPIOF))? 5UL :\
+                                    ((__GPIOx__) == (GPIOG))? 6UL :\
+                                    ((__GPIOx__) == (GPIOH))? 7UL :\
+                                    ((__GPIOx__) == (GPIOI))? 8UL :\
+                                    ((__GPIOx__) == (GPIOJ))? 9UL : 10UL)
+/**
+  * @}
+  */
+
+/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function
+  * @{
+  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup GPIOEx_Private_Functions GPIO Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_GPIO_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h
new file mode 100644
index 00000000..1ef97f3d
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h
@@ -0,0 +1,214 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_hsem.h
+  * @author  MCD Application Team
+  * @brief   Header file of HSEM HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_HSEM_H
+#define STM32H7xx_HAL_HSEM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+   * @{
+   */
+
+/** @addtogroup HSEM
+   * @{
+   */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup HSEM_Exported_Macros HSEM Exported Macros
+  * @{
+  */
+
+/**
+  * @brief  SemID to mask helper Macro.
+  * @param  __SEMID__: semaphore ID from 0 to 31
+  * @retval Semaphore Mask.
+  */
+#define __HAL_HSEM_SEMID_TO_MASK(__SEMID__) (1 << (__SEMID__))
+
+/**
+  * @brief  Enables the specified HSEM interrupts.
+  * @param  __SEM_MASK__: semaphores Mask
+  * @retval None.
+  */
+#if defined(DUAL_CORE)
+#define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
+                                            (HSEM->C1IER |= (__SEM_MASK__)) : \
+                                            (HSEM->C2IER |= (__SEM_MASK__)))
+#else
+#define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) (HSEM->IER |= (__SEM_MASK__))
+#endif /* DUAL_CORE */
+/**
+  * @brief  Disables the specified HSEM interrupts.
+  * @param  __SEM_MASK__: semaphores Mask
+  * @retval None.
+  */
+#if defined(DUAL_CORE)
+#define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
+                                             (HSEM->C1IER &= ~(__SEM_MASK__)) :       \
+                                             (HSEM->C2IER &= ~(__SEM_MASK__)))
+#else
+#define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) (HSEM->IER &= ~(__SEM_MASK__))
+#endif /* DUAL_CORE */
+
+/**
+  * @brief  Checks whether interrupt has occurred or not for semaphores specified by a mask.
+  * @param  __SEM_MASK__: semaphores Mask
+  * @retval semaphores Mask : Semaphores where an interrupt occurred.
+  */
+#if defined(DUAL_CORE)
+#define __HAL_HSEM_GET_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
+                                         ((__SEM_MASK__) & HSEM->C1MISR) :        \
+                                         ((__SEM_MASK__) & HSEM->C2MISR1))
+#else
+#define __HAL_HSEM_GET_IT(__SEM_MASK__) ((__SEM_MASK__) & HSEM->MISR)
+#endif /* DUAL_CORE */
+
+/**
+  * @brief  Get the semaphores release status flags.
+  * @param  __SEM_MASK__: semaphores Mask
+  * @retval semaphores Mask : Semaphores where Release flags rise.
+  */
+#if defined(DUAL_CORE)
+#define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
+                                           (__SEM_MASK__) & HSEM->C1ISR :           \
+                                           (__SEM_MASK__) & HSEM->C2ISR)
+#else
+#define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((__SEM_MASK__) & HSEM->ISR)
+#endif /* DUAL_CORE */
+
+/**
+  * @brief  Clears the HSEM Interrupt flags.
+  * @param  __SEM_MASK__: semaphores Mask
+  * @retval None.
+  */
+#if defined(DUAL_CORE)
+#define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
+                                             (HSEM->C1ICR |= (__SEM_MASK__)) :        \
+                                             (HSEM->C2ICR |= (__SEM_MASK__)))
+#else
+#define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) (HSEM->ICR |= (__SEM_MASK__))
+#endif /* DUAL_CORE */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup HSEM_Exported_Functions HSEM Exported Functions
+  * @{
+  */
+
+/** @addtogroup HSEM_Exported_Functions_Group1 Take and Release functions
+  * @brief    HSEM Take and Release functions
+  * @{
+  */
+
+/* HSEM semaphore take (lock) using 2-Step  method ****************************/
+HAL_StatusTypeDef  HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID);
+/* HSEM semaphore fast take (lock) using 1-Step  method ***********************/
+HAL_StatusTypeDef  HAL_HSEM_FastTake(uint32_t SemID);
+/* HSEM Check semaphore state Taken or not   **********************************/
+uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID);
+/* HSEM Release  **************************************************************/
+void  HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID);
+/* HSEM Release All************************************************************/
+void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t CoreID);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HSEM_Exported_Functions_Group2 HSEM Set and Get Key functions
+  * @brief    HSEM Set and Get Key functions.
+  * @{
+  */
+/* HSEM Set Clear Key *********************************************************/
+void  HAL_HSEM_SetClearKey(uint32_t Key);
+/* HSEM Get Clear Key *********************************************************/
+uint32_t HAL_HSEM_GetClearKey(void);
+/**
+  * @}
+  */
+
+/** @addtogroup HSEM_Exported_Functions_Group3
+  * @brief   HSEM Notification functions
+  * @{
+  */
+/* HSEM Activate HSEM Notification (When a semaphore is released) ) *****************/
+void HAL_HSEM_ActivateNotification(uint32_t SemMask);
+/* HSEM Deactivate HSEM Notification (When a semaphore is released)  ****************/
+void HAL_HSEM_DeactivateNotification(uint32_t SemMask);
+/* HSEM Free Callback (When a semaphore is released)  *******************************/
+void HAL_HSEM_FreeCallback(uint32_t SemMask);
+/* HSEM IRQ Handler  **********************************************************/
+void HAL_HSEM_IRQHandler(void);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup HSEM_Private_Macros HSEM Private Macros
+  * @{
+  */
+
+#define IS_HSEM_SEMID(__SEMID__) ((__SEMID__) <= HSEM_SEMID_MAX )
+
+#define IS_HSEM_PROCESSID(__PROCESSID__) ((__PROCESSID__) <= HSEM_PROCESSID_MAX )
+
+#define IS_HSEM_KEY(__KEY__) ((__KEY__) <= HSEM_CLEAR_KEY_MAX )
+
+#if defined(DUAL_CORE)
+#define IS_HSEM_COREID(__COREID__) (((__COREID__) == HSEM_CPU1_COREID) || \
+                                    ((__COREID__) == HSEM_CPU2_COREID))
+#else
+#define IS_HSEM_COREID(__COREID__) ((__COREID__) == HSEM_CPU1_COREID)
+#endif
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_HSEM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h
new file mode 100644
index 00000000..ea2cd885
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h
@@ -0,0 +1,782 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_i2c.h
+  * @author  MCD Application Team
+  * @brief   Header file of I2C HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_I2C_H
+#define STM32H7xx_HAL_I2C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup I2C
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup I2C_Exported_Types I2C Exported Types
+  * @{
+  */
+
+/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
+  * @brief  I2C Configuration Structure definition
+  * @{
+  */
+typedef struct
+{
+  uint32_t Timing;              /*!< Specifies the I2C_TIMINGR_register value.
+                                  This parameter calculated by referring to I2C initialization
+                                         section in Reference manual */
+
+  uint32_t OwnAddress1;         /*!< Specifies the first device own address.
+                                  This parameter can be a 7-bit or 10-bit address. */
+
+  uint32_t AddressingMode;      /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
+                                  This parameter can be a value of @ref I2C_ADDRESSING_MODE */
+
+  uint32_t DualAddressMode;     /*!< Specifies if dual addressing mode is selected.
+                                  This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
+
+  uint32_t OwnAddress2;         /*!< Specifies the second device own address if dual addressing mode is selected
+                                  This parameter can be a 7-bit address. */
+
+  uint32_t OwnAddress2Masks;    /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
+                                  This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
+
+  uint32_t GeneralCallMode;     /*!< Specifies if general call mode is selected.
+                                  This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
+
+  uint32_t NoStretchMode;       /*!< Specifies if nostretch mode is selected.
+                                  This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
+
+} I2C_InitTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_state_structure_definition HAL state structure definition
+  * @brief  HAL State structure definition
+  * @note  HAL I2C State value coding follow below described bitmap :\n
+  *          b7-b6  Error information\n
+  *             00 : No Error\n
+  *             01 : Abort (Abort user request on going)\n
+  *             10 : Timeout\n
+  *             11 : Error\n
+  *          b5     Peripheral initialization status\n
+  *             0  : Reset (peripheral not initialized)\n
+  *             1  : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n
+  *          b4     (not used)\n
+  *             x  : Should be set to 0\n
+  *          b3\n
+  *             0  : Ready or Busy (No Listen mode ongoing)\n
+  *             1  : Listen (peripheral in Address Listen Mode)\n
+  *          b2     Intrinsic process state\n
+  *             0  : Ready\n
+  *             1  : Busy (peripheral busy with some configuration or internal operations)\n
+  *          b1     Rx state\n
+  *             0  : Ready (no Rx operation ongoing)\n
+  *             1  : Busy (Rx operation ongoing)\n
+  *          b0     Tx state\n
+  *             0  : Ready (no Tx operation ongoing)\n
+  *             1  : Busy (Tx operation ongoing)
+  * @{
+  */
+typedef enum
+{
+  HAL_I2C_STATE_RESET             = 0x00U,   /*!< Peripheral is not yet Initialized         */
+  HAL_I2C_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use  */
+  HAL_I2C_STATE_BUSY              = 0x24U,   /*!< An internal process is ongoing            */
+  HAL_I2C_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing      */
+  HAL_I2C_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing         */
+  HAL_I2C_STATE_LISTEN            = 0x28U,   /*!< Address Listen Mode is ongoing            */
+  HAL_I2C_STATE_BUSY_TX_LISTEN    = 0x29U,   /*!< Address Listen Mode and Data Transmission
+                                                 process is ongoing                         */
+  HAL_I2C_STATE_BUSY_RX_LISTEN    = 0x2AU,   /*!< Address Listen Mode and Data Reception
+                                                 process is ongoing                         */
+  HAL_I2C_STATE_ABORT             = 0x60U,   /*!< Abort user request ongoing                */
+  HAL_I2C_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state                             */
+  HAL_I2C_STATE_ERROR             = 0xE0U    /*!< Error                                     */
+
+} HAL_I2C_StateTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_mode_structure_definition HAL mode structure definition
+  * @brief  HAL Mode structure definition
+  * @note  HAL I2C Mode value coding follow below described bitmap :\n
+  *          b7     (not used)\n
+  *             x  : Should be set to 0\n
+  *          b6\n
+  *             0  : None\n
+  *             1  : Memory (HAL I2C communication is in Memory Mode)\n
+  *          b5\n
+  *             0  : None\n
+  *             1  : Slave (HAL I2C communication is in Slave Mode)\n
+  *          b4\n
+  *             0  : None\n
+  *             1  : Master (HAL I2C communication is in Master Mode)\n
+  *          b3-b2-b1-b0  (not used)\n
+  *             xxxx : Should be set to 0000
+  * @{
+  */
+typedef enum
+{
+  HAL_I2C_MODE_NONE               = 0x00U,   /*!< No I2C communication on going             */
+  HAL_I2C_MODE_MASTER             = 0x10U,   /*!< I2C communication is in Master Mode       */
+  HAL_I2C_MODE_SLAVE              = 0x20U,   /*!< I2C communication is in Slave Mode        */
+  HAL_I2C_MODE_MEM                = 0x40U    /*!< I2C communication is in Memory Mode       */
+
+} HAL_I2C_ModeTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Error_Code_definition I2C Error Code definition
+  * @brief  I2C Error Code definition
+  * @{
+  */
+#define HAL_I2C_ERROR_NONE      (0x00000000U)    /*!< No error              */
+#define HAL_I2C_ERROR_BERR      (0x00000001U)    /*!< BERR error            */
+#define HAL_I2C_ERROR_ARLO      (0x00000002U)    /*!< ARLO error            */
+#define HAL_I2C_ERROR_AF        (0x00000004U)    /*!< ACKF error            */
+#define HAL_I2C_ERROR_OVR       (0x00000008U)    /*!< OVR error             */
+#define HAL_I2C_ERROR_DMA       (0x00000010U)    /*!< DMA transfer error    */
+#define HAL_I2C_ERROR_TIMEOUT   (0x00000020U)    /*!< Timeout error         */
+#define HAL_I2C_ERROR_SIZE      (0x00000040U)    /*!< Size Management error */
+#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U)    /*!< DMA Parameter Error   */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+#define HAL_I2C_ERROR_INVALID_CALLBACK  (0x00000100U)    /*!< Invalid Callback error */
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+#define HAL_I2C_ERROR_INVALID_PARAM     (0x00000200U)    /*!< Invalid Parameters error  */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
+  * @brief  I2C handle Structure definition
+  * @{
+  */
+typedef struct __I2C_HandleTypeDef
+{
+  I2C_TypeDef                *Instance;      /*!< I2C registers base address                */
+
+  I2C_InitTypeDef            Init;           /*!< I2C communication parameters              */
+
+  uint8_t                    *pBuffPtr;      /*!< Pointer to I2C transfer buffer            */
+
+  uint16_t                   XferSize;       /*!< I2C transfer size                         */
+
+  __IO uint16_t              XferCount;      /*!< I2C transfer counter                      */
+
+  __IO uint32_t              XferOptions;    /*!< I2C sequantial transfer options, this parameter can
+                                                  be a value of @ref I2C_XFEROPTIONS */
+
+  __IO uint32_t              PreviousState;  /*!< I2C communication Previous state          */
+
+  HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);  /*!< I2C transfer IRQ handler function pointer */
+
+  DMA_HandleTypeDef          *hdmatx;        /*!< I2C Tx DMA handle parameters              */
+
+  DMA_HandleTypeDef          *hdmarx;        /*!< I2C Rx DMA handle parameters              */
+
+  HAL_LockTypeDef            Lock;           /*!< I2C locking object                        */
+
+  __IO HAL_I2C_StateTypeDef  State;          /*!< I2C communication state                   */
+
+  __IO HAL_I2C_ModeTypeDef   Mode;           /*!< I2C communication mode                    */
+
+  __IO uint32_t              ErrorCode;      /*!< I2C Error code                            */
+
+  __IO uint32_t              AddrEventCount; /*!< I2C Address Event counter                 */
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+  void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);           /*!< I2C Master Tx Transfer completed callback */
+  void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);           /*!< I2C Master Rx Transfer completed callback */
+  void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);            /*!< I2C Slave Tx Transfer completed callback  */
+  void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);            /*!< I2C Slave Rx Transfer completed callback  */
+  void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);             /*!< I2C Listen Complete callback              */
+  void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Memory Tx Transfer completed callback */
+  void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Memory Rx Transfer completed callback */
+  void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);                  /*!< I2C Error callback                        */
+  void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Abort callback                        */
+
+  void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);  /*!< I2C Slave Address Match callback */
+
+  void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);                /*!< I2C Msp Init callback                     */
+  void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Msp DeInit callback                   */
+
+#endif  /* USE_HAL_I2C_REGISTER_CALLBACKS */
+} I2C_HandleTypeDef;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL I2C Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_I2C_MASTER_TX_COMPLETE_CB_ID      = 0x00U,    /*!< I2C Master Tx Transfer completed callback ID  */
+  HAL_I2C_MASTER_RX_COMPLETE_CB_ID      = 0x01U,    /*!< I2C Master Rx Transfer completed callback ID  */
+  HAL_I2C_SLAVE_TX_COMPLETE_CB_ID       = 0x02U,    /*!< I2C Slave Tx Transfer completed callback ID   */
+  HAL_I2C_SLAVE_RX_COMPLETE_CB_ID       = 0x03U,    /*!< I2C Slave Rx Transfer completed callback ID   */
+  HAL_I2C_LISTEN_COMPLETE_CB_ID         = 0x04U,    /*!< I2C Listen Complete callback ID               */
+  HAL_I2C_MEM_TX_COMPLETE_CB_ID         = 0x05U,    /*!< I2C Memory Tx Transfer callback ID            */
+  HAL_I2C_MEM_RX_COMPLETE_CB_ID         = 0x06U,    /*!< I2C Memory Rx Transfer completed callback ID  */
+  HAL_I2C_ERROR_CB_ID                   = 0x07U,    /*!< I2C Error callback ID                         */
+  HAL_I2C_ABORT_CB_ID                   = 0x08U,    /*!< I2C Abort callback ID                         */
+
+  HAL_I2C_MSPINIT_CB_ID                 = 0x09U,    /*!< I2C Msp Init callback ID                      */
+  HAL_I2C_MSPDEINIT_CB_ID               = 0x0AU     /*!< I2C Msp DeInit callback ID                    */
+
+} HAL_I2C_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL I2C Callback pointer definition
+  */
+typedef  void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */
+typedef  void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */
+
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Constants I2C Exported Constants
+  * @{
+  */
+
+/** @defgroup I2C_XFEROPTIONS  I2C Sequential Transfer Options
+  * @{
+  */
+#define I2C_FIRST_FRAME                 ((uint32_t)I2C_SOFTEND_MODE)
+#define I2C_FIRST_AND_NEXT_FRAME        ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
+#define I2C_NEXT_FRAME                  ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
+#define I2C_FIRST_AND_LAST_FRAME        ((uint32_t)I2C_AUTOEND_MODE)
+#define I2C_LAST_FRAME                  ((uint32_t)I2C_AUTOEND_MODE)
+#define I2C_LAST_FRAME_NO_STOP          ((uint32_t)I2C_SOFTEND_MODE)
+
+/* List of XferOptions in usage of :
+ * 1- Restart condition in all use cases (direction change or not)
+ */
+#define  I2C_OTHER_FRAME                (0x000000AAU)
+#define  I2C_OTHER_AND_LAST_FRAME       (0x0000AA00U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
+  * @{
+  */
+#define I2C_ADDRESSINGMODE_7BIT         (0x00000001U)
+#define I2C_ADDRESSINGMODE_10BIT        (0x00000002U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
+  * @{
+  */
+#define I2C_DUALADDRESS_DISABLE         (0x00000000U)
+#define I2C_DUALADDRESS_ENABLE          I2C_OAR2_OA2EN
+/**
+  * @}
+  */
+
+/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
+  * @{
+  */
+#define I2C_OA2_NOMASK                  ((uint8_t)0x00U)
+#define I2C_OA2_MASK01                  ((uint8_t)0x01U)
+#define I2C_OA2_MASK02                  ((uint8_t)0x02U)
+#define I2C_OA2_MASK03                  ((uint8_t)0x03U)
+#define I2C_OA2_MASK04                  ((uint8_t)0x04U)
+#define I2C_OA2_MASK05                  ((uint8_t)0x05U)
+#define I2C_OA2_MASK06                  ((uint8_t)0x06U)
+#define I2C_OA2_MASK07                  ((uint8_t)0x07U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
+  * @{
+  */
+#define I2C_GENERALCALL_DISABLE         (0x00000000U)
+#define I2C_GENERALCALL_ENABLE          I2C_CR1_GCEN
+/**
+  * @}
+  */
+
+/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
+  * @{
+  */
+#define I2C_NOSTRETCH_DISABLE           (0x00000000U)
+#define I2C_NOSTRETCH_ENABLE            I2C_CR1_NOSTRETCH
+/**
+  * @}
+  */
+
+/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
+  * @{
+  */
+#define I2C_MEMADD_SIZE_8BIT            (0x00000001U)
+#define I2C_MEMADD_SIZE_16BIT           (0x00000002U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
+  * @{
+  */
+#define I2C_DIRECTION_TRANSMIT          (0x00000000U)
+#define I2C_DIRECTION_RECEIVE           (0x00000001U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
+  * @{
+  */
+#define  I2C_RELOAD_MODE                I2C_CR2_RELOAD
+#define  I2C_AUTOEND_MODE               I2C_CR2_AUTOEND
+#define  I2C_SOFTEND_MODE               (0x00000000U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
+  * @{
+  */
+#define  I2C_NO_STARTSTOP               (0x00000000U)
+#define  I2C_GENERATE_STOP              (uint32_t)(0x80000000U | I2C_CR2_STOP)
+#define  I2C_GENERATE_START_READ        (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
+#define  I2C_GENERATE_START_WRITE       (uint32_t)(0x80000000U | I2C_CR2_START)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
+  * @brief I2C Interrupt definition
+  *        Elements values convention: 0xXXXXXXXX
+  *           - XXXXXXXX  : Interrupt control mask
+  * @{
+  */
+#define I2C_IT_ERRI                     I2C_CR1_ERRIE
+#define I2C_IT_TCI                      I2C_CR1_TCIE
+#define I2C_IT_STOPI                    I2C_CR1_STOPIE
+#define I2C_IT_NACKI                    I2C_CR1_NACKIE
+#define I2C_IT_ADDRI                    I2C_CR1_ADDRIE
+#define I2C_IT_RXI                      I2C_CR1_RXIE
+#define I2C_IT_TXI                      I2C_CR1_TXIE
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Flag_definition I2C Flag definition
+  * @{
+  */
+#define I2C_FLAG_TXE                    I2C_ISR_TXE
+#define I2C_FLAG_TXIS                   I2C_ISR_TXIS
+#define I2C_FLAG_RXNE                   I2C_ISR_RXNE
+#define I2C_FLAG_ADDR                   I2C_ISR_ADDR
+#define I2C_FLAG_AF                     I2C_ISR_NACKF
+#define I2C_FLAG_STOPF                  I2C_ISR_STOPF
+#define I2C_FLAG_TC                     I2C_ISR_TC
+#define I2C_FLAG_TCR                    I2C_ISR_TCR
+#define I2C_FLAG_BERR                   I2C_ISR_BERR
+#define I2C_FLAG_ARLO                   I2C_ISR_ARLO
+#define I2C_FLAG_OVR                    I2C_ISR_OVR
+#define I2C_FLAG_PECERR                 I2C_ISR_PECERR
+#define I2C_FLAG_TIMEOUT                I2C_ISR_TIMEOUT
+#define I2C_FLAG_ALERT                  I2C_ISR_ALERT
+#define I2C_FLAG_BUSY                   I2C_ISR_BUSY
+#define I2C_FLAG_DIR                    I2C_ISR_DIR
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Macros I2C Exported Macros
+  * @{
+  */
+
+/** @brief Reset I2C handle state.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                do{                                                   \
+                                                                    (__HANDLE__)->State = HAL_I2C_STATE_RESET;       \
+                                                                    (__HANDLE__)->MspInitCallback = NULL;            \
+                                                                    (__HANDLE__)->MspDeInitCallback = NULL;          \
+                                                                  } while(0)
+#else
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
+#endif
+
+/** @brief  Enable the specified I2C interrupt.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __INTERRUPT__ specifies the interrupt source to enable.
+  *        This parameter can be one of the following values:
+  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
+  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
+  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
+  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
+  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
+  *            @arg @ref I2C_IT_RXI   RX interrupt enable
+  *            @arg @ref I2C_IT_TXI   TX interrupt enable
+  *
+  * @retval None
+  */
+#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)          ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
+
+/** @brief  Disable the specified I2C interrupt.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __INTERRUPT__ specifies the interrupt source to disable.
+  *        This parameter can be one of the following values:
+  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
+  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
+  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
+  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
+  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
+  *            @arg @ref I2C_IT_RXI   RX interrupt enable
+  *            @arg @ref I2C_IT_TXI   TX interrupt enable
+  *
+  * @retval None
+  */
+#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
+
+/** @brief  Check whether the specified I2C interrupt source is enabled or not.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __INTERRUPT__ specifies the I2C interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
+  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
+  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
+  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
+  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
+  *            @arg @ref I2C_IT_RXI   RX interrupt enable
+  *            @arg @ref I2C_IT_TXI   TX interrupt enable
+  *
+  * @retval The new state of __INTERRUPT__ (SET or RESET).
+  */
+#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)      ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief  Check whether the specified I2C flag is set or not.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg @ref I2C_FLAG_TXE     Transmit data register empty
+  *            @arg @ref I2C_FLAG_TXIS    Transmit interrupt status
+  *            @arg @ref I2C_FLAG_RXNE    Receive data register not empty
+  *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)
+  *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag
+  *            @arg @ref I2C_FLAG_STOPF   STOP detection flag
+  *            @arg @ref I2C_FLAG_TC      Transfer complete (master mode)
+  *            @arg @ref I2C_FLAG_TCR     Transfer complete reload
+  *            @arg @ref I2C_FLAG_BERR    Bus error
+  *            @arg @ref I2C_FLAG_ARLO    Arbitration lost
+  *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun
+  *            @arg @ref I2C_FLAG_PECERR  PEC error in reception
+  *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
+  *            @arg @ref I2C_FLAG_ALERT   SMBus alert
+  *            @arg @ref I2C_FLAG_BUSY    Bus busy
+  *            @arg @ref I2C_FLAG_DIR     Transfer direction (slave mode)
+  *
+  * @retval The new state of __FLAG__ (SET or RESET).
+  */
+#define I2C_FLAG_MASK  (0x0001FFFFU)
+#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+
+/** @brief  Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __FLAG__ specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg @ref I2C_FLAG_TXE     Transmit data register empty
+  *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)
+  *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag
+  *            @arg @ref I2C_FLAG_STOPF   STOP detection flag
+  *            @arg @ref I2C_FLAG_BERR    Bus error
+  *            @arg @ref I2C_FLAG_ARLO    Arbitration lost
+  *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun
+  *            @arg @ref I2C_FLAG_PECERR  PEC error in reception
+  *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
+  *            @arg @ref I2C_FLAG_ALERT   SMBus alert
+  *
+  * @retval None
+  */
+#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
+                                                                                 : ((__HANDLE__)->Instance->ICR = (__FLAG__)))
+
+/** @brief  Enable the specified I2C peripheral.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#define __HAL_I2C_ENABLE(__HANDLE__)                            (SET_BIT((__HANDLE__)->Instance->CR1,  I2C_CR1_PE))
+
+/** @brief  Disable the specified I2C peripheral.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#define __HAL_I2C_DISABLE(__HANDLE__)                           (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
+
+/** @brief  Generate a Non-Acknowledge I2C peripheral in Slave mode.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#define __HAL_I2C_GENERATE_NACK(__HANDLE__)                     (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
+/**
+  * @}
+  */
+
+/* Include I2C HAL Extended module */
+#include "stm32h7xx_hal_i2c_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2C_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+/* Initialization and de-initialization functions******************************/
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
+  * @{
+  */
+/* IO operation functions  ****************************************************/
+/******* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
+
+/******* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
+
+/******* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
+void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
+  * @{
+  */
+/* Peripheral State, Mode and Error functions  *********************************/
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
+HAL_I2C_ModeTypeDef  HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
+uint32_t             HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Constants I2C Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2C_Private_Macro I2C Private Macros
+  * @{
+  */
+
+#define IS_I2C_ADDRESSING_MODE(MODE)    (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
+                                         ((MODE) == I2C_ADDRESSINGMODE_10BIT))
+
+#define IS_I2C_DUAL_ADDRESS(ADDRESS)    (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
+                                         ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
+
+#define IS_I2C_OWN_ADDRESS2_MASK(MASK)  (((MASK) == I2C_OA2_NOMASK)  || \
+                                         ((MASK) == I2C_OA2_MASK01) || \
+                                         ((MASK) == I2C_OA2_MASK02) || \
+                                         ((MASK) == I2C_OA2_MASK03) || \
+                                         ((MASK) == I2C_OA2_MASK04) || \
+                                         ((MASK) == I2C_OA2_MASK05) || \
+                                         ((MASK) == I2C_OA2_MASK06) || \
+                                         ((MASK) == I2C_OA2_MASK07))
+
+#define IS_I2C_GENERAL_CALL(CALL)       (((CALL) == I2C_GENERALCALL_DISABLE) || \
+                                         ((CALL) == I2C_GENERALCALL_ENABLE))
+
+#define IS_I2C_NO_STRETCH(STRETCH)      (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
+                                         ((STRETCH) == I2C_NOSTRETCH_ENABLE))
+
+#define IS_I2C_MEMADD_SIZE(SIZE)        (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
+                                         ((SIZE) == I2C_MEMADD_SIZE_16BIT))
+
+#define IS_TRANSFER_MODE(MODE)          (((MODE) == I2C_RELOAD_MODE)   || \
+                                         ((MODE) == I2C_AUTOEND_MODE) || \
+                                         ((MODE) == I2C_SOFTEND_MODE))
+
+#define IS_TRANSFER_REQUEST(REQUEST)    (((REQUEST) == I2C_GENERATE_STOP)        || \
+                                         ((REQUEST) == I2C_GENERATE_START_READ)  || \
+                                         ((REQUEST) == I2C_GENERATE_START_WRITE) || \
+                                         ((REQUEST) == I2C_NO_STARTSTOP))
+
+#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)  (((REQUEST) == I2C_FIRST_FRAME)          || \
+                                                   ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
+                                                   ((REQUEST) == I2C_NEXT_FRAME)           || \
+                                                   ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
+                                                   ((REQUEST) == I2C_LAST_FRAME)           || \
+                                                   ((REQUEST) == I2C_LAST_FRAME_NO_STOP)   || \
+                                                   IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
+
+#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME)     || \
+                                                        ((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
+
+#define I2C_RESET_CR2(__HANDLE__)                 ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
+
+#define I2C_GET_ADDR_MATCH(__HANDLE__)            ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U))
+#define I2C_GET_DIR(__HANDLE__)                   ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U))
+#define I2C_GET_STOP_MODE(__HANDLE__)             ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
+#define I2C_GET_OWN_ADDRESS1(__HANDLE__)          ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
+#define I2C_GET_OWN_ADDRESS2(__HANDLE__)          ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
+
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1)             ((ADDRESS1) <= 0x000003FFU)
+#define IS_I2C_OWN_ADDRESS2(ADDRESS2)             ((ADDRESS2) <= (uint16_t)0x00FFU)
+
+#define I2C_MEM_ADD_MSB(__ADDRESS__)              ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
+#define I2C_MEM_ADD_LSB(__ADDRESS__)              ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
+
+#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
+                                                          (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
+
+#define I2C_CHECK_FLAG(__ISR__, __FLAG__)         ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
+#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__)      ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
+/**
+  * @}
+  */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Functions I2C Private Functions
+  * @{
+  */
+/* Private functions are defined in stm32h7xx_hal_i2c.c file */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32H7xx_HAL_I2C_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h
new file mode 100644
index 00000000..bf89420b
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h
@@ -0,0 +1,181 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_i2c_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of I2C HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_I2C_EX_H
+#define STM32H7xx_HAL_I2C_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup I2CEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
+  * @{
+  */
+
+/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
+  * @{
+  */
+#define I2C_ANALOGFILTER_ENABLE         0x00000000U
+#define I2C_ANALOGFILTER_DISABLE        I2C_CR1_ANFOFF
+/**
+  * @}
+  */
+
+/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
+  * @{
+  */
+#define I2C_FASTMODEPLUS_PB6            SYSCFG_PMCR_I2C_PB6_FMP                        /*!< Enable Fast Mode Plus on PB6       */
+#define I2C_FASTMODEPLUS_PB7            SYSCFG_PMCR_I2C_PB7_FMP                        /*!< Enable Fast Mode Plus on PB7       */
+#define I2C_FASTMODEPLUS_PB8            SYSCFG_PMCR_I2C_PB8_FMP                        /*!< Enable Fast Mode Plus on PB8       */
+#define I2C_FASTMODEPLUS_PB9            SYSCFG_PMCR_I2C_PB9_FMP                        /*!< Enable Fast Mode Plus on PB9       */
+#define I2C_FASTMODEPLUS_I2C1           SYSCFG_PMCR_I2C1_FMP                           /*!< Enable Fast Mode Plus on I2C1 pins */
+#define I2C_FASTMODEPLUS_I2C2           SYSCFG_PMCR_I2C2_FMP                           /*!< Enable Fast Mode Plus on I2C2 pins */
+#define I2C_FASTMODEPLUS_I2C3           SYSCFG_PMCR_I2C3_FMP                           /*!< Enable Fast Mode Plus on I2C3 pins */
+#define I2C_FASTMODEPLUS_I2C4           SYSCFG_PMCR_I2C4_FMP                           /*!< Enable Fast Mode Plus on I2C4 pins */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
+  * @{
+  */
+
+/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions
+  * @brief    Extended features functions
+  * @{
+  */
+
+/* Peripheral Control functions  ************************************************/
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
+HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
+void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
+void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
+  * @{
+  */
+#define IS_I2C_ANALOG_FILTER(FILTER)    (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
+                                          ((FILTER) == I2C_ANALOGFILTER_DISABLE))
+
+#define IS_I2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000FU)
+
+#if (defined(SYSCFG_PMCR_I2C1_FMP) && defined(SYSCFG_PMCR_I2C2_FMP) && defined(SYSCFG_PMCR_I2C3_FMP) && defined(SYSCFG_PMCR_I2C4_FMP))
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3) || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C4) == I2C_FASTMODEPLUS_I2C4))
+#elif defined(SYSCFG_PMCR_I2C1_FMP) && defined(SYSCFG_PMCR_I2C2_FMP) && defined(SYSCFG_PMCR_I2C3_FMP)
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3))
+#elif defined(SYSCFG_PMCR_I2C1_FMP) && defined(SYSCFG_PMCR_I2C2_FMP)
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2))
+#elif defined(SYSCFG_PMCR_I2C1_FMP)
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1))
+#endif /* SYSCFG_PMCR_I2C1_FMP && SYSCFG_PMCR_I2C2_FMP && SYSCFG_PMCR_I2C3_FMP && SYSCFG_PMCR_I2C4_FMP */
+
+
+
+/**
+  * @}
+  */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
+  * @{
+  */
+/* Private functions are defined in stm32h7xx_hal_i2c_ex.c file */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_I2C_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h
new file mode 100644
index 00000000..6c1d9b71
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h
@@ -0,0 +1,855 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_mdma.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMA HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_MDMA_H
+#define STM32H7xx_HAL_MDMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup MDMA
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup MDMA_Exported_Types MDMA Exported Types
+  * @brief    MDMA Exported Types
+  * @{
+  */
+
+/**
+  * @brief  MDMA Configuration Structure definition
+  */
+typedef struct
+{
+
+  uint32_t Request;                 /*!< Specifies the MDMA request.
+                                        This parameter can be a value of @ref MDMA_Request_selection*/
+
+  uint32_t TransferTriggerMode;     /*!< Specifies the Trigger Transfer mode : each request triggers a :
+                                         a buffer transfer, a block transfer, a repeated block transfer or a linked list transfer
+                                         This parameter can be a value of @ref MDMA_Transfer_TriggerMode  */
+
+  uint32_t Priority;                 /*!< Specifies the software priority for the MDMAy channelx.
+                                         This parameter can be a value of @ref MDMA_Priority_level */
+
+  uint32_t Endianness;                /*!< Specifies if the MDMA transactions preserve the Little endianness.
+                                         This parameter can be a value of @ref MDMA_Endianness */
+
+  uint32_t SourceInc;                /*!< Specifies if the Source increment mode .
+                                         This parameter can be a value of @ref MDMA_Source_increment_mode */
+
+  uint32_t DestinationInc;           /*!< Specifies if the Destination increment mode .
+                                         This parameter can be a value of @ref MDMA_Destination_increment_mode */
+
+  uint32_t SourceDataSize;           /*!< Specifies the source data size.
+                                         This parameter can be a value of @ref MDMA_Source_data_size */
+
+  uint32_t DestDataSize;             /*!< Specifies the destination data size.
+                                          This parameter can be a value of @ref MDMA_Destination_data_size */
+
+
+  uint32_t DataAlignment;            /*!< Specifies the source to destination Memory data packing/padding mode.
+                                            This parameter can be a value of @ref MDMA_data_Alignment */
+
+  uint32_t BufferTransferLength;      /*!< Specifies the buffer Transfer Length (number of bytes),
+                                          this is the number of bytes to be transferred in a single transfer (1 byte to 128 bytes)*/
+
+  uint32_t SourceBurst;              /*!< Specifies the Burst transfer configuration for the source memory transfers.
+                                         It specifies the amount of data to be transferred in a single non interruptable
+                                         transaction.
+                                         This parameter can be a value of @ref MDMA_Source_burst
+                                         @note : the burst may be FIXED/INCR based on SourceInc value ,
+                                         the BURST must be programmed as to ensure that the burst size will be lower than than
+                                         BufferTransferLength */
+
+  uint32_t DestBurst;                 /*!< Specifies the Burst transfer configuration for the destination memory transfers.
+                                           It specifies the amount of data to be transferred in a single non interruptable
+                                           transaction.
+                                           This parameter can be a value of @ref MDMA_Destination_burst
+                                           @note : the burst may be FIXED/INCR based on DestinationInc value ,
+                                           the BURST must be programmed as to ensure that the burst size will be lower than than
+                                           BufferTransferLength */
+
+  int32_t SourceBlockAddressOffset;   /*!< this field specifies the Next block source address offset
+                                           signed value : if > 0 then  increment the next block source Address by offset from where the last block ends
+                                                          if < 0 then  decrement the next block source Address by offset from where the last block ends
+                                                          if == 0, the next block source address starts from where the last block ends
+                                       */
+
+
+  int32_t DestBlockAddressOffset;      /*!< this field specifies the Next block destination address offset
+                                           signed value : if > 0 then  increment the next block destination Address by offset from where the last block ends
+                                                          if < 0 then  decrement the next block destination Address by offset from where the last block ends
+                                                          if == 0, the next block destination address starts from where the last block ends
+                                       */
+
+}MDMA_InitTypeDef;
+
+/**
+  * @brief  HAL MDMA linked list node structure definition
+  * @note   The Linked list node allows to define a new MDMA configuration
+  *         (CTCR ,CBNDTR ,CSAR ,CDAR ,CBRUR, CLAR, CTBR, CMAR and CMDR registers).
+  *         When CLAR register is configured to a non NULL value , each time a transfer ends,
+  *         a new configuration (linked list node) is automatically loaded from the address given in CLAR register.
+  */
+typedef struct
+{
+  __IO uint32_t CTCR;     /*!< New CTCR register configuration for the given MDMA linked list node   */
+  __IO uint32_t CBNDTR;   /*!< New CBNDTR register configuration for the given MDMA linked list node */
+  __IO uint32_t CSAR;     /*!< New CSAR register configuration for the given MDMA linked list node   */
+  __IO uint32_t CDAR;     /*!< New CDAR register configuration for the given MDMA linked list node   */
+  __IO uint32_t CBRUR;    /*!< New CBRUR register configuration for the given MDMA linked list node  */
+  __IO uint32_t CLAR;     /*!< New CLAR register configuration for the given MDMA linked list node   */
+  __IO uint32_t CTBR;     /*!< New CTBR register configuration for the given MDMA linked list node   */
+  __IO uint32_t Reserved; /*!< Reserved register                                                     */
+  __IO uint32_t CMAR;     /*!< New CMAR register configuration for the given MDMA linked list node   */
+  __IO uint32_t CMDR;     /*!< New CMDR register configuration for the given MDMA linked list node   */
+
+}MDMA_LinkNodeTypeDef;
+
+/**
+  * @brief  HAL MDMA linked list node configuration structure definition
+  * @note   used with HAL_MDMA_LinkedList_CreateNode function
+  */
+typedef struct
+{
+  MDMA_InitTypeDef Init;            /*!< configuration of the specified MDMA Linked List Node    */
+  uint32_t         SrcAddress;      /*!< The source memory address for the Linked list Node      */
+  uint32_t         DstAddress;      /*!< The destination memory address for the Linked list Node */
+  uint32_t         BlockDataLength; /*!< The data length of a block in bytes                     */
+  uint32_t         BlockCount;      /*!< The number of blocks to be transferred                  */
+
+  uint32_t PostRequestMaskAddress;  /*!< specifies the address to be updated (written) with PostRequestMaskData after a request is served.
+                                         PostRequestMaskAddress and PostRequestMaskData could be used to automatically clear a peripheral flag when the request is served  */
+
+  uint32_t PostRequestMaskData;     /*!< specifies the value to be written to PostRequestMaskAddress after a request is served.
+                                         PostRequestMaskAddress and PostRequestMaskData could be used to automatically clear a peripheral flag when the request is served  */
+
+
+}MDMA_LinkNodeConfTypeDef;
+
+
+/**
+  * @brief  HAL MDMA State structure definition
+  */
+typedef enum
+{
+  HAL_MDMA_STATE_RESET               = 0x00U,  /*!< MDMA not yet initialized or disabled */
+  HAL_MDMA_STATE_READY               = 0x01U,  /*!< MDMA initialized and ready for use   */
+  HAL_MDMA_STATE_BUSY                = 0x02U,  /*!< MDMA process is ongoing              */
+  HAL_MDMA_STATE_ERROR               = 0x03U,  /*!< MDMA error state                     */
+  HAL_MDMA_STATE_ABORT               = 0x04U,  /*!< MDMA Abort state                     */
+
+}HAL_MDMA_StateTypeDef;
+
+/**
+  * @brief  HAL MDMA Level Complete structure definition
+  */
+typedef enum
+{
+  HAL_MDMA_FULL_TRANSFER         = 0x00U,   /*!< Full transfer         */
+  HAL_MDMA_BUFFER_TRANSFER       = 0x01U,   /*!< Buffer Transfer       */
+  HAL_MDMA_BLOCK_TRANSFER        = 0x02U,   /*!< Block Transfer        */
+  HAL_MDMA_REPEAT_BLOCK_TRANSFER = 0x03U    /*!< repeat block Transfer */
+
+}HAL_MDMA_LevelCompleteTypeDef;
+
+/**
+  * @brief  HAL MDMA Callbacks IDs structure definition
+  */
+typedef enum
+{
+  HAL_MDMA_XFER_CPLT_CB_ID          = 0x00U,    /*!< Full transfer           */
+  HAL_MDMA_XFER_BUFFERCPLT_CB_ID    = 0x01U,    /*!< Buffer Transfer         */
+  HAL_MDMA_XFER_BLOCKCPLT_CB_ID     = 0x02U,    /*!< Block Transfer          */
+  HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID  = 0x03U,    /*!< Repeated Block Transfer */
+  HAL_MDMA_XFER_ERROR_CB_ID         = 0x04U,    /*!< Error                   */
+  HAL_MDMA_XFER_ABORT_CB_ID         = 0x05U,    /*!< Abort                   */
+  HAL_MDMA_XFER_ALL_CB_ID           = 0x06U     /*!< All                     */
+
+}HAL_MDMA_CallbackIDTypeDef;
+
+
+/**
+  * @brief  MDMA handle Structure definition
+  */
+typedef struct __MDMA_HandleTypeDef
+{
+  MDMA_Channel_TypeDef *Instance;                                                              /*!< Register base address                  */
+
+  MDMA_InitTypeDef      Init;                                                                  /*!< MDMA communication parameters          */
+
+  HAL_LockTypeDef       Lock;                                                                  /*!< MDMA locking object                    */
+
+  __IO HAL_MDMA_StateTypeDef  State;                                                           /*!< MDMA transfer state                    */
+
+  void                  *Parent;                                                               /*!< Parent object state                    */
+
+  void                  (* XferCpltCallback)( struct __MDMA_HandleTypeDef * hmdma);            /*!< MDMA transfer complete callback        */
+
+  void                  (* XferBufferCpltCallback)( struct __MDMA_HandleTypeDef * hmdma);      /*!< MDMA buffer transfer complete callback */
+
+  void                  (* XferBlockCpltCallback)( struct __MDMA_HandleTypeDef * hmdma);       /*!< MDMA block transfer complete callback  */
+
+  void                  (* XferRepeatBlockCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA block transfer repeat callback    */
+
+  void                  (* XferErrorCallback)( struct __MDMA_HandleTypeDef * hmdma);           /*!< MDMA transfer error callback           */
+
+  void                  (* XferAbortCallback)( struct __MDMA_HandleTypeDef * hmdma);           /*!< MDMA transfer Abort callback           */
+
+
+  MDMA_LinkNodeTypeDef *FirstLinkedListNodeAddress;                                             /*!< specifies the first node address of the transfer list
+                                                                                                     (after the initial node defined by the Init struct)
+                                                                                                     this parameter is used internally by the MDMA driver
+                                                                                                     to construct the linked list node
+                                                                                                */
+
+  MDMA_LinkNodeTypeDef *LastLinkedListNodeAddress;                                             /*!< specifies the last node address of the transfer list
+                                                                                                    this parameter is used internally by the MDMA driver
+                                                                                                    to construct the linked list node
+                                                                                                */
+  uint32_t LinkedListNodeCounter;                                                               /*!< Number of nodes in the MDMA linked list */
+
+  __IO uint32_t          ErrorCode;                                                            /*!< MDMA Error code                        */
+
+} MDMA_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup MDMA_Exported_Constants MDMA Exported Constants
+  * @brief    MDMA Exported constants
+  * @{
+  */
+
+/** @defgroup MDMA_Error_Codes MDMA Error Codes
+  * @brief    MDMA Error Codes
+  * @{
+  */
+#define HAL_MDMA_ERROR_NONE        ((uint32_t)0x00000000U)   /*!< No error                               */
+#define HAL_MDMA_ERROR_READ_XFER   ((uint32_t)0x00000001U)   /*!< Read Transfer error                    */
+#define HAL_MDMA_ERROR_WRITE_XFER  ((uint32_t)0x00000002U)   /*!< Write Transfer error                   */
+#define HAL_MDMA_ERROR_MASK_DATA   ((uint32_t)0x00000004U)   /*!< Error Mask Data error                  */
+#define HAL_MDMA_ERROR_LINKED_LIST ((uint32_t)0x00000008U)   /*!< Linked list Data error                 */
+#define HAL_MDMA_ERROR_ALIGNMENT   ((uint32_t)0x00000010U)   /*!< Address/Size alignment  error          */
+#define HAL_MDMA_ERROR_BLOCK_SIZE  ((uint32_t)0x00000020U)   /*!< Block Size error                       */
+#define HAL_MDMA_ERROR_TIMEOUT     ((uint32_t)0x00000040U)   /*!< Timeout error                          */
+#define HAL_MDMA_ERROR_NO_XFER     ((uint32_t)0x00000080U)   /*!< Abort or SW trigger requested with no Xfer ongoing   */
+#define HAL_MDMA_ERROR_BUSY        ((uint32_t)0x00000100U)   /*!< DeInit or SW trigger requested with Xfer ongoing   */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_Request_selection MDMA Request selection
+  * @brief    MDMA_Request_selection
+  * @{
+  */
+
+#define MDMA_REQUEST_DMA1_Stream0_TC      ((uint32_t)0x00000000U)  /*!< MDMA HW request is DMA1 Stream 0 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA1_Stream1_TC      ((uint32_t)0x00000001U)  /*!< MDMA HW request is DMA1 Stream 1 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA1_Stream2_TC      ((uint32_t)0x00000002U)  /*!< MDMA HW request is DMA1 Stream 2 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA1_Stream3_TC      ((uint32_t)0x00000003U)  /*!< MDMA HW request is DMA1 Stream 3 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA1_Stream4_TC      ((uint32_t)0x00000004U)  /*!< MDMA HW request is DMA1 Stream 4 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA1_Stream5_TC      ((uint32_t)0x00000005U)  /*!< MDMA HW request is DMA1 Stream 5 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA1_Stream6_TC      ((uint32_t)0x00000006U)  /*!< MDMA HW request is DMA1 Stream 6 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA1_Stream7_TC      ((uint32_t)0x00000007U)  /*!< MDMA HW request is DMA1 Stream 7 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA2_Stream0_TC      ((uint32_t)0x00000008U)  /*!< MDMA HW request is DMA2 Stream 0 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA2_Stream1_TC      ((uint32_t)0x00000009U)  /*!< MDMA HW request is DMA2 Stream 1 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA2_Stream2_TC      ((uint32_t)0x0000000AU)  /*!< MDMA HW request is DMA2 Stream 2 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA2_Stream3_TC      ((uint32_t)0x0000000BU)  /*!< MDMA HW request is DMA2 Stream 3 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA2_Stream4_TC      ((uint32_t)0x0000000CU)  /*!< MDMA HW request is DMA2 Stream 4 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA2_Stream5_TC      ((uint32_t)0x0000000DU)  /*!< MDMA HW request is DMA2 Stream 5 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA2_Stream6_TC      ((uint32_t)0x0000000EU)  /*!< MDMA HW request is DMA2 Stream 6 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA2_Stream7_TC      ((uint32_t)0x0000000FU)  /*!< MDMA HW request is DMA2 Stream 7 Transfer Complete Flag   */
+#if defined (LTDC)
+#define MDMA_REQUEST_LTDC_LINE_IT         ((uint32_t)0x00000010U)  /*!< MDMA HW request is LTDC Line interrupt Flag               */
+#endif /* LTDC */
+#if defined (JPEG)
+#define MDMA_REQUEST_JPEG_INFIFO_TH       ((uint32_t)0x00000011U)  /*!< MDMA HW request is JPEG Input FIFO threshold Flag         */
+#define MDMA_REQUEST_JPEG_INFIFO_NF       ((uint32_t)0x00000012U)  /*!< MDMA HW request is JPEG Input FIFO not full Flag          */
+#define MDMA_REQUEST_JPEG_OUTFIFO_TH      ((uint32_t)0x00000013U)  /*!< MDMA HW request is JPEG Output FIFO threshold Flag        */
+#define MDMA_REQUEST_JPEG_OUTFIFO_NE      ((uint32_t)0x00000014U)  /*!< MDMA HW request is JPEG Output FIFO not empty Flag        */
+#define MDMA_REQUEST_JPEG_END_CONVERSION  ((uint32_t)0x00000015U)  /*!< MDMA HW request is JPEG End of conversion Flag            */
+#endif /* JPEG */
+#if defined (OCTOSPI1)
+#define MDMA_REQUEST_OCTOSPI1_FIFO_TH     ((uint32_t)0x00000016U)  /*!< MDMA HW request is OCTOSPI1 FIFO threshold Flag           */
+#define MDMA_REQUEST_OCTOSPI1_TC          ((uint32_t)0x00000017U)  /*!< MDMA HW request is OCTOSPI1 Transfer complete Flag        */
+#endif /* OCTOSPI1 */
+#if defined (QUADSPI)
+#define MDMA_REQUEST_QUADSPI_FIFO_TH      ((uint32_t)0x00000016U)  /*!< MDMA HW request is QSPI FIFO threshold Flag               */
+#define MDMA_REQUEST_QUADSPI_TC           ((uint32_t)0x00000017U)  /*!< MDMA HW request is QSPI Transfer complete Flag            */
+#endif /* QUADSPI */
+#define MDMA_REQUEST_DMA2D_CLUT_TC        ((uint32_t)0x00000018U)  /*!< MDMA HW request is DMA2D CLUT Transfer Complete Flag      */
+#define MDMA_REQUEST_DMA2D_TC             ((uint32_t)0x00000019U)  /*!< MDMA HW request is DMA2D Transfer Complete Flag           */
+#define MDMA_REQUEST_DMA2D_TW             ((uint32_t)0x0000001AU)  /*!< MDMA HW request is DMA2D Transfer Watermark Flag          */
+
+#if defined (DSI)
+#define MDMA_REQUEST_DSI_TEARING_EFFECT   ((uint32_t)0x0000001BU)  /*!< MDMA HW request is DSI Tearing Effect Flag                */
+#define MDMA_REQUEST_DSI_END_REFRESH      ((uint32_t)0x0000001CU)  /*!< MDMA HW request is DSI End of refresh  Flag               */
+#endif /* DSI */
+
+#define MDMA_REQUEST_SDMMC1_END_DATA      ((uint32_t)0x0000001DU)  /*!< MDMA HW request is SDMMC1 End of Data Flag                */
+
+#define MDMA_REQUEST_SDMMC1_DMA_ENDBUFFER ((uint32_t)0x0000001EU)  /*!< MDMA HW request is SDMMC1 Internal DMA buffer End Flag    */
+#define MDMA_REQUEST_SDMMC1_COMMAND_END   ((uint32_t)0x0000001FU)  /*!< MDMA HW request is SDMMC1 Command End Flag                */
+
+#if defined (OCTOSPI2)
+#define MDMA_REQUEST_OCTOSPI2_FIFO_TH     ((uint32_t)0x00000020U)  /*!< MDMA HW request is OCTOSPI2 FIFO threshold Flag           */
+#define MDMA_REQUEST_OCTOSPI2_TC          ((uint32_t)0x00000021U)  /*!< MDMA HW request is OCTOSPI2 Transfer complete Flag        */
+#endif /* OCTOSPI2 */
+
+#define MDMA_REQUEST_SW                   ((uint32_t)0x40000000U) /*!< MDMA SW request                                            */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_Transfer_TriggerMode MDMA Transfer Trigger  Mode
+  * @brief    MDMA Transfer Trigger Mode
+  * @{
+  */
+#define MDMA_BUFFER_TRANSFER          ((uint32_t)0x00000000U)        /*!< Each MDMA request (SW or HW) triggers a buffer transfer                                */
+#define MDMA_BLOCK_TRANSFER           ((uint32_t)MDMA_CTCR_TRGM_0)   /*!< Each MDMA request (SW or HW) triggers a block transfer                                 */
+#define MDMA_REPEAT_BLOCK_TRANSFER    ((uint32_t)MDMA_CTCR_TRGM_1)   /*!< Each MDMA request (SW or HW) triggers a repeated block transfer                        */
+#define MDMA_FULL_TRANSFER            ((uint32_t)MDMA_CTCR_TRGM)     /*!< Each MDMA request (SW or HW) triggers a Full transfer or a linked list transfer if any */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_Priority_level MDMA Priority level
+  * @brief    MDMA Priority level
+  * @{
+  */
+#define MDMA_PRIORITY_LOW             ((uint32_t)0x00000000U)     /*!< Priority level: Low      */
+#define MDMA_PRIORITY_MEDIUM          ((uint32_t)MDMA_CCR_PL_0)  /*!< Priority level: Medium    */
+#define MDMA_PRIORITY_HIGH            ((uint32_t)MDMA_CCR_PL_1)  /*!< Priority level: High      */
+#define MDMA_PRIORITY_VERY_HIGH       ((uint32_t)MDMA_CCR_PL)    /*!< Priority level: Very High */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup MDMA_Endianness MDMA Endianness
+  * @brief    MDMA Endianness
+  * @{
+  */
+#define MDMA_LITTLE_ENDIANNESS_PRESERVE          ((uint32_t)0x00000000U)   /*!< little endianness preserve                                               */
+#define MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE     ((uint32_t)MDMA_CCR_BEX)  /*!< BYTEs endianness exchange when destination data size is > Byte           */
+#define MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_HEX)  /*!< HALF WORDs endianness exchange when destination data size is > HALF WORD */
+#define MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE     ((uint32_t)MDMA_CCR_WEX)  /*!< WORDs endianness exchange  when destination data size is > DOUBLE WORD   */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_Source_increment_mode MDMA Source increment mode
+  * @brief    MDMA Source increment mode
+  * @{
+  */
+#define MDMA_SRC_INC_DISABLE      ((uint32_t)0x00000000U)                                     /*!< Source address pointer is fixed                                   */
+#define MDMA_SRC_INC_BYTE         ((uint32_t)MDMA_CTCR_SINC_1)                                /*!< Source address pointer is incremented by a BYTE (8 bits)          */
+#define MDMA_SRC_INC_HALFWORD     ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits)    */
+#define MDMA_SRC_INC_WORD         ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits)         */
+#define MDMA_SRC_INC_DOUBLEWORD   ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS)   /*!< Source address pointer is incremented by a double Word (64 bits)) */
+#define MDMA_SRC_DEC_BYTE         ((uint32_t)MDMA_CTCR_SINC)                                  /*!< Source address pointer is decremented by a BYTE (8 bits)          */
+#define MDMA_SRC_DEC_HALFWORD     ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_0)   /*!< Source address pointer is decremented by a half Word (16 bits)    */
+#define MDMA_SRC_DEC_WORD         ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_1)   /*!< Source address pointer is decremented by a Word (32 bits)         */
+#define MDMA_SRC_DEC_DOUBLEWORD   ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS)     /*!< Source address pointer is decremented by a double Word (64 bits)) */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_Destination_increment_mode MDMA Destination increment mode
+  * @brief    MDMA Destination increment mode
+  * @{
+  */
+#define MDMA_DEST_INC_DISABLE      ((uint32_t)0x00000000U)                                     /*!< Source address pointer is fixed                                   */
+#define MDMA_DEST_INC_BYTE         ((uint32_t)MDMA_CTCR_DINC_1)                                /*!< Source address pointer is incremented by a BYTE (8 bits)          */
+#define MDMA_DEST_INC_HALFWORD     ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits)    */
+#define MDMA_DEST_INC_WORD         ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits)         */
+#define MDMA_DEST_INC_DOUBLEWORD   ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS)   /*!< Source address pointer is incremented by a double Word (64 bits)) */
+#define MDMA_DEST_DEC_BYTE         ((uint32_t)MDMA_CTCR_DINC)                                  /*!< Source address pointer is decremented by a BYTE (8 bits)          */
+#define MDMA_DEST_DEC_HALFWORD     ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_0)   /*!< Source address pointer is decremented by a half Word (16 bits)    */
+#define MDMA_DEST_DEC_WORD         ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_1)   /*!< Source address pointer is decremented by a Word (32 bits)         */
+#define MDMA_DEST_DEC_DOUBLEWORD   ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS)     /*!< Source address pointer is decremented by a double Word (64 bits)) */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_Source_data_size MDMA Source data size
+  * @brief    MDMA Source data size
+  * @{
+  */
+#define MDMA_SRC_DATASIZE_BYTE        ((uint32_t)0x00000000U)         /*!< Source data size is Byte        */
+#define MDMA_SRC_DATASIZE_HALFWORD    ((uint32_t)MDMA_CTCR_SSIZE_0)   /*!< Source data size is half word   */
+#define MDMA_SRC_DATASIZE_WORD        ((uint32_t)MDMA_CTCR_SSIZE_1)   /*!< Source data size is word        */
+#define MDMA_SRC_DATASIZE_DOUBLEWORD  ((uint32_t)MDMA_CTCR_SSIZE)     /*!< Source data size is double word */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_Destination_data_size MDMA Destination data size
+  * @brief    MDMA Destination data size
+  * @{
+  */
+#define MDMA_DEST_DATASIZE_BYTE        ((uint32_t)0x00000000U)         /*!< Destination data size is Byte        */
+#define MDMA_DEST_DATASIZE_HALFWORD    ((uint32_t)MDMA_CTCR_DSIZE_0)   /*!< Destination data size is half word   */
+#define MDMA_DEST_DATASIZE_WORD        ((uint32_t)MDMA_CTCR_DSIZE_1)   /*!< Destination data size is word        */
+#define MDMA_DEST_DATASIZE_DOUBLEWORD  ((uint32_t)MDMA_CTCR_DSIZE)     /*!< Destination data size is double word */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_data_Alignment MDMA data alignment
+  * @brief    MDMA data alignment
+  * @{
+  */
+#define MDMA_DATAALIGN_PACKENABLE        ((uint32_t)MDMA_CTCR_PKE)     /*!< The source data is packed/un-packed into the destination data size
+                                                                            All data are right aligned, in Little Endien mode.                                              */
+#define MDMA_DATAALIGN_RIGHT            ((uint32_t)0x00000000U)        /*!< Right Aligned, padded w/ 0s (default)                                                           */
+#define MDMA_DATAALIGN_RIGHT_SIGNED     ((uint32_t)MDMA_CTCR_PAM_0)    /*!< Right Aligned, Sign extended ,
+                                                                            Note : this mode is allowed only if the Source data size is smaller than Destination data size  */
+#define MDMA_DATAALIGN_LEFT             ((uint32_t)MDMA_CTCR_PAM_1)    /*!< Left Aligned (padded with 0s)                                                                   */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_Source_burst MDMA Source burst
+  * @brief    MDMA Source burst
+  * @{
+  */
+#define MDMA_SOURCE_BURST_SINGLE        ((uint32_t)0x00000000U)                                       /*!< single transfer */
+#define MDMA_SOURCE_BURST_2BEATS        ((uint32_t)MDMA_CTCR_SBURST_0)                                /*!< Burst 2 beats   */
+#define MDMA_SOURCE_BURST_4BEATS        ((uint32_t)MDMA_CTCR_SBURST_1)                                /*!< Burst 4 beats   */
+#define MDMA_SOURCE_BURST_8BEATS        ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_1) /*!< Burst 8 beats   */
+#define MDMA_SOURCE_BURST_16BEATS       ((uint32_t)MDMA_CTCR_SBURST_2)                                /*!< Burst 16 beats  */
+#define MDMA_SOURCE_BURST_32BEATS       ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 32 beats  */
+#define MDMA_SOURCE_BURST_64BEATS       ((uint32_t)MDMA_CTCR_SBURST_1 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 64 beats  */
+#define MDMA_SOURCE_BURST_128BEATS      ((uint32_t)MDMA_CTCR_SBURST)                                  /*!< Burst 128 beats */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_Destination_burst MDMA Destination burst
+  * @brief    MDMA Destination burst
+  * @{
+  */
+#define MDMA_DEST_BURST_SINGLE        ((uint32_t)0x00000000U)                                        /*!< single transfer */
+#define MDMA_DEST_BURST_2BEATS        ((uint32_t)MDMA_CTCR_DBURST_0)                                 /*!< Burst 2 beats   */
+#define MDMA_DEST_BURST_4BEATS        ((uint32_t)MDMA_CTCR_DBURST_1)                                 /*!< Burst 4 beats   */
+#define MDMA_DEST_BURST_8BEATS        ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_1)  /*!< Burst 8 beats   */
+#define MDMA_DEST_BURST_16BEATS       ((uint32_t)MDMA_CTCR_DBURST_2)                                 /*!< Burst 16 beats  */
+#define MDMA_DEST_BURST_32BEATS       ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_2)  /*!< Burst 32 beats  */
+#define MDMA_DEST_BURST_64BEATS       ((uint32_t)MDMA_CTCR_DBURST_1 | (uint32_t)MDMA_CTCR_DBURST_2)  /*!< Burst 64 beats  */
+#define MDMA_DEST_BURST_128BEATS      ((uint32_t)MDMA_CTCR_DBURST)                                   /*!< Burst 128 beats */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_interrupt_enable_definitions MDMA interrupt enable definitions
+  * @brief    MDMA interrupt enable definitions
+  * @{
+  */
+#define MDMA_IT_TE   ((uint32_t)MDMA_CCR_TEIE)   /*!< Transfer Error interrupt            */
+#define MDMA_IT_CTC  ((uint32_t)MDMA_CCR_CTCIE)  /*!< Channel Transfer Complete interrupt */
+#define MDMA_IT_BRT  ((uint32_t)MDMA_CCR_BRTIE)  /*!< Block Repeat Transfer interrupt     */
+#define MDMA_IT_BT   ((uint32_t)MDMA_CCR_BTIE)   /*!< Block Transfer interrupt            */
+#define MDMA_IT_BFTC ((uint32_t)MDMA_CCR_TCIE)   /*!< Buffer Transfer Complete interrupt  */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_flag_definitions MDMA flag definitions
+  * @brief    MDMA flag definitions
+  * @{
+  */
+#define MDMA_FLAG_TE    ((uint32_t)MDMA_CISR_TEIF)  /*!< Transfer Error flag                 */
+#define MDMA_FLAG_CTC   ((uint32_t)MDMA_CISR_CTCIF) /*!< Channel Transfer Complete flag      */
+#define MDMA_FLAG_BRT   ((uint32_t)MDMA_CISR_BRTIF) /*!< Block Repeat Transfer complete flag */
+#define MDMA_FLAG_BT    ((uint32_t)MDMA_CISR_BTIF)  /*!< Block Transfer complete flag        */
+#define MDMA_FLAG_BFTC  ((uint32_t)MDMA_CISR_TCIF)  /*!< BuFfer Transfer complete flag       */
+#define MDMA_FLAG_CRQA  ((uint32_t)MDMA_CISR_CRQA)  /*!< Channel ReQest Active flag          */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup MDMA_Exported_Macros MDMA Exported Macros
+  * @{
+  */
+
+/**
+  * @brief  Enable the specified MDMA Channel.
+  * @param  __HANDLE__: MDMA handle
+  * @retval None
+  */
+#define __HAL_MDMA_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CCR |=  MDMA_CCR_EN)
+
+/**
+  * @brief  Disable the specified MDMA Channel.
+  * @param  __HANDLE__: MDMA handle
+  * @retval None
+  */
+#define __HAL_MDMA_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CCR &=  ~MDMA_CCR_EN)
+
+/**
+  * @brief  Get the MDMA Channel pending flags.
+  * @param  __HANDLE__: MDMA handle
+  * @param  __FLAG__: Get the specified flag.
+  *          This parameter can be any combination of the following values:
+  *            @arg MDMA_FLAG_TE   : Transfer Error flag.
+  *            @arg MDMA_FLAG_CTC  : Channel Transfer Complete flag.
+  *            @arg MDMA_FLAG_BRT  : Block Repeat Transfer flag.
+  *            @arg MDMA_FLAG_BT   : Block Transfer complete flag.
+  *            @arg MDMA_FLAG_BFTC : BuFfer Transfer Complete flag.
+  *            @arg MDMA_FLAG_CRQA : Channel ReQest Active flag.
+  * @retval The state of FLAG (SET or RESET).
+  */
+#define __HAL_MDMA_GET_FLAG(__HANDLE__, __FLAG__)  ((__HANDLE__)->Instance->CISR & (__FLAG__))
+
+/**
+  * @brief  Clear the MDMA Stream pending flags.
+  * @param  __HANDLE__: MDMA handle
+  * @param  __FLAG__: specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg MDMA_FLAG_TE   : Transfer Error flag.
+  *            @arg MDMA_FLAG_CTC  : Channel Transfer Complete flag.
+  *            @arg MDMA_FLAG_BRT  : Block Repeat Transfer flag.
+  *            @arg MDMA_FLAG_BT   : Block Transfer complete flag.
+  *            @arg MDMA_FLAG_BFTC : BuFfer Transfer Complete flag.
+  * @retval None
+  */
+#define __HAL_MDMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CIFCR = (__FLAG__))
+
+/**
+  * @brief  Enables the specified MDMA Channel interrupts.
+  * @param  __HANDLE__: MDMA handle
+  * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg MDMA_IT_TE   :  Transfer Error interrupt mask
+  *            @arg MDMA_IT_CTC  :  Channel Transfer Complete interrupt mask
+  *            @arg MDMA_IT_BRT  :  Block Repeat Transfer interrupt mask
+  *            @arg MDMA_IT_BT   :  Block Transfer interrupt mask
+  *            @arg MDMA_IT_BFTC :  BuFfer Transfer Complete interrupt mask
+  * @retval None
+  */
+#define __HAL_MDMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
+
+/**
+  * @brief  Disables the specified MDMA Channel interrupts.
+  * @param  __HANDLE__: MDMA handle
+  * @param __INTERRUPT__: specifies the MDMA interrupt sources to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg MDMA_IT_TE   :  Transfer Error interrupt mask
+  *            @arg MDMA_IT_CTC  :  Channel Transfer Complete interrupt mask
+  *            @arg MDMA_IT_BRT  :  Block Repeat Transfer interrupt mask
+  *            @arg MDMA_IT_BT   :  Block Transfer interrupt mask
+  *            @arg MDMA_IT_BFTC :  BuFfer Transfer Complete interrupt mask
+  * @retval None
+  */
+#define __HAL_MDMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Checks whether the specified MDMA Channel interrupt is enabled or not.
+  * @param  __HANDLE__: DMA handle
+  * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
+  *            @arg MDMA_IT_TE   :  Transfer Error interrupt mask
+  *            @arg MDMA_IT_CTC  :  Channel Transfer Complete interrupt mask
+  *            @arg MDMA_IT_BRT  :  Block Repeat Transfer interrupt mask
+  *            @arg MDMA_IT_BT   :  Block Transfer interrupt mask
+  *            @arg MDMA_IT_BFTC :  BuFfer Transfer Complete interrupt mask
+  * @retval The state of MDMA_IT (SET or RESET).
+  */
+#define __HAL_MDMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup MDMA_Exported_Functions  MDMA Exported Functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions *****************************/
+/** @defgroup MDMA_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief   Initialization and de-initialization functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_MDMA_Init(MDMA_HandleTypeDef *hmdma);
+HAL_StatusTypeDef HAL_MDMA_DeInit (MDMA_HandleTypeDef *hmdma);
+HAL_StatusTypeDef HAL_MDMA_ConfigPostRequestMask(MDMA_HandleTypeDef *hmdma, uint32_t MaskAddress, uint32_t MaskData);
+
+HAL_StatusTypeDef HAL_MDMA_RegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID, void (* pCallback)(MDMA_HandleTypeDef *_hmdma));
+HAL_StatusTypeDef HAL_MDMA_UnRegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID);
+
+/**
+  * @}
+  */
+
+/* Linked list operation functions ********************************************/
+/** @defgroup MDMA_Exported_Functions_Group2 Linked List operation functions
+  * @brief   Linked list operation functions
+  * @{
+  */
+
+HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig);
+HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, MDMA_LinkNodeTypeDef *pPrevNode);
+HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNode);
+HAL_StatusTypeDef HAL_MDMA_LinkedList_EnableCircularMode(MDMA_HandleTypeDef *hmdma);
+HAL_StatusTypeDef HAL_MDMA_LinkedList_DisableCircularMode(MDMA_HandleTypeDef *hmdma);
+
+
+/**
+  * @}
+  */
+
+/* IO operation functions *****************************************************/
+/** @defgroup MDMA_Exported_Functions_Group3 I/O operation functions
+  * @brief   I/O operation functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_MDMA_Start (MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount);
+HAL_StatusTypeDef HAL_MDMA_Start_IT(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount);
+HAL_StatusTypeDef HAL_MDMA_Abort(MDMA_HandleTypeDef *hmdma);
+HAL_StatusTypeDef HAL_MDMA_Abort_IT(MDMA_HandleTypeDef *hmdma);
+HAL_StatusTypeDef HAL_MDMA_PollForTransfer(MDMA_HandleTypeDef *hmdma, HAL_MDMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
+HAL_StatusTypeDef HAL_MDMA_GenerateSWRequest(MDMA_HandleTypeDef *hmdma);
+void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma);
+
+/**
+  * @}
+  */
+
+/* Peripheral State and Error functions ***************************************/
+/** @defgroup MDMA_Exported_Functions_Group4 Peripheral State functions
+  * @brief    Peripheral State functions
+  * @{
+  */
+HAL_MDMA_StateTypeDef HAL_MDMA_GetState(MDMA_HandleTypeDef *hmdma);
+uint32_t              HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup MDMA_Private_Types MDMA Private Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup MDMA_Private_Defines MDMA Private Defines
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup MDMA_Private_Variables MDMA Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup MDMA_Private_Constants MDMA Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup MDMA_Private_Macros MDMA Private Macros
+  * @{
+  */
+
+#define IS_MDMA_LEVEL_COMPLETE(__LEVEL__) (((__LEVEL__) == HAL_MDMA_FULL_TRANSFER )  || \
+                                           ((__LEVEL__) == HAL_MDMA_BUFFER_TRANSFER )|| \
+                                           ((__LEVEL__) == HAL_MDMA_BLOCK_TRANSFER ) || \
+                                           ((__LEVEL__) == HAL_MDMA_REPEAT_BLOCK_TRANSFER ))
+
+
+#define IS_MDMA_PRIORITY(__PRIORITY__) (((__PRIORITY__) == MDMA_PRIORITY_LOW )   || \
+                                        ((__PRIORITY__) == MDMA_PRIORITY_MEDIUM) || \
+                                        ((__PRIORITY__) == MDMA_PRIORITY_HIGH)   || \
+                                        ((__PRIORITY__) == MDMA_PRIORITY_VERY_HIGH))
+
+#define IS_MDMA_ENDIANNESS_MODE(__ENDIANNESS__) (((__ENDIANNESS__) == MDMA_LITTLE_ENDIANNESS_PRESERVE )         || \
+                                                 ((__ENDIANNESS__) == MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE)     || \
+                                                 ((__ENDIANNESS__) == MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE) || \
+                                                 ((__ENDIANNESS__) == MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE))
+
+
+#if defined (OCTOSPI2)
+#define IS_MDMA_REQUEST(__REQUEST__) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_OCTOSPI2_TC))
+#else
+#define IS_MDMA_REQUEST(__REQUEST__) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_SDMMC1_COMMAND_END))
+#endif /* OCTOSPI2 */
+
+#define IS_MDMA_SOURCE_INC(__INC__) (((__INC__) == MDMA_SRC_INC_DISABLE )   || \
+                                     ((__INC__) == MDMA_SRC_INC_BYTE )      || \
+                                     ((__INC__) == MDMA_SRC_INC_HALFWORD )  || \
+                                     ((__INC__) == MDMA_SRC_INC_WORD )      || \
+                                     ((__INC__) == MDMA_SRC_INC_DOUBLEWORD) || \
+                                     ((__INC__) == MDMA_SRC_DEC_BYTE)       || \
+                                     ((__INC__) == MDMA_SRC_DEC_HALFWORD)   || \
+                                     ((__INC__) == MDMA_SRC_DEC_WORD)       || \
+                                     ((__INC__) == MDMA_SRC_DEC_DOUBLEWORD))
+
+#define IS_MDMA_DESTINATION_INC(__INC__) (((__INC__) == MDMA_DEST_INC_DISABLE )   || \
+                                          ((__INC__) == MDMA_DEST_INC_BYTE )      || \
+                                          ((__INC__) == MDMA_DEST_INC_HALFWORD )  || \
+                                          ((__INC__) == MDMA_DEST_INC_WORD )      || \
+                                          ((__INC__) == MDMA_DEST_INC_DOUBLEWORD) || \
+                                          ((__INC__) == MDMA_DEST_DEC_BYTE)       || \
+                                          ((__INC__) == MDMA_DEST_DEC_HALFWORD)   || \
+                                          ((__INC__) == MDMA_DEST_DEC_WORD)       || \
+                                          ((__INC__) == MDMA_DEST_DEC_DOUBLEWORD))
+
+#define IS_MDMA_SOURCE_DATASIZE(__SIZE__) (((__SIZE__) == MDMA_SRC_DATASIZE_BYTE )     || \
+                                           ((__SIZE__) == MDMA_SRC_DATASIZE_HALFWORD ) || \
+                                           ((__SIZE__) == MDMA_SRC_DATASIZE_WORD )     || \
+                                           ((__SIZE__) == MDMA_SRC_DATASIZE_DOUBLEWORD))
+
+#define IS_MDMA_DESTINATION_DATASIZE(__SIZE__) (((__SIZE__) == MDMA_DEST_DATASIZE_BYTE )     || \
+                                                ((__SIZE__) == MDMA_DEST_DATASIZE_HALFWORD ) || \
+                                                ((__SIZE__) == MDMA_DEST_DATASIZE_WORD )     || \
+                                                ((__SIZE__) == MDMA_DEST_DATASIZE_DOUBLEWORD))
+
+#define IS_MDMA_DATA_ALIGNMENT(__ALIGNMENT__) (((__ALIGNMENT__) == MDMA_DATAALIGN_PACKENABLE )    || \
+                                               ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT )         || \
+                                               ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT_SIGNED )  || \
+                                               ((__ALIGNMENT__) == MDMA_DATAALIGN_LEFT))
+
+
+#define IS_MDMA_SOURCE_BURST(__BURST__) (((__BURST__) == MDMA_SOURCE_BURST_SINGLE ) || \
+                                         ((__BURST__) == MDMA_SOURCE_BURST_2BEATS ) || \
+                                         ((__BURST__) == MDMA_SOURCE_BURST_4BEATS ) || \
+                                         ((__BURST__) == MDMA_SOURCE_BURST_8BEATS)  || \
+                                         ((__BURST__) == MDMA_SOURCE_BURST_16BEATS) || \
+                                         ((__BURST__) == MDMA_SOURCE_BURST_32BEATS) || \
+                                         ((__BURST__) == MDMA_SOURCE_BURST_64BEATS) || \
+                                         ((__BURST__) == MDMA_SOURCE_BURST_128BEATS))
+
+
+#define IS_MDMA_DESTINATION_BURST(__BURST__) (((__BURST__) == MDMA_DEST_BURST_SINGLE ) || \
+                                              ((__BURST__) == MDMA_DEST_BURST_2BEATS ) || \
+                                              ((__BURST__) == MDMA_DEST_BURST_4BEATS ) || \
+                                              ((__BURST__) == MDMA_DEST_BURST_8BEATS)  || \
+                                              ((__BURST__) == MDMA_DEST_BURST_16BEATS) || \
+                                              ((__BURST__) == MDMA_DEST_BURST_32BEATS) || \
+                                              ((__BURST__) == MDMA_DEST_BURST_64BEATS) || \
+                                              ((__BURST__) == MDMA_DEST_BURST_128BEATS))
+
+ #define IS_MDMA_TRANSFER_TRIGGER_MODE(__MODE__) (((__MODE__) == MDMA_BUFFER_TRANSFER )      || \
+                                                  ((__MODE__) == MDMA_BLOCK_TRANSFER )        || \
+                                                  ((__MODE__) == MDMA_REPEAT_BLOCK_TRANSFER ) || \
+                                                  ((__MODE__) == MDMA_FULL_TRANSFER))
+
+#define IS_MDMA_BUFFER_TRANSFER_LENGTH(__LENGTH__) (((__LENGTH__) >= 0x00000001U) && ((__LENGTH__) < 0x000000FFU))
+
+#define IS_MDMA_BLOCK_COUNT(__COUNT__) (((__COUNT__) > 0U ) && ((__COUNT__) <= 4096U))
+
+#define IS_MDMA_TRANSFER_LENGTH(SIZE) (((SIZE) > 0U) && ((SIZE) <= 65536U))
+
+#define IS_MDMA_BLOCK_ADDR_OFFSET(__BLOCK_ADD_OFFSET__) (((__BLOCK_ADD_OFFSET__) > (-65536)) && ((__BLOCK_ADD_OFFSET__) < 65536))
+
+/**
+  * @}
+  */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup MDMA_Private_Functions_Prototypes MDMA Private Functions Prototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup MDMA_Private_Functions MDMA Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_MDMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h
new file mode 100644
index 00000000..0d462402
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h
@@ -0,0 +1,774 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_pwr.h
+  * @author  MCD Application Team
+  * @brief   Header file of PWR HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_PWR_H
+#define STM32H7xx_HAL_PWR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup PWR
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Types PWR Exported Types
+  * @{
+  */
+
+/**
+  * @brief  PWR PVD configuration structure definition
+  */
+typedef struct
+{
+  uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. This
+                                    parameter can be a value of @ref
+                                    PWR_PVD_detection_level.
+                     */
+
+  uint32_t Mode;     /*!< Mode: Specifies the EXTI operating mode for the PVD
+                                event. This parameter can be a value of @ref
+                                PWR_PVD_Mode.
+                     */
+}PWR_PVDTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PWR_Exported_Constants PWR Exported Constants
+  * @{
+  */
+
+/** @defgroup PWR_PVD_detection_level PWR PVD detection level
+  * @{
+  */
+#define PWR_PVDLEVEL_0  PWR_CR1_PLS_LEV0  /*!< Programmable voltage detector
+                                               level 0 selection : 1V95       */
+#define PWR_PVDLEVEL_1  PWR_CR1_PLS_LEV1  /*!< Programmable voltage detector
+                                               level 1 selection : 2V1        */
+#define PWR_PVDLEVEL_2  PWR_CR1_PLS_LEV2  /*!< Programmable voltage detector
+                                               level 2 selection : 2V25       */
+#define PWR_PVDLEVEL_3  PWR_CR1_PLS_LEV3  /*!< Programmable voltage detector
+                                               level 3 selection : 2V4        */
+#define PWR_PVDLEVEL_4  PWR_CR1_PLS_LEV4  /*!< Programmable voltage detector
+                                               level 4 selection : 2V55       */
+#define PWR_PVDLEVEL_5  PWR_CR1_PLS_LEV5  /*!< Programmable voltage detector
+                                               level 5 selection : 2V7        */
+#define PWR_PVDLEVEL_6  PWR_CR1_PLS_LEV6  /*!< Programmable voltage detector
+                                               level 6 selection : 2V85       */
+#define PWR_PVDLEVEL_7  PWR_CR1_PLS_LEV7  /*!< External input analog voltage
+                                               (Compare internally to VREF)   */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_PVD_Mode PWR PVD Mode
+  * @{
+  */
+#define PWR_PVD_MODE_NORMAL               (0x00000000U) /*!< Basic mode is used                                        */
+#define PWR_PVD_MODE_IT_RISING            (0x00010001U) /*!< Interrupt Mode with Rising edge trigger detection         */
+#define PWR_PVD_MODE_IT_FALLING           (0x00010002U) /*!< Interrupt Mode with Falling edge trigger detection        */
+#define PWR_PVD_MODE_IT_RISING_FALLING    (0x00010003U) /*!< Interrupt Mode with Rising/Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING         (0x00020001U) /*!< Event Mode with Rising edge trigger detection             */
+#define PWR_PVD_MODE_EVENT_FALLING        (0x00020002U) /*!< Event Mode with Falling edge trigger detection            */
+#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection     */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
+  * @{
+  */
+#define PWR_MAINREGULATOR_ON      (0U)
+#define PWR_LOWPOWERREGULATOR_ON  PWR_CR1_LPDS
+/**
+  * @}
+  */
+
+/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
+  * @{
+  */
+#define PWR_SLEEPENTRY_WFI  (0x01U)
+#define PWR_SLEEPENTRY_WFE  (0x02U)
+/**
+  * @}
+  */
+
+/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
+  * @{
+  */
+#define PWR_STOPENTRY_WFI  (0x01U)
+#define PWR_STOPENTRY_WFE  (0x02U)
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale
+  * @{
+  */
+#if defined(PWR_SRDCR_VOS)
+#define PWR_REGULATOR_VOLTAGE_SCALE0  (PWR_SRDCR_VOS_1 | PWR_SRDCR_VOS_0)
+#define PWR_REGULATOR_VOLTAGE_SCALE1  (PWR_SRDCR_VOS_1)
+#define PWR_REGULATOR_VOLTAGE_SCALE2  (PWR_SRDCR_VOS_0)
+#define PWR_REGULATOR_VOLTAGE_SCALE3  (0U)
+#else
+#define PWR_REGULATOR_VOLTAGE_SCALE0  (0U)
+#define PWR_REGULATOR_VOLTAGE_SCALE1  (PWR_D3CR_VOS_1 | PWR_D3CR_VOS_0)
+#define PWR_REGULATOR_VOLTAGE_SCALE2  (PWR_D3CR_VOS_1)
+#define PWR_REGULATOR_VOLTAGE_SCALE3  (PWR_D3CR_VOS_0)
+#endif /* PWR_SRDCR_VOS */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Flag PWR Flag
+  * @{
+  */
+/* PWR CPU flag */
+#define PWR_FLAG_STOP       (0x01U)
+#if defined (PWR_CPUCR_SBF_D2)
+#define PWR_FLAG_SB_D1      (0x02U)
+#define PWR_FLAG_SB_D2      (0x03U)
+#endif /* defined (PWR_CPUCR_SBF_D2) */
+#define PWR_FLAG_SB         (0x04U)
+#if defined (DUAL_CORE)
+#define PWR_FLAG_CPU_HOLD   (0x05U)
+#define PWR_FLAG_CPU2_HOLD  (0x06U)
+#define PWR_FLAG2_STOP      (0x07U)
+#define PWR_FLAG2_SB_D1     (0x08U)
+#define PWR_FLAG2_SB_D2     (0x09U)
+#define PWR_FLAG2_SB        (0x0AU)
+#endif /* defined (DUAL_CORE) */
+#define PWR_FLAG_PVDO       (0x0BU)
+#define PWR_FLAG_AVDO       (0x0CU)
+#define PWR_FLAG_ACTVOSRDY  (0x0DU)
+#define PWR_FLAG_ACTVOS     (0x0EU)
+#define PWR_FLAG_BRR        (0x0FU)
+#define PWR_FLAG_VOSRDY     (0x10U)
+#if defined (SMPS)
+#define PWR_FLAG_SMPSEXTRDY (0x11U)
+#else
+#define PWR_FLAG_SCUEN      (0x11U)
+#endif /* defined (SMPS) */
+#if defined (PWR_CSR1_MMCVDO)
+#define PWR_FLAG_MMCVDO     (0x12U)
+#endif /* defined (PWR_CSR1_MMCVDO) */
+#define PWR_FLAG_USB33RDY   (0x13U)
+#define PWR_FLAG_TEMPH      (0x14U)
+#define PWR_FLAG_TEMPL      (0x15U)
+#define PWR_FLAG_VBATH      (0x16U)
+#define PWR_FLAG_VBATL      (0x17U)
+
+/* PWR Wake up flag */
+#define PWR_FLAG_WKUP1 PWR_WKUPCR_WKUPC1
+#define PWR_FLAG_WKUP2 PWR_WKUPCR_WKUPC2
+#define PWR_FLAG_WKUP3 PWR_WKUPCR_WKUPC3
+#define PWR_FLAG_WKUP4 PWR_WKUPCR_WKUPC4
+#define PWR_FLAG_WKUP5 PWR_WKUPCR_WKUPC5
+#define PWR_FLAG_WKUP6 PWR_WKUPCR_WKUPC6
+/**
+  * @}
+  */
+
+/** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask
+  * @{
+  */
+#define  PWR_EWUP_MASK  (0x0FFF3F3FU)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PWR_Exported_Macro PWR Exported Macro
+  * @{
+  */
+
+/** @brief  Configure the main internal regulator output voltage.
+  * @param  __REGULATOR__ : Specifies the regulator output voltage to achieve a
+  *                         trade-off between performance and power consumption
+  *                         when the device does not operate at the maximum
+  *                         frequency (refer to the datasheet for more details).
+  *          This parameter can be one of the following values:
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE0 : Regulator voltage output
+  *                                                Scale 0 mode.
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output
+  *                                                Scale 1 mode.
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output
+  *                                                Scale 2 mode.
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output
+  *                                                Scale 3 mode.
+  * @note   For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines,
+  *         configuring Voltage Scale 0 is only possible when Vcore is supplied
+  *         from LDO (Low DropOut). The SYSCFG Clock must be enabled through
+  *         __HAL_RCC_SYSCFG_CLK_ENABLE() macro before configuring Voltage Scale
+  *         0 using __HAL_PWR_VOLTAGESCALING_CONFIG().
+  *         Transition to Voltage Scale 0 is only possible when the system is
+  *         already in Voltage Scale 1.
+  *         Transition from Voltage Scale 0 is only possible to Voltage Scale 1
+  *         then once in Voltage Scale 1 it is possible to switch to another
+  *         voltage scale.
+  *         After each regulator voltage setting, wait on VOSRDY flag to be set
+  *         using macro __HAL_PWR_GET_FLAG().
+  *         To enter low power mode , and if current regulator voltage is
+  *         Voltage Scale 0 then first switch to Voltage Scale 1 before entering
+  *         low power mode.
+  * @retval None.
+  */
+#if defined(PWR_SRDCR_VOS) /* STM32H7Axxx and STM32H7Bxxx lines */
+#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__)                         \
+do {                                                                           \
+      __IO uint32_t tmpreg = 0x00;                                             \
+      MODIFY_REG(PWR->SRDCR, PWR_SRDCR_VOS, (__REGULATOR__));                  \
+      /* Delay after setting the voltage scaling */                            \
+      tmpreg = READ_BIT(PWR->SRDCR, PWR_SRDCR_VOS);                            \
+      UNUSED(tmpreg);                                                          \
+} while(0)
+#else /* All H7 lines except STM32H7Axxx and STM32H7Bxxx lines */
+#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__)                         \
+do {                                                                           \
+      __IO uint32_t tmpreg = 0x00;                                             \
+      /* Check the voltage scaling to be configured */                         \
+      if((__REGULATOR__) == PWR_REGULATOR_VOLTAGE_SCALE0)                      \
+      {                                                                        \
+        /* Configure the Voltage Scaling 1 */                                  \
+        MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);     \
+        /* Delay after setting the voltage scaling */                          \
+        tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS);                            \
+        /* Enable the PWR overdrive */                                         \
+        SET_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);                             \
+        /* Delay after setting the syscfg boost setting */                     \
+        tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);                   \
+      }                                                                        \
+      else                                                                     \
+      {                                                                        \
+        /* Disable the PWR overdrive */                                        \
+        CLEAR_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);                           \
+        /* Delay after setting the syscfg boost setting */                     \
+        tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);                   \
+        /* Configure the Voltage Scaling x */                                  \
+        MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__));                  \
+        /* Delay after setting the voltage scaling */                          \
+        tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS);                            \
+      }                                                                        \
+      UNUSED(tmpreg);                                                          \
+} while(0)
+#endif /* PWR_SRDCR_VOS */
+
+/** @brief  Check PWR flags are set or not.
+  * @param  __FLAG__ : Specifies the flag to check.
+  *           This parameter can be one of the following values:
+  *            @arg PWR_FLAG_PVDO : PVD Output. This flag is valid only if PVD
+  *                                 is enabled by the HAL_PWR_EnablePVD()
+  *                                 function.
+  *                                 The PVD is stopped by STANDBY mode. For this
+  *                                 reason, this bit is equal to 0 after STANDBY
+  *                                 or reset until the PVDE bit is set.
+  *            @arg PWR_FLAG_AVDO : AVD Output. This flag is valid only if AVD
+  *                                 is enabled by the HAL_PWREx_EnableAVD()
+  *                                 function. The AVD is stopped by STANDBY mode.
+  *                                 For this reason, this bit is equal to 0
+  *                                 after STANDBY or reset until the AVDE bit
+  *                                 is set.
+  *            @arg PWR_FLAG_ACTVOSRDY : This flag indicates that the Regulator
+  *                                      voltage scaling output selection is
+  *                                      ready.
+  *            @arg PWR_FLAG_BRR : Backup regulator ready flag. This bit is not
+  *                                reset when the device wakes up from STANDBY
+  *                                mode or by a system reset or power-on reset.
+  *            @arg PWR_FLAG_VOSRDY : This flag indicates that the Regulator
+  *                                   voltage scaling output selection is ready.
+  *                                mode or by a system reset or power-on reset.
+  *            @arg PWR_FLAG_USB33RDY : This flag indicates that the USB supply
+  *                                     from regulator is ready.
+  *            @arg PWR_FLAG_TEMPH : This flag indicates that the temperature
+  *                                  equal or above high threshold level.
+  *            @arg PWR_FLAG_TEMPL : This flag indicates that the temperature
+  *                                  equal or below low threshold level.
+  *            @arg PWR_FLAG_VBATH : This flag indicates that VBAT level equal
+  *                                  or above high threshold level.
+  *            @arg PWR_FLAG_VBATL : This flag indicates that VBAT level equal
+  *                                  or below low threshold level.
+  *            @arg PWR_FLAG_STOP : This flag indicates that the system entered
+  *                                 in STOP mode.
+  *            @arg PWR_FLAG_SB : This flag indicates that the system entered in
+  *                               STANDBY mode.
+  *            @arg PWR_FLAG_SB_D1 : This flag indicates that the D1 domain
+  *                                  entered in STANDBY mode.
+  *            @arg PWR_FLAG_SB_D2 : This flag indicates that the D2 domain
+  *                                  entered in STANDBY mode.
+  *            @arg PWR_FLAG2_STOP : This flag indicates that the system entered
+  *                                 in STOP mode.
+  *            @arg PWR_FLAG2_SB : This flag indicates that the system entered
+  *                                in STANDBY mode.
+  *            @arg PWR_FLAG2_SB_D1 : This flag indicates that the D1 domain
+  *                                   entered in STANDBY mode.
+  *            @arg PWR_FLAG2_SB_D2 : This flag indicates that the D2 domain
+  *                                   entered in STANDBY mode.
+  *            @arg PWR_FLAG_CPU_HOLD : This flag indicates that the CPU1 wakes
+  *                                     up with hold.
+  *            @arg PWR_FLAG_CPU2_HOLD : This flag indicates that the CPU2 wakes
+  *                                      up with hold.
+  *            @arg PWR_FLAG_SMPSEXTRDY : This flag indicates that the SMPS
+  *                                       External supply is sready.
+  *            @arg PWR_FLAG_SCUEN : This flag indicates that the supply
+  *                                  configuration update is enabled.
+  *            @arg PWR_FLAG_MMCVDO : This flag indicates that the VDDMMC is
+  *                                   above or equal to 1.2 V.
+  * @note   The PWR_FLAG_PVDO, PWR_FLAG_AVDO, PWR_FLAG_ACTVOSRDY, PWR_FLAG_BRR,
+  *         PWR_FLAG_VOSRDY, PWR_FLAG_USB33RDY, PWR_FLAG_TEMPH, PWR_FLAG_TEMPL,
+  *         PWR_FLAG_VBATH, PWR_FLAG_VBATL, PWR_FLAG_STOP and PWR_FLAG_SB flags
+  *         are used for all H7 family lines.
+  *         The PWR_FLAG2_STOP, PWR_FLAG2_SB, PWR_FLAG2_SB_D1, PWR_FLAG2_SB_D2,
+  *         PWR_FLAG_CPU_HOLD and PWR_FLAG_CPU2_HOLD flags are used only for H7
+  *         dual core lines.
+  *         The PWR_FLAG_SB_D1 and PWR_FLAG_SB_D2 flags are used for all H7
+  *         family except STM32H7Axxx and STM32H7Bxxx lines.
+  *         The PWR_FLAG_MMCVDO flag is used only for STM32H7Axxx and
+  *         STM32H7Bxxx lines.
+  *         The PWR_FLAG_SCUEN flag is used for STM32H743, STM32H753, STM32H742,
+  *         STM32H750, STM32H7Axx and STM32H7Bxx lines.
+  *         The PWR_FLAG_SMPSEXTRDY flag is used for dual core and STM32H7AxxQ,
+  *         STM32H7BxxQ lines.
+  * @retval The (__FLAG__) state (TRUE or FALSE).
+  */
+#if defined (DUAL_CORE) /* Dual core lines */
+#define __HAL_PWR_GET_FLAG(__FLAG__)                                                              \
+(((__FLAG__) == PWR_FLAG_PVDO)       ? ((PWR->CSR1 & PWR_CSR1_PVDO)       == PWR_CSR1_PVDO)      :\
+ ((__FLAG__) == PWR_FLAG_AVDO)       ? ((PWR->CSR1 & PWR_CSR1_AVDO)       == PWR_CSR1_AVDO)      :\
+ ((__FLAG__) == PWR_FLAG_ACTVOSRDY)  ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY)  == PWR_CSR1_ACTVOSRDY) :\
+ ((__FLAG__) == PWR_FLAG_VOSRDY)     ? ((PWR->D3CR & PWR_D3CR_VOSRDY)     == PWR_D3CR_VOSRDY)    :\
+ ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_CR3_SMPSEXTRDY)   == PWR_CR3_SMPSEXTRDY) :\
+ ((__FLAG__) == PWR_FLAG_BRR)        ? ((PWR->CR2 & PWR_CR2_BRRDY)        == PWR_CR2_BRRDY)      :\
+ ((__FLAG__) == PWR_FLAG_CPU_HOLD)   ? ((PWR->CPU2CR & PWR_CPU2CR_HOLD1F) == PWR_CPU2CR_HOLD1F)  :\
+ ((__FLAG__) == PWR_FLAG_CPU2_HOLD)  ? ((PWR->CPUCR & PWR_CPUCR_HOLD2F)   == PWR_CPUCR_HOLD2F)   :\
+ ((__FLAG__) == PWR_FLAG_SB)         ? ((PWR->CPUCR & PWR_CPUCR_SBF)      == PWR_CPUCR_SBF)      :\
+ ((__FLAG__) == PWR_FLAG2_SB)        ? ((PWR->CPU2CR & PWR_CPU2CR_SBF)    == PWR_CPU2CR_SBF)     :\
+ ((__FLAG__) == PWR_FLAG_STOP)       ? ((PWR->CPUCR & PWR_CPUCR_STOPF)    == PWR_CPUCR_STOPF)    :\
+ ((__FLAG__) == PWR_FLAG2_STOP)      ? ((PWR->CPU2CR & PWR_CPU2CR_STOPF)  == PWR_CPU2CR_STOPF)   :\
+ ((__FLAG__) == PWR_FLAG_SB_D1)      ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1)   == PWR_CPUCR_SBF_D1)   :\
+ ((__FLAG__) == PWR_FLAG2_SB_D1)     ? ((PWR->CPU2CR & PWR_CPU2CR_SBF_D1) == PWR_CPU2CR_SBF_D1)  :\
+ ((__FLAG__) == PWR_FLAG_SB_D2)      ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2)   == PWR_CPUCR_SBF_D2)   :\
+ ((__FLAG__) == PWR_FLAG2_SB_D2)     ? ((PWR->CPU2CR & PWR_CPU2CR_SBF_D2) == PWR_CPU2CR_SBF_D2)  :\
+ ((__FLAG__) == PWR_FLAG_USB33RDY)   ? ((PWR->CR3 & PWR_CR3_USB33RDY)     == PWR_CR3_USB33RDY)   :\
+ ((__FLAG__) == PWR_FLAG_TEMPH)      ? ((PWR->CR2 & PWR_CR2_TEMPH)        == PWR_CR2_TEMPH)      :\
+ ((__FLAG__) == PWR_FLAG_TEMPL)      ? ((PWR->CR2 & PWR_CR2_TEMPL)        == PWR_CR2_TEMPL)      :\
+ ((__FLAG__) == PWR_FLAG_VBATH)      ? ((PWR->CR2 & PWR_CR2_VBATH)        == PWR_CR2_VBATH)      :\
+ ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
+#else /* Single core lines */
+#if defined (PWR_CPUCR_SBF_D2) /* STM32H743, STM32H753, STM32H742 and STM32H750 lines */
+#define __HAL_PWR_GET_FLAG(__FLAG__)                                                            \
+(((__FLAG__) == PWR_FLAG_PVDO)      ? ((PWR->CSR1 & PWR_CSR1_PVDO)      == PWR_CSR1_PVDO)      :\
+ ((__FLAG__) == PWR_FLAG_AVDO)      ? ((PWR->CSR1 & PWR_CSR1_AVDO)      == PWR_CSR1_AVDO)      :\
+ ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
+ ((__FLAG__) == PWR_FLAG_VOSRDY)    ? ((PWR->D3CR & PWR_D3CR_VOSRDY)    == PWR_D3CR_VOSRDY)    :\
+ ((__FLAG__) == PWR_FLAG_SCUEN)     ? ((PWR->CR3 & PWR_CR3_SCUEN)       == PWR_CR3_SCUEN)      :\
+ ((__FLAG__) == PWR_FLAG_BRR)       ? ((PWR->CR2 & PWR_CR2_BRRDY)       == PWR_CR2_BRRDY)      :\
+ ((__FLAG__) == PWR_FLAG_SB)        ? ((PWR->CPUCR & PWR_CPUCR_SBF)     == PWR_CPUCR_SBF)      :\
+ ((__FLAG__) == PWR_FLAG_STOP)      ? ((PWR->CPUCR & PWR_CPUCR_STOPF)   == PWR_CPUCR_STOPF)    :\
+ ((__FLAG__) == PWR_FLAG_SB_D1)     ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1)  == PWR_CPUCR_SBF_D1)   :\
+ ((__FLAG__) == PWR_FLAG_SB_D2)     ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2)  == PWR_CPUCR_SBF_D2)   :\
+ ((__FLAG__) == PWR_FLAG_USB33RDY)  ? ((PWR->CR3 & PWR_CR3_USB33RDY)    == PWR_CR3_USB33RDY)   :\
+ ((__FLAG__) == PWR_FLAG_TEMPH)     ? ((PWR->CR2 & PWR_CR2_TEMPH)       == PWR_CR2_TEMPH)      :\
+ ((__FLAG__) == PWR_FLAG_TEMPL)     ? ((PWR->CR2 & PWR_CR2_TEMPL)       == PWR_CR2_TEMPL)      :\
+ ((__FLAG__) == PWR_FLAG_VBATH)     ? ((PWR->CR2 & PWR_CR2_VBATH)       == PWR_CR2_VBATH)      :\
+ ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
+#else /* STM32H7Axxx and STM32H7Bxxx lines */
+#if defined (SMPS) /* STM32H7AxxQ and STM32H7BxxQ SMPS lines */
+#define __HAL_PWR_GET_FLAG(__FLAG__)                                                            \
+(((__FLAG__) == PWR_FLAG_PVDO)       ? ((PWR->CSR1 & PWR_CSR1_PVDO)      == PWR_CSR1_PVDO)      :\
+ ((__FLAG__) == PWR_FLAG_AVDO)       ? ((PWR->CSR1 & PWR_CSR1_AVDO)      == PWR_CSR1_AVDO)      :\
+ ((__FLAG__) == PWR_FLAG_ACTVOSRDY)  ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
+ ((__FLAG__) == PWR_FLAG_BRR)        ? ((PWR->CR2 & PWR_CR2_BRRDY)       == PWR_CR2_BRRDY)      :\
+ ((__FLAG__) == PWR_FLAG_VOSRDY)     ? ((PWR->SRDCR & PWR_SRDCR_VOSRDY)  == PWR_SRDCR_VOSRDY)   :\
+ ((__FLAG__) == PWR_FLAG_STOP)       ? ((PWR->CPUCR & PWR_CPUCR_STOPF)   == PWR_CPUCR_STOPF)    :\
+ ((__FLAG__) == PWR_FLAG_SB)         ? ((PWR->CPUCR & PWR_CPUCR_SBF)     == PWR_CPUCR_SBF)      :\
+ ((__FLAG__) == PWR_FLAG_MMCVDO)     ? ((PWR->CSR1 & PWR_CSR1_MMCVDO)    == PWR_CSR1_MMCVDO)    :\
+ ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_CR3_SMPSEXTRDY)  == PWR_CR3_SMPSEXTRDY) :\
+ ((__FLAG__) == PWR_FLAG_USB33RDY)   ? ((PWR->CR3 & PWR_CR3_USB33RDY)    == PWR_CR3_USB33RDY)   :\
+ ((__FLAG__) == PWR_FLAG_TEMPH)      ? ((PWR->CR2 & PWR_CR2_TEMPH)       == PWR_CR2_TEMPH)      :\
+ ((__FLAG__) == PWR_FLAG_TEMPL)      ? ((PWR->CR2 & PWR_CR2_TEMPL)       == PWR_CR2_TEMPL)      :\
+ ((__FLAG__) == PWR_FLAG_VBATH)      ? ((PWR->CR2 & PWR_CR2_VBATH)       == PWR_CR2_VBATH)      :\
+ ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
+#else /* STM32H7Axx and STM32H7Bxx LDO lines */
+#define __HAL_PWR_GET_FLAG(__FLAG__)                                    \
+(((__FLAG__) == PWR_FLAG_PVDO)      ? ((PWR->CSR1 & PWR_CSR1_PVDO)      == PWR_CSR1_PVDO)      :\
+ ((__FLAG__) == PWR_FLAG_AVDO)      ? ((PWR->CSR1 & PWR_CSR1_AVDO)      == PWR_CSR1_AVDO)      :\
+ ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
+ ((__FLAG__) == PWR_FLAG_BRR)       ? ((PWR->CR2 & PWR_CR2_BRRDY)       == PWR_CR2_BRRDY)      :\
+ ((__FLAG__) == PWR_FLAG_VOSRDY)    ? ((PWR->SRDCR & PWR_SRDCR_VOSRDY)  == PWR_SRDCR_VOSRDY)   :\
+ ((__FLAG__) == PWR_FLAG_SCUEN)     ? ((PWR->CR3 & PWR_CR3_SCUEN)       == PWR_CR3_SCUEN)      :\
+ ((__FLAG__) == PWR_FLAG_STOP)      ? ((PWR->CPUCR & PWR_CPUCR_STOPF)   == PWR_CPUCR_STOPF)    :\
+ ((__FLAG__) == PWR_FLAG_SB)        ? ((PWR->CPUCR & PWR_CPUCR_SBF)     == PWR_CPUCR_SBF)      :\
+ ((__FLAG__) == PWR_FLAG_MMCVDO)    ? ((PWR->CSR1 & PWR_CSR1_MMCVDO)    == PWR_CSR1_MMCVDO)    :\
+ ((__FLAG__) == PWR_FLAG_USB33RDY)  ? ((PWR->CR3 & PWR_CR3_USB33RDY)    == PWR_CR3_USB33RDY)   :\
+ ((__FLAG__) == PWR_FLAG_TEMPH)     ? ((PWR->CR2 & PWR_CR2_TEMPH)       == PWR_CR2_TEMPH)      :\
+ ((__FLAG__) == PWR_FLAG_TEMPL)     ? ((PWR->CR2 & PWR_CR2_TEMPL)       == PWR_CR2_TEMPL)      :\
+ ((__FLAG__) == PWR_FLAG_VBATH)     ? ((PWR->CR2 & PWR_CR2_VBATH)       == PWR_CR2_VBATH)      :\
+ ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
+#endif /* SMPS */
+#endif /* PWR_CPUCR_SBF_D2 */
+#endif /* DUAL_CORE */
+
+/** @brief  Check PWR wake up flags are set or not.
+  * @param  __FLAG__: specifies the wake up flag to check.
+  *           This parameter can be one of the following values:
+  *            @arg PWR_FLAG_WKUP1 : This parameter clear Wake up line 1 flag.
+  *            @arg PWR_FLAG_WKUP2 : This parameter clear Wake up line 2 flag.
+  *            @arg PWR_FLAG_WKUP3 : This parameter clear Wake up line 3 flag.
+  *            @arg PWR_FLAG_WKUP4 : This parameter clear Wake up line 4 flag.
+  *            @arg PWR_FLAG_WKUP5 : This parameter clear Wake up line 5 flag.
+  *            @arg PWR_FLAG_WKUP6 : This parameter clear Wake up line 6 flag.
+  * @retval The (__FLAG__) state (TRUE or FALSE).
+  */
+#define __HAL_PWR_GET_WAKEUPFLAG(__FLAG__) ((PWR->WKUPFR & (__FLAG__)) ? 0 : 1)
+
+#if defined (DUAL_CORE)
+/** @brief  Clear CPU PWR flags.
+  * @param  __FLAG__ : Specifies the flag to clear.
+  * @note   This parameter is not used for the STM32H7 family and is kept as
+  *         parameter just to maintain compatibility with other families.
+  * @note   This macro clear all CPU flags STOPF, SBF, SBF_D1, and SBF_D2.
+  *           This parameter can be one of the following values :
+  *            @arg PWR_CPU_FLAGS : Clear HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2
+  *                                 CPU flags.
+  * @retval None.
+  */
+#define __HAL_PWR_CLEAR_FLAG(__FLAG__)      \
+do {                                        \
+     SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF);   \
+     SET_BIT(PWR->CPU2CR, PWR_CPU2CR_CSSF); \
+} while(0)
+#else
+/** @brief  Clear CPU PWR flags.
+  * @param  __FLAG__ : Specifies the flag to clear.
+  * @note   This parameter is not used for the STM32H7 family and is kept as
+  *         parameter just to maintain compatibility with other families.
+  * @note   This macro clear all CPU flags.
+  *         For STM32H7Axxx and STM32H7Bxxx lines CPU flags are STOPF and SBF.
+  *         For dual core lines flags are HOLDxF, STOPF, SBF and SBF_Dx.
+  * @retval None.
+  */
+#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF)
+#endif /* defined (DUAL_CORE) */
+
+/** @brief  Clear PWR wake up flags.
+  * @param  __FLAG__ : Specifies the wake up flag to be cleared.
+  *           This parameter can be one of the following values :
+  *            @arg PWR_FLAG_WKUP1 : This parameter clear Wake up line 1 flag.
+  *            @arg PWR_FLAG_WKUP2 : This parameter clear Wake up line 2 flag.
+  *            @arg PWR_FLAG_WKUP3 : This parameter clear Wake up line 3 flag.
+  *            @arg PWR_FLAG_WKUP4 : This parameter clear Wake up line 4 flag.
+  *            @arg PWR_FLAG_WKUP5 : This parameter clear Wake up line 5 flag.
+  *            @arg PWR_FLAG_WKUP6 : This parameter clear Wake up line 6 flag.
+  * @retval None.
+  */
+#define __HAL_PWR_CLEAR_WAKEUPFLAG(__FLAG__) SET_BIT(PWR->WKUPCR, (__FLAG__))
+
+/**
+  * @brief Enable the PVD EXTI Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Enable the PVD EXTI D2 Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief Disable the PVD EXTI Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Disable the PVD EXTI D2 Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief   Enable event on PVD EXTI Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Enable event on PVD EXTI D2 Line.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief   Disable event on PVD EXTI Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Disable event on PVD EXTI D2 Line.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief Enable the PVD Rising Interrupt Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Disable the PVD Rising Interrupt Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Enable the PVD Falling Interrupt Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Disable the PVD Falling Interrupt Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Enable the PVD Rising & Falling Interrupt Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
+do {                                                    \
+      __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();          \
+      __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();         \
+} while(0);
+
+/**
+  * @brief Disable the PVD Rising & Falling Interrupt Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
+do {                                                     \
+      __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();          \
+      __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();         \
+} while(0);
+
+/**
+  * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
+  * @retval EXTI PVD Line Status.
+  */
+#define __HAL_PWR_PVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Checks whether the specified PVD EXTI interrupt flag is set or not.
+  * @retval EXTI D2 PVD Line Status.
+  */
+#define __HAL_PWR_PVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief Clear the PVD EXTI flag.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Clear the PVD EXTI D2 flag.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief  Generates a Software interrupt on PVD EXTI line.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
+/**
+  * @}
+  */
+
+/* Include PWR HAL Extension module */
+#include "stm32h7xx_hal_pwr_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PWR_Exported_Functions PWR Exported Functions
+  * @{
+  */
+
+/** @addtogroup PWR_Exported_Functions_Group1 Initialization and De-Initialization functions
+  * @{
+  */
+/* Initialization and de-initialization functions *****************************/
+void HAL_PWR_DeInit(void);
+void HAL_PWR_EnableBkUpAccess(void);
+void HAL_PWR_DisableBkUpAccess(void);
+/**
+  * @}
+  */
+
+/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
+  * @{
+  */
+/* Peripheral Control functions  **********************************************/
+/* PVD configuration */
+void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
+void HAL_PWR_EnablePVD(void);
+void HAL_PWR_DisablePVD(void);
+
+/* WakeUp pins configuration */
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
+
+/* Low Power modes entry */
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
+void HAL_PWR_EnterSTANDBYMode(void);
+
+/* Power PVD IRQ Handler */
+void HAL_PWR_PVD_IRQHandler(void);
+void HAL_PWR_PVDCallback(void);
+
+/* Cortex System Control functions  *******************************************/
+void HAL_PWR_EnableSleepOnExit(void);
+void HAL_PWR_DisableSleepOnExit(void);
+void HAL_PWR_EnableSEVOnPend(void);
+void HAL_PWR_DisableSEVOnPend(void);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup PWR_Private_Constants PWR Private Constants
+  * @{
+  */
+
+/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line
+  * @{
+  */
+#define PWR_EXTI_LINE_PVD  EXTI_IMR1_IM16 /*!< External interrupt line 16
+                                               Connected to the PVD EXTI Line */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PWR_Private_Macros PWR Private Macros
+  * @{
+  */
+
+/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters
+  * @{
+  */
+/* Check PVD level parameter */
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) ||\
+                                 ((LEVEL) == PWR_PVDLEVEL_1) ||\
+                                 ((LEVEL) == PWR_PVDLEVEL_2) ||\
+                                 ((LEVEL) == PWR_PVDLEVEL_3) ||\
+                                 ((LEVEL) == PWR_PVDLEVEL_4) ||\
+                                 ((LEVEL) == PWR_PVDLEVEL_5) ||\
+                                 ((LEVEL) == PWR_PVDLEVEL_6) ||\
+                                 ((LEVEL) == PWR_PVDLEVEL_7))
+
+/* Check PVD mode parameter */
+#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)            ||\
+                               ((MODE) == PWR_PVD_MODE_IT_FALLING)           ||\
+                               ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING)    ||\
+                               ((MODE) == PWR_PVD_MODE_EVENT_RISING)         ||\
+                               ((MODE) == PWR_PVD_MODE_EVENT_FALLING)        ||\
+                               ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) ||\
+                               ((MODE) == PWR_PVD_MODE_NORMAL))
+
+/* Check low power regulator parameter */
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON)   ||\
+                                     ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
+
+/* Check low power mode entry parameter */
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) ||\
+                                   ((ENTRY) == PWR_SLEEPENTRY_WFE))
+
+/* Check low power mode entry parameter */
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) ||\
+                                  ((ENTRY) == PWR_STOPENTRY_WFE))
+
+/* Check voltage scale level parameter */
+#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE0) || \
+                                           ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
+                                           ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
+                                           ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* STM32H7xx_HAL_PWR_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h
new file mode 100644
index 00000000..ebad73c5
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h
@@ -0,0 +1,743 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_pwr_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of PWR HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_PWR_EX_H
+#define STM32H7xx_HAL_PWR_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup PWREx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup PWREx_Exported_Types PWREx Exported Types
+  * @{
+  */
+/**
+  * @brief  PWREx AVD configuration structure definition
+  */
+typedef struct
+{
+  uint32_t AVDLevel; /*!< AVDLevel : Specifies the AVD detection level. This
+                          parameter can be a value of @ref
+                          PWREx_AVD_detection_level
+                     */
+
+  uint32_t Mode;     /*!< Mode : Specifies the EXTI operating mode for the AVD
+                                 event. This parameter can be a value of @ref
+                                 PWREx_AVD_Mode.
+                     */
+}PWREx_AVDTypeDef;
+
+/**
+  * @brief  PWREx Wakeup pin configuration structure definition
+  */
+typedef struct
+{
+  uint32_t WakeUpPin;   /*!< WakeUpPin: Specifies the Wake-Up pin to be enabled.
+                                        This parameter can be a value of @ref
+                                        PWREx_WakeUp_Pins
+                        */
+
+  uint32_t PinPolarity; /*!< PinPolarity: Specifies the Wake-Up pin polarity.
+                                          This parameter can be a value of @ref
+                                          PWREx_PIN_Polarity
+                        */
+
+  uint32_t PinPull;     /*!< PinPull: Specifies the Wake-Up pin pull. This
+                                      parameter can be a value of @ref
+                                      PWREx_PIN_Pull
+                        */
+}PWREx_WakeupPinTypeDef;
+
+#if defined (PWR_CSR1_MMCVDO)
+/**
+  * @brief  PWR VDDMMC voltage level enum definition
+  */
+typedef enum
+{
+  PWR_MMC_VOLTAGE_BELOW_1V2,      /*!< VDDMMC is below 1V2          */
+  PWR_MMC_VOLTAGE_EQUAL_ABOVE_1V2 /*!< VDDMMC is above or equal 1V2 */
+} PWREx_MMC_VoltageLevel;
+#endif /* defined (PWR_CSR1_MMCVDO) */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PWREx_Exported_Constants PWREx Exported Constants
+  * @{
+  */
+/** @defgroup PWREx_WakeUp_Pins PWREx Wake-Up Pins
+  * @{
+  */
+/* High level and No pull (default configuration) */
+#define PWR_WAKEUP_PIN6      PWR_WKUPEPR_WKUPEN6
+#define PWR_WAKEUP_PIN5      PWR_WKUPEPR_WKUPEN5
+#define PWR_WAKEUP_PIN4      PWR_WKUPEPR_WKUPEN4
+#define PWR_WAKEUP_PIN3      PWR_WKUPEPR_WKUPEN3
+#define PWR_WAKEUP_PIN2      PWR_WKUPEPR_WKUPEN2
+#define PWR_WAKEUP_PIN1      PWR_WKUPEPR_WKUPEN1
+
+/* High level and No pull */
+#define PWR_WAKEUP_PIN6_HIGH PWR_WKUPEPR_WKUPEN6
+#define PWR_WAKEUP_PIN5_HIGH PWR_WKUPEPR_WKUPEN5
+#define PWR_WAKEUP_PIN4_HIGH PWR_WKUPEPR_WKUPEN4
+#define PWR_WAKEUP_PIN3_HIGH PWR_WKUPEPR_WKUPEN3
+#define PWR_WAKEUP_PIN2_HIGH PWR_WKUPEPR_WKUPEN2
+#define PWR_WAKEUP_PIN1_HIGH PWR_WKUPEPR_WKUPEN1
+
+/* Low level and No pull */
+#define PWR_WAKEUP_PIN6_LOW  (PWR_WKUPEPR_WKUPP6 | PWR_WKUPEPR_WKUPEN6)
+#define PWR_WAKEUP_PIN5_LOW  (PWR_WKUPEPR_WKUPP5 | PWR_WKUPEPR_WKUPEN5)
+#define PWR_WAKEUP_PIN4_LOW  (PWR_WKUPEPR_WKUPP4 | PWR_WKUPEPR_WKUPEN4)
+#define PWR_WAKEUP_PIN3_LOW  (PWR_WKUPEPR_WKUPP3 | PWR_WKUPEPR_WKUPEN3)
+#define PWR_WAKEUP_PIN2_LOW  (PWR_WKUPEPR_WKUPP2 | PWR_WKUPEPR_WKUPEN2)
+#define PWR_WAKEUP_PIN1_LOW  (PWR_WKUPEPR_WKUPP1 | PWR_WKUPEPR_WKUPEN1)
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_PIN_Polarity PWREx Pin Polarity configuration
+  * @{
+  */
+#define PWR_PIN_POLARITY_HIGH (0x00000000U)
+#define PWR_PIN_POLARITY_LOW  (0x00000001U)
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_PIN_Pull PWREx Pin Pull configuration
+  * @{
+  */
+#define PWR_PIN_NO_PULL   (0x00000000U)
+#define PWR_PIN_PULL_UP   (0x00000001U)
+#define PWR_PIN_PULL_DOWN (0x00000002U)
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_Wakeup_Pins_Flags PWREx Wakeup Pins Flags.
+  * @{
+  */
+#define PWR_WAKEUP_FLAG1 PWR_WKUPFR_WKUPF1 /*!< Wakeup flag on PA0  */
+#define PWR_WAKEUP_FLAG2 PWR_WKUPFR_WKUPF2 /*!< Wakeup flag on PA2  */
+#define PWR_WAKEUP_FLAG3 PWR_WKUPFR_WKUPF3 /*!< Wakeup flag on PI8  */
+#define PWR_WAKEUP_FLAG4 PWR_WKUPFR_WKUPF4 /*!< Wakeup flag on PC13 */
+#define PWR_WAKEUP_FLAG5 PWR_WKUPFR_WKUPF5 /*!< Wakeup flag on PI11 */
+#define PWR_WAKEUP_FLAG6 PWR_WKUPFR_WKUPF6 /*!< Wakeup flag on PC1  */
+#define PWR_WAKEUP_FLAG_ALL (PWR_WKUPFR_WKUPF1 | PWR_WKUPFR_WKUPF2 |\
+                             PWR_WKUPFR_WKUPF3 | PWR_WKUPFR_WKUPF4 |\
+                             PWR_WKUPFR_WKUPF5 | PWR_WKUPFR_WKUPF6)
+/**
+  * @}
+  */
+
+#if defined (DUAL_CORE)
+/** @defgroup PWREx_Core_Select PWREx Core definition
+  * @{
+  */
+#define PWR_CORE_CPU1 (0x00000000U)
+#define PWR_CORE_CPU2 (0x00000001U)
+/**
+  * @}
+  */
+#endif /* defined (DUAL_CORE) */
+
+/** @defgroup PWREx_Domains PWREx Domains definition
+  * @{
+  */
+#define PWR_D1_DOMAIN (0x00000000U)
+#if defined (PWR_CPUCR_PDDS_D2)
+#define PWR_D2_DOMAIN (0x00000001U)
+#endif /* defined (PWR_CPUCR_PDDS_D2) */
+#define PWR_D3_DOMAIN (0x00000002U)
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_Domain_Flags PWREx Domain Flags definition
+  * @{
+  */
+#if defined (DUAL_CORE)
+#define PWR_D1_DOMAIN_FLAGS  (0x00000000U)
+#define PWR_D2_DOMAIN_FLAGS  (0x00000001U)
+#define PWR_ALL_DOMAIN_FLAGS (0x00000002U)
+#else
+#define PWR_CPU_FLAGS       (0x00000000U)
+#endif /* defined (DUAL_CORE) */
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_D3_State PWREx D3 Domain State
+  * @{
+  */
+#define PWR_D3_DOMAIN_STOP (0x00000000U)
+#define PWR_D3_DOMAIN_RUN  (0x00000800U)
+
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_Supply_configuration PWREx Supply configuration
+  * @{
+  */
+#define PWR_LDO_SUPPLY                      PWR_CR3_LDOEN                                                               /*!< Core domains are suppplied from the LDO                                                                     */
+#if defined (SMPS)
+#define PWR_DIRECT_SMPS_SUPPLY              PWR_CR3_SMPSEN                                                              /*!< Core domains are suppplied from the SMPS only                                                               */
+#define PWR_SMPS_1V8_SUPPLIES_LDO           (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN    | PWR_CR3_LDOEN)                   /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains                                       */
+#define PWR_SMPS_2V5_SUPPLIES_LDO           (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN    | PWR_CR3_LDOEN)                   /*!< The SMPS 2.5V output supplies the LDO which supplies the Core domains                                       */
+#define PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO   (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)  /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */
+#define PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO   (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)  /*!< The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */
+#define PWR_SMPS_1V8_SUPPLIES_EXT           (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 1.8V output supplies an external source which supplies the Core domains                            */
+#define PWR_SMPS_2V5_SUPPLIES_EXT           (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 2.5V output supplies an external source which supplies the Core domains                            */
+#endif /* defined (SMPS) */
+#define PWR_EXTERNAL_SOURCE_SUPPLY          PWR_CR3_BYPASS                                                              /*!< The SMPS disabled and the LDO Bypass. The Core domains are supplied from an external source                 */
+
+#if defined (SMPS)
+#define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | \
+                                PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)
+#else
+#define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)
+#endif /* defined (SMPS) */
+/**
+  * @}
+  */
+
+
+/** @defgroup PWREx_AVD_detection_level PWREx AVD detection level
+  * @{
+  */
+#define PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0 /*!< Analog voltage detector level 0
+                                             selection : 1V7                 */
+#define PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1 /*!< Analog voltage detector level 1
+                                             selection : 2V1                 */
+#define PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2 /*!< Analog voltage detector level 2
+                                             selection : 2V5                 */
+#define PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3 /*!< Analog voltage detector level 3
+                                             selection : 2V8                 */
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_AVD_Mode PWREx AVD Mode
+  * @{
+  */
+#define PWR_AVD_MODE_NORMAL               (0x00000000U)   /*!< Basic mode is used                                                 */
+#define PWR_AVD_MODE_IT_RISING            (0x00010001U)   /*!< External Interrupt Mode with Rising edge trigger detection         */
+#define PWR_AVD_MODE_IT_FALLING           (0x00010002U)   /*!< External Interrupt Mode with Falling edge trigger detection        */
+#define PWR_AVD_MODE_IT_RISING_FALLING    (0x00010003U)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define PWR_AVD_MODE_EVENT_RISING         (0x00020001U)   /*!< Event Mode with Rising edge trigger detection                      */
+#define PWR_AVD_MODE_EVENT_FALLING        (0x00020002U)   /*!< Event Mode with Falling edge trigger detection                     */
+#define PWR_AVD_MODE_EVENT_RISING_FALLING (0x00020003U)   /*!< Event Mode with Rising/Falling edge trigger detection              */
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale
+  * @{
+  */
+#define PWR_REGULATOR_SVOS_SCALE5 (PWR_CR1_SVOS_0)
+#define PWR_REGULATOR_SVOS_SCALE4 (PWR_CR1_SVOS_1)
+#define PWR_REGULATOR_SVOS_SCALE3 (PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1)
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_VBAT_Battery_Charging_Resistor PWR battery charging resistor selection
+  * @{
+  */
+#define PWR_BATTERY_CHARGING_RESISTOR_5    (0x00000000U) /*!< VBAT charging through a 5 kOhms resistor   */
+#define PWR_BATTERY_CHARGING_RESISTOR_1_5  PWR_CR3_VBRS  /*!< VBAT charging through a 1.5 kOhms resistor */
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_VBAT_Thresholds PWREx VBAT Thresholds
+  * @{
+  */
+#define PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD  (0x00000000U)
+#define PWR_VBAT_BELOW_LOW_THRESHOLD         PWR_CR2_VBATL
+#define PWR_VBAT_ABOVE_HIGH_THRESHOLD        PWR_CR2_VBATH
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_TEMP_Thresholds PWREx Temperature Thresholds
+  * @{
+  */
+#define PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD  (0x00000000U)
+#define PWR_TEMP_BELOW_LOW_THRESHOLD         PWR_CR2_TEMPL
+#define PWR_TEMP_ABOVE_HIGH_THRESHOLD        PWR_CR2_TEMPH
+/**
+  * @}
+  */
+/** @defgroup PWREx_AVD_EXTI_Line PWREx AVD EXTI Line 16
+  * @{
+  */
+#define PWR_EXTI_LINE_AVD EXTI_IMR1_IM16 /*!< External interrupt line 16
+                                              Connected to the AVD EXTI Line */
+/**
+  * @}
+  */
+
+#if defined (PWR_CR1_SRDRAMSO)
+/** @defgroup PWREx_Memory_Shut_Off Memory shut-off block selection
+  * @{
+  */
+#define PWR_SRD_AHB_MEMORY_BLOCK        PWR_CR1_SRDRAMSO    /*!< SmartRun domain AHB memory shut-off in DStop/DStop2 low-power mode         */
+#define PWR_USB_FDCAN_MEMORY_BLOCK      PWR_CR1_HSITFSO     /*!< High-speed interfaces USB and FDCAN memories shut-off in DStop/DStop2 mode */
+#define PWR_GFXMMU_JPEG_MEMORY_BLOCK    PWR_CR1_GFXSO       /*!< GFXMMU and JPEG memories shut-off in DStop/DStop2 mode                     */
+#define PWR_TCM_ECM_MEMORY_BLOCK        PWR_CR1_ITCMSO      /*!< Instruction TCM and ETM memories shut-off in DStop/DStop2 mode             */
+#define PWR_RAM1_AHB_MEMORY_BLOCK       PWR_CR1_AHBRAM1SO   /*!< AHB RAM1 shut-off in DStop/DStop2 mode                                     */
+#define PWR_RAM2_AHB_MEMORY_BLOCK       PWR_CR1_AHBRAM2SO   /*!< AHB RAM2 shut-off in DStop/DStop2 mode                                     */
+#define PWR_RAM1_AXI_MEMORY_BLOCK       PWR_CR1_AXIRAM1SO   /*!< AXI RAM1 shut-off in DStop/DStop2 mode                                     */
+#define PWR_RAM2_AXI_MEMORY_BLOCK       PWR_CR1_AXIRAM2SO   /*!< AXI RAM2 shut-off in DStop/DStop2 mode                                     */
+#define PWR_RAM3_AXI_MEMORY_BLOCK       PWR_CR1_AXIRAM3SO   /*!< AXI RAM3 shut-off in DStop/DStop2 mode                                     */
+#define PWR_MEMORY_BLOCK_KEEP_ON        0U                  /*!< Memory content is kept in DStop or DStop2 mode                             */
+#define PWR_MEMORY_BLOCK_SHUT_OFF       1U                  /*!< Memory content is lost in DStop or DStop2 mode                             */
+/**
+  * @}
+  */
+#endif /* defined (PWR_CR1_SRDRAMSO) */
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup PWREx_Exported_Macro PWREx Exported Macro
+  *  @{
+  */
+
+/**
+  * @brief Enable the AVD EXTI Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Enable the AVD EXTI D2 Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief Disable the AVD EXTI Line 16
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Disable the AVD EXTI D2 Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief Enable event on AVD EXTI Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Enable event on AVD EXTI D2 Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief Disable event on AVD EXTI Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Disable event on AVD EXTI D2 Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief Enable the AVD Extended Interrupt Rising Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)
+
+/**
+  * @brief Disable the AVD Extended Interrupt Rising Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)
+
+/**
+  * @brief Enable the AVD Extended Interrupt Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)
+
+/**
+  * @brief Disable the AVD Extended Interrupt Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)
+
+/**
+  * @brief Enable the AVD Extended Interrupt Rising and Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
+do {                                                    \
+     __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE();           \
+     __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE();          \
+} while(0);
+
+/**
+  * @brief Disable the AVD Extended Interrupt Rising & Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
+do {                                                     \
+     __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE();           \
+     __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE();          \
+} while(0);
+
+/**
+  * @brief Check whether the specified AVD EXTI interrupt flag is set or not.
+  * @retval EXTI AVD Line Status.
+  */
+#define __HAL_PWR_AVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? 1UL : 0UL)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Check whether the specified AVD EXTI D2 interrupt flag is set or not.
+  * @retval EXTI D2 AVD Line Status.
+  */
+#define __HAL_PWR_AVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? 1UL : 0UL)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief  Clear the AVD EXTI flag.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Clear the AVD EXTI D2 flag.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief  Generates a Software interrupt on AVD EXTI line.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_AVD)
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions
+  * @{
+  */
+
+/** @addtogroup PWREx_Exported_Functions_Group1 Power Supply Control Functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource);
+uint32_t HAL_PWREx_GetSupplyConfig(void);
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
+uint32_t HAL_PWREx_GetVoltageRange(void);
+HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling(uint32_t VoltageScaling);
+uint32_t HAL_PWREx_GetStopModeVoltageRange(void);
+/**
+  * @}
+  */
+
+/** @addtogroup PWREx_Exported_Functions_Group2 Low Power Control Functions
+  * @{
+  */
+/* System low power control functions */
+#if defined (PWR_CPUCR_RETDS_CD)
+void HAL_PWREx_EnterSTOP2Mode(uint32_t Regulator, uint8_t STOPEntry);
+#endif /* defined (PWR_CPUCR_RETDS_CD) */
+void HAL_PWREx_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain);
+void HAL_PWREx_EnterSTANDBYMode(uint32_t Domain);
+void HAL_PWREx_ConfigD3Domain(uint32_t D3State);
+/* Clear Cortex-Mx pending flag */
+void HAL_PWREx_ClearPendingEvent(void);
+#if defined (DUAL_CORE)
+/* Clear domain flags */
+void HAL_PWREx_ClearDomainFlags(uint32_t DomainFlags);
+/* Core Hold/Release functions */
+HAL_StatusTypeDef HAL_PWREx_HoldCore(uint32_t CPU);
+void HAL_PWREx_ReleaseCore(uint32_t CPU);
+#endif /* defined (DUAL_CORE) */
+/* Flash low power control functions */
+void HAL_PWREx_EnableFlashPowerDown(void);
+void HAL_PWREx_DisableFlashPowerDown(void);
+#if defined (PWR_CR1_SRDRAMSO)
+/* Memory shut-off functions */
+void HAL_PWREx_EnableMemoryShutOff(uint32_t MemoryBlock);
+void HAL_PWREx_DisableMemoryShutOff(uint32_t MemoryBlock);
+#endif /* defined(PWR_CR1_SRDRAMSO) */
+/* Wakeup Pins control functions */
+void HAL_PWREx_EnableWakeUpPin(PWREx_WakeupPinTypeDef *sPinParams);
+void HAL_PWREx_DisableWakeUpPin(uint32_t WakeUpPin);
+uint32_t HAL_PWREx_GetWakeupFlag(uint32_t WakeUpFlag);
+HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag(uint32_t WakeUpFlag);
+/* Power Wakeup PIN IRQ Handler */
+void HAL_PWREx_WAKEUP_PIN_IRQHandler(void);
+void HAL_PWREx_WKUP1_Callback(void);
+void HAL_PWREx_WKUP2_Callback(void);
+void HAL_PWREx_WKUP3_Callback(void);
+void HAL_PWREx_WKUP4_Callback(void);
+void HAL_PWREx_WKUP5_Callback(void);
+void HAL_PWREx_WKUP6_Callback(void);
+/**
+  * @}
+  */
+
+/** @addtogroup PWREx_Exported_Functions_Group3 Peripherals Control Functions
+  * @{
+  */
+/* Backup regulator control functions */
+HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);
+HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void);
+/* USB regulator control functions */
+HAL_StatusTypeDef HAL_PWREx_EnableUSBReg(void);
+HAL_StatusTypeDef HAL_PWREx_DisableUSBReg(void);
+void HAL_PWREx_EnableUSBVoltageDetector(void);
+void HAL_PWREx_DisableUSBVoltageDetector(void);
+/* Battery control functions */
+void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorValue);
+void HAL_PWREx_DisableBatteryCharging(void);
+#if defined(PWR_CR1_BOOSTE)
+/* Analog Booster functions */
+void HAL_PWREx_EnableAnalogBooster(void);
+void HAL_PWREx_DisableAnalogBooster(void);
+#endif /* PWR_CR1_BOOSTE */
+/**
+  * @}
+  */
+
+/** @addtogroup PWREx_Exported_Functions_Group4 Power Monitoring functions
+  * @{
+  */
+/* Power VBAT/Temperature monitoring functions */
+void HAL_PWREx_EnableMonitoring(void);
+void HAL_PWREx_DisableMonitoring(void);
+uint32_t HAL_PWREx_GetTemperatureLevel(void);
+uint32_t HAL_PWREx_GetVBATLevel(void);
+#if defined(PWR_CSR1_MMCVDO)
+PWREx_MMC_VoltageLevel HAL_PWREx_GetMMCVoltage(void);
+#endif /* PWR_CSR1_MMCVDO */
+/* Power AVD configuration functions */
+void HAL_PWREx_ConfigAVD(PWREx_AVDTypeDef *sConfigAVD);
+void HAL_PWREx_EnableAVD(void);
+void HAL_PWREx_DisableAVD(void);
+/* Power PVD/AVD IRQ Handler */
+void HAL_PWREx_PVD_AVD_IRQHandler(void);
+void HAL_PWREx_AVDCallback(void);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PWREx_Private_Macros PWREx Private Macros
+  * @{
+  */
+
+/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters
+  * @{
+  */
+/* Check PWR regulator configuration parameter */
+#if defined (SMPS)
+#define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY)                    ||\
+                                   ((PWR_SOURCE) == PWR_DIRECT_SMPS_SUPPLY)            ||\
+                                   ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_LDO)         ||\
+                                   ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_LDO)         ||\
+                                   ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) ||\
+                                   ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) ||\
+                                   ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT)         ||\
+                                   ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT)         ||\
+                                   ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY))
+
+#else
+#define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) ||\
+                                   ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY))
+#endif /* defined (SMPS) */
+
+/* Check PWR regulator configuration in STOP mode parameter */
+#define IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE3)  ||\
+                                                     ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE4)  ||\
+                                                     ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE5))
+
+/* Check PWR domain parameter */
+#if defined (PWR_CPUCR_PDDS_D2)
+#define IS_PWR_DOMAIN(DOMAIN) (((DOMAIN) == PWR_D1_DOMAIN) ||\
+                               ((DOMAIN) == PWR_D2_DOMAIN) ||\
+                               ((DOMAIN) == PWR_D3_DOMAIN))
+#else
+#define IS_PWR_DOMAIN(DOMAIN) (((DOMAIN) == PWR_D1_DOMAIN) ||\
+                               ((DOMAIN) == PWR_D3_DOMAIN))
+#endif /* defined (PWR_CPUCR_PDDS_D2) */
+
+/* Check D3/SRD domain state parameter */
+#define IS_D3_STATE(STATE) (((STATE) == PWR_D3_DOMAIN_STOP) ||\
+                            ((STATE) == PWR_D3_DOMAIN_RUN))
+
+/* Check wake up pin parameter */
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1)      ||\
+                                ((PIN) == PWR_WAKEUP_PIN2)      ||\
+                                ((PIN) == PWR_WAKEUP_PIN3)      ||\
+                                ((PIN) == PWR_WAKEUP_PIN4)      ||\
+                                ((PIN) == PWR_WAKEUP_PIN5)      ||\
+                                ((PIN) == PWR_WAKEUP_PIN6)      ||\
+                                ((PIN) == PWR_WAKEUP_PIN1_HIGH) ||\
+                                ((PIN) == PWR_WAKEUP_PIN2_HIGH) ||\
+                                ((PIN) == PWR_WAKEUP_PIN3_HIGH) ||\
+                                ((PIN) == PWR_WAKEUP_PIN4_HIGH) ||\
+                                ((PIN) == PWR_WAKEUP_PIN5_HIGH) ||\
+                                ((PIN) == PWR_WAKEUP_PIN6_HIGH) ||\
+                                ((PIN) == PWR_WAKEUP_PIN1_LOW)  ||\
+                                ((PIN) == PWR_WAKEUP_PIN2_LOW)  ||\
+                                ((PIN) == PWR_WAKEUP_PIN3_LOW)  ||\
+                                ((PIN) == PWR_WAKEUP_PIN4_LOW)  ||\
+                                ((PIN) == PWR_WAKEUP_PIN5_LOW)  ||\
+                                ((PIN) == PWR_WAKEUP_PIN6_LOW))
+
+/* Check wake up pin polarity parameter */
+#define IS_PWR_WAKEUP_PIN_POLARITY(POLARITY) (((POLARITY) == PWR_PIN_POLARITY_HIGH) ||\
+                                              ((POLARITY) == PWR_PIN_POLARITY_LOW))
+
+/* Check wake up pin pull configuration parameter */
+#define IS_PWR_WAKEUP_PIN_PULL(PULL) (((PULL) == PWR_PIN_NO_PULL) ||\
+                                      ((PULL) == PWR_PIN_PULL_UP) ||\
+                                      ((PULL) == PWR_PIN_PULL_DOWN))
+
+/* Check wake up flag parameter */
+#define IS_PWR_WAKEUP_FLAG(FLAG) (((FLAG) == PWR_WAKEUP_FLAG1) ||\
+                                  ((FLAG) == PWR_WAKEUP_FLAG2) ||\
+                                  ((FLAG) == PWR_WAKEUP_FLAG3) ||\
+                                  ((FLAG) == PWR_WAKEUP_FLAG4) ||\
+                                  ((FLAG) == PWR_WAKEUP_FLAG5) ||\
+                                  ((FLAG) == PWR_WAKEUP_FLAG6) ||\
+                                  ((FLAG) == PWR_WAKEUP_FLAG_ALL))
+
+/* Check wake up flag parameter */
+#define IS_PWR_AVD_LEVEL(LEVEL) (((LEVEL) == PWR_AVDLEVEL_0) ||\
+                                 ((LEVEL) == PWR_AVDLEVEL_1) ||\
+                                 ((LEVEL) == PWR_AVDLEVEL_2) ||\
+                                 ((LEVEL) == PWR_AVDLEVEL_3))
+
+/* Check AVD mode parameter */
+#define IS_PWR_AVD_MODE(MODE) (((MODE) == PWR_AVD_MODE_IT_RISING)         ||\
+                               ((MODE) == PWR_AVD_MODE_IT_FALLING)        ||\
+                               ((MODE) == PWR_AVD_MODE_IT_RISING_FALLING) ||\
+                               ((MODE) == PWR_AVD_MODE_EVENT_RISING)      ||\
+                               ((MODE) == PWR_AVD_MODE_EVENT_FALLING)     ||\
+                               ((MODE) == PWR_AVD_MODE_NORMAL)            ||\
+                               ((MODE) == PWR_AVD_MODE_EVENT_RISING_FALLING))
+
+/* Check resistor battery parameter */
+#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
+                                                  ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
+/* Check D1/CD CPU ID parameter */
+#define IS_PWR_D1_CPU(CPU) ((CPU) == CM7_CPUID)
+
+#if defined (DUAL_CORE)
+/* Check CPU parameter */
+#define IS_PWR_CORE(CPU)  (((CPU) == PWR_CORE_CPU1) || ((CPU) == PWR_CORE_CPU2))
+
+/* Check D2 CPU ID parameter */
+#define IS_PWR_D2_CPU(CPU) ((CPU) == CM4_CPUID)
+
+/* Check PWR domain flag parameter */
+#define IS_PWR_DOMAIN_FLAG(FLAG)  (((FLAG) == PWR_D1_DOMAIN_FLAGS) || \
+                                   ((FLAG) == PWR_D2_DOMAIN_FLAGS) || \
+                                   ((FLAG) == PWR_ALL_DOMAIN_FLAGS))
+#endif /* defined (DUAL_CORE) */
+
+#if defined (PWR_CR1_SRDRAMSO)
+/* Check memory block parameter */
+#define IS_PWR_MEMORY_BLOCK(BLOCK) (((BLOCK) == PWR_SRD_AHB_MEMORY_BLOCK)     || \
+                                    ((BLOCK) == PWR_USB_FDCAN_MEMORY_BLOCK)   || \
+                                    ((BLOCK) == PWR_GFXMMU_JPEG_MEMORY_BLOCK) || \
+                                    ((BLOCK) == PWR_TCM_ECM_MEMORY_BLOCK)     || \
+                                    ((BLOCK) == PWR_RAM1_AHB_MEMORY_BLOCK)    || \
+                                    ((BLOCK) == PWR_RAM2_AHB_MEMORY_BLOCK)    || \
+                                    ((BLOCK) == PWR_RAM1_AXI_MEMORY_BLOCK)    || \
+                                    ((BLOCK) == PWR_RAM2_AXI_MEMORY_BLOCK)    || \
+                                    ((BLOCK) == PWR_RAM3_AXI_MEMORY_BLOCK))
+#endif /* defined (PWR_CR1_SRDRAMSO) */
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* STM32H7xx_HAL_PWR_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h
new file mode 100644
index 00000000..ceb86440
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h
@@ -0,0 +1,7973 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_rcc.h
+  * @author  MCD Application Team
+  * @brief   Header file of RCC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_RCC_H
+#define STM32H7xx_HAL_RCC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup RCC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Types RCC Exported Types
+  * @{
+  */
+
+/**
+  * @brief  RCC PLL configuration structure definition
+  */
+typedef struct
+{
+  uint32_t PLLState;   /*!< The new state of the PLL.
+                            This parameter can be a value of @ref RCC_PLL_Config                      */
+
+  uint32_t PLLSource;  /*!< RCC_PLLSource: PLL entry clock source.
+                            This parameter must be a value of @ref RCC_PLL_Clock_Source               */
+
+  uint32_t PLLM;       /*!< PLLM: Division factor for PLL VCO input clock.
+                            This parameter must be a number between Min_Data = 1 and Max_Data = 63    */
+
+  uint32_t PLLN;       /*!< PLLN: Multiplication factor for PLL VCO output clock.
+                            This parameter must be a number between Min_Data = 4 and Max_Data = 512 
+                            or between Min_Data = 8 and Max_Data = 420(*)
+                            (*) : For stm32h7a3xx and stm32h7b3xx family lines.                       */                        
+
+  uint32_t PLLP;       /*!< PLLP: Division factor for system clock.
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 128
+                          odd division factors are not allowed                                        */
+
+  uint32_t PLLQ;       /*!< PLLQ: Division factor for peripheral clocks.
+                            This parameter must be a number between Min_Data = 1 and Max_Data = 128   */
+
+  uint32_t PLLR;       /*!< PLLR: Division factor for peripheral clocks.
+                            This parameter must be a number between Min_Data = 1 and Max_Data = 128   */
+  uint32_t PLLRGE;     /*!<PLLRGE: PLL1 clock Input range
+                         This parameter must be a value of @ref RCC_PLL1_VCI_Range                    */
+  uint32_t PLLVCOSEL;  /*!<PLLVCOSEL: PLL1 clock Output range
+                         This parameter must be a value of @ref RCC_PLL1_VCO_Range                    */
+
+  uint32_t PLLFRACN;   /*!<PLLFRACN: Specifies Fractional Part Of The Multiplication Factor for
+                        PLL1 VCO It should be a value between 0 and 8191                              */
+
+}RCC_PLLInitTypeDef;
+
+/**
+  * @brief  RCC Internal/External Oscillator (HSE, HSI, CSI, LSE and LSI) configuration structure definition
+  */
+typedef struct
+{
+  uint32_t OscillatorType;       /*!< The oscillators to be configured.
+                                      This parameter can be a value of @ref RCC_Oscillator_Type                   */
+
+  uint32_t HSEState;             /*!< The new state of the HSE.
+                                      This parameter can be a value of @ref RCC_HSE_Config                        */
+
+  uint32_t LSEState;             /*!< The new state of the LSE.
+                                      This parameter can be a value of @ref RCC_LSE_Config                        */
+
+  uint32_t HSIState;             /*!< The new state of the HSI.
+                                      This parameter can be a value of @ref RCC_HSI_Config                        */
+
+  uint32_t HSICalibrationValue;  /*!< The calibration trimming value.
+                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F for STM32H7 rev.Y
+                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F for STM32H7 rev.B and above */
+
+  uint32_t LSIState;             /*!< The new state of the LSI.
+                                      This parameter can be a value of @ref RCC_LSI_Config                        */
+
+ uint32_t HSI48State;            /*!< The new state of the HSI48.
+                                      This parameter can be a value of @ref RCC_HSI48_Config                      */
+
+  uint32_t CSIState;             /*!< The new state of the CSI.
+                                      This parameter can be a value of @ref RCC_CSI_Config */
+
+  uint32_t CSICalibrationValue;  /*!< The calibration trimming value.
+                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F for STM32H7 rev.Y
+                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F for STM32H7 rev.B and above */
+
+  RCC_PLLInitTypeDef PLL;        /*!< PLL structure parameters                                                    */
+
+}RCC_OscInitTypeDef;
+
+/**
+  * @brief  RCC System, AHB and APB busses clock configuration structure definition
+  */
+typedef struct
+{
+  uint32_t ClockType;             /*!< The clock to be configured.
+                                       This parameter can be a value of @ref RCC_System_Clock_Type                          */
+
+  uint32_t SYSCLKSource;          /*!< The clock source (SYSCLKS) used as system clock.
+                                       This parameter can be a value of @ref RCC_System_Clock_Source                        */
+
+  uint32_t SYSCLKDivider;         /*!< The system clock  divider. This parameter can be
+                                       a value of @ref RCC_SYS_Clock_Source                                                 */
+
+  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
+                                       This parameter can be a value of @ref RCC_HCLK_Clock_Source                          */
+
+  uint32_t APB3CLKDivider;        /*!< The APB3 clock (D1PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_APB3_Clock_Source                        */
+
+  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_APB1_Clock_Source                        */
+  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_APB2_Clock_Source                        */
+  uint32_t APB4CLKDivider;      /*!< The APB4 clock (D3PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_APB4_Clock_Source                        */
+}RCC_ClkInitTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Constants RCC Exported Constants
+  * @{
+  */
+
+/** @defgroup RCC_Oscillator_Type  RCC Oscillator Type
+  * @{
+  */
+#define RCC_OSCILLATORTYPE_NONE        (0x00000000U)
+#define RCC_OSCILLATORTYPE_HSE         (0x00000001U)
+#define RCC_OSCILLATORTYPE_HSI         (0x00000002U)
+#define RCC_OSCILLATORTYPE_LSE         (0x00000004U)
+#define RCC_OSCILLATORTYPE_LSI         (0x00000008U)
+#define RCC_OSCILLATORTYPE_CSI         (0x00000010U)
+#define RCC_OSCILLATORTYPE_HSI48       (0x00000020U)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_HSE_Config  RCC HSE Config
+  * @{
+  */
+#define RCC_HSE_OFF                    (0x00000000U)
+#define RCC_HSE_ON                     RCC_CR_HSEON
+#define RCC_HSE_BYPASS                 ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
+#if defined(RCC_CR_HSEEXT)
+#define RCC_HSE_BYPASS_DIGITAL         ((uint32_t)(RCC_CR_HSEEXT | RCC_CR_HSEBYP | RCC_CR_HSEON))
+#endif /* RCC_CR_HSEEXT */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LSE_Config  RCC LSE Config
+  * @{
+  */
+#define RCC_LSE_OFF                    (0x00000000U)
+#define RCC_LSE_ON                     RCC_BDCR_LSEON
+#define RCC_LSE_BYPASS                 ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
+#if defined(RCC_BDCR_LSEEXT)
+#define RCC_LSE_BYPASS_DIGITAL         ((uint32_t)(RCC_BDCR_LSEEXT | RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
+#endif /* RCC_BDCR_LSEEXT */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_HSI_Config  RCC HSI Config
+  * @{
+  */
+#define RCC_HSI_OFF                      (0x00000000U)           /*!< HSI clock deactivation */
+#define RCC_HSI_ON                       RCC_CR_HSION                     /*!< HSI clock activation */
+
+#define RCC_HSI_DIV1                     (RCC_CR_HSIDIV_1 | RCC_CR_HSION) /*!< HSI_DIV1 clock activation */
+#define RCC_HSI_DIV2                     (RCC_CR_HSIDIV_2 | RCC_CR_HSION) /*!< HSI_DIV2 clock activation */
+#define RCC_HSI_DIV4                     (RCC_CR_HSIDIV_4 | RCC_CR_HSION) /*!< HSI_DIV4 clock activation */
+#define RCC_HSI_DIV8                     (RCC_CR_HSIDIV | RCC_CR_HSION)   /*!< HSI_DIV8 clock activation */
+
+
+#if defined(RCC_HSICFGR_HSITRIM_6)
+#define RCC_HSICALIBRATION_DEFAULT     (0x40U)         /* Default HSI calibration trimming value, for STM32H7 rev.V and above  */
+#else
+#define RCC_HSICALIBRATION_DEFAULT     (0x20U)         /* Default HSI calibration trimming value, for STM32H7 rev.Y */
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup RCC_HSI48_Config  RCC HSI48 Config
+  * @{
+  */
+#define RCC_HSI48_OFF                      ((uint8_t)0x00)
+#define RCC_HSI48_ON                       ((uint8_t)0x01)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LSI_Config  RCC LSI Config
+  * @{
+  */
+#define RCC_LSI_OFF                    (0x00000000U)
+#define RCC_LSI_ON                     RCC_CSR_LSION
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_CSI_Config  RCC CSI Config
+  * @{
+  */
+#define RCC_CSI_OFF                    (0x00000000U)
+#define RCC_CSI_ON                     RCC_CR_CSION
+
+#if defined(RCC_CSICFGR_CSITRIM_5)
+#define RCC_CSICALIBRATION_DEFAULT     (0x20U)         /* Default CSI calibration trimming value */
+#else
+#define RCC_CSICALIBRATION_DEFAULT     (0x10U)         /* Default CSI calibration trimming value */
+#endif /* RCC_CSICFGR_CSITRIM_5 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLL_Config  RCC PLL Config
+  * @{
+  */
+#define RCC_PLL_NONE                   (0x00000000U)
+#define RCC_PLL_OFF                    (0x00000001U)
+#define RCC_PLL_ON                     (0x00000002U)
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_PLL_Clock_Source  RCC PLL Clock Source
+  * @{
+  */
+#define RCC_PLLSOURCE_HSI              (0x00000000U)
+#define RCC_PLLSOURCE_CSI              (0x00000001U)
+#define RCC_PLLSOURCE_HSE              (0x00000002U)
+#define RCC_PLLSOURCE_NONE             (0x00000003U)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLL_Clock_Output  RCC PLL Clock Output
+  * @{
+  */
+#define RCC_PLL1_DIVP                RCC_PLLCFGR_DIVP1EN
+#define RCC_PLL1_DIVQ                RCC_PLLCFGR_DIVQ1EN
+#define RCC_PLL1_DIVR                RCC_PLLCFGR_DIVR1EN
+
+/**
+  * @}
+  */
+
+
+
+/** @defgroup RCC_PLL1_VCI_Range  RCC PLL1 VCI Range
+  * @{
+  */
+#define RCC_PLL1VCIRANGE_0                RCC_PLLCFGR_PLL1RGE_0       /*!< Clock range frequency between 1 and 2 MHz  */
+#define RCC_PLL1VCIRANGE_1                RCC_PLLCFGR_PLL1RGE_1       /*!< Clock range frequency between 2 and 4 MHz  */
+#define RCC_PLL1VCIRANGE_2                RCC_PLLCFGR_PLL1RGE_2       /*!< Clock range frequency between 4 and 8 MHz  */
+#define RCC_PLL1VCIRANGE_3                RCC_PLLCFGR_PLL1RGE_3       /*!< Clock range frequency between 8 and 16 MHz */
+
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_PLL1_VCO_Range  RCC PLL1 VCO Range
+  * @{
+  */
+#define RCC_PLL1VCOWIDE                 (0x00000000U)
+#define RCC_PLL1VCOMEDIUM               RCC_PLLCFGR_PLL1VCOSEL
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_System_Clock_Type  RCC System Clock Type
+  * @{
+  */
+#define RCC_CLOCKTYPE_SYSCLK           (0x00000001U)
+#define RCC_CLOCKTYPE_HCLK             (0x00000002U)
+#define RCC_CLOCKTYPE_D1PCLK1          (0x00000004U)
+#define RCC_CLOCKTYPE_PCLK1            (0x00000008U)
+#define RCC_CLOCKTYPE_PCLK2            (0x00000010U)
+#define RCC_CLOCKTYPE_D3PCLK1          (0x00000020U)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_System_Clock_Source  RCC System Clock Source
+  * @{
+  */
+#define RCC_SYSCLKSOURCE_CSI           RCC_CFGR_SW_CSI
+#define RCC_SYSCLKSOURCE_HSI           RCC_CFGR_SW_HSI
+#define RCC_SYSCLKSOURCE_HSE           RCC_CFGR_SW_HSE
+#define RCC_SYSCLKSOURCE_PLLCLK        RCC_CFGR_SW_PLL1
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
+  * @{
+  */
+#define RCC_SYSCLKSOURCE_STATUS_CSI    RCC_CFGR_SWS_CSI   /*!< CSI used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL1  /*!< PLL1 used as system clock */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_SYS_Clock_Source  RCC SYS Clock Source
+  * @{
+  */
+#if defined(RCC_D1CFGR_D1CPRE_DIV1)
+#define RCC_SYSCLK_DIV1                RCC_D1CFGR_D1CPRE_DIV1
+#define RCC_SYSCLK_DIV2                RCC_D1CFGR_D1CPRE_DIV2
+#define RCC_SYSCLK_DIV4                RCC_D1CFGR_D1CPRE_DIV4
+#define RCC_SYSCLK_DIV8                RCC_D1CFGR_D1CPRE_DIV8
+#define RCC_SYSCLK_DIV16               RCC_D1CFGR_D1CPRE_DIV16
+#define RCC_SYSCLK_DIV64               RCC_D1CFGR_D1CPRE_DIV64
+#define RCC_SYSCLK_DIV128              RCC_D1CFGR_D1CPRE_DIV128
+#define RCC_SYSCLK_DIV256              RCC_D1CFGR_D1CPRE_DIV256
+#define RCC_SYSCLK_DIV512              RCC_D1CFGR_D1CPRE_DIV512
+#else
+#define RCC_SYSCLK_DIV1                RCC_CDCFGR1_CDCPRE_DIV1
+#define RCC_SYSCLK_DIV2                RCC_CDCFGR1_CDCPRE_DIV2
+#define RCC_SYSCLK_DIV4                RCC_CDCFGR1_CDCPRE_DIV4
+#define RCC_SYSCLK_DIV8                RCC_CDCFGR1_CDCPRE_DIV8
+#define RCC_SYSCLK_DIV16               RCC_CDCFGR1_CDCPRE_DIV16
+#define RCC_SYSCLK_DIV64               RCC_CDCFGR1_CDCPRE_DIV64
+#define RCC_SYSCLK_DIV128              RCC_CDCFGR1_CDCPRE_DIV128
+#define RCC_SYSCLK_DIV256              RCC_CDCFGR1_CDCPRE_DIV256
+#define RCC_SYSCLK_DIV512              RCC_CDCFGR1_CDCPRE_DIV512
+#endif
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_HCLK_Clock_Source  RCC HCLK Clock Source
+  * @{
+  */
+#if defined(RCC_D1CFGR_HPRE_DIV1)
+#define RCC_HCLK_DIV1                RCC_D1CFGR_HPRE_DIV1
+#define RCC_HCLK_DIV2                RCC_D1CFGR_HPRE_DIV2
+#define RCC_HCLK_DIV4                RCC_D1CFGR_HPRE_DIV4
+#define RCC_HCLK_DIV8                RCC_D1CFGR_HPRE_DIV8
+#define RCC_HCLK_DIV16               RCC_D1CFGR_HPRE_DIV16
+#define RCC_HCLK_DIV64               RCC_D1CFGR_HPRE_DIV64
+#define RCC_HCLK_DIV128              RCC_D1CFGR_HPRE_DIV128
+#define RCC_HCLK_DIV256              RCC_D1CFGR_HPRE_DIV256
+#define RCC_HCLK_DIV512              RCC_D1CFGR_HPRE_DIV512
+#else
+#define RCC_HCLK_DIV1                RCC_CDCFGR1_HPRE_DIV1
+#define RCC_HCLK_DIV2                RCC_CDCFGR1_HPRE_DIV2
+#define RCC_HCLK_DIV4                RCC_CDCFGR1_HPRE_DIV4
+#define RCC_HCLK_DIV8                RCC_CDCFGR1_HPRE_DIV8
+#define RCC_HCLK_DIV16               RCC_CDCFGR1_HPRE_DIV16
+#define RCC_HCLK_DIV64               RCC_CDCFGR1_HPRE_DIV64
+#define RCC_HCLK_DIV128              RCC_CDCFGR1_HPRE_DIV128
+#define RCC_HCLK_DIV256              RCC_CDCFGR1_HPRE_DIV256
+#define RCC_HCLK_DIV512              RCC_CDCFGR1_HPRE_DIV512
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB3_Clock_Source  RCC APB3 Clock Source
+  * @{
+  */
+#if defined (RCC_D1CFGR_D1PPRE_DIV1)
+#define RCC_APB3_DIV1                  RCC_D1CFGR_D1PPRE_DIV1
+#define RCC_APB3_DIV2                  RCC_D1CFGR_D1PPRE_DIV2
+#define RCC_APB3_DIV4                  RCC_D1CFGR_D1PPRE_DIV4
+#define RCC_APB3_DIV8                  RCC_D1CFGR_D1PPRE_DIV8
+#define RCC_APB3_DIV16                 RCC_D1CFGR_D1PPRE_DIV16
+#else
+#define RCC_APB3_DIV1                  RCC_CDCFGR1_CDPPRE_DIV1
+#define RCC_APB3_DIV2                  RCC_CDCFGR1_CDPPRE_DIV2
+#define RCC_APB3_DIV4                  RCC_CDCFGR1_CDPPRE_DIV4
+#define RCC_APB3_DIV8                  RCC_CDCFGR1_CDPPRE_DIV8
+#define RCC_APB3_DIV16                 RCC_CDCFGR1_CDPPRE_DIV16
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB1_Clock_Source  RCC APB1 Clock Source
+  * @{
+  */
+#if defined (RCC_D2CFGR_D2PPRE1_DIV1)
+#define RCC_APB1_DIV1                  RCC_D2CFGR_D2PPRE1_DIV1
+#define RCC_APB1_DIV2                  RCC_D2CFGR_D2PPRE1_DIV2
+#define RCC_APB1_DIV4                  RCC_D2CFGR_D2PPRE1_DIV4
+#define RCC_APB1_DIV8                  RCC_D2CFGR_D2PPRE1_DIV8
+#define RCC_APB1_DIV16                 RCC_D2CFGR_D2PPRE1_DIV16
+#else
+#define RCC_APB1_DIV1                  RCC_CDCFGR2_CDPPRE1_DIV1
+#define RCC_APB1_DIV2                  RCC_CDCFGR2_CDPPRE1_DIV2
+#define RCC_APB1_DIV4                  RCC_CDCFGR2_CDPPRE1_DIV4
+#define RCC_APB1_DIV8                  RCC_CDCFGR2_CDPPRE1_DIV8
+#define RCC_APB1_DIV16                 RCC_CDCFGR2_CDPPRE1_DIV16
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB2_Clock_Source  RCC APB2 Clock Source
+  * @{
+  */
+#if defined (RCC_D2CFGR_D2PPRE2_DIV1)
+#define RCC_APB2_DIV1                  RCC_D2CFGR_D2PPRE2_DIV1
+#define RCC_APB2_DIV2                  RCC_D2CFGR_D2PPRE2_DIV2
+#define RCC_APB2_DIV4                  RCC_D2CFGR_D2PPRE2_DIV4
+#define RCC_APB2_DIV8                  RCC_D2CFGR_D2PPRE2_DIV8
+#define RCC_APB2_DIV16                 RCC_D2CFGR_D2PPRE2_DIV16
+#else
+#define RCC_APB2_DIV1                  RCC_CDCFGR2_CDPPRE2_DIV1
+#define RCC_APB2_DIV2                  RCC_CDCFGR2_CDPPRE2_DIV2
+#define RCC_APB2_DIV4                  RCC_CDCFGR2_CDPPRE2_DIV4
+#define RCC_APB2_DIV8                  RCC_CDCFGR2_CDPPRE2_DIV8
+#define RCC_APB2_DIV16                 RCC_CDCFGR2_CDPPRE2_DIV16
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB4_Clock_Source  RCC APB4 Clock Source
+  * @{
+  */
+#if defined(RCC_D3CFGR_D3PPRE_DIV1)
+#define RCC_APB4_DIV1                  RCC_D3CFGR_D3PPRE_DIV1
+#define RCC_APB4_DIV2                  RCC_D3CFGR_D3PPRE_DIV2
+#define RCC_APB4_DIV4                  RCC_D3CFGR_D3PPRE_DIV4
+#define RCC_APB4_DIV8                  RCC_D3CFGR_D3PPRE_DIV8
+#define RCC_APB4_DIV16                 RCC_D3CFGR_D3PPRE_DIV16
+#else
+#define RCC_APB4_DIV1                  RCC_SRDCFGR_SRDPPRE_DIV1
+#define RCC_APB4_DIV2                  RCC_SRDCFGR_SRDPPRE_DIV2
+#define RCC_APB4_DIV4                  RCC_SRDCFGR_SRDPPRE_DIV4
+#define RCC_APB4_DIV8                  RCC_SRDCFGR_SRDPPRE_DIV8
+#define RCC_APB4_DIV16                 RCC_SRDCFGR_SRDPPRE_DIV16
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup RCC_RTC_Clock_Source  RCC RTC Clock Source
+  * @{
+  */
+#define RCC_RTCCLKSOURCE_NO_CLK          (0x00000000U)
+#define RCC_RTCCLKSOURCE_LSE             (0x00000100U)
+#define RCC_RTCCLKSOURCE_LSI             (0x00000200U)
+#define RCC_RTCCLKSOURCE_HSE_DIV2        (0x00002300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV3        (0x00003300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV4        (0x00004300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV5        (0x00005300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV6        (0x00006300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV7        (0x00007300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV8        (0x00008300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV9        (0x00009300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV10       (0x0000A300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV11       (0x0000B300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV12       (0x0000C300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV13       (0x0000D300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV14       (0x0000E300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV15       (0x0000F300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV16       (0x00010300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV17       (0x00011300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV18       (0x00012300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV19       (0x00013300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV20       (0x00014300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV21       (0x00015300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV22       (0x00016300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV23       (0x00017300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV24       (0x00018300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV25       (0x00019300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV26       (0x0001A300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV27       (0x0001B300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV28       (0x0001C300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV29       (0x0001D300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV30       (0x0001E300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV31       (0x0001F300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV32       (0x00020300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV33       (0x00021300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV34       (0x00022300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV35       (0x00023300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV36       (0x00024300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV37       (0x00025300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV38       (0x00026300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV39       (0x00027300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV40       (0x00028300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV41       (0x00029300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV42       (0x0002A300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV43       (0x0002B300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV44       (0x0002C300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV45       (0x0002D300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV46       (0x0002E300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV47       (0x0002F300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV48       (0x00030300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV49       (0x00031300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV50       (0x00032300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV51       (0x00033300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV52       (0x00034300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV53       (0x00035300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV54       (0x00036300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV55       (0x00037300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV56       (0x00038300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV57       (0x00039300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV58       (0x0003A300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV59       (0x0003B300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV60       (0x0003C300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV61       (0x0003D300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV62       (0x0003E300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV63       (0x0003F300U)
+
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_MCO_Index  RCC MCO Index
+  * @{
+  */
+#define RCC_MCO1                         (0x00000000U)
+#define RCC_MCO2                         (0x00000001U)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MCO1_Clock_Source  RCC MCO1 Clock Source
+  * @{
+  */
+#define RCC_MCO1SOURCE_HSI               (0x00000000U)
+#define RCC_MCO1SOURCE_LSE               RCC_CFGR_MCO1_0
+#define RCC_MCO1SOURCE_HSE               RCC_CFGR_MCO1_1
+#define RCC_MCO1SOURCE_PLL1QCLK          ((uint32_t)RCC_CFGR_MCO1_0 | RCC_CFGR_MCO1_1)
+#define RCC_MCO1SOURCE_HSI48              RCC_CFGR_MCO1_2
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MCO2_Clock_Source  RCC MCO2 Clock Source
+  * @{
+  */
+#define RCC_MCO2SOURCE_SYSCLK            (0x00000000U)
+#define RCC_MCO2SOURCE_PLL2PCLK          RCC_CFGR_MCO2_0
+#define RCC_MCO2SOURCE_HSE               RCC_CFGR_MCO2_1
+#define RCC_MCO2SOURCE_PLLCLK            ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_1)
+#define RCC_MCO2SOURCE_CSICLK            RCC_CFGR_MCO2_2
+#define RCC_MCO2SOURCE_LSICLK            ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_2)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MCOx_Clock_Prescaler  RCC MCOx Clock Prescaler
+  * @{
+  */
+#define RCC_MCODIV_1                    RCC_CFGR_MCO1PRE_0
+#define RCC_MCODIV_2                    RCC_CFGR_MCO1PRE_1
+#define RCC_MCODIV_3                    ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1)
+#define RCC_MCODIV_4                    RCC_CFGR_MCO1PRE_2
+#define RCC_MCODIV_5                    ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
+#define RCC_MCODIV_6                    ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
+#define RCC_MCODIV_7                    ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
+#define RCC_MCODIV_8                    RCC_CFGR_MCO1PRE_3
+#define RCC_MCODIV_9                    ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_3)
+#define RCC_MCODIV_10                   ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
+#define RCC_MCODIV_11                   ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
+#define RCC_MCODIV_12                   ((uint32_t)RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
+#define RCC_MCODIV_13                   ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
+#define RCC_MCODIV_14                   ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
+#define RCC_MCODIV_15                   RCC_CFGR_MCO1PRE
+
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Interrupt  RCC Interrupt
+  * @{
+  */
+#define RCC_IT_LSIRDY                  (0x00000001U)
+#define RCC_IT_LSERDY                  (0x00000002U)
+#define RCC_IT_HSIRDY                  (0x00000004U)
+#define RCC_IT_HSERDY                  (0x00000008U)
+#define RCC_IT_CSIRDY                  (0x00000010U)
+#define RCC_IT_HSI48RDY                (0x00000020U)
+#define RCC_IT_PLLRDY                  (0x00000040U)
+#define RCC_IT_PLL2RDY                 (0x00000080U)
+#define RCC_IT_PLL3RDY                 (0x00000100U)
+#define RCC_IT_LSECSS                  (0x00000200U)
+#define RCC_IT_CSS                     (0x00000400U)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Flag  RCC Flag
+  *        Elements values convention: XXXYYYYYb
+  *           - YYYYY  : Flag position in the register
+  *           - XXX  : Register index
+  *                 - 001: CR register
+  *                 - 010: BDCR register
+  *                 - 011: CSR register
+  *                 - 100: RSR register
+  * @{
+  */
+/* Flags in the CR register */
+#define RCC_FLAG_HSIRDY                ((uint8_t)0x22)
+#define RCC_FLAG_HSIDIV                ((uint8_t)0x25)
+#define RCC_FLAG_CSIRDY                ((uint8_t)0x28)
+#define RCC_FLAG_HSI48RDY              ((uint8_t)0x2D)
+#if defined(RCC_CR_D1CKRDY)
+#define RCC_FLAG_D1CKRDY               ((uint8_t)0x2E)
+#else
+#define RCC_FLAG_CPUCKRDY              ((uint8_t)0x2E)
+#define RCC_FLAG_D1CKRDY               RCC_FLAG_CPUCKRDY   /* alias */
+#endif /* RCC_CR_D1CKRDY */
+#if defined(RCC_CR_D2CKRDY)
+#define RCC_FLAG_D2CKRDY               ((uint8_t)0x2F)
+#else
+#define RCC_FLAG_CDCKRDY               ((uint8_t)0x2F)
+#define RCC_FLAG_D2CKRDY               RCC_FLAG_CDCKRDY    /* alias */
+#endif /* RCC_CR_D2CKRDY */
+#define RCC_FLAG_HSERDY                ((uint8_t)0x31)
+#define RCC_FLAG_PLLRDY                ((uint8_t)0x39)
+#define RCC_FLAG_PLL2RDY               ((uint8_t)0x3B)
+#define RCC_FLAG_PLL3RDY               ((uint8_t)0x3D)
+/* Flags in the BDCR register */
+#define RCC_FLAG_LSERDY                ((uint8_t)0x41)
+
+/* Flags in the CSR register */
+#define RCC_FLAG_LSIRDY                ((uint8_t)0x61)
+
+/* Flags in the RSR register */
+#if defined(RCC_RSR_CPURSTF)
+#define RCC_FLAG_CPURST                ((uint8_t)0x91)
+#endif /* RCC_RSR_CPURSTF */
+
+#if defined(RCC_RSR_D1RSTF)
+#define RCC_FLAG_D1RST                 ((uint8_t)0x93)
+#else
+#define RCC_FLAG_CDRST                 ((uint8_t)0x93)
+#endif /* RCC_RSR_D1RSTF */
+#if defined(RCC_RSR_D2RSTF)
+#define RCC_FLAG_D2RST                 ((uint8_t)0x94)
+#endif /* RCC_RSR_D2RSTF */
+#define RCC_FLAG_BORRST                ((uint8_t)0x95)
+#define RCC_FLAG_PINRST                ((uint8_t)0x96)
+#define RCC_FLAG_PORRST                ((uint8_t)0x97)
+#define RCC_FLAG_SFTRST                ((uint8_t)0x98)
+#define RCC_FLAG_IWDG1RST              ((uint8_t)0x9A)
+#define RCC_FLAG_WWDG1RST              ((uint8_t)0x9C)
+#define RCC_FLAG_LPWR1RST              ((uint8_t)0x9E)
+#define RCC_FLAG_LPWR2RST              ((uint8_t)0x9F)
+
+#if defined(DUAL_CORE)
+#define RCC_FLAG_C1RST                 (RCC_FLAG_CPURST)
+#define RCC_FLAG_C2RST                 ((uint8_t)0x92)
+#define RCC_FLAG_SFTR1ST               (RCC_FLAG_SFTRST)
+#define RCC_FLAG_SFTR2ST               ((uint8_t)0x99)
+#define RCC_FLAG_WWDG2RST              ((uint8_t)0x9D)
+#define RCC_FLAG_IWDG2RST              ((uint8_t)0x9B)
+#endif /*DUAL_CORE*/
+
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LSEDrive_Config LSE Drive Config
+  * @{
+  */
+#define RCC_LSEDRIVE_LOW                 (0x00000000U) /*!< LSE low drive capability */
+#define RCC_LSEDRIVE_MEDIUMLOW           RCC_BDCR_LSEDRV_0      /*!< LSE medium low drive capability */
+#define RCC_LSEDRIVE_MEDIUMHIGH          RCC_BDCR_LSEDRV_1      /*!< LSE medium high drive capability */
+#define RCC_LSEDRIVE_HIGH                RCC_BDCR_LSEDRV        /*!< LSE high drive capability */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Stop_WakeUpClock  RCC Stop WakeUpClock
+  * @{
+  */
+#define RCC_STOP_WAKEUPCLOCK_HSI       (0x00000000U)
+#define RCC_STOP_WAKEUPCLOCK_CSI       RCC_CFGR_STOPWUCK
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Stop_KernelWakeUpClock  RCC Stop KernelWakeUpClock
+  * @{
+  */
+#define RCC_STOP_KERWAKEUPCLOCK_HSI       (0x00000000U)
+#define RCC_STOP_KERWAKEUPCLOCK_CSI        RCC_CFGR_STOPKERWUCK
+
+
+/**
+  * @}
+  */
+
+#if defined(RCC_VER_X)
+#define HAL_RCC_REV_Y_HSITRIM_Pos  (12U)
+#define HAL_RCC_REV_Y_HSITRIM_Msk  (0x3F000U)
+#define HAL_RCC_REV_Y_CSITRIM_Pos  (26U)
+#define HAL_RCC_REV_Y_CSITRIM_Msk  (0x7C000000U)
+#endif /* RCC_VER_X */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Macros RCC Exported Macros
+  * @{
+  */
+
+/** @brief  Enable or disable the AHB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+#define __HAL_RCC_MDMA_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_DMA2D_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(JPEG)
+#define __HAL_RCC_JPGDECEN_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* JPEG */
+
+#define __HAL_RCC_FMC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* QUADSPI */
+#if defined(OCTOSPI1)
+#define __HAL_RCC_OSPI1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* OCTOSPI1 */
+#if defined(OCTOSPI2)
+#define __HAL_RCC_OSPI2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* OCTOSPI2 */
+#if defined(OCTOSPIM)
+#define __HAL_RCC_OCTOSPIM_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_IOMNGREN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_IOMNGREN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* OCTOSPIM */
+#if defined(OTFDEC1)
+#define __HAL_RCC_OTFDEC1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* OTFDEC1 */
+#if defined(OTFDEC2)
+#define __HAL_RCC_OTFDEC2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* OTFDEC2 */
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GFXMMUEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GFXMMUEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* GFXMMU */
+#define __HAL_RCC_SDMMC1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_MDMA_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN))
+#define __HAL_RCC_DMA2D_CLK_DISABLE()           (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN))
+#if defined(JPEG)
+#define __HAL_RCC_JPGDECEN_CLK_DISABLE()        (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN))
+#endif /* JPEG */
+#define __HAL_RCC_FMC_CLK_DISABLE()             (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))
+
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN))
+#endif /* QUADSPI */
+#if defined(OCTOSPI1)
+#define __HAL_RCC_OSPI1_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OSPI1EN))
+#endif /* OCTOSPII */
+#if defined(OCTOSPI2)
+#define __HAL_RCC_OSPI2_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OSPI2EN))
+#endif /* OCTOSPI2 */
+#define __HAL_RCC_SDMMC1_CLK_DISABLE()          (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN))
+#if defined(OCTOSPIM)
+#define __HAL_RCC_OCTOSPIM_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_IOMNGREN))
+#endif /* OCTOSPIM */
+#if defined(OTFDEC1)
+#define __HAL_RCC_OTFDEC1_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OTFDEC1EN))
+#endif /* OTOFDEC1 */
+#if defined(OTFDEC2)
+#define __HAL_RCC_OTFDEC2_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OTFDEC2EN))
+#endif /* OTOFDEC2 */
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_GFXMMUEN))
+#endif /* GFXMMU */
+
+/** @brief  Get the enable or disable status of the AHB3 peripheral clock
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_MDMA_IS_CLK_ENABLED()          ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN)   != 0U)
+#define __HAL_RCC_DMA2D_IS_CLK_ENABLED()         ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN)  != 0U)
+#if defined(JPEG)
+#define __HAL_RCC_JPGDECEN_IS_CLK_ENABLED()      ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) != 0U)
+#endif /* JPEG */
+#define __HAL_RCC_FMC_IS_CLK_ENABLED()           ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN)    != 0U)
+#if defined (QUADSPI)
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED()          ((RCC->AHB3ENR & RCC_AHB3ENR_QSPIEN)   != 0U)
+#endif /* QUADSPI */
+#if defined(OCTOSPI1)
+#define __HAL_RCC_OSPI1_IS_CLK_ENABLED()          ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI1EN)   != 0U)
+#endif /* OCTOSPII */
+#if defined(OCTOSPI2)
+#define __HAL_RCC_OSPI2_IS_CLK_ENABLED()          ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI2EN)   != 0U)
+#endif /* OCTOSPI2 */
+#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) != 0U)
+#if defined(OCTOSPIM)
+#define __HAL_RCC_OCTOSPIM_IS_CLK_ENABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_IOMNGREN) != 0U)
+#endif /* OCTOSPIM */
+#if defined(OTFDEC1)
+#define __HAL_RCC_OTFDEC1_IS_CLK_ENABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC1EN) != 0U)
+#endif /* OTOFDEC1 */
+#if defined(OTFDEC2)
+#define __HAL_RCC_OTFDEC2_IS_CLK_ENABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC2EN) != 0U)
+#endif /* OTOFDEC2 */
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_IS_CLK_ENABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_GFXMMUEN) != 0U)
+#endif /* GFXMMU */
+
+#define __HAL_RCC_MDMA_IS_CLK_DISABLED()         ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN)   == 0U)
+#define __HAL_RCC_DMA2D_IS_CLK_DISABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN)  == 0U)
+#if defined(JPEG)
+#define __HAL_RCC_JPGDECEN_IS_CLK_DISABLED()     ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) == 0U)
+#endif /* JPEG */
+#define __HAL_RCC_FMC_IS_CLK_DISABLED()          ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN)    == 0U)
+#if defined (QUADSPI)
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED()         ((RCC->AHB3ENR & RCC_AHB3ENR_QSPIEN)   == 0U)
+#endif /* QUADSPI */
+#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED()       ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) == 0U)
+#if defined(OCTOSPI1)
+#define __HAL_RCC_OSPI1_IS_CLK_DISABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI1EN) == 0U)
+#endif
+#if defined(OCTOSPI2)
+#define __HAL_RCC_OSPI2_IS_CLK_DISABLED()     ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI2EN) == 0U)
+#endif
+#if defined(OCTOSPIM)
+#define __HAL_RCC_OCTOSPIM_IS_CLK_DISABLED()     ((RCC->AHB3ENR & RCC_AHB3ENR_IOMNGREN) == 0U)
+#endif
+#if defined(OTFDEC1)
+#define __HAL_RCC_OTFDEC1_IS_CLK_DISABLED()      ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC1EN) == 0U)
+#endif
+#if defined(OTFDEC2)
+#define __HAL_RCC_OTFDEC2_IS_CLK_DISABLED()      ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC2EN) == 0U)
+#endif
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_IS_CLK_DISABLED()       ((RCC->AHB3ENR & RCC_AHB3ENR_GFXMMUEN) == 0U)
+#endif
+/** @brief  Enable or disable the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_DMA1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_DMA2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_ADC12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(DUAL_CORE)
+#define __HAL_RCC_ART_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ARTEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ARTEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /*DUAL_CORE*/
+
+#if defined(RCC_AHB1ENR_CRCEN)
+#define __HAL_RCC_CRC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif
+
+#if defined(ETH)
+#define __HAL_RCC_ETH1MAC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_ETH1TX_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_ETH1RX_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif
+
+#define __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(USB2_OTG_FS)
+#define __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif
+
+#define __HAL_RCC_DMA1_CLK_DISABLE()             (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN))
+#define __HAL_RCC_DMA2_CLK_DISABLE()             (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN))
+#define __HAL_RCC_ADC12_CLK_DISABLE()            (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN))
+#if defined(DUAL_CORE)
+#define __HAL_RCC_ART_CLK_DISABLE()              (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN))
+#endif /*DUAL_CORE*/
+#if defined(RCC_AHB1ENR_CRCEN)
+#define __HAL_RCC_CRC_CLK_DISABLE()              (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_CRCEN))
+#endif
+#if defined(ETH)
+#define __HAL_RCC_ETH1MAC_CLK_DISABLE()          (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN))
+#define __HAL_RCC_ETH1TX_CLK_DISABLE()           (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN))
+#define __HAL_RCC_ETH1RX_CLK_DISABLE()           (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN))
+#endif
+#define __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()      (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN))
+#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN))
+#if defined(USB2_OTG_FS)
+#define __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()      (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN))
+#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN))
+#endif /* USB2_OTG_FS */
+
+/** @brief  Get the enable or disable status of the AHB1 peripheral clock
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_DMA1_IS_CLK_ENABLED()              ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN)          != 0U)
+#define __HAL_RCC_DMA2_IS_CLK_ENABLED()              ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN)          != 0U)
+#define __HAL_RCC_ADC12_IS_CLK_ENABLED()             ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN)         != 0U)
+#if defined(DUAL_CORE)
+#define __HAL_RCC_ART_IS_CLK_ENABLED()               ((RCC->AHB1ENR & RCC_AHB1ENR_ARTEN)           != 0U)
+#endif /*DUAL_CORE*/
+#if defined(RCC_AHB1ENR_CRCEN)
+#define __HAL_RCC_CRC_IS_CLK_ENABLED()              ((RCC->AHB1ENR & RCC_AHB1ENR_CRCEN)       != 0U)
+#endif
+#if defined(ETH)
+#define __HAL_RCC_ETH1MAC_IS_CLK_ENABLED()           ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1MACEN)       != 0U)
+#define __HAL_RCC_ETH1TX_IS_CLK_ENABLED()            ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1TXEN)        != 0U)
+#define __HAL_RCC_ETH1RX_IS_CLK_ENABLED()            ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1RXEN)        != 0U)
+#endif
+#define __HAL_RCC_USB1_OTG_HS_IS_CLK_ENABLED()       ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN)     != 0U)
+#define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_ENABLED()  ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) != 0U)
+#if defined(USB2_OTG_FS)
+#define __HAL_RCC_USB2_OTG_FS_IS_CLK_ENABLED()       ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSEN)     != 0U)
+#define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_ENABLED()  ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSULPIEN) != 0U)
+#endif /* USB2_OTG_FS */
+
+#define __HAL_RCC_DMA1_IS_CLK_DISABLED()             ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN)          == 0U)
+#define __HAL_RCC_DMA2_IS_CLK_DISABLED()             ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN)          == 0U)
+#define __HAL_RCC_ADC12_IS_CLK_DISABLED()            ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN)         == 0U)
+#if defined(DUAL_CORE)
+#define __HAL_RCC_ART_IS_CLK_DISABLED()              ((RCC->AHB1ENR & RCC_AHB1ENR_ARTEN)           == 0U)
+#endif /*DUAL_CORE*/
+#if defined(RCC_AHB1ENR_CRCEN)
+#define __HAL_RCC_CRC_IS_CLK_DISABLED()              ((RCC->AHB1ENR & RCC_AHB1ENR_CRCEN)           == 0U)
+#endif
+#if defined(ETH)
+#define __HAL_RCC_ETH1MAC_IS_CLK_DISABLED()          ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1MACEN)       == 0U)
+#define __HAL_RCC_ETH1TX_IS_CLK_DISABLED()           ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1TXEN)        == 0U)
+#define __HAL_RCC_ETH1RX_IS_CLK_DISABLED()           ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1RXEN)        == 0U)
+#endif
+#define __HAL_RCC_USB1_OTG_HS_IS_CLK_DISABLED()      ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN)     == 0U)
+#define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) == 0U)
+#if defined(USB2_OTG_FS)
+#define __HAL_RCC_USB2_OTG_FS_IS_CLK_DISABLED()      ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSEN)     == 0U)
+#define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSULPIEN) == 0U)
+#endif /* USB2_OTG_FS */
+
+/** @brief  Enable or disable the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#if defined(DCMI) && defined(PSSI)
+#define __HAL_RCC_DCMI_PSSI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_DCMI_CLK_ENABLE()  __HAL_RCC_DCMI_PSSI_CLK_ENABLE()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_DCMI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* DCMI && PSSI */
+
+#if defined(CRYP)
+#define __HAL_RCC_CRYP_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* CRYP */
+
+#if defined(HASH)
+#define __HAL_RCC_HASH_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* HASH */
+
+#define __HAL_RCC_RNG_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_SDMMC2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(RCC_AHB2ENR_D2SRAM1EN)
+#define __HAL_RCC_D2SRAM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#else
+#define __HAL_RCC_AHBSRAM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* RCC_AHB2ENR_D2SRAM1EN */
+
+#if defined(RCC_AHB2ENR_D2SRAM2EN)
+#define __HAL_RCC_D2SRAM2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#else
+#define __HAL_RCC_AHBSRAM2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* RCC_AHB2ENR_D2SRAM2EN */
+
+#if defined(RCC_AHB2ENR_D2SRAM3EN)
+#define __HAL_RCC_D2SRAM3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif
+
+#if defined(RCC_AHB2ENR_HSEMEN)
+#define __HAL_RCC_HSEM_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* RCC_AHB2ENR_HSEMEN */
+
+#if defined(BDMA1)
+#define __HAL_RCC_BDMA1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_BDMA1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_BDMA1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* BDMA1 */
+
+#if defined(DCMI) && defined(PSSI)
+#define __HAL_RCC_DCMI_PSSI_CLK_DISABLE()         (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMI_PSSIEN))
+#define __HAL_RCC_DCMI_CLK_DISABLE()              __HAL_RCC_DCMI_PSSI_CLK_DISABLE()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_DCMI_CLK_DISABLE()             (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))
+#endif /* DCMI && PSSI */
+#if defined(CRYP)
+#define __HAL_RCC_CRYP_CLK_DISABLE()             (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_HASH_CLK_DISABLE()             (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))
+#endif /* HASH */
+#define __HAL_RCC_RNG_CLK_DISABLE()              (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))
+#define __HAL_RCC_SDMMC2_CLK_DISABLE()           (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))
+#if defined(RCC_AHB2ENR_D2SRAM1EN)
+#define __HAL_RCC_D2SRAM1_CLK_DISABLE()          (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN))
+#else
+#define __HAL_RCC_AHBSRAM1_CLK_DISABLE()         (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_AHBSRAM1EN))
+#endif /* RCC_AHB2ENR_D2SRAM1EN */
+#if defined(RCC_AHB2ENR_D2SRAM2EN)
+#define __HAL_RCC_D2SRAM2_CLK_DISABLE()          (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN))
+#else
+#define __HAL_RCC_AHBSRAM2_CLK_DISABLE()         (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_AHBSRAM2EN))
+#endif /* RCC_AHB2ENR_D2SRAM2EN */
+#if defined(RCC_AHB2ENR_D2SRAM3EN)
+#define __HAL_RCC_D2SRAM3_CLK_DISABLE()          (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN))
+#endif
+#if defined(RCC_AHB2ENR_HSEMEN)
+#define __HAL_RCC_HSEM_CLK_DISABLE()             (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HSEMEN))
+#endif
+#if defined(BDMA1)
+#define __HAL_RCC_BDMA1_CLK_DISABLE()            (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_BDMA1EN))
+#endif
+
+/** @brief  Get the enable or disable status of the AHB2 peripheral clock
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#if defined(DCMI) && defined(PSSI)
+#define __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED()         ((RCC->AHB2ENR & RCC_AHB2ENR_DCMI_PSSIEN)    != 0U)
+#define __HAL_RCC_DCMI_IS_CLK_ENABLED()              __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_DCMI_IS_CLK_ENABLED()              ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN)    != 0U)
+#endif /* DCMI && PSSI */
+#if defined(CRYP)
+#define __HAL_RCC_CRYP_IS_CLK_ENABLED()              ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN)    != 0U)
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_HASH_IS_CLK_ENABLED()              ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN)    != 0U)
+#endif /* HASH */
+#define __HAL_RCC_RNG_IS_CLK_ENABLED()               ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN)     != 0U)
+#define __HAL_RCC_SDMMC2_IS_CLK_ENABLED()            ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN)  != 0U)
+#if defined(RCC_AHB2ENR_D2SRAM1EN)
+#define __HAL_RCC_D2SRAM1_IS_CLK_ENABLED()           ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM1EN) != 0U)
+#else
+#define __HAL_RCC_AHBSRAM1_IS_CLK_ENABLED()          ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM1EN) != 0U)
+#endif /* RCC_AHB2ENR_D2SRAM1EN */
+#if defined(RCC_AHB2ENR_D2SRAM2EN)
+#define __HAL_RCC_D2SRAM2_IS_CLK_ENABLED()           ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM2EN) != 0U)
+#else
+#define __HAL_RCC_AHBSRAM2_IS_CLK_ENABLED()          ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM2EN) != 0U)
+#endif /* RCC_AHB2ENR_D2SRAM2EN */
+#if defined(RCC_AHB2ENR_D2SRAM3EN)
+#define __HAL_RCC_D2SRAM3_IS_CLK_ENABLED()           ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM3EN) != 0U)
+#endif
+#if defined(RCC_AHB2ENR_HSEMEN)
+#define __HAL_RCC_HSEM_IS_CLK_ENABLED()              ((RCC->AHB2ENR & RCC_AHB2ENR_HSEMEN)    != 0U)
+#endif
+#if defined(BDMA1)
+#define __HAL_RCC_BDMA1_IS_CLK_ENABLED()             ((RCC->AHB2ENR & RCC_AHB2ENR_BDMA1EN)  != 0U)
+#endif
+
+#if defined(DCMI) && defined(PSSI)
+#define __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED()        ((RCC->AHB2ENR & RCC_AHB2ENR_DCMI_PSSIEN)    == 0U)
+#define __HAL_RCC_DCMI_IS_CLK_DISABLED()             __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_DCMI_IS_CLK_DISABLED()             ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN)    == 0U)
+#endif /* DCMI && PSSI */
+#if defined(CRYP)
+#define __HAL_RCC_CRYP_IS_CLK_DISABLED()             ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN)    == 0U)
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_HASH_IS_CLK_DISABLED()             ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN)    == 0U)
+#endif /* HASH */
+#define __HAL_RCC_RNG_IS_CLK_DISABLED()              ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN)     == 0U)
+#define __HAL_RCC_SDMMC2_IS_CLK_DISABLED()           ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN)  == 0U)
+#if defined(RCC_AHB2ENR_D2SRAM1EN)
+#define __HAL_RCC_D2SRAM1_IS_CLK_DISABLED()          ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM1EN) == 0U)
+#else
+#define __HAL_RCC_AHBSRAM1_IS_CLK_DISABLED()         ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM1EN) == 0U)
+#endif /* RCC_AHB2ENR_D2SRAM1EN */
+#if defined(RCC_AHB2ENR_D2SRAM2EN)
+#define __HAL_RCC_D2SRAM2_IS_CLK_DISABLED()          ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM2EN) == 0U)
+#else
+#define __HAL_RCC_AHBSRAM2_IS_CLK_DISABLED()         ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM2EN) == 0U)
+#endif /* RCC_AHB2ENR_D2SRAM2EN */
+#if defined(RCC_AHB2ENR_D2SRAM3EN)
+#define __HAL_RCC_D2SRAM3_IS_CLK_DISABLED()          ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM3EN) == 0U)
+#endif
+#if defined(RCC_AHB2ENR_HSEMEN)
+#define __HAL_RCC_HSEM_IS_CLK_DISABLED()             ((RCC->AHB2ENR & RCC_AHB2ENR_HSEMEN)    == 0U)
+#endif
+#if defined(BDMA1)
+#define __HAL_RCC_BDMA1_IS_CLK_DISABLED()            ((RCC->AHB2ENR & RCC_AHB2ENR_BDMA1EN)   == 0U)
+#endif
+
+/** @brief  Enable or disable the AHB4 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_GPIOA_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_GPIOB_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_GPIOC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_GPIOF_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_GPIOG_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_GPIOH_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_GPIOI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_GPIOJ_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_GPIOK_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(RCC_AHB4ENR_CRCEN)
+#define __HAL_RCC_CRC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif
+
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMA2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMA2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_BDMA_CLK_ENABLE()  __HAL_RCC_BDMA2_CLK_ENABLE()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_BDMA_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif
+
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif
+
+#if defined(RCC_AHB4ENR_HSEMEN)
+#define __HAL_RCC_HSEM_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif
+
+#if defined(RCC_AHB4ENR_SRDSRAMEN)
+#define __HAL_RCC_SRDSRAM_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SRDSRAMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SRDSRAMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif
+
+#define __HAL_RCC_BKPRAM_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_GPIOA_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN)
+#define __HAL_RCC_GPIOB_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN)
+#define __HAL_RCC_GPIOC_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN)
+#define __HAL_RCC_GPIOD_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN)
+#define __HAL_RCC_GPIOE_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN)
+#define __HAL_RCC_GPIOF_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN)
+#define __HAL_RCC_GPIOG_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN)
+#define __HAL_RCC_GPIOH_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN)
+#define __HAL_RCC_GPIOI_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN)
+#define __HAL_RCC_GPIOJ_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN)
+#define __HAL_RCC_GPIOK_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN)
+#if defined(RCC_AHB4ENR_CRCEN)
+#define __HAL_RCC_CRC_CLK_DISABLE()             (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN)
+#endif
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMA2EN)
+#define __HAL_RCC_BDMA_CLK_DISABLE()            __HAL_RCC_BDMA2_CLK_DISABLE()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_BDMA_CLK_DISABLE()            (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN)
+#endif
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_CLK_DISABLE()            (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN)
+#endif
+#if defined(RCC_AHB4ENR_HSEMEN)
+#define __HAL_RCC_HSEM_CLK_DISABLE()            (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN)
+#endif
+#if defined(RCC_AHB4ENR_SRDSRAMEN)
+#define __HAL_RCC_SRDSRAM_CLK_DISABLE()         (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_SRDSRAMEN)
+#endif
+#define __HAL_RCC_BKPRAM_CLK_DISABLE()          (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN)
+
+
+/** @brief  Get the enable or disable status of the AHB4 peripheral clock
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_GPIOA_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN)  != 0U)
+#define __HAL_RCC_GPIOB_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN)  != 0U)
+#define __HAL_RCC_GPIOC_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN)  != 0U)
+#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN)  != 0U)
+#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN)  != 0U)
+#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN)  != 0U)
+#define __HAL_RCC_GPIOG_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN)  != 0U)
+#define __HAL_RCC_GPIOH_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN)  != 0U)
+#define __HAL_RCC_GPIOI_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN)  != 0U)
+#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN)  != 0U)
+#define __HAL_RCC_GPIOK_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN)  != 0U)
+#if defined(RCC_AHB4ENR_CRCEN)
+#define __HAL_RCC_CRC_IS_CLK_ENABLED()              ((RCC->AHB4ENR & RCC_AHB4ENR_CRCEN)    != 0U)
+#endif
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_BDMA2EN)   != 0U)
+#define __HAL_RCC_BDMA_IS_CLK_ENABLED()  __HAL_RCC_BDMA2_IS_CLK_ENABLED()            /* for API backward compatibility*/
+#else
+#define __HAL_RCC_BDMA_IS_CLK_ENABLED()             ((RCC->AHB4ENR & RCC_AHB4ENR_BDMAEN)   != 0U)
+#endif
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_IS_CLK_ENABLED()             ((RCC->AHB4ENR & RCC_AHB4ENR_ADC3EN)   != 0U)
+#endif
+#if defined(RCC_AHB4ENR_HSEMEN)
+#define __HAL_RCC_HSEM_IS_CLK_ENABLED()             ((RCC->AHB4ENR & RCC_AHB4ENR_HSEMEN)   != 0U)
+#endif
+#if defined(RCC_AHB4ENR_SRDSRAMEN)
+#define __HAL_RCC_SRDSRAM_IS_CLK_ENABLED()          ((RCC->AHB4ENR & RCC_AHB4ENR_SRDSRAMEN) != 0U)
+#endif
+#define __HAL_RCC_BKPRAM_IS_CLK_ENABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) != 0U)
+
+#define __HAL_RCC_GPIOA_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN)  == 0U)
+#define __HAL_RCC_GPIOB_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN)  == 0U)
+#define __HAL_RCC_GPIOC_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN)  == 0U)
+#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN)  == 0U)
+#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN)  == 0U)
+#define __HAL_RCC_GPIOF_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN)  == 0U)
+#define __HAL_RCC_GPIOG_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN)  == 0U)
+#define __HAL_RCC_GPIOH_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN)  == 0U)
+#define __HAL_RCC_GPIOI_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN)  == 0U)
+#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN)  == 0U)
+#define __HAL_RCC_GPIOK_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN)  == 0U)
+
+#if defined(RCC_AHB4ENR_CRCEN)
+#define __HAL_RCC_CRC_IS_CLK_DISABLED()             ((RCC->AHB4ENR & RCC_AHB4ENR_CRCEN)    == 0U)
+#endif
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_IS_CLK_DISABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_BDMA2EN)   == 0U)
+#define __HAL_RCC_BDMA_IS_CLK_DISABLED()  __HAL_RCC_BDMA2_IS_CLK_DISABLED()           /* for API backward compatibility*/
+#else
+#define __HAL_RCC_BDMA_IS_CLK_DISABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_BDMAEN)   == 0U)
+#endif
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_IS_CLK_DISABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_ADC3EN)   == 0U)
+#endif
+#if defined(RCC_AHB4ENR_HSEMEN)
+#define __HAL_RCC_HSEM_IS_CLK_DISABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_HSEMEN)   == 0U)
+#endif
+#if defined(RCC_AHB4ENR_SRDSRAMEN)
+#define __HAL_RCC_SRDSRAM_IS_CLK_DISABLED()         ((RCC->AHB4ENR & RCC_AHB4ENR_SRDSRAMEN)   == 0U)
+#endif
+#define __HAL_RCC_BKPRAM_IS_CLK_DISABLED()          ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) == 0U)
+
+
+/** @brief  Enable or disable the APB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LTDCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LTDCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* LTDC */
+
+#if defined(DSI)
+#define __HAL_RCC_DSI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB3ENR, RCC_APB3ENR_DSIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_DSIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /*DSI*/
+
+#define __HAL_RCC_WWDG1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_CLK_DISABLE()           (RCC->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN)
+#endif /* LTDC */
+#if defined(DSI)
+#define __HAL_RCC_DSI_CLK_DISABLE()            (RCC->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN)
+#endif /*DSI*/
+#define __HAL_RCC_WWDG1_CLK_DISABLE()          (RCC->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN)
+
+/** @brief  Get the enable or disable status of the APB3 peripheral clock
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_IS_CLK_ENABLED()            ((RCC->APB3ENR & RCC_APB3ENR_LTDCEN)  != 0U)
+#endif /* LTDC */
+#if defined(DSI)
+#define __HAL_RCC_DSI_IS_CLK_ENABLED()             ((RCC->APB3ENR & RCC_APB3ENR_DSIEN)   != 0U)
+#endif /*DSI*/
+#define __HAL_RCC_WWDG1_IS_CLK_ENABLED()           ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) != 0U)
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_IS_CLK_DISABLED()           ((RCC->APB3ENR & RCC_APB3ENR_LTDCEN)  == 0U)
+#endif /* LTDC */
+#if defined(DSI)
+#define __HAL_RCC_DSI_IS_CLK_DISABLED()            ((RCC->APB3ENR & RCC_APB3ENR_DSIEN)   == 0U)
+#endif /*DSI*/
+#define __HAL_RCC_WWDG1_IS_CLK_DISABLED()          ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) == 0U)
+
+
+/** @brief  Enable or disable the APB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_TIM2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM6_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM7_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM13_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM14_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_LPTIM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(DUAL_CORE)
+#define __HAL_RCC_WWDG2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDG2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDG2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /*DUAL_CORE*/
+
+#define __HAL_RCC_SPI2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_SPI3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_SPDIFRX_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_USART2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_USART3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_UART4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_UART5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_I2C1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_I2C2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_I2C3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_CEC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_DAC12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_UART7_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_UART8_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_CRS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_SWPMI1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_OPAMP_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_MDIOS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_FDCAN_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_TIM2_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN)
+#define __HAL_RCC_TIM3_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN)
+#define __HAL_RCC_TIM4_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN)
+#define __HAL_RCC_TIM5_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN)
+#define __HAL_RCC_TIM6_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN)
+#define __HAL_RCC_TIM7_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN)
+#define __HAL_RCC_TIM12_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN)
+#define __HAL_RCC_TIM13_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN)
+#define __HAL_RCC_TIM14_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN)
+#define __HAL_RCC_LPTIM1_CLK_DISABLE()         (RCC->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN)
+
+#if defined(DUAL_CORE)
+#define __HAL_RCC_WWDG2_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN)
+#endif /*DUAL_CORE*/
+
+#define __HAL_RCC_SPI2_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN)
+#define __HAL_RCC_SPI3_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN)
+#define __HAL_RCC_SPDIFRX_CLK_DISABLE()        (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN)
+#define __HAL_RCC_USART2_CLK_DISABLE()         (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN)
+#define __HAL_RCC_USART3_CLK_DISABLE()         (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN)
+#define __HAL_RCC_UART4_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN)
+#define __HAL_RCC_UART5_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN)
+#define __HAL_RCC_I2C1_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN)
+#define __HAL_RCC_I2C2_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN)
+#define __HAL_RCC_I2C3_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN)
+#define __HAL_RCC_CEC_CLK_DISABLE()            (RCC->APB1LENR) &= ~ (RCC_APB1LENR_CECEN)
+#define __HAL_RCC_DAC12_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN)
+#define __HAL_RCC_UART7_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN)
+#define __HAL_RCC_UART8_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN)
+#define __HAL_RCC_CRS_CLK_DISABLE()            (RCC->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN)
+#define __HAL_RCC_SWPMI1_CLK_DISABLE()          (RCC->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN)
+#define __HAL_RCC_OPAMP_CLK_DISABLE()          (RCC->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN)
+#define __HAL_RCC_MDIOS_CLK_DISABLE()          (RCC->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN)
+#define __HAL_RCC_FDCAN_CLK_DISABLE()          (RCC->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN)
+
+
+/** @brief  Get the enable or disable status of the APB1 peripheral clock
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_TIM2_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN)    != 0U)
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN)    != 0U)
+#define __HAL_RCC_TIM4_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN)    != 0U)
+#define __HAL_RCC_TIM5_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN)    != 0U)
+#define __HAL_RCC_TIM6_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN)    != 0U)
+#define __HAL_RCC_TIM7_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN)    != 0U)
+#define __HAL_RCC_TIM12_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN)   != 0U)
+#define __HAL_RCC_TIM13_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN)   != 0U)
+#define __HAL_RCC_TIM14_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN)   != 0U)
+#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED()          ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN)  != 0U)
+#if defined(DUAL_CORE)
+#define __HAL_RCC_WWDG2_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_WWDG2EN)   != 0U)
+#endif /*DUAL_CORE*/
+#define __HAL_RCC_SPI2_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN)    != 0U)
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN)    != 0U)
+#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED()         ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) != 0U)
+#define __HAL_RCC_USART2_IS_CLK_ENABLED()          ((RCC->APB1LENR & RCC_APB1LENR_USART2EN)  != 0U)
+#define __HAL_RCC_USART3_IS_CLK_ENABLED()          ((RCC->APB1LENR & RCC_APB1LENR_USART3EN)  != 0U)
+#define __HAL_RCC_UART4_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_UART4EN)   != 0U)
+#define __HAL_RCC_UART5_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_UART5EN)   != 0U)
+#define __HAL_RCC_I2C1_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN)    != 0U)
+#define __HAL_RCC_I2C2_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN)    != 0U)
+#define __HAL_RCC_I2C3_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN)    != 0U)
+#define __HAL_RCC_CEC_IS_CLK_ENABLED()             ((RCC->APB1LENR & RCC_APB1LENR_CECEN)     != 0U)
+#define __HAL_RCC_DAC12_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN)   != 0U)
+#define __HAL_RCC_UART7_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_UART7EN)   != 0U)
+#define __HAL_RCC_UART8_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_UART8EN)   != 0U)
+#define __HAL_RCC_CRS_IS_CLK_ENABLED()             ((RCC->APB1HENR & RCC_APB1HENR_CRSEN)     != 0U)
+#define __HAL_RCC_SWPMI1_IS_CLK_ENABLED()          ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN)   != 0U)
+#define __HAL_RCC_OPAMP_IS_CLK_ENABLED()           ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN)   != 0U)
+#define __HAL_RCC_MDIOS_IS_CLK_ENABLED()           ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN)   != 0U)
+#define __HAL_RCC_FDCAN_IS_CLK_ENABLED()           ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN)   != 0U)
+
+#define __HAL_RCC_TIM2_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN)    == 0U)
+#define __HAL_RCC_TIM3_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN)    == 0U)
+#define __HAL_RCC_TIM4_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN)    == 0U)
+#define __HAL_RCC_TIM5_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN)    == 0U)
+#define __HAL_RCC_TIM6_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN)    == 0U)
+#define __HAL_RCC_TIM7_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN)    == 0U)
+#define __HAL_RCC_TIM12_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN)   == 0U)
+#define __HAL_RCC_TIM13_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN)   == 0U)
+#define __HAL_RCC_TIM14_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN)   == 0U)
+#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED()         ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN)  == 0U)
+#if defined(DUAL_CORE)
+#define __HAL_RCC_WWDG2_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_WWDG2EN)   == 0U)
+#endif /*DUAL_CORE*/
+#define __HAL_RCC_SPI2_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN)    == 0U)
+#define __HAL_RCC_SPI3_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN)    == 0U)
+#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED()        ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) == 0U)
+#define __HAL_RCC_USART2_IS_CLK_DISABLED()         ((RCC->APB1LENR & RCC_APB1LENR_USART2EN)  == 0U)
+#define __HAL_RCC_USART3_IS_CLK_DISABLED()         ((RCC->APB1LENR & RCC_APB1LENR_USART3EN)  == 0U)
+#define __HAL_RCC_UART4_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_UART4EN)   == 0U)
+#define __HAL_RCC_UART5_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_UART5EN)   == 0U)
+#define __HAL_RCC_I2C1_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN)    == 0U)
+#define __HAL_RCC_I2C2_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN)    == 0U)
+#define __HAL_RCC_I2C3_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN)    == 0U)
+#define __HAL_RCC_CEC_IS_CLK_DISABLED()            ((RCC->APB1LENR & RCC_APB1LENR_CECEN)     == 0U)
+#define __HAL_RCC_DAC12_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN)   == 0U)
+#define __HAL_RCC_UART7_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_UART7EN)   == 0U)
+#define __HAL_RCC_UART8_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_UART8EN)   == 0U)
+#define __HAL_RCC_CRS_IS_CLK_DISABLED()            ((RCC->APB1HENR & RCC_APB1HENR_CRSEN)     == 0U)
+#define __HAL_RCC_SWPMI1_IS_CLK_DISABLED()         ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN)   == 0U)
+#define __HAL_RCC_OPAMP_IS_CLK_DISABLED()          ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN)   == 0U)
+#define __HAL_RCC_MDIOS_IS_CLK_DISABLED()          ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN)   == 0U)
+#define __HAL_RCC_FDCAN_IS_CLK_DISABLED()          ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN)   == 0U)
+
+
+/** @brief  Enable or disable the APB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_TIM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM8_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_USART1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_USART6_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(UART9)
+#define __HAL_RCC_UART9_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /*UART9*/
+
+#if defined(USART10)
+#define __HAL_RCC_USART10_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART10EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART10EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /*USART10*/
+
+#define __HAL_RCC_SPI1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_SPI4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM15_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM16_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM17_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_SPI5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_SAI1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_SAI2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(SAI3)
+#define __HAL_RCC_SAI3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /*SAI3*/
+
+#define __HAL_RCC_DFSDM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /*HRTIM1*/
+
+#define __HAL_RCC_TIM1_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)
+#define __HAL_RCC_TIM8_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)
+#define __HAL_RCC_USART1_CLK_DISABLE()         (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)
+#define __HAL_RCC_USART6_CLK_DISABLE()         (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)
+#if defined(UART9)
+#define __HAL_RCC_UART9_CLK_DISABLE()          (RCC->APB2ENR) &= ~ (RCC_APB2ENR_UART9EN)
+#endif /*UART9*/
+#if defined(USART10)
+#define __HAL_RCC_USART10_CLK_DISABLE()        (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART10EN)
+#endif /*USART10*/
+#define __HAL_RCC_SPI1_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)
+#define __HAL_RCC_SPI4_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)
+#define __HAL_RCC_TIM15_CLK_DISABLE()          (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)
+#define __HAL_RCC_TIM16_CLK_DISABLE()          (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)
+#define __HAL_RCC_TIM17_CLK_DISABLE()          (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)
+#define __HAL_RCC_SPI5_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)
+#define __HAL_RCC_SAI1_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)
+#define __HAL_RCC_SAI2_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN)
+#if defined(SAI3)
+#define __HAL_RCC_SAI3_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN)
+#endif /*SAI3*/
+#define __HAL_RCC_DFSDM1_CLK_DISABLE()         (RCC->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_CLK_DISABLE()         (RCC->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN)
+#endif /*HRTIM*/
+
+/** @brief  Get the enable or disable status of the APB2 peripheral clock
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_TIM1_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN)   != 0U)
+#define __HAL_RCC_TIM8_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN)   != 0U)
+#define __HAL_RCC_USART1_IS_CLK_ENABLED()          ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) != 0U)
+#define __HAL_RCC_USART6_IS_CLK_ENABLED()          ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) != 0U)
+#if defined(UART9)
+#define __HAL_RCC_UART9_IS_CLK_ENABLED()           ((RCC->APB2ENR & RCC_APB2ENR_UART9EN) != 0U)
+#endif /*UART9*/
+#if defined(USART10)
+#define __HAL_RCC_USART10_IS_CLK_ENABLED()         ((RCC->APB2ENR & RCC_APB2ENR_USART10EN) != 0U)
+#endif /*USART10*/
+#define __HAL_RCC_SPI1_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN)   != 0U)
+#define __HAL_RCC_SPI4_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN)   != 0U)
+#define __HAL_RCC_TIM15_IS_CLK_ENABLED()           ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN)  != 0U)
+#define __HAL_RCC_TIM16_IS_CLK_ENABLED()           ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN)  != 0U)
+#define __HAL_RCC_TIM17_IS_CLK_ENABLED()           ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN)  != 0U)
+#define __HAL_RCC_SPI5_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN)   != 0U)
+#define __HAL_RCC_SAI1_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN)   != 0U)
+#define __HAL_RCC_SAI2_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN)   != 0U)
+#if defined(SAI3)
+#define __HAL_RCC_SAI3_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_SAI3EN)   != 0U)
+#endif /* SAI3 */
+#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED()          ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) != 0U)
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_IS_CLK_ENABLED()          ((RCC->APB2ENR & RCC_APB2ENR_HRTIMEN)  != 0U)
+#endif /*HRTIM1*/
+
+#define __HAL_RCC_TIM1_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN)   == 0U)
+#define __HAL_RCC_TIM8_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN)   == 0U)
+#define __HAL_RCC_USART1_IS_CLK_DISABLED()         ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) == 0U)
+#define __HAL_RCC_USART6_IS_CLK_DISABLED()         ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) == 0U)
+#if defined(UART9)
+#define __HAL_RCC_UART9_IS_CLK_DISABLED()         ((RCC->APB2ENR & RCC_APB2ENR_UART9EN) == 0U)
+#endif /*UART9*/
+#if defined(USART10)
+#define __HAL_RCC_USART10_IS_CLK_DISABLED()         ((RCC->APB2ENR & RCC_APB2ENR_USART10EN) == 0U)
+#endif /*USART10*/
+#define __HAL_RCC_SPI1_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN)   == 0U)
+#define __HAL_RCC_SPI4_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN)   == 0U)
+#define __HAL_RCC_TIM15_IS_CLK_DISABLED()          ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN)  == 0U)
+#define __HAL_RCC_TIM16_IS_CLK_DISABLED()          ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN)  == 0U)
+#define __HAL_RCC_TIM17_IS_CLK_DISABLED()          ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN)  == 0U)
+#define __HAL_RCC_SPI5_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN)   == 0U)
+#define __HAL_RCC_SAI1_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN)   == 0U)
+#define __HAL_RCC_SAI2_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN)   == 0U)
+#if defined(SAI3)
+#define __HAL_RCC_SAI3_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_SAI3EN)   == 0U)
+#endif /*SAI3*/
+#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED()         ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) == 0U)
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_IS_CLK_DISABLED()         ((RCC->APB2ENR & RCC_APB2ENR_HRTIMEN)  == 0U)
+#endif /*HRTIM1*/
+
+/** @brief  Enable or disable the APB4 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_SYSCFG_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_LPUART1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_SPI6_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_I2C4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_LPTIM2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_LPTIM3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* LPTIM4 */
+
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* LPTIM5 */
+
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DAC2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DAC2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /*  DAC2 */
+
+#define __HAL_RCC_COMP12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_VREF_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SAI4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SAI4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* SAI4 */
+
+#define __HAL_RCC_RTC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(DTS)
+#define __HAL_RCC_DTS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DTSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DTSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /*DTS*/
+
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DFSDM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DFSDM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /*DFSDM2*/
+
+#define __HAL_RCC_SYSCFG_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN)
+#define __HAL_RCC_LPUART1_CLK_DISABLE()          (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN)
+#define __HAL_RCC_SPI6_CLK_DISABLE()             (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN)
+#define __HAL_RCC_I2C4_CLK_DISABLE()             (RCC->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN)
+#define __HAL_RCC_LPTIM2_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN)
+#define __HAL_RCC_LPTIM3_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN)
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN)
+#endif /*LPTIM4*/
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN)
+#endif /*LPTIM5*/
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_CLK_DISABLE()             (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DAC2EN)
+#endif /*DAC2*/
+#define __HAL_RCC_COMP12_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN)
+#define __HAL_RCC_VREF_CLK_DISABLE()             (RCC->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN)
+#define __HAL_RCC_RTC_CLK_DISABLE()              (RCC->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN)
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_CLK_DISABLE()             (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN)
+#endif /*SAI4*/
+#if defined(DTS)
+#define __HAL_RCC_DTS_CLK_DISABLE()              (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DTSEN)
+#endif /*DTS*/
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DFSDM2EN)
+#endif /*DFSDM2*/
+
+/** @brief  Get the enable or disable status of the APB4 peripheral clock
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED()            ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN)  != 0U)
+#define __HAL_RCC_LPUART1_IS_CLK_ENABLED()           ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) != 0U)
+#define __HAL_RCC_SPI6_IS_CLK_ENABLED()              ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN)    != 0U)
+#define __HAL_RCC_I2C4_IS_CLK_ENABLED()              ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN)    != 0U)
+#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED()            ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN)  != 0U)
+#define __HAL_RCC_LPTIM3_IS_CLK_ENABLED()            ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN)  != 0U)
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_IS_CLK_ENABLED()            ((RCC->APB4ENR & RCC_APB4ENR_LPTIM4EN)  != 0U)
+#endif /*LPTIM4*/
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_IS_CLK_ENABLED()            ((RCC->APB4ENR & RCC_APB4ENR_LPTIM5EN)  != 0U)
+#endif /*LPTIM5*/
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_IS_CLK_ENABLED()              ((RCC->APB4ENR & RCC_APB4ENR_DAC2EN)  != 0U)
+#endif /*DAC2*/
+#define __HAL_RCC_COMP12_IS_CLK_ENABLED()            ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN)  != 0U)
+#define __HAL_RCC_VREF_IS_CLK_ENABLED()              ((RCC->APB4ENR & RCC_APB4ENR_VREFEN)    != 0U)
+#define __HAL_RCC_RTC_IS_CLK_ENABLED()               ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN)  != 0U)
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_IS_CLK_ENABLED()              ((RCC->APB4ENR & RCC_APB4ENR_SAI4EN)    != 0U)
+#endif /*SAI4*/
+#if defined(DTS)
+#define __HAL_RCC_DTS_IS_CLK_ENABLED()               ((RCC->APB4ENR & RCC_APB4ENR_DTSEN)    != 0U)
+#endif /*DTS*/
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_IS_CLK_ENABLED()              ((RCC->APB4ENR & RCC_APB4ENR_DFSDM2EN)    != 0U)
+#endif /*DFSDM2*/
+
+#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED()           ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN)  == 0U)
+#define __HAL_RCC_LPUART1_IS_CLK_DISABLED()          ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) == 0U)
+#define __HAL_RCC_SPI6_IS_CLK_DISABLED()             ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN)    == 0U)
+#define __HAL_RCC_I2C4_IS_CLK_DISABLED()             ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN)    == 0U)
+#define __HAL_RCC_LPTIM2_IS_CLK_DISABLED()           ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN)  == 0U)
+#define __HAL_RCC_LPTIM3_IS_CLK_DISABLED()           ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN)  == 0U)
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_IS_CLK_DISABLED()           ((RCC->APB4ENR & RCC_APB4ENR_LPTIM4EN)  == 0U)
+#endif /*LPTIM4*/
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_IS_CLK_DISABLED()           ((RCC->APB4ENR & RCC_APB4ENR_LPTIM5EN)  == 0U)
+#endif /*LPTIM5*/
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_IS_CLK_DISABLED()             ((RCC->APB4ENR & RCC_APB4ENR_DAC2EN)  == 0U)
+#endif /*DAC2*/
+#define __HAL_RCC_COMP12_IS_CLK_DISABLED()           ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN)  == 0U)
+#define __HAL_RCC_VREF_IS_CLK_DISABLED()             ((RCC->APB4ENR & RCC_APB4ENR_VREFEN)    == 0U)
+#define __HAL_RCC_RTC_IS_CLK_DISABLED()              ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN)  == 0U)
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_IS_CLK_DISABLED()             ((RCC->APB4ENR & RCC_APB4ENR_SAI4EN)    == 0U)
+#endif /*SAI4*/
+#if defined(DTS)
+#define __HAL_RCC_DTS_IS_CLK_DISABLED()              ((RCC->APB4ENR & RCC_APB4ENR_DTSEN)    == 0U)
+#endif /*DTS*/
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_IS_CLK_DISABLED()          ((RCC->APB4ENR & RCC_APB4ENR_DFSDM2EN)    == 0U)
+#endif /*DFSDM2*/
+
+#if defined(DUAL_CORE)
+
+/* Exported macros for RCC_C1 -------------------------------------------------*/
+
+/** @brief  Enable or disable the AHB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C1_MDMA_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_DMA2D_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_JPGDECEN_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_C1_FMC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_QSPI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SDMMC1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+
+
+#define __HAL_RCC_C1_MDMA_CLK_DISABLE()            (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN))
+#define __HAL_RCC_C1_DMA2D_CLK_DISABLE()           (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN))
+#define __HAL_RCC_C1_JPGDECEN_CLK_DISABLE()        (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN))
+#define __HAL_RCC_C1_FMC_CLK_DISABLE()             (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))
+#define __HAL_RCC_C1_QSPI_CLK_DISABLE()            (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN))
+#define __HAL_RCC_C1_SDMMC1_CLK_DISABLE()          (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN))
+
+
+
+
+/** @brief  Enable or disable the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C1_DMA1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_DMA2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_ADC12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_ART_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ARTEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ARTEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_ETH1MAC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_ETH1TX_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_ETH1RX_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_C1_USB1_OTG_HS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_USB2_OTG_FS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_DMA1_CLK_DISABLE()             (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN))
+#define __HAL_RCC_C1_DMA2_CLK_DISABLE()             (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN))
+#define __HAL_RCC_C1_ADC12_CLK_DISABLE()            (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN))
+#define __HAL_RCC_C1_ART_CLK_DISABLE()              (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN))
+#define __HAL_RCC_C1_ETH1MAC_CLK_DISABLE()          (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN))
+#define __HAL_RCC_C1_ETH1TX_CLK_DISABLE()           (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN))
+#define __HAL_RCC_C1_ETH1RX_CLK_DISABLE()           (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN))
+#define __HAL_RCC_C1_USB1_OTG_HS_CLK_DISABLE()      (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN))
+#define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN))
+#define __HAL_RCC_C1_USB2_OTG_FS_CLK_DISABLE()      (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN))
+#define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN))
+
+/** @brief  Enable or disable the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C1_DCMI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#if defined(CRYP)
+#define __HAL_RCC_C1_CRYP_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* CRYP */
+
+#if defined(HASH)
+#define __HAL_RCC_C1_HASH_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* HASH */
+
+#define __HAL_RCC_C1_RNG_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SDMMC2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_D2SRAM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_D2SRAM2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_D2SRAM3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_DCMI_CLK_DISABLE()             (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))
+#if defined(CRYP)
+#define __HAL_RCC_C1_CRYP_CLK_DISABLE()             (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_C1_HASH_CLK_DISABLE()             (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))
+#endif /* HASH */
+#define __HAL_RCC_C1_RNG_CLK_DISABLE()              (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))
+#define __HAL_RCC_C1_SDMMC2_CLK_DISABLE()           (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))
+#define __HAL_RCC_C1_D2SRAM1_CLK_DISABLE()          (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN))
+#define __HAL_RCC_C1_D2SRAM2_CLK_DISABLE()          (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN))
+#define __HAL_RCC_C1_D2SRAM3_CLK_DISABLE()          (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN))
+
+/** @brief  Enable or disable the AHB4 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C1_GPIOA_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_GPIOB_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_GPIOC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_GPIOD_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_GPIOE_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_GPIOF_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_GPIOG_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_GPIOH_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_GPIOI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_GPIOJ_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_GPIOK_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_CRC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_CRCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_CRCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_BDMA_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_ADC3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_HSEM_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_BKPRAM_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_C1_GPIOA_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN)
+#define __HAL_RCC_C1_GPIOB_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN)
+#define __HAL_RCC_C1_GPIOC_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN)
+#define __HAL_RCC_C1_GPIOD_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN)
+#define __HAL_RCC_C1_GPIOE_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN)
+#define __HAL_RCC_C1_GPIOF_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN)
+#define __HAL_RCC_C1_GPIOG_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN)
+#define __HAL_RCC_C1_GPIOH_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN)
+#define __HAL_RCC_C1_GPIOI_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN)
+#define __HAL_RCC_C1_GPIOJ_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN)
+#define __HAL_RCC_C1_GPIOK_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN)
+#define __HAL_RCC_C1_CRC_CLK_DISABLE()             (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN)
+#define __HAL_RCC_C1_BDMA_CLK_DISABLE()            (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN)
+#define __HAL_RCC_C1_ADC3_CLK_DISABLE()            (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN)
+#define __HAL_RCC_C1_HSEM_CLK_DISABLE()            (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN)
+#define __HAL_RCC_C1_BKPRAM_CLK_DISABLE()          (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN)
+
+
+/** @brief  Enable or disable the APB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C1_LTDC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_LTDCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_LTDCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_DSI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_DSIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_DSIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_WWDG1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_WWDG1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_WWDG1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_LTDC_CLK_DISABLE()           (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN)
+#define __HAL_RCC_C1_DSI_CLK_DISABLE()            (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN)
+#define __HAL_RCC_C1_WWDG1_CLK_DISABLE()          (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN)
+
+/** @brief  Enable or disable the APB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C1_TIM2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM6_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM6EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM6EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM7_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM7EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM7EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM13_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM13EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM13EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM14_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM14EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM14EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_LPTIM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_WWDG2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_WWDG2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_WWDG2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SPI2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SPI3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SPDIFRX_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_USART2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_USART3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_UART4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_UART5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_I2C1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_I2C2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_I2C3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_CEC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_CECEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_CECEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_DAC12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_DAC12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_DAC12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_UART7_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART7EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART7EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_UART8_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART8EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART8EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_CRS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_CRSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_CRSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SWPMI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_SWPMIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_SWPMIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_OPAMP_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_OPAMPEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_OPAMPEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_MDIOS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_MDIOSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_MDIOSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_FDCAN_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_FDCANEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_FDCANEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_C1_TIM2_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN)
+#define __HAL_RCC_C1_TIM3_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN)
+#define __HAL_RCC_C1_TIM4_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN)
+#define __HAL_RCC_C1_TIM5_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN)
+#define __HAL_RCC_C1_TIM6_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN)
+#define __HAL_RCC_C1_TIM7_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN)
+#define __HAL_RCC_C1_TIM12_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN)
+#define __HAL_RCC_C1_TIM13_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN)
+#define __HAL_RCC_C1_TIM14_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN)
+#define __HAL_RCC_C1_LPTIM1_CLK_DISABLE()         (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN)
+#define __HAL_RCC_C1_WWDG2_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN)
+#define __HAL_RCC_C1_SPI2_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN)
+#define __HAL_RCC_C1_SPI3_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN)
+#define __HAL_RCC_C1_SPDIFRX_CLK_DISABLE()        (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN)
+#define __HAL_RCC_C1_USART2_CLK_DISABLE()         (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN)
+#define __HAL_RCC_C1_USART3_CLK_DISABLE()         (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN)
+#define __HAL_RCC_C1_UART4_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN)
+#define __HAL_RCC_C1_UART5_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN)
+#define __HAL_RCC_C1_I2C1_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN)
+#define __HAL_RCC_C1_I2C2_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN)
+#define __HAL_RCC_C1_I2C3_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN)
+#define __HAL_RCC_C1_CEC_CLK_DISABLE()            (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_CECEN)
+#define __HAL_RCC_C1_DAC12_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN)
+#define __HAL_RCC_C1_UART7_CLK_DISABLE()         (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN)
+#define __HAL_RCC_C1_UART8_CLK_DISABLE()         (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN)
+#define __HAL_RCC_C1_CRS_CLK_DISABLE()            (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN)
+#define __HAL_RCC_C1_SWPMI_CLK_DISABLE()          (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN)
+#define __HAL_RCC_C1_OPAMP_CLK_DISABLE()          (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN)
+#define __HAL_RCC_C1_MDIOS_CLK_DISABLE()          (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN)
+#define __HAL_RCC_C1_FDCAN_CLK_DISABLE()          (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN)
+
+/** @brief  Enable or disable the APB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C1_TIM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM8_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM8EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM8EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_USART1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_USART6_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART6EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART6EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SPI1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SPI4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM15_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM15EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM15EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM16_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM16EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM16EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM17_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM17EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM17EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SPI5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SAI1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SAI2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SAI3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_DFSDM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_HRTIM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_HRTIMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_HRTIMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM1_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)
+#define __HAL_RCC_C1_TIM8_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)
+#define __HAL_RCC_C1_USART1_CLK_DISABLE()         (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)
+#define __HAL_RCC_C1_USART6_CLK_DISABLE()         (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)
+#define __HAL_RCC_C1_SPI1_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)
+#define __HAL_RCC_C1_SPI4_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)
+#define __HAL_RCC_C1_TIM15_CLK_DISABLE()          (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)
+#define __HAL_RCC_C1_TIM16_CLK_DISABLE()          (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)
+#define __HAL_RCC_C1_TIM17_CLK_DISABLE()          (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)
+#define __HAL_RCC_C1_SPI5_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)
+#define __HAL_RCC_C1_SAI1_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)
+#define __HAL_RCC_C1_SAI2_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN)
+#define __HAL_RCC_C1_SAI3_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN)
+#define __HAL_RCC_C1_DFSDM1_CLK_DISABLE()         (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)
+#define __HAL_RCC_C1_HRTIM1_CLK_DISABLE()         (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN)
+
+/** @brief  Enable or disable the APB4 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C1_SYSCFG_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_LPUART1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPUART1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPUART1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SPI6_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SPI6EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SPI6EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_I2C4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_I2C4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_I2C4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_LPTIM2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_LPTIM3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_LPTIM4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_LPTIM5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_COMP12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_COMP12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_COMP12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_C1_VREF_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_VREFEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_VREFEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_RTC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SAI4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SAI4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SAI4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_C1_SYSCFG_CLK_DISABLE()           (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN)
+#define __HAL_RCC_C1_LPUART1_CLK_DISABLE()          (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN)
+#define __HAL_RCC_C1_SPI6_CLK_DISABLE()             (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN)
+#define __HAL_RCC_C1_I2C4_CLK_DISABLE()             (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN)
+#define __HAL_RCC_C1_LPTIM2_CLK_DISABLE()           (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN)
+#define __HAL_RCC_C1_LPTIM3_CLK_DISABLE()           (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN)
+#define __HAL_RCC_C1_LPTIM4_CLK_DISABLE()           (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN)
+#define __HAL_RCC_C1_LPTIM5_CLK_DISABLE()           (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN)
+#define __HAL_RCC_C1_COMP12_CLK_DISABLE()           (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN)
+#define __HAL_RCC_C1_VREF_CLK_DISABLE()             (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN)
+#define __HAL_RCC_C1_RTC_CLK_DISABLE()              (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN)
+#define __HAL_RCC_C1_SAI4_CLK_DISABLE()             (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN)
+
+/* Exported macros for RCC_C2 -------------------------------------------------*/
+
+/** @brief  Enable or disable the AHB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+
+#define __HAL_RCC_C2_MDMA_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_DMA2D_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_JPGDECEN_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_FLASH_C2_ALLOCATE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FLASHEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FLASHEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_DTCM1_C2_ALLOCATE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_DTCM2_C2_ALLOCATE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_ITCM_C2_ALLOCATE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_ITCMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_ITCMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_D1SRAM1_C2_ALLOCATE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_AXISRAMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_AXISRAMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_FMC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_QSPI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SDMMC1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+
+
+#define __HAL_RCC_C2_MDMA_CLK_DISABLE()            (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN))
+#define __HAL_RCC_C2_DMA2D_CLK_DISABLE()           (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN))
+#define __HAL_RCC_C2_JPGDECEN_CLK_DISABLE()        (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN))
+#define __HAL_RCC_C2_FMC_CLK_DISABLE()             (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))
+#define __HAL_RCC_C2_QSPI_CLK_DISABLE()            (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN))
+#define __HAL_RCC_C2_SDMMC1_CLK_DISABLE()          (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN))
+#define __HAL_RCC_FLASH_C2_DEALLOCATE()            (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_FLASHEN))
+#define __HAL_RCC_DTCM1_C2_DEALLOCATE()            (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DTCM1EN))
+#define __HAL_RCC_DTCM2_C2_DEALLOCATE()            (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DTCM2EN))
+#define __HAL_RCC_ITCM_C2_DEALLOCATE()             (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_ITCMEN))
+#define __HAL_RCC_D1SRAM1_C2_DEALLOCATE()          (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_AXISRAMEN))
+
+/** @brief  Enable or disable the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C2_DMA1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_DMA2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_ADC12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_ART_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ARTEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ARTEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_ETH1MAC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_ETH1TX_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_ETH1RX_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_USB1_OTG_HS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_USB2_OTG_FS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_C2_DMA1_CLK_DISABLE()             (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN))
+#define __HAL_RCC_C2_DMA2_CLK_DISABLE()             (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN))
+#define __HAL_RCC_C2_ADC12_CLK_DISABLE()            (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN))
+#define __HAL_RCC_C2_ART_CLK_DISABLE()              (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN))
+#define __HAL_RCC_C2_ETH1MAC_CLK_DISABLE()          (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN))
+#define __HAL_RCC_C2_ETH1TX_CLK_DISABLE()           (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN))
+#define __HAL_RCC_C2_ETH1RX_CLK_DISABLE()           (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN))
+#define __HAL_RCC_C2_USB1_OTG_HS_CLK_DISABLE()      (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN))
+#define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN))
+#define __HAL_RCC_C2_USB2_OTG_FS_CLK_DISABLE()      (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN))
+#define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN))
+
+/** @brief  Enable or disable the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C2_DCMI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(CRYP)
+#define __HAL_RCC_C2_CRYP_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* CRYP */
+
+#if defined(HASH)
+#define __HAL_RCC_C2_HASH_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* HASH */
+
+#define __HAL_RCC_C2_RNG_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SDMMC2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_D2SRAM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_D2SRAM2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_D2SRAM3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_DCMI_CLK_DISABLE()             (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))
+#if defined(CRYP)
+#define __HAL_RCC_C2_CRYP_CLK_DISABLE()             (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_C2_HASH_CLK_DISABLE()             (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))
+#endif /* HASH */
+#define __HAL_RCC_C2_RNG_CLK_DISABLE()              (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))
+#define __HAL_RCC_C2_SDMMC2_CLK_DISABLE()           (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))
+#define __HAL_RCC_C2_D2SRAM1_CLK_DISABLE()          (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN))
+#define __HAL_RCC_C2_D2SRAM2_CLK_DISABLE()          (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN))
+#define __HAL_RCC_C2_D2SRAM3_CLK_DISABLE()          (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN))
+
+/** @brief  Enable or disable the AHB4 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C2_GPIOA_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_GPIOB_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_GPIOC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_GPIOD_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_GPIOE_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_GPIOF_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_GPIOG_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_GPIOH_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_GPIOI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_GPIOJ_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_GPIOK_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_CRC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_CRCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_CRCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_BDMA_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_ADC3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_HSEM_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_BKPRAM_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_C2_GPIOA_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN)
+#define __HAL_RCC_C2_GPIOB_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN)
+#define __HAL_RCC_C2_GPIOC_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN)
+#define __HAL_RCC_C2_GPIOD_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN)
+#define __HAL_RCC_C2_GPIOE_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN)
+#define __HAL_RCC_C2_GPIOF_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN)
+#define __HAL_RCC_C2_GPIOG_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN)
+#define __HAL_RCC_C2_GPIOH_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN)
+#define __HAL_RCC_C2_GPIOI_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN)
+#define __HAL_RCC_C2_GPIOJ_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN)
+#define __HAL_RCC_C2_GPIOK_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN)
+#define __HAL_RCC_C2_CRC_CLK_DISABLE()             (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN)
+#define __HAL_RCC_C2_BDMA_CLK_DISABLE()            (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN)
+#define __HAL_RCC_C2_ADC3_CLK_DISABLE()            (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN)
+#define __HAL_RCC_C2_HSEM_CLK_DISABLE()            (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN)
+#define __HAL_RCC_C2_BKPRAM_CLK_DISABLE()          (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN)
+
+
+/** @brief  Enable or disable the APB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C2_LTDC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_LTDCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_LTDCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_DSI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_DSIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_DSIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_WWDG1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_WWDG1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_WWDG1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_LTDC_CLK_DISABLE()           (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN)
+#define __HAL_RCC_C2_DSI_CLK_DISABLE()            (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN)
+#define __HAL_RCC_C2_WWDG1_CLK_DISABLE()          (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN)
+
+/** @brief  Enable or disable the APB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C2_TIM2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM6_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM6EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM6EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM7_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM7EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM7EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM13_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM13EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM13EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM14_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM14EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM14EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_LPTIM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_WWDG2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_WWDG2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_WWDG2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SPI2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SPI3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SPDIFRX_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_USART2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_USART3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_UART4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_UART5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_I2C1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_I2C2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_I2C3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_CEC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_CECEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_CECEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_DAC12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_DAC12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_DAC12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_UART7_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART7EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART7EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_UART8_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART8EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART8EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_CRS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_CRSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_CRSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SWPMI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_SWPMIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_SWPMIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_OPAMP_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_OPAMPEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_OPAMPEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_MDIOS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_MDIOSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_MDIOSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_FDCAN_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_FDCANEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_FDCANEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_C2_TIM2_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN)
+#define __HAL_RCC_C2_TIM3_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN)
+#define __HAL_RCC_C2_TIM4_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN)
+#define __HAL_RCC_C2_TIM5_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN)
+#define __HAL_RCC_C2_TIM6_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN)
+#define __HAL_RCC_C2_TIM7_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN)
+#define __HAL_RCC_C2_TIM12_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN)
+#define __HAL_RCC_C2_TIM13_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN)
+#define __HAL_RCC_C2_TIM14_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN)
+#define __HAL_RCC_C2_LPTIM1_CLK_DISABLE()         (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN)
+#define __HAL_RCC_C2_WWDG2_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN)
+#define __HAL_RCC_C2_SPI2_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN)
+#define __HAL_RCC_C2_SPI3_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN)
+#define __HAL_RCC_C2_SPDIFRX_CLK_DISABLE()        (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN)
+#define __HAL_RCC_C2_USART2_CLK_DISABLE()         (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN)
+#define __HAL_RCC_C2_USART3_CLK_DISABLE()         (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN)
+#define __HAL_RCC_C2_UART4_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN)
+#define __HAL_RCC_C2_UART5_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN)
+#define __HAL_RCC_C2_I2C1_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN)
+#define __HAL_RCC_C2_I2C2_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN)
+#define __HAL_RCC_C2_I2C3_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN)
+#define __HAL_RCC_C2_CEC_CLK_DISABLE()            (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_CECEN)
+#define __HAL_RCC_C2_DAC12_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN)
+#define __HAL_RCC_C2_UART7_CLK_DISABLE()         (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN)
+#define __HAL_RCC_C2_UART8_CLK_DISABLE()         (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN)
+#define __HAL_RCC_C2_CRS_CLK_DISABLE()            (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN)
+#define __HAL_RCC_C2_SWPMI_CLK_DISABLE()          (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN)
+#define __HAL_RCC_C2_OPAMP_CLK_DISABLE()          (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN)
+#define __HAL_RCC_C2_MDIOS_CLK_DISABLE()          (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN)
+#define __HAL_RCC_C2_FDCAN_CLK_DISABLE()          (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN)
+
+/** @brief  Enable or disable the APB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C2_TIM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM8_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM8EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM8EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_USART1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_USART6_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART6EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART6EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SPI1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SPI4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM15_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM15EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM15EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM16_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM16EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM16EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM17_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM17EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM17EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SPI5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SAI1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SAI2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SAI3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_DFSDM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_HRTIM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_HRTIMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_HRTIMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM1_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)
+#define __HAL_RCC_C2_TIM8_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)
+#define __HAL_RCC_C2_USART1_CLK_DISABLE()         (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)
+#define __HAL_RCC_C2_USART6_CLK_DISABLE()         (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)
+#define __HAL_RCC_C2_SPI1_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)
+#define __HAL_RCC_C2_SPI4_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)
+#define __HAL_RCC_C2_TIM15_CLK_DISABLE()          (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)
+#define __HAL_RCC_C2_TIM16_CLK_DISABLE()          (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)
+#define __HAL_RCC_C2_TIM17_CLK_DISABLE()          (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)
+#define __HAL_RCC_C2_SPI5_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)
+#define __HAL_RCC_C2_SAI1_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)
+#define __HAL_RCC_C2_SAI2_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN)
+#define __HAL_RCC_C2_SAI3_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN)
+#define __HAL_RCC_C2_DFSDM1_CLK_DISABLE()         (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)
+#define __HAL_RCC_C2_HRTIM1_CLK_DISABLE()         (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN)
+
+/** @brief  Enable or disable the APB4 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C2_SYSCFG_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_LPUART1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPUART1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPUART1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SPI6_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SPI6EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SPI6EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_I2C4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_I2C4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_I2C4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_LPTIM2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_LPTIM3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_LPTIM4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_LPTIM5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_COMP12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_COMP12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_COMP12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_VREF_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_VREFEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_VREFEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_RTC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SAI4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SAI4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SAI4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+
+#define __HAL_RCC_C2_SYSCFG_CLK_DISABLE()           (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN)
+#define __HAL_RCC_C2_LPUART1_CLK_DISABLE()          (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN)
+#define __HAL_RCC_C2_SPI6_CLK_DISABLE()             (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN)
+#define __HAL_RCC_C2_I2C4_CLK_DISABLE()             (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN)
+#define __HAL_RCC_C2_LPTIM2_CLK_DISABLE()           (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN)
+#define __HAL_RCC_C2_LPTIM3_CLK_DISABLE()           (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN)
+#define __HAL_RCC_C2_LPTIM4_CLK_DISABLE()           (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN)
+#define __HAL_RCC_C2_LPTIM5_CLK_DISABLE()           (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN)
+#define __HAL_RCC_C2_COMP12_CLK_DISABLE()           (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN)
+#define __HAL_RCC_C2_VREF_CLK_DISABLE()             (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN)
+#define __HAL_RCC_C2_RTC_CLK_DISABLE()              (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN)
+#define __HAL_RCC_C2_SAI4_CLK_DISABLE()             (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN)
+
+#endif /*DUAL_CORE*/
+
+/** @brief  Enable or disable the AHB3 peripheral reset.
+  */
+
+#define __HAL_RCC_AHB3_FORCE_RESET()          (RCC->AHB3RSTR = 0x7FFFFFFFU)
+#define __HAL_RCC_MDMA_FORCE_RESET()          (RCC->AHB3RSTR |= (RCC_AHB3RSTR_MDMARST))
+#define __HAL_RCC_DMA2D_FORCE_RESET()         (RCC->AHB3RSTR |= (RCC_AHB3RSTR_DMA2DRST))
+#if defined(JPEG)
+#define __HAL_RCC_JPGDECRST_FORCE_RESET()     (RCC->AHB3RSTR |= (RCC_AHB3RSTR_JPGDECRST))
+#endif /* JPEG */
+#define __HAL_RCC_FMC_FORCE_RESET()           (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_FORCE_RESET()          (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
+#endif /*QUADSPI*/
+#if defined(OCTOSPI1)
+#define __HAL_RCC_OSPI1_FORCE_RESET()         (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OSPI1RST))
+#endif /*OCTOSPI1*/
+#define __HAL_RCC_SDMMC1_FORCE_RESET()        (RCC->AHB3RSTR |= (RCC_AHB3RSTR_SDMMC1RST))
+#if defined(OCTOSPI2)
+#define __HAL_RCC_OSPI2_FORCE_RESET()         (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OSPI2RST))
+#endif /*OCTOSPI2*/
+#if defined(OCTOSPIM)
+#define __HAL_RCC_IOMNGR_FORCE_RESET()      (RCC->AHB3RSTR |= (RCC_AHB3RSTR_IOMNGRRST))
+#endif /*OCTOSPIM*/
+#if defined(OTFDEC1)
+#define __HAL_RCC_OTFDEC1_FORCE_RESET()         (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OTFDEC1RST))
+#endif /*OTFDEC1*/
+#if defined(OTFDEC2)
+#define __HAL_RCC_OTFDEC2_FORCE_RESET()         (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OTFDEC2RST))
+#endif /*OTFDEC2*/
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_FORCE_RESET()        (RCC->AHB3RSTR |= (RCC_AHB3RSTR_GFXMMURST))
+#endif /*GFXMMU*/
+
+#define __HAL_RCC_AHB3_RELEASE_RESET()        (RCC->AHB3RSTR = 0x00)
+#define __HAL_RCC_MDMA_RELEASE_RESET()        (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_MDMARST))
+#define __HAL_RCC_DMA2D_RELEASE_RESET()       (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_DMA2DRST))
+#if defined(JPEG)
+#define __HAL_RCC_JPGDECRST_RELEASE_RESET()   (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_JPGDECRST))
+#endif /* JPEG */
+#define __HAL_RCC_FMC_RELEASE_RESET()         (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_FMCRST))
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_RELEASE_RESET()        (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_QSPIRST))
+#endif /*QUADSPI*/
+#if defined(OCTOSPI1)
+#define __HAL_RCC_OSPI1_RELEASE_RESET()       (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OSPI1RST))
+#endif /*OCTOSPI1*/
+#define __HAL_RCC_SDMMC1_RELEASE_RESET()      (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_SDMMC1RST))
+#if defined(OCTOSPI2)
+#define __HAL_RCC_OSPI2_RELEASE_RESET()       (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OSPI2RST))
+#endif /*OCTOSPI2*/
+#if defined(OCTOSPIM)
+#define __HAL_RCC_IOMNGR_RELEASE_RESET()      (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_IOMNGRRST))
+#endif /*OCTOSPIM*/
+#if defined(OTFDEC1)
+#define __HAL_RCC_OTFDEC1_RELEASE_RESET()       (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OTFDEC1RST))
+#endif /*OTFDEC1*/
+#if defined(OTFDEC2)
+#define __HAL_RCC_OTFDEC2_RELEASE_RESET()       (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OTFDEC2RST))
+#endif /*OTFDEC2*/
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_RELEASE_RESET()      (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_GFXMMURST))
+#endif /*GFXMMU*/
+
+
+
+/** @brief  Force or release the AHB1 peripheral reset.
+  */
+#define __HAL_RCC_AHB1_FORCE_RESET()             (RCC->AHB1RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_DMA1_FORCE_RESET()             (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
+#define __HAL_RCC_DMA2_FORCE_RESET()             (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
+#define __HAL_RCC_ADC12_FORCE_RESET()            (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ADC12RST))
+#if defined(DUAL_CORE)
+#define __HAL_RCC_ART_FORCE_RESET()              (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ARTRST))
+#endif /*DUAL_CORE*/
+#if defined(RCC_AHB1RSTR_CRCRST)
+#define __HAL_RCC_CRC_FORCE_RESET()            (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
+#endif
+#if defined(ETH)
+#define __HAL_RCC_ETH1MAC_FORCE_RESET()          (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETH1MACRST))
+#endif /*ETH*/
+#define __HAL_RCC_USB1_OTG_HS_FORCE_RESET()      (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB1OTGHSRST))
+#if defined(USB2_OTG_FS)
+#define __HAL_RCC_USB2_OTG_FS_FORCE_RESET()      (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB2OTGHSRST))
+#endif /*USB2_OTG_FS*/
+
+#define __HAL_RCC_AHB1_RELEASE_RESET()           (RCC->AHB1RSTR = 0x00U)
+#define __HAL_RCC_DMA1_RELEASE_RESET()             (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA1RST))
+#define __HAL_RCC_DMA2_RELEASE_RESET()             (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA2RST))
+#define __HAL_RCC_ADC12_RELEASE_RESET()            (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ADC12RST))
+#if defined(DUAL_CORE)
+#define __HAL_RCC_ART_RELEASE_RESET()              (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ARTRST))
+#endif /*DUAL_CORE*/
+#if defined(RCC_AHB1RSTR_CRCRST)
+#define __HAL_RCC_CRC_RELEASE_RESET()                (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_CRCRST))
+#endif
+#if defined(ETH)
+#define __HAL_RCC_ETH1MAC_RELEASE_RESET()          (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ETH1MACRST))
+#endif /*ETH*/
+#define __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()      (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB1OTGHSRST))
+#if defined(USB2_OTG_FS)
+#define __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()      (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB2OTGHSRST))
+#endif /*USB2_OTG_FS*/
+
+/** @brief  Force or release the AHB2 peripheral reset.
+  */
+#define __HAL_RCC_AHB2_FORCE_RESET()           (RCC->AHB2RSTR = 0xFFFFFFFFU)
+#if defined(DCMI) && defined(PSSI)
+#define __HAL_RCC_DCMI_PSSI_FORCE_RESET()        (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMI_PSSIRST))
+#define __HAL_RCC_DCMI_FORCE_RESET()             __HAL_RCC_DCMI_PSSI_FORCE_RESET()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_DCMI_FORCE_RESET()             (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
+#endif /* DCMI && PSSI */
+#if defined(CRYP)
+#define __HAL_RCC_CRYP_FORCE_RESET()             (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_HASH_FORCE_RESET()             (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
+#endif /* HASH */
+#define __HAL_RCC_RNG_FORCE_RESET()              (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
+#define __HAL_RCC_SDMMC2_FORCE_RESET()           (RCC->AHB2RSTR |= (RCC_AHB2RSTR_SDMMC2RST))
+#if defined(RCC_AHB2RSTR_HSEMRST)
+#define __HAL_RCC_HSEM_FORCE_RESET()             (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HSEMRST))
+#endif
+#if defined(BDMA1)
+#define __HAL_RCC_BDMA1_FORCE_RESET()           (RCC->AHB2RSTR |= (RCC_AHB2RSTR_BDMA1RST))
+#endif /*BDMA1*/
+
+#define __HAL_RCC_AHB2_RELEASE_RESET()           (RCC->AHB2RSTR = 0x00U)
+#if defined(DCMI) && defined(PSSI)
+#define __HAL_RCC_DCMI_PSSI_RELEASE_RESET()        (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMI_PSSIRST))
+#define __HAL_RCC_DCMI_RELEASE_RESET()             __HAL_RCC_DCMI_PSSI_RELEASE_RESET()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_DCMI_RELEASE_RESET()             (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMIRST))
+#endif /* DCMI && PSSI */
+#if defined(CRYP)
+#define __HAL_RCC_CRYP_RELEASE_RESET()             (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_CRYPRST))
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_HASH_RELEASE_RESET()             (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HASHRST))
+#endif /* HASH */
+#define __HAL_RCC_RNG_RELEASE_RESET()              (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_RNGRST))
+#define __HAL_RCC_SDMMC2_RELEASE_RESET()           (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_SDMMC2RST))
+#if defined(RCC_AHB2RSTR_HSEMRST)
+#define __HAL_RCC_HSEM_RELEASE_RESET()             (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HSEMRST))
+#endif
+#if defined(BDMA1)
+#define __HAL_RCC_BDMA1_RELEASE_RESET()           (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_BDMA1RST))
+#endif /*BDMA1*/
+
+
+/** @brief  Force or release the AHB4 peripheral reset.
+  */
+
+#define __HAL_RCC_AHB4_FORCE_RESET()            (RCC->AHB4RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_GPIOA_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOARST)
+#define __HAL_RCC_GPIOB_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOBRST)
+#define __HAL_RCC_GPIOC_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOCRST)
+#define __HAL_RCC_GPIOD_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIODRST)
+#define __HAL_RCC_GPIOE_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOERST)
+#define __HAL_RCC_GPIOF_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOFRST)
+#define __HAL_RCC_GPIOG_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOGRST)
+#define __HAL_RCC_GPIOH_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOHRST)
+#define __HAL_RCC_GPIOI_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOIRST)
+#define __HAL_RCC_GPIOJ_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOJRST)
+#define __HAL_RCC_GPIOK_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOKRST)
+#if defined(RCC_AHB4RSTR_CRCRST)
+#define __HAL_RCC_CRC_FORCE_RESET()             (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_CRCRST)
+#endif
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_BDMA2RST)
+#define __HAL_RCC_BDMA_FORCE_RESET()            __HAL_RCC_BDMA2_FORCE_RESET()         /* for API backward compatibility*/
+#else
+#define __HAL_RCC_BDMA_FORCE_RESET()            (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_BDMARST)
+#endif /*BDMA2*/
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_FORCE_RESET()            (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_ADC3RST)
+#endif /*ADC3*/
+#if defined(RCC_AHB4RSTR_HSEMRST)
+#define __HAL_RCC_HSEM_FORCE_RESET()            (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_HSEMRST)
+#endif
+
+#define __HAL_RCC_AHB4_RELEASE_RESET()          (RCC->AHB4RSTR = 0x00U)
+#define __HAL_RCC_GPIOA_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOARST)
+#define __HAL_RCC_GPIOB_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOBRST)
+#define __HAL_RCC_GPIOC_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOCRST)
+#define __HAL_RCC_GPIOD_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIODRST)
+#define __HAL_RCC_GPIOE_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOERST)
+#define __HAL_RCC_GPIOF_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOFRST)
+#define __HAL_RCC_GPIOG_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOGRST)
+#define __HAL_RCC_GPIOH_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOHRST)
+#define __HAL_RCC_GPIOI_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOIRST)
+#define __HAL_RCC_GPIOJ_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOJRST)
+#define __HAL_RCC_GPIOK_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOKRST)
+#if defined(RCC_AHB4RSTR_CRCRST)
+#define __HAL_RCC_CRC_RELEASE_RESET()             (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_CRCRST)
+#endif
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_RELEASE_RESET()            (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_BDMA2RST)
+#define __HAL_RCC_BDMA_RELEASE_RESET()   __HAL_RCC_BDMA2_RELEASE_RESET()      /* for API backward compatibility*/
+#else
+#define __HAL_RCC_BDMA_RELEASE_RESET()            (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_BDMARST)
+#endif /*BDMA2*/
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_RELEASE_RESET()            (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_ADC3RST)
+#endif /*ADC3*/
+#if defined(RCC_AHB4RSTR_HSEMRST)
+#define __HAL_RCC_HSEM_RELEASE_RESET()            (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_HSEMRST)
+#endif
+
+/** @brief  Force or release the APB3 peripheral reset.
+  */
+#define __HAL_RCC_APB3_FORCE_RESET()         (RCC->APB3RSTR = 0xFFFFFFFFU)
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_FORCE_RESET()           (RCC->APB3RSTR) |= (RCC_APB3RSTR_LTDCRST)
+#endif /* LTDC */
+#if defined(DSI)
+#define __HAL_RCC_DSI_FORCE_RESET()            (RCC->APB3RSTR) |= (RCC_APB3RSTR_DSIRST)
+#endif /*DSI*/
+
+#define __HAL_RCC_APB3_RELEASE_RESET()         (RCC->APB3RSTR = 0x00U)
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_RELEASE_RESET()           (RCC->APB3RSTR) &= ~ (RCC_APB3RSTR_LTDCRST)
+#endif /* LTDC */
+#if defined(DSI)
+#define __HAL_RCC_DSI_RELEASE_RESET()            (RCC->APB3RSTR) &= ~ (RCC_APB3RSTR_DSIRST)
+#endif /*DSI*/
+
+/** @brief  Force or release the APB1 peripheral reset.
+  */
+#define __HAL_RCC_APB1L_FORCE_RESET()        (RCC->APB1LRSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_APB1H_FORCE_RESET()        (RCC->APB1HRSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_TIM2_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM2RST)
+#define __HAL_RCC_TIM3_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM3RST)
+#define __HAL_RCC_TIM4_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM4RST)
+#define __HAL_RCC_TIM5_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM5RST)
+#define __HAL_RCC_TIM6_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM6RST)
+#define __HAL_RCC_TIM7_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM7RST)
+#define __HAL_RCC_TIM12_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM12RST)
+#define __HAL_RCC_TIM13_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM13RST)
+#define __HAL_RCC_TIM14_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM14RST)
+#define __HAL_RCC_LPTIM1_FORCE_RESET()         (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_LPTIM1RST)
+#define __HAL_RCC_SPI2_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI2RST)
+#define __HAL_RCC_SPI3_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI3RST)
+#define __HAL_RCC_SPDIFRX_FORCE_RESET()        (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPDIFRXRST)
+#define __HAL_RCC_USART2_FORCE_RESET()         (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART2RST)
+#define __HAL_RCC_USART3_FORCE_RESET()         (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART3RST)
+#define __HAL_RCC_UART4_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART4RST)
+#define __HAL_RCC_UART5_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART5RST)
+#define __HAL_RCC_I2C1_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C1RST)
+#define __HAL_RCC_I2C2_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C2RST)
+#define __HAL_RCC_I2C3_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C3RST)
+#define __HAL_RCC_CEC_FORCE_RESET()            (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_CECRST)
+#define __HAL_RCC_DAC12_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_DAC12RST)
+#define __HAL_RCC_UART7_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART7RST)
+#define __HAL_RCC_UART8_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART8RST)
+#define __HAL_RCC_CRS_FORCE_RESET()            (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_CRSRST)
+#define __HAL_RCC_SWPMI1_FORCE_RESET()          (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_SWPMIRST)
+#define __HAL_RCC_OPAMP_FORCE_RESET()          (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_OPAMPRST)
+#define __HAL_RCC_MDIOS_FORCE_RESET()          (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_MDIOSRST)
+#define __HAL_RCC_FDCAN_FORCE_RESET()          (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_FDCANRST)
+
+#define __HAL_RCC_APB1L_RELEASE_RESET()       (RCC->APB1LRSTR = 0x00U)
+#define __HAL_RCC_APB1H_RELEASE_RESET()       (RCC->APB1HRSTR = 0x00U)
+#define __HAL_RCC_TIM2_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM2RST)
+#define __HAL_RCC_TIM3_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM3RST)
+#define __HAL_RCC_TIM4_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM4RST)
+#define __HAL_RCC_TIM5_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM5RST)
+#define __HAL_RCC_TIM6_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM6RST)
+#define __HAL_RCC_TIM7_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM7RST)
+#define __HAL_RCC_TIM12_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM12RST)
+#define __HAL_RCC_TIM13_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM13RST)
+#define __HAL_RCC_TIM14_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM14RST)
+#define __HAL_RCC_LPTIM1_RELEASE_RESET()         (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_LPTIM1RST)
+#define __HAL_RCC_SPI2_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI2RST)
+#define __HAL_RCC_SPI3_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI3RST)
+#define __HAL_RCC_SPDIFRX_RELEASE_RESET()        (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPDIFRXRST)
+#define __HAL_RCC_USART2_RELEASE_RESET()         (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART2RST)
+#define __HAL_RCC_USART3_RELEASE_RESET()         (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART3RST)
+#define __HAL_RCC_UART4_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART4RST)
+#define __HAL_RCC_UART5_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART5RST)
+#define __HAL_RCC_I2C1_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C1RST)
+#define __HAL_RCC_I2C2_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C2RST)
+#define __HAL_RCC_I2C3_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C3RST)
+#define __HAL_RCC_CEC_RELEASE_RESET()            (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_CECRST)
+#define __HAL_RCC_DAC12_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_DAC12RST)
+#define __HAL_RCC_UART7_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART7RST)
+#define __HAL_RCC_UART8_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART8RST)
+#define __HAL_RCC_CRS_RELEASE_RESET()            (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_CRSRST)
+#define __HAL_RCC_SWPMI1_RELEASE_RESET()          (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_SWPMIRST)
+#define __HAL_RCC_OPAMP_RELEASE_RESET()          (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_OPAMPRST)
+#define __HAL_RCC_MDIOS_RELEASE_RESET()          (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_MDIOSRST)
+#define __HAL_RCC_FDCAN_RELEASE_RESET()          (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_FDCANRST)
+
+/** @brief  Force or release the APB2 peripheral reset.
+  */
+#define __HAL_RCC_APB2_FORCE_RESET()         (RCC->APB2RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_TIM1_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM1RST)
+#define __HAL_RCC_TIM8_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM8RST)
+#define __HAL_RCC_USART1_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART1RST)
+#define __HAL_RCC_USART6_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART6RST)
+#if defined(UART9)
+#define __HAL_RCC_UART9_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_UART9RST)
+#endif /*UART9*/
+#if defined(USART10)
+#define __HAL_RCC_USART10_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART10RST)
+#endif /*USART10*/
+#define __HAL_RCC_SPI1_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI1RST)
+#define __HAL_RCC_SPI4_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI4RST)
+#define __HAL_RCC_TIM15_FORCE_RESET()          (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM15RST)
+#define __HAL_RCC_TIM16_FORCE_RESET()          (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM16RST)
+#define __HAL_RCC_TIM17_FORCE_RESET()          (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM17RST)
+#define __HAL_RCC_SPI5_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI5RST)
+#define __HAL_RCC_SAI1_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI1RST)
+#define __HAL_RCC_SAI2_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI2RST)
+#if defined(SAI3)
+#define __HAL_RCC_SAI3_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI3RST)
+#endif /*SAI3*/
+#define __HAL_RCC_DFSDM1_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_DFSDM1RST)
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_HRTIMRST)
+#endif /*HRTIM1*/
+
+#define __HAL_RCC_APB2_RELEASE_RESET()         (RCC->APB2RSTR = 0x00U)
+#define __HAL_RCC_TIM1_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM1RST)
+#define __HAL_RCC_TIM8_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM8RST)
+#define __HAL_RCC_USART1_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART1RST)
+#define __HAL_RCC_USART6_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART6RST)
+#if defined(UART9)
+#define __HAL_RCC_UART9_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_UART9RST)
+#endif /*UART9*/
+#if defined(USART10)
+#define __HAL_RCC_USART10_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART10RST)
+#endif /*USART10*/
+#define __HAL_RCC_SPI1_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI1RST)
+#define __HAL_RCC_SPI4_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI4RST)
+#define __HAL_RCC_TIM15_RELEASE_RESET()          (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM15RST)
+#define __HAL_RCC_TIM16_RELEASE_RESET()          (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM16RST)
+#define __HAL_RCC_TIM17_RELEASE_RESET()          (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM17RST)
+#define __HAL_RCC_SPI5_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI5RST)
+#define __HAL_RCC_SAI1_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI1RST)
+#define __HAL_RCC_SAI2_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI2RST)
+#if defined(SAI3)
+#define __HAL_RCC_SAI3_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI3RST)
+#endif /*SAI3*/
+#define __HAL_RCC_DFSDM1_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_DFSDM1RST)
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_HRTIMRST)
+#endif /*HRTIM1*/
+
+/** @brief  Force or release the APB4 peripheral reset.
+  */
+
+#define __HAL_RCC_APB4_FORCE_RESET()           (RCC->APB4RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_SYSCFG_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_SYSCFGRST)
+#define __HAL_RCC_LPUART1_FORCE_RESET()          (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPUART1RST)
+#define __HAL_RCC_SPI6_FORCE_RESET()             (RCC->APB4RSTR) |= (RCC_APB4RSTR_SPI6RST)
+#define __HAL_RCC_I2C4_FORCE_RESET()             (RCC->APB4RSTR) |= (RCC_APB4RSTR_I2C4RST)
+#define __HAL_RCC_LPTIM2_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM2RST)
+#define __HAL_RCC_LPTIM3_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM3RST)
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM4RST)
+#endif /*LPTIM4*/
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM5RST)
+#endif /*LPTIM5*/
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_FORCE_RESET()             (RCC->APB4RSTR) |= (RCC_APB4RSTR_DAC2RST)
+#endif /*DAC2*/
+#define __HAL_RCC_COMP12_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_COMP12RST)
+#define __HAL_RCC_VREF_FORCE_RESET()             (RCC->APB4RSTR) |= (RCC_APB4RSTR_VREFRST)
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_FORCE_RESET()             (RCC->APB4RSTR) |= (RCC_APB4RSTR_SAI4RST)
+#endif /*SAI4*/
+#if defined(DTS)
+#define __HAL_RCC_DTS_FORCE_RESET()              (RCC->APB4RSTR) |= (RCC_APB4RSTR_DTSRST)
+#endif /*DTS*/
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_DFSDM2RST)
+#endif /*DFSDM2*/
+
+#define __HAL_RCC_APB4_RELEASE_RESET()           (RCC->APB4RSTR = 0x00U)
+#define __HAL_RCC_SYSCFG_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SYSCFGRST)
+#define __HAL_RCC_LPUART1_RELEASE_RESET()          (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPUART1RST)
+#define __HAL_RCC_SPI6_RELEASE_RESET()             (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SPI6RST)
+#define __HAL_RCC_I2C4_RELEASE_RESET()             (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_I2C4RST)
+#define __HAL_RCC_LPTIM2_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM2RST)
+#define __HAL_RCC_LPTIM3_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM3RST)
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM4RST)
+#endif /*LPTIM4*/
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM5RST)
+#endif /*LPTIM5*/
+#if defined(RCC_APB4RSTR_DAC2RST)
+#define __HAL_RCC_DAC2_RELEASE_RESET()             (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DAC2RST)
+#endif
+#define __HAL_RCC_COMP12_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_COMP12RST)
+#define __HAL_RCC_VREF_RELEASE_RESET()             (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_VREFRST)
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_RELEASE_RESET()             (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SAI4RST)
+#endif /*SAI4*/
+#if defined(DTS)
+#define __HAL_RCC_DTS_RELEASE_RESET()              (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DTSRST)
+#endif /*DTS*/
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DFSDM2RST)
+#endif /*DFSDM2*/
+
+/** @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+
+
+#define __HAL_RCC_MDMA_CLK_SLEEP_ENABLE()            (RCC->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN))
+#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE()           (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN))
+#if defined(JPEG)
+#define __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN))
+#endif /* JPEG */
+#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE()           (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN))
+#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE()             (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE()            (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
+#endif /*QUADSPI*/
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN))
+#if defined(OCTOSPI1)
+#define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OSPI1LPEN))
+#endif /*OCTOSPI1*/
+#if defined(OCTOSPI2)
+#define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OSPI2LPEN))
+#endif /*OCTOSPI2*/
+#if defined(OCTOSPIM)
+#define __HAL_RCC_IOMNGR_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_IOMNGRLPEN))
+#endif /*OCTOSPIM*/
+#if defined(OTFDEC1)
+#define __HAL_RCC_OTFDEC1_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OTFDEC1LPEN))
+#endif /*OTFDEC1*/
+#if defined(OTFDEC2)
+#define __HAL_RCC_OTFDEC2_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OTFDEC2LPEN))
+#endif /*OTFDEC2*/
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_GFXMMULPEN))
+#endif /*GFXMMU*/
+#if defined(CD_AXISRAM2_BASE)
+#define __HAL_RCC_AXISRAM2_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM2LPEN))
+#endif
+#if defined(CD_AXISRAM3_BASE)
+#define __HAL_RCC_AXISRAM3_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM3LPEN))
+#endif
+#define __HAL_RCC_DTCM1_CLK_SLEEP_ENABLE()           (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN))
+#define __HAL_RCC_DTCM2_CLK_SLEEP_ENABLE()           (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN))
+#define __HAL_RCC_ITCM_CLK_SLEEP_ENABLE()            (RCC->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN))
+#if defined(RCC_AHB3LPENR_AXISRAMLPEN)
+#define __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE()         (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN))
+#define __HAL_RCC_AXISRAM_CLK_SLEEP_ENABLE           __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE
+#else
+#define __HAL_RCC_AXISRAM1_CLK_SLEEP_ENABLE()        (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM1LPEN))
+#define __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE           __HAL_RCC_AXISRAM1_CLK_SLEEP_ENABLE  /* For backward compatibility */
+#endif /* RCC_AHB3LPENR_AXISRAMLPEN */
+
+#define __HAL_RCC_MDMA_CLK_SLEEP_DISABLE()            (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN))
+#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN))
+#if defined(JPEG)
+#define __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE()          (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN))
+#endif /* JPEG */
+#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN))
+#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE()             (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN))
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE()            (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN))
+#endif /*QUADSPI*/
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE()          (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN))
+#if defined(OCTOSPI1)
+#define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OSPI1LPEN))
+#endif /*OCTOSPI1*/
+#if defined(OCTOSPI2)
+#define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OSPI2LPEN))
+#endif /*OCTOSPI2*/
+#if defined(OCTOSPIM)
+#define __HAL_RCC_IOMNGR_CLK_SLEEP_DISABLE()          (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_IOMNGRLPEN))
+#endif /*OCTOSPIM*/
+#if defined(OTFDEC1)
+#define __HAL_RCC_OTFDEC1_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OTFDEC1LPEN))
+#endif /*OTFDEC1*/
+#if defined(OTFDEC2)
+#define __HAL_RCC_OTFDEC2_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OTFDEC2LPEN))
+#endif /*OTFDEC2*/
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_GFXMMULPEN))
+#endif /*GFXMMU*/
+#if defined(CD_AXISRAM2_BASE)
+#define __HAL_RCC_AXISRAM2_CLK_SLEEP_DISABLE()         (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM2LPEN))
+#endif
+#if defined(CD_AXISRAM3_BASE)
+#define __HAL_RCC_AXISRAM3_CLK_SLEEP_DISABLE()         (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM3LPEN))
+#endif
+#define __HAL_RCC_DTCM1_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN))
+#define __HAL_RCC_DTCM2_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN))
+#define __HAL_RCC_ITCM_CLK_SLEEP_DISABLE()            (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN))
+#if defined(RCC_AHB3LPENR_AXISRAMLPEN)
+#define __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE()         (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN))
+#define __HAL_RCC_AXISRAM_CLK_SLEEP_DISABLE           __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE
+#else
+#define __HAL_RCC_AXISRAM1_CLK_SLEEP_DISABLE()        (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM1LPEN))
+#define __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE          __HAL_RCC_AXISRAM1_CLK_SLEEP_DISABLE      /* For backward compatibility */
+#endif  /* RCC_AHB3LPENR_AXISRAMLPEN */
+
+/** @brief  Get the enable or disable status of the AHB3 peripheral clock during Low Poser (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+
+#define __HAL_RCC_MDMA_IS_CLK_SLEEP_ENABLED()             ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN)    != 0U)
+#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN)   != 0U)
+#if defined(JPEG)
+#define __HAL_RCC_JPGDEC_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_JPGDECLPEN)  != 0U)
+#endif /* JPEG */
+#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN)   != 0U)
+#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN)     != 0U)
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED()             ((RCC->AHB3LPENR & RCC_AHB3LPENR_QSPILPEN)    != 0U)
+#endif /*QUADSPI*/
+#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN)  != 0U)
+#if defined(OCTOSPI1)
+#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI1LPEN)    != 0U)
+#endif /*OCTOSPI1*/
+#if defined(OCTOSPI2)
+#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI2LPEN)    != 0U)
+#endif /*OCTOSPI2*/
+#if defined(OCTOSPIM)
+#define __HAL_RCC_IOMNGR_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_IOMNGRLPEN)   != 0U)
+#endif /*OCTOSPIM*/
+#if defined(OTFDEC1)
+#define __HAL_RCC_OTFDEC1_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC1LPEN) != 0U)
+#endif /*OTFDEC1*/
+#if defined(OTFDEC2)
+#define __HAL_RCC_OTFDEC2_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC2LPEN) != 0U)
+#endif /*OTFDEC2*/
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_GFXMMULPEN)    != 0U)
+#endif /*GFXMMU*/
+#if defined(CD_AXISRAM2_BASE)
+#define __HAL_RCC_AXISRAM2_IS_CLK_SLEEP_ENABLED()         ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM2LPEN)   != 0U)
+#endif
+#if defined(CD_AXISRAM3_BASE)
+#define __HAL_RCC_AXISRAM3_IS_CLK_SLEEP_ENABLED()         ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM3LPEN)   != 0U)
+#endif
+#define __HAL_RCC_DTCM1_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN)   != 0U)
+#define __HAL_RCC_DTCM2_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN)   != 0U)
+#define __HAL_RCC_ITCM_IS_CLK_SLEEP_ENABLED()             ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN)    != 0U)
+#if defined(RCC_AHB3LPENR_AXISRAMLPEN)
+#define __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_ENABLED()          ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAMLPEN) != 0U)
+#else
+#define __HAL_RCC_AXISRAM1_IS_CLK_SLEEP_ENABLED()         ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM1LPEN) != 0U)
+#endif
+
+#define __HAL_RCC_MDMA_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN)    == 0U)
+#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN)   == 0U)
+#if defined(JPEG)
+#define __HAL_RCC_JPGDEC_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB3LPENR & RCC_AHB3LPENR_JPGDECLPEN)  == 0U)
+#endif /* JPEG */
+#define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN)   == 0U)
+#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN)     == 0U)
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_QSPILPEN)    == 0U)
+#endif /*QUADSPI*/
+#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN)  == 0U)
+#if defined(OCTOSPI1)
+#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI1LPEN)  == 0U)
+#endif /*OCTOSPI1*/
+#if defined(OCTOSPI2)
+#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI2LPEN)  == 0U)
+#endif /*OCTOSPI2*/
+#if defined(OCTOSPIM)
+#define __HAL_RCC_IOMNGR_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_IOMNGRLPEN) == 0U)
+#endif /*OCTOSPIM*/
+#if defined(OTFDEC1)
+#define __HAL_RCC_OTFDEC1_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC1LPEN)  == 0U)
+#endif /*OTFDEC1*/
+#if defined(OTFDEC2)
+#define __HAL_RCC_OTFDEC2_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC2LPEN)  == 0U)
+#endif /*OTFDEC2*/
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_GFXMMULPEN)  == 0U)
+#endif /*GFXMMU*/
+#if defined(CD_AXISRAM2_BASE)
+#define __HAL_RCC_AXISRAM2_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM2LPEN)  == 0U)
+#endif
+#if defined(CD_AXISRAM3_BASE)
+#define __HAL_RCC_AXISRAM3_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM3LPEN)  == 0U)
+#endif
+#define __HAL_RCC_DTCM1_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN)   == 0U)
+#define __HAL_RCC_DTCM2_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN)   == 0U)
+#define __HAL_RCC_ITCM_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN)    == 0U)
+#if defined(RCC_AHB3LPENR_AXISRAMLPEN)
+#define __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAMLPEN) == 0U)
+#else
+#define __HAL_RCC_AXISRAM1_IS_CLK_SLEEP_DISABLED()        ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAML1PEN) == 0U)
+#endif /* RCC_AHB3LPENR_AXISRAMLPEN */
+
+/** @brief  ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE()             (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
+#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE()             (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
+#define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE()            (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN))
+#if defined(RCC_AHB1LPENR_CRCLPEN)
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()              (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
+#endif
+#if defined(ETH)
+#define __HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE()          (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN))
+#endif /*ETH*/
+#if defined(DUAL_CORE)
+#define __HAL_RCC_ART_CLK_SLEEP_ENABLE()              (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ARTLPEN))
+#endif /*DUAL_CORE*/
+#if defined(ETH)
+#define __HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE()           (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN))
+#define __HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE()           (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN))
+#endif /*ETH*/
+#define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN))
+#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
+#if defined(USB2_OTG_FS)
+#define __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN))
+#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
+#endif /* USB2_OTG_FS */
+
+#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE()             (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN))
+#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE()             (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN))
+#define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE()            (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN))
+#if defined(RCC_AHB1LPENR_CRCLPEN)
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()              (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_CRCLPEN))
+#endif
+#if defined(ETH)
+#define __HAL_RCC_ETH1MAC_CLK_SLEEP_DISABLE()          (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN))
+#endif  /*ETH*/
+#if defined(DUAL_CORE)
+#define __HAL_RCC_ART_CLK_SLEEP_DISABLE()              (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ARTLPEN))
+#endif /*DUAL_CORE*/
+#if defined(ETH)
+#define __HAL_RCC_ETH1TX_CLK_SLEEP_DISABLE()           (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN))
+#define __HAL_RCC_ETH1RX_CLK_SLEEP_DISABLE()           (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN))
+#endif  /*ETH*/
+#define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()      (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN))
+#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
+#if defined(USB2_OTG_FS)
+#define __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()      (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN))
+#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
+#endif /* USB2_OTG_FS */
+
+/** @brief  Get the enable or disable status of the AHB1 peripheral clock during Low Poser (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+
+#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN))          != 0U)
+#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN))          != 0U)
+#define __HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED()             ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN))         != 0U)
+#if defined(RCC_AHB1LPENR_CRCLPEN)
+#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED()                ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN))         != 0U)
+#endif
+#if defined(ETH)
+#define __HAL_RCC_ETH1MAC_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1MACLPEN))       != 0U)
+#endif  /*ETH*/
+#if defined(DUAL_CORE)
+#define __HAL_RCC_ART_IS_CLK_SLEEP_ENABLED()               ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ARTLPEN))       != 0U)
+#endif /*DUAL_CORE*/
+#if defined(ETH)
+#define __HAL_RCC_ETH1TX_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1TXLPEN))        != 0U)
+#define __HAL_RCC_ETH1RX_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1RXLPEN))        != 0U)
+#endif  /*ETH*/
+#define __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_ENABLED()       ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN))     != 0U)
+#define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED()  ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) != 0U)
+#if defined(USB2_OTG_FS)
+#define __HAL_RCC_USB2_OTG_FS_IS_CLK_SLEEP_ENABLED()       ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSLPEN))     != 0U)
+#define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_SLEEP_ENABLED()  ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) != 0U)
+#endif /* USB2_OTG_FS */
+
+#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN))          == 0U)
+#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN))          == 0U)
+#define __HAL_RCC_ADC12_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN))         == 0U)
+#if defined(RCC_AHB1LPENR_CRCLPEN)
+#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED()              ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN))           == 0U)
+#endif
+#if defined(ETH)
+#define __HAL_RCC_ETH1MAC_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1MACLPEN))       == 0U)
+#endif /* ETH */
+#if defined(DUAL_CORE)
+#define __HAL_RCC_ART_IS_CLK_SLEEP_DISABLED()              ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ARTLPEN))           == 0U)
+#endif /*DUAL_CORE*/
+#if defined(ETH)
+#define __HAL_RCC_ETH1TX_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1TXLPEN))        == 0U)
+#define __HAL_RCC_ETH1RX_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1RXLPEN))        == 0U)
+#endif /* ETH */
+#define __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_DISABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN))     == 0U)
+#define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) == 0U)
+#if defined(USB2_OTG_FS)
+#define __HAL_RCC_USB2_OTG_FS_IS_CLK_SLEEP_DISABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSLPEN))     == 0U)
+#define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) == 0U)
+#endif /* USB2_OTG_FS */
+
+
+/** @brief  ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#if defined(DCMI) && defined(PSSI)
+#define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE()        (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMI_PSSILPEN))
+#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE()             __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE()             (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
+#endif /* DCMI && PSSI */
+#if defined(CRYP)
+#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE()             (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE()             (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
+#endif /* HASH */
+#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()              (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
+#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE()           (RCC->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))
+#if defined(RCC_AHB2LPENR_DFSDMDMALPEN)
+#define __HAL_RCC_DFSDMDMA_CLK_SLEEP_ENABLE()         (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DFSDMDMALPEN))
+#endif
+#if defined(RCC_AHB2LPENR_D2SRAM1LPEN)
+#define __HAL_RCC_D2SRAM1_CLK_SLEEP_ENABLE()          (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN))
+#else
+#define __HAL_RCC_AHBSRAM1_CLK_SLEEP_ENABLE()         (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AHBSRAM1LPEN))
+#endif /* RCC_AHB2LPENR_D2SRAM1LPEN */
+#if defined(RCC_AHB2LPENR_D2SRAM2LPEN)
+#define __HAL_RCC_D2SRAM2_CLK_SLEEP_ENABLE()          (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN))
+#else
+#define __HAL_RCC_AHBSRAM2_CLK_SLEEP_ENABLE()         (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AHBSRAM2LPEN))
+#endif /* RCC_AHB2LPENR_D2SRAM2LPEN */
+#if defined(RCC_AHB2LPENR_D2SRAM3LPEN)
+#define __HAL_RCC_D2SRAM3_CLK_SLEEP_ENABLE()          (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN))
+#endif
+
+#if defined(DCMI) && defined(PSSI)
+#define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE()        (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMI_PSSILPEN))
+#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE()             __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE()             (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))
+#endif /* DCMI && PSSI */
+#if defined(CRYP)
+#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE()             (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE()             (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))
+#endif /* HASH */
+#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()              (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))
+#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE()           (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))
+#if defined(RCC_AHB2LPENR_DFSDMDMALPEN)
+#define __HAL_RCC_DFSDMDMA_CLK_SLEEP_DISABLE()         (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DFSDMDMALPEN))
+#endif
+#if defined(RCC_AHB2LPENR_D2SRAM1LPEN)
+#define __HAL_RCC_D2SRAM1_CLK_SLEEP_DISABLE()          (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN))
+#else
+#define __HAL_RCC_AHBSRAM1_CLK_SLEEP_DISABLE()         (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_AHBSRAM1LPEN))
+#endif /* RCC_AHB2LPENR_D2SRAM1LPEN */
+#if defined(RCC_AHB2LPENR_D2SRAM2LPEN)
+#define __HAL_RCC_D2SRAM2_CLK_SLEEP_DISABLE()          (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN))
+#else
+#define __HAL_RCC_AHBSRAM2_CLK_SLEEP_DISABLE()          (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_AHBSRAM2LPEN))
+#endif /* RCC_AHB2LPENR_D2SRAM2LPEN */
+#if defined(RCC_AHB2LPENR_D2SRAM3LPEN)
+#define __HAL_RCC_D2SRAM3_CLK_SLEEP_DISABLE()          (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN))
+#endif
+
+/** @brief  Get the enable or disable status of the AHB2 peripheral clock during Low Poser (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+
+#if defined(DCMI) && defined(PSSI)
+#define __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_ENABLED()         ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMI_PSSILPEN))    != 0U)
+#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED()              __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_ENABLED()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN))    != 0U)
+#endif /* DCMI && PSSI */
+#if defined(CRYP)
+#define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN))    != 0U)
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN))    != 0U)
+#endif /* HASH */
+#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED()               ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN))     != 0U)
+#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN))  != 0U)
+#if defined(RCC_AHB2LPENR_DFSDMDMALPEN)
+#define __HAL_RCC_DFSDMDMA_IS_CLK_SLEEP_ENABLED()          ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DFSDMDMALPEN)) != 0U)
+#endif
+#if defined(RCC_AHB2LPENR_D2SRAM1LPEN)
+#define __HAL_RCC_D2SRAM1_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM1LPEN)) != 0U)
+#else
+#define __HAL_RCC_AHBSRAM1_IS_CLK_SLEEP_ENABLED()          ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM1LPEN)) != 0U)
+#endif /* RCC_AHB2LPENR_D2SRAM1LPEN */
+#if defined(RCC_AHB2LPENR_D2SRAM2LPEN)
+#define __HAL_RCC_D2SRAM2_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM2LPEN)) != 0U)
+#else
+#define __HAL_RCC_AHBSRAM2_IS_CLK_SLEEP_ENABLED()          ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM2LPEN)) != 0U)
+#endif /* RCC_AHB2LPENR_D2SRAM2LPEN */
+#if defined(RCC_AHB2LPENR_D2SRAM3LPEN)
+#define __HAL_RCC_D2SRAM3_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM3LPEN)) != 0U)
+#endif /* RCC_AHB2LPENR_D2SRAM3LPEN */
+
+#if defined(DCMI) && defined(PSSI)
+#define __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_DISABLED()        ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMI_PSSILPEN))    == 0U)
+#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED()             __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_DISABLED()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN))    == 0U)
+#endif /* DCMI && PSSI */
+#if defined(CRYP)
+#define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN))    == 0U)
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN))    == 0U)
+#endif /* HASH */
+#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED()              ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN))     == 0U)
+#if defined(RCC_AHB2LPENR_DFSDMDMALPEN)
+#define __HAL_RCC_DFSDMDMA_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DFSDMDMALPEN)) == 0U)
+#endif
+#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN))  == 0U)
+#if defined(RCC_AHB2LPENR_D2SRAM1LPEN)
+#define __HAL_RCC_D2SRAM1_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM1LPEN)) == 0U)
+#else
+#define __HAL_RCC_AHBSRAM1_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM1LPEN)) == 0U)
+#endif /* RCC_AHB2LPENR_D2SRAM1LPEN */
+#if defined(RCC_AHB2LPENR_D2SRAM2LPEN)
+#define __HAL_RCC_D2SRAM2_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM2LPEN)) == 0U)
+#else
+#define __HAL_RCC_AHBSRAM2_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM2LPEN)) == 0U)
+#endif /* RCC_AHB2LPENR_D2SRAM2LPEN */
+#if defined(RCC_AHB2LPENR_D2SRAM3LPEN)
+#define __HAL_RCC_D2SRAM3_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM3LPEN)) == 0U)
+#endif /* RCC_AHB2LPENR_D2SRAM1LPEN*/
+
+
+/** @brief  ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN)
+#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN)
+#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN)
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN)
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN)
+#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN)
+#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN)
+#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN)
+#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN)
+#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN)
+#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN)
+#if defined(RCC_AHB4LPENR_CRCLPEN)
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()             (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN)
+#endif
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_CLK_SLEEP_ENABLE()            (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BDMA2LPEN)
+#define __HAL_RCC_BDMA_CLK_SLEEP_ENABLE  __HAL_RCC_BDMA2_CLK_SLEEP_ENABLE /* for API backward compatibility*/
+#else
+#define __HAL_RCC_BDMA_CLK_SLEEP_ENABLE()            (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN)
+#endif /* BDMA2 */
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE()            (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN)
+#endif /* ADC3 */
+#define __HAL_RCC_BKPRAM_CLK_SLEEP_ENABLE()          (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN)
+#if defined(RCC_AHB4LPENR_SRDSRAMLPEN)
+#define __HAL_RCC_SRDSRAM_CLK_SLEEP_ENABLE()         (RCC->AHB4LPENR  |= (RCC_AHB4LPENR_SRDSRAMLPEN))
+#define __HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE  __HAL_RCC_SRDSRAM_CLK_SLEEP_ENABLE /* for API backward compatibility*/
+#else
+#define __HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE()         (RCC->AHB4LPENR  |= (RCC_AHB4LPENR_D3SRAM1LPEN))
+#endif /* RCC_AHB4LPENR_SRDSRAMLPEN */
+
+#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN)
+#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN)
+#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN)
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN)
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN)
+#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN)
+#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN)
+#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN)
+#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN)
+#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN)
+#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN)
+#if defined(RCC_AHB4LPENR_CRCLPEN)
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()             (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN)
+#endif
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_CLK_SLEEP_DISABLE()            (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMA2LPEN)
+#define __HAL_RCC_BDMA_CLK_SLEEP_DISABLE  __HAL_RCC_BDMA2_CLK_SLEEP_DISABLE  /* For API backward compatibility*/
+#else
+#define __HAL_RCC_BDMA_CLK_SLEEP_DISABLE()            (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN)
+#endif /*BDMA2*/
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE()            (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN)
+#endif /*ADC3*/
+#define __HAL_RCC_BKPRAM_CLK_SLEEP_DISABLE()          (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN)
+#if defined(RCC_AHB4LPENR_SRDSRAMLPEN)
+#define __HAL_RCC_SRDSRAM_CLK_SLEEP_DISABLE()         (RCC->AHB4LPENR  &= ~ (RCC_AHB4LPENR_SRDSRAMLPEN))
+#define __HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE  __HAL_RCC_SRDSRAM_CLK_SLEEP_DISABLE
+#else
+#define __HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE()         (RCC->AHB4LPENR  &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN))
+#endif
+
+
+/** @brief  Get the enable or disable status of the AHB4 peripheral clock during Low Poser (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+
+#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN))   != 0U)
+#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN))   != 0U)
+#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN))   != 0U)
+#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN))   != 0U)
+#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN))   != 0U)
+#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN))   != 0U)
+#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN))   != 0U)
+#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN))   != 0U)
+#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN))   != 0U)
+#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN))   != 0U)
+#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN))   != 0U)
+#if defined(RCC_AHB4LPENR_CRCLPEN)
+#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB4LPENR & (RCC_AHB4LPENR_CRCLPEN))     != 0U)
+#endif
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMA2LPEN))    != 0U)
+#define __HAL_RCC_BDMA_IS_CLK_SLEEP_ENABLED __HAL_RCC_BDMA2_IS_CLK_SLEEP_ENABLED  /* For API backward compatibility*/
+#else
+#define __HAL_RCC_BDMA_IS_CLK_SLEEP_ENABLED()             ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMALPEN))    != 0U)
+#endif /*BDMA2*/
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED()             ((RCC->AHB4LPENR & (RCC_AHB4LPENR_ADC3LPEN))    != 0U)
+#endif /*ADC3*/
+#define __HAL_RCC_BKPRAM_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN))  != 0U)
+#if defined(RCC_AHB4LPENR_SRDSRAMLPEN)
+#define __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_ENABLED()          ((RCC->AHB4LPENR & (RCC_AHB4LPENR_SRDSRAMLPEN)) != 0U)
+#define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_ENABLED  __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_ENABLED  /* For API backward compatibility*/
+#else
+#define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_ENABLED()          ((RCC->AHB4LPENR & (RCC_AHB4LPENR_D3SRAM1LPEN)) != 0U)
+#endif
+
+#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN))   == 0U)
+#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN))   == 0U)
+#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN))   == 0U)
+#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN))   == 0U)
+#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN))   == 0U)
+#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN))   == 0U)
+#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN))   == 0U)
+#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN))   == 0U)
+#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN))   == 0U)
+#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN))   == 0U)
+#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN))   == 0U)
+#if defined(RCC_AHB4LPENR_CRCLPEN)
+#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB4LPENR & (RCC_AHB4LPENR_CRCLPEN))     == 0U)
+#endif
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMA2LPEN))  == 0U)
+#define __HAL_RCC_BDMA_IS_CLK_SLEEP_DISABLED __HAL_RCC_BDMA2_IS_CLK_SLEEP_DISABLED  /* For API backward compatibility*/
+#else
+#define __HAL_RCC_BDMA_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMALPEN))    == 0U)
+#endif /*BDMA2*/
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_ADC3LPEN))    == 0U)
+#endif /*ADC3*/
+#define __HAL_RCC_BKPRAM_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN))  == 0U)
+#if defined(RCC_AHB4LPENR_SRDSRAMLPEN)
+#define __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB4LPENR & (RCC_AHB4LPENR_SRDSRAMLPEN)) == 0U)
+#define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_DISABLED  __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_DISABLED  /* For API backward compatibility*/
+#else
+#define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB4LPENR & (RCC_AHB4LPENR_D3SRAM1LPEN)) == 0U)
+#endif
+
+
+/** @brief  ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE()           (RCC->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN)
+#endif /* LTDC */
+#if defined(DSI)
+#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE()            (RCC->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN)
+#endif /*DSI*/
+#define __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE()          (RCC->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN)
+
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE()           (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN)
+#endif /* LTDC */
+#if defined(DSI)
+#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE()            (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN)
+#endif /*DSI*/
+#define __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE()          (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN)
+
+
+/** @brief  Get the enable or disable status of the APB3 peripheral clock during Low Poser (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED()            ((RCC->APB3LPENR & (RCC_APB3LPENR_LTDCLPEN))  != 0U)
+#endif /* LTDC */
+#if defined(DSI)
+#define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED()             ((RCC->APB3LPENR & (RCC_APB3LPENR_DSILPEN))   != 0U)
+#endif /*DSI*/
+#define __HAL_RCC_WWDG1_IS_CLK_SLEEP_ENABLED()           ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) != 0U)
+
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED()           ((RCC->APB3LPENR & (RCC_APB3LPENR_LTDCLPEN))  == 0U)
+#endif /* LTDC */
+#if defined(DSI)
+#define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED()            ((RCC->APB3LPENR & (RCC_APB3LPENR_DSILPEN))   == 0U)
+#endif /*DSI*/
+#define __HAL_RCC_WWDG1_IS_CLK_SLEEP_DISABLED()          ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) == 0U)
+
+
+/** @brief  ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN)
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN)
+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN)
+#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN)
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN)
+#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN)
+#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN)
+#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN)
+#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN)
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE()         (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN)
+
+#if defined(DUAL_CORE)
+#define __HAL_RCC_WWDG2_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN)
+#endif /*DUAL_CORE*/
+
+#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN)
+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN)
+#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE()        (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN)
+#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE()         (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN)
+#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()         (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN)
+#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN)
+#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN)
+#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN)
+#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN)
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN)
+#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE()            (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN)
+#define __HAL_RCC_DAC12_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN)
+#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN)
+#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN)
+#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE()            (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN)
+#define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE()          (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN)
+#define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE()          (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN)
+#define __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE()          (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN)
+#define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE()          (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN)
+
+
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN)
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN)
+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN)
+#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN)
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN)
+#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN)
+#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN)
+#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN)
+#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN)
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE()         (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN)
+
+#if defined(DUAL_CORE)
+#define __HAL_RCC_WWDG2_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN)
+#endif /*DUAL_CORE*/
+
+#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN)
+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN)
+#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()        (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN)
+#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE()         (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN)
+#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE()         (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN)
+#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN)
+#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN)
+#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN)
+#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN)
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN)
+#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE()            (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN)
+#define __HAL_RCC_DAC12_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN)
+#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN)
+#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN)
+#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE()            (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN)
+#define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE()          (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN)
+#define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE()          (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN)
+#define __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE()          (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN)
+#define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE()          (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN)
+
+
+/** @brief  Get the enable or disable status of the APB1 peripheral clock during Low Poser (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+
+#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN))    != 0U)
+#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN))    != 0U)
+#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN))    != 0U)
+#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN))    != 0U)
+#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN))    != 0U)
+#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN))    != 0U)
+#define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN))   != 0U)
+#define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN))   != 0U)
+#define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN))   != 0U)
+#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN))  != 0U)
+#if defined(DUAL_CORE)
+#define __HAL_RCC_WWDG2_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_WWDG2LPEN))   != 0U)
+#endif /*DUAL_CORE*/
+#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN))    != 0U)
+#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN))    != 0U)
+#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED()         ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) != 0U)
+#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN))  != 0U)
+#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN))  != 0U)
+#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN))   != 0U)
+#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN))   != 0U)
+#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN))    != 0U)
+#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN))    != 0U)
+#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN))    != 0U)
+#define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED()             ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN))     != 0U)
+#define __HAL_RCC_DAC12_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN))   != 0U)
+#define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN))   != 0U)
+#define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN))   != 0U)
+#define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED()             ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN))     != 0U)
+#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED()          ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN))   != 0U)
+#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN))   != 0U)
+#define __HAL_RCC_MDIOS_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN))   != 0U)
+#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN))   != 0U)
+
+#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN))    == 0U)
+#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN))    == 0U)
+#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN))    == 0U)
+#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN))    == 0U)
+#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN))    == 0U)
+#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN))    == 0U)
+#define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN))   == 0U)
+#define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN))   == 0U)
+#define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN))   == 0U)
+#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED()         ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN))  == 0U)
+#if defined(DUAL_CORE)
+#define __HAL_RCC_WWDG2_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_WWDG2LPEN))   == 0U)
+#endif /*DUAL_CORE*/
+#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN))    == 0U)
+#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN))    == 0U)
+#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED()        ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) == 0U)
+#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED()         ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN))  == 0U)
+#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED()         ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN))  == 0U)
+#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN))   == 0U)
+#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN))   == 0U)
+#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN))    == 0U)
+#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN))    == 0U)
+#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN))    == 0U)
+#define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN))     == 0U)
+#define __HAL_RCC_DAC12_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN))   == 0U)
+#define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN))   == 0U)
+#define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN))   == 0U)
+#define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED()            ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN))     == 0U)
+#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED()         ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN))   == 0U)
+#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN))   == 0U)
+#define __HAL_RCC_MDIOS_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN))   == 0U)
+#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN))   == 0U)
+
+
+/** @brief  ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN)
+#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN)
+#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE()         (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN)
+#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE()         (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN)
+#if defined(UART9)
+#define __HAL_RCC_UART9_CLK_SLEEP_ENABLE()          (RCC->APB2LPENR) |= (RCC_APB2LPENR_UART9LPEN)
+#endif /*UART9*/
+#if defined(USART10)
+#define __HAL_RCC_USART10_CLK_SLEEP_ENABLE()        (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART10LPEN)
+#endif /*USART10*/
+#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN)
+#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN)
+#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE()          (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN)
+#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE()          (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN)
+#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE()          (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN)
+#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN)
+#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN)
+#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN)
+#if defined(SAI3)
+#define __HAL_RCC_SAI3_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN)
+#endif /*SAI3*/
+#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE()         (RCC->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN)
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_CLK_SLEEP_ENABLE()         (RCC->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN)
+#endif /*HRTIM1*/
+
+#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN)
+#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN)
+#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE()         (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN)
+#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE()         (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN)
+#if defined(UART9)
+#define __HAL_RCC_UART9_CLK_SLEEP_DISABLE()          (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_UART9LPEN)
+#endif /*UART9*/
+#if defined(USART10)
+#define __HAL_RCC_USART10_CLK_SLEEP_DISABLE()         (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART10LPEN)
+#endif /*USART10*/
+#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN)
+#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN)
+#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE()          (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN)
+#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE()          (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN)
+#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE()          (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN)
+#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN)
+#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN)
+#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN)
+#if defined(SAI3)
+#define __HAL_RCC_SAI3_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN)
+#endif /*SAI3*/
+#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE()         (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN)
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_CLK_SLEEP_DISABLE()         (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN)
+#endif /*HRTIM1*/
+
+
+/** @brief  Get the enable or disable status of the APB2 peripheral clock during Low Poser (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+
+#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN))   != 0U)
+#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN))   != 0U)
+#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != 0U)
+#define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != 0U)
+#if defined(UART9)
+#define __HAL_RCC_UART9_IS_CLK_SLEEP_ENABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_UART9LPEN)) != 0U)
+#endif /*UART9*/
+#if defined(USART10)
+#define __HAL_RCC_USART10_IS_CLK_SLEEP_ENABLED()         ((RCC->APB2LPENR & (RCC_APB2LPENR_USART10LPEN)) != 0U)
+#endif /*USART10*/
+#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN))   != 0U)
+#define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN))   != 0U)
+#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN))  != 0U)
+#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN))  != 0U)
+#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN))  != 0U)
+#define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN))   != 0U)
+#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN))   != 0U)
+#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN))   != 0U)
+#if defined(SAI3)
+#define __HAL_RCC_SAI3_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI3LPEN))   != 0U)
+#endif /*SAI3*/
+#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != 0U)
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_ENABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_HRTIMLPEN))  != 0U)
+#endif /*HRTIM1*/
+
+#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN))   == 0U)
+#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN))   == 0U)
+#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED()         ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == 0U)
+#define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED()         ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == 0U)
+#if defined(UART9)
+#define __HAL_RCC_USART9_IS_CLK_SLEEP_DISABLED()         ((RCC->APB2LPENR & (RCC_APB2LPENR_USART9LPEN)) == 0U)
+#endif /*UART9*/
+#if defined(USART10)
+#define __HAL_RCC_USART10_IS_CLK_SLEEP_DISABLED()        ((RCC->APB2LPENR & (RCC_APB2LPENR_USART10LPEN)) == 0U)
+#endif /*USART10*/
+#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN))   == 0U)
+#define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN))   == 0U)
+#define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN))  == 0U)
+#define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN))  == 0U)
+#define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN))  == 0U)
+#define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN))   == 0U)
+#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN))   == 0U)
+#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN))   == 0U)
+#if defined(SAI3)
+#define __HAL_RCC_SAI3_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI3LPEN))   == 0U)
+#endif /*SAI3*/
+#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED()         ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == 0U)
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_DISABLED()         ((RCC->APB2LPENR & (RCC_APB2LPENR_HRTIMLPEN))  == 0U)
+#endif /*HRTIM1*/
+
+/** @brief  ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN)
+#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE()          (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN)
+#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE()             (RCC->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN)
+#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE()             (RCC->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN)
+#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN)
+#define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN)
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN)
+#endif /*LPTIM4*/
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN)
+#endif /*LPTIM5*/
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_DAC2LPEN)
+#endif /*DAC2*/
+#define __HAL_RCC_COMP12_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN)
+#define __HAL_RCC_VREF_CLK_SLEEP_ENABLE()             (RCC->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN)
+#define __HAL_RCC_RTC_CLK_SLEEP_ENABLE()              (RCC->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN)
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_CLK_SLEEP_ENABLE()             (RCC->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN)
+#endif /*SAI4*/
+#if defined(DTS)
+#define __HAL_RCC_DTS_CLK_SLEEP_ENABLE()              (RCC->APB4LPENR) |= (RCC_APB4LPENR_DTSLPEN)
+#endif /*DTS*/
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_DFSDM2LPEN)
+#endif /*DFSDM2*/
+
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN)
+#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE()          (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN)
+#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE()             (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN)
+#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE()             (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN)
+#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN)
+#define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN)
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN)
+#endif /*LPTIM4*/
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN)
+#endif /*LPTIM5*/
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_CLK_SLEEP_DISABLE()             (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DAC2LPEN)
+#endif /*DAC2*/
+#define __HAL_RCC_COMP12_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN)
+#define __HAL_RCC_VREF_CLK_SLEEP_DISABLE()             (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN)
+#define __HAL_RCC_RTC_CLK_SLEEP_DISABLE()              (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN)
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_CLK_SLEEP_DISABLE()             (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN)
+#endif /*SAI4*/
+#if defined(DTS)
+#define __HAL_RCC_DTS_CLK_SLEEP_DISABLE()              (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DTSLPEN)
+#endif /*DTS*/
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_CLK_SLEEP_DISABLE()          (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DFSDM2LPEN)
+#endif /*DFSDM2*/
+
+
+/** @brief  Get the enable or disable status of the APB4 peripheral clock during Low Poser (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+
+#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN))  != 0U)
+#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) != 0U)
+#define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN))    != 0U)
+#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN))    != 0U)
+#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN))  != 0U)
+#define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN))  != 0U)
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM4LPEN))  != 0U)
+#endif /*LPTIM4*/
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM5LPEN))  != 0U)
+#endif /*LPTIM5*/
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_IS_CLK_SLEEP_ENABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_DAC2LPEN))  != 0U)
+#endif /*DAC2*/
+#define __HAL_RCC_COMP12_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN))  != 0U)
+#define __HAL_RCC_VREF_IS_CLK_SLEEP_ENABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN))    != 0U)
+#define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED()               ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN))  != 0U)
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_IS_CLK_SLEEP_ENABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_SAI4LPEN))    != 0U)
+#endif /*SAI4*/
+#if defined(DTS)
+#define __HAL_RCC_DTS_IS_CLK_SLEEP_ENABLED()               ((RCC->APB4LPENR & (RCC_APB4LPENR_DTSLPEN))    != 0U)
+#endif /*DTS*/
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_DFSDM2LPEN)) != 0U)
+#endif /*DFSDM2*/
+
+#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN))  == 0U)
+#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED()          ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) == 0U)
+#define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED()             ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN))    == 0U)
+#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED()             ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN))    == 0U)
+#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN))  == 0U)
+#define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN))  == 0U)
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM4LPEN))  == 0U)
+#endif /*LPTIM4*/
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM5LPEN))  == 0U)
+#endif /*LPTIM5*/
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_IS_CLK_SLEEP_DISABLED()             ((RCC->APB4LPENR & (RCC_APB4LPENR_DAC2LPEN))  == 0U)
+#endif /*DAC2*/
+#define __HAL_RCC_COMP12_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN))  == 0U)
+#define __HAL_RCC_VREF_IS_CLK_SLEEP_DISABLED()             ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN))    == 0U)
+#define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN))  == 0U)
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_IS_CLK_SLEEP_DISABLED()             ((RCC->APB4LPENR & (RCC_APB4LPENR_SAI4LPEN))    == 0U)
+#endif /*SAI4*/
+#if defined(DTS)
+#define __HAL_RCC_DTS_IS_CLK_SLEEP_DISABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_DTSLPEN))    == 0U)
+#endif /*DTS*/
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_DFSDM2LPEN)) == 0U)
+#endif /*DFSDM2*/
+
+
+#if defined(DUAL_CORE)
+
+/** @brief  Enable or disable the RCC_C1 AHB3 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+#define __HAL_RCC_C1_MDMA_CLK_SLEEP_ENABLE()            (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN))
+#define __HAL_RCC_C1_DMA2D_CLK_SLEEP_ENABLE()           (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN))
+#define __HAL_RCC_C1_JPGDEC_CLK_SLEEP_ENABLE()          (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN))
+#define __HAL_RCC_C1_FLASH_CLK_SLEEP_ENABLE()           (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN))
+#define __HAL_RCC_C1_FMC_CLK_SLEEP_ENABLE()             (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
+#define __HAL_RCC_C1_QSPI_CLK_SLEEP_ENABLE()            (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
+#define __HAL_RCC_C1_SDMMC1_CLK_SLEEP_ENABLE()          (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN))
+#define __HAL_RCC_C1_DTCM1_CLK_SLEEP_ENABLE()           (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN))
+#define __HAL_RCC_C1_DTCM2_CLK_SLEEP_ENABLE()           (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN))
+#define __HAL_RCC_C1_ITCM_CLK_SLEEP_ENABLE()            (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN))
+#define __HAL_RCC_C1_D1SRAM1_CLK_SLEEP_ENABLE()         (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN))
+
+
+#define __HAL_RCC_C1_MDMA_CLK_SLEEP_DISABLE()            (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN))
+#define __HAL_RCC_C1_DMA2D_CLK_SLEEP_DISABLE()           (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN))
+#define __HAL_RCC_C1_JPGDEC_CLK_SLEEP_DISABLE()          (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN))
+#define __HAL_RCC_C1_FLASH_CLK_SLEEP_DISABLE()           (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN))
+#define __HAL_RCC_C1_FMC_CLK_SLEEP_DISABLE()             (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN))
+#define __HAL_RCC_C1_QSPI_CLK_SLEEP_DISABLE()            (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN))
+#define __HAL_RCC_C1_SDMMC1_CLK_SLEEP_DISABLE()          (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN))
+#define __HAL_RCC_C1_DTCM1_CLK_SLEEP_DISABLE()           (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN))
+#define __HAL_RCC_C1_DTCM2_CLK_SLEEP_DISABLE()           (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN))
+#define __HAL_RCC_C1_ITCM_CLK_SLEEP_DISABLE()            (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN))
+#define __HAL_RCC_C1_D1SRAM1_CLK_SLEEP_DISABLE()         (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN))
+
+
+
+/** @brief  ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C1_DMA1_CLK_SLEEP_ENABLE()             (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
+#define __HAL_RCC_C1_DMA2_CLK_SLEEP_ENABLE()             (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
+#define __HAL_RCC_C1_ADC12_CLK_SLEEP_ENABLE()            (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN))
+#define __HAL_RCC_C1_ETH1MAC_CLK_SLEEP_ENABLE()          (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN))
+#define __HAL_RCC_C1_ETH1TX_CLK_SLEEP_ENABLE()           (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN))
+#define __HAL_RCC_C1_ETH1RX_CLK_SLEEP_ENABLE()           (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN))
+#define __HAL_RCC_C1_USB1_OTG_HS_CLK_SLEEP_ENABLE()      (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN))
+#define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
+#define __HAL_RCC_C1_USB2_OTG_FS_CLK_SLEEP_ENABLE()      (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN))
+#define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
+
+#define __HAL_RCC_C1_DMA1_CLK_SLEEP_DISABLE()             (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN))
+#define __HAL_RCC_C1_DMA2_CLK_SLEEP_DISABLE()             (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN))
+#define __HAL_RCC_C1_ADC12_CLK_SLEEP_DISABLE()            (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN))
+#define __HAL_RCC_C1_ETH1MAC_CLK_SLEEP_DISABLE()          (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN))
+#define __HAL_RCC_C1_ETH1TX_CLK_SLEEP_DISABLE()           (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN))
+#define __HAL_RCC_C1_ETH1RX_CLK_SLEEP_DISABLE()           (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN))
+#define __HAL_RCC_C1_USB1_OTG_HS_CLK_SLEEP_DISABLE()      (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN))
+#define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
+#define __HAL_RCC_C1_USB2_OTG_FS_CLK_SLEEP_DISABLE()      (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN))
+#define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
+
+/** @brief  ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C1_DCMI_CLK_SLEEP_ENABLE()             (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
+#if defined(CRYP)
+#define __HAL_RCC_C1_CRYP_CLK_SLEEP_ENABLE()             (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_C1_HASH_CLK_SLEEP_ENABLE()             (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
+#endif /* HASH */
+#define __HAL_RCC_C1_RNG_CLK_SLEEP_ENABLE()              (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
+#define __HAL_RCC_C1_SDMMC2_CLK_SLEEP_ENABLE()           (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))
+#define __HAL_RCC_C1_D2SRAM1_CLK_SLEEP_ENABLE()          (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN))
+#define __HAL_RCC_C1_D2SRAM2_CLK_SLEEP_ENABLE()          (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN))
+#define __HAL_RCC_C1_D2SRAM3_CLK_SLEEP_ENABLE()          (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN))
+
+#define __HAL_RCC_C1_DCMI_CLK_SLEEP_DISABLE()             (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))
+#if defined(CRYP)
+#define __HAL_RCC_C1_CRYP_CLK_SLEEP_DISABLE()             (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_C1_HASH_CLK_SLEEP_DISABLE()             (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))
+#endif /* HASH */
+#define __HAL_RCC_C1_RNG_CLK_SLEEP_DISABLE()              (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))
+#define __HAL_RCC_C1_SDMMC2_CLK_SLEEP_DISABLE()           (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))
+#define __HAL_RCC_C1_D2SRAM1_CLK_SLEEP_DISABLE()          (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN))
+#define __HAL_RCC_C1_D2SRAM2_CLK_SLEEP_DISABLE()          (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN))
+#define __HAL_RCC_C1_D2SRAM3_CLK_SLEEP_DISABLE()          (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN))
+
+/** @brief  ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C1_GPIOA_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN)
+#define __HAL_RCC_C1_GPIOB_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN)
+#define __HAL_RCC_C1_GPIOC_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN)
+#define __HAL_RCC_C1_GPIOD_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN)
+#define __HAL_RCC_C1_GPIOE_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN)
+#define __HAL_RCC_C1_GPIOF_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN)
+#define __HAL_RCC_C1_GPIOG_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN)
+#define __HAL_RCC_C1_GPIOH_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN)
+#define __HAL_RCC_C1_GPIOI_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN)
+#define __HAL_RCC_C1_GPIOJ_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN)
+#define __HAL_RCC_C1_GPIOK_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN)
+#define __HAL_RCC_C1_CRC_CLK_SLEEP_ENABLE()             (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN)
+#define __HAL_RCC_C1_BDMA_CLK_SLEEP_ENABLE()            (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN)
+#define __HAL_RCC_C1_ADC3_CLK_SLEEP_ENABLE()            (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN)
+#define __HAL_RCC_C1_BKPRAM_CLK_SLEEP_ENABLE()          (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN)
+#define __HAL_RCC_C1_D3SRAM1_CLK_SLEEP_ENABLE()         (RCC_C1->AHB4LPENR  |= (RCC_AHB4LPENR_D3SRAM1LPEN))
+
+#define __HAL_RCC_C1_GPIOA_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN)
+#define __HAL_RCC_C1_GPIOB_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN)
+#define __HAL_RCC_C1_GPIOC_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN)
+#define __HAL_RCC_C1_GPIOD_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN)
+#define __HAL_RCC_C1_GPIOE_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN)
+#define __HAL_RCC_C1_GPIOF_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN)
+#define __HAL_RCC_C1_GPIOG_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN)
+#define __HAL_RCC_C1_GPIOH_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN)
+#define __HAL_RCC_C1_GPIOI_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN)
+#define __HAL_RCC_C1_GPIOJ_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN)
+#define __HAL_RCC_C1_GPIOK_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN)
+#define __HAL_RCC_C1_CRC_CLK_SLEEP_DISABLE()             (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN)
+#define __HAL_RCC_C1_BDMA_CLK_SLEEP_DISABLE()            (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN)
+#define __HAL_RCC_C1_ADC3_CLK_SLEEP_DISABLE()            (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN)
+#define __HAL_RCC_C1_BKPRAM_CLK_SLEEP_DISABLE()          (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN)
+#define __HAL_RCC_C1_D3SRAM1_CLK_SLEEP_DISABLE()         (RCC_C1->AHB4LPENR  &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN))
+
+/** @brief  ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C1_LTDC_CLK_SLEEP_ENABLE()           (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN)
+#define __HAL_RCC_C1_DSI_CLK_SLEEP_ENABLE()            (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN)
+#define __HAL_RCC_C1_WWDG1_CLK_SLEEP_ENABLE()          (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN)
+
+#define __HAL_RCC_C1_LTDC_CLK_SLEEP_DISABLE()           (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN)
+#define __HAL_RCC_C1_DSI_CLK_SLEEP_DISABLE()            (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN)
+#define __HAL_RCC_C1_WWDG1_CLK_SLEEP_DISABLE()          (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN)
+
+/** @brief  ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C1_TIM2_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN)
+#define __HAL_RCC_C1_TIM3_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN)
+#define __HAL_RCC_C1_TIM4_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN)
+#define __HAL_RCC_C1_TIM5_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN)
+#define __HAL_RCC_C1_TIM6_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN)
+#define __HAL_RCC_C1_TIM7_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN)
+#define __HAL_RCC_C1_TIM12_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN)
+#define __HAL_RCC_C1_TIM13_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN)
+#define __HAL_RCC_C1_TIM14_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN)
+#define __HAL_RCC_C1_LPTIM1_CLK_SLEEP_ENABLE()         (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN)
+#define __HAL_RCC_C1_WWDG2_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN)
+#define __HAL_RCC_C1_SPI2_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN)
+#define __HAL_RCC_C1_SPI3_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN)
+#define __HAL_RCC_C1_SPDIFRX_CLK_SLEEP_ENABLE()        (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN)
+#define __HAL_RCC_C1_USART2_CLK_SLEEP_ENABLE()         (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN)
+#define __HAL_RCC_C1_USART3_CLK_SLEEP_ENABLE()         (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN)
+#define __HAL_RCC_C1_UART4_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN)
+#define __HAL_RCC_C1_UART5_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN)
+#define __HAL_RCC_C1_I2C1_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN)
+#define __HAL_RCC_C1_I2C2_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN)
+#define __HAL_RCC_C1_I2C3_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN)
+#define __HAL_RCC_C1_CEC_CLK_SLEEP_ENABLE()            (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN)
+#define __HAL_RCC_C1_DAC12_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN)
+#define __HAL_RCC_C1_UART7_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN)
+#define __HAL_RCC_C1_UART8_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN)
+#define __HAL_RCC_C1_CRS_CLK_SLEEP_ENABLE()            (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN)
+#define __HAL_RCC_C1_SWPMI_CLK_SLEEP_ENABLE()          (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN)
+#define __HAL_RCC_C1_OPAMP_CLK_SLEEP_ENABLE()          (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN)
+#define __HAL_RCC_C1_MDIOS_CLK_SLEEP_ENABLE()          (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN)
+#define __HAL_RCC_C1_FDCAN_CLK_SLEEP_ENABLE()          (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN)
+
+
+#define __HAL_RCC_C1_TIM2_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN)
+#define __HAL_RCC_C1_TIM3_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN)
+#define __HAL_RCC_C1_TIM4_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN)
+#define __HAL_RCC_C1_TIM5_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN)
+#define __HAL_RCC_C1_TIM6_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN)
+#define __HAL_RCC_C1_TIM7_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN)
+#define __HAL_RCC_C1_TIM12_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN)
+#define __HAL_RCC_C1_TIM13_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN)
+#define __HAL_RCC_C1_TIM14_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN)
+#define __HAL_RCC_C1_LPTIM1_CLK_SLEEP_DISABLE()         (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN)
+#define __HAL_RCC_C1_WWDG2_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN)
+#define __HAL_RCC_C1_SPI2_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN)
+#define __HAL_RCC_C1_SPI3_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN)
+#define __HAL_RCC_C1_SPDIFRX_CLK_SLEEP_DISABLE()        (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN)
+#define __HAL_RCC_C1_USART2_CLK_SLEEP_DISABLE()         (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN)
+#define __HAL_RCC_C1_USART3_CLK_SLEEP_DISABLE()         (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN)
+#define __HAL_RCC_C1_UART4_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN)
+#define __HAL_RCC_C1_UART5_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN)
+#define __HAL_RCC_C1_I2C1_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN)
+#define __HAL_RCC_C1_I2C2_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN)
+#define __HAL_RCC_C1_I2C3_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN)
+#define __HAL_RCC_C1_CEC_CLK_SLEEP_DISABLE()            (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN)
+#define __HAL_RCC_C1_DAC12_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN)
+#define __HAL_RCC_C1_UART7_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN)
+#define __HAL_RCC_C1_UART8_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN)
+#define __HAL_RCC_C1_CRS_CLK_SLEEP_DISABLE()            (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN)
+#define __HAL_RCC_C1_SWPMI_CLK_SLEEP_DISABLE()          (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN)
+#define __HAL_RCC_C1_OPAMP_CLK_SLEEP_DISABLE()          (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN)
+#define __HAL_RCC_C1_MDIOS_CLK_SLEEP_DISABLE()          (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN)
+#define __HAL_RCC_C1_FDCAN_CLK_SLEEP_DISABLE()          (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN)
+
+/** @brief  ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C1_TIM1_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN)
+#define __HAL_RCC_C1_TIM8_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN)
+#define __HAL_RCC_C1_USART1_CLK_SLEEP_ENABLE()         (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN)
+#define __HAL_RCC_C1_USART6_CLK_SLEEP_ENABLE()         (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN)
+#define __HAL_RCC_C1_SPI1_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN)
+#define __HAL_RCC_C1_SPI4_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN)
+#define __HAL_RCC_C1_TIM15_CLK_SLEEP_ENABLE()          (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN)
+#define __HAL_RCC_C1_TIM16_CLK_SLEEP_ENABLE()          (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN)
+#define __HAL_RCC_C1_TIM17_CLK_SLEEP_ENABLE()          (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN)
+#define __HAL_RCC_C1_SPI5_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN)
+#define __HAL_RCC_C1_SAI1_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN)
+#define __HAL_RCC_C1_SAI2_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN)
+#define __HAL_RCC_C1_SAI3_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN)
+#define __HAL_RCC_C1_DFSDM1_CLK_SLEEP_ENABLE()         (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN)
+#define __HAL_RCC_C1_HRTIM1_CLK_SLEEP_ENABLE()         (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN)
+
+#define __HAL_RCC_C1_TIM1_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN)
+#define __HAL_RCC_C1_TIM8_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN)
+#define __HAL_RCC_C1_USART1_CLK_SLEEP_DISABLE()         (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN)
+#define __HAL_RCC_C1_USART6_CLK_SLEEP_DISABLE()         (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN)
+#define __HAL_RCC_C1_SPI1_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN)
+#define __HAL_RCC_C1_SPI4_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN)
+#define __HAL_RCC_C1_TIM15_CLK_SLEEP_DISABLE()          (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN)
+#define __HAL_RCC_C1_TIM16_CLK_SLEEP_DISABLE()          (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN)
+#define __HAL_RCC_C1_TIM17_CLK_SLEEP_DISABLE()          (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN)
+#define __HAL_RCC_C1_SPI5_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN)
+#define __HAL_RCC_C1_SAI1_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN)
+#define __HAL_RCC_C1_SAI2_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN)
+#define __HAL_RCC_C1_SAI3_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN)
+#define __HAL_RCC_C1_DFSDM1_CLK_SLEEP_DISABLE()         (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN)
+#define __HAL_RCC_C1_HRTIM1_CLK_SLEEP_DISABLE()         (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN)
+
+/** @brief  ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C1_SYSCFG_CLK_SLEEP_ENABLE()           (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN)
+#define __HAL_RCC_C1_LPUART1_CLK_SLEEP_ENABLE()          (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN)
+#define __HAL_RCC_C1_SPI6_CLK_SLEEP_ENABLE()             (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN)
+#define __HAL_RCC_C1_I2C4_CLK_SLEEP_ENABLE()             (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN)
+#define __HAL_RCC_C1_LPTIM2_CLK_SLEEP_ENABLE()           (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN)
+#define __HAL_RCC_C1_LPTIM3_CLK_SLEEP_ENABLE()           (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN)
+#define __HAL_RCC_C1_LPTIM4_CLK_SLEEP_ENABLE()           (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN)
+#define __HAL_RCC_C1_LPTIM5_CLK_SLEEP_ENABLE()           (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN)
+#define __HAL_RCC_C1_COMP12_CLK_SLEEP_ENABLE()           (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN)
+#define __HAL_RCC_C1_VREF_CLK_SLEEP_ENABLE()             (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN)
+#define __HAL_RCC_C1_SAI4_CLK_SLEEP_ENABLE()             (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN)
+#define __HAL_RCC_C1_RTC_CLK_SLEEP_ENABLE()              (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN)
+
+
+#define __HAL_RCC_C1_SYSCFG_CLK_SLEEP_DISABLE()           (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN)
+#define __HAL_RCC_C1_LPUART1_CLK_SLEEP_DISABLE()          (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN)
+#define __HAL_RCC_C1_SPI6_CLK_SLEEP_DISABLE()             (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN)
+#define __HAL_RCC_C1_I2C4_CLK_SLEEP_DISABLE()             (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN)
+#define __HAL_RCC_C1_LPTIM2_CLK_SLEEP_DISABLE()           (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN)
+#define __HAL_RCC_C1_LPTIM3_CLK_SLEEP_DISABLE()           (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN)
+#define __HAL_RCC_C1_LPTIM4_CLK_SLEEP_DISABLE()           (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN)
+#define __HAL_RCC_C1_LPTIM5_CLK_SLEEP_DISABLE()           (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN)
+#define __HAL_RCC_C1_COMP12_CLK_SLEEP_DISABLE()           (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN)
+#define __HAL_RCC_C1_VREF_CLK_SLEEP_DISABLE()             (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN)
+#define __HAL_RCC_C1_SAI4_CLK_SLEEP_DISABLE()             (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN)
+#define __HAL_RCC_C1_RTC_CLK_SLEEP_DISABLE()              (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN)
+
+/** @brief  Enable or disable the RCC_C2 AHB3 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+
+
+#define __HAL_RCC_C2_MDMA_CLK_SLEEP_ENABLE()            (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN))
+#define __HAL_RCC_C2_DMA2D_CLK_SLEEP_ENABLE()           (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN))
+#define __HAL_RCC_C2_JPGDEC_CLK_SLEEP_ENABLE()          (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN))
+#define __HAL_RCC_C2_FLASH_CLK_SLEEP_ENABLE()           (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN))
+#define __HAL_RCC_C2_FMC_CLK_SLEEP_ENABLE()             (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
+#define __HAL_RCC_C2_QSPI_CLK_SLEEP_ENABLE()            (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
+#define __HAL_RCC_C2_SDMMC1_CLK_SLEEP_ENABLE()          (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN))
+#define __HAL_RCC_C2_DTCM1_CLK_SLEEP_ENABLE()           (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN))
+#define __HAL_RCC_C2_DTCM2_CLK_SLEEP_ENABLE()           (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN))
+#define __HAL_RCC_C2_ITCM_CLK_SLEEP_ENABLE()            (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN))
+#define __HAL_RCC_C2_D1SRAM1_CLK_SLEEP_ENABLE()         (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN))
+
+
+#define __HAL_RCC_C2_MDMA_CLK_SLEEP_DISABLE()            (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN))
+#define __HAL_RCC_C2_DMA2D_CLK_SLEEP_DISABLE()           (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN))
+#define __HAL_RCC_C2_JPGDEC_CLK_SLEEP_DISABLE()          (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN))
+#define __HAL_RCC_C2_FLASH_CLK_SLEEP_DISABLE()           (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN))
+#define __HAL_RCC_C2_FMC_CLK_SLEEP_DISABLE()             (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN))
+#define __HAL_RCC_C2_QSPI_CLK_SLEEP_DISABLE()            (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN))
+#define __HAL_RCC_C2_SDMMC1_CLK_SLEEP_DISABLE()          (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN))
+#define __HAL_RCC_C2_DTCM1_CLK_SLEEP_DISABLE()           (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN))
+#define __HAL_RCC_C2_DTCM2_CLK_SLEEP_DISABLE()           (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN))
+#define __HAL_RCC_C2_ITCM_CLK_SLEEP_DISABLE()            (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN))
+#define __HAL_RCC_C2_D1SRAM1_CLK_SLEEP_DISABLE()         (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN))
+
+
+
+/** @brief  ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C2_DMA1_CLK_SLEEP_ENABLE()             (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
+#define __HAL_RCC_C2_DMA2_CLK_SLEEP_ENABLE()             (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
+#define __HAL_RCC_C2_ADC12_CLK_SLEEP_ENABLE()            (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN))
+#define __HAL_RCC_C2_ETH1MAC_CLK_SLEEP_ENABLE()          (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN))
+#define __HAL_RCC_C2_ETH1TX_CLK_SLEEP_ENABLE()           (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN))
+#define __HAL_RCC_C2_ETH1RX_CLK_SLEEP_ENABLE()           (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN))
+#define __HAL_RCC_C2_USB1_OTG_HS_CLK_SLEEP_ENABLE()      (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN))
+#define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
+#define __HAL_RCC_C2_USB2_OTG_FS_CLK_SLEEP_ENABLE()      (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN))
+#define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
+
+#define __HAL_RCC_C2_DMA1_CLK_SLEEP_DISABLE()             (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN))
+#define __HAL_RCC_C2_DMA2_CLK_SLEEP_DISABLE()             (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN))
+#define __HAL_RCC_C2_ADC12_CLK_SLEEP_DISABLE()            (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN))
+#define __HAL_RCC_C2_ETH1MAC_CLK_SLEEP_DISABLE()          (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN))
+#define __HAL_RCC_C2_ETH1TX_CLK_SLEEP_DISABLE()           (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN))
+#define __HAL_RCC_C2_ETH1RX_CLK_SLEEP_DISABLE()           (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN))
+#define __HAL_RCC_C2_USB1_OTG_HS_CLK_SLEEP_DISABLE()      (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN))
+#define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
+#define __HAL_RCC_C2_USB2_OTG_FS_CLK_SLEEP_DISABLE()      (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN))
+#define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
+
+/** @brief  ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C2_DCMI_CLK_SLEEP_ENABLE()             (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
+#if defined(CRYP)
+#define __HAL_RCC_C2_CRYP_CLK_SLEEP_ENABLE()             (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_C2_HASH_CLK_SLEEP_ENABLE()             (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
+#endif /* HASH */
+#define __HAL_RCC_C2_RNG_CLK_SLEEP_ENABLE()              (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
+#define __HAL_RCC_C2_SDMMC2_CLK_SLEEP_ENABLE()           (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))
+#define __HAL_RCC_C2_D2SRAM1_CLK_SLEEP_ENABLE()          (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN))
+#define __HAL_RCC_C2_D2SRAM2_CLK_SLEEP_ENABLE()          (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN))
+#define __HAL_RCC_C2_D2SRAM3_CLK_SLEEP_ENABLE()          (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN))
+
+#define __HAL_RCC_C2_DCMI_CLK_SLEEP_DISABLE()             (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))
+#if defined(CRYP)
+#define __HAL_RCC_C2_CRYP_CLK_SLEEP_DISABLE()             (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_C2_HASH_CLK_SLEEP_DISABLE()             (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))
+#endif /* HASH */
+#define __HAL_RCC_C2_RNG_CLK_SLEEP_DISABLE()              (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))
+#define __HAL_RCC_C2_SDMMC2_CLK_SLEEP_DISABLE()           (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))
+#define __HAL_RCC_C2_D2SRAM1_CLK_SLEEP_DISABLE()          (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN))
+#define __HAL_RCC_C2_D2SRAM2_CLK_SLEEP_DISABLE()          (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN))
+#define __HAL_RCC_C2_D2SRAM3_CLK_SLEEP_DISABLE()          (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN))
+
+/** @brief  ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C2_GPIOA_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN)
+#define __HAL_RCC_C2_GPIOB_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN)
+#define __HAL_RCC_C2_GPIOC_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN)
+#define __HAL_RCC_C2_GPIOD_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN)
+#define __HAL_RCC_C2_GPIOE_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN)
+#define __HAL_RCC_C2_GPIOF_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN)
+#define __HAL_RCC_C2_GPIOG_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN)
+#define __HAL_RCC_C2_GPIOH_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN)
+#define __HAL_RCC_C2_GPIOI_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN)
+#define __HAL_RCC_C2_GPIOJ_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN)
+#define __HAL_RCC_C2_GPIOK_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN)
+#define __HAL_RCC_C2_CRC_CLK_SLEEP_ENABLE()             (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN)
+#define __HAL_RCC_C2_BDMA_CLK_SLEEP_ENABLE()            (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN)
+#define __HAL_RCC_C2_ADC3_CLK_SLEEP_ENABLE()            (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN)
+#define __HAL_RCC_C2_BKPRAM_CLK_SLEEP_ENABLE()          (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN)
+#define __HAL_RCC_C2_D3SRAM1_CLK_SLEEP_ENABLE()         (RCC_C2->AHB4LPENR  |= (RCC_AHB4LPENR_D3SRAM1LPEN))
+
+#define __HAL_RCC_C2_GPIOA_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN)
+#define __HAL_RCC_C2_GPIOB_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN)
+#define __HAL_RCC_C2_GPIOC_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN)
+#define __HAL_RCC_C2_GPIOD_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN)
+#define __HAL_RCC_C2_GPIOE_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN)
+#define __HAL_RCC_C2_GPIOF_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN)
+#define __HAL_RCC_C2_GPIOG_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN)
+#define __HAL_RCC_C2_GPIOH_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN)
+#define __HAL_RCC_C2_GPIOI_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN)
+#define __HAL_RCC_C2_GPIOJ_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN)
+#define __HAL_RCC_C2_GPIOK_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN)
+#define __HAL_RCC_C2_CRC_CLK_SLEEP_DISABLE()             (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN)
+#define __HAL_RCC_C2_BDMA_CLK_SLEEP_DISABLE()            (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN)
+#define __HAL_RCC_C2_ADC3_CLK_SLEEP_DISABLE()            (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN)
+#define __HAL_RCC_C2_BKPRAM_CLK_SLEEP_DISABLE()          (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN)
+#define __HAL_RCC_C2_D3SRAM1_CLK_SLEEP_DISABLE()         (RCC_C2->AHB4LPENR  &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN))
+
+/** @brief  ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C2_LTDC_CLK_SLEEP_ENABLE()           (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN)
+#define __HAL_RCC_C2_DSI_CLK_SLEEP_ENABLE()            (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN)
+#define __HAL_RCC_C2_WWDG1_CLK_SLEEP_ENABLE()          (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN)
+
+#define __HAL_RCC_C2_LTDC_CLK_SLEEP_DISABLE()           (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN)
+#define __HAL_RCC_C2_DSI_CLK_SLEEP_DISABLE()            (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN)
+#define __HAL_RCC_C2_WWDG1_CLK_SLEEP_DISABLE()          (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN)
+
+/** @brief  ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C2_TIM2_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN)
+#define __HAL_RCC_C2_TIM3_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN)
+#define __HAL_RCC_C2_TIM4_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN)
+#define __HAL_RCC_C2_TIM5_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN)
+#define __HAL_RCC_C2_TIM6_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN)
+#define __HAL_RCC_C2_TIM7_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN)
+#define __HAL_RCC_C2_TIM12_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN)
+#define __HAL_RCC_C2_TIM13_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN)
+#define __HAL_RCC_C2_TIM14_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN)
+#define __HAL_RCC_C2_LPTIM1_CLK_SLEEP_ENABLE()         (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN)
+#define __HAL_RCC_C2_WWDG2_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN)
+#define __HAL_RCC_C2_SPI2_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN)
+#define __HAL_RCC_C2_SPI3_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN)
+#define __HAL_RCC_C2_SPDIFRX_CLK_SLEEP_ENABLE()        (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN)
+#define __HAL_RCC_C2_USART2_CLK_SLEEP_ENABLE()         (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN)
+#define __HAL_RCC_C2_USART3_CLK_SLEEP_ENABLE()         (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN)
+#define __HAL_RCC_C2_UART4_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN)
+#define __HAL_RCC_C2_UART5_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN)
+#define __HAL_RCC_C2_I2C1_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN)
+#define __HAL_RCC_C2_I2C2_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN)
+#define __HAL_RCC_C2_I2C3_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN)
+#define __HAL_RCC_C2_CEC_CLK_SLEEP_ENABLE()            (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN)
+#define __HAL_RCC_C2_DAC12_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN)
+#define __HAL_RCC_C2_UART7_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN)
+#define __HAL_RCC_C2_UART8_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN)
+#define __HAL_RCC_C2_CRS_CLK_SLEEP_ENABLE()            (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN)
+#define __HAL_RCC_C2_SWPMI_CLK_SLEEP_ENABLE()          (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN)
+#define __HAL_RCC_C2_OPAMP_CLK_SLEEP_ENABLE()          (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN)
+#define __HAL_RCC_C2_MDIOS_CLK_SLEEP_ENABLE()          (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN)
+#define __HAL_RCC_C2_FDCAN_CLK_SLEEP_ENABLE()          (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN)
+
+
+#define __HAL_RCC_C2_TIM2_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN)
+#define __HAL_RCC_C2_TIM3_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN)
+#define __HAL_RCC_C2_TIM4_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN)
+#define __HAL_RCC_C2_TIM5_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN)
+#define __HAL_RCC_C2_TIM6_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN)
+#define __HAL_RCC_C2_TIM7_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN)
+#define __HAL_RCC_C2_TIM12_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN)
+#define __HAL_RCC_C2_TIM13_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN)
+#define __HAL_RCC_C2_TIM14_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN)
+#define __HAL_RCC_C2_LPTIM1_CLK_SLEEP_DISABLE()         (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN)
+#define __HAL_RCC_C2_WWDG2_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN)
+#define __HAL_RCC_C2_SPI2_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN)
+#define __HAL_RCC_C2_SPI3_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN)
+#define __HAL_RCC_C2_SPDIFRX_CLK_SLEEP_DISABLE()        (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN)
+#define __HAL_RCC_C2_USART2_CLK_SLEEP_DISABLE()         (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN)
+#define __HAL_RCC_C2_USART3_CLK_SLEEP_DISABLE()         (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN)
+#define __HAL_RCC_C2_UART4_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN)
+#define __HAL_RCC_C2_UART5_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN)
+#define __HAL_RCC_C2_I2C1_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN)
+#define __HAL_RCC_C2_I2C2_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN)
+#define __HAL_RCC_C2_I2C3_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN)
+#define __HAL_RCC_C2_CEC_CLK_SLEEP_DISABLE()            (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN)
+#define __HAL_RCC_C2_DAC12_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN)
+#define __HAL_RCC_C2_UART7_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN)
+#define __HAL_RCC_C2_UART8_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN)
+#define __HAL_RCC_C2_CRS_CLK_SLEEP_DISABLE()            (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN)
+#define __HAL_RCC_C2_SWPMI_CLK_SLEEP_DISABLE()          (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN)
+#define __HAL_RCC_C2_OPAMP_CLK_SLEEP_DISABLE()          (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN)
+#define __HAL_RCC_C2_MDIOS_CLK_SLEEP_DISABLE()          (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN)
+#define __HAL_RCC_C2_FDCAN_CLK_SLEEP_DISABLE()          (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN)
+
+/** @brief  ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C2_TIM1_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN)
+#define __HAL_RCC_C2_TIM8_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN)
+#define __HAL_RCC_C2_USART1_CLK_SLEEP_ENABLE()         (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN)
+#define __HAL_RCC_C2_USART6_CLK_SLEEP_ENABLE()         (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN)
+#define __HAL_RCC_C2_SPI1_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN)
+#define __HAL_RCC_C2_SPI4_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN)
+#define __HAL_RCC_C2_TIM15_CLK_SLEEP_ENABLE()          (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN)
+#define __HAL_RCC_C2_TIM16_CLK_SLEEP_ENABLE()          (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN)
+#define __HAL_RCC_C2_TIM17_CLK_SLEEP_ENABLE()          (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN)
+#define __HAL_RCC_C2_SPI5_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN)
+#define __HAL_RCC_C2_SAI1_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN)
+#define __HAL_RCC_C2_SAI2_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN)
+#define __HAL_RCC_C2_SAI3_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN)
+#define __HAL_RCC_C2_DFSDM1_CLK_SLEEP_ENABLE()         (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN)
+#define __HAL_RCC_C2_HRTIM1_CLK_SLEEP_ENABLE()         (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN)
+
+#define __HAL_RCC_C2_TIM1_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN)
+#define __HAL_RCC_C2_TIM8_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN)
+#define __HAL_RCC_C2_USART1_CLK_SLEEP_DISABLE()         (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN)
+#define __HAL_RCC_C2_USART6_CLK_SLEEP_DISABLE()         (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN)
+#define __HAL_RCC_C2_SPI1_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN)
+#define __HAL_RCC_C2_SPI4_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN)
+#define __HAL_RCC_C2_TIM15_CLK_SLEEP_DISABLE()          (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN)
+#define __HAL_RCC_C2_TIM16_CLK_SLEEP_DISABLE()          (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN)
+#define __HAL_RCC_C2_TIM17_CLK_SLEEP_DISABLE()          (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN)
+#define __HAL_RCC_C2_SPI5_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN)
+#define __HAL_RCC_C2_SAI1_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN)
+#define __HAL_RCC_C2_SAI2_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN)
+#define __HAL_RCC_C2_SAI3_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN)
+#define __HAL_RCC_C2_DFSDM1_CLK_SLEEP_DISABLE()         (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN)
+#define __HAL_RCC_C2_HRTIM1_CLK_SLEEP_DISABLE()         (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN)
+
+/** @brief  ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C2_SYSCFG_CLK_SLEEP_ENABLE()           (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN)
+#define __HAL_RCC_C2_LPUART1_CLK_SLEEP_ENABLE()          (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN)
+#define __HAL_RCC_C2_SPI6_CLK_SLEEP_ENABLE()             (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN)
+#define __HAL_RCC_C2_I2C4_CLK_SLEEP_ENABLE()             (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN)
+#define __HAL_RCC_C2_LPTIM2_CLK_SLEEP_ENABLE()           (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN)
+#define __HAL_RCC_C2_LPTIM3_CLK_SLEEP_ENABLE()           (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN)
+#define __HAL_RCC_C2_LPTIM4_CLK_SLEEP_ENABLE()           (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN)
+#define __HAL_RCC_C2_LPTIM5_CLK_SLEEP_ENABLE()           (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN)
+#define __HAL_RCC_C2_COMP12_CLK_SLEEP_ENABLE()           (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN)
+#define __HAL_RCC_C2_VREF_CLK_SLEEP_ENABLE()             (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN)
+#define __HAL_RCC_C2_SAI4_CLK_SLEEP_ENABLE()             (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN)
+#define __HAL_RCC_C2_RTC_CLK_SLEEP_ENABLE()              (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN)
+
+#define __HAL_RCC_C2_SYSCFG_CLK_SLEEP_DISABLE()           (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN)
+#define __HAL_RCC_C2_LPUART1_CLK_SLEEP_DISABLE()          (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN)
+#define __HAL_RCC_C2_SPI6_CLK_SLEEP_DISABLE()             (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN)
+#define __HAL_RCC_C2_I2C4_CLK_SLEEP_DISABLE()             (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN)
+#define __HAL_RCC_C2_LPTIM2_CLK_SLEEP_DISABLE()           (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN)
+#define __HAL_RCC_C2_LPTIM3_CLK_SLEEP_DISABLE()           (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN)
+#define __HAL_RCC_C2_LPTIM4_CLK_SLEEP_DISABLE()           (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN)
+#define __HAL_RCC_C2_LPTIM5_CLK_SLEEP_DISABLE()           (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN)
+#define __HAL_RCC_C2_COMP12_CLK_SLEEP_DISABLE()           (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN)
+#define __HAL_RCC_C2_VREF_CLK_SLEEP_DISABLE()             (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN)
+#define __HAL_RCC_C2_SAI4_CLK_SLEEP_DISABLE()             (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN)
+#define __HAL_RCC_C2_RTC_CLK_SLEEP_DISABLE()              (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN)
+
+#endif /*DUAL_CORE*/
+
+#if defined(DUAL_CORE)
+/** @brief  Enable or disable peripheral bus clock  when D3 domain is in DRUN
+  * @note   After reset (default config), peripheral clock is disabled when both CPUs are in CSTOP
+  */
+#else
+/** @brief  Enable or disable peripheral bus clock  when D3 domain is in DRUN
+  * @note   After reset (default config), peripheral clock is disabled when CPU is in CSTOP
+  */
+#endif /*DUAL_CORE*/
+
+#if defined(RCC_D3AMR_BDMAAMEN)
+#define __HAL_RCC_BDMA_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_BDMAAMEN)
+#endif
+#if defined(RCC_D3AMR_LPUART1AMEN)
+#define __HAL_RCC_LPUART1_CLKAM_ENABLE()          (RCC->D3AMR) |= (RCC_D3AMR_LPUART1AMEN)
+#endif
+#if defined(RCC_D3AMR_SPI6AMEN)
+#define __HAL_RCC_SPI6_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_SPI6AMEN)
+#endif
+#if defined(RCC_D3AMR_I2C4AMEN)
+#define __HAL_RCC_I2C4_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_I2C4AMEN)
+#endif
+#if defined(RCC_D3AMR_LPTIM2AMEN)
+#define __HAL_RCC_LPTIM2_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_LPTIM2AMEN)
+#endif
+#if defined(RCC_D3AMR_LPTIM3AMEN)
+#define __HAL_RCC_LPTIM3_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_LPTIM3AMEN)
+#endif
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_LPTIM4AMEN)
+#endif
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_LPTIM5AMEN)
+#endif
+#if defined(RCC_D3AMR_COMP12AMEN)
+#define __HAL_RCC_COMP12_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_COMP12AMEN)
+#endif
+#if defined(RCC_D3AMR_VREFAMEN)
+#define __HAL_RCC_VREF_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_VREFAMEN)
+#endif
+#if defined(RCC_D3AMR_RTCAMEN)
+#define __HAL_RCC_RTC_CLKAM_ENABLE()              (RCC->D3AMR) |= (RCC_D3AMR_RTCAMEN)
+#endif
+#if defined(RCC_D3AMR_CRCAMEN)
+#define __HAL_RCC_CRC_CLKAM_ENABLE()              (RCC->D3AMR) |= (RCC_D3AMR_CRCAMEN)
+#endif
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_SAI4AMEN)
+#endif
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_ADC3AMEN)
+#endif
+#if defined(RCC_D3AMR_BKPRAMAMEN)
+#define __HAL_RCC_BKPRAM_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_BKPRAMAMEN)
+#endif
+#if defined(RCC_D3AMR_SRAM4AMEN)
+#define __HAL_RCC_D3SRAM1_CLKAM_ENABLE()          (RCC->D3AMR) |= (RCC_D3AMR_SRAM4AMEN)
+#endif
+
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_CLKAM_ENABLE()            (RCC->SRDAMR) |= (RCC_SRDAMR_BDMA2AMEN)
+#endif
+#if defined(RCC_SRDAMR_GPIOAMEN)
+#define __HAL_RCC_GPIO_CLKAM_ENABLE()             (RCC->SRDAMR) |= (RCC_SRDAMR_GPIOAMEN)
+#endif
+#if defined(RCC_SRDAMR_LPUART1AMEN)
+#define __HAL_RCC_LPUART1_CLKAM_ENABLE()          (RCC->SRDAMR) |= (RCC_SRDAMR_LPUART1AMEN)
+#endif
+#if defined(RCC_SRDAMR_SPI6AMEN)
+#define __HAL_RCC_SPI6_CLKAM_ENABLE()             (RCC->SRDAMR) |= (RCC_SRDAMR_SPI6AMEN)
+#endif
+#if defined(RCC_SRDAMR_I2C4AMEN)
+#define __HAL_RCC_I2C4_CLKAM_ENABLE()             (RCC->SRDAMR) |= (RCC_SRDAMR_I2C4AMEN)
+#endif
+#if defined(RCC_SRDAMR_LPTIM2AMEN)
+#define __HAL_RCC_LPTIM2_CLKAM_ENABLE()           (RCC->SRDAMR) |= (RCC_SRDAMR_LPTIM2AMEN)
+#endif
+#if defined(RCC_SRDAMR_LPTIM3AMEN)
+#define __HAL_RCC_LPTIM3_CLKAM_ENABLE()           (RCC->SRDAMR) |= (RCC_SRDAMR_LPTIM3AMEN)
+#endif
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_CLKAM_ENABLE()             (RCC->SRDAMR) |= (RCC_SRDAMR_DAC2AMEN)
+#endif
+#if defined(RCC_SRDAMR_COMP12AMEN)
+#define __HAL_RCC_COMP12_CLKAM_ENABLE()           (RCC->SRDAMR) |= (RCC_SRDAMR_COMP12AMEN)
+#endif
+#if defined(RCC_SRDAMR_VREFAMEN)
+#define __HAL_RCC_VREF_CLKAM_ENABLE()             (RCC->SRDAMR) |= (RCC_SRDAMR_VREFAMEN)
+#endif
+#if defined(RCC_SRDAMR_RTCAMEN)
+#define __HAL_RCC_RTC_CLKAM_ENABLE()              (RCC->SRDAMR) |= (RCC_SRDAMR_RTCAMEN)
+#endif
+#if defined(RCC_SRDAMR_DTSAMEN)
+#define __HAL_RCC_DTS_CLKAM_ENABLE()              (RCC->SRDAMR) |= (RCC_SRDAMR_DTSAMEN)
+#endif
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_CLKAM_ENABLE()           (RCC->SRDAMR) |= (RCC_SRDAMR_DFSDM2AMEN)
+#endif
+#if defined(RCC_SRDAMR_BKPRAMAMEN)
+#define __HAL_RCC_BKPRAM_CLKAM_ENABLE()           (RCC->SRDAMR) |= (RCC_SRDAMR_BKPRAMAMEN)
+#endif
+#if defined(RCC_SRDAMR_SRDSRAMAMEN)
+#define __HAL_RCC_SRDSRAM_CLKAM_ENABLE()          (RCC->SRDAMR) |= (RCC_SRDAMR_SRDSRAMAMEN)
+#endif
+
+#if defined(RCC_D3AMR_BDMAAMEN)
+#define __HAL_RCC_BDMA_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_BDMAAMEN)
+#endif
+#if defined(RCC_D3AMR_LPUART1AMEN)
+#define __HAL_RCC_LPUART1_CLKAM_DISABLE()          (RCC->D3AMR) &= ~ (RCC_D3AMR_LPUART1AMEN)
+#endif
+#if defined(RCC_D3AMR_SPI6AMEN)
+#define __HAL_RCC_SPI6_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_SPI6AMEN)
+#endif
+#if defined(RCC_D3AMR_I2C4AMEN)
+#define __HAL_RCC_I2C4_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_I2C4AMEN)
+#endif
+#if defined(RCC_D3AMR_LPTIM2AMEN)
+#define __HAL_RCC_LPTIM2_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM2AMEN)
+#endif
+#if defined(RCC_D3AMR_LPTIM3AMEN)
+#define __HAL_RCC_LPTIM3_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM3AMEN)
+#endif
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM4AMEN)
+#endif
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM5AMEN)
+#endif
+#if defined(RCC_D3AMR_COMP12AMEN)
+#define __HAL_RCC_COMP12_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_COMP12AMEN)
+#endif
+#if defined(RCC_D3AMR_VREFAMEN)
+#define __HAL_RCC_VREF_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_VREFAMEN)
+#endif
+#if defined(RCC_D3AMR_RTCAMEN)
+#define __HAL_RCC_RTC_CLKAM_DISABLE()              (RCC->D3AMR) &= ~ (RCC_D3AMR_RTCAMEN)
+#endif
+#if defined(RCC_D3AMR_CRCAMEN)
+#define __HAL_RCC_CRC_CLKAM_DISABLE()              (RCC->D3AMR) &= ~ (RCC_D3AMR_CRCAMEN)
+#endif
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_SAI4AMEN)
+#endif
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_ADC3AMEN)
+#endif
+#if defined(RCC_D3AMR_BKPRAMAMEN)
+#define __HAL_RCC_BKPRAM_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_BKPRAMAMEN)
+#endif
+#if defined(RCC_D3AMR_SRAM4AMEN)
+#define __HAL_RCC_D3SRAM1_CLKAM_DISABLE()          (RCC->D3AMR)&= ~ (RCC_D3AMR_SRAM4AMEN)
+#endif
+
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_CLKAM_DISABLE()            (RCC->SRDAMR) &= ~ (RCC_SRDAMR_BDMA2AMEN)
+#endif
+#if defined(RCC_SRDAMR_GPIOAMEN)
+#define __HAL_RCC_GPIO_CLKAM_DISABLE()             (RCC->SRDAMR) &= ~ (RCC_SRDAMR_GPIOAMEN)
+#endif
+#if defined(RCC_SRDAMR_LPUART1AMEN)
+#define __HAL_RCC_LPUART1_CLKAM_DISABLE()          (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPUART1AMEN)
+#endif
+#if defined(RCC_SRDAMR_SPI6AMEN)
+#define __HAL_RCC_SPI6_CLKAM_DISABLE()             (RCC->SRDAMR) &= ~ (RCC_SRDAMR_SPI6AMEN)
+#endif
+#if defined(RCC_SRDAMR_I2C4AMEN)
+#define __HAL_RCC_I2C4_CLKAM_DISABLE()             (RCC->SRDAMR) &= ~ (RCC_SRDAMR_I2C4AMEN)
+#endif
+#if defined(RCC_SRDAMR_LPTIM2AMEN)
+#define __HAL_RCC_LPTIM2_CLKAM_DISABLE()           (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPTIM2AMEN)
+#endif
+#if defined(RCC_SRDAMR_LPTIM3AMEN)
+#define __HAL_RCC_LPTIM3_CLKAM_DISABLE()           (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPTIM3AMEN)
+#endif
+#if defined(RCC_SRDAMR_DAC2AMEN)
+#define __HAL_RCC_DAC2_CLKAM_DISABLE()             (RCC->SRDAMR) &= ~ (RCC_SRDAMR_DAC2AMEN)
+#endif
+#if defined(RCC_SRDAMR_COMP12AMEN)
+#define __HAL_RCC_COMP12_CLKAM_DISABLE()           (RCC->SRDAMR) &= ~ (RCC_SRDAMR_COMP12AMEN)
+#endif
+#if defined(RCC_SRDAMR_VREFAMEN)
+#define __HAL_RCC_VREF_CLKAM_DISABLE()             (RCC->SRDAMR) &= ~ (RCC_SRDAMR_VREFAMEN)
+#endif
+#if defined(RCC_SRDAMR_RTCAMEN)
+#define __HAL_RCC_RTC_CLKAM_DISABLE()              (RCC->SRDAMR) &= ~(RCC_SRDAMR_RTCAMEN)
+#endif
+#if defined(RCC_SRDAMR_DTSAMEN)
+#define __HAL_RCC_DTS_CLKAM_DISABLE()              (RCC->SRDAMR) &= ~(RCC_SRDAMR_DTSAMEN)
+#endif
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_CLKAM_DISABLE()           (RCC->SRDAMR) &= ~(RCC_SRDAMR_DFSDM2AMEN)
+#endif
+#if defined(RCC_SRDAMR_BKPRAMAMEN)
+#define __HAL_RCC_BKPRAM_CLKAM_DISABLE()           (RCC->SRDAMR) &= ~ (RCC_SRDAMR_BKPRAMAMEN)
+#endif
+#if defined(RCC_SRDAMR_SRDSRAMAMEN)
+#define __HAL_RCC_SRDSRAM_CLKAM_DISABLE()          (RCC->SRDAMR) &= ~ (RCC_SRDAMR_SRDSRAMAMEN)
+#endif
+
+
+#if defined(RCC_CKGAENR_AXICKG)
+    /** @brief  Macro to enable or disable the RCC_CKGAENR bits (AXI clocks gating enable register).
+  * @note
+  * @note
+  * @note
+  * @param
+  * @note
+  */
+
+#define __HAL_RCC_AXI_CLKGA_ENABLE()             (RCC->CKGAENR) |= (RCC_CKGAENR_AXICKG)
+#define __HAL_RCC_AHB_CLKGA_ENABLE()             (RCC->CKGAENR) |= (RCC_CKGAENR_AHBCKG)
+#define __HAL_RCC_CPU_CLKGA_ENABLE()             (RCC->CKGAENR) |= (RCC_CKGAENR_CPUCKG)
+#define __HAL_RCC_SDMMC_CLKGA_ENABLE()           (RCC->CKGAENR) |= (RCC_CKGAENR_SDMMCCKG)
+#define __HAL_RCC_MDMA_CLKGA_ENABLE()            (RCC->CKGAENR) |= (RCC_CKGAENR_MDMACKG)
+#define __HAL_RCC_DMA2D_CLKGA_ENABLE()           (RCC->CKGAENR) |= (RCC_CKGAENR_DMA2DCKG)
+#define __HAL_RCC_LTDC_CLKGA_ENABLE()            (RCC->CKGAENR) |= (RCC_CKGAENR_LTDCCKG)
+#define __HAL_RCC_GFXMMUM_CLKGA_ENABLE()         (RCC->CKGAENR) |= (RCC_CKGAENR_GFXMMUMCKG)
+#define __HAL_RCC_AHB12_CLKGA_ENABLE()           (RCC->CKGAENR) |= (RCC_CKGAENR_AHB12CKG)
+#define __HAL_RCC_AHB34_CLKGA_ENABLE()           (RCC->CKGAENR) |= (RCC_CKGAENR_AHB34CKG)
+#define __HAL_RCC_FLIFT_CLKGA_ENABLE()           (RCC->CKGAENR) |= (RCC_CKGAENR_FLIFTCKG)
+#define __HAL_RCC_OCTOSPI2_CLKGA_ENABLE()        (RCC->CKGAENR) |= (RCC_CKGAENR_OCTOSPI2CKG)
+#define __HAL_RCC_FMC_CLKGA_ENABLE()             (RCC->CKGAENR) |= (RCC_CKGAENR_FMCCKG)
+#define __HAL_RCC_OCTOSPI1_CLKGA_ENABLE()        (RCC->CKGAENR) |= (RCC_CKGAENR_OCTOSPI1CKG)
+#define __HAL_RCC_AXIRAM1_CLKGA_ENABLE()         (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM1CKG)
+#define __HAL_RCC_AXIRAM2_CLKGA_ENABLE()         (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM2CKG)
+#define __HAL_RCC_AXIRAM3_CLKGA_ENABLE()         (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM3CKG)
+#define __HAL_RCC_GFXMMUS_CLKGA_ENABLE()         (RCC->CKGAENR) |= (RCC_CKGAENR_GFXMMUSCKG)
+#define __HAL_RCC_ECCRAM_CLKGA_ENABLE()          (RCC->CKGAENR) |= (RCC_CKGAENR_ECCRAMCKG)
+#define __HAL_RCC_EXTI_CLKGA_ENABLE()            (RCC->CKGAENR) |= (RCC_CKGAENR_EXTICKG)
+#define __HAL_RCC_JTAG_CLKGA_ENABLE()            (RCC->CKGAENR) |= (RCC_CKGAENR_JTAGCKG)
+
+
+#define __HAL_RCC_AXI_CLKGA_DISABLE()             (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXICKG)
+#define __HAL_RCC_AHB_CLKGA_DISABLE()             (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHBCKG)
+#define __HAL_RCC_CPU_CLKGA_DISABLE()             (RCC->CKGAENR) &= ~ (RCC_CKGAENR_CPUCKG)
+#define __HAL_RCC_SDMMC_CLKGA_DISABLE()           (RCC->CKGAENR) &= ~ (RCC_CKGAENR_SDMMCCKG)
+#define __HAL_RCC_MDMA_CLKGA_DISABLE()            (RCC->CKGAENR) &= ~ (RCC_CKGAENR_MDMACKG)
+#define __HAL_RCC_DMA2D_CLKGA_DISABLE()           (RCC->CKGAENR) &= ~ (RCC_CKGAENR_DMA2DCKG)
+#define __HAL_RCC_LTDC_CLKGA_DISABLE()            (RCC->CKGAENR) &= ~ (RCC_CKGAENR_LTDCCKG)
+#define __HAL_RCC_GFXMMUM_CLKGA_DISABLE()         (RCC->CKGAENR) &= ~ (RCC_CKGAENR_GFXMMUMCKG)
+#define __HAL_RCC_AHB12_CLKGA_DISABLE()           (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHB12CKG)
+#define __HAL_RCC_AHB34_CLKGA_DISABLE()           (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHB34CKG)
+#define __HAL_RCC_FLIFT_CLKGA_DISABLE()           (RCC->CKGAENR) &= ~ (RCC_CKGAENR_FLIFTCKG)
+#define __HAL_RCC_OCTOSPI2_CLKGA_DISABLE()        (RCC->CKGAENR) &= ~ (RCC_CKGAENR_OCTOSPI2CKG)
+#define __HAL_RCC_FMC_CLKGA_DISABLE()             (RCC->CKGAENR) &= ~ (RCC_CKGAENR_FMCCKG)
+#define __HAL_RCC_OCTOSPI1_CLKGA_DISABLE()        (RCC->CKGAENR) &= ~ (RCC_CKGAENR_OCTOSPI1CKG)
+#define __HAL_RCC_AXIRAM1_CLKGA_DISABLE()         (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM1CKG)
+#define __HAL_RCC_AXIRAM2_CLKGA_DISABLE()         (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM2CKG)
+#define __HAL_RCC_AXIRAM3_CLKGA_DISABLE()         (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM3CKG)
+#define __HAL_RCC_GFXMMUS_CLKGA_DISABLE()         (RCC->CKGAENR) &= ~ (RCC_CKGAENR_GFXMMUSCKG)
+#define __HAL_RCC_ECCRAM_CLKGA_DISABLE()          (RCC->CKGAENR) &= ~ (RCC_CKGAENR_ECCRAMCKG)
+#define __HAL_RCC_EXTI_CLKGA_DISABLE()            (RCC->CKGAENR) &= ~ (RCC_CKGAENR_EXTICKG)
+#define __HAL_RCC_JTAG_CLKGA_DISABLE()            (RCC->CKGAENR) &= ~ (RCC_CKGAENR_JTAGCKG)
+
+#endif /* RCC_CKGAENR_AXICKG */
+
+
+
+
+/** @brief  Macro to enable or disable the Internal High Speed oscillator (HSI).
+  * @note     After enabling the HSI, the application software should wait on
+  *           HSIRDY flag to be set indicating that HSI clock is stable and can
+  *           be used to clock the PLL and/or system clock.
+  * @note     HSI can not be stopped if it is used directly or through the PLL
+  *           as system clock. In this case, you have to select another source
+  *           of the system clock then stop the HSI.
+  * @note     The HSI is stopped by hardware when entering STOP and STANDBY modes.
+  * @param    __STATE__ specifies the new state of the HSI.
+  *           This parameter can be one of the following values:
+  *            @arg RCC_HSI_OFF turn OFF the HSI oscillator
+  *            @arg RCC_HSI_ON turn ON the HSI oscillator
+  *            @arg RCC_HSI_DIV1 turn ON the HSI oscillator and divide it by 1 (default after reset)
+  *            @arg RCC_HSI_DIV2 turn ON the HSI oscillator and divide it by 2
+  *            @arg RCC_HSI_DIV4 turn ON the HSI oscillator and divide it by 4
+  *            @arg RCC_HSI_DIV8 turn ON the HSI oscillator and divide it by 8
+  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
+  *         clock cycles.
+  */
+#define __HAL_RCC_HSI_CONFIG(__STATE__) \
+                  MODIFY_REG(RCC->CR, RCC_CR_HSION | RCC_CR_HSIDIV , (uint32_t)(__STATE__))
+
+
+/** @brief  Macro to get the HSI divider.
+  * @retval The HSI divider. The returned value can be one
+  *         of the following:
+  *            - RCC_CR_HSIDIV_1  HSI oscillator divided by 1 (default after reset)
+  *            - RCC_CR_HSIDIV_2  HSI oscillator divided by 2
+  *            - RCC_CR_HSIDIV_4  HSI oscillator divided by 4
+  *            - RCC_CR_HSIDIV_8  HSI oscillator divided by 8
+  */
+#define __HAL_RCC_GET_HSI_DIVIDER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV)))
+
+/** @brief  Macros to enable or disable the Internal High Speed oscillator (HSI).
+  * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
+  *         It is used (enabled by hardware) as system clock source after start-up
+  *         from Reset, wakeup from STOP and STANDBY mode, or in case of failure
+  *         of the HSE used directly or indirectly as system clock (if the Clock
+  *         Security System CSS is enabled).
+  * @note   HSI can not be stopped if it is used as system clock source. In this case,
+  *         you have to select another source of the system clock then stop the HSI.
+  * @note   After enabling the HSI, the application software should wait on HSIRDY
+  *         flag to be set indicating that HSI clock is stable and can be used as
+  *         system clock source.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
+  *         clock cycles.
+  */
+#define __HAL_RCC_HSI_ENABLE()  SET_BIT(RCC->CR, RCC_CR_HSION)
+#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
+
+
+/** @brief  Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
+  * @note   The calibration is used to compensate for the variations in voltage
+  *         and temperature that influence the frequency of the internal HSI RC.
+  * @param  __HSICalibrationValue__: specifies the calibration trimming value.
+  *         This parameter must be a number between 0 and 0x7F (3F for Rev Y device).
+  */
+#if defined(RCC_VER_X)
+#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__)                                                                   \
+           do {                                                                                                                          \
+              if(HAL_GetREVID() <= REV_ID_Y)                                                                                             \
+             {                                                                                                                           \
+               MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk, (uint32_t)(__HSICalibrationValue__) << HAL_RCC_REV_Y_HSITRIM_Pos);    \
+             }                                                                                                                           \
+             else                                                                                                                        \
+             {                                                                                                                           \
+               MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_HSICFGR_HSITRIM_Pos);            \
+             }                                                                                                                           \
+           } while(0)
+
+#else
+#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__)                                                                   \
+               MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_HSICFGR_HSITRIM_Pos);
+#endif /*RCC_VER_X*/
+/**
+  * @brief    Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
+  *           in STOP mode to be quickly available as kernel clock for some peripherals.
+  * @note     Keeping the HSI ON in STOP mode allows to avoid slowing down the communication
+  *           speed because of the HSI start-up time.
+  * @note     The enable of this function has not effect on the HSION bit.
+  *           This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+#define __HAL_RCC_HSISTOP_ENABLE()     SET_BIT(RCC->CR, RCC_CR_HSIKERON)
+#define __HAL_RCC_HSISTOP_DISABLE()    CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
+
+
+/**
+  * @brief  Macro to enable or disable the Internal High Speed oscillator for USB (HSI48).
+  * @note   After enabling the HSI48, the application software should wait on
+  *         HSI48RDY flag to be set indicating that HSI48 clock is stable and can
+  *         be used to clock the USB.
+  * @note   The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
+  */
+#define __HAL_RCC_HSI48_ENABLE()    SET_BIT(RCC->CR, RCC_CR_HSI48ON);
+
+#define __HAL_RCC_HSI48_DISABLE()   CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON);
+
+/**
+  * @brief  Macros to enable or disable the Internal  oscillator (CSI).
+  * @note     The CSI is stopped by hardware when entering STOP and STANDBY modes.
+  *           It is used (enabled by hardware) as system clock source after
+  *           start-up from Reset, wakeup from STOP and STANDBY mode, or in case
+  *           of failure of the HSE used directly or indirectly as system clock
+  *           (if the Clock Security System CSS is enabled).
+  * @note     CSI can not be stopped if it is used as system clock source.
+  *           In this case, you have to select another source of the system
+  *           clock then stop the CSI.
+  * @note     After enabling the CSI, the application software should wait on
+  *           CSIRDY flag to be set indicating that CSI clock is stable and can
+  *           be used as system clock source.
+  * @note     When the CSI is stopped, CSIRDY flag goes low after 6 CSI oscillator
+  *           clock cycles.
+  */
+#define __HAL_RCC_CSI_ENABLE()  SET_BIT(RCC->CR, RCC_CR_CSION)
+#define __HAL_RCC_CSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSION)
+
+/** @brief  Macro Adjusts the Internal  oscillator (CSI) calibration value.
+  * @note   The calibration is used to compensate for the variations in voltage
+  *         and temperature that influence the frequency of the internal CSI RC.
+  * @param  __CSICalibrationValue__: specifies the calibration trimming value.
+  *         This parameter must be a number between 0 and 0x1F.
+  */
+#if defined(RCC_VER_X)
+#define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__)                                                                   \
+           do {                                                                                                                          \
+             if(HAL_GetREVID() <= REV_ID_Y)                                                                                              \
+             {                                                                                                                           \
+               MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk, (uint32_t)(__CSICalibrationValue__) << HAL_RCC_REV_Y_CSITRIM_Pos);    \
+             }                                                                                                                           \
+             else                                                                                                                        \
+             {                                                                                                                           \
+               MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, (uint32_t)(__CSICalibrationValue__) << RCC_CSICFGR_CSITRIM_Pos);            \
+             }                                                                                                                           \
+           } while(0)
+
+#else
+#define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__)                                                                   \
+           do {                                                                                                                          \
+               MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, (uint32_t)(__CSICalibrationValue__) << RCC_CSICFGR_CSITRIM_Pos);            \
+               } while(0)
+
+#endif /*RCC_VER_X*/
+/**
+  * @brief    Macros to enable or disable the force of the Low-power Internal oscillator (CSI)
+  *           in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
+  * @note     Keeping the CSI ON in STOP mode allows to avoid slowing down the communication
+  *           speed because of the CSI start-up time.
+  * @note     The enable of this function has not effect on the CSION bit.
+  *           This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+#define __HAL_RCC_CSISTOP_ENABLE()     SET_BIT(RCC->CR, RCC_CR_CSIKERON)
+#define __HAL_RCC_CSISTOP_DISABLE()    CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON)
+
+
+/** @brief  Macros to enable or disable the Internal Low Speed oscillator (LSI).
+  * @note   After enabling the LSI, the application software should wait on
+  *         LSIRDY flag to be set indicating that LSI clock is stable and can
+  *         be used to clock the IWDG and/or the RTC.
+  * @note   LSI can not be disabled if the IWDG is running.
+  * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
+  *         clock cycles.
+  */
+#define __HAL_RCC_LSI_ENABLE()         SET_BIT(RCC->CSR, RCC_CSR_LSION)
+#define __HAL_RCC_LSI_DISABLE()        CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
+
+/**
+  * @brief  Macro to configure the External High Speed oscillator (__HSE__).
+  * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
+  *         software should wait on HSERDY flag to be set indicating that HSE clock
+  *         is stable and can be used to clock the PLL and/or system clock.
+  * @note   HSE state can not be changed if it is used directly or through the
+  *         PLL as system clock. In this case, you have to select another source
+  *         of the system clock then change the HSE state (ex. disable it).
+  * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
+  * @note   This function reset the CSSON bit, so if the clock security system(CSS)
+  *         was previously enabled you have to enable it again after calling this
+  *         function.
+  * @param  __STATE__: specifies the new state of the HSE.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
+  *                              6 HSE oscillator clock cycles.
+  *            @arg RCC_HSE_ON: turn ON the HSE oscillator.
+  *            @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
+  */
+#if defined(RCC_CR_HSEEXT)
+#define __HAL_RCC_HSE_CONFIG(__STATE__)                                \
+                    do {                                               \
+                      if ((__STATE__) == RCC_HSE_ON)                   \
+                      {                                                \
+                        SET_BIT(RCC->CR, RCC_CR_HSEON);                \
+                      }                                                \
+                      else if ((__STATE__) == RCC_HSE_OFF)             \
+                      {                                                \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);              \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT);             \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);             \
+                      }                                                \
+                      else if ((__STATE__) == RCC_HSE_BYPASS)          \
+                      {                                                \
+                        SET_BIT(RCC->CR, RCC_CR_HSEBYP);               \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT);             \
+                        SET_BIT(RCC->CR, RCC_CR_HSEON);                \
+                      }                                                \
+                      else if((__STATE__) == RCC_HSE_BYPASS_DIGITAL)   \
+                      {                                                \
+                        SET_BIT(RCC->CR, RCC_CR_HSEBYP);               \
+                        SET_BIT(RCC->CR, RCC_CR_HSEEXT);               \
+                        SET_BIT(RCC->CR, RCC_CR_HSEON);                \
+                      }                                                \
+                      else                                             \
+                      {                                                \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);              \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);             \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT);             \
+                      }                                                \
+                    } while(0)
+#else
+#define __HAL_RCC_HSE_CONFIG(__STATE__)                         \
+                    do {                                        \
+                      if ((__STATE__) == RCC_HSE_ON)            \
+                      {                                         \
+                        SET_BIT(RCC->CR, RCC_CR_HSEON);         \
+                      }                                         \
+                      else if ((__STATE__) == RCC_HSE_OFF)      \
+                      {                                         \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);       \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);      \
+                      }                                         \
+                      else if ((__STATE__) == RCC_HSE_BYPASS)   \
+                      {                                         \
+                        SET_BIT(RCC->CR, RCC_CR_HSEBYP);        \
+                        SET_BIT(RCC->CR, RCC_CR_HSEON);         \
+                      }                                         \
+                      else                                      \
+                      {                                         \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);       \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);      \
+                      }                                         \
+                    } while(0)
+#endif /* RCC_CR_HSEEXT */
+
+/** @defgroup RCC_LSE_Configuration LSE Configuration
+  * @{
+  */
+
+/**
+  * @brief  Macro to configure the External Low Speed oscillator (LSE).
+  * @note   Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
+  *         User should request a transition to LSE Off first and then LSE On or LSE Bypass.
+  * @note   The external input clock can have a frequency up to 1 MHz and be low swing (analog) or digital(*).
+            A duty cycle close to 50% is recommended.
+  * @note   As the LSE is in the Backup domain and write access is denied to
+  *         this domain after reset, you have to enable write access using
+  *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE
+  *         (to be done once after reset).
+  * @note   After enabling the LSE (RCC_LSE_ON, RCC_LSE_BYPASS or RCC_LSE_BYPASS_DIGITAL*), the application
+  *         software should wait on LSERDY flag to be set indicating that LSE clock
+  *         is stable and can be used to clock the RTC.
+  * @note   If the RTC is used, the LSE bypass must not be configured in digital mode but in low swing analog mode (*)
+  * @param  __STATE__: specifies the new state of the LSE.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
+  *                              6 LSE oscillator clock cycles.
+  *            @arg RCC_LSE_ON: turn ON the LSE oscillator.
+  *            @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
+  *            @arg RCC_LSE_BYPASS_DIGITAL: LSE oscillator bypassed with external digital clock. (*)
+  *
+  *         (*) Available on some STM32H7 lines only.
+  */
+#if defined(RCC_BDCR_LSEEXT)
+#define __HAL_RCC_LSE_CONFIG(__STATE__) \
+                    do {                                               \
+                      if((__STATE__) == RCC_LSE_ON)                    \
+                      {                                                \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);            \
+                      }                                                \
+                      else if((__STATE__) == RCC_LSE_OFF)              \
+                      {                                                \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);          \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);         \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);         \
+                      }                                                \
+                      else if((__STATE__) == RCC_LSE_BYPASS)           \
+                      {                                                \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);           \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);         \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);            \
+                      }                                                \
+                      else if((__STATE__) == RCC_LSE_BYPASS_DIGITAL)   \
+                      {                                                \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);           \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);           \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);            \
+                      }                                                \
+                      else                                             \
+                      {                                                \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);          \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);         \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);         \
+                      }                                                \
+                    } while(0)
+#else
+
+#define __HAL_RCC_LSE_CONFIG(__STATE__) \
+                    do {                                       \
+                      if((__STATE__) == RCC_LSE_ON)            \
+                      {                                        \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \
+                      }                                        \
+                      else if((__STATE__) == RCC_LSE_OFF)      \
+                      {                                        \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);  \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
+                      }                                        \
+                      else if((__STATE__) == RCC_LSE_BYPASS)   \
+                      {                                        \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);   \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \
+                      }                                        \
+                      else                                     \
+                      {                                        \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);  \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
+                      }                                        \
+                    } while(0)
+
+#endif /* RCC_BDCR_LSEEXT */
+/**
+  * @}
+  */
+
+/** @brief  Macros to enable or disable the the RTC clock.
+  * @note   These macros must be used only after the RTC clock source was selected.
+  */
+#define __HAL_RCC_RTC_ENABLE()         SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
+#define __HAL_RCC_RTC_DISABLE()        CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
+
+/** @brief  Macros to configure the RTC clock (RTCCLK).
+  * @note   As the RTC clock configuration bits are in the Backup domain and write
+  *         access is denied to this domain after reset, you have to enable write
+  *         access using the Power Backup Access macro before to configure
+  *         the RTC clock source (to be done once after reset).
+  * @note   Once the RTC clock is configured it can't be changed unless the
+  *         Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
+  *         a Power On Reset (POR).
+  * @param  __RTCCLKSource__: specifies the RTC clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
+  *            @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
+  *            @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
+  *                                            as RTC clock, where x:[2,31]
+  * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
+  *         work in STOP and STANDBY modes, and can be used as wakeup source.
+  *         However, when the HSE clock is used as RTC clock source, the RTC
+  *         cannot be used in STOP and STANDBY modes.
+  * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as
+  *         RTC clock source).
+  */
+#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ?    \
+                                                 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, (((__RTCCLKSource__) & 0xFFFFCFFU) >> 4)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
+
+#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__);    \
+                                                    RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU);  \
+                                                   } while (0)
+
+#define  __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
+
+
+/** @brief  Macros to force or release the Backup domain reset.
+  * @note   This function resets the RTC peripheral (including the backup registers)
+  *         and the RTC clock source selection in RCC_BDCR register.
+  * @note   The BKPSRAM is not affected by this reset.
+  */
+#define __HAL_RCC_BACKUPRESET_FORCE()   SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
+#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
+
+/** @brief  Macros to enable or disable the main PLL.
+  * @note   After enabling the main PLL, the application software should wait on
+  *         PLLRDY flag to be set indicating that PLL clock is stable and can
+  *         be used as system clock source.
+  * @note   The main PLL can not be disabled if it is used as system clock source
+  * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.
+  */
+#define __HAL_RCC_PLL_ENABLE()         SET_BIT(RCC->CR, RCC_CR_PLL1ON)
+#define __HAL_RCC_PLL_DISABLE()        CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON)
+
+/**
+  * @brief  Enables or disables each clock output (PLL_P_CLK, PLL_Q_CLK, PLL_R_CLK)
+  * @note   Enabling/disabling  those Clocks can be done only when the PLL is disabled.
+  *         This is mainly used to save Power.
+  *        (The ck_pll_p of the System PLL cannot be stopped if used as System Clock).
+  * @param  __RCC_PLL1ClockOut__: specifies the PLL clock to be outputted
+  *          This parameter can be one of the following values:
+  *            @arg RCC_PLL1_DIVP: This clock is used to generate system clock up to 400MHZ or 280MHZ(*)
+  *            @arg RCC_PLL1_DIVQ: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
+  *            @arg RCC_PLL1_DIVR: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
+  *
+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  *
+  * @retval None
+  */
+#define __HAL_RCC_PLLCLKOUT_ENABLE(__RCC_PLL1ClockOut__)   SET_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__))
+
+#define __HAL_RCC_PLLCLKOUT_DISABLE(__RCC_PLL1ClockOut__)  CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__))
+
+
+/**
+  * @brief  Enables or disables Fractional Part Of The Multiplication Factor of PLL1 VCO
+  * @note   Enabling/disabling  Fractional Part can be any time  without the need to stop the PLL1
+  * @retval None
+  */
+#define __HAL_RCC_PLLFRACN_ENABLE()   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN)
+
+#define __HAL_RCC_PLLFRACN_DISABLE()  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN)
+
+
+/**
+  * @brief  Macro to configures the main PLL clock source, multiplication and division factors.
+  * @note   This function must be used only when the main PLL is disabled.
+  *
+  * @param  __RCC_PLLSOURCE__: specifies the PLL entry clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_PLLSOURCE_CSI: CSI oscillator clock selected as PLL clock entry
+  *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
+  *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
+  * @note   This clock source (__RCC_PLLSource__) is common for the main PLL1 (main PLL) and PLL2 & PLL3 .
+  *
+  * @param  __PLLM1__: specifies the division factor for PLL VCO input clock
+  *          This parameter must be a number between 1 and 63.
+  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
+  *         frequency ranges from 1 to 16 MHz.
+  *
+  * @param  __PLLN1__: specifies the multiplication factor for PLL VCO output clock
+  *          This parameter must be a number between 4 and 512 or between 8 and 420(*).
+  * @note   You have to set the PLLN parameter correctly to ensure that the VCO
+  *         output frequency is between 150 and 420 MHz (when in medium VCO range) or
+  *         between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range)
+  *
+  * @param  __PLLP1__: specifies the division factor for system  clock.
+  *          This parameter must be a number between 2 and 128 (where odd numbers are not allowed)
+  *
+  * @param  __PLLQ1__: specifies the division factor for peripheral kernel clocks
+  *          This parameter must be a number between 1 and 128
+  *
+  * @param  __PLLR1__: specifies the division factor for peripheral kernel clocks
+  *          This parameter must be a number between 1 and 128
+  *
+  * @note   To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR)
+  *         is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible 
+  *         value to  __PLL1P__, __PLL1Q__ or __PLL1R__ parameters.
+  * @retval None
+  *
+  *  (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  */
+
+
+#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLM1__, __PLLN1__, __PLLP1__, __PLLQ1__,__PLLR1__ ) \
+                  do{ MODIFY_REG(RCC->PLLCKSELR, (RCC_PLLCKSELR_PLLSRC | RCC_PLLCKSELR_DIVM1) , ((__RCC_PLLSOURCE__) | ( (__PLLM1__) <<4U)));  \
+                      WRITE_REG (RCC->PLL1DIVR , ( (((__PLLN1__) - 1U )& RCC_PLL1DIVR_N1) | ((((__PLLP1__) -1U ) << 9U) & RCC_PLL1DIVR_P1) | \
+                                ((((__PLLQ1__) -1U) << 16U)& RCC_PLL1DIVR_Q1) | ((((__PLLR1__) - 1U) << 24U)& RCC_PLL1DIVR_R1))); \
+                    } while(0)
+
+
+/** @brief  Macro to configure the PLLs clock source.
+  * @note   This function must be used only when all PLLs are disabled.
+  * @param  __PLLSOURCE__: specifies the PLLs entry clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PLLSOURCE_CSI: CSI oscillator clock selected as PLL clock entry
+  *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
+  *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
+  *
+  */
+#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, (__PLLSOURCE__))
+
+
+/**
+  * @brief  Macro to configures the main PLL clock Fractional Part Of The Multiplication Factor
+  *
+  * @note   These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO
+  *
+  * @param  __RCC_PLL1FRACN__: specifies Fractional Part Of The Multiplication Factor for PLL1 VCO
+  *                            It should be a value between 0 and 8191
+  * @note   Warning: The software has to set correctly these bits to insure that the VCO
+  *                  output frequency is between its valid frequency range, which is:
+  *                   192 to 836 MHz or 128 to 560 MHz(*) if PLL1VCOSEL = 0
+  *                   150 to 420 MHz if PLL1VCOSEL = 1.
+  *
+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  *
+  * @retval None
+  */
+ #define  __HAL_RCC_PLLFRACN_CONFIG(__RCC_PLL1FRACN__) MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, (uint32_t)(__RCC_PLL1FRACN__) << RCC_PLL1FRACR_FRACN1_Pos)
+
+
+/** @brief  Macro to select  the PLL1  reference frequency range.
+  * @param  __RCC_PLL1VCIRange__: specifies the PLL1 input frequency range
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PLL1VCIRANGE_0: Range frequency is between 1 and 2 MHz
+  *            @arg RCC_PLL1VCIRANGE_1: Range frequency is between 2 and 4 MHz
+  *            @arg RCC_PLL1VCIRANGE_2: Range frequency is between 4 and 8 MHz
+  *            @arg RCC_PLL1VCIRANGE_3: Range frequency is between 8 and 16 MHz
+  * @retval None
+  */
+#define __HAL_RCC_PLL_VCIRANGE(__RCC_PLL1VCIRange__) \
+                  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, (__RCC_PLL1VCIRange__))
+
+
+/** @brief  Macro to select  the PLL1  reference frequency range.
+  * @param  __RCC_PLL1VCORange__: specifies the PLL1 input frequency range
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PLL1VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*)
+  *            @arg RCC_PLL1VCOMEDIUM: Range frequency is between 150 and 420 MHz
+  *
+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  *
+  * @retval None
+  */
+#define __HAL_RCC_PLL_VCORANGE(__RCC_PLL1VCORange__) \
+                  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, (__RCC_PLL1VCORange__))
+
+
+
+/** @brief  Macro to get the clock source used as system clock.
+  * @retval The clock source used as system clock. The returned value can be one
+  *         of the following:
+  *              - RCC_CFGR_SWS_CSI: CSI used as system clock.
+  *              - RCC_CFGR_SWS_HSI: HSI used as system clock.
+  *              - RCC_CFGR_SWS_HSE: HSE used as system clock.
+  *              - RCC_CFGR_SWS_PLL: PLL used as system clock.
+  */
+#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
+
+
+/**
+  * @brief Macro to configure the system clock source.
+  * @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
+  * This parameter can be one of the following values:
+  *              - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
+  *              - RCC_SYSCLKSOURCE_CSI: CSI oscillator is used as system clock source.
+  *              - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
+  *              - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
+  */
+#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
+
+/** @brief  Macro to get the oscillator used as PLL clock source.
+  * @retval The oscillator used as PLL clock source. The returned value can be one
+  *         of the following:
+  *              - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.
+  *              - RCC_PLLSOURCE_CSI: CSI oscillator is used as PLL clock source.
+  *              - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
+  *              - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
+  */
+#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC))
+
+/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
+  * @{
+  */
+
+/** @brief  Macro to configure the MCO1 clock.
+  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_PLL1QCLK:  PLL1Q clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_HSI48: HSI48 (48MHZ) selected as MCO1 source
+  * @param  __MCODIV__ specifies the MCO clock prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCODIV_1 up to RCC_MCODIV_15  : divider applied to MCO1 clock
+  */
+#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
+                 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
+
+/** @brief  Macro to configure the MCO2 clock.
+  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_PLL2PCLK: PLL2P clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_PLLCLK:  PLL1P clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_CSICLK:  CSI clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_LSICLK:  LSI clock selected as MCO2 source
+  * @param  __MCODIV__ specifies the MCO clock prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCODIV_1 up to RCC_MCODIV_15  : divider applied to MCO2 clock
+  */
+#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
+    MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 7)));
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Macro to configure the External Low Speed oscillator (LSE) drive capability.
+  * @note   As the LSE is in the Backup domain and write access is denied to
+  *         this domain after reset, you have to enable write access using
+  *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE
+  *         (to be done once after reset).
+  * @note   On STM32H7 Rev.B and above devices this can't be updated while LSE is ON.
+  * @param  __LSEDRIVE__: specifies the new state of the LSE drive capability.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.
+  *            @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.
+  *            @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.
+  *            @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.
+  * @retval None
+  */
+#if defined(RCC_VER_X)
+#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
+           do{                                                                                                                                \
+             if((HAL_GetREVID() <= REV_ID_Y) && (((__LSEDRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || ((__LSEDRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH)))  \
+             {                                                                                                                                \
+              MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (~(uint32_t)(__LSEDRIVE__)) & RCC_BDCR_LSEDRV_Msk);                                      \
+             }                                                                                                                                \
+             else                                                                                                                             \
+             {                                                                                                                                \
+               MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__));                                                              \
+             }                                                                                                                                \
+           } while(0)
+#else
+#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
+               MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__));
+#endif /*RCC_VER_X*/
+/**
+  * @brief  Macro to configure the wake up from stop clock.
+  * @param  __RCC_STOPWUCLK__: specifies the clock source used after wake up from stop
+  *         This parameter can be one of the following values:
+  *            @arg RCC_STOP_WAKEUPCLOCK_CSI: CSI selected as system clock source
+  *            @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI selected as system clock source
+  * @retval None
+  */
+#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) \
+                  MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__RCC_STOPWUCLK__))
+
+/**
+  * @brief  Macro to configure the Kernel wake up from stop clock.
+  * @param  __RCC_STOPKERWUCLK__: specifies the Kernel clock source used after wake up from stop
+  *         This parameter can be one of the following values:
+  *            @arg RCC_STOP_KERWAKEUPCLOCK_CSI: CSI selected as Kernel clock source
+  *            @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI selected as Kernel clock source
+  * @retval None
+  */
+#define __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(__RCC_STOPKERWUCLK__) \
+                  MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, (__RCC_STOPKERWUCLK__))
+
+/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
+  * @brief macros to manage the specified RCC Flags and interrupts.
+  * @{
+  */
+/** @brief  Enable RCC interrupt.
+  * @param  __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
+  *         This parameter can be any combination of the following values:
+  *            @arg RCC_IT_LSIRDY: LSI ready interrupt
+  *            @arg RCC_IT_LSERDY: LSE ready interrupt
+  *            @arg RCC_IT_CSIRDY: HSI ready interrupt
+  *            @arg RCC_IT_HSIRDY: HSI ready interrupt
+  *            @arg RCC_IT_HSERDY: HSE ready interrupt
+  *            @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
+  *            @arg RCC_IT_PLLRDY: main PLL ready interrupt
+  *            @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
+  *            @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
+  *            @arg RCC_IT_LSECSS: Clock security system interrupt
+  */
+#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
+
+/** @brief Disable RCC interrupt
+  * @param  __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
+  *         This parameter can be any combination of the following values:
+  *            @arg RCC_IT_LSIRDY: LSI ready interrupt
+  *            @arg RCC_IT_LSERDY: LSE ready interrupt
+  *            @arg RCC_IT_CSIRDY: HSI ready interrupt
+  *            @arg RCC_IT_HSIRDY: HSI ready interrupt
+  *            @arg RCC_IT_HSERDY: HSE ready interrupt
+  *            @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
+  *            @arg RCC_IT_PLLRDY: main PLL ready interrupt
+  *            @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
+  *            @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
+  *            @arg RCC_IT_LSECSS: Clock security system interrupt
+  */
+#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
+
+/** @brief  Clear the RCC's interrupt pending bits
+  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
+  *         This parameter can be any combination of the following values:
+  *            @arg RCC_IT_LSIRDY: LSI ready interrupt
+  *            @arg RCC_IT_LSERDY: LSE ready interrupt
+  *            @arg RCC_IT_CSIRDY: CSI ready interrupt
+  *            @arg RCC_IT_HSIRDY: HSI ready interrupt
+  *            @arg RCC_IT_HSERDY: HSE ready interrupt
+  *            @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
+  *            @arg RCC_IT_PLLRDY: main PLL ready interrupt
+  *            @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
+  *            @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
+  *            @arg RCC_IT_HSECSS: HSE Clock Security interrupt
+  *            @arg RCC_IT_LSECSS: Clock security system interrupt
+  */
+#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
+
+/** @brief  Check the RCC's interrupt has occurred or not.
+  * @param  __INTERRUPT__: specifies the RCC interrupt source to check.
+  *         This parameter can be any combination of the following values:
+  *            @arg RCC_IT_LSIRDY: LSI ready interrupt
+  *            @arg RCC_IT_LSERDY: LSE ready interrupt
+  *            @arg RCC_IT_CSIRDY: CSI ready interrupt
+  *            @arg RCC_IT_HSIRDY: HSI ready interrupt
+  *            @arg RCC_IT_HSERDY: HSE ready interrupt
+  *            @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
+  *            @arg RCC_IT_PLLRDY: main PLL ready interrupt
+  *            @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
+  *            @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
+  *            @arg RCC_IT_HSECSS: HSE Clock Security interrupt
+  *            @arg RCC_IT_LSECSS: Clock security system interrupt
+  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+  */
+#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/** @brief Set RMVF bit to clear the reset flags.
+  */
+#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->RSR |= RCC_RSR_RMVF)
+
+#if defined(DUAL_CORE)
+#define __HAL_RCC_C1_CLEAR_RESET_FLAGS() (RCC_C1->RSR |= RCC_RSR_RMVF)
+
+#define __HAL_RCC_C2_CLEAR_RESET_FLAGS() (RCC_C2->RSR |= RCC_RSR_RMVF)
+#endif /*DUAL_CORE*/
+
+#if defined(DUAL_CORE)
+/** @brief  Check RCC flag is set or not.
+  * @param  __FLAG__: specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
+  *            @arg RCC_FLAG_HSIDIV: HSI divider flag
+  *            @arg RCC_FLAG_CSIRDY: CSI oscillator clock ready
+  *            @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready
+  *            @arg RCC_FLAG_HSERDY:  HSE oscillator clock ready
+  *            @arg RCC_FLAG_D1CKRDY:  Domain1 clock ready
+  *            @arg RCC_FLAG_D2CKRDY:  Domain2 clock ready
+  *            @arg RCC_FLAG_PLLRDY:  PLL1 clock ready
+  *            @arg RCC_FLAG_PLL2RDY: PLL2 clock ready
+  *            @arg RCC_FLAG_PLL3RDY: PLL3 clock ready
+  *            @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
+  *            @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
+  *            @arg RCC_FLAG_C1RST:  CPU reset flag
+  *            @arg RCC_FLAG_C2RST:  CPU2 reset flag
+  *            @arg RCC_FLAG_D1RST:  D1 domain power switch reset flag
+  *            @arg RCC_FLAG_D2RST:  D2 domain power switch reset flag
+  *            @arg RCC_FLAG_BORRST: BOR reset flag
+  *            @arg RCC_FLAG_PINRST: Pin reset
+  *            @arg RCC_FLAG_PORRST: POR/PDR  reset
+  *            @arg RCC_FLAG_SFTR1ST: System reset from CPU reset flag
+  *            @arg RCC_FLAG_SFTR2ST: System reset from CPU2 reset flag
+  *            @arg RCC_FLAG_BORRST:   D2 domain power switch reset flag
+  *            @arg RCC_FLAG_IWDG1RST: CPU Independent Watchdog reset
+  *            @arg RCC_FLAG_IWDG2RST: CPU2 Independent Watchdog reset
+  *            @arg RCC_FLAG_WWDG2RST: Window Watchdog2 reset
+  *            @arg RCC_FLAG_WWDG1RST: Window Watchdog1 reset
+  *            @arg RCC_FLAG_LPWR1RST: Reset due to illegal D1 DSTANDBY or CPU CSTOP flag
+  *            @arg RCC_FLAG_LPWR2RST: Reset due to illegal D2 DSTANDBY or CPU2 CSTOP flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define RCC_FLAG_MASK  ((uint8_t)0x1F)
+#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
+((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC->RSR :RCC->CIFR))))  & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
+
+#define __HAL_RCC_C1_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
+((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC_C1->RSR :RCC->CIFR))))  & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
+
+#define __HAL_RCC_C2_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
+((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC_C2->RSR :RCC->CIFR))))  & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
+
+#else
+
+/** @brief  Check RCC flag is set or not.
+  * @param  __FLAG__: specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
+  *            @arg RCC_FLAG_HSIDIV: HSI divider flag
+  *            @arg RCC_FLAG_CSIRDY: CSI oscillator clock ready
+  *            @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready
+  *            @arg RCC_FLAG_HSERDY:  HSE oscillator clock ready
+  *            @arg RCC_FLAG_D1CKRDY:  Domain1 clock ready (*)
+  *            @arg RCC_FLAG_D2CKRDY:  Domain2 clock ready (*)
+  *            @arg RCC_FLAG_CPUCKRDY: CPU Domain clock ready (CPU, APB3, bus matrix1 and related memories) (*)
+  *            @arg RCC_FLAG_CDCKRDY:  CPU Domain clock ready (*)
+  *            @arg RCC_FLAG_PLLRDY:  PLL1 clock ready
+  *            @arg RCC_FLAG_PLL2RDY: PLL2 clock ready
+  *            @arg RCC_FLAG_PLL3RDY: PLL3 clock ready
+  *            @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
+  *            @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
+  *            @arg RCC_FLAG_CPURST: CPU reset flag
+  *            @arg RCC_FLAG_D1RST:  D1 domain power switch reset flag (*)
+  *            @arg RCC_FLAG_D2RST:  D2 domain power switch reset flag (*)
+  *            @arg RCC_FLAG_CDRST:  CD domain power switch reset flag (*)
+  *            @arg RCC_FLAG_BORRST: BOR reset flag
+  *            @arg RCC_FLAG_PINRST: Pin reset
+  *            @arg RCC_FLAG_PORRST: POR/PDR  reset
+  *            @arg RCC_FLAG_SFTRST: System reset from CPU reset flag
+  *            @arg RCC_FLAG_BORRST:   D2 domain power switch reset flag
+  *            @arg RCC_FLAG_IWDG1RST: CPU Independent Watchdog reset
+  *            @arg RCC_FLAG_WWDG1RST: Window Watchdog1 reset
+  *            @arg RCC_FLAG_LPWR1RST: Reset due to illegal D1 DSTANDBY or CPU CSTOP flag
+  *            @arg RCC_FLAG_LPWR2RST: Reset due to illegal D2 DSTANDBY flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  *
+  *  (*) Available on some STM32H7 lines only.
+  */
+#define RCC_FLAG_MASK  ((uint8_t)0x1F)
+#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
+((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC->RSR :RCC->CIFR))))  & (1UL << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
+#endif /*DUAL_CORE*/
+
+/**
+  * @}
+  */
+
+#define RCC_GET_PLL_OSCSOURCE() ((RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC) >> RCC_PLLCKSELR_PLLSRC_Pos)
+
+/**
+  * @}
+  */
+
+/* Include RCC HAL Extension module */
+#include "stm32h7xx_hal_rcc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+ /** @addtogroup RCC_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup RCC_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de-initialization functions  ******************************/
+HAL_StatusTypeDef HAL_RCC_DeInit(void);
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
+
+/**
+  * @}
+  */
+
+/** @addtogroup RCC_Exported_Functions_Group2
+  * @{
+  */
+/* Peripheral Control functions  ************************************************/
+void     HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
+void     HAL_RCC_EnableCSS(void);
+void     HAL_RCC_DisableCSS(void);
+uint32_t HAL_RCC_GetSysClockFreq(void);
+uint32_t HAL_RCC_GetHCLKFreq(void);
+uint32_t HAL_RCC_GetPCLK1Freq(void);
+uint32_t HAL_RCC_GetPCLK2Freq(void);
+void     HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
+void     HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
+/* CSS NMI IRQ handler */
+void     HAL_RCC_NMI_IRQHandler(void);
+/* User Callbacks in non blocking mode (IT mode) */
+void     HAL_RCC_CCSCallback(void);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RCC_Private_Constants RCC Private Constants
+  * @{
+  */
+
+#define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT
+#define HSI_TIMEOUT_VALUE          (2U)    /* 2 ms */
+#define HSI48_TIMEOUT_VALUE        (2U)    /* 2 ms */
+#define CSI_TIMEOUT_VALUE          (2U)    /* 2 ms */
+#define LSI_TIMEOUT_VALUE          (2U)    /* 2 ms */
+#define PLL_TIMEOUT_VALUE          (2U)    /* 2 ms */
+#define CLOCKSWITCH_TIMEOUT_VALUE  (5000U) /* 5 s  */
+#define RCC_DBP_TIMEOUT_VALUE      (100U)
+#define RCC_LSE_TIMEOUT_VALUE      LSE_STARTUP_TIMEOUT
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RCC_Private_Macros RCC Private Macros
+  * @{
+  */
+
+/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
+  * @{
+  */
+
+#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE)                           || \
+                                           (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
+                                           (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
+                                           (((OSCILLATOR) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) || \
+                                           (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
+                                           (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \
+                                           (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48))
+
+#if defined(RCC_CR_HSEEXT)
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
+                         ((HSE) == RCC_HSE_BYPASS) || ((HSE) == RCC_HSE_BYPASS_DIGITAL))
+#else
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
+                         ((HSE) == RCC_HSE_BYPASS))
+#endif /* RCC_CR_HSEEXT */
+
+#if defined(RCC_BDCR_LSEEXT)
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
+                         ((LSE) == RCC_LSE_BYPASS) || ((LSE) == RCC_LSE_BYPASS_DIGITAL))
+#else
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
+                         ((LSE) == RCC_LSE_BYPASS))
+#endif /* RCC_BDCR_LSEEXT */
+
+#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON)    || \
+                         ((HSI) == RCC_HSI_DIV1) || ((HSI) == RCC_HSI_DIV2) || \
+                         ((HSI) == RCC_HSI_DIV4) || ((HSI) == RCC_HSI_DIV8))
+
+#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON))
+
+#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
+
+#define IS_RCC_CSI(CSI) (((CSI) == RCC_CSI_OFF) || ((CSI) == RCC_CSI_ON))
+
+#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || \
+                         ((PLL) == RCC_PLL_ON))
+
+#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_CSI)  || \
+                                  ((SOURCE) == RCC_PLLSOURCE_HSI)  || \
+                                  ((SOURCE) == RCC_PLLSOURCE_NONE) || \
+                                  ((SOURCE) == RCC_PLLSOURCE_HSE))
+#define IS_RCC_PLLM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))
+#if !defined(RCC_VER_2_0)
+#define IS_RCC_PLLN_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))
+#else
+#define IS_RCC_PLLN_VALUE(VALUE) ((8U <= (VALUE)) && ((VALUE) <= 420U))
+#endif /* !RCC_VER_2_0 */
+#define IS_RCC_PLLP_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
+#define IS_RCC_PLLQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
+#define IS_RCC_PLLR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
+
+#define IS_RCC_PLLCLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL1_DIVP) || \
+                                         ((VALUE) == RCC_PLL1_DIVQ) || \
+                                         ((VALUE) == RCC_PLL1_DIVR))
+
+#define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 0x3FU))
+
+#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_CSI) || \
+                                     ((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
+                                     ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
+                                     ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
+
+#define IS_RCC_SYSCLK(SYSCLK) (((SYSCLK) == RCC_SYSCLK_DIV1)   || ((SYSCLK) == RCC_SYSCLK_DIV2)   || \
+                               ((SYSCLK) == RCC_SYSCLK_DIV4)   || ((SYSCLK) == RCC_SYSCLK_DIV8)   || \
+                               ((SYSCLK) == RCC_SYSCLK_DIV16)  || ((SYSCLK) == RCC_SYSCLK_DIV64)  || \
+                               ((SYSCLK) == RCC_SYSCLK_DIV128) || ((SYSCLK) == RCC_SYSCLK_DIV256) || \
+                               ((SYSCLK) == RCC_SYSCLK_DIV512))
+
+
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_HCLK_DIV1)   || ((HCLK) == RCC_HCLK_DIV2)   || \
+                           ((HCLK) == RCC_HCLK_DIV4)   || ((HCLK) == RCC_HCLK_DIV8)   || \
+                           ((HCLK) == RCC_HCLK_DIV16)  || ((HCLK) == RCC_HCLK_DIV64)  || \
+                           ((HCLK) == RCC_HCLK_DIV128) || ((HCLK) == RCC_HCLK_DIV256) || \
+                           ((HCLK) == RCC_HCLK_DIV512))
+
+#define IS_RCC_CDPCLK1(CDPCLK1) (((CDPCLK1) == RCC_APB3_DIV1) || ((CDPCLK1) == RCC_APB3_DIV2) || \
+                                 ((CDPCLK1) == RCC_APB3_DIV4) || ((CDPCLK1) == RCC_APB3_DIV8) || \
+                                 ((CDPCLK1) == RCC_APB3_DIV16))
+
+#define IS_RCC_D1PCLK1 IS_RCC_CDPCLK1  /* for legacy compatibility between H7 lines */
+
+#define IS_RCC_PCLK1(PCLK1) (((PCLK1) == RCC_APB1_DIV1) || ((PCLK1) == RCC_APB1_DIV2) || \
+                             ((PCLK1) == RCC_APB1_DIV4) || ((PCLK1) == RCC_APB1_DIV8) || \
+                            ((PCLK1) == RCC_APB1_DIV16))
+
+#define IS_RCC_PCLK2(PCLK2) (((PCLK2) == RCC_APB2_DIV1) || ((PCLK2) == RCC_APB2_DIV2) || \
+                             ((PCLK2) == RCC_APB2_DIV4) || ((PCLK2) == RCC_APB2_DIV8) || \
+                             ((PCLK2) == RCC_APB2_DIV16))
+
+#define IS_RCC_SRDPCLK1(SRDPCLK1) (((SRDPCLK1) == RCC_APB4_DIV1) || ((SRDPCLK1) == RCC_APB4_DIV2) || \
+                                  ((SRDPCLK1) == RCC_APB4_DIV4)  || ((SRDPCLK1) == RCC_APB4_DIV8) || \
+                                  ((SRDPCLK1) == RCC_APB4_DIV16))
+
+#define IS_RCC_D3PCLK1 IS_RCC_SRDPCLK1 /* for legacy compatibility between H7 lines*/
+
+#define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE)       || ((SOURCE) == RCC_RTCCLKSOURCE_LSI)       || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2)  || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3)  || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4)  || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5)  || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6)  || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7)  || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8)  || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9)  || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV33) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV34) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV35) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV36) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV37) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV38) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV39) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV40) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV41) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV42) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV43) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV44) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV45) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV46) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV47) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV48) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV49) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV50) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV51) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV52) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV53) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV54) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV55) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV56) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV57) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV58) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV59) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV60) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV61) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV62) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV63))
+
+#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
+
+#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE)       || \
+                                   ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLL1QCLK)  || \
+                                   ((SOURCE) == RCC_MCO1SOURCE_HSI48))
+
+#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK)    || ((SOURCE) == RCC_MCO2SOURCE_PLL2PCLK) || \
+                                   ((SOURCE) == RCC_MCO2SOURCE_HSE)       || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK)   || \
+                                   ((SOURCE) == RCC_MCO2SOURCE_CSICLK)    || ((SOURCE) == RCC_MCO2SOURCE_LSICLK))
+
+#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1)  || ((DIV) == RCC_MCODIV_2)   || \
+                            ((DIV) == RCC_MCODIV_3)  || ((DIV) == RCC_MCODIV_4)   || \
+                            ((DIV) == RCC_MCODIV_5)  || ((DIV) == RCC_MCODIV_6)   || \
+                            ((DIV) == RCC_MCODIV_7)  || ((DIV) == RCC_MCODIV_8)   || \
+                            ((DIV) == RCC_MCODIV_9)  || ((DIV) == RCC_MCODIV_10)  || \
+                            ((DIV) == RCC_MCODIV_11) || ((DIV) == RCC_MCODIV_12)  || \
+                            ((DIV) == RCC_MCODIV_13) || ((DIV) == RCC_MCODIV_14)  || \
+                            ((DIV) == RCC_MCODIV_15))
+
+#if defined(DUAL_CORE)
+#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY)    || ((FLAG) == RCC_FLAG_CSIRDY)  || \
+                           ((FLAG) == RCC_FLAG_HSI48RDY)  || ((FLAG) == RCC_FLAG_HSERDY)  || \
+                           ((FLAG) == RCC_FLAG_D1CKRDY)   || ((FLAG) == RCC_FLAG_D2CKRDY) || \
+                           ((FLAG) == RCC_FLAG_PLLRDY)    || ((FLAG) == RCC_FLAG_PLL2RDY) || \
+                           ((FLAG) == RCC_FLAG_PLL3RDY)   || ((FLAG) == RCC_FLAG_LSERDY)  || \
+                           ((FLAG) == RCC_FLAG_LSIRDY)    || \
+                           ((FLAG) == RCC_FLAG_C1RST)     || ((FLAG) == RCC_FLAG_C2RST)   || \
+                           ((FLAG) == RCC_FLAG_SFTR2ST)   || ((FLAG) == RCC_FLAG_WWDG2RST)|| \
+                           ((FLAG) == RCC_FLAG_IWDG2RST)  || ((FLAG) == RCC_FLAG_D1RST)   || \
+                           ((FLAG) == RCC_FLAG_D2RST)     || ((FLAG) == RCC_FLAG_BORRST)  || \
+                           ((FLAG) == RCC_FLAG_PINRST)    || ((FLAG) == RCC_FLAG_PORRST)  || \
+                           ((FLAG) == RCC_FLAG_SFTR1ST)   || ((FLAG) == RCC_FLAG_IWDG1RST)|| \
+                           ((FLAG) == RCC_FLAG_WWDG1RST)  || ((FLAG) == RCC_FLAG_LPWR1RST)|| \
+                           ((FLAG) == RCC_FLAG_LPWR2RST)  || ((FLAG) == RCC_FLAG_HSIDIV))
+
+#else
+
+#if defined(RCC_CR_D2CKRDY)
+#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY)    || ((FLAG) == RCC_FLAG_CSIRDY)  || \
+                           ((FLAG) == RCC_FLAG_HSI48RDY)  || ((FLAG) == RCC_FLAG_HSERDY)  || \
+                           ((FLAG) == RCC_FLAG_D1CKRDY)   || ((FLAG) == RCC_FLAG_D2CKRDY) || \
+                           ((FLAG) == RCC_FLAG_PLLRDY)    || ((FLAG) == RCC_FLAG_PLL2RDY) || \
+                           ((FLAG) == RCC_FLAG_PLL3RDY)   || ((FLAG) == RCC_FLAG_LSERDY)  || \
+                           ((FLAG) == RCC_FLAG_LSIRDY)    || \
+                           ((FLAG) == RCC_FLAG_CPURST)    || ((FLAG) == RCC_FLAG_D1RST)   || \
+                           ((FLAG) == RCC_FLAG_D2RST)     || ((FLAG) == RCC_FLAG_BORRST)  || \
+                           ((FLAG) == RCC_FLAG_PINRST)    || ((FLAG) == RCC_FLAG_PORRST)  || \
+                           ((FLAG) == RCC_FLAG_SFTRST)    || ((FLAG) == RCC_FLAG_IWDG1RST)|| \
+                           ((FLAG) == RCC_FLAG_WWDG1RST)  || ((FLAG) == RCC_FLAG_LPWR1RST)|| \
+                           ((FLAG) == RCC_FLAG_LPWR2RST)  || ((FLAG) == RCC_FLAG_HSIDIV ))
+#else
+#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY)    || ((FLAG) == RCC_FLAG_CSIRDY)  || \
+                           ((FLAG) == RCC_FLAG_HSI48RDY)  || ((FLAG) == RCC_FLAG_HSERDY)  || \
+                           ((FLAG) == RCC_FLAG_CPUCKRDY)  || ((FLAG) == RCC_FLAG_CDCKRDY) || \
+                           ((FLAG) == RCC_FLAG_PLLRDY)    || ((FLAG) == RCC_FLAG_PLL2RDY) || \
+                           ((FLAG) == RCC_FLAG_PLL3RDY)   || ((FLAG) == RCC_FLAG_LSERDY)  || \
+                           ((FLAG) == RCC_FLAG_LSIRDY)    || \
+                           ((FLAG) == RCC_FLAG_CDRST)     || ((FLAG) == RCC_FLAG_BORRST)  || \
+                           ((FLAG) == RCC_FLAG_PINRST)    || ((FLAG) == RCC_FLAG_PORRST)  || \
+                           ((FLAG) == RCC_FLAG_SFTRST)    || ((FLAG) == RCC_FLAG_IWDG1RST)|| \
+                           ((FLAG) == RCC_FLAG_WWDG1RST)  || ((FLAG) == RCC_FLAG_LPWR1RST)|| \
+                           ((FLAG) == RCC_FLAG_LPWR2RST)  || ((FLAG) == RCC_FLAG_HSIDIV ))
+#endif /* RCC_CR_D2CKRDY */
+
+#endif /*DUAL_CORE*/
+
+#define IS_RCC_HSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7FU)
+#define IS_RCC_CSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x3FU)
+
+#define IS_RCC_STOP_WAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_WAKEUPCLOCK_CSI) || \
+                                         ((SOURCE) == RCC_STOP_WAKEUPCLOCK_HSI))
+
+#define IS_RCC_STOP_KERWAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_CSI) || \
+                                          ((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_HSI))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_RCC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h
new file mode 100644
index 00000000..42beccc8
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h
@@ -0,0 +1,4262 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_rcc_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of RCC HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_RCC_EX_H
+#define STM32H7xx_HAL_RCC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup RCCEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
+  * @{
+  */
+
+/**
+  * @brief  PLL2 Clock structure definition
+  */
+typedef struct
+{
+
+  uint32_t PLL2M;       /*!< PLL2M: Division factor for PLL2 VCO input clock.
+                             This parameter must be a number between Min_Data = 1 and Max_Data = 63    */
+
+  uint32_t PLL2N;       /*!< PLL2N: Multiplication factor for PLL2 VCO output clock.
+                             This parameter must be a number between Min_Data = 4 and Max_Data = 512
+                             or between Min_Data = 8 and Max_Data = 420(*)
+                             (*) : For stm32h7a3xx and stm32h7b3xx family lines.                       */   
+
+  uint32_t PLL2P;       /*!< PLL2P: Division factor for system clock.
+                             This parameter must be a number between Min_Data = 2 and Max_Data = 128
+                             odd division factors are not allowed                                      */
+
+  uint32_t PLL2Q;        /*!< PLL2Q: Division factor for peripheral clocks.
+                             This parameter must be a number between Min_Data = 1 and Max_Data = 128   */
+
+  uint32_t PLL2R;        /*!< PLL2R: Division factor for peripheral clocks.
+                             This parameter must be a number between Min_Data = 1 and Max_Data = 128   */
+  uint32_t PLL2RGE;      /*!<PLL2RGE: PLL2 clock Input range
+                          This parameter must be a value of @ref RCC_PLL2_VCI_Range                    */
+  uint32_t PLL2VCOSEL;   /*!<PLL2VCOSEL: PLL2 clock Output range
+                          This parameter must be a value of @ref RCC_PLL2_VCO_Range                    */
+
+  uint32_t PLL2FRACN;    /*!<PLL2FRACN: Specifies Fractional Part Of The Multiplication Factor for
+                            PLL2 VCO It should be a value between 0 and 8191                           */
+}RCC_PLL2InitTypeDef;
+
+/**
+  * @brief  PLL3 Clock structure definition
+  */
+typedef struct
+{
+
+  uint32_t PLL3M;       /*!< PLL3M: Division factor for PLL3 VCO input clock.
+                             This parameter must be a number between Min_Data = 1 and Max_Data = 63    */
+
+  uint32_t PLL3N;       /*!< PLL3N: Multiplication factor for PLL3 VCO output clock.
+                             This parameter must be a number between Min_Data = 4 and Max_Data = 512
+                             or between Min_Data = 8 and Max_Data = 420(*)
+                             (*) : For stm32h7a3xx and stm32h7b3xx family lines.                       */  
+
+  uint32_t PLL3P;       /*!< PLL3P: Division factor for system clock.
+                             This parameter must be a number between Min_Data = 2 and Max_Data = 128
+                             odd division factors are not allowed                                      */
+
+  uint32_t PLL3Q;        /*!< PLL3Q: Division factor for peripheral clocks.
+                             This parameter must be a number between Min_Data = 1 and Max_Data = 128   */
+
+  uint32_t PLL3R;        /*!< PLL3R: Division factor for peripheral clocks.
+                             This parameter must be a number between Min_Data = 1 and Max_Data = 128   */
+  uint32_t PLL3RGE;      /*!<PLL3RGE: PLL3 clock Input range
+                          This parameter must be a value of @ref RCC_PLL3_VCI_Range                    */
+  uint32_t PLL3VCOSEL;   /*!<PLL3VCOSEL: PLL3 clock Output range
+                          This parameter must be a value of @ref RCC_PLL3_VCO_Range                    */
+
+  uint32_t PLL3FRACN;    /*!<PLL3FRACN: Specifies Fractional Part Of The Multiplication Factor for
+                            PLL3 VCO It should be a value between 0 and 8191                           */
+}RCC_PLL3InitTypeDef;
+
+/**
+  * @brief  RCC PLL1 Clocks structure definition
+  */
+typedef struct
+{
+  uint32_t PLL1_P_Frequency;
+  uint32_t PLL1_Q_Frequency;
+  uint32_t PLL1_R_Frequency;
+}PLL1_ClocksTypeDef;
+
+/**
+  * @brief  RCC PLL2 Clocks structure definition
+  */
+typedef struct
+{
+  uint32_t PLL2_P_Frequency;
+  uint32_t PLL2_Q_Frequency;
+  uint32_t PLL2_R_Frequency;
+}PLL2_ClocksTypeDef;
+
+/**
+  * @brief  RCC PLL3 Clocks structure definition
+  */
+typedef struct
+{
+  uint32_t PLL3_P_Frequency;
+  uint32_t PLL3_Q_Frequency;
+  uint32_t PLL3_R_Frequency;
+}PLL3_ClocksTypeDef;
+
+
+/**
+  * @brief  RCC extended clocks structure definition
+  */
+typedef struct
+{
+  uint32_t PeriphClockSelection;   /*!< The Extended Clock to be configured.
+                                        This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+  RCC_PLL2InitTypeDef PLL2;        /*!< PLL2structure parameters.
+                                        This parameter will be used only when PLL2 is selected as kernel clock Source for some peripherals */
+
+  RCC_PLL3InitTypeDef PLL3;        /*!< PLL3 structure parameters.
+                                        This parameter will be used only when PLL2 is selected as kernel clock Source for some peripherals */
+
+  uint32_t FmcClockSelection;     /*!< Specifies FMC clock source
+                                        This parameter can be a value of @ref RCCEx_FMC_Clock_Source     */
+
+#if defined(QUADSPI)
+  uint32_t QspiClockSelection;    /*!< Specifies QSPI clock source
+                                        This parameter can be a value of @ref RCCEx_QSPI_Clock_Source    */
+#endif /* QUADSPI */
+
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+  uint32_t OspiClockSelection;    /*!< Specifies OSPI clock source
+                                        This parameter can be a value of @ref RCCEx_OSPI_Clock_Source    */
+#endif /*(OCTOSPI1) || (OCTOSPI2)*/
+
+
+#if defined(DSI)
+  uint32_t DsiClockSelection;     /*!< Specifies DSI clock source
+                                     This parameter can be a value of @ref RCCEx_DSI_Clock_Source        */
+#endif /* DSI */
+
+  uint32_t SdmmcClockSelection;    /*!< Specifies SDMMC clock source
+                                        This parameter can be a value of @ref RCCEx_SDMMC_Clock_Source   */
+
+  uint32_t CkperClockSelection;   /*!< Specifies CKPER clock source
+                                        This parameter can be a value of @ref RCCEx_CLKP_Clock_Source   */
+
+  uint32_t Sai1ClockSelection;     /*!< Specifies SAI1 clock source
+                                        This parameter can be a value of @ref RCCEx_SAI1_Clock_Source    */
+
+#if defined(SAI3)
+  uint32_t Sai23ClockSelection;     /*!< Specifies SAI2/3 clock source
+                                         This parameter can be a value of @ref RCCEx_SAI23_Clock_Source  */
+#endif /* SAI3 */
+
+#if defined(RCC_CDCCIP1R_SAI2ASEL)
+  uint32_t Sai2AClockSelection;     /*!< Specifies SAI2A clock source
+                                        This parameter can be a value of @ref RCCEx_SAI2A_Clock_Source  */
+#endif /* RCC_CDCCIP1R_SAI2ASEL */
+
+#if defined(RCC_CDCCIP1R_SAI2BSEL)
+  uint32_t Sai2BClockSelection;     /*!< Specifies SAI2B clock source
+                                         This parameter can be a value of @ref RCCEx_SAI2B_Clock_Source    */
+#endif /* RCC_CDCCIP1R_SAI2BSEL */
+
+  uint32_t Spi123ClockSelection;     /*!< Specifies SPI1/2/3 clock source
+                                          This parameter can be a value of @ref RCCEx_SPI123_Clock_Source    */
+
+  uint32_t Spi45ClockSelection;     /*!< Specifies SPI4/5 clock source
+                                         This parameter can be a value of @ref RCCEx_SPI45_Clock_Source    */
+
+  uint32_t SpdifrxClockSelection;   /*!< Specifies SPDIFRX Clock clock source
+                                        This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */
+
+  uint32_t Dfsdm1ClockSelection;    /*!< Specifies DFSDM1 Clock clock source
+                                        This parameter can be a value of @ref RCCEx_DFSDM1_Clock_Source  */
+
+#if defined(DFSDM2_BASE)
+  uint32_t Dfsdm2ClockSelection;    /*!< Specifies DFSDM2 Clock clock source
+                                        This parameter can be a value of @ref RCCEx_DFSDM2_Clock_Source  */
+#endif /* DFSDM2_BASE */
+
+#if defined(FDCAN1) || defined(FDCAN2)
+  uint32_t FdcanClockSelection;   /*!< Specifies FDCAN Clock clock source
+                                        This parameter can be a value of @ref RCCEx_FDCAN_Clock_Source   */
+#endif /*FDCAN1 || FDCAN2*/
+
+  uint32_t Swpmi1ClockSelection;   /*!< Specifies SWPMI1 Clock clock source
+                                        This parameter can be a value of @ref RCCEx_SWPMI1_Clock_Source  */
+
+  uint32_t Usart234578ClockSelection;   /*!< Specifies USART2/3/4/5/7/8 clock source
+                                             This parameter can be a value of @ref RCCEx_USART234578_Clock_Source  */
+
+  uint32_t Usart16ClockSelection;  /*!< Specifies USART1/6 clock source
+                                        This parameter can be a value of @ref RCCEx_USART16_Clock_Source  */
+
+   uint32_t RngClockSelection;      /*!< Specifies RNG clock source
+                                        This parameter can be a value of @ref RCCEx_RNG_Clock_Source     */
+
+   uint32_t I2c123ClockSelection;   /*!< Specifies I2C1/2/3 clock source
+                                        This parameter can be a value of @ref RCCEx_I2C123_Clock_Source    */
+
+  uint32_t UsbClockSelection;      /*!< Specifies USB clock source
+                                        This parameter can be a value of @ref RCCEx_USB_Clock_Source     */
+
+  uint32_t CecClockSelection;     /*!< Specifies CEC clock source
+                                        This parameter can be a value of @ref RCCEx_CEC_Clock_Source     */
+
+  uint32_t Lptim1ClockSelection;   /*!< Specifies LPTIM1 clock source
+                                        This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source  */
+
+  uint32_t Lpuart1ClockSelection;  /*!< Specifies LPUART1 clock source
+                                        This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
+
+  uint32_t I2c4ClockSelection;     /*!< Specifies I2C4 clock source
+                                        This parameter can be a value of @ref RCCEx_I2C4_Clock_Source    */
+
+  uint32_t Lptim2ClockSelection;   /*!< Specifies LPTIM2 clock source
+                                        This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source  */
+
+  uint32_t Lptim345ClockSelection;   /*!< Specifies LPTIM3/4/5 clock source
+                                          This parameter can be a value of @ref RCCEx_LPTIM345_Clock_Source  */
+
+  uint32_t AdcClockSelection;      /*!< Specifies ADC interface clock source
+                                        This parameter can be a value of @ref RCCEx_ADC_Clock_Source     */
+#if defined(SAI4)
+  uint32_t Sai4AClockSelection;     /*!< Specifies SAI4A clock source
+                                        This parameter can be a value of @ref RCCEx_SAI4A_Clock_Source   */
+
+  uint32_t Sai4BClockSelection;     /*!< Specifies SAI4B clock source
+                                        This parameter can be a value of @ref RCCEx_SAI4B_Clock_Source   */
+#endif /* SAI4 */
+
+  uint32_t Spi6ClockSelection;     /*!< Specifies SPI6 clock source
+                                        This parameter can be a value of @ref RCCEx_SPI6_Clock_Source    */
+
+  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock clock source
+                                        This parameter can be a value of @ref RCC_RTC_Clock_Source       */
+
+#if defined(HRTIM1)
+  uint32_t Hrtim1ClockSelection;      /*!< Specifies HRTIM1 Clock clock source
+                                        This parameter can be a value of @ref RCCEx_HRTIM1_Clock_Source   */
+#endif /* HRTIM1 */
+
+  uint32_t TIMPresSelection;       /*!< Specifies TIM Clock Prescalers Selection.
+                                       This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */
+}RCC_PeriphCLKInitTypeDef;
+
+
+/**
+  * @brief RCC_CRS Init structure definition
+  */
+typedef struct
+{
+  uint32_t Prescaler;             /*!< Specifies the division factor of the SYNC signal.
+                                     This parameter can be a value of @ref RCCEx_CRS_SynchroDivider  */
+
+  uint32_t Source;                /*!< Specifies the SYNC signal source.
+                                     This parameter can be a value of @ref RCCEx_CRS_SynchroSource   */
+
+  uint32_t Polarity;              /*!< Specifies the input polarity for the SYNC signal source.
+                                     This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
+
+  uint32_t ReloadValue;           /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
+                                      It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)
+                                     This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
+
+  uint32_t ErrorLimitValue;       /*!< Specifies the value to be used to evaluate the captured frequency error value.
+                                     This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
+
+  uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
+                                     This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
+
+}RCC_CRSInitTypeDef;
+
+/**
+  * @brief RCC_CRS Synchronization structure definition
+  */
+typedef struct
+{
+  uint32_t ReloadValue;           /*!< Specifies the value loaded in the Counter reload value.
+                                     This parameter must be a number between 0 and 0xFFFF */
+
+  uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
+                                     This parameter must be a number between 0 and 0x3F */
+
+  uint32_t FreqErrorCapture;      /*!< Specifies the value loaded in the .FECAP, the frequency error counter
+                                                                    value latched in the time of the last SYNC event.
+                                    This parameter must be a number between 0 and 0xFFFF */
+
+  uint32_t FreqErrorDirection;    /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
+                                                                    frequency error counter latched in the time of the last SYNC event.
+                                                                    It shows whether the actual frequency is below or above the target.
+                                    This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
+
+}RCC_CRSSynchroInfoTypeDef;
+
+/**
+  * @}
+  */
+
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Constants  RCCEx Exported Constants
+  * @{
+  */
+
+/** @defgroup RCCEx_Periph_Clock_Selection  RCCEx Periph Clock Selection
+  * @{
+  */
+
+#if defined(UART9) && defined(USART10)
+#define RCC_PERIPHCLK_USART16910       (0x00000001U)
+#define RCC_PERIPHCLK_USART1           RCC_PERIPHCLK_USART16910
+#define RCC_PERIPHCLK_USART6           RCC_PERIPHCLK_USART16910
+#define RCC_PERIPHCLK_UART9            RCC_PERIPHCLK_USART16910
+#define RCC_PERIPHCLK_USART10          RCC_PERIPHCLK_USART16910
+/*alias*/
+#define RCC_PERIPHCLK_USART16          RCC_PERIPHCLK_USART16910
+#else
+#define RCC_PERIPHCLK_USART16          (0x00000001U)
+#define RCC_PERIPHCLK_USART1           RCC_PERIPHCLK_USART16
+#define RCC_PERIPHCLK_USART6           RCC_PERIPHCLK_USART16
+/* alias */
+#define RCC_PERIPHCLK_USART16910       RCC_PERIPHCLK_USART16
+#endif /* UART9 && USART10*/
+#define RCC_PERIPHCLK_USART234578      (0x00000002U)
+#define RCC_PERIPHCLK_USART2           RCC_PERIPHCLK_USART234578
+#define RCC_PERIPHCLK_USART3           RCC_PERIPHCLK_USART234578
+#define RCC_PERIPHCLK_UART4            RCC_PERIPHCLK_USART234578
+#define RCC_PERIPHCLK_UART5            RCC_PERIPHCLK_USART234578
+#define RCC_PERIPHCLK_UART7            RCC_PERIPHCLK_USART234578
+#define RCC_PERIPHCLK_UART8            RCC_PERIPHCLK_USART234578
+#define RCC_PERIPHCLK_LPUART1          (0x00000004U)
+#define RCC_PERIPHCLK_I2C123           (0x00000008U)
+#define RCC_PERIPHCLK_I2C1             RCC_PERIPHCLK_I2C123
+#define RCC_PERIPHCLK_I2C2             RCC_PERIPHCLK_I2C123
+#define RCC_PERIPHCLK_I2C3             RCC_PERIPHCLK_I2C123
+#define RCC_PERIPHCLK_I2C4             (0x00000010U)
+#define RCC_PERIPHCLK_LPTIM1           (0x00000020U)
+#define RCC_PERIPHCLK_LPTIM2           (0x00000040U)
+#define RCC_PERIPHCLK_LPTIM345         (0x00000080U)
+#define RCC_PERIPHCLK_LPTIM3           RCC_PERIPHCLK_LPTIM345
+#if defined(LPTIM4)
+#define RCC_PERIPHCLK_LPTIM4           RCC_PERIPHCLK_LPTIM345
+#endif /*LPTIM4*/
+#if defined(LPTIM5)
+#define RCC_PERIPHCLK_LPTIM5           RCC_PERIPHCLK_LPTIM345
+#endif /*LPTIM5*/
+#define RCC_PERIPHCLK_SAI1             (0x00000100U)
+#if defined(SAI3)
+#define RCC_PERIPHCLK_SAI23            (0x00000200U)
+#define RCC_PERIPHCLK_SAI2             RCC_PERIPHCLK_SAI23
+#define RCC_PERIPHCLK_SAI3             RCC_PERIPHCLK_SAI23
+#endif /* SAI3 */
+#if defined(RCC_CDCCIP1R_SAI2ASEL_0)
+#define RCC_PERIPHCLK_SAI2A            (0x00000200U)
+#endif /* RCC_CDCCIP1R_SAI2ASEL_0 */
+#if defined(RCC_CDCCIP1R_SAI2BSEL_0)
+#define RCC_PERIPHCLK_SAI2B            (0x00000400U)
+#endif /* RCC_CDCCIP1R_SAI2BSEL_0 */
+#if defined(SAI4)
+#define RCC_PERIPHCLK_SAI4A            (0x00000400U)
+#define RCC_PERIPHCLK_SAI4B            (0x00000800U)
+#endif /* SAI4 */
+#define RCC_PERIPHCLK_SPI123           (0x00001000U)
+#define RCC_PERIPHCLK_SPI1             RCC_PERIPHCLK_SPI123
+#define RCC_PERIPHCLK_SPI2             RCC_PERIPHCLK_SPI123
+#define RCC_PERIPHCLK_SPI3             RCC_PERIPHCLK_SPI123
+#define RCC_PERIPHCLK_SPI45            (0x00002000U)
+#define RCC_PERIPHCLK_SPI4             RCC_PERIPHCLK_SPI45
+#define RCC_PERIPHCLK_SPI5             RCC_PERIPHCLK_SPI45
+#define RCC_PERIPHCLK_SPI6             (0x00004000U)
+#define RCC_PERIPHCLK_FDCAN            (0x00008000U)
+#define RCC_PERIPHCLK_SDMMC            (0x00010000U)
+#define RCC_PERIPHCLK_RNG              (0x00020000U)
+#define RCC_PERIPHCLK_USB              (0x00040000U)
+#define RCC_PERIPHCLK_ADC              (0x00080000U)
+#define RCC_PERIPHCLK_SWPMI1           (0x00100000U)
+#define RCC_PERIPHCLK_DFSDM1           (0x00200000U)
+#if defined(DFSDM2_BASE)
+#define RCC_PERIPHCLK_DFSDM2           (0x00000800U)
+#endif /* DFSDM2 */
+#define RCC_PERIPHCLK_RTC              (0x00400000U)
+#define RCC_PERIPHCLK_CEC              (0x00800000U)
+#define RCC_PERIPHCLK_FMC              (0x01000000U)
+#if defined(QUADSPI)
+#define RCC_PERIPHCLK_QSPI             (0x02000000U)
+#endif /* QUADSPI */
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+#define RCC_PERIPHCLK_OSPI             (0x02000000U)
+#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
+#define RCC_PERIPHCLK_DSI              (0x04000000U)
+#define RCC_PERIPHCLK_SPDIFRX          (0x08000000U)
+#if defined(HRTIM1)
+#define RCC_PERIPHCLK_HRTIM1           (0x10000000U)
+#endif /* HRTIM1 */
+#if defined(LTDC)
+#define RCC_PERIPHCLK_LTDC             (0x20000000U)
+#endif /* LTDC */
+#define RCC_PERIPHCLK_TIM              (0x40000000U)
+#define RCC_PERIPHCLK_CKPER            (0x80000000U)
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_PLL2_Clock_Output  RCC PLL2 Clock Output
+  * @{
+  */
+#define RCC_PLL2_DIVP                RCC_PLLCFGR_DIVP2EN
+#define RCC_PLL2_DIVQ                RCC_PLLCFGR_DIVQ2EN
+#define RCC_PLL2_DIVR                RCC_PLLCFGR_DIVR2EN
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLL3_Clock_Output  RCC PLL3 Clock Output
+  * @{
+  */
+#define RCC_PLL3_DIVP                RCC_PLLCFGR_DIVP3EN
+#define RCC_PLL3_DIVQ                RCC_PLLCFGR_DIVQ3EN
+#define RCC_PLL3_DIVR                RCC_PLLCFGR_DIVR3EN
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLL2_VCI_Range  RCC PLL2 VCI Range
+  * @{
+  */
+#define RCC_PLL2VCIRANGE_0                RCC_PLLCFGR_PLL2RGE_0        /*!< Clock range frequency between 1 and 2 MHz  */
+#define RCC_PLL2VCIRANGE_1                RCC_PLLCFGR_PLL2RGE_1        /*!< Clock range frequency between 2 and 4 MHz  */
+#define RCC_PLL2VCIRANGE_2                RCC_PLLCFGR_PLL2RGE_2        /*!< Clock range frequency between 4 and 8 MHz  */
+#define RCC_PLL2VCIRANGE_3                RCC_PLLCFGR_PLL2RGE_3        /*!< Clock range frequency between 8 and 16 MHz */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_PLL2_VCO_Range  RCC PLL2 VCO Range
+  * @{
+  */
+#define RCC_PLL2VCOWIDE                 (0x00000000U)
+#define RCC_PLL2VCOMEDIUM               RCC_PLLCFGR_PLL2VCOSEL
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLL3_VCI_Range  RCC PLL3 VCI Range
+  * @{
+  */
+#define RCC_PLL3VCIRANGE_0                RCC_PLLCFGR_PLL3RGE_0         /*!< Clock range frequency between 1 and 2 MHz  */
+#define RCC_PLL3VCIRANGE_1                RCC_PLLCFGR_PLL3RGE_1         /*!< Clock range frequency between 2 and 4 MHz  */
+#define RCC_PLL3VCIRANGE_2                RCC_PLLCFGR_PLL3RGE_2         /*!< Clock range frequency between 4 and 8 MHz  */
+#define RCC_PLL3VCIRANGE_3                RCC_PLLCFGR_PLL3RGE_3         /*!< Clock range frequency between 8 and 16 MHz */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_PLL3_VCO_Range  RCC PLL3 VCO Range
+  * @{
+  */
+#define RCC_PLL3VCOWIDE                 (0x00000000U)
+#define RCC_PLL3VCOMEDIUM               RCC_PLLCFGR_PLL3VCOSEL
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_USART16_Clock_Source  RCCEx USART1/6 Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP2R_USART16SEL)
+#define RCC_USART16CLKSOURCE_D2PCLK2    (0x00000000U)
+/* alias */
+#define RCC_USART16CLKSOURCE_PCLK2        RCC_USART16CLKSOURCE_D2PCLK2
+#define RCC_USART16CLKSOURCE_PLL2         RCC_D2CCIP2R_USART16SEL_0
+#define RCC_USART16CLKSOURCE_PLL3         RCC_D2CCIP2R_USART16SEL_1
+#define RCC_USART16CLKSOURCE_HSI         (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_1)
+#define RCC_USART16CLKSOURCE_CSI          RCC_D2CCIP2R_USART16SEL_2
+#define RCC_USART16CLKSOURCE_LSE         (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_2)
+
+#else
+#define RCC_USART16910CLKSOURCE_CDPCLK2   (0x00000000U)
+/* alias */
+#define RCC_USART16910CLKSOURCE_D2PCLK2   RCC_USART16910CLKSOURCE_CDPCLK2
+#define RCC_USART16910CLKSOURCE_PLL2      RCC_CDCCIP2R_USART16910SEL_0
+#define RCC_USART16910CLKSOURCE_PLL3      RCC_CDCCIP2R_USART16910SEL_1
+#define RCC_USART16910CLKSOURCE_HSI      (RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_1)
+#define RCC_USART16910CLKSOURCE_CSI       RCC_CDCCIP2R_USART16910SEL_2
+#define RCC_USART16910CLKSOURCE_LSE      (RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_2)
+
+/*  Aliases */
+#define RCC_USART16CLKSOURCE_CDPCLK2     RCC_USART16910CLKSOURCE_CDPCLK2
+#define RCC_USART16CLKSOURCE_PCLK2       RCC_USART16CLKSOURCE_CDPCLK2
+#define RCC_USART16CLKSOURCE_D2PCLK2     RCC_USART16CLKSOURCE_CDPCLK2
+#define RCC_USART16CLKSOURCE_PLL2        RCC_USART16910CLKSOURCE_PLL2
+#define RCC_USART16CLKSOURCE_PLL3        RCC_USART16910CLKSOURCE_PLL3
+#define RCC_USART16CLKSOURCE_HSI         RCC_USART16910CLKSOURCE_HSI
+#define RCC_USART16CLKSOURCE_CSI         RCC_USART16910CLKSOURCE_CSI
+#define RCC_USART16CLKSOURCE_LSE         RCC_USART16910CLKSOURCE_LSE
+#endif /* RCC_D2CCIP2R_USART16SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_USART1_Clock_Source  RCCEx USART1 Clock Source
+  * @{
+  */
+#define RCC_USART1CLKSOURCE_D2PCLK2   RCC_USART16CLKSOURCE_D2PCLK2
+#define RCC_USART1CLKSOURCE_PLL2      RCC_USART16CLKSOURCE_PLL2
+#define RCC_USART1CLKSOURCE_PLL3      RCC_USART16CLKSOURCE_PLL3
+#define RCC_USART1CLKSOURCE_HSI       RCC_USART16CLKSOURCE_HSI
+#define RCC_USART1CLKSOURCE_CSI       RCC_USART16CLKSOURCE_CSI
+#define RCC_USART1CLKSOURCE_LSE       RCC_USART16CLKSOURCE_LSE
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_USART6_Clock_Source  RCCEx USART6 Clock Source
+  * @{
+  */
+#define RCC_USART6CLKSOURCE_D2PCLK2   RCC_USART16CLKSOURCE_D2PCLK2
+#define RCC_USART6CLKSOURCE_PLL2      RCC_USART16CLKSOURCE_PLL2
+#define RCC_USART6CLKSOURCE_PLL3      RCC_USART16CLKSOURCE_PLL3
+#define RCC_USART6CLKSOURCE_HSI       RCC_USART16CLKSOURCE_HSI
+#define RCC_USART6CLKSOURCE_CSI       RCC_USART16CLKSOURCE_CSI
+#define RCC_USART6CLKSOURCE_LSE       RCC_USART16CLKSOURCE_LSE
+
+/**
+  * @}
+  */
+
+#if defined(UART9)
+/** @defgroup RCCEx_UART9_Clock_Source  RCCEx UART9 Clock Source
+  * @{
+  */
+#define RCC_UART9CLKSOURCE_D2PCLK2   RCC_USART16CLKSOURCE_D2PCLK2
+#define RCC_UART9CLKSOURCE_PLL2      RCC_USART16CLKSOURCE_PLL2
+#define RCC_UART9CLKSOURCE_PLL3      RCC_USART16CLKSOURCE_PLL3
+#define RCC_UART9CLKSOURCE_HSI       RCC_USART16CLKSOURCE_HSI
+#define RCC_UART9CLKSOURCE_CSI       RCC_USART16CLKSOURCE_CSI
+#define RCC_UART9CLKSOURCE_LSE       RCC_USART16CLKSOURCE_LSE
+/**
+  * @}
+  */
+#endif /* UART9 */
+
+#if defined(USART10)
+/** @defgroup RCCEx_USART10_Clock_Source  RCCEx USART10 Clock Source
+  * @{
+  */
+#define RCC_USART10CLKSOURCE_D2PCLK2   RCC_USART16CLKSOURCE_D2PCLK2
+#define RCC_USART10CLKSOURCE_PLL2      RCC_USART16CLKSOURCE_PLL2
+#define RCC_USART10CLKSOURCE_PLL3      RCC_USART16CLKSOURCE_PLL3
+#define RCC_USART10CLKSOURCE_HSI       RCC_USART16CLKSOURCE_HSI
+#define RCC_USART10CLKSOURCE_CSI       RCC_USART16CLKSOURCE_CSI
+#define RCC_USART10CLKSOURCE_LSE       RCC_USART16CLKSOURCE_LSE
+/**
+  * @}
+  */
+#endif /* USART10 */
+
+/** @defgroup RCCEx_USART234578_Clock_Source  RCCEx USART2/3/4/5/7/8 Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP2R_USART28SEL)
+#define RCC_USART234578CLKSOURCE_D2PCLK1    (0x00000000U)
+/* alias */
+#define RCC_USART234578CLKSOURCE_PCLK1      RCC_USART234578CLKSOURCE_D2PCLK1
+#define RCC_USART234578CLKSOURCE_PLL2       RCC_D2CCIP2R_USART28SEL_0
+#define RCC_USART234578CLKSOURCE_PLL3       RCC_D2CCIP2R_USART28SEL_1
+#define RCC_USART234578CLKSOURCE_HSI        (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)
+#define RCC_USART234578CLKSOURCE_CSI        RCC_D2CCIP2R_USART28SEL_2
+#define RCC_USART234578CLKSOURCE_LSE        (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)
+#else
+#define RCC_USART234578CLKSOURCE_CDPCLK1   (0x00000000U)
+/* alias */
+#define RCC_USART234578CLKSOURCE_PCLK1     RCC_USART234578CLKSOURCE_CDPCLK1
+#define RCC_USART234578CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_CDPCLK1
+#define RCC_USART234578CLKSOURCE_PLL2      RCC_CDCCIP2R_USART234578SEL_0
+#define RCC_USART234578CLKSOURCE_PLL3      RCC_CDCCIP2R_USART234578SEL_1
+#define RCC_USART234578CLKSOURCE_HSI      (RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_1)
+#define RCC_USART234578CLKSOURCE_CSI       RCC_CDCCIP2R_USART234578SEL_2
+#define RCC_USART234578CLKSOURCE_LSE      (RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_2)
+#endif /* RCC_D2CCIP2R_USART28SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_USART2_Clock_Source  RCCEx USART2 Clock Source
+  * @{
+  */
+#define RCC_USART2CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1
+#define RCC_USART2CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2
+#define RCC_USART2CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3
+#define RCC_USART2CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI
+#define RCC_USART2CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI
+#define RCC_USART2CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_USART3_Clock_Source  RCCEx USART3 Clock Source
+  * @{
+  */
+#define RCC_USART3CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1
+#define RCC_USART3CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2
+#define RCC_USART3CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3
+#define RCC_USART3CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI
+#define RCC_USART3CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI
+#define RCC_USART3CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_UART4_Clock_Source  RCCEx UART4 Clock Source
+  * @{
+  */
+#define RCC_UART4CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1
+#define RCC_UART4CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2
+#define RCC_UART4CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3
+#define RCC_UART4CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI
+#define RCC_UART4CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI
+#define RCC_UART4CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_UART5_Clock_Source  RCCEx UART5 Clock Source
+  * @{
+  */
+#define RCC_UART5CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1
+#define RCC_UART5CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2
+#define RCC_UART5CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3
+#define RCC_UART5CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI
+#define RCC_UART5CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI
+#define RCC_UART5CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_UART7_Clock_Source  RCCEx UART7 Clock Source
+  * @{
+  */
+#define RCC_UART7CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1
+#define RCC_UART7CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2
+#define RCC_UART7CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3
+#define RCC_UART7CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI
+#define RCC_UART7CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI
+#define RCC_UART7CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_UART8_Clock_Source  RCCEx UART8 Clock Source
+  * @{
+  */
+#define RCC_UART8CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1
+#define RCC_UART8CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2
+#define RCC_UART8CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3
+#define RCC_UART8CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI
+#define RCC_UART8CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI
+#define RCC_UART8CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_LPUART1_Clock_Source  RCCEx LPUART1 Clock Source
+  * @{
+  */
+#if defined(RCC_D3CCIPR_LPUART1SEL)
+#define RCC_LPUART1CLKSOURCE_D3PCLK1    (0x00000000U)
+/* alias */
+#define RCC_LPUART1CLKSOURCE_PCLK4     RCC_LPUART1CLKSOURCE_D3PCLK1
+#define RCC_LPUART1CLKSOURCE_PLL2      RCC_D3CCIPR_LPUART1SEL_0
+#define RCC_LPUART1CLKSOURCE_PLL3      RCC_D3CCIPR_LPUART1SEL_1
+#define RCC_LPUART1CLKSOURCE_HSI       (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_1)
+#define RCC_LPUART1CLKSOURCE_CSI        RCC_D3CCIPR_LPUART1SEL_2
+#define RCC_LPUART1CLKSOURCE_LSE       (RCC_D3CCIPR_LPUART1SEL_2 | RCC_D3CCIPR_LPUART1SEL_0)
+#else
+#define RCC_LPUART1CLKSOURCE_SRDPCLK4   (0x00000000U)
+/* alias*/
+#define RCC_LPUART1CLKSOURCE_PCLK4     RCC_LPUART1CLKSOURCE_SRDPCLK4
+#define RCC_LPUART1CLKSOURCE_D3PCLK1   RCC_LPUART1CLKSOURCE_SRDPCLK4
+#define RCC_LPUART1CLKSOURCE_PLL2      RCC_SRDCCIPR_LPUART1SEL_0
+#define RCC_LPUART1CLKSOURCE_PLL3      RCC_SRDCCIPR_LPUART1SEL_1
+#define RCC_LPUART1CLKSOURCE_HSI       (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_1)
+#define RCC_LPUART1CLKSOURCE_CSI        RCC_SRDCCIPR_LPUART1SEL_2
+#define RCC_LPUART1CLKSOURCE_LSE       (RCC_SRDCCIPR_LPUART1SEL_2 | RCC_SRDCCIPR_LPUART1SEL_0)
+#endif /* RCC_D3CCIPR_LPUART1SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_I2C123_Clock_Source  RCCEx I2C1/2/3 Clock Source
+  * @{
+  */
+#if defined (RCC_D2CCIP2R_I2C123SEL)
+#define RCC_I2C123CLKSOURCE_D2PCLK1      (0x00000000U)
+#define RCC_I2C123CLKSOURCE_PLL3         RCC_D2CCIP2R_I2C123SEL_0
+#define RCC_I2C123CLKSOURCE_HSI          RCC_D2CCIP2R_I2C123SEL_1
+#define RCC_I2C123CLKSOURCE_CSI         (RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1)
+#else
+#define RCC_I2C123CLKSOURCE_CDPCLK1      (0x00000000U)
+/* alias */
+#define RCC_I2C123CLKSOURCE_D2PCLK1      RCC_I2C123CLKSOURCE_CDPCLK1
+#define RCC_I2C123CLKSOURCE_PLL3         RCC_CDCCIP2R_I2C123SEL_0
+#define RCC_I2C123CLKSOURCE_HSI          RCC_CDCCIP2R_I2C123SEL_1
+#define RCC_I2C123CLKSOURCE_CSI         (RCC_CDCCIP2R_I2C123SEL_0 | RCC_CDCCIP2R_I2C123SEL_1)
+#endif /* RCC_D2CCIP2R_I2C123SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_I2C1_Clock_Source  RCCEx I2C1 Clock Source
+  * @{
+  */
+#define RCC_I2C1CLKSOURCE_D2PCLK1     RCC_I2C123CLKSOURCE_D2PCLK1
+#define RCC_I2C1CLKSOURCE_PLL3        RCC_I2C123CLKSOURCE_PLL3
+#define RCC_I2C1CLKSOURCE_HSI         RCC_I2C123CLKSOURCE_HSI
+#define RCC_I2C1CLKSOURCE_CSI         RCC_I2C123CLKSOURCE_CSI
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_I2C2_Clock_Source  RCCEx I2C2 Clock Source
+  * @{
+  */
+#define RCC_I2C2CLKSOURCE_D2PCLK1     RCC_I2C123CLKSOURCE_D2PCLK1
+#define RCC_I2C2CLKSOURCE_PLL3        RCC_I2C123CLKSOURCE_PLL3
+#define RCC_I2C2CLKSOURCE_HSI         RCC_I2C123CLKSOURCE_HSI
+#define RCC_I2C2CLKSOURCE_CSI         RCC_I2C123CLKSOURCE_CSI
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_I2C3_Clock_Source  RCCEx I2C3 Clock Source
+  * @{
+  */
+#define RCC_I2C3CLKSOURCE_D2PCLK1     RCC_I2C123CLKSOURCE_D2PCLK1
+#define RCC_I2C3CLKSOURCE_PLL3        RCC_I2C123CLKSOURCE_PLL3
+#define RCC_I2C3CLKSOURCE_HSI         RCC_I2C123CLKSOURCE_HSI
+#define RCC_I2C3CLKSOURCE_CSI         RCC_I2C123CLKSOURCE_CSI
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_I2C4_Clock_Source  RCCEx I2C4 Clock Source
+  * @{
+  */
+#if defined(RCC_D3CCIPR_I2C4SEL)
+#define RCC_I2C4CLKSOURCE_D3PCLK1      (0x00000000U)
+#define RCC_I2C4CLKSOURCE_PLL3         RCC_D3CCIPR_I2C4SEL_0
+#define RCC_I2C4CLKSOURCE_HSI          RCC_D3CCIPR_I2C4SEL_1
+#define RCC_I2C4CLKSOURCE_CSI         (RCC_D3CCIPR_I2C4SEL_0 | RCC_D3CCIPR_I2C4SEL_1)
+#else
+#define RCC_I2C4CLKSOURCE_SRDPCLK4     (0x00000000U)
+/* alias */
+#define RCC_I2C4CLKSOURCE_D3PCLK1     RCC_I2C4CLKSOURCE_SRDPCLK4
+#define RCC_I2C4CLKSOURCE_PLL3         RCC_SRDCCIPR_I2C4SEL_0
+#define RCC_I2C4CLKSOURCE_HSI          RCC_SRDCCIPR_I2C4SEL_1
+#define RCC_I2C4CLKSOURCE_CSI         (RCC_SRDCCIPR_I2C4SEL_0 | RCC_SRDCCIPR_I2C4SEL_1)
+#endif /* RCC_D3CCIPR_I2C4SEL */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_RNG_Clock_Source  RCCEx RNG Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP2R_RNGSEL)
+#define RCC_RNGCLKSOURCE_HSI48        (0x00000000U)
+#define RCC_RNGCLKSOURCE_PLL           RCC_D2CCIP2R_RNGSEL_0
+#define RCC_RNGCLKSOURCE_LSE           RCC_D2CCIP2R_RNGSEL_1
+#define RCC_RNGCLKSOURCE_LSI           RCC_D2CCIP2R_RNGSEL
+#else
+#define RCC_RNGCLKSOURCE_HSI48        (0x00000000U)
+#define RCC_RNGCLKSOURCE_PLL           RCC_CDCCIP2R_RNGSEL_0
+#define RCC_RNGCLKSOURCE_LSE           RCC_CDCCIP2R_RNGSEL_1
+#define RCC_RNGCLKSOURCE_LSI           RCC_CDCCIP2R_RNGSEL
+#endif /* RCC_D2CCIP2R_RNGSEL */
+
+/**
+  * @}
+  */
+#if defined(HRTIM1)
+
+/** @defgroup RCCEx_HRTIM1_Clock_Source RCC Extended HRTIM1 Clock Source
+  * @{
+  */
+#define RCC_HRTIM1CLK_TIMCLK                (0x00000000U)
+#define RCC_HRTIM1CLK_CPUCLK                RCC_CFGR_HRTIMSEL
+
+/**
+  * @}
+  */
+#endif /*HRTIM1*/
+
+/** @defgroup RCCEx_USB_Clock_Source  RCCEx USB Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP2R_USBSEL)
+#define RCC_USBCLKSOURCE_PLL                  RCC_D2CCIP2R_USBSEL_0
+#define RCC_USBCLKSOURCE_PLL3                 RCC_D2CCIP2R_USBSEL_1
+#define RCC_USBCLKSOURCE_HSI48                RCC_D2CCIP2R_USBSEL
+#else
+#define RCC_USBCLKSOURCE_PLL                  RCC_CDCCIP2R_USBSEL_0
+#define RCC_USBCLKSOURCE_PLL3                 RCC_CDCCIP2R_USBSEL_1
+#define RCC_USBCLKSOURCE_HSI48                RCC_CDCCIP2R_USBSEL
+#endif /* RCC_D2CCIP2R_USBSEL */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_SAI1SEL)
+#define RCC_SAI1CLKSOURCE_PLL         (0x00000000U)
+#define RCC_SAI1CLKSOURCE_PLL2         RCC_D2CCIP1R_SAI1SEL_0
+#define RCC_SAI1CLKSOURCE_PLL3         RCC_D2CCIP1R_SAI1SEL_1
+#define RCC_SAI1CLKSOURCE_PIN         (RCC_D2CCIP1R_SAI1SEL_0 | RCC_D2CCIP1R_SAI1SEL_1)
+#define RCC_SAI1CLKSOURCE_CLKP         RCC_D2CCIP1R_SAI1SEL_2
+#else
+#define RCC_SAI1CLKSOURCE_PLL         (0x00000000U)
+#define RCC_SAI1CLKSOURCE_PLL2         RCC_CDCCIP1R_SAI1SEL_0
+#define RCC_SAI1CLKSOURCE_PLL3         RCC_CDCCIP1R_SAI1SEL_1
+#define RCC_SAI1CLKSOURCE_PIN         (RCC_CDCCIP1R_SAI1SEL_0 | RCC_CDCCIP1R_SAI1SEL_1)
+#define RCC_SAI1CLKSOURCE_CLKP         RCC_CDCCIP1R_SAI1SEL_2
+#endif /* RCC_D2CCIP1R_SAI1SEL */
+/**
+  * @}
+  */
+
+#if defined(SAI3)
+/** @defgroup RCCEx_SAI23_Clock_Source SAI2/3 Clock Source
+  * @{
+  */
+#define RCC_SAI23CLKSOURCE_PLL         (0x00000000U)
+#define RCC_SAI23CLKSOURCE_PLL2         RCC_D2CCIP1R_SAI23SEL_0
+#define RCC_SAI23CLKSOURCE_PLL3         RCC_D2CCIP1R_SAI23SEL_1
+#define RCC_SAI23CLKSOURCE_PIN         (RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1)
+#define RCC_SAI23CLKSOURCE_CLKP         RCC_D2CCIP1R_SAI23SEL_2
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source
+  * @{
+  */
+#define RCC_SAI2CLKSOURCE_PLL         RCC_SAI23CLKSOURCE_PLL
+#define RCC_SAI2CLKSOURCE_PLL2        RCC_SAI23CLKSOURCE_PLL2
+#define RCC_SAI2CLKSOURCE_PLL3        RCC_SAI23CLKSOURCE_PLL3
+#define RCC_SAI2CLKSOURCE_PIN         RCC_SAI23CLKSOURCE_PIN
+#define RCC_SAI2CLKSOURCE_CLKP        RCC_SAI23CLKSOURCE_CLKP
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SAI3_Clock_Source SAI3 Clock Source
+  * @{
+  */
+#define RCC_SAI3CLKSOURCE_PLL         RCC_SAI23CLKSOURCE_PLL
+#define RCC_SAI3CLKSOURCE_PLL2        RCC_SAI23CLKSOURCE_PLL2
+#define RCC_SAI3CLKSOURCE_PLL3        RCC_SAI23CLKSOURCE_PLL3
+#define RCC_SAI3CLKSOURCE_PIN         RCC_SAI23CLKSOURCE_PIN
+#define RCC_SAI3CLKSOURCE_CLKP        RCC_SAI23CLKSOURCE_CLKP
+/**
+  * @}
+  */
+#endif /* SAI3 */
+
+#if defined(RCC_CDCCIP1R_SAI2ASEL)
+/** @defgroup RCCEx_SAI2_Clock_A Source SAI2A Clock Source
+  * @{
+  */
+#define RCC_SAI2ACLKSOURCE_PLL         (0x00000000U)
+#define RCC_SAI2ACLKSOURCE_PLL2         RCC_CDCCIP1R_SAI2ASEL_0
+#define RCC_SAI2ACLKSOURCE_PLL3         RCC_CDCCIP1R_SAI2ASEL_1
+#define RCC_SAI2ACLKSOURCE_PIN         (RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_1)
+#define RCC_SAI2ACLKSOURCE_CLKP         RCC_CDCCIP1R_SAI2ASEL_2
+#define RCC_SAI2ACLKSOURCE_SPDIF       (RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_2)
+ /**
+  * @}
+  */
+#endif /* RCC_CDCCIP1R_SAI2ASEL */
+
+#if defined(RCC_CDCCIP1R_SAI2BSEL)
+/** @defgroup RCCEx_SAI2_Block_B Clock_Source SAI2B Clock Source
+  * @{
+  */
+#define RCC_SAI2BCLKSOURCE_PLL         (0x00000000U)
+#define RCC_SAI2BCLKSOURCE_PLL2         RCC_CDCCIP1R_SAI2BSEL_0
+#define RCC_SAI2BCLKSOURCE_PLL3         RCC_CDCCIP1R_SAI2BSEL_1
+#define RCC_SAI2BCLKSOURCE_PIN         (RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_1)
+#define RCC_SAI2BCLKSOURCE_CLKP         RCC_CDCCIP1R_SAI2BSEL_2
+#define RCC_SAI2BCLKSOURCE_SPDIF       (RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_2)
+/**
+  * @}
+  */
+#endif /* RCC_CDCCIP1R_SAI2BSEL */
+
+
+/** @defgroup RCCEx_SPI123_Clock_Source SPI1/2/3 Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_SPI123SEL)
+#define RCC_SPI123CLKSOURCE_PLL         (0x00000000U)
+#define RCC_SPI123CLKSOURCE_PLL2         RCC_D2CCIP1R_SPI123SEL_0
+#define RCC_SPI123CLKSOURCE_PLL3         RCC_D2CCIP1R_SPI123SEL_1
+#define RCC_SPI123CLKSOURCE_PIN         (RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1)
+#define RCC_SPI123CLKSOURCE_CLKP         RCC_D2CCIP1R_SPI123SEL_2
+#else
+#define RCC_SPI123CLKSOURCE_PLL         (0x00000000U)
+#define RCC_SPI123CLKSOURCE_PLL2         RCC_CDCCIP1R_SPI123SEL_0
+#define RCC_SPI123CLKSOURCE_PLL3         RCC_CDCCIP1R_SPI123SEL_1
+#define RCC_SPI123CLKSOURCE_PIN         (RCC_CDCCIP1R_SPI123SEL_0 | RCC_CDCCIP1R_SPI123SEL_1)
+#define RCC_SPI123CLKSOURCE_CLKP         RCC_CDCCIP1R_SPI123SEL_2
+#endif /* RCC_D2CCIP1R_SPI123SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SPI1_Clock_Source SPI1 Clock Source
+  * @{
+  */
+#define RCC_SPI1CLKSOURCE_PLL         RCC_SPI123CLKSOURCE_PLL
+#define RCC_SPI1CLKSOURCE_PLL2        RCC_SPI123CLKSOURCE_PLL2
+#define RCC_SPI1CLKSOURCE_PLL3        RCC_SPI123CLKSOURCE_PLL3
+#define RCC_SPI1CLKSOURCE_PIN         RCC_SPI123CLKSOURCE_PIN
+#define RCC_SPI1CLKSOURCE_CLKP        RCC_SPI123CLKSOURCE_CLKP
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SPI2_Clock_Source SPI2 Clock Source
+  * @{
+  */
+#define RCC_SPI2CLKSOURCE_PLL         RCC_SPI123CLKSOURCE_PLL
+#define RCC_SPI2CLKSOURCE_PLL2        RCC_SPI123CLKSOURCE_PLL2
+#define RCC_SPI2CLKSOURCE_PLL3        RCC_SPI123CLKSOURCE_PLL3
+#define RCC_SPI2CLKSOURCE_PIN         RCC_SPI123CLKSOURCE_PIN
+#define RCC_SPI2CLKSOURCE_CLKP        RCC_SPI123CLKSOURCE_CLKP
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SPI3_Clock_Source SPI3 Clock Source
+  * @{
+  */
+#define RCC_SPI3CLKSOURCE_PLL         RCC_SPI123CLKSOURCE_PLL
+#define RCC_SPI3CLKSOURCE_PLL2        RCC_SPI123CLKSOURCE_PLL2
+#define RCC_SPI3CLKSOURCE_PLL3        RCC_SPI123CLKSOURCE_PLL3
+#define RCC_SPI3CLKSOURCE_PIN         RCC_SPI123CLKSOURCE_PIN
+#define RCC_SPI3CLKSOURCE_CLKP        RCC_SPI123CLKSOURCE_CLKP
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SPI45_Clock_Source SPI4/5 Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_SPI45SEL)
+#define RCC_SPI45CLKSOURCE_D2PCLK1     (0x00000000U)
+#define RCC_SPI45CLKSOURCE_PCLK1        RCC_SPI45CLKSOURCE_D2PCLK1
+#define RCC_SPI45CLKSOURCE_PLL2         RCC_D2CCIP1R_SPI45SEL_0
+#define RCC_SPI45CLKSOURCE_PLL3         RCC_D2CCIP1R_SPI45SEL_1
+#define RCC_SPI45CLKSOURCE_HSI         (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_1)
+#define RCC_SPI45CLKSOURCE_CSI          RCC_D2CCIP1R_SPI45SEL_2
+#define RCC_SPI45CLKSOURCE_HSE         (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_2)
+#else
+#define RCC_SPI45CLKSOURCE_CDPCLK1     (0x00000000U)
+/* aliases */
+#define RCC_SPI45CLKSOURCE_D2PCLK1      RCC_SPI45CLKSOURCE_CDPCLK1  /* D2PCLK1 is used in STM32H74xxx, STM32H75xxx, STM32H72xxx and STM32H73xxx family lines */
+#define RCC_SPI45CLKSOURCE_PCLK1        RCC_SPI45CLKSOURCE_CDPCLK1
+#define RCC_SPI45CLKSOURCE_PLL2         RCC_CDCCIP1R_SPI45SEL_0
+#define RCC_SPI45CLKSOURCE_PLL3         RCC_CDCCIP1R_SPI45SEL_1
+#define RCC_SPI45CLKSOURCE_HSI         (RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_1)
+#define RCC_SPI45CLKSOURCE_CSI          RCC_CDCCIP1R_SPI45SEL_2
+#define RCC_SPI45CLKSOURCE_HSE         (RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_2)
+#endif /* RCC_D2CCIP1R_SPI45SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SPI4_Clock_Source SPI4 Clock Source
+  * @{
+  */
+#define RCC_SPI4CLKSOURCE_D2PCLK1     RCC_SPI45CLKSOURCE_D2PCLK1
+#define RCC_SPI4CLKSOURCE_PLL2        RCC_SPI45CLKSOURCE_PLL2
+#define RCC_SPI4CLKSOURCE_PLL3        RCC_SPI45CLKSOURCE_PLL3
+#define RCC_SPI4CLKSOURCE_HSI         RCC_SPI45CLKSOURCE_HSI
+#define RCC_SPI4CLKSOURCE_CSI         RCC_SPI45CLKSOURCE_CSI
+#define RCC_SPI4CLKSOURCE_HSE         RCC_SPI45CLKSOURCE_HSE
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SPI5_Clock_Source SPI5 Clock Source
+  * @{
+  */
+#define RCC_SPI5CLKSOURCE_D2PCLK1     RCC_SPI45CLKSOURCE_D2PCLK1
+#define RCC_SPI5CLKSOURCE_PLL2        RCC_SPI45CLKSOURCE_PLL2
+#define RCC_SPI5CLKSOURCE_PLL3        RCC_SPI45CLKSOURCE_PLL3
+#define RCC_SPI5CLKSOURCE_HSI         RCC_SPI45CLKSOURCE_HSI
+#define RCC_SPI5CLKSOURCE_CSI         RCC_SPI45CLKSOURCE_CSI
+#define RCC_SPI5CLKSOURCE_HSE         RCC_SPI45CLKSOURCE_HSE
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SPI6_Clock_Source SPI6 Clock Source
+  * @{
+  */
+#if defined(RCC_D3CCIPR_SPI6SEL)
+#define RCC_SPI6CLKSOURCE_D3PCLK1     (0x00000000U)
+#define RCC_SPI6CLKSOURCE_PCLK4        RCC_SPI6CLKSOURCE_D3PCLK1
+#define RCC_SPI6CLKSOURCE_PLL2         RCC_D3CCIPR_SPI6SEL_0
+#define RCC_SPI6CLKSOURCE_PLL3         RCC_D3CCIPR_SPI6SEL_1
+#define RCC_SPI6CLKSOURCE_HSI         (RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_1)
+#define RCC_SPI6CLKSOURCE_CSI          RCC_D3CCIPR_SPI6SEL_2
+#define RCC_SPI6CLKSOURCE_HSE         (RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_2)
+#else
+#define RCC_SPI6CLKSOURCE_SRDPCLK4    (0x00000000U)
+/* alias */
+#define RCC_SPI6CLKSOURCE_D3PCLK1      RCC_SPI6CLKSOURCE_SRDPCLK4  /* D3PCLK1 is used in STM32H74xxx, STM32H75xxx, STM32H72xxx and STM32H73xxx family lines */
+#define RCC_SPI6CLKSOURCE_PCLK4        RCC_SPI6CLKSOURCE_SRDPCLK4
+#define RCC_SPI6CLKSOURCE_PLL2         RCC_SRDCCIPR_SPI6SEL_0
+#define RCC_SPI6CLKSOURCE_PLL3         RCC_SRDCCIPR_SPI6SEL_1
+#define RCC_SPI6CLKSOURCE_HSI         (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_1)
+#define RCC_SPI6CLKSOURCE_CSI          RCC_SRDCCIPR_SPI6SEL_2
+#define RCC_SPI6CLKSOURCE_HSE         (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_2)
+#define RCC_SPI6CLKSOURCE_PIN         (RCC_SRDCCIPR_SPI6SEL_1 | RCC_SRDCCIPR_SPI6SEL_2)
+#endif /* RCC_D3CCIPR_SPI6SEL */
+
+/**
+  * @}
+  */
+
+
+#if defined(SAI4_Block_A)
+/** @defgroup RCCEx_SAI4A_Clock_Source SAI4A Clock Source
+  * @{
+  */
+#define RCC_SAI4ACLKSOURCE_PLL         (0x00000000U)
+#define RCC_SAI4ACLKSOURCE_PLL2         RCC_D3CCIPR_SAI4ASEL_0
+#define RCC_SAI4ACLKSOURCE_PLL3         RCC_D3CCIPR_SAI4ASEL_1
+#define RCC_SAI4ACLKSOURCE_PIN         (RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1)
+#define RCC_SAI4ACLKSOURCE_CLKP         RCC_D3CCIPR_SAI4ASEL_2
+
+/**
+  * @}
+  */
+#endif /* SAI4_Block_A */
+
+
+
+#if defined(SAI4_Block_B)
+/** @defgroup RCCEx_SAI4B_Clock_Source SAI4B Clock Source
+  * @{
+  */
+#define RCC_SAI4BCLKSOURCE_PLL         (0x00000000U)
+#define RCC_SAI4BCLKSOURCE_PLL2         RCC_D3CCIPR_SAI4BSEL_0
+#define RCC_SAI4BCLKSOURCE_PLL3         RCC_D3CCIPR_SAI4BSEL_1
+#define RCC_SAI4BCLKSOURCE_PIN         (RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1)
+#define RCC_SAI4BCLKSOURCE_CLKP         RCC_D3CCIPR_SAI4BSEL_2
+
+/**
+  * @}
+  */
+#endif /* SAI4_Block_B */
+
+
+/** @defgroup RCCEx_LPTIM1_Clock_Source  RCCEx LPTIM1 Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP2R_LPTIM1SEL)
+#define RCC_LPTIM1CLKSOURCE_D2PCLK1        (0x00000000U)
+/* alias */
+#define RCC_LPTIM1CLKSOURCE_PCLK1         RCC_LPTIM1CLKSOURCE_D2PCLK1
+#define RCC_LPTIM1CLKSOURCE_PLL2          RCC_D2CCIP2R_LPTIM1SEL_0
+#define RCC_LPTIM1CLKSOURCE_PLL3          RCC_D2CCIP2R_LPTIM1SEL_1
+#define RCC_LPTIM1CLKSOURCE_LSE          (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_1)
+#define RCC_LPTIM1CLKSOURCE_LSI           RCC_D2CCIP2R_LPTIM1SEL_2
+#define RCC_LPTIM1CLKSOURCE_CLKP         (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_2)
+#else
+#define RCC_LPTIM1CLKSOURCE_CDPCLK1        (0x00000000U)
+/* alias */
+#define RCC_LPTIM1CLKSOURCE_PCLK1         RCC_LPTIM1CLKSOURCE_CDPCLK1
+#define RCC_LPTIM1CLKSOURCE_D2PCLK1       RCC_LPTIM1CLKSOURCE_CDPCLK1
+#define RCC_LPTIM1CLKSOURCE_PLL2          RCC_CDCCIP2R_LPTIM1SEL_0
+#define RCC_LPTIM1CLKSOURCE_PLL3          RCC_CDCCIP2R_LPTIM1SEL_1
+#define RCC_LPTIM1CLKSOURCE_LSE          (RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_1)
+#define RCC_LPTIM1CLKSOURCE_LSI           RCC_CDCCIP2R_LPTIM1SEL_2
+#define RCC_LPTIM1CLKSOURCE_CLKP         (RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_2)
+#endif /* RCC_D2CCIP2R_LPTIM1SEL */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_LPTIM2_Clock_Source  RCCEx LPTIM2 Clock Source
+  * @{
+  */
+#if defined(RCC_D3CCIPR_LPTIM2SEL)
+#define RCC_LPTIM2CLKSOURCE_D3PCLK1       (0x00000000U)
+/* alias */
+#define RCC_LPTIM2CLKSOURCE_PCLK4         RCC_LPTIM2CLKSOURCE_D3PCLK1
+#define RCC_LPTIM2CLKSOURCE_PLL2          RCC_D3CCIPR_LPTIM2SEL_0
+#define RCC_LPTIM2CLKSOURCE_PLL3          RCC_D3CCIPR_LPTIM2SEL_1
+#define RCC_LPTIM2CLKSOURCE_LSE          (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_1)
+#define RCC_LPTIM2CLKSOURCE_LSI           RCC_D3CCIPR_LPTIM2SEL_2
+#define RCC_LPTIM2CLKSOURCE_CLKP         (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_2)
+#else
+#define RCC_LPTIM2CLKSOURCE_SRDPCLK4       (0x00000000U)
+/*alias*/
+#define RCC_LPTIM2CLKSOURCE_PCLK4         RCC_LPTIM2CLKSOURCE_SRDPCLK4
+#define RCC_LPTIM2CLKSOURCE_D3PCLK1       RCC_LPTIM2CLKSOURCE_SRDPCLK4
+#define RCC_LPTIM2CLKSOURCE_PLL2          RCC_SRDCCIPR_LPTIM2SEL_0
+#define RCC_LPTIM2CLKSOURCE_PLL3          RCC_SRDCCIPR_LPTIM2SEL_1
+#define RCC_LPTIM2CLKSOURCE_LSE          (RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_1)
+#define RCC_LPTIM2CLKSOURCE_LSI           RCC_SRDCCIPR_LPTIM2SEL_2
+#define RCC_LPTIM2CLKSOURCE_CLKP         (RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_2)
+#endif /* RCC_D3CCIPR_LPTIM2SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_LPTIM345_Clock_Source  RCCEx LPTIM3/4/5 Clock Source
+  * @{
+  */
+#if defined(RCC_D3CCIPR_LPTIM345SEL)
+#define RCC_LPTIM345CLKSOURCE_D3PCLK1        (0x00000000U)
+/* alias*/
+#define RCC_LPTIM345CLKSOURCE_PCLK4         RCC_LPTIM345CLKSOURCE_D3PCLK1
+#define RCC_LPTIM345CLKSOURCE_PLL2          RCC_D3CCIPR_LPTIM345SEL_0
+#define RCC_LPTIM345CLKSOURCE_PLL3          RCC_D3CCIPR_LPTIM345SEL_1
+#define RCC_LPTIM345CLKSOURCE_LSE          (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1)
+#define RCC_LPTIM345CLKSOURCE_LSI           RCC_D3CCIPR_LPTIM345SEL_2
+#define RCC_LPTIM345CLKSOURCE_CLKP         (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2)
+#else
+#define RCC_LPTIM345CLKSOURCE_SRDPCLK4      (0x00000000U)
+/* alias */
+#define RCC_LPTIM345CLKSOURCE_PCLK4         RCC_LPTIM345CLKSOURCE_SRDPCLK4
+#define RCC_LPTIM345CLKSOURCE_D3PCLK1       RCC_LPTIM345CLKSOURCE_SRDPCLK4
+#define RCC_LPTIM345CLKSOURCE_PLL2          RCC_SRDCCIPR_LPTIM3SEL_0
+#define RCC_LPTIM345CLKSOURCE_PLL3          RCC_SRDCCIPR_LPTIM3SEL_1
+#define RCC_LPTIM345CLKSOURCE_LSE          (RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_1)
+#define RCC_LPTIM345CLKSOURCE_LSI           RCC_SRDCCIPR_LPTIM3SEL_2
+#define RCC_LPTIM345CLKSOURCE_CLKP         (RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_2)
+#endif /* RCC_D3CCIPR_LPTIM345SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_LPTIM3_Clock_Source  RCCEx LPTIM3 Clock Source
+  * @{
+  */
+#define RCC_LPTIM3CLKSOURCE_D3PCLK1       RCC_LPTIM345CLKSOURCE_D3PCLK1
+#define RCC_LPTIM3CLKSOURCE_PLL2          RCC_LPTIM345CLKSOURCE_PLL2
+#define RCC_LPTIM3CLKSOURCE_PLL3          RCC_LPTIM345CLKSOURCE_PLL3
+#define RCC_LPTIM3CLKSOURCE_LSE           RCC_LPTIM345CLKSOURCE_LSE
+#define RCC_LPTIM3CLKSOURCE_LSI           RCC_LPTIM345CLKSOURCE_LSI
+#define RCC_LPTIM3CLKSOURCE_CLKP          RCC_LPTIM345CLKSOURCE_CLKP
+
+/**
+  * @}
+  */
+#if defined(LPTIM4)
+/** @defgroup RCCEx_LPTIM4_Clock_Source  RCCEx LPTIM4 Clock Source
+  * @{
+  */
+#define RCC_LPTIM4CLKSOURCE_D3PCLK1       RCC_LPTIM345CLKSOURCE_D3PCLK1
+#define RCC_LPTIM4CLKSOURCE_PLL2          RCC_LPTIM345CLKSOURCE_PLL2
+#define RCC_LPTIM4CLKSOURCE_PLL3          RCC_LPTIM345CLKSOURCE_PLL3
+#define RCC_LPTIM4CLKSOURCE_LSE           RCC_LPTIM345CLKSOURCE_LSE
+#define RCC_LPTIM4CLKSOURCE_LSI           RCC_LPTIM345CLKSOURCE_LSI
+#define RCC_LPTIM4CLKSOURCE_CLKP          RCC_LPTIM345CLKSOURCE_CLKP
+/**
+  * @}
+  */
+#endif /* LPTIM4 */
+
+#if defined(LPTIM5)
+/** @defgroup RCCEx_LPTIM5_Clock_Source  RCCEx LPTIM5 Clock Source
+  * @{
+  */
+#define RCC_LPTIM5CLKSOURCE_D3PCLK1       RCC_LPTIM345CLKSOURCE_D3PCLK1
+#define RCC_LPTIM5CLKSOURCE_PLL2          RCC_LPTIM345CLKSOURCE_PLL2
+#define RCC_LPTIM5CLKSOURCE_PLL3          RCC_LPTIM345CLKSOURCE_PLL3
+#define RCC_LPTIM5CLKSOURCE_LSE           RCC_LPTIM345CLKSOURCE_LSE
+#define RCC_LPTIM5CLKSOURCE_LSI           RCC_LPTIM345CLKSOURCE_LSI
+#define RCC_LPTIM5CLKSOURCE_CLKP          RCC_LPTIM345CLKSOURCE_CLKP
+
+/**
+  * @}
+  */
+#endif /* LPTIM5 */
+
+#if defined(QUADSPI)
+/** @defgroup RCCEx_QSPI_Clock_Source  RCCEx QSPI Clock Source
+  * @{
+  */
+#define RCC_QSPICLKSOURCE_D1HCLK       (0x00000000U)
+#define RCC_QSPICLKSOURCE_PLL          RCC_D1CCIPR_QSPISEL_0
+#define RCC_QSPICLKSOURCE_PLL2         RCC_D1CCIPR_QSPISEL_1
+#define RCC_QSPICLKSOURCE_CLKP         RCC_D1CCIPR_QSPISEL
+
+/**
+  * @}
+  */
+#endif /* QUADSPI */
+
+
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+/** @defgroup RCCEx_OSPI_Clock_Source  RCCEx OSPI Clock Source
+  * @{
+  */
+#define RCC_OSPICLKSOURCE_CDHCLK       (0x00000000U)
+/*aliases*/
+#define RCC_OSPICLKSOURCE_D1HCLK       RCC_OSPICLKSOURCE_CDHCLK
+#define RCC_OSPICLKSOURCE_HCLK         RCC_OSPICLKSOURCE_CDHCLK
+#define RCC_OSPICLKSOURCE_PLL          RCC_CDCCIPR_OCTOSPISEL_0
+#define RCC_OSPICLKSOURCE_PLL2         RCC_CDCCIPR_OCTOSPISEL_1
+#define RCC_OSPICLKSOURCE_CLKP         RCC_CDCCIPR_OCTOSPISEL
+
+/**
+  * @}
+  */
+#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
+
+#if defined(DSI)
+/** @defgroup RCCEx_DSI_Clock_Source  RCCEx DSI Clock Source
+  * @{
+  */
+#define RCC_DSICLKSOURCE_PHY       (0x00000000U)
+#define RCC_DSICLKSOURCE_PLL2       RCC_D1CCIPR_DSISEL
+
+/**
+  * @}
+  */
+#endif /* DSI */
+
+/** @defgroup RCCEx_FMC_Clock_Source  RCCEx FMC Clock Source
+  * @{
+  */
+#if defined(RCC_D1CCIPR_FMCSEL)
+#define RCC_FMCCLKSOURCE_D1HCLK       (0x00000000U)
+#define RCC_FMCCLKSOURCE_HCLK         RCC_FMCCLKSOURCE_D1HCLK
+#define RCC_FMCCLKSOURCE_PLL          RCC_D1CCIPR_FMCSEL_0
+#define RCC_FMCCLKSOURCE_PLL2         RCC_D1CCIPR_FMCSEL_1
+#define RCC_FMCCLKSOURCE_CLKP         RCC_D1CCIPR_FMCSEL
+#else
+#define RCC_FMCCLKSOURCE_CDHCLK       (0x00000000U)
+#define RCC_FMCCLKSOURCE_HCLK         RCC_FMCCLKSOURCE_CDHCLK
+/*alias*/
+#define RCC_FMCCLKSOURCE_D1HCLK       RCC_FMCCLKSOURCE_CDHCLK
+#define RCC_FMCCLKSOURCE_PLL          RCC_CDCCIPR_FMCSEL_0
+#define RCC_FMCCLKSOURCE_PLL2         RCC_CDCCIPR_FMCSEL_1
+#define RCC_FMCCLKSOURCE_CLKP         RCC_CDCCIPR_FMCSEL
+#endif /* RCC_D1CCIPR_FMCSEL */
+/**
+  * @}
+  */
+
+#if defined(FDCAN1) || defined(FDCAN2)
+/** @defgroup RCCEx_FDCAN_Clock_Source  RCCEx FDCAN Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_FDCANSEL)
+#define RCC_FDCANCLKSOURCE_HSE         (0x00000000U)
+#define RCC_FDCANCLKSOURCE_PLL          RCC_D2CCIP1R_FDCANSEL_0
+#define RCC_FDCANCLKSOURCE_PLL2         RCC_D2CCIP1R_FDCANSEL_1
+#else
+#define RCC_FDCANCLKSOURCE_HSE         (0x00000000U)
+#define RCC_FDCANCLKSOURCE_PLL          RCC_CDCCIP1R_FDCANSEL_0
+#define RCC_FDCANCLKSOURCE_PLL2         RCC_CDCCIP1R_FDCANSEL_1
+#endif /* D3_SRAM_BASE */
+/**
+  * @}
+  */
+#endif /*FDCAN1 || FDCAN2*/
+
+
+/** @defgroup RCCEx_SDMMC_Clock_Source  RCCEx SDMMC Clock Source
+  * @{
+  */
+#if defined(RCC_D1CCIPR_SDMMCSEL)
+#define RCC_SDMMCCLKSOURCE_PLL           (0x00000000U)
+#define RCC_SDMMCCLKSOURCE_PLL2           RCC_D1CCIPR_SDMMCSEL
+#else
+#define RCC_SDMMCCLKSOURCE_PLL           (0x00000000U)
+#define RCC_SDMMCCLKSOURCE_PLL2           RCC_CDCCIPR_SDMMCSEL
+#endif /* RCC_D1CCIPR_SDMMCSEL */
+/**
+  * @}
+  */
+
+
+/** @defgroup RCCEx_ADC_Clock_Source  RCCEx ADC Clock Source
+  * @{
+  */
+#if defined(RCC_D3CCIPR_ADCSEL_0)
+#define RCC_ADCCLKSOURCE_PLL2       (0x00000000U)
+#define RCC_ADCCLKSOURCE_PLL3       RCC_D3CCIPR_ADCSEL_0
+#define RCC_ADCCLKSOURCE_CLKP       RCC_D3CCIPR_ADCSEL_1
+#else
+#define RCC_ADCCLKSOURCE_PLL2       (0x00000000U)
+#define RCC_ADCCLKSOURCE_PLL3       RCC_SRDCCIPR_ADCSEL_0
+#define RCC_ADCCLKSOURCE_CLKP       RCC_SRDCCIPR_ADCSEL_1
+#endif /* RCC_D3CCIPR_ADCSEL_0  */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SWPMI1_Clock_Source  RCCEx SWPMI1 Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_SWPSEL)
+#define RCC_SWPMI1CLKSOURCE_D2PCLK1       (0x00000000U)
+#define RCC_SWPMI1CLKSOURCE_HSI            RCC_D2CCIP1R_SWPSEL
+#else
+#define RCC_SWPMI1CLKSOURCE_CDPCLK1       (0x00000000U)
+/* alias */
+#define RCC_SWPMI1CLKSOURCE_D2PCLK1        RCC_SWPMI1CLKSOURCE_CDPCLK1
+#define RCC_SWPMI1CLKSOURCE_HSI            RCC_CDCCIP1R_SWPSEL
+#endif /* RCC_D2CCIP1R_SWPSEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_DFSDM1_Clock_Source  RCCEx DFSDM1 Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_DFSDM1SEL)
+#define RCC_DFSDM1CLKSOURCE_D2PCLK1        (0x00000000U)
+#define RCC_DFSDM1CLKSOURCE_SYS            RCC_D2CCIP1R_DFSDM1SEL
+#else
+#define RCC_DFSDM1CLKSOURCE_CDPCLK1        (0x00000000U)
+/* alias */
+#define RCC_DFSDM1CLKSOURCE_D2PCLK1        RCC_DFSDM1CLKSOURCE_CDPCLK1
+#define RCC_DFSDM1CLKSOURCE_SYS            RCC_CDCCIP1R_DFSDM1SEL
+#endif /* RCC_D2CCIP1R_DFSDM1SEL */
+/**
+  * @}
+  */
+
+#if defined(DFSDM2_BASE)
+/** @defgroup RCCEx_DFSDM2_Clock_Source  RCCEx DFSDM2 Clock Source
+  * @{
+  */
+#define RCC_DFSDM2CLKSOURCE_SRDPCLK4       (0x00000000U)
+/* alias */
+#define RCC_DFSDM2CLKSOURCE_SRDPCLK1       RCC_DFSDM2CLKSOURCE_SRDPCLK4
+#define RCC_DFSDM2CLKSOURCE_SYS            RCC_SRDCCIPR_DFSDM2SEL
+/**
+  * @}
+  */
+#endif /* DFSDM2 */
+
+/** @defgroup RCCEx_SPDIFRX_Clock_Source  RCCEx SPDIFRX Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_SPDIFSEL_0)
+#define RCC_SPDIFRXCLKSOURCE_PLL        (0x00000000U)
+#define RCC_SPDIFRXCLKSOURCE_PLL2       RCC_D2CCIP1R_SPDIFSEL_0
+#define RCC_SPDIFRXCLKSOURCE_PLL3       RCC_D2CCIP1R_SPDIFSEL_1
+#define RCC_SPDIFRXCLKSOURCE_HSI        RCC_D2CCIP1R_SPDIFSEL
+#else
+#define RCC_SPDIFRXCLKSOURCE_PLL        (0x00000000U)
+#define RCC_SPDIFRXCLKSOURCE_PLL2       RCC_CDCCIP1R_SPDIFSEL_0
+#define RCC_SPDIFRXCLKSOURCE_PLL3       RCC_CDCCIP1R_SPDIFSEL_1
+#define RCC_SPDIFRXCLKSOURCE_HSI        RCC_CDCCIP1R_SPDIFSEL
+#endif /* RCC_D2CCIP1R_SPDIFSEL_0 */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CEC_Clock_Source  RCCEx CEC Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP2R_CECSEL_0)
+#define RCC_CECCLKSOURCE_LSE        (0x00000000U)
+#define RCC_CECCLKSOURCE_LSI         RCC_D2CCIP2R_CECSEL_0
+#define RCC_CECCLKSOURCE_CSI         RCC_D2CCIP2R_CECSEL_1
+#else
+#define RCC_CECCLKSOURCE_LSE        (0x00000000U)
+#define RCC_CECCLKSOURCE_LSI         RCC_CDCCIP2R_CECSEL_0
+#define RCC_CECCLKSOURCE_CSI         RCC_CDCCIP2R_CECSEL_1
+#endif /* RCC_D2CCIP2R_CECSEL_0 */
+/**
+  * @}
+  */
+
+
+/** @defgroup RCCEx_CLKP_Clock_Source  RCCEx CLKP Clock Source
+  * @{
+  */
+#if defined(RCC_D1CCIPR_CKPERSEL_0)
+#define RCC_CLKPSOURCE_HSI        (0x00000000U)
+#define RCC_CLKPSOURCE_CSI         RCC_D1CCIPR_CKPERSEL_0
+#define RCC_CLKPSOURCE_HSE         RCC_D1CCIPR_CKPERSEL_1
+#else
+#define RCC_CLKPSOURCE_HSI        (0x00000000U)
+#define RCC_CLKPSOURCE_CSI         RCC_CDCCIPR_CKPERSEL_0
+#define RCC_CLKPSOURCE_HSE         RCC_CDCCIPR_CKPERSEL_1
+#endif /* RCC_D1CCIPR_CKPERSEL_0 */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection
+  * @{
+  */
+#define RCC_TIMPRES_DESACTIVATED        (0x00000000U)
+#define RCC_TIMPRES_ACTIVATED            RCC_CFGR_TIMPRE
+
+/**
+  * @}
+  */
+
+#if defined(DUAL_CORE)
+
+/** @defgroup RCCEx_RCC_BootCx RCCEx RCC BootCx
+  * @{
+  */
+#define RCC_BOOT_C1        RCC_GCR_BOOT_C1
+#define RCC_BOOT_C2        RCC_GCR_BOOT_C2
+
+/**
+  * @}
+  */
+#endif /*DUAL_CORE*/
+
+#if defined(DUAL_CORE)
+/** @defgroup RCCEx_RCC_WWDGx  RCCEx RCC WWDGx
+  * @{
+  */
+#define RCC_WWDG1        RCC_GCR_WW1RSC
+#define RCC_WWDG2        RCC_GCR_WW2RSC
+
+/**
+  * @}
+  */
+
+#else
+
+/** @defgroup RCCEx_RCC_WWDGx  RCCEx RCC WWDGx
+  * @{
+  */
+#define RCC_WWDG1        RCC_GCR_WW1RSC
+
+/**
+  * @}
+  */
+
+#endif /*DUAL_CORE*/
+
+/** @defgroup RCCEx_EXTI_LINE_LSECSS  RCC LSE CSS external interrupt line
+  * @{
+  */
+#define RCC_EXTI_LINE_LSECSS           EXTI_IMR1_IM18        /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_Status RCCEx CRS Status
+  * @{
+  */
+#define RCC_CRS_NONE                   (0x00000000U)
+#define RCC_CRS_TIMEOUT                (0x00000001U)
+#define RCC_CRS_SYNCOK                 (0x00000002U)
+#define RCC_CRS_SYNCWARN               (0x00000004U)
+#define RCC_CRS_SYNCERR                (0x00000008U)
+#define RCC_CRS_SYNCMISS               (0x00000010U)
+#define RCC_CRS_TRIMOVF                (0x00000020U)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
+  * @{
+  */
+#define RCC_CRS_SYNC_SOURCE_PIN       (0x00000000U)                            /*!< Synchro Signal source external pin, Available on STM32H7 Rev.B and above devices only */
+#define RCC_CRS_SYNC_SOURCE_LSE        CRS_CFGR_SYNCSRC_0                      /*!< Synchro Signal source LSE */
+#define RCC_CRS_SYNC_SOURCE_USB1       CRS_CFGR_SYNCSRC_1                      /*!< Synchro Signal source USB1 SOF (default) */
+#define RCC_CRS_SYNC_SOURCE_USB2      (CRS_CFGR_SYNCSRC_1|CRS_CFGR_SYNCSRC_0)  /*!< Synchro Signal source USB2 SOF */
+
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider
+  * @{
+  */
+#define RCC_CRS_SYNC_DIV1        (0x00000000U)           /*!< Synchro Signal not divided (default) */
+#define RCC_CRS_SYNC_DIV2        CRS_CFGR_SYNCDIV_0                         /*!< Synchro Signal divided by 2 */
+#define RCC_CRS_SYNC_DIV4        CRS_CFGR_SYNCDIV_1                         /*!< Synchro Signal divided by 4 */
+#define RCC_CRS_SYNC_DIV8        (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0)  /*!< Synchro Signal divided by 8 */
+#define RCC_CRS_SYNC_DIV16       CRS_CFGR_SYNCDIV_2                        /*!< Synchro Signal divided by 16 */
+#define RCC_CRS_SYNC_DIV32       (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
+#define RCC_CRS_SYNC_DIV64       (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
+#define RCC_CRS_SYNC_DIV128      CRS_CFGR_SYNCDIV                         /*!< Synchro Signal divided by 128 */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity
+  * @{
+  */
+#define RCC_CRS_SYNC_POLARITY_RISING   (0x00000000U) /*!< Synchro Active on rising edge (default) */
+#define RCC_CRS_SYNC_POLARITY_FALLING  CRS_CFGR_SYNCPOL        /*!< Synchro Active on falling edge */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault
+  * @{
+  */
+#define RCC_CRS_RELOADVALUE_DEFAULT    (0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds
+                                                                    to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault
+  * @{
+  */
+#define RCC_CRS_ERRORLIMIT_DEFAULT     (0x00000022U) /*!< Default Frequency error limit */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault
+  * @{
+  */
+#define RCC_CRS_HSI48CALIBRATION_DEFAULT (0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
+                                                                      The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
+                                                                      corresponds to a higher output frequency */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection
+  * @{
+  */
+#define RCC_CRS_FREQERRORDIR_UP        (0x00000000U)   /*!< Upcounting direction, the actual frequency is above the target */
+#define RCC_CRS_FREQERRORDIR_DOWN      (CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
+  * @{
+  */
+#define RCC_CRS_IT_SYNCOK              CRS_CR_SYNCOKIE       /*!< SYNC event OK */
+#define RCC_CRS_IT_SYNCWARN            CRS_CR_SYNCWARNIE     /*!< SYNC warning */
+#define RCC_CRS_IT_ERR                 CRS_CR_ERRIE          /*!< Error */
+#define RCC_CRS_IT_ESYNC               CRS_CR_ESYNCIE        /*!< Expected SYNC */
+#define RCC_CRS_IT_SYNCERR             CRS_CR_ERRIE          /*!< SYNC error */
+#define RCC_CRS_IT_SYNCMISS            CRS_CR_ERRIE          /*!< SYNC missed */
+#define RCC_CRS_IT_TRIMOVF             CRS_CR_ERRIE          /*!< Trimming overflow or underflow */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
+  * @{
+  */
+#define RCC_CRS_FLAG_SYNCOK            CRS_ISR_SYNCOKF       /*!< SYNC event OK flag     */
+#define RCC_CRS_FLAG_SYNCWARN          CRS_ISR_SYNCWARNF     /*!< SYNC warning flag      */
+#define RCC_CRS_FLAG_ERR               CRS_ISR_ERRF          /*!< Error flag        */
+#define RCC_CRS_FLAG_ESYNC             CRS_ISR_ESYNCF        /*!< Expected SYNC flag     */
+#define RCC_CRS_FLAG_SYNCERR           CRS_ISR_SYNCERR       /*!< SYNC error */
+#define RCC_CRS_FLAG_SYNCMISS          CRS_ISR_SYNCMISS      /*!< SYNC missed*/
+#define RCC_CRS_FLAG_TRIMOVF           CRS_ISR_TRIMOVF       /*!< Trimming overflow or underflow */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
+  * @{
+  */
+
+/** @brief  Macros to enable or disable PLL2.
+  * @note   After enabling PLL2, the application software should wait on
+  *         PLL2RDY flag to be set indicating that PLL2 clock is stable and can
+  *         be used as kernel clock source.
+  * @note   PLL2 is disabled by hardware when entering STOP and STANDBY modes.
+  */
+#define __HAL_RCC_PLL2_ENABLE()         SET_BIT(RCC->CR, RCC_CR_PLL2ON)
+#define __HAL_RCC_PLL2_DISABLE()        CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON)
+
+/**
+  * @brief  Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK)
+  * @note   Enabling/disabling  those Clocks can be done only when the PLL2 is disabled,
+  *         This is mainly used to save Power.
+  * @param  __RCC_PLL2ClockOut__ Specifies the PLL2 clock to be outputted
+  *          This parameter can be one of the following values:
+  *            @arg RCC_PLL2_DIVP: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
+  *            @arg RCC_PLL2_DIVQ: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
+  *            @arg RCC_PLL2_DIVR: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
+  *
+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  *
+  * @retval None
+  */
+#define __HAL_RCC_PLL2CLKOUT_ENABLE(__RCC_PLL2ClockOut__)   SET_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))
+
+#define __HAL_RCC_PLL2CLKOUT_DISABLE(__RCC_PLL2ClockOut__)  CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))
+
+/**
+  * @brief  Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO
+  * @note   Enabling/disabling  Fractional Part can be any time  without the need to stop the PLL2
+  * @retval None
+  */
+#define __HAL_RCC_PLL2FRACN_ENABLE()   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)
+
+#define __HAL_RCC_PLL2FRACN_DISABLE()  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)
+
+/**
+  * @brief  Macro to configures the PLL2  multiplication and division factors.
+  * @note   This function must be used only when PLL2 is disabled.
+  *
+  * @param  __PLL2M__ specifies the division factor for PLL2 VCO input clock
+  *          This parameter must be a number between 1 and 63.
+  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
+  *         frequency ranges from 1 to 16 MHz.
+  *
+  * @param  __PLL2N__ specifies the multiplication factor for PLL2 VCO output clock
+  *          This parameter must be a number between 4 and 512 or between 8 and 420(*).
+  * @note   You have to set the PLL2N parameter correctly to ensure that the VCO
+  *         output frequency is between 150 and 420 MHz (when in medium VCO range) or
+  *         between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range)
+  *
+  * @param  __PLL2P__ specifies the division factor for peripheral kernel clocks
+  *          This parameter must be a number between 1 and 128.
+  *
+  * @param  __PLL2Q__ specifies the division factor for peripheral kernel clocks
+  *          This parameter must be a number between 1 and 128.
+  *
+  * @param  __PLL2R__ specifies the division factor for peripheral kernel clocks
+  *          This parameter must be a number between 1 and 128.
+  *
+  * @note   To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR)
+  *         is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible
+  *         value to  __PLL2P__, __PLL2Q__ or __PLL2R__ parameters.
+  * @retval None
+  *
+  *  (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  */
+
+#define __HAL_RCC_PLL2_CONFIG(__PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__,__PLL2R__ ) \
+                  do{ \
+                       MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM2) , ( (__PLL2M__) <<12U));  \
+                       WRITE_REG (RCC->PLL2DIVR , ( (((__PLL2N__) - 1U ) & RCC_PLL2DIVR_N2) | ((((__PLL2P__) -1U ) << 9U) & RCC_PLL2DIVR_P2) | \
+                       ((((__PLL2Q__) -1U) << 16U) & RCC_PLL2DIVR_Q2) | ((((__PLL2R__)- 1U) << 24U) & RCC_PLL2DIVR_R2))); \
+                    } while(0)
+
+/**
+  * @brief  Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor
+  *
+  * @note   These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO
+  *
+  * @param  __RCC_PLL2FRACN__ Specifies Fractional Part Of The Multiplication factor for PLL2 VCO
+  *                           It should be a value between 0 and 8191
+  * @note   Warning: the software has to set correctly these bits to insure that the VCO
+  *                  output frequency is between its valid frequency range, which is:
+  *                  192 to 836 MHz or 128 to 560 MHz(*) if PLL2VCOSEL = 0
+  *                  150 to 420 MHz if PLL2VCOSEL = 1.
+  *
+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  *
+  * @retval None
+  */
+#define  __HAL_RCC_PLL2FRACN_CONFIG(__RCC_PLL2FRACN__) \
+                 MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2,((uint32_t)(__RCC_PLL2FRACN__) << RCC_PLL2FRACR_FRACN2_Pos))
+
+/** @brief  Macro to select  the PLL2  reference frequency range.
+  * @param  __RCC_PLL2VCIRange__ specifies the PLL2 input frequency range
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PLL2VCIRANGE_0: Range frequency is between 1 and 2 MHz
+  *            @arg RCC_PLL2VCIRANGE_1: Range frequency is between 2 and 4 MHz
+  *            @arg RCC_PLL2VCIRANGE_2: Range frequency is between 4 and 8 MHz
+  *            @arg RCC_PLL2VCIRANGE_3: Range frequency is between 8 and 16 MHz
+  * @retval None
+  */
+#define __HAL_RCC_PLL2_VCIRANGE(__RCC_PLL2VCIRange__) \
+                  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, (__RCC_PLL2VCIRange__))
+
+
+/** @brief  Macro to select  the PLL2  reference frequency range.
+  * @param  __RCC_PLL2VCORange__ Specifies the PLL2 input frequency range
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PLL2VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*)
+  *            @arg RCC_PLL2VCOMEDIUM: Range frequency is between 150 and 420 MHz
+  *
+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  *
+  * @retval None
+  */
+#define __HAL_RCC_PLL2_VCORANGE(__RCC_PLL2VCORange__) \
+                  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, (__RCC_PLL2VCORange__))
+
+/** @brief  Macros to enable or disable the main PLL3.
+  * @note   After enabling  PLL3, the application software should wait on
+  *         PLL3RDY flag to be set indicating that PLL3 clock is stable and can
+  *         be used as kernel clock source.
+  * @note   PLL3 is disabled by hardware when entering STOP and STANDBY modes.
+  */
+#define __HAL_RCC_PLL3_ENABLE()         SET_BIT(RCC->CR, RCC_CR_PLL3ON)
+#define __HAL_RCC_PLL3_DISABLE()        CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON)
+
+/**
+  * @brief  Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO
+  * @note   Enabling/disabling  Fractional Part can be any time  without the need to stop the PLL3
+  * @retval None
+  */
+#define __HAL_RCC_PLL3FRACN_ENABLE()   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)
+
+#define __HAL_RCC_PLL3FRACN_DISABLE()  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)
+
+/**
+  * @brief  Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK)
+  * @note   Enabling/disabling  those Clocks can be done only when the PLL3 is disabled,
+  *         This is mainly used to save Power.
+  * @param  __RCC_PLL3ClockOut__ specifies the PLL3 clock to be outputted
+  *          This parameter can be one of the following values:
+  *            @arg RCC_PLL3_DIVP: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
+  *            @arg RCC_PLL3_DIVQ: This clock is used to generate peripherals clock  up to 400MHZ or 280MHZ(*)
+  *            @arg RCC_PLL3_DIVR: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
+  *
+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  *
+  * @retval None
+  */
+#define __HAL_RCC_PLL3CLKOUT_ENABLE(__RCC_PLL3ClockOut__)   SET_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))
+
+#define __HAL_RCC_PLL3CLKOUT_DISABLE(__RCC_PLL3ClockOut__)  CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))
+
+/**
+  * @brief  Macro to configures the PLL3  multiplication and division factors.
+  * @note   This function must be used only when PLL3 is disabled.
+  *
+  * @param  __PLL3M__ specifies the division factor for PLL3 VCO input clock
+  *          This parameter must be a number between 1 and 63.
+  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
+  *         frequency ranges from 1 to 16 MHz.
+  *
+  * @param  __PLL3N__ specifies the multiplication factor for PLL3 VCO output clock
+  *          This parameter must be a number between 4 and 512.
+  * @note   You have to set the PLL3N parameter correctly to ensure that the VCO
+  *         output frequency is between 150 and 420 MHz (when in medium VCO range) or
+  *         between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range)
+  *
+  * @param  __PLL3P__ specifies the division factor for peripheral kernel clocks
+  *          This parameter must be a number between 2 and 128 (where odd numbers not allowed)
+  *
+  * @param  __PLL3Q__ specifies the division factor for peripheral kernel clocks
+  *          This parameter must be a number between 1 and 128
+  *
+  * @param  __PLL3R__ specifies the division factor for peripheral kernel clocks
+  *          This parameter must be a number between 1 and 128
+  *
+  * @note   To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR)
+  *         is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible
+  *         value to  __PLL3P__, __PLL3Q__ or __PLL3R__ parameters.
+  * @retval None
+  *
+  *  (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  */
+
+#define __HAL_RCC_PLL3_CONFIG(__PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__,__PLL3R__ ) \
+                  do{ MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM3) , ( (__PLL3M__) <<20U));  \
+                         WRITE_REG (RCC->PLL3DIVR , ( (((__PLL3N__) - 1U ) & RCC_PLL3DIVR_N3) | ((((__PLL3P__) -1U ) << 9U) & RCC_PLL3DIVR_P3) | \
+                                   ((((__PLL3Q__) -1U) << 16U) & RCC_PLL3DIVR_Q3) | ((((__PLL3R__) - 1U) << 24U) & RCC_PLL3DIVR_R3))); \
+                       } while(0)
+
+
+
+/**
+  * @brief  Macro to configures  PLL3 clock Fractional Part of The Multiplication Factor
+  *
+  * @note   These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO
+  *
+  * @param  __RCC_PLL3FRACN__ specifies Fractional Part Of The Multiplication Factor for PLL3 VCO
+  *                            It should be a value between 0 and 8191
+  * @note   Warning: the software has to set correctly these bits to insure that the VCO
+  *                  output frequency is between its valid frequency range, which is:
+  *                  192 to 836 MHz or 128 to 560 MHz(*) if PLL3VCOSEL = 0
+  *                  150 to 420 MHz if PLL3VCOSEL = 1.
+  *
+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  *
+  * @retval None
+  */
+ #define  __HAL_RCC_PLL3FRACN_CONFIG(__RCC_PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << RCC_PLL3FRACR_FRACN3_Pos)
+
+/** @brief  Macro to select  the PLL3  reference frequency range.
+  * @param  __RCC_PLL3VCIRange__ specifies the PLL1 input frequency range
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PLL3VCIRANGE_0: Range frequency is between 1 and 2 MHz
+  *            @arg RCC_PLL3VCIRANGE_1: Range frequency is between 2 and 4 MHz
+  *            @arg RCC_PLL3VCIRANGE_2: Range frequency is between 4 and 8 MHz
+  *            @arg RCC_PLL3VCIRANGE_3: Range frequency is between 8 and 16 MHz
+  * @retval None
+  */
+#define __HAL_RCC_PLL3_VCIRANGE(__RCC_PLL3VCIRange__) \
+                  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, (__RCC_PLL3VCIRange__))
+
+
+/** @brief  Macro to select  the PLL3  reference frequency range.
+  * @param  __RCC_PLL3VCORange__ specifies the PLL1 input frequency range
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PLL3VCOWIDE: Range frequency is between 192 and 836 MHz  or between 128 to 560 MHz(*)
+  *            @arg RCC_PLL3VCOMEDIUM: Range frequency is between 150 and 420 MHz
+  *
+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  *
+  * @retval None
+  */
+#define __HAL_RCC_PLL3_VCORANGE(__RCC_PLL3VCORange__) \
+                  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__))
+/**
+  * @brief  Macro to Configure the SAI1 clock source.
+  * @param  __RCC_SAI1CLKSource__ defines the SAI1 clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL
+  *             @arg RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2
+  *             @arg RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3
+  *             @arg RCC_SAI1CLKSOURCE_OSC: SAI1 clock  = OSC
+  *             @arg RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock
+  * @retval None
+  */
+#if defined(RCC_D2CCIP1R_SAI1SEL)
+#define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__ )\
+                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__))
+#else
+#define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__ )\
+                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__))
+#endif /* RCC_D2CCIP1R_SAI1SEL */
+
+/** @brief  Macro to get the SAI1 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL
+  *             @arg RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2
+  *             @arg RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3
+  *             @arg RCC_SAI1CLKSOURCE_CLKP: SAI1 clock  = CLKP
+  *             @arg RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock
+  */
+#if defined(RCC_D2CCIP1R_SAI1SEL)
+#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL)))
+#else
+#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL)))
+#endif /* RCC_D2CCIP1R_SAI1SEL */
+
+/**
+  * @brief  Macro to Configure the SPDIFRX clock source.
+  * @param  __RCC_SPDIFCLKSource__ defines the SPDIFRX clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3,  or internal OSC clock
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SPDIFRXCLKSOURCE_PLL:  SPDIFRX clock = PLL
+  *             @arg RCC_SPDIFRXCLKSOURCE_PLL2: SPDIFRX clock = PLL2
+  *             @arg RCC_SPDIFRXCLKSOURCE_PLL3: SPDIFRX clock = PLL3
+  *             @arg RCC_SPDIFRXCLKSOURCE_HSI:  SPDIFRX clock  = HSI
+  * @retval None
+  */
+#if defined(RCC_D2CCIP1R_SPDIFSEL)
+#define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__ )\
+                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__))
+#else
+#define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__ )\
+                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__))
+#endif /* RCC_D2CCIP1R_SPDIFSEL */
+
+/**
+  * @brief  Macro to get the SPDIFRX clock source.
+  * @retval None
+  */
+#if defined(RCC_D2CCIP1R_SPDIFSEL)
+#define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL)))
+#else
+#define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL)))
+#endif /* RCC_D2CCIP1R_SPDIFSEL */
+
+#if defined(SAI3)
+/**
+  * @brief  Macro to Configure the SAI2/3 clock source.
+  * @param  __RCC_SAI23CLKSource__ defines the SAI2/3 clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SAI23CLKSOURCE_PLL: SAI2/3 clock = PLL
+  *             @arg RCC_SAI23CLKSOURCE_PLL2: SAI2/3 clock = PLL2
+  *             @arg RCC_SAI23CLKSOURCE_PLL3: SAI2/3 clock = PLL3
+  *             @arg RCC_SAI23CLKSOURCE_CLKP: SAI2/3 clock  = CLKP
+  *             @arg RCC_SAI23CLKSOURCE_PIN: SAI2/3 clock = External Clock
+  * @retval None
+  */
+#define __HAL_RCC_SAI23_CONFIG(__RCC_SAI23CLKSource__ )\
+                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL, (__RCC_SAI23CLKSource__))
+
+/** @brief  Macro to get the SAI2/3 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SAI23CLKSOURCE_PLL: SAI2/3 clock = PLL
+  *             @arg RCC_SAI23CLKSOURCE_PLL2: SAI2/3 clock = PLL2
+  *             @arg RCC_SAI23CLKSOURCE_PLL3: SAI2/3 clock = PLL3
+  *             @arg RCC_SAI23CLKSOURCE_CLKP: SAI2/3 clock  = CLKP
+  *             @arg RCC_SAI23CLKSOURCE_PIN: SAI2/3 clock = External Clock
+  */
+#define __HAL_RCC_GET_SAI23_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL)))
+
+/**
+  * @brief  Macro to Configure the SAI2 clock source.
+  * @param  __RCC_SAI2CLKSource__ defines the SAI2 clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SAI2CLKSOURCE_PLL: SAI2 clock = PLL
+  *             @arg RCC_SAI2CLKSOURCE_PLL2: SAI2 clock = PLL2
+  *             @arg RCC_SAI2CLKSOURCE_PLL3: SAI2 clock = PLL3
+  *             @arg RCC_SAI2CLKSOURCE_CLKP: SAI2 clock  = CLKP
+  *             @arg RCC_SAI2CLKSOURCE_PIN: SAI2 clock = External Clock
+  * @retval None
+  */
+#define __HAL_RCC_SAI2_CONFIG  __HAL_RCC_SAI23_CONFIG
+
+/** @brief  Macro to get the SAI2 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SAI2CLKSOURCE_PLL: SAI2 clock = PLL
+  *             @arg RCC_SAI2CLKSOURCE_PLL2: SAI2 clock = PLL2
+  *             @arg RCC_SAI2CLKSOURCE_PLL3: SAI2 clock = PLL3
+  *             @arg RCC_SAI2CLKSOURCE_CLKP: SAI2 clock  = CLKP
+  *             @arg RCC_SAI2CLKSOURCE_PIN: SAI2 clock = External Clock
+  */
+#define __HAL_RCC_GET_SAI2_SOURCE  __HAL_RCC_GET_SAI23_SOURCE
+
+/**
+  * @brief  Macro to Configure the SAI3 clock source.
+  * @param  __RCC_SAI3CLKSource__ defines the SAI3 clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SAI3CLKSOURCE_PLL: SAI3 clock = PLL
+  *             @arg RCC_SAI3CLKSOURCE_PLL2: SAI3 clock = PLL2
+  *             @arg RCC_SAI3CLKSOURCE_PLL3: SAI3 clock = PLL3
+  *             @arg RCC_SAI3CLKSOURCE_CLKP: SAI3 clock  = CLKP
+  *             @arg RCC_SAI3CLKSOURCE_PIN: SAI3 clock = External Clock
+  * @retval None
+  */
+#define __HAL_RCC_SAI3_CONFIG __HAL_RCC_SAI23_CONFIG
+
+/** @brief  Macro to get the SAI3 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SAI3CLKSOURCE_PLL: SAI3 clock = PLL
+  *             @arg RCC_SAI3CLKSOURCE_PLL2: SAI3 clock = PLL2
+  *             @arg RCC_SAI3CLKSOURCE_PLL3: SAI3 clock = PLL3
+  *             @arg RCC_SAI3CLKSOURCE_CLKP: SAI3 clock  = CLKP
+  *             @arg RCC_SAI3CLKSOURCE_PIN: SAI3 clock = External Clock
+  */
+#define __HAL_RCC_GET_SAI3_SOURCE  __HAL_RCC_GET_SAI23_SOURCE
+#endif /* SAI3 */
+
+#if defined(RCC_CDCCIP1R_SAI2ASEL)
+/**
+  * @brief  Macro to Configure the SAI2A clock source.
+  * @param  __RCC_SAI2ACLKSource__ defines the SAI2A clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SAI2ACLKSOURCE_PLL: SAI2A clock = PLL
+  *             @arg RCC_SAI2ACLKSOURCE_PLL2: SAI2A clock = PLL2
+  *             @arg RCC_SAI2ACLKSOURCE_PLL3: SAI2A clock = PLL3
+  *             @arg RCC_SAI2ACLKSOURCE_CLKP: SAI2A clock  = CLKP
+  *             @arg RCC_SAI2ACLKSOURCE_PIN: SAI2A clock = External Clock
+  *             @arg RCC_SAI2ACLKSOURCE_SPDIF: SAI2A clock = SPDIF Clock
+  * @retval None
+  */
+#define __HAL_RCC_SAI2A_CONFIG(__RCC_SAI2ACLKSource__ )\
+                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2ASEL, (__RCC_SAI2ACLKSource__))
+
+/** @brief  Macro to get the SAI2A clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SAI2CLKSOURCE_PLL: SAI2A clock = PLL
+  *             @arg RCC_SAI2CLKSOURCE_PLL2: SAI2A clock = PLL2
+  *             @arg RCC_SAI2CLKSOURCE_PLL3: SAI2A clock = PLL3
+  *             @arg RCC_SAI2CLKSOURCE_CLKP: SAI2A clock  = CLKP
+  *             @arg RCC_SAI2CLKSOURCE_PIN: SAI2A clock = External Clock
+  *             @arg RCC_SAI2ACLKSOURCE_SPDIF: SAI2A clock = SPDIF Clock
+  */
+#define __HAL_RCC_GET_SAI2A_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2ASEL)))
+#endif /* defined(RCC_CDCCIP1R_SAI2ASEL) */
+
+#if defined(RCC_CDCCIP1R_SAI2BSEL)
+/**
+  * @brief  Macro to Configure the SAI2B clock source.
+  * @param  __RCC_SAI2BCLKSource__ defines the SAI2B clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SAI2BCLKSOURCE_PLL: SAI2B clock = PLL
+  *             @arg RCC_SAI2BCLKSOURCE_PLL2: SAI2B clock = PLL2
+  *             @arg RCC_SAI2BCLKSOURCE_PLL3: SAI2B clock = PLL3
+  *             @arg RCC_SAI2BCLKSOURCE_CLKP: SAI2B clock  = CLKP
+  *             @arg RCC_SAI2BCLKSOURCE_PIN: SAI2B clock = External Clock
+  *             @arg RCC_SAI2BCLKSOURCE_SPDIF: SAI2B clock = SPDIF Clock
+  * @retval None
+  */
+#define __HAL_RCC_SAI2B_CONFIG(__RCC_SAI2BCLKSource__ )\
+                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2BSEL, (__RCC_SAI2BCLKSource__))
+
+/** @brief  Macro to get the SAI2B clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SAI2BCLKSOURCE_PLL: SAI2B clock = PLL
+  *             @arg RCC_SAI2BCLKSOURCE_PLL2: SAI2B clock = PLL2
+  *             @arg RCC_SAI2BCLKSOURCE_PLL3: SAI2B clock = PLL3
+  *             @arg RCC_SAI2BCLKSOURCE_CLKP: SAI2B clock  = CLKP
+  *             @arg RCC_SAI2BCLKSOURCE_PIN: SAI2B clock = External Clock
+  *             @arg RCC_SAI2BCLKSOURCE_SPDIF: SAI2B clock = SPDIF Clock
+  */
+#define __HAL_RCC_GET_SAI2B_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2BSEL)))
+#endif /* defined(RCC_CDCCIP1R_SAI2BSEL) */
+
+
+#if defined(SAI4_Block_A)
+/**
+  * @brief  Macro to Configure the SAI4A clock source.
+  * @param  __RCC_SAI4ACLKSource__ defines the SAI4A clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SAI4ACLKSOURCE_PLL: SAI4A clock = PLL
+  *             @arg RCC_SAI4ACLKSOURCE_PLL2: SAI4A clock = PLL2
+  *             @arg RCC_SAI4ACLKSOURCE_PLL3: SAI4A clock = PLL3
+  *             @arg RCC_SAI4ACLKSOURCE_CLKP: SAI4A clock  = CLKP
+  *             @arg RCC_SAI4ACLKSOURCE_PIN: SAI4A clock = External Clock
+  * @retval None
+  */
+#define __HAL_RCC_SAI4A_CONFIG(__RCC_SAI4ACLKSource__ )\
+                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL, (__RCC_SAI4ACLKSource__))
+
+/** @brief  Macro to get the SAI4A clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SAI4ACLKSOURCE_PLL: SAI4B clock = PLL
+  *             @arg RCC_SAI4ACLKSOURCE_PLL2: SAI4B clock = PLL2
+  *             @arg RCC_SAI4ACLKSOURCE_PLL3: SAI4B clock = PLL3
+  *             @arg RCC_SAI4ACLKSOURCE_CLKP: SAI4B clock  = CLKP
+  *             @arg RCC_SAI4ACLKSOURCE_PIN: SAI4B clock = External Clock
+  */
+#define __HAL_RCC_GET_SAI4A_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL)))
+#endif /* SAI4_Block_A */
+
+#if defined(SAI4_Block_B)
+/**
+  * @brief  Macro to Configure the SAI4B clock source.
+  * @param  __RCC_SAI4BCLKSource__ defines the SAI4B clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SAI4BCLKSOURCE_PLL: SAI4B clock = PLL
+  *             @arg RCC_SAI4BCLKSOURCE_PLL2: SAI4B clock = PLL2
+  *             @arg RCC_SAI4BCLKSOURCE_PLL3: SAI4B clock = PLL3
+  *             @arg RCC_SAI4BCLKSOURCE_CLKP: SAI4B clock  = CLKP
+  *             @arg RCC_SAI4BCLKSOURCE_PIN: SAI4B clock = External Clock
+  * @retval None
+  */
+#define __HAL_RCC_SAI4B_CONFIG(__RCC_SAI4BCLKSource__ )\
+                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL, (__RCC_SAI4BCLKSource__))
+
+/** @brief  Macro to get the SAI4B clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SAI4BCLKSOURCE_PLL: SAI4B clock = PLL
+  *             @arg RCC_SAI4BCLKSOURCE_PLL2: SAI4B clock = PLL2
+  *             @arg RCC_SAI4BCLKSOURCE_PLL3: SAI4B clock = PLL3
+  *             @arg RCC_SAI4BCLKSOURCE_CLKP: SAI4B clock  = CLKP
+  *             @arg RCC_SAI4BCLKSOURCE_PIN: SAI4B clock = External Clock
+  */
+#define __HAL_RCC_GET_SAI4B_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL)))
+#endif /* SAI4_Block_B */
+
+/** @brief macro to configure the I2C1/2/3 clock (I2C123CLK).
+  *
+  * @param  __I2C123CLKSource__ specifies the I2C1/2/3 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3 clock
+  *            @arg RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3 clock
+  *            @arg RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3 clock
+  *            @arg RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3 clock
+  */
+#if defined(RCC_D2CCIP2R_I2C123SEL)
+#define __HAL_RCC_I2C123_CONFIG(__I2C123CLKSource__) \
+                  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C123CLKSource__))
+#else
+#define __HAL_RCC_I2C123_CONFIG(__I2C123CLKSource__) \
+                  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_I2C123SEL, (uint32_t)(__I2C123CLKSource__))
+#endif /* RCC_D2CCIP2R_I2C123SEL */
+
+/** @brief  macro to get the I2C1/2/3 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3 clock
+  *            @arg RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3 clock
+  *            @arg RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3 clock
+  *            @arg RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3 clock
+  */
+#if defined(RCC_D2CCIP2R_I2C123SEL)
+#define __HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL)))
+#else
+#define __HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_I2C123SEL)))
+#endif /* RCC_D2CCIP2R_I2C123SEL */
+
+/** @brief macro to configure the I2C1 clock (I2C1CLK).
+  *
+  * @param  __I2C1CLKSource__ specifies the I2C1 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock
+  *            @arg RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock
+  *            @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
+  *            @arg RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock
+  */
+#define __HAL_RCC_I2C1_CONFIG  __HAL_RCC_I2C123_CONFIG
+
+/** @brief  macro to get the I2C1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock
+  *            @arg RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock
+  *            @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
+  *            @arg RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock
+  */
+#define __HAL_RCC_GET_I2C1_SOURCE __HAL_RCC_GET_I2C123_SOURCE
+
+/** @brief macro to configure the I2C2 clock (I2C2CLK).
+  *
+  * @param  __I2C2CLKSource__ specifies the I2C2 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock
+  *            @arg RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock
+  *            @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
+  *            @arg RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock
+  */
+#define __HAL_RCC_I2C2_CONFIG __HAL_RCC_I2C123_CONFIG
+
+/** @brief  macro to get the I2C2 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock
+  *            @arg RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock
+  *            @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
+  *            @arg RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock
+  */
+#define __HAL_RCC_GET_I2C2_SOURCE __HAL_RCC_GET_I2C123_SOURCE
+
+/** @brief macro to configure the I2C3 clock (I2C3CLK).
+  *
+  * @param  __I2C3CLKSource__ specifies the I2C3 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock
+  *            @arg RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock
+  *            @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
+  *            @arg RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock
+  */
+#define __HAL_RCC_I2C3_CONFIG __HAL_RCC_I2C123_CONFIG
+
+/** @brief  macro to get the I2C3 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock
+  *            @arg RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock
+  *            @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
+  *            @arg RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock
+  */
+#define __HAL_RCC_GET_I2C3_SOURCE __HAL_RCC_GET_I2C123_SOURCE
+
+/** @brief macro to configure the I2C4 clock (I2C4CLK).
+  *
+  * @param  __I2C4CLKSource__ specifies the I2C4 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock
+  *            @arg RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock
+  *            @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
+  *            @arg RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock
+  */
+#if defined(RCC_D3CCIPR_I2C4SEL)
+#define __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) \
+                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__))
+#else
+#define __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) \
+                  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__))
+#endif /* RCC_D3CCIPR_I2C4SEL */
+
+/** @brief  macro to get the I2C4 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock
+  *            @arg RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock
+  *            @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
+  *            @arg RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock
+  */
+#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL)))
+
+/** @brief macro to configure the USART1/6/9* /10* clock (USART16CLK).
+  *
+  * @param  __USART16CLKSource__ specifies the USART1/6/9* /10* clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6/9* /10* clock
+  *            @arg RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6/9* /10* clock
+  *            @arg RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6/9* /10* clock
+  *            @arg RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6/9* /10* clock
+  *            @arg RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6/9* /10* clock
+  *            @arg RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6/9* /10* clock
+  *
+  * (*) : Available on some STM32H7 lines only.
+  */
+#if defined(RCC_D2CCIP2R_USART16SEL)
+#define __HAL_RCC_USART16_CONFIG(__USART16CLKSource__) \
+                  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART16CLKSource__))
+#else
+#define __HAL_RCC_USART16910_CONFIG(__USART16910CLKSource__) \
+                  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART16910SEL, (uint32_t)(__USART16910CLKSource__))
+/* alias */
+#define __HAL_RCC_USART16_CONFIG  __HAL_RCC_USART16910_CONFIG
+#endif /* RCC_D2CCIP2R_USART16SEL */
+
+/** @brief  macro to get the USART1/6/9* /10* clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6/9* /10* clock
+  *            @arg RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6/9* /10* clock
+  *            @arg RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6/9* /10* clock
+  *            @arg RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6/9* /10* clock
+  *            @arg RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6/9* /10* clock
+  *            @arg RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6/9* /10* clock
+  *
+  * (*) : Available on some STM32H7 lines only.
+  */
+#if defined(RCC_D2CCIP2R_USART16SEL)
+#define __HAL_RCC_GET_USART16_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL)))
+#else
+#define __HAL_RCC_GET_USART16910_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART16910SEL)))
+/* alias*/
+#define  __HAL_RCC_GET_USART16_SOURCE  __HAL_RCC_GET_USART16910_SOURCE
+#endif /* RCC_D2CCIP2R_USART16SEL */
+
+/** @brief macro to configure the USART234578 clock (USART234578CLK).
+  *
+  * @param  __USART234578CLKSource__ specifies the USART2/3/4/5/7/8 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock
+  *            @arg RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock
+  *            @arg RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock
+  *            @arg RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock
+  *            @arg RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock
+  *            @arg RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock
+  */
+#if defined(RCC_D2CCIP2R_USART28SEL)
+#define __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) \
+                  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART234578CLKSource__))
+#else
+#define __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) \
+                  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL, (uint32_t)(__USART234578CLKSource__))
+#endif /* RCC_D2CCIP2R_USART28SEL */
+
+/** @brief  macro to get the USART2/3/4/5/7/8 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock
+  *            @arg RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock
+  *            @arg RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock
+  *            @arg RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock
+  *            @arg RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock
+  *            @arg RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock
+  */
+#if defined(RCC_D2CCIP2R_USART28SEL)
+#define __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
+#else
+#define __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL)))
+#endif /* RCC_D2CCIP2R_USART28SEL */
+
+/** @brief macro to configure the USART1 clock (USART1CLK).
+  *
+  * @param  __USART1CLKSource__ specifies the USART1 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
+  */
+#define __HAL_RCC_USART1_CONFIG  __HAL_RCC_USART16_CONFIG
+
+/** @brief  macro to get the USART1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
+  */
+#define __HAL_RCC_GET_USART1_SOURCE  __HAL_RCC_GET_USART16_SOURCE
+
+/** @brief macro to configure the USART2 clock (USART2CLK).
+  *
+  * @param  __USART2CLKSource__ specifies the USART2 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
+  */
+#define __HAL_RCC_USART2_CONFIG  __HAL_RCC_USART234578_CONFIG
+
+/** @brief  macro to get the USART2 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
+  */
+#define __HAL_RCC_GET_USART2_SOURCE __HAL_RCC_GET_USART234578_SOURCE
+
+/** @brief macro to configure the USART3 clock (USART3CLK).
+  *
+  * @param  __USART3CLKSource__ specifies the USART3 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_USART3CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
+  */
+#define __HAL_RCC_USART3_CONFIG  __HAL_RCC_USART234578_CONFIG
+
+/** @brief  macro to get the USART3 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
+  */
+#define __HAL_RCC_GET_USART3_SOURCE  __HAL_RCC_GET_USART234578_SOURCE
+
+/** @brief macro to configure the UART4 clock (UART4CLK).
+  *
+  * @param  __UART4CLKSource__ specifies the UART4 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
+  */
+#define __HAL_RCC_UART4_CONFIG  __HAL_RCC_USART234578_CONFIG
+
+/** @brief  macro to get the UART4 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
+  */
+#define __HAL_RCC_GET_UART4_SOURCE  __HAL_RCC_GET_USART234578_SOURCE
+
+/** @brief macro to configure the UART5 clock (UART5CLK).
+  *
+  * @param  __UART5CLKSource__ specifies the UART5 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
+  */
+#define __HAL_RCC_UART5_CONFIG  __HAL_RCC_USART234578_CONFIG
+
+/** @brief  macro to get the UART5 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
+  */
+#define __HAL_RCC_GET_UART5_SOURCE  __HAL_RCC_GET_USART234578_SOURCE
+
+/** @brief macro to configure the USART6 clock (USART6CLK).
+  *
+  * @param  __USART6CLKSource__ specifies the USART6 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
+  */
+#define __HAL_RCC_USART6_CONFIG  __HAL_RCC_USART16_CONFIG
+
+/** @brief  macro to get the USART6 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
+  */
+#define __HAL_RCC_GET_USART6_SOURCE  __HAL_RCC_GET_USART16_SOURCE
+
+/** @brief macro to configure the UART5 clock (UART7CLK).
+  *
+  * @param  __UART7CLKSource__ specifies the UART7 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
+  */
+#define __HAL_RCC_UART7_CONFIG  __HAL_RCC_USART234578_CONFIG
+
+/** @brief  macro to get the UART7 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
+  */
+#define __HAL_RCC_GET_UART7_SOURCE  __HAL_RCC_GET_USART234578_SOURCE
+
+/** @brief macro to configure the UART8 clock (UART8CLK).
+  *
+  * @param  __UART8CLKSource__ specifies the UART8 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
+  */
+#define __HAL_RCC_UART8_CONFIG  __HAL_RCC_USART234578_CONFIG
+
+/** @brief  macro to get the UART8 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
+  */
+#define __HAL_RCC_GET_UART8_SOURCE  __HAL_RCC_GET_USART234578_SOURCE
+
+#if defined(UART9)
+/** @brief macro to configure the UART9 clock (UART9CLK).
+  *
+  * @param  __UART8CLKSource__ specifies the UART8 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_UART9CLKSOURCE_D2PCLK1: APB1 Clock selected as UART9 clock
+  *            @arg RCC_UART9CLKSOURCE_PLL2: PLL2_Q Clock selected as UART9 clock
+  *            @arg RCC_UART9CLKSOURCE_PLL3: PLL3_Q Clock selected as UART9 clock
+  *            @arg RCC_UART9CLKSOURCE_HSI: HSI selected as UART9 clock
+  *            @arg RCC_UART9CLKSOURCE_CSI: CSI Clock selected as UART9 clock
+  *            @arg RCC_UART9CLKSOURCE_LSE: LSE selected as UART9 clock
+  */
+#define __HAL_RCC_UART9_CONFIG  __HAL_RCC_USART16_CONFIG
+
+/** @brief  macro to get the UART9 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_UART9CLKSOURCE_D2PCLK1: APB1 Clock selected as UART99 clock
+  *            @arg RCC_UART9CLKSOURCE_PLL2: PLL2_Q Clock selected as UART99 clock
+  *            @arg RCC_UART9CLKSOURCE_PLL3: PLL3_Q Clock selected as UART99 clock
+  *            @arg RCC_UART9CLKSOURCE_HSI: HSI selected as UART9 clock
+  *            @arg RCC_UART9CLKSOURCE_CSI: CSI Clock selected as UART9 clock
+  *            @arg RCC_UART9CLKSOURCE_LSE: LSE selected as UART9 clock
+  */
+#define __HAL_RCC_GET_UART9_SOURCE  __HAL_RCC_GET_USART16_SOURCE
+#endif /* UART9 */
+
+#if defined(USART10)
+/** @brief macro to configure the USART10 clock (USART10CLK).
+  *
+  * @param  __UART8CLKSource__ specifies the UART8 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_USART10CLKSOURCE_D2PCLK1: APB1 Clock selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_PLL2: PLL2_Q Clock selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_PLL3: PLL3_Q Clock selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_HSI: HSI selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_CSI: CSI Clock selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_LSE: LSE selected as USART10 clock
+  */
+#define __HAL_RCC_USART10_CONFIG  __HAL_RCC_USART16_CONFIG
+
+/** @brief  macro to get the USART10 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_USART10CLKSOURCE_D2PCLK1: APB1 Clock selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_PLL2: PLL2_Q Clock selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_PLL3: PLL3_Q Clock selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_HSI: HSI selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_CSI: CSI Clock selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_LSE: LSE selected as USART10 clock
+  */
+#define __HAL_RCC_GET_USART10_SOURCE  __HAL_RCC_GET_USART16_SOURCE
+#endif /* USART10 */
+
+/** @brief macro to configure the LPUART1 clock (LPUART1CLK).
+  *
+  * @param  __LPUART1CLKSource__ specifies the LPUART1 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock
+  */
+#if defined (RCC_D3CCIPR_LPUART1SEL)
+#define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \
+                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))
+#else
+#define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \
+                  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))
+#endif /* RCC_D3CCIPR_LPUART1SEL */
+
+/** @brief  macro to get the LPUART1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock
+  */
+#if defined (RCC_D3CCIPR_LPUART1SEL)
+#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL)))
+#else
+#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL)))
+#endif /* RCC_D3CCIPR_LPUART1SEL */
+
+/** @brief  macro to configure the LPTIM1 clock source.
+  *
+  * @param  __LPTIM1CLKSource__ specifies the LPTIM1 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock
+  */
+#if defined(RCC_D2CCIP2R_LPTIM1SEL)
+#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \
+                  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))
+#else
+#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \
+                  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))
+#endif /* RCC_D2CCIP2R_LPTIM1SEL */
+
+/** @brief  macro to get the LPTIM1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock
+  */
+#if defined(RCC_D2CCIP2R_LPTIM1SEL)
+#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL)))
+#else
+#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL)))
+#endif /* RCC_D2CCIP2R_LPTIM1SEL */
+
+/** @brief  macro to configure the LPTIM2 clock source.
+  *
+  * @param  __LPTIM2CLKSource__ specifies the LPTIM2 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock
+  */
+#if defined(RCC_D3CCIPR_LPTIM2SEL)
+#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) \
+                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__))
+#else
+#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) \
+                  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__))
+#endif /* RCC_D3CCIPR_LPTIM2SEL */
+
+/** @brief  macro to get the LPTIM2 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock
+  */
+#if defined(RCC_D3CCIPR_LPTIM2SEL)
+#define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL)))
+#else
+#define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL)))
+#endif /* RCC_D3CCIPR_LPTIM2SEL */
+
+/** @brief  macro to configure the LPTIM3/4/5 clock source.
+  *
+  * @param  __LPTIM345CLKSource__ specifies the LPTIM3/4/5 clock source.
+  *            @arg RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock
+  *            @arg RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock
+  *            @arg RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock
+  *            @arg RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock
+  *            @arg RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock
+  *            @arg RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock
+  */
+#if defined(RCC_D3CCIPR_LPTIM345SEL)
+#define __HAL_RCC_LPTIM345_CONFIG(__LPTIM345CLKSource__) \
+                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM345CLKSource__))
+#else
+#define __HAL_RCC_LPTIM345_CONFIG(__LPTIM3CLKSource__) \
+                  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL, (uint32_t)(__LPTIM3CLKSource__))
+#endif /* RCC_D3CCIPR_LPTIM345SEL */
+
+/** @brief  macro to get the LPTIM3/4/5 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock
+  *            @arg RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock
+  *            @arg RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock
+  *            @arg RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock
+  *            @arg RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock
+  *            @arg RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock
+  */
+#if defined(RCC_D3CCIPR_LPTIM345SEL)
+#define __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL)))
+#else
+#define __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL)))
+#endif /* RCC_D3CCIPR_LPTIM345SEL */
+
+/** @brief  macro to configure the LPTIM3 clock source.
+  *
+  * @param  __LPTIM3CLKSource__ specifies the LPTIM3 clock source.
+  *            @arg RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock
+  */
+#define __HAL_RCC_LPTIM3_CONFIG  __HAL_RCC_LPTIM345_CONFIG
+
+/** @brief  macro to get the LPTIM3 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock
+  */
+#define __HAL_RCC_GET_LPTIM3_SOURCE  __HAL_RCC_GET_LPTIM345_SOURCE
+
+#if defined(LPTIM4)
+/** @brief  macro to configure the LPTIM4 clock source.
+  *
+  * @param  __LPTIM4CLKSource__ specifies the LPTIM4 clock source.
+  *            @arg RCC_LPTIM4CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_LSE: LSE selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_LSI: LSI Clock selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_CLKP: CLKP selected as LPTIM4 clock
+  */
+#define __HAL_RCC_LPTIM4_CONFIG  __HAL_RCC_LPTIM345_CONFIG
+
+
+/** @brief  macro to get the LPTIM4 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_LPTIM4CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_LSE: LSE selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_LSI: LSI Clock selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_CLKP: CLKP selected as LPTIM4 clock
+  */
+#define __HAL_RCC_GET_LPTIM4_SOURCE  __HAL_RCC_GET_LPTIM345_SOURCE
+#endif /* LPTIM4 */
+
+#if defined(LPTIM5)
+/** @brief  macro to configure the LPTIM5 clock source.
+  *
+  * @param  __LPTIM5CLKSource__ specifies the LPTIM5 clock source.
+  *            @arg RCC_LPTIM5CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_LSE: LSE selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_LSI: LSI Clock selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_CLKP: CLKP selected as LPTIM5 clock
+  */
+#define __HAL_RCC_LPTIM5_CONFIG  __HAL_RCC_LPTIM345_CONFIG
+
+
+/** @brief  macro to get the LPTIM5 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_LPTIM5CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_LSE: LSE selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_LSI: LSI Clock selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_CLKP: CLKP selected as LPTIM5 clock
+  */
+#define __HAL_RCC_GET_LPTIM5_SOURCE  __HAL_RCC_GET_LPTIM345_SOURCE
+#endif /* LPTIM5 */
+
+#if defined(QUADSPI)
+/** @brief  macro to configure the QSPI clock source.
+  *
+  * @param  __QSPICLKSource__ specifies the QSPI clock source.
+  *            @arg RCC_RCC_QSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as QSPI clock
+  *            @arg RCC_RCC_QSPICLKSOURCE_PLL   : PLL1_Q Clock selected as QSPI clock
+  *            @arg RCC_RCC_QSPICLKSOURCE_PLL2  : PLL2_R Clock selected as QSPI clock
+  *            @arg RCC_RCC_QSPICLKSOURCE_CLKP    CLKP selected as QSPI clock
+  */
+#define __HAL_RCC_QSPI_CONFIG(__QSPICLKSource__) \
+                  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL, (uint32_t)(__QSPICLKSource__))
+
+
+/** @brief  macro to get the QSPI clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_RCC_QSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as QSPI clock
+  *            @arg RCC_RCC_QSPICLKSOURCE_PLL   : PLL1_Q Clock selected as QSPI clock
+  *            @arg RCC_RCC_QSPICLKSOURCE_PLL2  : PLL2_R Clock selected as QSPI clock
+  *            @arg RCC_RCC_QSPICLKSOURCE_CLKP    CLKP selected as QSPI clock
+  */
+#define __HAL_RCC_GET_QSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL)))
+#endif /* QUADSPI */
+
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+/** @brief  macro to configure the OSPI clock source.
+  *
+  * @param  __OSPICLKSource__ specifies the OSPI clock source.
+  *            @arg RCC_RCC_OSPICLKSOURCE_CDHCLK: Domain1 HCLK Clock selected as OSPI clock
+  *            @arg RCC_RCC_OSPICLKSOURCE_PLL   : PLL1_Q Clock selected as OSPI clock
+  *            @arg RCC_RCC_OSPICLKSOURCE_PLL2  : PLL2_R Clock selected as OSPI clock
+  *            @arg RCC_RCC_OSPICLKSOURCE_CLKP    CLKP selected as OSPI clock
+  */
+#define __HAL_RCC_OSPI_CONFIG(__OSPICLKSource__) \
+                  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL, (uint32_t)(__OSPICLKSource__))
+
+
+/** @brief  macro to get the OSPI clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_RCC_OSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as OSPI clock
+  *            @arg RCC_RCC_OSPICLKSOURCE_PLL   : PLL1_Q Clock selected as OSPI clock
+  *            @arg RCC_RCC_OSPICLKSOURCE_PLL2  : PLL2_R Clock selected as OSPI clock
+  *            @arg RCC_RCC_OSPICLKSOURCE_CLKP    CLKP selected as OSPI clock
+  */
+#define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL)))
+#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
+
+
+#if defined(DSI)
+/** @brief  macro to configure the DSI clock source.
+  *
+  * @param  __DSICLKSource__ specifies the DSI clock source.
+  *            @arg RCC_RCC_DSICLKSOURCE_PHY:DSI clock from PHY is selected as DSI byte lane clock
+  *            @arg RCC_RCC_DSICLKSOURCE_PLL2   : PLL2_Q Clock clock is selected as DSI byte lane clock
+  */
+#define __HAL_RCC_DSI_CONFIG(__DSICLKSource__) \
+                  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL, (uint32_t)(__DSICLKSource__))
+
+
+/** @brief  macro to get the DSI clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_RCC_DSICLKSOURCE_PHY: DSI clock from PHY is selected as DSI byte lane clock
+  *            @arg RCC_RCC_DSICLKSOURCE_PLL2: PLL2_Q Clock clock is selected as DSI byte lane clock
+  */
+#define __HAL_RCC_GET_DSI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL)))
+#endif /*DSI*/
+
+/** @brief  macro to configure the FMC clock source.
+  *
+  * @param  __FMCCLKSource__ specifies the FMC clock source.
+  *            @arg RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock
+  *            @arg RCC_RCC_FMCCLKSOURCE_PLL   : PLL1_Q Clock selected as FMC clock
+  *            @arg RCC_RCC_FMCCLKSOURCE_PLL2  : PLL2_R Clock selected as FMC clock
+  *            @arg RCC_RCC_FMCCLKSOURCE_CLKP    CLKP selected as FMC clock
+  */
+#if defined(RCC_D1CCIPR_FMCSEL)
+#define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) \
+                  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__))
+#else
+#define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) \
+                  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__))
+#endif /* RCC_D1CCIPR_FMCSEL */
+
+/** @brief  macro to get the FMC clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock
+  *            @arg RCC_RCC_FMCCLKSOURCE_PLL   : PLL1_Q Clock selected as FMC clock
+  *            @arg RCC_RCC_FMCCLKSOURCE_PLL2  : PLL2_R Clock selected as FMC clock
+  *            @arg RCC_RCC_FMCCLKSOURCE_CLKP    CLKP selected as FMC clock
+  */
+#if defined(RCC_D1CCIPR_FMCSEL)
+#define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL)))
+#else
+#define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL)))
+#endif /* RCC_D1CCIPR_FMCSEL */
+
+/** @brief  Macro to configure the USB clock (USBCLK).
+  * @param  __USBCLKSource__ specifies the USB clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_USBCLKSOURCE_PLL:   PLL1Q selected as USB clock
+  *            @arg RCC_USBCLKSOURCE_PLL3:  PLL3Q Clock selected as USB clock
+  *            @arg RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock
+  */
+#if defined(RCC_D2CCIP2R_USBSEL)
+#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
+                  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, (uint32_t)(__USBCLKSource__))
+#else
+#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
+                  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL, (uint32_t)(__USBCLKSource__))
+#endif /* RCC_D2CCIP2R_USBSEL */
+
+/** @brief  Macro to get the USB clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_USBCLKSOURCE_PLL:   PLL1Q selected as USB clock
+  *            @arg RCC_USBCLKSOURCE_PLL3:  PLL3Q Clock selected as USB clock
+  *            @arg RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock
+  */
+#if defined(RCC_D2CCIP2R_USBSEL)
+#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL)))
+#else
+#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL)))
+#endif /* RCC_D2CCIP2R_USBSEL */
+
+/** @brief  Macro to configure the ADC clock
+  * @param  __ADCCLKSource__ specifies the ADC digital interface clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock
+  *            @arg RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock
+  *            @arg RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock
+  */
+#if defined(RCC_D3CCIPR_ADCSEL)
+#define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \
+                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__))
+#else
+#define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \
+                  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__))
+#endif /* RCC_D3CCIPR_ADCSEL */
+
+/** @brief  Macro to get the ADC clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock
+  *            @arg RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock
+  *            @arg RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock
+  */
+#if defined(RCC_D3CCIPR_ADCSEL)
+#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL)))
+#else
+#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL)))
+#endif /* RCC_D3CCIPR_ADCSEL */
+
+ /** @brief  Macro to configure the SWPMI1 clock
+  * @param  __SWPMI1CLKSource__ specifies the SWPMI1  clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_SWPMI1CLKSOURCE_D2PCLK1:  D2PCLK1 Clock selected as SWPMI1 clock
+  *            @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock
+  */
+#if defined(RCC_D2CCIP1R_SWPSEL)
+#define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) \
+                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__))
+#else
+#define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) \
+                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__))
+#endif /* RCC_D2CCIP1R_SWPSEL */
+
+/** @brief  Macro to get the SWPMI1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_SWPMI1CLKSOURCE_D2PCLK1:  D2PCLK1 Clock selected as SWPMI1 clock
+  *            @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock
+  */
+#if defined(RCC_D2CCIP1R_SWPSEL)
+#define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL)))
+#else
+#define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL)))
+#endif /* RCC_D2CCIP1R_SWPSEL */
+
+ /** @brief  Macro to configure the DFSDM1 clock
+  * @param  __DFSDM1CLKSource__ specifies the DFSDM1  clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_DFSDM1CLKSOURCE_D2PCLK:  D2PCLK Clock selected as DFSDM1 clock
+  *            @arg RCC_DFSDM1CLKSOURCE_SYS:     System Clock selected as DFSDM1 clock
+  */
+#if defined(RCC_D2CCIP1R_DFSDM1SEL)
+#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) \
+                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__))
+#else
+#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) \
+                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__))
+#endif /* RCC_D2CCIP1R_DFSDM1SEL */
+
+/** @brief  Macro to get the DFSDM1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_DFSDM1CLKSOURCE_D2PCLK:  D2PCLK Clock selected as DFSDM1 clock
+  *            @arg RCC_DFSDM1CLKSOURCE_SYS:   System Clock selected as DFSDM1 clock
+  */
+#if defined (RCC_D2CCIP1R_DFSDM1SEL)
+#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL)))
+#else
+#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL)))
+#endif /* RCC_D2CCIP1R_DFSDM1SEL */
+
+#if defined(DFSDM2_BASE)
+ /** @brief  Macro to configure the DFSDM2 clock
+  * @param  __DFSDM2CLKSource__ specifies the DFSDM2  clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_DFSDM2CLKSOURCE_SRDPCLK1:  SRDPCLK1 (APB4) selected as DFSDM2 clock
+  *            @arg RCC_DFSDM2CLKSOURCE_SYS:   System Clock selected as DFSDM2 clock
+  */
+#define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2CLKSource__) \
+                  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL, (uint32_t)(__DFSDM2CLKSource__))
+
+/** @brief  Macro to get the DFSDM2 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_DFSDM2CLKSOURCE_SRDPCLK1:  SRDPCLK1 (APB4) Clock selected as DFSDM2 clock
+  *            @arg RCC_DFSDM2CLKSOURCE_SYS:   System Clock selected as DFSDM2 clock
+  */
+#define __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL)))
+#endif /* DFSDM2 */
+
+/** @brief macro to configure the CEC clock (CECCLK).
+  *
+  * @param  __CECCLKSource__ specifies the CEC clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
+  *            @arg RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock
+  *            @arg RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock
+  */
+#if defined(RCC_D2CCIP2R_CECSEL)
+#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
+                  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, (uint32_t)(__CECCLKSource__))
+#else
+#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
+                  MODIFY_REG(RCC->D2CCIP2R, RCC_CDCCIP2R_CECSEL, (uint32_t)(__CECCLKSource__))
+#endif /* RCC_D2CCIP2R_CECSEL */
+
+/** @brief  macro to get the CEC clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
+  *            @arg RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock
+  *            @arg RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock
+  */
+#if defined(RCC_D2CCIP2R_CECSEL)
+#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL)))
+#else
+#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL)))
+#endif /* RCC_D2CCIP2R_CECSEL */
+
+/** @brief  Macro to configure the CLKP : Oscillator clock for peripheral
+  * @param  __CLKPSource__ specifies Oscillator clock for peripheral
+  *         This parameter can be one of the following values:
+  *            @arg RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral
+  *            @arg RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral
+  *            @arg RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral
+  */
+#if defined(RCC_D1CCIPR_CKPERSEL)
+#define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \
+                  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, (uint32_t)(__CLKPSource__))
+#else
+#define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \
+                  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL, (uint32_t)(__CLKPSource__))
+#endif /* RCC_D1CCIPR_CKPERSEL */
+
+/** @brief  Macro to get the Oscillator clock for peripheral  source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral
+  *            @arg RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral
+  *            @arg RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral
+  */
+#if defined(RCC_D1CCIPR_CKPERSEL)
+#define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL)))
+#else
+#define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL)))
+#endif /* RCC_D1CCIPR_CKPERSEL */
+
+#if defined(FDCAN1) || defined(FDCAN2)
+/** @brief  Macro to configure the FDCAN clock
+  * @param  __FDCANCLKSource__ specifies  clock source  for FDCAN
+  *         This parameter can be one of the following values:
+  *            @arg RCC_FDCANCLKSOURCE_HSE: HSE selected as FDCAN clock
+  *            @arg RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock
+  *            @arg RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock
+  */
+#if defined(RCC_D2CCIP1R_FDCANSEL)
+#define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) \
+                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__))
+#else
+#define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) \
+                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__))
+#endif /* RCC_D2CCIP1R_FDCANSEL */
+
+/** @brief  Macro to get the FDCAN clock
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_FDCANCLKSOURCE_HSE: HSE selected as FDCAN clock
+  *            @arg RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock
+  *            @arg RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock
+  */
+#if defined(RCC_D2CCIP1R_FDCANSEL)
+#define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL)))
+#else
+#define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL)))
+#endif /* RCC_D2CCIP1R_FDCANSEL */
+
+#endif /*FDCAN1 || FDCAN2*/
+
+/**
+  * @brief  Macro to Configure the SPI1/2/3 clock source.
+  * @param  __RCC_SPI123CLKSource__ defines the SPI1/2/3 clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL
+  *             @arg RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2
+  *             @arg RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3
+  *             @arg RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock  = CLKP
+  *             @arg RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock
+  * @retval None
+  */
+#if defined(RCC_D2CCIP1R_SPI123SEL)
+#define __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__ )\
+                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__))
+#else
+#define __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__ )\
+                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__))
+#endif /* RCC_D2CCIP1R_SPI123SEL */
+
+/** @brief  Macro to get the SPI1/2/3 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL
+  *             @arg RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2
+  *             @arg RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3
+  *             @arg RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock  = CLKP
+  *             @arg RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock
+  */
+#if defined(RCC_D2CCIP1R_SPI123SEL)
+#define __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL)))
+#else
+#define __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL)))
+#endif /* RCC_D2CCIP1R_SPI123SEL */
+
+/**
+  * @brief  Macro to Configure the SPI1 clock source.
+  * @param  __RCC_SPI1CLKSource__ defines the SPI1 clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL
+  *             @arg RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2
+  *             @arg RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3
+  *             @arg RCC_SPI1CLKSOURCE_CLKP: SPI1 clock  = CLKP
+  *             @arg RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock
+  * @retval None
+  */
+#define __HAL_RCC_SPI1_CONFIG  __HAL_RCC_SPI123_CONFIG
+
+/** @brief  Macro to get the SPI1 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL
+  *             @arg RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2
+  *             @arg RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3
+  *             @arg RCC_SPI1CLKSOURCE_CLKP: SPI1 clock  = CLKP
+  *             @arg RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock
+  */
+#define __HAL_RCC_GET_SPI1_SOURCE  __HAL_RCC_GET_SPI123_SOURCE
+
+/**
+  * @brief  Macro to Configure the SPI2 clock source.
+  * @param  __RCC_SPI2CLKSource__ defines the SPI2 clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL
+  *             @arg RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2
+  *             @arg RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3
+  *             @arg RCC_SPI2CLKSOURCE_CLKP: SPI2 clock  = CLKP
+  *             @arg RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock
+  * @retval None
+  */
+#define __HAL_RCC_SPI2_CONFIG  __HAL_RCC_SPI123_CONFIG
+
+/** @brief  Macro to get the SPI2 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL
+  *             @arg RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2
+  *             @arg RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3
+  *             @arg RCC_SPI2CLKSOURCE_CLKP: SPI2 clock  = CLKP
+  *             @arg RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock
+  */
+#define __HAL_RCC_GET_SPI2_SOURCE  __HAL_RCC_GET_SPI123_SOURCE
+
+/**
+  * @brief  Macro to Configure the SPI3 clock source.
+  * @param  __RCC_SPI3CLKSource__ defines the SPI3 clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL
+  *             @arg RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2
+  *             @arg RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3
+  *             @arg RCC_SPI3CLKSOURCE_CLKP: SPI3 clock  = CLKP
+  *             @arg RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock
+  * @retval None
+  */
+#define __HAL_RCC_SPI3_CONFIG  __HAL_RCC_SPI123_CONFIG
+
+/** @brief  Macro to get the SPI3 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL
+  *             @arg RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2
+  *             @arg RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3
+  *             @arg RCC_SPI3CLKSOURCE_CLKP: SPI3 clock  = CLKP
+  *             @arg RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock
+  */
+#define __HAL_RCC_GET_SPI3_SOURCE  __HAL_RCC_GET_SPI123_SOURCE
+
+/**
+  * @brief  Macro to Configure the SPI4/5 clock source.
+  * @param  __RCC_SPI45CLKSource__ defines the SPI4/5 clock source. This clock is derived
+  *         from system PCLK, PLL2, PLL3, OSC
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SPI45CLKSOURCE_D2PCLK1:SPI4/5 clock = D2PCLK1
+  *             @arg RCC_SPI45CLKSOURCE_PLL2:   SPI4/5 clock = PLL2
+  *             @arg RCC_SPI45CLKSOURCE_PLL3:   SPI4/5 clock = PLL3
+  *             @arg RCC_SPI45CLKSOURCE_HSI:    SPI4/5 clock = HSI
+  *             @arg RCC_SPI45CLKSOURCE_CSI:    SPI4/5 clock = CSI
+  *             @arg RCC_SPI45CLKSOURCE_HSE:    SPI4/5 clock = HSE
+  * @retval None
+  */
+#if defined(RCC_D2CCIP1R_SPI45SEL)
+#define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__ )\
+                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__))
+#else
+#define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__ )\
+                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__))
+#endif /* RCC_D2CCIP1R_SPI45SEL */
+
+/** @brief  Macro to get the SPI4/5 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SPI45CLKSOURCE_D2PCLK1:SPI4/5 clock = D2PCLK1
+  *             @arg RCC_SPI45CLKSOURCE_PLL2:   SPI4/5 clock = PLL2
+  *             @arg RCC_SPI45CLKSOURCE_PLL3:   SPI4/5 clock = PLL3
+  *             @arg RCC_SPI45CLKSOURCE_HSI:    SPI4/5 clock = HSI
+  *             @arg RCC_SPI45CLKSOURCE_CSI:    SPI4/5 clock = CSI
+  *             @arg RCC_SPI45CLKSOURCE_HSE:    SPI4/5 clock = HSE
+*/
+#if defined(RCC_D2CCIP1R_SPI45SEL)
+#define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL)))
+#else
+#define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL)))
+#endif /* RCC_D2CCIP1R_SPI45SEL */
+
+/**
+  * @brief  Macro to Configure the SPI4 clock source.
+  * @param  __RCC_SPI4CLKSource__ defines the SPI4 clock source. This clock is derived
+  *         from system PCLK, PLL2, PLL3, OSC
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1
+  *             @arg RCC_SPI4CLKSOURCE_PLL2:   SPI4 clock = PLL2
+  *             @arg RCC_SPI4CLKSOURCE_PLL3:   SPI4 clock = PLL3
+  *             @arg RCC_SPI4CLKSOURCE_HSI:    SPI4 clock = HSI
+  *             @arg RCC_SPI4CLKSOURCE_CSI:    SPI4 clock = CSI
+  *             @arg RCC_SPI4CLKSOURCE_HSE:    SPI4 clock = HSE
+  * @retval None
+  */
+#define __HAL_RCC_SPI4_CONFIG  __HAL_RCC_SPI45_CONFIG
+
+/** @brief  Macro to get the SPI4 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1
+  *             @arg RCC_SPI4CLKSOURCE_PLL2:   SPI4 clock = PLL2
+  *             @arg RCC_SPI4CLKSOURCE_PLL3:   SPI4 clock = PLL3
+  *             @arg RCC_SPI4CLKSOURCE_HSI:    SPI4 clock = HSI
+  *             @arg RCC_SPI4CLKSOURCE_CSI:    SPI4 clock = CSI
+  *             @arg RCC_SPI4CLKSOURCE_HSE:    SPI4 clock = HSE
+*/
+#define __HAL_RCC_GET_SPI4_SOURCE  __HAL_RCC_GET_SPI45_SOURCE
+
+/**
+  * @brief  Macro to Configure the SPI5 clock source.
+  * @param  __RCC_SPI5CLKSource__ defines the SPI5 clock source. This clock is derived
+  *         from system PCLK, PLL2, PLL3, OSC
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1
+  *             @arg RCC_SPI5CLKSOURCE_PLL2:   SPI5 clock = PLL2
+  *             @arg RCC_SPI5CLKSOURCE_PLL3:   SPI5 clock = PLL3
+  *             @arg RCC_SPI5CLKSOURCE_HSI:    SPI5 clock = HSI
+  *             @arg RCC_SPI5CLKSOURCE_CSI:    SPI5 clock = CSI
+  *             @arg RCC_SPI5CLKSOURCE_HSE:    SPI5 clock = HSE
+  * @retval None
+  */
+#define __HAL_RCC_SPI5_CONFIG  __HAL_RCC_SPI45_CONFIG
+
+/** @brief  Macro to get the SPI5 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1
+  *             @arg RCC_SPI5CLKSOURCE_PLL2:   SPI5 clock = PLL2
+  *             @arg RCC_SPI5CLKSOURCE_PLL3:   SPI5 clock = PLL3
+  *             @arg RCC_SPI5CLKSOURCE_HSI:    SPI5 clock = HSI
+  *             @arg RCC_SPI5CLKSOURCE_CSI:    SPI5 clock = CSI
+  *             @arg RCC_SPI5CLKSOURCE_HSE:    SPI5 clock = HSE
+*/
+#define __HAL_RCC_GET_SPI5_SOURCE  __HAL_RCC_GET_SPI45_SOURCE
+
+/**
+  * @brief  Macro to Configure the SPI6 clock source.
+  * @param  __RCC_SPI6CLKSource__ defines the SPI6 clock source. This clock is derived
+  *         from system PCLK, PLL2, PLL3, OSC
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1
+  *             @arg RCC_SPI6CLKSOURCE_PLL2:   SPI6 clock = PLL2
+  *             @arg RCC_SPI6CLKSOURCE_PLL3:   SPI6 clock = PLL3
+  *             @arg RCC_SPI6CLKSOURCE_HSI:    SPI6 clock = HSI
+  *             @arg RCC_SPI6CLKSOURCE_CSI:    SPI6 clock = CSI
+  *             @arg RCC_SPI6CLKSOURCE_HSE:    SPI6 clock = HSE
+  *             @arg RCC_SPI6CLKSOURCE_PIN:    SPI6 clock = I2S_CKIN (*)
+  *
+  * @retval None
+  *
+  * (*) : Available on stm32h7a3xx and stm32h7b3xx family lines.
+  *
+  */
+#if defined(RCC_D3CCIPR_SPI6SEL)
+#define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__ )\
+                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL, (__RCC_SPI6CLKSource__))
+#else
+#define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__ )\
+                  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL, (__RCC_SPI6CLKSource__))
+#endif /* RCC_D3CCIPR_SPI6SEL */
+
+/** @brief  Macro to get the SPI6 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1
+  *             @arg RCC_SPI6CLKSOURCE_PLL2:   SPI6 clock = PLL2
+  *             @arg RCC_SPI6CLKSOURCE_PLL3:   SPI6 clock = PLL3
+  *             @arg RCC_SPI6CLKSOURCE_HSI:    SPI6 clock = HSI
+  *             @arg RCC_SPI6CLKSOURCE_CSI:    SPI6 clock = CSI
+  *             @arg RCC_SPI6CLKSOURCE_HSE:    SPI6 clock = HSE
+  *                @arg RCC_SPI6CLKSOURCE_PIN:    SPI6 clock = I2S_CKIN
+*/
+#if defined(RCC_D3CCIPR_SPI6SEL)
+#define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL)))
+#else
+#define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL)))
+#endif /* RCC_D3CCIPR_SPI6SEL */
+
+/** @brief  Macro to configure the SDMMC clock
+  * @param  __SDMMCCLKSource__ specifies  clock source  for SDMMC
+  *         This parameter can be one of the following values:
+  *            @arg RCC_SDMMCCLKSOURCE_PLL:  PLLQ selected as SDMMC clock
+  *            @arg RCC_SDMMCCLKSOURCE_PLL2: PLL2R selected as SDMMC clock
+  */
+#if defined(RCC_D1CCIPR_SDMMCSEL)
+#define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) \
+                  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__))
+#else
+#define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) \
+                  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__))
+#endif /* RCC_D1CCIPR_SDMMCSEL */
+
+/** @brief  Macro to get the SDMMC clock
+  */
+#if defined(RCC_D1CCIPR_SDMMCSEL)
+#define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL)))
+#else
+#define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL)))
+#endif /* RCC_D1CCIPR_SDMMCSEL */
+
+/** @brief macro to configure the RNG clock (RNGCLK).
+  *
+  * @param  __RNGCLKSource__ specifies the RNG clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
+  *            @arg RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock
+  *            @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock
+  *            @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock
+  */
+#if defined(RCC_D2CCIP2R_RNGSEL)
+#define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \
+                  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__))
+#else
+#define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \
+                  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__))
+#endif /* RCC_D2CCIP2R_RNGSEL */
+
+/** @brief  macro to get the RNG clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
+  *            @arg RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock
+  *            @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock
+  *            @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock
+  */
+#if defined(RCC_D2CCIP2R_RNGSEL)
+#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL)))
+#else
+#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL)))
+#endif /* RCC_D2CCIP2R_RNGSEL */
+
+#if defined(HRTIM1)
+/** @defgroup RCCEx_HRTIMx_Clock_Config RCC Extended HRTIMx Clock Config
+  * @{
+  */
+/** @brief  Macro to configure the HRTIM1 prescaler clock source.
+  * @param  __HRTIM1CLKSource__ specifies the HRTIM1 prescaler clock source.
+  *         This parameter can be one of the following values:
+  *            @arg @ref RCC_HRTIM1CLK_TIMCLK    Timers  clock  selected as HRTIM1 prescaler clock
+  *            @arg @ref RCC_HRTIM1CLK_CPUCLK CPU Clock selected as HRTIM1 clock
+  */
+#define __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) \
+                  MODIFY_REG(RCC->CFGR, RCC_CFGR_HRTIMSEL, (uint32_t)(__HRTIM1CLKSource__))
+
+/** @brief  Macro to get the HRTIM1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg @ref RCC_HRTIM1CLK_TIMCLK   Timers  clock  selected as HRTIM1 prescaler clock
+  *            @arg @ref RCC_HRTIM1CLK_CPUCLK CPU Clock selected as HRTIM1 clock
+  */
+#define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HRTIMSEL)))
+#endif /* HRTIM1 */
+
+/** @brief  Macro to configure the Timers clocks prescalers
+  * @param  __PRESC__  specifies the Timers clocks prescalers selection
+  *         This parameter can be one of the following values:
+  *            @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
+  *                 equal to rcc_hclk1 if D2PPREx is corresponding to division by 1 or 2,
+  *                 else it is equal to 2 x Frcc_pclkx_d2 (default after reset)
+  *            @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
+  *                 equal to rcc_hclk1 if D2PPREx is corresponding to division by 1, 2 or 4,
+  *                 else it is equal to 4 x Frcc_pclkx_d2
+  */
+#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->CFGR &= ~(RCC_CFGR_TIMPRE);\
+                                                 RCC->CFGR |= (__PRESC__);       \
+                                                }while(0)
+
+/**
+  * @}
+  */
+    
+/**
+  * @brief Enable the RCC LSE CSS Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT()      SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Disable the RCC LSE CSS Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT()     CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Enable the RCC LSE CSS Event Line.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Disable the RCC LSE CSS Event Line.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
+
+#if defined(DUAL_CORE)
+/**
+  * @brief Enable the RCC LSE CSS Extended Interrupt Line for CM4.
+  * @retval None
+  */
+#define __HAL_RCC_C2_LSECSS_EXTI_ENABLE_IT()       SET_BIT(EXTI->C2IMR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Disable the RCC LSE CSS Extended Interrupt Line for CM4.
+  * @retval None
+  */
+#define __HAL_RCC_C2_LSECSS_EXTI_DISABLE_IT()      CLEAR_BIT(EXTI->C2IMR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Enable the RCC LSE CSS Event Line for CM4.
+  * @retval None.
+  */
+#define __HAL_RCC_C2_LSECSS_EXTI_ENABLE_EVENT()    SET_BIT(EXTI->C2EMR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Disable the RCC LSE CSS Event Line for CM4.
+  * @retval None.
+  */
+#define __HAL_RCC_C2_LSECSS_EXTI_DISABLE_EVENT()   CLEAR_BIT(EXTI->C2EMR1, RCC_EXTI_LINE_LSECSS)
+#endif /* DUAL_CORE */
+
+/**
+  * @brief  Enable the RCC LSE CSS Extended Interrupt Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE()  SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
+
+
+/**
+  * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
+
+
+/**
+  * @brief  Enable the RCC LSE CSS Extended Interrupt Rising Trigger.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE()  \
+  do {                                                      \
+    __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();             \
+    __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE();            \
+  } while(0)
+
+/**
+  * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE()  \
+  do {                                                       \
+    __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE();             \
+    __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE();            \
+  } while(0)
+
+/**
+  * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
+  * @retval EXTI RCC LSE CSS Line Status.
+  */
+#define __HAL_RCC_LSECSS_EXTI_GET_FLAG()       (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Clear the RCC LSE CSS EXTI flag.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG()     WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS)
+
+#if defined(DUAL_CORE)
+/**
+  * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not for CM4.
+  * @retval EXTI RCC LSE CSS Line Status.
+  */
+#define __HAL_RCC_C2_LSECSS_EXTI_GET_FLAG()       (READ_BIT(EXTI->C2PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Clear the RCC LSE CSS EXTI flag or not for CM4.
+  * @retval None.
+  */
+#define __HAL_RCC_C2_LSECSS_EXTI_CLEAR_FLAG()     WRITE_REG(EXTI->C2PR1, RCC_EXTI_LINE_LSECSS)
+#endif /* DUAL_CORE */
+/**
+  * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT()  SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS)
+ 
+/**
+  * @brief  Enable the specified CRS interrupts.
+  * @param  __INTERRUPT__ specifies the CRS interrupt sources to be enabled.
+  *          This parameter can be any combination of the following values:
+  *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
+  *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
+  *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
+  *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
+  * @retval None
+  */
+#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__)   SET_BIT(CRS->CR, (__INTERRUPT__))
+
+/**
+  * @brief  Disable the specified CRS interrupts.
+  * @param  __INTERRUPT__ specifies the CRS interrupt sources to be disabled.
+  *          This parameter can be any combination of the following values:
+  *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
+  *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
+  *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
+  *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
+  * @retval None
+  */
+#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__)  CLEAR_BIT(CRS->CR, (__INTERRUPT__))
+
+/** @brief  Check whether the CRS interrupt has occurred or not.
+  * @param  __INTERRUPT__ specifies the CRS interrupt source to check.
+  *         This parameter can be one of the following values:
+  *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
+  *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
+  *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
+  *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
+  * @retval The new state of __INTERRUPT__ (SET or RESET).
+  */
+#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__)  ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET)
+
+/** @brief  Clear the CRS interrupt pending bits
+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
+  *         This parameter can be any combination of the following values:
+  *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
+  *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
+  *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
+  *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
+  *              @arg @ref RCC_CRS_IT_TRIMOVF  Trimming overflow or underflow interrupt
+  *              @arg @ref RCC_CRS_IT_SYNCERR  SYNC error interrupt
+  *              @arg @ref RCC_CRS_IT_SYNCMISS  SYNC missed interrupt
+  */
+/* CRS IT Error Mask */
+#define  RCC_CRS_IT_ERROR_MASK                 ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))
+
+#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__)  do { \
+                                                 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \
+                                                 { \
+                                                   WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
+                                                 } \
+                                                 else \
+                                                 { \
+                                                   WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
+                                                 } \
+                                               } while(0)
+
+/**
+  * @brief  Check whether the specified CRS flag is set or not.
+  * @param  __FLAG__ specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *              @arg @ref RCC_CRS_FLAG_SYNCOK  SYNC event OK
+  *              @arg @ref RCC_CRS_FLAG_SYNCWARN  SYNC warning
+  *              @arg @ref RCC_CRS_FLAG_ERR  Error
+  *              @arg @ref RCC_CRS_FLAG_ESYNC  Expected SYNC
+  *              @arg @ref RCC_CRS_FLAG_TRIMOVF  Trimming overflow or underflow
+  *              @arg @ref RCC_CRS_FLAG_SYNCERR  SYNC error
+  *              @arg @ref RCC_CRS_FLAG_SYNCMISS  SYNC missed
+  * @retval The new state of _FLAG_ (TRUE or FALSE).
+  */
+#define __HAL_RCC_CRS_GET_FLAG(__FLAG__)  (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
+
+/**
+  * @brief  Clear the CRS specified FLAG.
+  * @param __FLAG__ specifies the flag to clear.
+  *          This parameter can be one of the following values:
+  *              @arg @ref RCC_CRS_FLAG_SYNCOK  SYNC event OK
+  *              @arg @ref RCC_CRS_FLAG_SYNCWARN  SYNC warning
+  *              @arg @ref RCC_CRS_FLAG_ERR  Error
+  *              @arg @ref RCC_CRS_FLAG_ESYNC  Expected SYNC
+  *              @arg @ref RCC_CRS_FLAG_TRIMOVF  Trimming overflow or underflow
+  *              @arg @ref RCC_CRS_FLAG_SYNCERR  SYNC error
+  *              @arg @ref RCC_CRS_FLAG_SYNCMISS  SYNC missed
+  * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR
+  * @retval None
+  */
+
+/* CRS Flag Error Mask */
+#define RCC_CRS_FLAG_ERROR_MASK                ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))
+
+#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__)     do { \
+                                                 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \
+                                                 { \
+                                                   WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
+                                                 } \
+                                                 else \
+                                                 { \
+                                                   WRITE_REG(CRS->ICR, (__FLAG__)); \
+                                                 } \
+                                               } while(0)
+
+ /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
+  * @{
+  */
+/**
+  * @brief  Enable the oscillator clock for frequency error counter.
+  * @note   when the CEN bit is set the CRS_CFGR register becomes write-protected.
+  * @retval None
+  */
+#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE()  SET_BIT(CRS->CR, CRS_CR_CEN)
+
+/**
+  * @brief  Disable the oscillator clock for frequency error counter.
+  * @retval None
+  */
+#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
+
+/**
+  * @brief  Enable the automatic hardware adjustment of TRIM bits.
+  * @note   When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
+  * @retval None
+  */
+#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE()     SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
+
+/**
+  * @brief  Enable or disable the automatic hardware adjustment of TRIM bits.
+  * @retval None
+  */
+#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE()    CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
+
+/**
+  * @brief  Macro to calculate reload value to be set in CRS register according to target and sync frequencies
+  * @note   The RELOAD value should be selected according to the ratio between the target frequency and the frequency
+  *             of the synchronization source after pre-scaling. It is then decreased by one in order to
+  *             reach the expected synchronization on the zero value. The formula is the following:
+  *             RELOAD = (fTARGET / fSYNC) -1
+  * @param  __FTARGET__ Target frequency (value in Hz)
+  * @param  __FSYNC__ Synchronization signal frequency (value in Hz)
+  * @retval None
+  */
+#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)  (((__FTARGET__) / (__FSYNC__)) - 1U)
+
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCCEx_Exported_Functions_Group1
+  * @{
+  */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
+uint32_t HAL_RCCEx_GetD1PCLK1Freq(void);
+uint32_t HAL_RCCEx_GetD3PCLK1Freq(void);
+uint32_t HAL_RCCEx_GetD1SysClockFreq(void);
+void     HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef* PLL1_Clocks);
+void     HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef* PLL2_Clocks);
+void     HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef* PLL3_Clocks);
+/**
+  * @}
+  */
+
+/** @addtogroup RCCEx_Exported_Functions_Group2
+  * @{
+  */
+void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk);
+void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk);
+void HAL_RCCEx_EnableLSECSS(void);
+void HAL_RCCEx_DisableLSECSS(void);
+void HAL_RCCEx_EnableLSECSS_IT(void);
+void HAL_RCCEx_LSECSS_IRQHandler(void);
+void HAL_RCCEx_LSECSS_Callback(void);
+#if defined(DUAL_CORE)
+void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx);
+#endif /*DUAL_CORE*/
+#if defined(RCC_GCR_WW1RSC)
+void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx);
+#endif /*RCC_GCR_WW1RSC*/
+/**
+  * @}
+  */
+
+
+/** @addtogroup RCCEx_Exported_Functions_Group3
+  * @{
+  */
+
+void     HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
+void     HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
+void     HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
+uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
+void     HAL_RCCEx_CRS_IRQHandler(void);
+void     HAL_RCCEx_CRS_SyncOkCallback(void);
+void     HAL_RCCEx_CRS_SyncWarnCallback(void);
+void     HAL_RCCEx_CRS_ExpectedSyncCallback(void);
+void     HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
+
+/**
+  * @}
+  */
+
+ /* Private macros ------------------------------------------------------------*/
+/** @addtogroup RCCEx_Private_Macros RCCEx Private Macros
+  * @{
+  */
+/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
+  * @{
+  */
+
+#define IS_RCC_PLL2CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL2_DIVP) || \
+                                         ((VALUE) == RCC_PLL2_DIVQ)  || \
+                                         ((VALUE) == RCC_PLL2_DIVR))
+
+#define IS_RCC_PLL3CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL3_DIVP) || \
+                                          ((VALUE) == RCC_PLL3_DIVQ) || \
+                                          ((VALUE) == RCC_PLL3_DIVR))
+
+#if defined(RCC_D2CCIP2R_USART16SEL)
+#define IS_RCC_USART16CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART16CLKSOURCE_D2PCLK2)|| \
+                                         ((SOURCE) == RCC_USART16CLKSOURCE_PLL2)   || \
+                                         ((SOURCE) == RCC_USART16CLKSOURCE_PLL3)   || \
+                                         ((SOURCE) == RCC_USART16CLKSOURCE_CSI)    || \
+                                         ((SOURCE) == RCC_USART16CLKSOURCE_LSE)    || \
+                                         ((SOURCE) == RCC_USART16CLKSOURCE_HSI))
+#else
+#define IS_RCC_USART16CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART16CLKSOURCE_D2PCLK2)|| \
+                                         ((SOURCE) == RCC_USART16CLKSOURCE_CDPCLK2)|| \
+                                         ((SOURCE) == RCC_USART16CLKSOURCE_PLL2)   || \
+                                         ((SOURCE) == RCC_USART16CLKSOURCE_PLL3)   || \
+                                         ((SOURCE) == RCC_USART16CLKSOURCE_CSI)    || \
+                                         ((SOURCE) == RCC_USART16CLKSOURCE_LSE)    || \
+                                         ((SOURCE) == RCC_USART16CLKSOURCE_HSI))
+/* alias*/
+#define IS_RCC_USART16910CLKSOURCE    IS_RCC_USART16CLKSOURCE
+#endif /* RCC_D2CCIP2R_USART16SEL */
+
+#if defined(RCC_D2CCIP2R_USART28SEL)
+#define IS_RCC_USART234578CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART234578CLKSOURCE_D2PCLK1)|| \
+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_PLL2)   || \
+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_PLL3)   || \
+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_CSI)    || \
+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_LSE)    || \
+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_HSI))
+#else
+#define IS_RCC_USART234578CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART234578CLKSOURCE_D2PCLK1)|| \
+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_CDPCLK1)|| \
+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_PLL2)   || \
+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_PLL3)   || \
+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_CSI)    || \
+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_LSE)    || \
+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_HSI))
+#endif /* RCC_D2CCIP2R_USART28SEL */
+
+#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_D2PCLK2)|| \
+                                        ((SOURCE) == RCC_USART1CLKSOURCE_PLL2)   || \
+                                        ((SOURCE) == RCC_USART1CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_USART1CLKSOURCE_CSI)    || \
+                                        ((SOURCE) == RCC_USART1CLKSOURCE_LSE)    || \
+                                        ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
+
+#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_D2PCLK1)|| \
+                                        ((SOURCE) == RCC_USART2CLKSOURCE_PLL2)   || \
+                                        ((SOURCE) == RCC_USART2CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_USART2CLKSOURCE_CSI)    || \
+                                        ((SOURCE) == RCC_USART2CLKSOURCE_LSE)    || \
+                                        ((SOURCE) == RCC_USART2CLKSOURCE_HSI))
+
+#define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_D2PCLK1)|| \
+                                        ((SOURCE) == RCC_USART3CLKSOURCE_PLL2)   || \
+                                        ((SOURCE) == RCC_USART3CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_USART3CLKSOURCE_CSI)    || \
+                                        ((SOURCE) == RCC_USART3CLKSOURCE_LSE)    || \
+                                        ((SOURCE) == RCC_USART3CLKSOURCE_HSI))
+
+#define IS_RCC_UART4CLKSOURCE(SOURCE)  (((SOURCE) == RCC_UART4CLKSOURCE_D2PCLK1) || \
+                                        ((SOURCE) == RCC_UART4CLKSOURCE_PLL2)    || \
+                                        ((SOURCE) == RCC_UART4CLKSOURCE_PLL3)    || \
+                                        ((SOURCE) == RCC_UART4CLKSOURCE_CSI)     || \
+                                        ((SOURCE) == RCC_UART4CLKSOURCE_LSE)     || \
+                                        ((SOURCE) == RCC_UART4CLKSOURCE_HSI))
+
+#define IS_RCC_UART5CLKSOURCE(SOURCE)  (((SOURCE) == RCC_UART5CLKSOURCE_D2PCLK1) || \
+                                        ((SOURCE) == RCC_UART5CLKSOURCE_PLL2)    || \
+                                        ((SOURCE) == RCC_UART5CLKSOURCE_PLL3)    || \
+                                        ((SOURCE) == RCC_UART5CLKSOURCE_CSI)     || \
+                                        ((SOURCE) == RCC_UART5CLKSOURCE_LSE)     || \
+                                        ((SOURCE) == RCC_UART5CLKSOURCE_HSI))
+
+#define IS_RCC_USART6CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART6CLKSOURCE_D2PCLK2)|| \
+                                        ((SOURCE) == RCC_USART6CLKSOURCE_PLL2)   || \
+                                        ((SOURCE) == RCC_USART6CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_USART6CLKSOURCE_CSI)    || \
+                                        ((SOURCE) == RCC_USART6CLKSOURCE_LSE)    || \
+                                        ((SOURCE) == RCC_USART6CLKSOURCE_HSI))
+
+#define IS_RCC_UART7CLKSOURCE(SOURCE)  (((SOURCE) == RCC_UART7CLKSOURCE_D2PCLK1) || \
+                                        ((SOURCE) == RCC_UART7CLKSOURCE_PLL2)    || \
+                                        ((SOURCE) == RCC_UART7CLKSOURCE_PLL3)    || \
+                                        ((SOURCE) == RCC_UART7CLKSOURCE_CSI)     || \
+                                        ((SOURCE) == RCC_UART7CLKSOURCE_LSE)     || \
+                                        ((SOURCE) == RCC_UART7CLKSOURCE_HSI))
+
+#define IS_RCC_UART8CLKSOURCE(SOURCE)  (((SOURCE) == RCC_UART8CLKSOURCE_D2PCLK1) || \
+                                        ((SOURCE) == RCC_UART8CLKSOURCE_PLL2)    || \
+                                        ((SOURCE) == RCC_UART8CLKSOURCE_PLL3)    || \
+                                        ((SOURCE) == RCC_UART8CLKSOURCE_CSI)     || \
+                                        ((SOURCE) == RCC_UART8CLKSOURCE_LSE)     || \
+                                        ((SOURCE) == RCC_UART8CLKSOURCE_HSI))
+
+#if defined(UART9)
+#define IS_RCC_UART9CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART9CLKSOURCE_D2PCLK2)|| \
+                                        ((SOURCE) == RCC_UART9CLKSOURCE_PLL2)  || \
+                                        ((SOURCE) == RCC_UART9CLKSOURCE_PLL3)  || \
+                                        ((SOURCE) == RCC_UART9CLKSOURCE_CSI)   || \
+                                        ((SOURCE) == RCC_UART9CLKSOURCE_LSE)   || \
+                                        ((SOURCE) == RCC_UART9CLKSOURCE_HSI))
+#endif
+
+#if defined(USART10)
+#define IS_RCC_USART10CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART10CLKSOURCE_D2PCLK2)|| \
+                                        ((SOURCE) == RCC_USART10CLKSOURCE_PLL2)    || \
+                                        ((SOURCE) == RCC_USART10CLKSOURCE_PLL3)    || \
+                                        ((SOURCE) == RCC_USART10CLKSOURCE_CSI)     || \
+                                        ((SOURCE) == RCC_USART10CLKSOURCE_LSE)     || \
+                                        ((SOURCE) == RCC_USART10CLKSOURCE_HSI))
+#endif
+
+#define IS_RCC_LPUART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPUART1CLKSOURCE_D3PCLK1) || \
+                                         ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL2)    || \
+                                         ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL3)    || \
+                                         ((SOURCE) == RCC_LPUART1CLKSOURCE_CSI)     || \
+                                         ((SOURCE) == RCC_LPUART1CLKSOURCE_LSE)     || \
+                                         ((SOURCE) == RCC_LPUART1CLKSOURCE_HSI))
+
+#define IS_RCC_I2C123CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C123CLKSOURCE_PLL3)   || \
+                                          ((SOURCE) == RCC_I2C123CLKSOURCE_HSI)    || \
+                                          ((SOURCE) == RCC_I2C123CLKSOURCE_D2PCLK1)|| \
+                                          ((SOURCE) == RCC_I2C123CLKSOURCE_CSI))
+
+#define IS_RCC_I2C1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C1CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_I2C1CLKSOURCE_HSI)    || \
+                                        ((SOURCE) == RCC_I2C1CLKSOURCE_D2PCLK1)|| \
+                                        ((SOURCE) == RCC_I2C1CLKSOURCE_CSI))
+
+#define IS_RCC_I2C2CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C2CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_I2C2CLKSOURCE_HSI)    || \
+                                        ((SOURCE) == RCC_I2C2CLKSOURCE_D2PCLK1)|| \
+                                        ((SOURCE) == RCC_I2C2CLKSOURCE_CSI))
+
+#define IS_RCC_I2C3CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C3CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_I2C3CLKSOURCE_HSI)    || \
+                                        ((SOURCE) == RCC_I2C3CLKSOURCE_D2PCLK1)|| \
+                                        ((SOURCE) == RCC_I2C3CLKSOURCE_CSI))
+
+#define IS_RCC_I2C4CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C4CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_I2C4CLKSOURCE_HSI)    || \
+                                        ((SOURCE) == RCC_I2C4CLKSOURCE_D3PCLK1)|| \
+                                        ((SOURCE) == RCC_I2C3CLKSOURCE_CSI))
+
+#define IS_RCC_RNGCLKSOURCE(SOURCE)    (((SOURCE) == RCC_RNGCLKSOURCE_HSI48)|| \
+                                        ((SOURCE) == RCC_RNGCLKSOURCE_PLL)  || \
+                                        ((SOURCE) == RCC_RNGCLKSOURCE_LSE)  || \
+                                        ((SOURCE) == RCC_RNGCLKSOURCE_LSI))
+
+#if defined(HRTIM1)
+#define IS_RCC_HRTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_HRTIM1CLK_TIMCLK) || \
+                                        ((SOURCE) == RCC_HRTIM1CLK_CPUCLK))
+#endif
+
+#define IS_RCC_USBCLKSOURCE(SOURCE)    (((SOURCE) == RCC_USBCLKSOURCE_PLL)  || \
+                                        ((SOURCE) == RCC_USBCLKSOURCE_PLL3) || \
+                                        ((SOURCE) == RCC_USBCLKSOURCE_HSI48))
+
+#define IS_RCC_SAI1CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SAI1CLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))
+
+#if defined(SAI3)
+#define IS_RCC_SAI23CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SAI23CLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SAI23CLKSOURCE_PIN))
+
+#define IS_RCC_SAI2CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SAI2CLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN))
+
+
+#define IS_RCC_SAI3CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SAI3CLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SAI3CLKSOURCE_PIN))
+#endif
+
+#if defined(RCC_CDCCIP1R_SAI2ASEL)
+#define IS_RCC_SAI2ACLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SAI2ACLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PIN) || \
+                ((__SOURCE__) == RCC_SAI2ACLKSOURCE_SPDIF))
+#endif
+
+#if defined(RCC_CDCCIP1R_SAI2BSEL)
+#define IS_RCC_SAI2BCLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SAI2BCLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PIN) || \
+                ((__SOURCE__) == RCC_SAI2BCLKSOURCE_SPDIF))
+#endif
+
+#define IS_RCC_SPI123CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SPI123CLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SPI123CLKSOURCE_PIN))
+
+#define IS_RCC_SPI1CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SPI1CLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SPI1CLKSOURCE_PIN))
+
+#define IS_RCC_SPI2CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SPI2CLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SPI2CLKSOURCE_PIN))
+
+#define IS_RCC_SPI3CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SPI3CLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SPI3CLKSOURCE_PIN))
+
+#define IS_RCC_SPI45CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SPI45CLKSOURCE_D2PCLK1)  || \
+                ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL2)     || \
+                ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL3)     || \
+                ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSI)      || \
+                ((__SOURCE__) == RCC_SPI45CLKSOURCE_CSI)      || \
+                ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSE))
+
+#define IS_RCC_SPI4CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SPI4CLKSOURCE_D2PCLK1)  || \
+                ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL2)     || \
+                ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL3)     || \
+                ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSI)      || \
+                ((__SOURCE__) == RCC_SPI4CLKSOURCE_CSI)      || \
+                ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSE))
+
+#define IS_RCC_SPI5CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SPI5CLKSOURCE_D2PCLK1)|| \
+                ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL2)   || \
+                ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL3)   || \
+                ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSI)    || \
+                ((__SOURCE__) == RCC_SPI5CLKSOURCE_CSI)    || \
+                ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSE))
+
+#if defined(RCC_D3CCIPR_SPI6SEL)
+#define IS_RCC_SPI6CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) || \
+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2)    || \
+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3)    || \
+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI)     || \
+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI)     || \
+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE))
+#else
+#define IS_RCC_SPI6CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) || \
+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2)    || \
+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3)    || \
+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI)     || \
+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI)     || \
+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE)     || \
+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_PIN))
+#endif /* RCC_D3CCIPR_SPI6SEL */
+
+#if defined(SAI4)
+#define IS_RCC_SAI4ACLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SAI4ACLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PIN))
+
+#define IS_RCC_SAI4BCLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SAI4BCLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PIN))
+#endif /*SAI4*/
+
+#define IS_RCC_PLL3M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))
+#define IS_RCC_PLL3N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))
+#define IS_RCC_PLL3P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
+#define IS_RCC_PLL3Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
+#define IS_RCC_PLL3R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
+
+#define IS_RCC_PLL2M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))
+#define IS_RCC_PLL2N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))
+#define IS_RCC_PLL2P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
+#define IS_RCC_PLL2Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
+#define IS_RCC_PLL2R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
+
+#define IS_RCC_PLL2RGE_VALUE(VALUE) (((VALUE) == RCC_PLL2VCIRANGE_0)  || \
+                                    ((VALUE) == RCC_PLL2VCIRANGE_1)   || \
+                                    ((VALUE) == RCC_PLL2VCIRANGE_2)   || \
+                                    ((VALUE) == RCC_PLL2VCIRANGE_3))
+
+#define IS_RCC_PLL3RGE_VALUE(VALUE) (((VALUE) == RCC_PLL3VCIRANGE_0)  || \
+                                    ((VALUE) == RCC_PLL3VCIRANGE_1)   || \
+                                    ((VALUE) == RCC_PLL3VCIRANGE_2)   || \
+                                    ((VALUE) == RCC_PLL3VCIRANGE_3))
+
+#define IS_RCC_PLL2VCO_VALUE(VALUE) (((VALUE) == RCC_PLL2VCOWIDE)  || \
+                                    ((VALUE) == RCC_PLL2VCOMEDIUM))
+
+#define IS_RCC_PLL3VCO_VALUE(VALUE) (((VALUE) == RCC_PLL3VCOWIDE)  || \
+                                    ((VALUE) == RCC_PLL3VCOMEDIUM))
+
+#define IS_RCC_PLLFRACN_VALUE(VALUE) ((VALUE) <=8191U)
+
+#define IS_RCC_LPTIM1CLK(SOURCE)       (((SOURCE) == RCC_LPTIM1CLKSOURCE_D2PCLK1)|| \
+                                        ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL2)   || \
+                                        ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)    || \
+                                        ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI)    || \
+                                        ((SOURCE) == RCC_LPTIM1CLKSOURCE_CLKP))
+
+#define IS_RCC_LPTIM2CLK(SOURCE)       (((SOURCE) == RCC_LPTIM2CLKSOURCE_D3PCLK1)|| \
+                                        ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL2)   || \
+                                        ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSE)    || \
+                                        ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSI)    || \
+                                        ((SOURCE) == RCC_LPTIM2CLKSOURCE_CLKP))
+
+#define IS_RCC_LPTIM345CLK(SOURCE)     (((SOURCE) == RCC_LPTIM345CLKSOURCE_D3PCLK1)|| \
+                                        ((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL2)   || \
+                                        ((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_LPTIM345CLKSOURCE_LSE)    || \
+                                        ((SOURCE) == RCC_LPTIM345CLKSOURCE_LSI)    || \
+                                        ((SOURCE) == RCC_LPTIM345CLKSOURCE_CLKP))
+
+#define IS_RCC_LPTIM3CLK(SOURCE)       (((SOURCE) == RCC_LPTIM3CLKSOURCE_D3PCLK1)  || \
+                                        ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL2)     || \
+                                        ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL3)     || \
+                                        ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSE)      || \
+                                        ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSI)      || \
+                                        ((SOURCE) == RCC_LPTIM3CLKSOURCE_CLKP))
+
+#if defined(LPTIM4)
+#define IS_RCC_LPTIM4CLK(SOURCE)       (((SOURCE) == RCC_LPTIM4CLKSOURCE_D3PCLK1)|| \
+                                        ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL2)   || \
+                                        ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSE)    || \
+                                        ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSI)    || \
+                                        ((SOURCE) == RCC_LPTIM4CLKSOURCE_CLKP))
+#endif /* LPTIM4*/
+
+#if defined(LPTIM5)
+#define IS_RCC_LPTIM5CLK(SOURCE)       (((SOURCE) == RCC_LPTIM5CLKSOURCE_D3PCLK1)|| \
+                                        ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL2)   || \
+                                        ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSE)    || \
+                                        ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSI)    || \
+                                        ((SOURCE) == RCC_LPTIM5CLKSOURCE_CLKP))
+#endif /*LPTIM5*/
+
+#if defined(QUADSPI)
+#define IS_RCC_QSPICLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_QSPICLKSOURCE_D1HCLK)  || \
+                ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL)     || \
+                ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL2)    || \
+                ((__SOURCE__) == RCC_QSPICLKSOURCE_CLKP))
+#endif /*QUADSPI*/
+
+#if defined(OCTOSPI1) || defined(OCTOSPI1)
+#define IS_RCC_OSPICLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_OSPICLKSOURCE_D1HCLK)  || \
+                ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL)     || \
+                ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL2)    || \
+                ((__SOURCE__) == RCC_OSPICLKSOURCE_CLKP))
+#endif /*OCTOSPI1 || OCTOSPI1*/
+
+#if defined(DSI)
+#define IS_RCC_DSICLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_DSICLKSOURCE_PHY)  || \
+                ((__SOURCE__) == RCC_DSICLKSOURCE_PLL2))
+#endif /*DSI*/
+
+#define IS_RCC_FMCCLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_FMCCLKSOURCE_D1HCLK)  || \
+                ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL)     || \
+                ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL2)    || \
+                ((__SOURCE__) == RCC_FMCCLKSOURCE_CLKP))
+
+#if defined(FDCAN1) || defined(FDCAN2)
+#define IS_RCC_FDCANCLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE)  || \
+                ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL2))
+#endif /*FDCAN1 || FDCAN2*/
+
+#define IS_RCC_SDMMC(__SOURCE__)   \
+                (((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL2))
+
+#define IS_RCC_ADCCLKSOURCE(SOURCE)    (((SOURCE) == RCC_ADCCLKSOURCE_PLL2) || \
+                                        ((SOURCE) == RCC_ADCCLKSOURCE_PLL3) || \
+                                        ((SOURCE) == RCC_ADCCLKSOURCE_CLKP))
+
+#define IS_RCC_SWPMI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SWPMI1CLKSOURCE_D2PCLK1) || \
+                                        ((SOURCE) == RCC_SWPMI1CLKSOURCE_HSI))
+
+#define IS_RCC_DFSDM1CLKSOURCE(SOURCE)  (((SOURCE) == RCC_DFSDM1CLKSOURCE_D2PCLK1) || \
+                                         ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYS))
+
+#if defined(DFSDM2_BASE)
+#define IS_RCC_DFSDM2CLKSOURCE(SOURCE)  (((SOURCE) == RCC_DFSDM2CLKSOURCE_SRDPCLK1) || \
+                                        ((SOURCE) == RCC_DFSDM2CLKSOURCE_SYS))
+#endif /*DFSDM2*/
+
+#define IS_RCC_SPDIFRXCLKSOURCE(SOURCE)(((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL)  || \
+                                        ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL2) || \
+                                        ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL3) || \
+                                        ((SOURCE) == RCC_SPDIFRXCLKSOURCE_HSI))
+
+#define IS_RCC_CECCLKSOURCE(SOURCE)  (((SOURCE) == RCC_CECCLKSOURCE_LSE) || \
+                                      ((SOURCE) == RCC_CECCLKSOURCE_LSI) || \
+                                      ((SOURCE) == RCC_CECCLKSOURCE_CSI))
+
+#define IS_RCC_CLKPSOURCE(SOURCE)   (((SOURCE) == RCC_CLKPSOURCE_HSI)  || \
+                                      ((SOURCE) == RCC_CLKPSOURCE_CSI) || \
+                                      ((SOURCE) == RCC_CLKPSOURCE_HSE))
+#define IS_RCC_TIMPRES(VALUE)  \
+               (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \
+                ((VALUE) == RCC_TIMPRES_ACTIVATED))
+
+#if defined(DUAL_CORE)
+#define IS_RCC_BOOT_CORE(CORE)   (((CORE) == RCC_BOOT_C1)  || \
+                                  ((CORE) == RCC_BOOT_C2))
+#endif /*DUAL_CORE*/
+
+#if defined(DUAL_CORE)
+#define IS_RCC_SCOPE_WWDG(WWDG)   (((WWDG) == RCC_WWDG1)  || \
+                                  ((WWDG) == RCC_WWDG2))
+#else
+#define IS_RCC_SCOPE_WWDG(WWDG)   ((WWDG) == RCC_WWDG1)
+
+#endif /*DUAL_CORE*/
+
+#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB2) || \
+                                            ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE)  || \
+                                            ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB1) || \
+                                            ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_PIN))
+
+#define IS_RCC_CRS_SYNC_DIV(__DIV__)       (((__DIV__) == RCC_CRS_SYNC_DIV1)  || ((__DIV__) == RCC_CRS_SYNC_DIV2)  || \
+                                            ((__DIV__) == RCC_CRS_SYNC_DIV4)  || ((__DIV__) == RCC_CRS_SYNC_DIV8)  || \
+                                            ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
+                                            ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))
+
+#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
+                                                ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
+
+#define IS_RCC_CRS_RELOADVALUE(__VALUE__)  (((__VALUE__) <= 0xFFFFU))
+
+#define IS_RCC_CRS_ERRORLIMIT(__VALUE__)   (((__VALUE__) <= 0xFFU))
+
+#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))
+
+#define IS_RCC_CRS_FREQERRORDIR(__DIR__)   (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
+                                            ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_RCC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h
new file mode 100644
index 00000000..37a7ada8
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h
@@ -0,0 +1,2285 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_tim.h
+  * @author  MCD Application Team
+  * @brief   Header file of TIM HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_TIM_H
+#define STM32H7xx_HAL_TIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup TIM
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TIM_Exported_Types TIM Exported Types
+  * @{
+  */
+
+/**
+  * @brief  TIM Time base Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
+                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+  uint32_t CounterMode;       /*!< Specifies the counter mode.
+                                   This parameter can be a value of @ref TIM_Counter_Mode */
+
+  uint32_t Period;            /*!< Specifies the period value to be loaded into the active
+                                   Auto-Reload Register at the next update event.
+                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.  */
+
+  uint32_t ClockDivision;     /*!< Specifies the clock division.
+                                   This parameter can be a value of @ref TIM_ClockDivision */
+
+  uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
+                                    reaches zero, an update event is generated and counting restarts
+                                    from the RCR value (N).
+                                    This means in PWM mode that (N+1) corresponds to:
+                                        - the number of PWM periods in edge-aligned mode
+                                        - the number of half PWM period in center-aligned mode
+                                     GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+                                     Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+  uint32_t AutoReloadPreload;  /*!< Specifies the auto-reload preload.
+                                   This parameter can be a value of @ref TIM_AutoReloadPreload */
+} TIM_Base_InitTypeDef;
+
+/**
+  * @brief  TIM Output Compare Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t OCMode;        /*!< Specifies the TIM mode.
+                               This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+  uint32_t OCPolarity;    /*!< Specifies the output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t OCFastMode;    /*!< Specifies the Fast mode state.
+                               This parameter can be a value of @ref TIM_Output_Fast_State
+                               @note This parameter is valid only in PWM1 and PWM2 mode. */
+
+
+  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+                               @note This parameter is valid only for timer instances supporting break feature. */
+} TIM_OC_InitTypeDef;
+
+/**
+  * @brief  TIM One Pulse Mode Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t OCMode;        /*!< Specifies the TIM mode.
+                               This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+  uint32_t OCPolarity;    /*!< Specifies the output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint32_t ICSelection;   /*!< Specifies the input.
+                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t ICFilter;      /*!< Specifies the input capture filter.
+                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_OnePulse_InitTypeDef;
+
+/**
+  * @brief  TIM Input Capture Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t  ICPolarity;  /*!< Specifies the active edge of the input signal.
+                              This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint32_t ICSelection;  /*!< Specifies the input.
+                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
+                              This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t ICFilter;     /*!< Specifies the input capture filter.
+                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_IC_InitTypeDef;
+
+/**
+  * @brief  TIM Encoder Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t EncoderMode;   /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Encoder_Mode */
+
+  uint32_t IC1Polarity;   /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
+
+  uint32_t IC1Selection;  /*!< Specifies the input.
+                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t IC1Prescaler;  /*!< Specifies the Input Capture Prescaler.
+                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t IC1Filter;     /*!< Specifies the input capture filter.
+                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+  uint32_t IC2Polarity;   /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
+
+  uint32_t IC2Selection;  /*!< Specifies the input.
+                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t IC2Prescaler;  /*!< Specifies the Input Capture Prescaler.
+                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t IC2Filter;     /*!< Specifies the input capture filter.
+                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_Encoder_InitTypeDef;
+
+/**
+  * @brief  Clock Configuration Handle Structure definition
+  */
+typedef struct
+{
+  uint32_t ClockSource;     /*!< TIM clock sources
+                                 This parameter can be a value of @ref TIM_Clock_Source */
+  uint32_t ClockPolarity;   /*!< TIM clock polarity
+                                 This parameter can be a value of @ref TIM_Clock_Polarity */
+  uint32_t ClockPrescaler;  /*!< TIM clock prescaler
+                                 This parameter can be a value of @ref TIM_Clock_Prescaler */
+  uint32_t ClockFilter;     /*!< TIM clock filter
+                                 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_ClockConfigTypeDef;
+
+/**
+  * @brief  TIM Clear Input Configuration Handle Structure definition
+  */
+typedef struct
+{
+  uint32_t ClearInputState;      /*!< TIM clear Input state
+                                      This parameter can be ENABLE or DISABLE */
+  uint32_t ClearInputSource;     /*!< TIM clear Input sources
+                                      This parameter can be a value of @ref TIM_ClearInput_Source */
+  uint32_t ClearInputPolarity;   /*!< TIM Clear Input polarity
+                                      This parameter can be a value of @ref TIM_ClearInput_Polarity */
+  uint32_t ClearInputPrescaler;  /*!< TIM Clear Input prescaler
+                                      This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */
+  uint32_t ClearInputFilter;     /*!< TIM Clear Input filter
+                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_ClearInputConfigTypeDef;
+
+/**
+  * @brief  TIM Master configuration Structure definition
+  * @note   Advanced timers provide TRGO2 internal line which is redirected
+  *         to the ADC
+  */
+typedef struct
+{
+  uint32_t  MasterOutputTrigger;   /*!< Trigger output (TRGO) selection
+                                        This parameter can be a value of @ref TIM_Master_Mode_Selection */
+  uint32_t  MasterOutputTrigger2;  /*!< Trigger output2 (TRGO2) selection
+                                        This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */
+  uint32_t  MasterSlaveMode;       /*!< Master/slave mode selection
+                                        This parameter can be a value of @ref TIM_Master_Slave_Mode
+                                        @note When the Master/slave mode is enabled, the effect of
+                                        an event on the trigger input (TRGI) is delayed to allow a
+                                        perfect synchronization between the current timer and its
+                                        slaves (through TRGO). It is not mandatory in case of timer
+                                        synchronization mode. */
+} TIM_MasterConfigTypeDef;
+
+/**
+  * @brief  TIM Slave configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t  SlaveMode;         /*!< Slave mode selection
+                                    This parameter can be a value of @ref TIM_Slave_Mode */
+  uint32_t  InputTrigger;      /*!< Input Trigger source
+                                    This parameter can be a value of @ref TIM_Trigger_Selection */
+  uint32_t  TriggerPolarity;   /*!< Input Trigger polarity
+                                    This parameter can be a value of @ref TIM_Trigger_Polarity */
+  uint32_t  TriggerPrescaler;  /*!< Input trigger prescaler
+                                    This parameter can be a value of @ref TIM_Trigger_Prescaler */
+  uint32_t  TriggerFilter;     /*!< Input trigger filter
+                                    This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF  */
+
+} TIM_SlaveConfigTypeDef;
+
+/**
+  * @brief  TIM Break input(s) and Dead time configuration Structure definition
+  * @note   2 break inputs can be configured (BKIN and BKIN2) with configurable
+  *        filter and polarity.
+  */
+typedef struct
+{
+  uint32_t OffStateRunMode;      /*!< TIM off state in run mode
+                                      This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
+  uint32_t OffStateIDLEMode;     /*!< TIM off state in IDLE mode
+                                      This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
+  uint32_t LockLevel;            /*!< TIM Lock level
+                                      This parameter can be a value of @ref TIM_Lock_level */
+  uint32_t DeadTime;             /*!< TIM dead Time
+                                      This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+  uint32_t BreakState;           /*!< TIM Break State
+                                      This parameter can be a value of @ref TIM_Break_Input_enable_disable */
+  uint32_t BreakPolarity;        /*!< TIM Break input polarity
+                                      This parameter can be a value of @ref TIM_Break_Polarity */
+  uint32_t BreakFilter;          /*!< Specifies the break input filter.
+                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+  uint32_t Break2State;          /*!< TIM Break2 State
+                                      This parameter can be a value of @ref TIM_Break2_Input_enable_disable */
+  uint32_t Break2Polarity;       /*!< TIM Break2 input polarity
+                                      This parameter can be a value of @ref TIM_Break2_Polarity */
+  uint32_t Break2Filter;         /*!< TIM break2 input filter.
+                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+  uint32_t AutomaticOutput;      /*!< TIM Automatic Output Enable state
+                                      This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+} TIM_BreakDeadTimeConfigTypeDef;
+
+/**
+  * @brief  HAL State structures definition
+  */
+typedef enum
+{
+  HAL_TIM_STATE_RESET             = 0x00U,    /*!< Peripheral not yet initialized or disabled  */
+  HAL_TIM_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */
+  HAL_TIM_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */
+  HAL_TIM_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */
+  HAL_TIM_STATE_ERROR             = 0x04U     /*!< Reception process is ongoing                */
+} HAL_TIM_StateTypeDef;
+
+/**
+  * @brief  HAL Active channel structures definition
+  */
+typedef enum
+{
+  HAL_TIM_ACTIVE_CHANNEL_1        = 0x01U,    /*!< The active channel is 1     */
+  HAL_TIM_ACTIVE_CHANNEL_2        = 0x02U,    /*!< The active channel is 2     */
+  HAL_TIM_ACTIVE_CHANNEL_3        = 0x04U,    /*!< The active channel is 3     */
+  HAL_TIM_ACTIVE_CHANNEL_4        = 0x08U,    /*!< The active channel is 4     */
+  HAL_TIM_ACTIVE_CHANNEL_5        = 0x10U,    /*!< The active channel is 5     */
+  HAL_TIM_ACTIVE_CHANNEL_6        = 0x20U,    /*!< The active channel is 6     */
+  HAL_TIM_ACTIVE_CHANNEL_CLEARED  = 0x00U     /*!< All active channels cleared */
+} HAL_TIM_ActiveChannel;
+
+/**
+  * @brief  TIM Time Base Handle Structure definition
+  */
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+typedef struct __TIM_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+{
+  TIM_TypeDef                 *Instance;     /*!< Register base address             */
+  TIM_Base_InitTypeDef        Init;          /*!< TIM Time Base required parameters */
+  HAL_TIM_ActiveChannel       Channel;       /*!< Active channel                    */
+  DMA_HandleTypeDef           *hdma[7];      /*!< DMA Handlers array
+                                                  This array is accessed by a @ref DMA_Handle_index */
+  HAL_LockTypeDef             Lock;          /*!< Locking object                    */
+  __IO HAL_TIM_StateTypeDef   State;         /*!< TIM operation state               */
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM Base Msp Init Callback                              */
+  void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);            /*!< TIM Base Msp DeInit Callback                            */
+  void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM IC Msp Init Callback                                */
+  void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM IC Msp DeInit Callback                              */
+  void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM OC Msp Init Callback                                */
+  void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM OC Msp DeInit Callback                              */
+  void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM PWM Msp Init Callback                               */
+  void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM PWM Msp DeInit Callback                             */
+  void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim);          /*!< TIM One Pulse Msp Init Callback                         */
+  void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM One Pulse Msp DeInit Callback                       */
+  void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Encoder Msp Init Callback                           */
+  void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM Encoder Msp DeInit Callback                         */
+  void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Hall Sensor Msp Init Callback                       */
+  void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);      /*!< TIM Hall Sensor Msp DeInit Callback                     */
+  void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM Period Elapsed Callback                             */
+  void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);     /*!< TIM Period Elapsed half complete Callback               */
+  void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim);                   /*!< TIM Trigger Callback                                    */
+  void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Trigger half complete Callback                      */
+  void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM Input Capture Callback                              */
+  void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Input Capture half complete Callback                */
+  void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Output Compare Delay Elapsed Callback               */
+  void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM PWM Pulse Finished Callback                         */
+  void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback           */
+  void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Error Callback                                      */
+  void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM Commutation Callback                                */
+  void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);       /*!< TIM Commutation half complete Callback                  */
+  void (* BreakCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Break Callback                                      */
+  void (* Break2Callback)(struct __TIM_HandleTypeDef *htim);                    /*!< TIM Break2 Callback                                     */
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+} TIM_HandleTypeDef;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL TIM Callback ID enumeration definition
+  */
+typedef enum
+{
+   HAL_TIM_BASE_MSPINIT_CB_ID            = 0x00U    /*!< TIM Base MspInit Callback ID                              */
+  ,HAL_TIM_BASE_MSPDEINIT_CB_ID          = 0x01U    /*!< TIM Base MspDeInit Callback ID                            */
+  ,HAL_TIM_IC_MSPINIT_CB_ID              = 0x02U    /*!< TIM IC MspInit Callback ID                                */
+  ,HAL_TIM_IC_MSPDEINIT_CB_ID            = 0x03U    /*!< TIM IC MspDeInit Callback ID                              */
+  ,HAL_TIM_OC_MSPINIT_CB_ID              = 0x04U    /*!< TIM OC MspInit Callback ID                                */
+  ,HAL_TIM_OC_MSPDEINIT_CB_ID            = 0x05U    /*!< TIM OC MspDeInit Callback ID                              */
+  ,HAL_TIM_PWM_MSPINIT_CB_ID             = 0x06U    /*!< TIM PWM MspInit Callback ID                               */
+  ,HAL_TIM_PWM_MSPDEINIT_CB_ID           = 0x07U    /*!< TIM PWM MspDeInit Callback ID                             */
+  ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID       = 0x08U    /*!< TIM One Pulse MspInit Callback ID                         */
+  ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID     = 0x09U    /*!< TIM One Pulse MspDeInit Callback ID                       */
+  ,HAL_TIM_ENCODER_MSPINIT_CB_ID         = 0x0AU    /*!< TIM Encoder MspInit Callback ID                           */
+  ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID       = 0x0BU    /*!< TIM Encoder MspDeInit Callback ID                         */
+  ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID     = 0x0CU    /*!< TIM Hall Sensor MspDeInit Callback ID                     */
+  ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID   = 0x0DU    /*!< TIM Hall Sensor MspDeInit Callback ID                     */
+  ,HAL_TIM_PERIOD_ELAPSED_CB_ID          = 0x0EU    /*!< TIM Period Elapsed Callback ID                             */
+  ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID     = 0x0FU    /*!< TIM Period Elapsed half complete Callback ID               */
+  ,HAL_TIM_TRIGGER_CB_ID                 = 0x10U    /*!< TIM Trigger Callback ID                                    */
+  ,HAL_TIM_TRIGGER_HALF_CB_ID            = 0x11U    /*!< TIM Trigger half complete Callback ID                      */
+
+  ,HAL_TIM_IC_CAPTURE_CB_ID              = 0x12U    /*!< TIM Input Capture Callback ID                              */
+  ,HAL_TIM_IC_CAPTURE_HALF_CB_ID         = 0x13U    /*!< TIM Input Capture half complete Callback ID                */
+  ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID        = 0x14U    /*!< TIM Output Compare Delay Elapsed Callback ID               */
+  ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID      = 0x15U    /*!< TIM PWM Pulse Finished Callback ID           */
+  ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U    /*!< TIM PWM Pulse Finished half complete Callback ID           */
+  ,HAL_TIM_ERROR_CB_ID                   = 0x17U    /*!< TIM Error Callback ID                                      */
+  ,HAL_TIM_COMMUTATION_CB_ID             = 0x18U    /*!< TIM Commutation Callback ID                                */
+  ,HAL_TIM_COMMUTATION_HALF_CB_ID        = 0x19U    /*!< TIM Commutation half complete Callback ID                  */
+  ,HAL_TIM_BREAK_CB_ID                   = 0x1AU    /*!< TIM Break Callback ID                                      */
+  ,HAL_TIM_BREAK2_CB_ID                  = 0x1BU    /*!< TIM Break2 Callback ID                                     */
+} HAL_TIM_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL TIM Callback pointer definition
+  */
+typedef  void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);  /*!< pointer to the TIM callback function */
+
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+/* End of exported types -----------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIM_Exported_Constants TIM Exported Constants
+  * @{
+  */
+
+/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
+  * @{
+  */
+#define TIM_CLEARINPUTSOURCE_NONE           0x00000000U   /*!< OCREF_CLR is disabled */
+#define TIM_CLEARINPUTSOURCE_ETR            0x00000001U   /*!< OCREF_CLR is connected to ETRF input */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
+  * @{
+  */
+#define TIM_DMABASE_CR1                    0x00000000U
+#define TIM_DMABASE_CR2                    0x00000001U
+#define TIM_DMABASE_SMCR                   0x00000002U
+#define TIM_DMABASE_DIER                   0x00000003U
+#define TIM_DMABASE_SR                     0x00000004U
+#define TIM_DMABASE_EGR                    0x00000005U
+#define TIM_DMABASE_CCMR1                  0x00000006U
+#define TIM_DMABASE_CCMR2                  0x00000007U
+#define TIM_DMABASE_CCER                   0x00000008U
+#define TIM_DMABASE_CNT                    0x00000009U
+#define TIM_DMABASE_PSC                    0x0000000AU
+#define TIM_DMABASE_ARR                    0x0000000BU
+#define TIM_DMABASE_RCR                    0x0000000CU
+#define TIM_DMABASE_CCR1                   0x0000000DU
+#define TIM_DMABASE_CCR2                   0x0000000EU
+#define TIM_DMABASE_CCR3                   0x0000000FU
+#define TIM_DMABASE_CCR4                   0x00000010U
+#define TIM_DMABASE_BDTR                   0x00000011U
+#define TIM_DMABASE_DCR                    0x00000012U
+#define TIM_DMABASE_DMAR                   0x00000013U
+#define TIM_DMABASE_CCMR3                  0x00000015U
+#define TIM_DMABASE_CCR5                   0x00000016U
+#define TIM_DMABASE_CCR6                   0x00000017U
+#if   defined(TIM_BREAK_INPUT_SUPPORT)
+#define TIM_DMABASE_AF1                    0x00000018U
+#define TIM_DMABASE_AF2                    0x00000019U
+#endif /* TIM_BREAK_INPUT_SUPPORT */
+#define TIM_DMABASE_TISEL                  0x0000001AU
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Event_Source TIM Event Source
+  * @{
+  */
+#define TIM_EVENTSOURCE_UPDATE              TIM_EGR_UG     /*!< Reinitialize the counter and generates an update of the registers */
+#define TIM_EVENTSOURCE_CC1                 TIM_EGR_CC1G   /*!< A capture/compare event is generated on channel 1 */
+#define TIM_EVENTSOURCE_CC2                 TIM_EGR_CC2G   /*!< A capture/compare event is generated on channel 2 */
+#define TIM_EVENTSOURCE_CC3                 TIM_EGR_CC3G   /*!< A capture/compare event is generated on channel 3 */
+#define TIM_EVENTSOURCE_CC4                 TIM_EGR_CC4G   /*!< A capture/compare event is generated on channel 4 */
+#define TIM_EVENTSOURCE_COM                 TIM_EGR_COMG   /*!< A commutation event is generated */
+#define TIM_EVENTSOURCE_TRIGGER             TIM_EGR_TG     /*!< A trigger event is generated */
+#define TIM_EVENTSOURCE_BREAK               TIM_EGR_BG     /*!< A break event is generated */
+#define TIM_EVENTSOURCE_BREAK2              TIM_EGR_B2G    /*!< A break 2 event is generated */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
+  * @{
+  */
+#define  TIM_INPUTCHANNELPOLARITY_RISING      0x00000000U                       /*!< Polarity for TIx source */
+#define  TIM_INPUTCHANNELPOLARITY_FALLING     TIM_CCER_CC1P                     /*!< Polarity for TIx source */
+#define  TIM_INPUTCHANNELPOLARITY_BOTHEDGE    (TIM_CCER_CC1P | TIM_CCER_CC1NP)  /*!< Polarity for TIx source */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
+  * @{
+  */
+#define TIM_ETRPOLARITY_INVERTED              TIM_SMCR_ETP                      /*!< Polarity for ETR source */
+#define TIM_ETRPOLARITY_NONINVERTED           0x00000000U                       /*!< Polarity for ETR source */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
+  * @{
+  */
+#define TIM_ETRPRESCALER_DIV1                 0x00000000U                       /*!< No prescaler is used */
+#define TIM_ETRPRESCALER_DIV2                 TIM_SMCR_ETPS_0                   /*!< ETR input source is divided by 2 */
+#define TIM_ETRPRESCALER_DIV4                 TIM_SMCR_ETPS_1                   /*!< ETR input source is divided by 4 */
+#define TIM_ETRPRESCALER_DIV8                 TIM_SMCR_ETPS                     /*!< ETR input source is divided by 8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Counter_Mode TIM Counter Mode
+  * @{
+  */
+#define TIM_COUNTERMODE_UP                 0x00000000U                          /*!< Counter used as up-counter   */
+#define TIM_COUNTERMODE_DOWN               TIM_CR1_DIR                          /*!< Counter used as down-counter */
+#define TIM_COUNTERMODE_CENTERALIGNED1     TIM_CR1_CMS_0                        /*!< Center-aligned mode 1        */
+#define TIM_COUNTERMODE_CENTERALIGNED2     TIM_CR1_CMS_1                        /*!< Center-aligned mode 2        */
+#define TIM_COUNTERMODE_CENTERALIGNED3     TIM_CR1_CMS                          /*!< Center-aligned mode 3        */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap
+  * @{
+  */
+#define TIM_UIFREMAP_DISABLE               0x00000000U                          /*!< Update interrupt flag remap disabled */
+#define TIM_UIFREMAP_ENABLE                TIM_CR1_UIFREMAP                     /*!< Update interrupt flag remap enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ClockDivision TIM Clock Division
+  * @{
+  */
+#define TIM_CLOCKDIVISION_DIV1             0x00000000U                          /*!< Clock division: tDTS=tCK_INT   */
+#define TIM_CLOCKDIVISION_DIV2             TIM_CR1_CKD_0                        /*!< Clock division: tDTS=2*tCK_INT */
+#define TIM_CLOCKDIVISION_DIV4             TIM_CR1_CKD_1                        /*!< Clock division: tDTS=4*tCK_INT */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_State TIM Output Compare State
+  * @{
+  */
+#define TIM_OUTPUTSTATE_DISABLE            0x00000000U                          /*!< Capture/Compare 1 output disabled */
+#define TIM_OUTPUTSTATE_ENABLE             TIM_CCER_CC1E                        /*!< Capture/Compare 1 output enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
+  * @{
+  */
+#define TIM_AUTORELOAD_PRELOAD_DISABLE                0x00000000U               /*!< TIMx_ARR register is not buffered */
+#define TIM_AUTORELOAD_PRELOAD_ENABLE                 TIM_CR1_ARPE              /*!< TIMx_ARR register is buffered */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Fast_State TIM Output Fast State
+  * @{
+  */
+#define TIM_OCFAST_DISABLE                 0x00000000U                          /*!< Output Compare fast disable */
+#define TIM_OCFAST_ENABLE                  TIM_CCMR1_OC1FE                      /*!< Output Compare fast enable  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
+  * @{
+  */
+#define TIM_OUTPUTNSTATE_DISABLE           0x00000000U                          /*!< OCxN is disabled  */
+#define TIM_OUTPUTNSTATE_ENABLE            TIM_CCER_CC1NE                       /*!< OCxN is enabled   */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
+  * @{
+  */
+#define TIM_OCPOLARITY_HIGH                0x00000000U                          /*!< Capture/Compare output polarity  */
+#define TIM_OCPOLARITY_LOW                 TIM_CCER_CC1P                        /*!< Capture/Compare output polarity  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
+  * @{
+  */
+#define TIM_OCNPOLARITY_HIGH               0x00000000U                          /*!< Capture/Compare complementary output polarity */
+#define TIM_OCNPOLARITY_LOW                TIM_CCER_CC1NP                       /*!< Capture/Compare complementary output polarity */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
+  * @{
+  */
+#define TIM_OCIDLESTATE_SET                TIM_CR2_OIS1                         /*!< Output Idle state: OCx=1 when MOE=0 */
+#define TIM_OCIDLESTATE_RESET              0x00000000U                          /*!< Output Idle state: OCx=0 when MOE=0 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
+  * @{
+  */
+#define TIM_OCNIDLESTATE_SET               TIM_CR2_OIS1N                        /*!< Complementary output Idle state: OCxN=1 when MOE=0 */
+#define TIM_OCNIDLESTATE_RESET             0x00000000U                          /*!< Complementary output Idle state: OCxN=0 when MOE=0 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
+  * @{
+  */
+#define  TIM_ICPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING      /*!< Capture triggered by rising edge on timer input                  */
+#define  TIM_ICPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Capture triggered by falling edge on timer input                 */
+#define  TIM_ICPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE    /*!< Capture triggered by both rising and falling edges on timer input*/
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
+  * @{
+  */
+#define  TIM_ENCODERINPUTPOLARITY_RISING   TIM_INPUTCHANNELPOLARITY_RISING      /*!< Encoder input with rising edge polarity  */
+#define  TIM_ENCODERINPUTPOLARITY_FALLING  TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Encoder input with falling edge polarity */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
+  * @{
+  */
+#define TIM_ICSELECTION_DIRECTTI           TIM_CCMR1_CC1S_0                     /*!< TIM Input 1, 2, 3 or 4 is selected to be
+                                                                                     connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSELECTION_INDIRECTTI         TIM_CCMR1_CC1S_1                     /*!< TIM Input 1, 2, 3 or 4 is selected to be
+                                                                                     connected to IC2, IC1, IC4 or IC3, respectively */
+#define TIM_ICSELECTION_TRC                TIM_CCMR1_CC1S                       /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
+  * @{
+  */
+#define TIM_ICPSC_DIV1                     0x00000000U                          /*!< Capture performed each time an edge is detected on the capture input */
+#define TIM_ICPSC_DIV2                     TIM_CCMR1_IC1PSC_0                   /*!< Capture performed once every 2 events                                */
+#define TIM_ICPSC_DIV4                     TIM_CCMR1_IC1PSC_1                   /*!< Capture performed once every 4 events                                */
+#define TIM_ICPSC_DIV8                     TIM_CCMR1_IC1PSC                     /*!< Capture performed once every 8 events                                */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
+  * @{
+  */
+#define TIM_OPMODE_SINGLE                  TIM_CR1_OPM                          /*!< Counter stops counting at the next update event */
+#define TIM_OPMODE_REPETITIVE              0x00000000U                          /*!< Counter is not stopped at update event          */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
+  * @{
+  */
+#define TIM_ENCODERMODE_TI1                      TIM_SMCR_SMS_0                                                      /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level  */
+#define TIM_ENCODERMODE_TI2                      TIM_SMCR_SMS_1                                                      /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */
+#define TIM_ENCODERMODE_TI12                     (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                                   /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
+  * @{
+  */
+#define TIM_IT_UPDATE                      TIM_DIER_UIE                         /*!< Update interrupt            */
+#define TIM_IT_CC1                         TIM_DIER_CC1IE                       /*!< Capture/Compare 1 interrupt */
+#define TIM_IT_CC2                         TIM_DIER_CC2IE                       /*!< Capture/Compare 2 interrupt */
+#define TIM_IT_CC3                         TIM_DIER_CC3IE                       /*!< Capture/Compare 3 interrupt */
+#define TIM_IT_CC4                         TIM_DIER_CC4IE                       /*!< Capture/Compare 4 interrupt */
+#define TIM_IT_COM                         TIM_DIER_COMIE                       /*!< Commutation interrupt       */
+#define TIM_IT_TRIGGER                     TIM_DIER_TIE                         /*!< Trigger interrupt           */
+#define TIM_IT_BREAK                       TIM_DIER_BIE                         /*!< Break interrupt             */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Commutation_Source  TIM Commutation Source
+  * @{
+  */
+#define TIM_COMMUTATION_TRGI              TIM_CR2_CCUS                          /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */
+#define TIM_COMMUTATION_SOFTWARE          0x00000000U                           /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_DMA_sources TIM DMA Sources
+  * @{
+  */
+#define TIM_DMA_UPDATE                     TIM_DIER_UDE                         /*!< DMA request is triggered by the update event */
+#define TIM_DMA_CC1                        TIM_DIER_CC1DE                       /*!< DMA request is triggered by the capture/compare macth 1 event */
+#define TIM_DMA_CC2                        TIM_DIER_CC2DE                       /*!< DMA request is triggered by the capture/compare macth 2 event event */
+#define TIM_DMA_CC3                        TIM_DIER_CC3DE                       /*!< DMA request is triggered by the capture/compare macth 3 event event */
+#define TIM_DMA_CC4                        TIM_DIER_CC4DE                       /*!< DMA request is triggered by the capture/compare macth 4 event event */
+#define TIM_DMA_COM                        TIM_DIER_COMDE                       /*!< DMA request is triggered by the commutation event */
+#define TIM_DMA_TRIGGER                    TIM_DIER_TDE                         /*!< DMA request is triggered by the trigger event */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Flag_definition TIM Flag Definition
+  * @{
+  */
+#define TIM_FLAG_UPDATE                    TIM_SR_UIF                           /*!< Update interrupt flag         */
+#define TIM_FLAG_CC1                       TIM_SR_CC1IF                         /*!< Capture/Compare 1 interrupt flag */
+#define TIM_FLAG_CC2                       TIM_SR_CC2IF                         /*!< Capture/Compare 2 interrupt flag */
+#define TIM_FLAG_CC3                       TIM_SR_CC3IF                         /*!< Capture/Compare 3 interrupt flag */
+#define TIM_FLAG_CC4                       TIM_SR_CC4IF                         /*!< Capture/Compare 4 interrupt flag */
+#define TIM_FLAG_CC5                       TIM_SR_CC5IF                         /*!< Capture/Compare 5 interrupt flag */
+#define TIM_FLAG_CC6                       TIM_SR_CC6IF                         /*!< Capture/Compare 6 interrupt flag */
+#define TIM_FLAG_COM                       TIM_SR_COMIF                         /*!< Commutation interrupt flag    */
+#define TIM_FLAG_TRIGGER                   TIM_SR_TIF                           /*!< Trigger interrupt flag        */
+#define TIM_FLAG_BREAK                     TIM_SR_BIF                           /*!< Break interrupt flag          */
+#define TIM_FLAG_BREAK2                    TIM_SR_B2IF                          /*!< Break 2 interrupt flag        */
+#define TIM_FLAG_SYSTEM_BREAK              TIM_SR_SBIF                          /*!< System Break interrupt flag   */
+#define TIM_FLAG_CC1OF                     TIM_SR_CC1OF                         /*!< Capture 1 overcapture flag    */
+#define TIM_FLAG_CC2OF                     TIM_SR_CC2OF                         /*!< Capture 2 overcapture flag    */
+#define TIM_FLAG_CC3OF                     TIM_SR_CC3OF                         /*!< Capture 3 overcapture flag    */
+#define TIM_FLAG_CC4OF                     TIM_SR_CC4OF                         /*!< Capture 4 overcapture flag    */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Channel TIM Channel
+  * @{
+  */
+#define TIM_CHANNEL_1                      0x00000000U                          /*!< Capture/compare channel 1 identifier      */
+#define TIM_CHANNEL_2                      0x00000004U                          /*!< Capture/compare channel 2 identifier      */
+#define TIM_CHANNEL_3                      0x00000008U                          /*!< Capture/compare channel 3 identifier      */
+#define TIM_CHANNEL_4                      0x0000000CU                          /*!< Capture/compare channel 4 identifier      */
+#define TIM_CHANNEL_5                      0x00000010U                          /*!< Compare channel 5 identifier              */
+#define TIM_CHANNEL_6                      0x00000014U                          /*!< Compare channel 6 identifier              */
+#define TIM_CHANNEL_ALL                    0x0000003CU                          /*!< Global Capture/compare channel identifier  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Clock_Source TIM Clock Source
+  * @{
+  */
+#define TIM_CLOCKSOURCE_ETRMODE2    TIM_SMCR_ETPS_1      /*!< External clock source mode 2                          */
+#define TIM_CLOCKSOURCE_INTERNAL    TIM_SMCR_ETPS_0      /*!< Internal clock source                                 */
+#define TIM_CLOCKSOURCE_ITR0        TIM_TS_ITR0          /*!< External clock source mode 1 (ITR0)                   */
+#define TIM_CLOCKSOURCE_ITR1        TIM_TS_ITR1          /*!< External clock source mode 1 (ITR1)                   */
+#define TIM_CLOCKSOURCE_ITR2        TIM_TS_ITR2          /*!< External clock source mode 1 (ITR2)                   */
+#define TIM_CLOCKSOURCE_ITR3        TIM_TS_ITR3          /*!< External clock source mode 1 (ITR3)                   */
+#define TIM_CLOCKSOURCE_TI1ED       TIM_TS_TI1F_ED       /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
+#define TIM_CLOCKSOURCE_TI1         TIM_TS_TI1FP1        /*!< External clock source mode 1 (TTI1FP1)                */
+#define TIM_CLOCKSOURCE_TI2         TIM_TS_TI2FP2        /*!< External clock source mode 1 (TTI2FP2)                */
+#define TIM_CLOCKSOURCE_ETRMODE1    TIM_TS_ETRF          /*!< External clock source mode 1 (ETRF)                   */
+#define TIM_CLOCKSOURCE_ITR4        TIM_TS_ITR4          /*!< External clock source mode 1 (ITR4)                   */
+#define TIM_CLOCKSOURCE_ITR5        TIM_TS_ITR5          /*!< External clock source mode 1 (ITR5)                   */
+#define TIM_CLOCKSOURCE_ITR6        TIM_TS_ITR6          /*!< External clock source mode 1 (ITR6)                   */
+#define TIM_CLOCKSOURCE_ITR7        TIM_TS_ITR7          /*!< External clock source mode 1 (ITR7)                   */
+#define TIM_CLOCKSOURCE_ITR8        TIM_TS_ITR8          /*!< External clock source mode 1 (ITR8)                   */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
+  * @{
+  */
+#define TIM_CLOCKPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED           /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED        /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING    /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING   /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE  /*!< Polarity for TIx clock sources */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
+  * @{
+  */
+#define TIM_CLOCKPRESCALER_DIV1                 TIM_ETRPRESCALER_DIV1           /*!< No prescaler is used                                                     */
+#define TIM_CLOCKPRESCALER_DIV2                 TIM_ETRPRESCALER_DIV2           /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
+#define TIM_CLOCKPRESCALER_DIV4                 TIM_ETRPRESCALER_DIV4           /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
+#define TIM_CLOCKPRESCALER_DIV8                 TIM_ETRPRESCALER_DIV8           /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
+  * @{
+  */
+#define TIM_CLEARINPUTPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED      /*!< Polarity for ETRx pin */
+#define TIM_CLEARINPUTPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED   /*!< Polarity for ETRx pin */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
+  * @{
+  */
+#define TIM_CLEARINPUTPRESCALER_DIV1              TIM_ETRPRESCALER_DIV1         /*!< No prescaler is used                                                   */
+#define TIM_CLEARINPUTPRESCALER_DIV2              TIM_ETRPRESCALER_DIV2         /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV4              TIM_ETRPRESCALER_DIV4         /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV8              TIM_ETRPRESCALER_DIV8         /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
+  * @{
+  */
+#define TIM_OSSR_ENABLE                          TIM_BDTR_OSSR                  /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer)           */
+#define TIM_OSSR_DISABLE                         0x00000000U                    /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
+  * @{
+  */
+#define TIM_OSSI_ENABLE                          TIM_BDTR_OSSI                  /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer)           */
+#define TIM_OSSI_DISABLE                         0x00000000U                    /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
+/**
+  * @}
+  */
+/** @defgroup TIM_Lock_level  TIM Lock level
+  * @{
+  */
+#define TIM_LOCKLEVEL_OFF                  0x00000000U                          /*!< LOCK OFF     */
+#define TIM_LOCKLEVEL_1                    TIM_BDTR_LOCK_0                      /*!< LOCK Level 1 */
+#define TIM_LOCKLEVEL_2                    TIM_BDTR_LOCK_1                      /*!< LOCK Level 2 */
+#define TIM_LOCKLEVEL_3                    TIM_BDTR_LOCK                        /*!< LOCK Level 3 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
+  * @{
+  */
+#define TIM_BREAK_ENABLE                   TIM_BDTR_BKE                         /*!< Break input BRK is enabled  */
+#define TIM_BREAK_DISABLE                  0x00000000U                          /*!< Break input BRK is disabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
+  * @{
+  */
+#define TIM_BREAKPOLARITY_LOW              0x00000000U                          /*!< Break input BRK is active low  */
+#define TIM_BREAKPOLARITY_HIGH             TIM_BDTR_BKP                         /*!< Break input BRK is active high */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable
+  * @{
+  */
+#define TIM_BREAK2_DISABLE                 0x00000000U                          /*!< Break input BRK2 is disabled  */
+#define TIM_BREAK2_ENABLE                  TIM_BDTR_BK2E                        /*!< Break input BRK2 is enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity
+  * @{
+  */
+#define TIM_BREAK2POLARITY_LOW             0x00000000U                          /*!< Break input BRK2 is active low   */
+#define TIM_BREAK2POLARITY_HIGH            TIM_BDTR_BK2P                        /*!< Break input BRK2 is active high  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
+  * @{
+  */
+#define TIM_AUTOMATICOUTPUT_DISABLE        0x00000000U                          /*!< MOE can be set only by software */
+#define TIM_AUTOMATICOUTPUT_ENABLE         TIM_BDTR_AOE                         /*!< MOE can be set by software or automatically at the next update event 
+                                                                                    (if none of the break inputs BRK and BRK2 is active) */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3
+  * @{
+  */
+#define TIM_GROUPCH5_NONE                  0x00000000U                          /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
+#define TIM_GROUPCH5_OC1REFC               TIM_CCR5_GC5C1                       /* !< OC1REFC is the logical AND of OC1REFC and OC5REF    */
+#define TIM_GROUPCH5_OC2REFC               TIM_CCR5_GC5C2                       /* !< OC2REFC is the logical AND of OC2REFC and OC5REF    */
+#define TIM_GROUPCH5_OC3REFC               TIM_CCR5_GC5C3                       /* !< OC3REFC is the logical AND of OC3REFC and OC5REF    */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
+  * @{
+  */
+#define TIM_TRGO_RESET            0x00000000U                                      /*!< TIMx_EGR.UG bit is used as trigger output (TRGO)              */
+#define TIM_TRGO_ENABLE           TIM_CR2_MMS_0                                    /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO)             */
+#define TIM_TRGO_UPDATE           TIM_CR2_MMS_1                                    /*!< Update event is used as trigger output (TRGO)                 */
+#define TIM_TRGO_OC1              (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                  /*!< Capture or a compare match 1 is used as trigger output (TRGO) */
+#define TIM_TRGO_OC1REF           TIM_CR2_MMS_2                                    /*!< OC1REF signal is used as trigger output (TRGO)                */
+#define TIM_TRGO_OC2REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                  /*!< OC2REF signal is used as trigger output(TRGO)                 */
+#define TIM_TRGO_OC3REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                  /*!< OC3REF signal is used as trigger output(TRGO)                 */
+#define TIM_TRGO_OC4REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)  /*!< OC4REF signal is used as trigger output(TRGO)                 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2)
+  * @{
+  */
+#define TIM_TRGO2_RESET                          0x00000000U                                                         /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2)              */
+#define TIM_TRGO2_ENABLE                         TIM_CR2_MMS2_0                                                      /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2)             */
+#define TIM_TRGO2_UPDATE                         TIM_CR2_MMS2_1                                                      /*!< Update event is used as trigger output (TRGO2)                 */
+#define TIM_TRGO2_OC1                            (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                                   /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */
+#define TIM_TRGO2_OC1REF                         TIM_CR2_MMS2_2                                                      /*!< OC1REF signal is used as trigger output (TRGO2)                */
+#define TIM_TRGO2_OC2REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                                   /*!< OC2REF signal is used as trigger output (TRGO2)                */
+#define TIM_TRGO2_OC3REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)                                   /*!< OC3REF signal is used as trigger output (TRGO2)                */
+#define TIM_TRGO2_OC4REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC4REF signal is used as trigger output (TRGO2)                */
+#define TIM_TRGO2_OC5REF                         TIM_CR2_MMS2_3                                                      /*!< OC5REF signal is used as trigger output (TRGO2)                */
+#define TIM_TRGO2_OC6REF                         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)                                   /*!< OC6REF signal is used as trigger output (TRGO2)                */
+#define TIM_TRGO2_OC4REF_RISINGFALLING           (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)                                   /*!< OC4REF rising or falling edges generate pulses on TRGO2        */
+#define TIM_TRGO2_OC6REF_RISINGFALLING           (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC6REF rising or falling edges generate pulses on TRGO2        */
+#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)                                   /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2         */
+#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING   (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                  /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */
+#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)                   /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2         */
+#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING   (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2         */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
+  * @{
+  */
+#define TIM_MASTERSLAVEMODE_ENABLE         TIM_SMCR_MSM                         /*!< No action */
+#define TIM_MASTERSLAVEMODE_DISABLE        0x00000000U                          /*!< Master/slave mode is selected */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Slave_Mode TIM Slave mode
+  * @{
+  */
+#define TIM_SLAVEMODE_DISABLE                0x00000000U                                        /*!< Slave mode disabled           */
+#define TIM_SLAVEMODE_RESET                  TIM_SMCR_SMS_2                                     /*!< Reset Mode                    */
+#define TIM_SLAVEMODE_GATED                  (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)                  /*!< Gated Mode                    */
+#define TIM_SLAVEMODE_TRIGGER                (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)                  /*!< Trigger Mode                  */
+#define TIM_SLAVEMODE_EXTERNAL1              (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1         */
+#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER  TIM_SMCR_SMS_3                                     /*!< Combined reset + trigger mode */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
+  * @{
+  */
+#define TIM_OCMODE_TIMING                   0x00000000U                                              /*!< Frozen                                 */
+#define TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!< Set channel to active level on match   */
+#define TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!< Set channel to inactive level on match */
+#define TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!< Toggle                                 */
+#define TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!< PWM mode 1                             */
+#define TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2                             */
+#define TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!< Force active level                     */
+#define TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                         /*!< Force inactive level                   */
+#define TIM_OCMODE_RETRIGERRABLE_OPM1      TIM_CCMR1_OC1M_3                                          /*!< Retrigerrable OPM mode 1               */
+#define TIM_OCMODE_RETRIGERRABLE_OPM2      (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)                     /*!< Retrigerrable OPM mode 2               */
+#define TIM_OCMODE_COMBINED_PWM1           (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)                     /*!< Combined PWM mode 1                    */
+#define TIM_OCMODE_COMBINED_PWM2           (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)  /*!< Combined PWM mode 2                    */
+#define TIM_OCMODE_ASSYMETRIC_PWM1         (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)  /*!< Asymmetric PWM mode 1                  */
+#define TIM_OCMODE_ASSYMETRIC_PWM2         TIM_CCMR1_OC1M                                            /*!< Asymmetric PWM mode 2                  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
+  * @{
+  */
+#define TIM_TS_ITR0          0x00000000U                                                       /*!< Internal Trigger 0 (ITR0)              */
+#define TIM_TS_ITR1          TIM_SMCR_TS_0                                                     /*!< Internal Trigger 1 (ITR1)              */
+#define TIM_TS_ITR2          TIM_SMCR_TS_1                                                     /*!< Internal Trigger 2 (ITR2)              */
+#define TIM_TS_ITR3          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                   /*!< Internal Trigger 3 (ITR3)              */
+#define TIM_TS_TI1F_ED       TIM_SMCR_TS_2                                                     /*!< TI1 Edge Detector (TI1F_ED)            */
+#define TIM_TS_TI1FP1        (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 1 (TI1FP1)        */
+#define TIM_TS_TI2FP2        (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 2 (TI2FP2)        */
+#define TIM_TS_ETRF          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                   /*!< Filtered External Trigger input (ETRF) */
+#define TIM_TS_ITR4          (TIM_SMCR_TS_3)                                                   /*!< Internal Trigger 4 (ITR4)              */
+#define TIM_TS_ITR5          (TIM_SMCR_TS_0 | TIM_SMCR_TS_3)                                   /*!< Internal Trigger 5 (ITR5)              */
+#define TIM_TS_ITR6          (TIM_SMCR_TS_1 | TIM_SMCR_TS_3)                                   /*!< Internal Trigger 6 (ITR6)              */
+#define TIM_TS_ITR7          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3)                   /*!< Internal Trigger 7 (ITR7)              */
+#define TIM_TS_ITR8          (TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                                   /*!< Internal Trigger 8 (ITR8)              */
+#define TIM_TS_ITR9          (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                   /*!< Internal Trigger 9 (ITR9)              */
+#define TIM_TS_ITR10         (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                   /*!< Internal Trigger 10 (ITR10)            */
+#define TIM_TS_ITR11         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)   /*!< Internal Trigger 11 (ITR11)            */
+#define TIM_TS_ITR12         (TIM_SMCR_TS_4)                                                   /*!< Internal Trigger 12 (ITR12)            */
+#define TIM_TS_ITR13         (TIM_SMCR_TS_0 | TIM_SMCR_TS_4)                                   /*!< Internal Trigger 13 (ITR13)            */
+#define TIM_TS_NONE          0x0000FFFFU                                                       /*!< No trigger selected                    */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
+  * @{
+  */
+#define TIM_TRIGGERPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED               /*!< Polarity for ETRx trigger sources             */
+#define TIM_TRIGGERPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED            /*!< Polarity for ETRx trigger sources             */
+#define TIM_TRIGGERPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING        /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING       /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE      /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
+  * @{
+  */
+#define TIM_TRIGGERPRESCALER_DIV1             TIM_ETRPRESCALER_DIV1             /*!< No prescaler is used                                                       */
+#define TIM_TRIGGERPRESCALER_DIV2             TIM_ETRPRESCALER_DIV2             /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
+#define TIM_TRIGGERPRESCALER_DIV4             TIM_ETRPRESCALER_DIV4             /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
+#define TIM_TRIGGERPRESCALER_DIV8             TIM_ETRPRESCALER_DIV8             /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
+  * @{
+  */
+#define TIM_TI1SELECTION_CH1               0x00000000U                          /*!< The TIMx_CH1 pin is connected to TI1 input */
+#define TIM_TI1SELECTION_XORCOMBINATION    TIM_CR2_TI1S                         /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
+  * @{
+  */
+#define TIM_DMABURSTLENGTH_1TRANSFER       0x00000000U                          /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA   */
+#define TIM_DMABURSTLENGTH_2TRANSFERS      0x00000100U                          /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_3TRANSFERS      0x00000200U                          /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_4TRANSFERS      0x00000300U                          /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_5TRANSFERS      0x00000400U                          /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_6TRANSFERS      0x00000500U                          /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_7TRANSFERS      0x00000600U                          /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_8TRANSFERS      0x00000700U                          /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_9TRANSFERS      0x00000800U                          /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_10TRANSFERS     0x00000900U                          /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_11TRANSFERS     0x00000A00U                          /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_12TRANSFERS     0x00000B00U                          /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_13TRANSFERS     0x00000C00U                          /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_14TRANSFERS     0x00000D00U                          /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_15TRANSFERS     0x00000E00U                          /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_16TRANSFERS     0x00000F00U                          /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_17TRANSFERS     0x00001000U                          /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_18TRANSFERS     0x00001100U                          /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Handle_index TIM DMA Handle Index
+  * @{
+  */
+#define TIM_DMA_ID_UPDATE                ((uint16_t) 0x0000)       /*!< Index of the DMA handle used for Update DMA requests */
+#define TIM_DMA_ID_CC1                   ((uint16_t) 0x0001)       /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
+#define TIM_DMA_ID_CC2                   ((uint16_t) 0x0002)       /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
+#define TIM_DMA_ID_CC3                   ((uint16_t) 0x0003)       /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
+#define TIM_DMA_ID_CC4                   ((uint16_t) 0x0004)       /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
+#define TIM_DMA_ID_COMMUTATION           ((uint16_t) 0x0005)       /*!< Index of the DMA handle used for Commutation DMA requests */
+#define TIM_DMA_ID_TRIGGER               ((uint16_t) 0x0006)       /*!< Index of the DMA handle used for Trigger DMA requests */
+/**
+  * @}
+  */
+
+/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
+  * @{
+  */
+#define TIM_CCx_ENABLE                   0x00000001U                            /*!< Input or output channel is enabled */
+#define TIM_CCx_DISABLE                  0x00000000U                            /*!< Input or output channel is disabled */
+#define TIM_CCxN_ENABLE                  0x00000004U                            /*!< Complementary output channel is enabled */
+#define TIM_CCxN_DISABLE                 0x00000000U                            /*!< Complementary output channel is enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break_System TIM Break System
+  * @{
+  */
+#define TIM_BREAK_SYSTEM_ECC                 SYSCFG_CFGR2_ECCL   /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */
+#define TIM_BREAK_SYSTEM_PVD                 SYSCFG_CFGR2_PVDL   /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */
+#define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR   SYSCFG_CFGR2_SPL    /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17 */
+#define TIM_BREAK_SYSTEM_LOCKUP              SYSCFG_CFGR2_CLL    /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported constants -------------------------------------------------*/
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup TIM_Exported_Macros TIM Exported Macros
+  * @{
+  */
+
+/** @brief  Reset TIM handle state.
+  * @param  __HANDLE__ TIM handle.
+  * @retval None
+  */
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                        \
+                                                      (__HANDLE__)->State             = HAL_TIM_STATE_RESET; \
+                                                      (__HANDLE__)->Base_MspInitCallback         = NULL;     \
+                                                      (__HANDLE__)->Base_MspDeInitCallback       = NULL;     \
+                                                      (__HANDLE__)->IC_MspInitCallback           = NULL;     \
+                                                      (__HANDLE__)->IC_MspDeInitCallback         = NULL;     \
+                                                      (__HANDLE__)->OC_MspInitCallback           = NULL;     \
+                                                      (__HANDLE__)->OC_MspDeInitCallback         = NULL;     \
+                                                      (__HANDLE__)->PWM_MspInitCallback          = NULL;     \
+                                                      (__HANDLE__)->PWM_MspDeInitCallback        = NULL;     \
+                                                      (__HANDLE__)->OnePulse_MspInitCallback     = NULL;     \
+                                                      (__HANDLE__)->OnePulse_MspDeInitCallback   = NULL;     \
+                                                      (__HANDLE__)->Encoder_MspInitCallback      = NULL;     \
+                                                      (__HANDLE__)->Encoder_MspDeInitCallback    = NULL;     \
+                                                      (__HANDLE__)->HallSensor_MspInitCallback   = NULL;     \
+                                                      (__HANDLE__)->HallSensor_MspDeInitCallback = NULL;     \
+                                                     } while(0)
+#else
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @brief  Enable the TIM peripheral.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
+
+/**
+  * @brief  Enable the TIM main Output.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  */
+#define __HAL_TIM_MOE_ENABLE(__HANDLE__)             ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
+
+/**
+  * @brief  Disable the TIM peripheral.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE(__HANDLE__) \
+  do { \
+    if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
+    { \
+      if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
+      { \
+        (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
+      } \
+    } \
+  } while(0)
+
+/**
+  * @brief  Disable the TIM main Output.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
+  */
+#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
+  do { \
+    if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
+    { \
+      if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
+      { \
+        (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
+      } \
+    } \
+  } while(0)
+
+/**
+  * @brief  Disable the TIM main Output.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  * @note The Main Output Enable of a timer instance is disabled unconditionally
+  */
+#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__)  (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
+
+/** @brief  Enable the specified TIM interrupt.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __INTERRUPT__ specifies the TIM interrupt source to enable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_COM:   Commutation interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  *            @arg TIM_IT_BREAK: Break interrupt
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
+
+/** @brief  Disable the specified TIM interrupt.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __INTERRUPT__ specifies the TIM interrupt source to disable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_COM:   Commutation interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  *            @arg TIM_IT_BREAK: Break interrupt
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
+
+/** @brief  Enable the specified DMA request.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __DMA__ specifies the TIM DMA request to enable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: Update DMA request
+  *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
+  *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
+  *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
+  *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
+  *            @arg TIM_DMA_COM:   Commutation DMA request
+  *            @arg TIM_DMA_TRIGGER: Trigger DMA request
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__)         ((__HANDLE__)->Instance->DIER |= (__DMA__))
+
+/** @brief  Disable the specified DMA request.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __DMA__ specifies the TIM DMA request to disable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: Update DMA request
+  *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
+  *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
+  *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
+  *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
+  *            @arg TIM_DMA_COM:   Commutation DMA request
+  *            @arg TIM_DMA_TRIGGER: Trigger DMA request
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__)        ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
+
+/** @brief  Check whether the specified TIM interrupt flag is set or not.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __FLAG__ specifies the TIM interrupt flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg TIM_FLAG_UPDATE: Update interrupt flag
+  *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
+  *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
+  *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
+  *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
+  *            @arg TIM_FLAG_CC5: Compare 5 interrupt flag
+  *            @arg TIM_FLAG_CC6: Compare 6 interrupt flag
+  *            @arg TIM_FLAG_COM:  Commutation interrupt flag
+  *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
+  *            @arg TIM_FLAG_BREAK: Break interrupt flag
+  *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
+  *            @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
+  *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
+  *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
+  *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
+  *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
+
+/** @brief  Clear the specified TIM interrupt flag.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __FLAG__ specifies the TIM interrupt flag to clear.
+  *        This parameter can be one of the following values:
+  *            @arg TIM_FLAG_UPDATE: Update interrupt flag
+  *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
+  *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
+  *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
+  *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
+  *            @arg TIM_FLAG_CC5: Compare 5 interrupt flag
+  *            @arg TIM_FLAG_CC6: Compare 6 interrupt flag
+  *            @arg TIM_FLAG_COM:  Commutation interrupt flag
+  *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
+  *            @arg TIM_FLAG_BREAK: Break interrupt flag
+  *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
+  *            @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
+  *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
+  *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
+  *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
+  *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->SR = ~(__FLAG__))
+
+/**
+  * @brief  Check whether the specified TIM interrupt source is enabled or not.
+  * @param  __HANDLE__ TIM handle
+  * @param  __INTERRUPT__ specifies the TIM interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_COM:   Commutation interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  *            @arg TIM_IT_BREAK: Break interrupt
+  * @retval The state of TIM_IT (SET or RESET).
+  */
+#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
+                                                             == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Clear the TIM interrupt pending bits.
+  * @param  __HANDLE__ TIM handle
+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_COM:   Commutation interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  *            @arg TIM_IT_BREAK: Break interrupt
+  * @retval None
+  */
+#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
+
+/**
+  * @brief  Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
+  * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
+  * @param  __HANDLE__ TIM handle.
+  * @retval None
+mode.
+  */
+#define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__)    (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP))
+
+/**
+  * @brief  Disable update interrupt flag (UIF) remapping.
+  * @param  __HANDLE__ TIM handle.
+  * @retval None
+mode.
+  */
+#define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__)    (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP))
+
+/**
+  * @brief  Get update interrupt flag (UIF) copy status.
+  * @param  __COUNTER__ Counter value.
+  * @retval The state of UIFCPY (TRUE or FALSE).
+mode.
+  */
+#define __HAL_TIM_GET_UIFCPY(__COUNTER__)    (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY))
+
+/**
+  * @brief  Indicates whether or not the TIM Counter is used as downcounter.
+  * @param  __HANDLE__ TIM handle.
+  * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
+  * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
+mode.
+  */
+#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__)    (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
+
+/**
+  * @brief  Set the TIM Prescaler on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __PRESC__ specifies the Prescaler new value.
+  * @retval None
+  */
+#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__)       ((__HANDLE__)->Instance->PSC = (__PRESC__))
+
+/**
+  * @brief  Set the TIM Counter Register value on runtime.
+  * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in case of 32 bits counter TIM instance.
+  *      Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __COUNTER__ specifies the Counter register new value.
+  * @retval None
+  */
+#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__)  ((__HANDLE__)->Instance->CNT = (__COUNTER__))
+
+/**
+  * @brief  Get the TIM Counter Register value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
+  */
+#define __HAL_TIM_GET_COUNTER(__HANDLE__)  ((__HANDLE__)->Instance->CNT)
+
+/**
+  * @brief  Set the TIM Autoreload Register value on runtime without calling another time any Init function.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __AUTORELOAD__ specifies the Counter register new value.
+  * @retval None
+  */
+#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
+  do{                                                    \
+    (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
+    (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
+  } while(0)
+
+/**
+  * @brief  Get the TIM Autoreload Register value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
+  */
+#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__)  ((__HANDLE__)->Instance->ARR)
+
+/**
+  * @brief  Set the TIM Clock Division value on runtime without calling another time any Init function.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CKD__ specifies the clock division value.
+  *          This parameter can be one of the following value:
+  *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
+  * @retval None
+  */
+#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
+  do{                                                   \
+    (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD);  \
+    (__HANDLE__)->Instance->CR1 |= (__CKD__);       \
+    (__HANDLE__)->Init.ClockDivision = (__CKD__);   \
+  } while(0)
+
+/**
+  * @brief  Get the TIM Clock Division value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @retval The clock division can be one of the following values:
+  *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
+  */
+#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__)  ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
+
+/**
+  * @brief  Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  __ICPSC__ specifies the Input Capture4 prescaler new value.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPSC_DIV1: no prescaler
+  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+  * @retval None
+  */
+#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
+  do{                                                    \
+    TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \
+    TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
+  } while(0)
+
+/**
+  * @brief  Get the TIM Input Capture prescaler on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: get input capture 1 prescaler value
+  *            @arg TIM_CHANNEL_2: get input capture 2 prescaler value
+  *            @arg TIM_CHANNEL_3: get input capture 3 prescaler value
+  *            @arg TIM_CHANNEL_4: get input capture 4 prescaler value
+  * @retval The input capture prescaler can be one of the following values:
+  *            @arg TIM_ICPSC_DIV1: no prescaler
+  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+  */
+#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)  \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
+   (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
+
+/**
+  * @brief  Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @param  __COMPARE__ specifies the Capture Compare register new value.
+  * @retval None
+  */
+#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
+   ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
+
+/**
+  * @brief  Get the TIM Capture Compare Register value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channel associated with the capture compare register
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: get capture/compare 1 register value
+  *            @arg TIM_CHANNEL_2: get capture/compare 2 register value
+  *            @arg TIM_CHANNEL_3: get capture/compare 3 register value
+  *            @arg TIM_CHANNEL_4: get capture/compare 4 register value
+  *            @arg TIM_CHANNEL_5: get capture/compare 5 register value
+  *            @arg TIM_CHANNEL_6: get capture/compare 6 register value
+  * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
+  */
+#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
+   ((__HANDLE__)->Instance->CCR6))
+
+/**
+  * @brief  Set the TIM Output compare preload.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
+   ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))
+
+/**
+  * @brief  Reset the TIM Output compare preload.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\
+   ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE))
+
+/**
+  * @brief  Enable fast mode for a given channel.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @note  When fast mode is enabled an active edge on the trigger input acts
+  *        like a compare match on CCx output. Delay to sample the trigger
+  *        input and to activate CCx output is reduced to 3 clock cycles.
+  * @note  Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\
+   ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE))
+
+/**
+  * @brief  Disable fast mode for a given channel.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @note  When fast mode is disabled CCx output behaves normally depending
+  *        on counter and CCRx values even when the trigger is ON. The minimum
+  *        delay to activate CCx output when an active edge occurs on the
+  *        trigger input is 5 clock cycles.
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\
+   ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE))
+
+/**
+  * @brief  Set the Update Request Source (URS) bit of the TIMx_CR1 register.
+  * @param  __HANDLE__ TIM handle.
+  * @note  When the URS bit of the TIMx_CR1 register is set, only counter
+  *        overflow/underflow generates an update interrupt or DMA request (if
+  *        enabled)
+  * @retval None
+  */
+#define __HAL_TIM_URS_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
+
+/**
+  * @brief  Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
+  * @param  __HANDLE__ TIM handle.
+  * @note  When the URS bit of the TIMx_CR1 register is reset, any of the
+  *        following events generate an update interrupt or DMA request (if
+  *        enabled):
+  *           _ Counter overflow underflow
+  *           _ Setting the UG bit
+  *           _ Update generation through the slave mode controller
+  * @retval None
+  */
+#define __HAL_TIM_URS_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
+
+/**
+  * @brief  Set the TIM Capture x input polarity on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  __POLARITY__ Polarity for TIx source
+  *            @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
+  *            @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
+  *            @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
+  * @retval None
+  */
+#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)    \
+  do{                                                                     \
+    TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \
+    TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
+  }while(0)
+
+/**
+  * @}
+  */
+/* End of exported macros ----------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup TIM_Private_Constants TIM Private Constants
+  * @{
+  */
+/* The counter of a timer instance is disabled only if all the CCx and CCxN
+   channels have been disabled */
+#define TIM_CCER_CCxE_MASK  ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
+#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
+/**
+  * @}
+  */
+/* End of private constants --------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TIM_Private_Macros TIM Private Macros
+  * @{
+  */
+#define IS_TIM_CLEARINPUT_SOURCE(__MODE__)  (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)      || \
+                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))
+
+#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1)   || \
+                                   ((__BASE__) == TIM_DMABASE_CR2)   || \
+                                   ((__BASE__) == TIM_DMABASE_SMCR)  || \
+                                   ((__BASE__) == TIM_DMABASE_DIER)  || \
+                                   ((__BASE__) == TIM_DMABASE_SR)    || \
+                                   ((__BASE__) == TIM_DMABASE_EGR)   || \
+                                   ((__BASE__) == TIM_DMABASE_CCMR1) || \
+                                   ((__BASE__) == TIM_DMABASE_CCMR2) || \
+                                   ((__BASE__) == TIM_DMABASE_CCER)  || \
+                                   ((__BASE__) == TIM_DMABASE_CNT)   || \
+                                   ((__BASE__) == TIM_DMABASE_PSC)   || \
+                                   ((__BASE__) == TIM_DMABASE_ARR)   || \
+                                   ((__BASE__) == TIM_DMABASE_RCR)   || \
+                                   ((__BASE__) == TIM_DMABASE_CCR1)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCR2)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCR3)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCR4)  || \
+                                   ((__BASE__) == TIM_DMABASE_BDTR)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCMR3) || \
+                                   ((__BASE__) == TIM_DMABASE_CCR5)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCR6)  || \
+                                   ((__BASE__) == TIM_DMABASE_AF1)   || \
+                                   ((__BASE__) == TIM_DMABASE_AF2)   || \
+                                   ((__BASE__) == TIM_DMABASE_TISEL))
+
+
+#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
+
+#define IS_TIM_COUNTER_MODE(__MODE__)      (((__MODE__) == TIM_COUNTERMODE_UP)              || \
+                                            ((__MODE__) == TIM_COUNTERMODE_DOWN)            || \
+                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
+                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
+                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
+
+#define IS_TIM_UIFREMAP_MODE(__MODE__)     (((__MODE__) == TIM_UIFREMAP_DISABLE) || \
+                                            ((__MODE__) == TIM_UIFREMAP_ENALE))
+
+#define IS_TIM_CLOCKDIVISION_DIV(__DIV__)  (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
+                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
+                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
+
+#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
+                                            ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
+
+#define IS_TIM_FAST_STATE(__STATE__)       (((__STATE__) == TIM_OCFAST_DISABLE) || \
+                                            ((__STATE__) == TIM_OCFAST_ENABLE))
+
+#define IS_TIM_OC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
+                                            ((__POLARITY__) == TIM_OCPOLARITY_LOW))
+
+#define IS_TIM_OCN_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
+                                            ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
+
+#define IS_TIM_OCIDLE_STATE(__STATE__)     (((__STATE__) == TIM_OCIDLESTATE_SET) || \
+                                            ((__STATE__) == TIM_OCIDLESTATE_RESET))
+
+#define IS_TIM_OCNIDLE_STATE(__STATE__)    (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
+                                            ((__STATE__) == TIM_OCNIDLESTATE_RESET))
+
+#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING)   || \
+                                                      ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
+
+#define IS_TIM_IC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ICPOLARITY_RISING)   || \
+                                            ((__POLARITY__) == TIM_ICPOLARITY_FALLING)  || \
+                                            ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
+
+#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
+                                            ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
+                                            ((__SELECTION__) == TIM_ICSELECTION_TRC))
+
+#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
+                                            ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
+                                            ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
+                                            ((__PRESCALER__) == TIM_ICPSC_DIV8))
+
+#define IS_TIM_OPM_MODE(__MODE__)          (((__MODE__) == TIM_OPMODE_SINGLE) || \
+                                            ((__MODE__) == TIM_OPMODE_REPETITIVE))
+
+#define IS_TIM_ENCODER_MODE(__MODE__)      (((__MODE__) == TIM_ENCODERMODE_TI1) || \
+                                            ((__MODE__) == TIM_ENCODERMODE_TI2) || \
+                                            ((__MODE__) == TIM_ENCODERMODE_TI12))
+
+#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
+
+#define IS_TIM_CHANNELS(__CHANNEL__)       (((__CHANNEL__) == TIM_CHANNEL_1) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_2) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_3) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_4) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_5) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_6) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_ALL))
+
+#define IS_TIM_OPM_CHANNELS(__CHANNEL__)   (((__CHANNEL__) == TIM_CHANNEL_1) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_2))
+
+#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
+                                                    ((__CHANNEL__) == TIM_CHANNEL_2) || \
+                                                    ((__CHANNEL__) == TIM_CHANNEL_3))
+
+#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
+
+#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED)    || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING)      || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING)     || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
+
+#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
+                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
+                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
+                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
+
+#define IS_TIM_CLOCKFILTER(__ICFILTER__)      ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
+                                                  ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
+
+#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
+                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
+                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
+                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
+
+#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_OSSR_STATE(__STATE__)       (((__STATE__) == TIM_OSSR_ENABLE) || \
+                                            ((__STATE__) == TIM_OSSR_DISABLE))
+
+#define IS_TIM_OSSI_STATE(__STATE__)       (((__STATE__) == TIM_OSSI_ENABLE) || \
+                                            ((__STATE__) == TIM_OSSI_DISABLE))
+
+#define IS_TIM_LOCK_LEVEL(__LEVEL__)       (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
+                                            ((__LEVEL__) == TIM_LOCKLEVEL_1)   || \
+                                            ((__LEVEL__) == TIM_LOCKLEVEL_2)   || \
+                                            ((__LEVEL__) == TIM_LOCKLEVEL_3))
+
+#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
+
+
+#define IS_TIM_BREAK_STATE(__STATE__)      (((__STATE__) == TIM_BREAK_ENABLE) || \
+                                            ((__STATE__) == TIM_BREAK_DISABLE))
+
+#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
+                                             ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
+
+#define IS_TIM_BREAK2_STATE(__STATE__)     (((__STATE__) == TIM_BREAK2_ENABLE) || \
+                                            ((__STATE__) == TIM_BREAK2_DISABLE))
+
+#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
+                                              ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
+
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
+                                                  ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
+
+#define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))
+
+#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET)  || \
+                                        ((__SOURCE__) == TIM_TRGO_ENABLE) || \
+                                        ((__SOURCE__) == TIM_TRGO_UPDATE) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC1)    || \
+                                        ((__SOURCE__) == TIM_TRGO_OC1REF) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC2REF) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC3REF) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC4REF))
+
+#define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET)                        || \
+                                         ((__SOURCE__) == TIM_TRGO2_ENABLE)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_UPDATE)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC1)                          || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC1REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC2REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC4REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC5REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC6REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING)         || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING)         || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING)  || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING)  || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
+
+#define IS_TIM_MSM_STATE(__STATE__)      (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
+                                          ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
+
+#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE)   || \
+                                     ((__MODE__) == TIM_SLAVEMODE_RESET)     || \
+                                     ((__MODE__) == TIM_SLAVEMODE_GATED)     || \
+                                     ((__MODE__) == TIM_SLAVEMODE_TRIGGER)   || \
+                                     ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \
+                                     ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
+
+#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1)               || \
+                                   ((__MODE__) == TIM_OCMODE_PWM2)               || \
+                                   ((__MODE__) == TIM_OCMODE_COMBINED_PWM1)      || \
+                                   ((__MODE__) == TIM_OCMODE_COMBINED_PWM2)      || \
+                                   ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1)    || \
+                                   ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))
+
+#define IS_TIM_OC_MODE(__MODE__)  (((__MODE__) == TIM_OCMODE_TIMING)             || \
+                                   ((__MODE__) == TIM_OCMODE_ACTIVE)             || \
+                                   ((__MODE__) == TIM_OCMODE_INACTIVE)           || \
+                                   ((__MODE__) == TIM_OCMODE_TOGGLE)             || \
+                                   ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE)      || \
+                                   ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)    || \
+                                   ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
+                                   ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2))
+
+#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR1) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR2) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR3) || \
+                                                 ((__SELECTION__) == TIM_TS_TI1F_ED) || \
+                                                 ((__SELECTION__) == TIM_TS_TI1FP1) || \
+                                                 ((__SELECTION__) == TIM_TS_TI2FP2) || \
+                                                 ((__SELECTION__) == TIM_TS_ETRF) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR4) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR5) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR6) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR7) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR8) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR12) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR13))
+
+#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR1) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR2) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR3) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR4) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR5) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR6) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR7) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR8) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR12) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR13) || \
+                                                               ((__SELECTION__) == TIM_TS_NONE))
+
+#define IS_TIM_TRIGGERPOLARITY(__POLARITY__)   (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING     ) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING    ) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))
+
+#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
+                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
+                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
+                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
+
+#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_TI1SELECTION(__TI1SELECTION__)  (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
+                                                ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
+
+#define IS_TIM_DMA_LENGTH(__LENGTH__)      (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
+
+#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
+
+#define IS_TIM_IC_FILTER(__ICFILTER__)   ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_DEADTIME(__DEADTIME__)    ((__DEADTIME__) <= 0xFFU)
+
+#define IS_TIM_BREAK_SYSTEM(__CONFIG__)    (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC)                  || \
+                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD)                  || \
+                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR)    || \
+                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))
+
+#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \
+                                                       ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
+
+#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
+   ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
+
+#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
+   ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
+
+#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
+   ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
+
+#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
+   ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
+
+/**
+  * @}
+  */
+/* End of private macros -----------------------------------------------------*/
+
+/* Include TIM HAL Extended module */
+#include "stm32h7xx_hal_tim_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIM_Exported_Functions TIM Exported Functions
+  * @{
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
+  *  @brief   Time Base functions
+  * @{
+  */
+/* Time Base functions ********************************************************/
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
+  *  @brief   TIM Output Compare functions
+  * @{
+  */
+/* Timer Output Compare functions *********************************************/
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
+  *  @brief   TIM PWM functions
+  * @{
+  */
+/* Timer PWM functions ********************************************************/
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
+  *  @brief   TIM Input Capture functions
+  * @{
+  */
+/* Timer Input Capture functions **********************************************/
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
+  *  @brief   TIM One Pulse functions
+  * @{
+  */
+/* Timer One Pulse functions **************************************************/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
+  *  @brief   TIM Encoder functions
+  * @{
+  */
+/* Timer Encoder functions ****************************************************/
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef *sConfig);
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
+                                            uint32_t *pData2, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
+  *  @brief   IRQ handler management
+  * @{
+  */
+/* Interrupt Handler functions  ***********************************************/
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
+  *  @brief   Peripheral Control functions
+  * @{
+  */
+/* Control functions  *********************************************************/
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
+                                                 uint32_t OutputChannel,  uint32_t InputChannel);
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,
+                                           uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                              uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                                   uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
+                                                   uint32_t DataLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                             uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                                  uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength,
+                                                  uint32_t  DataLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
+  *  @brief   TIM Callbacks functions
+  * @{
+  */
+/* Callback in non blocking modes (Interrupt and DMA) *************************/
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
+                                           pTIM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
+  *  @brief  Peripheral State functions
+  * @{
+  */
+/* Peripheral State functions  ************************************************/
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private functions----------------------------------------------------------*/
+/** @defgroup TIM_Private_Functions TIM Private Functions
+  * @{
+  */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
+                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
+
+void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMAError(DMA_HandleTypeDef *hdma);
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
+void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+void TIM_ResetCallback(TIM_HandleTypeDef *htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+/* End of private functions --------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_TIM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h
new file mode 100644
index 00000000..0a7ef48a
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h
@@ -0,0 +1,529 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_tim_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of TIM HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_TIM_EX_H
+#define STM32H7xx_HAL_TIM_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup TIMEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
+  * @{
+  */
+
+/**
+  * @brief  TIM Hall sensor Configuration Structure definition
+  */
+
+typedef struct
+{
+  uint32_t IC1Polarity;         /*!< Specifies the active edge of the input signal.
+                                     This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint32_t IC1Prescaler;        /*!< Specifies the Input Capture Prescaler.
+                                     This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t IC1Filter;           /*!< Specifies the input capture filter.
+                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+  uint32_t Commutation_Delay;   /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+                                     This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+} TIM_HallSensor_InitTypeDef;
+#if defined(TIM_BREAK_INPUT_SUPPORT)
+
+/**
+  * @brief  TIM Break/Break2 input configuration
+  */
+typedef struct
+{
+  uint32_t Source;         /*!< Specifies the source of the timer break input.
+                                This parameter can be a value of @ref TIMEx_Break_Input_Source */
+  uint32_t Enable;         /*!< Specifies whether or not the break input source is enabled.
+                                This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */
+  uint32_t Polarity;       /*!< Specifies the break input source polarity.
+                                This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity
+                                Not relevant when analog watchdog output of the DFSDM1 used as break input source */
+}
+TIMEx_BreakInputConfigTypeDef;
+
+#endif /* TIM_BREAK_INPUT_SUPPORT */
+/**
+  * @}
+  */
+/* End of exported types -----------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
+  * @{
+  */
+
+/** @defgroup TIMEx_Remap TIM Extended Remapping
+  * @{
+  */
+#define TIM_TIM1_ETR_GPIO        0x00000000U                                                 /* !< TIM1_ETR is connected to GPIO */
+#define TIM_TIM1_ETR_COMP1       TIM1_AF1_ETRSEL_0                                           /* !< TIM1_ETR is connected to COMP1 OUT */
+#define TIM_TIM1_ETR_COMP2       TIM1_AF1_ETRSEL_1                                           /* !< TIM1_ETR is connected to COMP2 OUT */
+#define TIM_TIM1_ETR_ADC1_AWD1   (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                     /* !< TIM1_ETR is connected to ADC1 AWD1 */
+#define TIM_TIM1_ETR_ADC1_AWD2   (TIM1_AF1_ETRSEL_2)                                         /* !< TIM1_ETR is connected to ADC1 AWD2 */
+#define TIM_TIM1_ETR_ADC1_AWD3   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                     /* !< TIM1_ETR is connected to ADC1 AWD3 */
+#define TIM_TIM1_ETR_ADC3_AWD1   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                     /* !< TIM1_ETR is connected to ADC3 AWD1 */
+#define TIM_TIM1_ETR_ADC3_AWD2   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC3 AWD2 */
+#define TIM_TIM1_ETR_ADC3_AWD3   TIM1_AF1_ETRSEL_3                                           /* !< TIM1_ETR is connected to ADC3 AWD3 */
+
+#define TIM_TIM8_ETR_GPIO        0x00000000U                                                 /* !< TIM8_ETR is connected to GPIO */
+#define TIM_TIM8_ETR_COMP1       TIM8_AF1_ETRSEL_0                                           /* !< TIM8_ETR is connected to COMP1 OUT */
+#define TIM_TIM8_ETR_COMP2       TIM8_AF1_ETRSEL_1                                           /* !< TIM8_ETR is connected to COMP2 OUT */
+#define TIM_TIM8_ETR_ADC2_AWD1   (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)                     /* !< TIM8_ETR is connected to ADC2 AWD1 */
+#define TIM_TIM8_ETR_ADC2_AWD2   (TIM8_AF1_ETRSEL_2)                                         /* !< TIM8_ETR is connected to ADC2 AWD2 */
+#define TIM_TIM8_ETR_ADC2_AWD3   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0)                     /* !< TIM8_ETR is connected to ADC2 AWD3 */
+#define TIM_TIM8_ETR_ADC3_AWD1   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1)                     /* !< TIM8_ETR is connected to ADC3 AWD1 */
+#define TIM_TIM8_ETR_ADC3_AWD2   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC3 AWD2 */
+#define TIM_TIM8_ETR_ADC3_AWD3   TIM8_AF1_ETRSEL_3                                           /* !< TIM8_ETR is connected to ADC3 AWD3 */
+
+#define TIM_TIM2_ETR_GPIO        0x00000000U                             /* !< TIM2_ETR is connected to GPIO */
+#define TIM_TIM2_ETR_COMP1       (TIM2_AF1_ETRSEL_0)                     /* !< TIM2_ETR is connected to COMP1 OUT */
+#define TIM_TIM2_ETR_COMP2       (TIM2_AF1_ETRSEL_1)                     /* !< TIM2_ETR is connected to COMP2 OUT */
+#define TIM_TIM2_ETR_RCC_LSE     (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to RCC LSE */
+#define TIM_TIM2_ETR_SAI1_FSA    TIM2_AF1_ETRSEL_2                       /* !< TIM2_ETR is connected to SAI1 FS_A */
+#define TIM_TIM2_ETR_SAI1_FSB    (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to SAI1 FS_B */
+
+#define TIM_TIM3_ETR_GPIO        0x00000000U          /* !< TIM3_ETR is connected to GPIO */
+#define TIM_TIM3_ETR_COMP1       TIM3_AF1_ETRSEL_0    /* !< TIM3_ETR is connected to COMP1 OUT */
+
+#define TIM_TIM5_ETR_GPIO        0x00000000U          /* !< TIM5_ETR is connected to GPIO */
+#define TIM_TIM5_ETR_SAI2_FSA    TIM5_AF1_ETRSEL_0    /* !< TIM5_ETR is connected to SAI2 FS_A */
+#define TIM_TIM5_ETR_SAI2_FSB    TIM5_AF1_ETRSEL_1    /* !< TIM5_ETR is connected to SAI2 FS_B */
+#define TIM_TIM5_ETR_SAI4_FSA    TIM5_AF1_ETRSEL_0    /* !< TIM5_ETR is connected to SAI4 FS_A */
+#define TIM_TIM5_ETR_SAI4_FSB    TIM5_AF1_ETRSEL_1    /* !< TIM5_ETR is connected to SAI4 FS_B */
+
+#define TIM_TIM23_ETR_GPIO       0x00000000U          /* !< TIM23_ETR is connected to GPIO */
+#define TIM_TIM23_ETR_COMP1      (TIM2_AF1_ETRSEL_0)  /* !< TIM23_ETR is connected to COMP1 OUT */
+#define TIM_TIM23_ETR_COMP2      (TIM2_AF1_ETRSEL_1)  /* !< TIM23_ETR is connected to COMP2 OUT */
+
+#define TIM_TIM24_ETR_GPIO        0x00000000U                                /* !< TIM24_ETR is connected to GPIO */
+#define TIM_TIM24_ETR_SAI4_FSA    TIM5_AF1_ETRSEL_0                          /* !< TIM24_ETR is connected to SAI4 FS_A */
+#define TIM_TIM24_ETR_SAI4_FSB    TIM5_AF1_ETRSEL_1                          /* !< TIM24_ETR is connected to SAI4 FS_B */
+#define TIM_TIM24_ETR_SAI1_FSA    (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)    /* !< TIM24_ETR is connected to SAI1 FS_A */
+#define TIM_TIM24_ETR_SAI1_FSB    TIM2_AF1_ETRSEL_2                          /* !< TIM24_ETR is connected to SAI1 FS_B */
+/**
+  * @}
+  */
+#if defined(TIM_BREAK_INPUT_SUPPORT)
+
+/** @defgroup TIMEx_Break_Input TIM Extended Break input
+  * @{
+  */
+#define TIM_BREAKINPUT_BRK     0x00000001U                                      /* !< Timer break input  */
+#define TIM_BREAKINPUT_BRK2    0x00000002U                                      /* !< Timer break2 input */
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source
+  * @{
+  */
+#define TIM_BREAKINPUTSOURCE_BKIN     0x00000001U                               /* !< An external source (GPIO) is connected to the BKIN pin  */
+#define TIM_BREAKINPUTSOURCE_COMP1    0x00000002U                               /* !< The COMP1 output is connected to the break input */
+#define TIM_BREAKINPUTSOURCE_COMP2    0x00000004U                               /* !< The COMP2 output is connected to the break input */
+#define TIM_BREAKINPUTSOURCE_DFSDM1   0x00000008U                               /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling
+  * @{
+  */
+#define TIM_BREAKINPUTSOURCE_DISABLE     0x00000000U                            /* !< Break input source is disabled */
+#define TIM_BREAKINPUTSOURCE_ENABLE      0x00000001U                            /* !< Break input source is enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity
+  * @{
+  */
+#define TIM_BREAKINPUTSOURCE_POLARITY_LOW     0x00000001U                       /* !< Break input source is active low */
+#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH    0x00000000U                       /* !< Break input source is active_high */
+/**
+  * @}
+  */
+#endif /* TIM_BREAK_INPUT_SUPPORT */
+
+/** @defgroup TIMEx_Timer_Input_Selection TIM Extended Timer input selection
+  * @{
+  */
+#define TIM_TIM1_TI1_GPIO                          0x00000000U                               /* !< TIM1_TI1 is connected to GPIO */
+#define TIM_TIM1_TI1_COMP1                         TIM_TISEL_TI1SEL_0                        /* !< TIM1_TI1 is connected to COMP1 OUT */
+
+#define TIM_TIM8_TI1_GPIO                          0x00000000U                               /* !< TIM8_TI1 is connected to GPIO */
+#define TIM_TIM8_TI1_COMP2                         TIM_TISEL_TI1SEL_0                        /* !< TIM8_TI1 is connected to COMP2 OUT */
+
+#define TIM_TIM2_TI4_GPIO                          0x00000000U                               /* !< TIM2_TI4 is connected to GPIO */
+#define TIM_TIM2_TI4_COMP1                         TIM_TISEL_TI4SEL_0                        /* !< TIM2_TI4 is connected to COMP1 OUT */
+#define TIM_TIM2_TI4_COMP2                         TIM_TISEL_TI4SEL_1                        /* !< TIM2_TI4 is connected to COMP2 OUT */
+#define TIM_TIM2_TI4_COMP1_COMP2                   (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM2_TI4 is connected to COMP2 OUT OR COMP2 OUT */
+
+#define TIM_TIM3_TI1_GPIO                          0x00000000U                               /* !< TIM3_TI1 is connected to GPIO */
+#define TIM_TIM3_TI1_COMP1                         TIM_TISEL_TI1SEL_0                        /* !< TIM3_TI1 is connected to COMP1 OUT */
+#define TIM_TIM3_TI1_COMP2                         TIM_TISEL_TI1SEL_1                        /* !< TIM3_TI1 is connected to COMP2 OUT */
+#define TIM_TIM3_TI1_COMP1_COMP2                   (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM3_TI1 is connected to COMP1 OUT or COMP2 OUT */
+
+#define TIM_TIM5_TI1_GPIO                          0x00000000U                               /* !< TIM5_TI1 is connected to GPIO */
+#define TIM_TIM5_TI1_CAN_TMP                       TIM_TISEL_TI1SEL_0                        /* !< TIM5_TI1 is connected to CAN TMP */
+#define TIM_TIM5_TI1_CAN_RTP                       TIM_TISEL_TI1SEL_1                        /* !< TIM5_TI1 is connected to CAN RTP */
+
+#define TIM_TIM12_TI1_GPIO                         0x00000000U                               /* !< TIM12 TI1 is connected to GPIO */
+#define TIM_TIM12_TI1_SPDIF_FS                     TIM_TISEL_TI1SEL_0                        /* !< TIM12 TI1 is connected to SPDIF FS */
+
+#define TIM_TIM15_TI1_GPIO                         0x00000000U                               /* !< TIM15_TI1 is connected to GPIO */
+#define TIM_TIM15_TI1_TIM2_CH1                     TIM_TISEL_TI1SEL_0                        /* !< TIM15_TI1 is connected to TIM2 CH1 */
+#define TIM_TIM15_TI1_TIM3_CH1                     TIM_TISEL_TI1SEL_1                        /* !< TIM15_TI1 is connected to TIM3 CH1 */
+#define TIM_TIM15_TI1_TIM4_CH1                     (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM15_TI1 is connected to TIM4 CH1 */
+#define TIM_TIM15_TI1_RCC_LSE                      (TIM_TISEL_TI1SEL_2)                      /* !< TIM15_TI1 is connected to RCC LSE  */
+#define TIM_TIM15_TI1_RCC_CSI                      (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /* !< TIM15_TI1 is connected to RCC CSI  */
+#define TIM_TIM15_TI1_RCC_MCO2                     (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /* !< TIM15_TI1 is connected to RCC MCO2 */
+
+#define TIM_TIM15_TI2_GPIO                         0x00000000U                               /* !< TIM15_TI2 is connected to GPIO */
+#define TIM_TIM15_TI2_TIM2_CH2                     (TIM_TISEL_TI2SEL_0)                      /* !< TIM15_TI2 is connected to TIM2 CH2 */
+#define TIM_TIM15_TI2_TIM3_CH2                     (TIM_TISEL_TI2SEL_1)                      /* !< TIM15_TI2 is connected to TIM3 CH2 */
+#define TIM_TIM15_TI2_TIM4_CH2                     (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1) /* !< TIM15_TI2 is connected to TIM4 CH2 */
+
+#define TIM_TIM16_TI1_GPIO                         0x00000000U                               /* !< TIM16 TI1 is connected to GPIO */
+#define TIM_TIM16_TI1_RCC_LSI                      TIM_TISEL_TI1SEL_0                        /* !< TIM16 TI1 is connected to RCC LSI */
+#define TIM_TIM16_TI1_RCC_LSE                      TIM_TISEL_TI1SEL_1                        /* !< TIM16 TI1 is connected to RCC LSE */
+#define TIM_TIM16_TI1_WKUP_IT                      (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM16 TI1 is connected to WKUP_IT */
+
+#define TIM_TIM17_TI1_GPIO                         0x00000000U                               /* !< TIM17 TI1 is connected to GPIO */
+#define TIM_TIM17_TI1_SPDIF_FS                     TIM_TISEL_TI1SEL_0                        /* !< TIM17 TI1 is connected to SPDIF FS */
+#define TIM_TIM17_TI1_RCC_HSE1MHZ                  TIM_TISEL_TI1SEL_1                        /* !< TIM17 TI1 is connected to RCC HSE 1Mhz */
+#define TIM_TIM17_TI1_RCC_MCO1                     (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM17 TI1 is connected to RCC MCO1 */
+
+#define TIM_TIM23_TI4_GPIO                         0x00000000U                               /* !< TIM23_TI4 is connected to GPIO */
+#define TIM_TIM23_TI4_COMP1                        TIM_TISEL_TI4SEL_0                        /* !< TIM23_TI4 is connected to COMP1 OUT */
+#define TIM_TIM23_TI4_COMP2                        TIM_TISEL_TI4SEL_1                        /* !< TIM23_TI4 is connected to COMP2 OUT */
+#define TIM_TIM23_TI4_COMP1_COMP2                  (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM23_TI4 is connected to COMP1 OUT or COMP2 OUT */
+
+#define TIM_TIM24_TI1_GPIO                         0x00000000U                               /* !< TIM24_TI1 is connected to GPIO */
+#define TIM_TIM24_TI1_CAN_TMP                      TIM_TISEL_TI1SEL_0                        /* !< TIM24_TI1 is connected to CAN TMP  */
+#define TIM_TIM24_TI1_CAN_RTP                      TIM_TISEL_TI1SEL_1                        /* !< TIM24_TI1 is connected to CAN RTP  */
+#define TIM_TIM24_TI1_CAN_SOC                      (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM24_TI1 is connected to CAN SOC */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported constants -------------------------------------------------*/
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+/* End of exported macro -----------------------------------------------------*/
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
+  * @{
+  */
+#define IS_TIM_BREAKINPUT(__BREAKINPUT__)  (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK)  || \
+                                            ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
+
+#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__)  (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)  || \
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM1))
+
+#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__)  (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE)  || \
+                                                   ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
+
+#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW)  || \
+                                                         ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
+
+#define IS_TIM_TISEL(__TISEL__)  (((__TISEL__) == TIM_TIM1_TI1_GPIO)         ||\
+                                  ((__TISEL__) == TIM_TIM1_TI1_COMP1)        ||\
+                                  ((__TISEL__) == TIM_TIM8_TI1_GPIO)         ||\
+                                  ((__TISEL__) == TIM_TIM8_TI1_COMP2)        ||\
+                                  ((__TISEL__) == TIM_TIM2_TI4_GPIO)         ||\
+                                  ((__TISEL__) == TIM_TIM2_TI4_COMP1)        ||\
+                                  ((__TISEL__) == TIM_TIM2_TI4_COMP2)        ||\
+                                  ((__TISEL__) == TIM_TIM2_TI4_COMP1_COMP2)  ||\
+                                  ((__TISEL__) == TIM_TIM3_TI1_GPIO)         ||\
+                                  ((__TISEL__) == TIM_TIM3_TI1_COMP1)        ||\
+                                  ((__TISEL__) == TIM_TIM3_TI1_COMP2)        ||\
+                                  ((__TISEL__) == TIM_TIM3_TI1_COMP1_COMP2)  ||\
+                                  ((__TISEL__) == TIM_TIM5_TI1_GPIO)         ||\
+                                  ((__TISEL__) == TIM_TIM5_TI1_CAN_TMP)      ||\
+                                  ((__TISEL__) == TIM_TIM5_TI1_CAN_RTP)      ||\
+                                  ((__TISEL__) == TIM_TIM12_TI1_SPDIF_FS)    ||\
+                                  ((__TISEL__) == TIM_TIM12_TI1_GPIO)        ||\
+                                  ((__TISEL__) == TIM_TIM15_TI1_GPIO)        ||\
+                                  ((__TISEL__) == TIM_TIM15_TI1_TIM2_CH1)    ||\
+                                  ((__TISEL__) == TIM_TIM15_TI1_TIM3_CH1)    ||\
+                                  ((__TISEL__) == TIM_TIM15_TI1_TIM4_CH1)    ||\
+                                  ((__TISEL__) == TIM_TIM15_TI1_RCC_LSE)     ||\
+                                  ((__TISEL__) == TIM_TIM15_TI1_RCC_CSI)     ||\
+                                  ((__TISEL__) == TIM_TIM15_TI1_RCC_MCO2)    ||\
+                                  ((__TISEL__) == TIM_TIM15_TI2_GPIO)        ||\
+                                  ((__TISEL__) == TIM_TIM15_TI2_TIM2_CH2)    ||\
+                                  ((__TISEL__) == TIM_TIM15_TI2_TIM3_CH2)    ||\
+                                  ((__TISEL__) == TIM_TIM15_TI2_TIM4_CH2)    ||\
+                                  ((__TISEL__) == TIM_TIM16_TI1_GPIO)        ||\
+                                  ((__TISEL__) == TIM_TIM16_TI1_RCC_LSI)     ||\
+                                  ((__TISEL__) == TIM_TIM16_TI1_RCC_LSE)     ||\
+                                  ((__TISEL__) == TIM_TIM16_TI1_WKUP_IT)     ||\
+                                  ((__TISEL__) == TIM_TIM17_TI1_GPIO)        ||\
+                                  ((__TISEL__) == TIM_TIM17_TI1_SPDIF_FS)    ||\
+                                  ((__TISEL__) == TIM_TIM17_TI1_RCC_HSE1MHZ) ||\
+                                  ((__TISEL__) == TIM_TIM17_TI1_RCC_MCO1)    ||\
+                                  ((__TISEL__) == TIM_TIM23_TI4_GPIO)        ||\
+                                  ((__TISEL__) == TIM_TIM23_TI4_COMP1)       ||\
+                                  ((__TISEL__) == TIM_TIM23_TI4_COMP2)       ||\
+                                  ((__TISEL__) == TIM_TIM23_TI4_COMP1_COMP2) ||\
+                                  ((__TISEL__) == TIM_TIM24_TI1_GPIO)        ||\
+                                  ((__TISEL__) == TIM_TIM24_TI1_CAN_TMP)     ||\
+                                  ((__TISEL__) == TIM_TIM24_TI1_CAN_RTP)     ||\
+                                  ((__TISEL__) == TIM_TIM24_TI1_CAN_SOC))
+
+#define IS_TIM_REMAP(__RREMAP__)     (((__RREMAP__) == TIM_TIM1_ETR_GPIO)      ||\
+                                      ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD1) ||\
+                                      ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD2) ||\
+                                      ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD3) ||\
+                                      ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD1) ||\
+                                      ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD2) ||\
+                                      ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD3) ||\
+                                      ((__RREMAP__) == TIM_TIM1_ETR_COMP1)     ||\
+                                      ((__RREMAP__) == TIM_TIM1_ETR_COMP2)     ||\
+                                      ((__RREMAP__) == TIM_TIM8_ETR_GPIO)      ||\
+                                      ((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD1) ||\
+                                      ((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD2) ||\
+                                      ((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD3) ||\
+                                      ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD1) ||\
+                                      ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD2) ||\
+                                      ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD3) ||\
+                                      ((__RREMAP__) == TIM_TIM8_ETR_COMP1)     ||\
+                                      ((__RREMAP__) == TIM_TIM8_ETR_COMP2)     ||\
+                                      ((__RREMAP__) == TIM_TIM2_ETR_GPIO)      ||\
+                                      ((__RREMAP__) == TIM_TIM2_ETR_COMP1)     ||\
+                                      ((__RREMAP__) == TIM_TIM2_ETR_COMP2)     ||\
+                                      ((__RREMAP__) == TIM_TIM2_ETR_RCC_LSE)   ||\
+                                      ((__RREMAP__) == TIM_TIM2_ETR_SAI1_FSA)  ||\
+                                      ((__RREMAP__) == TIM_TIM2_ETR_SAI1_FSB)  ||\
+                                      ((__RREMAP__) == TIM_TIM3_ETR_GPIO)      ||\
+                                      ((__RREMAP__) == TIM_TIM3_ETR_COMP1)     ||\
+                                      ((__RREMAP__) == TIM_TIM5_ETR_GPIO)      ||\
+                                      ((__RREMAP__) == TIM_TIM5_ETR_SAI2_FSA)  ||\
+                                      ((__RREMAP__) == TIM_TIM5_ETR_SAI2_FSB)  ||\
+                                      ((__RREMAP__) == TIM_TIM23_ETR_GPIO)     ||\
+                                      ((__RREMAP__) == TIM_TIM23_ETR_COMP1)    ||\
+                                      ((__RREMAP__) == TIM_TIM23_ETR_COMP2)    ||\
+                                      ((__RREMAP__) == TIM_TIM24_ETR_GPIO)     ||\
+                                      ((__RREMAP__) == TIM_TIM24_ETR_SAI4_FSA) ||\
+                                      ((__RREMAP__) == TIM_TIM24_ETR_SAI4_FSB) ||\
+                                      ((__RREMAP__) == TIM_TIM24_ETR_SAI1_FSA) ||\
+                                      ((__RREMAP__) == TIM_TIM24_ETR_SAI1_FSB))
+
+/**
+  * @}
+  */
+/* End of private macro ------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
+  * @{
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
+  *  @brief    Timer Hall Sensor functions
+  * @{
+  */
+/*  Timer Hall Sensor functions  **********************************************/
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
+
+void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
+
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
+  *  @brief   Timer Complementary Output Compare functions
+  * @{
+  */
+/*  Timer Complementary Output Compare functions  *****************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
+  *  @brief    Timer Complementary PWM functions
+  * @{
+  */
+/*  Timer Complementary PWM functions  ****************************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
+  *  @brief    Timer Complementary One Pulse functions
+  * @{
+  */
+/*  Timer Complementary One Pulse functions  **********************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
+  *  @brief    Peripheral Control functions
+  * @{
+  */
+/* Extended Control functions  ************************************************/
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                              uint32_t  CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                                 uint32_t  CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                                  uint32_t  CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+                                                        TIM_MasterConfigTypeDef *sMasterConfig);
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
+                                                TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
+#if defined(TIM_BREAK_INPUT_SUPPORT)
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput,
+                                             TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
+#endif /* TIM_BREAK_INPUT_SUPPORT */
+HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
+HAL_StatusTypeDef  HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
+  * @brief    Extended Callbacks functions
+  * @{
+  */
+/* Extended Callback **********************************************************/
+void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
+  * @brief    Extended Peripheral State functions
+  * @{
+  */
+/* Extended Peripheral State functions  ***************************************/
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private functions----------------------------------------------------------*/
+/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions
+  * @{
+  */
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
+void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+/* End of private functions --------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32H7xx_HAL_TIM_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h
new file mode 100644
index 00000000..48eb8db3
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h
@@ -0,0 +1,1649 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_uart.h
+  * @author  MCD Application Team
+  * @brief   Header file of UART HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_UART_H
+#define STM32H7xx_HAL_UART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup UART
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UART_Exported_Types UART Exported Types
+  * @{
+  */
+
+/**
+  * @brief UART Init Structure definition
+  */
+typedef struct
+{
+  uint32_t BaudRate;                  /*!< This member configures the UART communication baud rate.
+                                           The baud rate register is computed using the following formula:
+                                           LPUART:
+                                           =======
+                                              Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate)))
+                                           where lpuart_ker_ck_pres is the UART input clock divided by a prescaler
+                                           UART:
+                                           =====
+                                           - If oversampling is 16 or in LIN mode,
+                                              Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate)))
+                                           - If oversampling is 8,
+                                              Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[15:4]
+                                              Baud Rate Register[3] =  0
+                                              Baud Rate Register[2:0] =  (((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[3:0]) >> 1
+                                           where uart_ker_ck_pres is the UART input clock divided by a prescaler */
+
+  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter can be a value of @ref UARTEx_Word_Length. */
+
+  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
+                                           This parameter can be a value of @ref UART_Stop_Bits. */
+
+  uint32_t Parity;                    /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref UART_Parity
+                                           @note When parity is enabled, the computed parity is inserted
+                                                 at the MSB position of the transmitted data (9th bit when
+                                                 the word length is set to 9 data bits; 8th bit when the
+                                                 word length is set to 8 data bits). */
+
+  uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref UART_Mode. */
+
+  uint32_t HwFlowCtl;                 /*!< Specifies whether the hardware flow control mode is enabled
+                                           or disabled.
+                                           This parameter can be a value of @ref UART_Hardware_Flow_Control. */
+
+  uint32_t OverSampling;              /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8).
+                                           This parameter can be a value of @ref UART_Over_Sampling. */
+
+  uint32_t OneBitSampling;            /*!< Specifies whether a single sample or three samples' majority vote is selected.
+                                           Selecting the single sample method increases the receiver tolerance to clock
+                                           deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */
+
+  uint32_t ClockPrescaler;            /*!< Specifies the prescaler value used to divide the UART clock source.
+                                           This parameter can be a value of @ref UART_ClockPrescaler. */
+
+} UART_InitTypeDef;
+
+/**
+  * @brief  UART Advanced Features initialization structure definition
+  */
+typedef struct
+{
+  uint32_t AdvFeatureInit;        /*!< Specifies which advanced UART features is initialized. Several
+                                       Advanced Features may be initialized at the same time .
+                                       This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type. */
+
+  uint32_t TxPinLevelInvert;      /*!< Specifies whether the TX pin active level is inverted.
+                                       This parameter can be a value of @ref UART_Tx_Inv. */
+
+  uint32_t RxPinLevelInvert;      /*!< Specifies whether the RX pin active level is inverted.
+                                       This parameter can be a value of @ref UART_Rx_Inv. */
+
+  uint32_t DataInvert;            /*!< Specifies whether data are inverted (positive/direct logic
+                                       vs negative/inverted logic).
+                                       This parameter can be a value of @ref UART_Data_Inv. */
+
+  uint32_t Swap;                  /*!< Specifies whether TX and RX pins are swapped.
+                                       This parameter can be a value of @ref UART_Rx_Tx_Swap. */
+
+  uint32_t OverrunDisable;        /*!< Specifies whether the reception overrun detection is disabled.
+                                       This parameter can be a value of @ref UART_Overrun_Disable. */
+
+  uint32_t DMADisableonRxError;   /*!< Specifies whether the DMA is disabled in case of reception error.
+                                       This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */
+
+  uint32_t AutoBaudRateEnable;    /*!< Specifies whether auto Baud rate detection is enabled.
+                                       This parameter can be a value of @ref UART_AutoBaudRate_Enable. */
+
+  uint32_t AutoBaudRateMode;      /*!< If auto Baud rate detection is enabled, specifies how the rate
+                                       detection is carried out.
+                                       This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */
+
+  uint32_t MSBFirst;              /*!< Specifies whether MSB is sent first on UART line.
+                                       This parameter can be a value of @ref UART_MSB_First. */
+} UART_AdvFeatureInitTypeDef;
+
+/**
+  * @brief HAL UART State definition
+  * @note  HAL UART State value is a combination of 2 different substates: gState and RxState (see @ref UART_State_Definition).
+  *        - gState contains UART state information related to global Handle management
+  *          and also information related to Tx operations.
+  *          gState value coding follow below described bitmap :
+  *          b7-b6  Error information
+  *             00 : No Error
+  *             01 : (Not Used)
+  *             10 : Timeout
+  *             11 : Error
+  *          b5     Peripheral initialization status
+  *             0  : Reset (Peripheral not initialized)
+  *             1  : Init done (Peripheral not initialized. HAL UART Init function already called)
+  *          b4-b3  (not used)
+  *             xx : Should be set to 00
+  *          b2     Intrinsic process state
+  *             0  : Ready
+  *             1  : Busy (Peripheral busy with some configuration or internal operations)
+  *          b1     (not used)
+  *             x  : Should be set to 0
+  *          b0     Tx state
+  *             0  : Ready (no Tx operation ongoing)
+  *             1  : Busy (Tx operation ongoing)
+  *        - RxState contains information related to Rx operations.
+  *          RxState value coding follow below described bitmap :
+  *          b7-b6  (not used)
+  *             xx : Should be set to 00
+  *          b5     Peripheral initialization status
+  *             0  : Reset (Peripheral not initialized)
+  *             1  : Init done (Peripheral not initialized)
+  *          b4-b2  (not used)
+  *            xxx : Should be set to 000
+  *          b1     Rx state
+  *             0  : Ready (no Rx operation ongoing)
+  *             1  : Busy (Rx operation ongoing)
+  *          b0     (not used)
+  *             x  : Should be set to 0.
+  */
+typedef uint32_t HAL_UART_StateTypeDef;
+
+/**
+  * @brief UART clock sources definition
+  */
+typedef enum
+{
+  UART_CLOCKSOURCE_D2PCLK1    = 0x00U,    /*!< Domain2 PCLK1 clock source */
+  UART_CLOCKSOURCE_D2PCLK2    = 0x01U,    /*!< Domain2 PCLK2 clock source */
+  UART_CLOCKSOURCE_D3PCLK1    = 0x02U,    /*!< Domain3 PCLK1 clock source */
+  UART_CLOCKSOURCE_PLL2       = 0x04U,    /*!< PLL2Q clock source         */
+  UART_CLOCKSOURCE_PLL3       = 0x08U,    /*!< PLL3Q clock source         */
+  UART_CLOCKSOURCE_HSI        = 0x10U,    /*!< HSI clock source           */
+  UART_CLOCKSOURCE_CSI        = 0x20U,    /*!< CSI clock source           */
+  UART_CLOCKSOURCE_LSE        = 0x40U,    /*!< LSE clock source           */
+  UART_CLOCKSOURCE_UNDEFINED  = 0x80U     /*!< Undefined clock source     */
+} UART_ClockSourceTypeDef;
+
+/**
+  * @brief  UART handle Structure definition
+  */
+typedef struct __UART_HandleTypeDef
+{
+  USART_TypeDef            *Instance;                /*!< UART registers base address        */
+
+  UART_InitTypeDef         Init;                     /*!< UART communication parameters      */
+
+  UART_AdvFeatureInitTypeDef AdvancedInit;           /*!< UART Advanced Features initialization parameters */
+
+  uint8_t                  *pTxBuffPtr;              /*!< Pointer to UART Tx transfer Buffer */
+
+  uint16_t                 TxXferSize;               /*!< UART Tx Transfer size              */
+
+  __IO uint16_t            TxXferCount;              /*!< UART Tx Transfer Counter           */
+
+  uint8_t                  *pRxBuffPtr;              /*!< Pointer to UART Rx transfer Buffer */
+
+  uint16_t                 RxXferSize;               /*!< UART Rx Transfer size              */
+
+  __IO uint16_t            RxXferCount;              /*!< UART Rx Transfer Counter           */
+
+  uint16_t                 Mask;                     /*!< UART Rx RDR register mask          */
+
+  uint32_t                 FifoMode;                 /*!< Specifies if the FIFO mode is being used.
+                                                          This parameter can be a value of @ref UARTEx_FIFO_mode. */
+
+  uint16_t                 NbRxDataToProcess;        /*!< Number of data to process during RX ISR execution */
+
+  uint16_t                 NbTxDataToProcess;        /*!< Number of data to process during TX ISR execution */
+
+  void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
+
+  void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */
+
+  DMA_HandleTypeDef        *hdmatx;                  /*!< UART Tx DMA Handle parameters      */
+
+  DMA_HandleTypeDef        *hdmarx;                  /*!< UART Rx DMA Handle parameters      */
+
+  HAL_LockTypeDef           Lock;                    /*!< Locking object                     */
+
+  __IO HAL_UART_StateTypeDef    gState;              /*!< UART state information related to global Handle management
+                                                          and also related to Tx operations.
+                                                          This parameter can be a value of @ref HAL_UART_StateTypeDef */
+
+  __IO HAL_UART_StateTypeDef    RxState;             /*!< UART state information related to Rx operations.
+                                                          This parameter can be a value of @ref HAL_UART_StateTypeDef */
+
+  __IO uint32_t                 ErrorCode;           /*!< UART Error code                    */
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Tx Half Complete Callback        */
+  void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Tx Complete Callback             */
+  void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Rx Half Complete Callback        */
+  void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Rx Complete Callback             */
+  void (* ErrorCallback)(struct __UART_HandleTypeDef *huart);             /*!< UART Error Callback                   */
+  void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart);         /*!< UART Abort Complete Callback          */
+  void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */
+  void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart);  /*!< UART Abort Receive Complete Callback  */
+  void (* WakeupCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Wakeup Callback                  */
+  void (* RxFifoFullCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Rx Fifo Full Callback            */
+  void (* TxFifoEmptyCallback)(struct __UART_HandleTypeDef *huart);       /*!< UART Tx Fifo Empty Callback           */
+
+  void (* MspInitCallback)(struct __UART_HandleTypeDef *huart);           /*!< UART Msp Init callback                */
+  void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart);         /*!< UART Msp DeInit callback              */
+#endif  /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+} UART_HandleTypeDef;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL UART Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_UART_TX_HALFCOMPLETE_CB_ID         = 0x00U,    /*!< UART Tx Half Complete Callback ID        */
+  HAL_UART_TX_COMPLETE_CB_ID             = 0x01U,    /*!< UART Tx Complete Callback ID             */
+  HAL_UART_RX_HALFCOMPLETE_CB_ID         = 0x02U,    /*!< UART Rx Half Complete Callback ID        */
+  HAL_UART_RX_COMPLETE_CB_ID             = 0x03U,    /*!< UART Rx Complete Callback ID             */
+  HAL_UART_ERROR_CB_ID                   = 0x04U,    /*!< UART Error Callback ID                   */
+  HAL_UART_ABORT_COMPLETE_CB_ID          = 0x05U,    /*!< UART Abort Complete Callback ID          */
+  HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U,    /*!< UART Abort Transmit Complete Callback ID */
+  HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID  = 0x07U,    /*!< UART Abort Receive Complete Callback ID  */
+  HAL_UART_WAKEUP_CB_ID                  = 0x08U,    /*!< UART Wakeup Callback ID                  */
+  HAL_UART_RX_FIFO_FULL_CB_ID            = 0x09U,    /*!< UART Rx Fifo Full Callback ID            */
+  HAL_UART_TX_FIFO_EMPTY_CB_ID           = 0x0AU,    /*!< UART Tx Fifo Empty Callback ID           */
+
+  HAL_UART_MSPINIT_CB_ID                 = 0x0BU,    /*!< UART MspInit callback ID                 */
+  HAL_UART_MSPDEINIT_CB_ID               = 0x0CU     /*!< UART MspDeInit callback ID               */
+
+} HAL_UART_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL UART Callback pointer definition
+  */
+typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart);  /*!< pointer to an UART callback function */
+
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UART_Exported_Constants UART Exported Constants
+  * @{
+  */
+
+/** @defgroup UART_State_Definition UART State Code Definition
+  * @{
+  */
+#define  HAL_UART_STATE_RESET         0x00000000U    /*!< Peripheral is not initialized
+                                                          Value is allowed for gState and RxState */
+#define  HAL_UART_STATE_READY         0x00000020U    /*!< Peripheral Initialized and ready for use
+                                                          Value is allowed for gState and RxState */
+#define  HAL_UART_STATE_BUSY          0x00000024U    /*!< an internal process is ongoing
+                                                          Value is allowed for gState only */
+#define  HAL_UART_STATE_BUSY_TX       0x00000021U    /*!< Data Transmission process is ongoing
+                                                          Value is allowed for gState only */
+#define  HAL_UART_STATE_BUSY_RX       0x00000022U    /*!< Data Reception process is ongoing
+                                                          Value is allowed for RxState only */
+#define  HAL_UART_STATE_BUSY_TX_RX    0x00000023U    /*!< Data Transmission and Reception process is ongoing
+                                                          Not to be used for neither gState nor RxState.
+                                                          Value is result of combination (Or) between gState and RxState values */
+#define  HAL_UART_STATE_TIMEOUT       0x000000A0U    /*!< Timeout state
+                                                          Value is allowed for gState only */
+#define  HAL_UART_STATE_ERROR         0x000000E0U    /*!< Error
+                                                          Value is allowed for gState only */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Error_Definition   UART Error Definition
+  * @{
+  */
+#define  HAL_UART_ERROR_NONE             ((uint32_t)0x00000000U)    /*!< No error                */
+#define  HAL_UART_ERROR_PE               ((uint32_t)0x00000001U)    /*!< Parity error            */
+#define  HAL_UART_ERROR_NE               ((uint32_t)0x00000002U)    /*!< Noise error             */
+#define  HAL_UART_ERROR_FE               ((uint32_t)0x00000004U)    /*!< Frame error             */
+#define  HAL_UART_ERROR_ORE              ((uint32_t)0x00000008U)    /*!< Overrun error           */
+#define  HAL_UART_ERROR_DMA              ((uint32_t)0x00000010U)    /*!< DMA transfer error      */
+#define  HAL_UART_ERROR_RTO              ((uint32_t)0x00000020U)    /*!< Receiver Timeout error  */
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+#define  HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U)    /*!< Invalid Callback error  */
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Stop_Bits   UART Number of Stop Bits
+  * @{
+  */
+#define UART_STOPBITS_0_5                    USART_CR2_STOP_0                     /*!< UART frame with 0.5 stop bit  */
+#define UART_STOPBITS_1                     0x00000000U                           /*!< UART frame with 1 stop bit    */
+#define UART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */
+#define UART_STOPBITS_2                      USART_CR2_STOP_1                     /*!< UART frame with 2 stop bits   */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Parity  UART Parity
+  * @{
+  */
+#define UART_PARITY_NONE                    0x00000000U                        /*!< No parity   */
+#define UART_PARITY_EVEN                    USART_CR1_PCE                      /*!< Even parity */
+#define UART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)     /*!< Odd parity  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
+  * @{
+  */
+#define UART_HWCONTROL_NONE                  0x00000000U                          /*!< No hardware control       */
+#define UART_HWCONTROL_RTS                   USART_CR3_RTSE                       /*!< Request To Send           */
+#define UART_HWCONTROL_CTS                   USART_CR3_CTSE                       /*!< Clear To Send             */
+#define UART_HWCONTROL_RTS_CTS               (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< Request and Clear To Send */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Mode UART Transfer Mode
+  * @{
+  */
+#define UART_MODE_RX                        USART_CR1_RE                    /*!< RX mode        */
+#define UART_MODE_TX                        USART_CR1_TE                    /*!< TX mode        */
+#define UART_MODE_TX_RX                     (USART_CR1_TE |USART_CR1_RE)    /*!< RX and TX mode */
+/**
+  * @}
+  */
+
+/** @defgroup UART_State  UART State
+  * @{
+  */
+#define UART_STATE_DISABLE                  0x00000000U         /*!< UART disabled  */
+#define UART_STATE_ENABLE                   USART_CR1_UE        /*!< UART enabled   */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Over_Sampling UART Over Sampling
+  * @{
+  */
+#define UART_OVERSAMPLING_16                0x00000000U         /*!< Oversampling by 16 */
+#define UART_OVERSAMPLING_8                 USART_CR1_OVER8     /*!< Oversampling by 8  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method
+  * @{
+  */
+#define UART_ONE_BIT_SAMPLE_DISABLE         0x00000000U         /*!< One-bit sampling disable */
+#define UART_ONE_BIT_SAMPLE_ENABLE          USART_CR3_ONEBIT    /*!< One-bit sampling enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_ClockPrescaler  UART Clock Prescaler
+  * @{
+  */
+#define UART_PRESCALER_DIV1    0x00000000U  /*!< fclk_pres = fclk     */
+#define UART_PRESCALER_DIV2    0x00000001U  /*!< fclk_pres = fclk/2   */
+#define UART_PRESCALER_DIV4    0x00000002U  /*!< fclk_pres = fclk/4   */
+#define UART_PRESCALER_DIV6    0x00000003U  /*!< fclk_pres = fclk/6   */
+#define UART_PRESCALER_DIV8    0x00000004U  /*!< fclk_pres = fclk/8   */
+#define UART_PRESCALER_DIV10   0x00000005U  /*!< fclk_pres = fclk/10  */
+#define UART_PRESCALER_DIV12   0x00000006U  /*!< fclk_pres = fclk/12  */
+#define UART_PRESCALER_DIV16   0x00000007U  /*!< fclk_pres = fclk/16  */
+#define UART_PRESCALER_DIV32   0x00000008U  /*!< fclk_pres = fclk/32  */
+#define UART_PRESCALER_DIV64   0x00000009U  /*!< fclk_pres = fclk/64  */
+#define UART_PRESCALER_DIV128  0x0000000AU  /*!< fclk_pres = fclk/128 */
+#define UART_PRESCALER_DIV256  0x0000000BU  /*!< fclk_pres = fclk/256 */
+/**
+  * @}
+  */
+
+/** @defgroup UART_AutoBaud_Rate_Mode    UART Advanced Feature AutoBaud Rate Mode
+  * @{
+  */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT    0x00000000U           /*!< Auto Baud rate detection on start bit            */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0   /*!< Auto Baud rate detection on falling edge         */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME   USART_CR2_ABRMODE_1   /*!< Auto Baud rate detection on 0x7F frame detection */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME   USART_CR2_ABRMODE     /*!< Auto Baud rate detection on 0x55 frame detection */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Receiver_Timeout UART Receiver Timeout
+  * @{
+  */
+#define UART_RECEIVER_TIMEOUT_DISABLE       0x00000000U                /*!< UART Receiver Timeout disable */
+#define UART_RECEIVER_TIMEOUT_ENABLE        USART_CR2_RTOEN            /*!< UART Receiver Timeout enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_LIN    UART Local Interconnection Network mode
+  * @{
+  */
+#define UART_LIN_DISABLE                    0x00000000U                /*!< Local Interconnect Network disable */
+#define UART_LIN_ENABLE                     USART_CR2_LINEN            /*!< Local Interconnect Network enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_LIN_Break_Detection  UART LIN Break Detection
+  * @{
+  */
+#define UART_LINBREAKDETECTLENGTH_10B       0x00000000U                /*!< LIN 10-bit break detection length */
+#define UART_LINBREAKDETECTLENGTH_11B       USART_CR2_LBDL             /*!< LIN 11-bit break detection length  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_DMA_Tx    UART DMA Tx
+  * @{
+  */
+#define UART_DMA_TX_DISABLE                 0x00000000U                /*!< UART DMA TX disabled */
+#define UART_DMA_TX_ENABLE                  USART_CR3_DMAT             /*!< UART DMA TX enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_DMA_Rx   UART DMA Rx
+  * @{
+  */
+#define UART_DMA_RX_DISABLE                 0x00000000U                 /*!< UART DMA RX disabled */
+#define UART_DMA_RX_ENABLE                  USART_CR3_DMAR              /*!< UART DMA RX enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Half_Duplex_Selection  UART Half Duplex Selection
+  * @{
+  */
+#define UART_HALF_DUPLEX_DISABLE            0x00000000U                 /*!< UART half-duplex disabled */
+#define UART_HALF_DUPLEX_ENABLE             USART_CR3_HDSEL             /*!< UART half-duplex enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_WakeUp_Methods   UART WakeUp Methods
+  * @{
+  */
+#define UART_WAKEUPMETHOD_IDLELINE          0x00000000U                 /*!< UART wake-up on idle line    */
+#define UART_WAKEUPMETHOD_ADDRESSMARK       USART_CR1_WAKE              /*!< UART wake-up on address mark */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Request_Parameters UART Request Parameters
+  * @{
+  */
+#define UART_AUTOBAUD_REQUEST               USART_RQR_ABRRQ        /*!< Auto-Baud Rate Request      */
+#define UART_SENDBREAK_REQUEST              USART_RQR_SBKRQ        /*!< Send Break Request          */
+#define UART_MUTE_MODE_REQUEST              USART_RQR_MMRQ         /*!< Mute Mode Request           */
+#define UART_RXDATA_FLUSH_REQUEST           USART_RQR_RXFRQ        /*!< Receive Data flush Request  */
+#define UART_TXDATA_FLUSH_REQUEST           USART_RQR_TXFRQ        /*!< Transmit data flush Request */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Advanced_Features_Initialization_Type  UART Advanced Feature Initialization Type
+  * @{
+  */
+#define UART_ADVFEATURE_NO_INIT                 0x00000000U          /*!< No advanced feature initialization       */
+#define UART_ADVFEATURE_TXINVERT_INIT           0x00000001U          /*!< TX pin active level inversion            */
+#define UART_ADVFEATURE_RXINVERT_INIT           0x00000002U          /*!< RX pin active level inversion            */
+#define UART_ADVFEATURE_DATAINVERT_INIT         0x00000004U          /*!< Binary data inversion                    */
+#define UART_ADVFEATURE_SWAP_INIT               0x00000008U          /*!< TX/RX pins swap                          */
+#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT   0x00000010U          /*!< RX overrun disable                       */
+#define UART_ADVFEATURE_DMADISABLEONERROR_INIT  0x00000020U          /*!< DMA disable on Reception Error           */
+#define UART_ADVFEATURE_AUTOBAUDRATE_INIT       0x00000040U          /*!< Auto Baud rate detection initialization  */
+#define UART_ADVFEATURE_MSBFIRST_INIT           0x00000080U          /*!< Most significant bit sent/received first */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion
+  * @{
+  */
+#define UART_ADVFEATURE_TXINV_DISABLE       0x00000000U             /*!< TX pin active level inversion disable */
+#define UART_ADVFEATURE_TXINV_ENABLE        USART_CR2_TXINV         /*!< TX pin active level inversion enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion
+  * @{
+  */
+#define UART_ADVFEATURE_RXINV_DISABLE       0x00000000U             /*!< RX pin active level inversion disable */
+#define UART_ADVFEATURE_RXINV_ENABLE        USART_CR2_RXINV         /*!< RX pin active level inversion enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Data_Inv  UART Advanced Feature Binary Data Inversion
+  * @{
+  */
+#define UART_ADVFEATURE_DATAINV_DISABLE     0x00000000U             /*!< Binary data inversion disable */
+#define UART_ADVFEATURE_DATAINV_ENABLE      USART_CR2_DATAINV       /*!< Binary data inversion enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap
+  * @{
+  */
+#define UART_ADVFEATURE_SWAP_DISABLE        0x00000000U             /*!< TX/RX pins swap disable */
+#define UART_ADVFEATURE_SWAP_ENABLE         USART_CR2_SWAP          /*!< TX/RX pins swap enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Overrun_Disable  UART Advanced Feature Overrun Disable
+  * @{
+  */
+#define UART_ADVFEATURE_OVERRUN_ENABLE      0x00000000U             /*!< RX overrun enable  */
+#define UART_ADVFEATURE_OVERRUN_DISABLE     USART_CR3_OVRDIS        /*!< RX overrun disable */
+/**
+  * @}
+  */
+
+/** @defgroup UART_AutoBaudRate_Enable  UART Advanced Feature Auto BaudRate Enable
+  * @{
+  */
+#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE   0x00000000U          /*!< RX Auto Baud rate detection enable  */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE    USART_CR2_ABREN      /*!< RX Auto Baud rate detection disable */
+/**
+  * @}
+  */
+
+/** @defgroup UART_DMA_Disable_on_Rx_Error   UART Advanced Feature DMA Disable On Rx Error
+  * @{
+  */
+#define UART_ADVFEATURE_DMA_ENABLEONRXERROR    0x00000000U          /*!< DMA enable on Reception Error  */
+#define UART_ADVFEATURE_DMA_DISABLEONRXERROR   USART_CR3_DDRE       /*!< DMA disable on Reception Error */
+/**
+  * @}
+  */
+
+/** @defgroup UART_MSB_First   UART Advanced Feature MSB First
+  * @{
+  */
+#define UART_ADVFEATURE_MSBFIRST_DISABLE    0x00000000U             /*!< Most significant bit sent/received first disable */
+#define UART_ADVFEATURE_MSBFIRST_ENABLE     USART_CR2_MSBFIRST      /*!< Most significant bit sent/received first enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Stop_Mode_Enable   UART Advanced Feature Stop Mode Enable
+  * @{
+  */
+#define UART_ADVFEATURE_STOPMODE_DISABLE    0x00000000U             /*!< UART stop mode disable */
+#define UART_ADVFEATURE_STOPMODE_ENABLE     USART_CR1_UESM          /*!< UART stop mode enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Mute_Mode   UART Advanced Feature Mute Mode Enable
+  * @{
+  */
+#define UART_ADVFEATURE_MUTEMODE_DISABLE    0x00000000U             /*!< UART mute mode disable */
+#define UART_ADVFEATURE_MUTEMODE_ENABLE     USART_CR1_MME           /*!< UART mute mode enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_CR2_ADDRESS_LSB_POS    UART Address-matching LSB Position In CR2 Register
+  * @{
+  */
+#define UART_CR2_ADDRESS_LSB_POS             24U                                /*!< UART address-matching LSB position in CR2 register */
+/**
+  * @}
+  */
+
+/** @defgroup UART_WakeUp_from_Stop_Selection   UART WakeUp From Stop Selection
+  * @{
+  */
+#define UART_WAKEUP_ON_ADDRESS              0x00000000U             /*!< UART wake-up on address                         */
+#define UART_WAKEUP_ON_STARTBIT             USART_CR3_WUS_1         /*!< UART wake-up on start bit                       */
+#define UART_WAKEUP_ON_READDATA_NONEMPTY    USART_CR3_WUS           /*!< UART wake-up on receive data register not empty or RXFIFO is not empty */
+/**
+  * @}
+  */
+
+/** @defgroup UART_DriverEnable_Polarity      UART DriverEnable Polarity
+  * @{
+  */
+#define UART_DE_POLARITY_HIGH               0x00000000U             /*!< Driver enable signal is active high */
+#define UART_DE_POLARITY_LOW                USART_CR3_DEP           /*!< Driver enable signal is active low  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS    UART Driver Enable Assertion Time LSB Position In CR1 Register
+  * @{
+  */
+#define UART_CR1_DEAT_ADDRESS_LSB_POS       21U      /*!< UART Driver Enable assertion time LSB position in CR1 register */
+/**
+  * @}
+  */
+
+/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS    UART Driver Enable DeAssertion Time LSB Position In CR1 Register
+  * @{
+  */
+#define UART_CR1_DEDT_ADDRESS_LSB_POS       16U      /*!< UART Driver Enable de-assertion time LSB position in CR1 register */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Interruption_Mask    UART Interruptions Flag Mask
+  * @{
+  */
+#define UART_IT_MASK                        0x001FU  /*!< UART interruptions flags mask */
+/**
+  * @}
+  */
+
+/** @defgroup UART_TimeOut_Value    UART polling-based communications time-out value
+  * @{
+  */
+#define HAL_UART_TIMEOUT_VALUE              0x1FFFFFFU  /*!< UART polling-based communications time-out value */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Flags     UART Status Flags
+  *        Elements values convention: 0xXXXX
+  *           - 0xXXXX  : Flag mask in the ISR register
+  * @{
+  */
+#define UART_FLAG_TXFT                      USART_ISR_TXFT          /*!< UART TXFIFO threshold flag                */
+#define UART_FLAG_RXFT                      USART_ISR_RXFT          /*!< UART RXFIFO threshold flag                */
+#define UART_FLAG_RXFF                      USART_ISR_RXFF          /*!< UART RXFIFO Full flag                     */
+#define UART_FLAG_TXFE                      USART_ISR_TXFE          /*!< UART TXFIFO Empty flag                    */
+#define UART_FLAG_REACK                     USART_ISR_REACK         /*!< UART receive enable acknowledge flag      */
+#define UART_FLAG_TEACK                     USART_ISR_TEACK         /*!< UART transmit enable acknowledge flag     */
+#define UART_FLAG_WUF                       USART_ISR_WUF           /*!< UART wake-up from stop mode flag          */
+#define UART_FLAG_RWU                       USART_ISR_RWU           /*!< UART receiver wake-up from mute mode flag */
+#define UART_FLAG_SBKF                      USART_ISR_SBKF          /*!< UART send break flag                      */
+#define UART_FLAG_CMF                       USART_ISR_CMF           /*!< UART character match flag                 */
+#define UART_FLAG_BUSY                      USART_ISR_BUSY          /*!< UART busy flag                            */
+#define UART_FLAG_ABRF                      USART_ISR_ABRF          /*!< UART auto Baud rate flag                  */
+#define UART_FLAG_ABRE                      USART_ISR_ABRE          /*!< UART auto Baud rate error                 */
+#define UART_FLAG_RTOF                      USART_ISR_RTOF          /*!< UART receiver timeout flag                */
+#define UART_FLAG_CTS                       USART_ISR_CTS           /*!< UART clear to send flag                   */
+#define UART_FLAG_CTSIF                     USART_ISR_CTSIF         /*!< UART clear to send interrupt flag         */
+#define UART_FLAG_LBDF                      USART_ISR_LBDF          /*!< UART LIN break detection flag             */
+#define UART_FLAG_TXE                       USART_ISR_TXE_TXFNF     /*!< UART transmit data register empty         */
+#define UART_FLAG_TXFNF                     USART_ISR_TXE_TXFNF     /*!< UART TXFIFO not full                      */
+#define UART_FLAG_TC                        USART_ISR_TC            /*!< UART transmission complete                */
+#define UART_FLAG_RXNE                      USART_ISR_RXNE_RXFNE    /*!< UART read data register not empty         */
+#define UART_FLAG_RXFNE                     USART_ISR_RXNE_RXFNE    /*!< UART RXFIFO not empty                     */
+#define UART_FLAG_IDLE                      USART_ISR_IDLE          /*!< UART idle flag                            */
+#define UART_FLAG_ORE                       USART_ISR_ORE           /*!< UART overrun error                        */
+#define UART_FLAG_NE                        USART_ISR_NE            /*!< UART noise error                          */
+#define UART_FLAG_FE                        USART_ISR_FE            /*!< UART frame error                          */
+#define UART_FLAG_PE                        USART_ISR_PE            /*!< UART parity error                         */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Interrupt_definition   UART Interrupts Definition
+  *        Elements values convention: 000ZZZZZ0XXYYYYYb
+  *           - YYYYY  : Interrupt source position in the XX register (5bits)
+  *           - XX  : Interrupt source register (2bits)
+  *                 - 01: CR1 register
+  *                 - 10: CR2 register
+  *                 - 11: CR3 register
+  *           - ZZZZZ  : Flag position in the ISR register(5bits)
+  *        Elements values convention: 000000000XXYYYYYb
+  *           - YYYYY  : Interrupt source position in the XX register (5bits)
+  *           - XX  : Interrupt source register (2bits)
+  *                 - 01: CR1 register
+  *                 - 10: CR2 register
+  *                 - 11: CR3 register
+  *        Elements values convention: 0000ZZZZ00000000b
+  *           - ZZZZ  : Flag position in the ISR register(4bits)
+  * @{
+  */
+#define UART_IT_PE                          0x0028U                  /*!< UART parity error interruption                 */
+#define UART_IT_TXE                         0x0727U                  /*!< UART transmit data register empty interruption */
+#define UART_IT_TXFNF                       0x0727U                  /*!< UART TX FIFO not full interruption             */
+#define UART_IT_TC                          0x0626U                  /*!< UART transmission complete interruption        */
+#define UART_IT_RXNE                        0x0525U                  /*!< UART read data register not empty interruption */
+#define UART_IT_RXFNE                       0x0525U                  /*!< UART RXFIFO not empty interruption             */
+#define UART_IT_IDLE                        0x0424U                  /*!< UART idle interruption                         */
+#define UART_IT_LBD                         0x0846U                  /*!< UART LIN break detection interruption          */
+#define UART_IT_CTS                         0x096AU                  /*!< UART CTS interruption                          */
+#define UART_IT_CM                          0x112EU                  /*!< UART character match interruption              */
+#define UART_IT_WUF                         0x1476U                  /*!< UART wake-up from stop mode interruption       */
+#define UART_IT_RXFF                        0x183FU                  /*!< UART RXFIFO full interruption                  */
+#define UART_IT_TXFE                        0x173EU                  /*!< UART TXFIFO empty interruption                 */
+#define UART_IT_RXFT                        0x1A7CU                  /*!< UART RXFIFO threshold reached interruption     */
+#define UART_IT_TXFT                        0x1B77U                  /*!< UART TXFIFO threshold reached interruption     */
+#define UART_IT_RTO                         0x0B3AU                  /*!< UART receiver timeout interruption             */
+
+#define UART_IT_ERR                         0x0060U                  /*!< UART error interruption         */
+
+#define UART_IT_ORE                         0x0300U                  /*!< UART overrun error interruption */
+#define UART_IT_NE                          0x0200U                  /*!< UART noise error interruption   */
+#define UART_IT_FE                          0x0100U                  /*!< UART frame error interruption   */
+/**
+  * @}
+  */
+
+/** @defgroup UART_IT_CLEAR_Flags  UART Interruption Clear Flags
+  * @{
+  */
+#define UART_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag           */
+#define UART_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag          */
+#define UART_CLEAR_NEF                       USART_ICR_NECF            /*!< Noise Error detected Clear Flag   */
+#define UART_CLEAR_OREF                      USART_ICR_ORECF           /*!< Overrun Error Clear Flag          */
+#define UART_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag     */
+#define UART_CLEAR_TXFECF                    USART_ICR_TXFECF          /*!< TXFIFO empty clear flag           */
+#define UART_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag  */
+#define UART_CLEAR_LBDF                      USART_ICR_LBDCF           /*!< LIN Break Detection Clear Flag    */
+#define UART_CLEAR_CTSF                      USART_ICR_CTSCF           /*!< CTS Interrupt Clear Flag          */
+#define UART_CLEAR_CMF                       USART_ICR_CMCF            /*!< Character Match Clear Flag        */
+#define UART_CLEAR_WUF                       USART_ICR_WUCF            /*!< Wake Up from stop mode Clear Flag */
+#define UART_CLEAR_RTOF                      USART_ICR_RTOCF           /*!< UART receiver timeout clear flag  */
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup UART_Exported_Macros UART Exported Macros
+  * @{
+  */
+
+/** @brief  Reset UART handle states.
+  * @param  __HANDLE__ UART handle.
+  * @retval None
+  */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
+                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
+                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
+                                                       (__HANDLE__)->MspInitCallback = NULL;             \
+                                                       (__HANDLE__)->MspDeInitCallback = NULL;           \
+                                                     } while(0U)
+#else
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
+                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
+                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
+                                                     } while(0U)
+#endif /*USE_HAL_UART_REGISTER_CALLBACKS */
+
+/** @brief  Flush the UART Data registers.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__)  \
+  do{                \
+    SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
+    SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
+  }  while(0U)
+
+/** @brief  Clear the specified UART pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg @ref UART_CLEAR_PEF      Parity Error Clear Flag
+  *            @arg @ref UART_CLEAR_FEF      Framing Error Clear Flag
+  *            @arg @ref UART_CLEAR_NEF      Noise detected Clear Flag
+  *            @arg @ref UART_CLEAR_OREF     Overrun Error Clear Flag
+  *            @arg @ref UART_CLEAR_IDLEF    IDLE line detected Clear Flag
+  *            @arg @ref UART_CLEAR_TXFECF   TXFIFO empty clear Flag
+  *            @arg @ref UART_CLEAR_TCF      Transmission Complete Clear Flag
+  *            @arg @ref UART_CLEAR_RTOF     Receiver Timeout clear flag
+  *            @arg @ref UART_CLEAR_LBDF     LIN Break Detection Clear Flag
+  *            @arg @ref UART_CLEAR_CTSF     CTS Interrupt Clear Flag
+  *            @arg @ref UART_CLEAR_CMF      Character Match Clear Flag
+  *            @arg @ref UART_CLEAR_WUF      Wake Up from stop mode Clear Flag
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief  Clear the UART PE pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
+
+/** @brief  Clear the UART FE pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
+
+/** @brief  Clear the UART NE pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__)  __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
+
+/** @brief  Clear the UART ORE pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
+
+/** @brief  Clear the UART IDLE pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
+
+/** @brief  Clear the UART TX FIFO empty clear flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_TXFECF(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF)
+
+/** @brief  Check whether the specified UART flag is set or not.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg @ref UART_FLAG_TXFT  TXFIFO threshold flag
+  *            @arg @ref UART_FLAG_RXFT  RXFIFO threshold flag
+  *            @arg @ref UART_FLAG_RXFF  RXFIFO Full flag
+  *            @arg @ref UART_FLAG_TXFE  TXFIFO Empty flag
+  *            @arg @ref UART_FLAG_REACK Receive enable acknowledge flag
+  *            @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag
+  *            @arg @ref UART_FLAG_WUF   Wake up from stop mode flag
+  *            @arg @ref UART_FLAG_RWU   Receiver wake up flag (if the UART in mute mode)
+  *            @arg @ref UART_FLAG_SBKF  Send Break flag
+  *            @arg @ref UART_FLAG_CMF   Character match flag
+  *            @arg @ref UART_FLAG_BUSY  Busy flag
+  *            @arg @ref UART_FLAG_ABRF  Auto Baud rate detection flag
+  *            @arg @ref UART_FLAG_ABRE  Auto Baud rate detection error flag
+  *            @arg @ref UART_FLAG_CTS   CTS Change flag
+  *            @arg @ref UART_FLAG_LBDF  LIN Break detection flag
+  *            @arg @ref UART_FLAG_TXE   Transmit data register empty flag
+  *            @arg @ref UART_FLAG_TXFNF UART TXFIFO not full flag
+  *            @arg @ref UART_FLAG_TC    Transmission Complete flag
+  *            @arg @ref UART_FLAG_RXNE  Receive data register not empty flag
+  *            @arg @ref UART_FLAG_RXFNE UART RXFIFO not empty flag
+  *            @arg @ref UART_FLAG_RTOF  Receiver Timeout flag
+  *            @arg @ref UART_FLAG_IDLE  Idle Line detection flag
+  *            @arg @ref UART_FLAG_ORE   Overrun Error flag
+  *            @arg @ref UART_FLAG_NE    Noise Error flag
+  *            @arg @ref UART_FLAG_FE    Framing Error flag
+  *            @arg @ref UART_FLAG_PE    Parity Error flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Enable the specified UART interrupt.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __INTERRUPT__ specifies the UART interrupt source to enable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt
+  *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt
+  *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt
+  *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt
+  *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt
+  *            @arg @ref UART_IT_CM    Character match interrupt
+  *            @arg @ref UART_IT_CTS   CTS change interrupt
+  *            @arg @ref UART_IT_LBD   LIN Break detection interrupt
+  *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt
+  *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
+  *            @arg @ref UART_IT_TC    Transmission complete interrupt
+  *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
+  *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
+  *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
+  *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
+  *            @arg @ref UART_IT_PE    Parity Error interrupt
+  *            @arg @ref UART_IT_ERR   Error interrupt (frame error, noise error, overrun error)
+  * @retval None
+  */
+#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
+                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
+                                                           ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))))
+
+
+/** @brief  Disable the specified UART interrupt.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __INTERRUPT__ specifies the UART interrupt source to disable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt
+  *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt
+  *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt
+  *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt
+  *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt
+  *            @arg @ref UART_IT_CM    Character match interrupt
+  *            @arg @ref UART_IT_CTS   CTS change interrupt
+  *            @arg @ref UART_IT_LBD   LIN Break detection interrupt
+  *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt
+  *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
+  *            @arg @ref UART_IT_TC    Transmission complete interrupt
+  *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
+  *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
+  *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
+  *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
+  *            @arg @ref UART_IT_PE    Parity Error interrupt
+  *            @arg @ref UART_IT_ERR   Error interrupt (Frame error, noise error, overrun error)
+  * @retval None
+  */
+#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
+                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
+                                                           ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))
+
+/** @brief  Check whether the specified UART interrupt has occurred or not.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __INTERRUPT__ specifies the UART interrupt to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt
+  *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt
+  *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt
+  *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt
+  *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt
+  *            @arg @ref UART_IT_CM    Character match interrupt
+  *            @arg @ref UART_IT_CTS   CTS change interrupt
+  *            @arg @ref UART_IT_LBD   LIN Break detection interrupt
+  *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt
+  *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
+  *            @arg @ref UART_IT_TC    Transmission complete interrupt
+  *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
+  *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
+  *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
+  *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
+  *            @arg @ref UART_IT_PE    Parity Error interrupt
+  *            @arg @ref UART_IT_ERR   Error interrupt (Frame error, noise error, overrun error)
+  * @retval The new state of __INTERRUPT__ (SET or RESET).
+  */
+#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
+                                                        & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET)
+
+/** @brief  Check whether the specified UART interrupt source is enabled or not.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __INTERRUPT__ specifies the UART interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt
+  *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt
+  *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt
+  *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt
+  *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt
+  *            @arg @ref UART_IT_CM    Character match interrupt
+  *            @arg @ref UART_IT_CTS   CTS change interrupt
+  *            @arg @ref UART_IT_LBD   LIN Break detection interrupt
+  *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt
+  *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
+  *            @arg @ref UART_IT_TC    Transmission complete interrupt
+  *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
+  *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
+  *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
+  *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
+  *            @arg @ref UART_IT_PE    Parity Error interrupt
+  *            @arg @ref UART_IT_ERR   Error interrupt (Frame error, noise error, overrun error)
+  * @retval The new state of __INTERRUPT__ (SET or RESET).
+  */
+#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ? (__HANDLE__)->Instance->CR1 : \
+                                                                (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \
+                                                                 (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK)))  != RESET) ? SET : RESET)
+
+/** @brief  Clear the specified UART ISR flag, in setting the proper ICR register flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
+  *                       to clear the corresponding interrupt
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_CLEAR_PEF    Parity Error Clear Flag
+  *            @arg @ref UART_CLEAR_FEF    Framing Error Clear Flag
+  *            @arg @ref UART_CLEAR_NEF    Noise detected Clear Flag
+  *            @arg @ref UART_CLEAR_OREF   Overrun Error Clear Flag
+  *            @arg @ref UART_CLEAR_IDLEF  IDLE line detected Clear Flag
+  *            @arg @ref UART_CLEAR_RTOF   Receiver timeout clear flag
+  *            @arg @ref UART_CLEAR_TXFECF TXFIFO empty Clear Flag
+  *            @arg @ref UART_CLEAR_TCF    Transmission Complete Clear Flag
+  *            @arg @ref UART_CLEAR_LBDF   LIN Break Detection Clear Flag
+  *            @arg @ref UART_CLEAR_CTSF   CTS Interrupt Clear Flag
+  *            @arg @ref UART_CLEAR_CMF    Character Match Clear Flag
+  *            @arg @ref UART_CLEAR_WUF    Wake Up from stop mode Clear Flag
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
+
+/** @brief  Set a specific UART request flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __REQ__ specifies the request flag to set
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request
+  *            @arg @ref UART_SENDBREAK_REQUEST Send Break Request
+  *            @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request
+  *            @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request
+  *            @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request
+  * @retval None
+  */
+#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
+
+/** @brief  Enable the UART one bit sample method.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief  Disable the UART one bit sample method.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
+
+/** @brief  Enable UART.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+
+/** @brief  Disable UART.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+
+/** @brief  Enable CTS flow control.
+  * @note   This macro allows to enable CTS hardware flow control for a given UART instance,
+  *         without need to call HAL_UART_Init() function.
+  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+  * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
+  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
+  *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
+  *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)        \
+  do{                                                      \
+    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \
+    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;        \
+  } while(0U)
+
+/** @brief  Disable CTS flow control.
+  * @note   This macro allows to disable CTS hardware flow control for a given UART instance,
+  *         without need to call HAL_UART_Init() function.
+  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+  * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
+  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
+  *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
+  *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)        \
+  do{                                                       \
+    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
+    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);      \
+  } while(0U)
+
+/** @brief  Enable RTS flow control.
+  * @note   This macro allows to enable RTS hardware flow control for a given UART instance,
+  *         without need to call HAL_UART_Init() function.
+  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+  * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
+  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
+  *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
+  *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)       \
+  do{                                                     \
+    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
+    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;       \
+  } while(0U)
+
+/** @brief  Disable RTS flow control.
+  * @note   This macro allows to disable RTS hardware flow control for a given UART instance,
+  *         without need to call HAL_UART_Init() function.
+  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+  * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
+  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
+  *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
+  *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)       \
+  do{                                                      \
+    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
+    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);     \
+  } while(0U)
+/**
+  * @}
+  */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup UART_Private_Macros   UART Private Macros
+  * @{
+  */
+/** @brief  Get UART clok division factor from clock prescaler value.
+  * @param  __CLOCKPRESCALER__ UART prescaler value.
+  * @retval UART clock division factor
+  */
+#define UART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \
+  (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1)   ? 1U :       \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2)   ? 2U :       \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4)   ? 4U :       \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6)   ? 6U :       \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8)   ? 8U :       \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10)  ? 10U :      \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12)  ? 12U :      \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16)  ? 16U :      \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32)  ? 32U :      \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64)  ? 64U :      \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U :     \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U)
+
+/** @brief  BRR division operation to set BRR register with LPUART.
+  * @param  __PCLK__ LPUART clock.
+  * @param  __BAUD__ Baud rate set by the user.
+  * @param  __CLOCKPRESCALER__ UART prescaler value.
+  * @retval Division result
+  */
+#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__)      ((uint32_t)(((((uint64_t)(__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*256U)\
+                                                                      + (uint32_t)((__BAUD__)/2U)) / (__BAUD__)))
+
+/** @brief  BRR division operation to set BRR register in 8-bit oversampling mode.
+  * @param  __PCLK__ UART clock.
+  * @param  __BAUD__ Baud rate set by the user.
+  * @param  __CLOCKPRESCALER__ UART prescaler value.
+  * @retval Division result
+  */
+#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)   (((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*2U)\
+                                                                       + ((__BAUD__)/2U)) / (__BAUD__))
+
+/** @brief  BRR division operation to set BRR register in 16-bit oversampling mode.
+  * @param  __PCLK__ UART clock.
+  * @param  __BAUD__ Baud rate set by the user.
+  * @param  __CLOCKPRESCALER__ UART prescaler value.
+  * @retval Division result
+  */
+#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__)  ((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))\
+                                                                       + ((__BAUD__)/2U)) / (__BAUD__))
+
+/** @brief  Check whether or not UART instance is Low Power UART.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval SET (instance is LPUART) or RESET (instance isn't LPUART)
+  */
+#define UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE((__HANDLE__)->Instance))
+
+/** @brief  Check UART Baud rate.
+  * @param  __BAUDRATE__ Baudrate specified by the user.
+  *         The maximum Baud Rate is derived from the maximum clock on H7 (i.e. 100 MHz)
+  *         divided by the smallest oversampling used on the USART (i.e. 8)
+  * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)
+  */
+#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 12500001U)
+
+/** @brief  Check UART assertion time.
+  * @param  __TIME__ 5-bit value assertion time.
+  * @retval Test result (TRUE or FALSE).
+  */
+#define IS_UART_ASSERTIONTIME(__TIME__)    ((__TIME__) <= 0x1FU)
+
+/** @brief  Check UART deassertion time.
+  * @param  __TIME__ 5-bit value deassertion time.
+  * @retval Test result (TRUE or FALSE).
+  */
+#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
+
+/**
+  * @brief Ensure that UART frame number of stop bits is valid.
+  * @param __STOPBITS__ UART frame number of stop bits.
+  * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
+  */
+#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \
+                                        ((__STOPBITS__) == UART_STOPBITS_1)   || \
+                                        ((__STOPBITS__) == UART_STOPBITS_1_5) || \
+                                        ((__STOPBITS__) == UART_STOPBITS_2))
+
+/**
+  * @brief Ensure that LPUART frame number of stop bits is valid.
+  * @param __STOPBITS__ LPUART frame number of stop bits.
+  * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
+  */
+#define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \
+                                          ((__STOPBITS__) == UART_STOPBITS_2))
+
+/**
+  * @brief Ensure that UART frame parity is valid.
+  * @param __PARITY__ UART frame parity.
+  * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
+  */
+#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \
+                                    ((__PARITY__) == UART_PARITY_EVEN) || \
+                                    ((__PARITY__) == UART_PARITY_ODD))
+
+/**
+  * @brief Ensure that UART hardware flow control is valid.
+  * @param __CONTROL__ UART hardware flow control.
+  * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)
+  */
+#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\
+  (((__CONTROL__) == UART_HWCONTROL_NONE) || \
+   ((__CONTROL__) == UART_HWCONTROL_RTS)  || \
+   ((__CONTROL__) == UART_HWCONTROL_CTS)  || \
+   ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))
+
+/**
+  * @brief Ensure that UART communication mode is valid.
+  * @param __MODE__ UART communication mode.
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */
+#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
+
+/**
+  * @brief Ensure that UART state is valid.
+  * @param __STATE__ UART state.
+  * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
+  */
+#define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \
+                                  ((__STATE__) == UART_STATE_ENABLE))
+
+/**
+  * @brief Ensure that UART oversampling is valid.
+  * @param __SAMPLING__ UART oversampling.
+  * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
+  */
+#define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \
+                                            ((__SAMPLING__) == UART_OVERSAMPLING_8))
+
+/**
+  * @brief Ensure that UART frame sampling is valid.
+  * @param __ONEBIT__ UART frame sampling.
+  * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
+  */
+#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \
+                                            ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE))
+
+/**
+  * @brief Ensure that UART auto Baud rate detection mode is valid.
+  * @param __MODE__ UART auto Baud rate detection mode.
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__)  (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT)    || \
+                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \
+                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME)   || \
+                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))
+
+/**
+  * @brief Ensure that UART receiver timeout setting is valid.
+  * @param __TIMEOUT__ UART receiver timeout setting.
+  * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
+  */
+#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__)  (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
+                                                ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))
+
+/** @brief  Check the receiver timeout value.
+  * @note   The maximum UART receiver timeout value is 0xFFFFFF.
+  * @param  __TIMEOUTVALUE__ receiver timeout value.
+  * @retval Test result (TRUE or FALSE)
+  */
+#define IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__)  ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
+
+/**
+  * @brief Ensure that UART LIN state is valid.
+  * @param __LIN__ UART LIN state.
+  * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid)
+  */
+#define IS_UART_LIN(__LIN__)        (((__LIN__) == UART_LIN_DISABLE) || \
+                                     ((__LIN__) == UART_LIN_ENABLE))
+
+/**
+  * @brief Ensure that UART LIN break detection length is valid.
+  * @param __LENGTH__ UART LIN break detection length.
+  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+  */
+#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \
+                                                     ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))
+
+/**
+  * @brief Ensure that UART DMA TX state is valid.
+  * @param __DMATX__ UART DMA TX state.
+  * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
+  */
+#define IS_UART_DMA_TX(__DMATX__)     (((__DMATX__) == UART_DMA_TX_DISABLE) || \
+                                       ((__DMATX__) == UART_DMA_TX_ENABLE))
+
+/**
+  * @brief Ensure that UART DMA RX state is valid.
+  * @param __DMARX__ UART DMA RX state.
+  * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
+  */
+#define IS_UART_DMA_RX(__DMARX__)     (((__DMARX__) == UART_DMA_RX_DISABLE) || \
+                                       ((__DMARX__) == UART_DMA_RX_ENABLE))
+
+/**
+  * @brief Ensure that UART half-duplex state is valid.
+  * @param __HDSEL__ UART half-duplex state.
+  * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid)
+  */
+#define IS_UART_HALF_DUPLEX(__HDSEL__)     (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \
+                                            ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE))
+
+/**
+  * @brief Ensure that UART wake-up method is valid.
+  * @param __WAKEUP__ UART wake-up method .
+  * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid)
+  */
+#define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \
+                                          ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK))
+
+/**
+  * @brief Ensure that UART request parameter is valid.
+  * @param __PARAM__ UART request parameter.
+  * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
+  */
+#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST)     || \
+                                              ((__PARAM__) == UART_SENDBREAK_REQUEST)    || \
+                                              ((__PARAM__) == UART_MUTE_MODE_REQUEST)    || \
+                                              ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \
+                                              ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))
+
+/**
+  * @brief Ensure that UART advanced features initialization is valid.
+  * @param __INIT__ UART advanced features initialization.
+  * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_INIT(__INIT__)   ((__INIT__) <= (UART_ADVFEATURE_NO_INIT                | \
+                                                            UART_ADVFEATURE_TXINVERT_INIT          | \
+                                                            UART_ADVFEATURE_RXINVERT_INIT          | \
+                                                            UART_ADVFEATURE_DATAINVERT_INIT        | \
+                                                            UART_ADVFEATURE_SWAP_INIT              | \
+                                                            UART_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \
+                                                            UART_ADVFEATURE_DMADISABLEONERROR_INIT | \
+                                                            UART_ADVFEATURE_AUTOBAUDRATE_INIT      | \
+                                                            UART_ADVFEATURE_MSBFIRST_INIT))
+
+/**
+  * @brief Ensure that UART frame TX inversion setting is valid.
+  * @param __TXINV__ UART frame TX inversion setting.
+  * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \
+                                             ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE))
+
+/**
+  * @brief Ensure that UART frame RX inversion setting is valid.
+  * @param __RXINV__ UART frame RX inversion setting.
+  * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \
+                                             ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE))
+
+/**
+  * @brief Ensure that UART frame data inversion setting is valid.
+  * @param __DATAINV__ UART frame data inversion setting.
+  * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \
+                                                 ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE))
+
+/**
+  * @brief Ensure that UART frame RX/TX pins swap setting is valid.
+  * @param __SWAP__ UART frame RX/TX pins swap setting.
+  * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \
+                                           ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE))
+
+/**
+  * @brief Ensure that UART frame overrun setting is valid.
+  * @param __OVERRUN__ UART frame overrun setting.
+  * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
+  */
+#define IS_UART_OVERRUN(__OVERRUN__)     (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \
+                                          ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE))
+
+/**
+  * @brief Ensure that UART auto Baud rate state is valid.
+  * @param __AUTOBAUDRATE__ UART auto Baud rate state.
+  * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__)  (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
+                                                            ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
+
+/**
+  * @brief Ensure that UART DMA enabling or disabling on error setting is valid.
+  * @param __DMA__ UART DMA enabling or disabling on error setting.
+  * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__)  (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
+                                                   ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))
+
+/**
+  * @brief Ensure that UART frame MSB first setting is valid.
+  * @param __MSBFIRST__ UART frame MSB first setting.
+  * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
+                                                   ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))
+
+/**
+  * @brief Ensure that UART stop mode state is valid.
+  * @param __STOPMODE__ UART stop mode state.
+  * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \
+                                                   ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))
+
+/**
+  * @brief Ensure that UART mute mode state is valid.
+  * @param __MUTE__ UART mute mode state.
+  * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid)
+  */
+#define IS_UART_MUTE_MODE(__MUTE__)       (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
+                                           ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))
+
+/**
+  * @brief Ensure that UART wake-up selection is valid.
+  * @param __WAKE__ UART wake-up selection.
+  * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)
+  */
+#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS)           || \
+                                            ((__WAKE__) == UART_WAKEUP_ON_STARTBIT)          || \
+                                            ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY))
+
+/**
+  * @brief Ensure that UART driver enable polarity is valid.
+  * @param __POLARITY__ UART driver enable polarity.
+  * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)
+  */
+#define IS_UART_DE_POLARITY(__POLARITY__)    (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \
+                                              ((__POLARITY__) == UART_DE_POLARITY_LOW))
+
+/**
+  * @brief Ensure that UART Prescaler is valid.
+  * @param __CLOCKPRESCALER__ UART Prescaler value.
+  * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
+  */
+#define IS_UART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1)   || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2)   || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4)   || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6)   || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8)   || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10)  || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12)  || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16)  || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32)  || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64)  || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256))
+
+/**
+  * @}
+  */
+
+/* Include UART HAL Extended module */
+#include "stm32h7xx_hal_uart_ex.h"
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UART_Exported_Functions UART Exported Functions
+  * @{
+  */
+
+/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
+HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart);
+void HAL_UART_MspInit(UART_HandleTypeDef *huart);
+void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
+                                            pUART_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @addtogroup UART_Exported_Functions_Group2 IO operation functions
+  * @{
+  */
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);
+
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
+void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);
+
+/**
+  * @}
+  */
+
+/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions
+  * @{
+  */
+
+/* Peripheral Control functions  ************************************************/
+void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue);
+HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart);
+
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);
+void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
+
+/**
+  * @}
+  */
+
+/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions
+  * @{
+  */
+
+/* Peripheral State and Errors functions  **************************************************/
+HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
+uint32_t              HAL_UART_GetError(UART_HandleTypeDef *huart);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions -----------------------------------------------------------*/
+/** @addtogroup UART_Private_Functions UART Private Functions
+  * @{
+  */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
+                                              uint32_t Tickstart, uint32_t Timeout);
+void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_UART_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
new file mode 100644
index 00000000..bad4a667
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
@@ -0,0 +1,864 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_uart_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of UART HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_UART_EX_H
+#define STM32H7xx_HAL_UART_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup UARTEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UARTEx_Exported_Types UARTEx Exported Types
+  * @{
+  */
+
+/**
+  * @brief  UART wake up from stop mode parameters
+  */
+typedef struct
+{
+  uint32_t WakeUpEvent;        /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF).
+                                    This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.
+                                    If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must
+                                    be filled up. */
+
+  uint16_t AddressLength;      /*!< Specifies whether the address is 4 or 7-bit long.
+                                    This parameter can be a value of @ref UARTEx_WakeUp_Address_Length.  */
+
+  uint8_t Address;             /*!< UART/USART node address (7-bit long max). */
+} UART_WakeUpTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
+  * @{
+  */
+
+/** @defgroup UARTEx_Word_Length UARTEx Word Length
+  * @{
+  */
+#define UART_WORDLENGTH_7B          USART_CR1_M1   /*!< 7-bit long UART frame */
+#define UART_WORDLENGTH_8B          0x00000000U    /*!< 8-bit long UART frame */
+#define UART_WORDLENGTH_9B          USART_CR1_M0   /*!< 9-bit long UART frame */
+/**
+  * @}
+  */
+
+/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length
+  * @{
+  */
+#define UART_ADDRESS_DETECT_4B      0x00000000U      /*!< 4-bit long wake-up address */
+#define UART_ADDRESS_DETECT_7B      USART_CR2_ADDM7  /*!< 7-bit long wake-up address */
+/**
+  * @}
+  */
+
+/** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode
+  * @brief    UART FIFO mode
+  * @{
+  */
+#define UART_FIFOMODE_DISABLE       0x00000000U       /*!< FIFO mode disable */
+#define UART_FIFOMODE_ENABLE        USART_CR1_FIFOEN  /*!< FIFO mode enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level
+  * @brief    UART TXFIFO threshold level
+  * @{
+  */
+#define UART_TXFIFO_THRESHOLD_1_8   0x00000000U                               /*!< TXFIFO reaches 1/8 of its depth */
+#define UART_TXFIFO_THRESHOLD_1_4   USART_CR3_TXFTCFG_0                       /*!< TXFIFO reaches 1/4 of its depth */
+#define UART_TXFIFO_THRESHOLD_1_2   USART_CR3_TXFTCFG_1                       /*!< TXFIFO reaches 1/2 of its depth */
+#define UART_TXFIFO_THRESHOLD_3_4   (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */
+#define UART_TXFIFO_THRESHOLD_7_8   USART_CR3_TXFTCFG_2                       /*!< TXFIFO reaches 7/8 of its depth */
+#define UART_TXFIFO_THRESHOLD_8_8   (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty            */
+/**
+  * @}
+  */
+
+/** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level
+  * @brief    UART RXFIFO threshold level
+  * @{
+  */
+#define UART_RXFIFO_THRESHOLD_1_8   0x00000000U                               /*!< RXFIFO FIFO reaches 1/8 of its depth */
+#define UART_RXFIFO_THRESHOLD_1_4   USART_CR3_RXFTCFG_0                       /*!< RXFIFO FIFO reaches 1/4 of its depth */
+#define UART_RXFIFO_THRESHOLD_1_2   USART_CR3_RXFTCFG_1                       /*!< RXFIFO FIFO reaches 1/2 of its depth */
+#define UART_RXFIFO_THRESHOLD_3_4   (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */
+#define UART_RXFIFO_THRESHOLD_7_8   USART_CR3_RXFTCFG_2                       /*!< RXFIFO FIFO reaches 7/8 of its depth */
+#define UART_RXFIFO_THRESHOLD_8_8   (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full             */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UARTEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup UARTEx_Exported_Functions_Group1
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
+                                   uint32_t DeassertionTime);
+
+/**
+  * @}
+  */
+
+/** @addtogroup UARTEx_Exported_Functions_Group2
+  * @{
+  */
+
+void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
+
+void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart);
+void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart);
+
+/**
+  * @}
+  */
+
+/** @addtogroup UARTEx_Exported_Functions_Group3
+  * @{
+  */
+
+/* Peripheral Control functions  **********************************************/
+HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
+HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
+
+HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
+
+HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
+HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup UARTEx_Private_Macros UARTEx Private Macros
+  * @{
+  */
+
+/** @brief  Report the UART clock source.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __CLOCKSOURCE__ output variable.
+  * @retval UART clocking source, written in __CLOCKSOURCE__.
+  */
+#if defined(UART9) && defined(USART10)
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                        \
+    if((__HANDLE__)->Instance == USART1)                      \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART1_SOURCE())                   \
+      {                                                       \
+        case RCC_USART1CLKSOURCE_D2PCLK2:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2;       \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_PLL2:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_PLL3:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_CSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART2)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART2_SOURCE())                   \
+      {                                                       \
+        case RCC_USART2CLKSOURCE_D2PCLK1:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_PLL2:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_PLL3:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_CSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART3)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART3_SOURCE())                   \
+      {                                                       \
+        case RCC_USART3CLKSOURCE_D2PCLK1:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_PLL2:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_PLL3:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_CSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == UART4)                  \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART4_SOURCE())                    \
+      {                                                       \
+        case RCC_UART4CLKSOURCE_D2PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_PLL2:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_PLL3:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if ((__HANDLE__)->Instance == UART5)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART5_SOURCE())                    \
+      {                                                       \
+        case RCC_UART5CLKSOURCE_D2PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_PLL2:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_PLL3:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART6)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART6_SOURCE())                   \
+      {                                                       \
+        case RCC_USART6CLKSOURCE_D2PCLK2:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2;       \
+          break;                                              \
+        case RCC_USART6CLKSOURCE_PLL2:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_USART6CLKSOURCE_PLL3:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_USART6CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART6CLKSOURCE_CSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_USART6CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == UART7)                  \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART7_SOURCE())                    \
+      {                                                       \
+        case RCC_UART7CLKSOURCE_D2PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_UART7CLKSOURCE_PLL2:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_UART7CLKSOURCE_PLL3:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_UART7CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART7CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_UART7CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == UART8)                  \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART8_SOURCE())                    \
+      {                                                       \
+        case RCC_UART8CLKSOURCE_D2PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_UART8CLKSOURCE_PLL2:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_UART8CLKSOURCE_PLL3:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_UART8CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART8CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_UART8CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == UART9)                  \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART9_SOURCE())                    \
+      {                                                       \
+        case RCC_UART9CLKSOURCE_D2PCLK2:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2;       \
+          break;                                              \
+        case RCC_UART9CLKSOURCE_PLL2:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_UART9CLKSOURCE_PLL3:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_UART9CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART9CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_UART9CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART10)                \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART10_SOURCE())                  \
+      {                                                       \
+        case RCC_USART10CLKSOURCE_D2PCLK2:                    \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2;       \
+          break;                                              \
+        case RCC_USART10CLKSOURCE_PLL2:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_USART10CLKSOURCE_PLL3:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_USART10CLKSOURCE_HSI:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART10CLKSOURCE_CSI:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_USART10CLKSOURCE_LSE:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == LPUART1)                \
+    {                                                         \
+      switch(__HAL_RCC_GET_LPUART1_SOURCE())                  \
+      {                                                       \
+        case RCC_LPUART1CLKSOURCE_D3PCLK1:                    \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D3PCLK1;       \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_PLL2:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_PLL3:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_HSI:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_CSI:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_LSE:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else                                                      \
+    {                                                         \
+      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \
+    }                                                         \
+  } while(0U)
+#else
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                        \
+    if((__HANDLE__)->Instance == USART1)                      \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART1_SOURCE())                   \
+      {                                                       \
+        case RCC_USART1CLKSOURCE_D2PCLK2:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2;       \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_PLL2:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_PLL3:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_CSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART2)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART2_SOURCE())                   \
+      {                                                       \
+        case RCC_USART2CLKSOURCE_D2PCLK1:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_PLL2:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_PLL3:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_CSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART3)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART3_SOURCE())                   \
+      {                                                       \
+        case RCC_USART3CLKSOURCE_D2PCLK1:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_PLL2:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_PLL3:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_CSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == UART4)                  \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART4_SOURCE())                    \
+      {                                                       \
+        case RCC_UART4CLKSOURCE_D2PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_PLL2:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_PLL3:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if ((__HANDLE__)->Instance == UART5)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART5_SOURCE())                    \
+      {                                                       \
+        case RCC_UART5CLKSOURCE_D2PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_PLL2:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_PLL3:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART6)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART6_SOURCE())                   \
+      {                                                       \
+        case RCC_USART6CLKSOURCE_D2PCLK2:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2;       \
+          break;                                              \
+        case RCC_USART6CLKSOURCE_PLL2:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_USART6CLKSOURCE_PLL3:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_USART6CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART6CLKSOURCE_CSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_USART6CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == UART7)                  \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART7_SOURCE())                    \
+      {                                                       \
+        case RCC_UART7CLKSOURCE_D2PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_UART7CLKSOURCE_PLL2:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_UART7CLKSOURCE_PLL3:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_UART7CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART7CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_UART7CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == UART8)                  \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART8_SOURCE())                    \
+      {                                                       \
+        case RCC_UART8CLKSOURCE_D2PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_UART8CLKSOURCE_PLL2:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_UART8CLKSOURCE_PLL3:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_UART8CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART8CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_UART8CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == LPUART1)                \
+    {                                                         \
+      switch(__HAL_RCC_GET_LPUART1_SOURCE())                  \
+      {                                                       \
+        case RCC_LPUART1CLKSOURCE_D3PCLK1:                    \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D3PCLK1;       \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_PLL2:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_PLL3:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_HSI:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_CSI:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_LSE:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else                                                      \
+    {                                                         \
+      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \
+    }                                                         \
+  } while(0U)
+#endif  /* UART9 && USART10 */
+
+/** @brief  Report the UART mask to apply to retrieve the received data
+  *         according to the word length and to the parity bits activation.
+  * @note   If PCE = 1, the parity bit is not included in the data extracted
+  *         by the reception API().
+  *         This masking operation is not carried out in the case of
+  *         DMA transfers.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.
+  */
+#define UART_MASK_COMPUTATION(__HANDLE__)                             \
+  do {                                                                \
+    if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B)          \
+    {                                                                 \
+      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x01FFU ;                                \
+      }                                                               \
+      else                                                            \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x00FFU ;                                \
+      }                                                               \
+    }                                                                 \
+    else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B)     \
+    {                                                                 \
+      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x00FFU ;                                \
+      }                                                               \
+      else                                                            \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x007FU ;                                \
+      }                                                               \
+    }                                                                 \
+    else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B)     \
+    {                                                                 \
+      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x007FU ;                                \
+      }                                                               \
+      else                                                            \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x003FU ;                                \
+      }                                                               \
+    }                                                                 \
+    else                                                              \
+    {                                                                 \
+      (__HANDLE__)->Mask = 0x0000U;                                   \
+    }                                                                 \
+  } while(0U)
+
+/**
+  * @brief Ensure that UART frame length is valid.
+  * @param __LENGTH__ UART frame length.
+  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+  */
+#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \
+                                         ((__LENGTH__) == UART_WORDLENGTH_8B) || \
+                                         ((__LENGTH__) == UART_WORDLENGTH_9B))
+
+/**
+  * @brief Ensure that UART wake-up address length is valid.
+  * @param __ADDRESS__ UART wake-up address length.
+  * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
+  */
+#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
+                                                   ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
+
+/**
+  * @brief Ensure that UART TXFIFO threshold level is valid.
+  * @param __THRESHOLD__ UART TXFIFO threshold level.
+  * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
+  */
+#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \
+                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \
+                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \
+                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \
+                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \
+                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8))
+
+/**
+  * @brief Ensure that UART RXFIFO threshold level is valid.
+  * @param __THRESHOLD__ UART RXFIFO threshold level.
+  * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
+  */
+#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \
+                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \
+                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \
+                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \
+                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \
+                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8))
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_UART_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c
new file mode 100644
index 00000000..3e92312e
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c
@@ -0,0 +1,1276 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal.c
+  * @author  MCD Application Team
+  * @brief   HAL module driver.
+  *          This is the common part of the HAL initialization
+  *
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The common HAL driver contains a set of generic and common APIs that can be
+    used by the PPP peripheral drivers and the user to start using the HAL.
+    [..]
+    The HAL contains two APIs' categories:
+         (+) Common HAL APIs
+         (+) Services HAL APIs
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup HAL  HAL
+  * @brief HAL module driver.
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/**
+ * @brief STM32H7xx HAL Driver version number V1.8.0
+   */
+#define __STM32H7xx_HAL_VERSION_MAIN   (0x01UL) /*!< [31:24] main version */
+#define __STM32H7xx_HAL_VERSION_SUB1   (0x08UL) /*!< [23:16] sub1 version */
+#define __STM32H7xx_HAL_VERSION_SUB2   (0x00UL) /*!< [15:8]  sub2 version */
+#define __STM32H7xx_HAL_VERSION_RC     (0x00UL) /*!< [7:0]  release candidate */
+#define __STM32H7xx_HAL_VERSION         ((__STM32H7xx_HAL_VERSION_MAIN << 24)\
+                                        |(__STM32H7xx_HAL_VERSION_SUB1 << 16)\
+                                        |(__STM32H7xx_HAL_VERSION_SUB2 << 8 )\
+                                        |(__STM32H7xx_HAL_VERSION_RC))
+
+#define IDCODE_DEVID_MASK    ((uint32_t)0x00000FFF)
+#define VREFBUF_TIMEOUT_VALUE     (uint32_t)10   /* 10 ms  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Exported variables --------------------------------------------------------*/
+
+/** @defgroup HAL_Exported_Variables HAL Exported Variables
+  * @{
+  */
+__IO uint32_t uwTick;
+uint32_t uwTickPrio   = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
+HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT;  /* 1KHz */
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup HAL_Private_Functions  HAL Private Functions
+  * @{
+  */
+
+/** @defgroup HAL_Group1 Initialization and de-initialization Functions
+ *  @brief    Initialization and de-initialization functions
+ *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initializes the Flash interface the NVIC allocation and initial clock
+          configuration. It initializes the systick also when timeout is needed
+          and the backup domain when enabled.
+      (+) De-Initializes common part of the HAL.
+      (+) Configure The time base source to have 1ms time base with a dedicated
+          Tick interrupt priority.
+        (++) SysTick timer is used by default as source of time base, but user
+             can eventually implement his proper time base source (a general purpose
+             timer for example or other time source), keeping in mind that Time base
+             duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
+             handled in milliseconds basis.
+        (++) Time base configuration function (HAL_InitTick ()) is called automatically
+             at the beginning of the program after reset by HAL_Init() or at any time
+             when clock is configured, by HAL_RCC_ClockConfig().
+        (++) Source of time base is configured  to generate interrupts at regular
+             time intervals. Care must be taken if HAL_Delay() is called from a
+             peripheral ISR process, the Tick interrupt line must have higher priority
+            (numerically lower) than the peripheral interrupt. Otherwise the caller
+            ISR process will be blocked.
+       (++) functions affecting time base configurations are declared as __weak
+             to make  override possible  in case of other  implementations in user file.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function is used to initialize the HAL Library; it must be the first
+  *         instruction to be executed in the main program (before to call any other
+  *         HAL function), it performs the following:
+  *           Configures the SysTick to generate an interrupt each 1 millisecond,
+  *           which is clocked by the HSI (at this stage, the clock is not yet
+  *           configured and thus the system is running from the internal HSI at 16 MHz).
+  *           Set NVIC Group Priority to 4.
+  *           Calls the HAL_MspInit() callback function defined in user file
+  *           "stm32h7xx_hal_msp.c" to do the global low level hardware initialization
+  *
+  * @note   SysTick is used as time base for the HAL_Delay() function, the application
+  *         need to ensure that the SysTick time base is always set to 1 millisecond
+  *         to have correct HAL operation.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_Init(void)
+{
+
+uint32_t common_system_clock;
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+   /* Configure Cortex-M4 Instruction cache through ART accelerator */
+   __HAL_RCC_ART_CLK_ENABLE();                   /* Enable the Cortex-M4 ART Clock */
+   __HAL_ART_CONFIG_BASE_ADDRESS(0x08100000UL);  /* Configure the Cortex-M4 ART Base address to the Flash Bank 2 : */
+   __HAL_ART_ENABLE();                           /* Enable the Cortex-M4 ART */
+#endif /* DUAL_CORE &&  CORE_CM4 */
+
+  /* Set Interrupt Group Priority */
+  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+  /* Update the SystemCoreClock global variable */
+#if defined(RCC_D1CFGR_D1CPRE)
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
+#else
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
+#endif
+
+  /* Update the SystemD2Clock global variable */
+#if defined(RCC_D1CFGR_HPRE)
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+#else
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+#endif
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  SystemCoreClock = SystemD2Clock;
+#else
+  SystemCoreClock = common_system_clock;
+#endif /* DUAL_CORE && CORE_CM4 */
+
+  /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
+  if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Init the low level hardware */
+  HAL_MspInit();
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function de-Initializes common part of the HAL and stops the systick.
+  *         This function is optional.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DeInit(void)
+{
+  /* Reset of all peripherals */
+  __HAL_RCC_AHB3_FORCE_RESET();
+  __HAL_RCC_AHB3_RELEASE_RESET();
+
+  __HAL_RCC_AHB1_FORCE_RESET();
+  __HAL_RCC_AHB1_RELEASE_RESET();
+
+  __HAL_RCC_AHB2_FORCE_RESET();
+  __HAL_RCC_AHB2_RELEASE_RESET();
+
+  __HAL_RCC_AHB4_FORCE_RESET();
+ __HAL_RCC_AHB4_RELEASE_RESET();
+
+  __HAL_RCC_APB3_FORCE_RESET();
+  __HAL_RCC_APB3_RELEASE_RESET();
+
+  __HAL_RCC_APB1L_FORCE_RESET();
+  __HAL_RCC_APB1L_RELEASE_RESET();
+
+  __HAL_RCC_APB1H_FORCE_RESET();
+  __HAL_RCC_APB1H_RELEASE_RESET();
+
+   __HAL_RCC_APB2_FORCE_RESET();
+   __HAL_RCC_APB2_RELEASE_RESET();
+
+  __HAL_RCC_APB4_FORCE_RESET();
+  __HAL_RCC_APB4_RELEASE_RESET();
+
+  /* De-Init the low level hardware */
+  HAL_MspDeInit();
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the MSP.
+  * @retval None
+  */
+__weak void HAL_MspInit(void)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes the MSP.
+  * @retval None
+  */
+__weak void HAL_MspDeInit(void)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief This function configures the source of the time base.
+  *        The time source is configured  to have 1ms time base with a dedicated
+  *        Tick interrupt priority.
+  * @note This function is called  automatically at the beginning of program after
+  *       reset by HAL_Init() or at any time when clock is reconfigured  by HAL_RCC_ClockConfig().
+  * @note In the default implementation, SysTick timer is the source of time base.
+  *       It is used to generate interrupts at regular time intervals.
+  *       Care must be taken if HAL_Delay() is called from a peripheral ISR process,
+  *       The the SysTick interrupt must have higher priority (numerically lower)
+  *       than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+  *       The function is declared as __weak  to be overwritten  in case of other
+  *       implementation  in user file.
+  * @param TickPriority: Tick interrupt priority.
+  * @retval HAL status
+  */
+__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+  /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/
+  if((uint32_t)uwTickFreq == 0UL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Configure the SysTick to have interrupt in 1ms time basis*/
+  if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Configure the SysTick IRQ priority */
+  if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+  {
+    HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
+    uwTickPrio = TickPriority;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Group2 HAL Control functions
+ *  @brief    HAL Control functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### HAL Control functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Provide a tick value in millisecond
+      (+) Provide a blocking delay in millisecond
+      (+) Suspend the time base source interrupt
+      (+) Resume the time base source interrupt
+      (+) Get the HAL API driver version
+      (+) Get the device identifier
+      (+) Get the device revision identifier
+      (+) Enable/Disable Debug module during SLEEP mode
+      (+) Enable/Disable Debug module during STOP mode
+      (+) Enable/Disable Debug module during STANDBY mode
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief This function is called to increment  a global variable "uwTick"
+  *        used as application time base.
+  * @note In the default implementation, this variable is incremented each 1ms
+  *       in Systick ISR.
+ * @note This function is declared as __weak to be overwritten in case of other
+  *      implementations in user file.
+  * @retval None
+  */
+__weak void HAL_IncTick(void)
+{
+  uwTick += (uint32_t)uwTickFreq;
+}
+
+/**
+  * @brief Provides a tick value in millisecond.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @retval tick value
+  */
+__weak uint32_t HAL_GetTick(void)
+{
+  return uwTick;
+}
+
+/**
+  * @brief This function returns a tick priority.
+  * @retval tick priority
+  */
+uint32_t HAL_GetTickPrio(void)
+{
+  return uwTickPrio;
+}
+
+/**
+  * @brief Set new tick Freq.
+  * @retval Status
+  */
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
+{
+  HAL_StatusTypeDef status  = HAL_OK;
+  HAL_TickFreqTypeDef prevTickFreq;
+
+  assert_param(IS_TICKFREQ(Freq));
+
+  if (uwTickFreq != Freq)
+  {
+
+    /* Back up uwTickFreq frequency */
+    prevTickFreq = uwTickFreq;
+
+    /* Update uwTickFreq global variable used by HAL_InitTick() */
+    uwTickFreq = Freq;
+
+    /* Apply the new tick Freq  */
+    status = HAL_InitTick(uwTickPrio);
+    if (status != HAL_OK)
+    {
+      /* Restore previous tick frequency */
+      uwTickFreq = prevTickFreq;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief Return tick frequency.
+  * @retval tick period in Hz
+  */
+HAL_TickFreqTypeDef HAL_GetTickFreq(void)
+{
+  return uwTickFreq;
+}
+
+/**
+  * @brief This function provides minimum delay (in milliseconds) based
+  *        on variable incremented.
+  * @note In the default implementation , SysTick timer is the source of time base.
+  *       It is used to generate interrupts at regular time intervals where uwTick
+  *       is incremented.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @param Delay  specifies the delay time length, in milliseconds.
+  * @retval None
+  */
+__weak void HAL_Delay(uint32_t Delay)
+{
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t wait = Delay;
+
+  /* Add a freq to guarantee minimum wait */
+  if (wait < HAL_MAX_DELAY)
+  {
+    wait += (uint32_t)(uwTickFreq);
+  }
+
+  while ((HAL_GetTick() - tickstart) < wait)
+  {
+  }
+}
+
+/**
+  * @brief Suspend Tick increment.
+  * @note In the default implementation , SysTick timer is the source of time base. It is
+  *       used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
+  *       is called, the the SysTick interrupt will be disabled and so Tick increment
+  *       is suspended.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @retval None
+  */
+__weak void HAL_SuspendTick(void)
+{
+  /* Disable SysTick Interrupt */
+  SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
+}
+
+/**
+  * @brief Resume Tick increment.
+  * @note In the default implementation , SysTick timer is the source of time base. It is
+  *       used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
+  *       is called, the the SysTick interrupt will be enabled and so Tick increment
+  *       is resumed.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @retval None
+  */
+__weak void HAL_ResumeTick(void)
+{
+  /* Enable SysTick Interrupt */
+  SysTick->CTRL  |= SysTick_CTRL_TICKINT_Msk;
+}
+
+/**
+  * @brief  Returns the HAL revision
+  * @retval version : 0xXYZR (8bits for each decimal, R for RC)
+  */
+uint32_t HAL_GetHalVersion(void)
+{
+ return __STM32H7xx_HAL_VERSION;
+}
+
+/**
+  * @brief  Returns the device revision identifier.
+  * @retval Device revision identifier
+  */
+uint32_t HAL_GetREVID(void)
+{
+   return((DBGMCU->IDCODE) >> 16);
+}
+
+/**
+  * @brief  Returns the device identifier.
+  * @retval Device identifier
+  */
+uint32_t HAL_GetDEVID(void)
+{
+   return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
+}
+
+/**
+  * @brief  Return the first word of the unique device identifier (UID based on 96 bits)
+  * @retval Device identifier
+  */
+uint32_t HAL_GetUIDw0(void)
+{
+  return(READ_REG(*((uint32_t *)UID_BASE)));
+}
+
+/**
+  * @brief  Return the second word of the unique device identifier (UID based on 96 bits)
+  * @retval Device identifier
+  */
+uint32_t HAL_GetUIDw1(void)
+{
+  return(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
+}
+
+/**
+  * @brief  Return the third word of the unique device identifier (UID based on 96 bits)
+  * @retval Device identifier
+  */
+uint32_t HAL_GetUIDw2(void)
+{
+  return(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
+}
+
+/**
+  * @brief Configure the internal voltage reference buffer voltage scale.
+  * @param VoltageScaling  specifies the output voltage to achieve
+  *          This parameter can be one of the following values:
+  *            @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 2.048 V.
+  *                                                This requires VDDA equal to or higher than 2.4 V.
+  *            @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT2 around 2.5 V.
+  *                                                This requires VDDA equal to or higher than 2.8 V.
+  *            @arg SYSCFG_VREFBUF_VOLTAGE_SCALE2: VREF_OUT3 around 1.5 V.
+  *                                                This requires VDDA equal to or higher than 1.8 V.
+  *            @arg SYSCFG_VREFBUF_VOLTAGE_SCALE3: VREF_OUT4 around 1.8 V.
+  *                                                This requires VDDA equal to or higher than 2.1 V.
+  * @retval None
+  */
+void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling));
+
+  MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling);
+}
+
+/**
+  * @brief Configure the internal voltage reference buffer high impedance mode.
+  * @param Mode  specifies the high impedance mode
+  *          This parameter can be one of the following values:
+  *            @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output.
+  *            @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance.
+  * @retval None
+  */
+void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode));
+
+  MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode);
+}
+
+/**
+  * @brief  Tune the Internal Voltage Reference buffer (VREFBUF).
+  * @retval None
+  */
+void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue));
+
+  MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue);
+}
+
+/**
+  * @brief  Enable the Internal Voltage Reference buffer (VREFBUF).
+  * @retval HAL_OK/HAL_TIMEOUT
+  */
+HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void)
+{
+  uint32_t  tickstart;
+
+  SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
+
+  /* Get Start Tick*/
+  tickstart = HAL_GetTick();
+
+  /* Wait for VRR bit  */
+  while(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0UL)
+  {
+    if((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the Internal Voltage Reference buffer (VREFBUF).
+  *
+  * @retval None
+  */
+void HAL_SYSCFG_DisableVREFBUF(void)
+{
+  CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
+}
+
+#if defined(SYSCFG_PMCR_EPIS_SEL)
+/**
+  * @brief  Ethernet PHY Interface Selection either MII or RMII
+  * @param  SYSCFG_ETHInterface: Selects the Ethernet PHY interface
+  *   This parameter can be one of the following values:
+  *   @arg SYSCFG_ETH_MII : Select the Media Independent Interface
+  *   @arg SYSCFG_ETH_RMII: Select the Reduced Media Independent Interface
+  * @retval None
+  */
+void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface)
+{
+  /* Check the parameter */
+  assert_param(IS_SYSCFG_ETHERNET_CONFIG(SYSCFG_ETHInterface));
+
+  MODIFY_REG(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL, (uint32_t)(SYSCFG_ETHInterface));
+}
+#endif /* SYSCFG_PMCR_EPIS_SEL */
+
+/**
+  * @brief  Analog Switch control for dual analog pads.
+  * @param  SYSCFG_AnalogSwitch: Selects the analog pad
+  *   This parameter can be one or a combination of the following values:
+  *   @arg SYSCFG_SWITCH_PA0 : Select PA0 analog switch
+  *   @arg SYSCFG_SWITCH_PA1:  Select PA1 analog switch
+  *   @arg SYSCFG_SWITCH_PC2 : Select PC2 analog switch
+  *   @arg SYSCFG_SWITCH_PC3:  Select PC3 analog switch
+  * @param  SYSCFG_SwitchState: Open or Close the analog switch between dual pads (PXn and PXn_C)
+  *   This parameter can be one or a combination of the following values:
+  *   @arg SYSCFG_SWITCH_PA0_OPEN
+  *   @arg SYSCFG_SWITCH_PA0_CLOSE
+  *   @arg SYSCFG_SWITCH_PA1_OPEN
+  *   @arg SYSCFG_SWITCH_PA1_CLOSE
+  *   @arg SYSCFG_SWITCH_PC2_OPEN
+  *   @arg SYSCFG_SWITCH_PC2_CLOSE
+  *   @arg SYSCFG_SWITCH_PC3_OPEN
+  *   @arg SYSCFG_SWITCH_PC3_CLOSE
+  * @retval None
+  */
+
+void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState )
+{
+  /* Check the parameter */
+  assert_param(IS_SYSCFG_ANALOG_SWITCH(SYSCFG_AnalogSwitch));
+  assert_param(IS_SYSCFG_SWITCH_STATE(SYSCFG_SwitchState));
+
+  MODIFY_REG(SYSCFG->PMCR, (uint32_t) SYSCFG_AnalogSwitch, (uint32_t)(SYSCFG_SwitchState));
+}
+
+#if defined(SYSCFG_PMCR_BOOSTEN)
+/**
+  * @brief  Enables the booster to reduce the total harmonic distortion of the analog
+  *         switch when the supply voltage is lower than 2.7 V.
+  * @note   Activating the booster allows to guaranty the analog switch AC performance
+  *         when the supply voltage is below 2.7 V: in this case, the analog switch
+  *         performance is the same on the full voltage range
+  * @retval None
+  */
+void HAL_SYSCFG_EnableBOOST(void)
+{
+ SET_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
+}
+
+/**
+  * @brief  Disables the booster
+  * @note   Activating the booster allows to guaranty the analog switch AC performance
+  *         when the supply voltage is below 2.7 V: in this case, the analog switch
+  *         performance is the same on the full voltage range
+  * @retval None
+  */
+void HAL_SYSCFG_DisableBOOST(void)
+{
+ CLEAR_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
+}
+#endif /* SYSCFG_PMCR_BOOSTEN */
+
+#if defined (SYSCFG_UR2_BOOT_ADD0) ||  defined (SYSCFG_UR2_BCM7_ADD0)
+/**
+  * @brief  BootCM7 address 0 configuration
+  * @param  BootRegister :Specifies the Boot Address register (Address0 or Address1)
+  *   This parameter can be one of the following values:
+  *   @arg SYSCFG_BOOT_ADDR0 : Select the boot address0
+  *   @arg SYSCFG_BOOT_ADDR1:  Select the boot address1
+  * @param  BootAddress :Specifies the CM7 Boot Address to be loaded in Address0 or Address1
+  * @retval None
+  */
+void HAL_SYSCFG_CM7BootAddConfig(uint32_t BootRegister, uint32_t BootAddress)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_BOOT_REGISTER(BootRegister));
+  assert_param(IS_SYSCFG_BOOT_ADDRESS(BootAddress));
+  if ( BootRegister == SYSCFG_BOOT_ADDR0 )
+  {
+    /* Configure CM7 BOOT ADD0 */
+#if defined(DUAL_CORE)
+    MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0, ((BootAddress >> 16) << SYSCFG_UR2_BCM7_ADD0_Pos));
+#else
+    MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0, ((BootAddress >> 16) << SYSCFG_UR2_BOOT_ADD0_Pos));
+#endif /*DUAL_CORE*/
+  }
+  else
+  {
+    /* Configure CM7 BOOT ADD1 */
+#if defined(DUAL_CORE)
+    MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1, (BootAddress >> 16));
+#else
+    MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1, (BootAddress >> 16));
+#endif /*DUAL_CORE*/
+  }
+}
+#endif /* SYSCFG_UR2_BOOT_ADD0 || SYSCFG_UR2_BCM7_ADD0 */
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  BootCM4 address 0 configuration
+  * @param  BootRegister :Specifies the Boot Address register (Address0 or Address1)
+  *   This parameter can be one of the following values:
+  *   @arg SYSCFG_BOOT_ADDR0 : Select the boot address0
+  *   @arg SYSCFG_BOOT_ADDR1:  Select the boot address1
+  * @param  BootAddress :Specifies the CM4 Boot Address to be loaded in Address0 or Address1
+  * @retval None
+  */
+void HAL_SYSCFG_CM4BootAddConfig(uint32_t BootRegister, uint32_t BootAddress)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_BOOT_REGISTER(BootRegister));
+  assert_param(IS_SYSCFG_BOOT_ADDRESS(BootAddress));
+
+  if ( BootRegister == SYSCFG_BOOT_ADDR0 )
+  {
+    /* Configure CM4 BOOT ADD0 */
+    MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0, ((BootAddress >> 16)<< SYSCFG_UR3_BCM4_ADD0_Pos));
+  }
+
+  else
+  {
+    /* Configure CM4 BOOT ADD1 */
+    MODIFY_REG(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1, (BootAddress >> 16));
+  }
+}
+
+/**
+  * @brief  Enables the Cortex-M7 boot
+  * @retval None
+  */
+void HAL_SYSCFG_EnableCM7BOOT(void)
+{
+ SET_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM7);
+}
+
+/**
+  * @brief  Disables the Cortex-M7 boot
+  * @note   Disabling the boot will gate the CPU clock
+  * @retval None
+  */
+void HAL_SYSCFG_DisableCM7BOOT(void)
+{
+ CLEAR_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM7) ;
+}
+
+/**
+  * @brief  Enables the Cortex-M4 boot
+  * @retval None
+  */
+void HAL_SYSCFG_EnableCM4BOOT(void)
+{
+ SET_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4);
+}
+
+/**
+  * @brief  Disables the Cortex-M4 boot
+  * @note   Disabling the boot will gate the CPU clock
+  * @retval None
+  */
+void HAL_SYSCFG_DisableCM4BOOT(void)
+{
+  CLEAR_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4);
+}
+#endif /*DUAL_CORE*/
+/**
+  * @brief  Enables the I/O Compensation Cell.
+  * @note   The I/O compensation cell can be used only when the device supply
+  *         voltage ranges from 2.4 to 3.6 V.
+  * @retval None
+  */
+void HAL_EnableCompensationCell(void)
+{
+  SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN) ;
+}
+
+/**
+  * @brief  Power-down the I/O Compensation Cell.
+  * @note   The I/O compensation cell can be used only when the device supply
+  *         voltage ranges from 2.4 to 3.6 V.
+  * @retval None
+  */
+void HAL_DisableCompensationCell(void)
+{
+  CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN);
+}
+
+
+/**
+  * @brief  To Enable optimize the I/O speed when the product voltage is low.
+  * @note   This bit is active only if PRODUCT_BELOW_25V user option bit is set. It must be
+  *         used only if the product supply voltage is below 2.5 V. Setting this bit when VDD is
+  *         higher than 2.5 V might be destructive.
+  * @retval None
+  */
+void HAL_SYSCFG_EnableIOSpeedOptimize(void)
+{
+#if defined(SYSCFG_CCCSR_HSLV)
+  SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);
+#else
+  SET_BIT(SYSCFG->CCCSR, (SYSCFG_CCCSR_HSLV0| SYSCFG_CCCSR_HSLV1 | SYSCFG_CCCSR_HSLV2  | SYSCFG_CCCSR_HSLV3));
+#endif   /* SYSCFG_CCCSR_HSLV */
+}
+
+/**
+  * @brief  To Disable optimize the I/O speed when the product voltage is low.
+  * @note   This bit is active only if PRODUCT_BELOW_25V user option bit is set. It must be
+  *         used only if the product supply voltage is below 2.5 V. Setting this bit when VDD is
+  *         higher than 2.5 V might be destructive.
+  * @retval None
+  */
+void HAL_SYSCFG_DisableIOSpeedOptimize(void)
+{
+#if defined(SYSCFG_CCCSR_HSLV)
+  CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);
+#else
+  CLEAR_BIT(SYSCFG->CCCSR, (SYSCFG_CCCSR_HSLV0| SYSCFG_CCCSR_HSLV1 | SYSCFG_CCCSR_HSLV2  | SYSCFG_CCCSR_HSLV3));
+#endif   /* SYSCFG_CCCSR_HSLV */
+}
+
+/**
+  * @brief  Code selection for the I/O Compensation cell
+  * @param  SYSCFG_CompCode: Selects the code to be applied for the I/O compensation cell
+  *   This parameter can be one of the following values:
+  *   @arg SYSCFG_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR)
+  *   @arg SYSCFG_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR)
+  * @retval None
+  */
+void HAL_SYSCFG_CompensationCodeSelect(uint32_t SYSCFG_CompCode)
+{
+  /* Check the parameter */
+  assert_param(IS_SYSCFG_CODE_SELECT(SYSCFG_CompCode));
+  MODIFY_REG(SYSCFG->CCCSR, SYSCFG_CCCSR_CS, (uint32_t)(SYSCFG_CompCode));
+}
+
+/**
+  * @brief  Code selection for the I/O Compensation cell
+  * @param  SYSCFG_PMOSCode: PMOS compensation code
+  *         This code is applied to the I/O compensation cell when the CS bit of the
+  *          SYSCFG_CMPCR is set
+  * @param  SYSCFG_NMOSCode: NMOS compensation code
+  *         This code is applied to the I/O compensation cell when the CS bit of the
+  *          SYSCFG_CMPCR is set
+  * @retval None
+  */
+void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode )
+{
+  /* Check the parameter */
+  assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_PMOSCode));
+  assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_NMOSCode));
+  MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC|SYSCFG_CCCR_PCC, (((uint32_t)(SYSCFG_PMOSCode)<< 4)|(uint32_t)(SYSCFG_NMOSCode)) );
+}
+
+#if defined(SYSCFG_CCCR_NCC_MMC)
+/**
+  * @brief  Code selection for the I/O Compensation cell
+  * @param  SYSCFG_PMOSCode: VDDMMC PMOS compensation code
+  *         This code is applied to the I/O compensation cell when the CS bit of the
+  *          SYSCFG_CMPCR is set
+  * @param  SYSCFG_NMOSCode: VDDMMC NMOS compensation code
+  *         This code is applied to the I/O compensation cell when the CS bit of the
+  *          SYSCFG_CMPCR is set
+  * @retval None
+  */
+void HAL_SYSCFG_VDDMMC_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode )
+{
+  /* Check the parameter */
+  assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_PMOSCode));
+  assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_NMOSCode));
+  MODIFY_REG(SYSCFG->CCCR, (SYSCFG_CCCR_NCC_MMC | SYSCFG_CCCR_PCC_MMC), (((uint32_t)(SYSCFG_PMOSCode)<< 4)|(uint32_t)(SYSCFG_NMOSCode)) );
+}
+#endif /* SYSCFG_CCCR_NCC_MMC */
+
+/**
+  * @brief  Enable the Debug Module during Domain1/CDomain SLEEP mode
+  * @retval None
+  */
+void HAL_EnableDBGSleepMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
+}
+
+/**
+  * @brief  Disable the Debug Module during Domain1/CDomain SLEEP mode
+  * @retval None
+  */
+void HAL_DisableDBGSleepMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
+}
+
+
+/**
+  * @brief  Enable the Debug Module during Domain1/CDomain STOP mode
+  * @retval None
+  */
+void HAL_EnableDBGStopMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
+}
+
+/**
+  * @brief  Disable the Debug Module during Domain1/CDomain STOP mode
+  * @retval None
+  */
+void HAL_DisableDBGStopMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
+}
+
+/**
+  * @brief  Enable the Debug Module during Domain1/CDomain STANDBY mode
+  * @retval None
+  */
+void HAL_EnableDBGStandbyMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
+}
+
+/**
+  * @brief  Disable the Debug Module during Domain1/CDomain STANDBY mode
+  * @retval None
+  */
+void HAL_DisableDBGStandbyMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Enable the Debug Module during Domain1 SLEEP mode
+  * @retval None
+  */
+void HAL_EnableDomain2DBGSleepMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2);
+}
+
+/**
+  * @brief  Disable the Debug Module during Domain2 SLEEP mode
+  * @retval None
+  */
+void HAL_DisableDomain2DBGSleepMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2);
+}
+
+/**
+  * @brief  Enable the Debug Module during Domain2 STOP mode
+  * @retval None
+  */
+void HAL_EnableDomain2DBGStopMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2);
+}
+
+/**
+  * @brief  Disable the Debug Module during Domain2 STOP mode
+  * @retval None
+  */
+void HAL_DisableDomain2DBGStopMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2);
+}
+
+/**
+  * @brief  Enable the Debug Module during Domain2 STANDBY mode
+  * @retval None
+  */
+void HAL_EnableDomain2DBGStandbyMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2);
+}
+
+/**
+  * @brief  Disable the Debug Module during Domain2 STANDBY mode
+  * @retval None
+  */
+void HAL_DisableDomain2DBGStandbyMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2);
+}
+#endif /*DUAL_CORE*/
+
+/**
+  * @brief  Enable the Debug Module during Domain3/SRDomain STOP mode
+  * @retval None
+  */
+void HAL_EnableDomain3DBGStopMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
+}
+/**
+  * @brief  Disable the Debug Module during Domain3/SRDomain STOP mode
+  * @retval None
+  */
+void HAL_DisableDomain3DBGStopMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
+}
+
+/**
+  * @brief  Enable the Debug Module during Domain3/SRDomain STANDBY mode
+  * @retval None
+  */
+void HAL_EnableDomain3DBGStandbyMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
+}
+
+/**
+  * @brief  Disable the Debug Module during Domain3/SRDomain STANDBY mode
+  * @retval None
+  */
+void HAL_DisableDomain3DBGStandbyMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
+}
+
+/**
+  * @brief  Set the FMC Memory Mapping Swapping config.
+  * @param  BankMapConfig: Defines the FMC Bank mapping configuration. This parameter can be
+            FMC_SWAPBMAP_DISABLE, FMC_SWAPBMAP_SDRAM_SRAM, FMC_SWAPBMAP_SDRAMB2
+  * @retval HAL state
+  */
+void HAL_SetFMCMemorySwappingConfig(uint32_t BankMapConfig)
+{
+  /* Check the parameter */
+  assert_param(IS_FMC_SWAPBMAP_MODE(BankMapConfig));
+  MODIFY_REG(FMC_Bank1_R->BTCR[0], FMC_BCR1_BMAP, BankMapConfig);
+}
+
+/**
+  * @brief  Get FMC Bank mapping mode.
+  * @retval The FMC Bank mapping mode. This parameter can be
+            FMC_SWAPBMAP_DISABLE, FMC_SWAPBMAP_SDRAM_SRAM, FMC_SWAPBMAP_SDRAMB2
+*/
+uint32_t HAL_GetFMCMemorySwappingConfig(void)
+{
+  return READ_BIT(FMC_Bank1_R->BTCR[0], FMC_BCR1_BMAP);
+}
+
+/**
+  * @brief  Configure the EXTI input event line edge
+  * @note    No edge configuration for direct lines but for configurable lines:(EXTI_LINE0..EXTI_LINE21),
+  *          EXTI_LINE49,EXTI_LINE51,EXTI_LINE82,EXTI_LINE84,EXTI_LINE85 and EXTI_LINE86.
+  * @param   EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
+  *         (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
+  * @param   EXTI_Edge: Specifies  EXTI line Edge used.
+  *          This parameter can be one of the following values :
+  *   @arg EXTI_RISING_EDGE : Configurable line, with Rising edge trigger detection
+  *   @arg EXTI_FALLING_EDGE: Configurable line, with Falling edge trigger detection
+  * @retval None
+  */
+void HAL_EXTI_EdgeConfig(uint32_t EXTI_Line , uint32_t EXTI_Edge )
+{
+  /* Check the parameter */
+  assert_param(IS_HAL_EXTI_CONFIG_LINE(EXTI_Line));
+  assert_param(IS_EXTI_EDGE_LINE(EXTI_Edge));
+
+  /* Clear Rising Falling edge configuration */
+  CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+  CLEAR_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+
+  if( (EXTI_Edge & EXTI_RISING_EDGE) == EXTI_RISING_EDGE)
+  {
+   SET_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+  }
+  if( (EXTI_Edge & EXTI_FALLING_EDGE) == EXTI_FALLING_EDGE)
+  {
+   SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+  }
+}
+
+/**
+  * @brief  Generates a Software interrupt on selected EXTI line.
+  * @param   EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
+  *          (EXTI_LINE0..EXTI_LINE21),EXTI_LINE49,EXTI_LINE51,EXTI_LINE82,EXTI_LINE84,EXTI_LINE85 and EXTI_LINE86.
+  * @retval None
+  */
+void HAL_EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
+{
+  /* Check the parameters */
+  assert_param(IS_HAL_EXTI_CONFIG_LINE(EXTI_Line));
+
+  SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->SWIER1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+}
+
+
+/**
+  * @brief  Clears the EXTI's line pending flags for Domain D1
+  * @param   EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
+  *         (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
+  * @retval None
+  */
+void HAL_EXTI_D1_ClearFlag(uint32_t EXTI_Line)
+{
+  /* Check the parameters */
+ assert_param(IS_EXTI_D1_LINE(EXTI_Line));
+ WRITE_REG(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->PR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Clears the EXTI's line pending flags for Domain D2
+  * @param   EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
+  *         (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
+  * @retval None
+  */
+void HAL_EXTI_D2_ClearFlag(uint32_t EXTI_Line)
+{
+  /* Check the parameters */
+ assert_param(IS_EXTI_D2_LINE(EXTI_Line));
+ WRITE_REG(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->PR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+}
+
+#endif /*DUAL_CORE*/
+/**
+  * @brief  Configure the EXTI input event line for Domain D1
+  * @param   EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
+  *         (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
+  * @param   EXTI_Mode: Specifies which EXTI line is used as interrupt or an event.
+  *          This parameter can be one or a combination of the following values :
+  *   @arg EXTI_MODE_IT :  Interrupt Mode selected
+  *   @arg EXTI_MODE_EVT : Event Mode selected
+  * @param   EXTI_LineCmd controls (Enable/Disable) the EXTI line.
+
+  * @retval None
+  */
+void HAL_EXTI_D1_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode,  uint32_t EXTI_LineCmd )
+{
+  /* Check the parameter */
+  assert_param(IS_EXTI_D1_LINE(EXTI_Line));
+  assert_param(IS_EXTI_MODE_LINE(EXTI_Mode));
+
+  if( (EXTI_Mode & EXTI_MODE_IT) == EXTI_MODE_IT)
+  {
+     if( EXTI_LineCmd == 0UL)
+     {
+       /* Clear EXTI line configuration */
+        CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)),(uint32_t)(1UL << (EXTI_Line & 0x1FUL)) );
+     }
+     else
+     {
+        SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+     }
+  }
+
+  if( (EXTI_Mode & EXTI_MODE_EVT) == EXTI_MODE_EVT)
+  {
+    if( EXTI_LineCmd == 0UL)
+    {
+      /* Clear EXTI line configuration */
+      CLEAR_BIT(  *(__IO uint32_t *) (((uint32_t) &(EXTI_D1->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+    }
+    else
+    {
+      SET_BIT(  *(__IO uint32_t *) (((uint32_t) &(EXTI_D1->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+    }
+  }
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Configure the EXTI input event line for Domain D2
+  * @param   EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
+  *         (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
+  * @param   EXTI_Mode: Specifies which EXTI line is used as interrupt or an event.
+  *          This parameter can be one or a combination of the following values :
+  *   @arg EXTI_MODE_IT :  Interrupt Mode selected
+  *   @arg EXTI_MODE_EVT : Event Mode selected
+  * @param   EXTI_LineCmd controls (Enable/Disable) the EXTI line.
+
+  * @retval None
+  */
+void HAL_EXTI_D2_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode,  uint32_t EXTI_LineCmd )
+{
+  /* Check the parameter */
+  assert_param(IS_EXTI_D2_LINE(EXTI_Line));
+  assert_param(IS_EXTI_MODE_LINE(EXTI_Mode));
+
+  if( (EXTI_Mode & EXTI_MODE_IT) == EXTI_MODE_IT)
+  {
+    if( EXTI_LineCmd == 0UL)
+    {
+    /* Clear EXTI line configuration */
+     CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)),(uint32_t)(1UL << (EXTI_Line & 0x1FUL)) );
+    }
+    else
+    {
+     SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+    }
+  }
+
+  if( (EXTI_Mode & EXTI_MODE_EVT) == EXTI_MODE_EVT)
+  {
+    if( EXTI_LineCmd == 0UL)
+    {
+      /* Clear EXTI line configuration */
+      CLEAR_BIT(  *(__IO uint32_t *) (((uint32_t) &(EXTI_D2->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+    }
+    else
+    {
+      SET_BIT(  *(__IO uint32_t *) (((uint32_t) &(EXTI_D2->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+    }
+  }
+}
+#endif /*DUAL_CORE*/
+
+/**
+  * @brief  Configure the EXTI input event line for Domain D3
+  * @param   EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
+  *         (EXTI_LINE0...EXTI_LINE15),(EXTI_LINE19...EXTI_LINE21),EXTI_LINE25, EXTI_LINE34,
+  *          EXTI_LINE35,EXTI_LINE41,(EXTI_LINE48...EXTI_LINE53)
+  * @param   EXTI_LineCmd controls (Enable/Disable) the EXTI line.
+  * @param   EXTI_ClearSrc: Specifies the clear source of D3 pending event.
+  *          This parameter can be one of the following values :
+  *   @arg BDMA_CH6_CLEAR : BDMA ch6 event selected as D3 domain pendclear source
+  *   @arg BDMA_CH7_CLEAR : BDMA ch7 event selected as D3 domain pendclear source
+  *   @arg LPTIM4_OUT_CLEAR : LPTIM4 out selected as D3 domain pendclear source
+  *   @arg LPTIM5_OUT_CLEAR : LPTIM5 out selected as D3 domain pendclear source
+  * @retval None
+  */
+void HAL_EXTI_D3_EventInputConfig(uint32_t EXTI_Line, uint32_t EXTI_LineCmd , uint32_t EXTI_ClearSrc  )
+{
+  __IO uint32_t *pRegv;
+
+  /* Check the parameter */
+  assert_param(IS_EXTI_D3_LINE(EXTI_Line));
+  assert_param(IS_EXTI_D3_CLEAR(EXTI_ClearSrc));
+
+  if( EXTI_LineCmd == 0UL)
+  {
+    /* Clear EXTI line configuration */
+    CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->D3PMR1)) + ((EXTI_Line >> 5 ) * 0x20UL)),(uint32_t)(1UL << (EXTI_Line & 0x1FUL)) );
+  }
+  else
+  {
+    SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->D3PMR1)) +((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+  }
+
+  if(((EXTI_Line>>4)%2UL) == 0UL)
+  {
+    pRegv = (__IO uint32_t *) (((uint32_t) &(EXTI->D3PCR1L)) + ((EXTI_Line >> 5 ) * 0x20UL));
+  }
+  else
+  {
+    pRegv = (__IO uint32_t *) (((uint32_t) &(EXTI->D3PCR1H)) + ((EXTI_Line >> 5 ) * 0x20UL));
+  }
+  MODIFY_REG(*pRegv, (uint32_t)(3UL << ((EXTI_Line*2UL) & 0x1FUL)), (uint32_t)(EXTI_ClearSrc << ((EXTI_Line*2UL) & 0x1FUL)));
+
+}
+
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c
new file mode 100644
index 00000000..631f432f
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c
@@ -0,0 +1,533 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_cortex.c
+  * @author  MCD Application Team
+  * @brief   CORTEX HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the CORTEX:
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions
+  *
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+
+    [..]
+    *** How to configure Interrupts using CORTEX HAL driver ***
+    ===========================================================
+    [..]
+    This section provides functions allowing to configure the NVIC interrupts (IRQ).
+    The Cortex-M exceptions are managed by CMSIS functions.
+
+    (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
+        function according to the following table.
+    (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
+    (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
+    (#) please refer to programming manual for details in how to configure priority.
+
+     -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
+         The pending IRQ priority will be managed only by the sub priority.
+
+     -@- IRQ priority order (sorted by highest to lowest priority):
+        (+@) Lowest preemption priority
+        (+@) Lowest sub priority
+        (+@) Lowest hardware priority (IRQ number)
+
+    [..]
+    *** How to configure Systick using CORTEX HAL driver ***
+    ========================================================
+    [..]
+    Setup SysTick Timer for time base.
+
+   (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
+       is a CMSIS function that:
+        (++) Configures the SysTick Reload register with value passed as function parameter.
+        (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
+        (++) Resets the SysTick Counter register.
+        (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
+        (++) Enables the SysTick Interrupt.
+        (++) Starts the SysTick Counter.
+
+   (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
+       HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
+       HAL_SYSTICK_Config() function call. The HAL_SYSTICK_CLKSourceConfig() macro is defined
+       inside the stm32h7xx_hal_cortex.h file.
+
+   (+) You can change the SysTick IRQ priority by calling the
+       HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
+       call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
+
+   (+) To adjust the SysTick time base, use the following formula:
+
+       Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
+       (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
+       (++) Reload Value should not exceed 0xFFFFFF
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup CORTEX CORTEX
+  * @brief CORTEX HAL module driver
+  * @{
+  */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
+  * @{
+  */
+
+
+/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+  ==============================================================================
+              ##### Initialization and de-initialization functions #####
+  ==============================================================================
+    [..]
+      This section provides the CORTEX HAL driver functions allowing to configure Interrupts
+      Systick functionalities
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Sets the priority grouping field (preemption priority and subpriority)
+  *         using the required unlock sequence.
+  * @param  PriorityGroup The priority grouping bits length.
+  *         This parameter can be one of the following values:
+  *         @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
+  *                                    4 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
+  *                                    3 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
+  *                                    2 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
+  *                                    1 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
+  *                                    0 bits for subpriority
+  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
+  *         The pending IRQ priority will be managed only by the subpriority.
+  * @retval None
+  */
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+
+  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
+  NVIC_SetPriorityGrouping(PriorityGroup);
+}
+
+/**
+  * @brief  Sets the priority of an interrupt.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
+  * @param  PreemptPriority The preemption priority for the IRQn channel.
+  *         This parameter can be a value between 0 and 15
+  *         A lower priority value indicates a higher priority
+  * @param  SubPriority the subpriority level for the IRQ channel.
+  *         This parameter can be a value between 0 and 15
+  *         A lower priority value indicates a higher priority.
+  * @retval None
+  */
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t prioritygroup;
+
+  /* Check the parameters */
+  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
+  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
+
+  prioritygroup = NVIC_GetPriorityGrouping();
+
+  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
+}
+
+/**
+  * @brief  Enables a device specific interrupt in the NVIC interrupt controller.
+  * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
+  *         function should be called before.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+  /* Enable interrupt */
+  NVIC_EnableIRQ(IRQn);
+}
+
+/**
+  * @brief  Disables a device specific interrupt in the NVIC interrupt controller.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+  /* Disable interrupt */
+  NVIC_DisableIRQ(IRQn);
+}
+
+/**
+  * @brief  Initiates a system reset request to reset the MCU.
+  * @retval None
+  */
+void HAL_NVIC_SystemReset(void)
+{
+  /* System Reset */
+  NVIC_SystemReset();
+}
+
+/**
+  * @brief  Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+  *         Counter is in free running mode to generate periodic interrupts.
+  * @param  TicksNumb Specifies the ticks Number of ticks between two interrupts.
+  * @retval status   - 0  Function succeeded.
+  *                  - 1  Function failed.
+  */
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
+{
+   return SysTick_Config(TicksNumb);
+}
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
+ *  @brief   Cortex control functions
+ *
+@verbatim
+  ==============================================================================
+                      ##### Peripheral Control functions #####
+  ==============================================================================
+    [..]
+      This subsection provides a set of functions allowing to control the CORTEX
+      (NVIC, SYSTICK, MPU) functionalities.
+
+
+@endverbatim
+  * @{
+  */
+#if (__MPU_PRESENT == 1)
+/**
+  * @brief  Disables the MPU
+  * @retval None
+  */
+void HAL_MPU_Disable(void)
+{
+  /* Make sure outstanding transfers are done */
+  __DMB();
+
+  /* Disable fault exceptions */
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+
+  /* Disable the MPU and clear the control register*/
+  MPU->CTRL = 0;
+}
+
+/**
+  * @brief  Enables the MPU
+  * @param  MPU_Control Specifies the control mode of the MPU during hard fault,
+  *         NMI, FAULTMASK and privileged access to the default memory
+  *         This parameter can be one of the following values:
+  *            @arg MPU_HFNMI_PRIVDEF_NONE
+  *            @arg MPU_HARDFAULT_NMI
+  *            @arg MPU_PRIVILEGED_DEFAULT
+  *            @arg MPU_HFNMI_PRIVDEF
+  * @retval None
+  */
+void HAL_MPU_Enable(uint32_t MPU_Control)
+{
+  /* Enable the MPU */
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+
+  /* Enable fault exceptions */
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+
+  /* Ensure MPU setting take effects */
+  __DSB();
+  __ISB();
+}
+/**
+  * @brief  Initializes and configures the Region and the memory to be protected.
+  * @param  MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
+  *                  the initialization and configuration information.
+  * @retval None
+  */
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
+{
+  /* Check the parameters */
+  assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
+  assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
+
+  /* Set the Region number */
+  MPU->RNR = MPU_Init->Number;
+
+  if ((MPU_Init->Enable) != 0UL)
+  {
+    /* Check the parameters */
+    assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
+    assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
+    assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
+    assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
+    assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
+    assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
+    assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
+    assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
+
+    MPU->RBAR = MPU_Init->BaseAddress;
+    MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
+                ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
+                ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
+                ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
+                ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
+                ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
+                ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
+                ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
+                ((uint32_t)MPU_Init->Enable                  << MPU_RASR_ENABLE_Pos);
+  }
+  else
+  {
+    MPU->RBAR = 0x00;
+    MPU->RASR = 0x00;
+  }
+}
+#endif /* __MPU_PRESENT */
+
+/**
+  * @brief  Gets the priority grouping field from the NVIC Interrupt Controller.
+  * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
+  */
+uint32_t HAL_NVIC_GetPriorityGrouping(void)
+{
+  /* Get the PRIGROUP[10:8] field value */
+  return NVIC_GetPriorityGrouping();
+}
+
+/**
+  * @brief  Gets the priority of an interrupt.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
+  * @param   PriorityGroup the priority grouping bits length.
+  *         This parameter can be one of the following values:
+  *           @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
+  *                                      4 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
+  *                                      3 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
+  *                                      2 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
+  *                                      1 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
+  *                                      0 bits for subpriority
+  * @param  pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
+  * @param  pSubPriority Pointer on the Subpriority value (starting from 0).
+  * @retval None
+  */
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+ /* Get priority for Cortex-M system or device specific interrupts */
+  NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
+}
+
+/**
+  * @brief  Sets Pending bit of an external interrupt.
+  * @param  IRQn External interrupt number
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+  /* Set interrupt pending */
+  NVIC_SetPendingIRQ(IRQn);
+}
+
+/**
+  * @brief  Gets Pending Interrupt (reads the pending register in the NVIC
+  *         and returns the pending bit for the specified interrupt).
+  * @param  IRQn External interrupt number.
+  *          This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
+  * @retval status  - 0  Interrupt status is not pending.
+  *                 - 1  Interrupt status is pending.
+  */
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+  /* Return 1 if pending else 0 */
+  return NVIC_GetPendingIRQ(IRQn);
+}
+
+/**
+  * @brief  Clears the pending bit of an external interrupt.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+  /* Clear pending interrupt */
+  NVIC_ClearPendingIRQ(IRQn);
+}
+
+/**
+  * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
+  * @param IRQn External interrupt number
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
+  * @retval status  - 0  Interrupt status is not pending.
+  *                 - 1  Interrupt status is pending.
+  */
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+  /* Return 1 if active else 0 */
+  return NVIC_GetActive(IRQn);
+}
+
+/**
+  * @brief  Configures the SysTick clock source.
+  * @param  CLKSource specifies the SysTick clock source.
+  *         This parameter can be one of the following values:
+  *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
+  *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
+  * @retval None
+  */
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
+  if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
+  {
+    SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
+  }
+  else
+  {
+    SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
+  }
+}
+
+/**
+  * @brief  This function handles SYSTICK interrupt request.
+  * @retval None
+  */
+void HAL_SYSTICK_IRQHandler(void)
+{
+  HAL_SYSTICK_Callback();
+}
+
+/**
+  * @brief  SYSTICK callback.
+  * @retval None
+  */
+__weak void HAL_SYSTICK_Callback(void)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SYSTICK_Callback could be implemented in the user file
+   */
+}
+
+#if defined(DUAL_CORE)
+
+/**
+  * @brief  Returns the current CPU ID.
+  * @retval CPU identifier
+  */
+uint32_t HAL_GetCurrentCPUID(void)
+{
+  if (((SCB->CPUID & 0x000000F0U) >> 4 )== 0x7U)
+  {
+    return  CM7_CPUID;
+  }
+  else
+  {
+    return CM4_CPUID;
+  }
+}
+
+#else
+
+/**
+* @brief  Returns the current CPU ID.
+* @retval CPU identifier
+*/
+uint32_t HAL_GetCurrentCPUID(void)
+{
+  return  CM7_CPUID;
+}
+
+#endif /*DUAL_CORE*/
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c
new file mode 100644
index 00000000..e2bbea73
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c
@@ -0,0 +1,2055 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_dma.c
+  * @author  MCD Application Team
+  * @brief   DMA HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Direct Memory Access (DMA) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral State and errors functions
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+   (#) Enable and configure the peripheral to be connected to the DMA Stream
+       (except for internal SRAM/FLASH memories: no initialization is
+       necessary) please refer to Reference manual for connection between peripherals
+       and DMA requests .
+
+   (#) For a given Stream, program the required configuration through the following parameters:
+       Transfer Direction, Source and Destination data formats,
+       Circular, Normal or peripheral flow control mode, Stream Priority level,
+       Source and Destination Increment mode, FIFO mode and its Threshold (if needed),
+       Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.
+
+     *** Polling mode IO operation ***
+     =================================
+    [..]
+          (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
+              address and destination address and the Length of data to be transferred
+          (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
+              case a fixed Timeout can be configured by User depending from his application.
+
+     *** Interrupt mode IO operation ***
+     ===================================
+    [..]
+          (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
+          (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
+          (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
+              Source address and destination address and the Length of data to be transferred. In this
+              case the DMA interrupt is configured
+          (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
+          (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
+              add his own function by customization of function pointer XferCpltCallback and
+              XferErrorCallback (i.e a member of DMA handle structure).
+    [..]
+     (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
+         detection.
+
+     (#) Use HAL_DMA_Abort() function to abort the current transfer
+
+     -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.
+
+     -@-   The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is
+           possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set
+           Half-Word data size for the peripheral to access its data register and set Word data size
+           for the Memory to gain in access time. Each two half words will be packed and written in
+           a single access to a Word in the Memory).
+
+     -@-   When FIFO is disabled, it is not allowed to configure different Data Sizes for Source
+           and Destination. In this case the Peripheral Data Size will be applied to both Source
+           and Destination.
+
+     *** DMA HAL driver macros list ***
+     =============================================
+     [..]
+       Below the list of most used macros in DMA HAL driver.
+
+      (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.
+      (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.
+      (+) __HAL_DMA_GET_FS: Return the current DMA Stream FIFO filled level.
+      (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Stream interrupts.
+      (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts.
+      (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not.
+
+     [..]
+      (@) You can refer to the DMA HAL driver header file for more useful macros.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup DMA DMA
+  * @brief DMA HAL module driver
+  * @{
+  */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+typedef struct
+{
+  __IO uint32_t ISR;   /*!< DMA interrupt status register */
+  __IO uint32_t Reserved0;
+  __IO uint32_t IFCR;  /*!< DMA interrupt flag clear register */
+} DMA_Base_Registers;
+
+typedef struct
+{
+  __IO uint32_t ISR;   /*!< BDMA interrupt status register */
+  __IO uint32_t IFCR;  /*!< BDMA interrupt flag clear register */
+} BDMA_Base_Registers;
+
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup DMA_Private_Constants
+ * @{
+ */
+#define HAL_TIMEOUT_DMA_ABORT         (5U)  /* 5 ms */
+
+#define BDMA_PERIPH_TO_MEMORY         (0x00000000U)                /*!< Peripheral to memory direction */
+#define BDMA_MEMORY_TO_PERIPH         ((uint32_t)BDMA_CCR_DIR)     /*!< Memory to peripheral direction */
+#define BDMA_MEMORY_TO_MEMORY         ((uint32_t)BDMA_CCR_MEM2MEM) /*!< Memory to memory direction     */
+
+/* DMA to BDMA conversion */
+#define DMA_TO_BDMA_DIRECTION(__DMA_DIRECTION__) (((__DMA_DIRECTION__) == DMA_MEMORY_TO_PERIPH)? BDMA_MEMORY_TO_PERIPH: \
+                                                  ((__DMA_DIRECTION__) == DMA_MEMORY_TO_MEMORY)? BDMA_MEMORY_TO_MEMORY: \
+                                                  BDMA_PERIPH_TO_MEMORY)
+
+#define DMA_TO_BDMA_PERIPHERAL_INC(__DMA_PERIPHERAL_INC__) ((__DMA_PERIPHERAL_INC__) >> 3U)
+#define DMA_TO_BDMA_MEMORY_INC(__DMA_MEMORY_INC__) ((__DMA_MEMORY_INC__) >> 3U)
+
+#define DMA_TO_BDMA_PDATA_SIZE(__DMA_PDATA_SIZE__) ((__DMA_PDATA_SIZE__) >> 3U)
+#define DMA_TO_BDMA_MDATA_SIZE(__DMA_MDATA_SIZE__) ((__DMA_MDATA_SIZE__) >> 3U)
+
+#define DMA_TO_BDMA_MODE(__DMA_MODE__) ((__DMA_MODE__) >> 3U)
+
+#define DMA_TO_BDMA_PRIORITY(__DMA_PRIORITY__) ((__DMA_PRIORITY__) >> 4U)
+
+#if defined(UART9)
+#define IS_DMA_UART_USART_REQUEST(__REQUEST__) ((((__REQUEST__) >= DMA_REQUEST_USART1_RX)  &&  ((__REQUEST__) <= DMA_REQUEST_USART3_TX)) || \
+                                                 (((__REQUEST__) >= DMA_REQUEST_UART4_RX)  &&  ((__REQUEST__) <= DMA_REQUEST_UART5_TX )) || \
+                                                 (((__REQUEST__) >= DMA_REQUEST_USART6_RX) &&  ((__REQUEST__) <= DMA_REQUEST_USART6_TX)) || \
+                                                 (((__REQUEST__) >= DMA_REQUEST_UART7_RX)  &&  ((__REQUEST__) <= DMA_REQUEST_UART8_TX )) || \
+                                                 (((__REQUEST__) >= DMA_REQUEST_UART9_RX)  &&  ((__REQUEST__) <= DMA_REQUEST_USART10_TX )))
+#else
+#define IS_DMA_UART_USART_REQUEST(__REQUEST__) ((((__REQUEST__) >= DMA_REQUEST_USART1_RX)  &&  ((__REQUEST__) <= DMA_REQUEST_USART3_TX)) || \
+                                                 (((__REQUEST__) >= DMA_REQUEST_UART4_RX)  &&  ((__REQUEST__) <= DMA_REQUEST_UART5_TX )) || \
+                                                 (((__REQUEST__) >= DMA_REQUEST_USART6_RX) &&  ((__REQUEST__) <= DMA_REQUEST_USART6_TX)) || \
+                                                 (((__REQUEST__) >= DMA_REQUEST_UART7_RX)  &&  ((__REQUEST__) <= DMA_REQUEST_UART8_TX )))
+
+#endif
+/**
+  * @}
+  */
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup DMA_Private_Functions
+  * @{
+  */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma);
+static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma);
+static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma);
+
+/**
+  * @}
+  */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @addtogroup DMA_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group1
+  *
+@verbatim
+ ===============================================================================
+             ##### Initialization and de-initialization functions  #####
+ ===============================================================================
+    [..]
+    This section provides functions allowing to initialize the DMA Stream source
+    and destination incrementation and data sizes, transfer direction,
+    circular/normal mode selection, memory-to-memory mode selection and Stream priority value.
+    [..]
+    The HAL_DMA_Init() function follows the DMA configuration procedures as described in
+    reference manual.
+    The HAL_DMA_DeInit function allows to deinitialize the DMA stream.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the DMA according to the specified
+  *         parameters in the DMA_InitTypeDef and create the associated handle.
+  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
+{
+  uint32_t registerValue;
+  uint32_t tickstart = HAL_GetTick();
+  DMA_Base_Registers *regs_dma;
+  BDMA_Base_Registers *regs_bdma;
+
+  /* Check the DMA peripheral handle */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+  assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
+  assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
+  assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
+  assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
+  assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
+  assert_param(IS_DMA_MODE(hdma->Init.Mode));
+  assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
+
+  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+  {
+    assert_param(IS_DMA_REQUEST(hdma->Init.Request));
+    assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode));
+    /* Check the memory burst, peripheral burst and FIFO threshold parameters only
+       when FIFO mode is enabled */
+    if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE)
+    {
+      assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold));
+      assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
+      assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
+    }
+
+    /* Allocate lock resource */
+    __HAL_UNLOCK(hdma);
+
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+
+    /* Disable the peripheral */
+    __HAL_DMA_DISABLE(hdma);
+
+    /* Check if the DMA Stream is effectively disabled */
+    while((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U)
+    {
+      /* Check for the Timeout */
+      if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
+      {
+        /* Update error code */
+        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+
+        /* Change the DMA state */
+        hdma->State = HAL_DMA_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+    }
+
+    /* Get the CR register value */
+    registerValue = ((DMA_Stream_TypeDef   *)hdma->Instance)->CR;
+
+    /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
+    registerValue &= ((uint32_t)~(DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
+                        DMA_SxCR_PL    | DMA_SxCR_MSIZE  | DMA_SxCR_PSIZE  | \
+                        DMA_SxCR_MINC  | DMA_SxCR_PINC   | DMA_SxCR_CIRC   | \
+                        DMA_SxCR_DIR   | DMA_SxCR_CT     | DMA_SxCR_DBM));
+
+    /* Prepare the DMA Stream configuration */
+    registerValue |=  hdma->Init.Direction           |
+            hdma->Init.PeriphInc           | hdma->Init.MemInc           |
+            hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
+            hdma->Init.Mode                | hdma->Init.Priority;
+
+    /* the Memory burst and peripheral burst are not used when the FIFO is disabled */
+    if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
+    {
+      /* Get memory burst and peripheral burst */
+      registerValue |=  hdma->Init.MemBurst | hdma->Init.PeriphBurst;
+    }
+
+    /* Work around for Errata 2.22: UART/USART- DMA transfer lock: DMA stream could be
+                                    lock when transfering data to/from USART/UART */
+#if (STM32H7_DEV_ID == 0x450UL)
+    if((DBGMCU->IDCODE & 0xFFFF0000U) >= 0x20000000U)
+    {
+#endif /* STM32H7_DEV_ID == 0x450UL */
+      if(IS_DMA_UART_USART_REQUEST(hdma->Init.Request) != 0U)
+      {
+        registerValue |= DMA_SxCR_TRBUFF;
+      }
+#if (STM32H7_DEV_ID == 0x450UL)
+    }
+#endif /* STM32H7_DEV_ID == 0x450UL */
+
+    /* Write to DMA Stream CR register */
+    ((DMA_Stream_TypeDef   *)hdma->Instance)->CR = registerValue;
+
+    /* Get the FCR register value */
+    registerValue = ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR;
+
+    /* Clear Direct mode and FIFO threshold bits */
+    registerValue &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
+
+    /* Prepare the DMA Stream FIFO configuration */
+    registerValue |= hdma->Init.FIFOMode;
+
+    /* the FIFO threshold is not used when the FIFO mode is disabled */
+    if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
+    {
+      /* Get the FIFO threshold */
+      registerValue |= hdma->Init.FIFOThreshold;
+
+      /* Check compatibility between FIFO threshold level and size of the memory burst */
+      /* for INCR4, INCR8, INCR16 */
+      if(hdma->Init.MemBurst != DMA_MBURST_SINGLE)
+      {
+        if (DMA_CheckFifoParam(hdma) != HAL_OK)
+        {
+          /* Update error code */
+          hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
+
+          /* Change the DMA state */
+          hdma->State = HAL_DMA_STATE_READY;
+
+          return HAL_ERROR;
+        }
+      }
+    }
+
+    /* Write to DMA Stream FCR */
+    ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR = registerValue;
+
+    /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
+       DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
+    regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
+
+    /* Clear all interrupt flags */
+    regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
+  }
+  else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */
+  {
+    if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U)
+    {
+      /* Check the request parameter */
+      assert_param(IS_BDMA_REQUEST(hdma->Init.Request));
+    }
+
+    /* Allocate lock resource */
+    __HAL_UNLOCK(hdma);
+
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+
+    /* Get the CR register value */
+    registerValue = ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR;
+
+    /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, MEM2MEM, DBM and CT bits */
+    registerValue &= ((uint32_t)~(BDMA_CCR_PL    | BDMA_CCR_MSIZE   | BDMA_CCR_PSIZE  | \
+                                  BDMA_CCR_MINC  | BDMA_CCR_PINC    | BDMA_CCR_CIRC   | \
+                                  BDMA_CCR_DIR   | BDMA_CCR_MEM2MEM | BDMA_CCR_DBM    | \
+                                  BDMA_CCR_CT));
+
+    /* Prepare the DMA Channel configuration */
+    registerValue |=  DMA_TO_BDMA_DIRECTION(hdma->Init.Direction)            |
+                      DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc)       |
+                      DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc)              |
+                      DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) |
+                      DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment)    |
+                      DMA_TO_BDMA_MODE(hdma->Init.Mode)                      |
+                      DMA_TO_BDMA_PRIORITY(hdma->Init.Priority);
+
+    /* Write to DMA Channel CR register */
+    ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR = registerValue;
+
+    /* calculation of the channel index */
+    hdma->StreamIndex = (((uint32_t)((uint32_t*)hdma->Instance) - (uint32_t)BDMA_Channel0) / ((uint32_t)BDMA_Channel1 - (uint32_t)BDMA_Channel0)) << 2U;
+
+    /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
+    DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
+    regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
+
+    /* Clear all interrupt flags */
+    regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
+  }
+  else
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
+    hdma->State     = HAL_DMA_STATE_ERROR;
+
+    return HAL_ERROR;
+  }
+
+  if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+  {
+    /* Initialize parameters for DMAMUX channel :
+    DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask
+    */
+    DMA_CalcDMAMUXChannelBaseAndMask(hdma);
+
+    if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
+    {
+      /* if memory to memory force the request to 0*/
+      hdma->Init.Request = DMA_REQUEST_MEM2MEM;
+    }
+
+    /* Set peripheral request  to DMAMUX channel */
+    hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);
+
+    /* Clear the DMAMUX synchro overrun flag */
+    hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+    /* Initialize parameters for DMAMUX request generator :
+    if the DMA request is DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR7
+    */
+    if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7))
+    {
+      /* Initialize parameters for DMAMUX request generator :
+      DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */
+      DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
+
+      /* Reset the DMAMUX request generator register */
+      hdma->DMAmuxRequestGen->RGCR = 0U;
+
+      /* Clear the DMAMUX request generator overrun flag */
+      hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+    }
+    else
+    {
+      hdma->DMAmuxRequestGen = 0U;
+      hdma->DMAmuxRequestGenStatus = 0U;
+      hdma->DMAmuxRequestGenStatusMask = 0U;
+    }
+  }
+
+  /* Initialize the error code */
+  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+  /* Initialize the DMA state */
+  hdma->State = HAL_DMA_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the DMA peripheral
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
+{
+  DMA_Base_Registers *regs_dma;
+  BDMA_Base_Registers *regs_bdma;
+
+  /* Check the DMA peripheral handle */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Disable the selected DMA Streamx */
+  __HAL_DMA_DISABLE(hdma);
+
+  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+  {
+    /* Reset DMA Streamx control register */
+    ((DMA_Stream_TypeDef   *)hdma->Instance)->CR   = 0U;
+
+    /* Reset DMA Streamx number of data to transfer register */
+    ((DMA_Stream_TypeDef   *)hdma->Instance)->NDTR = 0U;
+
+    /* Reset DMA Streamx peripheral address register */
+    ((DMA_Stream_TypeDef   *)hdma->Instance)->PAR  = 0U;
+
+    /* Reset DMA Streamx memory 0 address register */
+    ((DMA_Stream_TypeDef   *)hdma->Instance)->M0AR = 0U;
+
+    /* Reset DMA Streamx memory 1 address register */
+    ((DMA_Stream_TypeDef   *)hdma->Instance)->M1AR = 0U;
+
+    /* Reset DMA Streamx FIFO control register */
+    ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR  = (uint32_t)0x00000021U;
+
+    /* Get DMA steam Base Address */
+    regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
+
+    /* Clear all interrupt flags at correct offset within the register */
+    regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
+  }
+  else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */
+  {
+    /* Reset DMA Channel control register */
+    ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR  = 0U;
+
+    /* Reset DMA Channel Number of Data to Transfer register */
+    ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = 0U;
+
+    /* Reset DMA Channel peripheral address register */
+    ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR  = 0U;
+
+    /* Reset DMA Channel memory 0 address register */
+    ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = 0U;
+
+    /* Reset DMA Channel memory 1 address register */
+    ((BDMA_Channel_TypeDef *)hdma->Instance)->CM1AR = 0U;
+
+    /* Get DMA steam Base Address */
+    regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
+
+    /* Clear all interrupt flags at correct offset within the register */
+    regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
+  }
+  else
+  {
+    /* Return error status */
+    return HAL_ERROR;
+  }
+
+  if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+  {
+    /* Initialize parameters for DMAMUX channel :
+    DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */
+    DMA_CalcDMAMUXChannelBaseAndMask(hdma);
+
+    if(hdma->DMAmuxChannel != 0U)
+    {
+      /* Resett he DMAMUX channel that corresponds to the DMA stream */
+      hdma->DMAmuxChannel->CCR = 0U;
+
+      /* Clear the DMAMUX synchro overrun flag */
+      hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+    }
+
+    if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7))
+    {
+      /* Initialize parameters for DMAMUX request generator :
+      DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */
+      DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
+
+      /* Reset the DMAMUX request generator register */
+      hdma->DMAmuxRequestGen->RGCR = 0U;
+
+      /* Clear the DMAMUX request generator overrun flag */
+      hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+    }
+
+    hdma->DMAmuxRequestGen = 0U;
+    hdma->DMAmuxRequestGenStatus = 0U;
+    hdma->DMAmuxRequestGenStatusMask = 0U;
+  }
+
+
+  /* Clean callbacks */
+  hdma->XferCpltCallback       = NULL;
+  hdma->XferHalfCpltCallback   = NULL;
+  hdma->XferM1CpltCallback     = NULL;
+  hdma->XferM1HalfCpltCallback = NULL;
+  hdma->XferErrorCallback      = NULL;
+  hdma->XferAbortCallback      = NULL;
+
+  /* Initialize the error code */
+  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+  /* Initialize the DMA state */
+  hdma->State = HAL_DMA_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdma);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group2
+  *
+@verbatim
+ ===============================================================================
+                      #####  IO operation functions  #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure the source, destination address and data length and Start DMA transfer
+      (+) Configure the source, destination address and data length and
+          Start DMA transfer with interrupt
+      (+) Register and Unregister DMA callbacks
+      (+) Abort DMA transfer
+      (+) Poll for transfer complete
+      (+) Handle DMA interrupt request
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the DMA Transfer.
+  * @param  hdma      : pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @param  SrcAddress: The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  DataLength: The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+  /* Check the DMA peripheral handle */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hdma);
+
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+
+    /* Initialize the error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+    /* Disable the peripheral */
+    __HAL_DMA_DISABLE(hdma);
+
+    /* Configure the source, destination address and the data length */
+    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+    /* Enable the Peripheral */
+    __HAL_DMA_ENABLE(hdma);
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hdma);
+
+    /* Set the error code to busy */
+    hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  return status;
+}
+
+/**
+  * @brief  Start the DMA Transfer with interrupt enabled.
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @param  SrcAddress: The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  DataLength: The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+  /* Check the DMA peripheral handle */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hdma);
+
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+
+    /* Initialize the error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+    /* Disable the peripheral */
+    __HAL_DMA_DISABLE(hdma);
+
+    /* Configure the source, destination address and the data length */
+    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+    {
+      /* Enable Common interrupts*/
+      MODIFY_REG(((DMA_Stream_TypeDef   *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME));
+
+      if(hdma->XferHalfCpltCallback != NULL)
+      {
+        /* Enable Half Transfer IT if corresponding Callback is set */
+        ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  |= DMA_IT_HT;
+      }
+    }
+    else /* BDMA channel */
+    {
+      /* Enable Common interrupts */
+      MODIFY_REG(((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR, (BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE), (BDMA_CCR_TCIE | BDMA_CCR_TEIE));
+
+      if(hdma->XferHalfCpltCallback != NULL)
+      {
+        /*Enable Half Transfer IT if corresponding Callback is set */
+        ((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR  |= BDMA_CCR_HTIE;
+      }
+    }
+
+    if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+    {
+      /* Check if DMAMUX Synchronization is enabled */
+      if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
+      {
+        /* Enable DMAMUX sync overrun IT*/
+        hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
+      }
+
+      if(hdma->DMAmuxRequestGen != 0U)
+      {
+        /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
+        /* enable the request gen overrun IT */
+        hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
+      }
+    }
+
+    /* Enable the Peripheral */
+    __HAL_DMA_ENABLE(hdma);
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hdma);
+
+    /* Set the error code to busy */
+    hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Aborts the DMA Transfer.
+  * @param  hdma  : pointer to a DMA_HandleTypeDef structure that contains
+  *                 the configuration information for the specified DMA Stream.
+  *
+  * @note  After disabling a DMA Stream, a check for wait until the DMA Stream is
+  *        effectively disabled is added. If a Stream is disabled
+  *        while a data transfer is ongoing, the current data will be transferred
+  *        and the Stream will be effectively disabled only after the transfer of
+  *        this single data is finished.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
+{
+  /* calculate DMA base and stream number */
+  DMA_Base_Registers *regs_dma;
+  BDMA_Base_Registers *regs_bdma;
+  const __IO uint32_t *enableRegister;
+
+  uint32_t tickstart = HAL_GetTick();
+
+ /* Check the DMA peripheral handle */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the DMA peripheral state */
+  if(hdma->State != HAL_DMA_STATE_BUSY)
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Disable all the transfer interrupts */
+    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+    {
+       /* Disable DMA All Interrupts  */
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT);
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR &= ~(DMA_IT_FE);
+
+      enableRegister = (__IO uint32_t *)(&(((DMA_Stream_TypeDef   *)hdma->Instance)->CR));
+    }
+    else /* BDMA channel */
+    {
+      /* Disable DMA All Interrupts */
+      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR  &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE);
+
+      enableRegister = (__IO uint32_t *)(&(((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR));
+    }
+
+    if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+    {
+      /* disable the DMAMUX sync overrun IT */
+      hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
+    }
+
+    /* Disable the stream */
+    __HAL_DMA_DISABLE(hdma);
+
+    /* Check if the DMA Stream is effectively disabled */
+    while(((*enableRegister) & DMA_SxCR_EN) != 0U)
+    {
+      /* Check for the Timeout */
+      if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
+      {
+        /* Update error code */
+        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdma);
+
+        /* Change the DMA state */
+        hdma->State = HAL_DMA_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+    }
+
+    /* Clear all interrupt flags at correct offset within the register */
+    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+    {
+      regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+      regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
+    }
+    else /* BDMA channel */
+    {
+      regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
+      regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
+    }
+
+    if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+    {
+      /* Clear the DMAMUX synchro overrun flag */
+      hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+      if(hdma->DMAmuxRequestGen != 0U)
+      {
+        /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT */
+        /* disable the request gen overrun IT */
+        hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
+
+        /* Clear the DMAMUX request generator overrun flag */
+        hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+      }
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+
+    /* Change the DMA state */
+    hdma->State = HAL_DMA_STATE_READY;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Aborts the DMA Transfer in Interrupt mode.
+  * @param  hdma  : pointer to a DMA_HandleTypeDef structure that contains
+  *                 the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
+{
+  BDMA_Base_Registers *regs_bdma;
+
+  /* Check the DMA peripheral handle */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if(hdma->State != HAL_DMA_STATE_BUSY)
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+    return HAL_ERROR;
+  }
+  else
+  {
+    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+    {
+      /* Set Abort State  */
+      hdma->State = HAL_DMA_STATE_ABORT;
+
+      /* Disable the stream */
+      __HAL_DMA_DISABLE(hdma);
+    }
+    else /* BDMA channel */
+    {
+      /* Disable DMA All Interrupts  */
+      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR  &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE);
+
+      /* Disable the channel */
+      __HAL_DMA_DISABLE(hdma);
+
+      if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+      {
+        /* disable the DMAMUX sync overrun IT */
+        hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
+
+        /* Clear all flags */
+        regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
+        regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
+
+        /* Clear the DMAMUX synchro overrun flag */
+        hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+        if(hdma->DMAmuxRequestGen != 0U)
+        {
+          /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
+          /* disable the request gen overrun IT */
+          hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
+
+          /* Clear the DMAMUX request generator overrun flag */
+          hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+        }
+      }
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma);
+
+      /* Change the DMA state */
+      hdma->State = HAL_DMA_STATE_READY;
+
+      /* Call User Abort callback */
+      if(hdma->XferAbortCallback != NULL)
+      {
+        hdma->XferAbortCallback(hdma);
+      }
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Polling for transfer complete.
+  * @param  hdma:          pointer to a DMA_HandleTypeDef structure that contains
+  *                        the configuration information for the specified DMA Stream.
+  * @param  CompleteLevel: Specifies the DMA level complete.
+  * @note   The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead.
+  *         This model could be used for debug purpose.
+  * @note   The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode).
+  * @param  Timeout:       Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t cpltlevel_mask;
+  uint32_t tickstart = HAL_GetTick();
+
+  /* IT status register */
+  __IO uint32_t *isr_reg;
+  /* IT clear flag register */
+  __IO uint32_t *ifcr_reg;
+
+  /* Check the DMA peripheral handle */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if(HAL_DMA_STATE_BUSY != hdma->State)
+  {
+    /* No transfer ongoing */
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+    __HAL_UNLOCK(hdma);
+
+    return HAL_ERROR;
+  }
+
+  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+  {
+    /* Polling mode not supported in circular mode and double buffering mode */
+    if ((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CIRC) != 0U)
+    {
+      hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+      return HAL_ERROR;
+    }
+
+    /* Get the level transfer complete flag */
+    if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
+    {
+      /* Transfer Complete flag */
+      cpltlevel_mask = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU);
+    }
+    else
+    {
+      /* Half Transfer Complete flag */
+      cpltlevel_mask = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU);
+    }
+
+    isr_reg  = &(((DMA_Base_Registers *)hdma->StreamBaseAddress)->ISR);
+    ifcr_reg = &(((DMA_Base_Registers *)hdma->StreamBaseAddress)->IFCR);
+  }
+  else /* BDMA channel */
+  {
+    /* Polling mode not supported in circular mode */
+    if ((((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR & BDMA_CCR_CIRC) != 0U)
+    {
+      hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+      return HAL_ERROR;
+    }
+
+    /* Get the level transfer complete flag */
+    if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
+    {
+      /* Transfer Complete flag */
+      cpltlevel_mask = BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU);
+    }
+    else
+    {
+      /* Half Transfer Complete flag */
+      cpltlevel_mask = BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU);
+    }
+
+    isr_reg  = &(((BDMA_Base_Registers *)hdma->StreamBaseAddress)->ISR);
+    ifcr_reg = &(((BDMA_Base_Registers *)hdma->StreamBaseAddress)->IFCR);
+  }
+
+  while(((*isr_reg) & cpltlevel_mask) == 0U)
+  {
+    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+    {
+      if(((*isr_reg) & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
+      {
+        /* Update error code */
+        hdma->ErrorCode |= HAL_DMA_ERROR_FE;
+
+        /* Clear the FIFO error flag */
+        (*ifcr_reg) = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU);
+      }
+
+      if(((*isr_reg) & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
+      {
+        /* Update error code */
+        hdma->ErrorCode |= HAL_DMA_ERROR_DME;
+
+        /* Clear the Direct Mode error flag */
+        (*ifcr_reg) = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU);
+      }
+
+      if(((*isr_reg) & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
+      {
+        /* Update error code */
+        hdma->ErrorCode |= HAL_DMA_ERROR_TE;
+
+        /* Clear the transfer error flag */
+        (*ifcr_reg) = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU);
+
+        /* Change the DMA state */
+        hdma->State = HAL_DMA_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdma);
+
+        return HAL_ERROR;
+      }
+    }
+    else /* BDMA channel */
+    {
+      if(((*isr_reg) & (BDMA_FLAG_TE0 << (hdma->StreamIndex & 0x1FU))) != 0U)
+      {
+        /* When a DMA transfer error occurs */
+        /* A hardware clear of its EN bits is performed */
+        /* Clear all flags */
+        (*isr_reg) = ((BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU));
+
+        /* Update error code */
+        hdma->ErrorCode = HAL_DMA_ERROR_TE;
+
+        /* Change the DMA state */
+        hdma->State = HAL_DMA_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdma);
+
+        return HAL_ERROR;
+      }
+    }
+
+    /* Check for the Timeout (Not applicable in circular mode)*/
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
+      {
+        /* Update error code */
+        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+
+        /* if timeout then abort the current transfer */
+        /* No need to check return value: as in this case we will return HAL_ERROR with HAL_DMA_ERROR_TIMEOUT error code  */
+        (void) HAL_DMA_Abort(hdma);
+          /*
+            Note that the Abort function will
+              - Clear the transfer error flags
+              - Unlock
+              - Set the State
+          */
+
+        return HAL_ERROR;
+      }
+    }
+
+    if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+    {
+      /* Check for DMAMUX Request generator (if used) overrun status */
+      if(hdma->DMAmuxRequestGen != 0U)
+      {
+        /* if using DMAMUX request generator Check for DMAMUX request generator overrun */
+        if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
+        {
+          /* Clear the DMAMUX request generator overrun flag */
+          hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+
+          /* Update error code */
+          hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
+        }
+      }
+
+      /* Check for DMAMUX Synchronization overrun */
+      if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
+      {
+        /* Clear the DMAMUX synchro overrun flag */
+        hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+        /* Update error code */
+        hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
+      }
+    }
+  }
+
+
+  /* Get the level transfer complete flag */
+  if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
+  {
+    /* Clear the half transfer and transfer complete flags */
+    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+    {
+      (*ifcr_reg) = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << (hdma->StreamIndex & 0x1FU);
+    }
+    else /* BDMA channel */
+    {
+      (*ifcr_reg) = (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU));
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+
+    hdma->State = HAL_DMA_STATE_READY;
+  }
+  else /*CompleteLevel = HAL_DMA_HALF_TRANSFER*/
+  {
+    /* Clear the half transfer and transfer complete flags */
+    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+    {
+      (*ifcr_reg) = (DMA_FLAG_HTIF0_4) << (hdma->StreamIndex & 0x1FU);
+    }
+    else /* BDMA channel */
+    {
+      (*ifcr_reg) = (BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU));
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Handles DMA interrupt request.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Stream.
+  * @retval None
+  */
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
+{
+  uint32_t tmpisr_dma, tmpisr_bdma;
+  uint32_t ccr_reg;
+  __IO uint32_t count = 0U;
+  uint32_t timeout = SystemCoreClock / 9600U;
+
+  /* calculate DMA base and stream number */
+  DMA_Base_Registers  *regs_dma  = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+  BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
+
+  tmpisr_dma  = regs_dma->ISR;
+  tmpisr_bdma = regs_bdma->ISR;
+
+  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U)  /* DMA1 or DMA2 instance */
+  {
+    /* Transfer Error Interrupt management ***************************************/
+    if ((tmpisr_dma & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
+    {
+      if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != 0U)
+      {
+        /* Disable the transfer error interrupt */
+        ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_TE);
+
+        /* Clear the transfer error flag */
+        regs_dma->IFCR = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU);
+
+        /* Update error code */
+        hdma->ErrorCode |= HAL_DMA_ERROR_TE;
+      }
+    }
+    /* FIFO Error Interrupt management ******************************************/
+    if ((tmpisr_dma & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
+    {
+      if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != 0U)
+      {
+        /* Clear the FIFO error flag */
+        regs_dma->IFCR = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU);
+
+        /* Update error code */
+        hdma->ErrorCode |= HAL_DMA_ERROR_FE;
+      }
+    }
+    /* Direct Mode Error Interrupt management ***********************************/
+    if ((tmpisr_dma & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
+    {
+      if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != 0U)
+      {
+        /* Clear the direct mode error flag */
+        regs_dma->IFCR = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU);
+
+        /* Update error code */
+        hdma->ErrorCode |= HAL_DMA_ERROR_DME;
+      }
+    }
+    /* Half Transfer Complete Interrupt management ******************************/
+    if ((tmpisr_dma & (DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
+    {
+      if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U)
+      {
+        /* Clear the half transfer complete flag */
+        regs_dma->IFCR = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU);
+
+        /* Multi_Buffering mode enabled */
+        if(((((DMA_Stream_TypeDef   *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U)
+        {
+          /* Current memory buffer used is Memory 0 */
+          if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U)
+          {
+            if(hdma->XferHalfCpltCallback != NULL)
+            {
+              /* Half transfer callback */
+              hdma->XferHalfCpltCallback(hdma);
+            }
+          }
+          /* Current memory buffer used is Memory 1 */
+          else
+          {
+            if(hdma->XferM1HalfCpltCallback != NULL)
+            {
+              /* Half transfer callback */
+              hdma->XferM1HalfCpltCallback(hdma);
+            }
+          }
+        }
+        else
+        {
+          /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
+          if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U)
+          {
+            /* Disable the half transfer interrupt */
+            ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_HT);
+          }
+
+          if(hdma->XferHalfCpltCallback != NULL)
+          {
+            /* Half transfer callback */
+            hdma->XferHalfCpltCallback(hdma);
+          }
+        }
+      }
+    }
+    /* Transfer Complete Interrupt management ***********************************/
+    if ((tmpisr_dma & (DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
+    {
+      if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U)
+      {
+        /* Clear the transfer complete flag */
+        regs_dma->IFCR = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU);
+
+        if(HAL_DMA_STATE_ABORT == hdma->State)
+        {
+          /* Disable all the transfer interrupts */
+          ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
+          ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR &= ~(DMA_IT_FE);
+
+          if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
+          {
+            ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_HT);
+          }
+
+          /* Clear all interrupt flags at correct offset within the register */
+          regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hdma);
+
+          /* Change the DMA state */
+          hdma->State = HAL_DMA_STATE_READY;
+
+          if(hdma->XferAbortCallback != NULL)
+          {
+            hdma->XferAbortCallback(hdma);
+          }
+          return;
+        }
+
+        if(((((DMA_Stream_TypeDef   *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U)
+        {
+          /* Current memory buffer used is Memory 0 */
+          if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U)
+          {
+            if(hdma->XferM1CpltCallback != NULL)
+            {
+              /* Transfer complete Callback for memory1 */
+              hdma->XferM1CpltCallback(hdma);
+            }
+          }
+          /* Current memory buffer used is Memory 1 */
+          else
+          {
+            if(hdma->XferCpltCallback != NULL)
+            {
+              /* Transfer complete Callback for memory0 */
+              hdma->XferCpltCallback(hdma);
+            }
+          }
+        }
+        /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
+        else
+        {
+          if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U)
+          {
+            /* Disable the transfer complete interrupt */
+            ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_TC);
+
+            /* Process Unlocked */
+            __HAL_UNLOCK(hdma);
+
+            /* Change the DMA state */
+            hdma->State = HAL_DMA_STATE_READY;
+          }
+
+          if(hdma->XferCpltCallback != NULL)
+          {
+            /* Transfer complete callback */
+            hdma->XferCpltCallback(hdma);
+          }
+        }
+      }
+    }
+
+    /* manage error case */
+    if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
+    {
+      if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != 0U)
+      {
+        hdma->State = HAL_DMA_STATE_ABORT;
+
+        /* Disable the stream */
+        __HAL_DMA_DISABLE(hdma);
+
+        do
+        {
+          if (++count > timeout)
+          {
+            break;
+          }
+        }
+        while((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U);
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdma);
+
+        if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U)
+        {
+          /* Change the DMA state to error if DMA disable fails */
+          hdma->State = HAL_DMA_STATE_ERROR;
+        }
+        else
+        {
+          /* Change the DMA state to Ready if DMA disable success */
+          hdma->State = HAL_DMA_STATE_READY;
+        }
+      }
+
+      if(hdma->XferErrorCallback != NULL)
+      {
+        /* Transfer error callback */
+        hdma->XferErrorCallback(hdma);
+      }
+    }
+  }
+  else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U)  /* BDMA instance(s) */
+  {
+    ccr_reg = (((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR);
+
+    /* Half Transfer Complete Interrupt management ******************************/
+    if (((tmpisr_bdma & (BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_HTIE) != 0U))
+    {
+      /* Clear the half transfer complete flag */
+      regs_bdma->IFCR = (BDMA_ISR_HTIF0 << (hdma->StreamIndex & 0x1FU));
+
+      /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */
+      if((ccr_reg & BDMA_CCR_DBM) != 0U)
+      {
+        /* Current memory buffer used is Memory 0 */
+        if((ccr_reg & BDMA_CCR_CT) == 0U)
+        {
+          if(hdma->XferM1HalfCpltCallback != NULL)
+          {
+            /* Half transfer Callback for Memory 1 */
+            hdma->XferM1HalfCpltCallback(hdma);
+          }
+        }
+        /* Current memory buffer used is Memory 1 */
+        else
+        {
+          if(hdma->XferHalfCpltCallback != NULL)
+          {
+            /* Half transfer Callback for Memory 0 */
+            hdma->XferHalfCpltCallback(hdma);
+          }
+        }
+      }
+      else
+      {
+        if((ccr_reg & BDMA_CCR_CIRC) == 0U)
+        {
+          /* Disable the half transfer interrupt */
+          __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
+        }
+
+        /* DMA peripheral state is not updated in Half Transfer */
+        /* but in Transfer Complete case */
+
+       if(hdma->XferHalfCpltCallback != NULL)
+        {
+          /* Half transfer callback */
+          hdma->XferHalfCpltCallback(hdma);
+        }
+      }
+    }
+
+    /* Transfer Complete Interrupt management ***********************************/
+    else if (((tmpisr_bdma & (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TCIE) != 0U))
+    {
+      /* Clear the transfer complete flag */
+      regs_bdma->IFCR = (BDMA_ISR_TCIF0) << (hdma->StreamIndex & 0x1FU);
+
+      /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */
+      if((ccr_reg & BDMA_CCR_DBM) != 0U)
+      {
+        /* Current memory buffer used is Memory 0 */
+        if((ccr_reg & BDMA_CCR_CT) == 0U)
+        {
+          if(hdma->XferM1CpltCallback != NULL)
+          {
+            /* Transfer complete Callback for Memory 1 */
+            hdma->XferM1CpltCallback(hdma);
+          }
+        }
+        /* Current memory buffer used is Memory 1 */
+        else
+        {
+          if(hdma->XferCpltCallback != NULL)
+          {
+            /* Transfer complete Callback for Memory 0 */
+            hdma->XferCpltCallback(hdma);
+          }
+        }
+      }
+      else
+      {
+        if((ccr_reg & BDMA_CCR_CIRC) == 0U)
+        {
+          /* Disable the transfer complete and error interrupt, if the DMA mode is not CIRCULAR */
+          __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hdma);
+
+          /* Change the DMA state */
+          hdma->State = HAL_DMA_STATE_READY;
+        }
+
+        if(hdma->XferCpltCallback != NULL)
+        {
+          /* Transfer complete callback */
+          hdma->XferCpltCallback(hdma);
+        }
+      }
+    }
+    /* Transfer Error Interrupt management **************************************/
+    else if (((tmpisr_bdma & (BDMA_FLAG_TE0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TEIE) != 0U))
+    {
+      /* When a DMA transfer error occurs */
+      /* A hardware clear of its EN bits is performed */
+      /* Disable ALL DMA IT */
+      __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+
+      /* Clear all flags */
+      regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);
+
+      /* Update error code */
+      hdma->ErrorCode = HAL_DMA_ERROR_TE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma);
+
+      /* Change the DMA state */
+      hdma->State = HAL_DMA_STATE_READY;
+
+      if (hdma->XferErrorCallback != NULL)
+      {
+        /* Transfer error callback */
+        hdma->XferErrorCallback(hdma);
+      }
+    }
+    else
+    {
+      /* Nothing To Do */
+    }
+  }
+  else
+  {
+    /* Nothing To Do */
+  }
+}
+
+/**
+  * @brief  Register callbacks
+  * @param  hdma:                 pointer to a DMA_HandleTypeDef structure that contains
+  *                               the configuration information for the specified DMA Stream.
+  * @param  CallbackID:           User Callback identifier
+  *                               a DMA_HandleTypeDef structure as parameter.
+  * @param  pCallback:            pointer to private callback function which has pointer to
+  *                               a DMA_HandleTypeDef structure as parameter.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))
+{
+
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the DMA peripheral handle */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hdma);
+
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    switch (CallbackID)
+    {
+    case  HAL_DMA_XFER_CPLT_CB_ID:
+      hdma->XferCpltCallback = pCallback;
+      break;
+
+    case  HAL_DMA_XFER_HALFCPLT_CB_ID:
+      hdma->XferHalfCpltCallback = pCallback;
+      break;
+
+    case  HAL_DMA_XFER_M1CPLT_CB_ID:
+      hdma->XferM1CpltCallback = pCallback;
+      break;
+
+    case  HAL_DMA_XFER_M1HALFCPLT_CB_ID:
+      hdma->XferM1HalfCpltCallback = pCallback;
+      break;
+
+    case  HAL_DMA_XFER_ERROR_CB_ID:
+      hdma->XferErrorCallback = pCallback;
+      break;
+
+    case  HAL_DMA_XFER_ABORT_CB_ID:
+      hdma->XferAbortCallback = pCallback;
+      break;
+
+    default:
+      break;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdma);
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister callbacks
+  * @param  hdma:                 pointer to a DMA_HandleTypeDef structure that contains
+  *                               the configuration information for the specified DMA Stream.
+  * @param  CallbackID:           User Callback identifier
+  *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the DMA peripheral handle */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hdma);
+
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    switch (CallbackID)
+    {
+    case  HAL_DMA_XFER_CPLT_CB_ID:
+      hdma->XferCpltCallback = NULL;
+      break;
+
+    case  HAL_DMA_XFER_HALFCPLT_CB_ID:
+      hdma->XferHalfCpltCallback = NULL;
+      break;
+
+    case  HAL_DMA_XFER_M1CPLT_CB_ID:
+      hdma->XferM1CpltCallback = NULL;
+      break;
+
+    case  HAL_DMA_XFER_M1HALFCPLT_CB_ID:
+      hdma->XferM1HalfCpltCallback = NULL;
+      break;
+
+    case  HAL_DMA_XFER_ERROR_CB_ID:
+      hdma->XferErrorCallback = NULL;
+      break;
+
+    case  HAL_DMA_XFER_ABORT_CB_ID:
+      hdma->XferAbortCallback = NULL;
+      break;
+
+    case   HAL_DMA_XFER_ALL_CB_ID:
+      hdma->XferCpltCallback = NULL;
+      hdma->XferHalfCpltCallback = NULL;
+      hdma->XferM1CpltCallback = NULL;
+      hdma->XferM1HalfCpltCallback = NULL;
+      hdma->XferErrorCallback = NULL;
+      hdma->XferAbortCallback = NULL;
+      break;
+
+    default:
+      status = HAL_ERROR;
+      break;
+    }
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdma);
+
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group3
+  *
+@verbatim
+ ===============================================================================
+                    ##### State and Errors functions #####
+ ===============================================================================
+    [..]
+    This subsection provides functions allowing to
+      (+) Check the DMA state
+      (+) Get error code
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the DMA state.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Stream.
+  * @retval HAL state
+  */
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
+{
+  return hdma->State;
+}
+
+/**
+  * @brief  Return the DMA error code
+  * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA Stream.
+  * @retval DMA Error Code
+  */
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
+{
+  return hdma->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMA_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Sets the DMA Transfer parameter.
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @param  SrcAddress: The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  DataLength: The length of data to be transferred from source to destination
+  * @retval None
+  */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+  /* calculate DMA base and stream number */
+  DMA_Base_Registers  *regs_dma  = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+  BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
+
+  if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+  {
+    /* Clear the DMAMUX synchro overrun flag */
+    hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+    if(hdma->DMAmuxRequestGen != 0U)
+    {
+      /* Clear the DMAMUX request generator overrun flag */
+      hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+    }
+  }
+
+  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+  {
+    /* Clear all interrupt flags at correct offset within the register */
+    regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
+
+    /* Clear DBM bit */
+    ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= (uint32_t)(~DMA_SxCR_DBM);
+
+    /* Configure DMA Stream data length */
+    ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = DataLength;
+
+    /* Peripheral to Memory */
+    if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+    {
+      /* Configure DMA Stream destination address */
+      ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = DstAddress;
+
+      /* Configure DMA Stream source address */
+      ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = SrcAddress;
+    }
+    /* Memory to Peripheral */
+    else
+    {
+      /* Configure DMA Stream source address */
+      ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = SrcAddress;
+
+      /* Configure DMA Stream destination address */
+      ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = DstAddress;
+    }
+  }
+  else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */
+  {
+    /* Clear all flags */
+    regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);
+
+    /* Configure DMA Channel data length */
+    ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = DataLength;
+
+    /* Peripheral to Memory */
+    if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+    {
+      /* Configure DMA Channel destination address */
+      ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = DstAddress;
+
+      /* Configure DMA Channel source address */
+      ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = SrcAddress;
+    }
+    /* Memory to Peripheral */
+    else
+    {
+      /* Configure DMA Channel source address */
+      ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = SrcAddress;
+
+      /* Configure DMA Channel destination address */
+      ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = DstAddress;
+    }
+  }
+  else
+  {
+    /* Nothing To Do */
+  }
+}
+
+/**
+  * @brief  Returns the DMA Stream base address depending on stream number
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @retval Stream base address
+  */
+static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
+{
+  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+  {
+    uint32_t stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U;
+
+    /* lookup table for necessary bitshift of flags within status registers */
+    static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};
+    hdma->StreamIndex = flagBitshiftOffset[stream_number & 0x7U];
+
+    if (stream_number > 3U)
+    {
+      /* return pointer to HISR and HIFCR */
+      hdma->StreamBaseAddress = (((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)) + 4U);
+    }
+    else
+    {
+      /* return pointer to LISR and LIFCR */
+      hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU));
+    }
+  }
+  else /* BDMA instance(s) */
+  {
+    /* return pointer to ISR and IFCR */
+    hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0xFFU));
+  }
+
+  return hdma->StreamBaseAddress;
+}
+
+/**
+  * @brief  Check compatibility between FIFO threshold level and size of the memory burst
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Memory Data size equal to Byte */
+  if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)
+  {
+    switch (hdma->Init.FIFOThreshold)
+    {
+      case DMA_FIFO_THRESHOLD_1QUARTERFULL:
+      case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
+
+        if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+        {
+          status = HAL_ERROR;
+        }
+        break;
+
+      case DMA_FIFO_THRESHOLD_HALFFULL:
+        if (hdma->Init.MemBurst == DMA_MBURST_INC16)
+        {
+          status = HAL_ERROR;
+        }
+        break;
+
+      case DMA_FIFO_THRESHOLD_FULL:
+        break;
+
+      default:
+        break;
+    }
+  }
+
+  /* Memory Data size equal to Half-Word */
+  else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
+  {
+    switch (hdma->Init.FIFOThreshold)
+    {
+      case DMA_FIFO_THRESHOLD_1QUARTERFULL:
+      case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
+        status = HAL_ERROR;
+        break;
+
+      case DMA_FIFO_THRESHOLD_HALFFULL:
+        if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+        {
+          status = HAL_ERROR;
+        }
+        break;
+
+      case DMA_FIFO_THRESHOLD_FULL:
+        if (hdma->Init.MemBurst == DMA_MBURST_INC16)
+        {
+          status = HAL_ERROR;
+        }
+        break;
+
+      default:
+        break;
+    }
+  }
+
+  /* Memory Data size equal to Word */
+  else
+  {
+    switch (hdma->Init.FIFOThreshold)
+    {
+      case DMA_FIFO_THRESHOLD_1QUARTERFULL:
+      case DMA_FIFO_THRESHOLD_HALFFULL:
+      case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
+        status = HAL_ERROR;
+        break;
+
+      case DMA_FIFO_THRESHOLD_FULL:
+        if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+        {
+          status = HAL_ERROR;
+        }
+    break;
+
+      default:
+        break;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Updates the DMA handle with the DMAMUX  channel and status mask depending on stream number
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)
+{
+  uint32_t stream_number;
+  uint32_t stream_baseaddress = (uint32_t)((uint32_t*)hdma->Instance);
+
+  if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U)
+  {
+    /* BDMA Channels are connected to DMAMUX2 channels */
+    stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 8U) / 20U;
+    hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_Channel0) + (stream_number * 4U)));
+    hdma->DMAmuxChannelStatus = DMAMUX2_ChannelStatus;
+    hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU);
+  }
+  else
+  {
+    /* DMA1/DMA2 Streams are connected to DMAMUX1 channels */
+    stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U;
+
+    if((stream_baseaddress <= ((uint32_t)DMA2_Stream7) ) && \
+       (stream_baseaddress >= ((uint32_t)DMA2_Stream0)))
+    {
+      stream_number += 8U;
+    }
+    hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U)));
+    hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
+    hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU);
+  }
+}
+
+/**
+  * @brief  Updates the DMA handle with the DMAMUX  request generator params
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma)
+{
+  uint32_t request =  hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID;
+
+  if((request >= DMA_REQUEST_GENERATOR0) && (request <= DMA_REQUEST_GENERATOR7))
+  {
+    if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U)
+    {
+      /* BDMA Channels are connected to DMAMUX2 request generator blocks */
+      hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_RequestGenerator0) + ((request - 1U) * 4U)));
+
+      hdma->DMAmuxRequestGenStatus = DMAMUX2_RequestGenStatus;
+    }
+    else
+    {
+      /* DMA1 and DMA2 Streams use DMAMUX1 request generator blocks */
+      hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U)));
+
+      hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
+    }
+
+    hdma->DMAmuxRequestGenStatusMask = 1UL << (request - 1U);
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c
new file mode 100644
index 00000000..6a48d942
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c
@@ -0,0 +1,714 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_dma_ex.c
+  * @author  MCD Application Team
+  * @brief   DMA Extension HAL module driver
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the DMA Extension peripheral:
+  *           + Extended features functions
+  *
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+  The DMA Extension HAL driver can be used as follows:
+   (+) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function
+       for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.
+
+   (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
+   (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
+       Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
+       to respectively enable/disable the request generator.
+
+   (+) To handle the DMAMUX Interrupts, the function  HAL_DMAEx_MUX_IRQHandler should be called from
+       the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler or DMAMUX2_OVR_IRQHandler .
+       As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMA_MUX_IRQHandler should be
+       called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project
+      (exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator)
+
+     -@-  In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.
+     -@-  When Multi (Double) Buffer mode is enabled, the transfer is circular by default.
+     -@-  In Multi (Double) buffer mode, it is possible to update the base address for
+          the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.
+     -@-  Multi (Double) buffer mode is possible with DMA and BDMA instances.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup DMAEx DMAEx
+  * @brief DMA Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private Constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup DMAEx_Private_Functions
+  * @{
+  */
+
+static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+
+/**
+  * @}
+  */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @addtogroup DMAEx_Exported_Functions
+  * @{
+  */
+
+
+/** @addtogroup DMAEx_Exported_Functions_Group1
+  *
+@verbatim
+ ===============================================================================
+                #####  Extended features functions  #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure the source, destination address and data length and
+          Start MultiBuffer DMA transfer
+      (+) Configure the source, destination address and data length and
+          Start MultiBuffer DMA transfer with interrupt
+      (+) Change on the fly the memory0 or memory1 address.
+      (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
+      (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
+      (+) Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
+          to respectively enable/disable the request generator.
+      (+) Handle DMAMUX interrupts using HAL_DMAEx_MUX_IRQHandler : should be called from
+          the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler or DMAMUX2_OVR_IRQHandler
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Starts the multi_buffer DMA Transfer.
+  * @param  hdma      : pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @param  SrcAddress: The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer
+  * @param  DataLength: The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  __IO uint32_t *ifcRegister_Base; /* DMA Stream Interrupt Clear register */
+
+  /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+
+  /* Memory-to-memory transfer not supported in double buffering mode */
+  if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Process Locked */
+    __HAL_LOCK(hdma);
+
+    if(HAL_DMA_STATE_READY == hdma->State)
+    {
+      /* Change DMA peripheral state */
+      hdma->State = HAL_DMA_STATE_BUSY;
+
+      /* Initialize the error code */
+      hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+      if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+      {
+        /* Enable the Double buffer mode */
+        ((DMA_Stream_TypeDef   *)hdma->Instance)->CR |= DMA_SxCR_DBM;
+
+        /* Configure DMA Stream destination address */
+        ((DMA_Stream_TypeDef   *)hdma->Instance)->M1AR = SecondMemAddress;
+
+        /* Calculate the interrupt clear flag register (IFCR) base address  */
+        ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 8U));
+
+        /* Clear all flags */
+        *ifcRegister_Base = 0x3FUL << (hdma->StreamIndex & 0x1FU);
+      }
+      else /* BDMA instance(s) */
+      {
+        /* Enable the Double buffer mode */
+        ((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR |= (BDMA_CCR_DBM | BDMA_CCR_CIRC);
+
+        /* Configure DMA Stream destination address */
+        ((BDMA_Channel_TypeDef   *)hdma->Instance)->CM1AR = SecondMemAddress;
+
+        /* Calculate the interrupt clear flag register (IFCR) base address  */
+        ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 4U));
+
+        /* Clear all flags */
+        *ifcRegister_Base = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);
+      }
+
+      if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+      {
+        /* Configure the source, destination address and the data length */
+        DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+        /* Clear the DMAMUX synchro overrun flag */
+        hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+        if(hdma->DMAmuxRequestGen != 0U)
+        {
+          /* Clear the DMAMUX request generator overrun flag */
+          hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+        }
+      }
+
+      /* Enable the peripheral */
+      __HAL_DMA_ENABLE(hdma);
+    }
+    else
+    {
+      /* Set the error code to busy */
+      hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+      /* Return error status */
+      status = HAL_ERROR;
+    }
+  }
+  return status;
+}
+
+/**
+  * @brief  Starts the multi_buffer DMA Transfer with interrupt enabled.
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @param  SrcAddress: The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer
+  * @param  DataLength: The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  __IO uint32_t *ifcRegister_Base; /* DMA Stream Interrupt Clear register */
+
+  /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+
+  /* Memory-to-memory transfer not supported in double buffering mode */
+  if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hdma);
+
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+
+    /* Initialize the error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+    {
+      /* Enable the Double buffer mode */
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->CR |= DMA_SxCR_DBM;
+
+      /* Configure DMA Stream destination address */
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->M1AR = SecondMemAddress;
+
+      /* Calculate the interrupt clear flag register (IFCR) base address  */
+      ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 8U));
+
+      /* Clear all flags */
+      *ifcRegister_Base = 0x3FUL << (hdma->StreamIndex & 0x1FU);
+    }
+    else /* BDMA instance(s) */
+    {
+      /* Enable the Double buffer mode */
+      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR |= (BDMA_CCR_DBM | BDMA_CCR_CIRC);
+
+      /* Configure DMA Stream destination address */
+      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CM1AR = SecondMemAddress;
+
+      /* Calculate the interrupt clear flag register (IFCR) base address  */
+      ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 4U));
+
+      /* Clear all flags */
+      *ifcRegister_Base = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);
+    }
+
+    /* Configure the source, destination address and the data length */
+    DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+    if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+    {
+      /* Clear the DMAMUX synchro overrun flag */
+      hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+      if(hdma->DMAmuxRequestGen != 0U)
+      {
+        /* Clear the DMAMUX request generator overrun flag */
+        hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+      }
+    }
+
+    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+    {
+      /* Enable Common interrupts*/
+      MODIFY_REG(((DMA_Stream_TypeDef   *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME));
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR |= DMA_IT_FE;
+
+      if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
+      {
+        /*Enable Half Transfer IT if corresponding Callback is set*/
+        ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  |= DMA_IT_HT;
+      }
+    }
+    else /* BDMA instance(s) */
+    {
+      /* Enable Common interrupts*/
+      MODIFY_REG(((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR, (BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE), (BDMA_CCR_TCIE | BDMA_CCR_TEIE));
+
+      if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
+      {
+        /*Enable Half Transfer IT if corresponding Callback is set*/
+        ((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR  |= BDMA_CCR_HTIE;
+      }
+    }
+
+    if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+    {
+      /* Check if DMAMUX Synchronization is enabled*/
+      if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
+      {
+        /* Enable DMAMUX sync overrun IT*/
+        hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
+      }
+
+      if(hdma->DMAmuxRequestGen != 0U)
+      {
+        /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
+        /* enable the request gen overrun IT*/
+        hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
+      }
+    }
+
+    /* Enable the peripheral */
+    __HAL_DMA_ENABLE(hdma);
+  }
+  else
+  {
+    /* Set the error code to busy */
+    hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  return status;
+}
+
+/**
+  * @brief  Change the memory0 or memory1 address on the fly.
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @param  Address:    The new address
+  * @param  memory:     the memory to be changed, This parameter can be one of
+  *                     the following values:
+  *                      MEMORY0 /
+  *                      MEMORY1
+  * @note   The MEMORY0 address can be changed only when the current transfer use
+  *         MEMORY1 and the MEMORY1 address can be changed only when the current
+  *         transfer use MEMORY0.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)
+{
+  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+  {
+    if(memory == MEMORY0)
+    {
+      /* change the memory0 address */
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->M0AR = Address;
+    }
+    else
+    {
+      /* change the memory1 address */
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->M1AR = Address;
+    }
+  }
+  else /* BDMA instance(s) */
+  {
+    if(memory == MEMORY0)
+    {
+      /* change the memory0 address */
+      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CM0AR = Address;
+    }
+    else
+    {
+      /* change the memory1 address */
+      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CM1AR = Address;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the DMAMUX synchronization parameters for a given DMA stream (instance).
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @param  pSyncConfig : pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the DMAMUX synchronization parameters
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)
+{
+  uint32_t syncSignalID = 0;
+  uint32_t syncPolarity = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));
+  assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable));
+  assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable));
+  assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber));
+
+  if(pSyncConfig->SyncEnable == ENABLE)
+  {
+    assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig->SyncPolarity));
+
+    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+    {
+      assert_param(IS_DMA_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));
+    }
+    else
+    {
+      assert_param(IS_BDMA_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));
+    }
+    syncSignalID = pSyncConfig->SyncSignalID;
+    syncPolarity = pSyncConfig->SyncPolarity;
+  }
+
+  /*Check if the DMA state is ready */
+  if(hdma->State == HAL_DMA_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hdma);
+
+    /* Disable the synchronization and event generation before applying a new config */
+    CLEAR_BIT(hdma->DMAmuxChannel->CCR,(DMAMUX_CxCR_SE | DMAMUX_CxCR_EGE));
+
+    /* Set the new synchronization parameters (and keep the request ID filled during the Init)*/
+    MODIFY_REG( hdma->DMAmuxChannel->CCR, \
+               (~DMAMUX_CxCR_DMAREQ_ID) , \
+               (syncSignalID << DMAMUX_CxCR_SYNC_ID_Pos)       | \
+               ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \
+               syncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos)    | \
+               ((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos));
+
+      /* Process Locked */
+    __HAL_UNLOCK(hdma);
+
+    return HAL_OK;
+  }
+  else
+  {
+    /* Set the error code to busy */
+    hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+    /* Return error status */
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the DMAMUX request generator block used by the given DMA stream (instance).
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @param  pRequestGeneratorConfig : pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef :
+  *         contains the request generator parameters.
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
+{
+  HAL_StatusTypeDef status;
+  HAL_DMA_StateTypeDef temp_state = hdma->State;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));
+
+  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+  {
+    assert_param(IS_DMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));
+  }
+  else
+  {
+    assert_param(IS_BDMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));
+  }
+
+
+  assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity));
+  assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber));
+
+  /* check if the DMA state is ready
+     and DMA is using a DMAMUX request generator block
+  */
+  if(hdma->DMAmuxRequestGen == 0U)
+  {
+    /* Set the error code to busy */
+    hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
+
+    /* error status */
+    status = HAL_ERROR;
+  }
+  else if(((hdma->DMAmuxRequestGen->RGCR & DMAMUX_RGxCR_GE) == 0U) && (temp_state == HAL_DMA_STATE_READY))
+  {
+    /* RequestGenerator must be disable prior to the configuration i.e GE bit is 0 */
+
+    /* Process Locked */
+    __HAL_LOCK(hdma);
+
+    /* Set the request generator new parameters */
+    hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \
+                                  ((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GNBREQ_Pos)| \
+                                  pRequestGeneratorConfig->Polarity;
+    /* Process Locked */
+    __HAL_UNLOCK(hdma);
+
+    return HAL_OK;
+  }
+  else
+  {
+    /* Set the error code to busy */
+    hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+    /* error status */
+    status = HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Enable the DMAMUX request generator block used by the given DMA stream (instance).
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));
+
+  /* check if the DMA state is ready
+     and DMA is using a DMAMUX request generator block */
+  if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0U))
+  {
+    /* Enable the request generator*/
+    hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE;
+
+   return HAL_OK;
+ }
+ else
+ {
+   return HAL_ERROR;
+ }
+}
+
+/**
+  * @brief  Disable the DMAMUX request generator block used by the given DMA stream (instance).
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));
+
+  /* check if the DMA state is ready
+     and DMA is using a DMAMUX request generator block */
+  if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0U))
+  {
+    /* Disable the request generator*/
+    hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE;
+
+   return HAL_OK;
+ }
+ else
+ {
+   return HAL_ERROR;
+ }
+}
+
+/**
+  * @brief  Handles DMAMUX interrupt request.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Stream.
+  * @retval None
+  */
+void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma)
+{
+  /* Check for DMAMUX Synchronization overrun */
+  if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
+  {
+    /* Disable the synchro overrun interrupt */
+    hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
+
+    /* Clear the DMAMUX synchro overrun flag */
+    hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+    /* Update error code */
+    hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
+
+    if(hdma->XferErrorCallback != NULL)
+    {
+      /* Transfer error callback */
+      hdma->XferErrorCallback(hdma);
+    }
+  }
+
+  if(hdma->DMAmuxRequestGen != 0)
+  {
+   /* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */
+    if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
+    {
+      /* Disable the request gen overrun interrupt */
+      hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
+
+      /* Clear the DMAMUX request generator overrun flag */
+      hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+
+      /* Update error code */
+      hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
+
+      if(hdma->XferErrorCallback != NULL)
+      {
+        /* Transfer error callback */
+        hdma->XferErrorCallback(hdma);
+      }
+    }
+  }
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMAEx_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Set the DMA Transfer parameter.
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @param  SrcAddress: The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  DataLength: The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+  {
+    /* Configure DMA Stream data length */
+    ((DMA_Stream_TypeDef   *)hdma->Instance)->NDTR = DataLength;
+
+    /* Peripheral to Memory */
+    if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+    {
+      /* Configure DMA Stream destination address */
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->PAR = DstAddress;
+
+      /* Configure DMA Stream source address */
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->M0AR = SrcAddress;
+    }
+    /* Memory to Peripheral */
+    else
+    {
+      /* Configure DMA Stream source address */
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->PAR = SrcAddress;
+
+      /* Configure DMA Stream destination address */
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->M0AR = DstAddress;
+    }
+  }
+  else /* BDMA instance(s) */
+  {
+    /* Configure DMA Stream data length */
+    ((BDMA_Channel_TypeDef   *)hdma->Instance)->CNDTR = DataLength;
+
+    /* Peripheral to Memory */
+    if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+    {
+      /* Configure DMA Stream destination address */
+      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CPAR = DstAddress;
+
+      /* Configure DMA Stream source address */
+      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CM0AR = SrcAddress;
+    }
+    /* Memory to Peripheral */
+    else
+    {
+      /* Configure DMA Stream source address */
+      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CPAR = SrcAddress;
+
+      /* Configure DMA Stream destination address */
+      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CM0AR = DstAddress;
+    }
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c
new file mode 100644
index 00000000..ffb5deef
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c
@@ -0,0 +1,877 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_exti.c
+  * @author  MCD Application Team
+  * @brief   EXTI HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the General Purpose Input/Output (EXTI) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *
+  @verbatim
+  ==============================================================================
+                    ##### EXTI Peripheral features #####
+  ==============================================================================
+  [..]
+    (+) Each Exti line can be configured within this driver.
+
+    (+) Exti line can be configured in 3 different modes
+        (++) Interrupt (CORE1 or CORE2 in case of dual core line )
+        (++) Event (CORE1 or CORE2 in case of dual core line )
+        (++) a combination of the previous
+
+    (+) Configurable Exti lines can be configured with 3 different triggers
+        (++) Rising
+        (++) Falling
+        (++) Both of them
+
+    (+) When set in interrupt mode, configurable Exti lines have two diffenrents
+        interrupt pending registers which allow to distinguish which transition
+        occurs:
+        (++) Rising edge pending interrupt
+        (++) Falling
+
+    (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
+        be selected throught multiplexer.
+
+    (+) PendClearSource used to set the D3 Smart Run Domain autoamtic pend clear soure.
+        It is applicable for line with wkaeup target is Any (CPU1 , CPU2 and D3 smart run domain).
+        Value can be one of the following:
+        (++)  EXTI_D3_PENDCLR_SRC_NONE : no pend clear source is selcted :
+              In this case corresponding bit of D2PMRx register is set to 0
+                (+++) On a configurable Line : the D3 domain wakeup signal is
+                      automatically cleared after after the Delay + Rising Edge detect
+                (+++) On a direct Line : the D3 domain wakeup signal is
+                      cleared after the direct event input signal is cleared
+
+        (++)  EXTI_D3_PENDCLR_SRC_DMACH6 : no pend clear source is selcted :
+              In this case corresponding bit of D2PMRx register is set to 1
+              and corresponding bits(2) of D3PCRxL/H is set to b00 :
+                DMA ch6 event selected as D3 domain pendclear source
+
+        (++)  EXTI_D3_PENDCLR_SRC_DMACH7 : no pend clear source is selcted :
+              In this case corresponding bit of D2PMRx register is set to 1
+              and corresponding bits(2) of D3PCRxL/H is set to b01 :
+                DMA ch7 event selected as D3 domain pendclear source
+
+        (++)  EXTI_D3_PENDCLR_SRC_LPTIM4 : no pend clear source is selcted :
+              In this case corresponding bit of D2PMRx register is set to 1
+              and corresponding bits(2) of D3PCRxL/H is set to b10 :
+                LPTIM4 out selected as D3 domain pendclear source
+
+        (++)  EXTI_D3_PENDCLR_SRC_LPTIM5 : no pend clear source is selcted :
+              In this case corresponding bit of D2PMRx register is set to 1
+              and corresponding bits(2) of D3PCRxL/H is set to b11 :
+                LPTIM5 out selected as D3 domain pendclear source
+
+
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+
+    (#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
+        (++) Choose the interrupt line number by setting "Line" member from
+             EXTI_ConfigTypeDef structure.
+        (++) Configure the interrupt and/or event mode using "Mode" member from
+             EXTI_ConfigTypeDef structure.
+        (++) For configurable lines, configure rising and/or falling trigger
+             "Trigger" member from EXTI_ConfigTypeDef structure.
+        (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
+             member from GPIO_InitTypeDef structure.
+        (++) For Exti lines with wkaeup target is Any (CPU1 , CPU2 and D3 smart run domain),
+             choose gpio D3 PendClearSource using PendClearSource
+             member from EXTI_PendClear_Source structure.
+
+    (#) Get current Exti configuration of a dedicated line using
+        HAL_EXTI_GetConfigLine().
+        (++) Provide exiting handle as parameter.
+        (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
+
+    (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
+        (++) Provide exiting handle as parameter.
+
+    (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
+        (++) Provide exiting handle as first parameter.
+        (++) Provide which callback will be registered using one value from
+             EXTI_CallbackIDTypeDef.
+        (++) Provide callback function pointer.
+
+    (#) Get interrupt pending bit using HAL_EXTI_GetPending().
+
+    (#) Clear interrupt pending bit using HAL_EXTI_GetPending().
+
+    (#) Generate software interrupt using HAL_EXTI_GenerateSWI().
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup EXTI
+  * @{
+  */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines ------------------------------------------------------------*/
+/** @defgroup EXTI_Private_Constants EXTI Private Constants
+  * @{
+  */
+#define EXTI_MODE_OFFSET                    0x04U   /* 0x10: offset between CPU IMR/EMR registers */
+#define EXTI_CONFIG_OFFSET                  0x08U   /* 0x20: offset between CPU Rising/Falling configuration registers */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup EXTI_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup EXTI_Exported_Functions_Group1
+ *  @brief    Configuration functions
+ *
+@verbatim
+ ===============================================================================
+              ##### Configuration functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Set configuration of a dedicated Exti line.
+  * @param  hexti Exti handle.
+  * @param  pExtiConfig Pointer on EXTI configuration to be set.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
+{
+  __IO uint32_t *regaddr;
+  uint32_t regval;
+  uint32_t linepos;
+  uint32_t maskline;
+  uint32_t offset;
+  uint32_t pcrlinepos;
+
+  /* Check null pointer */
+  if ((hexti == NULL) || (pExtiConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(pExtiConfig->Line));
+  assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
+
+  /* Assign line number to handle */
+  hexti->Line = pExtiConfig->Line;
+
+  /* compute line register offset and line mask */
+  offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
+  maskline = (1UL << linepos);
+
+  /* Configure triggers for configurable lines */
+  if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00U)
+  {
+    assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
+
+    /* Configure rising trigger */
+    regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = *regaddr;
+
+    /* Mask or set line */
+    if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00U)
+    {
+      regval |= maskline;
+    }
+    else
+    {
+      regval &= ~maskline;
+    }
+
+    /* Store rising trigger mode */
+    *regaddr = regval;
+
+    /* Configure falling trigger */
+    regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = *regaddr;
+
+    /* Mask or set line */
+    if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00U)
+    {
+      regval |= maskline;
+    }
+    else
+    {
+      regval &= ~maskline;
+    }
+
+    /* Store falling trigger mode */
+    *regaddr = regval;
+
+    /* Configure gpio port selection in case of gpio exti line */
+    if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
+    {
+      assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
+      assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+      regval = SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL];
+      regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03U)));
+      regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03U)));
+      SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL] = regval;
+    }
+  }
+
+  /* Configure interrupt mode : read current mode */
+  regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = *regaddr;
+
+  /* Mask or set line */
+  if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00U)
+  {
+    regval |= maskline;
+  }
+  else
+  {
+    regval &= ~maskline;
+  }
+
+  /* Store interrupt mode */
+  *regaddr = regval;
+
+  /* The event mode cannot be configured if the line does not support it */
+  assert_param(((pExtiConfig->Line & EXTI_EVENT) == EXTI_EVENT) || ((pExtiConfig->Mode & EXTI_MODE_EVENT) != EXTI_MODE_EVENT));
+
+  /* Configure event mode : read current mode */
+  regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = *regaddr;
+
+  /* Mask or set line */
+  if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00U)
+  {
+    regval |= maskline;
+  }
+  else
+  {
+    regval &= ~maskline;
+  }
+
+  /* Store event mode */
+  *regaddr = regval;
+
+#if defined (DUAL_CORE)
+  /* Configure interrupt mode for Core2 : read current mode */
+  regaddr = (__IO uint32_t *)(&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = *regaddr;
+
+  /* Mask or set line */
+  if ((pExtiConfig->Mode & EXTI_MODE_CORE2_INTERRUPT) != 0x00U)
+  {
+    regval |= maskline;
+  }
+  else
+  {
+    regval &= ~maskline;
+  }
+
+  /* Store interrupt mode */
+  *regaddr = regval;
+
+  /* The event mode cannot be configured if the line does not support it */
+  assert_param(((pExtiConfig->Line & EXTI_EVENT) == EXTI_EVENT) || ((pExtiConfig->Mode & EXTI_MODE_CORE2_EVENT) != EXTI_MODE_CORE2_EVENT));
+
+  /* Configure event mode : read current mode */
+  regaddr = (__IO uint32_t *)(&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = *regaddr;
+
+  /* Mask or set line */
+  if ((pExtiConfig->Mode & EXTI_MODE_CORE2_EVENT) != 0x00U)
+  {
+    regval |= maskline;
+  }
+  else
+  {
+    regval &= ~maskline;
+  }
+
+  /* Store event mode */
+  *regaddr = regval;
+#endif /* DUAL_CORE */
+
+  /* Configure the D3 PendClear source in case of Wakeup target is Any */
+  if ((pExtiConfig->Line & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL)
+  {
+    assert_param(IS_EXTI_D3_PENDCLR_SRC(pExtiConfig->PendClearSource));
+
+    /*Calc the PMR register address for the given line */
+    regaddr = (__IO uint32_t *)(&EXTI->D3PMR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = *regaddr;
+
+    if(pExtiConfig->PendClearSource == EXTI_D3_PENDCLR_SRC_NONE)
+    {
+      /* Clear D3PMRx register for the given line */
+      regval &= ~maskline;
+      /* Store D3PMRx register value */
+      *regaddr = regval;
+    }
+    else
+    {
+      /* Set D3PMRx register to 1 for the given line */
+      regval |= maskline;
+      /* Store D3PMRx register value */
+      *regaddr = regval;
+
+      if(linepos < 16UL)
+      {
+        regaddr = (__IO uint32_t *)(&EXTI->D3PCR1L + (EXTI_CONFIG_OFFSET * offset));
+        pcrlinepos = 1UL << linepos;
+      }
+      else
+      {
+        regaddr = (__IO uint32_t *)(&EXTI->D3PCR1H + (EXTI_CONFIG_OFFSET * offset));
+        pcrlinepos = 1UL << (linepos - 16UL);
+      }
+
+      regval = (*regaddr & (~(pcrlinepos * pcrlinepos * 3UL))) | (pcrlinepos * pcrlinepos * (pExtiConfig->PendClearSource - 1UL));
+      *regaddr = regval;
+    }
+  }
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Get configuration of a dedicated Exti line.
+  * @param  hexti Exti handle.
+  * @param  pExtiConfig Pointer on structure to store Exti configuration.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
+{
+  __IO uint32_t *regaddr;
+  uint32_t regval;
+  uint32_t linepos;
+  uint32_t maskline;
+  uint32_t offset;
+  uint32_t pcrlinepos;
+
+  /* Check null pointer */
+  if ((hexti == NULL) || (pExtiConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameter */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+
+  /* Store handle line number to configuration structure */
+  pExtiConfig->Line = hexti->Line;
+
+  /* compute line register offset and line mask */
+  offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
+  maskline = (1UL << linepos);
+
+  /* 1] Get core mode : interrupt */
+  regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = *regaddr;
+
+  pExtiConfig->Mode = EXTI_MODE_NONE;
+
+  /* Check if selected line is enable */
+  if ((regval & maskline) != 0x00U)
+  {
+    pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
+  }
+
+  /* Get event mode */
+  regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = *regaddr;
+
+  /* Check if selected line is enable */
+  if ((regval & maskline) != 0x00U)
+  {
+    pExtiConfig->Mode |= EXTI_MODE_EVENT;
+  }
+#if defined (DUAL_CORE)
+  regaddr = (__IO uint32_t *)(&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = *regaddr;
+
+  /* Check if selected line is enable */
+  if ((regval & maskline) != 0x00U)
+  {
+    pExtiConfig->Mode = EXTI_MODE_CORE2_INTERRUPT;
+  }
+
+  /* Get event mode */
+  regaddr = (__IO uint32_t *)(&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = *regaddr;
+
+  /* Check if selected line is enable */
+  if ((regval & maskline) != 0x00U)
+  {
+    pExtiConfig->Mode |= EXTI_MODE_CORE2_EVENT;
+  }
+#endif /*DUAL_CORE*/
+
+  /* 2] Get trigger for configurable lines : rising */
+  if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00U)
+  {
+    regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = *regaddr;
+
+    /* Check if configuration of selected line is enable */
+    if ((regval & maskline) != 0x00U)
+    {
+      pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
+    }
+    else
+    {
+      pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
+    }
+
+    /* Get falling configuration */
+    regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = *regaddr;
+
+    /* Check if configuration of selected line is enable */
+    if ((regval & maskline) != 0x00U)
+    {
+      pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
+    }
+
+    /* Get Gpio port selection for gpio lines */
+    if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
+    {
+      assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+      regval = SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL];
+      pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3UL - (linepos & 0x03UL)))) >> 24U);
+    }
+    else
+    {
+      pExtiConfig->GPIOSel = 0x00U;
+    }
+  }
+  else
+  {
+    pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
+    pExtiConfig->GPIOSel = 0x00U;
+  }
+
+  /* 3] Get D3 Pend Clear source */
+  if ((pExtiConfig->Line & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL)
+  {
+    regaddr = (__IO uint32_t *)(&EXTI->D3PMR1 + (EXTI_CONFIG_OFFSET * offset));
+    if(((*regaddr) & linepos) == 0UL)
+    {
+      /* if PMR unset, then no pend clear source is used */
+      pExtiConfig->PendClearSource = EXTI_D3_PENDCLR_SRC_NONE;
+    }
+    else
+    {
+      /* if wakeup target is any and PMR set, the read pend clear source from  D3PCRxL/H */
+      if(linepos < 16UL)
+      {
+        regaddr = (__IO uint32_t *)(&EXTI->D3PCR1L + (EXTI_CONFIG_OFFSET * offset));
+        pcrlinepos = 1UL << linepos;
+      }
+      else
+      {
+        regaddr = (__IO uint32_t *)(&EXTI->D3PCR1H + (EXTI_CONFIG_OFFSET * offset));
+        pcrlinepos = 1UL << (linepos - 16UL);
+      }
+
+      pExtiConfig->PendClearSource = 1UL + ((*regaddr & (pcrlinepos * pcrlinepos * 3UL)) / (pcrlinepos * pcrlinepos));
+    }
+  }
+  else
+  {
+    /* if line wakeup target is not any, then no pend clear source is used  */
+    pExtiConfig->PendClearSource = EXTI_D3_PENDCLR_SRC_NONE;
+  }
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Clear whole configuration of a dedicated Exti line.
+  * @param  hexti Exti handle.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
+{
+  __IO uint32_t *regaddr;
+  uint32_t regval;
+  uint32_t linepos;
+  uint32_t maskline;
+  uint32_t offset;
+  uint32_t pcrlinepos;
+
+  /* Check null pointer */
+  if (hexti == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameter */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+
+  /* compute line register offset and line mask */
+  offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  linepos = (hexti->Line & EXTI_PIN_MASK);
+  maskline = (1UL << linepos);
+
+  /* 1] Clear interrupt mode */
+  regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = (*regaddr & ~maskline);
+  *regaddr = regval;
+
+  /* 2] Clear event mode */
+  regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = (*regaddr & ~maskline);
+  *regaddr = regval;
+
+#if defined (DUAL_CORE)
+    /* 1] Clear CM4 interrupt mode */
+  regaddr = (__IO uint32_t *)(&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = (*regaddr & ~maskline);
+  *regaddr = regval;
+
+  /* 2] Clear CM4 event mode */
+  regaddr = (__IO uint32_t *)(&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = (*regaddr & ~maskline);
+  *regaddr = regval;
+#endif /* DUAL_CORE */
+
+  /* 3] Clear triggers in case of configurable lines */
+  if ((hexti->Line & EXTI_CONFIG) != 0x00U)
+  {
+    regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = (*regaddr & ~maskline);
+    *regaddr = regval;
+
+    regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = (*regaddr & ~maskline);
+    *regaddr = regval;
+
+    /* Get Gpio port selection for gpio lines */
+    if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
+    {
+      assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+      regval = SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL];
+      regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03UL)));
+      SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL] = regval;
+    }
+  }
+
+  /* 4] Clear D3 Config lines */
+  if ((hexti->Line & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL)
+  {
+    regaddr = (__IO uint32_t *)(&EXTI->D3PMR1 + (EXTI_CONFIG_OFFSET * offset));
+    *regaddr = (*regaddr & ~maskline);
+
+    if(linepos < 16UL)
+    {
+      regaddr = (__IO uint32_t *)(&EXTI->D3PCR1L + (EXTI_CONFIG_OFFSET * offset));
+      pcrlinepos = 1UL << linepos;
+    }
+    else
+    {
+      regaddr = (__IO uint32_t *)(&EXTI->D3PCR1H + (EXTI_CONFIG_OFFSET * offset));
+      pcrlinepos = 1UL << (linepos - 16UL);
+    }
+
+    /*Clear D3 PendClear source */
+    *regaddr &= (~(pcrlinepos * pcrlinepos * 3UL));
+  }
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Register callback for a dedicated Exti line.
+  * @param  hexti Exti handle.
+  * @param  CallbackID User callback identifier.
+  *         This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
+  * @param  pPendingCbfn function pointer to be stored as callback.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check null pointer */
+  if (hexti == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  switch (CallbackID)
+  {
+    case  HAL_EXTI_COMMON_CB_ID:
+      hexti->PendingCallback = pPendingCbfn;
+      break;
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  return status;
+}
+
+
+/**
+  * @brief  Store line number as handle private field.
+  * @param  hexti Exti handle.
+  * @param  ExtiLine Exti line number.
+  *         This parameter can be from 0 to @ref EXTI_LINE_NB.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
+{
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(ExtiLine));
+
+  /* Check null pointer */
+  if (hexti == NULL)
+  {
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Store line number as handle private field */
+    hexti->Line = ExtiLine;
+
+    return HAL_OK;
+  }
+}
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup EXTI_Exported_Functions_Group2
+ *  @brief EXTI IO functions.
+ *
+@verbatim
+ ===============================================================================
+                       ##### IO operation functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Handle EXTI interrupt request.
+  * @param  hexti Exti handle.
+  * @retval none.
+  */
+void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
+{
+  __IO uint32_t *regaddr;
+  uint32_t regval;
+  uint32_t maskline;
+  uint32_t offset;
+
+  /* Compute line register offset and line mask */
+  offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  maskline = (1UL << (hexti->Line & EXTI_PIN_MASK));
+
+#if defined(DUAL_CORE)
+  if (HAL_GetCurrentCPUID() == CM7_CPUID)
+  {
+    /* Get pending register address */
+    regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
+  }
+  else /* Cortex-M4*/
+  {
+    /* Get pending register address */
+    regaddr = (__IO uint32_t *)(&EXTI->C2PR1 + (EXTI_MODE_OFFSET * offset));
+  }
+#else
+  regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
+#endif /* DUAL_CORE */
+
+  /* Get pending bit  */
+  regval = (*regaddr & maskline);
+
+  if (regval != 0x00U)
+  {
+    /* Clear pending bit */
+    *regaddr = maskline;
+
+    /* Call callback */
+    if (hexti->PendingCallback != NULL)
+    {
+      hexti->PendingCallback();
+    }
+  }
+}
+
+
+/**
+  * @brief  Get interrupt pending bit of a dedicated line.
+  * @param  hexti Exti handle.
+  * @param  Edge Specify which pending edge as to be checked.
+  *         This parameter can be one of the following values:
+  *           @arg @ref EXTI_TRIGGER_RISING_FALLING
+  *         This parameter is kept for compatibility with other series.
+  * @retval 1 if interrupt is pending else 0.
+  */
+uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
+{
+  __IO uint32_t *regaddr;
+  uint32_t regval;
+  uint32_t linepos;
+  uint32_t maskline;
+  uint32_t offset;
+
+  /* Check parameters */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+  assert_param(IS_EXTI_PENDING_EDGE(Edge));
+
+  /* compute line register offset and line mask */
+  offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  linepos = (hexti->Line & EXTI_PIN_MASK);
+  maskline = (1UL << linepos);
+
+#if defined(DUAL_CORE)
+  if (HAL_GetCurrentCPUID() == CM7_CPUID)
+  {
+    /* Get pending register address */
+    regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
+  }
+  else /* Cortex-M4 */
+  {
+    /* Get pending register address */
+    regaddr = (__IO uint32_t *)(&EXTI->C2PR1 + (EXTI_MODE_OFFSET * offset));
+  }
+#else
+  regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
+#endif /* DUAL_CORE */
+
+  /* return 1 if bit is set else 0 */
+  regval = ((*regaddr & maskline) >> linepos);
+  return regval;
+}
+
+
+/**
+  * @brief  Clear interrupt pending bit of a dedicated line.
+  * @param  hexti Exti handle.
+  * @param  Edge Specify which pending edge as to be clear.
+  *         This parameter can be one of the following values:
+  *           @arg @ref EXTI_TRIGGER_RISING_FALLING
+  *         This parameter is kept for compatibility with other series.
+  * @retval None.
+  */
+void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
+{
+  __IO uint32_t *regaddr;
+  uint32_t maskline;
+  uint32_t offset;
+
+  /* Check parameters */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+  assert_param(IS_EXTI_PENDING_EDGE(Edge));
+
+  /* compute line register offset and line mask */
+  offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  maskline = (1UL << (hexti->Line & EXTI_PIN_MASK));
+
+#if defined(DUAL_CORE)
+  if (HAL_GetCurrentCPUID() == CM7_CPUID)
+  {
+    /* Get pending register address */
+    regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
+  }
+  else /* Cortex-M4 */
+  {
+    /* Get pending register address */
+    regaddr = (__IO uint32_t *)(&EXTI->C2PR1 + (EXTI_MODE_OFFSET * offset));
+  }
+#else
+  regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
+#endif /* DUAL_CORE */
+
+  /* Clear Pending bit */
+  *regaddr =  maskline;
+}
+
+/**
+  * @brief  Generate a software interrupt for a dedicated line.
+  * @param  hexti Exti handle.
+  * @retval None.
+  */
+void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
+{
+  __IO uint32_t *regaddr;
+  uint32_t maskline;
+  uint32_t offset;
+
+  /* Check parameters */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+
+  /* compute line register offset and line mask */
+  offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  maskline = (1UL << (hexti->Line & EXTI_PIN_MASK));
+
+  regaddr = (__IO uint32_t *)(&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset));
+  *regaddr = maskline;
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_EXTI_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c
new file mode 100644
index 00000000..7505fd5a
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c
@@ -0,0 +1,6169 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_fdcan.c
+  * @author  MCD Application Team
+  * @brief   FDCAN HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Flexible DataRate Controller Area Network
+  *          (FDCAN) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Configuration and Control functions
+  *           + Peripheral State and Error functions
+  *
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      (#) Initialize the FDCAN peripheral using HAL_FDCAN_Init function.
+
+      (#) If needed , configure the reception filters and optional features using
+          the following configuration functions:
+            (++) HAL_FDCAN_ConfigClockCalibration
+            (++) HAL_FDCAN_ConfigFilter
+            (++) HAL_FDCAN_ConfigGlobalFilter
+            (++) HAL_FDCAN_ConfigExtendedIdMask
+            (++) HAL_FDCAN_ConfigRxFifoOverwrite
+            (++) HAL_FDCAN_ConfigFifoWatermark
+            (++) HAL_FDCAN_ConfigRamWatchdog
+            (++) HAL_FDCAN_ConfigTimestampCounter
+            (++) HAL_FDCAN_EnableTimestampCounter
+            (++) HAL_FDCAN_DisableTimestampCounter
+            (++) HAL_FDCAN_ConfigTimeoutCounter
+            (++) HAL_FDCAN_EnableTimeoutCounter
+            (++) HAL_FDCAN_DisableTimeoutCounter
+            (++) HAL_FDCAN_ConfigTxDelayCompensation
+            (++) HAL_FDCAN_EnableTxDelayCompensation
+            (++) HAL_FDCAN_DisableTxDelayCompensation
+            (++) HAL_FDCAN_EnableISOMode
+            (++) HAL_FDCAN_DisableISOMode
+            (++) HAL_FDCAN_EnableEdgeFiltering
+            (++) HAL_FDCAN_DisableEdgeFiltering
+            (++) HAL_FDCAN_TT_ConfigOperation
+            (++) HAL_FDCAN_TT_ConfigReferenceMessage
+            (++) HAL_FDCAN_TT_ConfigTrigger
+
+      (#) Start the FDCAN module using HAL_FDCAN_Start function. At this level
+          the node is active on the bus: it can send and receive messages.
+
+      (#) The following Tx control functions can only be called when the FDCAN
+          module is started:
+            (++) HAL_FDCAN_AddMessageToTxFifoQ
+            (++) HAL_FDCAN_EnableTxBufferRequest
+            (++) HAL_FDCAN_AbortTxRequest
+
+      (#) After having submitted a Tx request in Tx Fifo or Queue, it is possible to
+          get Tx buffer location used to place the Tx request thanks to
+          HAL_FDCAN_GetLatestTxFifoQRequestBuffer API.
+          It is then possible to abort later on the corresponding Tx Request using
+          HAL_FDCAN_AbortTxRequest API.
+
+      (#) When a message is received into the FDCAN message RAM, it can be
+          retrieved using the HAL_FDCAN_GetRxMessage function.
+
+      (#) Calling the HAL_FDCAN_Stop function stops the FDCAN module by entering
+          it to initialization mode and re-enabling access to configuration
+          registers through the configuration functions listed here above.
+
+      (#) All other control functions can be called any time after initialization
+          phase, no matter if the FDCAN module is started or stoped.
+
+      *** Polling mode operation ***
+      ==============================
+
+    [..]
+        (#) Reception and transmission states can be monitored via the following
+            functions:
+              (++) HAL_FDCAN_IsRxBufferMessageAvailable
+              (++) HAL_FDCAN_IsTxBufferMessagePending
+              (++) HAL_FDCAN_GetRxFifoFillLevel
+              (++) HAL_FDCAN_GetTxFifoFreeLevel
+
+      *** Interrupt mode operation ***
+      ================================
+      [..]
+        (#) There are two interrupt lines: line 0 and 1.
+            By default, all interrupts are assigned to line 0. Interrupt lines
+            can be configured using HAL_FDCAN_ConfigInterruptLines function.
+
+        (#) Notifications are activated using HAL_FDCAN_ActivateNotification
+            function. Then, the process can be controlled through one of the
+            available user callbacks: HAL_FDCAN_xxxCallback.
+
+  *** Callback registration ***
+  =============================================
+
+  The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS when set to 1
+  allows the user to configure dynamically the driver callbacks.
+  Use Function @ref HAL_FDCAN_RegisterCallback() or HAL_FDCAN_RegisterXXXCallback()
+  to register an interrupt callback.
+
+  Function @ref HAL_FDCAN_RegisterCallback() allows to register following callbacks:
+    (+) TxFifoEmptyCallback          : Tx Fifo Empty Callback.
+    (+) RxBufferNewMessageCallback   : Rx Buffer New Message Callback.
+    (+) HighPriorityMessageCallback  : High Priority Message Callback.
+    (+) TimestampWraparoundCallback  : Timestamp Wraparound Callback.
+    (+) TimeoutOccurredCallback      : Timeout Occurred Callback.
+    (+) ErrorCallback                : Error Callback.
+    (+) MspInitCallback              : FDCAN MspInit.
+    (+) MspDeInitCallback            : FDCAN MspDeInit.
+  This function takes as parameters the HAL peripheral handle, the Callback ID
+  and a pointer to the user callback function.
+
+  For specific callbacks ClockCalibrationCallback, TxEventFifoCallback, RxFifo0Callback, RxFifo1Callback,
+  TxBufferCompleteCallback, TxBufferAbortCallback, ErrorStatusCallback, TT_ScheduleSyncCallback, TT_TimeMarkCallback,
+  TT_StopWatchCallback and TT_GlobalTimeCallback, use dedicated register callbacks :
+  respectively @ref HAL_FDCAN_RegisterClockCalibrationCallback(), @ref HAL_FDCAN_RegisterTxEventFifoCallback(),
+  @ref HAL_FDCAN_RegisterRxFifo0Callback(), @ref HAL_FDCAN_RegisterRxFifo1Callback(),
+  @ref HAL_FDCAN_RegisterTxBufferCompleCallback(), @ref HAL_FDCAN_RegisterTxBufferAbortCallback(),
+  @ref HAL_FDCAN_RegisterErrorStatusCallback(), @ref HAL_FDCAN_TT_RegisterScheduleSyncCallback(),
+  @ref HAL_FDCAN_TT_RegisterTimeMarkCallback(), @ref HAL_FDCAN_TT_RegisterStopWatchCallback() and
+  @ref HAL_FDCAN_TT_RegisterGlobalTimeCallback().
+
+  Use function @ref HAL_FDCAN_UnRegisterCallback() to reset a callback to the default
+  weak function.
+  @ref HAL_FDCAN_UnRegisterCallback takes as parameters the HAL peripheral handle,
+  and the Callback ID.
+  This function allows to reset following callbacks:
+    (+) TxFifoEmptyCallback          : Tx Fifo Empty Callback.
+    (+) RxBufferNewMessageCallback   : Rx Buffer New Message Callback.
+    (+) HighPriorityMessageCallback  : High Priority Message Callback.
+    (+) TimestampWraparoundCallback  : Timestamp Wraparound Callback.
+    (+) TimeoutOccurredCallback      : Timeout Occurred Callback.
+    (+) ErrorCallback                : Error Callback.
+    (+) MspInitCallback              : FDCAN MspInit.
+    (+) MspDeInitCallback            : FDCAN MspDeInit.
+
+  For specific callbacks ClockCalibrationCallback, TxEventFifoCallback, RxFifo0Callback,
+  RxFifo1Callback, TxBufferCompleteCallback, TxBufferAbortCallback, TT_ScheduleSyncCallback,
+  TT_TimeMarkCallback, TT_StopWatchCallback and TT_GlobalTimeCallback, use dedicated
+  register callbacks : respectively @ref HAL_FDCAN_UnRegisterClockCalibrationCallback(),
+  @ref HAL_FDCAN_UnRegisterTxEventFifoCallback(), @ref HAL_FDCAN_UnRegisterRxFifo0Callback(),
+  @ref HAL_FDCAN_UnRegisterRxFifo1Callback(), @ref HAL_FDCAN_UnRegisterTxBufferCompleCallback(),
+  @ref HAL_FDCAN_UnRegisterTxBufferAbortCallback(), @ref HAL_FDCAN_UnRegisterErrorStatusCallback(),
+  @ref HAL_FDCAN_TT_UnRegisterScheduleSyncCallback(), @ref HAL_FDCAN_TT_UnRegisterTimeMarkCallback(),
+  @ref HAL_FDCAN_TT_UnRegisterStopWatchCallback() and @ref HAL_FDCAN_TT_UnRegisterGlobalTimeCallback().
+
+  By default, after the @ref HAL_FDCAN_Init() and when the state is HAL_FDCAN_STATE_RESET,
+  all callbacks are set to the corresponding weak functions:
+  examples @ref HAL_FDCAN_ErrorCallback().
+  Exception done for MspInit and MspDeInit functions that are
+  reset to the legacy weak function in the @ref HAL_FDCAN_Init()/ @ref HAL_FDCAN_DeInit() only when
+  these callbacks are null (not registered beforehand).
+  if not, MspInit or MspDeInit are not null, the @ref HAL_FDCAN_Init()/ @ref HAL_FDCAN_DeInit()
+  keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+  Callbacks can be registered/unregistered in HAL_FDCAN_STATE_READY state only.
+  Exception done MspInit/MspDeInit that can be registered/unregistered
+  in HAL_FDCAN_STATE_READY or HAL_FDCAN_STATE_RESET state,
+  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+  In that case first register the MspInit/MspDeInit user callbacks
+  using @ref HAL_FDCAN_RegisterCallback() before calling @ref HAL_FDCAN_DeInit()
+  or @ref HAL_FDCAN_Init() function.
+
+  When The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS is set to 0 or
+  not defined, the callback registration feature is not available and all callbacks
+  are set to the corresponding weak functions.
+
+  @endverbatim
+
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup FDCAN FDCAN
+  * @brief FDCAN HAL module driver
+  * @{
+  */
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup FDCAN_Private_Constants
+  * @{
+  */
+#define FDCAN_TIMEOUT_VALUE 10U
+
+#define FDCAN_TX_EVENT_FIFO_MASK (FDCAN_IR_TEFL | FDCAN_IR_TEFF | FDCAN_IR_TEFW | FDCAN_IR_TEFN)
+#define FDCAN_RX_FIFO0_MASK (FDCAN_IR_RF0L | FDCAN_IR_RF0F | FDCAN_IR_RF0W | FDCAN_IR_RF0N)
+#define FDCAN_RX_FIFO1_MASK (FDCAN_IR_RF1L | FDCAN_IR_RF1F | FDCAN_IR_RF1W | FDCAN_IR_RF1N)
+#define FDCAN_ERROR_MASK (FDCAN_IR_ELO | FDCAN_IR_WDI | FDCAN_IR_PEA | FDCAN_IR_PED | FDCAN_IR_ARA)
+#define FDCAN_ERROR_STATUS_MASK (FDCAN_IR_EP | FDCAN_IR_EW | FDCAN_IR_BO)
+#define FDCAN_TT_SCHEDULE_SYNC_MASK (FDCAN_TTIR_SBC | FDCAN_TTIR_SMC | FDCAN_TTIR_CSM | FDCAN_TTIR_SOG)
+#define FDCAN_TT_TIME_MARK_MASK (FDCAN_TTIR_RTMI | FDCAN_TTIR_TTMI)
+#define FDCAN_TT_GLOBAL_TIME_MASK (FDCAN_TTIR_GTW | FDCAN_TTIR_GTD)
+#define FDCAN_TT_DISTURBING_ERROR_MASK (FDCAN_TTIR_GTE | FDCAN_TTIR_TXU | FDCAN_TTIR_TXO | \
+                                        FDCAN_TTIR_SE1 | FDCAN_TTIR_SE2 | FDCAN_TTIR_ELC)
+#define FDCAN_TT_FATAL_ERROR_MASK (FDCAN_TTIR_IWT | FDCAN_TTIR_WT | FDCAN_TTIR_AW | FDCAN_TTIR_CER)
+
+#define FDCAN_ELEMENT_MASK_STDID ((uint32_t)0x1FFC0000U) /* Standard Identifier         */
+#define FDCAN_ELEMENT_MASK_EXTID ((uint32_t)0x1FFFFFFFU) /* Extended Identifier         */
+#define FDCAN_ELEMENT_MASK_RTR   ((uint32_t)0x20000000U) /* Remote Transmission Request */
+#define FDCAN_ELEMENT_MASK_XTD   ((uint32_t)0x40000000U) /* Extended Identifier         */
+#define FDCAN_ELEMENT_MASK_ESI   ((uint32_t)0x80000000U) /* Error State Indicator       */
+#define FDCAN_ELEMENT_MASK_TS    ((uint32_t)0x0000FFFFU) /* Timestamp                   */
+#define FDCAN_ELEMENT_MASK_DLC   ((uint32_t)0x000F0000U) /* Data Length Code            */
+#define FDCAN_ELEMENT_MASK_BRS   ((uint32_t)0x00100000U) /* Bit Rate Switch             */
+#define FDCAN_ELEMENT_MASK_FDF   ((uint32_t)0x00200000U) /* FD Format                   */
+#define FDCAN_ELEMENT_MASK_EFC   ((uint32_t)0x00800000U) /* Event FIFO Control          */
+#define FDCAN_ELEMENT_MASK_MM    ((uint32_t)0xFF000000U) /* Message Marker              */
+#define FDCAN_ELEMENT_MASK_FIDX  ((uint32_t)0x7F000000U) /* Filter Index                */
+#define FDCAN_ELEMENT_MASK_ANMF  ((uint32_t)0x80000000U) /* Accepted Non-matching Frame */
+#define FDCAN_ELEMENT_MASK_ET    ((uint32_t)0x00C00000U) /* Event type                  */
+
+#define FDCAN_MESSAGE_RAM_SIZE 0x2800U
+#define FDCAN_MESSAGE_RAM_END_ADDRESS (SRAMCAN_BASE + FDCAN_MESSAGE_RAM_SIZE - 0x4U) /* The Message RAM has a width of 4 Bytes */
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+static const uint8_t DLCtoBytes[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64};
+
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup FDCAN_Private_Functions_Prototypes
+  * @{
+  */
+static HAL_StatusTypeDef FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan);
+static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup FDCAN_Exported_Functions FDCAN Exported Functions
+  * @{
+  */
+
+/** @defgroup FDCAN_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+  ==============================================================================
+              ##### Initialization and de-initialization functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize and configure the FDCAN.
+      (+) De-initialize the FDCAN.
+      (+) Enter FDCAN peripheral in power down mode.
+      (+) Exit power down mode.
+      (+) Register callbacks.
+      (+) Unregister callbacks.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the FDCAN peripheral according to the specified
+  *         parameters in the FDCAN_InitTypeDef structure.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t tickstart;
+  HAL_StatusTypeDef status;
+  const uint32_t CvtEltSize[] = {0, 0, 0, 0, 0, 1, 2, 3, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0, 7};
+
+  /* Check FDCAN handle */
+  if (hfdcan == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check FDCAN instance */
+  if (hfdcan->Instance == FDCAN1)
+  {
+    hfdcan->ttcan = (TTCAN_TypeDef *)((uint32_t)hfdcan->Instance + 0x100U);
+  }
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_FRAME_FORMAT(hfdcan->Init.FrameFormat));
+  assert_param(IS_FDCAN_MODE(hfdcan->Init.Mode));
+  assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.AutoRetransmission));
+  assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.TransmitPause));
+  assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.ProtocolException));
+  assert_param(IS_FDCAN_NOMINAL_PRESCALER(hfdcan->Init.NominalPrescaler));
+  assert_param(IS_FDCAN_NOMINAL_SJW(hfdcan->Init.NominalSyncJumpWidth));
+  assert_param(IS_FDCAN_NOMINAL_TSEG1(hfdcan->Init.NominalTimeSeg1));
+  assert_param(IS_FDCAN_NOMINAL_TSEG2(hfdcan->Init.NominalTimeSeg2));
+  if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS)
+  {
+    assert_param(IS_FDCAN_DATA_PRESCALER(hfdcan->Init.DataPrescaler));
+    assert_param(IS_FDCAN_DATA_SJW(hfdcan->Init.DataSyncJumpWidth));
+    assert_param(IS_FDCAN_DATA_TSEG1(hfdcan->Init.DataTimeSeg1));
+    assert_param(IS_FDCAN_DATA_TSEG2(hfdcan->Init.DataTimeSeg2));
+  }
+  assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.StdFiltersNbr, 128U));
+  assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.ExtFiltersNbr, 64U));
+  assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.RxFifo0ElmtsNbr, 64U));
+  if (hfdcan->Init.RxFifo0ElmtsNbr > 0U)
+  {
+    assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.RxFifo0ElmtSize));
+  }
+  assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.RxFifo1ElmtsNbr, 64U));
+  if (hfdcan->Init.RxFifo1ElmtsNbr > 0U)
+  {
+    assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.RxFifo1ElmtSize));
+  }
+  assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.RxBuffersNbr, 64U));
+  if (hfdcan->Init.RxBuffersNbr > 0U)
+  {
+    assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.RxBufferSize));
+  }
+  assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.TxEventsNbr, 32U));
+  assert_param(IS_FDCAN_MAX_VALUE((hfdcan->Init.TxBuffersNbr + hfdcan->Init.TxFifoQueueElmtsNbr), 32U));
+  if (hfdcan->Init.TxFifoQueueElmtsNbr > 0U)
+  {
+    assert_param(IS_FDCAN_TX_FIFO_QUEUE_MODE(hfdcan->Init.TxFifoQueueMode));
+  }
+  if ((hfdcan->Init.TxBuffersNbr + hfdcan->Init.TxFifoQueueElmtsNbr) > 0U)
+  {
+    assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.TxElmtSize));
+  }
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+  if (hfdcan->State == HAL_FDCAN_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hfdcan->Lock = HAL_UNLOCKED;
+
+    /* Reset callbacks to legacy functions */
+    hfdcan->ClockCalibrationCallback    = HAL_FDCAN_ClockCalibrationCallback;    /* Legacy weak ClockCalibrationCallback    */
+    hfdcan->TxEventFifoCallback         = HAL_FDCAN_TxEventFifoCallback;         /* Legacy weak TxEventFifoCallback         */
+    hfdcan->RxFifo0Callback             = HAL_FDCAN_RxFifo0Callback;             /* Legacy weak RxFifo0Callback             */
+    hfdcan->RxFifo1Callback             = HAL_FDCAN_RxFifo1Callback;             /* Legacy weak RxFifo1Callback             */
+    hfdcan->TxFifoEmptyCallback         = HAL_FDCAN_TxFifoEmptyCallback;         /* Legacy weak TxFifoEmptyCallback         */
+    hfdcan->TxBufferCompleteCallback    = HAL_FDCAN_TxBufferCompleteCallback;    /* Legacy weak TxBufferCompleteCallback    */
+    hfdcan->TxBufferAbortCallback       = HAL_FDCAN_TxBufferAbortCallback;       /* Legacy weak TxBufferAbortCallback       */
+    hfdcan->RxBufferNewMessageCallback  = HAL_FDCAN_RxBufferNewMessageCallback;  /* Legacy weak RxBufferNewMessageCallback  */
+    hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback; /* Legacy weak HighPriorityMessageCallback */
+    hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback; /* Legacy weak TimestampWraparoundCallback */
+    hfdcan->TimeoutOccurredCallback     = HAL_FDCAN_TimeoutOccurredCallback;     /* Legacy weak TimeoutOccurredCallback     */
+    hfdcan->ErrorCallback               = HAL_FDCAN_ErrorCallback;               /* Legacy weak ErrorCallback               */
+    hfdcan->ErrorStatusCallback         = HAL_FDCAN_ErrorStatusCallback;         /* Legacy weak ErrorStatusCallback         */
+    hfdcan->TT_ScheduleSyncCallback     = HAL_FDCAN_TT_ScheduleSyncCallback;     /* Legacy weak TT_ScheduleSyncCallback     */
+    hfdcan->TT_TimeMarkCallback         = HAL_FDCAN_TT_TimeMarkCallback;         /* Legacy weak TT_TimeMarkCallback         */
+    hfdcan->TT_StopWatchCallback        = HAL_FDCAN_TT_StopWatchCallback;        /* Legacy weak TT_StopWatchCallback        */
+    hfdcan->TT_GlobalTimeCallback       = HAL_FDCAN_TT_GlobalTimeCallback;       /* Legacy weak TT_GlobalTimeCallback       */
+
+    if (hfdcan->MspInitCallback == NULL)
+    {
+      hfdcan->MspInitCallback = HAL_FDCAN_MspInit;  /* Legacy weak MspInit */
+    }
+
+    /* Init the low level hardware: CLOCK, NVIC */
+    hfdcan->MspInitCallback(hfdcan);
+  }
+#else
+  if (hfdcan->State == HAL_FDCAN_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hfdcan->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware: CLOCK, NVIC */
+    HAL_FDCAN_MspInit(hfdcan);
+  }
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+  /* Exit from Sleep mode */
+  CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Check Sleep mode acknowledge */
+  while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
+  {
+    if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+      /* Change FDCAN state */
+      hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+      return HAL_ERROR;
+    }
+  }
+
+  /* Request initialisation */
+  SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait until the INIT bit into CCCR register is set */
+  while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U)
+  {
+    /* Check for the Timeout */
+    if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+      /* Change FDCAN state */
+      hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+      return HAL_ERROR;
+    }
+  }
+
+  /* Enable configuration change */
+  SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE);
+
+  /* Set the no automatic retransmission */
+  if (hfdcan->Init.AutoRetransmission == ENABLE)
+  {
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR);
+  }
+  else
+  {
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR);
+  }
+
+  /* Set the transmit pause feature */
+  if (hfdcan->Init.TransmitPause == ENABLE)
+  {
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP);
+  }
+  else
+  {
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP);
+  }
+
+  /* Set the Protocol Exception Handling */
+  if (hfdcan->Init.ProtocolException == ENABLE)
+  {
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD);
+  }
+  else
+  {
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD);
+  }
+
+  /* Set FDCAN Frame Format */
+  MODIFY_REG(hfdcan->Instance->CCCR, FDCAN_FRAME_FD_BRS, hfdcan->Init.FrameFormat);
+
+  /* Reset FDCAN Operation Mode */
+  CLEAR_BIT(hfdcan->Instance->CCCR, (FDCAN_CCCR_TEST | FDCAN_CCCR_MON | FDCAN_CCCR_ASM));
+  CLEAR_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK);
+
+  /* Set FDCAN Operating Mode:
+               | Normal | Restricted |    Bus     | Internal | External
+               |        | Operation  | Monitoring | LoopBack | LoopBack
+     CCCR.TEST |   0    |     0      |     0      |    1     |    1
+     CCCR.MON  |   0    |     0      |     1      |    1     |    0
+     TEST.LBCK |   0    |     0      |     0      |    1     |    1
+     CCCR.ASM  |   0    |     1      |     0      |    0     |    0
+  */
+  if (hfdcan->Init.Mode == FDCAN_MODE_RESTRICTED_OPERATION)
+  {
+    /* Enable Restricted Operation mode */
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM);
+  }
+  else if (hfdcan->Init.Mode != FDCAN_MODE_NORMAL)
+  {
+    if (hfdcan->Init.Mode != FDCAN_MODE_BUS_MONITORING)
+    {
+      /* Enable write access to TEST register */
+      SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TEST);
+
+      /* Enable LoopBack mode */
+      SET_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK);
+
+      if (hfdcan->Init.Mode == FDCAN_MODE_INTERNAL_LOOPBACK)
+      {
+        SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON);
+      }
+    }
+    else
+    {
+      /* Enable bus monitoring mode */
+      SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON);
+    }
+  }
+  else
+  {
+    /* Nothing to do: normal mode */
+  }
+
+  /* Set the nominal bit timing register */
+  hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U) << FDCAN_NBTP_NSJW_Pos) | \
+                            (((uint32_t)hfdcan->Init.NominalTimeSeg1 - 1U) << FDCAN_NBTP_NTSEG1_Pos)    | \
+                            (((uint32_t)hfdcan->Init.NominalTimeSeg2 - 1U) << FDCAN_NBTP_NTSEG2_Pos)    | \
+                            (((uint32_t)hfdcan->Init.NominalPrescaler - 1U) << FDCAN_NBTP_NBRP_Pos));
+
+  /* If FD operation with BRS is selected, set the data bit timing register */
+  if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS)
+  {
+    hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos) | \
+                              (((uint32_t)hfdcan->Init.DataTimeSeg1 - 1U) << FDCAN_DBTP_DTSEG1_Pos)    | \
+                              (((uint32_t)hfdcan->Init.DataTimeSeg2 - 1U) << FDCAN_DBTP_DTSEG2_Pos)    | \
+                              (((uint32_t)hfdcan->Init.DataPrescaler - 1U) << FDCAN_DBTP_DBRP_Pos));
+  }
+
+  if (hfdcan->Init.TxFifoQueueElmtsNbr > 0U)
+  {
+    /* Select between Tx FIFO and Tx Queue operation modes */
+    SET_BIT(hfdcan->Instance->TXBC, hfdcan->Init.TxFifoQueueMode);
+  }
+
+  /* Configure Tx element size */
+  if ((hfdcan->Init.TxBuffersNbr + hfdcan->Init.TxFifoQueueElmtsNbr) > 0U)
+  {
+    MODIFY_REG(hfdcan->Instance->TXESC, FDCAN_TXESC_TBDS, CvtEltSize[hfdcan->Init.TxElmtSize]);
+  }
+
+  /* Configure Rx FIFO 0 element size */
+  if (hfdcan->Init.RxFifo0ElmtsNbr > 0U)
+  {
+    MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_F0DS, (CvtEltSize[hfdcan->Init.RxFifo0ElmtSize] << FDCAN_RXESC_F0DS_Pos));
+  }
+
+  /* Configure Rx FIFO 1 element size */
+  if (hfdcan->Init.RxFifo1ElmtsNbr > 0U)
+  {
+    MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_F1DS, (CvtEltSize[hfdcan->Init.RxFifo1ElmtSize] << FDCAN_RXESC_F1DS_Pos));
+  }
+
+  /* Configure Rx buffer element size */
+  if (hfdcan->Init.RxBuffersNbr > 0U)
+  {
+    MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_RBDS, (CvtEltSize[hfdcan->Init.RxBufferSize] << FDCAN_RXESC_RBDS_Pos));
+  }
+
+  /* By default operation mode is set to Event-driven communication.
+     If Time-triggered communication is needed, user should call the
+     HAL_FDCAN_TT_ConfigOperation function just after the HAL_FDCAN_Init */
+  if (hfdcan->Instance == FDCAN1)
+  {
+    CLEAR_BIT(hfdcan->ttcan->TTOCF, FDCAN_TTOCF_OM);
+  }
+
+  /* Initialize the Latest Tx FIFO/Queue request buffer index */
+  hfdcan->LatestTxFifoQRequest = 0U;
+
+  /* Initialize the error code */
+  hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
+
+  /* Initialize the FDCAN state */
+  hfdcan->State = HAL_FDCAN_STATE_READY;
+
+  /* Calculate each RAM block address */
+  status = FDCAN_CalcultateRamBlockAddresses(hfdcan);
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Deinitializes the FDCAN peripheral registers to their default reset values.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Check FDCAN handle */
+  if (hfdcan == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance));
+
+  /* Stop the FDCAN module: return value is voluntary ignored */
+  (void)HAL_FDCAN_Stop(hfdcan);
+
+  /* Disable Interrupt lines */
+  CLEAR_BIT(hfdcan->Instance->ILE, (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1));
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+  if (hfdcan->MspDeInitCallback == NULL)
+  {
+    hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit; /* Legacy weak MspDeInit */
+  }
+
+  /* DeInit the low level hardware: CLOCK, NVIC */
+  hfdcan->MspDeInitCallback(hfdcan);
+#else
+  /* DeInit the low level hardware: CLOCK, NVIC */
+  HAL_FDCAN_MspDeInit(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+  /* Reset the FDCAN ErrorCode */
+  hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
+
+  /* Change FDCAN state */
+  hfdcan->State = HAL_FDCAN_STATE_RESET;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the FDCAN MSP.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes the FDCAN MSP.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Enter FDCAN peripheral in sleep mode.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t tickstart;
+
+  /* Request clock stop */
+  SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait until FDCAN is ready for power down */
+  while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+      /* Change FDCAN state */
+      hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+      return HAL_ERROR;
+    }
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Exit power down mode.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t tickstart;
+
+  /* Reset clock stop request */
+  CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait until FDCAN exits sleep mode */
+  while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
+  {
+    if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+      /* Change FDCAN state */
+      hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+      return HAL_ERROR;
+    }
+  }
+
+  /* Enter normal operation */
+  CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+/**
+  * @brief  Register a FDCAN CallBack.
+  *         To be used instead of the weak predefined callback
+  * @param  hfdcan pointer to a FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for FDCAN module
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_FDCAN_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty callback ID
+  *           @arg @ref HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID Rx buffer new message callback ID
+  *           @arg @ref HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID High priority message callback ID
+  *           @arg @ref HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID Timestamp wraparound callback ID
+  *           @arg @ref HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID Timeout occurred callback ID
+  *           @arg @ref HAL_FDCAN_ERROR_CALLBACK_CB_ID Error callback ID
+  *           @arg @ref HAL_FDCAN_MSPINIT_CB_ID MspInit callback ID
+  *           @arg @ref HAL_FDCAN_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, void (* pCallback)(FDCAN_HandleTypeDef *_hFDCAN))
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_FDCAN_TX_FIFO_EMPTY_CB_ID :
+        hfdcan->TxFifoEmptyCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID :
+        hfdcan->RxBufferNewMessageCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID :
+        hfdcan->HighPriorityMessageCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID :
+        hfdcan->TimestampWraparoundCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID :
+        hfdcan->TimeoutOccurredCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_ERROR_CALLBACK_CB_ID :
+        hfdcan->ErrorCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_MSPINIT_CB_ID :
+        hfdcan->MspInitCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_MSPDEINIT_CB_ID :
+        hfdcan->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hfdcan->State == HAL_FDCAN_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_FDCAN_MSPINIT_CB_ID :
+        hfdcan->MspInitCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_MSPDEINIT_CB_ID :
+        hfdcan->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a FDCAN CallBack.
+  *         FDCAN callback is redirected to the weak predefined callback
+  * @param  hfdcan pointer to a FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for FDCAN module
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_FDCAN_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty callback ID
+  *           @arg @ref HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID Rx buffer new message callback ID
+  *           @arg @ref HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID High priority message callback ID
+  *           @arg @ref HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID Timestamp wraparound callback ID
+  *           @arg @ref HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID Timeout occurred callback ID
+  *           @arg @ref HAL_FDCAN_ERROR_CALLBACK_CB_ID Error callback ID
+  *           @arg @ref HAL_FDCAN_MSPINIT_CB_ID MspInit callback ID
+  *           @arg @ref HAL_FDCAN_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_FDCAN_TX_FIFO_EMPTY_CB_ID :
+        hfdcan->TxFifoEmptyCallback = HAL_FDCAN_TxFifoEmptyCallback;
+        break;
+
+      case HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID :
+        hfdcan->RxBufferNewMessageCallback = HAL_FDCAN_RxBufferNewMessageCallback;
+        break;
+
+      case HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID :
+        hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback;
+        break;
+
+      case HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID :
+        hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback;
+        break;
+
+      case HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID :
+        hfdcan->TimeoutOccurredCallback = HAL_FDCAN_TimeoutOccurredCallback;
+        break;
+
+      case HAL_FDCAN_ERROR_CALLBACK_CB_ID :
+        hfdcan->ErrorCallback = HAL_FDCAN_ErrorCallback;
+        break;
+
+      case HAL_FDCAN_MSPINIT_CB_ID :
+        hfdcan->MspInitCallback = HAL_FDCAN_MspInit;
+        break;
+
+      case HAL_FDCAN_MSPDEINIT_CB_ID :
+        hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hfdcan->State == HAL_FDCAN_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_FDCAN_MSPINIT_CB_ID :
+        hfdcan->MspInitCallback = HAL_FDCAN_MspInit;
+        break;
+
+      case HAL_FDCAN_MSPDEINIT_CB_ID :
+        hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register Clock Calibration FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_ClockCalibrationCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the Clock Calibration Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ClockCalibrationCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->ClockCalibrationCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Clock Calibration FDCAN Callback
+  *         Clock Calibration FDCAN Callback is redirected to the weak HAL_FDCAN_ClockCalibrationCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->ClockCalibrationCallback = HAL_FDCAN_ClockCalibrationCallback; /* Legacy weak ClockCalibrationCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register Tx Event Fifo FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_TxEventFifoCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the Tx Event Fifo Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxEventFifoCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TxEventFifoCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Tx Event Fifo FDCAN Callback
+  *         Tx Event Fifo FDCAN Callback is redirected to the weak HAL_FDCAN_TxEventFifoCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TxEventFifoCallback = HAL_FDCAN_TxEventFifoCallback; /* Legacy weak TxEventFifoCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register Rx Fifo 0 FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_RxFifo0Callback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the Rx Fifo 0 Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo0CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->RxFifo0Callback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Rx Fifo 0 FDCAN Callback
+  *         Rx Fifo 0 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo0Callback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->RxFifo0Callback = HAL_FDCAN_RxFifo0Callback; /* Legacy weak RxFifo0Callback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register Rx Fifo 1 FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_RxFifo1Callback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the Rx Fifo 1 Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo1CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->RxFifo1Callback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Rx Fifo 1 FDCAN Callback
+  *         Rx Fifo 1 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo1Callback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->RxFifo1Callback = HAL_FDCAN_RxFifo1Callback; /* Legacy weak RxFifo1Callback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register Tx Buffer Complete FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the Tx Buffer Complete Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferCompleteCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TxBufferCompleteCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Tx Buffer Complete FDCAN Callback
+  *         Tx Buffer Complete FDCAN Callback is redirected to the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TxBufferCompleteCallback = HAL_FDCAN_TxBufferCompleteCallback; /* Legacy weak TxBufferCompleteCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register Tx Buffer Abort FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the Tx Buffer Abort Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferAbortCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TxBufferAbortCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Tx Buffer Abort FDCAN Callback
+  *         Tx Buffer Abort FDCAN Callback is redirected to the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TxBufferAbortCallback = HAL_FDCAN_TxBufferAbortCallback; /* Legacy weak TxBufferAbortCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register Error Status FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_ErrorStatusCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the Error Status Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ErrorStatusCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->ErrorStatusCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Error Status FDCAN Callback
+  *         Error Status FDCAN Callback is redirected to the weak HAL_FDCAN_ErrorStatusCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->ErrorStatusCallback = HAL_FDCAN_ErrorStatusCallback; /* Legacy weak ErrorStatusCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register TT Schedule Synchronization FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_TT_ScheduleSyncCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the TT Schedule Synchronization Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_ScheduleSyncCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_ScheduleSyncCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the TT Schedule Synchronization FDCAN Callback
+  *         TT Schedule Synchronization Callback is redirected to the weak HAL_FDCAN_TT_ScheduleSyncCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_ScheduleSyncCallback = HAL_FDCAN_TT_ScheduleSyncCallback; /* Legacy weak TT_ScheduleSyncCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register TT Time Mark FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_TT_TimeMarkCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the TT Time Mark Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_TimeMarkCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_TimeMarkCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the TT Time Mark FDCAN Callback
+  *         TT Time Mark Callback is redirected to the weak HAL_FDCAN_TT_TimeMarkCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_TimeMarkCallback = HAL_FDCAN_TT_TimeMarkCallback; /* Legacy weak TT_TimeMarkCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register TT Stop Watch FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_TT_StopWatchCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the TT Stop Watch Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_StopWatchCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_StopWatchCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the TT Stop Watch FDCAN Callback
+  *         TT Stop Watch Callback is redirected to the weak HAL_FDCAN_TT_StopWatchCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_StopWatchCallback = HAL_FDCAN_TT_StopWatchCallback; /* Legacy weak TT_StopWatchCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register TT Global Time FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_TT_GlobalTimeCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the TT Global Time Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_GlobalTimeCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_GlobalTimeCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the TT Global Time FDCAN Callback
+  *         TT Global Time Callback is redirected to the weak HAL_FDCAN_TT_GlobalTimeCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_GlobalTimeCallback = HAL_FDCAN_TT_GlobalTimeCallback; /* Legacy weak TT_GlobalTimeCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Exported_Functions_Group2 Configuration functions
+ *  @brief    FDCAN Configuration functions.
+ *
+@verbatim
+  ==============================================================================
+              ##### Configuration functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) HAL_FDCAN_ConfigClockCalibration        : Configure the FDCAN clock calibration unit
+        (+) HAL_FDCAN_GetClockCalibrationState      : Get the clock calibration state
+        (+) HAL_FDCAN_ResetClockCalibrationState    : Reset the clock calibration state
+        (+) HAL_FDCAN_GetClockCalibrationCounter    : Get the clock calibration counters values
+      (+) HAL_FDCAN_ConfigFilter                  : Configure the FDCAN reception filters
+      (+) HAL_FDCAN_ConfigGlobalFilter            : Configure the FDCAN global filter
+      (+) HAL_FDCAN_ConfigExtendedIdMask          : Configure the extended ID mask
+      (+) HAL_FDCAN_ConfigRxFifoOverwrite         : Configure the Rx FIFO operation mode
+      (+) HAL_FDCAN_ConfigFifoWatermark           : Configure the FIFO watermark
+      (+) HAL_FDCAN_ConfigRamWatchdog             : Configure the RAM watchdog
+      (+) HAL_FDCAN_ConfigTimestampCounter        : Configure the timestamp counter
+        (+) HAL_FDCAN_EnableTimestampCounter        : Enable the timestamp counter
+        (+) HAL_FDCAN_DisableTimestampCounter       : Disable the timestamp counter
+        (+) HAL_FDCAN_GetTimestampCounter           : Get the timestamp counter value
+        (+) HAL_FDCAN_ResetTimestampCounter         : Reset the timestamp counter to zero
+      (+) HAL_FDCAN_ConfigTimeoutCounter          : Configure the timeout counter
+        (+) HAL_FDCAN_EnableTimeoutCounter          : Enable the timeout counter
+        (+) HAL_FDCAN_DisableTimeoutCounter         : Disable the timeout counter
+        (+) HAL_FDCAN_GetTimeoutCounter             : Get the timeout counter value
+        (+) HAL_FDCAN_ResetTimeoutCounter           : Reset the timeout counter to its start value
+      (+) HAL_FDCAN_ConfigTxDelayCompensation     : Configure the transmitter delay compensation
+        (+) HAL_FDCAN_EnableTxDelayCompensation     : Enable the transmitter delay compensation
+        (+) HAL_FDCAN_DisableTxDelayCompensation    : Disable the transmitter delay compensation
+      (+) HAL_FDCAN_EnableISOMode                 : Enable ISO 11898-1 protocol mode
+      (+) HAL_FDCAN_DisableISOMode                : Disable ISO 11898-1 protocol mode
+      (+) HAL_FDCAN_EnableEdgeFiltering           : Enable edge filtering during bus integration
+      (+) HAL_FDCAN_DisableEdgeFiltering          : Disable edge filtering during bus integration
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the FDCAN clock calibration unit according to the specified
+  *         parameters in the FDCAN_ClkCalUnitTypeDef structure.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  sCcuConfig pointer to an FDCAN_ClkCalUnitTypeDef structure that
+  *         contains the clock calibration information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigClockCalibration(FDCAN_HandleTypeDef *hfdcan, FDCAN_ClkCalUnitTypeDef *sCcuConfig)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_CLOCK_CALIBRATION(sCcuConfig->ClockCalibration));
+  if (sCcuConfig->ClockCalibration == FDCAN_CLOCK_CALIBRATION_DISABLE)
+  {
+    assert_param(IS_FDCAN_CKDIV(sCcuConfig->ClockDivider));
+  }
+  else
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(sCcuConfig->MinOscClkPeriods, 0xFFU));
+    assert_param(IS_FDCAN_CALIBRATION_FIELD_LENGTH(sCcuConfig->CalFieldLength));
+    assert_param(IS_FDCAN_MIN_VALUE(sCcuConfig->TimeQuantaPerBitTime, 4U));
+    assert_param(IS_FDCAN_MAX_VALUE(sCcuConfig->TimeQuantaPerBitTime, 0x25U));
+    assert_param(IS_FDCAN_MAX_VALUE(sCcuConfig->WatchdogStartValue, 0xFFFFU));
+  }
+
+  /* FDCAN1 should be initialized in order to use clock calibration */
+  if (hfdcan->Instance != FDCAN1)
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    if (sCcuConfig->ClockCalibration == FDCAN_CLOCK_CALIBRATION_DISABLE)
+    {
+      /* Bypass clock calibration */
+      SET_BIT(FDCAN_CCU->CCFG, FDCANCCU_CCFG_BCC);
+
+      /* Configure clock divider */
+      MODIFY_REG(FDCAN_CCU->CCFG, FDCANCCU_CCFG_CDIV, sCcuConfig->ClockDivider);
+    }
+    else /* sCcuConfig->ClockCalibration == ENABLE */
+    {
+      /* Clock calibration unit generates time quanta clock */
+      CLEAR_BIT(FDCAN_CCU->CCFG, FDCANCCU_CCFG_BCC);
+
+      /* Configure clock calibration unit */
+      MODIFY_REG(FDCAN_CCU->CCFG,
+                 (FDCANCCU_CCFG_TQBT | FDCANCCU_CCFG_CFL | FDCANCCU_CCFG_OCPM),
+                 ((sCcuConfig->TimeQuantaPerBitTime << FDCANCCU_CCFG_TQBT_Pos) | sCcuConfig->CalFieldLength | (sCcuConfig->MinOscClkPeriods << FDCANCCU_CCFG_OCPM_Pos)));
+
+      /* Configure the start value of the calibration watchdog counter */
+      MODIFY_REG(FDCAN_CCU->CWD, FDCANCCU_CWD_WDC, sCcuConfig->WatchdogStartValue);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get the clock calibration state.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval State clock calibration state (can be a value of @arg FDCAN_calibration_state)
+  */
+uint32_t HAL_FDCAN_GetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  return (FDCAN_CCU->CSTAT & FDCANCCU_CSTAT_CALS);
+}
+
+/**
+  * @brief  Reset the clock calibration state.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ResetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* FDCAN1 should be initialized in order to use clock calibration */
+  if (hfdcan->Instance != FDCAN1)
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Calibration software reset */
+    SET_BIT(FDCAN_CCU->CCFG, FDCANCCU_CCFG_SWR);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get the clock calibration counter value.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  Counter clock calibration counter.
+  *         This parameter can be a value of @arg FDCAN_calibration_counter.
+  * @retval Value clock calibration counter value
+  */
+uint32_t HAL_FDCAN_GetClockCalibrationCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t Counter)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_CALIBRATION_COUNTER(Counter));
+
+  if (Counter == FDCAN_CALIB_TIME_QUANTA_COUNTER)
+  {
+    return ((FDCAN_CCU->CSTAT & FDCANCCU_CSTAT_TQC) >> FDCANCCU_CSTAT_TQC_Pos);
+  }
+  else if (Counter == FDCAN_CALIB_CLOCK_PERIOD_COUNTER)
+  {
+    return (FDCAN_CCU->CSTAT & FDCANCCU_CSTAT_OCPC);
+  }
+  else /* Counter == FDCAN_CALIB_WATCHDOG_COUNTER */
+  {
+    return ((FDCAN_CCU->CWD & FDCANCCU_CWD_WDV) >> FDCANCCU_CWD_WDV_Pos);
+  }
+}
+
+/**
+  * @brief  Configure the FDCAN reception filter according to the specified
+  *         parameters in the FDCAN_FilterTypeDef structure.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  sFilterConfig pointer to an FDCAN_FilterTypeDef structure that
+  *         contains the filter configuration information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig)
+{
+  uint32_t FilterElementW1;
+  uint32_t FilterElementW2;
+  uint32_t *FilterAddress;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Check function parameters */
+    assert_param(IS_FDCAN_ID_TYPE(sFilterConfig->IdType));
+    assert_param(IS_FDCAN_FILTER_CFG(sFilterConfig->FilterConfig));
+    if (sFilterConfig->FilterConfig == FDCAN_FILTER_TO_RXBUFFER)
+    {
+      assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->RxBufferIndex, 63U));
+      assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->IsCalibrationMsg, 1U));
+    }
+
+    if (sFilterConfig->IdType == FDCAN_STANDARD_ID)
+    {
+      /* Check function parameters */
+      assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.StdFiltersNbr - 1U)));
+      assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x7FFU));
+      if (sFilterConfig->FilterConfig != FDCAN_FILTER_TO_RXBUFFER)
+      {
+        assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x7FFU));
+        assert_param(IS_FDCAN_STD_FILTER_TYPE(sFilterConfig->FilterType));
+      }
+
+      /* Build filter element */
+      if (sFilterConfig->FilterConfig == FDCAN_FILTER_TO_RXBUFFER)
+      {
+        FilterElementW1 = ((FDCAN_FILTER_TO_RXBUFFER << 27U)       |
+                           (sFilterConfig->FilterID1 << 16U)       |
+                           (sFilterConfig->IsCalibrationMsg << 8U) |
+                           sFilterConfig->RxBufferIndex);
+      }
+      else
+      {
+        FilterElementW1 = ((sFilterConfig->FilterType << 30U)   |
+                           (sFilterConfig->FilterConfig << 27U) |
+                           (sFilterConfig->FilterID1 << 16U)    |
+                           sFilterConfig->FilterID2);
+      }
+
+      /* Calculate filter address */
+      FilterAddress = (uint32_t *)(hfdcan->msgRam.StandardFilterSA + (sFilterConfig->FilterIndex * 4U));
+
+      /* Write filter element to the message RAM */
+      *FilterAddress = FilterElementW1;
+    }
+    else /* sFilterConfig->IdType == FDCAN_EXTENDED_ID */
+    {
+      /* Check function parameters */
+      assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.ExtFiltersNbr - 1U)));
+      assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x1FFFFFFFU));
+      if (sFilterConfig->FilterConfig != FDCAN_FILTER_TO_RXBUFFER)
+      {
+        assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x1FFFFFFFU));
+        assert_param(IS_FDCAN_EXT_FILTER_TYPE(sFilterConfig->FilterType));
+      }
+
+      /* Build first word of filter element */
+      FilterElementW1 = ((sFilterConfig->FilterConfig << 29U) | sFilterConfig->FilterID1);
+
+      /* Build second word of filter element */
+      if (sFilterConfig->FilterConfig == FDCAN_FILTER_TO_RXBUFFER)
+      {
+        FilterElementW2 = sFilterConfig->RxBufferIndex;
+      }
+      else
+      {
+        FilterElementW2 = ((sFilterConfig->FilterType << 30U) | sFilterConfig->FilterID2);
+      }
+
+      /* Calculate filter address */
+      FilterAddress = (uint32_t *)(hfdcan->msgRam.ExtendedFilterSA + (sFilterConfig->FilterIndex * 4U * 2U));
+
+      /* Write filter element to the message RAM */
+      *FilterAddress = FilterElementW1;
+      FilterAddress++;
+      *FilterAddress = FilterElementW2;
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the FDCAN global filter.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  NonMatchingStd Defines how received messages with 11-bit IDs that
+  *         do not match any element of the filter list are treated.
+  *         This parameter can be a value of @arg FDCAN_Non_Matching_Frames.
+  * @param  NonMatchingExt Defines how received messages with 29-bit IDs that
+  *         do not match any element of the filter list are treated.
+  *         This parameter can be a value of @arg FDCAN_Non_Matching_Frames.
+  * @param  RejectRemoteStd Filter or reject all the remote 11-bit IDs frames.
+  *         This parameter can be a value of @arg FDCAN_Reject_Remote_Frames.
+  * @param  RejectRemoteExt Filter or reject all the remote 29-bit IDs frames.
+  *         This parameter can be a value of @arg FDCAN_Reject_Remote_Frames.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan,
+                                               uint32_t NonMatchingStd,
+                                               uint32_t NonMatchingExt,
+                                               uint32_t RejectRemoteStd,
+                                               uint32_t RejectRemoteExt)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_NON_MATCHING(NonMatchingStd));
+  assert_param(IS_FDCAN_NON_MATCHING(NonMatchingExt));
+  assert_param(IS_FDCAN_REJECT_REMOTE(RejectRemoteStd));
+  assert_param(IS_FDCAN_REJECT_REMOTE(RejectRemoteExt));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Configure global filter */
+    hfdcan->Instance->GFC = ((NonMatchingStd << FDCAN_GFC_ANFS_Pos)  |
+                             (NonMatchingExt << FDCAN_GFC_ANFE_Pos)  |
+                             (RejectRemoteStd << FDCAN_GFC_RRFS_Pos) |
+                             (RejectRemoteExt << FDCAN_GFC_RRFE_Pos));
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the extended ID mask.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  Mask Extended ID Mask.
+  *         This parameter must be a number between 0 and 0x1FFFFFFF
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_MAX_VALUE(Mask, 0x1FFFFFFFU));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Configure the extended ID mask */
+    hfdcan->Instance->XIDAM = Mask;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the Rx FIFO operation mode.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  RxFifo Rx FIFO.
+  *         This parameter can be one of the following values:
+  *           @arg FDCAN_RX_FIFO0: Rx FIFO 0
+  *           @arg FDCAN_RX_FIFO1: Rx FIFO 1
+  * @param  OperationMode operation mode.
+  *         This parameter can be a value of @arg FDCAN_Rx_FIFO_operation_mode.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_RX_FIFO(RxFifo));
+  assert_param(IS_FDCAN_RX_FIFO_MODE(OperationMode));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    if (RxFifo == FDCAN_RX_FIFO0)
+    {
+      /* Select FIFO 0 Operation Mode */
+      MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0OM, OperationMode);
+    }
+    else /* RxFifo == FDCAN_RX_FIFO1 */
+    {
+      /* Select FIFO 1 Operation Mode */
+      MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1OM, OperationMode);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the FIFO watermark.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  FIFO select the FIFO to be configured.
+  *         This parameter can be a value of @arg FDCAN_FIFO_watermark.
+  * @param  Watermark level for FIFO watermark interrupt.
+  *         This parameter must be a number between:
+  *           - 0 and 32, if FIFO is FDCAN_CFG_TX_EVENT_FIFO
+  *           - 0 and 64, if FIFO is FDCAN_CFG_RX_FIFO0 or FDCAN_CFG_RX_FIFO1
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigFifoWatermark(FDCAN_HandleTypeDef *hfdcan, uint32_t FIFO, uint32_t Watermark)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_FIFO_WATERMARK(FIFO));
+  if (FIFO == FDCAN_CFG_TX_EVENT_FIFO)
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(Watermark, 32U));
+  }
+  else /* (FIFO == FDCAN_CFG_RX_FIFO0) || (FIFO == FDCAN_CFG_RX_FIFO1) */
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(Watermark, 64U));
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Set the level for FIFO watermark interrupt */
+    if (FIFO == FDCAN_CFG_TX_EVENT_FIFO)
+    {
+      MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFWM, (Watermark << FDCAN_TXEFC_EFWM_Pos));
+    }
+    else if (FIFO == FDCAN_CFG_RX_FIFO0)
+    {
+      MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0WM, (Watermark << FDCAN_RXF0C_F0WM_Pos));
+    }
+    else /* FIFO == FDCAN_CFG_RX_FIFO1 */
+    {
+      MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1WM, (Watermark << FDCAN_RXF1C_F1WM_Pos));
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the RAM watchdog.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  CounterStartValue Start value of the Message RAM Watchdog Counter,
+  *         This parameter must be a number between 0x00 and 0xFF,
+  *         with the reset value of 0x00 the counter is disabled.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_MAX_VALUE(CounterStartValue, 0xFFU));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Configure the RAM watchdog counter start value */
+    MODIFY_REG(hfdcan->Instance->RWD, FDCAN_RWD_WDC, CounterStartValue);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the timestamp counter.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TimestampPrescaler Timestamp Counter Prescaler.
+  *         This parameter can be a value of @arg FDCAN_Timestamp_Prescaler.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TIMESTAMP_PRESCALER(TimestampPrescaler));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Configure prescaler */
+    MODIFY_REG(hfdcan->Instance->TSCC, FDCAN_TSCC_TCP, TimestampPrescaler);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable the timestamp counter.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TimestampOperation Timestamp counter operation.
+  *         This parameter can be a value of @arg FDCAN_Timestamp.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TIMESTAMP(TimestampOperation));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Enable timestamp counter */
+    MODIFY_REG(hfdcan->Instance->TSCC, FDCAN_TSCC_TSS, TimestampOperation);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable the timestamp counter.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Disable timestamp counter */
+    CLEAR_BIT(hfdcan->Instance->TSCC, FDCAN_TSCC_TSS);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get the timestamp counter value.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval Value Timestamp counter value
+  */
+uint16_t HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+  return (uint16_t)(hfdcan->Instance->TSCV);
+}
+
+/**
+  * @brief  Reset the timestamp counter to zero.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+  if ((hfdcan->Instance->TSCC & FDCAN_TSCC_TSS) != FDCAN_TIMESTAMP_EXTERNAL)
+  {
+    /* Reset timestamp counter.
+       Actually any write operation to TSCV clears the counter */
+    CLEAR_REG(hfdcan->Instance->TSCV);
+  }
+  else
+  {
+    /* Update error code.
+       Unable to reset external counter */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+    return HAL_ERROR;
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the timeout counter.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TimeoutOperation Timeout counter operation.
+  *         This parameter can be a value of @arg FDCAN_Timeout_Operation.
+  * @param  TimeoutPeriod Start value of the timeout down-counter.
+  *         This parameter must be a number between 0x0000 and 0xFFFF
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TIMEOUT(TimeoutOperation));
+  assert_param(IS_FDCAN_MAX_VALUE(TimeoutPeriod, 0xFFFFU));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Select timeout operation and configure period */
+    MODIFY_REG(hfdcan->Instance->TOCC, (FDCAN_TOCC_TOS | FDCAN_TOCC_TOP), (TimeoutOperation | (TimeoutPeriod << FDCAN_TOCC_TOP_Pos)));
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable the timeout counter.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Enable timeout counter */
+    SET_BIT(hfdcan->Instance->TOCC, FDCAN_TOCC_ETOC);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable the timeout counter.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Disable timeout counter */
+    CLEAR_BIT(hfdcan->Instance->TOCC, FDCAN_TOCC_ETOC);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get the timeout counter value.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval Value Timeout counter value
+  */
+uint16_t HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+  return (uint16_t)(hfdcan->Instance->TOCV);
+}
+
+/**
+  * @brief  Reset the timeout counter to its start value.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+  if ((hfdcan->Instance->TOCC & FDCAN_TOCC_TOS) == FDCAN_TIMEOUT_CONTINUOUS)
+  {
+    /* Reset timeout counter to start value */
+    CLEAR_REG(hfdcan->Instance->TOCV);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code.
+       Unable to reset counter: controlled only by FIFO empty state */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the transmitter delay compensation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TdcOffset Transmitter Delay Compensation Offset.
+  *         This parameter must be a number between 0x00 and 0x7F.
+  * @param  TdcFilter Transmitter Delay Compensation Filter Window Length.
+  *         This parameter must be a number between 0x00 and 0x7F.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_MAX_VALUE(TdcOffset, 0x7FU));
+  assert_param(IS_FDCAN_MAX_VALUE(TdcFilter, 0x7FU));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Configure TDC offset and filter window */
+    hfdcan->Instance->TDCR = ((TdcFilter << FDCAN_TDCR_TDCF_Pos) | (TdcOffset << FDCAN_TDCR_TDCO_Pos));
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable the transmitter delay compensation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Enable transmitter delay compensation */
+    SET_BIT(hfdcan->Instance->DBTP, FDCAN_DBTP_TDC);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable the transmitter delay compensation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Disable transmitter delay compensation */
+    CLEAR_BIT(hfdcan->Instance->DBTP, FDCAN_DBTP_TDC);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable ISO 11898-1 protocol mode.
+  *         CAN FD frame format is according to ISO 11898-1 standard.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Disable Non ISO protocol mode */
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_NISO);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable ISO 11898-1 protocol mode.
+  *         CAN FD frame format is according to Bosch CAN FD specification V1.0.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Enable Non ISO protocol mode */
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_NISO);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable edge filtering during bus integration.
+  *         Two consecutive dominant tq are required to detect an edge for hard synchronization.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Enable edge filtering */
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_EFBI);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable edge filtering during bus integration.
+  *         One dominant tq is required to detect an edge for hard synchronization.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Disable edge filtering */
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_EFBI);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Exported_Functions_Group3 Control functions
+ *  @brief    Control functions
+ *
+@verbatim
+  ==============================================================================
+                          ##### Control functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) HAL_FDCAN_Start                         : Start the FDCAN module
+      (+) HAL_FDCAN_Stop                          : Stop the FDCAN module and enable access to configuration registers
+      (+) HAL_FDCAN_AddMessageToTxFifoQ           : Add a message to the Tx FIFO/Queue and activate the corresponding transmission request
+      (+) HAL_FDCAN_AddMessageToTxBuffer          : Add a message to a dedicated Tx buffer
+      (+) HAL_FDCAN_EnableTxBufferRequest         : Enable transmission request
+      (+) HAL_FDCAN_GetLatestTxFifoQRequestBuffer : Get Tx buffer index of latest Tx FIFO/Queue request
+      (+) HAL_FDCAN_AbortTxRequest                : Abort transmission request
+      (+) HAL_FDCAN_GetRxMessage                  : Get an FDCAN frame from the Rx Buffer/FIFO zone into the message RAM
+      (+) HAL_FDCAN_GetTxEvent                    : Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM
+      (+) HAL_FDCAN_GetHighPriorityMessageStatus  : Get high priority message status
+      (+) HAL_FDCAN_GetProtocolStatus             : Get protocol status
+      (+) HAL_FDCAN_GetErrorCounters              : Get error counter values
+      (+) HAL_FDCAN_IsRxBufferMessageAvailable    : Check if a new message is received in the selected Rx buffer
+      (+) HAL_FDCAN_IsTxBufferMessagePending      : Check if a transmission request is pending on the selected Tx buffer
+      (+) HAL_FDCAN_GetRxFifoFillLevel            : Return Rx FIFO fill level
+      (+) HAL_FDCAN_GetTxFifoFreeLevel            : Return Tx FIFO free level
+      (+) HAL_FDCAN_IsRestrictedOperationMode     : Check if the FDCAN peripheral entered Restricted Operation Mode
+      (+) HAL_FDCAN_ExitRestrictedOperationMode   : Exit Restricted Operation Mode
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Start the FDCAN module.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Change FDCAN peripheral state */
+    hfdcan->State = HAL_FDCAN_STATE_BUSY;
+
+    /* Request leave initialisation */
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
+
+    /* Reset the FDCAN ErrorCode */
+    hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Stop the FDCAN module and enable access to configuration registers.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
+  {
+    /* Request initialisation */
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
+
+    /* Wait until the INIT bit into CCCR register is set */
+    while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Reset counter */
+    Counter = 0U;
+
+    /* Exit from Sleep mode */
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
+
+    /* Wait until FDCAN exits sleep mode */
+    while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Enable configuration change */
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE);
+
+    /* Reset Latest Tx FIFO/Queue Request Buffer Index */
+    hfdcan->LatestTxFifoQRequest = 0U;
+
+    /* Change FDCAN peripheral state */
+    hfdcan->State = HAL_FDCAN_STATE_READY;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Add a message to the Tx FIFO/Queue and activate the corresponding transmission request
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure.
+  * @param  pTxData pointer to a buffer containing the payload of the Tx frame.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData)
+{
+  uint32_t PutIndex;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_ID_TYPE(pTxHeader->IdType));
+  if (pTxHeader->IdType == FDCAN_STANDARD_ID)
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x7FFU));
+  }
+  else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x1FFFFFFFU));
+  }
+  assert_param(IS_FDCAN_FRAME_TYPE(pTxHeader->TxFrameType));
+  assert_param(IS_FDCAN_DLC(pTxHeader->DataLength));
+  assert_param(IS_FDCAN_ESI(pTxHeader->ErrorStateIndicator));
+  assert_param(IS_FDCAN_BRS(pTxHeader->BitRateSwitch));
+  assert_param(IS_FDCAN_FDF(pTxHeader->FDFormat));
+  assert_param(IS_FDCAN_EFC(pTxHeader->TxEventFifoControl));
+  assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->MessageMarker, 0xFFU));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
+  {
+    /* Check that the Tx FIFO/Queue has an allocated area into the RAM */
+    if ((hfdcan->Instance->TXBC & FDCAN_TXBC_TFQS) == 0U)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+      return HAL_ERROR;
+    }
+
+    /* Check that the Tx FIFO/Queue is not full */
+    if ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQF) != 0U)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_FULL;
+
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Retrieve the Tx FIFO PutIndex */
+      PutIndex = ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQPI) >> FDCAN_TXFQS_TFQPI_Pos);
+
+      /* Add the message to the Tx FIFO/Queue */
+      FDCAN_CopyMessageToRAM(hfdcan, pTxHeader, pTxData, PutIndex);
+
+      /* Activate the corresponding transmission request */
+      hfdcan->Instance->TXBAR = ((uint32_t)1 << PutIndex);
+
+      /* Store the Latest Tx FIFO/Queue Request Buffer Index */
+      hfdcan->LatestTxFifoQRequest = ((uint32_t)1 << PutIndex);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Add a message to a dedicated Tx buffer
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure.
+  * @param  pTxData pointer to a buffer containing the payload of the Tx frame.
+  * @param  BufferIndex index of the buffer to be configured.
+  *         This parameter can be a value of @arg FDCAN_Tx_location.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxBuffer(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex)
+{
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_ID_TYPE(pTxHeader->IdType));
+  if (pTxHeader->IdType == FDCAN_STANDARD_ID)
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x7FFU));
+  }
+  else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x1FFFFFFFU));
+  }
+  assert_param(IS_FDCAN_FRAME_TYPE(pTxHeader->TxFrameType));
+  assert_param(IS_FDCAN_DLC(pTxHeader->DataLength));
+  assert_param(IS_FDCAN_ESI(pTxHeader->ErrorStateIndicator));
+  assert_param(IS_FDCAN_BRS(pTxHeader->BitRateSwitch));
+  assert_param(IS_FDCAN_FDF(pTxHeader->FDFormat));
+  assert_param(IS_FDCAN_EFC(pTxHeader->TxEventFifoControl));
+  assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->MessageMarker, 0xFFU));
+  assert_param(IS_FDCAN_TX_LOCATION(BufferIndex));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Check that the selected buffer has an allocated area into the RAM */
+    if (POSITION_VAL(BufferIndex) >= ((hfdcan->Instance->TXBC & FDCAN_TXBC_NDTB) >> FDCAN_TXBC_NDTB_Pos))
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+      return HAL_ERROR;
+    }
+
+    /* Check that there is no transmittion request pending for the selected buffer */
+    if ((hfdcan->Instance->TXBRP & BufferIndex) != 0U)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING;
+
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Add the message to the Tx buffer */
+      FDCAN_CopyMessageToRAM(hfdcan, pTxHeader, pTxData, POSITION_VAL(BufferIndex));
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable transmission request.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  BufferIndex buffer index.
+  *         This parameter can be any combination of @arg FDCAN_Tx_location.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_EnableTxBufferRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
+  {
+    /* Add transmission request */
+    hfdcan->Instance->TXBAR = BufferIndex;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get Tx buffer index of latest Tx FIFO/Queue request
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval Tx buffer index of last Tx FIFO/Queue request
+  *          - Any value of @arg FDCAN_Tx_location if Tx request has been submitted.
+  *          - 0 if no Tx FIFO/Queue request have been submitted.
+  */
+uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Return Last Tx FIFO/Queue Request Buffer */
+  return hfdcan->LatestTxFifoQRequest;
+}
+
+/**
+  * @brief  Abort transmission request
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  BufferIndex buffer index.
+  *         This parameter can be any combination of @arg FDCAN_Tx_location.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
+  {
+    /* Add cancellation request */
+    hfdcan->Instance->TXBCR = BufferIndex;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get an FDCAN frame from the Rx Buffer/FIFO zone into the message RAM.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  RxLocation Location of the received message to be read.
+  *         This parameter can be a value of @arg FDCAN_Rx_location.
+  * @param  pRxHeader pointer to a FDCAN_RxHeaderTypeDef structure.
+  * @param  pRxData pointer to a buffer where the payload of the Rx frame will be stored.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData)
+{
+  uint32_t *RxAddress;
+  uint8_t  *pData;
+  uint32_t ByteCounter;
+  uint32_t GetIndex = 0;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  if (state == HAL_FDCAN_STATE_BUSY)
+  {
+    if (RxLocation == FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */
+    {
+      /* Check that the Rx FIFO 0 has an allocated area into the RAM */
+      if ((hfdcan->Instance->RXF0C & FDCAN_RXF0C_F0S) == 0U)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+        return HAL_ERROR;
+      }
+
+      /* Check that the Rx FIFO 0 is not empty */
+      if ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0FL) == 0U)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
+
+        return HAL_ERROR;
+      }
+      else
+      {
+        /* Calculate Rx FIFO 0 element address */
+        GetIndex = ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0GI) >> FDCAN_RXF0S_F0GI_Pos);
+        RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO0SA + (GetIndex * hfdcan->Init.RxFifo0ElmtSize * 4U));
+      }
+    }
+    else if (RxLocation == FDCAN_RX_FIFO1) /* Rx element is assigned to the Rx FIFO 1 */
+    {
+      /* Check that the Rx FIFO 1 has an allocated area into the RAM */
+      if ((hfdcan->Instance->RXF1C & FDCAN_RXF1C_F1S) == 0U)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+        return HAL_ERROR;
+      }
+
+      /* Check that the Rx FIFO 0 is not empty */
+      if ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL) == 0U)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
+
+        return HAL_ERROR;
+      }
+      else
+      {
+        /* Calculate Rx FIFO 1 element address */
+        GetIndex = ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1GI) >> FDCAN_RXF1S_F1GI_Pos);
+        RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO1SA + (GetIndex * hfdcan->Init.RxFifo1ElmtSize * 4U));
+      }
+    }
+    else /* Rx element is assigned to a dedicated Rx buffer */
+    {
+      /* Check that the selected buffer has an allocated area into the RAM */
+      if (RxLocation >= hfdcan->Init.RxBuffersNbr)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+        return HAL_ERROR;
+      }
+      else
+      {
+        /* Calculate Rx buffer address */
+        RxAddress = (uint32_t *)(hfdcan->msgRam.RxBufferSA + (RxLocation * hfdcan->Init.RxBufferSize * 4U));
+      }
+    }
+
+    /* Retrieve IdType */
+    pRxHeader->IdType = *RxAddress & FDCAN_ELEMENT_MASK_XTD;
+
+    /* Retrieve Identifier */
+    if (pRxHeader->IdType == FDCAN_STANDARD_ID) /* Standard ID element */
+    {
+      pRxHeader->Identifier = ((*RxAddress & FDCAN_ELEMENT_MASK_STDID) >> 18);
+    }
+    else /* Extended ID element */
+    {
+      pRxHeader->Identifier = (*RxAddress & FDCAN_ELEMENT_MASK_EXTID);
+    }
+
+    /* Retrieve RxFrameType */
+    pRxHeader->RxFrameType = (*RxAddress & FDCAN_ELEMENT_MASK_RTR);
+
+    /* Retrieve ErrorStateIndicator */
+    pRxHeader->ErrorStateIndicator = (*RxAddress & FDCAN_ELEMENT_MASK_ESI);
+
+    /* Increment RxAddress pointer to second word of Rx FIFO element */
+    RxAddress++;
+
+    /* Retrieve RxTimestamp */
+    pRxHeader->RxTimestamp = (*RxAddress & FDCAN_ELEMENT_MASK_TS);
+
+    /* Retrieve DataLength */
+    pRxHeader->DataLength = (*RxAddress & FDCAN_ELEMENT_MASK_DLC);
+
+    /* Retrieve BitRateSwitch */
+    pRxHeader->BitRateSwitch = (*RxAddress & FDCAN_ELEMENT_MASK_BRS);
+
+    /* Retrieve FDFormat */
+    pRxHeader->FDFormat = (*RxAddress & FDCAN_ELEMENT_MASK_FDF);
+
+    /* Retrieve FilterIndex */
+    pRxHeader->FilterIndex = ((*RxAddress & FDCAN_ELEMENT_MASK_FIDX) >> 24);
+
+    /* Retrieve NonMatchingFrame */
+    pRxHeader->IsFilterMatchingFrame = ((*RxAddress & FDCAN_ELEMENT_MASK_ANMF) >> 31);
+
+    /* Increment RxAddress pointer to payload of Rx FIFO element */
+    RxAddress++;
+
+    /* Retrieve Rx payload */
+    pData = (uint8_t *)RxAddress;
+    for (ByteCounter = 0; ByteCounter < DLCtoBytes[pRxHeader->DataLength >> 16]; ByteCounter++)
+    {
+      pRxData[ByteCounter] = pData[ByteCounter];
+    }
+
+    if (RxLocation == FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */
+    {
+      /* Acknowledge the Rx FIFO 0 that the oldest element is read so that it increments the GetIndex */
+      hfdcan->Instance->RXF0A = GetIndex;
+    }
+    else if (RxLocation == FDCAN_RX_FIFO1) /* Rx element is assigned to the Rx FIFO 1 */
+    {
+      /* Acknowledge the Rx FIFO 1 that the oldest element is read so that it increments the GetIndex */
+      hfdcan->Instance->RXF1A = GetIndex;
+    }
+    else /* Rx element is assigned to a dedicated Rx buffer */
+    {
+      /* Clear the New Data flag of the current Rx buffer */
+      if (RxLocation < FDCAN_RX_BUFFER32)
+      {
+        hfdcan->Instance->NDAT1 = ((uint32_t)1 << RxLocation);
+      }
+      else /* FDCAN_RX_BUFFER32 <= RxLocation <= FDCAN_RX_BUFFER63 */
+      {
+        hfdcan->Instance->NDAT2 = ((uint32_t)1 << (RxLocation & 0x1FU));
+      }
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  pTxEvent pointer to a FDCAN_TxEventFifoTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent)
+{
+  uint32_t *TxEventAddress;
+  uint32_t GetIndex;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_MIN_VALUE(hfdcan->Init.TxEventsNbr, 1U));
+
+  if (state == HAL_FDCAN_STATE_BUSY)
+  {
+    /* Check that the Tx Event FIFO has an allocated area into the RAM */
+    if ((hfdcan->Instance->TXEFC & FDCAN_TXEFC_EFS) == 0U)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+      return HAL_ERROR;
+    }
+
+    /* Check that the Tx event FIFO is not empty */
+    if ((hfdcan->Instance->TXEFS & FDCAN_TXEFS_EFFL) == 0U)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
+
+      return HAL_ERROR;
+    }
+
+    /* Calculate Tx event FIFO element address */
+    GetIndex = ((hfdcan->Instance->TXEFS & FDCAN_TXEFS_EFGI) >> FDCAN_TXEFS_EFGI_Pos);
+    TxEventAddress = (uint32_t *)(hfdcan->msgRam.TxEventFIFOSA + (GetIndex * 2U * 4U));
+
+    /* Retrieve IdType */
+    pTxEvent->IdType = *TxEventAddress & FDCAN_ELEMENT_MASK_XTD;
+
+    /* Retrieve Identifier */
+    if (pTxEvent->IdType == FDCAN_STANDARD_ID) /* Standard ID element */
+    {
+      pTxEvent->Identifier = ((*TxEventAddress & FDCAN_ELEMENT_MASK_STDID) >> 18U);
+    }
+    else /* Extended ID element */
+    {
+      pTxEvent->Identifier = (*TxEventAddress & FDCAN_ELEMENT_MASK_EXTID);
+    }
+
+    /* Retrieve RxFrameType */
+    pTxEvent->TxFrameType = (*TxEventAddress & FDCAN_ELEMENT_MASK_RTR);
+
+    /* Retrieve ErrorStateIndicator */
+    pTxEvent->ErrorStateIndicator = (*TxEventAddress & FDCAN_ELEMENT_MASK_ESI);
+
+    /* Increment TxEventAddress pointer to second word of Tx Event FIFO element */
+    TxEventAddress++;
+
+    /* Retrieve RxTimestamp */
+    pTxEvent->TxTimestamp = (*TxEventAddress & FDCAN_ELEMENT_MASK_TS);
+
+    /* Retrieve DataLength */
+    pTxEvent->DataLength = (*TxEventAddress & FDCAN_ELEMENT_MASK_DLC);
+
+    /* Retrieve BitRateSwitch */
+    pTxEvent->BitRateSwitch = (*TxEventAddress & FDCAN_ELEMENT_MASK_BRS);
+
+    /* Retrieve FDFormat */
+    pTxEvent->FDFormat = (*TxEventAddress & FDCAN_ELEMENT_MASK_FDF);
+
+    /* Retrieve EventType */
+    pTxEvent->EventType = (*TxEventAddress & FDCAN_ELEMENT_MASK_ET);
+
+    /* Retrieve MessageMarker */
+    pTxEvent->MessageMarker = ((*TxEventAddress & FDCAN_ELEMENT_MASK_MM) >> 24);
+
+    /* Acknowledge the Tx Event FIFO that the oldest element is read so that it increments the GetIndex */
+    hfdcan->Instance->TXEFA = GetIndex;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get high priority message status.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  HpMsgStatus pointer to an FDCAN_HpMsgStatusTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus)
+{
+  HpMsgStatus->FilterList = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FLST) >> FDCAN_HPMS_FLST_Pos);
+  HpMsgStatus->FilterIndex = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FIDX) >> FDCAN_HPMS_FIDX_Pos);
+  HpMsgStatus->MessageStorage = (hfdcan->Instance->HPMS & FDCAN_HPMS_MSI);
+  HpMsgStatus->MessageIndex = (hfdcan->Instance->HPMS & FDCAN_HPMS_BIDX);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get protocol status.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  ProtocolStatus pointer to an FDCAN_ProtocolStatusTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus)
+{
+  uint32_t StatusReg;
+
+  /* Read the protocol status register */
+  StatusReg = READ_REG(hfdcan->Instance->PSR);
+
+  /* Fill the protocol status structure */
+  ProtocolStatus->LastErrorCode = (StatusReg & FDCAN_PSR_LEC);
+  ProtocolStatus->DataLastErrorCode = ((StatusReg & FDCAN_PSR_DLEC) >> FDCAN_PSR_DLEC_Pos);
+  ProtocolStatus->Activity = (StatusReg & FDCAN_PSR_ACT);
+  ProtocolStatus->ErrorPassive = ((StatusReg & FDCAN_PSR_EP) >> FDCAN_PSR_EP_Pos);
+  ProtocolStatus->Warning = ((StatusReg & FDCAN_PSR_EW) >> FDCAN_PSR_EW_Pos);
+  ProtocolStatus->BusOff = ((StatusReg & FDCAN_PSR_BO) >> FDCAN_PSR_BO_Pos);
+  ProtocolStatus->RxESIflag = ((StatusReg & FDCAN_PSR_RESI) >> FDCAN_PSR_RESI_Pos);
+  ProtocolStatus->RxBRSflag = ((StatusReg & FDCAN_PSR_RBRS) >> FDCAN_PSR_RBRS_Pos);
+  ProtocolStatus->RxFDFflag = ((StatusReg & FDCAN_PSR_REDL) >> FDCAN_PSR_REDL_Pos);
+  ProtocolStatus->ProtocolException = ((StatusReg & FDCAN_PSR_PXE) >> FDCAN_PSR_PXE_Pos);
+  ProtocolStatus->TDCvalue = ((StatusReg & FDCAN_PSR_TDCV) >> FDCAN_PSR_TDCV_Pos);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get error counter values.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  ErrorCounters pointer to an FDCAN_ErrorCountersTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters)
+{
+  uint32_t CountersReg;
+
+  /* Read the error counters register */
+  CountersReg = READ_REG(hfdcan->Instance->ECR);
+
+  /* Fill the error counters structure */
+  ErrorCounters->TxErrorCnt = ((CountersReg & FDCAN_ECR_TEC) >> FDCAN_ECR_TEC_Pos);
+  ErrorCounters->RxErrorCnt = ((CountersReg & FDCAN_ECR_REC) >> FDCAN_ECR_REC_Pos);
+  ErrorCounters->RxErrorPassive = ((CountersReg & FDCAN_ECR_RP) >> FDCAN_ECR_RP_Pos);
+  ErrorCounters->ErrorLogging = ((CountersReg & FDCAN_ECR_CEL) >> FDCAN_ECR_CEL_Pos);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Check if a new message is received in the selected Rx buffer.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  RxBufferIndex Rx buffer index.
+  *         This parameter must be a number between 0 and 63.
+  * @retval Status
+  *          - 0 : No new message on RxBufferIndex.
+  *          - 1 : New message received on RxBufferIndex.
+  */
+uint32_t HAL_FDCAN_IsRxBufferMessageAvailable(FDCAN_HandleTypeDef *hfdcan, uint32_t RxBufferIndex)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_MAX_VALUE(RxBufferIndex, 63U));
+  uint32_t NewData1 = hfdcan->Instance->NDAT1;
+  uint32_t NewData2 = hfdcan->Instance->NDAT2;
+
+  /* Check new message reception on the selected buffer */
+  if (((RxBufferIndex < 32U) && ((NewData1 & (uint32_t)((uint32_t)1 << RxBufferIndex)) == 0U)) ||
+      ((RxBufferIndex >= 32U) && ((NewData2 & (uint32_t)((uint32_t)1 << (RxBufferIndex & 0x1FU))) == 0U)))
+  {
+    return 0;
+  }
+
+  /* Clear the New Data flag of the current Rx buffer */
+  if (RxBufferIndex < 32U)
+  {
+    hfdcan->Instance->NDAT1 = ((uint32_t)1 << RxBufferIndex);
+  }
+  else /* 32 <= RxBufferIndex <= 63 */
+  {
+    hfdcan->Instance->NDAT2 = ((uint32_t)1 << (RxBufferIndex & 0x1FU));
+  }
+
+  return 1;
+}
+
+/**
+  * @brief  Check if a transmission request is pending on the selected Tx buffer.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TxBufferIndex Tx buffer index.
+  *         This parameter can be any combination of @arg FDCAN_Tx_location.
+  * @retval Status
+  *          - 0 : No pending transmission request on TxBufferIndex.
+  *          - 1 : Pending transmission request on TxBufferIndex.
+  */
+uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex)
+{
+  /* Check pending transmittion request on the selected buffer */
+  if ((hfdcan->Instance->TXBRP & TxBufferIndex) == 0U)
+  {
+    return 0;
+  }
+  return 1;
+}
+
+/**
+  * @brief  Return Rx FIFO fill level.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  RxFifo Rx FIFO.
+  *         This parameter can be one of the following values:
+  *           @arg FDCAN_RX_FIFO0: Rx FIFO 0
+  *           @arg FDCAN_RX_FIFO1: Rx FIFO 1
+  * @retval Level Rx FIFO fill level.
+  */
+uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo)
+{
+  uint32_t FillLevel;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_RX_FIFO(RxFifo));
+
+  if (RxFifo == FDCAN_RX_FIFO0)
+  {
+    FillLevel = hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0FL;
+  }
+  else /* RxFifo == FDCAN_RX_FIFO1 */
+  {
+    FillLevel = hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL;
+  }
+
+  /* Return Rx FIFO fill level */
+  return FillLevel;
+}
+
+/**
+  * @brief  Return Tx FIFO free level: number of consecutive free Tx FIFO
+  *         elements starting from Tx FIFO GetIndex.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval Level Tx FIFO free level.
+  */
+uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t FreeLevel;
+
+  FreeLevel = hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFFL;
+
+  /* Return Tx FIFO free level */
+  return FreeLevel;
+}
+
+/**
+  * @brief  Check if the FDCAN peripheral entered Restricted Operation Mode.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval Status
+  *          - 0 : Normal FDCAN operation.
+  *          - 1 : Restricted Operation Mode active.
+  */
+uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t OperationMode;
+
+  /* Get Operation Mode */
+  OperationMode = ((hfdcan->Instance->CCCR & FDCAN_CCCR_ASM) >> FDCAN_CCCR_ASM_Pos);
+
+  return OperationMode;
+}
+
+/**
+  * @brief  Exit Restricted Operation Mode.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Exit Restricted Operation mode */
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Exported_Functions_Group4 TT Configuration and control functions
+ *  @brief    TT Configuration and control functions
+ *
+@verbatim
+  ==============================================================================
+              ##### TT Configuration and control functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) HAL_FDCAN_TT_ConfigOperation                  : Initialize TT operation parameters
+      (+) HAL_FDCAN_TT_ConfigReferenceMessage           : Configure the reference message
+      (+) HAL_FDCAN_TT_ConfigTrigger                    : Configure the FDCAN trigger
+      (+) HAL_FDCAN_TT_SetGlobalTime                    : Schedule global time adjustment
+      (+) HAL_FDCAN_TT_SetClockSynchronization          : Schedule TUR numerator update
+      (+) HAL_FDCAN_TT_ConfigStopWatch                  : Configure stop watch source and polarity
+      (+) HAL_FDCAN_TT_ConfigRegisterTimeMark           : Configure register time mark pulse generation
+        (+) HAL_FDCAN_TT_EnableRegisterTimeMarkPulse      : Enable register time mark pulse generation
+        (+) HAL_FDCAN_TT_DisableRegisterTimeMarkPulse     : Disable register time mark pulse generation
+      (+) HAL_FDCAN_TT_EnableTriggerTimeMarkPulse       : Enable trigger time mark pulse generation
+      (+) HAL_FDCAN_TT_DisableTriggerTimeMarkPulse      : Disable trigger time mark pulse generation
+      (+) HAL_FDCAN_TT_EnableHardwareGapControl         : Enable gap control by input pin fdcan1_evt
+      (+) HAL_FDCAN_TT_DisableHardwareGapControl        : Disable gap control by input pin fdcan1_evt
+      (+) HAL_FDCAN_TT_EnableTimeMarkGapControl         : Enable gap control (finish only) by register time mark interrupt
+      (+) HAL_FDCAN_TT_DisableTimeMarkGapControl        : Disable gap control by register time mark interrupt
+      (+) HAL_FDCAN_TT_SetNextIsGap                     : Transmit next reference message with Next_is_Gap = "1"
+      (+) HAL_FDCAN_TT_SetEndOfGap                      : Finish a Gap by requesting start of reference message
+      (+) HAL_FDCAN_TT_ConfigExternalSyncPhase          : Configure target phase used for external synchronization
+        (+) HAL_FDCAN_TT_EnableExternalSynchronization    : Synchronize the phase of the FDCAN schedule to an external schedule
+        (+) HAL_FDCAN_TT_DisableExternalSynchronization   : Disable external schedule synchronization
+      (+) HAL_FDCAN_TT_GetOperationStatus               : Get TT operation status
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize TT operation parameters.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  pTTParams pointer to a FDCAN_TT_ConfigTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigOperation(FDCAN_HandleTypeDef *hfdcan, FDCAN_TT_ConfigTypeDef *pTTParams)
+{
+  uint32_t tickstart;
+  uint32_t RAMcounter;
+  uint32_t StartAddress;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_TUR_NUMERATOR(pTTParams->TURNumerator));
+  assert_param(IS_FDCAN_TT_TUR_DENOMINATOR(pTTParams->TURDenominator));
+  assert_param(IS_FDCAN_TT_TIME_MASTER(pTTParams->TimeMaster));
+  assert_param(IS_FDCAN_MAX_VALUE(pTTParams->SyncDevLimit, 7U));
+  assert_param(IS_FDCAN_MAX_VALUE(pTTParams->InitRefTrigOffset, 127U));
+  assert_param(IS_FDCAN_MAX_VALUE(pTTParams->TriggerMemoryNbr, 64U));
+  assert_param(IS_FDCAN_TT_CYCLE_START_SYNC(pTTParams->CycleStartSync));
+  assert_param(IS_FDCAN_TT_STOP_WATCH_TRIGGER(pTTParams->StopWatchTrigSel));
+  assert_param(IS_FDCAN_TT_EVENT_TRIGGER(pTTParams->EventTrigSel));
+  if (pTTParams->TimeMaster == FDCAN_TT_POTENTIAL_MASTER)
+  {
+    assert_param(IS_FDCAN_TT_BASIC_CYCLES_NUMBER(pTTParams->BasicCyclesNbr));
+  }
+  if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL0)
+  {
+    assert_param(IS_FDCAN_TT_OPERATION(pTTParams->GapEnable));
+    assert_param(IS_FDCAN_MAX_VALUE(pTTParams->AppWdgLimit, 255U));
+    assert_param(IS_FDCAN_TT_EVENT_TRIGGER_POLARITY(pTTParams->EvtTrigPolarity));
+    assert_param(IS_FDCAN_TT_TX_ENABLE_WINDOW(pTTParams->TxEnableWindow));
+    assert_param(IS_FDCAN_MAX_VALUE(pTTParams->ExpTxTrigNbr, 4095U));
+  }
+  if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL1)
+  {
+    assert_param(IS_FDCAN_TT_TUR_LEVEL_0_2(pTTParams->TURNumerator, pTTParams->TURDenominator));
+    assert_param(IS_FDCAN_TT_EXTERNAL_CLK_SYNC(pTTParams->ExternalClkSync));
+    assert_param(IS_FDCAN_TT_GLOBAL_TIME_FILTERING(pTTParams->GlobalTimeFilter));
+    assert_param(IS_FDCAN_TT_AUTO_CLK_CALIBRATION(pTTParams->ClockCalibration));
+  }
+  else
+  {
+    assert_param(IS_FDCAN_TT_TUR_LEVEL_1(pTTParams->TURNumerator, pTTParams->TURDenominator));
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Stop local time in order to enable write access to the other bits of TURCF register */
+    CLEAR_BIT(hfdcan->ttcan->TURCF, FDCAN_TURCF_ELT);
+
+    /* Get tick */
+    tickstart = HAL_GetTick();
+
+    /* Wait until the ELT bit into TURCF register is reset */
+    while ((hfdcan->ttcan->TURCF & FDCAN_TURCF_ELT) != 0U)
+    {
+      /* Check for the Timeout */
+      if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+    }
+
+    /* Configure TUR (Time Unit Ratio) */
+    MODIFY_REG(hfdcan->ttcan->TURCF,
+               (FDCAN_TURCF_NCL | FDCAN_TURCF_DC),
+               (((pTTParams->TURNumerator - 0x10000U) << FDCAN_TURCF_NCL_Pos) | (pTTParams->TURDenominator << FDCAN_TURCF_DC_Pos)));
+
+    /* Enable local time */
+    SET_BIT(hfdcan->ttcan->TURCF, FDCAN_TURCF_ELT);
+
+    /* Configure TT operation */
+    MODIFY_REG(hfdcan->ttcan->TTOCF,
+               (FDCAN_TTOCF_OM | FDCAN_TTOCF_TM | FDCAN_TTOCF_LDSDL | FDCAN_TTOCF_IRTO),
+               (pTTParams->OperationMode                           | \
+                pTTParams->TimeMaster                              | \
+                (pTTParams->SyncDevLimit << FDCAN_TTOCF_LDSDL_Pos) | \
+                (pTTParams->InitRefTrigOffset << FDCAN_TTOCF_IRTO_Pos)));
+    if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      MODIFY_REG(hfdcan->ttcan->TTOCF,
+                 (FDCAN_TTOCF_GEN | FDCAN_TTOCF_AWL | FDCAN_TTOCF_EVTP),
+                 (pTTParams->GapEnable                            | \
+                  (pTTParams->AppWdgLimit << FDCAN_TTOCF_AWL_Pos) | \
+                  pTTParams->EvtTrigPolarity));
+    }
+    if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL1)
+    {
+      MODIFY_REG(hfdcan->ttcan->TTOCF,
+                 (FDCAN_TTOCF_EECS | FDCAN_TTOCF_EGTF | FDCAN_TTOCF_ECC),
+                 (pTTParams->ExternalClkSync  | \
+                  pTTParams->GlobalTimeFilter | \
+                  pTTParams->ClockCalibration));
+    }
+
+    /* Configure system matrix limits */
+    MODIFY_REG(hfdcan->ttcan->TTMLM, FDCAN_TTMLM_CSS, pTTParams->CycleStartSync);
+    if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      MODIFY_REG(hfdcan->ttcan->TTMLM,
+                 (FDCAN_TTMLM_TXEW | FDCAN_TTMLM_ENTT),
+                 (((pTTParams->TxEnableWindow - 1U) << FDCAN_TTMLM_TXEW_Pos) | (pTTParams->ExpTxTrigNbr << FDCAN_TTMLM_ENTT_Pos)));
+    }
+    if (pTTParams->TimeMaster == FDCAN_TT_POTENTIAL_MASTER)
+    {
+      MODIFY_REG(hfdcan->ttcan->TTMLM, FDCAN_TTMLM_CCM, pTTParams->BasicCyclesNbr);
+    }
+
+    /* Configure input triggers: Stop watch and Event */
+    MODIFY_REG(hfdcan->ttcan->TTTS,
+               (FDCAN_TTTS_SWTSEL | FDCAN_TTTS_EVTSEL),
+               (pTTParams->StopWatchTrigSel | pTTParams->EventTrigSel));
+
+    /* Configure trigger memory start address */
+    StartAddress = (hfdcan->msgRam.EndAddress - SRAMCAN_BASE) / 4U;
+    MODIFY_REG(hfdcan->ttcan->TTTMC, FDCAN_TTTMC_TMSA, (StartAddress << FDCAN_TTTMC_TMSA_Pos));
+
+    /* Trigger memory elements number */
+    MODIFY_REG(hfdcan->ttcan->TTTMC, FDCAN_TTTMC_TME, (pTTParams->TriggerMemoryNbr << FDCAN_TTTMC_TME_Pos));
+
+    /* Recalculate End Address */
+    hfdcan->msgRam.TTMemorySA = hfdcan->msgRam.EndAddress;
+    hfdcan->msgRam.EndAddress = hfdcan->msgRam.TTMemorySA + (pTTParams->TriggerMemoryNbr * 2U * 4U);
+
+    if (hfdcan->msgRam.EndAddress > FDCAN_MESSAGE_RAM_END_ADDRESS) /* Last address of the Message RAM */
+    {
+      /* Update error code.
+         Message RAM overflow */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Flush the allocated Message RAM area */
+      for (RAMcounter = hfdcan->msgRam.TTMemorySA; RAMcounter < hfdcan->msgRam.EndAddress; RAMcounter += 4U)
+      {
+        *(uint32_t *)(RAMcounter) = 0x00000000;
+      }
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the reference message.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  IdType Identifier Type.
+  *         This parameter can be a value of @arg FDCAN_id_type.
+  * @param  Identifier Reference Identifier.
+  *         This parameter must be a number between:
+  *           - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+  *           - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID
+  * @param  Payload Enable or disable the additional payload.
+  *         This parameter can be a value of @arg FDCAN_TT_Reference_Message_Payload.
+  *         This parameter is ignored in case of time slaves.
+  *         If this parameter is set to FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD, the
+  *         following elements are taken from Tx Buffer 0:
+  *          - MessageMarker
+  *          - TxEventFifoControl
+  *          - DataLength
+  *          - Data Bytes (payload):
+  *             - bytes 2-8, for Level 1
+  *             - bytes 5-8, for Level 0 and Level 2
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigReferenceMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t IdType, uint32_t Identifier, uint32_t Payload)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_ID_TYPE(IdType));
+  if (IdType == FDCAN_STANDARD_ID)
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(Identifier, 0x7FFU));
+  }
+  else /* IdType == FDCAN_EXTENDED_ID */
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(Identifier, 0x1FFFFFFFU));
+  }
+  assert_param(IS_FDCAN_TT_REFERENCE_MESSAGE_PAYLOAD(Payload));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Configure reference message identifier type, identifier and payload */
+    if (IdType == FDCAN_EXTENDED_ID)
+    {
+      MODIFY_REG(hfdcan->ttcan->TTRMC, (FDCAN_TTRMC_RID | FDCAN_TTRMC_XTD | FDCAN_TTRMC_RMPS), (Payload | IdType | Identifier));
+    }
+    else /* IdType == FDCAN_STANDARD_ID */
+    {
+      MODIFY_REG(hfdcan->ttcan->TTRMC, (FDCAN_TTRMC_RID | FDCAN_TTRMC_XTD | FDCAN_TTRMC_RMPS), (Payload | IdType | (Identifier << 18)));
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the FDCAN trigger according to the specified
+  *         parameters in the FDCAN_TriggerTypeDef structure.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  sTriggerConfig pointer to an FDCAN_TriggerTypeDef structure that
+  *         contains the trigger configuration information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigTrigger(FDCAN_HandleTypeDef *hfdcan, FDCAN_TriggerTypeDef *sTriggerConfig)
+{
+  uint32_t CycleCode;
+  uint32_t MessageNumber;
+  uint32_t TriggerElementW1;
+  uint32_t TriggerElementW2;
+  uint32_t *TriggerAddress;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->TriggerIndex, 63U));
+  assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->TimeMark, 0xFFFFU));
+  assert_param(IS_FDCAN_TT_REPEAT_FACTOR(sTriggerConfig->RepeatFactor));
+  if (sTriggerConfig->RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE)
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->StartCycle, (sTriggerConfig->RepeatFactor - 1U)));
+  }
+  assert_param(IS_FDCAN_TT_TM_EVENT_INTERNAL(sTriggerConfig->TmEventInt));
+  assert_param(IS_FDCAN_TT_TM_EVENT_EXTERNAL(sTriggerConfig->TmEventExt));
+  assert_param(IS_FDCAN_TT_TRIGGER_TYPE(sTriggerConfig->TriggerType));
+  assert_param(IS_FDCAN_ID_TYPE(sTriggerConfig->FilterType));
+  if ((sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_SINGLE) ||
+      (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_CONTINUOUS) ||
+      (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_ARBITRATION) ||
+      (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_MERGED))
+  {
+    assert_param(IS_FDCAN_TX_LOCATION(sTriggerConfig->TxBufferIndex));
+  }
+  if (sTriggerConfig->TriggerType == FDCAN_TT_RX_TRIGGER)
+  {
+    if (sTriggerConfig->FilterType == FDCAN_STANDARD_ID)
+    {
+      assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->FilterIndex, 63U));
+    }
+    else /* sTriggerConfig->FilterType == FDCAN_EXTENDED_ID */
+    {
+      assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->FilterIndex, 127U));
+    }
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Calculate cycle code */
+    if (sTriggerConfig->RepeatFactor == FDCAN_TT_REPEAT_EVERY_CYCLE)
+    {
+      CycleCode = FDCAN_TT_REPEAT_EVERY_CYCLE;
+    }
+    else /* sTriggerConfig->RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE */
+    {
+      CycleCode = sTriggerConfig->RepeatFactor + sTriggerConfig->StartCycle;
+    }
+
+    /* Build first word of trigger element */
+    TriggerElementW1 = ((sTriggerConfig->TimeMark << 16) | \
+                        (CycleCode << 8)                 | \
+                        sTriggerConfig->TmEventInt       | \
+                        sTriggerConfig->TmEventExt       | \
+                        sTriggerConfig->TriggerType);
+
+    /* Select message number depending on trigger type (transmission or reception) */
+    if (sTriggerConfig->TriggerType == FDCAN_TT_RX_TRIGGER)
+    {
+      MessageNumber = sTriggerConfig->FilterIndex;
+    }
+    else if ((sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_SINGLE) ||
+             (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_CONTINUOUS) ||
+             (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_ARBITRATION) ||
+             (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_MERGED))
+    {
+      MessageNumber = POSITION_VAL(sTriggerConfig->TxBufferIndex);
+    }
+    else
+    {
+      MessageNumber = 0U;
+    }
+
+    /* Build second word of trigger element */
+    TriggerElementW2 = ((sTriggerConfig->FilterType >> 7) | (MessageNumber << 16));
+
+    /* Calculate trigger address */
+    TriggerAddress = (uint32_t *)(hfdcan->msgRam.TTMemorySA + (sTriggerConfig->TriggerIndex * 4U * 2U));
+
+    /* Write trigger element to the message RAM */
+    *TriggerAddress = TriggerElementW1;
+    TriggerAddress++;
+    *TriggerAddress = TriggerElementW2;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Schedule global time adjustment for the next reference message.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TimePreset time preset value.
+  *         This parameter must be a number between:
+  *           - 0x0000 and 0x7FFF, Next_Master_Ref_Mark = Current_Master_Ref_Mark + TimePreset
+  *           or
+  *           - 0x8001 and 0xFFFF, Next_Master_Ref_Mark = Current_Master_Ref_Mark - (0x10000 - TimePreset)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_SetGlobalTime(FDCAN_HandleTypeDef *hfdcan, uint32_t TimePreset)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_TIME_PRESET(TimePreset));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Check that the external clock synchronization is enabled */
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_EECS) != FDCAN_TTOCF_EECS)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+
+    /* Check that no global time preset is pending */
+    if ((hfdcan->ttcan->TTOST & FDCAN_TTOST_WGTD) == FDCAN_TTOST_WGTD)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING;
+
+      return HAL_ERROR;
+    }
+
+    /* Configure time preset */
+    MODIFY_REG(hfdcan->ttcan->TTGTP, FDCAN_TTGTP_TP, (TimePreset << FDCAN_TTGTP_TP_Pos));
+
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Schedule time preset to take effect by the next reference message */
+    SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_SGT);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Schedule TUR numerator update for the next reference message.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  NewTURNumerator new value of the TUR numerator.
+  *         This parameter must be a number between 0x10000 and 0x1FFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_SetClockSynchronization(FDCAN_HandleTypeDef *hfdcan, uint32_t NewTURNumerator)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_TUR_NUMERATOR(NewTURNumerator));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Check that the external clock synchronization is enabled */
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_EECS) != FDCAN_TTOCF_EECS)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+
+    /* Check that no external clock synchronization is pending */
+    if ((hfdcan->ttcan->TTOST & FDCAN_TTOST_WECS) == FDCAN_TTOST_WECS)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING;
+
+      return HAL_ERROR;
+    }
+
+    /* Configure new TUR numerator */
+    MODIFY_REG(hfdcan->ttcan->TURCF, FDCAN_TURCF_NCL, (NewTURNumerator - 0x10000U));
+
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Schedule TUR numerator update by the next reference message */
+    SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_ECS);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure stop watch source and polarity.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  Source stop watch source.
+  *         This parameter can be a value of @arg FDCAN_TT_stop_watch_source.
+  * @param  Polarity stop watch polarity.
+  *         This parameter can be a value of @arg FDCAN_TT_stop_watch_polarity.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigStopWatch(FDCAN_HandleTypeDef *hfdcan, uint32_t Source, uint32_t Polarity)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_STOP_WATCH_SOURCE(Source));
+  assert_param(IS_FDCAN_TT_STOP_WATCH_POLARITY(Polarity));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Select stop watch source and polarity */
+    MODIFY_REG(hfdcan->ttcan->TTOCN, (FDCAN_TTOCN_SWS | FDCAN_TTOCN_SWP), (Source | Polarity));
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure register time mark pulse generation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TimeMarkSource time mark source.
+  *         This parameter can be a value of @arg FDCAN_TT_time_mark_source.
+  * @param  TimeMarkValue time mark value (reference).
+  *         This parameter must be a number between 0 and 0xFFFF.
+  * @param  RepeatFactor repeat factor of the cycle for which the time mark is valid.
+  *         This parameter can be a value of @arg FDCAN_TT_Repeat_Factor.
+  * @param  StartCycle index of the first cycle in which the time mark becomes valid.
+  *         This parameter is ignored if RepeatFactor is set to FDCAN_TT_REPEAT_EVERY_CYCLE.
+  *         This parameter must be a number between 0 and RepeatFactor.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigRegisterTimeMark(FDCAN_HandleTypeDef *hfdcan,
+                                                      uint32_t TimeMarkSource, uint32_t TimeMarkValue,
+                                                      uint32_t RepeatFactor, uint32_t StartCycle)
+{
+  uint32_t Counter = 0U;
+  uint32_t CycleCode;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_REGISTER_TIME_MARK_SOURCE(TimeMarkSource));
+  assert_param(IS_FDCAN_MAX_VALUE(TimeMarkValue, 0xFFFFU));
+  assert_param(IS_FDCAN_TT_REPEAT_FACTOR(RepeatFactor));
+  if (RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE)
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(StartCycle, (RepeatFactor - 1U)));
+  }
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Disable the time mark compare function */
+    CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMC);
+
+    if (TimeMarkSource != FDCAN_TT_REG_TIMEMARK_DIABLED)
+    {
+      /* Calculate cycle code */
+      if (RepeatFactor == FDCAN_TT_REPEAT_EVERY_CYCLE)
+      {
+        CycleCode = FDCAN_TT_REPEAT_EVERY_CYCLE;
+      }
+      else /* RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE */
+      {
+        CycleCode = RepeatFactor + StartCycle;
+      }
+
+      Counter = 0U;
+
+      /* Wait until the LCKM bit into TTTMK register is reset */
+      while ((hfdcan->ttcan->TTTMK & FDCAN_TTTMK_LCKM) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_VALUE)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Configure time mark value and cycle code */
+      hfdcan->ttcan->TTTMK = ((TimeMarkValue << FDCAN_TTTMK_TM_Pos) | (CycleCode << FDCAN_TTTMK_TICC_Pos));
+
+      Counter = 0U;
+
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_VALUE)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Update the register time mark compare source */
+      MODIFY_REG(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMC, TimeMarkSource);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable register time mark pulse generation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Enable Register Time Mark Interrupt output on fdcan1_rtp */
+    SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_RTIE);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable register time mark pulse generation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Disable Register Time Mark Interrupt output on fdcan1_rtp */
+    CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_RTIE);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable trigger time mark pulse generation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_VALUE)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Enable Trigger Time Mark Interrupt output on fdcan1_tmp */
+      SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TTIE);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable trigger time mark pulse generation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_VALUE)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Disable Trigger Time Mark Interrupt output on fdcan1_rtp */
+      CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TTIE);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable gap control by input pin fdcan1_evt.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_VALUE)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Enable gap control by pin fdcan1_evt */
+      SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_GCS);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable gap control by input pin fdcan1_evt.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_VALUE)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Disable gap control by pin fdcan1_evt */
+      CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_GCS);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable gap control (finish only) by register time mark interrupt.
+  *         The next register time mark interrupt (TTIR.RTMI = "1") will finish
+  *         the Gap and start the reference message.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_VALUE)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Enable gap control by register time mark interrupt */
+      SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMG);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable gap control by register time mark interrupt.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_VALUE)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Disable gap control by register time mark interrupt */
+      CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMG);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Transmit next reference message with Next_is_Gap = "1".
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_SetNextIsGap(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Check that the node is configured for external event-synchronized TT operation */
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_GEN) != FDCAN_TTOCF_GEN)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_VALUE)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Set Next is Gap */
+      SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_NIG);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Finish a Gap by requesting start of reference message.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_SetEndOfGap(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Check that the node is configured for external event-synchronized TT operation */
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_GEN) != FDCAN_TTOCF_GEN)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_VALUE)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Set Finish Gap */
+      SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_FGP);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure target phase used for external synchronization by event
+  *         trigger input pin fdcan1_evt.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TargetPhase defines target value of cycle time when a rising edge
+  *         of fdcan1_evt is expected.
+  *         This parameter must be a number between 0 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigExternalSyncPhase(FDCAN_HandleTypeDef *hfdcan, uint32_t TargetPhase)
+{
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_MAX_VALUE(TargetPhase, 0xFFFFU));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Check that no external schedule synchronization is pending */
+    if ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_ESCN) == FDCAN_TTOCN_ESCN)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING;
+
+      return HAL_ERROR;
+    }
+
+    /* Configure cycle time target phase */
+    MODIFY_REG(hfdcan->ttcan->TTGTP, FDCAN_TTGTP_CTP, (TargetPhase << FDCAN_TTGTP_CTP_Pos));
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Synchronize the phase of the FDCAN schedule to an external schedule
+  *         using event trigger input pin fdcan1_evt.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Enable external synchronization */
+    SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_ESCN);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable external schedule synchronization.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Disable external synchronization */
+    CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_ESCN);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get TT operation status.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TTOpStatus pointer to an FDCAN_TTOperationStatusTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_GetOperationStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_TTOperationStatusTypeDef *TTOpStatus)
+{
+  uint32_t TTStatusReg;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  /* Read the TT operation status register */
+  TTStatusReg = READ_REG(hfdcan->ttcan->TTOST);
+
+  /* Fill the TT operation status structure */
+  TTOpStatus->ErrorLevel = (TTStatusReg & FDCAN_TTOST_EL);
+  TTOpStatus->MasterState = (TTStatusReg & FDCAN_TTOST_MS);
+  TTOpStatus->SyncState = (TTStatusReg & FDCAN_TTOST_SYS);
+  TTOpStatus->GTimeQuality = ((TTStatusReg & FDCAN_TTOST_QGTP) >> FDCAN_TTOST_QGTP_Pos);
+  TTOpStatus->ClockQuality = ((TTStatusReg & FDCAN_TTOST_QCS) >> FDCAN_TTOST_QCS_Pos);
+  TTOpStatus->RefTrigOffset = ((TTStatusReg & FDCAN_TTOST_RTO) >> FDCAN_TTOST_RTO_Pos);
+  TTOpStatus->GTimeDiscPending = ((TTStatusReg & FDCAN_TTOST_WGTD) >> FDCAN_TTOST_WGTD_Pos);
+  TTOpStatus->GapFinished = ((TTStatusReg & FDCAN_TTOST_GFI) >> FDCAN_TTOST_GFI_Pos);
+  TTOpStatus->MasterPriority = ((TTStatusReg & FDCAN_TTOST_TMP) >> FDCAN_TTOST_TMP_Pos);
+  TTOpStatus->GapStarted = ((TTStatusReg & FDCAN_TTOST_GSI) >> FDCAN_TTOST_GSI_Pos);
+  TTOpStatus->WaitForEvt = ((TTStatusReg & FDCAN_TTOST_WFE) >> FDCAN_TTOST_WFE_Pos);
+  TTOpStatus->AppWdgEvt = ((TTStatusReg & FDCAN_TTOST_AWE) >> FDCAN_TTOST_AWE_Pos);
+  TTOpStatus->ECSPending = ((TTStatusReg & FDCAN_TTOST_WECS) >> FDCAN_TTOST_WECS_Pos);
+  TTOpStatus->PhaseLock = ((TTStatusReg & FDCAN_TTOST_SPL) >> FDCAN_TTOST_SPL_Pos);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Exported_Functions_Group5 Interrupts management
+ *  @brief    Interrupts management
+ *
+@verbatim
+  ==============================================================================
+                       ##### Interrupts management #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) HAL_FDCAN_ConfigInterruptLines      : Assign interrupts to either Interrupt line 0 or 1
+      (+) HAL_FDCAN_TT_ConfigInterruptLines   : Assign TT interrupts to either Interrupt line 0 or 1
+      (+) HAL_FDCAN_ActivateNotification      : Enable interrupts
+      (+) HAL_FDCAN_DeactivateNotification    : Disable interrupts
+      (+) HAL_FDCAN_TT_ActivateNotification   : Enable TT interrupts
+      (+) HAL_FDCAN_TT_DeactivateNotification : Disable TT interrupts
+      (+) HAL_FDCAN_IRQHandler                : Handles FDCAN interrupt request
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Assign interrupts to either Interrupt line 0 or 1.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  ITList indicates which interrupts will be assigned to the selected interrupt line.
+  *         This parameter can be any combination of @arg FDCAN_Interrupts.
+  * @param  InterruptLine Interrupt line.
+  *         This parameter can be a value of @arg FDCAN_Interrupt_Line.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine)
+{
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_IT(ITList));
+  assert_param(IS_FDCAN_IT_LINE(InterruptLine));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Assign list of interrupts to the selected line */
+    if (InterruptLine == FDCAN_INTERRUPT_LINE0)
+    {
+      CLEAR_BIT(hfdcan->Instance->ILS, ITList);
+    }
+    else /* InterruptLine == FDCAN_INTERRUPT_LINE1 */
+    {
+      SET_BIT(hfdcan->Instance->ILS, ITList);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Assign TT interrupts to either Interrupt line 0 or 1.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TTITList indicates which interrupts will be assigned to the selected interrupt line.
+  *         This parameter can be any combination of @arg FDCAN_TTInterrupts.
+  * @param  InterruptLine Interrupt line.
+  *         This parameter can be a value of @arg FDCAN_Interrupt_Line.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t TTITList, uint32_t InterruptLine)
+{
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_IT(TTITList));
+  assert_param(IS_FDCAN_IT_LINE(InterruptLine));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Assign list of interrupts to the selected line */
+    if (InterruptLine == FDCAN_INTERRUPT_LINE0)
+    {
+      CLEAR_BIT(hfdcan->ttcan->TTILS, TTITList);
+    }
+    else /* InterruptLine == FDCAN_INTERRUPT_LINE1 */
+    {
+      SET_BIT(hfdcan->ttcan->TTILS, TTITList);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable interrupts.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  ActiveITs indicates which interrupts will be enabled.
+  *         This parameter can be any combination of @arg FDCAN_Interrupts.
+  * @param  BufferIndexes Tx Buffer Indexes.
+  *         This parameter can be any combination of @arg FDCAN_Tx_location.
+  *         This parameter is ignored if ActiveITs does not include one of the following:
+  *           - FDCAN_IT_TX_COMPLETE
+  *           - FDCAN_IT_TX_ABORT_COMPLETE
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes)
+{
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_IT(ActiveITs));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Enable Interrupt lines */
+    if ((ActiveITs & hfdcan->Instance->ILS) == 0U)
+    {
+      /* Enable Interrupt line 0 */
+      SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
+    }
+    else if ((ActiveITs & hfdcan->Instance->ILS) == ActiveITs)
+    {
+      /* Enable Interrupt line 1 */
+      SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
+    }
+    else
+    {
+      /* Enable Interrupt lines 0 and 1 */
+      hfdcan->Instance->ILE = (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1);
+    }
+
+    if ((ActiveITs & FDCAN_IT_TX_COMPLETE) != 0U)
+    {
+      /* Enable Tx Buffer Transmission Interrupt to set TC flag in IR register,
+         but interrupt will only occure if TC is enabled in IE register */
+      SET_BIT(hfdcan->Instance->TXBTIE, BufferIndexes);
+    }
+
+    if ((ActiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != 0U)
+    {
+      /* Enable Tx Buffer Cancellation Finished Interrupt to set TCF flag in IR register,
+         but interrupt will only occure if TCF is enabled in IE register */
+      SET_BIT(hfdcan->Instance->TXBCIE, BufferIndexes);
+    }
+
+    /* Enable the selected interrupts */
+    __HAL_FDCAN_ENABLE_IT(hfdcan, ActiveITs);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable interrupts.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  InactiveITs indicates which interrupts will be disabled.
+  *         This parameter can be any combination of @arg FDCAN_Interrupts.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs)
+{
+  uint32_t ITLineSelection;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_IT(InactiveITs));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Disable the selected interrupts */
+    __HAL_FDCAN_DISABLE_IT(hfdcan, InactiveITs);
+
+    if ((InactiveITs & FDCAN_IT_TX_COMPLETE) != 0U)
+    {
+      /* Disable Tx Buffer Transmission Interrupts */
+      CLEAR_REG(hfdcan->Instance->TXBTIE);
+    }
+
+    if ((InactiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != 0U)
+    {
+      /* Disable Tx Buffer Cancellation Finished Interrupt */
+      CLEAR_REG(hfdcan->Instance->TXBCIE);
+    }
+
+    ITLineSelection = hfdcan->Instance->ILS;
+
+    if ((hfdcan->Instance->IE | ITLineSelection) == ITLineSelection)
+    {
+      /* Disable Interrupt line 0 */
+      CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
+    }
+
+    if ((hfdcan->Instance->IE & ITLineSelection) == 0U)
+    {
+      /* Disable Interrupt line 1 */
+      CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable TT interrupts.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  ActiveTTITs indicates which TT interrupts will be enabled.
+  *         This parameter can be any combination of @arg FDCAN_TTInterrupts.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveTTITs)
+{
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_IT(ActiveTTITs));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Enable Interrupt lines */
+    if ((ActiveTTITs & hfdcan->ttcan->TTILS) == 0U)
+    {
+      /* Enable Interrupt line 0 */
+      SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
+    }
+    else if ((ActiveTTITs & hfdcan->ttcan->TTILS) == ActiveTTITs)
+    {
+      /* Enable Interrupt line 1 */
+      SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
+    }
+    else
+    {
+      /* Enable Interrupt lines 0 and 1 */
+      hfdcan->Instance->ILE = (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1);
+    }
+
+    /* Enable the selected TT interrupts */
+    __HAL_FDCAN_TT_ENABLE_IT(hfdcan, ActiveTTITs);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable TT interrupts.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  InactiveTTITs indicates which TT interrupts will be disabled.
+  *         This parameter can be any combination of @arg FDCAN_TTInterrupts.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveTTITs)
+{
+  uint32_t ITLineSelection;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_IT(InactiveTTITs));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Disable the selected TT interrupts */
+    __HAL_FDCAN_TT_DISABLE_IT(hfdcan, InactiveTTITs);
+
+    ITLineSelection = hfdcan->ttcan->TTILS;
+
+    if ((hfdcan->ttcan->TTIE | ITLineSelection) == ITLineSelection)
+    {
+      /* Disable Interrupt line 0 */
+      CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
+    }
+
+    if ((hfdcan->ttcan->TTIE & ITLineSelection) == 0U)
+    {
+      /* Disable Interrupt line 1 */
+      CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Handles FDCAN interrupt request.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t ClkCalibrationITs;
+  uint32_t TxEventFifoITs;
+  uint32_t RxFifo0ITs;
+  uint32_t RxFifo1ITs;
+  uint32_t Errors;
+  uint32_t ErrorStatusITs;
+  uint32_t TransmittedBuffers;
+  uint32_t AbortedBuffers;
+  uint32_t TTSchedSyncITs;
+  uint32_t TTTimeMarkITs;
+  uint32_t TTGlobTimeITs;
+  uint32_t TTDistErrors;
+  uint32_t TTFatalErrors;
+  uint32_t SWTime;
+  uint32_t SWCycleCount;
+
+  ClkCalibrationITs = (FDCAN_CCU->IR << 30);
+  ClkCalibrationITs &= (FDCAN_CCU->IE << 30);
+  TxEventFifoITs = hfdcan->Instance->IR & FDCAN_TX_EVENT_FIFO_MASK;
+  TxEventFifoITs &= hfdcan->Instance->IE;
+  RxFifo0ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO0_MASK;
+  RxFifo0ITs &= hfdcan->Instance->IE;
+  RxFifo1ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO1_MASK;
+  RxFifo1ITs &= hfdcan->Instance->IE;
+  Errors = hfdcan->Instance->IR & FDCAN_ERROR_MASK;
+  Errors &= hfdcan->Instance->IE;
+  ErrorStatusITs = hfdcan->Instance->IR & FDCAN_ERROR_STATUS_MASK;
+  ErrorStatusITs &= hfdcan->Instance->IE;
+
+  /* High Priority Message interrupt management *******************************/
+  if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RX_HIGH_PRIORITY_MSG) != 0U)
+  {
+    if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG) != 0U)
+    {
+      /* Clear the High Priority Message flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->HighPriorityMessageCallback(hfdcan);
+#else
+      /* High Priority Message Callback */
+      HAL_FDCAN_HighPriorityMessageCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Transmission Abort interrupt management **********************************/
+  if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_ABORT_COMPLETE) != 0U)
+  {
+    if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE) != 0U)
+    {
+      /* List of aborted monitored buffers */
+      AbortedBuffers = hfdcan->Instance->TXBCF;
+      AbortedBuffers &= hfdcan->Instance->TXBCIE;
+
+      /* Clear the Transmission Cancellation flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->TxBufferAbortCallback(hfdcan, AbortedBuffers);
+#else
+      /* Transmission Cancellation Callback */
+      HAL_FDCAN_TxBufferAbortCallback(hfdcan, AbortedBuffers);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Clock calibration unit interrupts management *****************************/
+  if (ClkCalibrationITs != 0U)
+  {
+    /* Clear the Clock Calibration flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, ClkCalibrationITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->ClockCalibrationCallback(hfdcan, ClkCalibrationITs);
+#else
+    /* Clock Calibration Callback */
+    HAL_FDCAN_ClockCalibrationCallback(hfdcan, ClkCalibrationITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+
+  /* Tx event FIFO interrupts management **************************************/
+  if (TxEventFifoITs != 0U)
+  {
+    /* Clear the Tx Event FIFO flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, TxEventFifoITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->TxEventFifoCallback(hfdcan, TxEventFifoITs);
+#else
+    /* Tx Event FIFO Callback */
+    HAL_FDCAN_TxEventFifoCallback(hfdcan, TxEventFifoITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+
+  /* Rx FIFO 0 interrupts management ******************************************/
+  if (RxFifo0ITs != 0U)
+  {
+    /* Clear the Rx FIFO 0 flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo0ITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->RxFifo0Callback(hfdcan, RxFifo0ITs);
+#else
+    /* Rx FIFO 0 Callback */
+    HAL_FDCAN_RxFifo0Callback(hfdcan, RxFifo0ITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+
+  /* Rx FIFO 1 interrupts management ******************************************/
+  if (RxFifo1ITs != 0U)
+  {
+    /* Clear the Rx FIFO 1 flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo1ITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->RxFifo1Callback(hfdcan, RxFifo1ITs);
+#else
+    /* Rx FIFO 1 Callback */
+    HAL_FDCAN_RxFifo1Callback(hfdcan, RxFifo1ITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+
+  /* Tx FIFO empty interrupt management ***************************************/
+  if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_FIFO_EMPTY) != 0U)
+  {
+    if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY) != 0U)
+    {
+      /* Clear the Tx FIFO empty flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->TxFifoEmptyCallback(hfdcan);
+#else
+      /* Tx FIFO empty Callback */
+      HAL_FDCAN_TxFifoEmptyCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Transmission Complete interrupt management *******************************/
+  if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_COMPLETE) != 0U)
+  {
+    if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_COMPLETE) != 0U)
+    {
+      /* List of transmitted monitored buffers */
+      TransmittedBuffers = hfdcan->Instance->TXBTO;
+      TransmittedBuffers &= hfdcan->Instance->TXBTIE;
+
+      /* Clear the Transmission Complete flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_COMPLETE);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->TxBufferCompleteCallback(hfdcan, TransmittedBuffers);
+#else
+      /* Transmission Complete Callback */
+      HAL_FDCAN_TxBufferCompleteCallback(hfdcan, TransmittedBuffers);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Rx Buffer New Message interrupt management *******************************/
+  if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RX_BUFFER_NEW_MESSAGE) != 0U)
+  {
+    if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE) != 0U)
+    {
+      /* Clear the Rx Buffer New Message flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->RxBufferNewMessageCallback(hfdcan);
+#else
+      /* Rx Buffer New Message Callback */
+      HAL_FDCAN_RxBufferNewMessageCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Timestamp Wraparound interrupt management ********************************/
+  if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TIMESTAMP_WRAPAROUND) != 0U)
+  {
+    if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND) != 0U)
+    {
+      /* Clear the Timestamp Wraparound flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->TimestampWraparoundCallback(hfdcan);
+#else
+      /* Timestamp Wraparound Callback */
+      HAL_FDCAN_TimestampWraparoundCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Timeout Occurred interrupt management ************************************/
+  if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TIMEOUT_OCCURRED) != 0U)
+  {
+    if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED) != 0U)
+    {
+      /* Clear the Timeout Occurred flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->TimeoutOccurredCallback(hfdcan);
+#else
+      /* Timeout Occurred Callback */
+      HAL_FDCAN_TimeoutOccurredCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Message RAM access failure interrupt management **************************/
+  if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RAM_ACCESS_FAILURE) != 0U)
+  {
+    if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE) != 0U)
+    {
+      /* Clear the Message RAM access failure flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE);
+
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_RAM_ACCESS;
+    }
+  }
+
+  /* Error Status interrupts management ***************************************/
+  if (ErrorStatusITs != 0U)
+  {
+    /* Clear the Error flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, ErrorStatusITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->ErrorStatusCallback(hfdcan, ErrorStatusITs);
+#else
+    /* Error Status Callback */
+    HAL_FDCAN_ErrorStatusCallback(hfdcan, ErrorStatusITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+
+  /* Error interrupts management **********************************************/
+  if (Errors != 0U)
+  {
+    /* Clear the Error flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, Errors);
+
+    /* Update error code */
+    hfdcan->ErrorCode |= Errors;
+  }
+
+  if (hfdcan->Instance == FDCAN1)
+  {
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != 0U)
+    {
+      TTSchedSyncITs = hfdcan->ttcan->TTIR & FDCAN_TT_SCHEDULE_SYNC_MASK;
+      TTSchedSyncITs &= hfdcan->ttcan->TTIE;
+      TTTimeMarkITs = hfdcan->ttcan->TTIR & FDCAN_TT_TIME_MARK_MASK;
+      TTTimeMarkITs &= hfdcan->ttcan->TTIE;
+      TTGlobTimeITs = hfdcan->ttcan->TTIR & FDCAN_TT_GLOBAL_TIME_MASK;
+      TTGlobTimeITs &= hfdcan->ttcan->TTIE;
+      TTDistErrors = hfdcan->ttcan->TTIR & FDCAN_TT_DISTURBING_ERROR_MASK;
+      TTDistErrors &= hfdcan->ttcan->TTIE;
+      TTFatalErrors = hfdcan->ttcan->TTIR & FDCAN_TT_FATAL_ERROR_MASK;
+      TTFatalErrors &= hfdcan->ttcan->TTIE;
+
+      /* TT Schedule Synchronization interrupts management **********************/
+      if (TTSchedSyncITs != 0U)
+      {
+        /* Clear the TT Schedule Synchronization flags */
+        __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTSchedSyncITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+        /* Call registered callback*/
+        hfdcan->TT_ScheduleSyncCallback(hfdcan, TTSchedSyncITs);
+#else
+        /* TT Schedule Synchronization Callback */
+        HAL_FDCAN_TT_ScheduleSyncCallback(hfdcan, TTSchedSyncITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+      }
+
+      /* TT Time Mark interrupts management *************************************/
+      if (TTTimeMarkITs != 0U)
+      {
+        /* Clear the TT Time Mark flags */
+        __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTTimeMarkITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+        /* Call registered callback*/
+        hfdcan->TT_TimeMarkCallback(hfdcan, TTTimeMarkITs);
+#else
+        /* TT Time Mark Callback */
+        HAL_FDCAN_TT_TimeMarkCallback(hfdcan, TTTimeMarkITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+      }
+
+      /* TT Stop Watch interrupt management *************************************/
+      if (__HAL_FDCAN_TT_GET_IT_SOURCE(hfdcan, FDCAN_TT_IT_STOP_WATCH) != 0U)
+      {
+        if (__HAL_FDCAN_TT_GET_FLAG(hfdcan, FDCAN_TT_FLAG_STOP_WATCH) != 0U)
+        {
+          /* Retrieve Stop watch Time and Cycle count */
+          SWTime = ((hfdcan->ttcan->TTCPT & FDCAN_TTCPT_SWV) >> FDCAN_TTCPT_SWV_Pos);
+          SWCycleCount = ((hfdcan->ttcan->TTCPT & FDCAN_TTCPT_CCV) >> FDCAN_TTCPT_CCV_Pos);
+
+          /* Clear the TT Stop Watch flag */
+          __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, FDCAN_TT_FLAG_STOP_WATCH);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+          /* Call registered callback*/
+          hfdcan->TT_StopWatchCallback(hfdcan, SWTime, SWCycleCount);
+#else
+          /* TT Stop Watch Callback */
+          HAL_FDCAN_TT_StopWatchCallback(hfdcan, SWTime, SWCycleCount);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+        }
+      }
+
+      /* TT Global Time interrupts management ***********************************/
+      if (TTGlobTimeITs != 0U)
+      {
+        /* Clear the TT Global Time flags */
+        __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTGlobTimeITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+        /* Call registered callback*/
+        hfdcan->TT_GlobalTimeCallback(hfdcan, TTGlobTimeITs);
+#else
+        /* TT Global Time Callback */
+        HAL_FDCAN_TT_GlobalTimeCallback(hfdcan, TTGlobTimeITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+      }
+
+      /* TT Disturbing Error interrupts management ******************************/
+      if (TTDistErrors != 0U)
+      {
+        /* Clear the TT Disturbing Error flags */
+        __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTDistErrors);
+
+        /* Update error code */
+        hfdcan->ErrorCode |= TTDistErrors;
+      }
+
+      /* TT Fatal Error interrupts management ***********************************/
+      if (TTFatalErrors != 0U)
+      {
+        /* Clear the TT Fatal Error flags */
+        __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTFatalErrors);
+
+        /* Update error code */
+        hfdcan->ErrorCode |= TTFatalErrors;
+      }
+    }
+  }
+
+  if (hfdcan->ErrorCode != HAL_FDCAN_ERROR_NONE)
+  {
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->ErrorCallback(hfdcan);
+#else
+    /* Error Callback */
+    HAL_FDCAN_ErrorCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Exported_Functions_Group6 Callback functions
+ *  @brief   FDCAN Callback functions
+ *
+@verbatim
+  ==============================================================================
+                          ##### Callback functions #####
+  ==============================================================================
+    [..]
+    This subsection provides the following callback functions:
+      (+) HAL_FDCAN_ClockCalibrationCallback
+      (+) HAL_FDCAN_TxEventFifoCallback
+      (+) HAL_FDCAN_RxFifo0Callback
+      (+) HAL_FDCAN_RxFifo1Callback
+      (+) HAL_FDCAN_TxFifoEmptyCallback
+      (+) HAL_FDCAN_TxBufferCompleteCallback
+      (+) HAL_FDCAN_TxBufferAbortCallback
+      (+) HAL_FDCAN_RxBufferNewMessageCallback
+      (+) HAL_FDCAN_HighPriorityMessageCallback
+      (+) HAL_FDCAN_TimestampWraparoundCallback
+      (+) HAL_FDCAN_TimeoutOccurredCallback
+      (+) HAL_FDCAN_ErrorCallback
+      (+) HAL_FDCAN_ErrorStatusCallback
+      (+) HAL_FDCAN_TT_ScheduleSyncCallback
+      (+) HAL_FDCAN_TT_TimeMarkCallback
+      (+) HAL_FDCAN_TT_StopWatchCallback
+      (+) HAL_FDCAN_TT_GlobalTimeCallback
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Clock Calibration callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  ClkCalibrationITs indicates which Clock Calibration interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_Clock_Calibration_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_ClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(ClkCalibrationITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_ClockCalibrationCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Tx Event callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TxEventFifoITs indicates which Tx Event FIFO interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_Tx_Event_Fifo_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(TxEventFifoITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TxEventFifoCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Rx FIFO 0 callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  RxFifo0ITs indicates which Rx FIFO 0 interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_Rx_Fifo0_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(RxFifo0ITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_RxFifo0Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Rx FIFO 1 callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  RxFifo1ITs indicates which Rx FIFO 1 interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_Rx_Fifo1_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(RxFifo1ITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_RxFifo1Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Tx FIFO Empty callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TxFifoEmptyCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Transmission Complete callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  BufferIndexes Indexes of the transmitted buffers.
+  *         This parameter can be any combination of @arg FDCAN_Tx_location.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(BufferIndexes);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TxBufferCompleteCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Transmission Cancellation callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  BufferIndexes Indexes of the aborted buffers.
+  *         This parameter can be any combination of @arg FDCAN_Tx_location.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(BufferIndexes);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TxBufferAbortCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Rx Buffer New Message callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_RxBufferNewMessageCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_RxBufferNewMessageCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Timestamp Wraparound callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TimestampWraparoundCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Timeout Occurred callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TimeoutOccurredCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  High Priority Message callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_HighPriorityMessageCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Error callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Error status callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  ErrorStatusITs indicates which Error Status interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_Error_Status_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(ErrorStatusITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_ErrorStatusCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  TT Schedule Synchronization callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TTSchedSyncITs indicates which TT Schedule Synchronization interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_TTScheduleSynchronization_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TT_ScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(TTSchedSyncITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TT_ScheduleSyncCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  TT Time Mark callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TTTimeMarkITs indicates which TT Schedule Synchronization interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_TTTimeMark_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TT_TimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(TTTimeMarkITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TT_TimeMarkCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  TT Stop Watch callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  SWTime Time Value captured at the Stop Watch Trigger pin (fdcan1_swt) falling/rising
+  *         edge (as configured via HAL_FDCAN_TTConfigStopWatch).
+  *         This parameter is a number between 0 and 0xFFFF.
+  * @param  SWCycleCount Cycle count value captured together with SWTime.
+  *         This parameter is a number between 0 and 0x3F.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TT_StopWatchCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(SWTime);
+  UNUSED(SWCycleCount);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TT_StopWatchCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  TT Global Time callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TTGlobTimeITs indicates which TT Global Time interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_TTGlobalTime_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TT_GlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(TTGlobTimeITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TT_GlobalTimeCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Exported_Functions_Group7 Peripheral State functions
+ *  @brief   FDCAN Peripheral State functions
+ *
+@verbatim
+  ==============================================================================
+                      ##### Peripheral State functions #####
+  ==============================================================================
+    [..]
+    This subsection provides functions allowing to :
+      (+) HAL_FDCAN_GetState()  : Return the FDCAN state.
+      (+) HAL_FDCAN_GetError()  : Return the FDCAN error code if any.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Return the FDCAN state
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL state
+  */
+HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Return FDCAN state */
+  return hfdcan->State;
+}
+
+/**
+  * @brief  Return the FDCAN error code
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval FDCAN Error Code
+  */
+uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Return FDCAN error code */
+  return hfdcan->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup FDCAN_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Calculate each RAM block start address and size
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+ */
+static HAL_StatusTypeDef FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t RAMcounter;
+  uint32_t StartAddress;
+
+  StartAddress = hfdcan->Init.MessageRAMOffset;
+
+  /* Standard filter list start address */
+  MODIFY_REG(hfdcan->Instance->SIDFC, FDCAN_SIDFC_FLSSA, (StartAddress << FDCAN_SIDFC_FLSSA_Pos));
+
+  /* Standard filter elements number */
+  MODIFY_REG(hfdcan->Instance->SIDFC, FDCAN_SIDFC_LSS, (hfdcan->Init.StdFiltersNbr << FDCAN_SIDFC_LSS_Pos));
+
+  /* Extended filter list start address */
+  StartAddress += hfdcan->Init.StdFiltersNbr;
+  MODIFY_REG(hfdcan->Instance->XIDFC, FDCAN_XIDFC_FLESA, (StartAddress << FDCAN_XIDFC_FLESA_Pos));
+
+  /* Extended filter elements number */
+  MODIFY_REG(hfdcan->Instance->XIDFC, FDCAN_XIDFC_LSE, (hfdcan->Init.ExtFiltersNbr << FDCAN_XIDFC_LSE_Pos));
+
+  /* Rx FIFO 0 start address */
+  StartAddress += (hfdcan->Init.ExtFiltersNbr * 2U);
+  MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0SA, (StartAddress << FDCAN_RXF0C_F0SA_Pos));
+
+  /* Rx FIFO 0 elements number */
+  MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0S, (hfdcan->Init.RxFifo0ElmtsNbr << FDCAN_RXF0C_F0S_Pos));
+
+  /* Rx FIFO 1 start address */
+  StartAddress += (hfdcan->Init.RxFifo0ElmtsNbr * hfdcan->Init.RxFifo0ElmtSize);
+  MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1SA, (StartAddress << FDCAN_RXF1C_F1SA_Pos));
+
+  /* Rx FIFO 1 elements number */
+  MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1S, (hfdcan->Init.RxFifo1ElmtsNbr << FDCAN_RXF1C_F1S_Pos));
+
+  /* Rx buffer list start address */
+  StartAddress += (hfdcan->Init.RxFifo1ElmtsNbr * hfdcan->Init.RxFifo1ElmtSize);
+  MODIFY_REG(hfdcan->Instance->RXBC, FDCAN_RXBC_RBSA, (StartAddress << FDCAN_RXBC_RBSA_Pos));
+
+  /* Tx event FIFO start address */
+  StartAddress += (hfdcan->Init.RxBuffersNbr * hfdcan->Init.RxBufferSize);
+  MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFSA, (StartAddress << FDCAN_TXEFC_EFSA_Pos));
+
+  /* Tx event FIFO elements number */
+  MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFS, (hfdcan->Init.TxEventsNbr << FDCAN_TXEFC_EFS_Pos));
+
+  /* Tx buffer list start address */
+  StartAddress += (hfdcan->Init.TxEventsNbr * 2U);
+  MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_TBSA, (StartAddress << FDCAN_TXBC_TBSA_Pos));
+
+  /* Dedicated Tx buffers number */
+  MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_NDTB, (hfdcan->Init.TxBuffersNbr << FDCAN_TXBC_NDTB_Pos));
+
+  /* Tx FIFO/queue elements number */
+  MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_TFQS, (hfdcan->Init.TxFifoQueueElmtsNbr << FDCAN_TXBC_TFQS_Pos));
+
+  hfdcan->msgRam.StandardFilterSA = SRAMCAN_BASE + (hfdcan->Init.MessageRAMOffset * 4U);
+  hfdcan->msgRam.ExtendedFilterSA = hfdcan->msgRam.StandardFilterSA + (hfdcan->Init.StdFiltersNbr * 4U);
+  hfdcan->msgRam.RxFIFO0SA = hfdcan->msgRam.ExtendedFilterSA + (hfdcan->Init.ExtFiltersNbr * 2U * 4U);
+  hfdcan->msgRam.RxFIFO1SA = hfdcan->msgRam.RxFIFO0SA + (hfdcan->Init.RxFifo0ElmtsNbr * hfdcan->Init.RxFifo0ElmtSize * 4U);
+  hfdcan->msgRam.RxBufferSA = hfdcan->msgRam.RxFIFO1SA + (hfdcan->Init.RxFifo1ElmtsNbr * hfdcan->Init.RxFifo1ElmtSize * 4U);
+  hfdcan->msgRam.TxEventFIFOSA = hfdcan->msgRam.RxBufferSA + (hfdcan->Init.RxBuffersNbr * hfdcan->Init.RxBufferSize * 4U);
+  hfdcan->msgRam.TxBufferSA = hfdcan->msgRam.TxEventFIFOSA + (hfdcan->Init.TxEventsNbr * 2U * 4U);
+  hfdcan->msgRam.TxFIFOQSA = hfdcan->msgRam.TxBufferSA + (hfdcan->Init.TxBuffersNbr * hfdcan->Init.TxElmtSize * 4U);
+
+  hfdcan->msgRam.EndAddress = hfdcan->msgRam.TxFIFOQSA + (hfdcan->Init.TxFifoQueueElmtsNbr * hfdcan->Init.TxElmtSize * 4U);
+
+  if (hfdcan->msgRam.EndAddress > FDCAN_MESSAGE_RAM_END_ADDRESS) /* Last address of the Message RAM */
+  {
+    /* Update error code.
+       Message RAM overflow */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+    /* Change FDCAN state */
+    hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Flush the allocated Message RAM area */
+    for (RAMcounter = hfdcan->msgRam.StandardFilterSA; RAMcounter < hfdcan->msgRam.EndAddress; RAMcounter += 4U)
+    {
+      *(uint32_t *)(RAMcounter) = 0x00000000;
+    }
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Copy Tx message to the message RAM.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure.
+  * @param  pTxData pointer to a buffer containing the payload of the Tx frame.
+  * @param  BufferIndex index of the buffer to be configured.
+  * @retval HAL status
+ */
+static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex)
+{
+  uint32_t TxElementW1;
+  uint32_t TxElementW2;
+  uint32_t *TxAddress;
+  uint32_t ByteCounter;
+
+  /* Build first word of Tx header element */
+  if (pTxHeader->IdType == FDCAN_STANDARD_ID)
+  {
+    TxElementW1 = (pTxHeader->ErrorStateIndicator |
+                   FDCAN_STANDARD_ID |
+                   pTxHeader->TxFrameType |
+                   (pTxHeader->Identifier << 18));
+  }
+  else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
+  {
+    TxElementW1 = (pTxHeader->ErrorStateIndicator |
+                   FDCAN_EXTENDED_ID |
+                   pTxHeader->TxFrameType |
+                   pTxHeader->Identifier);
+  }
+
+  /* Build second word of Tx header element */
+  TxElementW2 = ((pTxHeader->MessageMarker << 24) |
+                 pTxHeader->TxEventFifoControl |
+                 pTxHeader->FDFormat |
+                 pTxHeader->BitRateSwitch |
+                 pTxHeader->DataLength);
+
+  /* Calculate Tx element address */
+  TxAddress = (uint32_t *)(hfdcan->msgRam.TxBufferSA + (BufferIndex * hfdcan->Init.TxElmtSize * 4U));
+
+  /* Write Tx element header to the message RAM */
+  *TxAddress = TxElementW1;
+  TxAddress++;
+  *TxAddress = TxElementW2;
+  TxAddress++;
+
+  /* Write Tx payload to the message RAM */
+  for (ByteCounter = 0; ByteCounter < DLCtoBytes[pTxHeader->DataLength >> 16]; ByteCounter += 4U)
+  {
+    *TxAddress = (((uint32_t)pTxData[ByteCounter + 3U] << 24) |
+                  ((uint32_t)pTxData[ByteCounter + 2U] << 16) |
+                  ((uint32_t)pTxData[ByteCounter + 1U] << 8) |
+                  (uint32_t)pTxData[ByteCounter]);
+    TxAddress++;
+  }
+}
+
+/**
+  * @}
+  */
+#endif /* HAL_FDCAN_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c
new file mode 100644
index 00000000..3a6b651f
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c
@@ -0,0 +1,1099 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_flash.c
+  * @author  MCD Application Team
+  * @brief   FLASH HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the internal FLASH memory:
+  *           + Program operations functions
+  *           + Memory Control functions
+  *           + Peripheral Errors functions
+  *
+ @verbatim
+  ==============================================================================
+                        ##### FLASH peripheral features #####
+  ==============================================================================
+
+  [..] The Flash memory interface manages CPU AXI I-Code and D-Code accesses
+       to the Flash memory. It implements the erase and program Flash memory operations
+       and the read and write protection mechanisms.
+
+  [..] The FLASH main features are:
+      (+) Flash memory read operations
+      (+) Flash memory program/erase operations
+      (+) Read / write protections
+      (+) Option bytes programming
+      (+) Error code correction (ECC) : Data in flash are 266-bits word
+          (10 bits added per flash word)
+
+                        ##### How to use this driver #####
+ ==============================================================================
+    [..]
+      This driver provides functions and macros to configure and program the FLASH
+      memory of all STM32H7xx devices.
+
+      (#) FLASH Memory IO Programming functions:
+           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
+                HAL_FLASH_Lock() functions
+           (++) Program functions: 256-bit word only
+           (++) There Two modes of programming :
+            (+++) Polling mode using HAL_FLASH_Program() function
+            (+++) Interrupt mode using HAL_FLASH_Program_IT() function
+
+      (#) Interrupts and flags management functions :
+           (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
+           (++) Callback functions are called when the flash operations are finished :
+                HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise
+                HAL_FLASH_OperationErrorCallback()
+           (++) Get error flag status by calling HAL_FLASH_GetError()
+
+      (#) Option bytes management functions :
+           (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and
+                HAL_FLASH_OB_Lock() functions
+           (++) Launch the reload of the option bytes using HAL_FLASH_OB_Launch() function.
+                In this case, a reset is generated
+    [..]
+      In addition to these functions, this driver includes a set of macros allowing
+      to handle the following operations:
+       (+) Set the latency
+       (+) Enable/Disable the FLASH interrupts
+       (+) Monitor the FLASH flags status
+     [..]
+    (@) For any Flash memory program operation (erase or program), the CPU clock frequency
+        (HCLK) must be at least 1MHz.
+    (@) The contents of the Flash memory are not guaranteed if a device reset occurs during
+        a Flash memory operation.
+    (@) The application can simultaneously request a read and a write operation through each AXI
+        interface.
+        As the Flash memory is divided into two independent banks, the embedded Flash
+        memory interface can drive different operations at the same time on each bank. For
+        example a read, write or erase operation can be executed on bank 1 while another read,
+        write or erase operation is executed on bank 2.
+
+ @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup FLASH FLASH
+  * @brief FLASH HAL module driver
+  * @{
+  */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup FLASH_Private_Constants
+  * @{
+  */
+#define FLASH_TIMEOUT_VALUE              50000U /* 50 s */
+
+/**
+  * @}
+  */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+FLASH_ProcessTypeDef pFlash;
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup FLASH_Exported_Functions FLASH Exported functions
+  * @{
+  */
+
+/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
+ *  @brief   Programming operation functions
+ *
+@verbatim
+ ===============================================================================
+                  ##### Programming operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the FLASH
+    program operations.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Program flash word at a specified address
+  * @param  TypeProgram Indicate the way to program at a specified address.
+  *         This parameter can be a value of @ref FLASH_Type_Program
+  * @param  FlashAddress specifies the address to be programmed.
+  * @param  DataAddress specifies the address of data to be programmed
+  *
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress)
+{
+  HAL_StatusTypeDef status;
+  __IO uint32_t *dest_addr = (__IO uint32_t *)FlashAddress;
+  __IO uint32_t *src_addr = (__IO uint32_t*)DataAddress;
+  uint32_t bank;
+  uint8_t row_index = FLASH_NB_32BITWORD_IN_FLASHWORD;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+  assert_param(IS_FLASH_PROGRAM_ADDRESS(FlashAddress));
+
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+#if defined (FLASH_OPTCR_PG_OTP)
+  if((IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress)) || (IS_FLASH_PROGRAM_ADDRESS_OTP(FlashAddress)))
+#else
+  if(IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress))
+#endif /* FLASH_OPTCR_PG_OTP */
+  {
+    bank = FLASH_BANK_1;
+  }
+  else
+  {
+    bank = FLASH_BANK_2;
+  }
+
+  /* Reset error code */
+  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, bank);
+
+  if(status == HAL_OK)
+  {
+    if(bank == FLASH_BANK_1)
+    {
+#if defined (FLASH_OPTCR_PG_OTP)
+      if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD)
+      {
+        /* Set OTP_PG bit */
+        SET_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP);
+      }
+      else
+#endif /* FLASH_OPTCR_PG_OTP */
+      {
+        /* Set PG bit */
+        SET_BIT(FLASH->CR1, FLASH_CR_PG);
+      }
+    }
+    else
+    {
+      /* Set PG bit */
+      SET_BIT(FLASH->CR2, FLASH_CR_PG);
+    }
+
+    __ISB();
+    __DSB();
+
+#if defined (FLASH_OPTCR_PG_OTP)
+    if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD)
+    {
+      /* Program an OTP word (16 bits) */
+      *(__IO uint16_t *)FlashAddress = *(__IO uint16_t*)DataAddress;
+    }
+    else
+#endif /* FLASH_OPTCR_PG_OTP */
+    {
+      /* Program the flash word */
+      do
+      {
+        *dest_addr = *src_addr;
+        dest_addr++;
+        src_addr++;
+        row_index--;
+     } while (row_index != 0U);
+    }
+
+    __ISB();
+    __DSB();
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, bank);
+
+#if defined (FLASH_OPTCR_PG_OTP)
+    if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD)
+    {
+      /* If the program operation is completed, disable the OTP_PG */
+      CLEAR_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP);
+    }
+    else
+#endif /* FLASH_OPTCR_PG_OTP */
+    {
+      if(bank == FLASH_BANK_1)
+      {
+        /* If the program operation is completed, disable the PG */
+        CLEAR_BIT(FLASH->CR1, FLASH_CR_PG);
+      }
+      else
+      {
+        /* If the program operation is completed, disable the PG */
+        CLEAR_BIT(FLASH->CR2, FLASH_CR_PG);
+      }
+    }
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(&pFlash);
+
+  return status;
+}
+
+/**
+  * @brief  Program flash words of 256 bits at a specified address with interrupt enabled.
+  * @param  TypeProgram Indicate the way to program at a specified address.
+  *                      This parameter can be a value of @ref FLASH_Type_Program
+  * @param  FlashAddress specifies the address to be programmed.
+  * @param  DataAddress specifies the address of data (256 bits) to be programmed
+  *
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress)
+{
+  HAL_StatusTypeDef status;
+  __IO uint32_t *dest_addr = (__IO uint32_t*)FlashAddress;
+  __IO uint32_t *src_addr = (__IO uint32_t*)DataAddress;
+  uint32_t bank;
+  uint8_t row_index = FLASH_NB_32BITWORD_IN_FLASHWORD;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+  assert_param(IS_FLASH_PROGRAM_ADDRESS(FlashAddress));
+
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Reset error code */
+  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+#if defined (FLASH_OPTCR_PG_OTP)
+  if((IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress)) || (IS_FLASH_PROGRAM_ADDRESS_OTP(FlashAddress)))
+#else
+  if(IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress))
+#endif /* FLASH_OPTCR_PG_OTP */
+  {
+    bank = FLASH_BANK_1;
+  }
+  else
+  {
+    bank = FLASH_BANK_2;
+  }
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, bank);
+
+  if (status != HAL_OK)
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(&pFlash);
+  }
+  else
+  {
+    pFlash.Address = FlashAddress;
+
+    if(bank == FLASH_BANK_1)
+    {
+      /* Set internal variables used by the IRQ handler */
+      pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_BANK1;
+
+#if defined (FLASH_OPTCR_PG_OTP)
+      if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD)
+      {
+        /* Set OTP_PG bit */
+        SET_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP);
+      }
+      else
+#endif /* FLASH_OPTCR_PG_OTP */
+      {
+        /* Set PG bit */
+        SET_BIT(FLASH->CR1, FLASH_CR_PG);
+      }
+
+      /* Enable End of Operation and Error interrupts for Bank 1 */
+#if defined (FLASH_CR_OPERRIE)
+      __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1     | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
+                                  FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1);
+#else
+      __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1     | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
+                                  FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1);
+#endif /* FLASH_CR_OPERRIE */
+    }
+    else
+    {
+      /* Set internal variables used by the IRQ handler */
+      pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_BANK2;
+
+      /* Set PG bit */
+      SET_BIT(FLASH->CR2, FLASH_CR_PG);
+
+      /* Enable End of Operation and Error interrupts for Bank2 */
+#if defined (FLASH_CR_OPERRIE)
+      __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2     | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
+                                  FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2);
+#else
+      __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2     | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
+                                  FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2);
+#endif /* FLASH_CR_OPERRIE */
+    }
+
+    __ISB();
+    __DSB();
+
+#if defined (FLASH_OPTCR_PG_OTP)
+    if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD)
+    {
+      /* Program an OTP word (16 bits) */
+      *(__IO uint16_t *)FlashAddress = *(__IO uint16_t*)DataAddress;
+    }
+    else
+#endif /* FLASH_OPTCR_PG_OTP */
+    {
+      /* Program the flash word */
+      do
+      {
+        *dest_addr = *src_addr;
+        dest_addr++;
+        src_addr++;
+        row_index--;
+      } while (row_index != 0U);
+    }
+
+    __ISB();
+    __DSB();
+  }
+
+  return status;
+}
+
+/**
+  * @brief This function handles FLASH interrupt request.
+  * @retval None
+  */
+void HAL_FLASH_IRQHandler(void)
+{
+  uint32_t temp;
+  uint32_t errorflag;
+  FLASH_ProcedureTypeDef procedure;
+
+  /* Check FLASH Bank1 End of Operation flag  */
+  if(__HAL_FLASH_GET_FLAG_BANK1(FLASH_SR_EOP) != RESET)
+  {
+    if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE_BANK1)
+    {
+      /* Nb of sector to erased can be decreased */
+      pFlash.NbSectorsToErase--;
+
+      /* Check if there are still sectors to erase */
+      if(pFlash.NbSectorsToErase != 0U)
+      {
+        /* Indicate user which sector has been erased */
+        HAL_FLASH_EndOfOperationCallback(pFlash.Sector);
+
+        /* Clear bank 1 End of Operation pending bit */
+        __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1);
+
+        /* Increment sector number */
+        pFlash.Sector++;
+        temp = pFlash.Sector;
+        FLASH_Erase_Sector(temp, FLASH_BANK_1, pFlash.VoltageForErase);
+      }
+      else
+      {
+        /* No more sectors to Erase, user callback can be called */
+        /* Reset Sector and stop Erase sectors procedure */
+        pFlash.Sector = 0xFFFFFFFFU;
+        pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+
+        /* FLASH EOP interrupt user callback */
+        HAL_FLASH_EndOfOperationCallback(pFlash.Sector);
+
+        /* Clear FLASH End of Operation pending bit */
+        __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1);
+      }
+    }
+    else
+    {
+      procedure = pFlash.ProcedureOnGoing;
+
+      if((procedure == FLASH_PROC_MASSERASE_BANK1) || (procedure == FLASH_PROC_ALLBANK_MASSERASE))
+      {
+        /* MassErase ended. Return the selected bank */
+        /* FLASH EOP interrupt user callback */
+        HAL_FLASH_EndOfOperationCallback(FLASH_BANK_1);
+      }
+      else if(procedure == FLASH_PROC_PROGRAM_BANK1)
+      {
+        /* Program ended. Return the selected address */
+        /* FLASH EOP interrupt user callback */
+        HAL_FLASH_EndOfOperationCallback(pFlash.Address);
+      }
+      else
+      {
+        /* Nothing to do */
+      }
+
+      if((procedure != FLASH_PROC_SECTERASE_BANK2) && \
+         (procedure != FLASH_PROC_MASSERASE_BANK2) && \
+         (procedure != FLASH_PROC_PROGRAM_BANK2))
+      {
+        pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+        /* Clear FLASH End of Operation pending bit */
+        __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1);
+      }
+    }
+  }
+
+  /* Check FLASH Bank2 End of Operation flag  */
+  if(__HAL_FLASH_GET_FLAG_BANK2(FLASH_SR_EOP) != RESET)
+  {
+    if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE_BANK2)
+    {
+      /*Nb of sector to erased can be decreased*/
+      pFlash.NbSectorsToErase--;
+
+      /* Check if there are still sectors to erase*/
+      if(pFlash.NbSectorsToErase != 0U)
+      {
+        /*Indicate user which sector has been erased*/
+        HAL_FLASH_EndOfOperationCallback(pFlash.Sector);
+
+        /* Clear bank 2 End of Operation pending bit */
+        __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2);
+
+        /*Increment sector number*/
+        pFlash.Sector++;
+        temp = pFlash.Sector;
+        FLASH_Erase_Sector(temp, FLASH_BANK_2, pFlash.VoltageForErase);
+      }
+      else
+      {
+        /* No more sectors to Erase, user callback can be called */
+        /* Reset Sector and stop Erase sectors procedure */
+        pFlash.Sector = 0xFFFFFFFFU;
+        pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+
+        /* FLASH EOP interrupt user callback */
+        HAL_FLASH_EndOfOperationCallback(pFlash.Sector);
+
+        /* Clear FLASH End of Operation pending bit */
+        __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2);
+      }
+    }
+    else
+    {
+      procedure = pFlash.ProcedureOnGoing;
+
+      if((procedure == FLASH_PROC_MASSERASE_BANK2) || (procedure == FLASH_PROC_ALLBANK_MASSERASE))
+      {
+        /*MassErase ended. Return the selected bank*/
+        /* FLASH EOP interrupt user callback */
+        HAL_FLASH_EndOfOperationCallback(FLASH_BANK_2);
+      }
+      else if(procedure == FLASH_PROC_PROGRAM_BANK2)
+      {
+        /* Program ended. Return the selected address */
+        /* FLASH EOP interrupt user callback */
+        HAL_FLASH_EndOfOperationCallback(pFlash.Address);
+      }
+      else
+      {
+        /* Nothing to do */
+      }
+
+      if((procedure != FLASH_PROC_SECTERASE_BANK1) && \
+         (procedure != FLASH_PROC_MASSERASE_BANK1) && \
+         (procedure != FLASH_PROC_PROGRAM_BANK1))
+      {
+        pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+        /* Clear FLASH End of Operation pending bit */
+        __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2);
+      }
+    }
+  }
+
+  /* Check FLASH Bank1 operation error flags */
+#if defined (FLASH_SR_OPERR)
+  errorflag = FLASH->SR1 & (FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | FLASH_FLAG_STRBERR_BANK1 | \
+                            FLASH_FLAG_INCERR_BANK1 | FLASH_FLAG_OPERR_BANK1);
+#else
+  errorflag = FLASH->SR1 & (FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | FLASH_FLAG_STRBERR_BANK1 | \
+                            FLASH_FLAG_INCERR_BANK1);
+#endif /* FLASH_SR_OPERR */
+
+  if(errorflag != 0U)
+  {
+    /* Save the error code */
+    pFlash.ErrorCode |= errorflag;
+
+    /* Clear error programming flags */
+    __HAL_FLASH_CLEAR_FLAG_BANK1(errorflag);
+
+    procedure = pFlash.ProcedureOnGoing;
+
+    if(procedure == FLASH_PROC_SECTERASE_BANK1)
+    {
+      /* Return the faulty sector */
+      temp = pFlash.Sector;
+      pFlash.Sector = 0xFFFFFFFFU;
+    }
+    else if((procedure == FLASH_PROC_MASSERASE_BANK1) || (procedure == FLASH_PROC_ALLBANK_MASSERASE))
+    {
+      /* Return the faulty bank */
+      temp = FLASH_BANK_1;
+    }
+    else
+    {
+      /* Return the faulty address */
+      temp = pFlash.Address;
+    }
+
+    /* Stop the procedure ongoing*/
+    pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+
+    /* FLASH error interrupt user callback */
+    HAL_FLASH_OperationErrorCallback(temp);
+  }
+
+  /* Check FLASH Bank2 operation error flags */
+#if defined (FLASH_SR_OPERR)
+  errorflag = FLASH->SR2 & ((FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | FLASH_FLAG_STRBERR_BANK2 | \
+                             FLASH_FLAG_INCERR_BANK2 | FLASH_FLAG_OPERR_BANK2) & 0x7FFFFFFFU);
+#else
+  errorflag = FLASH->SR2 & ((FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | FLASH_FLAG_STRBERR_BANK2 | \
+                             FLASH_FLAG_INCERR_BANK2) & 0x7FFFFFFFU);
+#endif /* FLASH_SR_OPERR */
+
+  if(errorflag != 0U)
+  {
+    /* Save the error code */
+    pFlash.ErrorCode |= (errorflag | 0x80000000U);
+
+    /* Clear error programming flags */
+    __HAL_FLASH_CLEAR_FLAG_BANK2(errorflag);
+
+    procedure = pFlash.ProcedureOnGoing;
+
+    if(procedure== FLASH_PROC_SECTERASE_BANK2)
+    {
+      /*return the faulty sector*/
+      temp = pFlash.Sector;
+      pFlash.Sector = 0xFFFFFFFFU;
+    }
+    else if((procedure == FLASH_PROC_MASSERASE_BANK2) || (procedure == FLASH_PROC_ALLBANK_MASSERASE))
+    {
+      /*return the faulty bank*/
+      temp = FLASH_BANK_2;
+    }
+    else
+    {
+      /*return the faulty address*/
+      temp = pFlash.Address;
+    }
+
+    /*Stop the procedure ongoing*/
+    pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+
+    /* FLASH error interrupt user callback */
+    HAL_FLASH_OperationErrorCallback(temp);
+  }
+
+  if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
+  {
+#if defined (FLASH_CR_OPERRIE)
+    /* Disable Bank1 Operation and Error source interrupt */
+    __HAL_FLASH_DISABLE_IT_BANK1(FLASH_IT_EOP_BANK1    | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
+                                 FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1);
+
+    /* Disable Bank2 Operation and Error source interrupt */
+    __HAL_FLASH_DISABLE_IT_BANK2(FLASH_IT_EOP_BANK2    | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
+                                 FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2);
+#else
+    /* Disable Bank1 Operation and Error source interrupt */
+    __HAL_FLASH_DISABLE_IT_BANK1(FLASH_IT_EOP_BANK1    | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
+                                 FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1);
+
+    /* Disable Bank2 Operation and Error source interrupt */
+    __HAL_FLASH_DISABLE_IT_BANK2(FLASH_IT_EOP_BANK2    | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
+                                 FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2);
+#endif /* FLASH_CR_OPERRIE */
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(&pFlash);
+  }
+}
+
+/**
+  * @brief  FLASH end of operation interrupt callback
+  * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure
+  *                  Mass Erase: Bank number which has been requested to erase
+  *                  Sectors Erase: Sector which has been erased
+  *                    (if 0xFFFFFFFF, it means that all the selected sectors have been erased)
+  *                  Program: Address which was selected for data program
+  * @retval None
+  */
+__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(ReturnValue);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  FLASH operation error interrupt callback
+  * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure
+  *                 Mass Erase: Bank number which has been requested to erase
+  *                 Sectors Erase: Sector number which returned an error
+  *                 Program: Address which was selected for data program
+  * @retval None
+  */
+__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(ReturnValue);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FLASH_OperationErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
+ *  @brief   Management functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the FLASH
+    memory operations.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Unlock the FLASH control registers access
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Unlock(void)
+{
+  if(READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != 0U)
+  {
+    /* Authorize the FLASH Bank1 Registers access */
+    WRITE_REG(FLASH->KEYR1, FLASH_KEY1);
+    WRITE_REG(FLASH->KEYR1, FLASH_KEY2);
+
+    /* Verify Flash Bank1 is unlocked */
+    if (READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != 0U)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  if(READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != 0U)
+  {
+    /* Authorize the FLASH Bank2 Registers access */
+    WRITE_REG(FLASH->KEYR2, FLASH_KEY1);
+    WRITE_REG(FLASH->KEYR2, FLASH_KEY2);
+
+    /* Verify Flash Bank2 is unlocked */
+    if (READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != 0U)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Locks the FLASH control registers access
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Lock(void)
+{
+  /* Set the LOCK Bit to lock the FLASH Bank1 Control Register access */
+  SET_BIT(FLASH->CR1, FLASH_CR_LOCK);
+
+  /* Verify Flash Bank1 is locked */
+  if (READ_BIT(FLASH->CR1, FLASH_CR_LOCK) == 0U)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the LOCK Bit to lock the FLASH Bank2 Control Register access */
+  SET_BIT(FLASH->CR2, FLASH_CR_LOCK);
+
+  /* Verify Flash Bank2 is locked */
+  if (READ_BIT(FLASH->CR2, FLASH_CR_LOCK) == 0U)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Unlock the FLASH Option Control Registers access.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
+{
+  if(READ_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK) != 0U)
+  {
+    /* Authorizes the Option Byte registers programming */
+    WRITE_REG(FLASH->OPTKEYR, FLASH_OPT_KEY1);
+    WRITE_REG(FLASH->OPTKEYR, FLASH_OPT_KEY2);
+
+    /* Verify that the Option Bytes are unlocked */
+    if (READ_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK) != 0U)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Lock the FLASH Option Control Registers access.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
+{
+  /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
+  SET_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK);
+
+  /* Verify that the Option Bytes are locked */
+  if (READ_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK) == 0U)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Launch the option bytes loading.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
+{
+  HAL_StatusTypeDef status;
+
+  /* Wait for CRC computation to be completed */
+  if (FLASH_CRC_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK)
+  {
+    status = HAL_ERROR;
+  }
+  else if (FLASH_CRC_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    status = HAL_OK;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Set OPTSTRT Bit */
+    SET_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTSTART);
+
+    /* Wait for OB change operation to be completed */
+    status = FLASH_OB_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+  }
+
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions
+ *  @brief   Peripheral Errors functions
+ *
+@verbatim
+ ===============================================================================
+                ##### Peripheral Errors functions #####
+ ===============================================================================
+    [..]
+    This subsection permits to get in run-time Errors of the FLASH peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Get the specific FLASH error flag.
+  * @retval HAL_FLASH_ERRORCode The returned value can be:
+  *            @arg HAL_FLASH_ERROR_NONE       : No error set
+  *
+  *            @arg HAL_FLASH_ERROR_WRP_BANK1  : Write Protection Error on Bank 1
+  *            @arg HAL_FLASH_ERROR_PGS_BANK1  : Program Sequence Error on Bank 1
+  *            @arg HAL_FLASH_ERROR_STRB_BANK1 : Strobe Error on Bank 1
+  *            @arg HAL_FLASH_ERROR_INC_BANK1  : Inconsistency Error on Bank 1
+  *            @arg HAL_FLASH_ERROR_OPE_BANK1  : Operation Error on Bank 1
+  *            @arg HAL_FLASH_ERROR_RDP_BANK1  : Read Protection Error on Bank 1
+  *            @arg HAL_FLASH_ERROR_RDS_BANK1  : Read Secured Error on Bank 1
+  *            @arg HAL_FLASH_ERROR_SNECC_BANK1: ECC Single Correction Error on Bank 1
+  *            @arg HAL_FLASH_ERROR_DBECC_BANK1: ECC Double Detection Error on Bank 1
+  *            @arg HAL_FLASH_ERROR_CRCRD_BANK1: CRC Read Error on Bank 1
+  *
+  *            @arg HAL_FLASH_ERROR_WRP_BANK2  : Write Protection Error on Bank 2
+  *            @arg HAL_FLASH_ERROR_PGS_BANK2  : Program Sequence Error on Bank 2
+  *            @arg HAL_FLASH_ERROR_STRB_BANK2 : Strobe Error on Bank 2
+  *            @arg HAL_FLASH_ERROR_INC_BANK2  : Inconsistency Error on Bank 2
+  *            @arg HAL_FLASH_ERROR_OPE_BANK2  : Operation Error on Bank 2
+  *            @arg HAL_FLASH_ERROR_RDP_BANK2  : Read Protection Error on Bank 2
+  *            @arg HAL_FLASH_ERROR_RDS_BANK2  : Read Secured Error on Bank 2
+  *            @arg HAL_FLASH_ERROR_SNECC_BANK2: SNECC Error on Bank 2
+  *            @arg HAL_FLASH_ERROR_DBECC_BANK2: Double Detection ECC on Bank 2
+  *            @arg HAL_FLASH_ERROR_CRCRD_BANK2: CRC Read Error on Bank 2
+*/
+
+uint32_t HAL_FLASH_GetError(void)
+{
+   return pFlash.ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @addtogroup FLASH_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Wait for a FLASH operation to complete.
+  * @param  Timeout maximum flash operation timeout
+  * @param  Bank flash FLASH_BANK_1 or FLASH_BANK_2
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout, uint32_t Bank)
+{
+  /* Wait for the FLASH operation to complete by polling on QW flag to be reset.
+     Even if the FLASH operation fails, the QW flag will be reset and an error
+     flag will be set */
+
+  uint32_t bsyflag, errorflag;
+  uint32_t tickstart = HAL_GetTick();
+
+  assert_param(IS_FLASH_BANK_EXCLUSIVE(Bank));
+
+  /* Select bsyflag depending on Bank */
+  if(Bank == FLASH_BANK_1)
+  {
+    bsyflag = FLASH_FLAG_QW_BANK1;
+  }
+  else
+  {
+    bsyflag = FLASH_FLAG_QW_BANK2;
+  }
+
+  while(__HAL_FLASH_GET_FLAG(bsyflag))
+  {
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  /* Get Error Flags */
+  if (Bank == FLASH_BANK_1)
+  {
+    errorflag = FLASH->SR1 & FLASH_FLAG_ALL_ERRORS_BANK1;
+  }
+  else
+  {
+    errorflag = (FLASH->SR2 & FLASH_FLAG_ALL_ERRORS_BANK2) | 0x80000000U;
+  }
+
+  /* In case of error reported in Flash SR1 or SR2 registers (ECCC not managed as an error) */
+  if((errorflag & 0x7DFFFFFFU) != 0U)
+  {
+    /*Save the error code*/
+    pFlash.ErrorCode |= errorflag;
+
+    /* Clear error programming flags */
+    __HAL_FLASH_CLEAR_FLAG(errorflag);
+
+    return HAL_ERROR;
+  }
+
+  /* Check FLASH End of Operation flag  */
+  if(Bank == FLASH_BANK_1)
+  {
+    if (__HAL_FLASH_GET_FLAG_BANK1(FLASH_FLAG_EOP_BANK1))
+    {
+      /* Clear FLASH End of Operation pending bit */
+      __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1);
+    }
+  }
+  else
+  {
+    if (__HAL_FLASH_GET_FLAG_BANK2(FLASH_FLAG_EOP_BANK2))
+    {
+      /* Clear FLASH End of Operation pending bit */
+      __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2);
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Wait for a FLASH Option Bytes change operation to complete.
+  * @param  Timeout maximum flash operation timeout
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef FLASH_OB_WaitForLastOperation(uint32_t Timeout)
+{
+  /* Get timeout */
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Wait for the FLASH Option Bytes change operation to complete by polling on OPT_BUSY flag to be reset */
+  while(READ_BIT(FLASH->OPTSR_CUR, FLASH_OPTSR_OPT_BUSY) != 0U)
+  {
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  /* Check option byte change error */
+  if(READ_BIT(FLASH->OPTSR_CUR, FLASH_OPTSR_OPTCHANGEERR) != 0U)
+  {
+    /* Save the error code */
+    pFlash.ErrorCode |= HAL_FLASH_ERROR_OB_CHANGE;
+
+    /* Clear the OB error flag */
+    FLASH->OPTCCR |= FLASH_OPTCCR_CLR_OPTCHANGEERR;
+
+    return HAL_ERROR;
+  }
+
+  /* If there is no error flag set */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Wait for a FLASH CRC computation to complete.
+  * @param  Timeout maximum flash operation timeout
+  * @param  Bank flash FLASH_BANK_1 or FLASH_BANK_2
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef FLASH_CRC_WaitForLastOperation(uint32_t Timeout, uint32_t Bank)
+{
+  uint32_t bsyflag;
+  uint32_t tickstart = HAL_GetTick();
+
+  assert_param(IS_FLASH_BANK_EXCLUSIVE(Bank));
+
+  /* Select bsyflag depending on Bank */
+  if(Bank == FLASH_BANK_1)
+  {
+    bsyflag = FLASH_FLAG_CRC_BUSY_BANK1;
+  }
+  else
+  {
+    bsyflag = FLASH_FLAG_CRC_BUSY_BANK2;
+  }
+
+  /* Wait for the FLASH CRC computation to complete by polling on CRC_BUSY flag to be reset */
+  while(__HAL_FLASH_GET_FLAG(bsyflag))
+  {
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  /* Check FLASH CRC read error flag  */
+  if(Bank == FLASH_BANK_1)
+  {
+    if (__HAL_FLASH_GET_FLAG_BANK1(FLASH_FLAG_CRCRDERR_BANK1))
+    {
+      /* Save the error code */
+      pFlash.ErrorCode |= HAL_FLASH_ERROR_CRCRD_BANK1;
+
+      /* Clear FLASH CRC read error pending bit */
+      __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_CRCRDERR_BANK1);
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    if (__HAL_FLASH_GET_FLAG_BANK2(FLASH_FLAG_CRCRDERR_BANK2))
+    {
+      /* Save the error code */
+      pFlash.ErrorCode |= HAL_FLASH_ERROR_CRCRD_BANK2;
+
+      /* Clear FLASH CRC read error pending bit */
+      __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_CRCRDERR_BANK2);
+
+      return HAL_ERROR;
+    }
+  }
+
+  /* If there is no error flag set */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c
new file mode 100644
index 00000000..77b809f7
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c
@@ -0,0 +1,1709 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_flash_ex.c
+  * @author  MCD Application Team
+  * @brief   Extended FLASH HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the FLASH extension peripheral:
+  *           + Extended programming operations functions
+  *
+ @verbatim
+ ==============================================================================
+                   ##### Flash Extension features #####
+  ==============================================================================
+
+  [..] Comparing to other previous devices, the FLASH interface for STM32H7xx
+       devices contains the following additional features
+
+       (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
+           capability (RWW)
+       (+) Dual bank memory organization
+       (+) PCROP protection for all banks
+       (+) Global readout protection (RDP)
+       (+) Write protection
+       (+) Secure access only protection
+       (+) Bank / register swapping
+       (+) Cyclic Redundancy Check (CRC)
+
+                        ##### How to use this driver #####
+ ==============================================================================
+  [..] This driver provides functions to configure and program the FLASH memory
+       of all STM32H7xx devices. It includes
+      (#) FLASH Memory Erase functions:
+           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
+                HAL_FLASH_Lock() functions
+           (++) Erase function: Sector erase, bank erase and dual-bank mass erase
+           (++) There are two modes of erase :
+             (+++) Polling Mode using HAL_FLASHEx_Erase()
+             (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
+
+      (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to:
+        (++) Set/Reset the write protection per bank
+        (++) Set the Read protection Level
+        (++) Set the BOR level
+        (++) Program the user Option Bytes
+        (++) PCROP protection configuration and control per bank
+        (++) Secure area configuration and control per bank
+        (++) Core Boot address configuration
+
+      (#) FLASH Memory Lock and unlock per Bank: HAL_FLASHEx_Lock_Bank1(), HAL_FLASHEx_Unlock_Bank1(),
+          HAL_FLASHEx_Lock_Bank2() and HAL_FLASHEx_Unlock_Bank2() functions
+
+      (#) FLASH CRC computation function: Use HAL_FLASHEx_ComputeCRC() to:
+          (++) Enable CRC feature
+          (++) Program the desired burst size
+          (++) Define the user Flash Area on which the CRC has be computed
+          (++) Perform the CRC computation
+          (++) Disable CRC feature
+
+ @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup FLASHEx  FLASHEx
+  * @brief FLASH HAL Extension module driver
+  * @{
+  */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup FLASHEx_Private_Constants
+  * @{
+  */
+#define FLASH_TIMEOUT_VALUE       50000U /* 50 s */
+
+/**
+  * @}
+  */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
+  * @{
+  */
+static void FLASH_MassErase(uint32_t VoltageRange, uint32_t Banks);
+static void FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks);
+static void FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Bank);
+static void FLASH_OB_GetWRP(uint32_t *WRPState, uint32_t *WRPSector, uint32_t Bank);
+static void FLASH_OB_RDPConfig(uint32_t RDPLevel);
+static uint32_t FLASH_OB_GetRDP(void);
+static void FLASH_OB_PCROPConfig(uint32_t PCROConfigRDP, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr, uint32_t Banks);
+static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROPStartAddr,uint32_t *PCROPEndAddr, uint32_t Bank);
+static void FLASH_OB_BOR_LevelConfig(uint32_t Level);
+static uint32_t FLASH_OB_GetBOR(void);
+static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig);
+static uint32_t FLASH_OB_GetUser(void);
+static void FLASH_OB_BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1);
+static void FLASH_OB_GetBootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1);
+static void FLASH_OB_SecureAreaConfig(uint32_t SecureAreaConfig, uint32_t SecureAreaStartAddr, uint32_t SecureAreaEndAddr, uint32_t Banks);
+static void FLASH_OB_GetSecureArea(uint32_t *SecureAreaConfig, uint32_t *SecureAreaStartAddr, uint32_t *SecureAreaEndAddr, uint32_t Bank);
+static void FLASH_CRC_AddSector(uint32_t Sector, uint32_t Bank);
+static void FLASH_CRC_SelectAddress(uint32_t CRCStartAddr, uint32_t CRCEndAddr, uint32_t Bank);
+
+#if defined (DUAL_CORE)
+static void FLASH_OB_CM4BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1);
+static void FLASH_OB_GetCM4BootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1);
+#endif /* DUAL_CORE */
+
+#if defined (FLASH_OTPBL_LOCKBL)
+static void FLASH_OB_OTP_LockConfig(uint32_t OTP_Block);
+static uint32_t FLASH_OB_OTP_GetLock(void);
+#endif /* FLASH_OTPBL_LOCKBL */
+/**
+  * @}
+  */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
+  * @{
+  */
+
+/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
+ *  @brief   Extended IO operation functions
+ *
+@verbatim
+ ===============================================================================
+                ##### Extended programming operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the Extension FLASH
+    programming operations Operations.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Perform a mass erase or erase the specified FLASH memory sectors
+  * @param[in]  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
+  *         contains the configuration information for the erasing.
+  *
+  * @param[out]  SectorError pointer to variable  that contains the configuration
+  *          information on faulty sector in case of error (0xFFFFFFFF means that all
+  *          the sectors have been correctly erased)
+  *
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t sector_index;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
+  assert_param(IS_FLASH_BANK(pEraseInit->Banks));
+
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Reset error code */
+  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+  /* Wait for last operation to be completed on Bank1 */
+  if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
+  {
+    if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK)
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  /* Wait for last operation to be completed on Bank2 */
+  if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
+  {
+    if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK)
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  if(status == HAL_OK)
+  {
+    if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
+    {
+      /* Mass erase to be done */
+      FLASH_MassErase(pEraseInit->VoltageRange, pEraseInit->Banks);
+
+      /* Wait for last operation to be completed */
+      if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
+      {
+        if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK)
+        {
+          status = HAL_ERROR;
+        }
+        /* if the erase operation is completed, disable the Bank1 BER Bit */
+        FLASH->CR1 &= (~FLASH_CR_BER);
+      }
+      if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
+      {
+        if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK)
+        {
+          status = HAL_ERROR;
+        }
+        /* if the erase operation is completed, disable the Bank2 BER Bit */
+        FLASH->CR2 &= (~FLASH_CR_BER);
+      }
+    }
+    else
+    {
+      /*Initialization of SectorError variable*/
+      *SectorError = 0xFFFFFFFFU;
+
+      /* Erase by sector by sector to be done*/
+      for(sector_index = pEraseInit->Sector; sector_index < (pEraseInit->NbSectors + pEraseInit->Sector); sector_index++)
+      {
+        FLASH_Erase_Sector(sector_index, pEraseInit->Banks, pEraseInit->VoltageRange);
+
+        if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
+        {
+          /* Wait for last operation to be completed */
+          status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
+
+          /* If the erase operation is completed, disable the SER Bit */
+          FLASH->CR1 &= (~(FLASH_CR_SER | FLASH_CR_SNB));
+        }
+        if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
+        {
+          /* Wait for last operation to be completed */
+          status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
+
+          /* If the erase operation is completed, disable the SER Bit */
+          FLASH->CR2 &= (~(FLASH_CR_SER | FLASH_CR_SNB));
+        }
+
+        if(status != HAL_OK)
+        {
+          /* In case of error, stop erase procedure and return the faulty sector */
+          *SectorError = sector_index;
+          break;
+        }
+      }
+    }
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(&pFlash);
+
+  return status;
+}
+
+/**
+  * @brief  Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled
+  * @param  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
+  *         contains the configuration information for the erasing.
+  *
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
+  assert_param(IS_FLASH_BANK(pEraseInit->Banks));
+
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Reset error code */
+  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+  /* Wait for last operation to be completed */
+  if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
+  {
+    if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK)
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
+  {
+    if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK)
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  if (status != HAL_OK)
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(&pFlash);
+  }
+  else
+  {
+    if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
+    {
+      /* Enable End of Operation and Error interrupts for Bank 1 */
+#if defined (FLASH_CR_OPERRIE)
+      __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1     | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
+                                  FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1);
+#else
+      __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1     | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
+                                  FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1);
+#endif /* FLASH_CR_OPERRIE */
+    }
+    if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
+    {
+      /* Enable End of Operation and Error interrupts for Bank 2 */
+#if defined (FLASH_CR_OPERRIE)
+      __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2     | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
+                                  FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2);
+#else
+      __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2     | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
+                                  FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2);
+#endif /* FLASH_CR_OPERRIE */
+    }
+
+    if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
+    {
+      /*Mass erase to be done*/
+      if(pEraseInit->Banks == FLASH_BANK_1)
+      {
+        pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE_BANK1;
+      }
+      else if(pEraseInit->Banks == FLASH_BANK_2)
+      {
+        pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE_BANK2;
+      }
+      else
+      {
+        pFlash.ProcedureOnGoing = FLASH_PROC_ALLBANK_MASSERASE;
+      }
+
+      FLASH_MassErase(pEraseInit->VoltageRange, pEraseInit->Banks);
+    }
+    else
+    {
+      /* Erase by sector to be done */
+      if(pEraseInit->Banks == FLASH_BANK_1)
+      {
+        pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE_BANK1;
+      }
+      else
+      {
+        pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE_BANK2;
+      }
+
+      pFlash.NbSectorsToErase = pEraseInit->NbSectors;
+      pFlash.Sector = pEraseInit->Sector;
+      pFlash.VoltageForErase = pEraseInit->VoltageRange;
+
+      /* Erase first sector and wait for IT */
+      FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->Banks, pEraseInit->VoltageRange);
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Program option bytes
+  * @param  pOBInit pointer to an FLASH_OBInitStruct structure that
+  *         contains the configuration information for the programming.
+  *
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check the parameters */
+  assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
+
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Reset Error Code */
+  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+  /* Wait for last operation to be completed */
+  if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK)
+  {
+    status = HAL_ERROR;
+  }
+  else if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    status = HAL_OK;
+  }
+
+  if(status == HAL_OK)
+  {
+    /*Write protection configuration*/
+    if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
+    {
+      assert_param(IS_WRPSTATE(pOBInit->WRPState));
+
+      if(pOBInit->WRPState == OB_WRPSTATE_ENABLE)
+      {
+        /*Enable of Write protection on the selected Sector*/
+        FLASH_OB_EnableWRP(pOBInit->WRPSector,pOBInit->Banks);
+      }
+      else
+      {
+        /*Disable of Write protection on the selected Sector*/
+        FLASH_OB_DisableWRP(pOBInit->WRPSector, pOBInit->Banks);
+      }
+    }
+
+    /* Read protection configuration */
+    if((pOBInit->OptionType & OPTIONBYTE_RDP) != 0U)
+    {
+      /* Configure the Read protection level */
+      FLASH_OB_RDPConfig(pOBInit->RDPLevel);
+    }
+
+    /* User Configuration */
+    if((pOBInit->OptionType & OPTIONBYTE_USER) != 0U)
+    {
+      /* Configure the user option bytes */
+      FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig);
+    }
+
+    /* PCROP Configuration */
+    if((pOBInit->OptionType & OPTIONBYTE_PCROP) != 0U)
+    {
+      assert_param(IS_FLASH_BANK(pOBInit->Banks));
+
+      /*Configure the Proprietary code readout protection */
+      FLASH_OB_PCROPConfig(pOBInit->PCROPConfig, pOBInit->PCROPStartAddr, pOBInit->PCROPEndAddr, pOBInit->Banks);
+    }
+
+    /* BOR Level configuration */
+    if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR)
+    {
+      FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel);
+    }
+
+#if defined(DUAL_CORE)
+    /* CM7 Boot Address  configuration */
+    if((pOBInit->OptionType & OPTIONBYTE_CM7_BOOTADD) == OPTIONBYTE_CM7_BOOTADD)
+    {
+      FLASH_OB_BootAddConfig(pOBInit->BootConfig, pOBInit->BootAddr0, pOBInit->BootAddr1);
+    }
+
+    /* CM4 Boot Address  configuration */
+    if((pOBInit->OptionType & OPTIONBYTE_CM4_BOOTADD) == OPTIONBYTE_CM4_BOOTADD)
+    {
+      FLASH_OB_CM4BootAddConfig(pOBInit->CM4BootConfig, pOBInit->CM4BootAddr0, pOBInit->CM4BootAddr1);
+    }
+#else /* Single Core*/
+    /* Boot Address  configuration */
+    if((pOBInit->OptionType & OPTIONBYTE_BOOTADD) == OPTIONBYTE_BOOTADD)
+    {
+      FLASH_OB_BootAddConfig(pOBInit->BootConfig, pOBInit->BootAddr0, pOBInit->BootAddr1);
+    }
+#endif /*DUAL_CORE*/
+
+    /* Secure area configuration */
+    if((pOBInit->OptionType & OPTIONBYTE_SECURE_AREA) == OPTIONBYTE_SECURE_AREA)
+    {
+      FLASH_OB_SecureAreaConfig(pOBInit->SecureAreaConfig, pOBInit->SecureAreaStartAddr, pOBInit->SecureAreaEndAddr,pOBInit->Banks);
+    }
+
+#if defined(FLASH_OTPBL_LOCKBL)
+    /* OTP Block Lock configuration */
+    if((pOBInit->OptionType & OPTIONBYTE_OTP_LOCK) == OPTIONBYTE_OTP_LOCK)
+    {
+      FLASH_OB_OTP_LockConfig(pOBInit->OTPBlockLock);
+    }
+#endif /* FLASH_OTPBL_LOCKBL */
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(&pFlash);
+
+  return status;
+}
+
+/**
+  * @brief Get the Option byte configuration
+  * @param  pOBInit pointer to an FLASH_OBInitStruct structure that
+  *         contains the configuration information for the programming.
+  * @note   The parameter Banks of the pOBInit structure must be set exclusively to FLASH_BANK_1 or FLASH_BANK_2,
+  *         as this parameter is use to get the given Bank WRP, PCROP and secured area configuration.
+  *
+  * @retval None
+  */
+void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
+{
+  pOBInit->OptionType = (OPTIONBYTE_USER | OPTIONBYTE_RDP | OPTIONBYTE_BOR);
+
+  /* Get Read protection level */
+  pOBInit->RDPLevel = FLASH_OB_GetRDP();
+
+  /* Get the user option bytes */
+  pOBInit->USERConfig = FLASH_OB_GetUser();
+
+  /*Get BOR Level*/
+  pOBInit->BORLevel = FLASH_OB_GetBOR();
+
+  if ((pOBInit->Banks == FLASH_BANK_1) || (pOBInit->Banks == FLASH_BANK_2))
+  {
+    pOBInit->OptionType |= (OPTIONBYTE_WRP | OPTIONBYTE_PCROP | OPTIONBYTE_SECURE_AREA);
+
+    /* Get write protection on the selected area */
+    FLASH_OB_GetWRP(&(pOBInit->WRPState), &(pOBInit->WRPSector), pOBInit->Banks);
+
+    /* Get the Proprietary code readout protection */
+    FLASH_OB_GetPCROP(&(pOBInit->PCROPConfig), &(pOBInit->PCROPStartAddr), &(pOBInit->PCROPEndAddr), pOBInit->Banks);
+
+    /*Get Bank Secure area*/
+    FLASH_OB_GetSecureArea(&(pOBInit->SecureAreaConfig), &(pOBInit->SecureAreaStartAddr), &(pOBInit->SecureAreaEndAddr), pOBInit->Banks);
+  }
+
+  /*Get Boot Address*/
+  FLASH_OB_GetBootAdd(&(pOBInit->BootAddr0), &(pOBInit->BootAddr1));
+#if defined(DUAL_CORE)
+  pOBInit->OptionType |= OPTIONBYTE_CM7_BOOTADD | OPTIONBYTE_CM4_BOOTADD;
+
+  /*Get CM4 Boot Address*/
+  FLASH_OB_GetCM4BootAdd(&(pOBInit->CM4BootAddr0), &(pOBInit->CM4BootAddr1));
+#else
+  pOBInit->OptionType |= OPTIONBYTE_BOOTADD;
+#endif /*DUAL_CORE*/
+
+#if defined (FLASH_OTPBL_LOCKBL)
+  pOBInit->OptionType |= OPTIONBYTE_OTP_LOCK;
+
+  /* Get OTP Block Lock */
+  pOBInit->OTPBlockLock = FLASH_OB_OTP_GetLock();
+#endif /* FLASH_OTPBL_LOCKBL */
+}
+
+/**
+  * @brief  Unlock the FLASH Bank1 control registers access
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank1(void)
+{
+  if(READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != 0U)
+  {
+    /* Authorize the FLASH Bank1 Registers access */
+    WRITE_REG(FLASH->KEYR1, FLASH_KEY1);
+    WRITE_REG(FLASH->KEYR1, FLASH_KEY2);
+
+    /* Verify Flash Bank1 is unlocked */
+    if (READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != 0U)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Locks the FLASH Bank1 control registers access
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1(void)
+{
+  /* Set the LOCK Bit to lock the FLASH Bank1 Registers access */
+  SET_BIT(FLASH->CR1, FLASH_CR_LOCK);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Unlock the FLASH Bank2 control registers access
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank2(void)
+{
+  if(READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != 0U)
+  {
+    /* Authorize the FLASH Bank2 Registers access */
+    WRITE_REG(FLASH->KEYR2, FLASH_KEY1);
+    WRITE_REG(FLASH->KEYR2, FLASH_KEY2);
+
+    /* Verify Flash Bank1 is unlocked */
+    if (READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != 0U)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Locks the FLASH Bank2 control registers access
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank2(void)
+{
+  /* Set the LOCK Bit to lock the FLASH Bank2 Registers access */
+  SET_BIT(FLASH->CR2, FLASH_CR_LOCK);
+  return HAL_OK;
+}
+
+/*
+  * @brief  Perform a CRC computation on the specified FLASH memory area
+  * @param  pCRCInit pointer to an FLASH_CRCInitTypeDef structure that
+  *         contains the configuration information for the CRC computation.
+  * @note   CRC computation uses CRC-32 (Ethernet) polynomial 0x4C11DB7
+  * @note   The application should avoid running a CRC on PCROP or secure-only
+  *         user Flash memory area since it may alter the expected CRC value.
+  *         A special error flag (CRC read error: CRCRDERR) can be used to
+  *         detect such a case.
+  * @retval HAL Status
+*/
+HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_t *CRC_Result)
+{
+  HAL_StatusTypeDef status;
+  uint32_t sector_index;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_BANK_EXCLUSIVE(pCRCInit->Bank));
+  assert_param(IS_FLASH_TYPECRC(pCRCInit->TypeCRC));
+
+  /* Wait for OB change operation to be completed */
+  status = FLASH_OB_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if (status == HAL_OK)
+  {
+    if (pCRCInit->Bank == FLASH_BANK_1)
+    {
+      /* Enable CRC feature */
+      FLASH->CR1 |= FLASH_CR_CRC_EN;
+
+      /* Clear CRC flags in Status Register: CRC end of calculation and CRC read error */
+      FLASH->CCR1 |= (FLASH_CCR_CLR_CRCEND | FLASH_CCR_CLR_CRCRDERR);
+
+      /* Clear current CRC result, program burst size and define memory area on which CRC has to be computed */
+      FLASH->CRCCR1 |= FLASH_CRCCR_CLEAN_CRC | pCRCInit->BurstSize | pCRCInit->TypeCRC;
+
+      if (pCRCInit->TypeCRC == FLASH_CRC_SECTORS)
+      {
+        /* Clear sectors list */
+        FLASH->CRCCR1 |= FLASH_CRCCR_CLEAN_SECT;
+
+        /* Select CRC sectors */
+        for(sector_index = pCRCInit->Sector; sector_index < (pCRCInit->NbSectors + pCRCInit->Sector); sector_index++)
+        {
+          FLASH_CRC_AddSector(sector_index, FLASH_BANK_1);
+        }
+      }
+      else if (pCRCInit->TypeCRC == FLASH_CRC_BANK)
+      {
+        /* Enable Bank 1 CRC select bit */
+        FLASH->CRCCR1 |= FLASH_CRCCR_ALL_BANK;
+      }
+      else
+      {
+        /* Select CRC start and end addresses */
+        FLASH_CRC_SelectAddress(pCRCInit->CRCStartAddr, pCRCInit->CRCEndAddr, FLASH_BANK_1);
+      }
+
+      /* Start the CRC calculation */
+      FLASH->CRCCR1 |= FLASH_CRCCR_START_CRC;
+
+      /* Wait on CRC busy flag */
+      status = FLASH_CRC_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
+
+      /* Return CRC result */
+      (*CRC_Result) = FLASH->CRCDATA;
+
+      /* Disable CRC feature */
+      FLASH->CR1 &= (~FLASH_CR_CRC_EN);
+
+      /* Clear CRC flags */
+      __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_CRCEND_BANK1 | FLASH_FLAG_CRCRDERR_BANK1);
+    }
+    else
+    {
+      /* Enable CRC feature */
+      FLASH->CR2 |= FLASH_CR_CRC_EN;
+
+      /* Clear CRC flags in Status Register: CRC end of calculation and CRC read error */
+      FLASH->CCR2 |= (FLASH_CCR_CLR_CRCEND | FLASH_CCR_CLR_CRCRDERR);
+
+      /* Clear current CRC result, program burst size and define memory area on which CRC has to be computed */
+      FLASH->CRCCR2 |= FLASH_CRCCR_CLEAN_CRC | pCRCInit->BurstSize | pCRCInit->TypeCRC;
+
+      if (pCRCInit->TypeCRC == FLASH_CRC_SECTORS)
+      {
+        /* Clear sectors list */
+        FLASH->CRCCR2 |= FLASH_CRCCR_CLEAN_SECT;
+
+        /* Add CRC sectors */
+        for(sector_index = pCRCInit->Sector; sector_index < (pCRCInit->NbSectors + pCRCInit->Sector); sector_index++)
+        {
+          FLASH_CRC_AddSector(sector_index, FLASH_BANK_2);
+        }
+      }
+      else if (pCRCInit->TypeCRC == FLASH_CRC_BANK)
+      {
+        /* Enable Bank 2 CRC select bit */
+        FLASH->CRCCR2 |= FLASH_CRCCR_ALL_BANK;
+      }
+      else
+      {
+        /* Select CRC start and end addresses */
+        FLASH_CRC_SelectAddress(pCRCInit->CRCStartAddr, pCRCInit->CRCEndAddr, FLASH_BANK_2);
+      }
+
+      /* Start the CRC calculation */
+      FLASH->CRCCR2 |= FLASH_CRCCR_START_CRC;
+
+      /* Wait on CRC busy flag */
+      status = FLASH_CRC_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
+
+      /* Return CRC result */
+      (*CRC_Result) = FLASH->CRCDATA;
+
+      /* Disable CRC feature */
+      FLASH->CR2 &= (~FLASH_CR_CRC_EN);
+
+      /* Clear CRC flags */
+      __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_CRCEND_BANK2 | FLASH_FLAG_CRCRDERR_BANK2);
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @addtogroup FLASHEx_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Mass erase of FLASH memory
+  * @param  VoltageRange The device program/erase parallelism.
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_VOLTAGE_RANGE_1 : Flash program/erase by 8 bits
+  *            @arg FLASH_VOLTAGE_RANGE_2 : Flash program/erase by 16 bits
+  *            @arg FLASH_VOLTAGE_RANGE_3 : Flash program/erase by 32 bits
+  *            @arg FLASH_VOLTAGE_RANGE_4 : Flash program/erase by 64 bits
+  *
+  * @param  Banks Banks to be erased
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: Bank1 to be erased
+  *            @arg FLASH_BANK_2: Bank2 to be erased
+  *            @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
+  *
+  * @retval HAL Status
+  */
+static void FLASH_MassErase(uint32_t VoltageRange, uint32_t Banks)
+{
+  /* Check the parameters */
+#if defined (FLASH_CR_PSIZE)
+  assert_param(IS_VOLTAGERANGE(VoltageRange));
+#else
+  UNUSED(VoltageRange);
+#endif /* FLASH_CR_PSIZE */
+  assert_param(IS_FLASH_BANK(Banks));
+
+  /* Flash Mass Erase */
+  if((Banks & FLASH_BANK_BOTH) == FLASH_BANK_BOTH)
+  {
+#if defined (FLASH_CR_PSIZE)
+    /* Reset Program/erase VoltageRange for Bank1 and Bank2 */
+    FLASH->CR1 &= (~FLASH_CR_PSIZE);
+    FLASH->CR2 &= (~FLASH_CR_PSIZE);
+
+    /* Set voltage range */
+    FLASH->CR1 |= VoltageRange;
+    FLASH->CR2 |= VoltageRange;
+#endif /* FLASH_CR_PSIZE */
+
+    /* Set Mass Erase Bit */
+    FLASH->OPTCR |= FLASH_OPTCR_MER;
+  }
+  else
+  {
+    /* Proceed to erase Flash Bank  */
+    if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
+    {
+#if defined (FLASH_CR_PSIZE)
+      /* Set Program/erase VoltageRange for Bank1 */
+      FLASH->CR1 &= (~FLASH_CR_PSIZE);
+      FLASH->CR1 |=  VoltageRange;
+#endif /* FLASH_CR_PSIZE */
+
+      /* Erase Bank1 */
+      FLASH->CR1 |= (FLASH_CR_BER | FLASH_CR_START);
+    }
+    if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
+    {
+#if defined (FLASH_CR_PSIZE)
+      /* Set Program/erase VoltageRange for Bank2 */
+      FLASH->CR2 &= (~FLASH_CR_PSIZE);
+      FLASH->CR2 |= VoltageRange;
+#endif /* FLASH_CR_PSIZE */
+
+      /* Erase Bank2 */
+      FLASH->CR2 |= (FLASH_CR_BER | FLASH_CR_START);
+    }
+  }
+}
+
+/**
+  * @brief  Erase the specified FLASH memory sector
+  * @param  Sector FLASH sector to erase
+  *          This parameter can be a value of @ref FLASH_Sectors
+  * @param  Banks Banks to be erased
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: Bank1 to be erased
+  *            @arg FLASH_BANK_2: Bank2 to be erased
+  *            @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
+  * @param  VoltageRange The device program/erase parallelism.
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_VOLTAGE_RANGE_1 : Flash program/erase by 8 bits
+  *            @arg FLASH_VOLTAGE_RANGE_2 : Flash program/erase by 16 bits
+  *            @arg FLASH_VOLTAGE_RANGE_3 : Flash program/erase by 32 bits
+  *            @arg FLASH_VOLTAGE_RANGE_4 : Flash program/erase by 64 bits
+  *
+  * @retval None
+  */
+void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange)
+{
+  assert_param(IS_FLASH_SECTOR(Sector));
+  assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks));
+#if defined (FLASH_CR_PSIZE)
+  assert_param(IS_VOLTAGERANGE(VoltageRange));
+#else
+  UNUSED(VoltageRange);
+#endif /* FLASH_CR_PSIZE */
+
+  if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
+  {
+#if defined (FLASH_CR_PSIZE)
+    /* Reset Program/erase VoltageRange and Sector Number for Bank1 */
+    FLASH->CR1 &= ~(FLASH_CR_PSIZE | FLASH_CR_SNB);
+
+    FLASH->CR1 |= (FLASH_CR_SER | VoltageRange | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START);
+#else
+    /* Reset Sector Number for Bank1 */
+    FLASH->CR1 &= ~(FLASH_CR_SNB);
+
+    FLASH->CR1 |= (FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START);
+#endif /* FLASH_CR_PSIZE */
+  }
+
+  if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
+  {
+#if defined (FLASH_CR_PSIZE)
+    /* Reset Program/erase VoltageRange and Sector Number for Bank2 */
+    FLASH->CR2 &= ~(FLASH_CR_PSIZE | FLASH_CR_SNB);
+
+    FLASH->CR2 |= (FLASH_CR_SER | VoltageRange  | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START);
+#else
+    /* Reset Sector Number for Bank2 */
+    FLASH->CR2 &= ~(FLASH_CR_SNB);
+
+    FLASH->CR2 |= (FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START);
+#endif /* FLASH_CR_PSIZE */
+  }
+}
+
+/**
+  * @brief  Enable the write protection of the desired bank1 or bank 2 sectors
+  * @param  WRPSector specifies the sector(s) to be write protected.
+  *          This parameter can be one of the following values:
+  *            @arg WRPSector:  A combination of OB_WRP_SECTOR_0 to OB_WRP_SECTOR_7 or OB_WRP_SECTOR_All
+  *
+  * @param  Banks the specific bank to apply WRP sectors
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: enable WRP on specified bank1 sectors
+  *            @arg FLASH_BANK_2: enable WRP on specified bank2 sectors
+  *            @arg FLASH_BANK_BOTH: enable WRP on both bank1 and bank2 specified sectors
+  *
+  * @retval HAL FLASH State
+  */
+static void FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
+{
+  /* Check the parameters */
+  assert_param(IS_OB_WRP_SECTOR(WRPSector));
+  assert_param(IS_FLASH_BANK(Banks));
+
+  if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
+  {
+    /* Enable Write Protection for bank 1 */
+    FLASH->WPSN_PRG1 &= (~(WRPSector & FLASH_WPSN_WRPSN));
+  }
+
+  if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
+  {
+    /* Enable Write Protection for bank 2 */
+    FLASH->WPSN_PRG2 &= (~(WRPSector & FLASH_WPSN_WRPSN));
+  }
+}
+
+/**
+  * @brief  Disable the write protection of the desired bank1 or bank 2 sectors
+  * @param  WRPSector specifies the sector(s) to disable write protection.
+  *          This parameter can be one of the following values:
+  *            @arg WRPSector:  A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_All
+  *
+  * @param  Banks the specific bank to apply WRP sectors
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: disable WRP on specified bank1 sectors
+  *            @arg FLASH_BANK_2: disable WRP on specified bank2 sectors
+  *            @arg FLASH_BANK_BOTH: disable WRP on both bank1 and bank2 specified sectors
+  *
+  * @retval HAL FLASH State
+  */
+static void FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)
+{
+  /* Check the parameters */
+  assert_param(IS_OB_WRP_SECTOR(WRPSector));
+  assert_param(IS_FLASH_BANK(Banks));
+
+  if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
+  {
+    /* Disable Write Protection for bank 1 */
+    FLASH->WPSN_PRG1 |= (WRPSector & FLASH_WPSN_WRPSN);
+  }
+
+  if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
+  {
+    /* Disable Write Protection for bank 2 */
+    FLASH->WPSN_PRG2 |= (WRPSector & FLASH_WPSN_WRPSN);
+  }
+}
+
+/**
+  * @brief  Get the write protection of the given bank 1 or bank 2 sectors
+  * @param  WRPState gives the write protection state on the given bank.
+  *          This parameter can be one of the following values:
+  *          @arg WRPState: OB_WRPSTATE_DISABLE or OB_WRPSTATE_ENABLE
+
+  * @param  WRPSector gives the write protected sector(s) on the given bank .
+  *          This parameter can be one of the following values:
+  *          @arg WRPSector: A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_All
+  *
+  * @param  Bank the specific bank to apply WRP sectors
+  *          This parameter can be exclusively one of the following values:
+  *            @arg FLASH_BANK_1: Get bank1 WRP sectors
+  *            @arg FLASH_BANK_2: Get bank2 WRP sectors
+  *            @arg FLASH_BANK_BOTH: note allowed in this functions
+  *
+  * @retval HAL FLASH State
+  */
+static void FLASH_OB_GetWRP(uint32_t *WRPState, uint32_t *WRPSector, uint32_t Bank)
+{
+  uint32_t regvalue = 0U;
+
+  if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_1)
+  {
+    regvalue = FLASH->WPSN_CUR1;
+  }
+
+  if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_2)
+  {
+    regvalue = FLASH->WPSN_CUR2;
+  }
+
+  (*WRPSector) = (~regvalue) & FLASH_WPSN_WRPSN;
+
+  if(*WRPSector == 0U)
+  {
+    (*WRPState) = OB_WRPSTATE_DISABLE;
+  }
+  else
+  {
+    (*WRPState) = OB_WRPSTATE_ENABLE;
+  }
+}
+
+/**
+  * @brief  Set the read protection level.
+  *
+  * @note   To configure the RDP level, the option lock bit OPTLOCK must be
+  *         cleared with the call of the HAL_FLASH_OB_Unlock() function.
+  * @note   To validate the RDP level, the option bytes must be reloaded
+  *         through the call of the HAL_FLASH_OB_Launch() function.
+  * @note   !!! Warning : When enabling OB_RDP level 2 it's no more possible
+  *         to go back to level 1 or 0 !!!
+  *
+  * @param  RDPLevel specifies the read protection level.
+  *         This parameter can be one of the following values:
+  *            @arg OB_RDP_LEVEL_0: No protection
+  *            @arg OB_RDP_LEVEL_1: Read protection of the memory
+  *            @arg OB_RDP_LEVEL_2: Full chip protection
+  *
+  * @retval HAL status
+  */
+static void FLASH_OB_RDPConfig(uint32_t RDPLevel)
+{
+  /* Check the parameters */
+  assert_param(IS_OB_RDP_LEVEL(RDPLevel));
+
+  /* Configure the RDP level in the option bytes register */
+  MODIFY_REG(FLASH->OPTSR_PRG, FLASH_OPTSR_RDP, RDPLevel);
+}
+
+/**
+  * @brief  Get the read protection level.
+  * @retval RDPLevel specifies the read protection level.
+  *         This return value can be one of the following values:
+  *            @arg OB_RDP_LEVEL_0: No protection
+  *            @arg OB_RDP_LEVEL_1: Read protection of the memory
+  *            @arg OB_RDP_LEVEL_2: Full chip protection
+  */
+static uint32_t FLASH_OB_GetRDP(void)
+{
+  uint32_t rdp_level = READ_BIT(FLASH->OPTSR_CUR, FLASH_OPTSR_RDP);
+  
+  if ((rdp_level != OB_RDP_LEVEL_0) && (rdp_level != OB_RDP_LEVEL_2))
+  {
+    return (OB_RDP_LEVEL_1);
+  }
+  else
+  {
+    return rdp_level;
+  }
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Program the FLASH User Option Byte.
+  *
+  * @note   To configure the user option bytes, the option lock bit OPTLOCK must
+  *         be cleared with the call of the HAL_FLASH_OB_Unlock() function.
+  *
+  * @note   To validate the user option bytes, the option bytes must be reloaded
+  *         through the call of the HAL_FLASH_OB_Launch() function.
+  *
+  * @param  UserType The FLASH User Option Bytes to be modified :
+  *                   a combination of @ref FLASHEx_OB_USER_Type
+  *
+  * @param  UserConfig The FLASH User Option Bytes values:
+  *         IWDG1_SW(Bit4), IWDG2_SW(Bit 5), nRST_STOP_D1(Bit 6), nRST_STDY_D1(Bit 7),
+  *         FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]),
+  *         SECURITY(Bit 21), BCM4(Bit 22), BCM7(Bit 23), nRST_STOP_D2(Bit 24),
+  *         nRST_STDY_D2(Bit 25), IO_HSLV (Bit 29) and SWAP_BANK_OPT(Bit 31).
+  *
+  * @retval HAL status
+  */
+#else
+/**
+  * @brief  Program the FLASH User Option Byte.
+  *
+  * @note   To configure the user option bytes, the option lock bit OPTLOCK must
+  *         be cleared with the call of the HAL_FLASH_OB_Unlock() function.
+  *
+  * @note   To validate the user option bytes, the option bytes must be reloaded
+  *         through the call of the HAL_FLASH_OB_Launch() function.
+  *
+  * @param  UserType The FLASH User Option Bytes to be modified :
+  *                   a combination of @arg FLASHEx_OB_USER_Type
+  *
+  * @param  UserConfig The FLASH User Option Bytes values:
+  *         IWDG_SW(Bit4), nRST_STOP_D1(Bit 6), nRST_STDY_D1(Bit 7),
+  *         FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]),
+  *         SECURITY(Bit 21), IO_HSLV (Bit 29) and SWAP_BANK_OPT(Bit 31).
+  *
+  * @retval HAL status
+  */
+#endif /*DUAL_CORE*/
+static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig)
+{
+  uint32_t optr_reg_val = 0;
+  uint32_t optr_reg_mask = 0;
+
+  /* Check the parameters */
+  assert_param(IS_OB_USER_TYPE(UserType));
+
+  if((UserType & OB_USER_IWDG1_SW) != 0U)
+  {
+    /* IWDG_HW option byte should be modified */
+    assert_param(IS_OB_IWDG1_SOURCE(UserConfig & FLASH_OPTSR_IWDG1_SW));
+
+    /* Set value and mask for IWDG_HW option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_IWDG1_SW);
+    optr_reg_mask |= FLASH_OPTSR_IWDG1_SW;
+  }
+#if defined(DUAL_CORE)
+  if((UserType & OB_USER_IWDG2_SW) != 0U)
+  {
+    /* IWDG2_SW option byte should be modified */
+    assert_param(IS_OB_IWDG2_SOURCE(UserConfig & FLASH_OPTSR_IWDG2_SW));
+
+    /* Set value and mask for IWDG2_SW option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_IWDG2_SW);
+    optr_reg_mask |= FLASH_OPTSR_IWDG2_SW;
+  }
+#endif /*DUAL_CORE*/
+  if((UserType & OB_USER_NRST_STOP_D1) != 0U)
+  {
+    /* NRST_STOP option byte should be modified */
+    assert_param(IS_OB_STOP_D1_RESET(UserConfig & FLASH_OPTSR_NRST_STOP_D1));
+
+    /* Set value and mask for NRST_STOP option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STOP_D1);
+    optr_reg_mask |= FLASH_OPTSR_NRST_STOP_D1;
+  }
+
+  if((UserType & OB_USER_NRST_STDBY_D1) != 0U)
+  {
+    /* NRST_STDBY option byte should be modified */
+    assert_param(IS_OB_STDBY_D1_RESET(UserConfig & FLASH_OPTSR_NRST_STBY_D1));
+
+    /* Set value and mask for NRST_STDBY option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STBY_D1);
+    optr_reg_mask |= FLASH_OPTSR_NRST_STBY_D1;
+  }
+
+  if((UserType & OB_USER_IWDG_STOP) != 0U)
+  {
+    /* IWDG_STOP option byte should be modified */
+    assert_param(IS_OB_USER_IWDG_STOP(UserConfig & FLASH_OPTSR_FZ_IWDG_STOP));
+
+    /* Set value and mask for IWDG_STOP option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_FZ_IWDG_STOP);
+    optr_reg_mask |= FLASH_OPTSR_FZ_IWDG_STOP;
+  }
+
+  if((UserType & OB_USER_IWDG_STDBY) != 0U)
+  {
+    /* IWDG_STDBY option byte should be modified */
+    assert_param(IS_OB_USER_IWDG_STDBY(UserConfig & FLASH_OPTSR_FZ_IWDG_SDBY));
+
+    /* Set value and mask for IWDG_STDBY option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_FZ_IWDG_SDBY);
+    optr_reg_mask |= FLASH_OPTSR_FZ_IWDG_SDBY;
+  }
+
+  if((UserType & OB_USER_ST_RAM_SIZE) != 0U)
+  {
+    /* ST_RAM_SIZE option byte should be modified */
+    assert_param(IS_OB_USER_ST_RAM_SIZE(UserConfig & FLASH_OPTSR_ST_RAM_SIZE));
+
+    /* Set value and mask for ST_RAM_SIZE option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_ST_RAM_SIZE);
+    optr_reg_mask |= FLASH_OPTSR_ST_RAM_SIZE;
+  }
+
+  if((UserType & OB_USER_SECURITY) != 0U)
+  {
+    /* SECURITY option byte should be modified */
+    assert_param(IS_OB_USER_SECURITY(UserConfig & FLASH_OPTSR_SECURITY));
+
+    /* Set value and mask for SECURITY option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_SECURITY);
+    optr_reg_mask |= FLASH_OPTSR_SECURITY;
+  }
+
+#if defined(DUAL_CORE)
+  if((UserType & OB_USER_BCM4) != 0U)
+  {
+    /* BCM4 option byte should be modified */
+    assert_param(IS_OB_USER_BCM4(UserConfig & FLASH_OPTSR_BCM4));
+
+    /* Set value and mask for BCM4 option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_BCM4);
+    optr_reg_mask |= FLASH_OPTSR_BCM4;
+  }
+
+  if((UserType & OB_USER_BCM7) != 0U)
+  {
+    /* BCM7 option byte should be modified */
+    assert_param(IS_OB_USER_BCM7(UserConfig & FLASH_OPTSR_BCM7));
+
+    /* Set value and mask for BCM7 option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_BCM7);
+    optr_reg_mask |= FLASH_OPTSR_BCM7;
+  }
+
+  if((UserType & OB_USER_NRST_STOP_D2) != 0U)
+  {
+    /* NRST_STOP option byte should be modified */
+    assert_param(IS_OB_STOP_D2_RESET(UserConfig & FLASH_OPTSR_NRST_STOP_D2));
+
+    /* Set value and mask for NRST_STOP option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STOP_D2);
+    optr_reg_mask |= FLASH_OPTSR_NRST_STOP_D2;
+  }
+
+  if((UserType & OB_USER_NRST_STDBY_D2) != 0U)
+  {
+    /* NRST_STDBY option byte should be modified */
+    assert_param(IS_OB_STDBY_D2_RESET(UserConfig & FLASH_OPTSR_NRST_STBY_D2));
+
+    /* Set value and mask for NRST_STDBY option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STBY_D2);
+    optr_reg_mask |= FLASH_OPTSR_NRST_STBY_D2;
+  }
+#endif /* DUAL_CORE */
+  if((UserType & OB_USER_SWAP_BANK) != 0U)
+  {
+    /* SWAP_BANK_OPT option byte should be modified */
+    assert_param(IS_OB_USER_SWAP_BANK(UserConfig & FLASH_OPTSR_SWAP_BANK_OPT));
+
+    /* Set value and mask for SWAP_BANK_OPT option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_SWAP_BANK_OPT);
+    optr_reg_mask |= FLASH_OPTSR_SWAP_BANK_OPT;
+  }
+
+  if((UserType & OB_USER_IOHSLV) != 0U)
+  {
+    /* IOHSLV_OPT option byte should be modified */
+    assert_param(IS_OB_USER_IOHSLV(UserConfig & FLASH_OPTSR_IO_HSLV));
+
+    /* Set value and mask for IOHSLV_OPT option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_IO_HSLV);
+    optr_reg_mask |= FLASH_OPTSR_IO_HSLV;
+  }
+
+#if defined (FLASH_OPTSR_VDDMMC_HSLV)
+  if((UserType & OB_USER_VDDMMC_HSLV) != 0U)
+  {
+    /* VDDMMC_HSLV option byte should be modified */
+    assert_param(IS_OB_USER_VDDMMC_HSLV(UserConfig & FLASH_OPTSR_VDDMMC_HSLV));
+
+    /* Set value and mask for VDDMMC_HSLV option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_VDDMMC_HSLV);
+    optr_reg_mask |= FLASH_OPTSR_VDDMMC_HSLV;
+  }
+#endif /* FLASH_OPTSR_VDDMMC_HSLV */
+
+  /* Configure the option bytes register */
+  MODIFY_REG(FLASH->OPTSR_PRG, optr_reg_mask, optr_reg_val);
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Return the FLASH User Option Byte value.
+  * @retval The FLASH User Option Bytes values
+  *         IWDG1_SW(Bit4), IWDG2_SW(Bit 5), nRST_STOP_D1(Bit 6), nRST_STDY_D1(Bit 7),
+  *         FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]),
+  *         SECURITY(Bit 21), BCM4(Bit 22), BCM7(Bit 23), nRST_STOP_D2(Bit 24),
+  *         nRST_STDY_D2(Bit 25), IO_HSLV (Bit 29) and SWAP_BANK_OPT(Bit 31).
+  */
+#else
+/**
+  * @brief  Return the FLASH User Option Byte value.
+  * @retval The FLASH User Option Bytes values
+  *         IWDG_SW(Bit4), nRST_STOP_D1(Bit 6), nRST_STDY_D1(Bit 7),
+  *         FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]),
+  *         SECURITY(Bit 21), IO_HSLV (Bit 29) and SWAP_BANK_OPT(Bit 31).
+  */
+#endif /*DUAL_CORE*/
+static uint32_t FLASH_OB_GetUser(void)
+{
+  uint32_t userConfig = READ_REG(FLASH->OPTSR_CUR);
+  userConfig &= (~(FLASH_OPTSR_BOR_LEV | FLASH_OPTSR_RDP));
+
+  return userConfig;
+}
+
+/**
+  * @brief  Configure the Proprietary code readout protection of the desired addresses
+  *
+  * @note   To configure the PCROP options, the option lock bit OPTLOCK must be
+  *         cleared with the call of the HAL_FLASH_OB_Unlock() function.
+  * @note   To validate the PCROP options, the option bytes must be reloaded
+  *         through the call of the HAL_FLASH_OB_Launch() function.
+  *
+  * @param  PCROPConfig specifies if the PCROP area for the given Bank shall be erased or not
+  *         when RDP level decreased from Level 1 to Level 0, or after a bank erase with protection removal
+  *         This parameter must be a value of @arg FLASHEx_OB_PCROP_RDP enumeration
+  *
+  * @param  PCROPStartAddr specifies the start address of the Proprietary code readout protection
+  *          This parameter can be an address between begin and end of the bank
+  *
+  * @param  PCROPEndAddr specifies the end address of the Proprietary code readout protection
+  *          This parameter can be an address between PCROPStartAddr and end of the bank
+  *
+  * @param  Banks the specific bank to apply PCROP protection
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: PCROP on specified bank1 area
+  *            @arg FLASH_BANK_2: PCROP on specified bank2 area
+  *            @arg FLASH_BANK_BOTH: PCROP on specified bank1 and bank2 area (same config will be applied on both banks)
+  *
+  * @retval None
+  */
+static void FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr, uint32_t Banks)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_BANK(Banks));
+  assert_param(IS_OB_PCROP_RDP(PCROPConfig));
+
+  if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
+  {
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(PCROPStartAddr));
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(PCROPEndAddr));
+
+    /* Configure the Proprietary code readout protection */
+    FLASH->PRAR_PRG1 = ((PCROPStartAddr - FLASH_BANK1_BASE) >> 8)                                 | \
+                       (((PCROPEndAddr - FLASH_BANK1_BASE) >> 8) << FLASH_PRAR_PROT_AREA_END_Pos) | \
+                       PCROPConfig;
+  }
+
+  if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
+  {
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(PCROPStartAddr));
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(PCROPEndAddr));
+
+    /* Configure the Proprietary code readout protection */
+    FLASH->PRAR_PRG2 = ((PCROPStartAddr - FLASH_BANK2_BASE) >> 8)                                 | \
+                       (((PCROPEndAddr - FLASH_BANK2_BASE) >> 8) << FLASH_PRAR_PROT_AREA_END_Pos) | \
+                       PCROPConfig;
+  }
+}
+
+/**
+  * @brief  Get the Proprietary code readout protection configuration on a given Bank
+  *
+  * @param  PCROPConfig indicates if the PCROP area for the given Bank shall be erased or not
+  *         when RDP level decreased from Level 1 to Level 0 or after a bank erase with protection removal
+  *
+  * @param  PCROPStartAddr gives the start address of the Proprietary code readout protection of the bank
+  *
+  * @param  PCROPEndAddr gives the end address of the Proprietary code readout protection of the bank
+  *
+  * @param  Bank the specific bank to apply PCROP protection
+  *          This parameter can be exclusively one of the following values:
+  *            @arg FLASH_BANK_1: PCROP on specified bank1 area
+  *            @arg FLASH_BANK_2: PCROP on specified bank2 area
+  *            @arg FLASH_BANK_BOTH: is  not allowed here
+  *
+  * @retval None
+  */
+static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROPStartAddr, uint32_t *PCROPEndAddr, uint32_t Bank)
+{
+  uint32_t regvalue = 0;
+  uint32_t bankBase = 0;
+
+  if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_1)
+  {
+    regvalue = FLASH->PRAR_CUR1;
+    bankBase = FLASH_BANK1_BASE;
+  }
+
+  if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_2)
+  {
+    regvalue = FLASH->PRAR_CUR2;
+    bankBase = FLASH_BANK2_BASE;
+  }
+
+  (*PCROPConfig) =  (regvalue & FLASH_PRAR_DMEP);
+
+  (*PCROPStartAddr) = ((regvalue & FLASH_PRAR_PROT_AREA_START) << 8) + bankBase;
+  (*PCROPEndAddr) = (regvalue & FLASH_PRAR_PROT_AREA_END) >> FLASH_PRAR_PROT_AREA_END_Pos;
+  (*PCROPEndAddr) = ((*PCROPEndAddr) << 8) + bankBase;
+}
+
+/**
+  * @brief  Set the BOR Level.
+  * @param  Level specifies the Option Bytes BOR Reset Level.
+  *          This parameter can be one of the following values:
+  *            @arg OB_BOR_LEVEL0: Reset level threshold is set to 1.6V
+  *            @arg OB_BOR_LEVEL1: Reset level threshold is set to 2.1V
+  *            @arg OB_BOR_LEVEL2: Reset level threshold is set to 2.4V
+  *            @arg OB_BOR_LEVEL3: Reset level threshold is set to 2.7V
+  * @retval None
+  */
+static void FLASH_OB_BOR_LevelConfig(uint32_t Level)
+{
+  assert_param(IS_OB_BOR_LEVEL(Level));
+
+  /* Configure BOR_LEV option byte */
+  MODIFY_REG(FLASH->OPTSR_PRG, FLASH_OPTSR_BOR_LEV, Level);
+}
+
+/**
+  * @brief  Get the BOR Level.
+  * @retval The Option Bytes BOR Reset Level.
+  *            This parameter can be one of the following values:
+  *            @arg OB_BOR_LEVEL0: Reset level threshold is set to 1.6V
+  *            @arg OB_BOR_LEVEL1: Reset level threshold is set to 2.1V
+  *            @arg OB_BOR_LEVEL2: Reset level threshold is set to 2.4V
+  *            @arg OB_BOR_LEVEL3: Reset level threshold is set to 2.7V
+  */
+static uint32_t FLASH_OB_GetBOR(void)
+{
+  return (FLASH->OPTSR_CUR & FLASH_OPTSR_BOR_LEV);
+}
+
+/**
+  * @brief  Set Boot address
+  * @param  BootOption Boot address option byte to be programmed,
+  *                     This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION
+                        (OB_BOOT_ADD0, OB_BOOT_ADD1 or OB_BOOT_ADD_BOTH)
+  *
+  * @param  BootAddress0 Specifies the Boot Address 0
+  * @param  BootAddress1 Specifies the Boot Address 1
+  * @retval HAL Status
+  */
+static void FLASH_OB_BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1)
+{
+  /* Check the parameters */
+  assert_param(IS_OB_BOOT_ADD_OPTION(BootOption));
+
+  if((BootOption & OB_BOOT_ADD0) == OB_BOOT_ADD0)
+  {
+    /* Check the parameters */
+    assert_param(IS_BOOT_ADDRESS(BootAddress0));
+
+    /* Configure CM7 BOOT ADD0 */
+#if defined(DUAL_CORE)
+    MODIFY_REG(FLASH->BOOT7_PRG, FLASH_BOOT7_BCM7_ADD0, (BootAddress0 >> 16));
+#else /* Single Core*/
+    MODIFY_REG(FLASH->BOOT_PRG, FLASH_BOOT_ADD0, (BootAddress0 >> 16));
+#endif /* DUAL_CORE */
+  }
+
+  if((BootOption & OB_BOOT_ADD1) == OB_BOOT_ADD1)
+  {
+    /* Check the parameters */
+    assert_param(IS_BOOT_ADDRESS(BootAddress1));
+
+    /* Configure CM7 BOOT ADD1 */
+#if defined(DUAL_CORE)
+    MODIFY_REG(FLASH->BOOT7_PRG, FLASH_BOOT7_BCM7_ADD1, BootAddress1);
+#else /* Single Core*/
+    MODIFY_REG(FLASH->BOOT_PRG, FLASH_BOOT_ADD1, BootAddress1);
+#endif /* DUAL_CORE */
+  }
+}
+
+/**
+  * @brief  Get Boot address
+  * @param  BootAddress0 Specifies the Boot Address 0.
+  * @param  BootAddress1 Specifies the Boot Address 1.
+  * @retval HAL Status
+  */
+static void FLASH_OB_GetBootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1)
+{
+  uint32_t regvalue;
+
+#if defined(DUAL_CORE)
+  regvalue = FLASH->BOOT7_CUR;
+
+  (*BootAddress0) = (regvalue & FLASH_BOOT7_BCM7_ADD0) << 16;
+  (*BootAddress1) = (regvalue & FLASH_BOOT7_BCM7_ADD1);
+#else /* Single Core */
+  regvalue = FLASH->BOOT_CUR;
+
+  (*BootAddress0) = (regvalue & FLASH_BOOT_ADD0) << 16;
+  (*BootAddress1) = (regvalue & FLASH_BOOT_ADD1);
+#endif /* DUAL_CORE */
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Set CM4 Boot address
+  * @param  BootOption Boot address option byte to be programmed,
+  *                     This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION
+                        (OB_BOOT_ADD0, OB_BOOT_ADD1 or OB_BOOT_ADD_BOTH)
+  *
+  * @param  BootAddress0 Specifies the CM4 Boot Address 0.
+  * @param  BootAddress1 Specifies the CM4 Boot Address 1.
+  * @retval HAL Status
+  */
+static void FLASH_OB_CM4BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1)
+{
+  /* Check the parameters */
+  assert_param(IS_OB_BOOT_ADD_OPTION(BootOption));
+
+  if((BootOption & OB_BOOT_ADD0) == OB_BOOT_ADD0)
+  {
+    /* Check the parameters */
+    assert_param(IS_BOOT_ADDRESS(BootAddress0));
+
+    /* Configure CM4 BOOT ADD0 */
+    MODIFY_REG(FLASH->BOOT4_PRG, FLASH_BOOT4_BCM4_ADD0, (BootAddress0 >> 16));
+
+  }
+
+  if((BootOption & OB_BOOT_ADD1) == OB_BOOT_ADD1)
+  {
+    /* Check the parameters */
+    assert_param(IS_BOOT_ADDRESS(BootAddress1));
+
+    /* Configure CM4 BOOT ADD1 */
+    MODIFY_REG(FLASH->BOOT4_PRG, FLASH_BOOT4_BCM4_ADD1, BootAddress1);
+  }
+}
+
+/**
+  * @brief  Get CM4 Boot address
+  * @param  BootAddress0 Specifies the CM4 Boot Address 0.
+  * @param  BootAddress1 Specifies the CM4 Boot Address 1.
+  * @retval HAL Status
+  */
+static void FLASH_OB_GetCM4BootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1)
+{
+  uint32_t regvalue;
+
+  regvalue = FLASH->BOOT4_CUR;
+
+  (*BootAddress0) = (regvalue & FLASH_BOOT4_BCM4_ADD0) << 16;
+  (*BootAddress1) = (regvalue & FLASH_BOOT4_BCM4_ADD1);
+}
+#endif /*DUAL_CORE*/
+
+/**
+  * @brief  Set secure area configuration
+  * @param  SecureAreaConfig specify if the secure area will be deleted or not
+  *         when RDP level decreased from Level 1 to Level 0 or during a mass erase.
+  *
+  * @param  SecureAreaStartAddr Specifies the secure area start address
+  * @param  SecureAreaEndAddr Specifies the secure area end address
+  * @param  Banks the specific bank to apply Security protection
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: Secure area on specified bank1 area
+  *            @arg FLASH_BANK_2: Secure area on specified bank2 area
+  *            @arg FLASH_BANK_BOTH: Secure area on specified bank1 and bank2 area (same config will be applied on both banks)
+  * @retval None
+  */
+static void FLASH_OB_SecureAreaConfig(uint32_t SecureAreaConfig, uint32_t SecureAreaStartAddr, uint32_t SecureAreaEndAddr, uint32_t Banks)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_BANK(Banks));
+  assert_param(IS_OB_SECURE_RDP(SecureAreaConfig));
+
+  if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
+  {
+    /* Check the parameters */
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(SecureAreaStartAddr));
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(SecureAreaEndAddr));
+
+    /* Configure the secure area */
+    FLASH->SCAR_PRG1 = ((SecureAreaStartAddr - FLASH_BANK1_BASE) >> 8)                                | \
+                       (((SecureAreaEndAddr - FLASH_BANK1_BASE) >> 8) << FLASH_SCAR_SEC_AREA_END_Pos) | \
+                       (SecureAreaConfig & FLASH_SCAR_DMES);
+  }
+
+  if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
+  {
+    /* Check the parameters */
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(SecureAreaStartAddr));
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(SecureAreaEndAddr));
+
+    /* Configure the secure area */
+    FLASH->SCAR_PRG2 = ((SecureAreaStartAddr - FLASH_BANK2_BASE) >> 8)                                | \
+                       (((SecureAreaEndAddr - FLASH_BANK2_BASE) >> 8) << FLASH_SCAR_SEC_AREA_END_Pos) | \
+                       (SecureAreaConfig & FLASH_SCAR_DMES);
+  }
+}
+
+/**
+  * @brief  Get secure area configuration
+  * @param  SecureAreaConfig indicates if the secure area will be deleted or not
+  *         when RDP level decreased from Level 1 to Level 0 or during a mass erase.
+  * @param  SecureAreaStartAddr gives the secure area start address
+  * @param  SecureAreaEndAddr gives the secure area end address
+  * @param  Bank Specifies the Bank
+  * @retval None
+  */
+static void FLASH_OB_GetSecureArea(uint32_t *SecureAreaConfig, uint32_t *SecureAreaStartAddr, uint32_t *SecureAreaEndAddr, uint32_t Bank)
+{
+  uint32_t regvalue = 0;
+  uint32_t bankBase = 0;
+
+  /* Check Bank parameter value */
+  if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_1)
+  {
+    regvalue = FLASH->SCAR_CUR1;
+    bankBase = FLASH_BANK1_BASE;
+  }
+
+  if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_2)
+  {
+    regvalue = FLASH->SCAR_CUR2;
+    bankBase = FLASH_BANK2_BASE;
+  }
+
+  /* Get the secure area settings */
+  (*SecureAreaConfig) = (regvalue & FLASH_SCAR_DMES);
+  (*SecureAreaStartAddr) = ((regvalue & FLASH_SCAR_SEC_AREA_START) << 8) + bankBase;
+  (*SecureAreaEndAddr) = (regvalue & FLASH_SCAR_SEC_AREA_END) >> FLASH_SCAR_SEC_AREA_END_Pos;
+  (*SecureAreaEndAddr) = ((*SecureAreaEndAddr) << 8) + bankBase;
+}
+
+/**
+  * @brief  Add a CRC sector to the list of sectors on which the CRC will be calculated
+  * @param  Sector Specifies the CRC sector number
+  * @param  Bank Specifies the Bank
+  * @retval None
+  */
+static void FLASH_CRC_AddSector(uint32_t Sector, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_SECTOR(Sector));
+
+  if (Bank == FLASH_BANK_1)
+  {
+    /* Clear CRC sector */
+    FLASH->CRCCR1 &= (~FLASH_CRCCR_CRC_SECT);
+
+    /* Select CRC Sector and activate ADD_SECT bit */
+    FLASH->CRCCR1 |= Sector | FLASH_CRCCR_ADD_SECT;
+  }
+  else
+  {
+    /* Clear CRC sector */
+    FLASH->CRCCR2 &= (~FLASH_CRCCR_CRC_SECT);
+
+    /* Select CRC Sector and activate ADD_SECT bit */
+    FLASH->CRCCR2 |= Sector | FLASH_CRCCR_ADD_SECT;
+  }
+}
+
+/**
+  * @brief  Select CRC start and end memory addresses on which the CRC will be calculated
+  * @param  CRCStartAddr Specifies the CRC start address
+  * @param  CRCEndAddr Specifies the CRC end address
+  * @param  Bank Specifies the Bank
+  * @retval None
+  */
+static void FLASH_CRC_SelectAddress(uint32_t CRCStartAddr, uint32_t CRCEndAddr, uint32_t Bank)
+{
+  if (Bank == FLASH_BANK_1)
+  {
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(CRCStartAddr));
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(CRCEndAddr));
+
+    /* Write CRC Start and End addresses */
+    FLASH->CRCSADD1 = CRCStartAddr;
+    FLASH->CRCEADD1 = CRCEndAddr;
+  }
+  else
+  {
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(CRCStartAddr));
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(CRCEndAddr));
+
+    /* Write CRC Start and End addresses */
+    FLASH->CRCSADD2 = CRCStartAddr;
+    FLASH->CRCEADD2 = CRCEndAddr;
+  }
+}
+/**
+  * @}
+  */
+
+#if defined (FLASH_OTPBL_LOCKBL)
+/**
+  * @brief  Configure the OTP Block Lock.
+  * @param  OTP_Block specifies the OTP Block to lock.
+  *         This parameter can be a value of @ref FLASHEx_OTP_Blocks
+  * @retval None
+  */
+static void FLASH_OB_OTP_LockConfig(uint32_t OTP_Block)
+{
+  /* Check the parameters */
+  assert_param(IS_OTP_BLOCK(OTP_Block));
+
+  /* Configure the OTP Block lock in the option bytes register */
+  FLASH->OTPBL_PRG |= (OTP_Block & FLASH_OTPBL_LOCKBL);
+}
+
+/**
+  * @brief  Get the OTP Block Lock.
+  * @retval OTP_Block specifies the OTP Block to lock.
+  *         This return value can be a value of @ref FLASHEx_OTP_Blocks
+  */
+static uint32_t FLASH_OB_OTP_GetLock(void)
+{
+  return (FLASH->OTPBL_CUR);
+}
+#endif /* FLASH_OTPBL_LOCKBL */
+
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c
new file mode 100644
index 00000000..13dcc40d
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c
@@ -0,0 +1,560 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_gpio.c
+  * @author  MCD Application Team
+  * @brief   GPIO HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *
+  @verbatim
+  ==============================================================================
+                    ##### GPIO Peripheral features #####
+  ==============================================================================
+  [..]
+    (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
+        configured by software in several modes:
+        (++) Input mode
+        (++) Analog mode
+        (++) Output mode
+        (++) Alternate function mode
+        (++) External interrupt/event lines
+
+    (+) During and just after reset, the alternate functions and external interrupt
+        lines are not active and the I/O ports are configured in input floating mode.
+
+    (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
+        activated or not.
+
+    (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
+        type and the IO speed can be selected depending on the VDD value.
+
+    (+) The microcontroller IO pins are connected to onboard peripherals/modules through a
+        multiplexer that allows only one peripheral alternate function (AF) connected
+       to an IO pin at a time. In this way, there can be no conflict between peripherals
+       sharing the same IO pin.
+
+    (+) All ports have external interrupt/event capability. To use external interrupt
+        lines, the port must be configured in input mode. All available GPIO pins are
+        connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
+
+  The external interrupt/event controller consists of up to 23 edge detectors
+        (16 lines are connected to GPIO) for generating event/interrupt requests (each
+        input line can be independently configured to select the type (interrupt or event)
+        and the corresponding trigger event (rising or falling or both). Each line can
+        also be masked independently.
+
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
+
+    (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
+        (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
+        (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
+             structure.
+        (++) In case of Output or alternate function mode selection: the speed is
+             configured through "Speed" member from GPIO_InitTypeDef structure.
+        (++) In alternate mode is selection, the alternate function connected to the IO
+             is configured through "Alternate" member from GPIO_InitTypeDef structure.
+        (++) Analog mode is required when a pin is to be used as ADC channel
+             or DAC output.
+        (++) In case of external interrupt/event selection the "Mode" member from
+             GPIO_InitTypeDef structure select the type (interrupt or event) and
+             the corresponding trigger event (rising or falling or both).
+
+    (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
+        mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
+        HAL_NVIC_EnableIRQ().
+
+    (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
+
+    (#) To set/reset the level of a pin configured in output mode use
+        HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
+
+   (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
+
+
+    (#) During and just after reset, the alternate functions are not
+        active and the GPIO pins are configured in input floating mode (except JTAG
+        pins).
+
+    (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
+        (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
+        priority over the GPIO function.
+
+    (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
+        general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
+        The HSE has priority over the GPIO function.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup GPIO  GPIO
+  * @brief GPIO HAL module driver
+  * @{
+  */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines ------------------------------------------------------------*/
+/** @addtogroup GPIO_Private_Constants GPIO Private Constants
+  * @{
+  */
+#define GPIO_MODE             (0x00000003U)
+#define ANALOG_MODE           (0x00000008U)
+#define EXTI_MODE             (0x10000000U)
+#define GPIO_MODE_IT          (0x00010000U)
+#define GPIO_MODE_EVT         (0x00020000U)
+#define RISING_EDGE           (0x00100000U)
+#define FALLING_EDGE          (0x00200000U)
+#define GPIO_OUTPUT_TYPE      (0x00000010U)
+
+#if defined(DUAL_CORE)
+#define EXTI_CPU1             (0x01000000U)
+#define EXTI_CPU2             (0x02000000U)
+#endif /*DUAL_CORE*/
+#define GPIO_NUMBER           (16U)
+/**
+  * @}
+  */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
+  * @{
+  */
+
+/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+  [..]
+    This section provides functions allowing to initialize and de-initialize the GPIOs
+    to be ready for use.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
+  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral.
+  * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
+  *         the configuration information for the specified GPIO peripheral.
+  * @retval None
+  */
+void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
+{
+  uint32_t position = 0x00U;
+  uint32_t iocurrent;
+  uint32_t temp;
+  EXTI_Core_TypeDef *EXTI_CurrentCPU;
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */
+#else
+  EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */
+#endif
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
+  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
+  assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
+
+  /* Configure the port pins */
+  while (((GPIO_Init->Pin) >> position) != 0x00U)
+  {
+    /* Get current io position */
+    iocurrent = (GPIO_Init->Pin) & (1UL << position);
+
+    if (iocurrent != 0x00U)
+    {
+      /*--------------------- GPIO Mode Configuration ------------------------*/
+      /* In case of Output or Alternate function mode selection */
+      if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
+          (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+      {
+        /* Check the Speed parameter */
+        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+        /* Configure the IO Speed */
+        temp = GPIOx->OSPEEDR;
+        temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
+        temp |= (GPIO_Init->Speed << (position * 2U));
+        GPIOx->OSPEEDR = temp;
+
+        /* Configure the IO Output Type */
+        temp = GPIOx->OTYPER;
+        temp &= ~(GPIO_OTYPER_OT0 << position) ;
+        temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
+        GPIOx->OTYPER = temp;
+      }
+
+      /* Activate the Pull-up or Pull down resistor for the current IO */
+      temp = GPIOx->PUPDR;
+      temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
+      temp |= ((GPIO_Init->Pull) << (position * 2U));
+      GPIOx->PUPDR = temp;
+
+      /* In case of Alternate function mode selection */
+      if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+      {
+        /* Check the Alternate function parameters */
+        assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
+        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
+
+        /* Configure Alternate function mapped with the current IO */
+        temp = GPIOx->AFR[position >> 3U];
+        temp &= ~(0xFU << ((position & 0x07U) * 4U));
+        temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
+        GPIOx->AFR[position >> 3U] = temp;
+      }
+
+      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+      temp = GPIOx->MODER;
+      temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
+      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
+      GPIOx->MODER = temp;
+
+      /*--------------------- EXTI Mode Configuration ------------------------*/
+      /* Configure the External Interrupt or event for the current IO */
+      if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
+      {
+        /* Enable SYSCFG Clock */
+        __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+        temp = SYSCFG->EXTICR[position >> 2U];
+        temp &= ~(0x0FUL << (4U * (position & 0x03U)));
+        temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
+        SYSCFG->EXTICR[position >> 2U] = temp;
+
+        /* Clear EXTI line configuration */
+        temp = EXTI_CurrentCPU->IMR1;
+        temp &= ~(iocurrent);
+        if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
+        {
+          temp |= iocurrent;
+        }
+        EXTI_CurrentCPU->IMR1 = temp;
+
+        temp = EXTI_CurrentCPU->EMR1;
+        temp &= ~(iocurrent);
+        if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
+        {
+          temp |= iocurrent;
+        }
+        EXTI_CurrentCPU->EMR1 = temp;
+
+        /* Clear Rising Falling edge configuration */
+        temp = EXTI->RTSR1;
+        temp &= ~(iocurrent);
+        if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
+        {
+          temp |= iocurrent;
+        }
+        EXTI->RTSR1 = temp;
+
+        temp = EXTI->FTSR1;
+        temp &= ~(iocurrent);
+        if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
+        {
+          temp |= iocurrent;
+        }
+        EXTI->FTSR1 = temp;
+      }
+    }
+
+    position++;
+  }
+}
+
+/**
+  * @brief  De-initializes the GPIOx peripheral registers to their default reset values.
+  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bit to be written.
+  *          This parameter can be one of GPIO_PIN_x where x can be (0..15).
+  * @retval None
+  */
+void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
+{
+  uint32_t position = 0x00U;
+  uint32_t iocurrent;
+  uint32_t tmp;
+  EXTI_Core_TypeDef *EXTI_CurrentCPU;
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */
+#else
+  EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */
+#endif
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  /* Configure the port pins */
+  while ((GPIO_Pin >> position) != 0x00U)
+  {
+    /* Get current io position */
+    iocurrent = GPIO_Pin & (1UL << position) ;
+
+    if (iocurrent != 0x00U)
+    {
+      /*------------------------- EXTI Mode Configuration --------------------*/
+      /* Clear the External Interrupt or Event for the current IO */
+      tmp = SYSCFG->EXTICR[position >> 2U];
+      tmp &= (0x0FUL << (4U * (position & 0x03U)));
+      if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
+      {
+        /* Clear EXTI line configuration for Current CPU */
+        EXTI_CurrentCPU->IMR1 &= ~(iocurrent);
+        EXTI_CurrentCPU->EMR1 &= ~(iocurrent);
+
+        /* Clear Rising Falling edge configuration */
+        EXTI->RTSR1 &= ~(iocurrent);
+        EXTI->FTSR1 &= ~(iocurrent);
+
+        tmp = 0x0FUL << (4U * (position & 0x03U));
+        SYSCFG->EXTICR[position >> 2U] &= ~tmp;
+      }
+
+      /*------------------------- GPIO Mode Configuration --------------------*/
+      /* Configure IO in Analog Mode */
+      GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2U));
+
+      /* Configure the default Alternate Function in current IO */
+      GPIOx->AFR[position >> 3U] &= ~(0xFU << ((position & 0x07U) * 4U)) ;
+
+      /* Deactivate the Pull-up and Pull-down resistor for the current IO */
+      GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
+
+      /* Configure the default value IO Output Type */
+      GPIOx->OTYPER  &= ~(GPIO_OTYPER_OT0 << position) ;
+
+      /* Configure the default value for IO Speed */
+      GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
+    }
+
+    position++;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
+ *  @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
+ *
+@verbatim
+ ===============================================================================
+                       ##### IO operation functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Reads the specified input port pin.
+  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bit to read.
+  *         This parameter can be GPIO_PIN_x where x can be (0..15).
+  * @retval The input port pin value.
+  */
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+  GPIO_PinState bitstatus;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  if ((GPIOx->IDR & GPIO_Pin) != 0x00U)
+  {
+    bitstatus = GPIO_PIN_SET;
+  }
+  else
+  {
+    bitstatus = GPIO_PIN_RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Sets or clears the selected data port bit.
+  *
+  * @note   This function uses GPIOx_BSRR register to allow atomic read/modify
+  *         accesses. In this way, there is no risk of an IRQ occurring between
+  *         the read and the modify access.
+  *
+  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bit to be written.
+  *          This parameter can be one of GPIO_PIN_x where x can be (0..15).
+  * @param  PinState: specifies the value to be written to the selected bit.
+  *          This parameter can be one of the GPIO_PinState enum values:
+  *            @arg GPIO_PIN_RESET: to clear the port pin
+  *            @arg GPIO_PIN_SET: to set the port pin
+  * @retval None
+  */
+void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+  assert_param(IS_GPIO_PIN_ACTION(PinState));
+
+  if (PinState != GPIO_PIN_RESET)
+  {
+    GPIOx->BSRR = GPIO_Pin;
+  }
+  else
+  {
+    GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
+  }
+}
+
+/**
+  * @brief  Toggles the specified GPIO pins.
+  * @param  GPIOx: Where x can be (A..K) to select the GPIO peripheral.
+  * @param  GPIO_Pin: Specifies the pins to be toggled.
+  * @retval None
+  */
+void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  if ((GPIOx->ODR & GPIO_Pin) == GPIO_Pin)
+  {
+    GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
+  }
+  else
+  {
+    GPIOx->BSRR = GPIO_Pin;
+  }
+}
+
+/**
+  * @brief  Locks GPIO Pins configuration registers.
+  * @note   The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
+  *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
+  * @note   The configuration of the locked GPIO pins can no longer be modified
+  *         until the next reset.
+  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32H7 family
+  * @param  GPIO_Pin: specifies the port bit to be locked.
+  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+  __IO uint32_t tmp = GPIO_LCKR_LCKK;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  /* Apply lock key write sequence */
+  tmp |= GPIO_Pin;
+  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+  GPIOx->LCKR = tmp;
+  /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
+  GPIOx->LCKR = GPIO_Pin;
+  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+  GPIOx->LCKR = tmp;
+  /* Read LCKK register. This read is mandatory to complete key lock sequence*/
+  tmp = GPIOx->LCKR;
+
+  /* read again in order to confirm lock is active */
+  if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00U)
+  {
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Handle EXTI interrupt request.
+  * @param  GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
+  * @retval None
+  */
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
+{
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  if (__HAL_GPIO_EXTID2_GET_IT(GPIO_Pin) != 0x00U)
+  {
+    __HAL_GPIO_EXTID2_CLEAR_IT(GPIO_Pin);
+    HAL_GPIO_EXTI_Callback(GPIO_Pin);
+  }
+#else
+  /* EXTI line interrupt detected */
+  if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00U)
+  {
+    __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
+    HAL_GPIO_EXTI_Callback(GPIO_Pin);
+  }
+#endif
+}
+
+/**
+  * @brief  EXTI line detection callback.
+  * @param  GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
+  * @retval None
+  */
+__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(GPIO_Pin);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+           the HAL_GPIO_EXTI_Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+#endif /* HAL_GPIO_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c
new file mode 100644
index 00000000..1fab0cef
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c
@@ -0,0 +1,441 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_hsem.c
+  * @author  MCD Application Team
+  * @brief   HSEM HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the semaphore peripheral:
+  *           + Semaphore Take function (2-Step Procedure) , non blocking
+  *           + Semaphore FastTake function (1-Step Procedure) , non blocking
+  *           + Semaphore Status check
+  *           + Semaphore Clear Key Set and Get
+  *           + Release and release all functions
+  *           + Semaphore notification enabling and disabling and callnack functions
+  *           + IRQ handler management
+  *
+  *
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+      (#)Take a semaphore In 2-Step mode Using function HAL_HSEM_Take. This function takes as parameters :
+           (++) the semaphore ID from 0 to 31
+           (++) the process ID from 0 to 255
+      (#) Fast Take semaphore In 1-Step mode Using function HAL_HSEM_FastTake. This function takes as parameter :
+           (++) the semaphore ID from 0_ID to 31. Note that the process ID value is implicitly assumed as zero
+      (#) Check if a semaphore is Taken using function HAL_HSEM_IsSemTaken. This function takes as parameter :
+          (++) the semaphore ID from 0_ID to 31
+          (++) It returns 1 if the given semaphore is taken otherwise (Free) zero
+      (#)Release a semaphore using function with HAL_HSEM_Release. This function takes as parameters :
+           (++) the semaphore ID from 0 to 31
+           (++) the process ID from 0 to 255:
+           (++) Note: If ProcessID and MasterID match, semaphore is freed, and an interrupt
+         may be generated when enabled (notification activated). If ProcessID or MasterID does not match,
+         semaphore remains taken (locked)
+
+      (#)Release all semaphores at once taken by a given Master using function HAL_HSEM_Release_All
+          This function takes as parameters :
+           (++) the Release Key (value from 0 to 0xFFFF) can be Set or Get respectively by
+              HAL_HSEM_SetClearKey() or HAL_HSEM_GetClearKey functions
+           (++) the Master ID:
+           (++) Note: If the Key and MasterID match, all semaphores taken by the given CPU that corresponds
+           to MasterID  will be freed, and an interrupt may be generated when enabled (notification activated). If the
+           Key or the MasterID doesn't match, semaphores remains taken (locked)
+
+      (#)Semaphores Release all key functions:
+         (++)  HAL_HSEM_SetClearKey() to set semaphore release all Key
+         (++)  HAL_HSEM_GetClearKey() to get release all Key
+      (#)Semaphores notification functions :
+         (++)  HAL_HSEM_ActivateNotification to activate a notification callback on
+               a given semaphores Mask (bitfield). When one or more semaphores defined by the mask are released
+               the callback HAL_HSEM_FreeCallback will be asserted giving as parameters a mask of the released
+               semaphores (bitfield).
+
+         (++)  HAL_HSEM_DeactivateNotification to deactivate the notification of a given semaphores Mask (bitfield).
+         (++) See the description of the macro __HAL_HSEM_SEMID_TO_MASK to check how to calculate a semaphore mask
+                Used by the notification functions
+     *** HSEM HAL driver macros list ***
+     =============================================
+     [..] Below the list of most used macros in HSEM HAL driver.
+
+      (+) __HAL_HSEM_SEMID_TO_MASK: Helper macro to convert a Semaphore ID to a Mask.
+      [..] Example of use :
+      [..] mask = __HAL_HSEM_SEMID_TO_MASK(8)  |  __HAL_HSEM_SEMID_TO_MASK(21) | __HAL_HSEM_SEMID_TO_MASK(25).
+      [..] All next macros take as parameter a semaphore Mask (bitfiled) that can be constructed using  __HAL_HSEM_SEMID_TO_MASK as the above example.
+      (+) __HAL_HSEM_ENABLE_IT: Enable the specified semaphores Mask interrupts.
+      (+) __HAL_HSEM_DISABLE_IT: Disable the specified semaphores Mask interrupts.
+      (+) __HAL_HSEM_GET_IT: Checks whether the specified semaphore interrupt has occurred or not.
+      (+) __HAL_HSEM_GET_FLAG: Get the semaphores status release flags.
+      (+) __HAL_HSEM_CLEAR_FLAG: Clear the semaphores status release flags.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup HSEM HSEM
+  * @brief HSEM HAL module driver
+  * @{
+  */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#if defined(DUAL_CORE)
+#ifndef HSEM_R_MASTERID
+#define HSEM_R_MASTERID HSEM_R_COREID
+#endif
+
+#ifndef HSEM_RLR_MASTERID
+#define HSEM_RLR_MASTERID HSEM_RLR_COREID
+#endif
+
+#ifndef HSEM_CR_MASTERID
+#define HSEM_CR_MASTERID HSEM_CR_COREID
+#endif
+#endif /* DUAL_CORE */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup HSEM_Exported_Functions  HSEM Exported Functions
+  * @{
+  */
+
+/** @defgroup HSEM_Exported_Functions_Group1 Take and Release functions
+  *  @brief    HSEM Take and Release functions
+  *
+@verbatim
+ ==============================================================================
+              ##### HSEM Take and Release functions #####
+ ==============================================================================
+[..] This section provides functions allowing to:
+      (+) Take a semaphore with 2 Step method
+      (+) Fast Take a semaphore with 1 Step method
+      (+) Check semaphore state Taken or not
+      (+) Release a semaphore
+      (+) Release all semaphore at once
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Take a semaphore in 2 Step mode.
+  * @param  SemID: semaphore ID from 0 to 31
+  * @param  ProcessID: Process ID from 0 to 255
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID)
+{
+  /* Check the parameters */
+  assert_param(IS_HSEM_SEMID(SemID));
+  assert_param(IS_HSEM_PROCESSID(ProcessID));
+
+#if  USE_MULTI_CORE_SHARED_CODE != 0U
+  /* First step  write R register with MasterID, processID and take bit=1*/
+  HSEM->R[SemID] = ((ProcessID & HSEM_R_PROCID) | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID) | HSEM_R_LOCK);
+
+  /* second step : read the R register . Take achieved if MasterID and processID match and take bit set to 1 */
+  if (HSEM->R[SemID] == ((ProcessID & HSEM_R_PROCID) | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID) | HSEM_R_LOCK))
+  {
+    /*take success when MasterID and ProcessID match and take bit set*/
+    return HAL_OK;
+  }
+#else
+  /* First step  write R register with MasterID, processID and take bit=1*/
+  HSEM->R[SemID] = (ProcessID | HSEM_CR_COREID_CURRENT | HSEM_R_LOCK);
+
+  /* second step : read the R register . Take achieved if MasterID and processID match and take bit set to 1 */
+  if (HSEM->R[SemID] == (ProcessID | HSEM_CR_COREID_CURRENT | HSEM_R_LOCK))
+  {
+    /*take success when MasterID and ProcessID match and take bit set*/
+    return HAL_OK;
+  }
+#endif
+
+  /* Semaphore take fails*/
+  return HAL_ERROR;
+}
+
+/**
+  * @brief  Fast Take a semaphore with 1 Step mode.
+  * @param  SemID: semaphore ID from 0 to 31
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HSEM_FastTake(uint32_t SemID)
+{
+  /* Check the parameters */
+  assert_param(IS_HSEM_SEMID(SemID));
+
+#if  USE_MULTI_CORE_SHARED_CODE != 0U
+  /* Read the RLR register to take the semaphore */
+  if (HSEM->RLR[SemID] == (((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_RLR_MASTERID) | HSEM_RLR_LOCK))
+  {
+    /*take success when MasterID match and take bit set*/
+    return HAL_OK;
+  }
+#else
+  /* Read the RLR register to take the semaphore */
+  if (HSEM->RLR[SemID] == (HSEM_CR_COREID_CURRENT | HSEM_RLR_LOCK))
+  {
+    /*take success when MasterID match and take bit set*/
+    return HAL_OK;
+  }
+#endif
+
+  /* Semaphore take fails */
+  return HAL_ERROR;
+}
+/**
+  * @brief  Check semaphore state Taken or not.
+  * @param  SemID: semaphore ID
+  * @retval HAL HSEM state
+  */
+uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID)
+{
+  return (((HSEM->R[SemID] & HSEM_R_LOCK) != 0U) ? 1UL : 0UL);
+}
+
+
+/**
+  * @brief  Release a semaphore.
+  * @param  SemID: semaphore ID from 0 to 31
+  * @param  ProcessID: Process ID from 0 to 255
+  * @retval None
+  */
+void  HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID)
+{
+  /* Check the parameters */
+  assert_param(IS_HSEM_SEMID(SemID));
+  assert_param(IS_HSEM_PROCESSID(ProcessID));
+
+  /* Clear the semaphore by writing to the R register : the MasterID , the processID and take bit = 0  */
+#if  USE_MULTI_CORE_SHARED_CODE != 0U
+  HSEM->R[SemID] = (ProcessID | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID));
+#else
+  HSEM->R[SemID] = (ProcessID | HSEM_CR_COREID_CURRENT);
+#endif
+
+}
+
+/**
+  * @brief  Release All semaphore used by a given Master .
+  * @param  Key: Semaphore Key , value from 0 to 0xFFFF
+  * @param  CoreID: CoreID of the CPU that is using semaphores to be released
+  * @retval None
+  */
+void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t CoreID)
+{
+  assert_param(IS_HSEM_KEY(Key));
+  assert_param(IS_HSEM_COREID(CoreID));
+
+  HSEM->CR = ((Key << HSEM_CR_KEY_Pos) | (CoreID << HSEM_CR_COREID_Pos));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HSEM_Exported_Functions_Group2 HSEM Set and Get Key functions
+  *  @brief    HSEM Set and Get Key functions.
+  *
+@verbatim
+  ==============================================================================
+              ##### HSEM Set and Get Key functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Set semaphore Key
+      (+) Get semaphore Key
+@endverbatim
+
+  * @{
+  */
+
+/**
+  * @brief  Set semaphore Key .
+  * @param  Key: Semaphore Key , value from 0 to 0xFFFF
+  * @retval None
+  */
+void  HAL_HSEM_SetClearKey(uint32_t Key)
+{
+  assert_param(IS_HSEM_KEY(Key));
+
+  MODIFY_REG(HSEM->KEYR, HSEM_KEYR_KEY, (Key << HSEM_KEYR_KEY_Pos));
+
+}
+
+/**
+  * @brief  Get semaphore Key .
+  * @retval Semaphore Key , value from 0 to 0xFFFF
+  */
+uint32_t HAL_HSEM_GetClearKey(void)
+{
+  return (HSEM->KEYR >> HSEM_KEYR_KEY_Pos);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HSEM_Exported_Functions_Group3 HSEM IRQ handler management
+  *  @brief    HSEM Notification functions.
+  *
+@verbatim
+  ==============================================================================
+      ##### HSEM IRQ handler management and Notification functions #####
+  ==============================================================================
+[..]  This section provides HSEM IRQ handler and Notification function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Activate Semaphore release Notification for a given Semaphores Mask .
+  * @param  SemMask: Mask of Released semaphores
+  * @retval Semaphore Key
+  */
+void HAL_HSEM_ActivateNotification(uint32_t SemMask)
+{
+#if  USE_MULTI_CORE_SHARED_CODE != 0U
+  /*enable the semaphore mask interrupts */
+  if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID)
+  {
+    /*Use interrupt line 0 for CPU1 Master */
+    HSEM->C1IER |= SemMask;
+  }
+  else /* HSEM_CPU2_COREID */
+  {
+    /*Use interrupt line 1 for CPU2 Master*/
+    HSEM->C2IER |= SemMask;
+  }
+#else
+  HSEM_COMMON->IER |= SemMask;
+#endif
+}
+
+/**
+  * @brief  Deactivate Semaphore release Notification for a given Semaphores Mask .
+  * @param  SemMask: Mask of Released semaphores
+  * @retval Semaphore Key
+  */
+void HAL_HSEM_DeactivateNotification(uint32_t SemMask)
+{
+#if  USE_MULTI_CORE_SHARED_CODE != 0U
+  /*enable the semaphore mask interrupts */
+  if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID)
+  {
+    /*Use interrupt line 0 for CPU1 Master */
+    HSEM->C1IER &= ~SemMask;
+  }
+  else /* HSEM_CPU2_COREID */
+  {
+    /*Use interrupt line 1 for CPU2 Master*/
+    HSEM->C2IER &= ~SemMask;
+  }
+#else
+  HSEM_COMMON->IER &= ~SemMask;
+#endif
+}
+
+/**
+  * @brief  This function handles HSEM interrupt request
+  * @retval None
+  */
+void HAL_HSEM_IRQHandler(void)
+{
+  uint32_t statusreg;
+#if  USE_MULTI_CORE_SHARED_CODE != 0U
+  if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID)
+  {
+    /* Get the list of masked freed semaphores*/
+    statusreg = HSEM->C1MISR; /*Use interrupt line 0 for CPU1 Master*/
+
+    /*Disable Interrupts*/
+    HSEM->C1IER &= ~((uint32_t)statusreg);
+
+    /*Clear Flags*/
+    HSEM->C1ICR = ((uint32_t)statusreg);
+  }
+  else /* HSEM_CPU2_COREID */
+  {
+    /* Get the list of masked freed semaphores*/
+    statusreg = HSEM->C2MISR;/*Use interrupt line 1 for CPU2 Master*/
+
+    /*Disable Interrupts*/
+    HSEM->C2IER &= ~((uint32_t)statusreg);
+
+    /*Clear Flags*/
+    HSEM->C2ICR = ((uint32_t)statusreg);
+  }
+#else
+  /* Get the list of masked freed semaphores*/
+  statusreg = HSEM_COMMON->MISR;
+
+  /*Disable Interrupts*/
+  HSEM_COMMON->IER &= ~((uint32_t)statusreg);
+
+  /*Clear Flags*/
+  HSEM_COMMON->ICR = ((uint32_t)statusreg);
+
+#endif
+  /* Call FreeCallback */
+  HAL_HSEM_FreeCallback(statusreg);
+}
+
+/**
+  * @brief Semaphore Released Callback.
+  * @param SemMask: Mask of Released semaphores
+  * @retval None
+  */
+__weak void HAL_HSEM_FreeCallback(uint32_t SemMask)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(SemMask);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+  the HAL_HSEM_FreeCallback can be implemented in the user file
+    */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_HSEM_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c
new file mode 100644
index 00000000..7c05d16f
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c
@@ -0,0 +1,6635 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_i2c.c
+  * @author  MCD Application Team
+  * @brief   I2C HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Inter Integrated Circuit (I2C) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral State and Errors functions
+  *
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The I2C HAL driver can be used as follows:
+
+    (#) Declare a I2C_HandleTypeDef handle structure, for example:
+        I2C_HandleTypeDef  hi2c;
+
+    (#)Initialize the I2C low level resources by implementing the @ref HAL_I2C_MspInit() API:
+        (##) Enable the I2Cx interface clock
+        (##) I2C pins configuration
+            (+++) Enable the clock for the I2C GPIOs
+            (+++) Configure I2C pins as alternate function open-drain
+        (##) NVIC configuration if you need to use interrupt process
+            (+++) Configure the I2Cx interrupt priority
+            (+++) Enable the NVIC I2C IRQ Channel
+        (##) DMA Configuration if you need to use DMA process
+            (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream or channel depends on Instance
+            (+++) Enable the DMAx interface clock using
+            (+++) Configure the DMA handle parameters
+            (+++) Configure the DMA Tx or Rx stream or channel depends on Instance
+            (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
+            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
+                  the DMA Tx or Rx stream or channel depends on Instance
+
+    (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
+        Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
+
+    (#) Initialize the I2C registers by calling the @ref HAL_I2C_Init(), configures also the low level Hardware
+        (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_I2C_MspInit(&hi2c) API.
+
+    (#) To check if target device is ready for communication, use the function @ref HAL_I2C_IsDeviceReady()
+
+    (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
+
+    *** Polling mode IO operation ***
+    =================================
+    [..]
+      (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Transmit()
+      (+) Receive in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Receive()
+      (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Transmit()
+      (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Receive()
+
+    *** Polling mode IO MEM operation ***
+    =====================================
+    [..]
+      (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_I2C_Mem_Write()
+      (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_I2C_Mem_Read()
+
+
+    *** Interrupt mode IO operation ***
+    ===================================
+    [..]
+      (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Transmit_IT()
+      (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
+      (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Receive_IT()
+      (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
+      (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Transmit_IT()
+      (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
+      (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Receive_IT()
+      (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
+      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
+      (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
+      (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
+      (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.
+           This action will inform Master to generate a Stop condition to discard the communication.
+
+
+    *** Interrupt mode or DMA mode IO sequential operation ***
+    ==========================================================
+    [..]
+      (@) These interfaces allow to manage a sequential transfer with a repeated start condition
+          when a direction change during transfer
+    [..]
+      (+) A specific option field manage the different steps of a sequential transfer
+      (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:
+      (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
+      (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
+                            and data to transfer without a final stop condition
+      (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
+                            and data to transfer without a final stop condition, an then permit a call the same master sequential interface
+                            several times (like @ref HAL_I2C_Master_Seq_Transmit_IT() then @ref HAL_I2C_Master_Seq_Transmit_IT()
+                            or @ref HAL_I2C_Master_Seq_Transmit_DMA() then @ref HAL_I2C_Master_Seq_Transmit_DMA())
+      (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
+                            and with new data to transfer if the direction change or manage only the new data to transfer
+                            if no direction change and without a final stop condition in both cases
+      (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
+                            and with new data to transfer if the direction change or manage only the new data to transfer
+                            if no direction change and with a final stop condition in both cases
+      (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential
+                            interface several times (link with option I2C_FIRST_AND_NEXT_FRAME).
+                            Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
+                              or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
+                              or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
+                              or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME).
+                            Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit
+                              without stopping the communication and so generate a restart condition.
+      (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential
+                            interface.
+                            Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
+                              or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
+                              or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
+                              or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME).
+                            Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition.
+
+      (+) Differents sequential I2C interfaces are listed below:
+      (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT()
+            or using @ref HAL_I2C_Master_Seq_Transmit_DMA()
+      (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
+      (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Receive_IT()
+            or using @ref HAL_I2C_Master_Seq_Receive_DMA()
+      (+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
+      (++) Abort a master IT or DMA I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
+      (+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
+      (++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen_IT() @ref HAL_I2C_DisableListen_IT()
+      (+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and user can
+           add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
+      (+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback()
+      (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Transmit_IT()
+            or using @ref HAL_I2C_Slave_Seq_Transmit_DMA()
+      (+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
+      (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Receive_IT()
+            or using @ref HAL_I2C_Slave_Seq_Receive_DMA()
+      (+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
+      (++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
+      (++) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.
+           This action will inform Master to generate a Stop condition to discard the communication.
+
+    *** Interrupt mode IO MEM operation ***
+    =======================================
+    [..]
+      (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
+          @ref HAL_I2C_Mem_Write_IT()
+      (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()
+      (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
+          @ref HAL_I2C_Mem_Read_IT()
+      (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()
+      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
+
+    *** DMA mode IO operation ***
+    ==============================
+    [..]
+      (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
+          @ref HAL_I2C_Master_Transmit_DMA()
+      (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
+      (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
+          @ref HAL_I2C_Master_Receive_DMA()
+      (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
+      (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
+          @ref HAL_I2C_Slave_Transmit_DMA()
+      (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
+      (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
+          @ref HAL_I2C_Slave_Receive_DMA()
+      (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
+      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
+      (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
+      (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
+      (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.
+           This action will inform Master to generate a Stop condition to discard the communication.
+
+    *** DMA mode IO MEM operation ***
+    =================================
+    [..]
+      (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
+          @ref HAL_I2C_Mem_Write_DMA()
+      (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()
+      (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
+          @ref HAL_I2C_Mem_Read_DMA()
+      (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()
+      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
+
+
+     *** I2C HAL driver macros list ***
+     ==================================
+     [..]
+       Below the list of most used macros in I2C HAL driver.
+
+      (+) @ref __HAL_I2C_ENABLE: Enable the I2C peripheral
+      (+) @ref __HAL_I2C_DISABLE: Disable the I2C peripheral
+      (+) @ref __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
+      (+) @ref __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
+      (+) @ref __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
+      (+) @ref __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
+      (+) @ref __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
+
+     *** Callback registration ***
+     =============================================
+    [..]
+     The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
+     allows the user to configure dynamically the driver callbacks.
+     Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback()
+     to register an interrupt callback.
+    [..]
+     Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks:
+       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+       (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
+       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
+       (+) ListenCpltCallback   : callback for end of listen mode.
+       (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.
+       (+) MemRxCpltCallback    : callback for Memory reception end of transfer.
+       (+) ErrorCallback        : callback for error detection.
+       (+) AbortCpltCallback    : callback for abort completion process.
+       (+) MspInitCallback      : callback for Msp Init.
+       (+) MspDeInitCallback    : callback for Msp DeInit.
+     This function takes as parameters the HAL peripheral handle, the Callback ID
+     and a pointer to the user callback function.
+    [..]
+     For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback().
+    [..]
+     Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default
+     weak function.
+     @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
+     and the Callback ID.
+     This function allows to reset following callbacks:
+       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+       (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
+       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
+       (+) ListenCpltCallback   : callback for end of listen mode.
+       (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.
+       (+) MemRxCpltCallback    : callback for Memory reception end of transfer.
+       (+) ErrorCallback        : callback for error detection.
+       (+) AbortCpltCallback    : callback for abort completion process.
+       (+) MspInitCallback      : callback for Msp Init.
+       (+) MspDeInitCallback    : callback for Msp DeInit.
+    [..]
+     For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback().
+    [..]
+     By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET
+     all callbacks are set to the corresponding weak functions:
+     examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback().
+     Exception done for MspInit and MspDeInit functions that are
+     reset to the legacy weak functions in the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() only when
+     these callbacks are null (not registered beforehand).
+     If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit()
+     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+    [..]
+     Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.
+     Exception done MspInit/MspDeInit functions that can be registered/unregistered
+     in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,
+     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+     Then, the user first registers the MspInit/MspDeInit user callbacks
+     using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit()
+     or @ref HAL_I2C_Init() function.
+    [..]
+     When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
+     not defined, the callback registration feature is not available and all callbacks
+     are set to the corresponding weak functions.
+
+     [..]
+       (@) You can refer to the I2C HAL driver header file for more useful macros
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup I2C I2C
+  * @brief I2C HAL module driver
+  * @{
+  */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup I2C_Private_Define I2C Private Define
+  * @{
+  */
+#define TIMING_CLEAR_MASK   (0xF0FFFFFFU)  /*!< I2C TIMING clear register Mask */
+#define I2C_TIMEOUT_ADDR    (10000U)       /*!< 10 s  */
+#define I2C_TIMEOUT_BUSY    (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_DIR     (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_RXNE    (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_STOPF   (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_TC      (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_TCR     (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_TXIS    (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_FLAG    (25U)          /*!< 25 ms */
+
+#define MAX_NBYTE_SIZE      255U
+#define SlaveAddr_SHIFT     7U
+#define SlaveAddr_MSK       0x06U
+
+/* Private define for @ref PreviousState usage */
+#define I2C_STATE_MSK             ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits            */
+#define I2C_STATE_NONE            ((uint32_t)(HAL_I2C_MODE_NONE))                                                        /*!< Default Value                                          */
+#define I2C_STATE_MASTER_BUSY_TX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER))            /*!< Master Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MASTER_BUSY_RX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER))            /*!< Master Busy RX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_SLAVE_BUSY_TX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE))             /*!< Slave Busy TX, combinaison of State LSB and Mode enum  */
+#define I2C_STATE_SLAVE_BUSY_RX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE))             /*!< Slave Busy RX, combinaison of State LSB and Mode enum  */
+#define I2C_STATE_MEM_BUSY_TX     ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM))               /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MEM_BUSY_RX     ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM))               /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
+
+
+/* Private define to centralize the enable/disable of Interrupts */
+#define I2C_XFER_TX_IT          (uint16_t)(0x0001U)   /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */
+#define I2C_XFER_RX_IT          (uint16_t)(0x0002U)   /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */
+#define I2C_XFER_LISTEN_IT      (uint16_t)(0x8000U)   /* Bit field can be combinated with @ref I2C_XFER_TX_IT and @ref I2C_XFER_RX_IT */
+
+#define I2C_XFER_ERROR_IT       (uint16_t)(0x0010U)   /* Bit definition to manage addition of global Error and NACK treatment */
+#define I2C_XFER_CPLT_IT        (uint16_t)(0x0020U)   /* Bit definition to manage only STOP evenement */
+#define I2C_XFER_RELOAD_IT      (uint16_t)(0x0040U)   /* Bit definition to manage only Reload of NBYTE */
+
+/* Private define Sequential Transfer Options default/reset value */
+#define I2C_NO_OPTION_FRAME     (0xFFFF0000U)
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/** @defgroup I2C_Private_Functions I2C Private Functions
+  * @{
+  */
+/* Private functions to handle DMA transfer */
+static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMAError(DMA_HandleTypeDef *hdma);
+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
+
+/* Private functions to handle IT transfer */
+static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c);
+static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c);
+static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
+
+/* Private functions to handle IT transfer */
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
+
+/* Private functions for I2C transfer IRQ handler */
+static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
+
+/* Private functions to handle flags during polling transfer */
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+
+/* Private functions to centralize the enable/disable of Interrupts */
+static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
+static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
+
+/* Private function to treat different error callback */
+static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c);
+
+/* Private function to flush TXDR register */
+static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
+
+/* Private function to handle  start, restart or stop a transfer */
+static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
+
+/* Private function to Convert Specific options */
+static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Functions I2C Exported Functions
+  * @{
+  */
+
+/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This subsection provides a set of functions allowing to initialize and
+          deinitialize the I2Cx peripheral:
+
+      (+) User must Implement HAL_I2C_MspInit() function in which he configures
+          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+      (+) Call the function HAL_I2C_Init() to configure the selected device with
+          the selected configuration:
+        (++) Clock Timing
+        (++) Own Address 1
+        (++) Addressing mode (Master, Slave)
+        (++) Dual Addressing mode
+        (++) Own Address 2
+        (++) Own Address 2 Mask
+        (++) General call mode
+        (++) Nostretch mode
+
+      (+) Call the function HAL_I2C_DeInit() to restore the default configuration
+          of the selected I2Cx peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the I2C according to the specified parameters
+  *         in the I2C_InitTypeDef and initialize the associated handle.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
+{
+  /* Check the I2C handle allocation */
+  if (hi2c == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
+  assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
+  assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
+  assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
+  assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
+  assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
+  assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
+
+  if (hi2c->State == HAL_I2C_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hi2c->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    /* Init the I2C Callback settings */
+    hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
+    hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
+    hi2c->SlaveTxCpltCallback  = HAL_I2C_SlaveTxCpltCallback;  /* Legacy weak SlaveTxCpltCallback  */
+    hi2c->SlaveRxCpltCallback  = HAL_I2C_SlaveRxCpltCallback;  /* Legacy weak SlaveRxCpltCallback  */
+    hi2c->ListenCpltCallback   = HAL_I2C_ListenCpltCallback;   /* Legacy weak ListenCpltCallback   */
+    hi2c->MemTxCpltCallback    = HAL_I2C_MemTxCpltCallback;    /* Legacy weak MemTxCpltCallback    */
+    hi2c->MemRxCpltCallback    = HAL_I2C_MemRxCpltCallback;    /* Legacy weak MemRxCpltCallback    */
+    hi2c->ErrorCallback        = HAL_I2C_ErrorCallback;        /* Legacy weak ErrorCallback        */
+    hi2c->AbortCpltCallback    = HAL_I2C_AbortCpltCallback;    /* Legacy weak AbortCpltCallback    */
+    hi2c->AddrCallback         = HAL_I2C_AddrCallback;         /* Legacy weak AddrCallback         */
+
+    if (hi2c->MspInitCallback == NULL)
+    {
+      hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit  */
+    }
+
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+    hi2c->MspInitCallback(hi2c);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+    HAL_I2C_MspInit(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+
+  hi2c->State = HAL_I2C_STATE_BUSY;
+
+  /* Disable the selected I2C peripheral */
+  __HAL_I2C_DISABLE(hi2c);
+
+  /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
+  /* Configure I2Cx: Frequency range */
+  hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
+
+  /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
+  /* Disable Own Address1 before set the Own Address1 configuration */
+  hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
+
+  /* Configure I2Cx: Own Address1 and ack own address1 mode */
+  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
+  {
+    hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
+  }
+  else /* I2C_ADDRESSINGMODE_10BIT */
+  {
+    hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
+  }
+
+  /*---------------------------- I2Cx CR2 Configuration ----------------------*/
+  /* Configure I2Cx: Addressing Master mode */
+  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+  {
+    hi2c->Instance->CR2 = (I2C_CR2_ADD10);
+  }
+  /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
+  hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
+
+  /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
+  /* Disable Own Address2 before set the Own Address2 configuration */
+  hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
+
+  /* Configure I2Cx: Dual mode and Own Address2 */
+  hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));
+
+  /*---------------------------- I2Cx CR1 Configuration ----------------------*/
+  /* Configure I2Cx: Generalcall and NoStretch mode */
+  hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
+
+  /* Enable the selected I2C peripheral */
+  __HAL_I2C_ENABLE(hi2c);
+
+  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+  hi2c->State = HAL_I2C_STATE_READY;
+  hi2c->PreviousState = I2C_STATE_NONE;
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the I2C peripheral.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
+{
+  /* Check the I2C handle allocation */
+  if (hi2c == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+
+  hi2c->State = HAL_I2C_STATE_BUSY;
+
+  /* Disable the I2C Peripheral Clock */
+  __HAL_I2C_DISABLE(hi2c);
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+  if (hi2c->MspDeInitCallback == NULL)
+  {
+    hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit  */
+  }
+
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  hi2c->MspDeInitCallback(hi2c);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_I2C_MspDeInit(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+
+  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+  hi2c->State = HAL_I2C_STATE_RESET;
+  hi2c->PreviousState = I2C_STATE_NONE;
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Initialize the I2C MSP.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief DeInitialize the I2C MSP.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MspDeInit could be implemented in the user file
+   */
+}
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User I2C Callback
+  *         To be used instead of the weak predefined callback
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+  *          @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
+  *          @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
+  *          @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
+  *          @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hi2c);
+
+  if (HAL_I2C_STATE_READY == hi2c->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
+        hi2c->MasterTxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
+        hi2c->MasterRxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
+        hi2c->SlaveTxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
+        hi2c->SlaveRxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_LISTEN_COMPLETE_CB_ID :
+        hi2c->ListenCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
+        hi2c->MemTxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
+        hi2c->MemRxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_ERROR_CB_ID :
+        hi2c->ErrorCallback = pCallback;
+        break;
+
+      case HAL_I2C_ABORT_CB_ID :
+        hi2c->AbortCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_MSPINIT_CB_ID :
+        hi2c->MspInitCallback = pCallback;
+        break;
+
+      case HAL_I2C_MSPDEINIT_CB_ID :
+        hi2c->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_I2C_STATE_RESET == hi2c->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_I2C_MSPINIT_CB_ID :
+        hi2c->MspInitCallback = pCallback;
+        break;
+
+      case HAL_I2C_MSPDEINIT_CB_ID :
+        hi2c->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hi2c);
+  return status;
+}
+
+/**
+  * @brief  Unregister an I2C Callback
+  *         I2C callback is redirected to the weak predefined callback
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+  *          @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
+  *          @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
+  *          @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
+  *          @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hi2c);
+
+  if (HAL_I2C_STATE_READY == hi2c->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
+        hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
+        break;
+
+      case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
+        hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
+        break;
+
+      case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
+        hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback;   /* Legacy weak SlaveTxCpltCallback  */
+        break;
+
+      case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
+        hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback;   /* Legacy weak SlaveRxCpltCallback  */
+        break;
+
+      case HAL_I2C_LISTEN_COMPLETE_CB_ID :
+        hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback;     /* Legacy weak ListenCpltCallback   */
+        break;
+
+      case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
+        hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback;       /* Legacy weak MemTxCpltCallback    */
+        break;
+
+      case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
+        hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback;       /* Legacy weak MemRxCpltCallback    */
+        break;
+
+      case HAL_I2C_ERROR_CB_ID :
+        hi2c->ErrorCallback = HAL_I2C_ErrorCallback;               /* Legacy weak ErrorCallback        */
+        break;
+
+      case HAL_I2C_ABORT_CB_ID :
+        hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback;       /* Legacy weak AbortCpltCallback    */
+        break;
+
+      case HAL_I2C_MSPINIT_CB_ID :
+        hi2c->MspInitCallback = HAL_I2C_MspInit;                   /* Legacy weak MspInit              */
+        break;
+
+      case HAL_I2C_MSPDEINIT_CB_ID :
+        hi2c->MspDeInitCallback = HAL_I2C_MspDeInit;               /* Legacy weak MspDeInit            */
+        break;
+
+      default :
+        /* Update the error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_I2C_STATE_RESET == hi2c->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_I2C_MSPINIT_CB_ID :
+        hi2c->MspInitCallback = HAL_I2C_MspInit;                   /* Legacy weak MspInit              */
+        break;
+
+      case HAL_I2C_MSPDEINIT_CB_ID :
+        hi2c->MspDeInitCallback = HAL_I2C_MspDeInit;               /* Legacy weak MspDeInit            */
+        break;
+
+      default :
+        /* Update the error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hi2c);
+  return status;
+}
+
+/**
+  * @brief  Register the Slave Address Match I2C Callback
+  *         To be used instead of the weak HAL_I2C_AddrCallback() predefined callback
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pCallback pointer to the Address Match Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hi2c);
+
+  if (HAL_I2C_STATE_READY == hi2c->State)
+  {
+    hi2c->AddrCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hi2c);
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Slave Address Match I2C Callback
+  *         Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hi2c);
+
+  if (HAL_I2C_STATE_READY == hi2c->State)
+  {
+    hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hi2c);
+  return status;
+}
+
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
+ *  @brief   Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the I2C data
+    transfers.
+
+    (#) There are two modes of transfer:
+       (++) Blocking mode : The communication is performed in the polling mode.
+            The status of all data processing is returned by the same function
+            after finishing transfer.
+       (++) No-Blocking mode : The communication is performed using Interrupts
+            or DMA. These functions return the status of the transfer startup.
+            The end of the data processing will be indicated through the
+            dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
+            using DMA mode.
+
+    (#) Blocking mode functions are :
+        (++) HAL_I2C_Master_Transmit()
+        (++) HAL_I2C_Master_Receive()
+        (++) HAL_I2C_Slave_Transmit()
+        (++) HAL_I2C_Slave_Receive()
+        (++) HAL_I2C_Mem_Write()
+        (++) HAL_I2C_Mem_Read()
+        (++) HAL_I2C_IsDeviceReady()
+
+    (#) No-Blocking mode functions with Interrupt are :
+        (++) HAL_I2C_Master_Transmit_IT()
+        (++) HAL_I2C_Master_Receive_IT()
+        (++) HAL_I2C_Slave_Transmit_IT()
+        (++) HAL_I2C_Slave_Receive_IT()
+        (++) HAL_I2C_Mem_Write_IT()
+        (++) HAL_I2C_Mem_Read_IT()
+        (++) HAL_I2C_Master_Seq_Transmit_IT()
+        (++) HAL_I2C_Master_Seq_Receive_IT()
+        (++) HAL_I2C_Slave_Seq_Transmit_IT()
+        (++) HAL_I2C_Slave_Seq_Receive_IT()
+        (++) HAL_I2C_EnableListen_IT()
+        (++) HAL_I2C_DisableListen_IT()
+        (++) HAL_I2C_Master_Abort_IT()
+
+    (#) No-Blocking mode functions with DMA are :
+        (++) HAL_I2C_Master_Transmit_DMA()
+        (++) HAL_I2C_Master_Receive_DMA()
+        (++) HAL_I2C_Slave_Transmit_DMA()
+        (++) HAL_I2C_Slave_Receive_DMA()
+        (++) HAL_I2C_Mem_Write_DMA()
+        (++) HAL_I2C_Mem_Read_DMA()
+        (++) HAL_I2C_Master_Seq_Transmit_DMA()
+        (++) HAL_I2C_Master_Seq_Receive_DMA()
+        (++) HAL_I2C_Slave_Seq_Transmit_DMA()
+        (++) HAL_I2C_Slave_Seq_Receive_DMA()
+
+    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+        (++) HAL_I2C_MasterTxCpltCallback()
+        (++) HAL_I2C_MasterRxCpltCallback()
+        (++) HAL_I2C_SlaveTxCpltCallback()
+        (++) HAL_I2C_SlaveRxCpltCallback()
+        (++) HAL_I2C_MemTxCpltCallback()
+        (++) HAL_I2C_MemRxCpltCallback()
+        (++) HAL_I2C_AddrCallback()
+        (++) HAL_I2C_ListenCpltCallback()
+        (++) HAL_I2C_ErrorCallback()
+        (++) HAL_I2C_AbortCpltCallback()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Transmits in master mode an amount of data in blocking mode.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferISR   = NULL;
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
+    }
+
+    while (hi2c->XferCount > 0U)
+    {
+      /* Wait until TXIS flag is set */
+      if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+
+      if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+      {
+        /* Wait until TCR flag is set */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        if (hi2c->XferCount > MAX_NBYTE_SIZE)
+        {
+          hi2c->XferSize = MAX_NBYTE_SIZE;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+        }
+        else
+        {
+          hi2c->XferSize = hi2c->XferCount;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+        }
+      }
+    }
+
+    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+    /* Wait until STOPF flag is set */
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Clear STOP Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Clear Configuration Register 2 */
+    I2C_RESET_CR2(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receives in master mode an amount of data in blocking mode.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferISR   = NULL;
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+    }
+
+    while (hi2c->XferCount > 0U)
+    {
+      /* Wait until RXNE flag is set */
+      if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Read data from RXDR */
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+
+      if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+      {
+        /* Wait until TCR flag is set */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        if (hi2c->XferCount > MAX_NBYTE_SIZE)
+        {
+          hi2c->XferSize = MAX_NBYTE_SIZE;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+        }
+        else
+        {
+          hi2c->XferSize = hi2c->XferCount;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+        }
+      }
+    }
+
+    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+    /* Wait until STOPF flag is set */
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Clear STOP Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Clear Configuration Register 2 */
+    I2C_RESET_CR2(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmits in slave mode an amount of data in blocking mode.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferISR   = NULL;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Wait until ADDR flag is set */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+
+    /* If 10bit addressing mode is selected */
+    if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+    {
+      /* Wait until ADDR flag is set */
+      if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+      {
+        /* Disable Address Acknowledge */
+        hi2c->Instance->CR2 |= I2C_CR2_NACK;
+        return HAL_ERROR;
+      }
+
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+    }
+
+    /* Wait until DIR flag is set Transmitter mode */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    while (hi2c->XferCount > 0U)
+    {
+      /* Wait until TXIS flag is set */
+      if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        /* Disable Address Acknowledge */
+        hi2c->Instance->CR2 |= I2C_CR2_NACK;
+        return HAL_ERROR;
+      }
+
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+    }
+
+    /* Wait until STOP flag is set */
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      {
+        /* Normal use case for Transmitter mode */
+        /* A NACK is generated to confirm the end of transfer */
+        hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+      }
+      else
+      {
+        return HAL_ERROR;
+      }
+    }
+
+    /* Clear STOP flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Wait until BUSY flag is reset */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    /* Disable Address Acknowledge */
+    hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in slave mode an amount of data in blocking mode
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferISR   = NULL;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Wait until ADDR flag is set */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+
+    /* Wait until DIR flag is reset Receiver mode */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    while (hi2c->XferCount > 0U)
+    {
+      /* Wait until RXNE flag is set */
+      if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        /* Disable Address Acknowledge */
+        hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+        /* Store Last receive data if any */
+        if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+        {
+          /* Read data from RXDR */
+          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+          /* Increment Buffer pointer */
+          hi2c->pBuffPtr++;
+
+          hi2c->XferCount--;
+        }
+
+        return HAL_ERROR;
+      }
+
+      /* Read data from RXDR */
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+    }
+
+    /* Wait until STOP flag is set */
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    /* Clear STOP flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Wait until BUSY flag is reset */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    /* Disable Address Acknowledge */
+    hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit in master mode an amount of data in non-blocking mode with Interrupt
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+  uint32_t xfermode;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_IT;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in master mode an amount of data in non-blocking mode with Interrupt
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+  uint32_t xfermode;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_IT;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit in slave mode an amount of data in non-blocking mode with Interrupt
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Slave_ISR_IT;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in slave mode an amount of data in non-blocking mode with Interrupt
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Slave_ISR_IT;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit in master mode an amount of data in non-blocking mode with DMA
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+  uint32_t xfermode;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_DMA;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    if (hi2c->XferSize > 0U)
+    {
+      if (hi2c->hdmatx != NULL)
+      {
+        /* Set the I2C DMA transfer complete callback */
+        hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+
+        /* Set the DMA error callback */
+        hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hi2c->hdmatx->XferHalfCpltCallback = NULL;
+        hi2c->hdmatx->XferAbortCallback = NULL;
+
+        /* Enable the DMA stream or channel depends on Instance */
+        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+
+      if (dmaxferstatus == HAL_OK)
+      {
+        /* Send Slave Address */
+        /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
+
+        /* Update XferCount value */
+        hi2c->XferCount -= hi2c->XferSize;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Note : The I2C interrupts must be enabled after unlocking current process
+                  to avoid the risk of I2C interrupt handle execution before current
+                  process unlock */
+        /* Enable ERR and NACK interrupts */
+        I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+        /* Enable DMA Request */
+        hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Update Transfer ISR function pointer */
+      hi2c->XferISR = I2C_Master_ISR_IT;
+
+      /* Send Slave Address */
+      /* Set NBYTES to write and generate START condition */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+      /* possible to enable all of these */
+      /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in master mode an amount of data in non-blocking mode with DMA
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+  uint32_t xfermode;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_DMA;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    if (hi2c->XferSize > 0U)
+    {
+      if (hi2c->hdmarx != NULL)
+      {
+        /* Set the I2C DMA transfer complete callback */
+        hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+
+        /* Set the DMA error callback */
+        hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hi2c->hdmarx->XferHalfCpltCallback = NULL;
+        hi2c->hdmarx->XferAbortCallback = NULL;
+
+        /* Enable the DMA stream or channel depends on Instance */
+        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+
+      if (dmaxferstatus == HAL_OK)
+      {
+        /* Send Slave Address */
+        /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+
+        /* Update XferCount value */
+        hi2c->XferCount -= hi2c->XferSize;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Note : The I2C interrupts must be enabled after unlocking current process
+                  to avoid the risk of I2C interrupt handle execution before current
+                  process unlock */
+        /* Enable ERR and NACK interrupts */
+        I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+        /* Enable DMA Request */
+        hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Update Transfer ISR function pointer */
+      hi2c->XferISR = I2C_Master_ISR_IT;
+
+      /* Send Slave Address */
+      /* Set NBYTES to read and generate START condition */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+      /* possible to enable all of these */
+      /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit in slave mode an amount of data in non-blocking mode with DMA
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef dmaxferstatus;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Slave_ISR_DMA;
+
+    if (hi2c->hdmatx != NULL)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmatx->XferHalfCpltCallback = NULL;
+      hi2c->hdmatx->XferAbortCallback = NULL;
+
+      /* Enable the DMA stream or channel depends on Instance */
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Enable Address Acknowledge */
+      hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, STOP, NACK, ADDR interrupts */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+      /* Enable DMA Request */
+      hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in slave mode an amount of data in non-blocking mode with DMA
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef dmaxferstatus;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Slave_ISR_DMA;
+
+    if (hi2c->hdmarx != NULL)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmarx->XferHalfCpltCallback = NULL;
+      hi2c->hdmarx->XferAbortCallback = NULL;
+
+      /* Enable the DMA stream or channel depends on Instance */
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Enable Address Acknowledge */
+      hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, STOP, NACK, ADDR interrupts */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+      /* Enable DMA Request */
+      hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+/**
+  * @brief  Write an amount of data in blocking mode to a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferISR   = NULL;
+
+    /* Send Slave Address and Memory Address */
+    if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+      return HAL_ERROR;
+    }
+
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+    }
+
+    do
+    {
+      /* Wait until TXIS flag is set */
+      if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+
+      if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+      {
+        /* Wait until TCR flag is set */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        if (hi2c->XferCount > MAX_NBYTE_SIZE)
+        {
+          hi2c->XferSize = MAX_NBYTE_SIZE;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+        }
+        else
+        {
+          hi2c->XferSize = hi2c->XferCount;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+        }
+      }
+
+    }
+    while (hi2c->XferCount > 0U);
+
+    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+    /* Wait until STOPF flag is reset */
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Clear STOP Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Clear Configuration Register 2 */
+    I2C_RESET_CR2(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Read an amount of data in blocking mode from a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferISR   = NULL;
+
+    /* Send Slave Address and Memory Address */
+    if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+      return HAL_ERROR;
+    }
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+    }
+
+    do
+    {
+      /* Wait until RXNE flag is set */
+      if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Read data from RXDR */
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+
+      if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+      {
+        /* Wait until TCR flag is set */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        if (hi2c->XferCount > MAX_NBYTE_SIZE)
+        {
+          hi2c->XferSize = MAX_NBYTE_SIZE;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+        }
+        else
+        {
+          hi2c->XferSize = hi2c->XferCount;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+        }
+      }
+    }
+    while (hi2c->XferCount > 0U);
+
+    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+    /* Wait until STOPF flag is reset */
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Clear STOP Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Clear Configuration Register 2 */
+    I2C_RESET_CR2(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+/**
+  * @brief  Write an amount of data in non-blocking mode with Interrupt to a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+  uint32_t tickstart;
+  uint32_t xfermode;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_IT;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    /* Send Slave Address and Memory Address */
+    if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+      return HAL_ERROR;
+    }
+
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Read an amount of data in non-blocking mode with Interrupt from a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+  uint32_t tickstart;
+  uint32_t xfermode;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_IT;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    /* Send Slave Address and Memory Address */
+    if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+      return HAL_ERROR;
+    }
+
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+/**
+  * @brief  Write an amount of data in non-blocking mode with DMA to a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+  uint32_t tickstart;
+  uint32_t xfermode;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_DMA;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    /* Send Slave Address and Memory Address */
+    if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+      return HAL_ERROR;
+    }
+
+
+    if (hi2c->hdmatx != NULL)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmatx->XferHalfCpltCallback = NULL;
+      hi2c->hdmatx->XferAbortCallback = NULL;
+
+      /* Enable the DMA stream or channel depends on Instance */
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_READY;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Send Slave Address */
+      /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+
+      /* Update XferCount value */
+      hi2c->XferCount -= hi2c->XferSize;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR and NACK interrupts */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+      /* Enable DMA Request */
+      hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_READY;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Reads an amount of data in non-blocking mode with DMA from a specific memory address.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be read
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+  uint32_t tickstart;
+  uint32_t xfermode;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_DMA;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    /* Send Slave Address and Memory Address */
+    if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+      return HAL_ERROR;
+    }
+
+    if (hi2c->hdmarx != NULL)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmarx->XferHalfCpltCallback = NULL;
+      hi2c->hdmarx->XferAbortCallback = NULL;
+
+      /* Enable the DMA stream or channel depends on Instance */
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_READY;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+
+      /* Update XferCount value */
+      hi2c->XferCount -= hi2c->XferSize;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR and NACK interrupts */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+      /* Enable DMA Request */
+      hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_READY;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Checks if target device is ready for communication.
+  * @note   This function is used with Memory devices
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  Trials Number of trials
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  __IO uint32_t I2C_Trials = 0UL;
+
+  FlagStatus tmp1;
+  FlagStatus tmp2;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    do
+    {
+      /* Generate Start */
+      hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress);
+
+      /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+      /* Wait until STOPF flag is set or a NACK flag is set*/
+      tickstart = HAL_GetTick();
+
+      tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
+      tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
+
+      while ((tmp1 == RESET) && (tmp2 == RESET))
+      {
+        if (Timeout != HAL_MAX_DELAY)
+        {
+          if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+          {
+            /* Update I2C state */
+            hi2c->State = HAL_I2C_STATE_READY;
+
+            /* Update I2C error code */
+            hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+
+            /* Process Unlocked */
+            __HAL_UNLOCK(hi2c);
+
+            return HAL_ERROR;
+          }
+        }
+
+        tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
+        tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
+      }
+
+      /* Check if the NACKF flag has not been set */
+      if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
+      {
+        /* Wait until STOPF flag is reset */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        /* Clear STOP Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+        /* Device is ready */
+        hi2c->State = HAL_I2C_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_OK;
+      }
+      else
+      {
+        /* Wait until STOPF flag is reset */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        /* Clear NACK Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+        /* Clear STOP Flag, auto generated with autoend*/
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+      }
+
+      /* Check if the maximum allowed number of trials has been reached */
+      if (I2C_Trials == Trials)
+      {
+        /* Generate Stop */
+        hi2c->Instance->CR2 |= I2C_CR2_STOP;
+
+        /* Wait until STOPF flag is reset */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        /* Clear STOP Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+      }
+
+      /* Increment Trials */
+      I2C_Trials++;
+    }
+    while (I2C_Trials < Trials);
+
+    /* Update I2C state */
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Update I2C error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_ERROR;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  uint32_t xfermode;
+  uint32_t xferrequest = I2C_GENERATE_START_WRITE;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Master_ISR_IT;
+
+    /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = hi2c->XferOptions;
+    }
+
+    /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+    /* Mean Previous state is same as current state */
+    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+    {
+      xferrequest = I2C_NO_STARTSTOP;
+    }
+    else
+    {
+      /* Convert OTHER_xxx XferOptions if any */
+      I2C_ConvertOtherXferOptions(hi2c);
+
+      /* Update xfermode accordingly if no reload is necessary */
+      if (hi2c->XferCount < MAX_NBYTE_SIZE)
+      {
+        xfermode = hi2c->XferOptions;
+      }
+    }
+
+    /* Send Slave Address and set NBYTES to write */
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  uint32_t xfermode;
+  uint32_t xferrequest = I2C_GENERATE_START_WRITE;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Master_ISR_DMA;
+
+    /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = hi2c->XferOptions;
+    }
+
+    /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+    /* Mean Previous state is same as current state */
+    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+    {
+      xferrequest = I2C_NO_STARTSTOP;
+    }
+    else
+    {
+      /* Convert OTHER_xxx XferOptions if any */
+      I2C_ConvertOtherXferOptions(hi2c);
+
+      /* Update xfermode accordingly if no reload is necessary */
+      if (hi2c->XferCount < MAX_NBYTE_SIZE)
+      {
+        xfermode = hi2c->XferOptions;
+      }
+    }
+
+    if (hi2c->XferSize > 0U)
+    {
+      if (hi2c->hdmatx != NULL)
+      {
+        /* Set the I2C DMA transfer complete callback */
+        hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+
+        /* Set the DMA error callback */
+        hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hi2c->hdmatx->XferHalfCpltCallback = NULL;
+        hi2c->hdmatx->XferAbortCallback = NULL;
+
+        /* Enable the DMA stream or channel depends on Instance */
+        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+
+      if (dmaxferstatus == HAL_OK)
+      {
+        /* Send Slave Address and set NBYTES to write */
+        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+
+        /* Update XferCount value */
+        hi2c->XferCount -= hi2c->XferSize;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Note : The I2C interrupts must be enabled after unlocking current process
+                  to avoid the risk of I2C interrupt handle execution before current
+                  process unlock */
+        /* Enable ERR and NACK interrupts */
+        I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+        /* Enable DMA Request */
+        hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Update Transfer ISR function pointer */
+      hi2c->XferISR = I2C_Master_ISR_IT;
+
+      /* Send Slave Address */
+      /* Set NBYTES to write and generate START condition */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+      /* possible to enable all of these */
+      /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  uint32_t xfermode;
+  uint32_t xferrequest = I2C_GENERATE_START_READ;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Master_ISR_IT;
+
+    /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = hi2c->XferOptions;
+    }
+
+    /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+    /* Mean Previous state is same as current state */
+    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+    {
+      xferrequest = I2C_NO_STARTSTOP;
+    }
+    else
+    {
+      /* Convert OTHER_xxx XferOptions if any */
+      I2C_ConvertOtherXferOptions(hi2c);
+
+      /* Update xfermode accordingly if no reload is necessary */
+      if (hi2c->XferCount < MAX_NBYTE_SIZE)
+      {
+        xfermode = hi2c->XferOptions;
+      }
+    }
+
+    /* Send Slave Address and set NBYTES to read */
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  uint32_t xfermode;
+  uint32_t xferrequest = I2C_GENERATE_START_READ;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Master_ISR_DMA;
+
+    /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = hi2c->XferOptions;
+    }
+
+    /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+    /* Mean Previous state is same as current state */
+    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+    {
+      xferrequest = I2C_NO_STARTSTOP;
+    }
+    else
+    {
+      /* Convert OTHER_xxx XferOptions if any */
+      I2C_ConvertOtherXferOptions(hi2c);
+
+      /* Update xfermode accordingly if no reload is necessary */
+      if (hi2c->XferCount < MAX_NBYTE_SIZE)
+      {
+        xfermode = hi2c->XferOptions;
+      }
+    }
+
+    if (hi2c->XferSize > 0U)
+    {
+      if (hi2c->hdmarx != NULL)
+      {
+        /* Set the I2C DMA transfer complete callback */
+        hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+
+        /* Set the DMA error callback */
+        hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hi2c->hdmarx->XferHalfCpltCallback = NULL;
+        hi2c->hdmarx->XferAbortCallback = NULL;
+
+        /* Enable the DMA stream or channel depends on Instance */
+        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+
+      if (dmaxferstatus == HAL_OK)
+      {
+        /* Send Slave Address and set NBYTES to read */
+        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+
+        /* Update XferCount value */
+        hi2c->XferCount -= hi2c->XferSize;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Note : The I2C interrupts must be enabled after unlocking current process
+                  to avoid the risk of I2C interrupt handle execution before current
+                  process unlock */
+        /* Enable ERR and NACK interrupts */
+        I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+        /* Enable DMA Request */
+        hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Update Transfer ISR function pointer */
+      hi2c->XferISR = I2C_Master_ISR_IT;
+
+      /* Send Slave Address */
+      /* Set NBYTES to read and generate START condition */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+      /* possible to enable all of these */
+      /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+    /* and then toggle the HAL slave RX state to TX state */
+    if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+    {
+      /* Disable associated Interrupts */
+      I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+      /* Abort DMA Xfer if any */
+      if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+      {
+        hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+        if (hi2c->hdmarx != NULL)
+        {
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA RX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+          }
+        }
+      }
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Slave_ISR_IT;
+
+    if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+    {
+      /* Clear ADDR flag after prepare the transfer parameters */
+      /* This action will generate an acknowledge to the Master */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
+    /* REnable ADDR interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+
+    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+    /* and then toggle the HAL slave RX state to TX state */
+    if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+    {
+      /* Disable associated Interrupts */
+      I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+      if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+      {
+        /* Abort DMA Xfer if any */
+        if (hi2c->hdmarx != NULL)
+        {
+          hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA RX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+          }
+        }
+      }
+    }
+    else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+    {
+      if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+      {
+        hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+        /* Abort DMA Xfer if any */
+        if (hi2c->hdmatx != NULL)
+        {
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA TX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+          }
+        }
+      }
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Slave_ISR_DMA;
+
+    if (hi2c->hdmatx != NULL)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmatx->XferHalfCpltCallback = NULL;
+      hi2c->hdmatx->XferAbortCallback = NULL;
+
+      /* Enable the DMA stream or channel depends on Instance */
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Update XferCount value */
+      hi2c->XferCount -= hi2c->XferSize;
+
+      /* Reset XferSize */
+      hi2c->XferSize = 0;
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+    {
+      /* Clear ADDR flag after prepare the transfer parameters */
+      /* This action will generate an acknowledge to the Master */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
+    /* Enable ERR, STOP, NACK, ADDR interrupts */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+    /* Enable DMA Request */
+    hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+    /* and then toggle the HAL slave TX state to RX state */
+    if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+    {
+      /* Disable associated Interrupts */
+      I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+      if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+      {
+        hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+        /* Abort DMA Xfer if any */
+        if (hi2c->hdmatx != NULL)
+        {
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA TX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+          }
+        }
+      }
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Slave_ISR_IT;
+
+    if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
+    {
+      /* Clear ADDR flag after prepare the transfer parameters */
+      /* This action will generate an acknowledge to the Master */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
+    /* REnable ADDR interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+    /* and then toggle the HAL slave TX state to RX state */
+    if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+    {
+      /* Disable associated Interrupts */
+      I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+      if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+      {
+        /* Abort DMA Xfer if any */
+        if (hi2c->hdmatx != NULL)
+        {
+          hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA TX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+          }
+        }
+      }
+    }
+    else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+    {
+      if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+      {
+        hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+        /* Abort DMA Xfer if any */
+        if (hi2c->hdmarx != NULL)
+        {
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA RX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+          }
+        }
+      }
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Slave_ISR_DMA;
+
+    if (hi2c->hdmarx != NULL)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmarx->XferHalfCpltCallback = NULL;
+      hi2c->hdmarx->XferAbortCallback = NULL;
+
+      /* Enable the DMA stream or channel depends on Instance */
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Update XferCount value */
+      hi2c->XferCount -= hi2c->XferSize;
+
+      /* Reset XferSize */
+      hi2c->XferSize = 0;
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
+    {
+      /* Clear ADDR flag after prepare the transfer parameters */
+      /* This action will generate an acknowledge to the Master */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
+    /* REnable ADDR interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
+
+    /* Enable DMA Request */
+    hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable the Address listen mode with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
+{
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    hi2c->State = HAL_I2C_STATE_LISTEN;
+    hi2c->XferISR = I2C_Slave_ISR_IT;
+
+    /* Enable the Address Match interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Disable the Address listen mode with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
+{
+  /* Declaration of tmp to prevent undefined behavior of volatile usage */
+  uint32_t tmp;
+
+  /* Disable Address listen mode only if a transfer is not ongoing */
+  if (hi2c->State == HAL_I2C_STATE_LISTEN)
+  {
+    tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
+    hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode = HAL_I2C_MODE_NONE;
+    hi2c->XferISR = NULL;
+
+    /* Disable the Address Match interrupt */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Abort a master I2C IT or DMA process communication with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
+{
+  if (hi2c->Mode == HAL_I2C_MODE_MASTER)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Disable Interrupts and Store Previous state */
+    if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+    {
+      I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+      hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+    }
+    else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+    {
+      I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+      hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+    }
+    else
+    {
+      /* Do nothing */
+    }
+
+    /* Set State at HAL_I2C_STATE_ABORT */
+    hi2c->State = HAL_I2C_STATE_ABORT;
+
+    /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
+    /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
+    I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    /* Wrong usage of abort function */
+    /* This function should be used only in case of abort monitored by master device */
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+
+/**
+  * @brief  This function handles I2C event interrupt request.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
+{
+  /* Get current IT Flags and IT sources value */
+  uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
+  uint32_t itsources = READ_REG(hi2c->Instance->CR1);
+
+  /* I2C events treatment -------------------------------------*/
+  if (hi2c->XferISR != NULL)
+  {
+    hi2c->XferISR(hi2c, itflags, itsources);
+  }
+}
+
+/**
+  * @brief  This function handles I2C error interrupt request.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
+{
+  uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
+  uint32_t itsources = READ_REG(hi2c->Instance->CR1);
+  uint32_t tmperror;
+
+  /* I2C Bus error interrupt occurred ------------------------------------*/
+  if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+  {
+    hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
+
+    /* Clear BERR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
+  }
+
+  /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
+  if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+  {
+    hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
+
+    /* Clear OVR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
+  }
+
+  /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
+  if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+  {
+    hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
+
+    /* Clear ARLO flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
+  }
+
+  /* Store current volatile hi2c->ErrorCode, misra rule */
+  tmperror = hi2c->ErrorCode;
+
+  /* Call the Error Callback in case of Error detected */
+  if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) !=  HAL_I2C_ERROR_NONE)
+  {
+    I2C_ITError(hi2c, tmperror);
+  }
+}
+
+/**
+  * @brief  Master Tx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Master Rx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
+   */
+}
+
+/** @brief  Slave Tx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Slave Rx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Slave Address Match callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
+  * @param  AddrMatchCode Address Match Code
+  * @retval None
+  */
+__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+  UNUSED(TransferDirection);
+  UNUSED(AddrMatchCode);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_AddrCallback() could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Listen Complete callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_ListenCpltCallback() could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Memory Tx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MemTxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Memory Rx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MemRxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  I2C error callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  I2C abort callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_AbortCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
+ *  @brief   Peripheral State, Mode and Error functions
+ *
+@verbatim
+ ===============================================================================
+            ##### Peripheral State, Mode and Error functions #####
+ ===============================================================================
+    [..]
+    This subsection permit to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the I2C handle state.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL state
+  */
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
+{
+  /* Return I2C handle state */
+  return hi2c->State;
+}
+
+/**
+  * @brief  Returns the I2C Master, Slave, Memory or no mode.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval HAL mode
+  */
+HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
+{
+  return hi2c->Mode;
+}
+
+/**
+* @brief  Return the I2C error code.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *              the configuration information for the specified I2C.
+* @retval I2C Error Code
+*/
+uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
+{
+  return hi2c->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  ITFlags Interrupt flags to handle.
+  * @param  ITSources Interrupt sources enabled.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
+{
+  uint16_t devaddress;
+  uint32_t tmpITFlags = ITFlags;
+
+  /* Process Locked */
+  __HAL_LOCK(hi2c);
+
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+  {
+    /* Clear NACK Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    /* Set corresponding Error Code */
+    /* No need to generate STOP, it is automatically done */
+    /* Error callback will be send during stop flag treatment */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+    /* Flush TX register */
+    I2C_Flush_TXDR(hi2c);
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+  {
+    /* Remove RXNE flag on temporary variable as read done */
+    tmpITFlags &= ~I2C_FLAG_RXNE;
+
+    /* Read data from RXDR */
+    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    hi2c->XferSize--;
+    hi2c->XferCount--;
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+  {
+    /* Write data to TXDR */
+    hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    hi2c->XferSize--;
+    hi2c->XferCount--;
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+  {
+    if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+    {
+      devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
+
+      if (hi2c->XferCount > MAX_NBYTE_SIZE)
+      {
+        hi2c->XferSize = MAX_NBYTE_SIZE;
+        I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+      }
+      else
+      {
+        hi2c->XferSize = hi2c->XferCount;
+        if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+        {
+          I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP);
+        }
+        else
+        {
+          I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+        }
+      }
+    }
+    else
+    {
+      /* Call TxCpltCallback() if no stop mode is set */
+      if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+      {
+        /* Call I2C Master Sequential complete process */
+        I2C_ITMasterSeqCplt(hi2c);
+      }
+      else
+      {
+        /* Wrong size Status regarding TCR flag event */
+        /* Call the corresponding callback to inform upper layer of End of Transfer */
+        I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+      }
+    }
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+  {
+    if (hi2c->XferCount == 0U)
+    {
+      if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+      {
+        /* Generate a stop condition in case of no transfer option */
+        if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
+        {
+          /* Generate Stop */
+          hi2c->Instance->CR2 |= I2C_CR2_STOP;
+        }
+        else
+        {
+          /* Call I2C Master Sequential complete process */
+          I2C_ITMasterSeqCplt(hi2c);
+        }
+      }
+    }
+    else
+    {
+      /* Wrong size Status regarding TC flag event */
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+      I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+    }
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+  {
+    /* Call I2C Master complete process */
+    I2C_ITMasterCplt(hi2c, tmpITFlags);
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  ITFlags Interrupt flags to handle.
+  * @param  ITSources Interrupt sources enabled.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
+{
+  uint32_t tmpoptions = hi2c->XferOptions;
+  uint32_t tmpITFlags = ITFlags;
+
+  /* Process locked */
+  __HAL_LOCK(hi2c);
+
+  /* Check if STOPF is set */
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+  {
+    /* Call I2C Slave complete process */
+    I2C_ITSlaveCplt(hi2c, tmpITFlags);
+  }
+
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+  {
+    /* Check that I2C transfer finished */
+    /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+    /* Mean XferCount == 0*/
+    /* So clear Flag NACKF only */
+    if (hi2c->XferCount == 0U)
+    {
+      if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */
+      {
+        /* Call I2C Listen complete process */
+        I2C_ITListenCplt(hi2c, tmpITFlags);
+      }
+      else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
+      {
+        /* Clear NACK Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+        /* Flush TX register */
+        I2C_Flush_TXDR(hi2c);
+
+        /* Last Byte is Transmitted */
+        /* Call I2C Slave Sequential complete process */
+        I2C_ITSlaveSeqCplt(hi2c);
+      }
+      else
+      {
+        /* Clear NACK Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+      }
+    }
+    else
+    {
+      /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
+      /* Clear NACK Flag */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+      /* Set ErrorCode corresponding to a Non-Acknowledge */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+      if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
+      {
+        /* Call the corresponding callback to inform upper layer of End of Transfer */
+        I2C_ITError(hi2c, hi2c->ErrorCode);
+      }
+    }
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+  {
+    if (hi2c->XferCount > 0U)
+    {
+      /* Read data from RXDR */
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+    }
+
+    if ((hi2c->XferCount == 0U) && \
+        (tmpoptions != I2C_NO_OPTION_FRAME))
+    {
+      /* Call I2C Slave Sequential complete process */
+      I2C_ITSlaveSeqCplt(hi2c);
+    }
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
+  {
+    I2C_ITAddrCplt(hi2c, tmpITFlags);
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+  {
+    /* Write data to TXDR only if XferCount not reach "0" */
+    /* A TXIS flag can be set, during STOP treatment      */
+    /* Check if all Datas have already been sent */
+    /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
+    if (hi2c->XferCount > 0U)
+    {
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+    }
+    else
+    {
+      if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
+      {
+        /* Last Byte is Transmitted */
+        /* Call I2C Slave Sequential complete process */
+        I2C_ITSlaveSeqCplt(hi2c);
+      }
+    }
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  ITFlags Interrupt flags to handle.
+  * @param  ITSources Interrupt sources enabled.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
+{
+  uint16_t devaddress;
+  uint32_t xfermode;
+
+  /* Process Locked */
+  __HAL_LOCK(hi2c);
+
+  if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+  {
+    /* Clear NACK Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    /* Set corresponding Error Code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+    /* No need to generate STOP, it is automatically done */
+    /* But enable STOP interrupt, to treat it */
+    /* Error callback will be send during stop flag treatment */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+
+    /* Flush TX register */
+    I2C_Flush_TXDR(hi2c);
+  }
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+  {
+    /* Disable TC interrupt */
+    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
+
+    if (hi2c->XferCount != 0U)
+    {
+      /* Recover Slave address */
+      devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
+
+      /* Prepare the new XferSize to transfer */
+      if (hi2c->XferCount > MAX_NBYTE_SIZE)
+      {
+        hi2c->XferSize = MAX_NBYTE_SIZE;
+        xfermode = I2C_RELOAD_MODE;
+      }
+      else
+      {
+        hi2c->XferSize = hi2c->XferCount;
+        if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+        {
+          xfermode = hi2c->XferOptions;
+        }
+        else
+        {
+          xfermode = I2C_AUTOEND_MODE;
+        }
+      }
+
+      /* Set the new XferSize in Nbytes register */
+      I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+
+      /* Update XferCount value */
+      hi2c->XferCount -= hi2c->XferSize;
+
+      /* Enable DMA Request */
+      if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+      {
+        hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+      }
+      else
+      {
+        hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+      }
+    }
+    else
+    {
+      /* Call TxCpltCallback() if no stop mode is set */
+      if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+      {
+        /* Call I2C Master Sequential complete process */
+        I2C_ITMasterSeqCplt(hi2c);
+      }
+      else
+      {
+        /* Wrong size Status regarding TCR flag event */
+        /* Call the corresponding callback to inform upper layer of End of Transfer */
+        I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+      }
+    }
+  }
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+  {
+    if (hi2c->XferCount == 0U)
+    {
+      if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+      {
+        /* Generate a stop condition in case of no transfer option */
+        if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
+        {
+          /* Generate Stop */
+          hi2c->Instance->CR2 |= I2C_CR2_STOP;
+        }
+        else
+        {
+          /* Call I2C Master Sequential complete process */
+          I2C_ITMasterSeqCplt(hi2c);
+        }
+      }
+    }
+    else
+    {
+      /* Wrong size Status regarding TC flag event */
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+      I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+    }
+  }
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+  {
+    /* Call I2C Master complete process */
+    I2C_ITMasterCplt(hi2c, ITFlags);
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  ITFlags Interrupt flags to handle.
+  * @param  ITSources Interrupt sources enabled.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
+{
+  uint32_t tmpoptions = hi2c->XferOptions;
+  uint32_t treatdmanack = 0U;
+  HAL_I2C_StateTypeDef tmpstate;
+
+  /* Process locked */
+  __HAL_LOCK(hi2c);
+
+  /* Check if STOPF is set */
+  if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+  {
+    /* Call I2C Slave complete process */
+    I2C_ITSlaveCplt(hi2c, ITFlags);
+  }
+
+  if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+  {
+    /* Check that I2C transfer finished */
+    /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+    /* Mean XferCount == 0 */
+    /* So clear Flag NACKF only */
+    if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
+        (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))
+    {
+      /* Split check of hdmarx, for MISRA compliance */
+      if (hi2c->hdmarx != NULL)
+      {
+        if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)
+        {
+          if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U)
+          {
+            treatdmanack = 1U;
+          }
+        }
+      }
+
+      /* Split check of hdmatx, for MISRA compliance  */
+      if (hi2c->hdmatx != NULL)
+      {
+        if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)
+        {
+          if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U)
+          {
+            treatdmanack = 1U;
+          }
+        }
+      }
+
+      if (treatdmanack == 1U)
+      {
+        if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */
+        {
+          /* Call I2C Listen complete process */
+          I2C_ITListenCplt(hi2c, ITFlags);
+        }
+        else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
+        {
+          /* Clear NACK Flag */
+          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+          /* Flush TX register */
+          I2C_Flush_TXDR(hi2c);
+
+          /* Last Byte is Transmitted */
+          /* Call I2C Slave Sequential complete process */
+          I2C_ITSlaveSeqCplt(hi2c);
+        }
+        else
+        {
+          /* Clear NACK Flag */
+          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+        }
+      }
+      else
+      {
+        /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
+        /* Clear NACK Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+        /* Set ErrorCode corresponding to a Non-Acknowledge */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+        /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */
+        tmpstate = hi2c->State;
+
+        if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
+        {
+          if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
+          {
+            hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+          }
+          else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+          {
+            hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+          }
+          else
+          {
+            /* Do nothing */
+          }
+
+          /* Call the corresponding callback to inform upper layer of End of Transfer */
+          I2C_ITError(hi2c, hi2c->ErrorCode);
+        }
+      }
+    }
+    else
+    {
+      /* Only Clear NACK Flag, no DMA treatment is pending */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+    }
+  }
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
+  {
+    I2C_ITAddrCplt(hi2c, ITFlags);
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Master sends target device address followed by internal memory address for write request.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
+{
+  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
+
+  /* Wait until TXIS flag is set */
+  if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* If Memory address size is 8Bit */
+  if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
+  {
+    /* Send Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+  }
+  /* If Memory address size is 16Bit */
+  else
+  {
+    /* Send MSB of Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+
+    /* Wait until TXIS flag is set */
+    if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Send LSB of Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+  }
+
+  /* Wait until TCR flag is set */
+  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Master sends target device address followed by internal memory address for read request.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
+{
+  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
+
+  /* Wait until TXIS flag is set */
+  if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* If Memory address size is 8Bit */
+  if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
+  {
+    /* Send Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+  }
+  /* If Memory address size is 16Bit */
+  else
+  {
+    /* Send MSB of Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+
+    /* Wait until TXIS flag is set */
+    if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Send LSB of Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+  }
+
+  /* Wait until TC flag is set */
+  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  I2C Address complete process callback.
+  * @param  hi2c I2C handle.
+  * @param  ITFlags Interrupt flags to handle.
+  * @retval None
+  */
+static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+  uint8_t transferdirection;
+  uint16_t slaveaddrcode;
+  uint16_t ownadd1code;
+  uint16_t ownadd2code;
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(ITFlags);
+
+  /* In case of Listen state, need to inform upper layer of address match code event */
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    transferdirection = I2C_GET_DIR(hi2c);
+    slaveaddrcode     = I2C_GET_ADDR_MATCH(hi2c);
+    ownadd1code       = I2C_GET_OWN_ADDRESS1(hi2c);
+    ownadd2code       = I2C_GET_OWN_ADDRESS2(hi2c);
+
+    /* If 10bits addressing mode is selected */
+    if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+    {
+      if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK))
+      {
+        slaveaddrcode = ownadd1code;
+        hi2c->AddrEventCount++;
+        if (hi2c->AddrEventCount == 2U)
+        {
+          /* Reset Address Event counter */
+          hi2c->AddrEventCount = 0U;
+
+          /* Clear ADDR flag */
+          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2c);
+
+          /* Call Slave Addr callback */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+          hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#else
+          HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+        }
+      }
+      else
+      {
+        slaveaddrcode = ownadd2code;
+
+        /* Disable ADDR Interrupts */
+        I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Call Slave Addr callback */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+        hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#else
+        HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+      }
+    }
+    /* else 7 bits addressing mode is selected */
+    else
+    {
+      /* Disable ADDR Interrupts */
+      I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Call Slave Addr callback */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#else
+      HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+  }
+  /* Else clear address flag only */
+  else
+  {
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+  }
+}
+
+/**
+  * @brief  I2C Master sequential complete process.
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c)
+{
+  /* Reset I2C handle mode */
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+
+  /* No Generate Stop, to permit restart mode */
+  /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
+  if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+  {
+    hi2c->State         = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+    hi2c->XferISR       = NULL;
+
+    /* Disable Interrupts */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->MasterTxCpltCallback(hi2c);
+#else
+    HAL_I2C_MasterTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+  /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
+  else
+  {
+    hi2c->State         = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+    hi2c->XferISR       = NULL;
+
+    /* Disable Interrupts */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->MasterRxCpltCallback(hi2c);
+#else
+    HAL_I2C_MasterRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief  I2C Slave sequential complete process.
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
+{
+  uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
+
+  /* Reset I2C handle mode */
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+
+  /* If a DMA is ongoing, Update handle size context */
+  if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+  }
+  else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+  }
+  else
+  {
+    /* Do nothing */
+  }
+
+  if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+  {
+    /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
+    hi2c->State         = HAL_I2C_STATE_LISTEN;
+    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+
+    /* Disable Interrupts */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->SlaveTxCpltCallback(hi2c);
+#else
+    HAL_I2C_SlaveTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+
+  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+  {
+    /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
+    hi2c->State         = HAL_I2C_STATE_LISTEN;
+    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+
+    /* Disable Interrupts */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->SlaveRxCpltCallback(hi2c);
+#else
+    HAL_I2C_SlaveRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+}
+
+/**
+  * @brief  I2C Master complete process.
+  * @param  hi2c I2C handle.
+  * @param  ITFlags Interrupt flags to handle.
+  * @retval None
+  */
+static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+  uint32_t tmperror;
+  uint32_t tmpITFlags = ITFlags;
+  uint32_t tmp;
+
+  /* Clear STOP Flag */
+  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+  /* Disable Interrupts and Store Previous state */
+  if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+  {
+    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+    hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+  }
+  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+  {
+    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+    hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+  }
+  else
+  {
+    /* Do nothing */
+  }
+
+  /* Clear Configuration Register 2 */
+  I2C_RESET_CR2(hi2c);
+
+  /* Reset handle parameters */
+  hi2c->XferISR       = NULL;
+  hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
+
+  if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET)
+  {
+    /* Clear NACK Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    /* Set acknowledge error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+  }
+
+  /* Fetch Last receive data if any */
+  if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET))
+  {
+    /* Read data from RXDR */
+    tmp = (uint8_t)hi2c->Instance->RXDR;
+
+    UNUSED(tmp);
+  }
+
+  /* Flush TX register */
+  I2C_Flush_TXDR(hi2c);
+
+  /* Store current volatile hi2c->ErrorCode, misra rule */
+  tmperror = hi2c->ErrorCode;
+
+  /* Call the corresponding callback to inform upper layer of End of Transfer */
+  if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE))
+  {
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    I2C_ITError(hi2c, hi2c->ErrorCode);
+  }
+  /* hi2c->State == HAL_I2C_STATE_BUSY_TX */
+  else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    if (hi2c->Mode == HAL_I2C_MODE_MEM)
+    {
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->MemTxCpltCallback(hi2c);
+#else
+      HAL_I2C_MemTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+    else
+    {
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->MasterTxCpltCallback(hi2c);
+#else
+      HAL_I2C_MasterTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+  }
+  /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
+  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    if (hi2c->Mode == HAL_I2C_MODE_MEM)
+    {
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->MemRxCpltCallback(hi2c);
+#else
+      HAL_I2C_MemRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+    else
+    {
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->MasterRxCpltCallback(hi2c);
+#else
+      HAL_I2C_MasterRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+}
+
+/**
+  * @brief  I2C Slave complete process.
+  * @param  hi2c I2C handle.
+  * @param  ITFlags Interrupt flags to handle.
+  * @retval None
+  */
+static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+  uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
+  uint32_t tmpITFlags = ITFlags;
+  HAL_I2C_StateTypeDef tmpstate = hi2c->State;
+
+  /* Clear STOP Flag */
+  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+  /* Disable Interrupts and Store Previous state */
+  if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
+  {
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+  }
+  else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+  {
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
+    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+  }
+  else
+  {
+    /* Do nothing */
+  }
+
+  /* Disable Address Acknowledge */
+  hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+  /* Clear Configuration Register 2 */
+  I2C_RESET_CR2(hi2c);
+
+  /* Flush TX register */
+  I2C_Flush_TXDR(hi2c);
+
+  /* If a DMA is ongoing, Update handle size context */
+  if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+    if (hi2c->hdmatx != NULL)
+    {
+      hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx);
+    }
+  }
+  else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+    if (hi2c->hdmarx != NULL)
+    {
+      hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx);
+    }
+  }
+  else
+  {
+    /* Do nothing */
+  }
+
+  /* Store Last receive data if any */
+  if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)
+  {
+    /* Remove RXNE flag on temporary variable as read done */
+    tmpITFlags &= ~I2C_FLAG_RXNE;
+
+    /* Read data from RXDR */
+    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    if ((hi2c->XferSize > 0U))
+    {
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+    }
+  }
+
+  /* All data are not transferred, so set error code accordingly */
+  if (hi2c->XferCount != 0U)
+  {
+    /* Set ErrorCode corresponding to a Non-Acknowledge */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+  }
+
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+  hi2c->XferISR = NULL;
+
+  if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+  {
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    I2C_ITError(hi2c, hi2c->ErrorCode);
+
+    /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+    if (hi2c->State == HAL_I2C_STATE_LISTEN)
+    {
+      /* Call I2C Listen complete process */
+      I2C_ITListenCplt(hi2c, tmpITFlags);
+    }
+  }
+  else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+  {
+    /* Call the Sequential Complete callback, to inform upper layer of the end of Tranfer */
+    I2C_ITSlaveSeqCplt(hi2c);
+
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->ListenCpltCallback(hi2c);
+#else
+    HAL_I2C_ListenCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+  /* Call the corresponding callback to inform upper layer of End of Transfer */
+  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->SlaveRxCpltCallback(hi2c);
+#else
+    HAL_I2C_SlaveRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->SlaveTxCpltCallback(hi2c);
+#else
+    HAL_I2C_SlaveTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief  I2C Listen complete process.
+  * @param  hi2c I2C handle.
+  * @param  ITFlags Interrupt flags to handle.
+  * @retval None
+  */
+static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+  /* Reset handle parameters */
+  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+  hi2c->PreviousState = I2C_STATE_NONE;
+  hi2c->State = HAL_I2C_STATE_READY;
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+  hi2c->XferISR = NULL;
+
+  /* Store Last receive data if any */
+  if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET)
+  {
+    /* Read data from RXDR */
+    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    if ((hi2c->XferSize > 0U))
+    {
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+
+      /* Set ErrorCode corresponding to a Non-Acknowledge */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+    }
+  }
+
+  /* Disable all Interrupts*/
+  I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
+
+  /* Clear NACK Flag */
+  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+  hi2c->ListenCpltCallback(hi2c);
+#else
+  HAL_I2C_ListenCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  I2C interrupts error process.
+  * @param  hi2c I2C handle.
+  * @param  ErrorCode Error code to handle.
+  * @retval None
+  */
+static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
+{
+  HAL_I2C_StateTypeDef tmpstate = hi2c->State;
+  uint32_t tmppreviousstate;
+
+  /* Reset handle parameters */
+  hi2c->Mode          = HAL_I2C_MODE_NONE;
+  hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
+  hi2c->XferCount     = 0U;
+
+  /* Set new error code */
+  hi2c->ErrorCode |= ErrorCode;
+
+  /* Disable Interrupts */
+  if ((tmpstate == HAL_I2C_STATE_LISTEN)         ||
+      (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
+      (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+  {
+    /* Disable all interrupts, except interrupts related to LISTEN state */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
+
+    /* keep HAL_I2C_STATE_LISTEN if set */
+    hi2c->State         = HAL_I2C_STATE_LISTEN;
+    hi2c->XferISR       = I2C_Slave_ISR_IT;
+  }
+  else
+  {
+    /* Disable all interrupts */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
+
+    /* If state is an abort treatment on goind, don't change state */
+    /* This change will be do later */
+    if (hi2c->State != HAL_I2C_STATE_ABORT)
+    {
+      /* Set HAL_I2C_STATE_READY */
+      hi2c->State         = HAL_I2C_STATE_READY;
+    }
+    hi2c->XferISR       = NULL;
+  }
+
+  /* Abort DMA TX transfer if any */
+  tmppreviousstate = hi2c->PreviousState;
+  if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
+  {
+    if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+    {
+      hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+    }
+
+    if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
+    {
+      /* Set the I2C DMA Abort callback :
+       will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+      hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Abort DMA TX */
+      if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+      {
+        /* Call Directly XferAbortCallback function in case of error */
+        hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+      }
+    }
+    else
+    {
+      I2C_TreatErrorCallback(hi2c);
+    }
+  }
+  /* Abort DMA RX transfer if any */
+  else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
+  {
+    if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+    {
+      hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+    }
+
+    if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
+    {
+      /* Set the I2C DMA Abort callback :
+        will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+      hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Abort DMA RX */
+      if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+      {
+        /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
+        hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+      }
+    }
+    else
+    {
+      I2C_TreatErrorCallback(hi2c);
+    }
+  }
+  else
+  {
+    I2C_TreatErrorCallback(hi2c);
+  }
+}
+
+/**
+  * @brief  I2C Error callback treatment.
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c)
+{
+  if (hi2c->State == HAL_I2C_STATE_ABORT)
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->AbortCpltCallback(hi2c);
+#else
+    HAL_I2C_AbortCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->ErrorCallback(hi2c);
+#else
+    HAL_I2C_ErrorCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief  I2C Tx data register flush process.
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
+{
+  /* If a pending TXIS flag is set */
+  /* Write a dummy data in TXDR to clear it */
+  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
+  {
+    hi2c->Instance->TXDR = 0x00U;
+  }
+
+  /* Flush TX register if not empty */
+  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
+  {
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
+  }
+}
+
+/**
+  * @brief  DMA I2C master transmit process complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+
+  /* Disable DMA Request */
+  hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+  /* If last transfer, enable STOP interrupt */
+  if (hi2c->XferCount == 0U)
+  {
+    /* Enable STOP interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+  }
+  /* else prepare a new DMA transfer and enable TCReload interrupt */
+  else
+  {
+    /* Update Buffer pointer */
+    hi2c->pBuffPtr += hi2c->XferSize;
+
+    /* Set the XferSize to transfer */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+    }
+
+    /* Enable the DMA stream or channel depends on Instance */
+    if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize) != HAL_OK)
+    {
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+      I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+    }
+    else
+    {
+      /* Enable TC interrupts */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
+    }
+  }
+}
+
+/**
+  * @brief  DMA I2C slave transmit process complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+  uint32_t tmpoptions = hi2c->XferOptions;
+
+  if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+    /* Last Byte is Transmitted */
+    /* Call I2C Slave Sequential complete process */
+    I2C_ITSlaveSeqCplt(hi2c);
+  }
+  else
+  {
+    /* No specific action, Master fully manage the generation of STOP condition */
+    /* Mean that this generation can arrive at any time, at the end or during DMA process */
+    /* So STOP condition should be manage through Interrupt treatment */
+  }
+}
+
+/**
+  * @brief DMA I2C master receive process complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+
+  /* Disable DMA Request */
+  hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+  /* If last transfer, enable STOP interrupt */
+  if (hi2c->XferCount == 0U)
+  {
+    /* Enable STOP interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+  }
+  /* else prepare a new DMA transfer and enable TCReload interrupt */
+  else
+  {
+    /* Update Buffer pointer */
+    hi2c->pBuffPtr += hi2c->XferSize;
+
+    /* Set the XferSize to transfer */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+    }
+
+    /* Enable the DMA stream or channel depends on Instance */
+    if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize) != HAL_OK)
+    {
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+      I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+    }
+    else
+    {
+      /* Enable TC interrupts */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
+    }
+  }
+}
+
+/**
+  * @brief  DMA I2C slave receive process complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+  uint32_t tmpoptions = hi2c->XferOptions;
+
+  if ((__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) && \
+      (tmpoptions != I2C_NO_OPTION_FRAME))
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+    /* Call I2C Slave Sequential complete process */
+    I2C_ITSlaveSeqCplt(hi2c);
+  }
+  else
+  {
+    /* No specific action, Master fully manage the generation of STOP condition */
+    /* Mean that this generation can arrive at any time, at the end or during DMA process */
+    /* So STOP condition should be manage through Interrupt treatment */
+  }
+}
+
+/**
+  * @brief  DMA I2C communication error callback.
+  * @param hdma DMA handle
+  * @retval None
+  */
+static void I2C_DMAError(DMA_HandleTypeDef *hdma)
+{
+  uint32_t treatdmaerror = 0U;
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+
+  if (hi2c->hdmatx != NULL)
+  {
+    if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U)
+    {
+      treatdmaerror = 1U;
+    }
+  }
+
+  if (hi2c->hdmarx != NULL)
+  {
+    if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U)
+    {
+      treatdmaerror = 1U;
+    }
+  }
+
+  /* Check if a FIFO error is detected, if true normal use case, so no specific action to perform */
+  if (!((HAL_DMA_GetError(hdma) == HAL_DMA_ERROR_FE)) && (treatdmaerror != 0U))
+  {
+    /* Disable Acknowledge */
+    hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+  }
+}
+
+/**
+  * @brief DMA I2C communication abort callback
+  *        (To be called at end of DMA Abort procedure).
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
+{
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+
+  /* Reset AbortCpltCallback */
+  if (hi2c->hdmatx != NULL)
+  {
+    hi2c->hdmatx->XferAbortCallback = NULL;
+  }
+  if (hi2c->hdmarx != NULL)
+  {
+    hi2c->hdmarx->XferAbortCallback = NULL;
+  }
+
+  I2C_TreatErrorCallback(hi2c);
+}
+
+/**
+  * @brief  This function handles I2C Communication Timeout.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Flag Specifies the I2C flag to check.
+  * @param  Status The new Flag status (SET or RESET).
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
+{
+  while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
+  {
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+      {
+        hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+        hi2c->State = HAL_I2C_STATE_READY;
+        hi2c->Mode = HAL_I2C_MODE_NONE;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        return HAL_ERROR;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles I2C Communication Timeout for specific usage of TXIS flag.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+{
+  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
+  {
+    /* Check if a NACK is detected */
+    if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+      {
+        hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+        hi2c->State = HAL_I2C_STATE_READY;
+        hi2c->Mode = HAL_I2C_MODE_NONE;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles I2C Communication Timeout for specific usage of STOP flag.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+{
+  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+  {
+    /* Check if a NACK is detected */
+    if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Check for the Timeout */
+    if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+    {
+      hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+      hi2c->State = HAL_I2C_STATE_READY;
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles I2C Communication Timeout for specific usage of RXNE flag.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+{
+  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
+  {
+    /* Check if a NACK is detected */
+    if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Check if a STOPF is detected */
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
+    {
+      /* Check if an RXNE is pending */
+      /* Store Last receive data if any */
+      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U))
+      {
+        /* Return HAL_OK */
+        /* The Reading of data from RXDR will be done in caller function */
+        return HAL_OK;
+      }
+      else
+      {
+        /* Clear STOP Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+        /* Clear Configuration Register 2 */
+        I2C_RESET_CR2(hi2c);
+
+        hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+        hi2c->State = HAL_I2C_STATE_READY;
+        hi2c->Mode = HAL_I2C_MODE_NONE;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+
+    /* Check for the Timeout */
+    if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+    {
+      hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+      hi2c->State = HAL_I2C_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles Acknowledge failed detection during an I2C Communication.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+{
+  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+  {
+    /* Wait until STOP Flag is reset */
+    /* AutoEnd should be initiate after AF */
+    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+    {
+      /* Check for the Timeout */
+      if (Timeout != HAL_MAX_DELAY)
+      {
+        if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+        {
+          hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+          hi2c->State = HAL_I2C_STATE_READY;
+          hi2c->Mode = HAL_I2C_MODE_NONE;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2c);
+
+          return HAL_ERROR;
+        }
+      }
+    }
+
+    /* Clear NACKF Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    /* Clear STOP Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Flush TX register */
+    I2C_Flush_TXDR(hi2c);
+
+    /* Clear Configuration Register 2 */
+    I2C_RESET_CR2(hi2c);
+
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_ERROR;
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
+  * @param  hi2c I2C handle.
+  * @param  DevAddress Specifies the slave address to be programmed.
+  * @param  Size Specifies the number of bytes to be programmed.
+  *   This parameter must be a value between 0 and 255.
+  * @param  Mode New state of the I2C START condition generation.
+  *   This parameter can be one of the following values:
+  *     @arg @ref I2C_RELOAD_MODE Enable Reload mode .
+  *     @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.
+  *     @arg @ref I2C_SOFTEND_MODE Enable Software end mode.
+  * @param  Request New state of the I2C START condition generation.
+  *   This parameter can be one of the following values:
+  *     @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.
+  *     @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
+  *     @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
+  *     @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
+  * @retval None
+  */
+static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  assert_param(IS_TRANSFER_MODE(Mode));
+  assert_param(IS_TRANSFER_REQUEST(Request));
+
+  /* update CR2 register */
+  MODIFY_REG(hi2c->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \
+             (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
+}
+
+/**
+  * @brief  Manage the enabling of Interrupts.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
+  * @retval None
+  */
+static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
+{
+  uint32_t tmpisr = 0U;
+
+  if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \
+      (hi2c->XferISR == I2C_Slave_ISR_DMA))
+  {
+    if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+    {
+      /* Enable ERR, STOP, NACK and ADDR interrupts */
+      tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+    }
+
+    if (InterruptRequest == I2C_XFER_ERROR_IT)
+    {
+      /* Enable ERR and NACK interrupts */
+      tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
+    }
+
+    if (InterruptRequest == I2C_XFER_CPLT_IT)
+    {
+      /* Enable STOP interrupts */
+      tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
+    }
+
+    if (InterruptRequest == I2C_XFER_RELOAD_IT)
+    {
+      /* Enable TC interrupts */
+      tmpisr |= I2C_IT_TCI;
+    }
+  }
+  else
+  {
+    if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+    {
+      /* Enable ERR, STOP, NACK, and ADDR interrupts */
+      tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+    }
+
+    if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
+    {
+      /* Enable ERR, TC, STOP, NACK and RXI interrupts */
+      tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
+    }
+
+    if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
+    {
+      /* Enable ERR, TC, STOP, NACK and TXI interrupts */
+      tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
+    }
+
+    if (InterruptRequest == I2C_XFER_CPLT_IT)
+    {
+      /* Enable STOP interrupts */
+      tmpisr |= I2C_IT_STOPI;
+    }
+  }
+
+  /* Enable interrupts only at the end */
+  /* to avoid the risk of I2C interrupt handle execution before */
+  /* all interrupts requested done */
+  __HAL_I2C_ENABLE_IT(hi2c, tmpisr);
+}
+
+/**
+  * @brief  Manage the disabling of Interrupts.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
+  * @retval None
+  */
+static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
+{
+  uint32_t tmpisr = 0U;
+
+  if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
+  {
+    /* Disable TC and TXI interrupts */
+    tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
+
+    if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
+    {
+      /* Disable NACK and STOP interrupts */
+      tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+    }
+  }
+
+  if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
+  {
+    /* Disable TC and RXI interrupts */
+    tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
+
+    if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
+    {
+      /* Disable NACK and STOP interrupts */
+      tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+    }
+  }
+
+  if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+  {
+    /* Disable ADDR, NACK and STOP interrupts */
+    tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+  }
+
+  if (InterruptRequest == I2C_XFER_ERROR_IT)
+  {
+    /* Enable ERR and NACK interrupts */
+    tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
+  }
+
+  if (InterruptRequest == I2C_XFER_CPLT_IT)
+  {
+    /* Enable STOP interrupts */
+    tmpisr |= I2C_IT_STOPI;
+  }
+
+  if (InterruptRequest == I2C_XFER_RELOAD_IT)
+  {
+    /* Enable TC interrupts */
+    tmpisr |= I2C_IT_TCI;
+  }
+
+  /* Disable interrupts only at the end */
+  /* to avoid a breaking situation like at "t" time */
+  /* all disable interrupts request are not done */
+  __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
+}
+
+/**
+  * @brief  Convert I2Cx OTHER_xxx XferOptions to functionnal XferOptions.
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
+{
+  /* if user set XferOptions to I2C_OTHER_FRAME            */
+  /* it request implicitly to generate a restart condition */
+  /* set XferOptions to I2C_FIRST_FRAME                    */
+  if (hi2c->XferOptions == I2C_OTHER_FRAME)
+  {
+    hi2c->XferOptions = I2C_FIRST_FRAME;
+  }
+  /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
+  /* it request implicitly to generate a restart condition    */
+  /* then generate a stop condition at the end of transfer    */
+  /* set XferOptions to I2C_FIRST_AND_LAST_FRAME              */
+  else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
+  {
+    hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_I2C_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c
new file mode 100644
index 00000000..ea50ce31
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c
@@ -0,0 +1,339 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_i2c_ex.c
+  * @author  MCD Application Team
+  * @brief   I2C Extended HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of I2C Extended peripheral:
+  *           + Extended features functions
+  *
+  @verbatim
+  ==============================================================================
+               ##### I2C peripheral Extended features  #####
+  ==============================================================================
+
+  [..] Comparing to other previous devices, the I2C interface for STM32H7xx
+       devices contains the following additional features
+
+       (+) Possibility to disable or enable Analog Noise Filter
+       (+) Use of a configured Digital Noise Filter
+       (+) Disable or enable wakeup from Stop mode(s)
+       (+) Disable or enable Fast Mode Plus
+
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..] This driver provides functions to configure Noise Filter and Wake Up Feature
+    (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
+    (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
+    (#) Configure the enable or disable of I2C Wake Up Mode using the functions :
+          (++) HAL_I2CEx_EnableWakeUp()
+          (++) HAL_I2CEx_DisableWakeUp()
+    (#) Configure the enable or disable of fast mode plus driving capability using the functions :
+          (++) HAL_I2CEx_EnableFastModePlus()
+          (++) HAL_I2CEx_DisableFastModePlus()
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup I2CEx I2CEx
+  * @brief I2C Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions
+  * @brief    Extended features functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### Extended features functions #####
+ ===============================================================================
+    [..] This section provides functions allowing to:
+      (+) Configure Noise Filters
+      (+) Configure Wake Up Feature
+      (+) Configure Fast Mode Plus
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure I2C Analog noise filter.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2Cx peripheral.
+  * @param  AnalogFilter New state of the Analog filter.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+
+    /* Disable the selected I2C peripheral */
+    __HAL_I2C_DISABLE(hi2c);
+
+    /* Reset I2Cx ANOFF bit */
+    hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
+
+    /* Set analog filter bit*/
+    hi2c->Instance->CR1 |= AnalogFilter;
+
+    __HAL_I2C_ENABLE(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Configure I2C Digital noise filter.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2Cx peripheral.
+  * @param  DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
+{
+  uint32_t tmpreg;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+
+    /* Disable the selected I2C peripheral */
+    __HAL_I2C_DISABLE(hi2c);
+
+    /* Get the old register value */
+    tmpreg = hi2c->Instance->CR1;
+
+    /* Reset I2Cx DNF bits [11:8] */
+    tmpreg &= ~(I2C_CR1_DNF);
+
+    /* Set I2Cx DNF coefficient */
+    tmpreg |= DigitalFilter << 8U;
+
+    /* Store the new register value */
+    hi2c->Instance->CR1 = tmpreg;
+
+    __HAL_I2C_ENABLE(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Enable I2C wakeup from Stop mode(s).
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2Cx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+
+    /* Disable the selected I2C peripheral */
+    __HAL_I2C_DISABLE(hi2c);
+
+    /* Enable wakeup from stop mode */
+    hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
+
+    __HAL_I2C_ENABLE(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Disable I2C wakeup from Stop mode(s).
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2Cx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+
+    /* Disable the selected I2C peripheral */
+    __HAL_I2C_DISABLE(hi2c);
+
+    /* Enable wakeup from stop mode */
+    hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
+
+    __HAL_I2C_ENABLE(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Enable the I2C fast mode plus driving capability.
+  * @param ConfigFastModePlus Selects the pin.
+  *   This parameter can be one of the @ref I2CEx_FastModePlus values
+  * @note  For I2C1, fast mode plus driving capability can be enabled on all selected
+  *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
+  *        on each one of the following pins PB6, PB7, PB8 and PB9.
+  * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
+  *        can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
+  * @note  For all I2C2 pins fast mode plus driving capability can be enabled
+  *        only by using I2C_FASTMODEPLUS_I2C2 parameter.
+  * @note  For all I2C3 pins fast mode plus driving capability can be enabled
+  *        only by using I2C_FASTMODEPLUS_I2C3 parameter.
+  * @note  For all I2C4 pins fast mode plus driving capability can be enabled
+  *        only by using I2C_FASTMODEPLUS_I2C4 parameter.
+  * @retval None
+  */
+void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
+{
+  /* Check the parameter */
+  assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
+
+  /* Enable SYSCFG clock */
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+  /* Enable fast mode plus driving capability for selected pin */
+  SET_BIT(SYSCFG->PMCR, (uint32_t)ConfigFastModePlus);
+}
+
+/**
+  * @brief Disable the I2C fast mode plus driving capability.
+  * @param ConfigFastModePlus Selects the pin.
+  *   This parameter can be one of the @ref I2CEx_FastModePlus values
+  * @note  For I2C1, fast mode plus driving capability can be disabled on all selected
+  *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
+  *        on each one of the following pins PB6, PB7, PB8 and PB9.
+  * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
+  *        can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
+  * @note  For all I2C2 pins fast mode plus driving capability can be disabled
+  *        only by using I2C_FASTMODEPLUS_I2C2 parameter.
+  * @note  For all I2C3 pins fast mode plus driving capability can be disabled
+  *        only by using I2C_FASTMODEPLUS_I2C3 parameter.
+  * @note  For all I2C4 pins fast mode plus driving capability can be disabled
+  *        only by using I2C_FASTMODEPLUS_I2C4 parameter.
+  * @retval None
+  */
+void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
+{
+  /* Check the parameter */
+  assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
+
+  /* Enable SYSCFG clock */
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+  /* Disable fast mode plus driving capability for selected pin */
+  CLEAR_BIT(SYSCFG->PMCR, (uint32_t)ConfigFastModePlus);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_I2C_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c
new file mode 100644
index 00000000..08498c46
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c
@@ -0,0 +1,1901 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_mdma.c
+  * @author  MCD Application Team
+  * @brief  This file provides firmware functions to manage the following
+  *         functionalities of the Master Direct Memory Access (MDMA) peripheral:
+  *           + Initialization/de-initialization functions
+  *           + I/O operation functions
+  *           + Peripheral State and errors functions
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+   (#) Enable and configure the peripheral to be connected to the MDMA Channel
+       (except for internal SRAM/FLASH memories: no initialization is
+       necessary) please refer to Reference manual for connection between peripherals
+       and MDMA requests.
+
+   (#)
+       For a given Channel use HAL_MDMA_Init function to program the required configuration through the following parameters:
+       transfer request , channel priority, data endianness, Source increment, destination increment ,
+       source data size, destination data size, data alignment, source Burst, destination Burst ,
+       buffer Transfer Length, Transfer Trigger Mode (buffer transfer, block transfer, repeated block transfer
+       or full transfer) source and destination block address offset, mask address and data.
+
+       If using the MDMA in linked list mode then use function HAL_MDMA_LinkedList_CreateNode to fill a transfer node.
+       Note that parameters given to the function HAL_MDMA_Init corresponds always to the node zero.
+       Use function HAL_MDMA_LinkedList_AddNode to connect the created node to the linked list at a given position.
+       User can make a linked list circular using function HAL_MDMA_LinkedList_EnableCircularMode , this function will automatically connect the
+       last node of the list to the first one in order to make the list circular.
+       In this case the linked list will loop on node 1 : first node connected after the initial transfer defined by the HAL_MDMA_Init
+
+      -@-   The initial transfer itself (node 0 corresponding to the Init).
+            User can disable the circular mode using function HAL_MDMA_LinkedList_DisableCircularMode, this function will then remove
+            the connection between last node and first one.
+
+       Function HAL_MDMA_LinkedList_RemoveNode can be used to remove (disconnect) a node from the transfer linked list.
+       When a linked list is circular (last node connected to first one), if removing node1  (node where the linked list loops),
+       the linked list remains circular and node 2 becomes the first one.
+       Note that if the linked list is made circular the transfer will loop infinitely (or until aborted by the user).
+
+    [..]
+       (+) User can select the transfer trigger mode (parameter TransferTriggerMode) to define the amount of data to be
+           transfer upon a request :
+             (++) MDMA_BUFFER_TRANSFER : each request triggers a transfer of BufferTransferLength data
+               with BufferTransferLength defined within the HAL_MDMA_Init.
+             (++) MDMA_BLOCK_TRANSFER : each request triggers a transfer of a block
+               with block size defined within the function HAL_MDMA_Start/HAL_MDMA_Start_IT
+               or within the current linked list node parameters.
+             (++) MDMA_REPEAT_BLOCK_TRANSFER : each request triggers a transfer of a number of blocks
+               with block size and number of blocks defined within the function HAL_MDMA_Start/HAL_MDMA_Start_IT
+               or within the current linked list node parameters.
+             (++) MDMA_FULL_TRANSFER : each request triggers a full transfer
+              all blocks and all nodes(if a linked list has been created using HAL_MDMA_LinkedList_CreateNode \ HAL_MDMA_LinkedList_AddNode).
+
+     *** Polling mode IO operation ***
+     =================================
+    [..]
+          (+) Use HAL_MDMA_Start() to start MDMA transfer after the configuration of Source
+              address and destination address and the Length of data to be transferred.
+          (+) Use HAL_MDMA_PollForTransfer() to poll for the end of current transfer or a transfer level
+             In this case a fixed Timeout can be configured by User depending from his application.
+          (+) Use HAL_MDMA_Abort() function to abort the current transfer : blocking method this API returns
+              when the abort ends or timeout (should not be called from an interrupt service routine).
+
+     *** Interrupt mode IO operation ***
+     ===================================
+    [..]
+          (+) Configure the MDMA interrupt priority using HAL_NVIC_SetPriority()
+          (+) Enable the MDMA IRQ handler using HAL_NVIC_EnableIRQ()
+          (+) Use HAL_MDMA_Start_IT() to start MDMA transfer after the configuration of
+              Source address and destination address and the Length of data to be transferred. In this
+              case the MDMA interrupt is configured.
+          (+) Use HAL_MDMA_IRQHandler() called under MDMA_IRQHandler() Interrupt subroutine
+          (+) At the end of data transfer HAL_MDMA_IRQHandler() function is executed and user can
+              add his own function by customization of function pointer XferCpltCallback and
+              XferErrorCallback (i.e a member of MDMA handle structure).
+
+          (+) Use HAL_MDMA_Abort_IT() function to abort the current transfer : non-blocking method. This API will finish the execution immediately
+              then the callback XferAbortCallback (if specified  by the user) is asserted once the MDMA channel has effectively aborted.
+              (could be called from an interrupt service routine).
+
+          (+) Use functions HAL_MDMA_RegisterCallback and HAL_MDMA_UnRegisterCallback respectevely to register unregister user callbacks
+              from the following list :
+              (++) XferCpltCallback            : transfer complete callback.
+              (++) XferBufferCpltCallback      : buffer transfer complete callback.
+              (++) XferBlockCpltCallback       : block transfer complete callback.
+              (++) XferRepeatBlockCpltCallback : repeated block transfer complete callback.
+              (++) XferErrorCallback           : transfer error callback.
+              (++) XferAbortCallback           : transfer abort complete callback.
+
+    [..]
+         (+)  If the transfer Request corresponds to SW request (MDMA_REQUEST_SW) User can use function HAL_MDMA_GenerateSWRequest to
+              trigger requests manually. Function HAL_MDMA_GenerateSWRequest must be used with the following precautions:
+              (++) This function returns an error if used while the Transfer has ended or not started.
+              (++) If used while the current request has not been served yet (current request transfer on going)
+                this function returns an error and the new request is ignored.
+
+              Generally this function should be used in conjunctions with the MDMA callbacks:
+              (++) example 1:
+                 (+++) Configure a transfer with request set to MDMA_REQUEST_SW and trigger mode set to MDMA_BUFFER_TRANSFER
+                 (+++) Register a callback for buffer transfer complete (using callback ID set to HAL_MDMA_XFER_BUFFERCPLT_CB_ID)
+                 (+++) After calling HAL_MDMA_Start_IT the MDMA will issue the transfer of a first BufferTransferLength data.
+                 (+++) When the buffer transfer complete callback is asserted first buffer has been transferred and user can ask for a new buffer transfer
+                   request using HAL_MDMA_GenerateSWRequest.
+
+              (++) example 2:
+                 (+++) Configure a transfer with request set to MDMA_REQUEST_SW and trigger mode set to MDMA_BLOCK_TRANSFER
+                 (+++) Register a callback for block transfer complete (using callback ID HAL_MDMA_XFER_BLOCKCPLT_CB_ID)
+                 (+++) After calling HAL_MDMA_Start_IT the MDMA will issue the transfer of a first block of data.
+                 (+++) When the block transfer complete callback is asserted the first block has been transferred and user can ask
+                   for a new block transfer request using HAL_MDMA_GenerateSWRequest.
+
+    [..]  Use HAL_MDMA_GetState() function to return the MDMA state and HAL_MDMA_GetError() in case of error detection.
+
+     *** MDMA HAL driver macros list ***
+     =============================================
+     [..]
+       Below the list of most used macros in MDMA HAL driver.
+
+      (+) __HAL_MDMA_ENABLE: Enable the specified MDMA Channel.
+      (+) __HAL_MDMA_DISABLE: Disable the specified MDMA Channel.
+      (+) __HAL_MDMA_GET_FLAG: Get the MDMA Channel pending flags.
+      (+) __HAL_MDMA_CLEAR_FLAG: Clear the MDMA Channel pending flags.
+      (+) __HAL_MDMA_ENABLE_IT: Enable the specified MDMA Channel interrupts.
+      (+) __HAL_MDMA_DISABLE_IT: Disable the specified MDMA Channel interrupts.
+      (+) __HAL_MDMA_GET_IT_SOURCE: Check whether the specified MDMA Channel interrupt has occurred or not.
+
+     [..]
+      (@) You can refer to the header file of the MDMA HAL driver for more useful macros.
+
+    [..]
+
+    @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup MDMA  MDMA
+  * @brief MDMA HAL module driver
+  * @{
+  */
+
+#ifdef HAL_MDMA_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup MDMA_Private_Constants
+ * @{
+ */
+#define HAL_TIMEOUT_MDMA_ABORT    5U    /* 5 ms */
+#define HAL_MDMA_CHANNEL_SIZE     0x40U /* an MDMA instance channel size is 64 byte  */
+/**
+  * @}
+  */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup MDMA_Private_Functions_Prototypes
+  * @{
+  */
+static void MDMA_SetConfig(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount);
+static void MDMA_Init(MDMA_HandleTypeDef *hmdma);
+
+/**
+  * @}
+  */
+
+/** @addtogroup MDMA_Exported_Functions MDMA Exported Functions
+  * @{
+  */
+
+/** @addtogroup MDMA_Exported_Functions_Group1
+  *
+@verbatim
+ ===============================================================================
+             ##### Initialization and de-initialization functions  #####
+ ===============================================================================
+    [..]
+    This section provides functions allowing to :
+      Initialize and de-initialize the MDMA channel.
+      Register and Unregister MDMA callbacks
+    [..]
+    The HAL_MDMA_Init() function follows the MDMA channel configuration procedures as described in
+    reference manual.
+    The HAL_MDMA_DeInit function allows to deinitialize the MDMA channel.
+    HAL_MDMA_RegisterCallback and  HAL_MDMA_UnRegisterCallback functions allows
+    respectevely to register/unregister an MDMA callback function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the MDMA according to the specified
+  *         parameters in the MDMA_InitTypeDef and create the associated handle.
+  * @param  hmdma: Pointer to a MDMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified MDMA Channel.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_Init(MDMA_HandleTypeDef *hmdma)
+{
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_MDMA_STREAM_ALL_INSTANCE(hmdma->Instance));
+  assert_param(IS_MDMA_PRIORITY(hmdma->Init.Priority));
+  assert_param(IS_MDMA_ENDIANNESS_MODE(hmdma->Init.Endianness));
+  assert_param(IS_MDMA_REQUEST(hmdma->Init.Request));
+  assert_param(IS_MDMA_SOURCE_INC(hmdma->Init.SourceInc));
+  assert_param(IS_MDMA_DESTINATION_INC(hmdma->Init.DestinationInc));
+  assert_param(IS_MDMA_SOURCE_DATASIZE(hmdma->Init.SourceDataSize));
+  assert_param(IS_MDMA_DESTINATION_DATASIZE(hmdma->Init.DestDataSize));
+  assert_param(IS_MDMA_DATA_ALIGNMENT(hmdma->Init.DataAlignment));
+  assert_param(IS_MDMA_SOURCE_BURST(hmdma->Init.SourceBurst));
+  assert_param(IS_MDMA_DESTINATION_BURST(hmdma->Init.DestBurst));
+  assert_param(IS_MDMA_BUFFER_TRANSFER_LENGTH(hmdma->Init.BufferTransferLength));
+  assert_param(IS_MDMA_TRANSFER_TRIGGER_MODE(hmdma->Init.TransferTriggerMode));
+  assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(hmdma->Init.SourceBlockAddressOffset));
+  assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(hmdma->Init.DestBlockAddressOffset));
+
+
+  /* Allocate lock resource */
+  __HAL_UNLOCK(hmdma);
+
+  /* Change MDMA peripheral state */
+  hmdma->State = HAL_MDMA_STATE_BUSY;
+
+  /* Disable the MDMA channel */
+  __HAL_MDMA_DISABLE(hmdma);
+
+  /* Check if the MDMA channel is effectively disabled */
+  while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U)
+  {
+    /* Check for the Timeout */
+    if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_MDMA_ABORT)
+    {
+      /* Update error code */
+      hmdma->ErrorCode = HAL_MDMA_ERROR_TIMEOUT;
+
+      /* Change the MDMA state */
+      hmdma->State = HAL_MDMA_STATE_ERROR;
+
+      return HAL_ERROR;
+    }
+  }
+
+  /* Initialize the MDMA channel registers */
+  MDMA_Init(hmdma);
+
+  /* Reset the MDMA first/last linkedlist node addresses and node counter */
+  hmdma->FirstLinkedListNodeAddress  = 0;
+  hmdma->LastLinkedListNodeAddress   = 0;
+  hmdma->LinkedListNodeCounter  = 0;
+
+  /* Initialize the error code */
+  hmdma->ErrorCode = HAL_MDMA_ERROR_NONE;
+
+  /* Initialize the MDMA state */
+  hmdma->State = HAL_MDMA_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the MDMA peripheral
+  * @param  hmdma: pointer to a MDMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified MDMA Channel.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_DeInit(MDMA_HandleTypeDef *hmdma)
+{
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Disable the selected MDMA Channelx */
+  __HAL_MDMA_DISABLE(hmdma);
+
+  /* Reset MDMA Channel control register */
+  hmdma->Instance->CCR  = 0;
+  hmdma->Instance->CTCR = 0;
+  hmdma->Instance->CBNDTR = 0;
+  hmdma->Instance->CSAR = 0;
+  hmdma->Instance->CDAR = 0;
+  hmdma->Instance->CBRUR = 0;
+  hmdma->Instance->CLAR = 0;
+  hmdma->Instance->CTBR = 0;
+  hmdma->Instance->CMAR = 0;
+  hmdma->Instance->CMDR = 0;
+
+  /* Clear all flags */
+  __HAL_MDMA_CLEAR_FLAG(hmdma,(MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_FLAG_BRT | MDMA_FLAG_BT | MDMA_FLAG_BFTC));
+
+  /* Reset the  MDMA first/last linkedlist node addresses and node counter */
+  hmdma->FirstLinkedListNodeAddress  = 0;
+  hmdma->LastLinkedListNodeAddress   = 0;
+  hmdma->LinkedListNodeCounter  = 0;
+
+  /* Initialize the error code */
+  hmdma->ErrorCode = HAL_MDMA_ERROR_NONE;
+
+  /* Initialize the MDMA state */
+  hmdma->State = HAL_MDMA_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hmdma);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Config the Post request Mask address and Mask data
+  * @param  hmdma      : pointer to a MDMA_HandleTypeDef structure that contains
+  *                               the configuration information for the specified MDMA Channel.
+  * @param  MaskAddress: specifies the address to be updated (written) with MaskData after a request is served.
+  * @param  MaskData:    specifies the value to be written to MaskAddress after a request is served.
+  *                      MaskAddress and MaskData could be used to automatically clear a peripheral flag when the request is served.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_ConfigPostRequestMask(MDMA_HandleTypeDef *hmdma, uint32_t MaskAddress, uint32_t MaskData)
+{
+  HAL_StatusTypeDef  status = HAL_OK;
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hmdma);
+
+  if(HAL_MDMA_STATE_READY == hmdma->State)
+  {
+    /* if HW request set Post Request MaskAddress and MaskData,  */
+    if((hmdma->Instance->CTCR & MDMA_CTCR_SWRM) == 0U)
+    {
+      /* Set the HW request clear Mask and Data */
+      hmdma->Instance->CMAR = MaskAddress;
+      hmdma->Instance->CMDR = MaskData;
+
+      /*
+      -If the request is done by SW : BWM could be set to 1 or 0.
+      -If the request is done by a peripheral :
+         If mask address not set (0) => BWM must be set to 0
+         If mask address set (different than 0) => BWM could be set to 1 or 0
+      */
+      if(MaskAddress == 0U)
+      {
+        hmdma->Instance->CTCR &=  ~MDMA_CTCR_BWM;
+      }
+      else
+      {
+        hmdma->Instance->CTCR |=  MDMA_CTCR_BWM;
+      }
+    }
+    else
+    {
+      /* Return error status */
+      status =  HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+  /* Release Lock */
+  __HAL_UNLOCK(hmdma);
+
+  return status;
+}
+
+/**
+  * @brief  Register callbacks
+  * @param  hmdma:                pointer to a MDMA_HandleTypeDef structure that contains
+  *                               the configuration information for the specified MDMA Channel.
+  * @param  CallbackID:           User Callback identifier
+  * @param  pCallback:            pointer to callbacsk function.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_RegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID, void (* pCallback)(MDMA_HandleTypeDef *_hmdma))
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hmdma);
+
+  if(HAL_MDMA_STATE_READY == hmdma->State)
+  {
+    switch (CallbackID)
+    {
+    case  HAL_MDMA_XFER_CPLT_CB_ID:
+      hmdma->XferCpltCallback = pCallback;
+      break;
+
+    case  HAL_MDMA_XFER_BUFFERCPLT_CB_ID:
+      hmdma->XferBufferCpltCallback = pCallback;
+      break;
+
+    case  HAL_MDMA_XFER_BLOCKCPLT_CB_ID:
+      hmdma->XferBlockCpltCallback = pCallback;
+      break;
+
+    case  HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID:
+      hmdma->XferRepeatBlockCpltCallback = pCallback;
+      break;
+
+    case  HAL_MDMA_XFER_ERROR_CB_ID:
+      hmdma->XferErrorCallback = pCallback;
+      break;
+
+    case  HAL_MDMA_XFER_ABORT_CB_ID:
+      hmdma->XferAbortCallback = pCallback;
+      break;
+
+    default:
+      break;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hmdma);
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister callbacks
+  * @param  hmdma:                 pointer to a MDMA_HandleTypeDef structure that contains
+  *                               the configuration information for the specified MDMA Channel.
+  * @param  CallbackID:           User Callback identifier
+  *                               a HAL_MDMA_CallbackIDTypeDef ENUM as parameter.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_UnRegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hmdma);
+
+  if(HAL_MDMA_STATE_READY == hmdma->State)
+  {
+    switch (CallbackID)
+    {
+    case  HAL_MDMA_XFER_CPLT_CB_ID:
+      hmdma->XferCpltCallback = NULL;
+      break;
+
+    case  HAL_MDMA_XFER_BUFFERCPLT_CB_ID:
+      hmdma->XferBufferCpltCallback = NULL;
+      break;
+
+    case  HAL_MDMA_XFER_BLOCKCPLT_CB_ID:
+      hmdma->XferBlockCpltCallback = NULL;
+      break;
+
+    case  HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID:
+      hmdma->XferRepeatBlockCpltCallback = NULL;
+      break;
+
+    case  HAL_MDMA_XFER_ERROR_CB_ID:
+      hmdma->XferErrorCallback = NULL;
+      break;
+
+    case  HAL_MDMA_XFER_ABORT_CB_ID:
+      hmdma->XferAbortCallback = NULL;
+      break;
+
+    case   HAL_MDMA_XFER_ALL_CB_ID:
+      hmdma->XferCpltCallback = NULL;
+      hmdma->XferBufferCpltCallback = NULL;
+      hmdma->XferBlockCpltCallback = NULL;
+      hmdma->XferRepeatBlockCpltCallback = NULL;
+      hmdma->XferErrorCallback = NULL;
+      hmdma->XferAbortCallback = NULL;
+      break;
+
+    default:
+      status = HAL_ERROR;
+      break;
+    }
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hmdma);
+
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup MDMA_Exported_Functions_Group2
+ *
+@verbatim
+ ===============================================================================
+                      #####  Linked list operation functions  #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Create a linked list node
+      (+) Add a node to the MDMA linked list
+      (+) Remove a node from the MDMA linked list
+      (+) Enable/Disable linked list circular mode
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes an MDMA Link Node according to the specified
+  *         parameters in the pMDMA_LinkedListNodeConfig .
+  * @param  pNode: Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node
+  *         registers configurations.
+  * @param  pNodeConfig: Pointer to a MDMA_LinkNodeConfTypeDef structure that contains
+  *               the configuration information for the specified MDMA Linked List Node.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig)
+{
+  uint32_t addressMask;
+  uint32_t blockoffset;
+
+  /* Check the MDMA peripheral state */
+  if((pNode == NULL) || (pNodeConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_MDMA_PRIORITY(pNodeConfig->Init.Priority));
+  assert_param(IS_MDMA_ENDIANNESS_MODE(pNodeConfig->Init.Endianness));
+  assert_param(IS_MDMA_REQUEST(pNodeConfig->Init.Request));
+  assert_param(IS_MDMA_SOURCE_INC(pNodeConfig->Init.SourceInc));
+  assert_param(IS_MDMA_DESTINATION_INC(pNodeConfig->Init.DestinationInc));
+  assert_param(IS_MDMA_SOURCE_DATASIZE(pNodeConfig->Init.SourceDataSize));
+  assert_param(IS_MDMA_DESTINATION_DATASIZE(pNodeConfig->Init.DestDataSize));
+  assert_param(IS_MDMA_DATA_ALIGNMENT(pNodeConfig->Init.DataAlignment));
+  assert_param(IS_MDMA_SOURCE_BURST(pNodeConfig->Init.SourceBurst));
+  assert_param(IS_MDMA_DESTINATION_BURST(pNodeConfig->Init.DestBurst));
+  assert_param(IS_MDMA_BUFFER_TRANSFER_LENGTH(pNodeConfig->Init.BufferTransferLength));
+  assert_param(IS_MDMA_TRANSFER_TRIGGER_MODE(pNodeConfig->Init.TransferTriggerMode));
+  assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(pNodeConfig->Init.SourceBlockAddressOffset));
+  assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(pNodeConfig->Init.DestBlockAddressOffset));
+
+  assert_param(IS_MDMA_TRANSFER_LENGTH(pNodeConfig->BlockDataLength));
+  assert_param(IS_MDMA_BLOCK_COUNT(pNodeConfig->BlockCount));
+
+
+  /* Configure next Link node Address Register to zero */
+  pNode->CLAR =  0;
+
+  /* Configure the Link Node registers*/
+  pNode->CTBR   = 0;
+  pNode->CMAR   = 0;
+  pNode->CMDR   = 0;
+  pNode->Reserved = 0;
+
+  /* Write new CTCR Register value */
+  pNode->CTCR =  pNodeConfig->Init.SourceInc | pNodeConfig->Init.DestinationInc | \
+    pNodeConfig->Init.SourceDataSize | pNodeConfig->Init.DestDataSize           | \
+      pNodeConfig->Init.DataAlignment| pNodeConfig->Init.SourceBurst            | \
+        pNodeConfig->Init.DestBurst                                             | \
+          ((pNodeConfig->Init.BufferTransferLength - 1U) << MDMA_CTCR_TLEN_Pos) | \
+            pNodeConfig->Init.TransferTriggerMode;
+
+  /* If SW request set the CTCR register to SW Request Mode*/
+  if(pNodeConfig->Init.Request == MDMA_REQUEST_SW)
+  {
+    pNode->CTCR |= MDMA_CTCR_SWRM;
+  }
+
+  /*
+  -If the request is done by SW : BWM could be set to 1 or 0.
+  -If the request is done by a peripheral :
+     If mask address not set (0) => BWM must be set to 0
+     If mask address set (different than 0) => BWM could be set to 1 or 0
+  */
+  if((pNodeConfig->Init.Request == MDMA_REQUEST_SW) || (pNodeConfig->PostRequestMaskAddress != 0U))
+  {
+    pNode->CTCR |=  MDMA_CTCR_BWM;
+  }
+
+  /* Set the new CBNDTR Register value */
+  pNode->CBNDTR = ((pNodeConfig->BlockCount - 1U) << MDMA_CBNDTR_BRC_Pos) & MDMA_CBNDTR_BRC;
+
+  /* if block source address offset is negative set the Block Repeat Source address Update Mode to decrement */
+  if(pNodeConfig->Init.SourceBlockAddressOffset < 0)
+  {
+    pNode->CBNDTR |= MDMA_CBNDTR_BRSUM;
+    /*write new CBRUR Register value : source repeat block offset */
+    blockoffset = (uint32_t)(- pNodeConfig->Init.SourceBlockAddressOffset);
+    pNode->CBRUR = blockoffset & 0x0000FFFFU;
+  }
+  else
+  {
+    /*write new CBRUR Register value : source repeat block offset */
+    pNode->CBRUR = (((uint32_t) pNodeConfig->Init.SourceBlockAddressOffset) & 0x0000FFFFU);
+  }
+
+  /* if block destination address offset is negative set the Block Repeat destination address Update Mode to decrement */
+  if(pNodeConfig->Init.DestBlockAddressOffset < 0)
+  {
+    pNode->CBNDTR |= MDMA_CBNDTR_BRDUM;
+    /*write new CBRUR Register value : destination repeat block offset */
+    blockoffset = (uint32_t)(- pNodeConfig->Init.DestBlockAddressOffset);
+    pNode->CBRUR |= ((blockoffset & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos);
+  }
+  else
+  {
+    /*write new CBRUR Register value : destination repeat block offset */
+    pNode->CBRUR |= ((((uint32_t)pNodeConfig->Init.DestBlockAddressOffset) & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos);
+  }
+
+  /* Configure MDMA Link Node data length */
+  pNode->CBNDTR |=  pNodeConfig->BlockDataLength;
+
+  /* Configure MDMA Link Node destination address */
+  pNode->CDAR = pNodeConfig->DstAddress;
+
+  /* Configure MDMA Link Node Source address */
+  pNode->CSAR = pNodeConfig->SrcAddress;
+
+  /* if HW request set the HW request and the requet CleraMask and ClearData MaskData,  */
+  if(pNodeConfig->Init.Request != MDMA_REQUEST_SW)
+  {
+    /* Set the HW request in CTBR register  */
+    pNode->CTBR = pNodeConfig->Init.Request & MDMA_CTBR_TSEL;
+    /* Set the HW request clear Mask and Data */
+    pNode->CMAR = pNodeConfig->PostRequestMaskAddress;
+    pNode->CMDR = pNodeConfig->PostRequestMaskData;
+  }
+
+  addressMask = pNodeConfig->SrcAddress & 0xFF000000U;
+  if((addressMask == 0x20000000U) || (addressMask == 0x00000000U))
+  {
+    /*The AHBSbus is used as source (read operation) on channel x */
+    pNode->CTBR |= MDMA_CTBR_SBUS;
+  }
+
+  addressMask = pNodeConfig->DstAddress & 0xFF000000U;
+  if((addressMask == 0x20000000U) || (addressMask == 0x00000000U))
+  {
+    /*The AHB bus is used as destination (write operation) on channel x */
+    pNode->CTBR |= MDMA_CTBR_DBUS;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Connect a node to the linked list.
+  * @param  hmdma    : Pointer to a MDMA_HandleTypeDef structure that contains
+  *                    the configuration information for the specified MDMA Channel.
+  * @param  pNewNode : Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node
+  *                    to be add to the list.
+  * @param pPrevNode : Pointer to the new node position in the linked list or zero to insert the new node
+  *                    at the end of the list
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, MDMA_LinkNodeTypeDef *pPrevNode)
+{
+  MDMA_LinkNodeTypeDef *pNode;
+  uint32_t counter = 0, nodeInserted = 0;
+  HAL_StatusTypeDef hal_status = HAL_OK;
+
+  /* Check the MDMA peripheral handle */
+  if((hmdma == NULL) || (pNewNode == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hmdma);
+
+  if(HAL_MDMA_STATE_READY == hmdma->State)
+  {
+    /* Change MDMA peripheral state */
+    hmdma->State = HAL_MDMA_STATE_BUSY;
+
+    /* Check if this is the first node (after the Inititlization node) */
+    if((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U)
+    {
+      if(pPrevNode == NULL)
+      {
+        /* if this is the first node after the initialization
+        connect this node to the node 0 by updating
+        the MDMA channel CLAR register to this node address */
+        hmdma->Instance->CLAR = (uint32_t)pNewNode;
+        /* Set the MDMA handle First linked List node*/
+        hmdma->FirstLinkedListNodeAddress = pNewNode;
+
+        /*reset New node link */
+        pNewNode->CLAR = 0;
+
+        /* Update the Handle last node address */
+        hmdma->LastLinkedListNodeAddress = pNewNode;
+
+        hmdma->LinkedListNodeCounter = 1;
+      }
+      else
+      {
+        hal_status = HAL_ERROR;
+      }
+    }
+    else if(hmdma->FirstLinkedListNodeAddress != pNewNode)
+    {
+      /* Check if the node to insert already exists*/
+      pNode = hmdma->FirstLinkedListNodeAddress;
+      while((counter < hmdma->LinkedListNodeCounter) && (hal_status == HAL_OK))
+      {
+        if(pNode->CLAR == (uint32_t)pNewNode)
+        {
+          hal_status = HAL_ERROR; /* error this node already exist in the linked list and it is not first node */
+        }
+        pNode = (MDMA_LinkNodeTypeDef *)pNode->CLAR;
+        counter++;
+      }
+
+      if(hal_status == HAL_OK)
+      {
+        /* Check if the previous node is the last one in the current list or zero */
+        if((pPrevNode == hmdma->LastLinkedListNodeAddress) || (pPrevNode == NULL))
+        {
+          /* insert the new node at the end of the list */
+          pNewNode->CLAR = hmdma->LastLinkedListNodeAddress->CLAR;
+          hmdma->LastLinkedListNodeAddress->CLAR = (uint32_t)pNewNode;
+          /* Update the Handle last node address */
+          hmdma->LastLinkedListNodeAddress = pNewNode;
+          /* Increment the linked list node counter */
+          hmdma->LinkedListNodeCounter++;
+        }
+        else
+        {
+          /*insert the new node after the pPreviousNode node */
+          pNode = hmdma->FirstLinkedListNodeAddress;
+          counter = 0;
+          while((counter < hmdma->LinkedListNodeCounter) && (nodeInserted == 0U))
+          {
+            counter++;
+            if(pNode == pPrevNode)
+            {
+              /*Insert the new node after the previous one */
+              pNewNode->CLAR = pNode->CLAR;
+              pNode->CLAR = (uint32_t)pNewNode;
+              /* Increment the linked list node counter */
+              hmdma->LinkedListNodeCounter++;
+              nodeInserted = 1;
+            }
+            else
+            {
+              pNode = (MDMA_LinkNodeTypeDef *)pNode->CLAR;
+            }
+          }
+
+          if(nodeInserted == 0U)
+          {
+            hal_status = HAL_ERROR;
+          }
+        }
+      }
+    }
+    else
+    {
+      hal_status = HAL_ERROR;
+    }
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hmdma);
+
+    hmdma->State = HAL_MDMA_STATE_READY;
+
+    return hal_status;
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hmdma);
+
+    /* Return error status */
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Disconnect/Remove a node from the transfer linked list.
+  * @param  hmdma : Pointer to a MDMA_HandleTypeDef structure that contains
+  *                 the configuration information for the specified MDMA Channel.
+  * @param  pNode : Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node
+  *                 to be removed from the list.
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNode)
+{
+  MDMA_LinkNodeTypeDef *ptmpNode;
+  uint32_t counter = 0, nodeDeleted = 0;
+  HAL_StatusTypeDef hal_status = HAL_OK;
+
+  /* Check the MDMA peripheral handle */
+  if((hmdma == NULL) || (pNode == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hmdma);
+
+  if(HAL_MDMA_STATE_READY == hmdma->State)
+  {
+    /* Change MDMA peripheral state */
+    hmdma->State = HAL_MDMA_STATE_BUSY;
+
+    /* If first and last node are null (no nodes in the list) : return error*/
+    if(((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U) || ((uint32_t)hmdma->LastLinkedListNodeAddress == 0U) || (hmdma->LinkedListNodeCounter == 0U))
+    {
+      hal_status = HAL_ERROR;
+    }
+    else if(hmdma->FirstLinkedListNodeAddress == pNode) /* Deleting first node */
+    {
+      /* Delete 1st node */
+      if(hmdma->LastLinkedListNodeAddress == pNode)
+      {
+        /*if the last node is at the same time the first one (1 single node after the init node 0)
+        then update the last node too */
+
+        hmdma->FirstLinkedListNodeAddress = 0;
+        hmdma->LastLinkedListNodeAddress  = 0;
+        hmdma->LinkedListNodeCounter = 0;
+
+        hmdma->Instance->CLAR = 0;
+      }
+      else
+      {
+        if((uint32_t)hmdma->FirstLinkedListNodeAddress == hmdma->LastLinkedListNodeAddress->CLAR)
+        {
+          /* if last node is looping to first (circular list) one update the last node connection */
+          hmdma->LastLinkedListNodeAddress->CLAR = pNode->CLAR;
+        }
+
+        /* if deleting the first node after the initialization
+        connect the next node to the node 0 by updating
+        the MDMA channel CLAR register to this node address */
+        hmdma->Instance->CLAR = pNode->CLAR;
+        hmdma->FirstLinkedListNodeAddress = (MDMA_LinkNodeTypeDef *)hmdma->Instance->CLAR;
+        /* Update the Handle node counter */
+        hmdma->LinkedListNodeCounter--;
+      }
+    }
+    else /* Deleting any other node */
+    {
+      /*Deleted node is not the first one : find it  */
+      ptmpNode = hmdma->FirstLinkedListNodeAddress;
+      while((counter < hmdma->LinkedListNodeCounter) && (nodeDeleted == 0U))
+      {
+        counter++;
+        if(ptmpNode->CLAR == ((uint32_t)pNode))
+        {
+          /* if deleting the last node */
+          if(pNode == hmdma->LastLinkedListNodeAddress)
+          {
+            /*Update the linked list last node address in the handle*/
+            hmdma->LastLinkedListNodeAddress = ptmpNode;
+          }
+          /* update the next node link after deleting pMDMA_LinkedListNode */
+          ptmpNode->CLAR = pNode->CLAR;
+          nodeDeleted = 1;
+          /* Update the Handle node counter */
+          hmdma->LinkedListNodeCounter--;
+        }
+        else
+        {
+          ptmpNode = (MDMA_LinkNodeTypeDef *)ptmpNode->CLAR;
+        }
+      }
+
+      if(nodeDeleted == 0U)
+      {
+        /* last node reashed without finding the node to delete : return error */
+        hal_status = HAL_ERROR;
+      }
+    }
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hmdma);
+
+    hmdma->State = HAL_MDMA_STATE_READY;
+
+    return hal_status;
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hmdma);
+
+    /* Return error status */
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Make the linked list circular by connecting the last node to the first.
+  * @param  hmdma : Pointer to a MDMA_HandleTypeDef structure that contains
+  *                 the configuration information for the specified MDMA Channel.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_LinkedList_EnableCircularMode(MDMA_HandleTypeDef *hmdma)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hmdma);
+
+  if(HAL_MDMA_STATE_READY == hmdma->State)
+  {
+    /* Change MDMA peripheral state */
+    hmdma->State = HAL_MDMA_STATE_BUSY;
+
+    /* If first and last node are null (no nodes in the list) : return error*/
+    if(((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U) || ((uint32_t)hmdma->LastLinkedListNodeAddress == 0U) || (hmdma->LinkedListNodeCounter == 0U))
+    {
+      hal_status = HAL_ERROR;
+    }
+    else
+    {
+      /* to enable circular mode Last Node should be connected to first node */
+      hmdma->LastLinkedListNodeAddress->CLAR = (uint32_t)hmdma->FirstLinkedListNodeAddress;
+    }
+
+  }
+  /* Process unlocked */
+  __HAL_UNLOCK(hmdma);
+
+  hmdma->State = HAL_MDMA_STATE_READY;
+
+  return hal_status;
+}
+
+/**
+  * @brief  Disable the linked list circular mode by setting the last node connection to null
+  * @param  hmdma : Pointer to a MDMA_HandleTypeDef structure that contains
+  *                 the configuration information for the specified MDMA Channel.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_LinkedList_DisableCircularMode(MDMA_HandleTypeDef *hmdma)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hmdma);
+
+  if(HAL_MDMA_STATE_READY == hmdma->State)
+  {
+    /* Change MDMA peripheral state */
+    hmdma->State = HAL_MDMA_STATE_BUSY;
+
+    /* If first and last node are null (no nodes in the list) : return error*/
+    if(((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U) || ((uint32_t)hmdma->LastLinkedListNodeAddress == 0U) || (hmdma->LinkedListNodeCounter == 0U))
+    {
+      hal_status = HAL_ERROR;
+    }
+    else
+    {
+      /* to disable circular mode Last Node should be connected to NULL */
+      hmdma->LastLinkedListNodeAddress->CLAR = 0;
+    }
+
+  }
+  /* Process unlocked */
+  __HAL_UNLOCK(hmdma);
+
+  hmdma->State = HAL_MDMA_STATE_READY;
+
+  return hal_status;
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup MDMA_Exported_Functions_Group3
+ *
+@verbatim
+ ===============================================================================
+                      #####  IO operation functions  #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure the source, destination address and data length and Start MDMA transfer
+      (+) Configure the source, destination address and data length and
+          Start MDMA transfer with interrupt
+      (+) Abort MDMA transfer
+      (+) Poll for transfer complete
+      (+) Generate a SW request (when Request is set to MDMA_REQUEST_SW)
+      (+) Handle MDMA interrupt request
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the MDMA Transfer.
+  * @param  hmdma           : pointer to a MDMA_HandleTypeDef structure that contains
+  *                           the configuration information for the specified MDMA Channel.
+  * @param  SrcAddress      : The source memory Buffer address
+  * @param  DstAddress      : The destination memory Buffer address
+  * @param  BlockDataLength : The length of a block transfer in bytes
+  * @param  BlockCount      : The number of a blocks to be transfer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_Start(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
+{
+  /* Check the parameters */
+  assert_param(IS_MDMA_TRANSFER_LENGTH(BlockDataLength));
+  assert_param(IS_MDMA_BLOCK_COUNT(BlockCount));
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hmdma);
+
+  if(HAL_MDMA_STATE_READY == hmdma->State)
+  {
+    /* Change MDMA peripheral state */
+    hmdma->State = HAL_MDMA_STATE_BUSY;
+
+    /* Initialize the error code */
+    hmdma->ErrorCode = HAL_MDMA_ERROR_NONE;
+
+    /* Disable the peripheral */
+    __HAL_MDMA_DISABLE(hmdma);
+
+    /* Configure the source, destination address and the data length */
+    MDMA_SetConfig(hmdma, SrcAddress, DstAddress, BlockDataLength, BlockCount);
+
+    /* Enable the Peripheral */
+    __HAL_MDMA_ENABLE(hmdma);
+
+    if(hmdma->Init.Request == MDMA_REQUEST_SW)
+    {
+      /* activate If SW request mode*/
+      hmdma->Instance->CCR |=  MDMA_CCR_SWRQ;
+    }
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hmdma);
+
+    /* Return error status */
+    return HAL_BUSY;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the MDMA Transfer with interrupts enabled.
+  * @param  hmdma           : pointer to a MDMA_HandleTypeDef structure that contains
+  *                           the configuration information for the specified MDMA Channel.
+  * @param  SrcAddress      : The source memory Buffer address
+  * @param  DstAddress      : The destination memory Buffer address
+  * @param  BlockDataLength : The length of a block transfer in bytes
+  * @param  BlockCount      : The number of a blocks to be transfer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_Start_IT(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
+{
+  /* Check the parameters */
+  assert_param(IS_MDMA_TRANSFER_LENGTH(BlockDataLength));
+  assert_param(IS_MDMA_BLOCK_COUNT(BlockCount));
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hmdma);
+
+  if(HAL_MDMA_STATE_READY == hmdma->State)
+  {
+    /* Change MDMA peripheral state */
+    hmdma->State = HAL_MDMA_STATE_BUSY;
+
+    /* Initialize the error code */
+    hmdma->ErrorCode = HAL_MDMA_ERROR_NONE;
+
+    /* Disable the peripheral */
+    __HAL_MDMA_DISABLE(hmdma);
+
+    /* Configure the source, destination address and the data length */
+    MDMA_SetConfig(hmdma, SrcAddress, DstAddress, BlockDataLength, BlockCount);
+
+    /* Enable Common interrupts i.e Transfer Error IT and Channel Transfer Complete IT*/
+    __HAL_MDMA_ENABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC));
+
+    if(hmdma->XferBlockCpltCallback != NULL)
+    {
+      /* if Block transfer complete Callback is set enable the corresponding IT*/
+      __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BT);
+    }
+
+    if(hmdma->XferRepeatBlockCpltCallback != NULL)
+    {
+      /* if Repeated Block transfer complete Callback is set enable the corresponding IT*/
+      __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BRT);
+    }
+
+    if(hmdma->XferBufferCpltCallback != NULL)
+    {
+      /* if buffer transfer complete Callback is set enable the corresponding IT*/
+      __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BFTC);
+    }
+
+    /* Enable the Peripheral */
+    __HAL_MDMA_ENABLE(hmdma);
+
+    if(hmdma->Init.Request == MDMA_REQUEST_SW)
+    {
+      /* activate If SW request mode*/
+      hmdma->Instance->CCR |=  MDMA_CCR_SWRQ;
+    }
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hmdma);
+
+    /* Return error status */
+    return HAL_BUSY;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Aborts the MDMA Transfer.
+  * @param  hmdma  : pointer to a MDMA_HandleTypeDef structure that contains
+  *                 the configuration information for the specified MDMA Channel.
+  *
+  * @note  After disabling a MDMA Channel, a check for wait until the MDMA Channel is
+  *        effectively disabled is added. If a Channel is disabled
+  *        while a data transfer is ongoing, the current data will be transferred
+  *        and the Channel will be effectively disabled only after the transfer of
+  *        this single data is finished.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_Abort(MDMA_HandleTypeDef *hmdma)
+{
+  uint32_t tickstart =  HAL_GetTick();
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if(HAL_MDMA_STATE_BUSY != hmdma->State)
+  {
+    hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hmdma);
+
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Disable all the transfer interrupts */
+    __HAL_MDMA_DISABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC | MDMA_IT_BT | MDMA_IT_BRT | MDMA_IT_BFTC));
+
+    /* Disable the channel */
+    __HAL_MDMA_DISABLE(hmdma);
+
+    /* Check if the MDMA Channel is effectively disabled */
+    while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U)
+    {
+      /* Check for the Timeout */
+      if( (HAL_GetTick()  - tickstart ) > HAL_TIMEOUT_MDMA_ABORT)
+      {
+        /* Update error code */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_TIMEOUT;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hmdma);
+
+        /* Change the MDMA state */
+        hmdma->State = HAL_MDMA_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+    }
+
+    /* Clear all interrupt flags */
+    __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_FLAG_BT | MDMA_FLAG_BRT | MDMA_FLAG_BFTC));
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hmdma);
+
+    /* Change the MDMA state*/
+    hmdma->State = HAL_MDMA_STATE_READY;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Aborts the MDMA Transfer in Interrupt mode.
+  * @param  hmdma  : pointer to a MDMA_HandleTypeDef structure that contains
+  *                 the configuration information for the specified MDMA Channel.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_Abort_IT(MDMA_HandleTypeDef *hmdma)
+{
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if(HAL_MDMA_STATE_BUSY != hmdma->State)
+  {
+    /* No transfer ongoing */
+    hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER;
+
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Set Abort State  */
+    hmdma->State = HAL_MDMA_STATE_ABORT;
+
+    /* Disable the stream */
+    __HAL_MDMA_DISABLE(hmdma);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Polling for transfer complete.
+  * @param  hmdma:          pointer to a MDMA_HandleTypeDef structure that contains
+  *                        the configuration information for the specified MDMA Channel.
+  * @param  CompleteLevel: Specifies the MDMA level complete.
+  * @param  Timeout:       Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_PollForTransfer(MDMA_HandleTypeDef *hmdma, HAL_MDMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
+{
+  uint32_t levelFlag, errorFlag;
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param(IS_MDMA_LEVEL_COMPLETE(CompleteLevel));
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if(HAL_MDMA_STATE_BUSY != hmdma->State)
+  {
+    /* No transfer ongoing */
+    hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER;
+
+    return HAL_ERROR;
+  }
+
+  /* Get the level transfer complete flag */
+  levelFlag = ((CompleteLevel == HAL_MDMA_FULL_TRANSFER)  ? MDMA_FLAG_CTC  : \
+               (CompleteLevel == HAL_MDMA_BUFFER_TRANSFER)? MDMA_FLAG_BFTC : \
+               (CompleteLevel == HAL_MDMA_BLOCK_TRANSFER) ? MDMA_FLAG_BT   : \
+               MDMA_FLAG_BRT);
+
+
+  /* Get timeout */
+  tickstart = HAL_GetTick();
+
+  while(__HAL_MDMA_GET_FLAG(hmdma, levelFlag) == 0U)
+  {
+    if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_TE) != 0U))
+    {
+      /* Get the transfer error source flag */
+      errorFlag = hmdma->Instance->CESR;
+
+      if((errorFlag & MDMA_CESR_TED) == 0U)
+      {
+        /* Update error code : Read Transfer error  */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_READ_XFER;
+      }
+      else
+      {
+        /* Update error code : Write Transfer error */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_WRITE_XFER;
+      }
+
+      if((errorFlag & MDMA_CESR_TEMD) != 0U)
+      {
+        /* Update error code : Error Mask Data */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_MASK_DATA;
+      }
+
+      if((errorFlag & MDMA_CESR_TELD) != 0U)
+      {
+        /* Update error code : Error Linked list */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_LINKED_LIST;
+      }
+
+      if((errorFlag & MDMA_CESR_ASE) != 0U)
+      {
+        /* Update error code : Address/Size alignment error */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_ALIGNMENT;
+      }
+
+      if((errorFlag & MDMA_CESR_BSE) != 0U)
+      {
+        /* Update error code : Block Size error */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_BLOCK_SIZE;
+      }
+
+      (void) HAL_MDMA_Abort(hmdma); /* if error then abort the current transfer */
+
+      /*
+        Note that the Abort function will
+          - Clear all transfer flags
+          - Unlock
+          - Set the State
+      */
+
+      return HAL_ERROR;
+
+    }
+
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(((HAL_GetTick() - tickstart ) > Timeout) || (Timeout == 0U))
+      {
+        /* Update error code */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_TIMEOUT;
+
+        (void) HAL_MDMA_Abort(hmdma); /* if timeout then abort the current transfer */
+
+        /*
+          Note that the Abort function will
+            - Clear all transfer flags
+            - Unlock
+            - Set the State
+        */
+
+        return HAL_ERROR;
+      }
+    }
+  }
+
+  /* Clear the transfer level flag */
+  if(CompleteLevel == HAL_MDMA_BUFFER_TRANSFER)
+  {
+    __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BFTC);
+
+  }
+  else if(CompleteLevel == HAL_MDMA_BLOCK_TRANSFER)
+  {
+    __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BFTC | MDMA_FLAG_BT));
+
+  }
+  else if(CompleteLevel == HAL_MDMA_REPEAT_BLOCK_TRANSFER)
+  {
+    __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BFTC | MDMA_FLAG_BT | MDMA_FLAG_BRT));
+  }
+  else if(CompleteLevel == HAL_MDMA_FULL_TRANSFER)
+  {
+    __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BRT | MDMA_FLAG_BT | MDMA_FLAG_BFTC | MDMA_FLAG_CTC));
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hmdma);
+
+    hmdma->State = HAL_MDMA_STATE_READY;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Generate an MDMA SW request trigger to activate the request on the given Channel.
+  * @param  hmdma:       pointer to a MDMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified MDMA Stream.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_GenerateSWRequest(MDMA_HandleTypeDef *hmdma)
+{
+  uint32_t request_mode;
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Get the softawre request mode */
+  request_mode = hmdma->Instance->CTCR & MDMA_CTCR_SWRM;
+
+  if((hmdma->Instance->CCR &  MDMA_CCR_EN) == 0U)
+  {
+    /* if no Transfer on going (MDMA enable bit not set) retrun error */
+    hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER;
+
+    return HAL_ERROR;
+  }
+  else if(((hmdma->Instance->CISR &  MDMA_CISR_CRQA) != 0U) || (request_mode == 0U))
+  {
+    /* if an MDMA ongoing request has not yet end or if request mode is not SW request retrun error */
+    hmdma->ErrorCode = HAL_MDMA_ERROR_BUSY;
+
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Set the SW request bit to activate the request on the Channel */
+    hmdma->Instance->CCR |= MDMA_CCR_SWRQ;
+
+    return HAL_OK;
+  }
+}
+
+/**
+  * @brief  Handles MDMA interrupt request.
+  * @param  hmdma: pointer to a MDMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified MDMA Channel.
+  * @retval None
+  */
+void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma)
+{
+  __IO uint32_t count = 0;
+  uint32_t timeout = SystemCoreClock / 9600U;
+
+  uint32_t generalIntFlag, errorFlag;
+
+  /* General Interrupt Flag management ****************************************/
+  generalIntFlag =  1UL << ((((uint32_t)hmdma->Instance - (uint32_t)(MDMA_Channel0))/HAL_MDMA_CHANNEL_SIZE) & 0x1FU);
+  if((MDMA->GISR0 & generalIntFlag) == 0U)
+  {
+    return; /* the  General interrupt flag for the current channel is down , nothing to do */
+  }
+
+  /* Transfer Error Interrupt management ***************************************/
+  if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_TE) != 0U))
+  {
+    if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_TE) != 0U)
+    {
+      /* Disable the transfer error interrupt */
+      __HAL_MDMA_DISABLE_IT(hmdma, MDMA_IT_TE);
+
+      /* Get the transfer error source flag */
+      errorFlag = hmdma->Instance->CESR;
+
+      if((errorFlag & MDMA_CESR_TED) == 0U)
+      {
+        /* Update error code : Read Transfer error  */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_READ_XFER;
+      }
+      else
+      {
+        /* Update error code : Write Transfer error */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_WRITE_XFER;
+      }
+
+      if((errorFlag & MDMA_CESR_TEMD) != 0U)
+      {
+        /* Update error code : Error Mask Data */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_MASK_DATA;
+      }
+
+      if((errorFlag & MDMA_CESR_TELD) != 0U)
+      {
+        /* Update error code : Error Linked list */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_LINKED_LIST;
+      }
+
+      if((errorFlag & MDMA_CESR_ASE) != 0U)
+      {
+        /* Update error code : Address/Size alignment error */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_ALIGNMENT;
+      }
+
+      if((errorFlag & MDMA_CESR_BSE) != 0U)
+      {
+        /* Update error code : Block Size error error */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_BLOCK_SIZE;
+      }
+
+      /* Clear the transfer error flags */
+      __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_TE);
+    }
+  }
+
+  /* Buffer Transfer Complete Interrupt management ******************************/
+  if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BFTC) != 0U))
+  {
+    if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BFTC) != 0U)
+    {
+      /* Clear the buffer transfer complete flag */
+      __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BFTC);
+
+      if(hmdma->XferBufferCpltCallback != NULL)
+      {
+        /* Buffer transfer callback */
+        hmdma->XferBufferCpltCallback(hmdma);
+      }
+    }
+  }
+
+  /* Block Transfer Complete Interrupt management ******************************/
+  if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BT) != 0U))
+  {
+    if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BT) != 0U)
+    {
+      /* Clear the block transfer complete flag */
+      __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BT);
+
+      if(hmdma->XferBlockCpltCallback != NULL)
+      {
+        /* Block transfer callback */
+        hmdma->XferBlockCpltCallback(hmdma);
+      }
+    }
+  }
+
+  /* Repeated Block Transfer Complete Interrupt management ******************************/
+  if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BRT) != 0U))
+  {
+    if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BRT) != 0U)
+    {
+      /* Clear the repeat block transfer complete flag */
+      __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BRT);
+
+      if(hmdma->XferRepeatBlockCpltCallback != NULL)
+      {
+        /* Repeated Block transfer callback */
+        hmdma->XferRepeatBlockCpltCallback(hmdma);
+      }
+    }
+  }
+
+  /* Channel Transfer Complete Interrupt management ***********************************/
+  if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_CTC) != 0U))
+  {
+    if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_CTC) != 0U)
+    {
+      /* Disable all the transfer interrupts */
+      __HAL_MDMA_DISABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC | MDMA_IT_BT | MDMA_IT_BRT | MDMA_IT_BFTC));
+
+      if(HAL_MDMA_STATE_ABORT == hmdma->State)
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hmdma);
+
+        /* Change the DMA state */
+        hmdma->State = HAL_MDMA_STATE_READY;
+
+        if(hmdma->XferAbortCallback != NULL)
+        {
+          hmdma->XferAbortCallback(hmdma);
+        }
+        return;
+      }
+
+      /* Clear the Channel Transfer Complete flag */
+      __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_CTC);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hmdma);
+
+      /* Change MDMA peripheral state */
+      hmdma->State = HAL_MDMA_STATE_READY;
+
+      if(hmdma->XferCpltCallback != NULL)
+      {
+        /* Channel Transfer Complete callback */
+        hmdma->XferCpltCallback(hmdma);
+      }
+    }
+  }
+
+  /* manage error case */
+  if(hmdma->ErrorCode != HAL_MDMA_ERROR_NONE)
+  {
+    hmdma->State = HAL_MDMA_STATE_ABORT;
+
+    /* Disable the channel */
+    __HAL_MDMA_DISABLE(hmdma);
+
+    do
+    {
+      if (++count > timeout)
+      {
+        break;
+      }
+    }
+    while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hmdma);
+
+    if((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U)
+    {
+      /* Change the MDMA state to error if MDMA disable fails */
+      hmdma->State = HAL_MDMA_STATE_ERROR;
+    }
+    else
+    {
+      /* Change the MDMA state to Ready if MDMA disable success */
+      hmdma->State = HAL_MDMA_STATE_READY;
+    }
+
+
+    if (hmdma->XferErrorCallback != NULL)
+    {
+      /* Transfer error callback */
+      hmdma->XferErrorCallback(hmdma);
+    }
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup MDMA_Exported_Functions_Group4
+ *
+@verbatim
+ ===============================================================================
+                    ##### State and Errors functions #####
+ ===============================================================================
+    [..]
+    This subsection provides functions allowing to
+      (+) Check the MDMA state
+      (+) Get error code
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the MDMA state.
+  * @param  hmdma: pointer to a MDMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified MDMA Channel.
+  * @retval HAL state
+  */
+HAL_MDMA_StateTypeDef HAL_MDMA_GetState(MDMA_HandleTypeDef *hmdma)
+{
+  return hmdma->State;
+}
+
+/**
+  * @brief  Return the MDMA error code
+  * @param  hmdma : pointer to a MDMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified MDMA Channel.
+  * @retval MDMA Error Code
+  */
+uint32_t HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma)
+{
+  return hmdma->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup MDMA_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Sets the MDMA Transfer parameter.
+  * @param  hmdma:       pointer to a MDMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified MDMA Channel.
+  * @param  SrcAddress: The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  BlockDataLength : The length of a block transfer in bytes
+  * @param  BlockCount: The number of blocks to be transfered
+  * @retval HAL status
+  */
+static void MDMA_SetConfig(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
+{
+  uint32_t addressMask;
+
+  /* Configure the MDMA Channel data length */
+  MODIFY_REG(hmdma->Instance->CBNDTR ,MDMA_CBNDTR_BNDT, (BlockDataLength & MDMA_CBNDTR_BNDT));
+
+  /* Configure the MDMA block repeat count */
+  MODIFY_REG(hmdma->Instance->CBNDTR , MDMA_CBNDTR_BRC , ((BlockCount - 1U) << MDMA_CBNDTR_BRC_Pos) & MDMA_CBNDTR_BRC);
+
+  /* Clear all interrupt flags */
+  __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_CISR_BRTIF | MDMA_CISR_BTIF | MDMA_CISR_TCIF);
+
+  /* Configure MDMA Channel destination address */
+  hmdma->Instance->CDAR = DstAddress;
+
+  /* Configure MDMA Channel Source address */
+  hmdma->Instance->CSAR = SrcAddress;
+
+  addressMask = SrcAddress & 0xFF000000U;
+  if((addressMask == 0x20000000U) || (addressMask == 0x00000000U))
+  {
+    /*The AHBSbus is used as source (read operation) on channel x */
+    hmdma->Instance->CTBR |= MDMA_CTBR_SBUS;
+  }
+  else
+  {
+    /*The AXI bus is used as source (read operation) on channel x */
+    hmdma->Instance->CTBR &= (~MDMA_CTBR_SBUS);
+  }
+
+  addressMask = DstAddress & 0xFF000000U;
+  if((addressMask == 0x20000000U) || (addressMask == 0x00000000U))
+  {
+    /*The AHB bus is used as destination (write operation) on channel x */
+    hmdma->Instance->CTBR |= MDMA_CTBR_DBUS;
+  }
+  else
+  {
+    /*The AXI bus is used as destination (write operation) on channel x */
+    hmdma->Instance->CTBR &= (~MDMA_CTBR_DBUS);
+  }
+
+  /* Set the linked list register to the first node of the list */
+  hmdma->Instance->CLAR = (uint32_t)hmdma->FirstLinkedListNodeAddress;
+}
+
+/**
+  * @brief  Initializes the MDMA handle according to the specified
+  *         parameters in the MDMA_InitTypeDef
+  * @param  hmdma:       pointer to a MDMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified MDMA Channel.
+  * @retval None
+  */
+static void MDMA_Init(MDMA_HandleTypeDef *hmdma)
+{
+  uint32_t blockoffset;
+
+  /* Prepare the MDMA Channel configuration */
+  hmdma->Instance->CCR = hmdma->Init.Priority  | hmdma->Init.Endianness;
+
+  /* Write new CTCR Register value */
+  hmdma->Instance->CTCR =  hmdma->Init.SourceInc      | hmdma->Init.DestinationInc | \
+                           hmdma->Init.SourceDataSize | hmdma->Init.DestDataSize   | \
+                           hmdma->Init.DataAlignment  | hmdma->Init.SourceBurst    | \
+                           hmdma->Init.DestBurst                                   | \
+                           ((hmdma->Init.BufferTransferLength - 1U) << MDMA_CTCR_TLEN_Pos) | \
+                           hmdma->Init.TransferTriggerMode;
+
+  /* If SW request set the CTCR register to SW Request Mode */
+  if(hmdma->Init.Request == MDMA_REQUEST_SW)
+  {
+    /*
+    -If the request is done by SW : BWM could be set to 1 or 0.
+    -If the request is done by a peripheral :
+    If mask address not set (0) => BWM must be set to 0
+    If mask address set (different than 0) => BWM could be set to 1 or 0
+    */
+    hmdma->Instance->CTCR |= (MDMA_CTCR_SWRM | MDMA_CTCR_BWM);
+  }
+
+  /* Reset CBNDTR Register */
+  hmdma->Instance->CBNDTR = 0;
+
+  /* if block source address offset is negative set the Block Repeat Source address Update Mode to decrement */
+  if(hmdma->Init.SourceBlockAddressOffset < 0)
+  {
+    hmdma->Instance->CBNDTR |= MDMA_CBNDTR_BRSUM;
+    /* Write new CBRUR Register value : source repeat block offset */
+    blockoffset = (uint32_t)(- hmdma->Init.SourceBlockAddressOffset);
+    hmdma->Instance->CBRUR = (blockoffset & 0x0000FFFFU);
+  }
+  else
+  {
+    /* Write new CBRUR Register value : source repeat block offset */
+    hmdma->Instance->CBRUR = (((uint32_t)hmdma->Init.SourceBlockAddressOffset) & 0x0000FFFFU);
+  }
+
+  /* If block destination address offset is negative set the Block Repeat destination address Update Mode to decrement */
+  if(hmdma->Init.DestBlockAddressOffset < 0)
+  {
+    hmdma->Instance->CBNDTR |= MDMA_CBNDTR_BRDUM;
+    /* Write new CBRUR Register value : destination repeat block offset */
+    blockoffset = (uint32_t)(- hmdma->Init.DestBlockAddressOffset);
+    hmdma->Instance->CBRUR |= ((blockoffset & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos);
+  }
+  else
+  {
+    /*write new CBRUR Register value : destination repeat block offset */
+    hmdma->Instance->CBRUR |= ((((uint32_t)hmdma->Init.DestBlockAddressOffset) & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos);
+  }
+
+  /* if HW request set the HW request and the requet CleraMask and ClearData MaskData, */
+  if(hmdma->Init.Request != MDMA_REQUEST_SW)
+  {
+    /* Set the HW request in CTRB register  */
+    hmdma->Instance->CTBR = hmdma->Init.Request & MDMA_CTBR_TSEL;
+  }
+  else /* SW request : reset the CTBR register */
+  {
+    hmdma->Instance->CTBR = 0;
+  }
+
+  /* Write Link Address Register */
+  hmdma->Instance->CLAR =  0;
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_MDMA_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c
new file mode 100644
index 00000000..43d9052a
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c
@@ -0,0 +1,868 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_pwr.c
+  * @author  MCD Application Team
+  * @brief   PWR HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Power Controller (PWR) peripheral:
+  *           + Initialization and de-initialization functions.
+  *           + Peripheral Control functions.
+  *           + Interrupt Handling functions.
+  @verbatim
+  ==============================================================================
+                        ##### PWR peripheral overview #####
+  ==============================================================================
+  [..]
+   (#) The Power control (PWR) provides an overview of the supply architecture
+       for the different power domains and of the supply configuration
+       controller.
+       In the H7 family, the number of power domains is different between
+       device lines. This difference is due to characteristics of each device.
+
+   (#) Domain architecture overview for the different H7 lines:
+      (+) Dual core lines are STM32H745, STM32H747, STM32H755 and STM32H757.
+          These devices have 3 power domains (D1, D2 and D3).
+          The domain D1 contains a CPU (Cortex-M7), a Flash memory and some
+          peripherals. The D2 domain contains peripherals and a CPU
+          (Cortex-M4). The D3 domain contains the system control, I/O logic
+          and low-power peripherals.
+      (+) STM32H743, STM32H753, STM32H742 and STM32H750 devices have 3 power
+          domains (D1, D2 and D3).
+          The domain D1 contains a CPU (Cortex-M7), a Flash memory and some
+          peripherals. The D2 domain contains peripherals. The D3 domains
+          contains the system control, I/O logic and low-power peripherals.
+      (+) STM32H7AxxQ, STM32H7BxxQ, STM32H7Axxx and STM32H7Bxxx devices have 2
+          power domains (CD and SRD).
+          The core domain (CD) contains a CPU (Cortex-M7), a Flash
+          memory and peripherals. The SmartRun domain contains the system
+          control, I/O logic and low-power peripherals.
+
+   (#) Every entity have low power mode as decribed below :
+   (#) The CPU low power modes are :
+      (+) CPU CRUN.
+      (+) CPU CSLEEP.
+      (+) CPU CSTOP.
+   (#) The domain low power modes are :
+      (+) DRUN.
+      (+) DSTOP.
+      (+) DSTANDBY.
+   (#) The SYSTEM low power modes are :
+      (+) RUN* : The Run* mode is entered after a POR reset and a wakeup from
+                 Standby. In Run* mode, the performance is limited and the
+                 system supply configuration shall be programmed. The system
+                 enters Run mode only when the ACTVOSRDY bit in PWR control
+                 status register 1 (PWR_CSR1) is set to 1.
+      (+) RUN.
+      (+) STOP.
+      (+) STANDBY.
+
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+   (#) Power management peripheral is active by default at startup level in
+       STM32h7xx lines.
+
+   (#) Call HAL_PWR_EnableBkUpAccess() and HAL_PWR_DisableBkUpAccess() functions
+       to enable/disable access to the backup domain (RTC registers, RTC backup
+       data registers and backup SRAM).
+
+   (#) Call HAL_PWR_ConfigPVD() after setting parameters to be configured (event
+       mode and voltage threshold) in order to set up the Power Voltage Detector,
+       then use HAL_PWR_EnablePVD() and  HAL_PWR_DisablePVD() functions to start
+       and stop the PVD detection.
+       (+) PVD level could be one of the following values :
+             (++) 1V95
+             (++) 2V1
+             (++) 2V25
+             (++) 2V4
+             (++) 2V55
+             (++) 2V7
+             (++) 2V85
+             (++) External voltage level
+
+   (#) Call HAL_PWR_EnableWakeUpPin() and HAL_PWR_DisableWakeUpPin() functions
+       with the right parameter to configure the wake up pin polarity (Low or
+       High) and to enable and disable it.
+
+   (#) Call HAL_PWR_EnterSLEEPMode() function to enter the current Core in SLEEP
+       mode. Wake-up from SLEEP mode could be following to an event or an
+       interrupt according to low power mode intrinsic request called (__WFI()
+       or __WFE()).
+       Please ensure to clear all CPU pending events by calling
+       HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx
+       in SLEEP mode with __WFE() entry.
+
+   (#) Call HAL_PWR_EnterSTOPMode() function to enter the whole system to Stop 0
+       mode for single core devices. For dual core devices, this API will enter
+       the domain (containing Cortex-Mx that executing this function) in DSTOP
+       mode. According to the used parameter, user could select the regulator to
+       be kept actif in low power mode and wake-up event type.
+       Please ensure to clear all CPU pending events by calling
+       HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx
+       in CSTOP mode with __WFE() entry.
+
+   (#) Call HAL_PWR_EnterSTANDBYMode() function to enter the whole system in
+       STANDBY mode for single core devices. For dual core devices, this API
+       will enter the domain (containing Cortex-Mx that executing this function)
+       in DSTANDBY mode.
+
+   (#) Call HAL_PWR_EnableSleepOnExit() and HAL_PWR_DisableSleepOnExit() APIs to
+       enable and disable the Cortex-Mx re-entring in SLEEP mode after an
+       interruption handling is over.
+
+   (#) Call HAL_PWR_EnableSEVOnPend() and HAL_PWR_DisableSEVOnPend() functions
+       to configure the Cortex-Mx to wake-up after any pending event / interrupt
+       even if it's disabled or has insufficient priority to cause exception
+       entry.
+
+   (#) Call HAL_PWR_PVD_IRQHandler() function to handle the PWR PVD interrupt
+       request.
+
+     *** PWR HAL driver macros list ***
+     =============================================
+     [..]
+       Below the list of most used macros in PWR HAL driver.
+
+      (+) __HAL_PWR_VOLTAGESCALING_CONFIG() : Configure the main internal
+                                              regulator output voltage.
+      (+) __HAL_PWR_GET_FLAG()              : Get the PWR pending flags.
+      (+) __HAL_PWR_CLEAR_FLAG()            : Clear the PWR pending flags.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup PWR PWR
+  * @brief PWR HAL module driver
+  * @{
+  */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @addtogroup PWR_Private_Constants PWR Private Constants
+  * @{
+  */
+
+/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
+  * @{
+  */
+#if !defined (DUAL_CORE)
+#define PVD_MODE_IT              (0x00010000U)
+#define PVD_MODE_EVT             (0x00020000U)
+#endif /* !defined (DUAL_CORE) */
+
+#define PVD_RISING_EDGE          (0x00000001U)
+#define PVD_FALLING_EDGE         (0x00000002U)
+#define PVD_RISING_FALLING_EDGE  (0x00000003U)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Functions PWR Exported Functions
+  * @{
+  */
+
+/** @defgroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions
+  * @brief    Initialization and De-Initialization functions
+  *
+@verbatim
+ ===============================================================================
+              ##### Initialization and De-Initialization Functions #####
+ ===============================================================================
+    [..]
+      This section provides functions allowing to deinitialize power peripheral.
+
+    [..]
+      After system reset, the backup domain (RTC registers, RTC backup data
+      registers and backup SRAM) is protected against possible unwanted write
+      accesses.
+      The HAL_PWR_EnableBkUpAccess() function enables the access to the backup
+      domain.
+      The HAL_PWR_DisableBkUpAccess() function disables the access to the backup
+      domain.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitialize the HAL PWR peripheral registers to their default reset
+  *         values.
+  * @note   This functionality is not available in this product.
+  *         The prototype is kept just to maintain compatibility with other
+  *         products.
+  * @retval None.
+  */
+void HAL_PWR_DeInit (void)
+{
+}
+
+/**
+  * @brief  Enable access to the backup domain (RTC registers, RTC backup data
+  *         registers and backup SRAM).
+  * @note   If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
+  *         Backup Domain Access should be kept enabled.
+  * @retval None.
+  */
+void HAL_PWR_EnableBkUpAccess (void)
+{
+  /* Enable access to RTC and backup registers */
+  SET_BIT (PWR->CR1, PWR_CR1_DBP);
+}
+
+/**
+  * @brief  Disable access to the backup domain (RTC registers, RTC backup data
+  *         registers and backup SRAM).
+  * @note   If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
+  *         Backup Domain Access should be kept enabled.
+  * @retval None.
+  */
+void HAL_PWR_DisableBkUpAccess (void)
+{
+  /* Disable access to RTC and backup registers */
+  CLEAR_BIT (PWR->CR1, PWR_CR1_DBP);
+}
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control Functions
+  *  @brief   Power Control functions
+  *
+@verbatim
+ ===============================================================================
+                 ##### Peripheral Control Functions #####
+ ===============================================================================
+    [..]
+      This section provides functions allowing to control power peripheral.
+
+    *** PVD configuration ***
+    =========================
+    [..]
+      (+) The PVD is used to monitor the VDD power supply by comparing it to a
+          threshold selected by the PVD Level (PLS[7:0] bits in the PWR_CR1
+          register).
+
+      (+) A PVDO flag is available to indicate if VDD is higher or lower
+          than the PVD threshold. This event is internally connected to the EXTI
+          line 16 to generate an interrupt if enabled.
+          It is configurable through __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
+
+      (+) The PVD is stopped in STANDBY mode.
+
+    *** Wake-up pin configuration ***
+    =================================
+    [..]
+      (+) Wake-up pin is used to wake up the system from STANDBY mode.
+          The pin pull is configurable through the WKUPEPR register to be in
+          No-pull, Pull-up and Pull-down.
+          The pin polarity is configurable through the WKUPEPR register to be
+          active on rising or falling edges.
+
+      (+) There are up to six Wake-up pin in the STM32H7 devices family.
+
+    *** Low Power modes configuration ***
+    =====================================
+    [..]
+     The device present 3 principles low-power modes features:
+      (+) SLEEP mode   : Cortex-Mx is stopped and all PWR domains are remaining
+                         active (Powered and Clocked).
+
+      (+) STOP mode    : Cortex-Mx is stopped, clocks are stopped and the
+                         regulator is running. The Main regulator or the LP
+                         regulator could be selected.
+
+      (+) STANDBY mode : All PWR domains enter DSTANDBY mode and the VCORE
+                         supply regulator is powered off.
+
+   *** SLEEP mode ***
+   ==================
+    [..]
+      (+) Entry:
+        The SLEEP mode is entered by using the HAL_PWR_EnterSLEEPMode(Regulator,
+        SLEEPEntry) function.
+
+          (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction.
+          (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction.
+
+      -@@- The Regulator parameter is not used for the STM32H7 family
+              and is kept as parameter just to maintain compatibility with the
+              lower power families (STM32L).
+
+      (+) Exit:
+        Any peripheral interrupt acknowledged by the nested vectored interrupt
+        controller (NVIC) can wake up the device from SLEEP mode.
+
+   *** STOP mode ***
+   =================
+    [..]
+      In system STOP mode, all clocks in the 1.2V domain are stopped, the PLL,
+      the HSI, and the HSE RC oscillators are disabled. Internal SRAM and
+      register contents are preserved.
+      The voltage regulator can be configured either in normal or low-power mode.
+      To minimize the consumption in STOP mode, FLASH can be powered off before
+      entering the STOP mode using the HAL_PWREx_EnableFlashPowerDown() function.
+      It can be switched on again by software after exiting the STOP mode using
+      the HAL_PWREx_DisableFlashPowerDown() function.
+
+      (+) Entry:
+         The STOP mode is entered using the HAL_PWR_EnterSTOPMode(Regulator,
+         STOPEntry) function with:
+
+         (++) Regulator:
+          (+++) PWR_MAINREGULATOR_ON: Main regulator ON.
+          (+++) PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON.
+
+         (++) STOPEntry:
+          (+++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction.
+          (+++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction.
+
+      (+) Exit:
+         Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
+
+   *** STANDBY mode ***
+   ====================
+    [..]
+    (+)
+      The system STANDBY mode allows to achieve the lowest power consumption.
+      It is based on the Cortex-Mx deep SLEEP mode, with the voltage regulator
+      disabled. The system is consequently powered off. The PLL, the HSI
+      oscillator and the HSE oscillator are also switched off. SRAM and register
+      contents are lost except for the RTC registers, RTC backup registers,
+      backup SRAM and standby circuitry.
+
+    [..]
+      The voltage regulator is OFF.
+
+      (++) Entry:
+        (+++) The STANDBY mode is entered using the HAL_PWR_EnterSTANDBYMode()
+              function.
+
+      (++) Exit:
+        (+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B),
+              RTC wakeup, tamper event, time stamp event, external reset in NRST
+              pin, IWDG reset.
+
+   *** Auto-wakeup (AWU) from low-power mode ***
+   =============================================
+    [..]
+     (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an
+         RTC Wakeup event, a tamper event or a time-stamp event, without
+         depending on an external interrupt (Auto-wakeup mode).
+
+     (+) RTC auto-wakeup (AWU) from the STOP and STANDBY modes
+
+       (++) To wake up from the STOP mode with an RTC alarm event, it is
+            necessary to configure the RTC to generate the RTC alarm using the
+            HAL_RTC_SetAlarm_IT() function.
+
+       (++) To wake up from the STOP mode with an RTC Tamper or time stamp event,
+            it is necessary to configure the RTC to detect the tamper or time
+            stamp event using the HAL_RTCEx_SetTimeStamp_IT() or
+            HAL_RTCEx_SetTamper_IT() functions.
+
+       (++) To wake up from the STOP mode with an RTC WakeUp event, it is
+            necessary to configure the RTC to generate the RTC WakeUp event
+            using the HAL_RTCEx_SetWakeUpTimer_IT() function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the event mode and the voltage threshold detected by the
+  *         Programmable Voltage Detector(PVD).
+  * @param  sConfigPVD : Pointer to an PWR_PVDTypeDef structure that contains
+  *                      the configuration information for the PVD.
+  * @note   Refer to the electrical characteristics of your device datasheet for
+  *         more details about the voltage threshold corresponding to each
+  *         detection level.
+  * @note   For dual core devices, please ensure to configure the EXTI lines for
+  *         the different Cortex-Mx through PWR_Exported_Macro provided by this
+  *         driver. All combination are allowed: wake up only Cortex-M7, wake up
+  *         only Cortex-M4 or wake up Cortex-M7 and Cortex-M4.
+  * @retval None.
+  */
+void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD)
+{
+  /* Check the PVD configuration parameter */
+  if (sConfigPVD == NULL)
+  {
+    return;
+  }
+
+  /* Check the parameters */
+  assert_param (IS_PWR_PVD_LEVEL (sConfigPVD->PVDLevel));
+  assert_param (IS_PWR_PVD_MODE (sConfigPVD->Mode));
+
+  /* Set PLS[7:5] bits according to PVDLevel value */
+  MODIFY_REG (PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel);
+
+  /* Clear previous config */
+#if !defined (DUAL_CORE)
+  __HAL_PWR_PVD_EXTI_DISABLE_EVENT ();
+  __HAL_PWR_PVD_EXTI_DISABLE_IT ();
+#endif /* !defined (DUAL_CORE) */
+
+  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE ();
+  __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE ();
+
+#if !defined (DUAL_CORE)
+  /* Interrupt mode configuration */
+  if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
+  {
+    __HAL_PWR_PVD_EXTI_ENABLE_IT ();
+  }
+
+  /* Event mode configuration */
+  if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
+  {
+    __HAL_PWR_PVD_EXTI_ENABLE_EVENT ();
+  }
+#endif /* !defined (DUAL_CORE) */
+
+  /* Rising edge configuration */
+  if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
+  {
+    __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE ();
+  }
+
+  /* Falling edge configuration */
+  if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
+  {
+    __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE ();
+  }
+}
+
+/**
+  * @brief Enable the Programmable Voltage Detector (PVD).
+  * @retval None.
+  */
+void HAL_PWR_EnablePVD (void)
+{
+  /* Enable the power voltage detector */
+  SET_BIT (PWR->CR1, PWR_CR1_PVDEN);
+}
+
+/**
+  * @brief Disable the Programmable Voltage Detector (PVD).
+  * @retval None.
+  */
+void HAL_PWR_DisablePVD (void)
+{
+  /* Disable the power voltage detector */
+  CLEAR_BIT (PWR->CR1, PWR_CR1_PVDEN);
+}
+
+/**
+  * @brief  Enable the WakeUp PINx functionality.
+  * @param  WakeUpPinPolarity : Specifies which Wake-Up pin to enable.
+  *          This parameter can be one of the following legacy values, which
+  *          sets the default (rising edge):
+  *            @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3,
+  *                 PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6.
+  *          or one of the following values where the user can explicitly states
+  *          the enabled pin and the chosen polarity:
+  *            @arg PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW,
+  *                 PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW,
+  *                 PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW,
+  *                 PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW,
+  *                 PWR_WAKEUP_PIN5_HIGH, PWR_WAKEUP_PIN5_LOW,
+  *                 PWR_WAKEUP_PIN6_HIGH, PWR_WAKEUP_PIN6_LOW.
+  * @note   PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
+  * @retval None.
+  */
+void HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity)
+{
+  /* Check the parameters */
+  assert_param (IS_PWR_WAKEUP_PIN (WakeUpPinPolarity));
+
+  /*
+     Enable and Specify the Wake-Up pin polarity and the pull configuration
+     for the event detection (rising or falling edge).
+  */
+  MODIFY_REG (PWR->WKUPEPR, PWR_EWUP_MASK, WakeUpPinPolarity);
+}
+
+/**
+  * @brief  Disable the WakeUp PINx functionality.
+  * @param  WakeUpPinx : Specifies the Power Wake-Up pin to disable.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3,
+  *                 PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6,
+  *                 PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW,
+  *                 PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW,
+  *                 PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW,
+  *                 PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW,
+  *                 PWR_WAKEUP_PIN5_HIGH, PWR_WAKEUP_PIN5_LOW,
+  *                 PWR_WAKEUP_PIN6_HIGH, PWR_WAKEUP_PIN6_LOW.
+  * @retval None.
+  */
+void HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx)
+{
+  /* Check the parameters */
+  assert_param (IS_PWR_WAKEUP_PIN (WakeUpPinx));
+
+  /* Disable the wake up pin selected */
+  CLEAR_BIT (PWR->WKUPEPR, (PWR_WKUPEPR_WKUPEN & WakeUpPinx));
+}
+
+/**
+  * @brief  Enter the current core in SLEEP mode (CSLEEP).
+  * @param  Regulator : Specifies the regulator state in SLEEP mode.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_MAINREGULATOR_ON     : SLEEP mode with regulator ON.
+  *            @arg PWR_LOWPOWERREGULATOR_ON : SLEEP mode with low power
+  *                                           regulator ON.
+  * @note   This parameter is not used for the STM32H7 family and is kept as
+  *         parameter just to maintain compatibility with the lower power
+  *         families.
+  * @param  SLEEPEntry : Specifies if SLEEP mode is entered with WFI or WFE
+  *                      intrinsic instruction.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_SLEEPENTRY_WFI : enter SLEEP mode with WFI instruction.
+  *            @arg PWR_SLEEPENTRY_WFE : enter SLEEP mode with WFE instruction.
+  * @note   Ensure to clear pending events before calling this API through
+  *         HAL_PWREx_ClearPendingEvent() when the SLEEP entry is WFE.
+  * @retval None.
+  */
+void HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry)
+{
+  /* Check the parameters */
+  assert_param (IS_PWR_REGULATOR (Regulator));
+  assert_param (IS_PWR_SLEEP_ENTRY (SLEEPEntry));
+
+  /* Clear SLEEPDEEP bit of Cortex System Control Register */
+  CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+
+  /* Select SLEEP mode entry */
+  if (SLEEPEntry == PWR_SLEEPENTRY_WFI)
+  {
+    /* Request Wait For Interrupt */
+    __WFI ();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __WFE ();
+  }
+}
+
+/**
+  * @brief  Enter STOP mode.
+  * @note   For single core devices, this API will enter the system in STOP mode
+  *         with all domains in DSTOP, if RUN_D3/RUN_SRD bit in CPUCR regiter is
+  *         cleared.
+  *         For dual core devices, this API will enter the domain (containing
+  *         Cortex-Mx that executing this function) in DSTOP mode. If all
+  *         Cortex-Mx domains are in DSTOP and RUN_D3 bit in CPUCR register is
+  *         cleared, all the system will enter in STOP mode.
+  * @param  Regulator : Specifies the regulator state in STOP mode.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_MAINREGULATOR_ON     : STOP mode with regulator ON.
+  *            @arg PWR_LOWPOWERREGULATOR_ON : STOP mode with low power
+  *                                            regulator ON.
+  * @param  STOPEntry : Specifies if STOP mode in entered with WFI or WFE
+  *                     intrinsic instruction.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction.
+  *            @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction.
+  * @note   In System STOP mode, all I/O pins keep the same state as in Run mode.
+  * @note   When exiting System STOP mode by issuing an interrupt or a wakeup
+  *         event, the HSI RC oscillator is selected as default system wakeup
+  *         clock.
+  * @note   In System STOP mode, when the voltage regulator operates in low
+  *         power mode, an additional startup delay is incurred when the system
+  *         is waking up. By keeping the internal regulator ON during STOP mode,
+  *         the consumption is higher although the startup time is reduced.
+  * @retval None.
+  */
+void HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry)
+{
+  /* Check the parameters */
+  assert_param (IS_PWR_REGULATOR (Regulator));
+  assert_param (IS_PWR_STOP_ENTRY (STOPEntry));
+
+  /* Select the regulator state in STOP mode */
+  MODIFY_REG (PWR->CR1, PWR_CR1_LPDS, Regulator);
+
+  /* Configure the PWR mode for the different Domains */
+#if defined (DUAL_CORE)
+  /* Check CPU ID */
+  if (HAL_GetCurrentCPUID () == CM7_CPUID)
+  {
+    /* Keep DSTOP mode when Cortex-M7 enters DEEP-SLEEP */
+    CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
+  }
+  else
+  {
+    /* Keep DSTOP mode when Cortex-M4 enters DEEP-SLEEP */
+    CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D2 | PWR_CPUCR_PDDS_D3));
+  }
+#else /* Single core devices */
+  /* Keep DSTOP mode when Cortex-M7 enter in DEEP-SLEEP */
+  CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
+
+#if defined (PWR_CPUCR_PDDS_D2)
+  /* Keep DSTOP mode when Cortex-M7 enter in DEEP-SLEEP */
+  CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2);
+#endif /* PWR_CPUCR_PDDS_D2 */
+#endif /* defined (DUAL_CORE) */
+
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+
+  /* Ensure that all instructions are done before entering STOP mode */
+  __DSB ();
+  __ISB ();
+
+  /* Select STOP mode entry */
+  if (STOPEntry == PWR_STOPENTRY_WFI)
+  {
+    /* Request Wait For Interrupt */
+    __WFI ();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __WFE ();
+  }
+
+  /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */
+  CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+}
+
+/**
+  * @brief  Enter STANDBY mode.
+  * @note   For single core devices, this API will enter the system in STANDBY
+  *         mode with all domains in DSTANDBY, if RUN_D3/RUN_SRD bit in CPUCR
+  *         regiter is cleared.
+  *         For dual core devices, this API will enter the domain (containing
+  *         Cortex-Mx that executing this function) in DSTANDBY mode. If all
+  *         Cortex-Mx domains are in DSTANDBY and RUN_D3 bit in CPUCR register
+  *         is cleared, all the system will enter in STANDBY mode.
+  * @note   The system enters Standby mode only when all domains are in DSTANDBY.
+  * @note   When the System exit STANDBY mode by issuing an interrupt or a
+  *         wakeup event, the HSI RC oscillator is selected as system clock.
+  * @retval None.
+  */
+void HAL_PWR_EnterSTANDBYMode (void)
+{
+  /* Configure the PWR mode for the different Domains */
+#if defined (DUAL_CORE)
+  /* Check CPU ID */
+  if (HAL_GetCurrentCPUID () == CM7_CPUID)
+  {
+    /* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */
+    SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
+    SET_BIT (PWR->CPU2CR, (PWR_CPU2CR_PDDS_D1 | PWR_CPU2CR_PDDS_D3));
+  }
+  else
+  {
+    /* Enter DSTANDBY mode when Cortex-M4 enters DEEP-SLEEP */
+    SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D2 | PWR_CPUCR_PDDS_D3));
+    SET_BIT (PWR->CPU2CR, (PWR_CPU2CR_PDDS_D2 | PWR_CPU2CR_PDDS_D3));
+  }
+#else /* Single core devices */
+  /* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */
+  SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
+
+#if defined (PWR_CPUCR_PDDS_D2)
+  /* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */
+  SET_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2);
+#endif /* PWR_CPUCR_PDDS_D2 */
+#endif /* defined (DUAL_CORE) */
+
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+
+  /* Ensure that all instructions are done before entering STOP mode */
+  __DSB ();
+  __ISB ();
+
+  /* This option is used to ensure that store operations are completed */
+#if defined (__CC_ARM)
+  __force_stores();
+#endif /* defined (__CC_ARM) */
+
+  /* Request Wait For Interrupt */
+  __WFI ();
+}
+
+/**
+  * @brief  Indicate Sleep-On-Exit feature when returning from Handler mode to
+  *         Thread mode.
+  * @note   Set SLEEPONEXIT bit of SCR register. When this bit is set, the
+  *         processor re-enters SLEEP mode when an interruption handling is over.
+  *         Setting this bit is useful when the processor is expected to run
+  *         only on interruptions handling.
+  * @retval None.
+  */
+void HAL_PWR_EnableSleepOnExit (void)
+{
+  /* Set SLEEPONEXIT bit of Cortex-Mx System Control Register */
+  SET_BIT (SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
+}
+
+/**
+  * @brief  Disable Sleep-On-Exit feature when returning from Handler mode to
+  *         Thread mode.
+  * @note   Clears SLEEPONEXIT bit of SCR register. When this bit is set, the
+  *         processor re-enters SLEEP mode when an interruption handling is over.
+  * @retval None
+  */
+void HAL_PWR_DisableSleepOnExit (void)
+{
+  /* Clear SLEEPONEXIT bit of Cortex-Mx System Control Register */
+  CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
+}
+
+/**
+  * @brief  Enable CORTEX SEVONPEND feature.
+  * @note   Sets SEVONPEND bit of SCR register. When this bit is set, any
+  *         pending event / interrupt even if it's disabled or has insufficient
+  *         priority to cause exception entry wakes up the Cortex-Mx.
+  * @retval None.
+  */
+void HAL_PWR_EnableSEVOnPend (void)
+{
+  /* Set SEVONPEND bit of Cortex-Mx System Control Register */
+  SET_BIT (SCB->SCR, SCB_SCR_SEVONPEND_Msk);
+}
+
+/**
+  * @brief  Disable CORTEX SEVONPEND feature.
+  * @note   Resets SEVONPEND bit of SCR register. When this bit is reset, only
+  *         enabled pending causes exception entry wakes up the Cortex-Mx.
+  * @retval None.
+  */
+void HAL_PWR_DisableSEVOnPend (void)
+{
+  /* Clear SEVONPEND bit of Cortex System Control Register */
+  CLEAR_BIT (SCB->SCR, SCB_SCR_SEVONPEND_Msk);
+}
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Exported_Functions_Group3 Interrupt Handling Functions
+  *  @brief   Interrupt Handling functions
+  *
+@verbatim
+ ===============================================================================
+                    ##### Interrupt Handling Functions #####
+ ===============================================================================
+    [..]
+    This section provides functions allowing to handle the PVD pending
+    interrupts.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function handles the PWR PVD interrupt request.
+  * @note   This API should be called under the PVD_AVD_IRQHandler().
+  * @retval None.
+  */
+void HAL_PWR_PVD_IRQHandler (void)
+{
+#if defined (DUAL_CORE)
+  /* Check Cortex-Mx ID */
+  if (HAL_GetCurrentCPUID () == CM7_CPUID)
+  {
+    /* Check PWR EXTI D1 flag */
+    if(__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U)
+    {
+      /* Clear PWR EXTI D1 pending bit */
+      __HAL_PWR_PVD_EXTI_CLEAR_FLAG ();
+
+      /* PWR PVD interrupt user callback */
+      HAL_PWR_PVDCallback ();
+    }
+  }
+  else
+  {
+    /* Check PWR EXTI D2 flag */
+    if (__HAL_PWR_PVD_EXTID2_GET_FLAG () != 0U)
+    {
+      /* Clear PWR EXTI D2 pending bit */
+      __HAL_PWR_PVD_EXTID2_CLEAR_FLAG ();
+
+      /* PWR PVD interrupt user callback */
+      HAL_PWR_PVDCallback ();
+    }
+  }
+#else /* Single core devices */
+  /* PVD EXTI line interrupt detected */
+  if (__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U)
+  {
+    /* Clear PWR EXTI pending bit */
+    __HAL_PWR_PVD_EXTI_CLEAR_FLAG ();
+
+    /* PWR PVD interrupt user callback */
+    HAL_PWR_PVDCallback ();
+  }
+#endif /* defined (DUAL_CORE) */
+}
+
+/**
+  * @brief  PWR PVD interrupt callback.
+  * @retval None.
+  */
+__weak void HAL_PWR_PVDCallback (void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PWR_PVDCallback can be implemented in the user file
+  */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_PWR_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c
new file mode 100644
index 00000000..82288f9e
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c
@@ -0,0 +1,2100 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_pwr_ex.c
+  * @author  MCD Application Team
+  * @brief   Extended PWR HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of PWR extension peripheral:
+  *           + Peripheral Extended features functions
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+   (#) Call HAL_PWREx_ConfigSupply() function to configure the regulator supply
+       with the following different setups according to hardware (support SMPS):
+       (+) PWR_DIRECT_SMPS_SUPPLY
+       (+) PWR_SMPS_1V8_SUPPLIES_LDO
+       (+) PWR_SMPS_2V5_SUPPLIES_LDO
+       (+) PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO
+       (+) PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO
+       (+) PWR_SMPS_1V8_SUPPLIES_EXT
+       (+) PWR_SMPS_2V5_SUPPLIES_EXT
+       (+) PWR_LDO_SUPPLY
+       (+) PWR_EXTERNAL_SOURCE_SUPPLY
+
+   (#) Call HAL_PWREx_GetSupplyConfig() function to get the current supply setup.
+
+   (#) Call HAL_PWREx_ControlVoltageScaling() function to configure the main
+       internal regulator output voltage. The voltage scaling could be one of
+       the following scales :
+       (+) PWR_REGULATOR_VOLTAGE_SCALE0
+       (+) PWR_REGULATOR_VOLTAGE_SCALE1
+       (+) PWR_REGULATOR_VOLTAGE_SCALE2
+       (+) PWR_REGULATOR_VOLTAGE_SCALE3
+
+   (#) Call HAL_PWREx_GetVoltageRange() function to get the current output
+       voltage applied to the main regulator.
+
+   (#) Call HAL_PWREx_ControlStopModeVoltageScaling() function to configure the
+       main internal regulator output voltage in STOP mode. The voltage scaling
+       in STOP mode could be one of the following scales :
+       (+) PWR_REGULATOR_SVOS_SCALE3
+       (+) PWR_REGULATOR_SVOS_SCALE4
+       (+) PWR_REGULATOR_SVOS_SCALE5
+
+   (#) Call HAL_PWREx_GetStopModeVoltageRange() function to get the current
+       output voltage applied to the main regulator in STOP mode.
+
+   (#) Call HAL_PWREx_EnterSTOP2Mode() function to enter the system in STOP mode
+       with core domain in D2STOP mode. This API is used only for STM32H7Axxx
+       and STM32H7Bxxx devices.
+       Please ensure to clear all CPU pending events by calling
+       HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx
+       in DEEP-SLEEP mode with __WFE() entry.
+
+   (#) Call HAL_PWREx_EnterSTOPMode() function to enter the selected domain in
+       DSTOP mode. Call this API with all available power domains to enter the
+       system in STOP mode.
+       Please ensure to clear all CPU pending events by calling
+       HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx
+       in DEEP-SLEEP mode with __WFE() entry.
+
+   (#) Call HAL_PWREx_ClearPendingEvent() function always before entring the
+       Cortex-Mx in any low power mode (SLEEP/DEEP-SLEEP) using WFE entry.
+
+   (#) Call HAL_PWREx_EnterSTANDBYMode() function to enter the selected domain
+       in DSTANDBY mode. Call this API with all available power domains to enter
+       the system in STANDBY mode.
+
+   (#) Call HAL_PWREx_ConfigD3Domain() function to setup the D3/SRD domain state
+       (RUN/STOP) when the system enter to low power mode.
+
+   (#) Call HAL_PWREx_ClearDomainFlags() function to clear the CPU flags for the
+       selected power domain. This API is used only for dual core devices.
+
+   (#) Call HAL_PWREx_HoldCore() and HAL_PWREx_ReleaseCore() functions to hold
+       and release the selected CPU and and their domain peripherals when
+       exiting STOP mode. These APIs are used only for dual core devices.
+
+   (#) Call HAL_PWREx_EnableFlashPowerDown() and
+       HAL_PWREx_DisableFlashPowerDown() functions to enable and disable the
+       Flash Power Down in STOP mode.
+
+   (#) Call HAL_PWREx_EnableMemoryShutOff() and
+       HAL_PWREx_DisableMemoryShutOff() functions to enable and disable the
+       memory block shut-off in DStop or DStop2. These APIs are used only for
+       STM32H7Axxx and STM32H7Bxxx lines.
+
+   (#) Call HAL_PWREx_EnableWakeUpPin() and HAL_PWREx_DisableWakeUpPin()
+       functions to enable and disable the Wake-up pin functionality for
+       the selected pin.
+
+   (#) Call HAL_PWREx_GetWakeupFlag() and HAL_PWREx_ClearWakeupFlag()
+       functions to manage wake-up flag for the selected pin.
+
+   (#) Call HAL_PWREx_WAKEUP_PIN_IRQHandler() function to handle all wake-up
+       pins interrupts.
+
+   (#) Call HAL_PWREx_EnableBkUpReg() and HAL_PWREx_DisableBkUpReg() functions
+       to enable and disable the backup domain regulator.
+
+   (#) Call HAL_PWREx_EnableUSBReg(), HAL_PWREx_DisableUSBReg(),
+       HAL_PWREx_EnableUSBVoltageDetector() and
+       HAL_PWREx_DisableUSBVoltageDetector() functions to manage USB power
+       regulation functionnalities.
+
+   (#) Call HAL_PWREx_EnableBatteryCharging() and
+       HAL_PWREx_DisableBatteryCharging() functions to enable and disable the
+       battery charging feature with the selected resistor.
+
+   (#) Call HAL_PWREx_EnableAnalogBooster() and
+       HAL_PWREx_DisableAnalogBooster() functions to enable and disable the
+       AVD boost feature when the VDD supply voltage is below 2V7.
+
+   (#) Call HAL_PWREx_EnableMonitoring() and HAL_PWREx_DisableMonitoring()
+       functions to enable and disable the VBAT and Temperature monitoring.
+       When VBAT and Temperature monitoring feature is enables, use
+       HAL_PWREx_GetTemperatureLevel() and HAL_PWREx_GetVBATLevel() to get
+       respectively the Temperature level and VBAT level.
+
+   (#) Call HAL_PWREx_GetMMCVoltage() and HAL_PWREx_DisableMonitoring()
+       function to get VDDMMC voltage level. This API is used only for
+       STM32H7AxxQ, STM32H7BxxQ, STM32H7Axxx and STM32H7Bxxx lines
+
+   (#) Call HAL_PWREx_ConfigAVD() after setting parameter to be configured
+       (event mode and voltage threshold) in order to set up the Analog Voltage
+       Detector then use HAL_PWREx_EnableAVD() and  HAL_PWREx_DisableAVD()
+       functions to start and stop the AVD detection.
+       (+) AVD level could be one of the following values :
+             (++) 1V7
+             (++) 2V1
+             (++) 2V5
+             (++) 2V8
+
+   (#) Call HAL_PWREx_PVD_AVD_IRQHandler() function to handle the PWR PVD and
+       AVD interrupt request.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup PWREx PWREx
+  * @brief PWR Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @addtogroup PWREx_Private_Constants
+  * @{
+  */
+
+/** @defgroup PWREx_AVD_Mode_Mask PWR Extended AVD Mode Mask
+  * @{
+  */
+#define AVD_MODE_IT              (0x00010000U)
+#define AVD_MODE_EVT             (0x00020000U)
+#define AVD_RISING_EDGE          (0x00000001U)
+#define AVD_FALLING_EDGE         (0x00000002U)
+#define AVD_RISING_FALLING_EDGE  (0x00000003U)
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_REG_SET_TIMEOUT PWR Extended Flag Setting Time Out Value
+  * @{
+  */
+#define PWR_FLAG_SETTING_DELAY   (1000U)
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_WakeUp_Pins_Offsets PWREx Wake-Up Pins masks and offsets
+  * @{
+  */
+/* Wake-Up Pins EXTI register mask */
+#define PWR_EXTI_WAKEUP_PINS_MASK  (EXTI_IMR2_IM55 | EXTI_IMR2_IM56 |\
+                                    EXTI_IMR2_IM57 | EXTI_IMR2_IM58 |\
+                                    EXTI_IMR2_IM59 | EXTI_IMR2_IM60)
+
+/* Wake-Up Pins PWR Pin Pull shift offsets */
+#define PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET (2U)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup PWREx_Exported_Functions PWREx Exported Functions
+  * @{
+  */
+
+/** @defgroup PWREx_Exported_Functions_Group1 Power Supply Control Functions
+  * @brief    Power supply control functions
+  *
+@verbatim
+ ===============================================================================
+                  ##### Power supply control functions #####
+ ===============================================================================
+    [..]
+   (#) When the system is powered on, the POR monitors VDD supply. Once VDD is
+       above the POR threshold level, the voltage regulator is enabled in the
+       default supply configuration:
+      (+) The Voltage converter output level is set at 1V0 in accordance with
+          the VOS3 level configured in PWR (D3/SRD) domain control register
+          (PWR_D3CR/PWR_SRDCR).
+      (+) The system is kept in reset mode as long as VCORE is not ok.
+      (+) Once VCORE is ok, the system is taken out of reset and the HSI
+          oscillator is enabled.
+      (+) Once the oscillator is stable, the system is initialized: Flash memory
+          and option bytes are loaded and the CPU starts in Run* mode.
+      (+) The software shall then initialize the system including supply
+          configuration programming using the HAL_PWREx_ConfigSupply().
+      (+) Once the supply configuration has been configured, the
+          HAL_PWREx_ConfigSupply() function checks the ACTVOSRDY bit in PWR
+          control status register 1 (PWR_CSR1) to guarantee a valid voltage
+          levels:
+       (++) As long as ACTVOSRDY indicates that voltage levels are invalid, the
+            system is in limited Run* mode, write accesses to the RAMs are not
+            permitted and VOS shall not be changed.
+       (++) Once ACTVOSRDY indicates that voltage levels are valid, the system
+            is in normal Run mode, write accesses to RAMs are allowed and VOS
+            can be changed.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Configure the system Power Supply.
+  * @param  SupplySource : Specifies the Power Supply source to set after a
+  *                        system startup.
+  *         This parameter can be one of the following values :
+  *            @arg PWR_DIRECT_SMPS_SUPPLY : The SMPS supplies the Vcore Power
+  *                                          Domains. The LDO is Bypassed.
+  *            @arg PWR_SMPS_1V8_SUPPLIES_LDO : The SMPS 1.8V output supplies
+  *                                             the LDO. The Vcore Power Domains
+  *                                             are supplied from the LDO.
+  *            @arg PWR_SMPS_2V5_SUPPLIES_LDO : The SMPS 2.5V output supplies
+  *                                             the LDO. The Vcore Power Domains
+  *                                             are supplied from the LDO.
+  *            @arg PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO : The SMPS 1.8V output
+  *                                                     supplies external
+  *                                                     circuits and the LDO.
+  *                                                     The Vcore Power Domains
+  *                                                     are supplied from the
+  *                                                     LDO.
+  *            @arg PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO : The SMPS 2.5V output
+  *                                                     supplies external
+  *                                                     circuits and the LDO.
+  *                                                     The Vcore Power Domains
+  *                                                     are supplied from the
+  *                                                     LDO.
+  *            @arg PWR_SMPS_1V8_SUPPLIES_EXT : The SMPS 1.8V output supplies
+  *                                             external circuits. The LDO is
+  *                                             Bypassed. The Vcore Power
+  *                                             Domains are supplied from
+  *                                             external source.
+  *            @arg PWR_SMPS_2V5_SUPPLIES_EXT : The SMPS 2.5V output supplies
+  *                                             external circuits. The LDO is
+  *                                             Bypassed. The Vcore Power
+  *                                             Domains are supplied from
+  *                                             external source.
+  *            @arg PWR_LDO_SUPPLY : The LDO regulator supplies the Vcore Power
+  *                                  Domains. The SMPS regulator is Bypassed.
+  *            @arg PWR_EXTERNAL_SOURCE_SUPPLY : The SMPS and the LDO are
+  *                                              Bypassed. The Vcore Power
+  *                                              Domains are supplied from
+  *                                              external source.
+  * @note   The PWR_LDO_SUPPLY and PWR_EXTERNAL_SOURCE_SUPPLY are used by all
+  *         H7 lines.
+  *         The PWR_DIRECT_SMPS_SUPPLY, PWR_SMPS_1V8_SUPPLIES_LDO,
+  *         PWR_SMPS_2V5_SUPPLIES_LDO, PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO,
+  *         PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO, PWR_SMPS_1V8_SUPPLIES_EXT and
+  *         PWR_SMPS_2V5_SUPPLIES_EXT are used only for lines that supports SMPS
+  *         regulator.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource)
+{
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param (IS_PWR_SUPPLY (SupplySource));
+
+  /* Check if supply source was configured */
+#if defined (PWR_FLAG_SCUEN)
+  if (__HAL_PWR_GET_FLAG (PWR_FLAG_SCUEN) == 0U)
+#else
+  if ((PWR->CR3 & (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)) != (PWR_CR3_SMPSEN | PWR_CR3_LDOEN))
+#endif /* defined (PWR_FLAG_SCUEN) */
+  {
+    /* Check supply configuration */
+    if ((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource)
+    {
+      /* Supply configuration update locked, can't apply a new supply config */
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Supply configuration update locked, but new supply configuration
+         matches with old supply configuration : nothing to do
+      */
+      return HAL_OK;
+    }
+  }
+
+  /* Set the power supply configuration */
+  MODIFY_REG (PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource);
+
+  /* Get tick */
+  tickstart = HAL_GetTick ();
+
+  /* Wait till voltage level flag is set */
+  while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
+  {
+    if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+#if defined (SMPS)
+  /* When the SMPS supplies external circuits verify that SDEXTRDY flag is set */
+  if ((SupplySource == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) ||
+      (SupplySource == PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) ||
+      (SupplySource == PWR_SMPS_1V8_SUPPLIES_EXT)         ||
+      (SupplySource == PWR_SMPS_2V5_SUPPLIES_EXT))
+  {
+    /* Get the current tick number */
+    tickstart = HAL_GetTick ();
+
+    /* Wait till SMPS external supply ready flag is set */
+    while (__HAL_PWR_GET_FLAG (PWR_FLAG_SMPSEXTRDY) == 0U)
+    {
+      if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY)
+      {
+        return HAL_ERROR;
+      }
+    }
+  }
+#endif /* defined (SMPS) */
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Get the power supply configuration.
+  * @retval The supply configuration.
+  */
+uint32_t HAL_PWREx_GetSupplyConfig (void)
+{
+  return (PWR->CR3 & PWR_SUPPLY_CONFIG_MASK);
+}
+
+/**
+  * @brief Configure the main internal regulator output voltage.
+  * @note   For STM32H7x3, STM32H7x5, STM32H7x7, STM32H742 and STM32H750 lines,
+  *         configuring Voltage Scale 0 is only possible when Vcore is supplied
+  *         from LDO (Low DropOut). The SYSCFG Clock must be enabled through
+  *         __HAL_RCC_SYSCFG_CLK_ENABLE() macro before configuring Voltage
+  *         Scale 0.
+  * @param  VoltageScaling : Specifies the regulator output voltage to achieve
+  *                          a tradeoff between performance and power
+  *                          consumption.
+  *          This parameter can be one of the following values :
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE0 : Regulator voltage output
+  *                                                Scale 0 mode.
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output
+  *                                                range 1 mode.
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output
+  *                                                range 2 mode.
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output
+  *                                                range 3 mode.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling)
+{
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param (IS_PWR_REGULATOR_VOLTAGE (VoltageScaling));
+
+  /* Get the voltage scaling  */
+  if ((PWR->CSR1 & PWR_CSR1_ACTVOS) == VoltageScaling)
+  {
+    /* Old and new voltage scaling configuration match : nothing to do */
+    return HAL_OK;
+  }
+
+#if defined (PWR_SRDCR_VOS)
+  /* Set the voltage range */
+  MODIFY_REG (PWR->SRDCR, PWR_SRDCR_VOS, VoltageScaling);
+#else
+  if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE0)
+  {
+    if ((PWR->CR3 & PWR_CR3_LDOEN) == PWR_CR3_LDOEN)
+    {
+      /* Set the voltage range */
+      MODIFY_REG (PWR->D3CR, PWR_D3CR_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
+
+      /* Get tick */
+      tickstart = HAL_GetTick ();
+
+      /* Wait till voltage level flag is set */
+      while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
+      {
+        if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY)
+        {
+          return HAL_ERROR;
+        }
+      }
+
+      /* Enable the PWR overdrive */
+      SET_BIT (SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);
+    }
+    else
+    {
+      /* The voltage scale 0 is only possible when LDO regulator is enabled */
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    if ((PWR->CSR1 & PWR_CSR1_ACTVOS) == PWR_REGULATOR_VOLTAGE_SCALE1)
+    {
+      if ((SYSCFG->PWRCR & SYSCFG_PWRCR_ODEN) != 0U)
+      {
+        /* Disable the PWR overdrive */
+        CLEAR_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);
+
+        /* Get tick */
+        tickstart = HAL_GetTick ();
+
+        /* Wait till voltage level flag is set */
+        while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
+        {
+          if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY)
+          {
+            return HAL_ERROR;
+          }
+        }
+      }
+    }
+
+    /* Set the voltage range */
+    MODIFY_REG (PWR->D3CR, PWR_D3CR_VOS, VoltageScaling);
+  }
+#endif /* defined (PWR_SRDCR_VOS) */
+
+  /* Get tick */
+  tickstart = HAL_GetTick ();
+
+  /* Wait till voltage level flag is set */
+  while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > PWR_FLAG_SETTING_DELAY)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Get the main internal regulator output voltage. Reflecting the last
+  *        VOS value applied to the PMU.
+  * @retval The current applied VOS selection.
+  */
+uint32_t HAL_PWREx_GetVoltageRange (void)
+{
+  /* Get the active voltage scaling */
+  return (PWR->CSR1 & PWR_CSR1_ACTVOS);
+}
+
+/**
+  * @brief Configure the main internal regulator output voltage in STOP mode.
+  * @param  VoltageScaling : Specifies the regulator output voltage when the
+  *         system enters Stop mode to achieve a tradeoff between performance
+  *         and power consumption.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_REGULATOR_SVOS_SCALE3 : Regulator voltage output range
+  *                                             3 mode.
+  *            @arg PWR_REGULATOR_SVOS_SCALE4 : Regulator voltage output range
+  *                                             4 mode.
+  *            @arg PWR_REGULATOR_SVOS_SCALE5 : Regulator voltage output range
+  *                                             5 mode.
+  * @note   The Stop mode voltage scaling for SVOS4 and SVOS5 sets the voltage
+  *         regulator in Low-power (LP) mode to further reduce power consumption.
+  *         When preselecting SVOS3, the use of the voltage regulator low-power
+  *         mode (LP) can be selected by LPDS register bit.
+  * @note   The selected SVOS4 and SVOS5 levels add an additional startup delay
+  *         when exiting from system Stop mode.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling (uint32_t VoltageScaling)
+{
+  /* Check the parameters */
+  assert_param (IS_PWR_STOP_MODE_REGULATOR_VOLTAGE (VoltageScaling));
+
+  /* Return the stop mode voltage range */
+  MODIFY_REG (PWR->CR1, PWR_CR1_SVOS, VoltageScaling);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Get the main internal regulator output voltage in STOP mode.
+  * @retval The actual applied VOS selection.
+  */
+uint32_t HAL_PWREx_GetStopModeVoltageRange (void)
+{
+  /* Return the stop voltage scaling */
+  return (PWR->CR1 & PWR_CR1_SVOS);
+}
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_Exported_Functions_Group2 Low Power Control Functions
+  * @brief    Low power control functions
+  *
+@verbatim
+ ===============================================================================
+                     ##### Low power control functions #####
+ ===============================================================================
+
+    *** Domains Low Power modes configuration ***
+    =============================================
+    [..]
+      This section provides the extended low power mode control APIs.
+      The system presents 3 principles domains (D1, D2 and D3) that can be
+      operated in low-power modes (DSTOP or DSTANDBY mode):
+
+      (+) DSTOP mode to enters a domain to STOP mode:
+       (++) D1 domain and/or D2 domain enters DSTOP mode only when the CPU
+            subsystem is in CSTOP mode and has allocated peripheral in the
+            domain.
+            In DSTOP mode the domain bus matrix clock is stopped.
+       (++) The system enters STOP mode using one of the following scenarios:
+        (+++) D1 domain enters DSTANDBY mode (powered off) and D2, D3 domains
+              enter DSTOP mode.
+        (+++) D2 domain enters DSTANDBY mode (powered off) and D1, D3 domains
+              enter DSTOP mode.
+        (+++) D3 domain enters DSTANDBY mode (powered off) and D1, D2 domains
+              enter DSTOP mode.
+        (+++) D1 and D2 domains enter DSTANDBY mode (powered off) and D3 domain
+              enters DSTOP mode.
+        (+++) D1 and D3 domains enter DSTANDBY mode (powered off) and D2 domain
+              enters DSTOP mode.
+        (+++) D2 and D3 domains enter DSTANDBY mode (powered off) and D1 domain
+              enters DSTOP mode.
+        (+++) D1, D2 and D3 domains enter DSTOP mode.
+       (++) When the system enters STOP mode, the clocks are stopped and the
+            regulator is running in main or low power mode.
+       (++) D3 domain can be kept in Run mode regardless of the CPU status when
+            enter STOP mode by using HAL_PWREx_ConfigD3Domain(D3State) function.
+
+      (+) DSTANDBY mode to enters a domain to STANDBY mode:
+       (++) The DSTANDBY mode is entered when the PDDS_Dn bit in PWR CPU control
+            register (PWR_CPUCR) for the Dn domain selects Standby mode.
+       (++) The system enters STANDBY mode only when D1, D2 and D3 domains enter
+            DSTANDBY mode. Consequently the VCORE supply regulator is powered
+            off.
+
+   *** DSTOP mode ***
+   ==================
+    [..]
+      In DStop mode the domain bus matrix clock is stopped.
+      The Flash memory can enter low-power Stop mode when it is enabled through
+      FLPS in PWR_CR1 register. This allows a trade-off between domain DStop
+      restart time and low power consumption.
+    [..]
+      In DStop mode domain peripherals using the LSI or LSE clock and
+      peripherals having a kernel clock request are still able to operate.
+    [..]
+      Before entering DSTOP mode it is recommended to call SCB_CleanDCache
+      function in order to clean the D-Cache and guarantee the data integrity
+      for the SRAM memories.
+
+      (+) Entry:
+         The DSTOP mode is entered using the HAL_PWREx_EnterSTOPMode(Regulator,
+         STOPEntry, Domain) function with:
+         (++) Regulator:
+          (+++) PWR_MAINREGULATOR_ON     : Main regulator ON.
+          (+++) PWR_LOWPOWERREGULATOR_ON : Low Power regulator ON.
+         (++) STOPEntry:
+          (+++) PWR_STOPENTRY_WFI : enter STOP mode with WFI instruction
+          (+++) PWR_STOPENTRY_WFE : enter STOP mode with WFE instruction
+         (++) Domain:
+          (+++) PWR_D1_DOMAIN : Enters D1 domain to DSTOP mode.
+          (+++) PWR_D2_DOMAIN : Enters D2 domain to DSTOP mode.
+          (+++) PWR_D3_DOMAIN : Enters D3 domain to DSTOP mode.
+
+      (+) Exit:
+        Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
+
+   *** DSTANDBY mode ***
+   =====================
+    [..]
+      In DStandby mode:
+        (+) The domain bus matrix clock is stopped.
+        (+) The domain is powered down and the domain RAM and register contents
+            are lost.
+    [..]
+      Before entering DSTANDBY mode it is recommended to call SCB_CleanDCache
+      function in order to clean the D-Cache and guarantee the data integrity
+      for the SRAM memories.
+
+      (+) Entry:
+         The DSTANDBY mode is entered using the HAL_PWREx_EnterSTANDBYMode
+         (Domain) function with:
+       (++) Domain:
+        (+++) PWR_D1_DOMAIN : Enters D1 domain to DSTANDBY mode.
+        (+++) PWR_D2_DOMAIN : Enters D2 domain to DSTANDBY mode.
+        (+++) PWR_D3_DOMAIN : Enters D3 domain to DSTANDBY mode.
+
+      (+) Exit:
+        WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC
+        wakeup, tamper event, time stamp event, external reset in NRST pin,
+        IWDG reset.
+
+   *** Keep D3/SRD in RUN mode ***
+   ===============================
+    [..]
+      D3/SRD domain can be kept in Run mode regardless of the CPU status when
+      entering STOP mode by using HAL_PWREx_ConfigD3Domain(D3State) function
+      with :
+       (+) D3State:
+        (++) PWR_D3_DOMAIN_STOP : D3/SDR domain follows the CPU sub-system
+                                  mode.
+        (++) PWR_D3_DOMAIN_RUN : D3/SRD domain remains in Run mode regardless
+                                 of CPU subsystem mode.
+
+    *** FLASH Power Down configuration ****
+    =======================================
+    [..]
+      By setting the FLPS bit in the PWR_CR1 register using the
+      HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters
+      power down mode when the device enters STOP mode. When the Flash memory is
+      in power down mode, an additional startup delay is incurred when waking up
+      from STOP mode.
+
+    *** Wakeup Pins configuration ****
+    ===================================
+    [..]
+      Wakeup pins allow the system to exit from Standby mode. The configuration
+      of wakeup pins is done with the HAL_PWREx_EnableWakeUpPin(sPinParams)
+      function with:
+       (+) sPinParams: structure to enable and configure a wakeup pin:
+        (++) WakeUpPin: Wakeup pin to be enabled.
+        (++) PinPolarity: Wakeup pin polarity (rising or falling edge).
+        (++) PinPull: Wakeup pin pull (no pull, pull-up or pull-down).
+    [..]
+      The wakeup pins are internally connected to the EXTI lines [55-60] to
+      generate an interrupt if enabled. The EXTI lines configuration is done by
+      the HAL_EXTI_Dx_EventInputConfig() functions defined in the stm32h7xxhal.c
+      file.
+    [..]
+      When a wakeup pin event is received the HAL_PWREx_WAKEUP_PIN_IRQHandler is
+      called and the appropriate flag is set in the PWR_WKUPFR register. Then in
+      the HAL_PWREx_WAKEUP_PIN_IRQHandler function the wakeup pin flag will be
+      cleared and the appropriate user callback will be called. The user can add
+      his own code by customization of function pointer HAL_PWREx_WKUPx_Callback.
+
+@endverbatim
+  * @{
+  */
+
+#if defined (PWR_CPUCR_RETDS_CD)
+/**
+  * @brief Enter the system to STOP mode with main domain in DSTOP2.
+  * @note   In STOP mode, the domain bus matrix clock is stalled.
+  * @note   In STOP mode, memories and registers are maintained and peripherals
+  *         in CPU domain are no longer operational.
+  * @note   All clocks in the VCORE domain are stopped, the PLL, the HSI and the
+  *         HSE oscillators are disabled. Only Peripherals that have wakeup
+  *         capability can switch on the HSI to receive a frame, and switch off
+  *         the HSI after receiving the frame if it is not a wakeup frame. In
+  *         this case the HSI clock is propagated only to the peripheral
+  *         requesting it.
+  * @note   When exiting STOP mode by issuing an interrupt or a wakeup event,
+  *         the HSI RC oscillator is selected as system clock if STOPWUCK bit in
+  *         RCC_CFGR register is set.
+  * @param  Regulator : Specifies the regulator state in STOP mode.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_MAINREGULATOR_ON     : STOP mode with regulator ON.
+  *            @arg PWR_LOWPOWERREGULATOR_ON : STOP mode with low power
+  *                                            regulator ON.
+  * @param  STOPEntry : Specifies if STOP mode in entered with WFI or WFE
+  *                     intrinsic instruction.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction.
+  *            @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction.
+  * @retval None.
+  */
+void HAL_PWREx_EnterSTOP2Mode (uint32_t Regulator, uint8_t STOPEntry)
+{
+  /* Check the parameters */
+  assert_param (IS_PWR_REGULATOR (Regulator));
+  assert_param (IS_PWR_STOP_ENTRY (STOPEntry));
+
+  /* Select the regulator state in Stop mode */
+  MODIFY_REG (PWR->CR1, PWR_CR1_LPDS, Regulator);
+
+  /* Go to DStop2 mode (deep retention) when CPU domain enters Deepsleep */
+  SET_BIT (PWR->CPUCR, PWR_CPUCR_RETDS_CD);
+
+  /* Keep DSTOP mode when SmartRun domain enters Deepsleep */
+  CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_SRD);
+
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+
+  /* Ensure that all instructions are done before entering STOP mode */
+  __ISB ();
+  __DSB ();
+
+  /* Select Stop mode entry */
+  if (STOPEntry == PWR_STOPENTRY_WFI)
+  {
+    /* Request Wait For Interrupt */
+    __WFI ();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __WFE ();
+  }
+
+  /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */
+  CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+}
+#endif /* defined (PWR_CPUCR_RETDS_CD) */
+
+/**
+  * @brief Enter a Domain to DSTOP mode.
+  * @note   This API gives flexibility to manage independently each domain STOP
+  *         mode. For dual core lines, this API should be executed with the
+  *         corresponding Cortex-Mx to enter domain to DSTOP mode. When it is
+  *         executed by all available Cortex-Mx, the system enter to STOP mode.
+  *         For single core lines, calling this API with domain parameter set to
+  *         PWR_D1_DOMAIN (D1/CD), the whole system will enter in STOP mode
+  *         independently of PWR_CPUCR_PDDS_Dx bits values if RUN_D3 bit in the
+  *         CPUCR_RUN_D3 is cleared.
+  * @note   In DStop mode the domain bus matrix clock is stopped.
+  * @note   The system D3/SRD domain enter Stop mode only when the CPU subsystem
+  *         is in CStop mode, the EXTI wakeup sources are inactive and at least
+  *         one PDDS_Dn bit in PWR CPU control register (PWR_CPUCR) for
+  *         any domain request Stop.
+  * @note   Before entering DSTOP mode it is recommended to call SCB_CleanDCache
+  *         function in order to clean the D-Cache and guarantee the data
+  *         integrity for the SRAM memories.
+  * @note   In System Stop mode, the domain peripherals that use the LSI or LSE
+  *         clock, and the peripherals that have a kernel clock request to
+  *         select HSI or CSI as source, are still able to operate.
+  * @param  Regulator : Specifies the regulator state in STOP mode.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_MAINREGULATOR_ON     : STOP mode with regulator ON.
+  *            @arg PWR_LOWPOWERREGULATOR_ON : STOP mode with low power
+  *                                            regulator ON.
+  * @param  STOPEntry : Specifies if STOP mode in entered with WFI or WFE
+  *                     intrinsic instruction.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction.
+  *            @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction.
+  * @param  Domain : Specifies the Domain to enter in DSTOP mode.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_D1_DOMAIN : Enter D1/CD Domain to DSTOP mode.
+  *            @arg PWR_D2_DOMAIN : Enter D2 Domain to DSTOP mode.
+  *            @arg PWR_D3_DOMAIN : Enter D3/SRD Domain to DSTOP mode.
+  * @retval None.
+  */
+void HAL_PWREx_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain)
+{
+  /* Check the parameters */
+  assert_param (IS_PWR_REGULATOR (Regulator));
+  assert_param (IS_PWR_STOP_ENTRY (STOPEntry));
+  assert_param (IS_PWR_DOMAIN (Domain));
+
+  /* Select the regulator state in Stop mode */
+  MODIFY_REG (PWR->CR1, PWR_CR1_LPDS, Regulator);
+
+  /* Select the domain Power Down DeepSleep */
+  if (Domain == PWR_D1_DOMAIN)
+  {
+#if defined (DUAL_CORE)
+    /* Check current core */
+    if (HAL_GetCurrentCPUID () != CM7_CPUID)
+    {
+      /*
+         When the domain selected and the cortex-mx don't match, entering stop
+         mode will not be performed
+      */
+      return;
+    }
+#endif /* defined (DUAL_CORE) */
+
+    /* Keep DSTOP mode when D1/CD domain enters Deepsleep */
+    CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D1);
+
+    /* Set SLEEPDEEP bit of Cortex System Control Register */
+    SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+
+    /* Ensure that all instructions are done before entering STOP mode */
+    __DSB ();
+    __ISB ();
+
+    /* Select Stop mode entry */
+    if (STOPEntry == PWR_STOPENTRY_WFI)
+    {
+      /* Request Wait For Interrupt */
+      __WFI ();
+    }
+    else
+    {
+      /* Request Wait For Event */
+      __WFE ();
+    }
+
+    /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */
+    CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+  }
+#if defined (PWR_CPUCR_PDDS_D2)
+  else if (Domain == PWR_D2_DOMAIN)
+  {
+    /* Keep DSTOP mode when D2 domain enters Deepsleep */
+    CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2);
+
+#if defined (DUAL_CORE)
+    /* Check current core */
+    if (HAL_GetCurrentCPUID () != CM4_CPUID)
+    {
+      /*
+         When the domain selected and the cortex-mx don't match, entering stop
+         mode will not be performed
+      */
+      return;
+    }
+
+    /* Set SLEEPDEEP bit of Cortex System Control Register */
+    SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+
+    /* Ensure that all instructions are done before entering STOP mode */
+    __DSB ();
+    __ISB ();
+
+    /* Select Stop mode entry */
+    if (STOPEntry == PWR_STOPENTRY_WFI)
+    {
+      /* Request Wait For Interrupt */
+      __WFI ();
+    }
+    else
+    {
+      /* Request Wait For Event */
+      __WFE ();
+    }
+
+    /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */
+    CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+#endif /* defined (DUAL_CORE) */
+  }
+#endif /* defined (PWR_CPUCR_PDDS_D2) */
+  else
+  {
+    /* Keep DSTOP mode when D3/SRD domain enters Deepsleep */
+    CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D3);
+  }
+}
+
+/**
+  * @brief Clear pending event.
+  * @note   This API clears the pending event in order to enter a given CPU
+  *         to CSLEEP or CSTOP. It should be called just before APIs performing
+  *         enter low power mode using Wait For Event request.
+  * @retval None.
+  */
+void HAL_PWREx_ClearPendingEvent (void)
+{
+#if defined (DUAL_CORE)
+  /* Check the current Core */
+  if (HAL_GetCurrentCPUID () == CM7_CPUID)
+  {
+    __WFE ();
+  }
+  else
+  {
+    __SEV ();
+    __WFE ();
+  }
+#else
+  __WFE ();
+#endif /* defined (DUAL_CORE) */
+}
+
+/**
+  * @brief Enter a Domain to DSTANDBY mode.
+  * @note   This API gives flexibility to manage independently each domain
+  *         STANDBY mode. For dual core lines, this API should be executed with
+  *         the corresponding Cortex-Mx to enter domain to DSTANDBY mode. When
+  *         it is executed by all available Cortex-Mx, the system enter STANDBY
+  *         mode.
+  *         For single core lines, calling this API with D1/SRD the selected
+  *         domain will enter the whole system in STOP if PWR_CPUCR_PDDS_D3 = 0
+  *         and enter the whole system in STANDBY if PWR_CPUCR_PDDS_D3 = 1.
+  * @note   The DStandby mode is entered when all PDDS_Dn bits in PWR_CPUCR for
+  *         the Dn domain select Standby mode. When the system enters Standby
+  *         mode, the voltage regulator is disabled.
+  * @note   When D2 or D3 domain is in DStandby mode and the CPU sets the
+  *         domain PDDS_Dn bit to select Stop mode, the domain remains in
+  *         DStandby mode. The domain will only exit DStandby when the CPU
+  *         allocates a peripheral in the domain.
+  * @note   The system D3/SRD domain enters Standby mode only when the D1 and D2
+  *         domain are in DStandby.
+  * @note   Before entering DSTANDBY mode it is recommended to call
+  *         SCB_CleanDCache function in order to clean the D-Cache and guarantee
+  *         the data integrity for the SRAM memories.
+  * @param  Domain : Specifies the Domain to enter to STANDBY mode.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_D1_DOMAIN: Enter D1/CD Domain to DSTANDBY mode.
+  *            @arg PWR_D2_DOMAIN: Enter D2 Domain to DSTANDBY mode.
+  *            @arg PWR_D3_DOMAIN: Enter D3/SRD Domain to DSTANDBY mode.
+  * @retval None
+  */
+void HAL_PWREx_EnterSTANDBYMode (uint32_t Domain)
+{
+  /* Check the parameters */
+  assert_param (IS_PWR_DOMAIN (Domain));
+
+  /* Select the domain Power Down DeepSleep */
+  if (Domain == PWR_D1_DOMAIN)
+  {
+#if defined (DUAL_CORE)
+    /* Check current core */
+    if (HAL_GetCurrentCPUID () != CM7_CPUID)
+    {
+      /*
+         When the domain selected and the cortex-mx don't match, entering
+         standby mode will not be performed
+      */
+      return;
+    }
+#endif /* defined (DUAL_CORE) */
+
+    /* Allow DSTANDBY mode when D1/CD domain enters Deepsleep */
+    SET_BIT (PWR-> CPUCR, PWR_CPUCR_PDDS_D1);
+
+#if defined (DUAL_CORE)
+    /* Allow DSTANDBY mode when D1/CD domain enters Deepsleep */
+    SET_BIT (PWR-> CPU2CR, PWR_CPU2CR_PDDS_D1);
+#endif /*DUAL_CORE*/
+
+    /* Set SLEEPDEEP bit of Cortex System Control Register */
+    SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+
+    /* This option is used to ensure that store operations are completed */
+#if defined (__CC_ARM)
+    __force_stores ();
+#endif /* defined (__CC_ARM) */
+
+    /* Request Wait For Interrupt */
+    __WFI ();
+  }
+#if defined (PWR_CPUCR_PDDS_D2)
+  else if (Domain == PWR_D2_DOMAIN)
+  {
+    /* Allow DSTANDBY mode when D2 domain enters Deepsleep */
+    SET_BIT (PWR-> CPUCR, PWR_CPUCR_PDDS_D2);
+
+#if defined (DUAL_CORE)
+    /* Check current core */
+    if (HAL_GetCurrentCPUID () != CM4_CPUID)
+    {
+      /*
+         When the domain selected and the cortex-mx don't match, entering
+         standby mode will not be performed
+      */
+      return;
+    }
+
+    /* Allow DSTANDBY mode when D2 domain enters Deepsleep */
+    SET_BIT (PWR-> CPU2CR, PWR_CPU2CR_PDDS_D2);
+
+    /* Set SLEEPDEEP bit of Cortex System Control Register */
+    SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+
+    /* This option is used to ensure that store operations are completed */
+#if defined (__CC_ARM)
+    __force_stores ();
+#endif /* defined (__CC_ARM) */
+
+    /* Request Wait For Interrupt */
+    __WFI ();
+#endif /* defined (DUAL_CORE) */
+  }
+#endif /* defined (PWR_CPUCR_PDDS_D2) */
+  else
+  {
+    /* Allow DSTANDBY mode when D3/SRD domain enters Deepsleep */
+    SET_BIT (PWR-> CPUCR, PWR_CPUCR_PDDS_D3);
+
+#if defined (DUAL_CORE)
+    /* Allow DSTANDBY mode when D3/SRD domain enters Deepsleep */
+    SET_BIT (PWR-> CPU2CR, PWR_CPU2CR_PDDS_D3);
+#endif /* defined (DUAL_CORE) */
+  }
+}
+
+/**
+  * @brief Configure the D3/SRD Domain state when the System in low power mode.
+  * @param  D3State : Specifies the D3/SRD state.
+  *          This parameter can be one of the following values :
+  *            @arg PWR_D3_DOMAIN_STOP : D3/SRD domain will follow the most deep
+  *                                      CPU sub-system low power mode.
+  *            @arg PWR_D3_DOMAIN_RUN : D3/SRD domain will stay in RUN mode
+  *                                     regardless of the CPU sub-system low
+  *                                     power mode.
+  * @retval None
+  */
+void HAL_PWREx_ConfigD3Domain (uint32_t D3State)
+{
+  /* Check the parameter */
+  assert_param (IS_D3_STATE (D3State));
+
+  /* Keep D3/SRD in run mode */
+  MODIFY_REG (PWR->CPUCR, PWR_CPUCR_RUN_D3, D3State);
+}
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Clear HOLD2F, HOLD1F, STOPF, SBF, SBF_D1, and SBF_D2 flags for a
+  *        given domain.
+  * @param  DomainFlags : Specifies the Domain flags to be cleared.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_D1_DOMAIN_FLAGS : Clear D1 Domain flags.
+  *            @arg PWR_D2_DOMAIN_FLAGS : Clear D2 Domain flags.
+  *            @arg PWR_ALL_DOMAIN_FLAGS : Clear D1 and D2 Domain flags.
+  * @retval None.
+  */
+void HAL_PWREx_ClearDomainFlags (uint32_t DomainFlags)
+{
+  /* Check the parameter */
+  assert_param (IS_PWR_DOMAIN_FLAG (DomainFlags));
+
+  /* D1 CPU flags */
+  if (DomainFlags == PWR_D1_DOMAIN_FLAGS)
+  {
+    /* Clear D1 domain flags (HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2) */
+    SET_BIT (PWR->CPUCR, PWR_CPUCR_CSSF);
+  }
+  /* D2 CPU flags */
+  else if (DomainFlags == PWR_D2_DOMAIN_FLAGS)
+  {
+    /* Clear D2 domain flags (HOLD1F, STOPF, SBF, SBF_D1, and SBF_D2) */
+    SET_BIT (PWR->CPU2CR, PWR_CPU2CR_CSSF);
+  }
+  else
+  {
+    /* Clear D1 domain flags (HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2) */
+    SET_BIT (PWR->CPUCR, PWR_CPUCR_CSSF);
+    /* Clear D2 domain flags (HOLD1F, STOPF, SBF, SBF_D1, and SBF_D2) */
+    SET_BIT (PWR->CPU2CR, PWR_CPU2CR_CSSF);
+  }
+}
+
+/**
+  * @brief Hold the CPU and their domain peripherals when exiting STOP mode.
+  * @param  CPU : Specifies the core to be held.
+  *         This parameter can be one of the following values:
+  *             @arg PWR_CORE_CPU1: Hold CPU1 and set CPU2 as master.
+  *             @arg PWR_CORE_CPU2: Hold CPU2 and set CPU1 as master.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PWREx_HoldCore (uint32_t CPU)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param (IS_PWR_CORE (CPU));
+
+  /* Check CPU index */
+  if (CPU == PWR_CORE_CPU2)
+  {
+    /* If CPU1 is not held */
+    if ((PWR->CPU2CR & PWR_CPU2CR_HOLD1) != PWR_CPU2CR_HOLD1)
+    {
+      /* Set HOLD2 bit */
+      SET_BIT (PWR->CPUCR, PWR_CPUCR_HOLD2);
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* If CPU2 is not held */
+    if ((PWR->CPUCR & PWR_CPUCR_HOLD2) != PWR_CPUCR_HOLD2)
+    {
+      /* Set HOLD1 bit */
+      SET_BIT (PWR->CPU2CR, PWR_CPU2CR_HOLD1);
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief Release the CPU and their domain peripherals after a wake-up from
+  *        STOP mode.
+  * @param  CPU: Specifies the core to be released.
+  *         This parameter can be one of the following values:
+  *             @arg  PWR_CORE_CPU1: Release the CPU1 and their domain
+  *                   peripherals from holding.
+  *             @arg  PWR_CORE_CPU2: Release the CPU2 and their domain
+  *                   peripherals from holding.
+  * @retval None
+  */
+void HAL_PWREx_ReleaseCore (uint32_t CPU)
+{
+  /* Check the parameters */
+  assert_param (IS_PWR_CORE (CPU));
+
+  /* Check CPU index */
+  if (CPU == PWR_CORE_CPU2)
+  {
+    /* Reset HOLD2 bit */
+    CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_HOLD2);
+  }
+  else
+  {
+    /* Reset HOLD1 bit */
+    CLEAR_BIT (PWR->CPU2CR, PWR_CPU2CR_HOLD1);
+  }
+}
+#endif /* defined (DUAL_CORE) */
+
+
+/**
+  * @brief Enable the Flash Power Down in Stop mode.
+  * @note   When Flash Power Down is enabled  the Flash memory enters low-power
+  *         mode when D1/SRD domain is in DStop mode. This feature allows to
+  *         obtain the best trade-off between low-power consumption and restart
+  *         time when exiting from DStop mode.
+  * @retval None.
+  */
+void HAL_PWREx_EnableFlashPowerDown (void)
+{
+  /* Enable the Flash Power Down */
+  SET_BIT (PWR->CR1, PWR_CR1_FLPS);
+}
+
+/**
+  * @brief Disable the Flash Power Down in Stop mode.
+  * @note   When Flash Power Down is disabled  the Flash memory is kept on
+  *         normal mode when D1/SRD domain is in DStop mode. This feature allows
+  *         to obtain the best trade-off between low-power consumption and
+  *         restart time when exiting from DStop mode.
+  * @retval None.
+  */
+void HAL_PWREx_DisableFlashPowerDown (void)
+{
+  /* Disable the Flash Power Down */
+  CLEAR_BIT (PWR->CR1, PWR_CR1_FLPS);
+}
+
+#if defined (PWR_CR1_SRDRAMSO)
+/**
+  * @brief Enable memory block shut-off in DStop or DStop2 modes
+  * @note   In DStop or DStop2 mode, the content of the memory blocks is
+  *         maintained. Further power optimization can be obtained by switching
+  *         off some memory blocks. This optimization implies loss of the memory
+  *         content. The user can select which memory is discarded during STOP
+  *         mode by means of xxSO bits.
+  * @param  MemoryBlock : Specifies the memory block to shut-off during DStop or
+  *                       DStop2 mode.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_SRD_AHB_MEMORY_BLOCK : SmartRun domain AHB memory.
+  *            @arg PWR_USB_FDCAN_MEMORY_BLOCK : High-speed interfaces USB and
+  *                                              FDCAN memories.
+  *            @arg PWR_GFXMMU_JPEG_MEMORY_BLOCK : GFXMMU and JPEG memories.
+  *            @arg PWR_TCM_ECM_MEMORY_BLOCK : Instruction TCM and ETM memories.
+  *            @arg PWR_RAM1_AHB_MEMORY_BLOCK : AHB RAM1 memory.
+  *            @arg PWR_RAM2_AHB_MEMORY_BLOCK : AHB RAM2 memory.
+  *            @arg PWR_RAM1_AXI_MEMORY_BLOCK : AXI RAM1 memory.
+  *            @arg PWR_RAM2_AXI_MEMORY_BLOCK : AXI RAM2 memory.
+  *            @arg PWR_RAM3_AXI_MEMORY_BLOCK : AXI RAM3 memory.
+  * @retval None.
+  */
+void HAL_PWREx_EnableMemoryShutOff (uint32_t MemoryBlock)
+{
+  /* Check the parameter */
+  assert_param (IS_PWR_MEMORY_BLOCK (MemoryBlock));
+
+  /* Enable memory block shut-off */
+  SET_BIT (PWR->CR1, MemoryBlock);
+}
+
+/**
+  * @brief Disable memory block shut-off in DStop or DStop2 modes
+  * @param  MemoryBlock : Specifies the memory block to keep content during
+  *                       DStop or DStop2 mode.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_SRD_AHB_MEMORY_BLOCK : SmartRun domain AHB memory.
+  *            @arg PWR_USB_FDCAN_MEMORY_BLOCK : High-speed interfaces USB and
+  *                                              FDCAN memories.
+  *            @arg PWR_GFXMMU_JPEG_MEMORY_BLOCK : GFXMMU and JPEG memories.
+  *            @arg PWR_TCM_ECM_MEMORY_BLOCK : Instruction TCM and ETM memories.
+  *            @arg PWR_RAM1_AHB_MEMORY_BLOCK : AHB RAM1 memory.
+  *            @arg PWR_RAM2_AHB_MEMORY_BLOCK : AHB RAM2 memory.
+  *            @arg PWR_RAM1_AXI_MEMORY_BLOCK : AXI RAM1 memory.
+  *            @arg PWR_RAM2_AXI_MEMORY_BLOCK : AXI RAM2 memory.
+  *            @arg PWR_RAM3_AXI_MEMORY_BLOCK : AXI RAM3 memory.
+  * @retval None.
+  */
+void HAL_PWREx_DisableMemoryShutOff (uint32_t MemoryBlock)
+{
+  /* Check the parameter */
+  assert_param (IS_PWR_MEMORY_BLOCK (MemoryBlock));
+
+  /* Disable memory block shut-off */
+  CLEAR_BIT (PWR->CR1, MemoryBlock);
+}
+#endif /* defined (PWR_CR1_SRDRAMSO) */
+
+/**
+  * @brief Enable the Wake-up PINx functionality.
+  * @param  sPinParams : Pointer to a PWREx_WakeupPinTypeDef structure that
+  *                      contains the configuration information for the wake-up
+  *                      Pin.
+  * @note   For dual core devices, please ensure to configure the EXTI lines for
+  *         the different Cortex-Mx. All combination are allowed: wake up only
+  *         Cortex-M7, wake up only Cortex-M4 and wake up Cortex-M7 and
+  *         Cortex-M4.
+  * @retval None.
+  */
+void HAL_PWREx_EnableWakeUpPin (PWREx_WakeupPinTypeDef *sPinParams)
+{
+  uint32_t pinConfig;
+  uint32_t regMask;
+  const uint32_t pullMask = PWR_WKUPEPR_WKUPPUPD1;
+
+  /* Check the parameters */
+  assert_param (IS_PWR_WAKEUP_PIN (sPinParams->WakeUpPin));
+  assert_param (IS_PWR_WAKEUP_PIN_POLARITY (sPinParams->PinPolarity));
+  assert_param (IS_PWR_WAKEUP_PIN_PULL (sPinParams->PinPull));
+
+  pinConfig = sPinParams->WakeUpPin | \
+              (sPinParams->PinPolarity << ((POSITION_VAL(sPinParams->WakeUpPin) + PWR_WKUPEPR_WKUPP1_Pos) & 0x1FU)) | \
+              (sPinParams->PinPull << (((POSITION_VAL(sPinParams->WakeUpPin) * PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET) + PWR_WKUPEPR_WKUPPUPD1_Pos) & 0x1FU));
+
+  regMask   = sPinParams->WakeUpPin | \
+              (PWR_WKUPEPR_WKUPP1 << (POSITION_VAL(sPinParams->WakeUpPin) & 0x1FU)) | \
+              (pullMask << ((POSITION_VAL(sPinParams->WakeUpPin) * PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET) & 0x1FU));
+
+  /* Enable and Specify the Wake-Up pin polarity and the pull configuration
+     for the event detection (rising or falling edge) */
+  MODIFY_REG (PWR->WKUPEPR, regMask, pinConfig);
+#ifndef DUAL_CORE
+  /* Configure the Wakeup Pin EXTI Line */
+  MODIFY_REG (EXTI->IMR2, PWR_EXTI_WAKEUP_PINS_MASK, (sPinParams->WakeUpPin << EXTI_IMR2_IM55_Pos));
+#endif /* !DUAL_CORE */
+}
+
+/**
+  * @brief Disable the Wake-up PINx functionality.
+  * @param  WakeUpPin : Specifies the Wake-Up pin to be disabled.
+  *          This parameter can be one of the following values:
+  *           @arg PWR_WAKEUP_PIN1 : Disable PA0  wake-up PIN.
+  *           @arg PWR_WAKEUP_PIN2 : Disable PA2  wake-up PIN.
+  *           @arg PWR_WAKEUP_PIN3 : Disable PI8  wake-up PIN.
+  *           @arg PWR_WAKEUP_PIN4 : Disable PC13 wake-up PIN.
+  *           @arg PWR_WAKEUP_PIN5 : Disable PI11 wake-up PIN.
+  *           @arg PWR_WAKEUP_PIN6 : Disable PC1  wake-up PIN.
+  * @retval None
+  */
+void HAL_PWREx_DisableWakeUpPin (uint32_t WakeUpPin)
+{
+  /* Check the parameter */
+  assert_param (IS_PWR_WAKEUP_PIN (WakeUpPin));
+
+  /* Disable the WakeUpPin */
+  CLEAR_BIT (PWR->WKUPEPR, WakeUpPin);
+}
+
+/**
+  * @brief Get the Wake-Up Pin pending flags.
+  * @param  WakeUpFlag : Specifies the Wake-Up PIN flag to be checked.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_WAKEUP_FLAG1    : Get wakeup event received from PA0.
+  *            @arg PWR_WAKEUP_FLAG2    : Get wakeup event received from PA2.
+  *            @arg PWR_WAKEUP_FLAG3    : Get wakeup event received from PI8.
+  *            @arg PWR_WAKEUP_FLAG4    : Get wakeup event received from PC13.
+  *            @arg PWR_WAKEUP_FLAG5    : Get wakeup event received from PI11.
+  *            @arg PWR_WAKEUP_FLAG6    : Get wakeup event received from PC1.
+  *            @arg PWR_WAKEUP_FLAG_ALL : Get Wakeup event received from all
+  *                                      wake up pins.
+  * @retval The Wake-Up pin flag.
+  */
+uint32_t HAL_PWREx_GetWakeupFlag (uint32_t WakeUpFlag)
+{
+  /* Check the parameters */
+  assert_param (IS_PWR_WAKEUP_FLAG (WakeUpFlag));
+
+  /* Return the wake up pin flag */
+  return (PWR->WKUPFR & WakeUpFlag);
+}
+
+/**
+  * @brief Clear the Wake-Up pin pending flag.
+  * @param  WakeUpFlag: Specifies the Wake-Up PIN flag to clear.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_WAKEUP_FLAG1 : Clear the wakeup event received from PA0.
+  *            @arg PWR_WAKEUP_FLAG2 : Clear the wakeup event received from PA2.
+  *            @arg PWR_WAKEUP_FLAG3 : Clear the wakeup event received from PI8.
+  *            @arg PWR_WAKEUP_FLAG4 : Clear the wakeup event received from PC13.
+  *            @arg PWR_WAKEUP_FLAG5 : Clear the wakeup event received from PI11.
+  *            @arg PWR_WAKEUP_FLAG6 : Clear the wakeup event received from PC1.
+  *            @arg PWR_WAKEUP_FLAG_ALL : Clear the wakeup events received from
+  *                                      all wake up pins.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag (uint32_t WakeUpFlag)
+{
+  /* Check the parameter */
+  assert_param (IS_PWR_WAKEUP_FLAG (WakeUpFlag));
+
+  /* Clear the wake up event received from wake up pin x */
+  SET_BIT (PWR->WKUPCR, WakeUpFlag);
+
+  /* Check if the wake up event is well cleared */
+  if ((PWR->WKUPFR & WakeUpFlag) != 0U)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief This function handles the PWR WAKEUP PIN interrupt request.
+  * @note   This API should be called under the WAKEUP_PIN_IRQHandler().
+  * @retval None.
+  */
+void HAL_PWREx_WAKEUP_PIN_IRQHandler (void)
+{
+  /* Wakeup pin EXTI line interrupt detected */
+  if (READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF1) != 0U)
+  {
+    /* Clear PWR WKUPF1 flag */
+    __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP1);
+
+    /* PWR WKUP1 interrupt user callback */
+    HAL_PWREx_WKUP1_Callback ();
+  }
+  else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF2) != 0U)
+  {
+    /* Clear PWR WKUPF2 flag */
+    __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP2);
+
+    /* PWR WKUP2 interrupt user callback */
+    HAL_PWREx_WKUP2_Callback ();
+  }
+  else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF3) != 0U)
+  {
+    /* Clear PWR WKUPF3 flag */
+    __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP3);
+
+    /* PWR WKUP3 interrupt user callback */
+    HAL_PWREx_WKUP3_Callback ();
+  }
+  else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF4) != 0U)
+  {
+    /* Clear PWR WKUPF4 flag */
+    __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP4);
+
+    /* PWR WKUP4 interrupt user callback */
+    HAL_PWREx_WKUP4_Callback ();
+  }
+  else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF5) != 0U)
+  {
+    /* Clear PWR WKUPF5 flag */
+    __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP5);
+
+    /* PWR WKUP5 interrupt user callback */
+    HAL_PWREx_WKUP5_Callback ();
+  }
+  else
+  {
+    /* Clear PWR WKUPF6 flag */
+    __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP6);
+
+    /* PWR WKUP6 interrupt user callback */
+    HAL_PWREx_WKUP6_Callback ();
+  }
+}
+
+/**
+  * @brief PWR WKUP1 interrupt callback.
+  * @retval None.
+  */
+__weak void HAL_PWREx_WKUP1_Callback (void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PWREx_WKUP1Callback can be implemented in the user file
+  */
+}
+
+/**
+  * @brief PWR WKUP2 interrupt callback.
+  * @retval None.
+  */
+__weak void HAL_PWREx_WKUP2_Callback (void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PWREx_WKUP2Callback can be implemented in the user file
+  */
+}
+
+/**
+  * @brief PWR WKUP3 interrupt callback.
+  * @retval None.
+  */
+__weak void HAL_PWREx_WKUP3_Callback (void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PWREx_WKUP3Callback can be implemented in the user file
+  */
+}
+
+/**
+  * @brief PWR WKUP4 interrupt callback.
+  * @retval None.
+  */
+__weak void HAL_PWREx_WKUP4_Callback (void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PWREx_WKUP4Callback can be implemented in the user file
+  */
+}
+
+/**
+  * @brief PWR WKUP5 interrupt callback.
+  * @retval None.
+  */
+__weak void HAL_PWREx_WKUP5_Callback (void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PWREx_WKUP5Callback can be implemented in the user file
+  */
+}
+
+/**
+  * @brief PWR WKUP6 interrupt callback.
+  * @retval None.
+  */
+__weak void HAL_PWREx_WKUP6_Callback (void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PWREx_WKUP6Callback can be implemented in the user file
+  */
+}
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_Exported_Functions_Group3 Peripherals control functions
+  * @brief    Peripherals control functions
+  *
+@verbatim
+ ===============================================================================
+                 ##### Peripherals control functions #####
+ ===============================================================================
+
+    *** Main and Backup Regulators configuration ***
+    ================================================
+    [..]
+      (+) The backup domain includes 4 Kbytes of backup SRAM accessible only
+          from the CPU, and addressed in 32-bit, 16-bit or 8-bit mode. Its
+          content is retained even in Standby or VBAT mode when the low power
+          backup regulator is enabled. It can be considered as an internal
+          EEPROM when VBAT is always present. You can use the
+          HAL_PWREx_EnableBkUpReg() function to enable the low power backup
+          regulator.
+      (+) When the backup domain is supplied by VDD (analog switch connected to
+          VDD) the backup SRAM is powered from VDD which replaces the VBAT power
+          supply to save battery life.
+      (+) The backup SRAM is not mass erased by a tamper event. It is read
+          protected to prevent confidential data, such as cryptographic private
+          key, from being accessed. The backup SRAM can be erased only through
+          the Flash interface when a protection level change from level 1 to
+          level 0 is requested.
+      -@- Refer to the description of Read protection (RDP) in the Flash
+          programming manual.
+      (+) The main internal regulator can be configured to have a tradeoff
+          between performance and power consumption when the device does not
+          operate at the maximum frequency. This is done through
+          HAL_PWREx_ControlVoltageScaling(VOS) function which configure the VOS
+          bit in PWR_D3CR register.
+      (+) The main internal regulator can be configured to operate in Low Power
+          mode when the system enters STOP mode to further reduce power
+          consumption.
+          This is done through HAL_PWREx_ControlStopModeVoltageScaling(SVOS)
+          function which configure the SVOS bit in PWR_CR1 register.
+          The selected SVOS4 and SVOS5 levels add an additional startup delay
+          when exiting from system Stop mode.
+    -@- Refer to the product datasheets for more details.
+
+    *** USB Regulator configuration ***
+    ===================================
+    [..]
+      (+) The USB transceivers are supplied from a dedicated VDD33USB supply
+          that can be provided either by the integrated USB regulator, or by an
+          external USB supply.
+      (+) The USB regulator is enabled by HAL_PWREx_EnableUSBReg() function, the
+          VDD33USB is then provided from the USB regulator.
+      (+) When the USB regulator is enabled, the VDD33USB supply level detector
+          shall be enabled through  HAL_PWREx_EnableUSBVoltageDetector()
+          function.
+      (+) The USB regulator is disabled through HAL_PWREx_DisableUSBReg()
+          function and VDD33USB can be provided from an external supply. In this
+          case VDD33USB and VDD50USB shall be connected together.
+
+    *** VBAT battery charging ***
+    =============================
+    [..]
+      (+) When VDD is present, the external battery connected to VBAT can be
+          charged through an internal resistance. VBAT charging can be performed
+          either through a 5 KOhm resistor or through a 1.5 KOhm resistor.
+      (+) VBAT charging is enabled by HAL_PWREx_EnableBatteryCharging
+          (ResistorValue) function with:
+       (++) ResistorValue:
+        (+++) PWR_BATTERY_CHARGING_RESISTOR_5: 5 KOhm resistor.
+        (+++) PWR_BATTERY_CHARGING_RESISTOR_1_5: 1.5 KOhm resistor.
+      (+) VBAT charging is disabled by HAL_PWREx_DisableBatteryCharging()
+          function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Enable the Backup Regulator.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg (void)
+{
+  uint32_t tickstart;
+
+  /* Enable the Backup regulator */
+  SET_BIT (PWR->CR2, PWR_CR2_BREN);
+
+  /* Get tick */
+  tickstart = HAL_GetTick ();
+
+  /* Wait till Backup regulator ready flag is set */
+  while (__HAL_PWR_GET_FLAG (PWR_FLAG_BRR) == 0U)
+  {
+    if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Disable the Backup Regulator.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg (void)
+{
+  uint32_t tickstart;
+
+  /* Disable the Backup regulator */
+  CLEAR_BIT (PWR->CR2, PWR_CR2_BREN);
+
+  /* Get tick */
+  tickstart = HAL_GetTick ();
+
+  /* Wait till Backup regulator ready flag is reset */
+  while (__HAL_PWR_GET_FLAG (PWR_FLAG_BRR) != 0U)
+  {
+    if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Enable the USB Regulator.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_PWREx_EnableUSBReg (void)
+{
+  uint32_t tickstart;
+
+  /* Enable the USB regulator */
+  SET_BIT (PWR->CR3, PWR_CR3_USBREGEN);
+
+  /* Get tick */
+  tickstart = HAL_GetTick ();
+
+  /* Wait till the USB regulator ready flag is set */
+  while (__HAL_PWR_GET_FLAG (PWR_FLAG_USB33RDY) == 0U)
+  {
+    if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Disable the USB Regulator.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_PWREx_DisableUSBReg (void)
+{
+  uint32_t tickstart;
+
+  /* Disable the USB regulator */
+  CLEAR_BIT (PWR->CR3, PWR_CR3_USBREGEN);
+
+  /* Get tick */
+  tickstart = HAL_GetTick ();
+
+  /* Wait till the USB regulator ready flag is reset */
+  while(__HAL_PWR_GET_FLAG (PWR_FLAG_USB33RDY) != 0U)
+  {
+    if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Enable the USB voltage level detector.
+  * @retval None.
+  */
+void HAL_PWREx_EnableUSBVoltageDetector (void)
+{
+  /* Enable the USB voltage detector */
+  SET_BIT (PWR->CR3, PWR_CR3_USB33DEN);
+}
+
+/**
+  * @brief Disable the USB voltage level detector.
+  * @retval None.
+  */
+void HAL_PWREx_DisableUSBVoltageDetector (void)
+{
+  /* Disable the USB voltage detector */
+  CLEAR_BIT (PWR->CR3, PWR_CR3_USB33DEN);
+}
+
+/**
+  * @brief Enable the Battery charging.
+  * @note   When VDD is present, charge the external battery through an internal
+  *         resistor.
+  * @param  ResistorValue : Specifies the charging resistor.
+  *          This parameter can be one of the following values :
+  *            @arg PWR_BATTERY_CHARGING_RESISTOR_5 : 5 KOhm resistor.
+  *            @arg PWR_BATTERY_CHARGING_RESISTOR_1_5 : 1.5 KOhm resistor.
+  * @retval None.
+  */
+void HAL_PWREx_EnableBatteryCharging (uint32_t ResistorValue)
+{
+  /* Check the parameter */
+  assert_param (IS_PWR_BATTERY_RESISTOR_SELECT (ResistorValue));
+
+  /* Specify the charging resistor */
+  MODIFY_REG (PWR->CR3, PWR_CR3_VBRS, ResistorValue);
+
+  /* Enable the Battery charging */
+  SET_BIT (PWR->CR3, PWR_CR3_VBE);
+}
+
+/**
+  * @brief Disable the Battery charging.
+  * @retval None.
+  */
+void HAL_PWREx_DisableBatteryCharging (void)
+{
+  /* Disable the Battery charging */
+  CLEAR_BIT (PWR->CR3, PWR_CR3_VBE);
+}
+
+#if defined (PWR_CR1_BOOSTE)
+/**
+  * @brief Enable the booster to guarantee the analog switch AC performance when
+  *        the VDD supply voltage is below 2V7.
+  * @note   The VDD supply voltage can be monitored through the PVD and the PLS
+  *         field bits.
+  * @retval None.
+  */
+void HAL_PWREx_EnableAnalogBooster (void)
+{
+  /* Enable the Analog voltage */
+  SET_BIT (PWR->CR1, PWR_CR1_AVD_READY);
+
+  /* Enable VDDA booster */
+  SET_BIT (PWR->CR1, PWR_CR1_BOOSTE);
+}
+
+/**
+  * @brief Disable the analog booster.
+  * @retval None.
+  */
+void HAL_PWREx_DisableAnalogBooster (void)
+{
+  /* Disable VDDA booster */
+  CLEAR_BIT (PWR->CR1, PWR_CR1_BOOSTE);
+
+  /* Disable the Analog voltage */
+  CLEAR_BIT (PWR->CR1, PWR_CR1_AVD_READY);
+}
+#endif /* defined (PWR_CR1_BOOSTE) */
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_Exported_Functions_Group4 Power Monitoring functions
+  * @brief    Power Monitoring functions
+  *
+@verbatim
+ ===============================================================================
+                 ##### Power Monitoring functions #####
+ ===============================================================================
+
+    *** VBAT and Temperature supervision ***
+    ========================================
+    [..]
+      (+) The VBAT battery voltage supply can be monitored by comparing it with
+          two threshold levels: VBAThigh and VBATlow. VBATH flag and VBATL flags
+          in the PWR control register 2 (PWR_CR2), indicate if VBAT is higher or
+          lower than the threshold.
+      (+) The temperature can be monitored by comparing it with two threshold
+          levels, TEMPhigh and TEMPlow. TEMPH and TEMPL flags, in the PWR
+          control register 2 (PWR_CR2), indicate whether the device temperature
+          is higher or lower than the threshold.
+      (+) The VBAT and the temperature monitoring is enabled by
+          HAL_PWREx_EnableMonitoring() function and disabled by
+          HAL_PWREx_DisableMonitoring() function.
+      (+) The HAL_PWREx_GetVBATLevel() function returns the VBAT level which can
+          be : PWR_VBAT_BELOW_LOW_THRESHOLD or PWR_VBAT_ABOVE_HIGH_THRESHOLD or
+          PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD.
+      (+) The HAL_PWREx_GetTemperatureLevel() function returns the Temperature
+          level which can be :
+          PWR_TEMP_BELOW_LOW_THRESHOLD or PWR_TEMP_ABOVE_HIGH_THRESHOLD or
+          PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD.
+
+    *** AVD configuration ***
+    =========================
+    [..]
+      (+) The AVD is used to monitor the VDDA power supply by comparing it to a
+          threshold selected by the AVD Level (ALS[3:0] bits in the PWR_CR1
+          register).
+      (+) A AVDO flag is available to indicate if VDDA is higher or lower
+          than the AVD threshold. This event is internally connected to the EXTI
+          line 16 to generate an interrupt if enabled.
+          It is configurable through __HAL_PWR_AVD_EXTI_ENABLE_IT() macro.
+      (+) The AVD is stopped in System Standby mode.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Enable the VBAT and temperature monitoring.
+  * @retval HAL status.
+  */
+void HAL_PWREx_EnableMonitoring (void)
+{
+  /* Enable the VBAT and Temperature monitoring */
+  SET_BIT (PWR->CR2, PWR_CR2_MONEN);
+}
+
+/**
+  * @brief Disable the VBAT and temperature monitoring.
+  * @retval HAL status.
+  */
+void HAL_PWREx_DisableMonitoring (void)
+{
+  /* Disable the VBAT and Temperature monitoring */
+  CLEAR_BIT (PWR->CR2, PWR_CR2_MONEN);
+}
+
+/**
+  * @brief Indicate whether the junction temperature is between, above or below
+  *        the thresholds.
+  * @retval Temperature level.
+  */
+uint32_t HAL_PWREx_GetTemperatureLevel (void)
+{
+  uint32_t tempLevel, regValue;
+
+  /* Read the temperature flags */
+  regValue = READ_BIT (PWR->CR2, (PWR_CR2_TEMPH | PWR_CR2_TEMPL));
+
+  /* Check if the temperature is below the threshold */
+  if (regValue == PWR_CR2_TEMPL)
+  {
+    tempLevel = PWR_TEMP_BELOW_LOW_THRESHOLD;
+  }
+  /* Check if the temperature is above the threshold */
+  else if (regValue == PWR_CR2_TEMPH)
+  {
+    tempLevel = PWR_TEMP_ABOVE_HIGH_THRESHOLD;
+  }
+  /* The temperature is between the thresholds */
+  else
+  {
+    tempLevel = PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD;
+  }
+
+  return tempLevel;
+}
+
+/**
+  * @brief Indicate whether the Battery voltage level is between, above or below
+  *        the thresholds.
+  * @retval VBAT level.
+  */
+uint32_t HAL_PWREx_GetVBATLevel (void)
+{
+  uint32_t VBATLevel, regValue;
+
+  /* Read the VBAT flags */
+  regValue = READ_BIT (PWR->CR2, (PWR_CR2_VBATH | PWR_CR2_VBATL));
+
+  /* Check if the VBAT is below the threshold */
+  if (regValue == PWR_CR2_VBATL)
+  {
+    VBATLevel = PWR_VBAT_BELOW_LOW_THRESHOLD;
+  }
+  /* Check if the VBAT is above the threshold */
+  else if (regValue == PWR_CR2_VBATH)
+  {
+    VBATLevel = PWR_VBAT_ABOVE_HIGH_THRESHOLD;
+  }
+  /* The VBAT is between the thresholds */
+  else
+  {
+    VBATLevel = PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD;
+  }
+
+  return VBATLevel;
+}
+
+#if defined (PWR_CSR1_MMCVDO)
+/**
+  * @brief Get the VDDMMC voltage level.
+  * @retval The VDDMMC voltage level.
+  */
+PWREx_MMC_VoltageLevel HAL_PWREx_GetMMCVoltage (void)
+{
+  PWREx_MMC_VoltageLevel mmc_voltage;
+
+  /* Check voltage detector output on VDDMMC value */
+  if ((PWR->CSR1 & PWR_CSR1_MMCVDO_Msk) == 0U)
+  {
+    mmc_voltage = PWR_MMC_VOLTAGE_BELOW_1V2;
+  }
+  else
+  {
+    mmc_voltage = PWR_MMC_VOLTAGE_EQUAL_ABOVE_1V2;
+  }
+
+  return mmc_voltage;
+}
+#endif /* defined (PWR_CSR1_MMCVDO) */
+
+/**
+  * @brief  Configure the event mode and the voltage threshold detected by the
+  *         Analog Voltage Detector (AVD).
+  * @param  sConfigAVD : Pointer to an PWREx_AVDTypeDef structure that contains
+  *                      the configuration information for the AVD.
+  * @note   Refer to the electrical characteristics of your device datasheet for
+  *         more details about the voltage threshold corresponding to each
+  *         detection level.
+  * @note   For dual core devices, please ensure to configure the EXTI lines for
+  *         the different Cortex-Mx through PWR_Exported_Macro provided by this
+  *         driver. All combination are allowed: wake up only Cortex-M7, wake up
+  *         only Cortex-M4 and wake up Cortex-M7 and Cortex-M4.
+  * @retval None.
+  */
+void HAL_PWREx_ConfigAVD (PWREx_AVDTypeDef *sConfigAVD)
+{
+  /* Check the parameters */
+  assert_param (IS_PWR_AVD_LEVEL (sConfigAVD->AVDLevel));
+  assert_param (IS_PWR_AVD_MODE (sConfigAVD->Mode));
+
+  /* Set the ALS[18:17] bits according to AVDLevel value */
+  MODIFY_REG (PWR->CR1, PWR_CR1_ALS, sConfigAVD->AVDLevel);
+
+  /* Clear any previous config */
+#if !defined (DUAL_CORE)
+  __HAL_PWR_AVD_EXTI_DISABLE_EVENT ();
+  __HAL_PWR_AVD_EXTI_DISABLE_IT ();
+#endif /* !defined (DUAL_CORE) */
+
+  __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE ();
+  __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE ();
+
+#if !defined (DUAL_CORE)
+  /* Configure the interrupt mode */
+  if ((sConfigAVD->Mode & AVD_MODE_IT) == AVD_MODE_IT)
+  {
+    __HAL_PWR_AVD_EXTI_ENABLE_IT ();
+  }
+
+  /* Configure the event mode */
+  if ((sConfigAVD->Mode & AVD_MODE_EVT) == AVD_MODE_EVT)
+  {
+    __HAL_PWR_AVD_EXTI_ENABLE_EVENT ();
+  }
+#endif /* !defined (DUAL_CORE) */
+
+  /* Rising edge configuration */
+  if ((sConfigAVD->Mode & AVD_RISING_EDGE) == AVD_RISING_EDGE)
+  {
+    __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE ();
+  }
+
+  /* Falling edge configuration */
+  if ((sConfigAVD->Mode & AVD_FALLING_EDGE) == AVD_FALLING_EDGE)
+  {
+    __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE ();
+  }
+}
+
+/**
+  * @brief Enable the Analog Voltage Detector (AVD).
+  * @retval None.
+  */
+void HAL_PWREx_EnableAVD (void)
+{
+  /* Enable the Analog Voltage Detector */
+  SET_BIT (PWR->CR1, PWR_CR1_AVDEN);
+}
+
+/**
+  * @brief Disable the Analog Voltage Detector(AVD).
+  * @retval None.
+  */
+void HAL_PWREx_DisableAVD (void)
+{
+  /* Disable the Analog Voltage Detector */
+  CLEAR_BIT (PWR->CR1, PWR_CR1_AVDEN);
+}
+
+/**
+  * @brief  This function handles the PWR PVD/AVD interrupt request.
+  * @note   This API should be called under the PVD_AVD_IRQHandler().
+  * @retval None
+  */
+void HAL_PWREx_PVD_AVD_IRQHandler (void)
+{
+  /* Check if the Programmable Voltage Detector is enabled (PVD) */
+  if(READ_BIT (PWR->CR1, PWR_CR1_PVDEN) != 0U)
+  {
+#if defined (DUAL_CORE)
+    if (HAL_GetCurrentCPUID () == CM7_CPUID)
+#endif /* defined (DUAL_CORE) */
+    {
+      /* Check PWR D1/CD EXTI flag */
+      if(__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U)
+      {
+        /* PWR PVD interrupt user callback */
+        HAL_PWR_PVDCallback ();
+
+        /* Clear PWR EXTI D1/CD pending bit */
+        __HAL_PWR_PVD_EXTI_CLEAR_FLAG ();
+      }
+    }
+#if defined (DUAL_CORE)
+    else
+    {
+      /* Check PWR EXTI D2 flag */
+      if (__HAL_PWR_PVD_EXTID2_GET_FLAG () != 0U)
+      {
+        /* PWR PVD interrupt user callback */
+        HAL_PWR_PVDCallback ();
+
+        /* Clear PWR EXTI D2 pending bit */
+        __HAL_PWR_PVD_EXTID2_CLEAR_FLAG();
+      }
+    }
+#endif /* defined (DUAL_CORE) */
+  }
+
+  /* Check if the Analog Voltage Detector is enabled (AVD) */
+  if (READ_BIT (PWR->CR1, PWR_CR1_AVDEN) != 0U)
+  {
+#if defined (DUAL_CORE)
+    if (HAL_GetCurrentCPUID () == CM7_CPUID)
+#endif /* defined (DUAL_CORE) */
+    {
+      /* Check PWR EXTI D1/CD flag */
+      if (__HAL_PWR_AVD_EXTI_GET_FLAG () != 0U)
+      {
+        /* PWR AVD interrupt user callback */
+        HAL_PWREx_AVDCallback ();
+
+        /* Clear PWR EXTI D1/CD pending bit */
+        __HAL_PWR_AVD_EXTI_CLEAR_FLAG ();
+      }
+    }
+#if defined (DUAL_CORE)
+    else
+    {
+      /* Check PWR EXTI D2 flag */
+      if (__HAL_PWR_AVD_EXTID2_GET_FLAG () != 0U)
+      {
+        /* PWR AVD interrupt user callback */
+        HAL_PWREx_AVDCallback ();
+
+        /* Clear PWR EXTI D2 pending bit */
+        __HAL_PWR_AVD_EXTID2_CLEAR_FLAG ();
+      }
+    }
+#endif /* defined (DUAL_CORE) */
+  }
+}
+
+/**
+  * @brief PWR AVD interrupt callback.
+  * @retval None.
+  */
+__weak void HAL_PWREx_AVDCallback (void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PWR_AVDCallback can be implemented in the user file
+  */
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c
new file mode 100644
index 00000000..7d73fa57
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c
@@ -0,0 +1,1775 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_rcc.c
+  * @author  MCD Application Team
+  * @brief   RCC HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Reset and Clock Control (RCC) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions
+  *
+  @verbatim
+  ==============================================================================
+                      ##### RCC specific features #####
+  ==============================================================================
+    [..]
+      After reset the device is running from Internal High Speed oscillator
+      (HSI 64MHz) with Flash 0 wait state,and all peripherals are off except
+      internal SRAM, Flash, JTAG and PWR
+      (+) There is no pre-scaler on High speed (AHB) and Low speed (APB) buses;
+          all peripherals mapped on these buses are running at HSI speed.
+      (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
+      (+) All GPIOs are in analogue mode , except the JTAG pins which
+          are assigned to be used for debug purpose.
+
+    [..]
+      Once the device started from reset, the user application has to:
+      (+) Configure the clock source to be used to drive the System clock
+          (if the application needs higher frequency/performance)
+      (+) Configure the System clock frequency and Flash settings
+      (+) Configure the AHB and APB buses pre-scalers
+      (+) Enable the clock for the peripheral(s) to be used
+      (+) Configure the clock kernel source(s) for peripherals which clocks are not
+          derived from the System clock through :RCC_D1CCIPR,RCC_D2CCIP1R,RCC_D2CCIP2R
+          and RCC_D3CCIPR registers
+
+                      ##### RCC Limitations #####
+  ==============================================================================
+    [..]
+      A delay between an RCC peripheral clock enable and the effective peripheral
+      enabling should be taken into account in order to manage the peripheral read/write
+      from/to registers.
+      (+) This delay depends on the peripheral mapping.
+      (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
+          after the clock enable bit is set on the hardware register
+      (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
+          after the clock enable bit is set on the hardware register
+
+    [..]
+      Implemented Workaround:
+      (+) For AHB & APB peripherals, a dummy read to the peripheral register has been
+          inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
+
+  @endverbatim
+ ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup RCC  RCC
+  * @brief RCC HAL module driver
+  * @{
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup RCC_Private_Macros RCC Private Macros
+  * @{
+  */
+#define MCO1_CLK_ENABLE()     __HAL_RCC_GPIOA_CLK_ENABLE()
+#define MCO1_GPIO_PORT        GPIOA
+#define MCO1_PIN              GPIO_PIN_8
+
+#define MCO2_CLK_ENABLE()      __HAL_RCC_GPIOC_CLK_ENABLE()
+#define MCO2_GPIO_PORT         GPIOC
+#define MCO2_PIN               GPIO_PIN_9
+
+/**
+  * @}
+  */
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup RCC_Private_Variables RCC Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Functions RCC Exported Functions
+  * @{
+  */
+
+/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+           ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]
+      This section provides functions allowing to configure the internal/external oscillators
+      (HSE, HSI, LSE,CSI, LSI,HSI48, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB3, AHB1
+       AHB2,AHB4,APB3, APB1L, APB1H, APB2, and APB4).
+
+    [..] Internal/external clock and PLL configuration
+         (#) HSI (high-speed internal), 64 MHz factory-trimmed RC used directly or through
+             the PLL as System clock source.
+         (#) CSI is a low-power RC oscillator which can be used directly as system clock, peripheral
+             clock, or PLL input.But even with frequency calibration, is less accurate than an
+             external crystal oscillator or ceramic resonator.
+         (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
+             clock source.
+
+         (#) HSE (high-speed external), 4 to 48 MHz crystal oscillator used directly or
+             through the PLL as System clock source. Can be used also as RTC clock source.
+
+         (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
+
+         (#) PLL , The RCC features three independent PLLs (clocked by HSI , HSE or CSI),
+             featuring three different output clocks and able  to work either in integer or Fractional mode.
+           (++) A main PLL, PLL1, which is generally used to provide clocks to the CPU
+                and to some peripherals.
+           (++) Two dedicated PLLs, PLL2 and PLL3, which are used to generate the kernel clock for peripherals.
+
+
+         (#) CSS (Clock security system), once enabled and if a HSE clock failure occurs
+            (HSE used directly or through PLL as System clock source), the System clock
+             is automatically switched to HSI and an interrupt is generated if enabled.
+             The interrupt is linked to the Cortex-M NMI (Non-Mask-able Interrupt)
+             exception vector.
+
+         (#) MCO1 (micro controller clock output), used to output HSI, LSE, HSE, PLL1(PLL1_Q)
+             or HSI48 clock (through a configurable pre-scaler) on PA8 pin.
+
+         (#) MCO2 (micro controller clock output), used to output HSE, PLL2(PLL2_P), SYSCLK,
+             LSI, CSI, or PLL1(PLL1_P) clock (through a configurable pre-scaler) on PC9 pin.
+
+    [..] System, AHB and APB buses clocks configuration
+         (#) Several clock sources can be used to drive the System clock (SYSCLK): CSI,HSI,
+             HSE and PLL.
+             The AHB clock (HCLK) is derived from System core clock through configurable
+             pre-scaler and used to clock the CPU, memory and peripherals mapped
+             on AHB and APB bus of the 3 Domains (D1, D2, D3)* through configurable pre-scalers
+             and used to clock the peripherals mapped on these buses. You can use
+             "HAL_RCC_GetSysClockFreq()" function to retrieve system clock frequency.
+
+         -@- All the peripheral clocks are derived from the System clock (SYSCLK) except those
+             with dual clock domain where kernel source clock could be selected through
+             RCC_D1CCIPR,RCC_D2CCIP1R,RCC_D2CCIP2R and RCC_D3CCIPR registers.
+
+     (*) : 2 Domains (CD and SRD) for stm32h7a3xx and stm32h7b3xx family lines.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Resets the RCC clock configuration to the default reset state.
+  * @note   The default reset state of the clock configuration is given below:
+  *            - HSI ON and used as system clock source
+  *            - HSE, PLL1, PLL2 and PLL3 OFF
+  *            - AHB, APB Bus pre-scaler set to 1.
+  *            - CSS, MCO1 and MCO2 OFF
+  *            - All interrupts disabled
+  * @note   This function doesn't modify the configuration of the
+  *            - Peripheral clocks
+  *            - LSI, LSE and RTC clocks
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCC_DeInit(void)
+{
+  uint32_t tickstart;
+
+        /* Increasing the CPU frequency */
+  if(FLASH_LATENCY_DEFAULT  > __HAL_FLASH_GET_LATENCY())
+  {
+    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+    __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT);
+
+    /* Check that the new number of wait states is taken into account to access the Flash
+    memory by reading the FLASH_ACR register */
+    if(__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT)
+    {
+      return HAL_ERROR;
+    }
+
+  }
+
+
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Set HSION bit */
+  SET_BIT(RCC->CR, RCC_CR_HSION);
+
+  /* Wait till HSI is ready */
+  while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Set HSITRIM[6:0] bits to the reset value */
+  SET_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM_6);
+
+  /* Reset CFGR register */
+  CLEAR_REG(RCC->CFGR);
+
+  /* Update the SystemCoreClock and SystemD2Clock global variables */
+  SystemCoreClock = HSI_VALUE;
+  SystemD2Clock = HSI_VALUE;
+
+  /* Adapt Systick interrupt period */
+  if(HAL_InitTick(uwTickPrio) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait till clock switch is ready */
+  while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Reset CSION, CSIKERON, HSEON, HSI48ON, HSECSSON, HSIDIV bits */
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSIKERON| RCC_CR_HSIDIV| RCC_CR_HSIDIVF| RCC_CR_CSION | RCC_CR_CSIKERON  \
+  | RCC_CR_HSI48ON | RCC_CR_CSSHSEON);
+
+  /* Wait till HSE is disabled */
+  while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Clear PLLON bit */
+  CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON);
+
+  /* Wait till PLL is disabled */
+  while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) != 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Reset PLL2ON bit */
+  CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
+
+  /* Wait till PLL2 is disabled */
+  while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Reset PLL3 bit */
+  CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
+
+  /* Wait till PLL3 is disabled */
+  while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+#if defined(RCC_D1CFGR_HPRE)
+  /* Reset D1CFGR register */
+  CLEAR_REG(RCC->D1CFGR);
+
+  /* Reset D2CFGR register */
+  CLEAR_REG(RCC->D2CFGR);
+
+  /* Reset D3CFGR register */
+  CLEAR_REG(RCC->D3CFGR);
+#else
+  /* Reset CDCFGR1 register */
+  CLEAR_REG(RCC->CDCFGR1);
+
+  /* Reset CDCFGR2 register */
+  CLEAR_REG(RCC->CDCFGR2);
+
+  /* Reset SRDCFGR register */
+  CLEAR_REG(RCC->SRDCFGR);
+#endif
+
+  /* Reset PLLCKSELR register to default value */
+  RCC->PLLCKSELR= RCC_PLLCKSELR_DIVM1_5|RCC_PLLCKSELR_DIVM2_5|RCC_PLLCKSELR_DIVM3_5;
+
+  /* Reset PLLCFGR register to default value */
+  WRITE_REG(RCC->PLLCFGR, 0x01FF0000U);
+
+  /* Reset PLL1DIVR register to default value */
+  WRITE_REG(RCC->PLL1DIVR,0x01010280U);
+
+  /* Reset PLL1FRACR register */
+  CLEAR_REG(RCC->PLL1FRACR);
+
+  /* Reset PLL2DIVR register to default value */
+  WRITE_REG(RCC->PLL2DIVR,0x01010280U);
+
+  /* Reset PLL2FRACR register */
+  CLEAR_REG(RCC->PLL2FRACR);
+
+  /* Reset PLL3DIVR register to default value */
+  WRITE_REG(RCC->PLL3DIVR,0x01010280U);
+
+  /* Reset PLL3FRACR register */
+  CLEAR_REG(RCC->PLL3FRACR);
+
+  /* Reset HSEBYP bit */
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
+
+  /* Disable all interrupts */
+  CLEAR_REG(RCC->CIER);
+
+  /* Clear all interrupts flags */
+  WRITE_REG(RCC->CICR,0xFFFFFFFFU);
+
+  /* Reset all RSR flags */
+  SET_BIT(RCC->RSR, RCC_RSR_RMVF);
+
+      /* Decreasing the number of wait states because of lower CPU frequency */
+  if(FLASH_LATENCY_DEFAULT  < __HAL_FLASH_GET_LATENCY())
+  {
+    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+    __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT);
+
+    /* Check that the new number of wait states is taken into account to access the Flash
+    memory by reading the FLASH_ACR register */
+    if(__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT)
+    {
+      return HAL_ERROR;
+    }
+
+}
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the RCC Oscillators according to the specified parameters in the
+  *         RCC_OscInitTypeDef.
+  * @param  RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
+  *         contains the configuration information for the RCC Oscillators.
+  * @note   The PLL is not disabled when used as system clock.
+  * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
+  *         supported by this function. User should request a transition to LSE Off
+  *         first and then LSE On or LSE Bypass.
+  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
+  *         supported by this function. User should request a transition to HSE Off
+  *         first and then HSE On or HSE Bypass.
+  * @retval HAL status
+  */
+__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
+{
+  uint32_t tickstart;
+  uint32_t temp1_pllckcfg, temp2_pllckcfg;
+
+    /* Check Null pointer */
+  if(RCC_OscInitStruct == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
+  /*------------------------------- HSE Configuration ------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
+
+    const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
+    const uint32_t temp_pllckselr = RCC->PLLCKSELR;
+    /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
+    if((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE)))
+    {
+      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
+      {
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Set the new HSE configuration ---------------------------------------*/
+      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
+
+      /* Check the HSE State */
+      if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
+      {
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSE is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
+        {
+          if((uint32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+      else
+      {
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSE is disabled */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
+        {
+          if((uint32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+  }
+  /*----------------------------- HSI Configuration --------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
+    assert_param(IS_RCC_HSICALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
+
+    /* When the HSI is used as system clock it will not be disabled */
+    const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
+    const uint32_t temp_pllckselr = RCC->PLLCKSELR;
+    if((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI)))
+    {
+      /* When HSI is used as system clock it will not be disabled */
+      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
+      {
+        return HAL_ERROR;
+      }
+      /* Otherwise, just the calibration is allowed */
+      else
+      {
+        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+      }
+    }
+
+    else
+    {
+      /* Check the HSI State */
+      if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
+      {
+     /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */
+        __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSI is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
+        {
+          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+
+        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+      }
+      else
+      {
+        /* Disable the Internal High Speed oscillator (HSI). */
+        __HAL_RCC_HSI_DISABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSI is disabled */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
+        {
+          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+  }
+  /*----------------------------- CSI Configuration --------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState));
+    assert_param(IS_RCC_CSICALIBRATION_VALUE(RCC_OscInitStruct->CSICalibrationValue));
+
+    /* When the CSI is used as system clock it will not disabled */
+    const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
+    const uint32_t temp_pllckselr = RCC->PLLCKSELR;
+    if((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI)))
+    {
+      /* When CSI is used as system clock it will not disabled */
+      if((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON))
+      {
+        return HAL_ERROR;
+      }
+      /* Otherwise, just the calibration is allowed */
+      else
+      {
+        /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/
+        __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
+      }
+    }
+    else
+    {
+      /* Check the CSI State */
+      if((RCC_OscInitStruct->CSIState)!= RCC_CSI_OFF)
+      {
+        /* Enable the Internal High Speed oscillator (CSI). */
+        __HAL_RCC_CSI_ENABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till CSI is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)
+        {
+          if((HAL_GetTick() - tickstart ) > CSI_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+
+        /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/
+        __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
+      }
+      else
+      {
+        /* Disable the Internal High Speed oscillator (CSI). */
+        __HAL_RCC_CSI_DISABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till CSI is disabled */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U)
+        {
+          if((HAL_GetTick() - tickstart ) > CSI_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+  }
+  /*------------------------------ LSI Configuration -------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
+
+    /* Check the LSI State */
+    if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
+    {
+      /* Enable the Internal Low Speed oscillator (LSI). */
+      __HAL_RCC_LSI_ENABLE();
+
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSI is ready */
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
+      {
+        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    else
+    {
+      /* Disable the Internal Low Speed oscillator (LSI). */
+      __HAL_RCC_LSI_DISABLE();
+
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSI is ready */
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
+      {
+        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /*------------------------------ HSI48 Configuration -------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
+
+    /* Check the HSI48 State */
+    if((RCC_OscInitStruct->HSI48State)!= RCC_HSI48_OFF)
+    {
+      /* Enable the Internal Low Speed oscillator (HSI48). */
+      __HAL_RCC_HSI48_ENABLE();
+
+      /* Get time-out */
+      tickstart = HAL_GetTick();
+
+      /* Wait till HSI48 is ready */
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U)
+      {
+        if((HAL_GetTick() - tickstart ) > HSI48_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    else
+    {
+      /* Disable the Internal Low Speed oscillator (HSI48). */
+      __HAL_RCC_HSI48_DISABLE();
+
+      /* Get time-out */
+      tickstart = HAL_GetTick();
+
+      /* Wait till HSI48 is ready */
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U)
+      {
+        if((HAL_GetTick() - tickstart ) > HSI48_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  /*------------------------------ LSE Configuration -------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
+
+    /* Enable write access to Backup domain */
+    PWR->CR1 |= PWR_CR1_DBP;
+
+    /* Wait for Backup domain Write protection disable */
+    tickstart = HAL_GetTick();
+
+    while((PWR->CR1 & PWR_CR1_DBP) == 0U)
+    {
+      if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Set the new LSE configuration -----------------------------------------*/
+    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
+    /* Check the LSE State */
+    if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
+    {
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSE is ready */
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
+      {
+        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    else
+    {
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSE is disabled */
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
+      {
+        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  /*-------------------------------- PLL Configuration -----------------------*/
+  /* Check the parameters */
+  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
+  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
+  {
+    /* Check if the PLL is used as system clock or not */
+    if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1)
+    {
+      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
+      {
+        /* Check the parameters */
+        assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
+        assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
+        assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
+        assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
+        assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
+        assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
+        assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN));
+
+        /* Disable the main PLL. */
+        __HAL_RCC_PLL_DISABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till PLL is disabled */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
+        {
+          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+
+        /* Configure the main PLL clock source, multiplication and division factors. */
+        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
+                             RCC_OscInitStruct->PLL.PLLM,
+                             RCC_OscInitStruct->PLL.PLLN,
+                             RCC_OscInitStruct->PLL.PLLP,
+                             RCC_OscInitStruct->PLL.PLLQ,
+                             RCC_OscInitStruct->PLL.PLLR);
+
+         /* Disable PLLFRACN . */
+         __HAL_RCC_PLLFRACN_DISABLE();
+
+         /* Configure PLL PLL1FRACN */
+         __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN);
+
+        /* Select PLL1 input reference frequency range: VCI */
+        __HAL_RCC_PLL_VCIRANGE(RCC_OscInitStruct->PLL.PLLRGE) ;
+
+        /* Select PLL1 output frequency range : VCO */
+        __HAL_RCC_PLL_VCORANGE(RCC_OscInitStruct->PLL.PLLVCOSEL) ;
+
+        /* Enable PLL System Clock output. */
+         __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
+
+        /* Enable PLL1Q Clock output. */
+         __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+        /* Enable PLL1R  Clock output. */
+         __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR);
+
+        /* Enable PLL1FRACN . */
+         __HAL_RCC_PLLFRACN_ENABLE();
+
+        /* Enable the main PLL. */
+        __HAL_RCC_PLL_ENABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till PLL is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
+        {
+          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+      else
+      {
+        /* Disable the main PLL. */
+        __HAL_RCC_PLL_DISABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till PLL is disabled */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
+        {
+          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+    else
+    {
+      /* Do not return HAL_ERROR if request repeats the current configuration */
+      temp1_pllckcfg = RCC->PLLCKSELR;
+      temp2_pllckcfg = RCC->PLL1DIVR;
+      if(((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
+	 (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
+         ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) ||
+         (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) ||
+         ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) ||
+         ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) ||
+         ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U)))
+      {
+        return HAL_ERROR;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CPU, AHB and APB buses clocks according to the specified
+  *         parameters in the RCC_ClkInitStruct.
+  * @param  RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
+  *         contains the configuration information for the RCC peripheral.
+  * @param  FLatency: FLASH Latency, this parameter depend on device selected
+  *
+  * @note   The SystemCoreClock CMSIS variable is used to store System Core Clock Frequency
+  *         and updated by HAL_InitTick() function called within this function
+  *
+  * @note   The HSI is used (enabled by hardware) as system clock source after
+  *         start-up from Reset, wake-up from STOP and STANDBY mode, or in case
+  *         of failure of the HSE used directly or indirectly as system clock
+  *         (if the Clock Security System CSS is enabled).
+  *
+  * @note   A switch from one clock source to another occurs only if the target
+  *         clock source is ready (clock stable after start-up delay or PLL locked).
+  *         If a clock source which is not yet ready is selected, the switch will
+  *         occur when the clock source will be ready.
+  *         You can use HAL_RCC_GetClockConfig() function to know which clock is
+  *         currently used as system clock source.
+  * @note   Depending on the device voltage range, the software has to set correctly
+  *         D1CPRE[3:0] bits to ensure that  Domain1 core clock not exceed the maximum allowed frequency
+  *         (for more details refer to section above "Initialization/de-initialization functions")
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
+{
+  HAL_StatusTypeDef halstatus;
+  uint32_t tickstart;
+  uint32_t common_system_clock;
+
+   /* Check Null pointer */
+  if(RCC_ClkInitStruct == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
+  assert_param(IS_FLASH_LATENCY(FLatency));
+
+  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
+    must be correctly programmed according to the frequency of the CPU clock
+    (HCLK) and the supply voltage of the device. */
+
+  /* Increasing the CPU frequency */
+  if(FLatency > __HAL_FLASH_GET_LATENCY())
+  {
+    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+    __HAL_FLASH_SET_LATENCY(FLatency);
+
+    /* Check that the new number of wait states is taken into account to access the Flash
+    memory by reading the FLASH_ACR register */
+    if(__HAL_FLASH_GET_LATENCY() != FLatency)
+    {
+      return HAL_ERROR;
+    }
+
+  }
+
+  /* Increasing the BUS frequency divider */
+  /*-------------------------- D1PCLK1/CDPCLK1 Configuration ---------------------------*/
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1)
+  {
+#if defined (RCC_D1CFGR_D1PPRE)
+    if((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_D1PPRE))
+    {
+      assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider));
+      MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider);
+    }
+#else
+    if((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE))
+    {
+      assert_param(IS_RCC_CDPCLK1(RCC_ClkInitStruct->APB3CLKDivider));
+      MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, RCC_ClkInitStruct->APB3CLKDivider);
+    }
+#endif
+  }
+
+  /*-------------------------- PCLK1 Configuration ---------------------------*/
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+  {
+#if defined (RCC_D2CFGR_D2PPRE1)
+    if((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1))
+    {
+      assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
+      MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
+    }
+#else
+    if((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1))
+    {
+      assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
+      MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
+  }
+#endif
+    }
+  /*-------------------------- PCLK2 Configuration ---------------------------*/
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+  {
+#if defined(RCC_D2CFGR_D2PPRE2)
+    if((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2))
+    {
+      assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
+      MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
+    }
+#else
+     if((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2))
+    {
+      assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
+      MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
+    }
+#endif
+  }
+
+  /*-------------------------- D3PCLK1 Configuration ---------------------------*/
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1)
+  {
+#if defined(RCC_D3CFGR_D3PPRE)
+    if((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->D3CFGR & RCC_D3CFGR_D3PPRE))
+    {
+      assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider));
+      MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider) );
+    }
+#else
+    if((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE))
+    {
+      assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider));
+      MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, (RCC_ClkInitStruct->APB4CLKDivider) );
+    }
+#endif
+  }
+
+   /*-------------------------- HCLK Configuration --------------------------*/
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+  {
+#if defined (RCC_D1CFGR_HPRE)
+    if((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_HPRE))
+    {
+      /* Set the new HCLK clock divider */
+      assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+      MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+    }
+#else
+        if((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->CDCFGR1 & RCC_CDCFGR1_HPRE))
+    {
+      /* Set the new HCLK clock divider */
+      assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+      MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+    }
+#endif
+  }
+
+    /*------------------------- SYSCLK Configuration -------------------------*/
+    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
+    {
+      assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider));
+      assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
+#if defined(RCC_D1CFGR_D1CPRE)
+      MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider);
+#else
+      MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, RCC_ClkInitStruct->SYSCLKDivider);
+#endif
+      /* HSE is selected as System Clock Source */
+      if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+      {
+        /* Check the HSE ready flag */
+        if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
+        {
+          return HAL_ERROR;
+        }
+      }
+      /* PLL is selected as System Clock Source */
+      else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+      {
+        /* Check the PLL ready flag */
+        if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
+        {
+          return HAL_ERROR;
+        }
+      }
+      /* CSI is selected as System Clock Source */
+      else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI)
+      {
+        /* Check the PLL ready flag */
+        if(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)
+        {
+          return HAL_ERROR;
+        }
+      }
+      /* HSI is selected as System Clock Source */
+      else
+      {
+        /* Check the HSI ready flag */
+        if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
+        {
+          return HAL_ERROR;
+        }
+      }
+      MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
+
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+        while (__HAL_RCC_GET_SYSCLK_SOURCE() !=  (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
+        {
+          if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+
+    }
+
+    /* Decreasing the BUS frequency divider */
+   /*-------------------------- HCLK Configuration --------------------------*/
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+  {
+#if defined(RCC_D1CFGR_HPRE)
+    if((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_HPRE))
+    {
+      /* Set the new HCLK clock divider */
+      assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+      MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+    }
+#else
+    if((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->CDCFGR1 & RCC_CDCFGR1_HPRE))
+    {
+      /* Set the new HCLK clock divider */
+      assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+      MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+    }
+#endif
+  }
+
+  /* Decreasing the number of wait states because of lower CPU frequency */
+  if(FLatency < __HAL_FLASH_GET_LATENCY())
+  {
+    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+    __HAL_FLASH_SET_LATENCY(FLatency);
+
+    /* Check that the new number of wait states is taken into account to access the Flash
+    memory by reading the FLASH_ACR register */
+    if(__HAL_FLASH_GET_LATENCY() != FLatency)
+    {
+      return HAL_ERROR;
+    }
+ }
+
+  /*-------------------------- D1PCLK1/CDPCLK Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1)
+ {
+#if defined(RCC_D1CFGR_D1PPRE)
+   if((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_D1PPRE))
+   {
+     assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider));
+     MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider);
+   }
+#else
+   if((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE))
+   {
+     assert_param(IS_RCC_CDPCLK1(RCC_ClkInitStruct->APB3CLKDivider));
+     MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, RCC_ClkInitStruct->APB3CLKDivider);
+   }
+#endif
+ }
+
+  /*-------------------------- PCLK1 Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ {
+#if defined(RCC_D2CFGR_D2PPRE1)
+   if((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1))
+   {
+     assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
+     MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
+   }
+#else
+   if((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1))
+   {
+     assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
+     MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
+   }
+#endif
+ }
+
+  /*-------------------------- PCLK2 Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+ {
+#if defined (RCC_D2CFGR_D2PPRE2)
+   if((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2))
+   {
+     assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
+     MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
+   }
+#else
+   if((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2))
+   {
+     assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
+     MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
+   }
+#endif
+ }
+
+  /*-------------------------- D3PCLK1/SRDPCLK1 Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1)
+ {
+#if defined(RCC_D3CFGR_D3PPRE)
+   if((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->D3CFGR & RCC_D3CFGR_D3PPRE))
+   {
+     assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider));
+     MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider) );
+   }
+#else
+   if((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE))
+   {
+     assert_param(IS_RCC_SRDPCLK1(RCC_ClkInitStruct->APB4CLKDivider));
+     MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, (RCC_ClkInitStruct->APB4CLKDivider) );
+   }
+#endif
+ }
+
+  /* Update the SystemCoreClock global variable */
+#if defined(RCC_D1CFGR_D1CPRE)
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
+#else
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
+#endif
+
+#if defined(RCC_D1CFGR_HPRE)
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+#else
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+#endif
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  SystemCoreClock = SystemD2Clock;
+#else
+  SystemCoreClock = common_system_clock;
+#endif /* DUAL_CORE && CORE_CM4 */
+
+  /* Configure the source of time base considering new system clocks settings*/
+  halstatus = HAL_InitTick (uwTickPrio);
+
+  return halstatus;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Group2 Peripheral Control functions
+ *  @brief   RCC clocks control functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the RCC Clocks
+    frequencies.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
+  * @note   PA8/PC9 should be configured in alternate function mode.
+  * @param  RCC_MCOx: specifies the output direction for the clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
+  *            @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
+  * @param  RCC_MCOSource: specifies the clock source to output.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_PLL1QCLK:  PLL1Q clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_HSI48: HSI48 (48MHZ) selected as MCO1 source
+  *            @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_PLL2PCLK: PLL2P clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_PLLCLK:  PLL1P clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_CSICLK:  CSI clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_LSICLK:  LSI clock selected as MCO2 source
+  * @param  RCC_MCODiv: specifies the MCOx pre-scaler.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCODIV_1 up to RCC_MCODIV_15  : divider applied to MCOx clock
+  * @retval None
+  */
+void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
+{
+  GPIO_InitTypeDef GPIO_InitStruct;
+  /* Check the parameters */
+  assert_param(IS_RCC_MCO(RCC_MCOx));
+  assert_param(IS_RCC_MCODIV(RCC_MCODiv));
+  /* RCC_MCO1 */
+  if(RCC_MCOx == RCC_MCO1)
+  {
+    assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
+
+    /* MCO1 Clock Enable */
+    MCO1_CLK_ENABLE();
+
+    /* Configure the MCO1 pin in alternate function mode */
+    GPIO_InitStruct.Pin = MCO1_PIN;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
+    HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
+
+    /* Mask MCO1 and MCO1PRE[3:0] bits then Select MCO1 clock source and pre-scaler */
+    MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
+  }
+  else
+  {
+    assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
+
+    /* MCO2 Clock Enable */
+    MCO2_CLK_ENABLE();
+
+    /* Configure the MCO2 pin in alternate function mode */
+    GPIO_InitStruct.Pin = MCO2_PIN;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
+    HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
+
+    /* Mask MCO2 and MCO2PRE[3:0] bits then Select MCO2 clock source and pre-scaler */
+    MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 7U)));
+  }
+}
+
+/**
+  * @brief  Enables the Clock Security System.
+  * @note   If a failure is detected on the HSE oscillator clock, this oscillator
+  *         is automatically disabled and an interrupt is generated to inform the
+  *         software about the failure (Clock Security System Interrupt, CSSI),
+  *         allowing the MCU to perform rescue operations. The CSSI is linked to
+  *         the Cortex-M NMI (Non-Mask-able Interrupt) exception vector.
+  * @retval None
+  */
+void HAL_RCC_EnableCSS(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_CSSHSEON) ;
+}
+
+/**
+  * @brief  Disables the Clock Security System.
+  * @retval None
+  */
+void HAL_RCC_DisableCSS(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_CSSHSEON);
+}
+
+/**
+  * @brief  Returns the SYSCLK frequency
+  *
+  * @note   The system frequency computed by this function is not the real
+  *         frequency in the chip. It is calculated based on the predefined
+  *         constant and the selected clock source:
+  * @note     If SYSCLK source is CSI, function returns values based on CSI_VALUE(*)
+  * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
+  * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
+  * @note     If SYSCLK source is PLL, function returns values based on CSI_VALUE(*),
+  *           HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
+  * @note     (*) CSI_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value
+  *               4 MHz) but the real value may vary depending on the variations
+  *               in voltage and temperature.
+  * @note     (**) HSI_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value
+  *               64 MHz) but the real value may vary depending on the variations
+  *               in voltage and temperature.
+  * @note     (***) HSE_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value
+  *                25 MHz), user has to ensure that HSE_VALUE is same as the real
+  *                frequency of the crystal used. Otherwise, this function may
+  *                have wrong result.
+  *
+  * @note   The result of this function could be not correct when using fractional
+  *         value for HSE crystal.
+  *
+  * @note   This function can be used by the user application to compute the
+  *         baud rate for the communication peripherals or configure other parameters.
+  *
+  * @note   Each time SYSCLK changes, this function must be called to update the
+  *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
+  *
+  *
+  * @retval SYSCLK frequency
+  */
+uint32_t HAL_RCC_GetSysClockFreq(void)
+{
+  uint32_t pllp, pllsource, pllm, pllfracen, hsivalue;
+  float_t fracn1, pllvco;
+  uint32_t sysclockfreq;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+  case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */
+
+   if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+      {
+        sysclockfreq = (uint32_t) (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
+      }
+      else
+      {
+        sysclockfreq = (uint32_t) HSI_VALUE;
+      }
+
+    break;
+
+  case RCC_CFGR_SWS_CSI:  /* CSI used as system clock  source */
+    sysclockfreq = CSI_VALUE;
+    break;
+
+  case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
+    sysclockfreq = HSE_VALUE;
+    break;
+
+  case RCC_CFGR_SWS_PLL1:  /* PLL1 used as system clock  source */
+
+    /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
+    SYSCLK = PLL_VCO / PLLR
+    */
+    pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+    pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4)  ;
+    pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
+    fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
+
+    if (pllm != 0U)
+    {
+      switch (pllsource)
+      {
+      case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
+
+       if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+        {
+          hsivalue= (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
+          pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+        }
+        else
+        {
+          pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+        }
+        break;
+
+      case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
+        pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+        break;
+
+      case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
+        pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+        break;
+
+      default:
+        pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+        break;
+      }
+      pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
+      sysclockfreq =  (uint32_t)(float_t)(pllvco/(float_t)pllp);
+    }
+    else
+    {
+      sysclockfreq = 0U;
+    }
+    break;
+
+  default:
+    sysclockfreq = CSI_VALUE;
+    break;
+  }
+
+  return sysclockfreq;
+}
+
+
+/**
+  * @brief  Returns the HCLK frequency
+  * @note   Each time HCLK changes, this function must be called to update the
+  *         right HCLK value. Otherwise, any configuration based on this function will be incorrect.
+  *
+  * @note   The SystemD2Clock CMSIS variable is used to store System domain2 Clock Frequency
+  *         and updated within this function
+  * @retval HCLK frequency
+  */
+uint32_t HAL_RCC_GetHCLKFreq(void)
+{
+uint32_t common_system_clock;
+
+#if defined(RCC_D1CFGR_D1CPRE)
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
+#else
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU);
+#endif
+
+#if defined(RCC_D1CFGR_HPRE)
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+#else
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+#endif
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  SystemCoreClock = SystemD2Clock;
+#else
+  SystemCoreClock = common_system_clock;
+#endif /* DUAL_CORE && CORE_CM4 */
+
+  return SystemD2Clock;
+}
+
+
+/**
+  * @brief  Returns the PCLK1 frequency
+  * @note   Each time PCLK1 changes, this function must be called to update the
+  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
+  * @retval PCLK1 frequency
+  */
+uint32_t HAL_RCC_GetPCLK1Freq(void)
+{
+#if defined (RCC_D2CFGR_D2PPRE1)
+  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)>> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU));
+#else
+ /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1)>> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU));
+#endif
+}
+
+
+/**
+  * @brief  Returns the PCLK2 frequency
+  * @note   Each time PCLK2 changes, this function must be called to update the
+  *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
+  * @retval PCLK1 frequency
+  */
+uint32_t HAL_RCC_GetPCLK2Freq(void)
+{
+  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
+#if defined(RCC_D2CFGR_D2PPRE2)
+  return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)>> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU));
+#else
+  return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2)>> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU));
+#endif
+}
+
+/**
+  * @brief  Configures the RCC_OscInitStruct according to the internal
+  * RCC configuration registers.
+  * @param  RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
+  * will be configured.
+  * @retval None
+  */
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
+{
+  /* Set all possible values for the Oscillator type parameter ---------------*/
+  RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_CSI | \
+                                      RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI| RCC_OSCILLATORTYPE_HSI48;
+
+  /* Get the HSE configuration -----------------------------------------------*/
+#if defined(RCC_CR_HSEEXT)
+  if((RCC->CR &(RCC_CR_HSEBYP | RCC_CR_HSEEXT)) == RCC_CR_HSEBYP)
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
+  }
+  else if((RCC->CR &(RCC_CR_HSEBYP | RCC_CR_HSEEXT)) == (RCC_CR_HSEBYP | RCC_CR_HSEEXT))
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS_DIGITAL;
+  }
+  else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
+  }
+#else
+  if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
+  }
+  else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
+  }
+#endif /* RCC_CR_HSEEXT */
+
+   /* Get the CSI configuration -----------------------------------------------*/
+  if((RCC->CR &RCC_CR_CSION) == RCC_CR_CSION)
+  {
+    RCC_OscInitStruct->CSIState = RCC_CSI_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->CSIState = RCC_CSI_OFF;
+  }
+
+#if defined(RCC_VER_X)
+  if(HAL_GetREVID() <= REV_ID_Y)
+  {
+    RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk) >> HAL_RCC_REV_Y_CSITRIM_Pos);
+  }
+  else
+  {
+    RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
+  }
+#else
+ RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
+#endif /*RCC_VER_X*/
+
+  /* Get the HSI configuration -----------------------------------------------*/
+  if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
+  {
+    RCC_OscInitStruct->HSIState = RCC_HSI_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
+  }
+
+#if defined(RCC_VER_X)
+  if(HAL_GetREVID() <= REV_ID_Y)
+  {
+    RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk) >> HAL_RCC_REV_Y_HSITRIM_Pos);
+  }
+  else
+  {
+    RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
+  }
+#else
+    RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
+#endif /*RCC_VER_X*/
+
+  /* Get the LSE configuration -----------------------------------------------*/
+#if defined(RCC_BDCR_LSEEXT)
+  if((RCC->BDCR &(RCC_BDCR_LSEBYP|RCC_BDCR_LSEEXT)) == RCC_BDCR_LSEBYP)
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
+  }
+  else if((RCC->BDCR &(RCC_BDCR_LSEBYP|RCC_BDCR_LSEEXT)) == (RCC_BDCR_LSEBYP|RCC_BDCR_LSEEXT))
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS_DIGITAL;
+  }
+  else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
+  }
+#else
+  if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
+  }
+  else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
+  }
+#endif /* RCC_BDCR_LSEEXT */
+
+  /* Get the LSI configuration -----------------------------------------------*/
+  if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
+  {
+    RCC_OscInitStruct->LSIState = RCC_LSI_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
+  }
+
+  /* Get the HSI48 configuration ---------------------------------------------*/
+  if((RCC->CR & RCC_CR_HSI48ON) == RCC_CR_HSI48ON)
+  {
+    RCC_OscInitStruct->HSI48State = RCC_HSI48_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF;
+  }
+
+  /* Get the PLL configuration -----------------------------------------------*/
+  if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
+  {
+    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
+  }
+  RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+  RCC_OscInitStruct->PLL.PLLM = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> RCC_PLLCKSELR_DIVM1_Pos);
+  RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) >> RCC_PLL1DIVR_N1_Pos)+ 1U;
+  RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos)+ 1U;
+  RCC_OscInitStruct->PLL.PLLP = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos)+ 1U;
+  RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos)+ 1U;
+  RCC_OscInitStruct->PLL.PLLRGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL1RGE));
+  RCC_OscInitStruct->PLL.PLLVCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL1VCOSEL) >> RCC_PLLCFGR_PLL1VCOSEL_Pos);
+  RCC_OscInitStruct->PLL.PLLFRACN = (uint32_t)(((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos));
+}
+
+/**
+  * @brief  Configures the RCC_ClkInitStruct according to the internal
+  * RCC configuration registers.
+  * @param  RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
+  * will be configured.
+  * @param  pFLatency: Pointer on the Flash Latency.
+  * @retval None
+  */
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
+{
+  /* Set all possible values for the Clock type parameter --------------------*/
+  RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 |
+                                 RCC_CLOCKTYPE_PCLK2 |  RCC_CLOCKTYPE_D3PCLK1  ;
+
+  /* Get the SYSCLK configuration --------------------------------------------*/
+  RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
+
+#if defined(RCC_D1CFGR_D1CPRE)
+  /* Get the SYSCLK configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1CPRE);
+
+  /* Get the D1HCLK configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_HPRE);
+
+  /* Get the APB3 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1PPRE);
+
+  /* Get the APB1 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1);
+
+  /* Get the APB2 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2);
+
+  /* Get the APB4 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->D3CFGR & RCC_D3CFGR_D3PPRE);
+#else
+  /* Get the SYSCLK configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE);
+
+  /* Get the D1HCLK configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE);
+
+  /* Get the APB3 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE);
+
+  /* Get the APB1 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1);
+
+  /* Get the APB2 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2);
+
+  /* Get the APB4 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE);
+#endif
+
+  /* Get the Flash Wait State (Latency) configuration ------------------------*/
+  *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
+}
+
+/**
+  * @brief This function handles the RCC CSS interrupt request.
+  * @note This API should be called under the NMI_Handler().
+  * @retval None
+  */
+void HAL_RCC_NMI_IRQHandler(void)
+{
+  /* Check RCC CSSF flag  */
+  if(__HAL_RCC_GET_IT(RCC_IT_CSS))
+  {
+    /* RCC Clock Security System interrupt user callback */
+    HAL_RCC_CCSCallback();
+
+    /* Clear RCC CSS pending bit */
+    __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
+  }
+}
+
+/**
+  * @brief  RCC Clock Security System interrupt callback
+  * @retval none
+  */
+__weak void HAL_RCC_CCSCallback(void)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_RCC_CCSCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_RCC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c
new file mode 100644
index 00000000..fa08e692
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c
@@ -0,0 +1,3437 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_rcc_ex.c
+  * @author  MCD Application Team
+  * @brief   Extended RCC HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities RCC extension peripheral:
+  *           + Extended Peripheral Control functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup RCCEx  RCCEx
+  * @brief RCC HAL module driver
+  * @{
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup RCCEx_Private_defines Private Defines
+ * @{
+ */
+#define PLL2_TIMEOUT_VALUE         PLL_TIMEOUT_VALUE    /* 2 ms */
+#define PLL3_TIMEOUT_VALUE         PLL_TIMEOUT_VALUE    /* 2 ms */
+
+#define DIVIDER_P_UPDATE          0U
+#define DIVIDER_Q_UPDATE          1U
+#define DIVIDER_R_UPDATE          2U
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider);
+static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider);
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Functions Exported Functions
+  * @{
+  */
+
+/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
+ *  @brief  Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+                ##### Extended Peripheral Control functions  #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the RCC Clocks
+    frequencies.
+    [..]
+    (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
+        select the RTC clock source; in this case the Backup domain will be reset in
+        order to modify the RTC Clock source, as consequence RTC registers (including
+        the backup registers) and RCC_BDCR register are set to their reset values.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the RCC extended peripherals clocks according to the specified
+  *         parameters in the RCC_PeriphCLKInitTypeDef.
+  * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
+  *         contains the configuration information for the Extended Peripherals
+  *         clocks (SDMMC, CKPER, FMC, QSPI*, OSPI*, DSI, SPI45, SPDIF, DFSDM1, DFSDM2*, FDCAN, SWPMI, SAI23*,SAI2A*, SAI2B*, SAI1, SPI123,
+  *         USART234578, USART16 (USART16910*), RNG, HRTIM1*, I2C123, USB, CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC,
+  *         SAI4A*, SAI4B*, SPI6, RTC).
+  * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
+  *         the RTC clock source; in this case the Backup domain will be reset in
+  *         order to modify the RTC Clock source, as consequence RTC registers (including
+  *         the backup registers) are set to their reset values.
+  *
+  * (*) : Available on some STM32H7 lines only.
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  uint32_t tmpreg;
+  uint32_t tickstart;
+  HAL_StatusTypeDef ret = HAL_OK;      /* Intermediate status */
+  HAL_StatusTypeDef status = HAL_OK;   /* Final status */
+
+  /*---------------------------- SPDIFRX configuration -------------------------------*/
+
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
+  {
+
+    switch(PeriphClkInit->SpdifrxClockSelection)
+    {
+    case RCC_SPDIFRXCLKSOURCE_PLL:      /* PLL is used as clock source for SPDIFRX*/
+      /* Enable PLL1Q Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* SPDIFRX clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPDIFRXCLKSOURCE_PLL2: /* PLL2 is used as clock source for SPDIFRX*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
+
+      /* SPDIFRX clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPDIFRXCLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPDIFRX*/
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
+
+      /* SPDIFRX clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPDIFRXCLKSOURCE_HSI:
+      /* Internal OSC clock is used as source of SPDIFRX clock*/
+      /* SPDIFRX clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SPDIFRX clock*/
+      __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+  /*---------------------------- SAI1 configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
+  {
+    switch(PeriphClkInit->Sai1ClockSelection)
+    {
+    case RCC_SAI1CLKSOURCE_PLL:      /* PLL is used as clock source for SAI1*/
+      /* Enable SAI Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* SAI1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+
+      /* SAI1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI1CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI1*/
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
+
+      /* SAI1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI1CLKSOURCE_PIN:
+      /* External clock is used as source of SAI1 clock*/
+      /* SAI1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI1CLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */
+      /* SAI1 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SAI1 clock*/
+      __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+#if defined(SAI3)
+  /*---------------------------- SAI2/3 configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23)
+  {
+    switch(PeriphClkInit->Sai23ClockSelection)
+    {
+    case RCC_SAI23CLKSOURCE_PLL:      /* PLL is used as clock source for SAI2/3 */
+      /* Enable SAI Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* SAI2/3 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2/3 */
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+
+      /* SAI2/3 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI23CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2/3 */
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
+
+      /* SAI2/3 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI23CLKSOURCE_PIN:
+      /* External clock is used as source of SAI2/3 clock*/
+      /* SAI2/3 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI23CLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of SAI2/3 clock */
+      /* SAI2/3 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SAI2/3 clock*/
+      __HAL_RCC_SAI23_CONFIG(PeriphClkInit->Sai23ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+#endif /* SAI3 */
+
+#if defined(RCC_CDCCIP1R_SAI2ASEL)
+  /*---------------------------- SAI2A configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2A) == RCC_PERIPHCLK_SAI2A)
+  {
+    switch(PeriphClkInit->Sai2AClockSelection)
+    {
+    case RCC_SAI2ACLKSOURCE_PLL:      /* PLL is used as clock source for SAI2A */
+      /* Enable SAI2A Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* SAI2A clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI2ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2A */
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+
+      /* SAI2A clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI2ACLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2A */
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
+
+      /* SAI2A clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI2ACLKSOURCE_PIN:
+      /* External clock is used as source of SAI2A clock*/
+      /* SAI2A clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI2ACLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of SAI2A clock */
+      /* SAI2A clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI2ACLKSOURCE_SPDIF:
+      /* SPDIF clock is used as source of SAI2A clock */
+      /* SAI2A clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SAI2A clock*/
+      __HAL_RCC_SAI2A_CONFIG(PeriphClkInit->Sai2AClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+#endif  /*SAI2A*/
+
+#if defined(RCC_CDCCIP1R_SAI2BSEL)
+
+  /*---------------------------- SAI2B configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2B) == RCC_PERIPHCLK_SAI2B)
+  {
+    switch(PeriphClkInit->Sai2BClockSelection)
+    {
+    case RCC_SAI2BCLKSOURCE_PLL:      /* PLL is used as clock source for SAI2B */
+      /* Enable SAI Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* SAI2B clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI2BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2B */
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+
+      /* SAI2B clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI2BCLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2B */
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
+
+      /* SAI2B clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI2BCLKSOURCE_PIN:
+      /* External clock is used as source of SAI2B clock*/
+      /* SAI2B clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI2BCLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of SAI2B clock */
+      /* SAI2B clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI2BCLKSOURCE_SPDIF:
+      /* SPDIF clock is used as source of SAI2B clock */
+      /* SAI2B clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SAI2B clock*/
+      __HAL_RCC_SAI2B_CONFIG(PeriphClkInit->Sai2BClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+#endif  /*SAI2B*/
+
+#if defined(SAI4)
+  /*---------------------------- SAI4A configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A)
+  {
+    switch(PeriphClkInit->Sai4AClockSelection)
+    {
+    case RCC_SAI4ACLKSOURCE_PLL:      /* PLL is used as clock source for SAI2*/
+      /* Enable SAI Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* SAI1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI4ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+
+      /* SAI2 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI4ACLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2*/
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
+
+      /* SAI1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI4ACLKSOURCE_PIN:
+      /* External clock is used as source of SAI2 clock*/
+      /* SAI2 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI4ACLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */
+      /* SAI1 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SAI4A clock*/
+      __HAL_RCC_SAI4A_CONFIG(PeriphClkInit->Sai4AClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+  /*---------------------------- SAI4B configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B)
+  {
+    switch(PeriphClkInit->Sai4BClockSelection)
+    {
+    case RCC_SAI4BCLKSOURCE_PLL:      /* PLL is used as clock source for SAI2*/
+      /* Enable SAI Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* SAI1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI4BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+
+      /* SAI2 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI4BCLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2*/
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
+
+      /* SAI1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI4BCLKSOURCE_PIN:
+      /* External clock is used as source of SAI2 clock*/
+      /* SAI2 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI4BCLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */
+      /* SAI1 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SAI4B clock*/
+      __HAL_RCC_SAI4B_CONFIG(PeriphClkInit->Sai4BClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+#endif  /*SAI4*/
+
+#if defined(QUADSPI)
+  /*---------------------------- QSPI configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI)
+  {
+    switch(PeriphClkInit->QspiClockSelection)
+    {
+    case RCC_QSPICLKSOURCE_PLL:      /* PLL is used as clock source for QSPI*/
+      /* Enable QSPI Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* QSPI clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_QSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for QSPI*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
+
+      /* QSPI clock source configuration done later after clock selection check */
+      break;
+
+
+    case RCC_QSPICLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of QSPI clock */
+      /* QSPI clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_QSPICLKSOURCE_D1HCLK:
+      /* Domain1 HCLK  clock selected as QSPI kernel peripheral clock */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of QSPI clock*/
+      __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+#endif  /*QUADSPI*/
+
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+  /*---------------------------- OCTOSPI configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI)
+  {
+    switch(PeriphClkInit->OspiClockSelection)
+    {
+    case RCC_OSPICLKSOURCE_PLL:      /* PLL is used as clock source for OSPI*/
+      /* Enable OSPI Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* OSPI clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_OSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for OSPI*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
+
+      /* OSPI clock source configuration done later after clock selection check */
+      break;
+
+
+    case RCC_OSPICLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of OSPI clock */
+      /* OSPI clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_OSPICLKSOURCE_HCLK:
+      /* HCLK clock selected as OSPI kernel peripheral clock */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of OSPI clock*/
+      __HAL_RCC_OSPI_CONFIG(PeriphClkInit->OspiClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+#endif  /*OCTOSPI*/
+
+  /*---------------------------- SPI1/2/3 configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123)
+  {
+    switch(PeriphClkInit->Spi123ClockSelection)
+    {
+    case RCC_SPI123CLKSOURCE_PLL:      /* PLL is used as clock source for SPI1/2/3 */
+      /* Enable SPI Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* SPI1/2/3 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI1/2/3 */
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+
+      /* SPI1/2/3 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI123CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPI1/2/3 */
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
+
+      /* SPI1/2/3 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI123CLKSOURCE_PIN:
+      /* External clock is used as source of SPI1/2/3 clock*/
+      /* SPI1/2/3 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI123CLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of SPI1/2/3 clock */
+      /* SPI1/2/3 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SPI1/2/3 clock*/
+      __HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+  /*---------------------------- SPI4/5 configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45)
+  {
+    switch(PeriphClkInit->Spi45ClockSelection)
+    {
+    case RCC_SPI45CLKSOURCE_PCLK1:      /* CD/D2 PCLK1 as clock source for SPI4/5 */
+      /* SPI4/5 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI4/5 */
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
+
+      /* SPI4/5 clock source configuration done later after clock selection check */
+      break;
+    case RCC_SPI45CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPI4/5 */
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
+      /* SPI4/5 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI45CLKSOURCE_HSI:
+      /* HSI oscillator clock is used as source of SPI4/5 clock*/
+      /* SPI4/5 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI45CLKSOURCE_CSI:
+      /*  CSI oscillator clock is used as source of SPI4/5 clock */
+      /* SPI4/5 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI45CLKSOURCE_HSE:
+      /* HSE,  oscillator is used as source of SPI4/5 clock */
+      /* SPI4/5 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SPI4/5 clock*/
+      __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+  /*---------------------------- SPI6 configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6)
+  {
+    switch(PeriphClkInit->Spi6ClockSelection)
+    {
+    case RCC_SPI6CLKSOURCE_PCLK4:      /* SRD/D3 PCLK1 (PCLK4) as clock source for SPI6*/
+      /* SPI6 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI6*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
+
+      /* SPI6 clock source configuration done later after clock selection check */
+      break;
+    case RCC_SPI6CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPI6*/
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
+      /* SPI6 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI6CLKSOURCE_HSI:
+      /* HSI oscillator clock is used as source of SPI6 clock*/
+      /* SPI6 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI6CLKSOURCE_CSI:
+      /*  CSI oscillator clock is used as source of SPI6 clock */
+      /* SPI6 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI6CLKSOURCE_HSE:
+      /* HSE,  oscillator is used as source of SPI6 clock */
+      /* SPI6 clock source configuration done later after clock selection check */
+      break;
+#if defined(RCC_SPI6CLKSOURCE_PIN)
+    case RCC_SPI6CLKSOURCE_PIN:
+      /* 2S_CKIN is used as source of SPI6 clock */
+      /* SPI6 clock source configuration done later after clock selection check */
+      break;
+#endif
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SPI6 clock*/
+      __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+#if defined(DSI)
+  /*---------------------------- DSI configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI)
+  {
+    switch(PeriphClkInit->DsiClockSelection)
+    {
+
+    case RCC_DSICLKSOURCE_PLL2: /* PLL2 is used as clock source for DSI*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
+
+      /* DSI clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_DSICLKSOURCE_PHY:
+      /* PHY is used as clock source for DSI*/
+      /* DSI clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of DSI clock*/
+      __HAL_RCC_DSI_CONFIG(PeriphClkInit->DsiClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+#endif /*DSI*/
+
+#if defined(FDCAN1) || defined(FDCAN2)
+  /*---------------------------- FDCAN configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
+  {
+    switch(PeriphClkInit->FdcanClockSelection)
+    {
+    case RCC_FDCANCLKSOURCE_PLL:      /* PLL is used as clock source for FDCAN*/
+      /* Enable FDCAN Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* FDCAN clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
+
+      /* FDCAN clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_FDCANCLKSOURCE_HSE:
+      /* HSE is used as clock source for FDCAN*/
+      /* FDCAN clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of FDCAN clock*/
+      __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+#endif /*FDCAN1 || FDCAN2*/
+
+  /*---------------------------- FMC configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC)
+  {
+    switch(PeriphClkInit->FmcClockSelection)
+    {
+    case RCC_FMCCLKSOURCE_PLL:      /* PLL is used as clock source for FMC*/
+      /* Enable FMC Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* FMC clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_FMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for FMC*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
+
+      /* FMC clock source configuration done later after clock selection check */
+      break;
+
+
+    case RCC_FMCCLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of FMC clock */
+      /* FMC clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_FMCCLKSOURCE_HCLK:
+      /* D1/CD HCLK  clock selected as FMC kernel peripheral clock */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of FMC clock*/
+      __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+  /*---------------------------- RTC configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
+  {
+    /* check for RTC Parameters used to output RTCCLK */
+    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+
+    /* Enable write access to Backup domain */
+    SET_BIT(PWR->CR1, PWR_CR1_DBP);
+
+    /* Wait for Backup domain Write protection disable */
+    tickstart = HAL_GetTick();
+
+    while((PWR->CR1 & PWR_CR1_DBP) == 0U)
+    {
+      if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+      {
+        ret = HAL_TIMEOUT;
+        break;
+      }
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Reset the Backup domain only if the RTC Clock source selection is modified */
+      if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
+      {
+        /* Store the content of BDCR register before the reset of Backup Domain */
+        tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+        /* RTC Clock selection can be changed only if the Backup Domain is reset */
+        __HAL_RCC_BACKUPRESET_FORCE();
+        __HAL_RCC_BACKUPRESET_RELEASE();
+        /* Restore the Content of BDCR register */
+        RCC->BDCR = tmpreg;
+      }
+
+      /* If LSE is selected as RTC clock source (and enabled prior to Backup Domain reset), wait for LSE reactivation */
+      if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
+      {
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till LSE is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
+        {
+          if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
+          {
+            ret = HAL_TIMEOUT;
+            break;
+          }
+        }
+      }
+
+      if(ret == HAL_OK)
+      {
+        __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+      }
+      else
+      {
+        /* set overall return value */
+        status = ret;
+      }
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+
+  /*-------------------------- USART1/6 configuration --------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16)
+  {
+    switch(PeriphClkInit->Usart16ClockSelection)
+    {
+    case RCC_USART16CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for USART1/6 */
+      /* USART1/6 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USART16CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART1/6 */
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
+      /* USART1/6 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USART16CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1/6 */
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
+      /* USART1/6 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USART16CLKSOURCE_HSI:
+      /* HSI oscillator clock is used as source of USART1/6 clock */
+      /* USART1/6 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USART16CLKSOURCE_CSI:
+      /* CSI oscillator clock is used as source of USART1/6 clock */
+      /* USART1/6 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USART16CLKSOURCE_LSE:
+      /* LSE,  oscillator is used as source of USART1/6 clock */
+      /* USART1/6 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of USART1/6 clock */
+      __HAL_RCC_USART16_CONFIG(PeriphClkInit->Usart16ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+  /*-------------------------- USART2/3/4/5/7/8 Configuration --------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578)
+  {
+    switch(PeriphClkInit->Usart234578ClockSelection)
+    {
+    case RCC_USART234578CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for USART2/3/4/5/7/8 */
+      /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USART234578CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART2/3/4/5/7/8 */
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
+      /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USART234578CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART2/3/4/5/7/8 */
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
+      /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USART234578CLKSOURCE_HSI:
+      /* HSI oscillator clock is used as source of USART2/3/4/5/7/8 clock */
+      /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USART234578CLKSOURCE_CSI:
+      /* CSI oscillator clock is used as source of USART2/3/4/5/7/8 clock */
+      /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USART234578CLKSOURCE_LSE:
+      /* LSE,  oscillator is used as source of USART2/3/4/5/7/8 clock */
+      /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of USART2/3/4/5/7/8 clock */
+      __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+  /*-------------------------- LPUART1 Configuration -------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
+  {
+    switch(PeriphClkInit->Lpuart1ClockSelection)
+    {
+    case RCC_LPUART1CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPUART1 */
+      /* LPUART1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPUART1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPUART1 */
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
+      /* LPUART1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPUART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPUART1 */
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
+      /* LPUART1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPUART1CLKSOURCE_HSI:
+      /* HSI oscillator clock is used as source of LPUART1 clock */
+      /* LPUART1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPUART1CLKSOURCE_CSI:
+      /* CSI oscillator clock is used as source of LPUART1 clock */
+      /* LPUART1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPUART1CLKSOURCE_LSE:
+      /* LSE,  oscillator is used as source of LPUART1 clock */
+      /* LPUART1 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of LPUART1 clock */
+      __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+  /*---------------------------- LPTIM1 configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
+  {
+    switch(PeriphClkInit->Lptim1ClockSelection)
+    {
+    case RCC_LPTIM1CLKSOURCE_PCLK1:      /* CD/D2 PCLK1 as clock source for LPTIM1*/
+      /* LPTIM1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM1*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+
+      /* LPTIM1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM1CLKSOURCE_PLL3:  /* PLL3 is used as clock source for LPTIM1*/
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
+
+      /* LPTIM1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM1CLKSOURCE_LSE:
+      /* External low speed OSC clock is used as source of LPTIM1 clock*/
+      /* LPTIM1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM1CLKSOURCE_LSI:
+      /* Internal  low speed OSC clock is used  as source of LPTIM1 clock*/
+      /* LPTIM1 clock source configuration done later after clock selection check */
+      break;
+    case RCC_LPTIM1CLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of LPTIM1 clock */
+      /* LPTIM1 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of LPTIM1 clock*/
+      __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+  /*---------------------------- LPTIM2 configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2)
+  {
+    switch(PeriphClkInit->Lptim2ClockSelection)
+    {
+    case RCC_LPTIM2CLKSOURCE_PCLK4:      /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM2*/
+      /* LPTIM2 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM2CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM2*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+
+      /* LPTIM2 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM2CLKSOURCE_PLL3:  /* PLL3 is used as clock source for LPTIM2*/
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
+
+      /* LPTIM2 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM2CLKSOURCE_LSE:
+      /* External low speed OSC clock is used as source of LPTIM2 clock*/
+      /* LPTIM2 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM2CLKSOURCE_LSI:
+      /* Internal  low speed OSC clock is used  as source of LPTIM2 clock*/
+      /* LPTIM2 clock source configuration done later after clock selection check */
+      break;
+    case RCC_LPTIM2CLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */
+      /* LPTIM2 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of LPTIM2 clock*/
+      __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+  /*---------------------------- LPTIM345 configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345)
+  {
+    switch(PeriphClkInit->Lptim345ClockSelection)
+    {
+
+    case RCC_LPTIM345CLKSOURCE_PCLK4:      /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM3/4/5 */
+      /* LPTIM3/4/5 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM345CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM3/4/5 */
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+
+      /* LPTIM3/4/5 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM345CLKSOURCE_PLL3:  /* PLL3 is used as clock source for LPTIM3/4/5 */
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
+
+      /* LPTIM3/4/5 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM345CLKSOURCE_LSE:
+      /* External low speed OSC clock is used as source of LPTIM3/4/5 clock */
+      /* LPTIM3/4/5 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM345CLKSOURCE_LSI:
+      /* Internal  low speed OSC clock is used  as source of LPTIM3/4/5 clock */
+      /* LPTIM3/4/5 clock source configuration done later after clock selection check */
+      break;
+    case RCC_LPTIM345CLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of LPTIM3/4/5 clock */
+      /* LPTIM3/4/5 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of LPTIM3/4/5 clock */
+      __HAL_RCC_LPTIM345_CONFIG(PeriphClkInit->Lptim345ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+  /*------------------------------ I2C1/2/3 Configuration ------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2C123CLKSOURCE(PeriphClkInit->I2c123ClockSelection));
+
+    if ((PeriphClkInit->I2c123ClockSelection )== RCC_I2C123CLKSOURCE_PLL3 )
+    {
+        if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!= HAL_OK)
+        {
+          status = HAL_ERROR;
+        }
+    }
+
+      __HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection);
+
+  }
+
+  /*------------------------------ I2C4 Configuration ------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
+
+    if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3 )
+    {
+      if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!= HAL_OK)
+      {
+        status = HAL_ERROR;
+      }
+    }
+
+      __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
+
+  }
+
+  /*---------------------------- ADC configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
+  {
+    switch(PeriphClkInit->AdcClockSelection)
+    {
+
+    case RCC_ADCCLKSOURCE_PLL2: /* PLL2 is used as clock source for ADC*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+
+      /* ADC clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_ADCCLKSOURCE_PLL3:  /* PLL3 is used as clock source for ADC*/
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
+
+      /* ADC clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_ADCCLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of ADC clock */
+      /* ADC clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of ADC clock*/
+      __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+  /*------------------------------ USB Configuration -------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
+  {
+
+    switch(PeriphClkInit->UsbClockSelection)
+    {
+    case RCC_USBCLKSOURCE_PLL:      /* PLL is used as clock source for USB*/
+      /* Enable USB Clock output generated form System USB . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* USB clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USBCLKSOURCE_PLL3: /* PLL3 is used as clock source for USB*/
+
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
+
+      /* USB clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USBCLKSOURCE_HSI48:
+      /* HSI48 oscillator is used as source of USB clock */
+      /* USB clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of USB clock*/
+      __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+
+  }
+
+  /*------------------------------------- SDMMC Configuration ------------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SDMMC(PeriphClkInit->SdmmcClockSelection));
+
+    switch(PeriphClkInit->SdmmcClockSelection)
+    {
+    case RCC_SDMMCCLKSOURCE_PLL:      /* PLL is used as clock source for SDMMC*/
+      /* Enable SDMMC Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* SDMMC clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for SDMMC*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
+
+      /* SDMMC clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SDMMC clock*/
+      __HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+#if defined(LTDC)
+  /*-------------------------------------- LTDC Configuration -----------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
+  {
+    if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!=HAL_OK)
+    {
+      status=HAL_ERROR;
+    }
+  }
+#endif /* LTDC */
+
+  /*------------------------------ RNG Configuration -------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG)
+  {
+
+    switch(PeriphClkInit->RngClockSelection)
+    {
+    case RCC_RNGCLKSOURCE_PLL:     /* PLL is used as clock source for RNG*/
+      /* Enable RNG Clock output generated form System RNG . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* RNG clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_RNGCLKSOURCE_LSE: /* LSE is used as clock source for RNG*/
+
+      /* RNG clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_RNGCLKSOURCE_LSI: /* LSI is used as clock source for RNG*/
+
+      /* RNG clock source configuration done later after clock selection check */
+      break;
+    case RCC_RNGCLKSOURCE_HSI48:
+      /* HSI48 oscillator is used as source of RNG clock */
+      /* RNG clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of RNG clock*/
+      __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+
+  }
+
+  /*------------------------------ SWPMI1 Configuration ------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection));
+
+    /* Configure the SWPMI1 interface clock source */
+    __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);
+  }
+#if defined(HRTIM)
+  /*------------------------------ HRTIM1 clock Configuration ----------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection));
+
+    /* Configure the HRTIM1 clock source */
+    __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection);
+  }
+#endif  /*HRTIM*/
+  /*------------------------------ DFSDM1 Configuration ------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
+
+    /* Configure the DFSDM1 interface clock source */
+    __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
+  }
+
+#if defined(DFSDM2_BASE)
+  /*------------------------------ DFSDM2 Configuration ------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2) == RCC_PERIPHCLK_DFSDM2)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_DFSDM2CLKSOURCE(PeriphClkInit->Dfsdm2ClockSelection));
+
+    /* Configure the DFSDM2 interface clock source */
+    __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection);
+  }
+#endif  /* DFSDM2 */
+
+  /*------------------------------------ TIM configuration --------------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
+
+    /* Configure Timer Prescaler */
+    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
+  }
+
+  /*------------------------------------ CKPER configuration --------------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_CLKPSOURCE(PeriphClkInit->CkperClockSelection));
+
+    /* Configure the CKPER clock source */
+    __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection);
+  }
+
+  if (status == HAL_OK)
+  {
+    return HAL_OK;
+  }
+  return HAL_ERROR;
+}
+
+/**
+  * @brief  Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
+  * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
+  *         returns the configuration information for the Extended Peripherals clocks :
+  *         (SDMMC, CKPER, FMC, QSPI*, OSPI*, DSI*, SPI45, SPDIF, DFSDM1, DFSDM2*, FDCAN, SWPMI, SAI23*, SAI1, SPI123,
+  *         USART234578, USART16, RNG, HRTIM1*, I2C123, USB, CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC.
+  *         SAI4A*, SAI4B*, SPI6, RTC, TIM).
+  * @retval None
+  *
+  *   (*) : Available on some STM32H7 lines only.
+  */
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  /* Set all possible values for the extended clock type parameter------------*/
+  PeriphClkInit->PeriphClockSelection =
+                 RCC_PERIPHCLK_USART16 | RCC_PERIPHCLK_USART234578 | RCC_PERIPHCLK_LPUART1 |
+                 RCC_PERIPHCLK_I2C4    | RCC_PERIPHCLK_LPTIM1      | RCC_PERIPHCLK_LPTIM2  | RCC_PERIPHCLK_LPTIM345 |
+                 RCC_PERIPHCLK_SAI1    | RCC_PERIPHCLK_SPI123      | RCC_PERIPHCLK_SPI45   | RCC_PERIPHCLK_SPI6     |
+	         RCC_PERIPHCLK_FDCAN   | RCC_PERIPHCLK_SDMMC       | RCC_PERIPHCLK_RNG     | RCC_PERIPHCLK_USB      |
+	         RCC_PERIPHCLK_ADC     | RCC_PERIPHCLK_SWPMI1      | RCC_PERIPHCLK_DFSDM1  | RCC_PERIPHCLK_RTC      |
+	         RCC_PERIPHCLK_CEC     | RCC_PERIPHCLK_FMC         | RCC_PERIPHCLK_SPDIFRX | RCC_PERIPHCLK_TIM      |
+	         RCC_PERIPHCLK_CKPER;
+
+PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C123;
+#if defined(RCC_CDCCIP1R_SAI2ASEL)
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI2A;
+#endif /* RCC_CDCCIP1R_SAI2ASEL */
+#if defined(RCC_CDCCIP1R_SAI2BSEL)
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI2B;
+#endif /* RCC_CDCCIP1R_SAI2BSEL */
+#if defined(SAI3)
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI23;
+#endif /* SAI3 */
+#if defined(SAI4)
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI4A;
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI4B;
+#endif /* SAI4 */
+#if defined(DFSDM2_BASE)
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_DFSDM2;
+#endif /* DFSDM2 */
+#if defined(QUADSPI)
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_QSPI;
+#endif /* QUADSPI */
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_OSPI;
+#endif /* OCTOSPI1 || OCTOSPI2 */
+#if defined(HRTIM)
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_HRTIM1;
+#endif /* HRTIM */
+#if defined(LTDC)
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LTDC;
+#endif /* LTDC */
+#if defined(DSI)
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_DSI;
+#endif /* DSI */
+
+  /* Get the PLL3 Clock configuration -----------------------------------------------*/
+  PeriphClkInit->PLL3.PLL3M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3)>> RCC_PLLCKSELR_DIVM3_Pos);
+  PeriphClkInit->PLL3.PLL3N = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_N3) >> RCC_PLL3DIVR_N3_Pos)+ 1U;
+  PeriphClkInit->PLL3.PLL3R = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> RCC_PLL3DIVR_R3_Pos)+ 1U;
+  PeriphClkInit->PLL3.PLL3P = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> RCC_PLL3DIVR_P3_Pos)+ 1U;
+  PeriphClkInit->PLL3.PLL3Q = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> RCC_PLL3DIVR_Q3_Pos)+ 1U;
+  PeriphClkInit->PLL3.PLL3RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3RGE) >> RCC_PLLCFGR_PLL3RGE_Pos);
+  PeriphClkInit->PLL3.PLL3VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3VCOSEL) >> RCC_PLLCFGR_PLL3VCOSEL_Pos);
+
+  /* Get the PLL2 Clock configuration -----------------------------------------------*/
+  PeriphClkInit->PLL2.PLL2M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2)>> RCC_PLLCKSELR_DIVM2_Pos);
+  PeriphClkInit->PLL2.PLL2N = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_N2) >> RCC_PLL2DIVR_N2_Pos)+ 1U;
+  PeriphClkInit->PLL2.PLL2R = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> RCC_PLL2DIVR_R2_Pos)+ 1U;
+  PeriphClkInit->PLL2.PLL2P = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> RCC_PLL2DIVR_P2_Pos)+ 1U;
+  PeriphClkInit->PLL2.PLL2Q = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> RCC_PLL2DIVR_Q2_Pos)+ 1U;
+  PeriphClkInit->PLL2.PLL2RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2RGE) >> RCC_PLLCFGR_PLL2RGE_Pos);
+  PeriphClkInit->PLL2.PLL2VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2VCOSEL) >> RCC_PLLCFGR_PLL2VCOSEL_Pos);
+
+  /* Get the USART1 configuration --------------------------------------------*/
+  PeriphClkInit->Usart16ClockSelection      = __HAL_RCC_GET_USART16_SOURCE();
+  /* Get the USART2/3/4/5/7/8 clock source -----------------------------------*/
+  PeriphClkInit->Usart234578ClockSelection  = __HAL_RCC_GET_USART234578_SOURCE();
+  /* Get the LPUART1 clock source --------------------------------------------*/
+  PeriphClkInit->Lpuart1ClockSelection      = __HAL_RCC_GET_LPUART1_SOURCE();
+  /* Get the I2C1/2/3 clock source -------------------------------------------*/
+  PeriphClkInit->I2c123ClockSelection       = __HAL_RCC_GET_I2C1_SOURCE();
+  /* Get the LPTIM1 clock source ---------------------------------------------*/
+  PeriphClkInit->Lptim1ClockSelection       = __HAL_RCC_GET_LPTIM1_SOURCE();
+  /* Get the LPTIM2 clock source ---------------------------------------------*/
+  PeriphClkInit->Lptim2ClockSelection       = __HAL_RCC_GET_LPTIM2_SOURCE();
+  /* Get the LPTIM3/4/5 clock source -----------------------------------------*/
+  PeriphClkInit->Lptim345ClockSelection     = __HAL_RCC_GET_LPTIM345_SOURCE();
+  /* Get the SAI1 clock source -----------------------------------------------*/
+  PeriphClkInit->Sai1ClockSelection         = __HAL_RCC_GET_SAI1_SOURCE();
+#if defined(SAI3)
+  /* Get the SAI2/3 clock source ---------------------------------------------*/
+  PeriphClkInit->Sai23ClockSelection        = __HAL_RCC_GET_SAI23_SOURCE();
+#endif  /*SAI3*/
+#if defined(RCC_CDCCIP1R_SAI2ASEL_0)
+  /* Get the SAI2A clock source ---------------------------------------------*/
+  PeriphClkInit->Sai2AClockSelection        = __HAL_RCC_GET_SAI2A_SOURCE();
+#endif  /*SAI2A*/
+#if defined(RCC_CDCCIP1R_SAI2BSEL_0)
+  /* Get the SAI2B clock source ---------------------------------------------*/
+  PeriphClkInit->Sai2BClockSelection        = __HAL_RCC_GET_SAI2B_SOURCE();
+#endif  /*SAI2B*/
+#if defined(SAI4)
+  /* Get the SAI4A clock source ----------------------------------------------*/
+  PeriphClkInit->Sai4AClockSelection        = __HAL_RCC_GET_SAI4A_SOURCE();
+  /* Get the SAI4B clock source ----------------------------------------------*/
+  PeriphClkInit->Sai4BClockSelection        = __HAL_RCC_GET_SAI4B_SOURCE();
+#endif  /*SAI4*/
+  /* Get the RTC clock source ------------------------------------------------*/
+  PeriphClkInit->RTCClockSelection          = __HAL_RCC_GET_RTC_SOURCE();
+  /* Get the USB clock source ------------------------------------------------*/
+  PeriphClkInit->UsbClockSelection          = __HAL_RCC_GET_USB_SOURCE();
+  /* Get the SDMMC clock source ----------------------------------------------*/
+  PeriphClkInit->SdmmcClockSelection        = __HAL_RCC_GET_SDMMC_SOURCE();
+  /* Get the RNG clock source ------------------------------------------------*/
+  PeriphClkInit->RngClockSelection          = __HAL_RCC_GET_RNG_SOURCE();
+#if defined(HRTIM1)
+  /* Get the HRTIM1 clock source ---------------------------------------------*/
+  PeriphClkInit->Hrtim1ClockSelection       = __HAL_RCC_GET_HRTIM1_SOURCE();
+#endif /* HRTIM1 */
+  /* Get the ADC clock source ------------------------------------------------*/
+  PeriphClkInit->AdcClockSelection          = __HAL_RCC_GET_ADC_SOURCE();
+  /* Get the SWPMI1 clock source ---------------------------------------------*/
+  PeriphClkInit->Swpmi1ClockSelection       = __HAL_RCC_GET_SWPMI1_SOURCE();
+  /* Get the DFSDM1 clock source ---------------------------------------------*/
+  PeriphClkInit->Dfsdm1ClockSelection       = __HAL_RCC_GET_DFSDM1_SOURCE();
+#if defined(DFSDM2_BASE)
+  /* Get the DFSDM2 clock source ---------------------------------------------*/
+  PeriphClkInit->Dfsdm2ClockSelection       = __HAL_RCC_GET_DFSDM2_SOURCE();
+#endif /* DFSDM2 */
+  /* Get the SPDIFRX clock source --------------------------------------------*/
+  PeriphClkInit->SpdifrxClockSelection      = __HAL_RCC_GET_SPDIFRX_SOURCE();
+  /* Get the SPI1/2/3 clock source -------------------------------------------*/
+  PeriphClkInit->Spi123ClockSelection       = __HAL_RCC_GET_SPI123_SOURCE();
+  /* Get the SPI4/5 clock source ---------------------------------------------*/
+  PeriphClkInit->Spi45ClockSelection        = __HAL_RCC_GET_SPI45_SOURCE();
+  /* Get the SPI6 clock source -----------------------------------------------*/
+  PeriphClkInit->Spi6ClockSelection         = __HAL_RCC_GET_SPI6_SOURCE();
+  /* Get the FDCAN clock source ----------------------------------------------*/
+  PeriphClkInit->FdcanClockSelection        = __HAL_RCC_GET_FDCAN_SOURCE();
+  /* Get the CEC clock source ------------------------------------------------*/
+  PeriphClkInit->CecClockSelection          = __HAL_RCC_GET_CEC_SOURCE();
+  /* Get the FMC clock source ------------------------------------------------*/
+  PeriphClkInit->FmcClockSelection          = __HAL_RCC_GET_FMC_SOURCE();
+#if defined(QUADSPI)
+  /* Get the QSPI clock source -----------------------------------------------*/
+  PeriphClkInit->QspiClockSelection         = __HAL_RCC_GET_QSPI_SOURCE();
+#endif /* QUADSPI */
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+  /* Get the OSPI clock source -----------------------------------------------*/
+  PeriphClkInit->OspiClockSelection         = __HAL_RCC_GET_OSPI_SOURCE();
+#endif /* OCTOSPI1 || OCTOSPI2 */
+
+#if defined(DSI)
+  /* Get the DSI clock source ------------------------------------------------*/
+  PeriphClkInit->DsiClockSelection          = __HAL_RCC_GET_DSI_SOURCE();
+#endif /*DSI*/
+
+  /* Get the CKPER clock source ----------------------------------------------*/
+  PeriphClkInit->CkperClockSelection        = __HAL_RCC_GET_CLKP_SOURCE();
+
+  /* Get the TIM Prescaler configuration -------------------------------------*/
+  if ((RCC->CFGR & RCC_CFGR_TIMPRE) == 0U)
+  {
+    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
+  }
+  else
+  {
+    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
+  }
+}
+
+/**
+  * @brief  Return the peripheral clock frequency for a given peripheral(SAI..)
+  * @note   Return 0 if peripheral clock identifier not managed by this API
+  * @param  PeriphClk: Peripheral clock identifier
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PERIPHCLK_SAI1  : SAI1 peripheral clock
+  *            @arg RCC_PERIPHCLK_SAI23 : SAI2/3  peripheral clock (*)
+  *            @arg RCC_PERIPHCLK_SAI2A : SAI2A peripheral clock (*)
+  *            @arg RCC_PERIPHCLK_SAI2B : SAI2B peripheral clock (*)
+  *            @arg RCC_PERIPHCLK_SAI4A : SAI4A peripheral clock (*)
+  *            @arg RCC_PERIPHCLK_SAI4B : SAI4B peripheral clock (*)
+  *            @arg RCC_PERIPHCLK_SPI123: SPI1/2/3 peripheral clock
+  *            @arg RCC_PERIPHCLK_ADC   : ADC peripheral clock
+  *            @arg RCC_PERIPHCLK_SDMMC : SDMMC peripheral clock
+  *            @arg RCC_PERIPHCLK_SPI6  : SPI6 peripheral clock
+  * @retval Frequency in KHz
+  *
+  *  (*) : Available on some STM32H7 lines only.
+  */
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
+{
+  PLL1_ClocksTypeDef pll1_clocks;
+  PLL2_ClocksTypeDef pll2_clocks;
+  PLL3_ClocksTypeDef pll3_clocks;
+
+  /* This variable is used to store the SAI clock frequency (value in Hz) */
+  uint32_t frequency;
+  /* This variable is used to store the SAI and CKP clock source */
+  uint32_t saiclocksource;
+  uint32_t ckpclocksource;
+  uint32_t srcclk;
+
+  if (PeriphClk == RCC_PERIPHCLK_SAI1)
+    {
+
+      saiclocksource= __HAL_RCC_GET_SAI1_SOURCE();
+
+      switch (saiclocksource)
+      {
+      case RCC_SAI1CLKSOURCE_PLL: /* PLL1 is the clock source for SAI1 */
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+          break;
+        }
+      case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI1 */
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_P_Frequency;
+          break;
+        }
+
+      case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI1 */
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+          frequency = pll3_clocks.PLL3_P_Frequency;
+          break;
+        }
+
+      case RCC_SAI1CLKSOURCE_CLKP: /* CKPER is the clock source for SAI1*/
+        {
+
+          ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
+
+          if(ckpclocksource== RCC_CLKPSOURCE_HSI)
+          {
+            /* In Case the CKPER Source is HSI */
+            frequency = HSI_VALUE;
+          }
+
+          else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
+          {
+            /* In Case the CKPER Source is CSI */
+            frequency = CSI_VALUE;
+          }
+
+          else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
+          {
+            /* In Case the CKPER Source is HSE */
+            frequency = HSE_VALUE;
+          }
+
+          else
+          {
+            /* In Case the CKPER is disabled*/
+            frequency = 0;
+          }
+
+          break;
+        }
+
+      case (RCC_SAI1CLKSOURCE_PIN): /* External clock is the clock source for SAI1 */
+        {
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+      default :
+        {
+          frequency = 0;
+          break;
+        }
+      }
+    }
+
+#if defined(SAI3)
+  else if (PeriphClk == RCC_PERIPHCLK_SAI23)
+    {
+
+      saiclocksource= __HAL_RCC_GET_SAI23_SOURCE();
+
+      switch (saiclocksource)
+      {
+      case 0: /* PLL1 is the clock source for SAI2/3 */
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+          break;
+        }
+      case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI2/3 */
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_P_Frequency;
+          break;
+        }
+
+      case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI2/3 */
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+          frequency = pll3_clocks.PLL3_P_Frequency;
+          break;
+        }
+
+      case RCC_SAI23CLKSOURCE_CLKP: /* CKPER is the clock source for SAI2/3 */
+        {
+
+          ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
+
+          if(ckpclocksource== RCC_CLKPSOURCE_HSI)
+          {
+            /* In Case the CKPER Source is HSI */
+            frequency = HSI_VALUE;
+          }
+
+          else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
+          {
+            /* In Case the CKPER Source is CSI */
+            frequency = CSI_VALUE;
+          }
+
+          else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
+          {
+            /* In Case the CKPER Source is HSE */
+            frequency = HSE_VALUE;
+          }
+
+          else
+          {
+            /* In Case the CKPER is disabled*/
+            frequency = 0;
+          }
+
+          break;
+        }
+
+      case (RCC_SAI23CLKSOURCE_PIN): /* External clock is the clock source for SAI2/3 */
+        {
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+      default :
+        {
+          frequency = 0;
+          break;
+        }
+      }
+    }
+#endif /* SAI3 */
+
+#if  defined(RCC_CDCCIP1R_SAI2ASEL)
+
+    else if (PeriphClk == RCC_PERIPHCLK_SAI2A)
+    {
+      saiclocksource= __HAL_RCC_GET_SAI2A_SOURCE();
+
+      switch (saiclocksource)
+      {
+      case 0: /* PLL1 is the clock source for SAI2A */
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+          break;
+        }
+      case RCC_SAI2ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI2A */
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_P_Frequency;
+          break;
+        }
+
+      case RCC_SAI2ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI2A  */
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+          frequency = pll3_clocks.PLL3_P_Frequency;
+          break;
+        }
+
+      case RCC_SAI2ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI2A  */
+        {
+
+          ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
+
+          if(ckpclocksource== RCC_CLKPSOURCE_HSI)
+          {
+            /* In Case the CKPER Source is HSI */
+            frequency = HSI_VALUE;
+          }
+
+          else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
+          {
+            /* In Case the CKPER Source is CSI */
+            frequency = CSI_VALUE;
+          }
+
+          else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
+          {
+            /* In Case the CKPER Source is HSE */
+            frequency = HSE_VALUE;
+          }
+
+          else
+          {
+            /* In Case the CKPER is disabled*/
+            frequency = 0;
+          }
+
+          break;
+        }
+
+      case (RCC_SAI2ACLKSOURCE_PIN): /* External clock is the clock source for SAI2A */
+        {
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+
+      default :
+        {
+          frequency = 0;
+          break;
+        }
+      }
+
+    }
+#endif
+
+#if  defined(RCC_CDCCIP1R_SAI2BSEL_0)
+  else if (PeriphClk == RCC_PERIPHCLK_SAI2B)
+    {
+
+      saiclocksource= __HAL_RCC_GET_SAI2B_SOURCE();
+
+      switch (saiclocksource)
+      {
+      case 0: /* PLL1 is the clock source for SAI2B */
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+          break;
+        }
+      case RCC_SAI2BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI2B */
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_P_Frequency;
+          break;
+        }
+
+      case RCC_SAI2BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI2B */
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+          frequency = pll3_clocks.PLL3_P_Frequency;
+          break;
+        }
+
+      case RCC_SAI2BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI2B*/
+        {
+
+          ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
+
+          if(ckpclocksource== RCC_CLKPSOURCE_HSI)
+          {
+            /* In Case the CKPER Source is HSI */
+            frequency = HSI_VALUE;
+          }
+
+          else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
+          {
+            /* In Case the CKPER Source is CSI */
+            frequency = CSI_VALUE;
+          }
+
+          else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
+          {
+            /* In Case the CKPER Source is HSE */
+            frequency = HSE_VALUE;
+          }
+
+          else
+          {
+            /* In Case the CKPER is disabled*/
+            frequency = 0;
+          }
+          break;
+        }
+
+      case (RCC_SAI2BCLKSOURCE_PIN): /* External clock is the clock source for SAI2B */
+        {
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+
+      default :
+        {
+          frequency = 0;
+          break;
+        }
+      }
+    }
+#endif
+
+#if defined(SAI4)
+  else if (PeriphClk == RCC_PERIPHCLK_SAI4A)
+    {
+
+      saiclocksource= __HAL_RCC_GET_SAI4A_SOURCE();
+
+      switch (saiclocksource)
+      {
+      case 0: /* PLL1 is the clock source for SAI4A */
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+          break;
+        }
+      case RCC_D3CCIPR_SAI4ASEL_0: /* PLLI2 is the clock source for SAI4A */
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_P_Frequency;
+          break;
+        }
+
+      case RCC_D3CCIPR_SAI4ASEL_1: /* PLLI3 is the clock source for SAI4A */
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+          frequency = pll3_clocks.PLL3_P_Frequency;
+          break;
+        }
+
+      case RCC_D3CCIPR_SAI4ASEL_2: /* CKPER is the clock source for SAI4A*/
+        {
+
+          ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
+
+          if(ckpclocksource== RCC_CLKPSOURCE_HSI)
+          {
+            /* In Case the CKPER Source is HSI */
+            frequency = HSI_VALUE;
+          }
+
+          else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
+          {
+            /* In Case the CKPER Source is CSI */
+            frequency = CSI_VALUE;
+          }
+
+          else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
+          {
+            /* In Case the CKPER Source is HSE */
+            frequency = HSE_VALUE;
+          }
+
+          else
+          {
+            /* In Case the CKPER is disabled*/
+            frequency = 0;
+          }
+
+          break;
+        }
+
+      case (RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1 ): /* External clock is the clock source for SAI4A */
+        {
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+
+      default :
+        {
+          frequency = 0;
+          break;
+        }
+      }
+    }
+
+  else if (PeriphClk == RCC_PERIPHCLK_SAI4B)
+    {
+
+      saiclocksource= __HAL_RCC_GET_SAI4B_SOURCE();
+
+      switch (saiclocksource)
+      {
+      case 0: /* PLL1 is the clock source for SAI4B */
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+          break;
+        }
+      case RCC_D3CCIPR_SAI4BSEL_0: /* PLLI2 is the clock source for SAI4B */
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_P_Frequency;
+          break;
+        }
+
+      case RCC_D3CCIPR_SAI4BSEL_1: /* PLLI3 is the clock source for SAI4B */
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+          frequency = pll3_clocks.PLL3_P_Frequency;
+          break;
+        }
+
+      case RCC_D3CCIPR_SAI4BSEL_2: /* CKPER is the clock source for SAI4B*/
+        {
+
+          ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
+
+          if(ckpclocksource== RCC_CLKPSOURCE_HSI)
+          {
+            /* In Case the CKPER Source is HSI */
+            frequency = HSI_VALUE;
+          }
+
+          else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
+          {
+            /* In Case the CKPER Source is CSI */
+            frequency = CSI_VALUE;
+          }
+
+          else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
+          {
+            /* In Case the CKPER Source is HSE */
+            frequency = HSE_VALUE;
+          }
+
+          else
+          {
+            /* In Case the CKPER is disabled*/
+            frequency = 0;
+          }
+
+          break;
+        }
+
+      case (RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1 ): /* External clock is the clock source for SAI4B */
+        {
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+
+      default :
+        {
+          frequency = 0;
+          break;
+        }
+      }
+    }
+#endif /*SAI4*/
+  else if (PeriphClk == RCC_PERIPHCLK_SPI123)
+    {
+      /* Get SPI1/2/3 clock source */
+      srcclk= __HAL_RCC_GET_SPI123_SOURCE();
+
+      switch (srcclk)
+      {
+      case RCC_SPI123CLKSOURCE_PLL: /* PLL1 is the clock source for I2S */
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+          break;
+        }
+      case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is the clock source for I2S */
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_P_Frequency;
+          break;
+        }
+
+      case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is the clock source for I2S */
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+          frequency = pll3_clocks.PLL3_P_Frequency;
+          break;
+        }
+
+      case RCC_SPI123CLKSOURCE_CLKP: /* CKPER is the clock source for I2S */
+        {
+
+          ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
+
+          if(ckpclocksource== RCC_CLKPSOURCE_HSI)
+          {
+            /* In Case the CKPER Source is HSI */
+            frequency = HSI_VALUE;
+          }
+
+          else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
+          {
+            /* In Case the CKPER Source is CSI */
+            frequency = CSI_VALUE;
+          }
+
+          else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
+          {
+            /* In Case the CKPER Source is HSE */
+            frequency = HSE_VALUE;
+          }
+
+          else
+          {
+            /* In Case the CKPER is disabled*/
+            frequency = 0;
+          }
+
+          break;
+        }
+
+      case (RCC_SPI123CLKSOURCE_PIN): /* External clock is the clock source for I2S */
+        {
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+      default :
+        {
+          frequency = 0;
+          break;
+        }
+      }
+    }
+  else if (PeriphClk == RCC_PERIPHCLK_ADC)
+    {
+      /* Get ADC clock source */
+      srcclk= __HAL_RCC_GET_ADC_SOURCE();
+
+      switch (srcclk)
+      {
+      case RCC_ADCCLKSOURCE_PLL2:
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_P_Frequency;
+          break;
+        }
+      case RCC_ADCCLKSOURCE_PLL3:
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+          frequency = pll3_clocks.PLL3_R_Frequency;
+          break;
+        }
+
+      case RCC_ADCCLKSOURCE_CLKP:
+        {
+
+          ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
+
+          if(ckpclocksource== RCC_CLKPSOURCE_HSI)
+          {
+            /* In Case the CKPER Source is HSI */
+            frequency = HSI_VALUE;
+          }
+
+          else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
+          {
+            /* In Case the CKPER Source is CSI */
+            frequency = CSI_VALUE;
+          }
+
+          else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
+          {
+            /* In Case the CKPER Source is HSE */
+            frequency = HSE_VALUE;
+          }
+
+          else
+          {
+            /* In Case the CKPER is disabled*/
+            frequency = 0;
+          }
+
+          break;
+        }
+
+      default :
+        {
+          frequency = 0;
+          break;
+        }
+      }
+    }
+  else if (PeriphClk == RCC_PERIPHCLK_SDMMC)
+    {
+      /* Get SDMMC clock source */
+      srcclk= __HAL_RCC_GET_SDMMC_SOURCE();
+
+      switch (srcclk)
+      {
+      case RCC_SDMMCCLKSOURCE_PLL: /* PLL1 is the clock source for SDMMC */
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+          break;
+        }
+      case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is the clock source for SDMMC */
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_R_Frequency;
+          break;
+        }
+
+      default :
+        {
+          frequency = 0;
+          break;
+        }
+      }
+    }
+  else if (PeriphClk == RCC_PERIPHCLK_SPI6)
+    {
+      /* Get SPI6 clock source */
+      srcclk= __HAL_RCC_GET_SPI6_SOURCE();
+
+      switch (srcclk)
+      {
+      case RCC_SPI6CLKSOURCE_D3PCLK1: /* D3PCLK1 (PCLK4) is the clock source for SPI6 */
+        {
+          frequency = HAL_RCCEx_GetD3PCLK1Freq();
+          break;
+        }
+      case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI6 */
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_Q_Frequency;
+          break;
+        }
+      case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI6 */
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+          frequency = pll3_clocks.PLL3_Q_Frequency;
+          break;
+        }
+      case RCC_SPI6CLKSOURCE_HSI: /* HSI is the clock source for SPI6 */
+        {
+          frequency = HSI_VALUE;
+          break;
+        }
+      case RCC_SPI6CLKSOURCE_CSI: /* CSI is the clock source for SPI6 */
+        {
+          frequency = CSI_VALUE;
+          break;
+        }
+      case RCC_SPI6CLKSOURCE_HSE: /* HSE is the clock source for SPI6 */
+        {
+          frequency = HSE_VALUE;
+          break;
+        }
+#if defined(RCC_SPI6CLKSOURCE_PIN)
+      case RCC_SPI6CLKSOURCE_PIN: /* External clock is the clock source for SPI6 */
+        {
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+#endif /* RCC_SPI6CLKSOURCE_PIN */
+      default :
+        {
+          frequency = 0;
+          break;
+        }
+      }
+    }
+  else
+    {
+      frequency = 0;
+    }
+
+  return frequency;
+}
+
+
+/**
+  * @brief  Returns the D1PCLK1 frequency
+  * @note   Each time D1PCLK1 changes, this function must be called to update the
+  *         right D1PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
+  * @retval D1PCLK1 frequency
+  */
+uint32_t HAL_RCCEx_GetD1PCLK1Freq(void)
+{
+#if defined(RCC_D1CFGR_D1PPRE)
+  /* Get HCLK source and Compute D1PCLK1 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1PPRE)>> RCC_D1CFGR_D1PPRE_Pos] & 0x1FU));
+#else
+/* Get HCLK source and Compute D1PCLK1 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE)>> RCC_CDCFGR1_CDPPRE_Pos] & 0x1FU));
+#endif
+}
+
+/**
+  * @brief  Returns the D3PCLK1 frequency
+  * @note   Each time D3PCLK1 changes, this function must be called to update the
+  *         right D3PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
+  * @retval D3PCLK1 frequency
+  */
+uint32_t HAL_RCCEx_GetD3PCLK1Freq(void)
+{
+#if defined(RCC_D3CFGR_D3PPRE)
+  /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE)>> RCC_D3CFGR_D3PPRE_Pos] & 0x1FU));
+#else
+  /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE)>> RCC_SRDCFGR_SRDPPRE_Pos] & 0x1FU));
+#endif
+}
+/**
+* @brief  Returns the PLL2 clock frequencies :PLL2_P_Frequency,PLL2_R_Frequency and PLL2_Q_Frequency
+  * @note   The PLL2 clock frequencies computed by this function is not the real
+  *         frequency in the chip. It is calculated based on the predefined
+  *         constant and the selected clock source:
+  * @note     The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors.
+  * @note   This function can be used by the user application to compute the
+  *         baud-rate for the communication peripherals or configure other parameters.
+  *
+  * @note   Each time PLL2CLK changes, this function must be called to update the
+  *         right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect.
+  * @param  PLL2_Clocks structure.
+  * @retval None
+  */
+void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef* PLL2_Clocks)
+{
+  uint32_t  pllsource, pll2m,  pll2fracen, hsivalue;
+  float_t fracn2, pll2vco;
+
+  /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL2M) * PLL2N
+     PLL2xCLK = PLL2_VCO / PLL2x
+  */
+  pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+  pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2)>> 12);
+  pll2fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) >> RCC_PLLCFGR_PLL2FRACEN_Pos;
+  fracn2 =(float_t)(uint32_t)(pll2fracen* ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2)>> 3));
+
+  if (pll2m != 0U)
+  {
+    switch (pllsource)
+    {
+
+    case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
+
+      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+      {
+        hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
+        pll2vco = ( (float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );
+      }
+      else
+      {
+        pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );
+      }
+      break;
+
+    case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
+      pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );
+      break;
+
+    case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
+      pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );
+      break;
+
+    default:
+      pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );
+      break;
+    }
+    PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >>9)  + (float_t)1 )) ;
+    PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >>16) + (float_t)1 )) ;
+    PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >>24) + (float_t)1 )) ;
+  }
+  else
+  {
+    PLL2_Clocks->PLL2_P_Frequency = 0U;
+    PLL2_Clocks->PLL2_Q_Frequency = 0U;
+    PLL2_Clocks->PLL2_R_Frequency = 0U;
+  }
+}
+
+/**
+* @brief  Returns the PLL3 clock frequencies :PLL3_P_Frequency,PLL3_R_Frequency and PLL3_Q_Frequency
+  * @note   The PLL3 clock frequencies computed by this function is not the real
+  *         frequency in the chip. It is calculated based on the predefined
+  *         constant and the selected clock source:
+  * @note     The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors.
+  * @note   This function can be used by the user application to compute the
+  *         baud-rate for the communication peripherals or configure other parameters.
+  *
+  * @note   Each time PLL3CLK changes, this function must be called to update the
+  *         right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect.
+  * @param  PLL3_Clocks structure.
+  * @retval None
+  */
+void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef* PLL3_Clocks)
+{
+  uint32_t pllsource, pll3m, pll3fracen, hsivalue;
+  float_t fracn3, pll3vco;
+
+  /* PLL3_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL3M) * PLL3N
+     PLL3xCLK = PLL3_VCO / PLLxR
+  */
+  pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+  pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3)>> 20)  ;
+  pll3fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) >> RCC_PLLCFGR_PLL3FRACEN_Pos;
+  fracn3 = (float_t)(uint32_t)(pll3fracen* ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3)>> 3));
+
+  if (pll3m != 0U)
+  {
+    switch (pllsource)
+    {
+    case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
+
+      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+      {
+        hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
+        pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );
+      }
+      else
+      {
+        pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );
+      }
+      break;
+    case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
+      pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );
+      break;
+
+    case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
+      pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );
+      break;
+
+    default:
+      pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );
+      break;
+    }
+    PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >>9)  + (float_t)1 )) ;
+    PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >>16) + (float_t)1 )) ;
+    PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >>24) + (float_t)1 )) ;
+  }
+  else
+  {
+    PLL3_Clocks->PLL3_P_Frequency = 0U;
+    PLL3_Clocks->PLL3_Q_Frequency = 0U;
+    PLL3_Clocks->PLL3_R_Frequency = 0U;
+  }
+
+}
+
+/**
+* @brief  Returns the PLL1 clock frequencies :PLL1_P_Frequency,PLL1_R_Frequency and PLL1_Q_Frequency
+  * @note   The PLL1 clock frequencies computed by this function is not the real
+  *         frequency in the chip. It is calculated based on the predefined
+  *         constant and the selected clock source:
+  * @note     The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors.
+  * @note   This function can be used by the user application to compute the
+  *         baud-rate for the communication peripherals or configure other parameters.
+  *
+  * @note   Each time PLL1CLK changes, this function must be called to update the
+  *         right PLL1CLK value. Otherwise, any configuration based on this function will be incorrect.
+  * @param  PLL1_Clocks structure.
+  * @retval None
+  */
+void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef* PLL1_Clocks)
+{
+  uint32_t pllsource, pll1m, pll1fracen, hsivalue;
+  float_t fracn1, pll1vco;
+
+  pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+  pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4);
+  pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN;
+  fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
+
+  if (pll1m != 0U)
+  {
+    switch (pllsource)
+    {
+
+    case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
+
+      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+      {
+        hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
+        pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+      }
+      else
+      {
+        pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+      }
+      break;
+    case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
+      pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+      break;
+
+    case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
+      pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+      break;
+
+    default:
+      pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+      break;
+    }
+
+    PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9)  + (float_t)1 )) ;
+    PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >>16) + (float_t)1 )) ;
+    PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >>24) + (float_t)1 )) ;
+  }
+  else
+  {
+    PLL1_Clocks->PLL1_P_Frequency = 0U;
+    PLL1_Clocks->PLL1_Q_Frequency = 0U;
+    PLL1_Clocks->PLL1_R_Frequency = 0U;
+  }
+
+}
+
+/**
+  * @brief  Returns the main System frequency
+  * @note   Each time System clock changes, this function must be called to update the
+  *         right core clock value. Otherwise, any configuration based on this function will be incorrect.
+  * @note   The SystemCoreClock CMSIS variable is used to store System current Core Clock Frequency
+  *         and updated within this function
+  * @retval HCLK frequency
+  */
+uint32_t HAL_RCCEx_GetD1SysClockFreq(void)
+{
+uint32_t common_system_clock;
+
+#if defined(RCC_D1CFGR_D1CPRE)
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
+#else
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU);
+#endif
+
+  /* Update the SystemD2Clock global variable */
+#if defined(RCC_D1CFGR_HPRE)
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+#else
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+#endif
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  SystemCoreClock = SystemD2Clock;
+#else
+  SystemCoreClock = common_system_clock;
+#endif /* DUAL_CORE && CORE_CM4 */
+
+  return common_system_clock;
+}
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_Exported_Functions_Group2 Extended System Control functions
+ *  @brief  Extended Peripheral Control functions
+  * @{
+  */
+/**
+  * @brief  Enables the LSE Clock Security System.
+  * @note   Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled
+  *         with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC
+  *         clock with HAL_RCCEx_PeriphCLKConfig().
+  * @retval None
+  */
+void HAL_RCCEx_EnableLSECSS(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
+}
+
+/**
+  * @brief  Disables the LSE Clock Security System.
+  * @note   LSE Clock Security System can only be disabled after a LSE failure detection.
+  * @retval None
+  */
+void HAL_RCCEx_DisableLSECSS(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
+  /* Disable LSE CSS IT if any */
+  __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS);
+}
+
+/**
+  * @brief  Enable the LSE Clock Security System Interrupt & corresponding EXTI line.
+  * @note   LSE Clock Security System Interrupt is mapped on EXTI line 18
+  * @retval None
+  */
+void HAL_RCCEx_EnableLSECSS_IT(void)
+{
+  /* Enable LSE CSS */
+  SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
+
+  /* Enable LSE CSS IT */
+  __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS);
+
+  /* Enable IT on EXTI Line 18 */
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  __HAL_RCC_C2_LSECSS_EXTI_ENABLE_IT();
+#else
+  __HAL_RCC_LSECSS_EXTI_ENABLE_IT();
+#endif /* DUAL_CORE && CORE_CM4 */
+  __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();
+}
+
+/**
+  * @brief  Configure the oscillator clock source for wakeup from Stop and CSS backup clock
+  * @param  WakeUpClk: Wakeup clock
+  *         This parameter can be one of the following values:
+  *            @arg RCC_STOP_WAKEUPCLOCK_CSI: CSI oscillator selection
+  *            @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI oscillator selection
+  * @note   This function shall not be called after the Clock Security System on HSE has been
+  *         enabled.
+  * @retval None
+  */
+void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)
+{
+  assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk));
+
+  __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk);
+}
+
+/**
+  * @brief  Configure the oscillator Kernel clock source for wakeup from Stop
+  * @param  WakeUpClk: Kernel Wakeup clock
+  *         This parameter can be one of the following values:
+  *            @arg RCC_STOP_KERWAKEUPCLOCK_CSI: CSI oscillator selection
+  *            @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI oscillator selection
+  * @retval None
+  */
+void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk)
+{
+  assert_param(IS_RCC_STOP_KERWAKEUPCLOCK(WakeUpClk));
+
+  __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(WakeUpClk);
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Enable COREx boot independently of CMx_B option byte value
+  * @param  RCC_BootCx: Boot Core to be enabled
+  *         This parameter can be one of the following values:
+  *            @arg RCC_BOOT_C1: CM7 core selection
+  *            @arg RCC_BOOT_C2: CM4 core selection
+  * @note   This bit can be set by software but is cleared by hardware after a system reset or STANDBY
+  *
+  * @retval None
+  */
+void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx)
+{
+  assert_param(IS_RCC_BOOT_CORE(RCC_BootCx));
+  SET_BIT(RCC->GCR, RCC_BootCx) ;
+}
+
+#endif /*DUAL_CORE*/
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Configure WWDGx to generate a system reset not only CPUx reset(default) when a time-out occurs
+  * @param  RCC_WWDGx: WWDGx to be configured
+  *         This parameter can be one of the following values:
+  *            @arg RCC_WWDG1: WWDG1 generates system reset
+  *            @arg RCC_WWDG2: WWDG2 generates system reset
+  * @note   This bit can be set by software but is cleared by hardware during a system reset
+  *
+  * @retval None
+  */
+void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx)
+{
+  assert_param(IS_RCC_SCOPE_WWDG(RCC_WWDGx));
+  SET_BIT(RCC->GCR, RCC_WWDGx) ;
+}
+
+#else
+#if defined(RCC_GCR_WW1RSC)
+/**
+  * @brief  Configure WWDG1 to generate a system reset not only CPU reset(default) when a time-out occurs
+  * @param  RCC_WWDGx: WWDGx to be configured
+  *         This parameter can be one of the following values:
+  *            @arg RCC_WWDG1: WWDG1 generates system reset
+  * @note   This bit can be set by software but is cleared by hardware during a system reset
+  *
+  * @retval None
+  */
+void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx)
+{
+  assert_param(IS_RCC_SCOPE_WWDG(RCC_WWDGx));
+  SET_BIT(RCC->GCR, RCC_WWDGx) ;
+}
+#endif
+#endif /*DUAL_CORE*/
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions
+ *  @brief  Extended Clock Recovery System Control functions
+ *
+@verbatim
+ ===============================================================================
+                ##### Extended Clock Recovery System Control functions  #####
+ ===============================================================================
+    [..]
+      For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows:
+
+      (#) In System clock config, HSI48 needs to be enabled
+
+      (#) Enable CRS clock in IP MSP init which will use CRS functions
+
+      (#) Call CRS functions as follows:
+          (##) Prepare synchronization configuration necessary for HSI48 calibration
+              (+++) Default values can be set for frequency Error Measurement (reload and error limit)
+                        and also HSI48 oscillator smooth trimming.
+              (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
+                        directly reload value with target and synchronization frequencies values
+          (##) Call function HAL_RCCEx_CRSConfig which
+              (+++) Resets CRS registers to their default values.
+              (+++) Configures CRS registers with synchronization configuration
+              (+++) Enables automatic calibration and frequency error counter feature
+           Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the
+           periodic USB SOF will not be generated by the host. No SYNC signal will therefore be
+           provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock
+           precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs
+           should be used as SYNC signal.
+
+          (##) A polling function is provided to wait for complete synchronization
+              (+++) Call function HAL_RCCEx_CRSWaitSynchronization()
+              (+++) According to CRS status, user can decide to adjust again the calibration or continue
+                        application if synchronization is OK
+
+      (#) User can retrieve information related to synchronization in calling function
+            HAL_RCCEx_CRSGetSynchronizationInfo()
+
+      (#) Regarding synchronization status and synchronization information, user can try a new calibration
+           in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
+           Note: When the SYNC event is detected during the down-counting phase (before reaching the zero value),
+           it means that the actual frequency is lower than the target (and so, that the TRIM value should be
+           incremented), while when it is detected during the up-counting phase it means that the actual frequency
+           is higher (and that the TRIM value should be decremented).
+
+      (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go
+          through CRS Handler (CRS_IRQn/CRS_IRQHandler)
+              (++) Call function HAL_RCCEx_CRSConfig()
+              (++) Enable CRS_IRQn (thanks to NVIC functions)
+              (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT)
+              (++) Implement CRS status management in the following user callbacks called from
+                   HAL_RCCEx_CRS_IRQHandler():
+                   (+++) HAL_RCCEx_CRS_SyncOkCallback()
+                   (+++) HAL_RCCEx_CRS_SyncWarnCallback()
+                   (+++) HAL_RCCEx_CRS_ExpectedSyncCallback()
+                   (+++) HAL_RCCEx_CRS_ErrorCallback()
+
+      (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate().
+          This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler)
+
+@endverbatim
+ * @{
+ */
+
+/**
+  * @brief  Start automatic synchronization for polling mode
+  * @param  pInit Pointer on RCC_CRSInitTypeDef structure
+  * @retval None
+  */
+void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
+{
+  uint32_t value;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));
+  assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));
+  assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));
+  assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));
+  assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));
+  assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));
+
+  /* CONFIGURATION */
+
+  /* Before configuration, reset CRS registers to their default values*/
+  __HAL_RCC_CRS_FORCE_RESET();
+  __HAL_RCC_CRS_RELEASE_RESET();
+
+  /* Set the SYNCDIV[2:0] bits according to Pre-scaler value */
+  /* Set the SYNCSRC[1:0] bits according to Source value */
+  /* Set the SYNCSPOL bit according to Polarity value */
+  if ((HAL_GetREVID() <= REV_ID_Y) && (pInit->Source == RCC_CRS_SYNC_SOURCE_USB2))
+  {
+    /* Use Rev.Y value of USB2 */
+    value = (pInit->Prescaler | RCC_CRS_SYNC_SOURCE_PIN | pInit->Polarity);
+  }
+  else
+  {
+    value = (pInit->Prescaler | pInit->Source | pInit->Polarity);
+  }
+  /* Set the RELOAD[15:0] bits according to ReloadValue value */
+  value |= pInit->ReloadValue;
+  /* Set the FELIM[7:0] bits according to ErrorLimitValue value */
+  value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos);
+  WRITE_REG(CRS->CFGR, value);
+
+  /* Adjust HSI48 oscillator smooth trimming */
+  /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */
+  MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos));
+
+  /* START AUTOMATIC SYNCHRONIZATION*/
+
+  /* Enable Automatic trimming & Frequency error counter */
+  SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN);
+}
+
+/**
+  * @brief  Generate the software synchronization event
+  * @retval None
+  */
+void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_SWSYNC);
+}
+
+/**
+  * @brief  Return synchronization info
+  * @param  pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
+  * @retval None
+  */
+void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
+{
+  /* Check the parameter */
+  assert_param(pSynchroInfo != (void *)NULL);
+
+  /* Get the reload value */
+  pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
+
+  /* Get HSI48 oscillator smooth trimming */
+  pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
+
+  /* Get Frequency error capture */
+  pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
+
+  /* Get Frequency error direction */
+  pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
+}
+
+/**
+* @brief Wait for CRS Synchronization status.
+* @param Timeout  Duration of the time-out
+* @note  Timeout is based on the maximum time to receive a SYNC event based on synchronization
+*        frequency.
+* @note    If Time-out set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
+* @retval Combination of Synchronization status
+*          This parameter can be a combination of the following values:
+*            @arg @ref RCC_CRS_TIMEOUT
+*            @arg @ref RCC_CRS_SYNCOK
+*            @arg @ref RCC_CRS_SYNCWARN
+*            @arg @ref RCC_CRS_SYNCERR
+*            @arg @ref RCC_CRS_SYNCMISS
+*            @arg @ref RCC_CRS_TRIMOVF
+*/
+uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
+{
+  uint32_t crsstatus = RCC_CRS_NONE;
+  uint32_t tickstart;
+
+  /* Get time-out */
+  tickstart = HAL_GetTick();
+
+  /* Wait for CRS flag or time-out detection */
+  do
+  {
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+      {
+        crsstatus = RCC_CRS_TIMEOUT;
+      }
+    }
+    /* Check CRS SYNCOK flag  */
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))
+    {
+      /* CRS SYNC event OK */
+      crsstatus |= RCC_CRS_SYNCOK;
+
+      /* Clear CRS SYNC event OK bit */
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);
+    }
+
+    /* Check CRS SYNCWARN flag  */
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))
+    {
+      /* CRS SYNC warning */
+      crsstatus |= RCC_CRS_SYNCWARN;
+
+      /* Clear CRS SYNCWARN bit */
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);
+    }
+
+    /* Check CRS TRIM overflow flag  */
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))
+    {
+      /* CRS SYNC Error */
+      crsstatus |= RCC_CRS_TRIMOVF;
+
+      /* Clear CRS Error bit */
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);
+    }
+
+    /* Check CRS Error flag  */
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))
+    {
+      /* CRS SYNC Error */
+      crsstatus |= RCC_CRS_SYNCERR;
+
+      /* Clear CRS Error bit */
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);
+    }
+
+    /* Check CRS SYNC Missed flag  */
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))
+    {
+      /* CRS SYNC Missed */
+      crsstatus |= RCC_CRS_SYNCMISS;
+
+      /* Clear CRS SYNC Missed bit */
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);
+    }
+
+    /* Check CRS Expected SYNC flag  */
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))
+    {
+      /* frequency error counter reached a zero value */
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
+    }
+  } while(RCC_CRS_NONE == crsstatus);
+
+  return crsstatus;
+}
+
+/**
+  * @brief Handle the Clock Recovery System interrupt request.
+  * @retval None
+  */
+void HAL_RCCEx_CRS_IRQHandler(void)
+{
+  uint32_t crserror = RCC_CRS_NONE;
+  /* Get current IT flags and IT sources values */
+  uint32_t itflags = READ_REG(CRS->ISR);
+  uint32_t itsources = READ_REG(CRS->CR);
+
+  /* Check CRS SYNCOK flag  */
+  if(((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U))
+  {
+    /* Clear CRS SYNC event OK flag */
+    WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
+
+    /* user callback */
+    HAL_RCCEx_CRS_SyncOkCallback();
+  }
+  /* Check CRS SYNCWARN flag  */
+  else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U))
+  {
+    /* Clear CRS SYNCWARN flag */
+    WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
+
+    /* user callback */
+    HAL_RCCEx_CRS_SyncWarnCallback();
+  }
+  /* Check CRS Expected SYNC flag  */
+  else if(((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U))
+  {
+    /* frequency error counter reached a zero value */
+    WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
+
+    /* user callback */
+    HAL_RCCEx_CRS_ExpectedSyncCallback();
+  }
+  /* Check CRS Error flags  */
+  else
+  {
+    if(((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U))
+    {
+      if((itflags & RCC_CRS_FLAG_SYNCERR) != 0U)
+      {
+        crserror |= RCC_CRS_SYNCERR;
+      }
+      if((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U)
+      {
+        crserror |= RCC_CRS_SYNCMISS;
+      }
+      if((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U)
+      {
+        crserror |= RCC_CRS_TRIMOVF;
+      }
+
+      /* Clear CRS Error flags */
+      WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
+
+      /* user error callback */
+      HAL_RCCEx_CRS_ErrorCallback(crserror);
+    }
+  }
+}
+
+/**
+  * @brief  RCCEx Clock Recovery System SYNCOK interrupt callback.
+  * @retval none
+  */
+__weak void HAL_RCCEx_CRS_SyncOkCallback(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file
+   */
+}
+
+/**
+  * @brief  RCCEx Clock Recovery System SYNCWARN interrupt callback.
+  * @retval none
+  */
+__weak void HAL_RCCEx_CRS_SyncWarnCallback(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file
+   */
+}
+
+/**
+  * @brief  RCCEx Clock Recovery System Expected SYNC interrupt callback.
+  * @retval none
+  */
+__weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file
+   */
+}
+
+/**
+  * @brief  RCCEx Clock Recovery System Error interrupt callback.
+  * @param  Error Combination of Error status.
+  *         This parameter can be a combination of the following values:
+  *           @arg @ref RCC_CRS_SYNCERR
+  *           @arg @ref RCC_CRS_SYNCMISS
+  *           @arg @ref RCC_CRS_TRIMOVF
+  * @retval none
+  */
+__weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(Error);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file
+   */
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_Private_functions Private Functions
+ * @{
+ */
+/**
+  * @brief  Configure the PLL2 VCI,VCO ranges, multiplication and division factors and enable it
+  * @param  pll2: Pointer to an RCC_PLL2InitTypeDef structure that
+  *         contains the configuration parameters  as well as VCI, VCO clock ranges.
+  * @param  Divider  divider parameter to be updated
+  * @note   PLL2 is temporary disabled to apply new parameters
+  *
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider)
+{
+
+  uint32_t tickstart;
+  HAL_StatusTypeDef status = HAL_OK;
+  assert_param(IS_RCC_PLL2M_VALUE(pll2->PLL2M));
+  assert_param(IS_RCC_PLL2N_VALUE(pll2->PLL2N));
+  assert_param(IS_RCC_PLL2P_VALUE(pll2->PLL2P));
+  assert_param(IS_RCC_PLL2R_VALUE(pll2->PLL2R));
+  assert_param(IS_RCC_PLL2Q_VALUE(pll2->PLL2Q));
+  assert_param(IS_RCC_PLL2RGE_VALUE(pll2->PLL2RGE));
+  assert_param(IS_RCC_PLL2VCO_VALUE(pll2->PLL2VCOSEL));
+  assert_param(IS_RCC_PLLFRACN_VALUE(pll2->PLL2FRACN));
+
+  /* Check that PLL2 OSC clock source is already set */
+  if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
+  {
+    return HAL_ERROR;
+  }
+
+
+  else
+  {
+    /* Disable  PLL2. */
+    __HAL_RCC_PLL2_DISABLE();
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+
+    /* Wait till PLL is disabled */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U)
+    {
+      if( (HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Configure PLL2 multiplication and division factors. */
+    __HAL_RCC_PLL2_CONFIG(pll2->PLL2M,
+                          pll2->PLL2N,
+                          pll2->PLL2P,
+                          pll2->PLL2Q,
+                          pll2->PLL2R);
+
+    /* Select PLL2 input reference frequency range: VCI */
+    __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE) ;
+
+    /* Select PLL2 output frequency range : VCO */
+    __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ;
+
+    /* Disable PLL2FRACN . */
+    __HAL_RCC_PLL2FRACN_DISABLE();
+
+    /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */
+    __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN);
+
+    /* Enable PLL2FRACN . */
+    __HAL_RCC_PLL2FRACN_ENABLE();
+
+    /* Enable the PLL2 clock output */
+    if(Divider == DIVIDER_P_UPDATE)
+    {
+      __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP);
+    }
+    else if(Divider == DIVIDER_Q_UPDATE)
+    {
+      __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ);
+    }
+    else
+    {
+      __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR);
+    }
+
+    /* Enable  PLL2. */
+    __HAL_RCC_PLL2_ENABLE();
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+
+    /* Wait till PLL2 is ready */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U)
+    {
+      if( (HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+
+  }
+
+
+  return status;
+}
+
+
+/**
+  * @brief  Configure the PLL3 VCI,VCO ranges, multiplication and division factors and enable it
+  * @param  pll3: Pointer to an RCC_PLL3InitTypeDef structure that
+  *         contains the configuration parameters  as well as VCI, VCO clock ranges.
+  * @param  Divider  divider parameter to be updated
+  * @note   PLL3 is temporary disabled to apply new parameters
+  *
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider)
+{
+  uint32_t tickstart;
+  HAL_StatusTypeDef status = HAL_OK;
+  assert_param(IS_RCC_PLL3M_VALUE(pll3->PLL3M));
+  assert_param(IS_RCC_PLL3N_VALUE(pll3->PLL3N));
+  assert_param(IS_RCC_PLL3P_VALUE(pll3->PLL3P));
+  assert_param(IS_RCC_PLL3R_VALUE(pll3->PLL3R));
+  assert_param(IS_RCC_PLL3Q_VALUE(pll3->PLL3Q));
+  assert_param(IS_RCC_PLL3RGE_VALUE(pll3->PLL3RGE));
+  assert_param(IS_RCC_PLL3VCO_VALUE(pll3->PLL3VCOSEL));
+  assert_param(IS_RCC_PLLFRACN_VALUE(pll3->PLL3FRACN));
+
+  /* Check that PLL3 OSC clock source is already set */
+  if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
+  {
+    return HAL_ERROR;
+  }
+
+
+  else
+  {
+    /* Disable  PLL3. */
+    __HAL_RCC_PLL3_DISABLE();
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+    /* Wait till PLL3 is ready */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U)
+    {
+      if( (HAL_GetTick() - tickstart ) > PLL3_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Configure the PLL3  multiplication and division factors. */
+    __HAL_RCC_PLL3_CONFIG(pll3->PLL3M,
+                          pll3->PLL3N,
+                          pll3->PLL3P,
+                          pll3->PLL3Q,
+                          pll3->PLL3R);
+
+    /* Select PLL3 input reference frequency range: VCI */
+    __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ;
+
+    /* Select PLL3 output frequency range : VCO */
+    __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ;
+
+    /* Disable PLL3FRACN . */
+    __HAL_RCC_PLL3FRACN_DISABLE();
+
+    /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */
+    __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN);
+
+    /* Enable PLL3FRACN . */
+    __HAL_RCC_PLL3FRACN_ENABLE();
+
+    /* Enable the PLL3 clock output */
+    if(Divider == DIVIDER_P_UPDATE)
+    {
+      __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP);
+    }
+    else if(Divider == DIVIDER_Q_UPDATE)
+    {
+      __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
+    }
+    else
+    {
+      __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
+    }
+
+    /* Enable  PLL3. */
+    __HAL_RCC_PLL3_ENABLE();
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+
+    /* Wait till PLL3 is ready */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U)
+    {
+      if( (HAL_GetTick() - tickstart ) > PLL3_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+
+  }
+
+
+  return status;
+}
+
+/**
+  * @brief Handle the RCC LSE Clock Security System interrupt request.
+  * @retval None
+  */
+void HAL_RCCEx_LSECSS_IRQHandler(void)
+{
+  /* Check RCC LSE CSSF flag  */
+  if(__HAL_RCC_GET_IT(RCC_IT_LSECSS))
+  {
+
+    /* Clear RCC LSE CSS pending bit */
+    __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS);
+
+    /* RCC LSE Clock Security System interrupt user callback */
+    HAL_RCCEx_LSECSS_Callback();
+
+  }
+}
+
+/**
+  * @brief  RCCEx LSE Clock Security System interrupt callback.
+  * @retval none
+  */
+__weak void HAL_RCCEx_LSECSS_Callback(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file
+   */
+}
+
+
+
+/**
+  * @}
+  */
+
+#endif /* HAL_RCC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c
new file mode 100644
index 00000000..1885d04b
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c
@@ -0,0 +1,7047 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_tim.c
+  * @author  MCD Application Team
+  * @brief   TIM HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Timer (TIM) peripheral:
+  *           + TIM Time Base Initialization
+  *           + TIM Time Base Start
+  *           + TIM Time Base Start Interruption
+  *           + TIM Time Base Start DMA
+  *           + TIM Output Compare/PWM Initialization
+  *           + TIM Output Compare/PWM Channel Configuration
+  *           + TIM Output Compare/PWM  Start
+  *           + TIM Output Compare/PWM  Start Interruption
+  *           + TIM Output Compare/PWM Start DMA
+  *           + TIM Input Capture Initialization
+  *           + TIM Input Capture Channel Configuration
+  *           + TIM Input Capture Start
+  *           + TIM Input Capture Start Interruption
+  *           + TIM Input Capture Start DMA
+  *           + TIM One Pulse Initialization
+  *           + TIM One Pulse Channel Configuration
+  *           + TIM One Pulse Start
+  *           + TIM Encoder Interface Initialization
+  *           + TIM Encoder Interface Start
+  *           + TIM Encoder Interface Start Interruption
+  *           + TIM Encoder Interface Start DMA
+  *           + Commutation Event configuration with Interruption and DMA
+  *           + TIM OCRef clear configuration
+  *           + TIM External Clock configuration
+  @verbatim
+  ==============================================================================
+                      ##### TIMER Generic features #####
+  ==============================================================================
+  [..] The Timer features include:
+       (#) 16-bit up, down, up/down auto-reload counter.
+       (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
+           counter clock frequency either by any factor between 1 and 65536.
+       (#) Up to 4 independent channels for:
+           (++) Input Capture
+           (++) Output Compare
+           (++) PWM generation (Edge and Center-aligned Mode)
+           (++) One-pulse mode output
+       (#) Synchronization circuit to control the timer with external signals and to interconnect
+            several timers together.
+       (#) Supports incremental encoder for positioning purposes
+
+            ##### How to use this driver #####
+  ==============================================================================
+    [..]
+     (#) Initialize the TIM low level resources by implementing the following functions
+         depending on the selected feature:
+           (++) Time Base : HAL_TIM_Base_MspInit()
+           (++) Input Capture : HAL_TIM_IC_MspInit()
+           (++) Output Compare : HAL_TIM_OC_MspInit()
+           (++) PWM generation : HAL_TIM_PWM_MspInit()
+           (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
+           (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
+
+     (#) Initialize the TIM low level resources :
+        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
+        (##) TIM pins configuration
+            (+++) Enable the clock for the TIM GPIOs using the following function:
+             __HAL_RCC_GPIOx_CLK_ENABLE();
+            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
+
+     (#) The external Clock can be configured, if needed (the default clock is the
+         internal clock from the APBx), using the following function:
+         HAL_TIM_ConfigClockSource, the clock configuration should be done before
+         any start function.
+
+     (#) Configure the TIM in the desired functioning mode using one of the
+       Initialization function of this driver:
+       (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
+       (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
+            Output Compare signal.
+       (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
+            PWM signal.
+       (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
+            external signal.
+       (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
+            in One Pulse Mode.
+       (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
+
+     (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
+           (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
+           (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
+           (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
+           (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
+           (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
+           (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
+
+     (#) The DMA Burst is managed with the two following functions:
+         HAL_TIM_DMABurst_WriteStart()
+         HAL_TIM_DMABurst_ReadStart()
+
+    *** Callback registration ***
+  =============================================
+
+  [..]
+  The compilation define  USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
+  allows the user to configure dynamically the driver callbacks.
+
+  [..]
+  Use Function @ref HAL_TIM_RegisterCallback() to register a callback.
+  @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
+  the Callback ID and a pointer to the user callback function.
+
+  [..]
+  Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default
+  weak function.
+  @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
+  and the Callback ID.
+
+  [..]
+  These functions allow to register/unregister following callbacks:
+    (+) Base_MspInitCallback              : TIM Base Msp Init Callback.
+    (+) Base_MspDeInitCallback            : TIM Base Msp DeInit Callback.
+    (+) IC_MspInitCallback                : TIM IC Msp Init Callback.
+    (+) IC_MspDeInitCallback              : TIM IC Msp DeInit Callback.
+    (+) OC_MspInitCallback                : TIM OC Msp Init Callback.
+    (+) OC_MspDeInitCallback              : TIM OC Msp DeInit Callback.
+    (+) PWM_MspInitCallback               : TIM PWM Msp Init Callback.
+    (+) PWM_MspDeInitCallback             : TIM PWM Msp DeInit Callback.
+    (+) OnePulse_MspInitCallback          : TIM One Pulse Msp Init Callback.
+    (+) OnePulse_MspDeInitCallback        : TIM One Pulse Msp DeInit Callback.
+    (+) Encoder_MspInitCallback           : TIM Encoder Msp Init Callback.
+    (+) Encoder_MspDeInitCallback         : TIM Encoder Msp DeInit Callback.
+    (+) HallSensor_MspInitCallback        : TIM Hall Sensor Msp Init Callback.
+    (+) HallSensor_MspDeInitCallback      : TIM Hall Sensor Msp DeInit Callback.
+    (+) PeriodElapsedCallback             : TIM Period Elapsed Callback.
+    (+) PeriodElapsedHalfCpltCallback     : TIM Period Elapsed half complete Callback.
+    (+) TriggerCallback                   : TIM Trigger Callback.
+    (+) TriggerHalfCpltCallback           : TIM Trigger half complete Callback.
+    (+) IC_CaptureCallback                : TIM Input Capture Callback.
+    (+) IC_CaptureHalfCpltCallback        : TIM Input Capture half complete Callback.
+    (+) OC_DelayElapsedCallback           : TIM Output Compare Delay Elapsed Callback.
+    (+) PWM_PulseFinishedCallback         : TIM PWM Pulse Finished Callback.
+    (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
+    (+) ErrorCallback                     : TIM Error Callback.
+    (+) CommutationCallback               : TIM Commutation Callback.
+    (+) CommutationHalfCpltCallback       : TIM Commutation half complete Callback.
+    (+) BreakCallback                     : TIM Break Callback.
+    (+) Break2Callback                    : TIM Break2 Callback.
+
+  [..]
+By default, after the Init and when the state is HAL_TIM_STATE_RESET
+all interrupt callbacks are set to the corresponding weak functions:
+  examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().
+
+  [..]
+  Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
+  functionalities in the Init / DeInit only when these callbacks are null
+  (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
+    keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
+
+  [..]
+    Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
+    Exception done MspInit / MspDeInit that can be registered / unregistered
+    in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
+    thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
+  In that case first register the MspInit/MspDeInit user callbacks
+      using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.
+
+  [..]
+      When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
+      not defined, the callback registration feature is not available and all callbacks
+      are set to the corresponding weak functions.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup TIM TIM
+  * @brief TIM HAL module driver
+  * @{
+  */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup TIM_Private_Functions
+  * @{
+  */
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter);
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter);
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter);
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+                                                  TIM_SlaveConfigTypeDef *sSlaveConfig);
+/**
+  * @}
+  */
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup TIM_Exported_Functions TIM Exported Functions
+  * @{
+  */
+
+/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
+  *  @brief    Time Base functions
+  *
+@verbatim
+  ==============================================================================
+              ##### Time Base functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM base.
+    (+) De-initialize the TIM base.
+    (+) Start the Time Base.
+    (+) Stop the Time Base.
+    (+) Start the Time Base and enable interrupt.
+    (+) Stop the Time Base and disable interrupt.
+    (+) Start the Time Base and enable DMA transfer.
+    (+) Stop the Time Base and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Time base Unit according to the specified
+  *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->Base_MspInitCallback == NULL)
+    {
+      htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->Base_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    HAL_TIM_Base_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Set the Time Base configuration */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM Base peripheral
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->Base_MspDeInitCallback == NULL)
+  {
+    htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->Base_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIM_Base_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Base MSP.
+  * @param  htim TIM Base handle
+  * @retval None
+  */
+__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_Base_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Base MSP.
+  * @param  htim TIM Base handle
+  * @retval None
+  */
+__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_Base_MspDeInit could be implemented in the user file
+   */
+}
+
+
+/**
+  * @brief  Starts the TIM Base generation.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Change the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Base generation.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Base generation in interrupt mode.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  /* Enable the TIM Update interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Base generation in interrupt mode.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  /* Disable the TIM Update interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Base generation in DMA mode.
+  * @param  htim TIM Base handle
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if ((pData == NULL) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+  /* Set the DMA Period elapsed callbacks */
+  htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+  htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+
+  /* Set the DMA error callback */
+  htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+  /* Enable the DMA stream */
+  if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Enable the TIM Update DMA request */
+  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Base generation in DMA mode.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+
+  /* Disable the TIM Update DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
+
+  (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
+  *  @brief    TIM Output Compare functions
+  *
+@verbatim
+  ==============================================================================
+                  ##### TIM Output Compare functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM Output Compare.
+    (+) De-initialize the TIM Output Compare.
+    (+) Start the TIM Output Compare.
+    (+) Stop the TIM Output Compare.
+    (+) Start the TIM Output Compare and enable interrupt.
+    (+) Stop the TIM Output Compare and disable interrupt.
+    (+) Start the TIM Output Compare and enable DMA transfer.
+    (+) Stop the TIM Output Compare and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Output Compare according to the specified
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
+  * @param  htim TIM Output Compare handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->OC_MspInitCallback == NULL)
+    {
+      htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->OC_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_OC_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Init the base time for the Output Compare */
+  TIM_Base_SetConfig(htim->Instance,  &htim->Init);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM peripheral
+  * @param  htim TIM Output Compare handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->OC_MspDeInitCallback == NULL)
+  {
+    htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->OC_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+  HAL_TIM_OC_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Output Compare MSP.
+  * @param  htim TIM Output Compare handle
+  * @retval None
+  */
+__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OC_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Output Compare MSP.
+  * @param  htim TIM Output Compare handle
+  * @retval None
+  */
+__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OC_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Enable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in interrupt mode.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Enable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Enable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in interrupt mode.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Disable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in DMA mode.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if ((pData == NULL) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Enable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 4 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Enable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in DMA mode.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Disable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
+  *  @brief    TIM PWM functions
+  *
+@verbatim
+  ==============================================================================
+                          ##### TIM PWM functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM PWM.
+    (+) De-initialize the TIM PWM.
+    (+) Start the TIM PWM.
+    (+) Stop the TIM PWM.
+    (+) Start the TIM PWM and enable interrupt.
+    (+) Stop the TIM PWM and disable interrupt.
+    (+) Start the TIM PWM and enable DMA transfer.
+    (+) Stop the TIM PWM and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM PWM Time Base according to the specified
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
+  * @param  htim TIM PWM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->PWM_MspInitCallback == NULL)
+    {
+      htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->PWM_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_PWM_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Init the base time for the PWM */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM peripheral
+  * @param  htim TIM PWM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->PWM_MspDeInitCallback == NULL)
+  {
+    htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->PWM_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+  HAL_TIM_PWM_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM PWM MSP.
+  * @param  htim TIM PWM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM PWM MSP.
+  * @param  htim TIM PWM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the PWM signal generation.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Enable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the PWM signal generation.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the PWM signal generation in interrupt mode.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Enable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Enable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the PWM signal generation in interrupt mode.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Disable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM PWM signal generation in DMA mode.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if ((pData == NULL) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Output Capture/Compare 3 request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 4 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Enable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM PWM signal generation in DMA mode.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Disable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
+  *  @brief    TIM Input Capture functions
+  *
+@verbatim
+  ==============================================================================
+              ##### TIM Input Capture functions #####
+  ==============================================================================
+ [..]
+   This section provides functions allowing to:
+   (+) Initialize and configure the TIM Input Capture.
+   (+) De-initialize the TIM Input Capture.
+   (+) Start the TIM Input Capture.
+   (+) Stop the TIM Input Capture.
+   (+) Start the TIM Input Capture and enable interrupt.
+   (+) Stop the TIM Input Capture and disable interrupt.
+   (+) Start the TIM Input Capture and enable DMA transfer.
+   (+) Stop the TIM Input Capture and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Input Capture Time base according to the specified
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
+  * @param  htim TIM Input Capture handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->IC_MspInitCallback == NULL)
+    {
+      htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->IC_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_IC_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Init the base time for the input capture */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM peripheral
+  * @param  htim TIM Input Capture handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->IC_MspDeInitCallback == NULL)
+  {
+    htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->IC_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+  HAL_TIM_IC_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Input Capture MSP.
+  * @param  htim TIM Input Capture handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Input Capture MSP.
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Input Capture measurement.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Enable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Input Capture measurement.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Input Capture measurement in interrupt mode.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Enable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      break;
+  }
+  /* Enable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Input Capture measurement in interrupt mode.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Disable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Input Capture measurement in DMA mode.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  pData The destination Buffer address.
+  * @param  Length The length of data to be transferred from TIM peripheral to memory.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if ((pData == NULL) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 2  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 3  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 4  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Enable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Input Capture measurement in DMA mode.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3  DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4  DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Disable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
+  *  @brief    TIM One Pulse functions
+  *
+@verbatim
+  ==============================================================================
+                        ##### TIM One Pulse functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM One Pulse.
+    (+) De-initialize the TIM One Pulse.
+    (+) Start the TIM One Pulse.
+    (+) Stop the TIM One Pulse.
+    (+) Start the TIM One Pulse and enable interrupt.
+    (+) Stop the TIM One Pulse and disable interrupt.
+    (+) Start the TIM One Pulse and enable DMA transfer.
+    (+) Stop the TIM One Pulse and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM One Pulse Time Base according to the specified
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
+  * @param  htim TIM One Pulse handle
+  * @param  OnePulseMode Select the One pulse mode.
+  *         This parameter can be one of the following values:
+  *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
+  *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_OPM_MODE(OnePulseMode));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->OnePulse_MspInitCallback == NULL)
+    {
+      htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->OnePulse_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_OnePulse_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Configure the Time base in the One Pulse Mode */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Reset the OPM Bit */
+  htim->Instance->CR1 &= ~TIM_CR1_OPM;
+
+  /* Configure the OPM Mode */
+  htim->Instance->CR1 |= OnePulseMode;
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM One Pulse
+  * @param  htim TIM One Pulse handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->OnePulse_MspDeInitCallback == NULL)
+  {
+    htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->OnePulse_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIM_OnePulse_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM One Pulse MSP.
+  * @param  htim TIM One Pulse handle
+  * @retval None
+  */
+__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OnePulse_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM One Pulse MSP.
+  * @param  htim TIM One Pulse handle
+  * @retval None
+  */
+__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation.
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Enable the Capture compare and the Input Capture channels
+    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+    in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+
+    No need to enable the counter, it's enabled automatically by hardware
+    (the counter starts in response to a stimulus and generate a pulse */
+
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM One Pulse signal generation.
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channels to be disable
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Disable the Capture compare and the Input Capture channels
+  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+  in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation in interrupt mode.
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Enable the Capture compare and the Input Capture channels
+    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+    in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+
+    No need to enable the counter, it's enabled automatically by hardware
+    (the counter starts in response to a stimulus and generate a pulse */
+
+  /* Enable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+  /* Enable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM One Pulse signal generation in interrupt mode.
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Disable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+  /* Disable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+
+  /* Disable the Capture compare and the Input Capture channels
+  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+  in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
+  *  @brief    TIM Encoder functions
+  *
+@verbatim
+  ==============================================================================
+                          ##### TIM Encoder functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM Encoder.
+    (+) De-initialize the TIM Encoder.
+    (+) Start the TIM Encoder.
+    (+) Stop the TIM Encoder.
+    (+) Start the TIM Encoder and enable interrupt.
+    (+) Stop the TIM Encoder and disable interrupt.
+    (+) Start the TIM Encoder and enable DMA transfer.
+    (+) Stop the TIM Encoder and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Encoder Interface and initialize the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
+  * @note   Encoder mode and External clock mode 2 are not compatible and must not be selected together
+  *         Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
+  *         using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
+  * @param  htim TIM Encoder Interface handle
+  * @param  sConfig TIM Encoder Interface configuration structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef *sConfig)
+{
+  uint32_t tmpsmcr;
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+  assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
+  assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
+  assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
+  assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
+  assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
+  assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+  assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->Encoder_MspInitCallback == NULL)
+    {
+      htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->Encoder_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_Encoder_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Reset the SMS and ECE bits */
+  htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
+
+  /* Configure the Time base in the Encoder Mode */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = htim->Instance->SMCR;
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmr1 = htim->Instance->CCMR1;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = htim->Instance->CCER;
+
+  /* Set the encoder Mode */
+  tmpsmcr |= sConfig->EncoderMode;
+
+  /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+  tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
+  tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
+
+  /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
+  tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
+  tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
+  tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
+  tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
+
+  /* Set the TI1 and the TI2 Polarities */
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
+  tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
+  tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
+
+  /* Write to TIMx SMCR */
+  htim->Instance->SMCR = tmpsmcr;
+
+  /* Write to TIMx CCMR1 */
+  htim->Instance->CCMR1 = tmpccmr1;
+
+  /* Write to TIMx CCER */
+  htim->Instance->CCER = tmpccer;
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  DeInitializes the TIM Encoder interface
+  * @param  htim TIM Encoder Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->Encoder_MspDeInitCallback == NULL)
+  {
+    htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->Encoder_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIM_Encoder_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Encoder Interface MSP.
+  * @param  htim TIM Encoder Interface handle
+  * @retval None
+  */
+__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_Encoder_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Encoder Interface MSP.
+  * @param  htim TIM Encoder Interface handle
+  * @retval None
+  */
+__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Encoder Interface.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Enable the encoder interface channels */
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      break;
+    }
+
+    default :
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      break;
+    }
+  }
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Encoder Interface.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channels 1 and 2
+    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+      break;
+    }
+
+    default :
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+      break;
+    }
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Encoder Interface in interrupt mode.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Enable the encoder interface channels */
+  /* Enable the capture compare Interrupts 1 and/or 2 */
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    default :
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+  }
+
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Encoder Interface in interrupt mode.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channels 1 and 2
+    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+  if (Channel == TIM_CHANNEL_1)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare Interrupts 1 */
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare Interrupts 2 */
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+  }
+  else
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare Interrupts 1 and 2 */
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Encoder Interface in DMA mode.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @param  pData1 The destination Buffer address for IC1.
+  * @param  pData2 The destination Buffer address for IC2.
+  * @param  Length The length of data to be transferred from TIM peripheral to memory.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
+                                            uint32_t *pData2, uint16_t Length)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Input Capture DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+
+      /* Enable the Peripheral */
+      __HAL_TIM_ENABLE(htim);
+
+      /* Enable the Capture compare channel */
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Input Capture  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+
+      /* Enable the Peripheral */
+      __HAL_TIM_ENABLE(htim);
+
+      /* Enable the Capture compare channel */
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      break;
+    }
+
+    case TIM_CHANNEL_ALL:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the Peripheral */
+      __HAL_TIM_ENABLE(htim);
+
+      /* Enable the Capture compare channel */
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+      /* Enable the TIM Input Capture  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      /* Enable the TIM Input Capture  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    default:
+      break;
+  }
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Encoder Interface in DMA mode.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channels 1 and 2
+    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+  if (Channel == TIM_CHANNEL_1)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare DMA Request 1 */
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare DMA Request 2 */
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+  }
+  else
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare DMA Request 1 and 2 */
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
+  *  @brief    TIM IRQ handler management
+  *
+@verbatim
+  ==============================================================================
+                        ##### IRQ handler management #####
+  ==============================================================================
+  [..]
+    This section provides Timer IRQ handler function.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  This function handles TIM interrupts requests.
+  * @param  htim TIM  handle
+  * @retval None
+  */
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
+{
+  /* Capture compare 1 event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
+    {
+      {
+        __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
+        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+        /* Input capture event */
+        if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
+        {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+          htim->IC_CaptureCallback(htim);
+#else
+          HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+        }
+        /* Output compare event */
+        else
+        {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+          htim->OC_DelayElapsedCallback(htim);
+          htim->PWM_PulseFinishedCallback(htim);
+#else
+          HAL_TIM_OC_DelayElapsedCallback(htim);
+          HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+        }
+        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+      }
+    }
+  }
+  /* Capture compare 2 event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+      /* Input capture event */
+      if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->IC_CaptureCallback(htim);
+#else
+        HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      /* Output compare event */
+      else
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->OC_DelayElapsedCallback(htim);
+        htim->PWM_PulseFinishedCallback(htim);
+#else
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+    }
+  }
+  /* Capture compare 3 event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+      /* Input capture event */
+      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->IC_CaptureCallback(htim);
+#else
+        HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      /* Output compare event */
+      else
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->OC_DelayElapsedCallback(htim);
+        htim->PWM_PulseFinishedCallback(htim);
+#else
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+    }
+  }
+  /* Capture compare 4 event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+      /* Input capture event */
+      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->IC_CaptureCallback(htim);
+#else
+        HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      /* Output compare event */
+      else
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->OC_DelayElapsedCallback(htim);
+        htim->PWM_PulseFinishedCallback(htim);
+#else
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+    }
+  }
+  /* TIM Update event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->PeriodElapsedCallback(htim);
+#else
+      HAL_TIM_PeriodElapsedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM Break input event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->BreakCallback(htim);
+#else
+      HAL_TIMEx_BreakCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM Break2 input event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->Break2Callback(htim);
+#else
+      HAL_TIMEx_Break2Callback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM Trigger detection event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->TriggerCallback(htim);
+#else
+      HAL_TIM_TriggerCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM commutation event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->CommutationCallback(htim);
+#else
+      HAL_TIMEx_CommutCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
+  *  @brief    TIM Peripheral Control functions
+  *
+@verbatim
+  ==============================================================================
+                   ##### Peripheral Control functions #####
+  ==============================================================================
+ [..]
+   This section provides functions allowing to:
+      (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
+      (+) Configure External Clock source.
+      (+) Configure Complementary channels, break features and dead time.
+      (+) Configure Master and the Slave synchronization.
+      (+) Configure the DMA Burst Mode.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the TIM Output Compare Channels according to the specified
+  *         parameters in the TIM_OC_InitTypeDef.
+  * @param  htim TIM Output Compare handle
+  * @param  sConfig TIM Output Compare configuration structure
+  * @param  Channel TIM Channels to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
+                                           TIM_OC_InitTypeDef *sConfig,
+                                           uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CHANNELS(Channel));
+  assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
+  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 1 in Output Compare */
+      TIM_OC1_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 2 in Output Compare */
+      TIM_OC2_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 3 in Output Compare */
+      TIM_OC3_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 4 in Output Compare */
+      TIM_OC4_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    case TIM_CHANNEL_5:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 5 in Output Compare */
+      TIM_OC5_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    case TIM_CHANNEL_6:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 6 in Output Compare */
+      TIM_OC6_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Input Capture Channels according to the specified
+  *         parameters in the TIM_IC_InitTypeDef.
+  * @param  htim TIM IC handle
+  * @param  sConfig TIM Input Capture configuration structure
+  * @param  Channel TIM Channel to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
+  assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
+  assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  if (Channel == TIM_CHANNEL_1)
+  {
+    /* TI1 Configuration */
+    TIM_TI1_SetConfig(htim->Instance,
+                      sConfig->ICPolarity,
+                      sConfig->ICSelection,
+                      sConfig->ICFilter);
+
+    /* Reset the IC1PSC Bits */
+    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+
+    /* Set the IC1PSC value */
+    htim->Instance->CCMR1 |= sConfig->ICPrescaler;
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    /* TI2 Configuration */
+    assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+    TIM_TI2_SetConfig(htim->Instance,
+                      sConfig->ICPolarity,
+                      sConfig->ICSelection,
+                      sConfig->ICFilter);
+
+    /* Reset the IC2PSC Bits */
+    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+    /* Set the IC2PSC value */
+    htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
+  }
+  else if (Channel == TIM_CHANNEL_3)
+  {
+    /* TI3 Configuration */
+    assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+    TIM_TI3_SetConfig(htim->Instance,
+                      sConfig->ICPolarity,
+                      sConfig->ICSelection,
+                      sConfig->ICFilter);
+
+    /* Reset the IC3PSC Bits */
+    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
+
+    /* Set the IC3PSC value */
+    htim->Instance->CCMR2 |= sConfig->ICPrescaler;
+  }
+  else
+  {
+    /* TI4 Configuration */
+    assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+    TIM_TI4_SetConfig(htim->Instance,
+                      sConfig->ICPolarity,
+                      sConfig->ICSelection,
+                      sConfig->ICFilter);
+
+    /* Reset the IC4PSC Bits */
+    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
+
+    /* Set the IC4PSC value */
+    htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
+  }
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM PWM  channels according to the specified
+  *         parameters in the TIM_OC_InitTypeDef.
+  * @param  htim TIM PWM handle
+  * @param  sConfig TIM PWM configuration structure
+  * @param  Channel TIM Channels to be configured
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
+                                            TIM_OC_InitTypeDef *sConfig,
+                                            uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CHANNELS(Channel));
+  assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
+  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+  assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 1 in PWM mode */
+      TIM_OC1_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel1 */
+      htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
+      htim->Instance->CCMR1 |= sConfig->OCFastMode;
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 2 in PWM mode */
+      TIM_OC2_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel2 */
+      htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
+      htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 3 in PWM mode */
+      TIM_OC3_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel3 */
+      htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
+      htim->Instance->CCMR2 |= sConfig->OCFastMode;
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 4 in PWM mode */
+      TIM_OC4_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel4 */
+      htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
+      htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
+      break;
+    }
+
+    case TIM_CHANNEL_5:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 5 in PWM mode */
+      TIM_OC5_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel5*/
+      htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
+      htim->Instance->CCMR3 |= sConfig->OCFastMode;
+      break;
+    }
+
+    case TIM_CHANNEL_6:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 6 in PWM mode */
+      TIM_OC6_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel6 */
+      htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
+      htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM One Pulse Channels according to the specified
+  *         parameters in the TIM_OnePulse_InitTypeDef.
+  * @param  htim TIM One Pulse handle
+  * @param  sConfig TIM One Pulse configuration structure
+  * @param  OutputChannel TIM output channel to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @param  InputChannel TIM input Channel to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @note  To output a waveform with a minimum delay user can enable the fast
+  *        mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
+  *        output is forced in response to the edge detection on TIx input,
+  *        without taking in account the comparison.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef *sConfig,
+                                                 uint32_t OutputChannel,  uint32_t InputChannel)
+{
+  TIM_OC_InitTypeDef temp1;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
+  assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
+
+  if (OutputChannel != InputChannel)
+  {
+    /* Process Locked */
+    __HAL_LOCK(htim);
+
+    htim->State = HAL_TIM_STATE_BUSY;
+
+    /* Extract the Output compare configuration from sConfig structure */
+    temp1.OCMode = sConfig->OCMode;
+    temp1.Pulse = sConfig->Pulse;
+    temp1.OCPolarity = sConfig->OCPolarity;
+    temp1.OCNPolarity = sConfig->OCNPolarity;
+    temp1.OCIdleState = sConfig->OCIdleState;
+    temp1.OCNIdleState = sConfig->OCNIdleState;
+
+    switch (OutputChannel)
+    {
+      case TIM_CHANNEL_1:
+      {
+        assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+        TIM_OC1_SetConfig(htim->Instance, &temp1);
+        break;
+      }
+      case TIM_CHANNEL_2:
+      {
+        assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+        TIM_OC2_SetConfig(htim->Instance, &temp1);
+        break;
+      }
+      default:
+        break;
+    }
+
+    switch (InputChannel)
+    {
+      case TIM_CHANNEL_1:
+      {
+        assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+        TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
+                          sConfig->ICSelection, sConfig->ICFilter);
+
+        /* Reset the IC1PSC Bits */
+        htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+
+        /* Select the Trigger source */
+        htim->Instance->SMCR &= ~TIM_SMCR_TS;
+        htim->Instance->SMCR |= TIM_TS_TI1FP1;
+
+        /* Select the Slave Mode */
+        htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+        htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+        break;
+      }
+      case TIM_CHANNEL_2:
+      {
+        assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+        TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
+                          sConfig->ICSelection, sConfig->ICFilter);
+
+        /* Reset the IC2PSC Bits */
+        htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+        /* Select the Trigger source */
+        htim->Instance->SMCR &= ~TIM_SMCR_TS;
+        htim->Instance->SMCR |= TIM_TS_TI2FP2;
+
+        /* Select the Slave Mode */
+        htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+        htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+        break;
+      }
+
+      default:
+        break;
+    }
+
+    htim->State = HAL_TIM_STATE_READY;
+
+    __HAL_UNLOCK(htim);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data write
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMABASE_CR1
+  *            @arg TIM_DMABASE_CR2
+  *            @arg TIM_DMABASE_SMCR
+  *            @arg TIM_DMABASE_DIER
+  *            @arg TIM_DMABASE_SR
+  *            @arg TIM_DMABASE_EGR
+  *            @arg TIM_DMABASE_CCMR1
+  *            @arg TIM_DMABASE_CCMR2
+  *            @arg TIM_DMABASE_CCER
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
+  *            @arg TIM_DMABASE_ARR
+  *            @arg TIM_DMABASE_RCR
+  *            @arg TIM_DMABASE_CCR1
+  *            @arg TIM_DMABASE_CCR2
+  *            @arg TIM_DMABASE_CCR3
+  *            @arg TIM_DMABASE_CCR4
+  *            @arg TIM_DMABASE_BDTR
+  *            @arg TIM_DMABASE_CCMR3 
+  *            @arg TIM_DMABASE_CCR5 
+  *            @arg TIM_DMABASE_CCR6 
+  *            @arg TIM_DMABASE_AF1  
+  *            @arg TIM_DMABASE_AF2  
+  *            @arg TIM_DMABASE_TISEL
+  *         
+  * @param  BurstRequestSrc TIM DMA Request sources
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+  * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                              uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t  BurstLength)
+{
+  return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+                                          ((BurstLength) >> 8U) + 1U);
+}
+
+/**
+  * @brief  Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA will start the Data write
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMABASE_CR1
+  *            @arg TIM_DMABASE_CR2
+  *            @arg TIM_DMABASE_SMCR
+  *            @arg TIM_DMABASE_DIER
+  *            @arg TIM_DMABASE_SR
+  *            @arg TIM_DMABASE_EGR
+  *            @arg TIM_DMABASE_CCMR1
+  *            @arg TIM_DMABASE_CCMR2
+  *            @arg TIM_DMABASE_CCER
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
+  *            @arg TIM_DMABASE_ARR
+  *            @arg TIM_DMABASE_RCR
+  *            @arg TIM_DMABASE_CCR1
+  *            @arg TIM_DMABASE_CCR2
+  *            @arg TIM_DMABASE_CCR3
+  *            @arg TIM_DMABASE_CCR4
+  *            @arg TIM_DMABASE_BDTR
+  *            @arg TIM_DMABASE_CCMR3 
+  *            @arg TIM_DMABASE_CCR5 
+  *            @arg TIM_DMABASE_CCR6 
+  *            @arg TIM_DMABASE_AF1  
+  *            @arg TIM_DMABASE_AF2  
+  *            @arg TIM_DMABASE_TISEL
+  *         
+  * @param  BurstRequestSrc TIM DMA Request sources
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+  * @param  DataLength Data length. This parameter can be one value
+  *         between 1 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                                   uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
+                                                   uint32_t  BurstLength,  uint32_t  DataLength)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+  assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+  assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if ((BurstBuffer == NULL) && (BurstLength > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+  switch (BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      /* Set the DMA Period elapsed callbacks */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC4:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_COM:
+    {
+      /* Set the DMA commutation callbacks */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_TRIGGER:
+    {
+      /* Set the DMA trigger callbacks */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    default:
+      break;
+  }
+
+  /* Configure the DMA Burst Mode */
+  htim->Instance->DCR = (BurstBaseAddress | BurstLength);
+  /* Enable the TIM DMA Request */
+  __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM DMA Burst mode
+  * @param  htim TIM handle
+  * @param  BurstRequestSrc TIM DMA Request sources to disable
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+
+  /* Abort the DMA transfer (at least disable the DMA stream) */
+  switch (BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+      break;
+    }
+    case TIM_DMA_CC1:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+    case TIM_DMA_CC2:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+    case TIM_DMA_CC3:
+    {
+      status =  HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+    case TIM_DMA_CC4:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+    case TIM_DMA_COM:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+      break;
+    }
+    case TIM_DMA_TRIGGER:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+      break;
+    }
+    default:
+      break;
+  }
+
+  if (HAL_OK == status)
+  {
+    /* Disable the TIM Update DMA request */
+    __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMABASE_CR1
+  *            @arg TIM_DMABASE_CR2
+  *            @arg TIM_DMABASE_SMCR
+  *            @arg TIM_DMABASE_DIER
+  *            @arg TIM_DMABASE_SR
+  *            @arg TIM_DMABASE_EGR
+  *            @arg TIM_DMABASE_CCMR1
+  *            @arg TIM_DMABASE_CCMR2
+  *            @arg TIM_DMABASE_CCER
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
+  *            @arg TIM_DMABASE_ARR
+  *            @arg TIM_DMABASE_RCR
+  *            @arg TIM_DMABASE_CCR1
+  *            @arg TIM_DMABASE_CCR2
+  *            @arg TIM_DMABASE_CCR3
+  *            @arg TIM_DMABASE_CCR4
+  *            @arg TIM_DMABASE_BDTR
+  *            @arg TIM_DMABASE_CCMR3 
+  *            @arg TIM_DMABASE_CCR5 
+  *            @arg TIM_DMABASE_CCR6 
+  *            @arg TIM_DMABASE_AF1  
+  *            @arg TIM_DMABASE_AF2  
+  *            @arg TIM_DMABASE_TISEL
+  *         
+  * @param  BurstRequestSrc TIM DMA Request sources
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+  * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                             uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength)
+{
+  return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+                                         ((BurstLength) >> 8U) + 1U);
+}
+
+/**
+  * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMABASE_CR1
+  *            @arg TIM_DMABASE_CR2
+  *            @arg TIM_DMABASE_SMCR
+  *            @arg TIM_DMABASE_DIER
+  *            @arg TIM_DMABASE_SR
+  *            @arg TIM_DMABASE_EGR
+  *            @arg TIM_DMABASE_CCMR1
+  *            @arg TIM_DMABASE_CCMR2
+  *            @arg TIM_DMABASE_CCER
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
+  *            @arg TIM_DMABASE_ARR
+  *            @arg TIM_DMABASE_RCR
+  *            @arg TIM_DMABASE_CCR1
+  *            @arg TIM_DMABASE_CCR2
+  *            @arg TIM_DMABASE_CCR3
+  *            @arg TIM_DMABASE_CCR4
+  *            @arg TIM_DMABASE_BDTR
+  *            @arg TIM_DMABASE_CCMR3 
+  *            @arg TIM_DMABASE_CCR5 
+  *            @arg TIM_DMABASE_CCR6 
+  *            @arg TIM_DMABASE_AF1  
+  *            @arg TIM_DMABASE_AF2  
+  *            @arg TIM_DMABASE_TISEL
+  *         
+  * @param  BurstRequestSrc TIM DMA Request sources
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+  * @param  DataLength Data length. This parameter can be one value
+  *         between 1 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                                  uint32_t BurstRequestSrc, uint32_t  *BurstBuffer,
+                                                  uint32_t  BurstLength, uint32_t  DataLength)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+  assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+  assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if ((BurstBuffer == NULL) && (BurstLength > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+  switch (BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      /* Set the DMA Period elapsed callbacks */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC1:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC2:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC3:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC4:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_COM:
+    {
+      /* Set the DMA commutation callbacks */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_TRIGGER:
+    {
+      /* Set the DMA trigger callbacks */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    default:
+      break;
+  }
+
+  /* Configure the DMA Burst Mode */
+  htim->Instance->DCR = (BurstBaseAddress | BurstLength);
+
+  /* Enable the TIM DMA Request */
+  __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the DMA burst reading
+  * @param  htim TIM handle
+  * @param  BurstRequestSrc TIM DMA Request sources to disable.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+
+  /* Abort the DMA transfer (at least disable the DMA stream) */
+  switch (BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+      break;
+    }
+    case TIM_DMA_CC1:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+    case TIM_DMA_CC2:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+    case TIM_DMA_CC3:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+    case TIM_DMA_CC4:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+    case TIM_DMA_COM:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+      break;
+    }
+    case TIM_DMA_TRIGGER:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+      break;
+    }
+    default:
+      break;
+  }
+
+  if (HAL_OK == status)
+  {
+    /* Disable the TIM Update DMA request */
+    __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Generate a software event
+  * @param  htim TIM handle
+  * @param  EventSource specifies the event source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
+  *            @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
+  *            @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
+  *            @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
+  *            @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
+  *            @arg TIM_EVENTSOURCE_COM: Timer COM event source
+  *            @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
+  *            @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
+  *            @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
+  * @note   Basic timers can only generate an update event.
+  * @note   TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
+  * @note   TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant
+  *         only for timer instances supporting break input(s).
+  * @retval HAL status
+  */
+
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_EVENT_SOURCE(EventSource));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  /* Change the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Set the event sources */
+  htim->Instance->EGR = EventSource;
+
+  /* Change the TIM state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the OCRef clear feature
+  * @param  htim TIM handle
+  * @param  sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
+  *         contains the OCREF clear feature and parameters for the TIM peripheral.
+  * @param  Channel specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1
+  *            @arg TIM_CHANNEL_2: TIM Channel 2
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  *            @arg TIM_CHANNEL_4: TIM Channel 4
+  *            @arg TIM_CHANNEL_5: TIM Channel 5
+  *            @arg TIM_CHANNEL_6: TIM Channel 6
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
+                                           TIM_ClearInputConfigTypeDef *sClearInputConfig,
+                                           uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  switch (sClearInputConfig->ClearInputSource)
+  {
+    case TIM_CLEARINPUTSOURCE_NONE:
+    {
+      /* Clear the OCREF clear selection bit and the the ETR Bits */
+      CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
+      break;
+    }
+
+    case TIM_CLEARINPUTSOURCE_ETR:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
+      assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
+      assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
+
+      /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
+      if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
+      {
+        htim->State = HAL_TIM_STATE_READY;
+        __HAL_UNLOCK(htim);
+        return HAL_ERROR;
+      }
+
+      TIM_ETR_SetConfig(htim->Instance,
+                        sClearInputConfig->ClearInputPrescaler,
+                        sClearInputConfig->ClearInputPolarity,
+                        sClearInputConfig->ClearInputFilter);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+      {
+        /* Enable the OCREF clear feature for Channel 1 */
+        SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
+      }
+      else
+      {
+        /* Disable the OCREF clear feature for Channel 1 */
+        CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
+      }
+      break;
+    }
+    case TIM_CHANNEL_2:
+    {
+      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+      {
+        /* Enable the OCREF clear feature for Channel 2 */
+        SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
+      }
+      else
+      {
+        /* Disable the OCREF clear feature for Channel 2 */
+        CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
+      }
+      break;
+    }
+    case TIM_CHANNEL_3:
+    {
+      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+      {
+        /* Enable the OCREF clear feature for Channel 3 */
+        SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
+      }
+      else
+      {
+        /* Disable the OCREF clear feature for Channel 3 */
+        CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
+      }
+      break;
+    }
+    case TIM_CHANNEL_4:
+    {
+      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+      {
+        /* Enable the OCREF clear feature for Channel 4 */
+        SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
+      }
+      else
+      {
+        /* Disable the OCREF clear feature for Channel 4 */
+        CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
+      }
+      break;
+    }
+    case TIM_CHANNEL_5:
+    {
+      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+      {
+        /* Enable the OCREF clear feature for Channel 5 */
+        SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
+      }
+      else
+      {
+        /* Disable the OCREF clear feature for Channel 5 */
+        CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
+      }
+      break;
+    }
+    case TIM_CHANNEL_6:
+    {
+      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+      {
+        /* Enable the OCREF clear feature for Channel 6 */
+        SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
+      }
+      else
+      {
+        /* Disable the OCREF clear feature for Channel 6 */
+        CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
+      }
+      break;
+    }
+    default:
+      break;
+  }
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief   Configures the clock source to be used
+  * @param  htim TIM handle
+  * @param  sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
+  *         contains the clock source information for the TIM peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
+{
+  uint32_t tmpsmcr;
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
+
+  /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
+  tmpsmcr = htim->Instance->SMCR;
+  tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+  htim->Instance->SMCR = tmpsmcr;
+
+  switch (sClockSourceConfig->ClockSource)
+  {
+    case TIM_CLOCKSOURCE_INTERNAL:
+    {
+      assert_param(IS_TIM_INSTANCE(htim->Instance));
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_ETRMODE1:
+    {
+      /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
+      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
+
+      /* Check ETR input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      /* Configure the ETR Clock source */
+      TIM_ETR_SetConfig(htim->Instance,
+                        sClockSourceConfig->ClockPrescaler,
+                        sClockSourceConfig->ClockPolarity,
+                        sClockSourceConfig->ClockFilter);
+
+      /* Select the External clock mode1 and the ETRF trigger */
+      tmpsmcr = htim->Instance->SMCR;
+      tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
+      /* Write to TIMx SMCR */
+      htim->Instance->SMCR = tmpsmcr;
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_ETRMODE2:
+    {
+      /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
+      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
+
+      /* Check ETR input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      /* Configure the ETR Clock source */
+      TIM_ETR_SetConfig(htim->Instance,
+                        sClockSourceConfig->ClockPrescaler,
+                        sClockSourceConfig->ClockPolarity,
+                        sClockSourceConfig->ClockFilter);
+      /* Enable the External clock mode2 */
+      htim->Instance->SMCR |= TIM_SMCR_ECE;
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_TI1:
+    {
+      /* Check whether or not the timer instance supports external clock mode 1 */
+      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+      /* Check TI1 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI1_ConfigInputStage(htim->Instance,
+                               sClockSourceConfig->ClockPolarity,
+                               sClockSourceConfig->ClockFilter);
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_TI2:
+    {
+      /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
+      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+      /* Check TI2 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI2_ConfigInputStage(htim->Instance,
+                               sClockSourceConfig->ClockPolarity,
+                               sClockSourceConfig->ClockFilter);
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_TI1ED:
+    {
+      /* Check whether or not the timer instance supports external clock mode 1 */
+      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+      /* Check TI1 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI1_ConfigInputStage(htim->Instance,
+                               sClockSourceConfig->ClockPolarity,
+                               sClockSourceConfig->ClockFilter);
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_ITR0:
+    case TIM_CLOCKSOURCE_ITR1:
+    case TIM_CLOCKSOURCE_ITR2:
+    case TIM_CLOCKSOURCE_ITR3:
+    case TIM_CLOCKSOURCE_ITR4:
+    case TIM_CLOCKSOURCE_ITR5:
+    case TIM_CLOCKSOURCE_ITR6:
+    case TIM_CLOCKSOURCE_ITR7:
+    case TIM_CLOCKSOURCE_ITR8:
+    {
+      /* Check whether or not the timer instance supports internal trigger input */
+      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
+
+      TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
+      break;
+    }
+
+    default:
+      break;
+  }
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Selects the signal connected to the TI1 input: direct from CH1_input
+  *         or a XOR combination between CH1_input, CH2_input & CH3_input
+  * @param  htim TIM handle.
+  * @param  TI1_Selection Indicate whether or not channel 1 is connected to the
+  *         output of a XOR gate.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
+  *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
+  *            pins are connected to the TI1 input (XOR combination)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
+{
+  uint32_t tmpcr2;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = htim->Instance->CR2;
+
+  /* Reset the TI1 selection */
+  tmpcr2 &= ~TIM_CR2_TI1S;
+
+  /* Set the TI1 selection */
+  tmpcr2 |= TI1_Selection;
+
+  /* Write to TIMxCR2 */
+  htim->Instance->CR2 = tmpcr2;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the TIM in Slave mode
+  * @param  htim TIM handle.
+  * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
+  *         contains the selected trigger (internal trigger input, filtered
+  *         timer input or external trigger input) and the Slave mode
+  *         (Disable, Reset, Gated, Trigger, External clock mode 1).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+  assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
+  {
+    htim->State = HAL_TIM_STATE_READY;
+    __HAL_UNLOCK(htim);
+    return HAL_ERROR;
+  }
+
+  /* Disable Trigger Interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
+
+  /* Disable Trigger DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the TIM in Slave mode in interrupt mode
+  * @param  htim TIM handle.
+  * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
+  *         contains the selected trigger (internal trigger input, filtered
+  *         timer input or external trigger input) and the Slave mode
+  *         (Disable, Reset, Gated, Trigger, External clock mode 1).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
+                                                TIM_SlaveConfigTypeDef *sSlaveConfig)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+  assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
+  {
+    htim->State = HAL_TIM_STATE_READY;
+    __HAL_UNLOCK(htim);
+    return HAL_ERROR;
+  }
+
+  /* Enable Trigger Interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
+
+  /* Disable Trigger DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Read the captured value from Capture Compare unit
+  * @param  htim TIM handle.
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval Captured value
+  */
+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpreg = 0U;
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+      /* Return the capture 1 value */
+      tmpreg =  htim->Instance->CCR1;
+
+      break;
+    }
+    case TIM_CHANNEL_2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+      /* Return the capture 2 value */
+      tmpreg =   htim->Instance->CCR2;
+
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+      /* Return the capture 3 value */
+      tmpreg =   htim->Instance->CCR3;
+
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+      /* Return the capture 4 value */
+      tmpreg =   htim->Instance->CCR4;
+
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  return tmpreg;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
+  *  @brief    TIM Callbacks functions
+  *
+@verbatim
+  ==============================================================================
+                        ##### TIM Callbacks functions #####
+  ==============================================================================
+ [..]
+   This section provides TIM callback functions:
+   (+) TIM Period elapsed callback
+   (+) TIM Output Compare callback
+   (+) TIM Input capture callback
+   (+) TIM Trigger callback
+   (+) TIM Error callback
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Period elapsed callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Period elapsed half complete callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Output Compare callback in non-blocking mode
+  * @param  htim TIM OC handle
+  * @retval None
+  */
+__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Input Capture callback in non-blocking mode
+  * @param  htim TIM IC handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_CaptureCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Input Capture half complete callback in non-blocking mode
+  * @param  htim TIM IC handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  PWM Pulse finished callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  PWM Pulse finished half complete callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Hall Trigger detection callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_TriggerCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Hall Trigger detection half complete callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Timer error callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_ErrorCallback could be implemented in the user file
+   */
+}
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User TIM callback to be used instead of the weak predefined callback
+  * @param htim tim handle
+  * @param CallbackID ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
+  *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
+  *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
+  *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
+  *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
+  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
+  *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
+  *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
+  *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
+  *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
+  *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
+  *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
+  *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
+  *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
+  *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
+  *          @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
+  *          @param pCallback pointer to the callback function
+  *          @retval status
+  */
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
+                                           pTIM_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(htim);
+
+  if (htim->State == HAL_TIM_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_TIM_BASE_MSPINIT_CB_ID :
+        htim->Base_MspInitCallback                 = pCallback;
+        break;
+
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+        htim->Base_MspDeInitCallback               = pCallback;
+        break;
+
+      case HAL_TIM_IC_MSPINIT_CB_ID :
+        htim->IC_MspInitCallback                   = pCallback;
+        break;
+
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :
+        htim->IC_MspDeInitCallback                 = pCallback;
+        break;
+
+      case HAL_TIM_OC_MSPINIT_CB_ID :
+        htim->OC_MspInitCallback                   = pCallback;
+        break;
+
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :
+        htim->OC_MspDeInitCallback                 = pCallback;
+        break;
+
+      case HAL_TIM_PWM_MSPINIT_CB_ID :
+        htim->PWM_MspInitCallback                  = pCallback;
+        break;
+
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+        htim->PWM_MspDeInitCallback                = pCallback;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+        htim->OnePulse_MspInitCallback             = pCallback;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+        htim->OnePulse_MspDeInitCallback           = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+        htim->Encoder_MspInitCallback              = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+        htim->Encoder_MspDeInitCallback            = pCallback;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+        htim->HallSensor_MspInitCallback           = pCallback;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+        htim->HallSensor_MspDeInitCallback         = pCallback;
+        break;
+
+      case HAL_TIM_PERIOD_ELAPSED_CB_ID :
+        htim->PeriodElapsedCallback                = pCallback;
+        break;
+
+      case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
+        htim->PeriodElapsedHalfCpltCallback        = pCallback;
+        break;
+
+      case HAL_TIM_TRIGGER_CB_ID :
+        htim->TriggerCallback                      = pCallback;
+        break;
+
+      case HAL_TIM_TRIGGER_HALF_CB_ID :
+        htim->TriggerHalfCpltCallback              = pCallback;
+        break;
+
+      case HAL_TIM_IC_CAPTURE_CB_ID :
+        htim->IC_CaptureCallback                   = pCallback;
+        break;
+
+      case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
+        htim->IC_CaptureHalfCpltCallback           = pCallback;
+        break;
+
+      case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
+        htim->OC_DelayElapsedCallback              = pCallback;
+        break;
+
+      case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
+        htim->PWM_PulseFinishedCallback            = pCallback;
+        break;
+
+      case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
+        htim->PWM_PulseFinishedHalfCpltCallback    = pCallback;
+        break;
+
+      case HAL_TIM_ERROR_CB_ID :
+        htim->ErrorCallback                        = pCallback;
+        break;
+
+      case HAL_TIM_COMMUTATION_CB_ID :
+        htim->CommutationCallback                  = pCallback;
+        break;
+
+      case HAL_TIM_COMMUTATION_HALF_CB_ID :
+        htim->CommutationHalfCpltCallback          = pCallback;
+        break;
+
+      case HAL_TIM_BREAK_CB_ID :
+        htim->BreakCallback                        = pCallback;
+        break;
+
+      case HAL_TIM_BREAK2_CB_ID :
+        htim->Break2Callback                       = pCallback;
+        break;
+
+      default :
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_TIM_BASE_MSPINIT_CB_ID :
+        htim->Base_MspInitCallback         = pCallback;
+        break;
+
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+        htim->Base_MspDeInitCallback       = pCallback;
+        break;
+
+      case HAL_TIM_IC_MSPINIT_CB_ID :
+        htim->IC_MspInitCallback           = pCallback;
+        break;
+
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :
+        htim->IC_MspDeInitCallback         = pCallback;
+        break;
+
+      case HAL_TIM_OC_MSPINIT_CB_ID :
+        htim->OC_MspInitCallback           = pCallback;
+        break;
+
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :
+        htim->OC_MspDeInitCallback         = pCallback;
+        break;
+
+      case HAL_TIM_PWM_MSPINIT_CB_ID :
+        htim->PWM_MspInitCallback          = pCallback;
+        break;
+
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+        htim->PWM_MspDeInitCallback        = pCallback;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+        htim->OnePulse_MspInitCallback     = pCallback;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+        htim->OnePulse_MspDeInitCallback   = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+        htim->Encoder_MspInitCallback      = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+        htim->Encoder_MspDeInitCallback    = pCallback;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+        htim->HallSensor_MspInitCallback   = pCallback;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+        htim->HallSensor_MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a TIM callback
+  *         TIM callback is redirected to the weak predefined callback
+  * @param htim tim handle
+  * @param CallbackID ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
+  *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
+  *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
+  *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
+  *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
+  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
+  *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
+  *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
+  *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
+  *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
+  *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
+  *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
+  *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
+  *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
+  *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
+  *          @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
+  *          @retval status
+  */
+HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(htim);
+
+  if (htim->State == HAL_TIM_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_TIM_BASE_MSPINIT_CB_ID :
+        htim->Base_MspInitCallback              = HAL_TIM_Base_MspInit;                      /* Legacy weak Base MspInit Callback */
+        break;
+
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+        htim->Base_MspDeInitCallback            = HAL_TIM_Base_MspDeInit;                    /* Legacy weak Base Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_IC_MSPINIT_CB_ID :
+        htim->IC_MspInitCallback                = HAL_TIM_IC_MspInit;                        /* Legacy weak IC Msp Init Callback */
+        break;
+
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :
+        htim->IC_MspDeInitCallback              = HAL_TIM_IC_MspDeInit;                      /* Legacy weak IC Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_OC_MSPINIT_CB_ID :
+        htim->OC_MspInitCallback                = HAL_TIM_OC_MspInit;                        /* Legacy weak OC Msp Init Callback */
+        break;
+
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :
+        htim->OC_MspDeInitCallback              = HAL_TIM_OC_MspDeInit;                      /* Legacy weak OC Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_PWM_MSPINIT_CB_ID :
+        htim->PWM_MspInitCallback               = HAL_TIM_PWM_MspInit;                       /* Legacy weak PWM Msp Init Callback */
+        break;
+
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+        htim->PWM_MspDeInitCallback             = HAL_TIM_PWM_MspDeInit;                     /* Legacy weak PWM Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+        htim->OnePulse_MspInitCallback          = HAL_TIM_OnePulse_MspInit;                  /* Legacy weak One Pulse Msp Init Callback */
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+        htim->OnePulse_MspDeInitCallback        = HAL_TIM_OnePulse_MspDeInit;                /* Legacy weak One Pulse Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+        htim->Encoder_MspInitCallback           = HAL_TIM_Encoder_MspInit;                   /* Legacy weak Encoder Msp Init Callback */
+        break;
+
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+        htim->Encoder_MspDeInitCallback         = HAL_TIM_Encoder_MspDeInit;                 /* Legacy weak Encoder Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+        htim->HallSensor_MspInitCallback        = HAL_TIMEx_HallSensor_MspInit;              /* Legacy weak Hall Sensor Msp Init Callback */
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+        htim->HallSensor_MspDeInitCallback      = HAL_TIMEx_HallSensor_MspDeInit;            /* Legacy weak Hall Sensor Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_PERIOD_ELAPSED_CB_ID :
+        htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;             /* Legacy weak Period Elapsed Callback */
+        break;
+
+      case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
+        htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;     /* Legacy weak Period Elapsed half complete Callback */
+        break;
+
+      case HAL_TIM_TRIGGER_CB_ID :
+        htim->TriggerCallback                   = HAL_TIM_TriggerCallback;                   /* Legacy weak Trigger Callback */
+        break;
+
+      case HAL_TIM_TRIGGER_HALF_CB_ID :
+        htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;           /* Legacy weak Trigger half complete Callback */
+        break;
+
+      case HAL_TIM_IC_CAPTURE_CB_ID :
+        htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;                /* Legacy weak IC Capture Callback */
+        break;
+
+      case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
+        htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;        /* Legacy weak IC Capture half complete Callback */
+        break;
+
+      case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
+        htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;           /* Legacy weak OC Delay Elapsed Callback */
+        break;
+
+      case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
+        htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;         /* Legacy weak PWM Pulse Finished Callback */
+        break;
+
+      case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
+        htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */
+        break;
+
+      case HAL_TIM_ERROR_CB_ID :
+        htim->ErrorCallback                     = HAL_TIM_ErrorCallback;                     /* Legacy weak Error Callback */
+        break;
+
+      case HAL_TIM_COMMUTATION_CB_ID :
+        htim->CommutationCallback               = HAL_TIMEx_CommutCallback;                  /* Legacy weak Commutation Callback */
+        break;
+
+      case HAL_TIM_COMMUTATION_HALF_CB_ID :
+        htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;          /* Legacy weak Commutation half complete Callback */
+        break;
+
+      case HAL_TIM_BREAK_CB_ID :
+        htim->BreakCallback                     = HAL_TIMEx_BreakCallback;                   /* Legacy weak Break Callback */
+        break;
+
+      case HAL_TIM_BREAK2_CB_ID :
+        htim->Break2Callback                    = HAL_TIMEx_Break2Callback;                  /* Legacy weak Break2 Callback */
+        break;
+
+      default :
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_TIM_BASE_MSPINIT_CB_ID :
+        htim->Base_MspInitCallback         = HAL_TIM_Base_MspInit;              /* Legacy weak Base MspInit Callback */
+        break;
+
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+        htim->Base_MspDeInitCallback       = HAL_TIM_Base_MspDeInit;            /* Legacy weak Base Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_IC_MSPINIT_CB_ID :
+        htim->IC_MspInitCallback           = HAL_TIM_IC_MspInit;                /* Legacy weak IC Msp Init Callback */
+        break;
+
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :
+        htim->IC_MspDeInitCallback         = HAL_TIM_IC_MspDeInit;              /* Legacy weak IC Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_OC_MSPINIT_CB_ID :
+        htim->OC_MspInitCallback           = HAL_TIM_OC_MspInit;                /* Legacy weak OC Msp Init Callback */
+        break;
+
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :
+        htim->OC_MspDeInitCallback         = HAL_TIM_OC_MspDeInit;              /* Legacy weak OC Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_PWM_MSPINIT_CB_ID :
+        htim->PWM_MspInitCallback          = HAL_TIM_PWM_MspInit;               /* Legacy weak PWM Msp Init Callback */
+        break;
+
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+        htim->PWM_MspDeInitCallback        = HAL_TIM_PWM_MspDeInit;             /* Legacy weak PWM Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+        htim->OnePulse_MspInitCallback     = HAL_TIM_OnePulse_MspInit;          /* Legacy weak One Pulse Msp Init Callback */
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+        htim->OnePulse_MspDeInitCallback   = HAL_TIM_OnePulse_MspDeInit;        /* Legacy weak One Pulse Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+        htim->Encoder_MspInitCallback      = HAL_TIM_Encoder_MspInit;           /* Legacy weak Encoder Msp Init Callback */
+        break;
+
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+        htim->Encoder_MspDeInitCallback    = HAL_TIM_Encoder_MspDeInit;         /* Legacy weak Encoder Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+        htim->HallSensor_MspInitCallback   = HAL_TIMEx_HallSensor_MspInit;      /* Legacy weak Hall Sensor Msp Init Callback */
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+        htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;    /* Legacy weak Hall Sensor Msp DeInit Callback */
+        break;
+
+      default :
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
+  *  @brief   TIM Peripheral State functions
+  *
+@verbatim
+  ==============================================================================
+                        ##### Peripheral State functions #####
+  ==============================================================================
+    [..]
+    This subsection permits to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the TIM Base handle state.
+  * @param  htim TIM Base handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM OC handle state.
+  * @param  htim TIM Output Compare handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM PWM handle state.
+  * @param  htim TIM handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM Input Capture handle state.
+  * @param  htim TIM IC handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM One Pulse Mode handle state.
+  * @param  htim TIM OPM handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM Encoder Mode handle state.
+  * @param  htim TIM Encoder Interface handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Private_Functions TIM Private Functions
+  * @{
+  */
+
+/**
+  * @brief  TIM DMA error callback
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMAError(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->ErrorCallback(htim);
+#else
+  HAL_TIM_ErrorCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Delay Pulse complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PWM_PulseFinishedCallback(htim);
+#else
+  HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Delay Pulse half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PWM_PulseFinishedHalfCpltCallback(htim);
+#else
+  HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Capture complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->IC_CaptureCallback(htim);
+#else
+  HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Capture half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->IC_CaptureHalfCpltCallback(htim);
+#else
+  HAL_TIM_IC_CaptureHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Period Elapse complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PeriodElapsedCallback(htim);
+#else
+  HAL_TIM_PeriodElapsedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Period Elapse half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PeriodElapsedHalfCpltCallback(htim);
+#else
+  HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Trigger callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->TriggerCallback(htim);
+#else
+  HAL_TIM_TriggerCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Trigger half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->TriggerHalfCpltCallback(htim);
+#else
+  HAL_TIM_TriggerHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  Time Base configuration
+  * @param  TIMx TIM peripheral
+  * @param  Structure TIM Base configuration structure
+  * @retval None
+  */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
+{
+  uint32_t tmpcr1;
+  tmpcr1 = TIMx->CR1;
+
+  /* Set TIM Time Base Unit parameters ---------------------------------------*/
+  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
+  {
+    /* Select the Counter Mode */
+    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
+    tmpcr1 |= Structure->CounterMode;
+  }
+
+  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
+  {
+    /* Set the clock division */
+    tmpcr1 &= ~TIM_CR1_CKD;
+    tmpcr1 |= (uint32_t)Structure->ClockDivision;
+  }
+
+  /* Set the auto-reload preload */
+  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
+
+  TIMx->CR1 = tmpcr1;
+
+  /* Set the Autoreload value */
+  TIMx->ARR = (uint32_t)Structure->Period ;
+
+  /* Set the Prescaler value */
+  TIMx->PSC = Structure->Prescaler;
+
+  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
+  {
+    /* Set the Repetition Counter value */
+    TIMx->RCR = Structure->RepetitionCounter;
+  }
+
+  /* Generate an update event to reload the Prescaler
+     and the repetition counter (only for advanced timer) value immediately */
+  TIMx->EGR = TIM_EGR_UG;
+}
+
+/**
+  * @brief  Timer Output Compare 1 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The ouput configuration structure
+  * @retval None
+  */
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR1;
+
+  /* Reset the Output Compare Mode Bits */
+  tmpccmrx &= ~TIM_CCMR1_OC1M;
+  tmpccmrx &= ~TIM_CCMR1_CC1S;
+  /* Select the Output Compare Mode */
+  tmpccmrx |= OC_Config->OCMode;
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC1P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= OC_Config->OCPolarity;
+
+  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+    /* Reset the Output N Polarity level */
+    tmpccer &= ~TIM_CCER_CC1NP;
+    /* Set the Output N Polarity */
+    tmpccer |= OC_Config->OCNPolarity;
+    /* Reset the Output N State */
+    tmpccer &= ~TIM_CCER_CC1NE;
+  }
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS1;
+    tmpcr2 &= ~TIM_CR2_OIS1N;
+    /* Set the Output Idle state */
+    tmpcr2 |= OC_Config->OCIdleState;
+    /* Set the Output N Idle state */
+    tmpcr2 |= OC_Config->OCNIdleState;
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR1 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Output Compare 2 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The ouput configuration structure
+  * @retval None
+  */
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR1;
+
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= ~TIM_CCMR1_OC2M;
+  tmpccmrx &= ~TIM_CCMR1_CC2S;
+
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (OC_Config->OCMode << 8U);
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC2P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 4U);
+
+  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
+  {
+    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+    /* Reset the Output N Polarity level */
+    tmpccer &= ~TIM_CCER_CC2NP;
+    /* Set the Output N Polarity */
+    tmpccer |= (OC_Config->OCNPolarity << 4U);
+    /* Reset the Output N State */
+    tmpccer &= ~TIM_CCER_CC2NE;
+
+  }
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS2;
+    tmpcr2 &= ~TIM_CR2_OIS2N;
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 2U);
+    /* Set the Output N Idle state */
+    tmpcr2 |= (OC_Config->OCNIdleState << 2U);
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR2 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Output Compare 3 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The ouput configuration structure
+  * @retval None
+  */
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Disable the Channel 3: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC3E;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+
+  /* Get the TIMx CCMR2 register value */
+  tmpccmrx = TIMx->CCMR2;
+
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= ~TIM_CCMR2_OC3M;
+  tmpccmrx &= ~TIM_CCMR2_CC3S;
+  /* Select the Output Compare Mode */
+  tmpccmrx |= OC_Config->OCMode;
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC3P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 8U);
+
+  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
+  {
+    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+    /* Reset the Output N Polarity level */
+    tmpccer &= ~TIM_CCER_CC3NP;
+    /* Set the Output N Polarity */
+    tmpccer |= (OC_Config->OCNPolarity << 8U);
+    /* Reset the Output N State */
+    tmpccer &= ~TIM_CCER_CC3NE;
+  }
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS3;
+    tmpcr2 &= ~TIM_CR2_OIS3N;
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 4U);
+    /* Set the Output N Idle state */
+    tmpcr2 |= (OC_Config->OCNIdleState << 4U);
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR2 */
+  TIMx->CCMR2 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR3 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Output Compare 4 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The ouput configuration structure
+  * @retval None
+  */
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Disable the Channel 4: Reset the CC4E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC4E;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+
+  /* Get the TIMx CCMR2 register value */
+  tmpccmrx = TIMx->CCMR2;
+
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= ~TIM_CCMR2_OC4M;
+  tmpccmrx &= ~TIM_CCMR2_CC4S;
+
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (OC_Config->OCMode << 8U);
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC4P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 12U);
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+    /* Reset the Output Compare IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS4;
+
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 6U);
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR2 */
+  TIMx->CCMR2 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR4 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Output Compare 5 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The ouput configuration structure
+  * @retval None
+  */
+static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
+                              TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Disable the output: Reset the CCxE Bit */
+  TIMx->CCER &= ~TIM_CCER_CC5E;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR3;
+
+  /* Reset the Output Compare Mode Bits */
+  tmpccmrx &= ~(TIM_CCMR3_OC5M);
+  /* Select the Output Compare Mode */
+  tmpccmrx |= OC_Config->OCMode;
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC5P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 16U);
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Reset the Output Compare IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS5;
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 8U);
+  }
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR3 */
+  TIMx->CCMR3 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR5 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Output Compare 6 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The ouput configuration structure
+  * @retval None
+  */
+static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
+                              TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Disable the output: Reset the CCxE Bit */
+  TIMx->CCER &= ~TIM_CCER_CC6E;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR3;
+
+  /* Reset the Output Compare Mode Bits */
+  tmpccmrx &= ~(TIM_CCMR3_OC6M);
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (OC_Config->OCMode << 8U);
+
+  /* Reset the Output Polarity level */
+  tmpccer &= (uint32_t)~TIM_CCER_CC6P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 20U);
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Reset the Output Compare IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS6;
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 10U);
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR3 */
+  TIMx->CCMR3 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR6 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Slave Timer configuration function
+  * @param  htim TIM handle
+  * @param  sSlaveConfig Slave timer configuration
+  * @retval None
+  */
+static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+                                                  TIM_SlaveConfigTypeDef *sSlaveConfig)
+{
+  uint32_t tmpsmcr;
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = htim->Instance->SMCR;
+
+  /* Reset the Trigger Selection Bits */
+  tmpsmcr &= ~TIM_SMCR_TS;
+  /* Set the Input Trigger source */
+  tmpsmcr |= sSlaveConfig->InputTrigger;
+
+  /* Reset the slave mode Bits */
+  tmpsmcr &= ~TIM_SMCR_SMS;
+  /* Set the slave mode */
+  tmpsmcr |= sSlaveConfig->SlaveMode;
+
+  /* Write to TIMx SMCR */
+  htim->Instance->SMCR = tmpsmcr;
+
+  /* Configure the trigger prescaler, filter, and polarity */
+  switch (sSlaveConfig->InputTrigger)
+  {
+    case TIM_TS_ETRF:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
+      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+      /* Configure the ETR Trigger source */
+      TIM_ETR_SetConfig(htim->Instance,
+                        sSlaveConfig->TriggerPrescaler,
+                        sSlaveConfig->TriggerPolarity,
+                        sSlaveConfig->TriggerFilter);
+      break;
+    }
+
+    case TIM_TS_TI1F_ED:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+      if(sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Disable the Channel 1: Reset the CC1E Bit */
+      tmpccer = htim->Instance->CCER;
+      htim->Instance->CCER &= ~TIM_CCER_CC1E;
+      tmpccmr1 = htim->Instance->CCMR1;
+
+      /* Set the filter */
+      tmpccmr1 &= ~TIM_CCMR1_IC1F;
+      tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
+
+      /* Write to TIMx CCMR1 and CCER registers */
+      htim->Instance->CCMR1 = tmpccmr1;
+      htim->Instance->CCER = tmpccer;
+      break;
+    }
+
+    case TIM_TS_TI1FP1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+      /* Configure TI1 Filter and Polarity */
+      TIM_TI1_ConfigInputStage(htim->Instance,
+                               sSlaveConfig->TriggerPolarity,
+                               sSlaveConfig->TriggerFilter);
+      break;
+    }
+
+    case TIM_TS_TI2FP2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+      /* Configure TI2 Filter and Polarity */
+      TIM_TI2_ConfigInputStage(htim->Instance,
+                               sSlaveConfig->TriggerPolarity,
+                               sSlaveConfig->TriggerFilter);
+      break;
+    }
+
+    case TIM_TS_ITR0:
+    case TIM_TS_ITR1:
+    case TIM_TS_ITR2:
+    case TIM_TS_ITR3:
+    case TIM_TS_ITR4:
+    case TIM_TS_ITR5:
+    case TIM_TS_ITR6:
+    case TIM_TS_ITR7:
+    case TIM_TS_ITR8:
+    case TIM_TS_ITR9:
+    case TIM_TS_ITR10:
+    case TIM_TS_ITR11:
+    case TIM_TS_ITR12:
+    case TIM_TS_ITR13:
+    {
+      /* Check the parameter */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+      break;
+    }
+
+    default:
+      break;
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the TI1 as Input.
+  * @param  TIMx to select the TIM peripheral.
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICSelection specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
+  *       (on channel2 path) is used as the input signal. Therefore CCMR1 must be
+  *        protected against un-initialized filter and polarity values.
+  */
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                       uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+  tmpccmr1 = TIMx->CCMR1;
+  tmpccer = TIMx->CCER;
+
+  /* Select the Input */
+  if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
+  {
+    tmpccmr1 &= ~TIM_CCMR1_CC1S;
+    tmpccmr1 |= TIM_ICSelection;
+  }
+  else
+  {
+    tmpccmr1 |= TIM_CCMR1_CC1S_0;
+  }
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC1F;
+  tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
+
+  /* Select the Polarity and set the CC1E Bit */
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+  tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the Polarity and Filter for TI1.
+  * @param  TIMx to select the TIM peripheral.
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  tmpccer = TIMx->CCER;
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC1F;
+  tmpccmr1 |= (TIM_ICFilter << 4U);
+
+  /* Select the Polarity and set the CC1E Bit */
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+  tmpccer |= TIM_ICPolarity;
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI2 as Input.
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICSelection specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
+  *       (on channel1 path) is used as the input signal. Therefore CCMR1 must be
+  *        protected against un-initialized filter and polarity values.
+  */
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+  tmpccmr1 = TIMx->CCMR1;
+  tmpccer = TIMx->CCER;
+
+  /* Select the Input */
+  tmpccmr1 &= ~TIM_CCMR1_CC2S;
+  tmpccmr1 |= (TIM_ICSelection << 8U);
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC2F;
+  tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
+
+  /* Select the Polarity and set the CC2E Bit */
+  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+  tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1 ;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the Polarity and Filter for TI2.
+  * @param  TIMx to select the TIM peripheral.
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+  tmpccmr1 = TIMx->CCMR1;
+  tmpccer = TIMx->CCER;
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC2F;
+  tmpccmr1 |= (TIM_ICFilter << 12U);
+
+  /* Select the Polarity and set the CC2E Bit */
+  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+  tmpccer |= (TIM_ICPolarity << 4U);
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1 ;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI3 as Input.
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICSelection specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
+  *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+  *        protected against un-initialized filter and polarity values.
+  */
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr2;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 3: Reset the CC3E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC3E;
+  tmpccmr2 = TIMx->CCMR2;
+  tmpccer = TIMx->CCER;
+
+  /* Select the Input */
+  tmpccmr2 &= ~TIM_CCMR2_CC3S;
+  tmpccmr2 |= TIM_ICSelection;
+
+  /* Set the filter */
+  tmpccmr2 &= ~TIM_CCMR2_IC3F;
+  tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
+
+  /* Select the Polarity and set the CC3E Bit */
+  tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
+  tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
+
+  /* Write to TIMx CCMR2 and CCER registers */
+  TIMx->CCMR2 = tmpccmr2;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI4 as Input.
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICSelection specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
+  *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+  *        protected against un-initialized filter and polarity values.
+  * @retval None
+  */
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr2;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 4: Reset the CC4E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC4E;
+  tmpccmr2 = TIMx->CCMR2;
+  tmpccer = TIMx->CCER;
+
+  /* Select the Input */
+  tmpccmr2 &= ~TIM_CCMR2_CC4S;
+  tmpccmr2 |= (TIM_ICSelection << 8U);
+
+  /* Set the filter */
+  tmpccmr2 &= ~TIM_CCMR2_IC4F;
+  tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
+
+  /* Select the Polarity and set the CC4E Bit */
+  tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
+  tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
+
+  /* Write to TIMx CCMR2 and CCER registers */
+  TIMx->CCMR2 = tmpccmr2;
+  TIMx->CCER = tmpccer ;
+}
+
+/**
+  * @brief  Selects the Input Trigger source
+  * @param  TIMx to select the TIM peripheral
+  * @param  InputTriggerSource The Input Trigger source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal Trigger 0
+  *            @arg TIM_TS_ITR1: Internal Trigger 1
+  *            @arg TIM_TS_ITR2: Internal Trigger 2
+  *            @arg TIM_TS_ITR3: Internal Trigger 3
+  *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
+  *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
+  *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
+  *            @arg TIM_TS_ETRF: External Trigger input
+  *            @arg TIM_TS_ITR4: Internal Trigger 4  (*)
+  *            @arg TIM_TS_ITR5: Internal Trigger 5
+  *            @arg TIM_TS_ITR6: Internal Trigger 6
+  *            @arg TIM_TS_ITR7: Internal Trigger 7
+  *            @arg TIM_TS_ITR8: Internal Trigger 8  (*)
+  *            @arg TIM_TS_ITR9: Internal Trigger 9  (*)
+  *            @arg TIM_TS_ITR10: Internal Trigger 10 (*)
+  *            @arg TIM_TS_ITR11: Internal Trigger 11 (*)
+  *            @arg TIM_TS_ITR12: Internal Trigger 12 (*)
+  *            @arg TIM_TS_ITR13: Internal Trigger 13 (*)
+  *
+  *       (*)  Value not defined in all devices.
+  *
+  * @retval None
+  */
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
+{
+  uint32_t tmpsmcr;
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = TIMx->SMCR;
+  /* Reset the TS Bits */
+  tmpsmcr &= ~TIM_SMCR_TS;
+  /* Set the Input Trigger source and the slave mode*/
+  tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+}
+/**
+  * @brief  Configures the TIMx External Trigger (ETR).
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ExtTRGPrescaler The external Trigger Prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
+  *            @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
+  *            @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
+  *            @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
+  * @param  TIM_ExtTRGPolarity The external Trigger Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
+  *            @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
+  * @param  ExtTRGFilter External Trigger Filter.
+  *          This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
+                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
+{
+  uint32_t tmpsmcr;
+
+  tmpsmcr = TIMx->SMCR;
+
+  /* Reset the ETR Bits */
+  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+
+  /* Set the Prescaler, the Filter value and the Polarity */
+  tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
+
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+}
+
+/**
+  * @brief  Enables or disables the TIM Capture Compare Channel x.
+  * @param  TIMx to select the TIM peripheral
+  * @param  Channel specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1
+  *            @arg TIM_CHANNEL_2: TIM Channel 2
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  *            @arg TIM_CHANNEL_4: TIM Channel 4
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @param  ChannelState specifies the TIM Channel CCxE bit new state.
+  *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
+  * @retval None
+  */
+void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
+{
+  uint32_t tmp;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+  assert_param(IS_TIM_CHANNELS(Channel));
+
+  tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
+
+  /* Reset the CCxE Bit */
+  TIMx->CCER &= ~tmp;
+
+  /* Set or reset the CCxE Bit */
+  TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
+}
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Reset interrupt callbacks to the legacy weak callbacks.
+  * @param  htim pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval None
+  */
+void TIM_ResetCallback(TIM_HandleTypeDef *htim)
+{
+  /* Reset the TIM callback to the legacy weak callbacks */
+  htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;             /* Legacy weak PeriodElapsedCallback             */
+  htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;     /* Legacy weak PeriodElapsedHalfCpltCallback     */
+  htim->TriggerCallback                   = HAL_TIM_TriggerCallback;                   /* Legacy weak TriggerCallback                   */
+  htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;           /* Legacy weak TriggerHalfCpltCallback           */
+  htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;                /* Legacy weak IC_CaptureCallback                */
+  htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;        /* Legacy weak IC_CaptureHalfCpltCallback        */
+  htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;           /* Legacy weak OC_DelayElapsedCallback           */
+  htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;         /* Legacy weak PWM_PulseFinishedCallback         */
+  htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */
+  htim->ErrorCallback                     = HAL_TIM_ErrorCallback;                     /* Legacy weak ErrorCallback                     */
+  htim->CommutationCallback               = HAL_TIMEx_CommutCallback;                  /* Legacy weak CommutationCallback               */
+  htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;          /* Legacy weak CommutationHalfCpltCallback       */
+  htim->BreakCallback                     = HAL_TIMEx_BreakCallback;                   /* Legacy weak BreakCallback                     */
+  htim->Break2Callback                    = HAL_TIMEx_Break2Callback;                  /* Legacy weak Break2Callback                    */
+}
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_TIM_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c
new file mode 100644
index 00000000..1dcd7704
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c
@@ -0,0 +1,2324 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_tim_ex.c
+  * @author  MCD Application Team
+  * @brief   TIM HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Timer Extended peripheral:
+  *           + Time Hall Sensor Interface Initialization
+  *           + Time Hall Sensor Interface Start
+  *           + Time Complementary signal break and dead time configuration
+  *           + Time Master and Slave synchronization configuration
+  *           + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
+  *           + Timer remapping capabilities configuration
+  @verbatim
+  ==============================================================================
+                      ##### TIMER Extended features #####
+  ==============================================================================
+  [..]
+    The Timer Extended features include:
+    (#) Complementary outputs with programmable dead-time for :
+        (++) Output Compare
+        (++) PWM generation (Edge and Center-aligned Mode)
+        (++) One-pulse mode output
+    (#) Synchronization circuit to control the timer with external signals and to
+        interconnect several timers together.
+    (#) Break input to put the timer output signals in reset state or in a known state.
+    (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
+        positioning purposes
+
+            ##### How to use this driver #####
+  ==============================================================================
+    [..]
+     (#) Initialize the TIM low level resources by implementing the following functions
+         depending on the selected feature:
+           (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
+
+     (#) Initialize the TIM low level resources :
+        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
+        (##) TIM pins configuration
+            (+++) Enable the clock for the TIM GPIOs using the following function:
+              __HAL_RCC_GPIOx_CLK_ENABLE();
+            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
+
+     (#) The external Clock can be configured, if needed (the default clock is the
+         internal clock from the APBx), using the following function:
+         HAL_TIM_ConfigClockSource, the clock configuration should be done before
+         any start function.
+
+     (#) Configure the TIM in the desired functioning mode using one of the
+         initialization function of this driver:
+          (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the
+               Timer Hall Sensor Interface and the commutation event with the corresponding
+               Interrupt and DMA request if needed (Note that One Timer is used to interface
+               with the Hall sensor Interface and another Timer should be used to use
+               the commutation event).
+
+     (#) Activate the TIM peripheral using one of the start functions:
+           (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()
+           (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
+           (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
+           (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup TIMEx TIMEx
+  * @brief TIM Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
+  * @brief    Timer Hall Sensor functions
+  *
+@verbatim
+  ==============================================================================
+                      ##### Timer Hall Sensor functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure TIM HAL Sensor.
+    (+) De-initialize TIM HAL Sensor.
+    (+) Start the Hall Sensor Interface.
+    (+) Stop the Hall Sensor Interface.
+    (+) Start the Hall Sensor Interface and enable interrupts.
+    (+) Stop the Hall Sensor Interface and disable interrupts.
+    (+) Start the Hall Sensor Interface and enable DMA transfers.
+    (+) Stop the Hall Sensor Interface and disable DMA transfers.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Hall Sensor Interface and initialize the associated handle.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @param  sConfig TIM Hall Sensor configuration structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
+{
+  TIM_OC_InitTypeDef OC_Config;
+
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+  assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+  assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy week callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->HallSensor_MspInitCallback == NULL)
+    {
+      htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->HallSensor_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIMEx_HallSensor_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Configure the Time base in the Encoder Mode */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the  Hall sensor */
+  TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
+
+  /* Reset the IC1PSC Bits */
+  htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+  /* Set the IC1PSC value */
+  htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
+
+  /* Enable the Hall sensor interface (XOR function of the three inputs) */
+  htim->Instance->CR2 |= TIM_CR2_TI1S;
+
+  /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
+  htim->Instance->SMCR &= ~TIM_SMCR_TS;
+  htim->Instance->SMCR |= TIM_TS_TI1F_ED;
+
+  /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
+  htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+  htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
+
+  /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
+  OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
+  OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
+  OC_Config.OCMode = TIM_OCMODE_PWM2;
+  OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
+  OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
+  OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
+  OC_Config.Pulse = sConfig->Commutation_Delay;
+
+  TIM_OC2_SetConfig(htim->Instance, &OC_Config);
+
+  /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
+    register to 101 */
+  htim->Instance->CR2 &= ~TIM_CR2_MMS;
+  htim->Instance->CR2 |= TIM_TRGO_OC2REF;
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM Hall Sensor interface
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->HallSensor_MspDeInitCallback == NULL)
+  {
+    htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->HallSensor_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIMEx_HallSensor_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Hall Sensor MSP.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Hall Sensor MSP.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Hall Sensor Interface.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Enable the Input Capture channel 1
+    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Hall sensor Interface.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channels 1, 2 and 3
+    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Hall Sensor Interface in interrupt mode.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Enable the capture compare Interrupts 1 event */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+  /* Enable the Input Capture channel 1
+    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Hall Sensor Interface in interrupt mode.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channel 1
+    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+  /* Disable the capture compare Interrupts event */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Hall Sensor Interface in DMA mode.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @param  pData The destination Buffer address.
+  * @param  Length The length of data to be transferred from TIM peripheral to memory.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if (((uint32_t)pData == 0U) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+  /* Enable the Input Capture channel 1
+    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+  /* Set the DMA Input Capture 1 Callbacks */
+  htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+  htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+  /* Set the DMA error callback */
+  htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+  /* Enable the DMA stream for Capture 1*/
+  if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  /* Enable the capture compare 1 Interrupt */
+  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Hall Sensor Interface in DMA mode.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channel 1
+    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+
+  /* Disable the capture compare Interrupts 1 event */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+
+  (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
+  *  @brief   Timer Complementary Output Compare functions
+  *
+@verbatim
+  ==============================================================================
+              ##### Timer Complementary Output Compare functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Start the Complementary Output Compare/PWM.
+    (+) Stop the Complementary Output Compare/PWM.
+    (+) Start the Complementary Output Compare/PWM and enable interrupts.
+    (+) Stop the Complementary Output Compare/PWM and disable interrupts.
+    (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
+    (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation on the complementary
+  *         output.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Enable the Capture compare channel N */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation on the complementary
+  *         output.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the Capture compare channel N */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in interrupt mode
+  *         on the complementary output.
+  * @param  htim TIM OC handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Output Compare interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Output Compare interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Output Compare interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+
+    default:
+      break;
+  }
+
+  /* Enable the TIM Break interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+
+  /* Enable the Capture compare channel N */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in interrupt mode
+  *         on the complementary output.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpccer;
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Output Compare interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Output Compare interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Output Compare interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Disable the Capture compare channel N */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+  /* Disable the TIM Break interrupt (only if no more channel is active) */
+  tmpccer = htim->Instance->CCER;
+  if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
+  {
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+  }
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in DMA mode
+  *         on the complementary output.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if (((uint32_t)pData == 0U) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do  */
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Output Compare DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Output Compare DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Output Compare DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Enable the Capture compare channel N */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in DMA mode
+  *         on the complementary output.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Output Compare DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Output Compare DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Output Compare DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Disable the Capture compare channel N */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
+  * @brief    Timer Complementary PWM functions
+  *
+@verbatim
+  ==============================================================================
+                 ##### Timer Complementary PWM functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Start the Complementary PWM.
+    (+) Stop the Complementary PWM.
+    (+) Start the Complementary PWM and enable interrupts.
+    (+) Stop the Complementary PWM and disable interrupts.
+    (+) Start the Complementary PWM and enable DMA transfers.
+    (+) Stop the Complementary PWM and disable DMA transfers.
+    (+) Start the Complementary Input Capture measurement.
+    (+) Stop the Complementary Input Capture.
+    (+) Start the Complementary Input Capture and enable interrupts.
+    (+) Stop the Complementary Input Capture and disable interrupts.
+    (+) Start the Complementary Input Capture and enable DMA transfers.
+    (+) Stop the Complementary Input Capture and disable DMA transfers.
+    (+) Start the Complementary One Pulse generation.
+    (+) Stop the Complementary One Pulse.
+    (+) Start the Complementary One Pulse and enable interrupts.
+    (+) Stop the Complementary One Pulse and disable interrupts.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the PWM signal generation on the complementary output.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Enable the complementary PWM output  */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the PWM signal generation on the complementary output.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the complementary PWM output  */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the PWM signal generation in interrupt mode on the
+  *         complementary output.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Enable the TIM Break interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+
+  /* Enable the complementary PWM output  */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the PWM signal generation in interrupt mode on the
+  *         complementary output.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpccer;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Disable the complementary PWM output  */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+  /* Disable the TIM Break interrupt (only if no more channel is active) */
+  tmpccer = htim->Instance->CCER;
+  if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
+  {
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+  }
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM PWM signal generation in DMA mode on the
+  *         complementary output
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if (((uint32_t)pData == 0U) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Enable the complementary PWM output  */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM PWM signal generation in DMA mode on the complementary
+  *         output
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Disable the complementary PWM output */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
+  * @brief    Timer Complementary One Pulse functions
+  *
+@verbatim
+  ==============================================================================
+                ##### Timer Complementary One Pulse functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Start the Complementary One Pulse generation.
+    (+) Stop the Complementary One Pulse.
+    (+) Start the Complementary One Pulse and enable interrupts.
+    (+) Stop the Complementary One Pulse and disable interrupts.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation on the complementary
+  *         output.
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+  /* Enable the complementary One Pulse output */
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM One Pulse signal generation on the complementary
+  *         output.
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+  /* Disable the complementary One Pulse output */
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation in interrupt mode on the
+  *         complementary channel.
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+  /* Enable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+  /* Enable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+
+  /* Enable the complementary One Pulse output */
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM One Pulse signal generation in interrupt mode on the
+  *         complementary channel.
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+  /* Disable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+  /* Disable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+
+  /* Disable the complementary One Pulse output */
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
+  * @brief    Peripheral Control functions
+  *
+@verbatim
+  ==============================================================================
+                    ##### Peripheral Control functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+      (+) Configure the commutation event in case of use of the Hall sensor interface.
+      (+) Configure Output channels for OC and PWM mode.
+
+      (+) Configure Complementary channels, break features and dead time.
+      (+) Configure Master synchronization.
+      (+) Configure timer remapping capabilities.
+      (+) Select timer input source.
+      (+) Enable or disable channel grouping.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the TIM commutation event sequence.
+  * @note  This function is mandatory to use the commutation event in order to
+  *        update the configuration at each commutation detection on the TRGI input of the Timer,
+  *        the typical use of this feature is with the use of another Timer(interface Timer)
+  *        configured in Hall sensor interface, this interface Timer will generate the
+  *        commutation at its TRGO output (connected to Timer used in this function) each time
+  *        the TI1 of the Interface Timer detect a commutation at its input TI1.
+  * @param  htim TIM handle
+  * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal trigger 0 selected
+  *            @arg TIM_TS_ITR1: Internal trigger 1 selected
+  *            @arg TIM_TS_ITR2: Internal trigger 2 selected
+  *            @arg TIM_TS_ITR3: Internal trigger 3 selected
+  *            @arg TIM_TS_ITR12: Internal trigger 12 selected (*)
+  *            @arg TIM_TS_ITR13: Internal trigger 13 selected (*)
+  *            @arg TIM_TS_NONE: No trigger is needed
+  * @param  CommutationSource the Commutation Event source
+  *          This parameter can be one of the following values:
+  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                              uint32_t  CommutationSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
+      (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
+      (InputTrigger == TIM_TS_ITR12)  || (InputTrigger == TIM_TS_ITR13))
+  {
+    /* Select the Input trigger */
+    htim->Instance->SMCR &= ~TIM_SMCR_TS;
+    htim->Instance->SMCR |= InputTrigger;
+  }
+
+  /* Select the Capture Compare preload feature */
+  htim->Instance->CR2 |= TIM_CR2_CCPC;
+  /* Select the Commutation event source */
+  htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+  htim->Instance->CR2 |= CommutationSource;
+
+  /* Disable Commutation Interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
+
+  /* Disable Commutation DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the TIM commutation event sequence with interrupt.
+  * @note  This function is mandatory to use the commutation event in order to
+  *        update the configuration at each commutation detection on the TRGI input of the Timer,
+  *        the typical use of this feature is with the use of another Timer(interface Timer)
+  *        configured in Hall sensor interface, this interface Timer will generate the
+  *        commutation at its TRGO output (connected to Timer used in this function) each time
+  *        the TI1 of the Interface Timer detect a commutation at its input TI1.
+  * @param  htim TIM handle
+  * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal trigger 0 selected
+  *            @arg TIM_TS_ITR1: Internal trigger 1 selected
+  *            @arg TIM_TS_ITR2: Internal trigger 2 selected
+  *            @arg TIM_TS_ITR3: Internal trigger 3 selected
+  *            @arg TIM_TS_ITR2: Internal trigger 12 selected (*)
+  *            @arg TIM_TS_ITR3: Internal trigger 13 selected (*)
+  *            @arg TIM_TS_NONE: No trigger is needed
+  * @param  CommutationSource the Commutation Event source
+  *          This parameter can be one of the following values:
+  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                                 uint32_t  CommutationSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
+      (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
+      (InputTrigger == TIM_TS_ITR12)  || (InputTrigger == TIM_TS_ITR13))
+  {
+    /* Select the Input trigger */
+    htim->Instance->SMCR &= ~TIM_SMCR_TS;
+    htim->Instance->SMCR |= InputTrigger;
+  }
+
+  /* Select the Capture Compare preload feature */
+  htim->Instance->CR2 |= TIM_CR2_CCPC;
+  /* Select the Commutation event source */
+  htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+  htim->Instance->CR2 |= CommutationSource;
+
+  /* Disable Commutation DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
+
+  /* Enable the Commutation Interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the TIM commutation event sequence with DMA.
+  * @note  This function is mandatory to use the commutation event in order to
+  *        update the configuration at each commutation detection on the TRGI input of the Timer,
+  *        the typical use of this feature is with the use of another Timer(interface Timer)
+  *        configured in Hall sensor interface, this interface Timer will generate the
+  *        commutation at its TRGO output (connected to Timer used in this function) each time
+  *        the TI1 of the Interface Timer detect a commutation at its input TI1.
+  * @note  The user should configure the DMA in his own software, in This function only the COMDE bit is set
+  * @param  htim TIM handle
+  * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal trigger 0 selected
+  *            @arg TIM_TS_ITR1: Internal trigger 1 selected
+  *            @arg TIM_TS_ITR2: Internal trigger 2 selected
+  *            @arg TIM_TS_ITR3: Internal trigger 3 selected
+  *            @arg TIM_TS_ITR2: Internal trigger 12 selected (*)
+  *            @arg TIM_TS_ITR3: Internal trigger 13 selected (*)
+  *            @arg TIM_TS_NONE: No trigger is needed
+  *
+  *         (*)  Value not defined in all devices.
+  *
+  * @param  CommutationSource the Commutation Event source
+  *          This parameter can be one of the following values:
+  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                                  uint32_t  CommutationSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
+      (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
+      (InputTrigger == TIM_TS_ITR12)  || (InputTrigger == TIM_TS_ITR13))
+  {
+    /* Select the Input trigger */
+    htim->Instance->SMCR &= ~TIM_SMCR_TS;
+    htim->Instance->SMCR |= InputTrigger;
+  }
+
+  /* Select the Capture Compare preload feature */
+  htim->Instance->CR2 |= TIM_CR2_CCPC;
+  /* Select the Commutation event source */
+  htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+  htim->Instance->CR2 |= CommutationSource;
+
+  /* Enable the Commutation DMA Request */
+  /* Set the DMA Commutation Callback */
+  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
+  /* Set the DMA error callback */
+  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
+
+  /* Disable Commutation Interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
+
+  /* Enable the Commutation DMA Request */
+  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the TIM in master mode.
+  * @param  htim TIM handle.
+  * @param  sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
+  *         contains the selected trigger output (TRGO) and the Master/Slave
+  *         mode.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+                                                        TIM_MasterConfigTypeDef *sMasterConfig)
+{
+  uint32_t tmpcr2;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
+  assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
+
+  /* Check input state */
+  __HAL_LOCK(htim);
+
+  /* Change the handler state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = htim->Instance->CR2;
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = htim->Instance->SMCR;
+
+  /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
+  if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
+  {
+    /* Check the parameters */
+    assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
+
+    /* Clear the MMS2 bits */
+    tmpcr2 &= ~TIM_CR2_MMS2;
+    /* Select the TRGO2 source*/
+    tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
+  }
+
+  /* Reset the MMS Bits */
+  tmpcr2 &= ~TIM_CR2_MMS;
+  /* Select the TRGO source */
+  tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
+
+  /* Update TIMx CR2 */
+  htim->Instance->CR2 = tmpcr2;
+
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    /* Reset the MSM Bit */
+    tmpsmcr &= ~TIM_SMCR_MSM;
+    /* Set master mode */
+    tmpsmcr |= sMasterConfig->MasterSlaveMode;
+
+    /* Update TIMx SMCR */
+    htim->Instance->SMCR = tmpsmcr;
+  }
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the Break feature, dead time, Lock level, OSSI/OSSR State
+  *         and the AOE(automatic output enable).
+  * @param  htim TIM handle
+  * @param  sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
+  *         contains the BDTR Register configuration  information for the TIM peripheral.
+  * @note   Interrupts can be generated when an active level is detected on the
+  *         break input, the break 2 input or the system break input. Break
+  *         interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
+                                                TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
+{
+  /* Keep this variable initialized to 0 as it is used to configure BDTR register */
+  uint32_t tmpbdtr = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
+  assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
+  assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
+  assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
+  assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
+  assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
+  assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
+  assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
+
+  /* Check input state */
+  __HAL_LOCK(htim);
+
+  /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
+     the OSSI State, the dead time value and the Automatic Output Enable Bit */
+
+  /* Set the BDTR bits */
+  MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
+
+  if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
+  {
+    /* Check the parameters */
+    assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
+    assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
+    assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
+
+    /* Set the BREAK2 input related BDTR bits */
+    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
+    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
+    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
+  }
+
+  /* Set TIMx_BDTR */
+  htim->Instance->BDTR = tmpbdtr;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+#if defined(TIM_BREAK_INPUT_SUPPORT)
+
+/**
+  * @brief  Configures the break input source.
+  * @param  htim TIM handle.
+  * @param  BreakInput Break input to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_BREAKINPUT_BRK: Timer break input
+  *            @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
+  * @param  sBreakInputConfig Break input source configuration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
+                                             uint32_t BreakInput,
+                                             TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
+
+{
+  uint32_t tmporx;
+  uint32_t bkin_enable_mask;
+  uint32_t bkin_polarity_mask;
+  uint32_t bkin_enable_bitpos;
+  uint32_t bkin_polarity_bitpos;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_BREAKINPUT(BreakInput));
+  assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
+  assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
+  if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
+  {
+    assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
+  }
+
+  /* Check input state */
+  __HAL_LOCK(htim);
+
+  switch (sBreakInputConfig->Source)
+  {
+    case TIM_BREAKINPUTSOURCE_BKIN:
+    {
+      bkin_enable_mask = TIM1_AF1_BKINE;
+      bkin_enable_bitpos = TIM1_AF1_BKINE_Pos;
+      bkin_polarity_mask = TIM1_AF1_BKINP;
+      bkin_polarity_bitpos = TIM1_AF1_BKINP_Pos;
+      break;
+    }
+    case TIM_BREAKINPUTSOURCE_COMP1:
+    {
+      bkin_enable_mask = TIM1_AF1_BKCMP1E;
+      bkin_enable_bitpos = TIM1_AF1_BKCMP1E_Pos;
+      bkin_polarity_mask = TIM1_AF1_BKCMP1P;
+      bkin_polarity_bitpos = TIM1_AF1_BKCMP1P_Pos;
+      break;
+    }
+    case TIM_BREAKINPUTSOURCE_COMP2:
+    {
+      bkin_enable_mask = TIM1_AF1_BKCMP2E;
+      bkin_enable_bitpos = TIM1_AF1_BKCMP2E_Pos;
+      bkin_polarity_mask = TIM1_AF1_BKCMP2P;
+      bkin_polarity_bitpos = TIM1_AF1_BKCMP2P_Pos;
+      break;
+    }
+    case TIM_BREAKINPUTSOURCE_DFSDM1:
+    {
+      bkin_enable_mask = TIM1_AF1_BKDF1BK0E;
+      bkin_enable_bitpos = 8U;
+      bkin_polarity_mask = 0U;
+      bkin_polarity_bitpos = 0U;
+      break;
+    }
+
+    default:
+    {
+      bkin_enable_mask = 0U;
+      bkin_polarity_mask = 0U;
+      bkin_enable_bitpos = 0U;
+      bkin_polarity_bitpos = 0U;
+      break;
+    }
+  }
+
+  switch (BreakInput)
+  {
+    case TIM_BREAKINPUT_BRK:
+    {
+      /* Get the TIMx_AF1 register value */
+      tmporx = htim->Instance->AF1;
+
+      /* Enable the break input */
+      tmporx &= ~bkin_enable_mask;
+      tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
+
+      /* Set the break input polarity */
+      if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
+      {
+        tmporx &= ~bkin_polarity_mask;
+        tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
+      }
+
+      /* Set TIMx_AF1 */
+      htim->Instance->AF1 = tmporx;
+      break;
+    }
+    case TIM_BREAKINPUT_BRK2:
+    {
+      /* Get the TIMx_AF2 register value */
+      tmporx = htim->Instance->AF2;
+
+      /* Enable the break input */
+      tmporx &= ~bkin_enable_mask;
+      tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
+
+      /* Set the break input polarity */
+      if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
+      {
+        tmporx &= ~bkin_polarity_mask;
+        tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
+      }
+
+      /* Set TIMx_AF2 */
+      htim->Instance->AF2 = tmporx;
+      break;
+    }
+    default:
+      break;
+  }
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+#endif /*TIM_BREAK_INPUT_SUPPORT */
+
+/**
+  * @brief  Configures the TIMx Remapping input capabilities.
+  * @param  htim TIM handle.
+  * @param  Remap specifies the TIM remapping source.
+  *         For TIM1, the parameter is one of the following values:
+  *            @arg TIM_TIM1_ETR_GPIO:               TIM1_ETR is connected to GPIO
+  *            @arg TIM_TIM1_ETR_COMP1:              TIM1_ETR is connected to COMP1 output
+  *            @arg TIM_TIM1_ETR_COMP2:              TIM1_ETR is connected to COMP2 output
+  *            @arg TIM_TIM1_ETR_ADC1_AWD1:          TIM1_ETR is connected to ADC1 AWD1
+  *            @arg TIM_TIM1_ETR_ADC1_AWD2:          TIM1_ETR is connected to ADC1 AWD2
+  *            @arg TIM_TIM1_ETR_ADC1_AWD3:          TIM1_ETR is connected to ADC1 AWD3
+  *            @arg TIM_TIM1_ETR_ADC3_AWD1:          TIM1_ETR is connected to ADC3 AWD1
+  *            @arg TIM_TIM1_ETR_ADC3_AWD2:          TIM1_ETR is connected to ADC3 AWD2
+  *            @arg TIM_TIM1_ETR_ADC3_AWD3:          TIM1_ETR is connected to ADC3 AWD3
+  *
+  *         For TIM2, the parameter is one of the following values:
+  *            @arg TIM_TIM2_ETR_GPIO:               TIM2_ETR is connected to GPIO
+  *            @arg TIM_TIM2_ETR_COMP1:              TIM2_ETR is connected to COMP1 output
+  *            @arg TIM_TIM2_ETR_COMP2:              TIM2_ETR is connected to COMP2 output
+  *            @arg TIM_TIM2_ETR_LSE:                TIM2_ETR is connected to LSE
+  *            @arg TIM_TIM2_ETR_SAI1_FSA:           TIM2_ETR is connected to SAI1 FS_A
+  *            @arg TIM_TIM2_ETR_SAI1_FSB:           TIM2_ETR is connected to SAI1 FS_B
+  *
+  *         For TIM3, the parameter is one of the following values:
+  *            @arg TIM_TIM3_ETR_GPIO:               TIM3_ETR is connected to GPIO
+  *            @arg TIM_TIM3_ETR_COMP1:              TIM3_ETR is connected to COMP1 output
+  *
+  *         For TIM5, the parameter is one of the following values:
+  *            @arg TIM_TIM5_ETR_GPIO:               TIM5_ETR is connected to GPIO
+  *            @arg TIM_TIM5_ETR_SAI2_FSA:           TIM5_ETR is connected to SAI2 FS_A (*)
+  *            @arg TIM_TIM5_ETR_SAI2_FSB:           TIM5_ETR is connected to SAI2 FS_B (*)
+  *            @arg TIM_TIM5_ETR_SAI4_FSA:           TIM5_ETR is connected to SAI2 FS_A (*)
+  *            @arg TIM_TIM5_ETR_SAI4_FSB:           TIM5_ETR is connected to SAI2 FS_B (*)
+  *
+  *         For TIM8, the parameter is one of the following values:
+  *            @arg TIM_TIM8_ETR_GPIO:               TIM8_ETR is connected to GPIO
+  *            @arg TIM_TIM8_ETR_COMP1:              TIM8_ETR is connected to COMP1 output
+  *            @arg TIM_TIM8_ETR_COMP2:              TIM8_ETR is connected to COMP2 output
+  *            @arg TIM_TIM8_ETR_ADC2_AWD1:          TIM8_ETR is connected to ADC2 AWD1
+  *            @arg TIM_TIM8_ETR_ADC2_AWD2:          TIM8_ETR is connected to ADC2 AWD2
+  *            @arg TIM_TIM8_ETR_ADC2_AWD3:          TIM8_ETR is connected to ADC2 AWD3
+  *            @arg TIM_TIM8_ETR_ADC3_AWD1:          TIM8_ETR is connected to ADC3 AWD1
+  *            @arg TIM_TIM8_ETR_ADC3_AWD2:          TIM8_ETR is connected to ADC3 AWD2
+  *            @arg TIM_TIM8_ETR_ADC3_AWD3:          TIM8_ETR is connected to ADC3 AWD3
+  *
+  *         For TIM23, the parameter is one of the following values: (*)
+  *            @arg TIM_TIM23_ETR_GPIO               TIM23_ETR is connected to GPIO
+  *            @arg TIM_TIM23_ETR_COMP1              TIM23_ETR is connected to COMP1 output
+  *            @arg TIM_TIM23_ETR_COMP2              TIM23_ETR is connected to COMP2 output
+  *
+  *         For TIM24, the parameter is one of the following values: (*)
+  *           @arg TIM_TIM24_ETR_GPIO                TIM24_ETR is connected to GPIO
+  *           @arg TIM_TIM24_ETR_SAI4_FSA            TIM24_ETR is connected to SAI4 FS_A
+  *           @arg TIM_TIM24_ETR_SAI4_FSB            TIM24_ETR is connected to SAI4 FS_B
+  *           @arg TIM_TIM24_ETR_SAI1_FSA            TIM24_ETR is connected to SAI1 FS_A
+  *           @arg TIM_TIM24_ETR_SAI1_FSB            TIM24_ETR is connected to SAI1 FS_B
+  *
+  *         (*)  Value not defined in all devices.
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
+{
+  /* Check parameters */
+  assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_REMAP(Remap));
+
+  __HAL_LOCK(htim);
+
+  MODIFY_REG(htim->Instance->AF1, TIM1_AF1_ETRSEL_Msk, Remap);
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Select the timer input source
+  * @param  htim TIM handle.
+  * @param  Channel specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TI1 input channel
+  *            @arg TIM_CHANNEL_2: TI2 input channel
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  *            @arg TIM_CHANNEL_4: TIM Channel 4
+  * @param  TISelection parameter of the TIM_TISelectionStruct structure is detailed as follows:
+  *         For TIM1, the parameter is one of the following values:
+  *            @arg TIM_TIM1_TI1_GPIO:                TIM1 TI1 is connected to GPIO
+  *            @arg TIM_TIM1_TI1_COMP1:               TIM1 TI1 is connected to COMP1 output
+  *
+  *         For TIM2, the parameter is one of the following values:
+  *            @arg TIM_TIM2_TI4_GPIO:                TIM2 TI4 is connected to GPIO
+  *            @arg TIM_TIM2_TI4_COMP1:               TIM2 TI4 is connected to COMP1 output
+  *            @arg TIM_TIM2_TI4_COMP2:               TIM2 TI4 is connected to COMP2 output
+  *            @arg TIM_TIM2_TI4_COMP1_COMP2:         TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output
+  *
+  *         For TIM3, the parameter is one of the following values:
+  *            @arg TIM_TIM3_TI1_GPIO:                TIM3 TI1 is connected to GPIO
+  *            @arg TIM_TIM3_TI1_COMP1:               TIM3 TI1 is connected to COMP1 output
+  *            @arg TIM_TIM3_TI1_COMP2:               TIM3 TI1 is connected to COMP2 output
+  *            @arg TIM_TIM3_TI1_COMP1_COMP2:         TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output
+  *
+  *         For TIM5, the parameter is one of the following values:
+  *            @arg TIM_TIM5_TI1_GPIO:                TIM5 TI1 is connected to GPIO
+  *            @arg TIM_TIM5_TI1_CAN_TMP:             TIM5 TI1 is connected to CAN TMP
+  *            @arg TIM_TIM5_TI1_CAN_RTP:             TIM5 TI1 is connected to CAN RTP
+  *
+  *         For TIM8, the parameter is one of the following values:
+  *            @arg TIM_TIM8_TI1_GPIO:               TIM8 TI1 is connected to GPIO
+  *            @arg TIM_TIM8_TI1_COMP2:              TIM8 TI1 is connected to COMP2 output
+  *
+  *         For TIM12, the parameter can have the following values: (*)
+  *            @arg TIM_TIM12_TI1_GPIO:              TIM12 TI1 is connected to GPIO
+  *            @arg TIM_TIM12_TI1_SPDIF_FS:          TIM12 TI1 is connected to SPDIF FS
+  *
+  *         For TIM15, the parameter is one of the following values:
+  *            @arg TIM_TIM15_TI1_GPIO:              TIM15 TI1 is connected to GPIO
+  *            @arg TIM_TIM15_TI1_TIM2:              TIM15 TI1 is connected to TIM2 CH1
+  *            @arg TIM_TIM15_TI1_TIM3:              TIM15 TI1 is connected to TIM3 CH1
+  *            @arg TIM_TIM15_TI1_TIM4:              TIM15 TI1 is connected to TIM4 CH1
+  *            @arg TIM_TIM15_TI1_LSE:               TIM15 TI1 is connected to LSE
+  *            @arg TIM_TIM15_TI1_CSI:               TIM15 TI1 is connected to CSI
+  *            @arg TIM_TIM15_TI1_MCO2:              TIM15 TI1 is connected to MCO2
+  *            @arg TIM_TIM15_TI2_GPIO:              TIM15 TI2 is connected to GPIO
+  *            @arg TIM_TIM15_TI2_TIM2:              TIM15 TI2 is connected to TIM2 CH2
+  *            @arg TIM_TIM15_TI2_TIM3:              TIM15 TI2 is connected to TIM3 CH2
+  *            @arg TIM_TIM15_TI2_TIM4:              TIM15 TI2 is connected to TIM4 CH2
+  *
+  *         For TIM16, the parameter can have the following values:
+  *            @arg TIM_TIM16_TI1_GPIO:              TIM16 TI1 is connected to GPIO
+  *            @arg TIM_TIM16_TI1_LSI:               TIM16 TI1 is connected to LSI
+  *            @arg TIM_TIM16_TI1_LSE:               TIM16 TI1 is connected to LSE
+  *            @arg TIM_TIM16_TI1_RTC:               TIM16 TI1 is connected to RTC wakeup interrupt
+  *
+  *         For TIM17, the parameter can have the following values:
+  *            @arg TIM_TIM17_TI1_GPIO:              TIM17 TI1 is connected to GPIO
+  *            @arg TIM_TIM17_TI1_SPDIF_FS:          TIM17 TI1 is connected to SPDIF FS (*)
+  *            @arg TIM_TIM17_TI1_HSE_1MHZ:          TIM17 TI1 is connected to HSE 1MHz
+  *            @arg TIM_TIM17_TI1_MCO1:              TIM17 TI1 is connected to MCO1
+  *
+  *         For TIM23, the parameter can have the following values: (*)
+  *            @arg TIM_TIM23_TI4_GPIO               TIM23_TI4 is connected to GPIO
+  *            @arg TIM_TIM23_TI4_COMP1              TIM23_TI4 is connected to COMP1 output
+  *            @arg TIM_TIM23_TI4_COMP2              TIM23_TI4 is connected to COMP2 output
+  *            @arg TIM_TIM23_TI4_COMP1_COMP2        TIM23_TI4 is connected to COMP2 output
+  *
+  *         For TIM24, the parameter can have the following values: (*)
+  *            @arg TIM_TIM24_TI1_GPIO               TIM24_TI1 is connected to GPIO
+  *            @arg TIM_TIM24_TI1_CAN_TMP            TIM24_TI1 is connected to CAN_TMP
+  *            @arg TIM_TIM24_TI1_CAN_RTP            TIM24_TI1 is connected to CAN_RTP
+  *            @arg TIM_TIM24_TI1_CAN_SOC            TIM24_TI1 is connected to CAN_SOC
+  *
+  *         (*)  Value not defined in all devices. \n
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_TIM_TISEL_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_TISEL(TISelection));
+
+  __HAL_LOCK(htim);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+      MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI1SEL, TISelection);
+      break;
+    case TIM_CHANNEL_2:
+      MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI2SEL, TISelection);
+      break;
+    case TIM_CHANNEL_3:
+      MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI3SEL, TISelection);
+      break;
+    case TIM_CHANNEL_4:
+      MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI4SEL, TISelection);
+      break;
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+
+/**
+  * @brief  Group channel 5 and channel 1, 2 or 3
+  * @param  htim TIM handle.
+  * @param  Channels specifies the reference signal(s) the OC5REF is combined with.
+  *         This parameter can be any combination of the following values:
+  *         TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
+  *         TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
+  *         TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
+  *         TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)
+{
+  /* Check parameters */
+  assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_GROUPCH5(Channels));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Clear GC5Cx bit fields */
+  htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1);
+
+  /* Set GC5Cx bit fields */
+  htim->Instance->CCR5 |= Channels;
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
+  * @brief    Extended Callbacks functions
+  *
+@verbatim
+  ==============================================================================
+                    ##### Extended Callbacks functions #####
+  ==============================================================================
+  [..]
+    This section provides Extended TIM callback functions:
+    (+) Timer Commutation callback
+    (+) Timer Break callback
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Hall commutation changed callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_CommutCallback could be implemented in the user file
+   */
+}
+/**
+  * @brief  Hall commutation changed half complete callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Hall Break detection callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_BreakCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Hall Break2 detection callback in non blocking mode
+  * @param  htim: TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_TIMEx_Break2Callback could be implemented in the user file
+   */
+}
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
+  * @brief    Extended Peripheral State functions
+  *
+@verbatim
+  ==============================================================================
+                ##### Extended Peripheral State functions #####
+  ==============================================================================
+  [..]
+    This subsection permits to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the TIM Hall Sensor interface handle state.
+  * @param  htim TIM Hall Sensor handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
+  * @{
+  */
+
+/**
+  * @brief  TIM DMA Commutation callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->CommutationCallback(htim);
+#else
+  HAL_TIMEx_CommutCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Commutation half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->CommutationHalfCpltCallback(htim);
+#else
+  HAL_TIMEx_CommutHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+
+/**
+  * @brief  Enables or disables the TIM Capture Compare Channel xN.
+  * @param  TIMx to select the TIM peripheral
+  * @param  Channel specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1
+  *            @arg TIM_CHANNEL_2: TIM Channel 2
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  * @param  ChannelNState specifies the TIM Channel CCxNE bit new state.
+  *          This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
+  * @retval None
+  */
+static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
+{
+  uint32_t tmp;
+
+  tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
+
+  /* Reset the CCxNE Bit */
+  TIMx->CCER &=  ~tmp;
+
+  /* Set or reset the CCxNE Bit */
+  TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
+}
+/**
+  * @}
+  */
+
+#endif /* HAL_TIM_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c
new file mode 100644
index 00000000..85a0b6e8
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c
@@ -0,0 +1,4115 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_uart.c
+  * @author  MCD Application Team
+  * @brief   UART HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *
+  *
+  @verbatim
+ ===============================================================================
+                        ##### How to use this driver #####
+ ===============================================================================
+  [..]
+    The UART HAL driver can be used as follows:
+
+    (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).
+    (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
+        (++) Enable the USARTx interface clock.
+        (++) UART pins configuration:
+            (+++) Enable the clock for the UART GPIOs.
+            (+++) Configure these UART pins as alternate function pull-up.
+        (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
+             and HAL_UART_Receive_IT() APIs):
+            (+++) Configure the USARTx interrupt priority.
+            (+++) Enable the NVIC USART IRQ handle.
+        (++) UART interrupts handling:
+              -@@-  The specific UART interrupts (Transmission complete interrupt,
+                RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts)
+                are managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT()
+                inside the transmit and receive processes.
+        (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
+             and HAL_UART_Receive_DMA() APIs):
+            (+++) Declare a DMA handle structure for the Tx/Rx channel.
+            (+++) Enable the DMAx interface clock.
+            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+            (+++) Configure the DMA Tx/Rx channel.
+            (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
+            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
+
+    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Prescaler value , Hardware
+        flow control and Mode (Receiver/Transmitter) in the huart handle Init structure.
+
+    (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...)
+        in the huart handle AdvancedInit structure.
+
+    (#) For the UART asynchronous mode, initialize the UART registers by calling
+        the HAL_UART_Init() API.
+
+    (#) For the UART Half duplex mode, initialize the UART registers by calling
+        the HAL_HalfDuplex_Init() API.
+
+    (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers
+        by calling the HAL_LIN_Init() API.
+
+    (#) For the UART Multiprocessor mode, initialize the UART registers
+        by calling the HAL_MultiProcessor_Init() API.
+
+    (#) For the UART RS485 Driver Enabled mode, initialize the UART registers
+        by calling the HAL_RS485Ex_Init() API.
+
+    [..]
+    (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(),
+        also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by
+        calling the customized HAL_UART_MspInit() API.
+
+    ##### Callback registration #####
+    ==================================
+
+    [..]
+    The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1
+    allows the user to configure dynamically the driver callbacks.
+
+    [..]
+    Use Function @ref HAL_UART_RegisterCallback() to register a user callback.
+    Function @ref HAL_UART_RegisterCallback() allows to register following callbacks:
+    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
+    (+) TxCpltCallback            : Tx Complete Callback.
+    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
+    (+) RxCpltCallback            : Rx Complete Callback.
+    (+) ErrorCallback             : Error Callback.
+    (+) AbortCpltCallback         : Abort Complete Callback.
+    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
+    (+) WakeupCallback            : Wakeup Callback.
+    (+) RxFifoFullCallback        : Rx Fifo Full Callback.
+    (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
+    (+) MspInitCallback           : UART MspInit.
+    (+) MspDeInitCallback         : UART MspDeInit.
+    This function takes as parameters the HAL peripheral handle, the Callback ID
+    and a pointer to the user callback function.
+
+    [..]
+    Use function @ref HAL_UART_UnRegisterCallback() to reset a callback to the default
+    weak (surcharged) function.
+    @ref HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+    and the Callback ID.
+    This function allows to reset following callbacks:
+    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
+    (+) TxCpltCallback            : Tx Complete Callback.
+    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
+    (+) RxCpltCallback            : Rx Complete Callback.
+    (+) ErrorCallback             : Error Callback.
+    (+) AbortCpltCallback         : Abort Complete Callback.
+    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
+    (+) WakeupCallback            : Wakeup Callback.
+    (+) RxFifoFullCallback        : Rx Fifo Full Callback.
+    (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
+    (+) MspInitCallback           : UART MspInit.
+    (+) MspDeInitCallback         : UART MspDeInit.
+
+    [..]
+    By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET
+    all callbacks are set to the corresponding weak (surcharged) functions:
+    examples @ref HAL_UART_TxCpltCallback(), @ref HAL_UART_RxHalfCpltCallback().
+    Exception done for MspInit and MspDeInit functions that are respectively
+    reset to the legacy weak (surcharged) functions in the @ref HAL_UART_Init()
+    and @ref HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).
+    If not, MspInit or MspDeInit are not null, the @ref HAL_UART_Init() and @ref HAL_UART_DeInit()
+    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+    [..]
+    Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only.
+    Exception done MspInit/MspDeInit that can be registered/unregistered
+    in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user)
+    MspInit/DeInit callbacks can be used during the Init/DeInit.
+    In that case first register the MspInit/MspDeInit user callbacks
+    using @ref HAL_UART_RegisterCallback() before calling @ref HAL_UART_DeInit()
+    or @ref HAL_UART_Init() function.
+
+    [..]
+    When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or
+    not defined, the callback registration feature is not available
+    and weak (surcharged) callbacks are used.
+
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup UART UART
+  * @brief HAL UART module driver
+  * @{
+  */
+
+#ifdef HAL_UART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup UART_Private_Constants UART Private Constants
+  * @{
+  */
+#define USART_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
+                                      USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \
+                                      USART_CR1_FIFOEN ))                      /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */
+
+#define USART_CR3_FIELDS  ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT| \
+                                      USART_CR3_TXFTCFG | USART_CR3_RXFTCFG ))  /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */
+
+#define LPUART_BRR_MIN  0x00000300U  /* LPUART BRR minimum authorized value */
+#define LPUART_BRR_MAX  0x000FFFFFU  /* LPUART BRR maximum authorized value */
+
+#define UART_BRR_MIN    0x10U        /* UART BRR minimum authorized value */
+#define UART_BRR_MAX    0x0000FFFFU  /* UART BRR maximum authorized value */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup UART_Private_Functions
+  * @{
+  */
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMAError(DMA_HandleTypeDef *hdma);
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_TxISR_8BIT(UART_HandleTypeDef *huart);
+static void UART_TxISR_16BIT(UART_HandleTypeDef *huart);
+static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart);
+static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart);
+static void UART_EndTransmit_IT(UART_HandleTypeDef *huart);
+static void UART_RxISR_8BIT(UART_HandleTypeDef *huart);
+static void UART_RxISR_16BIT(UART_HandleTypeDef *huart);
+static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart);
+static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup UART_Exported_Functions UART Exported Functions
+  * @{
+  */
+
+/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
+    in asynchronous mode.
+      (+) For the asynchronous mode the parameters below can be configured:
+        (++) Baud Rate
+        (++) Word Length
+        (++) Stop Bit
+        (++) Parity: If the parity is enabled, then the MSB bit of the data written
+             in the data register is transmitted but is changed by the parity bit.
+        (++) Hardware flow control
+        (++) Receiver/transmitter modes
+        (++) Over Sampling Method
+        (++) One-Bit Sampling Method
+      (+) For the asynchronous mode, the following advanced features can be configured as well:
+        (++) TX and/or RX pin level inversion
+        (++) data logical level inversion
+        (++) RX and TX pins swap
+        (++) RX overrun detection disabling
+        (++) DMA disabling on RX error
+        (++) MSB first on communication line
+        (++) auto Baud rate detection
+    [..]
+    The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API
+    follow respectively the UART asynchronous, UART Half duplex, UART LIN mode
+    and UART multiprocessor mode configuration procedures (details for the procedures
+    are available in reference manual).
+
+@endverbatim
+
+  Depending on the frame length defined by the M1 and M0 bits (7-bit,
+  8-bit or 9-bit), the possible UART formats are listed in the
+  following table.
+
+  Table 1. UART frame format.
+    +-----------------------------------------------------------------------+
+    |  M1 bit |  M0 bit |  PCE bit  |             UART frame                |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
+    +-----------------------------------------------------------------------+
+
+  * @{
+  */
+
+/**
+  * @brief Initialize the UART mode according to the specified
+  *        parameters in the UART_InitTypeDef and initialize the associated handle.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
+  {
+    /* Check the parameters */
+    assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
+  }
+  else
+  {
+    /* Check the parameters */
+    assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
+  }
+
+  if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    UART_InitCallbacksToDefault(huart);
+
+    if (huart->MspInitCallback == NULL)
+    {
+      huart->MspInitCallback = HAL_UART_MspInit;
+    }
+
+    /* Init the low level hardware */
+    huart->MspInitCallback(huart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the UART Communication parameters */
+  if (UART_SetConfig(huart) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+  {
+    UART_AdvFeatureConfig(huart);
+  }
+
+  /* In asynchronous mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
+  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+
+  __HAL_UART_ENABLE(huart);
+
+  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+  return (UART_CheckIdleState(huart));
+}
+
+/**
+  * @brief Initialize the half-duplex mode according to the specified
+  *        parameters in the UART_InitTypeDef and creates the associated handle.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check UART instance */
+  assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));
+
+  if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    UART_InitCallbacksToDefault(huart);
+
+    if (huart->MspInitCallback == NULL)
+    {
+      huart->MspInitCallback = HAL_UART_MspInit;
+    }
+
+    /* Init the low level hardware */
+    huart->MspInitCallback(huart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the UART Communication parameters */
+  if (UART_SetConfig(huart) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+  {
+    UART_AdvFeatureConfig(huart);
+  }
+
+  /* In half-duplex mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - SCEN and IREN bits in the USART_CR3 register.*/
+  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));
+
+  /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
+  SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
+
+  __HAL_UART_ENABLE(huart);
+
+  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+  return (UART_CheckIdleState(huart));
+}
+
+
+/**
+  * @brief Initialize the LIN mode according to the specified
+  *        parameters in the UART_InitTypeDef and creates the associated handle.
+  * @param huart             UART handle.
+  * @param BreakDetectLength Specifies the LIN break detection length.
+  *        This parameter can be one of the following values:
+  *          @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection
+  *          @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the LIN UART instance */
+  assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
+  /* Check the Break detection length parameter */
+  assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
+
+  /* LIN mode limited to 16-bit oversampling only */
+  if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
+  {
+    return HAL_ERROR;
+  }
+  /* LIN mode limited to 8-bit data length */
+  if (huart->Init.WordLength != UART_WORDLENGTH_8B)
+  {
+    return HAL_ERROR;
+  }
+
+  if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    UART_InitCallbacksToDefault(huart);
+
+    if (huart->MspInitCallback == NULL)
+    {
+      huart->MspInitCallback = HAL_UART_MspInit;
+    }
+
+    /* Init the low level hardware */
+    huart->MspInitCallback(huart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the UART Communication parameters */
+  if (UART_SetConfig(huart) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+  {
+    UART_AdvFeatureConfig(huart);
+  }
+
+  /* In LIN mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - SCEN and IREN bits in the USART_CR3 register.*/
+  CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));
+
+  /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
+  SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);
+
+  /* Set the USART LIN Break detection length. */
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);
+
+  __HAL_UART_ENABLE(huart);
+
+  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+  return (UART_CheckIdleState(huart));
+}
+
+
+/**
+  * @brief Initialize the multiprocessor mode according to the specified
+  *        parameters in the UART_InitTypeDef and initialize the associated handle.
+  * @param huart        UART handle.
+  * @param Address      UART node address (4-, 6-, 7- or 8-bit long).
+  * @param WakeUpMethod Specifies the UART wakeup method.
+  *        This parameter can be one of the following values:
+  *          @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection
+  *          @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark
+  * @note  If the user resorts to idle line detection wake up, the Address parameter
+  *        is useless and ignored by the initialization function.
+  * @note  If the user resorts to address mark wake up, the address length detection
+  *        is configured by default to 4 bits only. For the UART to be able to
+  *        manage 6-, 7- or 8-bit long addresses detection, the API
+  *        HAL_MultiProcessorEx_AddressLength_Set() must be called after
+  *        HAL_MultiProcessor_Init().
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the wake up method parameter */
+  assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
+
+  if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    UART_InitCallbacksToDefault(huart);
+
+    if (huart->MspInitCallback == NULL)
+    {
+      huart->MspInitCallback = HAL_UART_MspInit;
+    }
+
+    /* Init the low level hardware */
+    huart->MspInitCallback(huart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the UART Communication parameters */
+  if (UART_SetConfig(huart) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+  {
+    UART_AdvFeatureConfig(huart);
+  }
+
+  /* In multiprocessor mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - SCEN, HDSEL and IREN  bits in the USART_CR3 register. */
+  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+
+  if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK)
+  {
+    /* If address mark wake up method is chosen, set the USART address node */
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS));
+  }
+
+  /* Set the wake up method by setting the WAKE bit in the CR1 register */
+  MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);
+
+  __HAL_UART_ENABLE(huart);
+
+  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+  return (UART_CheckIdleState(huart));
+}
+
+
+/**
+  * @brief DeInitialize the UART peripheral.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  __HAL_UART_DISABLE(huart);
+
+  huart->Instance->CR1 = 0x0U;
+  huart->Instance->CR2 = 0x0U;
+  huart->Instance->CR3 = 0x0U;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  if (huart->MspDeInitCallback == NULL)
+  {
+    huart->MspDeInitCallback = HAL_UART_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  huart->MspDeInitCallback(huart);
+#else
+  /* DeInit the low level hardware */
+  HAL_UART_MspDeInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+  huart->gState = HAL_UART_STATE_RESET;
+  huart->RxState = HAL_UART_STATE_RESET;
+
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Initialize the UART MSP.
+  * @param huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_MspInit can be implemented in the user file
+   */
+}
+
+/**
+  * @brief DeInitialize the UART MSP.
+  * @param huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_MspDeInit can be implemented in the user file
+   */
+}
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User UART Callback
+  *         To be used instead of the weak predefined callback
+  * @param  huart uart handle
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+  *           @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+  *           @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+  *           @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+  *           @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
+  *           @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+  *           @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+  *           @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+  *           @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
+  *           @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
+  *           @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
+  *           @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
+  *           @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
+                                            pUART_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  __HAL_LOCK(huart);
+
+  if (huart->gState == HAL_UART_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_UART_TX_HALFCOMPLETE_CB_ID :
+        huart->TxHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_TX_COMPLETE_CB_ID :
+        huart->TxCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_RX_HALFCOMPLETE_CB_ID :
+        huart->RxHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_RX_COMPLETE_CB_ID :
+        huart->RxCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_ERROR_CB_ID :
+        huart->ErrorCallback = pCallback;
+        break;
+
+      case HAL_UART_ABORT_COMPLETE_CB_ID :
+        huart->AbortCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
+        huart->AbortTransmitCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
+        huart->AbortReceiveCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_WAKEUP_CB_ID :
+        huart->WakeupCallback = pCallback;
+        break;
+
+      case HAL_UART_RX_FIFO_FULL_CB_ID :
+        huart->RxFifoFullCallback = pCallback;
+        break;
+
+      case HAL_UART_TX_FIFO_EMPTY_CB_ID :
+        huart->TxFifoEmptyCallback = pCallback;
+        break;
+
+      case HAL_UART_MSPINIT_CB_ID :
+        huart->MspInitCallback = pCallback;
+        break;
+
+      case HAL_UART_MSPDEINIT_CB_ID :
+        huart->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_UART_MSPINIT_CB_ID :
+        huart->MspInitCallback = pCallback;
+        break;
+
+      case HAL_UART_MSPDEINIT_CB_ID :
+        huart->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+    status =  HAL_ERROR;
+  }
+
+  __HAL_UNLOCK(huart);
+
+  return status;
+}
+
+/**
+  * @brief  Unregister an UART Callback
+  *         UART callaback is redirected to the weak predefined callback
+  * @param  huart uart handle
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+  *           @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+  *           @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+  *           @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+  *           @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
+  *           @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+  *           @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+  *           @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+  *           @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
+  *           @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
+  *           @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
+  *           @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
+  *           @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  __HAL_LOCK(huart);
+
+  if (HAL_UART_STATE_READY == huart->gState)
+  {
+    switch (CallbackID)
+    {
+      case HAL_UART_TX_HALFCOMPLETE_CB_ID :
+        huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback;               /* Legacy weak  TxHalfCpltCallback       */
+        break;
+
+      case HAL_UART_TX_COMPLETE_CB_ID :
+        huart->TxCpltCallback = HAL_UART_TxCpltCallback;                       /* Legacy weak TxCpltCallback            */
+        break;
+
+      case HAL_UART_RX_HALFCOMPLETE_CB_ID :
+        huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback;               /* Legacy weak RxHalfCpltCallback        */
+        break;
+
+      case HAL_UART_RX_COMPLETE_CB_ID :
+        huart->RxCpltCallback = HAL_UART_RxCpltCallback;                       /* Legacy weak RxCpltCallback            */
+        break;
+
+      case HAL_UART_ERROR_CB_ID :
+        huart->ErrorCallback = HAL_UART_ErrorCallback;                         /* Legacy weak ErrorCallback             */
+        break;
+
+      case HAL_UART_ABORT_COMPLETE_CB_ID :
+        huart->AbortCpltCallback = HAL_UART_AbortCpltCallback;                 /* Legacy weak AbortCpltCallback         */
+        break;
+
+      case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
+        huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+        break;
+
+      case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
+        huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback;   /* Legacy weak AbortReceiveCpltCallback  */
+        break;
+
+      case HAL_UART_WAKEUP_CB_ID :
+        huart->WakeupCallback = HAL_UARTEx_WakeupCallback;                     /* Legacy weak WakeupCallback            */
+        break;
+
+      case HAL_UART_RX_FIFO_FULL_CB_ID :
+        huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback;             /* Legacy weak RxFifoFullCallback        */
+        break;
+
+      case HAL_UART_TX_FIFO_EMPTY_CB_ID :
+        huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback;           /* Legacy weak TxFifoEmptyCallback       */
+        break;
+
+      case HAL_UART_MSPINIT_CB_ID :
+        huart->MspInitCallback = HAL_UART_MspInit;                             /* Legacy weak MspInitCallback           */
+        break;
+
+      case HAL_UART_MSPDEINIT_CB_ID :
+        huart->MspDeInitCallback = HAL_UART_MspDeInit;                         /* Legacy weak MspDeInitCallback         */
+        break;
+
+      default :
+        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_UART_STATE_RESET == huart->gState)
+  {
+    switch (CallbackID)
+    {
+      case HAL_UART_MSPINIT_CB_ID :
+        huart->MspInitCallback = HAL_UART_MspInit;
+        break;
+
+      case HAL_UART_MSPDEINIT_CB_ID :
+        huart->MspDeInitCallback = HAL_UART_MspDeInit;
+        break;
+
+      default :
+        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+    status =  HAL_ERROR;
+  }
+
+  __HAL_UNLOCK(huart);
+
+  return status;
+}
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup UART_Exported_Functions_Group2 IO operation functions
+  * @brief UART Transmit/Receive functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    This subsection provides a set of functions allowing to manage the UART asynchronous
+    and Half duplex data transfers.
+
+    (#) There are two mode of transfer:
+       (+) Blocking mode: The communication is performed in polling mode.
+           The HAL status of all data processing is returned by the same function
+           after finishing transfer.
+       (+) Non-Blocking mode: The communication is performed using Interrupts
+           or DMA, These API's return the HAL status.
+           The end of the data processing will be indicated through the
+           dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
+           using DMA mode.
+           The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
+           will be executed respectively at the end of the transmit or Receive process
+           The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected
+
+    (#) Blocking mode API's are :
+        (+) HAL_UART_Transmit()
+        (+) HAL_UART_Receive()
+
+    (#) Non-Blocking mode API's with Interrupt are :
+        (+) HAL_UART_Transmit_IT()
+        (+) HAL_UART_Receive_IT()
+        (+) HAL_UART_IRQHandler()
+
+    (#) Non-Blocking mode API's with DMA are :
+        (+) HAL_UART_Transmit_DMA()
+        (+) HAL_UART_Receive_DMA()
+        (+) HAL_UART_DMAPause()
+        (+) HAL_UART_DMAResume()
+        (+) HAL_UART_DMAStop()
+
+    (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
+        (+) HAL_UART_TxHalfCpltCallback()
+        (+) HAL_UART_TxCpltCallback()
+        (+) HAL_UART_RxHalfCpltCallback()
+        (+) HAL_UART_RxCpltCallback()
+        (+) HAL_UART_ErrorCallback()
+
+    (#) Non-Blocking mode transfers could be aborted using Abort API's :
+        (+) HAL_UART_Abort()
+        (+) HAL_UART_AbortTransmit()
+        (+) HAL_UART_AbortReceive()
+        (+) HAL_UART_Abort_IT()
+        (+) HAL_UART_AbortTransmit_IT()
+        (+) HAL_UART_AbortReceive_IT()
+
+    (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
+        (+) HAL_UART_AbortCpltCallback()
+        (+) HAL_UART_AbortTransmitCpltCallback()
+        (+) HAL_UART_AbortReceiveCpltCallback()
+
+    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+        Errors are handled as follows :
+       (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+           to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
+           Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+           and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side.
+           If user wants to abort it, Abort services should be called by user.
+       (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+           This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
+           Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed.
+
+    -@- In the Half duplex communication, it is forbidden to run the transmit
+        and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Send an amount of data in blocking mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 provided through pData.
+  * @note When FIFO mode is enabled, writing a data in the TDR register adds one
+  *       data to the TXFIFO. Write operations to the TDR register are performed
+  *       when TXFNF flag is set. From hardware perspective, TXFNF flag and
+  *       TXE are mapped on the same bit-field.
+  * @param huart   UART handle.
+  * @param pData   Pointer to data buffer (u8 or u16 data elements).
+  * @param Size    Amount of data elements (u8 or u16) to be sent.
+  * @param Timeout Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint8_t  *pdata8bits;
+  uint16_t *pdata16bits;
+  uint32_t tickstart;
+
+  /* Check that a Tx process is not already ongoing */
+  if (huart->gState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    __HAL_LOCK(huart);
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->gState = HAL_UART_STATE_BUSY_TX;
+
+    /* Init tickstart for timeout managment*/
+    tickstart = HAL_GetTick();
+
+    huart->TxXferSize  = Size;
+    huart->TxXferCount = Size;
+
+    /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+    {
+      pdata8bits  = NULL;
+      pdata16bits = (uint16_t *) pData;
+    }
+    else
+    {
+      pdata8bits  = pData;
+      pdata16bits = NULL;
+    }
+
+    while (huart->TxXferCount > 0U)
+    {
+      if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+      if (pdata8bits == NULL)
+      {
+        huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
+        pdata16bits++;
+      }
+      else
+      {
+        huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
+        pdata8bits++;
+      }
+      huart->TxXferCount--;
+    }
+
+    if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    /* At end of Tx process, restore huart->gState to Ready */
+    huart->gState = HAL_UART_STATE_READY;
+
+    __HAL_UNLOCK(huart);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in blocking mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the received data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 available through pData.
+  * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO
+  *       is not empty. Read operations from the RDR register are performed when
+  *       RXFNE flag is set. From hardware perspective, RXFNE flag and
+  *       RXNE are mapped on the same bit-field.
+  * @param huart   UART handle.
+  * @param pData   Pointer to data buffer (u8 or u16 data elements).
+  * @param Size    Amount of data elements (u8 or u16) to be received.
+  * @param Timeout Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint8_t  *pdata8bits;
+  uint16_t *pdata16bits;
+  uint16_t uhMask;
+  uint32_t tickstart;
+
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    __HAL_LOCK(huart);
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+    /* Init tickstart for timeout managment*/
+    tickstart = HAL_GetTick();
+
+    huart->RxXferSize  = Size;
+    huart->RxXferCount = Size;
+
+    /* Computation of UART mask to apply to RDR register */
+    UART_MASK_COMPUTATION(huart);
+    uhMask = huart->Mask;
+
+    /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+    {
+      pdata8bits  = NULL;
+      pdata16bits = (uint16_t *) pData;
+    }
+    else
+    {
+      pdata8bits  = pData;
+      pdata16bits = NULL;
+    }
+
+    /* as long as data have to be received */
+    while (huart->RxXferCount > 0U)
+    {
+      if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+      if (pdata8bits == NULL)
+      {
+        *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);
+        pdata16bits++;
+      }
+      else
+      {
+        *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
+        pdata8bits++;
+      }
+      huart->RxXferCount--;
+    }
+
+    /* At end of Rx process, restore huart->RxState to Ready */
+    huart->RxState = HAL_UART_STATE_READY;
+
+    __HAL_UNLOCK(huart);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Send an amount of data in interrupt mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 provided through pData.
+  * @param huart UART handle.
+  * @param pData Pointer to data buffer (u8 or u16 data elements).
+  * @param Size  Amount of data elements (u8 or u16) to be sent.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Tx process is not already ongoing */
+  if (huart->gState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    __HAL_LOCK(huart);
+
+    huart->pTxBuffPtr  = pData;
+    huart->TxXferSize  = Size;
+    huart->TxXferCount = Size;
+    huart->TxISR       = NULL;
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->gState = HAL_UART_STATE_BUSY_TX;
+
+    /* Configure Tx interrupt processing */
+    if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+    {
+      /* Set the Tx ISR function pointer according to the data word length */
+      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+      {
+        huart->TxISR = UART_TxISR_16BIT_FIFOEN;
+      }
+      else
+      {
+        huart->TxISR = UART_TxISR_8BIT_FIFOEN;
+      }
+
+      __HAL_UNLOCK(huart);
+
+      /* Enable the TX FIFO threshold interrupt */
+      SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+    }
+    else
+    {
+      /* Set the Tx ISR function pointer according to the data word length */
+      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+      {
+        huart->TxISR = UART_TxISR_16BIT;
+      }
+      else
+      {
+        huart->TxISR = UART_TxISR_8BIT;
+      }
+
+      __HAL_UNLOCK(huart);
+
+      /* Enable the Transmit Data Register Empty interrupt */
+      SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in interrupt mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the received data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 available through pData.
+  * @param huart UART handle.
+  * @param pData Pointer to data buffer (u8 or u16 data elements).
+  * @param Size  Amount of data elements (u8 or u16) to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    __HAL_LOCK(huart);
+
+    huart->pRxBuffPtr  = pData;
+    huart->RxXferSize  = Size;
+    huart->RxXferCount = Size;
+    huart->RxISR       = NULL;
+
+    /* Computation of UART mask to apply to RDR register */
+    UART_MASK_COMPUTATION(huart);
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+    /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+    SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+    /* Configure Rx interrupt processing*/
+    if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess))
+    {
+      /* Set the Rx ISR function pointer according to the data word length */
+      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+      {
+        huart->RxISR = UART_RxISR_16BIT_FIFOEN;
+      }
+      else
+      {
+        huart->RxISR = UART_RxISR_8BIT_FIFOEN;
+      }
+
+      __HAL_UNLOCK(huart);
+
+      /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */
+      SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+      SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+    }
+    else
+    {
+      /* Set the Rx ISR function pointer according to the data word length */
+      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+      {
+        huart->RxISR = UART_RxISR_16BIT;
+      }
+      else
+      {
+        huart->RxISR = UART_RxISR_8BIT;
+      }
+
+      __HAL_UNLOCK(huart);
+
+      /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
+      SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Send an amount of data in DMA mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 provided through pData.
+  * @param huart UART handle.
+  * @param pData Pointer to data buffer (u8 or u16 data elements).
+  * @param Size  Amount of data elements (u8 or u16) to be sent.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Tx process is not already ongoing */
+  if (huart->gState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    __HAL_LOCK(huart);
+
+    huart->pTxBuffPtr  = pData;
+    huart->TxXferSize  = Size;
+    huart->TxXferCount = Size;
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->gState = HAL_UART_STATE_BUSY_TX;
+
+    if (huart->hdmatx != NULL)
+    {
+      /* Set the UART DMA transfer complete callback */
+      huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
+
+      /* Set the UART DMA Half transfer complete callback */
+      huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
+
+      /* Set the DMA error callback */
+      huart->hdmatx->XferErrorCallback = UART_DMAError;
+
+      /* Set the DMA abort callback */
+      huart->hdmatx->XferAbortCallback = NULL;
+
+      /* Enable the UART transmit DMA channel */
+      if (HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size) != HAL_OK)
+      {
+        /* Set error code to DMA */
+        huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+        __HAL_UNLOCK(huart);
+
+        /* Restore huart->gState to ready */
+        huart->gState = HAL_UART_STATE_READY;
+
+        return HAL_ERROR;
+      }
+    }
+    /* Clear the TC flag in the ICR register */
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
+
+    __HAL_UNLOCK(huart);
+
+    /* Enable the DMA transfer for transmit request by setting the DMAT bit
+    in the UART CR3 register */
+    SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in DMA mode.
+  * @note   When the UART parity is enabled (PCE = 1), the received data contain
+  *         the parity bit (MSB position).
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the received data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 available through pData.
+  * @param huart UART handle.
+  * @param pData Pointer to data buffer (u8 or u16 data elements).
+  * @param Size  Amount of data elements (u8 or u16) to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    __HAL_LOCK(huart);
+
+    huart->pRxBuffPtr = pData;
+    huart->RxXferSize = Size;
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+    if (huart->hdmarx != NULL)
+    {
+      /* Set the UART DMA transfer complete callback */
+      huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
+
+      /* Set the UART DMA Half transfer complete callback */
+      huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
+
+      /* Set the DMA error callback */
+      huart->hdmarx->XferErrorCallback = UART_DMAError;
+
+      /* Set the DMA abort callback */
+      huart->hdmarx->XferAbortCallback = NULL;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK)
+      {
+        /* Set error code to DMA */
+        huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+        __HAL_UNLOCK(huart);
+
+        /* Restore huart->gState to ready */
+        huart->gState = HAL_UART_STATE_READY;
+
+        return HAL_ERROR;
+      }
+    }
+    __HAL_UNLOCK(huart);
+
+    /* Enable the UART Parity Error Interrupt */
+    SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+
+    /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+    SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+    /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+    in the UART CR3 register */
+    SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Pause the DMA Transfer.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
+{
+  const HAL_UART_StateTypeDef gstate = huart->gState;
+  const HAL_UART_StateTypeDef rxstate = huart->RxState;
+
+  __HAL_LOCK(huart);
+
+  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
+      (gstate == HAL_UART_STATE_BUSY_TX))
+  {
+    /* Disable the UART DMA Tx request */
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+  }
+  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
+      (rxstate == HAL_UART_STATE_BUSY_RX))
+  {
+    /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+    CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+    /* Disable the UART DMA Rx request */
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+  }
+
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Resume the DMA Transfer.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
+{
+  __HAL_LOCK(huart);
+
+  if (huart->gState == HAL_UART_STATE_BUSY_TX)
+  {
+    /* Enable the UART DMA Tx request */
+    SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+  }
+  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+  {
+    /* Clear the Overrun flag before resuming the Rx transfer */
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+
+    /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
+    SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+    SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+    /* Enable the UART DMA Rx request */
+    SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+  }
+
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Stop the DMA Transfer.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
+{
+  /* The Lock is not implemented on this API to allow the user application
+     to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() /
+     HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback:
+     indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
+     interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
+     the stream and the corresponding call back is executed. */
+
+  const HAL_UART_StateTypeDef gstate = huart->gState;
+  const HAL_UART_StateTypeDef rxstate = huart->RxState;
+
+  /* Stop UART DMA Tx request if ongoing */
+  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
+      (gstate == HAL_UART_STATE_BUSY_TX))
+  {
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx channel */
+    if (huart->hdmatx != NULL)
+    {
+      if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+
+    UART_EndTxTransfer(huart);
+  }
+
+  /* Stop UART DMA Rx request if ongoing */
+  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
+      (rxstate == HAL_UART_STATE_BUSY_RX))
+  {
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx channel */
+    if (huart->hdmarx != NULL)
+    {
+      if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+
+    UART_EndRxTransfer(huart);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing transfers (blocking mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Tx and Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
+{
+  /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE);
+
+  /* Disable the UART DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+  {
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
+    if (huart->hdmatx != NULL)
+    {
+      /* Set the UART DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      huart->hdmatx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /* Disable the UART DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
+    if (huart->hdmarx != NULL)
+    {
+      /* Set the UART DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      huart->hdmarx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /* Reset Tx and Rx transfer counters */
+  huart->TxXferCount = 0U;
+  huart->RxXferCount = 0U;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+  /* Flush the whole TX FIFO (if needed) */
+  if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+  {
+    __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+  }
+
+  /* Discard the received data */
+  __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+  /* Restore huart->gState and huart->RxState to Ready */
+  huart->gState  = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Transmit transfer (blocking mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Tx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
+{
+  /* Disable TCIE, TXEIE and TXFTIE interrupts */
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
+  CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+
+  /* Disable the UART DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+  {
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
+    if (huart->hdmatx != NULL)
+    {
+      /* Set the UART DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      huart->hdmatx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /* Reset Tx transfer counter */
+  huart->TxXferCount = 0U;
+
+  /* Flush the whole TX FIFO (if needed) */
+  if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+  {
+    __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+  }
+
+  /* Restore huart->gState to Ready */
+  huart->gState = HAL_UART_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Receive transfer (blocking mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
+{
+  /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
+  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE);
+
+  /* Disable the UART DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
+    if (huart->hdmarx != NULL)
+    {
+      /* Set the UART DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      huart->hdmarx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /* Reset Rx transfer counter */
+  huart->RxXferCount = 0U;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+  /* Discard the received data */
+  __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+  /* Restore huart->RxState to Ready */
+  huart->RxState = HAL_UART_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing transfers (Interrupt mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Tx and Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
+{
+  uint32_t abortcplt = 1U;
+
+  /* Disable interrupts */
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE | USART_CR1_TXEIE_TXFNFIE));
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
+
+  /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
+     before any call to DMA Abort functions */
+  /* DMA Tx Handle is valid */
+  if (huart->hdmatx != NULL)
+  {
+    /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
+       Otherwise, set it to NULL */
+    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+    {
+      huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback;
+    }
+    else
+    {
+      huart->hdmatx->XferAbortCallback = NULL;
+    }
+  }
+  /* DMA Rx Handle is valid */
+  if (huart->hdmarx != NULL)
+  {
+    /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
+       Otherwise, set it to NULL */
+    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+    {
+      huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback;
+    }
+    else
+    {
+      huart->hdmarx->XferAbortCallback = NULL;
+    }
+  }
+
+  /* Disable the UART DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+  {
+    /* Disable DMA Tx at UART level */
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
+    if (huart->hdmatx != NULL)
+    {
+      /* UART Tx DMA Abort callback has already been initialised :
+         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA TX */
+      if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
+      {
+        huart->hdmatx->XferAbortCallback = NULL;
+      }
+      else
+      {
+        abortcplt = 0U;
+      }
+    }
+  }
+
+  /* Disable the UART DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
+    if (huart->hdmarx != NULL)
+    {
+      /* UART Rx DMA Abort callback has already been initialised :
+         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA RX */
+      if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+      {
+        huart->hdmarx->XferAbortCallback = NULL;
+        abortcplt = 1U;
+      }
+      else
+      {
+        abortcplt = 0U;
+      }
+    }
+  }
+
+  /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+  if (abortcplt == 1U)
+  {
+    /* Reset Tx and Rx transfer counters */
+    huart->TxXferCount = 0U;
+    huart->RxXferCount = 0U;
+
+    /* Clear ISR function pointers */
+    huart->RxISR = NULL;
+    huart->TxISR = NULL;
+
+    /* Reset errorCode */
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+    /* Clear the Error flags in the ICR register */
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+    /* Flush the whole TX FIFO (if needed) */
+    if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+    {
+      __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+    }
+
+    /* Discard the received data */
+    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+    /* Restore huart->gState and huart->RxState to Ready */
+    huart->gState  = HAL_UART_STATE_READY;
+    huart->RxState = HAL_UART_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Abort complete callback */
+    huart->AbortCpltCallback(huart);
+#else
+    /* Call legacy weak Abort complete callback */
+    HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Transmit transfer (Interrupt mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Tx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
+{
+  /* Disable interrupts */
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
+  CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+
+  /* Disable the UART DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+  {
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
+    if (huart->hdmatx != NULL)
+    {
+      /* Set the UART DMA Abort callback :
+         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+      huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback;
+
+      /* Abort DMA TX */
+      if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
+      {
+        /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */
+        huart->hdmatx->XferAbortCallback(huart->hdmatx);
+      }
+    }
+    else
+    {
+      /* Reset Tx transfer counter */
+      huart->TxXferCount = 0U;
+
+      /* Clear TxISR function pointers */
+      huart->TxISR = NULL;
+
+      /* Restore huart->gState to Ready */
+      huart->gState = HAL_UART_STATE_READY;
+
+      /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+      /* Call registered Abort Transmit Complete Callback */
+      huart->AbortTransmitCpltCallback(huart);
+#else
+      /* Call legacy weak Abort Transmit Complete Callback */
+      HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+    }
+  }
+  else
+  {
+    /* Reset Tx transfer counter */
+    huart->TxXferCount = 0U;
+
+    /* Clear TxISR function pointers */
+    huart->TxISR = NULL;
+
+    /* Flush the whole TX FIFO (if needed) */
+    if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+    {
+      __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+    }
+
+    /* Restore huart->gState to Ready */
+    huart->gState = HAL_UART_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Abort Transmit Complete Callback */
+    huart->AbortTransmitCpltCallback(huart);
+#else
+    /* Call legacy weak Abort Transmit Complete Callback */
+    HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Receive transfer (Interrupt mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
+{
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+  /* Disable the UART DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
+    if (huart->hdmarx != NULL)
+    {
+      /* Set the UART DMA Abort callback :
+         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+      huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;
+
+      /* Abort DMA RX */
+      if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+      {
+        /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
+        huart->hdmarx->XferAbortCallback(huart->hdmarx);
+      }
+    }
+    else
+    {
+      /* Reset Rx transfer counter */
+      huart->RxXferCount = 0U;
+
+      /* Clear RxISR function pointer */
+      huart->pRxBuffPtr = NULL;
+
+      /* Clear the Error flags in the ICR register */
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+      /* Discard the received data */
+      __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+      /* Restore huart->RxState to Ready */
+      huart->RxState = HAL_UART_STATE_READY;
+
+      /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+      /* Call registered Abort Receive Complete Callback */
+      huart->AbortReceiveCpltCallback(huart);
+#else
+      /* Call legacy weak Abort Receive Complete Callback */
+      HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+    }
+  }
+  else
+  {
+    /* Reset Rx transfer counter */
+    huart->RxXferCount = 0U;
+
+    /* Clear RxISR function pointer */
+    huart->pRxBuffPtr = NULL;
+
+    /* Clear the Error flags in the ICR register */
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+    /* Restore huart->RxState to Ready */
+    huart->RxState = HAL_UART_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Abort Receive Complete Callback */
+    huart->AbortReceiveCpltCallback(huart);
+#else
+    /* Call legacy weak Abort Receive Complete Callback */
+    HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Handle UART interrupt request.
+  * @param huart UART handle.
+  * @retval None
+  */
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
+{
+  uint32_t isrflags   = READ_REG(huart->Instance->ISR);
+  uint32_t cr1its     = READ_REG(huart->Instance->CR1);
+  uint32_t cr3its     = READ_REG(huart->Instance->CR3);
+
+  uint32_t errorflags;
+  uint32_t errorcode;
+
+  /* If no error occurs */
+  errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
+  if (errorflags == 0U)
+  {
+    /* UART in mode Receiver ---------------------------------------------------*/
+    if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
+        && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+            || ((cr3its & USART_CR3_RXFTIE) != 0U)))
+    {
+      if (huart->RxISR != NULL)
+      {
+        huart->RxISR(huart);
+      }
+      return;
+    }
+  }
+
+  /* If some errors occur */
+  if ((errorflags != 0U)
+      && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
+           || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))))
+  {
+    /* UART parity error interrupt occurred -------------------------------------*/
+    if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+    {
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
+
+      huart->ErrorCode |= HAL_UART_ERROR_PE;
+    }
+
+    /* UART frame error interrupt occurred --------------------------------------*/
+    if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+    {
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
+
+      huart->ErrorCode |= HAL_UART_ERROR_FE;
+    }
+
+    /* UART noise error interrupt occurred --------------------------------------*/
+    if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+    {
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
+
+      huart->ErrorCode |= HAL_UART_ERROR_NE;
+    }
+
+    /* UART Over-Run interrupt occurred -----------------------------------------*/
+    if (((isrflags & USART_ISR_ORE) != 0U)
+        && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
+            ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)))
+    {
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+
+      huart->ErrorCode |= HAL_UART_ERROR_ORE;
+    }
+
+    /* UART Receiver Timeout interrupt occurred ---------------------------------*/
+    if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
+    {
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
+
+      huart->ErrorCode |= HAL_UART_ERROR_RTO;
+    }
+
+    /* Call UART Error Call back function if need be ----------------------------*/
+    if (huart->ErrorCode != HAL_UART_ERROR_NONE)
+    {
+      /* UART in mode Receiver --------------------------------------------------*/
+      if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
+          && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+              || ((cr3its & USART_CR3_RXFTIE) != 0U)))
+      {
+        if (huart->RxISR != NULL)
+        {
+          huart->RxISR(huart);
+        }
+      }
+
+      /* If Error is to be considered as blocking :
+          - Receiver Timeout error in Reception
+          - Overrun error in Reception
+          - any error occurs in DMA mode reception
+      */
+      errorcode = huart->ErrorCode;
+      if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
+          ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
+      {
+        /* Blocking error : transfer is aborted
+           Set the UART state ready to be able to start again the process,
+           Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+        UART_EndRxTransfer(huart);
+
+        /* Disable the UART DMA Rx request if enabled */
+        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+        {
+          CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+          /* Abort the UART DMA Rx channel */
+          if (huart->hdmarx != NULL)
+          {
+            /* Set the UART DMA Abort callback :
+               will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
+            huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
+
+            /* Abort DMA RX */
+            if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+            {
+              /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
+              huart->hdmarx->XferAbortCallback(huart->hdmarx);
+            }
+          }
+          else
+          {
+            /* Call user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+            /*Call registered error callback*/
+            huart->ErrorCallback(huart);
+#else
+            /*Call legacy weak error callback*/
+            HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+          }
+        }
+        else
+        {
+          /* Call user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+          /*Call registered error callback*/
+          huart->ErrorCallback(huart);
+#else
+          /*Call legacy weak error callback*/
+          HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+        }
+      }
+      else
+      {
+        /* Non Blocking error : transfer could go on.
+           Error is notified to user through user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered error callback*/
+        huart->ErrorCallback(huart);
+#else
+        /*Call legacy weak error callback*/
+        HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+        huart->ErrorCode = HAL_UART_ERROR_NONE;
+      }
+    }
+    return;
+
+  } /* End if some error occurs */
+
+  /* UART wakeup from Stop mode interrupt occurred ---------------------------*/
+  if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
+  {
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
+
+    /* UART Rx state is not reset as a reception process might be ongoing.
+       If UART handle state fields need to be reset to READY, this could be done in Wakeup callback */
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Wakeup Callback */
+    huart->WakeupCallback(huart);
+#else
+    /* Call legacy weak Wakeup Callback */
+    HAL_UARTEx_WakeupCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+    return;
+  }
+
+  /* UART in mode Transmitter ------------------------------------------------*/
+  if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
+      && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
+          || ((cr3its & USART_CR3_TXFTIE) != 0U)))
+  {
+    if (huart->TxISR != NULL)
+    {
+      huart->TxISR(huart);
+    }
+    return;
+  }
+
+  /* UART in mode Transmitter (transmission end) -----------------------------*/
+  if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
+  {
+    UART_EndTransmit_IT(huart);
+    return;
+  }
+
+  /* UART TX Fifo Empty occurred ----------------------------------------------*/
+  if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))
+  {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Tx Fifo Empty Callback */
+    huart->TxFifoEmptyCallback(huart);
+#else
+    /* Call legacy weak Tx Fifo Empty Callback */
+    HAL_UARTEx_TxFifoEmptyCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+    return;
+  }
+
+  /* UART RX Fifo Full occurred ----------------------------------------------*/
+  if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))
+  {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Rx Fifo Full Callback */
+    huart->RxFifoFullCallback(huart);
+#else
+    /* Call legacy weak Rx Fifo Full Callback */
+    HAL_UARTEx_RxFifoFullCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+    return;
+  }
+}
+
+/**
+  * @brief Tx Transfer completed callback.
+  * @param huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_TxCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Tx Half Transfer completed callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_UART_TxHalfCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Rx Transfer completed callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_RxCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Rx Half Transfer completed callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_UART_RxHalfCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  UART error callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_ErrorCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  UART Abort Complete callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_AbortCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  UART Abort Complete callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  UART Abort Receive Complete callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
+  *  @brief   UART control functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the UART.
+     (+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver timeout value on the fly
+     (+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout feature
+     (+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout feature
+     (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
+     (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
+     (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
+     (+) UART_SetConfig() API configures the UART peripheral
+     (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features
+     (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization
+     (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter
+     (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver
+     (+) HAL_LIN_SendBreak() API transmits the break characters
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Update on the fly the receiver timeout value in RTOR register.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *                    the configuration information for the specified UART module.
+  * @param  TimeoutValue receiver timeout value in number of baud blocks. The timeout
+  *                     value must be less or equal to 0x0FFFFFFFF.
+  * @retval None
+  */
+void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue)
+{
+  if (!(IS_LPUART_INSTANCE(huart->Instance)))
+  {
+    assert_param(IS_UART_RECEIVER_TIMEOUT_VALUE(TimeoutValue));
+    MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue);
+  }
+}
+
+/**
+  * @brief  Enable the UART receiver timeout feature.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *                    the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart)
+{
+  if (!(IS_LPUART_INSTANCE(huart->Instance)))
+  {
+    if (huart->gState == HAL_UART_STATE_READY)
+    {
+      /* Process Locked */
+      __HAL_LOCK(huart);
+
+      huart->gState = HAL_UART_STATE_BUSY;
+
+      /* Set the USART RTOEN bit */
+      SET_BIT(huart->Instance->CR2, USART_CR2_RTOEN);
+
+      huart->gState = HAL_UART_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(huart);
+
+      return HAL_OK;
+    }
+    else
+    {
+      return HAL_BUSY;
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable the UART receiver timeout feature.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *                    the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart)
+{
+  if (!(IS_LPUART_INSTANCE(huart->Instance)))
+  {
+    if (huart->gState == HAL_UART_STATE_READY)
+    {
+      /* Process Locked */
+      __HAL_LOCK(huart);
+
+      huart->gState = HAL_UART_STATE_BUSY;
+
+      /* Clear the USART RTOEN bit */
+      CLEAR_BIT(huart->Instance->CR2, USART_CR2_RTOEN);
+
+      huart->gState = HAL_UART_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(huart);
+
+      return HAL_OK;
+    }
+    else
+    {
+      return HAL_BUSY;
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable UART in mute mode (does not mean UART enters mute mode;
+  *         to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
+  * @param  huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)
+{
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Enable USART mute mode by setting the MME bit in the CR1 register */
+  SET_BIT(huart->Instance->CR1, USART_CR1_MME);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  return (UART_CheckIdleState(huart));
+}
+
+/**
+  * @brief  Disable UART mute mode (does not mean the UART actually exits mute mode
+  *         as it may not have been in mute mode at this very moment).
+  * @param  huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)
+{
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Disable USART mute mode by clearing the MME bit in the CR1 register */
+  CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  return (UART_CheckIdleState(huart));
+}
+
+/**
+  * @brief Enter UART mute mode (means UART actually enters mute mode).
+  * @note  To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.
+  * @param huart UART handle.
+  * @retval None
+  */
+void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
+{
+  __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST);
+}
+
+/**
+  * @brief  Enable the UART transmitter and disable the UART receiver.
+  * @param  huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
+{
+  __HAL_LOCK(huart);
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Clear TE and RE bits */
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
+
+  /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
+  SET_BIT(huart->Instance->CR1, USART_CR1_TE);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the UART receiver and disable the UART transmitter.
+  * @param  huart UART handle.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
+{
+  __HAL_LOCK(huart);
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Clear TE and RE bits */
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
+
+  /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
+  SET_BIT(huart->Instance->CR1, USART_CR1_RE);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Transmit break characters.
+  * @param  huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
+{
+  /* Check the parameters */
+  assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
+
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Send break characters */
+  __HAL_UART_SEND_REQ(huart, UART_SENDBREAK_REQUEST);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions
+  *  @brief   UART Peripheral State functions
+  *
+@verbatim
+  ==============================================================================
+            ##### Peripheral State and Error functions #####
+  ==============================================================================
+    [..]
+    This subsection provides functions allowing to :
+      (+) Return the UART handle state.
+      (+) Return the UART handle error code
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Return the UART handle state.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART.
+  * @retval HAL state
+  */
+HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
+{
+  uint32_t temp1;
+  uint32_t temp2;
+  temp1 = huart->gState;
+  temp2 = huart->RxState;
+
+  return (HAL_UART_StateTypeDef)(temp1 | temp2);
+}
+
+/**
+  * @brief  Return the UART handle error code.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART.
+  * @retval UART Error Code
+  */
+uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
+{
+  return huart->ErrorCode;
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup UART_Private_Functions UART Private Functions
+  * @{
+  */
+
+/**
+  * @brief  Initialize the callbacks to their default values.
+  * @param  huart UART handle.
+  * @retval none
+  */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart)
+{
+  /* Init the UART Callback settings */
+  huart->TxHalfCpltCallback        = HAL_UART_TxHalfCpltCallback;        /* Legacy weak TxHalfCpltCallback        */
+  huart->TxCpltCallback            = HAL_UART_TxCpltCallback;            /* Legacy weak TxCpltCallback            */
+  huart->RxHalfCpltCallback        = HAL_UART_RxHalfCpltCallback;        /* Legacy weak RxHalfCpltCallback        */
+  huart->RxCpltCallback            = HAL_UART_RxCpltCallback;            /* Legacy weak RxCpltCallback            */
+  huart->ErrorCallback             = HAL_UART_ErrorCallback;             /* Legacy weak ErrorCallback             */
+  huart->AbortCpltCallback         = HAL_UART_AbortCpltCallback;         /* Legacy weak AbortCpltCallback         */
+  huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+  huart->AbortReceiveCpltCallback  = HAL_UART_AbortReceiveCpltCallback;  /* Legacy weak AbortReceiveCpltCallback  */
+  huart->WakeupCallback            = HAL_UARTEx_WakeupCallback;          /* Legacy weak WakeupCallback            */
+  huart->RxFifoFullCallback        = HAL_UARTEx_RxFifoFullCallback;      /* Legacy weak RxFifoFullCallback        */
+  huart->TxFifoEmptyCallback       = HAL_UARTEx_TxFifoEmptyCallback;     /* Legacy weak TxFifoEmptyCallback       */
+
+}
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+  * @brief Configure the UART peripheral.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
+{
+  uint32_t tmpreg;
+  uint16_t brrtemp;
+  UART_ClockSourceTypeDef clocksource;
+  uint32_t usartdiv                   = 0x00000000U;
+  HAL_StatusTypeDef ret               = HAL_OK;
+  uint32_t lpuart_ker_ck_pres         = 0x00000000U;
+  PLL2_ClocksTypeDef pll2_clocks;
+  PLL3_ClocksTypeDef pll3_clocks;
+  uint32_t pclk;
+
+  /* Check the parameters */
+  assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
+  assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
+  if (UART_INSTANCE_LOWPOWER(huart))
+  {
+    assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits));
+  }
+  else
+  {
+    assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
+    assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));
+  }
+
+  assert_param(IS_UART_PARITY(huart->Init.Parity));
+  assert_param(IS_UART_MODE(huart->Init.Mode));
+  assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
+  assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
+  assert_param(IS_UART_PRESCALER(huart->Init.ClockPrescaler));
+
+  /*-------------------------- USART CR1 Configuration -----------------------*/
+  /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure
+  *  the UART Word Length, Parity, Mode and oversampling:
+  *  set the M bits according to huart->Init.WordLength value
+  *  set PCE and PS bits according to huart->Init.Parity value
+  *  set TE and RE bits according to huart->Init.Mode value
+  *  set OVER8 bit according to huart->Init.OverSampling value */
+  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
+  tmpreg |= (uint32_t)huart->FifoMode;
+  MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+
+  /*-------------------------- USART CR2 Configuration -----------------------*/
+  /* Configure the UART Stop Bits: Set STOP[13:12] bits according
+  * to huart->Init.StopBits value */
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
+
+  /*-------------------------- USART CR3 Configuration -----------------------*/
+  /* Configure
+  * - UART HardWare Flow Control: set CTSE and RTSE bits according
+  *   to huart->Init.HwFlowCtl value
+  * - one-bit sampling method versus three samples' majority rule according
+  *   to huart->Init.OneBitSampling (not applicable to LPUART) */
+  tmpreg = (uint32_t)huart->Init.HwFlowCtl;
+
+  if (!(UART_INSTANCE_LOWPOWER(huart)))
+  {
+    tmpreg |= huart->Init.OneBitSampling;
+  }
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
+
+  /*-------------------------- USART PRESC Configuration -----------------------*/
+  /* Configure
+  * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
+  MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
+
+  /*-------------------------- USART BRR Configuration -----------------------*/
+  UART_GETCLOCKSOURCE(huart, clocksource);
+
+  /* Check LPUART instance */
+  if (UART_INSTANCE_LOWPOWER(huart))
+  {
+    /* Retrieve frequency clock */
+    switch (clocksource)
+    {
+      case UART_CLOCKSOURCE_D3PCLK1:
+        lpuart_ker_ck_pres = (HAL_RCCEx_GetD3PCLK1Freq() / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
+        break;
+      case UART_CLOCKSOURCE_PLL2:
+        HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+        lpuart_ker_ck_pres = (pll2_clocks.PLL2_Q_Frequency / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
+        break;
+      case UART_CLOCKSOURCE_PLL3:
+        HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+        lpuart_ker_ck_pres = (pll3_clocks.PLL3_Q_Frequency / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
+        break;
+      case UART_CLOCKSOURCE_HSI:
+        if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+        {
+          lpuart_ker_ck_pres = ((uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)) / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
+        }
+        else
+        {
+          lpuart_ker_ck_pres = ((uint32_t) HSI_VALUE / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
+        }
+        break;
+      case UART_CLOCKSOURCE_CSI:
+        lpuart_ker_ck_pres = ((uint32_t)CSI_VALUE / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
+        break;
+      case UART_CLOCKSOURCE_LSE:
+        lpuart_ker_ck_pres = ((uint32_t)LSE_VALUE / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
+        break;
+      default:
+        ret = HAL_ERROR;
+        break;
+    }
+
+    /* if proper clock source reported */
+    if (lpuart_ker_ck_pres != 0U)
+    {
+      /* ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
+      if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
+          (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate)))
+      {
+        ret = HAL_ERROR;
+      }
+      else
+      {
+        switch (clocksource)
+        {
+          case UART_CLOCKSOURCE_D3PCLK1:
+            pclk = HAL_RCCEx_GetD3PCLK1Freq();
+            usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+            break;
+          case UART_CLOCKSOURCE_PLL2:
+            HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+            usartdiv = (uint32_t)(UART_DIV_LPUART(pll2_clocks.PLL2_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+            break;
+          case UART_CLOCKSOURCE_PLL3:
+            HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+            usartdiv = (uint32_t)(UART_DIV_LPUART(pll3_clocks.PLL3_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+            break;
+          case UART_CLOCKSOURCE_HSI:
+            if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+            {
+              usartdiv = (uint32_t)(UART_DIV_LPUART((uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)), huart->Init.BaudRate, huart->Init.ClockPrescaler));
+            }
+            else
+            {
+              usartdiv = (uint32_t)(UART_DIV_LPUART(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+            }
+            break;
+          case UART_CLOCKSOURCE_CSI:
+            usartdiv = (uint32_t)(UART_DIV_LPUART(CSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+            break;
+          case UART_CLOCKSOURCE_LSE:
+            usartdiv = (uint32_t)(UART_DIV_LPUART(LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+            break;
+          default:
+            ret = HAL_ERROR;
+            break;
+        }
+
+        /* It is forbidden to write values lower than 0x300 in the LPUART_BRR register */
+        if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
+        {
+          huart->Instance->BRR = usartdiv;
+        }
+        else
+        {
+          ret = HAL_ERROR;
+        }
+      } /*   if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
+    } /* if (lpuart_ker_ck_pres != 0) */
+  }
+  /* Check UART Over Sampling to set Baud Rate Register */
+  else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
+  {
+    switch (clocksource)
+    {
+      case UART_CLOCKSOURCE_D2PCLK1:
+        pclk = HAL_RCC_GetPCLK1Freq();
+        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+        break;
+      case UART_CLOCKSOURCE_D2PCLK2:
+        pclk = HAL_RCC_GetPCLK2Freq();
+        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+        break;
+      case UART_CLOCKSOURCE_PLL2:
+        HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pll2_clocks.PLL2_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+        break;
+      case UART_CLOCKSOURCE_PLL3:
+        HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pll3_clocks.PLL3_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+        break;
+      case UART_CLOCKSOURCE_HSI:
+        if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+        {
+          usartdiv = (uint16_t)(UART_DIV_SAMPLING8((HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)), huart->Init.BaudRate, huart->Init.ClockPrescaler));
+        }
+        else
+        {
+          usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+        }
+        break;
+      case UART_CLOCKSOURCE_CSI:
+        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(CSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+        break;
+      case UART_CLOCKSOURCE_LSE:
+        usartdiv = (uint16_t)(UART_DIV_SAMPLING8((uint32_t)LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+        break;
+      default:
+        ret = HAL_ERROR;
+        break;
+    }
+
+    /* USARTDIV must be greater than or equal to 0d16 */
+    if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+    {
+      brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
+      brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+      huart->Instance->BRR = brrtemp;
+    }
+    else
+    {
+      ret = HAL_ERROR;
+    }
+  }
+  else
+  {
+    switch (clocksource)
+    {
+      case UART_CLOCKSOURCE_D2PCLK1:
+        pclk = HAL_RCC_GetPCLK1Freq();
+        usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+        break;
+      case UART_CLOCKSOURCE_D2PCLK2:
+        pclk = HAL_RCC_GetPCLK2Freq();
+        usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+        break;
+      case UART_CLOCKSOURCE_PLL2:
+        HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+        usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pll2_clocks.PLL2_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+        break;
+      case UART_CLOCKSOURCE_PLL3:
+        HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+        usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pll3_clocks.PLL3_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+        break;
+      case UART_CLOCKSOURCE_HSI:
+        if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+        {
+          usartdiv = (uint16_t)(UART_DIV_SAMPLING16((HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)), huart->Init.BaudRate, huart->Init.ClockPrescaler));
+        }
+        else
+        {
+          usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+        }
+        break;
+      case UART_CLOCKSOURCE_CSI:
+        usartdiv = (uint16_t)(UART_DIV_SAMPLING16(CSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+        break;
+      case UART_CLOCKSOURCE_LSE:
+        usartdiv = (uint16_t)(UART_DIV_SAMPLING16((uint32_t)LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+        break;
+      default:
+        ret = HAL_ERROR;
+        break;
+    }
+
+    /* USARTDIV must be greater than or equal to 0d16 */
+    if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+    {
+      huart->Instance->BRR = usartdiv;
+    }
+    else
+    {
+      ret = HAL_ERROR;
+    }
+  }
+
+  /* Initialize the number of data to process during RX/TX ISR execution */
+  huart->NbTxDataToProcess = 1;
+  huart->NbRxDataToProcess = 1;
+
+  /* Clear ISR function pointers */
+  huart->RxISR = NULL;
+  huart->TxISR = NULL;
+
+  return ret;
+}
+
+/**
+  * @brief Configure the UART peripheral advanced features.
+  * @param huart UART handle.
+  * @retval None
+  */
+void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
+{
+  /* Check whether the set of advanced features to configure is properly set */
+  assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
+
+  /* if required, configure TX pin active level inversion */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
+  {
+    assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
+  }
+
+  /* if required, configure RX pin active level inversion */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
+  {
+    assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
+  }
+
+  /* if required, configure data inversion */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
+  {
+    assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
+  }
+
+  /* if required, configure RX/TX pins swap */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
+  {
+    assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
+  }
+
+  /* if required, configure RX overrun detection disabling */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
+  {
+    assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
+    MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
+  }
+
+  /* if required, configure DMA disabling on reception error */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
+  {
+    assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
+    MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
+  }
+
+  /* if required, configure auto Baud rate detection scheme */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
+  {
+    assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
+    assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
+    /* set auto Baudrate detection parameters if detection is enabled */
+    if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
+    {
+      assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
+      MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
+    }
+  }
+
+  /* if required, configure MSB first on communication line */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
+  {
+    assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
+  }
+}
+
+/**
+  * @brief Check the UART Idle State.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
+{
+  uint32_t tickstart;
+
+  /* Initialize the UART ErrorCode */
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+  /* Init tickstart for timeout managment*/
+  tickstart = HAL_GetTick();
+
+  /* Check if the Transmitter is enabled */
+  if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+  {
+    /* Wait until TEACK flag is set */
+    if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+    {
+      /* Timeout occurred */
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Check if the Receiver is enabled */
+  if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+  {
+    /* Wait until REACK flag is set */
+    if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+    {
+      /* Timeout occurred */
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Initialize the UART State */
+  huart->gState = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle UART Communication Timeout.
+  * @param huart     UART handle.
+  * @param Flag      Specifies the UART flag to check
+  * @param Status    Flag status (SET or RESET)
+  * @param Tickstart Tick start value
+  * @param Timeout   Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
+                                              uint32_t Tickstart, uint32_t Timeout)
+{
+  /* Wait until flag is set */
+  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
+  {
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+      {
+        /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+        CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
+        CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+        huart->gState = HAL_UART_STATE_READY;
+        huart->RxState = HAL_UART_STATE_READY;
+
+        __HAL_UNLOCK(huart);
+
+        return HAL_TIMEOUT;
+      }
+
+      if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
+      {
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
+        {
+          /* Clear Receiver Timeout flag*/
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
+          
+          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+          CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
+          CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+          huart->gState = HAL_UART_STATE_READY;
+          huart->RxState = HAL_UART_STATE_READY;
+          huart->ErrorCode = HAL_UART_ERROR_RTO;
+          
+          /* Process Unlocked */
+          __HAL_UNLOCK(huart);
+          
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
+  * @param  huart UART handle.
+  * @retval None
+  */
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
+{
+  /* Disable TXEIE, TCIE, TXFT interrupts */
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE));
+
+  /* At end of Tx process, restore huart->gState to Ready */
+  huart->gState = HAL_UART_STATE_READY;
+}
+
+
+/**
+  * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
+  * @param  huart UART handle.
+  * @retval None
+  */
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
+{
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+  /* At end of Rx process, restore huart->RxState to Ready */
+  huart->RxState = HAL_UART_STATE_READY;
+
+  /* Reset RxIsr function pointer */
+  huart->RxISR = NULL;
+}
+
+
+/**
+  * @brief DMA UART transmit process complete callback.
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+  /* DMA Normal mode */
+  if (hdma->Init.Mode != DMA_CIRCULAR)
+  {
+    huart->TxXferCount = 0U;
+
+    /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+       in the UART CR3 register */
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Enable the UART Transmit Complete Interrupt */
+    SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+  }
+  /* DMA Circular mode */
+  else
+  {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /*Call registered Tx complete callback*/
+    huart->TxCpltCallback(huart);
+#else
+    /*Call legacy weak Tx complete callback*/
+    HAL_UART_TxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief DMA UART transmit process half complete callback.
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered Tx Half complete callback*/
+  huart->TxHalfCpltCallback(huart);
+#else
+  /*Call legacy weak Tx Half complete callback*/
+  HAL_UART_TxHalfCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief DMA UART receive process complete callback.
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+  /* DMA Normal mode */
+  if (hdma->Init.Mode != DMA_CIRCULAR)
+  {
+    huart->RxXferCount = 0U;
+
+    /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+    CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+    /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+       in the UART CR3 register */
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* At end of Rx process, restore huart->RxState to Ready */
+    huart->RxState = HAL_UART_STATE_READY;
+  }
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered Rx complete callback*/
+  huart->RxCpltCallback(huart);
+#else
+  /*Call legacy weak Rx complete callback*/
+  HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief DMA UART receive process half complete callback.
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered Rx Half complete callback*/
+  huart->RxHalfCpltCallback(huart);
+#else
+  /*Call legacy weak Rx Half complete callback*/
+  HAL_UART_RxHalfCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief DMA UART communication error callback.
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMAError(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+  const HAL_UART_StateTypeDef gstate = huart->gState;
+  const HAL_UART_StateTypeDef rxstate = huart->RxState;
+
+  /* Stop UART DMA Tx request if ongoing */
+  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
+      (gstate == HAL_UART_STATE_BUSY_TX))
+  {
+    huart->TxXferCount = 0U;
+    UART_EndTxTransfer(huart);
+  }
+
+  /* Stop UART DMA Rx request if ongoing */
+  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
+      (rxstate == HAL_UART_STATE_BUSY_RX))
+  {
+    huart->RxXferCount = 0U;
+    UART_EndRxTransfer(huart);
+  }
+
+  huart->ErrorCode |= HAL_UART_ERROR_DMA;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered error callback*/
+  huart->ErrorCallback(huart);
+#else
+  /*Call legacy weak error callback*/
+  HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA UART communication abort callback, when initiated by HAL services on Error
+  *         (To be called at end of DMA Abort procedure following error occurrence).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+  huart->RxXferCount = 0U;
+  huart->TxXferCount = 0U;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered error callback*/
+  huart->ErrorCallback(huart);
+#else
+  /*Call legacy weak error callback*/
+  HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA UART Tx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Tx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Rx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+  huart->hdmatx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if (huart->hdmarx != NULL)
+  {
+    if (huart->hdmarx->XferAbortCallback != NULL)
+    {
+      return;
+    }
+  }
+
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  huart->TxXferCount = 0U;
+  huart->RxXferCount = 0U;
+
+  /* Reset errorCode */
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+  /* Flush the whole TX FIFO (if needed) */
+  if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+  {
+    __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+  }
+
+  /* Restore huart->gState and huart->RxState to Ready */
+  huart->gState  = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort complete callback */
+  huart->AbortCpltCallback(huart);
+#else
+  /* Call legacy weak Abort complete callback */
+  HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+
+/**
+  * @brief  DMA UART Rx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Rx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Tx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+  huart->hdmarx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if (huart->hdmatx != NULL)
+  {
+    if (huart->hdmatx->XferAbortCallback != NULL)
+    {
+      return;
+    }
+  }
+
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  huart->TxXferCount = 0U;
+  huart->RxXferCount = 0U;
+
+  /* Reset errorCode */
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+  /* Discard the received data */
+  __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+  /* Restore huart->gState and huart->RxState to Ready */
+  huart->gState  = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort complete callback */
+  huart->AbortCpltCallback(huart);
+#else
+  /* Call legacy weak Abort complete callback */
+  HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+
+/**
+  * @brief  DMA UART Tx communication abort callback, when initiated by user by a call to
+  *         HAL_UART_AbortTransmit_IT API (Abort only Tx transfer)
+  *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
+  *         and leads to user Tx Abort Complete callback execution).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+  huart->TxXferCount = 0U;
+
+  /* Flush the whole TX FIFO (if needed) */
+  if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+  {
+    __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+  }
+
+  /* Restore huart->gState to Ready */
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort Transmit Complete Callback */
+  huart->AbortTransmitCpltCallback(huart);
+#else
+  /* Call legacy weak Abort Transmit Complete Callback */
+  HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA UART Rx communication abort callback, when initiated by user by a call to
+  *         HAL_UART_AbortReceive_IT API (Abort only Rx transfer)
+  *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
+  *         and leads to user Rx Abort Complete callback execution).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  huart->RxXferCount = 0U;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+  /* Discard the received data */
+  __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+  /* Restore huart->RxState to Ready */
+  huart->RxState = HAL_UART_STATE_READY;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort Receive Complete Callback */
+  huart->AbortReceiveCpltCallback(huart);
+#else
+  /* Call legacy weak Abort Receive Complete Callback */
+  HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief TX interrrupt handler for 7 or 8 bits data word length .
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_UART_Transmit_IT().
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_TxISR_8BIT(UART_HandleTypeDef *huart)
+{
+  /* Check that a Tx process is ongoing */
+  if (huart->gState == HAL_UART_STATE_BUSY_TX)
+  {
+    if (huart->TxXferCount == 0U)
+    {
+      /* Disable the UART Transmit Data Register Empty Interrupt */
+      CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+
+      /* Enable the UART Transmit Complete Interrupt */
+      SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+    }
+    else
+    {
+      huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
+      huart->pTxBuffPtr++;
+      huart->TxXferCount--;
+    }
+  }
+}
+
+/**
+  * @brief TX interrrupt handler for 9 bits data word length.
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_UART_Transmit_IT().
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_TxISR_16BIT(UART_HandleTypeDef *huart)
+{
+  uint16_t *tmp;
+
+  /* Check that a Tx process is ongoing */
+  if (huart->gState == HAL_UART_STATE_BUSY_TX)
+  {
+    if (huart->TxXferCount == 0U)
+    {
+      /* Disable the UART Transmit Data Register Empty Interrupt */
+      CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+
+      /* Enable the UART Transmit Complete Interrupt */
+      SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+    }
+    else
+    {
+      tmp = (uint16_t *) huart->pTxBuffPtr;
+      huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
+      huart->pTxBuffPtr += 2U;
+      huart->TxXferCount--;
+    }
+  }
+}
+
+/**
+  * @brief TX interrrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_UART_Transmit_IT().
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
+{
+  uint16_t  nb_tx_data;
+
+  /* Check that a Tx process is ongoing */
+  if (huart->gState == HAL_UART_STATE_BUSY_TX)
+  {
+    for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
+    {
+      if (huart->TxXferCount == 0U)
+      {
+        /* Disable the TX FIFO threshold interrupt */
+        CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+
+        /* Enable the UART Transmit Complete Interrupt */
+        SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+
+        break; /* force exit loop */
+      }
+      else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
+      {
+        huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
+        huart->pTxBuffPtr++;
+        huart->TxXferCount--;
+      }
+      else
+      {
+        /* Nothing to do */
+      }
+    }
+  }
+}
+
+/**
+  * @brief TX interrrupt handler for 9 bits data word length and FIFO mode is enabled.
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_UART_Transmit_IT().
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
+{
+  uint16_t *tmp;
+  uint16_t  nb_tx_data;
+
+  /* Check that a Tx process is ongoing */
+  if (huart->gState == HAL_UART_STATE_BUSY_TX)
+  {
+    for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
+    {
+      if (huart->TxXferCount == 0U)
+      {
+        /* Disable the TX FIFO threshold interrupt */
+        CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+
+        /* Enable the UART Transmit Complete Interrupt */
+        SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+
+        break; /* force exit loop */
+      }
+      else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
+      {
+        tmp = (uint16_t *) huart->pTxBuffPtr;
+        huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
+        huart->pTxBuffPtr += 2U;
+        huart->TxXferCount--;
+      }
+      else
+      {
+        /* Nothing to do */
+      }
+    }
+  }
+}
+
+/**
+  * @brief  Wrap up transmission in non-blocking mode.
+  * @param  huart pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval None
+  */
+static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
+{
+  /* Disable the UART Transmit Complete Interrupt */
+  CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+
+  /* Tx process is ended, restore huart->gState to Ready */
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Cleat TxISR function pointer */
+  huart->TxISR = NULL;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered Tx complete callback*/
+  huart->TxCpltCallback(huart);
+#else
+  /*Call legacy weak Tx complete callback*/
+  HAL_UART_TxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief RX interrrupt handler for 7 or 8 bits data word length .
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
+{
+  uint16_t uhMask = huart->Mask;
+  uint16_t  uhdata;
+
+  /* Check that a Rx process is ongoing */
+  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+  {
+    uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+    *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
+    huart->pRxBuffPtr++;
+    huart->RxXferCount--;
+
+    if (huart->RxXferCount == 0U)
+    {
+      /* Disable the UART Parity Error Interrupt and RXNE interrupts */
+      CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+
+      /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+      CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+      /* Rx process is completed, restore huart->RxState to Ready */
+      huart->RxState = HAL_UART_STATE_READY;
+
+      /* Clear RxISR function pointer */
+      huart->RxISR = NULL;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+      /*Call registered Rx complete callback*/
+      huart->RxCpltCallback(huart);
+#else
+      /*Call legacy weak Rx complete callback*/
+      HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+    }
+  }
+  else
+  {
+    /* Clear RXNE interrupt flag */
+    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+  }
+}
+
+/**
+  * @brief RX interrrupt handler for 9 bits data word length .
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_UART_Receive_IT()
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
+{
+  uint16_t *tmp;
+  uint16_t uhMask = huart->Mask;
+  uint16_t  uhdata;
+
+  /* Check that a Rx process is ongoing */
+  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+  {
+    uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+    tmp = (uint16_t *) huart->pRxBuffPtr ;
+    *tmp = (uint16_t)(uhdata & uhMask);
+    huart->pRxBuffPtr += 2U;
+    huart->RxXferCount--;
+
+    if (huart->RxXferCount == 0U)
+    {
+      /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
+      CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+
+      /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+      CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+      /* Rx process is completed, restore huart->RxState to Ready */
+      huart->RxState = HAL_UART_STATE_READY;
+
+      /* Clear RxISR function pointer */
+      huart->RxISR = NULL;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+      /*Call registered Rx complete callback*/
+      huart->RxCpltCallback(huart);
+#else
+      /*Call legacy weak Rx complete callback*/
+      HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+    }
+  }
+  else
+  {
+    /* Clear RXNE interrupt flag */
+    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+  }
+}
+
+/**
+  * @brief RX interrrupt handler for 7 or 8  bits data word length and FIFO mode is enabled.
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_UART_Receive_IT()
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
+{
+  uint16_t  uhMask = huart->Mask;
+  uint16_t  uhdata;
+  uint16_t   nb_rx_data;
+  uint16_t  rxdatacount;
+
+  /* Check that a Rx process is ongoing */
+  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+  {
+    for (nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)
+    {
+      uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+      *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
+      huart->pRxBuffPtr++;
+      huart->RxXferCount--;
+
+      if (huart->RxXferCount == 0U)
+      {
+        /* Disable the UART Parity Error Interrupt and RXFT interrupt*/
+        CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+
+        /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
+        CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+        /* Rx process is completed, restore huart->RxState to Ready */
+        huart->RxState = HAL_UART_STATE_READY;
+
+        /* Clear RxISR function pointer */
+        huart->RxISR = NULL;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered Rx complete callback*/
+        huart->RxCpltCallback(huart);
+#else
+        /*Call legacy weak Rx complete callback*/
+        HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+      }
+    }
+
+    /* When remaining number of bytes to receive is less than the RX FIFO
+    threshold, next incoming frames are processed as if FIFO mode was
+    disabled (i.e. one interrupt per received frame).
+    */
+    rxdatacount = huart->RxXferCount;
+    if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
+    {
+      /* Disable the UART RXFT interrupt*/
+      CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+
+      /* Update the RxISR function pointer */
+      huart->RxISR = UART_RxISR_8BIT;
+
+      /* Enable the UART Data Register Not Empty interrupt */
+      SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+    }
+  }
+  else
+  {
+    /* Clear RXNE interrupt flag */
+    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+  }
+}
+
+/**
+  * @brief RX interrrupt handler for 9 bits data word length and FIFO mode is enabled.
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_UART_Receive_IT()
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
+{
+  uint16_t *tmp;
+  uint16_t  uhMask = huart->Mask;
+  uint16_t  uhdata;
+  uint16_t   nb_rx_data;
+  uint16_t  rxdatacount;
+
+  /* Check that a Rx process is ongoing */
+  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+  {
+    for (nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)
+    {
+      uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+      tmp = (uint16_t *) huart->pRxBuffPtr ;
+      *tmp = (uint16_t)(uhdata & uhMask);
+      huart->pRxBuffPtr += 2U;
+      huart->RxXferCount--;
+
+      if (huart->RxXferCount == 0U)
+      {
+        /* Disable the UART Parity Error Interrupt and RXFT interrupt*/
+        CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+
+        /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
+        CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+        /* Rx process is completed, restore huart->RxState to Ready */
+        huart->RxState = HAL_UART_STATE_READY;
+
+        /* Clear RxISR function pointer */
+        huart->RxISR = NULL;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered Rx complete callback*/
+        huart->RxCpltCallback(huart);
+#else
+        /*Call legacy weak Rx complete callback*/
+        HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+      }
+    }
+
+    /* When remaining number of bytes to receive is less than the RX FIFO
+    threshold, next incoming frames are processed as if FIFO mode was
+    disabled (i.e. one interrupt per received frame).
+    */
+    rxdatacount = huart->RxXferCount;
+    if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
+    {
+      /* Disable the UART RXFT interrupt*/
+      CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+
+      /* Update the RxISR function pointer */
+      huart->RxISR = UART_RxISR_16BIT;
+
+      /* Enable the UART Data Register Not Empty interrupt */
+      SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+    }
+  }
+  else
+  {
+    /* Clear RXNE interrupt flag */
+    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_UART_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c
new file mode 100644
index 00000000..94920852
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c
@@ -0,0 +1,729 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_uart_ex.c
+  * @author  MCD Application Team
+  * @brief   Extended UART HAL module driver.
+  *          This file provides firmware functions to manage the following extended
+  *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions
+  *
+  *
+  @verbatim
+  ==============================================================================
+               ##### UART peripheral extended features  #####
+  ==============================================================================
+
+    (#) Declare a UART_HandleTypeDef handle structure.
+
+    (#) For the UART RS485 Driver Enable mode, initialize the UART registers
+        by calling the HAL_RS485Ex_Init() API.
+
+    (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.
+
+        -@- When UART operates in FIFO mode, FIFO mode must be enabled prior
+            starting RX/TX transfers. Also RX/TX FIFO thresholds must be
+            configured prior starting RX/TX transfers.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup UARTEx UARTEx
+  * @brief UART Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_UART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup UARTEX_Private_Constants UARTEx Private Constants
+  * @{
+  */
+/* UART RX FIFO depth */
+#define RX_FIFO_DEPTH 8U
+
+/* UART TX FIFO depth */
+#define TX_FIFO_DEPTH 8U
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup UARTEx_Private_Functions UARTEx Private Functions
+  * @{
+  */
+static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
+static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup UARTEx_Exported_Functions  UARTEx Exported Functions
+  * @{
+  */
+
+/** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief    Extended Initialization and Configuration Functions
+  *
+@verbatim
+===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
+    in asynchronous mode.
+      (+) For the asynchronous mode the parameters below can be configured:
+        (++) Baud Rate
+        (++) Word Length
+        (++) Stop Bit
+        (++) Parity: If the parity is enabled, then the MSB bit of the data written
+             in the data register is transmitted but is changed by the parity bit.
+        (++) Hardware flow control
+        (++) Receiver/transmitter modes
+        (++) Over Sampling Method
+        (++) One-Bit Sampling Method
+      (+) For the asynchronous mode, the following advanced features can be configured as well:
+        (++) TX and/or RX pin level inversion
+        (++) data logical level inversion
+        (++) RX and TX pins swap
+        (++) RX overrun detection disabling
+        (++) DMA disabling on RX error
+        (++) MSB first on communication line
+        (++) auto Baud rate detection
+    [..]
+    The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration
+     procedures (details for the procedures are available in reference manual).
+
+@endverbatim
+
+  Depending on the frame length defined by the M1 and M0 bits (7-bit,
+  8-bit or 9-bit), the possible UART formats are listed in the
+  following table.
+
+    Table 1. UART frame format.
+    +-----------------------------------------------------------------------+
+    |  M1 bit |  M0 bit |  PCE bit  |             UART frame                |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
+    +-----------------------------------------------------------------------+
+
+  * @{
+  */
+
+/**
+  * @brief Initialize the RS485 Driver enable feature according to the specified
+  *         parameters in the UART_InitTypeDef and creates the associated handle.
+  * @param huart            UART handle.
+  * @param Polarity         Select the driver enable polarity.
+  *          This parameter can be one of the following values:
+  *          @arg @ref UART_DE_POLARITY_HIGH DE signal is active high
+  *          @arg @ref UART_DE_POLARITY_LOW  DE signal is active low
+  * @param AssertionTime    Driver Enable assertion time:
+  *       5-bit value defining the time between the activation of the DE (Driver Enable)
+  *       signal and the beginning of the start bit. It is expressed in sample time
+  *       units (1/8 or 1/16 bit time, depending on the oversampling rate)
+  * @param DeassertionTime  Driver Enable deassertion time:
+  *       5-bit value defining the time between the end of the last stop bit, in a
+  *       transmitted message, and the de-activation of the DE (Driver Enable) signal.
+  *       It is expressed in sample time units (1/8 or 1/16 bit time, depending on the
+  *       oversampling rate).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
+                                   uint32_t DeassertionTime)
+{
+  uint32_t temp;
+
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+  /* Check the Driver Enable UART instance */
+  assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));
+
+  /* Check the Driver Enable polarity */
+  assert_param(IS_UART_DE_POLARITY(Polarity));
+
+  /* Check the Driver Enable assertion time */
+  assert_param(IS_UART_ASSERTIONTIME(AssertionTime));
+
+  /* Check the Driver Enable deassertion time */
+  assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));
+
+  if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    UART_InitCallbacksToDefault(huart);
+
+    if (huart->MspInitCallback == NULL)
+    {
+      huart->MspInitCallback = HAL_UART_MspInit;
+    }
+
+    /* Init the low level hardware */
+    huart->MspInitCallback(huart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX */
+    HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the UART Communication parameters */
+  if (UART_SetConfig(huart) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+  {
+    UART_AdvFeatureConfig(huart);
+  }
+
+  /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
+  SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
+
+  /* Set the Driver Enable polarity */
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
+
+  /* Set the Driver Enable assertion and deassertion times */
+  temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
+  temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
+  MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp);
+
+  /* Enable the Peripheral */
+  __HAL_UART_ENABLE(huart);
+
+  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+  return (UART_CheckIdleState(huart));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions
+  *  @brief Extended functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    This subsection provides a set of Wakeup and FIFO mode related callback functions.
+
+    (#) Wakeup from Stop mode Callback:
+        (+) HAL_UARTEx_WakeupCallback()
+
+    (#) TX/RX Fifos Callbacks:
+        (+) HAL_UARTEx_RxFifoFullCallback()
+        (+) HAL_UARTEx_TxFifoEmptyCallback()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief UART wakeup from Stop mode callback.
+  * @param huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UARTEx_WakeupCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  UART RX Fifo full callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  UART TX Fifo empty callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions
+  * @brief    Extended Peripheral Control functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..] This section provides the following functions:
+     (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
+         detection length to more than 4 bits for multiprocessor address mark wake up.
+     (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode
+         trigger: address match, Start Bit detection or RXNE bit status.
+     (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode
+     (+) HAL_UARTEx_DisableStopMode() API disables the above functionality
+     (+) HAL_UARTEx_EnableFifoMode() API enables the FIFO mode
+     (+) HAL_UARTEx_DisableFifoMode() API disables the FIFO mode
+     (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold
+     (+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief By default in multiprocessor mode, when the wake up method is set
+  *        to address mark, the UART handles only 4-bit long addresses detection;
+  *        this API allows to enable longer addresses detection (6-, 7- or 8-bit
+  *        long).
+  * @note  Addresses detection lengths are: 6-bit address detection in 7-bit data mode,
+  *        7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
+  * @param huart         UART handle.
+  * @param AddressLength This parameter can be one of the following values:
+  *          @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address
+  *          @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the address length parameter */
+  assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the address length */
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);
+
+  /* Enable the Peripheral */
+  __HAL_UART_ENABLE(huart);
+
+  /* TEACK and/or REACK to check before moving huart->gState to Ready */
+  return (UART_CheckIdleState(huart));
+}
+
+/**
+  * @brief Set Wakeup from Stop mode interrupt flag selection.
+  * @note It is the application responsibility to enable the interrupt used as
+  *       usart_wkup interrupt source before entering low-power mode.
+  * @param huart           UART handle.
+  * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status.
+  *          This parameter can be one of the following values:
+  *          @arg @ref UART_WAKEUP_ON_ADDRESS
+  *          @arg @ref UART_WAKEUP_ON_STARTBIT
+  *          @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tickstart;
+
+  /* check the wake-up from stop mode UART instance */
+  assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
+  /* check the wake-up selection parameter */
+  assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the wake-up selection scheme */
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent);
+
+  if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS)
+  {
+    UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection);
+  }
+
+  /* Enable the Peripheral */
+  __HAL_UART_ENABLE(huart);
+
+  /* Init tickstart for timeout managment*/
+  tickstart = HAL_GetTick();
+
+  /* Wait until REACK flag is set */
+  if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+  {
+    status = HAL_TIMEOUT;
+  }
+  else
+  {
+    /* Initialize the UART State */
+    huart->gState = HAL_UART_STATE_READY;
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return status;
+}
+
+/**
+  * @brief Enable UART Stop Mode.
+  * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)
+{
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  /* Set UESM bit */
+  SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Disable UART Stop Mode.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
+{
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  /* Clear UESM bit */
+  CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the FIFO mode.
+  * @param huart      UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart)
+{
+  uint32_t tmpcr1;
+
+  /* Check parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Save actual UART configuration */
+  tmpcr1 = READ_REG(huart->Instance->CR1);
+
+  /* Disable UART */
+  __HAL_UART_DISABLE(huart);
+
+  /* Enable FIFO mode */
+  SET_BIT(tmpcr1, USART_CR1_FIFOEN);
+  huart->FifoMode = UART_FIFOMODE_ENABLE;
+
+  /* Restore UART configuration */
+  WRITE_REG(huart->Instance->CR1, tmpcr1);
+
+  /* Determine the number of data to process during RX/TX ISR execution */
+  UARTEx_SetNbDataToProcess(huart);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the FIFO mode.
+  * @param huart      UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart)
+{
+  uint32_t tmpcr1;
+
+  /* Check parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Save actual UART configuration */
+  tmpcr1 = READ_REG(huart->Instance->CR1);
+
+  /* Disable UART */
+  __HAL_UART_DISABLE(huart);
+
+  /* Enable FIFO mode */
+  CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
+  huart->FifoMode = UART_FIFOMODE_DISABLE;
+
+  /* Restore UART configuration */
+  WRITE_REG(huart->Instance->CR1, tmpcr1);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the TXFIFO threshold.
+  * @param huart      UART handle.
+  * @param Threshold  TX FIFO threshold value
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_TXFIFO_THRESHOLD_1_8
+  *            @arg @ref UART_TXFIFO_THRESHOLD_1_4
+  *            @arg @ref UART_TXFIFO_THRESHOLD_1_2
+  *            @arg @ref UART_TXFIFO_THRESHOLD_3_4
+  *            @arg @ref UART_TXFIFO_THRESHOLD_7_8
+  *            @arg @ref UART_TXFIFO_THRESHOLD_8_8
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
+{
+  uint32_t tmpcr1;
+
+  /* Check parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+  assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Save actual UART configuration */
+  tmpcr1 = READ_REG(huart->Instance->CR1);
+
+  /* Disable UART */
+  __HAL_UART_DISABLE(huart);
+
+  /* Update TX threshold configuration */
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
+
+  /* Determine the number of data to process during RX/TX ISR execution */
+  UARTEx_SetNbDataToProcess(huart);
+
+  /* Restore UART configuration */
+  WRITE_REG(huart->Instance->CR1, tmpcr1);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the RXFIFO threshold.
+  * @param huart      UART handle.
+  * @param Threshold  RX FIFO threshold value
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_RXFIFO_THRESHOLD_1_8
+  *            @arg @ref UART_RXFIFO_THRESHOLD_1_4
+  *            @arg @ref UART_RXFIFO_THRESHOLD_1_2
+  *            @arg @ref UART_RXFIFO_THRESHOLD_3_4
+  *            @arg @ref UART_RXFIFO_THRESHOLD_7_8
+  *            @arg @ref UART_RXFIFO_THRESHOLD_8_8
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
+{
+  uint32_t tmpcr1;
+
+  /* Check the parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+  assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Save actual UART configuration */
+  tmpcr1 = READ_REG(huart->Instance->CR1);
+
+  /* Disable UART */
+  __HAL_UART_DISABLE(huart);
+
+  /* Update RX threshold configuration */
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
+
+  /* Determine the number of data to process during RX/TX ISR execution */
+  UARTEx_SetNbDataToProcess(huart);
+
+  /* Restore UART configuration */
+  WRITE_REG(huart->Instance->CR1, tmpcr1);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup UARTEx_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection.
+  * @param huart           UART handle.
+  * @param WakeUpSelection UART wake up from stop mode parameters.
+  * @retval None
+  */
+static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
+{
+  assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength));
+
+  /* Set the USART address length */
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength);
+
+  /* Set the USART address node */
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS));
+}
+
+/**
+  * @brief Calculate the number of data to process in RX/TX ISR.
+  * @note The RX FIFO depth and the TX FIFO depth is extracted from
+  *       the UART configuration registers.
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart)
+{
+  uint8_t rx_fifo_depth;
+  uint8_t tx_fifo_depth;
+  uint8_t rx_fifo_threshold;
+  uint8_t tx_fifo_threshold;
+  uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
+  uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
+
+  if (huart->FifoMode == UART_FIFOMODE_DISABLE)
+  {
+    huart->NbTxDataToProcess = 1U;
+    huart->NbRxDataToProcess = 1U;
+  }
+  else
+  {
+    rx_fifo_depth = RX_FIFO_DEPTH;
+    tx_fifo_depth = TX_FIFO_DEPTH;
+    rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
+    tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
+    huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold];
+    huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold];
+  }
+}
+/**
+  * @}
+  */
+
+#endif /* HAL_UART_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/stm32h7xx_hal_conf.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/stm32h7xx_hal_conf.h
new file mode 100644
index 00000000..ed47e1b5
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/stm32h7xx_hal_conf.h
@@ -0,0 +1,493 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32H7xx_HAL_CONF_H
+#define __STM32H7xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver 
+  */
+#define HAL_MODULE_ENABLED  
+
+  /* #define HAL_ADC_MODULE_ENABLED   */
+#define HAL_FDCAN_MODULE_ENABLED
+/* #define HAL_CEC_MODULE_ENABLED   */
+/* #define HAL_COMP_MODULE_ENABLED   */
+/* #define HAL_CRC_MODULE_ENABLED   */
+/* #define HAL_CRYP_MODULE_ENABLED   */
+/* #define HAL_DAC_MODULE_ENABLED   */
+/* #define HAL_DCMI_MODULE_ENABLED   */
+/* #define HAL_DMA2D_MODULE_ENABLED   */
+/* #define HAL_ETH_MODULE_ENABLED   */
+/* #define HAL_NAND_MODULE_ENABLED   */
+/* #define HAL_NOR_MODULE_ENABLED   */
+/* #define HAL_OTFDEC_MODULE_ENABLED   */
+/* #define HAL_SRAM_MODULE_ENABLED   */
+/* #define HAL_SDRAM_MODULE_ENABLED   */
+/* #define HAL_HASH_MODULE_ENABLED   */
+/* #define HAL_HRTIM_MODULE_ENABLED   */
+/* #define HAL_HSEM_MODULE_ENABLED   */
+/* #define HAL_GFXMMU_MODULE_ENABLED   */
+/* #define HAL_JPEG_MODULE_ENABLED   */
+/* #define HAL_OPAMP_MODULE_ENABLED   */
+/* #define HAL_OSPI_MODULE_ENABLED   */
+/* #define HAL_OSPI_MODULE_ENABLED   */
+/* #define HAL_I2S_MODULE_ENABLED   */
+/* #define HAL_SMBUS_MODULE_ENABLED   */
+/* #define HAL_IWDG_MODULE_ENABLED   */
+/* #define HAL_LPTIM_MODULE_ENABLED   */
+/* #define HAL_LTDC_MODULE_ENABLED   */
+/* #define HAL_QSPI_MODULE_ENABLED   */
+/* #define HAL_RNG_MODULE_ENABLED   */
+/* #define HAL_RTC_MODULE_ENABLED   */
+/* #define HAL_SAI_MODULE_ENABLED   */
+/* #define HAL_SD_MODULE_ENABLED   */
+/* #define HAL_MMC_MODULE_ENABLED   */
+/* #define HAL_SPDIFRX_MODULE_ENABLED   */
+/* #define HAL_SPI_MODULE_ENABLED   */
+/* #define HAL_SWPMI_MODULE_ENABLED   */
+/* #define HAL_TIM_MODULE_ENABLED   */
+#define HAL_UART_MODULE_ENABLED
+/* #define HAL_USART_MODULE_ENABLED   */
+/* #define HAL_IRDA_MODULE_ENABLED   */
+/* #define HAL_SMARTCARD_MODULE_ENABLED   */
+/* #define HAL_WWDG_MODULE_ENABLED   */
+/* #define HAL_PCD_MODULE_ENABLED   */
+/* #define HAL_HCD_MODULE_ENABLED   */
+/* #define HAL_DFSDM_MODULE_ENABLED   */
+/* #define HAL_DSI_MODULE_ENABLED   */
+/* #define HAL_JPEG_MODULE_ENABLED   */
+/* #define HAL_MDIOS_MODULE_ENABLED   */
+/* #define HAL_PSSI_MODULE_ENABLED   */
+/* #define HAL_DTS_MODULE_ENABLED   */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_MDMA_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_HSEM_MODULE_ENABLED
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).  
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal  oscillator (CSI) default value.
+  *        This value is the default CSI value after Reset.
+  */
+#if !defined  (CSI_VALUE)
+  #define CSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* CSI_VALUE */
+   
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL). 
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for I2S peripheral
+  *        This value is used by the I2S HAL module to compute the I2S clock source 
+  *        frequency, this source is inserted directly through I2S_CKIN pad. 
+  */
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+  #define EXTERNAL_CLOCK_VALUE    12288000U /*!< Value of the External clock in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+#define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            ((uint32_t)0U) /*!< tick interrupt priority */
+#define  USE_RTOS                     0U
+#define  USE_SD_TRANSCEIVER           0U               /*!< use uSD Transceiver */
+
+#define  USE_HAL_ADC_REGISTER_CALLBACKS     0U /* ADC register callback disabled     */
+#define  USE_HAL_CEC_REGISTER_CALLBACKS     0U /* CEC register callback disabled     */
+#define  USE_HAL_COMP_REGISTER_CALLBACKS    0U /* COMP register callback disabled    */
+#define  USE_HAL_CRYP_REGISTER_CALLBACKS    0U /* CRYP register callback disabled    */
+#define  USE_HAL_DAC_REGISTER_CALLBACKS     0U /* DAC register callback disabled     */
+#define  USE_HAL_DCMI_REGISTER_CALLBACKS    0U /* DCMI register callback disabled    */
+#define  USE_HAL_DFSDM_REGISTER_CALLBACKS   0U /* DFSDM register callback disabled   */
+#define  USE_HAL_DMA2D_REGISTER_CALLBACKS   0U /* DMA2D register callback disabled   */
+#define  USE_HAL_DSI_REGISTER_CALLBACKS     0U /* DSI register callback disabled     */
+#define  USE_HAL_DTS_REGISTER_CALLBACKS     0U /* DTS register callback disabled     */
+#define  USE_HAL_ETH_REGISTER_CALLBACKS     0U /* ETH register callback disabled     */
+#define  USE_HAL_FDCAN_REGISTER_CALLBACKS   0U /* FDCAN register callback disabled   */
+#define  USE_HAL_NAND_REGISTER_CALLBACKS    0U /* NAND register callback disabled    */
+#define  USE_HAL_NOR_REGISTER_CALLBACKS     0U /* NOR register callback disabled     */
+#define  USE_HAL_SDRAM_REGISTER_CALLBACKS   0U /* SDRAM register callback disabled   */
+#define  USE_HAL_SRAM_REGISTER_CALLBACKS    0U /* SRAM register callback disabled    */
+#define  USE_HAL_HASH_REGISTER_CALLBACKS    0U /* HASH register callback disabled    */
+#define  USE_HAL_HCD_REGISTER_CALLBACKS     0U /* HCD register callback disabled     */
+#define  USE_HAL_GFXMMU_REGISTER_CALLBACKS  0U /* GFXMMU register callback disabled  */
+#define  USE_HAL_HRTIM_REGISTER_CALLBACKS   0U /* HRTIM register callback disabled   */
+#define  USE_HAL_I2C_REGISTER_CALLBACKS     0U /* I2C register callback disabled     */
+#define  USE_HAL_I2S_REGISTER_CALLBACKS     0U /* I2S register callback disabled     */
+#define  USE_HAL_IRDA_REGISTER_CALLBACKS    0U /* IRDA register callback disabled    */
+#define  USE_HAL_JPEG_REGISTER_CALLBACKS    0U /* JPEG register callback disabled    */
+#define  USE_HAL_LPTIM_REGISTER_CALLBACKS   0U /* LPTIM register callback disabled   */
+#define  USE_HAL_LTDC_REGISTER_CALLBACKS    0U /* LTDC register callback disabled    */
+#define  USE_HAL_MDIOS_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */
+#define  USE_HAL_MMC_REGISTER_CALLBACKS     0U /* MMC register callback disabled     */
+#define  USE_HAL_OPAMP_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */
+#define  USE_HAL_OSPI_REGISTER_CALLBACKS    0U /* OSPI register callback disabled    */
+#define  USE_HAL_OTFDEC_REGISTER_CALLBACKS  0U /* OTFDEC register callback disabled  */
+#define  USE_HAL_PCD_REGISTER_CALLBACKS     0U /* PCD register callback disabled     */
+#define  USE_HAL_QSPI_REGISTER_CALLBACKS    0U /* QSPI register callback disabled    */
+#define  USE_HAL_RNG_REGISTER_CALLBACKS     0U /* RNG register callback disabled     */
+#define  USE_HAL_RTC_REGISTER_CALLBACKS     0U /* RTC register callback disabled     */
+#define  USE_HAL_SAI_REGISTER_CALLBACKS     0U /* SAI register callback disabled     */
+#define  USE_HAL_SD_REGISTER_CALLBACKS      0U /* SD register callback disabled      */
+#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS  0U /* SMARTCARD register callback disabled */
+#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */
+#define  USE_HAL_SMBUS_REGISTER_CALLBACKS   0U /* SMBUS register callback disabled   */
+#define  USE_HAL_SPI_REGISTER_CALLBACKS     0U /* SPI register callback disabled     */
+#define  USE_HAL_SWPMI_REGISTER_CALLBACKS   0U /* SWPMI register callback disabled   */
+#define  USE_HAL_TIM_REGISTER_CALLBACKS     0U /* TIM register callback disabled     */
+#define  USE_HAL_UART_REGISTER_CALLBACKS    0U /* UART register callback disabled    */
+#define  USE_HAL_USART_REGISTER_CALLBACKS   0U /* USART register callback disabled   */
+#define  USE_HAL_WWDG_REGISTER_CALLBACKS    0U /* WWDG register callback disabled    */
+
+/* ########################### Ethernet Configuration ######################### */
+#define ETH_TX_DESC_CNT         4  /* number of Ethernet Tx DMA descriptors */
+#define ETH_RX_DESC_CNT         4  /* number of Ethernet Rx DMA descriptors */
+
+#define ETH_MAC_ADDR0    ((uint8_t)0x02)
+#define ETH_MAC_ADDR1    ((uint8_t)0x00)
+#define ETH_MAC_ADDR2    ((uint8_t)0x00)
+#define ETH_MAC_ADDR3    ((uint8_t)0x00)
+#define ETH_MAC_ADDR4    ((uint8_t)0x00)
+#define ETH_MAC_ADDR5    ((uint8_t)0x00)
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */ 
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file 
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32h7xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32h7xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32h7xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_MDMA_MODULE_ENABLED
+ #include "stm32h7xx_hal_mdma.h"
+#endif /* HAL_MDMA_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+  #include "stm32h7xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+  #include "stm32h7xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+  #include "stm32h7xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DSI_MODULE_ENABLED
+  #include "stm32h7xx_hal_dsi.h"
+#endif /* HAL_DSI_MODULE_ENABLED */
+
+#ifdef HAL_DFSDM_MODULE_ENABLED
+  #include "stm32h7xx_hal_dfsdm.h"
+#endif /* HAL_DFSDM_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+  #include "stm32h7xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32h7xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32h7xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32h7xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+  #include "stm32h7xx_hal_fdcan.h"
+#endif /* HAL_FDCAN_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+  #include "stm32h7xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32h7xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32h7xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32h7xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+  #include "stm32h7xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32h7xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GFXMMU_MODULE_ENABLED
+  #include "stm32h7xx_hal_gfxmmu.h"
+#endif /* HAL_GFXMMU_MODULE_ENABLED */
+
+#ifdef HAL_HRTIM_MODULE_ENABLED
+  #include "stm32h7xx_hal_hrtim.h"
+#endif /* HAL_HRTIM_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32h7xx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+  #include "stm32h7xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+  #include "stm32h7xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+  #include "stm32h7xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32h7xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32h7xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32h7xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_JPEG_MODULE_ENABLED
+ #include "stm32h7xx_hal_jpeg.h"
+#endif /* HAL_JPEG_MODULE_ENABLED */
+
+#ifdef HAL_MDIOS_MODULE_ENABLED
+ #include "stm32h7xx_hal_mdios.h"
+#endif /* HAL_MDIOS_MODULE_ENABLED */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+ #include "stm32h7xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+#include "stm32h7xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+#include "stm32h7xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_OPAMP_MODULE_ENABLED
+#include "stm32h7xx_hal_opamp.h"
+#endif /* HAL_OPAMP_MODULE_ENABLED */
+
+#ifdef HAL_OSPI_MODULE_ENABLED
+  #include "stm32h7xx_hal_ospi.h"
+#endif /* HAL_OSPI_MODULE_ENABLED */
+   
+#ifdef HAL_OTFDEC_MODULE_ENABLED
+#include "stm32h7xx_hal_otfdec.h"
+#endif /* HAL_OTFDEC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32h7xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32h7xx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RAMECC_MODULE_ENABLED
+ #include "stm32h7xx_hal_ramecc.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32h7xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32h7xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32h7xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32h7xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+ #include "stm32h7xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32h7xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_SPDIFRX_MODULE_ENABLED
+ #include "stm32h7xx_hal_spdifrx.h"
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */
+
+#ifdef HAL_SWPMI_MODULE_ENABLED
+ #include "stm32h7xx_hal_swpmi.h"
+#endif /* HAL_SWPMI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32h7xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32h7xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32h7xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32h7xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32h7xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32h7xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32h7xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32h7xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32h7xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_PSSI_MODULE_ENABLED
+  #include "stm32h7xx_hal_pssi.h"
+#endif /* HAL_PSSI_MODULE_ENABLED */
+
+#ifdef HAL_DTS_MODULE_ENABLED
+  #include "stm32h7xx_hal_dts.h"
+#endif /* HAL_DTS_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed. 
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32H7xx_HAL_CONF_H */
+ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/system_stm32h7xx.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/system_stm32h7xx.c
new file mode 100644
index 00000000..58da4c83
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/lib/system_stm32h7xx.c
@@ -0,0 +1,399 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32h7xx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-Mx Device Peripheral Access Layer System Source File.
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32h7xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock, it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32h7xx_system
+  * @{
+  */
+
+/** @addtogroup STM32H7xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32h7xx.h"
+#include <math.h>
+#if !defined  (HSE_VALUE)
+#define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (CSI_VALUE)
+  #define CSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* CSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Private_Defines
+  * @{
+  */
+
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to use initialized data in D2 domain SRAM (AHB SRAM) */
+/* #define DATA_IN_D2_SRAM */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00000000UL /*!< Vector Table base offset field.
+                                      This value must be a multiple of 0x200. */
+/******************************************************************************/
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Private_Variables
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock = 64000000;
+  uint32_t SystemD2Clock = 64000000;
+  const  uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the FPU setting and  vector table location
+  *         configuration.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+#if defined (DATA_IN_D2_SRAM)
+ __IO uint32_t tmpreg;
+#endif /* DATA_IN_D2_SRAM */
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2)));  /* set CP10 and CP11 Full Access */
+  #endif
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set HSION bit */
+  RCC->CR |= RCC_CR_HSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00000000;
+
+  /* Reset HSEON, CSSON , CSION,RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */
+  RCC->CR &= 0xEAF6ED7FU;
+
+#if defined(D3_SRAM_BASE)
+  /* Reset D1CFGR register */
+  RCC->D1CFGR = 0x00000000;
+
+  /* Reset D2CFGR register */
+  RCC->D2CFGR = 0x00000000;
+
+  /* Reset D3CFGR register */
+  RCC->D3CFGR = 0x00000000;
+#else
+  /* Reset CDCFGR1 register */
+  RCC->CDCFGR1 = 0x00000000;
+
+  /* Reset CDCFGR2 register */
+  RCC->CDCFGR2 = 0x00000000;
+
+  /* Reset SRDCFGR register */
+  RCC->SRDCFGR = 0x00000000;
+#endif
+  /* Reset PLLCKSELR register */
+  RCC->PLLCKSELR = 0x00000000;
+
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x00000000;
+  /* Reset PLL1DIVR register */
+  RCC->PLL1DIVR = 0x00000000;
+  /* Reset PLL1FRACR register */
+  RCC->PLL1FRACR = 0x00000000;
+
+  /* Reset PLL2DIVR register */
+  RCC->PLL2DIVR = 0x00000000;
+
+  /* Reset PLL2FRACR register */
+
+  RCC->PLL2FRACR = 0x00000000;
+  /* Reset PLL3DIVR register */
+  RCC->PLL3DIVR = 0x00000000;
+
+  /* Reset PLL3FRACR register */
+  RCC->PLL3FRACR = 0x00000000;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+
+#if (STM32H7_DEV_ID == 0x450UL)
+  /* dual core CM7 or single core line */
+  if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
+  {
+    /* if stm32h7 revY*/
+    /* Change  the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
+    *((__IO uint32_t*)0x51008108) = 0x000000001U;
+  }
+#endif
+
+#if defined (DATA_IN_D2_SRAM)
+  /* in case of initialized data in D2 SRAM (AHB SRAM) , enable the D2 SRAM clock (AHB SRAM clock) */
+#if defined(RCC_AHB2ENR_D2SRAM3EN)
+  RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);
+#elif defined(RCC_AHB2ENR_D2SRAM2EN)
+  RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN);
+#else
+  RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN);
+#endif /* RCC_AHB2ENR_D2SRAM3EN */
+
+  tmpreg = RCC->AHB2ENR;
+  (void) tmpreg;
+#endif /* DATA_IN_D2_SRAM */
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  /* Configure the Vector Table location add offset address for cortex-M4 ------------------*/
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = D2_AHBSRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+  SCB->VTOR = FLASH_BANK2_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif /* VECT_TAB_SRAM */
+
+#else
+
+  /* Configure the Vector Table location add offset address for cortex-M7 ------------------*/
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = D1_AXISRAM_BASE  | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal AXI-RAM */
+#else
+  SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+#endif /*DUAL_CORE && CORE_CM4*/
+
+}
+
+/**
+   * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock , it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*),
+  *             HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
+  *
+  *         (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *         (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+  *             64 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+  *              25 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
+  uint32_t common_system_clock;
+  float_t fracn1, pllvco;
+
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+  case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */
+    common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
+    break;
+
+  case RCC_CFGR_SWS_CSI:  /* CSI used as system clock  source */
+    common_system_clock = CSI_VALUE;
+    break;
+
+  case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
+    common_system_clock = HSE_VALUE;
+    break;
+
+  case RCC_CFGR_SWS_PLL1:  /* PLL1 used as system clock  source */
+
+    /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
+    SYSCLK = PLL_VCO / PLLR
+    */
+    pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+    pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4)  ;
+    pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
+    fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
+
+    if (pllm != 0U)
+    {
+      switch (pllsource)
+      {
+        case RCC_PLLCKSELR_PLLSRC_HSI:  /* HSI used as PLL clock source */
+
+        hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
+        pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+
+        break;
+
+        case RCC_PLLCKSELR_PLLSRC_CSI:  /* CSI used as PLL clock source */
+          pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+        break;
+
+        case RCC_PLLCKSELR_PLLSRC_HSE:  /* HSE used as PLL clock source */
+          pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+        break;
+
+      default:
+          pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+        break;
+      }
+      pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
+      common_system_clock =  (uint32_t)(float_t)(pllvco/(float_t)pllp);
+    }
+    else
+    {
+      common_system_clock = 0U;
+    }
+    break;
+
+  default:
+    common_system_clock = CSI_VALUE;
+    break;
+  }
+
+  /* Compute SystemClock frequency --------------------------------------------------*/
+#if defined (RCC_D1CFGR_D1CPRE)
+  tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];
+
+  /* common_system_clock frequency : CM7 CPU frequency  */
+  common_system_clock >>= tmp;
+
+  /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency  */
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+
+#else
+  tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos];
+
+  /* common_system_clock frequency : CM7 CPU frequency  */
+  common_system_clock >>= tmp;
+
+  /* SystemD2Clock frequency : AXI and AHBs Clock frequency  */
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+
+#endif
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  SystemCoreClock = SystemD2Clock;
+#else
+  SystemCoreClock = common_system_clock;
+#endif /* DUAL_CORE && CORE_CM4 */
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/main.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/main.c
new file mode 100644
index 00000000..be6f2dcc
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/main.c
@@ -0,0 +1,278 @@
+/************************************************************************************//**
+* \file         Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/main.c
+* \brief        Demo program application source file.
+* \ingroup      Prog_ARMCM7_STM32H7_Nucleo_H743ZI_IAR
+* \internal
+*----------------------------------------------------------------------------------------
+*                          C O P Y R I G H T
+*----------------------------------------------------------------------------------------
+*   Copyright (c) 2020  by Feaser    http://www.feaser.com    All rights reserved
+*
+*----------------------------------------------------------------------------------------
+*                            L I C E N S E
+*----------------------------------------------------------------------------------------
+* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as published by the Free
+* Software Foundation, either version 3 of the License, or (at your option) any later
+* version.
+*
+* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+* PURPOSE. See the GNU General Public License for more details.
+*
+* You have received a copy of the GNU General Public License along with OpenBLT. It
+* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
+*
+* \endinternal
+****************************************************************************************/
+
+/****************************************************************************************
+* Include files
+****************************************************************************************/
+#include "header.h"                                    /* generic header               */
+
+
+/****************************************************************************************
+* Function prototypes
+****************************************************************************************/
+static void Init(void);
+static void SystemClock_Config(void);
+static void VectorBase_Config(void);
+
+
+/************************************************************************************//**
+** \brief     This is the entry point for the bootloader application and is called
+**            by the reset interrupt vector after the C-startup routines executed.
+** \return    none.
+**
+****************************************************************************************/
+void main(void)
+{
+  /* Initialize the microcontroller */
+  Init();
+  /* Initialize the bootloader interface */
+  BootComInit();
+
+  /* start the infinite program loop */
+  while (1)
+  {
+    /* Toggle LED with a fixed frequency. */
+    LedToggle();
+    /* Check for bootloader activation request. */
+    BootComCheckActivationRequest();
+  }
+} /*** end of main ***/
+
+
+/************************************************************************************//**
+** \brief     Initializes the microcontroller.
+** \return    none.
+**
+****************************************************************************************/
+static void Init(void)
+{
+  /* Configure the vector table base address. */
+  VectorBase_Config();
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+  /* Configure the system clock. */
+  SystemClock_Config();
+  /* Initialize the timer driver. */
+  TimerInit();
+  /* Initialize the led driver. */
+  LedInit();
+} /*** end of Init ***/
+
+
+/************************************************************************************//**
+** \brief     Vector base address configuration. It should no longer be at the start of
+**            flash memory but moved forward because the first part of flash is
+**            reserved for the bootloader. Note that this is already done by the
+**            bootloader before starting this program. Unfortunately, function
+**            SystemInit() overwrites this change again. 
+** \return    none.
+**
+****************************************************************************************/
+static void VectorBase_Config(void)
+{
+  /* The constant array with vectors of the vector table is declared externally in the
+   * c-startup code.
+   */
+  extern const unsigned long __vector_table[];
+
+  /* Remap the vector table to where the vector table is located for this program. */
+  SCB->VTOR = (unsigned long)&__vector_table[0];
+} /*** end of VectorBase_Config ***/
+
+
+/************************************************************************************//**
+** \brief     System Clock Configuration. This code was created by CubeMX and configures
+**            the system clock.
+** \return    none.
+**
+****************************************************************************************/
+static void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
+
+  /* Supply configuration update enable. */
+  HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
+  /* Configure the main internal regulator output voltage. */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
+  while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY))
+  {
+    ;
+  }
+
+  /* Initializes the CPU, AHB and APB busses clocks. */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM = 4;
+  RCC_OscInitStruct.PLL.PLLN = 480;
+  RCC_OscInitStruct.PLL.PLLP = 2;
+  RCC_OscInitStruct.PLL.PLLQ = 4;
+  RCC_OscInitStruct.PLL.PLLR = 2;
+  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_1;
+  RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
+  RCC_OscInitStruct.PLL.PLLFRACN = 0;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    /* Clock configuration incorrect or hardware failure. Hang the system to prevent
+     * damage.
+     */
+    while (1);
+  }
+
+  /* Initializes the CPU, AHB and APB busses clocks. */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |
+                                RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 |
+                                RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
+  RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
+  RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
+  {
+    /* Clock configuration incorrect or hardware failure. Hang the system to prevent
+     * damage.
+     */
+    while (1);
+  }
+} /*** end of SystemClock_Config ***/
+
+
+/************************************************************************************//**
+** \brief     Initializes the Global MSP. This function is called from HAL_Init()
+**            function to perform system level initialization (GPIOs, clock, DMA,
+**            interrupt).
+** \return    none.
+**
+****************************************************************************************/
+void HAL_MspInit(void)
+{
+  GPIO_InitTypeDef GPIO_InitStruct;
+
+  /* SYSCFG clock enable. */
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+  /* GPIO ports clock enable. */
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+#if (BOOT_COM_RS232_ENABLE > 0)
+  /* Peripheral clock enable. */
+  __HAL_RCC_USART3_CLK_ENABLE();
+#endif /* BOOT_COM_RS232_ENABLE > 0 */
+#if (BOOT_COM_CAN_ENABLE > 0)
+  /* Peripheral clock enable. */
+  __HAL_RCC_FDCAN_CLK_ENABLE();
+#endif /* BOOT_COM_CAN_ENABLE > 0 */
+
+  /* Set priority grouping. */
+  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+  /* MemoryManagement_IRQn interrupt configuration. */
+  HAL_NVIC_SetPriority(MemoryManagement_IRQn, 0, 0);
+  /* BusFault_IRQn interrupt configuration. */
+  HAL_NVIC_SetPriority(BusFault_IRQn, 0, 0);
+  /* UsageFault_IRQn interrupt configuration. */
+  HAL_NVIC_SetPriority(UsageFault_IRQn, 0, 0);
+  /* SVCall_IRQn interrupt configuration. */
+  HAL_NVIC_SetPriority(SVCall_IRQn, 0, 0);
+  /* DebugMonitor_IRQn interrupt configuration. */
+  HAL_NVIC_SetPriority(DebugMonitor_IRQn, 0, 0);
+  /* PendSV_IRQn interrupt configuration. */
+  HAL_NVIC_SetPriority(PendSV_IRQn, 0, 0);
+  /* SysTick_IRQn interrupt configuration. */
+  HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0);
+
+  /* Configure the LED GPIO pin. */
+  GPIO_InitStruct.Pin = GPIO_PIN_7;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+#if (BOOT_COM_RS232_ENABLE > 0)
+  /* UART TX and RX GPIO pin configuration. */
+  GPIO_InitStruct.Pin = GPIO_PIN_8 | GPIO_PIN_9;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.Alternate = GPIO_AF7_USART3;
+  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+#endif /* BOOT_COM_RS232_ENABLE > 0 */
+#if (BOOT_COM_CAN_ENABLE > 0)
+  /* CAN TX and RX GPIO pin configuration. */
+  GPIO_InitStruct.Pin = GPIO_PIN_8 | GPIO_PIN_9;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN1;
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+#endif /* BOOT_COM_CAN_ENABLE > 0 */
+} /*** end of HAL_MspInit ***/
+
+
+/************************************************************************************//**
+** \brief     Deinitializes the Global MSP. This function is called from HAL_DeInit()
+**            function to perform system level Deinitialization (GPIOs, clock, DMA,
+**            interrupt).
+** \return    none.
+**
+****************************************************************************************/
+void HAL_MspDeInit(void)
+{
+#if (BOOT_COM_CAN_ENABLE > 0)
+  /* Reset CAN GPIO pin configuration. */
+  HAL_GPIO_DeInit(GPIOB, GPIO_PIN_8 | GPIO_PIN_9);
+#endif /* BOOT_COM_CAN_ENABLE > 0 */
+#if (BOOT_COM_RS232_ENABLE > 0)
+  /* Reset UART GPIO pin configuration. */
+  HAL_GPIO_DeInit(GPIOD, GPIO_PIN_8 | GPIO_PIN_9);
+#endif /* BOOT_COM_RS232_ENABLE > 0 */
+  /* Deconfigure GPIO pin for the LED. */
+  HAL_GPIO_WritePin(GPIOB, GPIO_PIN_7, GPIO_PIN_RESET);
+  HAL_GPIO_DeInit(GPIOB, GPIO_PIN_7);
+
+#if (BOOT_COM_CAN_ENABLE > 0)
+  /* Peripheral clock enable. */
+  __HAL_RCC_FDCAN_CLK_DISABLE();
+#endif /* BOOT_COM_CAN_ENABLE > 0 */
+#if (BOOT_COM_RS232_ENABLE > 0)
+  /* Peripheral clock disable. */
+  __HAL_RCC_USART3_CLK_DISABLE();
+#endif /* BOOT_COM_RS232_ENABLE > 0 */
+  /* GPIO ports clock disable. */
+  __HAL_RCC_GPIOD_CLK_DISABLE();
+  __HAL_RCC_GPIOC_CLK_DISABLE();
+  __HAL_RCC_GPIOB_CLK_DISABLE();
+  /* SYSCFG clock disable. */
+  __HAL_RCC_SYSCFG_CLK_DISABLE();
+} /*** end of HAL_MspDeInit ***/
+
+
+/*********************************** end of main.c *************************************/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/prog.dox b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/prog.dox
new file mode 100644
index 00000000..a149619e
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/prog.dox
@@ -0,0 +1,16 @@
+/**
+\defgroup   Prog_ARMCM7_STM32H7_Nucleo_H743ZI_IAR User Program
+\ingroup    ARMCM7_STM32H7_Nucleo_H743ZI_IAR
+\brief      User Program. 
+\details    The intention of the demo user program is two-fold. (1) To test the 
+            bootloader, you need some sort of firmware to see if you can perform a
+            firmware update with the bootloader. This program can be used for this
+            purpose. (2) To make firmware programmable by the bootloader, a few 
+            adjustments to the firmware are required. The demo user program serves as an 
+            example for how these adjustments can be implemented. Additional details on
+            this subject can be found in the port specifics documentation, which is
+            available at: 
+            https://www.feaser.com/openblt/doku.php?id=manual:ports:armcm7_stm32h7.
+*/
+
+
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/startup_stm32h743xx.s b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/startup_stm32h743xx.s
new file mode 100644
index 00000000..326f6d7c
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/startup_stm32h743xx.s
@@ -0,0 +1,983 @@
+;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;* File Name          : startup_stm32h743xx.s
+;* Author             : MCD Application Team
+;* Description        : STM32H743xx devices vector table for EWARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR 
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;* @attention
+;*
+;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+                                                  
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog Interrupt ( wwdg1_it)                                                 
+        DCD     PVD_AVD_IRQHandler                ; PVD/AVD through EXTI Line detection                                  
+        DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line                      
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line                                 
+        DCD     FLASH_IRQHandler                  ; FLASH                                                
+        DCD     RCC_IRQHandler                    ; RCC                                                  
+        DCD     EXTI0_IRQHandler                  ; EXTI Line0                                                       
+        DCD     EXTI1_IRQHandler                  ; EXTI Line1                                                       
+        DCD     EXTI2_IRQHandler                  ; EXTI Line2                                                       
+        DCD     EXTI3_IRQHandler                  ; EXTI Line3                                                       
+        DCD     EXTI4_IRQHandler                  ; EXTI Line4             
+        DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0     
+        DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1                                        
+        DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2                                        
+        DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3                                        
+        DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4                                        
+        DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5                                        
+        DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6       
+        DCD     ADC_IRQHandler                    ; ADC1, ADC2                                  
+        DCD     FDCAN1_IT0_IRQHandler             ; FDCAN1 interrupt line 0                                    
+        DCD     FDCAN2_IT0_IRQHandler             ; FDCAN2 interrupt line 0                                           
+        DCD     FDCAN1_IT1_IRQHandler             ; FDCAN1 interrupt line 1                                    
+        DCD     FDCAN2_IT1_IRQHandler             ; FDCAN2 interrupt line 1                                           
+        DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s                                              
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break interrupt        
+        DCD     TIM1_UP_IRQHandler                ; TIM1 Update 
+        DCD     TIM1_TRG_COM_IRQHandler           ; TIM1 Trigger and Commutation Interrupt 
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare                                             
+        DCD     TIM2_IRQHandler                   ; TIM2                                                 
+        DCD     TIM3_IRQHandler                   ; TIM3                                                 
+        DCD     TIM4_IRQHandler                   ; TIM4                                                 
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event                                                       
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error                                                       
+        DCD     I2C2_EV_IRQHandler                ; I2C2 Event                                                       
+        DCD     I2C2_ER_IRQHandler                ; I2C2 Error                                                         
+        DCD     SPI1_IRQHandler                   ; SPI1                                                 
+        DCD     SPI2_IRQHandler                   ; SPI2                                                 
+        DCD     USART1_IRQHandler                 ; USART1                                               
+        DCD     USART2_IRQHandler                 ; USART2                                               
+        DCD     USART3_IRQHandler                 ; USART3                                               
+        DCD     EXTI15_10_IRQHandler              ; External Line[15:10]              
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line	            
+        DCD     0                                 ; Reserved                        
+        DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break Interrupt and TIM12 global interrupt      
+        DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update Interrupt and TIM13 global interrupt
+        DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation Interrupt and TIM14 glob
+        DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt            
+        DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7                                                     
+        DCD     FMC_IRQHandler                    ; FMC                                 
+        DCD     SDMMC1_IRQHandler                 ; SDMMC1                                   
+        DCD     TIM5_IRQHandler                   ; TIM5                                 
+        DCD     SPI3_IRQHandler                   ; SPI3                                 
+        DCD     UART4_IRQHandler                  ; UART4                                
+        DCD     UART5_IRQHandler                  ; UART5                                
+        DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors                  
+        DCD     TIM7_IRQHandler                   ; TIM7           
+        DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0                        
+        DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1                        
+        DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2                        
+        DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3                        
+        DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4                        
+        DCD     ETH_IRQHandler                    ; Ethernet                             
+        DCD     ETH_WKUP_IRQHandler               ; Ethernet Wakeup through EXTI line                          
+        DCD     FDCAN_CAL_IRQHandler              ; FDCAN calibration unit interrupt                                 
+        DCD     0                                 ; Reserved                                          
+        DCD     0                                 ; Reserved             
+        DCD     0                                 ; Reserved             
+        DCD     0                                 ; Reserved                           
+        DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5                        
+        DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6                        
+        DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7                        
+        DCD     USART6_IRQHandler                 ; USART6                                 
+        DCD     I2C3_EV_IRQHandler                ; I2C3 event                                         
+        DCD     I2C3_ER_IRQHandler                ; I2C3 error                                         
+        DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out                      
+        DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In                       
+        DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI                         
+        DCD     OTG_HS_IRQHandler                 ; USB OTG HS                         
+        DCD     DCMI_IRQHandler                   ; DCMI                                 
+        DCD     0                                 ; Reserved                                     
+        DCD     RNG_IRQHandler                    ; Rng
+        DCD     FPU_IRQHandler                    ; FPU
+        DCD     UART7_IRQHandler                  ; UART7
+        DCD     UART8_IRQHandler                  ; UART8
+        DCD     SPI4_IRQHandler                   ; SPI4
+        DCD     SPI5_IRQHandler                   ; SPI5
+        DCD     SPI6_IRQHandler                   ; SPI6
+        DCD     SAI1_IRQHandler                   ; SAI1
+        DCD     LTDC_IRQHandler                   ; LTDC
+        DCD     LTDC_ER_IRQHandler                ; LTDC error
+        DCD     DMA2D_IRQHandler                  ; DMA2D
+        DCD     SAI2_IRQHandler                   ; SAI2
+        DCD     QUADSPI_IRQHandler                ; QUADSPI
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1
+        DCD     CEC_IRQHandler                    ; HDMI_CEC
+        DCD     I2C4_EV_IRQHandler                ; I2C4 Event                                         
+        DCD     I2C4_ER_IRQHandler                ; I2C4 Error 
+        DCD     SPDIF_RX_IRQHandler               ; SPDIF_RX
+        DCD     OTG_FS_EP1_OUT_IRQHandler         ; USB OTG FS End Point 1 Out                      
+        DCD     OTG_FS_EP1_IN_IRQHandler          ; USB OTG FS End Point 1 In                       
+        DCD     OTG_FS_WKUP_IRQHandler            ; USB OTG FS Wakeup through EXTI                         
+        DCD     OTG_FS_IRQHandler                 ; USB OTG FS                  
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX1 Overrun interrupt  
+        DCD     HRTIM1_Master_IRQHandler          ; HRTIM Master Timer global Interrupts                
+        DCD     HRTIM1_TIMA_IRQHandler            ; HRTIM Timer A global Interrupt                      
+        DCD     HRTIM1_TIMB_IRQHandler            ; HRTIM Timer B global Interrupt                      
+        DCD     HRTIM1_TIMC_IRQHandler            ; HRTIM Timer C global Interrupt                      
+        DCD     HRTIM1_TIMD_IRQHandler            ; HRTIM Timer D global Interrupt                      
+        DCD     HRTIM1_TIME_IRQHandler            ; HRTIM Timer E global Interrupt                      
+        DCD     HRTIM1_FLT_IRQHandler             ; HRTIM Fault global Interrupt 
+        DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM Filter0 Interrupt   
+        DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM Filter1 Interrupt                              
+        DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM Filter2 Interrupt                              
+        DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM Filter3 Interrupt                              
+        DCD     SAI3_IRQHandler                   ; SAI3 global Interrupt                               
+        DCD     SWPMI1_IRQHandler                 ; Serial Wire Interface 1 global interrupt        
+        DCD     TIM15_IRQHandler                  ; TIM15 global Interrupt                          
+        DCD     TIM16_IRQHandler                  ; TIM16 global Interrupt                          
+        DCD     TIM17_IRQHandler                  ; TIM17 global Interrupt                          
+        DCD     MDIOS_WKUP_IRQHandler             ; MDIOS Wakeup  Interrupt                         
+        DCD     MDIOS_IRQHandler                  ; MDIOS global Interrupt                          
+        DCD     JPEG_IRQHandler                   ; JPEG global Interrupt                           
+        DCD     MDMA_IRQHandler                   ; MDMA global Interrupt                           
+        DCD     0                                 ; Reserved                            
+        DCD     SDMMC2_IRQHandler                 ; SDMMC2 global Interrupt                         
+        DCD     HSEM1_IRQHandler                  ; HSEM1 global Interrupt                          
+        DCD     0                                 ; Reserved                          
+        DCD     ADC3_IRQHandler                   ; ADC3 global Interrupt                           
+        DCD     DMAMUX2_OVR_IRQHandler            ; DMAMUX Overrun interrupt                         
+        DCD     BDMA_Channel0_IRQHandler          ; BDMA Channel 0 global Interrupt                  
+        DCD     BDMA_Channel1_IRQHandler          ; BDMA Channel 1 global Interrupt                  
+        DCD     BDMA_Channel2_IRQHandler          ; BDMA Channel 2 global Interrupt                  
+        DCD     BDMA_Channel3_IRQHandler          ; BDMA Channel 3 global Interrupt                  
+        DCD     BDMA_Channel4_IRQHandler          ; BDMA Channel 4 global Interrupt                  
+        DCD     BDMA_Channel5_IRQHandler          ; BDMA Channel 5 global Interrupt                  
+        DCD     BDMA_Channel6_IRQHandler          ; BDMA Channel 6 global Interrupt                  
+        DCD     BDMA_Channel7_IRQHandler          ; BDMA Channel 7 global Interrupt                  
+        DCD     COMP1_IRQHandler                  ; COMP1 global Interrupt                          
+        DCD     LPTIM2_IRQHandler                 ; LP TIM2 global interrupt                        
+        DCD     LPTIM3_IRQHandler                 ; LP TIM3 global interrupt                        
+        DCD     LPTIM4_IRQHandler                 ; LP TIM4 global interrupt                        
+        DCD     LPTIM5_IRQHandler                 ; LP TIM5 global interrupt                        
+        DCD     LPUART1_IRQHandler                ; LP UART1 interrupt                              
+        DCD     0                                 ; Reserved              
+        DCD     CRS_IRQHandler                    ; Clock Recovery Global Interrupt                 
+        DCD     ECC_IRQHandler                    ; ECC diagnostic Global Interrupt
+        DCD     SAI4_IRQHandler                   ; SAI4 global interrupt                           
+        DCD     0                                 ; Reserved              
+        DCD     0                                 ; Reserved                             
+        DCD     WAKEUP_PIN_IRQHandler             ; Interrupt for all 6 wake-up pins 
+        DCD     0x55AA11EE                        ; Reserved for OpenBLT checksum
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        ; Initialize the stack pointer
+        LDR	    R0, =sfe(CSTACK)
+        MOV	    SP, R0
+
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler  
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_AVD_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_AVD_IRQHandler  
+        B PVD_AVD_IRQHandler
+
+        PUBWEAK TAMP_STAMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+TAMP_STAMP_IRQHandler  
+        B TAMP_STAMP_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)  
+RTC_WKUP_IRQHandler  
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler  
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler  
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler  
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler  
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler  
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+EXTI4_IRQHandler  
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Stream0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA1_Stream0_IRQHandler  
+        B DMA1_Stream0_IRQHandler
+
+        PUBWEAK DMA1_Stream1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA1_Stream1_IRQHandler  
+        B DMA1_Stream1_IRQHandler
+
+        PUBWEAK DMA1_Stream2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA1_Stream2_IRQHandler  
+        B DMA1_Stream2_IRQHandler
+
+        PUBWEAK DMA1_Stream3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA1_Stream3_IRQHandler  
+        B DMA1_Stream3_IRQHandler
+
+        PUBWEAK DMA1_Stream4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA1_Stream4_IRQHandler  
+        B DMA1_Stream4_IRQHandler
+
+        PUBWEAK DMA1_Stream5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA1_Stream5_IRQHandler  
+        B DMA1_Stream5_IRQHandler
+
+        PUBWEAK DMA1_Stream6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA1_Stream6_IRQHandler  
+        B DMA1_Stream6_IRQHandler
+
+        PUBWEAK ADC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler  
+        B ADC_IRQHandler
+
+        PUBWEAK FDCAN1_IT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+FDCAN1_IT0_IRQHandler  
+        B FDCAN1_IT0_IRQHandler
+
+        PUBWEAK FDCAN2_IT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)  
+FDCAN2_IT0_IRQHandler  
+        B FDCAN2_IT0_IRQHandler
+
+        PUBWEAK FDCAN1_IT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)  
+FDCAN1_IT1_IRQHandler  
+        B FDCAN1_IT1_IRQHandler
+
+        PUBWEAK FDCAN2_IT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)  
+FDCAN2_IT1_IRQHandler  
+        B FDCAN2_IT1_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+EXTI9_5_IRQHandler  
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+TIM1_BRK_IRQHandler  
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+TIM1_UP_IRQHandler  
+        B TIM1_UP_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+TIM1_TRG_COM_IRQHandler  
+        B TIM1_TRG_COM_IRQHandler
+        
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+TIM1_CC_IRQHandler  
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler  
+        B TIM2_IRQHandler
+
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler  
+        B TIM3_IRQHandler
+
+        PUBWEAK TIM4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler  
+        B TIM4_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+I2C1_EV_IRQHandler  
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+I2C1_ER_IRQHandler  
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+I2C2_EV_IRQHandler  
+        B I2C2_EV_IRQHandler
+
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+I2C2_ER_IRQHandler  
+        B I2C2_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler  
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler  
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler  
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler  
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler  
+        B USART3_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)   
+EXTI15_10_IRQHandler  
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)   
+RTC_Alarm_IRQHandler  
+        B RTC_Alarm_IRQHandler
+      
+        PUBWEAK TIM8_BRK_TIM12_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+TIM8_BRK_TIM12_IRQHandler  
+        B TIM8_BRK_TIM12_IRQHandler
+
+        PUBWEAK TIM8_UP_TIM13_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+TIM8_UP_TIM13_IRQHandler  
+        B TIM8_UP_TIM13_IRQHandler
+
+        PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+TIM8_TRG_COM_TIM14_IRQHandler  
+        B TIM8_TRG_COM_TIM14_IRQHandler
+
+        PUBWEAK TIM8_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+TIM8_CC_IRQHandler  
+        B TIM8_CC_IRQHandler
+
+        PUBWEAK DMA1_Stream7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA1_Stream7_IRQHandler  
+        B DMA1_Stream7_IRQHandler
+
+        PUBWEAK FMC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler  
+        B FMC_IRQHandler
+
+        PUBWEAK SDMMC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler  
+        B SDMMC1_IRQHandler
+
+        PUBWEAK TIM5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler  
+        B TIM5_IRQHandler
+
+        PUBWEAK SPI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler  
+        B SPI3_IRQHandler
+
+        PUBWEAK UART4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler  
+        B UART4_IRQHandler
+
+        PUBWEAK UART5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler  
+        B UART5_IRQHandler
+
+        PUBWEAK TIM6_DAC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)   
+TIM6_DAC_IRQHandler  
+        B TIM6_DAC_IRQHandler
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)   
+TIM7_IRQHandler  
+        B TIM7_IRQHandler
+
+        PUBWEAK DMA2_Stream0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA2_Stream0_IRQHandler  
+        B DMA2_Stream0_IRQHandler
+
+        PUBWEAK DMA2_Stream1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA2_Stream1_IRQHandler  
+        B DMA2_Stream1_IRQHandler
+
+        PUBWEAK DMA2_Stream2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA2_Stream2_IRQHandler  
+        B DMA2_Stream2_IRQHandler
+
+        PUBWEAK DMA2_Stream3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA2_Stream3_IRQHandler  
+        B DMA2_Stream3_IRQHandler
+
+        PUBWEAK DMA2_Stream4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA2_Stream4_IRQHandler  
+        B DMA2_Stream4_IRQHandler
+
+        PUBWEAK ETH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ETH_IRQHandler  
+        B ETH_IRQHandler
+
+        PUBWEAK ETH_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)  
+ETH_WKUP_IRQHandler  
+        B ETH_WKUP_IRQHandler
+
+        PUBWEAK FDCAN_CAL_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+FDCAN_CAL_IRQHandler  
+        B FDCAN_CAL_IRQHandler
+
+        PUBWEAK DMA2_Stream5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA2_Stream5_IRQHandler  
+        B DMA2_Stream5_IRQHandler
+
+        PUBWEAK DMA2_Stream6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA2_Stream6_IRQHandler  
+        B DMA2_Stream6_IRQHandler
+
+        PUBWEAK DMA2_Stream7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+DMA2_Stream7_IRQHandler  
+        B DMA2_Stream7_IRQHandler
+
+        PUBWEAK USART6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART6_IRQHandler  
+        B USART6_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+I2C3_EV_IRQHandler  
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+I2C3_ER_IRQHandler  
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK OTG_HS_EP1_OUT_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+OTG_HS_EP1_OUT_IRQHandler  
+        B OTG_HS_EP1_OUT_IRQHandler
+
+        PUBWEAK OTG_HS_EP1_IN_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)    
+OTG_HS_EP1_IN_IRQHandler  
+        B OTG_HS_EP1_IN_IRQHandler
+
+        PUBWEAK OTG_HS_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_WKUP_IRQHandler  
+        B OTG_HS_WKUP_IRQHandler
+
+        PUBWEAK OTG_HS_IRQHandler                
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_IRQHandler                  
+        B OTG_HS_IRQHandler                
+
+        PUBWEAK DCMI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_IRQHandler  
+        B DCMI_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)  
+RNG_IRQHandler  
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)  
+FPU_IRQHandler  
+        B FPU_IRQHandler
+
+        PUBWEAK UART7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)      
+UART7_IRQHandler 
+        B UART7_IRQHandler  
+
+        PUBWEAK UART8_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+UART8_IRQHandler             
+        B UART8_IRQHandler
+        
+        PUBWEAK SPI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+SPI4_IRQHandler
+        B SPI4_IRQHandler                 
+
+        PUBWEAK SPI5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+SPI5_IRQHandler   
+        B SPI5_IRQHandler                  
+
+        PUBWEAK SPI6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+SPI6_IRQHandler 
+        B SPI6_IRQHandler                    
+
+        PUBWEAK SAI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+SAI1_IRQHandler  
+        B SAI1_IRQHandler                  
+
+        PUBWEAK LTDC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+LTDC_IRQHandler 
+        B LTDC_IRQHandler                     
+
+        PUBWEAK LTDC_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+LTDC_ER_IRQHandler 
+        B LTDC_ER_IRQHandler                 
+
+        PUBWEAK DMA2D_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+DMA2D_IRQHandler 
+        B DMA2D_IRQHandler                  
+
+       PUBWEAK SAI2_IRQHandler
+       SECTION .text:CODE:NOROOT:REORDER(1) 
+SAI2_IRQHandler 
+        B SAI2_IRQHandler          
+
+       PUBWEAK QUADSPI_IRQHandler
+       SECTION .text:CODE:NOROOT:REORDER(1) 
+QUADSPI_IRQHandler 
+        B QUADSPI_IRQHandler       
+        
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+LPTIM1_IRQHandler 
+        B LPTIM1_IRQHandler   
+        
+        PUBWEAK CEC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+CEC_IRQHandler 
+        B CEC_IRQHandler 
+
+        PUBWEAK I2C4_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+I2C4_EV_IRQHandler 
+        B I2C4_EV_IRQHandler   
+        
+        PUBWEAK I2C4_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+I2C4_ER_IRQHandler 
+        B I2C4_ER_IRQHandler 
+ 
+        PUBWEAK SPDIF_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+SPDIF_RX_IRQHandler 
+        B SPDIF_RX_IRQHandler 
+
+        PUBWEAK OTG_FS_EP1_OUT_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+OTG_FS_EP1_OUT_IRQHandler 
+        B OTG_FS_EP1_OUT_IRQHandler 
+
+        PUBWEAK OTG_FS_EP1_IN_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+OTG_FS_EP1_IN_IRQHandler 
+        B OTG_FS_EP1_IN_IRQHandler
+
+        PUBWEAK OTG_FS_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+OTG_FS_WKUP_IRQHandler 
+        B OTG_FS_WKUP_IRQHandler
+
+        PUBWEAK OTG_FS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+OTG_FS_IRQHandler 
+        B OTG_FS_IRQHandler 
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+DMAMUX1_OVR_IRQHandler 
+        B DMAMUX1_OVR_IRQHandler 
+
+        PUBWEAK HRTIM1_Master_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+HRTIM1_Master_IRQHandler 
+        B HRTIM1_Master_IRQHandler 
+
+        PUBWEAK HRTIM1_TIMA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+HRTIM1_TIMA_IRQHandler 
+        B HRTIM1_TIMA_IRQHandler 
+
+        PUBWEAK HRTIM1_TIMB_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+HRTIM1_TIMB_IRQHandler 
+        B HRTIM1_TIMB_IRQHandler 
+
+        PUBWEAK HRTIM1_TIMC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+HRTIM1_TIMC_IRQHandler 
+        B HRTIM1_TIMC_IRQHandler 
+
+        PUBWEAK HRTIM1_TIMD_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+HRTIM1_TIMD_IRQHandler 
+        B HRTIM1_TIMD_IRQHandler
+
+        PUBWEAK HRTIM1_TIME_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+HRTIM1_TIME_IRQHandler 
+        B HRTIM1_TIME_IRQHandler
+
+        PUBWEAK HRTIM1_FLT_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+HRTIM1_FLT_IRQHandler 
+        B HRTIM1_FLT_IRQHandler
+
+        PUBWEAK DFSDM1_FLT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+DFSDM1_FLT0_IRQHandler 
+        B DFSDM1_FLT0_IRQHandler 
+
+        PUBWEAK DFSDM1_FLT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+DFSDM1_FLT1_IRQHandler 
+        B DFSDM1_FLT1_IRQHandler
+
+        PUBWEAK DFSDM1_FLT2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+DFSDM1_FLT2_IRQHandler 
+        B DFSDM1_FLT2_IRQHandler
+
+        PUBWEAK DFSDM1_FLT3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+DFSDM1_FLT3_IRQHandler 
+        B DFSDM1_FLT3_IRQHandler	
+
+        PUBWEAK SAI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+SAI3_IRQHandler 
+        B SAI3_IRQHandler
+
+        PUBWEAK SWPMI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+SWPMI1_IRQHandler 
+        B SWPMI1_IRQHandler
+
+        PUBWEAK TIM15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+TIM15_IRQHandler 
+        B TIM15_IRQHandler
+
+        PUBWEAK TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+TIM16_IRQHandler 
+        B TIM16_IRQHandler
+
+        PUBWEAK TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+TIM17_IRQHandler 
+        B TIM17_IRQHandler
+
+        PUBWEAK MDIOS_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+MDIOS_WKUP_IRQHandler 
+        B MDIOS_WKUP_IRQHandler
+
+        PUBWEAK MDIOS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+MDIOS_IRQHandler 
+        B MDIOS_IRQHandler
+
+        PUBWEAK JPEG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+JPEG_IRQHandler 
+        B JPEG_IRQHandler
+
+        PUBWEAK MDMA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+MDMA_IRQHandler 
+        B MDMA_IRQHandler
+
+        PUBWEAK SDMMC2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+SDMMC2_IRQHandler 
+        B SDMMC2_IRQHandler
+
+        PUBWEAK HSEM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+HSEM1_IRQHandler 
+        B HSEM1_IRQHandler
+
+        PUBWEAK ADC3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+ADC3_IRQHandler 
+        B ADC3_IRQHandler
+
+        PUBWEAK DMAMUX2_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+DMAMUX2_OVR_IRQHandler 
+        B DMAMUX2_OVR_IRQHandler
+
+        PUBWEAK BDMA_Channel0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+BDMA_Channel0_IRQHandler 
+        B BDMA_Channel0_IRQHandler
+
+        PUBWEAK BDMA_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+BDMA_Channel1_IRQHandler 
+        B BDMA_Channel1_IRQHandler
+
+        PUBWEAK BDMA_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+BDMA_Channel2_IRQHandler 
+        B BDMA_Channel2_IRQHandler
+
+        PUBWEAK BDMA_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+BDMA_Channel3_IRQHandler 
+        B BDMA_Channel3_IRQHandler
+
+        PUBWEAK BDMA_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+BDMA_Channel4_IRQHandler 
+        B BDMA_Channel4_IRQHandler
+
+        PUBWEAK BDMA_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+BDMA_Channel5_IRQHandler 
+        B BDMA_Channel5_IRQHandler
+
+        PUBWEAK BDMA_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+BDMA_Channel6_IRQHandler 
+        B BDMA_Channel6_IRQHandler
+
+        PUBWEAK BDMA_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+BDMA_Channel7_IRQHandler 
+        B BDMA_Channel7_IRQHandler
+
+        PUBWEAK COMP1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+COMP1_IRQHandler 
+        B COMP1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+LPTIM2_IRQHandler 
+        B LPTIM2_IRQHandler
+
+        PUBWEAK LPTIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+LPTIM3_IRQHandler 
+        B LPTIM3_IRQHandler
+
+        PUBWEAK LPTIM4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+LPTIM4_IRQHandler 
+        B LPTIM4_IRQHandler
+
+        PUBWEAK LPTIM5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+LPTIM5_IRQHandler 
+        B LPTIM5_IRQHandler	
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+LPUART1_IRQHandler 
+        B LPUART1_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+CRS_IRQHandler 
+        B CRS_IRQHandler
+
+        PUBWEAK ECC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+ECC_IRQHandler 
+        B ECC_IRQHandler
+
+        PUBWEAK SAI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+SAI4_IRQHandler 
+        B SAI4_IRQHandler
+
+        PUBWEAK WAKEUP_PIN_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1) 
+WAKEUP_PIN_IRQHandler 
+        B WAKEUP_PIN_IRQHandler 
+        END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/stm32h743xx_flash.icf b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/stm32h743xx_flash.icf
new file mode 100644
index 00000000..a7d1c961
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/stm32h743xx_flash.icf
@@ -0,0 +1,34 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08020000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__     = 0x08020000;
+define symbol __ICFEDIT_region_ROM_end__       = 0x081FFFFF;
+define symbol __ICFEDIT_region_RAM_start__     = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__       = 0x2001FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__   = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region  = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/timer.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/timer.c
new file mode 100644
index 00000000..73b4ecdb
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/timer.c
@@ -0,0 +1,79 @@
+/************************************************************************************//**
+* \file         Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/timer.c
+* \brief        Timer driver source file.
+* \ingroup      Prog_ARMCM7_STM32H7_Nucleo_H743ZI_IAR
+* \internal
+*----------------------------------------------------------------------------------------
+*                          C O P Y R I G H T
+*----------------------------------------------------------------------------------------
+*   Copyright (c) 2020  by Feaser    http://www.feaser.com    All rights reserved
+*
+*----------------------------------------------------------------------------------------
+*                            L I C E N S E
+*----------------------------------------------------------------------------------------
+* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as published by the Free
+* Software Foundation, either version 3 of the License, or (at your option) any later
+* version.
+*
+* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+* PURPOSE. See the GNU General Public License for more details.
+*
+* You have received a copy of the GNU General Public License along with OpenBLT. It
+* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
+*
+* \endinternal
+****************************************************************************************/
+
+/****************************************************************************************
+* Include files
+****************************************************************************************/
+#include "header.h"                                    /* generic header               */
+
+
+/************************************************************************************//**
+** \brief     Initializes the timer.
+** \return    none.
+**
+****************************************************************************************/
+void TimerInit(void)
+{
+  /* Update the  system core clock variable. */
+  SystemCoreClockUpdate();
+  /* Configure the Systick interrupt time for 1 millisecond. */
+  HAL_SYSTICK_Config(SystemCoreClock/1000);
+  /* Configure the Systick. */
+  HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
+  /* SysTick_IRQn interrupt configuration. */
+  HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0);
+} /*** end of TimerInit ***/
+
+
+/************************************************************************************//**
+** \brief     Obtains the counter value of the millisecond timer.
+** \return    Current value of the millisecond timer.
+**
+****************************************************************************************/
+unsigned long TimerGet(void)
+{
+  /* Read and return the tick counter value. */
+  return HAL_GetTick();
+} /*** end of TimerGet ***/
+
+
+/************************************************************************************//**
+** \brief     Interrupt service routine of the timer.
+** \return    none.
+**
+****************************************************************************************/
+void SysTick_Handler(void)
+{
+  /* Increment the tick counter. */
+  HAL_IncTick();
+  /* Invoke the system tick handler. */
+  HAL_SYSTICK_IRQHandler();
+} /*** end of TimerISRHandler ***/
+
+
+/*********************************** end of timer.c ************************************/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/timer.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/timer.h
new file mode 100644
index 00000000..d821b2bc
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/timer.h
@@ -0,0 +1,38 @@
+/************************************************************************************//**
+* \file         Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/Prog/timer.h
+* \brief        Timer driver header file.
+* \ingroup      Prog_ARMCM7_STM32H7_Nucleo_H743ZI_IAR
+* \internal
+*----------------------------------------------------------------------------------------
+*                          C O P Y R I G H T
+*----------------------------------------------------------------------------------------
+*   Copyright (c) 2020  by Feaser    http://www.feaser.com    All rights reserved
+*
+*----------------------------------------------------------------------------------------
+*                            L I C E N S E
+*----------------------------------------------------------------------------------------
+* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as published by the Free
+* Software Foundation, either version 3 of the License, or (at your option) any later
+* version.
+*
+* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+* PURPOSE. See the GNU General Public License for more details.
+*
+* You have received a copy of the GNU General Public License along with OpenBLT. It
+* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
+*
+* \endinternal
+****************************************************************************************/
+#ifndef TIMER_H
+#define TIMER_H
+
+/****************************************************************************************
+* Function prototypes
+****************************************************************************************/
+void          TimerInit(void);
+unsigned long TimerGet(void);
+
+#endif /* TIMER_H */
+/*********************************** end of timer.h ************************************/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/demo.dox b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/demo.dox
new file mode 100644
index 00000000..2c44bb2e
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_IAR/demo.dox
@@ -0,0 +1,9 @@
+/**
+\defgroup   ARMCM7_STM32H7_Nucleo_H743ZI_IAR Demo for Nucleo-H743ZI/IAR
+\ingroup    Demos
+\brief      Preconfigured programs for the Nucleo-H743ZI board and the IAR Embedded Workbench IDE.
+\details    For detailed getting started instructions, refer to:
+            https://www.feaser.com/openblt/doku.php?id=manual:demos:nucleo_h743zi_iar.
+*/
+
+
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/bin/openblt_stm32h743.axf b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/bin/openblt_stm32h743.axf
new file mode 100644
index 00000000..a94cbd70
Binary files /dev/null and b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/bin/openblt_stm32h743.axf differ
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/bin/openblt_stm32h743.srec b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/bin/openblt_stm32h743.srec
new file mode 100644
index 00000000..c148a658
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/bin/openblt_stm32h743.srec
@@ -0,0 +1,1454 @@
+S31508000000301B002439030008410300084303000895
+S3150800001045030008470300084903000800000000DC
+S315080000200000000000000000000000004B0300086C
+S315080000304D030008000000004F030008293500089A
+S315080000405103000851030008510300085103000832
+S315080000505103000851030008510300085103000822
+S315080000605103000851030008510300085103000812
+S315080000705103000851030008510300085103000802
+S3150800008051030008510300085103000851030008F2
+S3150800009051030008510300085103000851030008E2
+S315080000A051030008510300085103000851030008D2
+S315080000B051030008510300085103000851030008C2
+S315080000C051030008510300085103000851030008B2
+S315080000D051030008510300085103000851030008A2
+S315080000E051030008510300080000000051030008EE
+S315080000F05103000851030008510300085103000882
+S315080001005103000851030008510300085103000871
+S315080001105103000851030008510300085103000861
+S315080001205103000851030008510300085103000851
+S315080001305103000851030008510300085103000841
+S3150800014000000000000000000000000000000000A1
+S315080001505103000851030008510300085103000821
+S315080001605103000851030008510300085103000811
+S31508000170510300085103000851030008000000005D
+S3150800018051030008510300085103000851030008F1
+S3150800019051030008510300085103000851030008E1
+S315080001A051030008510300085103000851030008D1
+S315080001B051030008510300085103000851030008C1
+S315080001C051030008510300085103000851030008B1
+S315080001D051030008510300085103000851030008A1
+S315080001E05103000851030008510300085103000891
+S315080001F05103000851030008510300085103000881
+S315080002005103000851030008510300085103000870
+S315080002105103000851030008510300085103000860
+S3150800022051030008510300085103000800000000AC
+S31508000230510300085103000800000000510300089C
+S315080002405103000851030008510300085103000830
+S315080002505103000851030008510300085103000820
+S315080002605103000851030008510300085103000810
+S31508000270510300085103000851030008000000005C
+S31508000280510300085103000851030008000000004C
+S31508000290000000005103000800F002F800F03CF8E6
+S315080002A00AA090E8000C82448344AAF10107DA45C3
+S315080002B001D100F031F8AFF2090EBAE80F0013F0D9
+S315080002C0010F18BFFB1A43F001031847E456000054
+S315080002D004570000103A24BF78C878C1FAD85207E4
+S315080002E024BF30C830C144BF04680C6070470000A2
+S315080002F00023002400250026103A28BF78C1FBD821
+S31508000300520728BF30C148BF0B6070471FB505F0BC
+S3150800031083FA1FBD10B510BD00F063F81146FFF74C
+S31508000320F5FF05F072FA00F081F803B4FFF7F2FF63
+S3150800033003BC00F089F800000948804709480047CF
+S31508000340FEE7FEE7FEE7FEE7FEE7FEE7FEE7FEE777
+S31508000350FEE7000004480549054A064B70470000B9
+S31508000360B53600089902000830150024301B002411
+S31508000370301700243017002410B5203AC0F00B803F
+S31508000380B1E81850203AA0E81850B1E81850A0E88B
+S315080003901850BFF4F5AF5FEA027C24BFB1E81850E5
+S315080003A0A0E8185044BF18C918C0BDE810405FEA55
+S315080003B0827C24BF51F8043B40F8043B08BF7047D1
+S315080003C0D20728BF31F8023B48BF11F8012B28BFD6
+S315080003D020F8023B48BF00F8012B7047704770476A
+S315080003E07047754600F02CF8AE4605006946534638
+S315080003F020F00700854618B020B5FFF7ABFFBDE82B
+S3150800040020404FF000064FF000074FF000084FF06D
+S31508000410000B21F00701AC46ACE8C009ACE8C009FE
+S31508000420ACE8C009ACE8C0098D46704710B504466B
+S31508000430AFF300802046BDE81040FFF776BF000006
+S3150800044000487047D014002401491820ABBEFEE7C7
+S3150800045026000200704700F0F6F9FCE710B500F038
+S3150800046099F9012812D00A4C207801280ED103F0F8
+S315080004706DF9D4E90112114401F5FA71884205D3E0
+S3150800048000202070BDE8104000F0F6B910BD00004D
+S31508000490D80000240148406870470000D8000024AE
+S315080004A010B504490120087000F006F8BDE81040B0
+S315080004B0FFF7D4BFD800002410B5044C20780128D3
+S315080004C002D103F043F9A06010BD0000D800002453
+S315080004D00149486070470000D800002410B500F0B4
+S315080004E0B6F900F0ABF903F039F902F02DFE00F089
+S315080004F03DF9BDE81040FFF7D3BF10B500F0A3F9EA
+S3150800050003F046F900F04EF9BDE81040FFF7A6BF24
+S315080005102DE9F041184C256825F0405525604FF423
+S31508000520FA560024154F4FF4007C07EB440817F8D9
+S31508000530145098F8018045446D1C4543B6FBF5F800
+S3150800054005FB1868B8F1000F10D1B6FBF5F5ADB28A
+S315080005500D806D1E654509D217F81400107007EB5B
+S315080005604400407818700120BDE8F081641CE4B2AC
+S31508000570122CDAD30020F7E750440258D85800085E
+S3150800058070B58CB000250B950A95099540F26766FB
+S3150800059009AB0AAA0BA94FF4FA70FFF7B9FF18B905
+S315080005A0B82121A0FFF757FF2A482949016085602D
+S315080005B0C5600124047445748574BDF82C10416126
+S315080005C084619DF82810C1619DF824100162446277
+S315080005D08462C462046345638463C5630464042156
+S315080005E041648564C164056541658565C4650566BC
+S315080005F04566816600F0EAFE019502950394049427
+S3150800060005960696079501A9124800F0A6FD02224E
+S31508000610104801231146009400F0E3FD0D4801F04F
+S3150800062013F80CB070BD00002E2E5C2E2E5C2E2EFC
+S315080006305C2E2E5C536F757263655C41524D434D5B
+S31508000640375F53544D333248375C63616E2E63000F
+S3150800065000A00040EC0700242DE9F0418AB080464E
+S315080006600F46002440F2676601250E48402100F037
+S31508000670E0FD30B10B48402143466A4600F0E6FDEE
+S31508000680054655B90098B04202D1019800B901242F
+S31508000690012C02D10398000C38700AB02046BDE838
+S315080006A0F0810000EC07002410B58AB040F2E1732F
+S315080006B00193002302930393090404910593069377
+S315080006C00793089352210991012301A902460F486D
+S315080006D000F010FD002816D10C48012100F099FD04
+S315080006E0002810D103F032F800F1320405E000F0DA
+S315080006F0AAF803F02BF8A04205D80448012100F017
+S3150800070099FF0028F3D10AB010BD0000EC070024B9
+S3150800071004F002BD09480078002807D0012807D050
+S31508000720022807D0032807D040207047402070478A
+S31508000730082070473F20704700207047E4000024D7
+S3150800074009480078002807D0012807D0022807D0D2
+S31508000750032807D04020704740207047082070477C
+S315080007603F20704700207047E400002410B504F0CD
+S315080007709DFFFFF705FF064C0120207002F022FEC0
+S315080007800020207004F0D8FC0220207010BD000064
+S31508000790E400002410B5002404F096FF00B10124FB
+S315080007A0204610BD38B514486946FFF755FF134C67
+S315080007B0012805D120709DF800100F4804F08EFF1F
+S315080007C00D48694602F02CFE012806D1002020704B
+S315080007D09DF80010084804F081FF0748694604F0B0
+S315080007E00FFD012806D1022020709DF8001002484E
+S315080007F004F074FF38BD000060070024E4000024FC
+S3150800080070B506460C460C4D2878012803D13046AB
+S31508000810E1B2FFF749FF287818B93046E1B202F08D
+S3150800082055FE2878022803D13046E1B204F06EFD61
+S31508000830BDE8704004F0BEBFE4000024AFF30080BA
+S31508000840642002F04FBCAFF3008002F051BCAFF356
+S31508000850008072B6704762B6704770B505460C469A
+S31508000860164605E014F8010B05F8010BFFF7EBFF38
+S31508000870761EB6B2F6D270BD10B502F067FC002837
+S3150800088018D000F01DF8002814D0FFF741FF00F03B
+S31508000890F7FB02F075FF02F055FC074908400749C7
+S315080008A0086002F04FFC4468FFF7D5FFA446BDE890
+S315080008B01040604710BD000080FFFF1F08ED00E0F4
+S315080008C010B54FF4005007490969884303D0002042
+S315080008D018B1002010BD0120FAE702F0FBFB012049
+S315080008E010BD00000008025830B5426B036853F883
+S315080008F0844F4FF6FC718C4344EA82041C600368FB
+S3150800090053F8844F058F24F47F0444EA05441C6099
+S31508000910836B1A44036853F8884F8C4344EA82046D
+S315080009201C60036853F8884F858F24F4FE0444EA54
+S3150800093005441C60C36B02EB4302036853F8A04FDF
+S315080009408C4344EA82041C60036853F8A04FB0F84D
+S31508000950405024F4FE0444EA05441C60D0E91034EF
+S3150800096003FB0422036853F8B04F8C4344EA82041D
+S315080009701C60036853F8B04FB0F8485024F4FE04DE
+S3150800098044EA05441C60D0E9123403FB04220368D8
+S3150800099053F8AC4F8C4344EA82041C60D0E9143403
+S315080009A003FB0422036853F8F04F8C4344EA82049D
+S315080009B01C60036853F8F04FB0F8585024F47C14C0
+S315080009C044EA05441C60836D02EB4303026852F84F
+S315080009D0C04F8C4344EA83011160016851F8C02F67
+S315080009E0B0F85C3022F47C1242EA03420A600168DD
+S315080009F051F8C02F90F8603022F07C5242EA036228
+S31508000A000A60416B224A02EB8101C166826B01EBE7
+S31508000A1082020267C36B02EBC3024267D0E9103455
+S31508000A20634302EB83028267D0E91234634302EB25
+S31508000A308302C267D0E91434634302EB8302C0F829
+S31508000A408020836D02EBC302C0F88420C46D836ED8
+S31508000A505C4302EB8402C0F88820046E5C4302EB18
+S31508000A608402C0F890200B4B9A4208D99830416806
+S31508000A7041F02001416003210170012030BD0022B0
+S31508000A8000E004C1D0F890308B42FAD8002030BD7F
+S31508000A9000AC0040FCD30040F0B5D1E901650C6913
+S31508000AA02C430D68002E19D045F080452C4391F84B
+S31508000AB02070D1E9066535434E6946EA076635432F
+S31508000AC0CE683543D0F88460806E584306EB8003C1
+S31508000AD01C605D60083300200C4E0FE044EA854434
+S31508000AE0E5E71418155CE77845EA0765A77864789A
+S31508000AF03F0447EA0424254320C3001DCC6806EBBF
+S31508000B00144424788442ECD8F0BD00003458000818
+S31508000B1030B50E4B4FF08404CD0744EA002007D0C9
+S31508000B20DC6824F4E664DC60DC6814430443DC60B7
+S31508000B30890709D503F58673196821F4E6611960F2
+S31508000B40196811430143196030BD000000200052A6
+S31508000B50CA4393071A4A1CD0CB070AD0D36823F096
+S31508000B603003D360D3680343D360D36843F0880364
+S31508000B70D36089070CD502F58672116821F0300119
+S31508000B801160116801431160106840F08800106018
+S31508000B907047D16821F03001D160D2F80C1121F0EC
+S31508000BA03001C2F80C11D1680143D160D2F80C119A
+S31508000BB00143C2F80C11906940F01000906170472B
+S31508000BC0002000522DE9F04705460F4600F07CFE4E
+S31508000BD08246012F06D0294CDFF8A490294E04EA54
+S31508000BE009080AE00424F7E7681C06D000F06CFE42
+S31508000BF0A0EB0A00A84224D81DB3B8F1000F22D0F2
+S31508000C00D6F8100124EA00004000EDD0012F1FD0CD
+S31508000C10D6F810011C49084040F0004030F0024167
+S31508000C201AD01A4A91690143916110EA090F01D154
+S31508000C30706103E020F00040C6F814010120BDE809
+S31508000C40F0870320FBE7306934EA0000CCD0DDE703
+S31508000C5030690F490840E1E7012F4FF4803007D08B
+S31508000C60D6F81011C90301D5C6F814010020E6E725
+S31508000C703169C903FAD57061F8E7000004000080FD
+S31508000C80F0FF10E0002000520000EE97FC00002460
+S31508000C900000EE172DE9F04704460D46164698461D
+S31508000CA001274FEA952A4FEA8A2A2068401C05D16F
+S31508000CB05146204600F0E8F800B90027012F09D16F
+S31508000CC02068504506D05146204600F0EDF8044607
+S31508000CD004B90027012F1DD12068281A05192D1DD2
+S31508000CE04FF480690AF5806AFFF7ADFD281B001FDF
+S31508000CF0484506D35146204600F0D6F8044664B166
+S31508000D00251D16F8010B05F8010BA8F10108B8F125
+S31508000D10000FE9D13846BDE8F0870027FAE700005A
+S31508000D2010B501240A480068401C04D0084800F0A1
+S31508000D3033F900B90024012C08D106480068401C84
+S31508000D4004D0044800F028F900B90024204610BD54
+S31508000D50900C00248C0800242DE9F04107460D4626
+S31508000D600124FF26FF210F48C21B681E824200D2BB
+S31508000D700024012C0DD1384600F058F8064678199B
+S31508000D80401E00F053F80146FF2E01D0FF2900D17E
+S31508000D900024012C03D1304600F006F8044620460C
+S31508000DA0BDE8F081FFFF1F082DE9F04186B0044633
+S31508000DB00E46012500270097B44200D90025012DCB
+S31508000DC002D10E2E00D90025012D28D100F05AFD9A
+S31508000DD0DFF854801FE0FFF736FD04EB440058F8AF
+S31508000DE0201008EB80004268491C10D07AB10197A0
+S31508000DF020210591417A0291007A039001200490FE
+S31508000E0001A8694600F038FC18B1002505E0002560
+S31508000E1003E0641CE4B2B442DDD900F0BBFC06B0C2
+S31508000E202846BDE8F0810000FC5800082DE9F0418D
+S31508000E300546FF2600240C4FFFF705FD04EB44008A
+S31508000E4057F82010A94207D807EB800040680844E5
+S31508000E50A84201D9264603E0641CE4B20F2CEBD362
+S31508000E603046BDE8F0810000FC580008004870478D
+S31508000E700000020803494FF0FF30086001F2044100
+S31508000E80086070478C08002410B501248A0500D034
+S31508000E900024012C06D102688A4203D002C0A202AD
+S31508000EA0FFF7DBFC204610BD70B505460E460E481A
+S31508000EB0854203D1A0F204452C460CE00B48864235
+S31508000EC003D1094D06462C4605E02C46284600F077
+S31508000ED063F800B900242CB131462846FFF7D4FF41
+S31508000EE000B90024204670BD900C002400000208BA
+S31508000EF001200A490A684B681A448B681A44CB6869
+S31508000F001A440B691A444B691A448B691A44D1F876
+S31508000F1098121144002900D00020704700000208EA
+S31508000F202DE9F04105460E46174601241648411B91
+S31508000F30701E814200D20024012C0BD12846FFF7EF
+S31508000F4075FFFF2805D0A819401EFFF76FFFFF2879
+S31508000F5000D10024012C13D1A80A80020B4988422B
+S31508000F6007D10B4833463A462946FFF793FE04460F
+S31508000F7006E0084833463A462946FFF78BFE0446FC
+S31508000F802046BDE8F0810000FFFF1F0800000208A8
+S31508000F90900C00248C0800242DE9F0410746012511
+S31508000FA03868FFF743FFFF2800D10025012D25D11A
+S31508000FB000F068FC0024386800EB441607EB441878
+S31508000FC008F10408FFF73FFC01204246314600F0CD
+S31508000FD0FBFB08B100250FE00023F05C18F80310AE
+S31508000FE0884201D0002503E05B1CDBB2202BF4D33A
+S31508000FF015B1641C202CDED300F0CCFB2846BDE8D6
+S31508001000F081000008B50120002100910C490A680A
+S31508001010521C14D048688A681044CA6810440A6981
+S3150800102010444A6910448A691044C9690844C0438F
+S31508001030401C0090034804216A46FFF771FF08BD6B
+S31508001040900C00249802020810B50B480168001D90
+S315080010500468001D0068084400280BD007490822C8
+S3150800106001F077FB054904222046BDE810401031FF
+S3150800107001F06FBB10BD000000E8F11FBE000024A0
+S3150800108010B512496FF00040086000200860411E44
+S315080010900E4A121D11601060121D11601060121D9B
+S315080010A011601060121D11601060121D1160106031
+S315080010B0121D11601060121D11601060121D116062
+S315080010C0106000F057FC002010BD00007C44025858
+S315080010D070B5044600F0F8FB0546601C02D00448CB
+S315080010E00078044400F0F0FB401BA042FAD370BD20
+S315080010F00C00002470B590F89840012C08D0022CFA
+S3150800110006D050F89C1F41F002010160012070BD15
+S315080011100468D4F8C05093FAA3F6B6FA86F6C5F36F
+S315080011200545B54206D850F89C1F41F020010160DC
+S31508001130012070BDD4F8CC401C4206D050F89C1F44
+S3150800114041F040010160012070BD93FAA3F3B3FAA0
+S3150800115083F3FFF7A1FC002070BD10B590F8982026
+S31508001160012A08D0022A06D050F89C1F41F0020135
+S315080011700160012010BDCA680B688BB1072A0B698C
+S3150800118043EA42732BD00C7A4A6942EA8472496868
+S31508001190006F00EBC100036042604FF0000010BD15
+S315080011A0072A10D00C7A4FEAC2624B6943EA847365
+S315080011B00C8A42EA044243EA02034968C06E00EB1D
+S315080011C081000360E9E70B8A4FF060548A6942EAB6
+S315080011D00343CA6944EA022243EA0203EDE78A693D
+S315080011E0D5E730B5039C90F89850012D06D050F8F5
+S315080011F09C1F41F004010160012030BD006809010F
+S3150800120041EA820141EA43012143C0F880100020E7
+S3150800121030BD90F89820022A06D050F89C1F41F05D
+S3150800122008010160012070470068C0F8D01000204E
+S3150800123070470068402904D0D0F8B40000F07F0059
+S315080012407047D0F8A40000F07F007047F0B500267C
+S3150800125090F89840022C06D050F89C1F41F00801DF
+S3150800126001600120F0BD40290BD041292BD0046D27
+S315080012708C424AD850F89C1F41F020010160012099
+S31508001280F0BD0468D4F8A05015F4FE0F0DD0D4F8BC
+S31508001290A4506D0610D0D4F8A440C4F30526446CB7
+S315080012A0456F744305EB840534E050F89C1F41F004
+S315080012B0200101600120F0BD50F89C1F41F48071A7
+S315080012C001600120F0BD0468D4F8B05015F4FE0F93
+S315080012D00DD0D4F8B4506D0610D0D4F8B440C4F389
+S315080012E00526C46C856F744305EB840512E050F837
+S315080012F09C1F41F0200101600120F0BD50F89C1FA1
+S3150800130041F4807101600120F0BD446DC56F4C4306
+S3150800131005EB84052C6804F0804454602CB32C68D3
+S3150800132024F0604414602C6804F0005494602C681F
+S3150800133004F000441461AC88A4B2D4616C6804F467
+S315080013407024D4606C6804F4801454616C6804F4E6
+S31508001350001494616C68C4F3066414626C680835FA
+S31508001360E40F54620024184F09E02C68C4F38A4439
+S315080013701460D8E715F804C003F804C0641CD2F852
+S315080013800CC007EB1C4C9CF800C0A445F2D84029B9
+S3150800139009D041290BD0012220290CD200688A40A5
+S315080013A0C0F898200DE00068C0F8A86009E0006859
+S315080013B0C0F8B86005E0006801F01F018A40C0F86F
+S315080013C09C200020F0BD0000345800082DE9F043A9
+S315080013D093B004464C2295496846FEF7CDFF6CB19A
+S315080013E0934F2068B84202D100F5807060604FF4D0
+S315080013F0407994F89800002620B108E0012013B03F
+S31508001400BDE8F08384F89960204600F01CF920684E
+S31508001410816921F01001816100F056FA05464FF006
+S3150800142003080DE000F050FA401B0A2808D954F8C2
+S315080014309C0F40F00100206004F8048C0120DEE7D0
+S31508001440206880690007EDD42068816941F00101B0
+S31508001450816100F039FA05460DE000F035FA401BC7
+S315080014600A2808D954F89C0F40F00100206004F8B7
+S31508001470048C0120C3E720688069C007EDD0206886
+S31508001480816941F002018161207C012839D02068F8
+S31508001490816941F040018161607C012837D020686C
+S315080014A0816921F480418161A07C012835D02068BA
+S315080014B0816941F48051816120688169A26821F4BB
+S315080014C04071114381612068816921F0A40181611D
+S315080014D02068016921F010010161E068012822D025
+S315080014E030B302282BD02068816941F080018161E0
+S315080014F02068016941F010010161E068032818D0ED
+S3150800150022E02068816921F040018161C4E72068F2
+S31508001510816941F480418161C6E72068816921F4C7
+S3150800152080518161C8E72068816941F004018161C1
+S315080015300AE02068816941F02001816104E02068A1
+S31508001540816941F020018161207E401E4106E069E3
+S31508001550401E41EA0020216A491E0843A18A491E05
+S3150800156040EA01402168C861A06848450FD1E16A90
+S31508001570A06A491E401E40EA0121206B401E41EA2E
+S315080015800011A08C401E41EA00402168C860206E08
+S3150800159028B1206850F8C01F626E11430160D4E973
+S315080015A01701C842694609D0206850F8C82FA36EAB
+S315080015B022F0070251F823301A430260206C48B122
+S315080015C0206850F8BC2F636C22F0070251F82330CC
+S315080015D01A430260A06C50B1206850F8BC2FE36C27
+S315080015E022F0700251F8233042EA03120260206D9D
+S315080015F050B1206850F8BC2F636D22F4E06251F8B0
+S31508001600231042EA012101602068B84204D16068CB
+S31508001610816821F00301816044F8946FA660012077
+S315080016202071943C2046FFF75FF9E8E64458000825
+S3150800163000A000400068D0F8CC00084201D1002084
+S31508001640704701207047704790F89810012906D016
+S3150800165050F89C1F41F004010160012070470221E7
+S3150800166080F8981001688A6922F001028A610021CF
+S31508001670C0F89C10002070472DE9F05F04468946A3
+S315080016800025DFF808A19AF8140001281CD00120CB
+S315080016908AF814004FF0000BCAF818B02079C00772
+S315080016A006D001214CF25030FFF78CFA00B1012523
+S315080016B02079800706D502214CF25030FFF782FACE
+S315080016C000B101251DB15CE00220BDE8F09F20684D
+S315080016D02F4F012807D04FF0FF30C9F80000A66841
+S315080016E040F2047848E061682069FFF731FA20790A
+S315080016F0C0070AD001214CF25030FFF763FA00B157
+S315080017000125F86820F00800F8602079800738D5A8
+S3150800171002214CF25030FFF755FA00B10125D7F8EF
+S315080017200C0120F00800C7F80C012AE022693046AF
+S315080017306168FFF7EDF92079C00709D001214CF25D
+S315080017405030FFF73FFA0546F86820EA0800F860C7
+S31508001750207980070BD502214CF25030FFF732FA78
+S315080017600546D7F80C0120EA0800C7F80C0115B1A0
+S31508001770C9F8006005E0761CD4E902100844B042B6
+S31508001780D4D88AF814B028469FE70000FC00002445
+S31508001790002000520B48C16841F00101C160C168D0
+S315080017A0C9070AD000F58670016841F00101016099
+S315080017B00068C00703D00020704701207047012049
+S315080017C070470000002000522DE9F05F15460C46D0
+S315080017D00826DFF8A89099F81400012809D00120F6
+S315080017E089F81400A1F10061B1F5801F04D2012720
+S315080017F003E00220BDE8F09F02274FF0000AC9F86F
+S3150800180018A04CF2503B39465846FFF7DBF918BB8F
+S31508001810DFF86C80012F22D0D8F80C0140F00200C6
+S31508001820C8F80C01BFF36F8FBFF34F8F01CD01C40A
+S31508001830761EF6B2002EF9D1BFF36F8FBFF34F8F26
+S3150800184039465846FFF7BEF9012F0FD0D8F80C11C4
+S3150800185021F00201C8F80C1189F814A0CAE7D8F8D3
+S315080018600C0040F00200C8F80C00DBE7D8F80C10B2
+S3150800187021F00201C8F80C10EEE70000FC00002475
+S31508001880002000520D48C1680E4ACB070C4906D005
+S3150800189041604260C368DB0701D001207047D0F879
+S315080018A00C31DB0708D000F58270016002608068A1
+S315080018B0C00701D001207047002070470020005261
+S315080018C023016745AB89EFCD01F040BF10B5032072
+S315080018D000F02EF900F048FE0F490A68C2F3032308
+S315080018E00E4AD35C03F01F03D840096801F00F01C4
+S315080018F0515C0B4A01F01F0120FA01F111600949F8
+S315080019000860002000F010F808B1012010BD00F0B2
+S3150800191071F8002010BD000018440258225800082B
+S31508001920040000240000002470B504460F4D2A78F0
+S31508001930002A0CD04FF47A700D49B0FBF2F0096812
+S31508001940B1FBF0F000F0EAFE18B1012070BD0120ED
+S3150800195070BD102C07D200222146501E00F0C8F890
+S315080019606C60002070BD012070BD00000C000024D2
+S315080019700000002410B501F04DF8194C4FF4000191
+S31508001980A161184800F026FF174800F023FF2046FB
+S3150800199000F020FF154800F01DFF1548016821F0EA
+S315080019A00061016012481430016821F480710160F9
+S315080019B0001F016821F480210160082000F0E6FE7E
+S315080019C0042000F0E3FE022000F0E0FE012000F013
+S315080019D0DDFE07481C30016821F00201016010BDD8
+S315080019E000040258000C0258000802580000025869
+S315080019F0D8440258F0B587B03848016841F002016A
+S31508001A000160006800F002000090012000F0C6FEA8
+S31508001A10022000F0C3FE042000F0C0FE082000F0FB
+S31508001A20BDFE2E480C38016841F48021016000682B
+S31508001A3000F48020009029480838016841F4807134
+S31508001A400160006800F480700090802001900120F9
+S31508001A500290002403940494059401A9204F384663
+S31508001A6000F048FF4FF4005001900294059401A934
+S31508001A701C4800F03FFF4FF4407601960225029578
+S31508001A800394049405940720069001A9164800F0CB
+S31508001A9031FF019602950395049405940920069052
+S31508001AA001A9384600F026FFF000019002950320B0
+S31508001AB00390049405940A20069001A90B4800F0A7
+S31508001AC019FF06481C38016841F00061016000688A
+S31508001AD000F00060009007B0F0BD0000F444025822
+S31508001AE00004025800080258000C02580000025868
+S31508001AF0F0B40D460D4B1B68C3F30223C3F107046C
+S31508001B00042C00D90424191D072901D2002300E05A
+S31508001B10DB1E012606FA04F1491E294099409E401B
+S31508001B20761E16403143F0BC03F05FBE0CED00E0B4
+S31508001B3000F00701054A10684FF6FF03184040EA0F
+S31508001B400120034908431060704700000CED00E0CF
+S31508001B500000FA0501680122C0F8FC23002280F87B
+S31508001B60F423886940F000608861486D024A104392
+S31508001B7048650020704700000300001070470068A1
+S31508001B8041620020704770B50368586A002907D07B
+S31508001B909C6A00EB14440020491E4FF482750AE043
+S31508001BA040EA024098620DE005EB80069E5904EB78
+S31508001BB01644401CC0B28842F6D305EB810144EABC
+S31508001BC002405850002070BD10B50446012003F0AD
+S31508001BD0D7F9D4F80404BDE8104002F073B9C1EB94
+S31508001BE0C10200EB8202D0F80404926C02F0B3B88A
+S31508001BF0C1EBC10200EB8202D0F80404D2F8082235
+S31508001C0002F014B910B50446002C0CD0032084F851
+S31508001C10BD03204600F046FC204600F0D5FB002018
+S31508001C2084F8BD0310BD012010BD10B50446206818
+S31508001C3094F8BC13012906D0012184F8BC13A16AC3
+S31508001C40012902D008E0022010BDA169012903D0AC
+S31508001C50816B41F480318163206802F065FD0020C4
+S31508001C6084F8BC0310BD10B5044694F8BC030128DB
+S31508001C7009D0012084F8BC03206802F061FD002029
+S31508001C8084F8BC0310BD022010BD10B50446002020
+S31508001C9003F076F9D4F80404BDE8104002F014B94C
+S31508001CA070B504464FF0010201F00F004FF0000531
+S31508001CB00B06C0EBC00104EB810102D53C314A702A
+S31508001CC002E001F5FE714D70087094F8BC03012816
+S31508001CD008D084F8BC23206802F0E4FC84F8BC53DE
+S31508001CE0002070BD022070BD70B5044601F00F00DB
+S31508001CF06268904201D9012070BD0B064FF00102BF
+S31508001D0001F00F014FF00005C1EBC10104EB8101A1
+S31508001D1002D53C314A7002E001F5FE714D708D70B6
+S31508001D20087094F8BC03012808D084F8BC232068FE
+S31508001D3002F080FE84F8BC53002070BD022070BDFE
+S31508001D4001F00F01C1EBC10100EB8100D0F81402CC
+S31508001D5070472DE9F04104464FF0010601F00F00E7
+S31508001D604FF000050F06C0EBC00104EB810102D558
+S31508001D703C314E7002E001F5FE714D7008708A60C4
+S31508001D80CB704A7802B1C880022B00D10D7194F845
+S31508001D90BC03012809D084F8BC63206802F0D6FB8E
+S31508001DA0284684F8BC53BDE8F0810220FBE770B5ED
+S31508001DB00D4605F00F04C4EBC40100EB810101F5E3
+S31508001DC0FE71CA604B6100238B614B700C7003690E
+S31508001DD0012B00D10A612A0705D0027C006802F0AF
+S31508001DE081FE002070BD027C006802F06FFDF8E7F6
+S31508001DF070B504460D4605F00F006168884201D9A2
+S31508001E00012070BD29064FF000064FF0010206D5E5
+S31508001E10C0EBC00104EB81013C314A7006E0C5EB1A
+S31508001E20C50104EB810101F5FE714E708A700870D8
+S31508001E3094F8BC03012807D084F8BC23206802F074
+S31508001E4025FE280702D007E0022070BD217C04F594
+S31508001E507172206802F0C4FD84F8BC63002070BD6E
+S31508001E6070B50D4605F00F04C4EBC40100EB810103
+S31508001E703C31CA604B6100238B6101234B700C70A7
+S31508001E800369012B00D10A612A0705D0027C006884
+S31508001E9002F028FE002070BD027C006802F016FDE4
+S31508001EA0F8E72DE9F84F04462568284602F04CFF66
+S31508001EB000287ED1206802F073FF002879D02068B8
+S31508001EC002F06EFF800704D52068416901F002011F
+S31508001ED04161206802F064FFC10604F57170009044
+S31508001EE035D52068816921F0100181612F6A07F0D4
+S31508001EF00F00C0EBC00004EB800606F5FE76C7F3BC
+S31508001F004340022802D0062812D01BE047F6F0709C
+S31508001F10074217D0C7F30A12F1681746284602F097
+S31508001F2043FFF0683844F060B0693844B06109E0AE
+S31508001F3000990822284602F037FFB069C7F30A114C
+S31508001F400844B0612068816941F010018161206808
+S31508001F5002F026FF00034FF001084FF008094FF082
+S31508001F60100A3ED50026206802F0F9FE834635E0C1
+S31508001F705FEACB702FD02068F1B202F009FF07465E
+S31508001F80F80707D005EB4610C0F8088B31462046FF
+S31508001F9001F004F9380707D505EB4610C0F8089B89
+S31508001FA03146204601F0D6F8F80605D505EB461069
+S31508001FB000E087E1C0F808ABB80604D505EB461182
+S31508001FC02020C1F8080BB80405D505EB46114FF4D7
+S31508001FD00050C1F8080B761C4FEA5B0BBBF1000FEB
+S31508001FE0C6D1206802F0DCFE400359D5206802F00D
+S31508001FF0AFFE8346002650E05FEACB704AD02068E1
+S31508002000F1B202F0B3FE0746F80723D006F00F0137
+S3150800201008FA01F0D5F834188143C5F8341805EBE9
+S315080020204610C0F80889206901280FD1C6EBC600FA
+S3150800203004EB8000D0E911211144816436B9206D82
+S3150800204020B920680121009A02F0CAFC2046F1B2A4
+S31508002050FFF7C5FD380703D505EB4610C0F8089904
+S31508002060F80603D505EB4610C0F808A9780604D586
+S3150800207005EB46114020C1F80809B80704D505EB59
+S3150800208046110220C1F80809380603D5314620460C
+S3150800209001F0F6F8761C4FEA5B0BBBF1000FABD1EB
+S315080020A0206802F07DFE002811DAD5F8040820F031
+S315080020B00100C5F8040894F8F403012839D020462D
+S315080020C000F0A6F92068416901F0004141612068E5
+S315080020D002F066FE00050BD5D5F80808C00702D041
+S315080020E0204600F0FDF92068416901F4006141616C
+S315080020F0206802F055FE00010AD52068416901F002
+S315080021000061416194F8F403D8B1204600F0E8F97B
+S31508002110206802F045FEC00473D5D5F8040820F0FF
+S315080021200100C5F804082068102102F0EBFD002123
+S3150800213032E0002084F8F40300212046FFF71EFD54
+S31508002140C0E784F8F4832068406DC0F38300C4F8C0
+S31508002150F80301212046FFF711FDD9E705EB4110E9
+S315080021604FF67F3200F510608260036823F400138F
+S315080021700360036843F000630360C0F80822D0F8E0
+S31508002180002222F40012C0F80022D0F8002242F001
+S315080021900062C0F80022491C60688842DED8D5F87B
+S315080021A01C0840F00110C5F81C08206B60B1D5F872
+S315080021B0840840F00B00C5F88408D5F8440840F0B8
+S315080021C00B00C5F844080CE0D5F8140842F22B01B8
+S315080021D00843C5F81408D5F8100840F00B00C5F8F0
+S315080021E01008D5F8000820F4FE60C5F80008217C20
+S315080021F02068009A02F0F4FB2068416901F48051D6
+S315080022004161206802F0CCFD800415D5206802F0F3
+S31508002210DFF9206802F088FDE06000F083F9227B90
+S315080022200146206802F0FEFD204600F0CFF820683F
+S31508002230416901F400514161206802F0B1FD0007CF
+S3150800224007D5204600F0EEF82068416901F008013C
+S315080022504161206802F0A4FDC00208D5002120468D
+S3150800226000F032F82068416901F480114161206864
+S3150800227002F096FD800208D50021204600F028F8D5
+S315080022802068416901F400114161206802F088FD67
+S31508002290400007D52046FFF797FC2068416901F002
+S315080022A080414161206802F07BFD40070AD520681D
+S315080022B04568680702D52046FFF7E7FC20684168AD
+S315080022C029434160BDE8F88FD0F8040401F05ABEEE
+S315080022D0D0F8040401F058BE2DE9F0418AB004464E
+S315080022E0002C05D0266894F8BD03002520B108E027
+S315080022F001200AB0BDE8F08184F8BC53204600F0FE
+S3150800230064F8032084F8BD03F06BC00500D425618A
+S31508002310206802F0D5FA04F110016846282288469A
+S31508002320FEF72AF894E80F0002F060F9022718B1C0
+S3150800233084F8BD730120DCE72068002102F043FD24
+S31508002340002101260DE0C1EBC10004EB80003C3002
+S3150800235046700170C180C5708560C5604561491CBD
+S31508002360C9B260688842EED800210DE0C1EBC10011
+S3150800237004EB800000F5FE7045700170C57085603D
+S31508002380C5604561491CC9B260688842EED82822F2
+S3150800239041466846FDF7F0FF94E80F0002F0DCF9C5
+S315080023A018B184F8BD730120A3E784F8385084F87F
+S315080023B0BD63606A012802D12046FFF7CBFB20687F
+S315080023C002F0BEF9002094E77047704770B50446DE
+S315080023D00125E068002810D0022803D0912108A022
+S315080023E0FEF739F8D4F80404294601F023FED4F898
+S315080023F00404BDE8704001F0DEBD0025F2E70000E8
+S315080024002E2E5C757362645F636F6E662E630000C2
+S3150800241010B5044602F0EAFED4F80404BDE81040FC
+S3150800242001F0F2BDD0F8040401F0F8BD10B5044679
+S3150800243094F8BC0301280BD0012084F8BC0384F867
+S315080024403810206802F0D7FC002084F8BC0310BDC1
+S31508002450022010BDD0F8042400F57171104601F071
+S31508002460F5BD10B50446206894F8BC13012906D0BA
+S31508002470012184F8BC13A16A012902D008E00220D0
+S3150800248010BDA169012903D0816B41F480318163B4
+S31508002490206802F049F9206802F01EFC002084F842
+S315080024A0BC0310BD70B5044694F8BC0301280ED0D1
+S315080024B0012084F8BC03206802F002FA206802F0C2
+S315080024C02BFD002528B184F8BC53012070BD0220DD
+S315080024D070BD206802F034F984F8BC53002070BD42
+S315080024E010B50446D4F8040401F0F8FD2068D0F8C5
+S315080024F0001E41F00101C0F8001E206A20B1044800
+S31508002500016841F006010160BDE8104002F039BDDE
+S3150800251010ED00E00248016841F0807101607047E3
+S315080025200C48025800B500F01FF80B490A68C2F3B8
+S3150800253003230A4AD35C03F01F03D840096801F055
+S315080025400F01515C064A01F01F0120FA01F11160E2
+S31508002550044A1060084600BD18440258225800086C
+S31508002560040000240000002430B564480068654C67
+S3150800257010F03801624808D0021108290DD0102938
+S315080025800DD018290DD0104630BD21688906FBD517
+S315080025902168C1F3C101C84030BD104630BD5A4854
+S315080025A030BD564918310A6802F003020968C1F3BA
+S315080025B00511524B1C331B6803F001034F4D24359C
+S315080025C02D68C5F3CC0515FB03F300EE103AB8EEFB
+S315080025D0400A002977D0DFED4D0A484BB7EE001ABE
+S315080025E020333AB39FED4A2A012A58D0022A6CD0E2
+S315080025F001EE901A1868F8EE611AC2EE212AC0F3A5
+S31508002600080001EE900AF8EE611A40EE201A31EE43
+S31508002610810A22EE800A1868C0F34620401C00EEA4
+S31508002620900AF8EE600A80EE201ABCEEC10A10EE97
+S31508002630100A30BD226892061BD52268C2F3C10271
+S31508002640D04001EE900A1868F8EE612A01EE901A59
+S31508002650F8EE611A82EEA12AC0F3080001EE900A8C
+S31508002660F8EE611A40EE201A31EE810A22EE000ACF
+S31508002670D1E701EE901ADFED272A1868F8EE611AFD
+S3150800268082EEA12AC0F3080001EE900AF8EE611A5C
+S3150800269040EE201A31EE810A22EE000ABBE701EE6F
+S315080026A0901A1868F8EE611AC2EE212AC0F30800DB
+S315080026B001EE900AF8EE611A40EE201A31EE810A10
+S315080026C022EE800AA7E716E0FFE701EE901ADFED93
+S315080026D0122A1868F8EE611A82EEA12AC0F30800D9
+S315080026E001EE900AF8EE611A40EE201A31EE810AE0
+S315080026F022EE000A8FE7002030BD00001044025881
+S315080027000090D0030044025800127A0000000039F5
+S315080027100024744A0024744C0024F44A10B5401E60
+S31508002720B0F1807F01D3012010BD4FF0E024606135
+S315080027300F21601703F059F80020A06107202061D7
+S31508002740002010BD10B5FFF7C1F8BDE8104000F035
+S31508002750EDBEF0B500230A2530263727002412E0FF
+S31508002760B5EB107F04D906EB107C01F813C003E023
+S3150800277007EB107C01F813C0000101EB430C8CF841
+S3150800278001405B1CDBB29342EAD3F0BD02490A68FA
+S3150800279082430A6070470000E044025808B50449BD
+S315080027A00A6802430A6009680140009108BD0000F2
+S315080027B0E044025802490A6802430A60704700006A
+S315080027C08844025802490A6882430A607047000032
+S315080027D08844025870B500243B49884206D1012036
+S315080027E0FFF7E8FF0120FFF7EDFF6AE03749884267
+S315080027F006D10220FFF7DEFF0220FFF7E3FF60E0C5
+S315080028003349884206D10420FFF7D4FF0420FFF796
+S31508002810D9FF56E02F49884206D10820FFF7CAFF9C
+S315080028200820FFF7CFFF4CE02B49884206D110203D
+S31508002830FFF7C0FF1020FFF7C5FF42E0274988428F
+S3150800284006D12020FFF7B6FF2020FFF7BBFF38E0B0
+S315080028502349884206D14020FFF7ACFF4020FFF706
+S31508002860B1FF2EE01F49884206D18020FFF7A2FF5C
+S315080028708020FFF7A7FF24E01B49884208D14FF4C0
+S3150800288080752846FFF796FF2846FFF79BFF18E056
+S315080028901649884208D14FF400752846FFF78AFF83
+S315080028A02846FFF78FFF0CE01149884208D14FF4FC
+S315080028B080652846FFF77EFF2846FFF783FF00E07E
+S315080028C00124204670BD000000000258000402588A
+S315080028D000080258000C025800100258001402584A
+S315080028E000180258001C02580020025800240258FA
+S315080028F000280258F0B50A6892FAA2F2B2FA82F4EF
+S3150800290053E00123A3401A40CAB34B68012B01D0F8
+S31508002910022B10D18D68134686685B4303EB430789
+S315080029206B43BE431E438660CD680B6846689E436C
+S315080029306B431E4346600D691346D0F80CC05B43D3
+S315080029401E4603EB43076B432CEA070C4CEA030CC1
+S31508002950C0F80CC04B68022B20D1FF2A10D84D694D
+S31508002960D0F820C006FB02F35343C3EB03126B43B4
+S315080029702CEA020C4CEA030CC0F820C00EE013E067
+S315080029804B69150A05FB05F26A436A43456AC2EBB9
+S31508002990021C5A4325EA0C05154345624A68036832
+S315080029A05643BB4333430360641C0A6832FA04F394
+S315080029B0A7D10020F0BD000002480068C0F300203F
+S315080029C07047000000440258DDED000A00EE100AC8
+S315080029D09FED0F2AB8EE401A00EE101AB8EE400A1C
+S315080029E0C1EE001A00EE102AB8EE401A00EE103AB0
+S315080029F0B8EE400A00EE021A21EE810AB8EE601A15
+S31508002A00C0EE010ABCEEE00A10EE100A704700009C
+S31508002A100000003970B5264D286840F0010028608E
+S31508002A2000F078FA0028FBD0214800241030046012
+S31508002A30286820490840286000F07CFA0028FBD165
+S31508002A4000F080FA0028FBD100F084FA0028FBD1B8
+S31508002A50174818300460001D0460001D04601449FE
+S31508002A60154828310860091D14480860091D1448CE
+S31508002A700860091D0C60091D0860091D0C60091D08
+S31508002A800860081D0460286820F48020286008482B
+S31508002A906030046006486830016840F2FF721143EE
+S31508002AA001600348D030016841F48031016070BD8F
+S31508002AB00044025845EDF6EA000202020000FF0152
+S31508002AC080020101064AC1B21144030E0A68C0F326
+S31508002AD004218B401A40CA4040EA02407047000071
+S31508002AE04C4402582DE9F84F044600250027374E76
+S31508002AF0306800F00300002804D001280BD0022813
+S31508002B0012D10DE000F006FA70B100F0FBF9304D75
+S31508002B10C008C54008E0FFF74FFF28B12D4D03E078
+S31508002B2000F0E8F900B12C4D002020606060A0603C
+S31508002B303068C0F30518254E08363068C0F3080912
+S31508002B4009F10109A6F1040ADAF80000C0F3000049
+S31508002B5018B1301D0068C0F3CC07B8F1000F33D0A8
+S31508002B60DAF80000C0F3004058B13068C0F34620D8
+S31508002B70401C3B464A46414600902846FFF724FF3C
+S31508002B802060DAF80000C0F3404058B13068C0F35E
+S31508002B900640401C3B464A46414600902846FFF7F9
+S31508002BA013FF6060DAF80000C0F3804000280BD0FD
+S31508002BB03068C0F30660401C3B464A4641460090D2
+S31508002BC02846FFF701FFA060BDE8F88F28440258A1
+S31508002BD00090D00300093D0000127A002DE9F84F55
+S31508002BE0044600250027384E306800F00300002808
+S31508002BF004D001280BD0022812D10DE000F08AF982
+S31508002C0070B100F07FF9314DC008C54008E0FFF704
+S31508002C10D3FE28B12E4D03E000F06CF900B12D4D1E
+S31508002C20002020606060A0603068C0F30538264E3A
+S31508002C3010363068C0F3080909F10109DFF888A0E1
+S31508002C400AF1040ADAF80000C0F3001018B1301DC2
+S31508002C500068C0F3CC07B8F1000F33D0DAF80000EB
+S31508002C60C0F3C04058B13068C0F34620401C3B460C
+S31508002C704A46414600902846FFF7A6FE2060DAF845
+S31508002C800000C0F3005058B13068C0F30640401C3D
+S31508002C903B464A46414600902846FFF795FE606047
+S31508002CA0DAF80000C0F3405000280BD03068C0F3B3
+S31508002CB00660401C3B464A46414600902846FFF7B8
+S31508002CC083FEA060BDE8F88F284402580090D00320
+S31508002CD000093D0000127A002DE9F84F0446002548
+S31508002CE00027394E306800F00300002804D0012878
+S31508002CF00BD0022812D10DE000F00CF970B100F0EB
+S31508002D0001F9324DC008C54008E0FFF755FE28B165
+S31508002D102F4D03E000F0EEF800B12E4D00202060A4
+S31508002D206060A0603068C0F30558274E18363068D2
+S31508002D30C0F3080909F10109DFF88CA00AF1040AB1
+S31508002D40DAF80000C0F3002018B1301D0068C0F39F
+S31508002D50CC07B8F1000F35D0002D33D0DAF80000D3
+S31508002D60C0F3805058B13068C0F34620401C3B463B
+S31508002D704A46414600902846FFF726FE2060DAF8C4
+S31508002D800000C0F3C05058B13068C0F30640401C7C
+S31508002D903B464A46414600902846FFF715FE6060C6
+S31508002DA0DAF80000C0F3006000280BD03068C0F3E2
+S31508002DB00660401C3B464A46414600902846FFF7B7
+S31508002DC003FEA060BDE8F88F284402580090D0039F
+S31508002DD000093D0000127A000248006800F470609D
+S31508002DE07047000018440258FEB50024FFF76AFE33
+S31508002DF03A4A4FF440764FF48033811A90424FF4A2
+S31508002E007D4560D022DC364A9042A0EB020109D00B
+S31508002E1010DC344DA0F1E060083842D0B0422ED024
+S31508002E2098422AD100F08EF838B36846FFF7D6FEE6
+S31508002E30019C22E0A94201D099421ED100F08AF8ED
+S31508002E40D8B16846FFF748FF019C16E0264A881A5B
+S31508002E50914204D008DCB14235D099420DD1FFF732
+S31508002E60ABFD50B1214C08E0A84201D0984204D1EC
+S31508002E7000F058F808B14FF400442046FEBD00F0B3
+S31508002E807BFA0446FFF7A8FFC0F30320285C00F08E
+S31508002E901F0024FA00F000F041FA00F05DFA04463B
+S31508002EA0EBE700F069FA0446FFF796FFC0F3032044
+S31508002EB0285C00F01F0024FA00F000F02FFA00F05A
+S31508002EC03BFA0446D9E700F025F80028D5D000F0EB
+S31508002ED019F8074CC008C440CFE7000008000307EC
+S31508002EE008030107905800080003010000093D0087
+S31508002EF00090D00302480068C0F3404070470000C5
+S31508002F00004402580248006800F0180070470000A4
+S31508002F100044025802480068C0F380007047000069
+S31508002F200044025802480068C0F340007047000099
+S31508002F307044025802480068C0F3406070470000B9
+S31508002F400044025802480068C0F3C0607047000099
+S31508002F500044025802480068C0F3407070470000F9
+S31508002F600044025803490A6822F00F0202430A6025
+S31508002F70704700001844025801490860704700006D
+S31508002F80000000242DE9F04104460D4601260020E4
+S31508002F902168C1F3000100296ED12A69A968EB6985
+S31508002FA011436A691A43114322683E4B1A4011437A
+S31508002FB02160E968626822F440520A436260A9699E
+S31508002FC0A26822F440720A43A2603749374B8C4202
+S31508002FD003D11846FFF708FF30E0354A35499442D1
+S31508002FE003D10846FFF700FF28E0334A944203D18D
+S31508002FF00846FFF7F9FE21E0304A944203D1084615
+S31508003000FFF7F2FE1AE02E4A944203D10846FFF76C
+S31508003010EBFE13E02B4A944203D11846FFF7E4FE71
+S315080030200CE0294A944203D10846FFF7DDFE05E085
+S31508003030264A944202D10846FFF7D6FEA8B1696827
+S3150800304099B10026EB692A680B2A0ED8204FB3F5EA
+S31508003050004F14D0D2B257F82220B0FBF2F000EBA2
+S315080030605100B0FBF1F080B2E0602888E16A80B2D6
+S3150800307021F00F010143E1623046BDE8F081D2B28A
+S3150800308057F82220B0FBF2F0400000EB5100B0FBED
+S31508003090F1F080B24FF6F0710140C0F342000143EF
+S315080030A0E160E2E7F369FFEF00100140080300075B
+S315080030B0004400400800000700480040004C00405B
+S315080030C0005000400014014000780040007C004099
+S315080030D0A058000802494FF40000886170470000B4
+S315080030E0000402580149488070470000180000246F
+S315080030F010B500F02BFB0B4C616888420CD3207886
+S31508003100094950B1002020704FF40000886100F092
+S315080031101DFB61880844606010BD01202070802076
+S315080031208861F4E7180000240004025810B5FDF77A
+S3150800313069FF18B1BDE81040FDF7F2BD002010BDCB
+S31508003140FDF70ABEFDF792BEFDF794BEFDF7D0BEA9
+S31508003150FDF7E6BE70B504462068056C00EB411025
+S31508003160D0F8081B0C4EB54205D9090403D54FF40F
+S315080031700041C0F8081B2046FFF76CF9B54208D98C
+S315080031802069012805D12068012104F5717201F032
+S3150800319027FC002070BD00000A30544F2DE9F0418D
+S315080031A004460D462668316C06EB4510D0F8083BF8
+S315080031B04FF40047D4F8108004F571724FF0200CD4
+S315080031C0B8F1010F08D0DFF8B080414545D11904A0
+S315080031D03AD5C0F8087B4CE0284E5FEA037806D556
+S315080031E0B14246D9190444D5C0F8087B41E05FEAE4
+S315080031F0836802D5C0F808CB3BE013F0280F38D116
+S31508003200B14204D9190402D5C0F8087B31E0C5EBF0
+S31508003210C501D0F8100B04EB810101F501710B68AB
+S31508003220C0F31200181A086148681844486035B98E
+S31508003230D4F8100218B92068012101F0D1FB204604
+S31508003240E9B2FEF7D5FC14E0990601D5C0F808CB1B
+S315080032502046E9B2FEF7CCFC0BE035B9D4F81002EB
+S3150800326018B90021304601F0BBFB2046E9B2FEF74B
+S31508003270BFFC0020BDE8F0810A31544F0A30544F94
+S315080032802DE9F84F80460E46D8F80070C6EBC60002
+S3150800329008EB80043C34D4E90510884202D90120A1
+S315080032A0BDE8F88F081AA168814200D20846C01CFA
+S315080032B04FEA900A07EB461916E0151AA268AA42C1
+S315080032C000D21546E81C4FEA900A98F810000090BC
+S315080032D0ABB2E1683846F2B201F03FFEE068284436
+S315080032E0E060A0692844A061D9F8180980B2504561
+S315080032F005D3D4E90520904201D2002ADDD1D4E9CC
+S315080033000501884208D8012006F00F018840D7F841
+S3150800331034188143C7F834180020C1E704490968FE
+S3150800332001F00F01034A515C01F01F01C8407047C4
+S3150800333018440258905800080549096801F07001B8
+S31508003340044A0909515C01F01F01C8407047000092
+S315080033501C440258905800080549096801F4E061C0
+S31508003360044A090A515C01F01F01C8407047000071
+S315080033701C440258905800080EB500200D490968EB
+S3150800338001F0380100290AD008290ED010290ED0DC
+S31508003390182903D16846FFF7A5FB00980EBDFFF76D
+S315080033A0B1FDC1080448C8400EBD04480EBD044816
+S315080033B00EBD0000104402580090D00300093D00DD
+S315080033C000127A0010B588B00D4C206820F0010074
+S315080033D02060002100914FF4614001900291039111
+S315080033E004910C2005900691079169462046FFF73F
+S315080033F0C9FD206840F00100206008B010BD00003B
+S3150800340000480040024600200449CB69C3F3401334
+S31508003410002B02D0486A107001207047004800400F
+S315080034202DE9F04180460F461B4C00251B4E60785F
+S31508003430002810D020783044401CFFF7E3FF01280D
+S3150800344019D000F083F961686431884200D9657043
+S315080034500020BDE8F0811148FFF7D4FF0128F7D115
+S315080034603078401E3F28F3D800F070F96060257068
+S3150800347001206070ECE72078401CC2B222703078D8
+S3150800348031469042E4D1491C4046FDF7E6F965709D
+S31508003490207838700120DCE7E80000249410002426
+S315080034A070B5094DA86200F051F900F10A0405E06B
+S315080034B0FDF7C9F900F04AF9A04204D8E869C0F353
+S315080034C0C0100028F4D070BD0048004070B505460D
+S315080034D00E46402E03D9842108A0FCF7BCFF3046CF
+S315080034E0FFF7DEFF002406E0FDF7ADF9285DFFF7DC
+S315080034F0D7FF641CA4B2B442F6D370BD2E2E5C2E40
+S315080035002E5C2E2E5C2E2E5C536F757263655C41A5
+S31508003510524D434D375F53544D333248375C7273BF
+S315080035203233322E630000007047000010B55A4847
+S31508003530016821F00F0141F004010160006800F004
+S315080035400F00042803D0672154A0FCF784FF5648CF
+S31508003550016821F0070141F00201016052480C3070
+S31508003560016841F4404101605049086840F48020F0
+S315080035700860086840F4803008600868C0F3404076
+S315080035800028FAD0494A2832106820F0030040F093
+S3150800359002001060101D036843F48033036003685B
+S315080035A043F400330360036823F00C0343F0040379
+S315080035B00360036823F002030360106820F47C703C
+S315080035C040F04000106039483030026840F2DF139E
+S315080035D06FF308021A430260026822F47E4242F43C
+S315080035E000720260026822F4FE0242F49812026037
+S315080035F0026822F0FE4242F080720260086840F0DB
+S31508003600807008600868C0F340600028FAD0082077
+S31508003610FFF7A8FC25481030016821F0070141F0A2
+S3150800362003010160214C1834206820F47060206082
+S315080036300820FFF797FC201D016821F0700141F072
+S3150800364040010160016821F4E06141F48061016094
+S31508003650206820F0700040F04000206013482030B9
+S31508003660016821F0700141F0400101600F485430B3
+S31508003670016821F007010160011F0A6822F0405223
+S315080036800A60016821F4401141F480110160BDE827
+S3150800369010400748FFF770BC002000522E2E5C6DC4
+S315080036A061696E2E630000000C48025800440258F7
+S315080036B000389C1C2048016841F4700101601F49CC
+S315080036C0086840F0010008601C4A002010321060AB
+S315080036D00A681B4B1A400A60184A18321060121DF5
+S315080036E01060121D1060154A28321060121D1060F5
+S315080036F0121D1060121D1060121D1060121D106040
+S31508003700121D1060121D10600A6822F480220A60D9
+S315080037100A49603108600B4800686FF30F00B0F182
+S31508003720005F02D20849012008604FF00060024994
+S31508003730803908607047000088ED00E000440258B0
+S315080037407FEDF6EA0010005C0881005100B500F034
+S315080037501FF80148006800BDF000002400B500F01D
+S315080037600FF84FF0E02004494161002181610522EC
+S3150800377002610248016000BDFF520700F000002404
+S315080037804FF0E0200021016141618161704700002E
+S315080037904FF0E0200069C00303D502480168491CC0
+S315080037A001607047F000002410B501F0E7FD002025
+S315080037B010BD084610B501F061FD002010BD70B5BA
+S315080037C0054600242846812100F0BCFA0121284636
+S315080037D000F0B8FA204670BD0A21018000487047FB
+S315080037E0240000242021018000487047300000246E
+S315080037F0004870471801002470B50546002428467D
+S3150800380040230222812100F0C1FB402328460222E0
+S31508003810012100F0BBFB044A40230121284600F0A1
+S31508003820C1FB204670BD00001801002410B590F8B1
+S315080038309C02032801D101F0A1FD002010BD000063
+S3150800384070B51722174C0B7813F0600F22D14B78FE
+S31508003850062B04D00A2B11D00B2B1BD114E04B8856
+S315080038602125B5EB132F05D10E4C0934CA88172A22
+S3150800387000D91722214600F058F80BE00949012221
+S31508003880193900F052F805E04A8812F0FF0F03D004
+S3150800389000F034F8002070BD0249D0B2193908602A
+S315080038A0F8E700003900002410B5D0F8B4225268B1
+S315080038B09047002010BD90F89C22012A05D0022AC4
+S315080038C003D0032A01D000F019B84988012904D188
+S315080038D00021C0F8A41200F035B8704710B5134699
+S315080038E00A46002100F05EFB002010BD10B5134605
+S315080038F00A46002100F0FAFB002010BD10B5044668
+S315080039008021204600F0CFFB2046BDE8104000216C
+S3150800391000F0C9BB10B50521C0F8941200231A4659
+S31508003920194600F03FFB002010BD10B50223C0F871
+S315080039309432C261026213460A46002100F0D6FBA1
+S31508003940002010BD10B50421C0F8941200231A46B1
+S31508003950194600F0CBFB002010BD10B50446012027
+S3150800396084F89C02D4F8B40221794268204690472C
+S31508003970204600F0AAFB204600F09BFA002010BD66
+S3150800398010B5002806D007A00A46054900F08AF9AE
+S31508003990034810BD03A00A46014900F083F9F7E77A
+S315080039A06005002444656661756C74001220088001
+S315080039B000487047A800002410B5002806D007A0C4
+S315080039C00A46054900F06EF9034810BD03A00A46E9
+S315080039D0014900F067F9F7E76005002457696E5555
+S315080039E053422042756C6B20496E7465726661633A
+S315080039F0650000000420088000487047A4000024E1
+S31508003A0010B504A00A46024900F04CF9004810BD5A
+S31508003A10600500244F70656E424C542055736572DC
+S31508003A200000000010B5002806D007A00A46054980
+S31508003A3000F038F9034810BD03A00A46014900F012
+S31508003A4031F9F7E76005002457696E55534220425D
+S31508003A50756C6B20446576696365000010B51A209D
+S31508003A600880FDF7F1FA014810BD0000BC000024EB
+S31508003A700A46D188012902D01146FFF73FBF90F8C0
+S31508003A809C12012906D0022904D0032909D011461F
+S31508003A90FFF734BF00218160012200F10801FFF71A
+S31508003AA044BF0122011DFFF740BF2DE9F843044634
+S31508003AB00F4600200090002600257888010A08296C
+S31508003AC070D2DFE801F0AB040C22ABAB8B9AD4F8CA
+S31508003AD0B012207C0A68694690470646A3E0207C17
+S31508003AE04FF0020840B1D4F8B402C16A6846884764
+S31508003AF0064686F8018096E0D4F8B402816A6846DC
+S31508003B008847064686F801808DE0C0B206285FD24F
+S31508003B10DFE800F0031221303F4FD4F8B0024268C4
+S31508003B2022B1207C6946904706467CE03946204605
+S31508003B30FFF7E4FE012576E0D4F8B002826822B1E8
+S31508003B40207C6946904706466DE039462046FFF7D1
+S31508003B50D5FE012567E0D4F8B002C26822B1207C00
+S31508003B606946904706465EE039462046FFF7C6FE98
+S31508003B70012558E0D4F8B002026922B1207C6946D2
+S31508003B80904706464FE039462046FFF7B7FE01251F
+S31508003B9049E0D4F8B00242692AB1207C69469047C8
+S31508003BA0064640E03AE039462046FFF7A7FE0125DB
+S31508003BB039E0D4F8B002826922B1207C6946904780
+S31508003BC0064630E039462046FFF798FE01252AE0EA
+S31508003BD039462046FFF792FE012524E0207C28B1CD
+S31508003BE039462046FFF78AFE01251CE0D4F8B402C0
+S31508003BF0416B68468847064615E0207C28B1394659
+S31508003C002046FFF77BFE01250DE0D4F8B402016BD0
+S31508003C106846884706460721717004E039462046FB
+S31508003C20FFF76CFE0125002D12D1BDF8000048B142
+S31508003C30FA883AB1824200D90246009231462046B5
+S31508003C40FFF773FEF888002802D12046FFF77AFEB0
+S31508003C50BDE8F883002102E0491CC9B2401C02787D
+S31508003C60002AF9D1084670470A4690F89C1201299D
+S31508003C7006D0022904D0032902D01146FFF73EBE1A
+S31508003C80D188022902D01146FFF738BE0121C1604A
+S31508003C90D0F8A41209B10321C160022200F10C0177
+S31508003CA0FFF743BE70B504460D461646002C17D0DE
+S31508003CB02046FFF7CFFF022101EB40003080307825
+S31508003CC02870032102206970002306E0411C641C49
+S31508003CD02A54C9B2481CC0B26B542278002AF5D1BE
+S31508003CE070BD01460020002906D0012905D0022909
+S31508003CF005D0032905D0022070470220704701200D
+S31508003D0070470220704710B5002810D0D0F8B4329A
+S31508003D1013B10023C0F8B43209B1C0F8B0120121BA
+S31508003D2080F89C12027000F0DFF8002010BD022017
+S31508003D3010BD10B5D0F8C002FDF7D6FFBDE810409B
+S31508003D40FFF7CFBF10B5D0F8C002FDF7A9FFBDE851
+S31508003D501040FFF7C6BF70B504461346002909D0C0
+S31508003D60D4F8B40242691AB194F89C02032859D0CF
+S31508003D70022070BD04F11400D4F89412002502291B
+S31508003D8003D0042940D0F1B342E0D0E903218A42A6
+S31508003D900DD9511AC1608AB219462046FFF7A6FD09
+S31508003DA0002320461A46194600F0FCF830E08068E1
+S31508003DB0B0FBF1F201FB12029AB9884211D3D4F88A
+S31508003DC0981288420DD2002220461146FFF78EFD32
+S31508003DD0C4F8985200231A461946204600F0E2F81D
+S31508003DE016E0D4F8B402C16829B194F89C020328F5
+S31508003DF001D1204688478021204600F054F9204604
+S31508003E00FFF788FD04E0FFE78021204600F04BF924
+S31508003E1094F8A002012807D1204600F08DF984F80D
+S31508003E20A05201E020469047002070BD70B50446B8
+S31508003E3008461146002809D0D4F8B4128A691AB17E
+S31508003E4094F89C1203292FD0022070BD04F5AA709D
+S31508003E50D4F89432032B02D0052B1DD027E0D0E9E5
+S31508003E6003539D420AD9EB1AC3600069834200D303
+S31508003E70034620469AB2FFF731FD18E0D4F8B4029B
+S31508003E80016929B194F89C02032801D12046884784
+S31508003E902046FFF757FD0AE00020C4F894020021E7
+S31508003EA0204600F000F902E001462046904700202F
+S31508003EB070BD10B5D0F8C002FDF7A4FEBDE81040ED
+S31508003EC0FFF70FBF0020704710B5012180F89C123C
+S31508003ED0D0F8B422017952689047002010BDD0F876
+S31508003EE0C002FDF72DBF000010B5017800292BD1BF
+S31508003EF01649C1F80404C0F8C0121548086009201C
+S31508003F0048600222CA60002008618A610122CA61EB
+S31508003F10086248628862C86208630846FEF7DCF9E8
+S31508003F2020B10CA04FF49371FCF795FA074880214D
+S31508003F30FDF725FE054840220021FDF724FE03482B
+S31508003F4080220121FDF71FFE002010BD5801002424
+S31508003F50000008402E2E5C757362645F636F6E66A0
+S31508003F602E6300000A06D0F8C00201F07F01C1EBFB
+S31508003F70C10100EB810002D590F83E00704790F829
+S31508003F80FE017047002070470020704710B51446A0
+S31508003F901A46D0F8C0022346FDF7DBFEBDE81040FE
+S31508003FA0FFF79FBE10B5D0F8C002FDF700FFBDE8C9
+S31508003FB01040FFF796BE70B50446002220464023FF
+S31508003FC01146FFF7E3FF0125C4F858514026C4F807
+S31508003FD064614023204600228021FFF7D7FFA561B0
+S31508003FE0666284F89C520020C4F894026060C4F8A3
+S31508003FF0A402D4F8B80228B1D4F8B4020021426861
+S3150800400020469047002070BD90F89C12042903D1E1
+S3150800401090F89D1280F89C120020704710B590F811
+S315080040209C12032904D1D0F8B412C96901B1884792
+S31508004030002010BD01740020704710B5D0F8C002EA
+S31508004040FEF7F4F9BDE81040FFF74BBE70B504461D
+S3150800405004F52A70054600F052F80120C4F89402C7
+S31508004060B4F8AE02C4F8980294F8A82212F01F0019
+S315080040700AD001280DD0022810D002F0800120466F
+S3150800408000F011F8002070BD2946204600F001F91D
+S31508004090F8E72946204600F023FAF3E729462046A2
+S315080040A000F02CF9EEE710B5D0F8C002FDF7A0FE37
+S315080040B0BDE81040FFF715BE10B5D0F8C002FEF7F0
+S315080040C0D0F9BDE81040FFF70CBE10B5D0F8C00215
+S315080040D0FEF7E8F9BDE81040FFF703BE00F52770C4
+S315080040E001784170042101700020704710B5D0F89E
+S315080040F0C002FDF7B5FEBDE81040FFF7F2BD0A782D
+S3150800410002704A784270CB788A7802EB03224280A2
+S315080041104B790A7902EB032282808A79C97902EB04
+S315080041200121C180704702460020002902D0C2F84A
+S31508004130B4127047022070470020704770B50446D5
+S315080041408888002821D1C888F8B9488880281CD2D0
+S3150800415000F07F0594F89C0203280DD084F89E523F
+S3150800416029462046FFF769FF2046FFF7EBFB45B1D6
+S31508004170022084F89C0270BD2046BDE87040FFF717
+S31508004180BDBB012084F89C0270BD2046BDE8704086
+S31508004190FFF7B4BB10B50224D0F8B422002A03D026
+S315080041A01268904700B90024204610BD70B5044631
+S315080041B00E46304DB1782970012905D93146204679
+S315080041C0BDE87040FFF79ABB94F89C0202280BD012
+S315080041D0032823D031462046FFF790FB297820464E
+S315080041E0BDE87040FFF760BB99B16160032084F8B1
+S315080041F09C022046FFF7CEFF022804D02046BDE8E1
+S315080042007040FFF79FBB31462046BDE87040FFF778
+S3150800421075BB2046BDE87040FFF794BB91B1606856
+S31508004220884221D0C1B22046FFF73EFB297861605B
+S315080042302046FFF7AFFF022810D02046BDE87040A1
+S31508004240FFF780BB022084F89C0261602046FFF7D6
+S315080042502BFB2046BDE87040FFF774BB314620466D
+S31508004260BDE87040FFF74ABB2046BDE87040FFF73F
+S3150800427069BB0000080000244988012903D1C0F859
+S31508004280A412FFF75FBB704710B5FFF715FF0020B4
+S3150800429010BD10B500240A7812F060020CD0202A4E
+S315080042A005D0402A03D0FFF729FB204610BDD0F8D9
+S315080042B0B42292689047F8E74A780A2A1BD2DFE8C0
+S315080042C002F011171A141A08051A0E0BFFF7EDFB60
+S315080042D0EBE7FFF733FFE8E7FFF768FFE5E7FFF7E8
+S315080042E0C7FBE2E7FFF7C0FCDFE7FFF7C5FFDCE740
+S315080042F0FFF7E1FAD9E7FFF701FBD6E72DE9F04129
+S3150800430004460A4600261179137813F0600011D086
+S31508004310202808D0402806D011462046FFF7EEFA96
+S315080043203046BDE8F081D4F8B402114683682046C9
+S315080043309847F5E7C3F3411001280BD050780028B9
+S3150800434060D0012837D003280CD011462046FFF745
+S31508004350D5FAE5E7D4F8B402114683682046BDE8E5
+S31508004360F041184794F89C02022806D0032814D076
+S3150800437011462046FFF7C2FAD2E749B1802907D08D
+S315080043802046FFF790FE80212046FFF78CFEC7E700
+S3150800439011462046FFF7B2FAC2E7508838B931B15C
+S315080043A0802904D0D08810B92046FFF77CFE204625
+S315080043B0FFF7C8FAB4E794F89C02022806D0032847
+S315080043C014D011462046FFF799FAA9E749B1802982
+S315080043D007D02046FFF767FE80212046FFF763FED9
+S315080043E09EE711462046FFF789FA99E75088002884
+S315080043F096D1480602D02046FFF79BFC2046FFF7D9
+S31508004400A1FA8DE794F89C020027022806D0032813
+S3150800441024D011462046FFF771FA81E731B1802989
+S3150800442004D011462046FFF769FA79E7080607D54A
+S3150800443001F07F0000EB800004EB8001143107E0F7
+S3150800444001F07F0000EB800004EB800101F5AA7102
+S315080044500F6002222046FFF768FA61E708060CD5C6
+S3150800446001F00F0000EB800004EB8000806968B95A
+S3150800447011462046FFF742FA52E701F00F0000EB1B
+S31508004480800004EB8000D0F8580148B108060CD526
+S3150800449001F07F0000EB800004EB800514350CE08A
+S315080044A011462046FFF72AFA3AE701F07F0000EBAB
+S315080044B0800004EB800505F5AA7541B1802906D070
+S315080044C02046FFF74FFD20B10120286002E02F604B
+S315080044D000E02F60022229462046FFF726FA1FE74A
+S315080044E070B505460C46207810F0600209D0202ADF
+S315080044F007D0402A05D021462846FFF7FFF90020B5
+S3150800450070BD95F89C22012A08D0022A06D0032AF3
+S3150800451004D021462846FFF7F1F9F0E7207901286B
+S315080045200ED8D5F8B4022146826828469047E18815
+S315080045300029E4D10028E2D12846FFF703FADEE78E
+S3150800454021462846FFF7DAF9D9E7000070B50A7858
+S3150800455001234E7802F00F041C4DA340012E19D0FA
+S31508004560D0F81C4844EA0343C0F81C3800EB421054
+S31508004570D0F8002B12040BD4D0F8002B0B89C9787D
+S31508004580C3F30A031A4345EA81410A43C0F8002BDC
+S31508004590002070BDD0F81C489BB21C43C0F81C48CC
+S315080045A000EB4210D0F800391B04F1D4D0F80039DA
+S315080045B00C89C978C4F30A048904234341EA825161
+S315080045C00B432B43C0F80039E2E7000000800010D7
+S315080045D0D0F800196FF30A01C0F80019D0F80418CA
+S315080045E041F48071C0F80418002070470FB410B564
+S315080045F00446089801281AD0E06840F04000E060B8
+S31508004600204600F033F80C9941B3A16B21F48031B0
+S31508004610A1630699012907D1A16841F00601A160A5
+S31508004620A16841F02001A16010BC5DF814FBA06BE5
+S3150800463020F48030A063E0680B490840E060E06839
+S3150800464020F44010E0600F98012803D1E06840F498
+S315080046508010E060204600F009F8DAE7A16B41F423
+S315080046608031A163D5E70000BFFFBDFF00210C4ADA
+S31508004670491C914201D9032070470369002BF7DAD8
+S315080046800021036943F001030361491C914201D9E2
+S31508004690032070470369DB07F7D100207047000045
+S315080046A0400D030070B50B7801244E7803F00F0512
+S315080046B004FA05F2012E19D0D0F83C5825EA024230
+S315080046C0C0F83C28D0F81C28097801F00F018C4066
+S315080046D022EA0441C0F81C1800EB4310D0F8001B6E
+S315080046E00F4A1140C0F8001B002070BDD0F83C5896
+S315080046F092B29543C0F83C58D0F81C28097801F0C6
+S315080047000F018C40A1B28A43C0F81C2800EB431065
+S31508004710D0F80019034A1140C0F80019E4E7000070
+S315080047200078F3EF007833EC10B5D0F8041821F0D0
+S315080047300201C0F804180320FCF7CAFC002010BDCB
+S3150800474010B5D0F8041841F00201C0F80418032087
+S31508004750FCF7BEFC002010BD0FB4F0B504460026D9
+S315080047600020002504EB8001C1F80451401C0F28E5
+S31508004770F8D3109848B3A06B40F40011A163C4F8AD
+S31508004780005ED4F80018C4F800180B9801282FD03A
+S315080047900321204600F03EFB1021204600F0B2FA25
+S315080047A000B10126204600F09DFA00B10126C4F8A2
+S315080047B01058C4F81458C4F81C5800204FF000626A
+S315080047C04FF67F374FF0904333E0D4F8040840F0B3
+S315080047D00201C4F80418A06B20F40011A163206834
+S315080047E040F040012160206840F080012160C6E762
+S315080047F0089820B10121204600F00CFBCCE70021E7
+S31508004800204600F007FBC7E704EB4011D1F800C9C2
+S31508004810BCF1000F06DA10B1C1F8003904E0C4F89B
+S31508004820002901E0C1F80059C1F81059C1F8087902
+S31508004830401C06998142E7D8002014E004EB401199
+S31508004840D1F800CBBCF1000F06DA10B1C1F8003B75
+S3150800485004E0C4F8002B01E0C1F8005BC1F8105B66
+S31508004860C1F8087B401C06998142E7D8D4F810089D
+S3150800487020F48071C4F81018A5616FF0804060615B
+S31508004880099818B9A06940F01000A061A0690A4902
+S315080048900843A0610C9818B1A06940F00800A0610F
+S315080048A01098012803D1A06904490843A06130463D
+S315080048B0F0BC5DF814FB000000383C8004000040A2
+S315080048C0816821F0010181600020704770B50C787D
+S315080048D00B784E78414D012E00EB43131FD0D3F8C9
+S315080048E0100B6FF31200C3F8100BD3F8100B284007
+S315080048F0C3F8100B486908B188684861D3F8100BEB
+S3150800490040F40020C3F8100BD3F8100B8C68C4F3DE
+S3150800491012042043C3F8100B012A53D056E04E69FF
+S3150800492096B3D3F810696FF31206C3F81069D3F873
+S3150800493010692E40C3F810694E698D68AE4200D9D9
+S315080049404D6103F511631D6845F400251D601D685A
+S315080049504E69C6F3120635431D60012A23D000EBC3
+S315080049604412D2F8003943F00443C2F800394A69C0
+S315080049703AB3D0F83428097801F00F030121994099
+S315080049800A43C0F8342827E0FFE703F511631E68D9
+S315080049902E401E601D6845F400251D601D686FF3D6
+S315080049A012051D60D9E7096919B100EB4412C2F86E
+S315080049B0141900EB4410D0F8001941F00441C0F86E
+S315080049C0001909E0C86808B1C3F8140BD3F8000B3E
+S315080049D040F00440C3F8000B002070BDFFFF07E05D
+S315080049E010B5036C124CA34205D9D0F8003B002B36
+S315080049F001DA002010BD00F531600023036003686A
+S31508004A0043F400230360036843F018030360036854
+S31508004A1043F0C0430360A0F53160012906D100F5D3
+S31508004A2030604261016841F080210160002010BDBC
+S31508004A300A30544F0B784A78012A00EB43100BD002
+S31508004A40D0F8002B22F40012C0F8002BC9780329ED
+S31508004A5014D0022912D017E0D0F8002922F4001247
+S31508004A60C0F80029C978032901D002290CD1D0F849
+S31508004A70001941F08051C0F8001905E0D0F8001B74
+S31508004A8041F08051C0F8001B002070470A784B7827
+S31508004A900978012B00EB411012D0D0F8001B002931
+S31508004AA006DB2AB1D0F8001B21F08041C0F8001BB4
+S31508004AB0D0F8001B41F40011C0F8001B0020704715
+S31508004AC0D0F80019002906DB2AB1D0F8001921F020
+S31508004AD08041C0F80019D0F8001941F40011C0F857
+S31508004AE00019EBE7F8B50C786FF060460B784F784D
+S31508004AF0784D012F00EB431326D0D3F8104B6FF3F4
+S31508004B001204C3F8104BD3F8104B2C40C3F8104BC3
+S31508004B104C69002C7ED08D682C44641EB4FBF5F4D9
+S31508004B20A4B2D3F8105B06EAC4463543C3F8105B53
+S31508004B30D3F8105B8E686643C6F312042543C3F8A0
+S31508004B40105B012A67D0A9E04F69FFB103F511632D
+S31508004B501F686FF312071F601F682F401F604F6999
+S31508004B608D682F447F1EB7FBF5F506EAC5451E6816
+S31508004B7035431D601D684E69C6F3120635431D6030
+S31508004B80A3F51163CD78012D0ED017E003F5116357
+S31508004B901E682E401E601D6845F400251D601D68B0
+S31508004BA06FF312051D6009E003F511631D6825F012
+S31508004BB0C0451D601D6845F000551D60012A17D0C7
+S31508004BC000EB4413D3F8004944F00444C3F8004901
+S31508004BD0CC78012C36D04A699AB3D0F834280978AB
+S31508004BE001F00F03012199400A43C0F834286FE009
+S31508004BF00A691AB100EB4413C3F81429C9780129C4
+S31508004C0017D1D0F80818C9050BD400EB4411D1F810
+S31508004C10002901E02FE03DE042F00052C1F80029EA
+S31508004C2007E000EB4411D1F8002942F08052C1F8A0
+S31508004C30002900EB4410D0F8001941F00441C0F8EF
+S31508004C40001945E0D0F80848E40506D4D3F8004929
+S31508004C5044F00054C3F8004905E0D3F8004944F08D
+S31508004C608054C3F8004900928A8A93B20A78C968C0
+S31508004C7000F073F92CE0D3F8104B8D68C5F31205D4
+S31508004C802C43C3F8104BD3F8104B44F40024C3F854
+S31508004C90104B56E7CA680AB1C3F8142BC97801291C
+S31508004CA010D1D0F80808C00506D4D3F8000B40F098
+S31508004CB00050C3F8000B05E0D3F8000B40F0805015
+S31508004CC0C3F8000BD3F8000B40F00440C3F8000B00
+S31508004CD00020F8BDFFFF07E0816841F0010181600F
+S31508004CE000207047002110220261054A491C9142A2
+S31508004CF001D9032070470369DB06F7D40020704703
+S31508004D00400D03000022202343EA81110161054971
+S31508004D10521C8A4201D90320704703699B06F7D4BF
+S31508004D2000207047400D0300D0F8080800F0060080
+S31508004D30002805D0022805D0062803D00F20704782
+S31508004D400020704702207047406900F00100704754
+S31508004D50D0F81818D0F81C08084080B27047D0F868
+S31508004D601818D0F81C080840000C704710B5D0F881
+S31508004D701038D0F8342801F00F04E24002F001029E
+S31508004D8043EAC21200EB4110D0F80809104010BDE2
+S31508004D9000EB4111D1F8081BD0F8140808407047F9
+S31508004DA041698069084070470346084610B5D21C19
+S31508004DB09208002103F5805302E01C6810C0491CC4
+S31508004DC09142FAD310BD10B5C26822F0C042C26043
+S31508004DD0012902D031B1012010BDC16841F000514E
+S31508004DE0C16003E0C16841F08041C1603220FCF730
+S31508004DF06FF9002010BD00F50060026822F4FE621B
+S31508004E00026002684FF4FE6303EA01110A43026076
+S31508004E1000207047D0F800280A43C0F80028002070
+S31508004E2070470000022A0ED082B30921C26822F414
+S31508004E307052C260C2684FF4705303EA81210A4374
+S31508004E40C26000207047224A224B0A449A4201D285
+S31508004E500F21EBE7204A214B0A449A4201D20E2140
+S31508004E60E4E71F4A1F4B0A449A4201D20D21DDE7A7
+S31508004E701D4A1E4B0A449A4201D20C21D6E71C4A07
+S31508004E801C4B0A449A4202D20B21CFE71DE01A4A6C
+S31508004E901A4B0A449A4201D20A21C7E7184A194B03
+S31508004EA00A449A4201D20921C0E7174A174B0A4415
+S31508004EB09A4201D20821B9E7154A1144154A914286
+S31508004EC001D20721B2E70621B0E70921AEE70000C3
+S31508004ED0405327FF00350C00401E1BFF40420F00C1
+S31508004EE000DC0BFF804F1200808CF9FE20D61300E1
+S31508004EF060B6E5FE60E3160000D3CEFE40771B00E1
+S31508004F00C05BB3FEC091210000CA91FE207538002F
+S31508004F10E05459FEE09C410010B5044600214FF6C6
+S31508004F207F3304EB4112C2F80839C2F8083B491C22
+S31508004F300F29F6D30020C4F81008C4F81408C4F8DA
+S31508004F401C082046FFF7CEFE002805D12046BDE8FE
+S31508004F5010401021FFF7D6BE10BD10B5029C002CDC
+S31508004F600CD1DB1C9C08002300EB023000F58050B6
+S31508004F7002E004C902605B1CA342FAD3002010BDFC
+S31508004F807047704710B5094B5A68002A0CD0546907
+S31508004F905C6011749060D0600023537410600844FC
+S31508004FA0401E5060907C10BDFF2010BDF400002408
+S31508004FB0094800F11802002181744261183018323C
+S31508004FC0491CC9B20029F7D08174002141610349FF
+S31508004FD0014848607047000058110024F400002476
+S31508004FE070B504460D46022C04D34FF4F2710EA098
+S31508004FF0FBF731FA164B04EB440203EBC200417C83
+S3150800500081B1816809782970417C491E417481689B
+S31508005010491C81604468A14202D953F83210816064
+S31508005020012070BD002070BD2E2E5C2E2E5C2E2E0B
+S315080050305C2E2E5C536F757263655C41524D434D11
+S31508005040375F53544D333248375C7573622E6300AD
+S315080050505811002410B50446022C04D34FF40171EC
+S3150800506004A0FBF7F8F90D4904EB440001EBC00076
+S31508005070407C10BD2E2E5C2E2E5C2E2E5C2E2E5CB9
+S31508005080536F757263655C41524D434D375F535498
+S315080050904D333248375C7573622E6300581100240D
+S315080050A070B504460D46022C04D310A04FF4E171E6
+S315080050B0FBF7D1F9174B04EB440203EBC200417C22
+S315080050C0047CA14201D1002070BDC1680D70417CED
+S315080050D0491C4174C168491CC1604468A14202D98F
+S315080050E053F83210C160012070BD00002E2E5C2ED0
+S315080050F02E5C2E2E5C2E2E5C536F757263655C419A
+S31508005100524D434D375F53544D333248375C7573B0
+S31508005110622E63005811002410B50648D0F8C00264
+S31508005120FCF7A1FD0348FEF718FCBDE81040002077
+S31508005130FFF726BF0C12002470B5FFF739FF1E4C87
+S315080051404021601CFFF71EFF207004F14105402135
+S31508005150681CFFF717FF28702178FF2901D0FF2860
+S3150800516003D1842115A0FBF776F9134800221D49BF
+S315080051708430FEF7C8FD10481B498430FEF7D3FF7C
+S315080051800120FFF7FDFE0C488430FFF77DF8FDF798
+S31508005190C1F909488430D0F8C002FCF746FDFBF790
+S315080051A079F94FF4FA61884204D2BDE8704008469E
+S315080051B0FBF78EB970BD0000881100242E2E5C2ED8
+S315080051C02E5C2E2E5C2E2E5C536F757263655C41C9
+S315080051D0524D434D375F53544D333248375C7573E0
+S315080051E0622E6300880000245000002470470000E7
+S315080051F0014602480078FFF7F3BE0000C9110024F3
+S315080052002DE9F04180460F461948D0F8C002FCF750
+S3150800521048FE184C0026184D607838B12078284486
+S31508005220401CFFF7E5FF01280DD01EE01248FFF7E6
+S31508005230DFFF012819D12878401E3E2815D80120FD
+S315080052406070267011E02078401CC2B2227028785F
+S315080052502946904209D1491C4046FBF7FEFA66707A
+S31508005260207838700120BDE8F0810020FBE70000B7
+S315080052700C120024F4000024D81000242DE9F04173
+S315080052800446FEF7B5FA064611482146FEF727FEFC
+S3150800529085B200240E4F4FF4B578433F0BE0315DDD
+S315080052A03878FFF7FDFE012803D00AA04146FBF730
+S315080052B0D2F8641CA4B2AC42F1D3FEF799FABDE861
+S315080052C0F0414023024602480121FEF76BBE00006A
+S315080052D00C1200242E2E5C2E2E5C2E2E5C2E2E5C9E
+S315080052E0536F757263655C41524D434D375F535436
+S315080052F04D333248375C7573622E630001460248A7
+S315080053000078FFF7CDBE00008811002470B5054669
+S315080053100E463F2E03D9BB210EA0FBF79CF830465C
+S31508005320FFF7ECFF012803D0BF210AA0FBF793F88B
+S3150800533000240CE0FBF787FA285DFFF7DFFF01285A
+S3150800534003D0C82103A0FBF786F8641CA4B2B442B4
+S31508005350F0D370BD2E2E5C2E2E5C2E2E5C2E2E5C6F
+S31508005360536F757263655C41524D434D375F5354B5
+S315080053704D333248375C7573622E63002DE9F84366
+S31508005380154E3078FFF766FE0546280021D0402DD9
+S3150800539000D940250024104F4FF4A478703F0EE042
+S315080053A030786946FFF71CFE012803D00BA041465A
+S315080053B0FBF751F89DF800003855641CE4B2AC427E
+S315080053C0EED3054A81212B46703A02F1F400FEF726
+S315080053D08DFEBDE8F8830000881100242E2E5C2E71
+S315080053E02E5C2E2E5C2E2E5C536F757263655C41A7
+S315080053F0524D434D375F53544D333248375C7573BE
+S31508005400622E630010B5084CFF21E170E21D416869
+S31508005410A06C00F037F9207100206071A071082097
+S31508005420A4F8440010BD0000A007002470B500F0E1
+S31508005430C9F90E4C01252570FF20E07000201021C7
+S3150800544021716071FBF766F9A071FBF779F9E071D4
+S31508005450FBF776F9000A20726572A5720820A4F88F
+S315080054604400BDE87040FDF76FBE0000A0070024A9
+S3150800547010B5054C0020207000F0A4F9FF20E0705C
+S315080054800120A4F8440010BDA00700240748FF2106
+S31508005490C170074981640021017141718171072139
+S315080054A0C0F807100821A0F844107047A007002488
+S315080054B0D05800080648FF21C170002101714278C2
+S315080054C042718171C17101720621A0F844107047BA
+S315080054D0A007002470B50446FBF71CF96178801E06
+S315080054E0884204DABDE87040222000F071B9104DF8
+S315080054F0FF20E8700120A5F84400617849B1A86C3E
+S31508005500A21CFDF725FE68B16178A86C0844A8645A
+S3150800551070BDFDF70BFE0028FAD1BDE870403120BA
+S3150800552000F056B9BDE87040312000F051B90000CE
+S31508005530A007002410B5084C4168A06CFDF700FED2
+S3150800554028B1FF20E0700120A4F8440010BDBDE892
+S315080055501040312000F03CB9A007002470B505467C
+S31508005560FBF7D8F80B4C411E6A1CA06CFDF7F0FD42
+S3150800557058B1FF20E070FBF7CDF8A16C401E084437
+S31508005580A0640120A4F8440070BDBDE87040312035
+S3150800559000F01EB9A0070024312000F019B9000058
+S315080055A010B5FBF769F90348FF21C1700121A0F87E
+S315080055B0441010BDA007002470B5084CFF20E07009
+S315080055C0002525716571FBF7A5F8A071E5712572AF
+S315080055D065720720A4F8440070BD0000A0070024E7
+S315080055E00449FF22CA70406888640120A1F8440073
+S315080055F070470000A007002470B50446FBF78AF838
+S315080056006178401E884204DABDE87040222000F026
+S31508005610DFB8094D6168A9646278281DFBF71DF992
+S31508005620FF20E8706178A86C0844A8646078401C7C
+S31508005630A5F8440070BD0000A0070024002000F073
+S31508005640C7B8000070B50546FBF764F86A78401ECF
+S31508005650904204DABDE87040222000F0B9B8084C40
+S31508005660201DA16CFBF7F9F8FF20E0706978A06CA3
+S315080056700844A0646878401CA4F8440070BD000083
+S31508005680A00700242DE9F04104460E4617460025DA
+S3150800569005E014F8010B2844C5B2FBF7D4F8761ECA
+S315080056A0701CF6D13D600120BDE8F0810548002157
+S315080056B00170816480F84310A0F84410817041702D
+S315080056C070470000A007002403480078002801D08E
+S315080056D00120704700207047A007002410B5017804
+S315080056E0334CFF290FD02278012A60D1F42921D022
+S315080056F013DCD02936D009DCC92930D0CC293DD0D5
+S31508005700CF293ED137E0FFF791FE3DE0D1292FD0D2
+S31508005710D2292AD0F32934D112E0F5390A2930D210
+S31508005720DFE801F0050B2F2F2F112F14171AFFF79B
+S3150800573089FF29E0FFF760FF26E0FFF751FF23E026
+S31508005740FFF760FE20E0FFF7A1FE1DE0FFF776FFFA
+S315080057501AE0FFF7AFFE17E0FFF78AFE14E0FFF73F
+S31508005760FDFE11E0FFF7B6FE0EE0FFF725FF0BE0A2
+S31508005770FFF7E0FE08E0FFF713FF05E0FFF70CFF71
+S3150800578002E0202000F024F894F84300012802D112
+S31508005790102000F01DF8B4F94410002907DD012295
+S315080057A084F84320E01CBDE8104000F01BB810BD8B
+S315080057B0A00700240249002081F843007047000032
+S315080057C0A00700240149002048707047A00700245C
+S315080057D00349FE22CA7008710220A1F844007047E6
+S315080057E0A007002489B2FBF70BB80907090E0028A1
+S315080057F004DB00F1E02080F80014704700F00F0089
+S3150800580000F1E02080F8141D7047FCF79BFFFAF7BB
+S3150800581065FEFAF772FEFCE74FF04070E1EE100AFB
+S315080058207047000000000102030401020304060792
+S31508005830080900000001020304050607080C1014F5
+S3150800584018203040000000000000000000000000A2
+S315080058500000000000000000010000000200000037
+S31508005860030000000400000000000000050000001E
+S315080058700000000000000000000000000600000014
+S315080058800000000000000000000000000700000003
+S3150800589000000000010203040102030406070809C8
+S315080058A001000000020000000400000006000000DD
+S315080058B0080000000A0000000C00000010000000AC
+S315080058C020000000400000008000000000010000E9
+S315080058D04F70656E424C5400050206020603070324
+S315080058E00803090309040A040B040C040C050D0536
+S315080058F00E050F050F06100610071008000002080F
+S315080059000000020001010000000004080000020077
+S315080059100201000000000608000002000301000062
+S3150800592000000808000002000401000000000A0840
+S31508005930000002000501000000000C08000002003B
+S315080059400601000000000E08000002000701000022
+S315080059500000100800000200000200000000120803
+S315080059600000020001020000000014080000020006
+S3150800597002020000000016080000020003020000F0
+S3150800598000001808000002000402000000001A08BF
+S31508005990000002000502000000001C0800000200CA
+S315080059A00602000000001E080000020007020000B0
+S315080059B0D059000800000024FC000000D4020008AA
+S315080059C0CC5A0008FC000024341A0000F002000833
+S315080059D00090D0030090D0030000000001000000F2
+S315080059E01000000000000000000000000000000099
+S315080059F0000000000A060002000000400100000046
+S31508005A0009022000010100C0320904000002FF005B
+S31508005A100000070581024000FF070501024000FF5C
+S31508005A20F9370008BF3700084138000800000000B1
+S31508005A3000000000A9370008B33700082D38000811
+S31508005A40000000000000000000000000E537000824
+S31508005A5000000000D9370008AD390008F5390008FC
+S31508005A60013A0008253A00085D3A0008813900081D
+S31508005A70B9390008040309041201000200000040B5
+S31508005A80501DAC6000020102030100001A03000069
+S31508005A9000000000000000000000000000000000F8
+S31508005AA000000000000000000000000000000000E8
+S31508005AB000000000040000000000000000000000D4
+S31108005AC0000000000000000000000000CC
+S7050800029957
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/blt_conf.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/blt_conf.h
new file mode 100644
index 00000000..27303e73
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/blt_conf.h
@@ -0,0 +1,189 @@
+/************************************************************************************//**
+* \file         Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/blt_conf.h
+* \brief        Bootloader configuration header file.
+* \ingroup      Boot_ARMCM7_STM32H7_Nucleo_H743ZI_Keil
+* \internal
+*----------------------------------------------------------------------------------------
+*                          C O P Y R I G H T
+*----------------------------------------------------------------------------------------
+*   Copyright (c) 2020  by Feaser    http://www.feaser.com    All rights reserved
+*
+*----------------------------------------------------------------------------------------
+*                            L I C E N S E
+*----------------------------------------------------------------------------------------
+* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as published by the Free
+* Software Foundation, either version 3 of the License, or (at your option) any later
+* version.
+*
+* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+* PURPOSE. See the GNU General Public License for more details.
+*
+* You have received a copy of the GNU General Public License along with OpenBLT. It
+* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
+*
+* \endinternal
+****************************************************************************************/
+#ifndef BLT_CONF_H
+#define BLT_CONF_H
+
+/****************************************************************************************
+*   C P U   D R I V E R   C O N F I G U R A T I O N
+****************************************************************************************/
+/* To properly initialize the baudrate clocks of the communication interface, typically
+ * the speed of the crystal oscillator and/or the speed at which the system runs is
+ * needed. Set these through configurables BOOT_CPU_XTAL_SPEED_KHZ and
+ * BOOT_CPU_SYSTEM_SPEED_KHZ, respectively. To enable data exchange with the host that is
+ * not dependent on the targets architecture, the byte ordering needs to be known.
+ * Setting BOOT_CPU_BYTE_ORDER_MOTOROLA to 1 selects big endian mode and 0 selects
+ * little endian mode.
+ *
+ * Set BOOT_CPU_USER_PROGRAM_START_HOOK to 1 if you would like a hook function to be
+ * called the moment the user program is about to be started. This could be used to
+ * de-initialize application specific parts, for example to stop blinking an LED, etc.
+ */
+/** \brief Frequency of the external crystal oscillator. */
+#define BOOT_CPU_XTAL_SPEED_KHZ          (8000)
+/** \brief Desired system speed. */
+#define BOOT_CPU_SYSTEM_SPEED_KHZ        (480000)
+/** \brief Motorola or Intel style byte ordering. */
+#define BOOT_CPU_BYTE_ORDER_MOTOROLA     (0)
+/** \brief Enable/disable hook function call right before user program start. */
+#define BOOT_CPU_USER_PROGRAM_START_HOOK (1)
+
+
+/****************************************************************************************
+*   C O M M U N I C A T I O N   I N T E R F A C E   C O N F I G U R A T I O N
+****************************************************************************************/
+/* The USB communication interface is selected by setting the BOOT_COM_USB_ENABLE
+ * configurable to 1. The maximum amount of data bytes in a message for data transmission
+ * and reception is set through BOOT_COM_USB_TX_MAX_DATA and BOOT_COM_USB_RX_MAX_DATA,
+ * respectively.
+ *
+ */
+/** \brief Enable/disable USB transport layer. */
+#define BOOT_COM_USB_ENABLE             (1)
+/** \brief Configure number of bytes in the target->host data packet. */
+#define BOOT_COM_USB_TX_MAX_DATA        (63)
+/** \brief Configure number of bytes in the host->target data packet. */
+#define BOOT_COM_USB_RX_MAX_DATA        (63)
+
+/* The CAN communication interface is selected by setting the BOOT_COM_CAN_ENABLE
+ * configurable to 1. Configurable BOOT_COM_CAN_BAUDRATE selects the communication speed
+ * in bits/second. Two CAN messages are reserved for communication with the host. The
+ * message identifier for sending data from the target to the host is configured with
+ * BOOT_COM_CAN_TXMSG_ID. The one for receiving data from the host is configured with
+ * BOOT_COM_CAN_RXMSG_ID. Note that an extended 29-bit CAN identifier is configured by
+ * OR-ing with mask 0x80000000. The maximum amount of data bytes in a message for data
+ * transmission and reception is set through BOOT_COM_CAN_TX_MAX_DATA and
+ * BOOT_COM_CAN_RX_MAX_DATA, respectively. It is common for a microcontroller to have more
+ * than 1 CAN controller on board. The zero-based BOOT_COM_CAN_CHANNEL_INDEX selects the
+ * CAN controller channel.
+ *
+ */
+/** \brief Enable/disable CAN transport layer. */
+#define BOOT_COM_CAN_ENABLE             (1)
+/** \brief Configure the desired CAN baudrate. */
+#define BOOT_COM_CAN_BAUDRATE           (500000)
+/** \brief Configure CAN message ID target->host. */
+#define BOOT_COM_CAN_TX_MSG_ID          (0x7E1 /*| 0x80000000*/)
+/** \brief Configure number of bytes in the target->host CAN message. */
+#define BOOT_COM_CAN_TX_MAX_DATA        (8)
+/** \brief Configure CAN message ID host->target. */
+#define BOOT_COM_CAN_RX_MSG_ID          (0x667 /*| 0x80000000*/)
+/** \brief Configure number of bytes in the host->target CAN message. */
+#define BOOT_COM_CAN_RX_MAX_DATA        (8)
+/** \brief Select the desired CAN peripheral as a zero based index. */
+#define BOOT_COM_CAN_CHANNEL_INDEX      (0)
+
+/* The RS232 communication interface is selected by setting the BOOT_COM_RS232_ENABLE
+ * configurable to 1. Configurable BOOT_COM_RS232_BAUDRATE selects the communication speed
+ * in bits/second. The maximum amount of data bytes in a message for data transmission
+ * and reception is set through BOOT_COM_RS232_TX_MAX_DATA and BOOT_COM_RS232_RX_MAX_DATA,
+ * respectively. It is common for a microcontroller to have more than 1 UART interface
+ * on board. The zero-based BOOT_COM_RS232_CHANNEL_INDEX selects the UART interface.
+ *
+ */
+/** \brief Enable/disable UART transport layer. */
+#define BOOT_COM_RS232_ENABLE            (1)
+/** \brief Configure the desired communication speed. */
+#define BOOT_COM_RS232_BAUDRATE          (57600)
+/** \brief Configure number of bytes in the target->host data packet. */
+#define BOOT_COM_RS232_TX_MAX_DATA       (64)
+/** \brief Configure number of bytes in the host->target data packet. */
+#define BOOT_COM_RS232_RX_MAX_DATA       (64)
+/** \brief Select the desired UART peripheral as a zero based index. */
+#define BOOT_COM_RS232_CHANNEL_INDEX     (2)
+
+
+/****************************************************************************************
+*   B A C K D O O R   E N T R Y   C O N F I G U R A T I O N
+****************************************************************************************/
+/* It is possible to implement an application specific method to force the bootloader to
+ * stay active after a reset. Such a backdoor entry into the bootloader is desired in
+ * situations where the user program does not run properly and therefore cannot
+ * reactivate the bootloader. By enabling these hook functions, the application can
+ * implement the backdoor, which overrides the default backdoor entry that is programmed
+ * into the bootloader. When desired for security purposes, these hook functions can
+ * also be implemented in a way that disables the backdoor entry altogether.
+ */
+/** \brief Enable/disable the backdoor override hook functions. */
+#define BOOT_BACKDOOR_HOOKS_ENABLE      (0)
+
+
+/****************************************************************************************
+*   N O N - V O L A T I L E   M E M O R Y   D R I V E R   C O N F I G U R A T I O N
+****************************************************************************************/
+/* The NVM driver typically supports erase and program operations of the internal memory
+ * present on the microcontroller. Through these hook functions the NVM driver can be
+ * extended to support additional memory types such as external flash memory and serial
+ * eeproms. The size of the internal memory in kilobytes is specified with configurable
+ * BOOT_NVM_SIZE_KB. If desired the internal checksum writing and verification method can
+ * be overridden with a application specific method by enabling configuration switch
+ * BOOT_NVM_CHECKSUM_HOOKS_ENABLE.
+ */
+/** \brief Enable/disable the NVM hook function for supporting additional memory devices. */
+#define BOOT_NVM_HOOKS_ENABLE           (0)
+/** \brief Configure the size of the default memory device (typically flash EEPROM). */
+#define BOOT_NVM_SIZE_KB                (2048)
+/** \brief Enable/disable hooks functions to override the user program checksum handling. */
+#define BOOT_NVM_CHECKSUM_HOOKS_ENABLE  (0)
+
+
+/****************************************************************************************
+*   W A T C H D O G   D R I V E R   C O N F I G U R A T I O N
+****************************************************************************************/
+/* The COP driver cannot be configured internally in the bootloader, because its use
+ * and configuration is application specific. The bootloader does need to service the
+ * watchdog in case it is used. When the application requires the use of a watchdog,
+ * set BOOT_COP_HOOKS_ENABLE to be able to initialize and service the watchdog through
+ * hook functions.
+ */
+/** \brief Enable/disable the hook functions for controlling the watchdog. */
+#define BOOT_COP_HOOKS_ENABLE           (1)
+
+
+/****************************************************************************************
+*   S E E D / K E Y   S E C U R I T Y   C O N F I G U R A T I O N
+****************************************************************************************/
+/* A security mechanism can be enabled in the bootloader's XCP module by setting configu-
+ * rable BOOT_XCP_SEED_KEY_ENABLE to 1. Before any memory erase or programming
+ * operations can be performed, access to this resource need to be unlocked.
+ * In the Microboot settings on tab "XCP Protection" you need to specify a DLL that
+ * implements the unlocking algorithm. The demo programs are configured for the (simple)
+ * algorithm in "libseednkey.dll". The source code for this DLL is available so it can be
+ * customized to your needs.
+ * During the unlock sequence, Microboot requests a seed from the bootloader, which is in
+ * the format of a byte array. Using this seed the unlock algorithm in the DLL computes
+ * a key, which is also a byte array, and sends this back to the bootloader. The
+ * bootloader then verifies this key to determine if programming and erase operations are
+ * permitted.
+ * After enabling this feature the hook functions XcpGetSeedHook() and XcpVerifyKeyHook()
+ * are called by the bootloader to obtain the seed and to verify the key, respectively.
+ */
+#define BOOT_XCP_SEED_KEY_ENABLE        (0)
+
+
+#endif /* BLT_CONF_H */
+/*********************************** end of blt_conf.h *********************************/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/boot.dox b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/boot.dox
new file mode 100644
index 00000000..14103b4a
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/boot.dox
@@ -0,0 +1,7 @@
+/**
+\defgroup   Boot_ARMCM7_STM32H7_Nucleo_H743ZI_Keil Bootloader
+\brief      Bootloader. 
+\ingroup    ARMCM7_STM32H7_Nucleo_H743ZI_Keil
+*/
+
+
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/hooks.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/hooks.c
new file mode 100644
index 00000000..e903fed6
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/hooks.c
@@ -0,0 +1,350 @@
+/************************************************************************************//**
+* \file         Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/hooks.c
+* \brief        Bootloader callback source file.
+* \ingroup      Boot_ARMCM7_STM32H7_Nucleo_H743ZI_Keil
+* \internal
+*----------------------------------------------------------------------------------------
+*                          C O P Y R I G H T
+*----------------------------------------------------------------------------------------
+*   Copyright (c) 2020  by Feaser    http://www.feaser.com    All rights reserved
+*
+*----------------------------------------------------------------------------------------
+*                            L I C E N S E
+*----------------------------------------------------------------------------------------
+* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as published by the Free
+* Software Foundation, either version 3 of the License, or (at your option) any later
+* version.
+*
+* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+* PURPOSE. See the GNU General Public License for more details.
+*
+* You have received a copy of the GNU General Public License along with OpenBLT. It
+* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
+*
+* \endinternal
+****************************************************************************************/
+
+/****************************************************************************************
+* Include files
+****************************************************************************************/
+#include "boot.h"                                /* bootloader generic header          */
+#include "led.h"                                 /* LED driver header                  */
+#include "stm32h7xx.h"                           /* STM32 CPU and HAL header           */
+#include "stm32h7xx_ll_gpio.h"                   /* STM32 LL GPIO header               */
+
+
+/****************************************************************************************
+*   C P U   D R I V E R   H O O K   F U N C T I O N S
+****************************************************************************************/
+
+#if (BOOT_CPU_USER_PROGRAM_START_HOOK > 0)
+/************************************************************************************//**
+** \brief     Callback that gets called when the bootloader is about to exit and
+**            hand over control to the user program. This is the last moment that
+**            some final checking can be performed and if necessary prevent the
+**            bootloader from activiting the user program.
+** \return    BLT_TRUE if it is okay to start the user program, BLT_FALSE to keep
+**            keep the bootloader active.
+**
+****************************************************************************************/
+blt_bool CpuUserProgramStartHook(void)
+{
+  /* additional and optional backdoor entry through the pushbutton on the board. to
+   * force the bootloader to stay active after reset, keep the pushbutton pressed while
+   * resetting the microcontroller.
+   */
+  if (LL_GPIO_IsInputPinSet(GPIOC, LL_GPIO_PIN_13) != 0)
+  {
+    /* pushbutton pressed, so do not start the user program and keep the
+     * bootloader active instead.
+     */
+    return BLT_FALSE;
+  }
+  /* clean up the LED driver */
+  LedBlinkExit();
+  /*  okay to start the user program.*/
+  return BLT_TRUE;
+} /*** end of CpuUserProgramStartHook ***/
+#endif /* BOOT_CPU_USER_PROGRAM_START_HOOK > 0 */
+
+
+/****************************************************************************************
+*   W A T C H D O G   D R I V E R   H O O K   F U N C T I O N S
+****************************************************************************************/
+
+#if (BOOT_COP_HOOKS_ENABLE > 0)
+/************************************************************************************//**
+** \brief     Callback that gets called at the end of the internal COP driver
+**            initialization routine. It can be used to configure and enable the
+**            watchdog.
+** \return    none.
+**
+****************************************************************************************/
+void CopInitHook(void)
+{
+  /* this function is called upon initialization. might as well use it to initialize
+   * the LED driver. It is kind of a visual watchdog anyways.
+   */
+  LedBlinkInit(100);
+} /*** end of CopInitHook ***/
+
+
+/************************************************************************************//**
+** \brief     Callback that gets called at the end of the internal COP driver
+**            service routine. This gets called upon initialization and during
+**            potential long lasting loops and routine. It can be used to service
+**            the watchdog to prevent a watchdog reset.
+** \return    none.
+**
+****************************************************************************************/
+void CopServiceHook(void)
+{
+  /* run the LED blink task. this is a better place to do it than in the main() program
+   * loop. certain operations such as flash erase can take a long time, which would cause
+   * a blink interval to be skipped. this function is also called during such operations,
+   * so no blink intervals will be skipped when calling the LED blink task here.
+   */
+  LedBlinkTask();
+} /*** end of CopServiceHook ***/
+#endif /* BOOT_COP_HOOKS_ENABLE > 0 */
+
+
+/****************************************************************************************
+*   U S B   C O M M U N I C A T I O N   I N T E R F A C E   H O O K   F U N C T I O N S
+****************************************************************************************/
+
+#if (BOOT_COM_USB_ENABLE > 0)
+/************************************************************************************//**
+** \brief     Callback that gets called whenever the USB device should be connected
+**            to the USB bus.
+** \param     connect BLT_TRUE to connect and BLT_FALSE to disconnect.
+** \return    none.
+**
+****************************************************************************************/
+void UsbConnectHook(blt_bool connect)
+{
+  /* Note that this is handled automatically by the OTG peripheral. */
+} /*** end of UsbConnect ***/
+
+
+/************************************************************************************//**
+** \brief     Callback that gets called whenever the USB host requests the device
+**            to enter a low power mode.
+** \return    none.
+**
+****************************************************************************************/
+void UsbEnterLowPowerModeHook(void)
+{
+  /* support to enter a low power mode can be implemented here */
+} /*** end of UsbEnterLowPowerMode ***/
+
+
+/************************************************************************************//**
+** \brief     Callback that gets called whenever the USB host requests the device to
+**            exit low power mode.
+** \return    none.
+**
+****************************************************************************************/
+void UsbLeaveLowPowerModeHook(void)
+{
+  /* support to leave a low power mode can be implemented here */
+} /*** end of UsbLeaveLowPowerMode ***/
+#endif /* BOOT_COM_USB_ENABLE > 0 */
+
+
+/****************************************************************************************
+*   B A C K D O O R   E N T R Y   H O O K   F U N C T I O N S
+****************************************************************************************/
+
+#if (BOOT_BACKDOOR_HOOKS_ENABLE > 0)
+/************************************************************************************//**
+** \brief     Initializes the backdoor entry option.
+** \return    none.
+**
+****************************************************************************************/
+void BackDoorInitHook(void)
+{
+} /*** end of BackDoorInitHook ***/
+
+
+/************************************************************************************//**
+** \brief     Checks if a backdoor entry is requested.
+** \return    BLT_TRUE if the backdoor entry is requested, BLT_FALSE otherwise.
+**
+****************************************************************************************/
+blt_bool BackDoorEntryHook(void)
+{
+  /* default implementation always activates the bootloader after a reset */
+  return BLT_TRUE;
+} /*** end of BackDoorEntryHook ***/
+#endif /* BOOT_BACKDOOR_HOOKS_ENABLE > 0 */
+
+
+/****************************************************************************************
+*   N O N - V O L A T I L E   M E M O R Y   D R I V E R   H O O K   F U N C T I O N S
+****************************************************************************************/
+
+#if (BOOT_NVM_HOOKS_ENABLE > 0)
+/************************************************************************************//**
+** \brief     Callback that gets called at the start of the internal NVM driver
+**            initialization routine.
+** \return    none.
+**
+****************************************************************************************/
+void NvmInitHook(void)
+{
+} /*** end of NvmInitHook ***/
+
+
+/************************************************************************************//**
+** \brief     Callback that gets called at the start of a firmware update to reinitialize
+**            the NVM driver.
+** \return    none.
+**
+****************************************************************************************/
+void NvmReinitHook(void)
+{
+} /*** end of NvmReinitHook ***/
+
+
+/************************************************************************************//**
+** \brief     Callback that gets called at the start of the NVM driver write
+**            routine. It allows additional memory to be operated on. If the address
+**            is not within the range of the additional memory, then
+**            BLT_NVM_NOT_IN_RANGE must be returned to indicate that the data hasn't
+**            been written yet.
+** \param     addr Start address.
+** \param     len  Length in bytes.
+** \param     data Pointer to the data buffer.
+** \return    BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is
+**            not within the supported memory range, or BLT_NVM_ERROR is the write
+**            operation failed.
+**
+****************************************************************************************/
+blt_int8u NvmWriteHook(blt_addr addr, blt_int32u len, blt_int8u *data)
+{
+  return BLT_NVM_NOT_IN_RANGE;
+} /*** end of NvmWriteHook ***/
+
+
+/************************************************************************************//**
+** \brief     Callback that gets called at the start of the NVM driver erase
+**            routine. It allows additional memory to be operated on. If the address
+**            is not within the range of the additional memory, then
+**            BLT_NVM_NOT_IN_RANGE must be returned to indicate that the memory
+**            hasn't been erased yet.
+** \param     addr Start address.
+** \param     len  Length in bytes.
+** \return    BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is
+**            not within the supported memory range, or BLT_NVM_ERROR is the erase
+**            operation failed.
+**
+****************************************************************************************/
+blt_int8u NvmEraseHook(blt_addr addr, blt_int32u len)
+{
+  return BLT_NVM_NOT_IN_RANGE;
+} /*** end of NvmEraseHook ***/
+
+
+/************************************************************************************//**
+** \brief     Callback that gets called at the end of the NVM programming session.
+** \return    BLT_TRUE is successful, BLT_FALSE otherwise.
+**
+****************************************************************************************/
+blt_bool NvmDoneHook(void)
+{
+  return BLT_TRUE;
+} /*** end of NvmDoneHook ***/
+#endif /* BOOT_NVM_HOOKS_ENABLE > 0 */
+
+
+#if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0)
+/************************************************************************************//**
+** \brief     Verifies the checksum, which indicates that a valid user program is
+**            present and can be started.
+** \return    BLT_TRUE if successful, BLT_FALSE otherwise.
+**
+****************************************************************************************/
+blt_bool NvmVerifyChecksumHook(void)
+{
+  return BLT_TRUE;
+} /*** end of NvmVerifyChecksum ***/
+
+
+/************************************************************************************//**
+** \brief     Writes a checksum of the user program to non-volatile memory. This is
+**            performed once the entire user program has been programmed. Through
+**            the checksum, the bootloader can check if a valid user programming is
+**            present and can be started.
+** \return    BLT_TRUE if successful, BLT_FALSE otherwise.
+**
+****************************************************************************************/
+blt_bool NvmWriteChecksumHook(void)
+{
+  return BLT_TRUE;
+}
+#endif /* BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0 */
+
+
+/****************************************************************************************
+*   S E E D / K E Y   S E C U R I T Y   H O O K   F U N C T I O N S
+****************************************************************************************/
+
+#if (BOOT_XCP_SEED_KEY_ENABLE > 0)
+/************************************************************************************//**
+** \brief     Provides a seed to the XCP master that will be used for the key
+**            generation when the master attempts to unlock the specified resource.
+**            Called by the GET_SEED command.
+** \param     resource  Resource that the seed if requested for (XCP_RES_XXX).
+** \param     seed      Pointer to byte buffer wher the seed will be stored.
+** \return    Length of the seed in bytes.
+**
+****************************************************************************************/
+blt_int8u XcpGetSeedHook(blt_int8u resource, blt_int8u *seed)
+{
+  /* request seed for unlocking ProGraMming resource */
+  if ((resource & XCP_RES_PGM) != 0)
+  {
+    seed[0] = 0x55;
+  }
+
+  /* return seed length */
+  return 1;
+} /*** end of XcpGetSeedHook ***/
+
+
+/************************************************************************************//**
+** \brief     Called by the UNLOCK command and checks if the key to unlock the
+**            specified resource was correct. If so, then the resource protection
+**            will be removed.
+** \param     resource  resource to unlock (XCP_RES_XXX).
+** \param     key       pointer to the byte buffer holding the key.
+** \param     len       length of the key in bytes.
+** \return    1 if the key was correct, 0 otherwise.
+**
+****************************************************************************************/
+blt_int8u XcpVerifyKeyHook(blt_int8u resource, blt_int8u *key, blt_int8u len)
+{
+  /* suppress compiler warning for unused parameter */
+  len = len;
+
+  /* the example key algorithm in "libseednkey.dll" works as follows:
+   *  - PGM will be unlocked if key = seed - 1
+   */
+
+  /* check key for unlocking ProGraMming resource */
+  if ((resource == XCP_RES_PGM) && (key[0] == (0x55-1)))
+  {
+    /* correct key received for unlocking PGM resource */
+    return 1;
+  }
+
+  /* still here so key incorrect */
+  return 0;
+} /*** end of XcpVerifyKeyHook ***/
+#endif /* BOOT_XCP_SEED_KEY_ENABLE > 0 */
+
+
+/*********************************** end of hooks.c ************************************/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/ide/stm32h743.uvoptx b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/ide/stm32h743.uvoptx
new file mode 100644
index 00000000..56b4cd7b
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/ide/stm32h743.uvoptx
@@ -0,0 +1,1944 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj; *.o</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>Target</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>16000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath></ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>18</CpuCode>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>1</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <bEvRecOn>1</bEvRecOn>
+        <bSchkAxf>0</bSchkAxf>
+        <bTchkAxf>0</bTchkAxf>
+        <nTsel>5</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>STLink\ST-LINKIII-KEIL_SWO.dll</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMRTXEVENTFLAGS</Key>
+          <Name>-L70 -Z18 -C0 -M0 -T1</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(6017=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(6016=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name>(105=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC8000 -FN1 -FF0STM32H7x_2048 -FS08000000 -FL0200000 -FP0($$Device:STM32H743ZITx$CMSIS\Flash\STM32H7x_2048.FLM))</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ST-LINKIII-KEIL_SWO</Key>
+          <Name>-U-O142 -O2254 -SF10000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP (ARM Core") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32H7x_2048.FLM -FS08000000 -FL0200000 -FP0($$Device:STM32H743ZITx$CMSIS\Flash\STM32H7x_2048.FLM)</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>1</periodic>
+        <aLwin>1</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+      <bAutoGenD>0</bAutoGenD>
+      <LntExFlags>0</LntExFlags>
+      <pMisraName></pMisraName>
+      <pszMrule></pszMrule>
+      <pSingCmds></pSingCmds>
+      <pMultCmds></pMultCmds>
+      <pMisraNamep></pMisraNamep>
+      <pszMrulep></pszMrulep>
+      <pSingCmdsp></pSingCmdsp>
+      <pMultCmdsp></pMultCmdsp>
+      <DebugDescription>
+        <Enable>1</Enable>
+        <EnableFlashSeq>0</EnableFlashSeq>
+        <EnableLog>0</EnableLog>
+        <Protocol>2</Protocol>
+        <DbgClock>10000000</DbgClock>
+      </DebugDescription>
+    </TargetOption>
+  </Target>
+
+  <Group>
+    <GroupName>Lib</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>1</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\stm32h7xx_hal_conf.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_conf.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>2</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\system_stm32h7xx.c</PathWithFileName>
+      <FilenameWithoutPath>system_stm32h7xx.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>3</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Device\ST\STM32H7xx\Include\stm32h7xx.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>4</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Device\ST\STM32H7xx\Include\stm32h743xx.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h743xx.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>5</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Device\ST\STM32H7xx\Include\system_stm32h7xx.h</PathWithFileName>
+      <FilenameWithoutPath>system_stm32h7xx.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>6</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Include\cmsis_armcc.h</PathWithFileName>
+      <FilenameWithoutPath>cmsis_armcc.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>7</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Include\cmsis_armclang.h</PathWithFileName>
+      <FilenameWithoutPath>cmsis_armclang.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>8</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Include\cmsis_compiler.h</PathWithFileName>
+      <FilenameWithoutPath>cmsis_compiler.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>9</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Include\cmsis_gcc.h</PathWithFileName>
+      <FilenameWithoutPath>cmsis_gcc.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>10</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Include\cmsis_iccarm.h</PathWithFileName>
+      <FilenameWithoutPath>cmsis_iccarm.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>11</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Include\cmsis_version.h</PathWithFileName>
+      <FilenameWithoutPath>cmsis_version.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>12</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Include\core_armv8mbl.h</PathWithFileName>
+      <FilenameWithoutPath>core_armv8mbl.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>13</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Include\core_armv8mml.h</PathWithFileName>
+      <FilenameWithoutPath>core_armv8mml.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>14</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Include\core_cm0.h</PathWithFileName>
+      <FilenameWithoutPath>core_cm0.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>15</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Include\core_cm0plus.h</PathWithFileName>
+      <FilenameWithoutPath>core_cm0plus.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>16</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Include\core_cm1.h</PathWithFileName>
+      <FilenameWithoutPath>core_cm1.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>17</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Include\core_cm3.h</PathWithFileName>
+      <FilenameWithoutPath>core_cm3.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>18</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Include\core_cm4.h</PathWithFileName>
+      <FilenameWithoutPath>core_cm4.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>19</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Include\core_cm7.h</PathWithFileName>
+      <FilenameWithoutPath>core_cm7.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>20</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Include\core_cm23.h</PathWithFileName>
+      <FilenameWithoutPath>core_cm23.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>21</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Include\core_cm33.h</PathWithFileName>
+      <FilenameWithoutPath>core_cm33.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>22</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Include\core_sc000.h</PathWithFileName>
+      <FilenameWithoutPath>core_sc000.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>23</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Include\core_sc300.h</PathWithFileName>
+      <FilenameWithoutPath>core_sc300.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>24</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Include\mpu_armv7.h</PathWithFileName>
+      <FilenameWithoutPath>mpu_armv7.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>25</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Include\mpu_armv8.h</PathWithFileName>
+      <FilenameWithoutPath>mpu_armv8.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>26</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Include\tz_context.h</PathWithFileName>
+      <FilenameWithoutPath>tz_context.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>27</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32_USB_Device_Library\Core\Inc\usbd_core.h</PathWithFileName>
+      <FilenameWithoutPath>usbd_core.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>28</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32_USB_Device_Library\Core\Inc\usbd_ctlreq.h</PathWithFileName>
+      <FilenameWithoutPath>usbd_ctlreq.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>29</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32_USB_Device_Library\Core\Inc\usbd_def.h</PathWithFileName>
+      <FilenameWithoutPath>usbd_def.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>30</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32_USB_Device_Library\Core\Inc\usbd_ioreq.h</PathWithFileName>
+      <FilenameWithoutPath>usbd_ioreq.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>31</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32_USB_Device_Library\Core\Src\usbd_core.c</PathWithFileName>
+      <FilenameWithoutPath>usbd_core.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>32</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32_USB_Device_Library\Core\Src\usbd_ctlreq.c</PathWithFileName>
+      <FilenameWithoutPath>usbd_ctlreq.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>33</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32_USB_Device_Library\Core\Src\usbd_ioreq.c</PathWithFileName>
+      <FilenameWithoutPath>usbd_ioreq.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>34</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>35</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_cortex.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_cortex.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>36</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_def.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_def.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>37</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dma.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_dma.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>38</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dma_ex.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_dma_ex.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>39</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_exti.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_exti.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>40</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_fdcan.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_fdcan.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>41</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_flash.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_flash.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>42</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_flash_ex.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_flash_ex.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>43</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_gpio.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_gpio.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>44</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_gpio_ex.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_gpio_ex.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>45</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_hsem.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_hsem.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>46</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_i2c.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_i2c.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>47</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_i2c_ex.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_i2c_ex.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>48</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_mdma.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_mdma.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>49</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pcd.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_pcd.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>50</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pcd_ex.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_pcd_ex.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>51</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pwr.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_pwr.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>52</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pwr_ex.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_pwr_ex.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>53</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_rcc.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_rcc.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>54</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_rcc_ex.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_rcc_ex.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>55</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_tim.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_tim.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>56</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_tim_ex.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_tim_ex.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>57</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_bus.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_ll_bus.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>58</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_cortex.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_ll_cortex.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>59</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_crs.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_ll_crs.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>60</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_dma.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_ll_dma.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>61</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_dmamux.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_ll_dmamux.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>62</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_exti.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_ll_exti.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>63</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_gpio.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_ll_gpio.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>64</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_pwr.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_ll_pwr.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>65</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_rcc.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_ll_rcc.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>66</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_system.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_ll_system.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>67</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_usart.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_ll_usart.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>68</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_usb.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_ll_usb.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>69</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_utils.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_ll_utils.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>70</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h</PathWithFileName>
+      <FilenameWithoutPath>stm32_hal_legacy.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>71</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>72</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cortex.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_cortex.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>73</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_dma.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>74</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma_ex.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_dma_ex.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>75</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_exti.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_exti.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>76</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_fdcan.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_fdcan.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>77</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_flash.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>78</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash_ex.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_flash_ex.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>79</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_gpio.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_gpio.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>80</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hsem.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_hsem.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>81</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_i2c.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>82</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c_ex.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_i2c_ex.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>83</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mdma.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_mdma.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>84</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pcd.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_pcd.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>85</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pcd_ex.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_pcd_ex.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>86</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_pwr.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>87</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr_ex.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_pwr_ex.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>88</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_rcc.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>89</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc_ex.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_rcc_ex.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>90</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_tim.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>91</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim_ex.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_tim_ex.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>92</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_dma.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_ll_dma.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>93</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_exti.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_ll_exti.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>94</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_gpio.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_ll_gpio.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>95</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_rcc.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_ll_rcc.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>96</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_usart.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_ll_usart.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>97</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_usb.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_ll_usb.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>98</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_utils.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_ll_utils.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>App</GroupName>
+    <tvExp>1</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>99</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\blt_conf.h</PathWithFileName>
+      <FilenameWithoutPath>blt_conf.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>100</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\hooks.c</PathWithFileName>
+      <FilenameWithoutPath>hooks.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>101</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\led.c</PathWithFileName>
+      <FilenameWithoutPath>led.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>102</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\led.h</PathWithFileName>
+      <FilenameWithoutPath>led.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>103</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\main.c</PathWithFileName>
+      <FilenameWithoutPath>main.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>104</FileNumber>
+      <FileType>2</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\startup_stm32h743xx.s</PathWithFileName>
+      <FilenameWithoutPath>startup_stm32h743xx.s</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>105</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\usbd_bulk.c</PathWithFileName>
+      <FilenameWithoutPath>usbd_bulk.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>106</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\usbd_bulk.h</PathWithFileName>
+      <FilenameWithoutPath>usbd_bulk.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>107</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\usbd_conf.c</PathWithFileName>
+      <FilenameWithoutPath>usbd_conf.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>108</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\usbd_conf.h</PathWithFileName>
+      <FilenameWithoutPath>usbd_conf.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>109</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\usbd_desc.c</PathWithFileName>
+      <FilenameWithoutPath>usbd_desc.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>110</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\usbd_desc.h</PathWithFileName>
+      <FilenameWithoutPath>usbd_desc.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>Core</GroupName>
+    <tvExp>1</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>111</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\Source\assert.c</PathWithFileName>
+      <FilenameWithoutPath>assert.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>112</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\Source\assert.h</PathWithFileName>
+      <FilenameWithoutPath>assert.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>113</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\Source\backdoor.c</PathWithFileName>
+      <FilenameWithoutPath>backdoor.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>114</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\Source\backdoor.h</PathWithFileName>
+      <FilenameWithoutPath>backdoor.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>115</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\Source\boot.c</PathWithFileName>
+      <FilenameWithoutPath>boot.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>116</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\Source\boot.h</PathWithFileName>
+      <FilenameWithoutPath>boot.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>117</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\Source\can.h</PathWithFileName>
+      <FilenameWithoutPath>can.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>118</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\Source\com.c</PathWithFileName>
+      <FilenameWithoutPath>com.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>119</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\Source\com.h</PathWithFileName>
+      <FilenameWithoutPath>com.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>120</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\Source\cop.c</PathWithFileName>
+      <FilenameWithoutPath>cop.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>121</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\Source\cop.h</PathWithFileName>
+      <FilenameWithoutPath>cop.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>122</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\Source\cpu.h</PathWithFileName>
+      <FilenameWithoutPath>cpu.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>123</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\Source\file.c</PathWithFileName>
+      <FilenameWithoutPath>file.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>124</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\Source\file.h</PathWithFileName>
+      <FilenameWithoutPath>file.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>125</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\Source\net.c</PathWithFileName>
+      <FilenameWithoutPath>net.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>126</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\Source\net.h</PathWithFileName>
+      <FilenameWithoutPath>net.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>127</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\Source\nvm.h</PathWithFileName>
+      <FilenameWithoutPath>nvm.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>128</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\Source\plausibility.h</PathWithFileName>
+      <FilenameWithoutPath>plausibility.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>129</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\Source\rs232.h</PathWithFileName>
+      <FilenameWithoutPath>rs232.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>130</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\Source\timer.h</PathWithFileName>
+      <FilenameWithoutPath>timer.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>131</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\Source\usb.h</PathWithFileName>
+      <FilenameWithoutPath>usb.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>132</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\Source\xcp.c</PathWithFileName>
+      <FilenameWithoutPath>xcp.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>133</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\Source\xcp.h</PathWithFileName>
+      <FilenameWithoutPath>xcp.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>134</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\Source\ARMCM7_STM32H7\can.c</PathWithFileName>
+      <FilenameWithoutPath>can.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>135</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\Source\ARMCM7_STM32H7\cpu.c</PathWithFileName>
+      <FilenameWithoutPath>cpu.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>136</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\Source\ARMCM7_STM32H7\flash.c</PathWithFileName>
+      <FilenameWithoutPath>flash.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>137</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\Source\ARMCM7_STM32H7\flash.h</PathWithFileName>
+      <FilenameWithoutPath>flash.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>138</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\Source\ARMCM7_STM32H7\nvm.c</PathWithFileName>
+      <FilenameWithoutPath>nvm.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>139</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\Source\ARMCM7_STM32H7\rs232.c</PathWithFileName>
+      <FilenameWithoutPath>rs232.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>140</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\Source\ARMCM7_STM32H7\timer.c</PathWithFileName>
+      <FilenameWithoutPath>timer.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>141</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\Source\ARMCM7_STM32H7\types.h</PathWithFileName>
+      <FilenameWithoutPath>types.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>142</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\Source\ARMCM7_STM32H7\usb.c</PathWithFileName>
+      <FilenameWithoutPath>usb.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>143</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\..\Source\ARMCM7_STM32H7\Keil\cpu_comp.c</PathWithFileName>
+      <FilenameWithoutPath>cpu_comp.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+</ProjectOpt>
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/ide/stm32h743.uvprojx b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/ide/stm32h743.uvprojx
new file mode 100644
index 00000000..9ab45b97
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/ide/stm32h743.uvprojx
@@ -0,0 +1,1129 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>Target</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
+      <uAC6>0</uAC6>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>STM32H743ZITx</Device>
+          <Vendor>STMicroelectronics</Vendor>
+          <PackID>Keil.STM32H7xx_DFP.2.4.0</PackID>
+          <PackURL>https://www.keil.com/pack/</PackURL>
+          <Cpu>IRAM(0x20000000-0x2001FFFF) IRAM2(0x24000000-0x2407FFFF) IROM(0x8000000-0x81FFFFF) CLOCK(12000000) FPU3(DFPU) CPUTYPE("Cortex-M7") ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll></FlashDriverDll>
+          <DeviceId></DeviceId>
+          <RegisterFile></RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:STM32H743ZITx$CMSIS\SVD\STM32H743.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>..\bin\</OutputDirectory>
+          <OutputName>openblt_stm32h743</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath></ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>1</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name>fromelf --m32 --output=..\bin\openblt_stm32h743.srec ..\bin\openblt_stm32h743.axf</UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>0</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>-REMAP -MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM7</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments>-MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM7</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4100</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>STLink\ST-LINKIII-KEIL_SWO.dll</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M7"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>3</RvdsVP>
+            <RvdsMve>0</RvdsMve>
+            <hadIRAM2>1</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>1</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x200000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x200000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x24000000</StartAddress>
+                <Size>0x80000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>2</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <uGnu>0</uGnu>
+            <useXO>0</useXO>
+            <v6Lang>1</v6Lang>
+            <v6LangP>1</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls>--diag_suppress=111</MiscControls>
+              <Define>USE_FULL_LL_DRIVER,USE_HAL_DRIVER,STM32H743xx</Define>
+              <Undefine></Undefine>
+              <IncludePath>..\..\Boot;..\lib;..\lib\CMSIS\Device\ST\STM32H7xx\Include;..\lib\CMSIS\Include;..\lib\STM32H7xx_HAL_Driver\Inc;..\lib\STM32H7xx_HAL_Driver\Inc\Legacy;..\lib\STM32_USB_Device_Library\Core\Inc;..\..\..\..\Source;..\..\..\..\Source\ARMCM7_STM32H7</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <uClangAs>0</uClangAs>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x08000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile>..\stm32h743.sct</ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Lib</GroupName>
+          <Files>
+            <File>
+              <FileName>stm32h7xx_hal_conf.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\stm32h7xx_hal_conf.h</FilePath>
+            </File>
+            <File>
+              <FileName>system_stm32h7xx.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\system_stm32h7xx.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Device\ST\STM32H7xx\Include\stm32h7xx.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h743xx.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Device\ST\STM32H7xx\Include\stm32h743xx.h</FilePath>
+            </File>
+            <File>
+              <FileName>system_stm32h7xx.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Device\ST\STM32H7xx\Include\system_stm32h7xx.h</FilePath>
+            </File>
+            <File>
+              <FileName>cmsis_armcc.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Include\cmsis_armcc.h</FilePath>
+            </File>
+            <File>
+              <FileName>cmsis_armclang.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Include\cmsis_armclang.h</FilePath>
+            </File>
+            <File>
+              <FileName>cmsis_compiler.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Include\cmsis_compiler.h</FilePath>
+            </File>
+            <File>
+              <FileName>cmsis_gcc.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Include\cmsis_gcc.h</FilePath>
+            </File>
+            <File>
+              <FileName>cmsis_iccarm.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Include\cmsis_iccarm.h</FilePath>
+            </File>
+            <File>
+              <FileName>cmsis_version.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Include\cmsis_version.h</FilePath>
+            </File>
+            <File>
+              <FileName>core_armv8mbl.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Include\core_armv8mbl.h</FilePath>
+            </File>
+            <File>
+              <FileName>core_armv8mml.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Include\core_armv8mml.h</FilePath>
+            </File>
+            <File>
+              <FileName>core_cm0.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Include\core_cm0.h</FilePath>
+            </File>
+            <File>
+              <FileName>core_cm0plus.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Include\core_cm0plus.h</FilePath>
+            </File>
+            <File>
+              <FileName>core_cm1.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Include\core_cm1.h</FilePath>
+            </File>
+            <File>
+              <FileName>core_cm3.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Include\core_cm3.h</FilePath>
+            </File>
+            <File>
+              <FileName>core_cm4.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Include\core_cm4.h</FilePath>
+            </File>
+            <File>
+              <FileName>core_cm7.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Include\core_cm7.h</FilePath>
+            </File>
+            <File>
+              <FileName>core_cm23.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Include\core_cm23.h</FilePath>
+            </File>
+            <File>
+              <FileName>core_cm33.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Include\core_cm33.h</FilePath>
+            </File>
+            <File>
+              <FileName>core_sc000.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Include\core_sc000.h</FilePath>
+            </File>
+            <File>
+              <FileName>core_sc300.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Include\core_sc300.h</FilePath>
+            </File>
+            <File>
+              <FileName>mpu_armv7.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Include\mpu_armv7.h</FilePath>
+            </File>
+            <File>
+              <FileName>mpu_armv8.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Include\mpu_armv8.h</FilePath>
+            </File>
+            <File>
+              <FileName>tz_context.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Include\tz_context.h</FilePath>
+            </File>
+            <File>
+              <FileName>usbd_core.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32_USB_Device_Library\Core\Inc\usbd_core.h</FilePath>
+            </File>
+            <File>
+              <FileName>usbd_ctlreq.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32_USB_Device_Library\Core\Inc\usbd_ctlreq.h</FilePath>
+            </File>
+            <File>
+              <FileName>usbd_def.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32_USB_Device_Library\Core\Inc\usbd_def.h</FilePath>
+            </File>
+            <File>
+              <FileName>usbd_ioreq.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32_USB_Device_Library\Core\Inc\usbd_ioreq.h</FilePath>
+            </File>
+            <File>
+              <FileName>usbd_core.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32_USB_Device_Library\Core\Src\usbd_core.c</FilePath>
+            </File>
+            <File>
+              <FileName>usbd_ctlreq.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32_USB_Device_Library\Core\Src\usbd_ctlreq.c</FilePath>
+            </File>
+            <File>
+              <FileName>usbd_ioreq.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32_USB_Device_Library\Core\Src\usbd_ioreq.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_cortex.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_cortex.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_def.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_def.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_dma.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dma.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_dma_ex.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dma_ex.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_exti.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_exti.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_fdcan.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_fdcan.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_flash.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_flash.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_flash_ex.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_flash_ex.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_gpio.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_gpio.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_gpio_ex.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_gpio_ex.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_hsem.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_hsem.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_i2c.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_i2c.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_i2c_ex.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_i2c_ex.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_mdma.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_mdma.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_pcd.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pcd.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_pcd_ex.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pcd_ex.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_pwr.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pwr.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_pwr_ex.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pwr_ex.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_rcc.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_rcc.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_rcc_ex.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_rcc_ex.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_tim.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_tim.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_tim_ex.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_tim_ex.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_ll_bus.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_bus.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_ll_cortex.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_cortex.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_ll_crs.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_crs.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_ll_dma.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_dma.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_ll_dmamux.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_dmamux.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_ll_exti.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_exti.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_ll_gpio.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_gpio.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_ll_pwr.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_pwr.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_ll_rcc.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_rcc.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_ll_system.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_system.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_ll_usart.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_usart.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_ll_usb.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_usb.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_ll_utils.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_utils.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32_hal_legacy.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_cortex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cortex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_dma.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_dma_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma_ex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_exti.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_exti.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_fdcan.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_fdcan.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_flash.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_flash_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash_ex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_gpio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_gpio.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_hsem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hsem.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_i2c.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_i2c_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c_ex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_mdma.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mdma.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_pcd.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pcd.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_pcd_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pcd_ex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_pwr.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_pwr_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr_ex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_rcc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_rcc_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc_ex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_tim.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_tim_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim_ex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_ll_dma.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_dma.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_ll_exti.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_exti.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_ll_gpio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_gpio.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_ll_rcc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_rcc.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_ll_usart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_usart.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_ll_usb.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_usb.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_ll_utils.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_utils.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>App</GroupName>
+          <Files>
+            <File>
+              <FileName>blt_conf.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\blt_conf.h</FilePath>
+            </File>
+            <File>
+              <FileName>hooks.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\hooks.c</FilePath>
+            </File>
+            <File>
+              <FileName>led.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\led.c</FilePath>
+            </File>
+            <File>
+              <FileName>led.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\led.h</FilePath>
+            </File>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\main.c</FilePath>
+            </File>
+            <File>
+              <FileName>startup_stm32h743xx.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\startup_stm32h743xx.s</FilePath>
+            </File>
+            <File>
+              <FileName>usbd_bulk.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\usbd_bulk.c</FilePath>
+            </File>
+            <File>
+              <FileName>usbd_bulk.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\usbd_bulk.h</FilePath>
+            </File>
+            <File>
+              <FileName>usbd_conf.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\usbd_conf.c</FilePath>
+            </File>
+            <File>
+              <FileName>usbd_conf.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\usbd_conf.h</FilePath>
+            </File>
+            <File>
+              <FileName>usbd_desc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\usbd_desc.c</FilePath>
+            </File>
+            <File>
+              <FileName>usbd_desc.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\usbd_desc.h</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Core</GroupName>
+          <Files>
+            <File>
+              <FileName>assert.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Source\assert.c</FilePath>
+            </File>
+            <File>
+              <FileName>assert.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\..\..\..\Source\assert.h</FilePath>
+            </File>
+            <File>
+              <FileName>backdoor.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Source\backdoor.c</FilePath>
+            </File>
+            <File>
+              <FileName>backdoor.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\..\..\..\Source\backdoor.h</FilePath>
+            </File>
+            <File>
+              <FileName>boot.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Source\boot.c</FilePath>
+            </File>
+            <File>
+              <FileName>boot.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\..\..\..\Source\boot.h</FilePath>
+            </File>
+            <File>
+              <FileName>can.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\..\..\..\Source\can.h</FilePath>
+            </File>
+            <File>
+              <FileName>com.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Source\com.c</FilePath>
+            </File>
+            <File>
+              <FileName>com.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\..\..\..\Source\com.h</FilePath>
+            </File>
+            <File>
+              <FileName>cop.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Source\cop.c</FilePath>
+            </File>
+            <File>
+              <FileName>cop.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\..\..\..\Source\cop.h</FilePath>
+            </File>
+            <File>
+              <FileName>cpu.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\..\..\..\Source\cpu.h</FilePath>
+            </File>
+            <File>
+              <FileName>file.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Source\file.c</FilePath>
+            </File>
+            <File>
+              <FileName>file.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\..\..\..\Source\file.h</FilePath>
+            </File>
+            <File>
+              <FileName>net.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Source\net.c</FilePath>
+            </File>
+            <File>
+              <FileName>net.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\..\..\..\Source\net.h</FilePath>
+            </File>
+            <File>
+              <FileName>nvm.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\..\..\..\Source\nvm.h</FilePath>
+            </File>
+            <File>
+              <FileName>plausibility.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\..\..\..\Source\plausibility.h</FilePath>
+            </File>
+            <File>
+              <FileName>rs232.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\..\..\..\Source\rs232.h</FilePath>
+            </File>
+            <File>
+              <FileName>timer.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\..\..\..\Source\timer.h</FilePath>
+            </File>
+            <File>
+              <FileName>usb.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\..\..\..\Source\usb.h</FilePath>
+            </File>
+            <File>
+              <FileName>xcp.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Source\xcp.c</FilePath>
+            </File>
+            <File>
+              <FileName>xcp.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\..\..\..\Source\xcp.h</FilePath>
+            </File>
+            <File>
+              <FileName>can.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Source\ARMCM7_STM32H7\can.c</FilePath>
+            </File>
+            <File>
+              <FileName>cpu.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Source\ARMCM7_STM32H7\cpu.c</FilePath>
+            </File>
+            <File>
+              <FileName>flash.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Source\ARMCM7_STM32H7\flash.c</FilePath>
+            </File>
+            <File>
+              <FileName>flash.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\..\..\..\Source\ARMCM7_STM32H7\flash.h</FilePath>
+            </File>
+            <File>
+              <FileName>nvm.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Source\ARMCM7_STM32H7\nvm.c</FilePath>
+            </File>
+            <File>
+              <FileName>rs232.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Source\ARMCM7_STM32H7\rs232.c</FilePath>
+            </File>
+            <File>
+              <FileName>timer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Source\ARMCM7_STM32H7\timer.c</FilePath>
+            </File>
+            <File>
+              <FileName>types.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\..\..\..\Source\ARMCM7_STM32H7\types.h</FilePath>
+            </File>
+            <File>
+              <FileName>usb.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Source\ARMCM7_STM32H7\usb.c</FilePath>
+            </File>
+            <File>
+              <FileName>cpu_comp.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\Source\ARMCM7_STM32H7\Keil\cpu_comp.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components>
+      <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="4.3.0" condition="CMSIS Core">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.5.0"/>
+        <targetInfos>
+          <targetInfo name="Boot"/>
+        </targetInfos>
+      </component>
+    </components>
+    <files/>
+  </RTE>
+
+</Project>
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/led.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/led.c
new file mode 100644
index 00000000..f1e8f555
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/led.c
@@ -0,0 +1,101 @@
+/************************************************************************************//**
+* \file         Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/led.c
+* \brief        LED driver source file.
+* \ingroup      Boot_ARMCM7_STM32H7_Nucleo_H743ZI_Keil
+* \internal
+*----------------------------------------------------------------------------------------
+*                          C O P Y R I G H T
+*----------------------------------------------------------------------------------------
+*   Copyright (c) 2020  by Feaser    http://www.feaser.com    All rights reserved
+*
+*----------------------------------------------------------------------------------------
+*                            L I C E N S E
+*----------------------------------------------------------------------------------------
+* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as published by the Free
+* Software Foundation, either version 3 of the License, or (at your option) any later
+* version.
+*
+* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+* PURPOSE. See the GNU General Public License for more details.
+*
+* You have received a copy of the GNU General Public License along with OpenBLT. It
+* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
+*
+* \endinternal
+****************************************************************************************/
+
+/****************************************************************************************
+* Include files
+****************************************************************************************/
+#include "boot.h"                                /* bootloader generic header          */
+#include "led.h"                                 /* module header                      */
+#include "stm32h7xx.h"                           /* STM32 CPU and HAL header           */
+#include "stm32h7xx_ll_gpio.h"                   /* STM32 LL GPIO header               */
+
+
+/****************************************************************************************
+* Local data declarations
+****************************************************************************************/
+/** \brief Holds the desired LED blink interval time. */
+static blt_int16u ledBlinkIntervalMs;
+
+
+/************************************************************************************//**
+** \brief     Initializes the LED blink driver.
+** \param     interval_ms Specifies the desired LED blink interval time in milliseconds.
+** \return    none.
+**
+****************************************************************************************/
+void LedBlinkInit(blt_int16u interval_ms)
+{
+  /* store the interval time between LED toggles */
+  ledBlinkIntervalMs = interval_ms;
+} /*** end of LedBlinkInit ***/
+
+
+/************************************************************************************//**
+** \brief     Task function for blinking the LED as a fixed timer interval.
+** \return    none.
+**
+****************************************************************************************/
+void LedBlinkTask(void)
+{
+  static blt_bool ledOn = BLT_FALSE;
+  static blt_int32u nextBlinkEvent = 0;
+
+  /* check for blink event */
+  if (TimerGet() >= nextBlinkEvent)
+  {
+    /* toggle the LED state */
+    if (ledOn == BLT_FALSE)
+    {
+      ledOn = BLT_TRUE;
+      LL_GPIO_SetOutputPin(GPIOB, LL_GPIO_PIN_7);
+    }
+    else
+    {
+      ledOn = BLT_FALSE;
+      LL_GPIO_ResetOutputPin(GPIOB, LL_GPIO_PIN_7);
+    }
+    /* schedule the next blink event */
+    nextBlinkEvent = TimerGet() + ledBlinkIntervalMs;
+  }
+} /*** end of LedBlinkTask ***/
+
+
+/************************************************************************************//**
+** \brief     Cleans up the LED blink driver. This is intended to be used upon program
+**            exit.
+** \return    none.
+**
+****************************************************************************************/
+void LedBlinkExit(void)
+{
+  /* turn the LED off */
+  LL_GPIO_ResetOutputPin(GPIOB, LL_GPIO_PIN_7);
+} /*** end of LedBlinkExit ***/
+
+
+/*********************************** end of led.c **************************************/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/led.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/led.h
new file mode 100644
index 00000000..7e958a47
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/led.h
@@ -0,0 +1,40 @@
+/************************************************************************************//**
+* \file         Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/led.h
+* \brief        LED driver header file.
+* \ingroup      Boot_ARMCM7_STM32H7_Nucleo_H743ZI_Keil
+* \internal
+*----------------------------------------------------------------------------------------
+*                          C O P Y R I G H T
+*----------------------------------------------------------------------------------------
+*   Copyright (c) 2020  by Feaser    http://www.feaser.com    All rights reserved
+*
+*----------------------------------------------------------------------------------------
+*                            L I C E N S E
+*----------------------------------------------------------------------------------------
+* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as published by the Free
+* Software Foundation, either version 3 of the License, or (at your option) any later
+* version.
+*
+* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+* PURPOSE. See the GNU General Public License for more details.
+*
+* You have received a copy of the GNU General Public License along with OpenBLT. It 
+* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
+*
+* \endinternal
+****************************************************************************************/
+#ifndef LED_H
+#define LED_H
+
+/****************************************************************************************
+* Function prototypes
+****************************************************************************************/
+void LedBlinkInit(blt_int16u interval_ms);
+void LedBlinkTask(void);
+void LedBlinkExit(void);
+
+
+#endif /* LED_H */
+/*********************************** end of led.h **************************************/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h
new file mode 100644
index 00000000..cdcde7d9
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h
@@ -0,0 +1,26288 @@
+/**
+  ******************************************************************************
+  * @file    stm32h743xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32H743xx Device Peripheral Access Layer Header File.
+  *
+  *          This file contains:
+  *           - Data structures and the address mapping for all peripherals
+  *           - Peripheral's registers declarations and bits definition
+  *           - Macros to access peripheral's registers hardware
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS_Device
+  * @{
+  */
+
+/** @addtogroup stm32h743xx
+  * @{
+  */
+
+#ifndef STM32H743xx_H
+#define STM32H743xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+  * @{
+  */
+
+/**
+ * @brief STM32H7XX Interrupt Number Definition, according to the selected device
+ *        in @ref Library_configuration_section
+ */
+typedef enum
+{
+/******  Cortex-M Processor Exceptions Numbers *****************************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
+  HardFault_IRQn              = -13,    /*!< 4 Cortex-M Memory Management Interrupt                            */
+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M Memory Management Interrupt                            */
+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M Bus Fault Interrupt                                    */
+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M Usage Fault Interrupt                                  */
+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M SV Call Interrupt                                     */
+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M Debug Monitor Interrupt                               */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M Pend SV Interrupt                                     */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M System Tick Interrupt                                 */
+/******  STM32 specific Interrupt Numbers **********************************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it)                   */
+  PVD_AVD_IRQn                = 1,      /*!< PVD/AVD through EXTI Line detection Interrupt                     */
+  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
+  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
+  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
+  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
+  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
+  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
+  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
+  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
+  ADC_IRQn                    = 18,     /*!< ADC1 and  ADC2 global Interrupts                                  */
+  FDCAN1_IT0_IRQn             = 19,     /*!< FDCAN1 Interrupt line 0                                           */
+  FDCAN2_IT0_IRQn             = 20,     /*!< FDCAN2 Interrupt line 0                                           */
+  FDCAN1_IT1_IRQn             = 21,     /*!< FDCAN1 Interrupt line 1                                           */
+  FDCAN2_IT1_IRQn             = 22,     /*!< FDCAN2 Interrupt line 1                                           */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
+  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                              */
+  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                             */
+  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt                            */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
+  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
+  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
+  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
+  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
+  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
+  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */
+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
+  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
+  DMA2_Stream0_IRQn           = 56,     /*!<   DMA2 Stream 0 global Interrupt                                  */
+  DMA2_Stream1_IRQn           = 57,     /*!<   DMA2 Stream 1 global Interrupt                                  */
+  DMA2_Stream2_IRQn           = 58,     /*!<   DMA2 Stream 2 global Interrupt                                  */
+  DMA2_Stream3_IRQn           = 59,     /*!<   DMA2 Stream 3 global Interrupt                                  */
+  DMA2_Stream4_IRQn           = 60,     /*!<   DMA2 Stream 4 global Interrupt                                  */
+  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
+  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
+  FDCAN_CAL_IRQn              = 63,     /*!< FDCAN Calibration unit Interrupt                                  */
+  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
+  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
+  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
+  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
+  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
+  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
+  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
+  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
+  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
+  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
+  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
+  RNG_IRQn                    = 80,     /*!< RNG global interrupt                                              */
+  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
+  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */
+  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */
+  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
+  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */
+  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */
+  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */
+  LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                             */
+  LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                       */
+  DMA2D_IRQn                  = 90,     /*!< DMA2D global Interrupt                                            */
+  SAI2_IRQn                   = 91,     /*!< SAI2 global Interrupt                                             */
+  QUADSPI_IRQn                = 92,     /*!< Quad SPI global interrupt                                         */
+  LPTIM1_IRQn                 = 93,     /*!< LP TIM1 interrupt                                                 */
+  CEC_IRQn                    = 94,     /*!< HDMI-CEC global Interrupt                                         */
+  I2C4_EV_IRQn                = 95,     /*!< I2C4 Event Interrupt                                              */
+  I2C4_ER_IRQn                = 96,     /*!< I2C4 Error Interrupt                                              */
+  SPDIF_RX_IRQn               = 97,     /*!< SPDIF-RX global Interrupt                                         */
+  OTG_FS_EP1_OUT_IRQn         = 98,     /*!< USB OTG HS2 global interrupt                                      */
+  OTG_FS_EP1_IN_IRQn          = 99,     /*!< USB OTG HS2 End Point 1 Out global interrupt                      */
+  OTG_FS_WKUP_IRQn            = 100,    /*!< USB OTG HS2 End Point 1 In global interrupt                       */
+  OTG_FS_IRQn                 = 101,    /*!< USB OTG HS2 Wakeup through EXTI interrupt                         */
+  DMAMUX1_OVR_IRQn            = 102,    /*!<DMAMUX1 Overrun interrupt                                          */
+  HRTIM1_Master_IRQn          = 103,    /*!< HRTIM Master Timer global Interrupts                              */
+  HRTIM1_TIMA_IRQn            = 104,    /*!< HRTIM Timer A global Interrupt                                    */
+  HRTIM1_TIMB_IRQn            = 105,    /*!< HRTIM Timer B global Interrupt                                    */
+  HRTIM1_TIMC_IRQn            = 106,    /*!< HRTIM Timer C global Interrupt                                    */
+  HRTIM1_TIMD_IRQn            = 107,    /*!< HRTIM Timer D global Interrupt                                    */
+  HRTIM1_TIME_IRQn            = 108,    /*!< HRTIM Timer E global Interrupt                                    */
+  HRTIM1_FLT_IRQn             = 109,    /*!< HRTIM Fault global Interrupt                                      */
+  DFSDM1_FLT0_IRQn            = 110,    /*!<DFSDM Filter1 Interrupt                                            */
+  DFSDM1_FLT1_IRQn            = 111,    /*!<DFSDM Filter2 Interrupt                                            */
+  DFSDM1_FLT2_IRQn            = 112,    /*!<DFSDM Filter3 Interrupt                                            */
+  DFSDM1_FLT3_IRQn            = 113,    /*!<DFSDM Filter4 Interrupt                                            */
+  SAI3_IRQn                   = 114,    /*!< SAI3 global Interrupt                                             */
+  SWPMI1_IRQn                 = 115,    /*!< Serial Wire Interface 1 global interrupt                          */
+  TIM15_IRQn                  = 116,    /*!< TIM15 global Interrupt                                            */
+  TIM16_IRQn                  = 117,    /*!< TIM16 global Interrupt                                            */
+  TIM17_IRQn                  = 118,    /*!< TIM17 global Interrupt                                            */
+  MDIOS_WKUP_IRQn             = 119,    /*!< MDIOS Wakeup  Interrupt                                           */
+  MDIOS_IRQn                  = 120,    /*!< MDIOS global Interrupt                                            */
+  JPEG_IRQn                   = 121,    /*!< JPEG global Interrupt                                             */
+  MDMA_IRQn                   = 122,    /*!< MDMA global Interrupt                                             */
+  SDMMC2_IRQn                 = 124,    /*!< SDMMC2 global Interrupt                                           */
+  HSEM1_IRQn                  = 125,    /*!< HSEM1 global Interrupt                                            */
+  ADC3_IRQn                   = 127,    /*!< ADC3 global Interrupt                                             */
+  DMAMUX2_OVR_IRQn            = 128,    /*!<DMAMUX2 Overrun interrupt                                          */
+  BDMA_Channel0_IRQn          = 129,    /*!< BDMA Channel 0 global Interrupt                                   */
+  BDMA_Channel1_IRQn          = 130,    /*!< BDMA Channel 1 global Interrupt                                   */
+  BDMA_Channel2_IRQn          = 131,    /*!< BDMA Channel 2 global Interrupt                                   */
+  BDMA_Channel3_IRQn          = 132,    /*!< BDMA Channel 3 global Interrupt                                   */
+  BDMA_Channel4_IRQn          = 133,    /*!< BDMA Channel 4 global Interrupt                                   */
+  BDMA_Channel5_IRQn          = 134,    /*!< BDMA Channel 5 global Interrupt                                   */
+  BDMA_Channel6_IRQn          = 135,    /*!< BDMA Channel 6 global Interrupt                                   */
+  BDMA_Channel7_IRQn          = 136,    /*!< BDMA Channel 7 global Interrupt                                   */
+  COMP_IRQn                   = 137 ,   /*!< COMP global Interrupt                                             */
+  LPTIM2_IRQn                 = 138,    /*!< LP TIM2 global interrupt                                          */
+  LPTIM3_IRQn                 = 139,    /*!< LP TIM3 global interrupt                                          */
+  LPTIM4_IRQn                 = 140,    /*!< LP TIM4 global interrupt                                          */
+  LPTIM5_IRQn                 = 141,    /*!< LP TIM5 global interrupt                                          */
+  LPUART1_IRQn                = 142,    /*!< LP UART1 interrupt                                                */
+  CRS_IRQn                    = 144,    /*!< Clock Recovery Global Interrupt                                   */
+  ECC_IRQn                    = 145,    /*!< ECC diagnostic Global Interrupt                                   */
+  SAI4_IRQn                   = 146,    /*!< SAI4 global interrupt                                             */
+  WAKEUP_PIN_IRQn             = 149,    /*!< Interrupt for all 6 wake-up pins                                  */
+} IRQn_Type;
+
+/**
+  * @}
+  */
+
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+
+
+
+
+/**
+  * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
+   */
+#define __CM7_REV               0x0100U   /*!< Cortex-M7 revision r1p0                       */
+#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */
+#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */
+#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1       /*!< FPU present                                   */
+#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */
+#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */
+#include "core_cm7.h"                     /*!< Cortex-M7 processor and core peripherals      */
+
+/**
+  * @}
+  */
+
+
+
+
+#include "system_stm32h7xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+  * @{
+  */
+
+/**
+  * @brief Analog to Digital Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t ISR;              /*!< ADC Interrupt and Status Register,                          Address offset: 0x00 */
+  __IO uint32_t IER;              /*!< ADC Interrupt Enable Register,                              Address offset: 0x04 */
+  __IO uint32_t CR;               /*!< ADC control register,                                       Address offset: 0x08 */
+  __IO uint32_t CFGR;             /*!< ADC Configuration register,                                 Address offset: 0x0C */
+  __IO uint32_t CFGR2;            /*!< ADC Configuration register 2,                               Address offset: 0x10 */
+  __IO uint32_t SMPR1;            /*!< ADC sample time register 1,                                 Address offset: 0x14 */
+  __IO uint32_t SMPR2;            /*!< ADC sample time register 2,                                 Address offset: 0x18 */
+  __IO uint32_t PCSEL;            /*!< ADC pre-channel selection,                                  Address offset: 0x1C */
+  __IO uint32_t LTR1;             /*!< ADC watchdog Lower threshold register 1,                    Address offset: 0x20 */
+  __IO uint32_t HTR1;             /*!< ADC watchdog higher threshold register 1,                   Address offset: 0x24 */
+  uint32_t      RESERVED1;        /*!< Reserved, 0x028                                                                  */
+  uint32_t      RESERVED2;        /*!< Reserved, 0x02C                                                                  */
+  __IO uint32_t SQR1;             /*!< ADC regular sequence register 1,                            Address offset: 0x30 */
+  __IO uint32_t SQR2;             /*!< ADC regular sequence register 2,                            Address offset: 0x34 */
+  __IO uint32_t SQR3;             /*!< ADC regular sequence register 3,                            Address offset: 0x38 */
+  __IO uint32_t SQR4;             /*!< ADC regular sequence register 4,                            Address offset: 0x3C */
+  __IO uint32_t DR;               /*!< ADC regular data register,                                  Address offset: 0x40 */
+  uint32_t      RESERVED3;        /*!< Reserved, 0x044                                                                  */
+  uint32_t      RESERVED4;        /*!< Reserved, 0x048                                                                  */
+  __IO uint32_t JSQR;             /*!< ADC injected sequence register,                             Address offset: 0x4C */
+  uint32_t      RESERVED5[4];     /*!< Reserved, 0x050 - 0x05C                                                          */
+  __IO uint32_t OFR1;             /*!< ADC offset register 1,                                      Address offset: 0x60 */
+  __IO uint32_t OFR2;             /*!< ADC offset register 2,                                      Address offset: 0x64 */
+  __IO uint32_t OFR3;             /*!< ADC offset register 3,                                      Address offset: 0x68 */
+  __IO uint32_t OFR4;             /*!< ADC offset register 4,                                      Address offset: 0x6C */
+  uint32_t      RESERVED6[4];     /*!< Reserved, 0x070 - 0x07C                                                          */
+  __IO uint32_t JDR1;             /*!< ADC injected data register 1,                               Address offset: 0x80 */
+  __IO uint32_t JDR2;             /*!< ADC injected data register 2,                               Address offset: 0x84 */
+  __IO uint32_t JDR3;             /*!< ADC injected data register 3,                               Address offset: 0x88 */
+  __IO uint32_t JDR4;             /*!< ADC injected data register 4,                               Address offset: 0x8C */
+  uint32_t      RESERVED7[4];     /*!< Reserved, 0x090 - 0x09C                                                          */
+  __IO uint32_t AWD2CR;           /*!< ADC  Analog Watchdog 2 Configuration Register,              Address offset: 0xA0 */
+  __IO uint32_t AWD3CR;           /*!< ADC  Analog Watchdog 3 Configuration Register,              Address offset: 0xA4 */
+  uint32_t      RESERVED8;        /*!< Reserved, 0x0A8                                                                  */
+  uint32_t      RESERVED9;        /*!< Reserved, 0x0AC                                                                  */
+  __IO uint32_t LTR2;             /*!< ADC watchdog Lower threshold register 2,                    Address offset: 0xB0 */
+  __IO uint32_t HTR2;             /*!< ADC watchdog Higher threshold register 2,                   Address offset: 0xB4 */
+  __IO uint32_t LTR3;             /*!< ADC watchdog Lower threshold register 3,                    Address offset: 0xB8 */
+  __IO uint32_t HTR3;             /*!< ADC watchdog Higher threshold register 3,                   Address offset: 0xBC */
+  __IO uint32_t DIFSEL;           /*!< ADC  Differential Mode Selection Register,                  Address offset: 0xC0 */
+  __IO uint32_t CALFACT;          /*!< ADC  Calibration Factors,                                   Address offset: 0xC4 */
+  __IO uint32_t CALFACT2;         /*!< ADC  Linearity Calibration Factors,                         Address offset: 0xC8 */
+} ADC_TypeDef;
+
+
+typedef struct
+{
+__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
+uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
+__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
+__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */
+__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */
+
+} ADC_Common_TypeDef;
+
+
+/**
+  * @brief VREFBUF
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */
+  __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */
+} VREFBUF_TypeDef;
+
+
+/**
+  * @brief FD Controller Area Network
+  */
+
+typedef struct
+{
+  __IO uint32_t CREL;         /*!< FDCAN Core Release register,                                     Address offset: 0x000 */
+  __IO uint32_t ENDN;         /*!< FDCAN Endian register,                                           Address offset: 0x004 */
+  __IO uint32_t RESERVED1;    /*!< Reserved,                                                                        0x008 */
+  __IO uint32_t DBTP;         /*!< FDCAN Data Bit Timing & Prescaler register,                      Address offset: 0x00C */
+  __IO uint32_t TEST;         /*!< FDCAN Test register,                                             Address offset: 0x010 */
+  __IO uint32_t RWD;          /*!< FDCAN RAM Watchdog register,                                     Address offset: 0x014 */
+  __IO uint32_t CCCR;         /*!< FDCAN CC Control register,                                       Address offset: 0x018 */
+  __IO uint32_t NBTP;         /*!< FDCAN Nominal Bit Timing & Prescaler register,                   Address offset: 0x01C */
+  __IO uint32_t TSCC;         /*!< FDCAN Timestamp Counter Configuration register,                  Address offset: 0x020 */
+  __IO uint32_t TSCV;         /*!< FDCAN Timestamp Counter Value register,                          Address offset: 0x024 */
+  __IO uint32_t TOCC;         /*!< FDCAN Timeout Counter Configuration register,                    Address offset: 0x028 */
+  __IO uint32_t TOCV;         /*!< FDCAN Timeout Counter Value register,                            Address offset: 0x02C */
+  __IO uint32_t RESERVED2[4]; /*!< Reserved,                                                                0x030 - 0x03C */
+  __IO uint32_t ECR;          /*!< FDCAN Error Counter register,                                    Address offset: 0x040 */
+  __IO uint32_t PSR;          /*!< FDCAN Protocol Status register,                                  Address offset: 0x044 */
+  __IO uint32_t TDCR;         /*!< FDCAN Transmitter Delay Compensation register,                   Address offset: 0x048 */
+  __IO uint32_t RESERVED3;    /*!< Reserved,                                                                        0x04C */
+  __IO uint32_t IR;           /*!< FDCAN Interrupt register,                                        Address offset: 0x050 */
+  __IO uint32_t IE;           /*!< FDCAN Interrupt Enable register,                                 Address offset: 0x054 */
+  __IO uint32_t ILS;          /*!< FDCAN Interrupt Line Select register,                            Address offset: 0x058 */
+  __IO uint32_t ILE;          /*!< FDCAN Interrupt Line Enable register,                            Address offset: 0x05C */
+  __IO uint32_t RESERVED4[8]; /*!< Reserved,                                                                0x060 - 0x07C */
+  __IO uint32_t GFC;          /*!< FDCAN Global Filter Configuration register,                      Address offset: 0x080 */
+  __IO uint32_t SIDFC;        /*!< FDCAN Standard ID Filter Configuration register,                 Address offset: 0x084 */
+  __IO uint32_t XIDFC;        /*!< FDCAN Extended ID Filter Configuration register,                 Address offset: 0x088 */
+  __IO uint32_t RESERVED5;    /*!< Reserved,                                                                        0x08C */
+  __IO uint32_t XIDAM;        /*!< FDCAN Extended ID AND Mask register,                             Address offset: 0x090 */
+  __IO uint32_t HPMS;         /*!< FDCAN High Priority Message Status register,                     Address offset: 0x094 */
+  __IO uint32_t NDAT1;        /*!< FDCAN New Data 1 register,                                       Address offset: 0x098 */
+  __IO uint32_t NDAT2;        /*!< FDCAN New Data 2 register,                                       Address offset: 0x09C */
+  __IO uint32_t RXF0C;        /*!< FDCAN Rx FIFO 0 Configuration register,                          Address offset: 0x0A0 */
+  __IO uint32_t RXF0S;        /*!< FDCAN Rx FIFO 0 Status register,                                 Address offset: 0x0A4 */
+  __IO uint32_t RXF0A;        /*!< FDCAN Rx FIFO 0 Acknowledge register,                            Address offset: 0x0A8 */
+  __IO uint32_t RXBC;         /*!< FDCAN Rx Buffer Configuration register,                          Address offset: 0x0AC */
+  __IO uint32_t RXF1C;        /*!< FDCAN Rx FIFO 1 Configuration register,                          Address offset: 0x0B0 */
+  __IO uint32_t RXF1S;        /*!< FDCAN Rx FIFO 1 Status register,                                 Address offset: 0x0B4 */
+  __IO uint32_t RXF1A;        /*!< FDCAN Rx FIFO 1 Acknowledge register,                            Address offset: 0x0B8 */
+  __IO uint32_t RXESC;        /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register,        Address offset: 0x0BC */
+  __IO uint32_t TXBC;         /*!< FDCAN Tx Buffer Configuration register,                          Address offset: 0x0C0 */
+  __IO uint32_t TXFQS;        /*!< FDCAN Tx FIFO/Queue Status register,                             Address offset: 0x0C4 */
+  __IO uint32_t TXESC;        /*!< FDCAN Tx Buffer Element Size Configuration register,             Address offset: 0x0C8 */
+  __IO uint32_t TXBRP;        /*!< FDCAN Tx Buffer Request Pending register,                        Address offset: 0x0CC */
+  __IO uint32_t TXBAR;        /*!< FDCAN Tx Buffer Add Request register,                            Address offset: 0x0D0 */
+  __IO uint32_t TXBCR;        /*!< FDCAN Tx Buffer Cancellation Request register,                   Address offset: 0x0D4 */
+  __IO uint32_t TXBTO;        /*!< FDCAN Tx Buffer Transmission Occurred register,                  Address offset: 0x0D8 */
+  __IO uint32_t TXBCF;        /*!< FDCAN Tx Buffer Cancellation Finished register,                  Address offset: 0x0DC */
+  __IO uint32_t TXBTIE;       /*!< FDCAN Tx Buffer Transmission Interrupt Enable register,          Address offset: 0x0E0 */
+  __IO uint32_t TXBCIE;       /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */
+  __IO uint32_t RESERVED6[2]; /*!< Reserved,                                                                0x0E8 - 0x0EC */
+  __IO uint32_t TXEFC;        /*!< FDCAN Tx Event FIFO Configuration register,                      Address offset: 0x0F0 */
+  __IO uint32_t TXEFS;        /*!< FDCAN Tx Event FIFO Status register,                             Address offset: 0x0F4 */
+  __IO uint32_t TXEFA;        /*!< FDCAN Tx Event FIFO Acknowledge register,                        Address offset: 0x0F8 */
+  __IO uint32_t RESERVED7;    /*!< Reserved,                                                                        0x0FC */
+} FDCAN_GlobalTypeDef;
+
+/**
+  * @brief TTFD Controller Area Network
+  */
+
+typedef struct
+{
+  __IO uint32_t TTTMC;          /*!< TT Trigger Memory Configuration register,    Address offset: 0x100 */
+  __IO uint32_t TTRMC;          /*!< TT Reference Message Configuration register, Address offset: 0x104 */
+  __IO uint32_t TTOCF;          /*!< TT Operation Configuration register,         Address offset: 0x108 */
+  __IO uint32_t TTMLM;          /*!< TT Matrix Limits register,                   Address offset: 0x10C */
+  __IO uint32_t TURCF;          /*!< TUR Configuration register,                  Address offset: 0x110 */
+  __IO uint32_t TTOCN;          /*!< TT Operation Control register,               Address offset: 0x114 */
+  __IO uint32_t TTGTP;          /*!< TT Global Time Preset register,              Address offset: 0x118 */
+  __IO uint32_t TTTMK;          /*!< TT Time Mark register,                       Address offset: 0x11C */
+  __IO uint32_t TTIR;           /*!< TT Interrupt register,                       Address offset: 0x120 */
+  __IO uint32_t TTIE;           /*!< TT Interrupt Enable register,                Address offset: 0x124 */
+  __IO uint32_t TTILS;          /*!< TT Interrupt Line Select register,           Address offset: 0x128 */
+  __IO uint32_t TTOST;          /*!< TT Operation Status register,                Address offset: 0x12C */
+  __IO uint32_t TURNA;          /*!< TT TUR Numerator Actual register,            Address offset: 0x130 */
+  __IO uint32_t TTLGT;          /*!< TT Local and Global Time register,           Address offset: 0x134 */
+  __IO uint32_t TTCTC;          /*!< TT Cycle Time and Count register,            Address offset: 0x138 */
+  __IO uint32_t TTCPT;          /*!< TT Capture Time register,                    Address offset: 0x13C */
+  __IO uint32_t TTCSM;          /*!< TT Cycle Sync Mark register,                 Address offset: 0x140 */
+  __IO uint32_t RESERVED1[111]; /*!< Reserved,                                            0x144 - 0x2FC */
+  __IO uint32_t TTTS;           /*!< TT Trigger Select register,                  Address offset: 0x300 */
+} TTCAN_TypeDef;
+
+/**
+  * @brief FD Controller Area Network
+  */
+
+typedef struct
+{
+  __IO uint32_t CREL;  /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */
+  __IO uint32_t CCFG;  /*!< Calibration Configuration register,           Address offset: 0x04 */
+  __IO uint32_t CSTAT; /*!< Calibration Status register,                  Address offset: 0x08 */
+  __IO uint32_t CWD;   /*!< Calibration Watchdog register,                Address offset: 0x0C */
+  __IO uint32_t IR;    /*!< CCU Interrupt register,                       Address offset: 0x10 */
+  __IO uint32_t IE;    /*!< CCU Interrupt Enable register,                Address offset: 0x14 */
+} FDCAN_ClockCalibrationUnit_TypeDef;
+
+
+/**
+  * @brief Consumer Electronics Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;           /*!< CEC control register,              Address offset:0x00 */
+  __IO uint32_t CFGR;         /*!< CEC configuration register,        Address offset:0x04 */
+  __IO uint32_t TXDR;         /*!< CEC Tx data register ,             Address offset:0x08 */
+  __IO uint32_t RXDR;         /*!< CEC Rx Data Register,              Address offset:0x0C */
+  __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register, Address offset:0x10 */
+  __IO uint32_t IER;          /*!< CEC interrupt enable register,     Address offset:0x14 */
+}CEC_TypeDef;
+
+/**
+  * @brief CRC calculation unit
+  */
+
+typedef struct
+{
+  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
+  __IO uint32_t IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
+  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
+  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */
+  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
+  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
+} CRC_TypeDef;
+
+
+/**
+  * @brief Clock Recovery System
+  */
+typedef struct
+{
+__IO uint32_t CR;            /*!< CRS ccontrol register,              Address offset: 0x00 */
+__IO uint32_t CFGR;          /*!< CRS configuration register,         Address offset: 0x04 */
+__IO uint32_t ISR;           /*!< CRS interrupt and status register,  Address offset: 0x08 */
+__IO uint32_t ICR;           /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
+} CRS_TypeDef;
+
+
+/**
+  * @brief Digital to Analog Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
+  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
+  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
+  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
+  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
+  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
+  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
+  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
+  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
+  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
+  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
+  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
+  __IO uint32_t CCR;      /*!< DAC calibration control register,                        Address offset: 0x38 */
+  __IO uint32_t MCR;      /*!< DAC mode control register,                               Address offset: 0x3C */
+  __IO uint32_t SHSR1;    /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */
+  __IO uint32_t SHSR2;    /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */
+  __IO uint32_t SHHR;     /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */
+  __IO uint32_t SHRR;     /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */
+} DAC_TypeDef;
+
+/**
+  * @brief DFSDM module registers
+  */
+typedef struct
+{
+  __IO uint32_t FLTCR1;          /*!< DFSDM control register1,                          Address offset: 0x100 */
+  __IO uint32_t FLTCR2;          /*!< DFSDM control register2,                          Address offset: 0x104 */
+  __IO uint32_t FLTISR;          /*!< DFSDM interrupt and status register,              Address offset: 0x108 */
+  __IO uint32_t FLTICR;          /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */
+  __IO uint32_t FLTJCHGR;        /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */
+  __IO uint32_t FLTFCR;          /*!< DFSDM filter control register,                    Address offset: 0x114 */
+  __IO uint32_t FLTJDATAR;       /*!< DFSDM data register for injected group,           Address offset: 0x118 */
+  __IO uint32_t FLTRDATAR;       /*!< DFSDM data register for regular group,            Address offset: 0x11C */
+  __IO uint32_t FLTAWHTR;        /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */
+  __IO uint32_t FLTAWLTR;        /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */
+  __IO uint32_t FLTAWSR;         /*!< DFSDM analog watchdog status register             Address offset: 0x128 */
+  __IO uint32_t FLTAWCFR;        /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */
+  __IO uint32_t FLTEXMAX;        /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */
+  __IO uint32_t FLTEXMIN;        /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */
+  __IO uint32_t FLTCNVTIMR;      /*!< DFSDM conversion timer,                           Address offset: 0x138 */
+} DFSDM_Filter_TypeDef;
+
+/**
+  * @brief DFSDM channel configuration registers
+  */
+typedef struct
+{
+  __IO uint32_t CHCFGR1;      /*!< DFSDM channel configuration register1,            Address offset: 0x00 */
+  __IO uint32_t CHCFGR2;      /*!< DFSDM channel configuration register2,            Address offset: 0x04 */
+  __IO uint32_t CHAWSCDR;     /*!< DFSDM channel analog watchdog and
+                                   short circuit detector register,                  Address offset: 0x08 */
+  __IO uint32_t CHWDATAR;     /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */
+  __IO uint32_t CHDATINR;     /*!< DFSDM channel data input register,                Address offset: 0x10 */
+} DFSDM_Channel_TypeDef;
+
+/**
+  * @brief Debug MCU
+  */
+typedef struct
+{
+  __IO uint32_t IDCODE;        /*!< MCU device ID code,                     Address offset: 0x00 */
+  __IO uint32_t CR;            /*!< Debug MCU configuration register,       Address offset: 0x04 */
+  uint32_t RESERVED4[11];      /*!< Reserved,                             Address offset: 0x08 */
+  __IO uint32_t APB3FZ1;     /*!< Debug MCU APB3FZ1 freeze register,    Address offset: 0x34 */
+  uint32_t RESERVED5;          /*!< Reserved,                             Address offset: 0x38 */
+  __IO uint32_t APB1LFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x3C */
+  uint32_t RESERVED6;          /*!< Reserved,                             Address offset: 0x40 */
+  __IO uint32_t APB1HFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x44 */
+  uint32_t RESERVED7;          /*!< Reserved,                             Address offset: 0x48 */
+  __IO uint32_t APB2FZ1;     /*!< Debug MCU APB2FZ1 freeze register,    Address offset: 0x4C */
+  uint32_t RESERVED8;          /*!< Reserved,                             Address offset: 0x50 */
+  __IO uint32_t APB4FZ1;     /*!< Debug MCU APB4FZ1 freeze register,    Address offset: 0x54 */
+}DBGMCU_TypeDef;
+/**
+  * @brief DCMI
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
+  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
+  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
+  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
+  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
+  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
+  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
+  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
+  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
+  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
+} DCMI_TypeDef;
+
+/**
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
+  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
+  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
+  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
+  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
+  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
+  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
+  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
+  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CCR;          /*!< DMA channel x configuration register          */
+  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register         */
+  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register     */
+  __IO uint32_t CM0AR;        /*!< DMA channel x memory 0 address register       */
+  __IO uint32_t CM1AR;        /*!< DMA channel x memory 1 address register       */
+} BDMA_Channel_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
+  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
+} BDMA_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t  CCR;        /*!< DMA Multiplexer Channel x Control Register   */
+}DMAMUX_Channel_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t  CSR;      /*!< DMA Channel Status Register     */
+  __IO uint32_t  CFR;      /*!< DMA Channel Clear Flag Register */
+}DMAMUX_ChannelStatus_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t  RGCR;        /*!< DMA Request Generator x Control Register   */
+}DMAMUX_RequestGen_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t  RGSR;        /*!< DMA Request Generator Status Register       */
+  __IO uint32_t  RGCFR;       /*!< DMA Request Generator Clear Flag Register   */
+}DMAMUX_RequestGenStatus_TypeDef;
+
+/**
+  * @brief MDMA Controller
+  */
+typedef struct
+{
+  __IO uint32_t  GISR0;   /*!< MDMA Global Interrupt/Status Register 0,          Address offset: 0x00 */
+}MDMA_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t  CISR;      /*!< MDMA channel x interrupt/status register,             Address offset: 0x40 */
+  __IO uint32_t  CIFCR;     /*!< MDMA channel x interrupt flag clear register,         Address offset: 0x44 */
+  __IO uint32_t  CESR;      /*!< MDMA Channel x error status register,                 Address offset: 0x48 */
+  __IO uint32_t  CCR;       /*!< MDMA channel x control register,                      Address offset: 0x4C */
+  __IO uint32_t  CTCR;      /*!< MDMA channel x Transfer Configuration register,       Address offset: 0x50 */
+  __IO uint32_t  CBNDTR;    /*!< MDMA Channel x block number of data register,         Address offset: 0x54 */
+  __IO uint32_t  CSAR;      /*!< MDMA channel x source address register,               Address offset: 0x58 */
+  __IO uint32_t  CDAR;      /*!< MDMA channel x destination address register,          Address offset: 0x5C */
+  __IO uint32_t  CBRUR;     /*!< MDMA channel x Block Repeat address Update register,  Address offset: 0x60 */
+  __IO uint32_t  CLAR;      /*!< MDMA channel x Link Address register,                 Address offset: 0x64 */
+  __IO uint32_t  CTBR;      /*!< MDMA channel x Trigger and Bus selection Register,    Address offset: 0x68 */
+  uint32_t       RESERVED0; /*!< Reserved, 0x68                                                             */
+  __IO uint32_t  CMAR;      /*!< MDMA channel x Mask address register,                 Address offset: 0x70 */
+  __IO uint32_t  CMDR;      /*!< MDMA channel x Mask Data register,                    Address offset: 0x74 */
+}MDMA_Channel_TypeDef;
+
+/**
+  * @brief DMA2D Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */
+  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */
+  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */
+  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */
+  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */
+  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */
+  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */
+  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */
+  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */
+  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */
+  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */
+  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */
+  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */
+  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */
+  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */
+  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */
+  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */
+  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */
+  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */
+  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */
+  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
+  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */
+  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */
+} DMA2D_TypeDef;
+
+
+/**
+  * @brief Ethernet MAC
+  */
+typedef struct
+{
+  __IO uint32_t MACCR;
+  __IO uint32_t MACECR;
+  __IO uint32_t MACPFR;
+  __IO uint32_t MACWTR;
+  __IO uint32_t MACHT0R;
+  __IO uint32_t MACHT1R;
+  uint32_t      RESERVED1[14];
+  __IO uint32_t MACVTR;
+  uint32_t      RESERVED2;
+  __IO uint32_t MACVHTR;
+  uint32_t      RESERVED3;
+  __IO uint32_t MACVIR;
+  __IO uint32_t MACIVIR;
+  uint32_t      RESERVED4[2];
+  __IO uint32_t MACTFCR;
+  uint32_t      RESERVED5[7];
+  __IO uint32_t MACRFCR;
+  uint32_t      RESERVED6[7];
+  __IO uint32_t MACISR;
+  __IO uint32_t MACIER;
+  __IO uint32_t MACRXTXSR;
+  uint32_t      RESERVED7;
+  __IO uint32_t MACPCSR;
+  __IO uint32_t MACRWKPFR;
+  uint32_t      RESERVED8[2];
+  __IO uint32_t MACLCSR;
+  __IO uint32_t MACLTCR;
+  __IO uint32_t MACLETR;
+  __IO uint32_t MAC1USTCR;
+  uint32_t      RESERVED9[12];
+  __IO uint32_t MACVR;
+  __IO uint32_t MACDR;
+  uint32_t      RESERVED10;
+  __IO uint32_t MACHWF0R;
+  __IO uint32_t MACHWF1R;
+  __IO uint32_t MACHWF2R;
+  uint32_t      RESERVED11[54];
+  __IO uint32_t MACMDIOAR;
+  __IO uint32_t MACMDIODR;
+  uint32_t      RESERVED12[2];
+  __IO uint32_t MACARPAR;
+  uint32_t      RESERVED13[59];
+  __IO uint32_t MACA0HR;
+  __IO uint32_t MACA0LR;
+  __IO uint32_t MACA1HR;
+  __IO uint32_t MACA1LR;
+  __IO uint32_t MACA2HR;
+  __IO uint32_t MACA2LR;
+  __IO uint32_t MACA3HR;
+  __IO uint32_t MACA3LR;
+  uint32_t      RESERVED14[248];
+  __IO uint32_t MMCCR;
+  __IO uint32_t MMCRIR;
+  __IO uint32_t MMCTIR;
+  __IO uint32_t MMCRIMR;
+  __IO uint32_t MMCTIMR;
+  uint32_t      RESERVED15[14];
+  __IO uint32_t MMCTSCGPR;
+  __IO uint32_t MMCTMCGPR;
+  uint32_t      RESERVED16[5];
+  __IO uint32_t MMCTPCGR;
+  uint32_t      RESERVED17[10];
+  __IO uint32_t MMCRCRCEPR;
+  __IO uint32_t MMCRAEPR;
+  uint32_t      RESERVED18[10];
+  __IO uint32_t MMCRUPGR;
+  uint32_t      RESERVED19[9];
+  __IO uint32_t MMCTLPIMSTR;
+  __IO uint32_t MMCTLPITCR;
+  __IO uint32_t MMCRLPIMSTR;
+  __IO uint32_t MMCRLPITCR;
+  uint32_t      RESERVED20[65];
+  __IO uint32_t MACL3L4C0R;
+  __IO uint32_t MACL4A0R;
+  uint32_t      RESERVED21[2];
+  __IO uint32_t MACL3A0R0R;
+  __IO uint32_t MACL3A1R0R;
+  __IO uint32_t MACL3A2R0R;
+  __IO uint32_t MACL3A3R0R;
+  uint32_t      RESERVED22[4];
+  __IO uint32_t MACL3L4C1R;
+  __IO uint32_t MACL4A1R;
+  uint32_t      RESERVED23[2];
+  __IO uint32_t MACL3A0R1R;
+  __IO uint32_t MACL3A1R1R;
+  __IO uint32_t MACL3A2R1R;
+  __IO uint32_t MACL3A3R1R;
+  uint32_t      RESERVED24[108];
+  __IO uint32_t MACTSCR;
+  __IO uint32_t MACSSIR;
+  __IO uint32_t MACSTSR;
+  __IO uint32_t MACSTNR;
+  __IO uint32_t MACSTSUR;
+  __IO uint32_t MACSTNUR;
+  __IO uint32_t MACTSAR;
+  uint32_t      RESERVED25;
+  __IO uint32_t MACTSSR;
+  uint32_t      RESERVED26[3];
+  __IO uint32_t MACTTSSNR;
+  __IO uint32_t MACTTSSSR;
+  uint32_t      RESERVED27[2];
+  __IO uint32_t MACACR;
+  uint32_t      RESERVED28;
+  __IO uint32_t MACATSNR;
+  __IO uint32_t MACATSSR;
+  __IO uint32_t MACTSIACR;
+  __IO uint32_t MACTSEACR;
+  __IO uint32_t MACTSICNR;
+  __IO uint32_t MACTSECNR;
+  uint32_t      RESERVED29[4];
+  __IO uint32_t MACPPSCR;
+  uint32_t      RESERVED30[3];
+  __IO uint32_t MACPPSTTSR;
+  __IO uint32_t MACPPSTTNR;
+  __IO uint32_t MACPPSIR;
+  __IO uint32_t MACPPSWR;
+  uint32_t      RESERVED31[12];
+  __IO uint32_t MACPOCR;
+  __IO uint32_t MACSPI0R;
+  __IO uint32_t MACSPI1R;
+  __IO uint32_t MACSPI2R;
+  __IO uint32_t MACLMIR;
+  uint32_t      RESERVED32[11];
+  __IO uint32_t MTLOMR;
+  uint32_t      RESERVED33[7];
+  __IO uint32_t MTLISR;
+  uint32_t      RESERVED34[55];
+  __IO uint32_t MTLTQOMR;
+  __IO uint32_t MTLTQUR;
+  __IO uint32_t MTLTQDR;
+  uint32_t      RESERVED35[8];
+  __IO uint32_t MTLQICSR;
+  __IO uint32_t MTLRQOMR;
+  __IO uint32_t MTLRQMPOCR;
+  __IO uint32_t MTLRQDR;
+  uint32_t      RESERVED36[177];
+  __IO uint32_t DMAMR;
+  __IO uint32_t DMASBMR;
+  __IO uint32_t DMAISR;
+  __IO uint32_t DMADSR;
+  uint32_t      RESERVED37[60];
+  __IO uint32_t DMACCR;
+  __IO uint32_t DMACTCR;
+  __IO uint32_t DMACRCR;
+  uint32_t      RESERVED38[2];
+  __IO uint32_t DMACTDLAR;
+  uint32_t      RESERVED39;
+  __IO uint32_t DMACRDLAR;
+  __IO uint32_t DMACTDTPR;
+  uint32_t      RESERVED40;
+  __IO uint32_t DMACRDTPR;
+  __IO uint32_t DMACTDRLR;
+  __IO uint32_t DMACRDRLR;
+  __IO uint32_t DMACIER;
+  __IO uint32_t DMACRIWTR;
+__IO uint32_t DMACSFCSR;
+  uint32_t      RESERVED41;
+  __IO uint32_t DMACCATDR;
+  uint32_t      RESERVED42;
+  __IO uint32_t DMACCARDR;
+  uint32_t      RESERVED43;
+  __IO uint32_t DMACCATBR;
+  uint32_t      RESERVED44;
+  __IO uint32_t DMACCARBR;
+  __IO uint32_t DMACSR;
+uint32_t      RESERVED45[2];
+__IO uint32_t DMACMFCR;
+}ETH_TypeDef;
+/**
+  * @brief External Interrupt/Event Controller
+  */
+
+typedef struct
+{
+__IO uint32_t RTSR1;               /*!< EXTI Rising trigger selection register,          Address offset: 0x00 */
+__IO uint32_t FTSR1;               /*!< EXTI Falling trigger selection register,         Address offset: 0x04 */
+__IO uint32_t SWIER1;              /*!< EXTI Software interrupt event register,          Address offset: 0x08 */
+__IO uint32_t D3PMR1;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */
+__IO uint32_t D3PCR1L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L)     Address offset: 0x10 */
+__IO uint32_t D3PCR1H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H)   Address offset: 0x14 */
+uint32_t      RESERVED1[2];        /*!< Reserved,                                        0x18 to 0x1C         */
+__IO uint32_t RTSR2;               /*!< EXTI Rising trigger selection register,          Address offset: 0x20 */
+__IO uint32_t FTSR2;               /*!< EXTI Falling trigger selection register,         Address offset: 0x24 */
+__IO uint32_t SWIER2;              /*!< EXTI Software interrupt event register,          Address offset: 0x28 */
+__IO uint32_t D3PMR2;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */
+__IO uint32_t D3PCR2L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L)  Address offset: 0x30 */
+__IO uint32_t D3PCR2H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */
+uint32_t      RESERVED2[2];        /*!< Reserved,                                        0x38 to 0x3C         */
+__IO uint32_t RTSR3;               /*!< EXTI Rising trigger selection register,          Address offset: 0x40 */
+__IO uint32_t FTSR3;               /*!< EXTI Falling trigger selection register,         Address offset: 0x44 */
+__IO uint32_t SWIER3;              /*!< EXTI Software interrupt event register,          Address offset: 0x48 */
+__IO uint32_t D3PMR3;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */
+__IO uint32_t D3PCR3L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */
+__IO uint32_t D3PCR3H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */
+uint32_t      RESERVED3[10];       /*!< Reserved,                                        0x58 to 0x7C         */
+__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                    Address offset: 0x80 */
+__IO uint32_t EMR1;                /*!< EXTI Event mask register,                        Address offset: 0x84 */
+__IO uint32_t PR1;                 /*!< EXTI Pending register,                           Address offset: 0x88 */
+uint32_t      RESERVED4;           /*!< Reserved,                                        0x8C                 */
+__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                    Address offset: 0x90 */
+__IO uint32_t EMR2;                /*!< EXTI Event mask register,                        Address offset: 0x94 */
+__IO uint32_t PR2;                 /*!< EXTI Pending register,                           Address offset: 0x98 */
+uint32_t      RESERVED5;           /*!< Reserved,                                        0x9C                 */
+__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                    Address offset: 0xA0 */
+__IO uint32_t EMR3;                /*!< EXTI Event mask register,                        Address offset: 0xA4 */
+__IO uint32_t PR3;                 /*!< EXTI Pending register,                           Address offset: 0xA8 */
+}EXTI_TypeDef;
+
+typedef struct
+{
+__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                Address offset: 0x00 */
+__IO uint32_t EMR1;                /*!< EXTI Event mask register,                    Address offset: 0x04 */
+__IO uint32_t PR1;                 /*!< EXTI Pending register,                       Address offset: 0x08 */
+uint32_t      RESERVED1;           /*!< Reserved, 0x0C                                                    */
+__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                Address offset: 0x10 */
+__IO uint32_t EMR2;                /*!< EXTI Event mask register,                    Address offset: 0x14 */
+__IO uint32_t PR2;                 /*!< EXTI Pending register,                       Address offset: 0x18 */
+uint32_t      RESERVED2;           /*!< Reserved, 0x1C                                                    */
+__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                Address offset: 0x20 */
+__IO uint32_t EMR3;                /*!< EXTI Event mask register,                    Address offset: 0x24 */
+__IO uint32_t PR3;                 /*!< EXTI Pending register,                       Address offset: 0x28 */
+}EXTI_Core_TypeDef;
+
+
+/**
+  * @brief FLASH Registers
+  */
+
+typedef struct
+{
+  __IO uint32_t ACR;             /*!< FLASH access control register,                            Address offset: 0x00  */
+  __IO uint32_t KEYR1;           /*!< Flash Key Register for bank1,                             Address offset: 0x04  */
+  __IO uint32_t OPTKEYR;         /*!< Flash Option Key Register,                                Address offset: 0x08  */
+  __IO uint32_t CR1;             /*!< Flash Control Register for bank1,                         Address offset: 0x0C  */
+  __IO uint32_t SR1;             /*!< Flash Status Register for bank1,                          Address offset: 0x10  */
+  __IO uint32_t CCR1;            /*!< Flash Control Register for bank1,                         Address offset: 0x14  */
+  __IO uint32_t OPTCR;           /*!< Flash Option Control Register,                            Address offset: 0x18  */
+  __IO uint32_t OPTSR_CUR;       /*!< Flash Option Status Current Register,                     Address offset: 0x1C  */
+  __IO uint32_t OPTSR_PRG;       /*!< Flash Option Status to Program Register,                  Address offset: 0x20  */
+  __IO uint32_t OPTCCR;          /*!< Flash Option Clear Control Register,                      Address offset: 0x24  */
+  __IO uint32_t PRAR_CUR1;       /*!< Flash Current Protection Address Register for bank1,      Address offset: 0x28  */
+  __IO uint32_t PRAR_PRG1;       /*!< Flash Protection Address to Program Register for bank1,   Address offset: 0x2C  */
+  __IO uint32_t SCAR_CUR1;       /*!< Flash Current Secure Address Register for bank1,          Address offset: 0x30  */
+  __IO uint32_t SCAR_PRG1;       /*!< Flash Secure Address to Program Register for bank1,       Address offset: 0x34  */
+  __IO uint32_t WPSN_CUR1;       /*!< Flash Current Write Protection Register on bank1,         Address offset: 0x38  */
+  __IO uint32_t WPSN_PRG1;       /*!< Flash Write Protection to Program Register on bank1,      Address offset: 0x3C  */
+  __IO uint32_t BOOT_CUR;        /*!< Flash Current Boot Address for Pelican Core Register,     Address offset: 0x40  */
+  __IO uint32_t BOOT_PRG;        /*!< Flash Boot Address to Program for Pelican Core Register,  Address offset: 0x44  */
+  uint32_t      RESERVED0[2];    /*!< Reserved, 0x48 to 0x4C                                                          */
+  __IO uint32_t CRCCR1;          /*!< Flash CRC Control register For Bank1 Register ,           Address offset: 0x50  */
+  __IO uint32_t CRCSADD1;        /*!< Flash CRC Start Address Register for Bank1 ,              Address offset: 0x54  */
+  __IO uint32_t CRCEADD1;        /*!< Flash CRC End Address Register for Bank1 ,                Address offset: 0x58  */
+  __IO uint32_t CRCDATA;         /*!< Flash CRC Data Register for Bank1 ,                       Address offset: 0x5C  */
+  __IO uint32_t ECC_FA1;         /*!< Flash ECC Fail Address For Bank1 Register ,               Address offset: 0x60  */
+  uint32_t      RESERVED1[40];   /*!< Reserved, 0x64 to 0x100                                                         */
+  __IO uint32_t KEYR2;           /*!< Flash Key Register for bank2,                             Address offset: 0x104 */
+  uint32_t      RESERVED2;       /*!< Reserved, 0x108                                                                 */
+  __IO uint32_t CR2;             /*!< Flash Control Register for bank2,                         Address offset: 0x10C */
+  __IO uint32_t SR2;             /*!< Flash Status Register for bank2,                          Address offset: 0x110 */
+  __IO uint32_t CCR2;            /*!< Flash Status Register for bank2,                          Address offset: 0x114 */
+  uint32_t      RESERVED3[4];    /*!< Reserved, 0x118 to 0x124                                                        */
+  __IO uint32_t PRAR_CUR2;       /*!< Flash Current Protection Address Register for bank2,      Address offset: 0x128 */
+  __IO uint32_t PRAR_PRG2;       /*!< Flash Protection Address to Program Register for bank2,   Address offset: 0x12C */
+  __IO uint32_t SCAR_CUR2;       /*!< Flash Current Secure Address Register for bank2,          Address offset: 0x130 */
+  __IO uint32_t SCAR_PRG2;       /*!< Flash Secure Address Register for bank2,                  Address offset: 0x134 */
+  __IO uint32_t WPSN_CUR2;       /*!< Flash Current Write Protection Register on bank2,         Address offset: 0x138 */
+  __IO uint32_t WPSN_PRG2;       /*!< Flash Write Protection to Program Register on bank2,      Address offset: 0x13C */
+  uint32_t      RESERVED4[4];    /*!< Reserved, 0x140 to 0x14C                                                        */
+  __IO uint32_t CRCCR2;          /*!< Flash CRC Control register For Bank2 Register ,           Address offset: 0x150 */
+  __IO uint32_t CRCSADD2;        /*!< Flash CRC Start Address Register for Bank2 ,              Address offset: 0x154 */
+  __IO uint32_t CRCEADD2;        /*!< Flash CRC End Address Register for Bank2 ,                Address offset: 0x158 */
+  __IO uint32_t CRCDATA2;        /*!< Flash CRC Data Register for Bank2 ,                       Address offset: 0x15C */
+  __IO uint32_t ECC_FA2;         /*!< Flash ECC Fail Address For Bank2 Register ,               Address offset: 0x160 */
+} FLASH_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FMC_Bank1_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank1E
+  */
+
+typedef struct
+{
+  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank2
+  */
+
+typedef struct
+{
+  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */
+  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */
+  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */
+  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
+  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */
+  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */
+} FMC_Bank2_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank3
+  */
+
+typedef struct
+{
+  __IO uint32_t PCR;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */
+  __IO uint32_t SR;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */
+  __IO uint32_t PMEM;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */
+  __IO uint32_t PATT;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
+  uint32_t      RESERVED;  /*!< Reserved, 0x90                                                            */
+  __IO uint32_t ECCR;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */
+} FMC_Bank3_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank5 and 6
+  */
+
+
+typedef struct
+{
+  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */
+  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */
+  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */
+  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */
+  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */
+} FMC_Bank5_6_TypeDef;
+
+/**
+  * @brief General Purpose I/O
+  */
+
+typedef struct
+{
+  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
+  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
+  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
+  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
+  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
+  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
+  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset,               Address offset: 0x18      */
+  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
+  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+  * @brief Operational Amplifier (OPAMP)
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;          /*!< OPAMP control/status register,                      Address offset: 0x00 */
+  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,     Address offset: 0x04 */
+  __IO uint32_t HSOTR;        /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */
+} OPAMP_TypeDef;
+
+/**
+  * @brief System configuration controller
+  */
+
+typedef struct
+{
+ uint32_t RESERVED1;           /*!< Reserved,                                           Address offset: 0x00        */
+ __IO uint32_t PMCR;           /*!< SYSCFG peripheral mode configuration register,      Address offset: 0x04        */
+ __IO uint32_t EXTICR[4];      /*!< SYSCFG external interrupt configuration registers,  Address offset: 0x08-0x14   */
+ __IO uint32_t CFGR;           /*!< SYSCFG configuration registers,                     Address offset: 0x18        */
+ uint32_t RESERVED2;           /*!< Reserved,                                           Address offset: 0x1C        */
+ __IO uint32_t CCCSR;          /*!< SYSCFG compensation cell control/status register,   Address offset: 0x20        */
+ __IO uint32_t CCVR;           /*!< SYSCFG compensation cell value register,            Address offset: 0x24        */
+ __IO uint32_t CCCR;           /*!< SYSCFG compensation cell code register,             Address offset: 0x28        */
+ __IO uint32_t PWRCR;          /*!< PWR control register,                               Address offset: 0x2C        */
+  uint32_t     RESERVED3[61];  /*!< Reserved, 0x30-0x120                                                            */
+  __IO uint32_t PKGR;          /*!< SYSCFG package register,                            Address offset: 0x124       */
+  uint32_t     RESERVED4[118]; /*!< Reserved, 0x128-0x2FC                                                           */
+ __IO uint32_t UR0;            /*!< SYSCFG user register 0,                             Address offset: 0x300       */
+ __IO uint32_t UR1;            /*!< SYSCFG user register 1,                             Address offset: 0x304       */
+ __IO uint32_t UR2;            /*!< SYSCFG user register 2,                             Address offset: 0x308       */
+ __IO uint32_t UR3;            /*!< SYSCFG user register 3,                             Address offset: 0x30C       */
+ __IO uint32_t UR4;            /*!< SYSCFG user register 4,                             Address offset: 0x310       */
+ __IO uint32_t UR5;            /*!< SYSCFG user register 5,                             Address offset: 0x314       */
+ __IO uint32_t UR6;            /*!< SYSCFG user register 6,                             Address offset: 0x318       */
+ __IO uint32_t UR7;            /*!< SYSCFG user register 7,                             Address offset: 0x31C       */
+ __IO uint32_t UR8;            /*!< SYSCFG user register 8,                             Address offset: 0x320       */
+ __IO uint32_t UR9;            /*!< SYSCFG user register 9,                             Address offset: 0x324       */
+ __IO uint32_t UR10;           /*!< SYSCFG user register 10,                            Address offset: 0x328       */
+ __IO uint32_t UR11;           /*!< SYSCFG user register 11,                            Address offset: 0x32C       */
+ __IO uint32_t UR12;           /*!< SYSCFG user register 12,                            Address offset: 0x330       */
+ __IO uint32_t UR13;           /*!< SYSCFG user register 13,                            Address offset: 0x334       */
+ __IO uint32_t UR14;           /*!< SYSCFG user register 14,                            Address offset: 0x338       */
+ __IO uint32_t UR15;           /*!< SYSCFG user register 15,                            Address offset: 0x33C       */
+ __IO uint32_t UR16;           /*!< SYSCFG user register 16,                            Address offset: 0x340       */
+ __IO uint32_t UR17;           /*!< SYSCFG user register 17,                            Address offset: 0x344       */
+
+} SYSCFG_TypeDef;
+
+/**
+  * @brief Inter-integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
+  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
+  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
+  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
+  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
+  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
+  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
+  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
+  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
+  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
+  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
+} I2C_TypeDef;
+
+/**
+  * @brief Independent WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
+  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
+} IWDG_TypeDef;
+
+
+/**
+  * @brief JPEG Codec
+  */
+typedef struct
+{
+  __IO uint32_t CONFR0;          /*!< JPEG Codec Control Register (JPEG_CONFR0),        Address offset: 00h       */
+  __IO uint32_t CONFR1;          /*!< JPEG Codec Control Register (JPEG_CONFR1),        Address offset: 04h       */
+  __IO uint32_t CONFR2;          /*!< JPEG Codec Control Register (JPEG_CONFR2),        Address offset: 08h       */
+  __IO uint32_t CONFR3;          /*!< JPEG Codec Control Register (JPEG_CONFR3),        Address offset: 0Ch       */
+  __IO uint32_t CONFR4;          /*!< JPEG Codec Control Register (JPEG_CONFR4),        Address offset: 10h       */
+  __IO uint32_t CONFR5;          /*!< JPEG Codec Control Register (JPEG_CONFR5),        Address offset: 14h       */
+  __IO uint32_t CONFR6;          /*!< JPEG Codec Control Register (JPEG_CONFR6),        Address offset: 18h       */
+  __IO uint32_t CONFR7;          /*!< JPEG Codec Control Register (JPEG_CONFR7),        Address offset: 1Ch       */
+  uint32_t  Reserved20[4];       /* Reserved                                            Address offset: 20h-2Ch   */
+  __IO uint32_t CR;              /*!< JPEG Control Register (JPEG_CR),                  Address offset: 30h       */
+  __IO uint32_t SR;              /*!< JPEG Status Register (JPEG_SR),                   Address offset: 34h       */
+  __IO uint32_t CFR;             /*!< JPEG Clear Flag Register (JPEG_CFR),              Address offset: 38h       */
+  uint32_t  Reserved3c;          /* Reserved                                            Address offset: 3Ch       */
+  __IO uint32_t DIR;             /*!< JPEG Data Input Register (JPEG_DIR),              Address offset: 40h       */
+  __IO uint32_t DOR;             /*!< JPEG Data Output Register (JPEG_DOR),             Address offset: 44h       */
+  uint32_t  Reserved48[2];       /* Reserved                                            Address offset: 48h-4Ch   */
+  __IO uint32_t QMEM0[16];       /*!< JPEG quantization tables 0,                       Address offset: 50h-8Ch   */
+  __IO uint32_t QMEM1[16];       /*!< JPEG quantization tables 1,                       Address offset: 90h-CCh   */
+  __IO uint32_t QMEM2[16];       /*!< JPEG quantization tables 2,                       Address offset: D0h-10Ch  */
+  __IO uint32_t QMEM3[16];       /*!< JPEG quantization tables 3,                       Address offset: 110h-14Ch */
+  __IO uint32_t HUFFMIN[16];     /*!< JPEG HuffMin tables,                              Address offset: 150h-18Ch */
+  __IO uint32_t HUFFBASE[32];    /*!< JPEG HuffSymb tables,                             Address offset: 190h-20Ch */
+  __IO uint32_t HUFFSYMB[84];    /*!< JPEG HUFFSYMB tables,                             Address offset: 210h-35Ch */
+  __IO uint32_t DHTMEM[103];     /*!< JPEG DHTMem tables,                               Address offset: 360h-4F8h */
+  uint32_t  Reserved4FC;         /* Reserved                                            Address offset: 4FCh      */
+  __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0,                 Address offset: 500h-65Ch */
+  __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1,                 Address offset: 660h-7BCh */
+  __IO uint32_t HUFFENC_DC0[8];  /*!< JPEG encodor, DC Huffman table 0,                 Address offset: 7C0h-7DCh */
+  __IO uint32_t HUFFENC_DC1[8];  /*!< JPEG encodor, DC Huffman table 1,                 Address offset: 7E0h-7FCh */
+
+} JPEG_TypeDef;
+
+/**
+  * @brief LCD-TFT Display Controller
+  */
+
+typedef struct
+{
+  uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04                                                       */
+  __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */
+  __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */
+  __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */
+  __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */
+  __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */
+  uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20                                                       */
+  __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */
+  uint32_t      RESERVED2[1];  /*!< Reserved, 0x28                                                            */
+  __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */
+  uint32_t      RESERVED3[1];  /*!< Reserved, 0x30                                                            */
+  __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */
+  __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */
+  __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */
+  __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
+  __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */
+  __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                 Address offset: 0x48 */
+} LTDC_TypeDef;
+
+/**
+  * @brief LCD-TFT Display layer x Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */
+  __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
+  __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */
+  __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */
+  __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */
+  __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */
+  __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */
+  __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */
+  uint32_t      RESERVED0[2];  /*!< Reserved */
+  __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */
+  __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */
+  __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */
+  uint32_t      RESERVED1[3];  /*!< Reserved */
+  __IO uint32_t CLUTWR;         /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */
+
+} LTDC_Layer_TypeDef;
+
+/**
+  * @brief Power Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;       /*!< PWR power control register 1,            Address offset: 0x00 */
+  __IO uint32_t CSR1;      /*!< PWR power control status register 1,     Address offset: 0x04 */
+  __IO uint32_t CR2;       /*!< PWR power control register 2,            Address offset: 0x08 */
+  __IO uint32_t CR3;       /*!< PWR power control register 3,            Address offset: 0x0C */
+  __IO uint32_t CPUCR;     /*!< PWR CPU control register,                Address offset: 0x10 */
+       uint32_t RESERVED0; /*!< Reserved,                                Address offset: 0x14 */
+  __IO uint32_t D3CR;      /*!< PWR D3 domain control register,          Address offset: 0x18 */
+       uint32_t RESERVED1; /*!< Reserved,                                Address offset: 0x1C */
+  __IO uint32_t WKUPCR;    /*!< PWR wakeup clear register,               Address offset: 0x20 */
+  __IO uint32_t WKUPFR;    /*!< PWR wakeup flag register,                Address offset: 0x24 */
+  __IO uint32_t WKUPEPR;   /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */
+} PWR_TypeDef;
+
+/**
+  * @brief Reset and Clock Control
+  */
+
+typedef struct
+{
+ __IO uint32_t CR;             /*!< RCC clock control register,                                              Address offset: 0x00  */
+ __IO uint32_t HSICFGR;        /*!< HSI Clock Calibration Register,                                          Address offset: 0x04  */
+ __IO uint32_t CRRCR;          /*!< Clock Recovery RC  Register,                                             Address offset: 0x08  */
+ __IO uint32_t CSICFGR;        /*!< CSI Clock Calibration Register,                                          Address offset: 0x0C  */
+ __IO uint32_t CFGR;           /*!< RCC clock configuration register,                                        Address offset: 0x10  */
+ uint32_t     RESERVED1;       /*!< Reserved,                                                                Address offset: 0x14  */
+ __IO uint32_t D1CFGR;         /*!< RCC Domain 1 configuration register,                                     Address offset: 0x18  */
+ __IO uint32_t D2CFGR;         /*!< RCC Domain 2 configuration register,                                     Address offset: 0x1C  */
+ __IO uint32_t D3CFGR;         /*!< RCC Domain 3 configuration register,                                     Address offset: 0x20  */
+ uint32_t     RESERVED2;       /*!< Reserved,                                                                Address offset: 0x24  */
+ __IO uint32_t PLLCKSELR;      /*!< RCC PLLs Clock Source Selection Register,                                Address offset: 0x28  */
+ __IO uint32_t PLLCFGR;        /*!< RCC PLLs  Configuration Register,                                        Address offset: 0x2C  */
+ __IO uint32_t PLL1DIVR;       /*!< RCC PLL1 Dividers Configuration Register,                                Address offset: 0x30  */
+ __IO uint32_t PLL1FRACR;      /*!< RCC PLL1 Fractional Divider Configuration Register,                      Address offset: 0x34  */
+ __IO uint32_t PLL2DIVR;       /*!< RCC PLL2 Dividers Configuration Register,                                Address offset: 0x38  */
+ __IO uint32_t PLL2FRACR;      /*!< RCC PLL2 Fractional Divider Configuration Register,                      Address offset: 0x3C  */
+ __IO uint32_t PLL3DIVR;       /*!< RCC PLL3 Dividers Configuration Register,                                Address offset: 0x40  */
+ __IO uint32_t PLL3FRACR;      /*!< RCC PLL3 Fractional Divider Configuration Register,                      Address offset: 0x44  */
+ uint32_t      RESERVED3;      /*!< Reserved,                                                                Address offset: 0x48  */
+ __IO uint32_t  D1CCIPR;       /*!< RCC Domain 1 Kernel Clock Configuration Register                         Address offset: 0x4C  */
+ __IO uint32_t  D2CCIP1R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x50  */
+ __IO uint32_t  D2CCIP2R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x54  */
+ __IO uint32_t  D3CCIPR;       /*!< RCC Domain 3 Kernel Clock Configuration Register                         Address offset: 0x58  */
+ uint32_t      RESERVED4;      /*!< Reserved,                                                                Address offset: 0x5C  */
+ __IO uint32_t  CIER;          /*!< RCC Clock Source Interrupt Enable Register                               Address offset: 0x60  */
+ __IO uint32_t  CIFR;          /*!< RCC Clock Source Interrupt Flag Register                                 Address offset: 0x64  */
+ __IO uint32_t  CICR;          /*!< RCC Clock Source Interrupt Clear Register                                Address offset: 0x68  */
+ uint32_t     RESERVED5;       /*!< Reserved,                                                                Address offset: 0x6C  */
+ __IO uint32_t  BDCR;          /*!< RCC Vswitch Backup Domain Control Register,                              Address offset: 0x70  */
+ __IO uint32_t  CSR;           /*!< RCC clock control & status register,                                     Address offset: 0x74  */
+ uint32_t     RESERVED6;       /*!< Reserved,                                                                Address offset: 0x78  */
+ __IO uint32_t AHB3RSTR;       /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x7C  */
+ __IO uint32_t AHB1RSTR;       /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x80  */
+ __IO uint32_t AHB2RSTR;       /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x84  */
+ __IO uint32_t AHB4RSTR;       /*!< RCC AHB4 peripheral reset register,                                      Address offset: 0x88  */
+ __IO uint32_t APB3RSTR;       /*!< RCC APB3 peripheral reset register,                                      Address offset: 0x8C  */
+ __IO uint32_t APB1LRSTR;      /*!< RCC APB1 peripheral reset Low Word register,                             Address offset: 0x90  */
+ __IO uint32_t APB1HRSTR;      /*!< RCC APB1 peripheral reset High Word register,                            Address offset: 0x94  */
+ __IO uint32_t APB2RSTR;       /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x98  */
+ __IO uint32_t APB4RSTR;       /*!< RCC APB4 peripheral reset register,                                      Address offset: 0x9C  */
+ __IO uint32_t GCR;            /*!< RCC RCC Global Control  Register,                                        Address offset: 0xA0  */
+ uint32_t     RESERVED8;       /*!< Reserved,                                                                Address offset: 0xA4  */
+ __IO uint32_t D3AMR;          /*!< RCC Domain 3 Autonomous Mode Register,                                   Address offset: 0xA8  */
+ uint32_t     RESERVED11[9];    /*!< Reserved, 0xAC-0xCC                                                      Address offset: 0xAC  */
+ __IO uint32_t RSR;            /*!< RCC Reset status register,                                               Address offset: 0xD0  */
+ __IO uint32_t AHB3ENR;        /*!< RCC AHB3 peripheral clock  register,                                     Address offset: 0xD4  */
+ __IO uint32_t AHB1ENR;        /*!< RCC AHB1 peripheral clock  register,                                     Address offset: 0xD8  */
+ __IO uint32_t AHB2ENR;        /*!< RCC AHB2 peripheral clock  register,                                     Address offset: 0xDC  */
+ __IO uint32_t AHB4ENR;        /*!< RCC AHB4 peripheral clock  register,                                     Address offset: 0xE0  */
+ __IO uint32_t APB3ENR;        /*!< RCC APB3 peripheral clock  register,                                     Address offset: 0xE4  */
+ __IO uint32_t APB1LENR;       /*!< RCC APB1 peripheral clock  Low Word register,                            Address offset: 0xE8  */
+ __IO uint32_t APB1HENR;       /*!< RCC APB1 peripheral clock  High Word register,                           Address offset: 0xEC  */
+ __IO uint32_t APB2ENR;        /*!< RCC APB2 peripheral clock  register,                                     Address offset: 0xF0  */
+ __IO uint32_t APB4ENR;        /*!< RCC APB4 peripheral clock  register,                                     Address offset: 0xF4  */
+ uint32_t      RESERVED12;      /*!< Reserved,                                                                Address offset: 0xF8  */
+ __IO uint32_t AHB3LPENR;      /*!< RCC AHB3 peripheral sleep clock  register,                               Address offset: 0xFC  */
+ __IO uint32_t AHB1LPENR;      /*!< RCC AHB1 peripheral sleep clock  register,                               Address offset: 0x100 */
+ __IO uint32_t AHB2LPENR;      /*!< RCC AHB2 peripheral sleep clock  register,                               Address offset: 0x104 */
+ __IO uint32_t AHB4LPENR;      /*!< RCC AHB4 peripheral sleep clock  register,                               Address offset: 0x108 */
+ __IO uint32_t APB3LPENR;      /*!< RCC APB3 peripheral sleep clock  register,                               Address offset: 0x10C */
+ __IO uint32_t APB1LLPENR;     /*!< RCC APB1 peripheral sleep clock  Low Word register,                      Address offset: 0x110 */
+ __IO uint32_t APB1HLPENR;     /*!< RCC APB1 peripheral sleep clock  High Word register,                     Address offset: 0x114 */
+ __IO uint32_t APB2LPENR;      /*!< RCC APB2 peripheral sleep clock  register,                               Address offset: 0x118 */
+ __IO uint32_t APB4LPENR;      /*!< RCC APB4 peripheral sleep clock  register,                               Address offset: 0x11C */
+ uint32_t     RESERVED13[4];   /*!< Reserved, 0x120-0x12C                                                    Address offset: 0x120 */
+
+} RCC_TypeDef;
+
+
+/**
+  * @brief Real-Time Clock
+  */
+typedef struct
+{
+  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
+  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
+  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
+  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
+  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
+  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
+       uint32_t RESERVED;   /*!< Reserved,                                                  Address offset: 0x18 */
+  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
+  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
+  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
+  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
+  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
+  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
+  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
+  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
+  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
+  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */
+  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
+  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
+  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset: 0x4C */
+  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
+  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
+  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
+  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
+  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
+  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */
+  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */
+  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */
+  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */
+  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
+  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */
+  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */
+  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */
+  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */
+  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */
+  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */
+  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */
+  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */
+  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */
+  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */
+  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */
+  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */
+  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */
+  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */
+  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */
+  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */
+  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */
+  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */
+  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */
+  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */
+  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */
+  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */
+} RTC_TypeDef;
+
+/**
+  * @brief Serial Audio Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t GCR;           /*!< SAI global configuration register, Address offset: 0x00 */
+  uint32_t      RESERVED0[16]; /*!< Reserved, 0x04 - 0x43                                   */
+  __IO uint32_t PDMCR;         /*!< SAI PDM control register,          Address offset: 0x44 */
+  __IO uint32_t PDMDLY;        /*!< SAI PDM delay register,            Address offset: 0x48 */
+} SAI_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */
+  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */
+  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */
+  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */
+  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
+  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */
+  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */
+  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+/**
+  * @brief SPDIF-RX Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t   CR;           /*!< Control register,                   Address offset: 0x00 */
+  __IO uint32_t   IMR;          /*!< Interrupt mask register,            Address offset: 0x04 */
+  __IO uint32_t   SR;           /*!< Status register,                    Address offset: 0x08 */
+  __IO uint32_t   IFCR;         /*!< Interrupt Flag Clear register,      Address offset: 0x0C */
+  __IO uint32_t   DR;           /*!< Data input register,                Address offset: 0x10 */
+  __IO uint32_t   CSR;          /*!< Channel Status register,            Address offset: 0x14 */
+  __IO uint32_t   DIR;          /*!< Debug Information register,         Address offset: 0x18 */
+  uint32_t        RESERVED2;    /*!< Reserved,  0x1A                                          */
+} SPDIFRX_TypeDef;
+
+
+/**
+  * @brief Secure digital input/output Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t POWER;          /*!< SDMMC power control register,             Address offset: 0x00  */
+  __IO uint32_t CLKCR;          /*!< SDMMC clock control register,             Address offset: 0x04  */
+  __IO uint32_t ARG;            /*!< SDMMC argument register,                  Address offset: 0x08  */
+  __IO uint32_t CMD;            /*!< SDMMC command register,                   Address offset: 0x0C  */
+  __I uint32_t  RESPCMD;        /*!< SDMMC command response register,          Address offset: 0x10  */
+  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,                Address offset: 0x14  */
+  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,                Address offset: 0x18  */
+  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,                Address offset: 0x1C  */
+  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,                Address offset: 0x20  */
+  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,                Address offset: 0x24  */
+  __IO uint32_t DLEN;           /*!< SDMMC data length register,               Address offset: 0x28  */
+  __IO uint32_t DCTRL;          /*!< SDMMC data control register,              Address offset: 0x2C  */
+  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,              Address offset: 0x30  */
+  __I uint32_t  STA;            /*!< SDMMC status register,                    Address offset: 0x34  */
+  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,           Address offset: 0x38  */
+  __IO uint32_t MASK;           /*!< SDMMC mask register,                      Address offset: 0x3C  */
+  __IO uint32_t ACKTIME;        /*!< SDMMC Acknowledgement timer register,     Address offset: 0x40  */
+  uint32_t      RESERVED0[3];   /*!< Reserved, 0x44 - 0x4C - 0x4C                                    */
+  __IO uint32_t IDMACTRL;       /*!< SDMMC DMA control register,               Address offset: 0x50  */
+  __IO uint32_t IDMABSIZE;      /*!< SDMMC DMA buffer size register,           Address offset: 0x54  */
+  __IO uint32_t IDMABASE0;      /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58  */
+  __IO uint32_t IDMABASE1;      /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C  */
+  uint32_t      RESERVED1[8];   /*!< Reserved, 0x60-0x7C                                             */
+  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,                 Address offset: 0x80  */
+  uint32_t      RESERVED2[222]; /*!< Reserved, 0x84-0x3F8                                            */
+  __IO uint32_t IPVR;           /*!< SDMMC data FIFO register,                 Address offset: 0x3FC */
+} SDMMC_TypeDef;
+
+
+/**
+  * @brief Delay Block DLYB
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< DELAY BLOCK control register,  Address offset: 0x00 */
+  __IO uint32_t CFGR;        /*!< DELAY BLOCK configuration register,  Address offset: 0x04 */
+} DLYB_TypeDef;
+
+/**
+  * @brief HW Semaphore HSEM
+  */
+
+typedef struct
+{
+  __IO uint32_t R[32];      /*!< 2-step write lock and read back registers,     Address offset: 00h-7Ch  */
+  __IO uint32_t RLR[32];    /*!< 1-step read lock registers,                    Address offset: 80h-FCh  */
+  __IO uint32_t C1IER;      /*!< HSEM Interrupt enable register ,             Address offset: 100h     */
+  __IO uint32_t C1ICR;      /*!< HSEM Interrupt clear register ,              Address offset: 104h     */
+  __IO uint32_t C1ISR;      /*!< HSEM Interrupt Status register ,             Address offset: 108h     */
+  __IO uint32_t C1MISR;     /*!< HSEM Interrupt Masked Status register ,      Address offset: 10Ch     */
+  uint32_t  Reserved[12];   /* Reserved                                       Address offset: 110h-13Ch  */
+  __IO uint32_t CR;         /*!< HSEM Semaphore clear register ,                Address offset: 140h      */
+  __IO uint32_t KEYR;       /*!< HSEM Semaphore clear key register ,            Address offset: 144h      */
+
+} HSEM_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t IER;        /*!< HSEM interrupt enable register ,                Address offset:   0h     */
+  __IO uint32_t ICR;        /*!< HSEM interrupt clear register ,                 Address offset:   4h     */
+  __IO uint32_t ISR;        /*!< HSEM interrupt status register ,                Address offset:   8h     */
+  __IO uint32_t MISR;       /*!< HSEM masked interrupt status register ,         Address offset:   Ch     */
+} HSEM_Common_TypeDef;
+
+/**
+  * @brief Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;           /*!< SPI/I2S Control register 1,                      Address offset: 0x00 */
+  __IO uint32_t CR2;           /*!< SPI Control register 2,                          Address offset: 0x04 */
+  __IO uint32_t CFG1;          /*!< SPI Configuration register 1,                    Address offset: 0x08 */
+  __IO uint32_t CFG2;          /*!< SPI Configuration register 2,                    Address offset: 0x0C */
+  __IO uint32_t IER;           /*!< SPI/I2S Interrupt Enable register,               Address offset: 0x10 */
+  __IO uint32_t SR;            /*!< SPI/I2S Status register,                         Address offset: 0x14 */
+  __IO uint32_t IFCR;          /*!< SPI/I2S Interrupt/Status flags clear register,   Address offset: 0x18 */
+  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                        */
+  __IO uint32_t TXDR;          /*!< SPI/I2S Transmit data register,                  Address offset: 0x20 */
+  uint32_t      RESERVED1[3];  /*!< Reserved, 0x24-0x2C                                                   */
+  __IO uint32_t RXDR;          /*!< SPI/I2S Receive data register,                   Address offset: 0x30 */
+  uint32_t      RESERVED2[3];  /*!< Reserved, 0x34-0x3C                                                   */
+  __IO uint32_t CRCPOLY;       /*!< SPI CRC Polynomial register,                     Address offset: 0x40 */
+  __IO uint32_t TXCRC;         /*!< SPI Transmitter CRC register,                    Address offset: 0x44 */
+  __IO uint32_t RXCRC;         /*!< SPI Receiver CRC register,                       Address offset: 0x48 */
+  __IO uint32_t UDRDR;         /*!< SPI Underrun data register,                      Address offset: 0x4C */
+  __IO uint32_t I2SCFGR;       /*!< I2S Configuration register,                      Address offset: 0x50 */
+
+} SPI_TypeDef;
+/**
+  * @brief QUAD Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< QUADSPI Control register,                           Address offset: 0x00 */
+  __IO uint32_t DCR;      /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */
+  __IO uint32_t SR;       /*!< QUADSPI Status register,                            Address offset: 0x08 */
+  __IO uint32_t FCR;      /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */
+  __IO uint32_t DLR;      /*!< QUADSPI Data Length register,                       Address offset: 0x10 */
+  __IO uint32_t CCR;      /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */
+  __IO uint32_t AR;       /*!< QUADSPI Address register,                           Address offset: 0x18 */
+  __IO uint32_t ABR;      /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */
+  __IO uint32_t DR;       /*!< QUADSPI Data register,                              Address offset: 0x20 */
+  __IO uint32_t PSMKR;    /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */
+  __IO uint32_t PSMAR;    /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */
+  __IO uint32_t PIR;      /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */
+  __IO uint32_t LPTR;     /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */
+} QUADSPI_TypeDef;
+
+/**
+  * @brief TIM
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */
+  __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */
+  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */
+  __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */
+  __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */
+  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */
+  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */
+  __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */
+  __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */
+  __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */
+  __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */
+  __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */
+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */
+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */
+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */
+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */
+  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */
+  __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */
+  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */
+  uint32_t      RESERVED1;   /*!< Reserved, 0x50                                                 */
+  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */
+  __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */
+  __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */
+  __IO uint32_t AF1;         /*!< TIM alternate function option register 1, Address offset: 0x60 */
+  __IO uint32_t AF2;         /*!< TIM alternate function option register 2, Address offset: 0x64 */
+  __IO uint32_t TISEL;       /*!< TIM Input Selection register,             Address offset: 0x68 */
+} TIM_TypeDef;
+
+/**
+  * @brief LPTIMIMER
+  */
+typedef struct
+{
+  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,         Address offset: 0x00 */
+  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,              Address offset: 0x04 */
+  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,             Address offset: 0x08 */
+  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                Address offset: 0x0C */
+  __IO uint32_t CR;       /*!< LPTIM Control register,                      Address offset: 0x10 */
+  __IO uint32_t CMP;      /*!< LPTIM Compare register,                      Address offset: 0x14 */
+  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                   Address offset: 0x18 */
+  __IO uint32_t CNT;      /*!< LPTIM Counter register,                      Address offset: 0x1C */
+  uint32_t  RESERVED1;    /*!< Reserved, 0x20                                                    */
+  __IO uint32_t CFGR2;    /*!< LPTIM Configuration register,                Address offset: 0x24 */
+} LPTIM_TypeDef;
+
+/**
+  * @brief Comparator
+  */
+typedef struct
+{
+  __IO uint32_t SR;        /*!< Comparator status register,                    Address offset: 0x00 */
+  __IO uint32_t ICFR;      /*!< Comparator interrupt clear flag register,       Address offset: 0x04 */
+  __IO uint32_t OR;        /*!< Comparator option register,                  Address offset: 0x08 */
+} COMPOPT_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CFGR;      /*!< Comparator configuration register  ,           Address offset: 0x00 */
+} COMP_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CFGR;       /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
+} COMP_Common_TypeDef;
+/**
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */
+  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */
+  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
+  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */
+  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
+  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */
+  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
+  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
+  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
+  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
+  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
+  __IO uint32_t PRESC;  /*!< USART clock Prescaler register,           Address offset: 0x2C */
+} USART_TypeDef;
+
+/**
+  * @brief Single Wire Protocol Master Interface SPWMI
+  */
+typedef struct
+{
+  __IO uint32_t CR;          /*!< SWPMI Configuration/Control register,     Address offset: 0x00 */
+  __IO uint32_t BRR;         /*!< SWPMI bitrate register,                   Address offset: 0x04 */
+    uint32_t  RESERVED1;     /*!< Reserved, 0x08                                                 */
+  __IO uint32_t ISR;         /*!< SWPMI Interrupt and Status register,      Address offset: 0x0C */
+  __IO uint32_t ICR;         /*!< SWPMI Interrupt Flag Clear register,      Address offset: 0x10 */
+  __IO uint32_t IER;         /*!< SWPMI Interrupt Enable register,          Address offset: 0x14 */
+  __IO uint32_t RFL;         /*!< SWPMI Receive Frame Length register,      Address offset: 0x18 */
+  __IO uint32_t TDR;         /*!< SWPMI Transmit data register,             Address offset: 0x1C */
+  __IO uint32_t RDR;         /*!< SWPMI Receive data register,              Address offset: 0x20 */
+  __IO uint32_t OR;          /*!< SWPMI Option register,                    Address offset: 0x24 */
+} SWPMI_TypeDef;
+
+/**
+  * @brief Window WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
+} WWDG_TypeDef;
+
+
+/**
+  * @brief RAM_ECC_Specific_Registers
+  */
+typedef struct
+{
+  __IO uint32_t CR;           /*!< RAMECC monitor configuration register          */
+  __IO uint32_t SR;           /*!< RAMECC monitor status register                 */
+  __IO uint32_t FAR;          /*!< RAMECC monitor failing address register        */
+  __IO uint32_t FDRL;         /*!< RAMECC monitor failing data low register       */
+  __IO uint32_t FDRH;         /*!< RAMECC monitor failing data high register      */
+  __IO uint32_t FECR;         /*!< RAMECC monitor failing ECC error code register */
+} RAMECC_MonitorTypeDef;
+
+typedef struct
+{
+  __IO uint32_t IER;          /*!< RAMECC interrupt enable register */
+} RAMECC_TypeDef;
+/**
+  * @}
+  */
+
+
+
+/**
+  * @brief High resolution Timer (HRTIM)
+  */
+/* HRTIM master registers definition */
+typedef struct
+{
+  __IO uint32_t MCR;            /*!< HRTIM Master Timer control register,                     Address offset: 0x00 */
+  __IO uint32_t MISR;           /*!< HRTIM Master Timer interrupt status register,            Address offset: 0x04 */
+  __IO uint32_t MICR;           /*!< HRTIM Master Timer interupt clear register,              Address offset: 0x08 */
+  __IO uint32_t MDIER;          /*!< HRTIM Master Timer DMA/interrupt enable register         Address offset: 0x0C */
+  __IO uint32_t MCNTR;          /*!< HRTIM Master Timer counter register,                     Address offset: 0x10 */
+  __IO uint32_t MPER;           /*!< HRTIM Master Timer period register,                      Address offset: 0x14 */
+  __IO uint32_t MREP;           /*!< HRTIM Master Timer repetition register,                  Address offset: 0x18 */
+  __IO uint32_t MCMP1R;         /*!< HRTIM Master Timer compare 1 register,                   Address offset: 0x1C */
+  uint32_t      RESERVED0;     /*!< Reserved,                                                                 0x20 */
+  __IO uint32_t MCMP2R;         /*!< HRTIM Master Timer compare 2 register,                   Address offset: 0x24 */
+  __IO uint32_t MCMP3R;         /*!< HRTIM Master Timer compare 3 register,                   Address offset: 0x28 */
+  __IO uint32_t MCMP4R;         /*!< HRTIM Master Timer compare 4 register,                   Address offset: 0x2C */
+  uint32_t      RESERVED1[20];  /*!< Reserved,                                                          0x30..0x7C */
+}HRTIM_Master_TypeDef;
+
+/* HRTIM Timer A to E registers definition */
+typedef struct
+{
+  __IO uint32_t TIMxCR;     /*!< HRTIM Timerx control register,                              Address offset: 0x00 */
+  __IO uint32_t TIMxISR;    /*!< HRTIM Timerx interrupt status register,                     Address offset: 0x04 */
+  __IO uint32_t TIMxICR;    /*!< HRTIM Timerx interrupt clear register,                      Address offset: 0x08 */
+  __IO uint32_t TIMxDIER;   /*!< HRTIM Timerx DMA/interrupt enable register,                 Address offset: 0x0C */
+  __IO uint32_t CNTxR;      /*!< HRTIM Timerx counter register,                              Address offset: 0x10 */
+  __IO uint32_t PERxR;      /*!< HRTIM Timerx period register,                               Address offset: 0x14 */
+  __IO uint32_t REPxR;      /*!< HRTIM Timerx repetition register,                           Address offset: 0x18 */
+  __IO uint32_t CMP1xR;     /*!< HRTIM Timerx compare 1 register,                            Address offset: 0x1C */
+  __IO uint32_t CMP1CxR;    /*!< HRTIM Timerx compare 1 compound register,                   Address offset: 0x20 */
+  __IO uint32_t CMP2xR;     /*!< HRTIM Timerx compare 2 register,                            Address offset: 0x24 */
+  __IO uint32_t CMP3xR;     /*!< HRTIM Timerx compare 3 register,                            Address offset: 0x28 */
+  __IO uint32_t CMP4xR;     /*!< HRTIM Timerx compare 4 register,                            Address offset: 0x2C */
+  __IO uint32_t CPT1xR;     /*!< HRTIM Timerx capture 1 register,                            Address offset: 0x30 */
+  __IO uint32_t CPT2xR;     /*!< HRTIM Timerx capture 2 register,                            Address offset: 0x34 */
+  __IO uint32_t DTxR;       /*!< HRTIM Timerx dead time register,                            Address offset: 0x38 */
+  __IO uint32_t SETx1R;     /*!< HRTIM Timerx output 1 set register,                         Address offset: 0x3C */
+  __IO uint32_t RSTx1R;     /*!< HRTIM Timerx output 1 reset register,                       Address offset: 0x40 */
+  __IO uint32_t SETx2R;     /*!< HRTIM Timerx output 2 set register,                         Address offset: 0x44 */
+  __IO uint32_t RSTx2R;     /*!< HRTIM Timerx output 2 reset register,                       Address offset: 0x48 */
+  __IO uint32_t EEFxR1;     /*!< HRTIM Timerx external event filtering 1 register,           Address offset: 0x4C */
+  __IO uint32_t EEFxR2;     /*!< HRTIM Timerx external event filtering 2 register,           Address offset: 0x50 */
+  __IO uint32_t RSTxR;      /*!< HRTIM Timerx Reset register,                                Address offset: 0x54 */
+  __IO uint32_t CHPxR;      /*!< HRTIM Timerx Chopper register,                              Address offset: 0x58 */
+  __IO uint32_t CPT1xCR;    /*!< HRTIM Timerx Capture 1 register,                            Address offset: 0x5C */
+  __IO uint32_t CPT2xCR;    /*!< HRTIM Timerx Capture 2 register,                            Address offset: 0x60 */
+  __IO uint32_t OUTxR;      /*!< HRTIM Timerx Output register,                               Address offset: 0x64 */
+  __IO uint32_t FLTxR;      /*!< HRTIM Timerx Fault register,                                Address offset: 0x68 */
+  uint32_t      RESERVED0[5];  /*!< Reserved,                                                          0x6C..0x7C */
+}HRTIM_Timerx_TypeDef;
+
+/* HRTIM common register definition */
+typedef struct
+{
+  __IO uint32_t CR1;        /*!< HRTIM control register1,                                    Address offset: 0x00 */
+  __IO uint32_t CR2;        /*!< HRTIM control register2,                                    Address offset: 0x04 */
+  __IO uint32_t ISR;        /*!< HRTIM interrupt status register,                            Address offset: 0x08 */
+  __IO uint32_t ICR;        /*!< HRTIM interrupt clear register,                             Address offset: 0x0C */
+  __IO uint32_t IER;        /*!< HRTIM interrupt enable register,                            Address offset: 0x10 */
+  __IO uint32_t OENR;       /*!< HRTIM Output enable register,                               Address offset: 0x14 */
+  __IO uint32_t ODISR;      /*!< HRTIM Output disable register,                              Address offset: 0x18 */
+  __IO uint32_t ODSR;       /*!< HRTIM Output disable status register,                       Address offset: 0x1C */
+  __IO uint32_t BMCR;       /*!< HRTIM Burst mode control register,                          Address offset: 0x20 */
+  __IO uint32_t BMTRGR;     /*!< HRTIM Busrt mode trigger register,                          Address offset: 0x24 */
+  __IO uint32_t BMCMPR;     /*!< HRTIM Burst mode compare register,                          Address offset: 0x28 */
+  __IO uint32_t BMPER;      /*!< HRTIM Burst mode period register,                           Address offset: 0x2C */
+  __IO uint32_t EECR1;      /*!< HRTIM Timer external event control register1,               Address offset: 0x30 */
+  __IO uint32_t EECR2;      /*!< HRTIM Timer external event control register2,               Address offset: 0x34 */
+  __IO uint32_t EECR3;      /*!< HRTIM Timer external event control register3,               Address offset: 0x38 */
+  __IO uint32_t ADC1R;      /*!< HRTIM ADC Trigger 1 register,                               Address offset: 0x3C */
+  __IO uint32_t ADC2R;      /*!< HRTIM ADC Trigger 2 register,                               Address offset: 0x40 */
+  __IO uint32_t ADC3R;      /*!< HRTIM ADC Trigger 3 register,                               Address offset: 0x44 */
+  __IO uint32_t ADC4R;      /*!< HRTIM ADC Trigger 4 register,                               Address offset: 0x48 */
+  __IO uint32_t RESERVED0;  /*!< Reserved,                                                   Address offset: 0x4C */
+  __IO uint32_t FLTINR1;    /*!< HRTIM Fault input register1,                                Address offset: 0x50 */
+  __IO uint32_t FLTINR2;    /*!< HRTIM Fault input register2,                                Address offset: 0x54 */
+  __IO uint32_t BDMUPR;     /*!< HRTIM Burst DMA Master Timer update register,               Address offset: 0x58 */
+  __IO uint32_t BDTAUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x5C */
+  __IO uint32_t BDTBUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x60 */
+  __IO uint32_t BDTCUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x64 */
+  __IO uint32_t BDTDUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x68 */
+  __IO uint32_t BDTEUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x6C */
+  __IO uint32_t BDMADR;     /*!< HRTIM Burst DMA Master Data register,                       Address offset: 0x70 */
+}HRTIM_Common_TypeDef;
+
+/* HRTIM  register definition */
+typedef struct {
+  HRTIM_Master_TypeDef sMasterRegs;
+  HRTIM_Timerx_TypeDef sTimerxRegs[5];
+  uint32_t             RESERVED0[32];
+  HRTIM_Common_TypeDef sCommonRegs;
+}HRTIM_TypeDef;
+/**
+  * @brief RNG
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
+} RNG_TypeDef;
+
+/**
+  * @brief MDIOS
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;
+  __IO uint32_t WRFR;
+  __IO uint32_t CWRFR;
+  __IO uint32_t RDFR;
+  __IO uint32_t CRDFR;
+  __IO uint32_t SR;
+  __IO uint32_t CLRFR;
+  uint32_t RESERVED[57];
+  __IO uint32_t DINR0;
+  __IO uint32_t DINR1;
+  __IO uint32_t DINR2;
+  __IO uint32_t DINR3;
+  __IO uint32_t DINR4;
+  __IO uint32_t DINR5;
+  __IO uint32_t DINR6;
+  __IO uint32_t DINR7;
+  __IO uint32_t DINR8;
+  __IO uint32_t DINR9;
+  __IO uint32_t DINR10;
+  __IO uint32_t DINR11;
+  __IO uint32_t DINR12;
+  __IO uint32_t DINR13;
+  __IO uint32_t DINR14;
+  __IO uint32_t DINR15;
+  __IO uint32_t DINR16;
+  __IO uint32_t DINR17;
+  __IO uint32_t DINR18;
+  __IO uint32_t DINR19;
+  __IO uint32_t DINR20;
+  __IO uint32_t DINR21;
+  __IO uint32_t DINR22;
+  __IO uint32_t DINR23;
+  __IO uint32_t DINR24;
+  __IO uint32_t DINR25;
+  __IO uint32_t DINR26;
+  __IO uint32_t DINR27;
+  __IO uint32_t DINR28;
+  __IO uint32_t DINR29;
+  __IO uint32_t DINR30;
+  __IO uint32_t DINR31;
+  __IO uint32_t DOUTR0;
+  __IO uint32_t DOUTR1;
+  __IO uint32_t DOUTR2;
+  __IO uint32_t DOUTR3;
+  __IO uint32_t DOUTR4;
+  __IO uint32_t DOUTR5;
+  __IO uint32_t DOUTR6;
+  __IO uint32_t DOUTR7;
+  __IO uint32_t DOUTR8;
+  __IO uint32_t DOUTR9;
+  __IO uint32_t DOUTR10;
+  __IO uint32_t DOUTR11;
+  __IO uint32_t DOUTR12;
+  __IO uint32_t DOUTR13;
+  __IO uint32_t DOUTR14;
+  __IO uint32_t DOUTR15;
+  __IO uint32_t DOUTR16;
+  __IO uint32_t DOUTR17;
+  __IO uint32_t DOUTR18;
+  __IO uint32_t DOUTR19;
+  __IO uint32_t DOUTR20;
+  __IO uint32_t DOUTR21;
+  __IO uint32_t DOUTR22;
+  __IO uint32_t DOUTR23;
+  __IO uint32_t DOUTR24;
+  __IO uint32_t DOUTR25;
+  __IO uint32_t DOUTR26;
+  __IO uint32_t DOUTR27;
+  __IO uint32_t DOUTR28;
+  __IO uint32_t DOUTR29;
+  __IO uint32_t DOUTR30;
+  __IO uint32_t DOUTR31;
+} MDIOS_TypeDef;
+
+
+/**
+  * @brief USB_OTG_Core_Registers
+  */
+typedef struct
+{
+ __IO uint32_t GOTGCTL;               /*!< USB_OTG Control and Status Register          000h */
+  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */
+  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */
+  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */
+  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */
+  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */
+  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */
+  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */
+  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */
+  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */
+  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */
+  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */
+  uint32_t Reserved30[2];             /*!< Reserved                                     030h */
+  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */
+  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */
+  __IO uint32_t GSNPSID;              /* USB_OTG core ID                                040h*/
+  __IO uint32_t GHWCFG1;              /* User HW config1                                044h*/
+  __IO uint32_t GHWCFG2;              /* User HW config2                                048h*/
+  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */
+  uint32_t  Reserved6;                /*!< Reserved                                     050h */
+  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */
+  __IO uint32_t GPWRDN;               /*!< Power Down Register                          058h */
+  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */
+   __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register       60Ch */
+    uint32_t  Reserved43[39];         /*!< Reserved                                058h-0FFh */
+  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */
+  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */
+} USB_OTG_GlobalTypeDef;
+
+
+/**
+  * @brief USB_OTG_device_Registers
+  */
+typedef struct
+{
+  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */
+  __IO uint32_t DCTL;            /*!< dev Control Register         804h */
+  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */
+  uint32_t Reserved0C;           /*!< Reserved                     80Ch */
+  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */
+  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */
+  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */
+  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */
+  uint32_t  Reserved20;          /*!< Reserved                     820h */
+  uint32_t Reserved9;            /*!< Reserved                     824h */
+  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */
+  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */
+  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */
+  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */
+  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */
+  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */
+  uint32_t Reserved40;           /*!< dedicated EP mask            840h */
+  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */
+  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */
+  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */
+} USB_OTG_DeviceTypeDef;
+
+
+/**
+  * @brief USB_OTG_IN_Endpoint-Specific_Register
+  */
+typedef struct
+{
+  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */
+  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */
+  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */
+  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */
+  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */
+  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */
+  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+
+/**
+  * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+  */
+typedef struct
+{
+  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */
+  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */
+  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */
+  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */
+  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */
+  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */
+  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
+} USB_OTG_OUTEndpointTypeDef;
+
+
+/**
+  * @brief USB_OTG_Host_Mode_Register_Structures
+  */
+typedef struct
+{
+  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */
+  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */
+  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */
+  uint32_t Reserved40C;           /*!< Reserved                             40Ch */
+  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */
+  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */
+  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */
+} USB_OTG_HostTypeDef;
+
+/**
+  * @brief USB_OTG_Host_Channel_Specific_Registers
+  */
+typedef struct
+{
+  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */
+  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */
+  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */
+  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */
+  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */
+  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */
+  uint32_t Reserved[2];           /*!< Reserved                                      */
+} USB_OTG_HostChannelTypeDef;
+/**
+  * @}
+  */
+
+
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+#define D1_ITCMRAM_BASE           (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM  */
+#define D1_ITCMICP_BASE           (0x00100000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM         */
+#define D1_DTCMRAM_BASE           (0x20000000UL) /*!< Base address of : 128KB system data RAM accessible over DTCM                            */
+#define D1_AXIFLASH_BASE          (0x08000000UL) /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI                */
+#define D1_AXIICP_BASE            (0x1FF00000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI          */
+#define D1_AXISRAM_BASE           (0x24000000UL) /*!< Base address of : (up to 512KB) system data RAM accessible over over AXI                */
+
+#define D2_AXISRAM_BASE           (0x10000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI                */
+#define D2_AHBSRAM_BASE           (0x30000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI->AHB Bridge    */
+
+#define D3_BKPSRAM_BASE           (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge                                */
+#define D3_SRAM_BASE              (0x38000000UL) /*!< Base address of : Backup SRAM(64 KB) over AXI->AHB Bridge                               */
+
+#define PERIPH_BASE               (0x40000000UL) /*!< Base address of : AHB/APB Peripherals                                                   */
+#define QSPI_BASE                 (0x90000000UL) /*!< Base address of : QSPI memories  accessible over AXI                                    */
+
+#define FLASH_BANK1_BASE          (0x08000000UL) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI                          */
+#define FLASH_BANK2_BASE          (0x08100000UL) /*!< Base address of : (up to 1 MB) Flash Bank2 accessible over AXI                          */
+#define FLASH_END                 (0x081FFFFFUL) /*!< FLASH end address                                                                       */
+
+/* Legacy define */
+#define FLASH_BASE                FLASH_BANK1_BASE
+
+/*!< Device electronic signature memory map */
+#define UID_BASE                  (0x1FF1E800UL)            /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE            (0x1FF1E880UL)            /*!< FLASH Size register base address */
+
+
+/*!< Peripheral memory map */
+#define D2_APB1PERIPH_BASE        PERIPH_BASE
+#define D2_APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
+#define D2_AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
+#define D2_AHB2PERIPH_BASE       (PERIPH_BASE + 0x08020000UL)
+
+#define D1_APB1PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)
+#define D1_AHB1PERIPH_BASE       (PERIPH_BASE + 0x12000000UL)
+
+#define D3_APB1PERIPH_BASE       (PERIPH_BASE + 0x18000000UL)
+#define D3_AHB1PERIPH_BASE       (PERIPH_BASE + 0x18020000UL)
+
+/*!< Legacy Peripheral memory map */
+#define APB1PERIPH_BASE        PERIPH_BASE
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000UL)
+
+
+/*!< D1_AHB1PERIPH peripherals */
+
+#define MDMA_BASE             (D1_AHB1PERIPH_BASE + 0x0000UL)
+#define DMA2D_BASE            (D1_AHB1PERIPH_BASE + 0x1000UL)
+#define JPGDEC_BASE           (D1_AHB1PERIPH_BASE + 0x3000UL)
+#define FLASH_R_BASE          (D1_AHB1PERIPH_BASE + 0x2000UL)
+#define FMC_R_BASE            (D1_AHB1PERIPH_BASE + 0x4000UL)
+#define QSPI_R_BASE           (D1_AHB1PERIPH_BASE + 0x5000UL)
+#define DLYB_QSPI_BASE        (D1_AHB1PERIPH_BASE + 0x6000UL)
+#define SDMMC1_BASE           (D1_AHB1PERIPH_BASE + 0x7000UL)
+#define DLYB_SDMMC1_BASE      (D1_AHB1PERIPH_BASE + 0x8000UL)
+#define RAMECC1_BASE          (D1_AHB1PERIPH_BASE + 0x9000UL)
+
+/*!< D2_AHB1PERIPH peripherals */
+
+#define DMA1_BASE               (D2_AHB1PERIPH_BASE + 0x0000UL)
+#define DMA2_BASE               (D2_AHB1PERIPH_BASE + 0x0400UL)
+#define DMAMUX1_BASE            (D2_AHB1PERIPH_BASE + 0x0800UL)
+#define ADC1_BASE               (D2_AHB1PERIPH_BASE + 0x2000UL)
+#define ADC2_BASE               (D2_AHB1PERIPH_BASE + 0x2100UL)
+#define ADC12_COMMON_BASE       (D2_AHB1PERIPH_BASE + 0x2300UL)
+#define ETH_BASE                (D2_AHB1PERIPH_BASE + 0x8000UL)
+#define ETH_MAC_BASE            (ETH_BASE)
+
+/*!< USB registers base address */
+#define USB1_OTG_HS_PERIPH_BASE              (0x40040000UL)
+#define USB2_OTG_FS_PERIPH_BASE              (0x40080000UL)
+#define USB_OTG_GLOBAL_BASE                  (0x000UL)
+#define USB_OTG_DEVICE_BASE                  (0x800UL)
+#define USB_OTG_IN_ENDPOINT_BASE             (0x900UL)
+#define USB_OTG_OUT_ENDPOINT_BASE            (0xB00UL)
+#define USB_OTG_EP_REG_SIZE                  (0x20UL)
+#define USB_OTG_HOST_BASE                    (0x400UL)
+#define USB_OTG_HOST_PORT_BASE               (0x440UL)
+#define USB_OTG_HOST_CHANNEL_BASE            (0x500UL)
+#define USB_OTG_HOST_CHANNEL_SIZE            (0x20UL)
+#define USB_OTG_PCGCCTL_BASE                 (0xE00UL)
+#define USB_OTG_FIFO_BASE                    (0x1000UL)
+#define USB_OTG_FIFO_SIZE                    (0x1000UL)
+
+/*!< D2_AHB2PERIPH peripherals */
+
+#define DCMI_BASE              (D2_AHB2PERIPH_BASE + 0x0000UL)
+#define RNG_BASE               (D2_AHB2PERIPH_BASE + 0x1800UL)
+#define SDMMC2_BASE            (D2_AHB2PERIPH_BASE + 0x2400UL)
+#define DLYB_SDMMC2_BASE       (D2_AHB2PERIPH_BASE + 0x2800UL)
+#define RAMECC2_BASE           (D2_AHB2PERIPH_BASE + 0x3000UL)
+
+/*!< D3_AHB1PERIPH peripherals */
+#define GPIOA_BASE            (D3_AHB1PERIPH_BASE + 0x0000UL)
+#define GPIOB_BASE            (D3_AHB1PERIPH_BASE + 0x0400UL)
+#define GPIOC_BASE            (D3_AHB1PERIPH_BASE + 0x0800UL)
+#define GPIOD_BASE            (D3_AHB1PERIPH_BASE + 0x0C00UL)
+#define GPIOE_BASE            (D3_AHB1PERIPH_BASE + 0x1000UL)
+#define GPIOF_BASE            (D3_AHB1PERIPH_BASE + 0x1400UL)
+#define GPIOG_BASE            (D3_AHB1PERIPH_BASE + 0x1800UL)
+#define GPIOH_BASE            (D3_AHB1PERIPH_BASE + 0x1C00UL)
+#define GPIOI_BASE            (D3_AHB1PERIPH_BASE + 0x2000UL)
+#define GPIOJ_BASE            (D3_AHB1PERIPH_BASE + 0x2400UL)
+#define GPIOK_BASE            (D3_AHB1PERIPH_BASE + 0x2800UL)
+#define RCC_BASE              (D3_AHB1PERIPH_BASE + 0x4400UL)
+#define PWR_BASE              (D3_AHB1PERIPH_BASE + 0x4800UL)
+#define CRC_BASE              (D3_AHB1PERIPH_BASE + 0x4C00UL)
+#define BDMA_BASE             (D3_AHB1PERIPH_BASE + 0x5400UL)
+#define DMAMUX2_BASE          (D3_AHB1PERIPH_BASE + 0x5800UL)
+#define ADC3_BASE             (D3_AHB1PERIPH_BASE + 0x6000UL)
+#define ADC3_COMMON_BASE      (D3_AHB1PERIPH_BASE + 0x6300UL)
+#define HSEM_BASE             (D3_AHB1PERIPH_BASE + 0x6400UL)
+#define RAMECC3_BASE          (D3_AHB1PERIPH_BASE + 0x7000UL)
+
+/*!< D1_APB1PERIPH peripherals */
+#define LTDC_BASE             (D1_APB1PERIPH_BASE + 0x1000UL)
+#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84UL)
+#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104UL)
+#define WWDG1_BASE            (D1_APB1PERIPH_BASE + 0x3000UL)
+
+/*!< D2_APB1PERIPH peripherals */
+#define TIM2_BASE             (D2_APB1PERIPH_BASE + 0x0000UL)
+#define TIM3_BASE             (D2_APB1PERIPH_BASE + 0x0400UL)
+#define TIM4_BASE             (D2_APB1PERIPH_BASE + 0x0800UL)
+#define TIM5_BASE             (D2_APB1PERIPH_BASE + 0x0C00UL)
+#define TIM6_BASE             (D2_APB1PERIPH_BASE + 0x1000UL)
+#define TIM7_BASE             (D2_APB1PERIPH_BASE + 0x1400UL)
+#define TIM12_BASE            (D2_APB1PERIPH_BASE + 0x1800UL)
+#define TIM13_BASE            (D2_APB1PERIPH_BASE + 0x1C00UL)
+#define TIM14_BASE            (D2_APB1PERIPH_BASE + 0x2000UL)
+#define LPTIM1_BASE           (D2_APB1PERIPH_BASE + 0x2400UL)
+
+
+#define SPI2_BASE             (D2_APB1PERIPH_BASE + 0x3800UL)
+#define SPI3_BASE             (D2_APB1PERIPH_BASE + 0x3C00UL)
+#define SPDIFRX_BASE          (D2_APB1PERIPH_BASE + 0x4000UL)
+#define USART2_BASE           (D2_APB1PERIPH_BASE + 0x4400UL)
+#define USART3_BASE           (D2_APB1PERIPH_BASE + 0x4800UL)
+#define UART4_BASE            (D2_APB1PERIPH_BASE + 0x4C00UL)
+#define UART5_BASE            (D2_APB1PERIPH_BASE + 0x5000UL)
+#define I2C1_BASE             (D2_APB1PERIPH_BASE + 0x5400UL)
+#define I2C2_BASE             (D2_APB1PERIPH_BASE + 0x5800UL)
+#define I2C3_BASE             (D2_APB1PERIPH_BASE + 0x5C00UL)
+#define CEC_BASE              (D2_APB1PERIPH_BASE + 0x6C00UL)
+#define DAC1_BASE             (D2_APB1PERIPH_BASE + 0x7400UL)
+#define UART7_BASE            (D2_APB1PERIPH_BASE + 0x7800UL)
+#define UART8_BASE            (D2_APB1PERIPH_BASE + 0x7C00UL)
+#define CRS_BASE              (D2_APB1PERIPH_BASE + 0x8400UL)
+#define SWPMI1_BASE           (D2_APB1PERIPH_BASE + 0x8800UL)
+#define OPAMP_BASE            (D2_APB1PERIPH_BASE + 0x9000UL)
+#define OPAMP1_BASE           (D2_APB1PERIPH_BASE + 0x9000UL)
+#define OPAMP2_BASE           (D2_APB1PERIPH_BASE + 0x9010UL)
+#define MDIOS_BASE            (D2_APB1PERIPH_BASE + 0x9400UL)
+#define FDCAN1_BASE           (D2_APB1PERIPH_BASE + 0xA000UL)
+#define FDCAN2_BASE           (D2_APB1PERIPH_BASE + 0xA400UL)
+#define FDCAN_CCU_BASE        (D2_APB1PERIPH_BASE + 0xA800UL)
+#define SRAMCAN_BASE          (D2_APB1PERIPH_BASE + 0xAC00UL)
+
+/*!< D2_APB2PERIPH peripherals */
+
+#define TIM1_BASE             (D2_APB2PERIPH_BASE + 0x0000UL)
+#define TIM8_BASE             (D2_APB2PERIPH_BASE + 0x0400UL)
+#define USART1_BASE           (D2_APB2PERIPH_BASE + 0x1000UL)
+#define USART6_BASE           (D2_APB2PERIPH_BASE + 0x1400UL)
+#define SPI1_BASE             (D2_APB2PERIPH_BASE + 0x3000UL)
+#define SPI4_BASE             (D2_APB2PERIPH_BASE + 0x3400UL)
+#define TIM15_BASE            (D2_APB2PERIPH_BASE + 0x4000UL)
+#define TIM16_BASE            (D2_APB2PERIPH_BASE + 0x4400UL)
+#define TIM17_BASE            (D2_APB2PERIPH_BASE + 0x4800UL)
+#define SPI5_BASE             (D2_APB2PERIPH_BASE + 0x5000UL)
+#define SAI1_BASE             (D2_APB2PERIPH_BASE + 0x5800UL)
+#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004UL)
+#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024UL)
+#define SAI2_BASE             (D2_APB2PERIPH_BASE + 0x5C00UL)
+#define SAI2_Block_A_BASE     (SAI2_BASE + 0x004UL)
+#define SAI2_Block_B_BASE     (SAI2_BASE + 0x024UL)
+#define SAI3_BASE             (D2_APB2PERIPH_BASE + 0x6000UL)
+#define SAI3_Block_A_BASE     (SAI3_BASE + 0x004UL)
+#define SAI3_Block_B_BASE     (SAI3_BASE + 0x024UL)
+#define DFSDM1_BASE           (D2_APB2PERIPH_BASE + 0x7000UL)
+#define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x00UL)
+#define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x20UL)
+#define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x40UL)
+#define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x60UL)
+#define DFSDM1_Channel4_BASE  (DFSDM1_BASE + 0x80UL)
+#define DFSDM1_Channel5_BASE  (DFSDM1_BASE + 0xA0UL)
+#define DFSDM1_Channel6_BASE  (DFSDM1_BASE + 0xC0UL)
+#define DFSDM1_Channel7_BASE  (DFSDM1_BASE + 0xE0UL)
+#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100UL)
+#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180UL)
+#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200UL)
+#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280UL)
+#define HRTIM1_BASE           (D2_APB2PERIPH_BASE + 0x7400UL)
+#define HRTIM1_TIMA_BASE      (HRTIM1_BASE + 0x00000080UL)
+#define HRTIM1_TIMB_BASE      (HRTIM1_BASE + 0x00000100UL)
+#define HRTIM1_TIMC_BASE      (HRTIM1_BASE + 0x00000180UL)
+#define HRTIM1_TIMD_BASE      (HRTIM1_BASE + 0x00000200UL)
+#define HRTIM1_TIME_BASE      (HRTIM1_BASE + 0x00000280UL)
+#define HRTIM1_COMMON_BASE    (HRTIM1_BASE + 0x00000380UL)
+
+
+/*!< D3_APB1PERIPH peripherals */
+#define EXTI_BASE             (D3_APB1PERIPH_BASE + 0x0000UL)
+#define EXTI_D1_BASE          (EXTI_BASE + 0x0080UL)
+#define EXTI_D2_BASE          (EXTI_BASE + 0x00C0UL)
+#define SYSCFG_BASE           (D3_APB1PERIPH_BASE + 0x0400UL)
+#define LPUART1_BASE          (D3_APB1PERIPH_BASE + 0x0C00UL)
+#define SPI6_BASE             (D3_APB1PERIPH_BASE + 0x1400UL)
+#define I2C4_BASE             (D3_APB1PERIPH_BASE + 0x1C00UL)
+#define LPTIM2_BASE           (D3_APB1PERIPH_BASE + 0x2400UL)
+#define LPTIM3_BASE           (D3_APB1PERIPH_BASE + 0x2800UL)
+#define LPTIM4_BASE           (D3_APB1PERIPH_BASE + 0x2C00UL)
+#define LPTIM5_BASE           (D3_APB1PERIPH_BASE + 0x3000UL)
+#define COMP12_BASE           (D3_APB1PERIPH_BASE + 0x3800UL)
+#define COMP1_BASE            (COMP12_BASE + 0x0CUL)
+#define COMP2_BASE            (COMP12_BASE + 0x10UL)
+#define VREFBUF_BASE          (D3_APB1PERIPH_BASE + 0x3C00UL)
+#define RTC_BASE              (D3_APB1PERIPH_BASE + 0x4000UL)
+#define IWDG1_BASE            (D3_APB1PERIPH_BASE + 0x4800UL)
+
+
+#define SAI4_BASE             (D3_APB1PERIPH_BASE + 0x5400UL)
+#define SAI4_Block_A_BASE     (SAI4_BASE + 0x004UL)
+#define SAI4_Block_B_BASE     (SAI4_BASE + 0x024UL)
+
+
+
+
+#define BDMA_Channel0_BASE    (BDMA_BASE + 0x0008UL)
+#define BDMA_Channel1_BASE    (BDMA_BASE + 0x001CUL)
+#define BDMA_Channel2_BASE    (BDMA_BASE + 0x0030UL)
+#define BDMA_Channel3_BASE    (BDMA_BASE + 0x0044UL)
+#define BDMA_Channel4_BASE    (BDMA_BASE + 0x0058UL)
+#define BDMA_Channel5_BASE    (BDMA_BASE + 0x006CUL)
+#define BDMA_Channel6_BASE    (BDMA_BASE + 0x0080UL)
+#define BDMA_Channel7_BASE    (BDMA_BASE + 0x0094UL)
+
+#define DMAMUX2_Channel0_BASE    (DMAMUX2_BASE)
+#define DMAMUX2_Channel1_BASE    (DMAMUX2_BASE + 0x0004UL)
+#define DMAMUX2_Channel2_BASE    (DMAMUX2_BASE + 0x0008UL)
+#define DMAMUX2_Channel3_BASE    (DMAMUX2_BASE + 0x000CUL)
+#define DMAMUX2_Channel4_BASE    (DMAMUX2_BASE + 0x0010UL)
+#define DMAMUX2_Channel5_BASE    (DMAMUX2_BASE + 0x0014UL)
+#define DMAMUX2_Channel6_BASE    (DMAMUX2_BASE + 0x0018UL)
+#define DMAMUX2_Channel7_BASE    (DMAMUX2_BASE + 0x001CUL)
+
+#define DMAMUX2_RequestGenerator0_BASE  (DMAMUX2_BASE + 0x0100UL)
+#define DMAMUX2_RequestGenerator1_BASE  (DMAMUX2_BASE + 0x0104UL)
+#define DMAMUX2_RequestGenerator2_BASE  (DMAMUX2_BASE + 0x0108UL)
+#define DMAMUX2_RequestGenerator3_BASE  (DMAMUX2_BASE + 0x010CUL)
+#define DMAMUX2_RequestGenerator4_BASE  (DMAMUX2_BASE + 0x0110UL)
+#define DMAMUX2_RequestGenerator5_BASE  (DMAMUX2_BASE + 0x0114UL)
+#define DMAMUX2_RequestGenerator6_BASE  (DMAMUX2_BASE + 0x0118UL)
+#define DMAMUX2_RequestGenerator7_BASE  (DMAMUX2_BASE + 0x011CUL)
+
+#define DMAMUX2_ChannelStatus_BASE      (DMAMUX2_BASE + 0x0080UL)
+#define DMAMUX2_RequestGenStatus_BASE   (DMAMUX2_BASE + 0x0140UL)
+
+#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)
+#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)
+#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)
+#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)
+#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)
+#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)
+#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)
+#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)
+
+#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)
+#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)
+#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)
+#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)
+#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)
+#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)
+#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)
+#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)
+
+#define DMAMUX1_Channel0_BASE    (DMAMUX1_BASE)
+#define DMAMUX1_Channel1_BASE    (DMAMUX1_BASE + 0x0004UL)
+#define DMAMUX1_Channel2_BASE    (DMAMUX1_BASE + 0x0008UL)
+#define DMAMUX1_Channel3_BASE    (DMAMUX1_BASE + 0x000CUL)
+#define DMAMUX1_Channel4_BASE    (DMAMUX1_BASE + 0x0010UL)
+#define DMAMUX1_Channel5_BASE    (DMAMUX1_BASE + 0x0014UL)
+#define DMAMUX1_Channel6_BASE    (DMAMUX1_BASE + 0x0018UL)
+#define DMAMUX1_Channel7_BASE    (DMAMUX1_BASE + 0x001CUL)
+#define DMAMUX1_Channel8_BASE    (DMAMUX1_BASE + 0x0020UL)
+#define DMAMUX1_Channel9_BASE    (DMAMUX1_BASE + 0x0024UL)
+#define DMAMUX1_Channel10_BASE   (DMAMUX1_BASE + 0x0028UL)
+#define DMAMUX1_Channel11_BASE   (DMAMUX1_BASE + 0x002CUL)
+#define DMAMUX1_Channel12_BASE   (DMAMUX1_BASE + 0x0030UL)
+#define DMAMUX1_Channel13_BASE   (DMAMUX1_BASE + 0x0034UL)
+#define DMAMUX1_Channel14_BASE   (DMAMUX1_BASE + 0x0038UL)
+#define DMAMUX1_Channel15_BASE   (DMAMUX1_BASE + 0x003CUL)
+
+#define DMAMUX1_RequestGenerator0_BASE  (DMAMUX1_BASE + 0x0100UL)
+#define DMAMUX1_RequestGenerator1_BASE  (DMAMUX1_BASE + 0x0104UL)
+#define DMAMUX1_RequestGenerator2_BASE  (DMAMUX1_BASE + 0x0108UL)
+#define DMAMUX1_RequestGenerator3_BASE  (DMAMUX1_BASE + 0x010CUL)
+#define DMAMUX1_RequestGenerator4_BASE  (DMAMUX1_BASE + 0x0110UL)
+#define DMAMUX1_RequestGenerator5_BASE  (DMAMUX1_BASE + 0x0114UL)
+#define DMAMUX1_RequestGenerator6_BASE  (DMAMUX1_BASE + 0x0118UL)
+#define DMAMUX1_RequestGenerator7_BASE  (DMAMUX1_BASE + 0x011CUL)
+
+#define DMAMUX1_ChannelStatus_BASE      (DMAMUX1_BASE + 0x0080UL)
+#define DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x0140UL)
+
+/*!< FMC Banks registers base  address */
+#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000UL)
+#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104UL)
+#define FMC_Bank2_R_BASE      (FMC_R_BASE + 0x0060UL)
+#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080UL)
+#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140UL)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE           (0x5C001000UL)
+
+#define MDMA_Channel0_BASE    (MDMA_BASE + 0x00000040UL)
+#define MDMA_Channel1_BASE    (MDMA_BASE + 0x00000080UL)
+#define MDMA_Channel2_BASE    (MDMA_BASE + 0x000000C0UL)
+#define MDMA_Channel3_BASE    (MDMA_BASE + 0x00000100UL)
+#define MDMA_Channel4_BASE    (MDMA_BASE + 0x00000140UL)
+#define MDMA_Channel5_BASE    (MDMA_BASE + 0x00000180UL)
+#define MDMA_Channel6_BASE    (MDMA_BASE + 0x000001C0UL)
+#define MDMA_Channel7_BASE    (MDMA_BASE + 0x00000200UL)
+#define MDMA_Channel8_BASE    (MDMA_BASE + 0x00000240UL)
+#define MDMA_Channel9_BASE    (MDMA_BASE + 0x00000280UL)
+#define MDMA_Channel10_BASE   (MDMA_BASE + 0x000002C0UL)
+#define MDMA_Channel11_BASE   (MDMA_BASE + 0x00000300UL)
+#define MDMA_Channel12_BASE   (MDMA_BASE + 0x00000340UL)
+#define MDMA_Channel13_BASE   (MDMA_BASE + 0x00000380UL)
+#define MDMA_Channel14_BASE   (MDMA_BASE + 0x000003C0UL)
+#define MDMA_Channel15_BASE   (MDMA_BASE + 0x00000400UL)
+
+#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL)
+#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL)
+#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL)
+#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL)
+#define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL)
+
+#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL)
+#define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL)
+#define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL)
+#define RAMECC2_Monitor4_BASE (RAMECC2_BASE + 0x80UL)
+#define RAMECC2_Monitor5_BASE (RAMECC2_BASE + 0xA0UL)
+
+#define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL)
+#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_declaration
+  * @{
+  */
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
+#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
+#define VREFBUF             ((VREFBUF_TypeDef *) VREFBUF_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG1               ((WWDG_TypeDef *) WWDG1_BASE)
+
+
+#define IWDG1               ((IWDG_TypeDef *) IWDG1_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
+#define SPI4                ((SPI_TypeDef *) SPI4_BASE)
+#define SPI5                ((SPI_TypeDef *) SPI5_BASE)
+#define SPI6                ((SPI_TypeDef *) SPI6_BASE)
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define USART3              ((USART_TypeDef *) USART3_BASE)
+#define USART6              ((USART_TypeDef *) USART6_BASE)
+#define UART7               ((USART_TypeDef *) UART7_BASE)
+#define UART8               ((USART_TypeDef *) UART8_BASE)
+#define CRS                 ((CRS_TypeDef *) CRS_BASE)
+#define UART4               ((USART_TypeDef *) UART4_BASE)
+#define UART5               ((USART_TypeDef *) UART5_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
+#define I2C4                ((I2C_TypeDef *) I2C4_BASE)
+#define FDCAN1              ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
+#define FDCAN2              ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
+#define FDCAN_CCU           ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)
+#define CEC                 ((CEC_TypeDef *) CEC_BASE)
+#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+#define DAC1                ((DAC_TypeDef *) DAC1_BASE)
+#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
+#define SWPMI1              ((SWPMI_TypeDef *) SWPMI1_BASE)
+#define LPTIM2              ((LPTIM_TypeDef *) LPTIM2_BASE)
+#define LPTIM3              ((LPTIM_TypeDef *) LPTIM3_BASE)
+#define LPTIM4              ((LPTIM_TypeDef *) LPTIM4_BASE)
+#define LPTIM5              ((LPTIM_TypeDef *) LPTIM5_BASE)
+
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define COMP12              ((COMPOPT_TypeDef *) COMP12_BASE)
+#define COMP1               ((COMP_TypeDef *) COMP1_BASE)
+#define COMP2               ((COMP_TypeDef *) COMP2_BASE)
+#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP2_BASE)
+#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
+#define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)
+#define OPAMP2              ((OPAMP_TypeDef *) OPAMP2_BASE)
+
+
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define EXTI_D1             ((EXTI_Core_TypeDef *) EXTI_D1_BASE)
+#define EXTI_D2             ((EXTI_Core_TypeDef *) EXTI_D2_BASE)
+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17               ((TIM_TypeDef *) TIM17_BASE)
+#define HRTIM1              ((HRTIM_TypeDef *) HRTIM1_BASE)
+#define HRTIM1_TIMA         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE)
+#define HRTIM1_TIMB         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE)
+#define HRTIM1_TIMC         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE)
+#define HRTIM1_TIMD         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE)
+#define HRTIM1_TIME         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE)
+#define HRTIM1_COMMON       ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)
+#define SAI1                ((SAI_TypeDef *) SAI1_BASE)
+#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
+#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+#define SAI2                ((SAI_TypeDef *) SAI2_BASE)
+#define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
+#define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
+#define SAI3                ((SAI_TypeDef *) SAI3_BASE)
+#define SAI3_Block_A        ((SAI_Block_TypeDef *)SAI3_Block_A_BASE)
+#define SAI3_Block_B        ((SAI_Block_TypeDef *)SAI3_Block_B_BASE)
+#define SAI4                ((SAI_TypeDef *) SAI4_BASE)
+#define SAI4_Block_A        ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)
+#define SAI4_Block_B        ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)
+
+#define SPDIFRX             ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
+#define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
+#define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
+#define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
+#define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
+#define DFSDM1_Channel4     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
+#define DFSDM1_Channel5     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
+#define DFSDM1_Channel6     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
+#define DFSDM1_Channel7     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
+#define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
+#define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
+#define DFSDM1_Filter2      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
+#define DFSDM1_Filter3      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
+#define DMA2D               ((DMA2D_TypeDef *) DMA2D_BASE)
+#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
+#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)
+#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)
+
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
+#define ADC3_COMMON         ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)
+#define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
+
+#define RNG                 ((RNG_TypeDef *) RNG_BASE)
+#define SDMMC2              ((SDMMC_TypeDef *) SDMMC2_BASE)
+#define DLYB_SDMMC2         ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)
+
+#define BDMA                ((BDMA_TypeDef *) BDMA_BASE)
+#define BDMA_Channel0       ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)
+#define BDMA_Channel1       ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)
+#define BDMA_Channel2       ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)
+#define BDMA_Channel3       ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)
+#define BDMA_Channel4       ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)
+#define BDMA_Channel5       ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)
+#define BDMA_Channel6       ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)
+#define BDMA_Channel7       ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)
+
+#define RAMECC1              ((RAMECC_TypeDef *)RAMECC1_BASE)
+#define RAMECC1_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)
+#define RAMECC1_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)
+#define RAMECC1_Monitor3     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)
+#define RAMECC1_Monitor4     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)
+#define RAMECC1_Monitor5     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)
+
+#define RAMECC2              ((RAMECC_TypeDef *)RAMECC2_BASE)
+#define RAMECC2_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)
+#define RAMECC2_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)
+#define RAMECC2_Monitor3     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)
+#define RAMECC2_Monitor4     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor4_BASE)
+#define RAMECC2_Monitor5     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor5_BASE)
+
+#define RAMECC3              ((RAMECC_TypeDef *)RAMECC3_BASE)
+#define RAMECC3_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)
+#define RAMECC3_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)
+
+#define DMAMUX2                ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)
+#define DMAMUX2_Channel0       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)
+#define DMAMUX2_Channel1       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)
+#define DMAMUX2_Channel2       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)
+#define DMAMUX2_Channel3       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)
+#define DMAMUX2_Channel4       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)
+#define DMAMUX2_Channel5       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)
+#define DMAMUX2_Channel6       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)
+#define DMAMUX2_Channel7       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)
+
+
+#define DMAMUX2_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)
+#define DMAMUX2_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)
+#define DMAMUX2_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)
+#define DMAMUX2_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)
+#define DMAMUX2_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)
+#define DMAMUX2_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)
+#define DMAMUX2_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)
+#define DMAMUX2_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)
+
+#define DMAMUX2_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)
+#define DMAMUX2_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)
+
+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+
+
+#define DMAMUX1              ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
+#define DMAMUX1_Channel0     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
+#define DMAMUX1_Channel1     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
+#define DMAMUX1_Channel2     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
+#define DMAMUX1_Channel3     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
+#define DMAMUX1_Channel4     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
+#define DMAMUX1_Channel5     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
+#define DMAMUX1_Channel6     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
+#define DMAMUX1_Channel7     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
+#define DMAMUX1_Channel8     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
+#define DMAMUX1_Channel9     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
+#define DMAMUX1_Channel10    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
+#define DMAMUX1_Channel11    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
+#define DMAMUX1_Channel12    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
+#define DMAMUX1_Channel13    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
+#define DMAMUX1_Channel14    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
+#define DMAMUX1_Channel15    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
+
+#define DMAMUX1_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
+#define DMAMUX1_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
+#define DMAMUX1_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
+#define DMAMUX1_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
+#define DMAMUX1_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)
+#define DMAMUX1_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)
+#define DMAMUX1_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)
+#define DMAMUX1_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)
+
+#define DMAMUX1_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *)    DMAMUX1_ChannelStatus_BASE)
+#define DMAMUX1_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
+
+
+#define FMC_Bank1_R           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
+#define FMC_Bank1E_R          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
+#define FMC_Bank2_R           ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)
+#define FMC_Bank3_R           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
+#define FMC_Bank5_6_R         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
+
+
+#define QUADSPI               ((QUADSPI_TypeDef *) QSPI_R_BASE)
+#define DLYB_QUADSPI          ((DLYB_TypeDef *) DLYB_QSPI_BASE)
+#define SDMMC1                ((SDMMC_TypeDef *) SDMMC1_BASE)
+#define DLYB_SDMMC1           ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)
+
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define JPEG                ((JPEG_TypeDef *) JPGDEC_BASE)
+#define HSEM                ((HSEM_TypeDef *) HSEM_BASE)
+#define HSEM_COMMON         ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))
+
+#define LTDC                ((LTDC_TypeDef *)LTDC_BASE)
+#define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
+#define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
+
+#define MDIOS               ((MDIOS_TypeDef *) MDIOS_BASE)
+
+#define ETH                 ((ETH_TypeDef *)ETH_BASE)
+#define MDMA                ((MDMA_TypeDef *)MDMA_BASE)
+#define MDMA_Channel0       ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)
+#define MDMA_Channel1       ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)
+#define MDMA_Channel2       ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)
+#define MDMA_Channel3       ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)
+#define MDMA_Channel4       ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)
+#define MDMA_Channel5       ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)
+#define MDMA_Channel6       ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)
+#define MDMA_Channel7       ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)
+#define MDMA_Channel8       ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)
+#define MDMA_Channel9       ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)
+#define MDMA_Channel10      ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)
+#define MDMA_Channel11      ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)
+#define MDMA_Channel12      ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)
+#define MDMA_Channel13      ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)
+#define MDMA_Channel14      ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)
+#define MDMA_Channel15      ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)
+
+
+#define USB1_OTG_HS         ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)
+#define USB2_OTG_FS         ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE)
+
+/* Legacy defines */
+#define USB_OTG_HS                   USB1_OTG_HS
+#define USB_OTG_HS_PERIPH_BASE       USB1_OTG_HS_PERIPH_BASE
+#define USB_OTG_FS                   USB2_OTG_FS
+#define USB_OTG_FS_PERIPH_BASE       USB2_OTG_FS_PERIPH_BASE
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+
+  /** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+
+/******************************************************************************/
+/*                         Peripheral Registers_Bits_Definition               */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Analog to Digital Converter                         */
+/*                                                                            */
+/******************************************************************************/
+/*******************************  ADC VERSION  ********************************/
+#define ADC_VER_V5_X
+/********************  Bit definition for ADC_ISR register  ********************/
+#define ADC_ISR_ADRDY_Pos                 (0U)
+#define ADC_ISR_ADRDY_Msk                 (0x1UL << ADC_ISR_ADRDY_Pos)         /*!< 0x00000001 */
+#define ADC_ISR_ADRDY                     ADC_ISR_ADRDY_Msk                    /*!< ADC Ready (ADRDY) flag  */
+#define ADC_ISR_EOSMP_Pos                 (1U)
+#define ADC_ISR_EOSMP_Msk                 (0x1UL << ADC_ISR_EOSMP_Pos)         /*!< 0x00000002 */
+#define ADC_ISR_EOSMP                     ADC_ISR_EOSMP_Msk                    /*!< ADC End of Sampling flag */
+#define ADC_ISR_EOC_Pos                   (2U)
+#define ADC_ISR_EOC_Msk                   (0x1UL << ADC_ISR_EOC_Pos)           /*!< 0x00000004 */
+#define ADC_ISR_EOC                       ADC_ISR_EOC_Msk                      /*!< ADC End of Regular Conversion flag */
+#define ADC_ISR_EOS_Pos                   (3U)
+#define ADC_ISR_EOS_Msk                   (0x1UL << ADC_ISR_EOS_Pos)           /*!< 0x00000008 */
+#define ADC_ISR_EOS                       ADC_ISR_EOS_Msk                      /*!< ADC End of Regular sequence of Conversions flag */
+#define ADC_ISR_OVR_Pos                   (4U)
+#define ADC_ISR_OVR_Msk                   (0x1UL << ADC_ISR_OVR_Pos)           /*!< 0x00000010 */
+#define ADC_ISR_OVR                       ADC_ISR_OVR_Msk                      /*!< ADC overrun flag */
+#define ADC_ISR_JEOC_Pos                  (5U)
+#define ADC_ISR_JEOC_Msk                  (0x1UL << ADC_ISR_JEOC_Pos)          /*!< 0x00000020 */
+#define ADC_ISR_JEOC                      ADC_ISR_JEOC_Msk                     /*!< ADC End of Injected Conversion flag */
+#define ADC_ISR_JEOS_Pos                  (6U)
+#define ADC_ISR_JEOS_Msk                  (0x1UL << ADC_ISR_JEOS_Pos)          /*!< 0x00000040 */
+#define ADC_ISR_JEOS                      ADC_ISR_JEOS_Msk                     /*!< ADC End of Injected sequence of Conversions flag */
+#define ADC_ISR_AWD1_Pos                  (7U)
+#define ADC_ISR_AWD1_Msk                  (0x1UL << ADC_ISR_AWD1_Pos)          /*!< 0x00000080 */
+#define ADC_ISR_AWD1                      ADC_ISR_AWD1_Msk                     /*!< ADC Analog watchdog 1 flag */
+#define ADC_ISR_AWD2_Pos                  (8U)
+#define ADC_ISR_AWD2_Msk                  (0x1UL << ADC_ISR_AWD2_Pos)          /*!< 0x00000100 */
+#define ADC_ISR_AWD2                      ADC_ISR_AWD2_Msk                     /*!< ADC Analog watchdog 2 flag */
+#define ADC_ISR_AWD3_Pos                  (9U)
+#define ADC_ISR_AWD3_Msk                  (0x1UL << ADC_ISR_AWD3_Pos)          /*!< 0x00000200 */
+#define ADC_ISR_AWD3                      ADC_ISR_AWD3_Msk                     /*!< ADC Analog watchdog 3 flag */
+#define ADC_ISR_JQOVF_Pos                 (10U)
+#define ADC_ISR_JQOVF_Msk                 (0x1UL << ADC_ISR_JQOVF_Pos)         /*!< 0x00000400 */
+#define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                    /*!< ADC Injected Context Queue Overflow flag */
+
+/********************  Bit definition for ADC_IER register  ********************/
+#define ADC_IER_ADRDYIE_Pos               (0U)
+#define ADC_IER_ADRDYIE_Msk               (0x1UL << ADC_IER_ADRDYIE_Pos)       /*!< 0x00000001 */
+#define ADC_IER_ADRDYIE                   ADC_IER_ADRDYIE_Msk                  /*!< ADC Ready (ADRDY) interrupt source */
+#define ADC_IER_EOSMPIE_Pos               (1U)
+#define ADC_IER_EOSMPIE_Msk               (0x1UL << ADC_IER_EOSMPIE_Pos)       /*!< 0x00000002 */
+#define ADC_IER_EOSMPIE                   ADC_IER_EOSMPIE_Msk                  /*!< ADC End of Sampling interrupt source */
+#define ADC_IER_EOCIE_Pos                 (2U)
+#define ADC_IER_EOCIE_Msk                 (0x1UL << ADC_IER_EOCIE_Pos)         /*!< 0x00000004 */
+#define ADC_IER_EOCIE                     ADC_IER_EOCIE_Msk                    /*!< ADC End of Regular Conversion interrupt source */
+#define ADC_IER_EOSIE_Pos                 (3U)
+#define ADC_IER_EOSIE_Msk                 (0x1UL << ADC_IER_EOSIE_Pos)         /*!< 0x00000008 */
+#define ADC_IER_EOSIE                     ADC_IER_EOSIE_Msk                    /*!< ADC End of Regular sequence of Conversions interrupt source */
+#define ADC_IER_OVRIE_Pos                 (4U)
+#define ADC_IER_OVRIE_Msk                 (0x1UL << ADC_IER_OVRIE_Pos)         /*!< 0x00000010 */
+#define ADC_IER_OVRIE                     ADC_IER_OVRIE_Msk                    /*!< ADC overrun interrupt source */
+#define ADC_IER_JEOCIE_Pos                (5U)
+#define ADC_IER_JEOCIE_Msk                (0x1UL << ADC_IER_JEOCIE_Pos)        /*!< 0x00000020 */
+#define ADC_IER_JEOCIE                    ADC_IER_JEOCIE_Msk                   /*!< ADC End of Injected Conversion interrupt source */
+#define ADC_IER_JEOSIE_Pos                (6U)
+#define ADC_IER_JEOSIE_Msk                (0x1UL << ADC_IER_JEOSIE_Pos)        /*!< 0x00000040 */
+#define ADC_IER_JEOSIE                    ADC_IER_JEOSIE_Msk                   /*!< ADC End of Injected sequence of Conversions interrupt source */
+#define ADC_IER_AWD1IE_Pos                (7U)
+#define ADC_IER_AWD1IE_Msk                (0x1UL << ADC_IER_AWD1IE_Pos)        /*!< 0x00000080 */
+#define ADC_IER_AWD1IE                    ADC_IER_AWD1IE_Msk                   /*!< ADC Analog watchdog 1 interrupt source */
+#define ADC_IER_AWD2IE_Pos                (8U)
+#define ADC_IER_AWD2IE_Msk                (0x1UL << ADC_IER_AWD2IE_Pos)        /*!< 0x00000100 */
+#define ADC_IER_AWD2IE                    ADC_IER_AWD2IE_Msk                   /*!< ADC Analog watchdog 2 interrupt source */
+#define ADC_IER_AWD3IE_Pos                (9U)
+#define ADC_IER_AWD3IE_Msk                (0x1UL << ADC_IER_AWD3IE_Pos)        /*!< 0x00000200 */
+#define ADC_IER_AWD3IE                    ADC_IER_AWD3IE_Msk                   /*!< ADC Analog watchdog 3 interrupt source */
+#define ADC_IER_JQOVFIE_Pos               (10U)
+#define ADC_IER_JQOVFIE_Msk               (0x1UL << ADC_IER_JQOVFIE_Pos)       /*!< 0x00000400 */
+#define ADC_IER_JQOVFIE                   ADC_IER_JQOVFIE_Msk                  /*!< ADC Injected Context Queue Overflow interrupt source */
+
+/********************  Bit definition for ADC_CR register  ********************/
+#define ADC_CR_ADEN_Pos                   (0U)
+#define ADC_CR_ADEN_Msk                   (0x1UL << ADC_CR_ADEN_Pos)           /*!< 0x00000001 */
+#define ADC_CR_ADEN                       ADC_CR_ADEN_Msk                      /*!< ADC Enable control */
+#define ADC_CR_ADDIS_Pos                  (1U)
+#define ADC_CR_ADDIS_Msk                  (0x1UL << ADC_CR_ADDIS_Pos)          /*!< 0x00000002 */
+#define ADC_CR_ADDIS                      ADC_CR_ADDIS_Msk                     /*!< ADC Disable command */
+#define ADC_CR_ADSTART_Pos                (2U)
+#define ADC_CR_ADSTART_Msk                (0x1UL << ADC_CR_ADSTART_Pos)        /*!< 0x00000004 */
+#define ADC_CR_ADSTART                    ADC_CR_ADSTART_Msk                   /*!< ADC Start of Regular conversion */
+#define ADC_CR_JADSTART_Pos               (3U)
+#define ADC_CR_JADSTART_Msk               (0x1UL << ADC_CR_JADSTART_Pos)       /*!< 0x00000008 */
+#define ADC_CR_JADSTART                   ADC_CR_JADSTART_Msk                  /*!< ADC Start of injected conversion */
+#define ADC_CR_ADSTP_Pos                  (4U)
+#define ADC_CR_ADSTP_Msk                  (0x1UL << ADC_CR_ADSTP_Pos)          /*!< 0x00000010 */
+#define ADC_CR_ADSTP                      ADC_CR_ADSTP_Msk                     /*!< ADC Stop of Regular conversion */
+#define ADC_CR_JADSTP_Pos                 (5U)
+#define ADC_CR_JADSTP_Msk                 (0x1UL << ADC_CR_JADSTP_Pos)         /*!< 0x00000020 */
+#define ADC_CR_JADSTP                     ADC_CR_JADSTP_Msk                    /*!< ADC Stop of injected conversion */
+#define ADC_CR_BOOST_Pos                  (8U)
+#define ADC_CR_BOOST_Msk                  (0x3UL << ADC_CR_BOOST_Pos)          /*!< 0x00000300 */
+#define ADC_CR_BOOST                      ADC_CR_BOOST_Msk                     /*!< ADC Boost Mode configuration */
+#define ADC_CR_BOOST_0                    (0x1UL << ADC_CR_BOOST_Pos)           /*!< 0x00000100 */
+#define ADC_CR_BOOST_1                    (0x2UL << ADC_CR_BOOST_Pos)           /*!< 0x00000200 */
+#define ADC_CR_ADCALLIN_Pos               (16U)
+#define ADC_CR_ADCALLIN_Msk               (0x1UL << ADC_CR_ADCALLIN_Pos)       /*!< 0x00010000 */
+#define ADC_CR_ADCALLIN                   ADC_CR_ADCALLIN_Msk                  /*!< ADC Linearity calibration */
+#define ADC_CR_LINCALRDYW1_Pos            (22U)
+#define ADC_CR_LINCALRDYW1_Msk            (0x1UL << ADC_CR_LINCALRDYW1_Pos)    /*!< 0x00400000 */
+#define ADC_CR_LINCALRDYW1                ADC_CR_LINCALRDYW1_Msk               /*!< ADC Linearity calibration ready Word 1 */
+#define ADC_CR_LINCALRDYW2_Pos            (23U)
+#define ADC_CR_LINCALRDYW2_Msk            (0x1UL << ADC_CR_LINCALRDYW2_Pos)    /*!< 0x00800000 */
+#define ADC_CR_LINCALRDYW2                ADC_CR_LINCALRDYW2_Msk               /*!< ADC Linearity calibration ready Word 2 */
+#define ADC_CR_LINCALRDYW3_Pos            (24U)
+#define ADC_CR_LINCALRDYW3_Msk            (0x1UL << ADC_CR_LINCALRDYW3_Pos)    /*!< 0x01000000 */
+#define ADC_CR_LINCALRDYW3                ADC_CR_LINCALRDYW3_Msk               /*!< ADC Linearity calibration ready Word 3 */
+#define ADC_CR_LINCALRDYW4_Pos            (25U)
+#define ADC_CR_LINCALRDYW4_Msk            (0x1UL << ADC_CR_LINCALRDYW4_Pos)    /*!< 0x02000000 */
+#define ADC_CR_LINCALRDYW4                ADC_CR_LINCALRDYW4_Msk               /*!< ADC Linearity calibration ready Word 4 */
+#define ADC_CR_LINCALRDYW5_Pos            (26U)
+#define ADC_CR_LINCALRDYW5_Msk            (0x1UL << ADC_CR_LINCALRDYW5_Pos)    /*!< 0x04000000 */
+#define ADC_CR_LINCALRDYW5                ADC_CR_LINCALRDYW5_Msk               /*!< ADC Linearity calibration ready Word 5 */
+#define ADC_CR_LINCALRDYW6_Pos            (27U)
+#define ADC_CR_LINCALRDYW6_Msk            (0x1UL << ADC_CR_LINCALRDYW6_Pos)    /*!< 0x08000000 */
+#define ADC_CR_LINCALRDYW6                ADC_CR_LINCALRDYW6_Msk               /*!< ADC Linearity calibration ready Word 6 */
+#define ADC_CR_ADVREGEN_Pos               (28U)
+#define ADC_CR_ADVREGEN_Msk               (0x1UL << ADC_CR_ADVREGEN_Pos)       /*!< 0x10000000 */
+#define ADC_CR_ADVREGEN                   ADC_CR_ADVREGEN_Msk                  /*!< ADC Voltage regulator Enable */
+#define ADC_CR_DEEPPWD_Pos                (29U)
+#define ADC_CR_DEEPPWD_Msk                (0x1UL << ADC_CR_DEEPPWD_Pos)        /*!< 0x20000000 */
+#define ADC_CR_DEEPPWD                    ADC_CR_DEEPPWD_Msk                   /*!< ADC Deep power down Enable */
+#define ADC_CR_ADCALDIF_Pos               (30U)
+#define ADC_CR_ADCALDIF_Msk               (0x1UL << ADC_CR_ADCALDIF_Pos)       /*!< 0x40000000 */
+#define ADC_CR_ADCALDIF                   ADC_CR_ADCALDIF_Msk                  /*!< ADC Differential Mode for calibration */
+#define ADC_CR_ADCAL_Pos                  (31U)
+#define ADC_CR_ADCAL_Msk                  (0x1UL << ADC_CR_ADCAL_Pos)          /*!< 0x80000000 */
+#define ADC_CR_ADCAL                      ADC_CR_ADCAL_Msk                     /*!< ADC Calibration */
+
+/********************  Bit definition for ADC_CFGR register  ********************/
+#define ADC_CFGR_DMNGT_Pos                (0U)
+#define ADC_CFGR_DMNGT_Msk                (0x3UL << ADC_CFGR_DMNGT_Pos)        /*!< 0x00000003 */
+#define ADC_CFGR_DMNGT                    ADC_CFGR_DMNGT_Msk                   /*!< ADC Data Management configuration */
+#define ADC_CFGR_DMNGT_0                  (0x1UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000001 */
+#define ADC_CFGR_DMNGT_1                  (0x2UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000002 */
+
+#define ADC_CFGR_RES_Pos                  (2U)
+#define ADC_CFGR_RES_Msk                  (0x7UL << ADC_CFGR_RES_Pos)          /*!< 0x0000001C */
+#define ADC_CFGR_RES                      ADC_CFGR_RES_Msk                     /*!< ADC Data resolution */
+#define ADC_CFGR_RES_0                    (0x1UL << ADC_CFGR_RES_Pos)           /*!< 0x00000004 */
+#define ADC_CFGR_RES_1                    (0x2UL << ADC_CFGR_RES_Pos)           /*!< 0x00000008 */
+#define ADC_CFGR_RES_2                    (0x4UL << ADC_CFGR_RES_Pos)           /*!< 0x00000010 */
+
+#define ADC_CFGR_EXTSEL_Pos               (5U)
+#define ADC_CFGR_EXTSEL_Msk               (0x1FUL << ADC_CFGR_EXTSEL_Pos)      /*!< 0x000003E0 */
+#define ADC_CFGR_EXTSEL                   ADC_CFGR_EXTSEL_Msk                  /*!< ADC External trigger selection for regular group */
+#define ADC_CFGR_EXTSEL_0                 (0x01UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000020 */
+#define ADC_CFGR_EXTSEL_1                 (0x02UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000040 */
+#define ADC_CFGR_EXTSEL_2                 (0x04UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000080 */
+#define ADC_CFGR_EXTSEL_3                 (0x08UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000100 */
+#define ADC_CFGR_EXTSEL_4                 (0x10UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000200 */
+
+#define ADC_CFGR_EXTEN_Pos                (10U)
+#define ADC_CFGR_EXTEN_Msk                (0x3UL << ADC_CFGR_EXTEN_Pos)        /*!< 0x00000C00 */
+#define ADC_CFGR_EXTEN                    ADC_CFGR_EXTEN_Msk                   /*!< ADC External trigger enable and polarity selection for regular channels */
+#define ADC_CFGR_EXTEN_0                  (0x1UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000400 */
+#define ADC_CFGR_EXTEN_1                  (0x2UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000800 */
+
+#define ADC_CFGR_OVRMOD_Pos               (12U)
+#define ADC_CFGR_OVRMOD_Msk               (0x1UL << ADC_CFGR_OVRMOD_Pos)       /*!< 0x00001000 */
+#define ADC_CFGR_OVRMOD                   ADC_CFGR_OVRMOD_Msk                  /*!< ADC overrun mode */
+#define ADC_CFGR_CONT_Pos                 (13U)
+#define ADC_CFGR_CONT_Msk                 (0x1UL << ADC_CFGR_CONT_Pos)         /*!< 0x00002000 */
+#define ADC_CFGR_CONT                     ADC_CFGR_CONT_Msk                    /*!< ADC Single/continuous conversion mode for regular conversion */
+#define ADC_CFGR_AUTDLY_Pos               (14U)
+#define ADC_CFGR_AUTDLY_Msk               (0x1UL << ADC_CFGR_AUTDLY_Pos)       /*!< 0x00004000 */
+#define ADC_CFGR_AUTDLY                   ADC_CFGR_AUTDLY_Msk                  /*!< ADC Delayed conversion mode */
+
+#define ADC_CFGR_DISCEN_Pos               (16U)
+#define ADC_CFGR_DISCEN_Msk               (0x1UL << ADC_CFGR_DISCEN_Pos)       /*!< 0x00010000 */
+#define ADC_CFGR_DISCEN                   ADC_CFGR_DISCEN_Msk                  /*!< ADC Discontinuous mode for regular channels */
+
+#define ADC_CFGR_DISCNUM_Pos              (17U)
+#define ADC_CFGR_DISCNUM_Msk              (0x7UL << ADC_CFGR_DISCNUM_Pos)      /*!< 0x000E0000 */
+#define ADC_CFGR_DISCNUM                  ADC_CFGR_DISCNUM_Msk                 /*!< ADC Discontinuous mode channel count */
+#define ADC_CFGR_DISCNUM_0                (0x1UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00020000 */
+#define ADC_CFGR_DISCNUM_1                (0x2UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00040000 */
+#define ADC_CFGR_DISCNUM_2                (0x4UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00080000 */
+
+#define ADC_CFGR_JDISCEN_Pos              (20U)
+#define ADC_CFGR_JDISCEN_Msk              (0x1UL << ADC_CFGR_JDISCEN_Pos)      /*!< 0x00100000 */
+#define ADC_CFGR_JDISCEN                  ADC_CFGR_JDISCEN_Msk                 /*!< ADC Discontinuous mode on injected channels */
+#define ADC_CFGR_JQM_Pos                  (21U)
+#define ADC_CFGR_JQM_Msk                  (0x1UL << ADC_CFGR_JQM_Pos)          /*!< 0x00200000 */
+#define ADC_CFGR_JQM                      ADC_CFGR_JQM_Msk                     /*!< ADC JSQR Queue mode */
+#define ADC_CFGR_AWD1SGL_Pos              (22U)
+#define ADC_CFGR_AWD1SGL_Msk              (0x1UL << ADC_CFGR_AWD1SGL_Pos)      /*!< 0x00400000 */
+#define ADC_CFGR_AWD1SGL                  ADC_CFGR_AWD1SGL_Msk                 /*!< Enable the watchdog 1 on a single channel or on all channels */
+#define ADC_CFGR_AWD1EN_Pos               (23U)
+#define ADC_CFGR_AWD1EN_Msk               (0x1UL << ADC_CFGR_AWD1EN_Pos)       /*!< 0x00800000 */
+#define ADC_CFGR_AWD1EN                   ADC_CFGR_AWD1EN_Msk                  /*!< ADC Analog watchdog 1 enable on regular Channels */
+#define ADC_CFGR_JAWD1EN_Pos              (24U)
+#define ADC_CFGR_JAWD1EN_Msk              (0x1UL << ADC_CFGR_JAWD1EN_Pos)      /*!< 0x01000000 */
+#define ADC_CFGR_JAWD1EN                  ADC_CFGR_JAWD1EN_Msk                 /*!< ADC Analog watchdog 1 enable on injected Channels */
+#define ADC_CFGR_JAUTO_Pos                (25U)
+#define ADC_CFGR_JAUTO_Msk                (0x1UL << ADC_CFGR_JAUTO_Pos)        /*!< 0x02000000 */
+#define ADC_CFGR_JAUTO                    ADC_CFGR_JAUTO_Msk                   /*!< ADC Automatic injected group conversion */
+
+#define ADC_CFGR_AWD1CH_Pos               (26U)
+#define ADC_CFGR_AWD1CH_Msk               (0x1FUL << ADC_CFGR_AWD1CH_Pos)      /*!< 0x7C000000 */
+#define ADC_CFGR_AWD1CH                   ADC_CFGR_AWD1CH_Msk                  /*!< ADC Analog watchdog 1 Channel selection */
+#define ADC_CFGR_AWD1CH_0                 (0x01UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x04000000 */
+#define ADC_CFGR_AWD1CH_1                 (0x02UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x08000000 */
+#define ADC_CFGR_AWD1CH_2                 (0x04UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x10000000 */
+#define ADC_CFGR_AWD1CH_3                 (0x08UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x20000000 */
+#define ADC_CFGR_AWD1CH_4                 (0x10UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x40000000 */
+
+#define ADC_CFGR_JQDIS_Pos                (31U)
+#define ADC_CFGR_JQDIS_Msk                (0x1UL << ADC_CFGR_JQDIS_Pos)        /*!< 0x80000000 */
+#define ADC_CFGR_JQDIS                    ADC_CFGR_JQDIS_Msk                   /*!< ADC Injected queue disable */
+
+/********************  Bit definition for ADC_CFGR2 register  ********************/
+#define ADC_CFGR2_ROVSE_Pos               (0U)
+#define ADC_CFGR2_ROVSE_Msk               (0x1UL << ADC_CFGR2_ROVSE_Pos)       /*!< 0x00000001 */
+#define ADC_CFGR2_ROVSE                   ADC_CFGR2_ROVSE_Msk                  /*!< ADC Regular group oversampler enable */
+#define ADC_CFGR2_JOVSE_Pos               (1U)
+#define ADC_CFGR2_JOVSE_Msk               (0x1UL << ADC_CFGR2_JOVSE_Pos)       /*!< 0x00000002 */
+#define ADC_CFGR2_JOVSE                   ADC_CFGR2_JOVSE_Msk                  /*!< ADC Injected group oversampler enable */
+
+#define ADC_CFGR2_OVSS_Pos                (5U)
+#define ADC_CFGR2_OVSS_Msk                (0xFUL << ADC_CFGR2_OVSS_Pos)        /*!< 0x000001E0 */
+#define ADC_CFGR2_OVSS                    ADC_CFGR2_OVSS_Msk                   /*!< ADC Regular Oversampling shift */
+#define ADC_CFGR2_OVSS_0                  (0x1UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000020 */
+#define ADC_CFGR2_OVSS_1                  (0x2UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000040 */
+#define ADC_CFGR2_OVSS_2                  (0x4UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000080 */
+#define ADC_CFGR2_OVSS_3                  (0x8UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000100 */
+
+#define ADC_CFGR2_TROVS_Pos               (9U)
+#define ADC_CFGR2_TROVS_Msk               (0x1UL << ADC_CFGR2_TROVS_Pos)       /*!< 0x00000200 */
+#define ADC_CFGR2_TROVS                   ADC_CFGR2_TROVS_Msk                  /*!< ADC Triggered regular Oversampling */
+#define ADC_CFGR2_ROVSM_Pos               (10U)
+#define ADC_CFGR2_ROVSM_Msk               (0x1UL << ADC_CFGR2_ROVSM_Pos)       /*!< 0x00000400 */
+#define ADC_CFGR2_ROVSM                   ADC_CFGR2_ROVSM_Msk                  /*!< ADC Regular oversampling mode */
+
+#define ADC_CFGR2_RSHIFT1_Pos             (11U)
+#define ADC_CFGR2_RSHIFT1_Msk             (0x1UL << ADC_CFGR2_RSHIFT1_Pos)     /*!< 0x00000800 */
+#define ADC_CFGR2_RSHIFT1                 ADC_CFGR2_RSHIFT1_Msk                /*!< ADC Right-shift data after Offset 1 correction */
+#define ADC_CFGR2_RSHIFT2_Pos             (12U)
+#define ADC_CFGR2_RSHIFT2_Msk             (0x1UL << ADC_CFGR2_RSHIFT2_Pos)     /*!< 0x00001000 */
+#define ADC_CFGR2_RSHIFT2                 ADC_CFGR2_RSHIFT2_Msk                /*!< ADC Right-shift data after Offset 2 correction */
+#define ADC_CFGR2_RSHIFT3_Pos             (13U)
+#define ADC_CFGR2_RSHIFT3_Msk             (0x1UL << ADC_CFGR2_RSHIFT3_Pos)     /*!< 0x00002000 */
+#define ADC_CFGR2_RSHIFT3                 ADC_CFGR2_RSHIFT3_Msk                /*!< ADC Right-shift data after Offset 3 correction */
+#define ADC_CFGR2_RSHIFT4_Pos             (14U)
+#define ADC_CFGR2_RSHIFT4_Msk             (0x1UL << ADC_CFGR2_RSHIFT4_Pos)     /*!< 0x00004000 */
+#define ADC_CFGR2_RSHIFT4                 ADC_CFGR2_RSHIFT4_Msk                /*!< ADC Right-shift data after Offset 4 correction */
+
+#define ADC_CFGR2_OVSR_Pos                (16U)
+#define ADC_CFGR2_OVSR_Msk                (0x3FFUL << ADC_CFGR2_OVSR_Pos)      /*!< 0x03FF0000 */
+#define ADC_CFGR2_OVSR                    ADC_CFGR2_OVSR_Msk                   /*!< ADC oversampling Ratio */
+#define ADC_CFGR2_OVSR_0                  (0x001UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00010000 */
+#define ADC_CFGR2_OVSR_1                  (0x002UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00020000 */
+#define ADC_CFGR2_OVSR_2                  (0x004UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00040000 */
+#define ADC_CFGR2_OVSR_3                  (0x008UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00080000 */
+#define ADC_CFGR2_OVSR_4                  (0x010UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00100000 */
+#define ADC_CFGR2_OVSR_5                  (0x020UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00200000 */
+#define ADC_CFGR2_OVSR_6                  (0x040UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00400000 */
+#define ADC_CFGR2_OVSR_7                  (0x080UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00800000 */
+#define ADC_CFGR2_OVSR_8                  (0x100UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x01000000 */
+#define ADC_CFGR2_OVSR_9                  (0x200UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x02000000 */
+
+#define ADC_CFGR2_LSHIFT_Pos              (28U)
+#define ADC_CFGR2_LSHIFT_Msk              (0xFUL << ADC_CFGR2_LSHIFT_Pos)      /*!< 0xF0000000 */
+#define ADC_CFGR2_LSHIFT                  ADC_CFGR2_LSHIFT_Msk                 /*!< ADC Left shift factor */
+#define ADC_CFGR2_LSHIFT_0                (0x1UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x10000000 */
+#define ADC_CFGR2_LSHIFT_1                (0x2UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x20000000 */
+#define ADC_CFGR2_LSHIFT_2                (0x4UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x40000000 */
+#define ADC_CFGR2_LSHIFT_3                (0x8UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_SMPR1 register  ********************/
+#define ADC_SMPR1_SMP0_Pos                (0U)
+#define ADC_SMPR1_SMP0_Msk                (0x7UL << ADC_SMPR1_SMP0_Pos)        /*!< 0x00000007 */
+#define ADC_SMPR1_SMP0                    ADC_SMPR1_SMP0_Msk                   /*!< ADC Channel 0 Sampling time selection  */
+#define ADC_SMPR1_SMP0_0                  (0x1UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000001 */
+#define ADC_SMPR1_SMP0_1                  (0x2UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000002 */
+#define ADC_SMPR1_SMP0_2                  (0x4UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000004 */
+
+#define ADC_SMPR1_SMP1_Pos                (3U)
+#define ADC_SMPR1_SMP1_Msk                (0x7UL << ADC_SMPR1_SMP1_Pos)        /*!< 0x00000038 */
+#define ADC_SMPR1_SMP1                    ADC_SMPR1_SMP1_Msk                   /*!< ADC Channel 1 Sampling time selection  */
+#define ADC_SMPR1_SMP1_0                  (0x1UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000008 */
+#define ADC_SMPR1_SMP1_1                  (0x2UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000010 */
+#define ADC_SMPR1_SMP1_2                  (0x4UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000020 */
+
+#define ADC_SMPR1_SMP2_Pos                (6U)
+#define ADC_SMPR1_SMP2_Msk                (0x7UL << ADC_SMPR1_SMP2_Pos)        /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP2                    ADC_SMPR1_SMP2_Msk                   /*!< ADC Channel 2 Sampling time selection  */
+#define ADC_SMPR1_SMP2_0                  (0x1UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000040 */
+#define ADC_SMPR1_SMP2_1                  (0x2UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000080 */
+#define ADC_SMPR1_SMP2_2                  (0x4UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000100 */
+
+#define ADC_SMPR1_SMP3_Pos                (9U)
+#define ADC_SMPR1_SMP3_Msk                (0x7UL << ADC_SMPR1_SMP3_Pos)        /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP3                    ADC_SMPR1_SMP3_Msk                   /*!< ADC Channel 3 Sampling time selection  */
+#define ADC_SMPR1_SMP3_0                  (0x1UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000200 */
+#define ADC_SMPR1_SMP3_1                  (0x2UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000400 */
+#define ADC_SMPR1_SMP3_2                  (0x4UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000800 */
+
+#define ADC_SMPR1_SMP4_Pos                (12U)
+#define ADC_SMPR1_SMP4_Msk                (0x7UL << ADC_SMPR1_SMP4_Pos)        /*!< 0x00007000 */
+#define ADC_SMPR1_SMP4                    ADC_SMPR1_SMP4_Msk                   /*!< ADC Channel 4 Sampling time selection  */
+#define ADC_SMPR1_SMP4_0                  (0x1UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00001000 */
+#define ADC_SMPR1_SMP4_1                  (0x2UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00002000 */
+#define ADC_SMPR1_SMP4_2                  (0x4UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00004000 */
+
+#define ADC_SMPR1_SMP5_Pos                (15U)
+#define ADC_SMPR1_SMP5_Msk                (0x7UL << ADC_SMPR1_SMP5_Pos)        /*!< 0x00038000 */
+#define ADC_SMPR1_SMP5                    ADC_SMPR1_SMP5_Msk                   /*!< ADC Channel 5 Sampling time selection  */
+#define ADC_SMPR1_SMP5_0                  (0x1UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00008000 */
+#define ADC_SMPR1_SMP5_1                  (0x2UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00010000 */
+#define ADC_SMPR1_SMP5_2                  (0x4UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00020000 */
+
+#define ADC_SMPR1_SMP6_Pos                (18U)
+#define ADC_SMPR1_SMP6_Msk                (0x7UL << ADC_SMPR1_SMP6_Pos)        /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP6                    ADC_SMPR1_SMP6_Msk                   /*!< ADC Channel 6 Sampling time selection  */
+#define ADC_SMPR1_SMP6_0                  (0x1UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00040000 */
+#define ADC_SMPR1_SMP6_1                  (0x2UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00080000 */
+#define ADC_SMPR1_SMP6_2                  (0x4UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00100000 */
+
+#define ADC_SMPR1_SMP7_Pos                (21U)
+#define ADC_SMPR1_SMP7_Msk                (0x7UL << ADC_SMPR1_SMP7_Pos)        /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP7                    ADC_SMPR1_SMP7_Msk                   /*!< ADC Channel 7 Sampling time selection  */
+#define ADC_SMPR1_SMP7_0                  (0x1UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00200000 */
+#define ADC_SMPR1_SMP7_1                  (0x2UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00400000 */
+#define ADC_SMPR1_SMP7_2                  (0x4UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00800000 */
+
+#define ADC_SMPR1_SMP8_Pos                (24U)
+#define ADC_SMPR1_SMP8_Msk                (0x7UL << ADC_SMPR1_SMP8_Pos)        /*!< 0x07000000 */
+#define ADC_SMPR1_SMP8                    ADC_SMPR1_SMP8_Msk                   /*!< ADC Channel 8 Sampling time selection  */
+#define ADC_SMPR1_SMP8_0                  (0x1UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x01000000 */
+#define ADC_SMPR1_SMP8_1                  (0x2UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x02000000 */
+#define ADC_SMPR1_SMP8_2                  (0x4UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x04000000 */
+
+#define ADC_SMPR1_SMP9_Pos                (27U)
+#define ADC_SMPR1_SMP9_Msk                (0x7UL << ADC_SMPR1_SMP9_Pos)        /*!< 0x38000000 */
+#define ADC_SMPR1_SMP9                    ADC_SMPR1_SMP9_Msk                   /*!< ADC Channel 9 Sampling time selection  */
+#define ADC_SMPR1_SMP9_0                  (0x1UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x08000000 */
+#define ADC_SMPR1_SMP9_1                  (0x2UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x10000000 */
+#define ADC_SMPR1_SMP9_2                  (0x4UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x20000000 */
+
+/********************  Bit definition for ADC_SMPR2 register  ********************/
+#define ADC_SMPR2_SMP10_Pos               (0U)
+#define ADC_SMPR2_SMP10_Msk               (0x7UL << ADC_SMPR2_SMP10_Pos)       /*!< 0x00000007 */
+#define ADC_SMPR2_SMP10                   ADC_SMPR2_SMP10_Msk                  /*!< ADC Channel 10 Sampling time selection  */
+#define ADC_SMPR2_SMP10_0                 (0x1UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000001 */
+#define ADC_SMPR2_SMP10_1                 (0x2UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000002 */
+#define ADC_SMPR2_SMP10_2                 (0x4UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000004 */
+
+#define ADC_SMPR2_SMP11_Pos               (3U)
+#define ADC_SMPR2_SMP11_Msk               (0x7UL << ADC_SMPR2_SMP11_Pos)       /*!< 0x00000038 */
+#define ADC_SMPR2_SMP11                   ADC_SMPR2_SMP11_Msk                  /*!< ADC Channel 11 Sampling time selection  */
+#define ADC_SMPR2_SMP11_0                 (0x1UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000008 */
+#define ADC_SMPR2_SMP11_1                 (0x2UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000010 */
+#define ADC_SMPR2_SMP11_2                 (0x4UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000020 */
+
+#define ADC_SMPR2_SMP12_Pos               (6U)
+#define ADC_SMPR2_SMP12_Msk               (0x7UL << ADC_SMPR2_SMP12_Pos)       /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP12                   ADC_SMPR2_SMP12_Msk                  /*!< ADC Channel 12 Sampling time selection  */
+#define ADC_SMPR2_SMP12_0                 (0x1UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000040 */
+#define ADC_SMPR2_SMP12_1                 (0x2UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000080 */
+#define ADC_SMPR2_SMP12_2                 (0x4UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000100 */
+
+#define ADC_SMPR2_SMP13_Pos               (9U)
+#define ADC_SMPR2_SMP13_Msk               (0x7UL << ADC_SMPR2_SMP13_Pos)       /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP13                   ADC_SMPR2_SMP13_Msk                  /*!< ADC Channel 13 Sampling time selection  */
+#define ADC_SMPR2_SMP13_0                 (0x1UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000200 */
+#define ADC_SMPR2_SMP13_1                 (0x2UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000400 */
+#define ADC_SMPR2_SMP13_2                 (0x4UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000800 */
+
+#define ADC_SMPR2_SMP14_Pos               (12U)
+#define ADC_SMPR2_SMP14_Msk               (0x7UL << ADC_SMPR2_SMP14_Pos)       /*!< 0x00007000 */
+#define ADC_SMPR2_SMP14                   ADC_SMPR2_SMP14_Msk                  /*!< ADC Channel 14 Sampling time selection  */
+#define ADC_SMPR2_SMP14_0                 (0x1UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00001000 */
+#define ADC_SMPR2_SMP14_1                 (0x2UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00002000 */
+#define ADC_SMPR2_SMP14_2                 (0x4UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00004000 */
+
+#define ADC_SMPR2_SMP15_Pos               (15U)
+#define ADC_SMPR2_SMP15_Msk               (0x7UL << ADC_SMPR2_SMP15_Pos)       /*!< 0x00038000 */
+#define ADC_SMPR2_SMP15                   ADC_SMPR2_SMP15_Msk                  /*!< ADC Channel 15 Sampling time selection  */
+#define ADC_SMPR2_SMP15_0                 (0x1UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00008000 */
+#define ADC_SMPR2_SMP15_1                 (0x2UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00010000 */
+#define ADC_SMPR2_SMP15_2                 (0x4UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00020000 */
+
+#define ADC_SMPR2_SMP16_Pos               (18U)
+#define ADC_SMPR2_SMP16_Msk               (0x7UL << ADC_SMPR2_SMP16_Pos)       /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP16                   ADC_SMPR2_SMP16_Msk                  /*!< ADC Channel 16 Sampling time selection  */
+#define ADC_SMPR2_SMP16_0                 (0x1UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00040000 */
+#define ADC_SMPR2_SMP16_1                 (0x2UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00080000 */
+#define ADC_SMPR2_SMP16_2                 (0x4UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00100000 */
+
+#define ADC_SMPR2_SMP17_Pos               (21U)
+#define ADC_SMPR2_SMP17_Msk               (0x7UL << ADC_SMPR2_SMP17_Pos)       /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP17                   ADC_SMPR2_SMP17_Msk                  /*!< ADC Channel 17 Sampling time selection  */
+#define ADC_SMPR2_SMP17_0                 (0x1UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00200000 */
+#define ADC_SMPR2_SMP17_1                 (0x2UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00400000 */
+#define ADC_SMPR2_SMP17_2                 (0x4UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00800000 */
+
+#define ADC_SMPR2_SMP18_Pos               (24U)
+#define ADC_SMPR2_SMP18_Msk               (0x7UL << ADC_SMPR2_SMP18_Pos)       /*!< 0x07000000 */
+#define ADC_SMPR2_SMP18                   ADC_SMPR2_SMP18_Msk                  /*!< ADC Channel 18 Sampling time selection  */
+#define ADC_SMPR2_SMP18_0                 (0x1UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x01000000 */
+#define ADC_SMPR2_SMP18_1                 (0x2UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x02000000 */
+#define ADC_SMPR2_SMP18_2                 (0x4UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x04000000 */
+
+#define ADC_SMPR2_SMP19_Pos               (27U)
+#define ADC_SMPR2_SMP19_Msk               (0x7UL << ADC_SMPR2_SMP19_Pos)       /*!< 0x38000000 */
+#define ADC_SMPR2_SMP19                   ADC_SMPR2_SMP19_Msk                  /*!< ADC Channel 19 Sampling time selection  */
+#define ADC_SMPR2_SMP19_0                 (0x1UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x08000000 */
+#define ADC_SMPR2_SMP19_1                 (0x2UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x10000000 */
+#define ADC_SMPR2_SMP19_2                 (0x4UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x20000000 */
+
+/********************  Bit definition for ADC_PCSEL register  ********************/
+#define ADC_PCSEL_PCSEL_Pos               (0U)
+#define ADC_PCSEL_PCSEL_Msk               (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos)   /*!< 0x000FFFFF */
+#define ADC_PCSEL_PCSEL                   ADC_PCSEL_PCSEL_Msk                  /*!< ADC pre channel selection */
+#define ADC_PCSEL_PCSEL_0                 (0x00001UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000001 */
+#define ADC_PCSEL_PCSEL_1                 (0x00002UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000002 */
+#define ADC_PCSEL_PCSEL_2                 (0x00004UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000004 */
+#define ADC_PCSEL_PCSEL_3                 (0x00008UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000008 */
+#define ADC_PCSEL_PCSEL_4                 (0x00010UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000010 */
+#define ADC_PCSEL_PCSEL_5                 (0x00020UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000020 */
+#define ADC_PCSEL_PCSEL_6                 (0x00040UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000040 */
+#define ADC_PCSEL_PCSEL_7                 (0x00080UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000080 */
+#define ADC_PCSEL_PCSEL_8                 (0x00100UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000100 */
+#define ADC_PCSEL_PCSEL_9                 (0x00200UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000200 */
+#define ADC_PCSEL_PCSEL_10                (0x00400UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000400 */
+#define ADC_PCSEL_PCSEL_11                (0x00800UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000800 */
+#define ADC_PCSEL_PCSEL_12                (0x01000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00001000 */
+#define ADC_PCSEL_PCSEL_13                (0x02000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00002000 */
+#define ADC_PCSEL_PCSEL_14                (0x04000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00004000 */
+#define ADC_PCSEL_PCSEL_15                (0x08000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00008000 */
+#define ADC_PCSEL_PCSEL_16                (0x10000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00010000 */
+#define ADC_PCSEL_PCSEL_17                (0x20000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00020000 */
+#define ADC_PCSEL_PCSEL_18                (0x40000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00040000 */
+#define ADC_PCSEL_PCSEL_19                (0x80000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00080000 */
+
+/*****************  Bit definition for ADC_LTR1, 2, 3 registers *****************/
+#define ADC_LTR_LT_Pos                    (0U)
+#define ADC_LTR_LT_Msk                    (0x3FFFFFFUL << ADC_LTR_LT_Pos)      /*!< 0x03FFFFFF */
+#define ADC_LTR_LT                        ADC_LTR_LT_Msk                       /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */
+
+/*****************  Bit definition for ADC_HTR1, 2, 3 registers  ****************/
+#define ADC_HTR_HT_Pos                    (0U)
+#define ADC_HTR_HT_Msk                    (0x3FFFFFFUL << ADC_HTR_HT_Pos)      /*!< 0x03FFFFFF */
+#define ADC_HTR_HT                        ADC_HTR_HT_Msk                       /*!< ADC Analog watchdog 1,2 and 3 higher threshold */
+
+
+/********************  Bit definition for ADC_SQR1 register  ********************/
+#define ADC_SQR1_L_Pos                    (0U)
+#define ADC_SQR1_L_Msk                    (0xFUL << ADC_SQR1_L_Pos)            /*!< 0x0000000F */
+#define ADC_SQR1_L                        ADC_SQR1_L_Msk                       /*!< ADC regular channel sequence lenght */
+#define ADC_SQR1_L_0                      (0x1UL << ADC_SQR1_L_Pos)             /*!< 0x00000001 */
+#define ADC_SQR1_L_1                      (0x2UL << ADC_SQR1_L_Pos)             /*!< 0x00000002 */
+#define ADC_SQR1_L_2                      (0x4UL << ADC_SQR1_L_Pos)             /*!< 0x00000004 */
+#define ADC_SQR1_L_3                      (0x8UL << ADC_SQR1_L_Pos)             /*!< 0x00000008 */
+
+#define ADC_SQR1_SQ1_Pos                  (6U)
+#define ADC_SQR1_SQ1_Msk                  (0x1FUL << ADC_SQR1_SQ1_Pos)         /*!< 0x000007C0 */
+#define ADC_SQR1_SQ1                      ADC_SQR1_SQ1_Msk                     /*!< ADC 1st conversion in regular sequence */
+#define ADC_SQR1_SQ1_0                    (0x01UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000040 */
+#define ADC_SQR1_SQ1_1                    (0x02UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000080 */
+#define ADC_SQR1_SQ1_2                    (0x04UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000100 */
+#define ADC_SQR1_SQ1_3                    (0x08UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000200 */
+#define ADC_SQR1_SQ1_4                    (0x10UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000400 */
+
+#define ADC_SQR1_SQ2_Pos                  (12U)
+#define ADC_SQR1_SQ2_Msk                  (0x1FUL << ADC_SQR1_SQ2_Pos)         /*!< 0x0001F000 */
+#define ADC_SQR1_SQ2                      ADC_SQR1_SQ2_Msk                     /*!< ADC 2nd conversion in regular sequence */
+#define ADC_SQR1_SQ2_0                    (0x01UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00001000 */
+#define ADC_SQR1_SQ2_1                    (0x02UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00002000 */
+#define ADC_SQR1_SQ2_2                    (0x04UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00004000 */
+#define ADC_SQR1_SQ2_3                    (0x08UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00008000 */
+#define ADC_SQR1_SQ2_4                    (0x10UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00010000 */
+
+#define ADC_SQR1_SQ3_Pos                  (18U)
+#define ADC_SQR1_SQ3_Msk                  (0x1FUL << ADC_SQR1_SQ3_Pos)         /*!< 0x007C0000 */
+#define ADC_SQR1_SQ3                      ADC_SQR1_SQ3_Msk                     /*!< ADC 3rd conversion in regular sequence */
+#define ADC_SQR1_SQ3_0                    (0x01UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00040000 */
+#define ADC_SQR1_SQ3_1                    (0x02UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00080000 */
+#define ADC_SQR1_SQ3_2                    (0x04UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00100000 */
+#define ADC_SQR1_SQ3_3                    (0x08UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00200000 */
+#define ADC_SQR1_SQ3_4                    (0x10UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00400000 */
+
+#define ADC_SQR1_SQ4_Pos                  (24U)
+#define ADC_SQR1_SQ4_Msk                  (0x1FUL << ADC_SQR1_SQ4_Pos)         /*!< 0x1F000000 */
+#define ADC_SQR1_SQ4                      ADC_SQR1_SQ4_Msk                     /*!< ADC 4th conversion in regular sequence */
+#define ADC_SQR1_SQ4_0                    (0x01UL << ADC_SQR1_SQ4_Pos)          /*!< 0x01000000 */
+#define ADC_SQR1_SQ4_1                    (0x02UL << ADC_SQR1_SQ4_Pos)          /*!< 0x02000000 */
+#define ADC_SQR1_SQ4_2                    (0x04UL << ADC_SQR1_SQ4_Pos)          /*!< 0x04000000 */
+#define ADC_SQR1_SQ4_3                    (0x08UL << ADC_SQR1_SQ4_Pos)          /*!< 0x08000000 */
+#define ADC_SQR1_SQ4_4                    (0x10UL << ADC_SQR1_SQ4_Pos)          /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR2 register  ********************/
+#define ADC_SQR2_SQ5_Pos                  (0U)
+#define ADC_SQR2_SQ5_Msk                  (0x1FUL << ADC_SQR2_SQ5_Pos)         /*!< 0x0000001F */
+#define ADC_SQR2_SQ5                      ADC_SQR2_SQ5_Msk                     /*!< ADC 5th conversion in regular sequence */
+#define ADC_SQR2_SQ5_0                    (0x01UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000001 */
+#define ADC_SQR2_SQ5_1                    (0x02UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000002 */
+#define ADC_SQR2_SQ5_2                    (0x04UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000004 */
+#define ADC_SQR2_SQ5_3                    (0x08UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000008 */
+#define ADC_SQR2_SQ5_4                    (0x10UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000010 */
+
+#define ADC_SQR2_SQ6_Pos                  (6U)
+#define ADC_SQR2_SQ6_Msk                  (0x1FUL << ADC_SQR2_SQ6_Pos)         /*!< 0x000007C0 */
+#define ADC_SQR2_SQ6                      ADC_SQR2_SQ6_Msk                     /*!< ADC 6th conversion in regular sequence */
+#define ADC_SQR2_SQ6_0                    (0x01UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000040 */
+#define ADC_SQR2_SQ6_1                    (0x02UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000080 */
+#define ADC_SQR2_SQ6_2                    (0x04UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000100 */
+#define ADC_SQR2_SQ6_3                    (0x08UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000200 */
+#define ADC_SQR2_SQ6_4                    (0x10UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000400 */
+
+#define ADC_SQR2_SQ7_Pos                  (12U)
+#define ADC_SQR2_SQ7_Msk                  (0x1FUL << ADC_SQR2_SQ7_Pos)         /*!< 0x0001F000 */
+#define ADC_SQR2_SQ7                      ADC_SQR2_SQ7_Msk                     /*!< ADC 7th conversion in regular sequence */
+#define ADC_SQR2_SQ7_0                    (0x01UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00001000 */
+#define ADC_SQR2_SQ7_1                    (0x02UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00002000 */
+#define ADC_SQR2_SQ7_2                    (0x04UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00004000 */
+#define ADC_SQR2_SQ7_3                    (0x08UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00008000 */
+#define ADC_SQR2_SQ7_4                    (0x10UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00010000 */
+
+#define ADC_SQR2_SQ8_Pos                  (18U)
+#define ADC_SQR2_SQ8_Msk                  (0x1FUL << ADC_SQR2_SQ8_Pos)         /*!< 0x007C0000 */
+#define ADC_SQR2_SQ8                      ADC_SQR2_SQ8_Msk                     /*!< ADC 8th conversion in regular sequence */
+#define ADC_SQR2_SQ8_0                    (0x01UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00040000 */
+#define ADC_SQR2_SQ8_1                    (0x02UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00080000 */
+#define ADC_SQR2_SQ8_2                    (0x04UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00100000 */
+#define ADC_SQR2_SQ8_3                    (0x08UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00200000 */
+#define ADC_SQR2_SQ8_4                    (0x10UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00400000 */
+
+#define ADC_SQR2_SQ9_Pos                  (24U)
+#define ADC_SQR2_SQ9_Msk                  (0x1FUL << ADC_SQR2_SQ9_Pos)         /*!< 0x1F000000 */
+#define ADC_SQR2_SQ9                      ADC_SQR2_SQ9_Msk                     /*!< ADC 9th conversion in regular sequence */
+#define ADC_SQR2_SQ9_0                    (0x01UL << ADC_SQR2_SQ9_Pos)          /*!< 0x01000000 */
+#define ADC_SQR2_SQ9_1                    (0x02UL << ADC_SQR2_SQ9_Pos)          /*!< 0x02000000 */
+#define ADC_SQR2_SQ9_2                    (0x04UL << ADC_SQR2_SQ9_Pos)          /*!< 0x04000000 */
+#define ADC_SQR2_SQ9_3                    (0x08UL << ADC_SQR2_SQ9_Pos)          /*!< 0x08000000 */
+#define ADC_SQR2_SQ9_4                    (0x10UL << ADC_SQR2_SQ9_Pos)          /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR3 register  ********************/
+#define ADC_SQR3_SQ10_Pos                 (0U)
+#define ADC_SQR3_SQ10_Msk                 (0x1FUL << ADC_SQR3_SQ10_Pos)        /*!< 0x0000001F */
+#define ADC_SQR3_SQ10                     ADC_SQR3_SQ10_Msk                    /*!< ADC 10th conversion in regular sequence */
+#define ADC_SQR3_SQ10_0                   (0x01UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000001 */
+#define ADC_SQR3_SQ10_1                   (0x02UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000002 */
+#define ADC_SQR3_SQ10_2                   (0x04UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000004 */
+#define ADC_SQR3_SQ10_3                   (0x08UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000008 */
+#define ADC_SQR3_SQ10_4                   (0x10UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000010 */
+
+#define ADC_SQR3_SQ11_Pos                 (6U)
+#define ADC_SQR3_SQ11_Msk                 (0x1FUL << ADC_SQR3_SQ11_Pos)        /*!< 0x000007C0 */
+#define ADC_SQR3_SQ11                     ADC_SQR3_SQ11_Msk                    /*!< ADC 11th conversion in regular sequence */
+#define ADC_SQR3_SQ11_0                   (0x01UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000040 */
+#define ADC_SQR3_SQ11_1                   (0x02UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000080 */
+#define ADC_SQR3_SQ11_2                   (0x04UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000100 */
+#define ADC_SQR3_SQ11_3                   (0x08UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000200 */
+#define ADC_SQR3_SQ11_4                   (0x10UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000400 */
+
+#define ADC_SQR3_SQ12_Pos                 (12U)
+#define ADC_SQR3_SQ12_Msk                 (0x1FUL << ADC_SQR3_SQ12_Pos)        /*!< 0x0001F000 */
+#define ADC_SQR3_SQ12                     ADC_SQR3_SQ12_Msk                    /*!< ADC 12th conversion in regular sequence */
+#define ADC_SQR3_SQ12_0                   (0x01UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00001000 */
+#define ADC_SQR3_SQ12_1                   (0x02UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00002000 */
+#define ADC_SQR3_SQ12_2                   (0x04UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00004000 */
+#define ADC_SQR3_SQ12_3                   (0x08UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00008000 */
+#define ADC_SQR3_SQ12_4                   (0x10UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00010000 */
+
+#define ADC_SQR3_SQ13_Pos                 (18U)
+#define ADC_SQR3_SQ13_Msk                 (0x1FUL << ADC_SQR3_SQ13_Pos)        /*!< 0x007C0000 */
+#define ADC_SQR3_SQ13                     ADC_SQR3_SQ13_Msk                    /*!< ADC 13th conversion in regular sequence */
+#define ADC_SQR3_SQ13_0                   (0x01UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00040000 */
+#define ADC_SQR3_SQ13_1                   (0x02UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00080000 */
+#define ADC_SQR3_SQ13_2                   (0x04UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00100000 */
+#define ADC_SQR3_SQ13_3                   (0x08UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00200000 */
+#define ADC_SQR3_SQ13_4                   (0x10UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00400000 */
+
+#define ADC_SQR3_SQ14_Pos                 (24U)
+#define ADC_SQR3_SQ14_Msk                 (0x1FUL << ADC_SQR3_SQ14_Pos)        /*!< 0x1F000000 */
+#define ADC_SQR3_SQ14                     ADC_SQR3_SQ14_Msk                    /*!< ADC 14th conversion in regular sequence */
+#define ADC_SQR3_SQ14_0                   (0x01UL << ADC_SQR3_SQ14_Pos)         /*!< 0x01000000 */
+#define ADC_SQR3_SQ14_1                   (0x02UL << ADC_SQR3_SQ14_Pos)         /*!< 0x02000000 */
+#define ADC_SQR3_SQ14_2                   (0x04UL << ADC_SQR3_SQ14_Pos)         /*!< 0x04000000 */
+#define ADC_SQR3_SQ14_3                   (0x08UL << ADC_SQR3_SQ14_Pos)         /*!< 0x08000000 */
+#define ADC_SQR3_SQ14_4                   (0x10UL << ADC_SQR3_SQ14_Pos)         /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR4 register  ********************/
+#define ADC_SQR4_SQ15_Pos                 (0U)
+#define ADC_SQR4_SQ15_Msk                 (0x1FUL << ADC_SQR4_SQ15_Pos)        /*!< 0x0000001F */
+#define ADC_SQR4_SQ15                     ADC_SQR4_SQ15_Msk                    /*!< ADC 15th conversion in regular sequence */
+#define ADC_SQR4_SQ15_0                   (0x01UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000001 */
+#define ADC_SQR4_SQ15_1                   (0x02UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000002 */
+#define ADC_SQR4_SQ15_2                   (0x04UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000004 */
+#define ADC_SQR4_SQ15_3                   (0x08UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000008 */
+#define ADC_SQR4_SQ15_4                   (0x10UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000010 */
+
+#define ADC_SQR4_SQ16_Pos                 (6U)
+#define ADC_SQR4_SQ16_Msk                 (0x1FUL << ADC_SQR4_SQ16_Pos)        /*!< 0x000007C0 */
+#define ADC_SQR4_SQ16                     ADC_SQR4_SQ16_Msk                    /*!< ADC 16th conversion in regular sequence */
+#define ADC_SQR4_SQ16_0                   (0x01UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000040 */
+#define ADC_SQR4_SQ16_1                   (0x02UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000080 */
+#define ADC_SQR4_SQ16_2                   (0x04UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000100 */
+#define ADC_SQR4_SQ16_3                   (0x08UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000200 */
+#define ADC_SQR4_SQ16_4                   (0x10UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000400 */
+/********************  Bit definition for ADC_DR register  ********************/
+#define ADC_DR_RDATA_Pos                  (0U)
+#define ADC_DR_RDATA_Msk                  (0xFFFFFFFFUL << ADC_DR_RDATA_Pos)   /*!< 0xFFFFFFFF */
+#define ADC_DR_RDATA                      ADC_DR_RDATA_Msk                     /*!< ADC regular Data converted */
+
+/********************  Bit definition for ADC_JSQR register  ********************/
+#define ADC_JSQR_JL_Pos                   (0U)
+#define ADC_JSQR_JL_Msk                   (0x3UL << ADC_JSQR_JL_Pos)           /*!< 0x00000003 */
+#define ADC_JSQR_JL                       ADC_JSQR_JL_Msk                      /*!< ADC injected channel sequence length */
+#define ADC_JSQR_JL_0                     (0x1UL << ADC_JSQR_JL_Pos)           /*!< 0x00000001 */
+#define ADC_JSQR_JL_1                     (0x2UL << ADC_JSQR_JL_Pos)           /*!< 0x00000002 */
+
+#define ADC_JSQR_JEXTSEL_Pos              (2U)
+#define ADC_JSQR_JEXTSEL_Msk              (0x1FUL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x0000007C */
+#define ADC_JSQR_JEXTSEL                  ADC_JSQR_JEXTSEL_Msk                 /*!< ADC external trigger selection for injected group */
+#define ADC_JSQR_JEXTSEL_0                (0x01UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000004 */
+#define ADC_JSQR_JEXTSEL_1                (0x02UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000008 */
+#define ADC_JSQR_JEXTSEL_2                (0x04UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000010 */
+#define ADC_JSQR_JEXTSEL_3                (0x08UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000020 */
+#define ADC_JSQR_JEXTSEL_4                (0x10UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000040 */
+
+#define ADC_JSQR_JEXTEN_Pos               (7U)
+#define ADC_JSQR_JEXTEN_Msk               (0x3UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000180 */
+#define ADC_JSQR_JEXTEN                   ADC_JSQR_JEXTEN_Msk                  /*!< ADC external trigger enable and polarity selection for injected channels */
+#define ADC_JSQR_JEXTEN_0                 (0x1UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000080 */
+#define ADC_JSQR_JEXTEN_1                 (0x2UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000100 */
+
+#define ADC_JSQR_JSQ1_Pos                 (9U)
+#define ADC_JSQR_JSQ1_Msk                 (0x1FUL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00003E00 */
+#define ADC_JSQR_JSQ1                     ADC_JSQR_JSQ1_Msk                    /*!< ADC 1st conversion in injected sequence */
+#define ADC_JSQR_JSQ1_0                   (0x01UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000200 */
+#define ADC_JSQR_JSQ1_1                   (0x02UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000400 */
+#define ADC_JSQR_JSQ1_2                   (0x04UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000800 */
+#define ADC_JSQR_JSQ1_3                   (0x08UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00001000 */
+#define ADC_JSQR_JSQ1_4                   (0x10UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00002000 */
+
+#define ADC_JSQR_JSQ2_Pos                 (15U)
+#define ADC_JSQR_JSQ2_Msk                 (0x1FUL << ADC_JSQR_JSQ2_Pos)        /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ2                     ADC_JSQR_JSQ2_Msk                    /*!< ADC 2nd conversion in injected sequence */
+#define ADC_JSQR_JSQ2_0                   (0x01UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00008000 */
+#define ADC_JSQR_JSQ2_1                   (0x02UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00010000 */
+#define ADC_JSQR_JSQ2_2                   (0x04UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00020000 */
+#define ADC_JSQR_JSQ2_3                   (0x08UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00040000 */
+#define ADC_JSQR_JSQ2_4                   (0x10UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00080000 */
+
+#define ADC_JSQR_JSQ3_Pos                 (21U)
+#define ADC_JSQR_JSQ3_Msk                 (0x1FUL << ADC_JSQR_JSQ3_Pos)        /*!< 0x03E00000 */
+#define ADC_JSQR_JSQ3                     ADC_JSQR_JSQ3_Msk                    /*!< ADC 3rd conversion in injected sequence */
+#define ADC_JSQR_JSQ3_0                   (0x01UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00200000 */
+#define ADC_JSQR_JSQ3_1                   (0x02UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00400000 */
+#define ADC_JSQR_JSQ3_2                   (0x04UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00800000 */
+#define ADC_JSQR_JSQ3_3                   (0x08UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x01000000 */
+#define ADC_JSQR_JSQ3_4                   (0x10UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x02000000 */
+
+#define ADC_JSQR_JSQ4_Pos                 (27U)
+#define ADC_JSQR_JSQ4_Msk                 (0x1FUL << ADC_JSQR_JSQ4_Pos)        /*!< 0xF8000000 */
+#define ADC_JSQR_JSQ4                     ADC_JSQR_JSQ4_Msk                    /*!< ADC 4th conversion in injected sequence */
+#define ADC_JSQR_JSQ4_0                   (0x01UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x08000000 */
+#define ADC_JSQR_JSQ4_1                   (0x02UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x10000000 */
+#define ADC_JSQR_JSQ4_2                   (0x04UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x20000000 */
+#define ADC_JSQR_JSQ4_3                   (0x08UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x40000000 */
+#define ADC_JSQR_JSQ4_4                   (0x10UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_OFR1 register  ********************/
+#define ADC_OFR1_OFFSET1_Pos              (0U)
+#define ADC_OFR1_OFFSET1_Msk              (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */
+#define ADC_OFR1_OFFSET1                  ADC_OFR1_OFFSET1_Msk                  /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
+#define ADC_OFR1_OFFSET1_0                (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
+#define ADC_OFR1_OFFSET1_1                (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
+#define ADC_OFR1_OFFSET1_2                (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
+#define ADC_OFR1_OFFSET1_3                (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
+#define ADC_OFR1_OFFSET1_4                (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
+#define ADC_OFR1_OFFSET1_5                (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
+#define ADC_OFR1_OFFSET1_6                (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
+#define ADC_OFR1_OFFSET1_7                (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
+#define ADC_OFR1_OFFSET1_8                (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
+#define ADC_OFR1_OFFSET1_9                (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
+#define ADC_OFR1_OFFSET1_10               (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
+#define ADC_OFR1_OFFSET1_11               (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
+#define ADC_OFR1_OFFSET1_12               (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */
+#define ADC_OFR1_OFFSET1_13               (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */
+#define ADC_OFR1_OFFSET1_14               (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */
+#define ADC_OFR1_OFFSET1_15               (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */
+#define ADC_OFR1_OFFSET1_16               (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */
+#define ADC_OFR1_OFFSET1_17               (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */
+#define ADC_OFR1_OFFSET1_18               (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */
+#define ADC_OFR1_OFFSET1_19               (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */
+#define ADC_OFR1_OFFSET1_20               (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */
+#define ADC_OFR1_OFFSET1_21               (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */
+#define ADC_OFR1_OFFSET1_22               (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */
+#define ADC_OFR1_OFFSET1_23               (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */
+#define ADC_OFR1_OFFSET1_24               (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */
+#define ADC_OFR1_OFFSET1_25               (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */
+
+#define ADC_OFR1_OFFSET1_CH_Pos           (26U)
+#define ADC_OFR1_OFFSET1_CH_Msk           (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x7C000000 */
+#define ADC_OFR1_OFFSET1_CH               ADC_OFR1_OFFSET1_CH_Msk               /*!< ADC Channel selection for the data offset 1 */
+#define ADC_OFR1_OFFSET1_CH_0             (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x04000000 */
+#define ADC_OFR1_OFFSET1_CH_1             (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x08000000 */
+#define ADC_OFR1_OFFSET1_CH_2             (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x10000000 */
+#define ADC_OFR1_OFFSET1_CH_3             (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x20000000 */
+#define ADC_OFR1_OFFSET1_CH_4             (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x40000000 */
+
+#define ADC_OFR1_SSATE_Pos                (31U)
+#define ADC_OFR1_SSATE_Msk                (0x1UL << ADC_OFR1_SSATE_Pos)         /*!< 0x80000000 */
+#define ADC_OFR1_SSATE                    ADC_OFR1_SSATE_Msk                    /*!< ADC Signed saturation Enable */
+
+
+/********************  Bit definition for ADC_OFR2 register  ********************/
+#define ADC_OFR2_OFFSET2_Pos              (0U)
+#define ADC_OFR2_OFFSET2_Msk              (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */
+#define ADC_OFR2_OFFSET2                  ADC_OFR2_OFFSET2_Msk                  /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
+#define ADC_OFR2_OFFSET2_0                (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
+#define ADC_OFR2_OFFSET2_1                (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
+#define ADC_OFR2_OFFSET2_2                (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
+#define ADC_OFR2_OFFSET2_3                (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
+#define ADC_OFR2_OFFSET2_4                (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
+#define ADC_OFR2_OFFSET2_5                (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
+#define ADC_OFR2_OFFSET2_6                (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
+#define ADC_OFR2_OFFSET2_7                (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
+#define ADC_OFR2_OFFSET2_8                (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
+#define ADC_OFR2_OFFSET2_9                (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
+#define ADC_OFR2_OFFSET2_10               (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
+#define ADC_OFR2_OFFSET2_11               (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
+#define ADC_OFR2_OFFSET2_12               (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */
+#define ADC_OFR2_OFFSET2_13               (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */
+#define ADC_OFR2_OFFSET2_14               (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */
+#define ADC_OFR2_OFFSET2_15               (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */
+#define ADC_OFR2_OFFSET2_16               (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */
+#define ADC_OFR2_OFFSET2_17               (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */
+#define ADC_OFR2_OFFSET2_18               (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */
+#define ADC_OFR2_OFFSET2_19               (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */
+#define ADC_OFR2_OFFSET2_20               (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */
+#define ADC_OFR2_OFFSET2_21               (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */
+#define ADC_OFR2_OFFSET2_22               (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */
+#define ADC_OFR2_OFFSET2_23               (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */
+#define ADC_OFR2_OFFSET2_24               (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */
+#define ADC_OFR2_OFFSET2_25               (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */
+
+#define ADC_OFR2_OFFSET2_CH_Pos           (26U)
+#define ADC_OFR2_OFFSET2_CH_Msk           (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x7C000000 */
+#define ADC_OFR2_OFFSET2_CH               ADC_OFR2_OFFSET2_CH_Msk               /*!< ADC Channel selection for the data offset 2 */
+#define ADC_OFR2_OFFSET2_CH_0             (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x04000000 */
+#define ADC_OFR2_OFFSET2_CH_1             (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x08000000 */
+#define ADC_OFR2_OFFSET2_CH_2             (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x10000000 */
+#define ADC_OFR2_OFFSET2_CH_3             (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x20000000 */
+#define ADC_OFR2_OFFSET2_CH_4             (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x40000000 */
+
+#define ADC_OFR2_SSATE_Pos                (31U)
+#define ADC_OFR2_SSATE_Msk                (0x1UL << ADC_OFR2_SSATE_Pos)         /*!< 0x80000000 */
+#define ADC_OFR2_SSATE                    ADC_OFR2_SSATE_Msk                    /*!< ADC Signed saturation Enable */
+
+
+/********************  Bit definition for ADC_OFR3 register  ********************/
+#define ADC_OFR3_OFFSET3_Pos              (0U)
+#define ADC_OFR3_OFFSET3_Msk              (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */
+#define ADC_OFR3_OFFSET3                  ADC_OFR3_OFFSET3_Msk                  /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
+#define ADC_OFR3_OFFSET3_0                (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
+#define ADC_OFR3_OFFSET3_1                (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
+#define ADC_OFR3_OFFSET3_2                (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
+#define ADC_OFR3_OFFSET3_3                (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
+#define ADC_OFR3_OFFSET3_4                (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
+#define ADC_OFR3_OFFSET3_5                (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
+#define ADC_OFR3_OFFSET3_6                (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
+#define ADC_OFR3_OFFSET3_7                (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
+#define ADC_OFR3_OFFSET3_8                (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
+#define ADC_OFR3_OFFSET3_9                (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
+#define ADC_OFR3_OFFSET3_10               (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
+#define ADC_OFR3_OFFSET3_11               (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
+#define ADC_OFR3_OFFSET3_12               (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */
+#define ADC_OFR3_OFFSET3_13               (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */
+#define ADC_OFR3_OFFSET3_14               (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */
+#define ADC_OFR3_OFFSET3_15               (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */
+#define ADC_OFR3_OFFSET3_16               (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */
+#define ADC_OFR3_OFFSET3_17               (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */
+#define ADC_OFR3_OFFSET3_18               (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */
+#define ADC_OFR3_OFFSET3_19               (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */
+#define ADC_OFR3_OFFSET3_20               (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */
+#define ADC_OFR3_OFFSET3_21               (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */
+#define ADC_OFR3_OFFSET3_22               (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */
+#define ADC_OFR3_OFFSET3_23               (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */
+#define ADC_OFR3_OFFSET3_24               (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */
+#define ADC_OFR3_OFFSET3_25               (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */
+
+#define ADC_OFR3_OFFSET3_CH_Pos           (26U)
+#define ADC_OFR3_OFFSET3_CH_Msk           (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x7C000000 */
+#define ADC_OFR3_OFFSET3_CH               ADC_OFR3_OFFSET3_CH_Msk               /*!< ADC Channel selection for the data offset 3 */
+#define ADC_OFR3_OFFSET3_CH_0             (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x04000000 */
+#define ADC_OFR3_OFFSET3_CH_1             (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x08000000 */
+#define ADC_OFR3_OFFSET3_CH_2             (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x10000000 */
+#define ADC_OFR3_OFFSET3_CH_3             (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x20000000 */
+#define ADC_OFR3_OFFSET3_CH_4             (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x40000000 */
+
+#define ADC_OFR3_SSATE_Pos                (31U)
+#define ADC_OFR3_SSATE_Msk                (0x1UL << ADC_OFR3_SSATE_Pos)         /*!< 0x80000000 */
+#define ADC_OFR3_SSATE                    ADC_OFR3_SSATE_Msk                    /*!< ADC Signed saturation Enable */
+
+
+/********************  Bit definition for ADC_OFR4 register  ********************/
+#define ADC_OFR4_OFFSET4_Pos              (0U)
+#define ADC_OFR4_OFFSET4_Msk              (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */
+#define ADC_OFR4_OFFSET4                  ADC_OFR4_OFFSET4_Msk                  /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
+#define ADC_OFR4_OFFSET4_0                (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
+#define ADC_OFR4_OFFSET4_1                (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
+#define ADC_OFR4_OFFSET4_2                (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
+#define ADC_OFR4_OFFSET4_3                (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
+#define ADC_OFR4_OFFSET4_4                (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
+#define ADC_OFR4_OFFSET4_5                (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
+#define ADC_OFR4_OFFSET4_6                (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
+#define ADC_OFR4_OFFSET4_7                (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
+#define ADC_OFR4_OFFSET4_8                (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
+#define ADC_OFR4_OFFSET4_9                (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
+#define ADC_OFR4_OFFSET4_10               (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
+#define ADC_OFR4_OFFSET4_11               (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
+#define ADC_OFR4_OFFSET4_12               (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */
+#define ADC_OFR4_OFFSET4_13               (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */
+#define ADC_OFR4_OFFSET4_14               (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */
+#define ADC_OFR4_OFFSET4_15               (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */
+#define ADC_OFR4_OFFSET4_16               (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */
+#define ADC_OFR4_OFFSET4_17               (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */
+#define ADC_OFR4_OFFSET4_18               (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */
+#define ADC_OFR4_OFFSET4_19               (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */
+#define ADC_OFR4_OFFSET4_20               (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */
+#define ADC_OFR4_OFFSET4_21               (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */
+#define ADC_OFR4_OFFSET4_22               (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */
+#define ADC_OFR4_OFFSET4_23               (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */
+#define ADC_OFR4_OFFSET4_24               (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */
+#define ADC_OFR4_OFFSET4_25               (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */
+
+#define ADC_OFR4_OFFSET4_CH_Pos           (26U)
+#define ADC_OFR4_OFFSET4_CH_Msk           (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x7C000000 */
+#define ADC_OFR4_OFFSET4_CH               ADC_OFR4_OFFSET4_CH_Msk               /*!< ADC Channel selection for the data offset 4 */
+#define ADC_OFR4_OFFSET4_CH_0             (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x04000000 */
+#define ADC_OFR4_OFFSET4_CH_1             (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x08000000 */
+#define ADC_OFR4_OFFSET4_CH_2             (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x10000000 */
+#define ADC_OFR4_OFFSET4_CH_3             (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x20000000 */
+#define ADC_OFR4_OFFSET4_CH_4             (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x40000000 */
+
+#define ADC_OFR4_SSATE_Pos                (31U)
+#define ADC_OFR4_SSATE_Msk                (0x1UL << ADC_OFR4_SSATE_Pos)         /*!< 0x80000000 */
+#define ADC_OFR4_SSATE                    ADC_OFR4_SSATE_Msk                    /*!< ADC Signed saturation Enable */
+
+
+/********************  Bit definition for ADC_JDR1 register  ********************/
+#define ADC_JDR1_JDATA_Pos                (0U)
+#define ADC_JDR1_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos)  /*!< 0xFFFFFFFF */
+#define ADC_JDR1_JDATA                    ADC_JDR1_JDATA_Msk                    /*!< ADC Injected DATA */
+#define ADC_JDR1_JDATA_0                  (0x00000001UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000001 */
+#define ADC_JDR1_JDATA_1                  (0x00000002UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000002 */
+#define ADC_JDR1_JDATA_2                  (0x00000004UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000004 */
+#define ADC_JDR1_JDATA_3                  (0x00000008UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000008 */
+#define ADC_JDR1_JDATA_4                  (0x00000010UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000010 */
+#define ADC_JDR1_JDATA_5                  (0x00000020UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000020 */
+#define ADC_JDR1_JDATA_6                  (0x00000040UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000040 */
+#define ADC_JDR1_JDATA_7                  (0x00000080UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000080 */
+#define ADC_JDR1_JDATA_8                  (0x00000100UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000100 */
+#define ADC_JDR1_JDATA_9                  (0x00000200UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000200 */
+#define ADC_JDR1_JDATA_10                 (0x00000400UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000400 */
+#define ADC_JDR1_JDATA_11                 (0x00000800UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000800 */
+#define ADC_JDR1_JDATA_12                 (0x00001000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00001000 */
+#define ADC_JDR1_JDATA_13                 (0x00002000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00002000 */
+#define ADC_JDR1_JDATA_14                 (0x00004000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00004000 */
+#define ADC_JDR1_JDATA_15                 (0x00008000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00008000 */
+#define ADC_JDR1_JDATA_16                 (0x00010000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00010000 */
+#define ADC_JDR1_JDATA_17                 (0x00020000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00020000 */
+#define ADC_JDR1_JDATA_18                 (0x00040000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00040000 */
+#define ADC_JDR1_JDATA_19                 (0x00080000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00080000 */
+#define ADC_JDR1_JDATA_20                 (0x00100000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00100000 */
+#define ADC_JDR1_JDATA_21                 (0x00200000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00200000 */
+#define ADC_JDR1_JDATA_22                 (0x00400000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00400000 */
+#define ADC_JDR1_JDATA_23                 (0x00800000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00800000 */
+#define ADC_JDR1_JDATA_24                 (0x01000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x01000000 */
+#define ADC_JDR1_JDATA_25                 (0x02000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x02000000 */
+#define ADC_JDR1_JDATA_26                 (0x04000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x04000000 */
+#define ADC_JDR1_JDATA_27                 (0x08000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x08000000 */
+#define ADC_JDR1_JDATA_28                 (0x10000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x10000000 */
+#define ADC_JDR1_JDATA_29                 (0x20000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x20000000 */
+#define ADC_JDR1_JDATA_30                 (0x40000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x40000000 */
+#define ADC_JDR1_JDATA_31                 (0x80000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_JDR2 register  ********************/
+#define ADC_JDR2_JDATA_Pos                (0U)
+#define ADC_JDR2_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos)  /*!< 0xFFFFFFFF */
+#define ADC_JDR2_JDATA                    ADC_JDR2_JDATA_Msk                    /*!< ADC Injected DATA */
+#define ADC_JDR2_JDATA_0                  (0x00000001UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000001 */
+#define ADC_JDR2_JDATA_1                  (0x00000002UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000002 */
+#define ADC_JDR2_JDATA_2                  (0x00000004UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000004 */
+#define ADC_JDR2_JDATA_3                  (0x00000008UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000008 */
+#define ADC_JDR2_JDATA_4                  (0x00000010UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000010 */
+#define ADC_JDR2_JDATA_5                  (0x00000020UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000020 */
+#define ADC_JDR2_JDATA_6                  (0x00000040UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000040 */
+#define ADC_JDR2_JDATA_7                  (0x00000080UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000080 */
+#define ADC_JDR2_JDATA_8                  (0x00000100UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000100 */
+#define ADC_JDR2_JDATA_9                  (0x00000200UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000200 */
+#define ADC_JDR2_JDATA_10                 (0x00000400UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000400 */
+#define ADC_JDR2_JDATA_11                 (0x00000800UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000800 */
+#define ADC_JDR2_JDATA_12                 (0x00001000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00001000 */
+#define ADC_JDR2_JDATA_13                 (0x00002000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00002000 */
+#define ADC_JDR2_JDATA_14                 (0x00004000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00004000 */
+#define ADC_JDR2_JDATA_15                 (0x00008000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00008000 */
+#define ADC_JDR2_JDATA_16                 (0x00010000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00010000 */
+#define ADC_JDR2_JDATA_17                 (0x00020000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00020000 */
+#define ADC_JDR2_JDATA_18                 (0x00040000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00040000 */
+#define ADC_JDR2_JDATA_19                 (0x00080000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00080000 */
+#define ADC_JDR2_JDATA_20                 (0x00100000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00100000 */
+#define ADC_JDR2_JDATA_21                 (0x00200000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00200000 */
+#define ADC_JDR2_JDATA_22                 (0x00400000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00400000 */
+#define ADC_JDR2_JDATA_23                 (0x00800000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00800000 */
+#define ADC_JDR2_JDATA_24                 (0x01000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x01000000 */
+#define ADC_JDR2_JDATA_25                 (0x02000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x02000000 */
+#define ADC_JDR2_JDATA_26                 (0x04000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x04000000 */
+#define ADC_JDR2_JDATA_27                 (0x08000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x08000000 */
+#define ADC_JDR2_JDATA_28                 (0x10000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x10000000 */
+#define ADC_JDR2_JDATA_29                 (0x20000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x20000000 */
+#define ADC_JDR2_JDATA_30                 (0x40000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x40000000 */
+#define ADC_JDR2_JDATA_31                 (0x80000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_JDR3 register  ********************/
+#define ADC_JDR3_JDATA_Pos                (0U)
+#define ADC_JDR3_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos)  /*!< 0xFFFFFFFF */
+#define ADC_JDR3_JDATA                    ADC_JDR3_JDATA_Msk                    /*!< ADC Injected DATA */
+#define ADC_JDR3_JDATA_0                  (0x00000001UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000001 */
+#define ADC_JDR3_JDATA_1                  (0x00000002UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000002 */
+#define ADC_JDR3_JDATA_2                  (0x00000004UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000004 */
+#define ADC_JDR3_JDATA_3                  (0x00000008UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000008 */
+#define ADC_JDR3_JDATA_4                  (0x00000010UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000010 */
+#define ADC_JDR3_JDATA_5                  (0x00000020UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000020 */
+#define ADC_JDR3_JDATA_6                  (0x00000040UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000040 */
+#define ADC_JDR3_JDATA_7                  (0x00000080UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000080 */
+#define ADC_JDR3_JDATA_8                  (0x00000100UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000100 */
+#define ADC_JDR3_JDATA_9                  (0x00000200UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000200 */
+#define ADC_JDR3_JDATA_10                 (0x00000400UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000400 */
+#define ADC_JDR3_JDATA_11                 (0x00000800UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000800 */
+#define ADC_JDR3_JDATA_12                 (0x00001000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00001000 */
+#define ADC_JDR3_JDATA_13                 (0x00002000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00002000 */
+#define ADC_JDR3_JDATA_14                 (0x00004000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00004000 */
+#define ADC_JDR3_JDATA_15                 (0x00008000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00008000 */
+#define ADC_JDR3_JDATA_16                 (0x00010000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00010000 */
+#define ADC_JDR3_JDATA_17                 (0x00020000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00020000 */
+#define ADC_JDR3_JDATA_18                 (0x00040000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00040000 */
+#define ADC_JDR3_JDATA_19                 (0x00080000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00080000 */
+#define ADC_JDR3_JDATA_20                 (0x00100000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00100000 */
+#define ADC_JDR3_JDATA_21                 (0x00200000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00200000 */
+#define ADC_JDR3_JDATA_22                 (0x00400000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00400000 */
+#define ADC_JDR3_JDATA_23                 (0x00800000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00800000 */
+#define ADC_JDR3_JDATA_24                 (0x01000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x01000000 */
+#define ADC_JDR3_JDATA_25                 (0x02000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x02000000 */
+#define ADC_JDR3_JDATA_26                 (0x04000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x04000000 */
+#define ADC_JDR3_JDATA_27                 (0x08000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x08000000 */
+#define ADC_JDR3_JDATA_28                 (0x10000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x10000000 */
+#define ADC_JDR3_JDATA_29                 (0x20000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x20000000 */
+#define ADC_JDR3_JDATA_30                 (0x40000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x40000000 */
+#define ADC_JDR3_JDATA_31                 (0x80000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_JDR4 register  ********************/
+#define ADC_JDR4_JDATA_Pos                (0U)
+#define ADC_JDR4_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos)  /*!< 0xFFFFFFFF */
+#define ADC_JDR4_JDATA                    ADC_JDR4_JDATA_Msk                    /*!< ADC Injected DATA */
+#define ADC_JDR4_JDATA_0                  (0x00000001UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000001 */
+#define ADC_JDR4_JDATA_1                  (0x00000002UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000002 */
+#define ADC_JDR4_JDATA_2                  (0x00000004UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000004 */
+#define ADC_JDR4_JDATA_3                  (0x00000008UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000008 */
+#define ADC_JDR4_JDATA_4                  (0x00000010UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000010 */
+#define ADC_JDR4_JDATA_5                  (0x00000020UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000020 */
+#define ADC_JDR4_JDATA_6                  (0x00000040UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000040 */
+#define ADC_JDR4_JDATA_7                  (0x00000080UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000080 */
+#define ADC_JDR4_JDATA_8                  (0x00000100UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000100 */
+#define ADC_JDR4_JDATA_9                  (0x00000200UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000200 */
+#define ADC_JDR4_JDATA_10                 (0x00000400UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000400 */
+#define ADC_JDR4_JDATA_11                 (0x00000800UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000800 */
+#define ADC_JDR4_JDATA_12                 (0x00001000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00001000 */
+#define ADC_JDR4_JDATA_13                 (0x00002000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00002000 */
+#define ADC_JDR4_JDATA_14                 (0x00004000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00004000 */
+#define ADC_JDR4_JDATA_15                 (0x00008000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00008000 */
+#define ADC_JDR4_JDATA_16                 (0x00010000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00010000 */
+#define ADC_JDR4_JDATA_17                 (0x00020000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00020000 */
+#define ADC_JDR4_JDATA_18                 (0x00040000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00040000 */
+#define ADC_JDR4_JDATA_19                 (0x00080000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00080000 */
+#define ADC_JDR4_JDATA_20                 (0x00100000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00100000 */
+#define ADC_JDR4_JDATA_21                 (0x00200000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00200000 */
+#define ADC_JDR4_JDATA_22                 (0x00400000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00400000 */
+#define ADC_JDR4_JDATA_23                 (0x00800000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00800000 */
+#define ADC_JDR4_JDATA_24                 (0x01000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x01000000 */
+#define ADC_JDR4_JDATA_25                 (0x02000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x02000000 */
+#define ADC_JDR4_JDATA_26                 (0x04000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x04000000 */
+#define ADC_JDR4_JDATA_27                 (0x08000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x08000000 */
+#define ADC_JDR4_JDATA_28                 (0x10000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x10000000 */
+#define ADC_JDR4_JDATA_29                 (0x20000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x20000000 */
+#define ADC_JDR4_JDATA_30                 (0x40000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x40000000 */
+#define ADC_JDR4_JDATA_31                 (0x80000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_AWD2CR register  ********************/
+#define ADC_AWD2CR_AWD2CH_Pos             (0U)
+#define ADC_AWD2CR_AWD2CH_Msk             (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x000FFFFF */
+#define ADC_AWD2CR_AWD2CH                 ADC_AWD2CR_AWD2CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */
+#define ADC_AWD2CR_AWD2CH_0               (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000001 */
+#define ADC_AWD2CR_AWD2CH_1               (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000002 */
+#define ADC_AWD2CR_AWD2CH_2               (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000004 */
+#define ADC_AWD2CR_AWD2CH_3               (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000008 */
+#define ADC_AWD2CR_AWD2CH_4               (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000010 */
+#define ADC_AWD2CR_AWD2CH_5               (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000020 */
+#define ADC_AWD2CR_AWD2CH_6               (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000040 */
+#define ADC_AWD2CR_AWD2CH_7               (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000080 */
+#define ADC_AWD2CR_AWD2CH_8               (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000100 */
+#define ADC_AWD2CR_AWD2CH_9               (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000200 */
+#define ADC_AWD2CR_AWD2CH_10              (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000400 */
+#define ADC_AWD2CR_AWD2CH_11              (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000800 */
+#define ADC_AWD2CR_AWD2CH_12              (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00001000 */
+#define ADC_AWD2CR_AWD2CH_13              (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00002000 */
+#define ADC_AWD2CR_AWD2CH_14              (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00004000 */
+#define ADC_AWD2CR_AWD2CH_15              (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00008000 */
+#define ADC_AWD2CR_AWD2CH_16              (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00010000 */
+#define ADC_AWD2CR_AWD2CH_17              (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00020000 */
+#define ADC_AWD2CR_AWD2CH_18              (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00040000 */
+#define ADC_AWD2CR_AWD2CH_19              (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00080000 */
+
+/********************  Bit definition for ADC_AWD3CR register  ********************/
+#define ADC_AWD3CR_AWD3CH_Pos             (0U)
+#define ADC_AWD3CR_AWD3CH_Msk             (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x000FFFFF */
+#define ADC_AWD3CR_AWD3CH                 ADC_AWD3CR_AWD3CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */
+#define ADC_AWD3CR_AWD3CH_0               (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000001 */
+#define ADC_AWD3CR_AWD3CH_1               (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000002 */
+#define ADC_AWD3CR_AWD3CH_2               (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000004 */
+#define ADC_AWD3CR_AWD3CH_3               (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000008 */
+#define ADC_AWD3CR_AWD3CH_4               (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000010 */
+#define ADC_AWD3CR_AWD3CH_5               (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000020 */
+#define ADC_AWD3CR_AWD3CH_6               (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000040 */
+#define ADC_AWD3CR_AWD3CH_7               (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000080 */
+#define ADC_AWD3CR_AWD3CH_8               (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000100 */
+#define ADC_AWD3CR_AWD3CH_9               (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000200 */
+#define ADC_AWD3CR_AWD3CH_10              (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000400 */
+#define ADC_AWD3CR_AWD3CH_11              (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000800 */
+#define ADC_AWD3CR_AWD3CH_12              (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00001000 */
+#define ADC_AWD3CR_AWD3CH_13              (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00002000 */
+#define ADC_AWD3CR_AWD3CH_14              (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00004000 */
+#define ADC_AWD3CR_AWD3CH_15              (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00008000 */
+#define ADC_AWD3CR_AWD3CH_16              (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00010000 */
+#define ADC_AWD3CR_AWD3CH_17              (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00020000 */
+#define ADC_AWD3CR_AWD3CH_18              (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00040000 */
+#define ADC_AWD3CR_AWD3CH_19              (0x80000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00080000 */
+
+/********************  Bit definition for ADC_DIFSEL register  ********************/
+#define ADC_DIFSEL_DIFSEL_Pos             (0U)
+#define ADC_DIFSEL_DIFSEL_Msk             (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x000FFFFF */
+#define ADC_DIFSEL_DIFSEL                 ADC_DIFSEL_DIFSEL_Msk                 /*!< ADC differential modes for channels 1 to 18 */
+#define ADC_DIFSEL_DIFSEL_0               (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000001 */
+#define ADC_DIFSEL_DIFSEL_1               (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000002 */
+#define ADC_DIFSEL_DIFSEL_2               (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000004 */
+#define ADC_DIFSEL_DIFSEL_3               (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000008 */
+#define ADC_DIFSEL_DIFSEL_4               (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000010 */
+#define ADC_DIFSEL_DIFSEL_5               (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000020 */
+#define ADC_DIFSEL_DIFSEL_6               (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000040 */
+#define ADC_DIFSEL_DIFSEL_7               (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000080 */
+#define ADC_DIFSEL_DIFSEL_8               (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000100 */
+#define ADC_DIFSEL_DIFSEL_9               (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000200 */
+#define ADC_DIFSEL_DIFSEL_10              (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000400 */
+#define ADC_DIFSEL_DIFSEL_11              (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000800 */
+#define ADC_DIFSEL_DIFSEL_12              (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00001000 */
+#define ADC_DIFSEL_DIFSEL_13              (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00002000 */
+#define ADC_DIFSEL_DIFSEL_14              (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00004000 */
+#define ADC_DIFSEL_DIFSEL_15              (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00008000 */
+#define ADC_DIFSEL_DIFSEL_16              (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00010000 */
+#define ADC_DIFSEL_DIFSEL_17              (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00020000 */
+#define ADC_DIFSEL_DIFSEL_18              (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00040000 */
+#define ADC_DIFSEL_DIFSEL_19              (0x80000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00080000 */
+
+/********************  Bit definition for ADC_CALFACT register  ********************/
+#define ADC_CALFACT_CALFACT_S_Pos         (0U)
+#define ADC_CALFACT_CALFACT_S_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */
+#define ADC_CALFACT_CALFACT_S             ADC_CALFACT_CALFACT_S_Msk              /*!< ADC calibration factors in single-ended mode */
+#define ADC_CALFACT_CALFACT_S_0           (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
+#define ADC_CALFACT_CALFACT_S_1           (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
+#define ADC_CALFACT_CALFACT_S_2           (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
+#define ADC_CALFACT_CALFACT_S_3           (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
+#define ADC_CALFACT_CALFACT_S_4           (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
+#define ADC_CALFACT_CALFACT_S_5           (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
+#define ADC_CALFACT_CALFACT_S_6           (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
+#define ADC_CALFACT_CALFACT_S_7           (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */
+#define ADC_CALFACT_CALFACT_S_8           (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */
+#define ADC_CALFACT_CALFACT_S_9           (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */
+#define ADC_CALFACT_CALFACT_S_10          (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */
+#define ADC_CALFACT_CALFACT_D_Pos         (16U)
+#define ADC_CALFACT_CALFACT_D_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */
+#define ADC_CALFACT_CALFACT_D             ADC_CALFACT_CALFACT_D_Msk              /*!< ADC calibration factors in differential mode */
+#define ADC_CALFACT_CALFACT_D_0           (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
+#define ADC_CALFACT_CALFACT_D_1           (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
+#define ADC_CALFACT_CALFACT_D_2           (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
+#define ADC_CALFACT_CALFACT_D_3           (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
+#define ADC_CALFACT_CALFACT_D_4           (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
+#define ADC_CALFACT_CALFACT_D_5           (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
+#define ADC_CALFACT_CALFACT_D_6           (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
+#define ADC_CALFACT_CALFACT_D_7           (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */
+#define ADC_CALFACT_CALFACT_D_8           (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */
+#define ADC_CALFACT_CALFACT_D_9           (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */
+#define ADC_CALFACT_CALFACT_D_10          (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */
+
+/********************  Bit definition for ADC_CALFACT2 register  ********************/
+#define ADC_CALFACT2_LINCALFACT_Pos       (0U)
+#define ADC_CALFACT2_LINCALFACT_Msk       (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */
+#define ADC_CALFACT2_LINCALFACT           ADC_CALFACT2_LINCALFACT_Msk                   /*!< ADC Linearity calibration factors */
+#define ADC_CALFACT2_LINCALFACT_0         (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */
+#define ADC_CALFACT2_LINCALFACT_1         (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */
+#define ADC_CALFACT2_LINCALFACT_2         (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */
+#define ADC_CALFACT2_LINCALFACT_3         (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */
+#define ADC_CALFACT2_LINCALFACT_4         (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */
+#define ADC_CALFACT2_LINCALFACT_5         (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */
+#define ADC_CALFACT2_LINCALFACT_6         (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */
+#define ADC_CALFACT2_LINCALFACT_7         (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */
+#define ADC_CALFACT2_LINCALFACT_8         (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */
+#define ADC_CALFACT2_LINCALFACT_9         (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */
+#define ADC_CALFACT2_LINCALFACT_10        (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */
+#define ADC_CALFACT2_LINCALFACT_11        (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */
+#define ADC_CALFACT2_LINCALFACT_12        (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */
+#define ADC_CALFACT2_LINCALFACT_13        (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */
+#define ADC_CALFACT2_LINCALFACT_14        (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */
+#define ADC_CALFACT2_LINCALFACT_15        (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */
+#define ADC_CALFACT2_LINCALFACT_16        (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */
+#define ADC_CALFACT2_LINCALFACT_17        (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */
+#define ADC_CALFACT2_LINCALFACT_18        (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */
+#define ADC_CALFACT2_LINCALFACT_19        (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */
+#define ADC_CALFACT2_LINCALFACT_20        (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */
+#define ADC_CALFACT2_LINCALFACT_21        (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */
+#define ADC_CALFACT2_LINCALFACT_22        (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */
+#define ADC_CALFACT2_LINCALFACT_23        (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */
+#define ADC_CALFACT2_LINCALFACT_24        (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */
+#define ADC_CALFACT2_LINCALFACT_25        (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */
+#define ADC_CALFACT2_LINCALFACT_26        (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */
+#define ADC_CALFACT2_LINCALFACT_27        (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */
+#define ADC_CALFACT2_LINCALFACT_28        (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */
+#define ADC_CALFACT2_LINCALFACT_29        (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */
+
+/*************************  ADC Common registers  *****************************/
+/********************  Bit definition for ADC_CSR register  ********************/
+#define ADC_CSR_ADRDY_MST_Pos             (0U)
+#define ADC_CSR_ADRDY_MST_Msk             (0x1UL << ADC_CSR_ADRDY_MST_Pos)     /*!< 0x00000001 */
+#define ADC_CSR_ADRDY_MST                 ADC_CSR_ADRDY_MST_Msk                /*!< Master ADC ready */
+#define ADC_CSR_EOSMP_MST_Pos             (1U)
+#define ADC_CSR_EOSMP_MST_Msk             (0x1UL << ADC_CSR_EOSMP_MST_Pos)     /*!< 0x00000002 */
+#define ADC_CSR_EOSMP_MST                 ADC_CSR_EOSMP_MST_Msk                /*!< End of sampling phase flag of the master ADC */
+#define ADC_CSR_EOC_MST_Pos               (2U)
+#define ADC_CSR_EOC_MST_Msk               (0x1UL << ADC_CSR_EOC_MST_Pos)       /*!< 0x00000004 */
+#define ADC_CSR_EOC_MST                   ADC_CSR_EOC_MST_Msk                  /*!< End of regular conversion of the master ADC */
+#define ADC_CSR_EOS_MST_Pos               (3U)
+#define ADC_CSR_EOS_MST_Msk               (0x1UL << ADC_CSR_EOS_MST_Pos)       /*!< 0x00000008 */
+#define ADC_CSR_EOS_MST                   ADC_CSR_EOS_MST_Msk                  /*!< End of regular sequence flag of the master ADC */
+#define ADC_CSR_OVR_MST_Pos               (4U)
+#define ADC_CSR_OVR_MST_Msk               (0x1UL << ADC_CSR_OVR_MST_Pos)       /*!< 0x00000010 */
+#define ADC_CSR_OVR_MST                   ADC_CSR_OVR_MST_Msk                  /*!< Overrun flag of the master ADC */
+#define ADC_CSR_JEOC_MST_Pos              (5U)
+#define ADC_CSR_JEOC_MST_Msk              (0x1UL << ADC_CSR_JEOC_MST_Pos)      /*!< 0x00000020 */
+#define ADC_CSR_JEOC_MST                  ADC_CSR_JEOC_MST_Msk                 /*!< End of injected conversion of the master ADC */
+#define ADC_CSR_JEOS_MST_Pos              (6U)
+#define ADC_CSR_JEOS_MST_Msk              (0x1UL << ADC_CSR_JEOS_MST_Pos)      /*!< 0x00000040 */
+#define ADC_CSR_JEOS_MST                  ADC_CSR_JEOS_MST_Msk                 /*!< End of injected sequence flag of the master ADC */
+#define ADC_CSR_AWD1_MST_Pos              (7U)
+#define ADC_CSR_AWD1_MST_Msk              (0x1UL << ADC_CSR_AWD1_MST_Pos)      /*!< 0x00000080 */
+#define ADC_CSR_AWD1_MST                  ADC_CSR_AWD1_MST_Msk                 /*!< Analog watchdog 1 flag of the master ADC */
+#define ADC_CSR_AWD2_MST_Pos              (8U)
+#define ADC_CSR_AWD2_MST_Msk              (0x1UL << ADC_CSR_AWD2_MST_Pos)      /*!< 0x00000100 */
+#define ADC_CSR_AWD2_MST                  ADC_CSR_AWD2_MST_Msk                 /*!< Analog watchdog 2 flag of the master ADC */
+#define ADC_CSR_AWD3_MST_Pos              (9U)
+#define ADC_CSR_AWD3_MST_Msk              (0x1UL << ADC_CSR_AWD3_MST_Pos)      /*!< 0x00000200 */
+#define ADC_CSR_AWD3_MST                  ADC_CSR_AWD3_MST_Msk                 /*!< Analog watchdog 3 flag of the master ADC */
+#define ADC_CSR_JQOVF_MST_Pos             (10U)
+#define ADC_CSR_JQOVF_MST_Msk             (0x1UL << ADC_CSR_JQOVF_MST_Pos)     /*!< 0x00000400 */
+#define ADC_CSR_JQOVF_MST                 ADC_CSR_JQOVF_MST_Msk                /*!< Injected context queue overflow flag of the master ADC */
+#define ADC_CSR_ADRDY_SLV_Pos             (16U)
+#define ADC_CSR_ADRDY_SLV_Msk             (0x1UL << ADC_CSR_ADRDY_SLV_Pos)     /*!< 0x00010000 */
+#define ADC_CSR_ADRDY_SLV                 ADC_CSR_ADRDY_SLV_Msk                /*!< Slave ADC ready */
+#define ADC_CSR_EOSMP_SLV_Pos             (17U)
+#define ADC_CSR_EOSMP_SLV_Msk             (0x1UL << ADC_CSR_EOSMP_SLV_Pos)     /*!< 0x00020000 */
+#define ADC_CSR_EOSMP_SLV                 ADC_CSR_EOSMP_SLV_Msk                /*!< End of sampling phase flag of the slave ADC */
+#define ADC_CSR_EOC_SLV_Pos               (18U)
+#define ADC_CSR_EOC_SLV_Msk               (0x1UL << ADC_CSR_EOC_SLV_Pos)       /*!< 0x00040000 */
+#define ADC_CSR_EOC_SLV                   ADC_CSR_EOC_SLV_Msk                  /*!< End of regular conversion of the slave ADC */
+#define ADC_CSR_EOS_SLV_Pos               (19U)
+#define ADC_CSR_EOS_SLV_Msk               (0x1UL << ADC_CSR_EOS_SLV_Pos)       /*!< 0x00080000 */
+#define ADC_CSR_EOS_SLV                   ADC_CSR_EOS_SLV_Msk                  /*!< End of regular sequence flag of the slave ADC */
+#define ADC_CSR_OVR_SLV_Pos               (20U)
+#define ADC_CSR_OVR_SLV_Msk               (0x1UL << ADC_CSR_OVR_SLV_Pos)       /*!< 0x00100000 */
+#define ADC_CSR_OVR_SLV                   ADC_CSR_OVR_SLV_Msk                  /*!< Overrun flag of the slave ADC */
+#define ADC_CSR_JEOC_SLV_Pos              (21U)
+#define ADC_CSR_JEOC_SLV_Msk              (0x1UL << ADC_CSR_JEOC_SLV_Pos)      /*!< 0x00200000 */
+#define ADC_CSR_JEOC_SLV                  ADC_CSR_JEOC_SLV_Msk                 /*!< End of injected conversion of the slave ADC */
+#define ADC_CSR_JEOS_SLV_Pos              (22U)
+#define ADC_CSR_JEOS_SLV_Msk              (0x1UL << ADC_CSR_JEOS_SLV_Pos)      /*!< 0x00400000 */
+#define ADC_CSR_JEOS_SLV                  ADC_CSR_JEOS_SLV_Msk                 /*!< End of injected sequence flag of the slave ADC */
+#define ADC_CSR_AWD1_SLV_Pos              (23U)
+#define ADC_CSR_AWD1_SLV_Msk              (0x1UL << ADC_CSR_AWD1_SLV_Pos)      /*!< 0x00800000 */
+#define ADC_CSR_AWD1_SLV                  ADC_CSR_AWD1_SLV_Msk                 /*!< Analog watchdog 1 flag of the slave ADC */
+#define ADC_CSR_AWD2_SLV_Pos              (24U)
+#define ADC_CSR_AWD2_SLV_Msk              (0x1UL << ADC_CSR_AWD2_SLV_Pos)      /*!< 0x01000000 */
+#define ADC_CSR_AWD2_SLV                  ADC_CSR_AWD2_SLV_Msk                 /*!< Analog watchdog 2 flag of the slave ADC */
+#define ADC_CSR_AWD3_SLV_Pos              (25U)
+#define ADC_CSR_AWD3_SLV_Msk              (0x1UL << ADC_CSR_AWD3_SLV_Pos)      /*!< 0x02000000 */
+#define ADC_CSR_AWD3_SLV                  ADC_CSR_AWD3_SLV_Msk                 /*!< Analog watchdog 3 flag of the slave ADC */
+#define ADC_CSR_JQOVF_SLV_Pos             (26U)
+#define ADC_CSR_JQOVF_SLV_Msk             (0x1UL << ADC_CSR_JQOVF_SLV_Pos)     /*!< 0x04000000 */
+#define ADC_CSR_JQOVF_SLV                 ADC_CSR_JQOVF_SLV_Msk                /*!< Injected context queue overflow flag of the slave ADC */
+
+/********************  Bit definition for ADC_CCR register  ********************/
+#define ADC_CCR_DUAL_Pos                  (0U)
+#define ADC_CCR_DUAL_Msk                  (0x1FUL << ADC_CCR_DUAL_Pos)          /*!< 0x0000001F */
+#define ADC_CCR_DUAL                      ADC_CCR_DUAL_Msk                      /*!< Dual ADC mode selection */
+#define ADC_CCR_DUAL_0                    (0x01UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000001 */
+#define ADC_CCR_DUAL_1                    (0x02UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000002 */
+#define ADC_CCR_DUAL_2                    (0x04UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000004 */
+#define ADC_CCR_DUAL_3                    (0x08UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000008 */
+#define ADC_CCR_DUAL_4                    (0x10UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000010 */
+
+#define ADC_CCR_DELAY_Pos                 (8U)
+#define ADC_CCR_DELAY_Msk                 (0xFUL << ADC_CCR_DELAY_Pos)          /*!< 0x00000F00 */
+#define ADC_CCR_DELAY                     ADC_CCR_DELAY_Msk                     /*!< Delay between 2 sampling phases */
+#define ADC_CCR_DELAY_0                   (0x1UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000100 */
+#define ADC_CCR_DELAY_1                   (0x2UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000200 */
+#define ADC_CCR_DELAY_2                   (0x4UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000400 */
+#define ADC_CCR_DELAY_3                   (0x8UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000800 */
+
+
+#define ADC_CCR_DAMDF_Pos                 (14U)
+#define ADC_CCR_DAMDF_Msk                 (0x3UL << ADC_CCR_DAMDF_Pos)          /*!< 0x0000C000 */
+#define ADC_CCR_DAMDF                     ADC_CCR_DAMDF_Msk                     /*!< Dual ADC mode Data format */
+#define ADC_CCR_DAMDF_0                   (0x1UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00004000 */
+#define ADC_CCR_DAMDF_1                   (0x2UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00008000 */
+
+#define ADC_CCR_CKMODE_Pos                (16U)
+#define ADC_CCR_CKMODE_Msk                (0x3UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00030000 */
+#define ADC_CCR_CKMODE                    ADC_CCR_CKMODE_Msk                    /*!< ADC clock mode */
+#define ADC_CCR_CKMODE_0                  (0x1UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00010000 */
+#define ADC_CCR_CKMODE_1                  (0x2UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00020000 */
+
+#define ADC_CCR_PRESC_Pos                 (18U)
+#define ADC_CCR_PRESC_Msk                 (0xFUL << ADC_CCR_PRESC_Pos)          /*!< 0x003C0000 */
+#define ADC_CCR_PRESC                     ADC_CCR_PRESC_Msk                     /*!< ADC prescaler */
+#define ADC_CCR_PRESC_0                   (0x1UL << ADC_CCR_PRESC_Pos)          /*!< 0x00040000 */
+#define ADC_CCR_PRESC_1                   (0x2UL << ADC_CCR_PRESC_Pos)          /*!< 0x00080000 */
+#define ADC_CCR_PRESC_2                   (0x4UL << ADC_CCR_PRESC_Pos)          /*!< 0x00100000 */
+#define ADC_CCR_PRESC_3                   (0x8UL << ADC_CCR_PRESC_Pos)          /*!< 0x00200000 */
+
+#define ADC_CCR_VREFEN_Pos                (22U)
+#define ADC_CCR_VREFEN_Msk                (0x1UL << ADC_CCR_VREFEN_Pos)         /*!< 0x00400000 */
+#define ADC_CCR_VREFEN                    ADC_CCR_VREFEN_Msk                    /*!< VREFINT enable */
+#define ADC_CCR_TSEN_Pos                  (23U)
+#define ADC_CCR_TSEN_Msk                  (0x1UL << ADC_CCR_TSEN_Pos)           /*!< 0x00800000 */
+#define ADC_CCR_TSEN                      ADC_CCR_TSEN_Msk                      /*!< Temperature sensor enable */
+#define ADC_CCR_VBATEN_Pos                (24U)
+#define ADC_CCR_VBATEN_Msk                (0x1UL << ADC_CCR_VBATEN_Pos)         /*!< 0x01000000 */
+#define ADC_CCR_VBATEN                    ADC_CCR_VBATEN_Msk                    /*!< VBAT enable */
+
+/********************  Bit definition for ADC_CDR register  *******************/
+#define ADC_CDR_RDATA_MST_Pos             (0U)
+#define ADC_CDR_RDATA_MST_Msk             (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)   /*!< 0x0000FFFF */
+#define ADC_CDR_RDATA_MST                 ADC_CDR_RDATA_MST_Msk                 /*!< ADC multimode master group regular conversion data */
+
+#define ADC_CDR_RDATA_SLV_Pos             (16U)
+#define ADC_CDR_RDATA_SLV_Msk             (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)   /*!< 0xFFFF0000 */
+#define ADC_CDR_RDATA_SLV                 ADC_CDR_RDATA_SLV_Msk                 /*!< ADC multimode slave group regular conversion data */
+
+/********************  Bit definition for ADC_CDR2 register  ******************/
+#define ADC_CDR2_RDATA_ALT_Pos            (0U)
+#define ADC_CDR2_RDATA_ALT_Msk            (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */
+#define ADC_CDR2_RDATA_ALT                ADC_CDR2_RDATA_ALT_Msk                   /*!< Regular data of the master/slave alternated ADCs */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                   VREFBUF                                  */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for VREFBUF_CSR register  ****************/
+#define VREFBUF_CSR_ENVR_Pos        (0U)
+#define VREFBUF_CSR_ENVR_Msk        (0x1UL << VREFBUF_CSR_ENVR_Pos)            /*!< 0x00000001 */
+#define VREFBUF_CSR_ENVR            VREFBUF_CSR_ENVR_Msk                       /*!<Voltage reference buffer enable */
+#define VREFBUF_CSR_HIZ_Pos         (1U)
+#define VREFBUF_CSR_HIZ_Msk         (0x1UL << VREFBUF_CSR_HIZ_Pos)             /*!< 0x00000002 */
+#define VREFBUF_CSR_HIZ             VREFBUF_CSR_HIZ_Msk                        /*!<High impedance mode             */
+#define VREFBUF_CSR_VRR_Pos         (3U)
+#define VREFBUF_CSR_VRR_Msk         (0x1UL << VREFBUF_CSR_VRR_Pos)             /*!< 0x00000008 */
+#define VREFBUF_CSR_VRR             VREFBUF_CSR_VRR_Msk                        /*!<Voltage reference buffer ready  */
+#define VREFBUF_CSR_VRS_Pos         (4U)
+#define VREFBUF_CSR_VRS_Msk         (0x7UL << VREFBUF_CSR_VRS_Pos)             /*!< 0x00000070 */
+#define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */
+
+#define VREFBUF_CSR_VRS_OUT1        ((uint32_t)0x00000000)                     /*!<Voltage reference VREF_OUT1     */
+#define VREFBUF_CSR_VRS_OUT2_Pos    (4U)
+#define VREFBUF_CSR_VRS_OUT2_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)        /*!< 0x00000010 */
+#define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */
+#define VREFBUF_CSR_VRS_OUT3_Pos    (5U)
+#define VREFBUF_CSR_VRS_OUT3_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT3_Pos)        /*!< 0x00000020 */
+#define VREFBUF_CSR_VRS_OUT3        VREFBUF_CSR_VRS_OUT3_Msk                   /*!<Voltage reference VREF_OUT3     */
+#define VREFBUF_CSR_VRS_OUT4_Pos    (4U)
+#define VREFBUF_CSR_VRS_OUT4_Msk    (0x3UL << VREFBUF_CSR_VRS_OUT4_Pos)        /*!< 0x00000030 */
+#define VREFBUF_CSR_VRS_OUT4        VREFBUF_CSR_VRS_OUT4_Msk                   /*!<Voltage reference VREF_OUT4     */
+
+/*******************  Bit definition for VREFBUF_CCR register  ****************/
+#define VREFBUF_CCR_TRIM_Pos        (0U)
+#define VREFBUF_CCR_TRIM_Msk        (0x3FUL << VREFBUF_CCR_TRIM_Pos)           /*!< 0x0000003F */
+#define VREFBUF_CCR_TRIM            VREFBUF_CCR_TRIM_Msk                       /*!<TRIM[5:0] bits (Trimming code)  */
+
+/******************************************************************************/
+/*                                                                            */
+/*                 Flexible Datarate Controller Area Network                  */
+/*                                                                            */
+/******************************************************************************/
+/*!<FDCAN control and status registers */
+/*****************  Bit definition for FDCAN_CREL register  *******************/
+#define FDCAN_CREL_DAY_Pos        (0U)
+#define FDCAN_CREL_DAY_Msk        (0xFFUL << FDCAN_CREL_DAY_Pos)               /*!< 0x000000FF */
+#define FDCAN_CREL_DAY            FDCAN_CREL_DAY_Msk                           /*!<Timestamp Day                           */
+#define FDCAN_CREL_MON_Pos        (8U)
+#define FDCAN_CREL_MON_Msk        (0xFFUL << FDCAN_CREL_MON_Pos)               /*!< 0x0000FF00 */
+#define FDCAN_CREL_MON            FDCAN_CREL_MON_Msk                           /*!<Timestamp Month                         */
+#define FDCAN_CREL_YEAR_Pos       (16U)
+#define FDCAN_CREL_YEAR_Msk       (0xFUL << FDCAN_CREL_YEAR_Pos)               /*!< 0x000F0000 */
+#define FDCAN_CREL_YEAR           FDCAN_CREL_YEAR_Msk                          /*!<Timestamp Year                          */
+#define FDCAN_CREL_SUBSTEP_Pos    (20U)
+#define FDCAN_CREL_SUBSTEP_Msk    (0xFUL << FDCAN_CREL_SUBSTEP_Pos)            /*!< 0x00F00000 */
+#define FDCAN_CREL_SUBSTEP        FDCAN_CREL_SUBSTEP_Msk                       /*!<Sub-step of Core release                */
+#define FDCAN_CREL_STEP_Pos       (24U)
+#define FDCAN_CREL_STEP_Msk       (0xFUL << FDCAN_CREL_STEP_Pos)               /*!< 0x0F000000 */
+#define FDCAN_CREL_STEP           FDCAN_CREL_STEP_Msk                          /*!<Step of Core release                    */
+#define FDCAN_CREL_REL_Pos        (28U)
+#define FDCAN_CREL_REL_Msk        (0xFUL << FDCAN_CREL_REL_Pos)                /*!< 0xF0000000 */
+#define FDCAN_CREL_REL            FDCAN_CREL_REL_Msk                           /*!<Core release                            */
+
+/*****************  Bit definition for FDCAN_ENDN register  *******************/
+#define FDCAN_ENDN_ETV_Pos        (0U)
+#define FDCAN_ENDN_ETV_Msk        (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)         /*!< 0xFFFFFFFF */
+#define FDCAN_ENDN_ETV            FDCAN_ENDN_ETV_Msk                           /*!<Endiannes Test Value                    */
+
+/*****************  Bit definition for FDCAN_DBTP register  *******************/
+#define FDCAN_DBTP_DSJW_Pos       (0U)
+#define FDCAN_DBTP_DSJW_Msk       (0xFUL << FDCAN_DBTP_DSJW_Pos)               /*!< 0x0000000F */
+#define FDCAN_DBTP_DSJW           FDCAN_DBTP_DSJW_Msk                          /*!<Synchronization Jump Width              */
+#define FDCAN_DBTP_DTSEG2_Pos     (4U)
+#define FDCAN_DBTP_DTSEG2_Msk     (0xFUL << FDCAN_DBTP_DTSEG2_Pos)             /*!< 0x000000F0 */
+#define FDCAN_DBTP_DTSEG2         FDCAN_DBTP_DTSEG2_Msk                        /*!<Data time segment after sample point    */
+#define FDCAN_DBTP_DTSEG1_Pos     (8U)
+#define FDCAN_DBTP_DTSEG1_Msk     (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)            /*!< 0x00001F00 */
+#define FDCAN_DBTP_DTSEG1         FDCAN_DBTP_DTSEG1_Msk                        /*!<Data time segment before sample point   */
+#define FDCAN_DBTP_DBRP_Pos       (16U)
+#define FDCAN_DBTP_DBRP_Msk       (0x1FUL << FDCAN_DBTP_DBRP_Pos)              /*!< 0x001F0000 */
+#define FDCAN_DBTP_DBRP           FDCAN_DBTP_DBRP_Msk                          /*!<Data BIt Rate Prescaler                 */
+#define FDCAN_DBTP_TDC_Pos        (23U)
+#define FDCAN_DBTP_TDC_Msk        (0x1UL << FDCAN_DBTP_TDC_Pos)                /*!< 0x00800000 */
+#define FDCAN_DBTP_TDC            FDCAN_DBTP_TDC_Msk                           /*!<Transceiver Delay Compensation          */
+
+/*****************  Bit definition for FDCAN_TEST register  *******************/
+#define FDCAN_TEST_LBCK_Pos       (4U)
+#define FDCAN_TEST_LBCK_Msk       (0x1UL << FDCAN_TEST_LBCK_Pos)               /*!< 0x00000010 */
+#define FDCAN_TEST_LBCK           FDCAN_TEST_LBCK_Msk                          /*!<Loop Back mode                           */
+#define FDCAN_TEST_TX_Pos         (5U)
+#define FDCAN_TEST_TX_Msk         (0x3UL << FDCAN_TEST_TX_Pos)                 /*!< 0x00000060 */
+#define FDCAN_TEST_TX             FDCAN_TEST_TX_Msk                            /*!<Control of Transmit Pin                  */
+#define FDCAN_TEST_RX_Pos         (7U)
+#define FDCAN_TEST_RX_Msk         (0x1UL << FDCAN_TEST_RX_Pos)                 /*!< 0x00000080 */
+#define FDCAN_TEST_RX             FDCAN_TEST_RX_Msk                            /*!<Receive Pin                              */
+
+/*****************  Bit definition for FDCAN_RWD register  ********************/
+#define FDCAN_RWD_WDC_Pos         (0U)
+#define FDCAN_RWD_WDC_Msk         (0xFFUL << FDCAN_RWD_WDC_Pos)                /*!< 0x000000FF */
+#define FDCAN_RWD_WDC             FDCAN_RWD_WDC_Msk                            /*!<Watchdog configuration                   */
+#define FDCAN_RWD_WDV_Pos         (8U)
+#define FDCAN_RWD_WDV_Msk         (0xFFUL << FDCAN_RWD_WDV_Pos)                /*!< 0x0000FF00 */
+#define FDCAN_RWD_WDV             FDCAN_RWD_WDV_Msk                            /*!<Watchdog value                           */
+
+/*****************  Bit definition for FDCAN_CCCR register  ********************/
+#define FDCAN_CCCR_INIT_Pos       (0U)
+#define FDCAN_CCCR_INIT_Msk       (0x1UL << FDCAN_CCCR_INIT_Pos)               /*!< 0x00000001 */
+#define FDCAN_CCCR_INIT           FDCAN_CCCR_INIT_Msk                          /*!<Initialization                           */
+#define FDCAN_CCCR_CCE_Pos        (1U)
+#define FDCAN_CCCR_CCE_Msk        (0x1UL << FDCAN_CCCR_CCE_Pos)                /*!< 0x00000002 */
+#define FDCAN_CCCR_CCE            FDCAN_CCCR_CCE_Msk                           /*!<Configuration Change Enable              */
+#define FDCAN_CCCR_ASM_Pos        (2U)
+#define FDCAN_CCCR_ASM_Msk        (0x1UL << FDCAN_CCCR_ASM_Pos)                /*!< 0x00000004 */
+#define FDCAN_CCCR_ASM            FDCAN_CCCR_ASM_Msk                           /*!<ASM Restricted Operation Mode            */
+#define FDCAN_CCCR_CSA_Pos        (3U)
+#define FDCAN_CCCR_CSA_Msk        (0x1UL << FDCAN_CCCR_CSA_Pos)                /*!< 0x00000008 */
+#define FDCAN_CCCR_CSA            FDCAN_CCCR_CSA_Msk                           /*!<Clock Stop Acknowledge                   */
+#define FDCAN_CCCR_CSR_Pos        (4U)
+#define FDCAN_CCCR_CSR_Msk        (0x1UL << FDCAN_CCCR_CSR_Pos)                /*!< 0x00000010 */
+#define FDCAN_CCCR_CSR            FDCAN_CCCR_CSR_Msk                           /*!<Clock Stop Request                       */
+#define FDCAN_CCCR_MON_Pos        (5U)
+#define FDCAN_CCCR_MON_Msk        (0x1UL << FDCAN_CCCR_MON_Pos)                /*!< 0x00000020 */
+#define FDCAN_CCCR_MON            FDCAN_CCCR_MON_Msk                           /*!<Bus Monitoring Mode                      */
+#define FDCAN_CCCR_DAR_Pos        (6U)
+#define FDCAN_CCCR_DAR_Msk        (0x1UL << FDCAN_CCCR_DAR_Pos)                /*!< 0x00000040 */
+#define FDCAN_CCCR_DAR            FDCAN_CCCR_DAR_Msk                           /*!<Disable Automatic Retransmission         */
+#define FDCAN_CCCR_TEST_Pos       (7U)
+#define FDCAN_CCCR_TEST_Msk       (0x1UL << FDCAN_CCCR_TEST_Pos)               /*!< 0x00000080 */
+#define FDCAN_CCCR_TEST           FDCAN_CCCR_TEST_Msk                          /*!<Test Mode Enable                         */
+#define FDCAN_CCCR_FDOE_Pos       (8U)
+#define FDCAN_CCCR_FDOE_Msk       (0x1UL << FDCAN_CCCR_FDOE_Pos)               /*!< 0x00000100 */
+#define FDCAN_CCCR_FDOE           FDCAN_CCCR_FDOE_Msk                          /*!<FD Operation Enable                      */
+#define FDCAN_CCCR_BRSE_Pos       (9U)
+#define FDCAN_CCCR_BRSE_Msk       (0x1UL << FDCAN_CCCR_BRSE_Pos)               /*!< 0x00000200 */
+#define FDCAN_CCCR_BRSE           FDCAN_CCCR_BRSE_Msk                          /*!<FDCAN Bit Rate Switching                 */
+#define FDCAN_CCCR_PXHD_Pos       (12U)
+#define FDCAN_CCCR_PXHD_Msk       (0x1UL << FDCAN_CCCR_PXHD_Pos)               /*!< 0x00001000 */
+#define FDCAN_CCCR_PXHD           FDCAN_CCCR_PXHD_Msk                          /*!<Protocol Exception Handling Disable      */
+#define FDCAN_CCCR_EFBI_Pos       (13U)
+#define FDCAN_CCCR_EFBI_Msk       (0x1UL << FDCAN_CCCR_EFBI_Pos)               /*!< 0x00002000 */
+#define FDCAN_CCCR_EFBI           FDCAN_CCCR_EFBI_Msk                          /*!<Edge Filtering during Bus Integration    */
+#define FDCAN_CCCR_TXP_Pos        (14U)
+#define FDCAN_CCCR_TXP_Msk        (0x1UL << FDCAN_CCCR_TXP_Pos)                /*!< 0x00004000 */
+#define FDCAN_CCCR_TXP            FDCAN_CCCR_TXP_Msk                           /*!<Two CAN bit times Pause                  */
+#define FDCAN_CCCR_NISO_Pos       (15U)
+#define FDCAN_CCCR_NISO_Msk       (0x1UL << FDCAN_CCCR_NISO_Pos)               /*!< 0x00008000 */
+#define FDCAN_CCCR_NISO           FDCAN_CCCR_NISO_Msk                          /*!<Non ISO Operation                        */
+
+/*****************  Bit definition for FDCAN_NBTP register  ********************/
+#define FDCAN_NBTP_NTSEG2_Pos     (0U)
+#define FDCAN_NBTP_NTSEG2_Msk     (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)            /*!< 0x0000007F */
+#define FDCAN_NBTP_NTSEG2         FDCAN_NBTP_NTSEG2_Msk                        /*!<Nominal Time segment after sample point  */
+#define FDCAN_NBTP_NTSEG1_Pos     (8U)
+#define FDCAN_NBTP_NTSEG1_Msk     (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)            /*!< 0x0000FF00 */
+#define FDCAN_NBTP_NTSEG1         FDCAN_NBTP_NTSEG1_Msk                        /*!<Nominal Time segment before sample point */
+#define FDCAN_NBTP_NBRP_Pos       (16U)
+#define FDCAN_NBTP_NBRP_Msk       (0x1FFUL << FDCAN_NBTP_NBRP_Pos)             /*!< 0x01FF0000 */
+#define FDCAN_NBTP_NBRP           FDCAN_NBTP_NBRP_Msk                          /*!<Bit Rate Prescaler                       */
+#define FDCAN_NBTP_NSJW_Pos       (25U)
+#define FDCAN_NBTP_NSJW_Msk       (0x7FUL << FDCAN_NBTP_NSJW_Pos)              /*!< 0xFE000000 */
+#define FDCAN_NBTP_NSJW           FDCAN_NBTP_NSJW_Msk                          /*!<Nominal (Re)Synchronization Jump Width   */
+
+/*****************  Bit definition for FDCAN_TSCC register  ********************/
+#define FDCAN_TSCC_TSS_Pos        (0U)
+#define FDCAN_TSCC_TSS_Msk        (0x3UL << FDCAN_TSCC_TSS_Pos)                /*!< 0x00000003 */
+#define FDCAN_TSCC_TSS            FDCAN_TSCC_TSS_Msk                           /*!<Timestamp Select                         */
+#define FDCAN_TSCC_TCP_Pos        (16U)
+#define FDCAN_TSCC_TCP_Msk        (0xFUL << FDCAN_TSCC_TCP_Pos)                /*!< 0x000F0000 */
+#define FDCAN_TSCC_TCP            FDCAN_TSCC_TCP_Msk                           /*!<Timestamp Counter Prescaler              */
+
+/*****************  Bit definition for FDCAN_TSCV register  ********************/
+#define FDCAN_TSCV_TSC_Pos        (0U)
+#define FDCAN_TSCV_TSC_Msk        (0xFFFFUL << FDCAN_TSCV_TSC_Pos)             /*!< 0x0000FFFF */
+#define FDCAN_TSCV_TSC            FDCAN_TSCV_TSC_Msk                           /*!<Timestamp Counter                        */
+
+/*****************  Bit definition for FDCAN_TOCC register  ********************/
+#define FDCAN_TOCC_ETOC_Pos       (0U)
+#define FDCAN_TOCC_ETOC_Msk       (0x1UL << FDCAN_TOCC_ETOC_Pos)               /*!< 0x00000001 */
+#define FDCAN_TOCC_ETOC           FDCAN_TOCC_ETOC_Msk                          /*!<Enable Timeout Counter                   */
+#define FDCAN_TOCC_TOS_Pos        (1U)
+#define FDCAN_TOCC_TOS_Msk        (0x3UL << FDCAN_TOCC_TOS_Pos)                /*!< 0x00000006 */
+#define FDCAN_TOCC_TOS            FDCAN_TOCC_TOS_Msk                           /*!<Timeout Select                           */
+#define FDCAN_TOCC_TOP_Pos        (16U)
+#define FDCAN_TOCC_TOP_Msk        (0xFFFFUL << FDCAN_TOCC_TOP_Pos)             /*!< 0xFFFF0000 */
+#define FDCAN_TOCC_TOP            FDCAN_TOCC_TOP_Msk                           /*!<Timeout Period                           */
+
+/*****************  Bit definition for FDCAN_TOCV register  ********************/
+#define FDCAN_TOCV_TOC_Pos        (0U)
+#define FDCAN_TOCV_TOC_Msk        (0xFFFFUL << FDCAN_TOCV_TOC_Pos)             /*!< 0x0000FFFF */
+#define FDCAN_TOCV_TOC            FDCAN_TOCV_TOC_Msk                           /*!<Timeout Counter                          */
+
+/*****************  Bit definition for FDCAN_ECR register  *********************/
+#define FDCAN_ECR_TEC_Pos         (0U)
+#define FDCAN_ECR_TEC_Msk         (0xFUL << FDCAN_ECR_TEC_Pos)                 /*!< 0x0000000F */
+#define FDCAN_ECR_TEC             FDCAN_ECR_TEC_Msk                            /*!<Transmit Error Counter                   */
+#define FDCAN_ECR_REC_Pos         (8U)
+#define FDCAN_ECR_REC_Msk         (0x7FUL << FDCAN_ECR_REC_Pos)                /*!< 0x00007F00 */
+#define FDCAN_ECR_REC             FDCAN_ECR_REC_Msk                            /*!<Receive Error Counter                    */
+#define FDCAN_ECR_RP_Pos          (15U)
+#define FDCAN_ECR_RP_Msk          (0x1UL << FDCAN_ECR_RP_Pos)                  /*!< 0x00008000 */
+#define FDCAN_ECR_RP              FDCAN_ECR_RP_Msk                             /*!<Receive Error Passive                    */
+#define FDCAN_ECR_CEL_Pos         (16U)
+#define FDCAN_ECR_CEL_Msk         (0xFFUL << FDCAN_ECR_CEL_Pos)                /*!< 0x00FF0000 */
+#define FDCAN_ECR_CEL             FDCAN_ECR_CEL_Msk                            /*!<CAN Error Logging                        */
+
+/*****************  Bit definition for FDCAN_PSR register  *********************/
+#define FDCAN_PSR_LEC_Pos         (0U)
+#define FDCAN_PSR_LEC_Msk         (0x7UL << FDCAN_PSR_LEC_Pos)                 /*!< 0x00000007 */
+#define FDCAN_PSR_LEC             FDCAN_PSR_LEC_Msk                            /*!<Last Error Code                          */
+#define FDCAN_PSR_ACT_Pos         (3U)
+#define FDCAN_PSR_ACT_Msk         (0x3UL << FDCAN_PSR_ACT_Pos)                 /*!< 0x00000018 */
+#define FDCAN_PSR_ACT             FDCAN_PSR_ACT_Msk                            /*!<Activity                                 */
+#define FDCAN_PSR_EP_Pos          (5U)
+#define FDCAN_PSR_EP_Msk          (0x1UL << FDCAN_PSR_EP_Pos)                  /*!< 0x00000020 */
+#define FDCAN_PSR_EP              FDCAN_PSR_EP_Msk                             /*!<Error Passive                            */
+#define FDCAN_PSR_EW_Pos          (6U)
+#define FDCAN_PSR_EW_Msk          (0x1UL << FDCAN_PSR_EW_Pos)                  /*!< 0x00000040 */
+#define FDCAN_PSR_EW              FDCAN_PSR_EW_Msk                             /*!<Warning Status                           */
+#define FDCAN_PSR_BO_Pos          (7U)
+#define FDCAN_PSR_BO_Msk          (0x1UL << FDCAN_PSR_BO_Pos)                  /*!< 0x00000080 */
+#define FDCAN_PSR_BO              FDCAN_PSR_BO_Msk                             /*!<Bus_Off Status                           */
+#define FDCAN_PSR_DLEC_Pos        (8U)
+#define FDCAN_PSR_DLEC_Msk        (0x7UL << FDCAN_PSR_DLEC_Pos)                /*!< 0x00000700 */
+#define FDCAN_PSR_DLEC            FDCAN_PSR_DLEC_Msk                           /*!<Data Last Error Code                     */
+#define FDCAN_PSR_RESI_Pos        (11U)
+#define FDCAN_PSR_RESI_Msk        (0x1UL << FDCAN_PSR_RESI_Pos)                /*!< 0x00000800 */
+#define FDCAN_PSR_RESI            FDCAN_PSR_RESI_Msk                           /*!<ESI flag of last received FDCAN Message  */
+#define FDCAN_PSR_RBRS_Pos        (12U)
+#define FDCAN_PSR_RBRS_Msk        (0x1UL << FDCAN_PSR_RBRS_Pos)                /*!< 0x00001000 */
+#define FDCAN_PSR_RBRS            FDCAN_PSR_RBRS_Msk                           /*!<BRS flag of last received FDCAN Message  */
+#define FDCAN_PSR_REDL_Pos        (13U)
+#define FDCAN_PSR_REDL_Msk        (0x1UL << FDCAN_PSR_REDL_Pos)                /*!< 0x00002000 */
+#define FDCAN_PSR_REDL            FDCAN_PSR_REDL_Msk                           /*!<Received FDCAN Message                   */
+#define FDCAN_PSR_PXE_Pos         (14U)
+#define FDCAN_PSR_PXE_Msk         (0x1UL << FDCAN_PSR_PXE_Pos)                 /*!< 0x00004000 */
+#define FDCAN_PSR_PXE             FDCAN_PSR_PXE_Msk                            /*!<Protocol Exception Event                 */
+#define FDCAN_PSR_TDCV_Pos        (16U)
+#define FDCAN_PSR_TDCV_Msk        (0x7FUL << FDCAN_PSR_TDCV_Pos)               /*!< 0x007F0000 */
+#define FDCAN_PSR_TDCV            FDCAN_PSR_TDCV_Msk                           /*!<Transmitter Delay Compensation Value     */
+
+/*****************  Bit definition for FDCAN_TDCR register  ********************/
+#define FDCAN_TDCR_TDCF_Pos       (0U)
+#define FDCAN_TDCR_TDCF_Msk       (0x7FUL << FDCAN_TDCR_TDCF_Pos)              /*!< 0x0000007F */
+#define FDCAN_TDCR_TDCF           FDCAN_TDCR_TDCF_Msk                          /*!<Transmitter Delay Compensation Filter    */
+#define FDCAN_TDCR_TDCO_Pos       (8U)
+#define FDCAN_TDCR_TDCO_Msk       (0x7FUL << FDCAN_TDCR_TDCO_Pos)              /*!< 0x00007F00 */
+#define FDCAN_TDCR_TDCO           FDCAN_TDCR_TDCO_Msk                          /*!<Transmitter Delay Compensation Offset    */
+
+/*****************  Bit definition for FDCAN_IR register  **********************/
+#define FDCAN_IR_RF0N_Pos         (0U)
+#define FDCAN_IR_RF0N_Msk         (0x1UL << FDCAN_IR_RF0N_Pos)                 /*!< 0x00000001 */
+#define FDCAN_IR_RF0N             FDCAN_IR_RF0N_Msk                            /*!<Rx FIFO 0 New Message                    */
+#define FDCAN_IR_RF0W_Pos         (1U)
+#define FDCAN_IR_RF0W_Msk         (0x1UL << FDCAN_IR_RF0W_Pos)                 /*!< 0x00000002 */
+#define FDCAN_IR_RF0W             FDCAN_IR_RF0W_Msk                            /*!<Rx FIFO 0 Watermark Reached              */
+#define FDCAN_IR_RF0F_Pos         (2U)
+#define FDCAN_IR_RF0F_Msk         (0x1UL << FDCAN_IR_RF0F_Pos)                 /*!< 0x00000004 */
+#define FDCAN_IR_RF0F             FDCAN_IR_RF0F_Msk                            /*!<Rx FIFO 0 Full                           */
+#define FDCAN_IR_RF0L_Pos         (3U)
+#define FDCAN_IR_RF0L_Msk         (0x1UL << FDCAN_IR_RF0L_Pos)                 /*!< 0x00000008 */
+#define FDCAN_IR_RF0L             FDCAN_IR_RF0L_Msk                            /*!<Rx FIFO 0 Message Lost                   */
+#define FDCAN_IR_RF1N_Pos         (4U)
+#define FDCAN_IR_RF1N_Msk         (0x1UL << FDCAN_IR_RF1N_Pos)                 /*!< 0x00000010 */
+#define FDCAN_IR_RF1N             FDCAN_IR_RF1N_Msk                            /*!<Rx FIFO 1 New Message                    */
+#define FDCAN_IR_RF1W_Pos         (5U)
+#define FDCAN_IR_RF1W_Msk         (0x1UL << FDCAN_IR_RF1W_Pos)                 /*!< 0x00000020 */
+#define FDCAN_IR_RF1W             FDCAN_IR_RF1W_Msk                            /*!<Rx FIFO 1 Watermark Reached              */
+#define FDCAN_IR_RF1F_Pos         (6U)
+#define FDCAN_IR_RF1F_Msk         (0x1UL << FDCAN_IR_RF1F_Pos)                 /*!< 0x00000040 */
+#define FDCAN_IR_RF1F             FDCAN_IR_RF1F_Msk                            /*!<Rx FIFO 1 Full                           */
+#define FDCAN_IR_RF1L_Pos         (7U)
+#define FDCAN_IR_RF1L_Msk         (0x1UL << FDCAN_IR_RF1L_Pos)                 /*!< 0x00000080 */
+#define FDCAN_IR_RF1L             FDCAN_IR_RF1L_Msk                            /*!<Rx FIFO 1 Message Lost                   */
+#define FDCAN_IR_HPM_Pos          (8U)
+#define FDCAN_IR_HPM_Msk          (0x1UL << FDCAN_IR_HPM_Pos)                  /*!< 0x00000100 */
+#define FDCAN_IR_HPM              FDCAN_IR_HPM_Msk                             /*!<High Priority Message                    */
+#define FDCAN_IR_TC_Pos           (9U)
+#define FDCAN_IR_TC_Msk           (0x1UL << FDCAN_IR_TC_Pos)                   /*!< 0x00000200 */
+#define FDCAN_IR_TC               FDCAN_IR_TC_Msk                              /*!<Transmission Completed                   */
+#define FDCAN_IR_TCF_Pos          (10U)
+#define FDCAN_IR_TCF_Msk          (0x1UL << FDCAN_IR_TCF_Pos)                  /*!< 0x00000400 */
+#define FDCAN_IR_TCF              FDCAN_IR_TCF_Msk                             /*!<Transmission Cancellation Finished       */
+#define FDCAN_IR_TFE_Pos          (11U)
+#define FDCAN_IR_TFE_Msk          (0x1UL << FDCAN_IR_TFE_Pos)                  /*!< 0x00000800 */
+#define FDCAN_IR_TFE              FDCAN_IR_TFE_Msk                             /*!<Tx FIFO Empty                            */
+#define FDCAN_IR_TEFN_Pos         (12U)
+#define FDCAN_IR_TEFN_Msk         (0x1UL << FDCAN_IR_TEFN_Pos)                 /*!< 0x00001000 */
+#define FDCAN_IR_TEFN             FDCAN_IR_TEFN_Msk                            /*!<Tx Event FIFO New Entry                  */
+#define FDCAN_IR_TEFW_Pos         (13U)
+#define FDCAN_IR_TEFW_Msk         (0x1UL << FDCAN_IR_TEFW_Pos)                 /*!< 0x00002000 */
+#define FDCAN_IR_TEFW             FDCAN_IR_TEFW_Msk                            /*!<Tx Event FIFO Watermark Reached          */
+#define FDCAN_IR_TEFF_Pos         (14U)
+#define FDCAN_IR_TEFF_Msk         (0x1UL << FDCAN_IR_TEFF_Pos)                 /*!< 0x00004000 */
+#define FDCAN_IR_TEFF             FDCAN_IR_TEFF_Msk                            /*!<Tx Event FIFO Full                       */
+#define FDCAN_IR_TEFL_Pos         (15U)
+#define FDCAN_IR_TEFL_Msk         (0x1UL << FDCAN_IR_TEFL_Pos)                 /*!< 0x00008000 */
+#define FDCAN_IR_TEFL             FDCAN_IR_TEFL_Msk                            /*!<Tx Event FIFO Element Lost               */
+#define FDCAN_IR_TSW_Pos          (16U)
+#define FDCAN_IR_TSW_Msk          (0x1UL << FDCAN_IR_TSW_Pos)                  /*!< 0x00010000 */
+#define FDCAN_IR_TSW              FDCAN_IR_TSW_Msk                             /*!<Timestamp Wraparound                     */
+#define FDCAN_IR_MRAF_Pos         (17U)
+#define FDCAN_IR_MRAF_Msk         (0x1UL << FDCAN_IR_MRAF_Pos)                 /*!< 0x00020000 */
+#define FDCAN_IR_MRAF             FDCAN_IR_MRAF_Msk                            /*!<Message RAM Access Failure               */
+#define FDCAN_IR_TOO_Pos          (18U)
+#define FDCAN_IR_TOO_Msk          (0x1UL << FDCAN_IR_TOO_Pos)                  /*!< 0x00040000 */
+#define FDCAN_IR_TOO              FDCAN_IR_TOO_Msk                             /*!<Timeout Occurred                         */
+#define FDCAN_IR_DRX_Pos          (19U)
+#define FDCAN_IR_DRX_Msk          (0x1UL << FDCAN_IR_DRX_Pos)                  /*!< 0x00080000 */
+#define FDCAN_IR_DRX              FDCAN_IR_DRX_Msk                             /*!<Message stored to Dedicated Rx Buffer    */
+#define FDCAN_IR_ELO_Pos          (22U)
+#define FDCAN_IR_ELO_Msk          (0x1UL << FDCAN_IR_ELO_Pos)                  /*!< 0x00400000 */
+#define FDCAN_IR_ELO              FDCAN_IR_ELO_Msk                             /*!<Error Logging Overflow                   */
+#define FDCAN_IR_EP_Pos           (23U)
+#define FDCAN_IR_EP_Msk           (0x1UL << FDCAN_IR_EP_Pos)                   /*!< 0x00800000 */
+#define FDCAN_IR_EP               FDCAN_IR_EP_Msk                              /*!<Error Passive                            */
+#define FDCAN_IR_EW_Pos           (24U)
+#define FDCAN_IR_EW_Msk           (0x1UL << FDCAN_IR_EW_Pos)                   /*!< 0x01000000 */
+#define FDCAN_IR_EW               FDCAN_IR_EW_Msk                              /*!<Warning Status                           */
+#define FDCAN_IR_BO_Pos           (25U)
+#define FDCAN_IR_BO_Msk           (0x1UL << FDCAN_IR_BO_Pos)                   /*!< 0x02000000 */
+#define FDCAN_IR_BO               FDCAN_IR_BO_Msk                              /*!<Bus_Off Status                           */
+#define FDCAN_IR_WDI_Pos          (26U)
+#define FDCAN_IR_WDI_Msk          (0x1UL << FDCAN_IR_WDI_Pos)                  /*!< 0x04000000 */
+#define FDCAN_IR_WDI              FDCAN_IR_WDI_Msk                             /*!<Watchdog Interrupt                       */
+#define FDCAN_IR_PEA_Pos          (27U)
+#define FDCAN_IR_PEA_Msk          (0x1UL << FDCAN_IR_PEA_Pos)                  /*!< 0x08000000 */
+#define FDCAN_IR_PEA              FDCAN_IR_PEA_Msk                             /*!<Protocol Error in Arbitration Phase      */
+#define FDCAN_IR_PED_Pos          (28U)
+#define FDCAN_IR_PED_Msk          (0x1UL << FDCAN_IR_PED_Pos)                  /*!< 0x10000000 */
+#define FDCAN_IR_PED              FDCAN_IR_PED_Msk                             /*!<Protocol Error in Data Phase             */
+#define FDCAN_IR_ARA_Pos          (29U)
+#define FDCAN_IR_ARA_Msk          (0x1UL << FDCAN_IR_ARA_Pos)                  /*!< 0x20000000 */
+#define FDCAN_IR_ARA              FDCAN_IR_ARA_Msk                             /*!<Access to Reserved Address               */
+
+/*****************  Bit definition for FDCAN_IE register  **********************/
+#define FDCAN_IE_RF0NE_Pos        (0U)
+#define FDCAN_IE_RF0NE_Msk        (0x1UL << FDCAN_IE_RF0NE_Pos)                /*!< 0x00000001 */
+#define FDCAN_IE_RF0NE            FDCAN_IE_RF0NE_Msk                           /*!<Rx FIFO 0 New Message Enable                 */
+#define FDCAN_IE_RF0WE_Pos        (1U)
+#define FDCAN_IE_RF0WE_Msk        (0x1UL << FDCAN_IE_RF0WE_Pos)                /*!< 0x00000002 */
+#define FDCAN_IE_RF0WE            FDCAN_IE_RF0WE_Msk                           /*!<Rx FIFO 0 Watermark Reached Enable           */
+#define FDCAN_IE_RF0FE_Pos        (2U)
+#define FDCAN_IE_RF0FE_Msk        (0x1UL << FDCAN_IE_RF0FE_Pos)                /*!< 0x00000004 */
+#define FDCAN_IE_RF0FE            FDCAN_IE_RF0FE_Msk                           /*!<Rx FIFO 0 Full Enable                        */
+#define FDCAN_IE_RF0LE_Pos        (3U)
+#define FDCAN_IE_RF0LE_Msk        (0x1UL << FDCAN_IE_RF0LE_Pos)                /*!< 0x00000008 */
+#define FDCAN_IE_RF0LE            FDCAN_IE_RF0LE_Msk                           /*!<Rx FIFO 0 Message Lost Enable                */
+#define FDCAN_IE_RF1NE_Pos        (4U)
+#define FDCAN_IE_RF1NE_Msk        (0x1UL << FDCAN_IE_RF1NE_Pos)                /*!< 0x00000010 */
+#define FDCAN_IE_RF1NE            FDCAN_IE_RF1NE_Msk                           /*!<Rx FIFO 1 New Message Enable                 */
+#define FDCAN_IE_RF1WE_Pos        (5U)
+#define FDCAN_IE_RF1WE_Msk        (0x1UL << FDCAN_IE_RF1WE_Pos)                /*!< 0x00000020 */
+#define FDCAN_IE_RF1WE            FDCAN_IE_RF1WE_Msk                           /*!<Rx FIFO 1 Watermark Reached Enable           */
+#define FDCAN_IE_RF1FE_Pos        (6U)
+#define FDCAN_IE_RF1FE_Msk        (0x1UL << FDCAN_IE_RF1FE_Pos)                /*!< 0x00000040 */
+#define FDCAN_IE_RF1FE            FDCAN_IE_RF1FE_Msk                           /*!<Rx FIFO 1 Full Enable                        */
+#define FDCAN_IE_RF1LE_Pos        (7U)
+#define FDCAN_IE_RF1LE_Msk        (0x1UL << FDCAN_IE_RF1LE_Pos)                /*!< 0x00000080 */
+#define FDCAN_IE_RF1LE            FDCAN_IE_RF1LE_Msk                           /*!<Rx FIFO 1 Message Lost Enable                */
+#define FDCAN_IE_HPME_Pos         (8U)
+#define FDCAN_IE_HPME_Msk         (0x1UL << FDCAN_IE_HPME_Pos)                 /*!< 0x00000100 */
+#define FDCAN_IE_HPME             FDCAN_IE_HPME_Msk                            /*!<High Priority Message Enable                 */
+#define FDCAN_IE_TCE_Pos          (9U)
+#define FDCAN_IE_TCE_Msk          (0x1UL << FDCAN_IE_TCE_Pos)                  /*!< 0x00000200 */
+#define FDCAN_IE_TCE              FDCAN_IE_TCE_Msk                             /*!<Transmission Completed Enable                */
+#define FDCAN_IE_TCFE_Pos         (10U)
+#define FDCAN_IE_TCFE_Msk         (0x1UL << FDCAN_IE_TCFE_Pos)                 /*!< 0x00000400 */
+#define FDCAN_IE_TCFE             FDCAN_IE_TCFE_Msk                            /*!<Transmission Cancellation Finished Enable    */
+#define FDCAN_IE_TFEE_Pos         (11U)
+#define FDCAN_IE_TFEE_Msk         (0x1UL << FDCAN_IE_TFEE_Pos)                 /*!< 0x00000800 */
+#define FDCAN_IE_TFEE             FDCAN_IE_TFEE_Msk                            /*!<Tx FIFO Empty Enable                         */
+#define FDCAN_IE_TEFNE_Pos        (12U)
+#define FDCAN_IE_TEFNE_Msk        (0x1UL << FDCAN_IE_TEFNE_Pos)                /*!< 0x00001000 */
+#define FDCAN_IE_TEFNE            FDCAN_IE_TEFNE_Msk                           /*!<Tx Event FIFO New Entry Enable               */
+#define FDCAN_IE_TEFWE_Pos        (13U)
+#define FDCAN_IE_TEFWE_Msk        (0x1UL << FDCAN_IE_TEFWE_Pos)                /*!< 0x00002000 */
+#define FDCAN_IE_TEFWE            FDCAN_IE_TEFWE_Msk                           /*!<Tx Event FIFO Watermark Reached Enable       */
+#define FDCAN_IE_TEFFE_Pos        (14U)
+#define FDCAN_IE_TEFFE_Msk        (0x1UL << FDCAN_IE_TEFFE_Pos)                /*!< 0x00004000 */
+#define FDCAN_IE_TEFFE            FDCAN_IE_TEFFE_Msk                           /*!<Tx Event FIFO Full Enable                    */
+#define FDCAN_IE_TEFLE_Pos        (15U)
+#define FDCAN_IE_TEFLE_Msk        (0x1UL << FDCAN_IE_TEFLE_Pos)                /*!< 0x00008000 */
+#define FDCAN_IE_TEFLE            FDCAN_IE_TEFLE_Msk                           /*!<Tx Event FIFO Element Lost Enable            */
+#define FDCAN_IE_TSWE_Pos         (16U)
+#define FDCAN_IE_TSWE_Msk         (0x1UL << FDCAN_IE_TSWE_Pos)                 /*!< 0x00010000 */
+#define FDCAN_IE_TSWE             FDCAN_IE_TSWE_Msk                            /*!<Timestamp Wraparound Enable                  */
+#define FDCAN_IE_MRAFE_Pos        (17U)
+#define FDCAN_IE_MRAFE_Msk        (0x1UL << FDCAN_IE_MRAFE_Pos)                /*!< 0x00020000 */
+#define FDCAN_IE_MRAFE            FDCAN_IE_MRAFE_Msk                           /*!<Message RAM Access Failure Enable            */
+#define FDCAN_IE_TOOE_Pos         (18U)
+#define FDCAN_IE_TOOE_Msk         (0x1UL << FDCAN_IE_TOOE_Pos)                 /*!< 0x00040000 */
+#define FDCAN_IE_TOOE             FDCAN_IE_TOOE_Msk                            /*!<Timeout Occurred Enable                      */
+#define FDCAN_IE_DRXE_Pos         (19U)
+#define FDCAN_IE_DRXE_Msk         (0x1UL << FDCAN_IE_DRXE_Pos)                 /*!< 0x00080000 */
+#define FDCAN_IE_DRXE             FDCAN_IE_DRXE_Msk                            /*!<Message stored to Dedicated Rx Buffer Enable */
+#define FDCAN_IE_BECE_Pos         (20U)
+#define FDCAN_IE_BECE_Msk         (0x1UL << FDCAN_IE_BECE_Pos)                 /*!< 0x00100000 */
+#define FDCAN_IE_BECE             FDCAN_IE_BECE_Msk                            /*!<Bit Error Corrected Interrupt Enable         */
+#define FDCAN_IE_BEUE_Pos         (21U)
+#define FDCAN_IE_BEUE_Msk         (0x1UL << FDCAN_IE_BEUE_Pos)                 /*!< 0x00200000 */
+#define FDCAN_IE_BEUE             FDCAN_IE_BEUE_Msk                            /*!<Bit Error Uncorrected Interrupt Enable       */
+#define FDCAN_IE_ELOE_Pos         (22U)
+#define FDCAN_IE_ELOE_Msk         (0x1UL << FDCAN_IE_ELOE_Pos)                 /*!< 0x00400000 */
+#define FDCAN_IE_ELOE             FDCAN_IE_ELOE_Msk                            /*!<Error Logging Overflow Enable                */
+#define FDCAN_IE_EPE_Pos          (23U)
+#define FDCAN_IE_EPE_Msk          (0x1UL << FDCAN_IE_EPE_Pos)                  /*!< 0x00800000 */
+#define FDCAN_IE_EPE              FDCAN_IE_EPE_Msk                             /*!<Error Passive Enable                         */
+#define FDCAN_IE_EWE_Pos          (24U)
+#define FDCAN_IE_EWE_Msk          (0x1UL << FDCAN_IE_EWE_Pos)                  /*!< 0x01000000 */
+#define FDCAN_IE_EWE              FDCAN_IE_EWE_Msk                             /*!<Warning Status Enable                        */
+#define FDCAN_IE_BOE_Pos          (25U)
+#define FDCAN_IE_BOE_Msk          (0x1UL << FDCAN_IE_BOE_Pos)                  /*!< 0x02000000 */
+#define FDCAN_IE_BOE              FDCAN_IE_BOE_Msk                             /*!<Bus_Off Status Enable                        */
+#define FDCAN_IE_WDIE_Pos         (26U)
+#define FDCAN_IE_WDIE_Msk         (0x1UL << FDCAN_IE_WDIE_Pos)                 /*!< 0x04000000 */
+#define FDCAN_IE_WDIE             FDCAN_IE_WDIE_Msk                            /*!<Watchdog Interrupt Enable                    */
+#define FDCAN_IE_PEAE_Pos         (27U)
+#define FDCAN_IE_PEAE_Msk         (0x1UL << FDCAN_IE_PEAE_Pos)                 /*!< 0x08000000 */
+#define FDCAN_IE_PEAE             FDCAN_IE_PEAE_Msk                            /*!<Protocol Error in Arbitration Phase Enable   */
+#define FDCAN_IE_PEDE_Pos         (28U)
+#define FDCAN_IE_PEDE_Msk         (0x1UL << FDCAN_IE_PEDE_Pos)                 /*!< 0x10000000 */
+#define FDCAN_IE_PEDE             FDCAN_IE_PEDE_Msk                            /*!<Protocol Error in Data Phase Enable          */
+#define FDCAN_IE_ARAE_Pos         (29U)
+#define FDCAN_IE_ARAE_Msk         (0x1UL << FDCAN_IE_ARAE_Pos)                 /*!< 0x20000000 */
+#define FDCAN_IE_ARAE             FDCAN_IE_ARAE_Msk                            /*!<Access to Reserved Address Enable            */
+
+/*****************  Bit definition for FDCAN_ILS register  **********************/
+#define FDCAN_ILS_RF0NL_Pos       (0U)
+#define FDCAN_ILS_RF0NL_Msk       (0x1UL << FDCAN_ILS_RF0NL_Pos)               /*!< 0x00000001 */
+#define FDCAN_ILS_RF0NL           FDCAN_ILS_RF0NL_Msk                          /*!<Rx FIFO 0 New Message Line                  */
+#define FDCAN_ILS_RF0WL_Pos       (1U)
+#define FDCAN_ILS_RF0WL_Msk       (0x1UL << FDCAN_ILS_RF0WL_Pos)               /*!< 0x00000002 */
+#define FDCAN_ILS_RF0WL           FDCAN_ILS_RF0WL_Msk                          /*!<Rx FIFO 0 Watermark Reached Line            */
+#define FDCAN_ILS_RF0FL_Pos       (2U)
+#define FDCAN_ILS_RF0FL_Msk       (0x1UL << FDCAN_ILS_RF0FL_Pos)               /*!< 0x00000004 */
+#define FDCAN_ILS_RF0FL           FDCAN_ILS_RF0FL_Msk                          /*!<Rx FIFO 0 Full Line                         */
+#define FDCAN_ILS_RF0LL_Pos       (3U)
+#define FDCAN_ILS_RF0LL_Msk       (0x1UL << FDCAN_ILS_RF0LL_Pos)               /*!< 0x00000008 */
+#define FDCAN_ILS_RF0LL           FDCAN_ILS_RF0LL_Msk                          /*!<Rx FIFO 0 Message Lost Line                 */
+#define FDCAN_ILS_RF1NL_Pos       (4U)
+#define FDCAN_ILS_RF1NL_Msk       (0x1UL << FDCAN_ILS_RF1NL_Pos)               /*!< 0x00000010 */
+#define FDCAN_ILS_RF1NL           FDCAN_ILS_RF1NL_Msk                          /*!<Rx FIFO 1 New Message Line                  */
+#define FDCAN_ILS_RF1WL_Pos       (5U)
+#define FDCAN_ILS_RF1WL_Msk       (0x1UL << FDCAN_ILS_RF1WL_Pos)               /*!< 0x00000020 */
+#define FDCAN_ILS_RF1WL           FDCAN_ILS_RF1WL_Msk                          /*!<Rx FIFO 1 Watermark Reached Line            */
+#define FDCAN_ILS_RF1FL_Pos       (6U)
+#define FDCAN_ILS_RF1FL_Msk       (0x1UL << FDCAN_ILS_RF1FL_Pos)               /*!< 0x00000040 */
+#define FDCAN_ILS_RF1FL           FDCAN_ILS_RF1FL_Msk                          /*!<Rx FIFO 1 Full Line                         */
+#define FDCAN_ILS_RF1LL_Pos       (7U)
+#define FDCAN_ILS_RF1LL_Msk       (0x1UL << FDCAN_ILS_RF1LL_Pos)               /*!< 0x00000080 */
+#define FDCAN_ILS_RF1LL           FDCAN_ILS_RF1LL_Msk                          /*!<Rx FIFO 1 Message Lost Line                 */
+#define FDCAN_ILS_HPML_Pos        (8U)
+#define FDCAN_ILS_HPML_Msk        (0x1UL << FDCAN_ILS_HPML_Pos)                /*!< 0x00000100 */
+#define FDCAN_ILS_HPML            FDCAN_ILS_HPML_Msk                           /*!<High Priority Message Line                  */
+#define FDCAN_ILS_TCL_Pos         (9U)
+#define FDCAN_ILS_TCL_Msk         (0x1UL << FDCAN_ILS_TCL_Pos)                 /*!< 0x00000200 */
+#define FDCAN_ILS_TCL             FDCAN_ILS_TCL_Msk                            /*!<Transmission Completed Line                 */
+#define FDCAN_ILS_TCFL_Pos        (10U)
+#define FDCAN_ILS_TCFL_Msk        (0x1UL << FDCAN_ILS_TCFL_Pos)                /*!< 0x00000400 */
+#define FDCAN_ILS_TCFL            FDCAN_ILS_TCFL_Msk                           /*!<Transmission Cancellation Finished Line     */
+#define FDCAN_ILS_TFEL_Pos        (11U)
+#define FDCAN_ILS_TFEL_Msk        (0x1UL << FDCAN_ILS_TFEL_Pos)                /*!< 0x00000800 */
+#define FDCAN_ILS_TFEL            FDCAN_ILS_TFEL_Msk                           /*!<Tx FIFO Empty Line                          */
+#define FDCAN_ILS_TEFNL_Pos       (12U)
+#define FDCAN_ILS_TEFNL_Msk       (0x1UL << FDCAN_ILS_TEFNL_Pos)               /*!< 0x00001000 */
+#define FDCAN_ILS_TEFNL           FDCAN_ILS_TEFNL_Msk                          /*!<Tx Event FIFO New Entry Line                */
+#define FDCAN_ILS_TEFWL_Pos       (13U)
+#define FDCAN_ILS_TEFWL_Msk       (0x1UL << FDCAN_ILS_TEFWL_Pos)               /*!< 0x00002000 */
+#define FDCAN_ILS_TEFWL           FDCAN_ILS_TEFWL_Msk                          /*!<Tx Event FIFO Watermark Reached Line        */
+#define FDCAN_ILS_TEFFL_Pos       (14U)
+#define FDCAN_ILS_TEFFL_Msk       (0x1UL << FDCAN_ILS_TEFFL_Pos)               /*!< 0x00004000 */
+#define FDCAN_ILS_TEFFL           FDCAN_ILS_TEFFL_Msk                          /*!<Tx Event FIFO Full Line                     */
+#define FDCAN_ILS_TEFLL_Pos       (15U)
+#define FDCAN_ILS_TEFLL_Msk       (0x1UL << FDCAN_ILS_TEFLL_Pos)               /*!< 0x00008000 */
+#define FDCAN_ILS_TEFLL           FDCAN_ILS_TEFLL_Msk                          /*!<Tx Event FIFO Element Lost Line             */
+#define FDCAN_ILS_TSWL_Pos        (16U)
+#define FDCAN_ILS_TSWL_Msk        (0x1UL << FDCAN_ILS_TSWL_Pos)                /*!< 0x00010000 */
+#define FDCAN_ILS_TSWL            FDCAN_ILS_TSWL_Msk                           /*!<Timestamp Wraparound Line                   */
+#define FDCAN_ILS_MRAFE_Pos       (17U)
+#define FDCAN_ILS_MRAFE_Msk       (0x1UL << FDCAN_ILS_MRAFE_Pos)               /*!< 0x00020000 */
+#define FDCAN_ILS_MRAFE           FDCAN_ILS_MRAFE_Msk                          /*!<Message RAM Access Failure Line             */
+#define FDCAN_ILS_TOOE_Pos        (18U)
+#define FDCAN_ILS_TOOE_Msk        (0x1UL << FDCAN_ILS_TOOE_Pos)                /*!< 0x00040000 */
+#define FDCAN_ILS_TOOE            FDCAN_ILS_TOOE_Msk                           /*!<Timeout Occurred Line                       */
+#define FDCAN_ILS_DRXE_Pos        (19U)
+#define FDCAN_ILS_DRXE_Msk        (0x1UL << FDCAN_ILS_DRXE_Pos)                /*!< 0x00080000 */
+#define FDCAN_ILS_DRXE            FDCAN_ILS_DRXE_Msk                           /*!<Message stored to Dedicated Rx Buffer Line  */
+#define FDCAN_ILS_BECE_Pos        (20U)
+#define FDCAN_ILS_BECE_Msk        (0x1UL << FDCAN_ILS_BECE_Pos)                /*!< 0x00100000 */
+#define FDCAN_ILS_BECE            FDCAN_ILS_BECE_Msk                           /*!<Bit Error Corrected Interrupt Line          */
+#define FDCAN_ILS_BEUE_Pos        (21U)
+#define FDCAN_ILS_BEUE_Msk        (0x1UL << FDCAN_ILS_BEUE_Pos)                /*!< 0x00200000 */
+#define FDCAN_ILS_BEUE            FDCAN_ILS_BEUE_Msk                           /*!<Bit Error Uncorrected Interrupt Line        */
+#define FDCAN_ILS_ELOE_Pos        (22U)
+#define FDCAN_ILS_ELOE_Msk        (0x1UL << FDCAN_ILS_ELOE_Pos)                /*!< 0x00400000 */
+#define FDCAN_ILS_ELOE            FDCAN_ILS_ELOE_Msk                           /*!<Error Logging Overflow Line                 */
+#define FDCAN_ILS_EPE_Pos         (23U)
+#define FDCAN_ILS_EPE_Msk         (0x1UL << FDCAN_ILS_EPE_Pos)                 /*!< 0x00800000 */
+#define FDCAN_ILS_EPE             FDCAN_ILS_EPE_Msk                            /*!<Error Passive Line                          */
+#define FDCAN_ILS_EWE_Pos         (24U)
+#define FDCAN_ILS_EWE_Msk         (0x1UL << FDCAN_ILS_EWE_Pos)                 /*!< 0x01000000 */
+#define FDCAN_ILS_EWE             FDCAN_ILS_EWE_Msk                            /*!<Warning Status Line                         */
+#define FDCAN_ILS_BOE_Pos         (25U)
+#define FDCAN_ILS_BOE_Msk         (0x1UL << FDCAN_ILS_BOE_Pos)                 /*!< 0x02000000 */
+#define FDCAN_ILS_BOE             FDCAN_ILS_BOE_Msk                            /*!<Bus_Off Status Line                         */
+#define FDCAN_ILS_WDIE_Pos        (26U)
+#define FDCAN_ILS_WDIE_Msk        (0x1UL << FDCAN_ILS_WDIE_Pos)                /*!< 0x04000000 */
+#define FDCAN_ILS_WDIE            FDCAN_ILS_WDIE_Msk                           /*!<Watchdog Interrupt Line                     */
+#define FDCAN_ILS_PEAE_Pos        (27U)
+#define FDCAN_ILS_PEAE_Msk        (0x1UL << FDCAN_ILS_PEAE_Pos)                /*!< 0x08000000 */
+#define FDCAN_ILS_PEAE            FDCAN_ILS_PEAE_Msk                           /*!<Protocol Error in Arbitration Phase Line    */
+#define FDCAN_ILS_PEDE_Pos        (28U)
+#define FDCAN_ILS_PEDE_Msk        (0x1UL << FDCAN_ILS_PEDE_Pos)                /*!< 0x10000000 */
+#define FDCAN_ILS_PEDE            FDCAN_ILS_PEDE_Msk                           /*!<Protocol Error in Data Phase Line           */
+#define FDCAN_ILS_ARAE_Pos        (29U)
+#define FDCAN_ILS_ARAE_Msk        (0x1UL << FDCAN_ILS_ARAE_Pos)                /*!< 0x20000000 */
+#define FDCAN_ILS_ARAE            FDCAN_ILS_ARAE_Msk                           /*!<Access to Reserved Address Line             */
+
+/*****************  Bit definition for FDCAN_ILE register  **********************/
+#define FDCAN_ILE_EINT0_Pos       (0U)
+#define FDCAN_ILE_EINT0_Msk       (0x1UL << FDCAN_ILE_EINT0_Pos)               /*!< 0x00000001 */
+#define FDCAN_ILE_EINT0           FDCAN_ILE_EINT0_Msk                          /*!<Enable Interrupt Line 0                   */
+#define FDCAN_ILE_EINT1_Pos       (1U)
+#define FDCAN_ILE_EINT1_Msk       (0x1UL << FDCAN_ILE_EINT1_Pos)               /*!< 0x00000002 */
+#define FDCAN_ILE_EINT1           FDCAN_ILE_EINT1_Msk                          /*!<Enable Interrupt Line 1                   */
+
+/*****************  Bit definition for FDCAN_GFC register  **********************/
+#define FDCAN_GFC_RRFE_Pos        (0U)
+#define FDCAN_GFC_RRFE_Msk        (0x1UL << FDCAN_GFC_RRFE_Pos)                /*!< 0x00000001 */
+#define FDCAN_GFC_RRFE            FDCAN_GFC_RRFE_Msk                           /*!<Reject Remote Frames Extended             */
+#define FDCAN_GFC_RRFS_Pos        (1U)
+#define FDCAN_GFC_RRFS_Msk        (0x1UL << FDCAN_GFC_RRFS_Pos)                /*!< 0x00000002 */
+#define FDCAN_GFC_RRFS            FDCAN_GFC_RRFS_Msk                           /*!<Reject Remote Frames Standard             */
+#define FDCAN_GFC_ANFE_Pos        (2U)
+#define FDCAN_GFC_ANFE_Msk        (0x3UL << FDCAN_GFC_ANFE_Pos)                /*!< 0x0000000C */
+#define FDCAN_GFC_ANFE            FDCAN_GFC_ANFE_Msk                           /*!<Accept Non-matching Frames Extended       */
+#define FDCAN_GFC_ANFS_Pos        (4U)
+#define FDCAN_GFC_ANFS_Msk        (0x3UL << FDCAN_GFC_ANFS_Pos)                /*!< 0x00000030 */
+#define FDCAN_GFC_ANFS            FDCAN_GFC_ANFS_Msk                           /*!<Accept Non-matching Frames Standard       */
+
+/*****************  Bit definition for FDCAN_SIDFC register  ********************/
+#define FDCAN_SIDFC_FLSSA_Pos     (2U)
+#define FDCAN_SIDFC_FLSSA_Msk     (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos)          /*!< 0x0000FFFC */
+#define FDCAN_SIDFC_FLSSA         FDCAN_SIDFC_FLSSA_Msk                        /*!<Filter List Standard Start Address        */
+#define FDCAN_SIDFC_LSS_Pos       (16U)
+#define FDCAN_SIDFC_LSS_Msk       (0xFFUL << FDCAN_SIDFC_LSS_Pos)              /*!< 0x00FF0000 */
+#define FDCAN_SIDFC_LSS           FDCAN_SIDFC_LSS_Msk                          /*!<List Size Standard                        */
+
+/*****************  Bit definition for FDCAN_XIDFC register  ********************/
+#define FDCAN_XIDFC_FLESA_Pos     (2U)
+#define FDCAN_XIDFC_FLESA_Msk     (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos)          /*!< 0x0000FFFC */
+#define FDCAN_XIDFC_FLESA         FDCAN_XIDFC_FLESA_Msk                        /*!<Filter List Standard Start Address        */
+#define FDCAN_XIDFC_LSE_Pos       (16U)
+#define FDCAN_XIDFC_LSE_Msk       (0x7FUL << FDCAN_XIDFC_LSE_Pos)              /*!< 0x007F0000 */
+#define FDCAN_XIDFC_LSE           FDCAN_XIDFC_LSE_Msk                          /*!<List Size Extended                        */
+
+/*****************  Bit definition for FDCAN_XIDAM register  ********************/
+#define FDCAN_XIDAM_EIDM_Pos      (0U)
+#define FDCAN_XIDAM_EIDM_Msk      (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)       /*!< 0x1FFFFFFF */
+#define FDCAN_XIDAM_EIDM          FDCAN_XIDAM_EIDM_Msk                         /*!<Extended ID Mask                          */
+
+/*****************  Bit definition for FDCAN_HPMS register  *********************/
+#define FDCAN_HPMS_BIDX_Pos       (0U)
+#define FDCAN_HPMS_BIDX_Msk       (0x3FUL << FDCAN_HPMS_BIDX_Pos)              /*!< 0x0000003F */
+#define FDCAN_HPMS_BIDX           FDCAN_HPMS_BIDX_Msk                          /*!<Buffer Index                              */
+#define FDCAN_HPMS_MSI_Pos        (6U)
+#define FDCAN_HPMS_MSI_Msk        (0x3UL << FDCAN_HPMS_MSI_Pos)                /*!< 0x000000C0 */
+#define FDCAN_HPMS_MSI            FDCAN_HPMS_MSI_Msk                           /*!<Message Storage Indicator                 */
+#define FDCAN_HPMS_FIDX_Pos       (8U)
+#define FDCAN_HPMS_FIDX_Msk       (0x7FUL << FDCAN_HPMS_FIDX_Pos)              /*!< 0x00007F00 */
+#define FDCAN_HPMS_FIDX           FDCAN_HPMS_FIDX_Msk                          /*!<Filter Index                              */
+#define FDCAN_HPMS_FLST_Pos       (15U)
+#define FDCAN_HPMS_FLST_Msk       (0x1UL << FDCAN_HPMS_FLST_Pos)               /*!< 0x00008000 */
+#define FDCAN_HPMS_FLST           FDCAN_HPMS_FLST_Msk                          /*!<Filter List                               */
+
+/*****************  Bit definition for FDCAN_NDAT1 register  ********************/
+#define FDCAN_NDAT1_ND0_Pos       (0U)
+#define FDCAN_NDAT1_ND0_Msk       (0x1UL << FDCAN_NDAT1_ND0_Pos)               /*!< 0x00000001 */
+#define FDCAN_NDAT1_ND0           FDCAN_NDAT1_ND0_Msk                          /*!<New Data flag of Rx Buffer 0              */
+#define FDCAN_NDAT1_ND1_Pos       (1U)
+#define FDCAN_NDAT1_ND1_Msk       (0x1UL << FDCAN_NDAT1_ND1_Pos)               /*!< 0x00000002 */
+#define FDCAN_NDAT1_ND1           FDCAN_NDAT1_ND1_Msk                          /*!<New Data flag of Rx Buffer 1              */
+#define FDCAN_NDAT1_ND2_Pos       (2U)
+#define FDCAN_NDAT1_ND2_Msk       (0x1UL << FDCAN_NDAT1_ND2_Pos)               /*!< 0x00000004 */
+#define FDCAN_NDAT1_ND2           FDCAN_NDAT1_ND2_Msk                          /*!<New Data flag of Rx Buffer 2              */
+#define FDCAN_NDAT1_ND3_Pos       (3U)
+#define FDCAN_NDAT1_ND3_Msk       (0x1UL << FDCAN_NDAT1_ND3_Pos)               /*!< 0x00000008 */
+#define FDCAN_NDAT1_ND3           FDCAN_NDAT1_ND3_Msk                          /*!<New Data flag of Rx Buffer 3              */
+#define FDCAN_NDAT1_ND4_Pos       (4U)
+#define FDCAN_NDAT1_ND4_Msk       (0x1UL << FDCAN_NDAT1_ND4_Pos)               /*!< 0x00000010 */
+#define FDCAN_NDAT1_ND4           FDCAN_NDAT1_ND4_Msk                          /*!<New Data flag of Rx Buffer 4              */
+#define FDCAN_NDAT1_ND5_Pos       (5U)
+#define FDCAN_NDAT1_ND5_Msk       (0x1UL << FDCAN_NDAT1_ND5_Pos)               /*!< 0x00000020 */
+#define FDCAN_NDAT1_ND5           FDCAN_NDAT1_ND5_Msk                          /*!<New Data flag of Rx Buffer 5              */
+#define FDCAN_NDAT1_ND6_Pos       (6U)
+#define FDCAN_NDAT1_ND6_Msk       (0x1UL << FDCAN_NDAT1_ND6_Pos)               /*!< 0x00000040 */
+#define FDCAN_NDAT1_ND6           FDCAN_NDAT1_ND6_Msk                          /*!<New Data flag of Rx Buffer 6              */
+#define FDCAN_NDAT1_ND7_Pos       (7U)
+#define FDCAN_NDAT1_ND7_Msk       (0x1UL << FDCAN_NDAT1_ND7_Pos)               /*!< 0x00000080 */
+#define FDCAN_NDAT1_ND7           FDCAN_NDAT1_ND7_Msk                          /*!<New Data flag of Rx Buffer 7              */
+#define FDCAN_NDAT1_ND8_Pos       (8U)
+#define FDCAN_NDAT1_ND8_Msk       (0x1UL << FDCAN_NDAT1_ND8_Pos)               /*!< 0x00000100 */
+#define FDCAN_NDAT1_ND8           FDCAN_NDAT1_ND8_Msk                          /*!<New Data flag of Rx Buffer 8              */
+#define FDCAN_NDAT1_ND9_Pos       (9U)
+#define FDCAN_NDAT1_ND9_Msk       (0x1UL << FDCAN_NDAT1_ND9_Pos)               /*!< 0x00000200 */
+#define FDCAN_NDAT1_ND9           FDCAN_NDAT1_ND9_Msk                          /*!<New Data flag of Rx Buffer 9              */
+#define FDCAN_NDAT1_ND10_Pos      (10U)
+#define FDCAN_NDAT1_ND10_Msk      (0x1UL << FDCAN_NDAT1_ND10_Pos)              /*!< 0x00000400 */
+#define FDCAN_NDAT1_ND10          FDCAN_NDAT1_ND10_Msk                         /*!<New Data flag of Rx Buffer 10             */
+#define FDCAN_NDAT1_ND11_Pos      (11U)
+#define FDCAN_NDAT1_ND11_Msk      (0x1UL << FDCAN_NDAT1_ND11_Pos)              /*!< 0x00000800 */
+#define FDCAN_NDAT1_ND11          FDCAN_NDAT1_ND11_Msk                         /*!<New Data flag of Rx Buffer 11             */
+#define FDCAN_NDAT1_ND12_Pos      (12U)
+#define FDCAN_NDAT1_ND12_Msk      (0x1UL << FDCAN_NDAT1_ND12_Pos)              /*!< 0x00001000 */
+#define FDCAN_NDAT1_ND12          FDCAN_NDAT1_ND12_Msk                         /*!<New Data flag of Rx Buffer 12             */
+#define FDCAN_NDAT1_ND13_Pos      (13U)
+#define FDCAN_NDAT1_ND13_Msk      (0x1UL << FDCAN_NDAT1_ND13_Pos)              /*!< 0x00002000 */
+#define FDCAN_NDAT1_ND13          FDCAN_NDAT1_ND13_Msk                         /*!<New Data flag of Rx Buffer 13             */
+#define FDCAN_NDAT1_ND14_Pos      (14U)
+#define FDCAN_NDAT1_ND14_Msk      (0x1UL << FDCAN_NDAT1_ND14_Pos)              /*!< 0x00004000 */
+#define FDCAN_NDAT1_ND14          FDCAN_NDAT1_ND14_Msk                         /*!<New Data flag of Rx Buffer 14             */
+#define FDCAN_NDAT1_ND15_Pos      (15U)
+#define FDCAN_NDAT1_ND15_Msk      (0x1UL << FDCAN_NDAT1_ND15_Pos)              /*!< 0x00008000 */
+#define FDCAN_NDAT1_ND15          FDCAN_NDAT1_ND15_Msk                         /*!<New Data flag of Rx Buffer 15             */
+#define FDCAN_NDAT1_ND16_Pos      (16U)
+#define FDCAN_NDAT1_ND16_Msk      (0x1UL << FDCAN_NDAT1_ND16_Pos)              /*!< 0x00010000 */
+#define FDCAN_NDAT1_ND16          FDCAN_NDAT1_ND16_Msk                         /*!<New Data flag of Rx Buffer 16             */
+#define FDCAN_NDAT1_ND17_Pos      (17U)
+#define FDCAN_NDAT1_ND17_Msk      (0x1UL << FDCAN_NDAT1_ND17_Pos)              /*!< 0x00020000 */
+#define FDCAN_NDAT1_ND17          FDCAN_NDAT1_ND17_Msk                         /*!<New Data flag of Rx Buffer 17             */
+#define FDCAN_NDAT1_ND18_Pos      (18U)
+#define FDCAN_NDAT1_ND18_Msk      (0x1UL << FDCAN_NDAT1_ND18_Pos)              /*!< 0x00040000 */
+#define FDCAN_NDAT1_ND18          FDCAN_NDAT1_ND18_Msk                         /*!<New Data flag of Rx Buffer 18             */
+#define FDCAN_NDAT1_ND19_Pos      (19U)
+#define FDCAN_NDAT1_ND19_Msk      (0x1UL << FDCAN_NDAT1_ND19_Pos)              /*!< 0x00080000 */
+#define FDCAN_NDAT1_ND19          FDCAN_NDAT1_ND19_Msk                         /*!<New Data flag of Rx Buffer 19             */
+#define FDCAN_NDAT1_ND20_Pos      (20U)
+#define FDCAN_NDAT1_ND20_Msk      (0x1UL << FDCAN_NDAT1_ND20_Pos)              /*!< 0x00100000 */
+#define FDCAN_NDAT1_ND20          FDCAN_NDAT1_ND20_Msk                         /*!<New Data flag of Rx Buffer 20             */
+#define FDCAN_NDAT1_ND21_Pos      (21U)
+#define FDCAN_NDAT1_ND21_Msk      (0x1UL << FDCAN_NDAT1_ND21_Pos)              /*!< 0x00200000 */
+#define FDCAN_NDAT1_ND21          FDCAN_NDAT1_ND21_Msk                         /*!<New Data flag of Rx Buffer 21             */
+#define FDCAN_NDAT1_ND22_Pos      (22U)
+#define FDCAN_NDAT1_ND22_Msk      (0x1UL << FDCAN_NDAT1_ND22_Pos)              /*!< 0x00400000 */
+#define FDCAN_NDAT1_ND22          FDCAN_NDAT1_ND22_Msk                         /*!<New Data flag of Rx Buffer 22             */
+#define FDCAN_NDAT1_ND23_Pos      (23U)
+#define FDCAN_NDAT1_ND23_Msk      (0x1UL << FDCAN_NDAT1_ND23_Pos)              /*!< 0x00800000 */
+#define FDCAN_NDAT1_ND23          FDCAN_NDAT1_ND23_Msk                         /*!<New Data flag of Rx Buffer 23             */
+#define FDCAN_NDAT1_ND24_Pos      (24U)
+#define FDCAN_NDAT1_ND24_Msk      (0x1UL << FDCAN_NDAT1_ND24_Pos)              /*!< 0x01000000 */
+#define FDCAN_NDAT1_ND24          FDCAN_NDAT1_ND24_Msk                         /*!<New Data flag of Rx Buffer 24             */
+#define FDCAN_NDAT1_ND25_Pos      (25U)
+#define FDCAN_NDAT1_ND25_Msk      (0x1UL << FDCAN_NDAT1_ND25_Pos)              /*!< 0x02000000 */
+#define FDCAN_NDAT1_ND25          FDCAN_NDAT1_ND25_Msk                         /*!<New Data flag of Rx Buffer 25             */
+#define FDCAN_NDAT1_ND26_Pos      (26U)
+#define FDCAN_NDAT1_ND26_Msk      (0x1UL << FDCAN_NDAT1_ND26_Pos)              /*!< 0x04000000 */
+#define FDCAN_NDAT1_ND26          FDCAN_NDAT1_ND26_Msk                         /*!<New Data flag of Rx Buffer 26             */
+#define FDCAN_NDAT1_ND27_Pos      (27U)
+#define FDCAN_NDAT1_ND27_Msk      (0x1UL << FDCAN_NDAT1_ND27_Pos)              /*!< 0x08000000 */
+#define FDCAN_NDAT1_ND27          FDCAN_NDAT1_ND27_Msk                         /*!<New Data flag of Rx Buffer 27             */
+#define FDCAN_NDAT1_ND28_Pos      (28U)
+#define FDCAN_NDAT1_ND28_Msk      (0x1UL << FDCAN_NDAT1_ND28_Pos)              /*!< 0x10000000 */
+#define FDCAN_NDAT1_ND28          FDCAN_NDAT1_ND28_Msk                         /*!<New Data flag of Rx Buffer 28             */
+#define FDCAN_NDAT1_ND29_Pos      (29U)
+#define FDCAN_NDAT1_ND29_Msk      (0x1UL << FDCAN_NDAT1_ND29_Pos)              /*!< 0x20000000 */
+#define FDCAN_NDAT1_ND29          FDCAN_NDAT1_ND29_Msk                         /*!<New Data flag of Rx Buffer 29             */
+#define FDCAN_NDAT1_ND30_Pos      (30U)
+#define FDCAN_NDAT1_ND30_Msk      (0x1UL << FDCAN_NDAT1_ND30_Pos)              /*!< 0x40000000 */
+#define FDCAN_NDAT1_ND30          FDCAN_NDAT1_ND30_Msk                         /*!<New Data flag of Rx Buffer 30             */
+#define FDCAN_NDAT1_ND31_Pos      (31U)
+#define FDCAN_NDAT1_ND31_Msk      (0x1UL << FDCAN_NDAT1_ND31_Pos)              /*!< 0x80000000 */
+#define FDCAN_NDAT1_ND31          FDCAN_NDAT1_ND31_Msk                         /*!<New Data flag of Rx Buffer 31             */
+
+/*****************  Bit definition for FDCAN_NDAT2 register  ********************/
+#define FDCAN_NDAT2_ND32_Pos      (0U)
+#define FDCAN_NDAT2_ND32_Msk      (0x1UL << FDCAN_NDAT2_ND32_Pos)              /*!< 0x00000001 */
+#define FDCAN_NDAT2_ND32          FDCAN_NDAT2_ND32_Msk                         /*!<New Data flag of Rx Buffer 32             */
+#define FDCAN_NDAT2_ND33_Pos      (1U)
+#define FDCAN_NDAT2_ND33_Msk      (0x1UL << FDCAN_NDAT2_ND33_Pos)              /*!< 0x00000002 */
+#define FDCAN_NDAT2_ND33          FDCAN_NDAT2_ND33_Msk                         /*!<New Data flag of Rx Buffer 33             */
+#define FDCAN_NDAT2_ND34_Pos      (2U)
+#define FDCAN_NDAT2_ND34_Msk      (0x1UL << FDCAN_NDAT2_ND34_Pos)              /*!< 0x00000004 */
+#define FDCAN_NDAT2_ND34          FDCAN_NDAT2_ND34_Msk                         /*!<New Data flag of Rx Buffer 34             */
+#define FDCAN_NDAT2_ND35_Pos      (3U)
+#define FDCAN_NDAT2_ND35_Msk      (0x1UL << FDCAN_NDAT2_ND35_Pos)              /*!< 0x00000008 */
+#define FDCAN_NDAT2_ND35          FDCAN_NDAT2_ND35_Msk                         /*!<New Data flag of Rx Buffer 35             */
+#define FDCAN_NDAT2_ND36_Pos      (4U)
+#define FDCAN_NDAT2_ND36_Msk      (0x1UL << FDCAN_NDAT2_ND36_Pos)              /*!< 0x00000010 */
+#define FDCAN_NDAT2_ND36          FDCAN_NDAT2_ND36_Msk                         /*!<New Data flag of Rx Buffer 36             */
+#define FDCAN_NDAT2_ND37_Pos      (5U)
+#define FDCAN_NDAT2_ND37_Msk      (0x1UL << FDCAN_NDAT2_ND37_Pos)              /*!< 0x00000020 */
+#define FDCAN_NDAT2_ND37          FDCAN_NDAT2_ND37_Msk                         /*!<New Data flag of Rx Buffer 37             */
+#define FDCAN_NDAT2_ND38_Pos      (6U)
+#define FDCAN_NDAT2_ND38_Msk      (0x1UL << FDCAN_NDAT2_ND38_Pos)              /*!< 0x00000040 */
+#define FDCAN_NDAT2_ND38          FDCAN_NDAT2_ND38_Msk                         /*!<New Data flag of Rx Buffer 38             */
+#define FDCAN_NDAT2_ND39_Pos      (7U)
+#define FDCAN_NDAT2_ND39_Msk      (0x1UL << FDCAN_NDAT2_ND39_Pos)              /*!< 0x00000080 */
+#define FDCAN_NDAT2_ND39          FDCAN_NDAT2_ND39_Msk                         /*!<New Data flag of Rx Buffer 39             */
+#define FDCAN_NDAT2_ND40_Pos      (8U)
+#define FDCAN_NDAT2_ND40_Msk      (0x1UL << FDCAN_NDAT2_ND40_Pos)              /*!< 0x00000100 */
+#define FDCAN_NDAT2_ND40          FDCAN_NDAT2_ND40_Msk                         /*!<New Data flag of Rx Buffer 40             */
+#define FDCAN_NDAT2_ND41_Pos      (9U)
+#define FDCAN_NDAT2_ND41_Msk      (0x1UL << FDCAN_NDAT2_ND41_Pos)              /*!< 0x00000200 */
+#define FDCAN_NDAT2_ND41          FDCAN_NDAT2_ND41_Msk                         /*!<New Data flag of Rx Buffer 41             */
+#define FDCAN_NDAT2_ND42_Pos      (10U)
+#define FDCAN_NDAT2_ND42_Msk      (0x1UL << FDCAN_NDAT2_ND42_Pos)              /*!< 0x00000400 */
+#define FDCAN_NDAT2_ND42          FDCAN_NDAT2_ND42_Msk                         /*!<New Data flag of Rx Buffer 42             */
+#define FDCAN_NDAT2_ND43_Pos      (11U)
+#define FDCAN_NDAT2_ND43_Msk      (0x1UL << FDCAN_NDAT2_ND43_Pos)              /*!< 0x00000800 */
+#define FDCAN_NDAT2_ND43          FDCAN_NDAT2_ND43_Msk                         /*!<New Data flag of Rx Buffer 43             */
+#define FDCAN_NDAT2_ND44_Pos      (12U)
+#define FDCAN_NDAT2_ND44_Msk      (0x1UL << FDCAN_NDAT2_ND44_Pos)              /*!< 0x00001000 */
+#define FDCAN_NDAT2_ND44          FDCAN_NDAT2_ND44_Msk                         /*!<New Data flag of Rx Buffer 44             */
+#define FDCAN_NDAT2_ND45_Pos      (13U)
+#define FDCAN_NDAT2_ND45_Msk      (0x1UL << FDCAN_NDAT2_ND45_Pos)              /*!< 0x00002000 */
+#define FDCAN_NDAT2_ND45          FDCAN_NDAT2_ND45_Msk                         /*!<New Data flag of Rx Buffer 45             */
+#define FDCAN_NDAT2_ND46_Pos      (14U)
+#define FDCAN_NDAT2_ND46_Msk      (0x1UL << FDCAN_NDAT2_ND46_Pos)              /*!< 0x00004000 */
+#define FDCAN_NDAT2_ND46          FDCAN_NDAT2_ND46_Msk                         /*!<New Data flag of Rx Buffer 46             */
+#define FDCAN_NDAT2_ND47_Pos      (15U)
+#define FDCAN_NDAT2_ND47_Msk      (0x1UL << FDCAN_NDAT2_ND47_Pos)              /*!< 0x00008000 */
+#define FDCAN_NDAT2_ND47          FDCAN_NDAT2_ND47_Msk                         /*!<New Data flag of Rx Buffer 47             */
+#define FDCAN_NDAT2_ND48_Pos      (16U)
+#define FDCAN_NDAT2_ND48_Msk      (0x1UL << FDCAN_NDAT2_ND48_Pos)              /*!< 0x00010000 */
+#define FDCAN_NDAT2_ND48          FDCAN_NDAT2_ND48_Msk                         /*!<New Data flag of Rx Buffer 48             */
+#define FDCAN_NDAT2_ND49_Pos      (17U)
+#define FDCAN_NDAT2_ND49_Msk      (0x1UL << FDCAN_NDAT2_ND49_Pos)              /*!< 0x00020000 */
+#define FDCAN_NDAT2_ND49          FDCAN_NDAT2_ND49_Msk                         /*!<New Data flag of Rx Buffer 49             */
+#define FDCAN_NDAT2_ND50_Pos      (18U)
+#define FDCAN_NDAT2_ND50_Msk      (0x1UL << FDCAN_NDAT2_ND50_Pos)              /*!< 0x00040000 */
+#define FDCAN_NDAT2_ND50          FDCAN_NDAT2_ND50_Msk                         /*!<New Data flag of Rx Buffer 50             */
+#define FDCAN_NDAT2_ND51_Pos      (19U)
+#define FDCAN_NDAT2_ND51_Msk      (0x1UL << FDCAN_NDAT2_ND51_Pos)              /*!< 0x00080000 */
+#define FDCAN_NDAT2_ND51          FDCAN_NDAT2_ND51_Msk                         /*!<New Data flag of Rx Buffer 51             */
+#define FDCAN_NDAT2_ND52_Pos      (20U)
+#define FDCAN_NDAT2_ND52_Msk      (0x1UL << FDCAN_NDAT2_ND52_Pos)              /*!< 0x00100000 */
+#define FDCAN_NDAT2_ND52          FDCAN_NDAT2_ND52_Msk                         /*!<New Data flag of Rx Buffer 52             */
+#define FDCAN_NDAT2_ND53_Pos      (21U)
+#define FDCAN_NDAT2_ND53_Msk      (0x1UL << FDCAN_NDAT2_ND53_Pos)              /*!< 0x00200000 */
+#define FDCAN_NDAT2_ND53          FDCAN_NDAT2_ND53_Msk                         /*!<New Data flag of Rx Buffer 53             */
+#define FDCAN_NDAT2_ND54_Pos      (22U)
+#define FDCAN_NDAT2_ND54_Msk      (0x1UL << FDCAN_NDAT2_ND54_Pos)              /*!< 0x00400000 */
+#define FDCAN_NDAT2_ND54          FDCAN_NDAT2_ND54_Msk                         /*!<New Data flag of Rx Buffer 54             */
+#define FDCAN_NDAT2_ND55_Pos      (23U)
+#define FDCAN_NDAT2_ND55_Msk      (0x1UL << FDCAN_NDAT2_ND55_Pos)              /*!< 0x00800000 */
+#define FDCAN_NDAT2_ND55          FDCAN_NDAT2_ND55_Msk                         /*!<New Data flag of Rx Buffer 55             */
+#define FDCAN_NDAT2_ND56_Pos      (24U)
+#define FDCAN_NDAT2_ND56_Msk      (0x1UL << FDCAN_NDAT2_ND56_Pos)              /*!< 0x01000000 */
+#define FDCAN_NDAT2_ND56          FDCAN_NDAT2_ND56_Msk                         /*!<New Data flag of Rx Buffer 56             */
+#define FDCAN_NDAT2_ND57_Pos      (25U)
+#define FDCAN_NDAT2_ND57_Msk      (0x1UL << FDCAN_NDAT2_ND57_Pos)              /*!< 0x02000000 */
+#define FDCAN_NDAT2_ND57          FDCAN_NDAT2_ND57_Msk                         /*!<New Data flag of Rx Buffer 57             */
+#define FDCAN_NDAT2_ND58_Pos      (26U)
+#define FDCAN_NDAT2_ND58_Msk      (0x1UL << FDCAN_NDAT2_ND58_Pos)              /*!< 0x04000000 */
+#define FDCAN_NDAT2_ND58          FDCAN_NDAT2_ND58_Msk                         /*!<New Data flag of Rx Buffer 58             */
+#define FDCAN_NDAT2_ND59_Pos      (27U)
+#define FDCAN_NDAT2_ND59_Msk      (0x1UL << FDCAN_NDAT2_ND59_Pos)              /*!< 0x08000000 */
+#define FDCAN_NDAT2_ND59          FDCAN_NDAT2_ND59_Msk                         /*!<New Data flag of Rx Buffer 59             */
+#define FDCAN_NDAT2_ND60_Pos      (28U)
+#define FDCAN_NDAT2_ND60_Msk      (0x1UL << FDCAN_NDAT2_ND60_Pos)              /*!< 0x10000000 */
+#define FDCAN_NDAT2_ND60          FDCAN_NDAT2_ND60_Msk                         /*!<New Data flag of Rx Buffer 60             */
+#define FDCAN_NDAT2_ND61_Pos      (29U)
+#define FDCAN_NDAT2_ND61_Msk      (0x1UL << FDCAN_NDAT2_ND61_Pos)              /*!< 0x20000000 */
+#define FDCAN_NDAT2_ND61          FDCAN_NDAT2_ND61_Msk                         /*!<New Data flag of Rx Buffer 61             */
+#define FDCAN_NDAT2_ND62_Pos      (30U)
+#define FDCAN_NDAT2_ND62_Msk      (0x1UL << FDCAN_NDAT2_ND62_Pos)              /*!< 0x40000000 */
+#define FDCAN_NDAT2_ND62          FDCAN_NDAT2_ND62_Msk                         /*!<New Data flag of Rx Buffer 62             */
+#define FDCAN_NDAT2_ND63_Pos      (31U)
+#define FDCAN_NDAT2_ND63_Msk      (0x1UL << FDCAN_NDAT2_ND63_Pos)              /*!< 0x80000000 */
+#define FDCAN_NDAT2_ND63          FDCAN_NDAT2_ND63_Msk                         /*!<New Data flag of Rx Buffer 63             */
+
+/*****************  Bit definition for FDCAN_RXF0C register  ********************/
+#define FDCAN_RXF0C_F0SA_Pos      (2U)
+#define FDCAN_RXF0C_F0SA_Msk      (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos)           /*!< 0x0000FFFC */
+#define FDCAN_RXF0C_F0SA          FDCAN_RXF0C_F0SA_Msk                         /*!<Rx FIFO 0 Start Address                   */
+#define FDCAN_RXF0C_F0S_Pos       (16U)
+#define FDCAN_RXF0C_F0S_Msk       (0x7FUL << FDCAN_RXF0C_F0S_Pos)              /*!< 0x007F0000 */
+#define FDCAN_RXF0C_F0S           FDCAN_RXF0C_F0S_Msk                          /*!<Number of Rx FIFO 0 elements              */
+#define FDCAN_RXF0C_F0WM_Pos      (24U)
+#define FDCAN_RXF0C_F0WM_Msk      (0x7FUL << FDCAN_RXF0C_F0WM_Pos)             /*!< 0x7F000000 */
+#define FDCAN_RXF0C_F0WM          FDCAN_RXF0C_F0WM_Msk                         /*!<FIFO 0 Watermark                          */
+#define FDCAN_RXF0C_F0OM_Pos      (31U)
+#define FDCAN_RXF0C_F0OM_Msk      (0x1UL << FDCAN_RXF0C_F0OM_Pos)              /*!< 0x80000000 */
+#define FDCAN_RXF0C_F0OM          FDCAN_RXF0C_F0OM_Msk                         /*!<FIFO 0 Operation Mode                     */
+
+/*****************  Bit definition for FDCAN_RXF0S register  ********************/
+#define FDCAN_RXF0S_F0FL_Pos      (0U)
+#define FDCAN_RXF0S_F0FL_Msk      (0x7FUL << FDCAN_RXF0S_F0FL_Pos)             /*!< 0x0000007F */
+#define FDCAN_RXF0S_F0FL          FDCAN_RXF0S_F0FL_Msk                         /*!<Rx FIFO 0 Fill Level                      */
+#define FDCAN_RXF0S_F0GI_Pos      (8U)
+#define FDCAN_RXF0S_F0GI_Msk      (0x3FUL << FDCAN_RXF0S_F0GI_Pos)             /*!< 0x00003F00 */
+#define FDCAN_RXF0S_F0GI          FDCAN_RXF0S_F0GI_Msk                         /*!<Rx FIFO 0 Get Index                       */
+#define FDCAN_RXF0S_F0PI_Pos      (16U)
+#define FDCAN_RXF0S_F0PI_Msk      (0x3FUL << FDCAN_RXF0S_F0PI_Pos)             /*!< 0x003F0000 */
+#define FDCAN_RXF0S_F0PI          FDCAN_RXF0S_F0PI_Msk                         /*!<Rx FIFO 0 Put Index                       */
+#define FDCAN_RXF0S_F0F_Pos       (24U)
+#define FDCAN_RXF0S_F0F_Msk       (0x1UL << FDCAN_RXF0S_F0F_Pos)               /*!< 0x01000000 */
+#define FDCAN_RXF0S_F0F           FDCAN_RXF0S_F0F_Msk                          /*!<Rx FIFO 0 Full                            */
+#define FDCAN_RXF0S_RF0L_Pos      (25U)
+#define FDCAN_RXF0S_RF0L_Msk      (0x1UL << FDCAN_RXF0S_RF0L_Pos)              /*!< 0x02000000 */
+#define FDCAN_RXF0S_RF0L          FDCAN_RXF0S_RF0L_Msk                         /*!<Rx FIFO 0 Message Lost                    */
+
+/*****************  Bit definition for FDCAN_RXF0A register  ********************/
+#define FDCAN_RXF0A_F0AI_Pos      (0U)
+#define FDCAN_RXF0A_F0AI_Msk      (0x3FUL << FDCAN_RXF0A_F0AI_Pos)             /*!< 0x0000003F */
+#define FDCAN_RXF0A_F0AI          FDCAN_RXF0A_F0AI_Msk                         /*!<Rx FIFO 0 Acknowledge Index               */
+
+/*****************  Bit definition for FDCAN_RXBC register  ********************/
+#define FDCAN_RXBC_RBSA_Pos       (2U)
+#define FDCAN_RXBC_RBSA_Msk       (0x3FFFUL << FDCAN_RXBC_RBSA_Pos)            /*!< 0x0000FFFC */
+#define FDCAN_RXBC_RBSA           FDCAN_RXBC_RBSA_Msk                          /*!<Rx Buffer Start Address                   */
+
+/*****************  Bit definition for FDCAN_RXF1C register  ********************/
+#define FDCAN_RXF1C_F1SA_Pos      (2U)
+#define FDCAN_RXF1C_F1SA_Msk      (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos)           /*!< 0x0000FFFC */
+#define FDCAN_RXF1C_F1SA          FDCAN_RXF1C_F1SA_Msk                         /*!<Rx FIFO 1 Start Address                   */
+#define FDCAN_RXF1C_F1S_Pos       (16U)
+#define FDCAN_RXF1C_F1S_Msk       (0x7FUL << FDCAN_RXF1C_F1S_Pos)              /*!< 0x007F0000 */
+#define FDCAN_RXF1C_F1S           FDCAN_RXF1C_F1S_Msk                          /*!<Number of Rx FIFO 1 elements              */
+#define FDCAN_RXF1C_F1WM_Pos      (24U)
+#define FDCAN_RXF1C_F1WM_Msk      (0x7FUL << FDCAN_RXF1C_F1WM_Pos)             /*!< 0x7F000000 */
+#define FDCAN_RXF1C_F1WM          FDCAN_RXF1C_F1WM_Msk                         /*!<Rx FIFO 1 Watermark                       */
+#define FDCAN_RXF1C_F1OM_Pos      (31U)
+#define FDCAN_RXF1C_F1OM_Msk      (0x1UL << FDCAN_RXF1C_F1OM_Pos)              /*!< 0x80000000 */
+#define FDCAN_RXF1C_F1OM          FDCAN_RXF1C_F1OM_Msk                         /*!<FIFO 1 Operation Mode                     */
+
+/*****************  Bit definition for FDCAN_RXF1S register  ********************/
+#define FDCAN_RXF1S_F1FL_Pos      (0U)
+#define FDCAN_RXF1S_F1FL_Msk      (0x7FUL << FDCAN_RXF1S_F1FL_Pos)             /*!< 0x0000007F */
+#define FDCAN_RXF1S_F1FL          FDCAN_RXF1S_F1FL_Msk                         /*!<Rx FIFO 1 Fill Level                      */
+#define FDCAN_RXF1S_F1GI_Pos      (8U)
+#define FDCAN_RXF1S_F1GI_Msk      (0x3FUL << FDCAN_RXF1S_F1GI_Pos)             /*!< 0x00003F00 */
+#define FDCAN_RXF1S_F1GI          FDCAN_RXF1S_F1GI_Msk                         /*!<Rx FIFO 1 Get Index                       */
+#define FDCAN_RXF1S_F1PI_Pos      (16U)
+#define FDCAN_RXF1S_F1PI_Msk      (0x3FUL << FDCAN_RXF1S_F1PI_Pos)             /*!< 0x003F0000 */
+#define FDCAN_RXF1S_F1PI          FDCAN_RXF1S_F1PI_Msk                         /*!<Rx FIFO 1 Put Index                       */
+#define FDCAN_RXF1S_F1F_Pos       (24U)
+#define FDCAN_RXF1S_F1F_Msk       (0x1UL << FDCAN_RXF1S_F1F_Pos)               /*!< 0x01000000 */
+#define FDCAN_RXF1S_F1F           FDCAN_RXF1S_F1F_Msk                          /*!<Rx FIFO 1 Full                            */
+#define FDCAN_RXF1S_RF1L_Pos      (25U)
+#define FDCAN_RXF1S_RF1L_Msk      (0x1UL << FDCAN_RXF1S_RF1L_Pos)              /*!< 0x02000000 */
+#define FDCAN_RXF1S_RF1L          FDCAN_RXF1S_RF1L_Msk                         /*!<Rx FIFO 1 Message Lost                    */
+
+/*****************  Bit definition for FDCAN_RXF1A register  ********************/
+#define FDCAN_RXF1A_F1AI_Pos      (0U)
+#define FDCAN_RXF1A_F1AI_Msk      (0x3FUL << FDCAN_RXF1A_F1AI_Pos)             /*!< 0x0000003F */
+#define FDCAN_RXF1A_F1AI          FDCAN_RXF1A_F1AI_Msk                         /*!<Rx FIFO 1 Acknowledge Index               */
+
+/*****************  Bit definition for FDCAN_RXESC register  ********************/
+#define FDCAN_RXESC_F0DS_Pos      (0U)
+#define FDCAN_RXESC_F0DS_Msk      (0x7UL << FDCAN_RXESC_F0DS_Pos)              /*!< 0x00000007 */
+#define FDCAN_RXESC_F0DS          FDCAN_RXESC_F0DS_Msk                         /*!<Rx FIFO 1 Data Field Size                 */
+#define FDCAN_RXESC_F1DS_Pos      (4U)
+#define FDCAN_RXESC_F1DS_Msk      (0x7UL << FDCAN_RXESC_F1DS_Pos)              /*!< 0x00000070 */
+#define FDCAN_RXESC_F1DS          FDCAN_RXESC_F1DS_Msk                         /*!<Rx FIFO 0 Data Field Size                 */
+#define FDCAN_RXESC_RBDS_Pos      (8U)
+#define FDCAN_RXESC_RBDS_Msk      (0x7UL << FDCAN_RXESC_RBDS_Pos)              /*!< 0x00000700 */
+#define FDCAN_RXESC_RBDS          FDCAN_RXESC_RBDS_Msk                         /*!<Rx Buffer Data Field Size                 */
+
+/*****************  Bit definition for FDCAN_TXBC register  *********************/
+#define FDCAN_TXBC_TBSA_Pos       (2U)
+#define FDCAN_TXBC_TBSA_Msk       (0x3FFFUL << FDCAN_TXBC_TBSA_Pos)            /*!< 0x0000FFFC */
+#define FDCAN_TXBC_TBSA           FDCAN_TXBC_TBSA_Msk                          /*!<Tx Buffers Start Address                  */
+#define FDCAN_TXBC_NDTB_Pos       (16U)
+#define FDCAN_TXBC_NDTB_Msk       (0x3FUL << FDCAN_TXBC_NDTB_Pos)              /*!< 0x003F0000 */
+#define FDCAN_TXBC_NDTB           FDCAN_TXBC_NDTB_Msk                          /*!<Number of Dedicated Transmit Buffers      */
+#define FDCAN_TXBC_TFQS_Pos       (24U)
+#define FDCAN_TXBC_TFQS_Msk       (0x3FUL << FDCAN_TXBC_TFQS_Pos)              /*!< 0x3F000000 */
+#define FDCAN_TXBC_TFQS           FDCAN_TXBC_TFQS_Msk                          /*!<Transmit FIFO/Queue Size                  */
+#define FDCAN_TXBC_TFQM_Pos       (30U)
+#define FDCAN_TXBC_TFQM_Msk       (0x1UL << FDCAN_TXBC_TFQM_Pos)               /*!< 0x40000000 */
+#define FDCAN_TXBC_TFQM           FDCAN_TXBC_TFQM_Msk                          /*!<Tx FIFO/Queue Mode                        */
+
+/*****************  Bit definition for FDCAN_TXFQS register  *********************/
+#define FDCAN_TXFQS_TFFL_Pos      (0U)
+#define FDCAN_TXFQS_TFFL_Msk      (0x3FUL << FDCAN_TXFQS_TFFL_Pos)             /*!< 0x0000003F */
+#define FDCAN_TXFQS_TFFL          FDCAN_TXFQS_TFFL_Msk                         /*!<Tx FIFO Free Level                        */
+#define FDCAN_TXFQS_TFGI_Pos      (8U)
+#define FDCAN_TXFQS_TFGI_Msk      (0x1FUL << FDCAN_TXFQS_TFGI_Pos)             /*!< 0x00001F00 */
+#define FDCAN_TXFQS_TFGI          FDCAN_TXFQS_TFGI_Msk                         /*!<Tx FIFO Get Index                         */
+#define FDCAN_TXFQS_TFQPI_Pos     (16U)
+#define FDCAN_TXFQS_TFQPI_Msk     (0x1FUL << FDCAN_TXFQS_TFQPI_Pos)            /*!< 0x001F0000 */
+#define FDCAN_TXFQS_TFQPI         FDCAN_TXFQS_TFQPI_Msk                        /*!<Tx FIFO/Queue Put Index                   */
+#define FDCAN_TXFQS_TFQF_Pos      (21U)
+#define FDCAN_TXFQS_TFQF_Msk      (0x1UL << FDCAN_TXFQS_TFQF_Pos)              /*!< 0x00200000 */
+#define FDCAN_TXFQS_TFQF          FDCAN_TXFQS_TFQF_Msk                         /*!<Tx FIFO/Queue Full                        */
+
+/*****************  Bit definition for FDCAN_TXESC register  *********************/
+#define FDCAN_TXESC_TBDS_Pos      (0U)
+#define FDCAN_TXESC_TBDS_Msk      (0x7UL << FDCAN_TXESC_TBDS_Pos)              /*!< 0x00000007 */
+#define FDCAN_TXESC_TBDS          FDCAN_TXESC_TBDS_Msk                         /*!<Tx Buffer Data Field Size                 */
+
+/*****************  Bit definition for FDCAN_TXBRP register  *********************/
+#define FDCAN_TXBRP_TRP_Pos       (0U)
+#define FDCAN_TXBRP_TRP_Msk       (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos)        /*!< 0xFFFFFFFF */
+#define FDCAN_TXBRP_TRP           FDCAN_TXBRP_TRP_Msk                          /*!<Transmission Request Pending              */
+
+/*****************  Bit definition for FDCAN_TXBAR register  *********************/
+#define FDCAN_TXBAR_AR_Pos        (0U)
+#define FDCAN_TXBAR_AR_Msk        (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos)         /*!< 0xFFFFFFFF */
+#define FDCAN_TXBAR_AR            FDCAN_TXBAR_AR_Msk                           /*!<Add Request                               */
+
+/*****************  Bit definition for FDCAN_TXBCR register  *********************/
+#define FDCAN_TXBCR_CR_Pos        (0U)
+#define FDCAN_TXBCR_CR_Msk        (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos)         /*!< 0xFFFFFFFF */
+#define FDCAN_TXBCR_CR            FDCAN_TXBCR_CR_Msk                           /*!<Cancellation Request                      */
+
+/*****************  Bit definition for FDCAN_TXBTO register  *********************/
+#define FDCAN_TXBTO_TO_Pos        (0U)
+#define FDCAN_TXBTO_TO_Msk        (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos)         /*!< 0xFFFFFFFF */
+#define FDCAN_TXBTO_TO            FDCAN_TXBTO_TO_Msk                           /*!<Transmission Occurred                     */
+
+/*****************  Bit definition for FDCAN_TXBCF register  *********************/
+#define FDCAN_TXBCF_CF_Pos        (0U)
+#define FDCAN_TXBCF_CF_Msk        (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos)         /*!< 0xFFFFFFFF */
+#define FDCAN_TXBCF_CF            FDCAN_TXBCF_CF_Msk                           /*!<Cancellation Finished                     */
+
+/*****************  Bit definition for FDCAN_TXBTIE register  ********************/
+#define FDCAN_TXBTIE_TIE_Pos      (0U)
+#define FDCAN_TXBTIE_TIE_Msk      (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos)       /*!< 0xFFFFFFFF */
+#define FDCAN_TXBTIE_TIE          FDCAN_TXBTIE_TIE_Msk                         /*!<Transmission Interrupt Enable             */
+
+/*****************  Bit definition for FDCAN_ TXBCIE register  *******************/
+#define FDCAN_TXBCIE_CFIE_Pos     (0U)
+#define FDCAN_TXBCIE_CFIE_Msk     (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos)      /*!< 0xFFFFFFFF */
+#define FDCAN_TXBCIE_CFIE         FDCAN_TXBCIE_CFIE_Msk                        /*!<Cancellation Finished Interrupt Enable    */
+
+/*****************  Bit definition for FDCAN_TXEFC register  *********************/
+#define FDCAN_TXEFC_EFSA_Pos      (2U)
+#define FDCAN_TXEFC_EFSA_Msk      (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos)           /*!< 0x0000FFFC */
+#define FDCAN_TXEFC_EFSA          FDCAN_TXEFC_EFSA_Msk                         /*!<Event FIFO Start Address                  */
+#define FDCAN_TXEFC_EFS_Pos       (16U)
+#define FDCAN_TXEFC_EFS_Msk       (0x3FUL << FDCAN_TXEFC_EFS_Pos)              /*!< 0x003F0000 */
+#define FDCAN_TXEFC_EFS           FDCAN_TXEFC_EFS_Msk                          /*!<Event FIFO Size                           */
+#define FDCAN_TXEFC_EFWM_Pos      (24U)
+#define FDCAN_TXEFC_EFWM_Msk      (0x3FUL << FDCAN_TXEFC_EFWM_Pos)             /*!< 0x3F000000 */
+#define FDCAN_TXEFC_EFWM          FDCAN_TXEFC_EFWM_Msk                         /*!<Event FIFO Watermark                      */
+
+/*****************  Bit definition for FDCAN_TXEFS register  *********************/
+#define FDCAN_TXEFS_EFFL_Pos      (0U)
+#define FDCAN_TXEFS_EFFL_Msk      (0x3FUL << FDCAN_TXEFS_EFFL_Pos)             /*!< 0x0000003F */
+#define FDCAN_TXEFS_EFFL          FDCAN_TXEFS_EFFL_Msk                         /*!<Event FIFO Fill Level                     */
+#define FDCAN_TXEFS_EFGI_Pos      (8U)
+#define FDCAN_TXEFS_EFGI_Msk      (0x1FUL << FDCAN_TXEFS_EFGI_Pos)             /*!< 0x00001F00 */
+#define FDCAN_TXEFS_EFGI          FDCAN_TXEFS_EFGI_Msk                         /*!<Event FIFO Get Index                      */
+#define FDCAN_TXEFS_EFPI_Pos      (16U)
+#define FDCAN_TXEFS_EFPI_Msk      (0x1FUL << FDCAN_TXEFS_EFPI_Pos)             /*!< 0x001F0000 */
+#define FDCAN_TXEFS_EFPI          FDCAN_TXEFS_EFPI_Msk                         /*!<Event FIFO Put Index                      */
+#define FDCAN_TXEFS_EFF_Pos       (24U)
+#define FDCAN_TXEFS_EFF_Msk       (0x1UL << FDCAN_TXEFS_EFF_Pos)               /*!< 0x01000000 */
+#define FDCAN_TXEFS_EFF           FDCAN_TXEFS_EFF_Msk                          /*!<Event FIFO Full                           */
+#define FDCAN_TXEFS_TEFL_Pos      (25U)
+#define FDCAN_TXEFS_TEFL_Msk      (0x1UL << FDCAN_TXEFS_TEFL_Pos)              /*!< 0x02000000 */
+#define FDCAN_TXEFS_TEFL          FDCAN_TXEFS_TEFL_Msk                         /*!<Tx Event FIFO Element Lost                */
+
+/*****************  Bit definition for FDCAN_TXEFA register  *********************/
+#define FDCAN_TXEFA_EFAI_Pos      (0U)
+#define FDCAN_TXEFA_EFAI_Msk      (0x1FUL << FDCAN_TXEFA_EFAI_Pos)             /*!< 0x0000001F */
+#define FDCAN_TXEFA_EFAI          FDCAN_TXEFA_EFAI_Msk                         /*!<Event FIFO Acknowledge Index              */
+
+/*****************  Bit definition for FDCAN_TTTMC register  *********************/
+#define FDCAN_TTTMC_TMSA_Pos      (2U)
+#define FDCAN_TTTMC_TMSA_Msk      (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos)           /*!< 0x0000FFFC */
+#define FDCAN_TTTMC_TMSA          FDCAN_TTTMC_TMSA_Msk                         /*!<Trigger Memory Start Address              */
+#define FDCAN_TTTMC_TME_Pos       (16U)
+#define FDCAN_TTTMC_TME_Msk       (0x7FUL << FDCAN_TTTMC_TME_Pos)              /*!< 0x007F0000 */
+#define FDCAN_TTTMC_TME           FDCAN_TTTMC_TME_Msk                          /*!<Trigger Memory Elements                   */
+
+/*****************  Bit definition for FDCAN_TTRMC register  *********************/
+#define FDCAN_TTRMC_RID_Pos       (0U)
+#define FDCAN_TTRMC_RID_Msk       (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos)        /*!< 0x1FFFFFFF */
+#define FDCAN_TTRMC_RID           FDCAN_TTRMC_RID_Msk                          /*!<Reference Identifier                      */
+#define FDCAN_TTRMC_XTD_Pos       (30U)
+#define FDCAN_TTRMC_XTD_Msk       (0x1UL << FDCAN_TTRMC_XTD_Pos)               /*!< 0x40000000 */
+#define FDCAN_TTRMC_XTD           FDCAN_TTRMC_XTD_Msk                          /*!< Extended Identifier                      */
+#define FDCAN_TTRMC_RMPS_Pos      (31U)
+#define FDCAN_TTRMC_RMPS_Msk      (0x1UL << FDCAN_TTRMC_RMPS_Pos)              /*!< 0x80000000 */
+#define FDCAN_TTRMC_RMPS          FDCAN_TTRMC_RMPS_Msk                         /*!<Reference Message Payload Select          */
+
+/*****************  Bit definition for FDCAN_TTOCF register  *********************/
+#define FDCAN_TTOCF_OM_Pos        (0U)
+#define FDCAN_TTOCF_OM_Msk        (0x3UL << FDCAN_TTOCF_OM_Pos)                /*!< 0x00000003 */
+#define FDCAN_TTOCF_OM            FDCAN_TTOCF_OM_Msk                           /*!<Operation Mode                            */
+#define FDCAN_TTOCF_GEN_Pos       (3U)
+#define FDCAN_TTOCF_GEN_Msk       (0x1UL << FDCAN_TTOCF_GEN_Pos)               /*!< 0x00000008 */
+#define FDCAN_TTOCF_GEN           FDCAN_TTOCF_GEN_Msk                          /*!<Gap Enable                                */
+#define FDCAN_TTOCF_TM_Pos        (4U)
+#define FDCAN_TTOCF_TM_Msk        (0x1UL << FDCAN_TTOCF_TM_Pos)                /*!< 0x00000010 */
+#define FDCAN_TTOCF_TM            FDCAN_TTOCF_TM_Msk                           /*!<Time Master                               */
+#define FDCAN_TTOCF_LDSDL_Pos     (5U)
+#define FDCAN_TTOCF_LDSDL_Msk     (0x7UL << FDCAN_TTOCF_LDSDL_Pos)             /*!< 0x000000E0 */
+#define FDCAN_TTOCF_LDSDL         FDCAN_TTOCF_LDSDL_Msk                        /*!<LD of Synchronization Deviation Limit     */
+#define FDCAN_TTOCF_IRTO_Pos      (8U)
+#define FDCAN_TTOCF_IRTO_Msk      (0x7FUL << FDCAN_TTOCF_IRTO_Pos)             /*!< 0x00007F00 */
+#define FDCAN_TTOCF_IRTO          FDCAN_TTOCF_IRTO_Msk                         /*!<Initial Reference Trigger Offset          */
+#define FDCAN_TTOCF_EECS_Pos      (15U)
+#define FDCAN_TTOCF_EECS_Msk      (0x1UL << FDCAN_TTOCF_EECS_Pos)              /*!< 0x00008000 */
+#define FDCAN_TTOCF_EECS          FDCAN_TTOCF_EECS_Msk                         /*!<Enable External Clock Synchronization     */
+#define FDCAN_TTOCF_AWL_Pos       (16U)
+#define FDCAN_TTOCF_AWL_Msk       (0xFFUL << FDCAN_TTOCF_AWL_Pos)              /*!< 0x00FF0000 */
+#define FDCAN_TTOCF_AWL           FDCAN_TTOCF_AWL_Msk                          /*!<Application Watchdog Limit                */
+#define FDCAN_TTOCF_EGTF_Pos      (24U)
+#define FDCAN_TTOCF_EGTF_Msk      (0x1UL << FDCAN_TTOCF_EGTF_Pos)              /*!< 0x01000000 */
+#define FDCAN_TTOCF_EGTF          FDCAN_TTOCF_EGTF_Msk                         /*!<Enable Global Time Filtering              */
+#define FDCAN_TTOCF_ECC_Pos       (25U)
+#define FDCAN_TTOCF_ECC_Msk       (0x1UL << FDCAN_TTOCF_ECC_Pos)               /*!< 0x02000000 */
+#define FDCAN_TTOCF_ECC           FDCAN_TTOCF_ECC_Msk                          /*!<Enable Clock Calibration                  */
+#define FDCAN_TTOCF_EVTP_Pos      (26U)
+#define FDCAN_TTOCF_EVTP_Msk      (0x1UL << FDCAN_TTOCF_EVTP_Pos)              /*!< 0x04000000 */
+#define FDCAN_TTOCF_EVTP          FDCAN_TTOCF_EVTP_Msk                         /*!<Event Trigger Polarity                    */
+
+/*****************  Bit definition for FDCAN_TTMLM register  *********************/
+#define FDCAN_TTMLM_CCM_Pos       (0U)
+#define FDCAN_TTMLM_CCM_Msk       (0x3FUL << FDCAN_TTMLM_CCM_Pos)              /*!< 0x0000003F */
+#define FDCAN_TTMLM_CCM           FDCAN_TTMLM_CCM_Msk                          /*!<Cycle Count Max                           */
+#define FDCAN_TTMLM_CSS_Pos       (6U)
+#define FDCAN_TTMLM_CSS_Msk       (0x3UL << FDCAN_TTMLM_CSS_Pos)               /*!< 0x000000C0 */
+#define FDCAN_TTMLM_CSS           FDCAN_TTMLM_CSS_Msk                          /*!<Cycle Start Synchronization               */
+#define FDCAN_TTMLM_TXEW_Pos      (8U)
+#define FDCAN_TTMLM_TXEW_Msk      (0xFUL << FDCAN_TTMLM_TXEW_Pos)              /*!< 0x00000F00 */
+#define FDCAN_TTMLM_TXEW          FDCAN_TTMLM_TXEW_Msk                         /*!<Tx Enable Window                          */
+#define FDCAN_TTMLM_ENTT_Pos      (16U)
+#define FDCAN_TTMLM_ENTT_Msk      (0xFFFUL << FDCAN_TTMLM_ENTT_Pos)            /*!< 0x0FFF0000 */
+#define FDCAN_TTMLM_ENTT          FDCAN_TTMLM_ENTT_Msk                         /*!<Expected Number of Tx Triggers            */
+
+/*****************  Bit definition for FDCAN_TURCF register  *********************/
+#define FDCAN_TURCF_NCL_Pos       (0U)
+#define FDCAN_TURCF_NCL_Msk       (0xFFFFUL << FDCAN_TURCF_NCL_Pos)            /*!< 0x0000FFFF */
+#define FDCAN_TURCF_NCL           FDCAN_TURCF_NCL_Msk                          /*!<Numerator Configuration Low               */
+#define FDCAN_TURCF_DC_Pos        (16U)
+#define FDCAN_TURCF_DC_Msk        (0x3FFFUL << FDCAN_TURCF_DC_Pos)             /*!< 0x3FFF0000 */
+#define FDCAN_TURCF_DC            FDCAN_TURCF_DC_Msk                           /*!<Denominator Configuration                 */
+#define FDCAN_TURCF_ELT_Pos       (31U)
+#define FDCAN_TURCF_ELT_Msk       (0x1UL << FDCAN_TURCF_ELT_Pos)               /*!< 0x80000000 */
+#define FDCAN_TURCF_ELT           FDCAN_TURCF_ELT_Msk                          /*!<Enable Local Time                         */
+
+/*****************  Bit definition for FDCAN_TTOCN register  ********************/
+#define FDCAN_TTOCN_SGT_Pos       (0U)
+#define FDCAN_TTOCN_SGT_Msk       (0x1UL << FDCAN_TTOCN_SGT_Pos)               /*!< 0x00000001 */
+#define FDCAN_TTOCN_SGT           FDCAN_TTOCN_SGT_Msk                          /*!<Set Global time                           */
+#define FDCAN_TTOCN_ECS_Pos       (1U)
+#define FDCAN_TTOCN_ECS_Msk       (0x1UL << FDCAN_TTOCN_ECS_Pos)               /*!< 0x00000002 */
+#define FDCAN_TTOCN_ECS           FDCAN_TTOCN_ECS_Msk                          /*!<External Clock Synchronization            */
+#define FDCAN_TTOCN_SWP_Pos       (2U)
+#define FDCAN_TTOCN_SWP_Msk       (0x1UL << FDCAN_TTOCN_SWP_Pos)               /*!< 0x00000004 */
+#define FDCAN_TTOCN_SWP           FDCAN_TTOCN_SWP_Msk                          /*!<Stop Watch Polarity                       */
+#define FDCAN_TTOCN_SWS_Pos       (3U)
+#define FDCAN_TTOCN_SWS_Msk       (0x3UL << FDCAN_TTOCN_SWS_Pos)               /*!< 0x00000018 */
+#define FDCAN_TTOCN_SWS           FDCAN_TTOCN_SWS_Msk                          /*!<Stop Watch Source                         */
+#define FDCAN_TTOCN_RTIE_Pos      (5U)
+#define FDCAN_TTOCN_RTIE_Msk      (0x1UL << FDCAN_TTOCN_RTIE_Pos)              /*!< 0x00000020 */
+#define FDCAN_TTOCN_RTIE          FDCAN_TTOCN_RTIE_Msk                         /*!<Register Time Mark Interrupt Pulse Enable */
+#define FDCAN_TTOCN_TMC_Pos       (6U)
+#define FDCAN_TTOCN_TMC_Msk       (0x3UL << FDCAN_TTOCN_TMC_Pos)               /*!< 0x000000C0 */
+#define FDCAN_TTOCN_TMC           FDCAN_TTOCN_TMC_Msk                          /*!<Register Time Mark Compare                */
+#define FDCAN_TTOCN_TTIE_Pos      (8U)
+#define FDCAN_TTOCN_TTIE_Msk      (0x1UL << FDCAN_TTOCN_TTIE_Pos)              /*!< 0x00000100 */
+#define FDCAN_TTOCN_TTIE          FDCAN_TTOCN_TTIE_Msk                         /*!<Trigger Time Mark Interrupt Pulse Enable  */
+#define FDCAN_TTOCN_GCS_Pos       (9U)
+#define FDCAN_TTOCN_GCS_Msk       (0x1UL << FDCAN_TTOCN_GCS_Pos)               /*!< 0x00000200 */
+#define FDCAN_TTOCN_GCS           FDCAN_TTOCN_GCS_Msk                          /*!<Gap Control Select                        */
+#define FDCAN_TTOCN_FGP_Pos       (10U)
+#define FDCAN_TTOCN_FGP_Msk       (0x1UL << FDCAN_TTOCN_FGP_Pos)               /*!< 0x00000400 */
+#define FDCAN_TTOCN_FGP           FDCAN_TTOCN_FGP_Msk                          /*!<Finish Gap                                */
+#define FDCAN_TTOCN_TMG_Pos       (11U)
+#define FDCAN_TTOCN_TMG_Msk       (0x1UL << FDCAN_TTOCN_TMG_Pos)               /*!< 0x00000800 */
+#define FDCAN_TTOCN_TMG           FDCAN_TTOCN_TMG_Msk                          /*!<Time Mark Gap                             */
+#define FDCAN_TTOCN_NIG_Pos       (12U)
+#define FDCAN_TTOCN_NIG_Msk       (0x1UL << FDCAN_TTOCN_NIG_Pos)               /*!< 0x00001000 */
+#define FDCAN_TTOCN_NIG           FDCAN_TTOCN_NIG_Msk                          /*!<Next is Gap                               */
+#define FDCAN_TTOCN_ESCN_Pos      (13U)
+#define FDCAN_TTOCN_ESCN_Msk      (0x1UL << FDCAN_TTOCN_ESCN_Pos)              /*!< 0x00002000 */
+#define FDCAN_TTOCN_ESCN          FDCAN_TTOCN_ESCN_Msk                         /*!<External Synchronization Control          */
+#define FDCAN_TTOCN_LCKC_Pos      (15U)
+#define FDCAN_TTOCN_LCKC_Msk      (0x1UL << FDCAN_TTOCN_LCKC_Pos)              /*!< 0x00008000 */
+#define FDCAN_TTOCN_LCKC          FDCAN_TTOCN_LCKC_Msk                         /*!<TT Operation Control Register Locked      */
+
+/*****************  Bit definition for FDCAN_TTGTP register  ********************/
+#define FDCAN_TTGTP_TP_Pos        (0U)
+#define FDCAN_TTGTP_TP_Msk        (0xFFFFUL << FDCAN_TTGTP_TP_Pos)             /*!< 0x0000FFFF */
+#define FDCAN_TTGTP_TP            FDCAN_TTGTP_TP_Msk                           /*!<Time Preset                               */
+#define FDCAN_TTGTP_CTP_Pos       (16U)
+#define FDCAN_TTGTP_CTP_Msk       (0xFFFFUL << FDCAN_TTGTP_CTP_Pos)            /*!< 0xFFFF0000 */
+#define FDCAN_TTGTP_CTP           FDCAN_TTGTP_CTP_Msk                          /*!<Cycle Time Target Phase                   */
+
+/*****************  Bit definition for FDCAN_TTTMK register  ********************/
+#define FDCAN_TTTMK_TM_Pos        (0U)
+#define FDCAN_TTTMK_TM_Msk        (0xFFFFUL << FDCAN_TTTMK_TM_Pos)             /*!< 0x0000FFFF */
+#define FDCAN_TTTMK_TM            FDCAN_TTTMK_TM_Msk                           /*!<Time Mark                                 */
+#define FDCAN_TTTMK_TICC_Pos      (16U)
+#define FDCAN_TTTMK_TICC_Msk      (0x7FUL << FDCAN_TTTMK_TICC_Pos)             /*!< 0x007F0000 */
+#define FDCAN_TTTMK_TICC          FDCAN_TTTMK_TICC_Msk                         /*!<Time Mark Cycle Code                      */
+#define FDCAN_TTTMK_LCKM_Pos      (31U)
+#define FDCAN_TTTMK_LCKM_Msk      (0x1UL << FDCAN_TTTMK_LCKM_Pos)              /*!< 0x80000000 */
+#define FDCAN_TTTMK_LCKM          FDCAN_TTTMK_LCKM_Msk                         /*!<TT Time Mark Register Locked              */
+
+/*****************  Bit definition for FDCAN_TTIR register  ********************/
+#define FDCAN_TTIR_SBC_Pos        (0U)
+#define FDCAN_TTIR_SBC_Msk        (0x1UL << FDCAN_TTIR_SBC_Pos)                /*!< 0x00000001 */
+#define FDCAN_TTIR_SBC            FDCAN_TTIR_SBC_Msk                           /*!<Start of Basic Cycle                      */
+#define FDCAN_TTIR_SMC_Pos        (1U)
+#define FDCAN_TTIR_SMC_Msk        (0x1UL << FDCAN_TTIR_SMC_Pos)                /*!< 0x00000002 */
+#define FDCAN_TTIR_SMC            FDCAN_TTIR_SMC_Msk                           /*!<Start of Matrix Cycle                     */
+#define FDCAN_TTIR_CSM_Pos        (2U)
+#define FDCAN_TTIR_CSM_Msk        (0x1UL << FDCAN_TTIR_CSM_Pos)                /*!< 0x00000004 */
+#define FDCAN_TTIR_CSM            FDCAN_TTIR_CSM_Msk                           /*!<Change of Synchronization Mode            */
+#define FDCAN_TTIR_SOG_Pos        (3U)
+#define FDCAN_TTIR_SOG_Msk        (0x1UL << FDCAN_TTIR_SOG_Pos)                /*!< 0x00000008 */
+#define FDCAN_TTIR_SOG            FDCAN_TTIR_SOG_Msk                           /*!<Start of Gap                              */
+#define FDCAN_TTIR_RTMI_Pos       (4U)
+#define FDCAN_TTIR_RTMI_Msk       (0x1UL << FDCAN_TTIR_RTMI_Pos)               /*!< 0x00000010 */
+#define FDCAN_TTIR_RTMI           FDCAN_TTIR_RTMI_Msk                          /*!<Register Time Mark Interrupt              */
+#define FDCAN_TTIR_TTMI_Pos       (5U)
+#define FDCAN_TTIR_TTMI_Msk       (0x1UL << FDCAN_TTIR_TTMI_Pos)               /*!< 0x00000020 */
+#define FDCAN_TTIR_TTMI           FDCAN_TTIR_TTMI_Msk                          /*!<Trigger Time Mark Event Internal          */
+#define FDCAN_TTIR_SWE_Pos        (6U)
+#define FDCAN_TTIR_SWE_Msk        (0x1UL << FDCAN_TTIR_SWE_Pos)                /*!< 0x00000040 */
+#define FDCAN_TTIR_SWE            FDCAN_TTIR_SWE_Msk                           /*!<Stop Watch Event                          */
+#define FDCAN_TTIR_GTW_Pos        (7U)
+#define FDCAN_TTIR_GTW_Msk        (0x1UL << FDCAN_TTIR_GTW_Pos)                /*!< 0x00000080 */
+#define FDCAN_TTIR_GTW            FDCAN_TTIR_GTW_Msk                           /*!<Global Time Wrap                          */
+#define FDCAN_TTIR_GTD_Pos        (8U)
+#define FDCAN_TTIR_GTD_Msk        (0x1UL << FDCAN_TTIR_GTD_Pos)                /*!< 0x00000100 */
+#define FDCAN_TTIR_GTD            FDCAN_TTIR_GTD_Msk                           /*!<Global Time Discontinuity                 */
+#define FDCAN_TTIR_GTE_Pos        (9U)
+#define FDCAN_TTIR_GTE_Msk        (0x1UL << FDCAN_TTIR_GTE_Pos)                /*!< 0x00000200 */
+#define FDCAN_TTIR_GTE            FDCAN_TTIR_GTE_Msk                           /*!<Global Time Error                         */
+#define FDCAN_TTIR_TXU_Pos        (10U)
+#define FDCAN_TTIR_TXU_Msk        (0x1UL << FDCAN_TTIR_TXU_Pos)                /*!< 0x00000400 */
+#define FDCAN_TTIR_TXU            FDCAN_TTIR_TXU_Msk                           /*!<Tx Count Underflow                        */
+#define FDCAN_TTIR_TXO_Pos        (11U)
+#define FDCAN_TTIR_TXO_Msk        (0x1UL << FDCAN_TTIR_TXO_Pos)                /*!< 0x00000800 */
+#define FDCAN_TTIR_TXO            FDCAN_TTIR_TXO_Msk                           /*!<Tx Count Overflow                         */
+#define FDCAN_TTIR_SE1_Pos        (12U)
+#define FDCAN_TTIR_SE1_Msk        (0x1UL << FDCAN_TTIR_SE1_Pos)                /*!< 0x00001000 */
+#define FDCAN_TTIR_SE1            FDCAN_TTIR_SE1_Msk                           /*!<Scheduling Error 1                        */
+#define FDCAN_TTIR_SE2_Pos        (13U)
+#define FDCAN_TTIR_SE2_Msk        (0x1UL << FDCAN_TTIR_SE2_Pos)                /*!< 0x00002000 */
+#define FDCAN_TTIR_SE2            FDCAN_TTIR_SE2_Msk                           /*!<Scheduling Error 2                        */
+#define FDCAN_TTIR_ELC_Pos        (14U)
+#define FDCAN_TTIR_ELC_Msk        (0x1UL << FDCAN_TTIR_ELC_Pos)                /*!< 0x00004000 */
+#define FDCAN_TTIR_ELC            FDCAN_TTIR_ELC_Msk                           /*!<Error Level Changed                       */
+#define FDCAN_TTIR_IWT_Pos        (15U)
+#define FDCAN_TTIR_IWT_Msk        (0x1UL << FDCAN_TTIR_IWT_Pos)                /*!< 0x00008000 */
+#define FDCAN_TTIR_IWT            FDCAN_TTIR_IWT_Msk                           /*!<Initialization Watch Trigger              */
+#define FDCAN_TTIR_WT_Pos         (16U)
+#define FDCAN_TTIR_WT_Msk         (0x1UL << FDCAN_TTIR_WT_Pos)                 /*!< 0x00010000 */
+#define FDCAN_TTIR_WT             FDCAN_TTIR_WT_Msk                            /*!<Watch Trigger                             */
+#define FDCAN_TTIR_AW_Pos         (17U)
+#define FDCAN_TTIR_AW_Msk         (0x1UL << FDCAN_TTIR_AW_Pos)                 /*!< 0x00020000 */
+#define FDCAN_TTIR_AW             FDCAN_TTIR_AW_Msk                            /*!<Application Watchdog                      */
+#define FDCAN_TTIR_CER_Pos        (18U)
+#define FDCAN_TTIR_CER_Msk        (0x1UL << FDCAN_TTIR_CER_Pos)                /*!< 0x00040000 */
+#define FDCAN_TTIR_CER            FDCAN_TTIR_CER_Msk                           /*!<Configuration Error                       */
+
+/*****************  Bit definition for FDCAN_TTIE register  ********************/
+#define FDCAN_TTIE_SBCE_Pos       (0U)
+#define FDCAN_TTIE_SBCE_Msk       (0x1UL << FDCAN_TTIE_SBCE_Pos)               /*!< 0x00000001 */
+#define FDCAN_TTIE_SBCE           FDCAN_TTIE_SBCE_Msk                          /*!<Start of Basic Cycle Interrupt Enable             */
+#define FDCAN_TTIE_SMCE_Pos       (1U)
+#define FDCAN_TTIE_SMCE_Msk       (0x1UL << FDCAN_TTIE_SMCE_Pos)               /*!< 0x00000002 */
+#define FDCAN_TTIE_SMCE           FDCAN_TTIE_SMCE_Msk                          /*!<Start of Matrix Cycle Interrupt Enable            */
+#define FDCAN_TTIE_CSME_Pos       (2U)
+#define FDCAN_TTIE_CSME_Msk       (0x1UL << FDCAN_TTIE_CSME_Pos)               /*!< 0x00000004 */
+#define FDCAN_TTIE_CSME           FDCAN_TTIE_CSME_Msk                          /*!<Change of Synchronization Mode Interrupt Enable   */
+#define FDCAN_TTIE_SOGE_Pos       (3U)
+#define FDCAN_TTIE_SOGE_Msk       (0x1UL << FDCAN_TTIE_SOGE_Pos)               /*!< 0x00000008 */
+#define FDCAN_TTIE_SOGE           FDCAN_TTIE_SOGE_Msk                          /*!<Start of Gap Interrupt Enable                     */
+#define FDCAN_TTIE_RTMIE_Pos      (4U)
+#define FDCAN_TTIE_RTMIE_Msk      (0x1UL << FDCAN_TTIE_RTMIE_Pos)              /*!< 0x00000010 */
+#define FDCAN_TTIE_RTMIE          FDCAN_TTIE_RTMIE_Msk                         /*!<Register Time Mark Interrupt Interrupt Enable     */
+#define FDCAN_TTIE_TTMIE_Pos      (5U)
+#define FDCAN_TTIE_TTMIE_Msk      (0x1UL << FDCAN_TTIE_TTMIE_Pos)              /*!< 0x00000020 */
+#define FDCAN_TTIE_TTMIE          FDCAN_TTIE_TTMIE_Msk                         /*!<Trigger Time Mark Event Internal Interrupt Enable */
+#define FDCAN_TTIE_SWEE_Pos       (6U)
+#define FDCAN_TTIE_SWEE_Msk       (0x1UL << FDCAN_TTIE_SWEE_Pos)               /*!< 0x00000040 */
+#define FDCAN_TTIE_SWEE           FDCAN_TTIE_SWEE_Msk                          /*!<Stop Watch Event Interrupt Enable                 */
+#define FDCAN_TTIE_GTWE_Pos       (7U)
+#define FDCAN_TTIE_GTWE_Msk       (0x1UL << FDCAN_TTIE_GTWE_Pos)               /*!< 0x00000080 */
+#define FDCAN_TTIE_GTWE           FDCAN_TTIE_GTWE_Msk                          /*!<Global Time Wrap Interrupt Enable                 */
+#define FDCAN_TTIE_GTDE_Pos       (8U)
+#define FDCAN_TTIE_GTDE_Msk       (0x1UL << FDCAN_TTIE_GTDE_Pos)               /*!< 0x00000100 */
+#define FDCAN_TTIE_GTDE           FDCAN_TTIE_GTDE_Msk                          /*!<Global Time Discontinuity Interrupt Enable        */
+#define FDCAN_TTIE_GTEE_Pos       (9U)
+#define FDCAN_TTIE_GTEE_Msk       (0x1UL << FDCAN_TTIE_GTEE_Pos)               /*!< 0x00000200 */
+#define FDCAN_TTIE_GTEE           FDCAN_TTIE_GTEE_Msk                          /*!<Global Time Error Interrupt Enable                */
+#define FDCAN_TTIE_TXUE_Pos       (10U)
+#define FDCAN_TTIE_TXUE_Msk       (0x1UL << FDCAN_TTIE_TXUE_Pos)               /*!< 0x00000400 */
+#define FDCAN_TTIE_TXUE           FDCAN_TTIE_TXUE_Msk                          /*!<Tx Count Underflow Interrupt Enable               */
+#define FDCAN_TTIE_TXOE_Pos       (11U)
+#define FDCAN_TTIE_TXOE_Msk       (0x1UL << FDCAN_TTIE_TXOE_Pos)               /*!< 0x00000800 */
+#define FDCAN_TTIE_TXOE           FDCAN_TTIE_TXOE_Msk                          /*!<Tx Count Overflow Interrupt Enable                */
+#define FDCAN_TTIE_SE1E_Pos       (12U)
+#define FDCAN_TTIE_SE1E_Msk       (0x1UL << FDCAN_TTIE_SE1E_Pos)               /*!< 0x00001000 */
+#define FDCAN_TTIE_SE1E           FDCAN_TTIE_SE1E_Msk                          /*!<Scheduling Error 1 Interrupt Enable               */
+#define FDCAN_TTIE_SE2E_Pos       (13U)
+#define FDCAN_TTIE_SE2E_Msk       (0x1UL << FDCAN_TTIE_SE2E_Pos)               /*!< 0x00002000 */
+#define FDCAN_TTIE_SE2E           FDCAN_TTIE_SE2E_Msk                          /*!<Scheduling Error 2 Interrupt Enable               */
+#define FDCAN_TTIE_ELCE_Pos       (14U)
+#define FDCAN_TTIE_ELCE_Msk       (0x1UL << FDCAN_TTIE_ELCE_Pos)               /*!< 0x00004000 */
+#define FDCAN_TTIE_ELCE           FDCAN_TTIE_ELCE_Msk                          /*!<Error Level Changed Interrupt Enable              */
+#define FDCAN_TTIE_IWTE_Pos       (15U)
+#define FDCAN_TTIE_IWTE_Msk       (0x1UL << FDCAN_TTIE_IWTE_Pos)               /*!< 0x00008000 */
+#define FDCAN_TTIE_IWTE           FDCAN_TTIE_IWTE_Msk                          /*!<Initialization Watch Trigger Interrupt Enable     */
+#define FDCAN_TTIE_WTE_Pos        (16U)
+#define FDCAN_TTIE_WTE_Msk        (0x1UL << FDCAN_TTIE_WTE_Pos)                /*!< 0x00010000 */
+#define FDCAN_TTIE_WTE            FDCAN_TTIE_WTE_Msk                           /*!<Watch Trigger Interrupt Enable                    */
+#define FDCAN_TTIE_AWE_Pos        (17U)
+#define FDCAN_TTIE_AWE_Msk        (0x1UL << FDCAN_TTIE_AWE_Pos)                /*!< 0x00020000 */
+#define FDCAN_TTIE_AWE            FDCAN_TTIE_AWE_Msk                           /*!<Application Watchdog Interrupt Enable             */
+#define FDCAN_TTIE_CERE_Pos       (18U)
+#define FDCAN_TTIE_CERE_Msk       (0x1UL << FDCAN_TTIE_CERE_Pos)               /*!< 0x00040000 */
+#define FDCAN_TTIE_CERE           FDCAN_TTIE_CERE_Msk                          /*!<Configuration Error Interrupt Enable              */
+
+/*****************  Bit definition for FDCAN_TTILS register  ********************/
+#define FDCAN_TTILS_SBCS_Pos      (0U)
+#define FDCAN_TTILS_SBCS_Msk      (0x1UL << FDCAN_TTILS_SBCS_Pos)              /*!< 0x00000001 */
+#define FDCAN_TTILS_SBCS          FDCAN_TTILS_SBCS_Msk                         /*!<Start of Basic Cycle Interrupt Line               */
+#define FDCAN_TTILS_SMCS_Pos      (1U)
+#define FDCAN_TTILS_SMCS_Msk      (0x1UL << FDCAN_TTILS_SMCS_Pos)              /*!< 0x00000002 */
+#define FDCAN_TTILS_SMCS          FDCAN_TTILS_SMCS_Msk                         /*!<Start of Matrix Cycle Interrupt Line              */
+#define FDCAN_TTILS_CSMS_Pos      (2U)
+#define FDCAN_TTILS_CSMS_Msk      (0x1UL << FDCAN_TTILS_CSMS_Pos)              /*!< 0x00000004 */
+#define FDCAN_TTILS_CSMS          FDCAN_TTILS_CSMS_Msk                         /*!<Change of Synchronization Mode Interrupt Line     */
+#define FDCAN_TTILS_SOGS_Pos      (3U)
+#define FDCAN_TTILS_SOGS_Msk      (0x1UL << FDCAN_TTILS_SOGS_Pos)              /*!< 0x00000008 */
+#define FDCAN_TTILS_SOGS          FDCAN_TTILS_SOGS_Msk                         /*!<Start of Gap Interrupt Line                       */
+#define FDCAN_TTILS_RTMIS_Pos     (4U)
+#define FDCAN_TTILS_RTMIS_Msk     (0x1UL << FDCAN_TTILS_RTMIS_Pos)             /*!< 0x00000010 */
+#define FDCAN_TTILS_RTMIS         FDCAN_TTILS_RTMIS_Msk                        /*!<Register Time Mark Interrupt Interrupt Line       */
+#define FDCAN_TTILS_TTMIS_Pos     (5U)
+#define FDCAN_TTILS_TTMIS_Msk     (0x1UL << FDCAN_TTILS_TTMIS_Pos)             /*!< 0x00000020 */
+#define FDCAN_TTILS_TTMIS         FDCAN_TTILS_TTMIS_Msk                        /*!<Trigger Time Mark Event Internal Interrupt Line   */
+#define FDCAN_TTILS_SWES_Pos      (6U)
+#define FDCAN_TTILS_SWES_Msk      (0x1UL << FDCAN_TTILS_SWES_Pos)              /*!< 0x00000040 */
+#define FDCAN_TTILS_SWES          FDCAN_TTILS_SWES_Msk                         /*!<Stop Watch Event Interrupt Line                   */
+#define FDCAN_TTILS_GTWS_Pos      (7U)
+#define FDCAN_TTILS_GTWS_Msk      (0x1UL << FDCAN_TTILS_GTWS_Pos)              /*!< 0x00000080 */
+#define FDCAN_TTILS_GTWS          FDCAN_TTILS_GTWS_Msk                         /*!<Global Time Wrap Interrupt Line                   */
+#define FDCAN_TTILS_GTDS_Pos      (8U)
+#define FDCAN_TTILS_GTDS_Msk      (0x1UL << FDCAN_TTILS_GTDS_Pos)              /*!< 0x00000100 */
+#define FDCAN_TTILS_GTDS          FDCAN_TTILS_GTDS_Msk                         /*!<Global Time Discontinuity Interrupt Line          */
+#define FDCAN_TTILS_GTES_Pos      (9U)
+#define FDCAN_TTILS_GTES_Msk      (0x1UL << FDCAN_TTILS_GTES_Pos)              /*!< 0x00000200 */
+#define FDCAN_TTILS_GTES          FDCAN_TTILS_GTES_Msk                         /*!<Global Time Error Interrupt Line                  */
+#define FDCAN_TTILS_TXUS_Pos      (10U)
+#define FDCAN_TTILS_TXUS_Msk      (0x1UL << FDCAN_TTILS_TXUS_Pos)              /*!< 0x00000400 */
+#define FDCAN_TTILS_TXUS          FDCAN_TTILS_TXUS_Msk                         /*!<Tx Count Underflow Interrupt Line                 */
+#define FDCAN_TTILS_TXOS_Pos      (11U)
+#define FDCAN_TTILS_TXOS_Msk      (0x1UL << FDCAN_TTILS_TXOS_Pos)              /*!< 0x00000800 */
+#define FDCAN_TTILS_TXOS          FDCAN_TTILS_TXOS_Msk                         /*!<Tx Count Overflow Interrupt Line                  */
+#define FDCAN_TTILS_SE1S_Pos      (12U)
+#define FDCAN_TTILS_SE1S_Msk      (0x1UL << FDCAN_TTILS_SE1S_Pos)              /*!< 0x00001000 */
+#define FDCAN_TTILS_SE1S          FDCAN_TTILS_SE1S_Msk                         /*!<Scheduling Error 1 Interrupt Line                 */
+#define FDCAN_TTILS_SE2S_Pos      (13U)
+#define FDCAN_TTILS_SE2S_Msk      (0x1UL << FDCAN_TTILS_SE2S_Pos)              /*!< 0x00002000 */
+#define FDCAN_TTILS_SE2S          FDCAN_TTILS_SE2S_Msk                         /*!<Scheduling Error 2 Interrupt Line                 */
+#define FDCAN_TTILS_ELCS_Pos      (14U)
+#define FDCAN_TTILS_ELCS_Msk      (0x1UL << FDCAN_TTILS_ELCS_Pos)              /*!< 0x00004000 */
+#define FDCAN_TTILS_ELCS          FDCAN_TTILS_ELCS_Msk                         /*!<Error Level Changed Interrupt Line                */
+#define FDCAN_TTILS_IWTS_Pos      (15U)
+#define FDCAN_TTILS_IWTS_Msk      (0x1UL << FDCAN_TTILS_IWTS_Pos)              /*!< 0x00008000 */
+#define FDCAN_TTILS_IWTS          FDCAN_TTILS_IWTS_Msk                         /*!<Initialization Watch Trigger Interrupt Line       */
+#define FDCAN_TTILS_WTS_Pos       (16U)
+#define FDCAN_TTILS_WTS_Msk       (0x1UL << FDCAN_TTILS_WTS_Pos)               /*!< 0x00010000 */
+#define FDCAN_TTILS_WTS           FDCAN_TTILS_WTS_Msk                          /*!<Watch Trigger Interrupt Line                      */
+#define FDCAN_TTILS_AWS_Pos       (17U)
+#define FDCAN_TTILS_AWS_Msk       (0x1UL << FDCAN_TTILS_AWS_Pos)               /*!< 0x00020000 */
+#define FDCAN_TTILS_AWS           FDCAN_TTILS_AWS_Msk                          /*!<Application Watchdog Interrupt Line               */
+#define FDCAN_TTILS_CERS_Pos      (18U)
+#define FDCAN_TTILS_CERS_Msk      (0x1UL << FDCAN_TTILS_CERS_Pos)              /*!< 0x00040000 */
+#define FDCAN_TTILS_CERS          FDCAN_TTILS_CERS_Msk                         /*!<Configuration Error Interrupt Line                */
+
+/*****************  Bit definition for FDCAN_TTOST register  ********************/
+#define FDCAN_TTOST_EL_Pos        (0U)
+#define FDCAN_TTOST_EL_Msk        (0x3UL << FDCAN_TTOST_EL_Pos)                /*!< 0x00000003 */
+#define FDCAN_TTOST_EL            FDCAN_TTOST_EL_Msk                           /*!<Error Level                              */
+#define FDCAN_TTOST_MS_Pos        (2U)
+#define FDCAN_TTOST_MS_Msk        (0x3UL << FDCAN_TTOST_MS_Pos)                /*!< 0x0000000C */
+#define FDCAN_TTOST_MS            FDCAN_TTOST_MS_Msk                           /*!<Master State                             */
+#define FDCAN_TTOST_SYS_Pos       (4U)
+#define FDCAN_TTOST_SYS_Msk       (0x3UL << FDCAN_TTOST_SYS_Pos)               /*!< 0x00000030 */
+#define FDCAN_TTOST_SYS           FDCAN_TTOST_SYS_Msk                          /*!<Synchronization State                    */
+#define FDCAN_TTOST_QGTP_Pos      (6U)
+#define FDCAN_TTOST_QGTP_Msk      (0x1UL << FDCAN_TTOST_QGTP_Pos)              /*!< 0x00000040 */
+#define FDCAN_TTOST_QGTP          FDCAN_TTOST_QGTP_Msk                         /*!<Quality of Global Time Phase             */
+#define FDCAN_TTOST_QCS_Pos       (7U)
+#define FDCAN_TTOST_QCS_Msk       (0x1UL << FDCAN_TTOST_QCS_Pos)               /*!< 0x00000080 */
+#define FDCAN_TTOST_QCS           FDCAN_TTOST_QCS_Msk                          /*!<Quality of Clock Speed                   */
+#define FDCAN_TTOST_RTO_Pos       (8U)
+#define FDCAN_TTOST_RTO_Msk       (0xFFUL << FDCAN_TTOST_RTO_Pos)              /*!< 0x0000FF00 */
+#define FDCAN_TTOST_RTO           FDCAN_TTOST_RTO_Msk                          /*!<Reference Trigger Offset                 */
+#define FDCAN_TTOST_WGTD_Pos      (22U)
+#define FDCAN_TTOST_WGTD_Msk      (0x1UL << FDCAN_TTOST_WGTD_Pos)              /*!< 0x00400000 */
+#define FDCAN_TTOST_WGTD          FDCAN_TTOST_WGTD_Msk                         /*!<Wait for Global Time Discontinuity       */
+#define FDCAN_TTOST_GFI_Pos       (23U)
+#define FDCAN_TTOST_GFI_Msk       (0x1UL << FDCAN_TTOST_GFI_Pos)               /*!< 0x00800000 */
+#define FDCAN_TTOST_GFI           FDCAN_TTOST_GFI_Msk                          /*!<Gap Finished Indicator                   */
+#define FDCAN_TTOST_TMP_Pos       (24U)
+#define FDCAN_TTOST_TMP_Msk       (0x7UL << FDCAN_TTOST_TMP_Pos)               /*!< 0x07000000 */
+#define FDCAN_TTOST_TMP           FDCAN_TTOST_TMP_Msk                          /*!<Time Master Priority                     */
+#define FDCAN_TTOST_GSI_Pos       (27U)
+#define FDCAN_TTOST_GSI_Msk       (0x1UL << FDCAN_TTOST_GSI_Pos)               /*!< 0x08000000 */
+#define FDCAN_TTOST_GSI           FDCAN_TTOST_GSI_Msk                          /*!<Gap Started Indicator                    */
+#define FDCAN_TTOST_WFE_Pos       (28U)
+#define FDCAN_TTOST_WFE_Msk       (0x1UL << FDCAN_TTOST_WFE_Pos)               /*!< 0x10000000 */
+#define FDCAN_TTOST_WFE           FDCAN_TTOST_WFE_Msk                          /*!<Wait for Event                           */
+#define FDCAN_TTOST_AWE_Pos       (29U)
+#define FDCAN_TTOST_AWE_Msk       (0x1UL << FDCAN_TTOST_AWE_Pos)               /*!< 0x20000000 */
+#define FDCAN_TTOST_AWE           FDCAN_TTOST_AWE_Msk                          /*!<Application Watchdog Event               */
+#define FDCAN_TTOST_WECS_Pos      (30U)
+#define FDCAN_TTOST_WECS_Msk      (0x1UL << FDCAN_TTOST_WECS_Pos)              /*!< 0x40000000 */
+#define FDCAN_TTOST_WECS          FDCAN_TTOST_WECS_Msk                         /*!<Wait for External Clock Synchronization  */
+#define FDCAN_TTOST_SPL_Pos       (31U)
+#define FDCAN_TTOST_SPL_Msk       (0x1UL << FDCAN_TTOST_SPL_Pos)               /*!< 0x80000000 */
+#define FDCAN_TTOST_SPL           FDCAN_TTOST_SPL_Msk                          /*!<Schedule Phase Lock                      */
+
+/*****************  Bit definition for FDCAN_TURNA register  ********************/
+#define FDCAN_TURNA_NAV_Pos       (0U)
+#define FDCAN_TURNA_NAV_Msk       (0x3FFFFUL << FDCAN_TURNA_NAV_Pos)           /*!< 0x0003FFFF */
+#define FDCAN_TURNA_NAV           FDCAN_TURNA_NAV_Msk                          /*!<Numerator Actual Value                   */
+
+/*****************  Bit definition for FDCAN_TTLGT register  ********************/
+#define FDCAN_TTLGT_LT_Pos        (0U)
+#define FDCAN_TTLGT_LT_Msk        (0xFFFFUL << FDCAN_TTLGT_LT_Pos)             /*!< 0x0000FFFF */
+#define FDCAN_TTLGT_LT            FDCAN_TTLGT_LT_Msk                           /*!<Local Time                               */
+#define FDCAN_TTLGT_GT_Pos        (16U)
+#define FDCAN_TTLGT_GT_Msk        (0xFFFFUL << FDCAN_TTLGT_GT_Pos)             /*!< 0xFFFF0000 */
+#define FDCAN_TTLGT_GT            FDCAN_TTLGT_GT_Msk                           /*!<Global Time                              */
+
+/*****************  Bit definition for FDCAN_TTCTC register  ********************/
+#define FDCAN_TTCTC_CT_Pos        (0U)
+#define FDCAN_TTCTC_CT_Msk        (0xFFFFUL << FDCAN_TTCTC_CT_Pos)             /*!< 0x0000FFFF */
+#define FDCAN_TTCTC_CT            FDCAN_TTCTC_CT_Msk                           /*!<Cycle Time                               */
+#define FDCAN_TTCTC_CC_Pos        (16U)
+#define FDCAN_TTCTC_CC_Msk        (0x3FUL << FDCAN_TTCTC_CC_Pos)               /*!< 0x003F0000 */
+#define FDCAN_TTCTC_CC            FDCAN_TTCTC_CC_Msk                           /*!<Cycle Count                              */
+
+/*****************  Bit definition for FDCAN_TTCPT register  ********************/
+#define FDCAN_TTCPT_CCV_Pos       (0U)
+#define FDCAN_TTCPT_CCV_Msk       (0x3FUL << FDCAN_TTCPT_CCV_Pos)              /*!< 0x0000003F */
+#define FDCAN_TTCPT_CCV           FDCAN_TTCPT_CCV_Msk                          /*!<Cycle Count Value                        */
+#define FDCAN_TTCPT_SWV_Pos       (16U)
+#define FDCAN_TTCPT_SWV_Msk       (0xFFFFUL << FDCAN_TTCPT_SWV_Pos)            /*!< 0xFFFF0000 */
+#define FDCAN_TTCPT_SWV           FDCAN_TTCPT_SWV_Msk                          /*!<Stop Watch Value                         */
+
+/*****************  Bit definition for FDCAN_TTCSM register  ********************/
+#define FDCAN_TTCSM_CSM_Pos       (0U)
+#define FDCAN_TTCSM_CSM_Msk       (0xFFFFUL << FDCAN_TTCSM_CSM_Pos)            /*!< 0x0000FFFF */
+#define FDCAN_TTCSM_CSM           FDCAN_TTCSM_CSM_Msk                          /*!<Cycle Sync Mark                          */
+
+/*****************  Bit definition for FDCAN_TTTS register  *********************/
+#define FDCAN_TTTS_SWTSEL_Pos     (0U)
+#define FDCAN_TTTS_SWTSEL_Msk     (0x3UL << FDCAN_TTTS_SWTSEL_Pos)             /*!< 0x00000003 */
+#define FDCAN_TTTS_SWTSEL         FDCAN_TTTS_SWTSEL_Msk                        /*!<Stop watch trigger input selection       */
+#define FDCAN_TTTS_EVTSEL_Pos     (4U)
+#define FDCAN_TTTS_EVTSEL_Msk     (0x3UL << FDCAN_TTTS_EVTSEL_Pos)             /*!< 0x00000030 */
+#define FDCAN_TTTS_EVTSEL         FDCAN_TTTS_EVTSEL_Msk                        /*!<Event trigger input selection            */
+
+/********************************************************************************/
+/*                                                                              */
+/*                      FDCANCCU (Clock Calibration unit)                       */
+/*                                                                              */
+/********************************************************************************/
+
+/*****************  Bit definition for FDCANCCU_CREL register  ******************/
+#define FDCANCCU_CREL_DAY_Pos        (0U)
+#define FDCANCCU_CREL_DAY_Msk        (0xFFUL << FDCANCCU_CREL_DAY_Pos)         /*!< 0x000000FF */
+#define FDCANCCU_CREL_DAY            FDCANCCU_CREL_DAY_Msk                     /*!<Timestamp Day                           */
+#define FDCANCCU_CREL_MON_Pos        (8U)
+#define FDCANCCU_CREL_MON_Msk        (0xFFUL << FDCANCCU_CREL_MON_Pos)         /*!< 0x0000FF00 */
+#define FDCANCCU_CREL_MON            FDCANCCU_CREL_MON_Msk                     /*!<Timestamp Month                         */
+#define FDCANCCU_CREL_YEAR_Pos       (16U)
+#define FDCANCCU_CREL_YEAR_Msk       (0xFUL << FDCANCCU_CREL_YEAR_Pos)         /*!< 0x000F0000 */
+#define FDCANCCU_CREL_YEAR           FDCANCCU_CREL_YEAR_Msk                    /*!<Timestamp Year                          */
+#define FDCANCCU_CREL_SUBSTEP_Pos    (20U)
+#define FDCANCCU_CREL_SUBSTEP_Msk    (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos)      /*!< 0x00F00000 */
+#define FDCANCCU_CREL_SUBSTEP        FDCANCCU_CREL_SUBSTEP_Msk                 /*!<Sub-step of Core release                */
+#define FDCANCCU_CREL_STEP_Pos       (24U)
+#define FDCANCCU_CREL_STEP_Msk       (0xFUL << FDCANCCU_CREL_STEP_Pos)         /*!< 0x0F000000 */
+#define FDCANCCU_CREL_STEP           FDCANCCU_CREL_STEP_Msk                    /*!<Step of Core release                    */
+#define FDCANCCU_CREL_REL_Pos        (28U)
+#define FDCANCCU_CREL_REL_Msk        (0xFUL << FDCANCCU_CREL_REL_Pos)          /*!< 0xF0000000 */
+#define FDCANCCU_CREL_REL            FDCANCCU_CREL_REL_Msk                     /*!<Core release                            */
+
+/*****************  Bit definition for FDCANCCU_CCFG register  ******************/
+#define FDCANCCU_CCFG_TQBT_Pos       (0U)
+#define FDCANCCU_CCFG_TQBT_Msk       (0x1FUL << FDCANCCU_CCFG_TQBT_Pos)        /*!< 0x0000001F */
+#define FDCANCCU_CCFG_TQBT           FDCANCCU_CCFG_TQBT_Msk                    /*!<Time Quanta per Bit Time                */
+#define FDCANCCU_CCFG_BCC_Pos        (6U)
+#define FDCANCCU_CCFG_BCC_Msk        (0x1UL << FDCANCCU_CCFG_BCC_Pos)          /*!< 0x00000040 */
+#define FDCANCCU_CCFG_BCC            FDCANCCU_CCFG_BCC_Msk                     /*!<Bypass Clock Calibration                */
+#define FDCANCCU_CCFG_CFL_Pos        (7U)
+#define FDCANCCU_CCFG_CFL_Msk        (0x1UL << FDCANCCU_CCFG_CFL_Pos)          /*!< 0x00000080 */
+#define FDCANCCU_CCFG_CFL            FDCANCCU_CCFG_CFL_Msk                     /*!<Calibration Field Length                */
+#define FDCANCCU_CCFG_OCPM_Pos       (8U)
+#define FDCANCCU_CCFG_OCPM_Msk       (0xFFUL << FDCANCCU_CCFG_OCPM_Pos)        /*!< 0x0000FF00 */
+#define FDCANCCU_CCFG_OCPM           FDCANCCU_CCFG_OCPM_Msk                    /*!<Oscillator Clock Periods Minimum        */
+#define FDCANCCU_CCFG_CDIV_Pos       (16U)
+#define FDCANCCU_CCFG_CDIV_Msk       (0xFUL << FDCANCCU_CCFG_CDIV_Pos)         /*!< 0x000F0000 */
+#define FDCANCCU_CCFG_CDIV           FDCANCCU_CCFG_CDIV_Msk                    /*!<Clock Divider                           */
+#define FDCANCCU_CCFG_SWR_Pos        (31U)
+#define FDCANCCU_CCFG_SWR_Msk        (0x1UL << FDCANCCU_CCFG_SWR_Pos)          /*!< 0x80000000 */
+#define FDCANCCU_CCFG_SWR            FDCANCCU_CCFG_SWR_Msk                     /*!<Software Reset                          */
+
+/*****************  Bit definition for FDCANCCU_CSTAT register  *****************/
+#define FDCANCCU_CSTAT_OCPC_Pos      (0U)
+#define FDCANCCU_CSTAT_OCPC_Msk      (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos)    /*!< 0x0003FFFF */
+#define FDCANCCU_CSTAT_OCPC          FDCANCCU_CSTAT_OCPC_Msk                   /*!<Oscillator Clock Period Counter        */
+#define FDCANCCU_CSTAT_TQC_Pos       (18U)
+#define FDCANCCU_CSTAT_TQC_Msk       (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos)       /*!< 0x1FFC0000 */
+#define FDCANCCU_CSTAT_TQC           FDCANCCU_CSTAT_TQC_Msk                    /*!<Time Quanta Counter                    */
+#define FDCANCCU_CSTAT_CALS_Pos      (30U)
+#define FDCANCCU_CSTAT_CALS_Msk      (0x3UL << FDCANCCU_CSTAT_CALS_Pos)        /*!< 0xC0000000 */
+#define FDCANCCU_CSTAT_CALS          FDCANCCU_CSTAT_CALS_Msk                   /*!<Calibration State                      */
+
+/******************  Bit definition for FDCANCCU_CWD register  ******************/
+#define FDCANCCU_CWD_WDC_Pos         (0U)
+#define FDCANCCU_CWD_WDC_Msk         (0xFFFFUL << FDCANCCU_CWD_WDC_Pos)        /*!< 0x0000FFFF */
+#define FDCANCCU_CWD_WDC             FDCANCCU_CWD_WDC_Msk                      /*!<Watchdog Configuration                 */
+#define FDCANCCU_CWD_WDV_Pos         (16U)
+#define FDCANCCU_CWD_WDV_Msk         (0xFFFFUL << FDCANCCU_CWD_WDV_Pos)        /*!< 0xFFFF0000 */
+#define FDCANCCU_CWD_WDV             FDCANCCU_CWD_WDV_Msk                      /*!<Watchdog Value                         */
+
+/******************  Bit definition for FDCANCCU_IR register  *******************/
+#define FDCANCCU_IR_CWE_Pos          (0U)
+#define FDCANCCU_IR_CWE_Msk          (0x1UL << FDCANCCU_IR_CWE_Pos)            /*!< 0x00000001 */
+#define FDCANCCU_IR_CWE              FDCANCCU_IR_CWE_Msk                       /*!<Calibration Watchdog Event             */
+#define FDCANCCU_IR_CSC_Pos          (1U)
+#define FDCANCCU_IR_CSC_Msk          (0x1UL << FDCANCCU_IR_CSC_Pos)            /*!< 0x00000002 */
+#define FDCANCCU_IR_CSC              FDCANCCU_IR_CSC_Msk                       /*!<Calibration State Changed              */
+
+/******************  Bit definition for FDCANCCU_IE register  *******************/
+#define FDCANCCU_IE_CWEE_Pos         (0U)
+#define FDCANCCU_IE_CWEE_Msk         (0x1UL << FDCANCCU_IE_CWEE_Pos)           /*!< 0x00000001 */
+#define FDCANCCU_IE_CWEE             FDCANCCU_IE_CWEE_Msk                      /*!<Calibration Watchdog Event Enable      */
+#define FDCANCCU_IE_CSCE_Pos         (1U)
+#define FDCANCCU_IE_CSCE_Msk         (0x1UL << FDCANCCU_IE_CSCE_Pos)           /*!< 0x00000002 */
+#define FDCANCCU_IE_CSCE             FDCANCCU_IE_CSCE_Msk                      /*!<Calibration State Changed Enable       */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          HDMI-CEC (CEC)                                    */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for CEC_CR register  *********************/
+#define CEC_CR_CECEN_Pos         (0U)
+#define CEC_CR_CECEN_Msk         (0x1UL << CEC_CR_CECEN_Pos)                   /*!< 0x00000001 */
+#define CEC_CR_CECEN             CEC_CR_CECEN_Msk                              /*!< CEC Enable                                */
+#define CEC_CR_TXSOM_Pos         (1U)
+#define CEC_CR_TXSOM_Msk         (0x1UL << CEC_CR_TXSOM_Pos)                   /*!< 0x00000002 */
+#define CEC_CR_TXSOM             CEC_CR_TXSOM_Msk                              /*!< CEC Tx Start Of Message                   */
+#define CEC_CR_TXEOM_Pos         (2U)
+#define CEC_CR_TXEOM_Msk         (0x1UL << CEC_CR_TXEOM_Pos)                   /*!< 0x00000004 */
+#define CEC_CR_TXEOM             CEC_CR_TXEOM_Msk                              /*!< CEC Tx End Of Message                     */
+
+/*******************  Bit definition for CEC_CFGR register  *******************/
+#define CEC_CFGR_SFT_Pos         (0U)
+#define CEC_CFGR_SFT_Msk         (0x7UL << CEC_CFGR_SFT_Pos)                   /*!< 0x00000007 */
+#define CEC_CFGR_SFT             CEC_CFGR_SFT_Msk                              /*!< CEC Signal Free Time                      */
+#define CEC_CFGR_RXTOL_Pos       (3U)
+#define CEC_CFGR_RXTOL_Msk       (0x1UL << CEC_CFGR_RXTOL_Pos)                 /*!< 0x00000008 */
+#define CEC_CFGR_RXTOL           CEC_CFGR_RXTOL_Msk                            /*!< CEC Tolerance                             */
+#define CEC_CFGR_BRESTP_Pos      (4U)
+#define CEC_CFGR_BRESTP_Msk      (0x1UL << CEC_CFGR_BRESTP_Pos)                /*!< 0x00000010 */
+#define CEC_CFGR_BRESTP          CEC_CFGR_BRESTP_Msk                           /*!< CEC Rx Stop                               */
+#define CEC_CFGR_BREGEN_Pos      (5U)
+#define CEC_CFGR_BREGEN_Msk      (0x1UL << CEC_CFGR_BREGEN_Pos)                /*!< 0x00000020 */
+#define CEC_CFGR_BREGEN          CEC_CFGR_BREGEN_Msk                           /*!< CEC Bit Rising Error generation           */
+#define CEC_CFGR_LBPEGEN_Pos     (6U)
+#define CEC_CFGR_LBPEGEN_Msk     (0x1UL << CEC_CFGR_LBPEGEN_Pos)               /*!< 0x00000040 */
+#define CEC_CFGR_LBPEGEN         CEC_CFGR_LBPEGEN_Msk                          /*!< CEC Long Bit Period Error generation      */
+#define CEC_CFGR_SFTOPT_Pos      (8U)
+#define CEC_CFGR_SFTOPT_Msk      (0x1UL << CEC_CFGR_SFTOPT_Pos)                /*!< 0x00000100 */
+#define CEC_CFGR_SFTOPT          CEC_CFGR_SFTOPT_Msk                           /*!< CEC Signal Free Time optional             */
+#define CEC_CFGR_BRDNOGEN_Pos    (7U)
+#define CEC_CFGR_BRDNOGEN_Msk    (0x1UL << CEC_CFGR_BRDNOGEN_Pos)              /*!< 0x00000080 */
+#define CEC_CFGR_BRDNOGEN        CEC_CFGR_BRDNOGEN_Msk                         /*!< CEC Broadcast No error generation         */
+#define CEC_CFGR_OAR_Pos         (16U)
+#define CEC_CFGR_OAR_Msk         (0x7FFFUL << CEC_CFGR_OAR_Pos)                /*!< 0x7FFF0000 */
+#define CEC_CFGR_OAR             CEC_CFGR_OAR_Msk                              /*!< CEC Own Address                           */
+#define CEC_CFGR_LSTN_Pos        (31U)
+#define CEC_CFGR_LSTN_Msk        (0x1UL << CEC_CFGR_LSTN_Pos)                  /*!< 0x80000000 */
+#define CEC_CFGR_LSTN            CEC_CFGR_LSTN_Msk                             /*!< CEC Listen mode                           */
+
+/*******************  Bit definition for CEC_TXDR register  *******************/
+#define CEC_TXDR_TXD_Pos         (0U)
+#define CEC_TXDR_TXD_Msk         (0xFFUL << CEC_TXDR_TXD_Pos)                  /*!< 0x000000FF */
+#define CEC_TXDR_TXD             CEC_TXDR_TXD_Msk                              /*!< CEC Tx Data                               */
+
+/*******************  Bit definition for CEC_RXDR register  *******************/
+#define CEC_RXDR_RXD_Pos         (0U)
+#define CEC_RXDR_RXD_Msk         (0xFFUL << CEC_RXDR_RXD_Pos)                  /*!< 0x000000FF */
+#define CEC_RXDR_RXD             CEC_RXDR_RXD_Msk                              /*!< CEC Rx Data                               */
+
+/*******************  Bit definition for CEC_ISR register  ********************/
+#define CEC_ISR_RXBR_Pos         (0U)
+#define CEC_ISR_RXBR_Msk         (0x1UL << CEC_ISR_RXBR_Pos)                   /*!< 0x00000001 */
+#define CEC_ISR_RXBR             CEC_ISR_RXBR_Msk                              /*!< CEC Rx-Byte Received                      */
+#define CEC_ISR_RXEND_Pos        (1U)
+#define CEC_ISR_RXEND_Msk        (0x1UL << CEC_ISR_RXEND_Pos)                  /*!< 0x00000002 */
+#define CEC_ISR_RXEND            CEC_ISR_RXEND_Msk                             /*!< CEC End Of Reception                      */
+#define CEC_ISR_RXOVR_Pos        (2U)
+#define CEC_ISR_RXOVR_Msk        (0x1UL << CEC_ISR_RXOVR_Pos)                  /*!< 0x00000004 */
+#define CEC_ISR_RXOVR            CEC_ISR_RXOVR_Msk                             /*!< CEC Rx-Overrun                            */
+#define CEC_ISR_BRE_Pos          (3U)
+#define CEC_ISR_BRE_Msk          (0x1UL << CEC_ISR_BRE_Pos)                    /*!< 0x00000008 */
+#define CEC_ISR_BRE              CEC_ISR_BRE_Msk                               /*!< CEC Rx Bit Rising Error                   */
+#define CEC_ISR_SBPE_Pos         (4U)
+#define CEC_ISR_SBPE_Msk         (0x1UL << CEC_ISR_SBPE_Pos)                   /*!< 0x00000010 */
+#define CEC_ISR_SBPE             CEC_ISR_SBPE_Msk                              /*!< CEC Rx Short Bit period Error             */
+#define CEC_ISR_LBPE_Pos         (5U)
+#define CEC_ISR_LBPE_Msk         (0x1UL << CEC_ISR_LBPE_Pos)                   /*!< 0x00000020 */
+#define CEC_ISR_LBPE             CEC_ISR_LBPE_Msk                              /*!< CEC Rx Long Bit period Error              */
+#define CEC_ISR_RXACKE_Pos       (6U)
+#define CEC_ISR_RXACKE_Msk       (0x1UL << CEC_ISR_RXACKE_Pos)                 /*!< 0x00000040 */
+#define CEC_ISR_RXACKE           CEC_ISR_RXACKE_Msk                            /*!< CEC Rx Missing Acknowledge                */
+#define CEC_ISR_ARBLST_Pos       (7U)
+#define CEC_ISR_ARBLST_Msk       (0x1UL << CEC_ISR_ARBLST_Pos)                 /*!< 0x00000080 */
+#define CEC_ISR_ARBLST           CEC_ISR_ARBLST_Msk                            /*!< CEC Arbitration Lost                      */
+#define CEC_ISR_TXBR_Pos         (8U)
+#define CEC_ISR_TXBR_Msk         (0x1UL << CEC_ISR_TXBR_Pos)                   /*!< 0x00000100 */
+#define CEC_ISR_TXBR             CEC_ISR_TXBR_Msk                              /*!< CEC Tx Byte Request                       */
+#define CEC_ISR_TXEND_Pos        (9U)
+#define CEC_ISR_TXEND_Msk        (0x1UL << CEC_ISR_TXEND_Pos)                  /*!< 0x00000200 */
+#define CEC_ISR_TXEND            CEC_ISR_TXEND_Msk                             /*!< CEC End of Transmission                   */
+#define CEC_ISR_TXUDR_Pos        (10U)
+#define CEC_ISR_TXUDR_Msk        (0x1UL << CEC_ISR_TXUDR_Pos)                  /*!< 0x00000400 */
+#define CEC_ISR_TXUDR            CEC_ISR_TXUDR_Msk                             /*!< CEC Tx-Buffer Underrun                    */
+#define CEC_ISR_TXERR_Pos        (11U)
+#define CEC_ISR_TXERR_Msk        (0x1UL << CEC_ISR_TXERR_Pos)                  /*!< 0x00000800 */
+#define CEC_ISR_TXERR            CEC_ISR_TXERR_Msk                             /*!< CEC Tx-Error                              */
+#define CEC_ISR_TXACKE_Pos       (12U)
+#define CEC_ISR_TXACKE_Msk       (0x1UL << CEC_ISR_TXACKE_Pos)                 /*!< 0x00001000 */
+#define CEC_ISR_TXACKE           CEC_ISR_TXACKE_Msk                            /*!< CEC Tx Missing Acknowledge                */
+
+/*******************  Bit definition for CEC_IER register  ********************/
+#define CEC_IER_RXBRIE_Pos       (0U)
+#define CEC_IER_RXBRIE_Msk       (0x1UL << CEC_IER_RXBRIE_Pos)                 /*!< 0x00000001 */
+#define CEC_IER_RXBRIE           CEC_IER_RXBRIE_Msk                            /*!< CEC Rx-Byte Received IT Enable            */
+#define CEC_IER_RXENDIE_Pos      (1U)
+#define CEC_IER_RXENDIE_Msk      (0x1UL << CEC_IER_RXENDIE_Pos)                /*!< 0x00000002 */
+#define CEC_IER_RXENDIE          CEC_IER_RXENDIE_Msk                           /*!< CEC End Of Reception IT Enable            */
+#define CEC_IER_RXOVRIE_Pos      (2U)
+#define CEC_IER_RXOVRIE_Msk      (0x1UL << CEC_IER_RXOVRIE_Pos)                /*!< 0x00000004 */
+#define CEC_IER_RXOVRIE          CEC_IER_RXOVRIE_Msk                           /*!< CEC Rx-Overrun IT Enable                  */
+#define CEC_IER_BREIE_Pos        (3U)
+#define CEC_IER_BREIE_Msk        (0x1UL << CEC_IER_BREIE_Pos)                  /*!< 0x00000008 */
+#define CEC_IER_BREIE            CEC_IER_BREIE_Msk                             /*!< CEC Rx Bit Rising Error IT Enable         */
+#define CEC_IER_SBPEIE_Pos       (4U)
+#define CEC_IER_SBPEIE_Msk       (0x1UL << CEC_IER_SBPEIE_Pos)                 /*!< 0x00000010 */
+#define CEC_IER_SBPEIE           CEC_IER_SBPEIE_Msk                            /*!< CEC Rx Short Bit period Error IT Enable   */
+#define CEC_IER_LBPEIE_Pos       (5U)
+#define CEC_IER_LBPEIE_Msk       (0x1UL << CEC_IER_LBPEIE_Pos)                 /*!< 0x00000020 */
+#define CEC_IER_LBPEIE           CEC_IER_LBPEIE_Msk                            /*!< CEC Rx Long Bit period Error IT Enable    */
+#define CEC_IER_RXACKEIE_Pos     (6U)
+#define CEC_IER_RXACKEIE_Msk     (0x1UL << CEC_IER_RXACKEIE_Pos)               /*!< 0x00000040 */
+#define CEC_IER_RXACKEIE         CEC_IER_RXACKEIE_Msk                          /*!< CEC Rx Missing Acknowledge IT Enable      */
+#define CEC_IER_ARBLSTIE_Pos     (7U)
+#define CEC_IER_ARBLSTIE_Msk     (0x1UL << CEC_IER_ARBLSTIE_Pos)               /*!< 0x00000080 */
+#define CEC_IER_ARBLSTIE         CEC_IER_ARBLSTIE_Msk                          /*!< CEC Arbitration Lost IT Enable            */
+#define CEC_IER_TXBRIE_Pos       (8U)
+#define CEC_IER_TXBRIE_Msk       (0x1UL << CEC_IER_TXBRIE_Pos)                 /*!< 0x00000100 */
+#define CEC_IER_TXBRIE           CEC_IER_TXBRIE_Msk                            /*!< CEC Tx Byte Request  IT Enable            */
+#define CEC_IER_TXENDIE_Pos      (9U)
+#define CEC_IER_TXENDIE_Msk      (0x1UL << CEC_IER_TXENDIE_Pos)                /*!< 0x00000200 */
+#define CEC_IER_TXENDIE          CEC_IER_TXENDIE_Msk                           /*!< CEC End of Transmission IT Enable         */
+#define CEC_IER_TXUDRIE_Pos      (10U)
+#define CEC_IER_TXUDRIE_Msk      (0x1UL << CEC_IER_TXUDRIE_Pos)                /*!< 0x00000400 */
+#define CEC_IER_TXUDRIE          CEC_IER_TXUDRIE_Msk                           /*!< CEC Tx-Buffer Underrun IT Enable          */
+#define CEC_IER_TXERRIE_Pos      (11U)
+#define CEC_IER_TXERRIE_Msk      (0x1UL << CEC_IER_TXERRIE_Pos)                /*!< 0x00000800 */
+#define CEC_IER_TXERRIE          CEC_IER_TXERRIE_Msk                           /*!< CEC Tx-Error IT Enable                    */
+#define CEC_IER_TXACKEIE_Pos     (12U)
+#define CEC_IER_TXACKEIE_Msk     (0x1UL << CEC_IER_TXACKEIE_Pos)               /*!< 0x00001000 */
+#define CEC_IER_TXACKEIE         CEC_IER_TXACKEIE_Msk                          /*!< CEC Tx Missing Acknowledge IT Enable      */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRC calculation unit                              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CRC_DR register  *********************/
+#define CRC_DR_DR_Pos            (0U)
+#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)               /*!< 0xFFFFFFFF */
+#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define CRC_IDR_IDR_Pos          (0U)
+#define CRC_IDR_IDR_Msk          (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)             /*!< 0xFFFFFFFF */
+#define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 32-bit data register bits */
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define CRC_CR_RESET_Pos         (0U)
+#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                   /*!< 0x00000001 */
+#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE_Pos      (3U)
+#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000018 */
+#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
+#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
+#define CRC_CR_REV_IN_Pos        (5U)
+#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000060 */
+#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
+#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
+#define CRC_CR_REV_OUT_Pos       (7U)
+#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                 /*!< 0x00000080 */
+#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
+
+/*******************  Bit definition for CRC_INIT register  *******************/
+#define CRC_INIT_INIT_Pos        (0U)
+#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)           /*!< 0xFFFFFFFF */
+#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
+
+/*******************  Bit definition for CRC_POL register  ********************/
+#define CRC_POL_POL_Pos          (0U)
+#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)             /*!< 0xFFFFFFFF */
+#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRS Clock Recovery System                         */
+/******************************************************************************/
+
+/*******************  Bit definition for CRS_CR register  *********************/
+#define CRS_CR_SYNCOKIE_Pos       (0U)
+#define CRS_CR_SYNCOKIE_Msk       (0x1UL << CRS_CR_SYNCOKIE_Pos)               /*!< 0x00000001 */
+#define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /*!< SYNC event OK interrupt enable */
+#define CRS_CR_SYNCWARNIE_Pos     (1U)
+#define CRS_CR_SYNCWARNIE_Msk     (0x1UL << CRS_CR_SYNCWARNIE_Pos)             /*!< 0x00000002 */
+#define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /*!< SYNC warning interrupt enable */
+#define CRS_CR_ERRIE_Pos          (2U)
+#define CRS_CR_ERRIE_Msk          (0x1UL << CRS_CR_ERRIE_Pos)                  /*!< 0x00000004 */
+#define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /*!< SYNC error or trimming error interrupt enable */
+#define CRS_CR_ESYNCIE_Pos        (3U)
+#define CRS_CR_ESYNCIE_Msk        (0x1UL << CRS_CR_ESYNCIE_Pos)                /*!< 0x00000008 */
+#define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /*!< Expected SYNC interrupt enable */
+#define CRS_CR_CEN_Pos            (5U)
+#define CRS_CR_CEN_Msk            (0x1UL << CRS_CR_CEN_Pos)                    /*!< 0x00000020 */
+#define CRS_CR_CEN                CRS_CR_CEN_Msk                               /*!< Frequency error counter enable */
+#define CRS_CR_AUTOTRIMEN_Pos     (6U)
+#define CRS_CR_AUTOTRIMEN_Msk     (0x1UL << CRS_CR_AUTOTRIMEN_Pos)             /*!< 0x00000040 */
+#define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /*!< Automatic trimming enable */
+#define CRS_CR_SWSYNC_Pos         (7U)
+#define CRS_CR_SWSYNC_Msk         (0x1UL << CRS_CR_SWSYNC_Pos)                 /*!< 0x00000080 */
+#define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /*!< Generate software SYNC event */
+#define CRS_CR_TRIM_Pos           (8U)
+#define CRS_CR_TRIM_Msk           (0x3FUL << CRS_CR_TRIM_Pos)                  /*!< 0x00003F00 */
+#define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /*!< HSI48 oscillator smooth trimming */
+
+/*******************  Bit definition for CRS_CFGR register  *********************/
+#define CRS_CFGR_RELOAD_Pos       (0U)
+#define CRS_CFGR_RELOAD_Msk       (0xFFFFUL << CRS_CFGR_RELOAD_Pos)            /*!< 0x0000FFFF */
+#define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /*!< Counter reload value */
+#define CRS_CFGR_FELIM_Pos        (16U)
+#define CRS_CFGR_FELIM_Msk        (0xFFUL << CRS_CFGR_FELIM_Pos)               /*!< 0x00FF0000 */
+#define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /*!< Frequency error limit */
+
+#define CRS_CFGR_SYNCDIV_Pos      (24U)
+#define CRS_CFGR_SYNCDIV_Msk      (0x7UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x07000000 */
+#define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /*!< SYNC divider */
+#define CRS_CFGR_SYNCDIV_0        (0x1UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */
+#define CRS_CFGR_SYNCDIV_1        (0x2UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */
+#define CRS_CFGR_SYNCDIV_2        (0x4UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */
+
+#define CRS_CFGR_SYNCSRC_Pos      (28U)
+#define CRS_CFGR_SYNCSRC_Msk      (0x3UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x30000000 */
+#define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /*!< SYNC signal source selection */
+#define CRS_CFGR_SYNCSRC_0        (0x1UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */
+#define CRS_CFGR_SYNCSRC_1        (0x2UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */
+
+#define CRS_CFGR_SYNCPOL_Pos      (31U)
+#define CRS_CFGR_SYNCPOL_Msk      (0x1UL << CRS_CFGR_SYNCPOL_Pos)              /*!< 0x80000000 */
+#define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /*!< SYNC polarity selection */
+
+/*******************  Bit definition for CRS_ISR register  *********************/
+#define CRS_ISR_SYNCOKF_Pos       (0U)
+#define CRS_ISR_SYNCOKF_Msk       (0x1UL << CRS_ISR_SYNCOKF_Pos)               /*!< 0x00000001 */
+#define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /*!< SYNC event OK flag */
+#define CRS_ISR_SYNCWARNF_Pos     (1U)
+#define CRS_ISR_SYNCWARNF_Msk     (0x1UL << CRS_ISR_SYNCWARNF_Pos)             /*!< 0x00000002 */
+#define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /*!< SYNC warning flag */
+#define CRS_ISR_ERRF_Pos          (2U)
+#define CRS_ISR_ERRF_Msk          (0x1UL << CRS_ISR_ERRF_Pos)                  /*!< 0x00000004 */
+#define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /*!< Error flag */
+#define CRS_ISR_ESYNCF_Pos        (3U)
+#define CRS_ISR_ESYNCF_Msk        (0x1UL << CRS_ISR_ESYNCF_Pos)                /*!< 0x00000008 */
+#define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /*!< Expected SYNC flag */
+#define CRS_ISR_SYNCERR_Pos       (8U)
+#define CRS_ISR_SYNCERR_Msk       (0x1UL << CRS_ISR_SYNCERR_Pos)               /*!< 0x00000100 */
+#define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /*!< SYNC error */
+#define CRS_ISR_SYNCMISS_Pos      (9U)
+#define CRS_ISR_SYNCMISS_Msk      (0x1UL << CRS_ISR_SYNCMISS_Pos)              /*!< 0x00000200 */
+#define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /*!< SYNC missed */
+#define CRS_ISR_TRIMOVF_Pos       (10U)
+#define CRS_ISR_TRIMOVF_Msk       (0x1UL << CRS_ISR_TRIMOVF_Pos)               /*!< 0x00000400 */
+#define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /*!< Trimming overflow or underflow */
+#define CRS_ISR_FEDIR_Pos         (15U)
+#define CRS_ISR_FEDIR_Msk         (0x1UL << CRS_ISR_FEDIR_Pos)                 /*!< 0x00008000 */
+#define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /*!< Frequency error direction */
+#define CRS_ISR_FECAP_Pos         (16U)
+#define CRS_ISR_FECAP_Msk         (0xFFFFUL << CRS_ISR_FECAP_Pos)              /*!< 0xFFFF0000 */
+#define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /*!< Frequency error capture */
+
+/*******************  Bit definition for CRS_ICR register  *********************/
+#define CRS_ICR_SYNCOKC_Pos       (0U)
+#define CRS_ICR_SYNCOKC_Msk       (0x1UL << CRS_ICR_SYNCOKC_Pos)               /*!< 0x00000001 */
+#define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /*!< SYNC event OK clear flag */
+#define CRS_ICR_SYNCWARNC_Pos     (1U)
+#define CRS_ICR_SYNCWARNC_Msk     (0x1UL << CRS_ICR_SYNCWARNC_Pos)             /*!< 0x00000002 */
+#define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /*!< SYNC warning clear flag */
+#define CRS_ICR_ERRC_Pos          (2U)
+#define CRS_ICR_ERRC_Msk          (0x1UL << CRS_ICR_ERRC_Pos)                  /*!< 0x00000004 */
+#define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /*!< Error clear flag */
+#define CRS_ICR_ESYNCC_Pos        (3U)
+#define CRS_ICR_ESYNCC_Msk        (0x1UL << CRS_ICR_ESYNCC_Pos)                /*!< 0x00000008 */
+#define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /*!< Expected SYNC clear flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Digital to Analog Converter                           */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DAC_CR register  ********************/
+#define DAC_CR_EN1_Pos              (0U)
+#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                  /*!< 0x00000001 */
+#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */
+#define DAC_CR_TEN1_Pos             (1U)
+#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                 /*!< 0x00000002 */
+#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos            (2U)
+#define DAC_CR_TSEL1_Msk            (0xFUL << DAC_CR_TSEL1_Pos)                /*!< 0x0000003C */
+#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000004 */
+#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
+#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
+#define DAC_CR_TSEL1_3              (0x8UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
+
+
+#define DAC_CR_WAVE1_Pos            (6U)
+#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                /*!< 0x000000C0 */
+#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos            (8U)
+#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                /*!< 0x00000F00 */
+#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos           (12U)
+#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)               /*!< 0x00001000 */
+#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1_Pos        (13U)
+#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)            /*!< 0x00002000 */
+#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/
+#define DAC_CR_CEN1_Pos             (14U)
+#define DAC_CR_CEN1_Msk             (0x1UL << DAC_CR_CEN1_Pos)                 /*!< 0x00004000 */
+#define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/
+
+#define DAC_CR_EN2_Pos              (16U)
+#define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                  /*!< 0x00010000 */
+#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */
+#define DAC_CR_TEN2_Pos             (17U)
+#define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                 /*!< 0x00020000 */
+#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2_Pos            (18U)
+#define DAC_CR_TSEL2_Msk            (0xFUL << DAC_CR_TSEL2_Pos)                /*!< 0x003C0000 */
+#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00040000 */
+#define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */
+#define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */
+#define DAC_CR_TSEL2_3              (0x8UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */
+
+
+#define DAC_CR_WAVE2_Pos            (22U)
+#define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                /*!< 0x00C00000 */
+#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */
+#define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */
+
+#define DAC_CR_MAMP2_Pos            (24U)
+#define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                /*!< 0x0F000000 */
+#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */
+#define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */
+#define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */
+#define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */
+
+#define DAC_CR_DMAEN2_Pos           (28U)
+#define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)               /*!< 0x10000000 */
+#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2_Pos        (29U)
+#define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)            /*!< 0x20000000 */
+#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/
+#define DAC_CR_CEN2_Pos             (30U)
+#define DAC_CR_CEN2_Msk             (0x1UL << DAC_CR_CEN2_Pos)                 /*!< 0x40000000 */
+#define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/
+
+/*****************  Bit definition for DAC_SWTRIGR register  ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)
+#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)         /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)
+#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)         /*!< 0x00000002 */
+#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */
+
+/*****************  Bit definition for DAC_DHR12R1 register  ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos    (0U)
+#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)      /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L1 register  ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos    (4U)
+#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)      /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R1 register  ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos     (0U)
+#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)        /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12R2 register  ******************/
+#define DAC_DHR12R2_DACC2DHR_Pos    (0U)
+#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)      /*!< 0x00000FFF */
+#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L2 register  ******************/
+#define DAC_DHR12L2_DACC2DHR_Pos    (4U)
+#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)      /*!< 0x0000FFF0 */
+#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R2 register  ******************/
+#define DAC_DHR8R2_DACC2DHR_Pos     (0U)
+#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)        /*!< 0x000000FF */
+#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12RD register  ******************/
+#define DAC_DHR12RD_DACC1DHR_Pos    (0U)
+#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)      /*!< 0x00000FFF */
+#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR_Pos    (16U)
+#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)      /*!< 0x0FFF0000 */
+#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12LD register  ******************/
+#define DAC_DHR12LD_DACC1DHR_Pos    (4U)
+#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)      /*!< 0x0000FFF0 */
+#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR_Pos    (20U)
+#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)      /*!< 0xFFF00000 */
+#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8RD register  ******************/
+#define DAC_DHR8RD_DACC1DHR_Pos     (0U)
+#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)        /*!< 0x000000FF */
+#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR_Pos     (8U)
+#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)        /*!< 0x0000FF00 */
+#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
+
+/*******************  Bit definition for DAC_DOR1 register  *******************/
+#define DAC_DOR1_DACC1DOR_Pos       (0U)
+#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)         /*!< 0x00000FFF */
+#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */
+
+/*******************  Bit definition for DAC_DOR2 register  *******************/
+#define DAC_DOR2_DACC2DOR_Pos       (0U)
+#define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)         /*!< 0x00000FFF */
+#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */
+
+/********************  Bit definition for DAC_SR register  ********************/
+#define DAC_SR_DMAUDR1_Pos          (13U)
+#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)              /*!< 0x00002000 */
+#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_CAL_FLAG1_Pos        (14U)
+#define DAC_SR_CAL_FLAG1_Msk        (0x1UL << DAC_SR_CAL_FLAG1_Pos)            /*!< 0x00004000 */
+#define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */
+#define DAC_SR_BWST1_Pos            (15U)
+#define DAC_SR_BWST1_Msk            (0x4001UL << DAC_SR_BWST1_Pos)             /*!< 0x20008000 */
+#define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */
+
+#define DAC_SR_DMAUDR2_Pos          (29U)
+#define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)              /*!< 0x20000000 */
+#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */
+#define DAC_SR_CAL_FLAG2_Pos        (30U)
+#define DAC_SR_CAL_FLAG2_Msk        (0x1UL << DAC_SR_CAL_FLAG2_Pos)            /*!< 0x40000000 */
+#define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */
+#define DAC_SR_BWST2_Pos            (31U)
+#define DAC_SR_BWST2_Msk            (0x1UL << DAC_SR_BWST2_Pos)                /*!< 0x80000000 */
+#define DAC_SR_BWST2                DAC_SR_BWST2_Msk                           /*!<DAC channel2 busy writing sample time flag */
+
+/*******************  Bit definition for DAC_CCR register  ********************/
+#define DAC_CCR_OTRIM1_Pos          (0U)
+#define DAC_CCR_OTRIM1_Msk          (0x1FUL << DAC_CCR_OTRIM1_Pos)             /*!< 0x0000001F */
+#define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */
+#define DAC_CCR_OTRIM2_Pos          (16U)
+#define DAC_CCR_OTRIM2_Msk          (0x1FUL << DAC_CCR_OTRIM2_Pos)             /*!< 0x001F0000 */
+#define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */
+
+/*******************  Bit definition for DAC_MCR register  *******************/
+#define DAC_MCR_MODE1_Pos           (0U)
+#define DAC_MCR_MODE1_Msk           (0x7UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000007 */
+#define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */
+#define DAC_MCR_MODE1_0             (0x1UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000001 */
+#define DAC_MCR_MODE1_1             (0x2UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000002 */
+#define DAC_MCR_MODE1_2             (0x4UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000004 */
+
+#define DAC_MCR_MODE2_Pos           (16U)
+#define DAC_MCR_MODE2_Msk           (0x7UL << DAC_MCR_MODE2_Pos)               /*!< 0x00070000 */
+#define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */
+#define DAC_MCR_MODE2_0             (0x1UL << DAC_MCR_MODE2_Pos)                /*!< 0x00010000 */
+#define DAC_MCR_MODE2_1             (0x2UL << DAC_MCR_MODE2_Pos)                /*!< 0x00020000 */
+#define DAC_MCR_MODE2_2             (0x4UL << DAC_MCR_MODE2_Pos)                /*!< 0x00040000 */
+
+/******************  Bit definition for DAC_SHSR1 register  ******************/
+#define DAC_SHSR1_TSAMPLE1_Pos      (0U)
+#define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)        /*!< 0x000003FF */
+#define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */
+
+/******************  Bit definition for DAC_SHSR2 register  ******************/
+#define DAC_SHSR2_TSAMPLE2_Pos      (0U)
+#define DAC_SHSR2_TSAMPLE2_Msk      (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)        /*!< 0x000003FF */
+#define DAC_SHSR2_TSAMPLE2          DAC_SHSR2_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */
+
+/******************  Bit definition for DAC_SHHR register  ******************/
+#define DAC_SHHR_THOLD1_Pos         (0U)
+#define DAC_SHHR_THOLD1_Msk         (0x3FFUL << DAC_SHHR_THOLD1_Pos)           /*!< 0x000003FF */
+#define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */
+#define DAC_SHHR_THOLD2_Pos         (16U)
+#define DAC_SHHR_THOLD2_Msk         (0x3FFUL << DAC_SHHR_THOLD2_Pos)           /*!< 0x03FF0000 */
+#define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */
+
+/******************  Bit definition for DAC_SHRR register  ******************/
+#define DAC_SHRR_TREFRESH1_Pos      (0U)
+#define DAC_SHRR_TREFRESH1_Msk      (0xFFUL << DAC_SHRR_TREFRESH1_Pos)         /*!< 0x000000FF */
+#define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */
+#define DAC_SHRR_TREFRESH2_Pos      (16U)
+#define DAC_SHRR_TREFRESH2_Msk      (0xFFUL << DAC_SHRR_TREFRESH2_Pos)         /*!< 0x00FF0000 */
+#define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    DCMI                                    */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for DCMI_CR register  ******************/
+#define DCMI_CR_CAPTURE_Pos        (0U)
+#define DCMI_CR_CAPTURE_Msk        (0x1UL << DCMI_CR_CAPTURE_Pos)              /*!< 0x00000001 */
+#define DCMI_CR_CAPTURE            DCMI_CR_CAPTURE_Msk
+#define DCMI_CR_CM_Pos             (1U)
+#define DCMI_CR_CM_Msk             (0x1UL << DCMI_CR_CM_Pos)                   /*!< 0x00000002 */
+#define DCMI_CR_CM                 DCMI_CR_CM_Msk
+#define DCMI_CR_CROP_Pos           (2U)
+#define DCMI_CR_CROP_Msk           (0x1UL << DCMI_CR_CROP_Pos)                 /*!< 0x00000004 */
+#define DCMI_CR_CROP               DCMI_CR_CROP_Msk
+#define DCMI_CR_JPEG_Pos           (3U)
+#define DCMI_CR_JPEG_Msk           (0x1UL << DCMI_CR_JPEG_Pos)                 /*!< 0x00000008 */
+#define DCMI_CR_JPEG               DCMI_CR_JPEG_Msk
+#define DCMI_CR_ESS_Pos            (4U)
+#define DCMI_CR_ESS_Msk            (0x1UL << DCMI_CR_ESS_Pos)                  /*!< 0x00000010 */
+#define DCMI_CR_ESS                DCMI_CR_ESS_Msk
+#define DCMI_CR_PCKPOL_Pos         (5U)
+#define DCMI_CR_PCKPOL_Msk         (0x1UL << DCMI_CR_PCKPOL_Pos)               /*!< 0x00000020 */
+#define DCMI_CR_PCKPOL             DCMI_CR_PCKPOL_Msk
+#define DCMI_CR_HSPOL_Pos          (6U)
+#define DCMI_CR_HSPOL_Msk          (0x1UL << DCMI_CR_HSPOL_Pos)                /*!< 0x00000040 */
+#define DCMI_CR_HSPOL              DCMI_CR_HSPOL_Msk
+#define DCMI_CR_VSPOL_Pos          (7U)
+#define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                /*!< 0x00000080 */
+#define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk
+#define DCMI_CR_FCRC_0             ((uint32_t)0x00000100U)
+#define DCMI_CR_FCRC_1             ((uint32_t)0x00000200U)
+#define DCMI_CR_EDM_0              ((uint32_t)0x00000400U)
+#define DCMI_CR_EDM_1              ((uint32_t)0x00000800U)
+#define DCMI_CR_CRE_Pos            (12U)
+#define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                  /*!< 0x00001000 */
+#define DCMI_CR_CRE                DCMI_CR_CRE_Msk
+#define DCMI_CR_ENABLE_Pos         (14U)
+#define DCMI_CR_ENABLE_Msk         (0x1UL << DCMI_CR_ENABLE_Pos)               /*!< 0x00004000 */
+#define DCMI_CR_ENABLE             DCMI_CR_ENABLE_Msk
+#define DCMI_CR_BSM_Pos            (16U)
+#define DCMI_CR_BSM_Msk            (0x3UL << DCMI_CR_BSM_Pos)                  /*!< 0x00030000 */
+#define DCMI_CR_BSM                DCMI_CR_BSM_Msk
+#define DCMI_CR_BSM_0              (0x1UL << DCMI_CR_BSM_Pos)                   /*!< 0x00010000 */
+#define DCMI_CR_BSM_1              (0x2UL << DCMI_CR_BSM_Pos)                   /*!< 0x00020000 */
+#define DCMI_CR_OEBS_Pos           (18U)
+#define DCMI_CR_OEBS_Msk           (0x1UL << DCMI_CR_OEBS_Pos)                 /*!< 0x00040000 */
+#define DCMI_CR_OEBS               DCMI_CR_OEBS_Msk
+#define DCMI_CR_LSM_Pos            (19U)
+#define DCMI_CR_LSM_Msk            (0x1UL << DCMI_CR_LSM_Pos)                  /*!< 0x00080000 */
+#define DCMI_CR_LSM                DCMI_CR_LSM_Msk
+#define DCMI_CR_OELS_Pos           (20U)
+#define DCMI_CR_OELS_Msk           (0x1UL << DCMI_CR_OELS_Pos)                 /*!< 0x00100000 */
+#define DCMI_CR_OELS               DCMI_CR_OELS_Msk
+
+/********************  Bits definition for DCMI_SR register  ******************/
+#define DCMI_SR_HSYNC_Pos          (0U)
+#define DCMI_SR_HSYNC_Msk          (0x1UL << DCMI_SR_HSYNC_Pos)                /*!< 0x00000001 */
+#define DCMI_SR_HSYNC              DCMI_SR_HSYNC_Msk
+#define DCMI_SR_VSYNC_Pos          (1U)
+#define DCMI_SR_VSYNC_Msk          (0x1UL << DCMI_SR_VSYNC_Pos)                /*!< 0x00000002 */
+#define DCMI_SR_VSYNC              DCMI_SR_VSYNC_Msk
+#define DCMI_SR_FNE_Pos            (2U)
+#define DCMI_SR_FNE_Msk            (0x1UL << DCMI_SR_FNE_Pos)                  /*!< 0x00000004 */
+#define DCMI_SR_FNE                DCMI_SR_FNE_Msk
+
+/********************  Bits definition for DCMI_RIS register   ****************/
+#define DCMI_RIS_FRAME_RIS_Pos     (0U)
+#define DCMI_RIS_FRAME_RIS_Msk     (0x1UL << DCMI_RIS_FRAME_RIS_Pos)           /*!< 0x00000001 */
+#define DCMI_RIS_FRAME_RIS         DCMI_RIS_FRAME_RIS_Msk
+#define DCMI_RIS_OVR_RIS_Pos       (1U)
+#define DCMI_RIS_OVR_RIS_Msk       (0x1UL << DCMI_RIS_OVR_RIS_Pos)             /*!< 0x00000002 */
+#define DCMI_RIS_OVR_RIS           DCMI_RIS_OVR_RIS_Msk
+#define DCMI_RIS_ERR_RIS_Pos       (2U)
+#define DCMI_RIS_ERR_RIS_Msk       (0x1UL << DCMI_RIS_ERR_RIS_Pos)             /*!< 0x00000004 */
+#define DCMI_RIS_ERR_RIS           DCMI_RIS_ERR_RIS_Msk
+#define DCMI_RIS_VSYNC_RIS_Pos     (3U)
+#define DCMI_RIS_VSYNC_RIS_Msk     (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)           /*!< 0x00000008 */
+#define DCMI_RIS_VSYNC_RIS         DCMI_RIS_VSYNC_RIS_Msk
+#define DCMI_RIS_LINE_RIS_Pos      (4U)
+#define DCMI_RIS_LINE_RIS_Msk      (0x1UL << DCMI_RIS_LINE_RIS_Pos)            /*!< 0x00000010 */
+#define DCMI_RIS_LINE_RIS          DCMI_RIS_LINE_RIS_Msk
+
+/********************  Bits definition for DCMI_IER register  *****************/
+#define DCMI_IER_FRAME_IE_Pos      (0U)
+#define DCMI_IER_FRAME_IE_Msk      (0x1UL << DCMI_IER_FRAME_IE_Pos)            /*!< 0x00000001 */
+#define DCMI_IER_FRAME_IE          DCMI_IER_FRAME_IE_Msk
+#define DCMI_IER_OVR_IE_Pos        (1U)
+#define DCMI_IER_OVR_IE_Msk        (0x1UL << DCMI_IER_OVR_IE_Pos)              /*!< 0x00000002 */
+#define DCMI_IER_OVR_IE            DCMI_IER_OVR_IE_Msk
+#define DCMI_IER_ERR_IE_Pos        (2U)
+#define DCMI_IER_ERR_IE_Msk        (0x1UL << DCMI_IER_ERR_IE_Pos)              /*!< 0x00000004 */
+#define DCMI_IER_ERR_IE            DCMI_IER_ERR_IE_Msk
+#define DCMI_IER_VSYNC_IE_Pos      (3U)
+#define DCMI_IER_VSYNC_IE_Msk      (0x1UL << DCMI_IER_VSYNC_IE_Pos)            /*!< 0x00000008 */
+#define DCMI_IER_VSYNC_IE          DCMI_IER_VSYNC_IE_Msk
+#define DCMI_IER_LINE_IE_Pos       (4U)
+#define DCMI_IER_LINE_IE_Msk       (0x1UL << DCMI_IER_LINE_IE_Pos)             /*!< 0x00000010 */
+#define DCMI_IER_LINE_IE           DCMI_IER_LINE_IE_Msk
+
+
+/********************  Bits definition for DCMI_MIS register  *****************/
+#define DCMI_MIS_FRAME_MIS_Pos     (0U)
+#define DCMI_MIS_FRAME_MIS_Msk     (0x1UL << DCMI_MIS_FRAME_MIS_Pos)           /*!< 0x00000001 */
+#define DCMI_MIS_FRAME_MIS         DCMI_MIS_FRAME_MIS_Msk
+#define DCMI_MIS_OVR_MIS_Pos       (1U)
+#define DCMI_MIS_OVR_MIS_Msk       (0x1UL << DCMI_MIS_OVR_MIS_Pos)             /*!< 0x00000002 */
+#define DCMI_MIS_OVR_MIS           DCMI_MIS_OVR_MIS_Msk
+#define DCMI_MIS_ERR_MIS_Pos       (2U)
+#define DCMI_MIS_ERR_MIS_Msk       (0x1UL << DCMI_MIS_ERR_MIS_Pos)             /*!< 0x00000004 */
+#define DCMI_MIS_ERR_MIS           DCMI_MIS_ERR_MIS_Msk
+#define DCMI_MIS_VSYNC_MIS_Pos     (3U)
+#define DCMI_MIS_VSYNC_MIS_Msk     (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)           /*!< 0x00000008 */
+#define DCMI_MIS_VSYNC_MIS         DCMI_MIS_VSYNC_MIS_Msk
+#define DCMI_MIS_LINE_MIS_Pos      (4U)
+#define DCMI_MIS_LINE_MIS_Msk      (0x1UL << DCMI_MIS_LINE_MIS_Pos)            /*!< 0x00000010 */
+#define DCMI_MIS_LINE_MIS          DCMI_MIS_LINE_MIS_Msk
+
+
+/********************  Bits definition for DCMI_ICR register  *****************/
+#define DCMI_ICR_FRAME_ISC_Pos     (0U)
+#define DCMI_ICR_FRAME_ISC_Msk     (0x1UL << DCMI_ICR_FRAME_ISC_Pos)           /*!< 0x00000001 */
+#define DCMI_ICR_FRAME_ISC         DCMI_ICR_FRAME_ISC_Msk
+#define DCMI_ICR_OVR_ISC_Pos       (1U)
+#define DCMI_ICR_OVR_ISC_Msk       (0x1UL << DCMI_ICR_OVR_ISC_Pos)             /*!< 0x00000002 */
+#define DCMI_ICR_OVR_ISC           DCMI_ICR_OVR_ISC_Msk
+#define DCMI_ICR_ERR_ISC_Pos       (2U)
+#define DCMI_ICR_ERR_ISC_Msk       (0x1UL << DCMI_ICR_ERR_ISC_Pos)             /*!< 0x00000004 */
+#define DCMI_ICR_ERR_ISC           DCMI_ICR_ERR_ISC_Msk
+#define DCMI_ICR_VSYNC_ISC_Pos     (3U)
+#define DCMI_ICR_VSYNC_ISC_Msk     (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)           /*!< 0x00000008 */
+#define DCMI_ICR_VSYNC_ISC         DCMI_ICR_VSYNC_ISC_Msk
+#define DCMI_ICR_LINE_ISC_Pos      (4U)
+#define DCMI_ICR_LINE_ISC_Msk      (0x1UL << DCMI_ICR_LINE_ISC_Pos)            /*!< 0x00000010 */
+#define DCMI_ICR_LINE_ISC          DCMI_ICR_LINE_ISC_Msk
+
+
+/********************  Bits definition for DCMI_ESCR register  ******************/
+#define DCMI_ESCR_FSC_Pos          (0U)
+#define DCMI_ESCR_FSC_Msk          (0xFFUL << DCMI_ESCR_FSC_Pos)               /*!< 0x000000FF */
+#define DCMI_ESCR_FSC              DCMI_ESCR_FSC_Msk
+#define DCMI_ESCR_LSC_Pos          (8U)
+#define DCMI_ESCR_LSC_Msk          (0xFFUL << DCMI_ESCR_LSC_Pos)               /*!< 0x0000FF00 */
+#define DCMI_ESCR_LSC              DCMI_ESCR_LSC_Msk
+#define DCMI_ESCR_LEC_Pos          (16U)
+#define DCMI_ESCR_LEC_Msk          (0xFFUL << DCMI_ESCR_LEC_Pos)               /*!< 0x00FF0000 */
+#define DCMI_ESCR_LEC              DCMI_ESCR_LEC_Msk
+#define DCMI_ESCR_FEC_Pos          (24U)
+#define DCMI_ESCR_FEC_Msk          (0xFFUL << DCMI_ESCR_FEC_Pos)               /*!< 0xFF000000 */
+#define DCMI_ESCR_FEC              DCMI_ESCR_FEC_Msk
+
+/********************  Bits definition for DCMI_ESUR register  ******************/
+#define DCMI_ESUR_FSU_Pos          (0U)
+#define DCMI_ESUR_FSU_Msk          (0xFFUL << DCMI_ESUR_FSU_Pos)               /*!< 0x000000FF */
+#define DCMI_ESUR_FSU              DCMI_ESUR_FSU_Msk
+#define DCMI_ESUR_LSU_Pos          (8U)
+#define DCMI_ESUR_LSU_Msk          (0xFFUL << DCMI_ESUR_LSU_Pos)               /*!< 0x0000FF00 */
+#define DCMI_ESUR_LSU              DCMI_ESUR_LSU_Msk
+#define DCMI_ESUR_LEU_Pos          (16U)
+#define DCMI_ESUR_LEU_Msk          (0xFFUL << DCMI_ESUR_LEU_Pos)               /*!< 0x00FF0000 */
+#define DCMI_ESUR_LEU              DCMI_ESUR_LEU_Msk
+#define DCMI_ESUR_FEU_Pos          (24U)
+#define DCMI_ESUR_FEU_Msk          (0xFFUL << DCMI_ESUR_FEU_Pos)               /*!< 0xFF000000 */
+#define DCMI_ESUR_FEU              DCMI_ESUR_FEU_Msk
+
+/********************  Bits definition for DCMI_CWSTRT register  ******************/
+#define DCMI_CWSTRT_HOFFCNT_Pos    (0U)
+#define DCMI_CWSTRT_HOFFCNT_Msk    (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)       /*!< 0x00003FFF */
+#define DCMI_CWSTRT_HOFFCNT        DCMI_CWSTRT_HOFFCNT_Msk
+#define DCMI_CWSTRT_VST_Pos        (16U)
+#define DCMI_CWSTRT_VST_Msk        (0x1FFFUL << DCMI_CWSTRT_VST_Pos)           /*!< 0x1FFF0000 */
+#define DCMI_CWSTRT_VST            DCMI_CWSTRT_VST_Msk
+
+/********************  Bits definition for DCMI_CWSIZE register  ******************/
+#define DCMI_CWSIZE_CAPCNT_Pos     (0U)
+#define DCMI_CWSIZE_CAPCNT_Msk     (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)        /*!< 0x00003FFF */
+#define DCMI_CWSIZE_CAPCNT         DCMI_CWSIZE_CAPCNT_Msk
+#define DCMI_CWSIZE_VLINE_Pos      (16U)
+#define DCMI_CWSIZE_VLINE_Msk      (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)         /*!< 0x3FFF0000 */
+#define DCMI_CWSIZE_VLINE          DCMI_CWSIZE_VLINE_Msk
+
+/********************  Bits definition for DCMI_DR register  ******************/
+#define DCMI_DR_BYTE0_Pos          (0U)
+#define DCMI_DR_BYTE0_Msk          (0xFFUL << DCMI_DR_BYTE0_Pos)               /*!< 0x000000FF */
+#define DCMI_DR_BYTE0              DCMI_DR_BYTE0_Msk
+#define DCMI_DR_BYTE1_Pos          (8U)
+#define DCMI_DR_BYTE1_Msk          (0xFFUL << DCMI_DR_BYTE1_Pos)               /*!< 0x0000FF00 */
+#define DCMI_DR_BYTE1              DCMI_DR_BYTE1_Msk
+#define DCMI_DR_BYTE2_Pos          (16U)
+#define DCMI_DR_BYTE2_Msk          (0xFFUL << DCMI_DR_BYTE2_Pos)               /*!< 0x00FF0000 */
+#define DCMI_DR_BYTE2              DCMI_DR_BYTE2_Msk
+#define DCMI_DR_BYTE3_Pos          (24U)
+#define DCMI_DR_BYTE3_Msk          (0xFFUL << DCMI_DR_BYTE3_Pos)               /*!< 0xFF000000 */
+#define DCMI_DR_BYTE3              DCMI_DR_BYTE3_Msk
+
+/******************************************************************************/
+/*                                                                            */
+/*                 Digital Filter for Sigma Delta Modulators                  */
+/*                                                                            */
+/******************************************************************************/
+
+/****************   DFSDM channel configuration registers  ********************/
+
+/***************  Bit definition for DFSDM_CHCFGR1 register  ******************/
+#define DFSDM_CHCFGR1_DFSDMEN_Pos       (31U)
+#define DFSDM_CHCFGR1_DFSDMEN_Msk       (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos)   /*!< 0x80000000 */
+#define DFSDM_CHCFGR1_DFSDMEN           DFSDM_CHCFGR1_DFSDMEN_Msk              /*!< Global enable for DFSDM interface */
+#define DFSDM_CHCFGR1_CKOUTSRC_Pos      (30U)
+#define DFSDM_CHCFGR1_CKOUTSRC_Msk      (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos)  /*!< 0x40000000 */
+#define DFSDM_CHCFGR1_CKOUTSRC          DFSDM_CHCFGR1_CKOUTSRC_Msk             /*!< Output serial clock source selection */
+#define DFSDM_CHCFGR1_CKOUTDIV_Pos      (16U)
+#define DFSDM_CHCFGR1_CKOUTDIV_Msk      (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */
+#define DFSDM_CHCFGR1_CKOUTDIV          DFSDM_CHCFGR1_CKOUTDIV_Msk             /*!< CKOUTDIV[7:0] output serial clock divider */
+#define DFSDM_CHCFGR1_DATPACK_Pos       (14U)
+#define DFSDM_CHCFGR1_DATPACK_Msk       (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos)   /*!< 0x0000C000 */
+#define DFSDM_CHCFGR1_DATPACK           DFSDM_CHCFGR1_DATPACK_Msk              /*!< DATPACK[1:0] Data packing mode */
+#define DFSDM_CHCFGR1_DATPACK_1         (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00008000 */
+#define DFSDM_CHCFGR1_DATPACK_0         (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00004000 */
+#define DFSDM_CHCFGR1_DATMPX_Pos        (12U)
+#define DFSDM_CHCFGR1_DATMPX_Msk        (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos)    /*!< 0x00003000 */
+#define DFSDM_CHCFGR1_DATMPX            DFSDM_CHCFGR1_DATMPX_Msk               /*!< DATMPX[1:0] Input data multiplexer for channel y */
+#define DFSDM_CHCFGR1_DATMPX_1          (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00002000 */
+#define DFSDM_CHCFGR1_DATMPX_0          (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00001000 */
+#define DFSDM_CHCFGR1_CHINSEL_Pos       (8U)
+#define DFSDM_CHCFGR1_CHINSEL_Msk       (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos)   /*!< 0x00000100 */
+#define DFSDM_CHCFGR1_CHINSEL           DFSDM_CHCFGR1_CHINSEL_Msk              /*!< Serial inputs selection for channel y */
+#define DFSDM_CHCFGR1_CHEN_Pos          (7U)
+#define DFSDM_CHCFGR1_CHEN_Msk          (0x1UL << DFSDM_CHCFGR1_CHEN_Pos)      /*!< 0x00000080 */
+#define DFSDM_CHCFGR1_CHEN              DFSDM_CHCFGR1_CHEN_Msk                 /*!< Channel y enable */
+#define DFSDM_CHCFGR1_CKABEN_Pos        (6U)
+#define DFSDM_CHCFGR1_CKABEN_Msk        (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos)    /*!< 0x00000040 */
+#define DFSDM_CHCFGR1_CKABEN            DFSDM_CHCFGR1_CKABEN_Msk               /*!< Clock absence detector enable on channel y */
+#define DFSDM_CHCFGR1_SCDEN_Pos         (5U)
+#define DFSDM_CHCFGR1_SCDEN_Msk         (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos)     /*!< 0x00000020 */
+#define DFSDM_CHCFGR1_SCDEN             DFSDM_CHCFGR1_SCDEN_Msk                /*!< Short circuit detector enable on channel y */
+#define DFSDM_CHCFGR1_SPICKSEL_Pos      (2U)
+#define DFSDM_CHCFGR1_SPICKSEL_Msk      (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos)  /*!< 0x0000000C */
+#define DFSDM_CHCFGR1_SPICKSEL          DFSDM_CHCFGR1_SPICKSEL_Msk             /*!< SPICKSEL[1:0] SPI clock select for channel y */
+#define DFSDM_CHCFGR1_SPICKSEL_1        (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000008 */
+#define DFSDM_CHCFGR1_SPICKSEL_0        (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000004 */
+#define DFSDM_CHCFGR1_SITP_Pos          (0U)
+#define DFSDM_CHCFGR1_SITP_Msk          (0x3UL << DFSDM_CHCFGR1_SITP_Pos)      /*!< 0x00000003 */
+#define DFSDM_CHCFGR1_SITP              DFSDM_CHCFGR1_SITP_Msk                 /*!< SITP[1:0] Serial interface type for channel y */
+#define DFSDM_CHCFGR1_SITP_1            (0x2UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000002 */
+#define DFSDM_CHCFGR1_SITP_0            (0x1UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000001 */
+
+/***************  Bit definition for DFSDM_CHCFGR2 register  ******************/
+#define DFSDM_CHCFGR2_OFFSET_Pos        (8U)
+#define DFSDM_CHCFGR2_OFFSET_Msk        (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_CHCFGR2_OFFSET            DFSDM_CHCFGR2_OFFSET_Msk               /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
+#define DFSDM_CHCFGR2_DTRBS_Pos         (3U)
+#define DFSDM_CHCFGR2_DTRBS_Msk         (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos)    /*!< 0x000000F8 */
+#define DFSDM_CHCFGR2_DTRBS             DFSDM_CHCFGR2_DTRBS_Msk                /*!< DTRBS[4:0] Data right bit-shift for channel y */
+
+/******************  Bit definition for DFSDM_CHAWSCDR register *****************/
+#define DFSDM_CHAWSCDR_AWFORD_Pos       (22U)
+#define DFSDM_CHAWSCDR_AWFORD_Msk       (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos)   /*!< 0x00C00000 */
+#define DFSDM_CHAWSCDR_AWFORD           DFSDM_CHAWSCDR_AWFORD_Msk              /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
+#define DFSDM_CHAWSCDR_AWFORD_1         (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00800000 */
+#define DFSDM_CHAWSCDR_AWFORD_0         (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00400000 */
+#define DFSDM_CHAWSCDR_AWFOSR_Pos       (16U)
+#define DFSDM_CHAWSCDR_AWFOSR_Msk       (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos)  /*!< 0x001F0000 */
+#define DFSDM_CHAWSCDR_AWFOSR           DFSDM_CHAWSCDR_AWFOSR_Msk              /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
+#define DFSDM_CHAWSCDR_BKSCD_Pos        (12U)
+#define DFSDM_CHAWSCDR_BKSCD_Msk        (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos)    /*!< 0x0000F000 */
+#define DFSDM_CHAWSCDR_BKSCD            DFSDM_CHAWSCDR_BKSCD_Msk               /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
+#define DFSDM_CHAWSCDR_SCDT_Pos         (0U)
+#define DFSDM_CHAWSCDR_SCDT_Msk         (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos)    /*!< 0x000000FF */
+#define DFSDM_CHAWSCDR_SCDT             DFSDM_CHAWSCDR_SCDT_Msk                /*!< SCDT[7:0] Short circuit detector threshold for channel y */
+
+/****************  Bit definition for DFSDM_CHWDATR register *******************/
+#define DFSDM_CHWDATR_WDATA_Pos         (0U)
+#define DFSDM_CHWDATR_WDATA_Msk         (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos)  /*!< 0x0000FFFF */
+#define DFSDM_CHWDATR_WDATA             DFSDM_CHWDATR_WDATA_Msk                /*!< WDATA[15:0] Input channel y watchdog data */
+
+/****************  Bit definition for DFSDM_CHDATINR register *****************/
+#define DFSDM_CHDATINR_INDAT0_Pos       (0U)
+#define DFSDM_CHDATINR_INDAT0_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */
+#define DFSDM_CHDATINR_INDAT0           DFSDM_CHDATINR_INDAT0_Msk              /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
+#define DFSDM_CHDATINR_INDAT1_Pos       (16U)
+#define DFSDM_CHDATINR_INDAT1_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */
+#define DFSDM_CHDATINR_INDAT1           DFSDM_CHDATINR_INDAT1_Msk              /*!< INDAT0[15:0] Input data for channel y */
+
+/************************   DFSDM module registers  ****************************/
+
+/********************  Bit definition for DFSDM_FLTCR1 register *******************/
+#define DFSDM_FLTCR1_AWFSEL_Pos         (30U)
+#define DFSDM_FLTCR1_AWFSEL_Msk         (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos)     /*!< 0x40000000 */
+#define DFSDM_FLTCR1_AWFSEL             DFSDM_FLTCR1_AWFSEL_Msk                /*!< Analog watchdog fast mode select */
+#define DFSDM_FLTCR1_FAST_Pos           (29U)
+#define DFSDM_FLTCR1_FAST_Msk           (0x1UL << DFSDM_FLTCR1_FAST_Pos)       /*!< 0x20000000 */
+#define DFSDM_FLTCR1_FAST               DFSDM_FLTCR1_FAST_Msk                  /*!< Fast conversion mode selection */
+#define DFSDM_FLTCR1_RCH_Pos            (24U)
+#define DFSDM_FLTCR1_RCH_Msk            (0x7UL << DFSDM_FLTCR1_RCH_Pos)        /*!< 0x07000000 */
+#define DFSDM_FLTCR1_RCH                DFSDM_FLTCR1_RCH_Msk                   /*!< RCH[2:0] Regular channel selection */
+#define DFSDM_FLTCR1_RDMAEN_Pos         (21U)
+#define DFSDM_FLTCR1_RDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos)     /*!< 0x00200000 */
+#define DFSDM_FLTCR1_RDMAEN             DFSDM_FLTCR1_RDMAEN_Msk                /*!< DMA channel enabled to read data for the regular conversion */
+#define DFSDM_FLTCR1_RSYNC_Pos          (19U)
+#define DFSDM_FLTCR1_RSYNC_Msk          (0x1UL << DFSDM_FLTCR1_RSYNC_Pos)      /*!< 0x00080000 */
+#define DFSDM_FLTCR1_RSYNC              DFSDM_FLTCR1_RSYNC_Msk                 /*!< Launch regular conversion synchronously with DFSDMx */
+#define DFSDM_FLTCR1_RCONT_Pos          (18U)
+#define DFSDM_FLTCR1_RCONT_Msk          (0x1UL << DFSDM_FLTCR1_RCONT_Pos)      /*!< 0x00040000 */
+#define DFSDM_FLTCR1_RCONT              DFSDM_FLTCR1_RCONT_Msk                 /*!< Continuous mode selection for regular conversions */
+#define DFSDM_FLTCR1_RSWSTART_Pos       (17U)
+#define DFSDM_FLTCR1_RSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos)   /*!< 0x00020000 */
+#define DFSDM_FLTCR1_RSWSTART           DFSDM_FLTCR1_RSWSTART_Msk              /*!< Software start of a conversion on the regular channel */
+#define DFSDM_FLTCR1_JEXTEN_Pos         (13U)
+#define DFSDM_FLTCR1_JEXTEN_Msk         (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos)     /*!< 0x00006000 */
+#define DFSDM_FLTCR1_JEXTEN             DFSDM_FLTCR1_JEXTEN_Msk                /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
+#define DFSDM_FLTCR1_JEXTEN_1           (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00004000 */
+#define DFSDM_FLTCR1_JEXTEN_0           (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00002000 */
+#define DFSDM_FLTCR1_JEXTSEL_Pos        (8U)
+#define DFSDM_FLTCR1_JEXTSEL_Msk        (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos)   /*!< 0x00001F00 */
+#define DFSDM_FLTCR1_JEXTSEL            DFSDM_FLTCR1_JEXTSEL_Msk               /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */
+#define DFSDM_FLTCR1_JEXTSEL_0          (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000100 */
+#define DFSDM_FLTCR1_JEXTSEL_1          (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000200 */
+#define DFSDM_FLTCR1_JEXTSEL_2          (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000400 */
+#define DFSDM_FLTCR1_JEXTSEL_3          (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000800 */
+#define DFSDM_FLTCR1_JEXTSEL_4          (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00001000 */
+
+#define DFSDM_FLTCR1_JDMAEN_Pos         (5U)
+#define DFSDM_FLTCR1_JDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos)     /*!< 0x00000020 */
+#define DFSDM_FLTCR1_JDMAEN             DFSDM_FLTCR1_JDMAEN_Msk                /*!< DMA channel enabled to read data for the injected channel group */
+#define DFSDM_FLTCR1_JSCAN_Pos          (4U)
+#define DFSDM_FLTCR1_JSCAN_Msk          (0x1UL << DFSDM_FLTCR1_JSCAN_Pos)      /*!< 0x00000010 */
+#define DFSDM_FLTCR1_JSCAN              DFSDM_FLTCR1_JSCAN_Msk                 /*!< Scanning conversion in continuous mode selection for injected conversions */
+#define DFSDM_FLTCR1_JSYNC_Pos          (3U)
+#define DFSDM_FLTCR1_JSYNC_Msk          (0x1UL << DFSDM_FLTCR1_JSYNC_Pos)      /*!< 0x00000008 */
+#define DFSDM_FLTCR1_JSYNC              DFSDM_FLTCR1_JSYNC_Msk                 /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */
+#define DFSDM_FLTCR1_JSWSTART_Pos       (1U)
+#define DFSDM_FLTCR1_JSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos)   /*!< 0x00000002 */
+#define DFSDM_FLTCR1_JSWSTART           DFSDM_FLTCR1_JSWSTART_Msk              /*!< Start the conversion of the injected group of channels */
+#define DFSDM_FLTCR1_DFEN_Pos           (0U)
+#define DFSDM_FLTCR1_DFEN_Msk           (0x1UL << DFSDM_FLTCR1_DFEN_Pos)       /*!< 0x00000001 */
+#define DFSDM_FLTCR1_DFEN               DFSDM_FLTCR1_DFEN_Msk                  /*!< DFSDM enable */
+
+/********************  Bit definition for DFSDM_FLTCR2 register *******************/
+#define DFSDM_FLTCR2_AWDCH_Pos          (16U)
+#define DFSDM_FLTCR2_AWDCH_Msk          (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos)     /*!< 0x00FF0000 */
+#define DFSDM_FLTCR2_AWDCH              DFSDM_FLTCR2_AWDCH_Msk                 /*!< AWDCH[7:0] Analog watchdog channel selection */
+#define DFSDM_FLTCR2_EXCH_Pos           (8U)
+#define DFSDM_FLTCR2_EXCH_Msk           (0xFFUL << DFSDM_FLTCR2_EXCH_Pos)      /*!< 0x0000FF00 */
+#define DFSDM_FLTCR2_EXCH               DFSDM_FLTCR2_EXCH_Msk                  /*!< EXCH[7:0] Extreme detector channel selection */
+#define DFSDM_FLTCR2_CKABIE_Pos         (6U)
+#define DFSDM_FLTCR2_CKABIE_Msk         (0x1UL << DFSDM_FLTCR2_CKABIE_Pos)     /*!< 0x00000040 */
+#define DFSDM_FLTCR2_CKABIE             DFSDM_FLTCR2_CKABIE_Msk                /*!< Clock absence interrupt enable */
+#define DFSDM_FLTCR2_SCDIE_Pos          (5U)
+#define DFSDM_FLTCR2_SCDIE_Msk          (0x1UL << DFSDM_FLTCR2_SCDIE_Pos)      /*!< 0x00000020 */
+#define DFSDM_FLTCR2_SCDIE              DFSDM_FLTCR2_SCDIE_Msk                 /*!< Short circuit detector interrupt enable */
+#define DFSDM_FLTCR2_AWDIE_Pos          (4U)
+#define DFSDM_FLTCR2_AWDIE_Msk          (0x1UL << DFSDM_FLTCR2_AWDIE_Pos)      /*!< 0x00000010 */
+#define DFSDM_FLTCR2_AWDIE              DFSDM_FLTCR2_AWDIE_Msk                 /*!< Analog watchdog interrupt enable */
+#define DFSDM_FLTCR2_ROVRIE_Pos         (3U)
+#define DFSDM_FLTCR2_ROVRIE_Msk         (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos)     /*!< 0x00000008 */
+#define DFSDM_FLTCR2_ROVRIE             DFSDM_FLTCR2_ROVRIE_Msk                /*!< Regular data overrun interrupt enable */
+#define DFSDM_FLTCR2_JOVRIE_Pos         (2U)
+#define DFSDM_FLTCR2_JOVRIE_Msk         (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos)     /*!< 0x00000004 */
+#define DFSDM_FLTCR2_JOVRIE             DFSDM_FLTCR2_JOVRIE_Msk                /*!< Injected data overrun interrupt enable */
+#define DFSDM_FLTCR2_REOCIE_Pos         (1U)
+#define DFSDM_FLTCR2_REOCIE_Msk         (0x1UL << DFSDM_FLTCR2_REOCIE_Pos)     /*!< 0x00000002 */
+#define DFSDM_FLTCR2_REOCIE             DFSDM_FLTCR2_REOCIE_Msk                /*!< Regular end of conversion interrupt enable */
+#define DFSDM_FLTCR2_JEOCIE_Pos         (0U)
+#define DFSDM_FLTCR2_JEOCIE_Msk         (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos)     /*!< 0x00000001 */
+#define DFSDM_FLTCR2_JEOCIE             DFSDM_FLTCR2_JEOCIE_Msk                /*!< Injected end of conversion interrupt enable */
+
+/********************  Bit definition for DFSDM_FLTISR register *******************/
+#define DFSDM_FLTISR_SCDF_Pos           (24U)
+#define DFSDM_FLTISR_SCDF_Msk           (0xFFUL << DFSDM_FLTISR_SCDF_Pos)      /*!< 0xFF000000 */
+#define DFSDM_FLTISR_SCDF               DFSDM_FLTISR_SCDF_Msk                  /*!< SCDF[7:0] Short circuit detector flag */
+#define DFSDM_FLTISR_CKABF_Pos          (16U)
+#define DFSDM_FLTISR_CKABF_Msk          (0xFFUL << DFSDM_FLTISR_CKABF_Pos)     /*!< 0x00FF0000 */
+#define DFSDM_FLTISR_CKABF              DFSDM_FLTISR_CKABF_Msk                 /*!< CKABF[7:0] Clock absence flag */
+#define DFSDM_FLTISR_RCIP_Pos           (14U)
+#define DFSDM_FLTISR_RCIP_Msk           (0x1UL << DFSDM_FLTISR_RCIP_Pos)       /*!< 0x00004000 */
+#define DFSDM_FLTISR_RCIP               DFSDM_FLTISR_RCIP_Msk                  /*!< Regular conversion in progress status */
+#define DFSDM_FLTISR_JCIP_Pos           (13U)
+#define DFSDM_FLTISR_JCIP_Msk           (0x1UL << DFSDM_FLTISR_JCIP_Pos)       /*!< 0x00002000 */
+#define DFSDM_FLTISR_JCIP               DFSDM_FLTISR_JCIP_Msk                  /*!< Injected conversion in progress status */
+#define DFSDM_FLTISR_AWDF_Pos           (4U)
+#define DFSDM_FLTISR_AWDF_Msk           (0x1UL << DFSDM_FLTISR_AWDF_Pos)       /*!< 0x00000010 */
+#define DFSDM_FLTISR_AWDF               DFSDM_FLTISR_AWDF_Msk                  /*!< Analog watchdog */
+#define DFSDM_FLTISR_ROVRF_Pos          (3U)
+#define DFSDM_FLTISR_ROVRF_Msk          (0x1UL << DFSDM_FLTISR_ROVRF_Pos)      /*!< 0x00000008 */
+#define DFSDM_FLTISR_ROVRF              DFSDM_FLTISR_ROVRF_Msk                 /*!< Regular conversion overrun flag */
+#define DFSDM_FLTISR_JOVRF_Pos          (2U)
+#define DFSDM_FLTISR_JOVRF_Msk          (0x1UL << DFSDM_FLTISR_JOVRF_Pos)      /*!< 0x00000004 */
+#define DFSDM_FLTISR_JOVRF              DFSDM_FLTISR_JOVRF_Msk                 /*!< Injected conversion overrun flag */
+#define DFSDM_FLTISR_REOCF_Pos          (1U)
+#define DFSDM_FLTISR_REOCF_Msk          (0x1UL << DFSDM_FLTISR_REOCF_Pos)      /*!< 0x00000002 */
+#define DFSDM_FLTISR_REOCF              DFSDM_FLTISR_REOCF_Msk                 /*!< End of regular conversion flag */
+#define DFSDM_FLTISR_JEOCF_Pos          (0U)
+#define DFSDM_FLTISR_JEOCF_Msk          (0x1UL << DFSDM_FLTISR_JEOCF_Pos)      /*!< 0x00000001 */
+#define DFSDM_FLTISR_JEOCF              DFSDM_FLTISR_JEOCF_Msk                 /*!< End of injected conversion flag */
+
+/********************  Bit definition for DFSDM_FLTICR register *******************/
+#define DFSDM_FLTICR_CLRSCDF_Pos        (24U)
+#define DFSDM_FLTICR_CLRSCDF_Msk        (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos)   /*!< 0xFF000000 */
+#define DFSDM_FLTICR_CLRSCDF            DFSDM_FLTICR_CLRSCDF_Msk               /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
+#define DFSDM_FLTICR_CLRCKABF_Pos       (16U)
+#define DFSDM_FLTICR_CLRCKABF_Msk       (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos)  /*!< 0x00FF0000 */
+#define DFSDM_FLTICR_CLRCKABF           DFSDM_FLTICR_CLRCKABF_Msk              /*!< CLRCKABF[7:0] Clear the clock absence flag */
+#define DFSDM_FLTICR_CLRROVRF_Pos       (3U)
+#define DFSDM_FLTICR_CLRROVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos)   /*!< 0x00000008 */
+#define DFSDM_FLTICR_CLRROVRF           DFSDM_FLTICR_CLRROVRF_Msk              /*!< Clear the regular conversion overrun flag */
+#define DFSDM_FLTICR_CLRJOVRF_Pos       (2U)
+#define DFSDM_FLTICR_CLRJOVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos)   /*!< 0x00000004 */
+#define DFSDM_FLTICR_CLRJOVRF           DFSDM_FLTICR_CLRJOVRF_Msk              /*!< Clear the injected conversion overrun flag */
+
+/*******************  Bit definition for DFSDM_FLTJCHGR register ******************/
+#define DFSDM_FLTJCHGR_JCHG_Pos         (0U)
+#define DFSDM_FLTJCHGR_JCHG_Msk         (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos)    /*!< 0x000000FF */
+#define DFSDM_FLTJCHGR_JCHG             DFSDM_FLTJCHGR_JCHG_Msk                /*!< JCHG[7:0] Injected channel group selection */
+
+/********************  Bit definition for DFSDM_FLTFCR register *******************/
+#define DFSDM_FLTFCR_FORD_Pos           (29U)
+#define DFSDM_FLTFCR_FORD_Msk           (0x7UL << DFSDM_FLTFCR_FORD_Pos)       /*!< 0xE0000000 */
+#define DFSDM_FLTFCR_FORD               DFSDM_FLTFCR_FORD_Msk                  /*!< FORD[2:0] Sinc filter order */
+#define DFSDM_FLTFCR_FORD_2             (0x4UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x80000000 */
+#define DFSDM_FLTFCR_FORD_1             (0x2UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x40000000 */
+#define DFSDM_FLTFCR_FORD_0             (0x1UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x20000000 */
+#define DFSDM_FLTFCR_FOSR_Pos           (16U)
+#define DFSDM_FLTFCR_FOSR_Msk           (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos)     /*!< 0x03FF0000 */
+#define DFSDM_FLTFCR_FOSR               DFSDM_FLTFCR_FOSR_Msk                  /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
+#define DFSDM_FLTFCR_IOSR_Pos           (0U)
+#define DFSDM_FLTFCR_IOSR_Msk           (0xFFUL << DFSDM_FLTFCR_IOSR_Pos)      /*!< 0x000000FF */
+#define DFSDM_FLTFCR_IOSR               DFSDM_FLTFCR_IOSR_Msk                  /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
+
+/******************  Bit definition for DFSDM_FLTJDATAR register *****************/
+#define DFSDM_FLTJDATAR_JDATA_Pos       (8U)
+#define DFSDM_FLTJDATAR_JDATA_Msk       (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTJDATAR_JDATA           DFSDM_FLTJDATAR_JDATA_Msk              /*!< JDATA[23:0] Injected group conversion data */
+#define DFSDM_FLTJDATAR_JDATACH_Pos     (0U)
+#define DFSDM_FLTJDATAR_JDATACH_Msk     (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */
+#define DFSDM_FLTJDATAR_JDATACH         DFSDM_FLTJDATAR_JDATACH_Msk            /*!< JDATACH[2:0] Injected channel most recently converted */
+
+/******************  Bit definition for DFSDM_FLTRDATAR register *****************/
+#define DFSDM_FLTRDATAR_RDATA_Pos       (8U)
+#define DFSDM_FLTRDATAR_RDATA_Msk       (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTRDATAR_RDATA           DFSDM_FLTRDATAR_RDATA_Msk              /*!< RDATA[23:0] Regular channel conversion data */
+#define DFSDM_FLTRDATAR_RPEND_Pos       (4U)
+#define DFSDM_FLTRDATAR_RPEND_Msk       (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos)   /*!< 0x00000010 */
+#define DFSDM_FLTRDATAR_RPEND           DFSDM_FLTRDATAR_RPEND_Msk              /*!< RPEND Regular channel pending data */
+#define DFSDM_FLTRDATAR_RDATACH_Pos     (0U)
+#define DFSDM_FLTRDATAR_RDATACH_Msk     (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */
+#define DFSDM_FLTRDATAR_RDATACH         DFSDM_FLTRDATAR_RDATACH_Msk            /*!< RDATACH[2:0] Regular channel most recently converted */
+
+/******************  Bit definition for DFSDM_FLTAWHTR register ******************/
+#define DFSDM_FLTAWHTR_AWHT_Pos         (8U)
+#define DFSDM_FLTAWHTR_AWHT_Msk         (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTAWHTR_AWHT             DFSDM_FLTAWHTR_AWHT_Msk                /*!< AWHT[23:0] Analog watchdog high threshold */
+#define DFSDM_FLTAWHTR_BKAWH_Pos        (0U)
+#define DFSDM_FLTAWHTR_BKAWH_Msk        (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)    /*!< 0x0000000F */
+#define DFSDM_FLTAWHTR_BKAWH            DFSDM_FLTAWHTR_BKAWH_Msk               /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
+
+/******************  Bit definition for DFSDM_FLTAWLTR register ******************/
+#define DFSDM_FLTAWLTR_AWLT_Pos         (8U)
+#define DFSDM_FLTAWLTR_AWLT_Msk         (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTAWLTR_AWLT             DFSDM_FLTAWLTR_AWLT_Msk                /*!< AWHT[23:0] Analog watchdog low threshold */
+#define DFSDM_FLTAWLTR_BKAWL_Pos        (0U)
+#define DFSDM_FLTAWLTR_BKAWL_Msk        (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos)    /*!< 0x0000000F */
+#define DFSDM_FLTAWLTR_BKAWL            DFSDM_FLTAWLTR_BKAWL_Msk               /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
+
+/******************  Bit definition for DFSDM_FLTAWSR register ******************/
+#define DFSDM_FLTAWSR_AWHTF_Pos         (8U)
+#define DFSDM_FLTAWSR_AWHTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos)    /*!< 0x0000FF00 */
+#define DFSDM_FLTAWSR_AWHTF             DFSDM_FLTAWSR_AWHTF_Msk                /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
+#define DFSDM_FLTAWSR_AWLTF_Pos         (0U)
+#define DFSDM_FLTAWSR_AWLTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos)    /*!< 0x000000FF */
+#define DFSDM_FLTAWSR_AWLTF             DFSDM_FLTAWSR_AWLTF_Msk                /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
+
+/******************  Bit definition for DFSDM_FLTAWCFR) register *****************/
+#define DFSDM_FLTAWCFR_CLRAWHTF_Pos     (8U)
+#define DFSDM_FLTAWCFR_CLRAWHTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */
+#define DFSDM_FLTAWCFR_CLRAWHTF         DFSDM_FLTAWCFR_CLRAWHTF_Msk            /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
+#define DFSDM_FLTAWCFR_CLRAWLTF_Pos     (0U)
+#define DFSDM_FLTAWCFR_CLRAWLTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */
+#define DFSDM_FLTAWCFR_CLRAWLTF         DFSDM_FLTAWCFR_CLRAWLTF_Msk            /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
+
+/******************  Bit definition for DFSDM_FLTEXMAX register ******************/
+#define DFSDM_FLTEXMAX_EXMAX_Pos        (8U)
+#define DFSDM_FLTEXMAX_EXMAX_Msk        (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTEXMAX_EXMAX            DFSDM_FLTEXMAX_EXMAX_Msk               /*!< EXMAX[23:0] Extreme detector maximum value */
+#define DFSDM_FLTEXMAX_EXMAXCH_Pos      (0U)
+#define DFSDM_FLTEXMAX_EXMAXCH_Msk      (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos)  /*!< 0x00000007 */
+#define DFSDM_FLTEXMAX_EXMAXCH          DFSDM_FLTEXMAX_EXMAXCH_Msk             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
+
+/******************  Bit definition for DFSDM_FLTEXMIN register ******************/
+#define DFSDM_FLTEXMIN_EXMIN_Pos        (8U)
+#define DFSDM_FLTEXMIN_EXMIN_Msk        (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTEXMIN_EXMIN            DFSDM_FLTEXMIN_EXMIN_Msk               /*!< EXMIN[23:0] Extreme detector minimum value */
+#define DFSDM_FLTEXMIN_EXMINCH_Pos      (0U)
+#define DFSDM_FLTEXMIN_EXMINCH_Msk      (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos)  /*!< 0x00000007 */
+#define DFSDM_FLTEXMIN_EXMINCH          DFSDM_FLTEXMIN_EXMINCH_Msk             /*!< EXMINCH[2:0] Extreme detector minimum data channel */
+
+/******************  Bit definition for DFSDM_FLTCNVTIMR register ******************/
+#define DFSDM_FLTCNVTIMR_CNVCNT_Pos     (4U)
+#define DFSDM_FLTCNVTIMR_CNVCNT_Msk     (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */
+#define DFSDM_FLTCNVTIMR_CNVCNT         DFSDM_FLTCNVTIMR_CNVCNT_Msk            /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           BDMA Controller                                  */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for BDMA_ISR register  ********************/
+#define BDMA_ISR_GIF0_Pos       (0U)
+#define BDMA_ISR_GIF0_Msk       (0x1UL << BDMA_ISR_GIF0_Pos)                   /*!< 0x00000001 */
+#define BDMA_ISR_GIF0           BDMA_ISR_GIF0_Msk                              /*!< Channel 0 Global interrupt flag */
+#define BDMA_ISR_TCIF0_Pos      (1U)
+#define BDMA_ISR_TCIF0_Msk      (0x1UL << BDMA_ISR_TCIF0_Pos)                  /*!< 0x00000002 */
+#define BDMA_ISR_TCIF0          BDMA_ISR_TCIF0_Msk                             /*!< Channel 0 Transfer Complete flag */
+#define BDMA_ISR_HTIF0_Pos      (2U)
+#define BDMA_ISR_HTIF0_Msk      (0x1UL << BDMA_ISR_HTIF0_Pos)                  /*!< 0x00000004 */
+#define BDMA_ISR_HTIF0          BDMA_ISR_HTIF0_Msk                             /*!< Channel 0 Half Transfer flag */
+#define BDMA_ISR_TEIF0_Pos      (3U)
+#define BDMA_ISR_TEIF0_Msk      (0x1UL << BDMA_ISR_TEIF0_Pos)                  /*!< 0x00000008 */
+#define BDMA_ISR_TEIF0          BDMA_ISR_TEIF0_Msk                             /*!< Channel 0 Transfer Error flag */
+#define BDMA_ISR_GIF1_Pos       (4U)
+#define BDMA_ISR_GIF1_Msk       (0x1UL << BDMA_ISR_GIF1_Pos)                   /*!< 0x00000010 */
+#define BDMA_ISR_GIF1           BDMA_ISR_GIF1_Msk                              /*!< Channel 1 Global interrupt flag */
+#define BDMA_ISR_TCIF1_Pos      (5U)
+#define BDMA_ISR_TCIF1_Msk      (0x1UL << BDMA_ISR_TCIF1_Pos)                  /*!< 0x00000020 */
+#define BDMA_ISR_TCIF1          BDMA_ISR_TCIF1_Msk                             /*!< Channel 1 Transfer Complete flag */
+#define BDMA_ISR_HTIF1_Pos      (6U)
+#define BDMA_ISR_HTIF1_Msk      (0x1UL << BDMA_ISR_HTIF1_Pos)                  /*!< 0x00000040 */
+#define BDMA_ISR_HTIF1          BDMA_ISR_HTIF1_Msk                             /*!< Channel 1 Half Transfer flag */
+#define BDMA_ISR_TEIF1_Pos      (7U)
+#define BDMA_ISR_TEIF1_Msk      (0x1UL << BDMA_ISR_TEIF1_Pos)                  /*!< 0x00000080 */
+#define BDMA_ISR_TEIF1          BDMA_ISR_TEIF1_Msk                             /*!< Channel 1 Transfer Error flag */
+#define BDMA_ISR_GIF2_Pos       (8U)
+#define BDMA_ISR_GIF2_Msk       (0x1UL << BDMA_ISR_GIF2_Pos)                   /*!< 0x00000100 */
+#define BDMA_ISR_GIF2           BDMA_ISR_GIF2_Msk                              /*!< Channel 2 Global interrupt flag */
+#define BDMA_ISR_TCIF2_Pos      (9U)
+#define BDMA_ISR_TCIF2_Msk      (0x1UL << BDMA_ISR_TCIF2_Pos)                  /*!< 0x00000200 */
+#define BDMA_ISR_TCIF2          BDMA_ISR_TCIF2_Msk                             /*!< Channel 2 Transfer Complete flag */
+#define BDMA_ISR_HTIF2_Pos      (10U)
+#define BDMA_ISR_HTIF2_Msk      (0x1UL << BDMA_ISR_HTIF2_Pos)                  /*!< 0x00000400 */
+#define BDMA_ISR_HTIF2          BDMA_ISR_HTIF2_Msk                             /*!< Channel 2 Half Transfer flag */
+#define BDMA_ISR_TEIF2_Pos      (11U)
+#define BDMA_ISR_TEIF2_Msk      (0x1UL << BDMA_ISR_TEIF2_Pos)                  /*!< 0x00000800 */
+#define BDMA_ISR_TEIF2          BDMA_ISR_TEIF2_Msk                             /*!< Channel 2 Transfer Error flag */
+#define BDMA_ISR_GIF3_Pos       (12U)
+#define BDMA_ISR_GIF3_Msk       (0x1UL << BDMA_ISR_GIF3_Pos)                   /*!< 0x00001000 */
+#define BDMA_ISR_GIF3           BDMA_ISR_GIF3_Msk                              /*!< Channel 3 Global interrupt flag */
+#define BDMA_ISR_TCIF3_Pos      (13U)
+#define BDMA_ISR_TCIF3_Msk      (0x1UL << BDMA_ISR_TCIF3_Pos)                  /*!< 0x00002000 */
+#define BDMA_ISR_TCIF3          BDMA_ISR_TCIF3_Msk                             /*!< Channel 3 Transfer Complete flag */
+#define BDMA_ISR_HTIF3_Pos      (14U)
+#define BDMA_ISR_HTIF3_Msk      (0x1UL << BDMA_ISR_HTIF3_Pos)                  /*!< 0x00004000 */
+#define BDMA_ISR_HTIF3          BDMA_ISR_HTIF3_Msk                             /*!< Channel 3 Half Transfer flag */
+#define BDMA_ISR_TEIF3_Pos      (15U)
+#define BDMA_ISR_TEIF3_Msk      (0x1UL << BDMA_ISR_TEIF3_Pos)                  /*!< 0x00008000 */
+#define BDMA_ISR_TEIF3          BDMA_ISR_TEIF3_Msk                             /*!< Channel 3 Transfer Error flag */
+#define BDMA_ISR_GIF4_Pos       (16U)
+#define BDMA_ISR_GIF4_Msk       (0x1UL << BDMA_ISR_GIF4_Pos)                   /*!< 0x00010000 */
+#define BDMA_ISR_GIF4           BDMA_ISR_GIF4_Msk                              /*!< Channel 4 Global interrupt flag */
+#define BDMA_ISR_TCIF4_Pos      (17U)
+#define BDMA_ISR_TCIF4_Msk      (0x1UL << BDMA_ISR_TCIF4_Pos)                  /*!< 0x00020000 */
+#define BDMA_ISR_TCIF4          BDMA_ISR_TCIF4_Msk                             /*!< Channel 4 Transfer Complete flag */
+#define BDMA_ISR_HTIF4_Pos      (18U)
+#define BDMA_ISR_HTIF4_Msk      (0x1UL << BDMA_ISR_HTIF4_Pos)                  /*!< 0x00040000 */
+#define BDMA_ISR_HTIF4          BDMA_ISR_HTIF4_Msk                             /*!< Channel 4 Half Transfer flag */
+#define BDMA_ISR_TEIF4_Pos      (19U)
+#define BDMA_ISR_TEIF4_Msk      (0x1UL << BDMA_ISR_TEIF4_Pos)                  /*!< 0x00080000 */
+#define BDMA_ISR_TEIF4          BDMA_ISR_TEIF4_Msk                             /*!< Channel 4 Transfer Error flag */
+#define BDMA_ISR_GIF5_Pos       (20U)
+#define BDMA_ISR_GIF5_Msk       (0x1UL << BDMA_ISR_GIF5_Pos)                   /*!< 0x00100000 */
+#define BDMA_ISR_GIF5           BDMA_ISR_GIF5_Msk                              /*!< Channel 5 Global interrupt flag */
+#define BDMA_ISR_TCIF5_Pos      (21U)
+#define BDMA_ISR_TCIF5_Msk      (0x1UL << BDMA_ISR_TCIF5_Pos)                  /*!< 0x00200000 */
+#define BDMA_ISR_TCIF5          BDMA_ISR_TCIF5_Msk                             /*!< Channel 5 Transfer Complete flag */
+#define BDMA_ISR_HTIF5_Pos      (22U)
+#define BDMA_ISR_HTIF5_Msk      (0x1UL << BDMA_ISR_HTIF5_Pos)                  /*!< 0x00400000 */
+#define BDMA_ISR_HTIF5          BDMA_ISR_HTIF5_Msk                             /*!< Channel 5 Half Transfer flag */
+#define BDMA_ISR_TEIF5_Pos      (23U)
+#define BDMA_ISR_TEIF5_Msk      (0x1UL << BDMA_ISR_TEIF5_Pos)                  /*!< 0x00800000 */
+#define BDMA_ISR_TEIF5          BDMA_ISR_TEIF5_Msk                             /*!< Channel 5 Transfer Error flag */
+#define BDMA_ISR_GIF6_Pos       (24U)
+#define BDMA_ISR_GIF6_Msk       (0x1UL << BDMA_ISR_GIF6_Pos)                   /*!< 0x01000000 */
+#define BDMA_ISR_GIF6           BDMA_ISR_GIF6_Msk                              /*!< Channel 6 Global interrupt flag */
+#define BDMA_ISR_TCIF6_Pos      (25U)
+#define BDMA_ISR_TCIF6_Msk      (0x1UL << BDMA_ISR_TCIF6_Pos)                  /*!< 0x02000000 */
+#define BDMA_ISR_TCIF6          BDMA_ISR_TCIF6_Msk                             /*!< Channel 6 Transfer Complete flag */
+#define BDMA_ISR_HTIF6_Pos      (26U)
+#define BDMA_ISR_HTIF6_Msk      (0x1UL << BDMA_ISR_HTIF6_Pos)                  /*!< 0x04000000 */
+#define BDMA_ISR_HTIF6          BDMA_ISR_HTIF6_Msk                             /*!< Channel 6 Half Transfer flag */
+#define BDMA_ISR_TEIF6_Pos      (27U)
+#define BDMA_ISR_TEIF6_Msk      (0x1UL << BDMA_ISR_TEIF6_Pos)                  /*!< 0x08000000 */
+#define BDMA_ISR_TEIF6          BDMA_ISR_TEIF6_Msk                             /*!< Channel 6 Transfer Error flag */
+#define BDMA_ISR_GIF7_Pos       (28U)
+#define BDMA_ISR_GIF7_Msk       (0x1UL << BDMA_ISR_GIF7_Pos)                   /*!< 0x10000000 */
+#define BDMA_ISR_GIF7           BDMA_ISR_GIF7_Msk                              /*!< Channel 7 Global interrupt flag */
+#define BDMA_ISR_TCIF7_Pos      (29U)
+#define BDMA_ISR_TCIF7_Msk      (0x1UL << BDMA_ISR_TCIF7_Pos)                  /*!< 0x20000000 */
+#define BDMA_ISR_TCIF7          BDMA_ISR_TCIF7_Msk                             /*!< Channel 7 Transfer Complete flag */
+#define BDMA_ISR_HTIF7_Pos      (30U)
+#define BDMA_ISR_HTIF7_Msk      (0x1UL << BDMA_ISR_HTIF7_Pos)                  /*!< 0x40000000 */
+#define BDMA_ISR_HTIF7          BDMA_ISR_HTIF7_Msk                             /*!< Channel 7 Half Transfer flag */
+#define BDMA_ISR_TEIF7_Pos      (31U)
+#define BDMA_ISR_TEIF7_Msk      (0x1UL << BDMA_ISR_TEIF7_Pos)                  /*!< 0x80000000 */
+#define BDMA_ISR_TEIF7          BDMA_ISR_TEIF7_Msk                             /*!< Channel 7 Transfer Error flag */
+
+/*******************  Bit definition for BDMA_IFCR register  *******************/
+#define BDMA_IFCR_CGIF0_Pos     (0U)
+#define BDMA_IFCR_CGIF0_Msk     (0x1UL << BDMA_IFCR_CGIF0_Pos)                 /*!< 0x00000001 */
+#define BDMA_IFCR_CGIF0         BDMA_IFCR_CGIF0_Msk                            /*!< Channel 0 Global interrupt clearr */
+#define BDMA_IFCR_CTCIF0_Pos    (1U)
+#define BDMA_IFCR_CTCIF0_Msk    (0x1UL << BDMA_IFCR_CTCIF0_Pos)                /*!< 0x00000002 */
+#define BDMA_IFCR_CTCIF0        BDMA_IFCR_CTCIF0_Msk                           /*!< Channel 0 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF0_Pos    (2U)
+#define BDMA_IFCR_CHTIF0_Msk    (0x1UL << BDMA_IFCR_CHTIF0_Pos)                /*!< 0x00000004 */
+#define BDMA_IFCR_CHTIF0        BDMA_IFCR_CHTIF0_Msk                           /*!< Channel 0 Half Transfer clear */
+#define BDMA_IFCR_CTEIF0_Pos    (3U)
+#define BDMA_IFCR_CTEIF0_Msk    (0x1UL << BDMA_IFCR_CTEIF0_Pos)                /*!< 0x00000008 */
+#define BDMA_IFCR_CTEIF0        BDMA_IFCR_CTEIF0_Msk                           /*!< Channel 0 Transfer Error clear */
+#define BDMA_IFCR_CGIF1_Pos     (4U)
+#define BDMA_IFCR_CGIF1_Msk     (0x1UL << BDMA_IFCR_CGIF1_Pos)                 /*!< 0x00000010 */
+#define BDMA_IFCR_CGIF1         BDMA_IFCR_CGIF1_Msk                            /*!< Channel 1 Global interrupt clear */
+#define BDMA_IFCR_CTCIF1_Pos    (5U)
+#define BDMA_IFCR_CTCIF1_Msk    (0x1UL << BDMA_IFCR_CTCIF1_Pos)                /*!< 0x00000020 */
+#define BDMA_IFCR_CTCIF1        BDMA_IFCR_CTCIF1_Msk                           /*!< Channel 1 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF1_Pos    (6U)
+#define BDMA_IFCR_CHTIF1_Msk    (0x1UL << BDMA_IFCR_CHTIF1_Pos)                /*!< 0x00000040 */
+#define BDMA_IFCR_CHTIF1        BDMA_IFCR_CHTIF1_Msk                           /*!< Channel 1 Half Transfer clear */
+#define BDMA_IFCR_CTEIF1_Pos    (7U)
+#define BDMA_IFCR_CTEIF1_Msk    (0x1UL << BDMA_IFCR_CTEIF1_Pos)                /*!< 0x00000080 */
+#define BDMA_IFCR_CTEIF1        BDMA_IFCR_CTEIF1_Msk                           /*!< Channel 1 Transfer Error clear */
+#define BDMA_IFCR_CGIF2_Pos     (8U)
+#define BDMA_IFCR_CGIF2_Msk     (0x1UL << BDMA_IFCR_CGIF2_Pos)                 /*!< 0x00000100 */
+#define BDMA_IFCR_CGIF2         BDMA_IFCR_CGIF2_Msk                            /*!< Channel 2 Global interrupt clear */
+#define BDMA_IFCR_CTCIF2_Pos    (9U)
+#define BDMA_IFCR_CTCIF2_Msk    (0x1UL << BDMA_IFCR_CTCIF2_Pos)                /*!< 0x00000200 */
+#define BDMA_IFCR_CTCIF2        BDMA_IFCR_CTCIF2_Msk                           /*!< Channel 2 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF2_Pos    (10U)
+#define BDMA_IFCR_CHTIF2_Msk    (0x1UL << BDMA_IFCR_CHTIF2_Pos)                /*!< 0x00000400 */
+#define BDMA_IFCR_CHTIF2        BDMA_IFCR_CHTIF2_Msk                           /*!< Channel 2 Half Transfer clear */
+#define BDMA_IFCR_CTEIF2_Pos    (11U)
+#define BDMA_IFCR_CTEIF2_Msk    (0x1UL << BDMA_IFCR_CTEIF2_Pos)                /*!< 0x00000800 */
+#define BDMA_IFCR_CTEIF2        BDMA_IFCR_CTEIF2_Msk                           /*!< Channel 2 Transfer Error clear */
+#define BDMA_IFCR_CGIF3_Pos     (12U)
+#define BDMA_IFCR_CGIF3_Msk     (0x1UL << BDMA_IFCR_CGIF3_Pos)                 /*!< 0x00001000 */
+#define BDMA_IFCR_CGIF3         BDMA_IFCR_CGIF3_Msk                            /*!< Channel 3 Global interrupt clear */
+#define BDMA_IFCR_CTCIF3_Pos    (13U)
+#define BDMA_IFCR_CTCIF3_Msk    (0x1UL << BDMA_IFCR_CTCIF3_Pos)                /*!< 0x00002000 */
+#define BDMA_IFCR_CTCIF3        BDMA_IFCR_CTCIF3_Msk                           /*!< Channel 3 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF3_Pos    (14U)
+#define BDMA_IFCR_CHTIF3_Msk    (0x1UL << BDMA_IFCR_CHTIF3_Pos)                /*!< 0x00004000 */
+#define BDMA_IFCR_CHTIF3        BDMA_IFCR_CHTIF3_Msk                           /*!< Channel 3 Half Transfer clear */
+#define BDMA_IFCR_CTEIF3_Pos    (15U)
+#define BDMA_IFCR_CTEIF3_Msk    (0x1UL << BDMA_IFCR_CTEIF3_Pos)                /*!< 0x00008000 */
+#define BDMA_IFCR_CTEIF3        BDMA_IFCR_CTEIF3_Msk                           /*!< Channel 3 Transfer Error clear */
+#define BDMA_IFCR_CGIF4_Pos     (16U)
+#define BDMA_IFCR_CGIF4_Msk     (0x1UL << BDMA_IFCR_CGIF4_Pos)                 /*!< 0x00010000 */
+#define BDMA_IFCR_CGIF4         BDMA_IFCR_CGIF4_Msk                            /*!< Channel 4 Global interrupt clear */
+#define BDMA_IFCR_CTCIF4_Pos    (17U)
+#define BDMA_IFCR_CTCIF4_Msk    (0x1UL << BDMA_IFCR_CTCIF4_Pos)                /*!< 0x00020000 */
+#define BDMA_IFCR_CTCIF4        BDMA_IFCR_CTCIF4_Msk                           /*!< Channel 4 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF4_Pos    (18U)
+#define BDMA_IFCR_CHTIF4_Msk    (0x1UL << BDMA_IFCR_CHTIF4_Pos)                /*!< 0x00040000 */
+#define BDMA_IFCR_CHTIF4        BDMA_IFCR_CHTIF4_Msk                           /*!< Channel 4 Half Transfer clear */
+#define BDMA_IFCR_CTEIF4_Pos    (19U)
+#define BDMA_IFCR_CTEIF4_Msk    (0x1UL << BDMA_IFCR_CTEIF4_Pos)                /*!< 0x00080000 */
+#define BDMA_IFCR_CTEIF4        BDMA_IFCR_CTEIF4_Msk                           /*!< Channel 4 Transfer Error clear */
+#define BDMA_IFCR_CGIF5_Pos     (20U)
+#define BDMA_IFCR_CGIF5_Msk     (0x1UL << BDMA_IFCR_CGIF5_Pos)                 /*!< 0x00100000 */
+#define BDMA_IFCR_CGIF5         BDMA_IFCR_CGIF5_Msk                            /*!< Channel 5 Global interrupt clear */
+#define BDMA_IFCR_CTCIF5_Pos    (21U)
+#define BDMA_IFCR_CTCIF5_Msk    (0x1UL << BDMA_IFCR_CTCIF5_Pos)                /*!< 0x00200000 */
+#define BDMA_IFCR_CTCIF5        BDMA_IFCR_CTCIF5_Msk                           /*!< Channel 5 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF5_Pos    (22U)
+#define BDMA_IFCR_CHTIF5_Msk    (0x1UL << BDMA_IFCR_CHTIF5_Pos)                /*!< 0x00400000 */
+#define BDMA_IFCR_CHTIF5        BDMA_IFCR_CHTIF5_Msk                           /*!< Channel 5 Half Transfer clear */
+#define BDMA_IFCR_CTEIF5_Pos    (23U)
+#define BDMA_IFCR_CTEIF5_Msk    (0x1UL << BDMA_IFCR_CTEIF5_Pos)                /*!< 0x00800000 */
+#define BDMA_IFCR_CTEIF5        BDMA_IFCR_CTEIF5_Msk                           /*!< Channel 5 Transfer Error clear */
+#define BDMA_IFCR_CGIF6_Pos     (24U)
+#define BDMA_IFCR_CGIF6_Msk     (0x1UL << BDMA_IFCR_CGIF6_Pos)                 /*!< 0x01000000 */
+#define BDMA_IFCR_CGIF6         BDMA_IFCR_CGIF6_Msk                            /*!< Channel 6 Global interrupt clear */
+#define BDMA_IFCR_CTCIF6_Pos    (25U)
+#define BDMA_IFCR_CTCIF6_Msk    (0x1UL << BDMA_IFCR_CTCIF6_Pos)                /*!< 0x02000000 */
+#define BDMA_IFCR_CTCIF6        BDMA_IFCR_CTCIF6_Msk                           /*!< Channel 6 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF6_Pos    (26U)
+#define BDMA_IFCR_CHTIF6_Msk    (0x1UL << BDMA_IFCR_CHTIF6_Pos)                /*!< 0x04000000 */
+#define BDMA_IFCR_CHTIF6        BDMA_IFCR_CHTIF6_Msk                           /*!< Channel 6 Half Transfer clear */
+#define BDMA_IFCR_CTEIF6_Pos    (27U)
+#define BDMA_IFCR_CTEIF6_Msk    (0x1UL << BDMA_IFCR_CTEIF6_Pos)                /*!< 0x08000000 */
+#define BDMA_IFCR_CTEIF6        BDMA_IFCR_CTEIF6_Msk                           /*!< Channel 6 Transfer Error clear */
+#define BDMA_IFCR_CGIF7_Pos     (28U)
+#define BDMA_IFCR_CGIF7_Msk     (0x1UL << BDMA_IFCR_CGIF7_Pos)                 /*!< 0x10000000 */
+#define BDMA_IFCR_CGIF7         BDMA_IFCR_CGIF7_Msk                            /*!< Channel 7 Global interrupt clear */
+#define BDMA_IFCR_CTCIF7_Pos    (29U)
+#define BDMA_IFCR_CTCIF7_Msk    (0x1UL << BDMA_IFCR_CTCIF7_Pos)                /*!< 0x20000000 */
+#define BDMA_IFCR_CTCIF7        BDMA_IFCR_CTCIF7_Msk                           /*!< Channel 7 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF7_Pos    (30U)
+#define BDMA_IFCR_CHTIF7_Msk    (0x1UL << BDMA_IFCR_CHTIF7_Pos)                /*!< 0x40000000 */
+#define BDMA_IFCR_CHTIF7        BDMA_IFCR_CHTIF7_Msk                           /*!< Channel 7 Half Transfer clear */
+#define BDMA_IFCR_CTEIF7_Pos    (31U)
+#define BDMA_IFCR_CTEIF7_Msk    (0x1UL << BDMA_IFCR_CTEIF7_Pos)                /*!< 0x80000000 */
+#define BDMA_IFCR_CTEIF7        BDMA_IFCR_CTEIF7_Msk                           /*!< Channel 7 Transfer Error clear */
+
+/*******************  Bit definition for BDMA_CCR register  ********************/
+#define BDMA_CCR_EN_Pos         (0U)
+#define BDMA_CCR_EN_Msk         (0x1UL << BDMA_CCR_EN_Pos)                     /*!< 0x00000001 */
+#define BDMA_CCR_EN             BDMA_CCR_EN_Msk                                /*!< Channel enable                      */
+#define BDMA_CCR_TCIE_Pos       (1U)
+#define BDMA_CCR_TCIE_Msk       (0x1UL << BDMA_CCR_TCIE_Pos)                   /*!< 0x00000002 */
+#define BDMA_CCR_TCIE           BDMA_CCR_TCIE_Msk                              /*!< Transfer complete interrupt enable  */
+#define BDMA_CCR_HTIE_Pos       (2U)
+#define BDMA_CCR_HTIE_Msk       (0x1UL << BDMA_CCR_HTIE_Pos)                   /*!< 0x00000004 */
+#define BDMA_CCR_HTIE           BDMA_CCR_HTIE_Msk                              /*!< Half Transfer interrupt enable      */
+#define BDMA_CCR_TEIE_Pos       (3U)
+#define BDMA_CCR_TEIE_Msk       (0x1UL << BDMA_CCR_TEIE_Pos)                   /*!< 0x00000008 */
+#define BDMA_CCR_TEIE           BDMA_CCR_TEIE_Msk                              /*!< Transfer error interrupt enable     */
+#define BDMA_CCR_DIR_Pos        (4U)
+#define BDMA_CCR_DIR_Msk        (0x1UL << BDMA_CCR_DIR_Pos)                    /*!< 0x00000010 */
+#define BDMA_CCR_DIR            BDMA_CCR_DIR_Msk                               /*!< Data transfer direction             */
+#define BDMA_CCR_CIRC_Pos       (5U)
+#define BDMA_CCR_CIRC_Msk       (0x1UL << BDMA_CCR_CIRC_Pos)                   /*!< 0x00000020 */
+#define BDMA_CCR_CIRC           BDMA_CCR_CIRC_Msk                              /*!< Circular mode                       */
+#define BDMA_CCR_PINC_Pos       (6U)
+#define BDMA_CCR_PINC_Msk       (0x1UL << BDMA_CCR_PINC_Pos)                   /*!< 0x00000040 */
+#define BDMA_CCR_PINC           BDMA_CCR_PINC_Msk                              /*!< Peripheral increment mode           */
+#define BDMA_CCR_MINC_Pos       (7U)
+#define BDMA_CCR_MINC_Msk       (0x1UL << BDMA_CCR_MINC_Pos)                   /*!< 0x00000080 */
+#define BDMA_CCR_MINC           BDMA_CCR_MINC_Msk                              /*!< Memory increment mode               */
+
+#define BDMA_CCR_PSIZE_Pos      (8U)
+#define BDMA_CCR_PSIZE_Msk      (0x3UL << BDMA_CCR_PSIZE_Pos)                  /*!< 0x00000300 */
+#define BDMA_CCR_PSIZE          BDMA_CCR_PSIZE_Msk                             /*!< PSIZE[1:0] bits (Peripheral size)   */
+#define BDMA_CCR_PSIZE_0        (0x1UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000100 */
+#define BDMA_CCR_PSIZE_1        (0x2UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000200 */
+
+#define BDMA_CCR_MSIZE_Pos      (10U)
+#define BDMA_CCR_MSIZE_Msk      (0x3UL << BDMA_CCR_MSIZE_Pos)                  /*!< 0x00000C00 */
+#define BDMA_CCR_MSIZE          BDMA_CCR_MSIZE_Msk                             /*!< MSIZE[1:0] bits (Memory size)       */
+#define BDMA_CCR_MSIZE_0        (0x1UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000400 */
+#define BDMA_CCR_MSIZE_1        (0x2UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000800 */
+
+#define BDMA_CCR_PL_Pos         (12U)
+#define BDMA_CCR_PL_Msk         (0x3UL << BDMA_CCR_PL_Pos)                     /*!< 0x00003000 */
+#define BDMA_CCR_PL             BDMA_CCR_PL_Msk                                /*!< PL[1:0] bits(Channel Priority level)*/
+#define BDMA_CCR_PL_0           (0x1UL << BDMA_CCR_PL_Pos)                      /*!< 0x00001000 */
+#define BDMA_CCR_PL_1           (0x2UL << BDMA_CCR_PL_Pos)                      /*!< 0x00002000 */
+
+#define BDMA_CCR_MEM2MEM_Pos    (14U)
+#define BDMA_CCR_MEM2MEM_Msk    (0x1UL << BDMA_CCR_MEM2MEM_Pos)                /*!< 0x00004000 */
+#define BDMA_CCR_MEM2MEM        BDMA_CCR_MEM2MEM_Msk                           /*!< Memory to memory mode               */
+#define BDMA_CCR_DBM_Pos        (15U)
+#define BDMA_CCR_DBM_Msk        (0x1UL << BDMA_CCR_DBM_Pos)                    /*!< 0x0000A000 */
+#define BDMA_CCR_DBM            BDMA_CCR_DBM_Msk                               /*!< Memory to memory mode               */
+#define BDMA_CCR_CT_Pos         (16U)
+#define BDMA_CCR_CT_Msk         (0x1UL << BDMA_CCR_CT_Pos)                     /*!< 0x00010000 */
+#define BDMA_CCR_CT             BDMA_CCR_CT_Msk                                /*!< Memory to memory mode               */
+
+/******************  Bit definition for BDMA_CNDTR register  *******************/
+#define BDMA_CNDTR_NDT_Pos      (0U)
+#define BDMA_CNDTR_NDT_Msk      (0xFFFFUL << BDMA_CNDTR_NDT_Pos)               /*!< 0x0000FFFF */
+#define BDMA_CNDTR_NDT          BDMA_CNDTR_NDT_Msk                             /*!< Number of data to Transfer          */
+
+/******************  Bit definition for BDMA_CPAR register  ********************/
+#define BDMA_CPAR_PA_Pos        (0U)
+#define BDMA_CPAR_PA_Msk        (0xFFFFFFFFUL << BDMA_CPAR_PA_Pos)             /*!< 0xFFFFFFFF */
+#define BDMA_CPAR_PA            BDMA_CPAR_PA_Msk                               /*!< Peripheral Address                  */
+
+/******************  Bit definition for BDMA_CM0AR register  ********************/
+#define BDMA_CM0AR_MA_Pos        (0U)
+#define BDMA_CM0AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM0AR_MA_Pos)             /*!< 0xFFFFFFFF */
+#define BDMA_CM0AR_MA            BDMA_CM0AR_MA_Msk                               /*!< Memory Address                      */
+
+/******************  Bit definition for BDMA_CM1AR register  ********************/
+#define BDMA_CM1AR_MA_Pos        (0U)
+#define BDMA_CM1AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM1AR_MA_Pos)             /*!< 0xFFFFFFFF */
+#define BDMA_CM1AR_MA            BDMA_CM1AR_MA_Msk                               /*!< Memory Address                      */
+
+/******************************************************************************/
+/*                                                                            */
+/*                Ethernet MAC Registers bits definitions                     */
+/*                                                                            */
+/******************************************************************************/
+/* Bit definition for Ethernet MAC Configuration Register register */
+#define ETH_MACCR_ARP_Pos                             (31U)
+#define ETH_MACCR_ARP_Msk                             (0x1UL << ETH_MACCR_ARP_Pos) /*!< 0x80000000 */
+#define ETH_MACCR_ARP                                 ETH_MACCR_ARP_Msk        /* ARP Offload Enable */
+#define ETH_MACCR_SARC_Pos                            (28U)
+#define ETH_MACCR_SARC_Msk                            (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
+#define ETH_MACCR_SARC                                ETH_MACCR_SARC_Msk       /* Source Address Insertion or Replacement Control */
+#define ETH_MACCR_SARC_MTIATI                         ((uint32_t)0x00000000)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
+#define ETH_MACCR_SARC_INSADDR0_Pos                   (29U)
+#define ETH_MACCR_SARC_INSADDR0_Msk                   (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
+#define ETH_MACCR_SARC_INSADDR0                       ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
+#define ETH_MACCR_SARC_INSADDR1_Pos                   (29U)
+#define ETH_MACCR_SARC_INSADDR1_Msk                   (0x3UL << ETH_MACCR_SARC_INSADDR1_Pos) /*!< 0x60000000 */
+#define ETH_MACCR_SARC_INSADDR1                       ETH_MACCR_SARC_INSADDR1_Msk /* Insert MAC Address1 in the SA field of all transmitted packets. */
+#define ETH_MACCR_SARC_REPADDR0_Pos                   (28U)
+#define ETH_MACCR_SARC_REPADDR0_Msk                   (0x3UL << ETH_MACCR_SARC_REPADDR0_Pos) /*!< 0x30000000 */
+#define ETH_MACCR_SARC_REPADDR0                       ETH_MACCR_SARC_REPADDR0_Msk /* Replace MAC Address0 in the SA field of all transmitted packets. */
+#define ETH_MACCR_SARC_REPADDR1_Pos                   (28U)
+#define ETH_MACCR_SARC_REPADDR1_Msk                   (0x7UL << ETH_MACCR_SARC_REPADDR1_Pos) /*!< 0x70000000 */
+#define ETH_MACCR_SARC_REPADDR1                       ETH_MACCR_SARC_REPADDR1_Msk /* Replace MAC Address1 in the SA field of all transmitted packets. */
+#define ETH_MACCR_IPC_Pos                             (27U)
+#define ETH_MACCR_IPC_Msk                             (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */
+#define ETH_MACCR_IPC                                 ETH_MACCR_IPC_Msk        /* Checksum Offload */
+#define ETH_MACCR_IPG_Pos                             (24U)
+#define ETH_MACCR_IPG_Msk                             (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
+#define ETH_MACCR_IPG                                 ETH_MACCR_IPG_Msk        /* Inter-Packet Gap */
+#define ETH_MACCR_IPG_96BIT                           ((uint32_t)0x00000000)   /* Minimum IFG between Packets during transmission is 96Bit */
+#define ETH_MACCR_IPG_88BIT                           ((uint32_t)0x01000000)   /* Minimum IFG between Packets during transmission is 88Bit */
+#define ETH_MACCR_IPG_80BIT                           ((uint32_t)0x02000000)   /* Minimum IFG between Packets during transmission is 80Bit */
+#define ETH_MACCR_IPG_72BIT                           ((uint32_t)0x03000000)   /* Minimum IFG between Packets during transmission is 72Bit */
+#define ETH_MACCR_IPG_64BIT                           ((uint32_t)0x04000000)   /* Minimum IFG between Packets during transmission is 64Bit */
+#define ETH_MACCR_IPG_56BIT                           ((uint32_t)0x05000000)   /* Minimum IFG between Packets during transmission is 56Bit */
+#define ETH_MACCR_IPG_48BIT                           ((uint32_t)0x06000000)   /* Minimum IFG between Packets during transmission is 48Bit */
+#define ETH_MACCR_IPG_40BIT                           ((uint32_t)0x07000000)   /* Minimum IFG between Packets during transmission is 40Bit */
+#define ETH_MACCR_GPSLCE_Pos                          (23U)
+#define ETH_MACCR_GPSLCE_Msk                          (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
+#define ETH_MACCR_GPSLCE                              ETH_MACCR_GPSLCE_Msk     /* Giant Packet Size Limit Control Enable */
+#define ETH_MACCR_S2KP_Pos                            (22U)
+#define ETH_MACCR_S2KP_Msk                            (0x1UL << ETH_MACCR_S2KP_Pos) /*!< 0x00400000 */
+#define ETH_MACCR_S2KP                                ETH_MACCR_S2KP_Msk       /* IEEE 802.3as Support for 2K Packets */
+#define ETH_MACCR_CST_Pos                             (21U)
+#define ETH_MACCR_CST_Msk                             (0x1UL << ETH_MACCR_CST_Pos) /*!< 0x00200000 */
+#define ETH_MACCR_CST                                 ETH_MACCR_CST_Msk        /* CRC stripping for Type packets */
+#define ETH_MACCR_ACS_Pos                             (20U)
+#define ETH_MACCR_ACS_Msk                             (0x1UL << ETH_MACCR_ACS_Pos) /*!< 0x00100000 */
+#define ETH_MACCR_ACS                                 ETH_MACCR_ACS_Msk        /* Automatic Pad or CRC Stripping */
+#define ETH_MACCR_WD_Pos                              (19U)
+#define ETH_MACCR_WD_Msk                              (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00080000 */
+#define ETH_MACCR_WD                                  ETH_MACCR_WD_Msk         /* Watchdog disable */
+#define ETH_MACCR_JD_Pos                              (17U)
+#define ETH_MACCR_JD_Msk                              (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00020000 */
+#define ETH_MACCR_JD                                  ETH_MACCR_JD_Msk         /* Jabber disable */
+#define ETH_MACCR_JE_Pos                              (16U)
+#define ETH_MACCR_JE_Msk                              (0x1UL << ETH_MACCR_JE_Pos) /*!< 0x00010000 */
+#define ETH_MACCR_JE                                  ETH_MACCR_JE_Msk         /* Jumbo Packet Enable */
+#define ETH_MACCR_FES_Pos                             (14U)
+#define ETH_MACCR_FES_Msk                             (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
+#define ETH_MACCR_FES                                 ETH_MACCR_FES_Msk        /* Fast ethernet speed */
+#define ETH_MACCR_DM_Pos                              (13U)
+#define ETH_MACCR_DM_Msk                              (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00002000 */
+#define ETH_MACCR_DM                                  ETH_MACCR_DM_Msk         /* Duplex mode */
+#define ETH_MACCR_LM_Pos                              (12U)
+#define ETH_MACCR_LM_Msk                              (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
+#define ETH_MACCR_LM                                  ETH_MACCR_LM_Msk         /* loopback mode */
+#define ETH_MACCR_ECRSFD_Pos                          (11U)
+#define ETH_MACCR_ECRSFD_Msk                          (0x1UL << ETH_MACCR_ECRSFD_Pos) /*!< 0x00000800 */
+#define ETH_MACCR_ECRSFD                              ETH_MACCR_ECRSFD_Msk     /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */
+#define ETH_MACCR_DO_Pos                              (10U)
+#define ETH_MACCR_DO_Msk                              (0x1UL << ETH_MACCR_DO_Pos) /*!< 0x00000400 */
+#define ETH_MACCR_DO                                  ETH_MACCR_DO_Msk         /* Disable Receive own  */
+#define ETH_MACCR_DCRS_Pos                            (9U)
+#define ETH_MACCR_DCRS_Msk                            (0x1UL << ETH_MACCR_DCRS_Pos) /*!< 0x00000200 */
+#define ETH_MACCR_DCRS                                ETH_MACCR_DCRS_Msk       /* Disable Carrier Sense During Transmission */
+#define ETH_MACCR_DR_Pos                              (8U)
+#define ETH_MACCR_DR_Msk                              (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */
+#define ETH_MACCR_DR                                  ETH_MACCR_DR_Msk         /* Disable Retry */
+#define ETH_MACCR_BL_Pos                              (5U)
+#define ETH_MACCR_BL_Msk                              (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
+#define ETH_MACCR_BL                                  ETH_MACCR_BL_Msk         /* Back-off limit mask */
+#define ETH_MACCR_BL_10                               (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */
+#define ETH_MACCR_BL_8                                (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */
+#define ETH_MACCR_BL_4                                (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */
+#define ETH_MACCR_BL_1                                (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
+#define ETH_MACCR_DC_Pos                              (4U)
+#define ETH_MACCR_DC_Msk                              (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
+#define ETH_MACCR_DC                                  ETH_MACCR_DC_Msk         /* Defferal check */
+#define ETH_MACCR_PRELEN_Pos                          (2U)
+#define ETH_MACCR_PRELEN_Msk                          (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */
+#define ETH_MACCR_PRELEN                              ETH_MACCR_PRELEN_Msk     /* Preamble Length for Transmit packets */
+#define ETH_MACCR_PRELEN_7                            (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */
+#define ETH_MACCR_PRELEN_5                            (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */
+#define ETH_MACCR_PRELEN_3                            (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */
+#define ETH_MACCR_TE_Pos                              (1U)
+#define ETH_MACCR_TE_Msk                              (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000002 */
+#define ETH_MACCR_TE                                  ETH_MACCR_TE_Msk         /* Transmitter enable */
+#define ETH_MACCR_RE_Pos                              (0U)
+#define ETH_MACCR_RE_Msk                              (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000001 */
+#define ETH_MACCR_RE                                  ETH_MACCR_RE_Msk         /* Receiver enable */
+
+/* Bit definition for Ethernet MAC Extended Configuration Register register */
+#define ETH_MACECR_EIPG_Pos                           (25U)
+#define ETH_MACECR_EIPG_Msk                           (0x1FUL << ETH_MACECR_EIPG_Pos) /*!< 0x3E000000 */
+#define ETH_MACECR_EIPG                               ETH_MACECR_EIPG_Msk      /* Extended Inter-Packet Gap */
+#define ETH_MACECR_EIPGEN_Pos                         (24U)
+#define ETH_MACECR_EIPGEN_Msk                         (0x1UL << ETH_MACECR_EIPGEN_Pos) /*!< 0x01000000 */
+#define ETH_MACECR_EIPGEN                             ETH_MACECR_EIPGEN_Msk    /* Extended Inter-Packet Gap Enable */
+#define ETH_MACECR_USP_Pos                            (18U)
+#define ETH_MACECR_USP_Msk                            (0x1UL << ETH_MACECR_USP_Pos) /*!< 0x00040000 */
+#define ETH_MACECR_USP                                ETH_MACECR_USP_Msk       /* Unicast Slow Protocol Packet Detect */
+#define ETH_MACECR_SPEN_Pos                           (17U)
+#define ETH_MACECR_SPEN_Msk                           (0x1UL << ETH_MACECR_SPEN_Pos) /*!< 0x00020000 */
+#define ETH_MACECR_SPEN                               ETH_MACECR_SPEN_Msk      /* Slow Protocol Detection Enable */
+#define ETH_MACECR_DCRCC_Pos                          (16U)
+#define ETH_MACECR_DCRCC_Msk                          (0x1UL << ETH_MACECR_DCRCC_Pos) /*!< 0x00010000 */
+#define ETH_MACECR_DCRCC                              ETH_MACECR_DCRCC_Msk     /* Disable CRC Checking for Received Packets */
+#define ETH_MACECR_GPSL_Pos                           (0U)
+#define ETH_MACECR_GPSL_Msk                           (0x3FFFUL << ETH_MACECR_GPSL_Pos) /*!< 0x00003FFF */
+#define ETH_MACECR_GPSL                               ETH_MACECR_GPSL_Msk      /* Giant Packet Size Limit */
+
+/* Bit definition for Ethernet MAC Packet Filter Register */
+#define ETH_MACPFR_RA_Pos                             (31U)
+#define ETH_MACPFR_RA_Msk                             (0x1UL << ETH_MACPFR_RA_Pos) /*!< 0x80000000 */
+#define ETH_MACPFR_RA                                 ETH_MACPFR_RA_Msk        /* Receive all */
+#define ETH_MACPFR_DNTU_Pos                           (21U)
+#define ETH_MACPFR_DNTU_Msk                           (0x1UL << ETH_MACPFR_DNTU_Pos) /*!< 0x00200000 */
+#define ETH_MACPFR_DNTU                               ETH_MACPFR_DNTU_Msk      /* Drop Non-TCP/UDP over IP Packets */
+#define ETH_MACPFR_IPFE_Pos                           (20U)
+#define ETH_MACPFR_IPFE_Msk                           (0x1UL << ETH_MACPFR_IPFE_Pos) /*!< 0x00100000 */
+#define ETH_MACPFR_IPFE                               ETH_MACPFR_IPFE_Msk      /* Layer 3 and Layer 4 Filter Enable */
+#define ETH_MACPFR_VTFE_Pos                           (16U)
+#define ETH_MACPFR_VTFE_Msk                           (0x1UL << ETH_MACPFR_VTFE_Pos) /*!< 0x00010000 */
+#define ETH_MACPFR_VTFE                               ETH_MACPFR_VTFE_Msk      /* VLAN Tag Filter Enable */
+#define ETH_MACPFR_HPF_Pos                            (10U)
+#define ETH_MACPFR_HPF_Msk                            (0x1UL << ETH_MACPFR_HPF_Pos) /*!< 0x00000400 */
+#define ETH_MACPFR_HPF                                ETH_MACPFR_HPF_Msk       /* Hash or perfect filter */
+#define ETH_MACPFR_SAF_Pos                            (9U)
+#define ETH_MACPFR_SAF_Msk                            (0x1UL << ETH_MACPFR_SAF_Pos) /*!< 0x00000200 */
+#define ETH_MACPFR_SAF                                ETH_MACPFR_SAF_Msk       /* Source address filter enable */
+#define ETH_MACPFR_SAIF_Pos                           (8U)
+#define ETH_MACPFR_SAIF_Msk                           (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */
+#define ETH_MACPFR_SAIF                               ETH_MACPFR_SAIF_Msk      /* SA inverse filtering */
+#define ETH_MACPFR_PCF_Pos                            (6U)
+#define ETH_MACPFR_PCF_Msk                            (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
+#define ETH_MACPFR_PCF                                ETH_MACPFR_PCF_Msk       /* Pass control frames: 4 cases */
+#define ETH_MACPFR_PCF_BLOCKALL                       ((uint32_t)0x00000000)   /* MAC filters all control frames from reaching the application */
+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos         (6U)
+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk         (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA             ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
+#define ETH_MACPFR_PCF_FORWARDALL_Pos                 (7U)
+#define ETH_MACPFR_PCF_FORWARDALL_Msk                 (0x1UL << ETH_MACPFR_PCF_FORWARDALL_Pos) /*!< 0x00000080 */
+#define ETH_MACPFR_PCF_FORWARDALL                     ETH_MACPFR_PCF_FORWARDALL_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos    (6U)
+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk    (0x3UL << ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos) /*!< 0x000000C0 */
+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER        ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk /* MAC forwards control frames that pass the Address Filter. */
+#define ETH_MACPFR_DBF_Pos                            (5U)
+#define ETH_MACPFR_DBF_Msk                            (0x1UL << ETH_MACPFR_DBF_Pos) /*!< 0x00000020 */
+#define ETH_MACPFR_DBF                                ETH_MACPFR_DBF_Msk       /* Disable Broadcast Packets */
+#define ETH_MACPFR_PM_Pos                             (4U)
+#define ETH_MACPFR_PM_Msk                             (0x1UL << ETH_MACPFR_PM_Pos) /*!< 0x00000010 */
+#define ETH_MACPFR_PM                                 ETH_MACPFR_PM_Msk        /* Pass all mutlicast */
+#define ETH_MACPFR_DAIF_Pos                           (3U)
+#define ETH_MACPFR_DAIF_Msk                           (0x1UL << ETH_MACPFR_DAIF_Pos) /*!< 0x00000008 */
+#define ETH_MACPFR_DAIF                               ETH_MACPFR_DAIF_Msk      /* DA Inverse filtering */
+#define ETH_MACPFR_HMC_Pos                            (2U)
+#define ETH_MACPFR_HMC_Msk                            (0x1UL << ETH_MACPFR_HMC_Pos) /*!< 0x00000004 */
+#define ETH_MACPFR_HMC                                ETH_MACPFR_HMC_Msk       /* Hash multicast */
+#define ETH_MACPFR_HUC_Pos                            (1U)
+#define ETH_MACPFR_HUC_Msk                            (0x1UL << ETH_MACPFR_HUC_Pos) /*!< 0x00000002 */
+#define ETH_MACPFR_HUC                                ETH_MACPFR_HUC_Msk       /* Hash unicast */
+#define ETH_MACPFR_PR_Pos                             (0U)
+#define ETH_MACPFR_PR_Msk                             (0x1UL << ETH_MACPFR_PR_Pos) /*!< 0x00000001 */
+#define ETH_MACPFR_PR                                 ETH_MACPFR_PR_Msk        /* Promiscuous mode */
+
+/* Bit definition for Ethernet MAC Watchdog Timeout Register */
+#define ETH_MACWTR_PWE_Pos                            (8U)
+#define ETH_MACWTR_PWE_Msk                            (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */
+#define ETH_MACWTR_PWE                                ETH_MACWTR_PWE_Msk       /* Programmable Watchdog Enable */
+#define ETH_MACWTR_WTO_Pos                            (0U)
+#define ETH_MACWTR_WTO_Msk                            (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
+#define ETH_MACWTR_WTO                                ETH_MACWTR_WTO_Msk       /* Watchdog Timeout */
+#define ETH_MACWTR_WTO_2KB                            ((uint32_t)0x00000000)   /* Maximum received packet length 2KB*/
+#define ETH_MACWTR_WTO_3KB                            ((uint32_t)0x00000001)   /* Maximum received packet length 3KB */
+#define ETH_MACWTR_WTO_4KB                            ((uint32_t)0x00000002)   /* Maximum received packet length 4KB */
+#define ETH_MACWTR_WTO_5KB                            ((uint32_t)0x00000003)   /* Maximum received packet length 5KB */
+#define ETH_MACWTR_WTO_6KB                            ((uint32_t)0x00000004)   /* Maximum received packet length 6KB */
+#define ETH_MACWTR_WTO_7KB                            ((uint32_t)0x00000005)   /* Maximum received packet length 7KB */
+#define ETH_MACWTR_WTO_8KB                            ((uint32_t)0x00000006)   /* Maximum received packet length 8KB */
+#define ETH_MACWTR_WTO_9KB                            ((uint32_t)0x00000007)   /* Maximum received packet length 9KB */
+#define ETH_MACWTR_WTO_10KB                           ((uint32_t)0x00000008)   /* Maximum received packet length 10KB */
+#define ETH_MACWTR_WTO_11KB                           ((uint32_t)0x00000009)   /* Maximum received packet length 11KB */
+#define ETH_MACWTR_WTO_12KB                           ((uint32_t)0x0000000A)   /* Maximum received packet length 12KB */
+#define ETH_MACWTR_WTO_13KB                           ((uint32_t)0x0000000B)   /* Maximum received packet length 13KB */
+#define ETH_MACWTR_WTO_14KB                           ((uint32_t)0x0000000C)   /* Maximum received packet length 14KB */
+#define ETH_MACWTR_WTO_15KB                           ((uint32_t)0x0000000D)   /* Maximum received packet length 15KB */
+#define ETH_MACWTR_WTO_16KB                           ((uint32_t)0x0000000E)   /* Maximum received packet length 16KB */
+
+/* Bit definition for Ethernet MAC Hash Table High Register */
+#define ETH_MACHTHR_HTH_Pos                           (0U)
+#define ETH_MACHTHR_HTH_Msk                           (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACHTHR_HTH                               ETH_MACHTHR_HTH_Msk      /* Hash table high */
+
+/* Bit definition for Ethernet MAC Hash Table Low Register */
+#define ETH_MACHTLR_HTL_Pos                           (0U)
+#define ETH_MACHTLR_HTL_Msk                           (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACHTLR_HTL                               ETH_MACHTLR_HTL_Msk      /* Hash table low */
+
+/* Bit definition for Ethernet MAC VLAN Tag Register */
+#define ETH_MACVTR_EIVLRXS_Pos                        (31U)
+#define ETH_MACVTR_EIVLRXS_Msk                        (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */
+#define ETH_MACVTR_EIVLRXS                            ETH_MACVTR_EIVLRXS_Msk   /* Enable Inner VLAN Tag in Rx Status */
+#define ETH_MACVTR_EIVLS_Pos                          (28U)
+#define ETH_MACVTR_EIVLS_Msk                          (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
+#define ETH_MACVTR_EIVLS                              ETH_MACVTR_EIVLS_Msk     /* Enable Inner VLAN Tag Stripping on Receive */
+#define ETH_MACVTR_EIVLS_DONOTSTRIP                   ((uint32_t)0x00000000)   /* Do not strip */
+#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos              (28U)
+#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk              (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
+#define ETH_MACVTR_EIVLS_STRIPIFPASS                  ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
+#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos             (29U)
+#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk             (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */
+#define ETH_MACVTR_EIVLS_STRIPIFFAILS                 ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
+#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos              (28U)
+#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk              (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */
+#define ETH_MACVTR_EIVLS_ALWAYSSTRIP                  ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */
+#define ETH_MACVTR_ERIVLT_Pos                         (27U)
+#define ETH_MACVTR_ERIVLT_Msk                         (0x1UL << ETH_MACVTR_ERIVLT_Pos) /*!< 0x08000000 */
+#define ETH_MACVTR_ERIVLT                             ETH_MACVTR_ERIVLT_Msk    /* Enable Inner VLAN Tag */
+#define ETH_MACVTR_EDVLP_Pos                          (26U)
+#define ETH_MACVTR_EDVLP_Msk                          (0x1UL << ETH_MACVTR_EDVLP_Pos) /*!< 0x04000000 */
+#define ETH_MACVTR_EDVLP                              ETH_MACVTR_EDVLP_Msk     /* Enable Double VLAN Processing */
+#define ETH_MACVTR_VTHM_Pos                           (25U)
+#define ETH_MACVTR_VTHM_Msk                           (0x1UL << ETH_MACVTR_VTHM_Pos) /*!< 0x02000000 */
+#define ETH_MACVTR_VTHM                               ETH_MACVTR_VTHM_Msk      /* VLAN Tag Hash Table Match Enable */
+#define ETH_MACVTR_EVLRXS_Pos                         (24U)
+#define ETH_MACVTR_EVLRXS_Msk                         (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */
+#define ETH_MACVTR_EVLRXS                             ETH_MACVTR_EVLRXS_Msk    /* Enable VLAN Tag in Rx status */
+#define ETH_MACVTR_EVLS_Pos                           (21U)
+#define ETH_MACVTR_EVLS_Msk                           (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
+#define ETH_MACVTR_EVLS                               ETH_MACVTR_EVLS_Msk      /* Enable VLAN Tag Stripping on Receive */
+#define ETH_MACVTR_EVLS_DONOTSTRIP                    ((uint32_t)0x00000000)   /* Do not strip */
+#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos               (21U)
+#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk               (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
+#define ETH_MACVTR_EVLS_STRIPIFPASS                   ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
+#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos              (22U)
+#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk              (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */
+#define ETH_MACVTR_EVLS_STRIPIFFAILS                  ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
+#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos               (21U)
+#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk               (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */
+#define ETH_MACVTR_EVLS_ALWAYSSTRIP                   ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */
+#define ETH_MACVTR_DOVLTC_Pos                         (20U)
+#define ETH_MACVTR_DOVLTC_Msk                         (0x1UL << ETH_MACVTR_DOVLTC_Pos) /*!< 0x00100000 */
+#define ETH_MACVTR_DOVLTC                             ETH_MACVTR_DOVLTC_Msk    /* Disable VLAN Type Check */
+#define ETH_MACVTR_ERSVLM_Pos                         (19U)
+#define ETH_MACVTR_ERSVLM_Msk                         (0x1UL << ETH_MACVTR_ERSVLM_Pos) /*!< 0x00080000 */
+#define ETH_MACVTR_ERSVLM                             ETH_MACVTR_ERSVLM_Msk    /* Enable Receive S-VLAN Match */
+#define ETH_MACVTR_ESVL_Pos                           (18U)
+#define ETH_MACVTR_ESVL_Msk                           (0x1UL << ETH_MACVTR_ESVL_Pos) /*!< 0x00040000 */
+#define ETH_MACVTR_ESVL                               ETH_MACVTR_ESVL_Msk      /* Enable S-VLAN */
+#define ETH_MACVTR_VTIM_Pos                           (17U)
+#define ETH_MACVTR_VTIM_Msk                           (0x1UL << ETH_MACVTR_VTIM_Pos) /*!< 0x00020000 */
+#define ETH_MACVTR_VTIM                               ETH_MACVTR_VTIM_Msk      /* VLAN Tag Inverse Match Enable */
+#define ETH_MACVTR_ETV_Pos                            (16U)
+#define ETH_MACVTR_ETV_Msk                            (0x1UL << ETH_MACVTR_ETV_Pos) /*!< 0x00010000 */
+#define ETH_MACVTR_ETV                                ETH_MACVTR_ETV_Msk       /* Enable 12-Bit VLAN Tag Comparison */
+#define ETH_MACVTR_VL_Pos                             (0U)
+#define ETH_MACVTR_VL_Msk                             (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */
+#define ETH_MACVTR_VL                                 ETH_MACVTR_VL_Msk        /* VLAN Tag Identifier for Receive Packets */
+#define ETH_MACVTR_VL_UP_Pos                          (13U)
+#define ETH_MACVTR_VL_UP_Msk                          (0x7UL << ETH_MACVTR_VL_UP_Pos) /*!< 0x0000E000 */
+#define ETH_MACVTR_VL_UP                              ETH_MACVTR_VL_UP_Msk     /* User Priority */
+#define ETH_MACVTR_VL_CFIDEI_Pos                      (12U)
+#define ETH_MACVTR_VL_CFIDEI_Msk                      (0x1UL << ETH_MACVTR_VL_CFIDEI_Pos) /*!< 0x00001000 */
+#define ETH_MACVTR_VL_CFIDEI                          ETH_MACVTR_VL_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
+#define ETH_MACVTR_VL_VID_Pos                         (0U)
+#define ETH_MACVTR_VL_VID_Msk                         (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */
+#define ETH_MACVTR_VL_VID                             ETH_MACVTR_VL_VID_Msk    /* VLAN Identifier field of VLAN tag */
+
+/* Bit definition for Ethernet MAC VLAN Hash Table Register */
+#define ETH_MACVHTR_VLHT_Pos                          (0U)
+#define ETH_MACVHTR_VLHT_Msk                          (0xFFFFUL << ETH_MACVHTR_VLHT_Pos) /*!< 0x0000FFFF */
+#define ETH_MACVHTR_VLHT                              ETH_MACVHTR_VLHT_Msk     /* VLAN Hash Table */
+
+/* Bit definition for Ethernet MAC VLAN Incl Register */
+#define ETH_MACVIR_VLTI_Pos                           (20U)
+#define ETH_MACVIR_VLTI_Msk                           (0x1UL << ETH_MACVIR_VLTI_Pos) /*!< 0x00100000 */
+#define ETH_MACVIR_VLTI                               ETH_MACVIR_VLTI_Msk      /* VLAN Tag Input */
+#define ETH_MACVIR_CSVL_Pos                           (19U)
+#define ETH_MACVIR_CSVL_Msk                           (0x1UL << ETH_MACVIR_CSVL_Pos) /*!< 0x00080000 */
+#define ETH_MACVIR_CSVL                               ETH_MACVIR_CSVL_Msk      /* C-VLAN or S-VLAN */
+#define ETH_MACVIR_VLP_Pos                            (18U)
+#define ETH_MACVIR_VLP_Msk                            (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */
+#define ETH_MACVIR_VLP                                ETH_MACVIR_VLP_Msk       /* VLAN Priority Control */
+#define ETH_MACVIR_VLC_Pos                            (16U)
+#define ETH_MACVIR_VLC_Msk                            (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
+#define ETH_MACVIR_VLC                                ETH_MACVIR_VLC_Msk       /* VLAN Tag Control in Transmit Packets */
+#define ETH_MACVIR_VLC_NOVLANTAG                      ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos              (16U)
+#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
+#define ETH_MACVIR_VLC_VLANTAGDELETE                  ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
+#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos              (17U)
+#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */
+#define ETH_MACVIR_VLC_VLANTAGINSERT                  ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
+#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos             (16U)
+#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk             (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */
+#define ETH_MACVIR_VLC_VLANTAGREPLACE                 ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
+#define ETH_MACVIR_VLT_Pos                            (0U)
+#define ETH_MACVIR_VLT_Msk                            (0xFFFFUL << ETH_MACVIR_VLT_Pos) /*!< 0x0000FFFF */
+#define ETH_MACVIR_VLT                                ETH_MACVIR_VLT_Msk       /* VLAN Tag for Transmit Packets */
+#define ETH_MACVIR_VLT_UP_Pos                         (13U)
+#define ETH_MACVIR_VLT_UP_Msk                         (0x7UL << ETH_MACVIR_VLT_UP_Pos) /*!< 0x0000E000 */
+#define ETH_MACVIR_VLT_UP                             ETH_MACVIR_VLT_UP_Msk    /* User Priority */
+#define ETH_MACVIR_VLT_CFIDEI_Pos                     (12U)
+#define ETH_MACVIR_VLT_CFIDEI_Msk                     (0x1UL << ETH_MACVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */
+#define ETH_MACVIR_VLT_CFIDEI                         ETH_MACVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
+#define ETH_MACVIR_VLT_VID_Pos                        (0U)
+#define ETH_MACVIR_VLT_VID_Msk                        (0xFFFUL << ETH_MACVIR_VLT_VID_Pos) /*!< 0x00000FFF */
+#define ETH_MACVIR_VLT_VID                            ETH_MACVIR_VLT_VID_Msk   /* VLAN Identifier field of VLAN tag */
+
+/* Bit definition for Ethernet MAC Inner_VLAN Incl Register */
+#define ETH_MACIVIR_VLTI_Pos                          (20U)
+#define ETH_MACIVIR_VLTI_Msk                          (0x1UL << ETH_MACIVIR_VLTI_Pos) /*!< 0x00100000 */
+#define ETH_MACIVIR_VLTI                              ETH_MACIVIR_VLTI_Msk     /* VLAN Tag Input */
+#define ETH_MACIVIR_CSVL_Pos                          (19U)
+#define ETH_MACIVIR_CSVL_Msk                          (0x1UL << ETH_MACIVIR_CSVL_Pos) /*!< 0x00080000 */
+#define ETH_MACIVIR_CSVL                              ETH_MACIVIR_CSVL_Msk     /* C-VLAN or S-VLAN */
+#define ETH_MACIVIR_VLP_Pos                           (18U)
+#define ETH_MACIVIR_VLP_Msk                           (0x1UL << ETH_MACIVIR_VLP_Pos) /*!< 0x00040000 */
+#define ETH_MACIVIR_VLP                               ETH_MACIVIR_VLP_Msk      /* VLAN Priority Control */
+#define ETH_MACIVIR_VLC_Pos                           (16U)
+#define ETH_MACIVIR_VLC_Msk                           (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
+#define ETH_MACIVIR_VLC                               ETH_MACIVIR_VLC_Msk      /* VLAN Tag Control in Transmit Packets */
+#define ETH_MACIVIR_VLC_NOVLANTAG                     ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos             (16U)
+#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
+#define ETH_MACIVIR_VLC_VLANTAGDELETE                 ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
+#define ETH_MACIVIR_VLC_VLANTAGINSERT_Pos             (17U)
+#define ETH_MACIVIR_VLC_VLANTAGINSERT_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */
+#define ETH_MACIVIR_VLC_VLANTAGINSERT                 ETH_MACIVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
+#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos            (16U)
+#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk            (0x3UL << ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */
+#define ETH_MACIVIR_VLC_VLANTAGREPLACE                ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
+#define ETH_MACIVIR_VLT_Pos                           (0U)
+#define ETH_MACIVIR_VLT_Msk                           (0xFFFFUL << ETH_MACIVIR_VLT_Pos) /*!< 0x0000FFFF */
+#define ETH_MACIVIR_VLT                               ETH_MACIVIR_VLT_Msk      /* VLAN Tag for Transmit Packets */
+#define ETH_MACIVIR_VLT_UP_Pos                        (13U)
+#define ETH_MACIVIR_VLT_UP_Msk                        (0x7UL << ETH_MACIVIR_VLT_UP_Pos) /*!< 0x0000E000 */
+#define ETH_MACIVIR_VLT_UP                            ETH_MACIVIR_VLT_UP_Msk   /* User Priority */
+#define ETH_MACIVIR_VLT_CFIDEI_Pos                    (12U)
+#define ETH_MACIVIR_VLT_CFIDEI_Msk                    (0x1UL << ETH_MACIVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */
+#define ETH_MACIVIR_VLT_CFIDEI                        ETH_MACIVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
+#define ETH_MACIVIR_VLT_VID_Pos                       (0U)
+#define ETH_MACIVIR_VLT_VID_Msk                       (0xFFFUL << ETH_MACIVIR_VLT_VID_Pos) /*!< 0x00000FFF */
+#define ETH_MACIVIR_VLT_VID                           ETH_MACIVIR_VLT_VID_Msk  /* VLAN Identifier field of VLAN tag */
+
+/* Bit definition for Ethernet MAC Tx Flow Ctrl Register */
+#define ETH_MACTFCR_PT_Pos                            (16U)
+#define ETH_MACTFCR_PT_Msk                            (0xFFFFUL << ETH_MACTFCR_PT_Pos) /*!< 0xFFFF0000 */
+#define ETH_MACTFCR_PT                                ETH_MACTFCR_PT_Msk       /* Pause Time */
+#define ETH_MACTFCR_DZPQ_Pos                          (7U)
+#define ETH_MACTFCR_DZPQ_Msk                          (0x1UL << ETH_MACTFCR_DZPQ_Pos) /*!< 0x00000080 */
+#define ETH_MACTFCR_DZPQ                              ETH_MACTFCR_DZPQ_Msk     /* Disable Zero-Quanta Pause */
+#define ETH_MACTFCR_PLT_Pos                           (4U)
+#define ETH_MACTFCR_PLT_Msk                           (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */
+#define ETH_MACTFCR_PLT                               ETH_MACTFCR_PLT_Msk      /* Pause Low Threshold */
+#define ETH_MACTFCR_PLT_MINUS4                        ((uint32_t)0x00000000)   /* Pause time minus 4 slot times */
+#define ETH_MACTFCR_PLT_MINUS28_Pos                   (4U)
+#define ETH_MACTFCR_PLT_MINUS28_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
+#define ETH_MACTFCR_PLT_MINUS28                       ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
+#define ETH_MACTFCR_PLT_MINUS36_Pos                   (5U)
+#define ETH_MACTFCR_PLT_MINUS36_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS36_Pos) /*!< 0x00000020 */
+#define ETH_MACTFCR_PLT_MINUS36                       ETH_MACTFCR_PLT_MINUS36_Msk /* Pause time minus 36 slot times */
+#define ETH_MACTFCR_PLT_MINUS144_Pos                  (4U)
+#define ETH_MACTFCR_PLT_MINUS144_Msk                  (0x3UL << ETH_MACTFCR_PLT_MINUS144_Pos) /*!< 0x00000030 */
+#define ETH_MACTFCR_PLT_MINUS144                      ETH_MACTFCR_PLT_MINUS144_Msk /* Pause time minus 144 slot times */
+#define ETH_MACTFCR_PLT_MINUS256_Pos                  (6U)
+#define ETH_MACTFCR_PLT_MINUS256_Msk                  (0x1UL << ETH_MACTFCR_PLT_MINUS256_Pos) /*!< 0x00000040 */
+#define ETH_MACTFCR_PLT_MINUS256                      ETH_MACTFCR_PLT_MINUS256_Msk /* Pause time minus 256 slot times */
+#define ETH_MACTFCR_PLT_MINUS512_Pos                  (4U)
+#define ETH_MACTFCR_PLT_MINUS512_Msk                  (0x5UL << ETH_MACTFCR_PLT_MINUS512_Pos) /*!< 0x00000050 */
+#define ETH_MACTFCR_PLT_MINUS512                      ETH_MACTFCR_PLT_MINUS512_Msk /* Pause time minus 512 slot times */
+#define ETH_MACTFCR_TFE_Pos                           (1U)
+#define ETH_MACTFCR_TFE_Msk                           (0x1UL << ETH_MACTFCR_TFE_Pos) /*!< 0x00000002 */
+#define ETH_MACTFCR_TFE                               ETH_MACTFCR_TFE_Msk      /* Transmit Flow Control Enable */
+#define ETH_MACTFCR_FCB_Pos                           (0U)
+#define ETH_MACTFCR_FCB_Msk                           (0x1UL << ETH_MACTFCR_FCB_Pos) /*!< 0x00000001 */
+#define ETH_MACTFCR_FCB                               ETH_MACTFCR_FCB_Msk      /* Flow Control Busy or Backpressure Activate */
+
+/* Bit definition for Ethernet MAC Rx Flow Ctrl Register */
+#define ETH_MACRFCR_UP_Pos                            (1U)
+#define ETH_MACRFCR_UP_Msk                            (0x1UL << ETH_MACRFCR_UP_Pos) /*!< 0x00000002 */
+#define ETH_MACRFCR_UP                                ETH_MACRFCR_UP_Msk       /* Unicast Pause Packet Detect */
+#define ETH_MACRFCR_RFE_Pos                           (0U)
+#define ETH_MACRFCR_RFE_Msk                           (0x1UL << ETH_MACRFCR_RFE_Pos) /*!< 0x00000001 */
+#define ETH_MACRFCR_RFE                               ETH_MACRFCR_RFE_Msk      /* Receive Flow Control Enable */
+
+/* Bit definition for Ethernet MAC Interrupt Status Register */
+#define ETH_MACISR_RXSTSIS_Pos                        (14U)
+#define ETH_MACISR_RXSTSIS_Msk                        (0x1UL << ETH_MACISR_RXSTSIS_Pos) /*!< 0x00004000 */
+#define ETH_MACISR_RXSTSIS                            ETH_MACISR_RXSTSIS_Msk   /* Receive Status Interrupt */
+#define ETH_MACISR_TXSTSIS_Pos                        (13U)
+#define ETH_MACISR_TXSTSIS_Msk                        (0x1UL << ETH_MACISR_TXSTSIS_Pos) /*!< 0x00002000 */
+#define ETH_MACISR_TXSTSIS                            ETH_MACISR_TXSTSIS_Msk   /* Transmit Status Interrupt */
+#define ETH_MACISR_TSIS_Pos                           (12U)
+#define ETH_MACISR_TSIS_Msk                           (0x1UL << ETH_MACISR_TSIS_Pos) /*!< 0x00001000 */
+#define ETH_MACISR_TSIS                               ETH_MACISR_TSIS_Msk      /* Timestamp Interrupt Status */
+#define ETH_MACISR_MMCTXIS_Pos                        (10U)
+#define ETH_MACISR_MMCTXIS_Msk                        (0x1UL << ETH_MACISR_MMCTXIS_Pos) /*!< 0x00000400 */
+#define ETH_MACISR_MMCTXIS                            ETH_MACISR_MMCTXIS_Msk   /* MMC Transmit Interrupt Status */
+#define ETH_MACISR_MMCRXIS_Pos                        (9U)
+#define ETH_MACISR_MMCRXIS_Msk                        (0x1UL << ETH_MACISR_MMCRXIS_Pos) /*!< 0x00000200 */
+#define ETH_MACISR_MMCRXIS                            ETH_MACISR_MMCRXIS_Msk   /* MMC Receive Interrupt Status */
+#define ETH_MACISR_MMCIS_Pos                          (8U)
+#define ETH_MACISR_MMCIS_Msk                          (0x1UL << ETH_MACISR_MMCIS_Pos) /*!< 0x00000100 */
+#define ETH_MACISR_MMCIS                              ETH_MACISR_MMCIS_Msk     /* MMC Interrupt Status */
+#define ETH_MACISR_LPIIS_Pos                          (5U)
+#define ETH_MACISR_LPIIS_Msk                          (0x1UL << ETH_MACISR_LPIIS_Pos) /*!< 0x00000020 */
+#define ETH_MACISR_LPIIS                              ETH_MACISR_LPIIS_Msk     /* LPI Interrupt Status */
+#define ETH_MACISR_PMTIS_Pos                          (4U)
+#define ETH_MACISR_PMTIS_Msk                          (0x1UL << ETH_MACISR_PMTIS_Pos) /*!< 0x00000010 */
+#define ETH_MACISR_PMTIS                              ETH_MACISR_PMTIS_Msk     /* PMT Interrupt Status */
+#define ETH_MACISR_PHYIS_Pos                          (3U)
+#define ETH_MACISR_PHYIS_Msk                          (0x1UL << ETH_MACISR_PHYIS_Pos) /*!< 0x00000008 */
+#define ETH_MACISR_PHYIS                              ETH_MACISR_PHYIS_Msk     /* PHY Interrupt */
+
+/* Bit definition for Ethernet MAC Interrupt Enable Register */
+#define ETH_MACIER_RXSTSIE_Pos                        (14U)
+#define ETH_MACIER_RXSTSIE_Msk                        (0x1UL << ETH_MACIER_RXSTSIE_Pos) /*!< 0x00004000 */
+#define ETH_MACIER_RXSTSIE                            ETH_MACIER_RXSTSIE_Msk   /* Receive Status Interrupt Enable */
+#define ETH_MACIER_TXSTSIE_Pos                        (13U)
+#define ETH_MACIER_TXSTSIE_Msk                        (0x1UL << ETH_MACIER_TXSTSIE_Pos) /*!< 0x00002000 */
+#define ETH_MACIER_TXSTSIE                            ETH_MACIER_TXSTSIE_Msk   /* Transmit Status Interrupt Enable */
+#define ETH_MACIER_TSIE_Pos                           (12U)
+#define ETH_MACIER_TSIE_Msk                           (0x1UL << ETH_MACIER_TSIE_Pos) /*!< 0x00001000 */
+#define ETH_MACIER_TSIE                               ETH_MACIER_TSIE_Msk      /* Timestamp Interrupt Enable */
+#define ETH_MACIER_LPIIE_Pos                          (5U)
+#define ETH_MACIER_LPIIE_Msk                          (0x1UL << ETH_MACIER_LPIIE_Pos) /*!< 0x00000020 */
+#define ETH_MACIER_LPIIE                              ETH_MACIER_LPIIE_Msk     /* LPI Interrupt Enable */
+#define ETH_MACIER_PMTIE_Pos                          (4U)
+#define ETH_MACIER_PMTIE_Msk                          (0x1UL << ETH_MACIER_PMTIE_Pos) /*!< 0x00000010 */
+#define ETH_MACIER_PMTIE                              ETH_MACIER_PMTIE_Msk     /* PMT Interrupt Enable */
+#define ETH_MACIER_PHYIE_Pos                          (3U)
+#define ETH_MACIER_PHYIE_Msk                          (0x1UL << ETH_MACIER_PHYIE_Pos) /*!< 0x00000008 */
+#define ETH_MACIER_PHYIE                              ETH_MACIER_PHYIE_Msk     /* PHY Interrupt Enable */
+
+/* Bit definition for Ethernet MAC Rx Tx Status Register */
+#define ETH_MACRXTXSR_RWT_Pos                         (8U)
+#define ETH_MACRXTXSR_RWT_Msk                         (0x1UL << ETH_MACRXTXSR_RWT_Pos) /*!< 0x00000100 */
+#define ETH_MACRXTXSR_RWT                             ETH_MACRXTXSR_RWT_Msk    /* Receive Watchdog Timeout */
+#define ETH_MACRXTXSR_EXCOL_Pos                       (5U)
+#define ETH_MACRXTXSR_EXCOL_Msk                       (0x1UL << ETH_MACRXTXSR_EXCOL_Pos) /*!< 0x00000020 */
+#define ETH_MACRXTXSR_EXCOL                           ETH_MACRXTXSR_EXCOL_Msk  /* Excessive Collisions */
+#define ETH_MACRXTXSR_LCOL_Pos                        (4U)
+#define ETH_MACRXTXSR_LCOL_Msk                        (0x1UL << ETH_MACRXTXSR_LCOL_Pos) /*!< 0x00000010 */
+#define ETH_MACRXTXSR_LCOL                            ETH_MACRXTXSR_LCOL_Msk   /* Late Collision */
+#define ETH_MACRXTXSR_EXDEF_Pos                       (3U)
+#define ETH_MACRXTXSR_EXDEF_Msk                       (0x1UL << ETH_MACRXTXSR_EXDEF_Pos) /*!< 0x00000008 */
+#define ETH_MACRXTXSR_EXDEF                           ETH_MACRXTXSR_EXDEF_Msk  /* Excessive Deferral */
+#define ETH_MACRXTXSR_LCARR_Pos                       (2U)
+#define ETH_MACRXTXSR_LCARR_Msk                       (0x1UL << ETH_MACRXTXSR_LCARR_Pos) /*!< 0x00000004 */
+#define ETH_MACRXTXSR_LCARR                           ETH_MACRXTXSR_LCARR_Msk  /* Loss of Carrier */
+#define ETH_MACRXTXSR_NCARR_Pos                       (1U)
+#define ETH_MACRXTXSR_NCARR_Msk                       (0x1UL << ETH_MACRXTXSR_NCARR_Pos) /*!< 0x00000002 */
+#define ETH_MACRXTXSR_NCARR                           ETH_MACRXTXSR_NCARR_Msk  /* No Carrier */
+#define ETH_MACRXTXSR_TJT_Pos                         (0U)
+#define ETH_MACRXTXSR_TJT_Msk                         (0x1UL << ETH_MACRXTXSR_TJT_Pos) /*!< 0x00000001 */
+#define ETH_MACRXTXSR_TJT                             ETH_MACRXTXSR_TJT_Msk    /* Transmit Jabber Timeout */
+
+/* Bit definition for Ethernet MAC PMT Control Status Register */
+#define ETH_MACPCSR_RWKFILTRST_Pos                    (31U)
+#define ETH_MACPCSR_RWKFILTRST_Msk                    (0x1UL << ETH_MACPCSR_RWKFILTRST_Pos) /*!< 0x80000000 */
+#define ETH_MACPCSR_RWKFILTRST                        ETH_MACPCSR_RWKFILTRST_Msk /* Remote Wake-Up Packet Filter Register Pointer Reset */
+#define ETH_MACPCSR_RWKPTR_Pos                        (24U)
+#define ETH_MACPCSR_RWKPTR_Msk                        (0x1FUL << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x1F000000 */
+#define ETH_MACPCSR_RWKPTR                            ETH_MACPCSR_RWKPTR_Msk   /* Remote Wake-up FIFO Pointer */
+#define ETH_MACPCSR_RWKPFE_Pos                        (10U)
+#define ETH_MACPCSR_RWKPFE_Msk                        (0x1UL << ETH_MACPCSR_RWKPFE_Pos) /*!< 0x00000400 */
+#define ETH_MACPCSR_RWKPFE                            ETH_MACPCSR_RWKPFE_Msk   /* Remote Wake-up Packet Forwarding Enable */
+#define ETH_MACPCSR_GLBLUCAST_Pos                     (9U)
+#define ETH_MACPCSR_GLBLUCAST_Msk                     (0x1UL << ETH_MACPCSR_GLBLUCAST_Pos) /*!< 0x00000200 */
+#define ETH_MACPCSR_GLBLUCAST                         ETH_MACPCSR_GLBLUCAST_Msk /* Global Unicast */
+#define ETH_MACPCSR_RWKPRCVD_Pos                      (6U)
+#define ETH_MACPCSR_RWKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_RWKPRCVD_Pos) /*!< 0x00000040 */
+#define ETH_MACPCSR_RWKPRCVD                          ETH_MACPCSR_RWKPRCVD_Msk /* Remote Wake-Up Packet Received */
+#define ETH_MACPCSR_MGKPRCVD_Pos                      (5U)
+#define ETH_MACPCSR_MGKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_MGKPRCVD_Pos) /*!< 0x00000020 */
+#define ETH_MACPCSR_MGKPRCVD                          ETH_MACPCSR_MGKPRCVD_Msk /* Magic Packet Received */
+#define ETH_MACPCSR_RWKPKTEN_Pos                      (2U)
+#define ETH_MACPCSR_RWKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_RWKPKTEN_Pos) /*!< 0x00000004 */
+#define ETH_MACPCSR_RWKPKTEN                          ETH_MACPCSR_RWKPKTEN_Msk /* Remote Wake-Up Packet Enable */
+#define ETH_MACPCSR_MGKPKTEN_Pos                      (1U)
+#define ETH_MACPCSR_MGKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_MGKPKTEN_Pos) /*!< 0x00000002 */
+#define ETH_MACPCSR_MGKPKTEN                          ETH_MACPCSR_MGKPKTEN_Msk /* Magic Packet Enable */
+#define ETH_MACPCSR_PWRDWN_Pos                        (0U)
+#define ETH_MACPCSR_PWRDWN_Msk                        (0x1UL << ETH_MACPCSR_PWRDWN_Pos) /*!< 0x00000001 */
+#define ETH_MACPCSR_PWRDWN                            ETH_MACPCSR_PWRDWN_Msk   /* Power Down */
+
+/* Bit definition for Ethernet MAC Remote Wake-Up Packet Filter Register */
+#define ETH_MACRWUPFR_D_Pos                           (0U)
+#define ETH_MACRWUPFR_D_Msk                           (0xFFFFFFFFUL << ETH_MACRWUPFR_D_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACRWUPFR_D                               ETH_MACRWUPFR_D_Msk      /* Wake-up Packet filter register data */
+
+/* Bit definition for Ethernet MAC LPI Control Status Register */
+#define ETH_MACLCSR_LPITCSE_Pos                       (21U)
+#define ETH_MACLCSR_LPITCSE_Msk                       (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */
+#define ETH_MACLCSR_LPITCSE                           ETH_MACLCSR_LPITCSE_Msk  /* LPI Tx Clock Stop Enable */
+#define ETH_MACLCSR_LPITE_Pos                         (20U)
+#define ETH_MACLCSR_LPITE_Msk                         (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */
+#define ETH_MACLCSR_LPITE                             ETH_MACLCSR_LPITE_Msk    /* LPI Timer Enable */
+#define ETH_MACLCSR_LPITXA_Pos                        (19U)
+#define ETH_MACLCSR_LPITXA_Msk                        (0x1UL << ETH_MACLCSR_LPITXA_Pos) /*!< 0x00080000 */
+#define ETH_MACLCSR_LPITXA                            ETH_MACLCSR_LPITXA_Msk   /* LPI Tx Automate */
+#define ETH_MACLCSR_PLS_Pos                           (17U)
+#define ETH_MACLCSR_PLS_Msk                           (0x1UL << ETH_MACLCSR_PLS_Pos) /*!< 0x00020000 */
+#define ETH_MACLCSR_PLS                               ETH_MACLCSR_PLS_Msk      /* PHY Link Status */
+#define ETH_MACLCSR_LPIEN_Pos                         (16U)
+#define ETH_MACLCSR_LPIEN_Msk                         (0x1UL << ETH_MACLCSR_LPIEN_Pos) /*!< 0x00010000 */
+#define ETH_MACLCSR_LPIEN                             ETH_MACLCSR_LPIEN_Msk    /* LPI Enable */
+#define ETH_MACLCSR_RLPIST_Pos                        (9U)
+#define ETH_MACLCSR_RLPIST_Msk                        (0x1UL << ETH_MACLCSR_RLPIST_Pos) /*!< 0x00000200 */
+#define ETH_MACLCSR_RLPIST                            ETH_MACLCSR_RLPIST_Msk   /* Receive LPI State */
+#define ETH_MACLCSR_TLPIST_Pos                        (8U)
+#define ETH_MACLCSR_TLPIST_Msk                        (0x1UL << ETH_MACLCSR_TLPIST_Pos) /*!< 0x00000100 */
+#define ETH_MACLCSR_TLPIST                            ETH_MACLCSR_TLPIST_Msk   /* Transmit LPI State */
+#define ETH_MACLCSR_RLPIEX_Pos                        (3U)
+#define ETH_MACLCSR_RLPIEX_Msk                        (0x1UL << ETH_MACLCSR_RLPIEX_Pos) /*!< 0x00000008 */
+#define ETH_MACLCSR_RLPIEX                            ETH_MACLCSR_RLPIEX_Msk   /* Receive LPI Exit */
+#define ETH_MACLCSR_RLPIEN_Pos                        (2U)
+#define ETH_MACLCSR_RLPIEN_Msk                        (0x1UL << ETH_MACLCSR_RLPIEN_Pos) /*!< 0x00000004 */
+#define ETH_MACLCSR_RLPIEN                            ETH_MACLCSR_RLPIEN_Msk   /* Receive LPI Entry */
+#define ETH_MACLCSR_TLPIEX_Pos                        (1U)
+#define ETH_MACLCSR_TLPIEX_Msk                        (0x1UL << ETH_MACLCSR_TLPIEX_Pos) /*!< 0x00000002 */
+#define ETH_MACLCSR_TLPIEX                            ETH_MACLCSR_TLPIEX_Msk   /* Transmit LPI Exit */
+#define ETH_MACLCSR_TLPIEN_Pos                        (0U)
+#define ETH_MACLCSR_TLPIEN_Msk                        (0x1UL << ETH_MACLCSR_TLPIEN_Pos) /*!< 0x00000001 */
+#define ETH_MACLCSR_TLPIEN                            ETH_MACLCSR_TLPIEN_Msk   /* Transmit LPI Entry */
+
+/* Bit definition for Ethernet MAC LPI Timers Control Register */
+#define ETH_MACLTCR_LST_Pos                           (16U)
+#define ETH_MACLTCR_LST_Msk                           (0x3FFUL << ETH_MACLTCR_LST_Pos) /*!< 0x03FF0000 */
+#define ETH_MACLTCR_LST                               ETH_MACLTCR_LST_Msk      /* LPI LS TIMER */
+#define ETH_MACLTCR_TWT_Pos                           (0U)
+#define ETH_MACLTCR_TWT_Msk                           (0xFFFFUL << ETH_MACLTCR_TWT_Pos) /*!< 0x0000FFFF */
+#define ETH_MACLTCR_TWT                               ETH_MACLTCR_TWT_Msk      /* LPI TW TIMER */
+
+/* Bit definition for Ethernet MAC LPI Entry Timer Register */
+#define ETH_MACLETR_LPIET_Pos                         (0U)
+#define ETH_MACLETR_LPIET_Msk                         (0xFFFFFUL << ETH_MACLETR_LPIET_Pos) /*!< 0x000FFFFF */
+#define ETH_MACLETR_LPIET                             ETH_MACLETR_LPIET_Msk    /* LPI Entry Timer */
+
+/* Bit definition for Ethernet MAC 1US Tic Counter Register */
+#define ETH_MAC1USTCR_TIC1USCNTR_Pos                  (0U)
+#define ETH_MAC1USTCR_TIC1USCNTR_Msk                  (0xFFFUL << ETH_MAC1USTCR_TIC1USCNTR_Pos) /*!< 0x00000FFF */
+#define ETH_MAC1USTCR_TIC1USCNTR                      ETH_MAC1USTCR_TIC1USCNTR_Msk /* 1US TIC Counter */
+
+/* Bit definition for Ethernet MAC Version Register */
+#define ETH_MACVR_USERVER_Pos                         (8U)
+#define ETH_MACVR_USERVER_Msk                         (0xFFUL << ETH_MACVR_USERVER_Pos) /*!< 0x0000FF00 */
+#define ETH_MACVR_USERVER                             ETH_MACVR_USERVER_Msk    /* User-defined Version */
+#define ETH_MACVR_SNPSVER_Pos                         (0U)
+#define ETH_MACVR_SNPSVER_Msk                         (0xFFUL << ETH_MACVR_SNPSVER_Pos) /*!< 0x000000FF */
+#define ETH_MACVR_SNPSVER                             ETH_MACVR_SNPSVER_Msk    /* Synopsys-defined Version */
+
+/* Bit definition for Ethernet MAC Debug Register */
+#define ETH_MACDR_TFCSTS_Pos                          (17U)
+#define ETH_MACDR_TFCSTS_Msk                          (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
+#define ETH_MACDR_TFCSTS                              ETH_MACDR_TFCSTS_Msk     /* MAC Transmit Packet Controller Status */
+#define ETH_MACDR_TFCSTS_IDLE                         ((uint32_t)0x00000000)   /* Idle state */
+#define ETH_MACDR_TFCSTS_WAIT_Pos                     (17U)
+#define ETH_MACDR_TFCSTS_WAIT_Msk                     (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
+#define ETH_MACDR_TFCSTS_WAIT                         ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
+#define ETH_MACDR_TFCSTS_GENERATEPCP_Pos              (18U)
+#define ETH_MACDR_TFCSTS_GENERATEPCP_Msk              (0x1UL << ETH_MACDR_TFCSTS_GENERATEPCP_Pos) /*!< 0x00040000 */
+#define ETH_MACDR_TFCSTS_GENERATEPCP                  ETH_MACDR_TFCSTS_GENERATEPCP_Msk /* Generating and transmitting a Pause control packet */
+#define ETH_MACDR_TFCSTS_TRASFERIP_Pos                (17U)
+#define ETH_MACDR_TFCSTS_TRASFERIP_Msk                (0x3UL << ETH_MACDR_TFCSTS_TRASFERIP_Pos) /*!< 0x00060000 */
+#define ETH_MACDR_TFCSTS_TRASFERIP                    ETH_MACDR_TFCSTS_TRASFERIP_Msk /* Transferring input packet for transmission */
+#define ETH_MACDR_TPESTS_Pos                          (16U)
+#define ETH_MACDR_TPESTS_Msk                          (0x1UL << ETH_MACDR_TPESTS_Pos) /*!< 0x00010000 */
+#define ETH_MACDR_TPESTS                              ETH_MACDR_TPESTS_Msk     /* MAC Receive Packet Controller FIFO Status */
+#define ETH_MACDR_RFCFCSTS_Pos                        (1U)
+#define ETH_MACDR_RFCFCSTS_Msk                        (0x3UL << ETH_MACDR_RFCFCSTS_Pos) /*!< 0x00000006 */
+#define ETH_MACDR_RFCFCSTS                            ETH_MACDR_RFCFCSTS_Msk   /* MAC MII Transmit Protocol Engine Status */
+#define ETH_MACDR_RPESTS_Pos                          (0U)
+#define ETH_MACDR_RPESTS_Msk                          (0x1UL << ETH_MACDR_RPESTS_Pos) /*!< 0x00000001 */
+#define ETH_MACDR_RPESTS                              ETH_MACDR_RPESTS_Msk     /* MAC MII Receive Protocol Engine Status */
+
+/* Bit definition for Ethernet MAC HW Feature0 Register */
+#define ETH_MACHWF0R_ACTPHYSEL_Pos                    (28U)
+#define ETH_MACHWF0R_ACTPHYSEL_Msk                    (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
+#define ETH_MACHWF0R_ACTPHYSEL                        ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
+#define ETH_MACHWF0R_ACTPHYSEL_MII                    ((uint32_t)0x00000000)   /* MII */
+#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos               (30U)
+#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk               (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
+#define ETH_MACHWF0R_ACTPHYSEL_RMII                   ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
+#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos             (28U)
+#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk             (0x7UL << ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos) /*!< 0x70000000 */
+#define ETH_MACHWF0R_ACTPHYSEL_REVMII                 ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk /* RevMII */
+#define ETH_MACHWF0R_SAVLANINS_Pos                    (27U)
+#define ETH_MACHWF0R_SAVLANINS_Msk                    (0x1UL << ETH_MACHWF0R_SAVLANINS_Pos) /*!< 0x08000000 */
+#define ETH_MACHWF0R_SAVLANINS                        ETH_MACHWF0R_SAVLANINS_Msk /* Source Address or VLAN Insertion Enable */
+#define ETH_MACHWF0R_TSSTSSEL_Pos                     (25U)
+#define ETH_MACHWF0R_TSSTSSEL_Msk                     (0x3UL << ETH_MACHWF0R_TSSTSSEL_Pos) /*!< 0x06000000 */
+#define ETH_MACHWF0R_TSSTSSEL                         ETH_MACHWF0R_TSSTSSEL_Msk /* Timestamp System Time Source */
+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos            (25U)
+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos) /*!< 0x02000000 */
+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL                ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk /* Timestamp System Time Source: Internal */
+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos            (26U)
+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos) /*!< 0x04000000 */
+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL                ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk /* Timestamp System Time Source: External */
+#define ETH_MACHWF0R_TSSTSSEL_BOTH_Pos                (25U)
+#define ETH_MACHWF0R_TSSTSSEL_BOTH_Msk                (0x3UL << ETH_MACHWF0R_TSSTSSEL_BOTH_Pos) /*!< 0x06000000 */
+#define ETH_MACHWF0R_TSSTSSEL_BOTH                    ETH_MACHWF0R_TSSTSSEL_BOTH_Msk /* Timestamp System Time Source: Internal & External */
+#define ETH_MACHWF0R_MACADR64SEL_Pos                  (24U)
+#define ETH_MACHWF0R_MACADR64SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR64SEL_Pos) /*!< 0x01000000 */
+#define ETH_MACHWF0R_MACADR64SEL                      ETH_MACHWF0R_MACADR64SEL_Msk /* MAC Addresses 64-127 Selected */
+#define ETH_MACHWF0R_MACADR32SEL_Pos                  (23U)
+#define ETH_MACHWF0R_MACADR32SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR32SEL_Pos) /*!< 0x00800000 */
+#define ETH_MACHWF0R_MACADR32SEL                      ETH_MACHWF0R_MACADR32SEL_Msk /* MAC Addresses 32-63 Selected */
+#define ETH_MACHWF0R_ADDMACADRSEL_Pos                 (18U)
+#define ETH_MACHWF0R_ADDMACADRSEL_Msk                 (0x1FUL << ETH_MACHWF0R_ADDMACADRSEL_Pos) /*!< 0x007C0000 */
+#define ETH_MACHWF0R_ADDMACADRSEL                     ETH_MACHWF0R_ADDMACADRSEL_Msk /* MAC Addresses 1- 31 Selected */
+#define ETH_MACHWF0R_RXCOESEL_Pos                     (16U)
+#define ETH_MACHWF0R_RXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_RXCOESEL_Pos) /*!< 0x00010000 */
+#define ETH_MACHWF0R_RXCOESEL                         ETH_MACHWF0R_RXCOESEL_Msk /* Receive Checksum Offload Enabled */
+#define ETH_MACHWF0R_TXCOESEL_Pos                     (14U)
+#define ETH_MACHWF0R_TXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_TXCOESEL_Pos) /*!< 0x00004000 */
+#define ETH_MACHWF0R_TXCOESEL                         ETH_MACHWF0R_TXCOESEL_Msk /* Transmit Checksum Offload Enabled */
+#define ETH_MACHWF0R_EEESEL_Pos                       (13U)
+#define ETH_MACHWF0R_EEESEL_Msk                       (0x1UL << ETH_MACHWF0R_EEESEL_Pos) /*!< 0x00002000 */
+#define ETH_MACHWF0R_EEESEL                           ETH_MACHWF0R_EEESEL_Msk  /* Energy Efficient Ethernet Enabled */
+#define ETH_MACHWF0R_TSSEL_Pos                        (12U)
+#define ETH_MACHWF0R_TSSEL_Msk                        (0x1UL << ETH_MACHWF0R_TSSEL_Pos) /*!< 0x00001000 */
+#define ETH_MACHWF0R_TSSEL                            ETH_MACHWF0R_TSSEL_Msk   /* IEEE 1588-2008 Timestamp Enabled */
+#define ETH_MACHWF0R_ARPOFFSEL_Pos                    (9U)
+#define ETH_MACHWF0R_ARPOFFSEL_Msk                    (0x1UL << ETH_MACHWF0R_ARPOFFSEL_Pos) /*!< 0x00000200 */
+#define ETH_MACHWF0R_ARPOFFSEL                        ETH_MACHWF0R_ARPOFFSEL_Msk /* ARP Offload Enabled */
+#define ETH_MACHWF0R_MMCSEL_Pos                       (8U)
+#define ETH_MACHWF0R_MMCSEL_Msk                       (0x1UL << ETH_MACHWF0R_MMCSEL_Pos) /*!< 0x00000100 */
+#define ETH_MACHWF0R_MMCSEL                           ETH_MACHWF0R_MMCSEL_Msk  /* RMON Module Enable */
+#define ETH_MACHWF0R_MGKSEL_Pos                       (7U)
+#define ETH_MACHWF0R_MGKSEL_Msk                       (0x1UL << ETH_MACHWF0R_MGKSEL_Pos) /*!< 0x00000080 */
+#define ETH_MACHWF0R_MGKSEL                           ETH_MACHWF0R_MGKSEL_Msk  /* PMT Magic Packet Enable */
+#define ETH_MACHWF0R_RWKSEL_Pos                       (6U)
+#define ETH_MACHWF0R_RWKSEL_Msk                       (0x1UL << ETH_MACHWF0R_RWKSEL_Pos) /*!< 0x00000040 */
+#define ETH_MACHWF0R_RWKSEL                           ETH_MACHWF0R_RWKSEL_Msk  /* PMT Remote Wake-up Packet Enable */
+#define ETH_MACHWF0R_SMASEL_Pos                       (5U)
+#define ETH_MACHWF0R_SMASEL_Msk                       (0x1UL << ETH_MACHWF0R_SMASEL_Pos) /*!< 0x00000020 */
+#define ETH_MACHWF0R_SMASEL                           ETH_MACHWF0R_SMASEL_Msk  /* SMA (MDIO) Interface */
+#define ETH_MACHWF0R_VLHASH_Pos                       (4U)
+#define ETH_MACHWF0R_VLHASH_Msk                       (0x1UL << ETH_MACHWF0R_VLHASH_Pos) /*!< 0x00000010 */
+#define ETH_MACHWF0R_VLHASH                           ETH_MACHWF0R_VLHASH_Msk  /* VLAN Hash Filter Selected */
+#define ETH_MACHWF0R_PCSSEL_Pos                       (3U)
+#define ETH_MACHWF0R_PCSSEL_Msk                       (0x1UL << ETH_MACHWF0R_PCSSEL_Pos) /*!< 0x00000008 */
+#define ETH_MACHWF0R_PCSSEL                           ETH_MACHWF0R_PCSSEL_Msk  /* PCS Registers (TBI, SGMII, or RTBI PHY interface) */
+#define ETH_MACHWF0R_HDSEL_Pos                        (2U)
+#define ETH_MACHWF0R_HDSEL_Msk                        (0x1UL << ETH_MACHWF0R_HDSEL_Pos) /*!< 0x00000004 */
+#define ETH_MACHWF0R_HDSEL                            ETH_MACHWF0R_HDSEL_Msk   /* Half-duplex Support */
+#define ETH_MACHWF0R_GMIISEL_Pos                      (1U)
+#define ETH_MACHWF0R_GMIISEL_Msk                      (0x1UL << ETH_MACHWF0R_GMIISEL_Pos) /*!< 0x00000002 */
+#define ETH_MACHWF0R_GMIISEL                          ETH_MACHWF0R_GMIISEL_Msk /* 1000 Mbps Support */
+#define ETH_MACHWF0R_MIISEL_Pos                       (0U)
+#define ETH_MACHWF0R_MIISEL_Msk                       (0x1UL << ETH_MACHWF0R_MIISEL_Pos) /*!< 0x00000001 */
+#define ETH_MACHWF0R_MIISEL                           ETH_MACHWF0R_MIISEL_Msk  /* 10 or 100 Mbps Support */
+
+/* Bit definition for Ethernet MAC HW Feature1 Register */
+#define ETH_MACHWF1R_L3L4FNUM_Pos                     (27U)
+#define ETH_MACHWF1R_L3L4FNUM_Msk                     (0xFUL << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x78000000 */
+#define ETH_MACHWF1R_L3L4FNUM                         ETH_MACHWF1R_L3L4FNUM_Msk /* Total number of L3 or L4 Filters */
+#define ETH_MACHWF1R_HASHTBLSZ_Pos                    (24U)
+#define ETH_MACHWF1R_HASHTBLSZ_Msk                    (0x3UL << ETH_MACHWF1R_HASHTBLSZ_Pos) /*!< 0x03000000 */
+#define ETH_MACHWF1R_HASHTBLSZ                        ETH_MACHWF1R_HASHTBLSZ_Msk /* Hash Table Size */
+#define ETH_MACHWF1R_AVSEL_Pos                        (20U)
+#define ETH_MACHWF1R_AVSEL_Msk                        (0x1UL << ETH_MACHWF1R_AVSEL_Pos) /*!< 0x00100000 */
+#define ETH_MACHWF1R_AVSEL                            ETH_MACHWF1R_AVSEL_Msk   /* AV Feature Enabled */
+#define ETH_MACHWF1R_DBGMEMA_Pos                      (19U)
+#define ETH_MACHWF1R_DBGMEMA_Msk                      (0x1UL << ETH_MACHWF1R_DBGMEMA_Pos) /*!< 0x00080000 */
+#define ETH_MACHWF1R_DBGMEMA                          ETH_MACHWF1R_DBGMEMA_Msk /* Debug Memory Interface Enabled */
+#define ETH_MACHWF1R_TSOEN_Pos                        (18U)
+#define ETH_MACHWF1R_TSOEN_Msk                        (0x1UL << ETH_MACHWF1R_TSOEN_Pos) /*!< 0x00040000 */
+#define ETH_MACHWF1R_TSOEN                            ETH_MACHWF1R_TSOEN_Msk   /* TCP Segmentation Offload Enable */
+#define ETH_MACHWF1R_SPHEN_Pos                        (17U)
+#define ETH_MACHWF1R_SPHEN_Msk                        (0x1UL << ETH_MACHWF1R_SPHEN_Pos) /*!< 0x00020000 */
+#define ETH_MACHWF1R_SPHEN                            ETH_MACHWF1R_SPHEN_Msk   /* Split Header Feature Enable */
+#define ETH_MACHWF1R_DCBEN_Pos                        (16U)
+#define ETH_MACHWF1R_DCBEN_Msk                        (0x1UL << ETH_MACHWF1R_DCBEN_Pos) /*!< 0x00010000 */
+#define ETH_MACHWF1R_DCBEN                            ETH_MACHWF1R_DCBEN_Msk   /* DCB Feature Enable */
+#define ETH_MACHWF1R_ADDR64_Pos                       (14U)
+#define ETH_MACHWF1R_ADDR64_Msk                       (0x3UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x0000C000 */
+#define ETH_MACHWF1R_ADDR64                           ETH_MACHWF1R_ADDR64_Msk  /* Address Width */
+#define ETH_MACHWF1R_ADDR64_32                        (0x0UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00000000 */
+#define ETH_MACHWF1R_ADDR64_40                        (0x1UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00004000 */
+#define ETH_MACHWF1R_ADDR64_48                        (0x2UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00008000 */
+#define ETH_MACHWF1R_ADVTHWORD_Pos                    (13U)
+#define ETH_MACHWF1R_ADVTHWORD_Msk                    (0x1UL << ETH_MACHWF1R_ADVTHWORD_Pos) /*!< 0x00002000 */
+#define ETH_MACHWF1R_ADVTHWORD                        ETH_MACHWF1R_ADVTHWORD_Msk /* IEEE 1588 High Word Register Enable */
+#define ETH_MACHWF1R_PTOEN_Pos                        (12U)
+#define ETH_MACHWF1R_PTOEN_Msk                        (0x1UL << ETH_MACHWF1R_PTOEN_Pos) /*!< 0x00001000 */
+#define ETH_MACHWF1R_PTOEN                            ETH_MACHWF1R_PTOEN_Msk   /* PTP Offload Enable */
+#define ETH_MACHWF1R_OSTEN_Pos                        (11U)
+#define ETH_MACHWF1R_OSTEN_Msk                        (0x1UL << ETH_MACHWF1R_OSTEN_Pos) /*!< 0x00000800 */
+#define ETH_MACHWF1R_OSTEN                            ETH_MACHWF1R_OSTEN_Msk   /* One-Step Timestamping Enable */
+#define ETH_MACHWF1R_TXFIFOSIZE_Pos                   (6U)
+#define ETH_MACHWF1R_TXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x000007C0 */
+#define ETH_MACHWF1R_TXFIFOSIZE                       ETH_MACHWF1R_TXFIFOSIZE_Msk /* MTL Transmit FIFO Size */
+#define ETH_MACHWF1R_RXFIFOSIZE_Pos                   (0U)
+#define ETH_MACHWF1R_RXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x0000001F */
+#define ETH_MACHWF1R_RXFIFOSIZE                       ETH_MACHWF1R_RXFIFOSIZE_Msk /* MTL Receive FIFO Size */
+
+/* Bit definition for Ethernet MAC HW Feature2 Register */
+#define ETH_MACHWF2R_AUXSNAPNUM_Pos                   (28U)
+#define ETH_MACHWF2R_AUXSNAPNUM_Msk                   (0x7UL << ETH_MACHWF2R_AUXSNAPNUM_Pos) /*!< 0x70000000 */
+#define ETH_MACHWF2R_AUXSNAPNUM                       ETH_MACHWF2R_AUXSNAPNUM_Msk /* Number of Auxiliary Snapshot Inputs */
+#define ETH_MACHWF2R_PPSOUTNUM_Pos                    (24U)
+#define ETH_MACHWF2R_PPSOUTNUM_Msk                    (0x7UL << ETH_MACHWF2R_PPSOUTNUM_Pos) /*!< 0x07000000 */
+#define ETH_MACHWF2R_PPSOUTNUM                        ETH_MACHWF2R_PPSOUTNUM_Msk /*  Number of PPS Outputs */
+#define ETH_MACHWF2R_TXCHCNT_Pos                      (18U)
+#define ETH_MACHWF2R_TXCHCNT_Msk                      (0xFUL << ETH_MACHWF2R_TXCHCNT_Pos) /*!< 0x003C0000 */
+#define ETH_MACHWF2R_TXCHCNT                          ETH_MACHWF2R_TXCHCNT_Msk /* Number of DMA Transmit Channels */
+#define ETH_MACHWF2R_RXCHCNT_Pos                      (13U)
+#define ETH_MACHWF2R_RXCHCNT_Msk                      (0x7UL << ETH_MACHWF2R_RXCHCNT_Pos) /*!< 0x0000E000 */
+#define ETH_MACHWF2R_RXCHCNT                          ETH_MACHWF2R_RXCHCNT_Msk /* Number of DMA Receive Channels */
+#define ETH_MACHWF2R_TXQCNT_Pos                       (6U)
+#define ETH_MACHWF2R_TXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_TXQCNT_Pos) /*!< 0x000003C0 */
+#define ETH_MACHWF2R_TXQCNT                           ETH_MACHWF2R_TXQCNT_Msk  /* Number of MTL Transmit Queues */
+#define ETH_MACHWF2R_RXQCNT_Pos                       (0U)
+#define ETH_MACHWF2R_RXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_RXQCNT_Pos) /*!< 0x0000000F */
+#define ETH_MACHWF2R_RXQCNT                           ETH_MACHWF2R_RXQCNT_Msk  /* Number of MTL Receive Queues */
+
+/* Bit definition for Ethernet MAC MDIO Address Register */
+#define ETH_MACMDIOAR_PSE_Pos                         (27U)
+#define ETH_MACMDIOAR_PSE_Msk                         (0x1UL << ETH_MACMDIOAR_PSE_Pos) /*!< 0x08000000 */
+#define ETH_MACMDIOAR_PSE                             ETH_MACMDIOAR_PSE_Msk    /* Preamble Suppression Enable */
+#define ETH_MACMDIOAR_BTB_Pos                         (26U)
+#define ETH_MACMDIOAR_BTB_Msk                         (0x1UL << ETH_MACMDIOAR_BTB_Pos) /*!< 0x04000000 */
+#define ETH_MACMDIOAR_BTB                             ETH_MACMDIOAR_BTB_Msk    /* Back to Back transactions */
+#define ETH_MACMDIOAR_PA_Pos                          (21U)
+#define ETH_MACMDIOAR_PA_Msk                          (0x1FUL << ETH_MACMDIOAR_PA_Pos) /*!< 0x03E00000 */
+#define ETH_MACMDIOAR_PA                              ETH_MACMDIOAR_PA_Msk     /* Physical Layer Address */
+#define ETH_MACMDIOAR_RDA_Pos                         (16U)
+#define ETH_MACMDIOAR_RDA_Msk                         (0x1FUL << ETH_MACMDIOAR_RDA_Pos) /*!< 0x001F0000 */
+#define ETH_MACMDIOAR_RDA                             ETH_MACMDIOAR_RDA_Msk    /* Register/Device Address */
+#define ETH_MACMDIOAR_NTC_Pos                         (12U)
+#define ETH_MACMDIOAR_NTC_Msk                         (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */
+#define ETH_MACMDIOAR_NTC                             ETH_MACMDIOAR_NTC_Msk    /* Number of Trailing Clocks */
+#define ETH_MACMDIOAR_CR_Pos                          (8U)
+#define ETH_MACMDIOAR_CR_Msk                          (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
+#define ETH_MACMDIOAR_CR                              ETH_MACMDIOAR_CR_Msk     /* CSR Clock Range */
+#define ETH_MACMDIOAR_CR_DIV42                        ((uint32_t)0x00000000)   /* CSR clock/42 */
+#define ETH_MACMDIOAR_CR_DIV62_Pos                    (8U)
+#define ETH_MACMDIOAR_CR_DIV62_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
+#define ETH_MACMDIOAR_CR_DIV62                        ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
+#define ETH_MACMDIOAR_CR_DIV16_Pos                    (9U)
+#define ETH_MACMDIOAR_CR_DIV16_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV16_Pos) /*!< 0x00000200 */
+#define ETH_MACMDIOAR_CR_DIV16                        ETH_MACMDIOAR_CR_DIV16_Msk /* CSR clock/16 */
+#define ETH_MACMDIOAR_CR_DIV26_Pos                    (8U)
+#define ETH_MACMDIOAR_CR_DIV26_Msk                    (0x3UL << ETH_MACMDIOAR_CR_DIV26_Pos) /*!< 0x00000300 */
+#define ETH_MACMDIOAR_CR_DIV26                        ETH_MACMDIOAR_CR_DIV26_Msk /* CSR clock/26 */
+#define ETH_MACMDIOAR_CR_DIV102_Pos                   (10U)
+#define ETH_MACMDIOAR_CR_DIV102_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV102_Pos) /*!< 0x00000400 */
+#define ETH_MACMDIOAR_CR_DIV102                       ETH_MACMDIOAR_CR_DIV102_Msk /* CSR clock/102 */
+#define ETH_MACMDIOAR_CR_DIV124_Pos                   (8U)
+#define ETH_MACMDIOAR_CR_DIV124_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV124_Pos) /*!< 0x00000500 */
+#define ETH_MACMDIOAR_CR_DIV124                       ETH_MACMDIOAR_CR_DIV124_Msk /* CSR clock/124 */
+#define ETH_MACMDIOAR_CR_DIV4AR_Pos                   (11U)
+#define ETH_MACMDIOAR_CR_DIV4AR_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV4AR_Pos) /*!< 0x00000800 */
+#define ETH_MACMDIOAR_CR_DIV4AR                       ETH_MACMDIOAR_CR_DIV4AR_Msk /* CSR clock/4: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV6AR_Pos                   (8U)
+#define ETH_MACMDIOAR_CR_DIV6AR_Msk                   (0x9UL << ETH_MACMDIOAR_CR_DIV6AR_Pos) /*!< 0x00000900 */
+#define ETH_MACMDIOAR_CR_DIV6AR                       ETH_MACMDIOAR_CR_DIV6AR_Msk /* CSR clock/6: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV8AR_Pos                   (9U)
+#define ETH_MACMDIOAR_CR_DIV8AR_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV8AR_Pos) /*!< 0x00000A00 */
+#define ETH_MACMDIOAR_CR_DIV8AR                       ETH_MACMDIOAR_CR_DIV8AR_Msk /* CSR clock/8: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV10AR_Pos                  (8U)
+#define ETH_MACMDIOAR_CR_DIV10AR_Msk                  (0xBUL << ETH_MACMDIOAR_CR_DIV10AR_Pos) /*!< 0x00000B00 */
+#define ETH_MACMDIOAR_CR_DIV10AR                      ETH_MACMDIOAR_CR_DIV10AR_Msk /* CSR clock/10: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV12AR_Pos                  (10U)
+#define ETH_MACMDIOAR_CR_DIV12AR_Msk                  (0x3UL << ETH_MACMDIOAR_CR_DIV12AR_Pos) /*!< 0x00000C00 */
+#define ETH_MACMDIOAR_CR_DIV12AR                      ETH_MACMDIOAR_CR_DIV12AR_Msk /* CSR clock/12: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV14AR_Pos                  (8U)
+#define ETH_MACMDIOAR_CR_DIV14AR_Msk                  (0xDUL << ETH_MACMDIOAR_CR_DIV14AR_Pos) /*!< 0x00000D00 */
+#define ETH_MACMDIOAR_CR_DIV14AR                      ETH_MACMDIOAR_CR_DIV14AR_Msk /* CSR clock/14: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV16AR_Pos                  (9U)
+#define ETH_MACMDIOAR_CR_DIV16AR_Msk                  (0x7UL << ETH_MACMDIOAR_CR_DIV16AR_Pos) /*!< 0x00000E00 */
+#define ETH_MACMDIOAR_CR_DIV16AR                      ETH_MACMDIOAR_CR_DIV16AR_Msk /* CSR clock/16: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV18AR_Pos                  (8U)
+#define ETH_MACMDIOAR_CR_DIV18AR_Msk                  (0xFUL << ETH_MACMDIOAR_CR_DIV18AR_Pos) /*!< 0x00000F00 */
+#define ETH_MACMDIOAR_CR_DIV18AR                      ETH_MACMDIOAR_CR_DIV18AR_Msk /* CSR clock/18: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_SKAP_Pos                        (4U)
+#define ETH_MACMDIOAR_SKAP_Msk                        (0x1UL << ETH_MACMDIOAR_SKAP_Pos) /*!< 0x00000010 */
+#define ETH_MACMDIOAR_SKAP                            ETH_MACMDIOAR_SKAP_Msk   /* Skip Address Packet */
+#define ETH_MACMDIOAR_MOC_Pos                         (2U)
+#define ETH_MACMDIOAR_MOC_Msk                         (0x3UL << ETH_MACMDIOAR_MOC_Pos) /*!< 0x0000000C */
+#define ETH_MACMDIOAR_MOC                             ETH_MACMDIOAR_MOC_Msk    /* MII Operation Command */
+#define ETH_MACMDIOAR_MOC_WR_Pos                      (2U)
+#define ETH_MACMDIOAR_MOC_WR_Msk                      (0x1UL << ETH_MACMDIOAR_MOC_WR_Pos) /*!< 0x00000004 */
+#define ETH_MACMDIOAR_MOC_WR                          ETH_MACMDIOAR_MOC_WR_Msk /* Write */
+#define ETH_MACMDIOAR_MOC_PRDIA_Pos                   (3U)
+#define ETH_MACMDIOAR_MOC_PRDIA_Msk                   (0x1UL << ETH_MACMDIOAR_MOC_PRDIA_Pos) /*!< 0x00000008 */
+#define ETH_MACMDIOAR_MOC_PRDIA                       ETH_MACMDIOAR_MOC_PRDIA_Msk /* Post Read Increment Address for Clause 45 PHY */
+#define ETH_MACMDIOAR_MOC_RD_Pos                      (2U)
+#define ETH_MACMDIOAR_MOC_RD_Msk                      (0x3UL << ETH_MACMDIOAR_MOC_RD_Pos) /*!< 0x0000000C */
+#define ETH_MACMDIOAR_MOC_RD                          ETH_MACMDIOAR_MOC_RD_Msk /* Read */
+#define ETH_MACMDIOAR_C45E_Pos                        (1U)
+#define ETH_MACMDIOAR_C45E_Msk                        (0x1UL << ETH_MACMDIOAR_C45E_Pos) /*!< 0x00000002 */
+#define ETH_MACMDIOAR_C45E                            ETH_MACMDIOAR_C45E_Msk   /* Clause 45 PHY Enable */
+#define ETH_MACMDIOAR_MB_Pos                          (0U)
+#define ETH_MACMDIOAR_MB_Msk                          (0x1UL << ETH_MACMDIOAR_MB_Pos) /*!< 0x00000001 */
+#define ETH_MACMDIOAR_MB                              ETH_MACMDIOAR_MB_Msk     /* MII Busy */
+
+/* Bit definition for Ethernet MAC MDIO Data Register */
+#define ETH_MACMDIODR_RA_Pos                          (16U)
+#define ETH_MACMDIODR_RA_Msk                          (0xFFFFUL << ETH_MACMDIODR_RA_Pos) /*!< 0xFFFF0000 */
+#define ETH_MACMDIODR_RA                              ETH_MACMDIODR_RA_Msk     /* Register Address */
+#define ETH_MACMDIODR_MD_Pos                          (0U)
+#define ETH_MACMDIODR_MD_Msk                          (0xFFFFUL << ETH_MACMDIODR_MD_Pos) /*!< 0x0000FFFF */
+#define ETH_MACMDIODR_MD                              ETH_MACMDIODR_MD_Msk     /* MII Data */
+
+/* Bit definition for Ethernet ARP Address Register */
+#define ETH_MACARPAR_ARPPA_Pos                         (0U)
+#define ETH_MACARPAR_ARPPA_Msk                         (0xFFFFFFFFUL << ETH_MACARPAR_ARPPA_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACARPAR_ARPPA                             ETH_MACARPAR_ARPPA_Msk     /* ARP Protocol Address */
+
+/* Bit definition for Ethernet MAC Address 0 High Register */
+#define ETH_MACA0HR_AE_Pos                            (31U)
+#define ETH_MACA0HR_AE_Msk                            (0x1UL << ETH_MACA0HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA0HR_AE                                ETH_MACA0HR_AE_Msk /* Address Enable*/
+#define ETH_MACA0HR_ADDRHI_Pos                        (0U)
+#define ETH_MACA0HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA0HR_ADDRHI                            ETH_MACA0HR_ADDRHI_Msk   /* MAC Address 0*/
+
+/* Bit definition for Ethernet MAC Address 0 Low Register */
+#define ETH_MACA0LR_ADDRLO_Pos                        (0U)
+#define ETH_MACA0LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA0LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA0LR_ADDRLO                            ETH_MACA0LR_ADDRLO_Msk   /* MAC Address 0*/
+
+/* Bit definition for Ethernet MAC Address 1 High Register */
+#define ETH_MACA1HR_AE_Pos                            (31U)
+#define ETH_MACA1HR_AE_Msk                            (0x1UL << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA1HR_AE                                ETH_MACA1HR_AE_Msk /* Address Enable*/
+#define ETH_MACA1HR_SA_Pos                            (30U)
+#define ETH_MACA1HR_SA_Msk                            (0x1UL << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA1HR_SA                                ETH_MACA1HR_SA_Msk /* Source Address */
+#define ETH_MACA1HR_MBC_Pos                           (24U)
+#define ETH_MACA1HR_MBC_Msk                           (0x3FUL << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA1HR_MBC                               ETH_MACA1HR_MBC_Msk /* Mask Byte Control */
+#define ETH_MACA1HR_ADDRHI_Pos                        (0U)
+#define ETH_MACA1HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA1HR_ADDRHI                            ETH_MACA1HR_ADDRHI_Msk   /* MAC Address 1*/
+
+/* Bit definition for Ethernet MAC Address 1 Low Register */
+#define ETH_MACA1LR_ADDRLO_Pos                        (0U)
+#define ETH_MACA1LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA1LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA1LR_ADDRLO                            ETH_MACA1LR_ADDRLO_Msk   /* MAC Address 1*/
+
+/* Bit definition for Ethernet MAC Address 2 High Register */
+#define ETH_MACA2HR_AE_Pos                            (31U)
+#define ETH_MACA2HR_AE_Msk                            (0x1UL << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA2HR_AE                                ETH_MACA2HR_AE_Msk /* Address Enable*/
+#define ETH_MACA2HR_SA_Pos                            (30U)
+#define ETH_MACA2HR_SA_Msk                            (0x1UL << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA2HR_SA                                ETH_MACA2HR_SA_Msk /* Source Address */
+#define ETH_MACA2HR_MBC_Pos                           (24U)
+#define ETH_MACA2HR_MBC_Msk                           (0x3FUL << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA2HR_MBC                               ETH_MACA2HR_MBC_Msk /* Mask Byte Control */
+#define ETH_MACA2HR_ADDRHI_Pos                        (0U)
+#define ETH_MACA2HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA2HR_ADDRHI                            ETH_MACA2HR_ADDRHI_Msk   /* MAC Address 1*/
+
+/* Bit definition for Ethernet MAC Address 2 Low Register */
+#define ETH_MACA2LR_ADDRLO_Pos                        (0U)
+#define ETH_MACA2LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA2LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA2LR_ADDRLO                            ETH_MACA2LR_ADDRLO_Msk   /* MAC Address 2*/
+
+/* Bit definition for Ethernet MAC Address 3 High Register */
+#define ETH_MACA3HR_AE_Pos                            (31U)
+#define ETH_MACA3HR_AE_Msk                            (0x1UL << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA3HR_AE                                ETH_MACA3HR_AE_Msk /* Address Enable*/
+#define ETH_MACA3HR_SA_Pos                            (30U)
+#define ETH_MACA3HR_SA_Msk                            (0x1UL << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA3HR_SA                                ETH_MACA3HR_SA_Msk /* Source Address */
+#define ETH_MACA3HR_MBC_Pos                           (24U)
+#define ETH_MACA3HR_MBC_Msk                           (0x3FUL << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA3HR_MBC                               ETH_MACA3HR_MBC_Msk /* Mask Byte Control */
+#define ETH_MACA3HR_ADDRHI_Pos                        (0U)
+#define ETH_MACA3HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA3HR_ADDRHI                            ETH_MACA3HR_ADDRHI_Msk   /* MAC Address 1*/
+
+/* Bit definition for Ethernet MAC Address 3 Low Register */
+#define ETH_MACA3LR_ADDRLO_Pos                        (0U)
+#define ETH_MACA3LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA3LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA3LR_ADDRLO                            ETH_MACA3LR_ADDRLO_Msk   /* MAC Address 3*/
+
+/* Bit definition for Ethernet MAC Address High Register */
+#define ETH_MACAHR_AE_Pos                             (31U)
+#define ETH_MACAHR_AE_Msk                             (0x1UL << ETH_MACAHR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACAHR_AE                                 ETH_MACAHR_AE_Msk        /* Address enable */
+#define ETH_MACAHR_SA_Pos                             (30U)
+#define ETH_MACAHR_SA_Msk                             (0x1UL << ETH_MACAHR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACAHR_SA                                 ETH_MACAHR_SA_Msk        /* Source address */
+#define ETH_MACAHR_MBC_Pos                            (24U)
+#define ETH_MACAHR_MBC_Msk                            (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACAHR_MBC                                ETH_MACAHR_MBC_Msk       /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+#define ETH_MACAHR_MBC_HBITS15_8                      ((uint32_t)0x20000000)   /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACAHR_MBC_HBITS7_0                       ((uint32_t)0x10000000)   /* Mask MAC Address high reg bits [7:0] */
+#define ETH_MACAHR_MBC_LBITS31_24                     ((uint32_t)0x08000000)   /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACAHR_MBC_LBITS23_16                     ((uint32_t)0x04000000)   /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACAHR_MBC_LBITS15_8                      ((uint32_t)0x02000000)   /* Mask MAC Address low reg bits [15:8] */
+#define ETH_MACAHR_MBC_LBITS7_0                       ((uint32_t)0x01000000)   /* Mask MAC Address low reg bits [7:0] */
+#define ETH_MACAHR_MACAH_Pos                          (0U)
+#define ETH_MACAHR_MACAH_Msk                          (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */
+#define ETH_MACAHR_MACAH                              ETH_MACAHR_MACAH_Msk     /* MAC address high */
+
+/* Bit definition for Ethernet MAC Address Low Register */
+#define ETH_MACALR_MACAL_Pos                          (0U)
+#define ETH_MACALR_MACAL_Msk                          (0xFFFFFFFFUL << ETH_MACALR_MACAL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACALR_MACAL                              ETH_MACALR_MACAL_Msk     /* MAC address low */
+
+/* Bit definition for Ethernet MMC Control Register */
+#define ETH_MMCCR_UCDBC_Pos                           (8U)
+#define ETH_MMCCR_UCDBC_Msk                           (0x1UL << ETH_MMCCR_UCDBC_Pos) /*!< 0x00000100 */
+#define ETH_MMCCR_UCDBC                               ETH_MMCCR_UCDBC_Msk  /* Update MMC Counters for Dropped Broadcast Packets */
+#define ETH_MMCCR_CNTPRSTLVL_Pos                      (5U)
+#define ETH_MMCCR_CNTPRSTLVL_Msk                      (0x1UL << ETH_MMCCR_CNTPRSTLVL_Pos) /*!< 0x00000020 */
+#define ETH_MMCCR_CNTPRSTLVL                          ETH_MMCCR_CNTPRSTLVL_Msk  /* Full-Half Preset */
+#define ETH_MMCCR_CNTPRST_Pos                         (4U)
+#define ETH_MMCCR_CNTPRST_Msk                         (0x1UL << ETH_MMCCR_CNTPRST_Pos) /*!< 0x00000010 */
+#define ETH_MMCCR_CNTPRST                             ETH_MMCCR_CNTPRST_Msk  /* Counters Reset */
+#define ETH_MMCCR_CNTFREEZ_Pos                        (3U)
+#define ETH_MMCCR_CNTFREEZ_Msk                        (0x1UL << ETH_MMCCR_CNTFREEZ_Pos) /*!< 0x00000008 */
+#define ETH_MMCCR_CNTFREEZ                            ETH_MMCCR_CNTFREEZ_Msk  /* MMC Counter Freeze */
+#define ETH_MMCCR_RSTONRD_Pos                         (2U)
+#define ETH_MMCCR_RSTONRD_Msk                         (0x1UL << ETH_MMCCR_RSTONRD_Pos) /*!< 0x00000004 */
+#define ETH_MMCCR_RSTONRD                             ETH_MMCCR_RSTONRD_Msk  /* Reset On Read */
+#define ETH_MMCCR_CNTSTOPRO_Pos                       (1U)
+#define ETH_MMCCR_CNTSTOPRO_Msk                       (0x1UL << ETH_MMCCR_CNTSTOPRO_Pos) /*!< 0x00000002 */
+#define ETH_MMCCR_CNTSTOPRO                           ETH_MMCCR_CNTSTOPRO_Msk  /* Counter Stop Rollover */
+#define ETH_MMCCR_CNTRST_Pos                          (0U)
+#define ETH_MMCCR_CNTRST_Msk                          (0x1UL << ETH_MMCCR_CNTRST_Pos) /*!< 0x00000001 */
+#define ETH_MMCCR_CNTRST                              ETH_MMCCR_CNTRST_Msk  /* Counters Reset */
+
+/* Bit definition for Ethernet MMC Rx Interrupt Register */
+#define ETH_MMCRIR_RXLPITRCIS_Pos                     (27U)
+#define ETH_MMCRIR_RXLPITRCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPITRCIS_Pos) /*!< 0x08000000 */
+#define ETH_MMCRIR_RXLPITRCIS                         ETH_MMCRIR_RXLPITRCIS_Msk  /* MMC Receive LPI transition counter interrupt status */
+#define ETH_MMCRIR_RXLPIUSCIS_Pos                     (26U)
+#define ETH_MMCRIR_RXLPIUSCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPIUSCIS_Pos) /*!< 0x04000000 */
+#define ETH_MMCRIR_RXLPIUSCIS                         ETH_MMCRIR_RXLPIUSCIS_Msk  /* MMC Receive LPI microsecond counter interrupt status */
+#define ETH_MMCRIR_RXUCGPIS_Pos                       (17U)
+#define ETH_MMCRIR_RXUCGPIS_Msk                       (0x1UL << ETH_MMCRIR_RXUCGPIS_Pos) /*!< 0x00020000 */
+#define ETH_MMCRIR_RXUCGPIS                           ETH_MMCRIR_RXUCGPIS_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Status */
+#define ETH_MMCRIR_RXALGNERPIS_Pos                    (6U)
+#define ETH_MMCRIR_RXALGNERPIS_Msk                    (0x1UL << ETH_MMCRIR_RXALGNERPIS_Pos) /*!< 0x00000040 */
+#define ETH_MMCRIR_RXALGNERPIS                        ETH_MMCRIR_RXALGNERPIS_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Status */
+#define ETH_MMCRIR_RXCRCERPIS_Pos                     (5U)
+#define ETH_MMCRIR_RXCRCERPIS_Msk                     (0x1UL << ETH_MMCRIR_RXCRCERPIS_Pos) /*!< 0x00000020 */
+#define ETH_MMCRIR_RXCRCERPIS                         ETH_MMCRIR_RXCRCERPIS_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Status */
+
+/* Bit definition for Ethernet MMC Tx Interrupt Register */
+#define ETH_MMCTIR_TXLPITRCIS_Pos                     (27U)
+#define ETH_MMCTIR_TXLPITRCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPITRCIS_Pos) /*!< 0x08000000 */
+#define ETH_MMCTIR_TXLPITRCIS                         ETH_MMCTIR_TXLPITRCIS_Msk  /* MMC Transmit LPI transition counter interrupt status */
+#define ETH_MMCTIR_TXLPIUSCIS_Pos                     (26U)
+#define ETH_MMCTIR_TXLPIUSCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPIUSCIS_Pos) /*!< 0x04000000 */
+#define ETH_MMCTIR_TXLPIUSCIS                         ETH_MMCTIR_TXLPIUSCIS_Msk  /* MMC Transmit LPI microsecond counter interrupt status */
+#define ETH_MMCTIR_TXGPKTIS_Pos                       (21U)
+#define ETH_MMCTIR_TXGPKTIS_Msk                       (0x1UL << ETH_MMCTIR_TXGPKTIS_Pos) /*!< 0x00200000 */
+#define ETH_MMCTIR_TXGPKTIS                           ETH_MMCTIR_TXGPKTIS_Msk  /* MMC Transmit Good Packet Counter Interrupt Status */
+#define ETH_MMCTIR_TXMCOLGPIS_Pos                     (15U)
+#define ETH_MMCTIR_TXMCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXMCOLGPIS_Pos) /*!< 0x00008000 */
+#define ETH_MMCTIR_TXMCOLGPIS                         ETH_MMCTIR_TXMCOLGPIS_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Status */
+#define ETH_MMCTIR_TXSCOLGPIS_Pos                     (14U)
+#define ETH_MMCTIR_TXSCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXSCOLGPIS_Pos) /*!< 0x00004000 */
+#define ETH_MMCTIR_TXSCOLGPIS                         ETH_MMCTIR_TXSCOLGPIS_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Status */
+
+/* Bit definition for Ethernet MMC Rx interrupt Mask register */
+#define ETH_MMCRIMR_RXLPITRCIM_Pos                    (27U)
+#define ETH_MMCRIMR_RXLPITRCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPITRCIM_Pos) /*!< 0x08000000 */
+#define ETH_MMCRIMR_RXLPITRCIM                        ETH_MMCRIMR_RXLPITRCIM_Msk  /* MMC Receive LPI transition counter interrupt Mask */
+#define ETH_MMCRIMR_RXLPIUSCIM_Pos                    (26U)
+#define ETH_MMCRIMR_RXLPIUSCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPIUSCIM_Pos) /*!< 0x04000000 */
+#define ETH_MMCRIMR_RXLPIUSCIM                        ETH_MMCRIMR_RXLPIUSCIM_Msk  /* MMC Receive LPI microsecond counter interrupt Mask */
+#define ETH_MMCRIMR_RXUCGPIM_Pos                      (17U)
+#define ETH_MMCRIMR_RXUCGPIM_Msk                      (0x1UL << ETH_MMCRIMR_RXUCGPIM_Pos) /*!< 0x00020000 */
+#define ETH_MMCRIMR_RXUCGPIM                          ETH_MMCRIMR_RXUCGPIM_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Mask */
+#define ETH_MMCRIMR_RXALGNERPIM_Pos                   (6U)
+#define ETH_MMCRIMR_RXALGNERPIM_Msk                   (0x1UL << ETH_MMCRIMR_RXALGNERPIM_Pos) /*!< 0x00000040 */
+#define ETH_MMCRIMR_RXALGNERPIM                       ETH_MMCRIMR_RXALGNERPIM_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Mask */
+#define ETH_MMCRIMR_RXCRCERPIM_Pos                    (5U)
+#define ETH_MMCRIMR_RXCRCERPIM_Msk                    (0x1UL << ETH_MMCRIMR_RXCRCERPIM_Pos) /*!< 0x00000020 */
+#define ETH_MMCRIMR_RXCRCERPIM                        ETH_MMCRIMR_RXCRCERPIM_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Mask */
+
+/* Bit definition for Ethernet MMC Tx Interrupt Mask Register */
+#define ETH_MMCTIMR_TXLPITRCIM_Pos                    (27U)
+#define ETH_MMCTIMR_TXLPITRCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */
+#define ETH_MMCTIMR_TXLPITRCIM                        ETH_MMCTIMR_TXLPITRCIM_Msk  /* MMC Transmit LPI transition counter interrupt Mask*/
+#define ETH_MMCTIMR_TXLPIUSCIM_Pos                    (26U)
+#define ETH_MMCTIMR_TXLPIUSCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPIUSCIM_Pos) /*!< 0x04000000 */
+#define ETH_MMCTIMR_TXLPIUSCIM                        ETH_MMCTIMR_TXLPIUSCIM_Msk  /* MMC Transmit LPI microsecond counter interrupt Mask*/
+#define ETH_MMCTIMR_TXGPKTIM_Pos                      (21U)
+#define ETH_MMCTIMR_TXGPKTIM_Msk                      (0x1UL << ETH_MMCTIMR_TXGPKTIM_Pos) /*!< 0x00200000 */
+#define ETH_MMCTIMR_TXGPKTIM                          ETH_MMCTIMR_TXGPKTIM_Msk  /* MMC Transmit Good Packet Counter Interrupt Mask*/
+#define ETH_MMCTIMR_TXMCOLGPIM_Pos                    (15U)
+#define ETH_MMCTIMR_TXMCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXMCOLGPIM_Pos) /*!< 0x00008000 */
+#define ETH_MMCTIMR_TXMCOLGPIM                        ETH_MMCTIMR_TXMCOLGPIM_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask */
+#define ETH_MMCTIMR_TXSCOLGPIM_Pos                    (14U)
+#define ETH_MMCTIMR_TXSCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXSCOLGPIM_Pos) /*!< 0x00004000 */
+#define ETH_MMCTIMR_TXSCOLGPIM                        ETH_MMCTIMR_TXSCOLGPIM_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Mask */
+
+/* Bit definition for Ethernet MMC Tx Single Collision Good Packets Register */
+#define ETH_MMCTSCGPR_TXSNGLCOLG_Pos                  (0U)
+#define ETH_MMCTSCGPR_TXSNGLCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTSCGPR_TXSNGLCOLG_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTSCGPR_TXSNGLCOLG                      ETH_MMCTSCGPR_TXSNGLCOLG_msk /* Tx Single Collision Good Packets */
+
+/* Bit definition for Ethernet MMC Tx Multiple Collision Good Packets Register */
+#define ETH_MMCTMCGPR_TXMULTCOLG_Pos                  (0U)
+#define ETH_MMCTMCGPR_TXMULTCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTMCGPR_TXMULTCOLG_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTMCGPR_TXMULTCOLG                      ETH_MMCTMCGPR_TXMULTCOLG_msk /* Tx Multiple Collision Good Packets */
+
+/* Bit definition for Ethernet MMC Tx Packet Count Good Register */
+#define ETH_MMCTPCGR_TXPKTG_Pos                       (0U)
+#define ETH_MMCTPCGR_TXPKTG_msk                       (0xFFFFFFFFUL <<  ETH_MMCTPCGR_TXPKTG_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTPCGR_TXPKTG                           ETH_MMCTPCGR_TXPKTG_msk /* Tx Packet Count Good */
+
+/* Bit definition for Ethernet MMC Rx CRC Error Packets Register */
+#define ETH_MMCRCRCEPR_RXCRCERR_Pos                   (0U)
+#define ETH_MMCRCRCEPR_RXCRCERR_msk                   (0xFFFFFFFFUL <<  ETH_MMCRCRCEPR_RXCRCERR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRCRCEPR_RXCRCERR                       ETH_MMCRCRCEPR_RXCRCERR_msk /* Rx CRC Error Packets */
+
+/* Bit definition for Ethernet MMC Rx alignment error packets register */
+#define ETH_MMCRAEPR_RXALGNERR_Pos                    (0U)
+#define ETH_MMCRAEPR_RXALGNERR_msk                    (0xFFFFFFFFUL <<  ETH_MMCRAEPR_RXALGNERR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRAEPR_RXALGNERR                        ETH_MMCRAEPR_RXALGNERR_msk /* Rx Alignment Error Packets */
+
+/* Bit definition for Ethernet MMC Rx Unicast Packets Good Register */
+#define ETH_MMCRUPGR_RXUCASTG_Pos                     (0U)
+#define ETH_MMCRUPGR_RXUCASTG_msk                     (0xFFFFFFFFUL <<  ETH_MMCRUPGR_RXUCASTG_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRUPGR_RXUCASTG                         ETH_MMCRUPGR_RXUCASTG_msk /* Rx Unicast Packets Good */
+
+/* Bit definition for Ethernet MMC Tx LPI Microsecond Timer Register */
+#define ETH_MMCTLPIMSTR_TXLPIUSC_Pos                  (0U)
+#define ETH_MMCTLPIMSTR_TXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCTLPIMSTR_TXLPIUSC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTLPIMSTR_TXLPIUSC                      ETH_MMCTLPIMSTR_TXLPIUSC_msk /* Tx LPI Microseconds Counter */
+
+/* Bit definition for Ethernet MMC Tx LPI Transition Counter Register */
+#define ETH_MMCTLPITCR_TXLPITRC_Pos                   (0U)
+#define ETH_MMCTLPITCR_TXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCTLPITCR_TXLPITRC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTLPITCR_TXLPITRC                       ETH_MMCTLPITCR_TXLPITRC_msk /* Tx LPI Transition counter */
+
+/* Bit definition for Ethernet MMC Rx LPI Microsecond Counter Register */
+#define ETH_MMCRLPIMSTR_RXLPIUSC_Pos                  (0U)
+#define ETH_MMCRLPIMSTR_RXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCRLPIMSTR_RXLPIUSC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRLPIMSTR_RXLPIUSC                      ETH_MMCRLPIMSTR_RXLPIUSC_msk /* Rx LPI Microseconds Counter */
+
+/* Bit definition for Ethernet MMC Rx LPI Transition Counter Register */
+#define ETH_MMCRLPITCR_RXLPITRC_Pos                   (0U)
+#define ETH_MMCRLPITCR_RXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCRLPITCR_RXLPITRC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRLPITCR_RXLPITRC                       ETH_MMCRLPITCR_RXLPITRC_msk /* Rx LPI Transition counter */
+
+/* Bit definition for Ethernet MAC L3 L4 Control Register */
+#define ETH_MACL3L4CR_L4DPIM_Pos                      (21U)
+#define ETH_MACL3L4CR_L4DPIM_Msk                      (0x1UL << ETH_MACL3L4CR_L4DPIM_Pos) /*!< 0x00200000 */
+#define ETH_MACL3L4CR_L4DPIM                          ETH_MACL3L4CR_L4DPIM_Msk /* Layer 4 Destination Port Inverse Match Enable */
+#define ETH_MACL3L4CR_L4DPM_Pos                       (20U)
+#define ETH_MACL3L4CR_L4DPM_Msk                       (0x1UL << ETH_MACL3L4CR_L4DPM_Pos) /*!< 0x00100000 */
+#define ETH_MACL3L4CR_L4DPM                           ETH_MACL3L4CR_L4DPM_Msk  /* Layer 4 Destination Port Match Enable */
+#define ETH_MACL3L4CR_L4SPIM_Pos                      (19U)
+#define ETH_MACL3L4CR_L4SPIM_Msk                      (0x1UL << ETH_MACL3L4CR_L4SPIM_Pos) /*!< 0x00080000 */
+#define ETH_MACL3L4CR_L4SPIM                          ETH_MACL3L4CR_L4SPIM_Msk /* Layer 4 Source Port Inverse Match Enable */
+#define ETH_MACL3L4CR_L4SPM_Pos                       (18U)
+#define ETH_MACL3L4CR_L4SPM_Msk                       (0x1UL << ETH_MACL3L4CR_L4SPM_Pos) /*!< 0x00040000 */
+#define ETH_MACL3L4CR_L4SPM                           ETH_MACL3L4CR_L4SPM_Msk  /* Layer 4 Source Port Match Enable */
+#define ETH_MACL3L4CR_L4PEN_Pos                       (16U)
+#define ETH_MACL3L4CR_L4PEN_Msk                       (0x1UL << ETH_MACL3L4CR_L4PEN_Pos) /*!< 0x00010000 */
+#define ETH_MACL3L4CR_L4PEN                           ETH_MACL3L4CR_L4PEN_Msk  /* Layer 4 Protocol Enable */
+#define ETH_MACL3L4CR_L3HDBM_Pos                      (11U)
+#define ETH_MACL3L4CR_L3HDBM_Msk                      (0x1FUL << ETH_MACL3L4CR_L3HDBM_Pos) /*!< 0x0000F800 */
+#define ETH_MACL3L4CR_L3HDBM                          ETH_MACL3L4CR_L3HDBM_Msk /* Layer 3 IP DA Higher Bits Match */
+#define ETH_MACL3L4CR_L3HSBM_Pos                      (6U)
+#define ETH_MACL3L4CR_L3HSBM_Msk                      (0x1FUL << ETH_MACL3L4CR_L3HSBM_Pos) /*!< 0x000007C0 */
+#define ETH_MACL3L4CR_L3HSBM                          ETH_MACL3L4CR_L3HSBM_Msk /* Layer 3 IP SA Higher Bits Match */
+#define ETH_MACL3L4CR_L3DAIM_Pos                      (5U)
+#define ETH_MACL3L4CR_L3DAIM_Msk                      (0x1UL << ETH_MACL3L4CR_L3DAIM_Pos) /*!< 0x00000020 */
+#define ETH_MACL3L4CR_L3DAIM                          ETH_MACL3L4CR_L3DAIM_Msk /* Layer 3 IP DA Inverse Match Enable */
+#define ETH_MACL3L4CR_L3DAM_Pos                       (4U)
+#define ETH_MACL3L4CR_L3DAM_Msk                       (0x1UL << ETH_MACL3L4CR_L3DAM_Pos) /*!< 0x00000010 */
+#define ETH_MACL3L4CR_L3DAM                           ETH_MACL3L4CR_L3DAM_Msk  /* Layer 3 IP DA Match Enable */
+#define ETH_MACL3L4CR_L3SAIM_Pos                      (3U)
+#define ETH_MACL3L4CR_L3SAIM_Msk                      (0x1UL << ETH_MACL3L4CR_L3SAIM_Pos) /*!< 0x00000008 */
+#define ETH_MACL3L4CR_L3SAIM                          ETH_MACL3L4CR_L3SAIM_Msk /* Layer 3 IP SA Inverse Match Enable */
+#define ETH_MACL3L4CR_L3SAM_Pos                       (2U)
+#define ETH_MACL3L4CR_L3SAM_Msk                       (0x1UL << ETH_MACL3L4CR_L3SAM_Pos) /*!< 0x00000004 */
+#define ETH_MACL3L4CR_L3SAM                           ETH_MACL3L4CR_L3SAM_Msk  /* Layer 3 IP SA Match Enable*/
+#define ETH_MACL3L4CR_L3PEN_Pos                       (0U)
+#define ETH_MACL3L4CR_L3PEN_Msk                       (0x1UL << ETH_MACL3L4CR_L3PEN_Pos) /*!< 0x00000001 */
+#define ETH_MACL3L4CR_L3PEN                           ETH_MACL3L4CR_L3PEN_Msk  /* Layer 3 Protocol Enable */
+
+/* Bit definition for Ethernet MAC L4 Address Register */
+#define ETH_MACL4AR_L4DP_Pos                          (16U)
+#define ETH_MACL4AR_L4DP_Msk                          (0xFFFFUL << ETH_MACL4AR_L4DP_Pos) /*!< 0xFFFF0000 */
+#define ETH_MACL4AR_L4DP                              ETH_MACL4AR_L4DP_Msk     /* Layer 4 Destination Port Number Field */
+#define ETH_MACL4AR_L4SP_Pos                          (0U)
+#define ETH_MACL4AR_L4SP_Msk                          (0xFFFFUL << ETH_MACL4AR_L4SP_Pos) /*!< 0x0000FFFF */
+#define ETH_MACL4AR_L4SP                              ETH_MACL4AR_L4SP_Msk     /* Layer 4 Source Port Number Field */
+
+/* Bit definition for Ethernet MAC L3 Address0 Register */
+#define ETH_MACL3A0R_L3A0_Pos                         (0U)
+#define ETH_MACL3A0R_L3A0_Msk                         (0xFFFFFFFFUL << ETH_MACL3A0R_L3A0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A0R_L3A0                             ETH_MACL3A0R_L3A0_Msk    /* Layer 3 Address 0 Field */
+
+/* Bit definition for Ethernet MAC L4 Address1 Register */
+#define ETH_MACL3A1R_L3A1_Pos                         (0U)
+#define ETH_MACL3A1R_L3A1_Msk                         (0xFFFFFFFFUL << ETH_MACL3A1R_L3A1_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A1R_L3A1                             ETH_MACL3A1R_L3A1_Msk    /* Layer 3 Address 1 Field */
+
+/* Bit definition for Ethernet MAC L4 Address2 Register */
+#define ETH_MACL3A2R_L3A2_Pos                         (0U)
+#define ETH_MACL3A2R_L3A2_Msk                         (0xFFFFFFFFUL << ETH_MACL3A2R_L3A2_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A2R_L3A2                             ETH_MACL3A2R_L3A2_Msk    /* Layer 3 Address 2 Field */
+
+/* Bit definition for Ethernet MAC L4 Address3 Register */
+#define ETH_MACL3A3R_L3A3_Pos                         (0U)
+#define ETH_MACL3A3R_L3A3_Msk                         (0xFFFFFFFFUL << ETH_MACL3A3R_L3A3_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A3R_L3A3                             ETH_MACL3A3R_L3A3_Msk    /* Layer 3 Address 3 Field */
+
+/* Bit definition for Ethernet MAC Timestamp Control Register */
+#define ETH_MACTSCR_TXTSSTSM_Pos                      (24U)
+#define ETH_MACTSCR_TXTSSTSM_Msk                      (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */
+#define ETH_MACTSCR_TXTSSTSM                          ETH_MACTSCR_TXTSSTSM_Msk  /* Transmit Timestamp Status Mode */
+#define ETH_MACTSCR_CSC_Pos                           (19U)
+#define ETH_MACTSCR_CSC_Msk                           (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */
+#define ETH_MACTSCR_CSC                               ETH_MACTSCR_CSC_Msk  /* Enable checksum correction during OST for PTP over UDP/IPv4 packets */
+#define ETH_MACTSCR_TSENMACADDR_Pos                   (18U)
+#define ETH_MACTSCR_TSENMACADDR_Msk                   (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */
+#define ETH_MACTSCR_TSENMACADDR                       ETH_MACTSCR_TSENMACADDR_Msk  /* Enable MAC Address for PTP Packet Filtering */
+#define ETH_MACTSCR_SNAPTYPSEL_Pos                    (16U)
+#define ETH_MACTSCR_SNAPTYPSEL_Msk                    (0x3UL << ETH_MACTSCR_SNAPTYPSEL_Pos) /*!< 0x00030000 */
+#define ETH_MACTSCR_SNAPTYPSEL                        ETH_MACTSCR_SNAPTYPSEL_Msk  /* Select PTP packets for Taking Snapshots */
+#define ETH_MACTSCR_TSMSTRENA_Pos                     (15U)
+#define ETH_MACTSCR_TSMSTRENA_Msk                     (0x1UL << ETH_MACTSCR_TSMSTRENA_Pos) /*!< 0x00008000 */
+#define ETH_MACTSCR_TSMSTRENA                         ETH_MACTSCR_TSMSTRENA_Msk  /* Enable Snapshot for Messages Relevant to Master */
+#define ETH_MACTSCR_TSEVNTENA_Pos                     (14U)
+#define ETH_MACTSCR_TSEVNTENA_Msk                     (0x1UL << ETH_MACTSCR_TSEVNTENA_Pos) /*!< 0x00004000 */
+#define ETH_MACTSCR_TSEVNTENA                         ETH_MACTSCR_TSEVNTENA_Msk  /* Enable Timestamp Snapshot for Event Messages */
+#define ETH_MACTSCR_TSIPV4ENA_Pos                     (13U)
+#define ETH_MACTSCR_TSIPV4ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV4ENA_Pos) /*!< 0x00002000 */
+#define ETH_MACTSCR_TSIPV4ENA                         ETH_MACTSCR_TSIPV4ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv4-UDP */
+#define ETH_MACTSCR_TSIPV6ENA_Pos                     (12U)
+#define ETH_MACTSCR_TSIPV6ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV6ENA_Pos) /*!< 0x00001000 */
+#define ETH_MACTSCR_TSIPV6ENA                         ETH_MACTSCR_TSIPV6ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv6-UDP */
+#define ETH_MACTSCR_TSIPENA_Pos                       (11U)
+#define ETH_MACTSCR_TSIPENA_Msk                       (0x1UL << ETH_MACTSCR_TSIPENA_Pos) /*!< 0x00000800 */
+#define ETH_MACTSCR_TSIPENA                           ETH_MACTSCR_TSIPENA_Msk  /* Enable Processing of PTP over Ethernet Packets */
+#define ETH_MACTSCR_TSVER2ENA_Pos                     (10U)
+#define ETH_MACTSCR_TSVER2ENA_Msk                     (0x1UL << ETH_MACTSCR_TSVER2ENA_Pos) /*!< 0x00000400 */
+#define ETH_MACTSCR_TSVER2ENA                         ETH_MACTSCR_TSVER2ENA_Msk  /* Enable PTP Packet Processing for Version 2 Format */
+#define ETH_MACTSCR_TSCTRLSSR_Pos                     (9U)
+#define ETH_MACTSCR_TSCTRLSSR_Msk                     (0x1UL << ETH_MACTSCR_TSCTRLSSR_Pos) /*!< 0x00000200 */
+#define ETH_MACTSCR_TSCTRLSSR                         ETH_MACTSCR_TSCTRLSSR_Msk  /* Timestamp Digital or Binary Rollover Control */
+#define ETH_MACTSCR_TSENALL_Pos                       (8U)
+#define ETH_MACTSCR_TSENALL_Msk                       (0x1UL << ETH_MACTSCR_TSENALL_Pos) /*!< 0x00000100 */
+#define ETH_MACTSCR_TSENALL                           ETH_MACTSCR_TSENALL_Msk  /* Enable Timestamp for All Packets */
+#define ETH_MACTSCR_TSADDREG_Pos                      (5U)
+#define ETH_MACTSCR_TSADDREG_Msk                      (0x1UL << ETH_MACTSCR_TSADDREG_Pos) /*!< 0x00000020 */
+#define ETH_MACTSCR_TSADDREG                          ETH_MACTSCR_TSADDREG_Msk  /* Update Addend Register */
+#define ETH_MACTSCR_TSUPDT_Pos                        (3U)
+#define ETH_MACTSCR_TSUPDT_Msk                        (0x1UL << ETH_MACTSCR_TSUPDT_Pos) /*!< 0x00000008 */
+#define ETH_MACTSCR_TSUPDT                            ETH_MACTSCR_TSUPDT_Msk  /* Update Timestamp */
+#define ETH_MACTSCR_TSINIT_Pos                        (2U)
+#define ETH_MACTSCR_TSINIT_Msk                        (0x1UL << ETH_MACTSCR_TSINIT_Pos) /*!< 0x00000004 */
+#define ETH_MACTSCR_TSINIT                             ETH_MACTSCR_TSINIT_Msk  /* Initialize Timestamp */
+#define ETH_MACTSCR_TSCFUPDT_Pos                      (1U)
+#define ETH_MACTSCR_TSCFUPDT_Msk                      (0x1UL << ETH_MACTSCR_TSCFUPDT_Pos) /*!< 0x00000002 */
+#define ETH_MACTSCR_TSCFUPDT                          ETH_MACTSCR_TSCFUPDT_Msk  /* Fine or Coarse Timestamp Update*/
+#define ETH_MACTSCR_TSENA_Pos                         (0U)
+#define ETH_MACTSCR_TSENA_Msk                         (0x1UL << ETH_MACTSCR_TSENA_Pos) /*!< 0x00000001 */
+#define ETH_MACTSCR_TSENA                             ETH_MACTSCR_TSENA_Msk  /* Enable Timestamp */
+
+/* Bit definition for Ethernet MAC Sub-second Increment Register */
+#define ETH_MACMACSSIR_SSINC_Pos                      (16U)
+#define ETH_MACMACSSIR_SSINC_Msk                      (0xFFUL << ETH_MACMACSSIR_SSINC_Pos) /*!< 0x0000FF00 */
+#define ETH_MACMACSSIR_SSINC                          ETH_MACMACSSIR_SSINC_Msk  /* Sub-second Increment Value */
+#define ETH_MACMACSSIR_SNSINC_Pos                     (8U)
+#define ETH_MACMACSSIR_SNSINC_Msk                     (0xFFUL << ETH_MACMACSSIR_SNSINC_Pos) /*!< 0x000000FF */
+#define ETH_MACMACSSIR_SNSINC                         ETH_MACMACSSIR_SNSINC_Msk  /* Sub-nanosecond Increment Value */
+
+/* Bit definition for Ethernet MAC System Time Seconds Register */
+#define ETH_MACSTSR_TSS_Pos                           (0U)
+#define ETH_MACSTSR_TSS_Msk                           (0xFFFFFFFFUL << ETH_MACSTSR_TSS_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACSTSR_TSS                               ETH_MACSTSR_TSS_Msk  /* Timestamp Second */
+
+/* Bit definition for Ethernet MAC System Time Nanoseconds Register */
+#define ETH_MACSTNR_TSSS_Pos                          (0U)
+#define ETH_MACSTNR_TSSS_Msk                          (0x7FFFFFFFUL << ETH_MACSTNR_TSSS_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACSTNR_TSSS                              ETH_MACSTNR_TSSS_Msk  /* Timestamp Sub-seconds */
+
+/* Bit definition for Ethernet MAC System Time Seconds Update Register */
+#define ETH_MACSTSUR_TSS_Pos                          (0U)
+#define ETH_MACSTSUR_TSS_Msk                          (0xFFFFFFFFUL << ETH_MACSTSUR_TSS_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACSTSUR_TSS                              ETH_MACSTSUR_TSS_Msk  /* Timestamp Seconds */
+
+/* Bit definition for Ethernet MAC System Time Nanoseconds Update Register */
+#define ETH_MACSTNUR_ADDSUB_Pos                       (31U)
+#define ETH_MACSTNUR_ADDSUB_Msk                       (0x1UL << ETH_MACSTNUR_ADDSUB_Pos) /*!< 0x80000000 */
+#define ETH_MACSTNUR_ADDSUB                           ETH_MACSTNUR_ADDSUB_Msk  /* Add or Subtract Time */
+#define ETH_MACSTNUR_TSSS_Pos                         (0U)
+#define ETH_MACSTNUR_TSSS_Msk                         (0x7FFFFFFFUL << ETH_MACSTNUR_TSSS_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACSTNUR_TSSS                             ETH_MACSTNUR_TSSS_Msk  /* Timestamp Sub-seconds */
+
+/* Bit definition for Ethernet MAC Timestamp Addend Register */
+#define ETH_MACTSAR_TSAR_Pos                          (0U)
+#define ETH_MACTSAR_TSAR_Msk                          (0xFFFFFFFFUL << ETH_MACTSAR_TSAR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSAR_TSAR                              ETH_MACTSAR_TSAR_Msk  /* Timestamp Addend Register */
+
+/* Bit definition for Ethernet MAC Timestamp Status Register */
+#define ETH_MACTSSR_ATSNS_Pos                         (25U)
+#define ETH_MACTSSR_ATSNS_Msk                         (0x1FUL << ETH_MACTSSR_ATSNS_Pos) /*!< 0x3E000000 */
+#define ETH_MACTSSR_ATSNS                             ETH_MACTSSR_ATSNS_Msk  /* Number of Auxiliary Timestamp Snapshots */
+#define ETH_MACTSSR_ATSSTM_Pos                        (24U)
+#define ETH_MACTSSR_ATSSTM_Msk                        (0x1UL << ETH_MACTSSR_ATSSTM_Pos) /*!< 0x01000000 */
+#define ETH_MACTSSR_ATSSTM                            ETH_MACTSSR_ATSSTM_Msk  /* Auxiliary Timestamp Snapshot Trigger Missed */
+#define ETH_MACTSSR_ATSSTN_Pos                        (16U)
+#define ETH_MACTSSR_ATSSTN_Msk                        (0xFUL << ETH_MACTSSR_ATSSTN_Pos) /*!< 0x000F0000 */
+#define ETH_MACTSSR_ATSSTN                            ETH_MACTSSR_ATSSTN_Msk  /* Auxiliary Timestamp Snapshot Trigger Identifier */
+#define ETH_MACTSSR_TXTSSIS_Pos                       (15U)
+#define ETH_MACTSSR_TXTSSIS_Msk                       (0x1UL << ETH_MACTSSR_TXTSSIS_Pos) /*!< 0x00008000 */
+#define ETH_MACTSSR_TXTSSIS                           ETH_MACTSSR_TXTSSIS_Msk  /* Tx Timestamp Status Interrupt Status */
+#define ETH_MACTSSR_TSTRGTERR0_Pos                    (3U)
+#define ETH_MACTSSR_TSTRGTERR0_Msk                    (0x1UL << ETH_MACTSSR_TSTRGTERR0_Pos) /*!< 0x00000008 */
+#define ETH_MACTSSR_TSTRGTERR0                        ETH_MACTSSR_TSTRGTERR0_Msk  /* Timestamp Target Time Error */
+#define ETH_MACTSSR_AUXTSTRIG_Pos                     (2U)
+#define ETH_MACTSSR_AUXTSTRIG_Msk                     (0x1UL << ETH_MACTSSR_AUXTSTRIG_Pos) /*!< 0x00000004 */
+#define ETH_MACTSSR_AUXTSTRIG                         ETH_MACTSSR_AUXTSTRIG_Msk  /* Auxiliary Timestamp Trigger Snapshot*/
+#define ETH_MACTSSR_TSTARGT0_Pos                      (1U)
+#define ETH_MACTSSR_TSTARGT0_Msk                      (0x1UL << ETH_MACTSSR_TSTARGT0_Pos) /*!< 0x00000002 */
+#define ETH_MACTSSR_TSTARGT0                          ETH_MACTSSR_TSTARGT0_Msk  /* Timestamp Target Time Reached */
+#define ETH_MACTSSR_TSSOVF_Pos                        (0U)
+#define ETH_MACTSSR_TSSOVF_Msk                        (0x1UL << ETH_MACTSSR_TSSOVF_Pos) /*!< 0x00000001 */
+#define ETH_MACTSSR_TSSOVF                            ETH_MACTSSR_TSSOVF_Msk  /* Timestamp Seconds Overflow */
+
+/* Bit definition for Ethernet MAC Tx Timestamp Status Nanoseconds Register */
+#define ETH_MACTTSSNR_TXTSSMIS_Pos                    (31U)
+#define ETH_MACTTSSNR_TXTSSMIS_Msk                    (0x1UL << ETH_MACTTSSNR_TXTSSMIS_Pos) /*!< 0x80000000 */
+#define ETH_MACTTSSNR_TXTSSMIS                        ETH_MACTTSSNR_TXTSSMIS_Msk  /* Transmit Timestamp Status Missed */
+#define ETH_MACTTSSNR_TXTSSLO_Pos                     (0U)
+#define ETH_MACTTSSNR_TXTSSLO_Msk                     (0x7FFFFFFFUL << ETH_MACTTSSNR_TXTSSLO_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACTTSSNR_TXTSSLO                         ETH_MACTTSSNR_TXTSSLO_Msk  /* Transmit Timestamp Status Low */
+
+/* Bit definition for Ethernet MAC Tx Timestamp Status Seconds Register */
+#define ETH_MACTTSSSR_TXTSSHI_Pos                     (0U)
+#define ETH_MACTTSSSR_TXTSSHI_Msk                     (0xFFFFFFFFUL << ETH_MACTTSSSR_TXTSSHI_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTTSSSR_TXTSSHI                         ETH_MACTTSSSR_TXTSSHI_Msk  /* Transmit Timestamp Status High */
+
+/* Bit definition for Ethernet MAC Auxiliary Control Register*/
+#define ETH_MACACR_ATSEN3_Pos                         (7U)
+#define ETH_MACACR_ATSEN3_Msk                         (0x1UL << ETH_MACACR_ATSEN3_Pos) /*!< 0x00000080 */
+#define ETH_MACACR_ATSEN3                             ETH_MACACR_ATSEN3_Msk  /* Auxiliary Snapshot 3 Enable */
+#define ETH_MACACR_ATSEN2_Pos                         (6U)
+#define ETH_MACACR_ATSEN2_Msk                         (0x1UL << ETH_MACACR_ATSEN2_Pos) /*!< 0x00000040 */
+#define ETH_MACACR_ATSEN2                             ETH_MACACR_ATSEN2_Msk  /* Auxiliary Snapshot 2 Enable */
+#define ETH_MACACR_ATSEN1_Pos                         (5U)
+#define ETH_MACACR_ATSEN1_Msk                         (0x1UL << ETH_MACACR_ATSEN1_Pos) /*!< 0x00000020 */
+#define ETH_MACACR_ATSEN1                             ETH_MACACR_ATSEN1_Msk  /* Auxiliary Snapshot 1 Enable */
+#define ETH_MACACR_ATSEN0_Pos                         (4U)
+#define ETH_MACACR_ATSEN0_Msk                         (0x1UL << ETH_MACACR_ATSEN0_Pos) /*!< 0x00000010 */
+#define ETH_MACACR_ATSEN0                             ETH_MACACR_ATSEN0_Msk  /* Auxiliary Snapshot 0 Enable */
+#define ETH_MACACR_ATSFC_Pos                          (0U)
+#define ETH_MACACR_ATSFC_Msk                          (0x1UL << ETH_MACACR_ATSFC_Pos) /*!< 0x00000001 */
+#define ETH_MACACR_ATSFC                              ETH_MACACR_ATSFC_Msk  /* Auxiliary Snapshot FIFO Clear */
+
+/* Bit definition for Ethernet MAC Auxiliary Timestamp Nanoseconds Register */
+#define ETH_MACATSNR_AUXTSLO_Pos                      (0U)
+#define ETH_MACATSNR_AUXTSLO_Msk                      (0x7FFFFFFFUL << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACATSNR_AUXTSLO                          ETH_MACATSNR_AUXTSLO_Msk  /* Auxiliary Timestamp */
+
+/* Bit definition for Ethernet MAC Auxiliary Timestamp Seconds Register */
+#define ETH_MACATSSR_AUXTSHI_Pos                      (0U)
+#define ETH_MACATSSR_AUXTSHI_Msk                      (0xFFFFFFFFUL << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACATSSR_AUXTSHI                          ETH_MACATSSR_AUXTSHI_Msk  /* Auxiliary Timestamp */
+
+/* Bit definition for Ethernet MAC Timestamp Ingress Asymmetric Correction Register */
+#define ETH_MACTSIACR_OSTIAC_Pos                      (0U)
+#define ETH_MACTSIACR_OSTIAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSIACR_OSTIAC                          ETH_MACTSIACR_OSTIAC_Msk  /* One-Step Timestamp Ingress Asymmetry Correction */
+
+/* Bit definition for Ethernet MAC Timestamp Egress Asymmetric Correction Register */
+#define ETH_MACTSEACR_OSTEAC_Pos                      (0U)
+#define ETH_MACTSEACR_OSTEAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSEACR_OSTEAC                          ETH_MACTSEACR_OSTEAC_Msk  /* One-Step Timestamp Egress Asymmetry Correction */
+
+/* Bit definition for Ethernet MAC Timestamp Ingress Correction Nanosecond Register */
+#define ETH_MACTSICNR_TSIC_Pos                        (0U)
+#define ETH_MACTSICNR_TSIC_Msk                        (0xFFFFFFFFUL << ETH_MACTSICNR_TSIC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSICNR_TSIC                            ETH_MACTSICNR_TSIC_Msk  /* Timestamp Ingress Correction */
+
+/* Bit definition for Ethernet MAC Timestamp Egress correction Nanosecond Register */
+#define ETH_MACTSECNR_TSEC_Pos                        (0U)
+#define ETH_MACTSECNR_TSEC_Msk                        (0xFFFFFFFFUL << ETH_MACTSECNR_TSEC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSECNR_TSEC                            ETH_MACTSECNR_TSEC_Msk  /* Timestamp Egress Correction */
+
+/* Bit definition for Ethernet MAC PPS Control Register */
+#define ETH_MACPPSCR_TRGTMODSEL0_Pos                  (5U)
+#define ETH_MACPPSCR_TRGTMODSEL0_Msk                  (0x3UL << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000060 */
+#define ETH_MACPPSCR_TRGTMODSEL0                      ETH_MACPPSCR_TRGTMODSEL0_Msk  /* Target Time Register Mode for PPS Output */
+#define ETH_MACPPSCR_PPSEN0_Pos                       (4U)
+#define ETH_MACPPSCR_PPSEN0_Msk                       (0x1UL << ETH_MACPPSCR_PPSEN0_Pos) /*!< 0x00000010 */
+#define ETH_MACPPSCR_PPSEN0                           ETH_MACPPSCR_PPSEN0_Msk  /* Flexible PPS Output Mode Enable */
+#define ETH_MACPPSCR_PPSCTRL_Pos                      (0U)
+#define ETH_MACPPSCR_PPSCTRL_Msk                      (0xFUL << ETH_MACPPSCR_PPSCTRL_Pos) /*!< 0x0000000F */
+#define ETH_MACPPSCR_PPSCTRL                          ETH_MACPPSCR_PPSCTRL_Msk  /* PPS Output Frequency Control */
+
+/* Bit definition for Ethernet MAC PPS Target Time Seconds Register */
+#define ETH_MACPPSTTSR_TSTRH0_Pos                     (0U)
+#define ETH_MACPPSTTSR_TSTRH0_Msk                     (0xFFFFFFFFUL << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACPPSTTSR_TSTRH0                         ETH_MACPPSTTSR_TSTRH0_Msk  /* PPS Target Time Seconds Register */
+
+/* Bit definition for Ethernet MAC PPS Target Time Nanoseconds Register */
+#define ETH_MACPPSTTNR_TRGTBUSY0_Pos                  (31U)
+#define ETH_MACPPSTTNR_TRGTBUSY0_Msk                  (0x1UL << ETH_MACPPSTTNR_TRGTBUSY0_Pos) /*!< 0x80000000 */
+#define ETH_MACPPSTTNR_TRGTBUSY0                      ETH_MACPPSTTNR_TRGTBUSY0_Msk  /* PPS Target Time Register Busy */
+#define ETH_MACPPSTTNR_TTSL0_Pos                      (0U)
+#define ETH_MACPPSTTNR_TTSL0_Msk                      (0x7FFFFFFFUL << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACPPSTTNR_TTSL0                          ETH_MACPPSTTNR_TTSL0_Msk  /* Target Time Low for PPS Register */
+
+/* Bit definition for Ethernet MAC PPS Interval Register */
+#define ETH_MACPPSIR_PPSINT0_Pos                      (0U)
+#define ETH_MACPPSIR_PPSINT0_Msk                      (0xFFFFFFFFUL << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACPPSIR_PPSINT0                          ETH_MACPPSIR_PPSINT0_Msk  /* PPS Output Signal Interval */
+
+/* Bit definition for Ethernet MAC PPS Width Register */
+#define ETH_MACPPSWR_PPSWIDTH0_Pos                    (0U)
+#define ETH_MACPPSWR_PPSWIDTH0_Msk                    (0xFFFFFFFFUL << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACPPSWR_PPSWIDTH0                        ETH_MACPPSWR_PPSWIDTH0_Msk  /* PPS Output Signal Width */
+
+/* Bit definition for Ethernet MAC PTP Offload Control Register */
+#define ETH_MACPOCR_DN_Pos                            (8U)
+#define ETH_MACPOCR_DN_Msk                            (0xFFUL << ETH_MACPOCR_DN_Pos) /*!< 0x0000FF00 */
+#define ETH_MACPOCR_DN                                ETH_MACPOCR_DN_Msk  /* Domain Number */
+#define ETH_MACPOCR_DRRDIS_Pos                        (6U)
+#define ETH_MACPOCR_DRRDIS_Msk                        (0x1UL << ETH_MACPOCR_DRRDIS_Pos) /*!< 0x00000040 */
+#define ETH_MACPOCR_DRRDIS                            ETH_MACPOCR_DRRDIS_Msk  /* Disable PTO Delay Request/Response response generation */
+#define ETH_MACPOCR_APDREQTRIG_Pos                    (5U)
+#define ETH_MACPOCR_APDREQTRIG_Msk                    (0x1UL << ETH_MACPOCR_APDREQTRIG_Pos) /*!< 0x00000020 */
+#define ETH_MACPOCR_APDREQTRIG                        ETH_MACPOCR_APDREQTRIG_Msk  /* Automatic PTP Pdelay_Req message Trigger */
+#define ETH_MACPOCR_ASYNCTRIG_Pos                     (4U)
+#define ETH_MACPOCR_ASYNCTRIG_Msk                     (0x1UL << ETH_MACPOCR_ASYNCTRIG_Pos) /*!< 0x00000010 */
+#define ETH_MACPOCR_ASYNCTRIG                         ETH_MACPOCR_ASYNCTRIG_Msk  /* Automatic PTP SYNC message Trigger */
+#define ETH_MACPOCR_APDREQEN_Pos                      (2U)
+#define ETH_MACPOCR_APDREQEN_Msk                      (0x1UL << ETH_MACPOCR_APDREQEN_Pos) /*!< 0x00000004 */
+#define ETH_MACPOCR_APDREQEN                          ETH_MACPOCR_APDREQEN_Msk  /* Automatic PTP Pdelay_Req message Enable */
+#define ETH_MACPOCR_ASYNCEN_Pos                       (1U)
+#define ETH_MACPOCR_ASYNCEN_Msk                       (0x1UL << ETH_MACPOCR_ASYNCEN_Pos) /*!< 0x00000002 */
+#define ETH_MACPOCR_ASYNCEN                           ETH_MACPOCR_ASYNCEN_Msk  /* Automatic PTP SYNC message Enable */
+#define ETH_MACPOCR_PTOEN_Pos                         (0U)
+#define ETH_MACPOCR_PTOEN_Msk                         (0x1UL << ETH_MACPOCR_PTOEN_Pos) /*!< 0x00000001 */
+#define ETH_MACPOCR_PTOEN                             ETH_MACPOCR_PTOEN_Msk  /* PTP Offload Enable */
+
+/* Bit definition for Ethernet MAC PTP Source Port Identity 0 Register */
+#define ETH_MACSPI0R_SPI0_Pos                         (0U)
+#define ETH_MACSPI0R_SPI0_Msk                         (0xFFFFFFFFUL << ETH_MACSPI0R_SPI0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACSPI0R_SPI0                             ETH_MACSPI0R_SPI0_Msk  /* Source Port Identity 0 */
+
+/* Bit definition for Ethernet MAC PTP Source Port Identity 1 Register */
+#define ETH_MACSPI1R_SPI1_Pos                         (0U)
+#define ETH_MACSPI1R_SPI1_Msk                         (0xFFFFFFFFUL << ETH_MACSPI1R_SPI1_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACSPI1R_SPI1                             ETH_MACSPI1R_SPI1_Msk  /* Source Port Identity 1 */
+
+/* Bit definition for Ethernet MAC PTP Source Port Identity 2 Register */
+#define ETH_MACSPI2R_SPI2_Pos                         (0U)
+#define ETH_MACSPI2R_SPI2_Msk                         (0xFFFFUL << ETH_MACSPI2R_SPI2_Pos) /*!< 0x0000FFFF */
+#define ETH_MACSPI2R_SPI2                             ETH_MACSPI2R_SPI2_Msk  /* Source Port Identity 2 */
+
+/* Bit definition for Ethernet MAC Log Message Interval Register */
+#define ETH_MACLMIR_LMPDRI_Pos                        (24U)
+#define ETH_MACLMIR_LMPDRI_Msk                        (0xFFUL << ETH_MACLMIR_LMPDRI_Pos) /*!< 0xFF000000 */
+#define ETH_MACLMIR_LMPDRI                             ETH_MACLMIR_LMPDRI_Msk  /* Log Min Pdelay_Req Interval */
+#define ETH_MACLMIR_DRSYNCR_Pos                       (8U)
+#define ETH_MACLMIR_DRSYNCR_Msk                       (0x7UL << ETH_MACLMIR_DRSYNCR_Pos) /*!< 0x00000700 */
+#define ETH_MACLMIR_DRSYNCR                           ETH_MACLMIR_DRSYNCR_Msk  /* Delay_Req to SYNC Ratio */
+#define ETH_MACLMIR_LSI_Pos                           (0U)
+#define ETH_MACLMIR_LSI_Msk                           (0xFFUL << ETH_MACLMIR_LSI_Pos) /*!< 0x000000FF */
+#define ETH_MACLMIR_LSI                               ETH_MACLMIR_LSI_Msk  /* Log Sync Interval */
+
+/* Bit definition for Ethernet MTL Operation Mode Register */
+#define ETH_MTLOMR_CNTCLR_Pos                         (9U)
+#define ETH_MTLOMR_CNTCLR_Msk                         (0x1UL << ETH_MTLOMR_CNTCLR_Pos) /*!< 0x00000200 */
+#define ETH_MTLOMR_CNTCLR                             ETH_MTLOMR_CNTCLR_Msk    /* Counters Reset */
+#define ETH_MTLOMR_CNTPRST_Pos                        (8U)
+#define ETH_MTLOMR_CNTPRST_Msk                        (0x1UL << ETH_MTLOMR_CNTPRST_Pos) /*!< 0x00000100 */
+#define ETH_MTLOMR_CNTPRST                            ETH_MTLOMR_CNTPRST_Msk   /* Counters Preset */
+#define ETH_MTLOMR_DTXSTS_Pos                         (1U)
+#define ETH_MTLOMR_DTXSTS_Msk                         (0x1UL << ETH_MTLOMR_DTXSTS_Pos) /*!< 0x00000002 */
+#define ETH_MTLOMR_DTXSTS                             ETH_MTLOMR_DTXSTS_Msk  /* Drop Transmit Status */
+
+/* Bit definition for Ethernet MTL Interrupt Status Register */
+#define ETH_MTLISR_MACIS_Pos                          (16U)
+#define ETH_MTLISR_MACIS_Msk                          (0x1UL << ETH_MTLISR_MACIS_Pos) /*!< 0x00010000 */
+#define ETH_MTLISR_MACIS                              ETH_MTLISR_MACIS_Msk     /* MAC Interrupt Status */
+#define ETH_MTLISR_QIS_Pos                            (0U)
+#define ETH_MTLISR_QIS_Msk                            (0x1UL << ETH_MTLISR_QIS_Pos) /*!< 0x00000001 */
+#define ETH_MTLISR_QIS                                ETH_MTLISR_QIS_Msk       /* Queue Interrupt status */
+
+/* Bit definition for Ethernet MTL Tx Queue Operation Mode Register */
+#define ETH_MTLTQOMR_TTC_Pos                          (4U)
+#define ETH_MTLTQOMR_TTC_Msk                          (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */
+#define ETH_MTLTQOMR_TTC                              ETH_MTLTQOMR_TTC_Msk     /* Transmit Threshold Control */
+#define ETH_MTLTQOMR_TTC_32BITS                       ((uint32_t)0x00000000)   /* 32 bits Threshold */
+#define ETH_MTLTQOMR_TTC_64BITS                       ((uint32_t)0x00000010)   /* 64  bits Threshold */
+#define ETH_MTLTQOMR_TTC_96BITS                       ((uint32_t)0x00000020)   /* 96 bits Threshold */
+#define ETH_MTLTQOMR_TTC_128BITS                      ((uint32_t)0x00000030)   /* 128 bits Threshold */
+#define ETH_MTLTQOMR_TTC_192BITS                      ((uint32_t)0x00000040)   /* 192 bits Threshold */
+#define ETH_MTLTQOMR_TTC_256BITS                      ((uint32_t)0x00000050)   /* 256 bits Threshold */
+#define ETH_MTLTQOMR_TTC_384BITS                      ((uint32_t)0x00000060)   /* 384 bits Threshold */
+#define ETH_MTLTQOMR_TTC_512BITS                      ((uint32_t)0x00000070)   /* 512 bits Threshold */
+#define ETH_MTLTQOMR_TSF_Pos                          (1U)
+#define ETH_MTLTQOMR_TSF_Msk                          (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */
+#define ETH_MTLTQOMR_TSF                              ETH_MTLTQOMR_TSF_Msk     /* Transmit Store and Forward */
+#define ETH_MTLTQOMR_FTQ_Pos                          (0U)
+#define ETH_MTLTQOMR_FTQ_Msk                          (0x1UL << ETH_MTLTQOMR_FTQ_Pos) /*!< 0x00000001 */
+#define ETH_MTLTQOMR_FTQ                              ETH_MTLTQOMR_FTQ_Msk     /* Flush Transmit Queue */
+
+/* Bit definition for Ethernet MTL Tx Queue Underflow Register */
+#define ETH_MTLTQUR_UFCNTOVF_Pos                      (11U)
+#define ETH_MTLTQUR_UFCNTOVF_Msk                      (0x1UL << ETH_MTLTQUR_UFCNTOVF_Pos) /*!< 0x00000800 */
+#define ETH_MTLTQUR_UFCNTOVF                          ETH_MTLTQUR_UFCNTOVF_Msk /* Overflow Bit for Underflow Packet Counter */
+#define ETH_MTLTQUR_UFPKTCNT_Pos                      (0U)
+#define ETH_MTLTQUR_UFPKTCNT_Msk                      (0x7FFUL << ETH_MTLTQUR_UFPKTCNT_Pos) /*!< 0x000007FF */
+#define ETH_MTLTQUR_UFPKTCNT                          ETH_MTLTQUR_UFPKTCNT_Msk /* Underflow Packet Counter */
+
+/* Bit definition for Ethernet MTL Tx Queue Debug Register */
+#define ETH_MTLTQDR_STXSTSF_Pos                       (20U)
+#define ETH_MTLTQDR_STXSTSF_Msk                       (0x7UL << ETH_MTLTQDR_STXSTSF_Pos) /*!< 0x00700000 */
+#define ETH_MTLTQDR_STXSTSF                           ETH_MTLTQDR_STXSTSF_Msk  /* Number of Status Words in the Tx Status FIFO of Queue */
+#define ETH_MTLTQDR_PTXQ_Pos                          (16U)
+#define ETH_MTLTQDR_PTXQ_Msk                          (0x7UL << ETH_MTLTQDR_PTXQ_Pos) /*!< 0x00070000 */
+#define ETH_MTLTQDR_PTXQ                              ETH_MTLTQDR_PTXQ_Msk     /* Number of Packets in the Transmit Queue */
+#define ETH_MTLTQDR_TXSTSFSTS_Pos                     (5U)
+#define ETH_MTLTQDR_TXSTSFSTS_Msk                     (0x1UL << ETH_MTLTQDR_TXSTSFSTS_Pos) /*!< 0x00000020 */
+#define ETH_MTLTQDR_TXSTSFSTS                         ETH_MTLTQDR_TXSTSFSTS_Msk /* MTL Tx Status FIFO Full Status */
+#define ETH_MTLTQDR_TXQSTS_Pos                        (4U)
+#define ETH_MTLTQDR_TXQSTS_Msk                        (0x1UL << ETH_MTLTQDR_TXQSTS_Pos) /*!< 0x00000010 */
+#define ETH_MTLTQDR_TXQSTS                            ETH_MTLTQDR_TXQSTS_Msk   /* MTL Tx Queue Not Empty Status */
+#define ETH_MTLTQDR_TWCSTS_Pos                        (3U)
+#define ETH_MTLTQDR_TWCSTS_Msk                        (0x1UL << ETH_MTLTQDR_TWCSTS_Pos) /*!< 0x00000008 */
+#define ETH_MTLTQDR_TWCSTS                            ETH_MTLTQDR_TWCSTS_Msk   /* MTL Tx Queue Write Controller Status */
+#define ETH_MTLTQDR_TRCSTS_Pos                        (1U)
+#define ETH_MTLTQDR_TRCSTS_Msk                        (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */
+#define ETH_MTLTQDR_TRCSTS                            ETH_MTLTQDR_TRCSTS_Msk  /* MTL Tx Queue Read Controller Status */
+#define ETH_MTLTQDR_TRCSTS_IDLE                       ((uint32_t)0x00000000)  /* Idle state */
+#define ETH_MTLTQDR_TRCSTS_READ                       ((uint32_t)0x00000002)  /* Read state (transferring data to the MAC transmitter) */
+#define ETH_MTLTQDR_TRCSTS_WAITING                    ((uint32_t)0x00000004)  /* Waiting for pending Tx Status from the MAC transmitter */
+#define ETH_MTLTQDR_TRCSTS_FLUSHING                   ((uint32_t)0x00000006)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */
+#define ETH_MTLTQDR_TXQPAUSED_Pos                     (0U)
+#define ETH_MTLTQDR_TXQPAUSED_Msk                     (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */
+#define ETH_MTLTQDR_TXQPAUSED                         ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
+
+/* Bit definition for Ethernet MTL Queue Interrupt Control Status Register */
+#define ETH_MTLQICSR_RXOIE_Pos                        (24U)
+#define ETH_MTLQICSR_RXOIE_Msk                        (0x1UL << ETH_MTLQICSR_RXOIE_Pos) /*!< 0x01000000 */
+#define ETH_MTLQICSR_RXOIE                            ETH_MTLQICSR_RXOIE_Msk   /* Receive Queue Overflow Interrupt Enable */
+#define ETH_MTLQICSR_RXOVFIS_Pos                      (16U)
+#define ETH_MTLQICSR_RXOVFIS_Msk                      (0x1UL << ETH_MTLQICSR_RXOVFIS_Pos) /*!< 0x00010000 */
+#define ETH_MTLQICSR_RXOVFIS                          ETH_MTLQICSR_RXOVFIS_Msk /* Receive Queue Overflow Interrupt Status */
+#define ETH_MTLQICSR_TXUIE_Pos                        (8U)
+#define ETH_MTLQICSR_TXUIE_Msk                        (0x1UL << ETH_MTLQICSR_TXUIE_Pos) /*!< 0x00000100 */
+#define ETH_MTLQICSR_TXUIE                            ETH_MTLQICSR_TXUIE_Msk   /* Transmit Queue Underflow Interrupt Enable */
+#define ETH_MTLQICSR_TXUNFIS_Pos                      (0U)
+#define ETH_MTLQICSR_TXUNFIS_Msk                      (0x1UL << ETH_MTLQICSR_TXUNFIS_Pos) /*!< 0x00000001 */
+#define ETH_MTLQICSR_TXUNFIS                          ETH_MTLQICSR_TXUNFIS_Msk /* Transmit Queue Underflow Interrupt Status */
+
+/* Bit definition for Ethernet MTL Rx Queue Operation Mode Register */
+#define ETH_MTLRQOMR_RQS_Pos                          (20U)
+#define ETH_MTLRQOMR_RQS_Msk                          (0x7UL << ETH_MTLRQOMR_RQS_Pos) /*!< 0x00700000 */
+#define ETH_MTLRQOMR_RQS                              ETH_MTLRQOMR_RQS_Msk /* Receive Queue Size */
+#define ETH_MTLRQOMR_RFD_Pos                          (14U)
+#define ETH_MTLRQOMR_RFD_Msk                          (0x7UL << ETH_MTLRQOMR_RFD_Pos) /*!< 0x0001C000 */
+#define ETH_MTLRQOMR_RFD                              ETH_MTLRQOMR_RFD_Msk /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */
+#define ETH_MTLRQOMR_RFA_Pos                          (8U)
+#define ETH_MTLRQOMR_RFA_Msk                          (0x7UL << ETH_MTLRQOMR_RFA_Pos) /*!< 0x00000700 */
+#define ETH_MTLRQOMR_RFA                              ETH_MTLRQOMR_RFA_Msk /* Threshold for Activating Flow Control (in half-duplex and full-duplex */
+#define ETH_MTLRQOMR_EHFC_Pos                         (7U)
+#define ETH_MTLRQOMR_EHFC_Msk                         (0x1UL << ETH_MTLRQOMR_EHFC_Pos) /*!< 0x00000080 */
+#define ETH_MTLRQOMR_EHFC                             ETH_MTLRQOMR_EHFC_Msk /* DEnable Hardware Flow Control */
+#define ETH_MTLRQOMR_DISTCPEF_Pos                     (6U)
+#define ETH_MTLRQOMR_DISTCPEF_Msk                     (0x1UL << ETH_MTLRQOMR_DISTCPEF_Pos) /*!< 0x00000040 */
+#define ETH_MTLRQOMR_DISTCPEF                         ETH_MTLRQOMR_DISTCPEF_Msk /* Disable Dropping of TCP/IP Checksum Error Packets */
+#define ETH_MTLRQOMR_RSF_Pos                          (5U)
+#define ETH_MTLRQOMR_RSF_Msk                          (0x1UL << ETH_MTLRQOMR_RSF_Pos) /*!< 0x00000020 */
+#define ETH_MTLRQOMR_RSF                              ETH_MTLRQOMR_RSF_Msk     /* Receive Queue Store and Forward */
+#define ETH_MTLRQOMR_FEP_Pos                          (4U)
+#define ETH_MTLRQOMR_FEP_Msk                          (0x1UL << ETH_MTLRQOMR_FEP_Pos) /*!< 0x00000010 */
+#define ETH_MTLRQOMR_FEP                              ETH_MTLRQOMR_FEP_Msk     /* Forward Error Packets */
+#define ETH_MTLRQOMR_FUP_Pos                          (3U)
+#define ETH_MTLRQOMR_FUP_Msk                          (0x1UL << ETH_MTLRQOMR_FUP_Pos) /*!< 0x00000008 */
+#define ETH_MTLRQOMR_FUP                              ETH_MTLRQOMR_FUP_Msk     /* Forward Undersized Good Packets */
+#define ETH_MTLRQOMR_RTC_Pos                          (0U)
+#define ETH_MTLRQOMR_RTC_Msk                          (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */
+#define ETH_MTLRQOMR_RTC                              ETH_MTLRQOMR_RTC_Msk     /* Receive Queue Threshold Control */
+#define ETH_MTLRQOMR_RTC_64BITS                       ((uint32_t)0x00000000)   /* 64 bits Threshold */
+#define ETH_MTLRQOMR_RTC_32BITS                       ((uint32_t)0x00000001)   /* 32 bits Threshold */
+#define ETH_MTLRQOMR_RTC_96BITS                       ((uint32_t)0x00000002)   /* 96 bits Threshold */
+#define ETH_MTLRQOMR_RTC_128BITS                      ((uint32_t)0x00000003)   /* 128 bits Threshold */
+
+/* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
+#define ETH_MTLRQMPOCR_MISCNTOVF_Pos                  (27U)
+#define ETH_MTLRQMPOCR_MISCNTOVF_Msk                  (0x1UL << ETH_MTLRQMPOCR_MISCNTOVF_Pos) /*!< 0x08000000 */
+#define ETH_MTLRQMPOCR_MISCNTOVF                      ETH_MTLRQMPOCR_MISCNTOVF_Msk /* Missed Packet Counter Overflow Bit */
+#define ETH_MTLRQMPOCR_MISPKTCNT_Pos                  (16U)
+#define ETH_MTLRQMPOCR_MISPKTCNT_Msk                  (0x7FFUL << ETH_MTLRQMPOCR_MISPKTCNT_Pos) /*!< 0x07FF0000 */
+#define ETH_MTLRQMPOCR_MISPKTCNT                      ETH_MTLRQMPOCR_MISPKTCNT_Msk /* Missed Packet Counter */
+#define ETH_MTLRQMPOCR_OVFCNTOVF_Pos                  (11U)
+#define ETH_MTLRQMPOCR_OVFCNTOVF_Msk                  (0x1UL << ETH_MTLRQMPOCR_OVFCNTOVF_Pos) /*!< 0x00000800 */
+#define ETH_MTLRQMPOCR_OVFCNTOVF                      ETH_MTLRQMPOCR_OVFCNTOVF_Msk /* Overflow Counter Overflow Bit */
+#define ETH_MTLRQMPOCR_OVFPKTCNT_Pos                  (0U)
+#define ETH_MTLRQMPOCR_OVFPKTCNT_Msk                  (0x7FFUL << ETH_MTLRQMPOCR_OVFPKTCNT_Pos) /*!< 0x000007FF */
+#define ETH_MTLRQMPOCR_OVFPKTCNT                      ETH_MTLRQMPOCR_OVFPKTCNT_Msk /* Overflow Packet Counter */
+
+/* Bit definition for Ethernet MTL Rx Queue Debug Register */
+#define ETH_MTLRQDR_PRXQ_Pos                          (16U)
+#define ETH_MTLRQDR_PRXQ_Msk                          (0x3FFFUL << ETH_MTLRQDR_PRXQ_Pos) /*!< 0x3FFF0000 */
+#define ETH_MTLRQDR_PRXQ                              ETH_MTLRQDR_PRXQ_Msk     /* Number of Packets in Receive Queue */
+#define ETH_MTLRQDR_RXQSTS_Pos                        (4U)
+#define ETH_MTLRQDR_RXQSTS_Msk                        (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */
+#define ETH_MTLRQDR_RXQSTS                            ETH_MTLRQDR_RXQSTS_Msk   /* MTL Rx Queue Fill-Level Status */
+#define ETH_MTLRQDR_RXQSTS_EMPTY                      ((uint32_t)0x00000000)   /* Rx Queue empty */
+#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos         (4U)
+#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
+#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD             ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
+#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos         (5U)
+#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos) /*!< 0x00000020 */
+#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD             ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk /* Rx Queue fill-level above flow-control activate threshold */
+#define ETH_MTLRQDR_RXQSTS_FULL_Pos                   (4U)
+#define ETH_MTLRQDR_RXQSTS_FULL_Msk                   (0x3UL << ETH_MTLRQDR_RXQSTS_FULL_Pos) /*!< 0x00000030 */
+#define ETH_MTLRQDR_RXQSTS_FULL                       ETH_MTLRQDR_RXQSTS_FULL_Msk /* Rx Queue full */
+#define ETH_MTLRQDR_RRCSTS_Pos                        (1U)
+#define ETH_MTLRQDR_RRCSTS_Msk                        (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */
+#define ETH_MTLRQDR_RRCSTS                            ETH_MTLRQDR_RRCSTS_Msk   /* MTL Rx Queue Read Controller State */
+#define ETH_MTLRQDR_RRCSTS_IDLE                       ((uint32_t)0x00000000)   /* Idle state */
+#define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos            (1U)
+#define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk            (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
+#define ETH_MTLRQDR_RRCSTS_READINGDATA                ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
+#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos          (2U)
+#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk          (0x1UL << ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos) /*!< 0x00000004 */
+#define ETH_MTLRQDR_RRCSTS_READINGSTATUS              ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk /* Reading packet status (or timestamp) */
+#define ETH_MTLRQDR_RRCSTS_FLUSHING_Pos               (1U)
+#define ETH_MTLRQDR_RRCSTS_FLUSHING_Msk               (0x3UL << ETH_MTLRQDR_RRCSTS_FLUSHING_Pos) /*!< 0x00000006 */
+#define ETH_MTLRQDR_RRCSTS_FLUSHING                   ETH_MTLRQDR_RRCSTS_FLUSHING_Msk /* Flushing the packet data and status */
+#define ETH_MTLRQDR_RWCSTS_Pos                        (0U)
+#define ETH_MTLRQDR_RWCSTS_Msk                        (0x1UL << ETH_MTLRQDR_RWCSTS_Pos) /*!< 0x00000001 */
+#define ETH_MTLRQDR_RWCSTS                            ETH_MTLRQDR_RWCSTS_Msk   /* MTL Rx Queue Write Controller Active Status */
+
+/* Bit definition for Ethernet MTL Rx Queue Control Register */
+#define ETH_MTLRQCR_RQPA_Pos                          (3U)
+#define ETH_MTLRQCR_RQPA_Msk                          (0x1UL << ETH_MTLRQCR_RQPA_Pos) /*!< 0x00000008 */
+#define ETH_MTLRQCR_RQPA                              ETH_MTLRQCR_RQPA_Msk     /* Receive Queue Packet Arbitration */
+#define ETH_MTLRQCR_RQW_Pos                           (0U)
+#define ETH_MTLRQCR_RQW_Msk                           (0x7UL << ETH_MTLRQCR_RQW_Pos) /*!< 0x00000007 */
+#define ETH_MTLRQCR_RQW                               ETH_MTLRQCR_RQW_Msk      /* Receive Queue Weight */
+
+/* Bit definition for Ethernet DMA Mode Register */
+#define ETH_DMAMR_INTM_Pos                            (16U)
+#define ETH_DMAMR_INTM_Msk                            (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */
+#define ETH_DMAMR_INTM                                ETH_DMAMR_INTM_Msk       /* This field defines the interrupt mode */
+#define ETH_DMAMR_INTM_0                              (0x0UL << ETH_DMAMR_INTM_Pos) /*!< 0x00000000 */
+#define ETH_DMAMR_INTM_1                              (0x1UL << ETH_DMAMR_INTM_Pos) /*!< 0x00010000 */
+#define ETH_DMAMR_INTM_2                              (0x2UL << ETH_DMAMR_INTM_Pos) /*!< 0x00020000 */
+#define ETH_DMAMR_PR_Pos                              (12U)
+#define ETH_DMAMR_PR_Msk                              (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
+#define ETH_DMAMR_PR                                  ETH_DMAMR_PR_Msk         /* Priority Ratio */
+#define ETH_DMAMR_PR_1_1                              ((uint32_t)0x00000000)   /* The priority ratio is 1:1 */
+#define ETH_DMAMR_PR_2_1                              ((uint32_t)0x00001000)   /* The priority ratio is 2:1 */
+#define ETH_DMAMR_PR_3_1                              ((uint32_t)0x00002000)   /* The priority ratio is 3:1 */
+#define ETH_DMAMR_PR_4_1                              ((uint32_t)0x00003000)   /* The priority ratio is 4:1 */
+#define ETH_DMAMR_PR_5_1                              ((uint32_t)0x00004000)   /* The priority ratio is 5:1 */
+#define ETH_DMAMR_PR_6_1                              ((uint32_t)0x00005000)   /* The priority ratio is 6:1 */
+#define ETH_DMAMR_PR_7_1                              ((uint32_t)0x00006000)   /* The priority ratio is 7:1 */
+#define ETH_DMAMR_PR_8_1                              ((uint32_t)0x00007000)   /* The priority ratio is 8:1 */
+#define ETH_DMAMR_TXPR_Pos                            (11U)
+#define ETH_DMAMR_TXPR_Msk                            (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
+#define ETH_DMAMR_TXPR                                ETH_DMAMR_TXPR_Msk       /* Transmit Priority */
+#define ETH_DMAMR_DA_Pos                              (1U)
+#define ETH_DMAMR_DA_Msk                              (0x1UL << ETH_DMAMR_DA_Pos) /*!< 0x00000002 */
+#define ETH_DMAMR_DA                                  ETH_DMAMR_DA_Msk         /* DMA Tx or Rx Arbitration Scheme */
+#define ETH_DMAMR_SWR_Pos                             (0U)
+#define ETH_DMAMR_SWR_Msk                             (0x1UL << ETH_DMAMR_SWR_Pos) /*!< 0x00000001 */
+#define ETH_DMAMR_SWR                                 ETH_DMAMR_SWR_Msk        /* Software Reset */
+
+/* Bit definition for Ethernet DMA SysBus Mode Register */
+#define ETH_DMASBMR_RB_Pos                            (15U)
+#define ETH_DMASBMR_RB_Msk                            (0x1UL << ETH_DMASBMR_RB_Pos) /*!< 0x00008000 */
+#define ETH_DMASBMR_RB                                ETH_DMASBMR_RB_Msk       /* Rebuild INCRx Burst */
+#define ETH_DMASBMR_MB_Pos                            (14U)
+#define ETH_DMASBMR_MB_Msk                            (0x1UL << ETH_DMASBMR_MB_Pos) /*!< 0x00004000 */
+#define ETH_DMASBMR_MB                                ETH_DMASBMR_MB_Msk       /* Mixed Burst */
+#define ETH_DMASBMR_AAL_Pos                           (12U)
+#define ETH_DMASBMR_AAL_Msk                           (0x1UL << ETH_DMASBMR_AAL_Pos) /*!< 0x00001000 */
+#define ETH_DMASBMR_AAL                               ETH_DMASBMR_AAL_Msk      /* Address-Aligned Beats */
+#define ETH_DMASBMR_FB_Pos                            (0U)
+#define ETH_DMASBMR_FB_Msk                            (0x1UL << ETH_DMASBMR_FB_Pos) /*!< 0x00000001 */
+#define ETH_DMASBMR_FB                                ETH_DMASBMR_FB_Msk       /* Fixed Burst Length */
+
+/* Bit definition for Ethernet DMA Interrupt Status Register */
+#define ETH_DMAISR_MACIS_Pos                          (17U)
+#define ETH_DMAISR_MACIS_Msk                          (0x1UL << ETH_DMAISR_MACIS_Pos) /*!< 0x00020000 */
+#define ETH_DMAISR_MACIS                              ETH_DMAISR_MACIS_Msk     /* MAC Interrupt Status */
+#define ETH_DMAISR_MTLIS_Pos                          (16U)
+#define ETH_DMAISR_MTLIS_Msk                          (0x1UL << ETH_DMAISR_MTLIS_Pos) /*!< 0x00010000 */
+#define ETH_DMAISR_MTLIS                              ETH_DMAISR_MTLIS_Msk     /* MAC Interrupt Status */
+#define ETH_DMAISR_DMACIS_Pos                         (0U)
+#define ETH_DMAISR_DMACIS_Msk                         (0x1UL << ETH_DMAISR_DMACIS_Pos) /*!< 0x00000001 */
+#define ETH_DMAISR_DMACIS                             ETH_DMAISR_DMACIS_Msk    /* DMA Channel Interrupt Status */
+
+/* Bit definition for Ethernet DMA Debug Status Register */
+#define ETH_DMADSR_TPS_Pos                            (12U)
+#define ETH_DMADSR_TPS_Msk                            (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */
+#define ETH_DMADSR_TPS                                ETH_DMADSR_TPS_Msk       /* DMA Channel Transmit Process State */
+#define ETH_DMADSR_TPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Transmit Command issued) */
+#define ETH_DMADSR_TPS_FETCHING_Pos                   (12U)
+#define ETH_DMADSR_TPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */
+#define ETH_DMADSR_TPS_FETCHING                       ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
+#define ETH_DMADSR_TPS_WAITING_Pos                    (13U)
+#define ETH_DMADSR_TPS_WAITING_Msk                    (0x1UL << ETH_DMADSR_TPS_WAITING_Pos) /*!< 0x00002000 */
+#define ETH_DMADSR_TPS_WAITING                        ETH_DMADSR_TPS_WAITING_Msk /* Running (Waiting for status) */
+#define ETH_DMADSR_TPS_READING_Pos                    (12U)
+#define ETH_DMADSR_TPS_READING_Msk                    (0x3UL << ETH_DMADSR_TPS_READING_Pos) /*!< 0x00003000 */
+#define ETH_DMADSR_TPS_READING                        ETH_DMADSR_TPS_READING_Msk /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */
+#define ETH_DMADSR_TPS_TIMESTAMP_WR_Pos               (14U)
+#define ETH_DMADSR_TPS_TIMESTAMP_WR_Msk               (0x1UL << ETH_DMADSR_TPS_TIMESTAMP_WR_Pos) /*!< 0x00004000 */
+#define ETH_DMADSR_TPS_TIMESTAMP_WR                   ETH_DMADSR_TPS_TIMESTAMP_WR_Msk /* Timestamp write state */
+#define ETH_DMADSR_TPS_SUSPENDED_Pos                  (13U)
+#define ETH_DMADSR_TPS_SUSPENDED_Msk                  (0x3UL << ETH_DMADSR_TPS_SUSPENDED_Pos) /*!< 0x00006000 */
+#define ETH_DMADSR_TPS_SUSPENDED                      ETH_DMADSR_TPS_SUSPENDED_Msk /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */
+#define ETH_DMADSR_TPS_CLOSING_Pos                    (12U)
+#define ETH_DMADSR_TPS_CLOSING_Msk                    (0x7UL << ETH_DMADSR_TPS_CLOSING_Pos) /*!< 0x00007000 */
+#define ETH_DMADSR_TPS_CLOSING                        ETH_DMADSR_TPS_CLOSING_Msk /* Running (Closing Tx Descriptor) */
+#define ETH_DMADSR_RPS_Pos                            (8U)
+#define ETH_DMADSR_RPS_Msk                            (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */
+#define ETH_DMADSR_RPS                                ETH_DMADSR_RPS_Msk       /* DMA Channel Receive Process State */
+#define ETH_DMADSR_RPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Receive Command issued) */
+#define ETH_DMADSR_RPS_FETCHING_Pos                   (12U)
+#define ETH_DMADSR_RPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */
+#define ETH_DMADSR_RPS_FETCHING                       ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
+#define ETH_DMADSR_RPS_WAITING_Pos                    (12U)
+#define ETH_DMADSR_RPS_WAITING_Msk                    (0x3UL << ETH_DMADSR_RPS_WAITING_Pos) /*!< 0x00003000 */
+#define ETH_DMADSR_RPS_WAITING                        ETH_DMADSR_RPS_WAITING_Msk /* Running (Waiting for status) */
+#define ETH_DMADSR_RPS_SUSPENDED_Pos                  (14U)
+#define ETH_DMADSR_RPS_SUSPENDED_Msk                  (0x1UL << ETH_DMADSR_RPS_SUSPENDED_Pos) /*!< 0x00004000 */
+#define ETH_DMADSR_RPS_SUSPENDED                      ETH_DMADSR_RPS_SUSPENDED_Msk /* Suspended (Rx Descriptor Unavailable) */
+#define ETH_DMADSR_RPS_CLOSING_Pos                    (12U)
+#define ETH_DMADSR_RPS_CLOSING_Msk                    (0x5UL << ETH_DMADSR_RPS_CLOSING_Pos) /*!< 0x00005000 */
+#define ETH_DMADSR_RPS_CLOSING                        ETH_DMADSR_RPS_CLOSING_Msk /* Running (Closing the Rx Descriptor) */
+#define ETH_DMADSR_RPS_TIMESTAMP_WR_Pos               (13U)
+#define ETH_DMADSR_RPS_TIMESTAMP_WR_Msk               (0x3UL << ETH_DMADSR_RPS_TIMESTAMP_WR_Pos) /*!< 0x00006000 */
+#define ETH_DMADSR_RPS_TIMESTAMP_WR                   ETH_DMADSR_RPS_TIMESTAMP_WR_Msk /* Timestamp write state */
+#define ETH_DMADSR_RPS_TRANSFERRING_Pos               (12U)
+#define ETH_DMADSR_RPS_TRANSFERRING_Msk               (0x7UL << ETH_DMADSR_RPS_TRANSFERRING_Pos) /*!< 0x00007000 */
+#define ETH_DMADSR_RPS_TRANSFERRING                   ETH_DMADSR_RPS_TRANSFERRING_Msk /* Running (Transferring the received packet data from the Rx buffer to the system memory) */
+
+/* Bit definition for Ethernet DMA Channel Control Register */
+#define ETH_DMACCR_DSL_Pos                            (18U)
+#define ETH_DMACCR_DSL_Msk                            (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */
+#define ETH_DMACCR_DSL                                ETH_DMACCR_DSL_Msk       /* Descriptor Skip Length */
+#define ETH_DMACCR_DSL_0BIT                           ((uint32_t)0x00000000)
+#define ETH_DMACCR_DSL_32BIT                          ((uint32_t)0x00040000)
+#define ETH_DMACCR_DSL_64BIT                          ((uint32_t)0x00080000)
+#define ETH_DMACCR_DSL_128BIT                         ((uint32_t)0x00100000)
+#define ETH_DMACCR_8PBL                               ((uint32_t)0x00010000)   /* 8xPBL mode */
+#define ETH_DMACCR_MSS_Pos                            (0U)
+#define ETH_DMACCR_MSS_Msk                            (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */
+#define ETH_DMACCR_MSS                                ETH_DMACCR_MSS_Msk       /* Maximum Segment Size */
+
+/* Bit definition for Ethernet DMA Channel Tx Control Register */
+#define ETH_DMACTCR_TPBL_Pos                          (16U)
+#define ETH_DMACTCR_TPBL_Msk                          (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */
+#define ETH_DMACTCR_TPBL                              ETH_DMACTCR_TPBL_Msk     /* Transmit Programmable Burst Length */
+#define ETH_DMACTCR_TPBL_1PBL                         ((uint32_t)0x00010000)   /* Transmit Programmable Burst Length 1 */
+#define ETH_DMACTCR_TPBL_2PBL                         ((uint32_t)0x00020000)   /* Transmit Programmable Burst Length 2 */
+#define ETH_DMACTCR_TPBL_4PBL                         ((uint32_t)0x00040000)   /* Transmit Programmable Burst Length 4 */
+#define ETH_DMACTCR_TPBL_8PBL                         ((uint32_t)0x00080000)   /* Transmit Programmable Burst Length 8 */
+#define ETH_DMACTCR_TPBL_16PBL                        ((uint32_t)0x00100000)   /* Transmit Programmable Burst Length 16 */
+#define ETH_DMACTCR_TPBL_32PBL                        ((uint32_t)0x00200000)   /* Transmit Programmable Burst Length 32 */
+#define ETH_DMACTCR_TSE_Pos                           (12U)
+#define ETH_DMACTCR_TSE_Msk                           (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */
+#define ETH_DMACTCR_TSE                               ETH_DMACTCR_TSE_Msk      /* TCP Segmentation Enabled */
+#define ETH_DMACTCR_OSP_Pos                           (4U)
+#define ETH_DMACTCR_OSP_Msk                           (0x1UL << ETH_DMACTCR_OSP_Pos) /*!< 0x00000010 */
+#define ETH_DMACTCR_OSP                               ETH_DMACTCR_OSP_Msk      /* Operate on Second Packet */
+#define ETH_DMACTCR_ST_Pos                            (0U)
+#define ETH_DMACTCR_ST_Msk                            (0x1UL << ETH_DMACTCR_ST_Pos) /*!< 0x00000001 */
+#define ETH_DMACTCR_ST                                ETH_DMACTCR_ST_Msk       /* Start or Stop Transmission Command */
+
+/* Bit definition for Ethernet DMA Channel Rx Control Register */
+#define ETH_DMACRCR_RPF_Pos                           (31U)
+#define ETH_DMACRCR_RPF_Msk                           (0x1UL << ETH_DMACRCR_RPF_Pos) /*!< 0x80000000 */
+#define ETH_DMACRCR_RPF                               ETH_DMACRCR_RPF_Msk      /* Rx Packet Flush */
+#define ETH_DMACRCR_RPBL_Pos                          (16U)
+#define ETH_DMACRCR_RPBL_Msk                          (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */
+#define ETH_DMACRCR_RPBL                              ETH_DMACRCR_RPBL_Msk     /* Receive Programmable Burst Length */
+#define ETH_DMACRCR_RPBL_1PBL                         ((uint32_t)0x00010000)   /* Receive Programmable Burst Length 1 */
+#define ETH_DMACRCR_RPBL_2PBL                         ((uint32_t)0x00020000)   /* Receive Programmable Burst Length 2 */
+#define ETH_DMACRCR_RPBL_4PBL                         ((uint32_t)0x00040000)   /* Receive Programmable Burst Length 4 */
+#define ETH_DMACRCR_RPBL_8PBL                         ((uint32_t)0x00080000)   /* Receive Programmable Burst Length 8 */
+#define ETH_DMACRCR_RPBL_16PBL                        ((uint32_t)0x00100000)   /* Receive Programmable Burst Length 16 */
+#define ETH_DMACRCR_RPBL_32PBL                        ((uint32_t)0x00200000)   /* Receive Programmable Burst Length 32 */
+#define ETH_DMACRCR_RBSZ_Pos                          (1U)
+#define ETH_DMACRCR_RBSZ_Msk                          (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */
+#define ETH_DMACRCR_RBSZ                              ETH_DMACRCR_RBSZ_Msk     /* Receive Buffer size */
+#define ETH_DMACRCR_SR_Pos                            (0U)
+#define ETH_DMACRCR_SR_Msk                            (0x1UL << ETH_DMACRCR_SR_Pos) /*!< 0x00000001 */
+#define ETH_DMACRCR_SR                                ETH_DMACRCR_SR_Msk       /* Start or Stop Receive */
+
+/* Bit definition for Ethernet DMA CH Tx Desc List Address Register */
+#define ETH_DMACTDLAR_TDESLA_Pos                      (2U)
+#define ETH_DMACTDLAR_TDESLA_Msk                      (0x3FFFFFFFUL << ETH_DMACTDLAR_TDESLA_Pos) /*!< 0xFFFFFFFC */
+#define ETH_DMACTDLAR_TDESLA                          ETH_DMACTDLAR_TDESLA_Msk /* Start of Transmit List */
+
+/* Bit definition for Ethernet DMA CH Rx Desc List Address Register */
+#define ETH_DMACRDLAR_RDESLA_Pos                      (2U)
+#define ETH_DMACRDLAR_RDESLA_Msk                      (0x3FFFFFFFUL << ETH_DMACRDLAR_RDESLA_Pos) /*!< 0xFFFFFFFC */
+#define ETH_DMACRDLAR_RDESLA                          ETH_DMACRDLAR_RDESLA_Msk /* Start of Receive List */
+
+/* Bit definition for Ethernet DMA CH Tx Desc Tail Pointer Register */
+#define ETH_DMACTDTPR_TDT_Pos                         (2U)
+#define ETH_DMACTDTPR_TDT_Msk                         (0x3FFFFFFFUL << ETH_DMACTDTPR_TDT_Pos) /*!< 0xFFFFFFFC */
+#define ETH_DMACTDTPR_TDT                             ETH_DMACTDTPR_TDT_Msk    /* Transmit Descriptor Tail Pointer */
+
+/* Bit definition for Ethernet DMA CH Rx Desc Tail Pointer Register */
+#define ETH_DMACRDTPR_RDT_Pos                         (2U)
+#define ETH_DMACRDTPR_RDT_Msk                         (0x3FFFFFFFUL << ETH_DMACRDTPR_RDT_Pos) /*!< 0xFFFFFFFC */
+#define ETH_DMACRDTPR_RDT                             ETH_DMACRDTPR_RDT_Msk    /* Receive Descriptor Tail Pointer */
+
+/* Bit definition for Ethernet DMA CH Tx Desc Ring Length Register */
+#define ETH_DMACTDRLR_TDRL_Pos                        (0U)
+#define ETH_DMACTDRLR_TDRL_Msk                        (0x3FFUL << ETH_DMACTDRLR_TDRL_Pos) /*!< 0x000003FF */
+#define ETH_DMACTDRLR_TDRL                            ETH_DMACTDRLR_TDRL_Msk   /* Transmit Descriptor Ring Length */
+
+/* Bit definition for Ethernet DMA CH Rx Desc Ring Length Register */
+#define ETH_DMACRDRLR_RDRL_Pos                        (0U)
+#define ETH_DMACRDRLR_RDRL_Msk                        (0x3FFUL << ETH_DMACRDRLR_RDRL_Pos) /*!< 0x000003FF */
+#define ETH_DMACRDRLR_RDRL                            ETH_DMACRDRLR_RDRL_Msk   /* Receive Descriptor Ring Length */
+
+/* Bit definition for Ethernet DMA Channel Interrupt Enable Register */
+#define ETH_DMACIER_NIE_Pos                           (15U)
+#define ETH_DMACIER_NIE_Msk                           (0x1UL << ETH_DMACIER_NIE_Pos) /*!< 0x00008000 */
+#define ETH_DMACIER_NIE                               ETH_DMACIER_NIE_Msk      /* Normal Interrupt Summary Enable */
+#define ETH_DMACIER_AIE_Pos                           (14U)
+#define ETH_DMACIER_AIE_Msk                           (0x1UL << ETH_DMACIER_AIE_Pos) /*!< 0x00004000 */
+#define ETH_DMACIER_AIE                               ETH_DMACIER_AIE_Msk      /* Abnormal Interrupt Summary Enable */
+#define ETH_DMACIER_CDEE_Pos                          (13U)
+#define ETH_DMACIER_CDEE_Msk                          (0x1UL << ETH_DMACIER_CDEE_Pos) /*!< 0x00002000 */
+#define ETH_DMACIER_CDEE                              ETH_DMACIER_CDEE_Msk     /* Context Descriptor Error Enable */
+#define ETH_DMACIER_FBEE_Pos                          (12U)
+#define ETH_DMACIER_FBEE_Msk                          (0x1UL << ETH_DMACIER_FBEE_Pos) /*!< 0x00001000 */
+#define ETH_DMACIER_FBEE                              ETH_DMACIER_FBEE_Msk     /* Fatal Bus Error Enable */
+#define ETH_DMACIER_ERIE_Pos                          (11U)
+#define ETH_DMACIER_ERIE_Msk                          (0x1UL << ETH_DMACIER_ERIE_Pos) /*!< 0x00000800 */
+#define ETH_DMACIER_ERIE                              ETH_DMACIER_ERIE_Msk     /* Early Receive Interrupt Enable */
+#define ETH_DMACIER_ETIE_Pos                          (10U)
+#define ETH_DMACIER_ETIE_Msk                          (0x1UL << ETH_DMACIER_ETIE_Pos) /*!< 0x00000400 */
+#define ETH_DMACIER_ETIE                              ETH_DMACIER_ETIE_Msk     /* Early Transmit Interrupt Enable */
+#define ETH_DMACIER_RWTE_Pos                          (9U)
+#define ETH_DMACIER_RWTE_Msk                          (0x1UL << ETH_DMACIER_RWTE_Pos) /*!< 0x00000200 */
+#define ETH_DMACIER_RWTE                              ETH_DMACIER_RWTE_Msk     /* Receive Watchdog Timeout Enable */
+#define ETH_DMACIER_RSE_Pos                           (8U)
+#define ETH_DMACIER_RSE_Msk                           (0x1UL << ETH_DMACIER_RSE_Pos) /*!< 0x00000100 */
+#define ETH_DMACIER_RSE                               ETH_DMACIER_RSE_Msk      /* Receive Stopped Enable */
+#define ETH_DMACIER_RBUE_Pos                          (7U)
+#define ETH_DMACIER_RBUE_Msk                          (0x1UL << ETH_DMACIER_RBUE_Pos) /*!< 0x00000080 */
+#define ETH_DMACIER_RBUE                              ETH_DMACIER_RBUE_Msk     /* Receive Buffer Unavailable Enable */
+#define ETH_DMACIER_RIE_Pos                           (6U)
+#define ETH_DMACIER_RIE_Msk                           (0x1UL << ETH_DMACIER_RIE_Pos) /*!< 0x00000040 */
+#define ETH_DMACIER_RIE                               ETH_DMACIER_RIE_Msk      /* Receive Interrupt Enable */
+#define ETH_DMACIER_TBUE_Pos                          (2U)
+#define ETH_DMACIER_TBUE_Msk                          (0x1UL << ETH_DMACIER_TBUE_Pos) /*!< 0x00000004 */
+#define ETH_DMACIER_TBUE                              ETH_DMACIER_TBUE_Msk     /* Transmit Buffer Unavailable Enable */
+#define ETH_DMACIER_TXSE_Pos                          (1U)
+#define ETH_DMACIER_TXSE_Msk                          (0x1UL << ETH_DMACIER_TXSE_Pos) /*!< 0x00000002 */
+#define ETH_DMACIER_TXSE                              ETH_DMACIER_TXSE_Msk     /* Transmit Stopped Enable */
+#define ETH_DMACIER_TIE_Pos                           (0U)
+#define ETH_DMACIER_TIE_Msk                           (0x1UL << ETH_DMACIER_TIE_Pos) /*!< 0x00000001 */
+#define ETH_DMACIER_TIE                               ETH_DMACIER_TIE_Msk      /* Transmit Interrupt Enable */
+
+/* Bit definition for Ethernet DMA Channel Rx Interrupt Watchdog Timer Register */
+#define ETH_DMACRIWTR_RWT_Pos                         (0U)
+#define ETH_DMACRIWTR_RWT_Msk                         (0xFFUL << ETH_DMACRIWTR_RWT_Pos) /*!< 0x000000FF */
+#define ETH_DMACRIWTR_RWT                             ETH_DMACRIWTR_RWT_Msk    /* Receive Interrupt Watchdog Timer Count */
+
+/* Bit definition for Ethernet DMA Channel Current App Tx Desc Register */
+#define ETH_DMACCATDR_CURTDESAPTR_Pos                 (0U)
+#define ETH_DMACCATDR_CURTDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCATDR_CURTDESAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACCATDR_CURTDESAPTR                     ETH_DMACCATDR_CURTDESAPTR_Msk /* Application Transmit Descriptor Address Pointer */
+
+/* Bit definition for Ethernet DMA Channel Current App Rx Desc Register */
+#define ETH_DMACCARDR_CURRDESAPTR_Pos                 (0U)
+#define ETH_DMACCARDR_CURRDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCARDR_CURRDESAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACCARDR_CURRDESAPTR                     ETH_DMACCARDR_CURRDESAPTR_Msk /* Application Receive Descriptor Address Pointer */
+
+/* Bit definition for Ethernet DMA Channel Current App Tx Buffer Register */
+#define ETH_DMACCATBR_CURTBUFAPTR_Pos                 (0U)
+#define ETH_DMACCATBR_CURTBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCATBR_CURTBUFAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACCATBR_CURTBUFAPTR                     ETH_DMACCATBR_CURTBUFAPTR_Msk /* Application Transmit Buffer Address Pointer */
+
+/* Bit definition for Ethernet DMA Channel Current App Rx Buffer Register */
+#define ETH_DMACCARBR_CURRBUFAPTR_Pos                 (0U)
+#define ETH_DMACCARBR_CURRBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCARBR_CURRBUFAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACCARBR_CURRBUFAPTR                     ETH_DMACCARBR_CURRBUFAPTR_Msk /* Application Receive Buffer Address Pointer */
+
+/* Bit definition for Ethernet DMA Channel Status Register */
+#define ETH_DMACSR_REB_Pos                            (19U)
+#define ETH_DMACSR_REB_Msk                            (0x7UL << ETH_DMACSR_REB_Pos) /*!< 0x00380000 */
+#define ETH_DMACSR_REB                                ETH_DMACSR_REB_Msk       /* Rx DMA Error Bits */
+#define ETH_DMACSR_TEB_Pos                            (16U)
+#define ETH_DMACSR_TEB_Msk                            (0x7UL << ETH_DMACSR_TEB_Pos) /*!< 0x00070000 */
+#define ETH_DMACSR_TEB                                ETH_DMACSR_TEB_Msk       /* Tx DMA Error Bits */
+#define ETH_DMACSR_NIS_Pos                            (15U)
+#define ETH_DMACSR_NIS_Msk                            (0x1UL << ETH_DMACSR_NIS_Pos) /*!< 0x00008000 */
+#define ETH_DMACSR_NIS                                ETH_DMACSR_NIS_Msk       /* Normal Interrupt Summary */
+#define ETH_DMACSR_AIS_Pos                            (14U)
+#define ETH_DMACSR_AIS_Msk                            (0x1UL << ETH_DMACSR_AIS_Pos) /*!< 0x00004000 */
+#define ETH_DMACSR_AIS                                ETH_DMACSR_AIS_Msk       /* Abnormal Interrupt Summary */
+#define ETH_DMACSR_CDE_Pos                            (13U)
+#define ETH_DMACSR_CDE_Msk                            (0x1UL << ETH_DMACSR_CDE_Pos) /*!< 0x00002000 */
+#define ETH_DMACSR_CDE                                ETH_DMACSR_CDE_Msk       /* Context Descriptor Error */
+#define ETH_DMACSR_FBE_Pos                            (12U)
+#define ETH_DMACSR_FBE_Msk                            (0x1UL << ETH_DMACSR_FBE_Pos) /*!< 0x00001000 */
+#define ETH_DMACSR_FBE                                ETH_DMACSR_FBE_Msk       /* Fatal Bus Error */
+#define ETH_DMACSR_ERI_Pos                            (11U)
+#define ETH_DMACSR_ERI_Msk                            (0x1UL << ETH_DMACSR_ERI_Pos) /*!< 0x00000800 */
+#define ETH_DMACSR_ERI                                ETH_DMACSR_ERI_Msk       /* Early Receive Interrupt */
+#define ETH_DMACSR_ETI_Pos                            (10U)
+#define ETH_DMACSR_ETI_Msk                            (0x1UL << ETH_DMACSR_ETI_Pos) /*!< 0x00000400 */
+#define ETH_DMACSR_ETI                                ETH_DMACSR_ETI_Msk       /* Early Transmit Interrupt */
+#define ETH_DMACSR_RWT_Pos                            (9U)
+#define ETH_DMACSR_RWT_Msk                            (0x1UL << ETH_DMACSR_RWT_Pos) /*!< 0x00000200 */
+#define ETH_DMACSR_RWT                                ETH_DMACSR_RWT_Msk       /* Receive Watchdog Timeout */
+#define ETH_DMACSR_RPS_Pos                            (8U)
+#define ETH_DMACSR_RPS_Msk                            (0x1UL << ETH_DMACSR_RPS_Pos) /*!< 0x00000100 */
+#define ETH_DMACSR_RPS                                ETH_DMACSR_RPS_Msk       /* Receive Process Stopped */
+#define ETH_DMACSR_RBU_Pos                            (7U)
+#define ETH_DMACSR_RBU_Msk                            (0x1UL << ETH_DMACSR_RBU_Pos) /*!< 0x00000080 */
+#define ETH_DMACSR_RBU                                ETH_DMACSR_RBU_Msk       /* Receive Buffer Unavailable */
+#define ETH_DMACSR_RI_Pos                             (6U)
+#define ETH_DMACSR_RI_Msk                             (0x1UL << ETH_DMACSR_RI_Pos) /*!< 0x00000040 */
+#define ETH_DMACSR_RI                                 ETH_DMACSR_RI_Msk        /* Receive Interrupt */
+#define ETH_DMACSR_TBU_Pos                            (2U)
+#define ETH_DMACSR_TBU_Msk                            (0x1UL << ETH_DMACSR_TBU_Pos) /*!< 0x00000004 */
+#define ETH_DMACSR_TBU                                ETH_DMACSR_TBU_Msk       /* Transmit Buffer Unavailable */
+#define ETH_DMACSR_TPS_Pos                            (1U)
+#define ETH_DMACSR_TPS_Msk                            (0x1UL << ETH_DMACSR_TPS_Pos) /*!< 0x00000002 */
+#define ETH_DMACSR_TPS                                ETH_DMACSR_TPS_Msk       /* Transmit Process Stopped */
+#define ETH_DMACSR_TI_Pos                             (0U)
+#define ETH_DMACSR_TI_Msk                             (0x1UL << ETH_DMACSR_TI_Pos) /*!< 0x00000001 */
+#define ETH_DMACSR_TI                                 ETH_DMACSR_TI_Msk        /* Transmit Interrupt */
+
+/* Bit definition for Ethernet DMA Channel missed frame count register */
+#define ETH_DMACMFCR_MFCO_Pos                         (15U)
+#define ETH_DMACMFCR_MFCO_Msk                         (0x1UL << ETH_DMACMFCR_MFCO_Pos) /*!< 0x00008000 */
+#define ETH_DMACMFCR_MFCO                             ETH_DMACMFCR_MFCO_Msk    /* Overflow status of the MFC Counter */
+#define ETH_DMACMFCR_MFC_Pos                          (0U)
+#define ETH_DMACMFCR_MFC_Msk                          (0x7FFUL << ETH_DMACMFCR_MFC_Pos) /*!< 0x000007FF */
+#define ETH_DMACMFCR_MFC                              ETH_DMACMFCR_MFC_Msk     /* The number of packet counters dropped by the DMA */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             DMA Controller                                 */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for DMA_SxCR register  *****************/
+#define DMA_SxCR_MBURST_Pos      (23U)
+#define DMA_SxCR_MBURST_Msk      (0x3UL << DMA_SxCR_MBURST_Pos)                /*!< 0x01800000 */
+#define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk                           /*!< Memory burst transfer configuration */
+#define DMA_SxCR_MBURST_0        (0x1UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */
+#define DMA_SxCR_MBURST_1        (0x2UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */
+#define DMA_SxCR_PBURST_Pos      (21U)
+#define DMA_SxCR_PBURST_Msk      (0x3UL << DMA_SxCR_PBURST_Pos)                /*!< 0x00600000 */
+#define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk                           /*!< Peripheral burst transfer configuration */
+#define DMA_SxCR_PBURST_0        (0x1UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */
+#define DMA_SxCR_PBURST_1        (0x2UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */
+#define DMA_SxCR_TRBUFF_Pos      (20U)
+#define DMA_SxCR_TRBUFF_Msk      (0x1UL << DMA_SxCR_TRBUFF_Pos)                 /*!< 0x00100000 */
+#define DMA_SxCR_TRBUFF          DMA_SxCR_TRBUFF_Msk                            /*!< bufferable transfers enabled/disable */
+#define DMA_SxCR_CT_Pos          (19U)
+#define DMA_SxCR_CT_Msk          (0x1UL << DMA_SxCR_CT_Pos)                    /*!< 0x00080000 */
+#define DMA_SxCR_CT              DMA_SxCR_CT_Msk                               /*!< Current target (only in double buffer mode) */
+#define DMA_SxCR_DBM_Pos         (18U)
+#define DMA_SxCR_DBM_Msk         (0x1UL << DMA_SxCR_DBM_Pos)                   /*!< 0x00040000 */
+#define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk                              /*!< Double buffer mode */
+#define DMA_SxCR_PL_Pos          (16U)
+#define DMA_SxCR_PL_Msk          (0x3UL << DMA_SxCR_PL_Pos)                    /*!< 0x00030000 */
+#define DMA_SxCR_PL              DMA_SxCR_PL_Msk                               /*!< Priority level */
+#define DMA_SxCR_PL_0            (0x1UL << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */
+#define DMA_SxCR_PL_1            (0x2UL << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */
+#define DMA_SxCR_PINCOS_Pos      (15U)
+#define DMA_SxCR_PINCOS_Msk      (0x1UL << DMA_SxCR_PINCOS_Pos)                /*!< 0x00008000 */
+#define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk                           /*!< Peripheral increment offset size */
+#define DMA_SxCR_MSIZE_Pos       (13U)
+#define DMA_SxCR_MSIZE_Msk       (0x3UL << DMA_SxCR_MSIZE_Pos)                 /*!< 0x00006000 */
+#define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk                            /*!< Memory data size */
+#define DMA_SxCR_MSIZE_0         (0x1UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */
+#define DMA_SxCR_MSIZE_1         (0x2UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */
+#define DMA_SxCR_PSIZE_Pos       (11U)
+#define DMA_SxCR_PSIZE_Msk       (0x3UL << DMA_SxCR_PSIZE_Pos)                 /*!< 0x00001800 */
+#define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk                            /*< Peripheral data size */
+#define DMA_SxCR_PSIZE_0         (0x1UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */
+#define DMA_SxCR_PSIZE_1         (0x2UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */
+#define DMA_SxCR_MINC_Pos        (10U)
+#define DMA_SxCR_MINC_Msk        (0x1UL << DMA_SxCR_MINC_Pos)                  /*!< 0x00000400 */
+#define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk                             /*!< Memory increment mode */
+#define DMA_SxCR_PINC_Pos        (9U)
+#define DMA_SxCR_PINC_Msk        (0x1UL << DMA_SxCR_PINC_Pos)                  /*!< 0x00000200 */
+#define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk                             /*!< Peripheral increment mode */
+#define DMA_SxCR_CIRC_Pos        (8U)
+#define DMA_SxCR_CIRC_Msk        (0x1UL << DMA_SxCR_CIRC_Pos)                  /*!< 0x00000100 */
+#define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk                             /*!< Circular mode */
+#define DMA_SxCR_DIR_Pos         (6U)
+#define DMA_SxCR_DIR_Msk         (0x3UL << DMA_SxCR_DIR_Pos)                   /*!< 0x000000C0 */
+#define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk                              /*!< Data transfer direction */
+#define DMA_SxCR_DIR_0           (0x1UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */
+#define DMA_SxCR_DIR_1           (0x2UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */
+#define DMA_SxCR_PFCTRL_Pos      (5U)
+#define DMA_SxCR_PFCTRL_Msk      (0x1UL << DMA_SxCR_PFCTRL_Pos)                /*!< 0x00000020 */
+#define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk                           /*!< Peripheral flow controller */
+#define DMA_SxCR_TCIE_Pos        (4U)
+#define DMA_SxCR_TCIE_Msk        (0x1UL << DMA_SxCR_TCIE_Pos)                  /*!< 0x00000010 */
+#define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk                             /*!< Transfer complete interrupt enable */
+#define DMA_SxCR_HTIE_Pos        (3U)
+#define DMA_SxCR_HTIE_Msk        (0x1UL << DMA_SxCR_HTIE_Pos)                  /*!< 0x00000008 */
+#define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk                             /*!< Half transfer interrupt enable */
+#define DMA_SxCR_TEIE_Pos        (2U)
+#define DMA_SxCR_TEIE_Msk        (0x1UL << DMA_SxCR_TEIE_Pos)                  /*!< 0x00000004 */
+#define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk                             /*!< Transfer error interrupt enable */
+#define DMA_SxCR_DMEIE_Pos       (1U)
+#define DMA_SxCR_DMEIE_Msk       (0x1UL << DMA_SxCR_DMEIE_Pos)                 /*!< 0x00000002 */
+#define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk                            /*!< Direct mode error interrupt enable */
+#define DMA_SxCR_EN_Pos          (0U)
+#define DMA_SxCR_EN_Msk          (0x1UL << DMA_SxCR_EN_Pos)                    /*!< 0x00000001 */
+#define DMA_SxCR_EN              DMA_SxCR_EN_Msk                               /*!< Stream enable / flag stream ready when read low */
+
+/********************  Bits definition for DMA_SxCNDTR register  **************/
+#define DMA_SxNDT_Pos            (0U)
+#define DMA_SxNDT_Msk            (0xFFFFUL << DMA_SxNDT_Pos)                   /*!< 0x0000FFFF */
+#define DMA_SxNDT                DMA_SxNDT_Msk                                 /*!< Number of data items to transfer */
+#define DMA_SxNDT_0              (0x0001UL << DMA_SxNDT_Pos)                    /*!< 0x00000001 */
+#define DMA_SxNDT_1              (0x0002UL << DMA_SxNDT_Pos)                    /*!< 0x00000002 */
+#define DMA_SxNDT_2              (0x0004UL << DMA_SxNDT_Pos)                    /*!< 0x00000004 */
+#define DMA_SxNDT_3              (0x0008UL << DMA_SxNDT_Pos)                    /*!< 0x00000008 */
+#define DMA_SxNDT_4              (0x0010UL << DMA_SxNDT_Pos)                    /*!< 0x00000010 */
+#define DMA_SxNDT_5              (0x0020UL << DMA_SxNDT_Pos)                    /*!< 0x00000020 */
+#define DMA_SxNDT_6              (0x0040UL << DMA_SxNDT_Pos)                    /*!< 0x00000040 */
+#define DMA_SxNDT_7              (0x0080UL << DMA_SxNDT_Pos)                    /*!< 0x00000080 */
+#define DMA_SxNDT_8              (0x0100UL << DMA_SxNDT_Pos)                    /*!< 0x00000100 */
+#define DMA_SxNDT_9              (0x0200UL << DMA_SxNDT_Pos)                    /*!< 0x00000200 */
+#define DMA_SxNDT_10             (0x0400UL << DMA_SxNDT_Pos)                    /*!< 0x00000400 */
+#define DMA_SxNDT_11             (0x0800UL << DMA_SxNDT_Pos)                    /*!< 0x00000800 */
+#define DMA_SxNDT_12             (0x1000UL << DMA_SxNDT_Pos)                    /*!< 0x00001000 */
+#define DMA_SxNDT_13             (0x2000UL << DMA_SxNDT_Pos)                    /*!< 0x00002000 */
+#define DMA_SxNDT_14             (0x4000UL << DMA_SxNDT_Pos)                    /*!< 0x00004000 */
+#define DMA_SxNDT_15             (0x8000UL << DMA_SxNDT_Pos)                    /*!< 0x00008000 */
+
+/********************  Bits definition for DMA_SxFCR register  ****************/
+#define DMA_SxFCR_FEIE_Pos       (7U)
+#define DMA_SxFCR_FEIE_Msk       (0x1UL << DMA_SxFCR_FEIE_Pos)                 /*!< 0x00000080 */
+#define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk                            /*!< FIFO error interrupt enable */
+#define DMA_SxFCR_FS_Pos         (3U)
+#define DMA_SxFCR_FS_Msk         (0x7UL << DMA_SxFCR_FS_Pos)                   /*!< 0x00000038 */
+#define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk                              /*!< FIFO status */
+#define DMA_SxFCR_FS_0           (0x1UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */
+#define DMA_SxFCR_FS_1           (0x2UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */
+#define DMA_SxFCR_FS_2           (0x4UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */
+#define DMA_SxFCR_DMDIS_Pos      (2U)
+#define DMA_SxFCR_DMDIS_Msk      (0x1UL << DMA_SxFCR_DMDIS_Pos)                /*!< 0x00000004 */
+#define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk                           /*!< Direct mode disable */
+#define DMA_SxFCR_FTH_Pos        (0U)
+#define DMA_SxFCR_FTH_Msk        (0x3UL << DMA_SxFCR_FTH_Pos)                  /*!< 0x00000003 */
+#define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk                             /*!< FIFO threshold selection */
+#define DMA_SxFCR_FTH_0          (0x1UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */
+#define DMA_SxFCR_FTH_1          (0x2UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */
+
+/********************  Bits definition for DMA_LISR register  *****************/
+#define DMA_LISR_TCIF3_Pos       (27U)
+#define DMA_LISR_TCIF3_Msk       (0x1UL << DMA_LISR_TCIF3_Pos)                 /*!< 0x08000000 */
+#define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk                            /*!<  Stream 3 transfer complete interrupt flag */
+#define DMA_LISR_HTIF3_Pos       (26U)
+#define DMA_LISR_HTIF3_Msk       (0x1UL << DMA_LISR_HTIF3_Pos)                 /*!< 0x04000000 */
+#define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk                            /*!<  Stream 3 half transfer interrupt flag */
+#define DMA_LISR_TEIF3_Pos       (25U)
+#define DMA_LISR_TEIF3_Msk       (0x1UL << DMA_LISR_TEIF3_Pos)                 /*!< 0x02000000 */
+#define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk                            /*!<  Stream 3 transfer error interrupt flag */
+#define DMA_LISR_DMEIF3_Pos      (24U)
+#define DMA_LISR_DMEIF3_Msk      (0x1UL << DMA_LISR_DMEIF3_Pos)                /*!< 0x01000000 */
+#define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk                           /*!<  Stream 3 direct mode error interrupt flag */
+#define DMA_LISR_FEIF3_Pos       (22U)
+#define DMA_LISR_FEIF3_Msk       (0x1UL << DMA_LISR_FEIF3_Pos)                 /*!< 0x00400000 */
+#define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk                            /*!<  Stream 3 FIFO error interrupt flag */
+#define DMA_LISR_TCIF2_Pos       (21U)
+#define DMA_LISR_TCIF2_Msk       (0x1UL << DMA_LISR_TCIF2_Pos)                 /*!< 0x00200000 */
+#define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk                            /*!<  Stream 2 transfer complete interrupt flag */
+#define DMA_LISR_HTIF2_Pos       (20U)
+#define DMA_LISR_HTIF2_Msk       (0x1UL << DMA_LISR_HTIF2_Pos)                 /*!< 0x00100000 */
+#define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk                            /*!<  Stream 2 half transfer interrupt flag */
+#define DMA_LISR_TEIF2_Pos       (19U)
+#define DMA_LISR_TEIF2_Msk       (0x1UL << DMA_LISR_TEIF2_Pos)                 /*!< 0x00080000 */
+#define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk                            /*!<  Stream 2 transfer error interrupt flag */
+#define DMA_LISR_DMEIF2_Pos      (18U)
+#define DMA_LISR_DMEIF2_Msk      (0x1UL << DMA_LISR_DMEIF2_Pos)                /*!< 0x00040000 */
+#define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk                           /*!<  Stream 2 direct mode error interrupt flag */
+#define DMA_LISR_FEIF2_Pos       (16U)
+#define DMA_LISR_FEIF2_Msk       (0x1UL << DMA_LISR_FEIF2_Pos)                 /*!< 0x00010000 */
+#define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk                            /*!<  Stream 2 FIFO error interrupt flag */
+#define DMA_LISR_TCIF1_Pos       (11U)
+#define DMA_LISR_TCIF1_Msk       (0x1UL << DMA_LISR_TCIF1_Pos)                 /*!< 0x00000800 */
+#define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk                            /*!<  Stream 1 transfer complete interrupt flag */
+#define DMA_LISR_HTIF1_Pos       (10U)
+#define DMA_LISR_HTIF1_Msk       (0x1UL << DMA_LISR_HTIF1_Pos)                 /*!< 0x00000400 */
+#define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk                            /*!<  Stream 1 half transfer interrupt flag */
+#define DMA_LISR_TEIF1_Pos       (9U)
+#define DMA_LISR_TEIF1_Msk       (0x1UL << DMA_LISR_TEIF1_Pos)                 /*!< 0x00000200 */
+#define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk                            /*!<  Stream 1 transfer error interrupt flag */
+#define DMA_LISR_DMEIF1_Pos      (8U)
+#define DMA_LISR_DMEIF1_Msk      (0x1UL << DMA_LISR_DMEIF1_Pos)                /*!< 0x00000100 */
+#define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk                           /*!<  Stream 1 direct mode error interrupt flag */
+#define DMA_LISR_FEIF1_Pos       (6U)
+#define DMA_LISR_FEIF1_Msk       (0x1UL << DMA_LISR_FEIF1_Pos)                 /*!< 0x00000040 */
+#define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk                            /*!<  Stream 1 FIFO error interrupt flag */
+#define DMA_LISR_TCIF0_Pos       (5U)
+#define DMA_LISR_TCIF0_Msk       (0x1UL << DMA_LISR_TCIF0_Pos)                 /*!< 0x00000020 */
+#define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk                            /*!<  Stream 0 transfer complete interrupt flag */
+#define DMA_LISR_HTIF0_Pos       (4U)
+#define DMA_LISR_HTIF0_Msk       (0x1UL << DMA_LISR_HTIF0_Pos)                 /*!< 0x00000010 */
+#define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk                            /*!<  Stream 0 half transfer interrupt flag */
+#define DMA_LISR_TEIF0_Pos       (3U)
+#define DMA_LISR_TEIF0_Msk       (0x1UL << DMA_LISR_TEIF0_Pos)                 /*!< 0x00000008 */
+#define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk                            /*!<  Stream 0 transfer error interrupt flag */
+#define DMA_LISR_DMEIF0_Pos      (2U)
+#define DMA_LISR_DMEIF0_Msk      (0x1UL << DMA_LISR_DMEIF0_Pos)                /*!< 0x00000004 */
+#define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk                           /*!<  Stream 0 direct mode error interrupt flag */
+#define DMA_LISR_FEIF0_Pos       (0U)
+#define DMA_LISR_FEIF0_Msk       (0x1UL << DMA_LISR_FEIF0_Pos)                 /*!< 0x00000001 */
+#define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk                            /*!<  Stream 0 FIFO error interrupt flag */
+
+/********************  Bits definition for DMA_HISR register  *****************/
+#define DMA_HISR_TCIF7_Pos       (27U)
+#define DMA_HISR_TCIF7_Msk       (0x1UL << DMA_HISR_TCIF7_Pos)                 /*!< 0x08000000 */
+#define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk                            /*!<  Stream 7 transfer complete interrupt flag */
+#define DMA_HISR_HTIF7_Pos       (26U)
+#define DMA_HISR_HTIF7_Msk       (0x1UL << DMA_HISR_HTIF7_Pos)                 /*!< 0x04000000 */
+#define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk                            /*!<  Stream 7 half transfer interrupt flag */
+#define DMA_HISR_TEIF7_Pos       (25U)
+#define DMA_HISR_TEIF7_Msk       (0x1UL << DMA_HISR_TEIF7_Pos)                 /*!< 0x02000000 */
+#define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk                            /*!<  Stream 7 transfer error interrupt flag */
+#define DMA_HISR_DMEIF7_Pos      (24U)
+#define DMA_HISR_DMEIF7_Msk      (0x1UL << DMA_HISR_DMEIF7_Pos)                /*!< 0x01000000 */
+#define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk                           /*!<  Stream 7 direct mode error interrupt flag */
+#define DMA_HISR_FEIF7_Pos       (22U)
+#define DMA_HISR_FEIF7_Msk       (0x1UL << DMA_HISR_FEIF7_Pos)                 /*!< 0x00400000 */
+#define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk                            /*!<  Stream 7 FIFO error interrupt flag */
+#define DMA_HISR_TCIF6_Pos       (21U)
+#define DMA_HISR_TCIF6_Msk       (0x1UL << DMA_HISR_TCIF6_Pos)                 /*!< 0x00200000 */
+#define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk                            /*!<  Stream 6 transfer complete interrupt flag */
+#define DMA_HISR_HTIF6_Pos       (20U)
+#define DMA_HISR_HTIF6_Msk       (0x1UL << DMA_HISR_HTIF6_Pos)                 /*!< 0x00100000 */
+#define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk                            /*!<  Stream 6 half transfer interrupt flag */
+#define DMA_HISR_TEIF6_Pos       (19U)
+#define DMA_HISR_TEIF6_Msk       (0x1UL << DMA_HISR_TEIF6_Pos)                 /*!< 0x00080000 */
+#define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk                            /*!<  Stream 6 transfer error interrupt flag */
+#define DMA_HISR_DMEIF6_Pos      (18U)
+#define DMA_HISR_DMEIF6_Msk      (0x1UL << DMA_HISR_DMEIF6_Pos)                /*!< 0x00040000 */
+#define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk                           /*!<  Stream 6 direct mode error interrupt flag */
+#define DMA_HISR_FEIF6_Pos       (16U)
+#define DMA_HISR_FEIF6_Msk       (0x1UL << DMA_HISR_FEIF6_Pos)                 /*!< 0x00010000 */
+#define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk                            /*!<  Stream 6 FIFO error interrupt flag */
+#define DMA_HISR_TCIF5_Pos       (11U)
+#define DMA_HISR_TCIF5_Msk       (0x1UL << DMA_HISR_TCIF5_Pos)                 /*!< 0x00000800 */
+#define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk                            /*!<  Stream 5 transfer complete interrupt flag */
+#define DMA_HISR_HTIF5_Pos       (10U)
+#define DMA_HISR_HTIF5_Msk       (0x1UL << DMA_HISR_HTIF5_Pos)                 /*!< 0x00000400 */
+#define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk                            /*!<  Stream 5 half transfer interrupt flag */
+#define DMA_HISR_TEIF5_Pos       (9U)
+#define DMA_HISR_TEIF5_Msk       (0x1UL << DMA_HISR_TEIF5_Pos)                 /*!< 0x00000200 */
+#define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk                            /*!<  Stream 5 transfer error interrupt flag */
+#define DMA_HISR_DMEIF5_Pos      (8U)
+#define DMA_HISR_DMEIF5_Msk      (0x1UL << DMA_HISR_DMEIF5_Pos)                /*!< 0x00000100 */
+#define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk                           /*!<  Stream 5 direct mode error interrupt flag */
+#define DMA_HISR_FEIF5_Pos       (6U)
+#define DMA_HISR_FEIF5_Msk       (0x1UL << DMA_HISR_FEIF5_Pos)                 /*!< 0x00000040 */
+#define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk                            /*!<  Stream 5 FIFO error interrupt flag */
+#define DMA_HISR_TCIF4_Pos       (5U)
+#define DMA_HISR_TCIF4_Msk       (0x1UL << DMA_HISR_TCIF4_Pos)                 /*!< 0x00000020 */
+#define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk                            /*!<  Stream 4 transfer complete interrupt flag */
+#define DMA_HISR_HTIF4_Pos       (4U)
+#define DMA_HISR_HTIF4_Msk       (0x1UL << DMA_HISR_HTIF4_Pos)                 /*!< 0x00000010 */
+#define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk                            /*!<  Stream 4 half transfer interrupt flag */
+#define DMA_HISR_TEIF4_Pos       (3U)
+#define DMA_HISR_TEIF4_Msk       (0x1UL << DMA_HISR_TEIF4_Pos)                 /*!< 0x00000008 */
+#define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk                            /*!<  Stream 4 transfer error interrupt flag */
+#define DMA_HISR_DMEIF4_Pos      (2U)
+#define DMA_HISR_DMEIF4_Msk      (0x1UL << DMA_HISR_DMEIF4_Pos)                /*!< 0x00000004 */
+#define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk                           /*!<  Stream 4 direct mode error interrupt flag */
+#define DMA_HISR_FEIF4_Pos       (0U)
+#define DMA_HISR_FEIF4_Msk       (0x1UL << DMA_HISR_FEIF4_Pos)                 /*!< 0x00000001 */
+#define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk                            /*!<  Stream 4 FIFO error interrupt flag */
+
+/********************  Bits definition for DMA_LIFCR register  ****************/
+#define DMA_LIFCR_CTCIF3_Pos     (27U)
+#define DMA_LIFCR_CTCIF3_Msk     (0x1UL << DMA_LIFCR_CTCIF3_Pos)               /*!< 0x08000000 */
+#define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk                          /*!<  Stream 3 clear transfer complete interrupt flag */
+#define DMA_LIFCR_CHTIF3_Pos     (26U)
+#define DMA_LIFCR_CHTIF3_Msk     (0x1UL << DMA_LIFCR_CHTIF3_Pos)               /*!< 0x04000000 */
+#define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk                          /*!<  Stream 3 clear half transfer interrupt flag */
+#define DMA_LIFCR_CTEIF3_Pos     (25U)
+#define DMA_LIFCR_CTEIF3_Msk     (0x1UL << DMA_LIFCR_CTEIF3_Pos)               /*!< 0x02000000 */
+#define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk                          /*!<  Stream 3 clear transfer error interrupt flag */
+#define DMA_LIFCR_CDMEIF3_Pos    (24U)
+#define DMA_LIFCR_CDMEIF3_Msk    (0x1UL << DMA_LIFCR_CDMEIF3_Pos)              /*!< 0x01000000 */
+#define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk                         /*!<  Stream 3 clear direct mode error interrupt flag */
+#define DMA_LIFCR_CFEIF3_Pos     (22U)
+#define DMA_LIFCR_CFEIF3_Msk     (0x1UL << DMA_LIFCR_CFEIF3_Pos)               /*!< 0x00400000 */
+#define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk                          /*!<  Stream 3 clear FIFO error interrupt flag */
+#define DMA_LIFCR_CTCIF2_Pos     (21U)
+#define DMA_LIFCR_CTCIF2_Msk     (0x1UL << DMA_LIFCR_CTCIF2_Pos)               /*!< 0x00200000 */
+#define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk                          /*!<  Stream 2 clear transfer complete interrupt flag */
+#define DMA_LIFCR_CHTIF2_Pos     (20U)
+#define DMA_LIFCR_CHTIF2_Msk     (0x1UL << DMA_LIFCR_CHTIF2_Pos)               /*!< 0x00100000 */
+#define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk                          /*!<  Stream 2 clear half transfer interrupt flag */
+#define DMA_LIFCR_CTEIF2_Pos     (19U)
+#define DMA_LIFCR_CTEIF2_Msk     (0x1UL << DMA_LIFCR_CTEIF2_Pos)               /*!< 0x00080000 */
+#define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk                          /*!<  Stream 2 clear transfer error interrupt flag */
+#define DMA_LIFCR_CDMEIF2_Pos    (18U)
+#define DMA_LIFCR_CDMEIF2_Msk    (0x1UL << DMA_LIFCR_CDMEIF2_Pos)              /*!< 0x00040000 */
+#define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk                         /*!<  Stream 2 clear direct mode error interrupt flag */
+#define DMA_LIFCR_CFEIF2_Pos     (16U)
+#define DMA_LIFCR_CFEIF2_Msk     (0x1UL << DMA_LIFCR_CFEIF2_Pos)               /*!< 0x00010000 */
+#define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk                          /*!<  Stream 2 clear FIFO error interrupt flag */
+#define DMA_LIFCR_CTCIF1_Pos     (11U)
+#define DMA_LIFCR_CTCIF1_Msk     (0x1UL << DMA_LIFCR_CTCIF1_Pos)               /*!< 0x00000800 */
+#define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk                          /*!<  Stream 1 clear transfer complete interrupt flag */
+#define DMA_LIFCR_CHTIF1_Pos     (10U)
+#define DMA_LIFCR_CHTIF1_Msk     (0x1UL << DMA_LIFCR_CHTIF1_Pos)               /*!< 0x00000400 */
+#define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk                          /*!<  Stream 1 clear half transfer interrupt flag */
+#define DMA_LIFCR_CTEIF1_Pos     (9U)
+#define DMA_LIFCR_CTEIF1_Msk     (0x1UL << DMA_LIFCR_CTEIF1_Pos)               /*!< 0x00000200 */
+#define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk                          /*!<  Stream 1 clear transfer error interrupt flag */
+#define DMA_LIFCR_CDMEIF1_Pos    (8U)
+#define DMA_LIFCR_CDMEIF1_Msk    (0x1UL << DMA_LIFCR_CDMEIF1_Pos)              /*!< 0x00000100 */
+#define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk                         /*!<  Stream 1 clear direct mode error interrupt flag */
+#define DMA_LIFCR_CFEIF1_Pos     (6U)
+#define DMA_LIFCR_CFEIF1_Msk     (0x1UL << DMA_LIFCR_CFEIF1_Pos)               /*!< 0x00000040 */
+#define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk                          /*!<  Stream 1 clear FIFO error interrupt flag */
+#define DMA_LIFCR_CTCIF0_Pos     (5U)
+#define DMA_LIFCR_CTCIF0_Msk     (0x1UL << DMA_LIFCR_CTCIF0_Pos)               /*!< 0x00000020 */
+#define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk                          /*!<  Stream 0 clear transfer complete interrupt flag */
+#define DMA_LIFCR_CHTIF0_Pos     (4U)
+#define DMA_LIFCR_CHTIF0_Msk     (0x1UL << DMA_LIFCR_CHTIF0_Pos)               /*!< 0x00000010 */
+#define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk                          /*!<  Stream 0 clear half transfer interrupt flag */
+#define DMA_LIFCR_CTEIF0_Pos     (3U)
+#define DMA_LIFCR_CTEIF0_Msk     (0x1UL << DMA_LIFCR_CTEIF0_Pos)               /*!< 0x00000008 */
+#define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk                          /*!<  Stream 0 clear transfer error interrupt flag */
+#define DMA_LIFCR_CDMEIF0_Pos    (2U)
+#define DMA_LIFCR_CDMEIF0_Msk    (0x1UL << DMA_LIFCR_CDMEIF0_Pos)              /*!< 0x00000004 */
+#define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk                         /*!<  Stream 0 clear direct mode error interrupt flag */
+#define DMA_LIFCR_CFEIF0_Pos     (0U)
+#define DMA_LIFCR_CFEIF0_Msk     (0x1UL << DMA_LIFCR_CFEIF0_Pos)               /*!< 0x00000001 */
+#define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk                          /*!<  Stream 0 clear FIFO error interrupt flag */
+
+/********************  Bits definition for DMA_HIFCR  register  ****************/
+#define DMA_HIFCR_CTCIF7_Pos     (27U)
+#define DMA_HIFCR_CTCIF7_Msk     (0x1UL << DMA_HIFCR_CTCIF7_Pos)               /*!< 0x08000000 */
+#define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk                          /*!<  Stream 7 clear transfer complete interrupt flag */
+#define DMA_HIFCR_CHTIF7_Pos     (26U)
+#define DMA_HIFCR_CHTIF7_Msk     (0x1UL << DMA_HIFCR_CHTIF7_Pos)               /*!< 0x04000000 */
+#define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk                          /*!<  Stream 7 clear half transfer interrupt flag */
+#define DMA_HIFCR_CTEIF7_Pos     (25U)
+#define DMA_HIFCR_CTEIF7_Msk     (0x1UL << DMA_HIFCR_CTEIF7_Pos)               /*!< 0x02000000 */
+#define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk                          /*!<  Stream 7 clear transfer error interrupt flag */
+#define DMA_HIFCR_CDMEIF7_Pos    (24U)
+#define DMA_HIFCR_CDMEIF7_Msk    (0x1UL << DMA_HIFCR_CDMEIF7_Pos)              /*!< 0x01000000 */
+#define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk                         /*!<  Stream 7 clear direct mode error interrupt flag */
+#define DMA_HIFCR_CFEIF7_Pos     (22U)
+#define DMA_HIFCR_CFEIF7_Msk     (0x1UL << DMA_HIFCR_CFEIF7_Pos)               /*!< 0x00400000 */
+#define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk                          /*!<  Stream 7 clear FIFO error interrupt flag */
+#define DMA_HIFCR_CTCIF6_Pos     (21U)
+#define DMA_HIFCR_CTCIF6_Msk     (0x1UL << DMA_HIFCR_CTCIF6_Pos)               /*!< 0x00200000 */
+#define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk                          /*!<  Stream 6 clear transfer complete interrupt flag */
+#define DMA_HIFCR_CHTIF6_Pos     (20U)
+#define DMA_HIFCR_CHTIF6_Msk     (0x1UL << DMA_HIFCR_CHTIF6_Pos)               /*!< 0x00100000 */
+#define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk                          /*!<  Stream 6 clear half transfer interrupt flag */
+#define DMA_HIFCR_CTEIF6_Pos     (19U)
+#define DMA_HIFCR_CTEIF6_Msk     (0x1UL << DMA_HIFCR_CTEIF6_Pos)               /*!< 0x00080000 */
+#define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk                          /*!<  Stream 6 clear transfer error interrupt flag */
+#define DMA_HIFCR_CDMEIF6_Pos    (18U)
+#define DMA_HIFCR_CDMEIF6_Msk    (0x1UL << DMA_HIFCR_CDMEIF6_Pos)              /*!< 0x00040000 */
+#define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk                         /*!<  Stream 6 clear direct mode error interrupt flag */
+#define DMA_HIFCR_CFEIF6_Pos     (16U)
+#define DMA_HIFCR_CFEIF6_Msk     (0x1UL << DMA_HIFCR_CFEIF6_Pos)               /*!< 0x00010000 */
+#define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk                          /*!<  Stream 6 clear FIFO error interrupt flag */
+#define DMA_HIFCR_CTCIF5_Pos     (11U)
+#define DMA_HIFCR_CTCIF5_Msk     (0x1UL << DMA_HIFCR_CTCIF5_Pos)               /*!< 0x00000800 */
+#define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk                          /*!<  Stream 5 clear transfer complete interrupt flag */
+#define DMA_HIFCR_CHTIF5_Pos     (10U)
+#define DMA_HIFCR_CHTIF5_Msk     (0x1UL << DMA_HIFCR_CHTIF5_Pos)               /*!< 0x00000400 */
+#define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk                          /*!<  Stream 5 clear half transfer interrupt flag */
+#define DMA_HIFCR_CTEIF5_Pos     (9U)
+#define DMA_HIFCR_CTEIF5_Msk     (0x1UL << DMA_HIFCR_CTEIF5_Pos)               /*!< 0x00000200 */
+#define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk                          /*!<  Stream 5 clear transfer error interrupt flag */
+#define DMA_HIFCR_CDMEIF5_Pos    (8U)
+#define DMA_HIFCR_CDMEIF5_Msk    (0x1UL << DMA_HIFCR_CDMEIF5_Pos)              /*!< 0x00000100 */
+#define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk                         /*!<  Stream 5 clear direct mode error interrupt flag */
+#define DMA_HIFCR_CFEIF5_Pos     (6U)
+#define DMA_HIFCR_CFEIF5_Msk     (0x1UL << DMA_HIFCR_CFEIF5_Pos)               /*!< 0x00000040 */
+#define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk                          /*!<  Stream 5 clear FIFO error interrupt flag */
+#define DMA_HIFCR_CTCIF4_Pos     (5U)
+#define DMA_HIFCR_CTCIF4_Msk     (0x1UL << DMA_HIFCR_CTCIF4_Pos)               /*!< 0x00000020 */
+#define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk                          /*!<  Stream 4 clear transfer complete interrupt flag */
+#define DMA_HIFCR_CHTIF4_Pos     (4U)
+#define DMA_HIFCR_CHTIF4_Msk     (0x1UL << DMA_HIFCR_CHTIF4_Pos)               /*!< 0x00000010 */
+#define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk                          /*!<  Stream 4 clear half transfer interrupt flag */
+#define DMA_HIFCR_CTEIF4_Pos     (3U)
+#define DMA_HIFCR_CTEIF4_Msk     (0x1UL << DMA_HIFCR_CTEIF4_Pos)               /*!< 0x00000008 */
+#define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk                          /*!<  Stream 4 clear transfer error interrupt flag */
+#define DMA_HIFCR_CDMEIF4_Pos    (2U)
+#define DMA_HIFCR_CDMEIF4_Msk    (0x1UL << DMA_HIFCR_CDMEIF4_Pos)              /*!< 0x00000004 */
+#define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk                         /*!<  Stream 4 clear direct mode error interrupt flag */
+#define DMA_HIFCR_CFEIF4_Pos     (0U)
+#define DMA_HIFCR_CFEIF4_Msk     (0x1UL << DMA_HIFCR_CFEIF4_Pos)               /*!< 0x00000001 */
+#define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk                          /*!<  Stream 4 clear FIFO error interrupt flag */
+
+/******************  Bit definition for DMA_SxPAR register  ********************/
+#define DMA_SxPAR_PA_Pos         (0U)
+#define DMA_SxPAR_PA_Msk         (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)            /*!< 0xFFFFFFFF */
+#define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_SxM0AR register  ********************/
+#define DMA_SxM0AR_M0A_Pos       (0U)
+#define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)          /*!< 0xFFFFFFFF */
+#define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory 0 Address */
+
+/******************  Bit definition for DMA_SxM1AR register  ********************/
+#define DMA_SxM1AR_M1A_Pos       (0U)
+#define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)          /*!< 0xFFFFFFFF */
+#define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory 1 Address */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             DMAMUX Controller                              */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for DMAMUX_CxCR register  **************/
+#define DMAMUX_CxCR_DMAREQ_ID_Pos      (0U)
+#define DMAMUX_CxCR_DMAREQ_ID_Msk      (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)   /*!< 0x000000FF */
+#define DMAMUX_CxCR_DMAREQ_ID          DMAMUX_CxCR_DMAREQ_ID_Msk               /*!<  DMA request identification */
+#define DMAMUX_CxCR_DMAREQ_ID_0        (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000001 */
+#define DMAMUX_CxCR_DMAREQ_ID_1        (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000002 */
+#define DMAMUX_CxCR_DMAREQ_ID_2        (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000004 */
+#define DMAMUX_CxCR_DMAREQ_ID_3        (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000008 */
+#define DMAMUX_CxCR_DMAREQ_ID_4        (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000010 */
+#define DMAMUX_CxCR_DMAREQ_ID_5        (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000020 */
+#define DMAMUX_CxCR_DMAREQ_ID_6        (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000040 */
+#define DMAMUX_CxCR_DMAREQ_ID_7        (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000080 */
+#define DMAMUX_CxCR_SOIE_Pos           (8U)
+#define DMAMUX_CxCR_SOIE_Msk           (0x1UL << DMAMUX_CxCR_SOIE_Pos)         /*!< 0x00000100 */
+#define DMAMUX_CxCR_SOIE               DMAMUX_CxCR_SOIE_Msk                    /*!<  Synchronization overrun interrupt enable */
+#define DMAMUX_CxCR_EGE_Pos            (9U)
+#define DMAMUX_CxCR_EGE_Msk            (0x1UL << DMAMUX_CxCR_EGE_Pos)          /*!< 0x00000200 */
+#define DMAMUX_CxCR_EGE                DMAMUX_CxCR_EGE_Msk                     /*!<  Event generation enable */
+#define DMAMUX_CxCR_SE_Pos             (16U)
+#define DMAMUX_CxCR_SE_Msk             (0x1UL << DMAMUX_CxCR_SE_Pos)           /*!< 0x00010000 */
+#define DMAMUX_CxCR_SE                 DMAMUX_CxCR_SE_Msk                      /*!<  Synchronization enable */
+#define DMAMUX_CxCR_SPOL_Pos           (17U)
+#define DMAMUX_CxCR_SPOL_Msk           (0x3UL << DMAMUX_CxCR_SPOL_Pos)         /*!< 0x00060000 */
+#define DMAMUX_CxCR_SPOL               DMAMUX_CxCR_SPOL_Msk                    /*!<  Synchronization polarity */
+#define DMAMUX_CxCR_SPOL_0             (0x1UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00020000 */
+#define DMAMUX_CxCR_SPOL_1             (0x2UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00040000 */
+#define DMAMUX_CxCR_NBREQ_Pos          (19U)
+#define DMAMUX_CxCR_NBREQ_Msk          (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)       /*!< 0x00F80000 */
+#define DMAMUX_CxCR_NBREQ              DMAMUX_CxCR_NBREQ_Msk                   /*!<  Number of DMA requests minus 1 to forward */
+#define DMAMUX_CxCR_NBREQ_0            (0x01UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00080000 */
+#define DMAMUX_CxCR_NBREQ_1            (0x02UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00100000 */
+#define DMAMUX_CxCR_NBREQ_2            (0x04UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00200000 */
+#define DMAMUX_CxCR_NBREQ_3            (0x08UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00400000 */
+#define DMAMUX_CxCR_NBREQ_4            (0x10UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00800000 */
+#define DMAMUX_CxCR_SYNC_ID_Pos        (24U)
+#define DMAMUX_CxCR_SYNC_ID_Msk        (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)     /*!< 0x1F000000 */
+#define DMAMUX_CxCR_SYNC_ID            DMAMUX_CxCR_SYNC_ID_Msk                 /*!<  Synchronization identification */
+#define DMAMUX_CxCR_SYNC_ID_0          (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x01000000 */
+#define DMAMUX_CxCR_SYNC_ID_1          (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x02000000 */
+#define DMAMUX_CxCR_SYNC_ID_2          (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x04000000 */
+#define DMAMUX_CxCR_SYNC_ID_3          (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x08000000 */
+#define DMAMUX_CxCR_SYNC_ID_4          (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x10000000 */
+
+/********************  Bits definition for DMAMUX_CSR register  **************/
+#define DMAMUX_CSR_SOF0_Pos            (0U)
+#define DMAMUX_CSR_SOF0_Msk            (0x1UL << DMAMUX_CSR_SOF0_Pos)          /*!< 0x00000001 */
+#define DMAMUX_CSR_SOF0                DMAMUX_CSR_SOF0_Msk                     /*!< Channel 0 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF1_Pos            (1U)
+#define DMAMUX_CSR_SOF1_Msk            (0x1UL << DMAMUX_CSR_SOF1_Pos)          /*!< 0x00000002 */
+#define DMAMUX_CSR_SOF1                DMAMUX_CSR_SOF1_Msk                     /*!< Channel 1 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF2_Pos            (2U)
+#define DMAMUX_CSR_SOF2_Msk            (0x1UL << DMAMUX_CSR_SOF2_Pos)          /*!< 0x00000004 */
+#define DMAMUX_CSR_SOF2                DMAMUX_CSR_SOF2_Msk                     /*!< Channel 2 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF3_Pos            (3U)
+#define DMAMUX_CSR_SOF3_Msk            (0x1UL << DMAMUX_CSR_SOF3_Pos)          /*!< 0x00000008 */
+#define DMAMUX_CSR_SOF3                DMAMUX_CSR_SOF3_Msk                     /*!< Channel 3 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF4_Pos            (4U)
+#define DMAMUX_CSR_SOF4_Msk            (0x1UL << DMAMUX_CSR_SOF4_Pos)          /*!< 0x00000010 */
+#define DMAMUX_CSR_SOF4                DMAMUX_CSR_SOF4_Msk                     /*!< Channel 4 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF5_Pos            (5U)
+#define DMAMUX_CSR_SOF5_Msk            (0x1UL << DMAMUX_CSR_SOF5_Pos)          /*!< 0x00000020 */
+#define DMAMUX_CSR_SOF5                DMAMUX_CSR_SOF5_Msk                     /*!< Channel 5 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF6_Pos            (6U)
+#define DMAMUX_CSR_SOF6_Msk            (0x1UL << DMAMUX_CSR_SOF6_Pos)          /*!< 0x00000040 */
+#define DMAMUX_CSR_SOF6                DMAMUX_CSR_SOF6_Msk                     /*!< Channel 6 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF7_Pos            (7U)
+#define DMAMUX_CSR_SOF7_Msk            (0x1UL << DMAMUX_CSR_SOF7_Pos)          /*!< 0x00000080 */
+#define DMAMUX_CSR_SOF7                DMAMUX_CSR_SOF7_Msk                     /*!< Channel 7 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF8_Pos            (8U)
+#define DMAMUX_CSR_SOF8_Msk            (0x1UL << DMAMUX_CSR_SOF8_Pos)          /*!< 0x00000100 */
+#define DMAMUX_CSR_SOF8                DMAMUX_CSR_SOF8_Msk                     /*!< Channel 8 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF9_Pos            (9U)
+#define DMAMUX_CSR_SOF9_Msk            (0x1UL << DMAMUX_CSR_SOF9_Pos)          /*!< 0x00000200 */
+#define DMAMUX_CSR_SOF9                DMAMUX_CSR_SOF9_Msk                     /*!< Channel 9 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF10_Pos           (10U)
+#define DMAMUX_CSR_SOF10_Msk           (0x1UL << DMAMUX_CSR_SOF10_Pos)         /*!< 0x00000400 */
+#define DMAMUX_CSR_SOF10               DMAMUX_CSR_SOF10_Msk                    /*!< Channel 10 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF11_Pos           (11U)
+#define DMAMUX_CSR_SOF11_Msk           (0x1UL << DMAMUX_CSR_SOF11_Pos)         /*!< 0x00000800 */
+#define DMAMUX_CSR_SOF11               DMAMUX_CSR_SOF11_Msk                    /*!< Channel 11 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF12_Pos           (12U)
+#define DMAMUX_CSR_SOF12_Msk           (0x1UL << DMAMUX_CSR_SOF12_Pos)         /*!< 0x00001000 */
+#define DMAMUX_CSR_SOF12               DMAMUX_CSR_SOF12_Msk                    /*!< Channel 12 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF13_Pos           (13U)
+#define DMAMUX_CSR_SOF13_Msk           (0x1UL << DMAMUX_CSR_SOF13_Pos)         /*!< 0x00002000 */
+#define DMAMUX_CSR_SOF13               DMAMUX_CSR_SOF13_Msk                    /*!< Channel 13 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF14_Pos           (14U)
+#define DMAMUX_CSR_SOF14_Msk           (0x1UL << DMAMUX_CSR_SOF14_Pos)         /*!< 0x00004000 */
+#define DMAMUX_CSR_SOF14               DMAMUX_CSR_SOF14_Msk                    /*!< Channel 14 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF15_Pos           (15U)
+#define DMAMUX_CSR_SOF15_Msk           (0x1UL << DMAMUX_CSR_SOF15_Pos)         /*!< 0x00008000 */
+#define DMAMUX_CSR_SOF15               DMAMUX_CSR_SOF15_Msk                    /*!< Channel 15 Synchronization overrun event flag */
+
+/********************  Bits definition for DMAMUX_CFR register  **************/
+#define DMAMUX_CFR_CSOF0_Pos           (0U)
+#define DMAMUX_CFR_CSOF0_Msk           (0x1UL << DMAMUX_CFR_CSOF0_Pos)         /*!< 0x00000001 */
+#define DMAMUX_CFR_CSOF0               DMAMUX_CFR_CSOF0_Msk                    /*!< Channel 0 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF1_Pos           (1U)
+#define DMAMUX_CFR_CSOF1_Msk           (0x1UL << DMAMUX_CFR_CSOF1_Pos)         /*!< 0x00000002 */
+#define DMAMUX_CFR_CSOF1               DMAMUX_CFR_CSOF1_Msk                    /*!< Channel 1 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF2_Pos           (2U)
+#define DMAMUX_CFR_CSOF2_Msk           (0x1UL << DMAMUX_CFR_CSOF2_Pos)         /*!< 0x00000004 */
+#define DMAMUX_CFR_CSOF2               DMAMUX_CFR_CSOF2_Msk                    /*!< Channel 2 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF3_Pos           (3U)
+#define DMAMUX_CFR_CSOF3_Msk           (0x1UL << DMAMUX_CFR_CSOF3_Pos)         /*!< 0x00000008 */
+#define DMAMUX_CFR_CSOF3               DMAMUX_CFR_CSOF3_Msk                    /*!< Channel 3 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF4_Pos           (4U)
+#define DMAMUX_CFR_CSOF4_Msk           (0x1UL << DMAMUX_CFR_CSOF4_Pos)         /*!< 0x00000010 */
+#define DMAMUX_CFR_CSOF4               DMAMUX_CFR_CSOF4_Msk                    /*!< Channel 4 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF5_Pos           (5U)
+#define DMAMUX_CFR_CSOF5_Msk           (0x1UL << DMAMUX_CFR_CSOF5_Pos)         /*!< 0x00000020 */
+#define DMAMUX_CFR_CSOF5               DMAMUX_CFR_CSOF5_Msk                    /*!< Channel 5 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF6_Pos           (6U)
+#define DMAMUX_CFR_CSOF6_Msk           (0x1UL << DMAMUX_CFR_CSOF6_Pos)         /*!< 0x00000040 */
+#define DMAMUX_CFR_CSOF6               DMAMUX_CFR_CSOF6_Msk                    /*!< Channel 6 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF7_Pos           (7U)
+#define DMAMUX_CFR_CSOF7_Msk           (0x1UL << DMAMUX_CFR_CSOF7_Pos)         /*!< 0x00000080 */
+#define DMAMUX_CFR_CSOF7               DMAMUX_CFR_CSOF7_Msk                    /*!< Channel 7 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF8_Pos           (8U)
+#define DMAMUX_CFR_CSOF8_Msk           (0x1UL << DMAMUX_CFR_CSOF8_Pos)         /*!< 0x00000100 */
+#define DMAMUX_CFR_CSOF8               DMAMUX_CFR_CSOF8_Msk                    /*!< Channel 8 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF9_Pos           (9U)
+#define DMAMUX_CFR_CSOF9_Msk           (0x1UL << DMAMUX_CFR_CSOF9_Pos)         /*!< 0x00000200 */
+#define DMAMUX_CFR_CSOF9               DMAMUX_CFR_CSOF9_Msk                    /*!< Channel 9 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF10_Pos          (10U)
+#define DMAMUX_CFR_CSOF10_Msk          (0x1UL << DMAMUX_CFR_CSOF10_Pos)        /*!< 0x00000400 */
+#define DMAMUX_CFR_CSOF10              DMAMUX_CFR_CSOF10_Msk                   /*!< Channel 10 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF11_Pos          (11U)
+#define DMAMUX_CFR_CSOF11_Msk          (0x1UL << DMAMUX_CFR_CSOF11_Pos)        /*!< 0x00000800 */
+#define DMAMUX_CFR_CSOF11              DMAMUX_CFR_CSOF11_Msk                   /*!< Channel 11 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF12_Pos          (12U)
+#define DMAMUX_CFR_CSOF12_Msk          (0x1UL << DMAMUX_CFR_CSOF12_Pos)        /*!< 0x00001000 */
+#define DMAMUX_CFR_CSOF12              DMAMUX_CFR_CSOF12_Msk                   /*!< Channel 12 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF13_Pos          (13U)
+#define DMAMUX_CFR_CSOF13_Msk          (0x1UL << DMAMUX_CFR_CSOF13_Pos)        /*!< 0x00002000 */
+#define DMAMUX_CFR_CSOF13              DMAMUX_CFR_CSOF13_Msk                   /*!< Channel 13 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF14_Pos          (14U)
+#define DMAMUX_CFR_CSOF14_Msk          (0x1UL << DMAMUX_CFR_CSOF14_Pos)        /*!< 0x00004000 */
+#define DMAMUX_CFR_CSOF14              DMAMUX_CFR_CSOF14_Msk                   /*!< Channel 14 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF15_Pos          (15U)
+#define DMAMUX_CFR_CSOF15_Msk          (0x1UL << DMAMUX_CFR_CSOF15_Pos)        /*!< 0x00008000 */
+#define DMAMUX_CFR_CSOF15              DMAMUX_CFR_CSOF15_Msk                   /*!< Channel 15 Clear synchronization overrun event flag */
+
+/********************  Bits definition for DMAMUX_RGxCR register  ************/
+#define DMAMUX_RGxCR_SIG_ID_Pos        (0U)
+#define DMAMUX_RGxCR_SIG_ID_Msk        (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)     /*!< 0x0000001F */
+#define DMAMUX_RGxCR_SIG_ID            DMAMUX_RGxCR_SIG_ID_Msk                 /*!< Signal identification */
+#define DMAMUX_RGxCR_SIG_ID_0          (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000001 */
+#define DMAMUX_RGxCR_SIG_ID_1          (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000002 */
+#define DMAMUX_RGxCR_SIG_ID_2          (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000004 */
+#define DMAMUX_RGxCR_SIG_ID_3          (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000008 */
+#define DMAMUX_RGxCR_SIG_ID_4          (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000010 */
+#define DMAMUX_RGxCR_OIE_Pos           (8U)
+#define DMAMUX_RGxCR_OIE_Msk           (0x1UL << DMAMUX_RGxCR_OIE_Pos)         /*!< 0x00000100 */
+#define DMAMUX_RGxCR_OIE               DMAMUX_RGxCR_OIE_Msk                    /*!< Trigger overrun interrupt enable */
+#define DMAMUX_RGxCR_GE_Pos            (16U)
+#define DMAMUX_RGxCR_GE_Msk            (0x1UL << DMAMUX_RGxCR_GE_Pos)          /*!< 0x00010000 */
+#define DMAMUX_RGxCR_GE                DMAMUX_RGxCR_GE_Msk                     /*!< DMA request generator enable */
+#define DMAMUX_RGxCR_GPOL_Pos          (17U)
+#define DMAMUX_RGxCR_GPOL_Msk          (0x3UL << DMAMUX_RGxCR_GPOL_Pos)        /*!< 0x00060000 */
+#define DMAMUX_RGxCR_GPOL              DMAMUX_RGxCR_GPOL_Msk                   /*!< DMA request generator trigger polarity */
+#define DMAMUX_RGxCR_GPOL_0            (0x1UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00020000 */
+#define DMAMUX_RGxCR_GPOL_1            (0x2UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00040000 */
+#define DMAMUX_RGxCR_GNBREQ_Pos        (19U)
+#define DMAMUX_RGxCR_GNBREQ_Msk        (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)     /*!< 0x00F80000 */
+#define DMAMUX_RGxCR_GNBREQ            DMAMUX_RGxCR_GNBREQ_Msk                 /*!< Number of DMA requests to be generated */
+#define DMAMUX_RGxCR_GNBREQ_0          (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00080000 */
+#define DMAMUX_RGxCR_GNBREQ_1          (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00100000 */
+#define DMAMUX_RGxCR_GNBREQ_2          (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00200000 */
+#define DMAMUX_RGxCR_GNBREQ_3          (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00400000 */
+#define DMAMUX_RGxCR_GNBREQ_4          (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00800000 */
+
+/********************  Bits definition for DMAMUX_RGSR register  **************/
+#define DMAMUX_RGSR_OF0_Pos            (0U)
+#define DMAMUX_RGSR_OF0_Msk            (0x1UL << DMAMUX_RGSR_OF0_Pos)          /*!< 0x00000001 */
+#define DMAMUX_RGSR_OF0                DMAMUX_RGSR_OF0_Msk                     /*!< Request generator channel 0 Trigger overrun event flag */
+#define DMAMUX_RGSR_OF1_Pos            (1U)
+#define DMAMUX_RGSR_OF1_Msk            (0x1UL << DMAMUX_RGSR_OF1_Pos)          /*!< 0x00000002 */
+#define DMAMUX_RGSR_OF1                DMAMUX_RGSR_OF1_Msk                     /*!< Request generator channel 1 Trigger overrun event flag */
+#define DMAMUX_RGSR_OF2_Pos            (2U)
+#define DMAMUX_RGSR_OF2_Msk            (0x1UL << DMAMUX_RGSR_OF2_Pos)          /*!< 0x00000004 */
+#define DMAMUX_RGSR_OF2                DMAMUX_RGSR_OF2_Msk                     /*!< Request generator channel 2 Trigger overrun event flag */
+#define DMAMUX_RGSR_OF3_Pos            (3U)
+#define DMAMUX_RGSR_OF3_Msk            (0x1UL << DMAMUX_RGSR_OF3_Pos)          /*!< 0x00000008 */
+#define DMAMUX_RGSR_OF3                DMAMUX_RGSR_OF3_Msk                     /*!< Request generator channel 3 Trigger overrun event flag */
+#define DMAMUX_RGSR_OF4_Pos            (4U)
+#define DMAMUX_RGSR_OF4_Msk            (0x1UL << DMAMUX_RGSR_OF4_Pos)          /*!< 0x00000010 */
+#define DMAMUX_RGSR_OF4                DMAMUX_RGSR_OF4_Msk                     /*!< Request generator channel 4 Trigger overrun event flag */
+#define DMAMUX_RGSR_OF5_Pos            (5U)
+#define DMAMUX_RGSR_OF5_Msk            (0x1UL << DMAMUX_RGSR_OF5_Pos)          /*!< 0x00000020 */
+#define DMAMUX_RGSR_OF5                DMAMUX_RGSR_OF5_Msk                     /*!< Request generator channel 5 Trigger overrun event flag */
+#define DMAMUX_RGSR_OF6_Pos            (6U)
+#define DMAMUX_RGSR_OF6_Msk            (0x1UL << DMAMUX_RGSR_OF6_Pos)          /*!< 0x00000040 */
+#define DMAMUX_RGSR_OF6                DMAMUX_RGSR_OF6_Msk                     /*!< Request generator channel 6 Trigger overrun event flag */
+#define DMAMUX_RGSR_OF7_Pos            (7U)
+#define DMAMUX_RGSR_OF7_Msk            (0x1UL << DMAMUX_RGSR_OF7_Pos)          /*!< 0x00000080 */
+#define DMAMUX_RGSR_OF7                DMAMUX_RGSR_OF7_Msk                     /*!< Request generator channel 7 Trigger overrun event flag */
+
+/********************  Bits definition for DMAMUX_RGCFR register  **************/
+#define DMAMUX_RGCFR_COF0_Pos          (0U)
+#define DMAMUX_RGCFR_COF0_Msk          (0x1UL << DMAMUX_RGCFR_COF0_Pos)        /*!< 0x00000001 */
+#define DMAMUX_RGCFR_COF0              DMAMUX_RGCFR_COF0_Msk                   /*!< Request generator channel 0 Clear trigger overrun event flag */
+#define DMAMUX_RGCFR_COF1_Pos          (1U)
+#define DMAMUX_RGCFR_COF1_Msk          (0x1UL << DMAMUX_RGCFR_COF1_Pos)        /*!< 0x00000002 */
+#define DMAMUX_RGCFR_COF1              DMAMUX_RGCFR_COF1_Msk                   /*!< Request generator channel 1 Clear trigger overrun event flag */
+#define DMAMUX_RGCFR_COF2_Pos          (2U)
+#define DMAMUX_RGCFR_COF2_Msk          (0x1UL << DMAMUX_RGCFR_COF2_Pos)        /*!< 0x00000004 */
+#define DMAMUX_RGCFR_COF2              DMAMUX_RGCFR_COF2_Msk                   /*!< Request generator channel 2 Clear trigger overrun event flag */
+#define DMAMUX_RGCFR_COF3_Pos          (3U)
+#define DMAMUX_RGCFR_COF3_Msk          (0x1UL << DMAMUX_RGCFR_COF3_Pos)        /*!< 0x00000008 */
+#define DMAMUX_RGCFR_COF3              DMAMUX_RGCFR_COF3_Msk                   /*!< Request generator channel 3 Clear trigger overrun event flag */
+#define DMAMUX_RGCFR_COF4_Pos          (4U)
+#define DMAMUX_RGCFR_COF4_Msk          (0x1UL << DMAMUX_RGCFR_COF4_Pos)        /*!< 0x00000010 */
+#define DMAMUX_RGCFR_COF4              DMAMUX_RGCFR_COF4_Msk                   /*!< Request generator channel 4 Clear trigger overrun event flag */
+#define DMAMUX_RGCFR_COF5_Pos          (5U)
+#define DMAMUX_RGCFR_COF5_Msk          (0x1UL << DMAMUX_RGCFR_COF5_Pos)        /*!< 0x00000020 */
+#define DMAMUX_RGCFR_COF5              DMAMUX_RGCFR_COF5_Msk                   /*!< Request generator channel 5 Clear trigger overrun event flag */
+#define DMAMUX_RGCFR_COF6_Pos          (6U)
+#define DMAMUX_RGCFR_COF6_Msk          (0x1UL << DMAMUX_RGCFR_COF6_Pos)        /*!< 0x00000040 */
+#define DMAMUX_RGCFR_COF6              DMAMUX_RGCFR_COF6_Msk                   /*!< Request generator channel 6 Clear trigger overrun event flag */
+#define DMAMUX_RGCFR_COF7_Pos          (7U)
+#define DMAMUX_RGCFR_COF7_Msk          (0x1UL << DMAMUX_RGCFR_COF7_Pos)        /*!< 0x00000080 */
+#define DMAMUX_RGCFR_COF7              DMAMUX_RGCFR_COF7_Msk                   /*!< Request generator channel 7 Clear trigger overrun event flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         AHB Master DMA2D Controller (DMA2D)                */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for DMA2D_CR register  ******************/
+
+#define DMA2D_CR_START_Pos         (0U)
+#define DMA2D_CR_START_Msk         (0x1UL << DMA2D_CR_START_Pos)               /*!< 0x00000001 */
+#define DMA2D_CR_START             DMA2D_CR_START_Msk                          /*!< Start transfer                          */
+#define DMA2D_CR_SUSP_Pos          (1U)
+#define DMA2D_CR_SUSP_Msk          (0x1UL << DMA2D_CR_SUSP_Pos)                /*!< 0x00000002 */
+#define DMA2D_CR_SUSP              DMA2D_CR_SUSP_Msk                           /*!< Suspend transfer                        */
+#define DMA2D_CR_ABORT_Pos         (2U)
+#define DMA2D_CR_ABORT_Msk         (0x1UL << DMA2D_CR_ABORT_Pos)               /*!< 0x00000004 */
+#define DMA2D_CR_ABORT             DMA2D_CR_ABORT_Msk                          /*!< Abort transfer                          */
+#define DMA2D_CR_LOM_Pos           (6U)
+#define DMA2D_CR_LOM_Msk           (0x1UL << DMA2D_CR_LOM_Pos)                 /*!< 0x00000040 */
+#define DMA2D_CR_LOM               DMA2D_CR_LOM_Msk                            /*!< Line Offset Mode                         */
+#define DMA2D_CR_TEIE_Pos          (8U)
+#define DMA2D_CR_TEIE_Msk          (0x1UL << DMA2D_CR_TEIE_Pos)                /*!< 0x00000100 */
+#define DMA2D_CR_TEIE              DMA2D_CR_TEIE_Msk                           /*!< Transfer Error Interrupt Enable         */
+#define DMA2D_CR_TCIE_Pos          (9U)
+#define DMA2D_CR_TCIE_Msk          (0x1UL << DMA2D_CR_TCIE_Pos)                /*!< 0x00000200 */
+#define DMA2D_CR_TCIE              DMA2D_CR_TCIE_Msk                           /*!< Transfer Complete Interrupt Enable      */
+#define DMA2D_CR_TWIE_Pos          (10U)
+#define DMA2D_CR_TWIE_Msk          (0x1UL << DMA2D_CR_TWIE_Pos)                /*!< 0x00000400 */
+#define DMA2D_CR_TWIE              DMA2D_CR_TWIE_Msk                           /*!< Transfer Watermark Interrupt Enable     */
+#define DMA2D_CR_CAEIE_Pos         (11U)
+#define DMA2D_CR_CAEIE_Msk         (0x1UL << DMA2D_CR_CAEIE_Pos)               /*!< 0x00000800 */
+#define DMA2D_CR_CAEIE             DMA2D_CR_CAEIE_Msk                          /*!< CLUT Access Error Interrupt Enable      */
+#define DMA2D_CR_CTCIE_Pos         (12U)
+#define DMA2D_CR_CTCIE_Msk         (0x1UL << DMA2D_CR_CTCIE_Pos)               /*!< 0x00001000 */
+#define DMA2D_CR_CTCIE             DMA2D_CR_CTCIE_Msk                          /*!< CLUT Transfer Complete Interrupt Enable */
+#define DMA2D_CR_CEIE_Pos          (13U)
+#define DMA2D_CR_CEIE_Msk          (0x1UL << DMA2D_CR_CEIE_Pos)                /*!< 0x00002000 */
+#define DMA2D_CR_CEIE              DMA2D_CR_CEIE_Msk                           /*!< Configuration Error Interrupt Enable    */
+#define DMA2D_CR_MODE_Pos          (16U)
+#define DMA2D_CR_MODE_Msk          (0x7UL << DMA2D_CR_MODE_Pos)                /*!< 0x00070000 */
+#define DMA2D_CR_MODE              DMA2D_CR_MODE_Msk                           /*!< DMA2D Mode[2:0]                         */
+#define DMA2D_CR_MODE_0            (0x1UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00010000 */
+#define DMA2D_CR_MODE_1            (0x2UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00020000 */
+#define DMA2D_CR_MODE_2            (0x4UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00040000 */
+
+/********************  Bit definition for DMA2D_ISR register  *****************/
+
+#define DMA2D_ISR_TEIF_Pos         (0U)
+#define DMA2D_ISR_TEIF_Msk         (0x1UL << DMA2D_ISR_TEIF_Pos)               /*!< 0x00000001 */
+#define DMA2D_ISR_TEIF             DMA2D_ISR_TEIF_Msk                          /*!< Transfer Error Interrupt Flag         */
+#define DMA2D_ISR_TCIF_Pos         (1U)
+#define DMA2D_ISR_TCIF_Msk         (0x1UL << DMA2D_ISR_TCIF_Pos)               /*!< 0x00000002 */
+#define DMA2D_ISR_TCIF             DMA2D_ISR_TCIF_Msk                          /*!< Transfer Complete Interrupt Flag      */
+#define DMA2D_ISR_TWIF_Pos         (2U)
+#define DMA2D_ISR_TWIF_Msk         (0x1UL << DMA2D_ISR_TWIF_Pos)               /*!< 0x00000004 */
+#define DMA2D_ISR_TWIF             DMA2D_ISR_TWIF_Msk                          /*!< Transfer Watermark Interrupt Flag     */
+#define DMA2D_ISR_CAEIF_Pos        (3U)
+#define DMA2D_ISR_CAEIF_Msk        (0x1UL << DMA2D_ISR_CAEIF_Pos)              /*!< 0x00000008 */
+#define DMA2D_ISR_CAEIF            DMA2D_ISR_CAEIF_Msk                         /*!< CLUT Access Error Interrupt Flag      */
+#define DMA2D_ISR_CTCIF_Pos        (4U)
+#define DMA2D_ISR_CTCIF_Msk        (0x1UL << DMA2D_ISR_CTCIF_Pos)              /*!< 0x00000010 */
+#define DMA2D_ISR_CTCIF            DMA2D_ISR_CTCIF_Msk                         /*!< CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_CEIF_Pos         (5U)
+#define DMA2D_ISR_CEIF_Msk         (0x1UL << DMA2D_ISR_CEIF_Pos)               /*!< 0x00000020 */
+#define DMA2D_ISR_CEIF             DMA2D_ISR_CEIF_Msk                          /*!< Configuration Error Interrupt Flag    */
+
+/********************  Bit definition for DMA2D_IFCR register  ****************/
+
+#define DMA2D_IFCR_CTEIF_Pos       (0U)
+#define DMA2D_IFCR_CTEIF_Msk       (0x1UL << DMA2D_IFCR_CTEIF_Pos)             /*!< 0x00000001 */
+#define DMA2D_IFCR_CTEIF           DMA2D_IFCR_CTEIF_Msk                        /*!< Clears Transfer Error Interrupt Flag         */
+#define DMA2D_IFCR_CTCIF_Pos       (1U)
+#define DMA2D_IFCR_CTCIF_Msk       (0x1UL << DMA2D_IFCR_CTCIF_Pos)             /*!< 0x00000002 */
+#define DMA2D_IFCR_CTCIF           DMA2D_IFCR_CTCIF_Msk                        /*!< Clears Transfer Complete Interrupt Flag      */
+#define DMA2D_IFCR_CTWIF_Pos       (2U)
+#define DMA2D_IFCR_CTWIF_Msk       (0x1UL << DMA2D_IFCR_CTWIF_Pos)             /*!< 0x00000004 */
+#define DMA2D_IFCR_CTWIF           DMA2D_IFCR_CTWIF_Msk                        /*!< Clears Transfer Watermark Interrupt Flag     */
+#define DMA2D_IFCR_CAECIF_Pos      (3U)
+#define DMA2D_IFCR_CAECIF_Msk      (0x1UL << DMA2D_IFCR_CAECIF_Pos)            /*!< 0x00000008 */
+#define DMA2D_IFCR_CAECIF          DMA2D_IFCR_CAECIF_Msk                       /*!< Clears CLUT Access Error Interrupt Flag      */
+#define DMA2D_IFCR_CCTCIF_Pos      (4U)
+#define DMA2D_IFCR_CCTCIF_Msk      (0x1UL << DMA2D_IFCR_CCTCIF_Pos)            /*!< 0x00000010 */
+#define DMA2D_IFCR_CCTCIF          DMA2D_IFCR_CCTCIF_Msk                       /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CCEIF_Pos       (5U)
+#define DMA2D_IFCR_CCEIF_Msk       (0x1UL << DMA2D_IFCR_CCEIF_Pos)             /*!< 0x00000020 */
+#define DMA2D_IFCR_CCEIF           DMA2D_IFCR_CCEIF_Msk                        /*!< Clears Configuration Error Interrupt Flag    */
+
+/********************  Bit definition for DMA2D_FGMAR register  ***************/
+
+#define DMA2D_FGMAR_MA_Pos         (0U)
+#define DMA2D_FGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)        /*!< 0xFFFFFFFF */
+#define DMA2D_FGMAR_MA             DMA2D_FGMAR_MA_Msk                          /*!< Foreground Memory Address */
+
+/********************  Bit definition for DMA2D_FGOR register  ****************/
+
+#define DMA2D_FGOR_LO_Pos          (0U)
+#define DMA2D_FGOR_LO_Msk          (0xFFFFUL << DMA2D_FGOR_LO_Pos)             /*!< 0x0000FFFF */
+#define DMA2D_FGOR_LO              DMA2D_FGOR_LO_Msk                           /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_BGMAR register  ***************/
+
+#define DMA2D_BGMAR_MA_Pos         (0U)
+#define DMA2D_BGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)        /*!< 0xFFFFFFFF */
+#define DMA2D_BGMAR_MA             DMA2D_BGMAR_MA_Msk                          /*!< Background Memory Address */
+
+/********************  Bit definition for DMA2D_BGOR register  ****************/
+
+#define DMA2D_BGOR_LO_Pos          (0U)
+#define DMA2D_BGOR_LO_Msk          (0xFFFFUL << DMA2D_BGOR_LO_Pos)             /*!< 0x0000FFFF */
+#define DMA2D_BGOR_LO              DMA2D_BGOR_LO_Msk                           /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_FGPFCCR register  *************/
+
+#define DMA2D_FGPFCCR_CM_Pos       (0U)
+#define DMA2D_FGPFCCR_CM_Msk       (0xFUL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x0000000F */
+#define DMA2D_FGPFCCR_CM           DMA2D_FGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */
+#define DMA2D_FGPFCCR_CM_0         (0x1UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000001 */
+#define DMA2D_FGPFCCR_CM_1         (0x2UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000002 */
+#define DMA2D_FGPFCCR_CM_2         (0x4UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000004 */
+#define DMA2D_FGPFCCR_CM_3         (0x8UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000008 */
+#define DMA2D_FGPFCCR_CCM_Pos      (4U)
+#define DMA2D_FGPFCCR_CCM_Msk      (0x1UL << DMA2D_FGPFCCR_CCM_Pos)            /*!< 0x00000010 */
+#define DMA2D_FGPFCCR_CCM          DMA2D_FGPFCCR_CCM_Msk                       /*!< CLUT Color mode */
+#define DMA2D_FGPFCCR_START_Pos    (5U)
+#define DMA2D_FGPFCCR_START_Msk    (0x1UL << DMA2D_FGPFCCR_START_Pos)          /*!< 0x00000020 */
+#define DMA2D_FGPFCCR_START        DMA2D_FGPFCCR_START_Msk                     /*!< Start */
+#define DMA2D_FGPFCCR_CS_Pos       (8U)
+#define DMA2D_FGPFCCR_CS_Msk       (0xFFUL << DMA2D_FGPFCCR_CS_Pos)            /*!< 0x0000FF00 */
+#define DMA2D_FGPFCCR_CS           DMA2D_FGPFCCR_CS_Msk                        /*!< CLUT size */
+#define DMA2D_FGPFCCR_AM_Pos       (16U)
+#define DMA2D_FGPFCCR_AM_Msk       (0x3UL << DMA2D_FGPFCCR_AM_Pos)             /*!< 0x00030000 */
+#define DMA2D_FGPFCCR_AM           DMA2D_FGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */
+#define DMA2D_FGPFCCR_AM_0         (0x1UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00010000 */
+#define DMA2D_FGPFCCR_AM_1         (0x2UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00020000 */
+#define DMA2D_FGPFCCR_CSS_Pos      (18U)
+#define DMA2D_FGPFCCR_CSS_Msk      (0x3UL << DMA2D_FGPFCCR_CSS_Pos)            /*!< 0x000C0000 */
+#define DMA2D_FGPFCCR_CSS          DMA2D_FGPFCCR_CSS_Msk                       /* !< Chroma Sub-Sampling */
+#define DMA2D_FGPFCCR_CSS_0        (0x1UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00040000 */
+#define DMA2D_FGPFCCR_CSS_1        (0x2UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00080000 */
+#define DMA2D_FGPFCCR_AI_Pos       (20U)
+#define DMA2D_FGPFCCR_AI_Msk       (0x1UL << DMA2D_FGPFCCR_AI_Pos)             /*!< 0x00100000 */
+#define DMA2D_FGPFCCR_AI           DMA2D_FGPFCCR_AI_Msk                        /*!< Foreground Input Alpha Inverted */
+#define DMA2D_FGPFCCR_RBS_Pos      (21U)
+#define DMA2D_FGPFCCR_RBS_Msk      (0x1UL << DMA2D_FGPFCCR_RBS_Pos)            /*!< 0x00200000 */
+#define DMA2D_FGPFCCR_RBS          DMA2D_FGPFCCR_RBS_Msk                       /*!< Foreground Input Red Blue Swap */
+#define DMA2D_FGPFCCR_ALPHA_Pos    (24U)
+#define DMA2D_FGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */
+#define DMA2D_FGPFCCR_ALPHA        DMA2D_FGPFCCR_ALPHA_Msk                     /*!< Alpha value */
+
+/********************  Bit definition for DMA2D_FGCOLR register  **************/
+
+#define DMA2D_FGCOLR_BLUE_Pos      (0U)
+#define DMA2D_FGCOLR_BLUE_Msk      (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)           /*!< 0x000000FF */
+#define DMA2D_FGCOLR_BLUE          DMA2D_FGCOLR_BLUE_Msk                       /*!< Foreground Blue Value */
+#define DMA2D_FGCOLR_GREEN_Pos     (8U)
+#define DMA2D_FGCOLR_GREEN_Msk     (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */
+#define DMA2D_FGCOLR_GREEN         DMA2D_FGCOLR_GREEN_Msk                      /*!< Foreground Green Value */
+#define DMA2D_FGCOLR_RED_Pos       (16U)
+#define DMA2D_FGCOLR_RED_Msk       (0xFFUL << DMA2D_FGCOLR_RED_Pos)            /*!< 0x00FF0000 */
+#define DMA2D_FGCOLR_RED           DMA2D_FGCOLR_RED_Msk                        /*!< Foreground Red Value */
+
+/********************  Bit definition for DMA2D_BGPFCCR register  *************/
+
+#define DMA2D_BGPFCCR_CM_Pos       (0U)
+#define DMA2D_BGPFCCR_CM_Msk       (0xFUL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x0000000F */
+#define DMA2D_BGPFCCR_CM           DMA2D_BGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */
+#define DMA2D_BGPFCCR_CM_0         (0x1UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000001 */
+#define DMA2D_BGPFCCR_CM_1         (0x2UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000002 */
+#define DMA2D_BGPFCCR_CM_2         (0x4UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000004 */
+#define DMA2D_BGPFCCR_CM_3         (0x8UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000008 */
+#define DMA2D_BGPFCCR_CCM_Pos      (4U)
+#define DMA2D_BGPFCCR_CCM_Msk      (0x1UL << DMA2D_BGPFCCR_CCM_Pos)            /*!< 0x00000010 */
+#define DMA2D_BGPFCCR_CCM          DMA2D_BGPFCCR_CCM_Msk                       /*!< CLUT Color mode */
+#define DMA2D_BGPFCCR_START_Pos    (5U)
+#define DMA2D_BGPFCCR_START_Msk    (0x1UL << DMA2D_BGPFCCR_START_Pos)          /*!< 0x00000020 */
+#define DMA2D_BGPFCCR_START        DMA2D_BGPFCCR_START_Msk                     /*!< Start */
+#define DMA2D_BGPFCCR_CS_Pos       (8U)
+#define DMA2D_BGPFCCR_CS_Msk       (0xFFUL << DMA2D_BGPFCCR_CS_Pos)            /*!< 0x0000FF00 */
+#define DMA2D_BGPFCCR_CS           DMA2D_BGPFCCR_CS_Msk                        /*!< CLUT size */
+#define DMA2D_BGPFCCR_AM_Pos       (16U)
+#define DMA2D_BGPFCCR_AM_Msk       (0x3UL << DMA2D_BGPFCCR_AM_Pos)             /*!< 0x00030000 */
+#define DMA2D_BGPFCCR_AM           DMA2D_BGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */
+#define DMA2D_BGPFCCR_AM_0         (0x1UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00010000 */
+#define DMA2D_BGPFCCR_AM_1         (0x2UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00020000 */
+#define DMA2D_BGPFCCR_AI_Pos       (20U)
+#define DMA2D_BGPFCCR_AI_Msk       (0x1UL << DMA2D_BGPFCCR_AI_Pos)             /*!< 0x00100000 */
+#define DMA2D_BGPFCCR_AI           DMA2D_BGPFCCR_AI_Msk                        /*!< background Input Alpha Inverted */
+#define DMA2D_BGPFCCR_RBS_Pos      (21U)
+#define DMA2D_BGPFCCR_RBS_Msk      (0x1UL << DMA2D_BGPFCCR_RBS_Pos)            /*!< 0x00200000 */
+#define DMA2D_BGPFCCR_RBS          DMA2D_BGPFCCR_RBS_Msk                       /*!< Background Input Red Blue Swap */
+#define DMA2D_BGPFCCR_ALPHA_Pos    (24U)
+#define DMA2D_BGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */
+#define DMA2D_BGPFCCR_ALPHA        DMA2D_BGPFCCR_ALPHA_Msk                     /*!< background Input Alpha value */
+
+/********************  Bit definition for DMA2D_BGCOLR register  **************/
+
+#define DMA2D_BGCOLR_BLUE_Pos      (0U)
+#define DMA2D_BGCOLR_BLUE_Msk      (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)           /*!< 0x000000FF */
+#define DMA2D_BGCOLR_BLUE          DMA2D_BGCOLR_BLUE_Msk                       /*!< Background Blue Value */
+#define DMA2D_BGCOLR_GREEN_Pos     (8U)
+#define DMA2D_BGCOLR_GREEN_Msk     (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */
+#define DMA2D_BGCOLR_GREEN         DMA2D_BGCOLR_GREEN_Msk                      /*!< Background Green Value */
+#define DMA2D_BGCOLR_RED_Pos       (16U)
+#define DMA2D_BGCOLR_RED_Msk       (0xFFUL << DMA2D_BGCOLR_RED_Pos)            /*!< 0x00FF0000 */
+#define DMA2D_BGCOLR_RED           DMA2D_BGCOLR_RED_Msk                        /*!< Background Red Value */
+
+/********************  Bit definition for DMA2D_FGCMAR register  **************/
+
+#define DMA2D_FGCMAR_MA_Pos        (0U)
+#define DMA2D_FGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */
+#define DMA2D_FGCMAR_MA            DMA2D_FGCMAR_MA_Msk                         /*!< Foreground CLUT Memory Address */
+
+/********************  Bit definition for DMA2D_BGCMAR register  **************/
+
+#define DMA2D_BGCMAR_MA_Pos        (0U)
+#define DMA2D_BGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */
+#define DMA2D_BGCMAR_MA            DMA2D_BGCMAR_MA_Msk                         /*!< Background CLUT Memory Address */
+
+/********************  Bit definition for DMA2D_OPFCCR register  **************/
+
+#define DMA2D_OPFCCR_CM_Pos        (0U)
+#define DMA2D_OPFCCR_CM_Msk        (0x7UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000007 */
+#define DMA2D_OPFCCR_CM            DMA2D_OPFCCR_CM_Msk                         /*!< Output Color mode CM[2:0] */
+#define DMA2D_OPFCCR_CM_0          (0x1UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000001 */
+#define DMA2D_OPFCCR_CM_1          (0x2UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000002 */
+#define DMA2D_OPFCCR_CM_2          (0x4UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000004 */
+#define DMA2D_OPFCCR_SB_Pos        (8U)
+#define DMA2D_OPFCCR_SB_Msk        (0x1UL << DMA2D_OPFCCR_SB_Pos)              /*!< 0x00000100 */
+#define DMA2D_OPFCCR_SB            DMA2D_OPFCCR_SB_Msk                         /*!< Swap Bytes */
+#define DMA2D_OPFCCR_AI_Pos        (20U)
+#define DMA2D_OPFCCR_AI_Msk        (0x1UL << DMA2D_OPFCCR_AI_Pos)              /*!< 0x00100000 */
+#define DMA2D_OPFCCR_AI            DMA2D_OPFCCR_AI_Msk                         /*!< Output Alpha Inverted */
+#define DMA2D_OPFCCR_RBS_Pos       (21U)
+#define DMA2D_OPFCCR_RBS_Msk       (0x1UL << DMA2D_OPFCCR_RBS_Pos)             /*!< 0x00200000 */
+#define DMA2D_OPFCCR_RBS           DMA2D_OPFCCR_RBS_Msk                        /*!< Output Red Blue Swap */
+
+/********************  Bit definition for DMA2D_OCOLR register  ***************/
+
+/*!<Mode_ARGB8888/RGB888 */
+
+#define DMA2D_OCOLR_BLUE_1_Pos     (0U)
+#define DMA2D_OCOLR_BLUE_1_Msk     (0xFFUL <<DMA2D_OCOLR_BLUE_1_Pos)            /*0x000000FFU*/
+#define DMA2D_OCOLR_BLUE_1         DMA2D_OCOLR_BLUE_1_Msk                      /*!< Output BLUE Value */
+#define DMA2D_OCOLR_GREEN_1_Pos    (8U)
+#define DMA2D_OCOLR_GREEN_1_Msk    (0xFFUL<<DMA2D_OCOLR_GREEN_1_Pos)            /*0x0000FF00U)*/
+#define DMA2D_OCOLR_GREEN_1        DMA2D_OCOLR_GREEN_1_Msk                     /*!< Output GREEN Value  */
+#define DMA2D_OCOLR_RED_1_Pos      (16U)
+#define DMA2D_OCOLR_RED_1_Msk      (0xFFUL << DMA2D_OCOLR_RED_1_Pos)            /*0x00FF0000U */
+#define DMA2D_OCOLR_RED_1          DMA2D_OCOLR_RED_1_Msk                       /*!< Output Red Value */
+#define DMA2D_OCOLR_ALPHA_1_Pos    (24U)
+#define DMA2D_OCOLR_ALPHA_1_Msk    (0xFFUL << DMA2D_OCOLR_ALPHA_1_Pos)          /*0xFF000000U*/
+#define DMA2D_OCOLR_ALPHA_1        DMA2D_OCOLR_ALPHA_1_Msk                     /*!< Output Alpha Channel Value */
+
+/*!<Mode_RGB565 */
+#define DMA2D_OCOLR_BLUE_2_Pos     (0U)
+#define DMA2D_OCOLR_BLUE_2_Msk     (0x1FUL <<DMA2D_OCOLR_BLUE_2_Pos)            /*0x0000001FU*/
+#define DMA2D_OCOLR_BLUE_2         DMA2D_OCOLR_BLUE_2_Msk                      /*!< Output BLUE Value */
+#define DMA2D_OCOLR_GREEN_2_Pos    (5U)
+#define DMA2D_OCOLR_GREEN_2_Msk    (0x7EUL << DMA2D_OCOLR_GREEN_2_Pos)          /* 0x000007E0U */
+#define DMA2D_OCOLR_GREEN_2        DMA2D_OCOLR_GREEN_2_Msk                     /*!< Output GREEN Value  */
+#define DMA2D_OCOLR_RED_2_Pos      (11U)
+#define DMA2D_OCOLR_RED_2_Msk      (0xF8UL<<DMA2D_OCOLR_RED_2_Pos)              /*0x0000F800U*/
+#define DMA2D_OCOLR_RED_2          DMA2D_OCOLR_RED_2_Msk                       /*!< Output Red Value */
+
+/*!<Mode_ARGB1555 */
+#define DMA2D_OCOLR_BLUE_3_Pos     (0U)
+#define DMA2D_OCOLR_BLUE_3_Msk     (0x1FUL << DMA2D_OCOLR_BLUE_3_Pos)           /*0x0000001FU*/
+#define DMA2D_OCOLR_BLUE_3         DMA2D_OCOLR_BLUE_3_Msk                      /*!< Output BLUE Value */
+#define DMA2D_OCOLR_GREEN_3_Pos    (5U)
+#define DMA2D_OCOLR_GREEN_3_Msk    (0x3EUL << DMA2D_OCOLR_GREEN_3_Pos)          /*0x000003E0U*/
+#define DMA2D_OCOLR_GREEN_3        DMA2D_OCOLR_GREEN_3_Msk                     /*!< Output GREEN Value  */
+#define DMA2D_OCOLR_RED_3_Pos      (10U)
+#define DMA2D_OCOLR_RED_3_Msk      (0x7CUL << DMA2D_OCOLR_RED_3_Pos)            /* 0x00007C00U*/
+#define DMA2D_OCOLR_RED_3          DMA2D_OCOLR_RED_3_Msk                       /*!< Output Red Value */
+#define DMA2D_OCOLR_ALPHA_3_Pos    (15U)
+#define DMA2D_OCOLR_ALPHA_3_Msk    (0x1UL << DMA2D_OCOLR_ALPHA_3_Pos)           /*0x00008000U*/
+#define DMA2D_OCOLR_ALPHA_3        DMA2D_OCOLR_ALPHA_3_Msk                     /*!< Output Alpha Channel Value */
+
+/*!<Mode_ARGB4444 */
+#define DMA2D_OCOLR_BLUE_4_Pos     (0U)
+#define DMA2D_OCOLR_BLUE_4_Msk     (0xFUL << DMA2D_OCOLR_BLUE_4_Pos)            /*0x0000000FU*/
+#define DMA2D_OCOLR_BLUE_4         DMA2D_OCOLR_BLUE_4_Msk                      /*!< Output BLUE Value */
+#define DMA2D_OCOLR_GREEN_4_Pos    (4U)
+#define DMA2D_OCOLR_GREEN_4_Msk    (0xFUL << DMA2D_OCOLR_GREEN_4_Pos)           /*0x000000F0U*/
+#define DMA2D_OCOLR_GREEN_4        DMA2D_OCOLR_GREEN_4_Msk                     /*!< Output GREEN Value  */
+#define DMA2D_OCOLR_RED_4_Pos      (8U)
+#define DMA2D_OCOLR_RED_4_Msk      (0xFUL << DMA2D_OCOLR_RED_4_Pos)             /*0x00000F00U*/
+#define DMA2D_OCOLR_RED_4          DMA2D_OCOLR_RED_4_Msk                       /*!< Output Red Value */
+#define DMA2D_OCOLR_ALPHA_4_Pos    (12U)
+#define DMA2D_OCOLR_ALPHA_4_Msk    (0xFUL << DMA2D_OCOLR_ALPHA_4_Pos)            /*0x0000F000U*/
+#define DMA2D_OCOLR_ALPHA_4        DMA2D_OCOLR_ALPHA_4_Msk                     /*!< Output Alpha Channel Value */
+
+/********************  Bit definition for DMA2D_OMAR register  ****************/
+
+#define DMA2D_OMAR_MA_Pos          (0U)
+#define DMA2D_OMAR_MA_Msk          (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)         /*!< 0xFFFFFFFF */
+#define DMA2D_OMAR_MA              DMA2D_OMAR_MA_Msk                           /*!< Output Memory Address */
+
+/********************  Bit definition for DMA2D_OOR register  *****************/
+
+#define DMA2D_OOR_LO_Pos           (0U)
+#define DMA2D_OOR_LO_Msk           (0xFFFFUL << DMA2D_OOR_LO_Pos)              /*!< 0x0000FFFF */
+#define DMA2D_OOR_LO               DMA2D_OOR_LO_Msk                            /*!< Output Line Offset */
+
+/********************  Bit definition for DMA2D_NLR register  *****************/
+
+#define DMA2D_NLR_NL_Pos           (0U)
+#define DMA2D_NLR_NL_Msk           (0xFFFFUL << DMA2D_NLR_NL_Pos)              /*!< 0x0000FFFF */
+#define DMA2D_NLR_NL               DMA2D_NLR_NL_Msk                            /*!< Number of Lines */
+#define DMA2D_NLR_PL_Pos           (16U)
+#define DMA2D_NLR_PL_Msk           (0x3FFFUL << DMA2D_NLR_PL_Pos)              /*!< 0x3FFF0000 */
+#define DMA2D_NLR_PL               DMA2D_NLR_PL_Msk                            /*!< Pixel per Lines */
+
+/********************  Bit definition for DMA2D_LWR register  *****************/
+
+#define DMA2D_LWR_LW_Pos           (0U)
+#define DMA2D_LWR_LW_Msk           (0xFFFFUL << DMA2D_LWR_LW_Pos)              /*!< 0x0000FFFF */
+#define DMA2D_LWR_LW               DMA2D_LWR_LW_Msk                            /*!< Line Watermark */
+
+/********************  Bit definition for DMA2D_AMTCR register  ***************/
+
+#define DMA2D_AMTCR_EN_Pos         (0U)
+#define DMA2D_AMTCR_EN_Msk         (0x1UL << DMA2D_AMTCR_EN_Pos)               /*!< 0x00000001 */
+#define DMA2D_AMTCR_EN             DMA2D_AMTCR_EN_Msk                          /*!< Enable */
+#define DMA2D_AMTCR_DT_Pos         (8U)
+#define DMA2D_AMTCR_DT_Msk         (0xFFUL << DMA2D_AMTCR_DT_Pos)              /*!< 0x0000FF00 */
+#define DMA2D_AMTCR_DT             DMA2D_AMTCR_DT_Msk                          /*!< Dead Time */
+
+
+/********************  Bit definition for DMA2D_FGCLUT register  **************/
+
+/********************  Bit definition for DMA2D_BGCLUT register  **************/
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                    External Interrupt/Event Controller                     */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for EXTI_RTSR1 register  *******************/
+#define EXTI_RTSR1_TR_Pos          (0U)
+#define EXTI_RTSR1_TR_Msk          (0x3FFFFFUL << EXTI_RTSR1_TR_Pos)           /*!< 0x003FFFFF */
+#define EXTI_RTSR1_TR              EXTI_RTSR1_TR_Msk                           /*!< Rising trigger event configuration bit */
+#define EXTI_RTSR1_TR0_Pos         (0U)
+#define EXTI_RTSR1_TR0_Msk         (0x1UL << EXTI_RTSR1_TR0_Pos)               /*!< 0x00000001 */
+#define EXTI_RTSR1_TR0             EXTI_RTSR1_TR0_Msk                          /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR1_TR1_Pos         (1U)
+#define EXTI_RTSR1_TR1_Msk         (0x1UL << EXTI_RTSR1_TR1_Pos)               /*!< 0x00000002 */
+#define EXTI_RTSR1_TR1             EXTI_RTSR1_TR1_Msk                          /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR1_TR2_Pos         (2U)
+#define EXTI_RTSR1_TR2_Msk         (0x1UL << EXTI_RTSR1_TR2_Pos)               /*!< 0x00000004 */
+#define EXTI_RTSR1_TR2             EXTI_RTSR1_TR2_Msk                          /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR1_TR3_Pos         (3U)
+#define EXTI_RTSR1_TR3_Msk         (0x1UL << EXTI_RTSR1_TR3_Pos)               /*!< 0x00000008 */
+#define EXTI_RTSR1_TR3             EXTI_RTSR1_TR3_Msk                          /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR1_TR4_Pos         (4U)
+#define EXTI_RTSR1_TR4_Msk         (0x1UL << EXTI_RTSR1_TR4_Pos)               /*!< 0x00000010 */
+#define EXTI_RTSR1_TR4             EXTI_RTSR1_TR4_Msk                          /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR1_TR5_Pos         (5U)
+#define EXTI_RTSR1_TR5_Msk         (0x1UL << EXTI_RTSR1_TR5_Pos)               /*!< 0x00000020 */
+#define EXTI_RTSR1_TR5             EXTI_RTSR1_TR5_Msk                          /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR1_TR6_Pos         (6U)
+#define EXTI_RTSR1_TR6_Msk         (0x1UL << EXTI_RTSR1_TR6_Pos)               /*!< 0x00000040 */
+#define EXTI_RTSR1_TR6             EXTI_RTSR1_TR6_Msk                          /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR1_TR7_Pos         (7U)
+#define EXTI_RTSR1_TR7_Msk         (0x1UL << EXTI_RTSR1_TR7_Pos)               /*!< 0x00000080 */
+#define EXTI_RTSR1_TR7             EXTI_RTSR1_TR7_Msk                          /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR1_TR8_Pos         (8U)
+#define EXTI_RTSR1_TR8_Msk         (0x1UL << EXTI_RTSR1_TR8_Pos)               /*!< 0x00000100 */
+#define EXTI_RTSR1_TR8             EXTI_RTSR1_TR8_Msk                          /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR1_TR9_Pos         (9U)
+#define EXTI_RTSR1_TR9_Msk         (0x1UL << EXTI_RTSR1_TR9_Pos)               /*!< 0x00000200 */
+#define EXTI_RTSR1_TR9             EXTI_RTSR1_TR9_Msk                          /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR1_TR10_Pos        (10U)
+#define EXTI_RTSR1_TR10_Msk        (0x1UL << EXTI_RTSR1_TR10_Pos)              /*!< 0x00000400 */
+#define EXTI_RTSR1_TR10            EXTI_RTSR1_TR10_Msk                         /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR1_TR11_Pos        (11U)
+#define EXTI_RTSR1_TR11_Msk        (0x1UL << EXTI_RTSR1_TR11_Pos)              /*!< 0x00000800 */
+#define EXTI_RTSR1_TR11            EXTI_RTSR1_TR11_Msk                         /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR1_TR12_Pos        (12U)
+#define EXTI_RTSR1_TR12_Msk        (0x1UL << EXTI_RTSR1_TR12_Pos)              /*!< 0x00001000 */
+#define EXTI_RTSR1_TR12            EXTI_RTSR1_TR12_Msk                         /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR1_TR13_Pos        (13U)
+#define EXTI_RTSR1_TR13_Msk        (0x1UL << EXTI_RTSR1_TR13_Pos)              /*!< 0x00002000 */
+#define EXTI_RTSR1_TR13            EXTI_RTSR1_TR13_Msk                         /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR1_TR14_Pos        (14U)
+#define EXTI_RTSR1_TR14_Msk        (0x1UL << EXTI_RTSR1_TR14_Pos)              /*!< 0x00004000 */
+#define EXTI_RTSR1_TR14            EXTI_RTSR1_TR14_Msk                         /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR1_TR15_Pos        (15U)
+#define EXTI_RTSR1_TR15_Msk        (0x1UL << EXTI_RTSR1_TR15_Pos)              /*!< 0x00008000 */
+#define EXTI_RTSR1_TR15            EXTI_RTSR1_TR15_Msk                         /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR1_TR16_Pos        (16U)
+#define EXTI_RTSR1_TR16_Msk        (0x1UL << EXTI_RTSR1_TR16_Pos)              /*!< 0x00010000 */
+#define EXTI_RTSR1_TR16            EXTI_RTSR1_TR16_Msk                         /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR1_TR17_Pos        (17U)
+#define EXTI_RTSR1_TR17_Msk        (0x1UL << EXTI_RTSR1_TR17_Pos)              /*!< 0x00020000 */
+#define EXTI_RTSR1_TR17            EXTI_RTSR1_TR17_Msk                         /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR1_TR18_Pos        (18U)
+#define EXTI_RTSR1_TR18_Msk        (0x1UL << EXTI_RTSR1_TR18_Pos)              /*!< 0x00040000 */
+#define EXTI_RTSR1_TR18            EXTI_RTSR1_TR18_Msk                         /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR1_TR19_Pos        (19U)
+#define EXTI_RTSR1_TR19_Msk        (0x1UL << EXTI_RTSR1_TR19_Pos)              /*!< 0x00080000 */
+#define EXTI_RTSR1_TR19            EXTI_RTSR1_TR19_Msk                         /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR1_TR20_Pos        (20U)
+#define EXTI_RTSR1_TR20_Msk        (0x1UL << EXTI_RTSR1_TR20_Pos)              /*!< 0x00100000 */
+#define EXTI_RTSR1_TR20            EXTI_RTSR1_TR20_Msk                         /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR1_TR21_Pos        (21U)
+#define EXTI_RTSR1_TR21_Msk        (0x1UL << EXTI_RTSR1_TR21_Pos)              /*!< 0x00200000 */
+#define EXTI_RTSR1_TR21            EXTI_RTSR1_TR21_Msk                         /*!< Rising trigger event configuration bit of line 21 */
+
+/******************  Bit definition for EXTI_FTSR1 register  *******************/
+#define EXTI_FTSR1_TR_Pos          (0U)
+#define EXTI_FTSR1_TR_Msk          (0x3FFFFFUL << EXTI_FTSR1_TR_Pos)           /*!< 0x003FFFFF */
+#define EXTI_FTSR1_TR              EXTI_FTSR1_TR_Msk                           /*!< Falling trigger event configuration bit */
+#define EXTI_FTSR1_TR0_Pos         (0U)
+#define EXTI_FTSR1_TR0_Msk         (0x1UL << EXTI_FTSR1_TR0_Pos)               /*!< 0x00000001 */
+#define EXTI_FTSR1_TR0             EXTI_FTSR1_TR0_Msk                          /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR1_TR1_Pos         (1U)
+#define EXTI_FTSR1_TR1_Msk         (0x1UL << EXTI_FTSR1_TR1_Pos)               /*!< 0x00000002 */
+#define EXTI_FTSR1_TR1             EXTI_FTSR1_TR1_Msk                          /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR1_TR2_Pos         (2U)
+#define EXTI_FTSR1_TR2_Msk         (0x1UL << EXTI_FTSR1_TR2_Pos)               /*!< 0x00000004 */
+#define EXTI_FTSR1_TR2             EXTI_FTSR1_TR2_Msk                          /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR1_TR3_Pos         (3U)
+#define EXTI_FTSR1_TR3_Msk         (0x1UL << EXTI_FTSR1_TR3_Pos)               /*!< 0x00000008 */
+#define EXTI_FTSR1_TR3             EXTI_FTSR1_TR3_Msk                          /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR1_TR4_Pos         (4U)
+#define EXTI_FTSR1_TR4_Msk         (0x1UL << EXTI_FTSR1_TR4_Pos)               /*!< 0x00000010 */
+#define EXTI_FTSR1_TR4             EXTI_FTSR1_TR4_Msk                          /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR1_TR5_Pos         (5U)
+#define EXTI_FTSR1_TR5_Msk         (0x1UL << EXTI_FTSR1_TR5_Pos)               /*!< 0x00000020 */
+#define EXTI_FTSR1_TR5             EXTI_FTSR1_TR5_Msk                          /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR1_TR6_Pos         (6U)
+#define EXTI_FTSR1_TR6_Msk         (0x1UL << EXTI_FTSR1_TR6_Pos)               /*!< 0x00000040 */
+#define EXTI_FTSR1_TR6             EXTI_FTSR1_TR6_Msk                          /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR1_TR7_Pos         (7U)
+#define EXTI_FTSR1_TR7_Msk         (0x1UL << EXTI_FTSR1_TR7_Pos)               /*!< 0x00000080 */
+#define EXTI_FTSR1_TR7             EXTI_FTSR1_TR7_Msk                          /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR1_TR8_Pos         (8U)
+#define EXTI_FTSR1_TR8_Msk         (0x1UL << EXTI_FTSR1_TR8_Pos)               /*!< 0x00000100 */
+#define EXTI_FTSR1_TR8             EXTI_FTSR1_TR8_Msk                          /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR1_TR9_Pos         (9U)
+#define EXTI_FTSR1_TR9_Msk         (0x1UL << EXTI_FTSR1_TR9_Pos)               /*!< 0x00000200 */
+#define EXTI_FTSR1_TR9             EXTI_FTSR1_TR9_Msk                          /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR1_TR10_Pos        (10U)
+#define EXTI_FTSR1_TR10_Msk        (0x1UL << EXTI_FTSR1_TR10_Pos)              /*!< 0x00000400 */
+#define EXTI_FTSR1_TR10            EXTI_FTSR1_TR10_Msk                         /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR1_TR11_Pos        (11U)
+#define EXTI_FTSR1_TR11_Msk        (0x1UL << EXTI_FTSR1_TR11_Pos)              /*!< 0x00000800 */
+#define EXTI_FTSR1_TR11            EXTI_FTSR1_TR11_Msk                         /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR1_TR12_Pos        (12U)
+#define EXTI_FTSR1_TR12_Msk        (0x1UL << EXTI_FTSR1_TR12_Pos)              /*!< 0x00001000 */
+#define EXTI_FTSR1_TR12            EXTI_FTSR1_TR12_Msk                         /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR1_TR13_Pos        (13U)
+#define EXTI_FTSR1_TR13_Msk        (0x1UL << EXTI_FTSR1_TR13_Pos)              /*!< 0x00002000 */
+#define EXTI_FTSR1_TR13            EXTI_FTSR1_TR13_Msk                         /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR1_TR14_Pos        (14U)
+#define EXTI_FTSR1_TR14_Msk        (0x1UL << EXTI_FTSR1_TR14_Pos)              /*!< 0x00004000 */
+#define EXTI_FTSR1_TR14            EXTI_FTSR1_TR14_Msk                         /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR1_TR15_Pos        (15U)
+#define EXTI_FTSR1_TR15_Msk        (0x1UL << EXTI_FTSR1_TR15_Pos)              /*!< 0x00008000 */
+#define EXTI_FTSR1_TR15            EXTI_FTSR1_TR15_Msk                         /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR1_TR16_Pos        (16U)
+#define EXTI_FTSR1_TR16_Msk        (0x1UL << EXTI_FTSR1_TR16_Pos)              /*!< 0x00010000 */
+#define EXTI_FTSR1_TR16            EXTI_FTSR1_TR16_Msk                         /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR1_TR17_Pos        (17U)
+#define EXTI_FTSR1_TR17_Msk        (0x1UL << EXTI_FTSR1_TR17_Pos)              /*!< 0x00020000 */
+#define EXTI_FTSR1_TR17            EXTI_FTSR1_TR17_Msk                         /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR1_TR18_Pos        (18U)
+#define EXTI_FTSR1_TR18_Msk        (0x1UL << EXTI_FTSR1_TR18_Pos)              /*!< 0x00040000 */
+#define EXTI_FTSR1_TR18            EXTI_FTSR1_TR18_Msk                         /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR1_TR19_Pos        (19U)
+#define EXTI_FTSR1_TR19_Msk        (0x1UL << EXTI_FTSR1_TR19_Pos)              /*!< 0x00080000 */
+#define EXTI_FTSR1_TR19            EXTI_FTSR1_TR19_Msk                         /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR1_TR20_Pos        (20U)
+#define EXTI_FTSR1_TR20_Msk        (0x1UL << EXTI_FTSR1_TR20_Pos)              /*!< 0x00100000 */
+#define EXTI_FTSR1_TR20            EXTI_FTSR1_TR20_Msk                         /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR1_TR21_Pos        (21U)
+#define EXTI_FTSR1_TR21_Msk        (0x1UL << EXTI_FTSR1_TR21_Pos)              /*!< 0x00200000 */
+#define EXTI_FTSR1_TR21            EXTI_FTSR1_TR21_Msk                         /*!< Falling trigger event configuration bit of line 21 */
+
+/******************  Bit definition for EXTI_SWIER1 register  ******************/
+#define EXTI_SWIER1_SWIER0_Pos     (0U)
+#define EXTI_SWIER1_SWIER0_Msk     (0x1UL << EXTI_SWIER1_SWIER0_Pos)           /*!< 0x00000001 */
+#define EXTI_SWIER1_SWIER0         EXTI_SWIER1_SWIER0_Msk                      /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER1_SWIER1_Pos     (1U)
+#define EXTI_SWIER1_SWIER1_Msk     (0x1UL << EXTI_SWIER1_SWIER1_Pos)           /*!< 0x00000002 */
+#define EXTI_SWIER1_SWIER1         EXTI_SWIER1_SWIER1_Msk                      /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER1_SWIER2_Pos     (2U)
+#define EXTI_SWIER1_SWIER2_Msk     (0x1UL << EXTI_SWIER1_SWIER2_Pos)           /*!< 0x00000004 */
+#define EXTI_SWIER1_SWIER2         EXTI_SWIER1_SWIER2_Msk                      /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER1_SWIER3_Pos     (3U)
+#define EXTI_SWIER1_SWIER3_Msk     (0x1UL << EXTI_SWIER1_SWIER3_Pos)           /*!< 0x00000008 */
+#define EXTI_SWIER1_SWIER3         EXTI_SWIER1_SWIER3_Msk                      /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER1_SWIER4_Pos     (4U)
+#define EXTI_SWIER1_SWIER4_Msk     (0x1UL << EXTI_SWIER1_SWIER4_Pos)           /*!< 0x00000010 */
+#define EXTI_SWIER1_SWIER4         EXTI_SWIER1_SWIER4_Msk                      /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER1_SWIER5_Pos     (5U)
+#define EXTI_SWIER1_SWIER5_Msk     (0x1UL << EXTI_SWIER1_SWIER5_Pos)           /*!< 0x00000020 */
+#define EXTI_SWIER1_SWIER5         EXTI_SWIER1_SWIER5_Msk                      /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER1_SWIER6_Pos     (6U)
+#define EXTI_SWIER1_SWIER6_Msk     (0x1UL << EXTI_SWIER1_SWIER6_Pos)           /*!< 0x00000040 */
+#define EXTI_SWIER1_SWIER6         EXTI_SWIER1_SWIER6_Msk                      /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER1_SWIER7_Pos     (7U)
+#define EXTI_SWIER1_SWIER7_Msk     (0x1UL << EXTI_SWIER1_SWIER7_Pos)           /*!< 0x00000080 */
+#define EXTI_SWIER1_SWIER7         EXTI_SWIER1_SWIER7_Msk                      /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER1_SWIER8_Pos     (8U)
+#define EXTI_SWIER1_SWIER8_Msk     (0x1UL << EXTI_SWIER1_SWIER8_Pos)           /*!< 0x00000100 */
+#define EXTI_SWIER1_SWIER8         EXTI_SWIER1_SWIER8_Msk                      /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER1_SWIER9_Pos     (9U)
+#define EXTI_SWIER1_SWIER9_Msk     (0x1UL << EXTI_SWIER1_SWIER9_Pos)           /*!< 0x00000200 */
+#define EXTI_SWIER1_SWIER9         EXTI_SWIER1_SWIER9_Msk                      /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER1_SWIER10_Pos    (10U)
+#define EXTI_SWIER1_SWIER10_Msk    (0x1UL << EXTI_SWIER1_SWIER10_Pos)          /*!< 0x00000400 */
+#define EXTI_SWIER1_SWIER10        EXTI_SWIER1_SWIER10_Msk                     /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER1_SWIER11_Pos    (11U)
+#define EXTI_SWIER1_SWIER11_Msk    (0x1UL << EXTI_SWIER1_SWIER11_Pos)          /*!< 0x00000800 */
+#define EXTI_SWIER1_SWIER11        EXTI_SWIER1_SWIER11_Msk                     /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER1_SWIER12_Pos    (12U)
+#define EXTI_SWIER1_SWIER12_Msk    (0x1UL << EXTI_SWIER1_SWIER12_Pos)          /*!< 0x00001000 */
+#define EXTI_SWIER1_SWIER12        EXTI_SWIER1_SWIER12_Msk                     /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER1_SWIER13_Pos    (13U)
+#define EXTI_SWIER1_SWIER13_Msk    (0x1UL << EXTI_SWIER1_SWIER13_Pos)          /*!< 0x00002000 */
+#define EXTI_SWIER1_SWIER13        EXTI_SWIER1_SWIER13_Msk                     /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER1_SWIER14_Pos    (14U)
+#define EXTI_SWIER1_SWIER14_Msk    (0x1UL << EXTI_SWIER1_SWIER14_Pos)          /*!< 0x00004000 */
+#define EXTI_SWIER1_SWIER14        EXTI_SWIER1_SWIER14_Msk                     /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER1_SWIER15_Pos    (15U)
+#define EXTI_SWIER1_SWIER15_Msk    (0x1UL << EXTI_SWIER1_SWIER15_Pos)          /*!< 0x00008000 */
+#define EXTI_SWIER1_SWIER15        EXTI_SWIER1_SWIER15_Msk                     /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER1_SWIER16_Pos    (16U)
+#define EXTI_SWIER1_SWIER16_Msk    (0x1UL << EXTI_SWIER1_SWIER16_Pos)          /*!< 0x00010000 */
+#define EXTI_SWIER1_SWIER16        EXTI_SWIER1_SWIER16_Msk                     /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER1_SWIER17_Pos    (17U)
+#define EXTI_SWIER1_SWIER17_Msk    (0x1UL << EXTI_SWIER1_SWIER17_Pos)          /*!< 0x00020000 */
+#define EXTI_SWIER1_SWIER17        EXTI_SWIER1_SWIER17_Msk                     /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER1_SWIER18_Pos    (18U)
+#define EXTI_SWIER1_SWIER18_Msk    (0x1UL << EXTI_SWIER1_SWIER18_Pos)          /*!< 0x00040000 */
+#define EXTI_SWIER1_SWIER18        EXTI_SWIER1_SWIER18_Msk                     /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER1_SWIER19_Pos    (19U)
+#define EXTI_SWIER1_SWIER19_Msk    (0x1UL << EXTI_SWIER1_SWIER19_Pos)          /*!< 0x00080000 */
+#define EXTI_SWIER1_SWIER19        EXTI_SWIER1_SWIER19_Msk                     /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER1_SWIER20_Pos    (20U)
+#define EXTI_SWIER1_SWIER20_Msk    (0x1UL << EXTI_SWIER1_SWIER20_Pos)          /*!< 0x00100000 */
+#define EXTI_SWIER1_SWIER20        EXTI_SWIER1_SWIER20_Msk                     /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER1_SWIER21_Pos    (21U)
+#define EXTI_SWIER1_SWIER21_Msk    (0x1UL << EXTI_SWIER1_SWIER21_Pos)          /*!< 0x00200000 */
+#define EXTI_SWIER1_SWIER21        EXTI_SWIER1_SWIER21_Msk                     /*!< Software Interrupt on line 21 */
+
+/******************  Bit definition for EXTI_D3PMR1 register  ******************/
+#define EXTI_D3PMR1_MR0_Pos        (0U)
+#define EXTI_D3PMR1_MR0_Msk        (0x1UL << EXTI_D3PMR1_MR0_Pos)              /*!< 0x00000001 */
+#define EXTI_D3PMR1_MR0            EXTI_D3PMR1_MR0_Msk                         /*!< Pending Mask Event for line 0  */
+#define EXTI_D3PMR1_MR1_Pos        (1U)
+#define EXTI_D3PMR1_MR1_Msk        (0x1UL << EXTI_D3PMR1_MR1_Pos)              /*!< 0x00000002 */
+#define EXTI_D3PMR1_MR1            EXTI_D3PMR1_MR1_Msk                         /*!< Pending Mask Event for line 1  */
+#define EXTI_D3PMR1_MR2_Pos        (2U)
+#define EXTI_D3PMR1_MR2_Msk        (0x1UL << EXTI_D3PMR1_MR2_Pos)              /*!< 0x00000004 */
+#define EXTI_D3PMR1_MR2            EXTI_D3PMR1_MR2_Msk                         /*!< Pending Mask Event for line 2  */
+#define EXTI_D3PMR1_MR3_Pos        (3U)
+#define EXTI_D3PMR1_MR3_Msk        (0x1UL << EXTI_D3PMR1_MR3_Pos)              /*!< 0x00000008 */
+#define EXTI_D3PMR1_MR3            EXTI_D3PMR1_MR3_Msk                         /*!< Pending Mask Event for line 3  */
+#define EXTI_D3PMR1_MR4_Pos        (4U)
+#define EXTI_D3PMR1_MR4_Msk        (0x1UL << EXTI_D3PMR1_MR4_Pos)              /*!< 0x00000010 */
+#define EXTI_D3PMR1_MR4            EXTI_D3PMR1_MR4_Msk                         /*!< Pending Mask Event for line 4  */
+#define EXTI_D3PMR1_MR5_Pos        (5U)
+#define EXTI_D3PMR1_MR5_Msk        (0x1UL << EXTI_D3PMR1_MR5_Pos)              /*!< 0x00000020 */
+#define EXTI_D3PMR1_MR5            EXTI_D3PMR1_MR5_Msk                         /*!< Pending Mask Event for line 5  */
+#define EXTI_D3PMR1_MR6_Pos        (6U)
+#define EXTI_D3PMR1_MR6_Msk        (0x1UL << EXTI_D3PMR1_MR6_Pos)              /*!< 0x00000040 */
+#define EXTI_D3PMR1_MR6            EXTI_D3PMR1_MR6_Msk                         /*!< Pending Mask Event for line 6  */
+#define EXTI_D3PMR1_MR7_Pos        (7U)
+#define EXTI_D3PMR1_MR7_Msk        (0x1UL << EXTI_D3PMR1_MR7_Pos)              /*!< 0x00000080 */
+#define EXTI_D3PMR1_MR7            EXTI_D3PMR1_MR7_Msk                         /*!< Pending Mask Event for line 7  */
+#define EXTI_D3PMR1_MR8_Pos        (8U)
+#define EXTI_D3PMR1_MR8_Msk        (0x1UL << EXTI_D3PMR1_MR8_Pos)              /*!< 0x00000100 */
+#define EXTI_D3PMR1_MR8            EXTI_D3PMR1_MR8_Msk                         /*!< Pending Mask Event for line 8  */
+#define EXTI_D3PMR1_MR9_Pos        (9U)
+#define EXTI_D3PMR1_MR9_Msk        (0x1UL << EXTI_D3PMR1_MR9_Pos)              /*!< 0x00000200 */
+#define EXTI_D3PMR1_MR9            EXTI_D3PMR1_MR9_Msk                         /*!< Pending Mask Event for line 9  */
+#define EXTI_D3PMR1_MR10_Pos       (10U)
+#define EXTI_D3PMR1_MR10_Msk       (0x1UL << EXTI_D3PMR1_MR10_Pos)             /*!< 0x00000400 */
+#define EXTI_D3PMR1_MR10           EXTI_D3PMR1_MR10_Msk                        /*!< Pending Mask Event for line 10 */
+#define EXTI_D3PMR1_MR11_Pos       (11U)
+#define EXTI_D3PMR1_MR11_Msk       (0x1UL << EXTI_D3PMR1_MR11_Pos)             /*!< 0x00000800 */
+#define EXTI_D3PMR1_MR11           EXTI_D3PMR1_MR11_Msk                        /*!< Pending Mask Event for line 11 */
+#define EXTI_D3PMR1_MR12_Pos       (12U)
+#define EXTI_D3PMR1_MR12_Msk       (0x1UL << EXTI_D3PMR1_MR12_Pos)             /*!< 0x00001000 */
+#define EXTI_D3PMR1_MR12           EXTI_D3PMR1_MR12_Msk                        /*!< Pending Mask Event for line 12 */
+#define EXTI_D3PMR1_MR13_Pos       (13U)
+#define EXTI_D3PMR1_MR13_Msk       (0x1UL << EXTI_D3PMR1_MR13_Pos)             /*!< 0x00002000 */
+#define EXTI_D3PMR1_MR13           EXTI_D3PMR1_MR13_Msk                        /*!< Pending Mask Event for line 13 */
+#define EXTI_D3PMR1_MR14_Pos       (14U)
+#define EXTI_D3PMR1_MR14_Msk       (0x1UL << EXTI_D3PMR1_MR14_Pos)             /*!< 0x00004000 */
+#define EXTI_D3PMR1_MR14           EXTI_D3PMR1_MR14_Msk                        /*!< Pending Mask Event for line 14 */
+#define EXTI_D3PMR1_MR15_Pos       (15U)
+#define EXTI_D3PMR1_MR15_Msk       (0x1UL << EXTI_D3PMR1_MR15_Pos)             /*!< 0x00008000 */
+#define EXTI_D3PMR1_MR15           EXTI_D3PMR1_MR15_Msk                        /*!< Pending Mask Event for line 15 */
+#define EXTI_D3PMR1_MR19_Pos       (19U)
+#define EXTI_D3PMR1_MR19_Msk       (0x1UL << EXTI_D3PMR1_MR19_Pos)             /*!< 0x00080000 */
+#define EXTI_D3PMR1_MR19           EXTI_D3PMR1_MR19_Msk                        /*!< Pending Mask Event for line 19 */
+#define EXTI_D3PMR1_MR20_Pos       (20U)
+#define EXTI_D3PMR1_MR20_Msk       (0x1UL << EXTI_D3PMR1_MR20_Pos)             /*!< 0x00100000 */
+#define EXTI_D3PMR1_MR20           EXTI_D3PMR1_MR20_Msk                        /*!< Pending Mask Event for line 20 */
+#define EXTI_D3PMR1_MR21_Pos       (21U)
+#define EXTI_D3PMR1_MR21_Msk       (0x1UL << EXTI_D3PMR1_MR21_Pos)             /*!< 0x00200000 */
+#define EXTI_D3PMR1_MR21           EXTI_D3PMR1_MR21_Msk                        /*!< Pending Mask Event for line 21 */
+#define EXTI_D3PMR1_MR25_Pos       (24U)
+#define EXTI_D3PMR1_MR25_Msk       (0x1UL << EXTI_D3PMR1_MR25_Pos)             /*!< 0x01000000 */
+#define EXTI_D3PMR1_MR25           EXTI_D3PMR1_MR25_Msk                        /*!< Pending Mask Event for line 25 */
+
+/*******************  Bit definition for EXTI_D3PCR1L register  ****************/
+#define EXTI_D3PCR1L_PCS0_Pos       (0U)
+#define EXTI_D3PCR1L_PCS0_Msk       (0x3UL << EXTI_D3PCR1L_PCS0_Pos)           /*!< 0x00000003 */
+#define EXTI_D3PCR1L_PCS0           EXTI_D3PCR1L_PCS0_Msk                      /*!< D3 Pending request clear input signal selection on line 0 */
+#define EXTI_D3PCR1L_PCS1_Pos       (2U)
+#define EXTI_D3PCR1L_PCS1_Msk       (0x3UL << EXTI_D3PCR1L_PCS1_Pos)           /*!< 0x000000C0 */
+#define EXTI_D3PCR1L_PCS1           EXTI_D3PCR1L_PCS1_Msk                      /*!< D3 Pending request clear input signal selection on line 1 */
+#define EXTI_D3PCR1L_PCS2_Pos       (4U)
+#define EXTI_D3PCR1L_PCS2_Msk       (0x3UL << EXTI_D3PCR1L_PCS2_Pos)           /*!< 0x00000030 */
+#define EXTI_D3PCR1L_PCS2           EXTI_D3PCR1L_PCS2_Msk                      /*!< D3 Pending request clear input signal selection on line 2 */
+#define EXTI_D3PCR1L_PCS3_Pos       (6U)
+#define EXTI_D3PCR1L_PCS3_Msk       (0x3UL << EXTI_D3PCR1L_PCS3_Pos)           /*!< 0x000000C0 */
+#define EXTI_D3PCR1L_PCS3           EXTI_D3PCR1L_PCS3_Msk                      /*!< D3 Pending request clear input signal selection on line 3 */
+#define EXTI_D3PCR1L_PCS4_Pos       (8U)
+#define EXTI_D3PCR1L_PCS4_Msk       (0x3UL << EXTI_D3PCR1L_PCS4_Pos)           /*!< 0x00000300 */
+#define EXTI_D3PCR1L_PCS4           EXTI_D3PCR1L_PCS4_Msk                      /*!< D3 Pending request clear input signal selection on line 4 */
+#define EXTI_D3PCR1L_PCS5_Pos       (10U)
+#define EXTI_D3PCR1L_PCS5_Msk       (0x3UL << EXTI_D3PCR1L_PCS5_Pos)           /*!< 0x00000C00 */
+#define EXTI_D3PCR1L_PCS5           EXTI_D3PCR1L_PCS5_Msk                      /*!< D3 Pending request clear input signal selection on line 5 */
+#define EXTI_D3PCR1L_PCS6_Pos       (12U)
+#define EXTI_D3PCR1L_PCS6_Msk       (0x3UL << EXTI_D3PCR1L_PCS6_Pos)           /*!< 0x00003000 */
+#define EXTI_D3PCR1L_PCS6           EXTI_D3PCR1L_PCS6_Msk                      /*!< D3 Pending request clear input signal selection on line 6 */
+#define EXTI_D3PCR1L_PCS7_Pos       (14U)
+#define EXTI_D3PCR1L_PCS7_Msk       (0x3UL << EXTI_D3PCR1L_PCS7_Pos)           /*!< 0x0000C000 */
+#define EXTI_D3PCR1L_PCS7           EXTI_D3PCR1L_PCS7_Msk                      /*!< D3 Pending request clear input signal selection on line 7 */
+#define EXTI_D3PCR1L_PCS8_Pos       (16U)
+#define EXTI_D3PCR1L_PCS8_Msk       (0x3UL << EXTI_D3PCR1L_PCS8_Pos)           /*!< 0x00030000 */
+#define EXTI_D3PCR1L_PCS8           EXTI_D3PCR1L_PCS8_Msk                      /*!< D3 Pending request clear input signal selection on line 8 */
+#define EXTI_D3PCR1L_PCS9_Pos       (18U)
+#define EXTI_D3PCR1L_PCS9_Msk       (0x3UL << EXTI_D3PCR1L_PCS9_Pos)           /*!< 0x000C0000 */
+#define EXTI_D3PCR1L_PCS9           EXTI_D3PCR1L_PCS9_Msk                      /*!< D3 Pending request clear input signal selection on line 9 */
+#define EXTI_D3PCR1L_PCS10_Pos      (20U)
+#define EXTI_D3PCR1L_PCS10_Msk      (0x3UL << EXTI_D3PCR1L_PCS10_Pos)          /*!< 0x00300000 */
+#define EXTI_D3PCR1L_PCS10          EXTI_D3PCR1L_PCS10_Msk                     /*!< D3 Pending request clear input signal selection on line 10*/
+#define EXTI_D3PCR1L_PCS11_Pos      (22U)
+#define EXTI_D3PCR1L_PCS11_Msk      (0x3UL << EXTI_D3PCR1L_PCS11_Pos)          /*!< 0x00C00000 */
+#define EXTI_D3PCR1L_PCS11          EXTI_D3PCR1L_PCS11_Msk                     /*!< D3 Pending request clear input signal selection on line 11*/
+#define EXTI_D3PCR1L_PCS12_Pos      (24U)
+#define EXTI_D3PCR1L_PCS12_Msk      (0x3UL << EXTI_D3PCR1L_PCS12_Pos)          /*!< 0x03000000 */
+#define EXTI_D3PCR1L_PCS12          EXTI_D3PCR1L_PCS12_Msk                     /*!< D3 Pending request clear input signal selection on line 12*/
+#define EXTI_D3PCR1L_PCS13_Pos      (26U)
+#define EXTI_D3PCR1L_PCS13_Msk      (0x3UL << EXTI_D3PCR1L_PCS13_Pos)          /*!< 0x0C000000 */
+#define EXTI_D3PCR1L_PCS13          EXTI_D3PCR1L_PCS13_Msk                     /*!< D3 Pending request clear input signal selection on line 13*/
+#define EXTI_D3PCR1L_PCS14_Pos      (28U)
+#define EXTI_D3PCR1L_PCS14_Msk      (0x3UL << EXTI_D3PCR1L_PCS14_Pos)          /*!< 0x30000000 */
+#define EXTI_D3PCR1L_PCS14          EXTI_D3PCR1L_PCS14_Msk                     /*!< D3 Pending request clear input signal selection on line 14*/
+#define EXTI_D3PCR1L_PCS15_Pos      (30U)
+#define EXTI_D3PCR1L_PCS15_Msk      (0x3UL << EXTI_D3PCR1L_PCS15_Pos)          /*!< 0xC0000000 */
+#define EXTI_D3PCR1L_PCS15          EXTI_D3PCR1L_PCS15_Msk                     /*!< D3 Pending request clear input signal selection on line 15*/
+
+/*******************  Bit definition for EXTI_D3PCR1H register  ****************/
+#define EXTI_D3PCR1H_PCS19_Pos       (6U)
+#define EXTI_D3PCR1H_PCS19_Msk       (0x3UL << EXTI_D3PCR1H_PCS19_Pos)         /*!< 0x000000C0 */
+#define EXTI_D3PCR1H_PCS19           EXTI_D3PCR1H_PCS19_Msk                    /*!< D3 Pending request clear input signal selection on line 19 */
+#define EXTI_D3PCR1H_PCS20_Pos       (8U)
+#define EXTI_D3PCR1H_PCS20_Msk       (0x3UL << EXTI_D3PCR1H_PCS20_Pos)         /*!< 0x00000300 */
+#define EXTI_D3PCR1H_PCS20           EXTI_D3PCR1H_PCS20_Msk                    /*!< D3 Pending request clear input signal selection on line 20 */
+#define EXTI_D3PCR1H_PCS21_Pos       (10U)
+#define EXTI_D3PCR1H_PCS21_Msk       (0x3UL << EXTI_D3PCR1H_PCS21_Pos)         /*!< 0x00000C00 */
+#define EXTI_D3PCR1H_PCS21           EXTI_D3PCR1H_PCS21_Msk                    /*!< D3 Pending request clear input signal selection on line 21 */
+#define EXTI_D3PCR1H_PCS25_Pos       (18U)
+#define EXTI_D3PCR1H_PCS25_Msk       (0x3UL << EXTI_D3PCR1H_PCS25_Pos)         /*!< 0x000C0000 */
+#define EXTI_D3PCR1H_PCS25           EXTI_D3PCR1H_PCS25_Msk                    /*!< D3 Pending request clear input signal selection on line 25 */
+
+/******************  Bit definition for EXTI_RTSR2 register  *******************/
+#define EXTI_RTSR2_TR_Pos          (17U)
+#define EXTI_RTSR2_TR_Msk          (0x5UL << EXTI_RTSR2_TR_Pos)                /*!< 0x000A0000 */
+#define EXTI_RTSR2_TR              EXTI_RTSR2_TR_Msk                           /*!< Rising trigger event configuration bit */
+#define EXTI_RTSR2_TR49_Pos        (17U)
+#define EXTI_RTSR2_TR49_Msk        (0x1UL << EXTI_RTSR2_TR49_Pos)              /*!< 0x00020000 */
+#define EXTI_RTSR2_TR49            EXTI_RTSR2_TR49_Msk                         /*!< Rising trigger event configuration bit of line 49 */
+#define EXTI_RTSR2_TR51_Pos        (19U)
+#define EXTI_RTSR2_TR51_Msk        (0x1UL << EXTI_RTSR2_TR51_Pos)              /*!< 0x00080000 */
+#define EXTI_RTSR2_TR51            EXTI_RTSR2_TR51_Msk                         /*!< Rising trigger event configuration bit of line 51 */
+
+/******************  Bit definition for EXTI_FTSR2 register  *******************/
+#define EXTI_FTSR2_TR_Pos          (17U)
+#define EXTI_FTSR2_TR_Msk          (0x5UL << EXTI_FTSR2_TR_Pos)                /*!< 0x000A0000 */
+#define EXTI_FTSR2_TR              EXTI_FTSR2_TR_Msk                           /*!< Falling trigger event configuration bit */
+#define EXTI_FTSR2_TR49_Pos        (17U)
+#define EXTI_FTSR2_TR49_Msk        (0x1UL << EXTI_FTSR2_TR49_Pos)              /*!< 0x00020000 */
+#define EXTI_FTSR2_TR49            EXTI_FTSR2_TR49_Msk                         /*!< Falling trigger event configuration bit of line 49 */
+#define EXTI_FTSR2_TR51_Pos        (19U)
+#define EXTI_FTSR2_TR51_Msk        (0x1UL << EXTI_FTSR2_TR51_Pos)              /*!< 0x00080000 */
+#define EXTI_FTSR2_TR51            EXTI_FTSR2_TR51_Msk                         /*!< Falling trigger event configuration bit of line 51 */
+
+/******************  Bit definition for EXTI_SWIER2 register  ******************/
+#define EXTI_SWIER2_SWIER49_Pos    (17U)
+#define EXTI_SWIER2_SWIER49_Msk    (0x1UL << EXTI_SWIER2_SWIER49_Pos)          /*!< 0x00020000 */
+#define EXTI_SWIER2_SWIER49        EXTI_SWIER2_SWIER49_Msk                     /*!< Software Interrupt on line 49 */
+#define EXTI_SWIER2_SWIER51_Pos    (19U)
+#define EXTI_SWIER2_SWIER51_Msk    (0x1UL << EXTI_SWIER2_SWIER51_Pos)          /*!< 0x00080000 */
+#define EXTI_SWIER2_SWIER51        EXTI_SWIER2_SWIER51_Msk                     /*!< Software Interrupt on line 51 */
+
+/******************  Bit definition for EXTI_D3PMR2 register  ******************/
+#define EXTI_D3PMR2_MR34_Pos       (2U)
+#define EXTI_D3PMR2_MR34_Msk       (0x1UL << EXTI_D3PMR2_MR34_Pos)             /*!< 0x00000004 */
+#define EXTI_D3PMR2_MR34           EXTI_D3PMR2_MR34_Msk                        /*!< Pending Mask Event for line 34  */
+#define EXTI_D3PMR2_MR35_Pos       (3U)
+#define EXTI_D3PMR2_MR35_Msk       (0x1UL << EXTI_D3PMR2_MR35_Pos)             /*!< 0x00000008 */
+#define EXTI_D3PMR2_MR35           EXTI_D3PMR2_MR35_Msk                        /*!< Pending Mask Event for line 35  */
+#define EXTI_D3PMR2_MR41_Pos       (9U)
+#define EXTI_D3PMR2_MR41_Msk       (0x1UL << EXTI_D3PMR2_MR41_Pos)             /*!< 0x00000200 */
+#define EXTI_D3PMR2_MR41           EXTI_D3PMR2_MR41_Msk                        /*!< Pending Mask Event for line 41  */
+#define EXTI_D3PMR2_MR48_Pos       (16U)
+#define EXTI_D3PMR2_MR48_Msk       (0x1UL << EXTI_D3PMR2_MR48_Pos)             /*!< 0x00010000 */
+#define EXTI_D3PMR2_MR48           EXTI_D3PMR2_MR48_Msk                        /*!< Pending Mask Event for line 48  */
+#define EXTI_D3PMR2_MR49_Pos       (17U)
+#define EXTI_D3PMR2_MR49_Msk       (0x1UL << EXTI_D3PMR2_MR49_Pos)             /*!< 0x00020000 */
+#define EXTI_D3PMR2_MR49           EXTI_D3PMR2_MR49_Msk                        /*!< Pending Mask Event for line 49  */
+#define EXTI_D3PMR2_MR50_Pos       (18U)
+#define EXTI_D3PMR2_MR50_Msk       (0x1UL << EXTI_D3PMR2_MR50_Pos)             /*!< 0x00040000 */
+#define EXTI_D3PMR2_MR50           EXTI_D3PMR2_MR50_Msk                        /*!< Pending Mask Event for line 50  */
+#define EXTI_D3PMR2_MR51_Pos       (19U)
+#define EXTI_D3PMR2_MR51_Msk       (0x1UL << EXTI_D3PMR2_MR51_Pos)             /*!< 0x00080000 */
+#define EXTI_D3PMR2_MR51           EXTI_D3PMR2_MR51_Msk                        /*!< Pending Mask Event for line 51  */
+#define EXTI_D3PMR2_MR52_Pos       (20U)
+#define EXTI_D3PMR2_MR52_Msk       (0x1UL << EXTI_D3PMR2_MR52_Pos)             /*!< 0x00100000 */
+#define EXTI_D3PMR2_MR52           EXTI_D3PMR2_MR52_Msk                        /*!< Pending Mask Event for line 52  */
+#define EXTI_D3PMR2_MR53_Pos       (21U)
+#define EXTI_D3PMR2_MR53_Msk       (0x1UL << EXTI_D3PMR2_MR53_Pos)             /*!< 0x00200000 */
+#define EXTI_D3PMR2_MR53           EXTI_D3PMR2_MR53_Msk                        /*!< Pending Mask Event for line 53  */
+/*******************  Bit definition for EXTI_D3PCR2L register  ****************/
+#define EXTI_D3PCR2L_PCS34_Pos       (4U)
+#define EXTI_D3PCR2L_PCS34_Msk       (0x3UL << EXTI_D3PCR2L_PCS34_Pos)         /*!< 0x00000030 */
+#define EXTI_D3PCR2L_PCS34           EXTI_D3PCR2L_PCS34_Msk                    /*!< D3 Pending request clear input signal selection on line 34 */
+#define EXTI_D3PCR2L_PCS35_Pos       (6U)
+#define EXTI_D3PCR2L_PCS35_Msk       (0x3UL << EXTI_D3PCR2L_PCS35_Pos)         /*!< 0x000000C0 */
+#define EXTI_D3PCR2L_PCS35           EXTI_D3PCR2L_PCS35_Msk                    /*!< D3 Pending request clear input signal selection on line 35 */
+#define EXTI_D3PCR2L_PCS41_Pos       (18U)
+#define EXTI_D3PCR2L_PCS41_Msk       (0x3UL << EXTI_D3PCR2L_PCS41_Pos)         /*!< 0x000C0000 */
+#define EXTI_D3PCR2L_PCS41           EXTI_D3PCR2L_PCS41_Msk                    /*!< D3 Pending request clear input signal selection on line 41 */
+
+
+/*******************  Bit definition for EXTI_D3PCR2H register  ****************/
+#define EXTI_D3PCR2H_PCS48_Pos       (0U)
+#define EXTI_D3PCR2H_PCS48_Msk       (0x3UL << EXTI_D3PCR2H_PCS48_Pos)         /*!< 0x00000003 */
+#define EXTI_D3PCR2H_PCS48           EXTI_D3PCR2H_PCS48_Msk                    /*!< D3 Pending request clear input signal selection on line 48 */
+#define EXTI_D3PCR2H_PCS49_Pos       (2U)
+#define EXTI_D3PCR2H_PCS49_Msk       (0x3UL << EXTI_D3PCR2H_PCS49_Pos)         /*!< 0x0000000C */
+#define EXTI_D3PCR2H_PCS49           EXTI_D3PCR2H_PCS49_Msk                    /*!< D3 Pending request clear input signal selection on line 49 */
+#define EXTI_D3PCR2H_PCS50_Pos       (4U)
+#define EXTI_D3PCR2H_PCS50_Msk       (0x3UL << EXTI_D3PCR2H_PCS50_Pos)         /*!< 0x00000030 */
+#define EXTI_D3PCR2H_PCS50           EXTI_D3PCR2H_PCS50_Msk                    /*!< D3 Pending request clear input signal selection on line 50 */
+#define EXTI_D3PCR2H_PCS51_Pos       (6U)
+#define EXTI_D3PCR2H_PCS51_Msk       (0x3UL << EXTI_D3PCR2H_PCS51_Pos)         /*!< 0x000000C0 */
+#define EXTI_D3PCR2H_PCS51           EXTI_D3PCR2H_PCS51_Msk                    /*!< D3 Pending request clear input signal selection on line 51 */
+#define EXTI_D3PCR2H_PCS52_Pos       (8U)
+#define EXTI_D3PCR2H_PCS52_Msk       (0x3UL << EXTI_D3PCR2H_PCS52_Pos)         /*!< 0x00000300 */
+#define EXTI_D3PCR2H_PCS52           EXTI_D3PCR2H_PCS52_Msk                    /*!< D3 Pending request clear input signal selection on line 52 */
+#define EXTI_D3PCR2H_PCS53_Pos       (10U)
+#define EXTI_D3PCR2H_PCS53_Msk       (0x3UL << EXTI_D3PCR2H_PCS53_Pos)         /*!< 0x00000C00 */
+#define EXTI_D3PCR2H_PCS53           EXTI_D3PCR2H_PCS53_Msk                    /*!< D3 Pending request clear input signal selection on line 53 */
+/******************  Bit definition for EXTI_RTSR3 register  *******************/
+#define EXTI_RTSR3_TR_Pos          (18U)
+#define EXTI_RTSR3_TR_Msk          (0x1DUL << EXTI_RTSR3_TR_Pos)               /*!< 0x00740000 */
+#define EXTI_RTSR3_TR              EXTI_RTSR3_TR_Msk                           /*!< Rising trigger event configuration bit */
+#define EXTI_RTSR3_TR82_Pos        (18U)
+#define EXTI_RTSR3_TR82_Msk        (0x1UL << EXTI_RTSR3_TR82_Pos)              /*!< 0x00040000 */
+#define EXTI_RTSR3_TR82            EXTI_RTSR3_TR82_Msk                         /*!< Rising trigger event configuration bit of line 82 */
+#define EXTI_RTSR3_TR84_Pos        (20U)
+#define EXTI_RTSR3_TR84_Msk        (0x1UL << EXTI_RTSR3_TR84_Pos)              /*!< 0x00100000 */
+#define EXTI_RTSR3_TR84            EXTI_RTSR3_TR84_Msk                         /*!< Rising trigger event configuration bit of line 84 */
+#define EXTI_RTSR3_TR85_Pos        (21U)
+#define EXTI_RTSR3_TR85_Msk        (0x1UL << EXTI_RTSR3_TR85_Pos)              /*!< 0x00200000 */
+#define EXTI_RTSR3_TR85            EXTI_RTSR3_TR85_Msk                         /*!< Rising trigger event configuration bit of line 85 */
+#define EXTI_RTSR3_TR86_Pos        (22U)
+#define EXTI_RTSR3_TR86_Msk        (0x1UL << EXTI_RTSR3_TR86_Pos)              /*!< 0x00400000 */
+#define EXTI_RTSR3_TR86            EXTI_RTSR3_TR86_Msk                         /*!< Rising trigger event configuration bit of line 86 */
+
+/******************  Bit definition for EXTI_FTSR3 register  *******************/
+#define EXTI_FTSR3_TR_Pos          (18U)
+#define EXTI_FTSR3_TR_Msk          (0x1DUL << EXTI_FTSR3_TR_Pos)               /*!< 0x00740000 */
+#define EXTI_FTSR3_TR              EXTI_FTSR3_TR_Msk                           /*!< Falling trigger event configuration bit */
+#define EXTI_FTSR3_TR82_Pos        (18U)
+#define EXTI_FTSR3_TR82_Msk        (0x1UL << EXTI_FTSR3_TR82_Pos)              /*!< 0x00040000 */
+#define EXTI_FTSR3_TR82            EXTI_FTSR3_TR82_Msk                         /*!< Falling trigger event configuration bit of line 82 */
+#define EXTI_FTSR3_TR84_Pos        (20U)
+#define EXTI_FTSR3_TR84_Msk        (0x1UL << EXTI_FTSR3_TR84_Pos)              /*!< 0x00100000 */
+#define EXTI_FTSR3_TR84            EXTI_FTSR3_TR84_Msk                         /*!< Falling trigger event configuration bit of line 84 */
+#define EXTI_FTSR3_TR85_Pos        (21U)
+#define EXTI_FTSR3_TR85_Msk        (0x1UL << EXTI_FTSR3_TR85_Pos)              /*!< 0x00200000 */
+#define EXTI_FTSR3_TR85            EXTI_FTSR3_TR85_Msk                         /*!< Falling trigger event configuration bit of line 85 */
+#define EXTI_FTSR3_TR86_Pos        (22U)
+#define EXTI_FTSR3_TR86_Msk        (0x1UL << EXTI_FTSR3_TR86_Pos)              /*!< 0x00400000 */
+#define EXTI_FTSR3_TR86            EXTI_FTSR3_TR86_Msk                         /*!< Falling trigger event configuration bit of line 86 */
+
+/******************  Bit definition for EXTI_SWIER3 register  ******************/
+#define EXTI_SWIER3_SWI_Pos        (18U)
+#define EXTI_SWIER3_SWI_Msk        (0x1DUL << EXTI_SWIER3_SWI_Pos)             /*!< 0x00740000 */
+#define EXTI_SWIER3_SWI            EXTI_SWIER3_SWI_Msk                         /*!< Software Interrupt event bit */
+#define EXTI_SWIER3_SWIER82_Pos    (18U)
+#define EXTI_SWIER3_SWIER82_Msk    (0x1UL << EXTI_SWIER3_SWIER82_Pos)          /*!< 0x00040000 */
+#define EXTI_SWIER3_SWIER82        EXTI_SWIER3_SWIER82_Msk                     /*!< Software Interrupt on line 82 */
+#define EXTI_SWIER3_SWIER84_Pos    (20U)
+#define EXTI_SWIER3_SWIER84_Msk    (0x1UL << EXTI_SWIER3_SWIER84_Pos)          /*!< 0x00100000 */
+#define EXTI_SWIER3_SWIER84        EXTI_SWIER3_SWIER84_Msk                     /*!< Software Interrupt on line 84 */
+#define EXTI_SWIER3_SWIER85_Pos    (21U)
+#define EXTI_SWIER3_SWIER85_Msk    (0x1UL << EXTI_SWIER3_SWIER85_Pos)          /*!< 0x00200000 */
+#define EXTI_SWIER3_SWIER85        EXTI_SWIER3_SWIER85_Msk                     /*!< Software Interrupt on line 85 */
+#define EXTI_SWIER3_SWIER86_Pos    (22U)
+#define EXTI_SWIER3_SWIER86_Msk    (0x1UL << EXTI_SWIER3_SWIER86_Pos)          /*!< 0x00400000 */
+#define EXTI_SWIER3_SWIER86        EXTI_SWIER3_SWIER86_Msk                     /*!< Software Interrupt on line 86 */
+
+/*******************  Bit definition for EXTI_IMR1 register  *******************/
+#define EXTI_IMR1_IM_Pos           (0U)
+#define EXTI_IMR1_IM_Msk           (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos)          /*!< 0xFFFFFFFF */
+#define EXTI_IMR1_IM               EXTI_IMR1_IM_Msk                            /*!< Interrupt Mask */
+#define EXTI_IMR1_IM0_Pos          (0U)
+#define EXTI_IMR1_IM0_Msk          (0x1UL << EXTI_IMR1_IM0_Pos)                /*!< 0x00000001 */
+#define EXTI_IMR1_IM0              EXTI_IMR1_IM0_Msk                           /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR1_IM1_Pos          (1U)
+#define EXTI_IMR1_IM1_Msk          (0x1UL << EXTI_IMR1_IM1_Pos)                /*!< 0x00000002 */
+#define EXTI_IMR1_IM1              EXTI_IMR1_IM1_Msk                           /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR1_IM2_Pos          (2U)
+#define EXTI_IMR1_IM2_Msk          (0x1UL << EXTI_IMR1_IM2_Pos)                /*!< 0x00000004 */
+#define EXTI_IMR1_IM2              EXTI_IMR1_IM2_Msk                           /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR1_IM3_Pos          (3U)
+#define EXTI_IMR1_IM3_Msk          (0x1UL << EXTI_IMR1_IM3_Pos)                /*!< 0x00000008 */
+#define EXTI_IMR1_IM3              EXTI_IMR1_IM3_Msk                           /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR1_IM4_Pos          (4U)
+#define EXTI_IMR1_IM4_Msk          (0x1UL << EXTI_IMR1_IM4_Pos)                /*!< 0x00000010 */
+#define EXTI_IMR1_IM4              EXTI_IMR1_IM4_Msk                           /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR1_IM5_Pos          (5U)
+#define EXTI_IMR1_IM5_Msk          (0x1UL << EXTI_IMR1_IM5_Pos)                /*!< 0x00000020 */
+#define EXTI_IMR1_IM5              EXTI_IMR1_IM5_Msk                           /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR1_IM6_Pos          (6U)
+#define EXTI_IMR1_IM6_Msk          (0x1UL << EXTI_IMR1_IM6_Pos)                /*!< 0x00000040 */
+#define EXTI_IMR1_IM6              EXTI_IMR1_IM6_Msk                           /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR1_IM7_Pos          (7U)
+#define EXTI_IMR1_IM7_Msk          (0x1UL << EXTI_IMR1_IM7_Pos)                /*!< 0x00000080 */
+#define EXTI_IMR1_IM7              EXTI_IMR1_IM7_Msk                           /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR1_IM8_Pos          (8U)
+#define EXTI_IMR1_IM8_Msk          (0x1UL << EXTI_IMR1_IM8_Pos)                /*!< 0x00000100 */
+#define EXTI_IMR1_IM8              EXTI_IMR1_IM8_Msk                           /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR1_IM9_Pos          (9U)
+#define EXTI_IMR1_IM9_Msk          (0x1UL << EXTI_IMR1_IM9_Pos)                /*!< 0x00000200 */
+#define EXTI_IMR1_IM9              EXTI_IMR1_IM9_Msk                           /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR1_IM10_Pos         (10U)
+#define EXTI_IMR1_IM10_Msk         (0x1UL << EXTI_IMR1_IM10_Pos)               /*!< 0x00000400 */
+#define EXTI_IMR1_IM10             EXTI_IMR1_IM10_Msk                          /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR1_IM11_Pos         (11U)
+#define EXTI_IMR1_IM11_Msk         (0x1UL << EXTI_IMR1_IM11_Pos)               /*!< 0x00000800 */
+#define EXTI_IMR1_IM11             EXTI_IMR1_IM11_Msk                          /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR1_IM12_Pos         (12U)
+#define EXTI_IMR1_IM12_Msk         (0x1UL << EXTI_IMR1_IM12_Pos)               /*!< 0x00001000 */
+#define EXTI_IMR1_IM12             EXTI_IMR1_IM12_Msk                          /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR1_IM13_Pos         (13U)
+#define EXTI_IMR1_IM13_Msk         (0x1UL << EXTI_IMR1_IM13_Pos)               /*!< 0x00002000 */
+#define EXTI_IMR1_IM13             EXTI_IMR1_IM13_Msk                          /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR1_IM14_Pos         (14U)
+#define EXTI_IMR1_IM14_Msk         (0x1UL << EXTI_IMR1_IM14_Pos)               /*!< 0x00004000 */
+#define EXTI_IMR1_IM14             EXTI_IMR1_IM14_Msk                          /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR1_IM15_Pos         (15U)
+#define EXTI_IMR1_IM15_Msk         (0x1UL << EXTI_IMR1_IM15_Pos)               /*!< 0x00008000 */
+#define EXTI_IMR1_IM15             EXTI_IMR1_IM15_Msk                          /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR1_IM16_Pos         (16U)
+#define EXTI_IMR1_IM16_Msk         (0x1UL << EXTI_IMR1_IM16_Pos)               /*!< 0x00010000 */
+#define EXTI_IMR1_IM16             EXTI_IMR1_IM16_Msk                          /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR1_IM17_Pos         (17U)
+#define EXTI_IMR1_IM17_Msk         (0x1UL << EXTI_IMR1_IM17_Pos)               /*!< 0x00020000 */
+#define EXTI_IMR1_IM17             EXTI_IMR1_IM17_Msk                          /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR1_IM18_Pos         (18U)
+#define EXTI_IMR1_IM18_Msk         (0x1UL << EXTI_IMR1_IM18_Pos)               /*!< 0x00040000 */
+#define EXTI_IMR1_IM18             EXTI_IMR1_IM18_Msk                          /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR1_IM19_Pos         (19U)
+#define EXTI_IMR1_IM19_Msk         (0x1UL << EXTI_IMR1_IM19_Pos)               /*!< 0x00080000 */
+#define EXTI_IMR1_IM19             EXTI_IMR1_IM19_Msk                          /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR1_IM20_Pos         (20U)
+#define EXTI_IMR1_IM20_Msk         (0x1UL << EXTI_IMR1_IM20_Pos)               /*!< 0x00100000 */
+#define EXTI_IMR1_IM20             EXTI_IMR1_IM20_Msk                          /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR1_IM21_Pos         (21U)
+#define EXTI_IMR1_IM21_Msk         (0x1UL << EXTI_IMR1_IM21_Pos)               /*!< 0x00200000 */
+#define EXTI_IMR1_IM21             EXTI_IMR1_IM21_Msk                          /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR1_IM22_Pos         (22U)
+#define EXTI_IMR1_IM22_Msk         (0x1UL << EXTI_IMR1_IM22_Pos)               /*!< 0x00400000 */
+#define EXTI_IMR1_IM22             EXTI_IMR1_IM22_Msk                          /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR1_IM23_Pos         (23U)
+#define EXTI_IMR1_IM23_Msk         (0x1UL << EXTI_IMR1_IM23_Pos)               /*!< 0x00800000 */
+#define EXTI_IMR1_IM23             EXTI_IMR1_IM23_Msk                          /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR1_IM24_Pos         (24U)
+#define EXTI_IMR1_IM24_Msk         (0x1UL << EXTI_IMR1_IM24_Pos)               /*!< 0x01000000 */
+#define EXTI_IMR1_IM24             EXTI_IMR1_IM24_Msk                          /*!< Interrupt Mask on line 24 */
+#define EXTI_IMR1_IM25_Pos         (25U)
+#define EXTI_IMR1_IM25_Msk         (0x1UL << EXTI_IMR1_IM25_Pos)               /*!< 0x02000000 */
+#define EXTI_IMR1_IM25             EXTI_IMR1_IM25_Msk                          /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR1_IM26_Pos         (26U)
+#define EXTI_IMR1_IM26_Msk         (0x1UL << EXTI_IMR1_IM26_Pos)               /*!< 0x04000000 */
+#define EXTI_IMR1_IM26             EXTI_IMR1_IM26_Msk                          /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR1_IM27_Pos         (27U)
+#define EXTI_IMR1_IM27_Msk         (0x1UL << EXTI_IMR1_IM27_Pos)               /*!< 0x08000000 */
+#define EXTI_IMR1_IM27             EXTI_IMR1_IM27_Msk                          /*!< Interrupt Mask on line 27 */
+#define EXTI_IMR1_IM28_Pos         (28U)
+#define EXTI_IMR1_IM28_Msk         (0x1UL << EXTI_IMR1_IM28_Pos)               /*!< 0x10000000 */
+#define EXTI_IMR1_IM28             EXTI_IMR1_IM28_Msk                          /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR1_IM29_Pos         (29U)
+#define EXTI_IMR1_IM29_Msk         (0x1UL << EXTI_IMR1_IM29_Pos)               /*!< 0x20000000 */
+#define EXTI_IMR1_IM29             EXTI_IMR1_IM29_Msk                          /*!< Interrupt Mask on line 29 */
+#define EXTI_IMR1_IM30_Pos         (30U)
+#define EXTI_IMR1_IM30_Msk         (0x1UL << EXTI_IMR1_IM30_Pos)               /*!< 0x40000000 */
+#define EXTI_IMR1_IM30             EXTI_IMR1_IM30_Msk                          /*!< Interrupt Mask on line 30 */
+#define EXTI_IMR1_IM31_Pos         (31U)
+#define EXTI_IMR1_IM31_Msk         (0x1UL << EXTI_IMR1_IM31_Pos)               /*!< 0x80000000 */
+#define EXTI_IMR1_IM31             EXTI_IMR1_IM31_Msk                          /*!< Interrupt Mask on line 31 */
+
+/*******************  Bit definition for EXTI_EMR1 register  *******************/
+#define EXTI_EMR1_EM_Pos           (0U)
+#define EXTI_EMR1_EM_Msk           (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos)          /*!< 0xFFFFFFFF */
+#define EXTI_EMR1_EM               EXTI_EMR1_EM_Msk                            /*!< Event Mask */
+#define EXTI_EMR1_EM0_Pos          (0U)
+#define EXTI_EMR1_EM0_Msk          (0x1UL << EXTI_EMR1_EM0_Pos)                /*!< 0x00000001 */
+#define EXTI_EMR1_EM0              EXTI_EMR1_EM0_Msk                           /*!< Event Mask on line 0 */
+#define EXTI_EMR1_EM1_Pos          (1U)
+#define EXTI_EMR1_EM1_Msk          (0x1UL << EXTI_EMR1_EM1_Pos)                /*!< 0x00000002 */
+#define EXTI_EMR1_EM1              EXTI_EMR1_EM1_Msk                           /*!< Event Mask on line 1 */
+#define EXTI_EMR1_EM2_Pos          (2U)
+#define EXTI_EMR1_EM2_Msk          (0x1UL << EXTI_EMR1_EM2_Pos)                /*!< 0x00000004 */
+#define EXTI_EMR1_EM2              EXTI_EMR1_EM2_Msk                           /*!< Event Mask on line 2 */
+#define EXTI_EMR1_EM3_Pos          (3U)
+#define EXTI_EMR1_EM3_Msk          (0x1UL << EXTI_EMR1_EM3_Pos)                /*!< 0x00000008 */
+#define EXTI_EMR1_EM3              EXTI_EMR1_EM3_Msk                           /*!< Event Mask on line 3 */
+#define EXTI_EMR1_EM4_Pos          (4U)
+#define EXTI_EMR1_EM4_Msk          (0x1UL << EXTI_EMR1_EM4_Pos)                /*!< 0x00000010 */
+#define EXTI_EMR1_EM4              EXTI_EMR1_EM4_Msk                           /*!< Event Mask on line 4 */
+#define EXTI_EMR1_EM5_Pos          (5U)
+#define EXTI_EMR1_EM5_Msk          (0x1UL << EXTI_EMR1_EM5_Pos)                /*!< 0x00000020 */
+#define EXTI_EMR1_EM5              EXTI_EMR1_EM5_Msk                           /*!< Event Mask on line 5 */
+#define EXTI_EMR1_EM6_Pos          (6U)
+#define EXTI_EMR1_EM6_Msk          (0x1UL << EXTI_EMR1_EM6_Pos)                /*!< 0x00000040 */
+#define EXTI_EMR1_EM6              EXTI_EMR1_EM6_Msk                           /*!< Event Mask on line 6 */
+#define EXTI_EMR1_EM7_Pos          (7U)
+#define EXTI_EMR1_EM7_Msk          (0x1UL << EXTI_EMR1_EM7_Pos)                /*!< 0x00000080 */
+#define EXTI_EMR1_EM7              EXTI_EMR1_EM7_Msk                           /*!< Event Mask on line 7 */
+#define EXTI_EMR1_EM8_Pos          (8U)
+#define EXTI_EMR1_EM8_Msk          (0x1UL << EXTI_EMR1_EM8_Pos)                /*!< 0x00000100 */
+#define EXTI_EMR1_EM8              EXTI_EMR1_EM8_Msk                           /*!< Event Mask on line 8 */
+#define EXTI_EMR1_EM9_Pos          (9U)
+#define EXTI_EMR1_EM9_Msk          (0x1UL << EXTI_EMR1_EM9_Pos)                /*!< 0x00000200 */
+#define EXTI_EMR1_EM9              EXTI_EMR1_EM9_Msk                           /*!< Event Mask on line 9 */
+#define EXTI_EMR1_EM10_Pos         (10U)
+#define EXTI_EMR1_EM10_Msk         (0x1UL << EXTI_EMR1_EM10_Pos)               /*!< 0x00000400 */
+#define EXTI_EMR1_EM10             EXTI_EMR1_EM10_Msk                          /*!< Event Mask on line 10 */
+#define EXTI_EMR1_EM11_Pos         (11U)
+#define EXTI_EMR1_EM11_Msk         (0x1UL << EXTI_EMR1_EM11_Pos)               /*!< 0x00000800 */
+#define EXTI_EMR1_EM11             EXTI_EMR1_EM11_Msk                          /*!< Event Mask on line 11 */
+#define EXTI_EMR1_EM12_Pos         (12U)
+#define EXTI_EMR1_EM12_Msk         (0x1UL << EXTI_EMR1_EM12_Pos)               /*!< 0x00001000 */
+#define EXTI_EMR1_EM12             EXTI_EMR1_EM12_Msk                          /*!< Event Mask on line 12 */
+#define EXTI_EMR1_EM13_Pos         (13U)
+#define EXTI_EMR1_EM13_Msk         (0x1UL << EXTI_EMR1_EM13_Pos)               /*!< 0x00002000 */
+#define EXTI_EMR1_EM13             EXTI_EMR1_EM13_Msk                          /*!< Event Mask on line 13 */
+#define EXTI_EMR1_EM14_Pos         (14U)
+#define EXTI_EMR1_EM14_Msk         (0x1UL << EXTI_EMR1_EM14_Pos)               /*!< 0x00004000 */
+#define EXTI_EMR1_EM14             EXTI_EMR1_EM14_Msk                          /*!< Event Mask on line 14 */
+#define EXTI_EMR1_EM15_Pos         (15U)
+#define EXTI_EMR1_EM15_Msk         (0x1UL << EXTI_EMR1_EM15_Pos)               /*!< 0x00008000 */
+#define EXTI_EMR1_EM15             EXTI_EMR1_EM15_Msk                          /*!< Event Mask on line 15 */
+#define EXTI_EMR1_EM16_Pos         (16U)
+#define EXTI_EMR1_EM16_Msk         (0x1UL << EXTI_EMR1_EM16_Pos)               /*!< 0x00010000 */
+#define EXTI_EMR1_EM16             EXTI_EMR1_EM16_Msk                          /*!< Event Mask on line 16 */
+#define EXTI_EMR1_EM17_Pos         (17U)
+#define EXTI_EMR1_EM17_Msk         (0x1UL << EXTI_EMR1_EM17_Pos)               /*!< 0x00020000 */
+#define EXTI_EMR1_EM17             EXTI_EMR1_EM17_Msk                          /*!< Event Mask on line 17 */
+#define EXTI_EMR1_EM18_Pos         (18U)
+#define EXTI_EMR1_EM18_Msk         (0x1UL << EXTI_EMR1_EM18_Pos)               /*!< 0x00040000 */
+#define EXTI_EMR1_EM18             EXTI_EMR1_EM18_Msk                          /*!< Event Mask on line 18 */
+#define EXTI_EMR1_EM20_Pos         (20U)
+#define EXTI_EMR1_EM20_Msk         (0x1UL << EXTI_EMR1_EM20_Pos)               /*!< 0x00100000 */
+#define EXTI_EMR1_EM20             EXTI_EMR1_EM20_Msk                          /*!< Event Mask on line 20 */
+#define EXTI_EMR1_EM21_Pos         (21U)
+#define EXTI_EMR1_EM21_Msk         (0x1UL << EXTI_EMR1_EM21_Pos)               /*!< 0x00200000 */
+#define EXTI_EMR1_EM21             EXTI_EMR1_EM21_Msk                          /*!< Event Mask on line 21 */
+#define EXTI_EMR1_EM22_Pos         (22U)
+#define EXTI_EMR1_EM22_Msk         (0x1UL << EXTI_EMR1_EM22_Pos)               /*!< 0x00400000 */
+#define EXTI_EMR1_EM22             EXTI_EMR1_EM22_Msk                          /*!< Event Mask on line 22 */
+#define EXTI_EMR1_EM23_Pos         (23U)
+#define EXTI_EMR1_EM23_Msk         (0x1UL << EXTI_EMR1_EM23_Pos)               /*!< 0x00800000 */
+#define EXTI_EMR1_EM23             EXTI_EMR1_EM23_Msk                          /*!< Event Mask on line 23 */
+#define EXTI_EMR1_EM24_Pos         (24U)
+#define EXTI_EMR1_EM24_Msk         (0x1UL << EXTI_EMR1_EM24_Pos)               /*!< 0x01000000 */
+#define EXTI_EMR1_EM24             EXTI_EMR1_EM24_Msk                          /*!< Event Mask on line 24 */
+#define EXTI_EMR1_EM25_Pos         (25U)
+#define EXTI_EMR1_EM25_Msk         (0x1UL << EXTI_EMR1_EM25_Pos)               /*!< 0x02000000 */
+#define EXTI_EMR1_EM25             EXTI_EMR1_EM25_Msk                          /*!< Event Mask on line 25 */
+#define EXTI_EMR1_EM26_Pos         (26U)
+#define EXTI_EMR1_EM26_Msk         (0x1UL << EXTI_EMR1_EM26_Pos)               /*!< 0x04000000 */
+#define EXTI_EMR1_EM26             EXTI_EMR1_EM26_Msk                          /*!< Event Mask on line 26 */
+#define EXTI_EMR1_EM27_Pos         (27U)
+#define EXTI_EMR1_EM27_Msk         (0x1UL << EXTI_EMR1_EM27_Pos)               /*!< 0x08000000 */
+#define EXTI_EMR1_EM27             EXTI_EMR1_EM27_Msk                          /*!< Event Mask on line 27 */
+#define EXTI_EMR1_EM28_Pos         (28U)
+#define EXTI_EMR1_EM28_Msk         (0x1UL << EXTI_EMR1_EM28_Pos)               /*!< 0x10000000 */
+#define EXTI_EMR1_EM28             EXTI_EMR1_EM28_Msk                          /*!< Event Mask on line 28 */
+#define EXTI_EMR1_EM29_Pos         (29U)
+#define EXTI_EMR1_EM29_Msk         (0x1UL << EXTI_EMR1_EM29_Pos)               /*!< 0x20000000 */
+#define EXTI_EMR1_EM29             EXTI_EMR1_EM29_Msk                          /*!< Event Mask on line 29 */
+#define EXTI_EMR1_EM30_Pos         (30U)
+#define EXTI_EMR1_EM30_Msk         (0x1UL << EXTI_EMR1_EM30_Pos)               /*!< 0x40000000 */
+#define EXTI_EMR1_EM30             EXTI_EMR1_EM30_Msk                          /*!< Event Mask on line 30 */
+#define EXTI_EMR1_EM31_Pos         (31U)
+#define EXTI_EMR1_EM31_Msk         (0x1UL << EXTI_EMR1_EM31_Pos)               /*!< 0x80000000 */
+#define EXTI_EMR1_EM31             EXTI_EMR1_EM31_Msk                          /*!< Event Mask on line 31 */
+
+/*******************  Bit definition for EXTI_PR1 register  ********************/
+#define EXTI_PR1_PR_Pos            (0U)
+#define EXTI_PR1_PR_Msk            (0x3FFFFFUL << EXTI_PR1_PR_Pos)             /*!< 0x003FFFFF */
+#define EXTI_PR1_PR                EXTI_PR1_PR_Msk                             /*!< Pending bit */
+#define EXTI_PR1_PR0_Pos           (0U)
+#define EXTI_PR1_PR0_Msk           (0x1UL << EXTI_PR1_PR0_Pos)                 /*!< 0x00000001 */
+#define EXTI_PR1_PR0               EXTI_PR1_PR0_Msk                            /*!< Pending bit for line 0 */
+#define EXTI_PR1_PR1_Pos           (1U)
+#define EXTI_PR1_PR1_Msk           (0x1UL << EXTI_PR1_PR1_Pos)                 /*!< 0x00000002 */
+#define EXTI_PR1_PR1               EXTI_PR1_PR1_Msk                            /*!< Pending bit for line 1 */
+#define EXTI_PR1_PR2_Pos           (2U)
+#define EXTI_PR1_PR2_Msk           (0x1UL << EXTI_PR1_PR2_Pos)                 /*!< 0x00000004 */
+#define EXTI_PR1_PR2               EXTI_PR1_PR2_Msk                            /*!< Pending bit for line 2 */
+#define EXTI_PR1_PR3_Pos           (3U)
+#define EXTI_PR1_PR3_Msk           (0x1UL << EXTI_PR1_PR3_Pos)                 /*!< 0x00000008 */
+#define EXTI_PR1_PR3               EXTI_PR1_PR3_Msk                            /*!< Pending bit for line 3 */
+#define EXTI_PR1_PR4_Pos           (4U)
+#define EXTI_PR1_PR4_Msk           (0x1UL << EXTI_PR1_PR4_Pos)                 /*!< 0x00000010 */
+#define EXTI_PR1_PR4               EXTI_PR1_PR4_Msk                            /*!< Pending bit for line 4 */
+#define EXTI_PR1_PR5_Pos           (5U)
+#define EXTI_PR1_PR5_Msk           (0x1UL << EXTI_PR1_PR5_Pos)                 /*!< 0x00000020 */
+#define EXTI_PR1_PR5               EXTI_PR1_PR5_Msk                            /*!< Pending bit for line 5 */
+#define EXTI_PR1_PR6_Pos           (6U)
+#define EXTI_PR1_PR6_Msk           (0x1UL << EXTI_PR1_PR6_Pos)                 /*!< 0x00000040 */
+#define EXTI_PR1_PR6               EXTI_PR1_PR6_Msk                            /*!< Pending bit for line 6 */
+#define EXTI_PR1_PR7_Pos           (7U)
+#define EXTI_PR1_PR7_Msk           (0x1UL << EXTI_PR1_PR7_Pos)                 /*!< 0x00000080 */
+#define EXTI_PR1_PR7               EXTI_PR1_PR7_Msk                            /*!< Pending bit for line 7 */
+#define EXTI_PR1_PR8_Pos           (8U)
+#define EXTI_PR1_PR8_Msk           (0x1UL << EXTI_PR1_PR8_Pos)                 /*!< 0x00000100 */
+#define EXTI_PR1_PR8               EXTI_PR1_PR8_Msk                            /*!< Pending bit for line 8 */
+#define EXTI_PR1_PR9_Pos           (9U)
+#define EXTI_PR1_PR9_Msk           (0x1UL << EXTI_PR1_PR9_Pos)                 /*!< 0x00000200 */
+#define EXTI_PR1_PR9               EXTI_PR1_PR9_Msk                            /*!< Pending bit for line 9 */
+#define EXTI_PR1_PR10_Pos          (10U)
+#define EXTI_PR1_PR10_Msk          (0x1UL << EXTI_PR1_PR10_Pos)                /*!< 0x00000400 */
+#define EXTI_PR1_PR10              EXTI_PR1_PR10_Msk                           /*!< Pending bit for line 10 */
+#define EXTI_PR1_PR11_Pos          (11U)
+#define EXTI_PR1_PR11_Msk          (0x1UL << EXTI_PR1_PR11_Pos)                /*!< 0x00000800 */
+#define EXTI_PR1_PR11              EXTI_PR1_PR11_Msk                           /*!< Pending bit for line 11 */
+#define EXTI_PR1_PR12_Pos          (12U)
+#define EXTI_PR1_PR12_Msk          (0x1UL << EXTI_PR1_PR12_Pos)                /*!< 0x00001000 */
+#define EXTI_PR1_PR12              EXTI_PR1_PR12_Msk                           /*!< Pending bit for line 12 */
+#define EXTI_PR1_PR13_Pos          (13U)
+#define EXTI_PR1_PR13_Msk          (0x1UL << EXTI_PR1_PR13_Pos)                /*!< 0x00002000 */
+#define EXTI_PR1_PR13              EXTI_PR1_PR13_Msk                           /*!< Pending bit for line 13 */
+#define EXTI_PR1_PR14_Pos          (14U)
+#define EXTI_PR1_PR14_Msk          (0x1UL << EXTI_PR1_PR14_Pos)                /*!< 0x00004000 */
+#define EXTI_PR1_PR14              EXTI_PR1_PR14_Msk                           /*!< Pending bit for line 14 */
+#define EXTI_PR1_PR15_Pos          (15U)
+#define EXTI_PR1_PR15_Msk          (0x1UL << EXTI_PR1_PR15_Pos)                /*!< 0x00008000 */
+#define EXTI_PR1_PR15              EXTI_PR1_PR15_Msk                           /*!< Pending bit for line 15 */
+#define EXTI_PR1_PR16_Pos          (16U)
+#define EXTI_PR1_PR16_Msk          (0x1UL << EXTI_PR1_PR16_Pos)                /*!< 0x00010000 */
+#define EXTI_PR1_PR16              EXTI_PR1_PR16_Msk                           /*!< Pending bit for line 16 */
+#define EXTI_PR1_PR17_Pos          (17U)
+#define EXTI_PR1_PR17_Msk          (0x1UL << EXTI_PR1_PR17_Pos)                /*!< 0x00020000 */
+#define EXTI_PR1_PR17              EXTI_PR1_PR17_Msk                           /*!< Pending bit for line 17 */
+#define EXTI_PR1_PR18_Pos          (18U)
+#define EXTI_PR1_PR18_Msk          (0x1UL << EXTI_PR1_PR18_Pos)                /*!< 0x00040000 */
+#define EXTI_PR1_PR18              EXTI_PR1_PR18_Msk                           /*!< Pending bit for line 18 */
+#define EXTI_PR1_PR19_Pos          (19U)
+#define EXTI_PR1_PR19_Msk          (0x1UL << EXTI_PR1_PR19_Pos)                /*!< 0x00080000 */
+#define EXTI_PR1_PR19              EXTI_PR1_PR19_Msk                           /*!< Pending bit for line 19 */
+#define EXTI_PR1_PR20_Pos          (20U)
+#define EXTI_PR1_PR20_Msk          (0x1UL << EXTI_PR1_PR20_Pos)                /*!< 0x00100000 */
+#define EXTI_PR1_PR20              EXTI_PR1_PR20_Msk                           /*!< Pending bit for line 20 */
+#define EXTI_PR1_PR21_Pos          (21U)
+#define EXTI_PR1_PR21_Msk          (0x1UL << EXTI_PR1_PR21_Pos)                /*!< 0x00200000 */
+#define EXTI_PR1_PR21              EXTI_PR1_PR21_Msk                           /*!< Pending bit for line 21 */
+
+/*******************  Bit definition for EXTI_IMR2 register  *******************/
+#define EXTI_IMR2_IM_Pos           (0U)
+#define EXTI_IMR2_IM_Msk           (0xFFFFDFFFUL << EXTI_IMR2_IM_Pos)          /*!< 0xFFFFDFFF */
+#define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            /*!< Interrupt Mask */
+#define EXTI_IMR2_IM32_Pos         (0U)
+#define EXTI_IMR2_IM32_Msk         (0x1UL << EXTI_IMR2_IM32_Pos)               /*!< 0x00000001 */
+#define EXTI_IMR2_IM32             EXTI_IMR2_IM32_Msk                          /*!< Interrupt Mask on line 32 */
+#define EXTI_IMR2_IM33_Pos         (1U)
+#define EXTI_IMR2_IM33_Msk         (0x1UL << EXTI_IMR2_IM33_Pos)               /*!< 0x00000002 */
+#define EXTI_IMR2_IM33             EXTI_IMR2_IM33_Msk                          /*!< Interrupt Mask on line 33 */
+#define EXTI_IMR2_IM34_Pos         (2U)
+#define EXTI_IMR2_IM34_Msk         (0x1UL << EXTI_IMR2_IM34_Pos)               /*!< 0x00000004 */
+#define EXTI_IMR2_IM34             EXTI_IMR2_IM34_Msk                          /*!< Interrupt Mask on line 34 */
+#define EXTI_IMR2_IM35_Pos         (3U)
+#define EXTI_IMR2_IM35_Msk         (0x1UL << EXTI_IMR2_IM35_Pos)               /*!< 0x00000008 */
+#define EXTI_IMR2_IM35             EXTI_IMR2_IM35_Msk                          /*!< Interrupt Mask on line 35 */
+#define EXTI_IMR2_IM36_Pos         (4U)
+#define EXTI_IMR2_IM36_Msk         (0x1UL << EXTI_IMR2_IM36_Pos)               /*!< 0x00000010 */
+#define EXTI_IMR2_IM36             EXTI_IMR2_IM36_Msk                          /*!< Interrupt Mask on line 36 */
+#define EXTI_IMR2_IM37_Pos         (5U)
+#define EXTI_IMR2_IM37_Msk         (0x1UL << EXTI_IMR2_IM37_Pos)               /*!< 0x00000020 */
+#define EXTI_IMR2_IM37             EXTI_IMR2_IM37_Msk                          /*!< Interrupt Mask on line 37 */
+#define EXTI_IMR2_IM38_Pos         (6U)
+#define EXTI_IMR2_IM38_Msk         (0x1UL << EXTI_IMR2_IM38_Pos)               /*!< 0x00000040 */
+#define EXTI_IMR2_IM38             EXTI_IMR2_IM38_Msk                          /*!< Interrupt Mask on line 38 */
+#define EXTI_IMR2_IM39_Pos         (7U)
+#define EXTI_IMR2_IM39_Msk         (0x1UL << EXTI_IMR2_IM39_Pos)               /*!< 0x00000080 */
+#define EXTI_IMR2_IM39             EXTI_IMR2_IM39_Msk                          /*!< Interrupt Mask on line 39 */
+#define EXTI_IMR2_IM40_Pos         (8U)
+#define EXTI_IMR2_IM40_Msk         (0x1UL << EXTI_IMR2_IM40_Pos)               /*!< 0x00000100 */
+#define EXTI_IMR2_IM40             EXTI_IMR2_IM40_Msk                          /*!< Interrupt Mask on line 40 */
+#define EXTI_IMR2_IM41_Pos         (9U)
+#define EXTI_IMR2_IM41_Msk         (0x1UL << EXTI_IMR2_IM41_Pos)               /*!< 0x00000200 */
+#define EXTI_IMR2_IM41             EXTI_IMR2_IM41_Msk                          /*!< Interrupt Mask on line 41 */
+#define EXTI_IMR2_IM42_Pos         (10U)
+#define EXTI_IMR2_IM42_Msk         (0x1UL << EXTI_IMR2_IM42_Pos)               /*!< 0x00000400 */
+#define EXTI_IMR2_IM42             EXTI_IMR2_IM42_Msk                          /*!< Interrupt Mask on line 42 */
+#define EXTI_IMR2_IM43_Pos         (11U)
+#define EXTI_IMR2_IM43_Msk         (0x1UL << EXTI_IMR2_IM43_Pos)               /*!< 0x00000800 */
+#define EXTI_IMR2_IM43             EXTI_IMR2_IM43_Msk                          /*!< Interrupt Mask on line 43 */
+#define EXTI_IMR2_IM44_Pos         (12U)
+#define EXTI_IMR2_IM44_Msk         (0x1UL << EXTI_IMR2_IM44_Pos)               /*!< 0x00001000 */
+#define EXTI_IMR2_IM44             EXTI_IMR2_IM44_Msk                          /*!< Interrupt Mask on line 44 */
+#define EXTI_IMR2_IM46_Pos         (14U)
+#define EXTI_IMR2_IM46_Msk         (0x1UL << EXTI_IMR2_IM46_Pos)               /*!< 0x00004000 */
+#define EXTI_IMR2_IM46             EXTI_IMR2_IM46_Msk                          /*!< Interrupt Mask on line 46 */
+#define EXTI_IMR2_IM47_Pos         (15U)
+#define EXTI_IMR2_IM47_Msk         (0x1UL << EXTI_IMR2_IM47_Pos)               /*!< 0x00008000 */
+#define EXTI_IMR2_IM47             EXTI_IMR2_IM47_Msk                          /*!< Interrupt Mask on line 47 */
+#define EXTI_IMR2_IM48_Pos         (16U)
+#define EXTI_IMR2_IM48_Msk         (0x1UL << EXTI_IMR2_IM48_Pos)               /*!< 0x00010000 */
+#define EXTI_IMR2_IM48             EXTI_IMR2_IM48_Msk                          /*!< Interrupt Mask on line 48 */
+#define EXTI_IMR2_IM49_Pos         (17U)
+#define EXTI_IMR2_IM49_Msk         (0x1UL << EXTI_IMR2_IM49_Pos)               /*!< 0x00020000 */
+#define EXTI_IMR2_IM49             EXTI_IMR2_IM49_Msk                          /*!< Interrupt Mask on line 49 */
+#define EXTI_IMR2_IM50_Pos         (18U)
+#define EXTI_IMR2_IM50_Msk         (0x1UL << EXTI_IMR2_IM50_Pos)               /*!< 0x00040000 */
+#define EXTI_IMR2_IM50             EXTI_IMR2_IM50_Msk                          /*!< Interrupt Mask on line 50 */
+#define EXTI_IMR2_IM51_Pos         (19U)
+#define EXTI_IMR2_IM51_Msk         (0x1UL << EXTI_IMR2_IM51_Pos)               /*!< 0x00080000 */
+#define EXTI_IMR2_IM51             EXTI_IMR2_IM51_Msk                          /*!< Interrupt Mask on line 51 */
+#define EXTI_IMR2_IM52_Pos         (20U)
+#define EXTI_IMR2_IM52_Msk         (0x1UL << EXTI_IMR2_IM52_Pos)               /*!< 0x00100000 */
+#define EXTI_IMR2_IM52             EXTI_IMR2_IM52_Msk                          /*!< Interrupt Mask on line 52 */
+#define EXTI_IMR2_IM53_Pos         (21U)
+#define EXTI_IMR2_IM53_Msk         (0x1UL << EXTI_IMR2_IM53_Pos)               /*!< 0x00200000 */
+#define EXTI_IMR2_IM53             EXTI_IMR2_IM53_Msk                          /*!< Interrupt Mask on line 53 */
+#define EXTI_IMR2_IM54_Pos         (22U)
+#define EXTI_IMR2_IM54_Msk         (0x1UL << EXTI_IMR2_IM54_Pos)               /*!< 0x00400000 */
+#define EXTI_IMR2_IM54             EXTI_IMR2_IM54_Msk                          /*!< Interrupt Mask on line 54 */
+#define EXTI_IMR2_IM55_Pos         (23U)
+#define EXTI_IMR2_IM55_Msk         (0x1UL << EXTI_IMR2_IM55_Pos)               /*!< 0x00800000 */
+#define EXTI_IMR2_IM55             EXTI_IMR2_IM55_Msk                          /*!< Interrupt Mask on line 55 */
+#define EXTI_IMR2_IM56_Pos         (24U)
+#define EXTI_IMR2_IM56_Msk         (0x1UL << EXTI_IMR2_IM56_Pos)               /*!< 0x01000000 */
+#define EXTI_IMR2_IM56             EXTI_IMR2_IM56_Msk                          /*!< Interrupt Mask on line 56 */
+#define EXTI_IMR2_IM57_Pos         (25U)
+#define EXTI_IMR2_IM57_Msk         (0x1UL << EXTI_IMR2_IM57_Pos)               /*!< 0x02000000 */
+#define EXTI_IMR2_IM57             EXTI_IMR2_IM57_Msk                          /*!< Interrupt Mask on line 57 */
+#define EXTI_IMR2_IM58_Pos         (26U)
+#define EXTI_IMR2_IM58_Msk         (0x1UL << EXTI_IMR2_IM58_Pos)               /*!< 0x04000000 */
+#define EXTI_IMR2_IM58             EXTI_IMR2_IM58_Msk                          /*!< Interrupt Mask on line 58 */
+#define EXTI_IMR2_IM59_Pos         (27U)
+#define EXTI_IMR2_IM59_Msk         (0x1UL << EXTI_IMR2_IM59_Pos)               /*!< 0x08000000 */
+#define EXTI_IMR2_IM59             EXTI_IMR2_IM59_Msk                          /*!< Interrupt Mask on line 59 */
+#define EXTI_IMR2_IM60_Pos         (28U)
+#define EXTI_IMR2_IM60_Msk         (0x1UL << EXTI_IMR2_IM60_Pos)               /*!< 0x10000000 */
+#define EXTI_IMR2_IM60             EXTI_IMR2_IM60_Msk                          /*!< Interrupt Mask on line 60 */
+#define EXTI_IMR2_IM61_Pos         (29U)
+#define EXTI_IMR2_IM61_Msk         (0x1UL << EXTI_IMR2_IM61_Pos)               /*!< 0x20000000 */
+#define EXTI_IMR2_IM61             EXTI_IMR2_IM61_Msk                          /*!< Interrupt Mask on line 61 */
+#define EXTI_IMR2_IM62_Pos         (30U)
+#define EXTI_IMR2_IM62_Msk         (0x1UL << EXTI_IMR2_IM62_Pos)               /*!< 0x40000000 */
+#define EXTI_IMR2_IM62             EXTI_IMR2_IM62_Msk                          /*!< Interrupt Mask on line 62 */
+#define EXTI_IMR2_IM63_Pos         (31U)
+#define EXTI_IMR2_IM63_Msk         (0x1UL << EXTI_IMR2_IM63_Pos)               /*!< 0x80000000 */
+#define EXTI_IMR2_IM63             EXTI_IMR2_IM63_Msk                          /*!< Interrupt Mask on line 63 */
+
+/*******************  Bit definition for EXTI_EMR2 register  *******************/
+#define EXTI_EMR2_EM_Pos           (0U)
+#define EXTI_EMR2_EM_Msk           (0xFFFFDFFFUL << EXTI_EMR2_EM_Pos)          /*!< 0xFFFFDFFF */
+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            /*!< Event Mask */
+#define EXTI_EMR2_EM32_Pos         (0U)
+#define EXTI_EMR2_EM32_Msk         (0x1UL << EXTI_EMR2_EM32_Pos)               /*!< 0x00000001 */
+#define EXTI_EMR2_EM32             EXTI_EMR2_EM32_Msk                          /*!< Event Mask on line 32*/
+#define EXTI_EMR2_EM33_Pos         (1U)
+#define EXTI_EMR2_EM33_Msk         (0x1UL << EXTI_EMR2_EM33_Pos)               /*!< 0x00000002 */
+#define EXTI_EMR2_EM33             EXTI_EMR2_EM33_Msk                          /*!< Event Mask on line 33*/
+#define EXTI_EMR2_EM34_Pos         (2U)
+#define EXTI_EMR2_EM34_Msk         (0x1UL << EXTI_EMR2_EM34_Pos)               /*!< 0x00000004 */
+#define EXTI_EMR2_EM34             EXTI_EMR2_EM34_Msk                          /*!< Event Mask on line 34*/
+#define EXTI_EMR2_EM35_Pos         (3U)
+#define EXTI_EMR2_EM35_Msk         (0x1UL << EXTI_EMR2_EM35_Pos)               /*!< 0x00000008 */
+#define EXTI_EMR2_EM35             EXTI_EMR2_EM35_Msk                          /*!< Event Mask on line 35*/
+#define EXTI_EMR2_EM36_Pos         (4U)
+#define EXTI_EMR2_EM36_Msk         (0x1UL << EXTI_EMR2_EM36_Pos)               /*!< 0x00000010 */
+#define EXTI_EMR2_EM36             EXTI_EMR2_EM36_Msk                          /*!< Event Mask on line 36*/
+#define EXTI_EMR2_EM37_Pos         (5U)
+#define EXTI_EMR2_EM37_Msk         (0x1UL << EXTI_EMR2_EM37_Pos)               /*!< 0x00000020 */
+#define EXTI_EMR2_EM37             EXTI_EMR2_EM37_Msk                          /*!< Event Mask on line 37*/
+#define EXTI_EMR2_EM38_Pos         (6U)
+#define EXTI_EMR2_EM38_Msk         (0x1UL << EXTI_EMR2_EM38_Pos)               /*!< 0x00000040 */
+#define EXTI_EMR2_EM38             EXTI_EMR2_EM38_Msk                          /*!< Event Mask on line 38*/
+#define EXTI_EMR2_EM39_Pos         (7U)
+#define EXTI_EMR2_EM39_Msk         (0x1UL << EXTI_EMR2_EM39_Pos)               /*!< 0x00000080 */
+#define EXTI_EMR2_EM39             EXTI_EMR2_EM39_Msk                          /*!< Event Mask on line 39*/
+#define EXTI_EMR2_EM40_Pos         (8U)
+#define EXTI_EMR2_EM40_Msk         (0x1UL << EXTI_EMR2_EM40_Pos)               /*!< 0x00000100 */
+#define EXTI_EMR2_EM40             EXTI_EMR2_EM40_Msk                          /*!< Event Mask on line 40*/
+#define EXTI_EMR2_EM41_Pos         (9U)
+#define EXTI_EMR2_EM41_Msk         (0x1UL << EXTI_EMR2_EM41_Pos)               /*!< 0x00000200 */
+#define EXTI_EMR2_EM41             EXTI_EMR2_EM41_Msk                          /*!< Event Mask on line 41*/
+#define EXTI_EMR2_EM42_Pos         (10U)
+#define EXTI_EMR2_EM42_Msk         (0x1UL << EXTI_EMR2_EM42_Pos)               /*!< 0x00000400 */
+#define EXTI_EMR2_EM42             EXTI_EMR2_EM42_Msk                          /*!< Event Mask on line 42 */
+#define EXTI_EMR2_EM43_Pos         (11U)
+#define EXTI_EMR2_EM43_Msk         (0x1UL << EXTI_EMR2_EM43_Pos)               /*!< 0x00000800 */
+#define EXTI_EMR2_EM43             EXTI_EMR2_EM43_Msk                          /*!< Event Mask on line 43 */
+#define EXTI_EMR2_EM44_Pos         (12U)
+#define EXTI_EMR2_EM44_Msk         (0x1UL << EXTI_EMR2_EM44_Pos)               /*!< 0x00001000 */
+#define EXTI_EMR2_EM44             EXTI_EMR2_EM44_Msk                          /*!< Event Mask on line 44 */
+#define EXTI_EMR2_EM46_Pos         (14U)
+#define EXTI_EMR2_EM46_Msk         (0x1UL << EXTI_EMR2_EM46_Pos)               /*!< 0x00004000 */
+#define EXTI_EMR2_EM46             EXTI_EMR2_EM46_Msk                          /*!< Event Mask on line 46 */
+#define EXTI_EMR2_EM47_Pos         (15U)
+#define EXTI_EMR2_EM47_Msk         (0x1UL << EXTI_EMR2_EM47_Pos)               /*!< 0x00008000 */
+#define EXTI_EMR2_EM47             EXTI_EMR2_EM47_Msk                          /*!< Event Mask on line 47 */
+#define EXTI_EMR2_EM48_Pos         (16U)
+#define EXTI_EMR2_EM48_Msk         (0x1UL << EXTI_EMR2_EM48_Pos)               /*!< 0x00010000 */
+#define EXTI_EMR2_EM48             EXTI_EMR2_EM48_Msk                          /*!< Event Mask on line 48 */
+#define EXTI_EMR2_EM49_Pos         (17U)
+#define EXTI_EMR2_EM49_Msk         (0x1UL << EXTI_EMR2_EM49_Pos)               /*!< 0x00020000 */
+#define EXTI_EMR2_EM49             EXTI_EMR2_EM49_Msk                          /*!< Event Mask on line 49 */
+#define EXTI_EMR2_EM50_Pos         (18U)
+#define EXTI_EMR2_EM50_Msk         (0x1UL << EXTI_EMR2_EM50_Pos)               /*!< 0x00040000 */
+#define EXTI_EMR2_EM50             EXTI_EMR2_EM50_Msk                          /*!< Event Mask on line 50 */
+#define EXTI_EMR2_EM51_Pos         (19U)
+#define EXTI_EMR2_EM51_Msk         (0x1UL << EXTI_EMR2_EM51_Pos)               /*!< 0x00080000 */
+#define EXTI_EMR2_EM51             EXTI_EMR2_EM51_Msk                          /*!< Event Mask on line 51 */
+#define EXTI_EMR2_EM52_Pos         (20U)
+#define EXTI_EMR2_EM52_Msk         (0x1UL << EXTI_EMR2_EM52_Pos)               /*!< 0x00100000 */
+#define EXTI_EMR2_EM52             EXTI_EMR2_EM52_Msk                          /*!< Event Mask on line 52 */
+#define EXTI_EMR2_EM53_Pos         (21U)
+#define EXTI_EMR2_EM53_Msk         (0x1UL << EXTI_EMR2_EM53_Pos)               /*!< 0x00200000 */
+#define EXTI_EMR2_EM53             EXTI_EMR2_EM53_Msk                          /*!< Event Mask on line 53 */
+#define EXTI_EMR2_EM54_Pos         (22U)
+#define EXTI_EMR2_EM54_Msk         (0x1UL << EXTI_EMR2_EM54_Pos)               /*!< 0x00400000 */
+#define EXTI_EMR2_EM54             EXTI_EMR2_EM54_Msk                          /*!< Event Mask on line 54 */
+#define EXTI_EMR2_EM55_Pos         (23U)
+#define EXTI_EMR2_EM55_Msk         (0x1UL << EXTI_EMR2_EM55_Pos)               /*!< 0x00800000 */
+#define EXTI_EMR2_EM55             EXTI_EMR2_EM55_Msk                          /*!< Event Mask on line 55 */
+#define EXTI_EMR2_EM56_Pos         (24U)
+#define EXTI_EMR2_EM56_Msk         (0x1UL << EXTI_EMR2_EM56_Pos)               /*!< 0x01000000 */
+#define EXTI_EMR2_EM56             EXTI_EMR2_EM56_Msk                          /*!< Event Mask on line 56 */
+#define EXTI_EMR2_EM57_Pos         (25U)
+#define EXTI_EMR2_EM57_Msk         (0x1UL << EXTI_EMR2_EM57_Pos)               /*!< 0x02000000 */
+#define EXTI_EMR2_EM57             EXTI_EMR2_EM57_Msk                          /*!< Event Mask on line 57 */
+#define EXTI_EMR2_EM58_Pos         (26U)
+#define EXTI_EMR2_EM58_Msk         (0x1UL << EXTI_EMR2_EM58_Pos)               /*!< 0x04000000 */
+#define EXTI_EMR2_EM58             EXTI_EMR2_EM58_Msk                          /*!< Event Mask on line 58 */
+#define EXTI_EMR2_EM59_Pos         (27U)
+#define EXTI_EMR2_EM59_Msk         (0x1UL << EXTI_EMR2_EM59_Pos)               /*!< 0x08000000 */
+#define EXTI_EMR2_EM59             EXTI_EMR2_EM59_Msk                          /*!< Event Mask on line 59 */
+#define EXTI_EMR2_EM60_Pos         (28U)
+#define EXTI_EMR2_EM60_Msk         (0x1UL << EXTI_EMR2_EM60_Pos)               /*!< 0x10000000 */
+#define EXTI_EMR2_EM60             EXTI_EMR2_EM60_Msk                          /*!< Event Mask on line 60 */
+#define EXTI_EMR2_EM61_Pos         (29U)
+#define EXTI_EMR2_EM61_Msk         (0x1UL << EXTI_EMR2_EM61_Pos)               /*!< 0x20000000 */
+#define EXTI_EMR2_EM61             EXTI_EMR2_EM61_Msk                          /*!< Event Mask on line 61 */
+#define EXTI_EMR2_EM62_Pos         (30U)
+#define EXTI_EMR2_EM62_Msk         (0x1UL << EXTI_EMR2_EM62_Pos)               /*!< 0x40000000 */
+#define EXTI_EMR2_EM62             EXTI_EMR2_EM62_Msk                          /*!< Event Mask on line 62 */
+#define EXTI_EMR2_EM63_Pos         (31U)
+#define EXTI_EMR2_EM63_Msk         (0x1UL << EXTI_EMR2_EM63_Pos)               /*!< 0x80000000 */
+#define EXTI_EMR2_EM63             EXTI_EMR2_EM63_Msk                          /*!< Event Mask on line 63 */
+
+/*******************  Bit definition for EXTI_PR2 register  ********************/
+#define EXTI_PR2_PR_Pos            (17U)
+#define EXTI_PR2_PR_Msk            (0x5UL << EXTI_PR2_PR_Pos)                  /*!< 0x000A0000 */
+#define EXTI_PR2_PR                EXTI_PR2_PR_Msk                             /*!< Pending bit */
+#define EXTI_PR2_PR49_Pos          (17U)
+#define EXTI_PR2_PR49_Msk          (0x1UL << EXTI_PR2_PR49_Pos)                /*!< 0x00020000 */
+#define EXTI_PR2_PR49              EXTI_PR2_PR49_Msk                           /*!< Pending bit for line 49 */
+#define EXTI_PR2_PR51_Pos          (19U)
+#define EXTI_PR2_PR51_Msk          (0x1UL << EXTI_PR2_PR51_Pos)                /*!< 0x00080000 */
+#define EXTI_PR2_PR51              EXTI_PR2_PR51_Msk                           /*!< Pending bit for line 51 */
+
+/*******************  Bit definition for EXTI_IMR3 register  *******************/
+#define EXTI_IMR3_IM_Pos           (0U)
+#define EXTI_IMR3_IM_Msk           (0x00F5FFFFUL << EXTI_IMR3_IM_Pos)          /*!< 0x00F5FFFF */
+#define EXTI_IMR3_IM               EXTI_IMR3_IM_Msk                            /*!< Interrupt Mask */
+#define EXTI_IMR3_IM64_Pos         (0U)
+#define EXTI_IMR3_IM64_Msk         (0x1UL << EXTI_IMR3_IM64_Pos)               /*!< 0x00000001 */
+#define EXTI_IMR3_IM64             EXTI_IMR3_IM64_Msk                          /*!< Interrupt Mask on line 64 */
+#define EXTI_IMR3_IM65_Pos         (1U)
+#define EXTI_IMR3_IM65_Msk         (0x1UL << EXTI_IMR3_IM65_Pos)               /*!< 0x00000002 */
+#define EXTI_IMR3_IM65             EXTI_IMR3_IM65_Msk                          /*!< Interrupt Mask on line 65 */
+#define EXTI_IMR3_IM66_Pos         (2U)
+#define EXTI_IMR3_IM66_Msk         (0x1UL << EXTI_IMR3_IM66_Pos)               /*!< 0x00000004 */
+#define EXTI_IMR3_IM66             EXTI_IMR3_IM66_Msk                          /*!< Interrupt Mask on line 66 */
+#define EXTI_IMR3_IM67_Pos         (3U)
+#define EXTI_IMR3_IM67_Msk         (0x1UL << EXTI_IMR3_IM67_Pos)               /*!< 0x00000008 */
+#define EXTI_IMR3_IM67             EXTI_IMR3_IM67_Msk                          /*!< Interrupt Mask on line 67 */
+#define EXTI_IMR3_IM68_Pos         (4U)
+#define EXTI_IMR3_IM68_Msk         (0x1UL << EXTI_IMR3_IM68_Pos)               /*!< 0x00000010 */
+#define EXTI_IMR3_IM68             EXTI_IMR3_IM68_Msk                          /*!< Interrupt Mask on line 68 */
+#define EXTI_IMR3_IM69_Pos         (5U)
+#define EXTI_IMR3_IM69_Msk         (0x1UL << EXTI_IMR3_IM69_Pos)               /*!< 0x00000020 */
+#define EXTI_IMR3_IM69             EXTI_IMR3_IM69_Msk                          /*!< Interrupt Mask on line 69 */
+#define EXTI_IMR3_IM70_Pos         (6U)
+#define EXTI_IMR3_IM70_Msk         (0x1UL << EXTI_IMR3_IM70_Pos)               /*!< 0x00000040 */
+#define EXTI_IMR3_IM70             EXTI_IMR3_IM70_Msk                          /*!< Interrupt Mask on line 70 */
+#define EXTI_IMR3_IM71_Pos         (7U)
+#define EXTI_IMR3_IM71_Msk         (0x1UL << EXTI_IMR3_IM71_Pos)               /*!< 0x00000080 */
+#define EXTI_IMR3_IM71             EXTI_IMR3_IM71_Msk                          /*!< Interrupt Mask on line 71 */
+#define EXTI_IMR3_IM72_Pos         (8U)
+#define EXTI_IMR3_IM72_Msk         (0x1UL << EXTI_IMR3_IM72_Pos)               /*!< 0x00000100 */
+#define EXTI_IMR3_IM72             EXTI_IMR3_IM72_Msk                          /*!< Interrupt Mask on line 72 */
+#define EXTI_IMR3_IM73_Pos         (9U)
+#define EXTI_IMR3_IM73_Msk         (0x1UL << EXTI_IMR3_IM73_Pos)               /*!< 0x00000200 */
+#define EXTI_IMR3_IM73             EXTI_IMR3_IM73_Msk                          /*!< Interrupt Mask on line 73 */
+#define EXTI_IMR3_IM74_Pos         (10U)
+#define EXTI_IMR3_IM74_Msk         (0x1UL << EXTI_IMR3_IM74_Pos)               /*!< 0x00000400 */
+#define EXTI_IMR3_IM74             EXTI_IMR3_IM74_Msk                          /*!< Interrupt Mask on line 74 */
+#define EXTI_IMR3_IM75_Pos         (11U)
+#define EXTI_IMR3_IM75_Msk         (0x1UL << EXTI_IMR3_IM75_Pos)               /*!< 0x00000800 */
+#define EXTI_IMR3_IM75             EXTI_IMR3_IM75_Msk                          /*!< Interrupt Mask on line 75 */
+#define EXTI_IMR3_IM76_Pos         (12U)
+#define EXTI_IMR3_IM76_Msk         (0x1UL << EXTI_IMR3_IM76_Pos)               /*!< 0x00001000 */
+#define EXTI_IMR3_IM76             EXTI_IMR3_IM76_Msk                          /*!< Interrupt Mask on line 76 */
+#define EXTI_IMR3_IM77_Pos         (13U)
+#define EXTI_IMR3_IM77_Msk         (0x1UL << EXTI_IMR3_IM77_Pos)               /*!< 0x00002000 */
+#define EXTI_IMR3_IM77             EXTI_IMR3_IM77_Msk                          /*!< Interrupt Mask on line 77 */
+#define EXTI_IMR3_IM78_Pos         (14U)
+#define EXTI_IMR3_IM78_Msk         (0x1UL << EXTI_IMR3_IM78_Pos)               /*!< 0x00004000 */
+#define EXTI_IMR3_IM78             EXTI_IMR3_IM78_Msk                          /*!< Interrupt Mask on line 78 */
+#define EXTI_IMR3_IM79_Pos         (15U)
+#define EXTI_IMR3_IM79_Msk         (0x1UL << EXTI_IMR3_IM79_Pos)               /*!< 0x00008000 */
+#define EXTI_IMR3_IM79             EXTI_IMR3_IM79_Msk                          /*!< Interrupt Mask on line 79 */
+#define EXTI_IMR3_IM80_Pos         (16U)
+#define EXTI_IMR3_IM80_Msk         (0x1UL << EXTI_IMR3_IM80_Pos)               /*!< 0x00010000 */
+#define EXTI_IMR3_IM80             EXTI_IMR3_IM80_Msk                          /*!< Interrupt Mask on line 80 */
+#define EXTI_IMR3_IM82_Pos         (18U)
+#define EXTI_IMR3_IM82_Msk         (0x1UL << EXTI_IMR3_IM82_Pos)               /*!< 0x00040000 */
+#define EXTI_IMR3_IM82             EXTI_IMR3_IM82_Msk                          /*!< Interrupt Mask on line 82 */
+#define EXTI_IMR3_IM84_Pos         (20U)
+#define EXTI_IMR3_IM84_Msk         (0x1UL << EXTI_IMR3_IM84_Pos)               /*!< 0x00100000 */
+#define EXTI_IMR3_IM84             EXTI_IMR3_IM84_Msk                          /*!< Interrupt Mask on line 84 */
+#define EXTI_IMR3_IM85_Pos         (21U)
+#define EXTI_IMR3_IM85_Msk         (0x1UL << EXTI_IMR3_IM85_Pos)               /*!< 0x00200000 */
+#define EXTI_IMR3_IM85             EXTI_IMR3_IM85_Msk                          /*!< Interrupt Mask on line 85 */
+#define EXTI_IMR3_IM86_Pos         (22U)
+#define EXTI_IMR3_IM86_Msk         (0x1UL << EXTI_IMR3_IM86_Pos)               /*!< 0x00400000 */
+#define EXTI_IMR3_IM86             EXTI_IMR3_IM86_Msk                          /*!< Interrupt Mask on line 86 */
+#define EXTI_IMR3_IM87_Pos         (23U)
+#define EXTI_IMR3_IM87_Msk         (0x1UL << EXTI_IMR3_IM87_Pos)               /*!< 0x00800000 */
+#define EXTI_IMR3_IM87             EXTI_IMR3_IM87_Msk                          /*!< Interrupt Mask on line 87 */
+
+
+/*******************  Bit definition for EXTI_EMR3 register  *******************/
+#define EXTI_EMR3_EM_Pos           (0U)
+#define EXTI_EMR3_EM_Msk           (0x00F5FFFFUL << EXTI_EMR3_EM_Pos)          /*!< 0x00F5FFFF */
+#define EXTI_EMR3_EM               EXTI_EMR3_EM_Msk                            /*!< Event Mask           */
+#define EXTI_EMR3_EM64_Pos         (0U)
+#define EXTI_EMR3_EM64_Msk         (0x1UL << EXTI_EMR3_EM64_Pos)               /*!< 0x00000001 */
+#define EXTI_EMR3_EM64             EXTI_EMR3_EM64_Msk                          /*!< Event Mask on line 64*/
+#define EXTI_EMR3_EM65_Pos         (1U)
+#define EXTI_EMR3_EM65_Msk         (0x1UL << EXTI_EMR3_EM65_Pos)               /*!< 0x00000002 */
+#define EXTI_EMR3_EM65             EXTI_EMR3_EM65_Msk                          /*!< Event Mask on line 65*/
+#define EXTI_EMR3_EM66_Pos         (2U)
+#define EXTI_EMR3_EM66_Msk         (0x1UL << EXTI_EMR3_EM66_Pos)               /*!< 0x00000004 */
+#define EXTI_EMR3_EM66             EXTI_EMR3_EM66_Msk                          /*!< Event Mask on line 66*/
+#define EXTI_EMR3_EM67_Pos         (3U)
+#define EXTI_EMR3_EM67_Msk         (0x1UL << EXTI_EMR3_EM67_Pos)               /*!< 0x00000008 */
+#define EXTI_EMR3_EM67             EXTI_EMR3_EM67_Msk                          /*!< Event Mask on line 67*/
+#define EXTI_EMR3_EM68_Pos         (4U)
+#define EXTI_EMR3_EM68_Msk         (0x1UL << EXTI_EMR3_EM68_Pos)               /*!< 0x00000010 */
+#define EXTI_EMR3_EM68             EXTI_EMR3_EM68_Msk                          /*!< Event Mask on line 68*/
+#define EXTI_EMR3_EM69_Pos         (5U)
+#define EXTI_EMR3_EM69_Msk         (0x1UL << EXTI_EMR3_EM69_Pos)               /*!< 0x00000020 */
+#define EXTI_EMR3_EM69             EXTI_EMR3_EM69_Msk                          /*!< Event Mask on line 69*/
+#define EXTI_EMR3_EM70_Pos         (6U)
+#define EXTI_EMR3_EM70_Msk         (0x1UL << EXTI_EMR3_EM70_Pos)               /*!< 0x00000040 */
+#define EXTI_EMR3_EM70             EXTI_EMR3_EM70_Msk                          /*!< Event Mask on line 70*/
+#define EXTI_EMR3_EM71_Pos         (7U)
+#define EXTI_EMR3_EM71_Msk         (0x1UL << EXTI_EMR3_EM71_Pos)               /*!< 0x00000080 */
+#define EXTI_EMR3_EM71             EXTI_EMR3_EM71_Msk                          /*!< Event Mask on line 71*/
+#define EXTI_EMR3_EM72_Pos         (8U)
+#define EXTI_EMR3_EM72_Msk         (0x1UL << EXTI_EMR3_EM72_Pos)               /*!< 0x00000100 */
+#define EXTI_EMR3_EM72             EXTI_EMR3_EM72_Msk                          /*!< Event Mask on line 72*/
+#define EXTI_EMR3_EM73_Pos         (9U)
+#define EXTI_EMR3_EM73_Msk         (0x1UL << EXTI_EMR3_EM73_Pos)               /*!< 0x00000200 */
+#define EXTI_EMR3_EM73             EXTI_EMR3_EM73_Msk                          /*!< Event Mask on line 73*/
+#define EXTI_EMR3_EM74_Pos         (10U)
+#define EXTI_EMR3_EM74_Msk         (0x1UL << EXTI_EMR3_EM74_Pos)               /*!< 0x00000400 */
+#define EXTI_EMR3_EM74             EXTI_EMR3_EM74_Msk                          /*!< Event Mask on line 74 */
+#define EXTI_EMR3_EM75_Pos         (11U)
+#define EXTI_EMR3_EM75_Msk         (0x1UL << EXTI_EMR3_EM75_Pos)               /*!< 0x00000800 */
+#define EXTI_EMR3_EM75             EXTI_EMR3_EM75_Msk                          /*!< Event Mask on line 75 */
+#define EXTI_EMR3_EM76_Pos         (12U)
+#define EXTI_EMR3_EM76_Msk         (0x1UL << EXTI_EMR3_EM76_Pos)               /*!< 0x00001000 */
+#define EXTI_EMR3_EM76             EXTI_EMR3_EM76_Msk                          /*!< Event Mask on line 76 */
+#define EXTI_EMR3_EM77_Pos         (13U)
+#define EXTI_EMR3_EM77_Msk         (0x1UL << EXTI_EMR3_EM77_Pos)               /*!< 0x00002000 */
+#define EXTI_EMR3_EM77             EXTI_EMR3_EM77_Msk                          /*!< Event Mask on line 77 */
+#define EXTI_EMR3_EM78_Pos         (14U)
+#define EXTI_EMR3_EM78_Msk         (0x1UL << EXTI_EMR3_EM78_Pos)               /*!< 0x00004000 */
+#define EXTI_EMR3_EM78             EXTI_EMR3_EM78_Msk                          /*!< Event Mask on line 78 */
+#define EXTI_EMR3_EM79_Pos         (15U)
+#define EXTI_EMR3_EM79_Msk         (0x1UL << EXTI_EMR3_EM79_Pos)               /*!< 0x00008000 */
+#define EXTI_EMR3_EM79             EXTI_EMR3_EM79_Msk                          /*!< Event Mask on line 79 */
+#define EXTI_EMR3_EM80_Pos         (16U)
+#define EXTI_EMR3_EM80_Msk         (0x1UL << EXTI_EMR3_EM80_Pos)               /*!< 0x00010000 */
+#define EXTI_EMR3_EM80             EXTI_EMR3_EM80_Msk                          /*!< Event Mask on line 80 */
+#define EXTI_EMR3_EM81_Pos         (17U)
+#define EXTI_EMR3_EM81_Msk         (0x1UL << EXTI_EMR3_EM81_Pos)               /*!< 0x00020000 */
+#define EXTI_EMR3_EM81             EXTI_EMR3_EM81_Msk                          /*!< Event Mask on line 81 */
+#define EXTI_EMR3_EM82_Pos         (18U)
+#define EXTI_EMR3_EM82_Msk         (0x1UL << EXTI_EMR3_EM82_Pos)               /*!< 0x00040000 */
+#define EXTI_EMR3_EM82             EXTI_EMR3_EM82_Msk                          /*!< Event Mask on line 82 */
+#define EXTI_EMR3_EM84_Pos         (20U)
+#define EXTI_EMR3_EM84_Msk         (0x1UL << EXTI_EMR3_EM84_Pos)               /*!< 0x00100000 */
+#define EXTI_EMR3_EM84             EXTI_EMR3_EM84_Msk                          /*!< Event Mask on line 84 */
+#define EXTI_EMR3_EM85_Pos         (21U)
+#define EXTI_EMR3_EM85_Msk         (0x1UL << EXTI_EMR3_EM85_Pos)               /*!< 0x00200000 */
+#define EXTI_EMR3_EM85             EXTI_EMR3_EM85_Msk                          /*!< Event Mask on line 85 */
+#define EXTI_EMR3_EM86_Pos         (22U)
+#define EXTI_EMR3_EM86_Msk         (0x1UL << EXTI_EMR3_EM86_Pos)               /*!< 0x00400000 */
+#define EXTI_EMR3_EM86             EXTI_EMR3_EM86_Msk                          /*!< Event Mask on line 86 */
+#define EXTI_EMR3_EM87_Pos         (23U)
+#define EXTI_EMR3_EM87_Msk         (0x1UL << EXTI_EMR3_EM87_Pos)               /*!< 0x00800000 */
+#define EXTI_EMR3_EM87             EXTI_EMR3_EM87_Msk                          /*!< Event Mask on line 87 */
+
+/*******************  Bit definition for EXTI_PR3 register  ********************/
+#define EXTI_PR3_PR_Pos            (18U)
+#define EXTI_PR3_PR_Msk            (0x1DUL << EXTI_PR3_PR_Pos)                 /*!< 0x00740000 */
+#define EXTI_PR3_PR                EXTI_PR3_PR_Msk                             /*!< Pending bit */
+#define EXTI_PR3_PR82_Pos          (18U)
+#define EXTI_PR3_PR82_Msk          (0x1UL << EXTI_PR3_PR82_Pos)                /*!< 0x00040000 */
+#define EXTI_PR3_PR82              EXTI_PR3_PR82_Msk                           /*!< Pending bit for line 82 */
+#define EXTI_PR3_PR84_Pos          (20U)
+#define EXTI_PR3_PR84_Msk          (0x1UL << EXTI_PR3_PR84_Pos)                /*!< 0x00100000 */
+#define EXTI_PR3_PR84              EXTI_PR3_PR84_Msk                           /*!< Pending bit for line 84 */
+#define EXTI_PR3_PR85_Pos          (21U)
+#define EXTI_PR3_PR85_Msk          (0x1UL << EXTI_PR3_PR85_Pos)                /*!< 0x00200000 */
+#define EXTI_PR3_PR85              EXTI_PR3_PR85_Msk                           /*!< Pending bit for line 85 */
+#define EXTI_PR3_PR86_Pos          (22U)
+#define EXTI_PR3_PR86_Msk          (0x1UL << EXTI_PR3_PR86_Pos)                /*!< 0x00400000 */
+#define EXTI_PR3_PR86              EXTI_PR3_PR86_Msk                           /*!< Pending bit for line 86 */
+/******************************************************************************/
+/*                                                                            */
+/*                                    FLASH                                   */
+/*                                                                            */
+/******************************************************************************/
+/*
+* @brief FLASH Global Defines
+*/
+#define FLASH_SECTOR_TOTAL                   8U                    /* 8 sectors */
+#define FLASH_SIZE                           0x200000UL            /* 2 MB   */
+#define FLASH_BANK_SIZE                      (FLASH_SIZE >> 1)     /* 1 MB   */
+#define FLASH_SECTOR_SIZE                    0x00020000UL          /* 128 KB */
+#define FLASH_LATENCY_DEFAULT                FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */
+#define FLASH_NB_32BITWORD_IN_FLASHWORD      8U                    /* 256 bits */
+#define DUAL_BANK                                                  /* Dual-bank Flash */
+
+/*******************  Bits definition for FLASH_ACR register  **********************/
+#define FLASH_ACR_LATENCY_Pos                (0U)
+#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Read Latency */
+#define FLASH_ACR_LATENCY_0WS                (0x00000000UL)
+#define FLASH_ACR_LATENCY_1WS                (0x00000001UL)
+#define FLASH_ACR_LATENCY_2WS                (0x00000002UL)
+#define FLASH_ACR_LATENCY_3WS                (0x00000003UL)
+#define FLASH_ACR_LATENCY_4WS                (0x00000004UL)
+#define FLASH_ACR_LATENCY_5WS                (0x00000005UL)
+#define FLASH_ACR_LATENCY_6WS                (0x00000006UL)
+#define FLASH_ACR_LATENCY_7WS                (0x00000007UL)
+#define FLASH_ACR_LATENCY_8WS                (0x00000008UL)
+#define FLASH_ACR_LATENCY_9WS                (0x00000009UL)
+#define FLASH_ACR_LATENCY_10WS               (0x0000000AUL)
+#define FLASH_ACR_LATENCY_11WS               (0x0000000BUL)
+#define FLASH_ACR_LATENCY_12WS               (0x0000000CUL)
+#define FLASH_ACR_LATENCY_13WS               (0x0000000DUL)
+#define FLASH_ACR_LATENCY_14WS               (0x0000000EUL)
+#define FLASH_ACR_LATENCY_15WS               (0x0000000FUL)
+#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
+#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
+#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
+#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
+#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
+
+/*******************  Bits definition for FLASH_CR register  ***********************/
+#define FLASH_CR_LOCK_Pos                    (0U)
+#define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)      /*!< 0x00000001 */
+#define FLASH_CR_LOCK                        FLASH_CR_LOCK_Msk                 /*!< Configuration lock bit */
+#define FLASH_CR_PG_Pos                      (1U)
+#define FLASH_CR_PG_Msk                      (0x1UL << FLASH_CR_PG_Pos)        /*!< 0x00000002 */
+#define FLASH_CR_PG                          FLASH_CR_PG_Msk                   /*!< Internal buffer control bit */
+#define FLASH_CR_SER_Pos                     (2U)
+#define FLASH_CR_SER_Msk                     (0x1UL << FLASH_CR_SER_Pos)       /*!< 0x00000004 */
+#define FLASH_CR_SER                         FLASH_CR_SER_Msk                  /*!< Sector erase request */
+#define FLASH_CR_BER_Pos                     (3U)
+#define FLASH_CR_BER_Msk                     (0x1UL << FLASH_CR_BER_Pos)       /*!< 0x00000008 */
+#define FLASH_CR_BER                         FLASH_CR_BER_Msk                  /*!< Bank erase request */
+#define FLASH_CR_PSIZE_Pos                   (4U)
+#define FLASH_CR_PSIZE_Msk                   (0x3UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000030 */
+#define FLASH_CR_PSIZE                       FLASH_CR_PSIZE_Msk                /*!< Program size */
+#define FLASH_CR_PSIZE_0                     (0x1UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000010 */
+#define FLASH_CR_PSIZE_1                     (0x2UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000020 */
+#define FLASH_CR_FW_Pos                      (6U)
+#define FLASH_CR_FW_Msk                      (0x1UL << FLASH_CR_FW_Pos)        /*!< 0x00000040 */
+#define FLASH_CR_FW                          FLASH_CR_FW_Msk                   /*!< Write forcing control bit */
+#define FLASH_CR_START_Pos                   (7U)
+#define FLASH_CR_START_Msk                   (0x1UL << FLASH_CR_START_Pos)     /*!< 0x00000080 */
+#define FLASH_CR_START                       FLASH_CR_START_Msk                /*!< Erase start control bit */
+#define FLASH_CR_SNB_Pos                     (8U)
+#define FLASH_CR_SNB_Msk                     (0x7UL << FLASH_CR_SNB_Pos)       /*!< 0x00000700 */
+#define FLASH_CR_SNB                         FLASH_CR_SNB_Msk                  /*!< Sector erase selection number */
+#define FLASH_CR_SNB_0                       (0x1UL << FLASH_CR_SNB_Pos)       /*!< 0x00000100 */
+#define FLASH_CR_SNB_1                       (0x2UL << FLASH_CR_SNB_Pos)       /*!< 0x00000200 */
+#define FLASH_CR_SNB_2                       (0x4UL << FLASH_CR_SNB_Pos)       /*!< 0x00000400 */
+#define FLASH_CR_CRC_EN_Pos                  (15U)
+#define FLASH_CR_CRC_EN_Msk                  (0x1UL << FLASH_CR_CRC_EN_Pos)    /*!< 0x00008000 */
+#define FLASH_CR_CRC_EN                      FLASH_CR_CRC_EN_Msk               /*!< CRC control bit */
+#define FLASH_CR_EOPIE_Pos                   (16U)
+#define FLASH_CR_EOPIE_Msk                   (0x1UL << FLASH_CR_EOPIE_Pos)     /*!< 0x00010000 */
+#define FLASH_CR_EOPIE                       FLASH_CR_EOPIE_Msk                /*!< End-of-program interrupt control bit */
+#define FLASH_CR_WRPERRIE_Pos                (17U)
+#define FLASH_CR_WRPERRIE_Msk                (0x1UL << FLASH_CR_WRPERRIE_Pos)  /*!< 0x00020000 */
+#define FLASH_CR_WRPERRIE                    FLASH_CR_WRPERRIE_Msk             /*!< Write protection error interrupt enable bit */
+#define FLASH_CR_PGSERRIE_Pos                (18U)
+#define FLASH_CR_PGSERRIE_Msk                (0x1UL << FLASH_CR_PGSERRIE_Pos)  /*!< 0x00040000 */
+#define FLASH_CR_PGSERRIE                    FLASH_CR_PGSERRIE_Msk             /*!< Programming sequence error interrupt enable bit */
+#define FLASH_CR_STRBERRIE_Pos               (19U)
+#define FLASH_CR_STRBERRIE_Msk               (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */
+#define FLASH_CR_STRBERRIE                   FLASH_CR_STRBERRIE_Msk            /*!< Strobe error interrupt enable bit */
+#define FLASH_CR_INCERRIE_Pos                (21U)
+#define FLASH_CR_INCERRIE_Msk                (0x1UL << FLASH_CR_INCERRIE_Pos)  /*!< 0x00200000 */
+#define FLASH_CR_INCERRIE                    FLASH_CR_INCERRIE_Msk             /*!< Inconsistency error interrupt enable bit */
+#define FLASH_CR_OPERRIE_Pos                 (22U)
+#define FLASH_CR_OPERRIE_Msk                 (0x1UL << FLASH_CR_OPERRIE_Pos)   /*!< 0x00400000 */
+#define FLASH_CR_OPERRIE                     FLASH_CR_OPERRIE_Msk              /*!< Write/erase error interrupt enable bit */
+#define FLASH_CR_RDPERRIE_Pos                (23U)
+#define FLASH_CR_RDPERRIE_Msk                (0x1UL << FLASH_CR_RDPERRIE_Pos)  /*!< 0x00800000 */
+#define FLASH_CR_RDPERRIE                    FLASH_CR_RDPERRIE_Msk             /*!< Read protection error interrupt enable bit */
+#define FLASH_CR_RDSERRIE_Pos                (24U)
+#define FLASH_CR_RDSERRIE_Msk                (0x1UL << FLASH_CR_RDSERRIE_Pos)  /*!< 0x01000000 */
+#define FLASH_CR_RDSERRIE                    FLASH_CR_RDSERRIE_Msk             /*!< Secure error interrupt enable bit */
+#define FLASH_CR_SNECCERRIE_Pos              (25U)
+#define FLASH_CR_SNECCERRIE_Msk              (0x1UL << FLASH_CR_SNECCERRIE_Pos) /*!< 0x02000000 */
+#define FLASH_CR_SNECCERRIE                  FLASH_CR_SNECCERRIE_Msk            /*!< ECC single correction error interrupt enable bit */
+#define FLASH_CR_DBECCERRIE_Pos              (26U)
+#define FLASH_CR_DBECCERRIE_Msk              (0x1UL << FLASH_CR_DBECCERRIE_Pos) /*!< 0x04000000 */
+#define FLASH_CR_DBECCERRIE                  FLASH_CR_DBECCERRIE_Msk            /*!< ECC double detection error interrupt enable bit */
+#define FLASH_CR_CRCENDIE_Pos                (27U)
+#define FLASH_CR_CRCENDIE_Msk                (0x1UL << FLASH_CR_CRCENDIE_Pos)  /*!< 0x08000000 */
+#define FLASH_CR_CRCENDIE                    FLASH_CR_CRCENDIE_Msk             /*!< CRC end of calculation interrupt enable bit */
+#define FLASH_CR_CRCRDERRIE_Pos              (28U)
+#define FLASH_CR_CRCRDERRIE_Msk              (0x1UL << FLASH_CR_CRCRDERRIE_Pos) /*!< 0x10000000 */
+#define FLASH_CR_CRCRDERRIE                  FLASH_CR_CRCRDERRIE_Msk            /*!< CRC read error interrupt enable bit */
+
+/*******************  Bits definition for FLASH_SR register  ***********************/
+#define FLASH_SR_BSY_Pos                     (0U)
+#define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)       /*!< 0x00000001 */
+#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy flag */
+#define FLASH_SR_WBNE_Pos                    (1U)
+#define FLASH_SR_WBNE_Msk                    (0x1UL << FLASH_SR_WBNE_Pos)      /*!< 0x00000002 */
+#define FLASH_SR_WBNE                        FLASH_SR_WBNE_Msk                 /*!< Write buffer not empty flag */
+#define FLASH_SR_QW_Pos                      (2U)
+#define FLASH_SR_QW_Msk                      (0x1UL << FLASH_SR_QW_Pos)        /*!< 0x00000004 */
+#define FLASH_SR_QW                          FLASH_SR_QW_Msk                   /*!< Wait queue flag */
+#define FLASH_SR_CRC_BUSY_Pos                (3U)
+#define FLASH_SR_CRC_BUSY_Msk                (0x1UL << FLASH_SR_CRC_BUSY_Pos)  /*!< 0x00000008 */
+#define FLASH_SR_CRC_BUSY                    FLASH_SR_CRC_BUSY_Msk             /*!< CRC busy flag */
+#define FLASH_SR_EOP_Pos                     (16U)
+#define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)       /*!< 0x00010000 */
+#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End-of-program flag */
+#define FLASH_SR_WRPERR_Pos                  (17U)
+#define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)    /*!< 0x00020000 */
+#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protection error flag */
+#define FLASH_SR_PGSERR_Pos                  (18U)
+#define FLASH_SR_PGSERR_Msk                  (0x1UL << FLASH_SR_PGSERR_Pos)    /*!< 0x00040000 */
+#define FLASH_SR_PGSERR                      FLASH_SR_PGSERR_Msk               /*!< Programming sequence error flag */
+#define FLASH_SR_STRBERR_Pos                 (19U)
+#define FLASH_SR_STRBERR_Msk                 (0x1UL << FLASH_SR_STRBERR_Pos)   /*!< 0x00080000 */
+#define FLASH_SR_STRBERR                     FLASH_SR_STRBERR_Msk              /*!< Strobe error flag */
+#define FLASH_SR_INCERR_Pos                  (21U)
+#define FLASH_SR_INCERR_Msk                  (0x1UL << FLASH_SR_INCERR_Pos)    /*!< 0x00200000 */
+#define FLASH_SR_INCERR                      FLASH_SR_INCERR_Msk               /*!< Inconsistency error flag */
+#define FLASH_SR_OPERR_Pos                   (22U)
+#define FLASH_SR_OPERR_Msk                   (0x1UL << FLASH_SR_OPERR_Pos)     /*!< 0x00400000 */
+#define FLASH_SR_OPERR                       FLASH_SR_OPERR_Msk                /*!< Write/erase error flag */
+#define FLASH_SR_RDPERR_Pos                  (23U)
+#define FLASH_SR_RDPERR_Msk                  (0x1UL << FLASH_SR_RDPERR_Pos)    /*!< 0x00800000 */
+#define FLASH_SR_RDPERR                      FLASH_SR_RDPERR_Msk               /*!< Read protection error flag */
+#define FLASH_SR_RDSERR_Pos                  (24U)
+#define FLASH_SR_RDSERR_Msk                  (0x1UL << FLASH_SR_RDSERR_Pos)    /*!< 0x01000000 */
+#define FLASH_SR_RDSERR                      FLASH_SR_RDSERR_Msk               /*!< Secure error flag */
+#define FLASH_SR_SNECCERR_Pos                (25U)
+#define FLASH_SR_SNECCERR_Msk                (0x1UL << FLASH_SR_SNECCERR_Pos)  /*!< 0x02000000 */
+#define FLASH_SR_SNECCERR                    FLASH_SR_SNECCERR_Msk             /*!< Single correction error flag */
+#define FLASH_SR_DBECCERR_Pos                (26U)
+#define FLASH_SR_DBECCERR_Msk                (0x1UL << FLASH_SR_DBECCERR_Pos)  /*!< 0x04000000 */
+#define FLASH_SR_DBECCERR                    FLASH_SR_DBECCERR_Msk             /*!< ECC double detection error flag */
+#define FLASH_SR_CRCEND_Pos                  (27U)
+#define FLASH_SR_CRCEND_Msk                  (0x1UL << FLASH_SR_CRCEND_Pos)    /*!< 0x08000000 */
+#define FLASH_SR_CRCEND                      FLASH_SR_CRCEND_Msk               /*!< CRC end of calculation flag */
+#define FLASH_SR_CRCRDERR_Pos                (28U)
+#define FLASH_SR_CRCRDERR_Msk                (0x1UL << FLASH_SR_CRCRDERR_Pos)  /*!< 0x10000000 */
+#define FLASH_SR_CRCRDERR                    FLASH_SR_CRCRDERR_Msk             /*!< CRC read error flag */
+
+/*******************  Bits definition for FLASH_CCR register  *******************/
+#define FLASH_CCR_CLR_EOP_Pos                (16U)
+#define FLASH_CCR_CLR_EOP_Msk                (0x1UL << FLASH_CCR_CLR_EOP_Pos)  /*!< 0x00010000 */
+#define FLASH_CCR_CLR_EOP                    FLASH_CCR_CLR_EOP_Msk             /*!< EOP flag clear bit */
+#define FLASH_CCR_CLR_WRPERR_Pos             (17U)
+#define FLASH_CCR_CLR_WRPERR_Msk             (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */
+#define FLASH_CCR_CLR_WRPERR                 FLASH_CCR_CLR_WRPERR_Msk            /*!< WRPERR flag clear bit */
+#define FLASH_CCR_CLR_PGSERR_Pos             (18U)
+#define FLASH_CCR_CLR_PGSERR_Msk             (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */
+#define FLASH_CCR_CLR_PGSERR                 FLASH_CCR_CLR_PGSERR_Msk            /*!< PGSERR flag clear bit */
+#define FLASH_CCR_CLR_STRBERR_Pos            (19U)
+#define FLASH_CCR_CLR_STRBERR_Msk            (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */
+#define FLASH_CCR_CLR_STRBERR                FLASH_CCR_CLR_STRBERR_Msk            /*!< STRBERR flag clear bit */
+#define FLASH_CCR_CLR_INCERR_Pos             (21U)
+#define FLASH_CCR_CLR_INCERR_Msk             (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00200000 */
+#define FLASH_CCR_CLR_INCERR                 FLASH_CCR_CLR_INCERR_Msk            /*!< INCERR flag clear bit */
+#define FLASH_CCR_CLR_OPERR_Pos              (22U)
+#define FLASH_CCR_CLR_OPERR_Msk              (0x1UL << FLASH_CCR_CLR_OPERR_Pos) /*!< 0x00400000 */
+#define FLASH_CCR_CLR_OPERR                  FLASH_CCR_CLR_OPERR_Msk            /*!< OPERR flag clear bit */
+#define FLASH_CCR_CLR_RDPERR_Pos             (23U)
+#define FLASH_CCR_CLR_RDPERR_Msk             (0x1UL << FLASH_CCR_CLR_RDPERR_Pos) /*!< 0x00800000 */
+#define FLASH_CCR_CLR_RDPERR                 FLASH_CCR_CLR_RDPERR_Msk            /*!< RDPERR flag clear bit */
+#define FLASH_CCR_CLR_RDSERR_Pos             (24U)
+#define FLASH_CCR_CLR_RDSERR_Msk             (0x1UL << FLASH_CCR_CLR_RDSERR_Pos) /*!< 0x01000000 */
+#define FLASH_CCR_CLR_RDSERR                 FLASH_CCR_CLR_RDSERR_Msk            /*!< RDSERR flag clear bit */
+#define FLASH_CCR_CLR_SNECCERR_Pos           (25U)
+#define FLASH_CCR_CLR_SNECCERR_Msk           (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos) /*!< 0x02000000 */
+#define FLASH_CCR_CLR_SNECCERR               FLASH_CCR_CLR_SNECCERR_Msk            /*!< SNECCERR flag clear bit */
+#define FLASH_CCR_CLR_DBECCERR_Pos           (26U)
+#define FLASH_CCR_CLR_DBECCERR_Msk           (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos) /*!< 0x04000000 */
+#define FLASH_CCR_CLR_DBECCERR               FLASH_CCR_CLR_DBECCERR_Msk            /*!< DBECCERR flag clear bit */
+#define FLASH_CCR_CLR_CRCEND_Pos             (27U)
+#define FLASH_CCR_CLR_CRCEND_Msk             (0x1UL << FLASH_CCR_CLR_CRCEND_Pos) /*!< 0x08000000 */
+#define FLASH_CCR_CLR_CRCEND                 FLASH_CCR_CLR_CRCEND_Msk            /*!< CRCEND flag clear bit */
+#define FLASH_CCR_CLR_CRCRDERR_Pos           (28U)
+#define FLASH_CCR_CLR_CRCRDERR_Msk           (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos) /*!< 0x10000000 */
+#define FLASH_CCR_CLR_CRCRDERR               FLASH_CCR_CLR_CRCRDERR_Msk            /*!< CRCRDERR flag clear bit */
+
+/*******************  Bits definition for FLASH_OPTCR register  *******************/
+#define FLASH_OPTCR_OPTLOCK_Pos              (0U)
+#define FLASH_OPTCR_OPTLOCK_Msk              (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)  /*!< 0x00000001 */
+#define FLASH_OPTCR_OPTLOCK                  FLASH_OPTCR_OPTLOCK_Msk             /*!< FLASH_OPTCR lock option configuration bit */
+#define FLASH_OPTCR_OPTSTART_Pos             (1U)
+#define FLASH_OPTCR_OPTSTART_Msk             (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */
+#define FLASH_OPTCR_OPTSTART                 FLASH_OPTCR_OPTSTART_Msk            /*!< Option byte start change option configuration bit */
+#define FLASH_OPTCR_MER_Pos                  (4U)
+#define FLASH_OPTCR_MER_Msk                  (0x1UL << FLASH_OPTCR_MER_Pos)      /*!< 0x00000010 */
+#define FLASH_OPTCR_MER                      FLASH_OPTCR_MER_Msk                 /*!< Mass erase request */
+#define FLASH_OPTCR_OPTCHANGEERRIE_Pos       (30U)
+#define FLASH_OPTCR_OPTCHANGEERRIE_Msk       (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) /*!< 0x40000000 */
+#define FLASH_OPTCR_OPTCHANGEERRIE           FLASH_OPTCR_OPTCHANGEERRIE_Msk            /*!< Option byte change error interrupt enable bit */
+#define FLASH_OPTCR_SWAP_BANK_Pos            (31U)
+#define FLASH_OPTCR_SWAP_BANK_Msk            (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */
+#define FLASH_OPTCR_SWAP_BANK                FLASH_OPTCR_SWAP_BANK_Msk            /*!< Bank swapping option configuration bit */
+
+/*******************  Bits definition for FLASH_OPTSR register  ***************/
+#define FLASH_OPTSR_OPT_BUSY_Pos             (0U)
+#define FLASH_OPTSR_OPT_BUSY_Msk             (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos) /*!< 0x00000001 */
+#define FLASH_OPTSR_OPT_BUSY                 FLASH_OPTSR_OPT_BUSY_Msk            /*!< Option byte change ongoing flag */
+#define FLASH_OPTSR_BOR_LEV_Pos              (2U)
+#define FLASH_OPTSR_BOR_LEV_Msk              (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x0000000C */
+#define FLASH_OPTSR_BOR_LEV                  FLASH_OPTSR_BOR_LEV_Msk            /*!< Brownout level option status bit */
+#define FLASH_OPTSR_BOR_LEV_0                (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000004 */
+#define FLASH_OPTSR_BOR_LEV_1                (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000008 */
+#define FLASH_OPTSR_IWDG1_SW_Pos             (4U)
+#define FLASH_OPTSR_IWDG1_SW_Msk             (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos) /*!< 0x00000010 */
+#define FLASH_OPTSR_IWDG1_SW                 FLASH_OPTSR_IWDG1_SW_Msk            /*!< IWDG1 control mode option status bit */
+#define FLASH_OPTSR_NRST_STOP_D1_Pos         (6U)
+#define FLASH_OPTSR_NRST_STOP_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos) /*!< 0x00000040 */
+#define FLASH_OPTSR_NRST_STOP_D1             FLASH_OPTSR_NRST_STOP_D1_Msk            /*!< D1 domain DStop entry reset option status bit */
+#define FLASH_OPTSR_NRST_STBY_D1_Pos         (7U)
+#define FLASH_OPTSR_NRST_STBY_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos) /*!< 0x00000080 */
+#define FLASH_OPTSR_NRST_STBY_D1             FLASH_OPTSR_NRST_STBY_D1_Msk            /*!< D1 domain DStandby entry reset option status bit */
+#define FLASH_OPTSR_RDP_Pos                  (8U)
+#define FLASH_OPTSR_RDP_Msk                  (0xFFUL << FLASH_OPTSR_RDP_Pos)   /*!< 0x0000FF00 */
+#define FLASH_OPTSR_RDP                      FLASH_OPTSR_RDP_Msk               /*!< Readout protection level option status byte */
+#define FLASH_OPTSR_FZ_IWDG_STOP_Pos         (17U)
+#define FLASH_OPTSR_FZ_IWDG_STOP_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos) /*!< 0x00020000 */
+#define FLASH_OPTSR_FZ_IWDG_STOP             FLASH_OPTSR_FZ_IWDG_STOP_Msk            /*!< IWDG Stop mode freeze option status bit */
+#define FLASH_OPTSR_FZ_IWDG_SDBY_Pos         (18U)
+#define FLASH_OPTSR_FZ_IWDG_SDBY_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos) /*!< 0x00040000 */
+#define FLASH_OPTSR_FZ_IWDG_SDBY             FLASH_OPTSR_FZ_IWDG_SDBY_Msk            /*!< IWDG Standby mode freeze option status bit */
+#define FLASH_OPTSR_ST_RAM_SIZE_Pos          (19U)
+#define FLASH_OPTSR_ST_RAM_SIZE_Msk          (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00180000 */
+#define FLASH_OPTSR_ST_RAM_SIZE              FLASH_OPTSR_ST_RAM_SIZE_Msk            /*!< ST RAM size option status */
+#define FLASH_OPTSR_ST_RAM_SIZE_0            (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00080000 */
+#define FLASH_OPTSR_ST_RAM_SIZE_1            (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00100000 */
+#define FLASH_OPTSR_SECURITY_Pos             (21U)
+#define FLASH_OPTSR_SECURITY_Msk             (0x1UL << FLASH_OPTSR_SECURITY_Pos) /*!< 0x00200000 */
+#define FLASH_OPTSR_SECURITY                 FLASH_OPTSR_SECURITY_Msk            /*!< Security enable option status bit */
+#define FLASH_OPTSR_IO_HSLV_Pos              (29U)
+#define FLASH_OPTSR_IO_HSLV_Msk              (0x1UL << FLASH_OPTSR_IO_HSLV_Pos) /*!< 0x20000000 */
+#define FLASH_OPTSR_IO_HSLV                  FLASH_OPTSR_IO_HSLV_Msk            /*!< I/O high-speed at low-voltage status bit */
+#define FLASH_OPTSR_OPTCHANGEERR_Pos         (30U)
+#define FLASH_OPTSR_OPTCHANGEERR_Msk         (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) /*!< 0x40000000 */
+#define FLASH_OPTSR_OPTCHANGEERR             FLASH_OPTSR_OPTCHANGEERR_Msk            /*!< Option byte change error flag */
+#define FLASH_OPTSR_SWAP_BANK_OPT_Pos        (31U)
+#define FLASH_OPTSR_SWAP_BANK_OPT_Msk        (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos) /*!< 0x80000000 */
+#define FLASH_OPTSR_SWAP_BANK_OPT            FLASH_OPTSR_SWAP_BANK_OPT_Msk            /*!< Bank swapping option status bit */
+
+/*******************  Bits definition for FLASH_OPTCCR register  *******************/
+#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos    (30U)
+#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk    (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos) /*!< 0x40000000 */
+#define FLASH_OPTCCR_CLR_OPTCHANGEERR        FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk            /*!< OPTCHANGEERR reset bit */
+
+/*******************  Bits definition for FLASH_PRAR register  *********************/
+#define FLASH_PRAR_PROT_AREA_START_Pos       (0U)
+#define FLASH_PRAR_PROT_AREA_START_Msk       (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos) /*!< 0x00000FFF */
+#define FLASH_PRAR_PROT_AREA_START           FLASH_PRAR_PROT_AREA_START_Msk              /*!< PCROP area start status bits */
+#define FLASH_PRAR_PROT_AREA_END_Pos         (16U)
+#define FLASH_PRAR_PROT_AREA_END_Msk         (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos) /*!< 0x0FFF0000 */
+#define FLASH_PRAR_PROT_AREA_END             FLASH_PRAR_PROT_AREA_END_Msk              /*!< PCROP area end status bits */
+#define FLASH_PRAR_DMEP_Pos                  (31U)
+#define FLASH_PRAR_DMEP_Msk                  (0x1UL << FLASH_PRAR_DMEP_Pos)    /*!< 0x80000000 */
+#define FLASH_PRAR_DMEP                      FLASH_PRAR_DMEP_Msk               /*!< PCROP protected erase enable option status bit */
+
+/*******************  Bits definition for FLASH_SCAR register  *********************/
+#define FLASH_SCAR_SEC_AREA_START_Pos        (0U)
+#define FLASH_SCAR_SEC_AREA_START_Msk        (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos) /*!< 0x00000FFF */
+#define FLASH_SCAR_SEC_AREA_START            FLASH_SCAR_SEC_AREA_START_Msk              /*!< Secure-only area start status bits */
+#define FLASH_SCAR_SEC_AREA_END_Pos          (16U)
+#define FLASH_SCAR_SEC_AREA_END_Msk          (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos) /*!< 0x0FFF0000 */
+#define FLASH_SCAR_SEC_AREA_END              FLASH_SCAR_SEC_AREA_END_Msk              /*!< Secure-only area end status bits */
+#define FLASH_SCAR_DMES_Pos                  (31U)
+#define FLASH_SCAR_DMES_Msk                  (0x1UL << FLASH_SCAR_DMES_Pos)    /*!< 0x80000000 */
+#define FLASH_SCAR_DMES                      FLASH_SCAR_DMES_Msk               /*!< Secure access protected erase enable option status bit */
+
+/*******************  Bits definition for FLASH_WPSN register  *********************/
+#define FLASH_WPSN_WRPSN_Pos                 (0U)
+#define FLASH_WPSN_WRPSN_Msk                 (0xFFUL << FLASH_WPSN_WRPSN_Pos)  /*!< 0x000000FF */
+#define FLASH_WPSN_WRPSN                     FLASH_WPSN_WRPSN_Msk              /*!< Sector write protection option status byte */
+
+/*******************  Bits definition for FLASH_BOOT_CUR register  ****************/
+#define FLASH_BOOT_ADD0_Pos                  (0U)
+#define FLASH_BOOT_ADD0_Msk                  (0xFFFFUL << FLASH_BOOT_ADD0_Pos) /*!< 0x0000FFFF */
+#define FLASH_BOOT_ADD0                      FLASH_BOOT_ADD0_Msk               /*!< Arm Cortex-M7 boot address 0 */
+#define FLASH_BOOT_ADD1_Pos                  (16U)
+#define FLASH_BOOT_ADD1_Msk                  (0xFFFFUL << FLASH_BOOT_ADD1_Pos) /*!< 0xFFFF0000 */
+#define FLASH_BOOT_ADD1                      FLASH_BOOT_ADD1_Msk               /*!< Arm Cortex-M7 boot address 1 */
+
+
+/*******************  Bits definition for FLASH_CRCCR register  ********************/
+#define FLASH_CRCCR_CRC_SECT_Pos             (0U)
+#define FLASH_CRCCR_CRC_SECT_Msk             (0x7UL << FLASH_CRCCR_CRC_SECT_Pos) /*!< 0x00000007 */
+#define FLASH_CRCCR_CRC_SECT                 FLASH_CRCCR_CRC_SECT_Msk            /*!< CRC sector number */
+#define FLASH_CRCCR_CRC_BY_SECT_Pos          (8U)
+#define FLASH_CRCCR_CRC_BY_SECT_Msk          (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos) /*!< 0x00000100 */
+#define FLASH_CRCCR_CRC_BY_SECT              FLASH_CRCCR_CRC_BY_SECT_Msk            /*!< CRC sector mode select bit */
+#define FLASH_CRCCR_ADD_SECT_Pos             (9U)
+#define FLASH_CRCCR_ADD_SECT_Msk             (0x1UL << FLASH_CRCCR_ADD_SECT_Pos) /*!< 0x00000200 */
+#define FLASH_CRCCR_ADD_SECT                 FLASH_CRCCR_ADD_SECT_Msk            /*!< CRC sector select bit */
+#define FLASH_CRCCR_CLEAN_SECT_Pos           (10U)
+#define FLASH_CRCCR_CLEAN_SECT_Msk           (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos) /*!< 0x00000400 */
+#define FLASH_CRCCR_CLEAN_SECT               FLASH_CRCCR_CLEAN_SECT_Msk            /*!< CRC sector list clear bit */
+#define FLASH_CRCCR_START_CRC_Pos            (16U)
+#define FLASH_CRCCR_START_CRC_Msk            (0x1UL << FLASH_CRCCR_START_CRC_Pos) /*!< 0x00010000 */
+#define FLASH_CRCCR_START_CRC                FLASH_CRCCR_START_CRC_Msk            /*!< CRC start bit */
+#define FLASH_CRCCR_CLEAN_CRC_Pos            (17U)
+#define FLASH_CRCCR_CLEAN_CRC_Msk            (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos) /*!< 0x00020000 */
+#define FLASH_CRCCR_CLEAN_CRC                FLASH_CRCCR_CLEAN_CRC_Msk            /*!< CRC clear bit */
+#define FLASH_CRCCR_CRC_BURST_Pos            (20U)
+#define FLASH_CRCCR_CRC_BURST_Msk            (0x3UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00300000 */
+#define FLASH_CRCCR_CRC_BURST                FLASH_CRCCR_CRC_BURST_Msk            /*!< CRC burst size */
+#define FLASH_CRCCR_CRC_BURST_0              (0x1UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00100000 */
+#define FLASH_CRCCR_CRC_BURST_1              (0x2UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00200000 */
+#define FLASH_CRCCR_ALL_BANK_Pos             (22U)
+#define FLASH_CRCCR_ALL_BANK_Msk             (0x1UL << FLASH_CRCCR_ALL_BANK_Pos) /*!< 0x00400000 */
+#define FLASH_CRCCR_ALL_BANK                 FLASH_CRCCR_ALL_BANK_Msk            /*!< CRC select bit */
+
+/*******************  Bits definition for FLASH_CRCSADD register  ****************/
+#define FLASH_CRCSADD_CRC_START_ADDR_Pos     (0U)
+#define FLASH_CRCSADD_CRC_START_ADDR_Msk     (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_CRCSADD_CRC_START_ADDR         FLASH_CRCSADD_CRC_START_ADDR_Msk                   /*!< CRC start address */
+
+/*******************  Bits definition for FLASH_CRCEADD register  ****************/
+#define FLASH_CRCEADD_CRC_END_ADDR_Pos       (0U)
+#define FLASH_CRCEADD_CRC_END_ADDR_Msk       (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_CRCEADD_CRC_END_ADDR           FLASH_CRCEADD_CRC_END_ADDR_Msk                   /*!< CRC end address */
+
+/*******************  Bits definition for FLASH_CRCDATA register  ***************/
+#define FLASH_CRCDATA_CRC_DATA_Pos           (0U)
+#define FLASH_CRCDATA_CRC_DATA_Msk           (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_CRCDATA_CRC_DATA               FLASH_CRCDATA_CRC_DATA_Msk                   /*!< CRC result */
+
+/*******************  Bits definition for FLASH_ECC_FA register  *******************/
+#define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos       (0U)
+#define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk       (0x7FFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos) /*!< 0x00007FFF */
+#define FLASH_ECC_FA_FAIL_ECC_ADDR           FLASH_ECC_FA_FAIL_ECC_ADDR_Msk               /*!< ECC error address */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Flexible Memory Controller                        */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for FMC_BCR1 register  *******************/
+#define FMC_BCR1_CCLKEN_Pos        (20U)
+#define FMC_BCR1_CCLKEN_Msk        (0x1UL << FMC_BCR1_CCLKEN_Pos)              /*!< 0x00100000 */
+#define FMC_BCR1_CCLKEN            FMC_BCR1_CCLKEN_Msk                         /*!<Continous clock enable     */
+#define FMC_BCR1_WFDIS_Pos         (21U)
+#define FMC_BCR1_WFDIS_Msk         (0x1UL << FMC_BCR1_WFDIS_Pos)               /*!< 0x00200000 */
+#define FMC_BCR1_WFDIS             FMC_BCR1_WFDIS_Msk                          /*!<Write FIFO Disable         */
+
+#define FMC_BCR1_BMAP_Pos          (24U)
+#define FMC_BCR1_BMAP_Msk          (0x3UL << FMC_BCR1_BMAP_Pos)                /*!< 0x03000000 */
+#define FMC_BCR1_BMAP              FMC_BCR1_BMAP_Msk                           /*!<BMAP[1:0] FMC bank mapping */
+#define FMC_BCR1_BMAP_0            (0x1UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x01000000 */
+#define FMC_BCR1_BMAP_1            (0x2UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x02000000 */
+
+#define FMC_BCR1_FMCEN_Pos         (31U)
+#define FMC_BCR1_FMCEN_Msk         (0x1UL << FMC_BCR1_FMCEN_Pos)               /*!< 0x80000000 */
+#define FMC_BCR1_FMCEN             FMC_BCR1_FMCEN_Msk                          /*!<FMC controller Enable */
+/******************  Bit definition for FMC_BCRx registers (x=1..4)  *********/
+#define FMC_BCRx_MBKEN_Pos         (0U)
+#define FMC_BCRx_MBKEN_Msk         (0x1UL << FMC_BCRx_MBKEN_Pos)               /*!< 0x00000001 */
+#define FMC_BCRx_MBKEN             FMC_BCRx_MBKEN_Msk                          /*!<Memory bank enable bit                 */
+#define FMC_BCRx_MUXEN_Pos         (1U)
+#define FMC_BCRx_MUXEN_Msk         (0x1UL << FMC_BCRx_MUXEN_Pos)               /*!< 0x00000002 */
+#define FMC_BCRx_MUXEN             FMC_BCRx_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */
+
+#define FMC_BCRx_MTYP_Pos          (2U)
+#define FMC_BCRx_MTYP_Msk          (0x3UL << FMC_BCRx_MTYP_Pos)                /*!< 0x0000000C */
+#define FMC_BCRx_MTYP              FMC_BCRx_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */
+#define FMC_BCRx_MTYP_0            (0x1UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000004 */
+#define FMC_BCRx_MTYP_1            (0x2UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000008 */
+
+#define FMC_BCRx_MWID_Pos          (4U)
+#define FMC_BCRx_MWID_Msk          (0x3UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000030 */
+#define FMC_BCRx_MWID              FMC_BCRx_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCRx_MWID_0            (0x1UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000010 */
+#define FMC_BCRx_MWID_1            (0x2UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000020 */
+
+#define FMC_BCRx_FACCEN_Pos        (6U)
+#define FMC_BCRx_FACCEN_Msk        (0x1UL << FMC_BCRx_FACCEN_Pos)              /*!< 0x00000040 */
+#define FMC_BCRx_FACCEN            FMC_BCRx_FACCEN_Msk                         /*!<Flash access enable        */
+#define FMC_BCRx_BURSTEN_Pos       (8U)
+#define FMC_BCRx_BURSTEN_Msk       (0x1UL << FMC_BCRx_BURSTEN_Pos)             /*!< 0x00000100 */
+#define FMC_BCRx_BURSTEN           FMC_BCRx_BURSTEN_Msk                        /*!<Burst enable bit           */
+#define FMC_BCRx_WAITPOL_Pos       (9U)
+#define FMC_BCRx_WAITPOL_Msk       (0x1UL << FMC_BCRx_WAITPOL_Pos)             /*!< 0x00000200 */
+#define FMC_BCRx_WAITPOL           FMC_BCRx_WAITPOL_Msk                        /*!<Wait signal polarity bit   */
+#define FMC_BCRx_WAITCFG_Pos       (11U)
+#define FMC_BCRx_WAITCFG_Msk       (0x1UL << FMC_BCRx_WAITCFG_Pos)             /*!< 0x00000800 */
+#define FMC_BCRx_WAITCFG           FMC_BCRx_WAITCFG_Msk                        /*!<Wait timing configuration  */
+#define FMC_BCRx_WREN_Pos          (12U)
+#define FMC_BCRx_WREN_Msk          (0x1UL << FMC_BCRx_WREN_Pos)                /*!< 0x00001000 */
+#define FMC_BCRx_WREN              FMC_BCRx_WREN_Msk                           /*!<Write enable bit           */
+#define FMC_BCRx_WAITEN_Pos        (13U)
+#define FMC_BCRx_WAITEN_Msk        (0x1UL << FMC_BCRx_WAITEN_Pos)              /*!< 0x00002000 */
+#define FMC_BCRx_WAITEN            FMC_BCRx_WAITEN_Msk                         /*!<Wait enable bit            */
+#define FMC_BCRx_EXTMOD_Pos        (14U)
+#define FMC_BCRx_EXTMOD_Msk        (0x1UL << FMC_BCRx_EXTMOD_Pos)              /*!< 0x00004000 */
+#define FMC_BCRx_EXTMOD            FMC_BCRx_EXTMOD_Msk                         /*!<Extended mode enable       */
+#define FMC_BCRx_ASYNCWAIT_Pos     (15U)
+#define FMC_BCRx_ASYNCWAIT_Msk     (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)           /*!< 0x00008000 */
+#define FMC_BCRx_ASYNCWAIT         FMC_BCRx_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */
+
+#define FMC_BCRx_CPSIZE_Pos        (16U)
+#define FMC_BCRx_CPSIZE_Msk        (0x7UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00070000 */
+#define FMC_BCRx_CPSIZE            FMC_BCRx_CPSIZE_Msk                         /*!<PSIZE[2:0] bits CRAM Page Size */
+#define FMC_BCRx_CPSIZE_0          (0x1UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00010000 */
+#define FMC_BCRx_CPSIZE_1          (0x2UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00020000 */
+#define FMC_BCRx_CPSIZE_2          (0x4UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00040000 */
+
+#define FMC_BCRx_CBURSTRW_Pos      (19U)
+#define FMC_BCRx_CBURSTRW_Msk      (0x1UL << FMC_BCRx_CBURSTRW_Pos)            /*!< 0x00080000 */
+#define FMC_BCRx_CBURSTRW          FMC_BCRx_CBURSTRW_Msk                       /*!<Write burst enable         */
+
+/******************  Bit definition for FMC_BTRx registers (x=1..4)  *********/
+#define FMC_BTRx_ADDSET_Pos        (0U)
+#define FMC_BTRx_ADDSET_Msk        (0xFUL << FMC_BTRx_ADDSET_Pos)              /*!< 0x0000000F */
+#define FMC_BTRx_ADDSET            FMC_BTRx_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTRx_ADDSET_0          (0x1UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000001 */
+#define FMC_BTRx_ADDSET_1          (0x2UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000002 */
+#define FMC_BTRx_ADDSET_2          (0x4UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000004 */
+#define FMC_BTRx_ADDSET_3          (0x8UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000008 */
+
+#define FMC_BTRx_ADDHLD_Pos        (4U)
+#define FMC_BTRx_ADDHLD_Msk        (0xFUL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x000000F0 */
+#define FMC_BTRx_ADDHLD            FMC_BTRx_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
+#define FMC_BTRx_ADDHLD_0          (0x1UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000010 */
+#define FMC_BTRx_ADDHLD_1          (0x2UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000020 */
+#define FMC_BTRx_ADDHLD_2          (0x4UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000040 */
+#define FMC_BTRx_ADDHLD_3          (0x8UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000080 */
+
+#define FMC_BTRx_DATAST_Pos        (8U)
+#define FMC_BTRx_DATAST_Msk        (0xFFUL << FMC_BTRx_DATAST_Pos)             /*!< 0x0000FF00 */
+#define FMC_BTRx_DATAST            FMC_BTRx_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTRx_DATAST_0          (0x01UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000100 */
+#define FMC_BTRx_DATAST_1          (0x02UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000200 */
+#define FMC_BTRx_DATAST_2          (0x04UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000400 */
+#define FMC_BTRx_DATAST_3          (0x08UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000800 */
+#define FMC_BTRx_DATAST_4          (0x10UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00001000 */
+#define FMC_BTRx_DATAST_5          (0x20UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00002000 */
+#define FMC_BTRx_DATAST_6          (0x40UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00004000 */
+#define FMC_BTRx_DATAST_7          (0x80UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00008000 */
+
+#define FMC_BTRx_BUSTURN_Pos       (16U)
+#define FMC_BTRx_BUSTURN_Msk       (0xFUL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x000F0000 */
+#define FMC_BTRx_BUSTURN           FMC_BTRx_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTRx_BUSTURN_0         (0x1UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00010000 */
+#define FMC_BTRx_BUSTURN_1         (0x2UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00020000 */
+#define FMC_BTRx_BUSTURN_2         (0x4UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00040000 */
+#define FMC_BTRx_BUSTURN_3         (0x8UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00080000 */
+
+#define FMC_BTRx_CLKDIV_Pos        (20U)
+#define FMC_BTRx_CLKDIV_Msk        (0xFUL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00F00000 */
+#define FMC_BTRx_CLKDIV            FMC_BTRx_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTRx_CLKDIV_0          (0x1UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00100000 */
+#define FMC_BTRx_CLKDIV_1          (0x2UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00200000 */
+#define FMC_BTRx_CLKDIV_2          (0x4UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00400000 */
+#define FMC_BTRx_CLKDIV_3          (0x8UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00800000 */
+
+#define FMC_BTRx_DATLAT_Pos        (24U)
+#define FMC_BTRx_DATLAT_Msk        (0xFUL << FMC_BTRx_DATLAT_Pos)              /*!< 0x0F000000 */
+#define FMC_BTRx_DATLAT            FMC_BTRx_DATLAT_Msk                         /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTRx_DATLAT_0          (0x1UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x01000000 */
+#define FMC_BTRx_DATLAT_1          (0x2UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x02000000 */
+#define FMC_BTRx_DATLAT_2          (0x4UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x04000000 */
+#define FMC_BTRx_DATLAT_3          (0x8UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x08000000 */
+
+#define FMC_BTRx_ACCMOD_Pos        (28U)
+#define FMC_BTRx_ACCMOD_Msk        (0x3UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x30000000 */
+#define FMC_BTRx_ACCMOD            FMC_BTRx_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTRx_ACCMOD_0          (0x1UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x10000000 */
+#define FMC_BTRx_ACCMOD_1          (0x2UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x20000000 */
+
+/******************  Bit definition for FMC_BWTRx registers (x=1..4)  *********/
+#define FMC_BWTRx_ADDSET_Pos       (0U)
+#define FMC_BWTRx_ADDSET_Msk       (0xFUL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x0000000F */
+#define FMC_BWTRx_ADDSET           FMC_BWTRx_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTRx_ADDSET_0         (0x1UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000001 */
+#define FMC_BWTRx_ADDSET_1         (0x2UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000002 */
+#define FMC_BWTRx_ADDSET_2         (0x4UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000004 */
+#define FMC_BWTRx_ADDSET_3         (0x8UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000008 */
+
+#define FMC_BWTRx_ADDHLD_Pos       (4U)
+#define FMC_BWTRx_ADDHLD_Msk       (0xFUL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x000000F0 */
+#define FMC_BWTRx_ADDHLD           FMC_BWTRx_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTRx_ADDHLD_0         (0x1UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000010 */
+#define FMC_BWTRx_ADDHLD_1         (0x2UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000020 */
+#define FMC_BWTRx_ADDHLD_2         (0x4UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000040 */
+#define FMC_BWTRx_ADDHLD_3         (0x8UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000080 */
+
+#define FMC_BWTRx_DATAST_Pos       (8U)
+#define FMC_BWTRx_DATAST_Msk       (0xFFUL << FMC_BWTRx_DATAST_Pos)            /*!< 0x0000FF00 */
+#define FMC_BWTRx_DATAST           FMC_BWTRx_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTRx_DATAST_0         (0x01UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000100 */
+#define FMC_BWTRx_DATAST_1         (0x02UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000200 */
+#define FMC_BWTRx_DATAST_2         (0x04UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000400 */
+#define FMC_BWTRx_DATAST_3         (0x08UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000800 */
+#define FMC_BWTRx_DATAST_4         (0x10UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00001000 */
+#define FMC_BWTRx_DATAST_5         (0x20UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00002000 */
+#define FMC_BWTRx_DATAST_6         (0x40UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00004000 */
+#define FMC_BWTRx_DATAST_7         (0x80UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00008000 */
+
+#define FMC_BWTRx_BUSTURN_Pos      (16U)
+#define FMC_BWTRx_BUSTURN_Msk      (0xFUL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x000F0000 */
+#define FMC_BWTRx_BUSTURN          FMC_BWTRx_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BWTRx_BUSTURN_0        (0x1UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00010000 */
+#define FMC_BWTRx_BUSTURN_1        (0x2UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00020000 */
+#define FMC_BWTRx_BUSTURN_2        (0x4UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00040000 */
+#define FMC_BWTRx_BUSTURN_3        (0x8UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00080000 */
+
+#define FMC_BWTRx_ACCMOD_Pos       (28U)
+#define FMC_BWTRx_ACCMOD_Msk       (0x3UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x30000000 */
+#define FMC_BWTRx_ACCMOD           FMC_BWTRx_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTRx_ACCMOD_0         (0x1UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x10000000 */
+#define FMC_BWTRx_ACCMOD_1         (0x2UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x20000000 */
+
+/******************  Bit definition for FMC_PCR register  *******************/
+#define FMC_PCR_PWAITEN_Pos        (1U)
+#define FMC_PCR_PWAITEN_Msk        (0x1UL << FMC_PCR_PWAITEN_Pos)              /*!< 0x00000002 */
+#define FMC_PCR_PWAITEN            FMC_PCR_PWAITEN_Msk                         /*!<Wait feature enable bit                   */
+#define FMC_PCR_PBKEN_Pos          (2U)
+#define FMC_PCR_PBKEN_Msk          (0x1UL << FMC_PCR_PBKEN_Pos)                /*!< 0x00000004 */
+#define FMC_PCR_PBKEN              FMC_PCR_PBKEN_Msk                           /*!<NAND Flash memory bank enable bit */
+
+#define FMC_PCR_PWID_Pos           (4U)
+#define FMC_PCR_PWID_Msk           (0x3UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000030 */
+#define FMC_PCR_PWID               FMC_PCR_PWID_Msk                            /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR_PWID_0             (0x1UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000010 */
+#define FMC_PCR_PWID_1             (0x2UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000020 */
+
+#define FMC_PCR_ECCEN_Pos          (6U)
+#define FMC_PCR_ECCEN_Msk          (0x1UL << FMC_PCR_ECCEN_Pos)                /*!< 0x00000040 */
+#define FMC_PCR_ECCEN              FMC_PCR_ECCEN_Msk                           /*!<ECC computation logic enable bit          */
+
+#define FMC_PCR_TCLR_Pos           (9U)
+#define FMC_PCR_TCLR_Msk           (0xFUL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001E00 */
+#define FMC_PCR_TCLR               FMC_PCR_TCLR_Msk                            /*!<TCLR[3:0] bits (CLE to RE delay)          */
+#define FMC_PCR_TCLR_0             (0x1UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000200 */
+#define FMC_PCR_TCLR_1             (0x2UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000400 */
+#define FMC_PCR_TCLR_2             (0x4UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000800 */
+#define FMC_PCR_TCLR_3             (0x8UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00001000 */
+
+#define FMC_PCR_TAR_Pos            (13U)
+#define FMC_PCR_TAR_Msk            (0xFUL << FMC_PCR_TAR_Pos)                  /*!< 0x0001E000 */
+#define FMC_PCR_TAR                FMC_PCR_TAR_Msk                             /*!<TAR[3:0] bits (ALE to RE delay)           */
+#define FMC_PCR_TAR_0              (0x1UL << FMC_PCR_TAR_Pos)                   /*!< 0x00002000 */
+#define FMC_PCR_TAR_1              (0x2UL << FMC_PCR_TAR_Pos)                   /*!< 0x00004000 */
+#define FMC_PCR_TAR_2              (0x4UL << FMC_PCR_TAR_Pos)                   /*!< 0x00008000 */
+#define FMC_PCR_TAR_3              (0x8UL << FMC_PCR_TAR_Pos)                   /*!< 0x00010000 */
+
+#define FMC_PCR_ECCPS_Pos          (17U)
+#define FMC_PCR_ECCPS_Msk          (0x7UL << FMC_PCR_ECCPS_Pos)                /*!< 0x000E0000 */
+#define FMC_PCR_ECCPS              FMC_PCR_ECCPS_Msk                           /*!<ECCPS[1:0] bits (ECC page size)           */
+#define FMC_PCR_ECCPS_0            (0x1UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00020000 */
+#define FMC_PCR_ECCPS_1            (0x2UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00040000 */
+#define FMC_PCR_ECCPS_2            (0x4UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00080000 */
+
+/*******************  Bit definition for FMC_SR register  *******************/
+#define FMC_SR_IRS_Pos             (0U)
+#define FMC_SR_IRS_Msk             (0x1UL << FMC_SR_IRS_Pos)                   /*!< 0x00000001 */
+#define FMC_SR_IRS                 FMC_SR_IRS_Msk                              /*!<Interrupt Rising Edge status                */
+#define FMC_SR_ILS_Pos             (1U)
+#define FMC_SR_ILS_Msk             (0x1UL << FMC_SR_ILS_Pos)                   /*!< 0x00000002 */
+#define FMC_SR_ILS                 FMC_SR_ILS_Msk                              /*!<Interrupt Level status                      */
+#define FMC_SR_IFS_Pos             (2U)
+#define FMC_SR_IFS_Msk             (0x1UL << FMC_SR_IFS_Pos)                   /*!< 0x00000004 */
+#define FMC_SR_IFS                 FMC_SR_IFS_Msk                              /*!<Interrupt Falling Edge status               */
+#define FMC_SR_IREN_Pos            (3U)
+#define FMC_SR_IREN_Msk            (0x1UL << FMC_SR_IREN_Pos)                  /*!< 0x00000008 */
+#define FMC_SR_IREN                FMC_SR_IREN_Msk                             /*!<Interrupt Rising Edge detection Enable bit  */
+#define FMC_SR_ILEN_Pos            (4U)
+#define FMC_SR_ILEN_Msk            (0x1UL << FMC_SR_ILEN_Pos)                  /*!< 0x00000010 */
+#define FMC_SR_ILEN                FMC_SR_ILEN_Msk                             /*!<Interrupt Level detection Enable bit        */
+#define FMC_SR_IFEN_Pos            (5U)
+#define FMC_SR_IFEN_Msk            (0x1UL << FMC_SR_IFEN_Pos)                  /*!< 0x00000020 */
+#define FMC_SR_IFEN                FMC_SR_IFEN_Msk                             /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR_FEMPT_Pos           (6U)
+#define FMC_SR_FEMPT_Msk           (0x1UL << FMC_SR_FEMPT_Pos)                 /*!< 0x00000040 */
+#define FMC_SR_FEMPT               FMC_SR_FEMPT_Msk                            /*!<FIFO empty                                  */
+
+/******************  Bit definition for FMC_PMEM register  ******************/
+#define FMC_PMEM_MEMSET_Pos       (0U)
+#define FMC_PMEM_MEMSET_Msk       (0xFFUL << FMC_PMEM_MEMSET_Pos)            /*!< 0x000000FF */
+#define FMC_PMEM_MEMSET           FMC_PMEM_MEMSET_Msk                        /*!<MEMSET[7:0] bits (Common memory setup time) */
+#define FMC_PMEM_MEMSET_0         (0x01UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000001 */
+#define FMC_PMEM_MEMSET_1         (0x02UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000002 */
+#define FMC_PMEM_MEMSET_2         (0x04UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000004 */
+#define FMC_PMEM_MEMSET_3         (0x08UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000008 */
+#define FMC_PMEM_MEMSET_4         (0x10UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000010 */
+#define FMC_PMEM_MEMSET_5         (0x20UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000020 */
+#define FMC_PMEM_MEMSET_6         (0x40UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000040 */
+#define FMC_PMEM_MEMSET_7         (0x80UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000080 */
+
+#define FMC_PMEM_MEMWAIT_Pos      (8U)
+#define FMC_PMEM_MEMWAIT_Msk      (0xFFUL << FMC_PMEM_MEMWAIT_Pos)           /*!< 0x0000FF00 */
+#define FMC_PMEM_MEMWAIT          FMC_PMEM_MEMWAIT_Msk                       /*!<MEMWAIT[7:0] bits (Common memory wait time) */
+#define FMC_PMEM_MEMWAIT_0        (0x01UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000100 */
+#define FMC_PMEM_MEMWAIT_1        (0x02UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000200 */
+#define FMC_PMEM_MEMWAIT_2        (0x04UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000400 */
+#define FMC_PMEM_MEMWAIT_3        (0x08UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000800 */
+#define FMC_PMEM_MEMWAIT_4        (0x10UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00001000 */
+#define FMC_PMEM_MEMWAIT_5        (0x20UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00002000 */
+#define FMC_PMEM_MEMWAIT_6        (0x40UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00004000 */
+#define FMC_PMEM_MEMWAIT_7        (0x80UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00008000 */
+
+#define FMC_PMEM_MEMHOLD_Pos      (16U)
+#define FMC_PMEM_MEMHOLD_Msk      (0xFFUL << FMC_PMEM_MEMHOLD_Pos)           /*!< 0x00FF0000 */
+#define FMC_PMEM_MEMHOLD          FMC_PMEM_MEMHOLD_Msk                       /*!<MEMHOLD[7:0] bits (Common memory hold time) */
+#define FMC_PMEM_MEMHOLD_0        (0x01UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00010000 */
+#define FMC_PMEM_MEMHOLD_1        (0x02UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00020000 */
+#define FMC_PMEM_MEMHOLD_2        (0x04UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00040000 */
+#define FMC_PMEM_MEMHOLD_3        (0x08UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00080000 */
+#define FMC_PMEM_MEMHOLD_4        (0x10UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00100000 */
+#define FMC_PMEM_MEMHOLD_5        (0x20UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00200000 */
+#define FMC_PMEM_MEMHOLD_6        (0x40UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00400000 */
+#define FMC_PMEM_MEMHOLD_7        (0x80UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00800000 */
+
+#define FMC_PMEM_MEMHIZ_Pos       (24U)
+#define FMC_PMEM_MEMHIZ_Msk       (0xFFUL << FMC_PMEM_MEMHIZ_Pos)            /*!< 0xFF000000 */
+#define FMC_PMEM_MEMHIZ           FMC_PMEM_MEMHIZ_Msk                        /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */
+#define FMC_PMEM_MEMHIZ_0         (0x01UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x01000000 */
+#define FMC_PMEM_MEMHIZ_1         (0x02UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x02000000 */
+#define FMC_PMEM_MEMHIZ_2         (0x04UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x04000000 */
+#define FMC_PMEM_MEMHIZ_3         (0x08UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x08000000 */
+#define FMC_PMEM_MEMHIZ_4         (0x10UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x10000000 */
+#define FMC_PMEM_MEMHIZ_5         (0x20UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x20000000 */
+#define FMC_PMEM_MEMHIZ_6         (0x40UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x40000000 */
+#define FMC_PMEM_MEMHIZ_7         (0x80UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_PATT register  ******************/
+#define FMC_PATT_ATTSET_Pos       (0U)
+#define FMC_PATT_ATTSET_Msk       (0xFFUL << FMC_PATT_ATTSET_Pos)            /*!< 0x000000FF */
+#define FMC_PATT_ATTSET           FMC_PATT_ATTSET_Msk                        /*!<ATTSET[7:0] bits (Attribute memory setup time) */
+#define FMC_PATT_ATTSET_0         (0x01UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000001 */
+#define FMC_PATT_ATTSET_1         (0x02UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000002 */
+#define FMC_PATT_ATTSET_2         (0x04UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000004 */
+#define FMC_PATT_ATTSET_3         (0x08UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000008 */
+#define FMC_PATT_ATTSET_4         (0x10UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000010 */
+#define FMC_PATT_ATTSET_5         (0x20UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000020 */
+#define FMC_PATT_ATTSET_6         (0x40UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000040 */
+#define FMC_PATT_ATTSET_7         (0x80UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000080 */
+
+#define FMC_PATT_ATTWAIT_Pos      (8U)
+#define FMC_PATT_ATTWAIT_Msk      (0xFFUL << FMC_PATT_ATTWAIT_Pos)           /*!< 0x0000FF00 */
+#define FMC_PATT_ATTWAIT          FMC_PATT_ATTWAIT_Msk                       /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */
+#define FMC_PATT_ATTWAIT_0        (0x01UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000100 */
+#define FMC_PATT_ATTWAIT_1        (0x02UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000200 */
+#define FMC_PATT_ATTWAIT_2        (0x04UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000400 */
+#define FMC_PATT_ATTWAIT_3        (0x08UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000800 */
+#define FMC_PATT_ATTWAIT_4        (0x10UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00001000 */
+#define FMC_PATT_ATTWAIT_5        (0x20UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00002000 */
+#define FMC_PATT_ATTWAIT_6        (0x40UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00004000 */
+#define FMC_PATT_ATTWAIT_7        (0x80UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00008000 */
+
+#define FMC_PATT_ATTHOLD_Pos      (16U)
+#define FMC_PATT_ATTHOLD_Msk      (0xFFUL << FMC_PATT_ATTHOLD_Pos)           /*!< 0x00FF0000 */
+#define FMC_PATT_ATTHOLD          FMC_PATT_ATTHOLD_Msk                       /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */
+#define FMC_PATT_ATTHOLD_0        (0x01UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00010000 */
+#define FMC_PATT_ATTHOLD_1        (0x02UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00020000 */
+#define FMC_PATT_ATTHOLD_2        (0x04UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00040000 */
+#define FMC_PATT_ATTHOLD_3        (0x08UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00080000 */
+#define FMC_PATT_ATTHOLD_4        (0x10UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00100000 */
+#define FMC_PATT_ATTHOLD_5        (0x20UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00200000 */
+#define FMC_PATT_ATTHOLD_6        (0x40UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00400000 */
+#define FMC_PATT_ATTHOLD_7        (0x80UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00800000 */
+
+#define FMC_PATT_ATTHIZ_Pos       (24U)
+#define FMC_PATT_ATTHIZ_Msk       (0xFFUL << FMC_PATT_ATTHIZ_Pos)            /*!< 0xFF000000 */
+#define FMC_PATT_ATTHIZ           FMC_PATT_ATTHIZ_Msk                        /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */
+#define FMC_PATT_ATTHIZ_0         (0x01UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x01000000 */
+#define FMC_PATT_ATTHIZ_1         (0x02UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x02000000 */
+#define FMC_PATT_ATTHIZ_2         (0x04UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x04000000 */
+#define FMC_PATT_ATTHIZ_3         (0x08UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x08000000 */
+#define FMC_PATT_ATTHIZ_4         (0x10UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x10000000 */
+#define FMC_PATT_ATTHIZ_5         (0x20UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x20000000 */
+#define FMC_PATT_ATTHIZ_6         (0x40UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x40000000 */
+#define FMC_PATT_ATTHIZ_7         (0x80UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_ECCR3 register  ******************/
+#define FMC_ECCR3_ECC3_Pos         (0U)
+#define FMC_ECCR3_ECC3_Msk         (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos)        /*!< 0xFFFFFFFF */
+#define FMC_ECCR3_ECC3             FMC_ECCR3_ECC3_Msk                          /*!<ECC result */
+
+/******************  Bit definition for FMC_SDCRx registers (x=1..4)  *********/
+#define FMC_SDCRx_NC_Pos           (0U)
+#define FMC_SDCRx_NC_Msk           (0x3UL << FMC_SDCRx_NC_Pos)                 /*!< 0x00000003 */
+#define FMC_SDCRx_NC               FMC_SDCRx_NC_Msk                            /*!<NC[1:0] bits (Number of column bits) */
+#define FMC_SDCRx_NC_0             (0x1UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000001 */
+#define FMC_SDCRx_NC_1             (0x2UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000002 */
+
+#define FMC_SDCRx_NR_Pos           (2U)
+#define FMC_SDCRx_NR_Msk           (0x3UL << FMC_SDCRx_NR_Pos)                 /*!< 0x0000000C */
+#define FMC_SDCRx_NR               FMC_SDCRx_NR_Msk                            /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCRx_NR_0             (0x1UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000004 */
+#define FMC_SDCRx_NR_1             (0x2UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000008 */
+
+#define FMC_SDCRx_MWID_Pos         (4U)
+#define FMC_SDCRx_MWID_Msk         (0x3UL << FMC_SDCRx_MWID_Pos)               /*!< 0x00000030 */
+#define FMC_SDCRx_MWID             FMC_SDCRx_MWID_Msk                          /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCRx_MWID_0           (0x1UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000010 */
+#define FMC_SDCRx_MWID_1           (0x2UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000020 */
+
+#define FMC_SDCRx_NB_Pos           (6U)
+#define FMC_SDCRx_NB_Msk           (0x1UL << FMC_SDCRx_NB_Pos)                 /*!< 0x00000040 */
+#define FMC_SDCRx_NB               FMC_SDCRx_NB_Msk                            /*!<Number of internal bank */
+
+#define FMC_SDCRx_CAS_Pos          (7U)
+#define FMC_SDCRx_CAS_Msk          (0x3UL << FMC_SDCRx_CAS_Pos)                /*!< 0x00000180 */
+#define FMC_SDCRx_CAS              FMC_SDCRx_CAS_Msk                           /*!<CAS[1:0] bits (CAS latency) */
+#define FMC_SDCRx_CAS_0            (0x1UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000080 */
+#define FMC_SDCRx_CAS_1            (0x2UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000100 */
+
+#define FMC_SDCRx_WP_Pos           (9U)
+#define FMC_SDCRx_WP_Msk           (0x1UL << FMC_SDCRx_WP_Pos)                 /*!< 0x00000200 */
+#define FMC_SDCRx_WP               FMC_SDCRx_WP_Msk                            /*!<Write protection */
+
+#define FMC_SDCRx_SDCLK_Pos        (10U)
+#define FMC_SDCRx_SDCLK_Msk        (0x3UL << FMC_SDCRx_SDCLK_Pos)              /*!< 0x00000C00 */
+#define FMC_SDCRx_SDCLK            FMC_SDCRx_SDCLK_Msk                         /*!<SDRAM clock configuration */
+#define FMC_SDCRx_SDCLK_0          (0x1UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000400 */
+#define FMC_SDCRx_SDCLK_1          (0x2UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000800 */
+
+#define FMC_SDCRx_RBURST_Pos       (12U)
+#define FMC_SDCRx_RBURST_Msk       (0x1UL << FMC_SDCRx_RBURST_Pos)             /*!< 0x00001000 */
+#define FMC_SDCRx_RBURST           FMC_SDCRx_RBURST_Msk                        /*!<Read burst */
+
+#define FMC_SDCRx_RPIPE_Pos        (13U)
+#define FMC_SDCRx_RPIPE_Msk        (0x3UL << FMC_SDCRx_RPIPE_Pos)              /*!< 0x00006000 */
+#define FMC_SDCRx_RPIPE            FMC_SDCRx_RPIPE_Msk                         /*!<Write protection */
+#define FMC_SDCRx_RPIPE_0          (0x1UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00002000 */
+#define FMC_SDCRx_RPIPE_1          (0x2UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00004000 */
+
+/******************  Bit definition for FMC_SDTRx(1,2) register  ******************/
+#define FMC_SDTRx_TMRD_Pos         (0U)
+#define FMC_SDTRx_TMRD_Msk         (0xFUL << FMC_SDTRx_TMRD_Pos)               /*!< 0x0000000F */
+#define FMC_SDTRx_TMRD             FMC_SDTRx_TMRD_Msk                          /*!<TMRD[3:0] bits (Load mode register to active) */
+#define FMC_SDTRx_TMRD_0           (0x1UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000001 */
+#define FMC_SDTRx_TMRD_1           (0x2UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000002 */
+#define FMC_SDTRx_TMRD_2           (0x4UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000004 */
+#define FMC_SDTRx_TMRD_3           (0x8UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000008 */
+
+#define FMC_SDTRx_TXSR_Pos         (4U)
+#define FMC_SDTRx_TXSR_Msk         (0xFUL << FMC_SDTRx_TXSR_Pos)               /*!< 0x000000F0 */
+#define FMC_SDTRx_TXSR             FMC_SDTRx_TXSR_Msk                          /*!<TXSR[3:0] bits (Exit self refresh) */
+#define FMC_SDTRx_TXSR_0           (0x1UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000010 */
+#define FMC_SDTRx_TXSR_1           (0x2UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000020 */
+#define FMC_SDTRx_TXSR_2           (0x4UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000040 */
+#define FMC_SDTRx_TXSR_3           (0x8UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000080 */
+
+#define FMC_SDTRx_TRAS_Pos         (8U)
+#define FMC_SDTRx_TRAS_Msk         (0xFUL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000F00 */
+#define FMC_SDTRx_TRAS             FMC_SDTRx_TRAS_Msk                          /*!<TRAS[3:0] bits (Self refresh time) */
+#define FMC_SDTRx_TRAS_0           (0x1UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000100 */
+#define FMC_SDTRx_TRAS_1           (0x2UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000200 */
+#define FMC_SDTRx_TRAS_2           (0x4UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000400 */
+#define FMC_SDTRx_TRAS_3           (0x8UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000800 */
+
+#define FMC_SDTRx_TRC_Pos          (12U)
+#define FMC_SDTRx_TRC_Msk          (0xFUL << FMC_SDTRx_TRC_Pos)                /*!< 0x0000F000 */
+#define FMC_SDTRx_TRC              FMC_SDTRx_TRC_Msk                           /*!<TRC[2:0] bits (Row cycle delay) */
+#define FMC_SDTRx_TRC_0            (0x1UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00001000 */
+#define FMC_SDTRx_TRC_1            (0x2UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00002000 */
+#define FMC_SDTRx_TRC_2            (0x4UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00004000 */
+
+#define FMC_SDTRx_TWR_Pos          (16U)
+#define FMC_SDTRx_TWR_Msk          (0xFUL << FMC_SDTRx_TWR_Pos)                /*!< 0x000F0000 */
+#define FMC_SDTRx_TWR              FMC_SDTRx_TWR_Msk                           /*!<TRC[2:0] bits (Write recovery delay) */
+#define FMC_SDTRx_TWR_0            (0x1UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00010000 */
+#define FMC_SDTRx_TWR_1            (0x2UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00020000 */
+#define FMC_SDTRx_TWR_2            (0x4UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00040000 */
+
+#define FMC_SDTRx_TRP_Pos          (20U)
+#define FMC_SDTRx_TRP_Msk          (0xFUL << FMC_SDTRx_TRP_Pos)                /*!< 0x00F00000 */
+#define FMC_SDTRx_TRP              FMC_SDTRx_TRP_Msk                           /*!<TRP[2:0] bits (Row precharge delay) */
+#define FMC_SDTRx_TRP_0            (0x1UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00100000 */
+#define FMC_SDTRx_TRP_1            (0x2UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00200000 */
+#define FMC_SDTRx_TRP_2            (0x4UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00400000 */
+
+#define FMC_SDTRx_TRCD_Pos         (24U)
+#define FMC_SDTRx_TRCD_Msk         (0xFUL << FMC_SDTRx_TRCD_Pos)               /*!< 0x0F000000 */
+#define FMC_SDTRx_TRCD             FMC_SDTRx_TRCD_Msk                          /*!<TRP[2:0] bits (Row to column delay) */
+#define FMC_SDTRx_TRCD_0           (0x1UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x01000000 */
+#define FMC_SDTRx_TRCD_1           (0x2UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x02000000 */
+#define FMC_SDTRx_TRCD_2           (0x4UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x04000000 */
+
+/******************  Bit definition for FMC_SDCMR register  ******************/
+#define FMC_SDCMR_MODE_Pos         (0U)
+#define FMC_SDCMR_MODE_Msk         (0x7UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000007 */
+#define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */
+#define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */
+#define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */
+#define FMC_SDCMR_MODE_2           (0x3UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000003 */
+
+#define FMC_SDCMR_CTB2_Pos         (3U)
+#define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */
+#define FMC_SDCMR_CTB2             FMC_SDCMR_CTB2_Msk                          /*!<Command target 2 */
+
+#define FMC_SDCMR_CTB1_Pos         (4U)
+#define FMC_SDCMR_CTB1_Msk         (0x1UL << FMC_SDCMR_CTB1_Pos)               /*!< 0x00000010 */
+#define FMC_SDCMR_CTB1             FMC_SDCMR_CTB1_Msk                          /*!<Command target 1 */
+
+#define FMC_SDCMR_NRFS_Pos         (5U)
+#define FMC_SDCMR_NRFS_Msk         (0xFUL << FMC_SDCMR_NRFS_Pos)               /*!< 0x000001E0 */
+#define FMC_SDCMR_NRFS             FMC_SDCMR_NRFS_Msk                          /*!<NRFS[3:0] bits (Number of auto-refresh) */
+#define FMC_SDCMR_NRFS_0           (0x1UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000020 */
+#define FMC_SDCMR_NRFS_1           (0x2UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000040 */
+#define FMC_SDCMR_NRFS_2           (0x4UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000080 */
+#define FMC_SDCMR_NRFS_3           (0x8UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000100 */
+
+#define FMC_SDCMR_MRD_Pos          (9U)
+#define FMC_SDCMR_MRD_Msk          (0x1FFFUL << FMC_SDCMR_MRD_Pos)             /*!< 0x003FFE00 */
+#define FMC_SDCMR_MRD              FMC_SDCMR_MRD_Msk                           /*!<MRD[12:0] bits (Mode register definition) */
+
+/******************  Bit definition for FMC_SDRTR register  ******************/
+#define FMC_SDRTR_CRE_Pos          (0U)
+#define FMC_SDRTR_CRE_Msk          (0x1UL << FMC_SDRTR_CRE_Pos)                /*!< 0x00000001 */
+#define FMC_SDRTR_CRE              FMC_SDRTR_CRE_Msk                           /*!<Clear refresh error flag */
+
+#define FMC_SDRTR_COUNT_Pos        (1U)
+#define FMC_SDRTR_COUNT_Msk        (0x1FFFUL << FMC_SDRTR_COUNT_Pos)           /*!< 0x00003FFE */
+#define FMC_SDRTR_COUNT            FMC_SDRTR_COUNT_Msk                         /*!<COUNT[12:0] bits (Refresh timer count) */
+
+#define FMC_SDRTR_REIE_Pos         (14U)
+#define FMC_SDRTR_REIE_Msk         (0x1UL << FMC_SDRTR_REIE_Pos)               /*!< 0x00004000 */
+#define FMC_SDRTR_REIE             FMC_SDRTR_REIE_Msk                          /*!<RES interupt enable */
+
+/******************  Bit definition for FMC_SDSR register  ******************/
+#define FMC_SDSR_RE_Pos            (0U)
+#define FMC_SDSR_RE_Msk            (0x1UL << FMC_SDSR_RE_Pos)                  /*!< 0x00000001 */
+#define FMC_SDSR_RE                FMC_SDSR_RE_Msk                             /*!<Refresh error flag */
+
+#define FMC_SDSR_MODES1_Pos        (1U)
+#define FMC_SDSR_MODES1_Msk        (0x3UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000006 */
+#define FMC_SDSR_MODES1            FMC_SDSR_MODES1_Msk                         /*!<MODES1[1:0]bits (Status mode for bank 1) */
+#define FMC_SDSR_MODES1_0          (0x1UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000002 */
+#define FMC_SDSR_MODES1_1          (0x2UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000004 */
+
+#define FMC_SDSR_MODES2_Pos        (3U)
+#define FMC_SDSR_MODES2_Msk        (0x3UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000018 */
+#define FMC_SDSR_MODES2            FMC_SDSR_MODES2_Msk                         /*!<MODES2[1:0]bits (Status mode for bank 2) */
+#define FMC_SDSR_MODES2_0          (0x1UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000008 */
+#define FMC_SDSR_MODES2_1          (0x2UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000010 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            General Purpose I/O                             */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bits definition for GPIO_MODER register  *****************/
+#define GPIO_MODER_MODE0_Pos           (0U)
+#define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
+#define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000002 */
+
+#define GPIO_MODER_MODE1_Pos           (2U)
+#define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
+#define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000008 */
+
+#define GPIO_MODER_MODE2_Pos           (4U)
+#define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
+#define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000020 */
+
+#define GPIO_MODER_MODE3_Pos           (6U)
+#define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000080 */
+
+#define GPIO_MODER_MODE4_Pos           (8U)
+#define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
+#define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000200 */
+
+#define GPIO_MODER_MODE5_Pos           (10U)
+#define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000800 */
+
+#define GPIO_MODER_MODE6_Pos           (12U)
+#define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
+#define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00002000 */
+
+#define GPIO_MODER_MODE7_Pos           (14U)
+#define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00008000 */
+
+#define GPIO_MODER_MODE8_Pos           (16U)
+#define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
+#define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00020000 */
+
+#define GPIO_MODER_MODE9_Pos           (18U)
+#define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00080000 */
+
+#define GPIO_MODER_MODE10_Pos          (20U)
+#define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
+#define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00200000 */
+
+#define GPIO_MODER_MODE11_Pos          (22U)
+#define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00800000 */
+
+#define GPIO_MODER_MODE12_Pos          (24U)
+#define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
+#define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)         /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)         /*!< 0x02000000 */
+
+#define GPIO_MODER_MODE13_Pos          (26U)
+#define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)         /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)         /*!< 0x08000000 */
+
+#define GPIO_MODER_MODE14_Pos          (28U)
+#define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
+#define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)         /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)         /*!< 0x20000000 */
+
+#define GPIO_MODER_MODE15_Pos          (30U)
+#define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)         /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)         /*!< 0x80000000 */
+
+/******************  Bits definition for GPIO_OTYPER register  ****************/
+#define GPIO_OTYPER_OT0_Pos            (0U)
+#define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */
+#define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk
+#define GPIO_OTYPER_OT1_Pos            (1U)
+#define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */
+#define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk
+#define GPIO_OTYPER_OT2_Pos            (2U)
+#define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */
+#define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk
+#define GPIO_OTYPER_OT3_Pos            (3U)
+#define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */
+#define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk
+#define GPIO_OTYPER_OT4_Pos            (4U)
+#define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */
+#define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk
+#define GPIO_OTYPER_OT5_Pos            (5U)
+#define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */
+#define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk
+#define GPIO_OTYPER_OT6_Pos            (6U)
+#define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */
+#define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk
+#define GPIO_OTYPER_OT7_Pos            (7U)
+#define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */
+#define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk
+#define GPIO_OTYPER_OT8_Pos            (8U)
+#define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */
+#define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk
+#define GPIO_OTYPER_OT9_Pos            (9U)
+#define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */
+#define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk
+#define GPIO_OTYPER_OT10_Pos           (10U)
+#define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */
+#define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk
+#define GPIO_OTYPER_OT11_Pos           (11U)
+#define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */
+#define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk
+#define GPIO_OTYPER_OT12_Pos           (12U)
+#define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */
+#define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk
+#define GPIO_OTYPER_OT13_Pos           (13U)
+#define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */
+#define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk
+#define GPIO_OTYPER_OT14_Pos           (14U)
+#define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */
+#define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk
+#define GPIO_OTYPER_OT15_Pos           (15U)
+#define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */
+#define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk
+
+/******************  Bits definition for GPIO_OSPEEDR register  ***************/
+#define GPIO_OSPEEDR_OSPEED0_Pos       (0U)
+#define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */
+#define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk
+#define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000001 */
+#define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000002 */
+
+#define GPIO_OSPEEDR_OSPEED1_Pos       (2U)
+#define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */
+#define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk
+#define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000004 */
+#define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000008 */
+
+#define GPIO_OSPEEDR_OSPEED2_Pos       (4U)
+#define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */
+#define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk
+#define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000010 */
+#define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000020 */
+
+#define GPIO_OSPEEDR_OSPEED3_Pos       (6U)
+#define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */
+#define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk
+#define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000040 */
+#define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000080 */
+
+#define GPIO_OSPEEDR_OSPEED4_Pos       (8U)
+#define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */
+#define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk
+#define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000100 */
+#define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000200 */
+
+#define GPIO_OSPEEDR_OSPEED5_Pos       (10U)
+#define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */
+#define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk
+#define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000400 */
+#define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000800 */
+
+#define GPIO_OSPEEDR_OSPEED6_Pos       (12U)
+#define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */
+#define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk
+#define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00001000 */
+#define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00002000 */
+
+#define GPIO_OSPEEDR_OSPEED7_Pos       (14U)
+#define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */
+#define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk
+#define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00004000 */
+#define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00008000 */
+
+#define GPIO_OSPEEDR_OSPEED8_Pos       (16U)
+#define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */
+#define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk
+#define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00010000 */
+#define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00020000 */
+
+#define GPIO_OSPEEDR_OSPEED9_Pos       (18U)
+#define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */
+#define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk
+#define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00040000 */
+#define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00080000 */
+
+#define GPIO_OSPEEDR_OSPEED10_Pos      (20U)
+#define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */
+#define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk
+#define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00100000 */
+#define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00200000 */
+
+#define GPIO_OSPEEDR_OSPEED11_Pos      (22U)
+#define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */
+#define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk
+#define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00400000 */
+#define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00800000 */
+
+#define GPIO_OSPEEDR_OSPEED12_Pos      (24U)
+#define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */
+#define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk
+#define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x01000000 */
+#define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x02000000 */
+
+#define GPIO_OSPEEDR_OSPEED13_Pos      (26U)
+#define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */
+#define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk
+#define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x04000000 */
+#define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x08000000 */
+
+#define GPIO_OSPEEDR_OSPEED14_Pos      (28U)
+#define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */
+#define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk
+#define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x10000000 */
+#define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x20000000 */
+
+#define GPIO_OSPEEDR_OSPEED15_Pos      (30U)
+#define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */
+#define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk
+#define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x40000000 */
+#define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x80000000 */
+
+/******************  Bits definition for GPIO_PUPDR register  *****************/
+#define GPIO_PUPDR_PUPD0_Pos           (0U)
+#define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000002 */
+
+#define GPIO_PUPDR_PUPD1_Pos           (2U)
+#define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000008 */
+
+#define GPIO_PUPDR_PUPD2_Pos           (4U)
+#define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000020 */
+
+#define GPIO_PUPDR_PUPD3_Pos           (6U)
+#define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000080 */
+
+#define GPIO_PUPDR_PUPD4_Pos           (8U)
+#define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000200 */
+
+#define GPIO_PUPDR_PUPD5_Pos           (10U)
+#define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000800 */
+
+#define GPIO_PUPDR_PUPD6_Pos           (12U)
+#define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00002000 */
+
+#define GPIO_PUPDR_PUPD7_Pos           (14U)
+#define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00008000 */
+
+#define GPIO_PUPDR_PUPD8_Pos           (16U)
+#define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00020000 */
+
+#define GPIO_PUPDR_PUPD9_Pos           (18U)
+#define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00080000 */
+
+#define GPIO_PUPDR_PUPD10_Pos          (20U)
+#define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00200000 */
+
+#define GPIO_PUPDR_PUPD11_Pos          (22U)
+#define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00800000 */
+
+#define GPIO_PUPDR_PUPD12_Pos          (24U)
+#define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x02000000 */
+
+#define GPIO_PUPDR_PUPD13_Pos          (26U)
+#define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x08000000 */
+
+#define GPIO_PUPDR_PUPD14_Pos          (28U)
+#define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x20000000 */
+
+#define GPIO_PUPDR_PUPD15_Pos          (30U)
+#define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x80000000 */
+
+/******************  Bits definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_ID0_Pos               (0U)
+#define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
+#define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos               (1U)
+#define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
+#define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos               (2U)
+#define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
+#define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos               (3U)
+#define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
+#define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos               (4U)
+#define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
+#define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos               (5U)
+#define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
+#define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos               (6U)
+#define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
+#define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos               (7U)
+#define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
+#define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos               (8U)
+#define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
+#define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos               (9U)
+#define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
+#define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos              (10U)
+#define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
+#define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos              (11U)
+#define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
+#define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos              (12U)
+#define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
+#define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos              (13U)
+#define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
+#define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos              (14U)
+#define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
+#define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos              (15U)
+#define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
+#define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk
+
+/******************  Bits definition for GPIO_ODR register  *******************/
+#define GPIO_ODR_OD0_Pos               (0U)
+#define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
+#define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos               (1U)
+#define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
+#define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos               (2U)
+#define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
+#define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos               (3U)
+#define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
+#define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos               (4U)
+#define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
+#define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos               (5U)
+#define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
+#define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos               (6U)
+#define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
+#define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos               (7U)
+#define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
+#define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos               (8U)
+#define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
+#define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos               (9U)
+#define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
+#define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos              (10U)
+#define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
+#define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos              (11U)
+#define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
+#define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos              (12U)
+#define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
+#define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos              (13U)
+#define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
+#define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos              (14U)
+#define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
+#define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos              (15U)
+#define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
+#define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk
+
+/******************  Bits definition for GPIO_BSRR register  ******************/
+#define GPIO_BSRR_BS0_Pos              (0U)
+#define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */
+#define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk
+#define GPIO_BSRR_BS1_Pos              (1U)
+#define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */
+#define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk
+#define GPIO_BSRR_BS2_Pos              (2U)
+#define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */
+#define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk
+#define GPIO_BSRR_BS3_Pos              (3U)
+#define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */
+#define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk
+#define GPIO_BSRR_BS4_Pos              (4U)
+#define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */
+#define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk
+#define GPIO_BSRR_BS5_Pos              (5U)
+#define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */
+#define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk
+#define GPIO_BSRR_BS6_Pos              (6U)
+#define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */
+#define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk
+#define GPIO_BSRR_BS7_Pos              (7U)
+#define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */
+#define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk
+#define GPIO_BSRR_BS8_Pos              (8U)
+#define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */
+#define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk
+#define GPIO_BSRR_BS9_Pos              (9U)
+#define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */
+#define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk
+#define GPIO_BSRR_BS10_Pos             (10U)
+#define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */
+#define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk
+#define GPIO_BSRR_BS11_Pos             (11U)
+#define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */
+#define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk
+#define GPIO_BSRR_BS12_Pos             (12U)
+#define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */
+#define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk
+#define GPIO_BSRR_BS13_Pos             (13U)
+#define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */
+#define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk
+#define GPIO_BSRR_BS14_Pos             (14U)
+#define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */
+#define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk
+#define GPIO_BSRR_BS15_Pos             (15U)
+#define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */
+#define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk
+#define GPIO_BSRR_BR0_Pos              (16U)
+#define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */
+#define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk
+#define GPIO_BSRR_BR1_Pos              (17U)
+#define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */
+#define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk
+#define GPIO_BSRR_BR2_Pos              (18U)
+#define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */
+#define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk
+#define GPIO_BSRR_BR3_Pos              (19U)
+#define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */
+#define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk
+#define GPIO_BSRR_BR4_Pos              (20U)
+#define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */
+#define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk
+#define GPIO_BSRR_BR5_Pos              (21U)
+#define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */
+#define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk
+#define GPIO_BSRR_BR6_Pos              (22U)
+#define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */
+#define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk
+#define GPIO_BSRR_BR7_Pos              (23U)
+#define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */
+#define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk
+#define GPIO_BSRR_BR8_Pos              (24U)
+#define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */
+#define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk
+#define GPIO_BSRR_BR9_Pos              (25U)
+#define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */
+#define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk
+#define GPIO_BSRR_BR10_Pos             (26U)
+#define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */
+#define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk
+#define GPIO_BSRR_BR11_Pos             (27U)
+#define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */
+#define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk
+#define GPIO_BSRR_BR12_Pos             (28U)
+#define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */
+#define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk
+#define GPIO_BSRR_BR13_Pos             (29U)
+#define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */
+#define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk
+#define GPIO_BSRR_BR14_Pos             (30U)
+#define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */
+#define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk
+#define GPIO_BSRR_BR15_Pos             (31U)
+#define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */
+#define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0_Pos             (0U)
+#define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos             (1U)
+#define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos             (2U)
+#define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos             (3U)
+#define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos             (4U)
+#define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos             (5U)
+#define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos             (6U)
+#define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos             (7U)
+#define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos             (8U)
+#define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos             (9U)
+#define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos            (10U)
+#define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos            (11U)
+#define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos            (12U)
+#define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos            (13U)
+#define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos            (14U)
+#define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos            (15U)
+#define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos             (16U)
+#define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk
+
+/****************** Bit definition for GPIO_AFRL register  ********************/
+#define GPIO_AFRL_AFSEL0_Pos           (0U)
+#define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000001 */
+#define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000002 */
+#define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000004 */
+#define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000008 */
+#define GPIO_AFRL_AFSEL1_Pos           (4U)
+#define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000010 */
+#define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000020 */
+#define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000040 */
+#define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000080 */
+#define GPIO_AFRL_AFSEL2_Pos           (8U)
+#define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000100 */
+#define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000200 */
+#define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000400 */
+#define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000800 */
+#define GPIO_AFRL_AFSEL3_Pos           (12U)
+#define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00001000 */
+#define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00002000 */
+#define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00004000 */
+#define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00008000 */
+#define GPIO_AFRL_AFSEL4_Pos           (16U)
+#define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00010000 */
+#define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00020000 */
+#define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00040000 */
+#define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00080000 */
+#define GPIO_AFRL_AFSEL5_Pos           (20U)
+#define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00100000 */
+#define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00200000 */
+#define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00400000 */
+#define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00800000 */
+#define GPIO_AFRL_AFSEL6_Pos           (24U)
+#define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x01000000 */
+#define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x02000000 */
+#define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x04000000 */
+#define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x08000000 */
+#define GPIO_AFRL_AFSEL7_Pos           (28U)
+#define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk
+#define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x10000000 */
+#define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x20000000 */
+#define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x40000000 */
+#define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0
+#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1
+#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2
+#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3
+#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4
+#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5
+#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6
+#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7
+
+/****************** Bit definition for GPIO_AFRH register  ********************/
+#define GPIO_AFRH_AFSEL8_Pos           (0U)
+#define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000001 */
+#define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000002 */
+#define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000004 */
+#define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000008 */
+#define GPIO_AFRH_AFSEL9_Pos           (4U)
+#define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000010 */
+#define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000020 */
+#define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000040 */
+#define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000080 */
+#define GPIO_AFRH_AFSEL10_Pos          (8U)
+#define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000100 */
+#define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000200 */
+#define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000400 */
+#define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000800 */
+#define GPIO_AFRH_AFSEL11_Pos          (12U)
+#define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00001000 */
+#define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00002000 */
+#define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00004000 */
+#define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00008000 */
+#define GPIO_AFRH_AFSEL12_Pos          (16U)
+#define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00010000 */
+#define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00020000 */
+#define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00040000 */
+#define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00080000 */
+#define GPIO_AFRH_AFSEL13_Pos          (20U)
+#define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00100000 */
+#define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00200000 */
+#define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00400000 */
+#define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00800000 */
+#define GPIO_AFRH_AFSEL14_Pos          (24U)
+#define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x01000000 */
+#define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x02000000 */
+#define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x04000000 */
+#define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x08000000 */
+#define GPIO_AFRH_AFSEL15_Pos          (28U)
+#define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk
+#define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x10000000 */
+#define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x20000000 */
+#define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x40000000 */
+#define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8
+#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9
+#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10
+#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11
+#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12
+#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13
+#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14
+#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15
+
+/******************************************************************************/
+/*                                                                            */
+/*                        HSEM HW Semaphore                                   */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for HSEM_R register  ********************/
+#define HSEM_R_PROCID_Pos         (0U)
+#define HSEM_R_PROCID_Msk         (0xFFUL << HSEM_R_PROCID_Pos)                /*!< 0x000000FF */
+#define HSEM_R_PROCID             HSEM_R_PROCID_Msk                            /*!<Semaphore ProcessID */
+#define HSEM_R_COREID_Pos         (8U)
+#define HSEM_R_COREID_Msk         (0xFFUL << HSEM_R_COREID_Pos)                /*!< 0x0000FF00 */
+#define HSEM_R_COREID             HSEM_R_COREID_Msk                            /*!<Semaphore CoreID.   */
+#define HSEM_R_LOCK_Pos           (31U)
+#define HSEM_R_LOCK_Msk           (0x1UL << HSEM_R_LOCK_Pos)                   /*!< 0x80000000 */
+#define HSEM_R_LOCK               HSEM_R_LOCK_Msk                              /*!<Lock indication.    */
+
+/********************  Bit definition for HSEM_RLR register  ******************/
+#define HSEM_RLR_PROCID_Pos       (0U)
+#define HSEM_RLR_PROCID_Msk       (0xFFUL << HSEM_RLR_PROCID_Pos)              /*!< 0x000000FF */
+#define HSEM_RLR_PROCID           HSEM_RLR_PROCID_Msk                          /*!<Semaphore ProcessID */
+#define HSEM_RLR_COREID_Pos       (8U)
+#define HSEM_RLR_COREID_Msk       (0xFFUL << HSEM_RLR_COREID_Pos)              /*!< 0x0000FF00 */
+#define HSEM_RLR_COREID           HSEM_RLR_COREID_Msk                          /*!<Semaphore CoreID.   */
+#define HSEM_RLR_LOCK_Pos         (31U)
+#define HSEM_RLR_LOCK_Msk         (0x1UL << HSEM_RLR_LOCK_Pos)                 /*!< 0x80000000 */
+#define HSEM_RLR_LOCK             HSEM_RLR_LOCK_Msk                            /*!<Lock indication.    */
+
+/********************  Bit definition for HSEM_C1IER register  *****************/
+#define HSEM_C1IER_ISE0_Pos       (0U)
+#define HSEM_C1IER_ISE0_Msk       (0x1UL << HSEM_C1IER_ISE0_Pos)               /*!< 0x00000001 */
+#define HSEM_C1IER_ISE0           HSEM_C1IER_ISE0_Msk                          /*!<semaphore 0 , interrupt 0 enable bit.  */
+#define HSEM_C1IER_ISE1_Pos       (1U)
+#define HSEM_C1IER_ISE1_Msk       (0x1UL << HSEM_C1IER_ISE1_Pos)               /*!< 0x00000002 */
+#define HSEM_C1IER_ISE1           HSEM_C1IER_ISE1_Msk                          /*!<semaphore 1 , interrupt 0 enable bit.  */
+#define HSEM_C1IER_ISE2_Pos       (2U)
+#define HSEM_C1IER_ISE2_Msk       (0x1UL << HSEM_C1IER_ISE2_Pos)               /*!< 0x00000004 */
+#define HSEM_C1IER_ISE2           HSEM_C1IER_ISE2_Msk                          /*!<semaphore 2 , interrupt 0 enable bit.  */
+#define HSEM_C1IER_ISE3_Pos       (3U)
+#define HSEM_C1IER_ISE3_Msk       (0x1UL << HSEM_C1IER_ISE3_Pos)               /*!< 0x00000008 */
+#define HSEM_C1IER_ISE3           HSEM_C1IER_ISE3_Msk                          /*!<semaphore 3 , interrupt 0 enable bit.  */
+#define HSEM_C1IER_ISE4_Pos       (4U)
+#define HSEM_C1IER_ISE4_Msk       (0x1UL << HSEM_C1IER_ISE4_Pos)               /*!< 0x00000010 */
+#define HSEM_C1IER_ISE4           HSEM_C1IER_ISE4_Msk                          /*!<semaphore 4 , interrupt 0 enable bit.  */
+#define HSEM_C1IER_ISE5_Pos       (5U)
+#define HSEM_C1IER_ISE5_Msk       (0x1UL << HSEM_C1IER_ISE5_Pos)               /*!< 0x00000020 */
+#define HSEM_C1IER_ISE5           HSEM_C1IER_ISE5_Msk                          /*!<semaphore 5 interrupt 0 enable bit.    */
+#define HSEM_C1IER_ISE6_Pos       (6U)
+#define HSEM_C1IER_ISE6_Msk       (0x1UL << HSEM_C1IER_ISE6_Pos)               /*!< 0x00000040 */
+#define HSEM_C1IER_ISE6           HSEM_C1IER_ISE6_Msk                          /*!<semaphore 6 interrupt 0 enable bit.    */
+#define HSEM_C1IER_ISE7_Pos       (7U)
+#define HSEM_C1IER_ISE7_Msk       (0x1UL << HSEM_C1IER_ISE7_Pos)               /*!< 0x00000080 */
+#define HSEM_C1IER_ISE7           HSEM_C1IER_ISE7_Msk                          /*!<semaphore 7 interrupt 0 enable bit.    */
+#define HSEM_C1IER_ISE8_Pos       (8U)
+#define HSEM_C1IER_ISE8_Msk       (0x1UL << HSEM_C1IER_ISE8_Pos)               /*!< 0x00000100 */
+#define HSEM_C1IER_ISE8           HSEM_C1IER_ISE8_Msk                          /*!<semaphore 8 interrupt 0 enable bit.    */
+#define HSEM_C1IER_ISE9_Pos       (9U)
+#define HSEM_C1IER_ISE9_Msk       (0x1UL << HSEM_C1IER_ISE9_Pos)               /*!< 0x00000200 */
+#define HSEM_C1IER_ISE9           HSEM_C1IER_ISE9_Msk                          /*!<semaphore 9 interrupt 0 enable bit.    */
+#define HSEM_C1IER_ISE10_Pos      (10U)
+#define HSEM_C1IER_ISE10_Msk      (0x1UL << HSEM_C1IER_ISE10_Pos)              /*!< 0x00000400 */
+#define HSEM_C1IER_ISE10          HSEM_C1IER_ISE10_Msk                         /*!<semaphore 10 interrupt 0 enable bit.   */
+#define HSEM_C1IER_ISE11_Pos      (11U)
+#define HSEM_C1IER_ISE11_Msk      (0x1UL << HSEM_C1IER_ISE11_Pos)              /*!< 0x00000800 */
+#define HSEM_C1IER_ISE11          HSEM_C1IER_ISE11_Msk                         /*!<semaphore 11 interrupt 0 enable bit.   */
+#define HSEM_C1IER_ISE12_Pos      (12U)
+#define HSEM_C1IER_ISE12_Msk      (0x1UL << HSEM_C1IER_ISE12_Pos)              /*!< 0x00001000 */
+#define HSEM_C1IER_ISE12          HSEM_C1IER_ISE12_Msk                         /*!<semaphore 12 interrupt 0 enable bit.   */
+#define HSEM_C1IER_ISE13_Pos      (13U)
+#define HSEM_C1IER_ISE13_Msk      (0x1UL << HSEM_C1IER_ISE13_Pos)              /*!< 0x00002000 */
+#define HSEM_C1IER_ISE13          HSEM_C1IER_ISE13_Msk                         /*!<semaphore 13 interrupt 0 enable bit.   */
+#define HSEM_C1IER_ISE14_Pos      (14U)
+#define HSEM_C1IER_ISE14_Msk      (0x1UL << HSEM_C1IER_ISE14_Pos)              /*!< 0x00004000 */
+#define HSEM_C1IER_ISE14          HSEM_C1IER_ISE14_Msk                         /*!<semaphore 14 interrupt 0 enable bit.   */
+#define HSEM_C1IER_ISE15_Pos      (15U)
+#define HSEM_C1IER_ISE15_Msk      (0x1UL << HSEM_C1IER_ISE15_Pos)              /*!< 0x00008000 */
+#define HSEM_C1IER_ISE15          HSEM_C1IER_ISE15_Msk                         /*!<semaphore 15 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE16_Pos      (16U)
+#define HSEM_C1IER_ISE16_Msk      (0x1UL << HSEM_C1IER_ISE16_Pos)              /*!< 0x00010000 */
+#define HSEM_C1IER_ISE16          HSEM_C1IER_ISE16_Msk                         /*!<semaphore 16 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE17_Pos      (17U)
+#define HSEM_C1IER_ISE17_Msk      (0x1UL << HSEM_C1IER_ISE17_Pos)              /*!< 0x00020000 */
+#define HSEM_C1IER_ISE17          HSEM_C1IER_ISE17_Msk                         /*!<semaphore 17 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE18_Pos      (18U)
+#define HSEM_C1IER_ISE18_Msk      (0x1UL << HSEM_C1IER_ISE18_Pos)              /*!< 0x00040000 */
+#define HSEM_C1IER_ISE18          HSEM_C1IER_ISE18_Msk                         /*!<semaphore 18 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE19_Pos      (19U)
+#define HSEM_C1IER_ISE19_Msk      (0x1UL << HSEM_C1IER_ISE19_Pos)              /*!< 0x00080000 */
+#define HSEM_C1IER_ISE19          HSEM_C1IER_ISE19_Msk                         /*!<semaphore 19 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE20_Pos      (20U)
+#define HSEM_C1IER_ISE20_Msk      (0x1UL << HSEM_C1IER_ISE20_Pos)              /*!< 0x00100000 */
+#define HSEM_C1IER_ISE20          HSEM_C1IER_ISE20_Msk                         /*!<semaphore 20 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE21_Pos      (21U)
+#define HSEM_C1IER_ISE21_Msk      (0x1UL << HSEM_C1IER_ISE21_Pos)              /*!< 0x00200000 */
+#define HSEM_C1IER_ISE21          HSEM_C1IER_ISE21_Msk                         /*!<semaphore 21 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE22_Pos      (22U)
+#define HSEM_C1IER_ISE22_Msk      (0x1UL << HSEM_C1IER_ISE22_Pos)              /*!< 0x00400000 */
+#define HSEM_C1IER_ISE22          HSEM_C1IER_ISE22_Msk                         /*!<semaphore 22 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE23_Pos      (23U)
+#define HSEM_C1IER_ISE23_Msk      (0x1UL << HSEM_C1IER_ISE23_Pos)              /*!< 0x00800000 */
+#define HSEM_C1IER_ISE23          HSEM_C1IER_ISE23_Msk                         /*!<semaphore 23 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE24_Pos      (24U)
+#define HSEM_C1IER_ISE24_Msk      (0x1UL << HSEM_C1IER_ISE24_Pos)              /*!< 0x01000000 */
+#define HSEM_C1IER_ISE24          HSEM_C1IER_ISE24_Msk                         /*!<semaphore 24 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE25_Pos      (25U)
+#define HSEM_C1IER_ISE25_Msk      (0x1UL << HSEM_C1IER_ISE25_Pos)              /*!< 0x02000000 */
+#define HSEM_C1IER_ISE25          HSEM_C1IER_ISE25_Msk                         /*!<semaphore 25 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE26_Pos      (26U)
+#define HSEM_C1IER_ISE26_Msk      (0x1UL << HSEM_C1IER_ISE26_Pos)              /*!< 0x04000000 */
+#define HSEM_C1IER_ISE26          HSEM_C1IER_ISE26_Msk                         /*!<semaphore 26 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE27_Pos      (27U)
+#define HSEM_C1IER_ISE27_Msk      (0x1UL << HSEM_C1IER_ISE27_Pos)              /*!< 0x08000000 */
+#define HSEM_C1IER_ISE27          HSEM_C1IER_ISE27_Msk                         /*!<semaphore 27 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE28_Pos      (28U)
+#define HSEM_C1IER_ISE28_Msk      (0x1UL << HSEM_C1IER_ISE28_Pos)              /*!< 0x10000000 */
+#define HSEM_C1IER_ISE28          HSEM_C1IER_ISE28_Msk                         /*!<semaphore 28 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE29_Pos      (29U)
+#define HSEM_C1IER_ISE29_Msk      (0x1UL << HSEM_C1IER_ISE29_Pos)              /*!< 0x20000000 */
+#define HSEM_C1IER_ISE29          HSEM_C1IER_ISE29_Msk                         /*!<semaphore 29 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE30_Pos      (30U)
+#define HSEM_C1IER_ISE30_Msk      (0x1UL << HSEM_C1IER_ISE30_Pos)              /*!< 0x40000000 */
+#define HSEM_C1IER_ISE30          HSEM_C1IER_ISE30_Msk                         /*!<semaphore 30 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE31_Pos      (31U)
+#define HSEM_C1IER_ISE31_Msk      (0x1UL << HSEM_C1IER_ISE31_Pos)              /*!< 0x80000000 */
+#define HSEM_C1IER_ISE31          HSEM_C1IER_ISE31_Msk                         /*!<semaphore 31 interrupt 0 enable bit. */
+
+/********************  Bit definition for HSEM_C1ICR register  *****************/
+#define HSEM_C1ICR_ISC0_Pos       (0U)
+#define HSEM_C1ICR_ISC0_Msk       (0x1UL << HSEM_C1ICR_ISC0_Pos)               /*!< 0x00000001 */
+#define HSEM_C1ICR_ISC0           HSEM_C1ICR_ISC0_Msk                          /*!<semaphore 0 , interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC1_Pos       (1U)
+#define HSEM_C1ICR_ISC1_Msk       (0x1UL << HSEM_C1ICR_ISC1_Pos)               /*!< 0x00000002 */
+#define HSEM_C1ICR_ISC1           HSEM_C1ICR_ISC1_Msk                          /*!<semaphore 1 , interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC2_Pos       (2U)
+#define HSEM_C1ICR_ISC2_Msk       (0x1UL << HSEM_C1ICR_ISC2_Pos)               /*!< 0x00000004 */
+#define HSEM_C1ICR_ISC2           HSEM_C1ICR_ISC2_Msk                          /*!<semaphore 2 , interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC3_Pos       (3U)
+#define HSEM_C1ICR_ISC3_Msk       (0x1UL << HSEM_C1ICR_ISC3_Pos)               /*!< 0x00000008 */
+#define HSEM_C1ICR_ISC3           HSEM_C1ICR_ISC3_Msk                          /*!<semaphore 3 , interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC4_Pos       (4U)
+#define HSEM_C1ICR_ISC4_Msk       (0x1UL << HSEM_C1ICR_ISC4_Pos)               /*!< 0x00000010 */
+#define HSEM_C1ICR_ISC4           HSEM_C1ICR_ISC4_Msk                          /*!<semaphore 4 , interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC5_Pos       (5U)
+#define HSEM_C1ICR_ISC5_Msk       (0x1UL << HSEM_C1ICR_ISC5_Pos)               /*!< 0x00000020 */
+#define HSEM_C1ICR_ISC5           HSEM_C1ICR_ISC5_Msk                          /*!<semaphore 5 interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC6_Pos       (6U)
+#define HSEM_C1ICR_ISC6_Msk       (0x1UL << HSEM_C1ICR_ISC6_Pos)               /*!< 0x00000040 */
+#define HSEM_C1ICR_ISC6           HSEM_C1ICR_ISC6_Msk                          /*!<semaphore 6 interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC7_Pos       (7U)
+#define HSEM_C1ICR_ISC7_Msk       (0x1UL << HSEM_C1ICR_ISC7_Pos)               /*!< 0x00000080 */
+#define HSEM_C1ICR_ISC7           HSEM_C1ICR_ISC7_Msk                          /*!<semaphore 7 interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC8_Pos       (8U)
+#define HSEM_C1ICR_ISC8_Msk       (0x1UL << HSEM_C1ICR_ISC8_Pos)               /*!< 0x00000100 */
+#define HSEM_C1ICR_ISC8           HSEM_C1ICR_ISC8_Msk                          /*!<semaphore 8 interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC9_Pos       (9U)
+#define HSEM_C1ICR_ISC9_Msk       (0x1UL << HSEM_C1ICR_ISC9_Pos)               /*!< 0x00000200 */
+#define HSEM_C1ICR_ISC9           HSEM_C1ICR_ISC9_Msk                          /*!<semaphore 9 interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC10_Pos      (10U)
+#define HSEM_C1ICR_ISC10_Msk      (0x1UL << HSEM_C1ICR_ISC10_Pos)              /*!< 0x00000400 */
+#define HSEM_C1ICR_ISC10          HSEM_C1ICR_ISC10_Msk                         /*!<semaphore 10 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC11_Pos      (11U)
+#define HSEM_C1ICR_ISC11_Msk      (0x1UL << HSEM_C1ICR_ISC11_Pos)              /*!< 0x00000800 */
+#define HSEM_C1ICR_ISC11          HSEM_C1ICR_ISC11_Msk                         /*!<semaphore 11 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC12_Pos      (12U)
+#define HSEM_C1ICR_ISC12_Msk      (0x1UL << HSEM_C1ICR_ISC12_Pos)              /*!< 0x00001000 */
+#define HSEM_C1ICR_ISC12          HSEM_C1ICR_ISC12_Msk                         /*!<semaphore 12 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC13_Pos      (13U)
+#define HSEM_C1ICR_ISC13_Msk      (0x1UL << HSEM_C1ICR_ISC13_Pos)              /*!< 0x00002000 */
+#define HSEM_C1ICR_ISC13          HSEM_C1ICR_ISC13_Msk                         /*!<semaphore 13 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC14_Pos      (14U)
+#define HSEM_C1ICR_ISC14_Msk      (0x1UL << HSEM_C1ICR_ISC14_Pos)              /*!< 0x00004000 */
+#define HSEM_C1ICR_ISC14          HSEM_C1ICR_ISC14_Msk                         /*!<semaphore 14 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC15_Pos      (15U)
+#define HSEM_C1ICR_ISC15_Msk      (0x1UL << HSEM_C1ICR_ISC15_Pos)              /*!< 0x00008000 */
+#define HSEM_C1ICR_ISC15          HSEM_C1ICR_ISC15_Msk                         /*!<semaphore 15 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC16_Pos      (16U)
+#define HSEM_C1ICR_ISC16_Msk      (0x1UL << HSEM_C1ICR_ISC16_Pos)              /*!< 0x00010000 */
+#define HSEM_C1ICR_ISC16          HSEM_C1ICR_ISC16_Msk                         /*!<semaphore 16 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC17_Pos      (17U)
+#define HSEM_C1ICR_ISC17_Msk      (0x1UL << HSEM_C1ICR_ISC17_Pos)              /*!< 0x00020000 */
+#define HSEM_C1ICR_ISC17          HSEM_C1ICR_ISC17_Msk                         /*!<semaphore 17 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC18_Pos      (18U)
+#define HSEM_C1ICR_ISC18_Msk      (0x1UL << HSEM_C1ICR_ISC18_Pos)              /*!< 0x00040000 */
+#define HSEM_C1ICR_ISC18          HSEM_C1ICR_ISC18_Msk                         /*!<semaphore 18 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC19_Pos      (19U)
+#define HSEM_C1ICR_ISC19_Msk      (0x1UL << HSEM_C1ICR_ISC19_Pos)              /*!< 0x00080000 */
+#define HSEM_C1ICR_ISC19          HSEM_C1ICR_ISC19_Msk                         /*!<semaphore 19 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC20_Pos      (20U)
+#define HSEM_C1ICR_ISC20_Msk      (0x1UL << HSEM_C1ICR_ISC20_Pos)              /*!< 0x00100000 */
+#define HSEM_C1ICR_ISC20          HSEM_C1ICR_ISC20_Msk                         /*!<semaphore 20 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC21_Pos      (21U)
+#define HSEM_C1ICR_ISC21_Msk      (0x1UL << HSEM_C1ICR_ISC21_Pos)              /*!< 0x00200000 */
+#define HSEM_C1ICR_ISC21          HSEM_C1ICR_ISC21_Msk                         /*!<semaphore 21 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC22_Pos      (22U)
+#define HSEM_C1ICR_ISC22_Msk      (0x1UL << HSEM_C1ICR_ISC22_Pos)              /*!< 0x00400000 */
+#define HSEM_C1ICR_ISC22          HSEM_C1ICR_ISC22_Msk                         /*!<semaphore 22 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC23_Pos      (23U)
+#define HSEM_C1ICR_ISC23_Msk      (0x1UL << HSEM_C1ICR_ISC23_Pos)              /*!< 0x00800000 */
+#define HSEM_C1ICR_ISC23          HSEM_C1ICR_ISC23_Msk                         /*!<semaphore 23 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC24_Pos      (24U)
+#define HSEM_C1ICR_ISC24_Msk      (0x1UL << HSEM_C1ICR_ISC24_Pos)              /*!< 0x01000000 */
+#define HSEM_C1ICR_ISC24          HSEM_C1ICR_ISC24_Msk                         /*!<semaphore 24 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC25_Pos      (25U)
+#define HSEM_C1ICR_ISC25_Msk      (0x1UL << HSEM_C1ICR_ISC25_Pos)              /*!< 0x02000000 */
+#define HSEM_C1ICR_ISC25          HSEM_C1ICR_ISC25_Msk                         /*!<semaphore 25 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC26_Pos      (26U)
+#define HSEM_C1ICR_ISC26_Msk      (0x1UL << HSEM_C1ICR_ISC26_Pos)              /*!< 0x04000000 */
+#define HSEM_C1ICR_ISC26          HSEM_C1ICR_ISC26_Msk                         /*!<semaphore 26 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC27_Pos      (27U)
+#define HSEM_C1ICR_ISC27_Msk      (0x1UL << HSEM_C1ICR_ISC27_Pos)              /*!< 0x08000000 */
+#define HSEM_C1ICR_ISC27          HSEM_C1ICR_ISC27_Msk                         /*!<semaphore 27 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC28_Pos      (28U)
+#define HSEM_C1ICR_ISC28_Msk      (0x1UL << HSEM_C1ICR_ISC28_Pos)              /*!< 0x10000000 */
+#define HSEM_C1ICR_ISC28          HSEM_C1ICR_ISC28_Msk                         /*!<semaphore 28 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC29_Pos      (29U)
+#define HSEM_C1ICR_ISC29_Msk      (0x1UL << HSEM_C1ICR_ISC29_Pos)              /*!< 0x20000000 */
+#define HSEM_C1ICR_ISC29          HSEM_C1ICR_ISC29_Msk                         /*!<semaphore 29 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC30_Pos      (30U)
+#define HSEM_C1ICR_ISC30_Msk      (0x1UL << HSEM_C1ICR_ISC30_Pos)              /*!< 0x40000000 */
+#define HSEM_C1ICR_ISC30          HSEM_C1ICR_ISC30_Msk                         /*!<semaphore 30 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC31_Pos      (31U)
+#define HSEM_C1ICR_ISC31_Msk      (0x1UL << HSEM_C1ICR_ISC31_Pos)              /*!< 0x80000000 */
+#define HSEM_C1ICR_ISC31          HSEM_C1ICR_ISC31_Msk                         /*!<semaphore 31 interrupt 0 clear bit. */
+
+/********************  Bit definition for HSEM_C1ISR register  *****************/
+#define HSEM_C1ISR_ISF0_Pos       (0U)
+#define HSEM_C1ISR_ISF0_Msk       (0x1UL << HSEM_C1ISR_ISF0_Pos)               /*!< 0x00000001 */
+#define HSEM_C1ISR_ISF0           HSEM_C1ISR_ISF0_Msk                          /*!<semaphore 0 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF1_Pos       (1U)
+#define HSEM_C1ISR_ISF1_Msk       (0x1UL << HSEM_C1ISR_ISF1_Pos)               /*!< 0x00000002 */
+#define HSEM_C1ISR_ISF1           HSEM_C1ISR_ISF1_Msk                          /*!<semaphore 1 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF2_Pos       (2U)
+#define HSEM_C1ISR_ISF2_Msk       (0x1UL << HSEM_C1ISR_ISF2_Pos)               /*!< 0x00000004 */
+#define HSEM_C1ISR_ISF2           HSEM_C1ISR_ISF2_Msk                          /*!<semaphore 2 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF3_Pos       (3U)
+#define HSEM_C1ISR_ISF3_Msk       (0x1UL << HSEM_C1ISR_ISF3_Pos)               /*!< 0x00000008 */
+#define HSEM_C1ISR_ISF3           HSEM_C1ISR_ISF3_Msk                          /*!<semaphore 3 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF4_Pos       (4U)
+#define HSEM_C1ISR_ISF4_Msk       (0x1UL << HSEM_C1ISR_ISF4_Pos)               /*!< 0x00000010 */
+#define HSEM_C1ISR_ISF4           HSEM_C1ISR_ISF4_Msk                          /*!<semaphore 4 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF5_Pos       (5U)
+#define HSEM_C1ISR_ISF5_Msk       (0x1UL << HSEM_C1ISR_ISF5_Pos)               /*!< 0x00000020 */
+#define HSEM_C1ISR_ISF5           HSEM_C1ISR_ISF5_Msk                          /*!<semaphore 5 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF6_Pos       (6U)
+#define HSEM_C1ISR_ISF6_Msk       (0x1UL << HSEM_C1ISR_ISF6_Pos)               /*!< 0x00000040 */
+#define HSEM_C1ISR_ISF6           HSEM_C1ISR_ISF6_Msk                          /*!<semaphore 6 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF7_Pos       (7U)
+#define HSEM_C1ISR_ISF7_Msk       (0x1UL << HSEM_C1ISR_ISF7_Pos)               /*!< 0x00000080 */
+#define HSEM_C1ISR_ISF7           HSEM_C1ISR_ISF7_Msk                          /*!<semaphore 7 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF8_Pos       (8U)
+#define HSEM_C1ISR_ISF8_Msk       (0x1UL << HSEM_C1ISR_ISF8_Pos)               /*!< 0x00000100 */
+#define HSEM_C1ISR_ISF8           HSEM_C1ISR_ISF8_Msk                          /*!<semaphore 8 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF9_Pos       (9U)
+#define HSEM_C1ISR_ISF9_Msk       (0x1UL << HSEM_C1ISR_ISF9_Pos)               /*!< 0x00000200 */
+#define HSEM_C1ISR_ISF9           HSEM_C1ISR_ISF9_Msk                          /*!<semaphore 9 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF10_Pos      (10U)
+#define HSEM_C1ISR_ISF10_Msk      (0x1UL << HSEM_C1ISR_ISF10_Pos)              /*!< 0x00000400 */
+#define HSEM_C1ISR_ISF10          HSEM_C1ISR_ISF10_Msk                         /*!<semaphore 10 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF11_Pos      (11U)
+#define HSEM_C1ISR_ISF11_Msk      (0x1UL << HSEM_C1ISR_ISF11_Pos)              /*!< 0x00000800 */
+#define HSEM_C1ISR_ISF11          HSEM_C1ISR_ISF11_Msk                         /*!<semaphore 11 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF12_Pos      (12U)
+#define HSEM_C1ISR_ISF12_Msk      (0x1UL << HSEM_C1ISR_ISF12_Pos)              /*!< 0x00001000 */
+#define HSEM_C1ISR_ISF12          HSEM_C1ISR_ISF12_Msk                         /*!<semaphore 12 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF13_Pos      (13U)
+#define HSEM_C1ISR_ISF13_Msk      (0x1UL << HSEM_C1ISR_ISF13_Pos)              /*!< 0x00002000 */
+#define HSEM_C1ISR_ISF13          HSEM_C1ISR_ISF13_Msk                         /*!<semaphore 13 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF14_Pos      (14U)
+#define HSEM_C1ISR_ISF14_Msk      (0x1UL << HSEM_C1ISR_ISF14_Pos)              /*!< 0x00004000 */
+#define HSEM_C1ISR_ISF14          HSEM_C1ISR_ISF14_Msk                         /*!<semaphore 14 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF15_Pos      (15U)
+#define HSEM_C1ISR_ISF15_Msk      (0x1UL << HSEM_C1ISR_ISF15_Pos)              /*!< 0x00008000 */
+#define HSEM_C1ISR_ISF15          HSEM_C1ISR_ISF15_Msk                         /*!<semaphore 15 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF16_Pos      (16U)
+#define HSEM_C1ISR_ISF16_Msk      (0x1UL << HSEM_C1ISR_ISF16_Pos)              /*!< 0x00010000 */
+#define HSEM_C1ISR_ISF16          HSEM_C1ISR_ISF16_Msk                         /*!<semaphore 16 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF17_Pos      (17U)
+#define HSEM_C1ISR_ISF17_Msk      (0x1UL << HSEM_C1ISR_ISF17_Pos)              /*!< 0x00020000 */
+#define HSEM_C1ISR_ISF17          HSEM_C1ISR_ISF17_Msk                         /*!<semaphore 17 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF18_Pos      (18U)
+#define HSEM_C1ISR_ISF18_Msk      (0x1UL << HSEM_C1ISR_ISF18_Pos)              /*!< 0x00040000 */
+#define HSEM_C1ISR_ISF18          HSEM_C1ISR_ISF18_Msk                         /*!<semaphore 18 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF19_Pos      (19U)
+#define HSEM_C1ISR_ISF19_Msk      (0x1UL << HSEM_C1ISR_ISF19_Pos)              /*!< 0x00080000 */
+#define HSEM_C1ISR_ISF19          HSEM_C1ISR_ISF19_Msk                         /*!<semaphore 19 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF20_Pos      (20U)
+#define HSEM_C1ISR_ISF20_Msk      (0x1UL << HSEM_C1ISR_ISF20_Pos)              /*!< 0x00100000 */
+#define HSEM_C1ISR_ISF20          HSEM_C1ISR_ISF20_Msk                         /*!<semaphore 20 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF21_Pos      (21U)
+#define HSEM_C1ISR_ISF21_Msk      (0x1UL << HSEM_C1ISR_ISF21_Pos)              /*!< 0x00200000 */
+#define HSEM_C1ISR_ISF21          HSEM_C1ISR_ISF21_Msk                         /*!<semaphore 21 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF22_Pos      (22U)
+#define HSEM_C1ISR_ISF22_Msk      (0x1UL << HSEM_C1ISR_ISF22_Pos)              /*!< 0x00400000 */
+#define HSEM_C1ISR_ISF22          HSEM_C1ISR_ISF22_Msk                         /*!<semaphore 22 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF23_Pos      (23U)
+#define HSEM_C1ISR_ISF23_Msk      (0x1UL << HSEM_C1ISR_ISF23_Pos)              /*!< 0x00800000 */
+#define HSEM_C1ISR_ISF23          HSEM_C1ISR_ISF23_Msk                         /*!<semaphore 23 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF24_Pos      (24U)
+#define HSEM_C1ISR_ISF24_Msk      (0x1UL << HSEM_C1ISR_ISF24_Pos)              /*!< 0x01000000 */
+#define HSEM_C1ISR_ISF24          HSEM_C1ISR_ISF24_Msk                         /*!<semaphore 24 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF25_Pos      (25U)
+#define HSEM_C1ISR_ISF25_Msk      (0x1UL << HSEM_C1ISR_ISF25_Pos)              /*!< 0x02000000 */
+#define HSEM_C1ISR_ISF25          HSEM_C1ISR_ISF25_Msk                         /*!<semaphore 25 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF26_Pos      (26U)
+#define HSEM_C1ISR_ISF26_Msk      (0x1UL << HSEM_C1ISR_ISF26_Pos)              /*!< 0x04000000 */
+#define HSEM_C1ISR_ISF26          HSEM_C1ISR_ISF26_Msk                         /*!<semaphore 26 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF27_Pos      (27U)
+#define HSEM_C1ISR_ISF27_Msk      (0x1UL << HSEM_C1ISR_ISF27_Pos)              /*!< 0x08000000 */
+#define HSEM_C1ISR_ISF27          HSEM_C1ISR_ISF27_Msk                         /*!<semaphore 27 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF28_Pos      (28U)
+#define HSEM_C1ISR_ISF28_Msk      (0x1UL << HSEM_C1ISR_ISF28_Pos)              /*!< 0x10000000 */
+#define HSEM_C1ISR_ISF28          HSEM_C1ISR_ISF28_Msk                         /*!<semaphore 28 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF29_Pos      (29U)
+#define HSEM_C1ISR_ISF29_Msk      (0x1UL << HSEM_C1ISR_ISF29_Pos)              /*!< 0x20000000 */
+#define HSEM_C1ISR_ISF29          HSEM_C1ISR_ISF29_Msk                         /*!<semaphore 29 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF30_Pos      (30U)
+#define HSEM_C1ISR_ISF30_Msk      (0x1UL << HSEM_C1ISR_ISF30_Pos)              /*!< 0x40000000 */
+#define HSEM_C1ISR_ISF30          HSEM_C1ISR_ISF30_Msk                         /*!<semaphore 30 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF31_Pos      (31U)
+#define HSEM_C1ISR_ISF31_Msk      (0x1UL << HSEM_C1ISR_ISF31_Pos)              /*!< 0x80000000 */
+#define HSEM_C1ISR_ISF31          HSEM_C1ISR_ISF31_Msk                         /*!<semaphore 31 interrupt 0 status bit. */
+
+/********************  Bit definition for HSEM_C1MISR register  *****************/
+#define HSEM_C1MISR_MISF0_Pos     (0U)
+#define HSEM_C1MISR_MISF0_Msk     (0x1UL << HSEM_C1MISR_MISF0_Pos)             /*!< 0x00000001 */
+#define HSEM_C1MISR_MISF0         HSEM_C1MISR_MISF0_Msk                        /*!<semaphore 0 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF1_Pos     (1U)
+#define HSEM_C1MISR_MISF1_Msk     (0x1UL << HSEM_C1MISR_MISF1_Pos)             /*!< 0x00000002 */
+#define HSEM_C1MISR_MISF1         HSEM_C1MISR_MISF1_Msk                        /*!<semaphore 1 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF2_Pos     (2U)
+#define HSEM_C1MISR_MISF2_Msk     (0x1UL << HSEM_C1MISR_MISF2_Pos)             /*!< 0x00000004 */
+#define HSEM_C1MISR_MISF2         HSEM_C1MISR_MISF2_Msk                        /*!<semaphore 2 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF3_Pos     (3U)
+#define HSEM_C1MISR_MISF3_Msk     (0x1UL << HSEM_C1MISR_MISF3_Pos)             /*!< 0x00000008 */
+#define HSEM_C1MISR_MISF3         HSEM_C1MISR_MISF3_Msk                        /*!<semaphore 3 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF4_Pos     (4U)
+#define HSEM_C1MISR_MISF4_Msk     (0x1UL << HSEM_C1MISR_MISF4_Pos)             /*!< 0x00000010 */
+#define HSEM_C1MISR_MISF4         HSEM_C1MISR_MISF4_Msk                        /*!<semaphore 4 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF5_Pos     (5U)
+#define HSEM_C1MISR_MISF5_Msk     (0x1UL << HSEM_C1MISR_MISF5_Pos)             /*!< 0x00000020 */
+#define HSEM_C1MISR_MISF5         HSEM_C1MISR_MISF5_Msk                        /*!<semaphore 5 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF6_Pos     (6U)
+#define HSEM_C1MISR_MISF6_Msk     (0x1UL << HSEM_C1MISR_MISF6_Pos)             /*!< 0x00000040 */
+#define HSEM_C1MISR_MISF6         HSEM_C1MISR_MISF6_Msk                        /*!<semaphore 6 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF7_Pos     (7U)
+#define HSEM_C1MISR_MISF7_Msk     (0x1UL << HSEM_C1MISR_MISF7_Pos)             /*!< 0x00000080 */
+#define HSEM_C1MISR_MISF7         HSEM_C1MISR_MISF7_Msk                        /*!<semaphore 7 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF8_Pos     (8U)
+#define HSEM_C1MISR_MISF8_Msk     (0x1UL << HSEM_C1MISR_MISF8_Pos)             /*!< 0x00000100 */
+#define HSEM_C1MISR_MISF8         HSEM_C1MISR_MISF8_Msk                        /*!<semaphore 8 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF9_Pos     (9U)
+#define HSEM_C1MISR_MISF9_Msk     (0x1UL << HSEM_C1MISR_MISF9_Pos)             /*!< 0x00000200 */
+#define HSEM_C1MISR_MISF9         HSEM_C1MISR_MISF9_Msk                        /*!<semaphore 9 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF10_Pos    (10U)
+#define HSEM_C1MISR_MISF10_Msk    (0x1UL << HSEM_C1MISR_MISF10_Pos)            /*!< 0x00000400 */
+#define HSEM_C1MISR_MISF10        HSEM_C1MISR_MISF10_Msk                       /*!<semaphore 10 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF11_Pos    (11U)
+#define HSEM_C1MISR_MISF11_Msk    (0x1UL << HSEM_C1MISR_MISF11_Pos)            /*!< 0x00000800 */
+#define HSEM_C1MISR_MISF11        HSEM_C1MISR_MISF11_Msk                       /*!<semaphore 11 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF12_Pos    (12U)
+#define HSEM_C1MISR_MISF12_Msk    (0x1UL << HSEM_C1MISR_MISF12_Pos)            /*!< 0x00001000 */
+#define HSEM_C1MISR_MISF12        HSEM_C1MISR_MISF12_Msk                       /*!<semaphore 12 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF13_Pos    (13U)
+#define HSEM_C1MISR_MISF13_Msk    (0x1UL << HSEM_C1MISR_MISF13_Pos)            /*!< 0x00002000 */
+#define HSEM_C1MISR_MISF13        HSEM_C1MISR_MISF13_Msk                       /*!<semaphore 13 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF14_Pos    (14U)
+#define HSEM_C1MISR_MISF14_Msk    (0x1UL << HSEM_C1MISR_MISF14_Pos)            /*!< 0x00004000 */
+#define HSEM_C1MISR_MISF14        HSEM_C1MISR_MISF14_Msk                       /*!<semaphore 14 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF15_Pos    (15U)
+#define HSEM_C1MISR_MISF15_Msk    (0x1UL << HSEM_C1MISR_MISF15_Pos)            /*!< 0x00008000 */
+#define HSEM_C1MISR_MISF15        HSEM_C1MISR_MISF15_Msk                       /*!<semaphore 15 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF16_Pos    (16U)
+#define HSEM_C1MISR_MISF16_Msk    (0x1UL << HSEM_C1MISR_MISF16_Pos)            /*!< 0x00010000 */
+#define HSEM_C1MISR_MISF16        HSEM_C1MISR_MISF16_Msk                       /*!<semaphore 16 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF17_Pos    (17U)
+#define HSEM_C1MISR_MISF17_Msk    (0x1UL << HSEM_C1MISR_MISF17_Pos)            /*!< 0x00020000 */
+#define HSEM_C1MISR_MISF17        HSEM_C1MISR_MISF17_Msk                       /*!<semaphore 17 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF18_Pos    (18U)
+#define HSEM_C1MISR_MISF18_Msk    (0x1UL << HSEM_C1MISR_MISF18_Pos)            /*!< 0x00040000 */
+#define HSEM_C1MISR_MISF18        HSEM_C1MISR_MISF18_Msk                       /*!<semaphore 18 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF19_Pos    (19U)
+#define HSEM_C1MISR_MISF19_Msk    (0x1UL << HSEM_C1MISR_MISF19_Pos)            /*!< 0x00080000 */
+#define HSEM_C1MISR_MISF19        HSEM_C1MISR_MISF19_Msk                       /*!<semaphore 19 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF20_Pos    (20U)
+#define HSEM_C1MISR_MISF20_Msk    (0x1UL << HSEM_C1MISR_MISF20_Pos)            /*!< 0x00100000 */
+#define HSEM_C1MISR_MISF20        HSEM_C1MISR_MISF20_Msk                       /*!<semaphore 20 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF21_Pos    (21U)
+#define HSEM_C1MISR_MISF21_Msk    (0x1UL << HSEM_C1MISR_MISF21_Pos)            /*!< 0x00200000 */
+#define HSEM_C1MISR_MISF21        HSEM_C1MISR_MISF21_Msk                       /*!<semaphore 21 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF22_Pos    (22U)
+#define HSEM_C1MISR_MISF22_Msk    (0x1UL << HSEM_C1MISR_MISF22_Pos)            /*!< 0x00400000 */
+#define HSEM_C1MISR_MISF22        HSEM_C1MISR_MISF22_Msk                       /*!<semaphore 22 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF23_Pos    (23U)
+#define HSEM_C1MISR_MISF23_Msk    (0x1UL << HSEM_C1MISR_MISF23_Pos)            /*!< 0x00800000 */
+#define HSEM_C1MISR_MISF23        HSEM_C1MISR_MISF23_Msk                       /*!<semaphore 23 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF24_Pos    (24U)
+#define HSEM_C1MISR_MISF24_Msk    (0x1UL << HSEM_C1MISR_MISF24_Pos)            /*!< 0x01000000 */
+#define HSEM_C1MISR_MISF24        HSEM_C1MISR_MISF24_Msk                       /*!<semaphore 24 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF25_Pos    (25U)
+#define HSEM_C1MISR_MISF25_Msk    (0x1UL << HSEM_C1MISR_MISF25_Pos)            /*!< 0x02000000 */
+#define HSEM_C1MISR_MISF25        HSEM_C1MISR_MISF25_Msk                       /*!<semaphore 25 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF26_Pos    (26U)
+#define HSEM_C1MISR_MISF26_Msk    (0x1UL << HSEM_C1MISR_MISF26_Pos)            /*!< 0x04000000 */
+#define HSEM_C1MISR_MISF26        HSEM_C1MISR_MISF26_Msk                       /*!<semaphore 26 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF27_Pos    (27U)
+#define HSEM_C1MISR_MISF27_Msk    (0x1UL << HSEM_C1MISR_MISF27_Pos)            /*!< 0x08000000 */
+#define HSEM_C1MISR_MISF27        HSEM_C1MISR_MISF27_Msk                       /*!<semaphore 27 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF28_Pos    (28U)
+#define HSEM_C1MISR_MISF28_Msk    (0x1UL << HSEM_C1MISR_MISF28_Pos)            /*!< 0x10000000 */
+#define HSEM_C1MISR_MISF28        HSEM_C1MISR_MISF28_Msk                       /*!<semaphore 28 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF29_Pos    (29U)
+#define HSEM_C1MISR_MISF29_Msk    (0x1UL << HSEM_C1MISR_MISF29_Pos)            /*!< 0x20000000 */
+#define HSEM_C1MISR_MISF29        HSEM_C1MISR_MISF29_Msk                       /*!<semaphore 29 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF30_Pos    (30U)
+#define HSEM_C1MISR_MISF30_Msk    (0x1UL << HSEM_C1MISR_MISF30_Pos)            /*!< 0x40000000 */
+#define HSEM_C1MISR_MISF30        HSEM_C1MISR_MISF30_Msk                       /*!<semaphore 30 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF31_Pos    (31U)
+#define HSEM_C1MISR_MISF31_Msk    (0x1UL << HSEM_C1MISR_MISF31_Pos)            /*!< 0x80000000 */
+#define HSEM_C1MISR_MISF31        HSEM_C1MISR_MISF31_Msk                       /*!<semaphore 31 interrupt 0 masked status bit. */
+
+/********************  Bit definition for HSEM_CR register  *****************/
+#define HSEM_CR_COREID_Pos        (8U)
+#define HSEM_CR_COREID_Msk        (0xFFUL << HSEM_CR_COREID_Pos)               /*!< 0x0000FF00 */
+#define HSEM_CR_COREID            HSEM_CR_COREID_Msk                           /*!<CoreID of semaphores to be cleared. */
+#define HSEM_CR_KEY_Pos           (16U)
+#define HSEM_CR_KEY_Msk           (0xFFFFUL << HSEM_CR_KEY_Pos)                /*!< 0xFFFF0000 */
+#define HSEM_CR_KEY               HSEM_CR_KEY_Msk                              /*!<semaphores clear key. */
+
+/********************  Bit definition for HSEM_KEYR register  *****************/
+#define HSEM_KEYR_KEY_Pos         (16U)
+#define HSEM_KEYR_KEY_Msk         (0xFFFFUL << HSEM_KEYR_KEY_Pos)              /*!< 0xFFFF0000 */
+#define HSEM_KEYR_KEY             HSEM_KEYR_KEY_Msk                            /*!<semaphores clear key. */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Inter-integrated Circuit Interface (I2C)              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for I2C_CR1 register  *******************/
+#define I2C_CR1_PE_Pos               (0U)
+#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                 /*!< 0x00000001 */
+#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */
+#define I2C_CR1_TXIE_Pos             (1U)
+#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)               /*!< 0x00000002 */
+#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */
+#define I2C_CR1_RXIE_Pos             (2U)
+#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)               /*!< 0x00000004 */
+#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE_Pos           (3U)
+#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)             /*!< 0x00000008 */
+#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE_Pos           (4U)
+#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)             /*!< 0x00000010 */
+#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE_Pos           (5U)
+#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)             /*!< 0x00000020 */
+#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE_Pos             (6U)
+#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)               /*!< 0x00000040 */
+#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE_Pos            (7U)
+#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)              /*!< 0x00000080 */
+#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */
+#define I2C_CR1_DNF_Pos              (8U)
+#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                /*!< 0x00000F00 */
+#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF_Pos           (12U)
+#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)             /*!< 0x00001000 */
+#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */
+#define I2C_CR1_TXDMAEN_Pos          (14U)
+#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)            /*!< 0x00004000 */
+#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN_Pos          (15U)
+#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)            /*!< 0x00008000 */
+#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */
+#define I2C_CR1_SBC_Pos              (16U)
+#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                /*!< 0x00010000 */
+#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH_Pos        (17U)
+#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)          /*!< 0x00020000 */
+#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN_Pos            (18U)
+#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)              /*!< 0x00040000 */
+#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN_Pos             (19U)
+#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)               /*!< 0x00080000 */
+#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */
+#define I2C_CR1_SMBHEN_Pos           (20U)
+#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)             /*!< 0x00100000 */
+#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN_Pos           (21U)
+#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)             /*!< 0x00200000 */
+#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN_Pos          (22U)
+#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)            /*!< 0x00400000 */
+#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */
+#define I2C_CR1_PECEN_Pos            (23U)
+#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)              /*!< 0x00800000 */
+#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */
+
+/******************  Bit definition for I2C_CR2 register  ********************/
+#define I2C_CR2_SADD_Pos             (0U)
+#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)             /*!< 0x000003FF */
+#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN_Pos           (10U)
+#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)             /*!< 0x00000400 */
+#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10_Pos            (11U)
+#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)              /*!< 0x00000800 */
+#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R_Pos          (12U)
+#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)            /*!< 0x00001000 */
+#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START_Pos            (13U)
+#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)              /*!< 0x00002000 */
+#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */
+#define I2C_CR2_STOP_Pos             (14U)
+#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)               /*!< 0x00004000 */
+#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK_Pos             (15U)
+#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)               /*!< 0x00008000 */
+#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES_Pos           (16U)
+#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)            /*!< 0x00FF0000 */
+#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */
+#define I2C_CR2_RELOAD_Pos           (24U)
+#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)             /*!< 0x01000000 */
+#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND_Pos          (25U)
+#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)            /*!< 0x02000000 */
+#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE_Pos          (26U)
+#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)            /*!< 0x04000000 */
+#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */
+
+/*******************  Bit definition for I2C_OAR1 register  ******************/
+#define I2C_OAR1_OA1_Pos             (0U)
+#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)             /*!< 0x000003FF */
+#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE_Pos         (10U)
+#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)           /*!< 0x00000400 */
+#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN_Pos           (15U)
+#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)             /*!< 0x00008000 */
+#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */
+
+/*******************  Bit definition for I2C_OAR2 register  ******************/
+#define I2C_OAR2_OA2_Pos             (1U)
+#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)              /*!< 0x000000FE */
+#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK_Pos          (8U)
+#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)            /*!< 0x00000700 */
+#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK           0x00000000UL                              /*!< No mask */
+#define I2C_OAR2_OA2MASK01_Pos       (8U)
+#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)         /*!< 0x00000100 */
+#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02_Pos       (9U)
+#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)         /*!< 0x00000200 */
+#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03_Pos       (8U)
+#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)         /*!< 0x00000300 */
+#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04_Pos       (10U)
+#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)         /*!< 0x00000400 */
+#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05_Pos       (8U)
+#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)         /*!< 0x00000500 */
+#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06_Pos       (9U)
+#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)         /*!< 0x00000600 */
+#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07_Pos       (8U)
+#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)         /*!< 0x00000700 */
+#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN_Pos           (15U)
+#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)             /*!< 0x00008000 */
+#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable */
+
+/*******************  Bit definition for I2C_TIMINGR register *******************/
+#define I2C_TIMINGR_SCLL_Pos         (0U)
+#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)          /*!< 0x000000FF */
+#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH_Pos         (8U)
+#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)          /*!< 0x0000FF00 */
+#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL_Pos       (16U)
+#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)         /*!< 0x000F0000 */
+#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL_Pos       (20U)
+#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)         /*!< 0x00F00000 */
+#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */
+#define I2C_TIMINGR_PRESC_Pos        (28U)
+#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)          /*!< 0xF0000000 */
+#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)
+#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)    /*!< 0x00000FFF */
+#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE_Pos       (12U)
+#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)         /*!< 0x00001000 */
+#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)
+#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)      /*!< 0x00008000 */
+#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)
+#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)    /*!< 0x0FFF0000 */
+#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)
+#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)        /*!< 0x80000000 */
+#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
+
+/******************  Bit definition for I2C_ISR register  *********************/
+#define I2C_ISR_TXE_Pos              (0U)
+#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                /*!< 0x00000001 */
+#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */
+#define I2C_ISR_TXIS_Pos             (1U)
+#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)               /*!< 0x00000002 */
+#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE_Pos             (2U)
+#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)               /*!< 0x00000004 */
+#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
+#define I2C_ISR_ADDR_Pos             (3U)
+#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)               /*!< 0x00000008 */
+#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF_Pos            (4U)
+#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)              /*!< 0x00000010 */
+#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */
+#define I2C_ISR_STOPF_Pos            (5U)
+#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)              /*!< 0x00000020 */
+#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */
+#define I2C_ISR_TC_Pos               (6U)
+#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                 /*!< 0x00000040 */
+#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR_Pos              (7U)
+#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                /*!< 0x00000080 */
+#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */
+#define I2C_ISR_BERR_Pos             (8U)
+#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)               /*!< 0x00000100 */
+#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */
+#define I2C_ISR_ARLO_Pos             (9U)
+#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)               /*!< 0x00000200 */
+#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */
+#define I2C_ISR_OVR_Pos              (10U)
+#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                /*!< 0x00000400 */
+#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR_Pos           (11U)
+#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)             /*!< 0x00000800 */
+#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT_Pos          (12U)
+#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)            /*!< 0x00001000 */
+#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT_Pos            (13U)
+#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)              /*!< 0x00002000 */
+#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */
+#define I2C_ISR_BUSY_Pos             (15U)
+#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)               /*!< 0x00008000 */
+#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */
+#define I2C_ISR_DIR_Pos              (16U)
+#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                /*!< 0x00010000 */
+#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE_Pos          (17U)
+#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)           /*!< 0x00FE0000 */
+#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
+
+/******************  Bit definition for I2C_ICR register  *********************/
+#define I2C_ICR_ADDRCF_Pos           (3U)
+#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)             /*!< 0x00000008 */
+#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF_Pos           (4U)
+#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)             /*!< 0x00000010 */
+#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */
+#define I2C_ICR_STOPCF_Pos           (5U)
+#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)             /*!< 0x00000020 */
+#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF_Pos           (8U)
+#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)             /*!< 0x00000100 */
+#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF_Pos           (9U)
+#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)             /*!< 0x00000200 */
+#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF_Pos            (10U)
+#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)              /*!< 0x00000400 */
+#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF_Pos            (11U)
+#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)              /*!< 0x00000800 */
+#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF_Pos         (12U)
+#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)           /*!< 0x00001000 */
+#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF_Pos          (13U)
+#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)            /*!< 0x00002000 */
+#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */
+
+/******************  Bit definition for I2C_PECR register  *********************/
+#define I2C_PECR_PEC_Pos             (0U)
+#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)              /*!< 0x000000FF */
+#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
+
+/******************  Bit definition for I2C_RXDR register  *********************/
+#define I2C_RXDR_RXDATA_Pos          (0U)
+#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)           /*!< 0x000000FF */
+#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
+
+/******************  Bit definition for I2C_TXDR register  *********************/
+#define I2C_TXDR_TXDATA_Pos          (0U)
+#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)           /*!< 0x000000FF */
+#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Independent WATCHDOG                             */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define IWDG_KR_KEY_Pos      (0U)
+#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                     /*!< 0x0000FFFF */
+#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define IWDG_PR_PR_Pos       (0U)
+#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                         /*!< 0x00000007 */
+#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */
+#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */
+#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */
+#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define IWDG_RLR_RL_Pos      (0U)
+#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                      /*!< 0x00000FFF */
+#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define IWDG_SR_PVU_Pos      (0U)
+#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                        /*!< 0x00000001 */
+#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos      (1U)
+#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                        /*!< 0x00000002 */
+#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU_Pos      (2U)
+#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                        /*!< 0x00000004 */
+#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
+
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define IWDG_WINR_WIN_Pos    (0U)
+#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                    /*!< 0x00000FFF */
+#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        JPEG Encoder/Decoder                                */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for CONFR0 register  ********************/
+#define JPEG_CONFR0_START_Pos           (0U)
+#define JPEG_CONFR0_START_Msk           (0x1UL << JPEG_CONFR0_START_Pos)       /*!< 0x00000001 */
+#define JPEG_CONFR0_START               JPEG_CONFR0_START_Msk                  /*!<Start/Stop bit */
+
+/********************  Bit definition for CONFR1 register  ********************/
+#define JPEG_CONFR1_NF_Pos              (0U)
+#define JPEG_CONFR1_NF_Msk              (0x3UL << JPEG_CONFR1_NF_Pos)          /*!< 0x00000003 */
+#define JPEG_CONFR1_NF                  JPEG_CONFR1_NF_Msk                     /*!<Number of color components */
+#define JPEG_CONFR1_NF_0                (0x1UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000001 */
+#define JPEG_CONFR1_NF_1                (0x2UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000002 */
+#define JPEG_CONFR1_DE_Pos              (3U)
+#define JPEG_CONFR1_DE_Msk              (0x1UL << JPEG_CONFR1_DE_Pos)          /*!< 0x00000008 */
+#define JPEG_CONFR1_DE                  JPEG_CONFR1_DE_Msk                     /*!<Decoding Enable */
+#define JPEG_CONFR1_COLORSPACE_Pos      (4U)
+#define JPEG_CONFR1_COLORSPACE_Msk      (0x3UL << JPEG_CONFR1_COLORSPACE_Pos)  /*!< 0x00000030 */
+#define JPEG_CONFR1_COLORSPACE          JPEG_CONFR1_COLORSPACE_Msk             /*!<Color Space */
+#define JPEG_CONFR1_COLORSPACE_0        (0x1UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000010 */
+#define JPEG_CONFR1_COLORSPACE_1        (0x2UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000020 */
+#define JPEG_CONFR1_NS_Pos              (6U)
+#define JPEG_CONFR1_NS_Msk              (0x3UL << JPEG_CONFR1_NS_Pos)          /*!< 0x000000C0 */
+#define JPEG_CONFR1_NS                  JPEG_CONFR1_NS_Msk                     /*!<Number of components for Scan */
+#define JPEG_CONFR1_NS_0                (0x1UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000040 */
+#define JPEG_CONFR1_NS_1                (0x2UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000080 */
+#define JPEG_CONFR1_HDR_Pos             (8U)
+#define JPEG_CONFR1_HDR_Msk             (0x1UL << JPEG_CONFR1_HDR_Pos)         /*!< 0x00000100 */
+#define JPEG_CONFR1_HDR                 JPEG_CONFR1_HDR_Msk                    /*!<Header Processing On/Off */
+#define JPEG_CONFR1_YSIZE_Pos           (16U)
+#define JPEG_CONFR1_YSIZE_Msk           (0xFFFFUL << JPEG_CONFR1_YSIZE_Pos)    /*!< 0xFFFF0000 */
+#define JPEG_CONFR1_YSIZE               JPEG_CONFR1_YSIZE_Msk                  /*!<Number of lines in source image */
+
+/********************  Bit definition for CONFR2 register  ********************/
+#define JPEG_CONFR2_NMCU_Pos            (0U)
+#define JPEG_CONFR2_NMCU_Msk            (0x3FFFFFFUL << JPEG_CONFR2_NMCU_Pos)  /*!< 0x03FFFFFF */
+#define JPEG_CONFR2_NMCU                JPEG_CONFR2_NMCU_Msk                   /*!<Number of MCU units minus 1 to encode */
+
+/********************  Bit definition for CONFR3 register  ********************/
+#define JPEG_CONFR3_XSIZE_Pos           (16U)
+#define JPEG_CONFR3_XSIZE_Msk           (0xFFFFUL << JPEG_CONFR3_XSIZE_Pos)    /*!< 0xFFFF0000 */
+#define JPEG_CONFR3_XSIZE               JPEG_CONFR3_XSIZE_Msk                  /*!<Number of pixels per line */
+
+/********************  Bit definition for CONFR4 register  ********************/
+#define JPEG_CONFR4_HD_Pos              (0U)
+#define JPEG_CONFR4_HD_Msk              (0x1UL << JPEG_CONFR4_HD_Pos)          /*!< 0x00000001 */
+#define JPEG_CONFR4_HD                  JPEG_CONFR4_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */
+#define JPEG_CONFR4_HA_Pos              (1U)
+#define JPEG_CONFR4_HA_Msk              (0x1UL << JPEG_CONFR4_HA_Pos)          /*!< 0x00000002 */
+#define JPEG_CONFR4_HA                  JPEG_CONFR4_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */
+#define JPEG_CONFR4_QT_Pos              (2U)
+#define JPEG_CONFR4_QT_Msk              (0x3UL << JPEG_CONFR4_QT_Pos)          /*!< 0x0000000C */
+#define JPEG_CONFR4_QT                  JPEG_CONFR4_QT_Msk                     /*!<Selects quantization table associated with a color component */
+#define JPEG_CONFR4_QT_0                (0x1UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000004 */
+#define JPEG_CONFR4_QT_1                (0x2UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000008 */
+#define JPEG_CONFR4_NB_Pos              (4U)
+#define JPEG_CONFR4_NB_Msk              (0xFUL << JPEG_CONFR4_NB_Pos)          /*!< 0x000000F0 */
+#define JPEG_CONFR4_NB                  JPEG_CONFR4_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */
+#define JPEG_CONFR4_NB_0                (0x1UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000010 */
+#define JPEG_CONFR4_NB_1                (0x2UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000020 */
+#define JPEG_CONFR4_NB_2                (0x4UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000040 */
+#define JPEG_CONFR4_NB_3                (0x8UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000080 */
+#define JPEG_CONFR4_VSF_Pos             (8U)
+#define JPEG_CONFR4_VSF_Msk             (0xFUL << JPEG_CONFR4_VSF_Pos)         /*!< 0x00000F00 */
+#define JPEG_CONFR4_VSF                 JPEG_CONFR4_VSF_Msk                    /*!<Vertical sampling factor for component 1 */
+#define JPEG_CONFR4_VSF_0               (0x1UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000100 */
+#define JPEG_CONFR4_VSF_1               (0x2UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000200 */
+#define JPEG_CONFR4_VSF_2               (0x4UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000400 */
+#define JPEG_CONFR4_VSF_3               (0x8UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000800 */
+#define JPEG_CONFR4_HSF_Pos             (12U)
+#define JPEG_CONFR4_HSF_Msk             (0xFUL << JPEG_CONFR4_HSF_Pos)         /*!< 0x0000F000 */
+#define JPEG_CONFR4_HSF                 JPEG_CONFR4_HSF_Msk                    /*!<Horizontal sampling factor for component 1 */
+#define JPEG_CONFR4_HSF_0               (0x1UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00001000 */
+#define JPEG_CONFR4_HSF_1               (0x2UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00002000 */
+#define JPEG_CONFR4_HSF_2               (0x4UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00004000 */
+#define JPEG_CONFR4_HSF_3               (0x8UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00008000 */
+
+/********************  Bit definition for CONFR5 register  ********************/
+#define JPEG_CONFR5_HD_Pos              (0U)
+#define JPEG_CONFR5_HD_Msk              (0x1UL << JPEG_CONFR5_HD_Pos)          /*!< 0x00000001 */
+#define JPEG_CONFR5_HD                  JPEG_CONFR5_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */
+#define JPEG_CONFR5_HA_Pos              (1U)
+#define JPEG_CONFR5_HA_Msk              (0x1UL << JPEG_CONFR5_HA_Pos)          /*!< 0x00000002 */
+#define JPEG_CONFR5_HA                  JPEG_CONFR5_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */
+#define JPEG_CONFR5_QT_Pos              (2U)
+#define JPEG_CONFR5_QT_Msk              (0x3UL << JPEG_CONFR5_QT_Pos)          /*!< 0x0000000C */
+#define JPEG_CONFR5_QT                  JPEG_CONFR5_QT_Msk                     /*!<Selects quantization table associated with a color component */
+#define JPEG_CONFR5_QT_0                (0x1UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000004 */
+#define JPEG_CONFR5_QT_1                (0x2UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000008 */
+#define JPEG_CONFR5_NB_Pos              (4U)
+#define JPEG_CONFR5_NB_Msk              (0xFUL << JPEG_CONFR5_NB_Pos)          /*!< 0x000000F0 */
+#define JPEG_CONFR5_NB                  JPEG_CONFR5_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */
+#define JPEG_CONFR5_NB_0                (0x1UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000010 */
+#define JPEG_CONFR5_NB_1                (0x2UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000020 */
+#define JPEG_CONFR5_NB_2                (0x4UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000040 */
+#define JPEG_CONFR5_NB_3                (0x8UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000080 */
+#define JPEG_CONFR5_VSF_Pos             (8U)
+#define JPEG_CONFR5_VSF_Msk             (0xFUL << JPEG_CONFR5_VSF_Pos)         /*!< 0x00000F00 */
+#define JPEG_CONFR5_VSF                 JPEG_CONFR5_VSF_Msk                    /*!<Vertical sampling factor for component 2 */
+#define JPEG_CONFR5_VSF_0               (0x1UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000100 */
+#define JPEG_CONFR5_VSF_1               (0x2UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000200 */
+#define JPEG_CONFR5_VSF_2               (0x4UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000400 */
+#define JPEG_CONFR5_VSF_3               (0x8UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000800 */
+#define JPEG_CONFR5_HSF_Pos             (12U)
+#define JPEG_CONFR5_HSF_Msk             (0xFUL << JPEG_CONFR5_HSF_Pos)         /*!< 0x0000F000 */
+#define JPEG_CONFR5_HSF                 JPEG_CONFR5_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */
+#define JPEG_CONFR5_HSF_0               (0x1UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00001000 */
+#define JPEG_CONFR5_HSF_1               (0x2UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00002000 */
+#define JPEG_CONFR5_HSF_2               (0x4UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00004000 */
+#define JPEG_CONFR5_HSF_3               (0x8UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00008000 */
+
+/********************  Bit definition for CONFR6 register  ********************/
+#define JPEG_CONFR6_HD_Pos              (0U)
+#define JPEG_CONFR6_HD_Msk              (0x1UL << JPEG_CONFR6_HD_Pos)          /*!< 0x00000001 */
+#define JPEG_CONFR6_HD                  JPEG_CONFR6_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */
+#define JPEG_CONFR6_HA_Pos              (1U)
+#define JPEG_CONFR6_HA_Msk              (0x1UL << JPEG_CONFR6_HA_Pos)          /*!< 0x00000002 */
+#define JPEG_CONFR6_HA                  JPEG_CONFR6_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */
+#define JPEG_CONFR6_QT_Pos              (2U)
+#define JPEG_CONFR6_QT_Msk              (0x3UL << JPEG_CONFR6_QT_Pos)          /*!< 0x0000000C */
+#define JPEG_CONFR6_QT                  JPEG_CONFR6_QT_Msk                     /*!<Selects quantization table associated with a color component */
+#define JPEG_CONFR6_QT_0                (0x1UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000004 */
+#define JPEG_CONFR6_QT_1                (0x2UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000008 */
+#define JPEG_CONFR6_NB_Pos              (4U)
+#define JPEG_CONFR6_NB_Msk              (0xFUL << JPEG_CONFR6_NB_Pos)          /*!< 0x000000F0 */
+#define JPEG_CONFR6_NB                  JPEG_CONFR6_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */
+#define JPEG_CONFR6_NB_0                (0x1UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000010 */
+#define JPEG_CONFR6_NB_1                (0x2UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000020 */
+#define JPEG_CONFR6_NB_2                (0x4UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000040 */
+#define JPEG_CONFR6_NB_3                (0x8UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000080 */
+#define JPEG_CONFR6_VSF_Pos             (8U)
+#define JPEG_CONFR6_VSF_Msk             (0xFUL << JPEG_CONFR6_VSF_Pos)         /*!< 0x00000F00 */
+#define JPEG_CONFR6_VSF                 JPEG_CONFR6_VSF_Msk                    /*!<Vertical sampling factor for component 2 */
+#define JPEG_CONFR6_VSF_0               (0x1UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000100 */
+#define JPEG_CONFR6_VSF_1               (0x2UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000200 */
+#define JPEG_CONFR6_VSF_2               (0x4UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000400 */
+#define JPEG_CONFR6_VSF_3               (0x8UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000800 */
+#define JPEG_CONFR6_HSF_Pos             (12U)
+#define JPEG_CONFR6_HSF_Msk             (0xFUL << JPEG_CONFR6_HSF_Pos)         /*!< 0x0000F000 */
+#define JPEG_CONFR6_HSF                 JPEG_CONFR6_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */
+#define JPEG_CONFR6_HSF_0               (0x1UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00001000 */
+#define JPEG_CONFR6_HSF_1               (0x2UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00002000 */
+#define JPEG_CONFR6_HSF_2               (0x4UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00004000 */
+#define JPEG_CONFR6_HSF_3               (0x8UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00008000 */
+
+/********************  Bit definition for CONFR7 register  ********************/
+#define JPEG_CONFR7_HD_Pos              (0U)
+#define JPEG_CONFR7_HD_Msk              (0x1UL << JPEG_CONFR7_HD_Pos)          /*!< 0x00000001 */
+#define JPEG_CONFR7_HD                  JPEG_CONFR7_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */
+#define JPEG_CONFR7_HA_Pos              (1U)
+#define JPEG_CONFR7_HA_Msk              (0x1UL << JPEG_CONFR7_HA_Pos)          /*!< 0x00000002 */
+#define JPEG_CONFR7_HA                  JPEG_CONFR7_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */
+#define JPEG_CONFR7_QT_Pos              (2U)
+#define JPEG_CONFR7_QT_Msk              (0x3UL << JPEG_CONFR7_QT_Pos)          /*!< 0x0000000C */
+#define JPEG_CONFR7_QT                  JPEG_CONFR7_QT_Msk                     /*!<Selects quantization table associated with a color component */
+#define JPEG_CONFR7_QT_0                (0x1UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000004 */
+#define JPEG_CONFR7_QT_1                (0x2UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000008 */
+#define JPEG_CONFR7_NB_Pos              (4U)
+#define JPEG_CONFR7_NB_Msk              (0xFUL << JPEG_CONFR7_NB_Pos)          /*!< 0x000000F0 */
+#define JPEG_CONFR7_NB                  JPEG_CONFR7_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */
+#define JPEG_CONFR7_NB_0                (0x1UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000010 */
+#define JPEG_CONFR7_NB_1                (0x2UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000020 */
+#define JPEG_CONFR7_NB_2                (0x4UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000040 */
+#define JPEG_CONFR7_NB_3                (0x8UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000080 */
+#define JPEG_CONFR7_VSF_Pos             (8U)
+#define JPEG_CONFR7_VSF_Msk             (0xFUL << JPEG_CONFR7_VSF_Pos)         /*!< 0x00000F00 */
+#define JPEG_CONFR7_VSF                 JPEG_CONFR7_VSF_Msk                    /*!<Vertical sampling factor for component 2 */
+#define JPEG_CONFR7_VSF_0               (0x1UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000100 */
+#define JPEG_CONFR7_VSF_1               (0x2UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000200 */
+#define JPEG_CONFR7_VSF_2               (0x4UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000400 */
+#define JPEG_CONFR7_VSF_3               (0x8UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000800 */
+#define JPEG_CONFR7_HSF_Pos             (12U)
+#define JPEG_CONFR7_HSF_Msk             (0xFUL << JPEG_CONFR7_HSF_Pos)         /*!< 0x0000F000 */
+#define JPEG_CONFR7_HSF                 JPEG_CONFR7_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */
+#define JPEG_CONFR7_HSF_0               (0x1UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00001000 */
+#define JPEG_CONFR7_HSF_1               (0x2UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00002000 */
+#define JPEG_CONFR7_HSF_2               (0x4UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00004000 */
+#define JPEG_CONFR7_HSF_3               (0x8UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00008000 */
+
+/********************  Bit definition for CR register  ********************/
+#define JPEG_CR_JCEN_Pos                (0U)
+#define JPEG_CR_JCEN_Msk                (0x1UL << JPEG_CR_JCEN_Pos)            /*!< 0x00000001 */
+#define JPEG_CR_JCEN                    JPEG_CR_JCEN_Msk                       /*!<Enable the JPEG Codec Core */
+#define JPEG_CR_IFTIE_Pos               (1U)
+#define JPEG_CR_IFTIE_Msk               (0x1UL << JPEG_CR_IFTIE_Pos)           /*!< 0x00000002 */
+#define JPEG_CR_IFTIE                   JPEG_CR_IFTIE_Msk                      /*!<Input FIFO Threshold Interrupt Enable */
+#define JPEG_CR_IFNFIE_Pos              (2U)
+#define JPEG_CR_IFNFIE_Msk              (0x1UL << JPEG_CR_IFNFIE_Pos)          /*!< 0x00000004 */
+#define JPEG_CR_IFNFIE                  JPEG_CR_IFNFIE_Msk                     /*!<Input FIFO Not Full Interrupt Enable */
+#define JPEG_CR_OFTIE_Pos               (3U)
+#define JPEG_CR_OFTIE_Msk               (0x1UL << JPEG_CR_OFTIE_Pos)           /*!< 0x00000008 */
+#define JPEG_CR_OFTIE                   JPEG_CR_OFTIE_Msk                      /*!<Output FIFO Threshold Interrupt Enable */
+#define JPEG_CR_OFNEIE_Pos              (4U)
+#define JPEG_CR_OFNEIE_Msk              (0x1UL << JPEG_CR_OFNEIE_Pos)          /*!< 0x00000010 */
+#define JPEG_CR_OFNEIE                  JPEG_CR_OFNEIE_Msk                     /*!<Output FIFO Not Empty Interrupt Enable */
+#define JPEG_CR_EOCIE_Pos               (5U)
+#define JPEG_CR_EOCIE_Msk               (0x1UL << JPEG_CR_EOCIE_Pos)           /*!< 0x00000020 */
+#define JPEG_CR_EOCIE                   JPEG_CR_EOCIE_Msk                      /*!<End of Conversion Interrupt Enable */
+#define JPEG_CR_HPDIE_Pos               (6U)
+#define JPEG_CR_HPDIE_Msk               (0x1UL << JPEG_CR_HPDIE_Pos)           /*!< 0x00000040 */
+#define JPEG_CR_HPDIE                   JPEG_CR_HPDIE_Msk                      /*!<Header Parsing Done Interrupt Enable */
+#define JPEG_CR_IFF_Pos                 (13U)
+#define JPEG_CR_IFF_Msk                 (0x1UL << JPEG_CR_IFF_Pos)             /*!< 0x00002000 */
+#define JPEG_CR_IFF                     JPEG_CR_IFF_Msk                        /*!<Flush the input FIFO */
+#define JPEG_CR_OFF_Pos                 (14U)
+#define JPEG_CR_OFF_Msk                 (0x1UL << JPEG_CR_OFF_Pos)             /*!< 0x00004000 */
+#define JPEG_CR_OFF                     JPEG_CR_OFF_Msk                        /*!<Flush the output FIFO */
+
+/********************  Bit definition for SR register  ********************/
+#define JPEG_SR_IFTF_Pos                (1U)
+#define JPEG_SR_IFTF_Msk                (0x1UL << JPEG_SR_IFTF_Pos)            /*!< 0x00000002 */
+#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is bellow its threshold flag */
+#define JPEG_SR_IFNFF_Pos               (2U)
+#define JPEG_SR_IFNFF_Msk               (0x1UL << JPEG_SR_IFNFF_Pos)           /*!< 0x00000004 */
+#define JPEG_SR_IFNFF                   JPEG_SR_IFNFF_Msk                      /*!<Input FIFO Not Full Flag, a data can be written */
+#define JPEG_SR_OFTF_Pos                (3U)
+#define JPEG_SR_OFTF_Msk                (0x1UL << JPEG_SR_OFTF_Pos)            /*!< 0x00000008 */
+#define JPEG_SR_OFTF                    JPEG_SR_OFTF_Msk                       /*!<Output FIFO is not empty and has reach its threshold */
+#define JPEG_SR_OFNEF_Pos               (4U)
+#define JPEG_SR_OFNEF_Msk               (0x1UL << JPEG_SR_OFNEF_Pos)           /*!< 0x00000010 */
+#define JPEG_SR_OFNEF                   JPEG_SR_OFNEF_Msk                      /*!<Output FIFO is not empty, a data is available */
+#define JPEG_SR_EOCF_Pos                (5U)
+#define JPEG_SR_EOCF_Msk                (0x1UL << JPEG_SR_EOCF_Pos)            /*!< 0x00000020 */
+#define JPEG_SR_EOCF                    JPEG_SR_EOCF_Msk                       /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */
+#define JPEG_SR_HPDF_Pos                (6U)
+#define JPEG_SR_HPDF_Msk                (0x1UL << JPEG_SR_HPDF_Pos)            /*!< 0x00000040 */
+#define JPEG_SR_HPDF                    JPEG_SR_HPDF_Msk                       /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */
+#define JPEG_SR_COF_Pos                 (7U)
+#define JPEG_SR_COF_Msk                 (0x1UL << JPEG_SR_COF_Pos)             /*!< 0x00000080 */
+#define JPEG_SR_COF                     JPEG_SR_COF_Msk                        /*!<JPEG Codec operation on going flag */
+
+/********************  Bit definition for CFR register  ********************/
+#define JPEG_CFR_CEOCF_Pos              (4U)
+#define JPEG_CFR_CEOCF_Msk              (0x1UL << JPEG_CFR_CEOCF_Pos)          /*!< 0x00000010 */
+#define JPEG_CFR_CEOCF                  JPEG_CFR_CEOCF_Msk                     /*!<Clear End of Conversion Flag */
+#define JPEG_CFR_CHPDF_Pos              (5U)
+#define JPEG_CFR_CHPDF_Msk              (0x1UL << JPEG_CFR_CHPDF_Pos)          /*!< 0x00000020 */
+#define JPEG_CFR_CHPDF                  JPEG_CFR_CHPDF_Msk                     /*!<Clear Header Parsing Done Flag */
+
+/********************  Bit definition for DIR register  ********************/
+#define JPEG_DIR_DATAIN_Pos             (0U)
+#define JPEG_DIR_DATAIN_Msk             (0xFFFFFFFFUL << JPEG_DIR_DATAIN_Pos)  /*!< 0xFFFFFFFF */
+#define JPEG_DIR_DATAIN                 JPEG_DIR_DATAIN_Msk                    /*!<Data Input FIFO */
+
+/********************  Bit definition for DOR register  ********************/
+#define JPEG_DOR_DATAOUT_Pos            (0U)
+#define JPEG_DOR_DATAOUT_Msk            (0xFFFFFFFFUL << JPEG_DOR_DATAOUT_Pos) /*!< 0xFFFFFFFF */
+#define JPEG_DOR_DATAOUT                JPEG_DOR_DATAOUT_Msk                   /*!<Data Output FIFO */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      LCD-TFT Display Controller (LTDC)                     */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for LTDC_SSCR register  *****************/
+
+#define LTDC_SSCR_VSH_Pos            (0U)
+#define LTDC_SSCR_VSH_Msk            (0x7FFUL << LTDC_SSCR_VSH_Pos)            /*!< 0x000007FF */
+#define LTDC_SSCR_VSH                LTDC_SSCR_VSH_Msk                         /*!< Vertical Synchronization Height  */
+#define LTDC_SSCR_HSW_Pos            (16U)
+#define LTDC_SSCR_HSW_Msk            (0xFFFUL << LTDC_SSCR_HSW_Pos)            /*!< 0x0FFF0000 */
+#define LTDC_SSCR_HSW                LTDC_SSCR_HSW_Msk                         /*!< Horizontal Synchronization Width */
+
+/********************  Bit definition for LTDC_BPCR register  *****************/
+
+#define LTDC_BPCR_AVBP_Pos           (0U)
+#define LTDC_BPCR_AVBP_Msk           (0x7FFUL << LTDC_BPCR_AVBP_Pos)           /*!< 0x000007FF */
+#define LTDC_BPCR_AVBP               LTDC_BPCR_AVBP_Msk                        /*!< Accumulated Vertical Back Porch   */
+#define LTDC_BPCR_AHBP_Pos           (16U)
+#define LTDC_BPCR_AHBP_Msk           (0xFFFUL << LTDC_BPCR_AHBP_Pos)           /*!< 0x0FFF0000 */
+#define LTDC_BPCR_AHBP               LTDC_BPCR_AHBP_Msk                        /*!< Accumulated Horizontal Back Porch */
+
+/********************  Bit definition for LTDC_AWCR register  *****************/
+
+#define LTDC_AWCR_AAH_Pos            (0U)
+#define LTDC_AWCR_AAH_Msk            (0x7FFUL << LTDC_AWCR_AAH_Pos)            /*!< 0x000007FF */
+#define LTDC_AWCR_AAH                LTDC_AWCR_AAH_Msk                         /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAW_Pos            (16U)
+#define LTDC_AWCR_AAW_Msk            (0xFFFUL << LTDC_AWCR_AAW_Pos)            /*!< 0x0FFF0000 */
+#define LTDC_AWCR_AAW                LTDC_AWCR_AAW_Msk                         /*!< Accumulated Active Width */
+
+/********************  Bit definition for LTDC_TWCR register  *****************/
+
+#define LTDC_TWCR_TOTALH_Pos         (0U)
+#define LTDC_TWCR_TOTALH_Msk         (0x7FFUL << LTDC_TWCR_TOTALH_Pos)         /*!< 0x000007FF */
+#define LTDC_TWCR_TOTALH             LTDC_TWCR_TOTALH_Msk                      /*!< Total Heigh */
+#define LTDC_TWCR_TOTALW_Pos         (16U)
+#define LTDC_TWCR_TOTALW_Msk         (0xFFFUL << LTDC_TWCR_TOTALW_Pos)         /*!< 0x0FFF0000 */
+#define LTDC_TWCR_TOTALW             LTDC_TWCR_TOTALW_Msk                      /*!< Total Width */
+
+/********************  Bit definition for LTDC_GCR register  ******************/
+
+#define LTDC_GCR_LTDCEN_Pos          (0U)
+#define LTDC_GCR_LTDCEN_Msk          (0x1UL << LTDC_GCR_LTDCEN_Pos)            /*!< 0x00000001 */
+#define LTDC_GCR_LTDCEN              LTDC_GCR_LTDCEN_Msk                       /*!< LCD-TFT controller enable bit       */
+#define LTDC_GCR_DBW_Pos             (4U)
+#define LTDC_GCR_DBW_Msk             (0x7UL << LTDC_GCR_DBW_Pos)               /*!< 0x00000070 */
+#define LTDC_GCR_DBW                 LTDC_GCR_DBW_Msk                          /*!< Dither Blue Width                   */
+#define LTDC_GCR_DGW_Pos             (8U)
+#define LTDC_GCR_DGW_Msk             (0x7UL << LTDC_GCR_DGW_Pos)               /*!< 0x00000700 */
+#define LTDC_GCR_DGW                 LTDC_GCR_DGW_Msk                          /*!< Dither Green Width                  */
+#define LTDC_GCR_DRW_Pos             (12U)
+#define LTDC_GCR_DRW_Msk             (0x7UL << LTDC_GCR_DRW_Pos)               /*!< 0x00007000 */
+#define LTDC_GCR_DRW                 LTDC_GCR_DRW_Msk                          /*!< Dither Red Width                    */
+#define LTDC_GCR_DEN_Pos             (16U)
+#define LTDC_GCR_DEN_Msk             (0x1UL << LTDC_GCR_DEN_Pos)               /*!< 0x00010000 */
+#define LTDC_GCR_DEN                 LTDC_GCR_DEN_Msk                          /*!< Dither Enable                       */
+#define LTDC_GCR_PCPOL_Pos           (28U)
+#define LTDC_GCR_PCPOL_Msk           (0x1UL << LTDC_GCR_PCPOL_Pos)             /*!< 0x10000000 */
+#define LTDC_GCR_PCPOL               LTDC_GCR_PCPOL_Msk                        /*!< Pixel Clock Polarity                */
+#define LTDC_GCR_DEPOL_Pos           (29U)
+#define LTDC_GCR_DEPOL_Msk           (0x1UL << LTDC_GCR_DEPOL_Pos)             /*!< 0x20000000 */
+#define LTDC_GCR_DEPOL               LTDC_GCR_DEPOL_Msk                        /*!< Data Enable Polarity                */
+#define LTDC_GCR_VSPOL_Pos           (30U)
+#define LTDC_GCR_VSPOL_Msk           (0x1UL << LTDC_GCR_VSPOL_Pos)             /*!< 0x40000000 */
+#define LTDC_GCR_VSPOL               LTDC_GCR_VSPOL_Msk                        /*!< Vertical Synchronization Polarity   */
+#define LTDC_GCR_HSPOL_Pos           (31U)
+#define LTDC_GCR_HSPOL_Msk           (0x1UL << LTDC_GCR_HSPOL_Pos)             /*!< 0x80000000 */
+#define LTDC_GCR_HSPOL               LTDC_GCR_HSPOL_Msk                        /*!< Horizontal Synchronization Polarity */
+
+
+/********************  Bit definition for LTDC_SRCR register  *****************/
+
+#define LTDC_SRCR_IMR_Pos            (0U)
+#define LTDC_SRCR_IMR_Msk            (0x1UL << LTDC_SRCR_IMR_Pos)              /*!< 0x00000001 */
+#define LTDC_SRCR_IMR                LTDC_SRCR_IMR_Msk                         /*!< Immediate Reload         */
+#define LTDC_SRCR_VBR_Pos            (1U)
+#define LTDC_SRCR_VBR_Msk            (0x1UL << LTDC_SRCR_VBR_Pos)              /*!< 0x00000002 */
+#define LTDC_SRCR_VBR                LTDC_SRCR_VBR_Msk                         /*!< Vertical Blanking Reload */
+
+/********************  Bit definition for LTDC_BCCR register  *****************/
+
+#define LTDC_BCCR_BCBLUE_Pos         (0U)
+#define LTDC_BCCR_BCBLUE_Msk         (0xFFUL << LTDC_BCCR_BCBLUE_Pos)          /*!< 0x000000FF */
+#define LTDC_BCCR_BCBLUE             LTDC_BCCR_BCBLUE_Msk                      /*!< Background Blue value  */
+#define LTDC_BCCR_BCGREEN_Pos        (8U)
+#define LTDC_BCCR_BCGREEN_Msk        (0xFFUL << LTDC_BCCR_BCGREEN_Pos)         /*!< 0x0000FF00 */
+#define LTDC_BCCR_BCGREEN            LTDC_BCCR_BCGREEN_Msk                     /*!< Background Green value */
+#define LTDC_BCCR_BCRED_Pos          (16U)
+#define LTDC_BCCR_BCRED_Msk          (0xFFUL << LTDC_BCCR_BCRED_Pos)           /*!< 0x00FF0000 */
+#define LTDC_BCCR_BCRED              LTDC_BCCR_BCRED_Msk                       /*!< Background Red value   */
+
+/********************  Bit definition for LTDC_IER register  ******************/
+
+#define LTDC_IER_LIE_Pos             (0U)
+#define LTDC_IER_LIE_Msk             (0x1UL << LTDC_IER_LIE_Pos)               /*!< 0x00000001 */
+#define LTDC_IER_LIE                 LTDC_IER_LIE_Msk                          /*!< Line Interrupt Enable            */
+#define LTDC_IER_FUIE_Pos            (1U)
+#define LTDC_IER_FUIE_Msk            (0x1UL << LTDC_IER_FUIE_Pos)              /*!< 0x00000002 */
+#define LTDC_IER_FUIE                LTDC_IER_FUIE_Msk                         /*!< FIFO Underrun Interrupt Enable   */
+#define LTDC_IER_TERRIE_Pos          (2U)
+#define LTDC_IER_TERRIE_Msk          (0x1UL << LTDC_IER_TERRIE_Pos)            /*!< 0x00000004 */
+#define LTDC_IER_TERRIE              LTDC_IER_TERRIE_Msk                       /*!< Transfer Error Interrupt Enable  */
+#define LTDC_IER_RRIE_Pos            (3U)
+#define LTDC_IER_RRIE_Msk            (0x1UL << LTDC_IER_RRIE_Pos)              /*!< 0x00000008 */
+#define LTDC_IER_RRIE                LTDC_IER_RRIE_Msk                         /*!< Register Reload interrupt enable */
+
+/********************  Bit definition for LTDC_ISR register  ******************/
+
+#define LTDC_ISR_LIF_Pos             (0U)
+#define LTDC_ISR_LIF_Msk             (0x1UL << LTDC_ISR_LIF_Pos)               /*!< 0x00000001 */
+#define LTDC_ISR_LIF                 LTDC_ISR_LIF_Msk                          /*!< Line Interrupt Flag */
+#define LTDC_ISR_FUIF_Pos            (1U)
+#define LTDC_ISR_FUIF_Msk            (0x1UL << LTDC_ISR_FUIF_Pos)              /*!< 0x00000002 */
+#define LTDC_ISR_FUIF                LTDC_ISR_FUIF_Msk                         /*!< FIFO Underrun Interrupt Flag */
+#define LTDC_ISR_TERRIF_Pos          (2U)
+#define LTDC_ISR_TERRIF_Msk          (0x1UL << LTDC_ISR_TERRIF_Pos)            /*!< 0x00000004 */
+#define LTDC_ISR_TERRIF              LTDC_ISR_TERRIF_Msk                       /*!< Transfer Error Interrupt Flag */
+#define LTDC_ISR_RRIF_Pos            (3U)
+#define LTDC_ISR_RRIF_Msk            (0x1UL << LTDC_ISR_RRIF_Pos)              /*!< 0x00000008 */
+#define LTDC_ISR_RRIF                LTDC_ISR_RRIF_Msk                         /*!< Register Reload interrupt Flag */
+
+/********************  Bit definition for LTDC_ICR register  ******************/
+
+#define LTDC_ICR_CLIF_Pos            (0U)
+#define LTDC_ICR_CLIF_Msk            (0x1UL << LTDC_ICR_CLIF_Pos)              /*!< 0x00000001 */
+#define LTDC_ICR_CLIF                LTDC_ICR_CLIF_Msk                         /*!< Clears the Line Interrupt Flag */
+#define LTDC_ICR_CFUIF_Pos           (1U)
+#define LTDC_ICR_CFUIF_Msk           (0x1UL << LTDC_ICR_CFUIF_Pos)             /*!< 0x00000002 */
+#define LTDC_ICR_CFUIF               LTDC_ICR_CFUIF_Msk                        /*!< Clears the FIFO Underrun Interrupt Flag */
+#define LTDC_ICR_CTERRIF_Pos         (2U)
+#define LTDC_ICR_CTERRIF_Msk         (0x1UL << LTDC_ICR_CTERRIF_Pos)           /*!< 0x00000004 */
+#define LTDC_ICR_CTERRIF             LTDC_ICR_CTERRIF_Msk                      /*!< Clears the Transfer Error Interrupt Flag */
+#define LTDC_ICR_CRRIF_Pos           (3U)
+#define LTDC_ICR_CRRIF_Msk           (0x1UL << LTDC_ICR_CRRIF_Pos)             /*!< 0x00000008 */
+#define LTDC_ICR_CRRIF               LTDC_ICR_CRRIF_Msk                        /*!< Clears Register Reload interrupt Flag */
+
+/********************  Bit definition for LTDC_LIPCR register  ****************/
+
+#define LTDC_LIPCR_LIPOS_Pos         (0U)
+#define LTDC_LIPCR_LIPOS_Msk         (0x7FFUL << LTDC_LIPCR_LIPOS_Pos)         /*!< 0x000007FF */
+#define LTDC_LIPCR_LIPOS             LTDC_LIPCR_LIPOS_Msk                      /*!< Line Interrupt Position */
+
+/********************  Bit definition for LTDC_CPSR register  *****************/
+
+#define LTDC_CPSR_CYPOS_Pos          (0U)
+#define LTDC_CPSR_CYPOS_Msk          (0xFFFFUL << LTDC_CPSR_CYPOS_Pos)         /*!< 0x0000FFFF */
+#define LTDC_CPSR_CYPOS              LTDC_CPSR_CYPOS_Msk                       /*!< Current Y Position */
+#define LTDC_CPSR_CXPOS_Pos          (16U)
+#define LTDC_CPSR_CXPOS_Msk          (0xFFFFUL << LTDC_CPSR_CXPOS_Pos)         /*!< 0xFFFF0000 */
+#define LTDC_CPSR_CXPOS              LTDC_CPSR_CXPOS_Msk                       /*!< Current X Position */
+
+/********************  Bit definition for LTDC_CDSR register  *****************/
+
+#define LTDC_CDSR_VDES_Pos           (0U)
+#define LTDC_CDSR_VDES_Msk           (0x1UL << LTDC_CDSR_VDES_Pos)             /*!< 0x00000001 */
+#define LTDC_CDSR_VDES               LTDC_CDSR_VDES_Msk                        /*!< Vertical Data Enable Status       */
+#define LTDC_CDSR_HDES_Pos           (1U)
+#define LTDC_CDSR_HDES_Msk           (0x1UL << LTDC_CDSR_HDES_Pos)             /*!< 0x00000002 */
+#define LTDC_CDSR_HDES               LTDC_CDSR_HDES_Msk                        /*!< Horizontal Data Enable Status     */
+#define LTDC_CDSR_VSYNCS_Pos         (2U)
+#define LTDC_CDSR_VSYNCS_Msk         (0x1UL << LTDC_CDSR_VSYNCS_Pos)           /*!< 0x00000004 */
+#define LTDC_CDSR_VSYNCS             LTDC_CDSR_VSYNCS_Msk                      /*!< Vertical Synchronization Status   */
+#define LTDC_CDSR_HSYNCS_Pos         (3U)
+#define LTDC_CDSR_HSYNCS_Msk         (0x1UL << LTDC_CDSR_HSYNCS_Pos)           /*!< 0x00000008 */
+#define LTDC_CDSR_HSYNCS             LTDC_CDSR_HSYNCS_Msk                      /*!< Horizontal Synchronization Status */
+
+/********************  Bit definition for LTDC_LxCR register  *****************/
+
+#define LTDC_LxCR_LEN_Pos            (0U)
+#define LTDC_LxCR_LEN_Msk            (0x1UL << LTDC_LxCR_LEN_Pos)              /*!< 0x00000001 */
+#define LTDC_LxCR_LEN                LTDC_LxCR_LEN_Msk                         /*!< Layer Enable              */
+#define LTDC_LxCR_COLKEN_Pos         (1U)
+#define LTDC_LxCR_COLKEN_Msk         (0x1UL << LTDC_LxCR_COLKEN_Pos)           /*!< 0x00000002 */
+#define LTDC_LxCR_COLKEN             LTDC_LxCR_COLKEN_Msk                      /*!< Color Keying Enable       */
+#define LTDC_LxCR_CLUTEN_Pos         (4U)
+#define LTDC_LxCR_CLUTEN_Msk         (0x1UL << LTDC_LxCR_CLUTEN_Pos)           /*!< 0x00000010 */
+#define LTDC_LxCR_CLUTEN             LTDC_LxCR_CLUTEN_Msk                      /*!< Color Lockup Table Enable */
+
+/********************  Bit definition for LTDC_LxWHPCR register  **************/
+
+#define LTDC_LxWHPCR_WHSTPOS_Pos     (0U)
+#define LTDC_LxWHPCR_WHSTPOS_Msk     (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos)     /*!< 0x00000FFF */
+#define LTDC_LxWHPCR_WHSTPOS         LTDC_LxWHPCR_WHSTPOS_Msk                  /*!< Window Horizontal Start Position */
+#define LTDC_LxWHPCR_WHSPPOS_Pos     (16U)
+#define LTDC_LxWHPCR_WHSPPOS_Msk     (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos)    /*!< 0xFFFF0000 */
+#define LTDC_LxWHPCR_WHSPPOS         LTDC_LxWHPCR_WHSPPOS_Msk                  /*!< Window Horizontal Stop Position  */
+
+/********************  Bit definition for LTDC_LxWVPCR register  **************/
+
+#define LTDC_LxWVPCR_WVSTPOS_Pos     (0U)
+#define LTDC_LxWVPCR_WVSTPOS_Msk     (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos)     /*!< 0x00000FFF */
+#define LTDC_LxWVPCR_WVSTPOS         LTDC_LxWVPCR_WVSTPOS_Msk                  /*!< Window Vertical Start Position */
+#define LTDC_LxWVPCR_WVSPPOS_Pos     (16U)
+#define LTDC_LxWVPCR_WVSPPOS_Msk     (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos)    /*!< 0xFFFF0000 */
+#define LTDC_LxWVPCR_WVSPPOS         LTDC_LxWVPCR_WVSPPOS_Msk                  /*!< Window Vertical Stop Position  */
+
+/********************  Bit definition for LTDC_LxCKCR register  ***************/
+
+#define LTDC_LxCKCR_CKBLUE_Pos       (0U)
+#define LTDC_LxCKCR_CKBLUE_Msk       (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos)        /*!< 0x000000FF */
+#define LTDC_LxCKCR_CKBLUE           LTDC_LxCKCR_CKBLUE_Msk                    /*!< Color Key Blue value  */
+#define LTDC_LxCKCR_CKGREEN_Pos      (8U)
+#define LTDC_LxCKCR_CKGREEN_Msk      (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos)       /*!< 0x0000FF00 */
+#define LTDC_LxCKCR_CKGREEN          LTDC_LxCKCR_CKGREEN_Msk                   /*!< Color Key Green value */
+#define LTDC_LxCKCR_CKRED_Pos        (16U)
+#define LTDC_LxCKCR_CKRED_Msk        (0xFFUL << LTDC_LxCKCR_CKRED_Pos)         /*!< 0x00FF0000 */
+#define LTDC_LxCKCR_CKRED            LTDC_LxCKCR_CKRED_Msk                     /*!< Color Key Red value   */
+
+/********************  Bit definition for LTDC_LxPFCR register  ***************/
+
+#define LTDC_LxPFCR_PF_Pos           (0U)
+#define LTDC_LxPFCR_PF_Msk           (0x7UL << LTDC_LxPFCR_PF_Pos)             /*!< 0x00000007 */
+#define LTDC_LxPFCR_PF               LTDC_LxPFCR_PF_Msk                        /*!< Pixel Format */
+
+/********************  Bit definition for LTDC_LxCACR register  ***************/
+
+#define LTDC_LxCACR_CONSTA_Pos       (0U)
+#define LTDC_LxCACR_CONSTA_Msk       (0xFFUL << LTDC_LxCACR_CONSTA_Pos)        /*!< 0x000000FF */
+#define LTDC_LxCACR_CONSTA           LTDC_LxCACR_CONSTA_Msk                    /*!< Constant Alpha */
+
+/********************  Bit definition for LTDC_LxDCCR register  ***************/
+
+#define LTDC_LxDCCR_DCBLUE_Pos       (0U)
+#define LTDC_LxDCCR_DCBLUE_Msk       (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos)        /*!< 0x000000FF */
+#define LTDC_LxDCCR_DCBLUE           LTDC_LxDCCR_DCBLUE_Msk                    /*!< Default Color Blue  */
+#define LTDC_LxDCCR_DCGREEN_Pos      (8U)
+#define LTDC_LxDCCR_DCGREEN_Msk      (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos)       /*!< 0x0000FF00 */
+#define LTDC_LxDCCR_DCGREEN          LTDC_LxDCCR_DCGREEN_Msk                   /*!< Default Color Green */
+#define LTDC_LxDCCR_DCRED_Pos        (16U)
+#define LTDC_LxDCCR_DCRED_Msk        (0xFFUL << LTDC_LxDCCR_DCRED_Pos)         /*!< 0x00FF0000 */
+#define LTDC_LxDCCR_DCRED            LTDC_LxDCCR_DCRED_Msk                     /*!< Default Color Red   */
+#define LTDC_LxDCCR_DCALPHA_Pos      (24U)
+#define LTDC_LxDCCR_DCALPHA_Msk      (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos)       /*!< 0xFF000000 */
+#define LTDC_LxDCCR_DCALPHA          LTDC_LxDCCR_DCALPHA_Msk                   /*!< Default Color Alpha */
+
+/********************  Bit definition for LTDC_LxBFCR register  ***************/
+
+#define LTDC_LxBFCR_BF2_Pos          (0U)
+#define LTDC_LxBFCR_BF2_Msk          (0x7UL << LTDC_LxBFCR_BF2_Pos)            /*!< 0x00000007 */
+#define LTDC_LxBFCR_BF2              LTDC_LxBFCR_BF2_Msk                       /*!< Blending Factor 2 */
+#define LTDC_LxBFCR_BF1_Pos          (8U)
+#define LTDC_LxBFCR_BF1_Msk          (0x7UL << LTDC_LxBFCR_BF1_Pos)            /*!< 0x00000700 */
+#define LTDC_LxBFCR_BF1              LTDC_LxBFCR_BF1_Msk                       /*!< Blending Factor 1 */
+
+/********************  Bit definition for LTDC_LxCFBAR register  **************/
+
+#define LTDC_LxCFBAR_CFBADD_Pos      (0U)
+#define LTDC_LxCFBAR_CFBADD_Msk      (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */
+#define LTDC_LxCFBAR_CFBADD          LTDC_LxCFBAR_CFBADD_Msk                   /*!< Color Frame Buffer Start Address */
+
+/********************  Bit definition for LTDC_LxCFBLR register  **************/
+
+#define LTDC_LxCFBLR_CFBLL_Pos       (0U)
+#define LTDC_LxCFBLR_CFBLL_Msk       (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos)      /*!< 0x00001FFF */
+#define LTDC_LxCFBLR_CFBLL           LTDC_LxCFBLR_CFBLL_Msk                    /*!< Color Frame Buffer Line Length    */
+#define LTDC_LxCFBLR_CFBP_Pos        (16U)
+#define LTDC_LxCFBLR_CFBP_Msk        (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos)       /*!< 0x1FFF0000 */
+#define LTDC_LxCFBLR_CFBP            LTDC_LxCFBLR_CFBP_Msk                     /*!< Color Frame Buffer Pitch in bytes */
+
+/********************  Bit definition for LTDC_LxCFBLNR register  *************/
+
+#define LTDC_LxCFBLNR_CFBLNBR_Pos    (0U)
+#define LTDC_LxCFBLNR_CFBLNBR_Msk    (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos)    /*!< 0x000007FF */
+#define LTDC_LxCFBLNR_CFBLNBR        LTDC_LxCFBLNR_CFBLNBR_Msk                 /*!< Frame Buffer Line Number */
+
+/********************  Bit definition for LTDC_LxCLUTWR register  *************/
+
+#define LTDC_LxCLUTWR_BLUE_Pos       (0U)
+#define LTDC_LxCLUTWR_BLUE_Msk       (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos)        /*!< 0x000000FF */
+#define LTDC_LxCLUTWR_BLUE           LTDC_LxCLUTWR_BLUE_Msk                    /*!< Blue value   */
+#define LTDC_LxCLUTWR_GREEN_Pos      (8U)
+#define LTDC_LxCLUTWR_GREEN_Msk      (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos)       /*!< 0x0000FF00 */
+#define LTDC_LxCLUTWR_GREEN          LTDC_LxCLUTWR_GREEN_Msk                   /*!< Green value  */
+#define LTDC_LxCLUTWR_RED_Pos        (16U)
+#define LTDC_LxCLUTWR_RED_Msk        (0xFFUL << LTDC_LxCLUTWR_RED_Pos)         /*!< 0x00FF0000 */
+#define LTDC_LxCLUTWR_RED            LTDC_LxCLUTWR_RED_Msk                     /*!< Red value    */
+#define LTDC_LxCLUTWR_CLUTADD_Pos    (24U)
+#define LTDC_LxCLUTWR_CLUTADD_Msk    (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos)     /*!< 0xFF000000 */
+#define LTDC_LxCLUTWR_CLUTADD        LTDC_LxCLUTWR_CLUTADD_Msk                 /*!< CLUT address */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                     MDMA                                   */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for MDMA_GISR0 register  ****************/
+#define MDMA_GISR0_GIF0_Pos       (0U)
+#define MDMA_GISR0_GIF0_Msk       (0x1UL << MDMA_GISR0_GIF0_Pos)               /*!< 0x00000001 */
+#define MDMA_GISR0_GIF0           MDMA_GISR0_GIF0_Msk                          /*!< Channel 0 global interrupt flag */
+#define MDMA_GISR0_GIF1_Pos       (1U)
+#define MDMA_GISR0_GIF1_Msk       (0x1UL << MDMA_GISR0_GIF1_Pos)               /*!< 0x00000002 */
+#define MDMA_GISR0_GIF1           MDMA_GISR0_GIF1_Msk                          /*!< Channel 1 global interrupt flag */
+#define MDMA_GISR0_GIF2_Pos       (2U)
+#define MDMA_GISR0_GIF2_Msk       (0x1UL << MDMA_GISR0_GIF2_Pos)               /*!< 0x00000004 */
+#define MDMA_GISR0_GIF2           MDMA_GISR0_GIF2_Msk                          /*!< Channel 2 global interrupt flag */
+#define MDMA_GISR0_GIF3_Pos       (3U)
+#define MDMA_GISR0_GIF3_Msk       (0x1UL << MDMA_GISR0_GIF3_Pos)               /*!< 0x00000008 */
+#define MDMA_GISR0_GIF3           MDMA_GISR0_GIF3_Msk                          /*!< Channel 3 global interrupt flag */
+#define MDMA_GISR0_GIF4_Pos       (4U)
+#define MDMA_GISR0_GIF4_Msk       (0x1UL << MDMA_GISR0_GIF4_Pos)               /*!< 0x00000010 */
+#define MDMA_GISR0_GIF4           MDMA_GISR0_GIF4_Msk                          /*!< Channel 4 global interrupt flag */
+#define MDMA_GISR0_GIF5_Pos       (5U)
+#define MDMA_GISR0_GIF5_Msk       (0x1UL << MDMA_GISR0_GIF5_Pos)               /*!< 0x00000020 */
+#define MDMA_GISR0_GIF5           MDMA_GISR0_GIF5_Msk                          /*!< Channel 5 global interrupt flag */
+#define MDMA_GISR0_GIF6_Pos       (6U)
+#define MDMA_GISR0_GIF6_Msk       (0x1UL << MDMA_GISR0_GIF6_Pos)               /*!< 0x00000040 */
+#define MDMA_GISR0_GIF6           MDMA_GISR0_GIF6_Msk                          /*!< Channel 6 global interrupt flag */
+#define MDMA_GISR0_GIF7_Pos       (7U)
+#define MDMA_GISR0_GIF7_Msk       (0x1UL << MDMA_GISR0_GIF7_Pos)               /*!< 0x00000080 */
+#define MDMA_GISR0_GIF7           MDMA_GISR0_GIF7_Msk                          /*!< Channel 7 global interrupt flag */
+#define MDMA_GISR0_GIF8_Pos       (8U)
+#define MDMA_GISR0_GIF8_Msk       (0x1UL << MDMA_GISR0_GIF8_Pos)               /*!< 0x00000100 */
+#define MDMA_GISR0_GIF8           MDMA_GISR0_GIF8_Msk                          /*!< Channel 8 global interrupt flag */
+#define MDMA_GISR0_GIF9_Pos       (9U)
+#define MDMA_GISR0_GIF9_Msk       (0x1UL << MDMA_GISR0_GIF9_Pos)               /*!< 0x00000200 */
+#define MDMA_GISR0_GIF9           MDMA_GISR0_GIF9_Msk                          /*!< Channel 9 global interrupt flag */
+#define MDMA_GISR0_GIF10_Pos      (10U)
+#define MDMA_GISR0_GIF10_Msk      (0x1UL << MDMA_GISR0_GIF10_Pos)              /*!< 0x00000400 */
+#define MDMA_GISR0_GIF10          MDMA_GISR0_GIF10_Msk                         /*!< Channel 10 global interrupt flag */
+#define MDMA_GISR0_GIF11_Pos      (11U)
+#define MDMA_GISR0_GIF11_Msk      (0x1UL << MDMA_GISR0_GIF11_Pos)              /*!< 0x00000800 */
+#define MDMA_GISR0_GIF11          MDMA_GISR0_GIF11_Msk                         /*!< Channel 11 global interrupt flag */
+#define MDMA_GISR0_GIF12_Pos      (12U)
+#define MDMA_GISR0_GIF12_Msk      (0x1UL << MDMA_GISR0_GIF12_Pos)              /*!< 0x00001000 */
+#define MDMA_GISR0_GIF12          MDMA_GISR0_GIF12_Msk                         /*!< Channel 12 global interrupt flag */
+#define MDMA_GISR0_GIF13_Pos      (13U)
+#define MDMA_GISR0_GIF13_Msk      (0x1UL << MDMA_GISR0_GIF13_Pos)              /*!< 0x00002000 */
+#define MDMA_GISR0_GIF13          MDMA_GISR0_GIF13_Msk                         /*!< Channel 13 global interrupt flag */
+#define MDMA_GISR0_GIF14_Pos      (14U)
+#define MDMA_GISR0_GIF14_Msk      (0x1UL << MDMA_GISR0_GIF14_Pos)              /*!< 0x00004000 */
+#define MDMA_GISR0_GIF14          MDMA_GISR0_GIF14_Msk                         /*!< Channel 14 global interrupt flag */
+#define MDMA_GISR0_GIF15_Pos      (15U)
+#define MDMA_GISR0_GIF15_Msk      (0x1UL << MDMA_GISR0_GIF15_Pos)              /*!< 0x00008000 */
+#define MDMA_GISR0_GIF15          MDMA_GISR0_GIF15_Msk                         /*!< Channel 15 global interrupt flag */
+
+/********************  Bit definition for MDMA_CxISR register  ****************/
+#define MDMA_CISR_TEIF_Pos        (0U)
+#define MDMA_CISR_TEIF_Msk        (0x1UL << MDMA_CISR_TEIF_Pos)                /*!< 0x00000001 */
+#define MDMA_CISR_TEIF            MDMA_CISR_TEIF_Msk                           /*!< Channel x transfer error interrupt flag */
+#define MDMA_CISR_CTCIF_Pos       (1U)
+#define MDMA_CISR_CTCIF_Msk       (0x1UL << MDMA_CISR_CTCIF_Pos)               /*!< 0x00000002 */
+#define MDMA_CISR_CTCIF           MDMA_CISR_CTCIF_Msk                          /*!< Channel x Channel Transfer Complete interrupt flag */
+#define MDMA_CISR_BRTIF_Pos       (2U)
+#define MDMA_CISR_BRTIF_Msk       (0x1UL << MDMA_CISR_BRTIF_Pos)               /*!< 0x00000004 */
+#define MDMA_CISR_BRTIF           MDMA_CISR_BRTIF_Msk                          /*!< Channel x block repeat transfer complete interrupt flag */
+#define MDMA_CISR_BTIF_Pos        (3U)
+#define MDMA_CISR_BTIF_Msk        (0x1UL << MDMA_CISR_BTIF_Pos)                /*!< 0x00000008 */
+#define MDMA_CISR_BTIF            MDMA_CISR_BTIF_Msk                           /*!< Channel x block transfer complete interrupt flag */
+#define MDMA_CISR_TCIF_Pos        (4U)
+#define MDMA_CISR_TCIF_Msk        (0x1UL << MDMA_CISR_TCIF_Pos)                /*!< 0x00000010 */
+#define MDMA_CISR_TCIF            MDMA_CISR_TCIF_Msk                           /*!< Channel x buffer transfer complete interrupt flag */
+#define MDMA_CISR_CRQA_Pos        (16U)
+#define MDMA_CISR_CRQA_Msk        (0x1UL << MDMA_CISR_CRQA_Pos)                /*!< 0x00010000 */
+#define MDMA_CISR_CRQA            MDMA_CISR_CRQA_Msk                           /*!< Channel x ReQest Active flag */
+
+/********************  Bit definition for MDMA_CxIFCR register  ****************/
+#define MDMA_CIFCR_CTEIF_Pos      (0U)
+#define MDMA_CIFCR_CTEIF_Msk      (0x1UL << MDMA_CIFCR_CTEIF_Pos)              /*!< 0x00000001 */
+#define MDMA_CIFCR_CTEIF          MDMA_CIFCR_CTEIF_Msk                         /*!< Channel x clear transfer error interrupt flag */
+#define MDMA_CIFCR_CCTCIF_Pos     (1U)
+#define MDMA_CIFCR_CCTCIF_Msk     (0x1UL << MDMA_CIFCR_CCTCIF_Pos)             /*!< 0x00000002 */
+#define MDMA_CIFCR_CCTCIF         MDMA_CIFCR_CCTCIF_Msk                        /*!< Clear Channel transfer complete interrupt flag for channel x */
+#define MDMA_CIFCR_CBRTIF_Pos     (2U)
+#define MDMA_CIFCR_CBRTIF_Msk     (0x1UL << MDMA_CIFCR_CBRTIF_Pos)             /*!< 0x00000004 */
+#define MDMA_CIFCR_CBRTIF         MDMA_CIFCR_CBRTIF_Msk                        /*!< Channel x clear block repeat transfer complete interrupt flag */
+#define MDMA_CIFCR_CBTIF_Pos      (3U)
+#define MDMA_CIFCR_CBTIF_Msk      (0x1UL << MDMA_CIFCR_CBTIF_Pos)              /*!< 0x00000008 */
+#define MDMA_CIFCR_CBTIF          MDMA_CIFCR_CBTIF_Msk                         /*!< Channel x Clear block transfer complete interrupt flag */
+#define MDMA_CIFCR_CLTCIF_Pos     (4U)
+#define MDMA_CIFCR_CLTCIF_Msk     (0x1UL << MDMA_CIFCR_CLTCIF_Pos)             /*!< 0x00000010 */
+#define MDMA_CIFCR_CLTCIF         MDMA_CIFCR_CLTCIF_Msk                        /*!< CLear Transfer buffer Complete Interrupt Flag for channel */
+
+/********************  Bit definition for MDMA_CxESR register  ****************/
+#define MDMA_CESR_TEA_Pos         (0U)
+#define MDMA_CESR_TEA_Msk         (0x7FUL << MDMA_CESR_TEA_Pos)                /*!< 0x0000007F */
+#define MDMA_CESR_TEA             MDMA_CESR_TEA_Msk                            /*!< Transfer Error Address */
+#define MDMA_CESR_TED_Pos         (7U)
+#define MDMA_CESR_TED_Msk         (0x1UL << MDMA_CESR_TED_Pos)                 /*!< 0x00000080 */
+#define MDMA_CESR_TED             MDMA_CESR_TED_Msk                            /*!< Transfer Error Direction */
+#define MDMA_CESR_TELD_Pos        (8U)
+#define MDMA_CESR_TELD_Msk        (0x1UL << MDMA_CESR_TELD_Pos)                /*!< 0x00000100 */
+#define MDMA_CESR_TELD            MDMA_CESR_TELD_Msk                           /*!< Transfer Error Link Data */
+#define MDMA_CESR_TEMD_Pos        (9U)
+#define MDMA_CESR_TEMD_Msk        (0x1UL << MDMA_CESR_TEMD_Pos)                /*!< 0x00000200 */
+#define MDMA_CESR_TEMD            MDMA_CESR_TEMD_Msk                           /*!< Transfer Error Mask Data */
+#define MDMA_CESR_ASE_Pos         (10U)
+#define MDMA_CESR_ASE_Msk         (0x1UL << MDMA_CESR_ASE_Pos)                 /*!< 0x00000400 */
+#define MDMA_CESR_ASE             MDMA_CESR_ASE_Msk                            /*!< Address/Size Error       */
+#define MDMA_CESR_BSE_Pos         (11U)
+#define MDMA_CESR_BSE_Msk         (0x1UL << MDMA_CESR_BSE_Pos)                 /*!< 0x00000800 */
+#define MDMA_CESR_BSE             MDMA_CESR_BSE_Msk                            /*!< Block Size Error         */
+
+/********************  Bit definition for MDMA_CxCR register  ****************/
+#define MDMA_CCR_EN_Pos           (0U)
+#define MDMA_CCR_EN_Msk           (0x1UL << MDMA_CCR_EN_Pos)                   /*!< 0x00000001 */
+#define MDMA_CCR_EN               MDMA_CCR_EN_Msk                              /*!< Channel enable / flag channel ready when read low */
+#define MDMA_CCR_TEIE_Pos         (1U)
+#define MDMA_CCR_TEIE_Msk         (0x1UL << MDMA_CCR_TEIE_Pos)                 /*!< 0x00000002 */
+#define MDMA_CCR_TEIE             MDMA_CCR_TEIE_Msk                            /*!< Transfer error interrupt enable */
+#define MDMA_CCR_CTCIE_Pos        (2U)
+#define MDMA_CCR_CTCIE_Msk        (0x1UL << MDMA_CCR_CTCIE_Pos)                /*!< 0x00000004 */
+#define MDMA_CCR_CTCIE            MDMA_CCR_CTCIE_Msk                           /*!< Channel Transfer Complete interrupt enable */
+#define MDMA_CCR_BRTIE_Pos        (3U)
+#define MDMA_CCR_BRTIE_Msk        (0x1UL << MDMA_CCR_BRTIE_Pos)                /*!< 0x00000008 */
+#define MDMA_CCR_BRTIE            MDMA_CCR_BRTIE_Msk                           /*!< Block Repeat transfer interrupt enable */
+#define MDMA_CCR_BTIE_Pos         (4U)
+#define MDMA_CCR_BTIE_Msk         (0x1UL << MDMA_CCR_BTIE_Pos)                 /*!< 0x00000010 */
+#define MDMA_CCR_BTIE             MDMA_CCR_BTIE_Msk                            /*!< Block Transfer interrupt enable */
+#define MDMA_CCR_TCIE_Pos         (5U)
+#define MDMA_CCR_TCIE_Msk         (0x1UL << MDMA_CCR_TCIE_Pos)                 /*!< 0x00000020 */
+#define MDMA_CCR_TCIE             MDMA_CCR_TCIE_Msk                            /*!< buffer Transfer Complete interrupt enable */
+#define MDMA_CCR_PL_Pos           (6U)
+#define MDMA_CCR_PL_Msk           (0x3UL << MDMA_CCR_PL_Pos)                   /*!< 0x000000C0 */
+#define MDMA_CCR_PL               MDMA_CCR_PL_Msk                              /*!< Priority level */
+#define MDMA_CCR_PL_0             (0x1UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000040 */
+#define MDMA_CCR_PL_1             (0x2UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000080 */
+#define MDMA_CCR_BEX_Pos          (12U)
+#define MDMA_CCR_BEX_Msk          (0x1UL << MDMA_CCR_BEX_Pos)                  /*!< 0x00001000 */
+#define MDMA_CCR_BEX              MDMA_CCR_BEX_Msk                             /*!< Byte Endianess eXchange */
+#define MDMA_CCR_HEX_Pos          (13U)
+#define MDMA_CCR_HEX_Msk          (0x1UL << MDMA_CCR_HEX_Pos)                  /*!< 0x00002000 */
+#define MDMA_CCR_HEX              MDMA_CCR_HEX_Msk                             /*!< Half word Endianess eXchange */
+#define MDMA_CCR_WEX_Pos          (14U)
+#define MDMA_CCR_WEX_Msk          (0x1UL << MDMA_CCR_WEX_Pos)                  /*!< 0x00004000 */
+#define MDMA_CCR_WEX              MDMA_CCR_WEX_Msk                             /*!< Word Endianess eXchange */
+#define MDMA_CCR_SWRQ_Pos         (16U)
+#define MDMA_CCR_SWRQ_Msk         (0x1UL << MDMA_CCR_SWRQ_Pos)                 /*!< 0x00010000 */
+#define MDMA_CCR_SWRQ             MDMA_CCR_SWRQ_Msk                            /*!< SW ReQuest */
+
+/********************  Bit definition for MDMA_CxTCR register  ****************/
+#define MDMA_CTCR_SINC_Pos        (0U)
+#define MDMA_CTCR_SINC_Msk        (0x3UL << MDMA_CTCR_SINC_Pos)                /*!< 0x00000003 */
+#define MDMA_CTCR_SINC            MDMA_CTCR_SINC_Msk                           /*!< Source increment mode */
+#define MDMA_CTCR_SINC_0          (0x1UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000001 */
+#define MDMA_CTCR_SINC_1          (0x2UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000002 */
+#define MDMA_CTCR_DINC_Pos        (2U)
+#define MDMA_CTCR_DINC_Msk        (0x3UL << MDMA_CTCR_DINC_Pos)                /*!< 0x0000000C */
+#define MDMA_CTCR_DINC            MDMA_CTCR_DINC_Msk                           /*!< Source increment mode */
+#define MDMA_CTCR_DINC_0          (0x1UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000004 */
+#define MDMA_CTCR_DINC_1          (0x2UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000008 */
+#define MDMA_CTCR_SSIZE_Pos       (4U)
+#define MDMA_CTCR_SSIZE_Msk       (0x3UL << MDMA_CTCR_SSIZE_Pos)               /*!< 0x00000030 */
+#define MDMA_CTCR_SSIZE           MDMA_CTCR_SSIZE_Msk                          /*!< Source data size */
+#define MDMA_CTCR_SSIZE_0         (0x1UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000010 */
+#define MDMA_CTCR_SSIZE_1         (0x2UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000020 */
+#define MDMA_CTCR_DSIZE_Pos       (6U)
+#define MDMA_CTCR_DSIZE_Msk       (0x3UL << MDMA_CTCR_DSIZE_Pos)               /*!< 0x000000C0 */
+#define MDMA_CTCR_DSIZE           MDMA_CTCR_DSIZE_Msk                          /*!< Destination data size */
+#define MDMA_CTCR_DSIZE_0         (0x1UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000040 */
+#define MDMA_CTCR_DSIZE_1         (0x2UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000080 */
+#define MDMA_CTCR_SINCOS_Pos      (8U)
+#define MDMA_CTCR_SINCOS_Msk      (0x3UL << MDMA_CTCR_SINCOS_Pos)              /*!< 0x00000300 */
+#define MDMA_CTCR_SINCOS          MDMA_CTCR_SINCOS_Msk                         /*!< Source increment offset size */
+#define MDMA_CTCR_SINCOS_0        (0x1UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000100 */
+#define MDMA_CTCR_SINCOS_1        (0x2UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000200 */
+#define MDMA_CTCR_DINCOS_Pos      (10U)
+#define MDMA_CTCR_DINCOS_Msk      (0x3UL << MDMA_CTCR_DINCOS_Pos)              /*!< 0x00000C00 */
+#define MDMA_CTCR_DINCOS          MDMA_CTCR_DINCOS_Msk                         /*!< Destination increment offset size */
+#define MDMA_CTCR_DINCOS_0        (0x1UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000400 */
+#define MDMA_CTCR_DINCOS_1        (0x2UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000800 */
+#define MDMA_CTCR_SBURST_Pos      (12U)
+#define MDMA_CTCR_SBURST_Msk      (0x7UL << MDMA_CTCR_SBURST_Pos)              /*!< 0x00007000 */
+#define MDMA_CTCR_SBURST          MDMA_CTCR_SBURST_Msk                         /*!< Source burst transfer configuration */
+#define MDMA_CTCR_SBURST_0        (0x1UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00001000 */
+#define MDMA_CTCR_SBURST_1        (0x2UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00002000 */
+#define MDMA_CTCR_SBURST_2        (0x4UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00004000 */
+#define MDMA_CTCR_DBURST_Pos      (15U)
+#define MDMA_CTCR_DBURST_Msk      (0x7UL << MDMA_CTCR_DBURST_Pos)              /*!< 0x00038000 */
+#define MDMA_CTCR_DBURST          MDMA_CTCR_DBURST_Msk                         /*!< Destination burst transfer configuration */
+#define MDMA_CTCR_DBURST_0        (0x1UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00008000 */
+#define MDMA_CTCR_DBURST_1        (0x2UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00010000 */
+#define MDMA_CTCR_DBURST_2        (0x4UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00020000 */
+#define MDMA_CTCR_TLEN_Pos        (18U)
+#define MDMA_CTCR_TLEN_Msk        (0x7FUL << MDMA_CTCR_TLEN_Pos)               /*!< 0x01FC0000 */
+#define MDMA_CTCR_TLEN            MDMA_CTCR_TLEN_Msk                           /*!< buffer Transfer Length (number of bytes - 1) */
+#define MDMA_CTCR_PKE_Pos         (25U)
+#define MDMA_CTCR_PKE_Msk         (0x1UL << MDMA_CTCR_PKE_Pos)                 /*!< 0x02000000 */
+#define MDMA_CTCR_PKE             MDMA_CTCR_PKE_Msk                            /*!< PacK Enable */
+#define MDMA_CTCR_PAM_Pos         (26U)
+#define MDMA_CTCR_PAM_Msk         (0x3UL << MDMA_CTCR_PAM_Pos)                 /*!< 0x0C000000 */
+#define MDMA_CTCR_PAM             MDMA_CTCR_PAM_Msk                            /*!< Padding/Alignement Mode */
+#define MDMA_CTCR_PAM_0           (0x1UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x4000000 */
+#define MDMA_CTCR_PAM_1           (0x2UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x8000000 */
+#define MDMA_CTCR_TRGM_Pos        (28U)
+#define MDMA_CTCR_TRGM_Msk        (0x3UL << MDMA_CTCR_TRGM_Pos)                /*!< 0x30000000 */
+#define MDMA_CTCR_TRGM            MDMA_CTCR_TRGM_Msk                           /*!< Trigger Mode */
+#define MDMA_CTCR_TRGM_0          (0x1UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x10000000 */
+#define MDMA_CTCR_TRGM_1          (0x2UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x20000000 */
+#define MDMA_CTCR_SWRM_Pos        (30U)
+#define MDMA_CTCR_SWRM_Msk        (0x1UL << MDMA_CTCR_SWRM_Pos)                /*!< 0x40000000 */
+#define MDMA_CTCR_SWRM            MDMA_CTCR_SWRM_Msk                           /*!< SW Request Mode */
+#define MDMA_CTCR_BWM_Pos         (31U)
+#define MDMA_CTCR_BWM_Msk         (0x1UL << MDMA_CTCR_BWM_Pos)                 /*!< 0x80000000 */
+#define MDMA_CTCR_BWM             MDMA_CTCR_BWM_Msk                            /*!< Bufferable Write Mode */
+
+/********************  Bit definition for MDMA_CxBNDTR register  ****************/
+#define MDMA_CBNDTR_BNDT_Pos      (0U)
+#define MDMA_CBNDTR_BNDT_Msk      (0x1FFFFUL << MDMA_CBNDTR_BNDT_Pos)          /*!< 0x0001FFFF */
+#define MDMA_CBNDTR_BNDT          MDMA_CBNDTR_BNDT_Msk                         /*!< Block Number of data bytes to transfer */
+#define MDMA_CBNDTR_BRSUM_Pos     (18U)
+#define MDMA_CBNDTR_BRSUM_Msk     (0x1UL << MDMA_CBNDTR_BRSUM_Pos)             /*!< 0x00040000 */
+#define MDMA_CBNDTR_BRSUM         MDMA_CBNDTR_BRSUM_Msk                        /*!< Block Repeat Source address Update Mode */
+#define MDMA_CBNDTR_BRDUM_Pos     (19U)
+#define MDMA_CBNDTR_BRDUM_Msk     (0x1UL << MDMA_CBNDTR_BRDUM_Pos)             /*!< 0x00080000 */
+#define MDMA_CBNDTR_BRDUM         MDMA_CBNDTR_BRDUM_Msk                        /*!< Block Repeat Destination address Update Mode */
+#define MDMA_CBNDTR_BRC_Pos       (20U)
+#define MDMA_CBNDTR_BRC_Msk       (0xFFFUL << MDMA_CBNDTR_BRC_Pos)             /*!< 0xFFF00000 */
+#define MDMA_CBNDTR_BRC           MDMA_CBNDTR_BRC_Msk                          /*!< Block Repeat Count */
+
+/********************  Bit definition for MDMA_CxSAR register  ****************/
+#define MDMA_CSAR_SAR_Pos         (0U)
+#define MDMA_CSAR_SAR_Msk         (0xFFFFFFFFUL << MDMA_CSAR_SAR_Pos)          /*!< 0xFFFFFFFF */
+#define MDMA_CSAR_SAR             MDMA_CSAR_SAR_Msk                            /*!< Source address */
+
+/********************  Bit definition for MDMA_CxDAR register  ****************/
+#define MDMA_CDAR_DAR_Pos         (0U)
+#define MDMA_CDAR_DAR_Msk         (0xFFFFFFFFUL << MDMA_CDAR_DAR_Pos)          /*!< 0xFFFFFFFF */
+#define MDMA_CDAR_DAR             MDMA_CDAR_DAR_Msk                            /*!< Destination address */
+
+/********************  Bit definition for MDMA_CxBRUR  ************************/
+#define MDMA_CBRUR_SUV_Pos        (0U)
+#define MDMA_CBRUR_SUV_Msk        (0xFFFFUL << MDMA_CBRUR_SUV_Pos)             /*!< 0x0000FFFF */
+#define MDMA_CBRUR_SUV            MDMA_CBRUR_SUV_Msk                           /*!< Source address Update Value */
+#define MDMA_CBRUR_DUV_Pos        (16U)
+#define MDMA_CBRUR_DUV_Msk        (0xFFFFUL << MDMA_CBRUR_DUV_Pos)             /*!< 0xFFFF0000 */
+#define MDMA_CBRUR_DUV            MDMA_CBRUR_DUV_Msk                           /*!< Destination address Update Value */
+
+/********************  Bit definition for MDMA_CxLAR  *************************/
+#define MDMA_CLAR_LAR_Pos         (0U)
+#define MDMA_CLAR_LAR_Msk         (0xFFFFFFFFUL << MDMA_CLAR_LAR_Pos)          /*!< 0xFFFFFFFF */
+#define MDMA_CLAR_LAR             MDMA_CLAR_LAR_Msk                            /*!< Link Address Register */
+
+/********************  Bit definition for MDMA_CxTBR)  ************************/
+#define MDMA_CTBR_TSEL_Pos        (0U)
+#define MDMA_CTBR_TSEL_Msk        (0xFFUL << MDMA_CTBR_TSEL_Pos)               /*!< 0x000000FF */
+#define MDMA_CTBR_TSEL            MDMA_CTBR_TSEL_Msk                           /*!< Trigger SELection */
+#define MDMA_CTBR_SBUS_Pos        (16U)
+#define MDMA_CTBR_SBUS_Msk        (0x1UL << MDMA_CTBR_SBUS_Pos)                /*!< 0x00010000 */
+#define MDMA_CTBR_SBUS            MDMA_CTBR_SBUS_Msk                           /*!< Source BUS select */
+#define MDMA_CTBR_DBUS_Pos        (17U)
+#define MDMA_CTBR_DBUS_Msk        (0x1UL << MDMA_CTBR_DBUS_Pos)                /*!< 0x00020000 */
+#define MDMA_CTBR_DBUS            MDMA_CTBR_DBUS_Msk                           /*!< Destination BUS select */
+
+/********************  Bit definition for MDMA_CxMAR)  ************************/
+#define MDMA_CMAR_MAR_Pos         (0U)
+#define MDMA_CMAR_MAR_Msk         (0xFFFFFFFFUL << MDMA_CMAR_MAR_Pos)          /*!< 0xFFFFFFFF */
+#define MDMA_CMAR_MAR             MDMA_CMAR_MAR_Msk                            /*!< Mask address */
+
+/********************  Bit definition for MDMA_CxMDR)  ************************/
+#define MDMA_CMDR_MDR_Pos         (0U)
+#define MDMA_CMDR_MDR_Msk         (0xFFFFFFFFUL << MDMA_CMDR_MDR_Pos)          /*!< 0xFFFFFFFF */
+#define MDMA_CMDR_MDR             MDMA_CMDR_MDR_Msk                            /*!< Mask Data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Operational Amplifier (OPAMP)                      */
+/*                                                                            */
+/******************************************************************************/
+/*********************  Bit definition for OPAMPx_CSR register  ***************/
+#define OPAMP_CSR_OPAMPxEN_Pos           (0U)
+#define OPAMP_CSR_OPAMPxEN_Msk           (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)     /*!< 0x00000001 */
+#define OPAMP_CSR_OPAMPxEN               OPAMP_CSR_OPAMPxEN_Msk                /*!< OPAMP enable */
+#define OPAMP_CSR_FORCEVP_Pos            (1U)
+#define OPAMP_CSR_FORCEVP_Msk            (0x1UL << OPAMP_CSR_FORCEVP_Pos)      /*!< 0x00000002 */
+#define OPAMP_CSR_FORCEVP                OPAMP_CSR_FORCEVP_Msk                 /*!< Force internal reference on VP */
+
+#define OPAMP_CSR_VPSEL_Pos              (2U)
+#define OPAMP_CSR_VPSEL_Msk              (0x3UL << OPAMP_CSR_VPSEL_Pos)        /*!< 0x0000000C */
+#define OPAMP_CSR_VPSEL                  OPAMP_CSR_VPSEL_Msk                   /*!< Non inverted input selection */
+#define OPAMP_CSR_VPSEL_0                (0x1UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000004 */
+#define OPAMP_CSR_VPSEL_1                (0x2UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000008 */
+
+#define OPAMP_CSR_VMSEL_Pos              (5U)
+#define OPAMP_CSR_VMSEL_Msk              (0x3UL << OPAMP_CSR_VMSEL_Pos)        /*!< 0x00000060 */
+#define OPAMP_CSR_VMSEL                  OPAMP_CSR_VMSEL_Msk                   /*!< Inverting input selection */
+#define OPAMP_CSR_VMSEL_0                (0x1UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000020 */
+#define OPAMP_CSR_VMSEL_1                (0x2UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000040 */
+
+#define OPAMP_CSR_OPAHSM_Pos             (8U)
+#define OPAMP_CSR_OPAHSM_Msk             (0x1UL << OPAMP_CSR_OPAHSM_Pos)       /*!< 0x00000100 */
+#define OPAMP_CSR_OPAHSM                 OPAMP_CSR_OPAHSM_Msk                  /*!< Operational amplifier high speed mode */
+#define OPAMP_CSR_CALON_Pos              (11U)
+#define OPAMP_CSR_CALON_Msk              (0x1UL << OPAMP_CSR_CALON_Pos)        /*!< 0x00000800 */
+#define OPAMP_CSR_CALON                  OPAMP_CSR_CALON_Msk                   /*!< Calibration mode enable */
+
+#define OPAMP_CSR_CALSEL_Pos             (12U)
+#define OPAMP_CSR_CALSEL_Msk             (0x3UL << OPAMP_CSR_CALSEL_Pos)       /*!< 0x00003000 */
+#define OPAMP_CSR_CALSEL                 OPAMP_CSR_CALSEL_Msk                  /*!< Calibration selection */
+#define OPAMP_CSR_CALSEL_0               (0x1UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00001000 */
+#define OPAMP_CSR_CALSEL_1               (0x2UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00002000 */
+
+#define OPAMP_CSR_PGGAIN_Pos             (14U)
+#define OPAMP_CSR_PGGAIN_Msk             (0xFUL << OPAMP_CSR_PGGAIN_Pos)       /*!< 0x0003C000 */
+#define OPAMP_CSR_PGGAIN                 OPAMP_CSR_PGGAIN_Msk                  /*!< Operational amplifier Programmable amplifier gain value */
+#define OPAMP_CSR_PGGAIN_0               (0x1UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00004000 */
+#define OPAMP_CSR_PGGAIN_1               (0x2UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00008000 */
+#define OPAMP_CSR_PGGAIN_2               (0x4UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00010000 */
+#define OPAMP_CSR_PGGAIN_3               (0x8UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00020000 */
+
+#define OPAMP_CSR_USERTRIM_Pos           (18U)
+#define OPAMP_CSR_USERTRIM_Msk           (0x1UL << OPAMP_CSR_USERTRIM_Pos)     /*!< 0x00040000 */
+#define OPAMP_CSR_USERTRIM               OPAMP_CSR_USERTRIM_Msk                /*!< User trimming enable */
+#define OPAMP_CSR_TSTREF_Pos             (29U)
+#define OPAMP_CSR_TSTREF_Msk             (0x1UL << OPAMP_CSR_TSTREF_Pos)       /*!< 0x20000000 */
+#define OPAMP_CSR_TSTREF                 OPAMP_CSR_TSTREF_Msk                  /*!< OpAmp calibration reference voltage output control */
+#define OPAMP_CSR_CALOUT_Pos             (30U)
+#define OPAMP_CSR_CALOUT_Msk             (0x1UL << OPAMP_CSR_CALOUT_Pos)       /*!< 0x40000000 */
+#define OPAMP_CSR_CALOUT                 OPAMP_CSR_CALOUT_Msk                  /*!< Operational amplifier calibration output */
+
+/*********************  Bit definition for OPAMP1_CSR register  ***************/
+#define OPAMP1_CSR_OPAEN_Pos              (0U)
+#define OPAMP1_CSR_OPAEN_Msk              (0x1UL << OPAMP1_CSR_OPAEN_Pos)      /*!< 0x00000001 */
+#define OPAMP1_CSR_OPAEN                  OPAMP1_CSR_OPAEN_Msk                 /*!< Operational amplifier1 Enable */
+#define OPAMP1_CSR_FORCEVP_Pos            (1U)
+#define OPAMP1_CSR_FORCEVP_Msk            (0x1UL << OPAMP1_CSR_FORCEVP_Pos)    /*!< 0x00000002 */
+#define OPAMP1_CSR_FORCEVP                OPAMP1_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */
+
+#define OPAMP1_CSR_VPSEL_Pos              (2U)
+#define OPAMP1_CSR_VPSEL_Msk              (0x3UL << OPAMP1_CSR_VPSEL_Pos)      /*!< 0x0000000C */
+#define OPAMP1_CSR_VPSEL                  OPAMP1_CSR_VPSEL_Msk                 /*!< Non inverted input selection */
+#define OPAMP1_CSR_VPSEL_0                (0x1UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000004 */
+#define OPAMP1_CSR_VPSEL_1                (0x2UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000008 */
+
+#define OPAMP1_CSR_VMSEL_Pos              (5U)
+#define OPAMP1_CSR_VMSEL_Msk              (0x3UL << OPAMP1_CSR_VMSEL_Pos)      /*!< 0x00000060 */
+#define OPAMP1_CSR_VMSEL                  OPAMP1_CSR_VMSEL_Msk                 /*!< Inverting input selection */
+#define OPAMP1_CSR_VMSEL_0                (0x1UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000020 */
+#define OPAMP1_CSR_VMSEL_1                (0x2UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000040 */
+
+#define OPAMP1_CSR_OPAHSM_Pos             (8U)
+#define OPAMP1_CSR_OPAHSM_Msk             (0x1UL << OPAMP1_CSR_OPAHSM_Pos)     /*!< 0x00000100 */
+#define OPAMP1_CSR_OPAHSM                 OPAMP1_CSR_OPAHSM_Msk                /*!< Operational amplifier1 high speed mode */
+#define OPAMP1_CSR_CALON_Pos              (11U)
+#define OPAMP1_CSR_CALON_Msk              (0x1UL << OPAMP1_CSR_CALON_Pos)      /*!< 0x00000800 */
+#define OPAMP1_CSR_CALON                  OPAMP1_CSR_CALON_Msk                 /*!< Calibration mode enable */
+
+#define OPAMP1_CSR_CALSEL_Pos             (12U)
+#define OPAMP1_CSR_CALSEL_Msk             (0x3UL << OPAMP1_CSR_CALSEL_Pos)     /*!< 0x00003000 */
+#define OPAMP1_CSR_CALSEL                 OPAMP1_CSR_CALSEL_Msk                /*!< Calibration selection */
+#define OPAMP1_CSR_CALSEL_0               (0x1UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00001000 */
+#define OPAMP1_CSR_CALSEL_1               (0x2UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00002000 */
+
+#define OPAMP1_CSR_PGGAIN_Pos             (14U)
+#define OPAMP1_CSR_PGGAIN_Msk             (0xFUL << OPAMP1_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */
+#define OPAMP1_CSR_PGGAIN                 OPAMP1_CSR_PGGAIN_Msk                /*!< Operational amplifier1 Programmable amplifier gain value */
+#define OPAMP1_CSR_PGGAIN_0               (0x1UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00004000 */
+#define OPAMP1_CSR_PGGAIN_1               (0x2UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00008000 */
+#define OPAMP1_CSR_PGGAIN_2               (0x4UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00010000 */
+#define OPAMP1_CSR_PGGAIN_3               (0x8UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00020000 */
+
+#define OPAMP1_CSR_USERTRIM_Pos           (18U)
+#define OPAMP1_CSR_USERTRIM_Msk           (0x1UL << OPAMP1_CSR_USERTRIM_Pos)   /*!< 0x00040000 */
+#define OPAMP1_CSR_USERTRIM               OPAMP1_CSR_USERTRIM_Msk              /*!< User trimming enable */
+#define OPAMP1_CSR_TSTREF_Pos             (29U)
+#define OPAMP1_CSR_TSTREF_Msk             (0x1UL << OPAMP1_CSR_TSTREF_Pos)     /*!< 0x20000000 */
+#define OPAMP1_CSR_TSTREF                 OPAMP1_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */
+#define OPAMP1_CSR_CALOUT_Pos             (30U)
+#define OPAMP1_CSR_CALOUT_Msk             (0x1UL << OPAMP1_CSR_CALOUT_Pos)     /*!< 0x40000000 */
+#define OPAMP1_CSR_CALOUT                 OPAMP1_CSR_CALOUT_Msk                /*!< Operational amplifier1 calibration output */
+
+/*********************  Bit definition for OPAMP2_CSR register  ***************/
+#define OPAMP2_CSR_OPAEN_Pos              (0U)
+#define OPAMP2_CSR_OPAEN_Msk              (0x1UL << OPAMP2_CSR_OPAEN_Pos)      /*!< 0x00000001 */
+#define OPAMP2_CSR_OPAEN                  OPAMP2_CSR_OPAEN_Msk                 /*!< Operational amplifier2 Enable */
+#define OPAMP2_CSR_FORCEVP_Pos            (1U)
+#define OPAMP2_CSR_FORCEVP_Msk            (0x1UL << OPAMP2_CSR_FORCEVP_Pos)    /*!< 0x00000002 */
+#define OPAMP2_CSR_FORCEVP                OPAMP2_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */
+
+#define OPAMP2_CSR_VPSEL_Pos              (2U)
+#define OPAMP2_CSR_VPSEL_Msk              (0x3UL << OPAMP2_CSR_VPSEL_Pos)      /*!< 0x0000000C */
+#define OPAMP2_CSR_VPSEL                  OPAMP2_CSR_VPSEL_Msk                 /*!< Non inverted input selection */
+#define OPAMP2_CSR_VPSEL_0                (0x1UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000004 */
+#define OPAMP2_CSR_VPSEL_1                (0x2UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000008 */
+
+#define OPAMP2_CSR_VMSEL_Pos              (5U)
+#define OPAMP2_CSR_VMSEL_Msk              (0x3UL << OPAMP2_CSR_VMSEL_Pos)      /*!< 0x00000060 */
+#define OPAMP2_CSR_VMSEL                  OPAMP2_CSR_VMSEL_Msk                 /*!< Inverting input selection */
+#define OPAMP2_CSR_VMSEL_0                (0x1UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000020 */
+#define OPAMP2_CSR_VMSEL_1                (0x2UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000040 */
+
+#define OPAMP2_CSR_OPAHSM_Pos             (8U)
+#define OPAMP2_CSR_OPAHSM_Msk             (0x1UL << OPAMP2_CSR_OPAHSM_Pos)     /*!< 0x00000100 */
+#define OPAMP2_CSR_OPAHSM                 OPAMP2_CSR_OPAHSM_Msk                /*!< Operational amplifier2 high speed mode */
+#define OPAMP2_CSR_CALON_Pos              (11U)
+#define OPAMP2_CSR_CALON_Msk              (0x1UL << OPAMP2_CSR_CALON_Pos)      /*!< 0x00000800 */
+#define OPAMP2_CSR_CALON                  OPAMP2_CSR_CALON_Msk                 /*!< Calibration mode enable */
+
+#define OPAMP2_CSR_CALSEL_Pos             (12U)
+#define OPAMP2_CSR_CALSEL_Msk             (0x3UL << OPAMP2_CSR_CALSEL_Pos)     /*!< 0x00003000 */
+#define OPAMP2_CSR_CALSEL                 OPAMP2_CSR_CALSEL_Msk                /*!< Calibration selection */
+#define OPAMP2_CSR_CALSEL_0               (0x1UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00001000 */
+#define OPAMP2_CSR_CALSEL_1               (0x2UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00002000 */
+
+#define OPAMP2_CSR_PGGAIN_Pos             (14U)
+#define OPAMP2_CSR_PGGAIN_Msk             (0xFUL << OPAMP2_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */
+#define OPAMP2_CSR_PGGAIN                 OPAMP2_CSR_PGGAIN_Msk                /*!< Operational amplifier2 Programmable amplifier gain value */
+#define OPAMP2_CSR_PGGAIN_0               (0x1UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00004000 */
+#define OPAMP2_CSR_PGGAIN_1               (0x2UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00008000 */
+#define OPAMP2_CSR_PGGAIN_2               (0x4UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00010000 */
+#define OPAMP2_CSR_PGGAIN_3               (0x8UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00020000 */
+
+#define OPAMP2_CSR_USERTRIM_Pos           (18U)
+#define OPAMP2_CSR_USERTRIM_Msk           (0x1UL << OPAMP2_CSR_USERTRIM_Pos)   /*!< 0x00040000 */
+#define OPAMP2_CSR_USERTRIM               OPAMP2_CSR_USERTRIM_Msk              /*!< User trimming enable */
+#define OPAMP2_CSR_TSTREF_Pos             (29U)
+#define OPAMP2_CSR_TSTREF_Msk             (0x1UL << OPAMP2_CSR_TSTREF_Pos)     /*!< 0x20000000 */
+#define OPAMP2_CSR_TSTREF                 OPAMP2_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */
+#define OPAMP2_CSR_CALOUT_Pos             (30U)
+#define OPAMP2_CSR_CALOUT_Msk             (0x1UL << OPAMP2_CSR_CALOUT_Pos)     /*!< 0x40000000 */
+#define OPAMP2_CSR_CALOUT                 OPAMP2_CSR_CALOUT_Msk                /*!< Operational amplifier2 calibration output */
+
+/*******************  Bit definition for OPAMP_OTR register  ******************/
+#define OPAMP_OTR_TRIMOFFSETN_Pos        (0U)
+#define OPAMP_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP_OTR_TRIMOFFSETN            OPAMP_OTR_TRIMOFFSETN_Msk             /*!< Trim for NMOS differential pairs */
+#define OPAMP_OTR_TRIMOFFSETP_Pos        (8U)
+#define OPAMP_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP_OTR_TRIMOFFSETP            OPAMP_OTR_TRIMOFFSETP_Msk             /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP1_OTR register  ******************/
+#define OPAMP1_OTR_TRIMOFFSETN_Pos        (0U)
+#define OPAMP1_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP1_OTR_TRIMOFFSETN            OPAMP1_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */
+#define OPAMP1_OTR_TRIMOFFSETP_Pos        (8U)
+#define OPAMP1_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP1_OTR_TRIMOFFSETP            OPAMP1_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP2_OTR register  ******************/
+#define OPAMP2_OTR_TRIMOFFSETN_Pos        (0U)
+#define OPAMP2_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP2_OTR_TRIMOFFSETN            OPAMP2_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */
+#define OPAMP2_OTR_TRIMOFFSETP_Pos        (8U)
+#define OPAMP2_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP2_OTR_TRIMOFFSETP            OPAMP2_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP_HSOTR register  ****************/
+#define OPAMP_HSOTR_TRIMHSOFFSETN_Pos    (0U)
+#define OPAMP_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP_HSOTR_TRIMHSOFFSETN        OPAMP_HSOTR_TRIMHSOFFSETN_Msk         /*!< Trim for NMOS differential pairs */
+#define OPAMP_HSOTR_TRIMHSOFFSETP_Pos    (8U)
+#define OPAMP_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP_HSOTR_TRIMHSOFFSETP        OPAMP_HSOTR_TRIMHSOFFSETP_Msk         /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP1_HSOTR register  ****************/
+#define OPAMP1_HSOTR_TRIMHSOFFSETN_Pos    (0U)
+#define OPAMP1_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP1_HSOTR_TRIMHSOFFSETN        OPAMP1_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */
+#define OPAMP1_HSOTR_TRIMHSOFFSETP_Pos    (8U)
+#define OPAMP1_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP1_HSOTR_TRIMHSOFFSETP        OPAMP1_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP2_HSOTR register  ****************/
+#define OPAMP2_HSOTR_TRIMHSOFFSETN_Pos    (0U)
+#define OPAMP2_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP2_HSOTR_TRIMHSOFFSETN        OPAMP2_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */
+#define OPAMP2_HSOTR_TRIMHSOFFSETP_Pos    (8U)
+#define OPAMP2_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP2_HSOTR_TRIMHSOFFSETP        OPAMP2_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             Power Control                                  */
+/*                                                                            */
+/******************************************************************************/
+/*************************  NUMBER OF POWER DOMAINS  **************************/
+#define POWER_DOMAINS_NUMBER           3U                                      /*!< 3 Domains */
+
+/********************  Bit definition for PWR_CR1 register  *******************/
+#define PWR_CR1_ALS_Pos                (17U)
+#define PWR_CR1_ALS_Msk                (0x3UL << PWR_CR1_ALS_Pos)              /*!< 0x00060000 */
+#define PWR_CR1_ALS                    PWR_CR1_ALS_Msk                         /*!< Analog Voltage Detector level selection */
+#define PWR_CR1_ALS_0                  (0x1UL << PWR_CR1_ALS_Pos)              /*!< 0x00020000 */
+#define PWR_CR1_ALS_1                  (0x2UL << PWR_CR1_ALS_Pos)              /*!< 0x00040000 */
+#define PWR_CR1_AVDEN_Pos              (16U)
+#define PWR_CR1_AVDEN_Msk              (0x1UL << PWR_CR1_AVDEN_Pos)            /*!< 0x00010000 */
+#define PWR_CR1_AVDEN                  PWR_CR1_AVDEN_Msk                       /*!< Analog Voltage Detector Enable */
+#define PWR_CR1_SVOS_Pos               (14U)
+#define PWR_CR1_SVOS_Msk               (0x3UL << PWR_CR1_SVOS_Pos)             /*!< 0x0000C000 */
+#define PWR_CR1_SVOS                   PWR_CR1_SVOS_Msk                        /*!< System STOP mode Voltage Scaling selection */
+#define PWR_CR1_SVOS_0                 (0x1UL << PWR_CR1_SVOS_Pos)             /*!< 0x00004000 */
+#define PWR_CR1_SVOS_1                 (0x2UL << PWR_CR1_SVOS_Pos)             /*!< 0x00008000 */
+#define PWR_CR1_FLPS_Pos               (9U)
+#define PWR_CR1_FLPS_Msk               (0x1UL << PWR_CR1_FLPS_Pos)             /*!< 0x00000200 */
+#define PWR_CR1_FLPS                   PWR_CR1_FLPS_Msk                        /*!< Flash low power mode in DSTOP */
+#define PWR_CR1_DBP_Pos                (8U)
+#define PWR_CR1_DBP_Msk                (0x1UL << PWR_CR1_DBP_Pos)              /*!< 0x00000100 */
+#define PWR_CR1_DBP                    PWR_CR1_DBP_Msk                         /*!< Disable Back-up domain Protection */
+#define PWR_CR1_PLS_Pos                (5U)
+#define PWR_CR1_PLS_Msk                (0x7UL << PWR_CR1_PLS_Pos)              /*!< 0x000000E0 */
+#define PWR_CR1_PLS                    PWR_CR1_PLS_Msk                         /*!< Programmable Voltage Detector level selection */
+#define PWR_CR1_PLS_0                  (0x1UL << PWR_CR1_PLS_Pos)              /*!< 0x00000020 */
+#define PWR_CR1_PLS_1                  (0x2UL << PWR_CR1_PLS_Pos)              /*!< 0x00000040 */
+#define PWR_CR1_PLS_2                  (0x4UL << PWR_CR1_PLS_Pos)              /*!< 0x00000080 */
+#define PWR_CR1_PVDEN_Pos              (4U)
+#define PWR_CR1_PVDEN_Msk              (0x1UL << PWR_CR1_PVDEN_Pos)            /*!< 0x00000010 */
+#define PWR_CR1_PVDEN                  PWR_CR1_PVDEN_Msk                       /*!< Programmable Voltage detector enable */
+#define PWR_CR1_LPDS_Pos               (0U)
+#define PWR_CR1_LPDS_Msk               (0x1UL << PWR_CR1_LPDS_Pos)             /*!< 0x00000001 */
+#define PWR_CR1_LPDS                   PWR_CR1_LPDS_Msk                        /*!< Low Power Deepsleep with SVOS3 */
+
+/*!< PVD level configuration */
+#define PWR_CR1_PLS_LEV0               (0UL)                                   /*!< PVD level 0 */
+#define PWR_CR1_PLS_LEV1_Pos           (5U)
+#define PWR_CR1_PLS_LEV1_Msk           (0x1UL << PWR_CR1_PLS_LEV1_Pos)         /*!< 0x00000020 */
+#define PWR_CR1_PLS_LEV1               PWR_CR1_PLS_LEV1_Msk                    /*!< PVD level 1 */
+#define PWR_CR1_PLS_LEV2_Pos           (6U)
+#define PWR_CR1_PLS_LEV2_Msk           (0x1UL << PWR_CR1_PLS_LEV2_Pos)         /*!< 0x00000040 */
+#define PWR_CR1_PLS_LEV2               PWR_CR1_PLS_LEV2_Msk                    /*!< PVD level 2 */
+#define PWR_CR1_PLS_LEV3_Pos           (5U)
+#define PWR_CR1_PLS_LEV3_Msk           (0x3UL << PWR_CR1_PLS_LEV3_Pos)         /*!< 0x00000060 */
+#define PWR_CR1_PLS_LEV3               PWR_CR1_PLS_LEV3_Msk                    /*!< PVD level 3 */
+#define PWR_CR1_PLS_LEV4_Pos           (7U)
+#define PWR_CR1_PLS_LEV4_Msk           (0x1UL << PWR_CR1_PLS_LEV4_Pos)         /*!< 0x00000080 */
+#define PWR_CR1_PLS_LEV4               PWR_CR1_PLS_LEV4_Msk                    /*!< PVD level 4 */
+#define PWR_CR1_PLS_LEV5_Pos           (5U)
+#define PWR_CR1_PLS_LEV5_Msk           (0x5UL << PWR_CR1_PLS_LEV5_Pos)         /*!< 0x000000A0 */
+#define PWR_CR1_PLS_LEV5               PWR_CR1_PLS_LEV5_Msk                    /*!< PVD level 5 */
+#define PWR_CR1_PLS_LEV6_Pos           (6U)
+#define PWR_CR1_PLS_LEV6_Msk           (0x3UL << PWR_CR1_PLS_LEV6_Pos)         /*!< 0x000000C0 */
+#define PWR_CR1_PLS_LEV6               PWR_CR1_PLS_LEV6_Msk                    /*!< PVD level 6 */
+#define PWR_CR1_PLS_LEV7_Pos           (5U)
+#define PWR_CR1_PLS_LEV7_Msk           (0x7UL << PWR_CR1_PLS_LEV7_Pos)         /*!< 0x000000E0 */
+#define PWR_CR1_PLS_LEV7               PWR_CR1_PLS_LEV7_Msk                    /*!< PVD level 7 */
+
+/*!< AVD level configuration */
+#define PWR_CR1_ALS_LEV0               (0UL)                                   /*!< AVD level 0 */
+#define PWR_CR1_ALS_LEV1_Pos           (17U)
+#define PWR_CR1_ALS_LEV1_Msk           (0x1UL << PWR_CR1_ALS_LEV1_Pos)         /*!< 0x00020000 */
+#define PWR_CR1_ALS_LEV1               PWR_CR1_ALS_LEV1_Msk                    /*!< AVD level 1 */
+#define PWR_CR1_ALS_LEV2_Pos           (18U)
+#define PWR_CR1_ALS_LEV2_Msk           (0x1UL << PWR_CR1_ALS_LEV2_Pos)         /*!< 0x00040000 */
+#define PWR_CR1_ALS_LEV2               PWR_CR1_ALS_LEV2_Msk                    /*!< AVD level 2 */
+#define PWR_CR1_ALS_LEV3_Pos           (17U)
+#define PWR_CR1_ALS_LEV3_Msk           (0x3UL << PWR_CR1_ALS_LEV3_Pos)         /*!< 0x00060000 */
+#define PWR_CR1_ALS_LEV3               PWR_CR1_ALS_LEV3_Msk                    /*!< AVD level 3 */
+
+/********************  Bit definition for PWR_CSR1 register  ******************/
+#define PWR_CSR1_AVDO_Pos              (16U)
+#define PWR_CSR1_AVDO_Msk              (0x1UL << PWR_CSR1_AVDO_Pos)            /*!< 0x00010000 */
+#define PWR_CSR1_AVDO                  PWR_CSR1_AVDO_Msk                       /*!< Analog Voltage Detect Output */
+#define PWR_CSR1_ACTVOS_Pos            (14U)
+#define PWR_CSR1_ACTVOS_Msk            (0x3UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x0000C000 */
+#define PWR_CSR1_ACTVOS                PWR_CSR1_ACTVOS_Msk                     /*!< Current actual used VOS for VDD11 Voltage Scaling */
+#define PWR_CSR1_ACTVOS_0              (0x1UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00004000 */
+#define PWR_CSR1_ACTVOS_1              (0x2UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00008000 */
+#define PWR_CSR1_ACTVOSRDY_Pos         (13U)
+#define PWR_CSR1_ACTVOSRDY_Msk         (0x1UL << PWR_CSR1_ACTVOSRDY_Pos)       /*!< 0x00002000 */
+#define PWR_CSR1_ACTVOSRDY             PWR_CSR1_ACTVOSRDY_Msk                  /*!< Ready bit for current actual used VOS for VDD11 Voltage Scaling  */
+#define PWR_CSR1_PVDO_Pos              (4U)
+#define PWR_CSR1_PVDO_Msk              (0x1UL << PWR_CSR1_PVDO_Pos)            /*!< 0x00000010 */
+#define PWR_CSR1_PVDO                  PWR_CSR1_PVDO_Msk                       /*!< Programmable Voltage Detect Output */
+
+/********************  Bit definition for PWR_CR2 register  *******************/
+#define PWR_CR2_TEMPH_Pos              (23U)
+#define PWR_CR2_TEMPH_Msk              (0x1UL << PWR_CR2_TEMPH_Pos)            /*!< 0x00800000 */
+#define PWR_CR2_TEMPH                  PWR_CR2_TEMPH_Msk                       /*!< Monitored temperature level above high threshold */
+#define PWR_CR2_TEMPL_Pos              (22U)
+#define PWR_CR2_TEMPL_Msk              (0x1UL << PWR_CR2_TEMPL_Pos)            /*!< 0x00400000 */
+#define PWR_CR2_TEMPL                  PWR_CR2_TEMPL_Msk                       /*!< Monitored temperature level above low threshold */
+#define PWR_CR2_VBATH_Pos              (21U)
+#define PWR_CR2_VBATH_Msk              (0x1UL << PWR_CR2_VBATH_Pos)            /*!< 0x00200000 */
+#define PWR_CR2_VBATH                  PWR_CR2_VBATH_Msk                       /*!< Monitored VBAT level above high threshold */
+#define PWR_CR2_VBATL_Pos              (20U)
+#define PWR_CR2_VBATL_Msk              (0x1UL << PWR_CR2_VBATL_Pos)            /*!< 0x00100000 */
+#define PWR_CR2_VBATL                  PWR_CR2_VBATL_Msk                       /*!< Monitored VBAT level above low threshold */
+#define PWR_CR2_BRRDY_Pos              (16U)
+#define PWR_CR2_BRRDY_Msk              (0x1UL << PWR_CR2_BRRDY_Pos)            /*!< 0x00010000 */
+#define PWR_CR2_BRRDY                  PWR_CR2_BRRDY_Msk                       /*!< Backup regulator ready */
+#define PWR_CR2_MONEN_Pos              (4U)
+#define PWR_CR2_MONEN_Msk              (0x1UL << PWR_CR2_MONEN_Pos)            /*!< 0x00000010 */
+#define PWR_CR2_MONEN                  PWR_CR2_MONEN_Msk                       /*!< VBAT and temperature monitoring enable */
+#define PWR_CR2_BREN_Pos               (0U)
+#define PWR_CR2_BREN_Msk               (0x1UL << PWR_CR2_BREN_Pos)             /*!< 0x00000001 */
+#define PWR_CR2_BREN                   PWR_CR2_BREN_Msk                        /*!< Backup regulator enable */
+
+/********************  Bit definition for PWR_CR3 register  *******************/
+#define PWR_CR3_USB33RDY_Pos           (26U)
+#define PWR_CR3_USB33RDY_Msk           (0x1UL << PWR_CR3_USB33RDY_Pos)         /*!< 0x04000000 */
+#define PWR_CR3_USB33RDY               PWR_CR3_USB33RDY_Msk                    /*!< USB supply ready */
+#define PWR_CR3_USBREGEN_Pos           (25U)
+#define PWR_CR3_USBREGEN_Msk           (0x1UL << PWR_CR3_USBREGEN_Pos)         /*!< 0x02000000 */
+#define PWR_CR3_USBREGEN               PWR_CR3_USBREGEN_Msk                    /*!< USB regulator enable */
+#define PWR_CR3_USB33DEN_Pos           (24U)
+#define PWR_CR3_USB33DEN_Msk           (0x1UL << PWR_CR3_USB33DEN_Pos)         /*!< 0x01000000 */
+#define PWR_CR3_USB33DEN               PWR_CR3_USB33DEN_Msk                    /*!< VDD33_USB voltage level detector enable */
+#define PWR_CR3_VBRS_Pos               (9U)
+#define PWR_CR3_VBRS_Msk               (0x1UL << PWR_CR3_VBRS_Pos)             /*!< 0x00000200 */
+#define PWR_CR3_VBRS                   PWR_CR3_VBRS_Msk                        /*!< VBAT charging resistor selection */
+#define PWR_CR3_VBE_Pos                (8U)
+#define PWR_CR3_VBE_Msk                (0x1UL << PWR_CR3_VBE_Pos)              /*!< 0x00000100 */
+#define PWR_CR3_VBE                    PWR_CR3_VBE_Msk                         /*!< VBAT charging enable */
+#define PWR_CR3_SCUEN_Pos              (2U)
+#define PWR_CR3_SCUEN_Msk              (0x1UL << PWR_CR3_SCUEN_Pos)            /*!< 0x00000004 */
+#define PWR_CR3_SCUEN                  PWR_CR3_SCUEN_Msk                       /*!< Supply configuration update enable */
+#define PWR_CR3_LDOEN_Pos              (1U)
+#define PWR_CR3_LDOEN_Msk              (0x1UL << PWR_CR3_LDOEN_Pos)            /*!< 0x00000002 */
+#define PWR_CR3_LDOEN                  PWR_CR3_LDOEN_Msk                       /*!< Low Drop Output regulator enable */
+#define PWR_CR3_BYPASS_Pos             (0U)
+#define PWR_CR3_BYPASS_Msk             (0x1UL << PWR_CR3_BYPASS_Pos)           /*!< 0x00000001 */
+#define PWR_CR3_BYPASS                 PWR_CR3_BYPASS_Msk                      /*!< Power Management Unit bypass */
+
+/********************  Bit definition for PWR_CPUCR register  *****************/
+#define PWR_CPUCR_RUN_D3_Pos           (11U)
+#define PWR_CPUCR_RUN_D3_Msk           (0x1UL << PWR_CPUCR_RUN_D3_Pos)         /*!< 0x00000800 */
+#define PWR_CPUCR_RUN_D3               PWR_CPUCR_RUN_D3_Msk                    /*!< Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes */
+#define PWR_CPUCR_CSSF_Pos             (9U)
+#define PWR_CPUCR_CSSF_Msk             (0x1UL << PWR_CPUCR_CSSF_Pos)           /*!< 0x00000200 */
+#define PWR_CPUCR_CSSF                 PWR_CPUCR_CSSF_Msk                      /*!< Clear D1 domain CPU1 STANDBY, STOP and HOLD flags */
+#define PWR_CPUCR_SBF_D2_Pos           (8U)
+#define PWR_CPUCR_SBF_D2_Msk           (0x1UL << PWR_CPUCR_SBF_D2_Pos)         /*!< 0x00000100 */
+#define PWR_CPUCR_SBF_D2               PWR_CPUCR_SBF_D2_Msk                    /*!< D2 domain DSTANDBY Flag */
+#define PWR_CPUCR_SBF_D1_Pos           (7U)
+#define PWR_CPUCR_SBF_D1_Msk           (0x1UL << PWR_CPUCR_SBF_D1_Pos)         /*!< 0x00000080 */
+#define PWR_CPUCR_SBF_D1               PWR_CPUCR_SBF_D1_Msk                    /*!< D1 domain DSTANDBY Flag */
+#define PWR_CPUCR_SBF_Pos              (6U)
+#define PWR_CPUCR_SBF_Msk              (0x1UL << PWR_CPUCR_SBF_Pos)            /*!< 0x00000040 */
+#define PWR_CPUCR_SBF                  PWR_CPUCR_SBF_Msk                       /*!< System STANDBY Flag */
+#define PWR_CPUCR_STOPF_Pos            (5U)
+#define PWR_CPUCR_STOPF_Msk            (0x1UL << PWR_CPUCR_STOPF_Pos)          /*!< 0x00000020 */
+#define PWR_CPUCR_STOPF                PWR_CPUCR_STOPF_Msk                     /*!< STOP Flag */
+#define PWR_CPUCR_PDDS_D3_Pos          (2U)
+#define PWR_CPUCR_PDDS_D3_Msk          (0x1UL << PWR_CPUCR_PDDS_D3_Pos)        /*!< 0x00000004 */
+#define PWR_CPUCR_PDDS_D3              PWR_CPUCR_PDDS_D3_Msk                   /*!< System D3 domain Power Down Deepsleep */
+#define PWR_CPUCR_PDDS_D2_Pos          (1U)
+#define PWR_CPUCR_PDDS_D2_Msk          (0x1UL << PWR_CPUCR_PDDS_D2_Pos)        /*!< 0x00000002 */
+#define PWR_CPUCR_PDDS_D2              PWR_CPUCR_PDDS_D2_Msk                   /*!< D2 domain Power Down Deepsleep */
+#define PWR_CPUCR_PDDS_D1_Pos          (0U)
+#define PWR_CPUCR_PDDS_D1_Msk          (0x1UL << PWR_CPUCR_PDDS_D1_Pos)        /*!< 0x00000001 */
+#define PWR_CPUCR_PDDS_D1              PWR_CPUCR_PDDS_D1_Msk                   /*!< D1 domain Power Down Deepsleep selection */
+
+
+/********************  Bit definition for PWR_D3CR register  ******************/
+#define PWR_D3CR_VOS_Pos               (14U)
+#define PWR_D3CR_VOS_Msk               (0x3UL << PWR_D3CR_VOS_Pos)             /*!< 0x0000C000 */
+#define PWR_D3CR_VOS                   PWR_D3CR_VOS_Msk                        /*!< Voltage Scaling selection according performance */
+#define PWR_D3CR_VOS_0                 (0x1UL << PWR_D3CR_VOS_Pos)             /*!< 0x00004000 */
+#define PWR_D3CR_VOS_1                 (0x2UL << PWR_D3CR_VOS_Pos)             /*!< 0x00008000 */
+#define PWR_D3CR_VOSRDY_Pos            (13U)
+#define PWR_D3CR_VOSRDY_Msk            (0x1UL << PWR_D3CR_VOSRDY_Pos)          /*!< 0x00002000 */
+#define PWR_D3CR_VOSRDY                PWR_D3CR_VOSRDY_Msk                     /*!< VOS Ready bit for VDD11 Voltage Scaling output selection */
+
+/******************  Bit definition for PWR_WKUPCR register  ******************/
+#define PWR_WKUPCR_WKUPC6_Pos          (5U)
+#define PWR_WKUPCR_WKUPC6_Msk          (0x1UL << PWR_WKUPCR_WKUPC6_Pos)        /*!< 0x00000020 */
+#define PWR_WKUPCR_WKUPC6              PWR_WKUPCR_WKUPC6_Msk                   /*!< Clear Wakeup Pin Flag 6 */
+#define PWR_WKUPCR_WKUPC5_Pos          (4U)
+#define PWR_WKUPCR_WKUPC5_Msk          (0x1UL << PWR_WKUPCR_WKUPC5_Pos)        /*!< 0x00000010 */
+#define PWR_WKUPCR_WKUPC5              PWR_WKUPCR_WKUPC5_Msk                   /*!< Clear Wakeup Pin Flag 5 */
+#define PWR_WKUPCR_WKUPC4_Pos          (3U)
+#define PWR_WKUPCR_WKUPC4_Msk          (0x1UL << PWR_WKUPCR_WKUPC4_Pos)        /*!< 0x00000008 */
+#define PWR_WKUPCR_WKUPC4              PWR_WKUPCR_WKUPC4_Msk                   /*!< Clear Wakeup Pin Flag 4 */
+#define PWR_WKUPCR_WKUPC3_Pos          (2U)
+#define PWR_WKUPCR_WKUPC3_Msk          (0x1UL << PWR_WKUPCR_WKUPC3_Pos)        /*!< 0x00000004 */
+#define PWR_WKUPCR_WKUPC3              PWR_WKUPCR_WKUPC3_Msk                   /*!< Clear Wakeup Pin Flag 3 */
+#define PWR_WKUPCR_WKUPC2_Pos          (1U)
+#define PWR_WKUPCR_WKUPC2_Msk          (0x1UL << PWR_WKUPCR_WKUPC2_Pos)        /*!< 0x00000002 */
+#define PWR_WKUPCR_WKUPC2              PWR_WKUPCR_WKUPC2_Msk                   /*!< Clear Wakeup Pin Flag 2 */
+#define PWR_WKUPCR_WKUPC1_Pos          (0U)
+#define PWR_WKUPCR_WKUPC1_Msk          (0x1UL << PWR_WKUPCR_WKUPC1_Pos)        /*!< 0x00000001 */
+#define PWR_WKUPCR_WKUPC1              PWR_WKUPCR_WKUPC1_Msk                   /*!< Clear Wakeup Pin Flag 1 */
+
+/********************  Bit definition for PWR_WKUPFR register  ****************/
+#define PWR_WKUPFR_WKUPF6_Pos          (5U)
+#define PWR_WKUPFR_WKUPF6_Msk          (0x1UL << PWR_WKUPFR_WKUPF6_Pos)        /*!< 0x00000020 */
+#define PWR_WKUPFR_WKUPF6              PWR_WKUPFR_WKUPF6_Msk                   /*!< Wakeup Pin Flag 6 */
+#define PWR_WKUPFR_WKUPF5_Pos          (4U)
+#define PWR_WKUPFR_WKUPF5_Msk          (0x1UL << PWR_WKUPFR_WKUPF5_Pos)        /*!< 0x00000010 */
+#define PWR_WKUPFR_WKUPF5              PWR_WKUPFR_WKUPF5_Msk                   /*!< Wakeup Pin Flag 5 */
+#define PWR_WKUPFR_WKUPF4_Pos          (3U)
+#define PWR_WKUPFR_WKUPF4_Msk          (0x1UL << PWR_WKUPFR_WKUPF4_Pos)        /*!< 0x00000008 */
+#define PWR_WKUPFR_WKUPF4              PWR_WKUPFR_WKUPF4_Msk                   /*!< Wakeup Pin Flag 4 */
+#define PWR_WKUPFR_WKUPF3_Pos          (2U)
+#define PWR_WKUPFR_WKUPF3_Msk          (0x1UL << PWR_WKUPFR_WKUPF3_Pos)        /*!< 0x00000004 */
+#define PWR_WKUPFR_WKUPF3              PWR_WKUPFR_WKUPF3_Msk                   /*!< Wakeup Pin Flag 3 */
+#define PWR_WKUPFR_WKUPF2_Pos          (1U)
+#define PWR_WKUPFR_WKUPF2_Msk          (0x1UL << PWR_WKUPFR_WKUPF2_Pos)        /*!< 0x00000002 */
+#define PWR_WKUPFR_WKUPF2              PWR_WKUPFR_WKUPF2_Msk                   /*!< Wakeup Pin Flag 2 */
+#define PWR_WKUPFR_WKUPF1_Pos          (0U)
+#define PWR_WKUPFR_WKUPF1_Msk          (0x1UL << PWR_WKUPFR_WKUPF1_Pos)        /*!< 0x00000001 */
+#define PWR_WKUPFR_WKUPF1              PWR_WKUPFR_WKUPF1_Msk                   /*!< Wakeup Pin Flag 1 */
+
+/******************  Bit definition for PWR_WKUPEPR register  *****************/
+#define PWR_WKUPEPR_WKUPPUPD6_Pos      (26U)
+#define PWR_WKUPEPR_WKUPPUPD6_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x0C000000 */
+#define PWR_WKUPEPR_WKUPPUPD6          PWR_WKUPEPR_WKUPPUPD6_Msk               /*!< Wakeup Pin pull configuration for WKUP6 */
+#define PWR_WKUPEPR_WKUPPUPD6_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x04000000 */
+#define PWR_WKUPEPR_WKUPPUPD6_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x08000000 */
+#define PWR_WKUPEPR_WKUPPUPD5_Pos      (24U)
+#define PWR_WKUPEPR_WKUPPUPD5_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x03000000 */
+#define PWR_WKUPEPR_WKUPPUPD5          PWR_WKUPEPR_WKUPPUPD5_Msk               /*!< Wakeup Pin pull configuration for WKUP5 */
+#define PWR_WKUPEPR_WKUPPUPD5_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x01000000 */
+#define PWR_WKUPEPR_WKUPPUPD5_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x02000000 */
+#define PWR_WKUPEPR_WKUPPUPD4_Pos      (22U)
+#define PWR_WKUPEPR_WKUPPUPD4_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00C00000 */
+#define PWR_WKUPEPR_WKUPPUPD4          PWR_WKUPEPR_WKUPPUPD4_Msk               /*!< Wakeup Pin pull configuration for WKUP4 */
+#define PWR_WKUPEPR_WKUPPUPD4_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00400000 */
+#define PWR_WKUPEPR_WKUPPUPD4_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00800000 */
+#define PWR_WKUPEPR_WKUPPUPD3_Pos      (20U)
+#define PWR_WKUPEPR_WKUPPUPD3_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00300000 */
+#define PWR_WKUPEPR_WKUPPUPD3          PWR_WKUPEPR_WKUPPUPD3_Msk               /*!< Wakeup Pin pull configuration for WKUP3 */
+#define PWR_WKUPEPR_WKUPPUPD3_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00100000 */
+#define PWR_WKUPEPR_WKUPPUPD3_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00200000 */
+#define PWR_WKUPEPR_WKUPPUPD2_Pos      (18U)
+#define PWR_WKUPEPR_WKUPPUPD2_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x000C0000 */
+#define PWR_WKUPEPR_WKUPPUPD2          PWR_WKUPEPR_WKUPPUPD2_Msk               /*!< Wakeup Pin pull configuration for WKUP2 */
+#define PWR_WKUPEPR_WKUPPUPD2_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00040000 */
+#define PWR_WKUPEPR_WKUPPUPD2_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00080000 */
+#define PWR_WKUPEPR_WKUPPUPD1_Pos      (16U)
+#define PWR_WKUPEPR_WKUPPUPD1_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00030000 */
+#define PWR_WKUPEPR_WKUPPUPD1          PWR_WKUPEPR_WKUPPUPD1_Msk               /*!< Wakeup Pin pull configuration for WKUP1 */
+#define PWR_WKUPEPR_WKUPPUPD1_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00010000 */
+#define PWR_WKUPEPR_WKUPPUPD1_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00020000 */
+#define PWR_WKUPEPR_WKUPP6_Pos         (13U)
+#define PWR_WKUPEPR_WKUPP6_Msk         (0x1UL << PWR_WKUPEPR_WKUPP6_Pos)       /*!< 0x00002000 */
+#define PWR_WKUPEPR_WKUPP6             PWR_WKUPEPR_WKUPP6_Msk                  /*!< Wakeup Pin Polarity for WKUP6 */
+#define PWR_WKUPEPR_WKUPP5_Pos         (12U)
+#define PWR_WKUPEPR_WKUPP5_Msk         (0x1UL << PWR_WKUPEPR_WKUPP5_Pos)       /*!< 0x00001000 */
+#define PWR_WKUPEPR_WKUPP5             PWR_WKUPEPR_WKUPP5_Msk                  /*!< Wakeup Pin Polarity for WKUP5 */
+#define PWR_WKUPEPR_WKUPP4_Pos         (11U)
+#define PWR_WKUPEPR_WKUPP4_Msk         (0x1UL << PWR_WKUPEPR_WKUPP4_Pos)       /*!< 0x00000800 */
+#define PWR_WKUPEPR_WKUPP4             PWR_WKUPEPR_WKUPP4_Msk                  /*!< Wakeup Pin Polarity for WKUP4 */
+#define PWR_WKUPEPR_WKUPP3_Pos         (10U)
+#define PWR_WKUPEPR_WKUPP3_Msk         (0x1UL << PWR_WKUPEPR_WKUPP3_Pos)       /*!< 0x00000400 */
+#define PWR_WKUPEPR_WKUPP3             PWR_WKUPEPR_WKUPP3_Msk                  /*!< Wakeup Pin Polarity for WKUP3 */
+#define PWR_WKUPEPR_WKUPP2_Pos         (9U)
+#define PWR_WKUPEPR_WKUPP2_Msk         (0x1UL << PWR_WKUPEPR_WKUPP2_Pos)       /*!< 0x00000200 */
+#define PWR_WKUPEPR_WKUPP2             PWR_WKUPEPR_WKUPP2_Msk                  /*!< Wakeup Pin Polarity for WKUP2 */
+#define PWR_WKUPEPR_WKUPP1_Pos         (8U)
+#define PWR_WKUPEPR_WKUPP1_Msk         (0x1UL << PWR_WKUPEPR_WKUPP1_Pos)       /*!< 0x00000100 */
+#define PWR_WKUPEPR_WKUPP1             PWR_WKUPEPR_WKUPP1_Msk                  /*!< Wakeup Pin Polarity for WKUP1 */
+#define PWR_WKUPEPR_WKUPEN6_Pos        (5U)
+#define PWR_WKUPEPR_WKUPEN6_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN6_Pos)      /*!< 0x00000020 */
+#define PWR_WKUPEPR_WKUPEN6            PWR_WKUPEPR_WKUPEN6_Msk                 /*!< Enable Wakeup Pin WKUP6 */
+#define PWR_WKUPEPR_WKUPEN5_Pos        (4U)
+#define PWR_WKUPEPR_WKUPEN5_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN5_Pos)      /*!< 0x00000010 */
+#define PWR_WKUPEPR_WKUPEN5            PWR_WKUPEPR_WKUPEN5_Msk                 /*!< Enable Wakeup Pin WKUP5 */
+#define PWR_WKUPEPR_WKUPEN4_Pos        (3U)
+#define PWR_WKUPEPR_WKUPEN4_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos)      /*!< 0x00000008 */
+#define PWR_WKUPEPR_WKUPEN4            PWR_WKUPEPR_WKUPEN4_Msk                 /*!< Enable Wakeup Pin WKUP4 */
+#define PWR_WKUPEPR_WKUPEN3_Pos        (2U)
+#define PWR_WKUPEPR_WKUPEN3_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos)      /*!< 0x00000004 */
+#define PWR_WKUPEPR_WKUPEN3            PWR_WKUPEPR_WKUPEN3_Msk                 /*!< Enable Wakeup Pin WKUP3 */
+#define PWR_WKUPEPR_WKUPEN2_Pos        (1U)
+#define PWR_WKUPEPR_WKUPEN2_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos)      /*!< 0x00000002 */
+#define PWR_WKUPEPR_WKUPEN2            PWR_WKUPEPR_WKUPEN2_Msk                 /*!< Enable Wakeup Pin WKUP2 */
+#define PWR_WKUPEPR_WKUPEN1_Pos        (0U)
+#define PWR_WKUPEPR_WKUPEN1_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos)      /*!< 0x00000001 */
+#define PWR_WKUPEPR_WKUPEN1            PWR_WKUPEPR_WKUPEN1_Msk                 /*!< Enable Wakeup Pin WKUP1 */
+#define PWR_WKUPEPR_WKUPEN_Pos         (0U)
+#define PWR_WKUPEPR_WKUPEN_Msk         (0x3FUL << PWR_WKUPEPR_WKUPEN_Pos)      /*!< 0x0000003F */
+#define PWR_WKUPEPR_WKUPEN             PWR_WKUPEPR_WKUPEN_Msk                  /*!< Enable all Wakeup Pin */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Reset and Clock Control                            */
+/*                                                                            */
+/******************************************************************************/
+/*******************************  RCC VERSION  ********************************/
+#define RCC_VER_X
+
+/********************  Bit definition for RCC_CR register  ********************/
+#define RCC_CR_HSION_Pos                       (0U)
+#define RCC_CR_HSION_Msk                       (0x1UL << RCC_CR_HSION_Pos)     /*!< 0x00000001 */
+#define RCC_CR_HSION                           RCC_CR_HSION_Msk                /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIKERON_Pos                    (1U)
+#define RCC_CR_HSIKERON_Msk                    (0x1UL << RCC_CR_HSIKERON_Pos)  /*!< 0x00000002 */
+#define RCC_CR_HSIKERON                        RCC_CR_HSIKERON_Msk             /*!< Internal High Speed clock enable for some IPs Kernel */
+#define RCC_CR_HSIRDY_Pos                      (2U)
+#define RCC_CR_HSIRDY_Msk                      (0x1UL << RCC_CR_HSIRDY_Pos)    /*!< 0x00000004 */
+#define RCC_CR_HSIRDY                          RCC_CR_HSIRDY_Msk               /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSIDIV_Pos                      (3U)
+#define RCC_CR_HSIDIV_Msk                      (0x3UL << RCC_CR_HSIDIV_Pos)    /*!< 0x00000018 */
+#define RCC_CR_HSIDIV                          RCC_CR_HSIDIV_Msk               /*!< Internal High Speed clock divider selection */
+#define RCC_CR_HSIDIV_1                        (0x0UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000000 */
+#define RCC_CR_HSIDIV_2                        (0x1UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000008 */
+#define RCC_CR_HSIDIV_4                        (0x2UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000010 */
+#define RCC_CR_HSIDIV_8                        (0x3UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000018 */
+
+#define RCC_CR_HSIDIVF_Pos                     (5U)
+#define RCC_CR_HSIDIVF_Msk                     (0x1UL << RCC_CR_HSIDIVF_Pos)   /*!< 0x00000020 */
+#define RCC_CR_HSIDIVF                         RCC_CR_HSIDIVF_Msk              /*!< HSI Divider flag */
+#define RCC_CR_CSION_Pos                       (7U)
+#define RCC_CR_CSION_Msk                       (0x1UL << RCC_CR_CSION_Pos)     /*!< 0x00000080 */
+#define RCC_CR_CSION                           RCC_CR_CSION_Msk                /*!< The Internal RC 4MHz oscillator clock enable */
+#define RCC_CR_CSIRDY_Pos                      (8U)
+#define RCC_CR_CSIRDY_Msk                      (0x1UL << RCC_CR_CSIRDY_Pos)    /*!< 0x00000100 */
+#define RCC_CR_CSIRDY                          RCC_CR_CSIRDY_Msk               /*!< The Internal RC 4MHz oscillator clock ready */
+#define RCC_CR_CSIKERON_Pos                    (9U)
+#define RCC_CR_CSIKERON_Msk                    (0x1UL << RCC_CR_CSIKERON_Pos)  /*!< 0x00000200 */
+#define RCC_CR_CSIKERON                        RCC_CR_CSIKERON_Msk             /*!< Internal RC 4MHz oscillator clock enable for some IPs Kernel */
+#define RCC_CR_HSI48ON_Pos                     (12U)
+#define RCC_CR_HSI48ON_Msk                     (0x1UL << RCC_CR_HSI48ON_Pos)   /*!< 0x00001000 */
+#define RCC_CR_HSI48ON                         RCC_CR_HSI48ON_Msk              /*!< HSI48 clock enable clock enable  */
+#define RCC_CR_HSI48RDY_Pos                    (13U)
+#define RCC_CR_HSI48RDY_Msk                    (0x1UL << RCC_CR_HSI48RDY_Pos)  /*!< 0x00002000 */
+#define RCC_CR_HSI48RDY                        RCC_CR_HSI48RDY_Msk             /*!< HSI48 clock ready */
+
+#define RCC_CR_D1CKRDY_Pos                     (14U)
+#define RCC_CR_D1CKRDY_Msk                     (0x1UL << RCC_CR_D1CKRDY_Pos)   /*!< 0x00004000 */
+#define RCC_CR_D1CKRDY                         RCC_CR_D1CKRDY_Msk              /*!< D1 domain clocks ready flag  */
+#define RCC_CR_D2CKRDY_Pos                     (15U)
+#define RCC_CR_D2CKRDY_Msk                     (0x1UL << RCC_CR_D2CKRDY_Pos)   /*!< 0x00008000 */
+#define RCC_CR_D2CKRDY                         RCC_CR_D2CKRDY_Msk              /*!< D2 domain clocks ready flag */
+
+#define RCC_CR_HSEON_Pos                       (16U)
+#define RCC_CR_HSEON_Msk                       (0x1UL << RCC_CR_HSEON_Pos)     /*!< 0x00010000 */
+#define RCC_CR_HSEON                           RCC_CR_HSEON_Msk                /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY_Pos                      (17U)
+#define RCC_CR_HSERDY_Msk                      (0x1UL << RCC_CR_HSERDY_Pos)    /*!< 0x00020000 */
+#define RCC_CR_HSERDY                          RCC_CR_HSERDY_Msk               /*!< External High Speed clock ready */
+#define RCC_CR_HSEBYP_Pos                      (18U)
+#define RCC_CR_HSEBYP_Msk                      (0x1UL << RCC_CR_HSEBYP_Pos)    /*!< 0x00040000 */
+#define RCC_CR_HSEBYP                          RCC_CR_HSEBYP_Msk               /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSHSEON_Pos                    (19U)
+#define RCC_CR_CSSHSEON_Msk                    (0x1UL << RCC_CR_CSSHSEON_Pos)  /*!< 0x00080000 */
+#define RCC_CR_CSSHSEON                        RCC_CR_CSSHSEON_Msk             /*!< HSE Clock security System enable */
+
+
+#define RCC_CR_PLL1ON_Pos                      (24U)
+#define RCC_CR_PLL1ON_Msk                      (0x1UL << RCC_CR_PLL1ON_Pos)    /*!< 0x01000000 */
+#define RCC_CR_PLL1ON                          RCC_CR_PLL1ON_Msk               /*!< System PLL1 clock enable */
+#define RCC_CR_PLL1RDY_Pos                     (25U)
+#define RCC_CR_PLL1RDY_Msk                     (0x1UL << RCC_CR_PLL1RDY_Pos)   /*!< 0x02000000 */
+#define RCC_CR_PLL1RDY                         RCC_CR_PLL1RDY_Msk              /*!< System PLL1 clock ready */
+#define RCC_CR_PLL2ON_Pos                      (26U)
+#define RCC_CR_PLL2ON_Msk                      (0x1UL << RCC_CR_PLL2ON_Pos)    /*!< 0x04000000 */
+#define RCC_CR_PLL2ON                          RCC_CR_PLL2ON_Msk               /*!< System PLL2 clock enable */
+#define RCC_CR_PLL2RDY_Pos                     (27U)
+#define RCC_CR_PLL2RDY_Msk                     (0x1UL << RCC_CR_PLL2RDY_Pos)   /*!< 0x08000000 */
+#define RCC_CR_PLL2RDY                         RCC_CR_PLL2RDY_Msk              /*!< System PLL2 clock ready */
+#define RCC_CR_PLL3ON_Pos                      (28U)
+#define RCC_CR_PLL3ON_Msk                      (0x1UL << RCC_CR_PLL3ON_Pos)    /*!< 0x10000000 */
+#define RCC_CR_PLL3ON                          RCC_CR_PLL3ON_Msk               /*!< System PLL3 clock enable */
+#define RCC_CR_PLL3RDY_Pos                     (29U)
+#define RCC_CR_PLL3RDY_Msk                     (0x1UL << RCC_CR_PLL3RDY_Pos)   /*!< 0x20000000 */
+#define RCC_CR_PLL3RDY                         RCC_CR_PLL3RDY_Msk              /*!< System PLL3 clock ready */
+
+/*Legacy */
+#define RCC_CR_PLLON_Pos                       (24U)
+#define RCC_CR_PLLON_Msk                       (0x1UL << RCC_CR_PLLON_Pos)     /*!< 0x01000000 */
+#define RCC_CR_PLLON                           RCC_CR_PLLON_Msk                /*!< System PLL clock enable */
+#define RCC_CR_PLLRDY_Pos                      (25U)
+#define RCC_CR_PLLRDY_Msk                      (0x1UL << RCC_CR_PLLRDY_Pos)    /*!< 0x02000000 */
+#define RCC_CR_PLLRDY                          RCC_CR_PLLRDY_Msk               /*!< System PLL clock ready */
+
+/********************  Bit definition for RCC_HSICFGR register  ***************/
+/*!< HSICAL configuration */
+#define RCC_HSICFGR_HSICAL_Pos                 (0U)
+#define RCC_HSICFGR_HSICAL_Msk                 (0xFFFUL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000FFF */
+#define RCC_HSICFGR_HSICAL                     RCC_HSICFGR_HSICAL_Msk          /*!< HSICAL[11:0] bits */
+#define RCC_HSICFGR_HSICAL_0                   (0x001UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000001 */
+#define RCC_HSICFGR_HSICAL_1                   (0x002UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000002 */
+#define RCC_HSICFGR_HSICAL_2                   (0x004UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000004 */
+#define RCC_HSICFGR_HSICAL_3                   (0x008UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000008 */
+#define RCC_HSICFGR_HSICAL_4                   (0x010UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000010 */
+#define RCC_HSICFGR_HSICAL_5                   (0x020UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000020 */
+#define RCC_HSICFGR_HSICAL_6                   (0x040UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000040 */
+#define RCC_HSICFGR_HSICAL_7                   (0x080UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000080 */
+#define RCC_HSICFGR_HSICAL_8                   (0x100UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000100 */
+#define RCC_HSICFGR_HSICAL_9                   (0x200UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000200 */
+#define RCC_HSICFGR_HSICAL_10                  (0x400UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000400 */
+#define RCC_HSICFGR_HSICAL_11                  (0x800UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000800 */
+
+/*!< HSITRIM configuration */
+#define RCC_HSICFGR_HSITRIM_Pos                (24U)
+#define RCC_HSICFGR_HSITRIM_Msk                (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x7F000000 */
+#define RCC_HSICFGR_HSITRIM                    RCC_HSICFGR_HSITRIM_Msk         /*!< HSITRIM[6:0] bits */
+#define RCC_HSICFGR_HSITRIM_0                  (0x01UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x01000000 */
+#define RCC_HSICFGR_HSITRIM_1                  (0x02UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x02000000 */
+#define RCC_HSICFGR_HSITRIM_2                  (0x04UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x04000000 */
+#define RCC_HSICFGR_HSITRIM_3                  (0x08UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x08000000 */
+#define RCC_HSICFGR_HSITRIM_4                  (0x10UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x10000000 */
+#define RCC_HSICFGR_HSITRIM_5                  (0x20UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x20000000 */
+#define RCC_HSICFGR_HSITRIM_6                  (0x40UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x40000000 */
+
+
+/********************  Bit definition for RCC_CRRCR register  *****************/
+
+/*!< HSI48CAL configuration */
+#define RCC_CRRCR_HSI48CAL_Pos                 (0U)
+#define RCC_CRRCR_HSI48CAL_Msk                 (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x000003FF */
+#define RCC_CRRCR_HSI48CAL                     RCC_CRRCR_HSI48CAL_Msk          /*!< HSI48CAL[9:0] bits */
+#define RCC_CRRCR_HSI48CAL_0                   (0x001UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000001 */
+#define RCC_CRRCR_HSI48CAL_1                   (0x002UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000002 */
+#define RCC_CRRCR_HSI48CAL_2                   (0x004UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000004 */
+#define RCC_CRRCR_HSI48CAL_3                   (0x008UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000008 */
+#define RCC_CRRCR_HSI48CAL_4                   (0x010UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000010 */
+#define RCC_CRRCR_HSI48CAL_5                   (0x020UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000020 */
+#define RCC_CRRCR_HSI48CAL_6                   (0x040UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000040 */
+#define RCC_CRRCR_HSI48CAL_7                   (0x080UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */
+#define RCC_CRRCR_HSI48CAL_8                   (0x100UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */
+#define RCC_CRRCR_HSI48CAL_9                   (0x200UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */
+
+
+/********************  Bit definition for RCC_CSICFGR register  *****************/
+/*!< CSICAL configuration */
+#define RCC_CSICFGR_CSICAL_Pos                 (0U)
+#define RCC_CSICFGR_CSICAL_Msk                 (0xFFUL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x000000FF */
+#define RCC_CSICFGR_CSICAL                     RCC_CSICFGR_CSICAL_Msk          /*!< CSICAL[7:0] bits */
+#define RCC_CSICFGR_CSICAL_0                   (0x01UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000001 */
+#define RCC_CSICFGR_CSICAL_1                   (0x02UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000002 */
+#define RCC_CSICFGR_CSICAL_2                   (0x04UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000004 */
+#define RCC_CSICFGR_CSICAL_3                   (0x08UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000008 */
+#define RCC_CSICFGR_CSICAL_4                   (0x10UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000010 */
+#define RCC_CSICFGR_CSICAL_5                   (0x20UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000020 */
+#define RCC_CSICFGR_CSICAL_6                   (0x40UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000040 */
+#define RCC_CSICFGR_CSICAL_7                   (0x80UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000080 */
+
+/*!< CSITRIM configuration */
+#define RCC_CSICFGR_CSITRIM_Pos                (24U)
+#define RCC_CSICFGR_CSITRIM_Msk                (0x3FUL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x3F000000 */
+#define RCC_CSICFGR_CSITRIM                    RCC_CSICFGR_CSITRIM_Msk         /*!< CSITRIM[5:0] bits */
+#define RCC_CSICFGR_CSITRIM_0                  (0x01UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x01000000 */
+#define RCC_CSICFGR_CSITRIM_1                  (0x02UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x02000000 */
+#define RCC_CSICFGR_CSITRIM_2                  (0x04UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x04000000 */
+#define RCC_CSICFGR_CSITRIM_3                  (0x08UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x08000000 */
+#define RCC_CSICFGR_CSITRIM_4                  (0x10UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x10000000 */
+#define RCC_CSICFGR_CSITRIM_5                  (0x20UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x20000000 */
+
+/********************  Bit definition for RCC_CFGR register  ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos                        (0U)
+#define RCC_CFGR_SW_Msk                        (0x7UL << RCC_CFGR_SW_Pos)           /*!< 0x00000007 */
+#define RCC_CFGR_SW                            RCC_CFGR_SW_Msk                     /*!< SW[2:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0                          (0x1UL << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */
+#define RCC_CFGR_SW_1                          (0x2UL << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */
+#define RCC_CFGR_SW_2                          (0x4UL << RCC_CFGR_SW_Pos)           /*!< 0x00000004 */
+
+#define RCC_CFGR_SW_HSI                        (0x00000000UL)                       /*!< HSI selection as system clock */
+#define RCC_CFGR_SW_CSI                        (0x00000001UL)                       /*!< CSI selection as system clock */
+#define RCC_CFGR_SW_HSE                        (0x00000002UL)                       /*!< HSE selection as system clock */
+#define RCC_CFGR_SW_PLL1                       (0x00000003UL)                       /*!< PLL1 selection as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos                       (3U)
+#define RCC_CFGR_SWS_Msk                       (0x7UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000038 */
+#define RCC_CFGR_SWS                           RCC_CFGR_SWS_Msk                    /*!< SWS[2:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0                         (0x1UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */
+#define RCC_CFGR_SWS_1                         (0x2UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000010 */
+#define RCC_CFGR_SWS_2                         (0x4UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000020 */
+
+#define RCC_CFGR_SWS_HSI                       (0x00000000UL)                       /*!< HSI used as system clock */
+#define RCC_CFGR_SWS_CSI                       (0x00000008UL)                       /*!< CSI used as system clock */
+#define RCC_CFGR_SWS_HSE                       (0x00000010UL)                       /*!< HSE used as system clock */
+#define RCC_CFGR_SWS_PLL1                      (0x00000018UL)                       /*!< PLL1 used as system clock */
+
+#define RCC_CFGR_STOPWUCK_Pos                  (6U)
+#define RCC_CFGR_STOPWUCK_Msk                  (0x1UL << RCC_CFGR_STOPWUCK_Pos)     /*!< 0x00000040 */
+#define RCC_CFGR_STOPWUCK                      RCC_CFGR_STOPWUCK_Msk                /*!< Wake Up from stop and CSS backup clock selection */
+
+#define RCC_CFGR_STOPKERWUCK_Pos               (7U)
+#define RCC_CFGR_STOPKERWUCK_Msk               (0x1UL << RCC_CFGR_STOPKERWUCK_Pos)  /*!< 0x00000080 */
+#define RCC_CFGR_STOPKERWUCK                   RCC_CFGR_STOPKERWUCK_Msk             /*!< Kernel Clock Selection after a Wake Up from STOP */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE_Pos                    (8U)
+#define RCC_CFGR_RTCPRE_Msk                    (0x3FUL << RCC_CFGR_RTCPRE_Pos)
+#define RCC_CFGR_RTCPRE                        RCC_CFGR_RTCPRE_Msk                  /*!< 0x00003F00 */
+#define RCC_CFGR_RTCPRE_0                      (0x1UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000100 */
+#define RCC_CFGR_RTCPRE_1                      (0x2UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000200 */
+#define RCC_CFGR_RTCPRE_2                      (0x4UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000400 */
+#define RCC_CFGR_RTCPRE_3                      (0x8UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000800 */
+#define RCC_CFGR_RTCPRE_4                      (0x10UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00001000 */
+#define RCC_CFGR_RTCPRE_5                      (0x20UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00002000 */
+
+/*!< HRTIMSEL configuration */
+#define RCC_CFGR_HRTIMSEL_Pos                  (14U)
+#define RCC_CFGR_HRTIMSEL_Msk                  (0x1UL << RCC_CFGR_HRTIMSEL_Pos)
+#define RCC_CFGR_HRTIMSEL                      RCC_CFGR_HRTIMSEL_Msk                /*!< 0x00004000 */
+
+/*!< TIMPRE configuration */
+#define RCC_CFGR_TIMPRE_Pos                    (15U)
+#define RCC_CFGR_TIMPRE_Msk                    (0x1UL << RCC_CFGR_TIMPRE_Pos)
+#define RCC_CFGR_TIMPRE                        RCC_CFGR_TIMPRE_Msk                  /*!< 0x00008000 */
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1_Pos                      (22U)
+#define RCC_CFGR_MCO1_Msk                      (0x7UL << RCC_CFGR_MCO1_Pos)
+#define RCC_CFGR_MCO1                          RCC_CFGR_MCO1_Msk                       /*!< 0x01C00000 */
+#define RCC_CFGR_MCO1_0                        (0x1UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00400000 */
+#define RCC_CFGR_MCO1_1                        (0x2UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00800000 */
+#define RCC_CFGR_MCO1_2                        (0x4UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x01000000 */
+
+#define RCC_CFGR_MCO1PRE_Pos                   (18U)
+#define RCC_CFGR_MCO1PRE_Msk                   (0xFUL << RCC_CFGR_MCO1PRE_Pos)
+#define RCC_CFGR_MCO1PRE                       RCC_CFGR_MCO1PRE_Msk                    /*!< 0x003C0000 */
+#define RCC_CFGR_MCO1PRE_0                     (0x1UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00040000 */
+#define RCC_CFGR_MCO1PRE_1                     (0x2UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00080000 */
+#define RCC_CFGR_MCO1PRE_2                     (0x4UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00100000 */
+#define RCC_CFGR_MCO1PRE_3                     (0x8UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00200000 */
+
+#define RCC_CFGR_MCO2PRE_Pos                   (25U)
+#define RCC_CFGR_MCO2PRE_Msk                   (0xFUL << RCC_CFGR_MCO2PRE_Pos)
+#define RCC_CFGR_MCO2PRE                       RCC_CFGR_MCO2PRE_Msk                    /*!< 0x1E000000 */
+#define RCC_CFGR_MCO2PRE_0                     (0x1UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x02000000 */
+#define RCC_CFGR_MCO2PRE_1                     (0x2UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x04000000 */
+#define RCC_CFGR_MCO2PRE_2                     (0x4UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x08000000 */
+#define RCC_CFGR_MCO2PRE_3                     (0x8UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x10000000 */
+
+#define RCC_CFGR_MCO2_Pos                      (29U)
+#define RCC_CFGR_MCO2_Msk                      (0x7UL << RCC_CFGR_MCO2_Pos)
+#define RCC_CFGR_MCO2                          RCC_CFGR_MCO2_Msk                       /*!< 0xE0000000 */
+#define RCC_CFGR_MCO2_0                        (0x1UL << RCC_CFGR_MCO2_Pos)             /*!< 0x20000000 */
+#define RCC_CFGR_MCO2_1                        (0x2UL << RCC_CFGR_MCO2_Pos)             /*!< 0x40000000 */
+#define RCC_CFGR_MCO2_2                        (0x4UL << RCC_CFGR_MCO2_Pos)             /*!< 0x80000000 */
+
+/********************  Bit definition for RCC_D1CFGR register  ******************/
+/*!< D1HPRE configuration */
+#define RCC_D1CFGR_HPRE_Pos                    (0U)
+#define RCC_D1CFGR_HPRE_Msk                    (0xFUL << RCC_D1CFGR_HPRE_Pos)  /*!< 0x0000000F */
+#define RCC_D1CFGR_HPRE                        RCC_D1CFGR_HPRE_Msk             /*!< HPRE[3:0] bits (AHB3 prescaler) */
+#define RCC_D1CFGR_HPRE_0                      (0x1UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000001 */
+#define RCC_D1CFGR_HPRE_1                      (0x2UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000002 */
+#define RCC_D1CFGR_HPRE_2                      (0x4UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000004 */
+#define RCC_D1CFGR_HPRE_3                      (0x8UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000008 */
+
+
+#define RCC_D1CFGR_HPRE_DIV1                   ((uint32_t)0x00000000)          /*!< AHB3 Clock not divided */
+#define RCC_D1CFGR_HPRE_DIV2_Pos               (3U)
+#define RCC_D1CFGR_HPRE_DIV2_Msk               (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */
+#define RCC_D1CFGR_HPRE_DIV2                   RCC_D1CFGR_HPRE_DIV2_Msk        /*!< AHB3 Clock divided by 2 */
+#define RCC_D1CFGR_HPRE_DIV4_Pos               (0U)
+#define RCC_D1CFGR_HPRE_DIV4_Msk               (0x9UL << RCC_D1CFGR_HPRE_DIV4_Pos) /*!< 0x00000009 */
+#define RCC_D1CFGR_HPRE_DIV4                   RCC_D1CFGR_HPRE_DIV4_Msk        /*!< AHB3 Clock divided by 4 */
+#define RCC_D1CFGR_HPRE_DIV8_Pos               (1U)
+#define RCC_D1CFGR_HPRE_DIV8_Msk               (0x5UL << RCC_D1CFGR_HPRE_DIV8_Pos) /*!< 0x0000000A */
+#define RCC_D1CFGR_HPRE_DIV8                   RCC_D1CFGR_HPRE_DIV8_Msk        /*!< AHB3 Clock divided by 8 */
+#define RCC_D1CFGR_HPRE_DIV16_Pos              (0U)
+#define RCC_D1CFGR_HPRE_DIV16_Msk              (0xBUL << RCC_D1CFGR_HPRE_DIV16_Pos) /*!< 0x0000000B */
+#define RCC_D1CFGR_HPRE_DIV16                  RCC_D1CFGR_HPRE_DIV16_Msk       /*!< AHB3 Clock divided by 16 */
+#define RCC_D1CFGR_HPRE_DIV64_Pos              (2U)
+#define RCC_D1CFGR_HPRE_DIV64_Msk              (0x3UL << RCC_D1CFGR_HPRE_DIV64_Pos) /*!< 0x0000000C */
+#define RCC_D1CFGR_HPRE_DIV64                  RCC_D1CFGR_HPRE_DIV64_Msk       /*!< AHB3 Clock divided by 64 */
+#define RCC_D1CFGR_HPRE_DIV128_Pos             (0U)
+#define RCC_D1CFGR_HPRE_DIV128_Msk             (0xDUL << RCC_D1CFGR_HPRE_DIV128_Pos) /*!< 0x0000000D */
+#define RCC_D1CFGR_HPRE_DIV128                 RCC_D1CFGR_HPRE_DIV128_Msk      /*!< AHB3 Clock divided by 128 */
+#define RCC_D1CFGR_HPRE_DIV256_Pos             (1U)
+#define RCC_D1CFGR_HPRE_DIV256_Msk             (0x7UL << RCC_D1CFGR_HPRE_DIV256_Pos) /*!< 0x0000000E */
+#define RCC_D1CFGR_HPRE_DIV256                 RCC_D1CFGR_HPRE_DIV256_Msk      /*!< AHB3 Clock divided by 256 */
+#define RCC_D1CFGR_HPRE_DIV512_Pos             (0U)
+#define RCC_D1CFGR_HPRE_DIV512_Msk             (0xFUL << RCC_D1CFGR_HPRE_DIV512_Pos) /*!< 0x0000000F */
+#define RCC_D1CFGR_HPRE_DIV512                 RCC_D1CFGR_HPRE_DIV512_Msk      /*!< AHB3 Clock divided by 512 */
+
+/*!< D1PPRE configuration */
+#define RCC_D1CFGR_D1PPRE_Pos                  (4U)
+#define RCC_D1CFGR_D1PPRE_Msk                  (0x7UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000070 */
+#define RCC_D1CFGR_D1PPRE                      RCC_D1CFGR_D1PPRE_Msk           /*!< D1PRE[2:0] bits (APB3 prescaler) */
+#define RCC_D1CFGR_D1PPRE_0                    (0x1UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000010 */
+#define RCC_D1CFGR_D1PPRE_1                    (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */
+#define RCC_D1CFGR_D1PPRE_2                    (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */
+
+#define RCC_D1CFGR_D1PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB3 clock not divided */
+#define RCC_D1CFGR_D1PPRE_DIV2_Pos             (6U)
+#define RCC_D1CFGR_D1PPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */
+#define RCC_D1CFGR_D1PPRE_DIV2                 RCC_D1CFGR_D1PPRE_DIV2_Msk      /*!< APB3 clock divided by 2 */
+#define RCC_D1CFGR_D1PPRE_DIV4_Pos             (4U)
+#define RCC_D1CFGR_D1PPRE_DIV4_Msk             (0x5UL << RCC_D1CFGR_D1PPRE_DIV4_Pos) /*!< 0x00000050 */
+#define RCC_D1CFGR_D1PPRE_DIV4                 RCC_D1CFGR_D1PPRE_DIV4_Msk      /*!< APB3 clock divided by 4 */
+#define RCC_D1CFGR_D1PPRE_DIV8_Pos             (5U)
+#define RCC_D1CFGR_D1PPRE_DIV8_Msk             (0x3UL << RCC_D1CFGR_D1PPRE_DIV8_Pos) /*!< 0x00000060 */
+#define RCC_D1CFGR_D1PPRE_DIV8                 RCC_D1CFGR_D1PPRE_DIV8_Msk      /*!< APB3 clock divided by 8 */
+#define RCC_D1CFGR_D1PPRE_DIV16_Pos            (4U)
+#define RCC_D1CFGR_D1PPRE_DIV16_Msk            (0x7UL << RCC_D1CFGR_D1PPRE_DIV16_Pos) /*!< 0x00000070 */
+#define RCC_D1CFGR_D1PPRE_DIV16                RCC_D1CFGR_D1PPRE_DIV16_Msk     /*!< APB3 clock divided by 16 */
+
+#define RCC_D1CFGR_D1CPRE_Pos                  (8U)
+#define RCC_D1CFGR_D1CPRE_Msk                  (0xFUL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000F00 */
+#define RCC_D1CFGR_D1CPRE                      RCC_D1CFGR_D1CPRE_Msk           /*!< D1CPRE[2:0] bits (Domain 1 Core prescaler) */
+#define RCC_D1CFGR_D1CPRE_0                    (0x1UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000100 */
+#define RCC_D1CFGR_D1CPRE_1                    (0x2UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000200 */
+#define RCC_D1CFGR_D1CPRE_2                    (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */
+#define RCC_D1CFGR_D1CPRE_3                    (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */
+
+#define RCC_D1CFGR_D1CPRE_DIV1                 ((uint32_t)0x00000000)          /*!< Domain 1 Core clock not divided */
+#define RCC_D1CFGR_D1CPRE_DIV2_Pos             (11U)
+#define RCC_D1CFGR_D1CPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */
+#define RCC_D1CFGR_D1CPRE_DIV2                 RCC_D1CFGR_D1CPRE_DIV2_Msk      /*!< Domain 1 Core clock divided by 2 */
+#define RCC_D1CFGR_D1CPRE_DIV4_Pos             (8U)
+#define RCC_D1CFGR_D1CPRE_DIV4_Msk             (0x9UL << RCC_D1CFGR_D1CPRE_DIV4_Pos) /*!< 0x00000900 */
+#define RCC_D1CFGR_D1CPRE_DIV4                 RCC_D1CFGR_D1CPRE_DIV4_Msk      /*!< Domain 1 Core clock divided by 4 */
+#define RCC_D1CFGR_D1CPRE_DIV8_Pos             (9U)
+#define RCC_D1CFGR_D1CPRE_DIV8_Msk             (0x5UL << RCC_D1CFGR_D1CPRE_DIV8_Pos) /*!< 0x00000A00 */
+#define RCC_D1CFGR_D1CPRE_DIV8                 RCC_D1CFGR_D1CPRE_DIV8_Msk      /*!< Domain 1 Core clock divided by 8 */
+#define RCC_D1CFGR_D1CPRE_DIV16_Pos            (8U)
+#define RCC_D1CFGR_D1CPRE_DIV16_Msk            (0xBUL << RCC_D1CFGR_D1CPRE_DIV16_Pos) /*!< 0x00000B00 */
+#define RCC_D1CFGR_D1CPRE_DIV16                RCC_D1CFGR_D1CPRE_DIV16_Msk     /*!< Domain 1 Core clock divided by 16 */
+#define RCC_D1CFGR_D1CPRE_DIV64_Pos            (10U)
+#define RCC_D1CFGR_D1CPRE_DIV64_Msk            (0x3UL << RCC_D1CFGR_D1CPRE_DIV64_Pos) /*!< 0x00000C00 */
+#define RCC_D1CFGR_D1CPRE_DIV64                RCC_D1CFGR_D1CPRE_DIV64_Msk     /*!< Domain 1 Core clock divided by 64 */
+#define RCC_D1CFGR_D1CPRE_DIV128_Pos           (8U)
+#define RCC_D1CFGR_D1CPRE_DIV128_Msk           (0xDUL << RCC_D1CFGR_D1CPRE_DIV128_Pos) /*!< 0x00000D00 */
+#define RCC_D1CFGR_D1CPRE_DIV128               RCC_D1CFGR_D1CPRE_DIV128_Msk    /*!< Domain 1 Core clock divided by 128 */
+#define RCC_D1CFGR_D1CPRE_DIV256_Pos           (9U)
+#define RCC_D1CFGR_D1CPRE_DIV256_Msk           (0x7UL << RCC_D1CFGR_D1CPRE_DIV256_Pos) /*!< 0x00000E00 */
+#define RCC_D1CFGR_D1CPRE_DIV256               RCC_D1CFGR_D1CPRE_DIV256_Msk    /*!< Domain 1 Core clock divided by 256 */
+#define RCC_D1CFGR_D1CPRE_DIV512_Pos           (8U)
+#define RCC_D1CFGR_D1CPRE_DIV512_Msk           (0xFUL << RCC_D1CFGR_D1CPRE_DIV512_Pos) /*!< 0x00000F00 */
+#define RCC_D1CFGR_D1CPRE_DIV512               RCC_D1CFGR_D1CPRE_DIV512_Msk    /*!< Domain 1 Core clock divided by 512 */
+
+/********************  Bit definition for RCC_D2CFGR register  ******************/
+/*!< D2PPRE1 configuration */
+#define RCC_D2CFGR_D2PPRE1_Pos                 (4U)
+#define RCC_D2CFGR_D2PPRE1_Msk                 (0x7UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000070 */
+#define RCC_D2CFGR_D2PPRE1                     RCC_D2CFGR_D2PPRE1_Msk          /*!< D1PPRE1[2:0] bits (APB1 prescaler) */
+#define RCC_D2CFGR_D2PPRE1_0                   (0x1UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000010 */
+#define RCC_D2CFGR_D2PPRE1_1                   (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */
+#define RCC_D2CFGR_D2PPRE1_2                   (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */
+
+#define RCC_D2CFGR_D2PPRE1_DIV1                ((uint32_t)0x00000000)          /*!< APB1 clock not divided */
+#define RCC_D2CFGR_D2PPRE1_DIV2_Pos            (6U)
+#define RCC_D2CFGR_D2PPRE1_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */
+#define RCC_D2CFGR_D2PPRE1_DIV2                RCC_D2CFGR_D2PPRE1_DIV2_Msk     /*!< APB1 clock divided by 2 */
+#define RCC_D2CFGR_D2PPRE1_DIV4_Pos            (4U)
+#define RCC_D2CFGR_D2PPRE1_DIV4_Msk            (0x5UL << RCC_D2CFGR_D2PPRE1_DIV4_Pos) /*!< 0x00000050 */
+#define RCC_D2CFGR_D2PPRE1_DIV4                RCC_D2CFGR_D2PPRE1_DIV4_Msk     /*!< APB1 clock divided by 4 */
+#define RCC_D2CFGR_D2PPRE1_DIV8_Pos            (5U)
+#define RCC_D2CFGR_D2PPRE1_DIV8_Msk            (0x3UL << RCC_D2CFGR_D2PPRE1_DIV8_Pos) /*!< 0x00000060 */
+#define RCC_D2CFGR_D2PPRE1_DIV8                RCC_D2CFGR_D2PPRE1_DIV8_Msk     /*!< APB1 clock divided by 8 */
+#define RCC_D2CFGR_D2PPRE1_DIV16_Pos           (4U)
+#define RCC_D2CFGR_D2PPRE1_DIV16_Msk           (0x7UL << RCC_D2CFGR_D2PPRE1_DIV16_Pos) /*!< 0x00000070 */
+#define RCC_D2CFGR_D2PPRE1_DIV16               RCC_D2CFGR_D2PPRE1_DIV16_Msk    /*!< APB1 clock divided by 16 */
+
+/*!< D2PPRE2 configuration */
+#define RCC_D2CFGR_D2PPRE2_Pos                 (8U)
+#define RCC_D2CFGR_D2PPRE2_Msk                 (0x7UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000700 */
+#define RCC_D2CFGR_D2PPRE2                     RCC_D2CFGR_D2PPRE2_Msk          /*!< D2PPRE2[2:0] bits (APB2 prescaler) */
+#define RCC_D2CFGR_D2PPRE2_0                   (0x1UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000100 */
+#define RCC_D2CFGR_D2PPRE2_1                   (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */
+#define RCC_D2CFGR_D2PPRE2_2                   (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */
+
+#define RCC_D2CFGR_D2PPRE2_DIV1                ((uint32_t)0x00000000)          /*!< APB2 clock not divided */
+#define RCC_D2CFGR_D2PPRE2_DIV2_Pos            (10U)
+#define RCC_D2CFGR_D2PPRE2_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */
+#define RCC_D2CFGR_D2PPRE2_DIV2                RCC_D2CFGR_D2PPRE2_DIV2_Msk     /*!< APB2 clock divided by 2 */
+#define RCC_D2CFGR_D2PPRE2_DIV4_Pos            (8U)
+#define RCC_D2CFGR_D2PPRE2_DIV4_Msk            (0x5UL << RCC_D2CFGR_D2PPRE2_DIV4_Pos) /*!< 0x00000500 */
+#define RCC_D2CFGR_D2PPRE2_DIV4                RCC_D2CFGR_D2PPRE2_DIV4_Msk     /*!< APB2 clock divided by 4 */
+#define RCC_D2CFGR_D2PPRE2_DIV8_Pos            (9U)
+#define RCC_D2CFGR_D2PPRE2_DIV8_Msk            (0x3UL << RCC_D2CFGR_D2PPRE2_DIV8_Pos) /*!< 0x00000600 */
+#define RCC_D2CFGR_D2PPRE2_DIV8                RCC_D2CFGR_D2PPRE2_DIV8_Msk     /*!< APB2 clock divided by 8 */
+#define RCC_D2CFGR_D2PPRE2_DIV16_Pos           (8U)
+#define RCC_D2CFGR_D2PPRE2_DIV16_Msk           (0x7UL << RCC_D2CFGR_D2PPRE2_DIV16_Pos) /*!< 0x00000700 */
+#define RCC_D2CFGR_D2PPRE2_DIV16               RCC_D2CFGR_D2PPRE2_DIV16_Msk    /*!< APB2 clock divided by 16 */
+
+/********************  Bit definition for RCC_D3CFGR register  ******************/
+/*!< D3PPRE configuration */
+#define RCC_D3CFGR_D3PPRE_Pos                  (4U)
+#define RCC_D3CFGR_D3PPRE_Msk                  (0x7UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000070 */
+#define RCC_D3CFGR_D3PPRE                      RCC_D3CFGR_D3PPRE_Msk           /*!< D3PPRE1[2:0] bits (APB4 prescaler) */
+#define RCC_D3CFGR_D3PPRE_0                    (0x1UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000010 */
+#define RCC_D3CFGR_D3PPRE_1                    (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */
+#define RCC_D3CFGR_D3PPRE_2                    (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */
+
+#define RCC_D3CFGR_D3PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB4 clock not divided */
+#define RCC_D3CFGR_D3PPRE_DIV2_Pos             (6U)
+#define RCC_D3CFGR_D3PPRE_DIV2_Msk             (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */
+#define RCC_D3CFGR_D3PPRE_DIV2                 RCC_D3CFGR_D3PPRE_DIV2_Msk      /*!< APB4 clock divided by 2 */
+#define RCC_D3CFGR_D3PPRE_DIV4_Pos             (4U)
+#define RCC_D3CFGR_D3PPRE_DIV4_Msk             (0x5UL << RCC_D3CFGR_D3PPRE_DIV4_Pos) /*!< 0x00000050 */
+#define RCC_D3CFGR_D3PPRE_DIV4                 RCC_D3CFGR_D3PPRE_DIV4_Msk      /*!< APB4 clock divided by 4 */
+#define RCC_D3CFGR_D3PPRE_DIV8_Pos             (5U)
+#define RCC_D3CFGR_D3PPRE_DIV8_Msk             (0x3UL << RCC_D3CFGR_D3PPRE_DIV8_Pos) /*!< 0x00000060 */
+#define RCC_D3CFGR_D3PPRE_DIV8                 RCC_D3CFGR_D3PPRE_DIV8_Msk      /*!< APB4 clock divided by 8 */
+#define RCC_D3CFGR_D3PPRE_DIV16_Pos            (4U)
+#define RCC_D3CFGR_D3PPRE_DIV16_Msk            (0x7UL << RCC_D3CFGR_D3PPRE_DIV16_Pos) /*!< 0x00000070 */
+#define RCC_D3CFGR_D3PPRE_DIV16                RCC_D3CFGR_D3PPRE_DIV16_Msk     /*!< APB4 clock divided by 16 */
+
+/********************  Bit definition for RCC_PLLCKSELR register  *************/
+
+#define RCC_PLLCKSELR_PLLSRC_Pos               (0U)
+#define RCC_PLLCKSELR_PLLSRC_Msk               (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
+#define RCC_PLLCKSELR_PLLSRC                   RCC_PLLCKSELR_PLLSRC_Msk
+
+#define RCC_PLLCKSELR_PLLSRC_HSI               ((uint32_t)0x00000000)          /*!< HSI source clock selected */
+#define RCC_PLLCKSELR_PLLSRC_CSI_Pos           (0U)
+#define RCC_PLLCKSELR_PLLSRC_CSI_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
+#define RCC_PLLCKSELR_PLLSRC_CSI               RCC_PLLCKSELR_PLLSRC_CSI_Msk    /*!< CSI source clock selected */
+#define RCC_PLLCKSELR_PLLSRC_HSE_Pos           (1U)
+#define RCC_PLLCKSELR_PLLSRC_HSE_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_HSE_Pos) /*!< 0x00000002 */
+#define RCC_PLLCKSELR_PLLSRC_HSE               RCC_PLLCKSELR_PLLSRC_HSE_Msk    /*!< HSE source clock selected */
+#define RCC_PLLCKSELR_PLLSRC_NONE_Pos          (0U)
+#define RCC_PLLCKSELR_PLLSRC_NONE_Msk          (0x3UL << RCC_PLLCKSELR_PLLSRC_NONE_Pos) /*!< 0x00000003 */
+#define RCC_PLLCKSELR_PLLSRC_NONE              RCC_PLLCKSELR_PLLSRC_NONE_Msk   /*!< No source clock selected  */
+
+#define RCC_PLLCKSELR_DIVM1_Pos                (4U)
+#define RCC_PLLCKSELR_DIVM1_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x000003F0 */
+#define RCC_PLLCKSELR_DIVM1                    RCC_PLLCKSELR_DIVM1_Msk
+#define RCC_PLLCKSELR_DIVM1_0                  (0x01UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000010 */
+#define RCC_PLLCKSELR_DIVM1_1                  (0x02UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000020 */
+#define RCC_PLLCKSELR_DIVM1_2                  (0x04UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000040 */
+#define RCC_PLLCKSELR_DIVM1_3                  (0x08UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000080 */
+#define RCC_PLLCKSELR_DIVM1_4                  (0x10UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000100 */
+#define RCC_PLLCKSELR_DIVM1_5                  (0x20UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000200 */
+
+#define RCC_PLLCKSELR_DIVM2_Pos                (12U)
+#define RCC_PLLCKSELR_DIVM2_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x0003F000 */
+#define RCC_PLLCKSELR_DIVM2                    RCC_PLLCKSELR_DIVM2_Msk
+#define RCC_PLLCKSELR_DIVM2_0                  (0x01UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00001000 */
+#define RCC_PLLCKSELR_DIVM2_1                  (0x02UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00002000 */
+#define RCC_PLLCKSELR_DIVM2_2                  (0x04UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00004000 */
+#define RCC_PLLCKSELR_DIVM2_3                  (0x08UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00008000 */
+#define RCC_PLLCKSELR_DIVM2_4                  (0x10UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00010000 */
+#define RCC_PLLCKSELR_DIVM2_5                  (0x20UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00020000 */
+
+#define RCC_PLLCKSELR_DIVM3_Pos                (20U)
+#define RCC_PLLCKSELR_DIVM3_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x03F00000 */
+#define RCC_PLLCKSELR_DIVM3                    RCC_PLLCKSELR_DIVM3_Msk
+#define RCC_PLLCKSELR_DIVM3_0                  (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00100000 */
+#define RCC_PLLCKSELR_DIVM3_1                  (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00200000 */
+#define RCC_PLLCKSELR_DIVM3_2                  (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00400000 */
+#define RCC_PLLCKSELR_DIVM3_3                  (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00800000 */
+#define RCC_PLLCKSELR_DIVM3_4                  (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x01000000 */
+#define RCC_PLLCKSELR_DIVM3_5                  (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 */
+
+/********************  Bit definition for RCC_PLLCFGR register  ***************/
+
+#define RCC_PLLCFGR_PLL1FRACEN_Pos             (0U)
+#define RCC_PLLCFGR_PLL1FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos) /*!< 0x00000001 */
+#define RCC_PLLCFGR_PLL1FRACEN                 RCC_PLLCFGR_PLL1FRACEN_Msk
+#define RCC_PLLCFGR_PLL1VCOSEL_Pos             (1U)
+#define RCC_PLLCFGR_PLL1VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos) /*!< 0x00000002 */
+#define RCC_PLLCFGR_PLL1VCOSEL                 RCC_PLLCFGR_PLL1VCOSEL_Msk
+#define RCC_PLLCFGR_PLL1RGE_Pos                (2U)
+#define RCC_PLLCFGR_PLL1RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
+#define RCC_PLLCFGR_PLL1RGE                    RCC_PLLCFGR_PLL1RGE_Msk
+#define RCC_PLLCFGR_PLL1RGE_0                  (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */
+#define RCC_PLLCFGR_PLL1RGE_1                  (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */
+#define RCC_PLLCFGR_PLL1RGE_2                  (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */
+#define RCC_PLLCFGR_PLL1RGE_3                  (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
+
+#define RCC_PLLCFGR_PLL2FRACEN_Pos             (4U)
+#define RCC_PLLCFGR_PLL2FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos) /*!< 0x00000010 */
+#define RCC_PLLCFGR_PLL2FRACEN                 RCC_PLLCFGR_PLL2FRACEN_Msk
+#define RCC_PLLCFGR_PLL2VCOSEL_Pos             (5U)
+#define RCC_PLLCFGR_PLL2VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos) /*!< 0x00000020 */
+#define RCC_PLLCFGR_PLL2VCOSEL                 RCC_PLLCFGR_PLL2VCOSEL_Msk
+#define RCC_PLLCFGR_PLL2RGE_Pos                (6U)
+#define RCC_PLLCFGR_PLL2RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */
+#define RCC_PLLCFGR_PLL2RGE                    RCC_PLLCFGR_PLL2RGE_Msk
+#define RCC_PLLCFGR_PLL2RGE_0                  (0x0UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000000 */
+#define RCC_PLLCFGR_PLL2RGE_1                  (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000040 */
+#define RCC_PLLCFGR_PLL2RGE_2                  (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000080 */
+#define RCC_PLLCFGR_PLL2RGE_3                  (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */
+
+#define RCC_PLLCFGR_PLL3FRACEN_Pos             (8U)
+#define RCC_PLLCFGR_PLL3FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos) /*!< 0x00000100 */
+#define RCC_PLLCFGR_PLL3FRACEN                 RCC_PLLCFGR_PLL3FRACEN_Msk
+#define RCC_PLLCFGR_PLL3VCOSEL_Pos             (9U)
+#define RCC_PLLCFGR_PLL3VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos) /*!< 0x00000200 */
+#define RCC_PLLCFGR_PLL3VCOSEL                 RCC_PLLCFGR_PLL3VCOSEL_Msk
+#define RCC_PLLCFGR_PLL3RGE_Pos                (10U)
+#define RCC_PLLCFGR_PLL3RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */
+#define RCC_PLLCFGR_PLL3RGE                    RCC_PLLCFGR_PLL3RGE_Msk
+#define RCC_PLLCFGR_PLL3RGE_0                  (0x0UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000000 */
+#define RCC_PLLCFGR_PLL3RGE_1                  (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000400 */
+#define RCC_PLLCFGR_PLL3RGE_2                  (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000800 */
+#define RCC_PLLCFGR_PLL3RGE_3                  (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */
+
+#define RCC_PLLCFGR_DIVP1EN_Pos                (16U)
+#define RCC_PLLCFGR_DIVP1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP1EN_Pos) /*!< 0x00010000 */
+#define RCC_PLLCFGR_DIVP1EN                    RCC_PLLCFGR_DIVP1EN_Msk
+#define RCC_PLLCFGR_DIVQ1EN_Pos                (17U)
+#define RCC_PLLCFGR_DIVQ1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ1EN_Pos) /*!< 0x00020000 */
+#define RCC_PLLCFGR_DIVQ1EN                    RCC_PLLCFGR_DIVQ1EN_Msk
+#define RCC_PLLCFGR_DIVR1EN_Pos                (18U)
+#define RCC_PLLCFGR_DIVR1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR1EN_Pos) /*!< 0x00040000 */
+#define RCC_PLLCFGR_DIVR1EN                    RCC_PLLCFGR_DIVR1EN_Msk
+
+#define RCC_PLLCFGR_DIVP2EN_Pos                (19U)
+#define RCC_PLLCFGR_DIVP2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP2EN_Pos) /*!< 0x00080000 */
+#define RCC_PLLCFGR_DIVP2EN                    RCC_PLLCFGR_DIVP2EN_Msk
+#define RCC_PLLCFGR_DIVQ2EN_Pos                (20U)
+#define RCC_PLLCFGR_DIVQ2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ2EN_Pos) /*!< 0x00100000 */
+#define RCC_PLLCFGR_DIVQ2EN                    RCC_PLLCFGR_DIVQ2EN_Msk
+#define RCC_PLLCFGR_DIVR2EN_Pos                (21U)
+#define RCC_PLLCFGR_DIVR2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR2EN_Pos) /*!< 0x00200000 */
+#define RCC_PLLCFGR_DIVR2EN                    RCC_PLLCFGR_DIVR2EN_Msk
+
+#define RCC_PLLCFGR_DIVP3EN_Pos                (22U)
+#define RCC_PLLCFGR_DIVP3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP3EN_Pos) /*!< 0x00400000 */
+#define RCC_PLLCFGR_DIVP3EN                    RCC_PLLCFGR_DIVP3EN_Msk
+#define RCC_PLLCFGR_DIVQ3EN_Pos                (23U)
+#define RCC_PLLCFGR_DIVQ3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ3EN_Pos) /*!< 0x00800000 */
+#define RCC_PLLCFGR_DIVQ3EN                    RCC_PLLCFGR_DIVQ3EN_Msk
+#define RCC_PLLCFGR_DIVR3EN_Pos                (24U)
+#define RCC_PLLCFGR_DIVR3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR3EN_Pos) /*!< 0x01000000 */
+#define RCC_PLLCFGR_DIVR3EN                    RCC_PLLCFGR_DIVR3EN_Msk
+
+
+/********************  Bit definition for RCC_PLL1DIVR register  ***************/
+#define RCC_PLL1DIVR_N1_Pos                    (0U)
+#define RCC_PLL1DIVR_N1_Msk                    (0x1FFUL << RCC_PLL1DIVR_N1_Pos) /*!< 0x000001FF */
+#define RCC_PLL1DIVR_N1                        RCC_PLL1DIVR_N1_Msk
+#define RCC_PLL1DIVR_P1_Pos                    (9U)
+#define RCC_PLL1DIVR_P1_Msk                    (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */
+#define RCC_PLL1DIVR_P1                        RCC_PLL1DIVR_P1_Msk
+#define RCC_PLL1DIVR_Q1_Pos                    (16U)
+#define RCC_PLL1DIVR_Q1_Msk                    (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */
+#define RCC_PLL1DIVR_Q1                        RCC_PLL1DIVR_Q1_Msk
+#define RCC_PLL1DIVR_R1_Pos                    (24U)
+#define RCC_PLL1DIVR_R1_Msk                    (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
+#define RCC_PLL1DIVR_R1                        RCC_PLL1DIVR_R1_Msk
+
+/********************  Bit definition for RCC_PLL1FRACR register  ***************/
+#define RCC_PLL1FRACR_FRACN1_Pos               (3U)
+#define RCC_PLL1FRACR_FRACN1_Msk               (0x1FFFUL << RCC_PLL1FRACR_FRACN1_Pos) /*!< 0x0000FFF8 */
+#define RCC_PLL1FRACR_FRACN1                   RCC_PLL1FRACR_FRACN1_Msk
+
+/********************  Bit definition for RCC_PLL2DIVR register  ***************/
+#define RCC_PLL2DIVR_N2_Pos                    (0U)
+#define RCC_PLL2DIVR_N2_Msk                    (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */
+#define RCC_PLL2DIVR_N2                        RCC_PLL2DIVR_N2_Msk
+#define RCC_PLL2DIVR_P2_Pos                    (9U)
+#define RCC_PLL2DIVR_P2_Msk                    (0x7FUL << RCC_PLL2DIVR_P2_Pos) /*!< 0x0000FE00 */
+#define RCC_PLL2DIVR_P2                        RCC_PLL2DIVR_P2_Msk
+#define RCC_PLL2DIVR_Q2_Pos                    (16U)
+#define RCC_PLL2DIVR_Q2_Msk                    (0x7FUL << RCC_PLL2DIVR_Q2_Pos) /*!< 0x007F0000 */
+#define RCC_PLL2DIVR_Q2                        RCC_PLL2DIVR_Q2_Msk
+#define RCC_PLL2DIVR_R2_Pos                    (24U)
+#define RCC_PLL2DIVR_R2_Msk                    (0x7FUL << RCC_PLL2DIVR_R2_Pos) /*!< 0x7F000000 */
+#define RCC_PLL2DIVR_R2                        RCC_PLL2DIVR_R2_Msk
+
+/********************  Bit definition for RCC_PLL2FRACR register  ***************/
+#define RCC_PLL2FRACR_FRACN2_Pos               (3U)
+#define RCC_PLL2FRACR_FRACN2_Msk               (0x1FFFUL << RCC_PLL2FRACR_FRACN2_Pos) /*!< 0x0000FFF8 */
+#define RCC_PLL2FRACR_FRACN2                   RCC_PLL2FRACR_FRACN2_Msk
+
+/********************  Bit definition for RCC_PLL3DIVR register  ***************/
+#define RCC_PLL3DIVR_N3_Pos                    (0U)
+#define RCC_PLL3DIVR_N3_Msk                    (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */
+#define RCC_PLL3DIVR_N3                        RCC_PLL3DIVR_N3_Msk
+#define RCC_PLL3DIVR_P3_Pos                    (9U)
+#define RCC_PLL3DIVR_P3_Msk                    (0x7FUL << RCC_PLL3DIVR_P3_Pos) /*!< 0x0000FE00 */
+#define RCC_PLL3DIVR_P3                        RCC_PLL3DIVR_P3_Msk
+#define RCC_PLL3DIVR_Q3_Pos                    (16U)
+#define RCC_PLL3DIVR_Q3_Msk                    (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */
+#define RCC_PLL3DIVR_Q3                        RCC_PLL3DIVR_Q3_Msk
+#define RCC_PLL3DIVR_R3_Pos                    (24U)
+#define RCC_PLL3DIVR_R3_Msk                    (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */
+#define RCC_PLL3DIVR_R3                        RCC_PLL3DIVR_R3_Msk
+
+/********************  Bit definition for RCC_PLL3FRACR register  ***************/
+#define RCC_PLL3FRACR_FRACN3_Pos               (3U)
+#define RCC_PLL3FRACR_FRACN3_Msk               (0x1FFFUL << RCC_PLL3FRACR_FRACN3_Pos) /*!< 0x0000FFF8 */
+#define RCC_PLL3FRACR_FRACN3                   RCC_PLL3FRACR_FRACN3_Msk
+
+/********************  Bit definition for RCC_D1CCIPR register  ***************/
+#define RCC_D1CCIPR_FMCSEL_Pos                 (0U)
+#define RCC_D1CCIPR_FMCSEL_Msk                 (0x3UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000003 */
+#define RCC_D1CCIPR_FMCSEL                     RCC_D1CCIPR_FMCSEL_Msk
+#define RCC_D1CCIPR_FMCSEL_0                   (0x1UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000001 */
+#define RCC_D1CCIPR_FMCSEL_1                   (0x2UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000002 */
+#define RCC_D1CCIPR_QSPISEL_Pos                (4U)
+#define RCC_D1CCIPR_QSPISEL_Msk                (0x3UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000030 */
+#define RCC_D1CCIPR_QSPISEL                    RCC_D1CCIPR_QSPISEL_Msk
+#define RCC_D1CCIPR_QSPISEL_0                  (0x1UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000010 */
+#define RCC_D1CCIPR_QSPISEL_1                  (0x2UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000020 */
+#define RCC_D1CCIPR_SDMMCSEL_Pos               (16U)
+#define RCC_D1CCIPR_SDMMCSEL_Msk               (0x1UL << RCC_D1CCIPR_SDMMCSEL_Pos) /*!< 0x00010000 */
+#define RCC_D1CCIPR_SDMMCSEL                   RCC_D1CCIPR_SDMMCSEL_Msk
+#define RCC_D1CCIPR_CKPERSEL_Pos               (28U)
+#define RCC_D1CCIPR_CKPERSEL_Msk               (0x3UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x30000000 */
+#define RCC_D1CCIPR_CKPERSEL                   RCC_D1CCIPR_CKPERSEL_Msk
+#define RCC_D1CCIPR_CKPERSEL_0                 (0x1UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x10000000 */
+#define RCC_D1CCIPR_CKPERSEL_1                 (0x2UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x20000000 */
+
+/********************  Bit definition for RCC_D2CCIP1R register  ***************/
+#define RCC_D2CCIP1R_SAI1SEL_Pos               (0U)
+#define RCC_D2CCIP1R_SAI1SEL_Msk               (0x7UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000007 */
+#define RCC_D2CCIP1R_SAI1SEL                   RCC_D2CCIP1R_SAI1SEL_Msk
+#define RCC_D2CCIP1R_SAI1SEL_0                 (0x1UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000001 */
+#define RCC_D2CCIP1R_SAI1SEL_1                 (0x2UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000002 */
+#define RCC_D2CCIP1R_SAI1SEL_2                 (0x4UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000004 */
+
+#define RCC_D2CCIP1R_SAI23SEL_Pos              (6U)
+#define RCC_D2CCIP1R_SAI23SEL_Msk              (0x7UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x000001C0 */
+#define RCC_D2CCIP1R_SAI23SEL                  RCC_D2CCIP1R_SAI23SEL_Msk
+#define RCC_D2CCIP1R_SAI23SEL_0                (0x1UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000040 */
+#define RCC_D2CCIP1R_SAI23SEL_1                (0x2UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000080 */
+#define RCC_D2CCIP1R_SAI23SEL_2                (0x4UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000100 */
+
+#define RCC_D2CCIP1R_SPI123SEL_Pos             (12U)
+#define RCC_D2CCIP1R_SPI123SEL_Msk             (0x7UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00007000 */
+#define RCC_D2CCIP1R_SPI123SEL                 RCC_D2CCIP1R_SPI123SEL_Msk
+#define RCC_D2CCIP1R_SPI123SEL_0               (0x1UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00001000 */
+#define RCC_D2CCIP1R_SPI123SEL_1               (0x2UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00002000 */
+#define RCC_D2CCIP1R_SPI123SEL_2               (0x4UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00004000 */
+
+#define RCC_D2CCIP1R_SPI45SEL_Pos              (16U)
+#define RCC_D2CCIP1R_SPI45SEL_Msk              (0x7UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00070000 */
+#define RCC_D2CCIP1R_SPI45SEL                  RCC_D2CCIP1R_SPI45SEL_Msk
+#define RCC_D2CCIP1R_SPI45SEL_0                (0x1UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00010000 */
+#define RCC_D2CCIP1R_SPI45SEL_1                (0x2UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00020000 */
+#define RCC_D2CCIP1R_SPI45SEL_2                (0x4UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00040000 */
+
+#define RCC_D2CCIP1R_SPDIFSEL_Pos              (20U)
+#define RCC_D2CCIP1R_SPDIFSEL_Msk              (0x3UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00300000 */
+#define RCC_D2CCIP1R_SPDIFSEL                  RCC_D2CCIP1R_SPDIFSEL_Msk
+#define RCC_D2CCIP1R_SPDIFSEL_0                (0x1UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00100000 */
+#define RCC_D2CCIP1R_SPDIFSEL_1                (0x2UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00200000 */
+
+#define RCC_D2CCIP1R_DFSDM1SEL_Pos             (24U)
+#define RCC_D2CCIP1R_DFSDM1SEL_Msk             (0x1UL << RCC_D2CCIP1R_DFSDM1SEL_Pos) /*!< 0x01000000 */
+#define RCC_D2CCIP1R_DFSDM1SEL                 RCC_D2CCIP1R_DFSDM1SEL_Msk
+
+#define RCC_D2CCIP1R_FDCANSEL_Pos              (28U)
+#define RCC_D2CCIP1R_FDCANSEL_Msk              (0x3UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x30000000 */
+#define RCC_D2CCIP1R_FDCANSEL                  RCC_D2CCIP1R_FDCANSEL_Msk
+#define RCC_D2CCIP1R_FDCANSEL_0                (0x1UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x10000000 */
+#define RCC_D2CCIP1R_FDCANSEL_1                (0x2UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x20000000 */
+
+#define RCC_D2CCIP1R_SWPSEL_Pos                (31U)
+#define RCC_D2CCIP1R_SWPSEL_Msk                (0x1UL << RCC_D2CCIP1R_SWPSEL_Pos) /*!< 0x80000000 */
+#define RCC_D2CCIP1R_SWPSEL                    RCC_D2CCIP1R_SWPSEL_Msk
+
+/********************  Bit definition for RCC_D2CCIP2R register  ***************/
+#define RCC_D2CCIP2R_USART16SEL_Pos            (3U)
+#define RCC_D2CCIP2R_USART16SEL_Msk            (0x7UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000038 */
+#define RCC_D2CCIP2R_USART16SEL                RCC_D2CCIP2R_USART16SEL_Msk
+#define RCC_D2CCIP2R_USART16SEL_0              (0x1UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000008 */
+#define RCC_D2CCIP2R_USART16SEL_1              (0x2UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000010 */
+#define RCC_D2CCIP2R_USART16SEL_2              (0x4UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000020 */
+
+#define RCC_D2CCIP2R_USART28SEL_Pos            (0U)
+#define RCC_D2CCIP2R_USART28SEL_Msk            (0x7UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000007 */
+#define RCC_D2CCIP2R_USART28SEL                RCC_D2CCIP2R_USART28SEL_Msk
+#define RCC_D2CCIP2R_USART28SEL_0              (0x1UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000001 */
+#define RCC_D2CCIP2R_USART28SEL_1              (0x2UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000002 */
+#define RCC_D2CCIP2R_USART28SEL_2              (0x4UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000004 */
+
+#define RCC_D2CCIP2R_RNGSEL_Pos                (8U)
+#define RCC_D2CCIP2R_RNGSEL_Msk                (0x3UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000300 */
+#define RCC_D2CCIP2R_RNGSEL                    RCC_D2CCIP2R_RNGSEL_Msk
+#define RCC_D2CCIP2R_RNGSEL_0                  (0x1UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000100 */
+#define RCC_D2CCIP2R_RNGSEL_1                  (0x2UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000200 */
+
+#define RCC_D2CCIP2R_I2C123SEL_Pos             (12U)
+#define RCC_D2CCIP2R_I2C123SEL_Msk             (0x3UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00003000 */
+#define RCC_D2CCIP2R_I2C123SEL                 RCC_D2CCIP2R_I2C123SEL_Msk
+#define RCC_D2CCIP2R_I2C123SEL_0               (0x1UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00001000 */
+#define RCC_D2CCIP2R_I2C123SEL_1               (0x2UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00002000 */
+
+#define RCC_D2CCIP2R_USBSEL_Pos                (20U)
+#define RCC_D2CCIP2R_USBSEL_Msk                (0x3UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00300000 */
+#define RCC_D2CCIP2R_USBSEL                    RCC_D2CCIP2R_USBSEL_Msk
+#define RCC_D2CCIP2R_USBSEL_0                  (0x1UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00100000 */
+#define RCC_D2CCIP2R_USBSEL_1                  (0x2UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00200000 */
+
+#define RCC_D2CCIP2R_CECSEL_Pos                (22U)
+#define RCC_D2CCIP2R_CECSEL_Msk                (0x3UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00C00000 */
+#define RCC_D2CCIP2R_CECSEL                    RCC_D2CCIP2R_CECSEL_Msk
+#define RCC_D2CCIP2R_CECSEL_0                  (0x1UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00400000 */
+#define RCC_D2CCIP2R_CECSEL_1                  (0x2UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00800000 */
+
+#define RCC_D2CCIP2R_LPTIM1SEL_Pos             (28U)
+#define RCC_D2CCIP2R_LPTIM1SEL_Msk             (0x7UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x70000000 */
+#define RCC_D2CCIP2R_LPTIM1SEL                 RCC_D2CCIP2R_LPTIM1SEL_Msk
+#define RCC_D2CCIP2R_LPTIM1SEL_0               (0x1UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x10000000 */
+#define RCC_D2CCIP2R_LPTIM1SEL_1               (0x2UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x20000000 */
+#define RCC_D2CCIP2R_LPTIM1SEL_2               (0x4UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for RCC_D3CCIPR register  ***************/
+#define RCC_D3CCIPR_LPUART1SEL_Pos             (0U)
+#define RCC_D3CCIPR_LPUART1SEL_Msk             (0x7UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000007 */
+#define RCC_D3CCIPR_LPUART1SEL                 RCC_D3CCIPR_LPUART1SEL_Msk
+#define RCC_D3CCIPR_LPUART1SEL_0               (0x1UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000001 */
+#define RCC_D3CCIPR_LPUART1SEL_1               (0x2UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000002 */
+#define RCC_D3CCIPR_LPUART1SEL_2               (0x4UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000004 */
+
+#define RCC_D3CCIPR_I2C4SEL_Pos                (8U)
+#define RCC_D3CCIPR_I2C4SEL_Msk                (0x3UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000300 */
+#define RCC_D3CCIPR_I2C4SEL                    RCC_D3CCIPR_I2C4SEL_Msk
+#define RCC_D3CCIPR_I2C4SEL_0                  (0x1UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000100 */
+#define RCC_D3CCIPR_I2C4SEL_1                  (0x2UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000200 */
+
+#define RCC_D3CCIPR_LPTIM2SEL_Pos              (10U)
+#define RCC_D3CCIPR_LPTIM2SEL_Msk              (0x7UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001C00 */
+#define RCC_D3CCIPR_LPTIM2SEL                  RCC_D3CCIPR_LPTIM2SEL_Msk
+#define RCC_D3CCIPR_LPTIM2SEL_0                (0x1UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000400 */
+#define RCC_D3CCIPR_LPTIM2SEL_1                (0x2UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000800 */
+#define RCC_D3CCIPR_LPTIM2SEL_2                (0x4UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001000 */
+
+#define RCC_D3CCIPR_LPTIM345SEL_Pos            (13U)
+#define RCC_D3CCIPR_LPTIM345SEL_Msk            (0x7UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x0000E000 */
+#define RCC_D3CCIPR_LPTIM345SEL                RCC_D3CCIPR_LPTIM345SEL_Msk
+#define RCC_D3CCIPR_LPTIM345SEL_0              (0x1UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00002000 */
+#define RCC_D3CCIPR_LPTIM345SEL_1              (0x2UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00004000 */
+#define RCC_D3CCIPR_LPTIM345SEL_2              (0x4UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00008000 */
+
+#define RCC_D3CCIPR_SAI4ASEL_Pos               (21U)
+#define RCC_D3CCIPR_SAI4ASEL_Msk               (0x7UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00E00000 */
+#define RCC_D3CCIPR_SAI4ASEL                   RCC_D3CCIPR_SAI4ASEL_Msk
+#define RCC_D3CCIPR_SAI4ASEL_0                 (0x1UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00200000 */
+#define RCC_D3CCIPR_SAI4ASEL_1                 (0x2UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00400000 */
+#define RCC_D3CCIPR_SAI4ASEL_2                 (0x4UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00800000 */
+
+#define RCC_D3CCIPR_SAI4BSEL_Pos               (24U)
+#define RCC_D3CCIPR_SAI4BSEL_Msk               (0x7UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x07000000 */
+#define RCC_D3CCIPR_SAI4BSEL                   RCC_D3CCIPR_SAI4BSEL_Msk
+#define RCC_D3CCIPR_SAI4BSEL_0                 (0x1UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x01000000 */
+#define RCC_D3CCIPR_SAI4BSEL_1                 (0x2UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x02000000 */
+#define RCC_D3CCIPR_SAI4BSEL_2                 (0x4UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x04000000 */
+
+#define RCC_D3CCIPR_ADCSEL_Pos                 (16U)
+#define RCC_D3CCIPR_ADCSEL_Msk                 (0x3UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00030000 */
+#define RCC_D3CCIPR_ADCSEL                     RCC_D3CCIPR_ADCSEL_Msk
+#define RCC_D3CCIPR_ADCSEL_0                   (0x1UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00010000 */
+#define RCC_D3CCIPR_ADCSEL_1                   (0x2UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00020000 */
+
+#define RCC_D3CCIPR_SPI6SEL_Pos                (28U)
+#define RCC_D3CCIPR_SPI6SEL_Msk                (0x7UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x70000000 */
+#define RCC_D3CCIPR_SPI6SEL                    RCC_D3CCIPR_SPI6SEL_Msk
+#define RCC_D3CCIPR_SPI6SEL_0                  (0x1UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x10000000 */
+#define RCC_D3CCIPR_SPI6SEL_1                  (0x2UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x20000000 */
+#define RCC_D3CCIPR_SPI6SEL_2                  (0x4UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x40000000 */
+/********************  Bit definition for RCC_CIER register  ******************/
+#define RCC_CIER_LSIRDYIE_Pos                  (0U)
+#define RCC_CIER_LSIRDYIE_Msk                  (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
+#define RCC_CIER_LSIRDYIE                      RCC_CIER_LSIRDYIE_Msk
+#define RCC_CIER_LSERDYIE_Pos                  (1U)
+#define RCC_CIER_LSERDYIE_Msk                  (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
+#define RCC_CIER_LSERDYIE                      RCC_CIER_LSERDYIE_Msk
+#define RCC_CIER_HSIRDYIE_Pos                  (2U)
+#define RCC_CIER_HSIRDYIE_Msk                  (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
+#define RCC_CIER_HSIRDYIE                      RCC_CIER_HSIRDYIE_Msk
+#define RCC_CIER_HSERDYIE_Pos                  (3U)
+#define RCC_CIER_HSERDYIE_Msk                  (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
+#define RCC_CIER_HSERDYIE                      RCC_CIER_HSERDYIE_Msk
+#define RCC_CIER_CSIRDYIE_Pos                  (4U)
+#define RCC_CIER_CSIRDYIE_Msk                  (0x1UL << RCC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */
+#define RCC_CIER_CSIRDYIE                      RCC_CIER_CSIRDYIE_Msk
+#define RCC_CIER_HSI48RDYIE_Pos                (5U)
+#define RCC_CIER_HSI48RDYIE_Msk                (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000020 */
+#define RCC_CIER_HSI48RDYIE                    RCC_CIER_HSI48RDYIE_Msk
+#define RCC_CIER_PLL1RDYIE_Pos                 (6U)
+#define RCC_CIER_PLL1RDYIE_Msk                 (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000040 */
+#define RCC_CIER_PLL1RDYIE                     RCC_CIER_PLL1RDYIE_Msk
+#define RCC_CIER_PLL2RDYIE_Pos                 (7U)
+#define RCC_CIER_PLL2RDYIE_Msk                 (0x1UL << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000080 */
+#define RCC_CIER_PLL2RDYIE                     RCC_CIER_PLL2RDYIE_Msk
+#define RCC_CIER_PLL3RDYIE_Pos                 (8U)
+#define RCC_CIER_PLL3RDYIE_Msk                 (0x1UL << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000100 */
+#define RCC_CIER_PLL3RDYIE                     RCC_CIER_PLL3RDYIE_Msk
+#define RCC_CIER_LSECSSIE_Pos                  (9U)
+#define RCC_CIER_LSECSSIE_Msk                  (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */
+#define RCC_CIER_LSECSSIE                      RCC_CIER_LSECSSIE_Msk
+
+/********************  Bit definition for RCC_CIFR register  ******************/
+#define RCC_CIFR_LSIRDYF_Pos                   (0U)
+#define RCC_CIFR_LSIRDYF_Msk                   (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIFR_LSIRDYF                       RCC_CIFR_LSIRDYF_Msk
+#define RCC_CIFR_LSERDYF_Pos                   (1U)
+#define RCC_CIFR_LSERDYF_Msk                   (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIFR_LSERDYF                       RCC_CIFR_LSERDYF_Msk
+#define RCC_CIFR_HSIRDYF_Pos                   (2U)
+#define RCC_CIFR_HSIRDYF_Msk                   (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIFR_HSIRDYF                       RCC_CIFR_HSIRDYF_Msk
+#define RCC_CIFR_HSERDYF_Pos                   (3U)
+#define RCC_CIFR_HSERDYF_Msk                   (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIFR_HSERDYF                       RCC_CIFR_HSERDYF_Msk
+#define RCC_CIFR_CSIRDYF_Pos                   (4U)
+#define RCC_CIFR_CSIRDYF_Msk                   (0x1UL << RCC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIFR_CSIRDYF                       RCC_CIFR_CSIRDYF_Msk
+#define RCC_CIFR_HSI48RDYF_Pos                 (5U)
+#define RCC_CIFR_HSI48RDYF_Msk                 (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000020 */
+#define RCC_CIFR_HSI48RDYF                     RCC_CIFR_HSI48RDYF_Msk
+#define RCC_CIFR_PLLRDYF_Pos                   (6U)
+#define RCC_CIFR_PLLRDYF_Msk                   (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000040 */
+#define RCC_CIFR_PLLRDYF                       RCC_CIFR_PLLRDYF_Msk
+#define RCC_CIFR_PLL2RDYF_Pos                  (7U)
+#define RCC_CIFR_PLL2RDYF_Msk                  (0x1UL << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000080 */
+#define RCC_CIFR_PLL2RDYF                      RCC_CIFR_PLL2RDYF_Msk
+#define RCC_CIFR_PLL3RDYF_Pos                  (8U)
+#define RCC_CIFR_PLL3RDYF_Msk                  (0x1UL << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000100 */
+#define RCC_CIFR_PLL3RDYF                      RCC_CIFR_PLL3RDYF_Msk
+#define RCC_CIFR_LSECSSF_Pos                   (9U)
+#define RCC_CIFR_LSECSSF_Msk                   (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */
+#define RCC_CIFR_LSECSSF                       RCC_CIFR_LSECSSF_Msk
+#define RCC_CIFR_HSECSSF_Pos                   (10U)
+#define RCC_CIFR_HSECSSF_Msk                   (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */
+#define RCC_CIFR_HSECSSF                       RCC_CIFR_HSECSSF_Msk
+
+/********************  Bit definition for RCC_CICR register  ******************/
+#define RCC_CICR_LSIRDYC_Pos                   (0U)
+#define RCC_CICR_LSIRDYC_Msk                   (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
+#define RCC_CICR_LSIRDYC                       RCC_CICR_LSIRDYC_Msk
+#define RCC_CICR_LSERDYC_Pos                   (1U)
+#define RCC_CICR_LSERDYC_Msk                   (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
+#define RCC_CICR_LSERDYC                       RCC_CICR_LSERDYC_Msk
+#define RCC_CICR_HSIRDYC_Pos                   (2U)
+#define RCC_CICR_HSIRDYC_Msk                   (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */
+#define RCC_CICR_HSIRDYC                       RCC_CICR_HSIRDYC_Msk
+#define RCC_CICR_HSERDYC_Pos                   (3U)
+#define RCC_CICR_HSERDYC_Msk                   (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */
+#define RCC_CICR_HSERDYC                       RCC_CICR_HSERDYC_Msk
+#define RCC_CICR_CSIRDYC_Pos                   (4U)
+#define RCC_CICR_CSIRDYC_Msk                   (0x1UL << RCC_CICR_CSIRDYC_Pos) /*!< 0x00000010 */
+#define RCC_CICR_CSIRDYC                       RCC_CICR_CSIRDYC_Msk
+#define RCC_CICR_HSI48RDYC_Pos                 (5U)
+#define RCC_CICR_HSI48RDYC_Msk                 (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000020 */
+#define RCC_CICR_HSI48RDYC                     RCC_CICR_HSI48RDYC_Msk
+#define RCC_CICR_PLLRDYC_Pos                   (6U)
+#define RCC_CICR_PLLRDYC_Msk                   (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000040 */
+#define RCC_CICR_PLLRDYC                       RCC_CICR_PLLRDYC_Msk
+#define RCC_CICR_PLL2RDYC_Pos                  (7U)
+#define RCC_CICR_PLL2RDYC_Msk                  (0x1UL << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000080 */
+#define RCC_CICR_PLL2RDYC                      RCC_CICR_PLL2RDYC_Msk
+#define RCC_CICR_PLL3RDYC_Pos                  (8U)
+#define RCC_CICR_PLL3RDYC_Msk                  (0x1UL << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000100 */
+#define RCC_CICR_PLL3RDYC                      RCC_CICR_PLL3RDYC_Msk
+#define RCC_CICR_LSECSSC_Pos                   (9U)
+#define RCC_CICR_LSECSSC_Msk                   (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */
+#define RCC_CICR_LSECSSC                       RCC_CICR_LSECSSC_Msk
+#define RCC_CICR_HSECSSC_Pos                   (10U)
+#define RCC_CICR_HSECSSC_Msk                   (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */
+#define RCC_CICR_HSECSSC                       RCC_CICR_HSECSSC_Msk
+
+/********************  Bit definition for RCC_BDCR register  ******************/
+#define RCC_BDCR_LSEON_Pos                     (0U)
+#define RCC_BDCR_LSEON_Msk                     (0x1UL << RCC_BDCR_LSEON_Pos)   /*!< 0x00000001 */
+#define RCC_BDCR_LSEON                         RCC_BDCR_LSEON_Msk
+#define RCC_BDCR_LSERDY_Pos                    (1U)
+#define RCC_BDCR_LSERDY_Msk                    (0x1UL << RCC_BDCR_LSERDY_Pos)  /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY                        RCC_BDCR_LSERDY_Msk
+#define RCC_BDCR_LSEBYP_Pos                    (2U)
+#define RCC_BDCR_LSEBYP_Msk                    (0x1UL << RCC_BDCR_LSEBYP_Pos)  /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP                        RCC_BDCR_LSEBYP_Msk
+
+#define RCC_BDCR_LSEDRV_Pos                    (3U)
+#define RCC_BDCR_LSEDRV_Msk                    (0x3UL << RCC_BDCR_LSEDRV_Pos)  /*!< 0x00000018 */
+#define RCC_BDCR_LSEDRV                        RCC_BDCR_LSEDRV_Msk
+#define RCC_BDCR_LSEDRV_0                      (0x1UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000008 */
+#define RCC_BDCR_LSEDRV_1                      (0x2UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000010 */
+
+#define RCC_BDCR_LSECSSON_Pos                  (5U)
+#define RCC_BDCR_LSECSSON_Msk                  (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */
+#define RCC_BDCR_LSECSSON                      RCC_BDCR_LSECSSON_Msk
+#define RCC_BDCR_LSECSSD_Pos                   (6U)
+#define RCC_BDCR_LSECSSD_Msk                   (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */
+#define RCC_BDCR_LSECSSD                       RCC_BDCR_LSECSSD_Msk
+
+#define RCC_BDCR_RTCSEL_Pos                    (8U)
+#define RCC_BDCR_RTCSEL_Msk                    (0x3UL << RCC_BDCR_RTCSEL_Pos)  /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL                        RCC_BDCR_RTCSEL_Msk
+#define RCC_BDCR_RTCSEL_0                      (0x1UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1                      (0x2UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000200 */
+
+#define RCC_BDCR_RTCEN_Pos                     (15U)
+#define RCC_BDCR_RTCEN_Msk                     (0x1UL << RCC_BDCR_RTCEN_Pos)   /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN                         RCC_BDCR_RTCEN_Msk
+#define RCC_BDCR_BDRST_Pos                     (16U)
+#define RCC_BDCR_BDRST_Msk                     (0x1UL << RCC_BDCR_BDRST_Pos)   /*!< 0x00010000 */
+#define RCC_BDCR_BDRST                         RCC_BDCR_BDRST_Msk
+/********************  Bit definition for RCC_CSR register  *******************/
+#define RCC_CSR_LSION_Pos                      (0U)
+#define RCC_CSR_LSION_Msk                      (0x1UL << RCC_CSR_LSION_Pos)    /*!< 0x00000001 */
+#define RCC_CSR_LSION                          RCC_CSR_LSION_Msk
+#define RCC_CSR_LSIRDY_Pos                     (1U)
+#define RCC_CSR_LSIRDY_Msk                     (0x1UL << RCC_CSR_LSIRDY_Pos)   /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY                         RCC_CSR_LSIRDY_Msk
+
+
+/********************  Bit definition for RCC_AHB3ENR register  **************/
+#define RCC_AHB3ENR_MDMAEN_Pos                 (0U)
+#define RCC_AHB3ENR_MDMAEN_Msk                 (0x1UL << RCC_AHB3ENR_MDMAEN_Pos)       /*!< 0x00000001 */
+#define RCC_AHB3ENR_MDMAEN                     RCC_AHB3ENR_MDMAEN_Msk
+#define RCC_AHB3ENR_DMA2DEN_Pos                (4U)
+#define RCC_AHB3ENR_DMA2DEN_Msk                (0x1UL << RCC_AHB3ENR_DMA2DEN_Pos)      /*!< 0x00000010 */
+#define RCC_AHB3ENR_DMA2DEN                    RCC_AHB3ENR_DMA2DEN_Msk
+#define RCC_AHB3ENR_JPGDECEN_Pos               (5U)
+#define RCC_AHB3ENR_JPGDECEN_Msk               (0x1UL << RCC_AHB3ENR_JPGDECEN_Pos)     /*!< 0x00000020 */
+#define RCC_AHB3ENR_JPGDECEN                   RCC_AHB3ENR_JPGDECEN_Msk
+#define RCC_AHB3ENR_FMCEN_Pos                  (12U)
+#define RCC_AHB3ENR_FMCEN_Msk                  (0x1UL << RCC_AHB3ENR_FMCEN_Pos)        /*!< 0x00001000 */
+#define RCC_AHB3ENR_FMCEN                      RCC_AHB3ENR_FMCEN_Msk
+#define RCC_AHB3ENR_QSPIEN_Pos                 (14U)
+#define RCC_AHB3ENR_QSPIEN_Msk                 (0x1UL << RCC_AHB3ENR_QSPIEN_Pos)       /*!< 0x00004000 */
+#define RCC_AHB3ENR_QSPIEN                     RCC_AHB3ENR_QSPIEN_Msk
+#define RCC_AHB3ENR_SDMMC1EN_Pos               (16U)
+#define RCC_AHB3ENR_SDMMC1EN_Msk               (0x1UL << RCC_AHB3ENR_SDMMC1EN_Pos)     /*!< 0x00010000 */
+#define RCC_AHB3ENR_SDMMC1EN                   RCC_AHB3ENR_SDMMC1EN_Msk
+
+/********************  Bit definition for RCC_AHB1ENR register  ***************/
+#define RCC_AHB1ENR_DMA1EN_Pos                 (0U)
+#define RCC_AHB1ENR_DMA1EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)          /*!< 0x00000001 */
+#define RCC_AHB1ENR_DMA1EN                     RCC_AHB1ENR_DMA1EN_Msk
+#define RCC_AHB1ENR_DMA2EN_Pos                 (1U)
+#define RCC_AHB1ENR_DMA2EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)          /*!< 0x00000002 */
+#define RCC_AHB1ENR_DMA2EN                     RCC_AHB1ENR_DMA2EN_Msk
+#define RCC_AHB1ENR_ADC12EN_Pos                (5U)
+#define RCC_AHB1ENR_ADC12EN_Msk                (0x1UL << RCC_AHB1ENR_ADC12EN_Pos)         /*!< 0x00000020 */
+#define RCC_AHB1ENR_ADC12EN                    RCC_AHB1ENR_ADC12EN_Msk
+#define RCC_AHB1ENR_ETH1MACEN_Pos              (15U)
+#define RCC_AHB1ENR_ETH1MACEN_Msk              (0x1UL << RCC_AHB1ENR_ETH1MACEN_Pos)       /*!< 0x00008000 */
+#define RCC_AHB1ENR_ETH1MACEN                  RCC_AHB1ENR_ETH1MACEN_Msk
+#define RCC_AHB1ENR_ETH1TXEN_Pos               (16U)
+#define RCC_AHB1ENR_ETH1TXEN_Msk               (0x1UL << RCC_AHB1ENR_ETH1TXEN_Pos)        /*!< 0x00010000 */
+#define RCC_AHB1ENR_ETH1TXEN                   RCC_AHB1ENR_ETH1TXEN_Msk
+#define RCC_AHB1ENR_ETH1RXEN_Pos               (17U)
+#define RCC_AHB1ENR_ETH1RXEN_Msk               (0x1UL << RCC_AHB1ENR_ETH1RXEN_Pos)        /*!< 0x00020000 */
+#define RCC_AHB1ENR_ETH1RXEN                   RCC_AHB1ENR_ETH1RXEN_Msk
+#define RCC_AHB1ENR_USB1OTGHSEN_Pos            (25U)
+#define RCC_AHB1ENR_USB1OTGHSEN_Msk            (0x1UL << RCC_AHB1ENR_USB1OTGHSEN_Pos)     /*!< 0x02000000 */
+#define RCC_AHB1ENR_USB1OTGHSEN                RCC_AHB1ENR_USB1OTGHSEN_Msk
+#define RCC_AHB1ENR_USB1OTGHSULPIEN_Pos        (26U)
+#define RCC_AHB1ENR_USB1OTGHSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_USB1OTGHSULPIEN_Pos) /*!< 0x04000000 */
+#define RCC_AHB1ENR_USB1OTGHSULPIEN            RCC_AHB1ENR_USB1OTGHSULPIEN_Msk
+#define RCC_AHB1ENR_USB2OTGFSEN_Pos            (27U)
+#define RCC_AHB1ENR_USB2OTGFSEN_Msk            (0x1UL << RCC_AHB1ENR_USB2OTGFSEN_Pos)     /*!< 0x08000000 */
+#define RCC_AHB1ENR_USB2OTGFSEN                RCC_AHB1ENR_USB2OTGFSEN_Msk
+#define RCC_AHB1ENR_USB2OTGFSULPIEN_Pos        (28U)
+#define RCC_AHB1ENR_USB2OTGFSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_USB2OTGFSULPIEN_Pos) /*!< 0x10000000 */
+#define RCC_AHB1ENR_USB2OTGFSULPIEN            RCC_AHB1ENR_USB2OTGFSULPIEN_Msk
+
+/* Legacy define */
+#define RCC_AHB1ENR_USB2OTGHSEN_Pos            RCC_AHB1ENR_USB2OTGFSEN_Pos
+#define RCC_AHB1ENR_USB2OTGHSEN_Msk            RCC_AHB1ENR_USB2OTGFSEN_Msk
+#define RCC_AHB1ENR_USB2OTGHSEN                RCC_AHB1ENR_USB2OTGFSEN
+#define RCC_AHB1ENR_USB2OTGHSULPIEN_Pos        RCC_AHB1ENR_USB2OTGFSULPIEN_Pos
+#define RCC_AHB1ENR_USB2OTGHSULPIEN_Msk        RCC_AHB1ENR_USB2OTGFSULPIEN_Msk
+#define RCC_AHB1ENR_USB2OTGHSULPIEN            RCC_AHB1ENR_USB2OTGFSULPIEN
+
+
+/********************  Bit definition for RCC_AHB2ENR register  ***************/
+#define RCC_AHB2ENR_DCMIEN_Pos                 (0U)
+#define RCC_AHB2ENR_DCMIEN_Msk                 (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)          /*!< 0x00000001 */
+#define RCC_AHB2ENR_DCMIEN                     RCC_AHB2ENR_DCMIEN_Msk
+#define RCC_AHB2ENR_RNGEN_Pos                  (6U)
+#define RCC_AHB2ENR_RNGEN_Msk                  (0x1UL << RCC_AHB2ENR_RNGEN_Pos)           /*!< 0x00000040 */
+#define RCC_AHB2ENR_RNGEN                      RCC_AHB2ENR_RNGEN_Msk
+#define RCC_AHB2ENR_SDMMC2EN_Pos               (9U)
+#define RCC_AHB2ENR_SDMMC2EN_Msk               (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos)        /*!< 0x00000200 */
+#define RCC_AHB2ENR_SDMMC2EN                   RCC_AHB2ENR_SDMMC2EN_Msk
+#define RCC_AHB2ENR_SRAM1EN_Pos                (29U)
+#define RCC_AHB2ENR_SRAM1EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM1EN_Pos)       /*!< 0x20000000 */
+#define RCC_AHB2ENR_SRAM1EN                    RCC_AHB2ENR_SRAM1EN_Msk
+#define RCC_AHB2ENR_SRAM2EN_Pos                (30U)
+#define RCC_AHB2ENR_SRAM2EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos)       /*!< 0x40000000 */
+#define RCC_AHB2ENR_SRAM2EN                    RCC_AHB2ENR_SRAM2EN_Msk
+#define RCC_AHB2ENR_SRAM3EN_Pos                (31U)
+#define RCC_AHB2ENR_SRAM3EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM3EN_Pos)       /*!< 0x80000000 */
+#define RCC_AHB2ENR_SRAM3EN                    RCC_AHB2ENR_SRAM3EN_Msk
+
+/* Legacy define */
+#define RCC_AHB2ENR_D2SRAM1EN_Pos              RCC_AHB2ENR_SRAM1EN_Pos
+#define RCC_AHB2ENR_D2SRAM1EN_Msk              RCC_AHB2ENR_SRAM1EN_Msk
+#define RCC_AHB2ENR_D2SRAM1EN                  RCC_AHB2ENR_SRAM1EN
+#define RCC_AHB2ENR_D2SRAM2EN_Pos              RCC_AHB2ENR_SRAM2EN_Pos
+#define RCC_AHB2ENR_D2SRAM2EN_Msk              RCC_AHB2ENR_SRAM2EN_Msk
+#define RCC_AHB2ENR_D2SRAM2EN                  RCC_AHB2ENR_SRAM2EN
+#define RCC_AHB2ENR_D2SRAM3EN_Pos              RCC_AHB2ENR_SRAM3EN_Pos
+#define RCC_AHB2ENR_D2SRAM3EN_Msk              RCC_AHB2ENR_SRAM3EN_Msk
+#define RCC_AHB2ENR_D2SRAM3EN                  RCC_AHB2ENR_SRAM3EN
+
+/********************  Bit definition for RCC_AHB4ENR register  ******************/
+#define RCC_AHB4ENR_GPIOAEN_Pos                (0U)
+#define RCC_AHB4ENR_GPIOAEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos)         /*!< 0x00000001 */
+#define RCC_AHB4ENR_GPIOAEN                    RCC_AHB4ENR_GPIOAEN_Msk
+#define RCC_AHB4ENR_GPIOBEN_Pos                (1U)
+#define RCC_AHB4ENR_GPIOBEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos)         /*!< 0x00000002 */
+#define RCC_AHB4ENR_GPIOBEN                    RCC_AHB4ENR_GPIOBEN_Msk
+#define RCC_AHB4ENR_GPIOCEN_Pos                (2U)
+#define RCC_AHB4ENR_GPIOCEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos)         /*!< 0x00000004 */
+#define RCC_AHB4ENR_GPIOCEN                    RCC_AHB4ENR_GPIOCEN_Msk
+#define RCC_AHB4ENR_GPIODEN_Pos                (3U)
+#define RCC_AHB4ENR_GPIODEN_Msk                (0x1UL << RCC_AHB4ENR_GPIODEN_Pos)         /*!< 0x00000008 */
+#define RCC_AHB4ENR_GPIODEN                    RCC_AHB4ENR_GPIODEN_Msk
+#define RCC_AHB4ENR_GPIOEEN_Pos                (4U)
+#define RCC_AHB4ENR_GPIOEEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos)         /*!< 0x00000010 */
+#define RCC_AHB4ENR_GPIOEEN                    RCC_AHB4ENR_GPIOEEN_Msk
+#define RCC_AHB4ENR_GPIOFEN_Pos                (5U)
+#define RCC_AHB4ENR_GPIOFEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos)         /*!< 0x00000020 */
+#define RCC_AHB4ENR_GPIOFEN                    RCC_AHB4ENR_GPIOFEN_Msk
+#define RCC_AHB4ENR_GPIOGEN_Pos                (6U)
+#define RCC_AHB4ENR_GPIOGEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos)         /*!< 0x00000040 */
+#define RCC_AHB4ENR_GPIOGEN                    RCC_AHB4ENR_GPIOGEN_Msk
+#define RCC_AHB4ENR_GPIOHEN_Pos                (7U)
+#define RCC_AHB4ENR_GPIOHEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos)         /*!< 0x00000080 */
+#define RCC_AHB4ENR_GPIOHEN                    RCC_AHB4ENR_GPIOHEN_Msk
+#define RCC_AHB4ENR_GPIOIEN_Pos                (8U)
+#define RCC_AHB4ENR_GPIOIEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOIEN_Pos)         /*!< 0x00000100 */
+#define RCC_AHB4ENR_GPIOIEN                    RCC_AHB4ENR_GPIOIEN_Msk
+#define RCC_AHB4ENR_GPIOJEN_Pos                (9U)
+#define RCC_AHB4ENR_GPIOJEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOJEN_Pos)         /*!< 0x00000200 */
+#define RCC_AHB4ENR_GPIOJEN                    RCC_AHB4ENR_GPIOJEN_Msk
+#define RCC_AHB4ENR_GPIOKEN_Pos                (10U)
+#define RCC_AHB4ENR_GPIOKEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOKEN_Pos)         /*!< 0x00000400 */
+#define RCC_AHB4ENR_GPIOKEN                    RCC_AHB4ENR_GPIOKEN_Msk
+#define RCC_AHB4ENR_CRCEN_Pos                  (19U)
+#define RCC_AHB4ENR_CRCEN_Msk                  (0x1UL << RCC_AHB4ENR_CRCEN_Pos)           /*!< 0x00080000 */
+#define RCC_AHB4ENR_CRCEN                      RCC_AHB4ENR_CRCEN_Msk
+#define RCC_AHB4ENR_BDMAEN_Pos                 (21U)
+#define RCC_AHB4ENR_BDMAEN_Msk                 (0x1UL << RCC_AHB4ENR_BDMAEN_Pos)          /*!< 0x00200000 */
+#define RCC_AHB4ENR_BDMAEN                     RCC_AHB4ENR_BDMAEN_Msk
+#define RCC_AHB4ENR_ADC3EN_Pos                 (24U)
+#define RCC_AHB4ENR_ADC3EN_Msk                 (0x1UL << RCC_AHB4ENR_ADC3EN_Pos)          /*!< 0x01000000 */
+#define RCC_AHB4ENR_ADC3EN                     RCC_AHB4ENR_ADC3EN_Msk
+#define RCC_AHB4ENR_HSEMEN_Pos                 (25U)
+#define RCC_AHB4ENR_HSEMEN_Msk                 (0x1UL << RCC_AHB4ENR_HSEMEN_Pos)          /*!< 0x02000000 */
+#define RCC_AHB4ENR_HSEMEN                     RCC_AHB4ENR_HSEMEN_Msk
+#define RCC_AHB4ENR_BKPRAMEN_Pos               (28U)
+#define RCC_AHB4ENR_BKPRAMEN_Msk               (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos)        /*!< 0x10000000 */
+#define RCC_AHB4ENR_BKPRAMEN                   RCC_AHB4ENR_BKPRAMEN_Msk
+
+/********************  Bit definition for RCC_APB3ENR register  ******************/
+#define RCC_APB3ENR_LTDCEN_Pos                 (3U)
+#define RCC_APB3ENR_LTDCEN_Msk                 (0x1UL << RCC_APB3ENR_LTDCEN_Pos) /*!< 0x00000008 */
+#define RCC_APB3ENR_LTDCEN                     RCC_APB3ENR_LTDCEN_Msk
+#define RCC_APB3ENR_WWDG1EN_Pos                (6U)
+#define RCC_APB3ENR_WWDG1EN_Msk                (0x1UL << RCC_APB3ENR_WWDG1EN_Pos) /*!< 0x00000040 */
+#define RCC_APB3ENR_WWDG1EN                    RCC_APB3ENR_WWDG1EN_Msk
+
+/********************  Bit definition for RCC_APB1LENR register  ******************/
+
+#define RCC_APB1LENR_TIM2EN_Pos                (0U)
+#define RCC_APB1LENR_TIM2EN_Msk                (0x1UL << RCC_APB1LENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1LENR_TIM2EN                    RCC_APB1LENR_TIM2EN_Msk
+#define RCC_APB1LENR_TIM3EN_Pos                (1U)
+#define RCC_APB1LENR_TIM3EN_Msk                (0x1UL << RCC_APB1LENR_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1LENR_TIM3EN                    RCC_APB1LENR_TIM3EN_Msk
+#define RCC_APB1LENR_TIM4EN_Pos                (2U)
+#define RCC_APB1LENR_TIM4EN_Msk                (0x1UL << RCC_APB1LENR_TIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1LENR_TIM4EN                    RCC_APB1LENR_TIM4EN_Msk
+#define RCC_APB1LENR_TIM5EN_Pos                (3U)
+#define RCC_APB1LENR_TIM5EN_Msk                (0x1UL << RCC_APB1LENR_TIM5EN_Pos) /*!< 0x00000008 */
+#define RCC_APB1LENR_TIM5EN                    RCC_APB1LENR_TIM5EN_Msk
+#define RCC_APB1LENR_TIM6EN_Pos                (4U)
+#define RCC_APB1LENR_TIM6EN_Msk                (0x1UL << RCC_APB1LENR_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_APB1LENR_TIM6EN                    RCC_APB1LENR_TIM6EN_Msk
+#define RCC_APB1LENR_TIM7EN_Pos                (5U)
+#define RCC_APB1LENR_TIM7EN_Msk                (0x1UL << RCC_APB1LENR_TIM7EN_Pos) /*!< 0x00000020 */
+#define RCC_APB1LENR_TIM7EN                    RCC_APB1LENR_TIM7EN_Msk
+#define RCC_APB1LENR_TIM12EN_Pos               (6U)
+#define RCC_APB1LENR_TIM12EN_Msk               (0x1UL << RCC_APB1LENR_TIM12EN_Pos) /*!< 0x00000040 */
+#define RCC_APB1LENR_TIM12EN                   RCC_APB1LENR_TIM12EN_Msk
+#define RCC_APB1LENR_TIM13EN_Pos               (7U)
+#define RCC_APB1LENR_TIM13EN_Msk               (0x1UL << RCC_APB1LENR_TIM13EN_Pos) /*!< 0x00000080 */
+#define RCC_APB1LENR_TIM13EN                   RCC_APB1LENR_TIM13EN_Msk
+#define RCC_APB1LENR_TIM14EN_Pos               (8U)
+#define RCC_APB1LENR_TIM14EN_Msk               (0x1UL << RCC_APB1LENR_TIM14EN_Pos) /*!< 0x00000100 */
+#define RCC_APB1LENR_TIM14EN                   RCC_APB1LENR_TIM14EN_Msk
+#define RCC_APB1LENR_LPTIM1EN_Pos              (9U)
+#define RCC_APB1LENR_LPTIM1EN_Msk              (0x1UL << RCC_APB1LENR_LPTIM1EN_Pos) /*!< 0x00000200 */
+#define RCC_APB1LENR_LPTIM1EN                  RCC_APB1LENR_LPTIM1EN_Msk
+
+
+#define RCC_APB1LENR_SPI2EN_Pos                (14U)
+#define RCC_APB1LENR_SPI2EN_Msk                (0x1UL << RCC_APB1LENR_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1LENR_SPI2EN                    RCC_APB1LENR_SPI2EN_Msk
+#define RCC_APB1LENR_SPI3EN_Pos                (15U)
+#define RCC_APB1LENR_SPI3EN_Msk                (0x1UL << RCC_APB1LENR_SPI3EN_Pos) /*!< 0x00008000 */
+#define RCC_APB1LENR_SPI3EN                    RCC_APB1LENR_SPI3EN_Msk
+#define RCC_APB1LENR_SPDIFRXEN_Pos             (16U)
+#define RCC_APB1LENR_SPDIFRXEN_Msk             (0x1UL << RCC_APB1LENR_SPDIFRXEN_Pos) /*!< 0x00010000 */
+#define RCC_APB1LENR_SPDIFRXEN                 RCC_APB1LENR_SPDIFRXEN_Msk
+#define RCC_APB1LENR_USART2EN_Pos              (17U)
+#define RCC_APB1LENR_USART2EN_Msk              (0x1UL << RCC_APB1LENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1LENR_USART2EN                  RCC_APB1LENR_USART2EN_Msk
+#define RCC_APB1LENR_USART3EN_Pos              (18U)
+#define RCC_APB1LENR_USART3EN_Msk              (0x1UL << RCC_APB1LENR_USART3EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1LENR_USART3EN                  RCC_APB1LENR_USART3EN_Msk
+#define RCC_APB1LENR_UART4EN_Pos               (19U)
+#define RCC_APB1LENR_UART4EN_Msk               (0x1UL << RCC_APB1LENR_UART4EN_Pos) /*!< 0x00080000 */
+#define RCC_APB1LENR_UART4EN                   RCC_APB1LENR_UART4EN_Msk
+#define RCC_APB1LENR_UART5EN_Pos               (20U)
+#define RCC_APB1LENR_UART5EN_Msk               (0x1UL << RCC_APB1LENR_UART5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB1LENR_UART5EN                   RCC_APB1LENR_UART5EN_Msk
+#define RCC_APB1LENR_I2C1EN_Pos                (21U)
+#define RCC_APB1LENR_I2C1EN_Msk                (0x1UL << RCC_APB1LENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1LENR_I2C1EN                    RCC_APB1LENR_I2C1EN_Msk
+#define RCC_APB1LENR_I2C2EN_Pos                (22U)
+#define RCC_APB1LENR_I2C2EN_Msk                (0x1UL << RCC_APB1LENR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1LENR_I2C2EN                    RCC_APB1LENR_I2C2EN_Msk
+#define RCC_APB1LENR_I2C3EN_Pos                (23U)
+#define RCC_APB1LENR_I2C3EN_Msk                (0x1UL << RCC_APB1LENR_I2C3EN_Pos) /*!< 0x00800000 */
+#define RCC_APB1LENR_I2C3EN                    RCC_APB1LENR_I2C3EN_Msk
+#define RCC_APB1LENR_CECEN_Pos                 (27U)
+#define RCC_APB1LENR_CECEN_Msk                 (0x1UL << RCC_APB1LENR_CECEN_Pos) /*!< 0x08000000 */
+#define RCC_APB1LENR_CECEN                     RCC_APB1LENR_CECEN_Msk
+#define RCC_APB1LENR_DAC12EN_Pos               (29U)
+#define RCC_APB1LENR_DAC12EN_Msk               (0x1UL << RCC_APB1LENR_DAC12EN_Pos) /*!< 0x20000000 */
+#define RCC_APB1LENR_DAC12EN                   RCC_APB1LENR_DAC12EN_Msk
+#define RCC_APB1LENR_UART7EN_Pos               (30U)
+#define RCC_APB1LENR_UART7EN_Msk               (0x1UL << RCC_APB1LENR_UART7EN_Pos) /*!< 0x40000000 */
+#define RCC_APB1LENR_UART7EN                   RCC_APB1LENR_UART7EN_Msk
+#define RCC_APB1LENR_UART8EN_Pos               (31U)
+#define RCC_APB1LENR_UART8EN_Msk               (0x1UL << RCC_APB1LENR_UART8EN_Pos) /*!< 0x80000000 */
+#define RCC_APB1LENR_UART8EN                   RCC_APB1LENR_UART8EN_Msk
+
+/* Legacy define */
+#define RCC_APB1LENR_HDMICECEN_Pos             RCC_APB1LENR_CECEN_Pos
+#define RCC_APB1LENR_HDMICECEN_Msk             RCC_APB1LENR_CECEN_Msk
+#define RCC_APB1LENR_HDMICECEN                 RCC_APB1LENR_CECEN
+/********************  Bit definition for RCC_APB1HENR register  ******************/
+#define RCC_APB1HENR_CRSEN_Pos                 (1U)
+#define RCC_APB1HENR_CRSEN_Msk                 (0x1UL << RCC_APB1HENR_CRSEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1HENR_CRSEN                     RCC_APB1HENR_CRSEN_Msk
+#define RCC_APB1HENR_SWPMIEN_Pos               (2U)
+#define RCC_APB1HENR_SWPMIEN_Msk               (0x1UL << RCC_APB1HENR_SWPMIEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1HENR_SWPMIEN                   RCC_APB1HENR_SWPMIEN_Msk
+#define RCC_APB1HENR_OPAMPEN_Pos               (4U)
+#define RCC_APB1HENR_OPAMPEN_Msk               (0x1UL << RCC_APB1HENR_OPAMPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1HENR_OPAMPEN                   RCC_APB1HENR_OPAMPEN_Msk
+#define RCC_APB1HENR_MDIOSEN_Pos               (5U)
+#define RCC_APB1HENR_MDIOSEN_Msk               (0x1UL << RCC_APB1HENR_MDIOSEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1HENR_MDIOSEN                   RCC_APB1HENR_MDIOSEN_Msk
+#define RCC_APB1HENR_FDCANEN_Pos               (8U)
+#define RCC_APB1HENR_FDCANEN_Msk               (0x1UL << RCC_APB1HENR_FDCANEN_Pos) /*!< 0x00000100 */
+#define RCC_APB1HENR_FDCANEN                   RCC_APB1HENR_FDCANEN_Msk
+
+/********************  Bit definition for RCC_APB2ENR register  ******************/
+#define RCC_APB2ENR_TIM1EN_Pos                 (0U)
+#define RCC_APB2ENR_TIM1EN_Msk                 (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_TIM1EN                     RCC_APB2ENR_TIM1EN_Msk
+#define RCC_APB2ENR_TIM8EN_Pos                 (1U)
+#define RCC_APB2ENR_TIM8EN_Msk                 (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
+#define RCC_APB2ENR_TIM8EN                     RCC_APB2ENR_TIM8EN_Msk
+#define RCC_APB2ENR_USART1EN_Pos               (4U)
+#define RCC_APB2ENR_USART1EN_Msk               (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
+#define RCC_APB2ENR_USART1EN                   RCC_APB2ENR_USART1EN_Msk
+#define RCC_APB2ENR_USART6EN_Pos               (5U)
+#define RCC_APB2ENR_USART6EN_Msk               (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_USART6EN                   RCC_APB2ENR_USART6EN_Msk
+#define RCC_APB2ENR_SPI1EN_Pos                 (12U)
+#define RCC_APB2ENR_SPI1EN_Msk                 (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN                     RCC_APB2ENR_SPI1EN_Msk
+#define RCC_APB2ENR_SPI4EN_Pos                 (13U)
+#define RCC_APB2ENR_SPI4EN_Msk                 (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
+#define RCC_APB2ENR_SPI4EN                     RCC_APB2ENR_SPI4EN_Msk
+#define RCC_APB2ENR_TIM15EN_Pos                (16U)
+#define RCC_APB2ENR_TIM15EN_Msk                (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
+#define RCC_APB2ENR_TIM15EN                    RCC_APB2ENR_TIM15EN_Msk
+#define RCC_APB2ENR_TIM16EN_Pos                (17U)
+#define RCC_APB2ENR_TIM16EN_Msk                (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
+#define RCC_APB2ENR_TIM16EN                    RCC_APB2ENR_TIM16EN_Msk
+#define RCC_APB2ENR_TIM17EN_Pos                (18U)
+#define RCC_APB2ENR_TIM17EN_Msk                (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
+#define RCC_APB2ENR_TIM17EN                    RCC_APB2ENR_TIM17EN_Msk
+#define RCC_APB2ENR_SPI5EN_Pos                 (20U)
+#define RCC_APB2ENR_SPI5EN_Msk                 (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB2ENR_SPI5EN                     RCC_APB2ENR_SPI5EN_Msk
+#define RCC_APB2ENR_SAI1EN_Pos                 (22U)
+#define RCC_APB2ENR_SAI1EN_Msk                 (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */
+#define RCC_APB2ENR_SAI1EN                     RCC_APB2ENR_SAI1EN_Msk
+#define RCC_APB2ENR_SAI2EN_Pos                 (23U)
+#define RCC_APB2ENR_SAI2EN_Msk                 (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */
+#define RCC_APB2ENR_SAI2EN                     RCC_APB2ENR_SAI2EN_Msk
+#define RCC_APB2ENR_SAI3EN_Pos                 (24U)
+#define RCC_APB2ENR_SAI3EN_Msk                 (0x1UL << RCC_APB2ENR_SAI3EN_Pos) /*!< 0x01000000 */
+#define RCC_APB2ENR_SAI3EN                     RCC_APB2ENR_SAI3EN_Msk
+#define RCC_APB2ENR_DFSDM1EN_Pos               (28U)
+#define RCC_APB2ENR_DFSDM1EN_Msk               (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x10000000 */
+#define RCC_APB2ENR_DFSDM1EN                   RCC_APB2ENR_DFSDM1EN_Msk
+#define RCC_APB2ENR_HRTIMEN_Pos                (29U)
+#define RCC_APB2ENR_HRTIMEN_Msk                (0x1UL << RCC_APB2ENR_HRTIMEN_Pos) /*!< 0x20000000 */
+#define RCC_APB2ENR_HRTIMEN                    RCC_APB2ENR_HRTIMEN_Msk
+
+/********************  Bit definition for RCC_APB4ENR register  ******************/
+#define RCC_APB4ENR_SYSCFGEN_Pos               (1U)
+#define RCC_APB4ENR_SYSCFGEN_Msk               (0x1UL << RCC_APB4ENR_SYSCFGEN_Pos) /*!< 0x00000002 */
+#define RCC_APB4ENR_SYSCFGEN                   RCC_APB4ENR_SYSCFGEN_Msk
+#define RCC_APB4ENR_LPUART1EN_Pos              (3U)
+#define RCC_APB4ENR_LPUART1EN_Msk              (0x1UL << RCC_APB4ENR_LPUART1EN_Pos) /*!< 0x00000008 */
+#define RCC_APB4ENR_LPUART1EN                  RCC_APB4ENR_LPUART1EN_Msk
+#define RCC_APB4ENR_SPI6EN_Pos                 (5U)
+#define RCC_APB4ENR_SPI6EN_Msk                 (0x1UL << RCC_APB4ENR_SPI6EN_Pos) /*!< 0x00000020 */
+#define RCC_APB4ENR_SPI6EN                     RCC_APB4ENR_SPI6EN_Msk
+#define RCC_APB4ENR_I2C4EN_Pos                 (7U)
+#define RCC_APB4ENR_I2C4EN_Msk                 (0x1UL << RCC_APB4ENR_I2C4EN_Pos) /*!< 0x00000080 */
+#define RCC_APB4ENR_I2C4EN                     RCC_APB4ENR_I2C4EN_Msk
+#define RCC_APB4ENR_LPTIM2EN_Pos               (9U)
+#define RCC_APB4ENR_LPTIM2EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos) /*!< 0x00000200 */
+#define RCC_APB4ENR_LPTIM2EN                   RCC_APB4ENR_LPTIM2EN_Msk
+#define RCC_APB4ENR_LPTIM3EN_Pos               (10U)
+#define RCC_APB4ENR_LPTIM3EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos) /*!< 0x00000400 */
+#define RCC_APB4ENR_LPTIM3EN                   RCC_APB4ENR_LPTIM3EN_Msk
+#define RCC_APB4ENR_LPTIM4EN_Pos               (11U)
+#define RCC_APB4ENR_LPTIM4EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM4EN_Pos) /*!< 0x00000800 */
+#define RCC_APB4ENR_LPTIM4EN                   RCC_APB4ENR_LPTIM4EN_Msk
+#define RCC_APB4ENR_LPTIM5EN_Pos               (12U)
+#define RCC_APB4ENR_LPTIM5EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM5EN_Pos) /*!< 0x00001000 */
+#define RCC_APB4ENR_LPTIM5EN                   RCC_APB4ENR_LPTIM5EN_Msk
+#define RCC_APB4ENR_COMP12EN_Pos               (14U)
+#define RCC_APB4ENR_COMP12EN_Msk               (0x1UL << RCC_APB4ENR_COMP12EN_Pos) /*!< 0x00004000 */
+#define RCC_APB4ENR_COMP12EN                   RCC_APB4ENR_COMP12EN_Msk
+#define RCC_APB4ENR_VREFEN_Pos                 (15U)
+#define RCC_APB4ENR_VREFEN_Msk                 (0x1UL << RCC_APB4ENR_VREFEN_Pos) /*!< 0x00008000 */
+#define RCC_APB4ENR_VREFEN                     RCC_APB4ENR_VREFEN_Msk
+#define RCC_APB4ENR_RTCAPBEN_Pos               (16U)
+#define RCC_APB4ENR_RTCAPBEN_Msk               (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos) /*!< 0x00010000 */
+#define RCC_APB4ENR_RTCAPBEN                   RCC_APB4ENR_RTCAPBEN_Msk
+#define RCC_APB4ENR_SAI4EN_Pos                 (21U)
+#define RCC_APB4ENR_SAI4EN_Msk                 (0x1UL << RCC_APB4ENR_SAI4EN_Pos) /*!< 0x00200000 */
+#define RCC_APB4ENR_SAI4EN                     RCC_APB4ENR_SAI4EN_Msk
+
+
+/********************  Bit definition for RCC_AHB3RSTR register  ***************/
+#define RCC_AHB3RSTR_MDMARST_Pos               (0U)
+#define RCC_AHB3RSTR_MDMARST_Msk               (0x1UL << RCC_AHB3RSTR_MDMARST_Pos)      /*!< 0x00000001 */
+#define RCC_AHB3RSTR_MDMARST                   RCC_AHB3RSTR_MDMARST_Msk
+#define RCC_AHB3RSTR_DMA2DRST_Pos              (4U)
+#define RCC_AHB3RSTR_DMA2DRST_Msk              (0x1UL << RCC_AHB3RSTR_DMA2DRST_Pos)     /*!< 0x00000010 */
+#define RCC_AHB3RSTR_DMA2DRST                  RCC_AHB3RSTR_DMA2DRST_Msk
+#define RCC_AHB3RSTR_JPGDECRST_Pos             (5U)
+#define RCC_AHB3RSTR_JPGDECRST_Msk             (0x1UL << RCC_AHB3RSTR_JPGDECRST_Pos)    /*!< 0x00000020 */
+#define RCC_AHB3RSTR_JPGDECRST                 RCC_AHB3RSTR_JPGDECRST_Msk
+#define RCC_AHB3RSTR_FMCRST_Pos                (12U)
+#define RCC_AHB3RSTR_FMCRST_Msk                (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)      /*!< 0x00001000 */
+#define RCC_AHB3RSTR_FMCRST                    RCC_AHB3RSTR_FMCRST_Msk
+#define RCC_AHB3RSTR_QSPIRST_Pos               (14U)
+#define RCC_AHB3RSTR_QSPIRST_Msk               (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)     /*!< 0x00004000 */
+#define RCC_AHB3RSTR_QSPIRST                   RCC_AHB3RSTR_QSPIRST_Msk
+#define RCC_AHB3RSTR_SDMMC1RST_Pos             (16U)
+#define RCC_AHB3RSTR_SDMMC1RST_Msk             (0x1UL << RCC_AHB3RSTR_SDMMC1RST_Pos)   /*!< 0x00010000 */
+#define RCC_AHB3RSTR_SDMMC1RST                 RCC_AHB3RSTR_SDMMC1RST_Msk
+
+
+/********************  Bit definition for RCC_AHB1RSTR register  ***************/
+#define RCC_AHB1RSTR_DMA1RST_Pos               (0U)
+#define RCC_AHB1RSTR_DMA1RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)      /*!< 0x00000001 */
+#define RCC_AHB1RSTR_DMA1RST                   RCC_AHB1RSTR_DMA1RST_Msk
+#define RCC_AHB1RSTR_DMA2RST_Pos               (1U)
+#define RCC_AHB1RSTR_DMA2RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)      /*!< 0x00000002 */
+#define RCC_AHB1RSTR_DMA2RST                   RCC_AHB1RSTR_DMA2RST_Msk
+#define RCC_AHB1RSTR_ADC12RST_Pos              (5U)
+#define RCC_AHB1RSTR_ADC12RST_Msk              (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos)     /*!< 0x00000020 */
+#define RCC_AHB1RSTR_ADC12RST                  RCC_AHB1RSTR_ADC12RST_Msk
+#define RCC_AHB1RSTR_ETH1MACRST_Pos            (15U)
+#define RCC_AHB1RSTR_ETH1MACRST_Msk            (0x1UL << RCC_AHB1RSTR_ETH1MACRST_Pos)   /*!< 0x00008000 */
+#define RCC_AHB1RSTR_ETH1MACRST                RCC_AHB1RSTR_ETH1MACRST_Msk
+#define RCC_AHB1RSTR_USB1OTGHSRST_Pos          (25U)
+#define RCC_AHB1RSTR_USB1OTGHSRST_Msk          (0x1UL << RCC_AHB1RSTR_USB1OTGHSRST_Pos) /*!< 0x02000000 */
+#define RCC_AHB1RSTR_USB1OTGHSRST              RCC_AHB1RSTR_USB1OTGHSRST_Msk
+#define RCC_AHB1RSTR_USB2OTGFSRST_Pos          (27U)
+#define RCC_AHB1RSTR_USB2OTGFSRST_Msk          (0x1UL << RCC_AHB1RSTR_USB2OTGFSRST_Pos) /*!< 0x08000000 */
+#define RCC_AHB1RSTR_USB2OTGFSRST              RCC_AHB1RSTR_USB2OTGFSRST_Msk
+
+/* Legacy define */
+#define RCC_AHB1RSTR_USB2OTGHSRST_Pos          RCC_AHB1RSTR_USB2OTGFSRST_Pos
+#define RCC_AHB1RSTR_USB2OTGHSRST_Msk          RCC_AHB1RSTR_USB2OTGFSRST_Msk
+#define RCC_AHB1RSTR_USB2OTGHSRST              RCC_AHB1RSTR_USB2OTGFSRST
+
+/********************  Bit definition for RCC_AHB2RSTR register  ***************/
+#define RCC_AHB2RSTR_DCMIRST_Pos               (0U)
+#define RCC_AHB2RSTR_DCMIRST_Msk               (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)       /*!< 0x00000001 */
+#define RCC_AHB2RSTR_DCMIRST                   RCC_AHB2RSTR_DCMIRST_Msk
+#define RCC_AHB2RSTR_RNGRST_Pos                (6U)
+#define RCC_AHB2RSTR_RNGRST_Msk                (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)        /*!< 0x00000040 */
+#define RCC_AHB2RSTR_RNGRST                    RCC_AHB2RSTR_RNGRST_Msk
+#define RCC_AHB2RSTR_SDMMC2RST_Pos             (9U)
+#define RCC_AHB2RSTR_SDMMC2RST_Msk             (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos)     /*!< 0x00000200 */
+#define RCC_AHB2RSTR_SDMMC2RST                 RCC_AHB2RSTR_SDMMC2RST_Msk
+
+/********************  Bit definition for RCC_AHB4RSTR register  ******************/
+#define RCC_AHB4RSTR_GPIOARST_Pos              (0U)
+#define RCC_AHB4RSTR_GPIOARST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos)      /*!< 0x00000001 */
+#define RCC_AHB4RSTR_GPIOARST                  RCC_AHB4RSTR_GPIOARST_Msk
+#define RCC_AHB4RSTR_GPIOBRST_Pos              (1U)
+#define RCC_AHB4RSTR_GPIOBRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos)      /*!< 0x00000002 */
+#define RCC_AHB4RSTR_GPIOBRST                  RCC_AHB4RSTR_GPIOBRST_Msk
+#define RCC_AHB4RSTR_GPIOCRST_Pos              (2U)
+#define RCC_AHB4RSTR_GPIOCRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos)      /*!< 0x00000004 */
+#define RCC_AHB4RSTR_GPIOCRST                  RCC_AHB4RSTR_GPIOCRST_Msk
+#define RCC_AHB4RSTR_GPIODRST_Pos              (3U)
+#define RCC_AHB4RSTR_GPIODRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos)      /*!< 0x00000008 */
+#define RCC_AHB4RSTR_GPIODRST                  RCC_AHB4RSTR_GPIODRST_Msk
+#define RCC_AHB4RSTR_GPIOERST_Pos              (4U)
+#define RCC_AHB4RSTR_GPIOERST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos)      /*!< 0x00000010 */
+#define RCC_AHB4RSTR_GPIOERST                  RCC_AHB4RSTR_GPIOERST_Msk
+#define RCC_AHB4RSTR_GPIOFRST_Pos              (5U)
+#define RCC_AHB4RSTR_GPIOFRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos)       /*!< 0x00000020 */
+#define RCC_AHB4RSTR_GPIOFRST                  RCC_AHB4RSTR_GPIOFRST_Msk
+#define RCC_AHB4RSTR_GPIOGRST_Pos              (6U)
+#define RCC_AHB4RSTR_GPIOGRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos)       /*!< 0x00000040 */
+#define RCC_AHB4RSTR_GPIOGRST                  RCC_AHB4RSTR_GPIOGRST_Msk
+#define RCC_AHB4RSTR_GPIOHRST_Pos              (7U)
+#define RCC_AHB4RSTR_GPIOHRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos)       /*!< 0x00000080 */
+#define RCC_AHB4RSTR_GPIOHRST                  RCC_AHB4RSTR_GPIOHRST_Msk
+#define RCC_AHB4RSTR_GPIOIRST_Pos              (8U)
+#define RCC_AHB4RSTR_GPIOIRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOIRST_Pos)       /*!< 0x00000100 */
+#define RCC_AHB4RSTR_GPIOIRST                  RCC_AHB4RSTR_GPIOIRST_Msk
+#define RCC_AHB4RSTR_GPIOJRST_Pos              (9U)
+#define RCC_AHB4RSTR_GPIOJRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOJRST_Pos)       /*!< 0x00000200 */
+#define RCC_AHB4RSTR_GPIOJRST                  RCC_AHB4RSTR_GPIOJRST_Msk
+#define RCC_AHB4RSTR_GPIOKRST_Pos              (10U)
+#define RCC_AHB4RSTR_GPIOKRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOKRST_Pos)       /*!< 0x00000400 */
+#define RCC_AHB4RSTR_GPIOKRST                  RCC_AHB4RSTR_GPIOKRST_Msk
+#define RCC_AHB4RSTR_CRCRST_Pos                (19U)
+#define RCC_AHB4RSTR_CRCRST_Msk                (0x1UL << RCC_AHB4RSTR_CRCRST_Pos)         /*!< 0x00080000 */
+#define RCC_AHB4RSTR_CRCRST                    RCC_AHB4RSTR_CRCRST_Msk
+#define RCC_AHB4RSTR_BDMARST_Pos               (21U)
+#define RCC_AHB4RSTR_BDMARST_Msk               (0x1UL << RCC_AHB4RSTR_BDMARST_Pos)        /*!< 0x00200000 */
+#define RCC_AHB4RSTR_BDMARST                   RCC_AHB4RSTR_BDMARST_Msk
+#define RCC_AHB4RSTR_ADC3RST_Pos               (24U)
+#define RCC_AHB4RSTR_ADC3RST_Msk               (0x1UL << RCC_AHB4RSTR_ADC3RST_Pos)        /*!< 0x01000000 */
+#define RCC_AHB4RSTR_ADC3RST                   RCC_AHB4RSTR_ADC3RST_Msk
+#define RCC_AHB4RSTR_HSEMRST_Pos               (25U)
+#define RCC_AHB4RSTR_HSEMRST_Msk               (0x1UL << RCC_AHB4RSTR_HSEMRST_Pos)        /*!< 0x02000000 */
+#define RCC_AHB4RSTR_HSEMRST                   RCC_AHB4RSTR_HSEMRST_Msk
+
+
+/********************  Bit definition for RCC_APB3RSTR register  ******************/
+#define RCC_APB3RSTR_LTDCRST_Pos               (3U)
+#define RCC_APB3RSTR_LTDCRST_Msk               (0x1UL << RCC_APB3RSTR_LTDCRST_Pos) /*!< 0x00000008 */
+#define RCC_APB3RSTR_LTDCRST                   RCC_APB3RSTR_LTDCRST_Msk
+
+/********************  Bit definition for RCC_APB1LRSTR register  ******************/
+
+#define RCC_APB1LRSTR_TIM2RST_Pos              (0U)
+#define RCC_APB1LRSTR_TIM2RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1LRSTR_TIM2RST                  RCC_APB1LRSTR_TIM2RST_Msk
+#define RCC_APB1LRSTR_TIM3RST_Pos              (1U)
+#define RCC_APB1LRSTR_TIM3RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1LRSTR_TIM3RST                  RCC_APB1LRSTR_TIM3RST_Msk
+#define RCC_APB1LRSTR_TIM4RST_Pos              (2U)
+#define RCC_APB1LRSTR_TIM4RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1LRSTR_TIM4RST                  RCC_APB1LRSTR_TIM4RST_Msk
+#define RCC_APB1LRSTR_TIM5RST_Pos              (3U)
+#define RCC_APB1LRSTR_TIM5RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos) /*!< 0x00000008 */
+#define RCC_APB1LRSTR_TIM5RST                  RCC_APB1LRSTR_TIM5RST_Msk
+#define RCC_APB1LRSTR_TIM6RST_Pos              (4U)
+#define RCC_APB1LRSTR_TIM6RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1LRSTR_TIM6RST                  RCC_APB1LRSTR_TIM6RST_Msk
+#define RCC_APB1LRSTR_TIM7RST_Pos              (5U)
+#define RCC_APB1LRSTR_TIM7RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1LRSTR_TIM7RST                  RCC_APB1LRSTR_TIM7RST_Msk
+#define RCC_APB1LRSTR_TIM12RST_Pos             (6U)
+#define RCC_APB1LRSTR_TIM12RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos) /*!< 0x00000040 */
+#define RCC_APB1LRSTR_TIM12RST                 RCC_APB1LRSTR_TIM12RST_Msk
+#define RCC_APB1LRSTR_TIM13RST_Pos             (7U)
+#define RCC_APB1LRSTR_TIM13RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM13RST_Pos) /*!< 0x00000080 */
+#define RCC_APB1LRSTR_TIM13RST                 RCC_APB1LRSTR_TIM13RST_Msk
+#define RCC_APB1LRSTR_TIM14RST_Pos             (8U)
+#define RCC_APB1LRSTR_TIM14RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM14RST_Pos) /*!< 0x00000100 */
+#define RCC_APB1LRSTR_TIM14RST                 RCC_APB1LRSTR_TIM14RST_Msk
+#define RCC_APB1LRSTR_LPTIM1RST_Pos            (9U)
+#define RCC_APB1LRSTR_LPTIM1RST_Msk            (0x1UL << RCC_APB1LRSTR_LPTIM1RST_Pos) /*!< 0x00000200 */
+#define RCC_APB1LRSTR_LPTIM1RST                RCC_APB1LRSTR_LPTIM1RST_Msk
+#define RCC_APB1LRSTR_SPI2RST_Pos              (14U)
+#define RCC_APB1LRSTR_SPI2RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1LRSTR_SPI2RST                  RCC_APB1LRSTR_SPI2RST_Msk
+#define RCC_APB1LRSTR_SPI3RST_Pos              (15U)
+#define RCC_APB1LRSTR_SPI3RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos) /*!< 0x00008000 */
+#define RCC_APB1LRSTR_SPI3RST                  RCC_APB1LRSTR_SPI3RST_Msk
+#define RCC_APB1LRSTR_SPDIFRXRST_Pos           (16U)
+#define RCC_APB1LRSTR_SPDIFRXRST_Msk           (0x1UL << RCC_APB1LRSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */
+#define RCC_APB1LRSTR_SPDIFRXRST               RCC_APB1LRSTR_SPDIFRXRST_Msk
+#define RCC_APB1LRSTR_USART2RST_Pos            (17U)
+#define RCC_APB1LRSTR_USART2RST_Msk            (0x1UL << RCC_APB1LRSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1LRSTR_USART2RST                RCC_APB1LRSTR_USART2RST_Msk
+#define RCC_APB1LRSTR_USART3RST_Pos            (18U)
+#define RCC_APB1LRSTR_USART3RST_Msk            (0x1UL << RCC_APB1LRSTR_USART3RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1LRSTR_USART3RST                RCC_APB1LRSTR_USART3RST_Msk
+#define RCC_APB1LRSTR_UART4RST_Pos             (19U)
+#define RCC_APB1LRSTR_UART4RST_Msk             (0x1UL << RCC_APB1LRSTR_UART4RST_Pos) /*!< 0x00080000 */
+#define RCC_APB1LRSTR_UART4RST                 RCC_APB1LRSTR_UART4RST_Msk
+#define RCC_APB1LRSTR_UART5RST_Pos             (20U)
+#define RCC_APB1LRSTR_UART5RST_Msk             (0x1UL << RCC_APB1LRSTR_UART5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB1LRSTR_UART5RST                 RCC_APB1LRSTR_UART5RST_Msk
+#define RCC_APB1LRSTR_I2C1RST_Pos              (21U)
+#define RCC_APB1LRSTR_I2C1RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1LRSTR_I2C1RST                  RCC_APB1LRSTR_I2C1RST_Msk
+#define RCC_APB1LRSTR_I2C2RST_Pos              (22U)
+#define RCC_APB1LRSTR_I2C2RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1LRSTR_I2C2RST                  RCC_APB1LRSTR_I2C2RST_Msk
+#define RCC_APB1LRSTR_I2C3RST_Pos              (23U)
+#define RCC_APB1LRSTR_I2C3RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C3RST_Pos) /*!< 0x00800000 */
+#define RCC_APB1LRSTR_I2C3RST                  RCC_APB1LRSTR_I2C3RST_Msk
+#define RCC_APB1LRSTR_CECRST_Pos               (27U)
+#define RCC_APB1LRSTR_CECRST_Msk               (0x1UL << RCC_APB1LRSTR_CECRST_Pos) /*!< 0x08000000 */
+#define RCC_APB1LRSTR_CECRST                   RCC_APB1LRSTR_CECRST_Msk
+#define RCC_APB1LRSTR_DAC12RST_Pos             (29U)
+#define RCC_APB1LRSTR_DAC12RST_Msk             (0x1UL << RCC_APB1LRSTR_DAC12RST_Pos) /*!< 0x20000000 */
+#define RCC_APB1LRSTR_DAC12RST                 RCC_APB1LRSTR_DAC12RST_Msk
+#define RCC_APB1LRSTR_UART7RST_Pos             (30U)
+#define RCC_APB1LRSTR_UART7RST_Msk             (0x1UL << RCC_APB1LRSTR_UART7RST_Pos) /*!< 0x40000000 */
+#define RCC_APB1LRSTR_UART7RST                 RCC_APB1LRSTR_UART7RST_Msk
+#define RCC_APB1LRSTR_UART8RST_Pos             (31U)
+#define RCC_APB1LRSTR_UART8RST_Msk             (0x1UL << RCC_APB1LRSTR_UART8RST_Pos) /*!< 0x80000000 */
+#define RCC_APB1LRSTR_UART8RST                 RCC_APB1LRSTR_UART8RST_Msk
+
+/* Legacy define */
+#define RCC_APB1LRSTR_HDMICECRST_Pos           RCC_APB1LRSTR_CECRST_Pos
+#define RCC_APB1LRSTR_HDMICECRST_Msk           RCC_APB1LRSTR_CECRST_Msk
+#define RCC_APB1LRSTR_HDMICECRST               RCC_APB1LRSTR_CECRST
+/********************  Bit definition for RCC_APB1HRSTR register  ******************/
+#define RCC_APB1HRSTR_CRSRST_Pos               (1U)
+#define RCC_APB1HRSTR_CRSRST_Msk               (0x1UL << RCC_APB1HRSTR_CRSRST_Pos) /*!< 0x00000002 */
+#define RCC_APB1HRSTR_CRSRST                   RCC_APB1HRSTR_CRSRST_Msk
+#define RCC_APB1HRSTR_SWPMIRST_Pos             (2U)
+#define RCC_APB1HRSTR_SWPMIRST_Msk             (0x1UL << RCC_APB1HRSTR_SWPMIRST_Pos) /*!< 0x00000004 */
+#define RCC_APB1HRSTR_SWPMIRST                 RCC_APB1HRSTR_SWPMIRST_Msk
+#define RCC_APB1HRSTR_OPAMPRST_Pos             (4U)
+#define RCC_APB1HRSTR_OPAMPRST_Msk             (0x1UL << RCC_APB1HRSTR_OPAMPRST_Pos) /*!< 0x00000010 */
+#define RCC_APB1HRSTR_OPAMPRST                 RCC_APB1HRSTR_OPAMPRST_Msk
+#define RCC_APB1HRSTR_MDIOSRST_Pos             (5U)
+#define RCC_APB1HRSTR_MDIOSRST_Msk             (0x1UL << RCC_APB1HRSTR_MDIOSRST_Pos) /*!< 0x00000020 */
+#define RCC_APB1HRSTR_MDIOSRST                 RCC_APB1HRSTR_MDIOSRST_Msk
+#define RCC_APB1HRSTR_FDCANRST_Pos             (8U)
+#define RCC_APB1HRSTR_FDCANRST_Msk             (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos) /*!< 0x00000100 */
+#define RCC_APB1HRSTR_FDCANRST                 RCC_APB1HRSTR_FDCANRST_Msk
+
+/********************  Bit definition for RCC_APB2RSTR register  ******************/
+#define RCC_APB2RSTR_TIM1RST_Pos               (0U)
+#define RCC_APB2RSTR_TIM1RST_Msk               (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_TIM1RST                   RCC_APB2RSTR_TIM1RST_Msk
+#define RCC_APB2RSTR_TIM8RST_Pos               (1U)
+#define RCC_APB2RSTR_TIM8RST_Msk               (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
+#define RCC_APB2RSTR_TIM8RST                   RCC_APB2RSTR_TIM8RST_Msk
+#define RCC_APB2RSTR_USART1RST_Pos             (4U)
+#define RCC_APB2RSTR_USART1RST_Msk             (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTR_USART1RST                 RCC_APB2RSTR_USART1RST_Msk
+#define RCC_APB2RSTR_USART6RST_Pos             (5U)
+#define RCC_APB2RSTR_USART6RST_Msk             (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_USART6RST                 RCC_APB2RSTR_USART6RST_Msk
+#define RCC_APB2RSTR_SPI1RST_Pos               (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk               (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST                   RCC_APB2RSTR_SPI1RST_Msk
+#define RCC_APB2RSTR_SPI4RST_Pos               (13U)
+#define RCC_APB2RSTR_SPI4RST_Msk               (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
+#define RCC_APB2RSTR_SPI4RST                   RCC_APB2RSTR_SPI4RST_Msk
+#define RCC_APB2RSTR_TIM15RST_Pos              (16U)
+#define RCC_APB2RSTR_TIM15RST_Msk              (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
+#define RCC_APB2RSTR_TIM15RST                  RCC_APB2RSTR_TIM15RST_Msk
+#define RCC_APB2RSTR_TIM16RST_Pos              (17U)
+#define RCC_APB2RSTR_TIM16RST_Msk              (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
+#define RCC_APB2RSTR_TIM16RST                  RCC_APB2RSTR_TIM16RST_Msk
+#define RCC_APB2RSTR_TIM17RST_Pos              (18U)
+#define RCC_APB2RSTR_TIM17RST_Msk              (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
+#define RCC_APB2RSTR_TIM17RST                  RCC_APB2RSTR_TIM17RST_Msk
+#define RCC_APB2RSTR_SPI5RST_Pos               (20U)
+#define RCC_APB2RSTR_SPI5RST_Msk               (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB2RSTR_SPI5RST                   RCC_APB2RSTR_SPI5RST_Msk
+#define RCC_APB2RSTR_SAI1RST_Pos               (22U)
+#define RCC_APB2RSTR_SAI1RST_Msk               (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */
+#define RCC_APB2RSTR_SAI1RST                   RCC_APB2RSTR_SAI1RST_Msk
+#define RCC_APB2RSTR_SAI2RST_Pos               (23U)
+#define RCC_APB2RSTR_SAI2RST_Msk               (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */
+#define RCC_APB2RSTR_SAI2RST                   RCC_APB2RSTR_SAI2RST_Msk
+#define RCC_APB2RSTR_SAI3RST_Pos               (24U)
+#define RCC_APB2RSTR_SAI3RST_Msk               (0x1UL << RCC_APB2RSTR_SAI3RST_Pos) /*!< 0x01000000 */
+#define RCC_APB2RSTR_SAI3RST                   RCC_APB2RSTR_SAI3RST_Msk
+#define RCC_APB2RSTR_DFSDM1RST_Pos             (28U)
+#define RCC_APB2RSTR_DFSDM1RST_Msk             (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x10000000 */
+#define RCC_APB2RSTR_DFSDM1RST                 RCC_APB2RSTR_DFSDM1RST_Msk
+#define RCC_APB2RSTR_HRTIMRST_Pos              (29U)
+#define RCC_APB2RSTR_HRTIMRST_Msk              (0x1UL << RCC_APB2RSTR_HRTIMRST_Pos) /*!< 0x20000000 */
+#define RCC_APB2RSTR_HRTIMRST                  RCC_APB2RSTR_HRTIMRST_Msk
+
+/********************  Bit definition for RCC_APB4RSTR register  ******************/
+#define RCC_APB4RSTR_SYSCFGRST_Pos             (1U)
+#define RCC_APB4RSTR_SYSCFGRST_Msk             (0x1UL << RCC_APB4RSTR_SYSCFGRST_Pos) /*!< 0x00000002 */
+#define RCC_APB4RSTR_SYSCFGRST                 RCC_APB4RSTR_SYSCFGRST_Msk
+#define RCC_APB4RSTR_LPUART1RST_Pos            (3U)
+#define RCC_APB4RSTR_LPUART1RST_Msk            (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos) /*!< 0x00000008 */
+#define RCC_APB4RSTR_LPUART1RST                RCC_APB4RSTR_LPUART1RST_Msk
+#define RCC_APB4RSTR_SPI6RST_Pos               (5U)
+#define RCC_APB4RSTR_SPI6RST_Msk               (0x1UL << RCC_APB4RSTR_SPI6RST_Pos) /*!< 0x00000020 */
+#define RCC_APB4RSTR_SPI6RST                   RCC_APB4RSTR_SPI6RST_Msk
+#define RCC_APB4RSTR_I2C4RST_Pos               (7U)
+#define RCC_APB4RSTR_I2C4RST_Msk               (0x1UL << RCC_APB4RSTR_I2C4RST_Pos) /*!< 0x00000080 */
+#define RCC_APB4RSTR_I2C4RST                   RCC_APB4RSTR_I2C4RST_Msk
+#define RCC_APB4RSTR_LPTIM2RST_Pos             (9U)
+#define RCC_APB4RSTR_LPTIM2RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos) /*!< 0x00000200 */
+#define RCC_APB4RSTR_LPTIM2RST                 RCC_APB4RSTR_LPTIM2RST_Msk
+#define RCC_APB4RSTR_LPTIM3RST_Pos             (10U)
+#define RCC_APB4RSTR_LPTIM3RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos) /*!< 0x00000400 */
+#define RCC_APB4RSTR_LPTIM3RST                 RCC_APB4RSTR_LPTIM3RST_Msk
+#define RCC_APB4RSTR_LPTIM4RST_Pos             (11U)
+#define RCC_APB4RSTR_LPTIM4RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM4RST_Pos) /*!< 0x00000800 */
+#define RCC_APB4RSTR_LPTIM4RST                 RCC_APB4RSTR_LPTIM4RST_Msk
+#define RCC_APB4RSTR_LPTIM5RST_Pos             (12U)
+#define RCC_APB4RSTR_LPTIM5RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM5RST_Pos) /*!< 0x00001000 */
+#define RCC_APB4RSTR_LPTIM5RST                 RCC_APB4RSTR_LPTIM5RST_Msk
+#define RCC_APB4RSTR_COMP12RST_Pos             (14U)
+#define RCC_APB4RSTR_COMP12RST_Msk             (0x1UL << RCC_APB4RSTR_COMP12RST_Pos) /*!< 0x00004000 */
+#define RCC_APB4RSTR_COMP12RST                 RCC_APB4RSTR_COMP12RST_Msk
+#define RCC_APB4RSTR_VREFRST_Pos               (15U)
+#define RCC_APB4RSTR_VREFRST_Msk               (0x1UL << RCC_APB4RSTR_VREFRST_Pos) /*!< 0x00008000 */
+#define RCC_APB4RSTR_VREFRST                   RCC_APB4RSTR_VREFRST_Msk
+#define RCC_APB4RSTR_SAI4RST_Pos               (21U)
+#define RCC_APB4RSTR_SAI4RST_Msk               (0x1UL << RCC_APB4RSTR_SAI4RST_Pos) /*!< 0x00200000 */
+#define RCC_APB4RSTR_SAI4RST                   RCC_APB4RSTR_SAI4RST_Msk
+
+
+/********************  Bit definition for RCC_GCR register  ********************/
+#define RCC_GCR_WW1RSC_Pos                     (0U)
+#define RCC_GCR_WW1RSC_Msk                     (0x1UL << RCC_GCR_WW1RSC_Pos)   /*!< 0x00000001 */
+#define RCC_GCR_WW1RSC                         RCC_GCR_WW1RSC_Msk
+
+/********************  Bit definition for RCC_D3AMR register  ********************/
+#define RCC_D3AMR_BDMAAMEN_Pos                 (0U)
+#define RCC_D3AMR_BDMAAMEN_Msk                 (0x1UL << RCC_D3AMR_BDMAAMEN_Pos) /*!< 0x00000001 */
+#define RCC_D3AMR_BDMAAMEN                     RCC_D3AMR_BDMAAMEN_Msk
+#define RCC_D3AMR_LPUART1AMEN_Pos              (3U)
+#define RCC_D3AMR_LPUART1AMEN_Msk              (0x1UL << RCC_D3AMR_LPUART1AMEN_Pos) /*!< 0x00000008 */
+#define RCC_D3AMR_LPUART1AMEN                  RCC_D3AMR_LPUART1AMEN_Msk
+#define RCC_D3AMR_SPI6AMEN_Pos                 (5U)
+#define RCC_D3AMR_SPI6AMEN_Msk                 (0x1UL << RCC_D3AMR_SPI6AMEN_Pos) /*!< 0x00000020 */
+#define RCC_D3AMR_SPI6AMEN                     RCC_D3AMR_SPI6AMEN_Msk
+#define RCC_D3AMR_I2C4AMEN_Pos                 (7U)
+#define RCC_D3AMR_I2C4AMEN_Msk                 (0x1UL << RCC_D3AMR_I2C4AMEN_Pos) /*!< 0x00000080 */
+#define RCC_D3AMR_I2C4AMEN                     RCC_D3AMR_I2C4AMEN_Msk
+#define RCC_D3AMR_LPTIM2AMEN_Pos               (9U)
+#define RCC_D3AMR_LPTIM2AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM2AMEN_Pos) /*!< 0x00000200 */
+#define RCC_D3AMR_LPTIM2AMEN                   RCC_D3AMR_LPTIM2AMEN_Msk
+#define RCC_D3AMR_LPTIM3AMEN_Pos               (10U)
+#define RCC_D3AMR_LPTIM3AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM3AMEN_Pos) /*!< 0x00000400 */
+#define RCC_D3AMR_LPTIM3AMEN                   RCC_D3AMR_LPTIM3AMEN_Msk
+#define RCC_D3AMR_LPTIM4AMEN_Pos               (11U)
+#define RCC_D3AMR_LPTIM4AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM4AMEN_Pos) /*!< 0x00000800 */
+#define RCC_D3AMR_LPTIM4AMEN                   RCC_D3AMR_LPTIM4AMEN_Msk
+#define RCC_D3AMR_LPTIM5AMEN_Pos               (12U)
+#define RCC_D3AMR_LPTIM5AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM5AMEN_Pos) /*!< 0x00001000 */
+#define RCC_D3AMR_LPTIM5AMEN                   RCC_D3AMR_LPTIM5AMEN_Msk
+#define RCC_D3AMR_COMP12AMEN_Pos               (14U)
+#define RCC_D3AMR_COMP12AMEN_Msk               (0x1UL << RCC_D3AMR_COMP12AMEN_Pos) /*!< 0x00004000 */
+#define RCC_D3AMR_COMP12AMEN                   RCC_D3AMR_COMP12AMEN_Msk
+#define RCC_D3AMR_VREFAMEN_Pos                 (15U)
+#define RCC_D3AMR_VREFAMEN_Msk                 (0x1UL << RCC_D3AMR_VREFAMEN_Pos) /*!< 0x00008000 */
+#define RCC_D3AMR_VREFAMEN                     RCC_D3AMR_VREFAMEN_Msk
+#define RCC_D3AMR_RTCAMEN_Pos                  (16U)
+#define RCC_D3AMR_RTCAMEN_Msk                  (0x1UL << RCC_D3AMR_RTCAMEN_Pos) /*!< 0x00010000 */
+#define RCC_D3AMR_RTCAMEN                      RCC_D3AMR_RTCAMEN_Msk
+#define RCC_D3AMR_CRCAMEN_Pos                  (19U)
+#define RCC_D3AMR_CRCAMEN_Msk                  (0x1UL << RCC_D3AMR_CRCAMEN_Pos) /*!< 0x00080000 */
+#define RCC_D3AMR_CRCAMEN                      RCC_D3AMR_CRCAMEN_Msk
+#define RCC_D3AMR_SAI4AMEN_Pos                 (21U)
+#define RCC_D3AMR_SAI4AMEN_Msk                 (0x1UL << RCC_D3AMR_SAI4AMEN_Pos) /*!< 0x00200000 */
+#define RCC_D3AMR_SAI4AMEN                     RCC_D3AMR_SAI4AMEN_Msk
+#define RCC_D3AMR_ADC3AMEN_Pos                 (24U)
+#define RCC_D3AMR_ADC3AMEN_Msk                 (0x1UL << RCC_D3AMR_ADC3AMEN_Pos) /*!< 0x01000000 */
+#define RCC_D3AMR_ADC3AMEN                     RCC_D3AMR_ADC3AMEN_Msk
+
+
+#define RCC_D3AMR_BKPRAMAMEN_Pos               (28U)
+#define RCC_D3AMR_BKPRAMAMEN_Msk               (0x1UL << RCC_D3AMR_BKPRAMAMEN_Pos) /*!< 0x10000000 */
+#define RCC_D3AMR_BKPRAMAMEN                   RCC_D3AMR_BKPRAMAMEN_Msk
+#define RCC_D3AMR_SRAM4AMEN_Pos                (29U)
+#define RCC_D3AMR_SRAM4AMEN_Msk                (0x1UL << RCC_D3AMR_SRAM4AMEN_Pos) /*!< 0x20000000 */
+#define RCC_D3AMR_SRAM4AMEN                    RCC_D3AMR_SRAM4AMEN_Msk
+/********************  Bit definition for RCC_AHB3LPENR register  **************/
+#define RCC_AHB3LPENR_MDMALPEN_Pos             (0U)
+#define RCC_AHB3LPENR_MDMALPEN_Msk             (0x1UL << RCC_AHB3LPENR_MDMALPEN_Pos)         /*!< 0x00000001 */
+#define RCC_AHB3LPENR_MDMALPEN                 RCC_AHB3LPENR_MDMALPEN_Msk
+#define RCC_AHB3LPENR_DMA2DLPEN_Pos            (4U)
+#define RCC_AHB3LPENR_DMA2DLPEN_Msk            (0x1UL << RCC_AHB3LPENR_DMA2DLPEN_Pos)        /*!< 0x00000010 */
+#define RCC_AHB3LPENR_DMA2DLPEN                RCC_AHB3LPENR_DMA2DLPEN_Msk
+#define RCC_AHB3LPENR_JPGDECLPEN_Pos           (5U)
+#define RCC_AHB3LPENR_JPGDECLPEN_Msk           (0x1UL << RCC_AHB3LPENR_JPGDECLPEN_Pos)       /*!< 0x00000020 */
+#define RCC_AHB3LPENR_JPGDECLPEN               RCC_AHB3LPENR_JPGDECLPEN_Msk
+#define RCC_AHB3LPENR_FLASHLPEN_Pos            (8U)
+#define RCC_AHB3LPENR_FLASHLPEN_Msk            (0x1UL << RCC_AHB3LPENR_FLASHLPEN_Pos)        /*!< 0x00000100 */
+#define RCC_AHB3LPENR_FLASHLPEN                RCC_AHB3LPENR_FLASHLPEN_Msk
+#define RCC_AHB3LPENR_FMCLPEN_Pos              (12U)
+#define RCC_AHB3LPENR_FMCLPEN_Msk              (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos)          /*!< 0x00001000 */
+#define RCC_AHB3LPENR_FMCLPEN                  RCC_AHB3LPENR_FMCLPEN_Msk
+#define RCC_AHB3LPENR_QSPILPEN_Pos             (14U)
+#define RCC_AHB3LPENR_QSPILPEN_Msk             (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos)         /*!< 0x00004000 */
+#define RCC_AHB3LPENR_QSPILPEN                 RCC_AHB3LPENR_QSPILPEN_Msk
+#define RCC_AHB3LPENR_SDMMC1LPEN_Pos           (16U)
+#define RCC_AHB3LPENR_SDMMC1LPEN_Msk           (0x1UL << RCC_AHB3LPENR_SDMMC1LPEN_Pos)       /*!< 0x00010000 */
+#define RCC_AHB3LPENR_SDMMC1LPEN               RCC_AHB3LPENR_SDMMC1LPEN_Msk
+#define RCC_AHB3LPENR_DTCM1LPEN_Pos            (28U)
+#define RCC_AHB3LPENR_DTCM1LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM1LPEN_Pos)        /*!< 0x10000000 */
+#define RCC_AHB3LPENR_DTCM1LPEN                RCC_AHB3LPENR_DTCM1LPEN_Msk
+#define RCC_AHB3LPENR_DTCM2LPEN_Pos            (29U)
+#define RCC_AHB3LPENR_DTCM2LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM2LPEN_Pos)        /*!< 0x20000000 */
+#define RCC_AHB3LPENR_DTCM2LPEN                RCC_AHB3LPENR_DTCM2LPEN_Msk
+#define RCC_AHB3LPENR_ITCMLPEN_Pos             (30U)
+#define RCC_AHB3LPENR_ITCMLPEN_Msk             (0x1UL << RCC_AHB3LPENR_ITCMLPEN_Pos)         /*!< 0x40000000 */
+#define RCC_AHB3LPENR_ITCMLPEN                 RCC_AHB3LPENR_ITCMLPEN_Msk
+#define RCC_AHB3LPENR_AXISRAMLPEN_Pos          (31U)
+#define RCC_AHB3LPENR_AXISRAMLPEN_Msk          (0x1UL << RCC_AHB3LPENR_AXISRAMLPEN_Pos)      /*!< 0x80000000 */
+#define RCC_AHB3LPENR_AXISRAMLPEN              RCC_AHB3LPENR_AXISRAMLPEN_Msk
+
+
+/********************  Bit definition for RCC_AHB1LPENR register  ***************/
+#define RCC_AHB1LPENR_DMA1LPEN_Pos             (0U)
+#define RCC_AHB1LPENR_DMA1LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1LPENR_DMA1LPEN                 RCC_AHB1LPENR_DMA1LPEN_Msk
+#define RCC_AHB1LPENR_DMA2LPEN_Pos             (1U)
+#define RCC_AHB1LPENR_DMA2LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1LPENR_DMA2LPEN                 RCC_AHB1LPENR_DMA2LPEN_Msk
+#define RCC_AHB1LPENR_ADC12LPEN_Pos            (5U)
+#define RCC_AHB1LPENR_ADC12LPEN_Msk            (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB1LPENR_ADC12LPEN                RCC_AHB1LPENR_ADC12LPEN_Msk
+#define RCC_AHB1LPENR_ETH1MACLPEN_Pos          (15U)
+#define RCC_AHB1LPENR_ETH1MACLPEN_Msk          (0x1UL << RCC_AHB1LPENR_ETH1MACLPEN_Pos) /*!< 0x00008000 */
+#define RCC_AHB1LPENR_ETH1MACLPEN              RCC_AHB1LPENR_ETH1MACLPEN_Msk
+#define RCC_AHB1LPENR_ETH1TXLPEN_Pos           (16U)
+#define RCC_AHB1LPENR_ETH1TXLPEN_Msk           (0x1UL << RCC_AHB1LPENR_ETH1TXLPEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB1LPENR_ETH1TXLPEN               RCC_AHB1LPENR_ETH1TXLPEN_Msk
+#define RCC_AHB1LPENR_ETH1RXLPEN_Pos           (17U)
+#define RCC_AHB1LPENR_ETH1RXLPEN_Msk           (0x1UL << RCC_AHB1LPENR_ETH1RXLPEN_Pos) /*!< 0x00020000 */
+#define RCC_AHB1LPENR_ETH1RXLPEN               RCC_AHB1LPENR_ETH1RXLPEN_Msk
+#define RCC_AHB1LPENR_USB1OTGHSLPEN_Pos        (25U)
+#define RCC_AHB1LPENR_USB1OTGHSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_USB1OTGHSLPEN_Pos) /*!< 0x02000000 */
+#define RCC_AHB1LPENR_USB1OTGHSLPEN            RCC_AHB1LPENR_USB1OTGHSLPEN_Msk
+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos    (26U)
+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos) /*!< 0x04000000 */
+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN        RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk
+#define RCC_AHB1LPENR_USB2OTGFSLPEN_Pos        (27U)
+#define RCC_AHB1LPENR_USB2OTGFSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_USB2OTGFSLPEN_Pos) /*!< 0x08000000 */
+#define RCC_AHB1LPENR_USB2OTGFSLPEN            RCC_AHB1LPENR_USB2OTGFSLPEN_Msk
+#define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos    (28U)
+#define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos) /*!< 0x10000000 */
+#define RCC_AHB1LPENR_USB2OTGFSULPILPEN        RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk
+
+/* Legacy define */
+#define RCC_AHB1LPENR_USB2OTGHSLPEN_Pos        RCC_AHB1LPENR_USB2OTGFSLPEN_Pos
+#define RCC_AHB1LPENR_USB2OTGHSLPEN_Msk        RCC_AHB1LPENR_USB2OTGFSLPEN_Msk
+#define RCC_AHB1LPENR_USB2OTGHSLPEN            RCC_AHB1LPENR_USB2OTGFSLPEN
+#define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Pos    RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos
+#define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Msk    RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk
+#define RCC_AHB1LPENR_USB2OTGHSULPILPEN        RCC_AHB1LPENR_USB2OTGFSULPILPEN
+
+/********************  Bit definition for RCC_AHB2LPENR register  ***************/
+#define RCC_AHB2LPENR_DCMILPEN_Pos             (0U)
+#define RCC_AHB2LPENR_DCMILPEN_Msk             (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB2LPENR_DCMILPEN                 RCC_AHB2LPENR_DCMILPEN_Msk
+#define RCC_AHB2LPENR_RNGLPEN_Pos              (6U)
+#define RCC_AHB2LPENR_RNGLPEN_Msk              (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB2LPENR_RNGLPEN                  RCC_AHB2LPENR_RNGLPEN_Msk
+#define RCC_AHB2LPENR_SDMMC2LPEN_Pos           (9U)
+#define RCC_AHB2LPENR_SDMMC2LPEN_Msk           (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000200 */
+#define RCC_AHB2LPENR_SDMMC2LPEN               RCC_AHB2LPENR_SDMMC2LPEN_Msk
+#define RCC_AHB2LPENR_SRAM1LPEN_Pos          (29U)
+#define RCC_AHB2LPENR_SRAM1LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM1LPEN_Pos) /*!< 0x20000000 */
+#define RCC_AHB2LPENR_SRAM1LPEN              RCC_AHB2LPENR_SRAM1LPEN_Msk
+#define RCC_AHB2LPENR_SRAM2LPEN_Pos          (30U)
+#define RCC_AHB2LPENR_SRAM2LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM2LPEN_Pos) /*!< 0x40000000 */
+#define RCC_AHB2LPENR_SRAM2LPEN              RCC_AHB2LPENR_SRAM2LPEN_Msk
+#define RCC_AHB2LPENR_SRAM3LPEN_Pos          (31U)
+#define RCC_AHB2LPENR_SRAM3LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM3LPEN_Pos) /*!< 0x80000000 */
+#define RCC_AHB2LPENR_SRAM3LPEN              RCC_AHB2LPENR_SRAM3LPEN_Msk
+
+/* Legacy define */
+#define RCC_AHB2LPENR_D2SRAM1LPEN_Pos          RCC_AHB2LPENR_SRAM1LPEN_Pos
+#define RCC_AHB2LPENR_D2SRAM1LPEN_Msk          RCC_AHB2LPENR_SRAM1LPEN_Msk
+#define RCC_AHB2LPENR_D2SRAM1LPEN              RCC_AHB2LPENR_SRAM1LPEN
+#define RCC_AHB2LPENR_D2SRAM2LPEN_Pos          RCC_AHB2LPENR_SRAM2LPEN_Pos
+#define RCC_AHB2LPENR_D2SRAM2LPEN_Msk          RCC_AHB2LPENR_SRAM2LPEN_Msk
+#define RCC_AHB2LPENR_D2SRAM2LPEN              RCC_AHB2LPENR_SRAM2LPEN
+#define RCC_AHB2LPENR_D2SRAM3LPEN_Pos          RCC_AHB2LPENR_SRAM3LPEN_Pos
+#define RCC_AHB2LPENR_D2SRAM3LPEN_Msk          RCC_AHB2LPENR_SRAM3LPEN_Msk
+#define RCC_AHB2LPENR_D2SRAM3LPEN              RCC_AHB2LPENR_SRAM3LPEN
+
+/********************  Bit definition for RCC_AHB4LPENR register  ******************/
+#define RCC_AHB4LPENR_GPIOALPEN_Pos            (0U)
+#define RCC_AHB4LPENR_GPIOALPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB4LPENR_GPIOALPEN                RCC_AHB4LPENR_GPIOALPEN_Msk
+#define RCC_AHB4LPENR_GPIOBLPEN_Pos            (1U)
+#define RCC_AHB4LPENR_GPIOBLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB4LPENR_GPIOBLPEN                RCC_AHB4LPENR_GPIOBLPEN_Msk
+#define RCC_AHB4LPENR_GPIOCLPEN_Pos            (2U)
+#define RCC_AHB4LPENR_GPIOCLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB4LPENR_GPIOCLPEN                RCC_AHB4LPENR_GPIOCLPEN_Msk
+#define RCC_AHB4LPENR_GPIODLPEN_Pos            (3U)
+#define RCC_AHB4LPENR_GPIODLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB4LPENR_GPIODLPEN                RCC_AHB4LPENR_GPIODLPEN_Msk
+#define RCC_AHB4LPENR_GPIOELPEN_Pos            (4U)
+#define RCC_AHB4LPENR_GPIOELPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB4LPENR_GPIOELPEN                RCC_AHB4LPENR_GPIOELPEN_Msk
+#define RCC_AHB4LPENR_GPIOFLPEN_Pos            (5U)
+#define RCC_AHB4LPENR_GPIOFLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB4LPENR_GPIOFLPEN                RCC_AHB4LPENR_GPIOFLPEN_Msk
+#define RCC_AHB4LPENR_GPIOGLPEN_Pos            (6U)
+#define RCC_AHB4LPENR_GPIOGLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB4LPENR_GPIOGLPEN                RCC_AHB4LPENR_GPIOGLPEN_Msk
+#define RCC_AHB4LPENR_GPIOHLPEN_Pos            (7U)
+#define RCC_AHB4LPENR_GPIOHLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB4LPENR_GPIOHLPEN                RCC_AHB4LPENR_GPIOHLPEN_Msk
+#define RCC_AHB4LPENR_GPIOILPEN_Pos            (8U)
+#define RCC_AHB4LPENR_GPIOILPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB4LPENR_GPIOILPEN                RCC_AHB4LPENR_GPIOILPEN_Msk
+#define RCC_AHB4LPENR_GPIOJLPEN_Pos            (9U)
+#define RCC_AHB4LPENR_GPIOJLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */
+#define RCC_AHB4LPENR_GPIOJLPEN                RCC_AHB4LPENR_GPIOJLPEN_Msk
+#define RCC_AHB4LPENR_GPIOKLPEN_Pos            (10U)
+#define RCC_AHB4LPENR_GPIOKLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */
+#define RCC_AHB4LPENR_GPIOKLPEN                RCC_AHB4LPENR_GPIOKLPEN_Msk
+#define RCC_AHB4LPENR_CRCLPEN_Pos              (19U)
+#define RCC_AHB4LPENR_CRCLPEN_Msk              (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos) /*!< 0x00080000 */
+#define RCC_AHB4LPENR_CRCLPEN                  RCC_AHB4LPENR_CRCLPEN_Msk
+#define RCC_AHB4LPENR_BDMALPEN_Pos             (21U)
+#define RCC_AHB4LPENR_BDMALPEN_Msk             (0x1UL << RCC_AHB4LPENR_BDMALPEN_Pos) /*!< 0x00200000 */
+#define RCC_AHB4LPENR_BDMALPEN                 RCC_AHB4LPENR_BDMALPEN_Msk
+#define RCC_AHB4LPENR_ADC3LPEN_Pos             (24U)
+#define RCC_AHB4LPENR_ADC3LPEN_Msk             (0x1UL << RCC_AHB4LPENR_ADC3LPEN_Pos) /*!< 0x01000000 */
+#define RCC_AHB4LPENR_ADC3LPEN                 RCC_AHB4LPENR_ADC3LPEN_Msk
+#define RCC_AHB4LPENR_BKPRAMLPEN_Pos           (28U)
+#define RCC_AHB4LPENR_BKPRAMLPEN_Msk           (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos) /*!< 0x10000000 */
+#define RCC_AHB4LPENR_BKPRAMLPEN               RCC_AHB4LPENR_BKPRAMLPEN_Msk
+#define RCC_AHB4LPENR_SRAM4LPEN_Pos            (29U)
+#define RCC_AHB4LPENR_SRAM4LPEN_Msk            (0x1UL << RCC_AHB4LPENR_SRAM4LPEN_Pos) /*!< 0x20000000 */
+#define RCC_AHB4LPENR_SRAM4LPEN                RCC_AHB4LPENR_SRAM4LPEN_Msk
+
+/* Legacy define */
+#define RCC_AHB4LPENR_D3SRAM1LPEN_Pos          RCC_AHB4LPENR_SRAM4LPEN_Pos
+#define RCC_AHB4LPENR_D3SRAM1LPEN_Msk          RCC_AHB4LPENR_SRAM4LPEN_Msk
+#define RCC_AHB4LPENR_D3SRAM1LPEN              RCC_AHB4LPENR_SRAM4LPEN
+/********************  Bit definition for RCC_APB3LPENR register  ******************/
+#define RCC_APB3LPENR_LTDCLPEN_Pos             (3U)
+#define RCC_APB3LPENR_LTDCLPEN_Msk             (0x1UL << RCC_APB3LPENR_LTDCLPEN_Pos) /*!< 0x00000008 */
+#define RCC_APB3LPENR_LTDCLPEN                 RCC_APB3LPENR_LTDCLPEN_Msk
+#define RCC_APB3LPENR_WWDG1LPEN_Pos            (6U)
+#define RCC_APB3LPENR_WWDG1LPEN_Msk            (0x1UL << RCC_APB3LPENR_WWDG1LPEN_Pos) /*!< 0x00000040 */
+#define RCC_APB3LPENR_WWDG1LPEN                RCC_APB3LPENR_WWDG1LPEN_Msk
+
+/********************  Bit definition for RCC_APB1LLPENR register  ******************/
+
+#define RCC_APB1LLPENR_TIM2LPEN_Pos            (0U)
+#define RCC_APB1LLPENR_TIM2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1LLPENR_TIM2LPEN                RCC_APB1LLPENR_TIM2LPEN_Msk
+#define RCC_APB1LLPENR_TIM3LPEN_Pos            (1U)
+#define RCC_APB1LLPENR_TIM3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1LLPENR_TIM3LPEN                RCC_APB1LLPENR_TIM3LPEN_Msk
+#define RCC_APB1LLPENR_TIM4LPEN_Pos            (2U)
+#define RCC_APB1LLPENR_TIM4LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1LLPENR_TIM4LPEN                RCC_APB1LLPENR_TIM4LPEN_Msk
+#define RCC_APB1LLPENR_TIM5LPEN_Pos            (3U)
+#define RCC_APB1LLPENR_TIM5LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
+#define RCC_APB1LLPENR_TIM5LPEN                RCC_APB1LLPENR_TIM5LPEN_Msk
+#define RCC_APB1LLPENR_TIM6LPEN_Pos            (4U)
+#define RCC_APB1LLPENR_TIM6LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1LLPENR_TIM6LPEN                RCC_APB1LLPENR_TIM6LPEN_Msk
+#define RCC_APB1LLPENR_TIM7LPEN_Pos            (5U)
+#define RCC_APB1LLPENR_TIM7LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1LLPENR_TIM7LPEN                RCC_APB1LLPENR_TIM7LPEN_Msk
+#define RCC_APB1LLPENR_TIM12LPEN_Pos           (6U)
+#define RCC_APB1LLPENR_TIM12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
+#define RCC_APB1LLPENR_TIM12LPEN               RCC_APB1LLPENR_TIM12LPEN_Msk
+#define RCC_APB1LLPENR_TIM13LPEN_Pos           (7U)
+#define RCC_APB1LLPENR_TIM13LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
+#define RCC_APB1LLPENR_TIM13LPEN               RCC_APB1LLPENR_TIM13LPEN_Msk
+#define RCC_APB1LLPENR_TIM14LPEN_Pos           (8U)
+#define RCC_APB1LLPENR_TIM14LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB1LLPENR_TIM14LPEN               RCC_APB1LLPENR_TIM14LPEN_Msk
+#define RCC_APB1LLPENR_LPTIM1LPEN_Pos          (9U)
+#define RCC_APB1LLPENR_LPTIM1LPEN_Msk          (0x1UL << RCC_APB1LLPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */
+#define RCC_APB1LLPENR_LPTIM1LPEN              RCC_APB1LLPENR_LPTIM1LPEN_Msk
+
+
+#define RCC_APB1LLPENR_SPI2LPEN_Pos            (14U)
+#define RCC_APB1LLPENR_SPI2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB1LLPENR_SPI2LPEN                RCC_APB1LLPENR_SPI2LPEN_Msk
+#define RCC_APB1LLPENR_SPI3LPEN_Pos            (15U)
+#define RCC_APB1LLPENR_SPI3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
+#define RCC_APB1LLPENR_SPI3LPEN                RCC_APB1LLPENR_SPI3LPEN_Msk
+#define RCC_APB1LLPENR_SPDIFRXLPEN_Pos         (16U)
+#define RCC_APB1LLPENR_SPDIFRXLPEN_Msk         (0x1UL << RCC_APB1LLPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */
+#define RCC_APB1LLPENR_SPDIFRXLPEN             RCC_APB1LLPENR_SPDIFRXLPEN_Msk
+#define RCC_APB1LLPENR_USART2LPEN_Pos          (17U)
+#define RCC_APB1LLPENR_USART2LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1LLPENR_USART2LPEN              RCC_APB1LLPENR_USART2LPEN_Msk
+#define RCC_APB1LLPENR_USART3LPEN_Pos          (18U)
+#define RCC_APB1LLPENR_USART3LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1LLPENR_USART3LPEN              RCC_APB1LLPENR_USART3LPEN_Msk
+#define RCC_APB1LLPENR_UART4LPEN_Pos           (19U)
+#define RCC_APB1LLPENR_UART4LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos) /*!< 0x00080000 */
+#define RCC_APB1LLPENR_UART4LPEN               RCC_APB1LLPENR_UART4LPEN_Msk
+#define RCC_APB1LLPENR_UART5LPEN_Pos           (20U)
+#define RCC_APB1LLPENR_UART5LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos) /*!< 0x00100000 */
+#define RCC_APB1LLPENR_UART5LPEN               RCC_APB1LLPENR_UART5LPEN_Msk
+#define RCC_APB1LLPENR_I2C1LPEN_Pos            (21U)
+#define RCC_APB1LLPENR_I2C1LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1LLPENR_I2C1LPEN                RCC_APB1LLPENR_I2C1LPEN_Msk
+#define RCC_APB1LLPENR_I2C2LPEN_Pos            (22U)
+#define RCC_APB1LLPENR_I2C2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_APB1LLPENR_I2C2LPEN                RCC_APB1LLPENR_I2C2LPEN_Msk
+#define RCC_APB1LLPENR_I2C3LPEN_Pos            (23U)
+#define RCC_APB1LLPENR_I2C3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1LLPENR_I2C3LPEN                RCC_APB1LLPENR_I2C3LPEN_Msk
+#define RCC_APB1LLPENR_CECLPEN_Pos             (27U)
+#define RCC_APB1LLPENR_CECLPEN_Msk             (0x1UL << RCC_APB1LLPENR_CECLPEN_Pos) /*!< 0x08000000 */
+#define RCC_APB1LLPENR_CECLPEN                 RCC_APB1LLPENR_CECLPEN_Msk
+#define RCC_APB1LLPENR_DAC12LPEN_Pos           (29U)
+#define RCC_APB1LLPENR_DAC12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_DAC12LPEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1LLPENR_DAC12LPEN               RCC_APB1LLPENR_DAC12LPEN_Msk
+#define RCC_APB1LLPENR_UART7LPEN_Pos           (30U)
+#define RCC_APB1LLPENR_UART7LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART7LPEN_Pos) /*!< 0x40000000 */
+#define RCC_APB1LLPENR_UART7LPEN               RCC_APB1LLPENR_UART7LPEN_Msk
+#define RCC_APB1LLPENR_UART8LPEN_Pos           (31U)
+#define RCC_APB1LLPENR_UART8LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART8LPEN_Pos) /*!< 0x80000000 */
+#define RCC_APB1LLPENR_UART8LPEN               RCC_APB1LLPENR_UART8LPEN_Msk
+
+/* Legacy define */
+#define RCC_APB1LLPENR_HDMICECEN_Pos           RCC_APB1LLPENR_CECLPEN_Pos
+#define RCC_APB1LLPENR_HDMICECEN_Msk           RCC_APB1LLPENR_CECLPEN_Msk
+#define RCC_APB1LLPENR_HDMICECEN               RCC_APB1LLPENR_CECLPEN
+/********************  Bit definition for RCC_APB1HLPENR register  ******************/
+#define RCC_APB1HLPENR_CRSLPEN_Pos             (1U)
+#define RCC_APB1HLPENR_CRSLPEN_Msk             (0x1UL << RCC_APB1HLPENR_CRSLPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1HLPENR_CRSLPEN                 RCC_APB1HLPENR_CRSLPEN_Msk
+#define RCC_APB1HLPENR_SWPMILPEN_Pos           (2U)
+#define RCC_APB1HLPENR_SWPMILPEN_Msk           (0x1UL << RCC_APB1HLPENR_SWPMILPEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1HLPENR_SWPMILPEN               RCC_APB1HLPENR_SWPMILPEN_Msk
+#define RCC_APB1HLPENR_OPAMPLPEN_Pos           (4U)
+#define RCC_APB1HLPENR_OPAMPLPEN_Msk           (0x1UL << RCC_APB1HLPENR_OPAMPLPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1HLPENR_OPAMPLPEN               RCC_APB1HLPENR_OPAMPLPEN_Msk
+#define RCC_APB1HLPENR_MDIOSLPEN_Pos           (5U)
+#define RCC_APB1HLPENR_MDIOSLPEN_Msk           (0x1UL << RCC_APB1HLPENR_MDIOSLPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1HLPENR_MDIOSLPEN               RCC_APB1HLPENR_MDIOSLPEN_Msk
+#define RCC_APB1HLPENR_FDCANLPEN_Pos           (8U)
+#define RCC_APB1HLPENR_FDCANLPEN_Msk           (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB1HLPENR_FDCANLPEN               RCC_APB1HLPENR_FDCANLPEN_Msk
+
+/********************  Bit definition for RCC_APB2LPENR register  ******************/
+#define RCC_APB2LPENR_TIM1LPEN_Pos             (0U)
+#define RCC_APB2LPENR_TIM1LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2LPENR_TIM1LPEN                 RCC_APB2LPENR_TIM1LPEN_Msk
+#define RCC_APB2LPENR_TIM8LPEN_Pos             (1U)
+#define RCC_APB2LPENR_TIM8LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB2LPENR_TIM8LPEN                 RCC_APB2LPENR_TIM8LPEN_Msk
+#define RCC_APB2LPENR_USART1LPEN_Pos           (4U)
+#define RCC_APB2LPENR_USART1LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB2LPENR_USART1LPEN               RCC_APB2LPENR_USART1LPEN_Msk
+#define RCC_APB2LPENR_USART6LPEN_Pos           (5U)
+#define RCC_APB2LPENR_USART6LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2LPENR_USART6LPEN               RCC_APB2LPENR_USART6LPEN_Msk
+#define RCC_APB2LPENR_SPI1LPEN_Pos             (12U)
+#define RCC_APB2LPENR_SPI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2LPENR_SPI1LPEN                 RCC_APB2LPENR_SPI1LPEN_Msk
+#define RCC_APB2LPENR_SPI4LPEN_Pos             (13U)
+#define RCC_APB2LPENR_SPI4LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
+#define RCC_APB2LPENR_SPI4LPEN                 RCC_APB2LPENR_SPI4LPEN_Msk
+#define RCC_APB2LPENR_TIM15LPEN_Pos            (16U)
+#define RCC_APB2LPENR_TIM15LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */
+#define RCC_APB2LPENR_TIM15LPEN                RCC_APB2LPENR_TIM15LPEN_Msk
+#define RCC_APB2LPENR_TIM16LPEN_Pos            (17U)
+#define RCC_APB2LPENR_TIM16LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB2LPENR_TIM16LPEN                RCC_APB2LPENR_TIM16LPEN_Msk
+#define RCC_APB2LPENR_TIM17LPEN_Pos            (18U)
+#define RCC_APB2LPENR_TIM17LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB2LPENR_TIM17LPEN                RCC_APB2LPENR_TIM17LPEN_Msk
+#define RCC_APB2LPENR_SPI5LPEN_Pos             (20U)
+#define RCC_APB2LPENR_SPI5LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
+#define RCC_APB2LPENR_SPI5LPEN                 RCC_APB2LPENR_SPI5LPEN_Msk
+#define RCC_APB2LPENR_SAI1LPEN_Pos             (22U)
+#define RCC_APB2LPENR_SAI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2LPENR_SAI1LPEN                 RCC_APB2LPENR_SAI1LPEN_Msk
+#define RCC_APB2LPENR_SAI2LPEN_Pos             (23U)
+#define RCC_APB2LPENR_SAI2LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */
+#define RCC_APB2LPENR_SAI2LPEN                 RCC_APB2LPENR_SAI2LPEN_Msk
+#define RCC_APB2LPENR_SAI3LPEN_Pos             (24U)
+#define RCC_APB2LPENR_SAI3LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI3LPEN_Pos) /*!< 0x01000000 */
+#define RCC_APB2LPENR_SAI3LPEN                 RCC_APB2LPENR_SAI3LPEN_Msk
+#define RCC_APB2LPENR_DFSDM1LPEN_Pos           (28U)
+#define RCC_APB2LPENR_DFSDM1LPEN_Msk           (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x10000000 */
+#define RCC_APB2LPENR_DFSDM1LPEN               RCC_APB2LPENR_DFSDM1LPEN_Msk
+#define RCC_APB2LPENR_HRTIMLPEN_Pos            (29U)
+#define RCC_APB2LPENR_HRTIMLPEN_Msk            (0x1UL << RCC_APB2LPENR_HRTIMLPEN_Pos) /*!< 0x20000000 */
+#define RCC_APB2LPENR_HRTIMLPEN                RCC_APB2LPENR_HRTIMLPEN_Msk
+
+/********************  Bit definition for RCC_APB4LPENR register  ******************/
+#define RCC_APB4LPENR_SYSCFGLPEN_Pos           (1U)
+#define RCC_APB4LPENR_SYSCFGLPEN_Msk           (0x1UL << RCC_APB4LPENR_SYSCFGLPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB4LPENR_SYSCFGLPEN               RCC_APB4LPENR_SYSCFGLPEN_Msk
+#define RCC_APB4LPENR_LPUART1LPEN_Pos          (3U)
+#define RCC_APB4LPENR_LPUART1LPEN_Msk          (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos) /*!< 0x00000008 */
+#define RCC_APB4LPENR_LPUART1LPEN              RCC_APB4LPENR_LPUART1LPEN_Msk
+#define RCC_APB4LPENR_SPI6LPEN_Pos             (5U)
+#define RCC_APB4LPENR_SPI6LPEN_Msk             (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB4LPENR_SPI6LPEN                 RCC_APB4LPENR_SPI6LPEN_Msk
+#define RCC_APB4LPENR_I2C4LPEN_Pos             (7U)
+#define RCC_APB4LPENR_I2C4LPEN_Msk             (0x1UL << RCC_APB4LPENR_I2C4LPEN_Pos) /*!< 0x00000080 */
+#define RCC_APB4LPENR_I2C4LPEN                 RCC_APB4LPENR_I2C4LPEN_Msk
+#define RCC_APB4LPENR_LPTIM2LPEN_Pos           (9U)
+#define RCC_APB4LPENR_LPTIM2LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos) /*!< 0x00000200 */
+#define RCC_APB4LPENR_LPTIM2LPEN               RCC_APB4LPENR_LPTIM2LPEN_Msk
+#define RCC_APB4LPENR_LPTIM3LPEN_Pos           (10U)
+#define RCC_APB4LPENR_LPTIM3LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos) /*!< 0x00000400 */
+#define RCC_APB4LPENR_LPTIM3LPEN               RCC_APB4LPENR_LPTIM3LPEN_Msk
+#define RCC_APB4LPENR_LPTIM4LPEN_Pos           (11U)
+#define RCC_APB4LPENR_LPTIM4LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM4LPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB4LPENR_LPTIM4LPEN               RCC_APB4LPENR_LPTIM4LPEN_Msk
+#define RCC_APB4LPENR_LPTIM5LPEN_Pos           (12U)
+#define RCC_APB4LPENR_LPTIM5LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM5LPEN_Pos) /*!< 0x00001000 */
+#define RCC_APB4LPENR_LPTIM5LPEN               RCC_APB4LPENR_LPTIM5LPEN_Msk
+#define RCC_APB4LPENR_COMP12LPEN_Pos           (14U)
+#define RCC_APB4LPENR_COMP12LPEN_Msk           (0x1UL << RCC_APB4LPENR_COMP12LPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB4LPENR_COMP12LPEN               RCC_APB4LPENR_COMP12LPEN_Msk
+#define RCC_APB4LPENR_VREFLPEN_Pos             (15U)
+#define RCC_APB4LPENR_VREFLPEN_Msk             (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos) /*!< 0x00008000 */
+#define RCC_APB4LPENR_VREFLPEN                 RCC_APB4LPENR_VREFLPEN_Msk
+#define RCC_APB4LPENR_RTCAPBLPEN_Pos           (16U)
+#define RCC_APB4LPENR_RTCAPBLPEN_Msk           (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos) /*!< 0x00010000 */
+#define RCC_APB4LPENR_RTCAPBLPEN               RCC_APB4LPENR_RTCAPBLPEN_Msk
+#define RCC_APB4LPENR_SAI4LPEN_Pos             (21U)
+#define RCC_APB4LPENR_SAI4LPEN_Msk             (0x1UL << RCC_APB4LPENR_SAI4LPEN_Pos) /*!< 0x00200000 */
+#define RCC_APB4LPENR_SAI4LPEN                 RCC_APB4LPENR_SAI4LPEN_Msk
+
+
+/********************  Bit definition for RCC_RSR register  *******************/
+#define RCC_RSR_RMVF_Pos                       (16U)
+#define RCC_RSR_RMVF_Msk                       (0x1UL << RCC_RSR_RMVF_Pos)     /*!< 0x00010000 */
+#define RCC_RSR_RMVF                           RCC_RSR_RMVF_Msk
+#define RCC_RSR_CPURSTF_Pos                    (17U)
+#define RCC_RSR_CPURSTF_Msk                    (0x1UL << RCC_RSR_CPURSTF_Pos)  /*!< 0x00020000 */
+#define RCC_RSR_CPURSTF                        RCC_RSR_CPURSTF_Msk
+#define RCC_RSR_D1RSTF_Pos                     (19U)
+#define RCC_RSR_D1RSTF_Msk                     (0x1UL << RCC_RSR_D1RSTF_Pos)   /*!< 0x00080000 */
+#define RCC_RSR_D1RSTF                         RCC_RSR_D1RSTF_Msk
+#define RCC_RSR_D2RSTF_Pos                     (20U)
+#define RCC_RSR_D2RSTF_Msk                     (0x1UL << RCC_RSR_D2RSTF_Pos)   /*!< 0x00100000 */
+#define RCC_RSR_D2RSTF                         RCC_RSR_D2RSTF_Msk
+#define RCC_RSR_BORRSTF_Pos                    (21U)
+#define RCC_RSR_BORRSTF_Msk                    (0x1UL << RCC_RSR_BORRSTF_Pos)  /*!< 0x00200000 */
+#define RCC_RSR_BORRSTF                        RCC_RSR_BORRSTF_Msk
+#define RCC_RSR_PINRSTF_Pos                    (22U)
+#define RCC_RSR_PINRSTF_Msk                    (0x1UL << RCC_RSR_PINRSTF_Pos)  /*!< 0x00400000 */
+#define RCC_RSR_PINRSTF                        RCC_RSR_PINRSTF_Msk
+#define RCC_RSR_PORRSTF_Pos                    (23U)
+#define RCC_RSR_PORRSTF_Msk                    (0x1UL << RCC_RSR_PORRSTF_Pos)  /*!< 0x00800000 */
+#define RCC_RSR_PORRSTF                        RCC_RSR_PORRSTF_Msk
+#define RCC_RSR_SFTRSTF_Pos                    (24U)
+#define RCC_RSR_SFTRSTF_Msk                    (0x1UL << RCC_RSR_SFTRSTF_Pos)  /*!< 0x01000000 */
+#define RCC_RSR_SFTRSTF                        RCC_RSR_SFTRSTF_Msk
+#define RCC_RSR_IWDG1RSTF_Pos                  (26U)
+#define RCC_RSR_IWDG1RSTF_Msk                  (0x1UL << RCC_RSR_IWDG1RSTF_Pos) /*!< 0x04000000 */
+#define RCC_RSR_IWDG1RSTF                      RCC_RSR_IWDG1RSTF_Msk
+#define RCC_RSR_WWDG1RSTF_Pos                  (28U)
+#define RCC_RSR_WWDG1RSTF_Msk                  (0x1UL << RCC_RSR_WWDG1RSTF_Pos) /*!< 0x10000000 */
+#define RCC_RSR_WWDG1RSTF                      RCC_RSR_WWDG1RSTF_Msk
+
+#define RCC_RSR_LPWRRSTF_Pos                   (30U)
+#define RCC_RSR_LPWRRSTF_Msk                   (0x1UL << RCC_RSR_LPWRRSTF_Pos) /*!< 0x40000000 */
+#define RCC_RSR_LPWRRSTF                       RCC_RSR_LPWRRSTF_Msk
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    RNG                                     */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RNG_CR register  *******************/
+#define RNG_CR_RNGEN_Pos    (2U)
+#define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                        /*!< 0x00000004 */
+#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk
+#define RNG_CR_IE_Pos       (3U)
+#define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                           /*!< 0x00000008 */
+#define RNG_CR_IE           RNG_CR_IE_Msk
+#define RNG_CR_CED_Pos      (5U)
+#define RNG_CR_CED_Msk      (0x1UL << RNG_CR_CED_Pos)                          /*!< 0x00000020 */
+#define RNG_CR_CED          RNG_CR_CED_Msk
+
+/********************  Bits definition for RNG_SR register  *******************/
+#define RNG_SR_DRDY_Pos     (0U)
+#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                         /*!< 0x00000001 */
+#define RNG_SR_DRDY         RNG_SR_DRDY_Msk
+#define RNG_SR_CECS_Pos     (1U)
+#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                         /*!< 0x00000002 */
+#define RNG_SR_CECS         RNG_SR_CECS_Msk
+#define RNG_SR_SECS_Pos     (2U)
+#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                         /*!< 0x00000004 */
+#define RNG_SR_SECS         RNG_SR_SECS_Msk
+#define RNG_SR_CEIS_Pos     (5U)
+#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                         /*!< 0x00000020 */
+#define RNG_SR_CEIS         RNG_SR_CEIS_Msk
+#define RNG_SR_SEIS_Pos     (6U)
+#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                         /*!< 0x00000040 */
+#define RNG_SR_SEIS         RNG_SR_SEIS_Msk
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RTC_TR register  *******************/
+#define RTC_TR_PM_Pos                  (22U)
+#define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                /*!< 0x00400000 */
+#define RTC_TR_PM                      RTC_TR_PM_Msk
+#define RTC_TR_HT_Pos                  (20U)
+#define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                /*!< 0x00300000 */
+#define RTC_TR_HT                      RTC_TR_HT_Msk
+#define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                 /*!< 0x00100000 */
+#define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                 /*!< 0x00200000 */
+#define RTC_TR_HU_Pos                  (16U)
+#define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                /*!< 0x000F0000 */
+#define RTC_TR_HU                      RTC_TR_HU_Msk
+#define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                 /*!< 0x00010000 */
+#define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                 /*!< 0x00020000 */
+#define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                 /*!< 0x00040000 */
+#define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                 /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos                 (12U)
+#define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)               /*!< 0x00007000 */
+#define RTC_TR_MNT                     RTC_TR_MNT_Msk
+#define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)                /*!< 0x00001000 */
+#define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)                /*!< 0x00002000 */
+#define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)                /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos                 (8U)
+#define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)               /*!< 0x00000F00 */
+#define RTC_TR_MNU                     RTC_TR_MNU_Msk
+#define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)                /*!< 0x00000100 */
+#define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)                /*!< 0x00000200 */
+#define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)                /*!< 0x00000400 */
+#define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)                /*!< 0x00000800 */
+#define RTC_TR_ST_Pos                  (4U)
+#define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                /*!< 0x00000070 */
+#define RTC_TR_ST                      RTC_TR_ST_Msk
+#define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                 /*!< 0x00000010 */
+#define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                 /*!< 0x00000020 */
+#define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                 /*!< 0x00000040 */
+#define RTC_TR_SU_Pos                  (0U)
+#define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                /*!< 0x0000000F */
+#define RTC_TR_SU                      RTC_TR_SU_Msk
+#define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                 /*!< 0x00000001 */
+#define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                 /*!< 0x00000002 */
+#define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                 /*!< 0x00000004 */
+#define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                 /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_DR register  *******************/
+#define RTC_DR_YT_Pos                  (20U)
+#define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                /*!< 0x00F00000 */
+#define RTC_DR_YT                      RTC_DR_YT_Msk
+#define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                 /*!< 0x00100000 */
+#define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                 /*!< 0x00200000 */
+#define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                 /*!< 0x00400000 */
+#define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                 /*!< 0x00800000 */
+#define RTC_DR_YU_Pos                  (16U)
+#define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                /*!< 0x000F0000 */
+#define RTC_DR_YU                      RTC_DR_YU_Msk
+#define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                 /*!< 0x00010000 */
+#define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                 /*!< 0x00020000 */
+#define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                 /*!< 0x00040000 */
+#define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                 /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos                 (13U)
+#define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)               /*!< 0x0000E000 */
+#define RTC_DR_WDU                     RTC_DR_WDU_Msk
+#define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)                /*!< 0x00002000 */
+#define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)                /*!< 0x00004000 */
+#define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)                /*!< 0x00008000 */
+#define RTC_DR_MT_Pos                  (12U)
+#define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                /*!< 0x00001000 */
+#define RTC_DR_MT                      RTC_DR_MT_Msk
+#define RTC_DR_MU_Pos                  (8U)
+#define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                /*!< 0x00000F00 */
+#define RTC_DR_MU                      RTC_DR_MU_Msk
+#define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                 /*!< 0x00000100 */
+#define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                 /*!< 0x00000200 */
+#define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                 /*!< 0x00000400 */
+#define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                 /*!< 0x00000800 */
+#define RTC_DR_DT_Pos                  (4U)
+#define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                /*!< 0x00000030 */
+#define RTC_DR_DT                      RTC_DR_DT_Msk
+#define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                 /*!< 0x00000010 */
+#define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                 /*!< 0x00000020 */
+#define RTC_DR_DU_Pos                  (0U)
+#define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                /*!< 0x0000000F */
+#define RTC_DR_DU                      RTC_DR_DU_Msk
+#define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                 /*!< 0x00000001 */
+#define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                 /*!< 0x00000002 */
+#define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                 /*!< 0x00000004 */
+#define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                 /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_CR register  *******************/
+#define RTC_CR_ITSE_Pos                (24U)
+#define RTC_CR_ITSE_Msk                (0x1UL << RTC_CR_ITSE_Pos)              /*!< 0x01000000 */
+#define RTC_CR_ITSE                    RTC_CR_ITSE_Msk
+#define RTC_CR_COE_Pos                 (23U)
+#define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)               /*!< 0x00800000 */
+#define RTC_CR_COE                     RTC_CR_COE_Msk
+#define RTC_CR_OSEL_Pos                (21U)
+#define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)              /*!< 0x00600000 */
+#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk
+#define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */
+#define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */
+#define RTC_CR_POL_Pos                 (20U)
+#define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)               /*!< 0x00100000 */
+#define RTC_CR_POL                     RTC_CR_POL_Msk
+#define RTC_CR_COSEL_Pos               (19U)
+#define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)             /*!< 0x00080000 */
+#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk
+#define RTC_CR_BKP_Pos                 (18U)
+#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)               /*!< 0x00040000 */
+#define RTC_CR_BKP                     RTC_CR_BKP_Msk
+#define RTC_CR_SUB1H_Pos               (17U)
+#define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)             /*!< 0x00020000 */
+#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk
+#define RTC_CR_ADD1H_Pos               (16U)
+#define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)             /*!< 0x00010000 */
+#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk
+#define RTC_CR_TSIE_Pos                (15U)
+#define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)              /*!< 0x00008000 */
+#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk
+#define RTC_CR_WUTIE_Pos               (14U)
+#define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)             /*!< 0x00004000 */
+#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk
+#define RTC_CR_ALRBIE_Pos              (13U)
+#define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)            /*!< 0x00002000 */
+#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk
+#define RTC_CR_ALRAIE_Pos              (12U)
+#define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)            /*!< 0x00001000 */
+#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk
+#define RTC_CR_TSE_Pos                 (11U)
+#define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)               /*!< 0x00000800 */
+#define RTC_CR_TSE                     RTC_CR_TSE_Msk
+#define RTC_CR_WUTE_Pos                (10U)
+#define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)              /*!< 0x00000400 */
+#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk
+#define RTC_CR_ALRBE_Pos               (9U)
+#define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)             /*!< 0x00000200 */
+#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk
+#define RTC_CR_ALRAE_Pos               (8U)
+#define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)             /*!< 0x00000100 */
+#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk
+#define RTC_CR_FMT_Pos                 (6U)
+#define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)               /*!< 0x00000040 */
+#define RTC_CR_FMT                     RTC_CR_FMT_Msk
+#define RTC_CR_BYPSHAD_Pos             (5U)
+#define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)           /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk
+#define RTC_CR_REFCKON_Pos             (4U)
+#define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)           /*!< 0x00000010 */
+#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk
+#define RTC_CR_TSEDGE_Pos              (3U)
+#define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)            /*!< 0x00000008 */
+#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk
+#define RTC_CR_WUCKSEL_Pos             (0U)
+#define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk
+#define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */
+
+/********************  Bits definition for RTC_ISR register  ******************/
+#define RTC_ISR_ITSF_Pos               (17U)
+#define RTC_ISR_ITSF_Msk               (0x1UL << RTC_ISR_ITSF_Pos)             /*!< 0x00020000 */
+#define RTC_ISR_ITSF                   RTC_ISR_ITSF_Msk
+#define RTC_ISR_RECALPF_Pos            (16U)
+#define RTC_ISR_RECALPF_Msk            (0x1UL << RTC_ISR_RECALPF_Pos)          /*!< 0x00010000 */
+#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk
+#define RTC_ISR_TAMP3F_Pos             (15U)
+#define RTC_ISR_TAMP3F_Msk             (0x1UL << RTC_ISR_TAMP3F_Pos)           /*!< 0x00008000 */
+#define RTC_ISR_TAMP3F                 RTC_ISR_TAMP3F_Msk
+#define RTC_ISR_TAMP2F_Pos             (14U)
+#define RTC_ISR_TAMP2F_Msk             (0x1UL << RTC_ISR_TAMP2F_Pos)           /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk
+#define RTC_ISR_TAMP1F_Pos             (13U)
+#define RTC_ISR_TAMP1F_Msk             (0x1UL << RTC_ISR_TAMP1F_Pos)           /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk
+#define RTC_ISR_TSOVF_Pos              (12U)
+#define RTC_ISR_TSOVF_Msk              (0x1UL << RTC_ISR_TSOVF_Pos)            /*!< 0x00001000 */
+#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk
+#define RTC_ISR_TSF_Pos                (11U)
+#define RTC_ISR_TSF_Msk                (0x1UL << RTC_ISR_TSF_Pos)              /*!< 0x00000800 */
+#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk
+#define RTC_ISR_WUTF_Pos               (10U)
+#define RTC_ISR_WUTF_Msk               (0x1UL << RTC_ISR_WUTF_Pos)             /*!< 0x00000400 */
+#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk
+#define RTC_ISR_ALRBF_Pos              (9U)
+#define RTC_ISR_ALRBF_Msk              (0x1UL << RTC_ISR_ALRBF_Pos)            /*!< 0x00000200 */
+#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk
+#define RTC_ISR_ALRAF_Pos              (8U)
+#define RTC_ISR_ALRAF_Msk              (0x1UL << RTC_ISR_ALRAF_Pos)            /*!< 0x00000100 */
+#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk
+#define RTC_ISR_INIT_Pos               (7U)
+#define RTC_ISR_INIT_Msk               (0x1UL << RTC_ISR_INIT_Pos)             /*!< 0x00000080 */
+#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk
+#define RTC_ISR_INITF_Pos              (6U)
+#define RTC_ISR_INITF_Msk              (0x1UL << RTC_ISR_INITF_Pos)            /*!< 0x00000040 */
+#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk
+#define RTC_ISR_RSF_Pos                (5U)
+#define RTC_ISR_RSF_Msk                (0x1UL << RTC_ISR_RSF_Pos)              /*!< 0x00000020 */
+#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk
+#define RTC_ISR_INITS_Pos              (4U)
+#define RTC_ISR_INITS_Msk              (0x1UL << RTC_ISR_INITS_Pos)            /*!< 0x00000010 */
+#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk
+#define RTC_ISR_SHPF_Pos               (3U)
+#define RTC_ISR_SHPF_Msk               (0x1UL << RTC_ISR_SHPF_Pos)             /*!< 0x00000008 */
+#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk
+#define RTC_ISR_WUTWF_Pos              (2U)
+#define RTC_ISR_WUTWF_Msk              (0x1UL << RTC_ISR_WUTWF_Pos)            /*!< 0x00000004 */
+#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk
+#define RTC_ISR_ALRBWF_Pos             (1U)
+#define RTC_ISR_ALRBWF_Msk             (0x1UL << RTC_ISR_ALRBWF_Pos)           /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk
+#define RTC_ISR_ALRAWF_Pos             (0U)
+#define RTC_ISR_ALRAWF_Msk             (0x1UL << RTC_ISR_ALRAWF_Pos)           /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk
+
+/********************  Bits definition for RTC_PRER register  *****************/
+#define RTC_PRER_PREDIV_A_Pos          (16U)
+#define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)       /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk
+#define RTC_PRER_PREDIV_S_Pos          (0U)
+#define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)     /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk
+
+/********************  Bits definition for RTC_WUTR register  *****************/
+#define RTC_WUTR_WUT_Pos               (0U)
+#define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)          /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk
+
+/********************  Bits definition for RTC_ALRMAR register  ***************/
+#define RTC_ALRMAR_MSK4_Pos            (31U)
+#define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)          /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk
+#define RTC_ALRMAR_WDSEL_Pos           (30U)
+#define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)         /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk
+#define RTC_ALRMAR_DT_Pos              (28U)
+#define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)            /*!< 0x30000000 */
+#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk
+#define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos              (24U)
+#define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)            /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk
+#define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos            (23U)
+#define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)          /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk
+#define RTC_ALRMAR_PM_Pos              (22U)
+#define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)            /*!< 0x00400000 */
+#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk
+#define RTC_ALRMAR_HT_Pos              (20U)
+#define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00300000 */
+#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk
+#define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos              (16U)
+#define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)            /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk
+#define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos            (15U)
+#define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)          /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk
+#define RTC_ALRMAR_MNT_Pos             (12U)
+#define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk
+#define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos             (8U)
+#define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk
+#define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos            (7U)
+#define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)          /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk
+#define RTC_ALRMAR_ST_Pos              (4U)
+#define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000070 */
+#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk
+#define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos              (0U)
+#define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)            /*!< 0x0000000F */
+#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk
+#define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_ALRMBR register  ***************/
+#define RTC_ALRMBR_MSK4_Pos            (31U)
+#define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)          /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk
+#define RTC_ALRMBR_WDSEL_Pos           (30U)
+#define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)         /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk
+#define RTC_ALRMBR_DT_Pos              (28U)
+#define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)            /*!< 0x30000000 */
+#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk
+#define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos              (24U)
+#define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)            /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk
+#define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos            (23U)
+#define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)          /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk
+#define RTC_ALRMBR_PM_Pos              (22U)
+#define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)            /*!< 0x00400000 */
+#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk
+#define RTC_ALRMBR_HT_Pos              (20U)
+#define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00300000 */
+#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk
+#define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos              (16U)
+#define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)            /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk
+#define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos            (15U)
+#define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)          /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk
+#define RTC_ALRMBR_MNT_Pos             (12U)
+#define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk
+#define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos             (8U)
+#define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk
+#define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos            (7U)
+#define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)          /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk
+#define RTC_ALRMBR_ST_Pos              (4U)
+#define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000070 */
+#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk
+#define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos              (0U)
+#define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)            /*!< 0x0000000F */
+#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk
+#define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_WPR register  ******************/
+#define RTC_WPR_KEY_Pos                (0U)
+#define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)             /*!< 0x000000FF */
+#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk
+
+/********************  Bits definition for RTC_SSR register  ******************/
+#define RTC_SSR_SS_Pos                 (0U)
+#define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)            /*!< 0x0000FFFF */
+#define RTC_SSR_SS                     RTC_SSR_SS_Msk
+
+/********************  Bits definition for RTC_SHIFTR register  ***************/
+#define RTC_SHIFTR_SUBFS_Pos           (0U)
+#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)      /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk
+#define RTC_SHIFTR_ADD1S_Pos           (31U)
+#define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)         /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk
+
+/********************  Bits definition for RTC_TSTR register  *****************/
+#define RTC_TSTR_PM_Pos                (22U)
+#define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)              /*!< 0x00400000 */
+#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk
+#define RTC_TSTR_HT_Pos                (20U)
+#define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)              /*!< 0x00300000 */
+#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk
+#define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */
+#define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos                (16U)
+#define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)              /*!< 0x000F0000 */
+#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk
+#define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */
+#define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */
+#define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */
+#define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos               (12U)
+#define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)             /*!< 0x00007000 */
+#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk
+#define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos               (8U)
+#define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)             /*!< 0x00000F00 */
+#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk
+#define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos                (4U)
+#define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)              /*!< 0x00000070 */
+#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk
+#define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */
+#define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */
+#define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos                (0U)
+#define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)              /*!< 0x0000000F */
+#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk
+#define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */
+#define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */
+#define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */
+#define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_TSDR register  *****************/
+#define RTC_TSDR_WDU_Pos               (13U)
+#define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)             /*!< 0x0000E000 */
+#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk
+#define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos                (12U)
+#define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)              /*!< 0x00001000 */
+#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk
+#define RTC_TSDR_MU_Pos                (8U)
+#define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)              /*!< 0x00000F00 */
+#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk
+#define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */
+#define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */
+#define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */
+#define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos                (4U)
+#define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)              /*!< 0x00000030 */
+#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk
+#define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */
+#define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos                (0U)
+#define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)              /*!< 0x0000000F */
+#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk
+#define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */
+#define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */
+#define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */
+#define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_TSSSR register  ****************/
+#define RTC_TSSSR_SS_Pos               (0U)
+#define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)          /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk
+
+/********************  Bits definition for RTC_CALR register  *****************/
+#define RTC_CALR_CALP_Pos              (15U)
+#define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)            /*!< 0x00008000 */
+#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk
+#define RTC_CALR_CALW8_Pos             (14U)
+#define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)           /*!< 0x00004000 */
+#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk
+#define RTC_CALR_CALW16_Pos            (13U)
+#define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)          /*!< 0x00002000 */
+#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk
+#define RTC_CALR_CALM_Pos              (0U)
+#define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)          /*!< 0x000001FF */
+#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk
+#define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */
+#define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */
+#define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */
+#define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */
+#define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */
+#define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */
+#define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */
+#define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */
+#define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */
+
+/********************  Bits definition for RTC_TAMPCR register  ***************/
+#define RTC_TAMPCR_TAMP3MF_Pos         (24U)
+#define RTC_TAMPCR_TAMP3MF_Msk         (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)       /*!< 0x01000000 */
+#define RTC_TAMPCR_TAMP3MF             RTC_TAMPCR_TAMP3MF_Msk
+#define RTC_TAMPCR_TAMP3NOERASE_Pos    (23U)
+#define RTC_TAMPCR_TAMP3NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)  /*!< 0x00800000 */
+#define RTC_TAMPCR_TAMP3NOERASE        RTC_TAMPCR_TAMP3NOERASE_Msk
+#define RTC_TAMPCR_TAMP3IE_Pos         (22U)
+#define RTC_TAMPCR_TAMP3IE_Msk         (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)       /*!< 0x00400000 */
+#define RTC_TAMPCR_TAMP3IE             RTC_TAMPCR_TAMP3IE_Msk
+#define RTC_TAMPCR_TAMP2MF_Pos         (21U)
+#define RTC_TAMPCR_TAMP2MF_Msk         (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)       /*!< 0x00200000 */
+#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk
+#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)
+#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)  /*!< 0x00100000 */
+#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk
+#define RTC_TAMPCR_TAMP2IE_Pos         (19U)
+#define RTC_TAMPCR_TAMP2IE_Msk         (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)       /*!< 0x00080000 */
+#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk
+#define RTC_TAMPCR_TAMP1MF_Pos         (18U)
+#define RTC_TAMPCR_TAMP1MF_Msk         (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)       /*!< 0x00040000 */
+#define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk
+#define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)
+#define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)  /*!< 0x00020000 */
+#define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk
+#define RTC_TAMPCR_TAMP1IE_Pos         (16U)
+#define RTC_TAMPCR_TAMP1IE_Msk         (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)       /*!< 0x00010000 */
+#define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk
+#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)
+#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)     /*!< 0x00008000 */
+#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk
+#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)
+#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)      /*!< 0x00006000 */
+#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk
+#define RTC_TAMPCR_TAMPPRCH_0          (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */
+#define RTC_TAMPCR_TAMPPRCH_1          (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */
+#define RTC_TAMPCR_TAMPFLT_Pos         (11U)
+#define RTC_TAMPCR_TAMPFLT_Msk         (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)       /*!< 0x00001800 */
+#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk
+#define RTC_TAMPCR_TAMPFLT_0           (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */
+#define RTC_TAMPCR_TAMPFLT_1           (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */
+#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)
+#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)      /*!< 0x00000700 */
+#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk
+#define RTC_TAMPCR_TAMPFREQ_0          (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */
+#define RTC_TAMPCR_TAMPFREQ_1          (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */
+#define RTC_TAMPCR_TAMPFREQ_2          (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */
+#define RTC_TAMPCR_TAMPTS_Pos          (7U)
+#define RTC_TAMPCR_TAMPTS_Msk          (0x1UL << RTC_TAMPCR_TAMPTS_Pos)        /*!< 0x00000080 */
+#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk
+#define RTC_TAMPCR_TAMP3TRG_Pos        (6U)
+#define RTC_TAMPCR_TAMP3TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)      /*!< 0x00000040 */
+#define RTC_TAMPCR_TAMP3TRG            RTC_TAMPCR_TAMP3TRG_Msk
+#define RTC_TAMPCR_TAMP3E_Pos          (5U)
+#define RTC_TAMPCR_TAMP3E_Msk          (0x1UL << RTC_TAMPCR_TAMP3E_Pos)        /*!< 0x00000020 */
+#define RTC_TAMPCR_TAMP3E              RTC_TAMPCR_TAMP3E_Msk
+#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)
+#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)      /*!< 0x00000010 */
+#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk
+#define RTC_TAMPCR_TAMP2E_Pos          (3U)
+#define RTC_TAMPCR_TAMP2E_Msk          (0x1UL << RTC_TAMPCR_TAMP2E_Pos)        /*!< 0x00000008 */
+#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk
+#define RTC_TAMPCR_TAMPIE_Pos          (2U)
+#define RTC_TAMPCR_TAMPIE_Msk          (0x1UL << RTC_TAMPCR_TAMPIE_Pos)        /*!< 0x00000004 */
+#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk
+#define RTC_TAMPCR_TAMP1TRG_Pos        (1U)
+#define RTC_TAMPCR_TAMP1TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)      /*!< 0x00000002 */
+#define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk
+#define RTC_TAMPCR_TAMP1E_Pos          (0U)
+#define RTC_TAMPCR_TAMP1E_Msk          (0x1UL << RTC_TAMPCR_TAMP1E_Pos)        /*!< 0x00000001 */
+#define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk
+
+/********************  Bits definition for RTC_ALRMASSR register  *************/
+#define RTC_ALRMASSR_MASKSS_Pos        (24U)
+#define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos            (0U)
+#define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)       /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk
+
+/********************  Bits definition for RTC_ALRMBSSR register  *************/
+#define RTC_ALRMBSSR_MASKSS_Pos        (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos            (0U)
+#define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)       /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk
+
+/********************  Bits definition for RTC_OR register  *******************/
+#define RTC_OR_OUT_RMP_Pos             (1U)
+#define RTC_OR_OUT_RMP_Msk             (0x1UL << RTC_OR_OUT_RMP_Pos)           /*!< 0x00000002 */
+#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk
+#define RTC_OR_ALARMOUTTYPE_Pos        (0U)
+#define RTC_OR_ALARMOUTTYPE_Msk        (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)      /*!< 0x00000001 */
+#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk
+
+/********************  Bits definition for RTC_BKP0R register  ****************/
+#define RTC_BKP0R_Pos                  (0U)
+#define RTC_BKP0R_Msk                  (0xFFFFFFFFUL << RTC_BKP0R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP0R                      RTC_BKP0R_Msk
+
+/********************  Bits definition for RTC_BKP1R register  ****************/
+#define RTC_BKP1R_Pos                  (0U)
+#define RTC_BKP1R_Msk                  (0xFFFFFFFFUL << RTC_BKP1R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP1R                      RTC_BKP1R_Msk
+
+/********************  Bits definition for RTC_BKP2R register  ****************/
+#define RTC_BKP2R_Pos                  (0U)
+#define RTC_BKP2R_Msk                  (0xFFFFFFFFUL << RTC_BKP2R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP2R                      RTC_BKP2R_Msk
+
+/********************  Bits definition for RTC_BKP3R register  ****************/
+#define RTC_BKP3R_Pos                  (0U)
+#define RTC_BKP3R_Msk                  (0xFFFFFFFFUL << RTC_BKP3R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP3R                      RTC_BKP3R_Msk
+
+/********************  Bits definition for RTC_BKP4R register  ****************/
+#define RTC_BKP4R_Pos                  (0U)
+#define RTC_BKP4R_Msk                  (0xFFFFFFFFUL << RTC_BKP4R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP4R                      RTC_BKP4R_Msk
+
+/********************  Bits definition for RTC_BKP5R register  ****************/
+#define RTC_BKP5R_Pos                  (0U)
+#define RTC_BKP5R_Msk                  (0xFFFFFFFFUL << RTC_BKP5R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP5R                      RTC_BKP5R_Msk
+
+/********************  Bits definition for RTC_BKP6R register  ****************/
+#define RTC_BKP6R_Pos                  (0U)
+#define RTC_BKP6R_Msk                  (0xFFFFFFFFUL << RTC_BKP6R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP6R                      RTC_BKP6R_Msk
+
+/********************  Bits definition for RTC_BKP7R register  ****************/
+#define RTC_BKP7R_Pos                  (0U)
+#define RTC_BKP7R_Msk                  (0xFFFFFFFFUL << RTC_BKP7R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP7R                      RTC_BKP7R_Msk
+
+/********************  Bits definition for RTC_BKP8R register  ****************/
+#define RTC_BKP8R_Pos                  (0U)
+#define RTC_BKP8R_Msk                  (0xFFFFFFFFUL << RTC_BKP8R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP8R                      RTC_BKP8R_Msk
+
+/********************  Bits definition for RTC_BKP9R register  ****************/
+#define RTC_BKP9R_Pos                  (0U)
+#define RTC_BKP9R_Msk                  (0xFFFFFFFFUL << RTC_BKP9R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP9R                      RTC_BKP9R_Msk
+
+/********************  Bits definition for RTC_BKP10R register  ***************/
+#define RTC_BKP10R_Pos                 (0U)
+#define RTC_BKP10R_Msk                 (0xFFFFFFFFUL << RTC_BKP10R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP10R                     RTC_BKP10R_Msk
+
+/********************  Bits definition for RTC_BKP11R register  ***************/
+#define RTC_BKP11R_Pos                 (0U)
+#define RTC_BKP11R_Msk                 (0xFFFFFFFFUL << RTC_BKP11R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP11R                     RTC_BKP11R_Msk
+
+/********************  Bits definition for RTC_BKP12R register  ***************/
+#define RTC_BKP12R_Pos                 (0U)
+#define RTC_BKP12R_Msk                 (0xFFFFFFFFUL << RTC_BKP12R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP12R                     RTC_BKP12R_Msk
+
+/********************  Bits definition for RTC_BKP13R register  ***************/
+#define RTC_BKP13R_Pos                 (0U)
+#define RTC_BKP13R_Msk                 (0xFFFFFFFFUL << RTC_BKP13R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP13R                     RTC_BKP13R_Msk
+
+/********************  Bits definition for RTC_BKP14R register  ***************/
+#define RTC_BKP14R_Pos                 (0U)
+#define RTC_BKP14R_Msk                 (0xFFFFFFFFUL << RTC_BKP14R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP14R                     RTC_BKP14R_Msk
+
+/********************  Bits definition for RTC_BKP15R register  ***************/
+#define RTC_BKP15R_Pos                 (0U)
+#define RTC_BKP15R_Msk                 (0xFFFFFFFFUL << RTC_BKP15R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP15R                     RTC_BKP15R_Msk
+
+/********************  Bits definition for RTC_BKP16R register  ***************/
+#define RTC_BKP16R_Pos                 (0U)
+#define RTC_BKP16R_Msk                 (0xFFFFFFFFUL << RTC_BKP16R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP16R                     RTC_BKP16R_Msk
+
+/********************  Bits definition for RTC_BKP17R register  ***************/
+#define RTC_BKP17R_Pos                 (0U)
+#define RTC_BKP17R_Msk                 (0xFFFFFFFFUL << RTC_BKP17R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP17R                     RTC_BKP17R_Msk
+
+/********************  Bits definition for RTC_BKP18R register  ***************/
+#define RTC_BKP18R_Pos                 (0U)
+#define RTC_BKP18R_Msk                 (0xFFFFFFFFUL << RTC_BKP18R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP18R                     RTC_BKP18R_Msk
+
+/********************  Bits definition for RTC_BKP19R register  ***************/
+#define RTC_BKP19R_Pos                 (0U)
+#define RTC_BKP19R_Msk                 (0xFFFFFFFFUL << RTC_BKP19R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP19R                     RTC_BKP19R_Msk
+
+/********************  Bits definition for RTC_BKP20R register  ***************/
+#define RTC_BKP20R_Pos                 (0U)
+#define RTC_BKP20R_Msk                 (0xFFFFFFFFUL << RTC_BKP20R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP20R                     RTC_BKP20R_Msk
+
+/********************  Bits definition for RTC_BKP21R register  ***************/
+#define RTC_BKP21R_Pos                 (0U)
+#define RTC_BKP21R_Msk                 (0xFFFFFFFFUL << RTC_BKP21R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP21R                     RTC_BKP21R_Msk
+
+/********************  Bits definition for RTC_BKP22R register  ***************/
+#define RTC_BKP22R_Pos                 (0U)
+#define RTC_BKP22R_Msk                 (0xFFFFFFFFUL << RTC_BKP22R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP22R                     RTC_BKP22R_Msk
+
+/********************  Bits definition for RTC_BKP23R register  ***************/
+#define RTC_BKP23R_Pos                 (0U)
+#define RTC_BKP23R_Msk                 (0xFFFFFFFFUL << RTC_BKP23R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP23R                     RTC_BKP23R_Msk
+
+/********************  Bits definition for RTC_BKP24R register  ***************/
+#define RTC_BKP24R_Pos                 (0U)
+#define RTC_BKP24R_Msk                 (0xFFFFFFFFUL << RTC_BKP24R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP24R                     RTC_BKP24R_Msk
+
+/********************  Bits definition for RTC_BKP25R register  ***************/
+#define RTC_BKP25R_Pos                 (0U)
+#define RTC_BKP25R_Msk                 (0xFFFFFFFFUL << RTC_BKP25R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP25R                     RTC_BKP25R_Msk
+
+/********************  Bits definition for RTC_BKP26R register  ***************/
+#define RTC_BKP26R_Pos                 (0U)
+#define RTC_BKP26R_Msk                 (0xFFFFFFFFUL << RTC_BKP26R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP26R                     RTC_BKP26R_Msk
+
+/********************  Bits definition for RTC_BKP27R register  ***************/
+#define RTC_BKP27R_Pos                 (0U)
+#define RTC_BKP27R_Msk                 (0xFFFFFFFFUL << RTC_BKP27R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP27R                     RTC_BKP27R_Msk
+
+/********************  Bits definition for RTC_BKP28R register  ***************/
+#define RTC_BKP28R_Pos                 (0U)
+#define RTC_BKP28R_Msk                 (0xFFFFFFFFUL << RTC_BKP28R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP28R                     RTC_BKP28R_Msk
+
+/********************  Bits definition for RTC_BKP29R register  ***************/
+#define RTC_BKP29R_Pos                 (0U)
+#define RTC_BKP29R_Msk                 (0xFFFFFFFFUL << RTC_BKP29R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP29R                     RTC_BKP29R_Msk
+
+/********************  Bits definition for RTC_BKP30R register  ***************/
+#define RTC_BKP30R_Pos                 (0U)
+#define RTC_BKP30R_Msk                 (0xFFFFFFFFUL << RTC_BKP30R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP30R                     RTC_BKP30R_Msk
+
+/********************  Bits definition for RTC_BKP31R register  ***************/
+#define RTC_BKP31R_Pos                 (0U)
+#define RTC_BKP31R_Msk                 (0xFFFFFFFFUL << RTC_BKP31R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP31R                     RTC_BKP31R_Msk
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER_Pos             (5U)
+#define RTC_BKP_NUMBER_Msk             (0x1UL << RTC_BKP_NUMBER_Pos)           /*!< 0x00000020 */
+#define RTC_BKP_NUMBER                 RTC_BKP_NUMBER_Msk
+
+/******************************************************************************/
+/*                                                                            */
+/*                              SPDIF-RX Interface                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for SPDIF_CR register  ******************/
+#define SPDIFRX_CR_SPDIFEN_Pos      (0U)
+#define SPDIFRX_CR_SPDIFEN_Msk      (0x3UL << SPDIFRX_CR_SPDIFEN_Pos)          /*!< 0x00000003 */
+#define SPDIFRX_CR_SPDIFEN          SPDIFRX_CR_SPDIFEN_Msk                     /*!<Peripheral Block Enable                      */
+#define SPDIFRX_CR_RXDMAEN_Pos      (2U)
+#define SPDIFRX_CR_RXDMAEN_Msk      (0x1UL << SPDIFRX_CR_RXDMAEN_Pos)          /*!< 0x00000004 */
+#define SPDIFRX_CR_RXDMAEN          SPDIFRX_CR_RXDMAEN_Msk                     /*!<Receiver DMA Enable for data flow            */
+#define SPDIFRX_CR_RXSTEO_Pos       (3U)
+#define SPDIFRX_CR_RXSTEO_Msk       (0x1UL << SPDIFRX_CR_RXSTEO_Pos)           /*!< 0x00000008 */
+#define SPDIFRX_CR_RXSTEO           SPDIFRX_CR_RXSTEO_Msk                      /*!<Stereo Mode                                  */
+#define SPDIFRX_CR_DRFMT_Pos        (4U)
+#define SPDIFRX_CR_DRFMT_Msk        (0x3UL << SPDIFRX_CR_DRFMT_Pos)            /*!< 0x00000030 */
+#define SPDIFRX_CR_DRFMT            SPDIFRX_CR_DRFMT_Msk                       /*!<RX Data format                               */
+#define SPDIFRX_CR_PMSK_Pos         (6U)
+#define SPDIFRX_CR_PMSK_Msk         (0x1UL << SPDIFRX_CR_PMSK_Pos)             /*!< 0x00000040 */
+#define SPDIFRX_CR_PMSK             SPDIFRX_CR_PMSK_Msk                        /*!<Mask Parity error bit                        */
+#define SPDIFRX_CR_VMSK_Pos         (7U)
+#define SPDIFRX_CR_VMSK_Msk         (0x1UL << SPDIFRX_CR_VMSK_Pos)             /*!< 0x00000080 */
+#define SPDIFRX_CR_VMSK             SPDIFRX_CR_VMSK_Msk                        /*!<Mask of Validity bit                         */
+#define SPDIFRX_CR_CUMSK_Pos        (8U)
+#define SPDIFRX_CR_CUMSK_Msk        (0x1UL << SPDIFRX_CR_CUMSK_Pos)            /*!< 0x00000100 */
+#define SPDIFRX_CR_CUMSK            SPDIFRX_CR_CUMSK_Msk                       /*!<Mask of channel status and user bits         */
+#define SPDIFRX_CR_PTMSK_Pos        (9U)
+#define SPDIFRX_CR_PTMSK_Msk        (0x1UL << SPDIFRX_CR_PTMSK_Pos)            /*!< 0x00000200 */
+#define SPDIFRX_CR_PTMSK            SPDIFRX_CR_PTMSK_Msk                       /*!<Mask of Preamble Type bits                   */
+#define SPDIFRX_CR_CBDMAEN_Pos      (10U)
+#define SPDIFRX_CR_CBDMAEN_Msk      (0x1UL << SPDIFRX_CR_CBDMAEN_Pos)          /*!< 0x00000400 */
+#define SPDIFRX_CR_CBDMAEN          SPDIFRX_CR_CBDMAEN_Msk                     /*!<Control Buffer DMA ENable for control flow   */
+#define SPDIFRX_CR_CHSEL_Pos        (11U)
+#define SPDIFRX_CR_CHSEL_Msk        (0x1UL << SPDIFRX_CR_CHSEL_Pos)            /*!< 0x00000800 */
+#define SPDIFRX_CR_CHSEL            SPDIFRX_CR_CHSEL_Msk                       /*!<Channel Selection                            */
+#define SPDIFRX_CR_NBTR_Pos         (12U)
+#define SPDIFRX_CR_NBTR_Msk         (0x3UL << SPDIFRX_CR_NBTR_Pos)             /*!< 0x00003000 */
+#define SPDIFRX_CR_NBTR             SPDIFRX_CR_NBTR_Msk                        /*!<Maximum allowed re-tries during synchronization phase */
+#define SPDIFRX_CR_WFA_Pos          (14U)
+#define SPDIFRX_CR_WFA_Msk          (0x1UL << SPDIFRX_CR_WFA_Pos)              /*!< 0x00004000 */
+#define SPDIFRX_CR_WFA              SPDIFRX_CR_WFA_Msk                         /*!<Wait For Activity     */
+#define SPDIFRX_CR_INSEL_Pos        (16U)
+#define SPDIFRX_CR_INSEL_Msk        (0x7UL << SPDIFRX_CR_INSEL_Pos)            /*!< 0x00070000 */
+#define SPDIFRX_CR_INSEL            SPDIFRX_CR_INSEL_Msk                       /*!<SPDIF input selection */
+#define SPDIFRX_CR_CKSEN_Pos        (20U)
+#define SPDIFRX_CR_CKSEN_Msk        (0x1UL << SPDIFRX_CR_CKSEN_Pos)            /*!< 0x00100000 */
+#define SPDIFRX_CR_CKSEN            SPDIFRX_CR_CKSEN_Msk                       /*!<Symbol Clock Enable */
+#define SPDIFRX_CR_CKSBKPEN_Pos     (21U)
+#define SPDIFRX_CR_CKSBKPEN_Msk     (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos)         /*!< 0x00200000 */
+#define SPDIFRX_CR_CKSBKPEN         SPDIFRX_CR_CKSBKPEN_Msk                    /*!<Backup Symbol Clock Enable */
+
+/*******************  Bit definition for SPDIFRX_IMR register  *******************/
+#define SPDIFRX_IMR_RXNEIE_Pos      (0U)
+#define SPDIFRX_IMR_RXNEIE_Msk      (0x1UL << SPDIFRX_IMR_RXNEIE_Pos)          /*!< 0x00000001 */
+#define SPDIFRX_IMR_RXNEIE          SPDIFRX_IMR_RXNEIE_Msk                     /*!<RXNE interrupt enable                              */
+#define SPDIFRX_IMR_CSRNEIE_Pos     (1U)
+#define SPDIFRX_IMR_CSRNEIE_Msk     (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos)         /*!< 0x00000002 */
+#define SPDIFRX_IMR_CSRNEIE         SPDIFRX_IMR_CSRNEIE_Msk                    /*!<Control Buffer Ready Interrupt Enable              */
+#define SPDIFRX_IMR_PERRIE_Pos      (2U)
+#define SPDIFRX_IMR_PERRIE_Msk      (0x1UL << SPDIFRX_IMR_PERRIE_Pos)          /*!< 0x00000004 */
+#define SPDIFRX_IMR_PERRIE          SPDIFRX_IMR_PERRIE_Msk                     /*!<Parity error interrupt enable                      */
+#define SPDIFRX_IMR_OVRIE_Pos       (3U)
+#define SPDIFRX_IMR_OVRIE_Msk       (0x1UL << SPDIFRX_IMR_OVRIE_Pos)           /*!< 0x00000008 */
+#define SPDIFRX_IMR_OVRIE           SPDIFRX_IMR_OVRIE_Msk                      /*!<Overrun error Interrupt Enable                     */
+#define SPDIFRX_IMR_SBLKIE_Pos      (4U)
+#define SPDIFRX_IMR_SBLKIE_Msk      (0x1UL << SPDIFRX_IMR_SBLKIE_Pos)          /*!< 0x00000010 */
+#define SPDIFRX_IMR_SBLKIE          SPDIFRX_IMR_SBLKIE_Msk                     /*!<Synchronization Block Detected Interrupt Enable    */
+#define SPDIFRX_IMR_SYNCDIE_Pos     (5U)
+#define SPDIFRX_IMR_SYNCDIE_Msk     (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos)         /*!< 0x00000020 */
+#define SPDIFRX_IMR_SYNCDIE         SPDIFRX_IMR_SYNCDIE_Msk                    /*!<Synchronization Done                               */
+#define SPDIFRX_IMR_IFEIE_Pos       (6U)
+#define SPDIFRX_IMR_IFEIE_Msk       (0x1UL << SPDIFRX_IMR_IFEIE_Pos)           /*!< 0x00000040 */
+#define SPDIFRX_IMR_IFEIE           SPDIFRX_IMR_IFEIE_Msk                      /*!<Serial Interface Error Interrupt Enable            */
+
+/*******************  Bit definition for SPDIFRX_SR register  *******************/
+#define SPDIFRX_SR_RXNE_Pos         (0U)
+#define SPDIFRX_SR_RXNE_Msk         (0x1UL << SPDIFRX_SR_RXNE_Pos)             /*!< 0x00000001 */
+#define SPDIFRX_SR_RXNE             SPDIFRX_SR_RXNE_Msk                        /*!<Read data register not empty                          */
+#define SPDIFRX_SR_CSRNE_Pos        (1U)
+#define SPDIFRX_SR_CSRNE_Msk        (0x1UL << SPDIFRX_SR_CSRNE_Pos)            /*!< 0x00000002 */
+#define SPDIFRX_SR_CSRNE            SPDIFRX_SR_CSRNE_Msk                       /*!<The Control Buffer register is not empty              */
+#define SPDIFRX_SR_PERR_Pos         (2U)
+#define SPDIFRX_SR_PERR_Msk         (0x1UL << SPDIFRX_SR_PERR_Pos)             /*!< 0x00000004 */
+#define SPDIFRX_SR_PERR             SPDIFRX_SR_PERR_Msk                        /*!<Parity error                                          */
+#define SPDIFRX_SR_OVR_Pos          (3U)
+#define SPDIFRX_SR_OVR_Msk          (0x1UL << SPDIFRX_SR_OVR_Pos)              /*!< 0x00000008 */
+#define SPDIFRX_SR_OVR              SPDIFRX_SR_OVR_Msk                         /*!<Overrun error                                         */
+#define SPDIFRX_SR_SBD_Pos          (4U)
+#define SPDIFRX_SR_SBD_Msk          (0x1UL << SPDIFRX_SR_SBD_Pos)              /*!< 0x00000010 */
+#define SPDIFRX_SR_SBD              SPDIFRX_SR_SBD_Msk                         /*!<Synchronization Block Detected                        */
+#define SPDIFRX_SR_SYNCD_Pos        (5U)
+#define SPDIFRX_SR_SYNCD_Msk        (0x1UL << SPDIFRX_SR_SYNCD_Pos)            /*!< 0x00000020 */
+#define SPDIFRX_SR_SYNCD            SPDIFRX_SR_SYNCD_Msk                       /*!<Synchronization Done                                  */
+#define SPDIFRX_SR_FERR_Pos         (6U)
+#define SPDIFRX_SR_FERR_Msk         (0x1UL << SPDIFRX_SR_FERR_Pos)             /*!< 0x00000040 */
+#define SPDIFRX_SR_FERR             SPDIFRX_SR_FERR_Msk                        /*!<Framing error                                         */
+#define SPDIFRX_SR_SERR_Pos         (7U)
+#define SPDIFRX_SR_SERR_Msk         (0x1UL << SPDIFRX_SR_SERR_Pos)             /*!< 0x00000080 */
+#define SPDIFRX_SR_SERR             SPDIFRX_SR_SERR_Msk                        /*!<Synchronization error                                 */
+#define SPDIFRX_SR_TERR_Pos         (8U)
+#define SPDIFRX_SR_TERR_Msk         (0x1UL << SPDIFRX_SR_TERR_Pos)             /*!< 0x00000100 */
+#define SPDIFRX_SR_TERR             SPDIFRX_SR_TERR_Msk                        /*!<Time-out error                                        */
+#define SPDIFRX_SR_WIDTH5_Pos       (16U)
+#define SPDIFRX_SR_WIDTH5_Msk       (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos)        /*!< 0x7FFF0000 */
+#define SPDIFRX_SR_WIDTH5           SPDIFRX_SR_WIDTH5_Msk                      /*!<Duration of 5 symbols counted with spdif_clk          */
+
+/*******************  Bit definition for SPDIFRX_IFCR register  *******************/
+#define SPDIFRX_IFCR_PERRCF_Pos     (2U)
+#define SPDIFRX_IFCR_PERRCF_Msk     (0x1UL << SPDIFRX_IFCR_PERRCF_Pos)         /*!< 0x00000004 */
+#define SPDIFRX_IFCR_PERRCF         SPDIFRX_IFCR_PERRCF_Msk                    /*!<Clears the Parity error flag                         */
+#define SPDIFRX_IFCR_OVRCF_Pos      (3U)
+#define SPDIFRX_IFCR_OVRCF_Msk      (0x1UL << SPDIFRX_IFCR_OVRCF_Pos)          /*!< 0x00000008 */
+#define SPDIFRX_IFCR_OVRCF          SPDIFRX_IFCR_OVRCF_Msk                     /*!<Clears the Overrun error flag                        */
+#define SPDIFRX_IFCR_SBDCF_Pos      (4U)
+#define SPDIFRX_IFCR_SBDCF_Msk      (0x1UL << SPDIFRX_IFCR_SBDCF_Pos)          /*!< 0x00000010 */
+#define SPDIFRX_IFCR_SBDCF          SPDIFRX_IFCR_SBDCF_Msk                     /*!<Clears the Synchronization Block Detected flag       */
+#define SPDIFRX_IFCR_SYNCDCF_Pos    (5U)
+#define SPDIFRX_IFCR_SYNCDCF_Msk    (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos)        /*!< 0x00000020 */
+#define SPDIFRX_IFCR_SYNCDCF        SPDIFRX_IFCR_SYNCDCF_Msk                   /*!<Clears the Synchronization Done flag                 */
+
+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b00 case) *******************/
+#define SPDIFRX_DR0_DR_Pos          (0U)
+#define SPDIFRX_DR0_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos)         /*!< 0x00FFFFFF */
+#define SPDIFRX_DR0_DR              SPDIFRX_DR0_DR_Msk                         /*!<Data value            */
+#define SPDIFRX_DR0_PE_Pos          (24U)
+#define SPDIFRX_DR0_PE_Msk          (0x1UL << SPDIFRX_DR0_PE_Pos)              /*!< 0x01000000 */
+#define SPDIFRX_DR0_PE              SPDIFRX_DR0_PE_Msk                         /*!<Parity Error bit      */
+#define SPDIFRX_DR0_V_Pos           (25U)
+#define SPDIFRX_DR0_V_Msk           (0x1UL << SPDIFRX_DR0_V_Pos)               /*!< 0x02000000 */
+#define SPDIFRX_DR0_V               SPDIFRX_DR0_V_Msk                          /*!<Validity bit          */
+#define SPDIFRX_DR0_U_Pos           (26U)
+#define SPDIFRX_DR0_U_Msk           (0x1UL << SPDIFRX_DR0_U_Pos)               /*!< 0x04000000 */
+#define SPDIFRX_DR0_U               SPDIFRX_DR0_U_Msk                          /*!<User bit              */
+#define SPDIFRX_DR0_C_Pos           (27U)
+#define SPDIFRX_DR0_C_Msk           (0x1UL << SPDIFRX_DR0_C_Pos)               /*!< 0x08000000 */
+#define SPDIFRX_DR0_C               SPDIFRX_DR0_C_Msk                          /*!<Channel Status bit    */
+#define SPDIFRX_DR0_PT_Pos          (28U)
+#define SPDIFRX_DR0_PT_Msk          (0x3UL << SPDIFRX_DR0_PT_Pos)              /*!< 0x30000000 */
+#define SPDIFRX_DR0_PT              SPDIFRX_DR0_PT_Msk                         /*!<Preamble Type         */
+
+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b01 case) *******************/
+#define SPDIFRX_DR1_DR_Pos          (8U)
+#define SPDIFRX_DR1_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos)         /*!< 0xFFFFFF00 */
+#define SPDIFRX_DR1_DR              SPDIFRX_DR1_DR_Msk                         /*!<Data value            */
+#define SPDIFRX_DR1_PT_Pos          (4U)
+#define SPDIFRX_DR1_PT_Msk          (0x3UL << SPDIFRX_DR1_PT_Pos)              /*!< 0x00000030 */
+#define SPDIFRX_DR1_PT              SPDIFRX_DR1_PT_Msk                         /*!<Preamble Type         */
+#define SPDIFRX_DR1_C_Pos           (3U)
+#define SPDIFRX_DR1_C_Msk           (0x1UL << SPDIFRX_DR1_C_Pos)               /*!< 0x00000008 */
+#define SPDIFRX_DR1_C               SPDIFRX_DR1_C_Msk                          /*!<Channel Status bit    */
+#define SPDIFRX_DR1_U_Pos           (2U)
+#define SPDIFRX_DR1_U_Msk           (0x1UL << SPDIFRX_DR1_U_Pos)               /*!< 0x00000004 */
+#define SPDIFRX_DR1_U               SPDIFRX_DR1_U_Msk                          /*!<User bit              */
+#define SPDIFRX_DR1_V_Pos           (1U)
+#define SPDIFRX_DR1_V_Msk           (0x1UL << SPDIFRX_DR1_V_Pos)               /*!< 0x00000002 */
+#define SPDIFRX_DR1_V               SPDIFRX_DR1_V_Msk                          /*!<Validity bit          */
+#define SPDIFRX_DR1_PE_Pos          (0U)
+#define SPDIFRX_DR1_PE_Msk          (0x1UL << SPDIFRX_DR1_PE_Pos)              /*!< 0x00000001 */
+#define SPDIFRX_DR1_PE              SPDIFRX_DR1_PE_Msk                         /*!<Parity Error bit      */
+
+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b10 case) *******************/
+#define SPDIFRX_DR1_DRNL1_Pos       (16U)
+#define SPDIFRX_DR1_DRNL1_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos)        /*!< 0xFFFF0000 */
+#define SPDIFRX_DR1_DRNL1           SPDIFRX_DR1_DRNL1_Msk                      /*!<Data value Channel B      */
+#define SPDIFRX_DR1_DRNL2_Pos       (0U)
+#define SPDIFRX_DR1_DRNL2_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos)        /*!< 0x0000FFFF */
+#define SPDIFRX_DR1_DRNL2           SPDIFRX_DR1_DRNL2_Msk                      /*!<Data value Channel A      */
+
+/*******************  Bit definition for SPDIFRX_CSR register   *******************/
+#define SPDIFRX_CSR_USR_Pos         (0U)
+#define SPDIFRX_CSR_USR_Msk         (0xFFFFUL << SPDIFRX_CSR_USR_Pos)          /*!< 0x0000FFFF */
+#define SPDIFRX_CSR_USR             SPDIFRX_CSR_USR_Msk                        /*!<User data information           */
+#define SPDIFRX_CSR_CS_Pos          (16U)
+#define SPDIFRX_CSR_CS_Msk          (0xFFUL << SPDIFRX_CSR_CS_Pos)             /*!< 0x00FF0000 */
+#define SPDIFRX_CSR_CS              SPDIFRX_CSR_CS_Msk                         /*!<Channel A status information    */
+#define SPDIFRX_CSR_SOB_Pos         (24U)
+#define SPDIFRX_CSR_SOB_Msk         (0x1UL << SPDIFRX_CSR_SOB_Pos)             /*!< 0x01000000 */
+#define SPDIFRX_CSR_SOB             SPDIFRX_CSR_SOB_Msk                        /*!<Start Of Block                  */
+
+/*******************  Bit definition for SPDIFRX_DIR register    *******************/
+#define SPDIFRX_DIR_THI_Pos         (0U)
+#define SPDIFRX_DIR_THI_Msk         (0x1FFFUL << SPDIFRX_DIR_THI_Pos)          /*!< 0x00001FFF */
+#define SPDIFRX_DIR_THI             SPDIFRX_DIR_THI_Msk                        /*!<Threshold LOW      */
+#define SPDIFRX_DIR_TLO_Pos         (16U)
+#define SPDIFRX_DIR_TLO_Msk         (0x1FFFUL << SPDIFRX_DIR_TLO_Pos)          /*!< 0x1FFF0000 */
+#define SPDIFRX_DIR_TLO             SPDIFRX_DIR_TLO_Msk                        /*!<Threshold HIGH     */
+
+/*******************  Bit definition for SPDIFRX_VERR register    *******************/
+#define SPDIFRX_VERR_MINREV_Pos     (0U)
+#define SPDIFRX_VERR_MINREV_Msk     (0xFUL << SPDIFRX_VERR_MINREV_Pos)         /*!< 0x0000000F */
+#define SPDIFRX_VERR_MINREV         SPDIFRX_VERR_MINREV_Msk                    /*!<SPDIFRX Minor revision     */
+#define SPDIFRX_VERR_MAJREV_Pos     (4U)
+#define SPDIFRX_VERR_MAJREV_Msk     (0xFUL << SPDIFRX_VERR_MAJREV_Pos)         /*!< 0x000000F0 */
+#define SPDIFRX_VERR_MAJREV         SPDIFRX_VERR_MAJREV_Msk                    /*!<SPDIFRX Major revision     */
+
+/*******************  Bit definition for SPDIFRX_IDR register    *******************/
+#define SPDIFRX_IDR_ID_Pos          (0U)
+#define SPDIFRX_IDR_ID_Msk          (0xFFFFFFFFUL << SPDIFRX_IDR_ID_Pos)       /*!< 0xFFFFFFFF */
+#define SPDIFRX_IDR_ID              SPDIFRX_IDR_ID_Msk                         /*!<SPDIFRX identifier     */
+
+/*******************  Bit definition for SPDIFRX_SIDR register    *******************/
+#define SPDIFRX_SIDR_SID_Pos        (0U)
+#define SPDIFRX_SIDR_SID_Msk        (0xFFFFFFFFUL << SPDIFRX_SIDR_SID_Pos)     /*!< 0xFFFFFFFF */
+#define SPDIFRX_SIDR_SID            SPDIFRX_SIDR_SID_Msk                       /*!<Size of the memory region allocated to SPDIFRX registers */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Serial Audio Interface                            */
+/*                                                                            */
+/******************************************************************************/
+/*******************************  SAI VERSION  ********************************/
+#define SAI_VER_V2_X
+
+/********************  Bit definition for SAI_GCR register  *******************/
+#define SAI_GCR_SYNCIN_Pos         (0U)
+#define SAI_GCR_SYNCIN_Msk         (0x3UL << SAI_GCR_SYNCIN_Pos)               /*!< 0x00000003 */
+#define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
+#define SAI_GCR_SYNCIN_0           (0x1UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */
+#define SAI_GCR_SYNCIN_1           (0x2UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */
+
+#define SAI_GCR_SYNCOUT_Pos        (4U)
+#define SAI_GCR_SYNCOUT_Msk        (0x3UL << SAI_GCR_SYNCOUT_Pos)              /*!< 0x00000030 */
+#define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define SAI_GCR_SYNCOUT_0          (0x1UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */
+#define SAI_GCR_SYNCOUT_1          (0x2UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */
+
+/*******************  Bit definition for SAI_xCR1 register  *******************/
+#define SAI_xCR1_MODE_Pos          (0U)
+#define SAI_xCR1_MODE_Msk          (0x3UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000003 */
+#define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */
+#define SAI_xCR1_MODE_0            (0x1UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */
+#define SAI_xCR1_MODE_1            (0x2UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */
+
+#define SAI_xCR1_PRTCFG_Pos        (2U)
+#define SAI_xCR1_PRTCFG_Msk        (0x3UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x0000000C */
+#define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
+#define SAI_xCR1_PRTCFG_0          (0x1UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */
+#define SAI_xCR1_PRTCFG_1          (0x2UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */
+
+#define SAI_xCR1_DS_Pos            (5U)
+#define SAI_xCR1_DS_Msk            (0x7UL << SAI_xCR1_DS_Pos)                  /*!< 0x000000E0 */
+#define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */
+#define SAI_xCR1_DS_0              (0x1UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */
+#define SAI_xCR1_DS_1              (0x2UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */
+#define SAI_xCR1_DS_2              (0x4UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */
+
+#define SAI_xCR1_LSBFIRST_Pos      (8U)
+#define SAI_xCR1_LSBFIRST_Msk      (0x1UL << SAI_xCR1_LSBFIRST_Pos)            /*!< 0x00000100 */
+#define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */
+#define SAI_xCR1_CKSTR_Pos         (9U)
+#define SAI_xCR1_CKSTR_Msk         (0x1UL << SAI_xCR1_CKSTR_Pos)               /*!< 0x00000200 */
+#define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */
+
+#define SAI_xCR1_SYNCEN_Pos        (10U)
+#define SAI_xCR1_SYNCEN_Msk        (0x3UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000C00 */
+#define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define SAI_xCR1_SYNCEN_0          (0x1UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */
+#define SAI_xCR1_SYNCEN_1          (0x2UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */
+
+#define SAI_xCR1_MONO_Pos          (12U)
+#define SAI_xCR1_MONO_Msk          (0x1UL << SAI_xCR1_MONO_Pos)                /*!< 0x00001000 */
+#define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */
+#define SAI_xCR1_OUTDRIV_Pos       (13U)
+#define SAI_xCR1_OUTDRIV_Msk       (0x1UL << SAI_xCR1_OUTDRIV_Pos)             /*!< 0x00002000 */
+#define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */
+#define SAI_xCR1_SAIEN_Pos         (16U)
+#define SAI_xCR1_SAIEN_Msk         (0x1UL << SAI_xCR1_SAIEN_Pos)               /*!< 0x00010000 */
+#define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */
+#define SAI_xCR1_DMAEN_Pos         (17U)
+#define SAI_xCR1_DMAEN_Msk         (0x1UL << SAI_xCR1_DMAEN_Pos)               /*!< 0x00020000 */
+#define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */
+#define SAI_xCR1_NODIV_Pos         (19U)
+#define SAI_xCR1_NODIV_Msk         (0x1UL << SAI_xCR1_NODIV_Pos)               /*!< 0x00080000 */
+#define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */
+
+#define SAI_xCR1_MCKDIV_Pos        (20U)
+#define SAI_xCR1_MCKDIV_Msk        (0x3FUL << SAI_xCR1_MCKDIV_Pos)             /*!< 0x03F00000 */
+#define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[5:0] (Master ClocK Divider)  */
+#define SAI_xCR1_MCKDIV_0          (0x01UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00100000 */
+#define SAI_xCR1_MCKDIV_1          (0x02UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00200000 */
+#define SAI_xCR1_MCKDIV_2          (0x04UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00400000 */
+#define SAI_xCR1_MCKDIV_3          (0x08UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00800000 */
+#define SAI_xCR1_MCKDIV_4          (0x10UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x01000000 */
+#define SAI_xCR1_MCKDIV_5          (0x20UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x02000000 */
+
+#define SAI_xCR1_MCKEN_Pos         (27U)
+#define SAI_xCR1_MCKEN_Msk         (0x1UL << SAI_xCR1_MCKEN_Pos)               /*!< 0x08000000 */
+#define SAI_xCR1_MCKEN             SAI_xCR1_MCKEN_Msk                          /*!<Master ClocK enable */
+
+#define SAI_xCR1_OSR_Pos           (26U)
+#define SAI_xCR1_OSR_Msk           (0x1UL << SAI_xCR1_OSR_Pos)                 /*!< 0x04000000 */
+#define SAI_xCR1_OSR               SAI_xCR1_OSR_Msk                            /*!<OverSampling Ratio for master clock  */
+
+/* Legacy define */
+#define  SAI_xCR1_NOMCK               SAI_xCR1_NODIV
+
+/*******************  Bit definition for SAI_xCR2 register  *******************/
+#define SAI_xCR2_FTH_Pos           (0U)
+#define SAI_xCR2_FTH_Msk           (0x7UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000007 */
+#define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */
+#define SAI_xCR2_FTH_0             (0x1UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */
+#define SAI_xCR2_FTH_1             (0x2UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */
+#define SAI_xCR2_FTH_2             (0x4UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */
+
+#define SAI_xCR2_FFLUSH_Pos        (3U)
+#define SAI_xCR2_FFLUSH_Msk        (0x1UL << SAI_xCR2_FFLUSH_Pos)              /*!< 0x00000008 */
+#define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */
+#define SAI_xCR2_TRIS_Pos          (4U)
+#define SAI_xCR2_TRIS_Msk          (0x1UL << SAI_xCR2_TRIS_Pos)                /*!< 0x00000010 */
+#define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */
+#define SAI_xCR2_MUTE_Pos          (5U)
+#define SAI_xCR2_MUTE_Msk          (0x1UL << SAI_xCR2_MUTE_Pos)                /*!< 0x00000020 */
+#define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */
+#define SAI_xCR2_MUTEVAL_Pos       (6U)
+#define SAI_xCR2_MUTEVAL_Msk       (0x1UL << SAI_xCR2_MUTEVAL_Pos)             /*!< 0x00000040 */
+#define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */
+
+#define SAI_xCR2_MUTECNT_Pos       (7U)
+#define SAI_xCR2_MUTECNT_Msk       (0x3FUL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00001F80 */
+#define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */
+#define SAI_xCR2_MUTECNT_0         (0x01UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */
+#define SAI_xCR2_MUTECNT_1         (0x02UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */
+#define SAI_xCR2_MUTECNT_2         (0x04UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */
+#define SAI_xCR2_MUTECNT_3         (0x08UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */
+#define SAI_xCR2_MUTECNT_4         (0x10UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */
+#define SAI_xCR2_MUTECNT_5         (0x20UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */
+
+#define SAI_xCR2_CPL_Pos           (13U)
+#define SAI_xCR2_CPL_Msk           (0x1UL << SAI_xCR2_CPL_Pos)                 /*!< 0x00002000 */
+#define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!< Complement Bit             */
+
+#define SAI_xCR2_COMP_Pos          (14U)
+#define SAI_xCR2_COMP_Msk          (0x3UL << SAI_xCR2_COMP_Pos)                /*!< 0x0000C000 */
+#define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */
+#define SAI_xCR2_COMP_0            (0x1UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */
+#define SAI_xCR2_COMP_1            (0x2UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */
+
+/******************  Bit definition for SAI_xFRCR register  *******************/
+#define SAI_xFRCR_FRL_Pos          (0U)
+#define SAI_xFRCR_FRL_Msk          (0xFFUL << SAI_xFRCR_FRL_Pos)               /*!< 0x000000FF */
+#define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](FRame Length)  */
+#define SAI_xFRCR_FRL_0            (0x01UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */
+#define SAI_xFRCR_FRL_1            (0x02UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */
+#define SAI_xFRCR_FRL_2            (0x04UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */
+#define SAI_xFRCR_FRL_3            (0x08UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */
+#define SAI_xFRCR_FRL_4            (0x10UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */
+#define SAI_xFRCR_FRL_5            (0x20UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */
+#define SAI_xFRCR_FRL_6            (0x40UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */
+#define SAI_xFRCR_FRL_7            (0x80UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */
+
+#define SAI_xFRCR_FSALL_Pos        (8U)
+#define SAI_xFRCR_FSALL_Msk        (0x7FUL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00007F00 */
+#define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FSALL[6:0] (Frame Synchronization Active Level Length)  */
+#define SAI_xFRCR_FSALL_0          (0x01UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */
+#define SAI_xFRCR_FSALL_1          (0x02UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */
+#define SAI_xFRCR_FSALL_2          (0x04UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */
+#define SAI_xFRCR_FSALL_3          (0x08UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */
+#define SAI_xFRCR_FSALL_4          (0x10UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */
+#define SAI_xFRCR_FSALL_5          (0x20UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */
+#define SAI_xFRCR_FSALL_6          (0x40UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */
+
+#define SAI_xFRCR_FSDEF_Pos        (16U)
+#define SAI_xFRCR_FSDEF_Msk        (0x1UL << SAI_xFRCR_FSDEF_Pos)              /*!< 0x00010000 */
+#define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!<Frame Synchronization Definition  */
+#define SAI_xFRCR_FSPOL_Pos        (17U)
+#define SAI_xFRCR_FSPOL_Msk        (0x1UL << SAI_xFRCR_FSPOL_Pos)              /*!< 0x00020000 */
+#define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */
+#define SAI_xFRCR_FSOFF_Pos        (18U)
+#define SAI_xFRCR_FSOFF_Msk        (0x1UL << SAI_xFRCR_FSOFF_Pos)              /*!< 0x00040000 */
+#define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */
+
+/* Legacy define */
+#define  SAI_xFRCR_FSPO                      SAI_xFRCR_FSPOL
+
+/******************  Bit definition for SAI_xSLOTR register  *******************/
+#define SAI_xSLOTR_FBOFF_Pos       (0U)
+#define SAI_xSLOTR_FBOFF_Msk       (0x1FUL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x0000001F */
+#define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FBOFF[4:0](First Bit Offset)  */
+#define SAI_xSLOTR_FBOFF_0         (0x01UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */
+#define SAI_xSLOTR_FBOFF_1         (0x02UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */
+#define SAI_xSLOTR_FBOFF_2         (0x04UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */
+#define SAI_xSLOTR_FBOFF_3         (0x08UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */
+#define SAI_xSLOTR_FBOFF_4         (0x10UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */
+
+#define SAI_xSLOTR_SLOTSZ_Pos      (6U)
+#define SAI_xSLOTR_SLOTSZ_Msk      (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x000000C0 */
+#define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */
+#define SAI_xSLOTR_SLOTSZ_0        (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */
+#define SAI_xSLOTR_SLOTSZ_1        (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */
+
+#define SAI_xSLOTR_NBSLOT_Pos      (8U)
+#define SAI_xSLOTR_NBSLOT_Msk      (0xFUL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000F00 */
+#define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
+#define SAI_xSLOTR_NBSLOT_0        (0x1UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */
+#define SAI_xSLOTR_NBSLOT_1        (0x2UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */
+#define SAI_xSLOTR_NBSLOT_2        (0x4UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */
+#define SAI_xSLOTR_NBSLOT_3        (0x8UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */
+
+#define SAI_xSLOTR_SLOTEN_Pos      (16U)
+#define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)         /*!< 0xFFFF0000 */
+#define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */
+
+/*******************  Bit definition for SAI_xIMR register  *******************/
+#define SAI_xIMR_OVRUDRIE_Pos      (0U)
+#define SAI_xIMR_OVRUDRIE_Msk      (0x1UL << SAI_xIMR_OVRUDRIE_Pos)            /*!< 0x00000001 */
+#define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */
+#define SAI_xIMR_MUTEDETIE_Pos     (1U)
+#define SAI_xIMR_MUTEDETIE_Msk     (0x1UL << SAI_xIMR_MUTEDETIE_Pos)           /*!< 0x00000002 */
+#define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */
+#define SAI_xIMR_WCKCFGIE_Pos      (2U)
+#define SAI_xIMR_WCKCFGIE_Msk      (0x1UL << SAI_xIMR_WCKCFGIE_Pos)            /*!< 0x00000004 */
+#define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */
+#define SAI_xIMR_FREQIE_Pos        (3U)
+#define SAI_xIMR_FREQIE_Msk        (0x1UL << SAI_xIMR_FREQIE_Pos)              /*!< 0x00000008 */
+#define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */
+#define SAI_xIMR_CNRDYIE_Pos       (4U)
+#define SAI_xIMR_CNRDYIE_Msk       (0x1UL << SAI_xIMR_CNRDYIE_Pos)             /*!< 0x00000010 */
+#define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */
+#define SAI_xIMR_AFSDETIE_Pos      (5U)
+#define SAI_xIMR_AFSDETIE_Msk      (0x1UL << SAI_xIMR_AFSDETIE_Pos)            /*!< 0x00000020 */
+#define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */
+#define SAI_xIMR_LFSDETIE_Pos      (6U)
+#define SAI_xIMR_LFSDETIE_Msk      (0x1UL << SAI_xIMR_LFSDETIE_Pos)            /*!< 0x00000040 */
+#define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */
+
+/********************  Bit definition for SAI_xSR register  *******************/
+#define SAI_xSR_OVRUDR_Pos         (0U)
+#define SAI_xSR_OVRUDR_Msk         (0x1UL << SAI_xSR_OVRUDR_Pos)               /*!< 0x00000001 */
+#define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */
+#define SAI_xSR_MUTEDET_Pos        (1U)
+#define SAI_xSR_MUTEDET_Msk        (0x1UL << SAI_xSR_MUTEDET_Pos)              /*!< 0x00000002 */
+#define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */
+#define SAI_xSR_WCKCFG_Pos         (2U)
+#define SAI_xSR_WCKCFG_Msk         (0x1UL << SAI_xSR_WCKCFG_Pos)               /*!< 0x00000004 */
+#define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */
+#define SAI_xSR_FREQ_Pos           (3U)
+#define SAI_xSR_FREQ_Msk           (0x1UL << SAI_xSR_FREQ_Pos)                 /*!< 0x00000008 */
+#define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */
+#define SAI_xSR_CNRDY_Pos          (4U)
+#define SAI_xSR_CNRDY_Msk          (0x1UL << SAI_xSR_CNRDY_Pos)                /*!< 0x00000010 */
+#define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */
+#define SAI_xSR_AFSDET_Pos         (5U)
+#define SAI_xSR_AFSDET_Msk         (0x1UL << SAI_xSR_AFSDET_Pos)               /*!< 0x00000020 */
+#define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */
+#define SAI_xSR_LFSDET_Pos         (6U)
+#define SAI_xSR_LFSDET_Msk         (0x1UL << SAI_xSR_LFSDET_Pos)               /*!< 0x00000040 */
+#define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */
+
+#define SAI_xSR_FLVL_Pos           (16U)
+#define SAI_xSR_FLVL_Msk           (0x7UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00070000 */
+#define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */
+#define SAI_xSR_FLVL_0             (0x1UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */
+#define SAI_xSR_FLVL_1             (0x2UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */
+#define SAI_xSR_FLVL_2             (0x4UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */
+
+/******************  Bit definition for SAI_xCLRFR register  ******************/
+#define SAI_xCLRFR_COVRUDR_Pos     (0U)
+#define SAI_xCLRFR_COVRUDR_Msk     (0x1UL << SAI_xCLRFR_COVRUDR_Pos)           /*!< 0x00000001 */
+#define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */
+#define SAI_xCLRFR_CMUTEDET_Pos    (1U)
+#define SAI_xCLRFR_CMUTEDET_Msk    (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)          /*!< 0x00000002 */
+#define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */
+#define SAI_xCLRFR_CWCKCFG_Pos     (2U)
+#define SAI_xCLRFR_CWCKCFG_Msk     (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)           /*!< 0x00000004 */
+#define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */
+#define SAI_xCLRFR_CFREQ_Pos       (3U)
+#define SAI_xCLRFR_CFREQ_Msk       (0x1UL << SAI_xCLRFR_CFREQ_Pos)             /*!< 0x00000008 */
+#define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */
+#define SAI_xCLRFR_CCNRDY_Pos      (4U)
+#define SAI_xCLRFR_CCNRDY_Msk      (0x1UL << SAI_xCLRFR_CCNRDY_Pos)            /*!< 0x00000010 */
+#define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */
+#define SAI_xCLRFR_CAFSDET_Pos     (5U)
+#define SAI_xCLRFR_CAFSDET_Msk     (0x1UL << SAI_xCLRFR_CAFSDET_Pos)           /*!< 0x00000020 */
+#define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */
+#define SAI_xCLRFR_CLFSDET_Pos     (6U)
+#define SAI_xCLRFR_CLFSDET_Msk     (0x1UL << SAI_xCLRFR_CLFSDET_Pos)           /*!< 0x00000040 */
+#define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */
+
+/******************  Bit definition for SAI_xDR register  *********************/
+#define SAI_xDR_DATA_Pos           (0U)
+#define SAI_xDR_DATA_Msk           (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)          /*!< 0xFFFFFFFF */
+#define SAI_xDR_DATA               SAI_xDR_DATA_Msk
+
+/*******************  Bit definition for SAI_PDMCR register  ******************/
+#define SAI_PDMCR_PDMEN_Pos        (0U)
+#define SAI_PDMCR_PDMEN_Msk        (0x1UL << SAI_PDMCR_PDMEN_Pos)              /*!< 0x00000001 */
+#define SAI_PDMCR_PDMEN            SAI_PDMCR_PDMEN_Msk                         /*!<PDM Enable                                          */
+
+#define SAI_PDMCR_MICNBR_Pos       (4U)
+#define SAI_PDMCR_MICNBR_Msk       (0x3UL << SAI_PDMCR_MICNBR_Pos)             /*!< 0x00000030 */
+#define SAI_PDMCR_MICNBR           SAI_PDMCR_MICNBR_Msk                        /*!<Number of microphones                               */
+#define SAI_PDMCR_MICNBR_0         (0x1UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000010 */
+#define SAI_PDMCR_MICNBR_1         (0x2UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000020 */
+
+#define SAI_PDMCR_CKEN1_Pos        (8U)
+#define SAI_PDMCR_CKEN1_Msk        (0x1UL << SAI_PDMCR_CKEN1_Pos)              /*!< 0x00000100 */
+#define SAI_PDMCR_CKEN1            SAI_PDMCR_CKEN1_Msk                         /*!<Clock enable of bitstream clock number 1            */
+#define SAI_PDMCR_CKEN2_Pos        (9U)
+#define SAI_PDMCR_CKEN2_Msk        (0x1UL << SAI_PDMCR_CKEN2_Pos)              /*!< 0x00000200 */
+#define SAI_PDMCR_CKEN2            SAI_PDMCR_CKEN2_Msk                         /*!<Clock enable of bitstream clock number 2            */
+#define SAI_PDMCR_CKEN3_Pos        (10U)
+#define SAI_PDMCR_CKEN3_Msk        (0x1UL << SAI_PDMCR_CKEN3_Pos)              /*!< 0x00000400 */
+#define SAI_PDMCR_CKEN3            SAI_PDMCR_CKEN3_Msk                         /*!<Clock enable of bitstream clock number 3            */
+#define SAI_PDMCR_CKEN4_Pos        (11U)
+#define SAI_PDMCR_CKEN4_Msk        (0x1UL << SAI_PDMCR_CKEN4_Pos)              /*!< 0x00000800 */
+#define SAI_PDMCR_CKEN4            SAI_PDMCR_CKEN4_Msk                         /*!<Clock enable of bitstream clock number 4            */
+
+/******************  Bit definition for SAI_PDMDLY register  ******************/
+#define SAI_PDMDLY_DLYM1L_Pos      (0U)
+#define SAI_PDMDLY_DLYM1L_Msk      (0x7UL << SAI_PDMDLY_DLYM1L_Pos)            /*!< 0x00000007 */
+#define SAI_PDMDLY_DLYM1L          SAI_PDMDLY_DLYM1L_Msk                       /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */
+#define SAI_PDMDLY_DLYM1L_0        (0x1UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000001 */
+#define SAI_PDMDLY_DLYM1L_1        (0x2UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000002 */
+#define SAI_PDMDLY_DLYM1L_2        (0x4UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000004 */
+
+#define SAI_PDMDLY_DLYM1R_Pos      (4U)
+#define SAI_PDMDLY_DLYM1R_Msk      (0x7UL << SAI_PDMDLY_DLYM1R_Pos)            /*!< 0x00000070 */
+#define SAI_PDMDLY_DLYM1R          SAI_PDMDLY_DLYM1R_Msk                       /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */
+#define SAI_PDMDLY_DLYM1R_0        (0x1UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000010 */
+#define SAI_PDMDLY_DLYM1R_1        (0x2UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000020 */
+#define SAI_PDMDLY_DLYM1R_2        (0x4UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000040 */
+
+#define SAI_PDMDLY_DLYM2L_Pos      (8U)
+#define SAI_PDMDLY_DLYM2L_Msk      (0x7UL << SAI_PDMDLY_DLYM2L_Pos)            /*!< 0x00000700 */
+#define SAI_PDMDLY_DLYM2L          SAI_PDMDLY_DLYM2L_Msk                       /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */
+#define SAI_PDMDLY_DLYM2L_0        (0x1UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000100 */
+#define SAI_PDMDLY_DLYM2L_1        (0x2UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000200 */
+#define SAI_PDMDLY_DLYM2L_2        (0x4UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000400 */
+
+#define SAI_PDMDLY_DLYM2R_Pos      (12U)
+#define SAI_PDMDLY_DLYM2R_Msk      (0x7UL << SAI_PDMDLY_DLYM2R_Pos)            /*!< 0x00007000 */
+#define SAI_PDMDLY_DLYM2R          SAI_PDMDLY_DLYM2R_Msk                       /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2)*/
+#define SAI_PDMDLY_DLYM2R_0        (0x1UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00001000 */
+#define SAI_PDMDLY_DLYM2R_1        (0x2UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00002000 */
+#define SAI_PDMDLY_DLYM2R_2        (0x4UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00004000 */
+
+#define SAI_PDMDLY_DLYM3L_Pos      (16U)
+#define SAI_PDMDLY_DLYM3L_Msk      (0x7UL << SAI_PDMDLY_DLYM3L_Pos)            /*!< 0x00070000 */
+#define SAI_PDMDLY_DLYM3L          SAI_PDMDLY_DLYM3L_Msk                       /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3)*/
+#define SAI_PDMDLY_DLYM3L_0        (0x1UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00010000 */
+#define SAI_PDMDLY_DLYM3L_1        (0x2UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00020000 */
+#define SAI_PDMDLY_DLYM3L_2        (0x4UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00040000 */
+
+#define SAI_PDMDLY_DLYM3R_Pos      (20U)
+#define SAI_PDMDLY_DLYM3R_Msk      (0x7UL << SAI_PDMDLY_DLYM3R_Pos)            /*!< 0x00700000 */
+#define SAI_PDMDLY_DLYM3R          SAI_PDMDLY_DLYM3R_Msk                       /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3)*/
+#define SAI_PDMDLY_DLYM3R_0        (0x1UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00100000 */
+#define SAI_PDMDLY_DLYM3R_1        (0x2UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00200000 */
+#define SAI_PDMDLY_DLYM3R_2        (0x4UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00400000 */
+
+#define SAI_PDMDLY_DLYM4L_Pos      (24U)
+#define SAI_PDMDLY_DLYM4L_Msk      (0x7UL << SAI_PDMDLY_DLYM4L_Pos)            /*!< 0x07000000 */
+#define SAI_PDMDLY_DLYM4L          SAI_PDMDLY_DLYM4L_Msk                       /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4)*/
+#define SAI_PDMDLY_DLYM4L_0        (0x1UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x01000000 */
+#define SAI_PDMDLY_DLYM4L_1        (0x2UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x02000000 */
+#define SAI_PDMDLY_DLYM4L_2        (0x4UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x04000000 */
+
+#define SAI_PDMDLY_DLYM4R_Pos      (28U)
+#define SAI_PDMDLY_DLYM4R_Msk      (0x7UL << SAI_PDMDLY_DLYM4R_Pos)            /*!< 0x70000000 */
+#define SAI_PDMDLY_DLYM4R          SAI_PDMDLY_DLYM4R_Msk                       /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4)*/
+#define SAI_PDMDLY_DLYM4R_0        (0x1UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x10000000 */
+#define SAI_PDMDLY_DLYM4R_1        (0x2UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x20000000 */
+#define SAI_PDMDLY_DLYM4R_2        (0x4UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x40000000 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           SDMMC Interface                                  */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SDMMC_POWER register  ******************/
+#define SDMMC_POWER_PWRCTRL_Pos          (0U)
+#define SDMMC_POWER_PWRCTRL_Msk          (0x3UL << SDMMC_POWER_PWRCTRL_Pos)    /*!< 0x00000003 */
+#define SDMMC_POWER_PWRCTRL              SDMMC_POWER_PWRCTRL_Msk               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDMMC_POWER_PWRCTRL_0            (0x1UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000001 */
+#define SDMMC_POWER_PWRCTRL_1            (0x2UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000002 */
+#define SDMMC_POWER_VSWITCH_Pos          (2U)
+#define SDMMC_POWER_VSWITCH_Msk          (0x1UL << SDMMC_POWER_VSWITCH_Pos)    /*!< 0x00000004 */
+#define SDMMC_POWER_VSWITCH              SDMMC_POWER_VSWITCH_Msk               /*!<Voltage switch sequence start */
+#define SDMMC_POWER_VSWITCHEN_Pos        (3U)
+#define SDMMC_POWER_VSWITCHEN_Msk        (0x1UL << SDMMC_POWER_VSWITCHEN_Pos)  /*!< 0x00000008 */
+#define SDMMC_POWER_VSWITCHEN            SDMMC_POWER_VSWITCHEN_Msk             /*!<Voltage switch procedure enable */
+#define SDMMC_POWER_DIRPOL_Pos           (4U)
+#define SDMMC_POWER_DIRPOL_Msk           (0x1UL << SDMMC_POWER_DIRPOL_Pos)     /*!< 0x00000010 */
+#define SDMMC_POWER_DIRPOL               SDMMC_POWER_DIRPOL_Msk                /*!<Data and Command direction signals polarity selection */
+
+/******************  Bit definition for SDMMC_CLKCR register  ******************/
+#define SDMMC_CLKCR_CLKDIV_Pos           (0U)
+#define SDMMC_CLKCR_CLKDIV_Msk           (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos)   /*!< 0x000003FF */
+#define SDMMC_CLKCR_CLKDIV               SDMMC_CLKCR_CLKDIV_Msk                /*!<Clock divide factor             */
+#define SDMMC_CLKCR_PWRSAV_Pos           (12U)
+#define SDMMC_CLKCR_PWRSAV_Msk           (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)     /*!< 0x00001000 */
+#define SDMMC_CLKCR_PWRSAV               SDMMC_CLKCR_PWRSAV_Msk                /*!<Power saving configuration bit  */
+
+#define SDMMC_CLKCR_WIDBUS_Pos           (14U)
+#define SDMMC_CLKCR_WIDBUS_Msk           (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)     /*!< 0x0000C000 */
+#define SDMMC_CLKCR_WIDBUS               SDMMC_CLKCR_WIDBUS_Msk                /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDMMC_CLKCR_WIDBUS_0             (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00004000 */
+#define SDMMC_CLKCR_WIDBUS_1             (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00008000 */
+
+#define SDMMC_CLKCR_NEGEDGE_Pos          (16U)
+#define SDMMC_CLKCR_NEGEDGE_Msk          (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)    /*!< 0x00010000 */
+#define SDMMC_CLKCR_NEGEDGE              SDMMC_CLKCR_NEGEDGE_Msk               /*!<SDMMC_CK dephasing selection bit */
+#define SDMMC_CLKCR_HWFC_EN_Pos          (17U)
+#define SDMMC_CLKCR_HWFC_EN_Msk          (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)    /*!< 0x00020000 */
+#define SDMMC_CLKCR_HWFC_EN              SDMMC_CLKCR_HWFC_EN_Msk               /*!<HW Flow Control enable           */
+#define SDMMC_CLKCR_DDR_Pos              (18U)
+#define SDMMC_CLKCR_DDR_Msk              (0x1UL << SDMMC_CLKCR_DDR_Pos)        /*!< 0x00040000 */
+#define SDMMC_CLKCR_DDR                  SDMMC_CLKCR_DDR_Msk                   /*!<Data rate signaling selection    */
+#define SDMMC_CLKCR_BUSSPEED_Pos         (19U)
+#define SDMMC_CLKCR_BUSSPEED_Msk         (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos)   /*!< 0x00080000 */
+#define SDMMC_CLKCR_BUSSPEED             SDMMC_CLKCR_BUSSPEED_Msk              /*!<Bus speed mode selection         */
+#define SDMMC_CLKCR_SELCLKRX_Pos         (20U)
+#define SDMMC_CLKCR_SELCLKRX_Msk         (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos)   /*!< 0x00300000 */
+#define SDMMC_CLKCR_SELCLKRX             SDMMC_CLKCR_SELCLKRX_Msk              /*!<SELCLKRX[1:0] bits (Receive clock selection) */
+#define SDMMC_CLKCR_SELCLKRX_0           (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00100000 */
+#define SDMMC_CLKCR_SELCLKRX_1           (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00200000 */
+
+/*******************  Bit definition for SDMMC_ARG register  *******************/
+#define SDMMC_ARG_CMDARG_Pos             (0U)
+#define SDMMC_ARG_CMDARG_Msk             (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_ARG_CMDARG                 SDMMC_ARG_CMDARG_Msk                  /*!<Command argument */
+
+/*******************  Bit definition for SDMMC_CMD register  *******************/
+#define SDMMC_CMD_CMDINDEX_Pos           (0U)
+#define SDMMC_CMD_CMDINDEX_Msk           (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)    /*!< 0x0000003F */
+#define SDMMC_CMD_CMDINDEX               SDMMC_CMD_CMDINDEX_Msk                /*!<Command Index                               */
+#define SDMMC_CMD_CMDTRANS_Pos           (6U)
+#define SDMMC_CMD_CMDTRANS_Msk           (0x1UL << SDMMC_CMD_CMDTRANS_Pos)     /*!< 0x00000040 */
+#define SDMMC_CMD_CMDTRANS               SDMMC_CMD_CMDTRANS_Msk                /*!<CPSM Treats command as a Data Transfer      */
+#define SDMMC_CMD_CMDSTOP_Pos            (7U)
+#define SDMMC_CMD_CMDSTOP_Msk            (0x1UL << SDMMC_CMD_CMDSTOP_Pos)      /*!< 0x00000080 */
+#define SDMMC_CMD_CMDSTOP                SDMMC_CMD_CMDSTOP_Msk                 /*!<CPSM Treats command as a Stop               */
+
+#define SDMMC_CMD_WAITRESP_Pos           (8U)
+#define SDMMC_CMD_WAITRESP_Msk           (0x3UL << SDMMC_CMD_WAITRESP_Pos)     /*!< 0x00000300 */
+#define SDMMC_CMD_WAITRESP               SDMMC_CMD_WAITRESP_Msk                /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDMMC_CMD_WAITRESP_0             (0x1UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000100 */
+#define SDMMC_CMD_WAITRESP_1             (0x2UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000200 */
+
+#define SDMMC_CMD_WAITINT_Pos            (10U)
+#define SDMMC_CMD_WAITINT_Msk            (0x1UL << SDMMC_CMD_WAITINT_Pos)      /*!< 0x00000400 */
+#define SDMMC_CMD_WAITINT                SDMMC_CMD_WAITINT_Msk                 /*!<CPSM Waits for Interrupt Request                               */
+#define SDMMC_CMD_WAITPEND_Pos           (11U)
+#define SDMMC_CMD_WAITPEND_Msk           (0x1UL << SDMMC_CMD_WAITPEND_Pos)     /*!< 0x00000800 */
+#define SDMMC_CMD_WAITPEND               SDMMC_CMD_WAITPEND_Msk                /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDMMC_CMD_CPSMEN_Pos             (12U)
+#define SDMMC_CMD_CPSMEN_Msk             (0x1UL << SDMMC_CMD_CPSMEN_Pos)       /*!< 0x00001000 */
+#define SDMMC_CMD_CPSMEN                 SDMMC_CMD_CPSMEN_Msk                  /*!<Command path state machine (CPSM) Enable bit                   */
+#define SDMMC_CMD_DTHOLD_Pos             (13U)
+#define SDMMC_CMD_DTHOLD_Msk             (0x1UL << SDMMC_CMD_DTHOLD_Pos)       /*!< 0x00002000 */
+#define SDMMC_CMD_DTHOLD                 SDMMC_CMD_DTHOLD_Msk                  /*!<Hold new data block transmission and reception in the DPSM     */
+#define SDMMC_CMD_BOOTMODE_Pos           (14U)
+#define SDMMC_CMD_BOOTMODE_Msk           (0x1UL << SDMMC_CMD_BOOTMODE_Pos)     /*!< 0x00004000 */
+#define SDMMC_CMD_BOOTMODE               SDMMC_CMD_BOOTMODE_Msk                /*!<Boot mode                                                      */
+#define SDMMC_CMD_BOOTEN_Pos             (15U)
+#define SDMMC_CMD_BOOTEN_Msk             (0x1UL << SDMMC_CMD_BOOTEN_Pos)       /*!< 0x00008000 */
+#define SDMMC_CMD_BOOTEN                 SDMMC_CMD_BOOTEN_Msk                  /*!<Enable Boot mode procedure                                     */
+#define SDMMC_CMD_CMDSUSPEND_Pos         (16U)
+#define SDMMC_CMD_CMDSUSPEND_Msk         (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos)   /*!< 0x00010000 */
+#define SDMMC_CMD_CMDSUSPEND             SDMMC_CMD_CMDSUSPEND_Msk              /*!<CPSM Treats command as a Suspend or Resume command             */
+
+/*****************  Bit definition for SDMMC_RESPCMD register  *****************/
+#define SDMMC_RESPCMD_RESPCMD_Pos        (0U)
+#define SDMMC_RESPCMD_RESPCMD_Msk        (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
+#define SDMMC_RESPCMD_RESPCMD            SDMMC_RESPCMD_RESPCMD_Msk             /*!<Response command index */
+
+/******************  Bit definition for SDMMC_RESP0 register  ******************/
+#define SDMMC_RESP0_CARDSTATUS0_Pos      (0U)
+#define SDMMC_RESP0_CARDSTATUS0_Msk      (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP0_CARDSTATUS0          SDMMC_RESP0_CARDSTATUS0_Msk           /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP1 register  ******************/
+#define SDMMC_RESP1_CARDSTATUS1_Pos      (0U)
+#define SDMMC_RESP1_CARDSTATUS1_Msk      (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP1_CARDSTATUS1          SDMMC_RESP1_CARDSTATUS1_Msk           /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP2 register  ******************/
+#define SDMMC_RESP2_CARDSTATUS2_Pos      (0U)
+#define SDMMC_RESP2_CARDSTATUS2_Msk      (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP2_CARDSTATUS2          SDMMC_RESP2_CARDSTATUS2_Msk           /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP3 register  ******************/
+#define SDMMC_RESP3_CARDSTATUS3_Pos      (0U)
+#define SDMMC_RESP3_CARDSTATUS3_Msk      (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP3_CARDSTATUS3          SDMMC_RESP3_CARDSTATUS3_Msk           /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP4 register  ******************/
+#define SDMMC_RESP4_CARDSTATUS4_Pos      (0U)
+#define SDMMC_RESP4_CARDSTATUS4_Msk      (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP4_CARDSTATUS4          SDMMC_RESP4_CARDSTATUS4_Msk           /*!<Card Status */
+
+/******************  Bit definition for SDMMC_DTIMER register  *****************/
+#define SDMMC_DTIMER_DATATIME_Pos        (0U)
+#define SDMMC_DTIMER_DATATIME_Msk        (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_DTIMER_DATATIME            SDMMC_DTIMER_DATATIME_Msk             /*!<Data timeout period. */
+
+/******************  Bit definition for SDMMC_DLEN register  *******************/
+#define SDMMC_DLEN_DATALENGTH_Pos        (0U)
+#define SDMMC_DLEN_DATALENGTH_Msk        (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_DLEN_DATALENGTH            SDMMC_DLEN_DATALENGTH_Msk             /*!<Data length value    */
+
+/******************  Bit definition for SDMMC_DCTRL register  ******************/
+#define SDMMC_DCTRL_DTEN_Pos             (0U)
+#define SDMMC_DCTRL_DTEN_Msk             (0x1UL << SDMMC_DCTRL_DTEN_Pos)       /*!< 0x00000001 */
+#define SDMMC_DCTRL_DTEN                 SDMMC_DCTRL_DTEN_Msk                  /*!<Data transfer enabled bit                */
+#define SDMMC_DCTRL_DTDIR_Pos            (1U)
+#define SDMMC_DCTRL_DTDIR_Msk            (0x1UL << SDMMC_DCTRL_DTDIR_Pos)      /*!< 0x00000002 */
+#define SDMMC_DCTRL_DTDIR                SDMMC_DCTRL_DTDIR_Msk                 /*!<Data transfer direction selection        */
+#define SDMMC_DCTRL_DTMODE_Pos           (2U)
+#define SDMMC_DCTRL_DTMODE_Msk           (0x3UL << SDMMC_DCTRL_DTMODE_Pos)     /*!< 0x0000000C */
+#define SDMMC_DCTRL_DTMODE               SDMMC_DCTRL_DTMODE_Msk                /*!<DTMODE[1:0] Data transfer mode selection */
+#define SDMMC_DCTRL_DTMODE_0             (0x1UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000004 */
+#define SDMMC_DCTRL_DTMODE_1             (0x2UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000008 */
+
+#define SDMMC_DCTRL_DBLOCKSIZE_Pos       (4U)
+#define SDMMC_DCTRL_DBLOCKSIZE_Msk       (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
+#define SDMMC_DCTRL_DBLOCKSIZE           SDMMC_DCTRL_DBLOCKSIZE_Msk            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDMMC_DCTRL_DBLOCKSIZE_0         (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000010 */
+#define SDMMC_DCTRL_DBLOCKSIZE_1         (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000020 */
+#define SDMMC_DCTRL_DBLOCKSIZE_2         (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000040 */
+#define SDMMC_DCTRL_DBLOCKSIZE_3         (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000080 */
+
+#define SDMMC_DCTRL_RWSTART_Pos          (8U)
+#define SDMMC_DCTRL_RWSTART_Msk          (0x1UL << SDMMC_DCTRL_RWSTART_Pos)    /*!< 0x00000100 */
+#define SDMMC_DCTRL_RWSTART              SDMMC_DCTRL_RWSTART_Msk               /*!<Read wait start                                 */
+#define SDMMC_DCTRL_RWSTOP_Pos           (9U)
+#define SDMMC_DCTRL_RWSTOP_Msk           (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)     /*!< 0x00000200 */
+#define SDMMC_DCTRL_RWSTOP               SDMMC_DCTRL_RWSTOP_Msk                /*!<Read wait stop                                  */
+#define SDMMC_DCTRL_RWMOD_Pos            (10U)
+#define SDMMC_DCTRL_RWMOD_Msk            (0x1UL << SDMMC_DCTRL_RWMOD_Pos)      /*!< 0x00000400 */
+#define SDMMC_DCTRL_RWMOD                SDMMC_DCTRL_RWMOD_Msk                 /*!<Read wait mode                                  */
+#define SDMMC_DCTRL_SDIOEN_Pos           (11U)
+#define SDMMC_DCTRL_SDIOEN_Msk           (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)     /*!< 0x00000800 */
+#define SDMMC_DCTRL_SDIOEN               SDMMC_DCTRL_SDIOEN_Msk                /*!<SD I/O enable functions                         */
+#define SDMMC_DCTRL_BOOTACKEN_Pos        (12U)
+#define SDMMC_DCTRL_BOOTACKEN_Msk        (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos)  /*!< 0x00001000 */
+#define SDMMC_DCTRL_BOOTACKEN            SDMMC_DCTRL_BOOTACKEN_Msk             /*!<Enable the reception of the Boot Acknowledgment */
+#define SDMMC_DCTRL_FIFORST_Pos          (13U)
+#define SDMMC_DCTRL_FIFORST_Msk          (0x1UL << SDMMC_DCTRL_FIFORST_Pos)    /*!< 0x00002000 */
+#define SDMMC_DCTRL_FIFORST              SDMMC_DCTRL_FIFORST_Msk               /*!<FIFO reset                                      */
+
+/******************  Bit definition for SDMMC_DCOUNT register  *****************/
+#define SDMMC_DCOUNT_DATACOUNT_Pos       (0U)
+#define SDMMC_DCOUNT_DATACOUNT_Msk       (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_DCOUNT_DATACOUNT           SDMMC_DCOUNT_DATACOUNT_Msk            /*!<Data count value */
+
+/******************  Bit definition for SDMMC_STA register  ********************/
+#define SDMMC_STA_CCRCFAIL_Pos           (0U)
+#define SDMMC_STA_CCRCFAIL_Msk           (0x1UL << SDMMC_STA_CCRCFAIL_Pos)     /*!< 0x00000001 */
+#define SDMMC_STA_CCRCFAIL               SDMMC_STA_CCRCFAIL_Msk                /*!<Command response received (CRC check failed)  */
+#define SDMMC_STA_DCRCFAIL_Pos           (1U)
+#define SDMMC_STA_DCRCFAIL_Msk           (0x1UL << SDMMC_STA_DCRCFAIL_Pos)     /*!< 0x00000002 */
+#define SDMMC_STA_DCRCFAIL               SDMMC_STA_DCRCFAIL_Msk                /*!<Data block sent/received (CRC check failed)   */
+#define SDMMC_STA_CTIMEOUT_Pos           (2U)
+#define SDMMC_STA_CTIMEOUT_Msk           (0x1UL << SDMMC_STA_CTIMEOUT_Pos)     /*!< 0x00000004 */
+#define SDMMC_STA_CTIMEOUT               SDMMC_STA_CTIMEOUT_Msk                /*!<Command response timeout                      */
+#define SDMMC_STA_DTIMEOUT_Pos           (3U)
+#define SDMMC_STA_DTIMEOUT_Msk           (0x1UL << SDMMC_STA_DTIMEOUT_Pos)     /*!< 0x00000008 */
+#define SDMMC_STA_DTIMEOUT               SDMMC_STA_DTIMEOUT_Msk                /*!<Data timeout                                  */
+#define SDMMC_STA_TXUNDERR_Pos           (4U)
+#define SDMMC_STA_TXUNDERR_Msk           (0x1UL << SDMMC_STA_TXUNDERR_Pos)     /*!< 0x00000010 */
+#define SDMMC_STA_TXUNDERR               SDMMC_STA_TXUNDERR_Msk                /*!<Transmit FIFO underrun error                  */
+#define SDMMC_STA_RXOVERR_Pos            (5U)
+#define SDMMC_STA_RXOVERR_Msk            (0x1UL << SDMMC_STA_RXOVERR_Pos)      /*!< 0x00000020 */
+#define SDMMC_STA_RXOVERR                SDMMC_STA_RXOVERR_Msk                 /*!<Received FIFO overrun error                   */
+#define SDMMC_STA_CMDREND_Pos            (6U)
+#define SDMMC_STA_CMDREND_Msk            (0x1UL << SDMMC_STA_CMDREND_Pos)      /*!< 0x00000040 */
+#define SDMMC_STA_CMDREND                SDMMC_STA_CMDREND_Msk                 /*!<Command response received (CRC check passed)  */
+#define SDMMC_STA_CMDSENT_Pos            (7U)
+#define SDMMC_STA_CMDSENT_Msk            (0x1UL << SDMMC_STA_CMDSENT_Pos)      /*!< 0x00000080 */
+#define SDMMC_STA_CMDSENT                SDMMC_STA_CMDSENT_Msk                 /*!<Command sent (no response required)           */
+#define SDMMC_STA_DATAEND_Pos            (8U)
+#define SDMMC_STA_DATAEND_Msk            (0x1UL << SDMMC_STA_DATAEND_Pos)      /*!< 0x00000100 */
+#define SDMMC_STA_DATAEND                SDMMC_STA_DATAEND_Msk                 /*!<Data end (data counter, SDIDCOUNT, is zero)   */
+#define SDMMC_STA_DHOLD_Pos              (9U)
+#define SDMMC_STA_DHOLD_Msk              (0x1UL << SDMMC_STA_DHOLD_Pos)        /*!< 0x00000200 */
+#define SDMMC_STA_DHOLD                  SDMMC_STA_DHOLD_Msk                   /*!<Data transfer Hold                                                      */
+#define SDMMC_STA_DBCKEND_Pos            (10U)
+#define SDMMC_STA_DBCKEND_Msk            (0x1UL << SDMMC_STA_DBCKEND_Pos)      /*!< 0x00000400 */
+#define SDMMC_STA_DBCKEND                SDMMC_STA_DBCKEND_Msk                 /*!<Data block sent/received (CRC check passed)   */
+#define SDMMC_STA_DABORT_Pos             (11U)
+#define SDMMC_STA_DABORT_Msk             (0x1UL << SDMMC_STA_DABORT_Pos)       /*!< 0x00000800 */
+#define SDMMC_STA_DABORT                 SDMMC_STA_DABORT_Msk                  /*!<Data transfer aborted by CMD12                                          */
+#define SDMMC_STA_DPSMACT_Pos            (12U)
+#define SDMMC_STA_DPSMACT_Msk            (0x1UL << SDMMC_STA_DPSMACT_Pos)      /*!< 0x00001000 */
+#define SDMMC_STA_DPSMACT                SDMMC_STA_DPSMACT_Msk                 /*!<Data path state machine active                                       */
+#define SDMMC_STA_CPSMACT_Pos            (13U)
+#define SDMMC_STA_CPSMACT_Msk            (0x1UL << SDMMC_STA_CPSMACT_Pos)      /*!< 0x00002000 */
+#define SDMMC_STA_CPSMACT                SDMMC_STA_CPSMACT_Msk                 /*!<Command path state machine active                                          */
+#define SDMMC_STA_TXFIFOHE_Pos           (14U)
+#define SDMMC_STA_TXFIFOHE_Msk           (0x1UL << SDMMC_STA_TXFIFOHE_Pos)     /*!< 0x00004000 */
+#define SDMMC_STA_TXFIFOHE               SDMMC_STA_TXFIFOHE_Msk                /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDMMC_STA_RXFIFOHF_Pos           (15U)
+#define SDMMC_STA_RXFIFOHF_Msk           (0x1UL << SDMMC_STA_RXFIFOHF_Pos)     /*!< 0x00008000 */
+#define SDMMC_STA_RXFIFOHF               SDMMC_STA_RXFIFOHF_Msk                /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDMMC_STA_TXFIFOF_Pos            (16U)
+#define SDMMC_STA_TXFIFOF_Msk            (0x1UL << SDMMC_STA_TXFIFOF_Pos)      /*!< 0x00010000 */
+#define SDMMC_STA_TXFIFOF                SDMMC_STA_TXFIFOF_Msk                 /*!<Transmit FIFO full                            */
+#define SDMMC_STA_RXFIFOF_Pos            (17U)
+#define SDMMC_STA_RXFIFOF_Msk            (0x1UL << SDMMC_STA_RXFIFOF_Pos)      /*!< 0x00020000 */
+#define SDMMC_STA_RXFIFOF                SDMMC_STA_RXFIFOF_Msk                 /*!<Receive FIFO full                             */
+#define SDMMC_STA_TXFIFOE_Pos            (18U)
+#define SDMMC_STA_TXFIFOE_Msk            (0x1UL << SDMMC_STA_TXFIFOE_Pos)      /*!< 0x00040000 */
+#define SDMMC_STA_TXFIFOE                SDMMC_STA_TXFIFOE_Msk                 /*!<Transmit FIFO empty                           */
+#define SDMMC_STA_RXFIFOE_Pos            (19U)
+#define SDMMC_STA_RXFIFOE_Msk            (0x1UL << SDMMC_STA_RXFIFOE_Pos)      /*!< 0x00080000 */
+#define SDMMC_STA_RXFIFOE                SDMMC_STA_RXFIFOE_Msk                 /*!<Receive FIFO empty                            */
+#define SDMMC_STA_BUSYD0_Pos             (20U)
+#define SDMMC_STA_BUSYD0_Msk             (0x1UL << SDMMC_STA_BUSYD0_Pos)       /*!< 0x00100000 */
+#define SDMMC_STA_BUSYD0                 SDMMC_STA_BUSYD0_Msk                  /*!<Inverted value of SDMMC_D0 line (Busy)                                  */
+#define SDMMC_STA_BUSYD0END_Pos          (21U)
+#define SDMMC_STA_BUSYD0END_Msk          (0x1UL << SDMMC_STA_BUSYD0END_Pos)    /*!< 0x00200000 */
+#define SDMMC_STA_BUSYD0END              SDMMC_STA_BUSYD0END_Msk               /*!<End of SDMMC_D0 Busy following a CMD response detected                  */
+#define SDMMC_STA_SDIOIT_Pos             (22U)
+#define SDMMC_STA_SDIOIT_Msk             (0x1UL << SDMMC_STA_SDIOIT_Pos)       /*!< 0x00400000 */
+#define SDMMC_STA_SDIOIT                 SDMMC_STA_SDIOIT_Msk                  /*!<SDIO interrupt received                                                 */
+#define SDMMC_STA_ACKFAIL_Pos            (23U)
+#define SDMMC_STA_ACKFAIL_Msk            (0x1UL << SDMMC_STA_ACKFAIL_Pos)      /*!< 0x00800000 */
+#define SDMMC_STA_ACKFAIL                SDMMC_STA_ACKFAIL_Msk                 /*!<Boot Acknowledgment received (BootAck check fail)                       */
+#define SDMMC_STA_ACKTIMEOUT_Pos         (24U)
+#define SDMMC_STA_ACKTIMEOUT_Msk         (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos)   /*!< 0x01000000 */
+#define SDMMC_STA_ACKTIMEOUT             SDMMC_STA_ACKTIMEOUT_Msk              /*!<Boot Acknowledgment timeout                                             */
+#define SDMMC_STA_VSWEND_Pos             (25U)
+#define SDMMC_STA_VSWEND_Msk             (0x1UL << SDMMC_STA_VSWEND_Pos)       /*!< 0x02000000 */
+#define SDMMC_STA_VSWEND                 SDMMC_STA_VSWEND_Msk                  /*!<Voltage switch critical timing section completion                       */
+#define SDMMC_STA_CKSTOP_Pos             (26U)
+#define SDMMC_STA_CKSTOP_Msk             (0x1UL << SDMMC_STA_CKSTOP_Pos)       /*!< 0x04000000 */
+#define SDMMC_STA_CKSTOP                 SDMMC_STA_CKSTOP_Msk                  /*!<SDMMC_CK stopped in Voltage switch procedure                            */
+#define SDMMC_STA_IDMATE_Pos             (27U)
+#define SDMMC_STA_IDMATE_Msk             (0x1UL << SDMMC_STA_IDMATE_Pos)       /*!< 0x08000000 */
+#define SDMMC_STA_IDMATE                 SDMMC_STA_IDMATE_Msk                  /*!<IDMA transfer error                                                     */
+#define SDMMC_STA_IDMABTC_Pos            (28U)
+#define SDMMC_STA_IDMABTC_Msk            (0x1UL << SDMMC_STA_IDMABTC_Pos)      /*!< 0x10000000 */
+#define SDMMC_STA_IDMABTC                SDMMC_STA_IDMABTC_Msk                 /*!<IDMA buffer transfer complete                                           */
+
+/*******************  Bit definition for SDMMC_ICR register  *******************/
+#define SDMMC_ICR_CCRCFAILC_Pos          (0U)
+#define SDMMC_ICR_CCRCFAILC_Msk          (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)    /*!< 0x00000001 */
+#define SDMMC_ICR_CCRCFAILC              SDMMC_ICR_CCRCFAILC_Msk               /*!<CCRCFAIL flag clear bit */
+#define SDMMC_ICR_DCRCFAILC_Pos          (1U)
+#define SDMMC_ICR_DCRCFAILC_Msk          (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)    /*!< 0x00000002 */
+#define SDMMC_ICR_DCRCFAILC              SDMMC_ICR_DCRCFAILC_Msk               /*!<DCRCFAIL flag clear bit */
+#define SDMMC_ICR_CTIMEOUTC_Pos          (2U)
+#define SDMMC_ICR_CTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)    /*!< 0x00000004 */
+#define SDMMC_ICR_CTIMEOUTC              SDMMC_ICR_CTIMEOUTC_Msk               /*!<CTIMEOUT flag clear bit */
+#define SDMMC_ICR_DTIMEOUTC_Pos          (3U)
+#define SDMMC_ICR_DTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)    /*!< 0x00000008 */
+#define SDMMC_ICR_DTIMEOUTC              SDMMC_ICR_DTIMEOUTC_Msk               /*!<DTIMEOUT flag clear bit */
+#define SDMMC_ICR_TXUNDERRC_Pos          (4U)
+#define SDMMC_ICR_TXUNDERRC_Msk          (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)    /*!< 0x00000010 */
+#define SDMMC_ICR_TXUNDERRC              SDMMC_ICR_TXUNDERRC_Msk               /*!<TXUNDERR flag clear bit */
+#define SDMMC_ICR_RXOVERRC_Pos           (5U)
+#define SDMMC_ICR_RXOVERRC_Msk           (0x1UL << SDMMC_ICR_RXOVERRC_Pos)     /*!< 0x00000020 */
+#define SDMMC_ICR_RXOVERRC               SDMMC_ICR_RXOVERRC_Msk                /*!<RXOVERR flag clear bit  */
+#define SDMMC_ICR_CMDRENDC_Pos           (6U)
+#define SDMMC_ICR_CMDRENDC_Msk           (0x1UL << SDMMC_ICR_CMDRENDC_Pos)     /*!< 0x00000040 */
+#define SDMMC_ICR_CMDRENDC               SDMMC_ICR_CMDRENDC_Msk                /*!<CMDREND flag clear bit  */
+#define SDMMC_ICR_CMDSENTC_Pos           (7U)
+#define SDMMC_ICR_CMDSENTC_Msk           (0x1UL << SDMMC_ICR_CMDSENTC_Pos)     /*!< 0x00000080 */
+#define SDMMC_ICR_CMDSENTC               SDMMC_ICR_CMDSENTC_Msk                /*!<CMDSENT flag clear bit  */
+#define SDMMC_ICR_DATAENDC_Pos           (8U)
+#define SDMMC_ICR_DATAENDC_Msk           (0x1UL << SDMMC_ICR_DATAENDC_Pos)     /*!< 0x00000100 */
+#define SDMMC_ICR_DATAENDC               SDMMC_ICR_DATAENDC_Msk                /*!<DATAEND flag clear bit  */
+#define SDMMC_ICR_DHOLDC_Pos             (9U)
+#define SDMMC_ICR_DHOLDC_Msk             (0x1UL << SDMMC_ICR_DHOLDC_Pos)       /*!< 0x00000200 */
+#define SDMMC_ICR_DHOLDC                 SDMMC_ICR_DHOLDC_Msk                  /*!<DHOLD flag clear bit       */
+#define SDMMC_ICR_DBCKENDC_Pos           (10U)
+#define SDMMC_ICR_DBCKENDC_Msk           (0x1UL << SDMMC_ICR_DBCKENDC_Pos)     /*!< 0x00000400 */
+#define SDMMC_ICR_DBCKENDC               SDMMC_ICR_DBCKENDC_Msk                /*!<DBCKEND flag clear bit  */
+#define SDMMC_ICR_DABORTC_Pos            (11U)
+#define SDMMC_ICR_DABORTC_Msk            (0x1UL << SDMMC_ICR_DABORTC_Pos)      /*!< 0x00000800 */
+#define SDMMC_ICR_DABORTC                SDMMC_ICR_DABORTC_Msk                 /*!<DABORTC flag clear bit     */
+#define SDMMC_ICR_BUSYD0ENDC_Pos         (21U)
+#define SDMMC_ICR_BUSYD0ENDC_Msk         (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos)   /*!< 0x00200000 */
+#define SDMMC_ICR_BUSYD0ENDC             SDMMC_ICR_BUSYD0ENDC_Msk              /*!<BUSYD0ENDC flag clear bit  */
+#define SDMMC_ICR_SDIOITC_Pos            (22U)
+#define SDMMC_ICR_SDIOITC_Msk            (0x1UL << SDMMC_ICR_SDIOITC_Pos)      /*!< 0x00400000 */
+#define SDMMC_ICR_SDIOITC                SDMMC_ICR_SDIOITC_Msk                 /*!<SDIOIT flag clear bit      */
+#define SDMMC_ICR_ACKFAILC_Pos           (23U)
+#define SDMMC_ICR_ACKFAILC_Msk           (0x1UL << SDMMC_ICR_ACKFAILC_Pos)     /*!< 0x00800000 */
+#define SDMMC_ICR_ACKFAILC               SDMMC_ICR_ACKFAILC_Msk                /*!<ACKFAILC flag clear bit    */
+#define SDMMC_ICR_ACKTIMEOUTC_Pos        (24U)
+#define SDMMC_ICR_ACKTIMEOUTC_Msk        (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos)  /*!< 0x01000000 */
+#define SDMMC_ICR_ACKTIMEOUTC            SDMMC_ICR_ACKTIMEOUTC_Msk             /*!<ACKTIMEOUTC flag clear bit */
+#define SDMMC_ICR_VSWENDC_Pos            (25U)
+#define SDMMC_ICR_VSWENDC_Msk            (0x1UL << SDMMC_ICR_VSWENDC_Pos)      /*!< 0x02000000 */
+#define SDMMC_ICR_VSWENDC                SDMMC_ICR_VSWENDC_Msk                 /*!<VSWENDC flag clear bit     */
+#define SDMMC_ICR_CKSTOPC_Pos            (26U)
+#define SDMMC_ICR_CKSTOPC_Msk            (0x1UL << SDMMC_ICR_CKSTOPC_Pos)      /*!< 0x04000000 */
+#define SDMMC_ICR_CKSTOPC                SDMMC_ICR_CKSTOPC_Msk                 /*!<CKSTOPC flag clear bit     */
+#define SDMMC_ICR_IDMATEC_Pos            (27U)
+#define SDMMC_ICR_IDMATEC_Msk            (0x1UL << SDMMC_ICR_IDMATEC_Pos)      /*!< 0x08000000 */
+#define SDMMC_ICR_IDMATEC                SDMMC_ICR_IDMATEC_Msk                 /*!<IDMATEC flag clear bit     */
+#define SDMMC_ICR_IDMABTCC_Pos           (28U)
+#define SDMMC_ICR_IDMABTCC_Msk           (0x1UL << SDMMC_ICR_IDMABTCC_Pos)     /*!< 0x10000000 */
+#define SDMMC_ICR_IDMABTCC               SDMMC_ICR_IDMABTCC_Msk                /*!<IDMABTCC flag clear bit    */
+
+/******************  Bit definition for SDMMC_MASK register  *******************/
+#define SDMMC_MASK_CCRCFAILIE_Pos        (0U)
+#define SDMMC_MASK_CCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)  /*!< 0x00000001 */
+#define SDMMC_MASK_CCRCFAILIE            SDMMC_MASK_CCRCFAILIE_Msk             /*!<Command CRC Fail Interrupt Enable          */
+#define SDMMC_MASK_DCRCFAILIE_Pos        (1U)
+#define SDMMC_MASK_DCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)  /*!< 0x00000002 */
+#define SDMMC_MASK_DCRCFAILIE            SDMMC_MASK_DCRCFAILIE_Msk             /*!<Data CRC Fail Interrupt Enable             */
+#define SDMMC_MASK_CTIMEOUTIE_Pos        (2U)
+#define SDMMC_MASK_CTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)  /*!< 0x00000004 */
+#define SDMMC_MASK_CTIMEOUTIE            SDMMC_MASK_CTIMEOUTIE_Msk             /*!<Command TimeOut Interrupt Enable           */
+#define SDMMC_MASK_DTIMEOUTIE_Pos        (3U)
+#define SDMMC_MASK_DTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)  /*!< 0x00000008 */
+#define SDMMC_MASK_DTIMEOUTIE            SDMMC_MASK_DTIMEOUTIE_Msk             /*!<Data TimeOut Interrupt Enable              */
+#define SDMMC_MASK_TXUNDERRIE_Pos        (4U)
+#define SDMMC_MASK_TXUNDERRIE_Msk        (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)  /*!< 0x00000010 */
+#define SDMMC_MASK_TXUNDERRIE            SDMMC_MASK_TXUNDERRIE_Msk             /*!<Tx FIFO UnderRun Error Interrupt Enable    */
+#define SDMMC_MASK_RXOVERRIE_Pos         (5U)
+#define SDMMC_MASK_RXOVERRIE_Msk         (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)   /*!< 0x00000020 */
+#define SDMMC_MASK_RXOVERRIE             SDMMC_MASK_RXOVERRIE_Msk              /*!<Rx FIFO OverRun Error Interrupt Enable     */
+#define SDMMC_MASK_CMDRENDIE_Pos         (6U)
+#define SDMMC_MASK_CMDRENDIE_Msk         (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)   /*!< 0x00000040 */
+#define SDMMC_MASK_CMDRENDIE             SDMMC_MASK_CMDRENDIE_Msk              /*!<Command Response Received Interrupt Enable */
+#define SDMMC_MASK_CMDSENTIE_Pos         (7U)
+#define SDMMC_MASK_CMDSENTIE_Msk         (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)   /*!< 0x00000080 */
+#define SDMMC_MASK_CMDSENTIE             SDMMC_MASK_CMDSENTIE_Msk              /*!<Command Sent Interrupt Enable              */
+#define SDMMC_MASK_DATAENDIE_Pos         (8U)
+#define SDMMC_MASK_DATAENDIE_Msk         (0x1UL << SDMMC_MASK_DATAENDIE_Pos)   /*!< 0x00000100 */
+#define SDMMC_MASK_DATAENDIE             SDMMC_MASK_DATAENDIE_Msk              /*!<Data End Interrupt Enable                  */
+#define SDMMC_MASK_DHOLDIE_Pos           (9U)
+#define SDMMC_MASK_DHOLDIE_Msk           (0x1UL << SDMMC_MASK_DHOLDIE_Pos)     /*!< 0x00000200 */
+#define SDMMC_MASK_DHOLDIE               SDMMC_MASK_DHOLDIE_Msk                /*!<Data Hold Interrupt Enable                 */
+#define SDMMC_MASK_DBCKENDIE_Pos         (10U)
+#define SDMMC_MASK_DBCKENDIE_Msk         (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)   /*!< 0x00000400 */
+#define SDMMC_MASK_DBCKENDIE             SDMMC_MASK_DBCKENDIE_Msk              /*!<Data Block End Interrupt Enable            */
+#define SDMMC_MASK_DABORTIE_Pos          (11U)
+#define SDMMC_MASK_DABORTIE_Msk          (0x1UL << SDMMC_MASK_DABORTIE_Pos)    /*!< 0x00000800 */
+#define SDMMC_MASK_DABORTIE              SDMMC_MASK_DABORTIE_Msk               /*!<Data transfer aborted interrupt enable     */
+
+#define SDMMC_MASK_TXFIFOHEIE_Pos        (14U)
+#define SDMMC_MASK_TXFIFOHEIE_Msk        (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)  /*!< 0x00004000 */
+#define SDMMC_MASK_TXFIFOHEIE            SDMMC_MASK_TXFIFOHEIE_Msk             /*!<Tx FIFO Half Empty interrupt Enable        */
+#define SDMMC_MASK_RXFIFOHFIE_Pos        (15U)
+#define SDMMC_MASK_RXFIFOHFIE_Msk        (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)  /*!< 0x00008000 */
+#define SDMMC_MASK_RXFIFOHFIE            SDMMC_MASK_RXFIFOHFIE_Msk             /*!<Rx FIFO Half Full interrupt Enable         */
+
+#define SDMMC_MASK_RXFIFOFIE_Pos         (17U)
+#define SDMMC_MASK_RXFIFOFIE_Msk         (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)   /*!< 0x00020000 */
+#define SDMMC_MASK_RXFIFOFIE             SDMMC_MASK_RXFIFOFIE_Msk              /*!<Rx FIFO Full interrupt Enable              */
+#define SDMMC_MASK_TXFIFOEIE_Pos         (18U)
+#define SDMMC_MASK_TXFIFOEIE_Msk         (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)   /*!< 0x00040000 */
+#define SDMMC_MASK_TXFIFOEIE             SDMMC_MASK_TXFIFOEIE_Msk              /*!<Tx FIFO Empty interrupt Enable             */
+
+#define SDMMC_MASK_BUSYD0ENDIE_Pos       (21U)
+#define SDMMC_MASK_BUSYD0ENDIE_Msk       (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */
+#define SDMMC_MASK_BUSYD0ENDIE           SDMMC_MASK_BUSYD0ENDIE_Msk            /*!<BUSYD0ENDIE interrupt Enable */
+#define SDMMC_MASK_SDIOITIE_Pos           (22U)
+#define SDMMC_MASK_SDIOITIE_Msk           (0x1UL << SDMMC_MASK_SDIOITIE_Pos)     /*!< 0x00400000 */
+#define SDMMC_MASK_SDIOITIE               SDMMC_MASK_SDIOITIE_Msk                /*!<SDMMC Mode Interrupt Received interrupt Enable */
+#define SDMMC_MASK_ACKFAILIE_Pos         (23U)
+#define SDMMC_MASK_ACKFAILIE_Msk         (0x1UL << SDMMC_MASK_ACKFAILIE_Pos)   /*!< 0x00800000 */
+#define SDMMC_MASK_ACKFAILIE             SDMMC_MASK_ACKFAILIE_Msk              /*!<Acknowledgment Fail Interrupt Enable */
+#define SDMMC_MASK_ACKTIMEOUTIE_Pos      (24U)
+#define SDMMC_MASK_ACKTIMEOUTIE_Msk      (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */
+#define SDMMC_MASK_ACKTIMEOUTIE          SDMMC_MASK_ACKTIMEOUTIE_Msk           /*!<Acknowledgment timeout Interrupt Enable */
+#define SDMMC_MASK_VSWENDIE_Pos          (25U)
+#define SDMMC_MASK_VSWENDIE_Msk          (0x1UL << SDMMC_MASK_VSWENDIE_Pos)    /*!< 0x02000000 */
+#define SDMMC_MASK_VSWENDIE              SDMMC_MASK_VSWENDIE_Msk               /*!<Voltage switch critical timing section completion Interrupt Enable */
+#define SDMMC_MASK_CKSTOPIE_Pos          (26U)
+#define SDMMC_MASK_CKSTOPIE_Msk          (0x1UL << SDMMC_MASK_CKSTOPIE_Pos)    /*!< 0x04000000 */
+#define SDMMC_MASK_CKSTOPIE              SDMMC_MASK_CKSTOPIE_Msk               /*!<Voltage Switch clock stopped Interrupt Enable */
+#define SDMMC_MASK_IDMABTCIE_Pos         (28U)
+#define SDMMC_MASK_IDMABTCIE_Msk         (0x1UL << SDMMC_MASK_IDMABTCIE_Pos)   /*!< 0x10000000 */
+#define SDMMC_MASK_IDMABTCIE             SDMMC_MASK_IDMABTCIE_Msk              /*!<IDMA buffer transfer complete Interrupt Enable */
+
+/*****************  Bit definition for SDMMC_ACKTIME register  *****************/
+#define SDMMC_ACKTIME_ACKTIME_Pos        (0U)
+#define SDMMC_ACKTIME_ACKTIME_Msk        (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_ACKTIME_ACKTIME            SDMMC_ACKTIME_ACKTIME_Msk             /*!<Boot acknowledgment timeout period */
+
+/******************  Bit definition for SDMMC_FIFO register  *******************/
+#define SDMMC_FIFO_FIFODATA_Pos          (0U)
+#define SDMMC_FIFO_FIFODATA_Msk          (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_FIFO_FIFODATA              SDMMC_FIFO_FIFODATA_Msk               /*!<Receive and transmit FIFO data */
+
+/******************  Bit definition for SDMMC_IDMACTRL register ****************/
+#define SDMMC_IDMA_IDMAEN_Pos            (0U)
+#define SDMMC_IDMA_IDMAEN_Msk            (0x1UL << SDMMC_IDMA_IDMAEN_Pos)      /*!< 0x00000001 */
+#define SDMMC_IDMA_IDMAEN                SDMMC_IDMA_IDMAEN_Msk                 /*!< Enable the internal DMA of the SDMMC peripheral */
+#define SDMMC_IDMA_IDMABMODE_Pos         (1U)
+#define SDMMC_IDMA_IDMABMODE_Msk         (0x1UL << SDMMC_IDMA_IDMABMODE_Pos)   /*!< 0x00000002 */
+#define SDMMC_IDMA_IDMABMODE             SDMMC_IDMA_IDMABMODE_Msk              /*!< Enable double buffer mode for IDMA */
+#define SDMMC_IDMA_IDMABACT_Pos          (2U)
+#define SDMMC_IDMA_IDMABACT_Msk          (0x1UL << SDMMC_IDMA_IDMABACT_Pos)    /*!< 0x00000004 */
+#define SDMMC_IDMA_IDMABACT              SDMMC_IDMA_IDMABACT_Msk               /*!< Uses buffer 1 when double buffer mode is selected */
+
+/*****************  Bit definition for SDMMC_IDMABSIZE register  ***************/
+#define SDMMC_IDMABSIZE_IDMABNDT_Pos     (5U)
+#define SDMMC_IDMABSIZE_IDMABNDT_Msk     (0xFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos) /*!< 0x00001FE0 */
+#define SDMMC_IDMABSIZE_IDMABNDT         SDMMC_IDMABSIZE_IDMABNDT_Msk          /*!< Number of transfers per buffer */
+
+/*****************  Bit definition for SDMMC_IDMABASE0 register  ***************/
+#define SDMMC_IDMABASE0_IDMABASE0        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 0 memory base address */
+
+/*****************  Bit definition for SDMMC_IDMABASE1 register  ***************/
+#define SDMMC_IDMABASE1_IDMABASE1        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 1 memory base address */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Delay Block Interface (DLYB)                        */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for DLYB_CR register  ********************/
+#define DLYB_CR_DEN_Pos         (0U)
+#define DLYB_CR_DEN_Msk         (0x1UL << DLYB_CR_DEN_Pos)                     /*!< 0x00000001 */
+#define DLYB_CR_DEN             DLYB_CR_DEN_Msk                                /*!<Delay Block enable */
+#define DLYB_CR_SEN_Pos         (1U)
+#define DLYB_CR_SEN_Msk         (0x1UL << DLYB_CR_SEN_Pos)                     /*!< 0x00000002 */
+#define DLYB_CR_SEN             DLYB_CR_SEN_Msk                                /*!<Sampler length enable */
+
+
+/*******************  Bit definition for DLYB_CFGR register  ********************/
+#define DLYB_CFGR_SEL_Pos       (0U)
+#define DLYB_CFGR_SEL_Msk       (0xFUL << DLYB_CFGR_SEL_Pos)                   /*!< 0x0000000F */
+#define DLYB_CFGR_SEL           DLYB_CFGR_SEL_Msk                              /*!<Select the phase for the Output clock[3:0] */
+#define DLYB_CFGR_SEL_0         (0x1UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000001 */
+#define DLYB_CFGR_SEL_1         (0x2UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000002 */
+#define DLYB_CFGR_SEL_2         (0x3UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000003 */
+#define DLYB_CFGR_SEL_3         (0x8UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000008 */
+
+#define DLYB_CFGR_UNIT_Pos      (8U)
+#define DLYB_CFGR_UNIT_Msk      (0x7FUL << DLYB_CFGR_UNIT_Pos)                 /*!< 0x00007F00 */
+#define DLYB_CFGR_UNIT          DLYB_CFGR_UNIT_Msk                             /*!<Delay Defines the delay of a Unit delay cell[6:0] */
+#define DLYB_CFGR_UNIT_0        (0x01UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000100 */
+#define DLYB_CFGR_UNIT_1        (0x02UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000200 */
+#define DLYB_CFGR_UNIT_2        (0x04UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000400 */
+#define DLYB_CFGR_UNIT_3        (0x08UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000800 */
+#define DLYB_CFGR_UNIT_4        (0x10UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00001000 */
+#define DLYB_CFGR_UNIT_5        (0x20UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00002000 */
+#define DLYB_CFGR_UNIT_6        (0x40UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00004000 */
+
+#define DLYB_CFGR_LNG_Pos       (16U)
+#define DLYB_CFGR_LNG_Msk       (0xFFFUL << DLYB_CFGR_LNG_Pos)                 /*!< 0x0FFF0000 */
+#define DLYB_CFGR_LNG           DLYB_CFGR_LNG_Msk                              /*!<Delay line length value[11:0] */
+#define DLYB_CFGR_LNG_0         (0x001UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00010000 */
+#define DLYB_CFGR_LNG_1         (0x002UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00020000 */
+#define DLYB_CFGR_LNG_2         (0x004UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00040000 */
+#define DLYB_CFGR_LNG_3         (0x008UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00080000 */
+#define DLYB_CFGR_LNG_4         (0x010UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00100000 */
+#define DLYB_CFGR_LNG_5         (0x020UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00200000 */
+#define DLYB_CFGR_LNG_6         (0x040UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00400000 */
+#define DLYB_CFGR_LNG_7         (0x080UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00800000 */
+#define DLYB_CFGR_LNG_8         (0x100UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x01000000 */
+#define DLYB_CFGR_LNG_9         (0x200UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x02000000 */
+#define DLYB_CFGR_LNG_10        (0x400UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x04000000 */
+#define DLYB_CFGR_LNG_11        (0x800UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x08000000 */
+
+#define DLYB_CFGR_LNGF_Pos      (31U)
+#define DLYB_CFGR_LNGF_Msk      (0x1UL << DLYB_CFGR_LNGF_Pos)                  /*!< 0x80000000 */
+#define DLYB_CFGR_LNGF          DLYB_CFGR_LNGF_Msk                             /*!<Length valid flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                   Serial Peripheral Interface (SPI/I2S)                    */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define SPI_CR1_SPE_Pos             (0U)
+#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000001 */
+#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<Serial Peripheral Enable                         */
+#define SPI_CR1_MASRX_Pos           (8U)
+#define SPI_CR1_MASRX_Msk           (0x1UL << SPI_CR1_MASRX_Pos)               /*!< 0x00000100 */
+#define SPI_CR1_MASRX               SPI_CR1_MASRX_Msk                          /*!<Master automatic SUSP in Receive mode            */
+#define SPI_CR1_CSTART_Pos          (9U)
+#define SPI_CR1_CSTART_Msk          (0x1UL << SPI_CR1_CSTART_Pos)              /*!< 0x00000200 */
+#define SPI_CR1_CSTART              SPI_CR1_CSTART_Msk                         /*!<Master transfer start                            */
+#define SPI_CR1_CSUSP_Pos           (10U)
+#define SPI_CR1_CSUSP_Msk           (0x1UL << SPI_CR1_CSUSP_Pos)               /*!< 0x00000400 */
+#define SPI_CR1_CSUSP               SPI_CR1_CSUSP_Msk                          /*!<Master SUSPend request                           */
+#define SPI_CR1_HDDIR_Pos           (11U)
+#define SPI_CR1_HDDIR_Msk           (0x1UL << SPI_CR1_HDDIR_Pos)               /*!< 0x00000800 */
+#define SPI_CR1_HDDIR               SPI_CR1_HDDIR_Msk                          /*!<Rx/Tx direction at Half-duplex mode              */
+#define SPI_CR1_SSI_Pos             (12U)
+#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                 /*!< 0x00001000 */
+#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal SS signal input level                   */
+#define SPI_CR1_CRC33_17_Pos        (13U)
+#define SPI_CR1_CRC33_17_Msk        (0x1UL << SPI_CR1_CRC33_17_Pos)            /*!< 0x00002000 */
+#define SPI_CR1_CRC33_17             SPI_CR1_CRC33_17_Msk                      /*!<32-bit CRC polynomial configuration              */
+#define SPI_CR1_RCRCINI_Pos         (14U)
+#define SPI_CR1_RCRCINI_Msk         (0x1UL << SPI_CR1_RCRCINI_Pos)             /*!< 0x00004000 */
+#define SPI_CR1_RCRCINI             SPI_CR1_RCRCINI_Msk                        /*!<CRC init pattern control for receiver            */
+#define SPI_CR1_TCRCINI_Pos         (15U)
+#define SPI_CR1_TCRCINI_Msk         (0x1UL << SPI_CR1_TCRCINI_Pos)             /*!< 0x00008000 */
+#define SPI_CR1_TCRCINI             SPI_CR1_TCRCINI_Msk                        /*!<CRC init pattern control for transmitter         */
+#define SPI_CR1_IOLOCK_Pos          (16U)
+#define SPI_CR1_IOLOCK_Msk          (0x1UL << SPI_CR1_IOLOCK_Pos)              /*!< 0x00010000 */
+#define SPI_CR1_IOLOCK              SPI_CR1_IOLOCK_Msk                         /*!<Locking the AF configuration of associated IOs   */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define SPI_CR2_TSER_Pos            (16U)
+#define SPI_CR2_TSER_Msk            (0xFFFFUL << SPI_CR2_TSER_Pos)             /*!< 0xFFFF0000 */
+#define SPI_CR2_TSER                SPI_CR2_TSER_Msk                           /*!<Number of data transfer extension                */
+#define SPI_CR2_TSIZE_Pos           (0U)
+#define SPI_CR2_TSIZE_Msk           (0xFFFFUL << SPI_CR2_TSIZE_Pos)            /*!< 0x0000FFFF */
+#define SPI_CR2_TSIZE               SPI_CR2_TSIZE_Msk                          /*!<Number of data at current transfer               */
+
+/*******************  Bit definition for SPI_CFG1 register  ********************/
+#define SPI_CFG1_DSIZE_Pos          (0U)
+#define SPI_CFG1_DSIZE_Msk          (0x1FUL << SPI_CFG1_DSIZE_Pos)             /*!< 0x0000001F */
+#define SPI_CFG1_DSIZE              SPI_CFG1_DSIZE_Msk                         /*!<DSIZE[4:0]: Bits number in single SPI data frame */
+#define SPI_CFG1_DSIZE_0            (0x01UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000001 */
+#define SPI_CFG1_DSIZE_1            (0x02UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000002 */
+#define SPI_CFG1_DSIZE_2            (0x04UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000004 */
+#define SPI_CFG1_DSIZE_3            (0x08UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000008 */
+#define SPI_CFG1_DSIZE_4            (0x10UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000010 */
+
+#define SPI_CFG1_FTHLV_Pos          (5U)
+#define SPI_CFG1_FTHLV_Msk          (0xFUL << SPI_CFG1_FTHLV_Pos)              /*!< 0x000001E0 */
+#define SPI_CFG1_FTHLV              SPI_CFG1_FTHLV_Msk                         /*!<FTHVL [3:0]: FIFO threshold level*/
+#define SPI_CFG1_FTHLV_0            (0x1UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000020 */
+#define SPI_CFG1_FTHLV_1            (0x2UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000040 */
+#define SPI_CFG1_FTHLV_2            (0x4UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000080 */
+#define SPI_CFG1_FTHLV_3            (0x8UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000100 */
+
+#define SPI_CFG1_UDRCFG_Pos         (9U)
+#define SPI_CFG1_UDRCFG_Msk         (0x3UL << SPI_CFG1_UDRCFG_Pos)             /*!< 0x00000600 */
+#define SPI_CFG1_UDRCFG             SPI_CFG1_UDRCFG_Msk                        /*!<UDRCFG[1:0]: Behavior of transmitter at underrun */
+#define SPI_CFG1_UDRCFG_0           (0x1UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000200 */
+#define SPI_CFG1_UDRCFG_1           (0x2UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000400 */
+
+
+#define SPI_CFG1_UDRDET_Pos         (11U)
+#define SPI_CFG1_UDRDET_Msk         (0x3UL << SPI_CFG1_UDRDET_Pos)             /*!< 0x00001800 */
+#define SPI_CFG1_UDRDET             SPI_CFG1_UDRDET_Msk                        /*!<UDRDET[1:0]: Detection of underrun condition     */
+#define SPI_CFG1_UDRDET_0           (0x1UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00000800 */
+#define SPI_CFG1_UDRDET_1           (0x2UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00001000 */
+
+#define SPI_CFG1_RXDMAEN_Pos        (14U)
+#define SPI_CFG1_RXDMAEN_Msk        (0x1UL << SPI_CFG1_RXDMAEN_Pos)            /*!< 0x00004000 */
+#define SPI_CFG1_RXDMAEN            SPI_CFG1_RXDMAEN_Msk                       /*!<Rx DMA stream enable                */
+#define SPI_CFG1_TXDMAEN_Pos        (15U)
+#define SPI_CFG1_TXDMAEN_Msk        (0x1UL << SPI_CFG1_TXDMAEN_Pos)            /*!< 0x00008000 */
+#define SPI_CFG1_TXDMAEN            SPI_CFG1_TXDMAEN_Msk                       /*!<Tx DMA stream enable                */
+
+#define SPI_CFG1_CRCSIZE_Pos        (16U)
+#define SPI_CFG1_CRCSIZE_Msk        (0x1FUL << SPI_CFG1_CRCSIZE_Pos)           /*!< 0x001F0000 */
+#define SPI_CFG1_CRCSIZE            SPI_CFG1_CRCSIZE_Msk                       /*!<CRCSIZE [4:0]: Length of CRC frame*/
+#define SPI_CFG1_CRCSIZE_0          (0x01UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00010000 */
+#define SPI_CFG1_CRCSIZE_1          (0x02UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00020000 */
+#define SPI_CFG1_CRCSIZE_2          (0x04UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00040000 */
+#define SPI_CFG1_CRCSIZE_3          (0x08UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00080000 */
+#define SPI_CFG1_CRCSIZE_4          (0x10UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00100000 */
+
+#define SPI_CFG1_CRCEN_Pos          (22U)
+#define SPI_CFG1_CRCEN_Msk          (0x1UL << SPI_CFG1_CRCEN_Pos)              /*!< 0x00400000 */
+#define SPI_CFG1_CRCEN              SPI_CFG1_CRCEN_Msk                         /*!<Hardware CRC computation enable */
+
+#define SPI_CFG1_MBR_Pos            (28U)
+#define SPI_CFG1_MBR_Msk            (0x7UL << SPI_CFG1_MBR_Pos)                /*!< 0x70000000 */
+#define SPI_CFG1_MBR                SPI_CFG1_MBR_Msk                           /*!<Master baud rate                */
+#define SPI_CFG1_MBR_0              (0x1UL << SPI_CFG1_MBR_Pos)                 /*!< 0x10000000 */
+#define SPI_CFG1_MBR_1              (0x2UL << SPI_CFG1_MBR_Pos)                 /*!< 0x20000000 */
+#define SPI_CFG1_MBR_2              (0x4UL << SPI_CFG1_MBR_Pos)                 /*!< 0x40000000 */
+
+/*******************  Bit definition for SPI_CFG2 register  ********************/
+#define SPI_CFG2_MSSI_Pos           (0U)
+#define SPI_CFG2_MSSI_Msk           (0xFUL << SPI_CFG2_MSSI_Pos)               /*!< 0x0000000F */
+#define SPI_CFG2_MSSI               SPI_CFG2_MSSI_Msk                          /*!<Master SS Idleness */
+#define SPI_CFG2_MSSI_0             (0x1UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000001 */
+#define SPI_CFG2_MSSI_1             (0x2UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000002 */
+#define SPI_CFG2_MSSI_2             (0x4UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000004 */
+#define SPI_CFG2_MSSI_3             (0x8UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000008 */
+
+#define SPI_CFG2_MIDI_Pos           (4U)
+#define SPI_CFG2_MIDI_Msk           (0xFUL << SPI_CFG2_MIDI_Pos)               /*!< 0x000000F0 */
+#define SPI_CFG2_MIDI               SPI_CFG2_MIDI_Msk                          /*!<Master Inter-Data Idleness */
+#define SPI_CFG2_MIDI_0             (0x1UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000010 */
+#define SPI_CFG2_MIDI_1             (0x2UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000020 */
+#define SPI_CFG2_MIDI_2             (0x4UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000040 */
+#define SPI_CFG2_MIDI_3             (0x8UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000080 */
+
+#define SPI_CFG2_IOSWP_Pos          (15U)
+#define SPI_CFG2_IOSWP_Msk          (0x1UL << SPI_CFG2_IOSWP_Pos)              /*!< 0x00008000 */
+#define SPI_CFG2_IOSWP              SPI_CFG2_IOSWP_Msk                         /*!<Swap functionality of MISO and MOSI pins */
+
+#define SPI_CFG2_COMM_Pos           (17U)
+#define SPI_CFG2_COMM_Msk           (0x3UL << SPI_CFG2_COMM_Pos)               /*!< 0x00060000 */
+#define SPI_CFG2_COMM               SPI_CFG2_COMM_Msk                          /*!<COMM [1:0]: SPI Communication Mode*/
+#define SPI_CFG2_COMM_0             (0x1UL << SPI_CFG2_COMM_Pos)                /*!< 0x00020000 */
+#define SPI_CFG2_COMM_1             (0x2UL << SPI_CFG2_COMM_Pos)                /*!< 0x00040000 */
+
+#define SPI_CFG2_SP_Pos             (19U)
+#define SPI_CFG2_SP_Msk             (0x7UL << SPI_CFG2_SP_Pos)                 /*!< 0x00380000 */
+#define SPI_CFG2_SP                 SPI_CFG2_SP_Msk                            /*!<SP[2:0]: Serial Protocol */
+#define SPI_CFG2_SP_0               (0x1UL << SPI_CFG2_SP_Pos)                  /*!< 0x00080000 */
+#define SPI_CFG2_SP_1               (0x2UL << SPI_CFG2_SP_Pos)                  /*!< 0x00100000 */
+#define SPI_CFG2_SP_2               (0x4UL << SPI_CFG2_SP_Pos)                  /*!< 0x00200000 */
+
+#define SPI_CFG2_MASTER_Pos         (22U)
+#define SPI_CFG2_MASTER_Msk         (0x1UL << SPI_CFG2_MASTER_Pos)             /*!< 0x00400000 */
+#define SPI_CFG2_MASTER             SPI_CFG2_MASTER_Msk                        /*!<SPI Master           */
+#define SPI_CFG2_LSBFRST_Pos        (23U)
+#define SPI_CFG2_LSBFRST_Msk        (0x1UL << SPI_CFG2_LSBFRST_Pos)            /*!< 0x00800000 */
+#define SPI_CFG2_LSBFRST            SPI_CFG2_LSBFRST_Msk                       /*!<Data frame format               */
+#define SPI_CFG2_CPHA_Pos           (24U)
+#define SPI_CFG2_CPHA_Msk           (0x1UL << SPI_CFG2_CPHA_Pos)               /*!< 0x01000000 */
+#define SPI_CFG2_CPHA               SPI_CFG2_CPHA_Msk                          /*!<Clock Phase      */
+#define SPI_CFG2_CPOL_Pos           (25U)
+#define SPI_CFG2_CPOL_Msk           (0x1UL << SPI_CFG2_CPOL_Pos)               /*!< 0x02000000 */
+#define SPI_CFG2_CPOL               SPI_CFG2_CPOL_Msk                          /*!<Clock Polarity   */
+#define SPI_CFG2_SSM_Pos            (26U)
+#define SPI_CFG2_SSM_Msk            (0x1UL << SPI_CFG2_SSM_Pos)                /*!< 0x04000000 */
+#define SPI_CFG2_SSM                SPI_CFG2_SSM_Msk                           /*!<Software slave management */
+
+#define SPI_CFG2_SSIOP_Pos          (28U)
+#define SPI_CFG2_SSIOP_Msk          (0x1UL << SPI_CFG2_SSIOP_Pos)              /*!< 0x10000000 */
+#define SPI_CFG2_SSIOP              SPI_CFG2_SSIOP_Msk                         /*!<SS input/output polarity */
+#define SPI_CFG2_SSOE_Pos           (29U)
+#define SPI_CFG2_SSOE_Msk           (0x1UL << SPI_CFG2_SSOE_Pos)               /*!< 0x20000000 */
+#define SPI_CFG2_SSOE               SPI_CFG2_SSOE_Msk                          /*!<SS output enable */
+#define SPI_CFG2_SSOM_Pos           (30U)
+#define SPI_CFG2_SSOM_Msk           (0x1UL << SPI_CFG2_SSOM_Pos)               /*!< 0x40000000 */
+#define SPI_CFG2_SSOM               SPI_CFG2_SSOM_Msk                          /*!<SS output management in master mode */
+
+#define SPI_CFG2_AFCNTR_Pos         (31U)
+#define SPI_CFG2_AFCNTR_Msk         (0x1UL << SPI_CFG2_AFCNTR_Pos)             /*!< 0x80000000 */
+#define SPI_CFG2_AFCNTR             SPI_CFG2_AFCNTR_Msk                        /*!<Alternate function GPIOs control */
+
+/*******************  Bit definition for SPI_IER register  ********************/
+#define SPI_IER_RXPIE_Pos           (0U)
+#define SPI_IER_RXPIE_Msk           (0x1UL << SPI_IER_RXPIE_Pos)               /*!< 0x00000001 */
+#define SPI_IER_RXPIE               SPI_IER_RXPIE_Msk                          /*!<RXP Interrupt Enable            */
+#define SPI_IER_TXPIE_Pos           (1U)
+#define SPI_IER_TXPIE_Msk           (0x1UL << SPI_IER_TXPIE_Pos)               /*!< 0x00000002 */
+#define SPI_IER_TXPIE               SPI_IER_TXPIE_Msk                          /*!<TXP interrupt enable            */
+#define SPI_IER_DXPIE_Pos           (2U)
+#define SPI_IER_DXPIE_Msk           (0x1UL << SPI_IER_DXPIE_Pos)               /*!< 0x00000004 */
+#define SPI_IER_DXPIE               SPI_IER_DXPIE_Msk                          /*!<DXP interrupt enable            */
+#define SPI_IER_EOTIE_Pos           (3U)
+#define SPI_IER_EOTIE_Msk           (0x1UL << SPI_IER_EOTIE_Pos)               /*!< 0x00000008 */
+#define SPI_IER_EOTIE               SPI_IER_EOTIE_Msk                          /*!<EOT/SUSP/TXC interrupt enable   */
+#define SPI_IER_TXTFIE_Pos          (4U)
+#define SPI_IER_TXTFIE_Msk          (0x1UL << SPI_IER_TXTFIE_Pos)              /*!< 0x00000010 */
+#define SPI_IER_TXTFIE              SPI_IER_TXTFIE_Msk                         /*!<TXTF interrupt enable           */
+#define SPI_IER_UDRIE_Pos           (5U)
+#define SPI_IER_UDRIE_Msk           (0x1UL << SPI_IER_UDRIE_Pos)               /*!< 0x00000020 */
+#define SPI_IER_UDRIE               SPI_IER_UDRIE_Msk                          /*!<UDR interrupt enable            */
+#define SPI_IER_OVRIE_Pos           (6U)
+#define SPI_IER_OVRIE_Msk           (0x1UL << SPI_IER_OVRIE_Pos)               /*!< 0x00000040 */
+#define SPI_IER_OVRIE               SPI_IER_OVRIE_Msk                          /*!<OVR interrupt enable            */
+#define SPI_IER_CRCEIE_Pos          (7U)
+#define SPI_IER_CRCEIE_Msk          (0x1UL << SPI_IER_CRCEIE_Pos)               /*!< 0x00000080 */
+#define SPI_IER_CRCEIE              SPI_IER_CRCEIE_Msk                          /*!<CRCE interrupt enable           */
+#define SPI_IER_TIFREIE_Pos         (8U)
+#define SPI_IER_TIFREIE_Msk         (0x1UL << SPI_IER_TIFREIE_Pos)             /*!< 0x00000100 */
+#define SPI_IER_TIFREIE             SPI_IER_TIFREIE_Msk                        /*!<TI Frame Error interrupt enable */
+#define SPI_IER_MODFIE_Pos          (9U)
+#define SPI_IER_MODFIE_Msk          (0x1UL << SPI_IER_MODFIE_Pos)              /*!< 0x00000200 */
+#define SPI_IER_MODFIE              SPI_IER_MODFIE_Msk                         /*!<MODF interrupt enable           */
+#define SPI_IER_TSERFIE_Pos         (10U)
+#define SPI_IER_TSERFIE_Msk         (0x1UL << SPI_IER_TSERFIE_Pos)              /*!< 0x00000400 */
+#define SPI_IER_TSERFIE             SPI_IER_TSERFIE_Msk                        /*!<TSERF interrupt enable          */
+
+/*******************  Bit definition for SPI_SR register  ********************/
+#define SPI_SR_RXP_Pos              (0U)
+#define SPI_SR_RXP_Msk              (0x1UL << SPI_SR_RXP_Pos)                  /*!< 0x00000001 */
+#define SPI_SR_RXP                  SPI_SR_RXP_Msk                             /*!<Rx-Packet available             */
+#define SPI_SR_TXP_Pos              (1U)
+#define SPI_SR_TXP_Msk              (0x1UL << SPI_SR_TXP_Pos)                  /*!< 0x00000002 */
+#define SPI_SR_TXP                  SPI_SR_TXP_Msk                             /*!<Tx-Packet space available       */
+#define SPI_SR_DXP_Pos              (2U)
+#define SPI_SR_DXP_Msk              (0x1UL << SPI_SR_DXP_Pos)                  /*!< 0x00000004 */
+#define SPI_SR_DXP                  SPI_SR_DXP_Msk                             /*!<Duplex Packet available         */
+#define SPI_SR_EOT_Pos              (3U)
+#define SPI_SR_EOT_Msk              (0x1UL << SPI_SR_EOT_Pos)                  /*!< 0x00000008 */
+#define SPI_SR_EOT                  SPI_SR_EOT_Msk                             /*!<Duplex Packet available         */
+#define SPI_SR_TXTF_Pos             (4U)
+#define SPI_SR_TXTF_Msk             (0x1UL << SPI_SR_TXTF_Pos)                 /*!< 0x00000010 */
+#define SPI_SR_TXTF                 SPI_SR_TXTF_Msk                            /*!<Transmission Transfer Filled    */
+#define SPI_SR_UDR_Pos              (5U)
+#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                  /*!< 0x00000020 */
+#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<UDR at Slave transmission       */
+#define SPI_SR_OVR_Pos              (6U)
+#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                  /*!< 0x00000040 */
+#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Rx-Packet available             */
+#define SPI_SR_CRCE_Pos             (7U)
+#define SPI_SR_CRCE_Msk             (0x1UL << SPI_SR_CRCE_Pos)                 /*!< 0x00000080 */
+#define SPI_SR_CRCE                 SPI_SR_CRCE_Msk                            /*!<CRC Error Detected              */
+#define SPI_SR_TIFRE_Pos            (8U)
+#define SPI_SR_TIFRE_Msk            (0x1UL << SPI_SR_TIFRE_Pos)                /*!< 0x00000100 */
+#define SPI_SR_TIFRE                SPI_SR_TIFRE_Msk                           /*!<TI frame format error Detected  */
+#define SPI_SR_MODF_Pos             (9U)
+#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                 /*!< 0x00000200 */
+#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode Fault Detected             */
+#define SPI_SR_TSERF_Pos            (10U)
+#define SPI_SR_TSERF_Msk            (0x1UL << SPI_SR_TSERF_Pos)                /*!< 0x00000400 */
+#define SPI_SR_TSERF                SPI_SR_TSERF_Msk                           /*!<Number of SPI data to be transacted reloaded     */
+#define SPI_SR_SUSP_Pos             (11U)
+#define SPI_SR_SUSP_Msk             (0x1UL << SPI_SR_SUSP_Pos)                 /*!< 0x00000800 */
+#define SPI_SR_SUSP                 SPI_SR_SUSP_Msk                            /*!<SUSP is set by hardware  */
+#define SPI_SR_TXC_Pos              (12U)
+#define SPI_SR_TXC_Msk              (0x1UL << SPI_SR_TXC_Pos)                  /*!< 0x00001000 */
+#define SPI_SR_TXC                  SPI_SR_TXC_Msk                             /*!<TxFIFO transmission complete */
+#define SPI_SR_RXPLVL_Pos           (13U)
+#define SPI_SR_RXPLVL_Msk           (0x3UL << SPI_SR_RXPLVL_Pos)               /*!< 0x00006000 */
+#define SPI_SR_RXPLVL               SPI_SR_RXPLVL_Msk                          /*!<RxFIFO Packing Level                             */
+#define SPI_SR_RXPLVL_0             (0x1UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00002000 */
+#define SPI_SR_RXPLVL_1             (0x2UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00004000 */
+#define SPI_SR_RXWNE_Pos            (15U)
+#define SPI_SR_RXWNE_Msk            (0x1UL << SPI_SR_RXWNE_Pos)                /*!< 0x00008000 */
+#define SPI_SR_RXWNE                SPI_SR_RXWNE_Msk                           /*!<Rx FIFO Word Not Empty                           */
+#define SPI_SR_CTSIZE_Pos           (16U)
+#define SPI_SR_CTSIZE_Msk           (0xFFFFUL << SPI_SR_CTSIZE_Pos)            /*!< 0xFFFF0000 */
+#define SPI_SR_CTSIZE               SPI_SR_CTSIZE_Msk                          /*!<Number of data frames remaining in TSIZE         */
+
+/*******************  Bit definition for SPI_IFCR register  ********************/
+#define SPI_IFCR_EOTC_Pos           (3U)
+#define SPI_IFCR_EOTC_Msk           (0x1UL << SPI_IFCR_EOTC_Pos)               /*!< 0x00000008 */
+#define SPI_IFCR_EOTC               SPI_IFCR_EOTC_Msk                          /*!<End Of Transfer flag clear              */
+#define SPI_IFCR_TXTFC_Pos          (4U)
+#define SPI_IFCR_TXTFC_Msk          (0x1UL << SPI_IFCR_TXTFC_Pos)              /*!< 0x00000010 */
+#define SPI_IFCR_TXTFC              SPI_IFCR_TXTFC_Msk                         /*!<Transmission Transfer Filled flag clear */
+#define SPI_IFCR_UDRC_Pos           (5U)
+#define SPI_IFCR_UDRC_Msk           (0x1UL << SPI_IFCR_UDRC_Pos)               /*!< 0x00000020 */
+#define SPI_IFCR_UDRC               SPI_IFCR_UDRC_Msk                          /*!<Underrun flag clear                     */
+#define SPI_IFCR_OVRC_Pos           (6U)
+#define SPI_IFCR_OVRC_Msk           (0x1UL << SPI_IFCR_OVRC_Pos)               /*!< 0x00000040 */
+#define SPI_IFCR_OVRC               SPI_IFCR_OVRC_Msk                          /*!<Overrun flag clear                      */
+#define SPI_IFCR_CRCEC_Pos          (7U)
+#define SPI_IFCR_CRCEC_Msk          (0x1UL << SPI_IFCR_CRCEC_Pos)              /*!< 0x00000080 */
+#define SPI_IFCR_CRCEC              SPI_IFCR_CRCEC_Msk                         /*!<CRC Error flag clear                    */
+#define SPI_IFCR_TIFREC_Pos         (8U)
+#define SPI_IFCR_TIFREC_Msk         (0x1UL << SPI_IFCR_TIFREC_Pos)             /*!< 0x00000100 */
+#define SPI_IFCR_TIFREC             SPI_IFCR_TIFREC_Msk                        /*!<TI frame format error flag clear        */
+#define SPI_IFCR_MODFC_Pos          (9U)
+#define SPI_IFCR_MODFC_Msk          (0x1UL << SPI_IFCR_MODFC_Pos)              /*!< 0x00000200 */
+#define SPI_IFCR_MODFC              SPI_IFCR_MODFC_Msk                         /*!<Mode Fault flag clear                   */
+#define SPI_IFCR_TSERFC_Pos         (10U)
+#define SPI_IFCR_TSERFC_Msk         (0x1UL << SPI_IFCR_TSERFC_Pos)             /*!< 0x00000400 */
+#define SPI_IFCR_TSERFC             SPI_IFCR_TSERFC_Msk                        /*!<TSERFC flag clear                       */
+#define SPI_IFCR_SUSPC_Pos          (11U)
+#define SPI_IFCR_SUSPC_Msk          (0x1UL << SPI_IFCR_SUSPC_Pos)              /*!< 0x00000800 */
+#define SPI_IFCR_SUSPC              SPI_IFCR_SUSPC_Msk                         /*!<SUSPend flag clear                      */
+
+/*******************  Bit definition for SPI_TXDR register  ********************/
+#define SPI_TXDR_TXDR_Pos           (0U)
+#define SPI_TXDR_TXDR_Msk           (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos)        /*!< 0xFFFFFFFF */
+#define SPI_TXDR_TXDR               SPI_TXDR_TXDR_Msk                          /* Transmit Data Register */
+
+/*******************  Bit definition for SPI_RXDR register  ********************/
+#define SPI_RXDR_RXDR_Pos           (0U)
+#define SPI_RXDR_RXDR_Msk           (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos)        /*!< 0xFFFFFFFF */
+#define SPI_RXDR_RXDR               SPI_RXDR_RXDR_Msk                          /* Receive Data Register  */
+
+/*******************  Bit definition for SPI_CRCPOLY register  ********************/
+#define SPI_CRCPOLY_CRCPOLY_Pos     (0U)
+#define SPI_CRCPOLY_CRCPOLY_Msk     (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos)  /*!< 0xFFFFFFFF */
+#define SPI_CRCPOLY_CRCPOLY         SPI_CRCPOLY_CRCPOLY_Msk                    /* CRC Polynomial register  */
+
+/*******************  Bit definition for SPI_TXCRC register  ********************/
+#define SPI_TXCRC_TXCRC_Pos         (0U)
+#define SPI_TXCRC_TXCRC_Msk         (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos)      /*!< 0xFFFFFFFF */
+#define SPI_TXCRC_TXCRC             SPI_TXCRC_TXCRC_Msk                        /* CRCRegister for transmitter */
+
+/*******************  Bit definition for SPI_RXCRC register  ********************/
+#define SPI_RXCRC_RXCRC_Pos         (0U)
+#define SPI_RXCRC_RXCRC_Msk         (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos)      /*!< 0xFFFFFFFF */
+#define SPI_RXCRC_RXCRC             SPI_RXCRC_RXCRC_Msk                        /* CRCRegister for receiver */
+
+/*******************  Bit definition for SPI_UDRDR register  ********************/
+#define SPI_UDRDR_UDRDR_Pos         (0U)
+#define SPI_UDRDR_UDRDR_Msk         (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos)      /*!< 0xFFFFFFFF */
+#define SPI_UDRDR_UDRDR             SPI_UDRDR_UDRDR_Msk                        /* Data at slave underrun condition */
+
+/******************  Bit definition for SPI_I2SCFGR register  *****************/
+#define SPI_I2SCFGR_I2SMOD_Pos      (0U)
+#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)          /*!< 0x00000001 */
+#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
+#define SPI_I2SCFGR_I2SCFG_Pos      (1U)
+#define SPI_I2SCFGR_I2SCFG_Msk      (0x7UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x0000000E */
+#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[2:0] I2S configuration mode                */
+#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000002 */
+#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000004 */
+#define SPI_I2SCFGR_I2SCFG_2        (0x4UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000008 */
+#define SPI_I2SCFGR_I2SSTD_Pos      (4U)
+#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] I2S standard selection                */
+#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */
+#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)
+#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)         /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                         */
+#define SPI_I2SCFGR_DATLEN_Pos      (8U)
+#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000300 */
+#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] Data length to be transferred         */
+#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000100 */
+#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000200 */
+#define SPI_I2SCFGR_CHLEN_Pos       (10U)
+#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)           /*!< 0x00000400 */
+#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
+#define SPI_I2SCFGR_CKPOL_Pos       (11U)
+#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)           /*!< 0x00000800 */
+#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<Steady state clock polarity                       */
+#define SPI_I2SCFGR_FIXCH_Pos       (12U)
+#define SPI_I2SCFGR_FIXCH_Msk       (0x1UL << SPI_I2SCFGR_FIXCH_Pos)           /*!< 0x00001000 */
+#define SPI_I2SCFGR_FIXCH           SPI_I2SCFGR_FIXCH_Msk                      /*!<Fixed channel length in SLAVE                     */
+#define SPI_I2SCFGR_WSINV_Pos       (13U)
+#define SPI_I2SCFGR_WSINV_Msk       (0x1UL << SPI_I2SCFGR_WSINV_Pos)           /*!< 0x00002000 */
+#define SPI_I2SCFGR_WSINV           SPI_I2SCFGR_WSINV_Msk                      /*!<Word select inversion                             */
+#define SPI_I2SCFGR_DATFMT_Pos      (14U)
+#define SPI_I2SCFGR_DATFMT_Msk      (0x1UL << SPI_I2SCFGR_DATFMT_Pos)          /*!< 0x00004000 */
+#define SPI_I2SCFGR_DATFMT          SPI_I2SCFGR_DATFMT_Msk                     /*!<Data format                                       */
+#define SPI_I2SCFGR_I2SDIV_Pos      (16U)
+#define SPI_I2SCFGR_I2SDIV_Msk      (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos)         /*!< 0x00FF0000 */
+#define SPI_I2SCFGR_I2SDIV          SPI_I2SCFGR_I2SDIV_Msk                     /*!<I2S Linear prescaler */
+#define SPI_I2SCFGR_ODD_Pos         (24U)
+#define SPI_I2SCFGR_ODD_Msk         (0x1UL << SPI_I2SCFGR_ODD_Pos)             /*!< 0x01000000 */
+#define SPI_I2SCFGR_ODD             SPI_I2SCFGR_ODD_Msk                        /*!<Odd factor for the prescaler */
+#define SPI_I2SCFGR_MCKOE_Pos       (25U)
+#define SPI_I2SCFGR_MCKOE_Msk       (0x1UL << SPI_I2SCFGR_MCKOE_Pos)           /*!< 0x02000000 */
+#define SPI_I2SCFGR_MCKOE           SPI_I2SCFGR_MCKOE_Msk                      /*!<Master Clock Output Enable */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    QUADSPI                                 */
+/*                                                                            */
+/******************************************************************************/
+/*****************  Bit definition for QUADSPI_CR register  *******************/
+#define QUADSPI_CR_EN_Pos                (0U)
+#define QUADSPI_CR_EN_Msk                (0x1UL << QUADSPI_CR_EN_Pos)          /*!< 0x00000001 */
+#define QUADSPI_CR_EN                    QUADSPI_CR_EN_Msk                     /*!< Enable */
+#define QUADSPI_CR_ABORT_Pos             (1U)
+#define QUADSPI_CR_ABORT_Msk             (0x1UL << QUADSPI_CR_ABORT_Pos)       /*!< 0x00000002 */
+#define QUADSPI_CR_ABORT                 QUADSPI_CR_ABORT_Msk                  /*!< Abort request */
+#define QUADSPI_CR_DMAEN_Pos             (2U)
+#define QUADSPI_CR_DMAEN_Msk             (0x1UL << QUADSPI_CR_DMAEN_Pos)       /*!< 0x00000004 */
+#define QUADSPI_CR_DMAEN                 QUADSPI_CR_DMAEN_Msk                  /*!< DMA Enable */
+#define QUADSPI_CR_TCEN_Pos              (3U)
+#define QUADSPI_CR_TCEN_Msk              (0x1UL << QUADSPI_CR_TCEN_Pos)        /*!< 0x00000008 */
+#define QUADSPI_CR_TCEN                  QUADSPI_CR_TCEN_Msk                   /*!< Timeout Counter Enable */
+#define QUADSPI_CR_SSHIFT_Pos            (4U)
+#define QUADSPI_CR_SSHIFT_Msk            (0x1UL << QUADSPI_CR_SSHIFT_Pos)      /*!< 0x00000010 */
+#define QUADSPI_CR_SSHIFT                QUADSPI_CR_SSHIFT_Msk                 /*!< SSHIFT Sample Shift */
+#define QUADSPI_CR_DFM_Pos               (6U)
+#define QUADSPI_CR_DFM_Msk               (0x1UL << QUADSPI_CR_DFM_Pos)         /*!< 0x00000040 */
+#define QUADSPI_CR_DFM                   QUADSPI_CR_DFM_Msk                    /*!< Dual Flash Mode */
+#define QUADSPI_CR_FSEL_Pos              (7U)
+#define QUADSPI_CR_FSEL_Msk              (0x1UL << QUADSPI_CR_FSEL_Pos)        /*!< 0x00000080 */
+#define QUADSPI_CR_FSEL                  QUADSPI_CR_FSEL_Msk                   /*!< Flash Select */
+#define QUADSPI_CR_FTHRES_Pos            (8U)
+#define QUADSPI_CR_FTHRES_Msk            (0xFUL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000F00 */
+#define QUADSPI_CR_FTHRES                QUADSPI_CR_FTHRES_Msk                 /*!< FTHRES[3:0] FIFO Level */
+#define QUADSPI_CR_FTHRES_0              (0x1UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000100 */
+#define QUADSPI_CR_FTHRES_1              (0x2UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000200 */
+#define QUADSPI_CR_FTHRES_2              (0x4UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000400 */
+#define QUADSPI_CR_FTHRES_3              (0x8UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000800 */
+#define QUADSPI_CR_TEIE_Pos              (16U)
+#define QUADSPI_CR_TEIE_Msk              (0x1UL << QUADSPI_CR_TEIE_Pos)        /*!< 0x00010000 */
+#define QUADSPI_CR_TEIE                  QUADSPI_CR_TEIE_Msk                   /*!< Transfer Error Interrupt Enable */
+#define QUADSPI_CR_TCIE_Pos              (17U)
+#define QUADSPI_CR_TCIE_Msk              (0x1UL << QUADSPI_CR_TCIE_Pos)        /*!< 0x00020000 */
+#define QUADSPI_CR_TCIE                  QUADSPI_CR_TCIE_Msk                   /*!< Transfer Complete Interrupt Enable */
+#define QUADSPI_CR_FTIE_Pos              (18U)
+#define QUADSPI_CR_FTIE_Msk              (0x1UL << QUADSPI_CR_FTIE_Pos)        /*!< 0x00040000 */
+#define QUADSPI_CR_FTIE                  QUADSPI_CR_FTIE_Msk                   /*!< FIFO Threshold Interrupt Enable */
+#define QUADSPI_CR_SMIE_Pos              (19U)
+#define QUADSPI_CR_SMIE_Msk              (0x1UL << QUADSPI_CR_SMIE_Pos)        /*!< 0x00080000 */
+#define QUADSPI_CR_SMIE                  QUADSPI_CR_SMIE_Msk                   /*!< Status Match Interrupt Enable */
+#define QUADSPI_CR_TOIE_Pos              (20U)
+#define QUADSPI_CR_TOIE_Msk              (0x1UL << QUADSPI_CR_TOIE_Pos)        /*!< 0x00100000 */
+#define QUADSPI_CR_TOIE                  QUADSPI_CR_TOIE_Msk                   /*!< TimeOut Interrupt Enable */
+#define QUADSPI_CR_APMS_Pos              (22U)
+#define QUADSPI_CR_APMS_Msk              (0x1UL << QUADSPI_CR_APMS_Pos)        /*!< 0x00400000 */
+#define QUADSPI_CR_APMS                  QUADSPI_CR_APMS_Msk                   /*!< Bit 1 */
+#define QUADSPI_CR_PMM_Pos               (23U)
+#define QUADSPI_CR_PMM_Msk               (0x1UL << QUADSPI_CR_PMM_Pos)         /*!< 0x00800000 */
+#define QUADSPI_CR_PMM                   QUADSPI_CR_PMM_Msk                    /*!< Polling Match Mode */
+#define QUADSPI_CR_PRESCALER_Pos         (24U)
+#define QUADSPI_CR_PRESCALER_Msk         (0xFFUL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0xFF000000 */
+#define QUADSPI_CR_PRESCALER             QUADSPI_CR_PRESCALER_Msk              /*!< PRESCALER[7:0] Clock prescaler */
+#define QUADSPI_CR_PRESCALER_0           (0x01UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x01000000 */
+#define QUADSPI_CR_PRESCALER_1           (0x02UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x02000000 */
+#define QUADSPI_CR_PRESCALER_2           (0x04UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x04000000 */
+#define QUADSPI_CR_PRESCALER_3           (0x08UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x08000000 */
+#define QUADSPI_CR_PRESCALER_4           (0x10UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x10000000 */
+#define QUADSPI_CR_PRESCALER_5           (0x20UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x20000000 */
+#define QUADSPI_CR_PRESCALER_6           (0x40UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x40000000 */
+#define QUADSPI_CR_PRESCALER_7           (0x80UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x80000000 */
+
+/*****************  Bit definition for QUADSPI_DCR register  ******************/
+#define QUADSPI_DCR_CKMODE_Pos           (0U)
+#define QUADSPI_DCR_CKMODE_Msk           (0x1UL << QUADSPI_DCR_CKMODE_Pos)     /*!< 0x00000001 */
+#define QUADSPI_DCR_CKMODE               QUADSPI_DCR_CKMODE_Msk                /*!< Mode 0 / Mode 3 */
+#define QUADSPI_DCR_CSHT_Pos             (8U)
+#define QUADSPI_DCR_CSHT_Msk             (0x7UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000700 */
+#define QUADSPI_DCR_CSHT                 QUADSPI_DCR_CSHT_Msk                  /*!< CSHT[2:0]: ChipSelect High Time */
+#define QUADSPI_DCR_CSHT_0               (0x1UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000100 */
+#define QUADSPI_DCR_CSHT_1               (0x2UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000200 */
+#define QUADSPI_DCR_CSHT_2               (0x4UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000400 */
+#define QUADSPI_DCR_FSIZE_Pos            (16U)
+#define QUADSPI_DCR_FSIZE_Msk            (0x1FUL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x001F0000 */
+#define QUADSPI_DCR_FSIZE                QUADSPI_DCR_FSIZE_Msk                 /*!< FSIZE[4:0]: Flash Size */
+#define QUADSPI_DCR_FSIZE_0              (0x01UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00010000 */
+#define QUADSPI_DCR_FSIZE_1              (0x02UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00020000 */
+#define QUADSPI_DCR_FSIZE_2              (0x04UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00040000 */
+#define QUADSPI_DCR_FSIZE_3              (0x08UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00080000 */
+#define QUADSPI_DCR_FSIZE_4              (0x10UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00100000 */
+
+/******************  Bit definition for QUADSPI_SR register  *******************/
+#define QUADSPI_SR_TEF_Pos               (0U)
+#define QUADSPI_SR_TEF_Msk               (0x1UL << QUADSPI_SR_TEF_Pos)         /*!< 0x00000001 */
+#define QUADSPI_SR_TEF                   QUADSPI_SR_TEF_Msk                    /*!< Transfer Error Flag */
+#define QUADSPI_SR_TCF_Pos               (1U)
+#define QUADSPI_SR_TCF_Msk               (0x1UL << QUADSPI_SR_TCF_Pos)         /*!< 0x00000002 */
+#define QUADSPI_SR_TCF                   QUADSPI_SR_TCF_Msk                    /*!< Transfer Complete Flag */
+#define QUADSPI_SR_FTF_Pos               (2U)
+#define QUADSPI_SR_FTF_Msk               (0x1UL << QUADSPI_SR_FTF_Pos)         /*!< 0x00000004 */
+#define QUADSPI_SR_FTF                   QUADSPI_SR_FTF_Msk                    /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_SMF_Pos               (3U)
+#define QUADSPI_SR_SMF_Msk               (0x1UL << QUADSPI_SR_SMF_Pos)         /*!< 0x00000008 */
+#define QUADSPI_SR_SMF                   QUADSPI_SR_SMF_Msk                    /*!< Status Match Flag */
+#define QUADSPI_SR_TOF_Pos               (4U)
+#define QUADSPI_SR_TOF_Msk               (0x1UL << QUADSPI_SR_TOF_Pos)         /*!< 0x00000010 */
+#define QUADSPI_SR_TOF                   QUADSPI_SR_TOF_Msk                    /*!< Timeout Flag */
+#define QUADSPI_SR_BUSY_Pos              (5U)
+#define QUADSPI_SR_BUSY_Msk              (0x1UL << QUADSPI_SR_BUSY_Pos)        /*!< 0x00000020 */
+#define QUADSPI_SR_BUSY                  QUADSPI_SR_BUSY_Msk                   /*!< Busy */
+#define QUADSPI_SR_FLEVEL_Pos            (8U)
+#define QUADSPI_SR_FLEVEL_Msk            (0x3FUL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00003F00 */
+#define QUADSPI_SR_FLEVEL                QUADSPI_SR_FLEVEL_Msk                 /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_FLEVEL_0              (0x01UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000100 */
+#define QUADSPI_SR_FLEVEL_1              (0x02UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000200 */
+#define QUADSPI_SR_FLEVEL_2              (0x04UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000400 */
+#define QUADSPI_SR_FLEVEL_3              (0x08UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000800 */
+#define QUADSPI_SR_FLEVEL_4              (0x10UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00001000 */
+#define QUADSPI_SR_FLEVEL_5              (0x20UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00002000 */
+
+/******************  Bit definition for QUADSPI_FCR register  ******************/
+#define QUADSPI_FCR_CTEF_Pos             (0U)
+#define QUADSPI_FCR_CTEF_Msk             (0x1UL << QUADSPI_FCR_CTEF_Pos)       /*!< 0x00000001 */
+#define QUADSPI_FCR_CTEF                 QUADSPI_FCR_CTEF_Msk                  /*!< Clear Transfer Error Flag */
+#define QUADSPI_FCR_CTCF_Pos             (1U)
+#define QUADSPI_FCR_CTCF_Msk             (0x1UL << QUADSPI_FCR_CTCF_Pos)       /*!< 0x00000002 */
+#define QUADSPI_FCR_CTCF                 QUADSPI_FCR_CTCF_Msk                  /*!< Clear Transfer Complete Flag */
+#define QUADSPI_FCR_CSMF_Pos             (3U)
+#define QUADSPI_FCR_CSMF_Msk             (0x1UL << QUADSPI_FCR_CSMF_Pos)       /*!< 0x00000008 */
+#define QUADSPI_FCR_CSMF                 QUADSPI_FCR_CSMF_Msk                  /*!< Clear Status Match Flag */
+#define QUADSPI_FCR_CTOF_Pos             (4U)
+#define QUADSPI_FCR_CTOF_Msk             (0x1UL << QUADSPI_FCR_CTOF_Pos)       /*!< 0x00000010 */
+#define QUADSPI_FCR_CTOF                 QUADSPI_FCR_CTOF_Msk                  /*!< Clear Timeout Flag */
+
+/******************  Bit definition for QUADSPI_DLR register  ******************/
+#define QUADSPI_DLR_DL_Pos               (0U)
+#define QUADSPI_DLR_DL_Msk               (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)  /*!< 0xFFFFFFFF */
+#define QUADSPI_DLR_DL                   QUADSPI_DLR_DL_Msk                    /*!< DL[31:0]: Data Length */
+
+/******************  Bit definition for QUADSPI_CCR register  ******************/
+#define QUADSPI_CCR_INSTRUCTION_Pos      (0U)
+#define QUADSPI_CCR_INSTRUCTION_Msk      (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
+#define QUADSPI_CCR_INSTRUCTION          QUADSPI_CCR_INSTRUCTION_Msk             /*!< INSTRUCTION[7:0]: Instruction */
+#define QUADSPI_CCR_INSTRUCTION_0        (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */
+#define QUADSPI_CCR_INSTRUCTION_1        (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */
+#define QUADSPI_CCR_INSTRUCTION_2        (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */
+#define QUADSPI_CCR_INSTRUCTION_3        (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */
+#define QUADSPI_CCR_INSTRUCTION_4        (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */
+#define QUADSPI_CCR_INSTRUCTION_5        (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */
+#define QUADSPI_CCR_INSTRUCTION_6        (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */
+#define QUADSPI_CCR_INSTRUCTION_7        (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */
+#define QUADSPI_CCR_IMODE_Pos            (8U)
+#define QUADSPI_CCR_IMODE_Msk            (0x3UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000300 */
+#define QUADSPI_CCR_IMODE                QUADSPI_CCR_IMODE_Msk                   /*!< IMODE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_IMODE_0              (0x1UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000100 */
+#define QUADSPI_CCR_IMODE_1              (0x2UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000200 */
+#define QUADSPI_CCR_ADMODE_Pos           (10U)
+#define QUADSPI_CCR_ADMODE_Msk           (0x3UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000C00 */
+#define QUADSPI_CCR_ADMODE               QUADSPI_CCR_ADMODE_Msk                  /*!< ADMODE[1:0]: Address Mode */
+#define QUADSPI_CCR_ADMODE_0             (0x1UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000400 */
+#define QUADSPI_CCR_ADMODE_1             (0x2UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000800 */
+#define QUADSPI_CCR_ADSIZE_Pos           (12U)
+#define QUADSPI_CCR_ADSIZE_Msk           (0x3UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00003000 */
+#define QUADSPI_CCR_ADSIZE               QUADSPI_CCR_ADSIZE_Msk                  /*!< ADSIZE[1:0]: Address Size */
+#define QUADSPI_CCR_ADSIZE_0             (0x1UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00001000 */
+#define QUADSPI_CCR_ADSIZE_1             (0x2UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00002000 */
+#define QUADSPI_CCR_ABMODE_Pos           (14U)
+#define QUADSPI_CCR_ABMODE_Msk           (0x3UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x0000C000 */
+#define QUADSPI_CCR_ABMODE               QUADSPI_CCR_ABMODE_Msk                  /*!< ABMODE[1:0]: Alternate Bytes Mode */
+#define QUADSPI_CCR_ABMODE_0             (0x1UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00004000 */
+#define QUADSPI_CCR_ABMODE_1             (0x2UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00008000 */
+#define QUADSPI_CCR_ABSIZE_Pos           (16U)
+#define QUADSPI_CCR_ABSIZE_Msk           (0x3UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00030000 */
+#define QUADSPI_CCR_ABSIZE               QUADSPI_CCR_ABSIZE_Msk                  /*!< ABSIZE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_ABSIZE_0             (0x1UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00010000 */
+#define QUADSPI_CCR_ABSIZE_1             (0x2UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00020000 */
+#define QUADSPI_CCR_DCYC_Pos             (18U)
+#define QUADSPI_CCR_DCYC_Msk             (0x1FUL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x007C0000 */
+#define QUADSPI_CCR_DCYC                 QUADSPI_CCR_DCYC_Msk                    /*!< DCYC[4:0]: Dummy Cycles */
+#define QUADSPI_CCR_DCYC_0               (0x01UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00040000 */
+#define QUADSPI_CCR_DCYC_1               (0x02UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00080000 */
+#define QUADSPI_CCR_DCYC_2               (0x04UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00100000 */
+#define QUADSPI_CCR_DCYC_3               (0x08UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00200000 */
+#define QUADSPI_CCR_DCYC_4               (0x10UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00400000 */
+#define QUADSPI_CCR_DMODE_Pos            (24U)
+#define QUADSPI_CCR_DMODE_Msk            (0x3UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x03000000 */
+#define QUADSPI_CCR_DMODE                QUADSPI_CCR_DMODE_Msk                   /*!< DMODE[1:0]: Data Mode */
+#define QUADSPI_CCR_DMODE_0              (0x1UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x01000000 */
+#define QUADSPI_CCR_DMODE_1              (0x2UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x02000000 */
+#define QUADSPI_CCR_FMODE_Pos            (26U)
+#define QUADSPI_CCR_FMODE_Msk            (0x3UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x0C000000 */
+#define QUADSPI_CCR_FMODE                QUADSPI_CCR_FMODE_Msk                   /*!< FMODE[1:0]: Functional Mode */
+#define QUADSPI_CCR_FMODE_0              (0x1UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x04000000 */
+#define QUADSPI_CCR_FMODE_1              (0x2UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x08000000 */
+#define QUADSPI_CCR_SIOO_Pos             (28U)
+#define QUADSPI_CCR_SIOO_Msk             (0x1UL << QUADSPI_CCR_SIOO_Pos)         /*!< 0x10000000 */
+#define QUADSPI_CCR_SIOO                 QUADSPI_CCR_SIOO_Msk                    /*!< SIOO: Send Instruction Only Once Mode */
+#define QUADSPI_CCR_DHHC_Pos             (30U)
+#define QUADSPI_CCR_DHHC_Msk             (0x1UL << QUADSPI_CCR_DHHC_Pos)         /*!< 0x40000000 */
+#define QUADSPI_CCR_DHHC                 QUADSPI_CCR_DHHC_Msk                    /*!< DHHC: DDR hold half cycle */
+#define QUADSPI_CCR_DDRM_Pos             (31U)
+#define QUADSPI_CCR_DDRM_Msk             (0x1UL << QUADSPI_CCR_DDRM_Pos)         /*!< 0x80000000 */
+#define QUADSPI_CCR_DDRM                 QUADSPI_CCR_DDRM_Msk                    /*!< DDRM: Double Data Rate Mode */
+
+/******************  Bit definition for QUADSPI_AR register  *******************/
+#define QUADSPI_AR_ADDRESS_Pos           (0U)
+#define QUADSPI_AR_ADDRESS_Msk           (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_AR_ADDRESS               QUADSPI_AR_ADDRESS_Msk                /*!< ADDRESS[31:0]: Address */
+
+/******************  Bit definition for QUADSPI_ABR register  ******************/
+#define QUADSPI_ABR_ALTERNATE_Pos        (0U)
+#define QUADSPI_ABR_ALTERNATE_Msk        (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_ABR_ALTERNATE            QUADSPI_ABR_ALTERNATE_Msk             /*!< ALTERNATE[31:0]: Alternate Bytes */
+
+/******************  Bit definition for QUADSPI_DR register  *******************/
+#define QUADSPI_DR_DATA_Pos              (0U)
+#define QUADSPI_DR_DATA_Msk              (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_DR_DATA                  QUADSPI_DR_DATA_Msk                   /*!< DATA[31:0]: Data */
+
+/******************  Bit definition for QUADSPI_PSMKR register  ****************/
+#define QUADSPI_PSMKR_MASK_Pos           (0U)
+#define QUADSPI_PSMKR_MASK_Msk           (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_PSMKR_MASK               QUADSPI_PSMKR_MASK_Msk                /*!< MASK[31:0]: Status Mask */
+
+/******************  Bit definition for QUADSPI_PSMAR register  ****************/
+#define QUADSPI_PSMAR_MATCH_Pos          (0U)
+#define QUADSPI_PSMAR_MATCH_Msk          (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_PSMAR_MATCH              QUADSPI_PSMAR_MATCH_Msk               /*!< MATCH[31:0]: Status Match */
+
+/******************  Bit definition for QUADSPI_PIR register  *****************/
+#define QUADSPI_PIR_INTERVAL_Pos         (0U)
+#define QUADSPI_PIR_INTERVAL_Msk         (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
+#define QUADSPI_PIR_INTERVAL             QUADSPI_PIR_INTERVAL_Msk              /*!< INTERVAL[15:0]: Polling Interval */
+
+/******************  Bit definition for QUADSPI_LPTR register  *****************/
+#define QUADSPI_LPTR_TIMEOUT_Pos         (0U)
+#define QUADSPI_LPTR_TIMEOUT_Msk         (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
+#define QUADSPI_LPTR_TIMEOUT             QUADSPI_LPTR_TIMEOUT_Msk              /*!< TIMEOUT[15:0]: Timeout period */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 SYSCFG                                     */
+/*                                                                            */
+/******************************************************************************/
+
+/******************  Bit definition for SYSCFG_PMCR register  ******************/
+#define SYSCFG_PMCR_I2C1_FMP_Pos        (0U)
+#define SYSCFG_PMCR_I2C1_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C1_FMP_Pos)    /*!< 0x00000001 */
+#define SYSCFG_PMCR_I2C1_FMP            SYSCFG_PMCR_I2C1_FMP_Msk               /*!< I2C1 Fast mode plus */
+#define SYSCFG_PMCR_I2C2_FMP_Pos        (1U)
+#define SYSCFG_PMCR_I2C2_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C2_FMP_Pos)    /*!< 0x00000002 */
+#define SYSCFG_PMCR_I2C2_FMP            SYSCFG_PMCR_I2C2_FMP_Msk               /*!< I2C2 Fast mode plus */
+#define SYSCFG_PMCR_I2C3_FMP_Pos        (2U)
+#define SYSCFG_PMCR_I2C3_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C3_FMP_Pos)    /*!< 0x00000004 */
+#define SYSCFG_PMCR_I2C3_FMP            SYSCFG_PMCR_I2C3_FMP_Msk               /*!< I2C3 Fast mode plus */
+#define SYSCFG_PMCR_I2C4_FMP_Pos        (3U)
+#define SYSCFG_PMCR_I2C4_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C4_FMP_Pos)    /*!< 0x00000008 */
+#define SYSCFG_PMCR_I2C4_FMP            SYSCFG_PMCR_I2C4_FMP_Msk               /*!< I2C4 Fast mode plus */
+#define SYSCFG_PMCR_I2C_PB6_FMP_Pos     (4U)
+#define SYSCFG_PMCR_I2C_PB6_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB6_FMP_Pos) /*!< 0x00000010 */
+#define SYSCFG_PMCR_I2C_PB6_FMP         SYSCFG_PMCR_I2C_PB6_FMP_Msk            /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_PMCR_I2C_PB7_FMP_Pos     (5U)
+#define SYSCFG_PMCR_I2C_PB7_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB7_FMP_Pos) /*!< 0x00000020 */
+#define SYSCFG_PMCR_I2C_PB7_FMP         SYSCFG_PMCR_I2C_PB7_FMP_Msk            /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_PMCR_I2C_PB8_FMP_Pos     (6U)
+#define SYSCFG_PMCR_I2C_PB8_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB8_FMP_Pos) /*!< 0x00000040 */
+#define SYSCFG_PMCR_I2C_PB8_FMP         SYSCFG_PMCR_I2C_PB8_FMP_Msk            /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_PMCR_I2C_PB9_FMP_Pos     (7U)
+#define SYSCFG_PMCR_I2C_PB9_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB9_FMP_Pos) /*!< 0x00000080 */
+#define SYSCFG_PMCR_I2C_PB9_FMP         SYSCFG_PMCR_I2C_PB9_FMP_Msk            /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_PMCR_BOOSTEN_Pos         (8U)
+#define SYSCFG_PMCR_BOOSTEN_Msk         (0x1UL << SYSCFG_PMCR_BOOSTEN_Pos)     /*!< 0x00000100 */
+#define SYSCFG_PMCR_BOOSTEN             SYSCFG_PMCR_BOOSTEN_Msk                /*!< I/O analog switch voltage booster enable */
+
+#define SYSCFG_PMCR_BOOSTVDDSEL_Pos     (9U)
+#define SYSCFG_PMCR_BOOSTVDDSEL_Msk     (0x1UL << SYSCFG_PMCR_BOOSTVDDSEL_Pos) /*!< 0x00000200 */
+#define SYSCFG_PMCR_BOOSTVDDSEL         SYSCFG_PMCR_BOOSTVDDSEL_Msk            /*!< Analog switch supply source selection : VDD/VDDA */
+
+#define SYSCFG_PMCR_EPIS_SEL_Pos        (21U)
+#define SYSCFG_PMCR_EPIS_SEL_Msk        (0x7UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00E00000 */
+#define SYSCFG_PMCR_EPIS_SEL            SYSCFG_PMCR_EPIS_SEL_Msk               /*!< Ethernet PHY Interface Selection */
+#define SYSCFG_PMCR_EPIS_SEL_0          (0x1UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00200000 */
+#define SYSCFG_PMCR_EPIS_SEL_1          (0x2UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00400000 */
+#define SYSCFG_PMCR_EPIS_SEL_2          (0x4UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00800000 */
+#define SYSCFG_PMCR_PA0SO_Pos           (24U)
+#define SYSCFG_PMCR_PA0SO_Msk           (0x1UL << SYSCFG_PMCR_PA0SO_Pos)       /*!< 0x01000000 */
+#define SYSCFG_PMCR_PA0SO               SYSCFG_PMCR_PA0SO_Msk                  /*!< PA0 Switch Open */
+#define SYSCFG_PMCR_PA1SO_Pos           (25U)
+#define SYSCFG_PMCR_PA1SO_Msk           (0x1UL << SYSCFG_PMCR_PA1SO_Pos)       /*!< 0x02000000 */
+#define SYSCFG_PMCR_PA1SO               SYSCFG_PMCR_PA1SO_Msk                  /*!< PA1 Switch Open */
+#define SYSCFG_PMCR_PC2SO_Pos           (26U)
+#define SYSCFG_PMCR_PC2SO_Msk           (0x1UL << SYSCFG_PMCR_PC2SO_Pos)       /*!< 0x04000000 */
+#define SYSCFG_PMCR_PC2SO               SYSCFG_PMCR_PC2SO_Msk                  /*!< PC2 Switch Open */
+#define SYSCFG_PMCR_PC3SO_Pos           (27U)
+#define SYSCFG_PMCR_PC3SO_Msk           (0x1UL << SYSCFG_PMCR_PC3SO_Pos)       /*!< 0x08000000 */
+#define SYSCFG_PMCR_PC3SO               SYSCFG_PMCR_PC3SO_Msk                  /*!< PC3 Switch Open */
+
+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)
+#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)    /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)
+#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)    /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)
+#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)    /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)
+#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)    /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */
+/**
+  * @brief   EXTI0 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000)                 /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001)                 /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002)                 /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003)                 /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004)                 /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x00000005)                 /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x00000006)                 /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000007)                 /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI         ((uint32_t)0x00000008)                 /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x00000009)                 /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x0000000A)                 /*!<PK[0] pin */
+
+/**
+  * @brief   EXTI1 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000)                 /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010)                 /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020)                 /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030)                 /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040)                 /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x00000050)                 /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x00000060)                 /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000070)                 /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI         ((uint32_t)0x00000080)                 /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x00000090)                 /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x000000A0)                 /*!<PK[1] pin */
+/**
+  * @brief   EXTI2 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000)                 /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100)                 /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200)                 /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300)                 /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400)                 /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x00000500)                 /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x00000600)                 /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x00000700)                 /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI         ((uint32_t)0x00000800)                 /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x00000900)                 /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x00000A00)                 /*!<PK[2] pin */
+
+/**
+  * @brief   EXTI3 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000)                 /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000)                 /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000)                 /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000)                 /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000)                 /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x00005000)                 /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x00006000)                 /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x00007000)                 /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI         ((uint32_t)0x00008000)                 /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x00009000)                 /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0x0000A000)                 /*!<PK[3] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
+#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)
+#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)    /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)
+#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)    /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)
+#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)    /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)
+#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)    /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */
+/**
+  * @brief   EXTI4 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000)                 /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001)                 /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002)                 /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003)                 /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004)                 /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x00000005)                 /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x00000006)                 /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x00000007)                 /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI         ((uint32_t)0x00000008)                 /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x00000009)                 /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x0000000A)                 /*!<PK[4] pin */
+/**
+  * @brief   EXTI5 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000)                 /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010)                 /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020)                 /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030)                 /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040)                 /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x00000050)                 /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x00000060)                 /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x00000070)                 /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI         ((uint32_t)0x00000080)                 /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x00000090)                 /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x000000A0)                 /*!<PK[5] pin */
+/**
+  * @brief   EXTI6 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000)                 /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100)                 /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200)                 /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300)                 /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400)                 /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x00000500)                 /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x00000600)                 /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x00000700)                 /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI         ((uint32_t)0x00000800)                 /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x00000900)                 /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x00000A00)                 /*!<PK[6] pin */
+
+/**
+  * @brief   EXTI7 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000)                 /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000)                 /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000)                 /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000)                 /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000)                 /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x00005000)                 /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x00006000)                 /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x00007000)                 /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI         ((uint32_t)0x00008000)                 /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x00009000)                 /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0x0000A000)                 /*!<PK[7] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
+#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)
+#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)    /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)
+#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)    /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)
+#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)   /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)
+#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)   /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */
+
+/**
+  * @brief   EXTI8 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000)                 /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001)                 /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002)                 /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003)                 /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004)                 /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x00000005)                 /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x00000006)                 /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x00000007)                 /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI         ((uint32_t)0x00000008)                 /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x00000009)                 /*!<PJ[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PK         ((uint32_t)0x0000000A)                 /*!<PK[8] pin */
+
+/**
+  * @brief   EXTI9 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000)                 /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010)                 /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020)                 /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030)                 /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040)                 /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x00000050)                 /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x00000060)                 /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x00000070)                 /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI         ((uint32_t)0x00000080)                 /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x00000090)                 /*!<PJ[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PK         ((uint32_t)0x000000A0)                 /*!<PK[9] pin */
+
+/**
+  * @brief   EXTI10 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000)                 /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100)                 /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200)                 /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300)                 /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400)                 /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x00000500)                 /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x00000600)                 /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x00000700)                 /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI        ((uint32_t)0x00000800)                 /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x00000900)                 /*!<PJ[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PK        ((uint32_t)0x00000A00)                 /*!<PK[10] pin */
+
+/**
+  * @brief   EXTI11 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000)                 /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000)                 /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000)                 /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000)                 /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000)                 /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x00005000)                 /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x00006000)                 /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x00007000)                 /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI        ((uint32_t)0x00008000)                 /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x00009000)                 /*!<PJ[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PK        ((uint32_t)0x0000A000)                 /*!<PK[11] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
+#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)
+#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)   /*!< 0x0000000F */
+#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)
+#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)   /*!< 0x000000F0 */
+#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)
+#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)   /*!< 0x00000F00 */
+#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)
+#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)   /*!< 0x0000F000 */
+#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */
+/**
+  * @brief   EXTI12 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000)                 /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001)                 /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002)                 /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003)                 /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004)                 /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x00000005)                 /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x00000006)                 /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x00000007)                 /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI        ((uint32_t)0x00000008)                 /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x00000009)                 /*!<PJ[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PK        ((uint32_t)0x0000000A)                 /*!<PK[12] pin */
+/**
+  * @brief   EXTI13 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000)                 /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010)                 /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020)                 /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030)                 /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040)                 /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x00000050)                 /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x00000060)                 /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x00000070)                 /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI        ((uint32_t)0x00000080)                 /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x00000090)                 /*!<PJ[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PK        ((uint32_t)0x000000A0)                 /*!<PK[13] pin */
+/**
+  * @brief   EXTI14 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000)                 /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100)                 /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200)                 /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300)                 /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400)                 /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x00000500)                 /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x00000600)                 /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x00000700)                 /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI        ((uint32_t)0x00000800)                 /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x00000900)                 /*!<PJ[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PK        ((uint32_t)0x00000A00)                 /*!<PK[14] pin */
+/**
+  * @brief   EXTI15 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000)                 /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000)                 /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000)                 /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000)                 /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000)                 /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x00005000)                 /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x00006000)                 /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x00007000)                 /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI        ((uint32_t)0x00008000)                 /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x00009000)                 /*!<PJ[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PK        ((uint32_t)0x0000A000)                 /*!<PK[15] pin */
+
+/******************  Bit definition for SYSCFG_CFGR register  ******************/
+#define SYSCFG_CFGR_PVDL_Pos            (2U)
+#define SYSCFG_CFGR_PVDL_Msk            (0x1UL << SYSCFG_CFGR_PVDL_Pos)        /*!< 0x00000004 */
+#define SYSCFG_CFGR_PVDL                SYSCFG_CFGR_PVDL_Msk                   /*!<PVD lock enable bit */
+#define SYSCFG_CFGR_FLASHL_Pos          (3U)
+#define SYSCFG_CFGR_FLASHL_Msk          (0x1UL << SYSCFG_CFGR_FLASHL_Pos)      /*!< 0x00000008 */
+#define SYSCFG_CFGR_FLASHL              SYSCFG_CFGR_FLASHL_Msk                 /*!<FLASH double ECC error lock bit */
+#define SYSCFG_CFGR_CM7L_Pos            (6U)
+#define SYSCFG_CFGR_CM7L_Msk            (0x1UL << SYSCFG_CFGR_CM7L_Pos)        /*!< 0x00000040 */
+#define SYSCFG_CFGR_CM7L                SYSCFG_CFGR_CM7L_Msk                   /*!<Cortex-M7 LOCKUP (Hardfault) output enable bit */
+#define SYSCFG_CFGR_BKRAML_Pos          (7U)
+#define SYSCFG_CFGR_BKRAML_Msk          (0x1UL << SYSCFG_CFGR_BKRAML_Pos)      /*!< 0x00000080 */
+#define SYSCFG_CFGR_BKRAML              SYSCFG_CFGR_BKRAML_Msk                 /*!<Backup SRAM double ECC error lock bit */
+#define SYSCFG_CFGR_SRAM4L_Pos          (9U)
+#define SYSCFG_CFGR_SRAM4L_Msk          (0x1UL << SYSCFG_CFGR_SRAM4L_Pos)      /*!< 0x00000200 */
+#define SYSCFG_CFGR_SRAM4L              SYSCFG_CFGR_SRAM4L_Msk                 /*!<SRAM4 double ECC error lock bit */
+#define SYSCFG_CFGR_SRAM3L_Pos          (10U)
+#define SYSCFG_CFGR_SRAM3L_Msk          (0x1UL << SYSCFG_CFGR_SRAM3L_Pos)      /*!< 0x00000400 */
+#define SYSCFG_CFGR_SRAM3L              SYSCFG_CFGR_SRAM3L_Msk                 /*!<SRAM3 double ECC error lock bit */
+#define SYSCFG_CFGR_SRAM2L_Pos          (11U)
+#define SYSCFG_CFGR_SRAM2L_Msk          (0x1UL << SYSCFG_CFGR_SRAM2L_Pos)      /*!< 0x00000800 */
+#define SYSCFG_CFGR_SRAM2L              SYSCFG_CFGR_SRAM2L_Msk                 /*!<SRAM2 double ECC error lock bit */
+#define SYSCFG_CFGR_SRAM1L_Pos          (12U)
+#define SYSCFG_CFGR_SRAM1L_Msk          (0x1UL << SYSCFG_CFGR_SRAM1L_Pos)      /*!< 0x00001000 */
+#define SYSCFG_CFGR_SRAM1L              SYSCFG_CFGR_SRAM1L_Msk                 /*!<SRAM1 double ECC error lock bit */
+#define SYSCFG_CFGR_DTCML_Pos           (13U)
+#define SYSCFG_CFGR_DTCML_Msk           (0x1UL << SYSCFG_CFGR_DTCML_Pos)       /*!< 0x00002000 */
+#define SYSCFG_CFGR_DTCML               SYSCFG_CFGR_DTCML_Msk                  /*!<DTCM double ECC error lock bit */
+#define SYSCFG_CFGR_ITCML_Pos           (14U)
+#define SYSCFG_CFGR_ITCML_Msk           (0x1UL << SYSCFG_CFGR_ITCML_Pos)       /*!< 0x00004000 */
+#define SYSCFG_CFGR_ITCML               SYSCFG_CFGR_ITCML_Msk                  /*!<ITCM double ECC error lock bit */
+#define SYSCFG_CFGR_AXISRAML_Pos        (15U)
+#define SYSCFG_CFGR_AXISRAML_Msk        (0x1UL << SYSCFG_CFGR_AXISRAML_Pos)    /*!< 0x00008000 */
+#define SYSCFG_CFGR_AXISRAML            SYSCFG_CFGR_AXISRAML_Msk               /*!<AXISRAM double ECC error lock bit */
+
+/******************  Bit definition for SYSCFG_CCCSR register  ******************/
+#define SYSCFG_CCCSR_EN_Pos             (0U)
+#define SYSCFG_CCCSR_EN_Msk             (0x1UL << SYSCFG_CCCSR_EN_Pos)         /*!< 0x00000001 */
+#define SYSCFG_CCCSR_EN                 SYSCFG_CCCSR_EN_Msk                    /*!< I/O compensation cell enable */
+#define SYSCFG_CCCSR_CS_Pos             (1U)
+#define SYSCFG_CCCSR_CS_Msk             (0x1UL << SYSCFG_CCCSR_CS_Pos)         /*!< 0x00000002 */
+#define SYSCFG_CCCSR_CS                 SYSCFG_CCCSR_CS_Msk                    /*!< I/O compensation cell code selection */
+#define SYSCFG_CCCSR_READY_Pos          (8U)
+#define SYSCFG_CCCSR_READY_Msk          (0x1UL << SYSCFG_CCCSR_READY_Pos)      /*!< 0x00000100 */
+#define SYSCFG_CCCSR_READY              SYSCFG_CCCSR_READY_Msk                 /*!< I/O compensation cell ready flag */
+#define SYSCFG_CCCSR_HSLV_Pos           (16U)
+#define SYSCFG_CCCSR_HSLV_Msk           (0x1UL << SYSCFG_CCCSR_HSLV_Pos)       /*!< 0x00010000 */
+#define SYSCFG_CCCSR_HSLV               SYSCFG_CCCSR_HSLV_Msk                  /*!< High-speed at low-voltage */
+
+/******************  Bit definition for SYSCFG_CCVR register  *******************/
+#define SYSCFG_CCVR_NCV_Pos             (0U)
+#define SYSCFG_CCVR_NCV_Msk             (0xFUL << SYSCFG_CCVR_NCV_Pos)         /*!< 0x0000000F */
+#define SYSCFG_CCVR_NCV                 SYSCFG_CCVR_NCV_Msk                    /*!< NMOS compensation value */
+#define SYSCFG_CCVR_PCV_Pos             (4U)
+#define SYSCFG_CCVR_PCV_Msk             (0xFUL << SYSCFG_CCVR_PCV_Pos)         /*!< 0x000000F0 */
+#define SYSCFG_CCVR_PCV                 SYSCFG_CCVR_PCV_Msk                    /*!< PMOS compensation value */
+
+/******************  Bit definition for SYSCFG_CCCR register  *******************/
+#define SYSCFG_CCCR_NCC_Pos             (0U)
+#define SYSCFG_CCCR_NCC_Msk             (0xFUL << SYSCFG_CCCR_NCC_Pos)         /*!< 0x0000000F */
+#define SYSCFG_CCCR_NCC                 SYSCFG_CCCR_NCC_Msk                    /*!< NMOS compensation code */
+#define SYSCFG_CCCR_PCC_Pos             (4U)
+#define SYSCFG_CCCR_PCC_Msk             (0xFUL << SYSCFG_CCCR_PCC_Pos)         /*!< 0x000000F0 */
+#define SYSCFG_CCCR_PCC                 SYSCFG_CCCR_PCC_Msk                    /*!< PMOS compensation code */
+/******************  Bit definition for SYSCFG_PWRCR register  *******************/
+#define SYSCFG_PWRCR_ODEN_Pos           (0U)
+#define SYSCFG_PWRCR_ODEN_Msk           (0x1UL << SYSCFG_PWRCR_ODEN_Pos)         /*!< 0x00000001 */
+#define SYSCFG_PWRCR_ODEN               SYSCFG_PWRCR_ODEN_Msk                    /*!< PWR overdrive enable */
+
+/******************  Bit definition for SYSCFG_PKGR register  *******************/
+#define SYSCFG_PKGR_PKG_Pos             (0U)
+#define SYSCFG_PKGR_PKG_Msk             (0xFUL << SYSCFG_PKGR_PKG_Pos)         /*!< 0x0000000F */
+#define SYSCFG_PKGR_PKG                 SYSCFG_PKGR_PKG_Msk                    /*!< Package type */
+
+/******************  Bit definition for SYSCFG_UR0 register  *******************/
+#define SYSCFG_UR0_BKS_Pos              (0U)
+#define SYSCFG_UR0_BKS_Msk              (0x1UL << SYSCFG_UR0_BKS_Pos)          /*!< 0x00000001 */
+#define SYSCFG_UR0_BKS                  SYSCFG_UR0_BKS_Msk                     /*!< Bank Swap */
+#define SYSCFG_UR0_RDP_Pos              (16U)
+#define SYSCFG_UR0_RDP_Msk              (0xFFUL << SYSCFG_UR0_RDP_Pos)         /*!< 0x00FF0000 */
+#define SYSCFG_UR0_RDP                  SYSCFG_UR0_RDP_Msk                     /*!< Readout protection */
+
+/******************  Bit definition for SYSCFG_UR2 register  *******************/
+#define SYSCFG_UR2_BORH_Pos             (0U)
+#define SYSCFG_UR2_BORH_Msk             (0x3UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000003 */
+#define SYSCFG_UR2_BORH                 SYSCFG_UR2_BORH_Msk                    /*!< Brown Out Reset High level */
+#define SYSCFG_UR2_BORH_0               (0x1UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000001 */
+#define SYSCFG_UR2_BORH_1               (0x2UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000002 */
+#define SYSCFG_UR2_BOOT_ADD0_Pos        (16U)
+#define SYSCFG_UR2_BOOT_ADD0_Msk        (0xFFFFUL << SYSCFG_UR2_BOOT_ADD0_Pos) /*!< 0xFFFF0000 */
+#define SYSCFG_UR2_BOOT_ADD0            SYSCFG_UR2_BOOT_ADD0_Msk               /*!< Core Boot Address 0 */
+/******************  Bit definition for SYSCFG_UR3 register  *******************/
+#define SYSCFG_UR3_BOOT_ADD1_Pos        (0U)
+#define SYSCFG_UR3_BOOT_ADD1_Msk        (0xFFFFUL << SYSCFG_UR3_BOOT_ADD1_Pos) /*!< 0x0000FFFF */
+#define SYSCFG_UR3_BOOT_ADD1            SYSCFG_UR3_BOOT_ADD1_Msk               /*!< Core Boot Address 1 */
+
+  /******************  Bit definition for SYSCFG_UR4 register  *******************/
+
+#define SYSCFG_UR4_MEPAD_BANK1_Pos      (16U)
+#define SYSCFG_UR4_MEPAD_BANK1_Msk      (0x1UL << SYSCFG_UR4_MEPAD_BANK1_Pos)  /*!< 0x00010000 */
+#define SYSCFG_UR4_MEPAD_BANK1          SYSCFG_UR4_MEPAD_BANK1_Msk             /*!< Mass Erase Protected Area Disabled for bank 1 */
+
+/******************  Bit definition for SYSCFG_UR5 register  *******************/
+#define SYSCFG_UR5_MESAD_BANK1_Pos      (0U)
+#define SYSCFG_UR5_MESAD_BANK1_Msk      (0x1UL << SYSCFG_UR5_MESAD_BANK1_Pos)  /*!< 0x00000001 */
+#define SYSCFG_UR5_MESAD_BANK1          SYSCFG_UR5_MESAD_BANK1_Msk             /*!< Mass erase secured area disabled for bank 1 */
+#define SYSCFG_UR5_WRPN_BANK1_Pos       (16U)
+#define SYSCFG_UR5_WRPN_BANK1_Msk       (0xFFUL << SYSCFG_UR5_WRPN_BANK1_Pos)  /*!< 0x00FF0000 */
+#define SYSCFG_UR5_WRPN_BANK1           SYSCFG_UR5_WRPN_BANK1_Msk              /*!< Write protection for flash bank 1 */
+
+/******************  Bit definition for SYSCFG_UR6 register  *******************/
+#define SYSCFG_UR6_PABEG_BANK1_Pos      (0U)
+#define SYSCFG_UR6_PABEG_BANK1_Msk      (0xFFFUL << SYSCFG_UR6_PABEG_BANK1_Pos) /*!< 0x00000FFF */
+#define SYSCFG_UR6_PABEG_BANK1          SYSCFG_UR6_PABEG_BANK1_Msk             /*!< Protected area start address for bank 1 */
+#define SYSCFG_UR6_PAEND_BANK1_Pos      (16U)
+#define SYSCFG_UR6_PAEND_BANK1_Msk      (0xFFFUL << SYSCFG_UR6_PAEND_BANK1_Pos) /*!< 0x0FFF0000 */
+#define SYSCFG_UR6_PAEND_BANK1          SYSCFG_UR6_PAEND_BANK1_Msk             /*!< Protected area end address for bank 1 */
+
+/******************  Bit definition for SYSCFG_UR7 register  *******************/
+#define SYSCFG_UR7_SABEG_BANK1_Pos      (0U)
+#define SYSCFG_UR7_SABEG_BANK1_Msk      (0xFFFUL << SYSCFG_UR7_SABEG_BANK1_Pos) /*!< 0x00000FFF */
+#define SYSCFG_UR7_SABEG_BANK1          SYSCFG_UR7_SABEG_BANK1_Msk             /*!< Secured area start address for bank 1 */
+#define SYSCFG_UR7_SAEND_BANK1_Pos      (16U)
+#define SYSCFG_UR7_SAEND_BANK1_Msk      (0xFFFUL << SYSCFG_UR7_SAEND_BANK1_Pos) /*!< 0x0FFF0000 */
+#define SYSCFG_UR7_SAEND_BANK1          SYSCFG_UR7_SAEND_BANK1_Msk             /*!< Secured area end address for bank 1 */
+
+/******************  Bit definition for SYSCFG_UR8 register  *******************/
+#define SYSCFG_UR8_MEPAD_BANK2_Pos      (0U)
+#define SYSCFG_UR8_MEPAD_BANK2_Msk      (0x1UL << SYSCFG_UR8_MEPAD_BANK2_Pos)  /*!< 0x00000001 */
+#define SYSCFG_UR8_MEPAD_BANK2          SYSCFG_UR8_MEPAD_BANK2_Msk             /*!< Mass erase Protected area disabled for bank 2 */
+#define SYSCFG_UR8_MESAD_BANK2_Pos      (16U)
+#define SYSCFG_UR8_MESAD_BANK2_Msk      (0x1UL << SYSCFG_UR8_MESAD_BANK2_Pos)  /*!< 0x00010000 */
+#define SYSCFG_UR8_MESAD_BANK2          SYSCFG_UR8_MESAD_BANK2_Msk             /*!< Mass Erase Secured Area Disabled for bank 2 */
+
+/******************  Bit definition for SYSCFG_UR9 register  *******************/
+#define SYSCFG_UR9_WRPN_BANK2_Pos       (0U)
+#define SYSCFG_UR9_WRPN_BANK2_Msk       (0xFFUL << SYSCFG_UR9_WRPN_BANK2_Pos)  /*!< 0x000000FF */
+#define SYSCFG_UR9_WRPN_BANK2           SYSCFG_UR9_WRPN_BANK2_Msk              /*!< Write protection for flash bank 2 */
+#define SYSCFG_UR9_PABEG_BANK2_Pos      (16U)
+#define SYSCFG_UR9_PABEG_BANK2_Msk      (0xFFFUL << SYSCFG_UR9_PABEG_BANK2_Pos) /*!< 0x0FFF0000 */
+#define SYSCFG_UR9_PABEG_BANK2          SYSCFG_UR9_PABEG_BANK2_Msk             /*!< Protected area start address for bank 2 */
+
+/******************  Bit definition for SYSCFG_UR10 register  *******************/
+#define SYSCFG_UR10_PAEND_BANK2_Pos     (0U)
+#define SYSCFG_UR10_PAEND_BANK2_Msk     (0xFFFUL << SYSCFG_UR10_PAEND_BANK2_Pos) /*!< 0x00000FFF */
+#define SYSCFG_UR10_PAEND_BANK2         SYSCFG_UR10_PAEND_BANK2_Msk            /*!< Protected area end address for bank 2 */
+#define SYSCFG_UR10_SABEG_BANK2_Pos     (16U)
+#define SYSCFG_UR10_SABEG_BANK2_Msk     (0xFFFUL << SYSCFG_UR10_SABEG_BANK2_Pos) /*!< 0x0FFF0000 */
+#define SYSCFG_UR10_SABEG_BANK2         SYSCFG_UR10_SABEG_BANK2_Msk            /*!< Secured area start address for bank 2 */
+
+/******************  Bit definition for SYSCFG_UR11 register  *******************/
+#define SYSCFG_UR11_SAEND_BANK2_Pos     (0U)
+#define SYSCFG_UR11_SAEND_BANK2_Msk     (0xFFFUL << SYSCFG_UR11_SAEND_BANK2_Pos) /*!< 0x00000FFF */
+#define SYSCFG_UR11_SAEND_BANK2         SYSCFG_UR11_SAEND_BANK2_Msk            /*!< Secured area end address for bank 2 */
+#define SYSCFG_UR11_IWDG1M_Pos          (16U)
+#define SYSCFG_UR11_IWDG1M_Msk          (0x1UL << SYSCFG_UR11_IWDG1M_Pos)      /*!< 0x00010000 */
+#define SYSCFG_UR11_IWDG1M              SYSCFG_UR11_IWDG1M_Msk                 /*!< Independent Watchdog 1 mode (SW or HW) */
+
+/******************  Bit definition for SYSCFG_UR12 register  *******************/
+
+#define SYSCFG_UR12_SECURE_Pos          (16U)
+#define SYSCFG_UR12_SECURE_Msk          (0x1UL << SYSCFG_UR12_SECURE_Pos)      /*!< 0x00010000 */
+#define SYSCFG_UR12_SECURE              SYSCFG_UR12_SECURE_Msk                 /*!< Secure mode status */
+
+/******************  Bit definition for SYSCFG_UR13 register  *******************/
+#define SYSCFG_UR13_SDRS_Pos            (0U)
+#define SYSCFG_UR13_SDRS_Msk            (0x3UL << SYSCFG_UR13_SDRS_Pos)        /*!< 0x00000003 */
+#define SYSCFG_UR13_SDRS                SYSCFG_UR13_SDRS_Msk                   /*!< Secured DTCM RAM Size */
+#define SYSCFG_UR13_D1SBRST_Pos         (16U)
+#define SYSCFG_UR13_D1SBRST_Msk         (0x1UL << SYSCFG_UR13_D1SBRST_Pos)     /*!< 0x00010000 */
+#define SYSCFG_UR13_D1SBRST             SYSCFG_UR13_D1SBRST_Msk                /*!< D1 Standby reset */
+
+/******************  Bit definition for SYSCFG_UR14 register  *******************/
+#define SYSCFG_UR14_D1STPRST_Pos        (0U)
+#define SYSCFG_UR14_D1STPRST_Msk        (0x1UL << SYSCFG_UR14_D1STPRST_Pos)    /*!< 0x00000001 */
+#define SYSCFG_UR14_D1STPRST            SYSCFG_UR14_D1STPRST_Msk               /*!< D1 Stop Reset */
+
+/******************  Bit definition for SYSCFG_UR15 register  *******************/
+#define SYSCFG_UR15_FZIWDGSTB_Pos       (16U)
+#define SYSCFG_UR15_FZIWDGSTB_Msk       (0x1UL << SYSCFG_UR15_FZIWDGSTB_Pos)   /*!< 0x00010000 */
+#define SYSCFG_UR15_FZIWDGSTB           SYSCFG_UR15_FZIWDGSTB_Msk              /*!< Freeze independent watchdogs in Standby mode */
+
+/******************  Bit definition for SYSCFG_UR16 register  *******************/
+#define SYSCFG_UR16_FZIWDGSTP_Pos       (0U)
+#define SYSCFG_UR16_FZIWDGSTP_Msk       (0x1UL << SYSCFG_UR16_FZIWDGSTP_Pos)   /*!< 0x00000001 */
+#define SYSCFG_UR16_FZIWDGSTP           SYSCFG_UR16_FZIWDGSTP_Msk              /*!< Freeze independent watchdogs in Stop mode */
+#define SYSCFG_UR16_PKP_Pos             (16U)
+#define SYSCFG_UR16_PKP_Msk             (0x1UL << SYSCFG_UR16_PKP_Pos)         /*!< 0x00010000 */
+#define SYSCFG_UR16_PKP                 SYSCFG_UR16_PKP_Msk                    /*!< Private key programmed */
+
+/******************  Bit definition for SYSCFG_UR17 register  *******************/
+#define SYSCFG_UR17_IOHSLV_Pos          (0U)
+#define SYSCFG_UR17_IOHSLV_Msk          (0x1UL << SYSCFG_UR17_IOHSLV_Pos)      /*!< 0x00000001 */
+#define SYSCFG_UR17_IOHSLV              SYSCFG_UR17_IOHSLV_Msk                 /*!< I/O high speed / low voltage */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    TIM                                     */
+/*                                                                            */
+/******************************************************************************/
+#define TIM_BREAK_INPUT_SUPPORT             /*!<TIM Break input feature */
+
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define TIM_CR1_CEN_Pos           (0U)
+#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */
+#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos          (1U)
+#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */
+#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
+#define TIM_CR1_URS_Pos           (2U)
+#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */
+#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
+#define TIM_CR1_OPM_Pos           (3U)
+#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */
+#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos           (4U)
+#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */
+#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
+
+#define TIM_CR1_CMS_Pos           (5U)
+#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */
+#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
+#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos          (7U)
+#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */
+#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos           (8U)
+#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */
+#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
+#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
+
+#define TIM_CR1_UIFREMAP_Pos      (11U)
+#define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */
+#define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define TIM_CR2_CCPC_Pos          (0U)
+#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */
+#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos          (2U)
+#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */
+#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos          (3U)
+#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */
+#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos           (4U)
+#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000070 */
+#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
+#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
+#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos          (7U)
+#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */
+#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos          (8U)
+#define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */
+#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos         (9U)
+#define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */
+#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos          (10U)
+#define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */
+#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos         (11U)
+#define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */
+#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos          (12U)
+#define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */
+#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos         (13U)
+#define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */
+#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos          (14U)
+#define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */
+#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
+#define TIM_CR2_OIS5_Pos          (16U)
+#define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
+#define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */
+#define TIM_CR2_OIS6_Pos          (17U)
+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00020000 */
+#define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */
+
+#define TIM_CR2_MMS2_Pos          (20U)
+#define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */
+#define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00100000 */
+#define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00200000 */
+#define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00400000 */
+#define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00800000 */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define TIM_SMCR_SMS_Pos          (0U)
+#define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */
+#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000004 */
+#define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)               /*!< 0x00010000 */
+
+#define TIM_SMCR_TS_Pos           (4U)
+#define TIM_SMCR_TS_Msk           (0x30007UL << TIM_SMCR_TS_Pos)               /*!< 0x00300070 */
+#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[4:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0             (0x00001UL << TIM_SMCR_TS_Pos)                /*!< 0x00000010 */
+#define TIM_SMCR_TS_1             (0x00002UL << TIM_SMCR_TS_Pos)                /*!< 0x00000020 */
+#define TIM_SMCR_TS_2             (0x00004UL << TIM_SMCR_TS_Pos)                /*!< 0x00000040 */
+#define TIM_SMCR_TS_3             (0x10000UL << TIM_SMCR_TS_Pos)                /*!< 0x00100000 */
+#define TIM_SMCR_TS_4             (0x20000UL << TIM_SMCR_TS_Pos)                /*!< 0x00200000 */
+
+#define TIM_SMCR_MSM_Pos          (7U)
+#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */
+#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos          (8U)
+#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */
+#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos         (12U)
+#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */
+#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos          (14U)
+#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */
+#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos          (15U)
+#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */
+#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define TIM_DIER_UIE_Pos          (0U)
+#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */
+#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos        (1U)
+#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */
+#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos        (2U)
+#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */
+#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos        (3U)
+#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */
+#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos        (4U)
+#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */
+#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos        (5U)
+#define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */
+#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos          (6U)
+#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */
+#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos          (7U)
+#define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */
+#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos          (8U)
+#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */
+#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos        (9U)
+#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */
+#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos        (10U)
+#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */
+#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos        (11U)
+#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */
+#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos        (12U)
+#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */
+#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos        (13U)
+#define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */
+#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos          (14U)
+#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */
+#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define TIM_SR_UIF_Pos            (0U)
+#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */
+#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos          (1U)
+#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */
+#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos          (2U)
+#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */
+#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos          (3U)
+#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */
+#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos          (4U)
+#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */
+#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos          (5U)
+#define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */
+#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos            (6U)
+#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */
+#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos            (7U)
+#define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */
+#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
+#define TIM_SR_B2IF_Pos           (8U)
+#define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */
+#define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break2 interrupt Flag */
+#define TIM_SR_CC1OF_Pos          (9U)
+#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */
+#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos          (10U)
+#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */
+#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos          (11U)
+#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */
+#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos          (12U)
+#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */
+#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
+#define TIM_SR_CC5IF_Pos          (16U)
+#define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */
+#define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */
+#define TIM_SR_CC6IF_Pos          (17U)
+#define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */
+#define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */
+#define TIM_SR_SBIF_Pos           (13U)
+#define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */
+#define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!< System Break Flag */
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define TIM_EGR_UG_Pos            (0U)
+#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */
+#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos          (1U)
+#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */
+#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos          (2U)
+#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */
+#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos          (3U)
+#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */
+#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos          (4U)
+#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */
+#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos          (5U)
+#define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */
+#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos            (6U)
+#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */
+#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos            (7U)
+#define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */
+#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */
+#define TIM_EGR_B2G_Pos           (8U)
+#define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */
+#define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break Generation */
+
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define TIM_CCMR1_CC1S_Pos        (0U)
+#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos       (2U)
+#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos       (3U)
+#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos        (4U)
+#define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */
+#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000040 */
+#define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010000 */
+
+#define TIM_CCMR1_OC1CE_Pos       (7U)
+#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos        (8U)
+#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos       (10U)
+#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos       (11U)
+#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos        (12U)
+#define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */
+#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00004000 */
+#define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x01000000 */
+
+#define TIM_CCMR1_OC2CE_Pos       (15U)
+#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos      (2U)
+#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos        (4U)
+#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos      (10U)
+#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos        (12U)
+#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define TIM_CCMR2_CC3S_Pos        (0U)
+#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos       (2U)
+#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos       (3U)
+#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos        (4U)
+#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
+#define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010000 */
+
+#define TIM_CCMR2_OC3CE_Pos       (7U)
+#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos        (8U)
+#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos       (10U)
+#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos       (11U)
+#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos        (12U)
+#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
+#define TIM_CCMR2_OC4M_3          (0x100UL << TIM_CCMR2_OC4M_Pos)               /*!< 0x00100000 */
+
+#define TIM_CCMR2_OC4CE_Pos       (15U)
+#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos      (2U)
+#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos        (4U)
+#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos      (10U)
+#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos        (12U)
+#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define TIM_CCER_CC1E_Pos         (0U)
+#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */
+#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos         (1U)
+#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */
+#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos        (2U)
+#define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */
+#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos        (3U)
+#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */
+#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos         (4U)
+#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */
+#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos         (5U)
+#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */
+#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos        (6U)
+#define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */
+#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos        (7U)
+#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */
+#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos         (8U)
+#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */
+#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos         (9U)
+#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */
+#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos        (10U)
+#define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */
+#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos        (11U)
+#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */
+#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos         (12U)
+#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */
+#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos         (13U)
+#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */
+#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos        (15U)
+#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */
+#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
+#define TIM_CCER_CC5E_Pos         (16U)
+#define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */
+#define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */
+#define TIM_CCER_CC5P_Pos         (17U)
+#define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */
+#define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */
+#define TIM_CCER_CC6E_Pos         (20U)
+#define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */
+#define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */
+#define TIM_CCER_CC6P_Pos         (21U)
+#define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */
+#define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define TIM_CNT_CNT_Pos           (0U)
+#define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
+#define TIM_CNT_UIFCPY_Pos        (31U)
+#define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */
+#define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy */
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define TIM_PSC_PSC_Pos           (0U)
+#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */
+#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define TIM_ARR_ARR_Pos           (0U)
+#define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RCR register  ********************/
+#define TIM_RCR_REP_Pos           (0U)
+#define TIM_RCR_REP_Msk           (0xFFUL << TIM_RCR_REP_Pos)                  /*!< 0x000000FF */
+#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define TIM_CCR1_CCR1_Pos         (0U)
+#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)              /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define TIM_CCR2_CCR2_Pos         (0U)
+#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)              /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define TIM_CCR3_CCR3_Pos         (0U)
+#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)              /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define TIM_CCR4_CCR4_Pos         (0U)
+#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)              /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_CCR5 register  *******************/
+#define TIM_CCR5_CCR5_Pos         (0U)
+#define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)          /*!< 0xFFFFFFFF */
+#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */
+#define TIM_CCR5_GC5C1_Pos        (29U)
+#define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */
+#define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */
+#define TIM_CCR5_GC5C2_Pos        (30U)
+#define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */
+#define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */
+#define TIM_CCR5_GC5C3_Pos        (31U)
+#define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */
+#define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */
+
+/*******************  Bit definition for TIM_CCR6 register  *******************/
+#define TIM_CCR6_CCR6_Pos         (0U)
+#define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */
+#define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define TIM_BDTR_DTG_Pos          (0U)
+#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */
+#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000001 */
+#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000002 */
+#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000004 */
+#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000008 */
+#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000010 */
+#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000020 */
+#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000040 */
+#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000080 */
+
+#define TIM_BDTR_LOCK_Pos         (8U)
+#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */
+#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000100 */
+#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000200 */
+
+#define TIM_BDTR_OSSI_Pos         (10U)
+#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */
+#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos         (11U)
+#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */
+#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos          (12U)
+#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */
+#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break1 */
+#define TIM_BDTR_BKP_Pos          (13U)
+#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */
+#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break1 */
+#define TIM_BDTR_AOE_Pos          (14U)
+#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */
+#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos          (15U)
+#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */
+#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
+
+#define TIM_BDTR_BKF_Pos          (16U)
+#define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */
+#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break1 */
+#define TIM_BDTR_BK2F_Pos         (20U)
+#define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */
+#define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break2 */
+
+#define TIM_BDTR_BK2E_Pos         (24U)
+#define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */
+#define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break2 */
+#define TIM_BDTR_BK2P_Pos         (25U)
+#define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */
+#define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break2 */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define TIM_DCR_DBA_Pos           (0U)
+#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */
+#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
+#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
+#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
+#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
+#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos           (8U)
+#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */
+#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
+#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
+#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
+#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
+#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define TIM_DMAR_DMAB_Pos         (0U)
+#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)              /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
+
+/******************  Bit definition for TIM_CCMR3 register  *******************/
+#define TIM_CCMR3_OC5FE_Pos       (2U)
+#define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */
+#define TIM_CCMR3_OC5PE_Pos       (3U)
+#define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */
+#define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
+
+#define TIM_CCMR3_OC5M_Pos        (4U)
+#define TIM_CCMR3_OC5M_Msk        (0x7UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00000070 */
+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_0          (0x1UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000010 */
+#define TIM_CCMR3_OC5M_1          (0x2UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000020 */
+#define TIM_CCMR3_OC5M_2          (0x4UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000040 */
+#define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010000 */
+
+#define TIM_CCMR3_OC5CE_Pos       (7U)
+#define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */
+#define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */
+
+#define TIM_CCMR3_OC6FE_Pos       (10U)
+#define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR3_OC6PE_Pos       (11U)
+#define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */
+#define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR3_OC6M_Pos        (12U)
+#define TIM_CCMR3_OC6M_Msk        (0x7UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x00007000 */
+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR3_OC6M_0          (0x1UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00001000 */
+#define TIM_CCMR3_OC6M_1          (0x2UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00002000 */
+#define TIM_CCMR3_OC6M_2          (0x4UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00004000 */
+#define TIM_CCMR3_OC6M_3          (0x100UL << TIM_CCMR3_OC6M_Pos)               /*!< 0x00100000 */
+
+#define TIM_CCMR3_OC6CE_Pos       (15U)
+#define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
+#define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 4 Clear Enable */
+/*******************  Bit definition for TIM1_AF1 register  *********************/
+#define TIM1_AF1_BKINE_Pos        (0U)
+#define TIM1_AF1_BKINE_Msk        (0x1UL << TIM1_AF1_BKINE_Pos)                /*!< 0x00000001 */
+#define TIM1_AF1_BKINE            TIM1_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */
+#define TIM1_AF1_BKCMP1E_Pos      (1U)
+#define TIM1_AF1_BKCMP1E_Msk      (0x1UL << TIM1_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */
+#define TIM1_AF1_BKCMP1E          TIM1_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */
+#define TIM1_AF1_BKCMP2E_Pos      (2U)
+#define TIM1_AF1_BKCMP2E_Msk      (0x1UL << TIM1_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */
+#define TIM1_AF1_BKCMP2E          TIM1_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit */
+#define TIM1_AF1_BKDF1BK0E_Pos    (8U)
+#define TIM1_AF1_BKDF1BK0E_Msk    (0x1UL << TIM1_AF1_BKDF1BK0E_Pos)            /*!< 0x00000100 */
+#define TIM1_AF1_BKDF1BK0E        TIM1_AF1_BKDF1BK0E_Msk                       /*!<BKDF1BK0E Break input DFSDM Break 0 */
+#define TIM1_AF1_BKINP_Pos        (9U)
+#define TIM1_AF1_BKINP_Msk        (0x1UL << TIM1_AF1_BKINP_Pos)                /*!< 0x00000200 */
+#define TIM1_AF1_BKINP            TIM1_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */
+#define TIM1_AF1_BKCMP1P_Pos      (10U)
+#define TIM1_AF1_BKCMP1P_Msk      (0x1UL << TIM1_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */
+#define TIM1_AF1_BKCMP1P          TIM1_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */
+#define TIM1_AF1_BKCMP2P_Pos      (11U)
+#define TIM1_AF1_BKCMP2P_Msk      (0x1UL << TIM1_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */
+#define TIM1_AF1_BKCMP2P          TIM1_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */
+
+#define TIM1_AF1_ETRSEL_Pos       (14U)
+#define TIM1_AF1_ETRSEL_Msk       (0xFUL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */
+#define TIM1_AF1_ETRSEL           TIM1_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM1 ETRSEL) */
+#define TIM1_AF1_ETRSEL_0         (0x1UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00004000 */
+#define TIM1_AF1_ETRSEL_1         (0x2UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00008000 */
+#define TIM1_AF1_ETRSEL_2         (0x4UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00010000 */
+#define TIM1_AF1_ETRSEL_3         (0x8UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00020000 */
+
+/*******************  Bit definition for TIM1_AF2 register  *********************/
+#define TIM1_AF2_BK2INE_Pos       (0U)
+#define TIM1_AF2_BK2INE_Msk       (0x1UL << TIM1_AF2_BK2INE_Pos)               /*!< 0x00000001 */
+#define TIM1_AF2_BK2INE           TIM1_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */
+#define TIM1_AF2_BK2CMP1E_Pos     (1U)
+#define TIM1_AF2_BK2CMP1E_Msk     (0x1UL << TIM1_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */
+#define TIM1_AF2_BK2CMP1E         TIM1_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */
+#define TIM1_AF2_BK2CMP2E_Pos     (2U)
+#define TIM1_AF2_BK2CMP2E_Msk     (0x1UL << TIM1_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */
+#define TIM1_AF2_BK2CMP2E         TIM1_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */
+#define TIM1_AF2_BK2DFBK1E_Pos    (8U)
+#define TIM1_AF2_BK2DFBK1E_Msk    (0x1UL << TIM1_AF2_BK2DFBK1E_Pos)            /*!< 0x00000100 */
+#define TIM1_AF2_BK2DFBK1E        TIM1_AF2_BK2DFBK1E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 1 */
+#define TIM1_AF2_BK2INP_Pos       (9U)
+#define TIM1_AF2_BK2INP_Msk       (0x1UL << TIM1_AF2_BK2INP_Pos)               /*!< 0x00000200 */
+#define TIM1_AF2_BK2INP           TIM1_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */
+#define TIM1_AF2_BK2CMP1P_Pos     (10U)
+#define TIM1_AF2_BK2CMP1P_Msk     (0x1UL << TIM1_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */
+#define TIM1_AF2_BK2CMP1P         TIM1_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */
+#define TIM1_AF2_BK2CMP2P_Pos     (11U)
+#define TIM1_AF2_BK2CMP2P_Msk     (0x1UL << TIM1_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */
+#define TIM1_AF2_BK2CMP2P         TIM1_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */
+
+/*******************  Bit definition for TIM_TISEL register  *********************/
+#define TIM_TISEL_TI1SEL_Pos      (0U)
+#define TIM_TISEL_TI1SEL_Msk      (0xFUL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x0000000F */
+#define TIM_TISEL_TI1SEL          TIM_TISEL_TI1SEL_Msk                         /*!<TI1SEL[3:0] bits (TIM TI1 SEL)*/
+#define TIM_TISEL_TI1SEL_0        (0x1UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000001 */
+#define TIM_TISEL_TI1SEL_1        (0x2UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000002 */
+#define TIM_TISEL_TI1SEL_2        (0x4UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000004 */
+#define TIM_TISEL_TI1SEL_3        (0x8UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000008 */
+
+#define TIM_TISEL_TI2SEL_Pos      (8U)
+#define TIM_TISEL_TI2SEL_Msk      (0xFUL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000F00 */
+#define TIM_TISEL_TI2SEL          TIM_TISEL_TI2SEL_Msk                         /*!<TI2SEL[3:0] bits (TIM TI2 SEL)*/
+#define TIM_TISEL_TI2SEL_0        (0x1UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000100 */
+#define TIM_TISEL_TI2SEL_1        (0x2UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000200 */
+#define TIM_TISEL_TI2SEL_2        (0x4UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000400 */
+#define TIM_TISEL_TI2SEL_3        (0x8UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000800 */
+
+#define TIM_TISEL_TI3SEL_Pos      (16U)
+#define TIM_TISEL_TI3SEL_Msk      (0xFUL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x000F0000 */
+#define TIM_TISEL_TI3SEL          TIM_TISEL_TI3SEL_Msk                         /*!<TI3SEL[3:0] bits (TIM TI3 SEL)*/
+#define TIM_TISEL_TI3SEL_0        (0x1UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00010000 */
+#define TIM_TISEL_TI3SEL_1        (0x2UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00020000 */
+#define TIM_TISEL_TI3SEL_2        (0x4UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00040000 */
+#define TIM_TISEL_TI3SEL_3        (0x8UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00080000 */
+
+#define TIM_TISEL_TI4SEL_Pos      (24U)
+#define TIM_TISEL_TI4SEL_Msk      (0xFUL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x0F000000 */
+#define TIM_TISEL_TI4SEL          TIM_TISEL_TI4SEL_Msk                         /*!<TI4SEL[3:0] bits (TIM TI4 SEL)*/
+#define TIM_TISEL_TI4SEL_0        (0x1UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x01000000 */
+#define TIM_TISEL_TI4SEL_1        (0x2UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x02000000 */
+#define TIM_TISEL_TI4SEL_2        (0x4UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x04000000 */
+#define TIM_TISEL_TI4SEL_3        (0x8UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x08000000 */
+
+/*******************  Bit definition for TIM8_AF1 register  *********************/
+#define TIM8_AF1_BKINE_Pos        (0U)
+#define TIM8_AF1_BKINE_Msk        (0x1UL << TIM8_AF1_BKINE_Pos)                /*!< 0x00000001 */
+#define TIM8_AF1_BKINE            TIM8_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */
+#define TIM8_AF1_BKCMP1E_Pos      (1U)
+#define TIM8_AF1_BKCMP1E_Msk      (0x1UL << TIM8_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */
+#define TIM8_AF1_BKCMP1E          TIM8_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */
+#define TIM8_AF1_BKCMP2E_Pos      (2U)
+#define TIM8_AF1_BKCMP2E_Msk      (0x1UL << TIM8_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */
+#define TIM8_AF1_BKCMP2E          TIM8_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit  */
+#define TIM8_AF1_BKDFBK2E_Pos     (8U)
+#define TIM8_AF1_BKDFBK2E_Msk     (0x1UL << TIM8_AF1_BKDFBK2E_Pos)             /*!< 0x00000100 */
+#define TIM8_AF1_BKDFBK2E         TIM8_AF1_BKDFBK2E_Msk                        /*!<BKDFBK2E Break input DFSDM Break 2 */
+#define TIM8_AF1_BKINP_Pos        (9U)
+#define TIM8_AF1_BKINP_Msk        (0x1UL << TIM8_AF1_BKINP_Pos)                /*!< 0x00000200 */
+#define TIM8_AF1_BKINP            TIM8_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */
+#define TIM8_AF1_BKCMP1P_Pos      (10U)
+#define TIM8_AF1_BKCMP1P_Msk      (0x1UL << TIM8_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */
+#define TIM8_AF1_BKCMP1P          TIM8_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */
+#define TIM8_AF1_BKCMP2P_Pos      (11U)
+#define TIM8_AF1_BKCMP2P_Msk      (0x1UL << TIM8_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */
+#define TIM8_AF1_BKCMP2P          TIM8_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */
+
+#define TIM8_AF1_ETRSEL_Pos       (14U)
+#define TIM8_AF1_ETRSEL_Msk       (0xFUL << TIM8_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */
+#define TIM8_AF1_ETRSEL           TIM8_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM8 ETRSEL) */
+#define TIM8_AF1_ETRSEL_0         (0x1UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00004000 */
+#define TIM8_AF1_ETRSEL_1         (0x2UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00008000 */
+#define TIM8_AF1_ETRSEL_2         (0x4UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00010000 */
+#define TIM8_AF1_ETRSEL_3         (0x8UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00020000 */
+/*******************  Bit definition for TIM8_AF2 register  *********************/
+#define TIM8_AF2_BK2INE_Pos       (0U)
+#define TIM8_AF2_BK2INE_Msk       (0x1UL << TIM8_AF2_BK2INE_Pos)               /*!< 0x00000001 */
+#define TIM8_AF2_BK2INE           TIM8_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */
+#define TIM8_AF2_BK2CMP1E_Pos     (1U)
+#define TIM8_AF2_BK2CMP1E_Msk     (0x1UL << TIM8_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */
+#define TIM8_AF2_BK2CMP1E         TIM8_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */
+#define TIM8_AF2_BK2CMP2E_Pos     (2U)
+#define TIM8_AF2_BK2CMP2E_Msk     (0x1UL << TIM8_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */
+#define TIM8_AF2_BK2CMP2E         TIM8_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */
+#define TIM8_AF2_BK2DFBK3E_Pos    (8U)
+#define TIM8_AF2_BK2DFBK3E_Msk    (0x1UL << TIM8_AF2_BK2DFBK3E_Pos)            /*!< 0x00000100 */
+#define TIM8_AF2_BK2DFBK3E        TIM8_AF2_BK2DFBK3E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 3 */
+#define TIM8_AF2_BK2INP_Pos       (9U)
+#define TIM8_AF2_BK2INP_Msk       (0x1UL << TIM8_AF2_BK2INP_Pos)               /*!< 0x00000200 */
+#define TIM8_AF2_BK2INP           TIM8_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */
+#define TIM8_AF2_BK2CMP1P_Pos     (10U)
+#define TIM8_AF2_BK2CMP1P_Msk     (0x1UL << TIM8_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */
+#define TIM8_AF2_BK2CMP1P         TIM8_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */
+#define TIM8_AF2_BK2CMP2P_Pos     (11U)
+#define TIM8_AF2_BK2CMP2P_Msk     (0x1UL << TIM8_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */
+#define TIM8_AF2_BK2CMP2P         TIM8_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */
+
+/*******************  Bit definition for TIM2_AF1 register  *********************/
+#define TIM2_AF1_ETRSEL_Pos      (14U)
+#define TIM2_AF1_ETRSEL_Msk      (0xFUL << TIM2_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */
+#define TIM2_AF1_ETRSEL          TIM2_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM2 ETRSEL) */
+#define TIM2_AF1_ETRSEL_0        (0x1UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */
+#define TIM2_AF1_ETRSEL_1        (0x2UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */
+#define TIM2_AF1_ETRSEL_2        (0x4UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */
+#define TIM2_AF1_ETRSEL_3        (0x8UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */
+
+/*******************  Bit definition for TIM3_AF1 register  *********************/
+#define TIM3_AF1_ETRSEL_Pos      (14U)
+#define TIM3_AF1_ETRSEL_Msk      (0xFUL << TIM3_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */
+#define TIM3_AF1_ETRSEL          TIM3_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM3 ETRSEL) */
+#define TIM3_AF1_ETRSEL_0        (0x1UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */
+#define TIM3_AF1_ETRSEL_1        (0x2UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */
+#define TIM3_AF1_ETRSEL_2        (0x4UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */
+#define TIM3_AF1_ETRSEL_3        (0x8UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */
+
+/*******************  Bit definition for TIM5_AF1 register  *********************/
+#define TIM5_AF1_ETRSEL_Pos      (14U)
+#define TIM5_AF1_ETRSEL_Msk      (0xFUL << TIM5_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */
+#define TIM5_AF1_ETRSEL          TIM5_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM5 ETRSEL) */
+#define TIM5_AF1_ETRSEL_0        (0x1UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */
+#define TIM5_AF1_ETRSEL_1        (0x2UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */
+#define TIM5_AF1_ETRSEL_2        (0x4UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */
+#define TIM5_AF1_ETRSEL_3        (0x8UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */
+
+/*******************  Bit definition for TIM15_AF1 register  *********************/
+#define TIM15_AF1_BKINE_Pos        (0U)
+#define TIM15_AF1_BKINE_Msk        (0x1UL << TIM15_AF1_BKINE_Pos)              /*!< 0x00000001 */
+#define TIM15_AF1_BKINE            TIM15_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */
+#define TIM15_AF1_BKCMP1E_Pos      (1U)
+#define TIM15_AF1_BKCMP1E_Msk      (0x1UL << TIM15_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */
+#define TIM15_AF1_BKCMP1E          TIM15_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */
+#define TIM15_AF1_BKCMP2E_Pos      (2U)
+#define TIM15_AF1_BKCMP2E_Msk      (0x1UL << TIM15_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */
+#define TIM15_AF1_BKCMP2E          TIM15_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */
+#define TIM15_AF1_BKDF1BK2E_Pos    (8U)
+#define TIM15_AF1_BKDF1BK2E_Msk    (0x1UL << TIM15_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */
+#define TIM15_AF1_BKDF1BK2E        TIM15_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[0] enable */
+#define TIM15_AF1_BKINP_Pos        (9U)
+#define TIM15_AF1_BKINP_Msk        (0x1UL << TIM15_AF1_BKINP_Pos)              /*!< 0x00000200 */
+#define TIM15_AF1_BKINP            TIM15_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */
+#define TIM15_AF1_BKCMP1P_Pos      (10U)
+#define TIM15_AF1_BKCMP1P_Msk      (0x1UL << TIM15_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */
+#define TIM15_AF1_BKCMP1P          TIM15_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */
+#define TIM15_AF1_BKCMP2P_Pos      (11U)
+#define TIM15_AF1_BKCMP2P_Msk      (0x1UL << TIM15_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */
+#define TIM15_AF1_BKCMP2P          TIM15_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */
+
+/*******************  Bit definition for TIM16_ register  *********************/
+#define TIM16_AF1_BKINE_Pos        (0U)
+#define TIM16_AF1_BKINE_Msk        (0x1UL << TIM16_AF1_BKINE_Pos)              /*!< 0x00000001 */
+#define TIM16_AF1_BKINE            TIM16_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */
+#define TIM16_AF1_BKCMP1E_Pos      (1U)
+#define TIM16_AF1_BKCMP1E_Msk      (0x1UL << TIM16_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */
+#define TIM16_AF1_BKCMP1E          TIM16_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */
+#define TIM16_AF1_BKCMP2E_Pos      (2U)
+#define TIM16_AF1_BKCMP2E_Msk      (0x1UL << TIM16_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */
+#define TIM16_AF1_BKCMP2E          TIM16_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */
+#define TIM16_AF1_BKDF1BK2E_Pos    (8U)
+#define TIM16_AF1_BKDF1BK2E_Msk    (0x1UL << TIM16_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */
+#define TIM16_AF1_BKDF1BK2E        TIM16_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[1] enable */
+#define TIM16_AF1_BKINP_Pos        (9U)
+#define TIM16_AF1_BKINP_Msk        (0x1UL << TIM16_AF1_BKINP_Pos)              /*!< 0x00000200 */
+#define TIM16_AF1_BKINP            TIM16_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */
+#define TIM16_AF1_BKCMP1P_Pos      (10U)
+#define TIM16_AF1_BKCMP1P_Msk      (0x1UL << TIM16_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */
+#define TIM16_AF1_BKCMP1P          TIM16_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */
+#define TIM16_AF1_BKCMP2P_Pos      (11U)
+#define TIM16_AF1_BKCMP2P_Msk      (0x1UL << TIM16_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */
+#define TIM16_AF1_BKCMP2P          TIM16_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */
+
+/*******************  Bit definition for TIM17_AF1 register  *********************/
+#define TIM17_AF1_BKINE_Pos        (0U)
+#define TIM17_AF1_BKINE_Msk        (0x1UL << TIM17_AF1_BKINE_Pos)              /*!< 0x00000001 */
+#define TIM17_AF1_BKINE            TIM17_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */
+#define TIM17_AF1_BKCMP1E_Pos      (1U)
+#define TIM17_AF1_BKCMP1E_Msk      (0x1UL << TIM17_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */
+#define TIM17_AF1_BKCMP1E          TIM17_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */
+#define TIM17_AF1_BKCMP2E_Pos      (2U)
+#define TIM17_AF1_BKCMP2E_Msk      (0x1UL << TIM17_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */
+#define TIM17_AF1_BKCMP2E          TIM17_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */
+#define TIM17_AF1_BKDF1BK2E_Pos    (8U)
+#define TIM17_AF1_BKDF1BK2E_Msk    (0x1UL << TIM17_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */
+#define TIM17_AF1_BKDF1BK2E        TIM17_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[2] enable */
+#define TIM17_AF1_BKINP_Pos        (9U)
+#define TIM17_AF1_BKINP_Msk        (0x1UL << TIM17_AF1_BKINP_Pos)              /*!< 0x00000200 */
+#define TIM17_AF1_BKINP            TIM17_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */
+#define TIM17_AF1_BKCMP1P_Pos      (10U)
+#define TIM17_AF1_BKCMP1P_Msk      (0x1UL << TIM17_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */
+#define TIM17_AF1_BKCMP1P          TIM17_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */
+#define TIM17_AF1_BKCMP2P_Pos      (11U)
+#define TIM17_AF1_BKCMP2P_Msk      (0x1UL << TIM17_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */
+#define TIM17_AF1_BKCMP2P          TIM17_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Low Power Timer (LPTTIM)                           */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for LPTIM_ISR register  *******************/
+#define LPTIM_ISR_CMPM_Pos          (0U)
+#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)              /*!< 0x00000001 */
+#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
+#define LPTIM_ISR_ARRM_Pos          (1U)
+#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */
+#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG_Pos       (2U)
+#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */
+#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK_Pos         (3U)
+#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)             /*!< 0x00000008 */
+#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK_Pos         (4U)
+#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */
+#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP_Pos            (5U)
+#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */
+#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN_Pos          (6U)
+#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */
+#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
+
+/******************  Bit definition for LPTIM_ICR register  *******************/
+#define LPTIM_ICR_CMPMCF_Pos        (0U)
+#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)            /*!< 0x00000001 */
+#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF_Pos        (1U)
+#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */
+#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)
+#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */
+#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF_Pos       (3U)
+#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)           /*!< 0x00000008 */
+#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF_Pos       (4U)
+#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */
+#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF_Pos          (5U)
+#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */
+#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF_Pos        (6U)
+#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */
+#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
+
+/******************  Bit definition for LPTIM_IER register ********************/
+#define LPTIM_IER_CMPMIE_Pos        (0U)
+#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)            /*!< 0x00000001 */
+#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE_Pos        (1U)
+#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)            /*!< 0x00000002 */
+#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE_Pos     (2U)
+#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)         /*!< 0x00000004 */
+#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE_Pos       (3U)
+#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)           /*!< 0x00000008 */
+#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE_Pos       (4U)
+#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)           /*!< 0x00000010 */
+#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE_Pos          (5U)
+#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)              /*!< 0x00000020 */
+#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE_Pos        (6U)
+#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)            /*!< 0x00000040 */
+#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
+
+/******************  Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL_Pos        (0U)
+#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */
+#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL_Pos        (1U)
+#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */
+#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */
+#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */
+
+#define LPTIM_CFGR_CKFLT_Pos        (3U)
+#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */
+#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */
+#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */
+
+#define LPTIM_CFGR_TRGFLT_Pos       (6U)
+#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */
+#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */
+#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */
+
+#define LPTIM_CFGR_PRESC_Pos        (9U)
+#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */
+#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */
+#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */
+#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */
+
+#define LPTIM_CFGR_TRIGSEL_Pos      (13U)
+#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x0000E000 */
+#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */
+#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */
+#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */
+
+#define LPTIM_CFGR_TRIGEN_Pos       (17U)
+#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */
+#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */
+#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */
+
+#define LPTIM_CFGR_TIMOUT_Pos       (19U)
+#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */
+#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
+#define LPTIM_CFGR_WAVE_Pos         (20U)
+#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */
+#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL_Pos       (21U)
+#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */
+#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD_Pos      (22U)
+#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */
+#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE_Pos    (23U)
+#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */
+#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC_Pos          (24U)
+#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */
+#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
+
+/******************  Bit definition for LPTIM_CR register  ********************/
+#define LPTIM_CR_ENABLE_Pos         (0U)
+#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */
+#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT_Pos        (1U)
+#define LPTIM_CR_SNGSTRT_Msk        (0x40001UL << LPTIM_CR_SNGSTRT_Pos)        /*!< 0x00080002 */
+#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT_Pos        (2U)
+#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */
+#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
+#define LPTIM_CR_COUNTRST_Pos       (3U)
+#define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */
+#define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Timer Counter reset in synchronous mode*/
+#define LPTIM_CR_RSTARE_Pos         (4U)
+#define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */
+#define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Timer Counter reset after read enable (asynchronously)*/
+
+
+/******************  Bit definition for LPTIM_CMP register  *******************/
+#define LPTIM_CMP_CMP_Pos           (0U)
+#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)            /*!< 0x0000FFFF */
+#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
+
+/******************  Bit definition for LPTIM_ARR register  *******************/
+#define LPTIM_ARR_ARR_Pos           (0U)
+#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */
+#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
+
+/******************  Bit definition for LPTIM_CNT register  *******************/
+#define LPTIM_CNT_CNT_Pos           (0U)
+#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */
+#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
+
+/******************  Bit definition for LPTIM_CFGR2 register  *****************/
+#define LPTIM_CFGR2_IN1SEL_Pos      (0U)
+#define LPTIM_CFGR2_IN1SEL_Msk      (0x3UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000003 */
+#define LPTIM_CFGR2_IN1SEL          LPTIM_CFGR2_IN1SEL_Msk                     /*!< IN1SEL[1:0] bits (Remap selection) */
+#define LPTIM_CFGR2_IN1SEL_0        (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000001 */
+#define LPTIM_CFGR2_IN1SEL_1        (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000002 */
+#define LPTIM_CFGR2_IN2SEL_Pos      (4U)
+#define LPTIM_CFGR2_IN2SEL_Msk      (0x3UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000030 */
+#define LPTIM_CFGR2_IN2SEL          LPTIM_CFGR2_IN2SEL_Msk                     /*!< IN2SEL[5:4] bits (Remap selection) */
+#define LPTIM_CFGR2_IN2SEL_0        (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000010 */
+#define LPTIM_CFGR2_IN2SEL_1        (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000020 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Analog Comparators (COMP)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for COMP_SR register  ********************/
+#define COMP_SR_C1VAL_Pos            (0U)
+#define COMP_SR_C1VAL_Msk            (0x1UL << COMP_SR_C1VAL_Pos)              /*!< 0x00000001 */
+#define COMP_SR_C1VAL                COMP_SR_C1VAL_Msk
+#define COMP_SR_C2VAL_Pos            (1U)
+#define COMP_SR_C2VAL_Msk            (0x1UL << COMP_SR_C2VAL_Pos)              /*!< 0x00000002 */
+#define COMP_SR_C2VAL                COMP_SR_C2VAL_Msk
+#define COMP_SR_C1IF_Pos             (16U)
+#define COMP_SR_C1IF_Msk             (0x1UL << COMP_SR_C1IF_Pos)               /*!< 0x00010000 */
+#define COMP_SR_C1IF                 COMP_SR_C1IF_Msk
+#define COMP_SR_C2IF_Pos             (17U)
+#define COMP_SR_C2IF_Msk             (0x1UL << COMP_SR_C2IF_Pos)               /*!< 0x00020000 */
+#define COMP_SR_C2IF                 COMP_SR_C2IF_Msk
+/*******************  Bit definition for COMP_ICFR register  ********************/
+#define COMP_ICFR_C1IF_Pos           (16U)
+#define COMP_ICFR_C1IF_Msk           (0x1UL << COMP_ICFR_C1IF_Pos)             /*!< 0x00010000 */
+#define COMP_ICFR_C1IF               COMP_ICFR_C1IF_Msk
+#define COMP_ICFR_C2IF_Pos           (17U)
+#define COMP_ICFR_C2IF_Msk           (0x1UL << COMP_ICFR_C2IF_Pos)             /*!< 0x00020000 */
+#define COMP_ICFR_C2IF               COMP_ICFR_C2IF_Msk
+/*******************  Bit definition for COMP_OR register  ********************/
+#define COMP_OR_AFOPA6_Pos           (0U)
+#define COMP_OR_AFOPA6_Msk           (0x1UL << COMP_OR_AFOPA6_Pos)             /*!< 0x00000001 */
+#define COMP_OR_AFOPA6               COMP_OR_AFOPA6_Msk
+#define COMP_OR_AFOPA8_Pos           (1U)
+#define COMP_OR_AFOPA8_Msk           (0x1UL << COMP_OR_AFOPA8_Pos)             /*!< 0x00000002 */
+#define COMP_OR_AFOPA8               COMP_OR_AFOPA8_Msk
+#define COMP_OR_AFOPB12_Pos          (2U)
+#define COMP_OR_AFOPB12_Msk          (0x1UL << COMP_OR_AFOPB12_Pos)            /*!< 0x00000004 */
+#define COMP_OR_AFOPB12              COMP_OR_AFOPB12_Msk
+#define COMP_OR_AFOPE6_Pos           (3U)
+#define COMP_OR_AFOPE6_Msk           (0x1UL << COMP_OR_AFOPE6_Pos)             /*!< 0x00000008 */
+#define COMP_OR_AFOPE6               COMP_OR_AFOPE6_Msk
+#define COMP_OR_AFOPE15_Pos          (4U)
+#define COMP_OR_AFOPE15_Msk          (0x1UL << COMP_OR_AFOPE15_Pos)            /*!< 0x00000010 */
+#define COMP_OR_AFOPE15              COMP_OR_AFOPE15_Msk
+#define COMP_OR_AFOPG2_Pos           (5U)
+#define COMP_OR_AFOPG2_Msk           (0x1UL << COMP_OR_AFOPG2_Pos)             /*!< 0x00000020 */
+#define COMP_OR_AFOPG2               COMP_OR_AFOPG2_Msk
+#define COMP_OR_AFOPG3_Pos           (6U)
+#define COMP_OR_AFOPG3_Msk           (0x1UL << COMP_OR_AFOPG3_Pos)             /*!< 0x00000040 */
+#define COMP_OR_AFOPG3               COMP_OR_AFOPG3_Msk
+#define COMP_OR_AFOPG4_Pos           (7U)
+#define COMP_OR_AFOPG4_Msk           (0x1UL << COMP_OR_AFOPG4_Pos)             /*!< 0x00000080 */
+#define COMP_OR_AFOPG4               COMP_OR_AFOPG4_Msk
+#define COMP_OR_AFOPI1_Pos           (8U)
+#define COMP_OR_AFOPI1_Msk           (0x1UL << COMP_OR_AFOPI1_Pos)             /*!< 0x00000100 */
+#define COMP_OR_AFOPI1               COMP_OR_AFOPI1_Msk
+#define COMP_OR_AFOPI4_Pos           (9U)
+#define COMP_OR_AFOPI4_Msk           (0x1UL << COMP_OR_AFOPI4_Pos)             /*!< 0x00000200 */
+#define COMP_OR_AFOPI4               COMP_OR_AFOPI4_Msk
+#define COMP_OR_AFOPK2_Pos           (10U)
+#define COMP_OR_AFOPK2_Msk           (0x1UL << COMP_OR_AFOPK2_Pos)             /*!< 0x00000400 */
+#define COMP_OR_AFOPK2               COMP_OR_AFOPK2_Msk
+
+/*!< ******************  Bit definition for COMP_CFGRx register  ********************/
+#define COMP_CFGRx_EN_Pos            (0U)
+#define COMP_CFGRx_EN_Msk            (0x1UL << COMP_CFGRx_EN_Pos)              /*!< 0x00000001 */
+#define COMP_CFGRx_EN                COMP_CFGRx_EN_Msk                         /*!< COMPx enable bit                     */
+#define COMP_CFGRx_BRGEN_Pos         (1U)
+#define COMP_CFGRx_BRGEN_Msk         (0x1UL << COMP_CFGRx_BRGEN_Pos)           /*!< 0x00000002 */
+#define COMP_CFGRx_BRGEN             COMP_CFGRx_BRGEN_Msk                      /*!< COMPx Scaler bridge enable           */
+#define COMP_CFGRx_SCALEN_Pos        (2U)
+#define COMP_CFGRx_SCALEN_Msk        (0x1UL << COMP_CFGRx_SCALEN_Pos)          /*!< 0x00000004 */
+#define COMP_CFGRx_SCALEN            COMP_CFGRx_SCALEN_Msk                     /*!< COMPx Voltage scaler enable bit      */
+#define COMP_CFGRx_POLARITY_Pos      (3U)
+#define COMP_CFGRx_POLARITY_Msk      (0x1UL << COMP_CFGRx_POLARITY_Pos)        /*!< 0x00000008 */
+#define COMP_CFGRx_POLARITY          COMP_CFGRx_POLARITY_Msk                   /*!< COMPx  polarity selection bit        */
+#define COMP_CFGRx_WINMODE_Pos       (4U)
+#define COMP_CFGRx_WINMODE_Msk       (0x1UL << COMP_CFGRx_WINMODE_Pos)         /*!< 0x00000010 */
+#define COMP_CFGRx_WINMODE           COMP_CFGRx_WINMODE_Msk                    /*!< COMPx Windows mode selection bit     */
+#define COMP_CFGRx_ITEN_Pos          (6U)
+#define COMP_CFGRx_ITEN_Msk          (0x1UL << COMP_CFGRx_ITEN_Pos)            /*!< 0x00000040 */
+#define COMP_CFGRx_ITEN              COMP_CFGRx_ITEN_Msk                       /*!< COMPx  interrupt enable              */
+#define COMP_CFGRx_HYST_Pos          (8U)
+#define COMP_CFGRx_HYST_Msk          (0x3UL << COMP_CFGRx_HYST_Pos)            /*!< 0x00000300 */
+#define COMP_CFGRx_HYST              COMP_CFGRx_HYST_Msk                       /*!< COMPx  hysteresis selection bits     */
+#define COMP_CFGRx_HYST_0            (0x1UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000100 */
+#define COMP_CFGRx_HYST_1            (0x2UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000200 */
+#define COMP_CFGRx_PWRMODE_Pos       (12U)
+#define COMP_CFGRx_PWRMODE_Msk       (0x3UL << COMP_CFGRx_PWRMODE_Pos)         /*!< 0x00003000 */
+#define COMP_CFGRx_PWRMODE           COMP_CFGRx_PWRMODE_Msk                    /*!< COMPx Power Mode of the comparator   */
+#define COMP_CFGRx_PWRMODE_0         (0x1UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00001000 */
+#define COMP_CFGRx_PWRMODE_1         (0x2UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00002000 */
+#define COMP_CFGRx_INMSEL_Pos        (16U)
+#define COMP_CFGRx_INMSEL_Msk        (0x7UL << COMP_CFGRx_INMSEL_Pos)          /*!< 0x00070000 */
+#define COMP_CFGRx_INMSEL            COMP_CFGRx_INMSEL_Msk                     /*!< COMPx  input minus selection bit  */
+#define COMP_CFGRx_INMSEL_0          (0x1UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00010000 */
+#define COMP_CFGRx_INMSEL_1          (0x2UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00020000 */
+#define COMP_CFGRx_INMSEL_2          (0x4UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00040000 */
+#define COMP_CFGRx_INPSEL_Pos        (20U)
+#define COMP_CFGRx_INPSEL_Msk        (0x1UL << COMP_CFGRx_INPSEL_Pos)          /*!< 0x00100000 */
+#define COMP_CFGRx_INPSEL            COMP_CFGRx_INPSEL_Msk                     /*!< COMPx  input plus selection bit       */
+#define COMP_CFGRx_BLANKING_Pos      (24U)
+#define COMP_CFGRx_BLANKING_Msk      (0xFUL << COMP_CFGRx_BLANKING_Pos)        /*!< 0x0F000000 */
+#define COMP_CFGRx_BLANKING          COMP_CFGRx_BLANKING_Msk                   /*!< COMPx  blanking source selection bits */
+#define COMP_CFGRx_BLANKING_0        (0x1UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x01000000 */
+#define COMP_CFGRx_BLANKING_1        (0x2UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x02000000 */
+#define COMP_CFGRx_BLANKING_2        (0x4UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x04000000 */
+#define COMP_CFGRx_LOCK_Pos          (31U)
+#define COMP_CFGRx_LOCK_Msk          (0x1UL << COMP_CFGRx_LOCK_Pos)            /*!< 0x80000000 */
+#define COMP_CFGRx_LOCK              COMP_CFGRx_LOCK_Msk                       /*!< COMPx Lock Bit                        */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for USART_CR1 register  *******************/
+#define USART_CR1_UE_Pos                (0U)
+#define USART_CR1_UE_Msk                (0x1UL << USART_CR1_UE_Pos)            /*!< 0x00000001 */
+#define USART_CR1_UE                    USART_CR1_UE_Msk                       /*!< USART Enable */
+#define USART_CR1_UESM_Pos              (1U)
+#define USART_CR1_UESM_Msk              (0x1UL << USART_CR1_UESM_Pos)          /*!< 0x00000002 */
+#define USART_CR1_UESM                  USART_CR1_UESM_Msk                     /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE_Pos                (2U)
+#define USART_CR1_RE_Msk                (0x1UL << USART_CR1_RE_Pos)            /*!< 0x00000004 */
+#define USART_CR1_RE                    USART_CR1_RE_Msk                       /*!< Receiver Enable */
+#define USART_CR1_TE_Pos                (3U)
+#define USART_CR1_TE_Msk                (0x1UL << USART_CR1_TE_Pos)            /*!< 0x00000008 */
+#define USART_CR1_TE                    USART_CR1_TE_Msk                       /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos            (4U)
+#define USART_CR1_IDLEIE_Msk            (0x1UL << USART_CR1_IDLEIE_Pos)        /*!< 0x00000010 */
+#define USART_CR1_IDLEIE                USART_CR1_IDLEIE_Msk                   /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_RXFNEIE_Pos    (5U)
+#define USART_CR1_RXNEIE_RXFNEIE_Msk    (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE_RXFNEIE        USART_CR1_RXNEIE_RXFNEIE_Msk           /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
+#define USART_CR1_TCIE_Pos              (6U)
+#define USART_CR1_TCIE_Msk              (0x1UL << USART_CR1_TCIE_Pos)          /*!< 0x00000040 */
+#define USART_CR1_TCIE                  USART_CR1_TCIE_Msk                     /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_TXFNFIE_Pos     (7U)
+#define USART_CR1_TXEIE_TXFNFIE_Msk     (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE_TXFNFIE         USART_CR1_TXEIE_TXFNFIE_Msk            /*!< TXE and TX FIFO Not Full Interrupt Enable */
+#define USART_CR1_PEIE_Pos              (8U)
+#define USART_CR1_PEIE_Msk              (0x1UL << USART_CR1_PEIE_Pos)          /*!< 0x00000100 */
+#define USART_CR1_PEIE                  USART_CR1_PEIE_Msk                     /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos                (9U)
+#define USART_CR1_PS_Msk                (0x1UL << USART_CR1_PS_Pos)            /*!< 0x00000200 */
+#define USART_CR1_PS                    USART_CR1_PS_Msk                       /*!< Parity Selection */
+#define USART_CR1_PCE_Pos               (10U)
+#define USART_CR1_PCE_Msk               (0x1UL << USART_CR1_PCE_Pos)           /*!< 0x00000400 */
+#define USART_CR1_PCE                   USART_CR1_PCE_Msk                      /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos              (11U)
+#define USART_CR1_WAKE_Msk              (0x1UL << USART_CR1_WAKE_Pos)          /*!< 0x00000800 */
+#define USART_CR1_WAKE                  USART_CR1_WAKE_Msk                     /*!< Receiver Wakeup method */
+#define USART_CR1_M_Pos                 (12U)
+#define USART_CR1_M_Msk                 (0x10001UL << USART_CR1_M_Pos)         /*!< 0x10001000 */
+#define USART_CR1_M                     USART_CR1_M_Msk                        /*!< Word length */
+#define USART_CR1_M0_Pos                (12U)
+#define USART_CR1_M0_Msk                (0x1UL << USART_CR1_M0_Pos)            /*!< 0x00001000 */
+#define USART_CR1_M0                    USART_CR1_M0_Msk                       /*!< Word length - Bit 0 */
+#define USART_CR1_MME_Pos               (13U)
+#define USART_CR1_MME_Msk               (0x1UL << USART_CR1_MME_Pos)           /*!< 0x00002000 */
+#define USART_CR1_MME                   USART_CR1_MME_Msk                      /*!< Mute Mode Enable */
+#define USART_CR1_CMIE_Pos              (14U)
+#define USART_CR1_CMIE_Msk              (0x1UL << USART_CR1_CMIE_Pos)          /*!< 0x00004000 */
+#define USART_CR1_CMIE                  USART_CR1_CMIE_Msk                     /*!< Character match interrupt enable */
+#define USART_CR1_OVER8_Pos             (15U)
+#define USART_CR1_OVER8_Msk             (0x1UL << USART_CR1_OVER8_Pos)         /*!< 0x00008000 */
+#define USART_CR1_OVER8                 USART_CR1_OVER8_Msk                    /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT_Pos              (16U)
+#define USART_CR1_DEDT_Msk              (0x1FUL << USART_CR1_DEDT_Pos)         /*!< 0x001F0000 */
+#define USART_CR1_DEDT                  USART_CR1_DEDT_Msk                     /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0                (0x01UL << USART_CR1_DEDT_Pos)          /*!< 0x00010000 */
+#define USART_CR1_DEDT_1                (0x02UL << USART_CR1_DEDT_Pos)          /*!< 0x00020000 */
+#define USART_CR1_DEDT_2                (0x04UL << USART_CR1_DEDT_Pos)          /*!< 0x00040000 */
+#define USART_CR1_DEDT_3                (0x08UL << USART_CR1_DEDT_Pos)          /*!< 0x00080000 */
+#define USART_CR1_DEDT_4                (0x10UL << USART_CR1_DEDT_Pos)          /*!< 0x00100000 */
+#define USART_CR1_DEAT_Pos              (21U)
+#define USART_CR1_DEAT_Msk              (0x1FUL << USART_CR1_DEAT_Pos)         /*!< 0x03E00000 */
+#define USART_CR1_DEAT                  USART_CR1_DEAT_Msk                     /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0                (0x01UL << USART_CR1_DEAT_Pos)          /*!< 0x00200000 */
+#define USART_CR1_DEAT_1                (0x02UL << USART_CR1_DEAT_Pos)          /*!< 0x00400000 */
+#define USART_CR1_DEAT_2                (0x04UL << USART_CR1_DEAT_Pos)          /*!< 0x00800000 */
+#define USART_CR1_DEAT_3                (0x08UL << USART_CR1_DEAT_Pos)          /*!< 0x01000000 */
+#define USART_CR1_DEAT_4                (0x10UL << USART_CR1_DEAT_Pos)          /*!< 0x02000000 */
+#define USART_CR1_RTOIE_Pos             (26U)
+#define USART_CR1_RTOIE_Msk             (0x1UL << USART_CR1_RTOIE_Pos)         /*!< 0x04000000 */
+#define USART_CR1_RTOIE                 USART_CR1_RTOIE_Msk                    /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE_Pos             (27U)
+#define USART_CR1_EOBIE_Msk             (0x1UL << USART_CR1_EOBIE_Pos)         /*!< 0x08000000 */
+#define USART_CR1_EOBIE                 USART_CR1_EOBIE_Msk                    /*!< End of Block interrupt enable */
+#define USART_CR1_M1_Pos                (28U)
+#define USART_CR1_M1_Msk                (0x1UL << USART_CR1_M1_Pos)            /*!< 0x10000000 */
+#define USART_CR1_M1                    USART_CR1_M1_Msk                       /*!< Word length - Bit 1 */
+#define USART_CR1_FIFOEN_Pos            (29U)
+#define USART_CR1_FIFOEN_Msk            (0x1UL << USART_CR1_FIFOEN_Pos)        /*!< 0x20000000 */
+#define USART_CR1_FIFOEN                USART_CR1_FIFOEN_Msk                   /*!< FIFO mode enable */
+#define USART_CR1_TXFEIE_Pos            (30U)
+#define USART_CR1_TXFEIE_Msk            (0x1UL << USART_CR1_TXFEIE_Pos)        /*!< 0x40000000 */
+#define USART_CR1_TXFEIE                USART_CR1_TXFEIE_Msk                   /*!< TXFIFO empty interrupt enable */
+#define USART_CR1_RXFFIE_Pos            (31U)
+#define USART_CR1_RXFFIE_Msk            (0x1UL << USART_CR1_RXFFIE_Pos)        /*!< 0x80000000 */
+#define USART_CR1_RXFFIE                USART_CR1_RXFFIE_Msk                   /*!< RXFIFO Full interrupt enable */
+
+/* Legacy define */
+#define  USART_CR1_RXNEIE  USART_CR1_RXNEIE_RXFNEIE
+#define  USART_CR1_TXEIE   USART_CR1_TXEIE_TXFNFIE
+
+/******************  Bit definition for USART_CR2 register  *******************/
+#define USART_CR2_SLVEN_Pos             (0U)
+#define USART_CR2_SLVEN_Msk             (0x1UL << USART_CR2_SLVEN_Pos)         /*!< 0x00000001 */
+#define USART_CR2_SLVEN                 USART_CR2_SLVEN_Msk                    /*!< Synchronous Slave mode Enable */
+#define USART_CR2_DIS_NSS_Pos           (3U)
+#define USART_CR2_DIS_NSS_Msk           (0x1UL << USART_CR2_DIS_NSS_Pos)       /*!< 0x00000008 */
+#define USART_CR2_DIS_NSS               USART_CR2_DIS_NSS_Msk                  /*!< Negative Slave Select (NSS) pin management */
+#define USART_CR2_ADDM7_Pos             (4U)
+#define USART_CR2_ADDM7_Msk             (0x1UL << USART_CR2_ADDM7_Pos)         /*!< 0x00000010 */
+#define USART_CR2_ADDM7                 USART_CR2_ADDM7_Msk                    /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL_Pos              (5U)
+#define USART_CR2_LBDL_Msk              (0x1UL << USART_CR2_LBDL_Pos)          /*!< 0x00000020 */
+#define USART_CR2_LBDL                  USART_CR2_LBDL_Msk                     /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos             (6U)
+#define USART_CR2_LBDIE_Msk             (0x1UL << USART_CR2_LBDIE_Pos)         /*!< 0x00000040 */
+#define USART_CR2_LBDIE                 USART_CR2_LBDIE_Msk                    /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos              (8U)
+#define USART_CR2_LBCL_Msk              (0x1UL << USART_CR2_LBCL_Pos)          /*!< 0x00000100 */
+#define USART_CR2_LBCL                  USART_CR2_LBCL_Msk                     /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos              (9U)
+#define USART_CR2_CPHA_Msk              (0x1UL << USART_CR2_CPHA_Pos)          /*!< 0x00000200 */
+#define USART_CR2_CPHA                  USART_CR2_CPHA_Msk                     /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos              (10U)
+#define USART_CR2_CPOL_Msk              (0x1UL << USART_CR2_CPOL_Pos)          /*!< 0x00000400 */
+#define USART_CR2_CPOL                  USART_CR2_CPOL_Msk                     /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos             (11U)
+#define USART_CR2_CLKEN_Msk             (0x1UL << USART_CR2_CLKEN_Pos)         /*!< 0x00000800 */
+#define USART_CR2_CLKEN                 USART_CR2_CLKEN_Msk                    /*!< Clock Enable */
+#define USART_CR2_STOP_Pos              (12U)
+#define USART_CR2_STOP_Msk              (0x3UL << USART_CR2_STOP_Pos)          /*!< 0x00003000 */
+#define USART_CR2_STOP                  USART_CR2_STOP_Msk                     /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0                (0x1UL << USART_CR2_STOP_Pos)           /*!< 0x00001000 */
+#define USART_CR2_STOP_1                (0x2UL << USART_CR2_STOP_Pos)           /*!< 0x00002000 */
+#define USART_CR2_LINEN_Pos             (14U)
+#define USART_CR2_LINEN_Msk             (0x1UL << USART_CR2_LINEN_Pos)         /*!< 0x00004000 */
+#define USART_CR2_LINEN                 USART_CR2_LINEN_Msk                    /*!< LIN mode enable */
+#define USART_CR2_SWAP_Pos              (15U)
+#define USART_CR2_SWAP_Msk              (0x1UL << USART_CR2_SWAP_Pos)          /*!< 0x00008000 */
+#define USART_CR2_SWAP                  USART_CR2_SWAP_Msk                     /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV_Pos             (16U)
+#define USART_CR2_RXINV_Msk             (0x1UL << USART_CR2_RXINV_Pos)         /*!< 0x00010000 */
+#define USART_CR2_RXINV                 USART_CR2_RXINV_Msk                    /*!< RX pin active level inversion */
+#define USART_CR2_TXINV_Pos             (17U)
+#define USART_CR2_TXINV_Msk             (0x1UL << USART_CR2_TXINV_Pos)         /*!< 0x00020000 */
+#define USART_CR2_TXINV                 USART_CR2_TXINV_Msk                    /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV_Pos           (18U)
+#define USART_CR2_DATAINV_Msk           (0x1UL << USART_CR2_DATAINV_Pos)       /*!< 0x00040000 */
+#define USART_CR2_DATAINV               USART_CR2_DATAINV_Msk                  /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST_Pos          (19U)
+#define USART_CR2_MSBFIRST_Msk          (0x1UL << USART_CR2_MSBFIRST_Pos)      /*!< 0x00080000 */
+#define USART_CR2_MSBFIRST              USART_CR2_MSBFIRST_Msk                 /*!< Most Significant Bit First */
+#define USART_CR2_ABREN_Pos             (20U)
+#define USART_CR2_ABREN_Msk             (0x1UL << USART_CR2_ABREN_Pos)         /*!< 0x00100000 */
+#define USART_CR2_ABREN                 USART_CR2_ABREN_Msk                    /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE_Pos           (21U)
+#define USART_CR2_ABRMODE_Msk           (0x3UL << USART_CR2_ABRMODE_Pos)       /*!< 0x00600000 */
+#define USART_CR2_ABRMODE               USART_CR2_ABRMODE_Msk                  /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0             (0x1UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00200000 */
+#define USART_CR2_ABRMODE_1             (0x2UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00400000 */
+#define USART_CR2_RTOEN_Pos             (23U)
+#define USART_CR2_RTOEN_Msk             (0x1UL << USART_CR2_RTOEN_Pos)         /*!< 0x00800000 */
+#define USART_CR2_RTOEN                 USART_CR2_RTOEN_Msk                    /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD_Pos               (24U)
+#define USART_CR2_ADD_Msk               (0xFFUL << USART_CR2_ADD_Pos)          /*!< 0xFF000000 */
+#define USART_CR2_ADD                   USART_CR2_ADD_Msk                      /*!< Address of the USART node */
+
+/******************  Bit definition for USART_CR3 register  *******************/
+#define USART_CR3_EIE_Pos               (0U)
+#define USART_CR3_EIE_Msk               (0x1UL << USART_CR3_EIE_Pos)           /*!< 0x00000001 */
+#define USART_CR3_EIE                   USART_CR3_EIE_Msk                      /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos              (1U)
+#define USART_CR3_IREN_Msk              (0x1UL << USART_CR3_IREN_Pos)          /*!< 0x00000002 */
+#define USART_CR3_IREN                  USART_CR3_IREN_Msk                     /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos              (2U)
+#define USART_CR3_IRLP_Msk              (0x1UL << USART_CR3_IRLP_Pos)          /*!< 0x00000004 */
+#define USART_CR3_IRLP                  USART_CR3_IRLP_Msk                     /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos             (3U)
+#define USART_CR3_HDSEL_Msk             (0x1UL << USART_CR3_HDSEL_Pos)         /*!< 0x00000008 */
+#define USART_CR3_HDSEL                 USART_CR3_HDSEL_Msk                    /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos              (4U)
+#define USART_CR3_NACK_Msk              (0x1UL << USART_CR3_NACK_Pos)          /*!< 0x00000010 */
+#define USART_CR3_NACK                  USART_CR3_NACK_Msk                     /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN_Pos              (5U)
+#define USART_CR3_SCEN_Msk              (0x1UL << USART_CR3_SCEN_Pos)          /*!< 0x00000020 */
+#define USART_CR3_SCEN                  USART_CR3_SCEN_Msk                     /*!< SmartCard mode enable */
+#define USART_CR3_DMAR_Pos              (6U)
+#define USART_CR3_DMAR_Msk              (0x1UL << USART_CR3_DMAR_Pos)          /*!< 0x00000040 */
+#define USART_CR3_DMAR                  USART_CR3_DMAR_Msk                     /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos              (7U)
+#define USART_CR3_DMAT_Msk              (0x1UL << USART_CR3_DMAT_Pos)          /*!< 0x00000080 */
+#define USART_CR3_DMAT                  USART_CR3_DMAT_Msk                     /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos              (8U)
+#define USART_CR3_RTSE_Msk              (0x1UL << USART_CR3_RTSE_Pos)          /*!< 0x00000100 */
+#define USART_CR3_RTSE                  USART_CR3_RTSE_Msk                     /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos              (9U)
+#define USART_CR3_CTSE_Msk              (0x1UL << USART_CR3_CTSE_Pos)          /*!< 0x00000200 */
+#define USART_CR3_CTSE                  USART_CR3_CTSE_Msk                     /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos             (10U)
+#define USART_CR3_CTSIE_Msk             (0x1UL << USART_CR3_CTSIE_Pos)         /*!< 0x00000400 */
+#define USART_CR3_CTSIE                 USART_CR3_CTSIE_Msk                    /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos            (11U)
+#define USART_CR3_ONEBIT_Msk            (0x1UL << USART_CR3_ONEBIT_Pos)        /*!< 0x00000800 */
+#define USART_CR3_ONEBIT                USART_CR3_ONEBIT_Msk                   /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS_Pos            (12U)
+#define USART_CR3_OVRDIS_Msk            (0x1UL << USART_CR3_OVRDIS_Pos)        /*!< 0x00001000 */
+#define USART_CR3_OVRDIS                USART_CR3_OVRDIS_Msk                   /*!< Overrun Disable */
+#define USART_CR3_DDRE_Pos              (13U)
+#define USART_CR3_DDRE_Msk              (0x1UL << USART_CR3_DDRE_Pos)          /*!< 0x00002000 */
+#define USART_CR3_DDRE                  USART_CR3_DDRE_Msk                     /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM_Pos               (14U)
+#define USART_CR3_DEM_Msk               (0x1UL << USART_CR3_DEM_Pos)           /*!< 0x00004000 */
+#define USART_CR3_DEM                   USART_CR3_DEM_Msk                      /*!< Driver Enable Mode */
+#define USART_CR3_DEP_Pos               (15U)
+#define USART_CR3_DEP_Msk               (0x1UL << USART_CR3_DEP_Pos)           /*!< 0x00008000 */
+#define USART_CR3_DEP                   USART_CR3_DEP_Msk                      /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT_Pos           (17U)
+#define USART_CR3_SCARCNT_Msk           (0x7UL << USART_CR3_SCARCNT_Pos)       /*!< 0x000E0000 */
+#define USART_CR3_SCARCNT               USART_CR3_SCARCNT_Msk                  /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0             (0x1UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00020000 */
+#define USART_CR3_SCARCNT_1             (0x2UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00040000 */
+#define USART_CR3_SCARCNT_2             (0x4UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00080000 */
+#define USART_CR3_WUS_Pos               (20U)
+#define USART_CR3_WUS_Msk               (0x3UL << USART_CR3_WUS_Pos)           /*!< 0x00300000 */
+#define USART_CR3_WUS                   USART_CR3_WUS_Msk                      /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0                 (0x1UL << USART_CR3_WUS_Pos)            /*!< 0x00100000 */
+#define USART_CR3_WUS_1                 (0x2UL << USART_CR3_WUS_Pos)            /*!< 0x00200000 */
+#define USART_CR3_WUFIE_Pos             (22U)
+#define USART_CR3_WUFIE_Msk             (0x1UL << USART_CR3_WUFIE_Pos)         /*!< 0x00400000 */
+#define USART_CR3_WUFIE                 USART_CR3_WUFIE_Msk                    /*!< Wake Up Interrupt Enable */
+#define USART_CR3_TXFTIE_Pos            (23U)
+#define USART_CR3_TXFTIE_Msk            (0x1UL << USART_CR3_TXFTIE_Pos)        /*!< 0x00800000 */
+#define USART_CR3_TXFTIE                USART_CR3_TXFTIE_Msk                   /*!< TXFIFO threshold interrupt enable */
+#define USART_CR3_TCBGTIE_Pos           (24U)
+#define USART_CR3_TCBGTIE_Msk           (0x1UL << USART_CR3_TCBGTIE_Pos)       /*!< 0x01000000 */
+#define USART_CR3_TCBGTIE               USART_CR3_TCBGTIE_Msk                  /*!< Transmission Complete before guard time, interrupt enable */
+#define USART_CR3_RXFTCFG_Pos           (25U)
+#define USART_CR3_RXFTCFG_Msk           (0x7UL << USART_CR3_RXFTCFG_Pos)       /*!< 0x0E000000 */
+#define USART_CR3_RXFTCFG               USART_CR3_RXFTCFG_Msk                  /*!< RXFTCFG [2:0]Receive FIFO threshold configuration */
+#define USART_CR3_RXFTCFG_0             (0x1UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x02000000 */
+#define USART_CR3_RXFTCFG_1             (0x2UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x04000000 */
+#define USART_CR3_RXFTCFG_2             (0x4UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x08000000 */
+#define USART_CR3_RXFTIE_Pos            (28U)
+#define USART_CR3_RXFTIE_Msk            (0x1UL << USART_CR3_RXFTIE_Pos)        /*!< 0x10000000 */
+#define USART_CR3_RXFTIE                USART_CR3_RXFTIE_Msk                   /*!< RXFIFO threshold interrupt enable */
+#define USART_CR3_TXFTCFG_Pos           (29U)
+#define USART_CR3_TXFTCFG_Msk           (0x7UL << USART_CR3_TXFTCFG_Pos)       /*!< 0xE0000000 */
+#define USART_CR3_TXFTCFG               USART_CR3_TXFTCFG_Msk                  /*!< TXFIFO [2:0] threshold configuration */
+#define USART_CR3_TXFTCFG_0             (0x1UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x20000000 */
+#define USART_CR3_TXFTCFG_1             (0x2UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x40000000 */
+#define USART_CR3_TXFTCFG_2             (0x4UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x80000000 */
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define USART_BRR_DIV_FRACTION_Pos      (0U)
+#define USART_BRR_DIV_FRACTION_Msk      (0xFUL << USART_BRR_DIV_FRACTION_Pos)  /*!< 0x0000000F */
+#define USART_BRR_DIV_FRACTION          USART_BRR_DIV_FRACTION_Msk             /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA_Pos      (4U)
+#define USART_BRR_DIV_MANTISSA_Msk      (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_MANTISSA          USART_BRR_DIV_MANTISSA_Msk             /*!< Mantissa of USARTDIV */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define USART_GTPR_PSC_Pos              (0U)
+#define USART_GTPR_PSC_Msk              (0xFFUL << USART_GTPR_PSC_Pos)         /*!< 0x000000FF */
+#define USART_GTPR_PSC                  USART_GTPR_PSC_Msk                     /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT_Pos               (8U)
+#define USART_GTPR_GT_Msk               (0xFFUL << USART_GTPR_GT_Pos)          /*!< 0x0000FF00 */
+#define USART_GTPR_GT                   USART_GTPR_GT_Msk                      /*!< GT[7:0] bits (Guard time value) */
+
+/*******************  Bit definition for USART_RTOR register  *****************/
+#define USART_RTOR_RTO_Pos              (0U)
+#define USART_RTOR_RTO_Msk              (0xFFFFFFUL << USART_RTOR_RTO_Pos)     /*!< 0x00FFFFFF */
+#define USART_RTOR_RTO                  USART_RTOR_RTO_Msk                     /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN_Pos             (24U)
+#define USART_RTOR_BLEN_Msk             (0xFFUL << USART_RTOR_BLEN_Pos)        /*!< 0xFF000000 */
+#define USART_RTOR_BLEN                 USART_RTOR_BLEN_Msk                    /*!< Block Length */
+
+/*******************  Bit definition for USART_RQR register  ******************/
+#define USART_RQR_ABRRQ_Pos             (0U)
+#define USART_RQR_ABRRQ_Msk             (0x1UL << USART_RQR_ABRRQ_Pos)         /*!< 0x00000001 */
+#define USART_RQR_ABRRQ                 USART_RQR_ABRRQ_Msk                    /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ_Pos             (1U)
+#define USART_RQR_SBKRQ_Msk             (0x1UL << USART_RQR_SBKRQ_Pos)         /*!< 0x00000002 */
+#define USART_RQR_SBKRQ                 USART_RQR_SBKRQ_Msk                    /*!< Send Break Request */
+#define USART_RQR_MMRQ_Pos              (2U)
+#define USART_RQR_MMRQ_Msk              (0x1UL << USART_RQR_MMRQ_Pos)          /*!< 0x00000004 */
+#define USART_RQR_MMRQ                  USART_RQR_MMRQ_Msk                     /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ_Pos             (3U)
+#define USART_RQR_RXFRQ_Msk             (0x1UL << USART_RQR_RXFRQ_Pos)         /*!< 0x00000008 */
+#define USART_RQR_RXFRQ                 USART_RQR_RXFRQ_Msk                    /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ_Pos             (4U)
+#define USART_RQR_TXFRQ_Msk             (0x1UL << USART_RQR_TXFRQ_Pos)         /*!< 0x00000010 */
+#define USART_RQR_TXFRQ                 USART_RQR_TXFRQ_Msk                    /*!< Transmit data flush Request */
+
+/*******************  Bit definition for USART_ISR register  ******************/
+#define USART_ISR_PE_Pos                (0U)
+#define USART_ISR_PE_Msk                (0x1UL << USART_ISR_PE_Pos)            /*!< 0x00000001 */
+#define USART_ISR_PE                    USART_ISR_PE_Msk                       /*!< Parity Error */
+#define USART_ISR_FE_Pos                (1U)
+#define USART_ISR_FE_Msk                (0x1UL << USART_ISR_FE_Pos)            /*!< 0x00000002 */
+#define USART_ISR_FE                    USART_ISR_FE_Msk                       /*!< Framing Error */
+#define USART_ISR_NE_Pos                (2U)
+#define USART_ISR_NE_Msk                (0x1UL << USART_ISR_NE_Pos)            /*!< 0x00000004 */
+#define USART_ISR_NE                    USART_ISR_NE_Msk                       /*!< Noise detected Flag */
+#define USART_ISR_ORE_Pos               (3U)
+#define USART_ISR_ORE_Msk               (0x1UL << USART_ISR_ORE_Pos)           /*!< 0x00000008 */
+#define USART_ISR_ORE                   USART_ISR_ORE_Msk                      /*!< OverRun Error */
+#define USART_ISR_IDLE_Pos              (4U)
+#define USART_ISR_IDLE_Msk              (0x1UL << USART_ISR_IDLE_Pos)          /*!< 0x00000010 */
+#define USART_ISR_IDLE                  USART_ISR_IDLE_Msk                     /*!< IDLE line detected */
+#define USART_ISR_RXNE_RXFNE_Pos        (5U)
+#define USART_ISR_RXNE_RXFNE_Msk        (0x1UL << USART_ISR_RXNE_RXFNE_Pos)    /*!< 0x00000020 */
+#define USART_ISR_RXNE_RXFNE            USART_ISR_RXNE_RXFNE_Msk               /*!< Read Data Register or RX FIFO Not Empty */
+#define USART_ISR_TC_Pos                (6U)
+#define USART_ISR_TC_Msk                (0x1UL << USART_ISR_TC_Pos)            /*!< 0x00000040 */
+#define USART_ISR_TC                    USART_ISR_TC_Msk                       /*!< Transmission Complete */
+#define USART_ISR_TXE_TXFNF_Pos         (7U)
+#define USART_ISR_TXE_TXFNF_Msk         (0x1UL << USART_ISR_TXE_TXFNF_Pos)     /*!< 0x00000080 */
+#define USART_ISR_TXE_TXFNF             USART_ISR_TXE_TXFNF_Msk                /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
+#define USART_ISR_LBDF_Pos              (8U)
+#define USART_ISR_LBDF_Msk              (0x1UL << USART_ISR_LBDF_Pos)          /*!< 0x00000100 */
+#define USART_ISR_LBDF                  USART_ISR_LBDF_Msk                     /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF_Pos             (9U)
+#define USART_ISR_CTSIF_Msk             (0x1UL << USART_ISR_CTSIF_Pos)         /*!< 0x00000200 */
+#define USART_ISR_CTSIF                 USART_ISR_CTSIF_Msk                    /*!< CTS interrupt flag */
+#define USART_ISR_CTS_Pos               (10U)
+#define USART_ISR_CTS_Msk               (0x1UL << USART_ISR_CTS_Pos)           /*!< 0x00000400 */
+#define USART_ISR_CTS                   USART_ISR_CTS_Msk                      /*!< CTS flag */
+#define USART_ISR_RTOF_Pos              (11U)
+#define USART_ISR_RTOF_Msk              (0x1UL << USART_ISR_RTOF_Pos)          /*!< 0x00000800 */
+#define USART_ISR_RTOF                  USART_ISR_RTOF_Msk                     /*!< Receiver Time Out */
+#define USART_ISR_EOBF_Pos              (12U)
+#define USART_ISR_EOBF_Msk              (0x1UL << USART_ISR_EOBF_Pos)          /*!< 0x00001000 */
+#define USART_ISR_EOBF                  USART_ISR_EOBF_Msk                     /*!< End Of Block Flag */
+#define USART_ISR_UDR_Pos               (13U)
+#define USART_ISR_UDR_Msk               (0x1UL << USART_ISR_UDR_Pos)           /*!< 0x00002000 */
+#define USART_ISR_UDR                   USART_ISR_UDR_Msk                      /*!< SPI slave underrun error flag */
+#define USART_ISR_ABRE_Pos              (14U)
+#define USART_ISR_ABRE_Msk              (0x1UL << USART_ISR_ABRE_Pos)          /*!< 0x00004000 */
+#define USART_ISR_ABRE                  USART_ISR_ABRE_Msk                     /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF_Pos              (15U)
+#define USART_ISR_ABRF_Msk              (0x1UL << USART_ISR_ABRF_Pos)          /*!< 0x00008000 */
+#define USART_ISR_ABRF                  USART_ISR_ABRF_Msk                     /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY_Pos              (16U)
+#define USART_ISR_BUSY_Msk              (0x1UL << USART_ISR_BUSY_Pos)          /*!< 0x00010000 */
+#define USART_ISR_BUSY                  USART_ISR_BUSY_Msk                     /*!< Busy Flag */
+#define USART_ISR_CMF_Pos               (17U)
+#define USART_ISR_CMF_Msk               (0x1UL << USART_ISR_CMF_Pos)           /*!< 0x00020000 */
+#define USART_ISR_CMF                   USART_ISR_CMF_Msk                      /*!< Character Match Flag */
+#define USART_ISR_SBKF_Pos              (18U)
+#define USART_ISR_SBKF_Msk              (0x1UL << USART_ISR_SBKF_Pos)          /*!< 0x00040000 */
+#define USART_ISR_SBKF                  USART_ISR_SBKF_Msk                     /*!< Send Break Flag */
+#define USART_ISR_RWU_Pos               (19U)
+#define USART_ISR_RWU_Msk               (0x1UL << USART_ISR_RWU_Pos)           /*!< 0x00080000 */
+#define USART_ISR_RWU                   USART_ISR_RWU_Msk                      /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF_Pos               (20U)
+#define USART_ISR_WUF_Msk               (0x1UL << USART_ISR_WUF_Pos)           /*!< 0x00100000 */
+#define USART_ISR_WUF                   USART_ISR_WUF_Msk                      /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK_Pos             (21U)
+#define USART_ISR_TEACK_Msk             (0x1UL << USART_ISR_TEACK_Pos)         /*!< 0x00200000 */
+#define USART_ISR_TEACK                 USART_ISR_TEACK_Msk                    /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK_Pos             (22U)
+#define USART_ISR_REACK_Msk             (0x1UL << USART_ISR_REACK_Pos)         /*!< 0x00400000 */
+#define USART_ISR_REACK                 USART_ISR_REACK_Msk                    /*!< Receive Enable Acknowledge Flag */
+#define USART_ISR_TXFE_Pos              (23U)
+#define USART_ISR_TXFE_Msk              (0x1UL << USART_ISR_TXFE_Pos)          /*!< 0x00800000 */
+#define USART_ISR_TXFE                  USART_ISR_TXFE_Msk                     /*!< TXFIFO Empty */
+#define USART_ISR_RXFF_Pos              (24U)
+#define USART_ISR_RXFF_Msk              (0x1UL << USART_ISR_RXFF_Pos)          /*!< 0x01000000 */
+#define USART_ISR_RXFF                  USART_ISR_RXFF_Msk                     /*!< RXFIFO Full Flag */
+#define USART_ISR_TCBGT_Pos             (25U)
+#define USART_ISR_TCBGT_Msk             (0x1UL << USART_ISR_TCBGT_Pos)         /*!< 0x02000000 */
+#define USART_ISR_TCBGT                 USART_ISR_TCBGT_Msk                    /*!< Transmission complete before guard time Flag */
+#define USART_ISR_RXFT_Pos              (26U)
+#define USART_ISR_RXFT_Msk              (0x1UL << USART_ISR_RXFT_Pos)          /*!< 0x04000000 */
+#define USART_ISR_RXFT                  USART_ISR_RXFT_Msk                     /*!< RXFIFO threshold Flag */
+#define USART_ISR_TXFT_Pos              (27U)
+#define USART_ISR_TXFT_Msk              (0x1UL << USART_ISR_TXFT_Pos)          /*!< 0x08000000 */
+#define USART_ISR_TXFT                  USART_ISR_TXFT_Msk                     /*!< TXFIFO threshold Flag */
+
+/*******************  Bit definition for USART_ICR register  ******************/
+#define USART_ICR_PECF_Pos              (0U)
+#define USART_ICR_PECF_Msk              (0x1UL << USART_ICR_PECF_Pos)          /*!< 0x00000001 */
+#define USART_ICR_PECF                  USART_ICR_PECF_Msk                     /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF_Pos              (1U)
+#define USART_ICR_FECF_Msk              (0x1UL << USART_ICR_FECF_Pos)          /*!< 0x00000002 */
+#define USART_ICR_FECF                  USART_ICR_FECF_Msk                     /*!< Framing Error Clear Flag */
+#define USART_ICR_NECF_Pos              (2U)
+#define USART_ICR_NECF_Msk              (0x1UL << USART_ICR_NECF_Pos)          /*!< 0x00000004 */
+#define USART_ICR_NECF                  USART_ICR_NECF_Msk                     /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF_Pos             (3U)
+#define USART_ICR_ORECF_Msk             (0x1UL << USART_ICR_ORECF_Pos)         /*!< 0x00000008 */
+#define USART_ICR_ORECF                 USART_ICR_ORECF_Msk                    /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF_Pos            (4U)
+#define USART_ICR_IDLECF_Msk            (0x1UL << USART_ICR_IDLECF_Pos)        /*!< 0x00000010 */
+#define USART_ICR_IDLECF                USART_ICR_IDLECF_Msk                   /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TXFECF_Pos            (5U)
+#define USART_ICR_TXFECF_Msk            (0x1UL << USART_ICR_TXFECF_Pos)        /*!< 0x00000020 */
+#define USART_ICR_TXFECF                USART_ICR_TXFECF_Msk                   /*!< TXFIFO empty clear flag */
+#define USART_ICR_TCCF_Pos              (6U)
+#define USART_ICR_TCCF_Msk              (0x1UL << USART_ICR_TCCF_Pos)          /*!< 0x00000040 */
+#define USART_ICR_TCCF                  USART_ICR_TCCF_Msk                     /*!< Transmission Complete Clear Flag */
+#define USART_ICR_TCBGTCF_Pos           (7U)
+#define USART_ICR_TCBGTCF_Msk           (0x1UL << USART_ICR_TCBGTCF_Pos)       /*!< 0x00000080 */
+#define USART_ICR_TCBGTCF               USART_ICR_TCBGTCF_Msk                  /*!< Transmission complete before guard time Clear Flag */
+#define USART_ICR_LBDCF_Pos             (8U)
+#define USART_ICR_LBDCF_Msk             (0x1UL << USART_ICR_LBDCF_Pos)         /*!< 0x00000100 */
+#define USART_ICR_LBDCF                 USART_ICR_LBDCF_Msk                    /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF_Pos             (9U)
+#define USART_ICR_CTSCF_Msk             (0x1UL << USART_ICR_CTSCF_Pos)         /*!< 0x00000200 */
+#define USART_ICR_CTSCF                 USART_ICR_CTSCF_Msk                    /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF_Pos             (11U)
+#define USART_ICR_RTOCF_Msk             (0x1UL << USART_ICR_RTOCF_Pos)         /*!< 0x00000800 */
+#define USART_ICR_RTOCF                 USART_ICR_RTOCF_Msk                    /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF_Pos             (12U)
+#define USART_ICR_EOBCF_Msk             (0x1UL << USART_ICR_EOBCF_Pos)         /*!< 0x00001000 */
+#define USART_ICR_EOBCF                 USART_ICR_EOBCF_Msk                    /*!< End Of Block Clear Flag */
+#define USART_ICR_UDRCF_Pos             (13U)
+#define USART_ICR_UDRCF_Msk             (0x1UL << USART_ICR_UDRCF_Pos)         /*!< 0x00002000 */
+#define USART_ICR_UDRCF                 USART_ICR_UDRCF_Msk                    /*!< SPI slave underrun clear flag */
+#define USART_ICR_CMCF_Pos              (17U)
+#define USART_ICR_CMCF_Msk              (0x1UL << USART_ICR_CMCF_Pos)          /*!< 0x00020000 */
+#define USART_ICR_CMCF                  USART_ICR_CMCF_Msk                     /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF_Pos              (20U)
+#define USART_ICR_WUCF_Msk              (0x1UL << USART_ICR_WUCF_Pos)          /*!< 0x00100000 */
+#define USART_ICR_WUCF                  USART_ICR_WUCF_Msk                     /*!< Wake Up from stop mode Clear Flag */
+
+/*******************  Bit definition for USART_RDR register  ******************/
+#define USART_RDR_RDR_Pos               (0U)
+#define USART_RDR_RDR_Msk               (0x1FFUL << USART_RDR_RDR_Pos)         /*!< 0x000001FF */
+#define USART_RDR_RDR                   USART_RDR_RDR_Msk                      /*!< RDR[8:0] bits (Receive Data value) */
+
+/*******************  Bit definition for USART_TDR register  ******************/
+#define USART_TDR_TDR_Pos               (0U)
+#define USART_TDR_TDR_Msk               (0x1FFUL << USART_TDR_TDR_Pos)         /*!< 0x000001FF */
+#define USART_TDR_TDR                   USART_TDR_TDR_Msk                      /*!< TDR[8:0] bits (Transmit Data value) */
+
+/*******************  Bit definition for USART_PRESC register  ******************/
+#define USART_PRESC_PRESCALER_Pos       (0U)
+#define USART_PRESC_PRESCALER_Msk       (0xFUL << USART_PRESC_PRESCALER_Pos)   /*!< 0x0000000F */
+#define USART_PRESC_PRESCALER           USART_PRESC_PRESCALER_Msk              /*!< PRESCALER[3:0] bits (Clock prescaler) */
+#define USART_PRESC_PRESCALER_0         (0x1UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000001 */
+#define USART_PRESC_PRESCALER_1         (0x2UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000002 */
+#define USART_PRESC_PRESCALER_2         (0x4UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000004 */
+#define USART_PRESC_PRESCALER_3         (0x8UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000008 */
+
+/******************************************************************************/
+/*                                                                            */
+/*           Single Wire Protocol Master Interface (SWPMI)                    */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for SWPMI_CR register   ********************/
+#define SWPMI_CR_RXDMA_Pos       (0U)
+#define SWPMI_CR_RXDMA_Msk       (0x1UL << SWPMI_CR_RXDMA_Pos)                 /*!< 0x00000001 */
+#define SWPMI_CR_RXDMA           SWPMI_CR_RXDMA_Msk                            /*!<Reception DMA enable                                 */
+#define SWPMI_CR_TXDMA_Pos       (1U)
+#define SWPMI_CR_TXDMA_Msk       (0x1UL << SWPMI_CR_TXDMA_Pos)                 /*!< 0x00000002 */
+#define SWPMI_CR_TXDMA           SWPMI_CR_TXDMA_Msk                            /*!<Transmission DMA enable                              */
+#define SWPMI_CR_RXMODE_Pos      (2U)
+#define SWPMI_CR_RXMODE_Msk      (0x1UL << SWPMI_CR_RXMODE_Pos)                /*!< 0x00000004 */
+#define SWPMI_CR_RXMODE          SWPMI_CR_RXMODE_Msk                           /*!<Reception buffering mode                             */
+#define SWPMI_CR_TXMODE_Pos      (3U)
+#define SWPMI_CR_TXMODE_Msk      (0x1UL << SWPMI_CR_TXMODE_Pos)                /*!< 0x00000008 */
+#define SWPMI_CR_TXMODE          SWPMI_CR_TXMODE_Msk                           /*!<Transmission buffering mode                          */
+#define SWPMI_CR_LPBK_Pos        (4U)
+#define SWPMI_CR_LPBK_Msk        (0x1UL << SWPMI_CR_LPBK_Pos)                  /*!< 0x00000010 */
+#define SWPMI_CR_LPBK            SWPMI_CR_LPBK_Msk                             /*!<Loopback mode enable                                 */
+#define SWPMI_CR_SWPACT_Pos      (5U)
+#define SWPMI_CR_SWPACT_Msk      (0x1UL << SWPMI_CR_SWPACT_Pos)                /*!< 0x00000020 */
+#define SWPMI_CR_SWPACT          SWPMI_CR_SWPACT_Msk                           /*!<Single wire protocol master interface activate       */
+#define SWPMI_CR_DEACT_Pos       (10U)
+#define SWPMI_CR_DEACT_Msk       (0x1UL << SWPMI_CR_DEACT_Pos)                 /*!< 0x00000400 */
+#define SWPMI_CR_DEACT           SWPMI_CR_DEACT_Msk                            /*!<Single wire protocol master interface deactivate     */
+#define SWPMI_CR_SWPEN_Pos       (11U)
+#define SWPMI_CR_SWPEN_Msk       (0x1UL << SWPMI_CR_SWPEN_Pos)                 /*!< 0x00000800 */
+#define SWPMI_CR_SWPEN           SWPMI_CR_SWPEN_Msk                            /*!<Single wire protocol master transceiver enable       */
+
+/*******************  Bit definition for SWPMI_BRR register  ********************/
+#define SWPMI_BRR_BR_Pos         (0U)
+#define SWPMI_BRR_BR_Msk         (0xFFUL << SWPMI_BRR_BR_Pos)                  /*!< 0x000000FF */
+#define SWPMI_BRR_BR             SWPMI_BRR_BR_Msk                              /*!<BR[7:0] bits (Bitrate prescaler) */
+
+/*******************  Bit definition for SWPMI_ISR register  ********************/
+#define SWPMI_ISR_RXBFF_Pos      (0U)
+#define SWPMI_ISR_RXBFF_Msk      (0x1UL << SWPMI_ISR_RXBFF_Pos)                /*!< 0x00000001 */
+#define SWPMI_ISR_RXBFF          SWPMI_ISR_RXBFF_Msk                           /*!<Receive buffer full flag        */
+#define SWPMI_ISR_TXBEF_Pos      (1U)
+#define SWPMI_ISR_TXBEF_Msk      (0x1UL << SWPMI_ISR_TXBEF_Pos)                /*!< 0x00000002 */
+#define SWPMI_ISR_TXBEF          SWPMI_ISR_TXBEF_Msk                           /*!<Transmit buffer empty flag      */
+#define SWPMI_ISR_RXBERF_Pos     (2U)
+#define SWPMI_ISR_RXBERF_Msk     (0x1UL << SWPMI_ISR_RXBERF_Pos)               /*!< 0x00000004 */
+#define SWPMI_ISR_RXBERF         SWPMI_ISR_RXBERF_Msk                          /*!<Receive CRC error flag          */
+#define SWPMI_ISR_RXOVRF_Pos     (3U)
+#define SWPMI_ISR_RXOVRF_Msk     (0x1UL << SWPMI_ISR_RXOVRF_Pos)               /*!< 0x00000008 */
+#define SWPMI_ISR_RXOVRF         SWPMI_ISR_RXOVRF_Msk                          /*!<Receive overrun error flag      */
+#define SWPMI_ISR_TXUNRF_Pos     (4U)
+#define SWPMI_ISR_TXUNRF_Msk     (0x1UL << SWPMI_ISR_TXUNRF_Pos)               /*!< 0x00000010 */
+#define SWPMI_ISR_TXUNRF         SWPMI_ISR_TXUNRF_Msk                          /*!<Transmit underrun error flag    */
+#define SWPMI_ISR_RXNE_Pos       (5U)
+#define SWPMI_ISR_RXNE_Msk       (0x1UL << SWPMI_ISR_RXNE_Pos)                 /*!< 0x00000020 */
+#define SWPMI_ISR_RXNE           SWPMI_ISR_RXNE_Msk                            /*!<Receive data register not empty */
+#define SWPMI_ISR_TXE_Pos        (6U)
+#define SWPMI_ISR_TXE_Msk        (0x1UL << SWPMI_ISR_TXE_Pos)                  /*!< 0x00000040 */
+#define SWPMI_ISR_TXE            SWPMI_ISR_TXE_Msk                             /*!<Transmit data register empty    */
+#define SWPMI_ISR_TCF_Pos        (7U)
+#define SWPMI_ISR_TCF_Msk        (0x1UL << SWPMI_ISR_TCF_Pos)                  /*!< 0x00000080 */
+#define SWPMI_ISR_TCF            SWPMI_ISR_TCF_Msk                             /*!<Transfer complete flag          */
+#define SWPMI_ISR_SRF_Pos        (8U)
+#define SWPMI_ISR_SRF_Msk        (0x1UL << SWPMI_ISR_SRF_Pos)                  /*!< 0x00000100 */
+#define SWPMI_ISR_SRF            SWPMI_ISR_SRF_Msk                             /*!<Slave resume flag               */
+#define SWPMI_ISR_SUSP_Pos       (9U)
+#define SWPMI_ISR_SUSP_Msk       (0x1UL << SWPMI_ISR_SUSP_Pos)                 /*!< 0x00000200 */
+#define SWPMI_ISR_SUSP           SWPMI_ISR_SUSP_Msk                            /*!<SUSPEND flag                    */
+#define SWPMI_ISR_DEACTF_Pos     (10U)
+#define SWPMI_ISR_DEACTF_Msk     (0x1UL << SWPMI_ISR_DEACTF_Pos)               /*!< 0x00000400 */
+#define SWPMI_ISR_DEACTF         SWPMI_ISR_DEACTF_Msk                          /*!<DEACTIVATED flag                */
+#define SWPMI_ISR_RDYF_Pos       (11U)
+#define SWPMI_ISR_RDYF_Msk       (0x1UL << SWPMI_ISR_RDYF_Pos)                 /*!< 0x00000800 */
+#define SWPMI_ISR_RDYF           SWPMI_ISR_RDYF_Msk                            /*!<Transceiver ready flag          */
+
+/*******************  Bit definition for SWPMI_ICR register  ********************/
+#define SWPMI_ICR_CRXBFF_Pos     (0U)
+#define SWPMI_ICR_CRXBFF_Msk     (0x1UL << SWPMI_ICR_CRXBFF_Pos)               /*!< 0x00000001 */
+#define SWPMI_ICR_CRXBFF         SWPMI_ICR_CRXBFF_Msk                          /*!<Clear receive buffer full flag       */
+#define SWPMI_ICR_CTXBEF_Pos     (1U)
+#define SWPMI_ICR_CTXBEF_Msk     (0x1UL << SWPMI_ICR_CTXBEF_Pos)               /*!< 0x00000002 */
+#define SWPMI_ICR_CTXBEF         SWPMI_ICR_CTXBEF_Msk                          /*!<Clear transmit buffer empty flag     */
+#define SWPMI_ICR_CRXBERF_Pos    (2U)
+#define SWPMI_ICR_CRXBERF_Msk    (0x1UL << SWPMI_ICR_CRXBERF_Pos)              /*!< 0x00000004 */
+#define SWPMI_ICR_CRXBERF        SWPMI_ICR_CRXBERF_Msk                         /*!<Clear receive CRC error flag         */
+#define SWPMI_ICR_CRXOVRF_Pos    (3U)
+#define SWPMI_ICR_CRXOVRF_Msk    (0x1UL << SWPMI_ICR_CRXOVRF_Pos)              /*!< 0x00000008 */
+#define SWPMI_ICR_CRXOVRF        SWPMI_ICR_CRXOVRF_Msk                         /*!<Clear receive overrun error flag     */
+#define SWPMI_ICR_CTXUNRF_Pos    (4U)
+#define SWPMI_ICR_CTXUNRF_Msk    (0x1UL << SWPMI_ICR_CTXUNRF_Pos)              /*!< 0x00000010 */
+#define SWPMI_ICR_CTXUNRF        SWPMI_ICR_CTXUNRF_Msk                         /*!<Clear transmit underrun error flag   */
+#define SWPMI_ICR_CTCF_Pos       (7U)
+#define SWPMI_ICR_CTCF_Msk       (0x1UL << SWPMI_ICR_CTCF_Pos)                 /*!< 0x00000080 */
+#define SWPMI_ICR_CTCF           SWPMI_ICR_CTCF_Msk                            /*!<Clear transfer complete flag         */
+#define SWPMI_ICR_CSRF_Pos       (8U)
+#define SWPMI_ICR_CSRF_Msk       (0x1UL << SWPMI_ICR_CSRF_Pos)                 /*!< 0x00000100 */
+#define SWPMI_ICR_CSRF           SWPMI_ICR_CSRF_Msk                            /*!<Clear slave resume flag              */
+#define SWPMI_ICR_CRDYF_Pos      (11U)
+#define SWPMI_ICR_CRDYF_Msk      (0x1UL << SWPMI_ICR_CRDYF_Pos)                /*!< 0x00000800 */
+#define SWPMI_ICR_CRDYF          SWPMI_ICR_CRDYF_Msk                           /*!<Clear transceiver ready flag         */
+
+/*******************  Bit definition for SWPMI_IER register  ********************/
+#define SWPMI_IER_RXBFIE_Pos     (0U)
+#define SWPMI_IER_RXBFIE_Msk     (0x1UL << SWPMI_IER_RXBFIE_Pos)               /*!< 0x00000001 */
+#define SWPMI_IER_RXBFIE         SWPMI_IER_RXBFIE_Msk                          /*!<Receive buffer full interrupt enable        */
+#define SWPMI_IER_TXBEIE_Pos     (1U)
+#define SWPMI_IER_TXBEIE_Msk     (0x1UL << SWPMI_IER_TXBEIE_Pos)               /*!< 0x00000002 */
+#define SWPMI_IER_TXBEIE         SWPMI_IER_TXBEIE_Msk                          /*!<Transmit buffer empty interrupt enable      */
+#define SWPMI_IER_RXBERIE_Pos    (2U)
+#define SWPMI_IER_RXBERIE_Msk    (0x1UL << SWPMI_IER_RXBERIE_Pos)              /*!< 0x00000004 */
+#define SWPMI_IER_RXBERIE        SWPMI_IER_RXBERIE_Msk                         /*!<Receive CRC error interrupt enable          */
+#define SWPMI_IER_RXOVRIE_Pos    (3U)
+#define SWPMI_IER_RXOVRIE_Msk    (0x1UL << SWPMI_IER_RXOVRIE_Pos)              /*!< 0x00000008 */
+#define SWPMI_IER_RXOVRIE        SWPMI_IER_RXOVRIE_Msk                         /*!<Receive overrun error interrupt enable      */
+#define SWPMI_IER_TXUNRIE_Pos    (4U)
+#define SWPMI_IER_TXUNRIE_Msk    (0x1UL << SWPMI_IER_TXUNRIE_Pos)              /*!< 0x00000010 */
+#define SWPMI_IER_TXUNRIE        SWPMI_IER_TXUNRIE_Msk                         /*!<Transmit underrun error interrupt enable    */
+#define SWPMI_IER_RIE_Pos        (5U)
+#define SWPMI_IER_RIE_Msk        (0x1UL << SWPMI_IER_RIE_Pos)                  /*!< 0x00000020 */
+#define SWPMI_IER_RIE            SWPMI_IER_RIE_Msk                             /*!<Receive interrupt enable                    */
+#define SWPMI_IER_TIE_Pos        (6U)
+#define SWPMI_IER_TIE_Msk        (0x1UL << SWPMI_IER_TIE_Pos)                  /*!< 0x00000040 */
+#define SWPMI_IER_TIE            SWPMI_IER_TIE_Msk                             /*!<Transmit interrupt enable                   */
+#define SWPMI_IER_TCIE_Pos       (7U)
+#define SWPMI_IER_TCIE_Msk       (0x1UL << SWPMI_IER_TCIE_Pos)                 /*!< 0x00000080 */
+#define SWPMI_IER_TCIE           SWPMI_IER_TCIE_Msk                            /*!<Transmit complete interrupt enable          */
+#define SWPMI_IER_SRIE_Pos       (8U)
+#define SWPMI_IER_SRIE_Msk       (0x1UL << SWPMI_IER_SRIE_Pos)                 /*!< 0x00000100 */
+#define SWPMI_IER_SRIE           SWPMI_IER_SRIE_Msk                            /*!<Slave resume interrupt enable               */
+#define SWPMI_IER_RDYIE_Pos      (11U)
+#define SWPMI_IER_RDYIE_Msk      (0x1UL << SWPMI_IER_RDYIE_Pos)                /*!< 0x00000800 */
+#define SWPMI_IER_RDYIE          SWPMI_IER_RDYIE_Msk                           /*!<Transceiver ready interrupt enable          */
+
+/*******************  Bit definition for SWPMI_RFL register  ********************/
+#define SWPMI_RFL_RFL_Pos        (0U)
+#define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */
+#define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */
+#define SWPMI_RFL_RFL_0_1        ((uint32_t)0x00000003)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
+
+/*******************  Bit definition for SWPMI_TDR register  ********************/
+#define SWPMI_TDR_TD_Pos         (0U)
+#define SWPMI_TDR_TD_Msk         (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos)            /*!< 0xFFFFFFFF */
+#define SWPMI_TDR_TD             SWPMI_TDR_TD_Msk                              /*!<Transmit Data Register         */
+
+/*******************  Bit definition for SWPMI_RDR register  ********************/
+#define SWPMI_RDR_RD_Pos         (0U)
+#define SWPMI_RDR_RD_Msk         (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos)            /*!< 0xFFFFFFFF */
+#define SWPMI_RDR_RD             SWPMI_RDR_RD_Msk                              /*!<Recive Data Register           */
+
+
+/*******************  Bit definition for SWPMI_OR register  ********************/
+#define SWPMI_OR_TBYP_Pos        (0U)
+#define SWPMI_OR_TBYP_Msk        (0x1UL << SWPMI_OR_TBYP_Pos)                  /*!< 0x00000001 */
+#define SWPMI_OR_TBYP            SWPMI_OR_TBYP_Msk                             /*!<SWP Transceiver Bypass */
+#define SWPMI_OR_CLASS_Pos       (1U)
+#define SWPMI_OR_CLASS_Msk       (0x1UL << SWPMI_OR_CLASS_Pos)                 /*!< 0x00000002 */
+#define SWPMI_OR_CLASS           SWPMI_OR_CLASS_Msk                            /*!<SWP CLASS selection */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Window WATCHDOG                                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define WWDG_CR_T_Pos           (0U)
+#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                      /*!< 0x0000007F */
+#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
+#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
+#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
+#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
+#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
+#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
+#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
+
+#define WWDG_CR_WDGA_Pos        (7U)
+#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                    /*!< 0x00000080 */
+#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define WWDG_CFR_W_Pos          (0U)
+#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                     /*!< 0x0000007F */
+#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
+#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
+#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
+#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
+#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
+#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
+#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
+
+#define WWDG_CFR_EWI_Pos        (9U)
+#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                    /*!< 0x00000200 */
+#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
+
+#define WWDG_CFR_WDGTB_Pos      (11U)
+#define WWDG_CFR_WDGTB_Msk      (0x7UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00003800 */
+#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[2:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000800 */
+#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00001000 */
+#define WWDG_CFR_WDGTB_2        (0x4UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00002000 */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define WWDG_SR_EWIF_Pos        (0U)
+#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                    /*!< 0x00000001 */
+#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                DBG                                         */
+/*                                                                            */
+/******************************************************************************/
+/*********************************  DEVICE ID  ********************************/
+#define STM32H7_DEV_ID           0x450UL
+
+/********************  Bit definition for DBGMCU_IDCODE register  *************/
+#define DBGMCU_IDCODE_DEV_ID_Pos          (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk          (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID              DBGMCU_IDCODE_DEV_ID_Msk
+#define DBGMCU_IDCODE_REV_ID_Pos          (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk          (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID              DBGMCU_IDCODE_REV_ID_Msk
+
+/********************  Bit definition for DBGMCU_CR register  *****************/
+#define DBGMCU_CR_DBG_SLEEPD1_Pos         (0U)
+#define DBGMCU_CR_DBG_SLEEPD1_Msk         (0x1UL << DBGMCU_CR_DBG_SLEEPD1_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEPD1             DBGMCU_CR_DBG_SLEEPD1_Msk
+#define DBGMCU_CR_DBG_STOPD1_Pos          (1U)
+#define DBGMCU_CR_DBG_STOPD1_Msk          (0x1UL << DBGMCU_CR_DBG_STOPD1_Pos)  /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOPD1              DBGMCU_CR_DBG_STOPD1_Msk
+#define DBGMCU_CR_DBG_STANDBYD1_Pos       (2U)
+#define DBGMCU_CR_DBG_STANDBYD1_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYD1_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBYD1           DBGMCU_CR_DBG_STANDBYD1_Msk
+#define DBGMCU_CR_DBG_STOPD3_Pos          (7U)
+#define DBGMCU_CR_DBG_STOPD3_Msk          (0x1UL << DBGMCU_CR_DBG_STOPD3_Pos)  /*!< 0x00000080 */
+#define DBGMCU_CR_DBG_STOPD3              DBGMCU_CR_DBG_STOPD3_Msk
+#define DBGMCU_CR_DBG_STANDBYD3_Pos       (8U)
+#define DBGMCU_CR_DBG_STANDBYD3_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYD3_Pos) /*!< 0x00000100 */
+#define DBGMCU_CR_DBG_STANDBYD3           DBGMCU_CR_DBG_STANDBYD3_Msk
+#define DBGMCU_CR_DBG_TRACECKEN_Pos       (20U)
+#define DBGMCU_CR_DBG_TRACECKEN_Msk       (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos) /*!< 0x00100000 */
+#define DBGMCU_CR_DBG_TRACECKEN           DBGMCU_CR_DBG_TRACECKEN_Msk
+#define DBGMCU_CR_DBG_CKD1EN_Pos          (21U)
+#define DBGMCU_CR_DBG_CKD1EN_Msk          (0x1UL << DBGMCU_CR_DBG_CKD1EN_Pos)  /*!< 0x00200000 */
+#define DBGMCU_CR_DBG_CKD1EN              DBGMCU_CR_DBG_CKD1EN_Msk
+#define DBGMCU_CR_DBG_CKD3EN_Pos          (22U)
+#define DBGMCU_CR_DBG_CKD3EN_Msk          (0x1UL << DBGMCU_CR_DBG_CKD3EN_Pos)  /*!< 0x00400000 */
+#define DBGMCU_CR_DBG_CKD3EN              DBGMCU_CR_DBG_CKD3EN_Msk
+#define DBGMCU_CR_DBG_TRGOEN_Pos          (28U)
+#define DBGMCU_CR_DBG_TRGOEN_Msk          (0x1UL << DBGMCU_CR_DBG_TRGOEN_Pos)  /*!< 0x10000000 */
+#define DBGMCU_CR_DBG_TRGOEN              DBGMCU_CR_DBG_TRGOEN_Msk
+
+/********************  Bit definition for APB3FZ1 register  ************/
+#define DBGMCU_APB3FZ1_DBG_WWDG1_Pos      (6U)
+#define DBGMCU_APB3FZ1_DBG_WWDG1_Msk      (0x1UL << DBGMCU_APB3FZ1_DBG_WWDG1_Pos) /*!< 0x00000040 */
+#define DBGMCU_APB3FZ1_DBG_WWDG1          DBGMCU_APB3FZ1_DBG_WWDG1_Msk
+/********************  Bit definition for APB1LFZ1 register  ************/
+#define DBGMCU_APB1LFZ1_DBG_TIM2_Pos      (0U)
+#define DBGMCU_APB1LFZ1_DBG_TIM2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1LFZ1_DBG_TIM2          DBGMCU_APB1LFZ1_DBG_TIM2_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM3_Pos      (1U)
+#define DBGMCU_APB1LFZ1_DBG_TIM3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB1LFZ1_DBG_TIM3          DBGMCU_APB1LFZ1_DBG_TIM3_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM4_Pos      (2U)
+#define DBGMCU_APB1LFZ1_DBG_TIM4_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB1LFZ1_DBG_TIM4          DBGMCU_APB1LFZ1_DBG_TIM4_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM5_Pos      (3U)
+#define DBGMCU_APB1LFZ1_DBG_TIM5_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_Pos) /*!< 0x00000008 */
+#define DBGMCU_APB1LFZ1_DBG_TIM5          DBGMCU_APB1LFZ1_DBG_TIM5_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM6_Pos      (4U)
+#define DBGMCU_APB1LFZ1_DBG_TIM6_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB1LFZ1_DBG_TIM6          DBGMCU_APB1LFZ1_DBG_TIM6_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM7_Pos      (5U)
+#define DBGMCU_APB1LFZ1_DBG_TIM7_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB1LFZ1_DBG_TIM7          DBGMCU_APB1LFZ1_DBG_TIM7_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM12_Pos     (6U)
+#define DBGMCU_APB1LFZ1_DBG_TIM12_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_Pos) /*!< 0x00000040 */
+#define DBGMCU_APB1LFZ1_DBG_TIM12         DBGMCU_APB1LFZ1_DBG_TIM12_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM13_Pos     (7U)
+#define DBGMCU_APB1LFZ1_DBG_TIM13_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_Pos) /*!< 0x00000080 */
+#define DBGMCU_APB1LFZ1_DBG_TIM13         DBGMCU_APB1LFZ1_DBG_TIM13_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM14_Pos     (8U)
+#define DBGMCU_APB1LFZ1_DBG_TIM14_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_Pos) /*!< 0x00000100 */
+#define DBGMCU_APB1LFZ1_DBG_TIM14         DBGMCU_APB1LFZ1_DBG_TIM14_Msk
+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos    (9U)
+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos) /*!< 0x00000200 */
+#define DBGMCU_APB1LFZ1_DBG_LPTIM1        DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk
+#define DBGMCU_APB1LFZ1_DBG_I2C1_Pos      (21U)
+#define DBGMCU_APB1LFZ1_DBG_I2C1_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1LFZ1_DBG_I2C1          DBGMCU_APB1LFZ1_DBG_I2C1_Msk
+#define DBGMCU_APB1LFZ1_DBG_I2C2_Pos      (22U)
+#define DBGMCU_APB1LFZ1_DBG_I2C2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1LFZ1_DBG_I2C2          DBGMCU_APB1LFZ1_DBG_I2C2_Msk
+#define DBGMCU_APB1LFZ1_DBG_I2C3_Pos      (23U)
+#define DBGMCU_APB1LFZ1_DBG_I2C3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_Pos) /*!< 0x00800000 */
+#define DBGMCU_APB1LFZ1_DBG_I2C3          DBGMCU_APB1LFZ1_DBG_I2C3_Msk
+
+/********************  Bit definition for APB1HFZ1 register  ************/
+#define DBGMCU_APB1HFZ1_DBG_FDCAN_Pos     (8U)
+#define DBGMCU_APB1HFZ1_DBG_FDCAN_Msk     (0x1UL << DBGMCU_APB1HFZ1_DBG_FDCAN_Pos) /*!< 0x00000100 */
+#define DBGMCU_APB1HFZ1_DBG_FDCAN         DBGMCU_APB1HFZ1_DBG_FDCAN_Msk
+/********************  Bit definition for APB2FZ1 register  ************/
+#define DBGMCU_APB2FZ1_DBG_TIM1_Pos       (0U)
+#define DBGMCU_APB2FZ1_DBG_TIM1_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB2FZ1_DBG_TIM1           DBGMCU_APB2FZ1_DBG_TIM1_Msk
+#define DBGMCU_APB2FZ1_DBG_TIM8_Pos       (1U)
+#define DBGMCU_APB2FZ1_DBG_TIM8_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB2FZ1_DBG_TIM8           DBGMCU_APB2FZ1_DBG_TIM8_Msk
+#define DBGMCU_APB2FZ1_DBG_TIM15_Pos      (16U)
+#define DBGMCU_APB2FZ1_DBG_TIM15_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_Pos) /*!< 0x00010000 */
+#define DBGMCU_APB2FZ1_DBG_TIM15          DBGMCU_APB2FZ1_DBG_TIM15_Msk
+#define DBGMCU_APB2FZ1_DBG_TIM16_Pos      (17U)
+#define DBGMCU_APB2FZ1_DBG_TIM16_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_Pos) /*!< 0x00020000 */
+#define DBGMCU_APB2FZ1_DBG_TIM16          DBGMCU_APB2FZ1_DBG_TIM16_Msk
+#define DBGMCU_APB2FZ1_DBG_TIM17_Pos      (18U)
+#define DBGMCU_APB2FZ1_DBG_TIM17_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_Pos) /*!< 0x00040000 */
+#define DBGMCU_APB2FZ1_DBG_TIM17          DBGMCU_APB2FZ1_DBG_TIM17_Msk
+#define DBGMCU_APB2FZ1_DBG_HRTIM_Pos      (29U)
+#define DBGMCU_APB2FZ1_DBG_HRTIM_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_HRTIM_Pos) /*!< 0x20000000 */
+#define DBGMCU_APB2FZ1_DBG_HRTIM          DBGMCU_APB2FZ1_DBG_HRTIM_Msk
+
+/********************  Bit definition for APB4FZ1 register  ************/
+#define DBGMCU_APB4FZ1_DBG_I2C4_Pos       (7U)
+#define DBGMCU_APB4FZ1_DBG_I2C4_Msk       (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_Pos) /*!< 0x00000080 */
+#define DBGMCU_APB4FZ1_DBG_I2C4           DBGMCU_APB4FZ1_DBG_I2C4_Msk
+#define DBGMCU_APB4FZ1_DBG_LPTIM2_Pos     (9U)
+#define DBGMCU_APB4FZ1_DBG_LPTIM2_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_Pos) /*!< 0x00000200 */
+#define DBGMCU_APB4FZ1_DBG_LPTIM2         DBGMCU_APB4FZ1_DBG_LPTIM2_Msk
+#define DBGMCU_APB4FZ1_DBG_LPTIM3_Pos     (10U)
+#define DBGMCU_APB4FZ1_DBG_LPTIM3_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB4FZ1_DBG_LPTIM3         DBGMCU_APB4FZ1_DBG_LPTIM3_Msk
+#define DBGMCU_APB4FZ1_DBG_LPTIM4_Pos     (11U)
+#define DBGMCU_APB4FZ1_DBG_LPTIM4_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM4_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB4FZ1_DBG_LPTIM4         DBGMCU_APB4FZ1_DBG_LPTIM4_Msk
+#define DBGMCU_APB4FZ1_DBG_LPTIM5_Pos     (12U)
+#define DBGMCU_APB4FZ1_DBG_LPTIM5_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM5_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB4FZ1_DBG_LPTIM5         DBGMCU_APB4FZ1_DBG_LPTIM5_Msk
+#define DBGMCU_APB4FZ1_DBG_RTC_Pos        (16U)
+#define DBGMCU_APB4FZ1_DBG_RTC_Msk        (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_Pos) /*!< 0x00010000 */
+#define DBGMCU_APB4FZ1_DBG_RTC            DBGMCU_APB4FZ1_DBG_RTC_Msk
+#define DBGMCU_APB4FZ1_DBG_IWDG1_Pos      (18U)
+#define DBGMCU_APB4FZ1_DBG_IWDG1_Msk      (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG1_Pos) /*!< 0x00040000 */
+#define DBGMCU_APB4FZ1_DBG_IWDG1          DBGMCU_APB4FZ1_DBG_IWDG1_Msk
+/******************************************************************************/
+/*                                                                            */
+/*                        High Resolution Timer (HRTIM)                       */
+/*                                                                            */
+/******************************************************************************/
+/******************** Master Timer control register ***************************/
+#define HRTIM_MCR_CK_PSC_Pos          (0U)
+#define HRTIM_MCR_CK_PSC_Msk          (0x7UL << HRTIM_MCR_CK_PSC_Pos)          /*!< 0x00000007 */
+#define HRTIM_MCR_CK_PSC              HRTIM_MCR_CK_PSC_Msk                     /*!< Prescaler mask */
+#define HRTIM_MCR_CK_PSC_0            (0x1UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000001 */
+#define HRTIM_MCR_CK_PSC_1            (0x2UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000002 */
+#define HRTIM_MCR_CK_PSC_2            (0x4UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000004 */
+
+#define HRTIM_MCR_CONT_Pos            (3U)
+#define HRTIM_MCR_CONT_Msk            (0x1UL << HRTIM_MCR_CONT_Pos)            /*!< 0x00000008 */
+#define HRTIM_MCR_CONT                HRTIM_MCR_CONT_Msk                       /*!< Continuous mode */
+#define HRTIM_MCR_RETRIG_Pos          (4U)
+#define HRTIM_MCR_RETRIG_Msk          (0x1UL << HRTIM_MCR_RETRIG_Pos)          /*!< 0x00000010 */
+#define HRTIM_MCR_RETRIG              HRTIM_MCR_RETRIG_Msk                     /*!< Rettrigreable mode */
+#define HRTIM_MCR_HALF_Pos            (5U)
+#define HRTIM_MCR_HALF_Msk            (0x1UL << HRTIM_MCR_HALF_Pos)            /*!< 0x00000020 */
+#define HRTIM_MCR_HALF                HRTIM_MCR_HALF_Msk                       /*!< Half mode */
+
+#define HRTIM_MCR_SYNC_IN_Pos         (8U)
+#define HRTIM_MCR_SYNC_IN_Msk         (0x3UL << HRTIM_MCR_SYNC_IN_Pos)         /*!< 0x00000300 */
+#define HRTIM_MCR_SYNC_IN             HRTIM_MCR_SYNC_IN_Msk                    /*!< Synchronization input master */
+#define HRTIM_MCR_SYNC_IN_0           (0x1UL << HRTIM_MCR_SYNC_IN_Pos)          /*!< 0x00000100 */
+#define HRTIM_MCR_SYNC_IN_1           (0x2UL << HRTIM_MCR_SYNC_IN_Pos)          /*!< 0x00000200 */
+#define HRTIM_MCR_SYNCRSTM_Pos        (10U)
+#define HRTIM_MCR_SYNCRSTM_Msk        (0x1UL << HRTIM_MCR_SYNCRSTM_Pos)        /*!< 0x00000400 */
+#define HRTIM_MCR_SYNCRSTM            HRTIM_MCR_SYNCRSTM_Msk                   /*!< Synchronization reset master */
+#define HRTIM_MCR_SYNCSTRTM_Pos       (11U)
+#define HRTIM_MCR_SYNCSTRTM_Msk       (0x1UL << HRTIM_MCR_SYNCSTRTM_Pos)       /*!< 0x00000800 */
+#define HRTIM_MCR_SYNCSTRTM           HRTIM_MCR_SYNCSTRTM_Msk                  /*!< Synchronization start master */
+#define HRTIM_MCR_SYNC_OUT_Pos        (12U)
+#define HRTIM_MCR_SYNC_OUT_Msk        (0x3UL << HRTIM_MCR_SYNC_OUT_Pos)        /*!< 0x00003000 */
+#define HRTIM_MCR_SYNC_OUT            HRTIM_MCR_SYNC_OUT_Msk                   /*!< Synchronization output master */
+#define HRTIM_MCR_SYNC_OUT_0          (0x1UL << HRTIM_MCR_SYNC_OUT_Pos)         /*!< 0x00001000 */
+#define HRTIM_MCR_SYNC_OUT_1          (0x2UL << HRTIM_MCR_SYNC_OUT_Pos)         /*!< 0x00002000 */
+#define HRTIM_MCR_SYNC_SRC_Pos        (14U)
+#define HRTIM_MCR_SYNC_SRC_Msk        (0x3UL << HRTIM_MCR_SYNC_SRC_Pos)        /*!< 0x0000C000 */
+#define HRTIM_MCR_SYNC_SRC            HRTIM_MCR_SYNC_SRC_Msk                   /*!< Synchronization source */
+#define HRTIM_MCR_SYNC_SRC_0          (0x1UL << HRTIM_MCR_SYNC_SRC_Pos)         /*!< 0x00004000 */
+#define HRTIM_MCR_SYNC_SRC_1          (0x2UL << HRTIM_MCR_SYNC_SRC_Pos)         /*!< 0x00008000 */
+
+#define HRTIM_MCR_MCEN_Pos            (16U)
+#define HRTIM_MCR_MCEN_Msk            (0x1UL << HRTIM_MCR_MCEN_Pos)            /*!< 0x00010000 */
+#define HRTIM_MCR_MCEN                HRTIM_MCR_MCEN_Msk                       /*!< Master counter enable */
+#define HRTIM_MCR_TACEN_Pos           (17U)
+#define HRTIM_MCR_TACEN_Msk           (0x1UL << HRTIM_MCR_TACEN_Pos)           /*!< 0x00020000 */
+#define HRTIM_MCR_TACEN               HRTIM_MCR_TACEN_Msk                      /*!< Timer A counter enable */
+#define HRTIM_MCR_TBCEN_Pos           (18U)
+#define HRTIM_MCR_TBCEN_Msk           (0x1UL << HRTIM_MCR_TBCEN_Pos)           /*!< 0x00040000 */
+#define HRTIM_MCR_TBCEN               HRTIM_MCR_TBCEN_Msk                      /*!< Timer B counter enable */
+#define HRTIM_MCR_TCCEN_Pos           (19U)
+#define HRTIM_MCR_TCCEN_Msk           (0x1UL << HRTIM_MCR_TCCEN_Pos)           /*!< 0x00080000 */
+#define HRTIM_MCR_TCCEN               HRTIM_MCR_TCCEN_Msk                      /*!< Timer C counter enable */
+#define HRTIM_MCR_TDCEN_Pos           (20U)
+#define HRTIM_MCR_TDCEN_Msk           (0x1UL << HRTIM_MCR_TDCEN_Pos)           /*!< 0x00100000 */
+#define HRTIM_MCR_TDCEN               HRTIM_MCR_TDCEN_Msk                      /*!< Timer D counter enable */
+#define HRTIM_MCR_TECEN_Pos           (21U)
+#define HRTIM_MCR_TECEN_Msk           (0x1UL << HRTIM_MCR_TECEN_Pos)           /*!< 0x00200000 */
+#define HRTIM_MCR_TECEN               HRTIM_MCR_TECEN_Msk                      /*!< Timer E counter enable */
+
+#define HRTIM_MCR_DACSYNC_Pos         (25U)
+#define HRTIM_MCR_DACSYNC_Msk         (0x3UL << HRTIM_MCR_DACSYNC_Pos)         /*!< 0x06000000 */
+#define HRTIM_MCR_DACSYNC             HRTIM_MCR_DACSYNC_Msk                    /*!< DAC sychronization mask */
+#define HRTIM_MCR_DACSYNC_0           (0x1UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x02000000 */
+#define HRTIM_MCR_DACSYNC_1           (0x2UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x04000000 */
+
+#define HRTIM_MCR_PREEN_Pos           (27U)
+#define HRTIM_MCR_PREEN_Msk           (0x1UL << HRTIM_MCR_PREEN_Pos)           /*!< 0x08000000 */
+#define HRTIM_MCR_PREEN               HRTIM_MCR_PREEN_Msk                      /*!< Master preload enable */
+#define HRTIM_MCR_MREPU_Pos           (29U)
+#define HRTIM_MCR_MREPU_Msk           (0x1UL << HRTIM_MCR_MREPU_Pos)           /*!< 0x20000000 */
+#define HRTIM_MCR_MREPU               HRTIM_MCR_MREPU_Msk                      /*!< Master repetition update */
+
+#define HRTIM_MCR_BRSTDMA_Pos         (30U)
+#define HRTIM_MCR_BRSTDMA_Msk         (0x3UL << HRTIM_MCR_BRSTDMA_Pos)         /*!< 0xC0000000 */
+#define HRTIM_MCR_BRSTDMA             HRTIM_MCR_BRSTDMA_Msk                    /*!< Burst DMA update */
+#define HRTIM_MCR_BRSTDMA_0           (0x1UL << HRTIM_MCR_BRSTDMA_Pos)          /*!< 0x40000000 */
+#define HRTIM_MCR_BRSTDMA_1           (0x2UL << HRTIM_MCR_BRSTDMA_Pos)          /*!< 0x80000000 */
+
+/******************** Master Timer Interrupt status register ******************/
+#define HRTIM_MISR_MCMP1_Pos          (0U)
+#define HRTIM_MISR_MCMP1_Msk          (0x1UL << HRTIM_MISR_MCMP1_Pos)          /*!< 0x00000001 */
+#define HRTIM_MISR_MCMP1              HRTIM_MISR_MCMP1_Msk                     /*!< Master compare 1 interrupt flag */
+#define HRTIM_MISR_MCMP2_Pos          (1U)
+#define HRTIM_MISR_MCMP2_Msk          (0x1UL << HRTIM_MISR_MCMP2_Pos)          /*!< 0x00000002 */
+#define HRTIM_MISR_MCMP2              HRTIM_MISR_MCMP2_Msk                     /*!< Master compare 2 interrupt flag */
+#define HRTIM_MISR_MCMP3_Pos          (2U)
+#define HRTIM_MISR_MCMP3_Msk          (0x1UL << HRTIM_MISR_MCMP3_Pos)          /*!< 0x00000004 */
+#define HRTIM_MISR_MCMP3              HRTIM_MISR_MCMP3_Msk                     /*!< Master compare 3 interrupt flag */
+#define HRTIM_MISR_MCMP4_Pos          (3U)
+#define HRTIM_MISR_MCMP4_Msk          (0x1UL << HRTIM_MISR_MCMP4_Pos)          /*!< 0x00000008 */
+#define HRTIM_MISR_MCMP4              HRTIM_MISR_MCMP4_Msk                     /*!< Master compare 4 interrupt flag */
+#define HRTIM_MISR_MREP_Pos           (4U)
+#define HRTIM_MISR_MREP_Msk           (0x1UL << HRTIM_MISR_MREP_Pos)           /*!< 0x00000010 */
+#define HRTIM_MISR_MREP               HRTIM_MISR_MREP_Msk                      /*!< Master Repetition interrupt flag */
+#define HRTIM_MISR_SYNC_Pos           (5U)
+#define HRTIM_MISR_SYNC_Msk           (0x1UL << HRTIM_MISR_SYNC_Pos)           /*!< 0x00000020 */
+#define HRTIM_MISR_SYNC               HRTIM_MISR_SYNC_Msk                      /*!< Synchronization input interrupt flag */
+#define HRTIM_MISR_MUPD_Pos           (6U)
+#define HRTIM_MISR_MUPD_Msk           (0x1UL << HRTIM_MISR_MUPD_Pos)           /*!< 0x00000040 */
+#define HRTIM_MISR_MUPD               HRTIM_MISR_MUPD_Msk                      /*!< Master update interrupt flag */
+
+/******************** Master Timer Interrupt clear register *******************/
+#define HRTIM_MICR_MCMP1_Pos          (0U)
+#define HRTIM_MICR_MCMP1_Msk          (0x1UL << HRTIM_MICR_MCMP1_Pos)          /*!< 0x00000001 */
+#define HRTIM_MICR_MCMP1              HRTIM_MICR_MCMP1_Msk                     /*!< Master compare 1 interrupt flag clear */
+#define HRTIM_MICR_MCMP2_Pos          (1U)
+#define HRTIM_MICR_MCMP2_Msk          (0x1UL << HRTIM_MICR_MCMP2_Pos)          /*!< 0x00000002 */
+#define HRTIM_MICR_MCMP2              HRTIM_MICR_MCMP2_Msk                     /*!< Master compare 2 interrupt flag clear */
+#define HRTIM_MICR_MCMP3_Pos          (2U)
+#define HRTIM_MICR_MCMP3_Msk          (0x1UL << HRTIM_MICR_MCMP3_Pos)          /*!< 0x00000004 */
+#define HRTIM_MICR_MCMP3              HRTIM_MICR_MCMP3_Msk                     /*!< Master compare 3 interrupt flag clear */
+#define HRTIM_MICR_MCMP4_Pos          (3U)
+#define HRTIM_MICR_MCMP4_Msk          (0x1UL << HRTIM_MICR_MCMP4_Pos)          /*!< 0x00000008 */
+#define HRTIM_MICR_MCMP4              HRTIM_MICR_MCMP4_Msk                     /*!< Master compare 4 interrupt flag clear */
+#define HRTIM_MICR_MREP_Pos           (4U)
+#define HRTIM_MICR_MREP_Msk           (0x1UL << HRTIM_MICR_MREP_Pos)           /*!< 0x00000010 */
+#define HRTIM_MICR_MREP               HRTIM_MICR_MREP_Msk                      /*!< Master Repetition interrupt flag clear */
+#define HRTIM_MICR_SYNC_Pos           (5U)
+#define HRTIM_MICR_SYNC_Msk           (0x1UL << HRTIM_MICR_SYNC_Pos)           /*!< 0x00000020 */
+#define HRTIM_MICR_SYNC               HRTIM_MICR_SYNC_Msk                      /*!< Synchronization input interrupt flag clear */
+#define HRTIM_MICR_MUPD_Pos           (6U)
+#define HRTIM_MICR_MUPD_Msk           (0x1UL << HRTIM_MICR_MUPD_Pos)           /*!< 0x00000040 */
+#define HRTIM_MICR_MUPD               HRTIM_MICR_MUPD_Msk                      /*!< Master update interrupt flag clear */
+
+/******************** Master Timer DMA/Interrupt enable register **************/
+#define HRTIM_MDIER_MCMP1IE_Pos       (0U)
+#define HRTIM_MDIER_MCMP1IE_Msk       (0x1UL << HRTIM_MDIER_MCMP1IE_Pos)       /*!< 0x00000001 */
+#define HRTIM_MDIER_MCMP1IE           HRTIM_MDIER_MCMP1IE_Msk                  /*!< Master compare 1 interrupt enable */
+#define HRTIM_MDIER_MCMP2IE_Pos       (1U)
+#define HRTIM_MDIER_MCMP2IE_Msk       (0x1UL << HRTIM_MDIER_MCMP2IE_Pos)       /*!< 0x00000002 */
+#define HRTIM_MDIER_MCMP2IE           HRTIM_MDIER_MCMP2IE_Msk                  /*!< Master compare 2 interrupt enable */
+#define HRTIM_MDIER_MCMP3IE_Pos       (2U)
+#define HRTIM_MDIER_MCMP3IE_Msk       (0x1UL << HRTIM_MDIER_MCMP3IE_Pos)       /*!< 0x00000004 */
+#define HRTIM_MDIER_MCMP3IE           HRTIM_MDIER_MCMP3IE_Msk                  /*!< Master compare 3 interrupt enable */
+#define HRTIM_MDIER_MCMP4IE_Pos       (3U)
+#define HRTIM_MDIER_MCMP4IE_Msk       (0x1UL << HRTIM_MDIER_MCMP4IE_Pos)       /*!< 0x00000008 */
+#define HRTIM_MDIER_MCMP4IE           HRTIM_MDIER_MCMP4IE_Msk                  /*!< Master compare 4 interrupt enable */
+#define HRTIM_MDIER_MREPIE_Pos        (4U)
+#define HRTIM_MDIER_MREPIE_Msk        (0x1UL << HRTIM_MDIER_MREPIE_Pos)        /*!< 0x00000010 */
+#define HRTIM_MDIER_MREPIE            HRTIM_MDIER_MREPIE_Msk                   /*!< Master Repetition interrupt enable */
+#define HRTIM_MDIER_SYNCIE_Pos        (5U)
+#define HRTIM_MDIER_SYNCIE_Msk        (0x1UL << HRTIM_MDIER_SYNCIE_Pos)        /*!< 0x00000020 */
+#define HRTIM_MDIER_SYNCIE            HRTIM_MDIER_SYNCIE_Msk                   /*!< Synchronization input interrupt enable */
+#define HRTIM_MDIER_MUPDIE_Pos        (6U)
+#define HRTIM_MDIER_MUPDIE_Msk        (0x1UL << HRTIM_MDIER_MUPDIE_Pos)        /*!< 0x00000040 */
+#define HRTIM_MDIER_MUPDIE            HRTIM_MDIER_MUPDIE_Msk                   /*!< Master update interrupt enable */
+
+#define HRTIM_MDIER_MCMP1DE_Pos       (16U)
+#define HRTIM_MDIER_MCMP1DE_Msk       (0x1UL << HRTIM_MDIER_MCMP1DE_Pos)       /*!< 0x00010000 */
+#define HRTIM_MDIER_MCMP1DE           HRTIM_MDIER_MCMP1DE_Msk                  /*!< Master compare 1 DMA enable */
+#define HRTIM_MDIER_MCMP2DE_Pos       (17U)
+#define HRTIM_MDIER_MCMP2DE_Msk       (0x1UL << HRTIM_MDIER_MCMP2DE_Pos)       /*!< 0x00020000 */
+#define HRTIM_MDIER_MCMP2DE           HRTIM_MDIER_MCMP2DE_Msk                  /*!< Master compare 2 DMA enable */
+#define HRTIM_MDIER_MCMP3DE_Pos       (18U)
+#define HRTIM_MDIER_MCMP3DE_Msk       (0x1UL << HRTIM_MDIER_MCMP3DE_Pos)       /*!< 0x00040000 */
+#define HRTIM_MDIER_MCMP3DE           HRTIM_MDIER_MCMP3DE_Msk                  /*!< Master compare 3 DMA enable */
+#define HRTIM_MDIER_MCMP4DE_Pos       (19U)
+#define HRTIM_MDIER_MCMP4DE_Msk       (0x1UL << HRTIM_MDIER_MCMP4DE_Pos)       /*!< 0x00080000 */
+#define HRTIM_MDIER_MCMP4DE           HRTIM_MDIER_MCMP4DE_Msk                  /*!< Master compare 4 DMA enable */
+#define HRTIM_MDIER_MREPDE_Pos        (20U)
+#define HRTIM_MDIER_MREPDE_Msk        (0x1UL << HRTIM_MDIER_MREPDE_Pos)        /*!< 0x00100000 */
+#define HRTIM_MDIER_MREPDE            HRTIM_MDIER_MREPDE_Msk                   /*!< Master Repetition DMA enable */
+#define HRTIM_MDIER_SYNCDE_Pos        (21U)
+#define HRTIM_MDIER_SYNCDE_Msk        (0x1UL << HRTIM_MDIER_SYNCDE_Pos)        /*!< 0x00200000 */
+#define HRTIM_MDIER_SYNCDE            HRTIM_MDIER_SYNCDE_Msk                   /*!< Synchronization input DMA enable */
+#define HRTIM_MDIER_MUPDDE_Pos        (22U)
+#define HRTIM_MDIER_MUPDDE_Msk        (0x1UL << HRTIM_MDIER_MUPDDE_Pos)        /*!< 0x00400000 */
+#define HRTIM_MDIER_MUPDDE            HRTIM_MDIER_MUPDDE_Msk                   /*!< Master update DMA enable */
+
+/*******************  Bit definition for HRTIM_MCNTR register  ****************/
+#define HRTIM_MCNTR_MCNTR_Pos         (0U)
+#define HRTIM_MCNTR_MCNTR_Msk         (0xFFFFUL << HRTIM_MCNTR_MCNTR_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_MCNTR_MCNTR             HRTIM_MCNTR_MCNTR_Msk                    /*!<Counter Value */
+
+/*******************  Bit definition for HRTIM_MPER register  *****************/
+#define HRTIM_MPER_MPER_Pos           (0U)
+#define HRTIM_MPER_MPER_Msk           (0xFFFFUL << HRTIM_MPER_MPER_Pos)        /*!< 0x0000FFFF */
+#define HRTIM_MPER_MPER               HRTIM_MPER_MPER_Msk                      /*!< Period Value */
+
+/*******************  Bit definition for HRTIM_MREP register  *****************/
+#define HRTIM_MREP_MREP_Pos           (0U)
+#define HRTIM_MREP_MREP_Msk           (0xFFUL << HRTIM_MREP_MREP_Pos)          /*!< 0x000000FF */
+#define HRTIM_MREP_MREP               HRTIM_MREP_MREP_Msk                      /*!<Repetition Value */
+
+/*******************  Bit definition for HRTIM_MCMP1R register  *****************/
+#define HRTIM_MCMP1R_MCMP1R_Pos       (0U)
+#define HRTIM_MCMP1R_MCMP1R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP1R_Pos)    /*!< 0x0000FFFF */
+#define HRTIM_MCMP1R_MCMP1R           HRTIM_MCMP1R_MCMP1R_Msk                  /*!<Compare Value */
+
+/*******************  Bit definition for HRTIM_MCMP2R register  *****************/
+#define HRTIM_MCMP1R_MCMP2R_Pos       (0U)
+#define HRTIM_MCMP1R_MCMP2R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP2R_Pos)    /*!< 0x0000FFFF */
+#define HRTIM_MCMP1R_MCMP2R           HRTIM_MCMP1R_MCMP2R_Msk                  /*!<Compare Value */
+
+/*******************  Bit definition for HRTIM_MCMP3R register  *****************/
+#define HRTIM_MCMP1R_MCMP3R_Pos       (0U)
+#define HRTIM_MCMP1R_MCMP3R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP3R_Pos)    /*!< 0x0000FFFF */
+#define HRTIM_MCMP1R_MCMP3R           HRTIM_MCMP1R_MCMP3R_Msk                  /*!<Compare Value */
+
+/*******************  Bit definition for HRTIM_MCMP4R register  *****************/
+#define HRTIM_MCMP1R_MCMP4R_Pos       (0U)
+#define HRTIM_MCMP1R_MCMP4R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP4R_Pos)    /*!< 0x0000FFFF */
+#define HRTIM_MCMP1R_MCMP4R           HRTIM_MCMP1R_MCMP4R_Msk                  /*!<Compare Value */
+
+/******************** Slave control register **********************************/
+#define HRTIM_TIMCR_CK_PSC_Pos        (0U)
+#define HRTIM_TIMCR_CK_PSC_Msk        (0x7UL << HRTIM_TIMCR_CK_PSC_Pos)        /*!< 0x00000007 */
+#define HRTIM_TIMCR_CK_PSC            HRTIM_TIMCR_CK_PSC_Msk                   /*!< Slave prescaler mask*/
+#define HRTIM_TIMCR_CK_PSC_0          (0x1UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000001 */
+#define HRTIM_TIMCR_CK_PSC_1          (0x2UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000002 */
+#define HRTIM_TIMCR_CK_PSC_2          (0x4UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000004 */
+
+#define HRTIM_TIMCR_CONT_Pos          (3U)
+#define HRTIM_TIMCR_CONT_Msk          (0x1UL << HRTIM_TIMCR_CONT_Pos)          /*!< 0x00000008 */
+#define HRTIM_TIMCR_CONT              HRTIM_TIMCR_CONT_Msk                     /*!< Slave continuous mode */
+#define HRTIM_TIMCR_RETRIG_Pos        (4U)
+#define HRTIM_TIMCR_RETRIG_Msk        (0x1UL << HRTIM_TIMCR_RETRIG_Pos)        /*!< 0x00000010 */
+#define HRTIM_TIMCR_RETRIG            HRTIM_TIMCR_RETRIG_Msk                   /*!< Slave Retrigreable mode */
+#define HRTIM_TIMCR_HALF_Pos          (5U)
+#define HRTIM_TIMCR_HALF_Msk          (0x1UL << HRTIM_TIMCR_HALF_Pos)          /*!< 0x00000020 */
+#define HRTIM_TIMCR_HALF              HRTIM_TIMCR_HALF_Msk                     /*!< Slave Half mode */
+#define HRTIM_TIMCR_PSHPLL_Pos        (6U)
+#define HRTIM_TIMCR_PSHPLL_Msk        (0x1UL << HRTIM_TIMCR_PSHPLL_Pos)        /*!< 0x00000040 */
+#define HRTIM_TIMCR_PSHPLL            HRTIM_TIMCR_PSHPLL_Msk                   /*!< Slave push-pull mode */
+
+#define HRTIM_TIMCR_SYNCRST_Pos       (10U)
+#define HRTIM_TIMCR_SYNCRST_Msk       (0x1UL << HRTIM_TIMCR_SYNCRST_Pos)       /*!< 0x00000400 */
+#define HRTIM_TIMCR_SYNCRST           HRTIM_TIMCR_SYNCRST_Msk                  /*!< Slave synchronization resets */
+#define HRTIM_TIMCR_SYNCSTRT_Pos      (11U)
+#define HRTIM_TIMCR_SYNCSTRT_Msk      (0x1UL << HRTIM_TIMCR_SYNCSTRT_Pos)      /*!< 0x00000800 */
+#define HRTIM_TIMCR_SYNCSTRT          HRTIM_TIMCR_SYNCSTRT_Msk                 /*!< Slave synchronization starts */
+
+#define HRTIM_TIMCR_DELCMP2_Pos       (12U)
+#define HRTIM_TIMCR_DELCMP2_Msk       (0x3UL << HRTIM_TIMCR_DELCMP2_Pos)       /*!< 0x00003000 */
+#define HRTIM_TIMCR_DELCMP2           HRTIM_TIMCR_DELCMP2_Msk                  /*!< Slave delayed compartor 2 mode mask */
+#define HRTIM_TIMCR_DELCMP2_0         (0x1UL << HRTIM_TIMCR_DELCMP2_Pos)        /*!< 0x00001000 */
+#define HRTIM_TIMCR_DELCMP2_1         (0x2UL << HRTIM_TIMCR_DELCMP2_Pos)        /*!< 0x00002000 */
+#define HRTIM_TIMCR_DELCMP4_Pos       (14U)
+#define HRTIM_TIMCR_DELCMP4_Msk       (0x3UL << HRTIM_TIMCR_DELCMP4_Pos)       /*!< 0x0000C000 */
+#define HRTIM_TIMCR_DELCMP4           HRTIM_TIMCR_DELCMP4_Msk                  /*!< Slave delayed compartor 4 mode mask */
+#define HRTIM_TIMCR_DELCMP4_0         (0x1UL << HRTIM_TIMCR_DELCMP4_Pos)        /*!< 0x00004000 */
+#define HRTIM_TIMCR_DELCMP4_1         (0x2UL << HRTIM_TIMCR_DELCMP4_Pos)        /*!< 0x00008000 */
+
+#define HRTIM_TIMCR_TREPU_Pos         (17U)
+#define HRTIM_TIMCR_TREPU_Msk         (0x1UL << HRTIM_TIMCR_TREPU_Pos)         /*!< 0x00020000 */
+#define HRTIM_TIMCR_TREPU             HRTIM_TIMCR_TREPU_Msk                    /*!< Slave repetition update */
+#define HRTIM_TIMCR_TRSTU_Pos         (18U)
+#define HRTIM_TIMCR_TRSTU_Msk         (0x1UL << HRTIM_TIMCR_TRSTU_Pos)         /*!< 0x00040000 */
+#define HRTIM_TIMCR_TRSTU             HRTIM_TIMCR_TRSTU_Msk                    /*!< Slave reset update */
+#define HRTIM_TIMCR_TAU_Pos           (19U)
+#define HRTIM_TIMCR_TAU_Msk           (0x1UL << HRTIM_TIMCR_TAU_Pos)           /*!< 0x00080000 */
+#define HRTIM_TIMCR_TAU               HRTIM_TIMCR_TAU_Msk                      /*!< Slave Timer A update reserved for TIM A */
+#define HRTIM_TIMCR_TBU_Pos           (20U)
+#define HRTIM_TIMCR_TBU_Msk           (0x1UL << HRTIM_TIMCR_TBU_Pos)           /*!< 0x00100000 */
+#define HRTIM_TIMCR_TBU               HRTIM_TIMCR_TBU_Msk                      /*!< Slave Timer B update reserved for TIM B */
+#define HRTIM_TIMCR_TCU_Pos           (21U)
+#define HRTIM_TIMCR_TCU_Msk           (0x1UL << HRTIM_TIMCR_TCU_Pos)           /*!< 0x00200000 */
+#define HRTIM_TIMCR_TCU               HRTIM_TIMCR_TCU_Msk                      /*!< Slave Timer C update reserved for TIM C */
+#define HRTIM_TIMCR_TDU_Pos           (22U)
+#define HRTIM_TIMCR_TDU_Msk           (0x1UL << HRTIM_TIMCR_TDU_Pos)           /*!< 0x00400000 */
+#define HRTIM_TIMCR_TDU               HRTIM_TIMCR_TDU_Msk                      /*!< Slave Timer D update reserved for TIM D */
+#define HRTIM_TIMCR_TEU_Pos           (23U)
+#define HRTIM_TIMCR_TEU_Msk           (0x1UL << HRTIM_TIMCR_TEU_Pos)           /*!< 0x00800000 */
+#define HRTIM_TIMCR_TEU               HRTIM_TIMCR_TEU_Msk                      /*!< Slave Timer E update reserved for TIM E */
+#define HRTIM_TIMCR_MSTU_Pos          (24U)
+#define HRTIM_TIMCR_MSTU_Msk          (0x1UL << HRTIM_TIMCR_MSTU_Pos)          /*!< 0x01000000 */
+#define HRTIM_TIMCR_MSTU              HRTIM_TIMCR_MSTU_Msk                     /*!< Master Update */
+
+#define HRTIM_TIMCR_DACSYNC_Pos       (25U)
+#define HRTIM_TIMCR_DACSYNC_Msk       (0x3UL << HRTIM_TIMCR_DACSYNC_Pos)       /*!< 0x06000000 */
+#define HRTIM_TIMCR_DACSYNC           HRTIM_TIMCR_DACSYNC_Msk                  /*!< DAC sychronization mask */
+#define HRTIM_TIMCR_DACSYNC_0         (0x1UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x02000000 */
+#define HRTIM_TIMCR_DACSYNC_1         (0x2UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x04000000 */
+#define HRTIM_TIMCR_PREEN_Pos         (27U)
+#define HRTIM_TIMCR_PREEN_Msk         (0x1UL << HRTIM_TIMCR_PREEN_Pos)         /*!< 0x08000000 */
+#define HRTIM_TIMCR_PREEN             HRTIM_TIMCR_PREEN_Msk                    /*!< Slave preload enable */
+
+#define HRTIM_TIMCR_UPDGAT_Pos        (28U)
+#define HRTIM_TIMCR_UPDGAT_Msk        (0xFUL << HRTIM_TIMCR_UPDGAT_Pos)        /*!< 0xF0000000 */
+#define HRTIM_TIMCR_UPDGAT            HRTIM_TIMCR_UPDGAT_Msk                   /*!< Slave update gating mask */
+#define HRTIM_TIMCR_UPDGAT_0          (0x1UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x10000000 */
+#define HRTIM_TIMCR_UPDGAT_1          (0x2UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x20000000 */
+#define HRTIM_TIMCR_UPDGAT_2          (0x4UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x40000000 */
+#define HRTIM_TIMCR_UPDGAT_3          (0x8UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x80000000 */
+
+/******************** Slave Interrupt status register **************************/
+#define HRTIM_TIMISR_CMP1_Pos         (0U)
+#define HRTIM_TIMISR_CMP1_Msk         (0x1UL << HRTIM_TIMISR_CMP1_Pos)         /*!< 0x00000001 */
+#define HRTIM_TIMISR_CMP1             HRTIM_TIMISR_CMP1_Msk                    /*!< Slave compare 1 interrupt flag */
+#define HRTIM_TIMISR_CMP2_Pos         (1U)
+#define HRTIM_TIMISR_CMP2_Msk         (0x1UL << HRTIM_TIMISR_CMP2_Pos)         /*!< 0x00000002 */
+#define HRTIM_TIMISR_CMP2             HRTIM_TIMISR_CMP2_Msk                    /*!< Slave compare 2 interrupt flag */
+#define HRTIM_TIMISR_CMP3_Pos         (2U)
+#define HRTIM_TIMISR_CMP3_Msk         (0x1UL << HRTIM_TIMISR_CMP3_Pos)         /*!< 0x00000004 */
+#define HRTIM_TIMISR_CMP3             HRTIM_TIMISR_CMP3_Msk                    /*!< Slave compare 3 interrupt flag */
+#define HRTIM_TIMISR_CMP4_Pos         (3U)
+#define HRTIM_TIMISR_CMP4_Msk         (0x1UL << HRTIM_TIMISR_CMP4_Pos)         /*!< 0x00000008 */
+#define HRTIM_TIMISR_CMP4             HRTIM_TIMISR_CMP4_Msk                    /*!< Slave compare 4 interrupt flag */
+#define HRTIM_TIMISR_REP_Pos          (4U)
+#define HRTIM_TIMISR_REP_Msk          (0x1UL << HRTIM_TIMISR_REP_Pos)          /*!< 0x00000010 */
+#define HRTIM_TIMISR_REP              HRTIM_TIMISR_REP_Msk                     /*!< Slave repetition interrupt flag */
+#define HRTIM_TIMISR_UPD_Pos          (6U)
+#define HRTIM_TIMISR_UPD_Msk          (0x1UL << HRTIM_TIMISR_UPD_Pos)          /*!< 0x00000040 */
+#define HRTIM_TIMISR_UPD              HRTIM_TIMISR_UPD_Msk                     /*!< Slave update interrupt flag */
+#define HRTIM_TIMISR_CPT1_Pos         (7U)
+#define HRTIM_TIMISR_CPT1_Msk         (0x1UL << HRTIM_TIMISR_CPT1_Pos)         /*!< 0x00000080 */
+#define HRTIM_TIMISR_CPT1             HRTIM_TIMISR_CPT1_Msk                    /*!< Slave capture 1 interrupt flag */
+#define HRTIM_TIMISR_CPT2_Pos         (8U)
+#define HRTIM_TIMISR_CPT2_Msk         (0x1UL << HRTIM_TIMISR_CPT2_Pos)         /*!< 0x00000100 */
+#define HRTIM_TIMISR_CPT2             HRTIM_TIMISR_CPT2_Msk                    /*!< Slave capture 2 interrupt flag */
+#define HRTIM_TIMISR_SET1_Pos         (9U)
+#define HRTIM_TIMISR_SET1_Msk         (0x1UL << HRTIM_TIMISR_SET1_Pos)         /*!< 0x00000200 */
+#define HRTIM_TIMISR_SET1             HRTIM_TIMISR_SET1_Msk                    /*!< Slave output 1 set interrupt flag */
+#define HRTIM_TIMISR_RST1_Pos         (10U)
+#define HRTIM_TIMISR_RST1_Msk         (0x1UL << HRTIM_TIMISR_RST1_Pos)         /*!< 0x00000400 */
+#define HRTIM_TIMISR_RST1             HRTIM_TIMISR_RST1_Msk                    /*!< Slave output 1 reset interrupt flag */
+#define HRTIM_TIMISR_SET2_Pos         (11U)
+#define HRTIM_TIMISR_SET2_Msk         (0x1UL << HRTIM_TIMISR_SET2_Pos)         /*!< 0x00000800 */
+#define HRTIM_TIMISR_SET2             HRTIM_TIMISR_SET2_Msk                    /*!< Slave output 2 set interrupt flag */
+#define HRTIM_TIMISR_RST2_Pos         (12U)
+#define HRTIM_TIMISR_RST2_Msk         (0x1UL << HRTIM_TIMISR_RST2_Pos)         /*!< 0x00001000 */
+#define HRTIM_TIMISR_RST2             HRTIM_TIMISR_RST2_Msk                    /*!< Slave output 2 reset interrupt flag */
+#define HRTIM_TIMISR_RST_Pos          (13U)
+#define HRTIM_TIMISR_RST_Msk          (0x1UL << HRTIM_TIMISR_RST_Pos)          /*!< 0x00002000 */
+#define HRTIM_TIMISR_RST              HRTIM_TIMISR_RST_Msk                     /*!< Slave reset interrupt flag */
+#define HRTIM_TIMISR_DLYPRT_Pos       (14U)
+#define HRTIM_TIMISR_DLYPRT_Msk       (0x1UL << HRTIM_TIMISR_DLYPRT_Pos)       /*!< 0x00004000 */
+#define HRTIM_TIMISR_DLYPRT           HRTIM_TIMISR_DLYPRT_Msk                  /*!< Slave output 1 delay protection interrupt flag */
+#define HRTIM_TIMISR_CPPSTAT_Pos      (16U)
+#define HRTIM_TIMISR_CPPSTAT_Msk      (0x1UL << HRTIM_TIMISR_CPPSTAT_Pos)      /*!< 0x00010000 */
+#define HRTIM_TIMISR_CPPSTAT          HRTIM_TIMISR_CPPSTAT_Msk                 /*!< Slave current push-pull flag */
+#define HRTIM_TIMISR_IPPSTAT_Pos      (17U)
+#define HRTIM_TIMISR_IPPSTAT_Msk      (0x1UL << HRTIM_TIMISR_IPPSTAT_Pos)      /*!< 0x00020000 */
+#define HRTIM_TIMISR_IPPSTAT          HRTIM_TIMISR_IPPSTAT_Msk                 /*!< Slave idle push-pull flag */
+#define HRTIM_TIMISR_O1STAT_Pos       (18U)
+#define HRTIM_TIMISR_O1STAT_Msk       (0x1UL << HRTIM_TIMISR_O1STAT_Pos)       /*!< 0x00040000 */
+#define HRTIM_TIMISR_O1STAT           HRTIM_TIMISR_O1STAT_Msk                  /*!< Slave output 1 state flag */
+#define HRTIM_TIMISR_O2STAT_Pos       (19U)
+#define HRTIM_TIMISR_O2STAT_Msk       (0x1UL << HRTIM_TIMISR_O2STAT_Pos)       /*!< 0x00080000 */
+#define HRTIM_TIMISR_O2STAT           HRTIM_TIMISR_O2STAT_Msk                  /*!< Slave output 2 state flag */
+#define HRTIM_TIMISR_O1CPY_Pos        (20U)
+#define HRTIM_TIMISR_O1CPY_Msk        (0x1UL << HRTIM_TIMISR_O1CPY_Pos)        /*!< 0x00100000 */
+#define HRTIM_TIMISR_O1CPY            HRTIM_TIMISR_O1CPY_Msk                   /*!< Slave output 1 copy flag */
+#define HRTIM_TIMISR_O2CPY_Pos        (21U)
+#define HRTIM_TIMISR_O2CPY_Msk        (0x1UL << HRTIM_TIMISR_O2CPY_Pos)        /*!< 0x00200000 */
+#define HRTIM_TIMISR_O2CPY            HRTIM_TIMISR_O2CPY_Msk                   /*!< Slave output 2 copy flag */
+
+/******************** Slave Interrupt clear register **************************/
+#define HRTIM_TIMICR_CMP1C_Pos        (0U)
+#define HRTIM_TIMICR_CMP1C_Msk        (0x1UL << HRTIM_TIMICR_CMP1C_Pos)        /*!< 0x00000001 */
+#define HRTIM_TIMICR_CMP1C            HRTIM_TIMICR_CMP1C_Msk                   /*!< Slave compare 1 clear flag */
+#define HRTIM_TIMICR_CMP2C_Pos        (1U)
+#define HRTIM_TIMICR_CMP2C_Msk        (0x1UL << HRTIM_TIMICR_CMP2C_Pos)        /*!< 0x00000002 */
+#define HRTIM_TIMICR_CMP2C            HRTIM_TIMICR_CMP2C_Msk                   /*!< Slave compare 2 clear flag */
+#define HRTIM_TIMICR_CMP3C_Pos        (2U)
+#define HRTIM_TIMICR_CMP3C_Msk        (0x1UL << HRTIM_TIMICR_CMP3C_Pos)        /*!< 0x00000004 */
+#define HRTIM_TIMICR_CMP3C            HRTIM_TIMICR_CMP3C_Msk                   /*!< Slave compare 3 clear flag */
+#define HRTIM_TIMICR_CMP4C_Pos        (3U)
+#define HRTIM_TIMICR_CMP4C_Msk        (0x1UL << HRTIM_TIMICR_CMP4C_Pos)        /*!< 0x00000008 */
+#define HRTIM_TIMICR_CMP4C            HRTIM_TIMICR_CMP4C_Msk                   /*!< Slave compare 4 clear flag */
+#define HRTIM_TIMICR_REPC_Pos         (4U)
+#define HRTIM_TIMICR_REPC_Msk         (0x1UL << HRTIM_TIMICR_REPC_Pos)         /*!< 0x00000010 */
+#define HRTIM_TIMICR_REPC             HRTIM_TIMICR_REPC_Msk                    /*!< Slave repetition clear flag */
+#define HRTIM_TIMICR_UPDC_Pos         (6U)
+#define HRTIM_TIMICR_UPDC_Msk         (0x1UL << HRTIM_TIMICR_UPDC_Pos)         /*!< 0x00000040 */
+#define HRTIM_TIMICR_UPDC             HRTIM_TIMICR_UPDC_Msk                    /*!< Slave update clear flag */
+#define HRTIM_TIMICR_CPT1C_Pos        (7U)
+#define HRTIM_TIMICR_CPT1C_Msk        (0x1UL << HRTIM_TIMICR_CPT1C_Pos)        /*!< 0x00000080 */
+#define HRTIM_TIMICR_CPT1C            HRTIM_TIMICR_CPT1C_Msk                   /*!< Slave capture 1 clear flag */
+#define HRTIM_TIMICR_CPT2C_Pos        (8U)
+#define HRTIM_TIMICR_CPT2C_Msk        (0x1UL << HRTIM_TIMICR_CPT2C_Pos)        /*!< 0x00000100 */
+#define HRTIM_TIMICR_CPT2C            HRTIM_TIMICR_CPT2C_Msk                   /*!< Slave capture 2 clear flag */
+#define HRTIM_TIMICR_SET1C_Pos        (9U)
+#define HRTIM_TIMICR_SET1C_Msk        (0x1UL << HRTIM_TIMICR_SET1C_Pos)        /*!< 0x00000200 */
+#define HRTIM_TIMICR_SET1C            HRTIM_TIMICR_SET1C_Msk                   /*!< Slave output 1 set clear flag */
+#define HRTIM_TIMICR_RST1C_Pos        (10U)
+#define HRTIM_TIMICR_RST1C_Msk        (0x1UL << HRTIM_TIMICR_RST1C_Pos)        /*!< 0x00000400 */
+#define HRTIM_TIMICR_RST1C            HRTIM_TIMICR_RST1C_Msk                   /*!< Slave output 1 reset clear flag */
+#define HRTIM_TIMICR_SET2C_Pos        (11U)
+#define HRTIM_TIMICR_SET2C_Msk        (0x1UL << HRTIM_TIMICR_SET2C_Pos)        /*!< 0x00000800 */
+#define HRTIM_TIMICR_SET2C            HRTIM_TIMICR_SET2C_Msk                   /*!< Slave output 2 set clear flag */
+#define HRTIM_TIMICR_RST2C_Pos        (12U)
+#define HRTIM_TIMICR_RST2C_Msk        (0x1UL << HRTIM_TIMICR_RST2C_Pos)        /*!< 0x00001000 */
+#define HRTIM_TIMICR_RST2C            HRTIM_TIMICR_RST2C_Msk                   /*!< Slave output 2 reset clear flag */
+#define HRTIM_TIMICR_RSTC_Pos         (13U)
+#define HRTIM_TIMICR_RSTC_Msk         (0x1UL << HRTIM_TIMICR_RSTC_Pos)         /*!< 0x00002000 */
+#define HRTIM_TIMICR_RSTC             HRTIM_TIMICR_RSTC_Msk                    /*!< Slave reset clear flag */
+#define HRTIM_TIMICR_DLYPRTC_Pos      (14U)
+#define HRTIM_TIMICR_DLYPRTC_Msk      (0x1UL << HRTIM_TIMICR_DLYPRTC_Pos)      /*!< 0x00004000 */
+#define HRTIM_TIMICR_DLYPRTC          HRTIM_TIMICR_DLYPRTC_Msk                 /*!< Slave output 1 delay protection clear flag */
+
+/******************** Slave DMA/Interrupt enable register *********************/
+#define HRTIM_TIMDIER_CMP1IE_Pos      (0U)
+#define HRTIM_TIMDIER_CMP1IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP1IE_Pos)      /*!< 0x00000001 */
+#define HRTIM_TIMDIER_CMP1IE          HRTIM_TIMDIER_CMP1IE_Msk                 /*!< Slave compare 1 interrupt enable */
+#define HRTIM_TIMDIER_CMP2IE_Pos      (1U)
+#define HRTIM_TIMDIER_CMP2IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP2IE_Pos)      /*!< 0x00000002 */
+#define HRTIM_TIMDIER_CMP2IE          HRTIM_TIMDIER_CMP2IE_Msk                 /*!< Slave compare 2 interrupt enable */
+#define HRTIM_TIMDIER_CMP3IE_Pos      (2U)
+#define HRTIM_TIMDIER_CMP3IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP3IE_Pos)      /*!< 0x00000004 */
+#define HRTIM_TIMDIER_CMP3IE          HRTIM_TIMDIER_CMP3IE_Msk                 /*!< Slave compare 3 interrupt enable */
+#define HRTIM_TIMDIER_CMP4IE_Pos      (3U)
+#define HRTIM_TIMDIER_CMP4IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP4IE_Pos)      /*!< 0x00000008 */
+#define HRTIM_TIMDIER_CMP4IE          HRTIM_TIMDIER_CMP4IE_Msk                 /*!< Slave compare 4 interrupt enable */
+#define HRTIM_TIMDIER_REPIE_Pos       (4U)
+#define HRTIM_TIMDIER_REPIE_Msk       (0x1UL << HRTIM_TIMDIER_REPIE_Pos)       /*!< 0x00000010 */
+#define HRTIM_TIMDIER_REPIE           HRTIM_TIMDIER_REPIE_Msk                  /*!< Slave repetition interrupt enable */
+#define HRTIM_TIMDIER_UPDIE_Pos       (6U)
+#define HRTIM_TIMDIER_UPDIE_Msk       (0x1UL << HRTIM_TIMDIER_UPDIE_Pos)       /*!< 0x00000040 */
+#define HRTIM_TIMDIER_UPDIE           HRTIM_TIMDIER_UPDIE_Msk                  /*!< Slave update interrupt enable */
+#define HRTIM_TIMDIER_CPT1IE_Pos      (7U)
+#define HRTIM_TIMDIER_CPT1IE_Msk      (0x1UL << HRTIM_TIMDIER_CPT1IE_Pos)      /*!< 0x00000080 */
+#define HRTIM_TIMDIER_CPT1IE          HRTIM_TIMDIER_CPT1IE_Msk                 /*!< Slave capture 1 interrupt enable */
+#define HRTIM_TIMDIER_CPT2IE_Pos      (8U)
+#define HRTIM_TIMDIER_CPT2IE_Msk      (0x1UL << HRTIM_TIMDIER_CPT2IE_Pos)      /*!< 0x00000100 */
+#define HRTIM_TIMDIER_CPT2IE          HRTIM_TIMDIER_CPT2IE_Msk                 /*!< Slave capture 2 interrupt enable */
+#define HRTIM_TIMDIER_SET1IE_Pos      (9U)
+#define HRTIM_TIMDIER_SET1IE_Msk      (0x1UL << HRTIM_TIMDIER_SET1IE_Pos)      /*!< 0x00000200 */
+#define HRTIM_TIMDIER_SET1IE          HRTIM_TIMDIER_SET1IE_Msk                 /*!< Slave output 1 set interrupt enable */
+#define HRTIM_TIMDIER_RST1IE_Pos      (10U)
+#define HRTIM_TIMDIER_RST1IE_Msk      (0x1UL << HRTIM_TIMDIER_RST1IE_Pos)      /*!< 0x00000400 */
+#define HRTIM_TIMDIER_RST1IE          HRTIM_TIMDIER_RST1IE_Msk                 /*!< Slave output 1 reset interrupt enable */
+#define HRTIM_TIMDIER_SET2IE_Pos      (11U)
+#define HRTIM_TIMDIER_SET2IE_Msk      (0x1UL << HRTIM_TIMDIER_SET2IE_Pos)      /*!< 0x00000800 */
+#define HRTIM_TIMDIER_SET2IE          HRTIM_TIMDIER_SET2IE_Msk                 /*!< Slave output 2 set interrupt enable */
+#define HRTIM_TIMDIER_RST2IE_Pos      (12U)
+#define HRTIM_TIMDIER_RST2IE_Msk      (0x1UL << HRTIM_TIMDIER_RST2IE_Pos)      /*!< 0x00001000 */
+#define HRTIM_TIMDIER_RST2IE          HRTIM_TIMDIER_RST2IE_Msk                 /*!< Slave output 2 reset interrupt enable */
+#define HRTIM_TIMDIER_RSTIE_Pos       (13U)
+#define HRTIM_TIMDIER_RSTIE_Msk       (0x1UL << HRTIM_TIMDIER_RSTIE_Pos)       /*!< 0x00002000 */
+#define HRTIM_TIMDIER_RSTIE           HRTIM_TIMDIER_RSTIE_Msk                  /*!< Slave reset interrupt enable */
+#define HRTIM_TIMDIER_DLYPRTIE_Pos    (14U)
+#define HRTIM_TIMDIER_DLYPRTIE_Msk    (0x1UL << HRTIM_TIMDIER_DLYPRTIE_Pos)    /*!< 0x00004000 */
+#define HRTIM_TIMDIER_DLYPRTIE        HRTIM_TIMDIER_DLYPRTIE_Msk               /*!< Slave delay protection interrupt enable */
+
+#define HRTIM_TIMDIER_CMP1DE_Pos      (16U)
+#define HRTIM_TIMDIER_CMP1DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP1DE_Pos)      /*!< 0x00010000 */
+#define HRTIM_TIMDIER_CMP1DE          HRTIM_TIMDIER_CMP1DE_Msk                 /*!< Slave compare 1 request enable */
+#define HRTIM_TIMDIER_CMP2DE_Pos      (17U)
+#define HRTIM_TIMDIER_CMP2DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP2DE_Pos)      /*!< 0x00020000 */
+#define HRTIM_TIMDIER_CMP2DE          HRTIM_TIMDIER_CMP2DE_Msk                 /*!< Slave compare 2 request enable */
+#define HRTIM_TIMDIER_CMP3DE_Pos      (18U)
+#define HRTIM_TIMDIER_CMP3DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP3DE_Pos)      /*!< 0x00040000 */
+#define HRTIM_TIMDIER_CMP3DE          HRTIM_TIMDIER_CMP3DE_Msk                 /*!< Slave compare 3 request enable */
+#define HRTIM_TIMDIER_CMP4DE_Pos      (19U)
+#define HRTIM_TIMDIER_CMP4DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP4DE_Pos)      /*!< 0x00080000 */
+#define HRTIM_TIMDIER_CMP4DE          HRTIM_TIMDIER_CMP4DE_Msk                 /*!< Slave compare 4 request enable */
+#define HRTIM_TIMDIER_REPDE_Pos       (20U)
+#define HRTIM_TIMDIER_REPDE_Msk       (0x1UL << HRTIM_TIMDIER_REPDE_Pos)       /*!< 0x00100000 */
+#define HRTIM_TIMDIER_REPDE           HRTIM_TIMDIER_REPDE_Msk                  /*!< Slave repetition request enable */
+#define HRTIM_TIMDIER_UPDDE_Pos       (22U)
+#define HRTIM_TIMDIER_UPDDE_Msk       (0x1UL << HRTIM_TIMDIER_UPDDE_Pos)       /*!< 0x00400000 */
+#define HRTIM_TIMDIER_UPDDE           HRTIM_TIMDIER_UPDDE_Msk                  /*!< Slave update request enable */
+#define HRTIM_TIMDIER_CPT1DE_Pos      (23U)
+#define HRTIM_TIMDIER_CPT1DE_Msk      (0x1UL << HRTIM_TIMDIER_CPT1DE_Pos)      /*!< 0x00800000 */
+#define HRTIM_TIMDIER_CPT1DE          HRTIM_TIMDIER_CPT1DE_Msk                 /*!< Slave capture 1 request enable */
+#define HRTIM_TIMDIER_CPT2DE_Pos      (24U)
+#define HRTIM_TIMDIER_CPT2DE_Msk      (0x1UL << HRTIM_TIMDIER_CPT2DE_Pos)      /*!< 0x01000000 */
+#define HRTIM_TIMDIER_CPT2DE          HRTIM_TIMDIER_CPT2DE_Msk                 /*!< Slave capture 2 request enable */
+#define HRTIM_TIMDIER_SET1DE_Pos      (25U)
+#define HRTIM_TIMDIER_SET1DE_Msk      (0x1UL << HRTIM_TIMDIER_SET1DE_Pos)      /*!< 0x02000000 */
+#define HRTIM_TIMDIER_SET1DE          HRTIM_TIMDIER_SET1DE_Msk                 /*!< Slave output 1 set request enable */
+#define HRTIM_TIMDIER_RST1DE_Pos      (26U)
+#define HRTIM_TIMDIER_RST1DE_Msk      (0x1UL << HRTIM_TIMDIER_RST1DE_Pos)      /*!< 0x04000000 */
+#define HRTIM_TIMDIER_RST1DE          HRTIM_TIMDIER_RST1DE_Msk                 /*!< Slave output 1 reset request enable */
+#define HRTIM_TIMDIER_SET2DE_Pos      (27U)
+#define HRTIM_TIMDIER_SET2DE_Msk      (0x1UL << HRTIM_TIMDIER_SET2DE_Pos)      /*!< 0x08000000 */
+#define HRTIM_TIMDIER_SET2DE          HRTIM_TIMDIER_SET2DE_Msk                 /*!< Slave output 2 set request enable */
+#define HRTIM_TIMDIER_RST2DE_Pos      (28U)
+#define HRTIM_TIMDIER_RST2DE_Msk      (0x1UL << HRTIM_TIMDIER_RST2DE_Pos)      /*!< 0x10000000 */
+#define HRTIM_TIMDIER_RST2DE          HRTIM_TIMDIER_RST2DE_Msk                 /*!< Slave output 2 reset request enable */
+#define HRTIM_TIMDIER_RSTDE_Pos       (29U)
+#define HRTIM_TIMDIER_RSTDE_Msk       (0x1UL << HRTIM_TIMDIER_RSTDE_Pos)       /*!< 0x20000000 */
+#define HRTIM_TIMDIER_RSTDE           HRTIM_TIMDIER_RSTDE_Msk                  /*!< Slave reset request enable */
+#define HRTIM_TIMDIER_DLYPRTDE_Pos    (30U)
+#define HRTIM_TIMDIER_DLYPRTDE_Msk    (0x1UL << HRTIM_TIMDIER_DLYPRTDE_Pos)    /*!< 0x40000000 */
+#define HRTIM_TIMDIER_DLYPRTDE        HRTIM_TIMDIER_DLYPRTDE_Msk               /*!< Slavedelay protection request enable */
+
+/******************  Bit definition for HRTIM_CNTR register  ****************/
+#define HRTIM_CNTR_CNTR_Pos           (0U)
+#define HRTIM_CNTR_CNTR_Msk           (0xFFFFUL << HRTIM_CNTR_CNTR_Pos)        /*!< 0x0000FFFF */
+#define HRTIM_CNTR_CNTR               HRTIM_CNTR_CNTR_Msk                      /*!< Counter Value */
+
+/*******************  Bit definition for HRTIM_PER register  *****************/
+#define HRTIM_PER_PER_Pos             (0U)
+#define HRTIM_PER_PER_Msk             (0xFFFFUL << HRTIM_PER_PER_Pos)          /*!< 0x0000FFFF */
+#define HRTIM_PER_PER                 HRTIM_PER_PER_Msk                        /*!< Period Value */
+
+/*******************  Bit definition for HRTIM_REP register  *****************/
+#define HRTIM_REP_REP_Pos             (0U)
+#define HRTIM_REP_REP_Msk             (0xFFUL << HRTIM_REP_REP_Pos)            /*!< 0x000000FF */
+#define HRTIM_REP_REP                 HRTIM_REP_REP_Msk                        /*!< Repetition Value */
+
+/*******************  Bit definition for HRTIM_CMP1R register  *****************/
+#define HRTIM_CMP1R_CMP1R_Pos         (0U)
+#define HRTIM_CMP1R_CMP1R_Msk         (0xFFFFUL << HRTIM_CMP1R_CMP1R_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_CMP1R_CMP1R             HRTIM_CMP1R_CMP1R_Msk                    /*!< Compare Value */
+
+/*******************  Bit definition for HRTIM_CMP1CR register  *****************/
+#define HRTIM_CMP1CR_CMP1CR_Pos       (0U)
+#define HRTIM_CMP1CR_CMP1CR_Msk       (0xFFFFFFFFUL << HRTIM_CMP1CR_CMP1CR_Pos) /*!< 0xFFFFFFFF */
+#define HRTIM_CMP1CR_CMP1CR           HRTIM_CMP1CR_CMP1CR_Msk                  /*!< Compare Value */
+
+/*******************  Bit definition for HRTIM_CMP2R register  *****************/
+#define HRTIM_CMP2R_CMP2R_Pos         (0U)
+#define HRTIM_CMP2R_CMP2R_Msk         (0xFFFFUL << HRTIM_CMP2R_CMP2R_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_CMP2R_CMP2R             HRTIM_CMP2R_CMP2R_Msk                    /*!< Compare Value */
+
+/*******************  Bit definition for HRTIM_CMP3R register  *****************/
+#define HRTIM_CMP3R_CMP3R_Pos         (0U)
+#define HRTIM_CMP3R_CMP3R_Msk         (0xFFFFUL << HRTIM_CMP3R_CMP3R_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_CMP3R_CMP3R             HRTIM_CMP3R_CMP3R_Msk                    /*!< Compare Value */
+
+/*******************  Bit definition for HRTIM_CMP4R register  *****************/
+#define HRTIM_CMP4R_CMP4R_Pos         (0U)
+#define HRTIM_CMP4R_CMP4R_Msk         (0xFFFFUL << HRTIM_CMP4R_CMP4R_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_CMP4R_CMP4R             HRTIM_CMP4R_CMP4R_Msk                    /*!< Compare Value */
+
+/*******************  Bit definition for HRTIM_CPT1R register  ****************/
+#define HRTIM_CPT1R_CPT1R_Pos         (0U)
+#define HRTIM_CPT1R_CPT1R_Msk         (0xFFFFUL << HRTIM_CPT1R_CPT1R_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_CPT1R_CPT1R             HRTIM_CPT1R_CPT1R_Msk                    /*!< Capture Value */
+
+/*******************  Bit definition for HRTIM_CPT2R register  ****************/
+#define HRTIM_CPT2R_CPT2R_Pos         (0U)
+#define HRTIM_CPT2R_CPT2R_Msk         (0xFFFFUL << HRTIM_CPT2R_CPT2R_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_CPT2R_CPT2R             HRTIM_CPT2R_CPT2R_Msk                    /*!< Capture Value */
+
+/******************** Bit definition for Slave Deadtime register **************/
+#define HRTIM_DTR_DTR_Pos             (0U)
+#define HRTIM_DTR_DTR_Msk             (0x1FFUL << HRTIM_DTR_DTR_Pos)           /*!< 0x000001FF */
+#define HRTIM_DTR_DTR                 HRTIM_DTR_DTR_Msk                        /*!< Dead time rising value */
+#define HRTIM_DTR_DTR_0               (0x001UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000001 */
+#define HRTIM_DTR_DTR_1               (0x002UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000002 */
+#define HRTIM_DTR_DTR_2               (0x004UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000004 */
+#define HRTIM_DTR_DTR_3               (0x008UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000008 */
+#define HRTIM_DTR_DTR_4               (0x010UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000010 */
+#define HRTIM_DTR_DTR_5               (0x020UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000020 */
+#define HRTIM_DTR_DTR_6               (0x040UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000040 */
+#define HRTIM_DTR_DTR_7               (0x080UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000080 */
+#define HRTIM_DTR_DTR_8               (0x100UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000100 */
+#define HRTIM_DTR_SDTR_Pos            (9U)
+#define HRTIM_DTR_SDTR_Msk            (0x1UL << HRTIM_DTR_SDTR_Pos)            /*!< 0x00000200 */
+#define HRTIM_DTR_SDTR                HRTIM_DTR_SDTR_Msk                       /*!< Sign dead time rising value */
+#define HRTIM_DTR_DTPRSC_Pos          (10U)
+#define HRTIM_DTR_DTPRSC_Msk          (0x7UL << HRTIM_DTR_DTPRSC_Pos)          /*!< 0x00001C00 */
+#define HRTIM_DTR_DTPRSC              HRTIM_DTR_DTPRSC_Msk                     /*!< Dead time prescaler */
+#define HRTIM_DTR_DTPRSC_0            (0x1UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00000400 */
+#define HRTIM_DTR_DTPRSC_1            (0x2UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00000800 */
+#define HRTIM_DTR_DTPRSC_2            (0x4UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00001000 */
+#define HRTIM_DTR_DTRSLK_Pos          (14U)
+#define HRTIM_DTR_DTRSLK_Msk          (0x1UL << HRTIM_DTR_DTRSLK_Pos)          /*!< 0x00004000 */
+#define HRTIM_DTR_DTRSLK              HRTIM_DTR_DTRSLK_Msk                     /*!< Dead time rising sign lock */
+#define HRTIM_DTR_DTRLK_Pos           (15U)
+#define HRTIM_DTR_DTRLK_Msk           (0x1UL << HRTIM_DTR_DTRLK_Pos)           /*!< 0x00008000 */
+#define HRTIM_DTR_DTRLK               HRTIM_DTR_DTRLK_Msk                      /*!< Dead time rising lock */
+#define HRTIM_DTR_DTF_Pos             (16U)
+#define HRTIM_DTR_DTF_Msk             (0x1FFUL << HRTIM_DTR_DTF_Pos)           /*!< 0x01FF0000 */
+#define HRTIM_DTR_DTF                 HRTIM_DTR_DTF_Msk                        /*!< Dead time falling value */
+#define HRTIM_DTR_DTF_0               (0x001UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00010000 */
+#define HRTIM_DTR_DTF_1               (0x002UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00020000 */
+#define HRTIM_DTR_DTF_2               (0x004UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00040000 */
+#define HRTIM_DTR_DTF_3               (0x008UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00080000 */
+#define HRTIM_DTR_DTF_4               (0x010UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00100000 */
+#define HRTIM_DTR_DTF_5               (0x020UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00200000 */
+#define HRTIM_DTR_DTF_6               (0x040UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00400000 */
+#define HRTIM_DTR_DTF_7               (0x080UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00800000 */
+#define HRTIM_DTR_DTF_8               (0x100UL << HRTIM_DTR_DTF_Pos)            /*!< 0x01000000 */
+#define HRTIM_DTR_SDTF_Pos            (25U)
+#define HRTIM_DTR_SDTF_Msk            (0x1UL << HRTIM_DTR_SDTF_Pos)            /*!< 0x02000000 */
+#define HRTIM_DTR_SDTF                HRTIM_DTR_SDTF_Msk                       /*!< Sign dead time falling value */
+#define HRTIM_DTR_DTFSLK_Pos          (30U)
+#define HRTIM_DTR_DTFSLK_Msk          (0x1UL << HRTIM_DTR_DTFSLK_Pos)          /*!< 0x40000000 */
+#define HRTIM_DTR_DTFSLK              HRTIM_DTR_DTFSLK_Msk                     /*!< Dead time falling sign lock */
+#define HRTIM_DTR_DTFLK_Pos           (31U)
+#define HRTIM_DTR_DTFLK_Msk           (0x1UL << HRTIM_DTR_DTFLK_Pos)           /*!< 0x80000000 */
+#define HRTIM_DTR_DTFLK               HRTIM_DTR_DTFLK_Msk                      /*!< Dead time falling lock */
+
+/**** Bit definition for Slave Output 1 set register **************************/
+#define HRTIM_SET1R_SST_Pos           (0U)
+#define HRTIM_SET1R_SST_Msk           (0x1UL << HRTIM_SET1R_SST_Pos)           /*!< 0x00000001 */
+#define HRTIM_SET1R_SST               HRTIM_SET1R_SST_Msk                      /*!< software set trigger */
+#define HRTIM_SET1R_RESYNC_Pos        (1U)
+#define HRTIM_SET1R_RESYNC_Msk        (0x1UL << HRTIM_SET1R_RESYNC_Pos)        /*!< 0x00000002 */
+#define HRTIM_SET1R_RESYNC            HRTIM_SET1R_RESYNC_Msk                   /*!< Timer A resynchronization */
+#define HRTIM_SET1R_PER_Pos           (2U)
+#define HRTIM_SET1R_PER_Msk           (0x1UL << HRTIM_SET1R_PER_Pos)           /*!< 0x00000004 */
+#define HRTIM_SET1R_PER               HRTIM_SET1R_PER_Msk                      /*!< Timer A period */
+#define HRTIM_SET1R_CMP1_Pos          (3U)
+#define HRTIM_SET1R_CMP1_Msk          (0x1UL << HRTIM_SET1R_CMP1_Pos)          /*!< 0x00000008 */
+#define HRTIM_SET1R_CMP1              HRTIM_SET1R_CMP1_Msk                     /*!< Timer A compare 1 */
+#define HRTIM_SET1R_CMP2_Pos          (4U)
+#define HRTIM_SET1R_CMP2_Msk          (0x1UL << HRTIM_SET1R_CMP2_Pos)          /*!< 0x00000010 */
+#define HRTIM_SET1R_CMP2              HRTIM_SET1R_CMP2_Msk                     /*!< Timer A compare 2 */
+#define HRTIM_SET1R_CMP3_Pos          (5U)
+#define HRTIM_SET1R_CMP3_Msk          (0x1UL << HRTIM_SET1R_CMP3_Pos)          /*!< 0x00000020 */
+#define HRTIM_SET1R_CMP3              HRTIM_SET1R_CMP3_Msk                     /*!< Timer A compare 3 */
+#define HRTIM_SET1R_CMP4_Pos          (6U)
+#define HRTIM_SET1R_CMP4_Msk          (0x1UL << HRTIM_SET1R_CMP4_Pos)          /*!< 0x00000040 */
+#define HRTIM_SET1R_CMP4              HRTIM_SET1R_CMP4_Msk                     /*!< Timer A compare 4 */
+
+#define HRTIM_SET1R_MSTPER_Pos        (7U)
+#define HRTIM_SET1R_MSTPER_Msk        (0x1UL << HRTIM_SET1R_MSTPER_Pos)        /*!< 0x00000080 */
+#define HRTIM_SET1R_MSTPER            HRTIM_SET1R_MSTPER_Msk                   /*!< Master period */
+#define HRTIM_SET1R_MSTCMP1_Pos       (8U)
+#define HRTIM_SET1R_MSTCMP1_Msk       (0x1UL << HRTIM_SET1R_MSTCMP1_Pos)       /*!< 0x00000100 */
+#define HRTIM_SET1R_MSTCMP1           HRTIM_SET1R_MSTCMP1_Msk                  /*!< Master compare 1 */
+#define HRTIM_SET1R_MSTCMP2_Pos       (9U)
+#define HRTIM_SET1R_MSTCMP2_Msk       (0x1UL << HRTIM_SET1R_MSTCMP2_Pos)       /*!< 0x00000200 */
+#define HRTIM_SET1R_MSTCMP2           HRTIM_SET1R_MSTCMP2_Msk                  /*!< Master compare 2 */
+#define HRTIM_SET1R_MSTCMP3_Pos       (10U)
+#define HRTIM_SET1R_MSTCMP3_Msk       (0x1UL << HRTIM_SET1R_MSTCMP3_Pos)       /*!< 0x00000400 */
+#define HRTIM_SET1R_MSTCMP3           HRTIM_SET1R_MSTCMP3_Msk                  /*!< Master compare 3 */
+#define HRTIM_SET1R_MSTCMP4_Pos       (11U)
+#define HRTIM_SET1R_MSTCMP4_Msk       (0x1UL << HRTIM_SET1R_MSTCMP4_Pos)       /*!< 0x00000800 */
+#define HRTIM_SET1R_MSTCMP4           HRTIM_SET1R_MSTCMP4_Msk                  /*!< Master compare 4 */
+
+#define HRTIM_SET1R_TIMEVNT1_Pos      (12U)
+#define HRTIM_SET1R_TIMEVNT1_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT1_Pos)      /*!< 0x00001000 */
+#define HRTIM_SET1R_TIMEVNT1          HRTIM_SET1R_TIMEVNT1_Msk                 /*!< Timer event 1 */
+#define HRTIM_SET1R_TIMEVNT2_Pos      (13U)
+#define HRTIM_SET1R_TIMEVNT2_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT2_Pos)      /*!< 0x00002000 */
+#define HRTIM_SET1R_TIMEVNT2          HRTIM_SET1R_TIMEVNT2_Msk                 /*!< Timer event 2 */
+#define HRTIM_SET1R_TIMEVNT3_Pos      (14U)
+#define HRTIM_SET1R_TIMEVNT3_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT3_Pos)      /*!< 0x00004000 */
+#define HRTIM_SET1R_TIMEVNT3          HRTIM_SET1R_TIMEVNT3_Msk                 /*!< Timer event 3 */
+#define HRTIM_SET1R_TIMEVNT4_Pos      (15U)
+#define HRTIM_SET1R_TIMEVNT4_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT4_Pos)      /*!< 0x00008000 */
+#define HRTIM_SET1R_TIMEVNT4          HRTIM_SET1R_TIMEVNT4_Msk                 /*!< Timer event 4 */
+#define HRTIM_SET1R_TIMEVNT5_Pos      (16U)
+#define HRTIM_SET1R_TIMEVNT5_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT5_Pos)      /*!< 0x00010000 */
+#define HRTIM_SET1R_TIMEVNT5          HRTIM_SET1R_TIMEVNT5_Msk                 /*!< Timer event 5 */
+#define HRTIM_SET1R_TIMEVNT6_Pos      (17U)
+#define HRTIM_SET1R_TIMEVNT6_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT6_Pos)      /*!< 0x00020000 */
+#define HRTIM_SET1R_TIMEVNT6          HRTIM_SET1R_TIMEVNT6_Msk                 /*!< Timer event 6 */
+#define HRTIM_SET1R_TIMEVNT7_Pos      (18U)
+#define HRTIM_SET1R_TIMEVNT7_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT7_Pos)      /*!< 0x00040000 */
+#define HRTIM_SET1R_TIMEVNT7          HRTIM_SET1R_TIMEVNT7_Msk                 /*!< Timer event 7 */
+#define HRTIM_SET1R_TIMEVNT8_Pos      (19U)
+#define HRTIM_SET1R_TIMEVNT8_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT8_Pos)      /*!< 0x00080000 */
+#define HRTIM_SET1R_TIMEVNT8          HRTIM_SET1R_TIMEVNT8_Msk                 /*!< Timer event 8 */
+#define HRTIM_SET1R_TIMEVNT9_Pos      (20U)
+#define HRTIM_SET1R_TIMEVNT9_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT9_Pos)      /*!< 0x00100000 */
+#define HRTIM_SET1R_TIMEVNT9          HRTIM_SET1R_TIMEVNT9_Msk                 /*!< Timer event 9 */
+
+#define HRTIM_SET1R_EXTVNT1_Pos       (21U)
+#define HRTIM_SET1R_EXTVNT1_Msk       (0x1UL << HRTIM_SET1R_EXTVNT1_Pos)       /*!< 0x00200000 */
+#define HRTIM_SET1R_EXTVNT1           HRTIM_SET1R_EXTVNT1_Msk                  /*!< External event 1 */
+#define HRTIM_SET1R_EXTVNT2_Pos       (22U)
+#define HRTIM_SET1R_EXTVNT2_Msk       (0x1UL << HRTIM_SET1R_EXTVNT2_Pos)       /*!< 0x00400000 */
+#define HRTIM_SET1R_EXTVNT2           HRTIM_SET1R_EXTVNT2_Msk                  /*!< External event 2 */
+#define HRTIM_SET1R_EXTVNT3_Pos       (23U)
+#define HRTIM_SET1R_EXTVNT3_Msk       (0x1UL << HRTIM_SET1R_EXTVNT3_Pos)       /*!< 0x00800000 */
+#define HRTIM_SET1R_EXTVNT3           HRTIM_SET1R_EXTVNT3_Msk                  /*!< External event 3 */
+#define HRTIM_SET1R_EXTVNT4_Pos       (24U)
+#define HRTIM_SET1R_EXTVNT4_Msk       (0x1UL << HRTIM_SET1R_EXTVNT4_Pos)       /*!< 0x01000000 */
+#define HRTIM_SET1R_EXTVNT4           HRTIM_SET1R_EXTVNT4_Msk                  /*!< External event 4 */
+#define HRTIM_SET1R_EXTVNT5_Pos       (25U)
+#define HRTIM_SET1R_EXTVNT5_Msk       (0x1UL << HRTIM_SET1R_EXTVNT5_Pos)       /*!< 0x02000000 */
+#define HRTIM_SET1R_EXTVNT5           HRTIM_SET1R_EXTVNT5_Msk                  /*!< External event 5 */
+#define HRTIM_SET1R_EXTVNT6_Pos       (26U)
+#define HRTIM_SET1R_EXTVNT6_Msk       (0x1UL << HRTIM_SET1R_EXTVNT6_Pos)       /*!< 0x04000000 */
+#define HRTIM_SET1R_EXTVNT6           HRTIM_SET1R_EXTVNT6_Msk                  /*!< External event 6 */
+#define HRTIM_SET1R_EXTVNT7_Pos       (27U)
+#define HRTIM_SET1R_EXTVNT7_Msk       (0x1UL << HRTIM_SET1R_EXTVNT7_Pos)       /*!< 0x08000000 */
+#define HRTIM_SET1R_EXTVNT7           HRTIM_SET1R_EXTVNT7_Msk                  /*!< External event 7 */
+#define HRTIM_SET1R_EXTVNT8_Pos       (28U)
+#define HRTIM_SET1R_EXTVNT8_Msk       (0x1UL << HRTIM_SET1R_EXTVNT8_Pos)       /*!< 0x10000000 */
+#define HRTIM_SET1R_EXTVNT8           HRTIM_SET1R_EXTVNT8_Msk                  /*!< External event 8 */
+#define HRTIM_SET1R_EXTVNT9_Pos       (29U)
+#define HRTIM_SET1R_EXTVNT9_Msk       (0x1UL << HRTIM_SET1R_EXTVNT9_Pos)       /*!< 0x20000000 */
+#define HRTIM_SET1R_EXTVNT9           HRTIM_SET1R_EXTVNT9_Msk                  /*!< External event 9 */
+#define HRTIM_SET1R_EXTVNT10_Pos      (30U)
+#define HRTIM_SET1R_EXTVNT10_Msk      (0x1UL << HRTIM_SET1R_EXTVNT10_Pos)      /*!< 0x40000000 */
+#define HRTIM_SET1R_EXTVNT10          HRTIM_SET1R_EXTVNT10_Msk                 /*!< External event 10 */
+
+#define HRTIM_SET1R_UPDATE_Pos        (31U)
+#define HRTIM_SET1R_UPDATE_Msk        (0x1UL << HRTIM_SET1R_UPDATE_Pos)        /*!< 0x80000000 */
+#define HRTIM_SET1R_UPDATE            HRTIM_SET1R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */
+
+/**** Bit definition for Slave Output 1 reset register ************************/
+#define HRTIM_RST1R_SRT_Pos           (0U)
+#define HRTIM_RST1R_SRT_Msk           (0x1UL << HRTIM_RST1R_SRT_Pos)           /*!< 0x00000001 */
+#define HRTIM_RST1R_SRT               HRTIM_RST1R_SRT_Msk                      /*!< software reset trigger */
+#define HRTIM_RST1R_RESYNC_Pos        (1U)
+#define HRTIM_RST1R_RESYNC_Msk        (0x1UL << HRTIM_RST1R_RESYNC_Pos)        /*!< 0x00000002 */
+#define HRTIM_RST1R_RESYNC            HRTIM_RST1R_RESYNC_Msk                   /*!< Timer A resynchronization */
+#define HRTIM_RST1R_PER_Pos           (2U)
+#define HRTIM_RST1R_PER_Msk           (0x1UL << HRTIM_RST1R_PER_Pos)           /*!< 0x00000004 */
+#define HRTIM_RST1R_PER               HRTIM_RST1R_PER_Msk                      /*!< Timer A period */
+#define HRTIM_RST1R_CMP1_Pos          (3U)
+#define HRTIM_RST1R_CMP1_Msk          (0x1UL << HRTIM_RST1R_CMP1_Pos)          /*!< 0x00000008 */
+#define HRTIM_RST1R_CMP1              HRTIM_RST1R_CMP1_Msk                     /*!< Timer A compare 1 */
+#define HRTIM_RST1R_CMP2_Pos          (4U)
+#define HRTIM_RST1R_CMP2_Msk          (0x1UL << HRTIM_RST1R_CMP2_Pos)          /*!< 0x00000010 */
+#define HRTIM_RST1R_CMP2              HRTIM_RST1R_CMP2_Msk                     /*!< Timer A compare 2 */
+#define HRTIM_RST1R_CMP3_Pos          (5U)
+#define HRTIM_RST1R_CMP3_Msk          (0x1UL << HRTIM_RST1R_CMP3_Pos)          /*!< 0x00000020 */
+#define HRTIM_RST1R_CMP3              HRTIM_RST1R_CMP3_Msk                     /*!< Timer A compare 3 */
+#define HRTIM_RST1R_CMP4_Pos          (6U)
+#define HRTIM_RST1R_CMP4_Msk          (0x1UL << HRTIM_RST1R_CMP4_Pos)          /*!< 0x00000040 */
+#define HRTIM_RST1R_CMP4              HRTIM_RST1R_CMP4_Msk                     /*!< Timer A compare 4 */
+
+#define HRTIM_RST1R_MSTPER_Pos        (7U)
+#define HRTIM_RST1R_MSTPER_Msk        (0x1UL << HRTIM_RST1R_MSTPER_Pos)        /*!< 0x00000080 */
+#define HRTIM_RST1R_MSTPER            HRTIM_RST1R_MSTPER_Msk                   /*!< Master period */
+#define HRTIM_RST1R_MSTCMP1_Pos       (8U)
+#define HRTIM_RST1R_MSTCMP1_Msk       (0x1UL << HRTIM_RST1R_MSTCMP1_Pos)       /*!< 0x00000100 */
+#define HRTIM_RST1R_MSTCMP1           HRTIM_RST1R_MSTCMP1_Msk                  /*!< Master compare 1 */
+#define HRTIM_RST1R_MSTCMP2_Pos       (9U)
+#define HRTIM_RST1R_MSTCMP2_Msk       (0x1UL << HRTIM_RST1R_MSTCMP2_Pos)       /*!< 0x00000200 */
+#define HRTIM_RST1R_MSTCMP2           HRTIM_RST1R_MSTCMP2_Msk                  /*!< Master compare 2 */
+#define HRTIM_RST1R_MSTCMP3_Pos       (10U)
+#define HRTIM_RST1R_MSTCMP3_Msk       (0x1UL << HRTIM_RST1R_MSTCMP3_Pos)       /*!< 0x00000400 */
+#define HRTIM_RST1R_MSTCMP3           HRTIM_RST1R_MSTCMP3_Msk                  /*!< Master compare 3 */
+#define HRTIM_RST1R_MSTCMP4_Pos       (11U)
+#define HRTIM_RST1R_MSTCMP4_Msk       (0x1UL << HRTIM_RST1R_MSTCMP4_Pos)       /*!< 0x00000800 */
+#define HRTIM_RST1R_MSTCMP4           HRTIM_RST1R_MSTCMP4_Msk                  /*!< Master compare 4 */
+
+#define HRTIM_RST1R_TIMEVNT1_Pos      (12U)
+#define HRTIM_RST1R_TIMEVNT1_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT1_Pos)      /*!< 0x00001000 */
+#define HRTIM_RST1R_TIMEVNT1          HRTIM_RST1R_TIMEVNT1_Msk                 /*!< Timer event 1 */
+#define HRTIM_RST1R_TIMEVNT2_Pos      (13U)
+#define HRTIM_RST1R_TIMEVNT2_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT2_Pos)      /*!< 0x00002000 */
+#define HRTIM_RST1R_TIMEVNT2          HRTIM_RST1R_TIMEVNT2_Msk                 /*!< Timer event 2 */
+#define HRTIM_RST1R_TIMEVNT3_Pos      (14U)
+#define HRTIM_RST1R_TIMEVNT3_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT3_Pos)      /*!< 0x00004000 */
+#define HRTIM_RST1R_TIMEVNT3          HRTIM_RST1R_TIMEVNT3_Msk                 /*!< Timer event 3 */
+#define HRTIM_RST1R_TIMEVNT4_Pos      (15U)
+#define HRTIM_RST1R_TIMEVNT4_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT4_Pos)      /*!< 0x00008000 */
+#define HRTIM_RST1R_TIMEVNT4          HRTIM_RST1R_TIMEVNT4_Msk                 /*!< Timer event 4 */
+#define HRTIM_RST1R_TIMEVNT5_Pos      (16U)
+#define HRTIM_RST1R_TIMEVNT5_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT5_Pos)      /*!< 0x00010000 */
+#define HRTIM_RST1R_TIMEVNT5          HRTIM_RST1R_TIMEVNT5_Msk                 /*!< Timer event 5 */
+#define HRTIM_RST1R_TIMEVNT6_Pos      (17U)
+#define HRTIM_RST1R_TIMEVNT6_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT6_Pos)      /*!< 0x00020000 */
+#define HRTIM_RST1R_TIMEVNT6          HRTIM_RST1R_TIMEVNT6_Msk                 /*!< Timer event 6 */
+#define HRTIM_RST1R_TIMEVNT7_Pos      (18U)
+#define HRTIM_RST1R_TIMEVNT7_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT7_Pos)      /*!< 0x00040000 */
+#define HRTIM_RST1R_TIMEVNT7          HRTIM_RST1R_TIMEVNT7_Msk                 /*!< Timer event 7 */
+#define HRTIM_RST1R_TIMEVNT8_Pos      (19U)
+#define HRTIM_RST1R_TIMEVNT8_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT8_Pos)      /*!< 0x00080000 */
+#define HRTIM_RST1R_TIMEVNT8          HRTIM_RST1R_TIMEVNT8_Msk                 /*!< Timer event 8 */
+#define HRTIM_RST1R_TIMEVNT9_Pos      (20U)
+#define HRTIM_RST1R_TIMEVNT9_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT9_Pos)      /*!< 0x00100000 */
+#define HRTIM_RST1R_TIMEVNT9          HRTIM_RST1R_TIMEVNT9_Msk                 /*!< Timer event 9 */
+
+#define HRTIM_RST1R_EXTVNT1_Pos       (21U)
+#define HRTIM_RST1R_EXTVNT1_Msk       (0x1UL << HRTIM_RST1R_EXTVNT1_Pos)       /*!< 0x00200000 */
+#define HRTIM_RST1R_EXTVNT1           HRTIM_RST1R_EXTVNT1_Msk                  /*!< External event 1 */
+#define HRTIM_RST1R_EXTVNT2_Pos       (22U)
+#define HRTIM_RST1R_EXTVNT2_Msk       (0x1UL << HRTIM_RST1R_EXTVNT2_Pos)       /*!< 0x00400000 */
+#define HRTIM_RST1R_EXTVNT2           HRTIM_RST1R_EXTVNT2_Msk                  /*!< External event 2 */
+#define HRTIM_RST1R_EXTVNT3_Pos       (23U)
+#define HRTIM_RST1R_EXTVNT3_Msk       (0x1UL << HRTIM_RST1R_EXTVNT3_Pos)       /*!< 0x00800000 */
+#define HRTIM_RST1R_EXTVNT3           HRTIM_RST1R_EXTVNT3_Msk                  /*!< External event 3 */
+#define HRTIM_RST1R_EXTVNT4_Pos       (24U)
+#define HRTIM_RST1R_EXTVNT4_Msk       (0x1UL << HRTIM_RST1R_EXTVNT4_Pos)       /*!< 0x01000000 */
+#define HRTIM_RST1R_EXTVNT4           HRTIM_RST1R_EXTVNT4_Msk                  /*!< External event 4 */
+#define HRTIM_RST1R_EXTVNT5_Pos       (25U)
+#define HRTIM_RST1R_EXTVNT5_Msk       (0x1UL << HRTIM_RST1R_EXTVNT5_Pos)       /*!< 0x02000000 */
+#define HRTIM_RST1R_EXTVNT5           HRTIM_RST1R_EXTVNT5_Msk                  /*!< External event 5 */
+#define HRTIM_RST1R_EXTVNT6_Pos       (26U)
+#define HRTIM_RST1R_EXTVNT6_Msk       (0x1UL << HRTIM_RST1R_EXTVNT6_Pos)       /*!< 0x04000000 */
+#define HRTIM_RST1R_EXTVNT6           HRTIM_RST1R_EXTVNT6_Msk                  /*!< External event 6 */
+#define HRTIM_RST1R_EXTVNT7_Pos       (27U)
+#define HRTIM_RST1R_EXTVNT7_Msk       (0x1UL << HRTIM_RST1R_EXTVNT7_Pos)       /*!< 0x08000000 */
+#define HRTIM_RST1R_EXTVNT7           HRTIM_RST1R_EXTVNT7_Msk                  /*!< External event 7 */
+#define HRTIM_RST1R_EXTVNT8_Pos       (28U)
+#define HRTIM_RST1R_EXTVNT8_Msk       (0x1UL << HRTIM_RST1R_EXTVNT8_Pos)       /*!< 0x10000000 */
+#define HRTIM_RST1R_EXTVNT8           HRTIM_RST1R_EXTVNT8_Msk                  /*!< External event 8 */
+#define HRTIM_RST1R_EXTVNT9_Pos       (29U)
+#define HRTIM_RST1R_EXTVNT9_Msk       (0x1UL << HRTIM_RST1R_EXTVNT9_Pos)       /*!< 0x20000000 */
+#define HRTIM_RST1R_EXTVNT9           HRTIM_RST1R_EXTVNT9_Msk                  /*!< External event 9 */
+#define HRTIM_RST1R_EXTVNT10_Pos      (30U)
+#define HRTIM_RST1R_EXTVNT10_Msk      (0x1UL << HRTIM_RST1R_EXTVNT10_Pos)      /*!< 0x40000000 */
+#define HRTIM_RST1R_EXTVNT10          HRTIM_RST1R_EXTVNT10_Msk                 /*!< External event 10 */
+
+#define HRTIM_RST1R_UPDATE_Pos        (31U)
+#define HRTIM_RST1R_UPDATE_Msk        (0x1UL << HRTIM_RST1R_UPDATE_Pos)        /*!< 0x80000000 */
+#define HRTIM_RST1R_UPDATE            HRTIM_RST1R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */
+
+
+/**** Bit definition for Slave Output 2 set register **************************/
+#define HRTIM_SET2R_SST_Pos           (0U)
+#define HRTIM_SET2R_SST_Msk           (0x1UL << HRTIM_SET2R_SST_Pos)           /*!< 0x00000001 */
+#define HRTIM_SET2R_SST               HRTIM_SET2R_SST_Msk                      /*!< software set trigger */
+#define HRTIM_SET2R_RESYNC_Pos        (1U)
+#define HRTIM_SET2R_RESYNC_Msk        (0x1UL << HRTIM_SET2R_RESYNC_Pos)        /*!< 0x00000002 */
+#define HRTIM_SET2R_RESYNC            HRTIM_SET2R_RESYNC_Msk                   /*!< Timer A resynchronization */
+#define HRTIM_SET2R_PER_Pos           (2U)
+#define HRTIM_SET2R_PER_Msk           (0x1UL << HRTIM_SET2R_PER_Pos)           /*!< 0x00000004 */
+#define HRTIM_SET2R_PER               HRTIM_SET2R_PER_Msk                      /*!< Timer A period */
+#define HRTIM_SET2R_CMP1_Pos          (3U)
+#define HRTIM_SET2R_CMP1_Msk          (0x1UL << HRTIM_SET2R_CMP1_Pos)          /*!< 0x00000008 */
+#define HRTIM_SET2R_CMP1              HRTIM_SET2R_CMP1_Msk                     /*!< Timer A compare 1 */
+#define HRTIM_SET2R_CMP2_Pos          (4U)
+#define HRTIM_SET2R_CMP2_Msk          (0x1UL << HRTIM_SET2R_CMP2_Pos)          /*!< 0x00000010 */
+#define HRTIM_SET2R_CMP2              HRTIM_SET2R_CMP2_Msk                     /*!< Timer A compare 2 */
+#define HRTIM_SET2R_CMP3_Pos          (5U)
+#define HRTIM_SET2R_CMP3_Msk          (0x1UL << HRTIM_SET2R_CMP3_Pos)          /*!< 0x00000020 */
+#define HRTIM_SET2R_CMP3              HRTIM_SET2R_CMP3_Msk                     /*!< Timer A compare 3 */
+#define HRTIM_SET2R_CMP4_Pos          (6U)
+#define HRTIM_SET2R_CMP4_Msk          (0x1UL << HRTIM_SET2R_CMP4_Pos)          /*!< 0x00000040 */
+#define HRTIM_SET2R_CMP4              HRTIM_SET2R_CMP4_Msk                     /*!< Timer A compare 4 */
+
+#define HRTIM_SET2R_MSTPER_Pos        (7U)
+#define HRTIM_SET2R_MSTPER_Msk        (0x1UL << HRTIM_SET2R_MSTPER_Pos)        /*!< 0x00000080 */
+#define HRTIM_SET2R_MSTPER            HRTIM_SET2R_MSTPER_Msk                   /*!< Master period */
+#define HRTIM_SET2R_MSTCMP1_Pos       (8U)
+#define HRTIM_SET2R_MSTCMP1_Msk       (0x1UL << HRTIM_SET2R_MSTCMP1_Pos)       /*!< 0x00000100 */
+#define HRTIM_SET2R_MSTCMP1           HRTIM_SET2R_MSTCMP1_Msk                  /*!< Master compare 1 */
+#define HRTIM_SET2R_MSTCMP2_Pos       (9U)
+#define HRTIM_SET2R_MSTCMP2_Msk       (0x1UL << HRTIM_SET2R_MSTCMP2_Pos)       /*!< 0x00000200 */
+#define HRTIM_SET2R_MSTCMP2           HRTIM_SET2R_MSTCMP2_Msk                  /*!< Master compare 2 */
+#define HRTIM_SET2R_MSTCMP3_Pos       (10U)
+#define HRTIM_SET2R_MSTCMP3_Msk       (0x1UL << HRTIM_SET2R_MSTCMP3_Pos)       /*!< 0x00000400 */
+#define HRTIM_SET2R_MSTCMP3           HRTIM_SET2R_MSTCMP3_Msk                  /*!< Master compare 3 */
+#define HRTIM_SET2R_MSTCMP4_Pos       (11U)
+#define HRTIM_SET2R_MSTCMP4_Msk       (0x1UL << HRTIM_SET2R_MSTCMP4_Pos)       /*!< 0x00000800 */
+#define HRTIM_SET2R_MSTCMP4           HRTIM_SET2R_MSTCMP4_Msk                  /*!< Master compare 4 */
+
+#define HRTIM_SET2R_TIMEVNT1_Pos      (12U)
+#define HRTIM_SET2R_TIMEVNT1_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT1_Pos)      /*!< 0x00001000 */
+#define HRTIM_SET2R_TIMEVNT1          HRTIM_SET2R_TIMEVNT1_Msk                 /*!< Timer event 1 */
+#define HRTIM_SET2R_TIMEVNT2_Pos      (13U)
+#define HRTIM_SET2R_TIMEVNT2_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT2_Pos)      /*!< 0x00002000 */
+#define HRTIM_SET2R_TIMEVNT2          HRTIM_SET2R_TIMEVNT2_Msk                 /*!< Timer event 2 */
+#define HRTIM_SET2R_TIMEVNT3_Pos      (14U)
+#define HRTIM_SET2R_TIMEVNT3_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT3_Pos)      /*!< 0x00004000 */
+#define HRTIM_SET2R_TIMEVNT3          HRTIM_SET2R_TIMEVNT3_Msk                 /*!< Timer event 3 */
+#define HRTIM_SET2R_TIMEVNT4_Pos      (15U)
+#define HRTIM_SET2R_TIMEVNT4_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT4_Pos)      /*!< 0x00008000 */
+#define HRTIM_SET2R_TIMEVNT4          HRTIM_SET2R_TIMEVNT4_Msk                 /*!< Timer event 4 */
+#define HRTIM_SET2R_TIMEVNT5_Pos      (16U)
+#define HRTIM_SET2R_TIMEVNT5_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT5_Pos)      /*!< 0x00010000 */
+#define HRTIM_SET2R_TIMEVNT5          HRTIM_SET2R_TIMEVNT5_Msk                 /*!< Timer event 5 */
+#define HRTIM_SET2R_TIMEVNT6_Pos      (17U)
+#define HRTIM_SET2R_TIMEVNT6_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT6_Pos)      /*!< 0x00020000 */
+#define HRTIM_SET2R_TIMEVNT6          HRTIM_SET2R_TIMEVNT6_Msk                 /*!< Timer event 6 */
+#define HRTIM_SET2R_TIMEVNT7_Pos      (18U)
+#define HRTIM_SET2R_TIMEVNT7_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT7_Pos)      /*!< 0x00040000 */
+#define HRTIM_SET2R_TIMEVNT7          HRTIM_SET2R_TIMEVNT7_Msk                 /*!< Timer event 7 */
+#define HRTIM_SET2R_TIMEVNT8_Pos      (19U)
+#define HRTIM_SET2R_TIMEVNT8_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT8_Pos)      /*!< 0x00080000 */
+#define HRTIM_SET2R_TIMEVNT8          HRTIM_SET2R_TIMEVNT8_Msk                 /*!< Timer event 8 */
+#define HRTIM_SET2R_TIMEVNT9_Pos      (20U)
+#define HRTIM_SET2R_TIMEVNT9_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT9_Pos)      /*!< 0x00100000 */
+#define HRTIM_SET2R_TIMEVNT9          HRTIM_SET2R_TIMEVNT9_Msk                 /*!< Timer event 9 */
+
+#define HRTIM_SET2R_EXTVNT1_Pos       (21U)
+#define HRTIM_SET2R_EXTVNT1_Msk       (0x1UL << HRTIM_SET2R_EXTVNT1_Pos)       /*!< 0x00200000 */
+#define HRTIM_SET2R_EXTVNT1           HRTIM_SET2R_EXTVNT1_Msk                  /*!< External event 1 */
+#define HRTIM_SET2R_EXTVNT2_Pos       (22U)
+#define HRTIM_SET2R_EXTVNT2_Msk       (0x1UL << HRTIM_SET2R_EXTVNT2_Pos)       /*!< 0x00400000 */
+#define HRTIM_SET2R_EXTVNT2           HRTIM_SET2R_EXTVNT2_Msk                  /*!< External event 2 */
+#define HRTIM_SET2R_EXTVNT3_Pos       (23U)
+#define HRTIM_SET2R_EXTVNT3_Msk       (0x1UL << HRTIM_SET2R_EXTVNT3_Pos)       /*!< 0x00800000 */
+#define HRTIM_SET2R_EXTVNT3           HRTIM_SET2R_EXTVNT3_Msk                  /*!< External event 3 */
+#define HRTIM_SET2R_EXTVNT4_Pos       (24U)
+#define HRTIM_SET2R_EXTVNT4_Msk       (0x1UL << HRTIM_SET2R_EXTVNT4_Pos)       /*!< 0x01000000 */
+#define HRTIM_SET2R_EXTVNT4           HRTIM_SET2R_EXTVNT4_Msk                  /*!< External event 4 */
+#define HRTIM_SET2R_EXTVNT5_Pos       (25U)
+#define HRTIM_SET2R_EXTVNT5_Msk       (0x1UL << HRTIM_SET2R_EXTVNT5_Pos)       /*!< 0x02000000 */
+#define HRTIM_SET2R_EXTVNT5           HRTIM_SET2R_EXTVNT5_Msk                  /*!< External event 5 */
+#define HRTIM_SET2R_EXTVNT6_Pos       (26U)
+#define HRTIM_SET2R_EXTVNT6_Msk       (0x1UL << HRTIM_SET2R_EXTVNT6_Pos)       /*!< 0x04000000 */
+#define HRTIM_SET2R_EXTVNT6           HRTIM_SET2R_EXTVNT6_Msk                  /*!< External event 6 */
+#define HRTIM_SET2R_EXTVNT7_Pos       (27U)
+#define HRTIM_SET2R_EXTVNT7_Msk       (0x1UL << HRTIM_SET2R_EXTVNT7_Pos)       /*!< 0x08000000 */
+#define HRTIM_SET2R_EXTVNT7           HRTIM_SET2R_EXTVNT7_Msk                  /*!< External event 7 */
+#define HRTIM_SET2R_EXTVNT8_Pos       (28U)
+#define HRTIM_SET2R_EXTVNT8_Msk       (0x1UL << HRTIM_SET2R_EXTVNT8_Pos)       /*!< 0x10000000 */
+#define HRTIM_SET2R_EXTVNT8           HRTIM_SET2R_EXTVNT8_Msk                  /*!< External event 8 */
+#define HRTIM_SET2R_EXTVNT9_Pos       (29U)
+#define HRTIM_SET2R_EXTVNT9_Msk       (0x1UL << HRTIM_SET2R_EXTVNT9_Pos)       /*!< 0x20000000 */
+#define HRTIM_SET2R_EXTVNT9           HRTIM_SET2R_EXTVNT9_Msk                  /*!< External event 9 */
+#define HRTIM_SET2R_EXTVNT10_Pos      (30U)
+#define HRTIM_SET2R_EXTVNT10_Msk      (0x1UL << HRTIM_SET2R_EXTVNT10_Pos)      /*!< 0x40000000 */
+#define HRTIM_SET2R_EXTVNT10          HRTIM_SET2R_EXTVNT10_Msk                 /*!< External event 10 */
+
+#define HRTIM_SET2R_UPDATE_Pos        (31U)
+#define HRTIM_SET2R_UPDATE_Msk        (0x1UL << HRTIM_SET2R_UPDATE_Pos)        /*!< 0x80000000 */
+#define HRTIM_SET2R_UPDATE            HRTIM_SET2R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */
+
+/**** Bit definition for Slave Output 2 reset register ************************/
+#define HRTIM_RST2R_SRT_Pos           (0U)
+#define HRTIM_RST2R_SRT_Msk           (0x1UL << HRTIM_RST2R_SRT_Pos)           /*!< 0x00000001 */
+#define HRTIM_RST2R_SRT               HRTIM_RST2R_SRT_Msk                      /*!< software reset trigger */
+#define HRTIM_RST2R_RESYNC_Pos        (1U)
+#define HRTIM_RST2R_RESYNC_Msk        (0x1UL << HRTIM_RST2R_RESYNC_Pos)        /*!< 0x00000002 */
+#define HRTIM_RST2R_RESYNC            HRTIM_RST2R_RESYNC_Msk                   /*!< Timer A resynchronization */
+#define HRTIM_RST2R_PER_Pos           (2U)
+#define HRTIM_RST2R_PER_Msk           (0x1UL << HRTIM_RST2R_PER_Pos)           /*!< 0x00000004 */
+#define HRTIM_RST2R_PER               HRTIM_RST2R_PER_Msk                      /*!< Timer A period */
+#define HRTIM_RST2R_CMP1_Pos          (3U)
+#define HRTIM_RST2R_CMP1_Msk          (0x1UL << HRTIM_RST2R_CMP1_Pos)          /*!< 0x00000008 */
+#define HRTIM_RST2R_CMP1              HRTIM_RST2R_CMP1_Msk                     /*!< Timer A compare 1 */
+#define HRTIM_RST2R_CMP2_Pos          (4U)
+#define HRTIM_RST2R_CMP2_Msk          (0x1UL << HRTIM_RST2R_CMP2_Pos)          /*!< 0x00000010 */
+#define HRTIM_RST2R_CMP2              HRTIM_RST2R_CMP2_Msk                     /*!< Timer A compare 2 */
+#define HRTIM_RST2R_CMP3_Pos          (5U)
+#define HRTIM_RST2R_CMP3_Msk          (0x1UL << HRTIM_RST2R_CMP3_Pos)          /*!< 0x00000020 */
+#define HRTIM_RST2R_CMP3              HRTIM_RST2R_CMP3_Msk                     /*!< Timer A compare 3 */
+#define HRTIM_RST2R_CMP4_Pos          (6U)
+#define HRTIM_RST2R_CMP4_Msk          (0x1UL << HRTIM_RST2R_CMP4_Pos)          /*!< 0x00000040 */
+#define HRTIM_RST2R_CMP4              HRTIM_RST2R_CMP4_Msk                     /*!< Timer A compare 4 */
+
+#define HRTIM_RST2R_MSTPER_Pos        (7U)
+#define HRTIM_RST2R_MSTPER_Msk        (0x1UL << HRTIM_RST2R_MSTPER_Pos)        /*!< 0x00000080 */
+#define HRTIM_RST2R_MSTPER            HRTIM_RST2R_MSTPER_Msk                   /*!< Master period */
+#define HRTIM_RST2R_MSTCMP1_Pos       (8U)
+#define HRTIM_RST2R_MSTCMP1_Msk       (0x1UL << HRTIM_RST2R_MSTCMP1_Pos)       /*!< 0x00000100 */
+#define HRTIM_RST2R_MSTCMP1           HRTIM_RST2R_MSTCMP1_Msk                  /*!< Master compare 1 */
+#define HRTIM_RST2R_MSTCMP2_Pos       (9U)
+#define HRTIM_RST2R_MSTCMP2_Msk       (0x1UL << HRTIM_RST2R_MSTCMP2_Pos)       /*!< 0x00000200 */
+#define HRTIM_RST2R_MSTCMP2           HRTIM_RST2R_MSTCMP2_Msk                  /*!< Master compare 2 */
+#define HRTIM_RST2R_MSTCMP3_Pos       (10U)
+#define HRTIM_RST2R_MSTCMP3_Msk       (0x1UL << HRTIM_RST2R_MSTCMP3_Pos)       /*!< 0x00000400 */
+#define HRTIM_RST2R_MSTCMP3           HRTIM_RST2R_MSTCMP3_Msk                  /*!< Master compare 3 */
+#define HRTIM_RST2R_MSTCMP4_Pos       (11U)
+#define HRTIM_RST2R_MSTCMP4_Msk       (0x1UL << HRTIM_RST2R_MSTCMP4_Pos)       /*!< 0x00000800 */
+#define HRTIM_RST2R_MSTCMP4           HRTIM_RST2R_MSTCMP4_Msk                  /*!< Master compare 4 */
+
+#define HRTIM_RST2R_TIMEVNT1_Pos      (12U)
+#define HRTIM_RST2R_TIMEVNT1_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT1_Pos)      /*!< 0x00001000 */
+#define HRTIM_RST2R_TIMEVNT1          HRTIM_RST2R_TIMEVNT1_Msk                 /*!< Timer event 1 */
+#define HRTIM_RST2R_TIMEVNT2_Pos      (13U)
+#define HRTIM_RST2R_TIMEVNT2_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT2_Pos)      /*!< 0x00002000 */
+#define HRTIM_RST2R_TIMEVNT2          HRTIM_RST2R_TIMEVNT2_Msk                 /*!< Timer event 2 */
+#define HRTIM_RST2R_TIMEVNT3_Pos      (14U)
+#define HRTIM_RST2R_TIMEVNT3_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT3_Pos)      /*!< 0x00004000 */
+#define HRTIM_RST2R_TIMEVNT3          HRTIM_RST2R_TIMEVNT3_Msk                 /*!< Timer event 3 */
+#define HRTIM_RST2R_TIMEVNT4_Pos      (15U)
+#define HRTIM_RST2R_TIMEVNT4_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT4_Pos)      /*!< 0x00008000 */
+#define HRTIM_RST2R_TIMEVNT4          HRTIM_RST2R_TIMEVNT4_Msk                 /*!< Timer event 4 */
+#define HRTIM_RST2R_TIMEVNT5_Pos      (16U)
+#define HRTIM_RST2R_TIMEVNT5_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT5_Pos)      /*!< 0x00010000 */
+#define HRTIM_RST2R_TIMEVNT5          HRTIM_RST2R_TIMEVNT5_Msk                 /*!< Timer event 5 */
+#define HRTIM_RST2R_TIMEVNT6_Pos      (17U)
+#define HRTIM_RST2R_TIMEVNT6_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT6_Pos)      /*!< 0x00020000 */
+#define HRTIM_RST2R_TIMEVNT6          HRTIM_RST2R_TIMEVNT6_Msk                 /*!< Timer event 6 */
+#define HRTIM_RST2R_TIMEVNT7_Pos      (18U)
+#define HRTIM_RST2R_TIMEVNT7_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT7_Pos)      /*!< 0x00040000 */
+#define HRTIM_RST2R_TIMEVNT7          HRTIM_RST2R_TIMEVNT7_Msk                 /*!< Timer event 7 */
+#define HRTIM_RST2R_TIMEVNT8_Pos      (19U)
+#define HRTIM_RST2R_TIMEVNT8_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT8_Pos)      /*!< 0x00080000 */
+#define HRTIM_RST2R_TIMEVNT8          HRTIM_RST2R_TIMEVNT8_Msk                 /*!< Timer event 8 */
+#define HRTIM_RST2R_TIMEVNT9_Pos      (20U)
+#define HRTIM_RST2R_TIMEVNT9_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT9_Pos)      /*!< 0x00100000 */
+#define HRTIM_RST2R_TIMEVNT9          HRTIM_RST2R_TIMEVNT9_Msk                 /*!< Timer event 9 */
+
+#define HRTIM_RST2R_EXTVNT1_Pos       (21U)
+#define HRTIM_RST2R_EXTVNT1_Msk       (0x1UL << HRTIM_RST2R_EXTVNT1_Pos)       /*!< 0x00200000 */
+#define HRTIM_RST2R_EXTVNT1           HRTIM_RST2R_EXTVNT1_Msk                  /*!< External event 1 */
+#define HRTIM_RST2R_EXTVNT2_Pos       (22U)
+#define HRTIM_RST2R_EXTVNT2_Msk       (0x1UL << HRTIM_RST2R_EXTVNT2_Pos)       /*!< 0x00400000 */
+#define HRTIM_RST2R_EXTVNT2           HRTIM_RST2R_EXTVNT2_Msk                  /*!< External event 2 */
+#define HRTIM_RST2R_EXTVNT3_Pos       (23U)
+#define HRTIM_RST2R_EXTVNT3_Msk       (0x1UL << HRTIM_RST2R_EXTVNT3_Pos)       /*!< 0x00800000 */
+#define HRTIM_RST2R_EXTVNT3           HRTIM_RST2R_EXTVNT3_Msk                  /*!< External event 3 */
+#define HRTIM_RST2R_EXTVNT4_Pos       (24U)
+#define HRTIM_RST2R_EXTVNT4_Msk       (0x1UL << HRTIM_RST2R_EXTVNT4_Pos)       /*!< 0x01000000 */
+#define HRTIM_RST2R_EXTVNT4           HRTIM_RST2R_EXTVNT4_Msk                  /*!< External event 4 */
+#define HRTIM_RST2R_EXTVNT5_Pos       (25U)
+#define HRTIM_RST2R_EXTVNT5_Msk       (0x1UL << HRTIM_RST2R_EXTVNT5_Pos)       /*!< 0x02000000 */
+#define HRTIM_RST2R_EXTVNT5           HRTIM_RST2R_EXTVNT5_Msk                  /*!< External event 5 */
+#define HRTIM_RST2R_EXTVNT6_Pos       (26U)
+#define HRTIM_RST2R_EXTVNT6_Msk       (0x1UL << HRTIM_RST2R_EXTVNT6_Pos)       /*!< 0x04000000 */
+#define HRTIM_RST2R_EXTVNT6           HRTIM_RST2R_EXTVNT6_Msk                  /*!< External event 6 */
+#define HRTIM_RST2R_EXTVNT7_Pos       (27U)
+#define HRTIM_RST2R_EXTVNT7_Msk       (0x1UL << HRTIM_RST2R_EXTVNT7_Pos)       /*!< 0x08000000 */
+#define HRTIM_RST2R_EXTVNT7           HRTIM_RST2R_EXTVNT7_Msk                  /*!< External event 7 */
+#define HRTIM_RST2R_EXTVNT8_Pos       (28U)
+#define HRTIM_RST2R_EXTVNT8_Msk       (0x1UL << HRTIM_RST2R_EXTVNT8_Pos)       /*!< 0x10000000 */
+#define HRTIM_RST2R_EXTVNT8           HRTIM_RST2R_EXTVNT8_Msk                  /*!< External event 8 */
+#define HRTIM_RST2R_EXTVNT9_Pos       (29U)
+#define HRTIM_RST2R_EXTVNT9_Msk       (0x1UL << HRTIM_RST2R_EXTVNT9_Pos)       /*!< 0x20000000 */
+#define HRTIM_RST2R_EXTVNT9           HRTIM_RST2R_EXTVNT9_Msk                  /*!< External event 9 */
+#define HRTIM_RST2R_EXTVNT10_Pos      (30U)
+#define HRTIM_RST2R_EXTVNT10_Msk      (0x1UL << HRTIM_RST2R_EXTVNT10_Pos)      /*!< 0x40000000 */
+#define HRTIM_RST2R_EXTVNT10          HRTIM_RST2R_EXTVNT10_Msk                 /*!< External event 10 */
+
+#define HRTIM_RST2R_UPDATE_Pos        (31U)
+#define HRTIM_RST2R_UPDATE_Msk        (0x1UL << HRTIM_RST2R_UPDATE_Pos)        /*!< 0x80000000 */
+#define HRTIM_RST2R_UPDATE            HRTIM_RST2R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */
+
+/**** Bit definition for Slave external event filtering  register 1 ***********/
+#define HRTIM_EEFR1_EE1LTCH_Pos       (0U)
+#define HRTIM_EEFR1_EE1LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE1LTCH_Pos)       /*!< 0x00000001 */
+#define HRTIM_EEFR1_EE1LTCH           HRTIM_EEFR1_EE1LTCH_Msk                  /*!< External Event 1 latch */
+#define HRTIM_EEFR1_EE1FLTR_Pos       (1U)
+#define HRTIM_EEFR1_EE1FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE1FLTR_Pos)       /*!< 0x0000001E */
+#define HRTIM_EEFR1_EE1FLTR           HRTIM_EEFR1_EE1FLTR_Msk                  /*!< External Event 1 filter mask */
+#define HRTIM_EEFR1_EE1FLTR_0         (0x1UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000002 */
+#define HRTIM_EEFR1_EE1FLTR_1         (0x2UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000004 */
+#define HRTIM_EEFR1_EE1FLTR_2         (0x4UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000008 */
+#define HRTIM_EEFR1_EE1FLTR_3         (0x8UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000010 */
+
+#define HRTIM_EEFR1_EE2LTCH_Pos       (6U)
+#define HRTIM_EEFR1_EE2LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE2LTCH_Pos)       /*!< 0x00000040 */
+#define HRTIM_EEFR1_EE2LTCH           HRTIM_EEFR1_EE2LTCH_Msk                  /*!< External Event 2 latch */
+#define HRTIM_EEFR1_EE2FLTR_Pos       (7U)
+#define HRTIM_EEFR1_EE2FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE2FLTR_Pos)       /*!< 0x00000780 */
+#define HRTIM_EEFR1_EE2FLTR           HRTIM_EEFR1_EE2FLTR_Msk                  /*!< External Event 2 filter mask */
+#define HRTIM_EEFR1_EE2FLTR_0         (0x1UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000080 */
+#define HRTIM_EEFR1_EE2FLTR_1         (0x2UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000100 */
+#define HRTIM_EEFR1_EE2FLTR_2         (0x4UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000200 */
+#define HRTIM_EEFR1_EE2FLTR_3         (0x8UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000400 */
+
+#define HRTIM_EEFR1_EE3LTCH_Pos       (12U)
+#define HRTIM_EEFR1_EE3LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE3LTCH_Pos)       /*!< 0x00001000 */
+#define HRTIM_EEFR1_EE3LTCH           HRTIM_EEFR1_EE3LTCH_Msk                  /*!< External Event 3 latch */
+#define HRTIM_EEFR1_EE3FLTR_Pos       (13U)
+#define HRTIM_EEFR1_EE3FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE3FLTR_Pos)       /*!< 0x0001E000 */
+#define HRTIM_EEFR1_EE3FLTR           HRTIM_EEFR1_EE3FLTR_Msk                  /*!< External Event 3 filter mask */
+#define HRTIM_EEFR1_EE3FLTR_0         (0x1UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00002000 */
+#define HRTIM_EEFR1_EE3FLTR_1         (0x2UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00004000 */
+#define HRTIM_EEFR1_EE3FLTR_2         (0x4UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00008000 */
+#define HRTIM_EEFR1_EE3FLTR_3         (0x8UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00010000 */
+
+#define HRTIM_EEFR1_EE4LTCH_Pos       (18U)
+#define HRTIM_EEFR1_EE4LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE4LTCH_Pos)       /*!< 0x00040000 */
+#define HRTIM_EEFR1_EE4LTCH           HRTIM_EEFR1_EE4LTCH_Msk                  /*!< External Event 4 latch */
+#define HRTIM_EEFR1_EE4FLTR_Pos       (19U)
+#define HRTIM_EEFR1_EE4FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE4FLTR_Pos)       /*!< 0x00780000 */
+#define HRTIM_EEFR1_EE4FLTR           HRTIM_EEFR1_EE4FLTR_Msk                  /*!< External Event 4 filter mask */
+#define HRTIM_EEFR1_EE4FLTR_0         (0x1UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00080000 */
+#define HRTIM_EEFR1_EE4FLTR_1         (0x2UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00100000 */
+#define HRTIM_EEFR1_EE4FLTR_2         (0x4UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00200000 */
+#define HRTIM_EEFR1_EE4FLTR_3         (0x8UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00400000 */
+
+#define HRTIM_EEFR1_EE5LTCH_Pos       (24U)
+#define HRTIM_EEFR1_EE5LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE5LTCH_Pos)       /*!< 0x01000000 */
+#define HRTIM_EEFR1_EE5LTCH           HRTIM_EEFR1_EE5LTCH_Msk                  /*!< External Event 5 latch */
+#define HRTIM_EEFR1_EE5FLTR_Pos       (25U)
+#define HRTIM_EEFR1_EE5FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE5FLTR_Pos)       /*!< 0x1E000000 */
+#define HRTIM_EEFR1_EE5FLTR           HRTIM_EEFR1_EE5FLTR_Msk                  /*!< External Event 5 filter mask */
+#define HRTIM_EEFR1_EE5FLTR_0         (0x1UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x02000000 */
+#define HRTIM_EEFR1_EE5FLTR_1         (0x2UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x04000000 */
+#define HRTIM_EEFR1_EE5FLTR_2         (0x4UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x08000000 */
+#define HRTIM_EEFR1_EE5FLTR_3         (0x8UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x10000000 */
+
+/**** Bit definition for Slave external event filtering  register 2 ***********/
+#define HRTIM_EEFR2_EE6LTCH_Pos       (0U)
+#define HRTIM_EEFR2_EE6LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE6LTCH_Pos)       /*!< 0x00000001 */
+#define HRTIM_EEFR2_EE6LTCH           HRTIM_EEFR2_EE6LTCH_Msk                  /*!< External Event 6 latch */
+#define HRTIM_EEFR2_EE6FLTR_Pos       (1U)
+#define HRTIM_EEFR2_EE6FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE6FLTR_Pos)       /*!< 0x0000001E */
+#define HRTIM_EEFR2_EE6FLTR           HRTIM_EEFR2_EE6FLTR_Msk                  /*!< External Event 6 filter mask */
+#define HRTIM_EEFR2_EE6FLTR_0         (0x1UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000002 */
+#define HRTIM_EEFR2_EE6FLTR_1         (0x2UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000004 */
+#define HRTIM_EEFR2_EE6FLTR_2         (0x4UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000008 */
+#define HRTIM_EEFR2_EE6FLTR_3         (0x8UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000010 */
+
+#define HRTIM_EEFR2_EE7LTCH_Pos       (6U)
+#define HRTIM_EEFR2_EE7LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE7LTCH_Pos)       /*!< 0x00000040 */
+#define HRTIM_EEFR2_EE7LTCH           HRTIM_EEFR2_EE7LTCH_Msk                  /*!< External Event 7 latch */
+#define HRTIM_EEFR2_EE7FLTR_Pos       (7U)
+#define HRTIM_EEFR2_EE7FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE7FLTR_Pos)       /*!< 0x00000780 */
+#define HRTIM_EEFR2_EE7FLTR           HRTIM_EEFR2_EE7FLTR_Msk                  /*!< External Event 7 filter mask */
+#define HRTIM_EEFR2_EE7FLTR_0         (0x1UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000080 */
+#define HRTIM_EEFR2_EE7FLTR_1         (0x2UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000100 */
+#define HRTIM_EEFR2_EE7FLTR_2         (0x4UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000200 */
+#define HRTIM_EEFR2_EE7FLTR_3         (0x8UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000400 */
+
+#define HRTIM_EEFR2_EE8LTCH_Pos       (12U)
+#define HRTIM_EEFR2_EE8LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE8LTCH_Pos)       /*!< 0x00001000 */
+#define HRTIM_EEFR2_EE8LTCH           HRTIM_EEFR2_EE8LTCH_Msk                  /*!< External Event 8 latch */
+#define HRTIM_EEFR2_EE8FLTR_Pos       (13U)
+#define HRTIM_EEFR2_EE8FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE8FLTR_Pos)       /*!< 0x0001E000 */
+#define HRTIM_EEFR2_EE8FLTR           HRTIM_EEFR2_EE8FLTR_Msk                  /*!< External Event 8 filter mask */
+#define HRTIM_EEFR2_EE8FLTR_0         (0x1UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00002000 */
+#define HRTIM_EEFR2_EE8FLTR_1         (0x2UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00004000 */
+#define HRTIM_EEFR2_EE8FLTR_2         (0x4UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00008000 */
+#define HRTIM_EEFR2_EE8FLTR_3         (0x8UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00010000 */
+
+#define HRTIM_EEFR2_EE9LTCH_Pos       (18U)
+#define HRTIM_EEFR2_EE9LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE9LTCH_Pos)       /*!< 0x00040000 */
+#define HRTIM_EEFR2_EE9LTCH           HRTIM_EEFR2_EE9LTCH_Msk                  /*!< External Event 9 latch */
+#define HRTIM_EEFR2_EE9FLTR_Pos       (19U)
+#define HRTIM_EEFR2_EE9FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE9FLTR_Pos)       /*!< 0x00780000 */
+#define HRTIM_EEFR2_EE9FLTR           HRTIM_EEFR2_EE9FLTR_Msk                  /*!< External Event 9 filter mask */
+#define HRTIM_EEFR2_EE9FLTR_0         (0x1UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00080000 */
+#define HRTIM_EEFR2_EE9FLTR_1         (0x2UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00100000 */
+#define HRTIM_EEFR2_EE9FLTR_2         (0x4UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00200000 */
+#define HRTIM_EEFR2_EE9FLTR_3         (0x8UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00400000 */
+
+#define HRTIM_EEFR2_EE10LTCH_Pos      (24U)
+#define HRTIM_EEFR2_EE10LTCH_Msk      (0x1UL << HRTIM_EEFR2_EE10LTCH_Pos)      /*!< 0x01000000 */
+#define HRTIM_EEFR2_EE10LTCH          HRTIM_EEFR2_EE10LTCH_Msk                 /*!< External Event 10 latch */
+#define HRTIM_EEFR2_EE10FLTR_Pos      (25U)
+#define HRTIM_EEFR2_EE10FLTR_Msk      (0xFUL << HRTIM_EEFR2_EE10FLTR_Pos)      /*!< 0x1E000000 */
+#define HRTIM_EEFR2_EE10FLTR          HRTIM_EEFR2_EE10FLTR_Msk                 /*!< External Event 10 filter mask */
+#define HRTIM_EEFR2_EE10FLTR_0        (0x1UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x02000000 */
+#define HRTIM_EEFR2_EE10FLTR_1        (0x2UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x04000000 */
+#define HRTIM_EEFR2_EE10FLTR_2        (0x4UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x08000000 */
+#define HRTIM_EEFR2_EE10FLTR_3        (0x8UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x10000000 */
+
+/**** Bit definition for Slave Timer reset register ***************************/
+#define HRTIM_RSTR_UPDATE_Pos         (1U)
+#define HRTIM_RSTR_UPDATE_Msk         (0x1UL << HRTIM_RSTR_UPDATE_Pos)         /*!< 0x00000002 */
+#define HRTIM_RSTR_UPDATE             HRTIM_RSTR_UPDATE_Msk                    /*!< Timer update */
+#define HRTIM_RSTR_CMP2_Pos           (2U)
+#define HRTIM_RSTR_CMP2_Msk           (0x1UL << HRTIM_RSTR_CMP2_Pos)           /*!< 0x00000004 */
+#define HRTIM_RSTR_CMP2               HRTIM_RSTR_CMP2_Msk                      /*!< Timer compare2 */
+#define HRTIM_RSTR_CMP4_Pos           (3U)
+#define HRTIM_RSTR_CMP4_Msk           (0x1UL << HRTIM_RSTR_CMP4_Pos)           /*!< 0x00000008 */
+#define HRTIM_RSTR_CMP4               HRTIM_RSTR_CMP4_Msk                      /*!< Timer compare4 */
+
+#define HRTIM_RSTR_MSTPER_Pos         (4U)
+#define HRTIM_RSTR_MSTPER_Msk         (0x1UL << HRTIM_RSTR_MSTPER_Pos)         /*!< 0x00000010 */
+#define HRTIM_RSTR_MSTPER             HRTIM_RSTR_MSTPER_Msk                    /*!< Master period */
+#define HRTIM_RSTR_MSTCMP1_Pos        (5U)
+#define HRTIM_RSTR_MSTCMP1_Msk        (0x1UL << HRTIM_RSTR_MSTCMP1_Pos)        /*!< 0x00000020 */
+#define HRTIM_RSTR_MSTCMP1            HRTIM_RSTR_MSTCMP1_Msk                   /*!< Master compare1 */
+#define HRTIM_RSTR_MSTCMP2_Pos        (6U)
+#define HRTIM_RSTR_MSTCMP2_Msk        (0x1UL << HRTIM_RSTR_MSTCMP2_Pos)        /*!< 0x00000040 */
+#define HRTIM_RSTR_MSTCMP2            HRTIM_RSTR_MSTCMP2_Msk                   /*!< Master compare2 */
+#define HRTIM_RSTR_MSTCMP3_Pos        (7U)
+#define HRTIM_RSTR_MSTCMP3_Msk        (0x1UL << HRTIM_RSTR_MSTCMP3_Pos)        /*!< 0x00000080 */
+#define HRTIM_RSTR_MSTCMP3            HRTIM_RSTR_MSTCMP3_Msk                   /*!< Master compare3 */
+#define HRTIM_RSTR_MSTCMP4_Pos        (8U)
+#define HRTIM_RSTR_MSTCMP4_Msk        (0x1UL << HRTIM_RSTR_MSTCMP4_Pos)        /*!< 0x00000100 */
+#define HRTIM_RSTR_MSTCMP4            HRTIM_RSTR_MSTCMP4_Msk                   /*!< Master compare4 */
+
+#define HRTIM_RSTR_EXTEVNT1_Pos       (9U)
+#define HRTIM_RSTR_EXTEVNT1_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT1_Pos)       /*!< 0x00000200 */
+#define HRTIM_RSTR_EXTEVNT1           HRTIM_RSTR_EXTEVNT1_Msk                  /*!< External event 1 */
+#define HRTIM_RSTR_EXTEVNT2_Pos       (10U)
+#define HRTIM_RSTR_EXTEVNT2_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT2_Pos)       /*!< 0x00000400 */
+#define HRTIM_RSTR_EXTEVNT2           HRTIM_RSTR_EXTEVNT2_Msk                  /*!< External event 2 */
+#define HRTIM_RSTR_EXTEVNT3_Pos       (11U)
+#define HRTIM_RSTR_EXTEVNT3_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT3_Pos)       /*!< 0x00000800 */
+#define HRTIM_RSTR_EXTEVNT3           HRTIM_RSTR_EXTEVNT3_Msk                  /*!< External event 3 */
+#define HRTIM_RSTR_EXTEVNT4_Pos       (12U)
+#define HRTIM_RSTR_EXTEVNT4_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT4_Pos)       /*!< 0x00001000 */
+#define HRTIM_RSTR_EXTEVNT4           HRTIM_RSTR_EXTEVNT4_Msk                  /*!< External event 4 */
+#define HRTIM_RSTR_EXTEVNT5_Pos       (13U)
+#define HRTIM_RSTR_EXTEVNT5_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT5_Pos)       /*!< 0x00002000 */
+#define HRTIM_RSTR_EXTEVNT5           HRTIM_RSTR_EXTEVNT5_Msk                  /*!< External event 5 */
+#define HRTIM_RSTR_EXTEVNT6_Pos       (14U)
+#define HRTIM_RSTR_EXTEVNT6_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT6_Pos)       /*!< 0x00004000 */
+#define HRTIM_RSTR_EXTEVNT6           HRTIM_RSTR_EXTEVNT6_Msk                  /*!< External event 6 */
+#define HRTIM_RSTR_EXTEVNT7_Pos       (15U)
+#define HRTIM_RSTR_EXTEVNT7_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT7_Pos)       /*!< 0x00008000 */
+#define HRTIM_RSTR_EXTEVNT7           HRTIM_RSTR_EXTEVNT7_Msk                  /*!< External event 7 */
+#define HRTIM_RSTR_EXTEVNT8_Pos       (16U)
+#define HRTIM_RSTR_EXTEVNT8_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT8_Pos)       /*!< 0x00010000 */
+#define HRTIM_RSTR_EXTEVNT8           HRTIM_RSTR_EXTEVNT8_Msk                  /*!< External event 8 */
+#define HRTIM_RSTR_EXTEVNT9_Pos       (17U)
+#define HRTIM_RSTR_EXTEVNT9_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT9_Pos)       /*!< 0x00020000 */
+#define HRTIM_RSTR_EXTEVNT9           HRTIM_RSTR_EXTEVNT9_Msk                  /*!< External event 9 */
+#define HRTIM_RSTR_EXTEVNT10_Pos      (18U)
+#define HRTIM_RSTR_EXTEVNT10_Msk      (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos)      /*!< 0x00040000 */
+#define HRTIM_RSTR_EXTEVNT10          HRTIM_RSTR_EXTEVNT10_Msk                 /*!< External event 10 */
+
+#define HRTIM_RSTR_TIMBCMP1_Pos       (19U)
+#define HRTIM_RSTR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos)       /*!< 0x00080000 */
+#define HRTIM_RSTR_TIMBCMP1           HRTIM_RSTR_TIMBCMP1_Msk                  /*!< Timer B compare 1 */
+#define HRTIM_RSTR_TIMBCMP2_Pos       (20U)
+#define HRTIM_RSTR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP2_Pos)       /*!< 0x00100000 */
+#define HRTIM_RSTR_TIMBCMP2           HRTIM_RSTR_TIMBCMP2_Msk                  /*!< Timer B compare 2 */
+#define HRTIM_RSTR_TIMBCMP4_Pos       (21U)
+#define HRTIM_RSTR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP4_Pos)       /*!< 0x00200000 */
+#define HRTIM_RSTR_TIMBCMP4           HRTIM_RSTR_TIMBCMP4_Msk                  /*!< Timer B compare 4 */
+
+#define HRTIM_RSTR_TIMCCMP1_Pos       (22U)
+#define HRTIM_RSTR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP1_Pos)       /*!< 0x00400000 */
+#define HRTIM_RSTR_TIMCCMP1           HRTIM_RSTR_TIMCCMP1_Msk                  /*!< Timer C compare 1 */
+#define HRTIM_RSTR_TIMCCMP2_Pos       (23U)
+#define HRTIM_RSTR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP2_Pos)       /*!< 0x00800000 */
+#define HRTIM_RSTR_TIMCCMP2           HRTIM_RSTR_TIMCCMP2_Msk                  /*!< Timer C compare 2 */
+#define HRTIM_RSTR_TIMCCMP4_Pos       (24U)
+#define HRTIM_RSTR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP4_Pos)       /*!< 0x01000000 */
+#define HRTIM_RSTR_TIMCCMP4           HRTIM_RSTR_TIMCCMP4_Msk                  /*!< Timer C compare 4 */
+
+#define HRTIM_RSTR_TIMDCMP1_Pos       (25U)
+#define HRTIM_RSTR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP1_Pos)       /*!< 0x02000000 */
+#define HRTIM_RSTR_TIMDCMP1           HRTIM_RSTR_TIMDCMP1_Msk                  /*!< Timer D compare 1 */
+#define HRTIM_RSTR_TIMDCMP2_Pos       (26U)
+#define HRTIM_RSTR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP2_Pos)       /*!< 0x04000000 */
+#define HRTIM_RSTR_TIMDCMP2           HRTIM_RSTR_TIMDCMP2_Msk                  /*!< Timer D compare 2 */
+#define HRTIM_RSTR_TIMDCMP4_Pos       (27U)
+#define HRTIM_RSTR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP4_Pos)       /*!< 0x08000000 */
+#define HRTIM_RSTR_TIMDCMP4           HRTIM_RSTR_TIMDCMP4_Msk                  /*!< Timer D compare 4 */
+
+#define HRTIM_RSTR_TIMECMP1_Pos       (28U)
+#define HRTIM_RSTR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTR_TIMECMP1_Pos)       /*!< 0x10000000 */
+#define HRTIM_RSTR_TIMECMP1           HRTIM_RSTR_TIMECMP1_Msk                  /*!< Timer E compare 1 */
+#define HRTIM_RSTR_TIMECMP2_Pos       (29U)
+#define HRTIM_RSTR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTR_TIMECMP2_Pos)       /*!< 0x20000000 */
+#define HRTIM_RSTR_TIMECMP2           HRTIM_RSTR_TIMECMP2_Msk                  /*!< Timer E compare 2 */
+#define HRTIM_RSTR_TIMECMP4_Pos       (30U)
+#define HRTIM_RSTR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTR_TIMECMP4_Pos)       /*!< 0x40000000 */
+#define HRTIM_RSTR_TIMECMP4           HRTIM_RSTR_TIMECMP4_Msk                  /*!< Timer E compare 4 */
+
+/**** Bit definition for Slave Timer Chopper register *************************/
+#define HRTIM_CHPR_CARFRQ_Pos         (0U)
+#define HRTIM_CHPR_CARFRQ_Msk         (0xFUL << HRTIM_CHPR_CARFRQ_Pos)         /*!< 0x0000000F */
+#define HRTIM_CHPR_CARFRQ             HRTIM_CHPR_CARFRQ_Msk                    /*!< Timer carrier frequency value */
+#define HRTIM_CHPR_CARFRQ_0           (0x1UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000001 */
+#define HRTIM_CHPR_CARFRQ_1           (0x2UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000002 */
+#define HRTIM_CHPR_CARFRQ_2           (0x4UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000004 */
+#define HRTIM_CHPR_CARFRQ_3           (0x8UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000008 */
+
+#define HRTIM_CHPR_CARDTY_Pos         (4U)
+#define HRTIM_CHPR_CARDTY_Msk         (0x7UL << HRTIM_CHPR_CARDTY_Pos)         /*!< 0x00000070 */
+#define HRTIM_CHPR_CARDTY             HRTIM_CHPR_CARDTY_Msk                    /*!< Timer chopper duty cycle value */
+#define HRTIM_CHPR_CARDTY_0           (0x1UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000010 */
+#define HRTIM_CHPR_CARDTY_1           (0x2UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000020 */
+#define HRTIM_CHPR_CARDTY_2           (0x4UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000040 */
+
+#define HRTIM_CHPR_STRPW_Pos          (7U)
+#define HRTIM_CHPR_STRPW_Msk          (0xFUL << HRTIM_CHPR_STRPW_Pos)          /*!< 0x00000780 */
+#define HRTIM_CHPR_STRPW              HRTIM_CHPR_STRPW_Msk                     /*!< Timer start pulse width value */
+#define HRTIM_CHPR_STRPW_0            (0x1UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000080 */
+#define HRTIM_CHPR_STRPW_1            (0x2UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000100 */
+#define HRTIM_CHPR_STRPW_2            (0x4UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000200 */
+#define HRTIM_CHPR_STRPW_3            (0x8UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000400 */
+
+/**** Bit definition for Slave Timer Capture 1 control register ***************/
+#define HRTIM_CPT1CR_SWCPT_Pos        (0U)
+#define HRTIM_CPT1CR_SWCPT_Msk        (0x1UL << HRTIM_CPT1CR_SWCPT_Pos)        /*!< 0x00000001 */
+#define HRTIM_CPT1CR_SWCPT            HRTIM_CPT1CR_SWCPT_Msk                   /*!< Software capture */
+#define HRTIM_CPT1CR_UPDCPT_Pos       (1U)
+#define HRTIM_CPT1CR_UPDCPT_Msk       (0x1UL << HRTIM_CPT1CR_UPDCPT_Pos)       /*!< 0x00000002 */
+#define HRTIM_CPT1CR_UPDCPT           HRTIM_CPT1CR_UPDCPT_Msk                  /*!< Update capture */
+#define HRTIM_CPT1CR_EXEV1CPT_Pos     (2U)
+#define HRTIM_CPT1CR_EXEV1CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV1CPT_Pos)     /*!< 0x00000004 */
+#define HRTIM_CPT1CR_EXEV1CPT         HRTIM_CPT1CR_EXEV1CPT_Msk                /*!< External event 1 capture */
+#define HRTIM_CPT1CR_EXEV2CPT_Pos     (3U)
+#define HRTIM_CPT1CR_EXEV2CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV2CPT_Pos)     /*!< 0x00000008 */
+#define HRTIM_CPT1CR_EXEV2CPT         HRTIM_CPT1CR_EXEV2CPT_Msk                /*!< External event 2 capture */
+#define HRTIM_CPT1CR_EXEV3CPT_Pos     (4U)
+#define HRTIM_CPT1CR_EXEV3CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV3CPT_Pos)     /*!< 0x00000010 */
+#define HRTIM_CPT1CR_EXEV3CPT         HRTIM_CPT1CR_EXEV3CPT_Msk                /*!< External event 3 capture */
+#define HRTIM_CPT1CR_EXEV4CPT_Pos     (5U)
+#define HRTIM_CPT1CR_EXEV4CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV4CPT_Pos)     /*!< 0x00000020 */
+#define HRTIM_CPT1CR_EXEV4CPT         HRTIM_CPT1CR_EXEV4CPT_Msk                /*!< External event 4 capture */
+#define HRTIM_CPT1CR_EXEV5CPT_Pos     (6U)
+#define HRTIM_CPT1CR_EXEV5CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV5CPT_Pos)     /*!< 0x00000040 */
+#define HRTIM_CPT1CR_EXEV5CPT         HRTIM_CPT1CR_EXEV5CPT_Msk                /*!< External event 5 capture */
+#define HRTIM_CPT1CR_EXEV6CPT_Pos     (7U)
+#define HRTIM_CPT1CR_EXEV6CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV6CPT_Pos)     /*!< 0x00000080 */
+#define HRTIM_CPT1CR_EXEV6CPT         HRTIM_CPT1CR_EXEV6CPT_Msk                /*!< External event 6 capture */
+#define HRTIM_CPT1CR_EXEV7CPT_Pos     (8U)
+#define HRTIM_CPT1CR_EXEV7CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV7CPT_Pos)     /*!< 0x00000100 */
+#define HRTIM_CPT1CR_EXEV7CPT         HRTIM_CPT1CR_EXEV7CPT_Msk                /*!< External event 7 capture */
+#define HRTIM_CPT1CR_EXEV8CPT_Pos     (9U)
+#define HRTIM_CPT1CR_EXEV8CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV8CPT_Pos)     /*!< 0x00000200 */
+#define HRTIM_CPT1CR_EXEV8CPT         HRTIM_CPT1CR_EXEV8CPT_Msk                /*!< External event 8 capture */
+#define HRTIM_CPT1CR_EXEV9CPT_Pos     (10U)
+#define HRTIM_CPT1CR_EXEV9CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV9CPT_Pos)     /*!< 0x00000400 */
+#define HRTIM_CPT1CR_EXEV9CPT         HRTIM_CPT1CR_EXEV9CPT_Msk                /*!< External event 9 capture */
+#define HRTIM_CPT1CR_EXEV10CPT_Pos    (11U)
+#define HRTIM_CPT1CR_EXEV10CPT_Msk    (0x1UL << HRTIM_CPT1CR_EXEV10CPT_Pos)    /*!< 0x00000800 */
+#define HRTIM_CPT1CR_EXEV10CPT        HRTIM_CPT1CR_EXEV10CPT_Msk               /*!< External event 10 capture */
+
+#define HRTIM_CPT1CR_TA1SET_Pos       (12U)
+#define HRTIM_CPT1CR_TA1SET_Msk       (0x1UL << HRTIM_CPT1CR_TA1SET_Pos)       /*!< 0x00001000 */
+#define HRTIM_CPT1CR_TA1SET           HRTIM_CPT1CR_TA1SET_Msk                  /*!< Timer A output 1 set */
+#define HRTIM_CPT1CR_TA1RST_Pos       (13U)
+#define HRTIM_CPT1CR_TA1RST_Msk       (0x1UL << HRTIM_CPT1CR_TA1RST_Pos)       /*!< 0x00002000 */
+#define HRTIM_CPT1CR_TA1RST           HRTIM_CPT1CR_TA1RST_Msk                  /*!< Timer A output 1 reset */
+#define HRTIM_CPT1CR_TIMACMP1_Pos     (14U)
+#define HRTIM_CPT1CR_TIMACMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMACMP1_Pos)     /*!< 0x00004000 */
+#define HRTIM_CPT1CR_TIMACMP1         HRTIM_CPT1CR_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_CPT1CR_TIMACMP2_Pos     (15U)
+#define HRTIM_CPT1CR_TIMACMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMACMP2_Pos)     /*!< 0x00008000 */
+#define HRTIM_CPT1CR_TIMACMP2         HRTIM_CPT1CR_TIMACMP2_Msk                /*!< Timer A compare 2 */
+
+#define HRTIM_CPT1CR_TB1SET_Pos       (16U)
+#define HRTIM_CPT1CR_TB1SET_Msk       (0x1UL << HRTIM_CPT1CR_TB1SET_Pos)       /*!< 0x00010000 */
+#define HRTIM_CPT1CR_TB1SET           HRTIM_CPT1CR_TB1SET_Msk                  /*!< Timer B output 1 set */
+#define HRTIM_CPT1CR_TB1RST_Pos       (17U)
+#define HRTIM_CPT1CR_TB1RST_Msk       (0x1UL << HRTIM_CPT1CR_TB1RST_Pos)       /*!< 0x00020000 */
+#define HRTIM_CPT1CR_TB1RST           HRTIM_CPT1CR_TB1RST_Msk                  /*!< Timer B output 1 reset */
+#define HRTIM_CPT1CR_TIMBCMP1_Pos     (18U)
+#define HRTIM_CPT1CR_TIMBCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMBCMP1_Pos)     /*!< 0x00040000 */
+#define HRTIM_CPT1CR_TIMBCMP1         HRTIM_CPT1CR_TIMBCMP1_Msk                /*!< Timer B compare 1 */
+#define HRTIM_CPT1CR_TIMBCMP2_Pos     (19U)
+#define HRTIM_CPT1CR_TIMBCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMBCMP2_Pos)     /*!< 0x00080000 */
+#define HRTIM_CPT1CR_TIMBCMP2         HRTIM_CPT1CR_TIMBCMP2_Msk                /*!< Timer B compare 2 */
+
+#define HRTIM_CPT1CR_TC1SET_Pos       (20U)
+#define HRTIM_CPT1CR_TC1SET_Msk       (0x1UL << HRTIM_CPT1CR_TC1SET_Pos)       /*!< 0x00100000 */
+#define HRTIM_CPT1CR_TC1SET           HRTIM_CPT1CR_TC1SET_Msk                  /*!< Timer C output 1 set */
+#define HRTIM_CPT1CR_TC1RST_Pos       (21U)
+#define HRTIM_CPT1CR_TC1RST_Msk       (0x1UL << HRTIM_CPT1CR_TC1RST_Pos)       /*!< 0x00200000 */
+#define HRTIM_CPT1CR_TC1RST           HRTIM_CPT1CR_TC1RST_Msk                  /*!< Timer C output 1 reset */
+#define HRTIM_CPT1CR_TIMCCMP1_Pos     (22U)
+#define HRTIM_CPT1CR_TIMCCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMCCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_CPT1CR_TIMCCMP1         HRTIM_CPT1CR_TIMCCMP1_Msk                /*!< Timer C compare 1 */
+#define HRTIM_CPT1CR_TIMCCMP2_Pos     (23U)
+#define HRTIM_CPT1CR_TIMCCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMCCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_CPT1CR_TIMCCMP2         HRTIM_CPT1CR_TIMCCMP2_Msk                /*!< Timer C compare 2 */
+
+#define HRTIM_CPT1CR_TD1SET_Pos       (24U)
+#define HRTIM_CPT1CR_TD1SET_Msk       (0x1UL << HRTIM_CPT1CR_TD1SET_Pos)       /*!< 0x01000000 */
+#define HRTIM_CPT1CR_TD1SET           HRTIM_CPT1CR_TD1SET_Msk                  /*!< Timer D output 1 set */
+#define HRTIM_CPT1CR_TD1RST_Pos       (25U)
+#define HRTIM_CPT1CR_TD1RST_Msk       (0x1UL << HRTIM_CPT1CR_TD1RST_Pos)       /*!< 0x02000000 */
+#define HRTIM_CPT1CR_TD1RST           HRTIM_CPT1CR_TD1RST_Msk                  /*!< Timer D output 1 reset */
+#define HRTIM_CPT1CR_TIMDCMP1_Pos     (26U)
+#define HRTIM_CPT1CR_TIMDCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMDCMP1_Pos)     /*!< 0x04000000 */
+#define HRTIM_CPT1CR_TIMDCMP1         HRTIM_CPT1CR_TIMDCMP1_Msk                /*!< Timer D compare 1 */
+#define HRTIM_CPT1CR_TIMDCMP2_Pos     (27U)
+#define HRTIM_CPT1CR_TIMDCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMDCMP2_Pos)     /*!< 0x08000000 */
+#define HRTIM_CPT1CR_TIMDCMP2         HRTIM_CPT1CR_TIMDCMP2_Msk                /*!< Timer D compare 2 */
+
+#define HRTIM_CPT1CR_TE1SET_Pos       (28U)
+#define HRTIM_CPT1CR_TE1SET_Msk       (0x1UL << HRTIM_CPT1CR_TE1SET_Pos)       /*!< 0x10000000 */
+#define HRTIM_CPT1CR_TE1SET           HRTIM_CPT1CR_TE1SET_Msk                  /*!< Timer E output 1 set */
+#define HRTIM_CPT1CR_TE1RST_Pos       (29U)
+#define HRTIM_CPT1CR_TE1RST_Msk       (0x1UL << HRTIM_CPT1CR_TE1RST_Pos)       /*!< 0x20000000 */
+#define HRTIM_CPT1CR_TE1RST           HRTIM_CPT1CR_TE1RST_Msk                  /*!< Timer E output 1 reset */
+#define HRTIM_CPT1CR_TIMECMP1_Pos     (30U)
+#define HRTIM_CPT1CR_TIMECMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMECMP1_Pos)     /*!< 0x40000000 */
+#define HRTIM_CPT1CR_TIMECMP1         HRTIM_CPT1CR_TIMECMP1_Msk                /*!< Timer E compare 1 */
+#define HRTIM_CPT1CR_TIMECMP2_Pos     (31U)
+#define HRTIM_CPT1CR_TIMECMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMECMP2_Pos)     /*!< 0x80000000 */
+#define HRTIM_CPT1CR_TIMECMP2         HRTIM_CPT1CR_TIMECMP2_Msk                /*!< Timer E compare 2 */
+
+/**** Bit definition for Slave Timer Capture 2 control register ***************/
+#define HRTIM_CPT2CR_SWCPT_Pos        (0U)
+#define HRTIM_CPT2CR_SWCPT_Msk        (0x1UL << HRTIM_CPT2CR_SWCPT_Pos)        /*!< 0x00000001 */
+#define HRTIM_CPT2CR_SWCPT            HRTIM_CPT2CR_SWCPT_Msk                   /*!< Software capture */
+#define HRTIM_CPT2CR_UPDCPT_Pos       (1U)
+#define HRTIM_CPT2CR_UPDCPT_Msk       (0x1UL << HRTIM_CPT2CR_UPDCPT_Pos)       /*!< 0x00000002 */
+#define HRTIM_CPT2CR_UPDCPT           HRTIM_CPT2CR_UPDCPT_Msk                  /*!< Update capture */
+#define HRTIM_CPT2CR_EXEV1CPT_Pos     (2U)
+#define HRTIM_CPT2CR_EXEV1CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV1CPT_Pos)     /*!< 0x00000004 */
+#define HRTIM_CPT2CR_EXEV1CPT         HRTIM_CPT2CR_EXEV1CPT_Msk                /*!< External event 1 capture */
+#define HRTIM_CPT2CR_EXEV2CPT_Pos     (3U)
+#define HRTIM_CPT2CR_EXEV2CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV2CPT_Pos)     /*!< 0x00000008 */
+#define HRTIM_CPT2CR_EXEV2CPT         HRTIM_CPT2CR_EXEV2CPT_Msk                /*!< External event 2 capture */
+#define HRTIM_CPT2CR_EXEV3CPT_Pos     (4U)
+#define HRTIM_CPT2CR_EXEV3CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV3CPT_Pos)     /*!< 0x00000010 */
+#define HRTIM_CPT2CR_EXEV3CPT         HRTIM_CPT2CR_EXEV3CPT_Msk                /*!< External event 3 capture */
+#define HRTIM_CPT2CR_EXEV4CPT_Pos     (5U)
+#define HRTIM_CPT2CR_EXEV4CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV4CPT_Pos)     /*!< 0x00000020 */
+#define HRTIM_CPT2CR_EXEV4CPT         HRTIM_CPT2CR_EXEV4CPT_Msk                /*!< External event 4 capture */
+#define HRTIM_CPT2CR_EXEV5CPT_Pos     (6U)
+#define HRTIM_CPT2CR_EXEV5CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV5CPT_Pos)     /*!< 0x00000040 */
+#define HRTIM_CPT2CR_EXEV5CPT         HRTIM_CPT2CR_EXEV5CPT_Msk                /*!< External event 5 capture */
+#define HRTIM_CPT2CR_EXEV6CPT_Pos     (7U)
+#define HRTIM_CPT2CR_EXEV6CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV6CPT_Pos)     /*!< 0x00000080 */
+#define HRTIM_CPT2CR_EXEV6CPT         HRTIM_CPT2CR_EXEV6CPT_Msk                /*!< External event 6 capture */
+#define HRTIM_CPT2CR_EXEV7CPT_Pos     (8U)
+#define HRTIM_CPT2CR_EXEV7CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV7CPT_Pos)     /*!< 0x00000100 */
+#define HRTIM_CPT2CR_EXEV7CPT         HRTIM_CPT2CR_EXEV7CPT_Msk                /*!< External event 7 capture */
+#define HRTIM_CPT2CR_EXEV8CPT_Pos     (9U)
+#define HRTIM_CPT2CR_EXEV8CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV8CPT_Pos)     /*!< 0x00000200 */
+#define HRTIM_CPT2CR_EXEV8CPT         HRTIM_CPT2CR_EXEV8CPT_Msk                /*!< External event 8 capture */
+#define HRTIM_CPT2CR_EXEV9CPT_Pos     (10U)
+#define HRTIM_CPT2CR_EXEV9CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV9CPT_Pos)     /*!< 0x00000400 */
+#define HRTIM_CPT2CR_EXEV9CPT         HRTIM_CPT2CR_EXEV9CPT_Msk                /*!< External event 9 capture */
+#define HRTIM_CPT2CR_EXEV10CPT_Pos    (11U)
+#define HRTIM_CPT2CR_EXEV10CPT_Msk    (0x1UL << HRTIM_CPT2CR_EXEV10CPT_Pos)    /*!< 0x00000800 */
+#define HRTIM_CPT2CR_EXEV10CPT        HRTIM_CPT2CR_EXEV10CPT_Msk               /*!< External event 10 capture */
+
+#define HRTIM_CPT2CR_TA1SET_Pos       (12U)
+#define HRTIM_CPT2CR_TA1SET_Msk       (0x1UL << HRTIM_CPT2CR_TA1SET_Pos)       /*!< 0x00001000 */
+#define HRTIM_CPT2CR_TA1SET           HRTIM_CPT2CR_TA1SET_Msk                  /*!< Timer A output 1 set */
+#define HRTIM_CPT2CR_TA1RST_Pos       (13U)
+#define HRTIM_CPT2CR_TA1RST_Msk       (0x1UL << HRTIM_CPT2CR_TA1RST_Pos)       /*!< 0x00002000 */
+#define HRTIM_CPT2CR_TA1RST           HRTIM_CPT2CR_TA1RST_Msk                  /*!< Timer A output 1 reset */
+#define HRTIM_CPT2CR_TIMACMP1_Pos     (14U)
+#define HRTIM_CPT2CR_TIMACMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMACMP1_Pos)     /*!< 0x00004000 */
+#define HRTIM_CPT2CR_TIMACMP1         HRTIM_CPT2CR_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_CPT2CR_TIMACMP2_Pos     (15U)
+#define HRTIM_CPT2CR_TIMACMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMACMP2_Pos)     /*!< 0x00008000 */
+#define HRTIM_CPT2CR_TIMACMP2         HRTIM_CPT2CR_TIMACMP2_Msk                /*!< Timer A compare 2 */
+
+#define HRTIM_CPT2CR_TB1SET_Pos       (16U)
+#define HRTIM_CPT2CR_TB1SET_Msk       (0x1UL << HRTIM_CPT2CR_TB1SET_Pos)       /*!< 0x00010000 */
+#define HRTIM_CPT2CR_TB1SET           HRTIM_CPT2CR_TB1SET_Msk                  /*!< Timer B output 1 set */
+#define HRTIM_CPT2CR_TB1RST_Pos       (17U)
+#define HRTIM_CPT2CR_TB1RST_Msk       (0x1UL << HRTIM_CPT2CR_TB1RST_Pos)       /*!< 0x00020000 */
+#define HRTIM_CPT2CR_TB1RST           HRTIM_CPT2CR_TB1RST_Msk                  /*!< Timer B output 1 reset */
+#define HRTIM_CPT2CR_TIMBCMP1_Pos     (18U)
+#define HRTIM_CPT2CR_TIMBCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMBCMP1_Pos)     /*!< 0x00040000 */
+#define HRTIM_CPT2CR_TIMBCMP1         HRTIM_CPT2CR_TIMBCMP1_Msk                /*!< Timer B compare 1 */
+#define HRTIM_CPT2CR_TIMBCMP2_Pos     (19U)
+#define HRTIM_CPT2CR_TIMBCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMBCMP2_Pos)     /*!< 0x00080000 */
+#define HRTIM_CPT2CR_TIMBCMP2         HRTIM_CPT2CR_TIMBCMP2_Msk                /*!< Timer B compare 2 */
+
+#define HRTIM_CPT2CR_TC1SET_Pos       (20U)
+#define HRTIM_CPT2CR_TC1SET_Msk       (0x1UL << HRTIM_CPT2CR_TC1SET_Pos)       /*!< 0x00100000 */
+#define HRTIM_CPT2CR_TC1SET           HRTIM_CPT2CR_TC1SET_Msk                  /*!< Timer C output 1 set */
+#define HRTIM_CPT2CR_TC1RST_Pos       (21U)
+#define HRTIM_CPT2CR_TC1RST_Msk       (0x1UL << HRTIM_CPT2CR_TC1RST_Pos)       /*!< 0x00200000 */
+#define HRTIM_CPT2CR_TC1RST           HRTIM_CPT2CR_TC1RST_Msk                  /*!< Timer C output 1 reset */
+#define HRTIM_CPT2CR_TIMCCMP1_Pos     (22U)
+#define HRTIM_CPT2CR_TIMCCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMCCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_CPT2CR_TIMCCMP1         HRTIM_CPT2CR_TIMCCMP1_Msk                /*!< Timer C compare 1 */
+#define HRTIM_CPT2CR_TIMCCMP2_Pos     (23U)
+#define HRTIM_CPT2CR_TIMCCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMCCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_CPT2CR_TIMCCMP2         HRTIM_CPT2CR_TIMCCMP2_Msk                /*!< Timer C compare 2 */
+
+#define HRTIM_CPT2CR_TD1SET_Pos       (24U)
+#define HRTIM_CPT2CR_TD1SET_Msk       (0x1UL << HRTIM_CPT2CR_TD1SET_Pos)       /*!< 0x01000000 */
+#define HRTIM_CPT2CR_TD1SET           HRTIM_CPT2CR_TD1SET_Msk                  /*!< Timer D output 1 set */
+#define HRTIM_CPT2CR_TD1RST_Pos       (25U)
+#define HRTIM_CPT2CR_TD1RST_Msk       (0x1UL << HRTIM_CPT2CR_TD1RST_Pos)       /*!< 0x02000000 */
+#define HRTIM_CPT2CR_TD1RST           HRTIM_CPT2CR_TD1RST_Msk                  /*!< Timer D output 1 reset */
+#define HRTIM_CPT2CR_TIMDCMP1_Pos     (26U)
+#define HRTIM_CPT2CR_TIMDCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMDCMP1_Pos)     /*!< 0x04000000 */
+#define HRTIM_CPT2CR_TIMDCMP1         HRTIM_CPT2CR_TIMDCMP1_Msk                /*!< Timer D compare 1 */
+#define HRTIM_CPT2CR_TIMDCMP2_Pos     (27U)
+#define HRTIM_CPT2CR_TIMDCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMDCMP2_Pos)     /*!< 0x08000000 */
+#define HRTIM_CPT2CR_TIMDCMP2         HRTIM_CPT2CR_TIMDCMP2_Msk                /*!< Timer D compare 2 */
+
+#define HRTIM_CPT2CR_TE1SET_Pos       (28U)
+#define HRTIM_CPT2CR_TE1SET_Msk       (0x1UL << HRTIM_CPT2CR_TE1SET_Pos)       /*!< 0x10000000 */
+#define HRTIM_CPT2CR_TE1SET           HRTIM_CPT2CR_TE1SET_Msk                  /*!< Timer E output 1 set */
+#define HRTIM_CPT2CR_TE1RST_Pos       (29U)
+#define HRTIM_CPT2CR_TE1RST_Msk       (0x1UL << HRTIM_CPT2CR_TE1RST_Pos)       /*!< 0x20000000 */
+#define HRTIM_CPT2CR_TE1RST           HRTIM_CPT2CR_TE1RST_Msk                  /*!< Timer E output 1 reset */
+#define HRTIM_CPT2CR_TIMECMP1_Pos     (30U)
+#define HRTIM_CPT2CR_TIMECMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMECMP1_Pos)     /*!< 0x40000000 */
+#define HRTIM_CPT2CR_TIMECMP1         HRTIM_CPT2CR_TIMECMP1_Msk                /*!< Timer E compare 1 */
+#define HRTIM_CPT2CR_TIMECMP2_Pos     (31U)
+#define HRTIM_CPT2CR_TIMECMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMECMP2_Pos)     /*!< 0x80000000 */
+#define HRTIM_CPT2CR_TIMECMP2         HRTIM_CPT2CR_TIMECMP2_Msk                /*!< Timer E compare 2 */
+
+/**** Bit definition for Slave Timer Output register **************************/
+#define HRTIM_OUTR_POL1_Pos           (1U)
+#define HRTIM_OUTR_POL1_Msk           (0x1UL << HRTIM_OUTR_POL1_Pos)           /*!< 0x00000002 */
+#define HRTIM_OUTR_POL1               HRTIM_OUTR_POL1_Msk                      /*!< Slave output 1 polarity */
+#define HRTIM_OUTR_IDLM1_Pos          (2U)
+#define HRTIM_OUTR_IDLM1_Msk          (0x1UL << HRTIM_OUTR_IDLM1_Pos)          /*!< 0x00000004 */
+#define HRTIM_OUTR_IDLM1              HRTIM_OUTR_IDLM1_Msk                     /*!< Slave output 1 idle mode */
+#define HRTIM_OUTR_IDLES1_Pos         (3U)
+#define HRTIM_OUTR_IDLES1_Msk         (0x1UL << HRTIM_OUTR_IDLES1_Pos)         /*!< 0x00000008 */
+#define HRTIM_OUTR_IDLES1             HRTIM_OUTR_IDLES1_Msk                    /*!< Slave output 1 idle state */
+#define HRTIM_OUTR_FAULT1_Pos         (4U)
+#define HRTIM_OUTR_FAULT1_Msk         (0x3UL << HRTIM_OUTR_FAULT1_Pos)         /*!< 0x00000030 */
+#define HRTIM_OUTR_FAULT1             HRTIM_OUTR_FAULT1_Msk                    /*!< Slave output 1 fault state */
+#define HRTIM_OUTR_FAULT1_0           (0x1UL << HRTIM_OUTR_FAULT1_Pos)          /*!< 0x00000010 */
+#define HRTIM_OUTR_FAULT1_1           (0x2UL << HRTIM_OUTR_FAULT1_Pos)          /*!< 0x00000020 */
+#define HRTIM_OUTR_CHP1_Pos           (6U)
+#define HRTIM_OUTR_CHP1_Msk           (0x1UL << HRTIM_OUTR_CHP1_Pos)           /*!< 0x00000040 */
+#define HRTIM_OUTR_CHP1               HRTIM_OUTR_CHP1_Msk                      /*!< Slave output 1 chopper enable */
+#define HRTIM_OUTR_DIDL1_Pos          (7U)
+#define HRTIM_OUTR_DIDL1_Msk          (0x1UL << HRTIM_OUTR_DIDL1_Pos)          /*!< 0x00000080 */
+#define HRTIM_OUTR_DIDL1              HRTIM_OUTR_DIDL1_Msk                     /*!< Slave output 1 dead time idle */
+
+#define HRTIM_OUTR_DTEN_Pos           (8U)
+#define HRTIM_OUTR_DTEN_Msk           (0x1UL << HRTIM_OUTR_DTEN_Pos)           /*!< 0x00000100 */
+#define HRTIM_OUTR_DTEN               HRTIM_OUTR_DTEN_Msk                      /*!< Slave output deadtime enable */
+#define HRTIM_OUTR_DLYPRTEN_Pos       (9U)
+#define HRTIM_OUTR_DLYPRTEN_Msk       (0x1UL << HRTIM_OUTR_DLYPRTEN_Pos)       /*!< 0x00000200 */
+#define HRTIM_OUTR_DLYPRTEN           HRTIM_OUTR_DLYPRTEN_Msk                  /*!< Slave output delay protection enable */
+#define HRTIM_OUTR_DLYPRT_Pos         (10U)
+#define HRTIM_OUTR_DLYPRT_Msk         (0x7UL << HRTIM_OUTR_DLYPRT_Pos)         /*!< 0x00001C00 */
+#define HRTIM_OUTR_DLYPRT             HRTIM_OUTR_DLYPRT_Msk                    /*!< Slave output delay protection */
+#define HRTIM_OUTR_DLYPRT_0           (0x1UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00000400 */
+#define HRTIM_OUTR_DLYPRT_1           (0x2UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00000800 */
+#define HRTIM_OUTR_DLYPRT_2           (0x4UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00001000 */
+
+#define HRTIM_OUTR_POL2_Pos           (17U)
+#define HRTIM_OUTR_POL2_Msk           (0x1UL << HRTIM_OUTR_POL2_Pos)           /*!< 0x00020000 */
+#define HRTIM_OUTR_POL2               HRTIM_OUTR_POL2_Msk                      /*!< Slave output 2 polarity */
+#define HRTIM_OUTR_IDLM2_Pos          (18U)
+#define HRTIM_OUTR_IDLM2_Msk          (0x1UL << HRTIM_OUTR_IDLM2_Pos)          /*!< 0x00040000 */
+#define HRTIM_OUTR_IDLM2              HRTIM_OUTR_IDLM2_Msk                     /*!< Slave output 2 idle mode */
+#define HRTIM_OUTR_IDLES2_Pos         (19U)
+#define HRTIM_OUTR_IDLES2_Msk         (0x1UL << HRTIM_OUTR_IDLES2_Pos)         /*!< 0x00080000 */
+#define HRTIM_OUTR_IDLES2             HRTIM_OUTR_IDLES2_Msk                    /*!< Slave output 2 idle state */
+#define HRTIM_OUTR_FAULT2_Pos         (20U)
+#define HRTIM_OUTR_FAULT2_Msk         (0x3UL << HRTIM_OUTR_FAULT2_Pos)         /*!< 0x00300000 */
+#define HRTIM_OUTR_FAULT2             HRTIM_OUTR_FAULT2_Msk                    /*!< Slave output 2 fault state */
+#define HRTIM_OUTR_FAULT2_0           (0x1UL << HRTIM_OUTR_FAULT2_Pos)          /*!< 0x00100000 */
+#define HRTIM_OUTR_FAULT2_1           (0x2UL << HRTIM_OUTR_FAULT2_Pos)          /*!< 0x00200000 */
+#define HRTIM_OUTR_CHP2_Pos           (22U)
+#define HRTIM_OUTR_CHP2_Msk           (0x1UL << HRTIM_OUTR_CHP2_Pos)           /*!< 0x00400000 */
+#define HRTIM_OUTR_CHP2               HRTIM_OUTR_CHP2_Msk                      /*!< Slave output 2 chopper enable */
+#define HRTIM_OUTR_DIDL2_Pos          (23U)
+#define HRTIM_OUTR_DIDL2_Msk          (0x1UL << HRTIM_OUTR_DIDL2_Pos)          /*!< 0x00800000 */
+#define HRTIM_OUTR_DIDL2              HRTIM_OUTR_DIDL2_Msk                     /*!< Slave output 2 dead time idle */
+
+/**** Bit definition for Slave Timer Fault register ***************************/
+#define HRTIM_FLTR_FLT1EN_Pos         (0U)
+#define HRTIM_FLTR_FLT1EN_Msk         (0x1UL << HRTIM_FLTR_FLT1EN_Pos)         /*!< 0x00000001 */
+#define HRTIM_FLTR_FLT1EN             HRTIM_FLTR_FLT1EN_Msk                    /*!< Fault 1 enable */
+#define HRTIM_FLTR_FLT2EN_Pos         (1U)
+#define HRTIM_FLTR_FLT2EN_Msk         (0x1UL << HRTIM_FLTR_FLT2EN_Pos)         /*!< 0x00000002 */
+#define HRTIM_FLTR_FLT2EN             HRTIM_FLTR_FLT2EN_Msk                    /*!< Fault 2 enable */
+#define HRTIM_FLTR_FLT3EN_Pos         (2U)
+#define HRTIM_FLTR_FLT3EN_Msk         (0x1UL << HRTIM_FLTR_FLT3EN_Pos)         /*!< 0x00000004 */
+#define HRTIM_FLTR_FLT3EN             HRTIM_FLTR_FLT3EN_Msk                    /*!< Fault 3 enable */
+#define HRTIM_FLTR_FLT4EN_Pos         (3U)
+#define HRTIM_FLTR_FLT4EN_Msk         (0x1UL << HRTIM_FLTR_FLT4EN_Pos)         /*!< 0x00000008 */
+#define HRTIM_FLTR_FLT4EN             HRTIM_FLTR_FLT4EN_Msk                    /*!< Fault 4 enable */
+#define HRTIM_FLTR_FLT5EN_Pos         (4U)
+#define HRTIM_FLTR_FLT5EN_Msk         (0x1UL << HRTIM_FLTR_FLT5EN_Pos)         /*!< 0x00000010 */
+#define HRTIM_FLTR_FLT5EN             HRTIM_FLTR_FLT5EN_Msk                    /*!< Fault 5 enable */
+#define HRTIM_FLTR_FLTLCK_Pos         (31U)
+#define HRTIM_FLTR_FLTLCK_Msk         (0x1UL << HRTIM_FLTR_FLTLCK_Pos)         /*!< 0x80000000 */
+#define HRTIM_FLTR_FLTLCK             HRTIM_FLTR_FLTLCK_Msk                    /*!< Fault sources lock */
+
+/**** Bit definition for Common HRTIM Timer control register 1 ****************/
+#define HRTIM_CR1_MUDIS_Pos           (0U)
+#define HRTIM_CR1_MUDIS_Msk           (0x1UL << HRTIM_CR1_MUDIS_Pos)           /*!< 0x00000001 */
+#define HRTIM_CR1_MUDIS               HRTIM_CR1_MUDIS_Msk                      /*!< Master update disable*/
+#define HRTIM_CR1_TAUDIS_Pos          (1U)
+#define HRTIM_CR1_TAUDIS_Msk          (0x1UL << HRTIM_CR1_TAUDIS_Pos)          /*!< 0x00000002 */
+#define HRTIM_CR1_TAUDIS              HRTIM_CR1_TAUDIS_Msk                     /*!< Timer A update disable*/
+#define HRTIM_CR1_TBUDIS_Pos          (2U)
+#define HRTIM_CR1_TBUDIS_Msk          (0x1UL << HRTIM_CR1_TBUDIS_Pos)          /*!< 0x00000004 */
+#define HRTIM_CR1_TBUDIS              HRTIM_CR1_TBUDIS_Msk                     /*!< Timer B update disable*/
+#define HRTIM_CR1_TCUDIS_Pos          (3U)
+#define HRTIM_CR1_TCUDIS_Msk          (0x1UL << HRTIM_CR1_TCUDIS_Pos)          /*!< 0x00000008 */
+#define HRTIM_CR1_TCUDIS              HRTIM_CR1_TCUDIS_Msk                     /*!< Timer C update disable*/
+#define HRTIM_CR1_TDUDIS_Pos          (4U)
+#define HRTIM_CR1_TDUDIS_Msk          (0x1UL << HRTIM_CR1_TDUDIS_Pos)          /*!< 0x00000010 */
+#define HRTIM_CR1_TDUDIS              HRTIM_CR1_TDUDIS_Msk                     /*!< Timer D update disable*/
+#define HRTIM_CR1_TEUDIS_Pos          (5U)
+#define HRTIM_CR1_TEUDIS_Msk          (0x1UL << HRTIM_CR1_TEUDIS_Pos)          /*!< 0x00000020 */
+#define HRTIM_CR1_TEUDIS              HRTIM_CR1_TEUDIS_Msk                     /*!< Timer E update disable*/
+#define HRTIM_CR1_ADC1USRC_Pos        (16U)
+#define HRTIM_CR1_ADC1USRC_Msk        (0x7UL << HRTIM_CR1_ADC1USRC_Pos)        /*!< 0x00070000 */
+#define HRTIM_CR1_ADC1USRC            HRTIM_CR1_ADC1USRC_Msk                   /*!< ADC Trigger 1 update source */
+#define HRTIM_CR1_ADC1USRC_0          (0x1UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00010000 */
+#define HRTIM_CR1_ADC1USRC_1          (0x2UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00020000 */
+#define HRTIM_CR1_ADC1USRC_2          (0x4UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00040000 */
+#define HRTIM_CR1_ADC2USRC_Pos        (19U)
+#define HRTIM_CR1_ADC2USRC_Msk        (0x7UL << HRTIM_CR1_ADC2USRC_Pos)        /*!< 0x00380000 */
+#define HRTIM_CR1_ADC2USRC            HRTIM_CR1_ADC2USRC_Msk                   /*!< ADC Trigger 2 update source */
+#define HRTIM_CR1_ADC2USRC_0          (0x1UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00080000 */
+#define HRTIM_CR1_ADC2USRC_1          (0x2UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00100000 */
+#define HRTIM_CR1_ADC2USRC_2          (0x4UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00200000 */
+#define HRTIM_CR1_ADC3USRC_Pos        (22U)
+#define HRTIM_CR1_ADC3USRC_Msk        (0x7UL << HRTIM_CR1_ADC3USRC_Pos)        /*!< 0x01C00000 */
+#define HRTIM_CR1_ADC3USRC            HRTIM_CR1_ADC3USRC_Msk                   /*!< ADC Trigger 3 update source */
+#define HRTIM_CR1_ADC3USRC_0          (0x1UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x00400000 */
+#define HRTIM_CR1_ADC3USRC_1          (0x2UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x00800000 */
+#define HRTIM_CR1_ADC3USRC_2          (0x4UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x01000000 */
+#define HRTIM_CR1_ADC4USRC_Pos        (25U)
+#define HRTIM_CR1_ADC4USRC_Msk        (0x7UL << HRTIM_CR1_ADC4USRC_Pos)        /*!< 0x0E000000 */
+#define HRTIM_CR1_ADC4USRC            HRTIM_CR1_ADC4USRC_Msk                   /*!< ADC Trigger 4 update source */
+#define HRTIM_CR1_ADC4USRC_0          (0x1UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x02000000 */
+#define HRTIM_CR1_ADC4USRC_1          (0x2UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x04000000 */
+#define HRTIM_CR1_ADC4USRC_2          (0x0UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x0800000 */
+
+/**** Bit definition for Common HRTIM Timer control register 2 ****************/
+#define HRTIM_CR2_MSWU_Pos            (0U)
+#define HRTIM_CR2_MSWU_Msk            (0x1UL << HRTIM_CR2_MSWU_Pos)            /*!< 0x00000001 */
+#define HRTIM_CR2_MSWU                HRTIM_CR2_MSWU_Msk                       /*!< Master software update */
+#define HRTIM_CR2_TASWU_Pos           (1U)
+#define HRTIM_CR2_TASWU_Msk           (0x1UL << HRTIM_CR2_TASWU_Pos)           /*!< 0x00000002 */
+#define HRTIM_CR2_TASWU               HRTIM_CR2_TASWU_Msk                      /*!< Timer A software update */
+#define HRTIM_CR2_TBSWU_Pos           (2U)
+#define HRTIM_CR2_TBSWU_Msk           (0x1UL << HRTIM_CR2_TBSWU_Pos)           /*!< 0x00000004 */
+#define HRTIM_CR2_TBSWU               HRTIM_CR2_TBSWU_Msk                      /*!< Timer B software update */
+#define HRTIM_CR2_TCSWU_Pos           (3U)
+#define HRTIM_CR2_TCSWU_Msk           (0x1UL << HRTIM_CR2_TCSWU_Pos)           /*!< 0x00000008 */
+#define HRTIM_CR2_TCSWU               HRTIM_CR2_TCSWU_Msk                      /*!< Timer C software update */
+#define HRTIM_CR2_TDSWU_Pos           (4U)
+#define HRTIM_CR2_TDSWU_Msk           (0x1UL << HRTIM_CR2_TDSWU_Pos)           /*!< 0x00000010 */
+#define HRTIM_CR2_TDSWU               HRTIM_CR2_TDSWU_Msk                      /*!< Timer D software update */
+#define HRTIM_CR2_TESWU_Pos           (5U)
+#define HRTIM_CR2_TESWU_Msk           (0x1UL << HRTIM_CR2_TESWU_Pos)           /*!< 0x00000020 */
+#define HRTIM_CR2_TESWU               HRTIM_CR2_TESWU_Msk                      /*!< Timer E software update */
+#define HRTIM_CR2_MRST_Pos            (8U)
+#define HRTIM_CR2_MRST_Msk            (0x1UL << HRTIM_CR2_MRST_Pos)            /*!< 0x00000100 */
+#define HRTIM_CR2_MRST                HRTIM_CR2_MRST_Msk                       /*!< Master count software reset */
+#define HRTIM_CR2_TARST_Pos           (9U)
+#define HRTIM_CR2_TARST_Msk           (0x1UL << HRTIM_CR2_TARST_Pos)           /*!< 0x00000200 */
+#define HRTIM_CR2_TARST               HRTIM_CR2_TARST_Msk                      /*!< Timer A count software reset */
+#define HRTIM_CR2_TBRST_Pos           (10U)
+#define HRTIM_CR2_TBRST_Msk           (0x1UL << HRTIM_CR2_TBRST_Pos)           /*!< 0x00000400 */
+#define HRTIM_CR2_TBRST               HRTIM_CR2_TBRST_Msk                      /*!< Timer B count software reset */
+#define HRTIM_CR2_TCRST_Pos           (11U)
+#define HRTIM_CR2_TCRST_Msk           (0x1UL << HRTIM_CR2_TCRST_Pos)           /*!< 0x00000800 */
+#define HRTIM_CR2_TCRST               HRTIM_CR2_TCRST_Msk                      /*!< Timer C count software reset */
+#define HRTIM_CR2_TDRST_Pos           (12U)
+#define HRTIM_CR2_TDRST_Msk           (0x1UL << HRTIM_CR2_TDRST_Pos)           /*!< 0x00001000 */
+#define HRTIM_CR2_TDRST               HRTIM_CR2_TDRST_Msk                      /*!< Timer D count software reset */
+#define HRTIM_CR2_TERST_Pos           (13U)
+#define HRTIM_CR2_TERST_Msk           (0x1UL << HRTIM_CR2_TERST_Pos)           /*!< 0x00002000 */
+#define HRTIM_CR2_TERST               HRTIM_CR2_TERST_Msk                      /*!< Timer E count software reset */
+
+/**** Bit definition for Common HRTIM Timer interrupt status register *********/
+#define HRTIM_ISR_FLT1_Pos            (0U)
+#define HRTIM_ISR_FLT1_Msk            (0x1UL << HRTIM_ISR_FLT1_Pos)            /*!< 0x00000001 */
+#define HRTIM_ISR_FLT1                HRTIM_ISR_FLT1_Msk                       /*!< Fault 1 interrupt flag */
+#define HRTIM_ISR_FLT2_Pos            (1U)
+#define HRTIM_ISR_FLT2_Msk            (0x1UL << HRTIM_ISR_FLT2_Pos)            /*!< 0x00000002 */
+#define HRTIM_ISR_FLT2                HRTIM_ISR_FLT2_Msk                       /*!< Fault 2 interrupt flag */
+#define HRTIM_ISR_FLT3_Pos            (2U)
+#define HRTIM_ISR_FLT3_Msk            (0x1UL << HRTIM_ISR_FLT3_Pos)            /*!< 0x00000004 */
+#define HRTIM_ISR_FLT3                HRTIM_ISR_FLT3_Msk                       /*!< Fault 3 interrupt flag */
+#define HRTIM_ISR_FLT4_Pos            (3U)
+#define HRTIM_ISR_FLT4_Msk            (0x1UL << HRTIM_ISR_FLT4_Pos)            /*!< 0x00000008 */
+#define HRTIM_ISR_FLT4                HRTIM_ISR_FLT4_Msk                       /*!< Fault 4 interrupt flag */
+#define HRTIM_ISR_FLT5_Pos            (4U)
+#define HRTIM_ISR_FLT5_Msk            (0x1UL << HRTIM_ISR_FLT5_Pos)            /*!< 0x00000010 */
+#define HRTIM_ISR_FLT5                HRTIM_ISR_FLT5_Msk                       /*!< Fault 5 interrupt flag */
+#define HRTIM_ISR_SYSFLT_Pos          (5U)
+#define HRTIM_ISR_SYSFLT_Msk          (0x1UL << HRTIM_ISR_SYSFLT_Pos)          /*!< 0x00000020 */
+#define HRTIM_ISR_SYSFLT              HRTIM_ISR_SYSFLT_Msk                     /*!< System Fault interrupt flag */
+#define HRTIM_ISR_BMPER_Pos           (17U)
+#define HRTIM_ISR_BMPER_Msk           (0x1UL << HRTIM_ISR_BMPER_Pos)           /*!< 0x00020000 */
+#define HRTIM_ISR_BMPER               HRTIM_ISR_BMPER_Msk                      /*!<  Burst mode period interrupt flag */
+
+/**** Bit definition for Common HRTIM Timer interrupt clear register **********/
+#define HRTIM_ICR_FLT1C_Pos           (0U)
+#define HRTIM_ICR_FLT1C_Msk           (0x1UL << HRTIM_ICR_FLT1C_Pos)           /*!< 0x00000001 */
+#define HRTIM_ICR_FLT1C               HRTIM_ICR_FLT1C_Msk                      /*!< Fault 1 interrupt flag clear */
+#define HRTIM_ICR_FLT2C_Pos           (1U)
+#define HRTIM_ICR_FLT2C_Msk           (0x1UL << HRTIM_ICR_FLT2C_Pos)           /*!< 0x00000002 */
+#define HRTIM_ICR_FLT2C               HRTIM_ICR_FLT2C_Msk                      /*!< Fault 2 interrupt flag clear */
+#define HRTIM_ICR_FLT3C_Pos           (2U)
+#define HRTIM_ICR_FLT3C_Msk           (0x1UL << HRTIM_ICR_FLT3C_Pos)           /*!< 0x00000004 */
+#define HRTIM_ICR_FLT3C               HRTIM_ICR_FLT3C_Msk                      /*!< Fault 3 interrupt flag clear */
+#define HRTIM_ICR_FLT4C_Pos           (3U)
+#define HRTIM_ICR_FLT4C_Msk           (0x1UL << HRTIM_ICR_FLT4C_Pos)           /*!< 0x00000008 */
+#define HRTIM_ICR_FLT4C               HRTIM_ICR_FLT4C_Msk                      /*!< Fault 4 interrupt flag clear */
+#define HRTIM_ICR_FLT5C_Pos           (4U)
+#define HRTIM_ICR_FLT5C_Msk           (0x1UL << HRTIM_ICR_FLT5C_Pos)           /*!< 0x00000010 */
+#define HRTIM_ICR_FLT5C               HRTIM_ICR_FLT5C_Msk                      /*!< Fault 5 interrupt flag clear */
+#define HRTIM_ICR_SYSFLTC_Pos         (5U)
+#define HRTIM_ICR_SYSFLTC_Msk         (0x1UL << HRTIM_ICR_SYSFLTC_Pos)         /*!< 0x00000020 */
+#define HRTIM_ICR_SYSFLTC             HRTIM_ICR_SYSFLTC_Msk                    /*!< System Fault interrupt flag clear */
+#define HRTIM_ICR_BMPERC_Pos          (17U)
+#define HRTIM_ICR_BMPERC_Msk          (0x1UL << HRTIM_ICR_BMPERC_Pos)          /*!< 0x00020000 */
+#define HRTIM_ICR_BMPERC              HRTIM_ICR_BMPERC_Msk                     /*!<  Burst mode period interrupt flag clear */
+
+/**** Bit definition for Common HRTIM Timer interrupt enable register *********/
+#define HRTIM_IER_FLT1_Pos            (0U)
+#define HRTIM_IER_FLT1_Msk            (0x1UL << HRTIM_IER_FLT1_Pos)            /*!< 0x00000001 */
+#define HRTIM_IER_FLT1                HRTIM_IER_FLT1_Msk                       /*!< Fault 1 interrupt enable */
+#define HRTIM_IER_FLT2_Pos            (1U)
+#define HRTIM_IER_FLT2_Msk            (0x1UL << HRTIM_IER_FLT2_Pos)            /*!< 0x00000002 */
+#define HRTIM_IER_FLT2                HRTIM_IER_FLT2_Msk                       /*!< Fault 2 interrupt enable */
+#define HRTIM_IER_FLT3_Pos            (2U)
+#define HRTIM_IER_FLT3_Msk            (0x1UL << HRTIM_IER_FLT3_Pos)            /*!< 0x00000004 */
+#define HRTIM_IER_FLT3                HRTIM_IER_FLT3_Msk                       /*!< Fault 3 interrupt enable */
+#define HRTIM_IER_FLT4_Pos            (3U)
+#define HRTIM_IER_FLT4_Msk            (0x1UL << HRTIM_IER_FLT4_Pos)            /*!< 0x00000008 */
+#define HRTIM_IER_FLT4                HRTIM_IER_FLT4_Msk                       /*!< Fault 4 interrupt enable */
+#define HRTIM_IER_FLT5_Pos            (4U)
+#define HRTIM_IER_FLT5_Msk            (0x1UL << HRTIM_IER_FLT5_Pos)            /*!< 0x00000010 */
+#define HRTIM_IER_FLT5                HRTIM_IER_FLT5_Msk                       /*!< Fault 5 interrupt enable */
+#define HRTIM_IER_SYSFLT_Pos          (5U)
+#define HRTIM_IER_SYSFLT_Msk          (0x1UL << HRTIM_IER_SYSFLT_Pos)          /*!< 0x00000020 */
+#define HRTIM_IER_SYSFLT              HRTIM_IER_SYSFLT_Msk                     /*!< System Fault interrupt enable */
+#define HRTIM_IER_BMPER_Pos           (17U)
+#define HRTIM_IER_BMPER_Msk           (0x1UL << HRTIM_IER_BMPER_Pos)           /*!< 0x00020000 */
+#define HRTIM_IER_BMPER               HRTIM_IER_BMPER_Msk                      /*!<  Burst mode period interrupt enable */
+
+/**** Bit definition for Common HRTIM Timer output enable register ************/
+#define HRTIM_OENR_TA1OEN_Pos         (0U)
+#define HRTIM_OENR_TA1OEN_Msk         (0x1UL << HRTIM_OENR_TA1OEN_Pos)         /*!< 0x00000001 */
+#define HRTIM_OENR_TA1OEN             HRTIM_OENR_TA1OEN_Msk                    /*!< Timer A Output 1 enable */
+#define HRTIM_OENR_TA2OEN_Pos         (1U)
+#define HRTIM_OENR_TA2OEN_Msk         (0x1UL << HRTIM_OENR_TA2OEN_Pos)         /*!< 0x00000002 */
+#define HRTIM_OENR_TA2OEN             HRTIM_OENR_TA2OEN_Msk                    /*!< Timer A Output 2 enable */
+#define HRTIM_OENR_TB1OEN_Pos         (2U)
+#define HRTIM_OENR_TB1OEN_Msk         (0x1UL << HRTIM_OENR_TB1OEN_Pos)         /*!< 0x00000004 */
+#define HRTIM_OENR_TB1OEN             HRTIM_OENR_TB1OEN_Msk                    /*!< Timer B Output 1 enable */
+#define HRTIM_OENR_TB2OEN_Pos         (3U)
+#define HRTIM_OENR_TB2OEN_Msk         (0x1UL << HRTIM_OENR_TB2OEN_Pos)         /*!< 0x00000008 */
+#define HRTIM_OENR_TB2OEN             HRTIM_OENR_TB2OEN_Msk                    /*!< Timer B Output 2 enable */
+#define HRTIM_OENR_TC1OEN_Pos         (4U)
+#define HRTIM_OENR_TC1OEN_Msk         (0x1UL << HRTIM_OENR_TC1OEN_Pos)         /*!< 0x00000010 */
+#define HRTIM_OENR_TC1OEN             HRTIM_OENR_TC1OEN_Msk                    /*!< Timer C Output 1 enable */
+#define HRTIM_OENR_TC2OEN_Pos         (5U)
+#define HRTIM_OENR_TC2OEN_Msk         (0x1UL << HRTIM_OENR_TC2OEN_Pos)         /*!< 0x00000020 */
+#define HRTIM_OENR_TC2OEN             HRTIM_OENR_TC2OEN_Msk                    /*!< Timer C Output 2 enable */
+#define HRTIM_OENR_TD1OEN_Pos         (6U)
+#define HRTIM_OENR_TD1OEN_Msk         (0x1UL << HRTIM_OENR_TD1OEN_Pos)         /*!< 0x00000040 */
+#define HRTIM_OENR_TD1OEN             HRTIM_OENR_TD1OEN_Msk                    /*!< Timer D Output 1 enable */
+#define HRTIM_OENR_TD2OEN_Pos         (7U)
+#define HRTIM_OENR_TD2OEN_Msk         (0x1UL << HRTIM_OENR_TD2OEN_Pos)         /*!< 0x00000080 */
+#define HRTIM_OENR_TD2OEN             HRTIM_OENR_TD2OEN_Msk                    /*!< Timer D Output 2 enable */
+#define HRTIM_OENR_TE1OEN_Pos         (8U)
+#define HRTIM_OENR_TE1OEN_Msk         (0x1UL << HRTIM_OENR_TE1OEN_Pos)         /*!< 0x00000100 */
+#define HRTIM_OENR_TE1OEN             HRTIM_OENR_TE1OEN_Msk                    /*!< Timer E Output 1 enable */
+#define HRTIM_OENR_TE2OEN_Pos         (9U)
+#define HRTIM_OENR_TE2OEN_Msk         (0x1UL << HRTIM_OENR_TE2OEN_Pos)         /*!< 0x00000200 */
+#define HRTIM_OENR_TE2OEN             HRTIM_OENR_TE2OEN_Msk                    /*!< Timer E Output 2 enable */
+
+/**** Bit definition for Common HRTIM Timer output disable register ***********/
+#define HRTIM_ODISR_TA1ODIS_Pos       (0U)
+#define HRTIM_ODISR_TA1ODIS_Msk       (0x1UL << HRTIM_ODISR_TA1ODIS_Pos)       /*!< 0x00000001 */
+#define HRTIM_ODISR_TA1ODIS           HRTIM_ODISR_TA1ODIS_Msk                  /*!< Timer A Output 1 disable */
+#define HRTIM_ODISR_TA2ODIS_Pos       (1U)
+#define HRTIM_ODISR_TA2ODIS_Msk       (0x1UL << HRTIM_ODISR_TA2ODIS_Pos)       /*!< 0x00000002 */
+#define HRTIM_ODISR_TA2ODIS           HRTIM_ODISR_TA2ODIS_Msk                  /*!< Timer A Output 2 disable */
+#define HRTIM_ODISR_TB1ODIS_Pos       (2U)
+#define HRTIM_ODISR_TB1ODIS_Msk       (0x1UL << HRTIM_ODISR_TB1ODIS_Pos)       /*!< 0x00000004 */
+#define HRTIM_ODISR_TB1ODIS           HRTIM_ODISR_TB1ODIS_Msk                  /*!< Timer B Output 1 disable */
+#define HRTIM_ODISR_TB2ODIS_Pos       (3U)
+#define HRTIM_ODISR_TB2ODIS_Msk       (0x1UL << HRTIM_ODISR_TB2ODIS_Pos)       /*!< 0x00000008 */
+#define HRTIM_ODISR_TB2ODIS           HRTIM_ODISR_TB2ODIS_Msk                  /*!< Timer B Output 2 disable */
+#define HRTIM_ODISR_TC1ODIS_Pos       (4U)
+#define HRTIM_ODISR_TC1ODIS_Msk       (0x1UL << HRTIM_ODISR_TC1ODIS_Pos)       /*!< 0x00000010 */
+#define HRTIM_ODISR_TC1ODIS           HRTIM_ODISR_TC1ODIS_Msk                  /*!< Timer C Output 1 disable */
+#define HRTIM_ODISR_TC2ODIS_Pos       (5U)
+#define HRTIM_ODISR_TC2ODIS_Msk       (0x1UL << HRTIM_ODISR_TC2ODIS_Pos)       /*!< 0x00000020 */
+#define HRTIM_ODISR_TC2ODIS           HRTIM_ODISR_TC2ODIS_Msk                  /*!< Timer C Output 2 disable */
+#define HRTIM_ODISR_TD1ODIS_Pos       (6U)
+#define HRTIM_ODISR_TD1ODIS_Msk       (0x1UL << HRTIM_ODISR_TD1ODIS_Pos)       /*!< 0x00000040 */
+#define HRTIM_ODISR_TD1ODIS           HRTIM_ODISR_TD1ODIS_Msk                  /*!< Timer D Output 1 disable */
+#define HRTIM_ODISR_TD2ODIS_Pos       (7U)
+#define HRTIM_ODISR_TD2ODIS_Msk       (0x1UL << HRTIM_ODISR_TD2ODIS_Pos)       /*!< 0x00000080 */
+#define HRTIM_ODISR_TD2ODIS           HRTIM_ODISR_TD2ODIS_Msk                  /*!< Timer D Output 2 disable */
+#define HRTIM_ODISR_TE1ODIS_Pos       (8U)
+#define HRTIM_ODISR_TE1ODIS_Msk       (0x1UL << HRTIM_ODISR_TE1ODIS_Pos)       /*!< 0x00000100 */
+#define HRTIM_ODISR_TE1ODIS           HRTIM_ODISR_TE1ODIS_Msk                  /*!< Timer E Output 1 disable */
+#define HRTIM_ODISR_TE2ODIS_Pos       (9U)
+#define HRTIM_ODISR_TE2ODIS_Msk       (0x1UL << HRTIM_ODISR_TE2ODIS_Pos)       /*!< 0x00000200 */
+#define HRTIM_ODISR_TE2ODIS           HRTIM_ODISR_TE2ODIS_Msk                  /*!< Timer E Output 2 disable */
+
+/**** Bit definition for Common HRTIM Timer output disable status register *****/
+#define HRTIM_ODSR_TA1ODS_Pos         (0U)
+#define HRTIM_ODSR_TA1ODS_Msk         (0x1UL << HRTIM_ODSR_TA1ODS_Pos)         /*!< 0x00000001 */
+#define HRTIM_ODSR_TA1ODS             HRTIM_ODSR_TA1ODS_Msk                    /*!< Timer A Output 1 disable status */
+#define HRTIM_ODSR_TA2ODS_Pos         (1U)
+#define HRTIM_ODSR_TA2ODS_Msk         (0x1UL << HRTIM_ODSR_TA2ODS_Pos)         /*!< 0x00000002 */
+#define HRTIM_ODSR_TA2ODS             HRTIM_ODSR_TA2ODS_Msk                    /*!< Timer A Output 2 disable status */
+#define HRTIM_ODSR_TB1ODS_Pos         (2U)
+#define HRTIM_ODSR_TB1ODS_Msk         (0x1UL << HRTIM_ODSR_TB1ODS_Pos)         /*!< 0x00000004 */
+#define HRTIM_ODSR_TB1ODS             HRTIM_ODSR_TB1ODS_Msk                    /*!< Timer B Output 1 disable status */
+#define HRTIM_ODSR_TB2ODS_Pos         (3U)
+#define HRTIM_ODSR_TB2ODS_Msk         (0x1UL << HRTIM_ODSR_TB2ODS_Pos)         /*!< 0x00000008 */
+#define HRTIM_ODSR_TB2ODS             HRTIM_ODSR_TB2ODS_Msk                    /*!< Timer B Output 2 disable status */
+#define HRTIM_ODSR_TC1ODS_Pos         (4U)
+#define HRTIM_ODSR_TC1ODS_Msk         (0x1UL << HRTIM_ODSR_TC1ODS_Pos)         /*!< 0x00000010 */
+#define HRTIM_ODSR_TC1ODS             HRTIM_ODSR_TC1ODS_Msk                    /*!< Timer C Output 1 disable status */
+#define HRTIM_ODSR_TC2ODS_Pos         (5U)
+#define HRTIM_ODSR_TC2ODS_Msk         (0x1UL << HRTIM_ODSR_TC2ODS_Pos)         /*!< 0x00000020 */
+#define HRTIM_ODSR_TC2ODS             HRTIM_ODSR_TC2ODS_Msk                    /*!< Timer C Output 2 disable status */
+#define HRTIM_ODSR_TD1ODS_Pos         (6U)
+#define HRTIM_ODSR_TD1ODS_Msk         (0x1UL << HRTIM_ODSR_TD1ODS_Pos)         /*!< 0x00000040 */
+#define HRTIM_ODSR_TD1ODS             HRTIM_ODSR_TD1ODS_Msk                    /*!< Timer D Output 1 disable status */
+#define HRTIM_ODSR_TD2ODS_Pos         (7U)
+#define HRTIM_ODSR_TD2ODS_Msk         (0x1UL << HRTIM_ODSR_TD2ODS_Pos)         /*!< 0x00000080 */
+#define HRTIM_ODSR_TD2ODS             HRTIM_ODSR_TD2ODS_Msk                    /*!< Timer D Output 2 disable status */
+#define HRTIM_ODSR_TE1ODS_Pos         (8U)
+#define HRTIM_ODSR_TE1ODS_Msk         (0x1UL << HRTIM_ODSR_TE1ODS_Pos)         /*!< 0x00000100 */
+#define HRTIM_ODSR_TE1ODS             HRTIM_ODSR_TE1ODS_Msk                    /*!< Timer E Output 1 disable status */
+#define HRTIM_ODSR_TE2ODS_Pos         (9U)
+#define HRTIM_ODSR_TE2ODS_Msk         (0x1UL << HRTIM_ODSR_TE2ODS_Pos)         /*!< 0x00000200 */
+#define HRTIM_ODSR_TE2ODS             HRTIM_ODSR_TE2ODS_Msk                    /*!< Timer E Output 2 disable status */
+
+/**** Bit definition for Common HRTIM Timer Burst mode control register ********/
+#define HRTIM_BMCR_BME_Pos            (0U)
+#define HRTIM_BMCR_BME_Msk            (0x1UL << HRTIM_BMCR_BME_Pos)            /*!< 0x00000001 */
+#define HRTIM_BMCR_BME                HRTIM_BMCR_BME_Msk                       /*!< Burst mode enbale */
+#define HRTIM_BMCR_BMOM_Pos           (1U)
+#define HRTIM_BMCR_BMOM_Msk           (0x1UL << HRTIM_BMCR_BMOM_Pos)           /*!< 0x00000002 */
+#define HRTIM_BMCR_BMOM               HRTIM_BMCR_BMOM_Msk                      /*!< Burst mode operating mode */
+#define HRTIM_BMCR_BMCLK_Pos          (2U)
+#define HRTIM_BMCR_BMCLK_Msk          (0xFUL << HRTIM_BMCR_BMCLK_Pos)          /*!< 0x0000003C */
+#define HRTIM_BMCR_BMCLK              HRTIM_BMCR_BMCLK_Msk                     /*!< Burst mode clock source */
+#define HRTIM_BMCR_BMCLK_0            (0x1UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000004 */
+#define HRTIM_BMCR_BMCLK_1            (0x2UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000008 */
+#define HRTIM_BMCR_BMCLK_2            (0x4UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000010 */
+#define HRTIM_BMCR_BMCLK_3            (0x8UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000020 */
+#define HRTIM_BMCR_BMPRSC_Pos         (6U)
+#define HRTIM_BMCR_BMPRSC_Msk         (0xFUL << HRTIM_BMCR_BMPRSC_Pos)         /*!< 0x000003C0 */
+#define HRTIM_BMCR_BMPRSC             HRTIM_BMCR_BMPRSC_Msk                    /*!< Burst mode prescaler */
+#define HRTIM_BMCR_BMPRSC_0           (0x1UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000040 */
+#define HRTIM_BMCR_BMPRSC_1           (0x2UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000080 */
+#define HRTIM_BMCR_BMPRSC_2           (0x4UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000100 */
+#define HRTIM_BMCR_BMPRSC_3           (0x8UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000200 */
+#define HRTIM_BMCR_BMPREN_Pos         (10U)
+#define HRTIM_BMCR_BMPREN_Msk         (0x1UL << HRTIM_BMCR_BMPREN_Pos)         /*!< 0x00000400 */
+#define HRTIM_BMCR_BMPREN             HRTIM_BMCR_BMPREN_Msk                    /*!< Burst mode Preload bit */
+#define HRTIM_BMCR_MTBM_Pos           (16U)
+#define HRTIM_BMCR_MTBM_Msk           (0x1UL << HRTIM_BMCR_MTBM_Pos)           /*!< 0x00010000 */
+#define HRTIM_BMCR_MTBM               HRTIM_BMCR_MTBM_Msk                      /*!< Master Timer Burst mode */
+#define HRTIM_BMCR_TABM_Pos           (17U)
+#define HRTIM_BMCR_TABM_Msk           (0x1UL << HRTIM_BMCR_TABM_Pos)           /*!< 0x00020000 */
+#define HRTIM_BMCR_TABM               HRTIM_BMCR_TABM_Msk                      /*!< Timer A Burst mode */
+#define HRTIM_BMCR_TBBM_Pos           (18U)
+#define HRTIM_BMCR_TBBM_Msk           (0x1UL << HRTIM_BMCR_TBBM_Pos)           /*!< 0x00040000 */
+#define HRTIM_BMCR_TBBM               HRTIM_BMCR_TBBM_Msk                      /*!< Timer B Burst mode */
+#define HRTIM_BMCR_TCBM_Pos           (19U)
+#define HRTIM_BMCR_TCBM_Msk           (0x1UL << HRTIM_BMCR_TCBM_Pos)           /*!< 0x00080000 */
+#define HRTIM_BMCR_TCBM               HRTIM_BMCR_TCBM_Msk                      /*!< Timer C Burst mode */
+#define HRTIM_BMCR_TDBM_Pos           (20U)
+#define HRTIM_BMCR_TDBM_Msk           (0x1UL << HRTIM_BMCR_TDBM_Pos)           /*!< 0x00100000 */
+#define HRTIM_BMCR_TDBM               HRTIM_BMCR_TDBM_Msk                      /*!< Timer D Burst mode */
+#define HRTIM_BMCR_TEBM_Pos           (21U)
+#define HRTIM_BMCR_TEBM_Msk           (0x1UL << HRTIM_BMCR_TEBM_Pos)           /*!< 0x00200000 */
+#define HRTIM_BMCR_TEBM               HRTIM_BMCR_TEBM_Msk                      /*!< Timer E Burst mode */
+#define HRTIM_BMCR_BMSTAT_Pos         (31U)
+#define HRTIM_BMCR_BMSTAT_Msk         (0x1UL << HRTIM_BMCR_BMSTAT_Pos)         /*!< 0x80000000 */
+#define HRTIM_BMCR_BMSTAT             HRTIM_BMCR_BMSTAT_Msk                    /*!< Burst mode status */
+
+/**** Bit definition for Common HRTIM Timer Burst mode Trigger register *******/
+#define HRTIM_BMTRGR_SW_Pos           (0U)
+#define HRTIM_BMTRGR_SW_Msk           (0x1UL << HRTIM_BMTRGR_SW_Pos)           /*!< 0x00000001 */
+#define HRTIM_BMTRGR_SW               HRTIM_BMTRGR_SW_Msk                      /*!< Software start */
+#define HRTIM_BMTRGR_MSTRST_Pos       (1U)
+#define HRTIM_BMTRGR_MSTRST_Msk       (0x1UL << HRTIM_BMTRGR_MSTRST_Pos)       /*!< 0x00000002 */
+#define HRTIM_BMTRGR_MSTRST           HRTIM_BMTRGR_MSTRST_Msk                  /*!<  Master reset */
+#define HRTIM_BMTRGR_MSTREP_Pos       (2U)
+#define HRTIM_BMTRGR_MSTREP_Msk       (0x1UL << HRTIM_BMTRGR_MSTREP_Pos)       /*!< 0x00000004 */
+#define HRTIM_BMTRGR_MSTREP           HRTIM_BMTRGR_MSTREP_Msk                  /*!<  Master repetition */
+#define HRTIM_BMTRGR_MSTCMP1_Pos      (3U)
+#define HRTIM_BMTRGR_MSTCMP1_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP1_Pos)      /*!< 0x00000008 */
+#define HRTIM_BMTRGR_MSTCMP1          HRTIM_BMTRGR_MSTCMP1_Msk                 /*!<  Master compare 1 */
+#define HRTIM_BMTRGR_MSTCMP2_Pos      (4U)
+#define HRTIM_BMTRGR_MSTCMP2_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP2_Pos)      /*!< 0x00000010 */
+#define HRTIM_BMTRGR_MSTCMP2          HRTIM_BMTRGR_MSTCMP2_Msk                 /*!< Master compare 2  */
+#define HRTIM_BMTRGR_MSTCMP3_Pos      (5U)
+#define HRTIM_BMTRGR_MSTCMP3_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP3_Pos)      /*!< 0x00000020 */
+#define HRTIM_BMTRGR_MSTCMP3          HRTIM_BMTRGR_MSTCMP3_Msk                 /*!< Master compare 3 */
+#define HRTIM_BMTRGR_MSTCMP4_Pos      (6U)
+#define HRTIM_BMTRGR_MSTCMP4_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP4_Pos)      /*!< 0x00000040 */
+#define HRTIM_BMTRGR_MSTCMP4          HRTIM_BMTRGR_MSTCMP4_Msk                 /*!< Master compare 4 */
+#define HRTIM_BMTRGR_TARST_Pos        (7U)
+#define HRTIM_BMTRGR_TARST_Msk        (0x1UL << HRTIM_BMTRGR_TARST_Pos)        /*!< 0x00000080 */
+#define HRTIM_BMTRGR_TARST            HRTIM_BMTRGR_TARST_Msk                   /*!< Timer A reset  */
+#define HRTIM_BMTRGR_TAREP_Pos        (8U)
+#define HRTIM_BMTRGR_TAREP_Msk        (0x1UL << HRTIM_BMTRGR_TAREP_Pos)        /*!< 0x00000100 */
+#define HRTIM_BMTRGR_TAREP            HRTIM_BMTRGR_TAREP_Msk                   /*!< Timer A repetition  */
+#define HRTIM_BMTRGR_TACMP1_Pos       (9U)
+#define HRTIM_BMTRGR_TACMP1_Msk       (0x1UL << HRTIM_BMTRGR_TACMP1_Pos)       /*!< 0x00000200 */
+#define HRTIM_BMTRGR_TACMP1           HRTIM_BMTRGR_TACMP1_Msk                  /*!< Timer A compare 1  */
+#define HRTIM_BMTRGR_TACMP2_Pos       (10U)
+#define HRTIM_BMTRGR_TACMP2_Msk       (0x1UL << HRTIM_BMTRGR_TACMP2_Pos)       /*!< 0x00000400 */
+#define HRTIM_BMTRGR_TACMP2           HRTIM_BMTRGR_TACMP2_Msk                  /*!< Timer A compare 2  */
+#define HRTIM_BMTRGR_TBRST_Pos        (11U)
+#define HRTIM_BMTRGR_TBRST_Msk        (0x1UL << HRTIM_BMTRGR_TBRST_Pos)        /*!< 0x00000800 */
+#define HRTIM_BMTRGR_TBRST            HRTIM_BMTRGR_TBRST_Msk                   /*!< Timer B reset  */
+#define HRTIM_BMTRGR_TBREP_Pos        (12U)
+#define HRTIM_BMTRGR_TBREP_Msk        (0x1UL << HRTIM_BMTRGR_TBREP_Pos)        /*!< 0x00001000 */
+#define HRTIM_BMTRGR_TBREP            HRTIM_BMTRGR_TBREP_Msk                   /*!< Timer B repetition  */
+#define HRTIM_BMTRGR_TBCMP1_Pos       (13U)
+#define HRTIM_BMTRGR_TBCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TBCMP1_Pos)       /*!< 0x00002000 */
+#define HRTIM_BMTRGR_TBCMP1           HRTIM_BMTRGR_TBCMP1_Msk                  /*!< Timer B compare 1 */
+#define HRTIM_BMTRGR_TBCMP2_Pos       (14U)
+#define HRTIM_BMTRGR_TBCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TBCMP2_Pos)       /*!< 0x00004000 */
+#define HRTIM_BMTRGR_TBCMP2           HRTIM_BMTRGR_TBCMP2_Msk                  /*!< Timer B compare 2 */
+#define HRTIM_BMTRGR_TCRST_Pos        (15U)
+#define HRTIM_BMTRGR_TCRST_Msk        (0x1UL << HRTIM_BMTRGR_TCRST_Pos)        /*!< 0x00008000 */
+#define HRTIM_BMTRGR_TCRST            HRTIM_BMTRGR_TCRST_Msk                   /*!< Timer C reset  */
+#define HRTIM_BMTRGR_TCREP_Pos        (16U)
+#define HRTIM_BMTRGR_TCREP_Msk        (0x1UL << HRTIM_BMTRGR_TCREP_Pos)        /*!< 0x00010000 */
+#define HRTIM_BMTRGR_TCREP            HRTIM_BMTRGR_TCREP_Msk                   /*!< Timer C repetition */
+#define HRTIM_BMTRGR_TCCMP1_Pos       (17U)
+#define HRTIM_BMTRGR_TCCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TCCMP1_Pos)       /*!< 0x00020000 */
+#define HRTIM_BMTRGR_TCCMP1           HRTIM_BMTRGR_TCCMP1_Msk                  /*!< Timer C compare 1 */
+#define HRTIM_BMTRGR_TCCMP2_Pos       (18U)
+#define HRTIM_BMTRGR_TCCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TCCMP2_Pos)       /*!< 0x00040000 */
+#define HRTIM_BMTRGR_TCCMP2           HRTIM_BMTRGR_TCCMP2_Msk                  /*!< Timer C compare 2 */
+#define HRTIM_BMTRGR_TDRST_Pos        (19U)
+#define HRTIM_BMTRGR_TDRST_Msk        (0x1UL << HRTIM_BMTRGR_TDRST_Pos)        /*!< 0x00080000 */
+#define HRTIM_BMTRGR_TDRST            HRTIM_BMTRGR_TDRST_Msk                   /*!< Timer D reset  */
+#define HRTIM_BMTRGR_TDREP_Pos        (20U)
+#define HRTIM_BMTRGR_TDREP_Msk        (0x1UL << HRTIM_BMTRGR_TDREP_Pos)        /*!< 0x00100000 */
+#define HRTIM_BMTRGR_TDREP            HRTIM_BMTRGR_TDREP_Msk                   /*!< Timer D repetition  */
+#define HRTIM_BMTRGR_TDCMP1_Pos       (21U)
+#define HRTIM_BMTRGR_TDCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TDCMP1_Pos)       /*!< 0x00200000 */
+#define HRTIM_BMTRGR_TDCMP1           HRTIM_BMTRGR_TDCMP1_Msk                  /*!< Timer D compare 1 */
+#define HRTIM_BMTRGR_TDCMP2_Pos       (22U)
+#define HRTIM_BMTRGR_TDCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TDCMP2_Pos)       /*!< 0x00400000 */
+#define HRTIM_BMTRGR_TDCMP2           HRTIM_BMTRGR_TDCMP2_Msk                  /*!< Timer D compare 2 */
+#define HRTIM_BMTRGR_TERST_Pos        (23U)
+#define HRTIM_BMTRGR_TERST_Msk        (0x1UL << HRTIM_BMTRGR_TERST_Pos)        /*!< 0x00800000 */
+#define HRTIM_BMTRGR_TERST            HRTIM_BMTRGR_TERST_Msk                   /*!< Timer E reset  */
+#define HRTIM_BMTRGR_TEREP_Pos        (24U)
+#define HRTIM_BMTRGR_TEREP_Msk        (0x1UL << HRTIM_BMTRGR_TEREP_Pos)        /*!< 0x01000000 */
+#define HRTIM_BMTRGR_TEREP            HRTIM_BMTRGR_TEREP_Msk                   /*!< Timer E repetition  */
+#define HRTIM_BMTRGR_TECMP1_Pos       (25U)
+#define HRTIM_BMTRGR_TECMP1_Msk       (0x1UL << HRTIM_BMTRGR_TECMP1_Pos)       /*!< 0x02000000 */
+#define HRTIM_BMTRGR_TECMP1           HRTIM_BMTRGR_TECMP1_Msk                  /*!< Timer E compare 1 */
+#define HRTIM_BMTRGR_TECMP2_Pos       (26U)
+#define HRTIM_BMTRGR_TECMP2_Msk       (0x1UL << HRTIM_BMTRGR_TECMP2_Pos)       /*!< 0x04000000 */
+#define HRTIM_BMTRGR_TECMP2           HRTIM_BMTRGR_TECMP2_Msk                  /*!< Timer E compare 2 */
+#define HRTIM_BMTRGR_TAEEV7_Pos       (27U)
+#define HRTIM_BMTRGR_TAEEV7_Msk       (0x1UL << HRTIM_BMTRGR_TAEEV7_Pos)       /*!< 0x08000000 */
+#define HRTIM_BMTRGR_TAEEV7           HRTIM_BMTRGR_TAEEV7_Msk                  /*!< Timer A period following External Event7  */
+#define HRTIM_BMTRGR_TDEEV8_Pos       (28U)
+#define HRTIM_BMTRGR_TDEEV8_Msk       (0x1UL << HRTIM_BMTRGR_TDEEV8_Pos)       /*!< 0x10000000 */
+#define HRTIM_BMTRGR_TDEEV8           HRTIM_BMTRGR_TDEEV8_Msk                  /*!< Timer D period following External Event8  */
+#define HRTIM_BMTRGR_EEV7_Pos         (29U)
+#define HRTIM_BMTRGR_EEV7_Msk         (0x1UL << HRTIM_BMTRGR_EEV7_Pos)         /*!< 0x20000000 */
+#define HRTIM_BMTRGR_EEV7             HRTIM_BMTRGR_EEV7_Msk                    /*!< External Event 7 */
+#define HRTIM_BMTRGR_EEV8_Pos         (30U)
+#define HRTIM_BMTRGR_EEV8_Msk         (0x1UL << HRTIM_BMTRGR_EEV8_Pos)         /*!< 0x40000000 */
+#define HRTIM_BMTRGR_EEV8             HRTIM_BMTRGR_EEV8_Msk                    /*!< External Event 8 */
+#define HRTIM_BMTRGR_OCHPEV_Pos       (31U)
+#define HRTIM_BMTRGR_OCHPEV_Msk       (0x1UL << HRTIM_BMTRGR_OCHPEV_Pos)       /*!< 0x80000000 */
+#define HRTIM_BMTRGR_OCHPEV           HRTIM_BMTRGR_OCHPEV_Msk                  /*!< on-chip Event */
+
+/*******************  Bit definition for HRTIM_BMCMPR register  ***************/
+#define HRTIM_BMCMPR_BMCMPR_Pos       (0U)
+#define HRTIM_BMCMPR_BMCMPR_Msk       (0xFFFFUL << HRTIM_BMCMPR_BMCMPR_Pos)    /*!< 0x0000FFFF */
+#define HRTIM_BMCMPR_BMCMPR           HRTIM_BMCMPR_BMCMPR_Msk                  /*!<!<Burst Compare Value */
+
+/*******************  Bit definition for HRTIM_BMPER register  ****************/
+#define HRTIM_BMPER_BMPER_Pos         (0U)
+#define HRTIM_BMPER_BMPER_Msk         (0xFFFFUL << HRTIM_BMPER_BMPER_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_BMPER_BMPER             HRTIM_BMPER_BMPER_Msk                    /*!<!<Burst period Value */
+
+/*******************  Bit definition for HRTIM_EECR1 register  ****************/
+#define HRTIM_EECR1_EE1SRC_Pos        (0U)
+#define HRTIM_EECR1_EE1SRC_Msk        (0x3UL << HRTIM_EECR1_EE1SRC_Pos)        /*!< 0x00000003 */
+#define HRTIM_EECR1_EE1SRC            HRTIM_EECR1_EE1SRC_Msk                   /*!< External event 1 source */
+#define HRTIM_EECR1_EE1SRC_0          (0x1UL << HRTIM_EECR1_EE1SRC_Pos)         /*!< 0x00000001 */
+#define HRTIM_EECR1_EE1SRC_1          (0x2UL << HRTIM_EECR1_EE1SRC_Pos)         /*!< 0x00000002 */
+#define HRTIM_EECR1_EE1POL_Pos        (2U)
+#define HRTIM_EECR1_EE1POL_Msk        (0x1UL << HRTIM_EECR1_EE1POL_Pos)        /*!< 0x00000004 */
+#define HRTIM_EECR1_EE1POL            HRTIM_EECR1_EE1POL_Msk                   /*!< External event 1 Polarity */
+#define HRTIM_EECR1_EE1SNS_Pos        (3U)
+#define HRTIM_EECR1_EE1SNS_Msk        (0x3UL << HRTIM_EECR1_EE1SNS_Pos)        /*!< 0x00000018 */
+#define HRTIM_EECR1_EE1SNS            HRTIM_EECR1_EE1SNS_Msk                   /*!< External event 1 sensitivity */
+#define HRTIM_EECR1_EE1SNS_0          (0x1UL << HRTIM_EECR1_EE1SNS_Pos)         /*!< 0x00000008 */
+#define HRTIM_EECR1_EE1SNS_1          (0x2UL << HRTIM_EECR1_EE1SNS_Pos)         /*!< 0x00000010 */
+#define HRTIM_EECR1_EE1FAST_Pos       (5U)
+#define HRTIM_EECR1_EE1FAST_Msk       (0x1UL << HRTIM_EECR1_EE1FAST_Pos)       /*!< 0x00000020 */
+#define HRTIM_EECR1_EE1FAST           HRTIM_EECR1_EE1FAST_Msk                  /*!< External event 1 Fast mode */
+
+#define HRTIM_EECR1_EE2SRC_Pos        (6U)
+#define HRTIM_EECR1_EE2SRC_Msk        (0x3UL << HRTIM_EECR1_EE2SRC_Pos)        /*!< 0x000000C0 */
+#define HRTIM_EECR1_EE2SRC            HRTIM_EECR1_EE2SRC_Msk                   /*!< External event 2 source */
+#define HRTIM_EECR1_EE2SRC_0          (0x1UL << HRTIM_EECR1_EE2SRC_Pos)         /*!< 0x00000040 */
+#define HRTIM_EECR1_EE2SRC_1          (0x2UL << HRTIM_EECR1_EE2SRC_Pos)         /*!< 0x00000080 */
+#define HRTIM_EECR1_EE2POL_Pos        (8U)
+#define HRTIM_EECR1_EE2POL_Msk        (0x1UL << HRTIM_EECR1_EE2POL_Pos)        /*!< 0x00000100 */
+#define HRTIM_EECR1_EE2POL            HRTIM_EECR1_EE2POL_Msk                   /*!< External event 2 Polarity */
+#define HRTIM_EECR1_EE2SNS_Pos        (9U)
+#define HRTIM_EECR1_EE2SNS_Msk        (0x3UL << HRTIM_EECR1_EE2SNS_Pos)        /*!< 0x00000600 */
+#define HRTIM_EECR1_EE2SNS            HRTIM_EECR1_EE2SNS_Msk                   /*!< External event 2 sensitivity */
+#define HRTIM_EECR1_EE2SNS_0          (0x1UL << HRTIM_EECR1_EE2SNS_Pos)         /*!< 0x00000200 */
+#define HRTIM_EECR1_EE2SNS_1          (0x2UL << HRTIM_EECR1_EE2SNS_Pos)         /*!< 0x00000400 */
+#define HRTIM_EECR1_EE2FAST_Pos       (11U)
+#define HRTIM_EECR1_EE2FAST_Msk       (0x1UL << HRTIM_EECR1_EE2FAST_Pos)       /*!< 0x00000800 */
+#define HRTIM_EECR1_EE2FAST           HRTIM_EECR1_EE2FAST_Msk                  /*!< External event 2 Fast mode */
+
+#define HRTIM_EECR1_EE3SRC_Pos        (12U)
+#define HRTIM_EECR1_EE3SRC_Msk        (0x3UL << HRTIM_EECR1_EE3SRC_Pos)        /*!< 0x00003000 */
+#define HRTIM_EECR1_EE3SRC            HRTIM_EECR1_EE3SRC_Msk                   /*!< External event 3 source */
+#define HRTIM_EECR1_EE3SRC_0          (0x1UL << HRTIM_EECR1_EE3SRC_Pos)         /*!< 0x00001000 */
+#define HRTIM_EECR1_EE3SRC_1          (0x2UL << HRTIM_EECR1_EE3SRC_Pos)         /*!< 0x00002000 */
+#define HRTIM_EECR1_EE3POL_Pos        (14U)
+#define HRTIM_EECR1_EE3POL_Msk        (0x1UL << HRTIM_EECR1_EE3POL_Pos)        /*!< 0x00004000 */
+#define HRTIM_EECR1_EE3POL            HRTIM_EECR1_EE3POL_Msk                   /*!< External event 3 Polarity */
+#define HRTIM_EECR1_EE3SNS_Pos        (15U)
+#define HRTIM_EECR1_EE3SNS_Msk        (0x3UL << HRTIM_EECR1_EE3SNS_Pos)        /*!< 0x00018000 */
+#define HRTIM_EECR1_EE3SNS            HRTIM_EECR1_EE3SNS_Msk                   /*!< External event 3 sensitivity */
+#define HRTIM_EECR1_EE3SNS_0          (0x1UL << HRTIM_EECR1_EE3SNS_Pos)         /*!< 0x00008000 */
+#define HRTIM_EECR1_EE3SNS_1          (0x2UL << HRTIM_EECR1_EE3SNS_Pos)         /*!< 0x00010000 */
+#define HRTIM_EECR1_EE3FAST_Pos       (17U)
+#define HRTIM_EECR1_EE3FAST_Msk       (0x1UL << HRTIM_EECR1_EE3FAST_Pos)       /*!< 0x00020000 */
+#define HRTIM_EECR1_EE3FAST           HRTIM_EECR1_EE3FAST_Msk                  /*!< External event 3 Fast mode */
+
+#define HRTIM_EECR1_EE4SRC_Pos        (18U)
+#define HRTIM_EECR1_EE4SRC_Msk        (0x3UL << HRTIM_EECR1_EE4SRC_Pos)        /*!< 0x000C0000 */
+#define HRTIM_EECR1_EE4SRC            HRTIM_EECR1_EE4SRC_Msk                   /*!< External event 4 source */
+#define HRTIM_EECR1_EE4SRC_0          (0x1UL << HRTIM_EECR1_EE4SRC_Pos)         /*!< 0x00040000 */
+#define HRTIM_EECR1_EE4SRC_1          (0x2UL << HRTIM_EECR1_EE4SRC_Pos)         /*!< 0x00080000 */
+#define HRTIM_EECR1_EE4POL_Pos        (20U)
+#define HRTIM_EECR1_EE4POL_Msk        (0x1UL << HRTIM_EECR1_EE4POL_Pos)        /*!< 0x00100000 */
+#define HRTIM_EECR1_EE4POL            HRTIM_EECR1_EE4POL_Msk                   /*!< External event 4 Polarity */
+#define HRTIM_EECR1_EE4SNS_Pos        (21U)
+#define HRTIM_EECR1_EE4SNS_Msk        (0x3UL << HRTIM_EECR1_EE4SNS_Pos)        /*!< 0x00600000 */
+#define HRTIM_EECR1_EE4SNS            HRTIM_EECR1_EE4SNS_Msk                   /*!< External event 4 sensitivity */
+#define HRTIM_EECR1_EE4SNS_0          (0x1UL << HRTIM_EECR1_EE4SNS_Pos)         /*!< 0x00200000 */
+#define HRTIM_EECR1_EE4SNS_1          (0x2UL << HRTIM_EECR1_EE4SNS_Pos)         /*!< 0x00400000 */
+#define HRTIM_EECR1_EE4FAST_Pos       (23U)
+#define HRTIM_EECR1_EE4FAST_Msk       (0x1UL << HRTIM_EECR1_EE4FAST_Pos)       /*!< 0x00800000 */
+#define HRTIM_EECR1_EE4FAST           HRTIM_EECR1_EE4FAST_Msk                  /*!< External event 4 Fast mode */
+
+#define HRTIM_EECR1_EE5SRC_Pos        (24U)
+#define HRTIM_EECR1_EE5SRC_Msk        (0x3UL << HRTIM_EECR1_EE5SRC_Pos)        /*!< 0x03000000 */
+#define HRTIM_EECR1_EE5SRC            HRTIM_EECR1_EE5SRC_Msk                   /*!< External event 5 source */
+#define HRTIM_EECR1_EE5SRC_0          (0x1UL << HRTIM_EECR1_EE5SRC_Pos)         /*!< 0x01000000 */
+#define HRTIM_EECR1_EE5SRC_1          (0x2UL << HRTIM_EECR1_EE5SRC_Pos)         /*!< 0x02000000 */
+#define HRTIM_EECR1_EE5POL_Pos        (26U)
+#define HRTIM_EECR1_EE5POL_Msk        (0x1UL << HRTIM_EECR1_EE5POL_Pos)        /*!< 0x04000000 */
+#define HRTIM_EECR1_EE5POL            HRTIM_EECR1_EE5POL_Msk                   /*!< External event 5 Polarity */
+#define HRTIM_EECR1_EE5SNS_Pos        (27U)
+#define HRTIM_EECR1_EE5SNS_Msk        (0x3UL << HRTIM_EECR1_EE5SNS_Pos)        /*!< 0x18000000 */
+#define HRTIM_EECR1_EE5SNS            HRTIM_EECR1_EE5SNS_Msk                   /*!< External event 5 sensitivity */
+#define HRTIM_EECR1_EE5SNS_0          (0x1UL << HRTIM_EECR1_EE5SNS_Pos)         /*!< 0x08000000 */
+#define HRTIM_EECR1_EE5SNS_1          (0x2UL << HRTIM_EECR1_EE5SNS_Pos)         /*!< 0x10000000 */
+#define HRTIM_EECR1_EE5FAST_Pos       (29U)
+#define HRTIM_EECR1_EE5FAST_Msk       (0x1UL << HRTIM_EECR1_EE5FAST_Pos)       /*!< 0x20000000 */
+#define HRTIM_EECR1_EE5FAST           HRTIM_EECR1_EE5FAST_Msk                  /*!< External event 5 Fast mode */
+
+/*******************  Bit definition for HRTIM_EECR2 register  ****************/
+#define HRTIM_EECR2_EE6SRC_Pos        (0U)
+#define HRTIM_EECR2_EE6SRC_Msk        (0x3UL << HRTIM_EECR2_EE6SRC_Pos)        /*!< 0x00000003 */
+#define HRTIM_EECR2_EE6SRC            HRTIM_EECR2_EE6SRC_Msk                   /*!< External event 6 source */
+#define HRTIM_EECR2_EE6SRC_0          (0x1UL << HRTIM_EECR2_EE6SRC_Pos)         /*!< 0x00000001 */
+#define HRTIM_EECR2_EE6SRC_1          (0x2UL << HRTIM_EECR2_EE6SRC_Pos)         /*!< 0x00000002 */
+#define HRTIM_EECR2_EE6POL_Pos        (2U)
+#define HRTIM_EECR2_EE6POL_Msk        (0x1UL << HRTIM_EECR2_EE6POL_Pos)        /*!< 0x00000004 */
+#define HRTIM_EECR2_EE6POL            HRTIM_EECR2_EE6POL_Msk                   /*!< External event 6 Polarity */
+#define HRTIM_EECR2_EE6SNS_Pos        (3U)
+#define HRTIM_EECR2_EE6SNS_Msk        (0x3UL << HRTIM_EECR2_EE6SNS_Pos)        /*!< 0x00000018 */
+#define HRTIM_EECR2_EE6SNS            HRTIM_EECR2_EE6SNS_Msk                   /*!< External event 6 sensitivity */
+#define HRTIM_EECR2_EE6SNS_0          (0x1UL << HRTIM_EECR2_EE6SNS_Pos)         /*!< 0x00000008 */
+#define HRTIM_EECR2_EE6SNS_1          (0x2UL << HRTIM_EECR2_EE6SNS_Pos)         /*!< 0x00000010 */
+
+#define HRTIM_EECR2_EE7SRC_Pos        (6U)
+#define HRTIM_EECR2_EE7SRC_Msk        (0x3UL << HRTIM_EECR2_EE7SRC_Pos)        /*!< 0x000000C0 */
+#define HRTIM_EECR2_EE7SRC            HRTIM_EECR2_EE7SRC_Msk                   /*!< External event 7 source */
+#define HRTIM_EECR2_EE7SRC_0          (0x1UL << HRTIM_EECR2_EE7SRC_Pos)         /*!< 0x00000040 */
+#define HRTIM_EECR2_EE7SRC_1          (0x2UL << HRTIM_EECR2_EE7SRC_Pos)         /*!< 0x00000080 */
+#define HRTIM_EECR2_EE7POL_Pos        (8U)
+#define HRTIM_EECR2_EE7POL_Msk        (0x1UL << HRTIM_EECR2_EE7POL_Pos)        /*!< 0x00000100 */
+#define HRTIM_EECR2_EE7POL            HRTIM_EECR2_EE7POL_Msk                   /*!< External event 7 Polarity */
+#define HRTIM_EECR2_EE7SNS_Pos        (9U)
+#define HRTIM_EECR2_EE7SNS_Msk        (0x3UL << HRTIM_EECR2_EE7SNS_Pos)        /*!< 0x00000600 */
+#define HRTIM_EECR2_EE7SNS            HRTIM_EECR2_EE7SNS_Msk                   /*!< External event 7 sensitivity */
+#define HRTIM_EECR2_EE7SNS_0          (0x1UL << HRTIM_EECR2_EE7SNS_Pos)         /*!< 0x00000200 */
+#define HRTIM_EECR2_EE7SNS_1          (0x2UL << HRTIM_EECR2_EE7SNS_Pos)         /*!< 0x00000400 */
+
+#define HRTIM_EECR2_EE8SRC_Pos        (12U)
+#define HRTIM_EECR2_EE8SRC_Msk        (0x3UL << HRTIM_EECR2_EE8SRC_Pos)        /*!< 0x00003000 */
+#define HRTIM_EECR2_EE8SRC            HRTIM_EECR2_EE8SRC_Msk                   /*!< External event 8 source */
+#define HRTIM_EECR2_EE8SRC_0          (0x1UL << HRTIM_EECR2_EE8SRC_Pos)         /*!< 0x00001000 */
+#define HRTIM_EECR2_EE8SRC_1          (0x2UL << HRTIM_EECR2_EE8SRC_Pos)         /*!< 0x00002000 */
+#define HRTIM_EECR2_EE8POL_Pos        (14U)
+#define HRTIM_EECR2_EE8POL_Msk        (0x1UL << HRTIM_EECR2_EE8POL_Pos)        /*!< 0x00004000 */
+#define HRTIM_EECR2_EE8POL            HRTIM_EECR2_EE8POL_Msk                   /*!< External event 8 Polarity */
+#define HRTIM_EECR2_EE8SNS_Pos        (15U)
+#define HRTIM_EECR2_EE8SNS_Msk        (0x3UL << HRTIM_EECR2_EE8SNS_Pos)        /*!< 0x00018000 */
+#define HRTIM_EECR2_EE8SNS            HRTIM_EECR2_EE8SNS_Msk                   /*!< External event 8 sensitivity */
+#define HRTIM_EECR2_EE8SNS_0          (0x1UL << HRTIM_EECR2_EE8SNS_Pos)         /*!< 0x00008000 */
+#define HRTIM_EECR2_EE8SNS_1          (0x2UL << HRTIM_EECR2_EE8SNS_Pos)         /*!< 0x00010000 */
+
+#define HRTIM_EECR2_EE9SRC_Pos        (18U)
+#define HRTIM_EECR2_EE9SRC_Msk        (0x3UL << HRTIM_EECR2_EE9SRC_Pos)        /*!< 0x000C0000 */
+#define HRTIM_EECR2_EE9SRC            HRTIM_EECR2_EE9SRC_Msk                   /*!< External event 9 source */
+#define HRTIM_EECR2_EE9SRC_0          (0x1UL << HRTIM_EECR2_EE9SRC_Pos)         /*!< 0x00040000 */
+#define HRTIM_EECR2_EE9SRC_1          (0x2UL << HRTIM_EECR2_EE9SRC_Pos)         /*!< 0x00080000 */
+#define HRTIM_EECR2_EE9POL_Pos        (20U)
+#define HRTIM_EECR2_EE9POL_Msk        (0x1UL << HRTIM_EECR2_EE9POL_Pos)        /*!< 0x00100000 */
+#define HRTIM_EECR2_EE9POL            HRTIM_EECR2_EE9POL_Msk                   /*!< External event 9 Polarity */
+#define HRTIM_EECR2_EE9SNS_Pos        (21U)
+#define HRTIM_EECR2_EE9SNS_Msk        (0x3UL << HRTIM_EECR2_EE9SNS_Pos)        /*!< 0x00600000 */
+#define HRTIM_EECR2_EE9SNS            HRTIM_EECR2_EE9SNS_Msk                   /*!< External event 9 sensitivity */
+#define HRTIM_EECR2_EE9SNS_0          (0x1UL << HRTIM_EECR2_EE9SNS_Pos)         /*!< 0x00200000 */
+#define HRTIM_EECR2_EE9SNS_1          (0x2UL << HRTIM_EECR2_EE9SNS_Pos)         /*!< 0x00400000 */
+
+#define HRTIM_EECR2_EE10SRC_Pos       (24U)
+#define HRTIM_EECR2_EE10SRC_Msk       (0x3UL << HRTIM_EECR2_EE10SRC_Pos)       /*!< 0x03000000 */
+#define HRTIM_EECR2_EE10SRC           HRTIM_EECR2_EE10SRC_Msk                  /*!< External event 10 source */
+#define HRTIM_EECR2_EE10SRC_0         (0x1UL << HRTIM_EECR2_EE10SRC_Pos)        /*!< 0x01000000 */
+#define HRTIM_EECR2_EE10SRC_1         (0x2UL << HRTIM_EECR2_EE10SRC_Pos)        /*!< 0x02000000 */
+#define HRTIM_EECR2_EE10POL_Pos       (26U)
+#define HRTIM_EECR2_EE10POL_Msk       (0x1UL << HRTIM_EECR2_EE10POL_Pos)       /*!< 0x04000000 */
+#define HRTIM_EECR2_EE10POL           HRTIM_EECR2_EE10POL_Msk                  /*!< External event 10 Polarity */
+#define HRTIM_EECR2_EE10SNS_Pos       (27U)
+#define HRTIM_EECR2_EE10SNS_Msk       (0x3UL << HRTIM_EECR2_EE10SNS_Pos)       /*!< 0x18000000 */
+#define HRTIM_EECR2_EE10SNS           HRTIM_EECR2_EE10SNS_Msk                  /*!< External event 10 sensitivity */
+#define HRTIM_EECR2_EE10SNS_0         (0x1UL << HRTIM_EECR2_EE10SNS_Pos)        /*!< 0x08000000 */
+#define HRTIM_EECR2_EE10SNS_1         (0x2UL << HRTIM_EECR2_EE10SNS_Pos)        /*!< 0x10000000 */
+
+/*******************  Bit definition for HRTIM_EECR3 register  ****************/
+#define HRTIM_EECR3_EE6F_Pos          (0U)
+#define HRTIM_EECR3_EE6F_Msk          (0xFUL << HRTIM_EECR3_EE6F_Pos)          /*!< 0x0000000F */
+#define HRTIM_EECR3_EE6F              HRTIM_EECR3_EE6F_Msk                     /*!< External event 6 filter */
+#define HRTIM_EECR3_EE6F_0            (0x1UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000001 */
+#define HRTIM_EECR3_EE6F_1            (0x2UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000002 */
+#define HRTIM_EECR3_EE6F_2            (0x4UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000004 */
+#define HRTIM_EECR3_EE6F_3            (0x8UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000008 */
+#define HRTIM_EECR3_EE7F_Pos          (6U)
+#define HRTIM_EECR3_EE7F_Msk          (0xFUL << HRTIM_EECR3_EE7F_Pos)          /*!< 0x000003C0 */
+#define HRTIM_EECR3_EE7F              HRTIM_EECR3_EE7F_Msk                     /*!< External event 7 filter */
+#define HRTIM_EECR3_EE7F_0            (0x1UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000040 */
+#define HRTIM_EECR3_EE7F_1            (0x2UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000080 */
+#define HRTIM_EECR3_EE7F_2            (0x4UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000100 */
+#define HRTIM_EECR3_EE7F_3            (0x8UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000200 */
+#define HRTIM_EECR3_EE8F_Pos          (12U)
+#define HRTIM_EECR3_EE8F_Msk          (0xFUL << HRTIM_EECR3_EE8F_Pos)          /*!< 0x0000F000 */
+#define HRTIM_EECR3_EE8F              HRTIM_EECR3_EE8F_Msk                     /*!< External event 8 filter */
+#define HRTIM_EECR3_EE8F_0            (0x1UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00001000 */
+#define HRTIM_EECR3_EE8F_1            (0x2UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00002000 */
+#define HRTIM_EECR3_EE8F_2            (0x4UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00004000 */
+#define HRTIM_EECR3_EE8F_3            (0x8UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00008000 */
+#define HRTIM_EECR3_EE9F_Pos          (18U)
+#define HRTIM_EECR3_EE9F_Msk          (0xFUL << HRTIM_EECR3_EE9F_Pos)          /*!< 0x003C0000 */
+#define HRTIM_EECR3_EE9F              HRTIM_EECR3_EE9F_Msk                     /*!< External event 9 filter */
+#define HRTIM_EECR3_EE9F_0            (0x1UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00040000 */
+#define HRTIM_EECR3_EE9F_1            (0x2UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00080000 */
+#define HRTIM_EECR3_EE9F_2            (0x4UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00100000 */
+#define HRTIM_EECR3_EE9F_3            (0x8UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00200000 */
+#define HRTIM_EECR3_EE10F_Pos         (24U)
+#define HRTIM_EECR3_EE10F_Msk         (0xFUL << HRTIM_EECR3_EE10F_Pos)         /*!< 0x0F000000 */
+#define HRTIM_EECR3_EE10F             HRTIM_EECR3_EE10F_Msk                    /*!< External event 10 filter */
+#define HRTIM_EECR3_EE10F_0           (0x1UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x01000000 */
+#define HRTIM_EECR3_EE10F_1           (0x2UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x02000000 */
+#define HRTIM_EECR3_EE10F_2           (0x4UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x04000000 */
+#define HRTIM_EECR3_EE10F_3           (0x8UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x08000000 */
+#define HRTIM_EECR3_EEVSD_Pos         (30U)
+#define HRTIM_EECR3_EEVSD_Msk         (0x3UL << HRTIM_EECR3_EEVSD_Pos)         /*!< 0xC0000000 */
+#define HRTIM_EECR3_EEVSD             HRTIM_EECR3_EEVSD_Msk                    /*!< External event sampling clock division */
+#define HRTIM_EECR3_EEVSD_0           (0x1UL << HRTIM_EECR3_EEVSD_Pos)          /*!< 0x40000000 */
+#define HRTIM_EECR3_EEVSD_1           (0x2UL << HRTIM_EECR3_EEVSD_Pos)          /*!< 0x80000000 */
+
+/*******************  Bit definition for HRTIM_ADC1R register  ****************/
+#define HRTIM_ADC1R_AD1MC1_Pos        (0U)
+#define HRTIM_ADC1R_AD1MC1_Msk        (0x1UL << HRTIM_ADC1R_AD1MC1_Pos)        /*!< 0x00000001 */
+#define HRTIM_ADC1R_AD1MC1            HRTIM_ADC1R_AD1MC1_Msk                   /*!< ADC Trigger 1 on master compare 1 */
+#define HRTIM_ADC1R_AD1MC2_Pos        (1U)
+#define HRTIM_ADC1R_AD1MC2_Msk        (0x1UL << HRTIM_ADC1R_AD1MC2_Pos)        /*!< 0x00000002 */
+#define HRTIM_ADC1R_AD1MC2            HRTIM_ADC1R_AD1MC2_Msk                   /*!< ADC Trigger 1 on master compare 2 */
+#define HRTIM_ADC1R_AD1MC3_Pos        (2U)
+#define HRTIM_ADC1R_AD1MC3_Msk        (0x1UL << HRTIM_ADC1R_AD1MC3_Pos)        /*!< 0x00000004 */
+#define HRTIM_ADC1R_AD1MC3            HRTIM_ADC1R_AD1MC3_Msk                   /*!< ADC Trigger 1 on master compare 3 */
+#define HRTIM_ADC1R_AD1MC4_Pos        (3U)
+#define HRTIM_ADC1R_AD1MC4_Msk        (0x1UL << HRTIM_ADC1R_AD1MC4_Pos)        /*!< 0x00000008 */
+#define HRTIM_ADC1R_AD1MC4            HRTIM_ADC1R_AD1MC4_Msk                   /*!< ADC Trigger 1 on master compare 4 */
+#define HRTIM_ADC1R_AD1MPER_Pos       (4U)
+#define HRTIM_ADC1R_AD1MPER_Msk       (0x1UL << HRTIM_ADC1R_AD1MPER_Pos)       /*!< 0x00000010 */
+#define HRTIM_ADC1R_AD1MPER           HRTIM_ADC1R_AD1MPER_Msk                  /*!< ADC Trigger 1 on master period */
+#define HRTIM_ADC1R_AD1EEV1_Pos       (5U)
+#define HRTIM_ADC1R_AD1EEV1_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV1_Pos)       /*!< 0x00000020 */
+#define HRTIM_ADC1R_AD1EEV1           HRTIM_ADC1R_AD1EEV1_Msk                  /*!< ADC Trigger 1 on external event 1 */
+#define HRTIM_ADC1R_AD1EEV2_Pos       (6U)
+#define HRTIM_ADC1R_AD1EEV2_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV2_Pos)       /*!< 0x00000040 */
+#define HRTIM_ADC1R_AD1EEV2           HRTIM_ADC1R_AD1EEV2_Msk                  /*!< ADC Trigger 1 on external event 2 */
+#define HRTIM_ADC1R_AD1EEV3_Pos       (7U)
+#define HRTIM_ADC1R_AD1EEV3_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV3_Pos)       /*!< 0x00000080 */
+#define HRTIM_ADC1R_AD1EEV3           HRTIM_ADC1R_AD1EEV3_Msk                  /*!< ADC Trigger 1 on external event 3 */
+#define HRTIM_ADC1R_AD1EEV4_Pos       (8U)
+#define HRTIM_ADC1R_AD1EEV4_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV4_Pos)       /*!< 0x00000100 */
+#define HRTIM_ADC1R_AD1EEV4           HRTIM_ADC1R_AD1EEV4_Msk                  /*!< ADC Trigger 1 on external event 4 */
+#define HRTIM_ADC1R_AD1EEV5_Pos       (9U)
+#define HRTIM_ADC1R_AD1EEV5_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV5_Pos)       /*!< 0x00000200 */
+#define HRTIM_ADC1R_AD1EEV5           HRTIM_ADC1R_AD1EEV5_Msk                  /*!< ADC Trigger 1 on external event 5 */
+#define HRTIM_ADC1R_AD1TAC2_Pos       (10U)
+#define HRTIM_ADC1R_AD1TAC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC2_Pos)       /*!< 0x00000400 */
+#define HRTIM_ADC1R_AD1TAC2           HRTIM_ADC1R_AD1TAC2_Msk                  /*!< ADC Trigger 1 on Timer A compare 2 */
+#define HRTIM_ADC1R_AD1TAC3_Pos       (11U)
+#define HRTIM_ADC1R_AD1TAC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC3_Pos)       /*!< 0x00000800 */
+#define HRTIM_ADC1R_AD1TAC3           HRTIM_ADC1R_AD1TAC3_Msk                  /*!< ADC Trigger 1 on Timer A compare 3 */
+#define HRTIM_ADC1R_AD1TAC4_Pos       (12U)
+#define HRTIM_ADC1R_AD1TAC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC4_Pos)       /*!< 0x00001000 */
+#define HRTIM_ADC1R_AD1TAC4           HRTIM_ADC1R_AD1TAC4_Msk                  /*!< ADC Trigger 1 on Timer A compare 4 */
+#define HRTIM_ADC1R_AD1TAPER_Pos      (13U)
+#define HRTIM_ADC1R_AD1TAPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TAPER_Pos)      /*!< 0x00002000 */
+#define HRTIM_ADC1R_AD1TAPER          HRTIM_ADC1R_AD1TAPER_Msk                 /*!< ADC Trigger 1 on Timer A period */
+#define HRTIM_ADC1R_AD1TARST_Pos      (14U)
+#define HRTIM_ADC1R_AD1TARST_Msk      (0x1UL << HRTIM_ADC1R_AD1TARST_Pos)      /*!< 0x00004000 */
+#define HRTIM_ADC1R_AD1TARST          HRTIM_ADC1R_AD1TARST_Msk                 /*!< ADC Trigger 1 on Timer A reset */
+#define HRTIM_ADC1R_AD1TBC2_Pos       (15U)
+#define HRTIM_ADC1R_AD1TBC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC2_Pos)       /*!< 0x00008000 */
+#define HRTIM_ADC1R_AD1TBC2           HRTIM_ADC1R_AD1TBC2_Msk                  /*!< ADC Trigger 1 on Timer B compare 2 */
+#define HRTIM_ADC1R_AD1TBC3_Pos       (16U)
+#define HRTIM_ADC1R_AD1TBC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC3_Pos)       /*!< 0x00010000 */
+#define HRTIM_ADC1R_AD1TBC3           HRTIM_ADC1R_AD1TBC3_Msk                  /*!< ADC Trigger 1 on Timer B compare 3 */
+#define HRTIM_ADC1R_AD1TBC4_Pos       (17U)
+#define HRTIM_ADC1R_AD1TBC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC4_Pos)       /*!< 0x00020000 */
+#define HRTIM_ADC1R_AD1TBC4           HRTIM_ADC1R_AD1TBC4_Msk                  /*!< ADC Trigger 1 on Timer B compare 4 */
+#define HRTIM_ADC1R_AD1TBPER_Pos      (18U)
+#define HRTIM_ADC1R_AD1TBPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TBPER_Pos)      /*!< 0x00040000 */
+#define HRTIM_ADC1R_AD1TBPER          HRTIM_ADC1R_AD1TBPER_Msk                 /*!< ADC Trigger 1 on Timer B period */
+#define HRTIM_ADC1R_AD1TBRST_Pos      (19U)
+#define HRTIM_ADC1R_AD1TBRST_Msk      (0x1UL << HRTIM_ADC1R_AD1TBRST_Pos)      /*!< 0x00080000 */
+#define HRTIM_ADC1R_AD1TBRST          HRTIM_ADC1R_AD1TBRST_Msk                 /*!< ADC Trigger 1 on Timer B reset */
+#define HRTIM_ADC1R_AD1TCC2_Pos       (20U)
+#define HRTIM_ADC1R_AD1TCC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC2_Pos)       /*!< 0x00100000 */
+#define HRTIM_ADC1R_AD1TCC2           HRTIM_ADC1R_AD1TCC2_Msk                  /*!< ADC Trigger 1 on Timer C compare 2 */
+#define HRTIM_ADC1R_AD1TCC3_Pos       (21U)
+#define HRTIM_ADC1R_AD1TCC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC3_Pos)       /*!< 0x00200000 */
+#define HRTIM_ADC1R_AD1TCC3           HRTIM_ADC1R_AD1TCC3_Msk                  /*!< ADC Trigger 1 on Timer C compare 3 */
+#define HRTIM_ADC1R_AD1TCC4_Pos       (22U)
+#define HRTIM_ADC1R_AD1TCC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC4_Pos)       /*!< 0x00400000 */
+#define HRTIM_ADC1R_AD1TCC4           HRTIM_ADC1R_AD1TCC4_Msk                  /*!< ADC Trigger 1 on Timer C compare 4 */
+#define HRTIM_ADC1R_AD1TCPER_Pos      (23U)
+#define HRTIM_ADC1R_AD1TCPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TCPER_Pos)      /*!< 0x00800000 */
+#define HRTIM_ADC1R_AD1TCPER          HRTIM_ADC1R_AD1TCPER_Msk                 /*!< ADC Trigger 1 on Timer C period */
+#define HRTIM_ADC1R_AD1TDC2_Pos       (24U)
+#define HRTIM_ADC1R_AD1TDC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC2_Pos)       /*!< 0x01000000 */
+#define HRTIM_ADC1R_AD1TDC2           HRTIM_ADC1R_AD1TDC2_Msk                  /*!< ADC Trigger 1 on Timer D compare 2 */
+#define HRTIM_ADC1R_AD1TDC3_Pos       (25U)
+#define HRTIM_ADC1R_AD1TDC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC3_Pos)       /*!< 0x02000000 */
+#define HRTIM_ADC1R_AD1TDC3           HRTIM_ADC1R_AD1TDC3_Msk                  /*!< ADC Trigger 1 on Timer D compare 3 */
+#define HRTIM_ADC1R_AD1TDC4_Pos       (26U)
+#define HRTIM_ADC1R_AD1TDC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC4_Pos)       /*!< 0x04000000 */
+#define HRTIM_ADC1R_AD1TDC4           HRTIM_ADC1R_AD1TDC4_Msk                  /*!< ADC Trigger 1 on Timer D compare 4 */
+#define HRTIM_ADC1R_AD1TDPER_Pos      (27U)
+#define HRTIM_ADC1R_AD1TDPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TDPER_Pos)      /*!< 0x08000000 */
+#define HRTIM_ADC1R_AD1TDPER          HRTIM_ADC1R_AD1TDPER_Msk                 /*!< ADC Trigger 1 on Timer D period */
+#define HRTIM_ADC1R_AD1TEC2_Pos       (28U)
+#define HRTIM_ADC1R_AD1TEC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC2_Pos)       /*!< 0x10000000 */
+#define HRTIM_ADC1R_AD1TEC2           HRTIM_ADC1R_AD1TEC2_Msk                  /*!< ADC Trigger 1 on Timer E compare 2 */
+#define HRTIM_ADC1R_AD1TEC3_Pos       (29U)
+#define HRTIM_ADC1R_AD1TEC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC3_Pos)       /*!< 0x20000000 */
+#define HRTIM_ADC1R_AD1TEC3           HRTIM_ADC1R_AD1TEC3_Msk                  /*!< ADC Trigger 1 on Timer E compare 3 */
+#define HRTIM_ADC1R_AD1TEC4_Pos       (30U)
+#define HRTIM_ADC1R_AD1TEC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC4_Pos)       /*!< 0x40000000 */
+#define HRTIM_ADC1R_AD1TEC4           HRTIM_ADC1R_AD1TEC4_Msk                  /*!< ADC Trigger 1 on Timer E compare 4 */
+#define HRTIM_ADC1R_AD1TEPER_Pos      (31U)
+#define HRTIM_ADC1R_AD1TEPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TEPER_Pos)      /*!< 0x80000000 */
+#define HRTIM_ADC1R_AD1TEPER          HRTIM_ADC1R_AD1TEPER_Msk                 /*!< ADC Trigger 1 on Timer E period */
+
+/*******************  Bit definition for HRTIM_ADC2R register  ****************/
+#define HRTIM_ADC2R_AD2MC1_Pos        (0U)
+#define HRTIM_ADC2R_AD2MC1_Msk        (0x1UL << HRTIM_ADC2R_AD2MC1_Pos)        /*!< 0x00000001 */
+#define HRTIM_ADC2R_AD2MC1            HRTIM_ADC2R_AD2MC1_Msk                   /*!< ADC Trigger 2 on master compare 1 */
+#define HRTIM_ADC2R_AD2MC2_Pos        (1U)
+#define HRTIM_ADC2R_AD2MC2_Msk        (0x1UL << HRTIM_ADC2R_AD2MC2_Pos)        /*!< 0x00000002 */
+#define HRTIM_ADC2R_AD2MC2            HRTIM_ADC2R_AD2MC2_Msk                   /*!< ADC Trigger 2 on master compare 2 */
+#define HRTIM_ADC2R_AD2MC3_Pos        (2U)
+#define HRTIM_ADC2R_AD2MC3_Msk        (0x1UL << HRTIM_ADC2R_AD2MC3_Pos)        /*!< 0x00000004 */
+#define HRTIM_ADC2R_AD2MC3            HRTIM_ADC2R_AD2MC3_Msk                   /*!< ADC Trigger 2 on master compare 3 */
+#define HRTIM_ADC2R_AD2MC4_Pos        (3U)
+#define HRTIM_ADC2R_AD2MC4_Msk        (0x1UL << HRTIM_ADC2R_AD2MC4_Pos)        /*!< 0x00000008 */
+#define HRTIM_ADC2R_AD2MC4            HRTIM_ADC2R_AD2MC4_Msk                   /*!< ADC Trigger 2 on master compare 4 */
+#define HRTIM_ADC2R_AD2MPER_Pos       (4U)
+#define HRTIM_ADC2R_AD2MPER_Msk       (0x1UL << HRTIM_ADC2R_AD2MPER_Pos)       /*!< 0x00000010 */
+#define HRTIM_ADC2R_AD2MPER           HRTIM_ADC2R_AD2MPER_Msk                  /*!< ADC Trigger 2 on master period */
+#define HRTIM_ADC2R_AD2EEV6_Pos       (5U)
+#define HRTIM_ADC2R_AD2EEV6_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV6_Pos)       /*!< 0x00000020 */
+#define HRTIM_ADC2R_AD2EEV6           HRTIM_ADC2R_AD2EEV6_Msk                  /*!< ADC Trigger 2 on external event 6 */
+#define HRTIM_ADC2R_AD2EEV7_Pos       (6U)
+#define HRTIM_ADC2R_AD2EEV7_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV7_Pos)       /*!< 0x00000040 */
+#define HRTIM_ADC2R_AD2EEV7           HRTIM_ADC2R_AD2EEV7_Msk                  /*!< ADC Trigger 2 on external event 7 */
+#define HRTIM_ADC2R_AD2EEV8_Pos       (7U)
+#define HRTIM_ADC2R_AD2EEV8_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV8_Pos)       /*!< 0x00000080 */
+#define HRTIM_ADC2R_AD2EEV8           HRTIM_ADC2R_AD2EEV8_Msk                  /*!< ADC Trigger 2 on external event 8 */
+#define HRTIM_ADC2R_AD2EEV9_Pos       (8U)
+#define HRTIM_ADC2R_AD2EEV9_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV9_Pos)       /*!< 0x00000100 */
+#define HRTIM_ADC2R_AD2EEV9           HRTIM_ADC2R_AD2EEV9_Msk                  /*!< ADC Trigger 2 on external event 9 */
+#define HRTIM_ADC2R_AD2EEV10_Pos      (9U)
+#define HRTIM_ADC2R_AD2EEV10_Msk      (0x1UL << HRTIM_ADC2R_AD2EEV10_Pos)      /*!< 0x00000200 */
+#define HRTIM_ADC2R_AD2EEV10          HRTIM_ADC2R_AD2EEV10_Msk                 /*!< ADC Trigger 2 on external event 10 */
+#define HRTIM_ADC2R_AD2TAC2_Pos       (10U)
+#define HRTIM_ADC2R_AD2TAC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC2_Pos)       /*!< 0x00000400 */
+#define HRTIM_ADC2R_AD2TAC2           HRTIM_ADC2R_AD2TAC2_Msk                  /*!< ADC Trigger 2 on Timer A compare 2 */
+#define HRTIM_ADC2R_AD2TAC3_Pos       (11U)
+#define HRTIM_ADC2R_AD2TAC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC3_Pos)       /*!< 0x00000800 */
+#define HRTIM_ADC2R_AD2TAC3           HRTIM_ADC2R_AD2TAC3_Msk                  /*!< ADC Trigger 2 on Timer A compare 3 */
+#define HRTIM_ADC2R_AD2TAC4_Pos       (12U)
+#define HRTIM_ADC2R_AD2TAC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC4_Pos)       /*!< 0x00001000 */
+#define HRTIM_ADC2R_AD2TAC4           HRTIM_ADC2R_AD2TAC4_Msk                  /*!< ADC Trigger 2 on Timer A compare 4*/
+#define HRTIM_ADC2R_AD2TAPER_Pos      (13U)
+#define HRTIM_ADC2R_AD2TAPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TAPER_Pos)      /*!< 0x00002000 */
+#define HRTIM_ADC2R_AD2TAPER          HRTIM_ADC2R_AD2TAPER_Msk                 /*!< ADC Trigger 2 on Timer A period */
+#define HRTIM_ADC2R_AD2TBC2_Pos       (14U)
+#define HRTIM_ADC2R_AD2TBC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC2_Pos)       /*!< 0x00004000 */
+#define HRTIM_ADC2R_AD2TBC2           HRTIM_ADC2R_AD2TBC2_Msk                  /*!< ADC Trigger 2 on Timer B compare 2 */
+#define HRTIM_ADC2R_AD2TBC3_Pos       (15U)
+#define HRTIM_ADC2R_AD2TBC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC3_Pos)       /*!< 0x00008000 */
+#define HRTIM_ADC2R_AD2TBC3           HRTIM_ADC2R_AD2TBC3_Msk                  /*!< ADC Trigger 2 on Timer B compare 3 */
+#define HRTIM_ADC2R_AD2TBC4_Pos       (16U)
+#define HRTIM_ADC2R_AD2TBC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC4_Pos)       /*!< 0x00010000 */
+#define HRTIM_ADC2R_AD2TBC4           HRTIM_ADC2R_AD2TBC4_Msk                  /*!< ADC Trigger 2 on Timer B compare 4 */
+#define HRTIM_ADC2R_AD2TBPER_Pos      (17U)
+#define HRTIM_ADC2R_AD2TBPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TBPER_Pos)      /*!< 0x00020000 */
+#define HRTIM_ADC2R_AD2TBPER          HRTIM_ADC2R_AD2TBPER_Msk                 /*!< ADC Trigger 2 on Timer B period */
+#define HRTIM_ADC2R_AD2TCC2_Pos       (18U)
+#define HRTIM_ADC2R_AD2TCC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC2_Pos)       /*!< 0x00040000 */
+#define HRTIM_ADC2R_AD2TCC2           HRTIM_ADC2R_AD2TCC2_Msk                  /*!< ADC Trigger 2 on Timer C compare 2 */
+#define HRTIM_ADC2R_AD2TCC3_Pos       (19U)
+#define HRTIM_ADC2R_AD2TCC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC3_Pos)       /*!< 0x00080000 */
+#define HRTIM_ADC2R_AD2TCC3           HRTIM_ADC2R_AD2TCC3_Msk                  /*!< ADC Trigger 2 on Timer C compare 3 */
+#define HRTIM_ADC2R_AD2TCC4_Pos       (20U)
+#define HRTIM_ADC2R_AD2TCC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC4_Pos)       /*!< 0x00100000 */
+#define HRTIM_ADC2R_AD2TCC4           HRTIM_ADC2R_AD2TCC4_Msk                  /*!< ADC Trigger 2 on Timer C compare 4 */
+#define HRTIM_ADC2R_AD2TCPER_Pos      (21U)
+#define HRTIM_ADC2R_AD2TCPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TCPER_Pos)      /*!< 0x00200000 */
+#define HRTIM_ADC2R_AD2TCPER          HRTIM_ADC2R_AD2TCPER_Msk                 /*!< ADC Trigger 2 on Timer C period */
+#define HRTIM_ADC2R_AD2TCRST_Pos      (22U)
+#define HRTIM_ADC2R_AD2TCRST_Msk      (0x1UL << HRTIM_ADC2R_AD2TCRST_Pos)      /*!< 0x00400000 */
+#define HRTIM_ADC2R_AD2TCRST          HRTIM_ADC2R_AD2TCRST_Msk                 /*!< ADC Trigger 2 on Timer C reset */
+#define HRTIM_ADC2R_AD2TDC2_Pos       (23U)
+#define HRTIM_ADC2R_AD2TDC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC2_Pos)       /*!< 0x00800000 */
+#define HRTIM_ADC2R_AD2TDC2           HRTIM_ADC2R_AD2TDC2_Msk                  /*!< ADC Trigger 2 on Timer D compare 2 */
+#define HRTIM_ADC2R_AD2TDC3_Pos       (24U)
+#define HRTIM_ADC2R_AD2TDC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC3_Pos)       /*!< 0x01000000 */
+#define HRTIM_ADC2R_AD2TDC3           HRTIM_ADC2R_AD2TDC3_Msk                  /*!< ADC Trigger 2 on Timer D compare 3 */
+#define HRTIM_ADC2R_AD2TDC4_Pos       (25U)
+#define HRTIM_ADC2R_AD2TDC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC4_Pos)       /*!< 0x02000000 */
+#define HRTIM_ADC2R_AD2TDC4           HRTIM_ADC2R_AD2TDC4_Msk                  /*!< ADC Trigger 2 on Timer D compare 4*/
+#define HRTIM_ADC2R_AD2TDPER_Pos      (26U)
+#define HRTIM_ADC2R_AD2TDPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TDPER_Pos)      /*!< 0x04000000 */
+#define HRTIM_ADC2R_AD2TDPER          HRTIM_ADC2R_AD2TDPER_Msk                 /*!< ADC Trigger 2 on Timer D period */
+#define HRTIM_ADC2R_AD2TDRST_Pos      (27U)
+#define HRTIM_ADC2R_AD2TDRST_Msk      (0x1UL << HRTIM_ADC2R_AD2TDRST_Pos)      /*!< 0x08000000 */
+#define HRTIM_ADC2R_AD2TDRST          HRTIM_ADC2R_AD2TDRST_Msk                 /*!< ADC Trigger 2 on Timer D reset */
+#define HRTIM_ADC2R_AD2TEC2_Pos       (28U)
+#define HRTIM_ADC2R_AD2TEC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC2_Pos)       /*!< 0x10000000 */
+#define HRTIM_ADC2R_AD2TEC2           HRTIM_ADC2R_AD2TEC2_Msk                  /*!< ADC Trigger 2 on Timer E compare 2 */
+#define HRTIM_ADC2R_AD2TEC3_Pos       (29U)
+#define HRTIM_ADC2R_AD2TEC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC3_Pos)       /*!< 0x20000000 */
+#define HRTIM_ADC2R_AD2TEC3           HRTIM_ADC2R_AD2TEC3_Msk                  /*!< ADC Trigger 2 on Timer E compare 3 */
+#define HRTIM_ADC2R_AD2TEC4_Pos       (30U)
+#define HRTIM_ADC2R_AD2TEC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC4_Pos)       /*!< 0x40000000 */
+#define HRTIM_ADC2R_AD2TEC4           HRTIM_ADC2R_AD2TEC4_Msk                  /*!< ADC Trigger 2 on Timer E compare 4 */
+#define HRTIM_ADC2R_AD2TERST_Pos      (31U)
+#define HRTIM_ADC2R_AD2TERST_Msk      (0x1UL << HRTIM_ADC2R_AD2TERST_Pos)      /*!< 0x80000000 */
+#define HRTIM_ADC2R_AD2TERST          HRTIM_ADC2R_AD2TERST_Msk                 /*!< ADC Trigger 2 on Timer E reset */
+
+/*******************  Bit definition for HRTIM_ADC3R register  ****************/
+#define HRTIM_ADC3R_AD3MC1_Pos        (0U)
+#define HRTIM_ADC3R_AD3MC1_Msk        (0x1UL << HRTIM_ADC3R_AD3MC1_Pos)        /*!< 0x00000001 */
+#define HRTIM_ADC3R_AD3MC1            HRTIM_ADC3R_AD3MC1_Msk                   /*!< ADC Trigger 3 on master compare 1 */
+#define HRTIM_ADC3R_AD3MC2_Pos        (1U)
+#define HRTIM_ADC3R_AD3MC2_Msk        (0x1UL << HRTIM_ADC3R_AD3MC2_Pos)        /*!< 0x00000002 */
+#define HRTIM_ADC3R_AD3MC2            HRTIM_ADC3R_AD3MC2_Msk                   /*!< ADC Trigger 3 on master compare 2 */
+#define HRTIM_ADC3R_AD3MC3_Pos        (2U)
+#define HRTIM_ADC3R_AD3MC3_Msk        (0x1UL << HRTIM_ADC3R_AD3MC3_Pos)        /*!< 0x00000004 */
+#define HRTIM_ADC3R_AD3MC3            HRTIM_ADC3R_AD3MC3_Msk                   /*!< ADC Trigger 3 on master compare 3 */
+#define HRTIM_ADC3R_AD3MC4_Pos        (3U)
+#define HRTIM_ADC3R_AD3MC4_Msk        (0x1UL << HRTIM_ADC3R_AD3MC4_Pos)        /*!< 0x00000008 */
+#define HRTIM_ADC3R_AD3MC4            HRTIM_ADC3R_AD3MC4_Msk                   /*!< ADC Trigger 3 on master compare 4 */
+#define HRTIM_ADC3R_AD3MPER_Pos       (4U)
+#define HRTIM_ADC3R_AD3MPER_Msk       (0x1UL << HRTIM_ADC3R_AD3MPER_Pos)       /*!< 0x00000010 */
+#define HRTIM_ADC3R_AD3MPER           HRTIM_ADC3R_AD3MPER_Msk                  /*!< ADC Trigger 3 on master period */
+#define HRTIM_ADC3R_AD3EEV1_Pos       (5U)
+#define HRTIM_ADC3R_AD3EEV1_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV1_Pos)       /*!< 0x00000020 */
+#define HRTIM_ADC3R_AD3EEV1           HRTIM_ADC3R_AD3EEV1_Msk                  /*!< ADC Trigger 3 on external event 1 */
+#define HRTIM_ADC3R_AD3EEV2_Pos       (6U)
+#define HRTIM_ADC3R_AD3EEV2_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV2_Pos)       /*!< 0x00000040 */
+#define HRTIM_ADC3R_AD3EEV2           HRTIM_ADC3R_AD3EEV2_Msk                  /*!< ADC Trigger 3 on external event 2 */
+#define HRTIM_ADC3R_AD3EEV3_Pos       (7U)
+#define HRTIM_ADC3R_AD3EEV3_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV3_Pos)       /*!< 0x00000080 */
+#define HRTIM_ADC3R_AD3EEV3           HRTIM_ADC3R_AD3EEV3_Msk                  /*!< ADC Trigger 3 on external event 3 */
+#define HRTIM_ADC3R_AD3EEV4_Pos       (8U)
+#define HRTIM_ADC3R_AD3EEV4_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV4_Pos)       /*!< 0x00000100 */
+#define HRTIM_ADC3R_AD3EEV4           HRTIM_ADC3R_AD3EEV4_Msk                  /*!< ADC Trigger 3 on external event 4 */
+#define HRTIM_ADC3R_AD3EEV5_Pos       (9U)
+#define HRTIM_ADC3R_AD3EEV5_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV5_Pos)       /*!< 0x00000200 */
+#define HRTIM_ADC3R_AD3EEV5           HRTIM_ADC3R_AD3EEV5_Msk                  /*!< ADC Trigger 3 on external event 5 */
+#define HRTIM_ADC3R_AD3TAC2_Pos       (10U)
+#define HRTIM_ADC3R_AD3TAC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC2_Pos)       /*!< 0x00000400 */
+#define HRTIM_ADC3R_AD3TAC2           HRTIM_ADC3R_AD3TAC2_Msk                  /*!< ADC Trigger 3 on Timer A compare 2 */
+#define HRTIM_ADC3R_AD3TAC3_Pos       (11U)
+#define HRTIM_ADC3R_AD3TAC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC3_Pos)       /*!< 0x00000800 */
+#define HRTIM_ADC3R_AD3TAC3           HRTIM_ADC3R_AD3TAC3_Msk                  /*!< ADC Trigger 3 on Timer A compare 3 */
+#define HRTIM_ADC3R_AD3TAC4_Pos       (12U)
+#define HRTIM_ADC3R_AD3TAC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC4_Pos)       /*!< 0x00001000 */
+#define HRTIM_ADC3R_AD3TAC4           HRTIM_ADC3R_AD3TAC4_Msk                  /*!< ADC Trigger 3 on Timer A compare 4 */
+#define HRTIM_ADC3R_AD3TAPER_Pos      (13U)
+#define HRTIM_ADC3R_AD3TAPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TAPER_Pos)      /*!< 0x00002000 */
+#define HRTIM_ADC3R_AD3TAPER          HRTIM_ADC3R_AD3TAPER_Msk                 /*!< ADC Trigger 3 on Timer A period */
+#define HRTIM_ADC3R_AD3TARST_Pos      (14U)
+#define HRTIM_ADC3R_AD3TARST_Msk      (0x1UL << HRTIM_ADC3R_AD3TARST_Pos)      /*!< 0x00004000 */
+#define HRTIM_ADC3R_AD3TARST          HRTIM_ADC3R_AD3TARST_Msk                 /*!< ADC Trigger 3 on Timer A reset */
+#define HRTIM_ADC3R_AD3TBC2_Pos       (15U)
+#define HRTIM_ADC3R_AD3TBC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC2_Pos)       /*!< 0x00008000 */
+#define HRTIM_ADC3R_AD3TBC2           HRTIM_ADC3R_AD3TBC2_Msk                  /*!< ADC Trigger 3 on Timer B compare 2 */
+#define HRTIM_ADC3R_AD3TBC3_Pos       (16U)
+#define HRTIM_ADC3R_AD3TBC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC3_Pos)       /*!< 0x00010000 */
+#define HRTIM_ADC3R_AD3TBC3           HRTIM_ADC3R_AD3TBC3_Msk                  /*!< ADC Trigger 3 on Timer B compare 3 */
+#define HRTIM_ADC3R_AD3TBC4_Pos       (17U)
+#define HRTIM_ADC3R_AD3TBC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC4_Pos)       /*!< 0x00020000 */
+#define HRTIM_ADC3R_AD3TBC4           HRTIM_ADC3R_AD3TBC4_Msk                  /*!< ADC Trigger 3 on Timer B compare 4 */
+#define HRTIM_ADC3R_AD3TBPER_Pos      (18U)
+#define HRTIM_ADC3R_AD3TBPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TBPER_Pos)      /*!< 0x00040000 */
+#define HRTIM_ADC3R_AD3TBPER          HRTIM_ADC3R_AD3TBPER_Msk                 /*!< ADC Trigger 3 on Timer B period */
+#define HRTIM_ADC3R_AD3TBRST_Pos      (19U)
+#define HRTIM_ADC3R_AD3TBRST_Msk      (0x1UL << HRTIM_ADC3R_AD3TBRST_Pos)      /*!< 0x00080000 */
+#define HRTIM_ADC3R_AD3TBRST          HRTIM_ADC3R_AD3TBRST_Msk                 /*!< ADC Trigger 3 on Timer B reset */
+#define HRTIM_ADC3R_AD3TCC2_Pos       (20U)
+#define HRTIM_ADC3R_AD3TCC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC2_Pos)       /*!< 0x00100000 */
+#define HRTIM_ADC3R_AD3TCC2           HRTIM_ADC3R_AD3TCC2_Msk                  /*!< ADC Trigger 3 on Timer C compare 2 */
+#define HRTIM_ADC3R_AD3TCC3_Pos       (21U)
+#define HRTIM_ADC3R_AD3TCC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC3_Pos)       /*!< 0x00200000 */
+#define HRTIM_ADC3R_AD3TCC3           HRTIM_ADC3R_AD3TCC3_Msk                  /*!< ADC Trigger 3 on Timer C compare 3 */
+#define HRTIM_ADC3R_AD3TCC4_Pos       (22U)
+#define HRTIM_ADC3R_AD3TCC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC4_Pos)       /*!< 0x00400000 */
+#define HRTIM_ADC3R_AD3TCC4           HRTIM_ADC3R_AD3TCC4_Msk                  /*!< ADC Trigger 3 on Timer C compare 4 */
+#define HRTIM_ADC3R_AD3TCPER_Pos      (23U)
+#define HRTIM_ADC3R_AD3TCPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TCPER_Pos)      /*!< 0x00800000 */
+#define HRTIM_ADC3R_AD3TCPER          HRTIM_ADC3R_AD3TCPER_Msk                 /*!< ADC Trigger 3 on Timer C period */
+#define HRTIM_ADC3R_AD3TDC2_Pos       (24U)
+#define HRTIM_ADC3R_AD3TDC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC2_Pos)       /*!< 0x01000000 */
+#define HRTIM_ADC3R_AD3TDC2           HRTIM_ADC3R_AD3TDC2_Msk                  /*!< ADC Trigger 3 on Timer D compare 2 */
+#define HRTIM_ADC3R_AD3TDC3_Pos       (25U)
+#define HRTIM_ADC3R_AD3TDC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC3_Pos)       /*!< 0x02000000 */
+#define HRTIM_ADC3R_AD3TDC3           HRTIM_ADC3R_AD3TDC3_Msk                  /*!< ADC Trigger 3 on Timer D compare 3 */
+#define HRTIM_ADC3R_AD3TDC4_Pos       (26U)
+#define HRTIM_ADC3R_AD3TDC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC4_Pos)       /*!< 0x04000000 */
+#define HRTIM_ADC3R_AD3TDC4           HRTIM_ADC3R_AD3TDC4_Msk                  /*!< ADC Trigger 3 on Timer D compare 4 */
+#define HRTIM_ADC3R_AD3TDPER_Pos      (27U)
+#define HRTIM_ADC3R_AD3TDPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TDPER_Pos)      /*!< 0x08000000 */
+#define HRTIM_ADC3R_AD3TDPER          HRTIM_ADC3R_AD3TDPER_Msk                 /*!< ADC Trigger 3 on Timer D period */
+#define HRTIM_ADC3R_AD3TEC2_Pos       (28U)
+#define HRTIM_ADC3R_AD3TEC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC2_Pos)       /*!< 0x10000000 */
+#define HRTIM_ADC3R_AD3TEC2           HRTIM_ADC3R_AD3TEC2_Msk                  /*!< ADC Trigger 3 on Timer E compare 2 */
+#define HRTIM_ADC3R_AD3TEC3_Pos       (29U)
+#define HRTIM_ADC3R_AD3TEC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC3_Pos)       /*!< 0x20000000 */
+#define HRTIM_ADC3R_AD3TEC3           HRTIM_ADC3R_AD3TEC3_Msk                  /*!< ADC Trigger 3 on Timer E compare 3 */
+#define HRTIM_ADC3R_AD3TEC4_Pos       (30U)
+#define HRTIM_ADC3R_AD3TEC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC4_Pos)       /*!< 0x40000000 */
+#define HRTIM_ADC3R_AD3TEC4           HRTIM_ADC3R_AD3TEC4_Msk                  /*!< ADC Trigger 3 on Timer E compare 4 */
+#define HRTIM_ADC3R_AD3TEPER_Pos      (31U)
+#define HRTIM_ADC3R_AD3TEPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TEPER_Pos)      /*!< 0x80000000 */
+#define HRTIM_ADC3R_AD3TEPER          HRTIM_ADC3R_AD3TEPER_Msk                 /*!< ADC Trigger 3 on Timer E period */
+
+/*******************  Bit definition for HRTIM_ADC4R register  ****************/
+#define HRTIM_ADC4R_AD4MC1_Pos        (0U)
+#define HRTIM_ADC4R_AD4MC1_Msk        (0x1UL << HRTIM_ADC4R_AD4MC1_Pos)        /*!< 0x00000001 */
+#define HRTIM_ADC4R_AD4MC1            HRTIM_ADC4R_AD4MC1_Msk                   /*!< ADC Trigger 4 on master compare 1 */
+#define HRTIM_ADC4R_AD4MC2_Pos        (1U)
+#define HRTIM_ADC4R_AD4MC2_Msk        (0x1UL << HRTIM_ADC4R_AD4MC2_Pos)        /*!< 0x00000002 */
+#define HRTIM_ADC4R_AD4MC2            HRTIM_ADC4R_AD4MC2_Msk                   /*!< ADC Trigger 4 on master compare 2 */
+#define HRTIM_ADC4R_AD4MC3_Pos        (2U)
+#define HRTIM_ADC4R_AD4MC3_Msk        (0x1UL << HRTIM_ADC4R_AD4MC3_Pos)        /*!< 0x00000004 */
+#define HRTIM_ADC4R_AD4MC3            HRTIM_ADC4R_AD4MC3_Msk                   /*!< ADC Trigger 4 on master compare 3 */
+#define HRTIM_ADC4R_AD4MC4_Pos        (3U)
+#define HRTIM_ADC4R_AD4MC4_Msk        (0x1UL << HRTIM_ADC4R_AD4MC4_Pos)        /*!< 0x00000008 */
+#define HRTIM_ADC4R_AD4MC4            HRTIM_ADC4R_AD4MC4_Msk                   /*!< ADC Trigger 4 on master compare 4 */
+#define HRTIM_ADC4R_AD4MPER_Pos       (4U)
+#define HRTIM_ADC4R_AD4MPER_Msk       (0x1UL << HRTIM_ADC4R_AD4MPER_Pos)       /*!< 0x00000010 */
+#define HRTIM_ADC4R_AD4MPER           HRTIM_ADC4R_AD4MPER_Msk                  /*!< ADC Trigger 4 on master period */
+#define HRTIM_ADC4R_AD4EEV6_Pos       (5U)
+#define HRTIM_ADC4R_AD4EEV6_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV6_Pos)       /*!< 0x00000020 */
+#define HRTIM_ADC4R_AD4EEV6           HRTIM_ADC4R_AD4EEV6_Msk                  /*!< ADC Trigger 4 on external event 6 */
+#define HRTIM_ADC4R_AD4EEV7_Pos       (6U)
+#define HRTIM_ADC4R_AD4EEV7_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV7_Pos)       /*!< 0x00000040 */
+#define HRTIM_ADC4R_AD4EEV7           HRTIM_ADC4R_AD4EEV7_Msk                  /*!< ADC Trigger 4 on external event 7 */
+#define HRTIM_ADC4R_AD4EEV8_Pos       (7U)
+#define HRTIM_ADC4R_AD4EEV8_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV8_Pos)       /*!< 0x00000080 */
+#define HRTIM_ADC4R_AD4EEV8           HRTIM_ADC4R_AD4EEV8_Msk                  /*!< ADC Trigger 4 on external event 8 */
+#define HRTIM_ADC4R_AD4EEV9_Pos       (8U)
+#define HRTIM_ADC4R_AD4EEV9_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV9_Pos)       /*!< 0x00000100 */
+#define HRTIM_ADC4R_AD4EEV9           HRTIM_ADC4R_AD4EEV9_Msk                  /*!< ADC Trigger 4 on external event 9 */
+#define HRTIM_ADC4R_AD4EEV10_Pos      (9U)
+#define HRTIM_ADC4R_AD4EEV10_Msk      (0x1UL << HRTIM_ADC4R_AD4EEV10_Pos)      /*!< 0x00000200 */
+#define HRTIM_ADC4R_AD4EEV10          HRTIM_ADC4R_AD4EEV10_Msk                 /*!< ADC Trigger 4 on external event 10 */
+#define HRTIM_ADC4R_AD4TAC2_Pos       (10U)
+#define HRTIM_ADC4R_AD4TAC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC2_Pos)       /*!< 0x00000400 */
+#define HRTIM_ADC4R_AD4TAC2           HRTIM_ADC4R_AD4TAC2_Msk                  /*!< ADC Trigger 4 on Timer A compare 2 */
+#define HRTIM_ADC4R_AD4TAC3_Pos       (11U)
+#define HRTIM_ADC4R_AD4TAC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC3_Pos)       /*!< 0x00000800 */
+#define HRTIM_ADC4R_AD4TAC3           HRTIM_ADC4R_AD4TAC3_Msk                  /*!< ADC Trigger 4 on Timer A compare 3 */
+#define HRTIM_ADC4R_AD4TAC4_Pos       (12U)
+#define HRTIM_ADC4R_AD4TAC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC4_Pos)       /*!< 0x00001000 */
+#define HRTIM_ADC4R_AD4TAC4           HRTIM_ADC4R_AD4TAC4_Msk                  /*!< ADC Trigger 4 on Timer A compare 4*/
+#define HRTIM_ADC4R_AD4TAPER_Pos      (13U)
+#define HRTIM_ADC4R_AD4TAPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TAPER_Pos)      /*!< 0x00002000 */
+#define HRTIM_ADC4R_AD4TAPER          HRTIM_ADC4R_AD4TAPER_Msk                 /*!< ADC Trigger 4 on Timer A period */
+#define HRTIM_ADC4R_AD4TBC2_Pos       (14U)
+#define HRTIM_ADC4R_AD4TBC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC2_Pos)       /*!< 0x00004000 */
+#define HRTIM_ADC4R_AD4TBC2           HRTIM_ADC4R_AD4TBC2_Msk                  /*!< ADC Trigger 4 on Timer B compare 2 */
+#define HRTIM_ADC4R_AD4TBC3_Pos       (15U)
+#define HRTIM_ADC4R_AD4TBC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC3_Pos)       /*!< 0x00008000 */
+#define HRTIM_ADC4R_AD4TBC3           HRTIM_ADC4R_AD4TBC3_Msk                  /*!< ADC Trigger 4 on Timer B compare 3 */
+#define HRTIM_ADC4R_AD4TBC4_Pos       (16U)
+#define HRTIM_ADC4R_AD4TBC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC4_Pos)       /*!< 0x00010000 */
+#define HRTIM_ADC4R_AD4TBC4           HRTIM_ADC4R_AD4TBC4_Msk                  /*!< ADC Trigger 4 on Timer B compare 4 */
+#define HRTIM_ADC4R_AD4TBPER_Pos      (17U)
+#define HRTIM_ADC4R_AD4TBPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TBPER_Pos)      /*!< 0x00020000 */
+#define HRTIM_ADC4R_AD4TBPER          HRTIM_ADC4R_AD4TBPER_Msk                 /*!< ADC Trigger 4 on Timer B period */
+#define HRTIM_ADC4R_AD4TCC2_Pos       (18U)
+#define HRTIM_ADC4R_AD4TCC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC2_Pos)       /*!< 0x00040000 */
+#define HRTIM_ADC4R_AD4TCC2           HRTIM_ADC4R_AD4TCC2_Msk                  /*!< ADC Trigger 4 on Timer C compare 2 */
+#define HRTIM_ADC4R_AD4TCC3_Pos       (19U)
+#define HRTIM_ADC4R_AD4TCC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC3_Pos)       /*!< 0x00080000 */
+#define HRTIM_ADC4R_AD4TCC3           HRTIM_ADC4R_AD4TCC3_Msk                  /*!< ADC Trigger 4 on Timer C compare 3 */
+#define HRTIM_ADC4R_AD4TCC4_Pos       (20U)
+#define HRTIM_ADC4R_AD4TCC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC4_Pos)       /*!< 0x00100000 */
+#define HRTIM_ADC4R_AD4TCC4           HRTIM_ADC4R_AD4TCC4_Msk                  /*!< ADC Trigger 4 on Timer C compare 4 */
+#define HRTIM_ADC4R_AD4TCPER_Pos      (21U)
+#define HRTIM_ADC4R_AD4TCPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TCPER_Pos)      /*!< 0x00200000 */
+#define HRTIM_ADC4R_AD4TCPER          HRTIM_ADC4R_AD4TCPER_Msk                 /*!< ADC Trigger 4 on Timer C period */
+#define HRTIM_ADC4R_AD4TCRST_Pos      (22U)
+#define HRTIM_ADC4R_AD4TCRST_Msk      (0x1UL << HRTIM_ADC4R_AD4TCRST_Pos)      /*!< 0x00400000 */
+#define HRTIM_ADC4R_AD4TCRST          HRTIM_ADC4R_AD4TCRST_Msk                 /*!< ADC Trigger 4 on Timer C reset */
+#define HRTIM_ADC4R_AD4TDC2_Pos       (23U)
+#define HRTIM_ADC4R_AD4TDC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC2_Pos)       /*!< 0x00800000 */
+#define HRTIM_ADC4R_AD4TDC2           HRTIM_ADC4R_AD4TDC2_Msk                  /*!< ADC Trigger 4 on Timer D compare 2 */
+#define HRTIM_ADC4R_AD4TDC3_Pos       (24U)
+#define HRTIM_ADC4R_AD4TDC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC3_Pos)       /*!< 0x01000000 */
+#define HRTIM_ADC4R_AD4TDC3           HRTIM_ADC4R_AD4TDC3_Msk                  /*!< ADC Trigger 4 on Timer D compare 3 */
+#define HRTIM_ADC4R_AD4TDC4_Pos       (25U)
+#define HRTIM_ADC4R_AD4TDC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC4_Pos)       /*!< 0x02000000 */
+#define HRTIM_ADC4R_AD4TDC4           HRTIM_ADC4R_AD4TDC4_Msk                  /*!< ADC Trigger 4 on Timer D compare 4*/
+#define HRTIM_ADC4R_AD4TDPER_Pos      (26U)
+#define HRTIM_ADC4R_AD4TDPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TDPER_Pos)      /*!< 0x04000000 */
+#define HRTIM_ADC4R_AD4TDPER          HRTIM_ADC4R_AD4TDPER_Msk                 /*!< ADC Trigger 4 on Timer D period */
+#define HRTIM_ADC4R_AD4TDRST_Pos      (27U)
+#define HRTIM_ADC4R_AD4TDRST_Msk      (0x1UL << HRTIM_ADC4R_AD4TDRST_Pos)      /*!< 0x08000000 */
+#define HRTIM_ADC4R_AD4TDRST          HRTIM_ADC4R_AD4TDRST_Msk                 /*!< ADC Trigger 4 on Timer D reset */
+#define HRTIM_ADC4R_AD4TEC2_Pos       (28U)
+#define HRTIM_ADC4R_AD4TEC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC2_Pos)       /*!< 0x10000000 */
+#define HRTIM_ADC4R_AD4TEC2           HRTIM_ADC4R_AD4TEC2_Msk                  /*!< ADC Trigger 4 on Timer E compare 2 */
+#define HRTIM_ADC4R_AD4TEC3_Pos       (29U)
+#define HRTIM_ADC4R_AD4TEC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC3_Pos)       /*!< 0x20000000 */
+#define HRTIM_ADC4R_AD4TEC3           HRTIM_ADC4R_AD4TEC3_Msk                  /*!< ADC Trigger 4 on Timer E compare 3 */
+#define HRTIM_ADC4R_AD4TEC4_Pos       (30U)
+#define HRTIM_ADC4R_AD4TEC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC4_Pos)       /*!< 0x40000000 */
+#define HRTIM_ADC4R_AD4TEC4           HRTIM_ADC4R_AD4TEC4_Msk                  /*!< ADC Trigger 4 on Timer E compare 4 */
+#define HRTIM_ADC4R_AD4TERST_Pos      (31U)
+#define HRTIM_ADC4R_AD4TERST_Msk      (0x1UL << HRTIM_ADC4R_AD4TERST_Pos)      /*!< 0x80000000 */
+#define HRTIM_ADC4R_AD4TERST          HRTIM_ADC4R_AD4TERST_Msk                 /*!< ADC Trigger 4 on Timer E reset */
+
+/*******************  Bit definition for HRTIM_FLTINR1 register  ***************/
+#define HRTIM_FLTINR1_FLT1E_Pos       (0U)
+#define HRTIM_FLTINR1_FLT1E_Msk       (0x1UL << HRTIM_FLTINR1_FLT1E_Pos)       /*!< 0x00000001 */
+#define HRTIM_FLTINR1_FLT1E           HRTIM_FLTINR1_FLT1E_Msk                  /*!< Fault 1 enable */
+#define HRTIM_FLTINR1_FLT1P_Pos       (1U)
+#define HRTIM_FLTINR1_FLT1P_Msk       (0x1UL << HRTIM_FLTINR1_FLT1P_Pos)       /*!< 0x00000002 */
+#define HRTIM_FLTINR1_FLT1P           HRTIM_FLTINR1_FLT1P_Msk                  /*!< Fault 1 polarity */
+#define HRTIM_FLTINR1_FLT1SRC_Pos     (2U)
+#define HRTIM_FLTINR1_FLT1SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT1SRC_Pos)     /*!< 0x00000004 */
+#define HRTIM_FLTINR1_FLT1SRC         HRTIM_FLTINR1_FLT1SRC_Msk                /*!< Fault 1 source */
+#define HRTIM_FLTINR1_FLT1F_Pos       (3U)
+#define HRTIM_FLTINR1_FLT1F_Msk       (0xFUL << HRTIM_FLTINR1_FLT1F_Pos)       /*!< 0x00000078 */
+#define HRTIM_FLTINR1_FLT1F           HRTIM_FLTINR1_FLT1F_Msk                  /*!< Fault 1 filter */
+#define HRTIM_FLTINR1_FLT1F_0         (0x1UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000008 */
+#define HRTIM_FLTINR1_FLT1F_1         (0x2UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000010 */
+#define HRTIM_FLTINR1_FLT1F_2         (0x4UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000020 */
+#define HRTIM_FLTINR1_FLT1F_3         (0x8UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000040 */
+#define HRTIM_FLTINR1_FLT1LCK_Pos     (7U)
+#define HRTIM_FLTINR1_FLT1LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT1LCK_Pos)     /*!< 0x00000080 */
+#define HRTIM_FLTINR1_FLT1LCK         HRTIM_FLTINR1_FLT1LCK_Msk                /*!< Fault 1 lock */
+
+#define HRTIM_FLTINR1_FLT2E_Pos       (8U)
+#define HRTIM_FLTINR1_FLT2E_Msk       (0x1UL << HRTIM_FLTINR1_FLT2E_Pos)       /*!< 0x00000100 */
+#define HRTIM_FLTINR1_FLT2E           HRTIM_FLTINR1_FLT2E_Msk                  /*!< Fault 2 enable */
+#define HRTIM_FLTINR1_FLT2P_Pos       (9U)
+#define HRTIM_FLTINR1_FLT2P_Msk       (0x1UL << HRTIM_FLTINR1_FLT2P_Pos)       /*!< 0x00000200 */
+#define HRTIM_FLTINR1_FLT2P           HRTIM_FLTINR1_FLT2P_Msk                  /*!< Fault 2 polarity */
+#define HRTIM_FLTINR1_FLT2SRC_Pos     (10U)
+#define HRTIM_FLTINR1_FLT2SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT2SRC_Pos)     /*!< 0x00000400 */
+#define HRTIM_FLTINR1_FLT2SRC         HRTIM_FLTINR1_FLT2SRC_Msk                /*!< Fault 2 source */
+#define HRTIM_FLTINR1_FLT2F_Pos       (11U)
+#define HRTIM_FLTINR1_FLT2F_Msk       (0xFUL << HRTIM_FLTINR1_FLT2F_Pos)       /*!< 0x00007800 */
+#define HRTIM_FLTINR1_FLT2F           HRTIM_FLTINR1_FLT2F_Msk                  /*!< Fault 2 filter */
+#define HRTIM_FLTINR1_FLT2F_0         (0x1UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00000800 */
+#define HRTIM_FLTINR1_FLT2F_1         (0x2UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00001000 */
+#define HRTIM_FLTINR1_FLT2F_2         (0x4UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00002000 */
+#define HRTIM_FLTINR1_FLT2F_3         (0x8UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00004000 */
+#define HRTIM_FLTINR1_FLT2LCK_Pos     (15U)
+#define HRTIM_FLTINR1_FLT2LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT2LCK_Pos)     /*!< 0x00008000 */
+#define HRTIM_FLTINR1_FLT2LCK         HRTIM_FLTINR1_FLT2LCK_Msk                /*!< Fault 2 lock */
+
+#define HRTIM_FLTINR1_FLT3E_Pos       (16U)
+#define HRTIM_FLTINR1_FLT3E_Msk       (0x1UL << HRTIM_FLTINR1_FLT3E_Pos)       /*!< 0x00010000 */
+#define HRTIM_FLTINR1_FLT3E           HRTIM_FLTINR1_FLT3E_Msk                  /*!< Fault 3 enable */
+#define HRTIM_FLTINR1_FLT3P_Pos       (17U)
+#define HRTIM_FLTINR1_FLT3P_Msk       (0x1UL << HRTIM_FLTINR1_FLT3P_Pos)       /*!< 0x00020000 */
+#define HRTIM_FLTINR1_FLT3P           HRTIM_FLTINR1_FLT3P_Msk                  /*!< Fault 3 polarity */
+#define HRTIM_FLTINR1_FLT3SRC_Pos     (18U)
+#define HRTIM_FLTINR1_FLT3SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT3SRC_Pos)     /*!< 0x00040000 */
+#define HRTIM_FLTINR1_FLT3SRC         HRTIM_FLTINR1_FLT3SRC_Msk                /*!< Fault 3 source */
+#define HRTIM_FLTINR1_FLT3F_Pos       (19U)
+#define HRTIM_FLTINR1_FLT3F_Msk       (0xFUL << HRTIM_FLTINR1_FLT3F_Pos)       /*!< 0x00780000 */
+#define HRTIM_FLTINR1_FLT3F           HRTIM_FLTINR1_FLT3F_Msk                  /*!< Fault 3 filter */
+#define HRTIM_FLTINR1_FLT3F_0         (0x1UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00080000 */
+#define HRTIM_FLTINR1_FLT3F_1         (0x2UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00100000 */
+#define HRTIM_FLTINR1_FLT3F_2         (0x4UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00200000 */
+#define HRTIM_FLTINR1_FLT3F_3         (0x8UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00400000 */
+#define HRTIM_FLTINR1_FLT3LCK_Pos     (23U)
+#define HRTIM_FLTINR1_FLT3LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT3LCK_Pos)     /*!< 0x00800000 */
+#define HRTIM_FLTINR1_FLT3LCK         HRTIM_FLTINR1_FLT3LCK_Msk                /*!< Fault 3 lock */
+
+#define HRTIM_FLTINR1_FLT4E_Pos       (24U)
+#define HRTIM_FLTINR1_FLT4E_Msk       (0x1UL << HRTIM_FLTINR1_FLT4E_Pos)       /*!< 0x01000000 */
+#define HRTIM_FLTINR1_FLT4E           HRTIM_FLTINR1_FLT4E_Msk                  /*!< Fault 4 enable */
+#define HRTIM_FLTINR1_FLT4P_Pos       (25U)
+#define HRTIM_FLTINR1_FLT4P_Msk       (0x1UL << HRTIM_FLTINR1_FLT4P_Pos)       /*!< 0x02000000 */
+#define HRTIM_FLTINR1_FLT4P           HRTIM_FLTINR1_FLT4P_Msk                  /*!< Fault 4 polarity */
+#define HRTIM_FLTINR1_FLT4SRC_Pos     (26U)
+#define HRTIM_FLTINR1_FLT4SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT4SRC_Pos)     /*!< 0x04000000 */
+#define HRTIM_FLTINR1_FLT4SRC         HRTIM_FLTINR1_FLT4SRC_Msk                /*!< Fault 4 source */
+#define HRTIM_FLTINR1_FLT4F_Pos       (27U)
+#define HRTIM_FLTINR1_FLT4F_Msk       (0xFUL << HRTIM_FLTINR1_FLT4F_Pos)       /*!< 0x78000000 */
+#define HRTIM_FLTINR1_FLT4F           HRTIM_FLTINR1_FLT4F_Msk                  /*!< Fault 4 filter */
+#define HRTIM_FLTINR1_FLT4F_0         (0x1UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x08000000 */
+#define HRTIM_FLTINR1_FLT4F_1         (0x2UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x10000000 */
+#define HRTIM_FLTINR1_FLT4F_2         (0x4UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x20000000 */
+#define HRTIM_FLTINR1_FLT4F_3         (0x8UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x40000000 */
+#define HRTIM_FLTINR1_FLT4LCK_Pos     (31U)
+#define HRTIM_FLTINR1_FLT4LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT4LCK_Pos)     /*!< 0x80000000 */
+#define HRTIM_FLTINR1_FLT4LCK         HRTIM_FLTINR1_FLT4LCK_Msk                /*!< Fault 4 lock */
+
+/*******************  Bit definition for HRTIM_FLTINR2 register  ***************/
+#define HRTIM_FLTINR2_FLT5E_Pos       (0U)
+#define HRTIM_FLTINR2_FLT5E_Msk       (0x1UL << HRTIM_FLTINR2_FLT5E_Pos)       /*!< 0x00000001 */
+#define HRTIM_FLTINR2_FLT5E           HRTIM_FLTINR2_FLT5E_Msk                  /*!< Fault 5 enable */
+#define HRTIM_FLTINR2_FLT5P_Pos       (1U)
+#define HRTIM_FLTINR2_FLT5P_Msk       (0x1UL << HRTIM_FLTINR2_FLT5P_Pos)       /*!< 0x00000002 */
+#define HRTIM_FLTINR2_FLT5P           HRTIM_FLTINR2_FLT5P_Msk                  /*!< Fault 5 polarity */
+#define HRTIM_FLTINR2_FLT5SRC_Pos     (2U)
+#define HRTIM_FLTINR2_FLT5SRC_Msk     (0x1UL << HRTIM_FLTINR2_FLT5SRC_Pos)     /*!< 0x00000004 */
+#define HRTIM_FLTINR2_FLT5SRC         HRTIM_FLTINR2_FLT5SRC_Msk                /*!< Fault 5 source */
+#define HRTIM_FLTINR2_FLT5F_Pos       (3U)
+#define HRTIM_FLTINR2_FLT5F_Msk       (0xFUL << HRTIM_FLTINR2_FLT5F_Pos)       /*!< 0x00000078 */
+#define HRTIM_FLTINR2_FLT5F           HRTIM_FLTINR2_FLT5F_Msk                  /*!< Fault 5 filter */
+#define HRTIM_FLTINR2_FLT5F_0         (0x1UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000008 */
+#define HRTIM_FLTINR2_FLT5F_1         (0x2UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000010 */
+#define HRTIM_FLTINR2_FLT5F_2         (0x4UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000020 */
+#define HRTIM_FLTINR2_FLT5F_3         (0x8UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000040 */
+#define HRTIM_FLTINR2_FLT5LCK_Pos     (7U)
+#define HRTIM_FLTINR2_FLT5LCK_Msk     (0x1UL << HRTIM_FLTINR2_FLT5LCK_Pos)     /*!< 0x00000080 */
+#define HRTIM_FLTINR2_FLT5LCK         HRTIM_FLTINR2_FLT5LCK_Msk                /*!< Fault 5 lock */
+#define HRTIM_FLTINR2_FLTSD_Pos       (24U)
+#define HRTIM_FLTINR2_FLTSD_Msk       (0x3UL << HRTIM_FLTINR2_FLTSD_Pos)       /*!< 0x03000000 */
+#define HRTIM_FLTINR2_FLTSD           HRTIM_FLTINR2_FLTSD_Msk                  /*!< Fault sampling clock division */
+#define HRTIM_FLTINR2_FLTSD_0         (0x1UL << HRTIM_FLTINR2_FLTSD_Pos)        /*!< 0x01000000 */
+#define HRTIM_FLTINR2_FLTSD_1         (0x2UL << HRTIM_FLTINR2_FLTSD_Pos)        /*!< 0x02000000 */
+
+/*******************  Bit definition for HRTIM_BDMUPR register  ***************/
+#define HRTIM_BDMUPR_MCR_Pos          (0U)
+#define HRTIM_BDMUPR_MCR_Msk          (0x1UL << HRTIM_BDMUPR_MCR_Pos)          /*!< 0x00000001 */
+#define HRTIM_BDMUPR_MCR              HRTIM_BDMUPR_MCR_Msk                     /*!< MCR register update enable */
+#define HRTIM_BDMUPR_MICR_Pos         (1U)
+#define HRTIM_BDMUPR_MICR_Msk         (0x1UL << HRTIM_BDMUPR_MICR_Pos)         /*!< 0x00000002 */
+#define HRTIM_BDMUPR_MICR             HRTIM_BDMUPR_MICR_Msk                    /*!< MICR register update enable */
+#define HRTIM_BDMUPR_MDIER_Pos        (2U)
+#define HRTIM_BDMUPR_MDIER_Msk        (0x1UL << HRTIM_BDMUPR_MDIER_Pos)        /*!< 0x00000004 */
+#define HRTIM_BDMUPR_MDIER            HRTIM_BDMUPR_MDIER_Msk                   /*!< MDIER register update enable */
+#define HRTIM_BDMUPR_MCNT_Pos         (3U)
+#define HRTIM_BDMUPR_MCNT_Msk         (0x1UL << HRTIM_BDMUPR_MCNT_Pos)         /*!< 0x00000008 */
+#define HRTIM_BDMUPR_MCNT             HRTIM_BDMUPR_MCNT_Msk                    /*!< MCNT register update enable */
+#define HRTIM_BDMUPR_MPER_Pos         (4U)
+#define HRTIM_BDMUPR_MPER_Msk         (0x1UL << HRTIM_BDMUPR_MPER_Pos)         /*!< 0x00000010 */
+#define HRTIM_BDMUPR_MPER             HRTIM_BDMUPR_MPER_Msk                    /*!< MPER register update enable */
+#define HRTIM_BDMUPR_MREP_Pos         (5U)
+#define HRTIM_BDMUPR_MREP_Msk         (0x1UL << HRTIM_BDMUPR_MREP_Pos)         /*!< 0x00000020 */
+#define HRTIM_BDMUPR_MREP             HRTIM_BDMUPR_MREP_Msk                    /*!< MREP register update enable */
+#define HRTIM_BDMUPR_MCMP1_Pos        (6U)
+#define HRTIM_BDMUPR_MCMP1_Msk        (0x1UL << HRTIM_BDMUPR_MCMP1_Pos)        /*!< 0x00000040 */
+#define HRTIM_BDMUPR_MCMP1            HRTIM_BDMUPR_MCMP1_Msk                   /*!< MCMP1 register update enable */
+#define HRTIM_BDMUPR_MCMP2_Pos        (7U)
+#define HRTIM_BDMUPR_MCMP2_Msk        (0x1UL << HRTIM_BDMUPR_MCMP2_Pos)        /*!< 0x00000080 */
+#define HRTIM_BDMUPR_MCMP2            HRTIM_BDMUPR_MCMP2_Msk                   /*!< MCMP2 register update enable */
+#define HRTIM_BDMUPR_MCMP3_Pos        (8U)
+#define HRTIM_BDMUPR_MCMP3_Msk        (0x1UL << HRTIM_BDMUPR_MCMP3_Pos)        /*!< 0x00000100 */
+#define HRTIM_BDMUPR_MCMP3            HRTIM_BDMUPR_MCMP3_Msk                   /*!< MCMP3 register update enable */
+#define HRTIM_BDMUPR_MCMP4_Pos        (9U)
+#define HRTIM_BDMUPR_MCMP4_Msk        (0x1UL << HRTIM_BDMUPR_MCMP4_Pos)        /*!< 0x00000200 */
+#define HRTIM_BDMUPR_MCMP4            HRTIM_BDMUPR_MCMP4_Msk                   /*!< MPCMP4 register update enable */
+
+/*******************  Bit definition for HRTIM_BDTUPR register  ***************/
+#define HRTIM_BDTUPR_TIMCR_Pos        (0U)
+#define HRTIM_BDTUPR_TIMCR_Msk        (0x1UL << HRTIM_BDTUPR_TIMCR_Pos)        /*!< 0x00000001 */
+#define HRTIM_BDTUPR_TIMCR            HRTIM_BDTUPR_TIMCR_Msk                   /*!<  TIMCR register update enable */
+#define HRTIM_BDTUPR_TIMICR_Pos       (1U)
+#define HRTIM_BDTUPR_TIMICR_Msk       (0x1UL << HRTIM_BDTUPR_TIMICR_Pos)       /*!< 0x00000002 */
+#define HRTIM_BDTUPR_TIMICR           HRTIM_BDTUPR_TIMICR_Msk                  /*!<  TIMICR register update enable */
+#define HRTIM_BDTUPR_TIMDIER_Pos      (2U)
+#define HRTIM_BDTUPR_TIMDIER_Msk      (0x1UL << HRTIM_BDTUPR_TIMDIER_Pos)      /*!< 0x00000004 */
+#define HRTIM_BDTUPR_TIMDIER          HRTIM_BDTUPR_TIMDIER_Msk                 /*!<  TIMDIER register update enable */
+#define HRTIM_BDTUPR_TIMCNT_Pos       (3U)
+#define HRTIM_BDTUPR_TIMCNT_Msk       (0x1UL << HRTIM_BDTUPR_TIMCNT_Pos)       /*!< 0x00000008 */
+#define HRTIM_BDTUPR_TIMCNT           HRTIM_BDTUPR_TIMCNT_Msk                  /*!<  TIMCNT register update enable */
+#define HRTIM_BDTUPR_TIMPER_Pos       (4U)
+#define HRTIM_BDTUPR_TIMPER_Msk       (0x1UL << HRTIM_BDTUPR_TIMPER_Pos)       /*!< 0x00000010 */
+#define HRTIM_BDTUPR_TIMPER           HRTIM_BDTUPR_TIMPER_Msk                  /*!<  TIMPER register update enable */
+#define HRTIM_BDTUPR_TIMREP_Pos       (5U)
+#define HRTIM_BDTUPR_TIMREP_Msk       (0x1UL << HRTIM_BDTUPR_TIMREP_Pos)       /*!< 0x00000020 */
+#define HRTIM_BDTUPR_TIMREP           HRTIM_BDTUPR_TIMREP_Msk                  /*!<  TIMREP register update enable */
+#define HRTIM_BDTUPR_TIMCMP1_Pos      (6U)
+#define HRTIM_BDTUPR_TIMCMP1_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP1_Pos)      /*!< 0x00000040 */
+#define HRTIM_BDTUPR_TIMCMP1          HRTIM_BDTUPR_TIMCMP1_Msk                 /*!<  TIMCMP1 register update enable */
+#define HRTIM_BDTUPR_TIMCMP2_Pos      (7U)
+#define HRTIM_BDTUPR_TIMCMP2_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP2_Pos)      /*!< 0x00000080 */
+#define HRTIM_BDTUPR_TIMCMP2          HRTIM_BDTUPR_TIMCMP2_Msk                 /*!<  TIMCMP2 register update enable */
+#define HRTIM_BDTUPR_TIMCMP3_Pos      (8U)
+#define HRTIM_BDTUPR_TIMCMP3_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP3_Pos)      /*!< 0x00000100 */
+#define HRTIM_BDTUPR_TIMCMP3          HRTIM_BDTUPR_TIMCMP3_Msk                 /*!<  TIMCMP3 register update enable */
+#define HRTIM_BDTUPR_TIMCMP4_Pos      (9U)
+#define HRTIM_BDTUPR_TIMCMP4_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP4_Pos)      /*!< 0x00000200 */
+#define HRTIM_BDTUPR_TIMCMP4          HRTIM_BDTUPR_TIMCMP4_Msk                 /*!<  TIMCMP4 register update enable */
+#define HRTIM_BDTUPR_TIMDTR_Pos       (10U)
+#define HRTIM_BDTUPR_TIMDTR_Msk       (0x1UL << HRTIM_BDTUPR_TIMDTR_Pos)       /*!< 0x00000400 */
+#define HRTIM_BDTUPR_TIMDTR           HRTIM_BDTUPR_TIMDTR_Msk                  /*!<  TIMDTR register update enable */
+#define HRTIM_BDTUPR_TIMSET1R_Pos     (11U)
+#define HRTIM_BDTUPR_TIMSET1R_Msk     (0x1UL << HRTIM_BDTUPR_TIMSET1R_Pos)     /*!< 0x00000800 */
+#define HRTIM_BDTUPR_TIMSET1R         HRTIM_BDTUPR_TIMSET1R_Msk                /*!<  TIMSET1R register update enable */
+#define HRTIM_BDTUPR_TIMRST1R_Pos     (12U)
+#define HRTIM_BDTUPR_TIMRST1R_Msk     (0x1UL << HRTIM_BDTUPR_TIMRST1R_Pos)     /*!< 0x00001000 */
+#define HRTIM_BDTUPR_TIMRST1R         HRTIM_BDTUPR_TIMRST1R_Msk                /*!<  TIMRST1R register update enable */
+#define HRTIM_BDTUPR_TIMSET2R_Pos     (13U)
+#define HRTIM_BDTUPR_TIMSET2R_Msk     (0x1UL << HRTIM_BDTUPR_TIMSET2R_Pos)     /*!< 0x00002000 */
+#define HRTIM_BDTUPR_TIMSET2R         HRTIM_BDTUPR_TIMSET2R_Msk                /*!<  TIMSET2R register update enable */
+#define HRTIM_BDTUPR_TIMRST2R_Pos     (14U)
+#define HRTIM_BDTUPR_TIMRST2R_Msk     (0x1UL << HRTIM_BDTUPR_TIMRST2R_Pos)     /*!< 0x00004000 */
+#define HRTIM_BDTUPR_TIMRST2R         HRTIM_BDTUPR_TIMRST2R_Msk                /*!<  TIMRST2R register update enable */
+#define HRTIM_BDTUPR_TIMEEFR1_Pos     (15U)
+#define HRTIM_BDTUPR_TIMEEFR1_Msk     (0x1UL << HRTIM_BDTUPR_TIMEEFR1_Pos)     /*!< 0x00008000 */
+#define HRTIM_BDTUPR_TIMEEFR1         HRTIM_BDTUPR_TIMEEFR1_Msk                /*!<  TIMEEFR1 register update enable */
+#define HRTIM_BDTUPR_TIMEEFR2_Pos     (16U)
+#define HRTIM_BDTUPR_TIMEEFR2_Msk     (0x1UL << HRTIM_BDTUPR_TIMEEFR2_Pos)     /*!< 0x00010000 */
+#define HRTIM_BDTUPR_TIMEEFR2         HRTIM_BDTUPR_TIMEEFR2_Msk                /*!<  TIMEEFR2 register update enable */
+#define HRTIM_BDTUPR_TIMRSTR_Pos      (17U)
+#define HRTIM_BDTUPR_TIMRSTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMRSTR_Pos)      /*!< 0x00020000 */
+#define HRTIM_BDTUPR_TIMRSTR          HRTIM_BDTUPR_TIMRSTR_Msk                 /*!<  TIMRSTR register update enable */
+#define HRTIM_BDTUPR_TIMCHPR_Pos      (18U)
+#define HRTIM_BDTUPR_TIMCHPR_Msk      (0x1UL << HRTIM_BDTUPR_TIMCHPR_Pos)      /*!< 0x00040000 */
+#define HRTIM_BDTUPR_TIMCHPR          HRTIM_BDTUPR_TIMCHPR_Msk                 /*!<  TIMCHPR register update enable */
+#define HRTIM_BDTUPR_TIMOUTR_Pos      (19U)
+#define HRTIM_BDTUPR_TIMOUTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMOUTR_Pos)      /*!< 0x00080000 */
+#define HRTIM_BDTUPR_TIMOUTR          HRTIM_BDTUPR_TIMOUTR_Msk                 /*!<  TIMOUTR register update enable */
+#define HRTIM_BDTUPR_TIMFLTR_Pos      (20U)
+#define HRTIM_BDTUPR_TIMFLTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMFLTR_Pos)      /*!< 0x00100000 */
+#define HRTIM_BDTUPR_TIMFLTR          HRTIM_BDTUPR_TIMFLTR_Msk                 /*!<  TIMFLTR register update enable */
+
+/*******************  Bit definition for HRTIM_BDMADR register  ***************/
+#define HRTIM_BDMADR_BDMADR_Pos       (0U)
+#define HRTIM_BDMADR_BDMADR_Msk       (0xFFFFFFFFUL << HRTIM_BDMADR_BDMADR_Pos) /*!< 0xFFFFFFFF */
+#define HRTIM_BDMADR_BDMADR           HRTIM_BDMADR_BDMADR_Msk                  /*!<  Burst DMA Data register */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             RAM ECC monitoring                             */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for RAMECC_IER register  ******************/
+#define RAMECC_IER_GECCDEBWIE_Pos         (3U)
+#define RAMECC_IER_GECCDEBWIE_Msk         (0x1UL << RAMECC_IER_GECCDEBWIE_Pos)  /*!< 0x00000008 */
+#define RAMECC_IER_GECCDEBWIE             RAMECC_IER_GECCDEBWIE_Msk             /*!< Global ECC double error on byte write (BW) interrupt enable */
+#define RAMECC_IER_GECCDEIE_Pos           (2U)
+#define RAMECC_IER_GECCDEIE_Msk           (0x1UL << RAMECC_IER_GECCDEIE_Pos)    /*!< 0x00000004 */
+#define RAMECC_IER_GECCDEIE               RAMECC_IER_GECCDEIE_Msk               /*!< Global ECC double error interrupt enable */
+#define RAMECC_IER_GECCSEIE_Pos           (1U)
+#define RAMECC_IER_GECCSEIE_Msk           (0x1UL << RAMECC_IER_GECCSEIE_Pos)    /*!< 0x00000002 */
+#define RAMECC_IER_GECCSEIE               RAMECC_IER_GECCSEIE_Msk               /*!< Global ECC single error interrupt enable */
+#define RAMECC_IER_GIE_Pos                (0U)
+#define RAMECC_IER_GIE_Msk                (0x1UL << RAMECC_IER_GIE_Pos)         /*!< 0x00000001 */
+#define RAMECC_IER_GIE                    RAMECC_IER_GIE_Msk                    /*!< Global interrupt enable */
+
+/*******************  Bit definition for RAMECC_CR register  ******************/
+#define RAMECC_CR_ECCELEN_Pos             (5U)
+#define RAMECC_CR_ECCELEN_Msk             (0x1UL << RAMECC_CR_ECCELEN_Pos)      /*!< 0x00000020 */
+#define RAMECC_CR_ECCELEN                 RAMECC_CR_ECCELEN_Msk                 /*!< ECC error latching enable */
+#define RAMECC_CR_ECCDEBWIE_Pos           (4U)
+#define RAMECC_CR_ECCDEBWIE_Msk           (0x1UL << RAMECC_CR_ECCDEBWIE_Pos)    /*!< 0x00000010 */
+#define RAMECC_CR_ECCDEBWIE               RAMECC_CR_ECCDEBWIE_Msk               /*!< ECC double error on byte write (BW) interrupt enable */
+#define RAMECC_CR_ECCDEIE_Pos             (3U)
+#define RAMECC_CR_ECCDEIE_Msk             (0x1UL << RAMECC_CR_ECCDEIE_Pos)      /*!< 0x00000008 */
+#define RAMECC_CR_ECCDEIE                 RAMECC_CR_ECCDEIE_Msk                 /*!< ECC double error interrupt enable */
+#define RAMECC_CR_ECCSEIE_Pos             (2U)
+#define RAMECC_CR_ECCSEIE_Msk             (0x1UL << RAMECC_CR_ECCSEIE_Pos)      /*!< 0x00000004 */
+#define RAMECC_CR_ECCSEIE                 RAMECC_CR_ECCSEIE_Msk                 /*!< ECC single error interrupt enable */
+
+/*******************  Bit definition for RAMECC_SR register  ******************/
+#define RAMECC_SR_DEBWDF_Pos             (2U)
+#define RAMECC_SR_DEBWDF_Msk             (0x1UL << RAMECC_SR_DEBWDF_Pos)        /*!< 0x00000004 */
+#define RAMECC_SR_DEBWDF                 RAMECC_SR_DEBWDF_Msk                   /*!< ECC double error on byte write (BW) detected flag */
+#define RAMECC_SR_DEDF_Pos               (1U)
+#define RAMECC_SR_DEDF_Msk               (0x1UL << RAMECC_SR_DEDF_Pos)          /*!< 0x00000002 */
+#define RAMECC_SR_DEDF                   RAMECC_SR_DEDF_Msk                     /*!< ECC double error detected flag */
+#define RAMECC_SR_SEDCF_Pos              (0U)
+#define RAMECC_SR_SEDCF_Msk              (0x1UL << RAMECC_SR_SEDCF_Pos)         /*!< 0x00000001 */
+#define RAMECC_SR_SEDCF                  RAMECC_SR_SEDCF_Msk                    /*!< ECC single error detected and corrected flag */
+
+/******************  Bit definition for RAMECC_FAR register  ******************/
+#define RAMECC_FAR_FADD_Pos              (0U)
+#define RAMECC_FAR_FADD_Msk              (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos)  /*!< 0xFFFFFFFF */
+#define RAMECC_FAR_FADD                  RAMECC_FAR_FADD_Msk                    /*!< ECC error failing address */
+
+/******************  Bit definition for RAMECC_FDRL register  *****************/
+#define RAMECC_FAR_FDATAL_Pos            (0U)
+#define RAMECC_FAR_FDATAL_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAL_Pos)/*!< 0xFFFFFFFF */
+#define RAMECC_FAR_FDATAL                RAMECC_FAR_FDATAL_Msk                  /*!< ECC error failing address */
+
+/******************  Bit definition for RAMECC_FDRH register  *****************/
+#define RAMECC_FAR_FDATAH_Pos            (0U)
+#define RAMECC_FAR_FDATAH_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAH_Pos)/*!< 0xFFFFFFFF */
+#define RAMECC_FAR_FDATAH                RAMECC_FAR_FDATAH_Msk                  /* Failing data high (64-bit memory) */
+
+/*****************  Bit definition for RAMECC_FECR register  ******************/
+#define RAMECC_FECR_FEC_Pos              (0U)
+#define RAMECC_FECR_FEC_Msk              (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos)  /*!< 0xFFFFFFFF */
+#define RAMECC_FECR_FEC                  RAMECC_FECR_FEC_Msk                    /*!< Failing error code */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                MDIOS                                        */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for MDIOS_CR register  *******************/
+#define MDIOS_CR_EN_Pos                (0U)
+#define MDIOS_CR_EN_Msk                (0x1UL << MDIOS_CR_EN_Pos)              /*!< 0x00000001 */
+#define MDIOS_CR_EN                    MDIOS_CR_EN_Msk                         /*!<  MDIOS slave peripheral enable */
+#define MDIOS_CR_WRIE_Pos              (1U)
+#define MDIOS_CR_WRIE_Msk              (0x1UL << MDIOS_CR_WRIE_Pos)            /*!< 0x00000002 */
+#define MDIOS_CR_WRIE                  MDIOS_CR_WRIE_Msk                       /*!<  MDIOS slave register write interrupt enable. */
+#define MDIOS_CR_RDIE_Pos              (2U)
+#define MDIOS_CR_RDIE_Msk              (0x1UL << MDIOS_CR_RDIE_Pos)            /*!< 0x00000004 */
+#define MDIOS_CR_RDIE                  MDIOS_CR_RDIE_Msk                       /*!<  MDIOS slave register read interrupt enable. */
+#define MDIOS_CR_EIE_Pos               (3U)
+#define MDIOS_CR_EIE_Msk               (0x1UL << MDIOS_CR_EIE_Pos)             /*!< 0x00000008 */
+#define MDIOS_CR_EIE                   MDIOS_CR_EIE_Msk                        /*!<  MDIOS slave register error interrupt enable. */
+#define MDIOS_CR_DPC_Pos               (7U)
+#define MDIOS_CR_DPC_Msk               (0x1UL << MDIOS_CR_DPC_Pos)             /*!< 0x00000080 */
+#define MDIOS_CR_DPC                   MDIOS_CR_DPC_Msk                        /*!<  MDIOS slave disable preamble check. */
+#define MDIOS_CR_PORT_ADDRESS_Pos      (8U)
+#define MDIOS_CR_PORT_ADDRESS_Msk      (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos)   /*!< 0x00001F00 */
+#define MDIOS_CR_PORT_ADDRESS          MDIOS_CR_PORT_ADDRESS_Msk               /*!<  MDIOS slave port address mask. */
+#define MDIOS_CR_PORT_ADDRESS_0        (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000100 */
+#define MDIOS_CR_PORT_ADDRESS_1        (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000200 */
+#define MDIOS_CR_PORT_ADDRESS_2        (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000400 */
+#define MDIOS_CR_PORT_ADDRESS_3        (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000800 */
+#define MDIOS_CR_PORT_ADDRESS_4        (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00001000 */
+
+/********************  Bit definition for MDIOS_SR register  *******************/
+#define MDIOS_SR_PERF_Pos              (0U)
+#define MDIOS_SR_PERF_Msk              (0x1UL << MDIOS_SR_PERF_Pos)            /*!< 0x00000001 */
+#define MDIOS_SR_PERF                  MDIOS_SR_PERF_Msk                       /*!<  MDIOS slave turnaround error flag*/
+#define MDIOS_SR_SERF_Pos              (1U)
+#define MDIOS_SR_SERF_Msk              (0x1UL << MDIOS_SR_SERF_Pos)            /*!< 0x00000002 */
+#define MDIOS_SR_SERF                  MDIOS_SR_SERF_Msk                       /*!<  MDIOS slave start error flag */
+#define MDIOS_SR_TERF_Pos              (2U)
+#define MDIOS_SR_TERF_Msk              (0x1UL << MDIOS_SR_TERF_Pos)            /*!< 0x00000004 */
+#define MDIOS_SR_TERF                  MDIOS_SR_TERF_Msk                       /*!<  MDIOS slave preamble error flag */
+
+/********************  Bit definition for MDIOS_CLRFR register  *******************/
+#define MDIOS_SR_CPERF_Pos             (0U)
+#define MDIOS_SR_CPERF_Msk             (0x1UL << MDIOS_SR_CPERF_Pos)           /*!< 0x00000001 */
+#define MDIOS_SR_CPERF                 MDIOS_SR_CPERF_Msk                      /*!<  MDIOS slave Clear the turnaround error flag */
+#define MDIOS_SR_CSERF_Pos             (1U)
+#define MDIOS_SR_CSERF_Msk             (0x1UL << MDIOS_SR_CSERF_Pos)           /*!< 0x00000002 */
+#define MDIOS_SR_CSERF                 MDIOS_SR_CSERF_Msk                      /*!<  MDIOS slave Clear the start error flag */
+#define MDIOS_SR_CTERF_Pos             (2U)
+#define MDIOS_SR_CTERF_Msk             (0x1UL << MDIOS_SR_CTERF_Pos)           /*!< 0x00000004 */
+#define MDIOS_SR_CTERF                 MDIOS_SR_CTERF_Msk                      /*!<  MDIOS slave Clear the preamble error flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                       USB_OTG                              */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/
+#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)
+#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)
+#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
+#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */
+#define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)
+#define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */
+#define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)
+#define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
+#define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
+#define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)
+#define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)
+#define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
+#define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)
+#define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)
+#define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */
+#define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)
+#define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)
+#define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)
+#define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)
+#define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
+#define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_EHEN_Pos                 (12U)
+#define USB_OTG_GOTGCTL_EHEN_Msk                 (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
+#define USB_OTG_GOTGCTL_EHEN                     USB_OTG_GOTGCTL_EHEN_Msk      /*!< Embedded host enable */
+#define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)
+#define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
+#define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)
+#define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)
+#define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */
+#define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)
+#define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!< B-session valid */
+#define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)
+#define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
+#define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */
+
+/********************  Bit definition forUSB_OTG_HCFG register  ********************/
+
+#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)
+#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
+#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */
+#define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCFG_FSLSS_Pos                   (2U)
+#define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */
+
+/********************  Bit definition forUSB_OTG_DCFG register  ********************/
+
+#define USB_OTG_DCFG_DSPD_Pos                    (0U)
+#define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
+#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)
+#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD_Pos                     (4U)
+#define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */
+#define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
+
+#define USB_OTG_DCFG_PFIVL_Pos                   (11U)
+#define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
+
+#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)
+#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
+#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
+
+/********************  Bit definition forUSB_OTG_PCGCR register  ********************/
+#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)
+#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)
+#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)
+#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */
+
+/********************  Bit definition forUSB_OTG_GOTGINT register  ********************/
+#define USB_OTG_GOTGINT_SEDET_Pos                (2U)
+#define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */
+#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)
+#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */
+#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)
+#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)
+#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */
+#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)
+#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */
+#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)
+#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */
+
+/********************  Bit definition forUSB_OTG_DCTL register  ********************/
+#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)
+#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS_Pos                    (1U)
+#define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */
+#define USB_OTG_DCTL_GINSTS_Pos                  (2U)
+#define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */
+#define USB_OTG_DCTL_GONSTS_Pos                  (3U)
+#define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
+#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */
+
+#define USB_OTG_DCTL_TCTL_Pos                    (4U)
+#define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
+#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCTL_SGINAK_Pos                  (7U)
+#define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */
+#define USB_OTG_DCTL_CGINAK_Pos                  (8U)
+#define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */
+#define USB_OTG_DCTL_SGONAK_Pos                  (9U)
+#define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */
+#define USB_OTG_DCTL_CGONAK_Pos                  (10U)
+#define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */
+#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)
+#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
+
+/********************  Bit definition forUSB_OTG_HFIR register  ********************/
+#define USB_OTG_HFIR_FRIVL_Pos                   (0U)
+#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */
+
+/********************  Bit definition forUSB_OTG_HFNUM register  ********************/
+#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)
+#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */
+#define USB_OTG_HFNUM_FTREM_Pos                  (16U)
+#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */
+
+/********************  Bit definition forUSB_OTG_DSTS register  ********************/
+#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)
+#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */
+
+#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)
+#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
+#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
+#define USB_OTG_DSTS_EERR_Pos                    (3U)
+#define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
+#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */
+#define USB_OTG_DSTS_FNSOF_Pos                   (8U)
+#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
+#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */
+
+/********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/
+#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)
+#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
+#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */
+
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)
+#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
+#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
+#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
+#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
+#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
+#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)
+#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)
+#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)
+#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
+#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */
+
+/********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)
+#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
+#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
+#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
+#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
+#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)
+#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
+#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)
+#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
+#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)
+#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
+#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */
+
+#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)
+#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
+#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
+#define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
+#define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
+#define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)
+#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)
+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
+#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */
+#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)
+#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
+#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */
+#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)
+#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
+#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */
+#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)
+#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
+#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)
+#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
+#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */
+#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)
+#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
+#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)
+#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
+#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */
+#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)
+#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
+#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */
+#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)
+#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
+#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */
+#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)
+#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */
+
+/********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
+#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)
+#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
+#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */
+#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)
+#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
+#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */
+#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)
+#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
+#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)
+#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
+#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)
+#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
+#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */
+
+#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)
+#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
+#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
+#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
+#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)
+#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
+#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)
+#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
+#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */
+
+/********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/
+#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)
+#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */
+#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)
+#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */
+#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)
+#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
+#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)
+#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */
+#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)
+#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */
+#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)
+#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */
+#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)
+#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */
+
+/********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)
+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */
+
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)
+#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)
+#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
+
+/********************  Bit definition forUSB_OTG_HAINT register  ********************/
+#define USB_OTG_HAINT_HAINT_Pos                  (0U)
+#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */
+
+/********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/
+#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)
+#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)
+#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */
+#define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)
+#define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
+#define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk      /*!< OUT transaction AHB Error interrupt mask               */
+#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)
+#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */
+#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)
+#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)
+#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)
+#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */
+#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)
+#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */
+#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)
+#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */
+#define USB_OTG_DOEPMSK_BERRM_Pos                (12U)
+#define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask               */
+#define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)
+#define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask               */
+#define USB_OTG_DOEPMSK_NYETM_Pos                (14U)
+#define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk      /*!< NYET interrupt mask                */
+
+/********************  Bit definition forUSB_OTG_GINTSTS register  ********************/
+#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)
+#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
+#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */
+#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)
+#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */
+#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)
+#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */
+#define USB_OTG_GINTSTS_SOF_Pos                  (3U)
+#define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */
+#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)
+#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */
+#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)
+#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */
+#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)
+#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */
+#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)
+#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */
+#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)
+#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */
+#define USB_OTG_GINTSTS_USBRST_Pos               (12U)
+#define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */
+#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)
+#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */
+#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)
+#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */
+#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)
+#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */
+#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)
+#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */
+#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)
+#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */
+#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)
+#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)
+#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */
+#define USB_OTG_GINTSTS_RSTDET_Pos               (23U)
+#define USB_OTG_GINTSTS_RSTDET_Msk               (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
+#define USB_OTG_GINTSTS_RSTDET                   USB_OTG_GINTSTS_RSTDET_Msk    /*!< Reset detected interrupt                       */
+#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)
+#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */
+#define USB_OTG_GINTSTS_HCINT_Pos                (25U)
+#define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */
+#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)
+#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */
+#define USB_OTG_GINTSTS_LPMINT_Pos               (27U)
+#define USB_OTG_GINTSTS_LPMINT_Msk               (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt                                  */
+#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)
+#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */
+#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)
+#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */
+#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)
+#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)
+#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */
+
+/********************  Bit definition forUSB_OTG_GINTMSK register  ********************/
+#define USB_OTG_GINTMSK_MMISM_Pos                (1U)
+#define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */
+#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)
+#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */
+#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)
+#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */
+#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)
+#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */
+#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)
+#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)
+#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)
+#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */
+#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)
+#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */
+#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)
+#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */
+#define USB_OTG_GINTMSK_USBRST_Pos               (12U)
+#define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)
+#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */
+#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)
+#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */
+#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)
+#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */
+#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)
+#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
+#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */
+#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)
+#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */
+#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)
+#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)
+#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */
+#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)
+#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */
+#define USB_OTG_GINTMSK_RSTDEM_Pos               (23U)
+#define USB_OTG_GINTMSK_RSTDEM_Msk               (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */
+#define USB_OTG_GINTMSK_RSTDEM                   USB_OTG_GINTMSK_RSTDEM_Msk    /*!< Reset detected interrupt mask                      */
+#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)
+#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */
+#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)
+#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */
+#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)
+#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */
+#define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)
+#define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask                                  */
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)
+#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */
+#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)
+#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */
+#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)
+#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)
+#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */
+
+/********************  Bit definition forUSB_OTG_DAINT register  ********************/
+#define USB_OTG_DAINT_IEPINT_Pos                 (0U)
+#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */
+#define USB_OTG_DAINT_OEPINT_Pos                 (16U)
+#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */
+
+/********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/
+#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)
+#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */
+
+/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
+#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)
+#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */
+#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)
+#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)
+#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)
+#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/
+#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)
+#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)
+#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition for OTG register  ********************/
+
+#define USB_OTG_CHNUM_Pos                        (0U)
+#define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)  /*!< 0x0000000F */
+#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */
+#define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos                         (4U)
+#define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */
+
+#define USB_OTG_DPID_Pos                         (15U)
+#define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)   /*!< 0x00018000 */
+#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */
+#define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */
+#define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */
+
+#define USB_OTG_PKTSTS_Pos                       (17U)
+#define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */
+
+#define USB_OTG_EPNUM_Pos                        (0U)
+#define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)  /*!< 0x0000000F */
+#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */
+
+#define USB_OTG_FRMNUM_Pos                       (21U)
+#define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */
+
+/********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/
+#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)
+#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */
+
+/********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)
+#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */
+
+/********************  Bit definition for OTG register  ********************/
+#define USB_OTG_NPTXFSA_Pos                      (0U)
+#define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD_Pos                       (16U)
+#define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */
+#define USB_OTG_TX0FSA_Pos                       (0U)
+#define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */
+#define USB_OTG_TX0FD_Pos                        (16U)
+#define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */
+
+/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)
+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
+#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
+
+/********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
+#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
+#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)
+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
+#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)
+#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
+#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)
+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
+#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)
+#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
+#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */
+
+/********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/********************  Bit definition forUSB_OTG_DEACHINT register  ********************/
+#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)
+#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */
+#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)
+#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */
+
+/********************  Bit definition forUSB_OTG_GCCFG register  ********************/
+#define USB_OTG_GCCFG_DCDET_Pos                  (0U)
+#define USB_OTG_GCCFG_DCDET_Msk                  (0x1UL << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */
+#define USB_OTG_GCCFG_DCDET                      USB_OTG_GCCFG_DCDET_Msk       /*!< Data contact detection (DCD) status */
+#define USB_OTG_GCCFG_PDET_Pos                   (1U)
+#define USB_OTG_GCCFG_PDET_Msk                   (0x1UL << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_GCCFG_PDET                       USB_OTG_GCCFG_PDET_Msk        /*!< Primary detection (PD) status */
+#define USB_OTG_GCCFG_SDET_Pos                   (2U)
+#define USB_OTG_GCCFG_SDET_Msk                   (0x1UL << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GCCFG_SDET                       USB_OTG_GCCFG_SDET_Msk        /*!< Secondary detection (SD) status */
+#define USB_OTG_GCCFG_PS2DET_Pos                 (3U)
+#define USB_OTG_GCCFG_PS2DET_Msk                 (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */
+#define USB_OTG_GCCFG_PS2DET                     USB_OTG_GCCFG_PS2DET_Msk      /*!< DM pull-up detection status */
+#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)
+#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
+#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */
+#define USB_OTG_GCCFG_BCDEN_Pos                  (17U)
+#define USB_OTG_GCCFG_BCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_GCCFG_BCDEN                      USB_OTG_GCCFG_BCDEN_Msk       /*!< Battery charging detector (BCD) enable */
+#define USB_OTG_GCCFG_DCDEN_Pos                  (18U)
+#define USB_OTG_GCCFG_DCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_GCCFG_DCDEN                      USB_OTG_GCCFG_DCDEN_Msk       /*!< Data contact detection (DCD) mode enable*/
+#define USB_OTG_GCCFG_PDEN_Pos                   (19U)
+#define USB_OTG_GCCFG_PDEN_Msk                   (0x1UL << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_GCCFG_PDEN                       USB_OTG_GCCFG_PDEN_Msk        /*!< Primary detection (PD) mode enable*/
+#define USB_OTG_GCCFG_SDEN_Pos                   (20U)
+#define USB_OTG_GCCFG_SDEN_Msk                   (0x1UL << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_GCCFG_SDEN                       USB_OTG_GCCFG_SDEN_Msk        /*!< Secondary detection (SD) mode enable */
+#define USB_OTG_GCCFG_VBDEN_Pos                  (21U)
+#define USB_OTG_GCCFG_VBDEN_Msk                  (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk       /*!< Secondary detection (SD) mode enable */
+
+/********************  Bit definition forUSB_OTG_GPWRDN) register  ********************/
+#define USB_OTG_GPWRDN_ADPMEN_Pos                (0U)
+#define USB_OTG_GPWRDN_ADPMEN_Msk                (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */
+#define USB_OTG_GPWRDN_ADPMEN                    USB_OTG_GPWRDN_ADPMEN_Msk     /*!< ADP module enable */
+#define USB_OTG_GPWRDN_ADPIF_Pos                 (23U)
+#define USB_OTG_GPWRDN_ADPIF_Msk                 (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */
+#define USB_OTG_GPWRDN_ADPIF                     USB_OTG_GPWRDN_ADPIF_Msk      /*!< ADP Interrupt flag */
+
+/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
+
+/********************  Bit definition forUSB_OTG_CID register  ********************/
+#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)
+#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */
+
+/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/
+#define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)
+#define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
+#define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /*!< LPM support enable                                     */
+#define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)
+#define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
+#define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /*!< LPM Token acknowledge enable                           */
+#define USB_OTG_GLPMCFG_BESL_Pos                 (2U)
+#define USB_OTG_GLPMCFG_BESL_Msk                 (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
+#define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /*!< BESL value received with last ACKed LPM Token          */
+#define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)
+#define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
+#define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /*!< bRemoteWake value received with last ACKed LPM Token   */
+#define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)
+#define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /*!< L1 shallow sleep enable                                */
+#define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)
+#define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
+#define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /*!< BESL threshold                                         */
+#define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)
+#define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
+#define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /*!< L1 deep sleep enable                                   */
+#define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)
+#define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
+#define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /*!< LPM response                                           */
+#define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)
+#define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /*!< Port sleep status                                      */
+#define USB_OTG_GLPMCFG_L1RSMOK_Pos              (16U)
+#define USB_OTG_GLPMCFG_L1RSMOK_Msk              (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
+#define USB_OTG_GLPMCFG_L1RSMOK                  USB_OTG_GLPMCFG_L1RSMOK_Msk   /*!< Sleep State Resume OK                                  */
+#define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)
+#define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /*!< LPM Channel Index                                      */
+#define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)
+#define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
+#define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /*!< LPM retry count                                        */
+#define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)
+#define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /*!< Send LPM transaction                                   */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status                                 */
+#define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)
+#define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
+#define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /*!< Enable best effort service latency                     */
+
+/********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)
+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)
+#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)
+#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)
+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+
+/********************  Bit definition forUSB_OTG_HPRT register  ********************/
+#define USB_OTG_HPRT_PCSTS_Pos                   (0U)
+#define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */
+#define USB_OTG_HPRT_PCDET_Pos                   (1U)
+#define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */
+#define USB_OTG_HPRT_PENA_Pos                    (2U)
+#define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
+#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */
+#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)
+#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
+#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA_Pos                    (4U)
+#define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
+#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */
+#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)
+#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
+#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */
+#define USB_OTG_HPRT_PRES_Pos                    (6U)
+#define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
+#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume   */
+#define USB_OTG_HPRT_PSUSP_Pos                   (7U)
+#define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
+#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend  */
+#define USB_OTG_HPRT_PRST_Pos                    (8U)
+#define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
+#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset    */
+
+#define USB_OTG_HPRT_PLSTS_Pos                   (10U)
+#define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
+#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
+#define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_HPRT_PPWR_Pos                    (12U)
+#define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL_Pos                   (13U)
+#define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
+#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
+#define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
+#define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
+#define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_HPRT_PSPD_Pos                    (17U)
+#define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
+#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
+
+/********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)
+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)
+#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)
+#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)
+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)
+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)
+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
+
+/********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)
+#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)
+#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth */
+
+/********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/
+#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)
+#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)
+#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)
+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)
+#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)
+#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DIEPCTL_STALL_Pos                (21U)
+#define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)
+#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
+#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
+#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
+#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)
+#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)
+#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)
+#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)
+#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)
+#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable */
+
+/********************  Bit definition forUSB_OTG_HCCHAR register  ********************/
+#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)
+#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)
+#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
+#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
+#define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)
+#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)
+#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)
+#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
+
+#define USB_OTG_HCCHAR_MC_Pos                    (20U)
+#define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
+#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
+#define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
+
+#define USB_OTG_HCCHAR_DAD_Pos                   (22U)
+#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
+#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
+#define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
+#define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
+#define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
+#define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
+#define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
+#define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
+#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)
+#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)
+#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)
+#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */
+
+/********************  Bit definition forUSB_OTG_HCSPLT register  ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)
+#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
+#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
+
+#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)
+#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
+#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
+
+#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)
+#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
+#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)
+#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
+#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)
+#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */
+
+/********************  Bit definition forUSB_OTG_HCINT register  ********************/
+#define USB_OTG_HCINT_XFRC_Pos                   (0U)
+#define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH_Pos                    (1U)
+#define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR_Pos                 (2U)
+#define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */
+#define USB_OTG_HCINT_STALL_Pos                  (3U)
+#define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK_Pos                    (4U)
+#define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK_Pos                    (5U)
+#define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET_Pos                   (6U)
+#define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR_Pos                  (7U)
+#define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR_Pos                  (8U)
+#define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR_Pos                  (9U)
+#define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR_Pos                  (10U)
+#define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */
+
+/********************  Bit definition forUSB_OTG_DIEPINT register  ********************/
+#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)
+#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)
+#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_AHBERR_Pos               (2U)
+#define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */
+#define USB_OTG_DIEPINT_TOC_Pos                  (3U)
+#define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)
+#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNM_Pos               (5U)
+#define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */
+#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)
+#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)
+#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
+#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA_Pos                  (9U)
+#define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)
+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR_Pos                 (12U)
+#define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK_Pos                  (13U)
+#define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */
+
+/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/
+#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)
+#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)
+#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)
+#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)
+#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)
+#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)
+#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET_Pos                (6U)
+#define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)
+#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)
+#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)
+#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)
+#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */
+
+/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)
+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)
+#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */
+/********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)
+#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)
+#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)
+#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)
+#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
+#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/
+#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)
+#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */
+
+/********************  Bit definition forUSB_OTG_HCDMA register  ********************/
+#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)
+#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */
+
+/********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)
+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
+
+/********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)
+#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)
+#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */
+
+/********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)
+#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)
+#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)
+#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)
+#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)
+#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)
+#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
+#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL_Pos                (21U)
+#define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)
+#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)
+#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)
+#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)
+#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */
+
+/********************  Bit definition forUSB_OTG_DOEPINT register  ********************/
+#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)
+#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)
+#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_AHBERR_Pos               (2U)
+#define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */
+#define USB_OTG_DOEPINT_STUP_Pos                 (3U)
+#define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)
+#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)
+#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< OUT Status Phase Received interrupt */
+#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)
+#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)
+#define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */
+#define USB_OTG_DOEPINT_BERR_Pos                 (12U)
+#define USB_OTG_DOEPINT_BERR_Msk                 (0x1UL << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPINT_BERR                      USB_OTG_DOEPINT_BERR_Msk   /*!< Babble error interrupt */
+#define USB_OTG_DOEPINT_NAK_Pos                  (13U)
+#define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */
+#define USB_OTG_DOEPINT_NYET_Pos                 (14U)
+#define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */
+#define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)
+#define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */
+
+/********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)
+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for PCGCCTL register  ********************/
+#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)
+#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)
+#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)
+#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+                                       ((INSTANCE) == ADC2) || \
+                                       ((INSTANCE) == ADC3))
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON) ||\
+                                          ((INSTANCE) == ADC3_COMMON))
+
+/******************************** COMP Instances ******************************/
+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
+                                       ((INSTANCE) == COMP2))
+
+#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
+/******************** COMP Instances with window mode capability **************/
+#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
+
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
+/******************************* DCMI Instances *******************************/
+#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
+
+/******************************* DELAYBLOCK Instances *******************************/
+#define IS_DLYB_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DLYB_SDMMC1) || \
+                                         ((INSTANCE) == DLYB_SDMMC2) || \
+                                         ((INSTANCE) == DLYB_QUADSPI))
+/****************************** DFSDM Instances *******************************/
+#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
+                                               ((INSTANCE) == DFSDM1_Filter1) || \
+                                               ((INSTANCE) == DFSDM1_Filter2) || \
+                                               ((INSTANCE) == DFSDM1_Filter3))
+
+#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
+                                                 ((INSTANCE) == DFSDM1_Channel1) || \
+                                                 ((INSTANCE) == DFSDM1_Channel2) || \
+                                                 ((INSTANCE) == DFSDM1_Channel3) || \
+                                                 ((INSTANCE) == DFSDM1_Channel4) || \
+                                                 ((INSTANCE) == DFSDM1_Channel5) || \
+                                                 ((INSTANCE) == DFSDM1_Channel6) || \
+                                                 ((INSTANCE) == DFSDM1_Channel7))
+/****************************** RAMECC Instances ******************************/
+#define IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMECC1_Monitor1)   || \
+                                                  ((INSTANCE) == RAMECC1_Monitor2)   || \
+                                                  ((INSTANCE) == RAMECC1_Monitor3)   || \
+                                                  ((INSTANCE) == RAMECC1_Monitor4)   || \
+                                                  ((INSTANCE) == RAMECC1_Monitor5)   || \
+                                                  ((INSTANCE) == RAMECC2_Monitor1)   || \
+                                                  ((INSTANCE) == RAMECC2_Monitor2)   || \
+                                                  ((INSTANCE) == RAMECC2_Monitor3)   || \
+                                                  ((INSTANCE) == RAMECC2_Monitor4)   || \
+                                                  ((INSTANCE) == RAMECC2_Monitor5)   || \
+                                                  ((INSTANCE) == RAMECC3_Monitor1)   || \
+                                                  ((INSTANCE) == RAMECC3_Monitor2))
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \
+                                       ((INSTANCE) == DMA1_Stream1)   || \
+                                       ((INSTANCE) == DMA1_Stream2)   || \
+                                       ((INSTANCE) == DMA1_Stream3)   || \
+                                       ((INSTANCE) == DMA1_Stream4)   || \
+                                       ((INSTANCE) == DMA1_Stream5)   || \
+                                       ((INSTANCE) == DMA1_Stream6)   || \
+                                       ((INSTANCE) == DMA1_Stream7)   || \
+                                       ((INSTANCE) == DMA2_Stream0)   || \
+                                       ((INSTANCE) == DMA2_Stream1)   || \
+                                       ((INSTANCE) == DMA2_Stream2)   || \
+                                       ((INSTANCE) == DMA2_Stream3)   || \
+                                       ((INSTANCE) == DMA2_Stream4)   || \
+                                       ((INSTANCE) == DMA2_Stream5)   || \
+                                       ((INSTANCE) == DMA2_Stream6)   || \
+                                       ((INSTANCE) == DMA2_Stream7)   || \
+                                       ((INSTANCE) == BDMA_Channel0) || \
+                                       ((INSTANCE) == BDMA_Channel1) || \
+                                       ((INSTANCE) == BDMA_Channel2) || \
+                                       ((INSTANCE) == BDMA_Channel3) || \
+                                       ((INSTANCE) == BDMA_Channel4) || \
+                                       ((INSTANCE) == BDMA_Channel5) || \
+                                       ((INSTANCE) == BDMA_Channel6) || \
+                                       ((INSTANCE) == BDMA_Channel7))
+
+/****************************** BDMA CHANNEL Instances ***************************/
+#define IS_BDMA_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == BDMA_Channel0) || \
+                                            ((INSTANCE) == BDMA_Channel1) || \
+                                            ((INSTANCE) == BDMA_Channel2) || \
+                                            ((INSTANCE) == BDMA_Channel3) || \
+                                            ((INSTANCE) == BDMA_Channel4) || \
+                                            ((INSTANCE) == BDMA_Channel5) || \
+                                            ((INSTANCE) == BDMA_Channel6) || \
+                                            ((INSTANCE) == BDMA_Channel7))
+
+/****************************** DMA DMAMUX ALL Instances ***************************/
+#define IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)    || \
+                                               ((INSTANCE) == DMA1_Stream1)    || \
+                                               ((INSTANCE) == DMA1_Stream2)    || \
+                                               ((INSTANCE) == DMA1_Stream3)    || \
+                                               ((INSTANCE) == DMA1_Stream4)    || \
+                                               ((INSTANCE) == DMA1_Stream5)    || \
+                                               ((INSTANCE) == DMA1_Stream6)    || \
+                                               ((INSTANCE) == DMA1_Stream7)    || \
+                                               ((INSTANCE) == DMA2_Stream0)    || \
+                                               ((INSTANCE) == DMA2_Stream1)    || \
+                                               ((INSTANCE) == DMA2_Stream2)    || \
+                                               ((INSTANCE) == DMA2_Stream3)    || \
+                                               ((INSTANCE) == DMA2_Stream4)    || \
+                                               ((INSTANCE) == DMA2_Stream5)    || \
+                                               ((INSTANCE) == DMA2_Stream6)    || \
+                                               ((INSTANCE) == DMA2_Stream7)    || \
+                                               ((INSTANCE) == BDMA_Channel0)   || \
+                                               ((INSTANCE) == BDMA_Channel1)   || \
+                                               ((INSTANCE) == BDMA_Channel2)   || \
+                                               ((INSTANCE) == BDMA_Channel3)   || \
+                                               ((INSTANCE) == BDMA_Channel4)   || \
+                                               ((INSTANCE) == BDMA_Channel5)   || \
+                                               ((INSTANCE) == BDMA_Channel6)   || \
+                                               ((INSTANCE) == BDMA_Channel7))
+
+/****************************** BDMA DMAMUX Instances ***************************/
+#define IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == BDMA_Channel0) || \
+                                                    ((INSTANCE) == BDMA_Channel1) || \
+                                                    ((INSTANCE) == BDMA_Channel2) || \
+                                                    ((INSTANCE) == BDMA_Channel3) || \
+                                                    ((INSTANCE) == BDMA_Channel4) || \
+                                                    ((INSTANCE) == BDMA_Channel5) || \
+                                                    ((INSTANCE) == BDMA_Channel6) || \
+                                                    ((INSTANCE) == BDMA_Channel7))
+
+/****************************** DMA STREAM Instances ***************************/
+#define IS_DMA_STREAM_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \
+                                          ((INSTANCE) == DMA1_Stream1)   || \
+                                          ((INSTANCE) == DMA1_Stream2)   || \
+                                          ((INSTANCE) == DMA1_Stream3)   || \
+                                          ((INSTANCE) == DMA1_Stream4)   || \
+                                          ((INSTANCE) == DMA1_Stream5)   || \
+                                          ((INSTANCE) == DMA1_Stream6)   || \
+                                          ((INSTANCE) == DMA1_Stream7)   || \
+                                          ((INSTANCE) == DMA2_Stream0)   || \
+                                          ((INSTANCE) == DMA2_Stream1)   || \
+                                          ((INSTANCE) == DMA2_Stream2)   || \
+                                          ((INSTANCE) == DMA2_Stream3)   || \
+                                          ((INSTANCE) == DMA2_Stream4)   || \
+                                          ((INSTANCE) == DMA2_Stream5)   || \
+                                          ((INSTANCE) == DMA2_Stream6)   || \
+                                          ((INSTANCE) == DMA2_Stream7))
+
+/****************************** DMA DMAMUX Instances ***************************/
+#define IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)   || \
+                                                  ((INSTANCE) == DMA1_Stream1)   || \
+                                                  ((INSTANCE) == DMA1_Stream2)   || \
+                                                  ((INSTANCE) == DMA1_Stream3)   || \
+                                                  ((INSTANCE) == DMA1_Stream4)   || \
+                                                  ((INSTANCE) == DMA1_Stream5)   || \
+                                                  ((INSTANCE) == DMA1_Stream6)   || \
+                                                  ((INSTANCE) == DMA1_Stream7)   || \
+                                                  ((INSTANCE) == DMA2_Stream0)   || \
+                                                  ((INSTANCE) == DMA2_Stream1)   || \
+                                                  ((INSTANCE) == DMA2_Stream2)   || \
+                                                  ((INSTANCE) == DMA2_Stream3)   || \
+                                                  ((INSTANCE) == DMA2_Stream4)   || \
+                                                  ((INSTANCE) == DMA2_Stream5)   || \
+                                                  ((INSTANCE) == DMA2_Stream6)   || \
+                                                  ((INSTANCE) == DMA2_Stream7))
+
+/******************************** DMA Request Generator Instances **************/
+#define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator1) || \
+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator2) || \
+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator3) || \
+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator4) || \
+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator5) || \
+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator6) || \
+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator7) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator0) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator1) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator2) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator3) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator4) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator5) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator6) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator7))
+
+/******************************* DMA2D Instances *******************************/
+#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
+
+/******************************** MDMA Request Generator Instances **************/
+#define IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDMA_Channel0)  || \
+                                               ((INSTANCE) == MDMA_Channel1)  || \
+                                               ((INSTANCE) == MDMA_Channel2)  || \
+                                               ((INSTANCE) == MDMA_Channel3)  || \
+                                               ((INSTANCE) == MDMA_Channel4)  || \
+                                               ((INSTANCE) == MDMA_Channel5)  || \
+                                               ((INSTANCE) == MDMA_Channel6)  || \
+                                               ((INSTANCE) == MDMA_Channel7)  || \
+                                               ((INSTANCE) == MDMA_Channel8)  || \
+                                               ((INSTANCE) == MDMA_Channel9)  || \
+                                               ((INSTANCE) == MDMA_Channel10) || \
+                                               ((INSTANCE) == MDMA_Channel11) || \
+                                               ((INSTANCE) == MDMA_Channel12) || \
+                                               ((INSTANCE) == MDMA_Channel13) || \
+                                               ((INSTANCE) == MDMA_Channel14) || \
+                                               ((INSTANCE) == MDMA_Channel15))
+
+/******************************* QUADSPI Instances *******************************/
+#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
+
+/******************************* FDCAN Instances ******************************/
+#define IS_FDCAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == FDCAN1) || \
+                                             ((__INSTANCE__) == FDCAN2))
+
+#define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1)
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+                                        ((INSTANCE) == GPIOB) || \
+                                        ((INSTANCE) == GPIOC) || \
+                                        ((INSTANCE) == GPIOD) || \
+                                        ((INSTANCE) == GPIOE) || \
+                                        ((INSTANCE) == GPIOF) || \
+                                        ((INSTANCE) == GPIOG) || \
+                                        ((INSTANCE) == GPIOH) || \
+                                        ((INSTANCE) == GPIOI) || \
+                                        ((INSTANCE) == GPIOJ) || \
+                                        ((INSTANCE) == GPIOK))
+
+/******************************* GPIO AF Instances ****************************/
+#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/**************************** GPIO Lock Instances *****************************/
+/* On H7, all GPIO Bank support the Lock mechanism */
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/******************************** HSEM Instances *******************************/
+#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)
+#define HSEM_CPU1_COREID         (0x00000003U) /* Semaphore Core CM7 ID */
+#define HSEM_CR_COREID_CPU1      (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
+#define HSEM_CR_COREID_CURRENT   (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
+
+#define HSEM_SEMID_MIN     (0U)       /* HSEM ID Min*/
+#define HSEM_SEMID_MAX     (31U)      /* HSEM ID Max */
+
+#define HSEM_PROCESSID_MIN (0U)       /* HSEM Process ID Min */
+#define HSEM_PROCESSID_MAX (255U)     /* HSEM Process ID Max */
+
+#define HSEM_CLEAR_KEY_MIN (0U)       /* HSEM clear Key Min value */
+#define HSEM_CLEAR_KEY_MAX (0xFFFFU)  /* HSEM clear Key Max value */
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+                                       ((INSTANCE) == I2C2) || \
+                                       ((INSTANCE) == I2C3) || \
+                                       ((INSTANCE) == I2C4))
+/************** I2C Instances : wakeup capability from stop modes *************/
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
+
+/****************************** SMBUS Instances *******************************/
+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+                                         ((INSTANCE) == I2C2) || \
+                                         ((INSTANCE) == I2C3) || \
+                                         ((INSTANCE) == I2C4))
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE)   (((INSTANCE) == SPI1) || \
+                                         ((INSTANCE) == SPI2) || \
+                                         ((INSTANCE) == SPI3))
+
+/****************************** LTDC Instances ********************************/
+#define IS_LTDC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == LTDC)
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
+
+/****************************** SDMMC Instances *********************************/
+#define IS_SDMMC_ALL_INSTANCE(_INSTANCE_) (((_INSTANCE_) == SDMMC1) || \
+                                           ((_INSTANCE_) == SDMMC2))
+
+/******************************** SMBUS Instances *****************************/
+#define IS_SMBUS_INSTANCE(INSTANCE)  ((INSTANCE) == I2C1)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+                                       ((INSTANCE) == SPI2) || \
+                                       ((INSTANCE) == SPI3) || \
+                                       ((INSTANCE) == SPI4) || \
+                                       ((INSTANCE) == SPI5) || \
+                                       ((INSTANCE) == SPI6))
+
+#define IS_SPI_HIGHEND_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+                                           ((INSTANCE) == SPI2) || \
+                                           ((INSTANCE) == SPI3))
+
+/******************************** SWPMI Instances *****************************/
+#define IS_SWPMI_INSTANCE(INSTANCE)  ((INSTANCE) == SWPMI1)
+
+/****************** LPTIM Instances : All supported instances *****************/
+#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \
+                                         ((INSTANCE) == LPTIM2) || \
+                                         ((INSTANCE) == LPTIM3) || \
+                                         ((INSTANCE) == LPTIM4) || \
+                                         ((INSTANCE) == LPTIM5))
+
+/****************** LPTIM Instances : supporting encoder interface **************/
+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \
+                                                           ((INSTANCE) == LPTIM2))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM6)   || \
+                                         ((INSTANCE) == TIM7)   || \
+                                         ((INSTANCE) == TIM8)   || \
+                                         ((INSTANCE) == TIM12)  || \
+                                         ((INSTANCE) == TIM13)  || \
+                                         ((INSTANCE) == TIM14)  || \
+                                         ((INSTANCE) == TIM15)  || \
+                                         ((INSTANCE) == TIM16)  || \
+                                         ((INSTANCE) == TIM17))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8)   || \
+                                         ((INSTANCE) == TIM12)  || \
+                                         ((INSTANCE) == TIM13)  || \
+                                         ((INSTANCE) == TIM14)  || \
+                                         ((INSTANCE) == TIM15)  || \
+                                         ((INSTANCE) == TIM16)  || \
+                                         ((INSTANCE) == TIM17))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8)   || \
+                                         ((INSTANCE) == TIM12)  || \
+                                         ((INSTANCE) == TIM15))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 5 capture/compare channels *************/
+#define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM8))
+/************ TIM Instances : at least 6 capture/compare channels *************/
+#define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
+                                                ((__INSTANCE__) == TIM8))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8)   || \
+                                         ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \
+                                           ((INSTANCE) == TIM2)   || \
+                                           ((INSTANCE) == TIM3)   || \
+                                           ((INSTANCE) == TIM4)   || \
+                                           ((INSTANCE) == TIM5)   || \
+                                           ((INSTANCE) == TIM6)   || \
+                                           ((INSTANCE) == TIM7)   || \
+                                           ((INSTANCE) == TIM8)   || \
+                                           ((INSTANCE) == TIM15)  || \
+                                           ((INSTANCE) == TIM16)  || \
+                                           ((INSTANCE) == TIM17))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM5)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15)  || \
+                                            ((INSTANCE) == TIM16)  || \
+                                            ((INSTANCE) == TIM17))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM5)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM5)   || \
+                                            ((INSTANCE) == TIM8))
+
+/*************** TIM Instances : external trigger reamp input available *******/
+#define IS_TIM_ETR_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \
+                                           ((INSTANCE) == TIM2)   || \
+                                           ((INSTANCE) == TIM3)   || \
+                                           ((INSTANCE) == TIM4)   || \
+                                           ((INSTANCE) == TIM5)   || \
+                                           ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
+                                          ((INSTANCE) == TIM2)  || \
+                                          ((INSTANCE) == TIM3)  || \
+                                          ((INSTANCE) == TIM5)  || \
+                                          ((INSTANCE) == TIM8)  || \
+                                          ((INSTANCE) == TIM16) || \
+                                          ((INSTANCE) == TIM17))
+
+/*************** TIM Instances : external trigger reamp input available *******/
+#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \
+                                              ((INSTANCE) == TIM2)   || \
+                                              ((INSTANCE) == TIM3)   || \
+                                              ((INSTANCE) == TIM5)   || \
+                                              ((INSTANCE) == TIM8))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM5)   || \
+                                            ((INSTANCE) == TIM6)   || \
+                                            ((INSTANCE) == TIM7)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15))
+
+/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                           ((INSTANCE) == TIM2)   || \
+                                           ((INSTANCE) == TIM3)   || \
+                                           ((INSTANCE) == TIM4)   || \
+                                           ((INSTANCE) == TIM5)   || \
+                                           ((INSTANCE) == TIM8)   || \
+                                           ((INSTANCE) == TIM12))
+
+/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
+#define IS_TIM_TRGO2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                           ((INSTANCE) == TIM8))
+
+/****** TIM Instances : TISEL available (TIMx_TISEL available )*********/
+#define IS_TIM_TISEL_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)   || \
+                                          ((INSTANCE) == TIM2)   || \
+                                          ((INSTANCE) == TIM3)   || \
+                                          ((INSTANCE) == TIM4)   || \
+                                          ((INSTANCE) == TIM5)   || \
+                                          ((INSTANCE) == TIM8)   || \
+                                          ((INSTANCE) == TIM15)  || \
+                                          ((INSTANCE) == TIM16)  || \
+                                          ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting commutation event *************/
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)    || \
+                                                     ((INSTANCE) == TIM8)    || \
+                                                     ((INSTANCE) == TIM15)   || \
+                                                     ((INSTANCE) == TIM16)   || \
+                                                     ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1)  || \
+                                                      ((__INSTANCE__) == TIM2)      || \
+                                                      ((__INSTANCE__) == TIM3)      || \
+                                                      ((__INSTANCE__) == TIM4)      || \
+                                                      ((__INSTANCE__) == TIM5)      || \
+                                                      ((__INSTANCE__) == TIM8))
+
+/****** TIM Instances : TIM_CCR5_GC5C available (TIMx_CCR5.GC5C available )*********/
+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                                       ((INSTANCE) == TIM8))
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+    ((((INSTANCE) == TIM1) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4) ||          \
+      ((CHANNEL) == TIM_CHANNEL_5) ||          \
+      ((CHANNEL) == TIM_CHANNEL_6)))           \
+     ||                                        \
+     (((INSTANCE) == TIM2) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+  ||                                           \
+      (((INSTANCE) == TIM3) &&                 \
+      (((CHANNEL) == TIM_CHANNEL_1)||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+  ||                                           \
+      (((INSTANCE) == TIM4) &&                 \
+      (((CHANNEL) == TIM_CHANNEL_1) ||         \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+  ||                                           \
+      (((INSTANCE) == TIM5) &&                 \
+      (((CHANNEL) == TIM_CHANNEL_1) ||         \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+  ||                                           \
+      (((INSTANCE) == TIM8) &&                 \
+      (((CHANNEL) == TIM_CHANNEL_1) ||         \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4) ||          \
+      ((CHANNEL) == TIM_CHANNEL_5) ||          \
+      ((CHANNEL) == TIM_CHANNEL_6)))           \
+  ||                                           \
+     (((INSTANCE) == TIM12) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2)))           \
+  ||                                           \
+     (((INSTANCE) == TIM13) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+  ||                                           \
+     (((INSTANCE) == TIM14) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+  ||                                           \
+     (((INSTANCE) == TIM15) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+     ((CHANNEL) == TIM_CHANNEL_2)))            \
+  ||                                           \
+     (((INSTANCE) == TIM16) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+  ||                                           \
+     (((INSTANCE) == TIM17) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1))))
+
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
+      (((INSTANCE) == TIM1)    || \
+      ((INSTANCE) == TIM8)     || \
+       ((INSTANCE) == TIM15)   || \
+       ((INSTANCE) == TIM16)   || \
+       ((INSTANCE) == TIM17))
+
+/************** TIM Instances : supporting Break source selection *************/
+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                               ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting complementary output(s) ********/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+   ((((INSTANCE) == TIM1) &&                    \
+     (((CHANNEL) == TIM_CHANNEL_1) ||           \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3)))            \
+ ||                                             \
+      (((INSTANCE) == TIM8) &&                  \
+      (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3)))            \
+    ||                                          \
+    (((INSTANCE) == TIM15) &&                   \
+      ((CHANNEL) == TIM_CHANNEL_1))             \
+    ||                                          \
+    (((INSTANCE) == TIM16) &&                   \
+     ((CHANNEL) == TIM_CHANNEL_1))              \
+    ||                                          \
+    (((INSTANCE) == TIM17) &&                   \
+     ((CHANNEL) == TIM_CHANNEL_1)))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM5)    || \
+   ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM15)   || \
+   ((INSTANCE) == TIM16)   || \
+   ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting synchronization ****************/
+#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
+    (((__INSTANCE__) == TIM1)    || \
+     ((__INSTANCE__) == TIM2)    || \
+     ((__INSTANCE__) == TIM3)    || \
+     ((__INSTANCE__) == TIM4)    || \
+     ((__INSTANCE__) == TIM5)    || \
+     ((__INSTANCE__) == TIM6)    || \
+     ((__INSTANCE__) == TIM8)    || \
+     ((__INSTANCE__) == TIM12)   || \
+     ((__INSTANCE__) == TIM15))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM5)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM15)   || \
+   ((INSTANCE) == TIM16)   || \
+   ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting external clock mode 1 for ETRF input */
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM5)    || \
+   ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting external clock mode 2 **********/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1)     || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM5)    || \
+   ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM5)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM5)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3))
+
+/****************** TIM Instances : TIM_32B_COUNTER ***************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : TIM_BKIN2 ***************************/
+#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting Hall sensor interface **********/
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1)  || \
+                                                             ((__INSTANCE__) == TIM2)  || \
+                                                             ((__INSTANCE__) == TIM3)  || \
+                                                             ((__INSTANCE__) == TIM4)  || \
+                                                             ((__INSTANCE__) == TIM5)  || \
+                                                             ((__INSTANCE__) == TIM15) || \
+                                                             ((__INSTANCE__) == TIM8))
+
+/****************************** HRTIM Instances *******************************/
+#define IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                     ((INSTANCE) == USART2) || \
+                                     ((INSTANCE) == USART3) || \
+                                     ((INSTANCE) == USART6))
+
+/******************** USART Instances : SPI slave mode ************************/
+#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                              ((INSTANCE) == USART2) || \
+                                              ((INSTANCE) == USART3) || \
+                                              ((INSTANCE) == USART6))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                    ((INSTANCE) == USART2) || \
+                                    ((INSTANCE) == USART3) || \
+                                    ((INSTANCE) == UART4)  || \
+                                    ((INSTANCE) == UART5)  || \
+                                    ((INSTANCE) == USART6) || \
+                                    ((INSTANCE) == UART7)  || \
+                                    ((INSTANCE) == UART8))
+
+/******************** UART Instances : FIFO mode.******************************/
+#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                         ((INSTANCE) == USART2) || \
+                                         ((INSTANCE) == USART3) || \
+                                         ((INSTANCE) == UART4)  || \
+                                         ((INSTANCE) == UART5)  || \
+                                         ((INSTANCE) == USART6) || \
+                                         ((INSTANCE) == UART7)  || \
+                                         ((INSTANCE) == UART8))
+
+/****************** UART Instances : Auto Baud Rate detection *****************/
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                                            ((INSTANCE) == USART2) || \
+                                                            ((INSTANCE) == USART3) || \
+                                                            ((INSTANCE) == UART4)  || \
+                                                            ((INSTANCE) == UART5)  || \
+                                                            ((INSTANCE) == USART6) || \
+                                                            ((INSTANCE) == UART7)  || \
+                                                            ((INSTANCE) == UART8))
+
+/*********************** UART Instances : Driver Enable ***********************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                                  ((INSTANCE) == USART2) || \
+                                                  ((INSTANCE) == USART3) || \
+                                                  ((INSTANCE) == UART4)  || \
+                                                  ((INSTANCE) == UART5)  || \
+                                                  ((INSTANCE) == USART6) || \
+                                                  ((INSTANCE) == UART7)  || \
+                                                  ((INSTANCE) == UART8)  || \
+                                                  ((INSTANCE) == LPUART1))
+
+/********************* UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                               ((INSTANCE) == USART2) || \
+                                               ((INSTANCE) == USART3) || \
+                                               ((INSTANCE) == UART4)  || \
+                                               ((INSTANCE) == UART5)  || \
+                                               ((INSTANCE) == USART6) || \
+                                               ((INSTANCE) == UART7)  || \
+                                               ((INSTANCE) == UART8)  || \
+                                               ((INSTANCE) == LPUART1))
+
+/******************* UART Instances : Hardware Flow control *******************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                           ((INSTANCE) == USART2) || \
+                                           ((INSTANCE) == USART3) || \
+                                           ((INSTANCE) == UART4)  || \
+                                           ((INSTANCE) == UART5)  || \
+                                           ((INSTANCE) == USART6) || \
+                                           ((INSTANCE) == UART7)  || \
+                                           ((INSTANCE) == UART8)  || \
+                                           ((INSTANCE) == LPUART1))
+
+/************************* UART Instances : LIN mode **************************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                        ((INSTANCE) == USART2) || \
+                                        ((INSTANCE) == USART3) || \
+                                        ((INSTANCE) == UART4)  || \
+                                        ((INSTANCE) == UART5)  || \
+                                        ((INSTANCE) == USART6) || \
+                                        ((INSTANCE) == UART7)  || \
+                                        ((INSTANCE) == UART8))
+
+/****************** UART Instances : Wake-up from Stop mode *******************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                                    ((INSTANCE) == USART2) || \
+                                                    ((INSTANCE) == USART3) || \
+                                                    ((INSTANCE) == UART4)  || \
+                                                    ((INSTANCE) == UART5)  || \
+                                                    ((INSTANCE) == USART6) || \
+                                                    ((INSTANCE) == UART7)  || \
+                                                    ((INSTANCE) == UART8)  || \
+                                                    ((INSTANCE) == LPUART1))
+
+/************************* UART Instances : IRDA mode *************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                    ((INSTANCE) == USART2) || \
+                                    ((INSTANCE) == USART3) || \
+                                    ((INSTANCE) == UART4)  || \
+                                    ((INSTANCE) == UART5)  || \
+                                    ((INSTANCE) == USART6) || \
+                                    ((INSTANCE) == UART7)  || \
+                                    ((INSTANCE) == UART8))
+
+/********************* USART Instances : Smard card mode **********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                         ((INSTANCE) == USART2) || \
+                                         ((INSTANCE) == USART3) || \
+                                         ((INSTANCE) == USART6))
+
+/****************************** LPUART Instance *******************************/
+#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG1)
+/****************************** USB Instances ********************************/
+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG1)
+/****************************** MDIOS Instances ********************************/
+#define IS_MDIOS_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == MDIOS)
+
+/****************************** CEC Instances *********************************/
+#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
+
+/****************************** SAI Instances ********************************/
+#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
+                    ((INSTANCE) == SAI1_Block_B) || \
+                     ((INSTANCE) == SAI2_Block_A) || \
+                     ((INSTANCE) == SAI2_Block_B) || \
+                     ((INSTANCE) == SAI3_Block_A) || \
+                     ((INSTANCE) == SAI3_Block_B) || \
+                     ((INSTANCE) == SAI4_Block_A) || \
+                     ((INSTANCE) == SAI4_Block_B))
+
+/****************************** SPDIFRX Instances ********************************/
+#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)
+
+/****************************** OPAMP Instances *******************************/
+#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
+                                         ((INSTANCE) == OPAMP2))
+
+#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
+
+/*********************** USB OTG PCD Instances ********************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+                                        ((INSTANCE) == USB_OTG_HS))
+
+/*********************** USB OTG HCD Instances ********************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+                                       ((INSTANCE) == USB_OTG_HS))
+
+/******************************************************************************/
+/*  For a painless codes migration between the STM32H7xx device product       */
+/*  lines, or with STM32F7xx devices the aliases defined below are put        */
+/*   in place to overcome the differences in the interrupt handlers and IRQn  */
+/*   definitions. No need to update developed interrupt code when moving      */
+/*  across product lines within the same STM32H7 Family                       */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define  HASH_RNG_IRQn                  RNG_IRQn
+#define  TIM1_BRK_TIM9_IRQn             TIM1_BRK_IRQn
+#define  TIM1_UP_TIM10_IRQn             TIM1_UP_IRQn
+#define  TIM1_TRG_COM_TIM11_IRQn        TIM1_TRG_COM_IRQn
+#define  PVD_IRQn                       PVD_AVD_IRQn
+
+
+
+/* Aliases for __IRQHandler */
+#define  HASH_RNG_IRQHandler           RNG_IRQHandler
+#define TIM1_BRK_TIM9_IRQHandler       TIM1_BRK_IRQHandler
+#define TIM1_UP_TIM9_IRQHandler        TIM1_UP_IRQHandler
+#define TIM1_TRG_COM_TIM11_IRQHandler  TIM1_TRG_COM_IRQHandler
+#define PVD_IRQHandler                 PVD_AVD_IRQHandler
+
+/* Aliases for COMP __IRQHandler */
+#define COMP_IRQHandler                COMP1_IRQHandler
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* STM32H743xx_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h
new file mode 100644
index 00000000..f6296181
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h
@@ -0,0 +1,224 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32H7xx Device Peripheral Access Layer Header File.
+  *
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The STM32H7xx device used in the target application
+  *              - To use or not the peripheral�s drivers in application code(i.e.
+  *                code will be based on direct access to peripheral�s registers
+  *                rather than drivers API), this option is controlled by
+  *                "#define USE_HAL_DRIVER"
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32h7xx
+  * @{
+  */
+
+#ifndef STM32H7xx_H
+#define STM32H7xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+
+/**
+  * @brief STM32 Family
+  */
+#if !defined  (STM32H7)
+#define STM32H7
+#endif /* STM32H7 */
+
+
+/* Uncomment the line below according to the target STM32H7 device used in your
+   application
+  */
+
+#if !defined (STM32H743xx) && !defined (STM32H753xx)  && !defined (STM32H750xx) && !defined (STM32H742xx) && \
+    !defined (STM32H745xx) && !defined (STM32H755xx)  && !defined (STM32H747xx) && !defined (STM32H757xx) && \
+    !defined (STM32H7A3xx) && !defined (STM32H7A3xxQ) && !defined (STM32H7B3xx) && !defined (STM32H7B3xxQ) && !defined (STM32H7B0xx)  && !defined (STM32H7B0xxQ)
+  /* #define STM32H742xx */   /*!< STM32H742VI, STM32H742ZI, STM32H742AI, STM32H742II, STM32H742BI, STM32H742XI Devices */
+  /* #define STM32H743xx */   /*!< STM32H743VI, STM32H743ZI, STM32H743AI, STM32H743II, STM32H743BI, STM32H743XI Devices */
+  /* #define STM32H753xx */   /*!< STM32H753VI, STM32H753ZI, STM32H753AI, STM32H753II, STM32H753BI, STM32H753XI Devices */
+  /* #define STM32H750xx */   /*!< STM32H750V, STM32H750I, STM32H750X Devices */
+  /* #define STM32H747xx */   /*!< STM32H747ZI, STM32H747AI, STM32H747II, STM32H747BI, STM32H747XI Devices */
+  /* #define STM32H757xx */   /*!< STM32H757ZI, STM32H757AI, STM32H757II, STM32H757BI, STM32H757XI Devices */
+  /* #define STM32H745xx */   /*!< STM32H745ZI, STM32H745II, STM32H745BI, STM32H745XI Devices  */
+  /* #define STM32H755xx */   /*!< STM32H755ZI, STM32H755II, STM32H755BI, STM32H755XI Devices  */
+  /* #define STM32H7B0xx */   /*!< STM32H7B0ABIxQ, STM32H7B0IBTx, STM32H7B0RBTx, STM32H7B0VBTx, STM32H7B0ZBTx, STM32H7B0IBKxQ */
+  /* #define STM32H7A3xx */   /*!< STM32H7A3IIK6, STM32H7A3IIT6, STM32H7A3NIH6, STM32H7A3RIT6, STM32H7A3VIH6, STM32H7A3VIT6, STM32H7A3ZIT6 */
+  /* #define STM32H7A3xxQ */  /*!< STM32H7A3QIY6Q, STM32H7A3IIK6Q, STM32H7A3IIT6Q, STM32H7A3LIH6Q, STM32H7A3VIH6Q, STM32H7A3VIT6Q, STM32H7A3AII6Q, STM32H7A3ZIT6Q */
+  /* #define STM32H7B3xx */   /*!< STM32H7B3IIK6, STM32H7B3IIT6, STM32H7B3NIH6, STM32H7B3RIT6, STM32H7B3VIH6, STM32H7B3VIT6, STM32H7B3ZIT6 */
+  /* #define STM32H7B3xxQ */  /*!< STM32H7B3QIY6Q, STM32H7B3IIK6Q, STM32H7B3IIT6Q, STM32H7B3LIH6Q, STM32H7B3VIH6Q, STM32H7B3VIT6Q, STM32H7B3AII6Q, STM32H7B3ZIT6Q */
+#endif
+
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+
+#if defined(DUAL_CORE) && !defined(CORE_CM4) && !defined(CORE_CM7)
+ #error "Dual core device, please select CORE_CM4 or CORE_CM7"
+#endif
+
+#if !defined  (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will
+   be based on direct access to peripherals registers
+   */
+  /*#define USE_HAL_DRIVER */
+#endif /* USE_HAL_DRIVER */
+
+/**
+  * @brief CMSIS Device version number V1.8.0
+  */
+#define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN   (0x01) /*!< [31:24] main version */
+#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1   (0x08) /*!< [23:16] sub1 version */
+#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __STM32H7xx_CMSIS_DEVICE_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
+#define __STM32H7xx_CMSIS_DEVICE_VERSION        ((__CMSIS_DEVICE_VERSION_MAIN     << 24)\
+                                      |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
+                                      |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
+                                      |(__CMSIS_DEVICE_HAL_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Device_Included
+  * @{
+  */
+
+#if defined(STM32H743xx)
+  #include "stm32h743xx.h"
+#elif defined(STM32H753xx)
+  #include "stm32h753xx.h"
+#elif defined(STM32H750xx)
+  #include "stm32h750xx.h"
+#elif defined(STM32H742xx)
+  #include "stm32h742xx.h"
+#elif defined(STM32H745xx)
+  #include "stm32h745xx.h"
+#elif defined(STM32H755xx)
+  #include "stm32h755xx.h"
+#elif defined(STM32H747xx)
+  #include "stm32h747xx.h"
+#elif defined(STM32H757xx)
+  #include "stm32h757xx.h"
+#elif defined(STM32H7B0xx)
+  #include "stm32h7b0xx.h"
+#elif defined(STM32H7B0xxQ)
+  #include "stm32h7b0xxq.h"
+#elif defined(STM32H7A3xx)
+  #include "stm32h7a3xx.h"
+#elif defined(STM32H7B3xx)
+  #include "stm32h7b3xx.h"
+#elif defined(STM32H7A3xxQ)
+  #include "stm32h7a3xxq.h"
+#elif defined(STM32H7B3xxQ)
+  #include "stm32h7b3xxq.h"
+#else
+ #error "Please select first the target STM32H7xx device used in your application (in stm32h7xx.h file)"
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_types
+  * @{
+  */
+typedef enum
+{
+  RESET = 0,
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+  DISABLE = 0,
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+  SUCCESS = 0,
+  ERROR = !SUCCESS
+} ErrorStatus;
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL)))
+
+
+/**
+  * @}
+  */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32h7xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* STM32H7xx_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h
new file mode 100644
index 00000000..dd75af67
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h
@@ -0,0 +1,105 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32h7xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-Mx Device System Source File for STM32H7xx devices.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32h7xx_system
+  * @{
+  */
+
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef SYSTEM_STM32H7XX_H
+#define SYSTEM_STM32H7XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32H7xx_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32H7xx_System_Exported_types
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+extern uint32_t SystemCoreClock;             /*!< System Domain1 Clock Frequency  */
+extern uint32_t SystemD2Clock;               /*!< System Domain2 Clock Frequency  */
+extern const  uint8_t D1CorePrescTable[16] ; /*!< D1CorePrescTable prescalers table values */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Exported_Functions
+  * @{
+  */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_STM32H7XX_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/cmsis_armcc.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/cmsis_armcc.h
new file mode 100644
index 00000000..7d751fb3
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/cmsis_armcc.h
@@ -0,0 +1,865 @@
+/**************************************************************************//**
+ * @file     cmsis_armcc.h
+ * @brief    CMSIS compiler ARMCC (Arm Compiler 5) header file
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+  #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \
+     (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )
+  #define __ARM_ARCH_6M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))
+  #define __ARM_ARCH_7M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+  #define __ARM_ARCH_7EM__          1
+#endif
+
+  /* __ARM_ARCH_8M_BASE__  not applicable */
+  /* __ARM_ARCH_8M_MAIN__  not applicable */
+
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE                 
+  #define __STATIC_FORCEINLINE                   static __forceinline
+#endif           
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __declspec(noreturn)
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        __packed struct
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         __packed union
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #define __UNALIGNED_UINT32(x)                  (*((__packed uint32_t *)(x)))
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();     */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();    */
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  register uint32_t __regBasePriMax      __ASM("basepri_max");
+  __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#else
+  (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB() do {\
+                   __schedule_barrier();\
+                   __isb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+                   __schedule_barrier();\
+                   __dsb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+                   __schedule_barrier();\
+                   __dmb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+                  
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+  #define __RBIT                          __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value != 0U; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+  return result;
+}
+#endif
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
+#else
+  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
+#else
+  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
+#else
+  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXB(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX                           __clrex
+
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#else  /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/cmsis_armclang.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/cmsis_armclang.h
new file mode 100644
index 00000000..d8031b03
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/cmsis_armclang.h
@@ -0,0 +1,1869 @@
+/**************************************************************************//**
+ * @file     cmsis_armclang.h
+ * @brief    CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header   /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include <arm_compat.h>    /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE                 
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline
+#endif                                           
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+  
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+  
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+  return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#define __get_FPSCR      (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR()      ((uint32_t)0U)
+#endif
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#define __set_FPSCR      __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x)      ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP          __builtin_arm_nop
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI          __builtin_arm_wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE          __builtin_arm_wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV          __builtin_arm_sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB()        __builtin_arm_isb(0xF);
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()        __builtin_arm_dsb(0xF);
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB()        __builtin_arm_dmb(0xF);
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV(value)   __builtin_bswap32(value)
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U)
+  {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)     __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __RBIT            __builtin_arm_rbit
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ             (uint8_t)__builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB        (uint8_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH        (uint16_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW        (uint32_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXB        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXH        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXW        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX             __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT             __builtin_arm_ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT             __builtin_arm_usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXB                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXH                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEX                  (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+  int32_t result;
+
+  __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/cmsis_compiler.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/cmsis_compiler.h
new file mode 100644
index 00000000..79a2cac3
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/cmsis_compiler.h
@@ -0,0 +1,266 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/cmsis_gcc.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/cmsis_gcc.h
new file mode 100644
index 00000000..1bd41a49
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/cmsis_gcc.h
@@ -0,0 +1,2085 @@
+/**************************************************************************//**
+ * @file     cmsis_gcc.h
+ * @brief    CMSIS compiler GCC header file
+ * @version  V5.0.4
+ * @date     09. April 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+  #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static inline
+#endif
+#ifndef   __STATIC_FORCEINLINE                 
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
+#endif                                           
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+  
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+  
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+  return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_get_fpscr) 
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+  return __builtin_arm_get_fpscr();
+#else
+  uint32_t result;
+
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  return(result);
+#endif
+#else
+  return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_set_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+  __builtin_arm_set_fpscr(fpscr);
+#else
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#endif
+#else
+  (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP()                             __ASM volatile ("nop")
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI()                             __ASM volatile ("wfi")
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE()                             __ASM volatile ("wfe")
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV()                             __ASM volatile ("sev")
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE void __ISB(void)
+{
+  __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+  __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+  __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (int16_t)__builtin_bswap16(value);
+#else
+  int16_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U)
+  {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value != 0U; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+#endif
+  return result;
+}
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ             (uint8_t)__builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  ARG1  Value to be saturated
+  \param [in]  ARG2  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+__extension__ \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  ARG1  Value to be saturated
+  \param [in]  ARG2  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+ __extension__ \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/cmsis_iccarm.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/cmsis_iccarm.h
new file mode 100644
index 00000000..3c90a2cd
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/cmsis_iccarm.h
@@ -0,0 +1,935 @@
+/**************************************************************************//**
+ * @file     cmsis_iccarm.h
+ * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version  V5.0.7
+ * @date     19. June 2018
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2018 IAR Systems
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+  #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+  #define __ICCARM_V8 1
+#else
+  #define __ICCARM_V8 0
+#endif
+
+#ifndef __ALIGNED
+  #if __ICCARM_V8
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #elif (__VER__ >= 7080000)
+    /* Needs IAR language extensions */
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #else
+    #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
+/* Macros already defined */
+#else
+  #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
+    #if __ARM_ARCH == 6
+      #define __ARM_ARCH_6M__ 1
+    #elif __ARM_ARCH == 7
+      #if __ARM_FEATURE_DSP
+        #define __ARM_ARCH_7EM__ 1
+      #else
+        #define __ARM_ARCH_7M__ 1
+      #endif
+    #endif /* __ARM_ARCH */
+  #endif /* __ARM_ARCH_PROFILE == 'M' */
+#endif
+
+/* Alternativ core deduction for older ICCARM's */
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
+    !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
+  #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
+    #define __ARM_ARCH_6M__ 1
+  #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
+    #define __ARM_ARCH_7M__ 1
+  #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
+    #define __ARM_ARCH_7EM__  1
+  #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #else
+    #error "Unknown target."
+  #endif
+#endif
+
+
+
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
+  #define __IAR_M0_FAMILY  1
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
+  #define __IAR_M0_FAMILY  1
+#else
+  #define __IAR_M0_FAMILY  0
+#endif
+
+
+#ifndef __ASM
+  #define __ASM __asm
+#endif
+
+#ifndef __INLINE
+  #define __INLINE inline
+#endif
+
+#ifndef   __NO_RETURN
+  #if __ICCARM_V8
+    #define __NO_RETURN __attribute__((__noreturn__))
+  #else
+    #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+  #endif
+#endif
+
+#ifndef   __PACKED
+  #if __ICCARM_V8
+    #define __PACKED __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED __packed
+  #endif
+#endif
+
+#ifndef   __PACKED_STRUCT
+  #if __ICCARM_V8
+    #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_STRUCT __packed struct
+  #endif
+#endif
+
+#ifndef   __PACKED_UNION
+  #if __ICCARM_V8
+    #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_UNION __packed union
+  #endif
+#endif
+
+#ifndef   __RESTRICT
+  #define __RESTRICT            __restrict
+#endif
+
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE       static inline
+#endif
+
+#ifndef   __FORCEINLINE
+  #define __FORCEINLINE         _Pragma("inline=forced")
+#endif
+
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE  __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+{
+  return *(__packed uint16_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+{
+  *(__packed uint16_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+{
+  return *(__packed uint32_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+{
+  *(__packed uint32_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32   /* deprecated */
+#pragma language=save
+#pragma language=extended
+__packed struct  __iar_u32 { uint32_t v; };
+#pragma language=restore
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+
+#ifndef   __USED
+  #if __ICCARM_V8
+    #define __USED __attribute__((used))
+  #else
+    #define __USED _Pragma("__root")
+  #endif
+#endif
+
+#ifndef   __WEAK
+  #if __ICCARM_V8
+    #define __WEAK __attribute__((weak))
+  #else
+    #define __WEAK _Pragma("__weak")
+  #endif
+#endif
+
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+  #define __ICCARM_INTRINSICS_VERSION__  0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+  #if defined(__CLZ)
+    #undef __CLZ
+  #endif
+  #if defined(__REVSH)
+    #undef __REVSH
+  #endif
+  #if defined(__RBIT)
+    #undef __RBIT
+  #endif
+  #if defined(__SSAT)
+    #undef __SSAT
+  #endif
+  #if defined(__USAT)
+    #undef __USAT
+  #endif
+
+  #include "iccarm_builtin.h"
+
+  #define __disable_fault_irq __iar_builtin_disable_fiq
+  #define __disable_irq       __iar_builtin_disable_interrupt
+  #define __enable_fault_irq  __iar_builtin_enable_fiq
+  #define __enable_irq        __iar_builtin_enable_interrupt
+  #define __arm_rsr           __iar_builtin_rsr
+  #define __arm_wsr           __iar_builtin_wsr
+
+
+  #define __get_APSR()                (__arm_rsr("APSR"))
+  #define __get_BASEPRI()             (__arm_rsr("BASEPRI"))
+  #define __get_CONTROL()             (__arm_rsr("CONTROL"))
+  #define __get_FAULTMASK()           (__arm_rsr("FAULTMASK"))
+
+  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+    #define __get_FPSCR()             (__arm_rsr("FPSCR"))
+    #define __set_FPSCR(VALUE)        (__arm_wsr("FPSCR", (VALUE)))
+  #else
+    #define __get_FPSCR()             ( 0 )
+    #define __set_FPSCR(VALUE)        ((void)VALUE)
+  #endif
+
+  #define __get_IPSR()                (__arm_rsr("IPSR"))
+  #define __get_MSP()                 (__arm_rsr("MSP"))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __get_MSPLIM()            (0U)
+  #else
+    #define __get_MSPLIM()            (__arm_rsr("MSPLIM"))
+  #endif
+  #define __get_PRIMASK()             (__arm_rsr("PRIMASK"))
+  #define __get_PSP()                 (__arm_rsr("PSP"))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __get_PSPLIM()            (0U)
+  #else
+    #define __get_PSPLIM()            (__arm_rsr("PSPLIM"))
+  #endif
+
+  #define __get_xPSR()                (__arm_rsr("xPSR"))
+
+  #define __set_BASEPRI(VALUE)        (__arm_wsr("BASEPRI", (VALUE)))
+  #define __set_BASEPRI_MAX(VALUE)    (__arm_wsr("BASEPRI_MAX", (VALUE)))
+  #define __set_CONTROL(VALUE)        (__arm_wsr("CONTROL", (VALUE)))
+  #define __set_FAULTMASK(VALUE)      (__arm_wsr("FAULTMASK", (VALUE)))
+  #define __set_MSP(VALUE)            (__arm_wsr("MSP", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __set_MSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_MSPLIM(VALUE)       (__arm_wsr("MSPLIM", (VALUE)))
+  #endif
+  #define __set_PRIMASK(VALUE)        (__arm_wsr("PRIMASK", (VALUE)))
+  #define __set_PSP(VALUE)            (__arm_wsr("PSP", (VALUE)))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __set_PSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_PSPLIM(VALUE)       (__arm_wsr("PSPLIM", (VALUE)))
+  #endif
+
+  #define __TZ_get_CONTROL_NS()       (__arm_rsr("CONTROL_NS"))
+  #define __TZ_set_CONTROL_NS(VALUE)  (__arm_wsr("CONTROL_NS", (VALUE)))
+  #define __TZ_get_PSP_NS()           (__arm_rsr("PSP_NS"))
+  #define __TZ_set_PSP_NS(VALUE)      (__arm_wsr("PSP_NS", (VALUE)))
+  #define __TZ_get_MSP_NS()           (__arm_rsr("MSP_NS"))
+  #define __TZ_set_MSP_NS(VALUE)      (__arm_wsr("MSP_NS", (VALUE)))
+  #define __TZ_get_SP_NS()            (__arm_rsr("SP_NS"))
+  #define __TZ_set_SP_NS(VALUE)       (__arm_wsr("SP_NS", (VALUE)))
+  #define __TZ_get_PRIMASK_NS()       (__arm_rsr("PRIMASK_NS"))
+  #define __TZ_set_PRIMASK_NS(VALUE)  (__arm_wsr("PRIMASK_NS", (VALUE)))
+  #define __TZ_get_BASEPRI_NS()       (__arm_rsr("BASEPRI_NS"))
+  #define __TZ_set_BASEPRI_NS(VALUE)  (__arm_wsr("BASEPRI_NS", (VALUE)))
+  #define __TZ_get_FAULTMASK_NS()     (__arm_rsr("FAULTMASK_NS"))
+  #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __TZ_get_PSPLIM_NS()      (0U)
+    #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+  #else
+    #define __TZ_get_PSPLIM_NS()      (__arm_rsr("PSPLIM_NS"))
+    #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+  #endif
+
+  #define __TZ_get_MSPLIM_NS()        (__arm_rsr("MSPLIM_NS"))
+  #define __TZ_set_MSPLIM_NS(VALUE)   (__arm_wsr("MSPLIM_NS", (VALUE)))
+
+  #define __NOP     __iar_builtin_no_operation
+
+  #define __CLZ     __iar_builtin_CLZ
+  #define __CLREX   __iar_builtin_CLREX
+
+  #define __DMB     __iar_builtin_DMB
+  #define __DSB     __iar_builtin_DSB
+  #define __ISB     __iar_builtin_ISB
+
+  #define __LDREXB  __iar_builtin_LDREXB
+  #define __LDREXH  __iar_builtin_LDREXH
+  #define __LDREXW  __iar_builtin_LDREX
+
+  #define __RBIT    __iar_builtin_RBIT
+  #define __REV     __iar_builtin_REV
+  #define __REV16   __iar_builtin_REV16
+
+  __IAR_FT int16_t __REVSH(int16_t val)
+  {
+    return (int16_t) __iar_builtin_REVSH(val);
+  }
+
+  #define __ROR     __iar_builtin_ROR
+  #define __RRX     __iar_builtin_RRX
+
+  #define __SEV     __iar_builtin_SEV
+
+  #if !__IAR_M0_FAMILY
+    #define __SSAT    __iar_builtin_SSAT
+  #endif
+
+  #define __STREXB  __iar_builtin_STREXB
+  #define __STREXH  __iar_builtin_STREXH
+  #define __STREXW  __iar_builtin_STREX
+
+  #if !__IAR_M0_FAMILY
+    #define __USAT    __iar_builtin_USAT
+  #endif
+
+  #define __WFE     __iar_builtin_WFE
+  #define __WFI     __iar_builtin_WFI
+
+  #if __ARM_MEDIA__
+    #define __SADD8   __iar_builtin_SADD8
+    #define __QADD8   __iar_builtin_QADD8
+    #define __SHADD8  __iar_builtin_SHADD8
+    #define __UADD8   __iar_builtin_UADD8
+    #define __UQADD8  __iar_builtin_UQADD8
+    #define __UHADD8  __iar_builtin_UHADD8
+    #define __SSUB8   __iar_builtin_SSUB8
+    #define __QSUB8   __iar_builtin_QSUB8
+    #define __SHSUB8  __iar_builtin_SHSUB8
+    #define __USUB8   __iar_builtin_USUB8
+    #define __UQSUB8  __iar_builtin_UQSUB8
+    #define __UHSUB8  __iar_builtin_UHSUB8
+    #define __SADD16  __iar_builtin_SADD16
+    #define __QADD16  __iar_builtin_QADD16
+    #define __SHADD16 __iar_builtin_SHADD16
+    #define __UADD16  __iar_builtin_UADD16
+    #define __UQADD16 __iar_builtin_UQADD16
+    #define __UHADD16 __iar_builtin_UHADD16
+    #define __SSUB16  __iar_builtin_SSUB16
+    #define __QSUB16  __iar_builtin_QSUB16
+    #define __SHSUB16 __iar_builtin_SHSUB16
+    #define __USUB16  __iar_builtin_USUB16
+    #define __UQSUB16 __iar_builtin_UQSUB16
+    #define __UHSUB16 __iar_builtin_UHSUB16
+    #define __SASX    __iar_builtin_SASX
+    #define __QASX    __iar_builtin_QASX
+    #define __SHASX   __iar_builtin_SHASX
+    #define __UASX    __iar_builtin_UASX
+    #define __UQASX   __iar_builtin_UQASX
+    #define __UHASX   __iar_builtin_UHASX
+    #define __SSAX    __iar_builtin_SSAX
+    #define __QSAX    __iar_builtin_QSAX
+    #define __SHSAX   __iar_builtin_SHSAX
+    #define __USAX    __iar_builtin_USAX
+    #define __UQSAX   __iar_builtin_UQSAX
+    #define __UHSAX   __iar_builtin_UHSAX
+    #define __USAD8   __iar_builtin_USAD8
+    #define __USADA8  __iar_builtin_USADA8
+    #define __SSAT16  __iar_builtin_SSAT16
+    #define __USAT16  __iar_builtin_USAT16
+    #define __UXTB16  __iar_builtin_UXTB16
+    #define __UXTAB16 __iar_builtin_UXTAB16
+    #define __SXTB16  __iar_builtin_SXTB16
+    #define __SXTAB16 __iar_builtin_SXTAB16
+    #define __SMUAD   __iar_builtin_SMUAD
+    #define __SMUADX  __iar_builtin_SMUADX
+    #define __SMMLA   __iar_builtin_SMMLA
+    #define __SMLAD   __iar_builtin_SMLAD
+    #define __SMLADX  __iar_builtin_SMLADX
+    #define __SMLALD  __iar_builtin_SMLALD
+    #define __SMLALDX __iar_builtin_SMLALDX
+    #define __SMUSD   __iar_builtin_SMUSD
+    #define __SMUSDX  __iar_builtin_SMUSDX
+    #define __SMLSD   __iar_builtin_SMLSD
+    #define __SMLSDX  __iar_builtin_SMLSDX
+    #define __SMLSLD  __iar_builtin_SMLSLD
+    #define __SMLSLDX __iar_builtin_SMLSLDX
+    #define __SEL     __iar_builtin_SEL
+    #define __QADD    __iar_builtin_QADD
+    #define __QSUB    __iar_builtin_QSUB
+    #define __PKHBT   __iar_builtin_PKHBT
+    #define __PKHTB   __iar_builtin_PKHTB
+  #endif
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #define __CLZ  __cmsis_iar_clz_not_active
+    #define __SSAT __cmsis_iar_ssat_not_active
+    #define __USAT __cmsis_iar_usat_not_active
+    #define __RBIT __cmsis_iar_rbit_not_active
+    #define __get_APSR  __cmsis_iar_get_APSR_not_active
+  #endif
+
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+    #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
+  #endif
+
+  #ifdef __INTRINSICS_INCLUDED
+  #error intrinsics.h is already included previously!
+  #endif
+
+  #include <intrinsics.h>
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #undef __CLZ
+    #undef __SSAT
+    #undef __USAT
+    #undef __RBIT
+    #undef __get_APSR
+
+    __STATIC_INLINE uint8_t __CLZ(uint32_t data)
+    {
+      if (data == 0U) { return 32U; }
+
+      uint32_t count = 0U;
+      uint32_t mask = 0x80000000U;
+
+      while ((data & mask) == 0U)
+      {
+        count += 1U;
+        mask = mask >> 1U;
+      }
+      return count;
+    }
+
+    __STATIC_INLINE uint32_t __RBIT(uint32_t v)
+    {
+      uint8_t sc = 31U;
+      uint32_t r = v;
+      for (v >>= 1U; v; v >>= 1U)
+      {
+        r <<= 1U;
+        r |= v & 1U;
+        sc--;
+      }
+      return (r << sc);
+    }
+
+    __STATIC_INLINE  uint32_t __get_APSR(void)
+    {
+      uint32_t res;
+      __asm("MRS      %0,APSR" : "=r" (res));
+      return res;
+    }
+
+  #endif
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #undef __get_FPSCR
+    #undef __set_FPSCR
+    #define __get_FPSCR()       (0)
+    #define __set_FPSCR(VALUE)  ((void)VALUE)
+  #endif
+
+  #pragma diag_suppress=Pe940
+  #pragma diag_suppress=Pe177
+
+  #define __enable_irq    __enable_interrupt
+  #define __disable_irq   __disable_interrupt
+  #define __NOP           __no_operation
+
+  #define __get_xPSR      __get_PSR
+
+  #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
+
+    __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+    {
+      return __LDREX((unsigned long *)ptr);
+    }
+
+    __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+    {
+      return __STREX(value, (unsigned long *)ptr);
+    }
+  #endif
+
+
+  /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+  #if (__CORTEX_M >= 0x03)
+
+    __IAR_FT uint32_t __RRX(uint32_t value)
+    {
+      uint32_t result;
+      __ASM("RRX      %0, %1" : "=r"(result) : "r" (value) : "cc");
+      return(result);
+    }
+
+    __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_MAX,%0"::"r" (value));
+    }
+
+
+    #define __enable_fault_irq  __enable_fiq
+    #define __disable_fault_irq __disable_fiq
+
+
+  #endif /* (__CORTEX_M >= 0x03) */
+
+  __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+  {
+    return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+  }
+
+  #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+       (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+   __IAR_FT uint32_t __get_MSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,MSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_MSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      MSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __get_PSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,PSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_PSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      PSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,CONTROL_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_CONTROL_NS(uint32_t value)
+    {
+      __asm volatile("MSR      CONTROL_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_SP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,SP_NS" : "=r" (res));
+      return res;
+    }
+    __IAR_FT void   __TZ_set_SP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      SP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PRIMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PRIMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PRIMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PRIMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_BASEPRI_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,BASEPRI_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_BASEPRI_NS(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_FAULTMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,FAULTMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_FAULTMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      FAULTMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSPLIM_NS(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,PSPLIM_NS" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PSPLIM_NS(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      PSPLIM_NS,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSPLIM_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSPLIM_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSPLIM_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSPLIM_NS,%0" :: "r" (value));
+    }
+
+  #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#endif   /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value)    __asm volatile ("BKPT     %0" : : "i"(value))
+
+#if __IAR_M0_FAMILY
+  __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+  {
+    if ((sat >= 1U) && (sat <= 32U))
+    {
+      const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+      const int32_t min = -1 - max ;
+      if (val > max)
+      {
+        return max;
+      }
+      else if (val < min)
+      {
+        return min;
+      }
+    }
+    return val;
+  }
+
+  __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+  {
+    if (sat <= 31U)
+    {
+      const uint32_t max = ((1U << sat) - 1U);
+      if (val > (int32_t)max)
+      {
+        return max;
+      }
+      else if (val < 0)
+      {
+        return 0U;
+      }
+    }
+    return (uint32_t)val;
+  }
+#endif
+
+#if (__CORTEX_M >= 0x03)   /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+  __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
+  {
+    __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
+  {
+    __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
+  {
+    __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+  }
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+
+  __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
+  {
+    __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
+  {
+    __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
+  {
+    __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#undef __IAR_FT
+#undef __IAR_M0_FAMILY
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#endif /* __CMSIS_ICCARM_H__ */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/cmsis_version.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/cmsis_version.h
new file mode 100644
index 00000000..ae3f2e33
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/cmsis_version.h
@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 1U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/core_armv8mbl.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/core_armv8mbl.h
new file mode 100644
index 00000000..ec76ab21
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/core_armv8mbl.h
@@ -0,0 +1,1918 @@
+/**************************************************************************//**
+ * @file     core_armv8mbl.h
+ * @brief    CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File
+ * @version  V5.0.7
+ * @date     22. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MBL_H_GENERIC
+#define __CORE_ARMV8MBL_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_ARMv8MBL
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS definitions */
+#define __ARMv8MBL_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __ARMv8MBL_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __ARMv8MBL_CMSIS_VERSION       ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
+                                         __ARMv8MBL_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                     ( 2U)                                            /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MBL_H_DEPENDANT
+#define __CORE_ARMV8MBL_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __ARMv8MBL_REV
+    #define __ARMv8MBL_REV               0x0000U
+    #warning "__ARMv8MBL_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ETM_PRESENT
+    #define __ETM_PRESENT             0U
+    #warning "__ETM_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MTB_PRESENT
+    #define __MTB_PRESENT             0U
+    #warning "__MTB_PRESENT not defined in device header file; using default!"
+  #endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MBL */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+        uint32_t RESERVED0[6U];
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Sizes Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Sizes Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
+        uint32_t RESERVED3[809U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  Software Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  Software Lock Status Register */
+        uint32_t RESERVED4[4U];
+  __IM  uint32_t TYPE;                   /*!< Offset: 0xFC8 (R/ )  Device Identifier Register */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos              0U                                         /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk             (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)    /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos                0U                                         /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk               (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)        /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos                     1U                                         /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk                    (0x1UL << TPI_LSR_nTT_Pos)                  /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos                     1U                                         /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk                    (0x1UL << TPI_LSR_SLK_Pos)                  /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos                     0U                                         /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk                    (0x1UL /*<< TPI_LSR_SLI_Pos*/)              /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+        uint32_t RESERVED0[7U];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
+#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
+#else
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
+#endif
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/core_armv8mml.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/core_armv8mml.h
new file mode 100644
index 00000000..2d0f1067
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/core_armv8mml.h
@@ -0,0 +1,2927 @@
+/**************************************************************************//**
+ * @file     core_armv8mml.h
+ * @brief    CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File
+ * @version  V5.0.7
+ * @date     06. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MML_H_GENERIC
+#define __CORE_ARMV8MML_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_ARMv8MML
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS Armv8MML definitions */
+#define __ARMv8MML_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __ARMv8MML_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __ARMv8MML_CMSIS_VERSION       ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
+                                         __ARMv8MML_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                     (81U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MML_H_DEPENDANT
+#define __CORE_ARMV8MML_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __ARMv8MML_REV
+    #define __ARMv8MML_REV               0x0000U
+    #warning "__ARMv8MML_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DSP_PRESENT
+    #define __DSP_PRESENT             0U
+    #warning "__DSP_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MML */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */
+    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */
+    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED6[580U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
+        uint32_t RESERVED3[92U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+        uint32_t RESERVED7[6U];
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
+        uint32_t RESERVED6[4U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+        uint32_t RESERVED32[934U];
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+        uint32_t RESERVED33[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Sizes Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Sizes Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
+        uint32_t RESERVED3[809U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  Software Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  Software Lock Status Register */
+        uint32_t RESERVED4[4U];
+  __IM  uint32_t TYPE;                   /*!< Offset: 0xFC8 (R/ )  Device Identifier Register */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos              0U                                         /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk             (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)    /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos                0U                                         /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk               (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)        /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos                     1U                                         /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk                    (0x1UL << TPI_LSR_nTT_Pos)                  /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos                     1U                                         /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk                    (0x1UL << TPI_LSR_SLK_Pos)                  /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos                     0U                                         /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk                    (0x1UL /*<< TPI_LSR_SLI_Pos*/)              /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
+  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
+  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
+  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
+        uint32_t RESERVED0[1];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#else
+        uint32_t RESERVED0[3];
+#endif
+  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
+  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
+  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
+  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
+#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
+#else
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
+#endif
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Priority Grouping (non-secure)
+  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB_NS->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB_NS->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping (non-secure)
+  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/core_cm0.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/core_cm0.h
new file mode 100644
index 00000000..6f82227c
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/core_cm0.h
@@ -0,0 +1,949 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V5.0.5
+ * @date     28. May 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M0
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM0_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (0U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000U
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+        uint32_t RESERVED0;
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           Address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/core_cm0plus.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/core_cm0plus.h
new file mode 100644
index 00000000..b9377e8c
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/core_cm0plus.h
@@ -0,0 +1,1083 @@
+/**************************************************************************//**
+ * @file     core_cm0plus.h
+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version  V5.0.6
+ * @date     28. May 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex-M0+
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM0+ definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB  (__CM_CMSIS_VERSION_SUB)                   /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
+                                       __CM0PLUS_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                   (0U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0PLUS_REV
+    #define __CM0PLUS_REV             0x0000U
+    #warning "__CM0PLUS_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 8U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0+ header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0+ */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+    uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/core_cm1.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/core_cm1.h
new file mode 100644
index 00000000..fd1c4077
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/core_cm1.h
@@ -0,0 +1,976 @@
+/**************************************************************************//**
+ * @file     core_cm1.h
+ * @brief    CMSIS Cortex-M1 Core Peripheral Access Layer Header File
+ * @version  V1.0.0
+ * @date     23. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM1_H_GENERIC
+#define __CORE_CM1_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M1
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM1 definitions */
+#define __CM1_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM1_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM1_CMSIS_VERSION       ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM1_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (1U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM1_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM1_H_DEPENDANT
+#define __CORE_CM1_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM1_REV
+    #define __CM1_REV               0x0100U
+    #warning "__CM1_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M1 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+        uint32_t RESERVED0;
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_ITCMUAEN_Pos            4U                                        /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMUAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos)         /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
+
+#define SCnSCB_ACTLR_ITCMLAEN_Pos            3U                                        /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMLAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos)         /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M1 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M1 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           Address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM1_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/core_cm23.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/core_cm23.h
new file mode 100644
index 00000000..8202a8dd
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/core_cm23.h
@@ -0,0 +1,1993 @@
+/**************************************************************************//**
+ * @file     core_cm23.h
+ * @brief    CMSIS Cortex-M23 Core Peripheral Access Layer Header File
+ * @version  V5.0.7
+ * @date     22. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM23_H_GENERIC
+#define __CORE_CM23_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M23
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS definitions */
+#define __CM23_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM23_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM23_CMSIS_VERSION       ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
+                                     __CM23_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                 (23U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM23_H_DEPENDANT
+#define __CORE_CM23_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM23_REV
+    #define __CM23_REV                0x0000U
+    #warning "__CM23_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ETM_PRESENT
+    #define __ETM_PRESENT             0U
+    #warning "__ETM_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MTB_PRESENT
+    #define __MTB_PRESENT             0U
+    #warning "__MTB_PRESENT not defined in device header file; using default!"
+  #endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M23 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+        uint32_t RESERVED0[6U];
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t ITFTTD0;                /*!< Offset: 0xEEC (R/ )  Integration Test FIFO Test Data 0 Register */
+  __IOM uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/W)  Integration Test ATB Control Register 2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  Integration Test ATB Control Register 0 */
+  __IM  uint32_t ITFTTD1;                /*!< Offset: 0xEFC (R/ )  Integration Test FIFO Test Data 1 Register */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  Device Configuration Register */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos      16U                                         /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos       8U                                         /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos       0U                                          /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk      (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)      /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)      /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos      16U                                         /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos       8U                                         /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos       0U                                          /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk      (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)      /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)      /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+        uint32_t RESERVED0[7U];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M23 */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M23 */
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */ 
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
+#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
+#else 
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
+#endif
+
+	
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/core_cm3.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/core_cm3.h
new file mode 100644
index 00000000..b0dfbd3d
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/core_cm3.h
@@ -0,0 +1,1941 @@
+/**************************************************************************//**
+ * @file     core_cm3.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version  V5.0.8
+ * @date     04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M3
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM3_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (3U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM3_REV
+    #define __CM3_REV               0x0200U
+    #warning "__CM3_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if defined (__CM3_REV) && (__CM3_REV < 0x0201U)                   /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+#else
+        uint32_t RESERVED1[1U];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) );               /* Insert write key and priority group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/core_cm33.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/core_cm33.h
new file mode 100644
index 00000000..02f82e29
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/core_cm33.h
@@ -0,0 +1,3002 @@
+/**************************************************************************//**
+ * @file     core_cm33.h
+ * @brief    CMSIS Cortex-M33 Core Peripheral Access Layer Header File
+ * @version  V5.0.9
+ * @date     06. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM33_H_GENERIC
+#define __CORE_CM33_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M33
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS CM33 definitions */
+#define __CM33_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM33_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM33_CMSIS_VERSION       ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
+                                     __CM33_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                 (33U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined (__TARGET_FPU_VFP)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined (__ARM_PCS_VFP)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined (__ARMVFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined (__TI_VFP_SUPPORT__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined (__FPU_VFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM33_H_DEPENDANT
+#define __CORE_CM33_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM33_REV
+    #define __CM33_REV                0x0000U
+    #warning "__CM33_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DSP_PRESENT
+    #define __DSP_PRESENT             0U
+    #warning "__DSP_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M33 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */
+    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */
+    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED6[580U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
+        uint32_t RESERVED3[92U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+        uint32_t RESERVED7[6U];
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
+        uint32_t RESERVED6[4U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+        uint32_t RESERVED32[934U];
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+        uint32_t RESERVED33[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t ITFTTD0;                /*!< Offset: 0xEEC (R/ )  Integration Test FIFO Test Data 0 Register */
+  __IOM uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/W)  Integration Test ATB Control Register 2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  Integration Test ATB Control Register 0 */
+  __IM  uint32_t ITFTTD1;                /*!< Offset: 0xEFC (R/ )  Integration Test FIFO Test Data 1 Register */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  Device Configuration Register */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos      16U                                         /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos       8U                                         /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos       0U                                          /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk      (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)      /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)      /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos      16U                                         /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos       8U                                         /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos       0U                                          /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk      (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)      /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)      /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
+  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
+  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
+  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
+        uint32_t RESERVED0[1];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#else
+        uint32_t RESERVED0[3];
+#endif
+  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
+  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
+  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
+  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */ 
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
+#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
+#else 
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
+#endif
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priority group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Priority Grouping (non-secure)
+  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB_NS->AIRCR;                                                /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
+  SCB_NS->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping (non-secure)
+  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/core_cm4.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/core_cm4.h
new file mode 100644
index 00000000..308b8681
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/core_cm4.h
@@ -0,0 +1,2129 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V5.0.8
+ * @date     04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M4
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM4_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (4U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000U
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
+#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+#define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after return, restore floating-point state  */
+#define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after return, restore floating-point state  */
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/core_cm7.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/core_cm7.h
new file mode 100644
index 00000000..ada6c2a5
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/core_cm7.h
@@ -0,0 +1,2671 @@
+/**************************************************************************//**
+ * @file     core_cm7.h
+ * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File
+ * @version  V5.0.8
+ * @date     04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM7_H_GENERIC
+#define __CORE_CM7_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M7
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM7 definitions */
+#define __CM7_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM7_CMSIS_VERSION_SUB   ( __CM_CMSIS_VERSION_SUB)                  /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM7_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (7U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM7_H_DEPENDANT
+#define __CORE_CM7_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM7_REV
+    #define __CM7_REV               0x0000U
+    #warning "__CM7_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ICACHE_PRESENT
+    #define __ICACHE_PRESENT          0U
+    #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DCACHE_PRESENT
+    #define __DCACHE_PRESENT          0U
+    #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DTCM_PRESENT
+    #define __DTCM_PRESENT            0U
+    #warning "__DTCM_PRESENT        not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M7 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MFR[4U];             /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[5U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+        uint32_t RESERVED3[93U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+        uint32_t RESERVED7[6U];
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                      18U                                           /*!< SCB CCR: Branch prediction enable bit Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: Branch prediction enable bit Mask */
+
+#define SCB_CCR_IC_Pos                      17U                                           /*!< SCB CCR: Instruction cache enable bit Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: Instruction cache enable bit Mask */
+
+#define SCB_CCR_DC_Pos                      16U                                           /*!< SCB CCR: Cache enable bit Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: Cache enable bit Mask */
+
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12U                                         /*!< ACTLR: DISITMATBFLUSH Position */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define SCnSCB_ACTLR_DISRAMODE_Pos         11U                                         /*!< ACTLR: DISRAMODE Position */
+#define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: DISRAMODE Mask */
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos         10U                                         /*!< ACTLR: FPEXCODIS Position */
+#define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: FPEXCODIS Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED3[981U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 (  W)  Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
+#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+#define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after return, restore floating-point state  */
+#define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after return, restore floating-point state  */
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)IRQn)]                = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]                >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = SCB->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################  Cache functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_CacheFunctions Cache Functions
+  \brief    Functions that configure Instruction and Data cache.
+  @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )
+
+
+/**
+  \brief   Enable I-Cache
+  \details Turns on I-Cache
+  */
+__STATIC_INLINE void SCB_EnableICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+    __DSB();
+    __ISB();
+    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Disable I-Cache
+  \details Turns off I-Cache
+  */
+__STATIC_INLINE void SCB_DisableICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  /* disable I-Cache */
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Invalidate I-Cache
+  \details Invalidates I-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Enable D-Cache
+  \details Turns on D-Cache
+  */
+__STATIC_INLINE void SCB_EnableDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+    __DSB();
+
+    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Disable D-Cache
+  \details Turns off D-Cache
+  */
+__STATIC_INLINE void SCB_DisableDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  /* disable D-Cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean & invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Invalidate D-Cache
+  \details Invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Clean D-Cache
+  \details Cleans D-Cache
+  */
+__STATIC_INLINE void SCB_CleanDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+     SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+   __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
+                      ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Clean & Invalidate D-Cache
+  \details Cleans and Invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean & invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Invalidate by address
+  \details Invalidates D-Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+     int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t)addr;
+     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCIMVAC = op_addr;
+      op_addr += (uint32_t)linesize;
+      op_size -=           linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Clean by address
+  \details Cleans D-Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+     int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t) addr;
+     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCCMVAC = op_addr;
+      op_addr += (uint32_t)linesize;
+      op_size -=           linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Clean and Invalidate by address
+  \details Cleans and invalidates D_Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+     int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t) addr;
+     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCCIMVAC = op_addr;
+      op_addr += (uint32_t)linesize;
+      op_size -=           linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/core_sc000.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/core_sc000.h
new file mode 100644
index 00000000..9086c642
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/core_sc000.h
@@ -0,0 +1,1022 @@
+/**************************************************************************//**
+ * @file     core_sc000.h
+ * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version  V5.0.5
+ * @date     28. May 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup SC000
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                 /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
+                                      __SC000_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_SC                 (000U)                                   /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC000_REV
+    #define __SC000_REV             0x0000U
+    #warning "__SC000_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+        uint32_t RESERVED1[154U];
+  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the SC000 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for SC000 */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for SC000 */
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for SC000 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/core_sc300.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/core_sc300.h
new file mode 100644
index 00000000..665822da
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/core_sc300.h
@@ -0,0 +1,1915 @@
+/**************************************************************************//**
+ * @file     core_sc300.h
+ * @brief    CMSIS SC300 Core Peripheral Access Layer Header File
+ * @version  V5.0.6
+ * @date     04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup SC3000
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                 /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
+                                      __SC300_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_SC                 (300U)                                   /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC300_H_DEPENDANT
+#define __CORE_SC300_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC300_REV
+    #define __SC300_REV               0x0000U
+    #warning "__SC300_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+        uint32_t RESERVED1[129U];
+  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+        uint32_t RESERVED1[1U];
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/mpu_armv7.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/mpu_armv7.h
new file mode 100644
index 00000000..7d4b600c
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/mpu_armv7.h
@@ -0,0 +1,270 @@
+/******************************************************************************
+ * @file     mpu_armv7.h
+ * @brief    CMSIS MPU API for Armv7-M MPU
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+ 
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
+#define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
+#define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
+#define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
+#define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
+#define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
+#define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
+#define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
+#define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
+#define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
+#define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
+#define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
+#define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
+#define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
+#define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
+#define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
+#define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
+#define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
+#define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
+#define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
+#define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
+#define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
+#define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
+#define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
+#define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
+#define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
+#define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
+#define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
+
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
+#define ARM_MPU_AP_URO  2U ///!< MPU Access Permission unprivileged access read-only
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
+#define ARM_MPU_AP_PRO  5U ///!< MPU Access Permission privileged access read-only
+#define ARM_MPU_AP_RO   6U ///!< MPU Access Permission read-only access
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+  (((BaseAddress) & MPU_RBAR_ADDR_Msk) |  \
+   ((Region) & MPU_RBAR_REGION_Msk)    |  \
+   (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Memory Access Attributes
+* 
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+*/  
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)   \
+  ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk)                 | \
+   (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk)                      | \
+   (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk)                      | \
+   (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param AccessAttributes  Memory access attribution, see \ref ARM_MPU_ACCESS_.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)      \
+  ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk)                                          | \
+   (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)                                      | \
+   (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
+  
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/                         
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+  ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
+
+/**
+* MPU Memory Access Attribute for strongly ordered memory.
+*  - TEX: 000b
+*  - Shareable
+*  - Non-cacheable
+*  - Non-bufferable
+*/ 
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
+
+/**
+* MPU Memory Access Attribute for device memory.
+*  - TEX: 000b (if non-shareable) or 010b (if shareable)
+*  - Shareable or non-shareable
+*  - Non-cacheable
+*  - Bufferable (if shareable) or non-bufferable (if non-shareable)
+*
+* \param IsShareable Configures the device memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
+
+/**
+* MPU Memory Access Attribute for normal memory.
+*  - TEX: 1BBb (reflecting outer cacheability rules)
+*  - Shareable or non-shareable
+*  - Cacheable or non-cacheable (reflecting inner cacheability rules)
+*  - Bufferable or non-bufferable (reflecting inner cacheability rules)
+*
+* \param OuterCp Configures the outer cache policy.
+* \param InnerCp Configures the inner cache policy.
+* \param IsShareable Configures the memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
+
+/**
+* MPU Memory Access Attribute non-cacheable policy.
+*/
+#define ARM_MPU_CACHEP_NOCACHE 0U
+
+/**
+* MPU Memory Access Attribute write-back, write and read allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_WRA 1U
+
+/**
+* MPU Memory Access Attribute write-through, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WT_NWA 2U
+
+/**
+* MPU Memory Access Attribute write-back, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_NWA 3U
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR; //!< The region base address register value (RBAR)
+  uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  MPU->RNR = rnr;
+  MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+  MPU->RNR = rnr;
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  while (cnt > MPU_TYPE_RALIASES) {
+    orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+    table += MPU_TYPE_RALIASES;
+    cnt -= MPU_TYPE_RALIASES;
+  }
+  orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/mpu_armv8.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/mpu_armv8.h
new file mode 100644
index 00000000..99ee9f99
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/mpu_armv8.h
@@ -0,0 +1,333 @@
+/******************************************************************************
+ * @file     mpu_armv8.h
+ * @brief    CMSIS MPU API for Armv8-M MPU
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV8_H
+#define ARM_MPU_ARMV8_H
+
+/** \brief Attribute for device memory (outer only) */
+#define ARM_MPU_ATTR_DEVICE                           ( 0U )
+
+/** \brief Attribute for non-cacheable, normal memory */
+#define ARM_MPU_ATTR_NON_CACHEABLE                    ( 4U )
+
+/** \brief Attribute for normal memory (outer and inner)
+* \param NT Non-Transient: Set to 1 for non-transient data.
+* \param WB Write-Back: Set to 1 to use write-back update policy.
+* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
+* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
+*/
+#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
+  (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
+
+/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
+
+/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRE  (1U)
+
+/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGRE   (2U)
+
+/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_GRE    (3U)
+
+/** \brief Memory Attribute
+* \param O Outer memory attributes
+* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
+*/
+#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
+
+/** \brief Normal memory non-shareable  */
+#define ARM_MPU_SH_NON   (0U)
+
+/** \brief Normal memory outer shareable  */
+#define ARM_MPU_SH_OUTER (2U)
+
+/** \brief Normal memory inner shareable  */
+#define ARM_MPU_SH_INNER (3U)
+
+/** \brief Memory access permissions
+* \param RO Read-Only: Set to 1 for read-only memory.
+* \param NP Non-Privileged: Set to 1 for non-privileged memory.
+*/
+#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
+
+/** \brief Region Base Address Register value
+* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
+* \param SH Defines the Shareability domain for this memory region.
+* \param RO Read-Only: Set to 1 for a read-only memory region.
+* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
+* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
+*/
+#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
+  ((BASE & MPU_RBAR_BASE_Msk) | \
+  ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
+  ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
+  ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
+
+/** \brief Region Limit Address Register value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR(LIMIT, IDX) \
+  ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
+  ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+  (MPU_RLAR_EN_Msk))
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR;                   /*!< Region Base Address Register value */
+  uint32_t RLAR;                   /*!< Region Limit Address Register value */
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+#ifdef MPU_NS
+/** Enable the Non-secure MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the Non-secure MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable_NS(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU_NS->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+#endif
+
+/** Set the memory attribute encoding to the given MPU.
+* \param mpu Pointer to the MPU to be configured.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
+{
+  const uint8_t reg = idx / 4U;
+  const uint32_t pos = ((idx % 4U) * 8U);
+  const uint32_t mask = 0xFFU << pos;
+  
+  if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
+    return; // invalid index
+  }
+  
+  mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
+}
+
+/** Set the memory attribute encoding.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU, idx, attr);
+}
+
+#ifdef MPU_NS
+/** Set the memory attribute encoding to the Non-secure MPU.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
+}
+#endif
+
+/** Clear and disable the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
+{
+  mpu->RNR = rnr;
+  mpu->RLAR = 0U;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  ARM_MPU_ClrRegionEx(MPU, rnr);
+}
+
+#ifdef MPU_NS
+/** Clear and disable the given Non-secure MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
+{  
+  ARM_MPU_ClrRegionEx(MPU_NS, rnr);
+}
+#endif
+
+/** Configure the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  mpu->RNR = rnr;
+  mpu->RBAR = rbar;
+  mpu->RLAR = rlar;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
+}
+
+#ifdef MPU_NS
+/** Configure the given Non-secure MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);  
+}
+#endif
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table to the given MPU.
+* \param mpu Pointer to the MPU registers to be used.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  if (cnt == 1U) {
+    mpu->RNR = rnr;
+    orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
+  } else {
+    uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);
+    uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
+    
+    mpu->RNR = rnrBase;
+    while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
+      uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
+      orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
+      table += c;
+      cnt -= c;
+      rnrOffset = 0U;
+      rnrBase += MPU_TYPE_RALIASES;
+      mpu->RNR = rnrBase;
+    }
+    
+    orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU, rnr, table, cnt);
+}
+
+#ifdef MPU_NS
+/** Load the given number of MPU regions from a table to the Non-secure MPU.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
+}
+#endif
+
+#endif
+
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/tz_context.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/tz_context.h
new file mode 100644
index 00000000..d4c1474f
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/CMSIS/Include/tz_context.h
@@ -0,0 +1,70 @@
+/******************************************************************************
+ * @file     tz_context.h
+ * @brief    Context Management for Armv8-M TrustZone
+ * @version  V1.0.1
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef TZ_CONTEXT_H
+#define TZ_CONTEXT_H
+ 
+#include <stdint.h>
+ 
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+ 
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+  
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+ 
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in]  module   identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0    no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+ 
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+ 
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+ 
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+ 
+#endif  // TZ_CONTEXT_H
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
new file mode 100644
index 00000000..7b859e37
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
@@ -0,0 +1,3775 @@
+/**
+  ******************************************************************************
+  * @file    stm32_hal_legacy.h
+  * @author  MCD Application Team
+  * @brief   This file contains aliases definition for the STM32Cube HAL constants
+  *          macros and functions maintained for legacy purpose.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32_HAL_LEGACY
+#define STM32_HAL_LEGACY
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define AES_FLAG_RDERR                  CRYP_FLAG_RDERR
+#define AES_FLAG_WRERR                  CRYP_FLAG_WRERR
+#define AES_CLEARFLAG_CCF               CRYP_CLEARFLAG_CCF
+#define AES_CLEARFLAG_RDERR             CRYP_CLEARFLAG_RDERR
+#define AES_CLEARFLAG_WRERR             CRYP_CLEARFLAG_WRERR
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define ADC_RESOLUTION12b               ADC_RESOLUTION_12B
+#define ADC_RESOLUTION10b               ADC_RESOLUTION_10B
+#define ADC_RESOLUTION8b                ADC_RESOLUTION_8B
+#define ADC_RESOLUTION6b                ADC_RESOLUTION_6B
+#define OVR_DATA_OVERWRITTEN            ADC_OVR_DATA_OVERWRITTEN
+#define OVR_DATA_PRESERVED              ADC_OVR_DATA_PRESERVED
+#define EOC_SINGLE_CONV                 ADC_EOC_SINGLE_CONV
+#define EOC_SEQ_CONV                    ADC_EOC_SEQ_CONV
+#define EOC_SINGLE_SEQ_CONV             ADC_EOC_SINGLE_SEQ_CONV
+#define REGULAR_GROUP                   ADC_REGULAR_GROUP
+#define INJECTED_GROUP                  ADC_INJECTED_GROUP
+#define REGULAR_INJECTED_GROUP          ADC_REGULAR_INJECTED_GROUP
+#define AWD_EVENT                       ADC_AWD_EVENT
+#define AWD1_EVENT                      ADC_AWD1_EVENT
+#define AWD2_EVENT                      ADC_AWD2_EVENT
+#define AWD3_EVENT                      ADC_AWD3_EVENT
+#define OVR_EVENT                       ADC_OVR_EVENT
+#define JQOVF_EVENT                     ADC_JQOVF_EVENT
+#define ALL_CHANNELS                    ADC_ALL_CHANNELS
+#define REGULAR_CHANNELS                ADC_REGULAR_CHANNELS
+#define INJECTED_CHANNELS               ADC_INJECTED_CHANNELS
+#define SYSCFG_FLAG_SENSOR_ADC          ADC_FLAG_SENSOR
+#define SYSCFG_FLAG_VREF_ADC            ADC_FLAG_VREFINT
+#define ADC_CLOCKPRESCALER_PCLK_DIV1    ADC_CLOCK_SYNC_PCLK_DIV1
+#define ADC_CLOCKPRESCALER_PCLK_DIV2    ADC_CLOCK_SYNC_PCLK_DIV2
+#define ADC_CLOCKPRESCALER_PCLK_DIV4    ADC_CLOCK_SYNC_PCLK_DIV4
+#define ADC_CLOCKPRESCALER_PCLK_DIV6    ADC_CLOCK_SYNC_PCLK_DIV6
+#define ADC_CLOCKPRESCALER_PCLK_DIV8    ADC_CLOCK_SYNC_PCLK_DIV8
+#define ADC_EXTERNALTRIG0_T6_TRGO       ADC_EXTERNALTRIGCONV_T6_TRGO
+#define ADC_EXTERNALTRIG1_T21_CC2       ADC_EXTERNALTRIGCONV_T21_CC2
+#define ADC_EXTERNALTRIG2_T2_TRGO       ADC_EXTERNALTRIGCONV_T2_TRGO
+#define ADC_EXTERNALTRIG3_T2_CC4        ADC_EXTERNALTRIGCONV_T2_CC4
+#define ADC_EXTERNALTRIG4_T22_TRGO      ADC_EXTERNALTRIGCONV_T22_TRGO
+#define ADC_EXTERNALTRIG7_EXT_IT11      ADC_EXTERNALTRIGCONV_EXT_IT11
+#define ADC_CLOCK_ASYNC                 ADC_CLOCK_ASYNC_DIV1
+#define ADC_EXTERNALTRIG_EDGE_NONE      ADC_EXTERNALTRIGCONVEDGE_NONE
+#define ADC_EXTERNALTRIG_EDGE_RISING    ADC_EXTERNALTRIGCONVEDGE_RISING
+#define ADC_EXTERNALTRIG_EDGE_FALLING   ADC_EXTERNALTRIGCONVEDGE_FALLING
+#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
+#define ADC_SAMPLETIME_2CYCLE_5         ADC_SAMPLETIME_2CYCLES_5
+
+#define HAL_ADC_STATE_BUSY_REG          HAL_ADC_STATE_REG_BUSY
+#define HAL_ADC_STATE_BUSY_INJ          HAL_ADC_STATE_INJ_BUSY
+#define HAL_ADC_STATE_EOC_REG           HAL_ADC_STATE_REG_EOC
+#define HAL_ADC_STATE_EOC_INJ           HAL_ADC_STATE_INJ_EOC
+#define HAL_ADC_STATE_ERROR             HAL_ADC_STATE_ERROR_INTERNAL
+#define HAL_ADC_STATE_BUSY              HAL_ADC_STATE_BUSY_INTERNAL
+#define HAL_ADC_STATE_AWD               HAL_ADC_STATE_AWD1
+
+#if defined(STM32H7)
+#define ADC_CHANNEL_VBAT_DIV4           ADC_CHANNEL_VBAT
+#endif /* STM32H7 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define COMP_WINDOWMODE_DISABLED       COMP_WINDOWMODE_DISABLE
+#define COMP_WINDOWMODE_ENABLED        COMP_WINDOWMODE_ENABLE
+#define COMP_EXTI_LINE_COMP1_EVENT     COMP_EXTI_LINE_COMP1
+#define COMP_EXTI_LINE_COMP2_EVENT     COMP_EXTI_LINE_COMP2
+#define COMP_EXTI_LINE_COMP3_EVENT     COMP_EXTI_LINE_COMP3
+#define COMP_EXTI_LINE_COMP4_EVENT     COMP_EXTI_LINE_COMP4
+#define COMP_EXTI_LINE_COMP5_EVENT     COMP_EXTI_LINE_COMP5
+#define COMP_EXTI_LINE_COMP6_EVENT     COMP_EXTI_LINE_COMP6
+#define COMP_EXTI_LINE_COMP7_EVENT     COMP_EXTI_LINE_COMP7
+#if defined(STM32L0)
+#define COMP_LPTIMCONNECTION_ENABLED   ((uint32_t)0x00000003U)    /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
+#endif
+#define COMP_OUTPUT_COMP6TIM2OCREFCLR  COMP_OUTPUT_COMP6_TIM2OCREFCLR
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define COMP_OUTPUT_TIM3IC1            COMP_OUTPUT_COMP1_TIM3IC1
+#define COMP_OUTPUT_TIM3OCREFCLR       COMP_OUTPUT_COMP1_TIM3OCREFCLR
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32L0) || defined(STM32L4)
+#define COMP_WINDOWMODE_ENABLE         COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
+
+#define COMP_NONINVERTINGINPUT_IO1      COMP_INPUT_PLUS_IO1
+#define COMP_NONINVERTINGINPUT_IO2      COMP_INPUT_PLUS_IO2
+#define COMP_NONINVERTINGINPUT_IO3      COMP_INPUT_PLUS_IO3
+#define COMP_NONINVERTINGINPUT_IO4      COMP_INPUT_PLUS_IO4
+#define COMP_NONINVERTINGINPUT_IO5      COMP_INPUT_PLUS_IO5
+#define COMP_NONINVERTINGINPUT_IO6      COMP_INPUT_PLUS_IO6
+
+#define COMP_INVERTINGINPUT_1_4VREFINT  COMP_INPUT_MINUS_1_4VREFINT
+#define COMP_INVERTINGINPUT_1_2VREFINT  COMP_INPUT_MINUS_1_2VREFINT
+#define COMP_INVERTINGINPUT_3_4VREFINT  COMP_INPUT_MINUS_3_4VREFINT
+#define COMP_INVERTINGINPUT_VREFINT     COMP_INPUT_MINUS_VREFINT
+#define COMP_INVERTINGINPUT_DAC1_CH1    COMP_INPUT_MINUS_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC1_CH2    COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_DAC1        COMP_INPUT_MINUS_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC2        COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_IO1         COMP_INPUT_MINUS_IO1
+#if defined(STM32L0)
+/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2),     */
+/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding   */
+/* to the second dedicated IO (only for COMP2).                               */
+#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO2
+#else
+#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_IO2
+#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO3
+#endif
+#define COMP_INVERTINGINPUT_IO4         COMP_INPUT_MINUS_IO4
+#define COMP_INVERTINGINPUT_IO5         COMP_INPUT_MINUS_IO5
+
+#define COMP_OUTPUTLEVEL_LOW            COMP_OUTPUT_LEVEL_LOW
+#define COMP_OUTPUTLEVEL_HIGH           COMP_OUTPUT_LEVEL_HIGH
+
+/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose.                    */
+/*       To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()".        */
+#if defined(COMP_CSR_LOCK)
+#define COMP_FLAG_LOCK                 COMP_CSR_LOCK
+#elif defined(COMP_CSR_COMP1LOCK)
+#define COMP_FLAG_LOCK                 COMP_CSR_COMP1LOCK
+#elif defined(COMP_CSR_COMPxLOCK)
+#define COMP_FLAG_LOCK                 COMP_CSR_COMPxLOCK
+#endif
+
+#if defined(STM32L4)
+#define COMP_BLANKINGSRCE_TIM1OC5        COMP_BLANKINGSRC_TIM1_OC5_COMP1
+#define COMP_BLANKINGSRCE_TIM2OC3        COMP_BLANKINGSRC_TIM2_OC3_COMP1
+#define COMP_BLANKINGSRCE_TIM3OC3        COMP_BLANKINGSRC_TIM3_OC3_COMP1
+#define COMP_BLANKINGSRCE_TIM3OC4        COMP_BLANKINGSRC_TIM3_OC4_COMP2
+#define COMP_BLANKINGSRCE_TIM8OC5        COMP_BLANKINGSRC_TIM8_OC5_COMP2
+#define COMP_BLANKINGSRCE_TIM15OC1       COMP_BLANKINGSRC_TIM15_OC1_COMP2
+#define COMP_BLANKINGSRCE_NONE           COMP_BLANKINGSRC_NONE
+#endif
+
+#if defined(STM32L0)
+#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_MEDIUMSPEED
+#define COMP_MODE_LOWSPEED               COMP_POWERMODE_ULTRALOWPOWER
+#else
+#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_HIGHSPEED
+#define COMP_MODE_MEDIUMSPEED            COMP_POWERMODE_MEDIUMSPEED
+#define COMP_MODE_LOWPOWER               COMP_POWERMODE_LOWPOWER
+#define COMP_MODE_ULTRALOWPOWER          COMP_POWERMODE_ULTRALOWPOWER
+#endif
+
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
+/**
+  * @}
+  */
+
+/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define CRC_OUTPUTDATA_INVERSION_DISABLED    CRC_OUTPUTDATA_INVERSION_DISABLE
+#define CRC_OUTPUTDATA_INVERSION_ENABLED     CRC_OUTPUTDATA_INVERSION_ENABLE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define DAC1_CHANNEL_1                                  DAC_CHANNEL_1
+#define DAC1_CHANNEL_2                                  DAC_CHANNEL_2
+#define DAC2_CHANNEL_1                                  DAC_CHANNEL_1
+#define DAC_WAVE_NONE                                   0x00000000U
+#define DAC_WAVE_NOISE                                  DAC_CR_WAVE1_0
+#define DAC_WAVE_TRIANGLE                               DAC_CR_WAVE1_1
+#define DAC_WAVEGENERATION_NONE                         DAC_WAVE_NONE
+#define DAC_WAVEGENERATION_NOISE                        DAC_WAVE_NOISE
+#define DAC_WAVEGENERATION_TRIANGLE                     DAC_WAVE_TRIANGLE
+
+#if defined(STM32G4) || defined(STM32H7)
+#define DAC_CHIPCONNECT_DISABLE       DAC_CHIPCONNECT_EXTERNAL
+#define DAC_CHIPCONNECT_ENABLE        DAC_CHIPCONNECT_INTERNAL
+#endif
+
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
+#define HAL_DAC_MSP_INIT_CB_ID       HAL_DAC_MSPINIT_CB_ID
+#define HAL_DAC_MSP_DEINIT_CB_ID     HAL_DAC_MSPDEINIT_CB_ID
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define HAL_REMAPDMA_ADC_DMA_CH2                DMA_REMAP_ADC_DMA_CH2
+#define HAL_REMAPDMA_USART1_TX_DMA_CH4          DMA_REMAP_USART1_TX_DMA_CH4
+#define HAL_REMAPDMA_USART1_RX_DMA_CH5          DMA_REMAP_USART1_RX_DMA_CH5
+#define HAL_REMAPDMA_TIM16_DMA_CH4              DMA_REMAP_TIM16_DMA_CH4
+#define HAL_REMAPDMA_TIM17_DMA_CH2              DMA_REMAP_TIM17_DMA_CH2
+#define HAL_REMAPDMA_USART3_DMA_CH32            DMA_REMAP_USART3_DMA_CH32
+#define HAL_REMAPDMA_TIM16_DMA_CH6              DMA_REMAP_TIM16_DMA_CH6
+#define HAL_REMAPDMA_TIM17_DMA_CH7              DMA_REMAP_TIM17_DMA_CH7
+#define HAL_REMAPDMA_SPI2_DMA_CH67              DMA_REMAP_SPI2_DMA_CH67
+#define HAL_REMAPDMA_USART2_DMA_CH67            DMA_REMAP_USART2_DMA_CH67
+#define HAL_REMAPDMA_I2C1_DMA_CH76              DMA_REMAP_I2C1_DMA_CH76
+#define HAL_REMAPDMA_TIM1_DMA_CH6               DMA_REMAP_TIM1_DMA_CH6
+#define HAL_REMAPDMA_TIM2_DMA_CH7               DMA_REMAP_TIM2_DMA_CH7
+#define HAL_REMAPDMA_TIM3_DMA_CH6               DMA_REMAP_TIM3_DMA_CH6
+
+#define IS_HAL_REMAPDMA                          IS_DMA_REMAP
+#define __HAL_REMAPDMA_CHANNEL_ENABLE            __HAL_DMA_REMAP_CHANNEL_ENABLE
+#define __HAL_REMAPDMA_CHANNEL_DISABLE           __HAL_DMA_REMAP_CHANNEL_DISABLE
+
+#if defined(STM32L4)
+
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI0            HAL_DMAMUX1_REQ_GEN_EXTI0
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI1            HAL_DMAMUX1_REQ_GEN_EXTI1
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI2            HAL_DMAMUX1_REQ_GEN_EXTI2
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI3            HAL_DMAMUX1_REQ_GEN_EXTI3
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI4            HAL_DMAMUX1_REQ_GEN_EXTI4
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI5            HAL_DMAMUX1_REQ_GEN_EXTI5
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI6            HAL_DMAMUX1_REQ_GEN_EXTI6
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI7            HAL_DMAMUX1_REQ_GEN_EXTI7
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI8            HAL_DMAMUX1_REQ_GEN_EXTI8
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI9            HAL_DMAMUX1_REQ_GEN_EXTI9
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI10           HAL_DMAMUX1_REQ_GEN_EXTI10
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI11           HAL_DMAMUX1_REQ_GEN_EXTI11
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI12           HAL_DMAMUX1_REQ_GEN_EXTI12
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI13           HAL_DMAMUX1_REQ_GEN_EXTI13
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI14           HAL_DMAMUX1_REQ_GEN_EXTI14
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI15           HAL_DMAMUX1_REQ_GEN_EXTI15
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT       HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT       HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE           HAL_DMAMUX1_REQ_GEN_DSI_TE
+#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT          HAL_DMAMUX1_REQ_GEN_DSI_EOT
+#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT        HAL_DMAMUX1_REQ_GEN_DMA2D_EOT
+#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT          HAL_DMAMUX1_REQ_GEN_LTDC_IT
+
+#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT          HAL_DMAMUX_REQ_GEN_NO_EVENT
+#define HAL_DMAMUX_REQUEST_GEN_RISING            HAL_DMAMUX_REQ_GEN_RISING
+#define HAL_DMAMUX_REQUEST_GEN_FALLING           HAL_DMAMUX_REQ_GEN_FALLING
+#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING    HAL_DMAMUX_REQ_GEN_RISING_FALLING
+
+#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+#define DMA_REQUEST_DCMI_PSSI                    DMA_REQUEST_DCMI
+#endif
+
+#endif /* STM32L4 */
+
+#if defined(STM32G0)
+#define DMA_REQUEST_DAC1_CHANNEL1                DMA_REQUEST_DAC1_CH1
+#define DMA_REQUEST_DAC1_CHANNEL2                DMA_REQUEST_DAC1_CH2
+#endif
+
+#if defined(STM32H7)
+
+#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
+#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
+
+#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
+#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
+
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI0              HAL_DMAMUX1_REQ_GEN_EXTI0
+#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO         HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
+
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP          HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP          HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT          HAL_DMAMUX2_REQ_GEN_COMP1_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT          HAL_DMAMUX2_REQ_GEN_COMP2_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP           HAL_DMAMUX2_REQ_GEN_RTC_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_EXTI0              HAL_DMAMUX2_REQ_GEN_EXTI0
+#define HAL_DMAMUX2_REQUEST_GEN_EXTI2              HAL_DMAMUX2_REQ_GEN_EXTI2
+#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT        HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT            HAL_DMAMUX2_REQ_GEN_SPI6_IT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
+#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT            HAL_DMAMUX2_REQ_GEN_ADC3_IT
+#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT      HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
+#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
+
+#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT            HAL_DMAMUX_REQ_GEN_NO_EVENT
+#define HAL_DMAMUX_REQUEST_GEN_RISING              HAL_DMAMUX_REQ_GEN_RISING
+#define HAL_DMAMUX_REQUEST_GEN_FALLING             HAL_DMAMUX_REQ_GEN_FALLING
+#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING      HAL_DMAMUX_REQ_GEN_RISING_FALLING
+
+#define DFSDM_FILTER_EXT_TRIG_LPTIM1               DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT
+#define DFSDM_FILTER_EXT_TRIG_LPTIM2               DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
+#define DFSDM_FILTER_EXT_TRIG_LPTIM3               DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
+
+#define DAC_TRIGGER_LP1_OUT                        DAC_TRIGGER_LPTIM1_OUT
+#define DAC_TRIGGER_LP2_OUT                        DAC_TRIGGER_LPTIM2_OUT
+
+#endif /* STM32H7 */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define TYPEPROGRAM_BYTE              FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_HALFWORD          FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_WORD              FLASH_TYPEPROGRAM_WORD
+#define TYPEPROGRAM_DOUBLEWORD        FLASH_TYPEPROGRAM_DOUBLEWORD
+#define TYPEERASE_SECTORS             FLASH_TYPEERASE_SECTORS
+#define TYPEERASE_PAGES               FLASH_TYPEERASE_PAGES
+#define TYPEERASE_PAGEERASE           FLASH_TYPEERASE_PAGES
+#define TYPEERASE_MASSERASE           FLASH_TYPEERASE_MASSERASE
+#define WRPSTATE_DISABLE              OB_WRPSTATE_DISABLE
+#define WRPSTATE_ENABLE               OB_WRPSTATE_ENABLE
+#define HAL_FLASH_TIMEOUT_VALUE       FLASH_TIMEOUT_VALUE
+#define OBEX_PCROP                    OPTIONBYTE_PCROP
+#define OBEX_BOOTCONFIG               OPTIONBYTE_BOOTCONFIG
+#define PCROPSTATE_DISABLE            OB_PCROP_STATE_DISABLE
+#define PCROPSTATE_ENABLE             OB_PCROP_STATE_ENABLE
+#define TYPEERASEDATA_BYTE            FLASH_TYPEERASEDATA_BYTE
+#define TYPEERASEDATA_HALFWORD        FLASH_TYPEERASEDATA_HALFWORD
+#define TYPEERASEDATA_WORD            FLASH_TYPEERASEDATA_WORD
+#define TYPEPROGRAMDATA_BYTE          FLASH_TYPEPROGRAMDATA_BYTE
+#define TYPEPROGRAMDATA_HALFWORD      FLASH_TYPEPROGRAMDATA_HALFWORD
+#define TYPEPROGRAMDATA_WORD          FLASH_TYPEPROGRAMDATA_WORD
+#define TYPEPROGRAMDATA_FASTBYTE      FLASH_TYPEPROGRAMDATA_FASTBYTE
+#define TYPEPROGRAMDATA_FASTHALFWORD  FLASH_TYPEPROGRAMDATA_FASTHALFWORD
+#define TYPEPROGRAMDATA_FASTWORD      FLASH_TYPEPROGRAMDATA_FASTWORD
+#define PAGESIZE                      FLASH_PAGE_SIZE
+#define TYPEPROGRAM_FASTBYTE          FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_FASTHALFWORD      FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_FASTWORD          FLASH_TYPEPROGRAM_WORD
+#define VOLTAGE_RANGE_1               FLASH_VOLTAGE_RANGE_1
+#define VOLTAGE_RANGE_2               FLASH_VOLTAGE_RANGE_2
+#define VOLTAGE_RANGE_3               FLASH_VOLTAGE_RANGE_3
+#define VOLTAGE_RANGE_4               FLASH_VOLTAGE_RANGE_4
+#define TYPEPROGRAM_FAST              FLASH_TYPEPROGRAM_FAST
+#define TYPEPROGRAM_FAST_AND_LAST     FLASH_TYPEPROGRAM_FAST_AND_LAST
+#define WRPAREA_BANK1_AREAA           OB_WRPAREA_BANK1_AREAA
+#define WRPAREA_BANK1_AREAB           OB_WRPAREA_BANK1_AREAB
+#define WRPAREA_BANK2_AREAA           OB_WRPAREA_BANK2_AREAA
+#define WRPAREA_BANK2_AREAB           OB_WRPAREA_BANK2_AREAB
+#define IWDG_STDBY_FREEZE             OB_IWDG_STDBY_FREEZE
+#define IWDG_STDBY_ACTIVE             OB_IWDG_STDBY_RUN
+#define IWDG_STOP_FREEZE              OB_IWDG_STOP_FREEZE
+#define IWDG_STOP_ACTIVE              OB_IWDG_STOP_RUN
+#define FLASH_ERROR_NONE              HAL_FLASH_ERROR_NONE
+#define FLASH_ERROR_RD                HAL_FLASH_ERROR_RD
+#define FLASH_ERROR_PG                HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_PGP               HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_WRP               HAL_FLASH_ERROR_WRP
+#define FLASH_ERROR_OPTV              HAL_FLASH_ERROR_OPTV
+#define FLASH_ERROR_OPTVUSR           HAL_FLASH_ERROR_OPTVUSR
+#define FLASH_ERROR_PROG              HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_OP                HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_PGA               HAL_FLASH_ERROR_PGA
+#define FLASH_ERROR_SIZE              HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_SIZ               HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_PGS               HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_MIS               HAL_FLASH_ERROR_MIS
+#define FLASH_ERROR_FAST              HAL_FLASH_ERROR_FAST
+#define FLASH_ERROR_FWWERR            HAL_FLASH_ERROR_FWWERR
+#define FLASH_ERROR_NOTZERO           HAL_FLASH_ERROR_NOTZERO
+#define FLASH_ERROR_OPERATION         HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_ERS               HAL_FLASH_ERROR_ERS
+#define OB_WDG_SW                     OB_IWDG_SW
+#define OB_WDG_HW                     OB_IWDG_HW
+#define OB_SDADC12_VDD_MONITOR_SET    OB_SDACD_VDD_MONITOR_SET
+#define OB_SDADC12_VDD_MONITOR_RESET  OB_SDACD_VDD_MONITOR_RESET
+#define OB_RAM_PARITY_CHECK_SET       OB_SRAM_PARITY_SET
+#define OB_RAM_PARITY_CHECK_RESET     OB_SRAM_PARITY_RESET
+#define IS_OB_SDADC12_VDD_MONITOR     IS_OB_SDACD_VDD_MONITOR
+#define OB_RDP_LEVEL0                 OB_RDP_LEVEL_0
+#define OB_RDP_LEVEL1                 OB_RDP_LEVEL_1
+#define OB_RDP_LEVEL2                 OB_RDP_LEVEL_2
+#if defined(STM32G0)
+#define OB_BOOT_LOCK_DISABLE          OB_BOOT_ENTRY_FORCED_NONE
+#define OB_BOOT_LOCK_ENABLE           OB_BOOT_ENTRY_FORCED_FLASH
+#else
+#define OB_BOOT_ENTRY_FORCED_NONE     OB_BOOT_LOCK_DISABLE
+#define OB_BOOT_ENTRY_FORCED_FLASH    OB_BOOT_LOCK_ENABLE
+#endif
+#if defined(STM32H7)
+#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1
+#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1
+#define FLASH_FLAG_STRBER_BANK1R  FLASH_FLAG_STRBERR_BANK1
+#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
+#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
+#define FLASH_FLAG_STRBER_BANK2R  FLASH_FLAG_STRBERR_BANK2
+#define FLASH_FLAG_WDW            FLASH_FLAG_WBNE
+#define OB_WRP_SECTOR_All         OB_WRP_SECTOR_ALL
+#endif /* STM32H7 */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#if defined(STM32H7)
+#define __HAL_RCC_JPEG_CLK_ENABLE               __HAL_RCC_JPGDECEN_CLK_ENABLE
+#define __HAL_RCC_JPEG_CLK_DISABLE              __HAL_RCC_JPGDECEN_CLK_DISABLE
+#define __HAL_RCC_JPEG_FORCE_RESET              __HAL_RCC_JPGDECRST_FORCE_RESET
+#define __HAL_RCC_JPEG_RELEASE_RESET            __HAL_RCC_JPGDECRST_RELEASE_RESET
+#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE         __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
+#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE        __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
+#endif /* STM32H7 */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9    I2C_FASTMODEPLUS_PA9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10   I2C_FASTMODEPLUS_PA10
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6    I2C_FASTMODEPLUS_PB6
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7    I2C_FASTMODEPLUS_PB7
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8    I2C_FASTMODEPLUS_PB8
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9    I2C_FASTMODEPLUS_PB9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C1       I2C_FASTMODEPLUS_I2C1
+#define HAL_SYSCFG_FASTMODEPLUS_I2C2       I2C_FASTMODEPLUS_I2C2
+#define HAL_SYSCFG_FASTMODEPLUS_I2C3       I2C_FASTMODEPLUS_I2C3
+#if defined(STM32G4)
+
+#define HAL_SYSCFG_EnableIOAnalogSwitchBooster    HAL_SYSCFG_EnableIOSwitchBooster
+#define HAL_SYSCFG_DisableIOAnalogSwitchBooster   HAL_SYSCFG_DisableIOSwitchBooster
+#define HAL_SYSCFG_EnableIOAnalogSwitchVDD        HAL_SYSCFG_EnableIOSwitchVDD
+#define HAL_SYSCFG_DisableIOAnalogSwitchVDD       HAL_SYSCFG_DisableIOSwitchVDD
+#endif /* STM32G4 */
+/**
+  * @}
+  */
+
+
+/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
+  * @{
+  */
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
+#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE       FMC_NAND_WAIT_FEATURE_DISABLE
+#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE        FMC_NAND_WAIT_FEATURE_ENABLE
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_8            FMC_NAND_MEM_BUS_WIDTH_8
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_16           FMC_NAND_MEM_BUS_WIDTH_16
+#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4)
+#define FMC_NAND_WAIT_FEATURE_DISABLE           FMC_NAND_PCC_WAIT_FEATURE_DISABLE
+#define FMC_NAND_WAIT_FEATURE_ENABLE            FMC_NAND_PCC_WAIT_FEATURE_ENABLE
+#define FMC_NAND_MEM_BUS_WIDTH_8                FMC_NAND_PCC_MEM_BUS_WIDTH_8
+#define FMC_NAND_MEM_BUS_WIDTH_16               FMC_NAND_PCC_MEM_BUS_WIDTH_16
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define FSMC_NORSRAM_TYPEDEF                      FSMC_NORSRAM_TypeDef
+#define FSMC_NORSRAM_EXTENDED_TYPEDEF             FSMC_NORSRAM_EXTENDED_TypeDef
+/**
+  * @}
+  */
+
+/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define GET_GPIO_SOURCE                           GPIO_GET_INDEX
+#define GET_GPIO_INDEX                            GPIO_GET_INDEX
+
+#if defined(STM32F4)
+#define GPIO_AF12_SDMMC                           GPIO_AF12_SDIO
+#define GPIO_AF12_SDMMC1                          GPIO_AF12_SDIO
+#endif
+
+#if defined(STM32F7)
+#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1
+#endif
+
+#if defined(STM32L4)
+#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1
+#endif
+
+#if defined(STM32H7)
+#define GPIO_AF7_SDIO1                            GPIO_AF7_SDMMC1
+#define GPIO_AF8_SDIO1                            GPIO_AF8_SDMMC1
+#define GPIO_AF12_SDIO1                           GPIO_AF12_SDMMC1
+#define GPIO_AF9_SDIO2                            GPIO_AF9_SDMMC2
+#define GPIO_AF10_SDIO2                           GPIO_AF10_SDMMC2
+#define GPIO_AF11_SDIO2                           GPIO_AF11_SDMMC2
+
+#if defined (STM32H743xx) || defined (STM32H753xx)  || defined (STM32H750xx) || defined (STM32H742xx) || \
+    defined (STM32H745xx) || defined (STM32H755xx)  || defined (STM32H747xx) || defined (STM32H757xx)
+#define GPIO_AF10_OTG2_HS  GPIO_AF10_OTG2_FS
+#define GPIO_AF10_OTG1_FS  GPIO_AF10_OTG1_HS
+#define GPIO_AF12_OTG2_FS  GPIO_AF12_OTG1_FS
+#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
+#endif /* STM32H7 */
+
+#define GPIO_AF0_LPTIM                            GPIO_AF0_LPTIM1
+#define GPIO_AF1_LPTIM                            GPIO_AF1_LPTIM1
+#define GPIO_AF2_LPTIM                            GPIO_AF2_LPTIM1
+
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7)
+#define  GPIO_SPEED_LOW                           GPIO_SPEED_FREQ_LOW
+#define  GPIO_SPEED_MEDIUM                        GPIO_SPEED_FREQ_MEDIUM
+#define  GPIO_SPEED_FAST                          GPIO_SPEED_FREQ_HIGH
+#define  GPIO_SPEED_HIGH                          GPIO_SPEED_FREQ_VERY_HIGH
+#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/
+
+#if defined(STM32L1)
+ #define  GPIO_SPEED_VERY_LOW    GPIO_SPEED_FREQ_LOW
+ #define  GPIO_SPEED_LOW         GPIO_SPEED_FREQ_MEDIUM
+ #define  GPIO_SPEED_MEDIUM      GPIO_SPEED_FREQ_HIGH
+ #define  GPIO_SPEED_HIGH        GPIO_SPEED_FREQ_VERY_HIGH
+#endif /* STM32L1 */
+
+#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
+ #define  GPIO_SPEED_LOW    GPIO_SPEED_FREQ_LOW
+ #define  GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
+ #define  GPIO_SPEED_HIGH   GPIO_SPEED_FREQ_HIGH
+#endif /* STM32F0 || STM32F3 || STM32F1 */
+
+#define GPIO_AF6_DFSDM                            GPIO_AF6_DFSDM1
+/**
+  * @}
+  */
+
+/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define HRTIM_TIMDELAYEDPROTECTION_DISABLED           HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
+
+#define __HAL_HRTIM_SetCounter        __HAL_HRTIM_SETCOUNTER
+#define __HAL_HRTIM_GetCounter        __HAL_HRTIM_GETCOUNTER
+#define __HAL_HRTIM_SetPeriod         __HAL_HRTIM_SETPERIOD
+#define __HAL_HRTIM_GetPeriod         __HAL_HRTIM_GETPERIOD
+#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
+#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
+#define __HAL_HRTIM_SetCompare        __HAL_HRTIM_SETCOMPARE
+#define __HAL_HRTIM_GetCompare        __HAL_HRTIM_GETCOMPARE
+
+#if defined(STM32G4)
+#define HAL_HRTIM_ExternalEventCounterConfig    HAL_HRTIM_ExtEventCounterConfig
+#define HAL_HRTIM_ExternalEventCounterEnable    HAL_HRTIM_ExtEventCounterEnable
+#define HAL_HRTIM_ExternalEventCounterDisable   HAL_HRTIM_ExtEventCounterDisable
+#define HAL_HRTIM_ExternalEventCounterReset     HAL_HRTIM_ExtEventCounterReset
+#endif /* STM32G4 */
+
+#if defined(STM32H7)
+#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
+
+#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
+#endif /* STM32H7 */
+
+#if defined(STM32F3)
+/** @brief Constants defining available sources associated to external events.
+  */
+#define HRTIM_EVENTSRC_1              (0x00000000U)
+#define HRTIM_EVENTSRC_2              (HRTIM_EECR1_EE1SRC_0)
+#define HRTIM_EVENTSRC_3              (HRTIM_EECR1_EE1SRC_1)
+#define HRTIM_EVENTSRC_4              (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
+
+/** @brief Constants defining the events that can be selected to configure the
+  *        set/reset crossbar of a timer output
+  */
+#define HRTIM_OUTPUTSET_TIMEV_1       (HRTIM_SET1R_TIMEVNT1)
+#define HRTIM_OUTPUTSET_TIMEV_2       (HRTIM_SET1R_TIMEVNT2)
+#define HRTIM_OUTPUTSET_TIMEV_3       (HRTIM_SET1R_TIMEVNT3)
+#define HRTIM_OUTPUTSET_TIMEV_4       (HRTIM_SET1R_TIMEVNT4)
+#define HRTIM_OUTPUTSET_TIMEV_5       (HRTIM_SET1R_TIMEVNT5)
+#define HRTIM_OUTPUTSET_TIMEV_6       (HRTIM_SET1R_TIMEVNT6)
+#define HRTIM_OUTPUTSET_TIMEV_7       (HRTIM_SET1R_TIMEVNT7)
+#define HRTIM_OUTPUTSET_TIMEV_8       (HRTIM_SET1R_TIMEVNT8)
+#define HRTIM_OUTPUTSET_TIMEV_9       (HRTIM_SET1R_TIMEVNT9)
+
+#define HRTIM_OUTPUTRESET_TIMEV_1     (HRTIM_RST1R_TIMEVNT1)
+#define HRTIM_OUTPUTRESET_TIMEV_2     (HRTIM_RST1R_TIMEVNT2)
+#define HRTIM_OUTPUTRESET_TIMEV_3     (HRTIM_RST1R_TIMEVNT3)
+#define HRTIM_OUTPUTRESET_TIMEV_4     (HRTIM_RST1R_TIMEVNT4)
+#define HRTIM_OUTPUTRESET_TIMEV_5     (HRTIM_RST1R_TIMEVNT5)
+#define HRTIM_OUTPUTRESET_TIMEV_6     (HRTIM_RST1R_TIMEVNT6)
+#define HRTIM_OUTPUTRESET_TIMEV_7     (HRTIM_RST1R_TIMEVNT7)
+#define HRTIM_OUTPUTRESET_TIMEV_8     (HRTIM_RST1R_TIMEVNT8)
+#define HRTIM_OUTPUTRESET_TIMEV_9     (HRTIM_RST1R_TIMEVNT9)
+
+/** @brief Constants defining the event filtering applied to external events
+  *        by a timer
+  */
+#define HRTIM_TIMEVENTFILTER_NONE             (0x00000000U)
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1     (HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2     (HRTIM_EEFR1_EE1FLTR_1)
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3     (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4     (HRTIM_EEFR1_EE1FLTR_2)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4    (HRTIM_EEFR1_EE1FLTR_3)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)
+#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
+#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM     (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
+
+/** @brief Constants defining the DLL calibration periods (in micro seconds)
+  */
+#define HRTIM_CALIBRATIONRATE_7300             0x00000000U
+#define HRTIM_CALIBRATIONRATE_910              (HRTIM_DLLCR_CALRTE_0)
+#define HRTIM_CALIBRATIONRATE_114              (HRTIM_DLLCR_CALRTE_1)
+#define HRTIM_CALIBRATIONRATE_14               (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
+
+#endif /* STM32F3 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define I2C_DUALADDRESS_DISABLED                I2C_DUALADDRESS_DISABLE
+#define I2C_DUALADDRESS_ENABLED                 I2C_DUALADDRESS_ENABLE
+#define I2C_GENERALCALL_DISABLED                I2C_GENERALCALL_DISABLE
+#define I2C_GENERALCALL_ENABLED                 I2C_GENERALCALL_ENABLE
+#define I2C_NOSTRETCH_DISABLED                  I2C_NOSTRETCH_DISABLE
+#define I2C_NOSTRETCH_ENABLED                   I2C_NOSTRETCH_ENABLE
+#define I2C_ANALOGFILTER_ENABLED                I2C_ANALOGFILTER_ENABLE
+#define I2C_ANALOGFILTER_DISABLED               I2C_ANALOGFILTER_DISABLE
+#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
+#define HAL_I2C_STATE_MEM_BUSY_TX               HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_MEM_BUSY_RX               HAL_I2C_STATE_BUSY_RX
+#define HAL_I2C_STATE_MASTER_BUSY_TX            HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_MASTER_BUSY_RX            HAL_I2C_STATE_BUSY_RX
+#define HAL_I2C_STATE_SLAVE_BUSY_TX             HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_SLAVE_BUSY_RX             HAL_I2C_STATE_BUSY_RX
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define IRDA_ONE_BIT_SAMPLE_DISABLED            IRDA_ONE_BIT_SAMPLE_DISABLE
+#define IRDA_ONE_BIT_SAMPLE_ENABLED             IRDA_ONE_BIT_SAMPLE_ENABLE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define KR_KEY_RELOAD                   IWDG_KEY_RELOAD
+#define KR_KEY_ENABLE                   IWDG_KEY_ENABLE
+#define KR_KEY_EWA                      IWDG_KEY_WRITE_ACCESS_ENABLE
+#define KR_KEY_DWA                      IWDG_KEY_WRITE_ACCESS_DISABLE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
+
+#define LPTIM_CLOCKPOLARITY_RISINGEDGE          LPTIM_CLOCKPOLARITY_RISING
+#define LPTIM_CLOCKPOLARITY_FALLINGEDGE         LPTIM_CLOCKPOLARITY_FALLING
+#define LPTIM_CLOCKPOLARITY_BOTHEDGES           LPTIM_CLOCKPOLARITY_RISING_FALLING
+
+#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION  LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS      LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS      LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS      LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+/* The following 3 definition have also been present in a temporary version of lptim.h */
+/* They need to be renamed also to the right name, just in case */
+#define LPTIM_TRIGSAMPLETIME_2TRANSITION        LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSITION        LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSITION        LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define HAL_NAND_Read_Page              HAL_NAND_Read_Page_8b
+#define HAL_NAND_Write_Page             HAL_NAND_Write_Page_8b
+#define HAL_NAND_Read_SpareArea         HAL_NAND_Read_SpareArea_8b
+#define HAL_NAND_Write_SpareArea        HAL_NAND_Write_SpareArea_8b
+
+#define NAND_AddressTypedef             NAND_AddressTypeDef
+
+#define __ARRAY_ADDRESS                 ARRAY_ADDRESS
+#define __ADDR_1st_CYCLE                ADDR_1ST_CYCLE
+#define __ADDR_2nd_CYCLE                ADDR_2ND_CYCLE
+#define __ADDR_3rd_CYCLE                ADDR_3RD_CYCLE
+#define __ADDR_4th_CYCLE                ADDR_4TH_CYCLE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define NOR_StatusTypedef              HAL_NOR_StatusTypeDef
+#define NOR_SUCCESS                    HAL_NOR_STATUS_SUCCESS
+#define NOR_ONGOING                    HAL_NOR_STATUS_ONGOING
+#define NOR_ERROR                      HAL_NOR_STATUS_ERROR
+#define NOR_TIMEOUT                    HAL_NOR_STATUS_TIMEOUT
+
+#define __NOR_WRITE                    NOR_WRITE
+#define __NOR_ADDR_SHIFT               NOR_ADDR_SHIFT
+/**
+  * @}
+  */
+
+/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define OPAMP_NONINVERTINGINPUT_VP0           OPAMP_NONINVERTINGINPUT_IO0
+#define OPAMP_NONINVERTINGINPUT_VP1           OPAMP_NONINVERTINGINPUT_IO1
+#define OPAMP_NONINVERTINGINPUT_VP2           OPAMP_NONINVERTINGINPUT_IO2
+#define OPAMP_NONINVERTINGINPUT_VP3           OPAMP_NONINVERTINGINPUT_IO3
+
+#define OPAMP_SEC_NONINVERTINGINPUT_VP0       OPAMP_SEC_NONINVERTINGINPUT_IO0
+#define OPAMP_SEC_NONINVERTINGINPUT_VP1       OPAMP_SEC_NONINVERTINGINPUT_IO1
+#define OPAMP_SEC_NONINVERTINGINPUT_VP2       OPAMP_SEC_NONINVERTINGINPUT_IO2
+#define OPAMP_SEC_NONINVERTINGINPUT_VP3       OPAMP_SEC_NONINVERTINGINPUT_IO3
+
+#define OPAMP_INVERTINGINPUT_VM0              OPAMP_INVERTINGINPUT_IO0
+#define OPAMP_INVERTINGINPUT_VM1              OPAMP_INVERTINGINPUT_IO1
+
+#define IOPAMP_INVERTINGINPUT_VM0             OPAMP_INVERTINGINPUT_IO0
+#define IOPAMP_INVERTINGINPUT_VM1             OPAMP_INVERTINGINPUT_IO1
+
+#define OPAMP_SEC_INVERTINGINPUT_VM0          OPAMP_SEC_INVERTINGINPUT_IO0
+#define OPAMP_SEC_INVERTINGINPUT_VM1          OPAMP_SEC_INVERTINGINPUT_IO1
+
+#define OPAMP_INVERTINGINPUT_VINM             OPAMP_SEC_INVERTINGINPUT_IO1
+
+#define OPAMP_PGACONNECT_NO                   OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
+#define OPAMP_PGACONNECT_VM0                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
+#define OPAMP_PGACONNECT_VM1                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
+
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
+#define HAL_OPAMP_MSP_INIT_CB_ID       HAL_OPAMP_MSPINIT_CB_ID
+#define HAL_OPAMP_MSP_DEINIT_CB_ID     HAL_OPAMP_MSPDEINIT_CB_ID
+#endif
+
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define I2S_STANDARD_PHILLIPS      I2S_STANDARD_PHILIPS
+
+#if defined(STM32H7)
+  #define I2S_IT_TXE               I2S_IT_TXP
+  #define I2S_IT_RXNE              I2S_IT_RXP
+
+  #define I2S_FLAG_TXE             I2S_FLAG_TXP
+  #define I2S_FLAG_RXNE            I2S_FLAG_RXP
+#endif
+
+#if defined(STM32F7)
+  #define I2S_CLOCK_SYSCLK           I2S_CLOCK_PLL
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+/* Compact Flash-ATA registers description */
+#define CF_DATA                       ATA_DATA
+#define CF_SECTOR_COUNT               ATA_SECTOR_COUNT
+#define CF_SECTOR_NUMBER              ATA_SECTOR_NUMBER
+#define CF_CYLINDER_LOW               ATA_CYLINDER_LOW
+#define CF_CYLINDER_HIGH              ATA_CYLINDER_HIGH
+#define CF_CARD_HEAD                  ATA_CARD_HEAD
+#define CF_STATUS_CMD                 ATA_STATUS_CMD
+#define CF_STATUS_CMD_ALTERNATE       ATA_STATUS_CMD_ALTERNATE
+#define CF_COMMON_DATA_AREA           ATA_COMMON_DATA_AREA
+
+/* Compact Flash-ATA commands */
+#define CF_READ_SECTOR_CMD            ATA_READ_SECTOR_CMD
+#define CF_WRITE_SECTOR_CMD           ATA_WRITE_SECTOR_CMD
+#define CF_ERASE_SECTOR_CMD           ATA_ERASE_SECTOR_CMD
+#define CF_IDENTIFY_CMD               ATA_IDENTIFY_CMD
+
+#define PCCARD_StatusTypedef          HAL_PCCARD_StatusTypeDef
+#define PCCARD_SUCCESS                HAL_PCCARD_STATUS_SUCCESS
+#define PCCARD_ONGOING                HAL_PCCARD_STATUS_ONGOING
+#define PCCARD_ERROR                  HAL_PCCARD_STATUS_ERROR
+#define PCCARD_TIMEOUT                HAL_PCCARD_STATUS_TIMEOUT
+/**
+  * @}
+  */
+  
+/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define FORMAT_BIN                  RTC_FORMAT_BIN
+#define FORMAT_BCD                  RTC_FORMAT_BCD
+
+#define RTC_ALARMSUBSECONDMASK_None     RTC_ALARMSUBSECONDMASK_NONE
+#define RTC_TAMPERERASEBACKUP_DISABLED  RTC_TAMPER_ERASE_BACKUP_DISABLE
+#define RTC_TAMPERMASK_FLAG_DISABLED    RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_TAMPERMASK_FLAG_ENABLED     RTC_TAMPERMASK_FLAG_ENABLE
+
+#define RTC_MASKTAMPERFLAG_DISABLED     RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE
+#define RTC_TAMPERERASEBACKUP_ENABLED   RTC_TAMPER_ERASE_BACKUP_ENABLE
+#define RTC_TAMPER1_2_INTERRUPT         RTC_ALL_TAMPER_INTERRUPT
+#define RTC_TAMPER1_2_3_INTERRUPT       RTC_ALL_TAMPER_INTERRUPT
+
+#define RTC_TIMESTAMPPIN_PC13  RTC_TIMESTAMPPIN_DEFAULT
+#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PC1   RTC_TIMESTAMPPIN_POS2
+
+#define RTC_OUTPUT_REMAP_PC13  RTC_OUTPUT_REMAP_NONE
+#define RTC_OUTPUT_REMAP_PB14  RTC_OUTPUT_REMAP_POS1
+#define RTC_OUTPUT_REMAP_PB2   RTC_OUTPUT_REMAP_POS1
+
+#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
+#define RTC_TAMPERPIN_PA0  RTC_TAMPERPIN_POS1
+#define RTC_TAMPERPIN_PI8  RTC_TAMPERPIN_POS1
+
+#if defined(STM32H7)
+#define RTC_TAMPCR_TAMPXE          RTC_TAMPER_X
+#define RTC_TAMPCR_TAMPXIE         RTC_TAMPER_X_INTERRUPT
+
+#define RTC_TAMPER1_INTERRUPT      RTC_IT_TAMP1
+#define RTC_TAMPER2_INTERRUPT      RTC_IT_TAMP2
+#define RTC_TAMPER3_INTERRUPT      RTC_IT_TAMP3
+#define RTC_ALL_TAMPER_INTERRUPT   RTC_IT_TAMPALL
+#endif /* STM32H7 */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define SMARTCARD_NACK_ENABLED                  SMARTCARD_NACK_ENABLE
+#define SMARTCARD_NACK_DISABLED                 SMARTCARD_NACK_DISABLE
+
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLED      SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLED       SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLE       SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLE        SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+
+#define SMARTCARD_TIMEOUT_DISABLED              SMARTCARD_TIMEOUT_DISABLE
+#define SMARTCARD_TIMEOUT_ENABLED               SMARTCARD_TIMEOUT_ENABLE
+
+#define SMARTCARD_LASTBIT_DISABLED              SMARTCARD_LASTBIT_DISABLE
+#define SMARTCARD_LASTBIT_ENABLED               SMARTCARD_LASTBIT_ENABLE
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define SMBUS_DUALADDRESS_DISABLED      SMBUS_DUALADDRESS_DISABLE
+#define SMBUS_DUALADDRESS_ENABLED       SMBUS_DUALADDRESS_ENABLE
+#define SMBUS_GENERALCALL_DISABLED      SMBUS_GENERALCALL_DISABLE
+#define SMBUS_GENERALCALL_ENABLED       SMBUS_GENERALCALL_ENABLE
+#define SMBUS_NOSTRETCH_DISABLED        SMBUS_NOSTRETCH_DISABLE
+#define SMBUS_NOSTRETCH_ENABLED         SMBUS_NOSTRETCH_ENABLE
+#define SMBUS_ANALOGFILTER_ENABLED      SMBUS_ANALOGFILTER_ENABLE
+#define SMBUS_ANALOGFILTER_DISABLED     SMBUS_ANALOGFILTER_DISABLE
+#define SMBUS_PEC_DISABLED              SMBUS_PEC_DISABLE
+#define SMBUS_PEC_ENABLED               SMBUS_PEC_ENABLE
+#define HAL_SMBUS_STATE_SLAVE_LISTEN    HAL_SMBUS_STATE_LISTEN
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define SPI_TIMODE_DISABLED             SPI_TIMODE_DISABLE
+#define SPI_TIMODE_ENABLED              SPI_TIMODE_ENABLE
+
+#define SPI_CRCCALCULATION_DISABLED     SPI_CRCCALCULATION_DISABLE
+#define SPI_CRCCALCULATION_ENABLED      SPI_CRCCALCULATION_ENABLE
+
+#define SPI_NSS_PULSE_DISABLED          SPI_NSS_PULSE_DISABLE
+#define SPI_NSS_PULSE_ENABLED           SPI_NSS_PULSE_ENABLE
+
+#if defined(STM32H7)
+
+ #define SPI_FLAG_TXE                    SPI_FLAG_TXP
+ #define SPI_FLAG_RXNE                   SPI_FLAG_RXP
+
+ #define SPI_IT_TXE                      SPI_IT_TXP
+ #define SPI_IT_RXNE                     SPI_IT_RXP
+
+ #define SPI_FRLVL_EMPTY                 SPI_RX_FIFO_0PACKET
+ #define SPI_FRLVL_QUARTER_FULL          SPI_RX_FIFO_1PACKET
+ #define SPI_FRLVL_HALF_FULL             SPI_RX_FIFO_2PACKET
+ #define SPI_FRLVL_FULL                  SPI_RX_FIFO_3PACKET
+
+#endif /* STM32H7 */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define CCER_CCxE_MASK                   TIM_CCER_CCxE_MASK
+#define CCER_CCxNE_MASK                  TIM_CCER_CCxNE_MASK
+
+#define TIM_DMABase_CR1                  TIM_DMABASE_CR1
+#define TIM_DMABase_CR2                  TIM_DMABASE_CR2
+#define TIM_DMABase_SMCR                 TIM_DMABASE_SMCR
+#define TIM_DMABase_DIER                 TIM_DMABASE_DIER
+#define TIM_DMABase_SR                   TIM_DMABASE_SR
+#define TIM_DMABase_EGR                  TIM_DMABASE_EGR
+#define TIM_DMABase_CCMR1                TIM_DMABASE_CCMR1
+#define TIM_DMABase_CCMR2                TIM_DMABASE_CCMR2
+#define TIM_DMABase_CCER                 TIM_DMABASE_CCER
+#define TIM_DMABase_CNT                  TIM_DMABASE_CNT
+#define TIM_DMABase_PSC                  TIM_DMABASE_PSC
+#define TIM_DMABase_ARR                  TIM_DMABASE_ARR
+#define TIM_DMABase_RCR                  TIM_DMABASE_RCR
+#define TIM_DMABase_CCR1                 TIM_DMABASE_CCR1
+#define TIM_DMABase_CCR2                 TIM_DMABASE_CCR2
+#define TIM_DMABase_CCR3                 TIM_DMABASE_CCR3
+#define TIM_DMABase_CCR4                 TIM_DMABASE_CCR4
+#define TIM_DMABase_BDTR                 TIM_DMABASE_BDTR
+#define TIM_DMABase_DCR                  TIM_DMABASE_DCR
+#define TIM_DMABase_DMAR                 TIM_DMABASE_DMAR
+#define TIM_DMABase_OR1                  TIM_DMABASE_OR1
+#define TIM_DMABase_CCMR3                TIM_DMABASE_CCMR3
+#define TIM_DMABase_CCR5                 TIM_DMABASE_CCR5
+#define TIM_DMABase_CCR6                 TIM_DMABASE_CCR6
+#define TIM_DMABase_OR2                  TIM_DMABASE_OR2
+#define TIM_DMABase_OR3                  TIM_DMABASE_OR3
+#define TIM_DMABase_OR                   TIM_DMABASE_OR
+
+#define TIM_EventSource_Update           TIM_EVENTSOURCE_UPDATE
+#define TIM_EventSource_CC1              TIM_EVENTSOURCE_CC1
+#define TIM_EventSource_CC2              TIM_EVENTSOURCE_CC2
+#define TIM_EventSource_CC3              TIM_EVENTSOURCE_CC3
+#define TIM_EventSource_CC4              TIM_EVENTSOURCE_CC4
+#define TIM_EventSource_COM              TIM_EVENTSOURCE_COM
+#define TIM_EventSource_Trigger          TIM_EVENTSOURCE_TRIGGER
+#define TIM_EventSource_Break            TIM_EVENTSOURCE_BREAK
+#define TIM_EventSource_Break2           TIM_EVENTSOURCE_BREAK2
+
+#define TIM_DMABurstLength_1Transfer     TIM_DMABURSTLENGTH_1TRANSFER
+#define TIM_DMABurstLength_2Transfers    TIM_DMABURSTLENGTH_2TRANSFERS
+#define TIM_DMABurstLength_3Transfers    TIM_DMABURSTLENGTH_3TRANSFERS
+#define TIM_DMABurstLength_4Transfers    TIM_DMABURSTLENGTH_4TRANSFERS
+#define TIM_DMABurstLength_5Transfers    TIM_DMABURSTLENGTH_5TRANSFERS
+#define TIM_DMABurstLength_6Transfers    TIM_DMABURSTLENGTH_6TRANSFERS
+#define TIM_DMABurstLength_7Transfers    TIM_DMABURSTLENGTH_7TRANSFERS
+#define TIM_DMABurstLength_8Transfers    TIM_DMABURSTLENGTH_8TRANSFERS
+#define TIM_DMABurstLength_9Transfers    TIM_DMABURSTLENGTH_9TRANSFERS
+#define TIM_DMABurstLength_10Transfers   TIM_DMABURSTLENGTH_10TRANSFERS
+#define TIM_DMABurstLength_11Transfers   TIM_DMABURSTLENGTH_11TRANSFERS
+#define TIM_DMABurstLength_12Transfers   TIM_DMABURSTLENGTH_12TRANSFERS
+#define TIM_DMABurstLength_13Transfers   TIM_DMABURSTLENGTH_13TRANSFERS
+#define TIM_DMABurstLength_14Transfers   TIM_DMABURSTLENGTH_14TRANSFERS
+#define TIM_DMABurstLength_15Transfers   TIM_DMABURSTLENGTH_15TRANSFERS
+#define TIM_DMABurstLength_16Transfers   TIM_DMABURSTLENGTH_16TRANSFERS
+#define TIM_DMABurstLength_17Transfers   TIM_DMABURSTLENGTH_17TRANSFERS
+#define TIM_DMABurstLength_18Transfers   TIM_DMABURSTLENGTH_18TRANSFERS
+
+#if defined(STM32L0)
+#define TIM22_TI1_GPIO1   TIM22_TI1_GPIO
+#define TIM22_TI1_GPIO2   TIM22_TI1_GPIO
+#endif
+
+#if defined(STM32F3)
+#define IS_TIM_HALL_INTERFACE_INSTANCE   IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
+#endif
+
+#if defined(STM32H7)
+#define TIM_TIM1_ETR_COMP1_OUT        TIM_TIM1_ETR_COMP1
+#define TIM_TIM1_ETR_COMP2_OUT        TIM_TIM1_ETR_COMP2
+#define TIM_TIM8_ETR_COMP1_OUT        TIM_TIM8_ETR_COMP1
+#define TIM_TIM8_ETR_COMP2_OUT        TIM_TIM8_ETR_COMP2
+#define TIM_TIM2_ETR_COMP1_OUT        TIM_TIM2_ETR_COMP1
+#define TIM_TIM2_ETR_COMP2_OUT        TIM_TIM2_ETR_COMP2
+#define TIM_TIM3_ETR_COMP1_OUT        TIM_TIM3_ETR_COMP1
+#define TIM_TIM1_TI1_COMP1_OUT        TIM_TIM1_TI1_COMP1
+#define TIM_TIM8_TI1_COMP2_OUT        TIM_TIM8_TI1_COMP2
+#define TIM_TIM2_TI4_COMP1_OUT        TIM_TIM2_TI4_COMP1
+#define TIM_TIM2_TI4_COMP2_OUT        TIM_TIM2_TI4_COMP2
+#define TIM_TIM2_TI4_COMP1COMP2_OUT   TIM_TIM2_TI4_COMP1_COMP2
+#define TIM_TIM3_TI1_COMP1_OUT        TIM_TIM3_TI1_COMP1
+#define TIM_TIM3_TI1_COMP2_OUT        TIM_TIM3_TI1_COMP2
+#define TIM_TIM3_TI1_COMP1COMP2_OUT   TIM_TIM3_TI1_COMP1_COMP2
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define TSC_SYNC_POL_FALL        TSC_SYNC_POLARITY_FALLING
+#define TSC_SYNC_POL_RISE_HIGH   TSC_SYNC_POLARITY_RISING
+/**
+  * @}
+  */
+
+/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define UART_ONEBIT_SAMPLING_DISABLED   UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONEBIT_SAMPLING_ENABLED    UART_ONE_BIT_SAMPLE_ENABLE
+#define UART_ONE_BIT_SAMPLE_DISABLED    UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONE_BIT_SAMPLE_ENABLED     UART_ONE_BIT_SAMPLE_ENABLE
+
+#define __HAL_UART_ONEBIT_ENABLE        __HAL_UART_ONE_BIT_SAMPLE_ENABLE
+#define __HAL_UART_ONEBIT_DISABLE       __HAL_UART_ONE_BIT_SAMPLE_DISABLE
+
+#define __DIV_SAMPLING16                UART_DIV_SAMPLING16
+#define __DIVMANT_SAMPLING16            UART_DIVMANT_SAMPLING16
+#define __DIVFRAQ_SAMPLING16            UART_DIVFRAQ_SAMPLING16
+#define __UART_BRR_SAMPLING16           UART_BRR_SAMPLING16
+
+#define __DIV_SAMPLING8                 UART_DIV_SAMPLING8
+#define __DIVMANT_SAMPLING8             UART_DIVMANT_SAMPLING8
+#define __DIVFRAQ_SAMPLING8             UART_DIVFRAQ_SAMPLING8
+#define __UART_BRR_SAMPLING8            UART_BRR_SAMPLING8
+
+#define __DIV_LPUART                    UART_DIV_LPUART
+
+#define UART_WAKEUPMETHODE_IDLELINE     UART_WAKEUPMETHOD_IDLELINE
+#define UART_WAKEUPMETHODE_ADDRESSMARK  UART_WAKEUPMETHOD_ADDRESSMARK
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define USART_CLOCK_DISABLED            USART_CLOCK_DISABLE
+#define USART_CLOCK_ENABLED             USART_CLOCK_ENABLE
+
+#define USARTNACK_ENABLED               USART_NACK_ENABLE
+#define USARTNACK_DISABLED              USART_NACK_DISABLE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define CFR_BASE                    WWDG_CFR_BASE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define CAN_FilterFIFO0             CAN_FILTER_FIFO0
+#define CAN_FilterFIFO1             CAN_FILTER_FIFO1
+#define CAN_IT_RQCP0                CAN_IT_TME
+#define CAN_IT_RQCP1                CAN_IT_TME
+#define CAN_IT_RQCP2                CAN_IT_TME
+#define INAK_TIMEOUT                CAN_TIMEOUT_VALUE
+#define SLAK_TIMEOUT                CAN_TIMEOUT_VALUE
+#define CAN_TXSTATUS_FAILED         ((uint8_t)0x00U)
+#define CAN_TXSTATUS_OK             ((uint8_t)0x01U)
+#define CAN_TXSTATUS_PENDING        ((uint8_t)0x02U)
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define VLAN_TAG                ETH_VLAN_TAG
+#define MIN_ETH_PAYLOAD         ETH_MIN_ETH_PAYLOAD
+#define MAX_ETH_PAYLOAD         ETH_MAX_ETH_PAYLOAD
+#define JUMBO_FRAME_PAYLOAD     ETH_JUMBO_FRAME_PAYLOAD
+#define MACMIIAR_CR_MASK        ETH_MACMIIAR_CR_MASK
+#define MACCR_CLEAR_MASK        ETH_MACCR_CLEAR_MASK
+#define MACFCR_CLEAR_MASK       ETH_MACFCR_CLEAR_MASK
+#define DMAOMR_CLEAR_MASK       ETH_DMAOMR_CLEAR_MASK
+
+#define ETH_MMCCR              0x00000100U
+#define ETH_MMCRIR             0x00000104U
+#define ETH_MMCTIR             0x00000108U
+#define ETH_MMCRIMR            0x0000010CU
+#define ETH_MMCTIMR            0x00000110U
+#define ETH_MMCTGFSCCR         0x0000014CU
+#define ETH_MMCTGFMSCCR        0x00000150U
+#define ETH_MMCTGFCR           0x00000168U
+#define ETH_MMCRFCECR          0x00000194U
+#define ETH_MMCRFAECR          0x00000198U
+#define ETH_MMCRGUFCR          0x000001C4U
+
+#define ETH_MAC_TXFIFO_FULL                             0x02000000U  /* Tx FIFO full */
+#define ETH_MAC_TXFIFONOT_EMPTY                         0x01000000U  /* Tx FIFO not empty */
+#define ETH_MAC_TXFIFO_WRITE_ACTIVE                     0x00400000U  /* Tx FIFO write active */
+#define ETH_MAC_TXFIFO_IDLE                             0x00000000U  /* Tx FIFO read status: Idle */
+#define ETH_MAC_TXFIFO_READ                             0x00100000U  /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
+#define ETH_MAC_TXFIFO_WAITING                          0x00200000U  /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
+#define ETH_MAC_TXFIFO_WRITING                          0x00300000U  /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
+#define ETH_MAC_TRANSMISSION_PAUSE                      0x00080000U  /* MAC transmitter in pause */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE            0x00000000U  /* MAC transmit frame controller: Idle */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING         0x00020000U  /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF   0x00040000U  /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING    0x00060000U  /* MAC transmit frame controller: Transferring input frame for transmission */
+#define ETH_MAC_MII_TRANSMIT_ACTIVE           0x00010000U  /* MAC MII transmit engine active */
+#define ETH_MAC_RXFIFO_EMPTY                  0x00000000U  /* Rx FIFO fill level: empty */
+#define ETH_MAC_RXFIFO_BELOW_THRESHOLD        0x00000100U  /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
+#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD        0x00000200U  /* Rx FIFO fill level: fill-level above flow-control activate threshold */
+#define ETH_MAC_RXFIFO_FULL                   0x00000300U  /* Rx FIFO fill level: full */
+#if defined(STM32F1)
+#else
+#define ETH_MAC_READCONTROLLER_IDLE           0x00000000U  /* Rx FIFO read controller IDLE state */
+#define ETH_MAC_READCONTROLLER_READING_DATA   0x00000020U  /* Rx FIFO read controller Reading frame data */
+#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U  /* Rx FIFO read controller Reading frame status (or time-stamp) */
+#endif
+#define ETH_MAC_READCONTROLLER_FLUSHING       0x00000060U  /* Rx FIFO read controller Flushing the frame data and status */
+#define ETH_MAC_RXFIFO_WRITE_ACTIVE           0x00000010U  /* Rx FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_NOTACTIVE          0x00000000U  /* MAC small FIFO read / write controllers not active */
+#define ETH_MAC_SMALL_FIFO_READ_ACTIVE        0x00000002U  /* MAC small FIFO read controller active */
+#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE       0x00000004U  /* MAC small FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_RW_ACTIVE          0x00000006U  /* MAC small FIFO read / write controllers active */
+#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE   0x00000001U  /* MAC MII receive protocol engine active */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define HAL_DCMI_ERROR_OVF      HAL_DCMI_ERROR_OVR
+#define DCMI_IT_OVF             DCMI_IT_OVR
+#define DCMI_FLAG_OVFRI         DCMI_FLAG_OVRRI
+#define DCMI_FLAG_OVFMI         DCMI_FLAG_OVRMI
+
+#define HAL_DCMI_ConfigCROP     HAL_DCMI_ConfigCrop
+#define HAL_DCMI_EnableCROP     HAL_DCMI_EnableCrop
+#define HAL_DCMI_DisableCROP    HAL_DCMI_DisableCrop
+
+/**
+  * @}
+  */
+
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
+  || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
+  || defined(STM32H7)
+/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define DMA2D_ARGB8888          DMA2D_OUTPUT_ARGB8888
+#define DMA2D_RGB888            DMA2D_OUTPUT_RGB888
+#define DMA2D_RGB565            DMA2D_OUTPUT_RGB565
+#define DMA2D_ARGB1555          DMA2D_OUTPUT_ARGB1555
+#define DMA2D_ARGB4444          DMA2D_OUTPUT_ARGB4444
+
+#define CM_ARGB8888             DMA2D_INPUT_ARGB8888
+#define CM_RGB888               DMA2D_INPUT_RGB888
+#define CM_RGB565               DMA2D_INPUT_RGB565
+#define CM_ARGB1555             DMA2D_INPUT_ARGB1555
+#define CM_ARGB4444             DMA2D_INPUT_ARGB4444
+#define CM_L8                   DMA2D_INPUT_L8
+#define CM_AL44                 DMA2D_INPUT_AL44
+#define CM_AL88                 DMA2D_INPUT_AL88
+#define CM_L4                   DMA2D_INPUT_L4
+#define CM_A8                   DMA2D_INPUT_A8
+#define CM_A4                   DMA2D_INPUT_A4
+/**
+  * @}
+  */
+#endif  /* STM32L4 ||  STM32F7 ||  STM32F4 ||  STM32H7 */
+
+/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_CRYP_ComputationCpltCallback     HAL_CRYPEx_ComputationCpltCallback
+/**
+  * @}
+  */
+
+/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_HASH_STATETypeDef        HAL_HASH_StateTypeDef
+#define HAL_HASHPhaseTypeDef         HAL_HASH_PhaseTypeDef
+#define HAL_HMAC_MD5_Finish          HAL_HASH_MD5_Finish
+#define HAL_HMAC_SHA1_Finish         HAL_HASH_SHA1_Finish
+#define HAL_HMAC_SHA224_Finish       HAL_HASH_SHA224_Finish
+#define HAL_HMAC_SHA256_Finish       HAL_HASH_SHA256_Finish
+
+/*HASH Algorithm Selection*/
+
+#define HASH_AlgoSelection_SHA1      HASH_ALGOSELECTION_SHA1
+#define HASH_AlgoSelection_SHA224    HASH_ALGOSELECTION_SHA224
+#define HASH_AlgoSelection_SHA256    HASH_ALGOSELECTION_SHA256
+#define HASH_AlgoSelection_MD5       HASH_ALGOSELECTION_MD5
+
+#define HASH_AlgoMode_HASH         HASH_ALGOMODE_HASH
+#define HASH_AlgoMode_HMAC         HASH_ALGOMODE_HMAC
+
+#define HASH_HMACKeyType_ShortKey  HASH_HMAC_KEYTYPE_SHORTKEY
+#define HASH_HMACKeyType_LongKey   HASH_HMAC_KEYTYPE_LONGKEY
+
+#if defined(STM32L4) || defined(STM32L5) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
+
+#define HAL_HASH_MD5_Accumulate                HAL_HASH_MD5_Accmlt
+#define HAL_HASH_MD5_Accumulate_End            HAL_HASH_MD5_Accmlt_End
+#define HAL_HASH_MD5_Accumulate_IT             HAL_HASH_MD5_Accmlt_IT
+#define HAL_HASH_MD5_Accumulate_End_IT         HAL_HASH_MD5_Accmlt_End_IT
+
+#define HAL_HASH_SHA1_Accumulate               HAL_HASH_SHA1_Accmlt
+#define HAL_HASH_SHA1_Accumulate_End           HAL_HASH_SHA1_Accmlt_End
+#define HAL_HASH_SHA1_Accumulate_IT            HAL_HASH_SHA1_Accmlt_IT
+#define HAL_HASH_SHA1_Accumulate_End_IT        HAL_HASH_SHA1_Accmlt_End_IT
+
+#define HAL_HASHEx_SHA224_Accumulate           HAL_HASHEx_SHA224_Accmlt
+#define HAL_HASHEx_SHA224_Accumulate_End       HAL_HASHEx_SHA224_Accmlt_End
+#define HAL_HASHEx_SHA224_Accumulate_IT        HAL_HASHEx_SHA224_Accmlt_IT
+#define HAL_HASHEx_SHA224_Accumulate_End_IT    HAL_HASHEx_SHA224_Accmlt_End_IT
+
+#define HAL_HASHEx_SHA256_Accumulate           HAL_HASHEx_SHA256_Accmlt
+#define HAL_HASHEx_SHA256_Accumulate_End       HAL_HASHEx_SHA256_Accmlt_End
+#define HAL_HASHEx_SHA256_Accumulate_IT        HAL_HASHEx_SHA256_Accmlt_IT
+#define HAL_HASHEx_SHA256_Accumulate_End_IT    HAL_HASHEx_SHA256_Accmlt_End_IT
+
+#endif  /* STM32L4 || STM32L5 || STM32F4 || STM32F7 || STM32H7 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
+#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
+#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
+#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
+#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
+#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
+#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
+#define HAL_VREFINT_OutputSelect  HAL_SYSCFG_VREFINT_OutputSelect
+#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
+#if defined(STM32L0)
+#else
+#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
+#endif
+#define HAL_ADC_EnableBuffer_Cmd(cmd)  (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
+#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ?  HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
+#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
+#define HAL_EnableSRDomainDBGStopMode      HAL_EnableDomain3DBGStopMode
+#define HAL_DisableSRDomainDBGStopMode     HAL_DisableDomain3DBGStopMode
+#define HAL_EnableSRDomainDBGStandbyMode   HAL_EnableDomain3DBGStandbyMode
+#define HAL_DisableSRDomainDBGStandbyMode  HAL_DisableDomain3DBGStandbyMode
+#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ  || STM32H7B0xxQ */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define FLASH_HalfPageProgram      HAL_FLASHEx_HalfPageProgram
+#define FLASH_EnableRunPowerDown   HAL_FLASHEx_EnableRunPowerDown
+#define FLASH_DisableRunPowerDown  HAL_FLASHEx_DisableRunPowerDown
+#define HAL_DATA_EEPROMEx_Unlock   HAL_FLASHEx_DATAEEPROM_Unlock
+#define HAL_DATA_EEPROMEx_Lock     HAL_FLASHEx_DATAEEPROM_Lock
+#define HAL_DATA_EEPROMEx_Erase    HAL_FLASHEx_DATAEEPROM_Erase
+#define HAL_DATA_EEPROMEx_Program  HAL_FLASHEx_DATAEEPROM_Program
+
+ /**
+  * @}
+  */
+
+/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_I2CEx_AnalogFilter_Config         HAL_I2CEx_ConfigAnalogFilter
+#define HAL_I2CEx_DigitalFilter_Config        HAL_I2CEx_ConfigDigitalFilter
+#define HAL_FMPI2CEx_AnalogFilter_Config      HAL_FMPI2CEx_ConfigAnalogFilter
+#define HAL_FMPI2CEx_DigitalFilter_Config     HAL_FMPI2CEx_ConfigDigitalFilter
+
+#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
+
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)
+#define HAL_I2C_Master_Sequential_Transmit_IT  HAL_I2C_Master_Seq_Transmit_IT
+#define HAL_I2C_Master_Sequential_Receive_IT   HAL_I2C_Master_Seq_Receive_IT
+#define HAL_I2C_Slave_Sequential_Transmit_IT   HAL_I2C_Slave_Seq_Transmit_IT
+#define HAL_I2C_Slave_Sequential_Receive_IT    HAL_I2C_Slave_Seq_Receive_IT
+#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)
+#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
+#define HAL_I2C_Master_Sequential_Receive_DMA  HAL_I2C_Master_Seq_Receive_DMA
+#define HAL_I2C_Slave_Sequential_Transmit_DMA  HAL_I2C_Slave_Seq_Transmit_DMA
+#define HAL_I2C_Slave_Sequential_Receive_DMA   HAL_I2C_Slave_Seq_Receive_DMA
+#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */
+
+#if defined(STM32F4)
+#define HAL_FMPI2C_Master_Sequential_Transmit_IT  HAL_FMPI2C_Master_Seq_Transmit_IT
+#define HAL_FMPI2C_Master_Sequential_Receive_IT   HAL_FMPI2C_Master_Seq_Receive_IT
+#define HAL_FMPI2C_Slave_Sequential_Transmit_IT   HAL_FMPI2C_Slave_Seq_Transmit_IT
+#define HAL_FMPI2C_Slave_Sequential_Receive_IT    HAL_FMPI2C_Slave_Seq_Receive_IT
+#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA
+#define HAL_FMPI2C_Master_Sequential_Receive_DMA  HAL_FMPI2C_Master_Seq_Receive_DMA
+#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA  HAL_FMPI2C_Slave_Seq_Transmit_DMA
+#define HAL_FMPI2C_Slave_Sequential_Receive_DMA   HAL_FMPI2C_Slave_Seq_Receive_DMA
+#endif /* STM32F4 */
+ /**
+  * @}
+  */
+
+/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
+  * @{
+  */
+
+#if defined(STM32G0)
+#define HAL_PWR_ConfigPVD                             HAL_PWREx_ConfigPVD
+#define HAL_PWR_EnablePVD                             HAL_PWREx_EnablePVD
+#define HAL_PWR_DisablePVD                            HAL_PWREx_DisablePVD
+#define HAL_PWR_PVD_IRQHandler                        HAL_PWREx_PVD_IRQHandler
+#endif
+#define HAL_PWR_PVDConfig                             HAL_PWR_ConfigPVD
+#define HAL_PWR_DisableBkUpReg                        HAL_PWREx_DisableBkUpReg
+#define HAL_PWR_DisableFlashPowerDown                 HAL_PWREx_DisableFlashPowerDown
+#define HAL_PWR_DisableVddio2Monitor                  HAL_PWREx_DisableVddio2Monitor
+#define HAL_PWR_EnableBkUpReg                         HAL_PWREx_EnableBkUpReg
+#define HAL_PWR_EnableFlashPowerDown                  HAL_PWREx_EnableFlashPowerDown
+#define HAL_PWR_EnableVddio2Monitor                   HAL_PWREx_EnableVddio2Monitor
+#define HAL_PWR_PVD_PVM_IRQHandler                    HAL_PWREx_PVD_PVM_IRQHandler
+#define HAL_PWR_PVDLevelConfig                        HAL_PWR_ConfigPVD
+#define HAL_PWR_Vddio2Monitor_IRQHandler              HAL_PWREx_Vddio2Monitor_IRQHandler
+#define HAL_PWR_Vddio2MonitorCallback                 HAL_PWREx_Vddio2MonitorCallback
+#define HAL_PWREx_ActivateOverDrive                   HAL_PWREx_EnableOverDrive
+#define HAL_PWREx_DeactivateOverDrive                 HAL_PWREx_DisableOverDrive
+#define HAL_PWREx_DisableSDADCAnalog                  HAL_PWREx_DisableSDADC
+#define HAL_PWREx_EnableSDADCAnalog                   HAL_PWREx_EnableSDADC
+#define HAL_PWREx_PVMConfig                           HAL_PWREx_ConfigPVM
+
+#define PWR_MODE_NORMAL                               PWR_PVD_MODE_NORMAL
+#define PWR_MODE_IT_RISING                            PWR_PVD_MODE_IT_RISING
+#define PWR_MODE_IT_FALLING                           PWR_PVD_MODE_IT_FALLING
+#define PWR_MODE_IT_RISING_FALLING                    PWR_PVD_MODE_IT_RISING_FALLING
+#define PWR_MODE_EVENT_RISING                         PWR_PVD_MODE_EVENT_RISING
+#define PWR_MODE_EVENT_FALLING                        PWR_PVD_MODE_EVENT_FALLING
+#define PWR_MODE_EVENT_RISING_FALLING                 PWR_PVD_MODE_EVENT_RISING_FALLING
+
+#define CR_OFFSET_BB                                  PWR_CR_OFFSET_BB
+#define CSR_OFFSET_BB                                 PWR_CSR_OFFSET_BB
+#define PMODE_BIT_NUMBER                              VOS_BIT_NUMBER
+#define CR_PMODE_BB                                   CR_VOS_BB
+
+#define DBP_BitNumber                                 DBP_BIT_NUMBER
+#define PVDE_BitNumber                                PVDE_BIT_NUMBER
+#define PMODE_BitNumber                               PMODE_BIT_NUMBER
+#define EWUP_BitNumber                                EWUP_BIT_NUMBER
+#define FPDS_BitNumber                                FPDS_BIT_NUMBER
+#define ODEN_BitNumber                                ODEN_BIT_NUMBER
+#define ODSWEN_BitNumber                              ODSWEN_BIT_NUMBER
+#define MRLVDS_BitNumber                              MRLVDS_BIT_NUMBER
+#define LPLVDS_BitNumber                              LPLVDS_BIT_NUMBER
+#define BRE_BitNumber                                 BRE_BIT_NUMBER
+
+#define PWR_MODE_EVT                                  PWR_PVD_MODE_NORMAL
+
+ /**
+  * @}
+  */
+
+/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_SMBUS_Slave_Listen_IT          HAL_SMBUS_EnableListen_IT
+#define HAL_SMBUS_SlaveAddrCallback        HAL_SMBUS_AddrCallback
+#define HAL_SMBUS_SlaveListenCpltCallback  HAL_SMBUS_ListenCpltCallback
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_SPI_FlushRxFifo                HAL_SPIEx_FlushRxFifo
+/**
+  * @}
+  */
+
+/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_TIM_DMADelayPulseCplt                       TIM_DMADelayPulseCplt
+#define HAL_TIM_DMAError                                TIM_DMAError
+#define HAL_TIM_DMACaptureCplt                          TIM_DMACaptureCplt
+#define HAL_TIMEx_DMACommutationCplt                    TIMEx_DMACommutationCplt
+#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
+#define HAL_TIM_SlaveConfigSynchronization              HAL_TIM_SlaveConfigSynchro
+#define HAL_TIM_SlaveConfigSynchronization_IT           HAL_TIM_SlaveConfigSynchro_IT
+#define HAL_TIMEx_CommutationCallback                   HAL_TIMEx_CommutCallback
+#define HAL_TIMEx_ConfigCommutationEvent                HAL_TIMEx_ConfigCommutEvent
+#define HAL_TIMEx_ConfigCommutationEvent_IT             HAL_TIMEx_ConfigCommutEvent_IT
+#define HAL_TIMEx_ConfigCommutationEvent_DMA            HAL_TIMEx_ConfigCommutEvent_DMA
+#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
+/**
+  * @}
+  */
+
+/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
+#define HAL_LTDC_Relaod           HAL_LTDC_Reload
+#define HAL_LTDC_StructInitFromVideoConfig  HAL_LTDCEx_StructInitFromVideoConfig
+#define HAL_LTDC_StructInitFromAdaptedCommandConfig  HAL_LTDCEx_StructInitFromAdaptedCommandConfig
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros ------------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define AES_IT_CC                      CRYP_IT_CC
+#define AES_IT_ERR                     CRYP_IT_ERR
+#define AES_FLAG_CCF                   CRYP_FLAG_CCF
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_GET_BOOT_MODE                   __HAL_SYSCFG_GET_BOOT_MODE
+#define __HAL_REMAPMEMORY_FLASH               __HAL_SYSCFG_REMAPMEMORY_FLASH
+#define __HAL_REMAPMEMORY_SYSTEMFLASH         __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
+#define __HAL_REMAPMEMORY_SRAM                __HAL_SYSCFG_REMAPMEMORY_SRAM
+#define __HAL_REMAPMEMORY_FMC                 __HAL_SYSCFG_REMAPMEMORY_FMC
+#define __HAL_REMAPMEMORY_FMC_SDRAM           __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
+#define __HAL_REMAPMEMORY_FSMC                __HAL_SYSCFG_REMAPMEMORY_FSMC
+#define __HAL_REMAPMEMORY_QUADSPI             __HAL_SYSCFG_REMAPMEMORY_QUADSPI
+#define __HAL_FMC_BANK                        __HAL_SYSCFG_FMC_BANK
+#define __HAL_GET_FLAG                        __HAL_SYSCFG_GET_FLAG
+#define __HAL_CLEAR_FLAG                      __HAL_SYSCFG_CLEAR_FLAG
+#define __HAL_VREFINT_OUT_ENABLE              __HAL_SYSCFG_VREFINT_OUT_ENABLE
+#define __HAL_VREFINT_OUT_DISABLE             __HAL_SYSCFG_VREFINT_OUT_DISABLE
+#define __HAL_SYSCFG_SRAM2_WRP_ENABLE         __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
+
+#define SYSCFG_FLAG_VREF_READY                SYSCFG_FLAG_VREFINT_READY
+#define SYSCFG_FLAG_RC48                      RCC_FLAG_HSI48
+#define IS_SYSCFG_FASTMODEPLUS_CONFIG         IS_I2C_FASTMODEPLUS
+#define UFB_MODE_BitNumber                    UFB_MODE_BIT_NUMBER
+#define CMP_PD_BitNumber                      CMP_PD_BIT_NUMBER
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __ADC_ENABLE                                     __HAL_ADC_ENABLE
+#define __ADC_DISABLE                                    __HAL_ADC_DISABLE
+#define __HAL_ADC_ENABLING_CONDITIONS                    ADC_ENABLING_CONDITIONS
+#define __HAL_ADC_DISABLING_CONDITIONS                   ADC_DISABLING_CONDITIONS
+#define __HAL_ADC_IS_ENABLED                             ADC_IS_ENABLE
+#define __ADC_IS_ENABLED                                 ADC_IS_ENABLE
+#define __HAL_ADC_IS_SOFTWARE_START_REGULAR              ADC_IS_SOFTWARE_START_REGULAR
+#define __HAL_ADC_IS_SOFTWARE_START_INJECTED             ADC_IS_SOFTWARE_START_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR          ADC_IS_CONVERSION_ONGOING_REGULAR
+#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED         ADC_IS_CONVERSION_ONGOING_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING                  ADC_IS_CONVERSION_ONGOING
+#define __HAL_ADC_CLEAR_ERRORCODE                        ADC_CLEAR_ERRORCODE
+
+#define __HAL_ADC_GET_RESOLUTION                         ADC_GET_RESOLUTION
+#define __HAL_ADC_JSQR_RK                                ADC_JSQR_RK
+#define __HAL_ADC_CFGR_AWD1CH                            ADC_CFGR_AWD1CH_SHIFT
+#define __HAL_ADC_CFGR_AWD23CR                           ADC_CFGR_AWD23CR
+#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION            ADC_CFGR_INJECT_AUTO_CONVERSION
+#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE              ADC_CFGR_INJECT_CONTEXT_QUEUE
+#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS             ADC_CFGR_INJECT_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS                ADC_CFGR_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM                 ADC_CFGR_DISCONTINUOUS_NUM
+#define __HAL_ADC_CFGR_AUTOWAIT                          ADC_CFGR_AUTOWAIT
+#define __HAL_ADC_CFGR_CONTINUOUS                        ADC_CFGR_CONTINUOUS
+#define __HAL_ADC_CFGR_OVERRUN                           ADC_CFGR_OVERRUN
+#define __HAL_ADC_CFGR_DMACONTREQ                        ADC_CFGR_DMACONTREQ
+#define __HAL_ADC_CFGR_EXTSEL                            ADC_CFGR_EXTSEL_SET
+#define __HAL_ADC_JSQR_JEXTSEL                           ADC_JSQR_JEXTSEL_SET
+#define __HAL_ADC_OFR_CHANNEL                            ADC_OFR_CHANNEL
+#define __HAL_ADC_DIFSEL_CHANNEL                         ADC_DIFSEL_CHANNEL
+#define __HAL_ADC_CALFACT_DIFF_SET                       ADC_CALFACT_DIFF_SET
+#define __HAL_ADC_CALFACT_DIFF_GET                       ADC_CALFACT_DIFF_GET
+#define __HAL_ADC_TRX_HIGHTHRESHOLD                      ADC_TRX_HIGHTHRESHOLD
+
+#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION                ADC_OFFSET_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION         ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION        ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_COMMON_REGISTER                        ADC_COMMON_REGISTER
+#define __HAL_ADC_COMMON_CCR_MULTI                       ADC_COMMON_CCR_MULTI
+#define __HAL_ADC_MULTIMODE_IS_ENABLED                   ADC_MULTIMODE_IS_ENABLE
+#define __ADC_MULTIMODE_IS_ENABLED                       ADC_MULTIMODE_IS_ENABLE
+#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER        ADC_NONMULTIMODE_OR_MULTIMODEMASTER
+#define __HAL_ADC_COMMON_ADC_OTHER                       ADC_COMMON_ADC_OTHER
+#define __HAL_ADC_MULTI_SLAVE                            ADC_MULTI_SLAVE
+
+#define __HAL_ADC_SQR1_L                                 ADC_SQR1_L_SHIFT
+#define __HAL_ADC_JSQR_JL                                ADC_JSQR_JL_SHIFT
+#define __HAL_ADC_JSQR_RK_JL                             ADC_JSQR_RK_JL
+#define __HAL_ADC_CR1_DISCONTINUOUS_NUM                  ADC_CR1_DISCONTINUOUS_NUM
+#define __HAL_ADC_CR1_SCAN                               ADC_CR1_SCAN_SET
+#define __HAL_ADC_CONVCYCLES_MAX_RANGE                   ADC_CONVCYCLES_MAX_RANGE
+#define __HAL_ADC_CLOCK_PRESCALER_RANGE                  ADC_CLOCK_PRESCALER_RANGE
+#define __HAL_ADC_GET_CLOCK_PRESCALER                    ADC_GET_CLOCK_PRESCALER
+
+#define __HAL_ADC_SQR1                                   ADC_SQR1
+#define __HAL_ADC_SMPR1                                  ADC_SMPR1
+#define __HAL_ADC_SMPR2                                  ADC_SMPR2
+#define __HAL_ADC_SQR3_RK                                ADC_SQR3_RK
+#define __HAL_ADC_SQR2_RK                                ADC_SQR2_RK
+#define __HAL_ADC_SQR1_RK                                ADC_SQR1_RK
+#define __HAL_ADC_CR2_CONTINUOUS                         ADC_CR2_CONTINUOUS
+#define __HAL_ADC_CR1_DISCONTINUOUS                      ADC_CR1_DISCONTINUOUS
+#define __HAL_ADC_CR1_SCANCONV                           ADC_CR1_SCANCONV
+#define __HAL_ADC_CR2_EOCSelection                       ADC_CR2_EOCSelection
+#define __HAL_ADC_CR2_DMAContReq                         ADC_CR2_DMAContReq
+#define __HAL_ADC_JSQR                                   ADC_JSQR
+
+#define __HAL_ADC_CHSELR_CHANNEL                         ADC_CHSELR_CHANNEL
+#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS               ADC_CFGR1_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR1_AUTOOFF                          ADC_CFGR1_AUTOOFF
+#define __HAL_ADC_CFGR1_AUTOWAIT                         ADC_CFGR1_AUTOWAIT
+#define __HAL_ADC_CFGR1_CONTINUOUS                       ADC_CFGR1_CONTINUOUS
+#define __HAL_ADC_CFGR1_OVERRUN                          ADC_CFGR1_OVERRUN
+#define __HAL_ADC_CFGR1_SCANDIR                          ADC_CFGR1_SCANDIR
+#define __HAL_ADC_CFGR1_DMACONTREQ                       ADC_CFGR1_DMACONTREQ
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_DHR12R1_ALIGNEMENT                        DAC_DHR12R1_ALIGNMENT
+#define __HAL_DHR12R2_ALIGNEMENT                        DAC_DHR12R2_ALIGNMENT
+#define __HAL_DHR12RD_ALIGNEMENT                        DAC_DHR12RD_ALIGNMENT
+#define IS_DAC_GENERATE_WAVE                            IS_DAC_WAVE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
+#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
+#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
+#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
+#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
+#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
+#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
+#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
+#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
+#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
+#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
+#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
+#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
+#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
+#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
+#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
+
+#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
+#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
+#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
+#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
+#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
+#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
+#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
+#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
+#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
+#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
+#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
+#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
+#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
+#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
+
+
+#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
+#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
+#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
+#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
+#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
+#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
+#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
+#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
+#if defined(STM32H7)
+  #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
+  #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
+  #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
+  #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
+#else
+  #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
+  #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
+  #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
+  #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
+#endif /* STM32H7 */
+#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
+#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
+#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
+#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
+#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
+#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
+#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
+#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
+#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
+#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
+#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
+#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#if defined(STM32F3)
+#define COMP_START                                       __HAL_COMP_ENABLE
+#define COMP_STOP                                        __HAL_COMP_DISABLE
+#define COMP_LOCK                                        __HAL_COMP_LOCK
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F302xE) || defined(STM32F302xC)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP7_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP7_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP7_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F373xC) ||defined(STM32F378xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+# endif
+#else
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+#endif
+
+#define __HAL_COMP_GET_EXTI_LINE  COMP_GET_EXTI_LINE
+
+#if defined(STM32L0) || defined(STM32L4)
+/* Note: On these STM32 families, the only argument of this macro             */
+/*       is COMP_FLAG_LOCK.                                                   */
+/*       This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle  */
+/*       argument.                                                            */
+#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__)  (__HAL_COMP_IS_LOCKED(__HANDLE__))
+#endif
+/**
+  * @}
+  */
+
+#if defined(STM32L0) || defined(STM32L4)
+/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_COMP_Start_IT       HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
+#define HAL_COMP_Stop_IT        HAL_COMP_Stop  /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
+/**
+  * @}
+  */
+#endif
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
+                          ((WAVE) == DAC_WAVE_NOISE)|| \
+                          ((WAVE) == DAC_WAVE_TRIANGLE))
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define IS_WRPAREA          IS_OB_WRPAREA
+#define IS_TYPEPROGRAM      IS_FLASH_TYPEPROGRAM
+#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
+#define IS_TYPEERASE        IS_FLASH_TYPEERASE
+#define IS_NBSECTORS        IS_FLASH_NBSECTORS
+#define IS_OB_WDG_SOURCE    IS_OB_IWDG_SOURCE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_I2C_RESET_CR2             I2C_RESET_CR2
+#define __HAL_I2C_GENERATE_START        I2C_GENERATE_START
+#if defined(STM32F1)
+#define __HAL_I2C_FREQ_RANGE            I2C_FREQRANGE
+#else
+#define __HAL_I2C_FREQ_RANGE            I2C_FREQ_RANGE
+#endif /* STM32F1 */
+#define __HAL_I2C_RISE_TIME             I2C_RISE_TIME
+#define __HAL_I2C_SPEED_STANDARD        I2C_SPEED_STANDARD
+#define __HAL_I2C_SPEED_FAST            I2C_SPEED_FAST
+#define __HAL_I2C_SPEED                 I2C_SPEED
+#define __HAL_I2C_7BIT_ADD_WRITE        I2C_7BIT_ADD_WRITE
+#define __HAL_I2C_7BIT_ADD_READ         I2C_7BIT_ADD_READ
+#define __HAL_I2C_10BIT_ADDRESS         I2C_10BIT_ADDRESS
+#define __HAL_I2C_10BIT_HEADER_WRITE    I2C_10BIT_HEADER_WRITE
+#define __HAL_I2C_10BIT_HEADER_READ     I2C_10BIT_HEADER_READ
+#define __HAL_I2C_MEM_ADD_MSB           I2C_MEM_ADD_MSB
+#define __HAL_I2C_MEM_ADD_LSB           I2C_MEM_ADD_LSB
+#define __HAL_I2C_FREQRANGE             I2C_FREQRANGE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define IS_I2S_INSTANCE                 IS_I2S_ALL_INSTANCE
+#define IS_I2S_INSTANCE_EXT             IS_I2S_ALL_INSTANCE_EXT
+
+#if defined(STM32H7)
+  #define __HAL_I2S_CLEAR_FREFLAG       __HAL_I2S_CLEAR_TIFREFLAG
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __IRDA_DISABLE                  __HAL_IRDA_DISABLE
+#define __IRDA_ENABLE                   __HAL_IRDA_ENABLE
+
+#define __HAL_IRDA_GETCLOCKSOURCE       IRDA_GETCLOCKSOURCE
+#define __HAL_IRDA_MASK_COMPUTATION     IRDA_MASK_COMPUTATION
+#define __IRDA_GETCLOCKSOURCE           IRDA_GETCLOCKSOURCE
+#define __IRDA_MASK_COMPUTATION         IRDA_MASK_COMPUTATION
+
+#define IS_IRDA_ONEBIT_SAMPLE           IS_IRDA_ONE_BIT_SAMPLE
+
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_IWDG_ENABLE_WRITE_ACCESS  IWDG_ENABLE_WRITE_ACCESS
+#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_LPTIM_ENABLE_INTERRUPT    __HAL_LPTIM_ENABLE_IT
+#define __HAL_LPTIM_DISABLE_INTERRUPT   __HAL_LPTIM_DISABLE_IT
+#define __HAL_LPTIM_GET_ITSTATUS        __HAL_LPTIM_GET_IT_SOURCE
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __OPAMP_CSR_OPAXPD                OPAMP_CSR_OPAXPD
+#define __OPAMP_CSR_S3SELX                OPAMP_CSR_S3SELX
+#define __OPAMP_CSR_S4SELX                OPAMP_CSR_S4SELX
+#define __OPAMP_CSR_S5SELX                OPAMP_CSR_S5SELX
+#define __OPAMP_CSR_S6SELX                OPAMP_CSR_S6SELX
+#define __OPAMP_CSR_OPAXCAL_L             OPAMP_CSR_OPAXCAL_L
+#define __OPAMP_CSR_OPAXCAL_H             OPAMP_CSR_OPAXCAL_H
+#define __OPAMP_CSR_OPAXLPM               OPAMP_CSR_OPAXLPM
+#define __OPAMP_CSR_ALL_SWITCHES          OPAMP_CSR_ALL_SWITCHES
+#define __OPAMP_CSR_ANAWSELX              OPAMP_CSR_ANAWSELX
+#define __OPAMP_CSR_OPAXCALOUT            OPAMP_CSR_OPAXCALOUT
+#define __OPAMP_OFFSET_TRIM_BITSPOSITION  OPAMP_OFFSET_TRIM_BITSPOSITION
+#define __OPAMP_OFFSET_TRIM_SET           OPAMP_OFFSET_TRIM_SET
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_PVD_EVENT_DISABLE                                  __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PVD_EVENT_ENABLE                                   __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PVM_EVENT_DISABLE                                  __HAL_PWR_PVM_EVENT_DISABLE
+#define __HAL_PVM_EVENT_ENABLE                                   __HAL_PWR_PVM_EVENT_ENABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
+#define __HAL_PWR_INTERNALWAKEUP_DISABLE                         HAL_PWREx_DisableInternalWakeUpLine
+#define __HAL_PWR_INTERNALWAKEUP_ENABLE                          HAL_PWREx_EnableInternalWakeUpLine
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE                    HAL_PWREx_DisablePullUpPullDownConfig
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE                     HAL_PWREx_EnablePullUpPullDownConfig
+#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER()                  do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
+#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE                         __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE                          __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE                __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE                 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE                 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE                  __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER              __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER               __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVM_DISABLE()                                  do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
+#define __HAL_PWR_PVM_ENABLE()                                   do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE                  HAL_PWREx_DisableSRAM2ContentRetention
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE                   HAL_PWREx_EnableSRAM2ContentRetention
+#define __HAL_PWR_VDDIO2_DISABLE                                 HAL_PWREx_DisableVddIO2
+#define __HAL_PWR_VDDIO2_ENABLE                                  HAL_PWREx_EnableVddIO2
+#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER                 __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER           __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_VDDUSB_DISABLE                                 HAL_PWREx_DisableVddUSB
+#define __HAL_PWR_VDDUSB_ENABLE                                  HAL_PWREx_EnableVddUSB
+
+#if defined (STM32F4)
+#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD)         __HAL_PWR_PVD_EXTI_ENABLE_IT()
+#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_DISABLE_IT()
+#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD)          __HAL_PWR_PVD_EXTI_GET_FLAG()
+#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
+#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD)     __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
+#else
+#define __HAL_PVD_EXTI_CLEAR_FLAG                                __HAL_PWR_PVD_EXTI_CLEAR_FLAG
+#define __HAL_PVD_EXTI_DISABLE_IT                                __HAL_PWR_PVD_EXTI_DISABLE_IT
+#define __HAL_PVD_EXTI_ENABLE_IT                                 __HAL_PWR_PVD_EXTI_ENABLE_IT
+#define __HAL_PVD_EXTI_GENERATE_SWIT                             __HAL_PWR_PVD_EXTI_GENERATE_SWIT
+#define __HAL_PVD_EXTI_GET_FLAG                                  __HAL_PWR_PVD_EXTI_GET_FLAG
+#endif /* STM32F4 */
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
+  * @{
+  */
+
+#define RCC_StopWakeUpClock_MSI     RCC_STOP_WAKEUPCLOCK_MSI
+#define RCC_StopWakeUpClock_HSI     RCC_STOP_WAKEUPCLOCK_HSI
+
+#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
+#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
+
+#define __ADC_CLK_DISABLE          __HAL_RCC_ADC_CLK_DISABLE
+#define __ADC_CLK_ENABLE           __HAL_RCC_ADC_CLK_ENABLE
+#define __ADC_CLK_SLEEP_DISABLE    __HAL_RCC_ADC_CLK_SLEEP_DISABLE
+#define __ADC_CLK_SLEEP_ENABLE     __HAL_RCC_ADC_CLK_SLEEP_ENABLE
+#define __ADC_FORCE_RESET          __HAL_RCC_ADC_FORCE_RESET
+#define __ADC_RELEASE_RESET        __HAL_RCC_ADC_RELEASE_RESET
+#define __ADC1_CLK_DISABLE         __HAL_RCC_ADC1_CLK_DISABLE
+#define __ADC1_CLK_ENABLE          __HAL_RCC_ADC1_CLK_ENABLE
+#define __ADC1_FORCE_RESET         __HAL_RCC_ADC1_FORCE_RESET
+#define __ADC1_RELEASE_RESET       __HAL_RCC_ADC1_RELEASE_RESET
+#define __ADC1_CLK_SLEEP_ENABLE    __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
+#define __ADC1_CLK_SLEEP_DISABLE   __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_DISABLE         __HAL_RCC_ADC2_CLK_DISABLE
+#define __ADC2_CLK_ENABLE          __HAL_RCC_ADC2_CLK_ENABLE
+#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
+#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
+#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
+#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
+#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
+#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
+#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
+#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
+#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
+#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
+#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
+#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
+#define __CRYP_CLK_SLEEP_ENABLE      __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
+#define __CRYP_CLK_SLEEP_DISABLE  __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
+#define __CRYP_CLK_ENABLE  __HAL_RCC_CRYP_CLK_ENABLE
+#define __CRYP_CLK_DISABLE  __HAL_RCC_CRYP_CLK_DISABLE
+#define __CRYP_FORCE_RESET       __HAL_RCC_CRYP_FORCE_RESET
+#define __CRYP_RELEASE_RESET  __HAL_RCC_CRYP_RELEASE_RESET
+#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
+#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
+#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
+#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
+#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
+#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
+#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
+#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
+#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
+#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
+#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
+#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
+#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
+#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
+#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
+#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
+#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
+#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
+#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
+#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
+#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
+#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
+#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN_CLK_DISABLE         __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN_CLK_ENABLE          __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN_FORCE_RESET         __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN_RELEASE_RESET       __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
+#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
+#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
+#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
+#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
+#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
+#define __COMP_CLK_DISABLE        __HAL_RCC_COMP_CLK_DISABLE
+#define __COMP_CLK_ENABLE         __HAL_RCC_COMP_CLK_ENABLE
+#define __COMP_FORCE_RESET        __HAL_RCC_COMP_FORCE_RESET
+#define __COMP_RELEASE_RESET      __HAL_RCC_COMP_RELEASE_RESET
+#define __COMP_CLK_SLEEP_ENABLE   __HAL_RCC_COMP_CLK_SLEEP_ENABLE
+#define __COMP_CLK_SLEEP_DISABLE  __HAL_RCC_COMP_CLK_SLEEP_DISABLE
+#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
+#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
+#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
+#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
+#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
+#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
+#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
+#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
+#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
+#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
+#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
+#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
+#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
+#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
+#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
+#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
+#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
+#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
+#define __DBGMCU_CLK_ENABLE     __HAL_RCC_DBGMCU_CLK_ENABLE
+#define __DBGMCU_CLK_DISABLE     __HAL_RCC_DBGMCU_CLK_DISABLE
+#define __DBGMCU_FORCE_RESET    __HAL_RCC_DBGMCU_FORCE_RESET
+#define __DBGMCU_RELEASE_RESET  __HAL_RCC_DBGMCU_RELEASE_RESET
+#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
+#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
+#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
+#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
+#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
+#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
+#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
+#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
+#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
+#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
+#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
+#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
+#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
+#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
+#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
+#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
+#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
+#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
+#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
+#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
+#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
+#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
+#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
+#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
+#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
+#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
+#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
+#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
+#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
+#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
+#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
+#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
+#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
+#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
+#define __FLITF_CLK_DISABLE       __HAL_RCC_FLITF_CLK_DISABLE
+#define __FLITF_CLK_ENABLE        __HAL_RCC_FLITF_CLK_ENABLE
+#define __FLITF_FORCE_RESET       __HAL_RCC_FLITF_FORCE_RESET
+#define __FLITF_RELEASE_RESET     __HAL_RCC_FLITF_RELEASE_RESET
+#define __FLITF_CLK_SLEEP_ENABLE  __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
+#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
+#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
+#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
+#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
+#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
+#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
+#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
+#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
+#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
+#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
+#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
+#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
+#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
+#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
+#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
+#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
+#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
+#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
+#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
+#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
+#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
+#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
+#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
+#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
+#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
+#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
+#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
+#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
+#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
+#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
+#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
+#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
+#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
+#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
+#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
+#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
+#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
+#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
+#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
+#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
+#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
+#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
+#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
+#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
+#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
+#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
+#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
+#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
+#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
+#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
+#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
+#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
+#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
+#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
+#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
+#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
+#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
+#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
+#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
+#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
+#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
+#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
+#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
+#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
+#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
+#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
+#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
+#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
+#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
+#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
+#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
+#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
+#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
+#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
+#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
+#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
+#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
+#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
+#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
+#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
+#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
+#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
+#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
+#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
+#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
+#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
+#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
+#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
+#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
+#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
+#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
+#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
+#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
+#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
+#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
+#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
+#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
+#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
+#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
+#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
+#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
+#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
+#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
+#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
+#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
+#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
+#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
+#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
+#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
+#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
+#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
+#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
+#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
+#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
+#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
+#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
+#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
+#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
+#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
+#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
+#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
+#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
+#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
+
+#if defined(STM32WB)
+#define __HAL_RCC_QSPI_CLK_DISABLE            __HAL_RCC_QUADSPI_CLK_DISABLE
+#define __HAL_RCC_QSPI_CLK_ENABLE             __HAL_RCC_QUADSPI_CLK_ENABLE
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE      __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE       __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_QSPI_FORCE_RESET            __HAL_RCC_QUADSPI_FORCE_RESET
+#define __HAL_RCC_QSPI_RELEASE_RESET          __HAL_RCC_QUADSPI_RELEASE_RESET
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED         __HAL_RCC_QUADSPI_IS_CLK_ENABLED
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED        __HAL_RCC_QUADSPI_IS_CLK_DISABLED
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED   __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED  __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED
+#define QSPI_IRQHandler QUADSPI_IRQHandler
+#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */
+
+#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
+#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
+#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
+#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
+#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
+#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
+#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
+#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
+#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
+#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
+#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
+#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
+#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
+#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
+#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
+#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
+#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
+#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
+#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
+#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
+#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
+#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
+#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
+#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
+#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
+#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
+#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
+#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
+#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
+#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
+#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
+#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
+#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
+#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
+#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
+#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
+#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
+#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
+#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
+#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
+#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
+#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
+#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
+#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
+#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
+#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
+#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
+#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
+#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
+#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
+#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
+#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
+#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
+#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
+#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
+#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
+#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
+#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
+#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
+#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
+#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
+#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
+#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
+#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
+#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
+#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
+#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
+#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
+#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
+#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
+#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
+#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
+#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
+#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
+#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
+#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
+#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
+#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
+#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
+#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
+#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
+#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
+#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
+#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
+#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
+#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
+#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
+#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
+#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
+#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
+#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
+#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
+#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
+#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
+#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
+#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
+#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
+#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
+#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
+#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
+#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
+#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
+#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
+#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
+#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
+#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
+#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
+#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
+#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
+#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
+#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
+#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
+#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
+#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
+#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
+#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
+#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
+#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
+#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
+#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
+#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
+#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
+#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
+#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
+#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
+#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
+#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
+#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
+#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
+#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
+#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
+#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
+#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
+#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
+#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
+#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
+#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
+#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
+#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
+#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
+#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
+#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
+#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
+#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
+#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
+#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
+#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
+#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
+#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
+#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
+#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
+#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
+#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
+#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
+#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
+#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
+#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
+#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
+#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
+#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
+#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
+#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
+#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
+#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
+#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
+#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
+#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
+#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
+#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
+#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
+#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
+#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
+#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
+#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
+#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
+#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
+#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
+#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
+#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
+#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
+#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
+#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
+#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
+#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
+#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
+#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
+#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
+#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
+#define __USART4_CLK_DISABLE        __HAL_RCC_UART4_CLK_DISABLE
+#define __USART4_CLK_ENABLE         __HAL_RCC_UART4_CLK_ENABLE
+#define __USART4_CLK_SLEEP_ENABLE   __HAL_RCC_UART4_CLK_SLEEP_ENABLE
+#define __USART4_CLK_SLEEP_DISABLE  __HAL_RCC_UART4_CLK_SLEEP_DISABLE
+#define __USART4_FORCE_RESET        __HAL_RCC_UART4_FORCE_RESET
+#define __USART4_RELEASE_RESET      __HAL_RCC_UART4_RELEASE_RESET
+#define __USART5_CLK_DISABLE        __HAL_RCC_UART5_CLK_DISABLE
+#define __USART5_CLK_ENABLE         __HAL_RCC_UART5_CLK_ENABLE
+#define __USART5_CLK_SLEEP_ENABLE   __HAL_RCC_UART5_CLK_SLEEP_ENABLE
+#define __USART5_CLK_SLEEP_DISABLE  __HAL_RCC_UART5_CLK_SLEEP_DISABLE
+#define __USART5_FORCE_RESET        __HAL_RCC_UART5_FORCE_RESET
+#define __USART5_RELEASE_RESET      __HAL_RCC_UART5_RELEASE_RESET
+#define __USART7_CLK_DISABLE        __HAL_RCC_UART7_CLK_DISABLE
+#define __USART7_CLK_ENABLE         __HAL_RCC_UART7_CLK_ENABLE
+#define __USART7_FORCE_RESET        __HAL_RCC_UART7_FORCE_RESET
+#define __USART7_RELEASE_RESET      __HAL_RCC_UART7_RELEASE_RESET
+#define __USART8_CLK_DISABLE        __HAL_RCC_UART8_CLK_DISABLE
+#define __USART8_CLK_ENABLE         __HAL_RCC_UART8_CLK_ENABLE
+#define __USART8_FORCE_RESET        __HAL_RCC_UART8_FORCE_RESET
+#define __USART8_RELEASE_RESET      __HAL_RCC_UART8_RELEASE_RESET
+#define __USB_CLK_DISABLE         __HAL_RCC_USB_CLK_DISABLE
+#define __USB_CLK_ENABLE          __HAL_RCC_USB_CLK_ENABLE
+#define __USB_FORCE_RESET         __HAL_RCC_USB_FORCE_RESET
+#define __USB_CLK_SLEEP_ENABLE    __HAL_RCC_USB_CLK_SLEEP_ENABLE
+#define __USB_CLK_SLEEP_DISABLE   __HAL_RCC_USB_CLK_SLEEP_DISABLE
+#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
+#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
+#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
+
+#if defined(STM32H7)
+#define __HAL_RCC_WWDG_CLK_DISABLE   __HAL_RCC_WWDG1_CLK_DISABLE
+#define __HAL_RCC_WWDG_CLK_ENABLE   __HAL_RCC_WWDG1_CLK_ENABLE
+#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE  __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE  __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE
+
+#define __HAL_RCC_WWDG_FORCE_RESET    ((void)0U)  /* Not available on the STM32H7*/
+#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/
+
+
+#define  __HAL_RCC_WWDG_IS_CLK_ENABLED    __HAL_RCC_WWDG1_IS_CLK_ENABLED
+#define  __HAL_RCC_WWDG_IS_CLK_DISABLED  __HAL_RCC_WWDG1_IS_CLK_DISABLED
+#endif
+
+#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
+#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
+#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
+#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
+#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
+#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
+
+#define __TIM21_CLK_ENABLE   __HAL_RCC_TIM21_CLK_ENABLE
+#define __TIM21_CLK_DISABLE   __HAL_RCC_TIM21_CLK_DISABLE
+#define __TIM21_FORCE_RESET   __HAL_RCC_TIM21_FORCE_RESET
+#define __TIM21_RELEASE_RESET  __HAL_RCC_TIM21_RELEASE_RESET
+#define __TIM21_CLK_SLEEP_ENABLE   __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
+#define __TIM21_CLK_SLEEP_DISABLE   __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
+#define __TIM22_CLK_ENABLE   __HAL_RCC_TIM22_CLK_ENABLE
+#define __TIM22_CLK_DISABLE   __HAL_RCC_TIM22_CLK_DISABLE
+#define __TIM22_FORCE_RESET   __HAL_RCC_TIM22_FORCE_RESET
+#define __TIM22_RELEASE_RESET  __HAL_RCC_TIM22_RELEASE_RESET
+#define __TIM22_CLK_SLEEP_ENABLE   __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
+#define __TIM22_CLK_SLEEP_DISABLE   __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
+#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
+#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
+#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
+#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
+#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
+#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
+#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
+#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
+
+#define __USB_OTG_FS_FORCE_RESET  __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __USB_OTG_FS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+#define __USB_OTG_FS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
+#define __USB_OTG_FS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
+#define __USB_OTG_HS_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_DISABLE
+#define __USB_OTG_HS_CLK_ENABLE          __HAL_RCC_USB_OTG_HS_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
+#define __TIM9_CLK_SLEEP_ENABLE          __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
+#define __TIM9_CLK_SLEEP_DISABLE  __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
+#define __TIM10_CLK_SLEEP_ENABLE  __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
+#define __TIM10_CLK_SLEEP_DISABLE  __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
+#define __TIM11_CLK_SLEEP_ENABLE  __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
+#define __TIM11_CLK_SLEEP_DISABLE  __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
+#define __ETHMACPTP_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
+#define __ETHMACPTP_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
+#define __ETHMACPTP_CLK_ENABLE          __HAL_RCC_ETHMACPTP_CLK_ENABLE
+#define __ETHMACPTP_CLK_DISABLE          __HAL_RCC_ETHMACPTP_CLK_DISABLE
+#define __HASH_CLK_ENABLE          __HAL_RCC_HASH_CLK_ENABLE
+#define __HASH_FORCE_RESET          __HAL_RCC_HASH_FORCE_RESET
+#define __HASH_RELEASE_RESET          __HAL_RCC_HASH_RELEASE_RESET
+#define __HASH_CLK_SLEEP_ENABLE          __HAL_RCC_HASH_CLK_SLEEP_ENABLE
+#define __HASH_CLK_SLEEP_DISABLE  __HAL_RCC_HASH_CLK_SLEEP_DISABLE
+#define __HASH_CLK_DISABLE            __HAL_RCC_HASH_CLK_DISABLE
+#define __SPI5_CLK_ENABLE          __HAL_RCC_SPI5_CLK_ENABLE
+#define __SPI5_CLK_DISABLE              __HAL_RCC_SPI5_CLK_DISABLE
+#define __SPI5_FORCE_RESET          __HAL_RCC_SPI5_FORCE_RESET
+#define __SPI5_RELEASE_RESET          __HAL_RCC_SPI5_RELEASE_RESET
+#define __SPI5_CLK_SLEEP_ENABLE          __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
+#define __SPI5_CLK_SLEEP_DISABLE  __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
+#define __SPI6_CLK_ENABLE          __HAL_RCC_SPI6_CLK_ENABLE
+#define __SPI6_CLK_DISABLE          __HAL_RCC_SPI6_CLK_DISABLE
+#define __SPI6_FORCE_RESET          __HAL_RCC_SPI6_FORCE_RESET
+#define __SPI6_RELEASE_RESET         __HAL_RCC_SPI6_RELEASE_RESET
+#define __SPI6_CLK_SLEEP_ENABLE          __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
+#define __SPI6_CLK_SLEEP_DISABLE  __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
+#define __LTDC_CLK_ENABLE          __HAL_RCC_LTDC_CLK_ENABLE
+#define __LTDC_CLK_DISABLE          __HAL_RCC_LTDC_CLK_DISABLE
+#define __LTDC_FORCE_RESET          __HAL_RCC_LTDC_FORCE_RESET
+#define __LTDC_RELEASE_RESET          __HAL_RCC_LTDC_RELEASE_RESET
+#define __LTDC_CLK_SLEEP_ENABLE          __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
+#define __ETHMAC_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
+#define __ETHMAC_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
+#define __ETHMACTX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
+#define __ETHMACTX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
+#define __ETHMACRX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
+#define __ETHMACRX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
+#define __TIM12_CLK_SLEEP_ENABLE  __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
+#define __TIM12_CLK_SLEEP_DISABLE  __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
+#define __TIM13_CLK_SLEEP_ENABLE  __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
+#define __TIM13_CLK_SLEEP_DISABLE  __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
+#define __TIM14_CLK_SLEEP_ENABLE  __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
+#define __TIM14_CLK_SLEEP_DISABLE  __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
+#define __BKPSRAM_CLK_ENABLE          __HAL_RCC_BKPSRAM_CLK_ENABLE
+#define __BKPSRAM_CLK_DISABLE          __HAL_RCC_BKPSRAM_CLK_DISABLE
+#define __BKPSRAM_CLK_SLEEP_ENABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
+#define __BKPSRAM_CLK_SLEEP_DISABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
+#define __CCMDATARAMEN_CLK_ENABLE  __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
+#define __CCMDATARAMEN_CLK_DISABLE  __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
+#define __USART6_CLK_ENABLE          __HAL_RCC_USART6_CLK_ENABLE
+#define __USART6_CLK_DISABLE          __HAL_RCC_USART6_CLK_DISABLE
+#define __USART6_FORCE_RESET        __HAL_RCC_USART6_FORCE_RESET
+#define __USART6_RELEASE_RESET        __HAL_RCC_USART6_RELEASE_RESET
+#define __USART6_CLK_SLEEP_ENABLE  __HAL_RCC_USART6_CLK_SLEEP_ENABLE
+#define __USART6_CLK_SLEEP_DISABLE  __HAL_RCC_USART6_CLK_SLEEP_DISABLE
+#define __SPI4_CLK_ENABLE          __HAL_RCC_SPI4_CLK_ENABLE
+#define __SPI4_CLK_DISABLE          __HAL_RCC_SPI4_CLK_DISABLE
+#define __SPI4_FORCE_RESET          __HAL_RCC_SPI4_FORCE_RESET
+#define __SPI4_RELEASE_RESET        __HAL_RCC_SPI4_RELEASE_RESET
+#define __SPI4_CLK_SLEEP_ENABLE   __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
+#define __SPI4_CLK_SLEEP_DISABLE  __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
+#define __GPIOI_CLK_ENABLE          __HAL_RCC_GPIOI_CLK_ENABLE
+#define __GPIOI_CLK_DISABLE          __HAL_RCC_GPIOI_CLK_DISABLE
+#define __GPIOI_FORCE_RESET          __HAL_RCC_GPIOI_FORCE_RESET
+#define __GPIOI_RELEASE_RESET          __HAL_RCC_GPIOI_RELEASE_RESET
+#define __GPIOI_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
+#define __GPIOI_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
+#define __GPIOJ_CLK_ENABLE          __HAL_RCC_GPIOJ_CLK_ENABLE
+#define __GPIOJ_CLK_DISABLE          __HAL_RCC_GPIOJ_CLK_DISABLE
+#define __GPIOJ_FORCE_RESET         __HAL_RCC_GPIOJ_FORCE_RESET
+#define __GPIOJ_RELEASE_RESET          __HAL_RCC_GPIOJ_RELEASE_RESET
+#define __GPIOJ_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
+#define __GPIOJ_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
+#define __GPIOK_CLK_ENABLE          __HAL_RCC_GPIOK_CLK_ENABLE
+#define __GPIOK_CLK_DISABLE          __HAL_RCC_GPIOK_CLK_DISABLE
+#define __GPIOK_RELEASE_RESET          __HAL_RCC_GPIOK_RELEASE_RESET
+#define __GPIOK_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
+#define __GPIOK_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
+#define __ETH_CLK_ENABLE          __HAL_RCC_ETH_CLK_ENABLE
+#define __ETH_CLK_DISABLE          __HAL_RCC_ETH_CLK_DISABLE
+#define __DCMI_CLK_ENABLE          __HAL_RCC_DCMI_CLK_ENABLE
+#define __DCMI_CLK_DISABLE          __HAL_RCC_DCMI_CLK_DISABLE
+#define __DCMI_FORCE_RESET          __HAL_RCC_DCMI_FORCE_RESET
+#define __DCMI_RELEASE_RESET          __HAL_RCC_DCMI_RELEASE_RESET
+#define __DCMI_CLK_SLEEP_ENABLE   __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
+#define __DCMI_CLK_SLEEP_DISABLE  __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
+#define __UART7_CLK_ENABLE          __HAL_RCC_UART7_CLK_ENABLE
+#define __UART7_CLK_DISABLE          __HAL_RCC_UART7_CLK_DISABLE
+#define __UART7_RELEASE_RESET       __HAL_RCC_UART7_RELEASE_RESET
+#define __UART7_FORCE_RESET       __HAL_RCC_UART7_FORCE_RESET
+#define __UART7_CLK_SLEEP_ENABLE  __HAL_RCC_UART7_CLK_SLEEP_ENABLE
+#define __UART7_CLK_SLEEP_DISABLE  __HAL_RCC_UART7_CLK_SLEEP_DISABLE
+#define __UART8_CLK_ENABLE          __HAL_RCC_UART8_CLK_ENABLE
+#define __UART8_CLK_DISABLE          __HAL_RCC_UART8_CLK_DISABLE
+#define __UART8_FORCE_RESET          __HAL_RCC_UART8_FORCE_RESET
+#define __UART8_RELEASE_RESET          __HAL_RCC_UART8_RELEASE_RESET
+#define __UART8_CLK_SLEEP_ENABLE  __HAL_RCC_UART8_CLK_SLEEP_ENABLE
+#define __UART8_CLK_SLEEP_DISABLE  __HAL_RCC_UART8_CLK_SLEEP_DISABLE
+#define __OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __OTGHSULPI_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __OTGHSULPI_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
+#define __HAL_RCC_OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __HAL_RCC_OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE      __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE     __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED  __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
+#define __SRAM3_CLK_SLEEP_ENABLE       __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_ENABLE        __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_DISABLE       __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
+#define __DAC_CLK_SLEEP_ENABLE         __HAL_RCC_DAC_CLK_SLEEP_ENABLE
+#define __DAC_CLK_SLEEP_DISABLE        __HAL_RCC_DAC_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_SLEEP_ENABLE        __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
+#define __ADC2_CLK_SLEEP_DISABLE       __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
+#define __ADC3_CLK_SLEEP_ENABLE        __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
+#define __ADC3_CLK_SLEEP_DISABLE       __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
+#define __FSMC_FORCE_RESET             __HAL_RCC_FSMC_FORCE_RESET
+#define __FSMC_RELEASE_RESET           __HAL_RCC_FSMC_RELEASE_RESET
+#define __FSMC_CLK_SLEEP_ENABLE        __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
+#define __FSMC_CLK_SLEEP_DISABLE       __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
+#define __SDIO_FORCE_RESET             __HAL_RCC_SDIO_FORCE_RESET
+#define __SDIO_RELEASE_RESET           __HAL_RCC_SDIO_RELEASE_RESET
+#define __SDIO_CLK_SLEEP_DISABLE       __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __SDIO_CLK_SLEEP_ENABLE        __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_ENABLE             __HAL_RCC_DMA2D_CLK_ENABLE
+#define __DMA2D_CLK_DISABLE            __HAL_RCC_DMA2D_CLK_DISABLE
+#define __DMA2D_FORCE_RESET            __HAL_RCC_DMA2D_FORCE_RESET
+#define __DMA2D_RELEASE_RESET          __HAL_RCC_DMA2D_RELEASE_RESET
+#define __DMA2D_CLK_SLEEP_ENABLE       __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_SLEEP_DISABLE      __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
+
+/* alias define maintained for legacy */
+#define __HAL_RCC_OTGFS_FORCE_RESET    __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __HAL_RCC_OTGFS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+
+#define __ADC12_CLK_ENABLE          __HAL_RCC_ADC12_CLK_ENABLE
+#define __ADC12_CLK_DISABLE         __HAL_RCC_ADC12_CLK_DISABLE
+#define __ADC34_CLK_ENABLE          __HAL_RCC_ADC34_CLK_ENABLE
+#define __ADC34_CLK_DISABLE         __HAL_RCC_ADC34_CLK_DISABLE
+#define __DAC2_CLK_ENABLE           __HAL_RCC_DAC2_CLK_ENABLE
+#define __DAC2_CLK_DISABLE          __HAL_RCC_DAC2_CLK_DISABLE
+#define __TIM18_CLK_ENABLE          __HAL_RCC_TIM18_CLK_ENABLE
+#define __TIM18_CLK_DISABLE         __HAL_RCC_TIM18_CLK_DISABLE
+#define __TIM19_CLK_ENABLE          __HAL_RCC_TIM19_CLK_ENABLE
+#define __TIM19_CLK_DISABLE         __HAL_RCC_TIM19_CLK_DISABLE
+#define __TIM20_CLK_ENABLE          __HAL_RCC_TIM20_CLK_ENABLE
+#define __TIM20_CLK_DISABLE         __HAL_RCC_TIM20_CLK_DISABLE
+#define __HRTIM1_CLK_ENABLE         __HAL_RCC_HRTIM1_CLK_ENABLE
+#define __HRTIM1_CLK_DISABLE        __HAL_RCC_HRTIM1_CLK_DISABLE
+#define __SDADC1_CLK_ENABLE         __HAL_RCC_SDADC1_CLK_ENABLE
+#define __SDADC2_CLK_ENABLE         __HAL_RCC_SDADC2_CLK_ENABLE
+#define __SDADC3_CLK_ENABLE         __HAL_RCC_SDADC3_CLK_ENABLE
+#define __SDADC1_CLK_DISABLE        __HAL_RCC_SDADC1_CLK_DISABLE
+#define __SDADC2_CLK_DISABLE        __HAL_RCC_SDADC2_CLK_DISABLE
+#define __SDADC3_CLK_DISABLE        __HAL_RCC_SDADC3_CLK_DISABLE
+
+#define __ADC12_FORCE_RESET         __HAL_RCC_ADC12_FORCE_RESET
+#define __ADC12_RELEASE_RESET       __HAL_RCC_ADC12_RELEASE_RESET
+#define __ADC34_FORCE_RESET         __HAL_RCC_ADC34_FORCE_RESET
+#define __ADC34_RELEASE_RESET       __HAL_RCC_ADC34_RELEASE_RESET
+#define __DAC2_FORCE_RESET          __HAL_RCC_DAC2_FORCE_RESET
+#define __DAC2_RELEASE_RESET        __HAL_RCC_DAC2_RELEASE_RESET
+#define __TIM18_FORCE_RESET         __HAL_RCC_TIM18_FORCE_RESET
+#define __TIM18_RELEASE_RESET       __HAL_RCC_TIM18_RELEASE_RESET
+#define __TIM19_FORCE_RESET         __HAL_RCC_TIM19_FORCE_RESET
+#define __TIM19_RELEASE_RESET       __HAL_RCC_TIM19_RELEASE_RESET
+#define __TIM20_FORCE_RESET         __HAL_RCC_TIM20_FORCE_RESET
+#define __TIM20_RELEASE_RESET       __HAL_RCC_TIM20_RELEASE_RESET
+#define __HRTIM1_FORCE_RESET        __HAL_RCC_HRTIM1_FORCE_RESET
+#define __HRTIM1_RELEASE_RESET      __HAL_RCC_HRTIM1_RELEASE_RESET
+#define __SDADC1_FORCE_RESET        __HAL_RCC_SDADC1_FORCE_RESET
+#define __SDADC2_FORCE_RESET        __HAL_RCC_SDADC2_FORCE_RESET
+#define __SDADC3_FORCE_RESET        __HAL_RCC_SDADC3_FORCE_RESET
+#define __SDADC1_RELEASE_RESET      __HAL_RCC_SDADC1_RELEASE_RESET
+#define __SDADC2_RELEASE_RESET      __HAL_RCC_SDADC2_RELEASE_RESET
+#define __SDADC3_RELEASE_RESET      __HAL_RCC_SDADC3_RELEASE_RESET
+
+#define __ADC1_IS_CLK_ENABLED       __HAL_RCC_ADC1_IS_CLK_ENABLED
+#define __ADC1_IS_CLK_DISABLED      __HAL_RCC_ADC1_IS_CLK_DISABLED
+#define __ADC12_IS_CLK_ENABLED      __HAL_RCC_ADC12_IS_CLK_ENABLED
+#define __ADC12_IS_CLK_DISABLED     __HAL_RCC_ADC12_IS_CLK_DISABLED
+#define __ADC34_IS_CLK_ENABLED      __HAL_RCC_ADC34_IS_CLK_ENABLED
+#define __ADC34_IS_CLK_DISABLED     __HAL_RCC_ADC34_IS_CLK_DISABLED
+#define __CEC_IS_CLK_ENABLED        __HAL_RCC_CEC_IS_CLK_ENABLED
+#define __CEC_IS_CLK_DISABLED       __HAL_RCC_CEC_IS_CLK_DISABLED
+#define __CRC_IS_CLK_ENABLED        __HAL_RCC_CRC_IS_CLK_ENABLED
+#define __CRC_IS_CLK_DISABLED       __HAL_RCC_CRC_IS_CLK_DISABLED
+#define __DAC1_IS_CLK_ENABLED       __HAL_RCC_DAC1_IS_CLK_ENABLED
+#define __DAC1_IS_CLK_DISABLED      __HAL_RCC_DAC1_IS_CLK_DISABLED
+#define __DAC2_IS_CLK_ENABLED       __HAL_RCC_DAC2_IS_CLK_ENABLED
+#define __DAC2_IS_CLK_DISABLED      __HAL_RCC_DAC2_IS_CLK_DISABLED
+#define __DMA1_IS_CLK_ENABLED       __HAL_RCC_DMA1_IS_CLK_ENABLED
+#define __DMA1_IS_CLK_DISABLED      __HAL_RCC_DMA1_IS_CLK_DISABLED
+#define __DMA2_IS_CLK_ENABLED       __HAL_RCC_DMA2_IS_CLK_ENABLED
+#define __DMA2_IS_CLK_DISABLED      __HAL_RCC_DMA2_IS_CLK_DISABLED
+#define __FLITF_IS_CLK_ENABLED      __HAL_RCC_FLITF_IS_CLK_ENABLED
+#define __FLITF_IS_CLK_DISABLED     __HAL_RCC_FLITF_IS_CLK_DISABLED
+#define __FMC_IS_CLK_ENABLED        __HAL_RCC_FMC_IS_CLK_ENABLED
+#define __FMC_IS_CLK_DISABLED       __HAL_RCC_FMC_IS_CLK_DISABLED
+#define __GPIOA_IS_CLK_ENABLED      __HAL_RCC_GPIOA_IS_CLK_ENABLED
+#define __GPIOA_IS_CLK_DISABLED     __HAL_RCC_GPIOA_IS_CLK_DISABLED
+#define __GPIOB_IS_CLK_ENABLED      __HAL_RCC_GPIOB_IS_CLK_ENABLED
+#define __GPIOB_IS_CLK_DISABLED     __HAL_RCC_GPIOB_IS_CLK_DISABLED
+#define __GPIOC_IS_CLK_ENABLED      __HAL_RCC_GPIOC_IS_CLK_ENABLED
+#define __GPIOC_IS_CLK_DISABLED     __HAL_RCC_GPIOC_IS_CLK_DISABLED
+#define __GPIOD_IS_CLK_ENABLED      __HAL_RCC_GPIOD_IS_CLK_ENABLED
+#define __GPIOD_IS_CLK_DISABLED     __HAL_RCC_GPIOD_IS_CLK_DISABLED
+#define __GPIOE_IS_CLK_ENABLED      __HAL_RCC_GPIOE_IS_CLK_ENABLED
+#define __GPIOE_IS_CLK_DISABLED     __HAL_RCC_GPIOE_IS_CLK_DISABLED
+#define __GPIOF_IS_CLK_ENABLED      __HAL_RCC_GPIOF_IS_CLK_ENABLED
+#define __GPIOF_IS_CLK_DISABLED     __HAL_RCC_GPIOF_IS_CLK_DISABLED
+#define __GPIOG_IS_CLK_ENABLED      __HAL_RCC_GPIOG_IS_CLK_ENABLED
+#define __GPIOG_IS_CLK_DISABLED     __HAL_RCC_GPIOG_IS_CLK_DISABLED
+#define __GPIOH_IS_CLK_ENABLED      __HAL_RCC_GPIOH_IS_CLK_ENABLED
+#define __GPIOH_IS_CLK_DISABLED     __HAL_RCC_GPIOH_IS_CLK_DISABLED
+#define __HRTIM1_IS_CLK_ENABLED     __HAL_RCC_HRTIM1_IS_CLK_ENABLED
+#define __HRTIM1_IS_CLK_DISABLED    __HAL_RCC_HRTIM1_IS_CLK_DISABLED
+#define __I2C1_IS_CLK_ENABLED       __HAL_RCC_I2C1_IS_CLK_ENABLED
+#define __I2C1_IS_CLK_DISABLED      __HAL_RCC_I2C1_IS_CLK_DISABLED
+#define __I2C2_IS_CLK_ENABLED       __HAL_RCC_I2C2_IS_CLK_ENABLED
+#define __I2C2_IS_CLK_DISABLED      __HAL_RCC_I2C2_IS_CLK_DISABLED
+#define __I2C3_IS_CLK_ENABLED       __HAL_RCC_I2C3_IS_CLK_ENABLED
+#define __I2C3_IS_CLK_DISABLED      __HAL_RCC_I2C3_IS_CLK_DISABLED
+#define __PWR_IS_CLK_ENABLED        __HAL_RCC_PWR_IS_CLK_ENABLED
+#define __PWR_IS_CLK_DISABLED       __HAL_RCC_PWR_IS_CLK_DISABLED
+#define __SYSCFG_IS_CLK_ENABLED     __HAL_RCC_SYSCFG_IS_CLK_ENABLED
+#define __SYSCFG_IS_CLK_DISABLED    __HAL_RCC_SYSCFG_IS_CLK_DISABLED
+#define __SPI1_IS_CLK_ENABLED       __HAL_RCC_SPI1_IS_CLK_ENABLED
+#define __SPI1_IS_CLK_DISABLED      __HAL_RCC_SPI1_IS_CLK_DISABLED
+#define __SPI2_IS_CLK_ENABLED       __HAL_RCC_SPI2_IS_CLK_ENABLED
+#define __SPI2_IS_CLK_DISABLED      __HAL_RCC_SPI2_IS_CLK_DISABLED
+#define __SPI3_IS_CLK_ENABLED       __HAL_RCC_SPI3_IS_CLK_ENABLED
+#define __SPI3_IS_CLK_DISABLED      __HAL_RCC_SPI3_IS_CLK_DISABLED
+#define __SPI4_IS_CLK_ENABLED       __HAL_RCC_SPI4_IS_CLK_ENABLED
+#define __SPI4_IS_CLK_DISABLED      __HAL_RCC_SPI4_IS_CLK_DISABLED
+#define __SDADC1_IS_CLK_ENABLED     __HAL_RCC_SDADC1_IS_CLK_ENABLED
+#define __SDADC1_IS_CLK_DISABLED    __HAL_RCC_SDADC1_IS_CLK_DISABLED
+#define __SDADC2_IS_CLK_ENABLED     __HAL_RCC_SDADC2_IS_CLK_ENABLED
+#define __SDADC2_IS_CLK_DISABLED    __HAL_RCC_SDADC2_IS_CLK_DISABLED
+#define __SDADC3_IS_CLK_ENABLED     __HAL_RCC_SDADC3_IS_CLK_ENABLED
+#define __SDADC3_IS_CLK_DISABLED    __HAL_RCC_SDADC3_IS_CLK_DISABLED
+#define __SRAM_IS_CLK_ENABLED       __HAL_RCC_SRAM_IS_CLK_ENABLED
+#define __SRAM_IS_CLK_DISABLED      __HAL_RCC_SRAM_IS_CLK_DISABLED
+#define __TIM1_IS_CLK_ENABLED       __HAL_RCC_TIM1_IS_CLK_ENABLED
+#define __TIM1_IS_CLK_DISABLED      __HAL_RCC_TIM1_IS_CLK_DISABLED
+#define __TIM2_IS_CLK_ENABLED       __HAL_RCC_TIM2_IS_CLK_ENABLED
+#define __TIM2_IS_CLK_DISABLED      __HAL_RCC_TIM2_IS_CLK_DISABLED
+#define __TIM3_IS_CLK_ENABLED       __HAL_RCC_TIM3_IS_CLK_ENABLED
+#define __TIM3_IS_CLK_DISABLED      __HAL_RCC_TIM3_IS_CLK_DISABLED
+#define __TIM4_IS_CLK_ENABLED       __HAL_RCC_TIM4_IS_CLK_ENABLED
+#define __TIM4_IS_CLK_DISABLED      __HAL_RCC_TIM4_IS_CLK_DISABLED
+#define __TIM5_IS_CLK_ENABLED       __HAL_RCC_TIM5_IS_CLK_ENABLED
+#define __TIM5_IS_CLK_DISABLED      __HAL_RCC_TIM5_IS_CLK_DISABLED
+#define __TIM6_IS_CLK_ENABLED       __HAL_RCC_TIM6_IS_CLK_ENABLED
+#define __TIM6_IS_CLK_DISABLED      __HAL_RCC_TIM6_IS_CLK_DISABLED
+#define __TIM7_IS_CLK_ENABLED       __HAL_RCC_TIM7_IS_CLK_ENABLED
+#define __TIM7_IS_CLK_DISABLED      __HAL_RCC_TIM7_IS_CLK_DISABLED
+#define __TIM8_IS_CLK_ENABLED       __HAL_RCC_TIM8_IS_CLK_ENABLED
+#define __TIM8_IS_CLK_DISABLED      __HAL_RCC_TIM8_IS_CLK_DISABLED
+#define __TIM12_IS_CLK_ENABLED      __HAL_RCC_TIM12_IS_CLK_ENABLED
+#define __TIM12_IS_CLK_DISABLED     __HAL_RCC_TIM12_IS_CLK_DISABLED
+#define __TIM13_IS_CLK_ENABLED      __HAL_RCC_TIM13_IS_CLK_ENABLED
+#define __TIM13_IS_CLK_DISABLED     __HAL_RCC_TIM13_IS_CLK_DISABLED
+#define __TIM14_IS_CLK_ENABLED      __HAL_RCC_TIM14_IS_CLK_ENABLED
+#define __TIM14_IS_CLK_DISABLED     __HAL_RCC_TIM14_IS_CLK_DISABLED
+#define __TIM15_IS_CLK_ENABLED      __HAL_RCC_TIM15_IS_CLK_ENABLED
+#define __TIM15_IS_CLK_DISABLED     __HAL_RCC_TIM15_IS_CLK_DISABLED
+#define __TIM16_IS_CLK_ENABLED      __HAL_RCC_TIM16_IS_CLK_ENABLED
+#define __TIM16_IS_CLK_DISABLED     __HAL_RCC_TIM16_IS_CLK_DISABLED
+#define __TIM17_IS_CLK_ENABLED      __HAL_RCC_TIM17_IS_CLK_ENABLED
+#define __TIM17_IS_CLK_DISABLED     __HAL_RCC_TIM17_IS_CLK_DISABLED
+#define __TIM18_IS_CLK_ENABLED      __HAL_RCC_TIM18_IS_CLK_ENABLED
+#define __TIM18_IS_CLK_DISABLED     __HAL_RCC_TIM18_IS_CLK_DISABLED
+#define __TIM19_IS_CLK_ENABLED      __HAL_RCC_TIM19_IS_CLK_ENABLED
+#define __TIM19_IS_CLK_DISABLED     __HAL_RCC_TIM19_IS_CLK_DISABLED
+#define __TIM20_IS_CLK_ENABLED      __HAL_RCC_TIM20_IS_CLK_ENABLED
+#define __TIM20_IS_CLK_DISABLED     __HAL_RCC_TIM20_IS_CLK_DISABLED
+#define __TSC_IS_CLK_ENABLED        __HAL_RCC_TSC_IS_CLK_ENABLED
+#define __TSC_IS_CLK_DISABLED       __HAL_RCC_TSC_IS_CLK_DISABLED
+#define __UART4_IS_CLK_ENABLED      __HAL_RCC_UART4_IS_CLK_ENABLED
+#define __UART4_IS_CLK_DISABLED     __HAL_RCC_UART4_IS_CLK_DISABLED
+#define __UART5_IS_CLK_ENABLED      __HAL_RCC_UART5_IS_CLK_ENABLED
+#define __UART5_IS_CLK_DISABLED     __HAL_RCC_UART5_IS_CLK_DISABLED
+#define __USART1_IS_CLK_ENABLED     __HAL_RCC_USART1_IS_CLK_ENABLED
+#define __USART1_IS_CLK_DISABLED    __HAL_RCC_USART1_IS_CLK_DISABLED
+#define __USART2_IS_CLK_ENABLED     __HAL_RCC_USART2_IS_CLK_ENABLED
+#define __USART2_IS_CLK_DISABLED    __HAL_RCC_USART2_IS_CLK_DISABLED
+#define __USART3_IS_CLK_ENABLED     __HAL_RCC_USART3_IS_CLK_ENABLED
+#define __USART3_IS_CLK_DISABLED    __HAL_RCC_USART3_IS_CLK_DISABLED
+#define __USB_IS_CLK_ENABLED        __HAL_RCC_USB_IS_CLK_ENABLED
+#define __USB_IS_CLK_DISABLED       __HAL_RCC_USB_IS_CLK_DISABLED
+#define __WWDG_IS_CLK_ENABLED       __HAL_RCC_WWDG_IS_CLK_ENABLED
+#define __WWDG_IS_CLK_DISABLED      __HAL_RCC_WWDG_IS_CLK_DISABLED
+
+#if defined(STM32L1)
+#define __HAL_RCC_CRYP_CLK_DISABLE         __HAL_RCC_AES_CLK_DISABLE
+#define __HAL_RCC_CRYP_CLK_ENABLE          __HAL_RCC_AES_CLK_ENABLE
+#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE   __HAL_RCC_AES_CLK_SLEEP_DISABLE
+#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE    __HAL_RCC_AES_CLK_SLEEP_ENABLE
+#define __HAL_RCC_CRYP_FORCE_RESET         __HAL_RCC_AES_FORCE_RESET
+#define __HAL_RCC_CRYP_RELEASE_RESET       __HAL_RCC_AES_RELEASE_RESET
+#endif /* STM32L1 */
+
+#if defined(STM32F4)
+#define __HAL_RCC_SDMMC1_FORCE_RESET       __HAL_RCC_SDIO_FORCE_RESET
+#define __HAL_RCC_SDMMC1_RELEASE_RESET     __HAL_RCC_SDIO_RELEASE_RESET
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE  __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDMMC1_CLK_ENABLE        __HAL_RCC_SDIO_CLK_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_DISABLE       __HAL_RCC_SDIO_CLK_DISABLE
+#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED    __HAL_RCC_SDIO_IS_CLK_ENABLED
+#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED   __HAL_RCC_SDIO_IS_CLK_DISABLED
+#define Sdmmc1ClockSelection               SdioClockSelection
+#define RCC_PERIPHCLK_SDMMC1               RCC_PERIPHCLK_SDIO
+#define RCC_SDMMC1CLKSOURCE_CLK48          RCC_SDIOCLKSOURCE_CK48
+#define RCC_SDMMC1CLKSOURCE_SYSCLK         RCC_SDIOCLKSOURCE_SYSCLK
+#define __HAL_RCC_SDMMC1_CONFIG            __HAL_RCC_SDIO_CONFIG
+#define __HAL_RCC_GET_SDMMC1_SOURCE        __HAL_RCC_GET_SDIO_SOURCE
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define __HAL_RCC_SDIO_FORCE_RESET         __HAL_RCC_SDMMC1_FORCE_RESET
+#define __HAL_RCC_SDIO_RELEASE_RESET       __HAL_RCC_SDMMC1_RELEASE_RESET
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE    __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE   __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDIO_CLK_ENABLE          __HAL_RCC_SDMMC1_CLK_ENABLE
+#define __HAL_RCC_SDIO_CLK_DISABLE         __HAL_RCC_SDMMC1_CLK_DISABLE
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED      __HAL_RCC_SDMMC1_IS_CLK_ENABLED
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED     __HAL_RCC_SDMMC1_IS_CLK_DISABLED
+#define SdioClockSelection                 Sdmmc1ClockSelection
+#define RCC_PERIPHCLK_SDIO                 RCC_PERIPHCLK_SDMMC1
+#define __HAL_RCC_SDIO_CONFIG              __HAL_RCC_SDMMC1_CONFIG
+#define __HAL_RCC_GET_SDIO_SOURCE          __HAL_RCC_GET_SDMMC1_SOURCE
+#endif
+
+#if defined(STM32F7)
+#define RCC_SDIOCLKSOURCE_CLK48             RCC_SDMMC1CLKSOURCE_CLK48
+#define RCC_SDIOCLKSOURCE_SYSCLK           RCC_SDMMC1CLKSOURCE_SYSCLK
+#endif
+
+#if defined(STM32H7)
+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()              __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()         __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()             __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE()        __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET()             __HAL_RCC_USB1_OTG_HS_FORCE_RESET()
+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()           __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()        __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()   __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()       __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE()  __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
+
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()             __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE()        __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE()            __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE()       __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()            __HAL_RCC_USB2_OTG_FS_FORCE_RESET()
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET()          __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()       __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE()  __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE()      __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()
+#endif
+
+#define __HAL_RCC_I2SCLK            __HAL_RCC_I2S_CONFIG
+#define __HAL_RCC_I2SCLK_CONFIG     __HAL_RCC_I2S_CONFIG
+
+#define __RCC_PLLSRC                RCC_GET_PLL_OSCSOURCE
+
+#define IS_RCC_MSIRANGE             IS_RCC_MSI_CLOCK_RANGE
+#define IS_RCC_RTCCLK_SOURCE        IS_RCC_RTCCLKSOURCE
+#define IS_RCC_SYSCLK_DIV           IS_RCC_HCLK
+#define IS_RCC_HCLK_DIV             IS_RCC_PCLK
+#define IS_RCC_PERIPHCLK            IS_RCC_PERIPHCLOCK
+
+#define RCC_IT_HSI14                RCC_IT_HSI14RDY
+
+#define RCC_IT_CSSLSE               RCC_IT_LSECSS
+#define RCC_IT_CSSHSE               RCC_IT_CSS
+
+#define RCC_PLLMUL_3                RCC_PLL_MUL3
+#define RCC_PLLMUL_4                RCC_PLL_MUL4
+#define RCC_PLLMUL_6                RCC_PLL_MUL6
+#define RCC_PLLMUL_8                RCC_PLL_MUL8
+#define RCC_PLLMUL_12               RCC_PLL_MUL12
+#define RCC_PLLMUL_16               RCC_PLL_MUL16
+#define RCC_PLLMUL_24               RCC_PLL_MUL24
+#define RCC_PLLMUL_32               RCC_PLL_MUL32
+#define RCC_PLLMUL_48               RCC_PLL_MUL48
+
+#define RCC_PLLDIV_2                RCC_PLL_DIV2
+#define RCC_PLLDIV_3                RCC_PLL_DIV3
+#define RCC_PLLDIV_4                RCC_PLL_DIV4
+
+#define IS_RCC_MCOSOURCE            IS_RCC_MCO1SOURCE
+#define __HAL_RCC_MCO_CONFIG        __HAL_RCC_MCO1_CONFIG
+#define RCC_MCO_NODIV               RCC_MCODIV_1
+#define RCC_MCO_DIV1                RCC_MCODIV_1
+#define RCC_MCO_DIV2                RCC_MCODIV_2
+#define RCC_MCO_DIV4                RCC_MCODIV_4
+#define RCC_MCO_DIV8                RCC_MCODIV_8
+#define RCC_MCO_DIV16               RCC_MCODIV_16
+#define RCC_MCO_DIV32               RCC_MCODIV_32
+#define RCC_MCO_DIV64               RCC_MCODIV_64
+#define RCC_MCO_DIV128              RCC_MCODIV_128
+#define RCC_MCOSOURCE_NONE          RCC_MCO1SOURCE_NOCLOCK
+#define RCC_MCOSOURCE_LSI           RCC_MCO1SOURCE_LSI
+#define RCC_MCOSOURCE_LSE           RCC_MCO1SOURCE_LSE
+#define RCC_MCOSOURCE_SYSCLK        RCC_MCO1SOURCE_SYSCLK
+#define RCC_MCOSOURCE_HSI           RCC_MCO1SOURCE_HSI
+#define RCC_MCOSOURCE_HSI14         RCC_MCO1SOURCE_HSI14
+#define RCC_MCOSOURCE_HSI48         RCC_MCO1SOURCE_HSI48
+#define RCC_MCOSOURCE_HSE           RCC_MCO1SOURCE_HSE
+#define RCC_MCOSOURCE_PLLCLK_DIV1   RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_NODIV  RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_DIV2   RCC_MCO1SOURCE_PLLCLK_DIV2
+
+#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
+#define RCC_RTCCLKSOURCE_NO_CLK     RCC_RTCCLKSOURCE_NONE
+#else
+#define RCC_RTCCLKSOURCE_NONE       RCC_RTCCLKSOURCE_NO_CLK
+#endif
+
+#define RCC_USBCLK_PLLSAI1          RCC_USBCLKSOURCE_PLLSAI1
+#define RCC_USBCLK_PLL              RCC_USBCLKSOURCE_PLL
+#define RCC_USBCLK_MSI              RCC_USBCLKSOURCE_MSI
+#define RCC_USBCLKSOURCE_PLLCLK     RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1          RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1_5        RCC_USBCLKSOURCE_PLL_DIV1_5
+#define RCC_USBPLLCLK_DIV2          RCC_USBCLKSOURCE_PLL_DIV2
+#define RCC_USBPLLCLK_DIV3          RCC_USBCLKSOURCE_PLL_DIV3
+
+#define HSION_BitNumber        RCC_HSION_BIT_NUMBER
+#define HSION_BITNUMBER        RCC_HSION_BIT_NUMBER
+#define HSEON_BitNumber        RCC_HSEON_BIT_NUMBER
+#define HSEON_BITNUMBER        RCC_HSEON_BIT_NUMBER
+#define MSION_BITNUMBER        RCC_MSION_BIT_NUMBER
+#define CSSON_BitNumber        RCC_CSSON_BIT_NUMBER
+#define CSSON_BITNUMBER        RCC_CSSON_BIT_NUMBER
+#define PLLON_BitNumber        RCC_PLLON_BIT_NUMBER
+#define PLLON_BITNUMBER        RCC_PLLON_BIT_NUMBER
+#define PLLI2SON_BitNumber     RCC_PLLI2SON_BIT_NUMBER
+#define I2SSRC_BitNumber       RCC_I2SSRC_BIT_NUMBER
+#define RTCEN_BitNumber        RCC_RTCEN_BIT_NUMBER
+#define RTCEN_BITNUMBER        RCC_RTCEN_BIT_NUMBER
+#define BDRST_BitNumber        RCC_BDRST_BIT_NUMBER
+#define BDRST_BITNUMBER        RCC_BDRST_BIT_NUMBER
+#define RTCRST_BITNUMBER       RCC_RTCRST_BIT_NUMBER
+#define LSION_BitNumber        RCC_LSION_BIT_NUMBER
+#define LSION_BITNUMBER        RCC_LSION_BIT_NUMBER
+#define LSEON_BitNumber        RCC_LSEON_BIT_NUMBER
+#define LSEON_BITNUMBER        RCC_LSEON_BIT_NUMBER
+#define LSEBYP_BITNUMBER       RCC_LSEBYP_BIT_NUMBER
+#define PLLSAION_BitNumber     RCC_PLLSAION_BIT_NUMBER
+#define TIMPRE_BitNumber       RCC_TIMPRE_BIT_NUMBER
+#define RMVF_BitNumber         RCC_RMVF_BIT_NUMBER
+#define RMVF_BITNUMBER         RCC_RMVF_BIT_NUMBER
+#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
+#define CR_BYTE2_ADDRESS       RCC_CR_BYTE2_ADDRESS
+#define CIR_BYTE1_ADDRESS      RCC_CIR_BYTE1_ADDRESS
+#define CIR_BYTE2_ADDRESS      RCC_CIR_BYTE2_ADDRESS
+#define BDCR_BYTE0_ADDRESS     RCC_BDCR_BYTE0_ADDRESS
+#define DBP_TIMEOUT_VALUE      RCC_DBP_TIMEOUT_VALUE
+#define LSE_TIMEOUT_VALUE      RCC_LSE_TIMEOUT_VALUE
+
+#define CR_HSION_BB            RCC_CR_HSION_BB
+#define CR_CSSON_BB            RCC_CR_CSSON_BB
+#define CR_PLLON_BB            RCC_CR_PLLON_BB
+#define CR_PLLI2SON_BB         RCC_CR_PLLI2SON_BB
+#define CR_MSION_BB            RCC_CR_MSION_BB
+#define CSR_LSION_BB           RCC_CSR_LSION_BB
+#define CSR_LSEON_BB           RCC_CSR_LSEON_BB
+#define CSR_LSEBYP_BB          RCC_CSR_LSEBYP_BB
+#define CSR_RTCEN_BB           RCC_CSR_RTCEN_BB
+#define CSR_RTCRST_BB          RCC_CSR_RTCRST_BB
+#define CFGR_I2SSRC_BB         RCC_CFGR_I2SSRC_BB
+#define BDCR_RTCEN_BB          RCC_BDCR_RTCEN_BB
+#define BDCR_BDRST_BB          RCC_BDCR_BDRST_BB
+#define CR_HSEON_BB            RCC_CR_HSEON_BB
+#define CSR_RMVF_BB            RCC_CSR_RMVF_BB
+#define CR_PLLSAION_BB         RCC_CR_PLLSAION_BB
+#define DCKCFGR_TIMPRE_BB      RCC_DCKCFGR_TIMPRE_BB
+
+#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER     __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
+#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER    __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
+#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB        __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
+#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB       __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
+#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE         __HAL_RCC_CRS_RELOADVALUE_CALCULATE
+
+#define __HAL_RCC_GET_IT_SOURCE                     __HAL_RCC_GET_IT
+
+#define RCC_CRS_SYNCWARM       RCC_CRS_SYNCWARN
+#define RCC_CRS_TRIMOV         RCC_CRS_TRIMOVF
+
+#define RCC_PERIPHCLK_CK48               RCC_PERIPHCLK_CLK48
+#define RCC_CK48CLKSOURCE_PLLQ           RCC_CLK48CLKSOURCE_PLLQ
+#define RCC_CK48CLKSOURCE_PLLSAIP        RCC_CLK48CLKSOURCE_PLLSAIP
+#define RCC_CK48CLKSOURCE_PLLI2SQ        RCC_CLK48CLKSOURCE_PLLI2SQ
+#define IS_RCC_CK48CLKSOURCE             IS_RCC_CLK48CLKSOURCE
+#define RCC_SDIOCLKSOURCE_CK48           RCC_SDIOCLKSOURCE_CLK48
+
+#define __HAL_RCC_DFSDM_CLK_ENABLE             __HAL_RCC_DFSDM1_CLK_ENABLE
+#define __HAL_RCC_DFSDM_CLK_DISABLE            __HAL_RCC_DFSDM1_CLK_DISABLE
+#define __HAL_RCC_DFSDM_IS_CLK_ENABLED         __HAL_RCC_DFSDM1_IS_CLK_ENABLED
+#define __HAL_RCC_DFSDM_IS_CLK_DISABLED        __HAL_RCC_DFSDM1_IS_CLK_DISABLED
+#define __HAL_RCC_DFSDM_FORCE_RESET            __HAL_RCC_DFSDM1_FORCE_RESET
+#define __HAL_RCC_DFSDM_RELEASE_RESET          __HAL_RCC_DFSDM1_RELEASE_RESET
+#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE       __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
+#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE      __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED   __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED  __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
+#define DfsdmClockSelection         Dfsdm1ClockSelection
+#define RCC_PERIPHCLK_DFSDM         RCC_PERIPHCLK_DFSDM1
+#define RCC_DFSDMCLKSOURCE_PCLK     RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_DFSDMCLKSOURCE_SYSCLK   RCC_DFSDM1CLKSOURCE_SYSCLK
+#define __HAL_RCC_DFSDM_CONFIG      __HAL_RCC_DFSDM1_CONFIG
+#define __HAL_RCC_GET_DFSDM_SOURCE  __HAL_RCC_GET_DFSDM1_SOURCE
+#define RCC_DFSDM1CLKSOURCE_PCLK    RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_SWPMI1CLKSOURCE_PCLK    RCC_SWPMI1CLKSOURCE_PCLK1
+#define RCC_LPTIM1CLKSOURCE_PCLK    RCC_LPTIM1CLKSOURCE_PCLK1
+#define RCC_LPTIM2CLKSOURCE_PCLK    RCC_LPTIM2CLKSOURCE_PCLK1
+
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM1AUDIOCLKSOURCE_I2S1
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM1AUDIOCLKSOURCE_I2S2
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM2AUDIOCLKSOURCE_I2S1
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM2AUDIOCLKSOURCE_I2S2
+#define RCC_DFSDM1CLKSOURCE_APB2            RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_DFSDM2CLKSOURCE_APB2            RCC_DFSDM2CLKSOURCE_PCLK2
+#define RCC_FMPI2C1CLKSOURCE_APB            RCC_FMPI2C1CLKSOURCE_PCLK1
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define  HAL_RNG_ReadyCallback(__HANDLE__)  HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4)
+#else
+#define __HAL_RTC_CLEAR_FLAG                      __HAL_RTC_EXTI_CLEAR_FLAG
+#endif
+#define __HAL_RTC_DISABLE_IT                      __HAL_RTC_EXTI_DISABLE_IT
+#define __HAL_RTC_ENABLE_IT                       __HAL_RTC_EXTI_ENABLE_IT
+
+#if defined (STM32F1)
+#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
+
+#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_ENABLE_IT()
+
+#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_DISABLE_IT()
+
+#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT)    __HAL_RTC_ALARM_EXTI_GET_FLAG()
+
+#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
+#else
+#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
+                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
+                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
+#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__)   (((__EXTI_LINE__)  == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
+                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
+                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
+#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
+                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
+                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
+#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__)    (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
+                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
+                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
+#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__)   (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
+                                                      (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() :  \
+                                                          __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
+#endif   /* STM32F1 */
+
+#define IS_ALARM                                  IS_RTC_ALARM
+#define IS_ALARM_MASK                             IS_RTC_ALARM_MASK
+#define IS_TAMPER                                 IS_RTC_TAMPER
+#define IS_TAMPER_ERASE_MODE                      IS_RTC_TAMPER_ERASE_MODE
+#define IS_TAMPER_FILTER                          IS_RTC_TAMPER_FILTER
+#define IS_TAMPER_INTERRUPT                       IS_RTC_TAMPER_INTERRUPT
+#define IS_TAMPER_MASKFLAG_STATE                  IS_RTC_TAMPER_MASKFLAG_STATE
+#define IS_TAMPER_PRECHARGE_DURATION              IS_RTC_TAMPER_PRECHARGE_DURATION
+#define IS_TAMPER_PULLUP_STATE                    IS_RTC_TAMPER_PULLUP_STATE
+#define IS_TAMPER_SAMPLING_FREQ                   IS_RTC_TAMPER_SAMPLING_FREQ
+#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION     IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
+#define IS_TAMPER_TRIGGER                         IS_RTC_TAMPER_TRIGGER
+#define IS_WAKEUP_CLOCK                           IS_RTC_WAKEUP_CLOCK
+#define IS_WAKEUP_COUNTER                         IS_RTC_WAKEUP_COUNTER
+
+#define __RTC_WRITEPROTECTION_ENABLE  __HAL_RTC_WRITEPROTECTION_ENABLE
+#define __RTC_WRITEPROTECTION_DISABLE  __HAL_RTC_WRITEPROTECTION_DISABLE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define SD_OCR_CID_CSD_OVERWRIETE   SD_OCR_CID_CSD_OVERWRITE
+#define SD_CMD_SD_APP_STAUS         SD_CMD_SD_APP_STATUS
+
+#if defined(STM32F4) || defined(STM32F2)
+#define  SD_SDMMC_DISABLED          SD_SDIO_DISABLED
+#define  SD_SDMMC_FUNCTION_BUSY     SD_SDIO_FUNCTION_BUSY
+#define  SD_SDMMC_FUNCTION_FAILED   SD_SDIO_FUNCTION_FAILED
+#define  SD_SDMMC_UNKNOWN_FUNCTION  SD_SDIO_UNKNOWN_FUNCTION
+#define  SD_CMD_SDMMC_SEN_OP_COND   SD_CMD_SDIO_SEN_OP_COND
+#define  SD_CMD_SDMMC_RW_DIRECT     SD_CMD_SDIO_RW_DIRECT
+#define  SD_CMD_SDMMC_RW_EXTENDED   SD_CMD_SDIO_RW_EXTENDED
+#define  __HAL_SD_SDMMC_ENABLE      __HAL_SD_SDIO_ENABLE
+#define  __HAL_SD_SDMMC_DISABLE     __HAL_SD_SDIO_DISABLE
+#define  __HAL_SD_SDMMC_DMA_ENABLE  __HAL_SD_SDIO_DMA_ENABLE
+#define  __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
+#define  __HAL_SD_SDMMC_ENABLE_IT   __HAL_SD_SDIO_ENABLE_IT
+#define  __HAL_SD_SDMMC_DISABLE_IT  __HAL_SD_SDIO_DISABLE_IT
+#define  __HAL_SD_SDMMC_GET_FLAG    __HAL_SD_SDIO_GET_FLAG
+#define  __HAL_SD_SDMMC_CLEAR_FLAG  __HAL_SD_SDIO_CLEAR_FLAG
+#define  __HAL_SD_SDMMC_GET_IT      __HAL_SD_SDIO_GET_IT
+#define  __HAL_SD_SDMMC_CLEAR_IT    __HAL_SD_SDIO_CLEAR_IT
+#define  SDMMC_STATIC_FLAGS         SDIO_STATIC_FLAGS
+#define  SDMMC_CMD0TIMEOUT          SDIO_CMD0TIMEOUT
+#define  SD_SDMMC_SEND_IF_COND      SD_SDIO_SEND_IF_COND
+/* alias CMSIS */
+#define  SDMMC1_IRQn                SDIO_IRQn
+#define  SDMMC1_IRQHandler          SDIO_IRQHandler
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define  SD_SDIO_DISABLED           SD_SDMMC_DISABLED
+#define  SD_SDIO_FUNCTION_BUSY      SD_SDMMC_FUNCTION_BUSY
+#define  SD_SDIO_FUNCTION_FAILED    SD_SDMMC_FUNCTION_FAILED
+#define  SD_SDIO_UNKNOWN_FUNCTION   SD_SDMMC_UNKNOWN_FUNCTION
+#define  SD_CMD_SDIO_SEN_OP_COND    SD_CMD_SDMMC_SEN_OP_COND
+#define  SD_CMD_SDIO_RW_DIRECT      SD_CMD_SDMMC_RW_DIRECT
+#define  SD_CMD_SDIO_RW_EXTENDED    SD_CMD_SDMMC_RW_EXTENDED
+#define  __HAL_SD_SDIO_ENABLE       __HAL_SD_SDMMC_ENABLE
+#define  __HAL_SD_SDIO_DISABLE      __HAL_SD_SDMMC_DISABLE
+#define  __HAL_SD_SDIO_DMA_ENABLE   __HAL_SD_SDMMC_DMA_ENABLE
+#define  __HAL_SD_SDIO_DMA_DISABL   __HAL_SD_SDMMC_DMA_DISABLE
+#define  __HAL_SD_SDIO_ENABLE_IT    __HAL_SD_SDMMC_ENABLE_IT
+#define  __HAL_SD_SDIO_DISABLE_IT   __HAL_SD_SDMMC_DISABLE_IT
+#define  __HAL_SD_SDIO_GET_FLAG     __HAL_SD_SDMMC_GET_FLAG
+#define  __HAL_SD_SDIO_CLEAR_FLAG   __HAL_SD_SDMMC_CLEAR_FLAG
+#define  __HAL_SD_SDIO_GET_IT       __HAL_SD_SDMMC_GET_IT
+#define  __HAL_SD_SDIO_CLEAR_IT     __HAL_SD_SDMMC_CLEAR_IT
+#define  SDIO_STATIC_FLAGS          SDMMC_STATIC_FLAGS
+#define  SDIO_CMD0TIMEOUT           SDMMC_CMD0TIMEOUT
+#define  SD_SDIO_SEND_IF_COND       SD_SDMMC_SEND_IF_COND
+/* alias CMSIS for compatibilities */
+#define  SDIO_IRQn                  SDMMC1_IRQn
+#define  SDIO_IRQHandler            SDMMC1_IRQHandler
+#endif
+
+#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7)
+#define  HAL_SD_CardCIDTypedef       HAL_SD_CardCIDTypeDef
+#define  HAL_SD_CardCSDTypedef       HAL_SD_CardCSDTypeDef
+#define  HAL_SD_CardStatusTypedef    HAL_SD_CardStatusTypeDef
+#define  HAL_SD_CardStateTypedef     HAL_SD_CardStateTypeDef
+#endif
+
+#if defined(STM32H7) || defined(STM32L5)
+#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback   HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
+#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback   HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
+#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback  HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
+#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback  HAL_MMCEx_Write_DMADoubleBuf1CpltCallback
+#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback    HAL_SDEx_Read_DMADoubleBuf0CpltCallback
+#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback    HAL_SDEx_Read_DMADoubleBuf1CpltCallback
+#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback   HAL_SDEx_Write_DMADoubleBuf0CpltCallback
+#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback   HAL_SDEx_Write_DMADoubleBuf1CpltCallback
+#define HAL_SD_DriveTransciver_1_8V_Callback          HAL_SD_DriveTransceiver_1_8V_Callback
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __SMARTCARD_ENABLE_IT           __HAL_SMARTCARD_ENABLE_IT
+#define __SMARTCARD_DISABLE_IT          __HAL_SMARTCARD_DISABLE_IT
+#define __SMARTCARD_ENABLE              __HAL_SMARTCARD_ENABLE
+#define __SMARTCARD_DISABLE             __HAL_SMARTCARD_DISABLE
+#define __SMARTCARD_DMA_REQUEST_ENABLE  __HAL_SMARTCARD_DMA_REQUEST_ENABLE
+#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
+
+#define __HAL_SMARTCARD_GETCLOCKSOURCE  SMARTCARD_GETCLOCKSOURCE
+#define __SMARTCARD_GETCLOCKSOURCE      SMARTCARD_GETCLOCKSOURCE
+
+#define IS_SMARTCARD_ONEBIT_SAMPLING    IS_SMARTCARD_ONE_BIT_SAMPLE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_SMBUS_RESET_CR1           SMBUS_RESET_CR1
+#define __HAL_SMBUS_RESET_CR2           SMBUS_RESET_CR2
+#define __HAL_SMBUS_GENERATE_START      SMBUS_GENERATE_START
+#define __HAL_SMBUS_GET_ADDR_MATCH      SMBUS_GET_ADDR_MATCH
+#define __HAL_SMBUS_GET_DIR             SMBUS_GET_DIR
+#define __HAL_SMBUS_GET_STOP_MODE       SMBUS_GET_STOP_MODE
+#define __HAL_SMBUS_GET_PEC_MODE        SMBUS_GET_PEC_MODE
+#define __HAL_SMBUS_GET_ALERT_ENABLED   SMBUS_GET_ALERT_ENABLED
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_SPI_1LINE_TX              SPI_1LINE_TX
+#define __HAL_SPI_1LINE_RX              SPI_1LINE_RX
+#define __HAL_SPI_RESET_CRC             SPI_RESET_CRC
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_UART_GETCLOCKSOURCE       UART_GETCLOCKSOURCE
+#define __HAL_UART_MASK_COMPUTATION     UART_MASK_COMPUTATION
+#define __UART_GETCLOCKSOURCE           UART_GETCLOCKSOURCE
+#define __UART_MASK_COMPUTATION         UART_MASK_COMPUTATION
+
+#define IS_UART_WAKEUPMETHODE           IS_UART_WAKEUPMETHOD
+
+#define IS_UART_ONEBIT_SAMPLE           IS_UART_ONE_BIT_SAMPLE
+#define IS_UART_ONEBIT_SAMPLING         IS_UART_ONE_BIT_SAMPLE
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __USART_ENABLE_IT               __HAL_USART_ENABLE_IT
+#define __USART_DISABLE_IT              __HAL_USART_DISABLE_IT
+#define __USART_ENABLE                  __HAL_USART_ENABLE
+#define __USART_DISABLE                 __HAL_USART_DISABLE
+
+#define __HAL_USART_GETCLOCKSOURCE      USART_GETCLOCKSOURCE
+#define __USART_GETCLOCKSOURCE          USART_GETCLOCKSOURCE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define USB_EXTI_LINE_WAKEUP                               USB_WAKEUP_EXTI_LINE
+
+#define USB_FS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
+#define USB_FS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_FS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_FS_EXTI_LINE_WAKEUP                            USB_OTG_FS_WAKEUP_EXTI_LINE
+
+#define USB_HS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
+#define USB_HS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_HS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_HS_EXTI_LINE_WAKEUP                            USB_OTG_HS_WAKEUP_EXTI_LINE
+
+#define __HAL_USB_EXTI_ENABLE_IT                           __HAL_USB_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_EXTI_DISABLE_IT                          __HAL_USB_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_EXTI_GET_FLAG                            __HAL_USB_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_EXTI_CLEAR_FLAG                          __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER             __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER            __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER           __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+
+#define __HAL_USB_FS_EXTI_ENABLE_IT                        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_FS_EXTI_DISABLE_IT                       __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_FS_EXTI_GET_FLAG                         __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_FS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define __HAL_USB_HS_EXTI_ENABLE_IT                        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_HS_EXTI_DISABLE_IT                       __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_HS_EXTI_GET_FLAG                         __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_HS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define HAL_PCD_ActiveRemoteWakeup                         HAL_PCD_ActivateRemoteWakeup
+#define HAL_PCD_DeActiveRemoteWakeup                       HAL_PCD_DeActivateRemoteWakeup
+
+#define HAL_PCD_SetTxFiFo                                  HAL_PCDEx_SetTxFiFo
+#define HAL_PCD_SetRxFiFo                                  HAL_PCDEx_SetRxFiFo
+/**
+  * @}
+  */
+
+/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_TIM_SetICPrescalerValue   TIM_SET_ICPRESCALERVALUE
+#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
+
+#define TIM_GET_ITSTATUS                __HAL_TIM_GET_IT_SOURCE
+#define TIM_GET_CLEAR_IT                __HAL_TIM_CLEAR_IT
+
+#define __HAL_TIM_GET_ITSTATUS          __HAL_TIM_GET_IT_SOURCE
+
+#define __HAL_TIM_DIRECTION_STATUS      __HAL_TIM_IS_TIM_COUNTING_DOWN
+#define __HAL_TIM_PRESCALER             __HAL_TIM_SET_PRESCALER
+#define __HAL_TIM_SetCounter            __HAL_TIM_SET_COUNTER
+#define __HAL_TIM_GetCounter            __HAL_TIM_GET_COUNTER
+#define __HAL_TIM_SetAutoreload         __HAL_TIM_SET_AUTORELOAD
+#define __HAL_TIM_GetAutoreload         __HAL_TIM_GET_AUTORELOAD
+#define __HAL_TIM_SetClockDivision      __HAL_TIM_SET_CLOCKDIVISION
+#define __HAL_TIM_GetClockDivision      __HAL_TIM_GET_CLOCKDIVISION
+#define __HAL_TIM_SetICPrescaler        __HAL_TIM_SET_ICPRESCALER
+#define __HAL_TIM_GetICPrescaler        __HAL_TIM_GET_ICPRESCALER
+#define __HAL_TIM_SetCompare            __HAL_TIM_SET_COMPARE
+#define __HAL_TIM_GetCompare            __HAL_TIM_GET_COMPARE
+
+#define TIM_BREAKINPUTSOURCE_DFSDM  TIM_BREAKINPUTSOURCE_DFSDM1
+/**
+  * @}
+  */
+
+/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_ETH_EXTI_ENABLE_IT                   __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_ETH_EXTI_DISABLE_IT                  __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_ETH_EXTI_GET_FLAG                    __HAL_ETH_WAKEUP_EXTI_GET_FLAG
+#define __HAL_ETH_EXTI_CLEAR_FLAG                  __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER     __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER    __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER   __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
+
+#define ETH_PROMISCIOUSMODE_ENABLE   ETH_PROMISCUOUS_MODE_ENABLE
+#define ETH_PROMISCIOUSMODE_DISABLE  ETH_PROMISCUOUS_MODE_DISABLE
+#define IS_ETH_PROMISCIOUS_MODE      IS_ETH_PROMISCUOUS_MODE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_LTDC_LAYER LTDC_LAYER
+#define __HAL_LTDC_RELOAD_CONFIG  __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define SAI_OUTPUTDRIVE_DISABLED          SAI_OUTPUTDRIVE_DISABLE
+#define SAI_OUTPUTDRIVE_ENABLED           SAI_OUTPUTDRIVE_ENABLE
+#define SAI_MASTERDIVIDER_ENABLED         SAI_MASTERDIVIDER_ENABLE
+#define SAI_MASTERDIVIDER_DISABLED        SAI_MASTERDIVIDER_DISABLE
+#define SAI_STREOMODE                     SAI_STEREOMODE
+#define SAI_FIFOStatus_Empty              SAI_FIFOSTATUS_EMPTY
+#define SAI_FIFOStatus_Less1QuarterFull   SAI_FIFOSTATUS_LESS1QUARTERFULL
+#define SAI_FIFOStatus_1QuarterFull       SAI_FIFOSTATUS_1QUARTERFULL
+#define SAI_FIFOStatus_HalfFull           SAI_FIFOSTATUS_HALFFULL
+#define SAI_FIFOStatus_3QuartersFull      SAI_FIFOSTATUS_3QUARTERFULL
+#define SAI_FIFOStatus_Full               SAI_FIFOSTATUS_FULL
+#define IS_SAI_BLOCK_MONO_STREO_MODE      IS_SAI_BLOCK_MONO_STEREO_MODE
+#define SAI_SYNCHRONOUS_EXT               SAI_SYNCHRONOUS_EXT_SAI1
+#define SAI_SYNCEXT_IN_ENABLE             SAI_SYNCEXT_OUTBLOCKA_ENABLE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#if defined(STM32H7)
+#define HAL_SPDIFRX_ReceiveControlFlow      HAL_SPDIFRX_ReceiveCtrlFlow
+#define HAL_SPDIFRX_ReceiveControlFlow_IT   HAL_SPDIFRX_ReceiveCtrlFlow_IT
+#define HAL_SPDIFRX_ReceiveControlFlow_DMA  HAL_SPDIFRX_ReceiveCtrlFlow_DMA
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
+#define HAL_HRTIM_WaveformCounterStart_IT      HAL_HRTIM_WaveformCountStart_IT
+#define HAL_HRTIM_WaveformCounterStart_DMA     HAL_HRTIM_WaveformCountStart_DMA
+#define HAL_HRTIM_WaveformCounterStart         HAL_HRTIM_WaveformCountStart
+#define HAL_HRTIM_WaveformCounterStop_IT       HAL_HRTIM_WaveformCountStop_IT
+#define HAL_HRTIM_WaveformCounterStop_DMA      HAL_HRTIM_WaveformCountStop_DMA
+#define HAL_HRTIM_WaveformCounterStop          HAL_HRTIM_WaveformCountStop
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)
+#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
+#endif /* STM32L4 || STM32F4 || STM32F7 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32_HAL_LEGACY */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h
new file mode 100644
index 00000000..2ee957c3
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h
@@ -0,0 +1,1078 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal.h
+  * @author  MCD Application Team
+  * @brief   This file contains all the functions prototypes for the HAL
+  *          module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_H
+#define STM32H7xx_HAL_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_conf.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup HAL
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup HAL_TICK_FREQ Tick Frequency
+  * @{
+  */
+typedef enum
+{
+  HAL_TICK_FREQ_10HZ         = 100U,
+  HAL_TICK_FREQ_100HZ        = 10U,
+  HAL_TICK_FREQ_1KHZ         = 1U,
+  HAL_TICK_FREQ_DEFAULT      = HAL_TICK_FREQ_1KHZ
+} HAL_TickFreqTypeDef;
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup REV_ID device revision ID
+  * @{
+  */
+#define REV_ID_Y ((uint32_t)0x1003)  /*!< STM32H7 rev.Y */
+#define REV_ID_B ((uint32_t)0x2000)  /*!< STM32H7 rev.B */
+#define REV_ID_X ((uint32_t)0x2001)  /*!< STM32H7 rev.X */
+#define REV_ID_V ((uint32_t)0x2003)  /*!< STM32H7 rev.V */
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
+  * @{
+  */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE0   VREFBUF_CSR_VRS_OUT2   /*!< Voltage reference scale 0 (VREF_OUT2) */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE1   VREFBUF_CSR_VRS_OUT1   /*!< Voltage reference scale 1 (VREF_OUT1) */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE2   VREFBUF_CSR_VRS_OUT4   /*!< Voltage reference scale 2 (VREF_OUT4) */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE3   VREFBUF_CSR_VRS_OUT3   /*!< Voltage reference scale 3 (VREF_OUT3) */
+
+
+#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__)  (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
+                                                     ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1) || \
+                                                     ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE2) || \
+                                                     ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE3))
+
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance
+  * @{
+  */
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE  ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to Voltage reference buffer output */
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE   VREFBUF_CSR_HIZ        /*!< VREF_plus pin is high impedance */
+
+#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__)  (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
+                                                      ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
+
+#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__)  (((__VALUE__) > 0UL) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
+
+/**
+  * @}
+  */
+
+#if !defined(SYSCFG_PMCR_BOOSTEN)
+/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
+  * @{
+  */
+
+/** @brief  Fast-mode Plus driving capability on a specific GPIO
+  */
+#define SYSCFG_FASTMODEPLUS_PB6        SYSCFG_PMCR_I2C_PB6_FMP  /*!< Enable Fast-mode Plus on PB6 */
+#define SYSCFG_FASTMODEPLUS_PB7        SYSCFG_PMCR_I2C_PB7_FMP  /*!< Enable Fast-mode Plus on PB7 */
+#define SYSCFG_FASTMODEPLUS_PB8        SYSCFG_PMCR_I2C_PB8_FMP  /*!< Enable Fast-mode Plus on PB8 */
+#define SYSCFG_FASTMODEPLUS_PB9        SYSCFG_PMCR_I2C_PB9_FMP  /*!< Enable Fast-mode Plus on PB9 */
+
+#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
+
+#endif /* ! SYSCFG_PMCR_BOOSTEN */
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_Ethernet_Config  Ethernet Config
+  * @{
+  */
+#define SYSCFG_ETH_MII                      ((uint32_t)0x00000000)  /*!< Select the Media Independent Interface */
+#define SYSCFG_ETH_RMII                     SYSCFG_PMCR_EPIS_SEL_2  /*!< Select the Reduced Media Independent Interface */
+
+#define IS_SYSCFG_ETHERNET_CONFIG(CONFIG) (((CONFIG) == SYSCFG_ETH_MII)        || \
+                                          ((CONFIG) == SYSCFG_ETH_RMII))
+
+/**
+  * @}
+  */
+
+
+/** @defgroup SYSCFG_Analog_Switch_Config  Analog Switch Config
+  * @{
+  */
+#define SYSCFG_SWITCH_PA0                       SYSCFG_PMCR_PA0SO  /*!< Select PA0 analog switch */
+#define SYSCFG_SWITCH_PA1                       SYSCFG_PMCR_PA1SO  /*!< Select PA1 analog switch */
+#define SYSCFG_SWITCH_PC2                       SYSCFG_PMCR_PC2SO  /*!< Select PC2 analog switch */
+#define SYSCFG_SWITCH_PC3                       SYSCFG_PMCR_PC3SO  /*!< Select PC3 analog switch */
+
+
+#define IS_SYSCFG_ANALOG_SWITCH(SWITCH)    ((((SWITCH) & SYSCFG_SWITCH_PA0) == SYSCFG_SWITCH_PA0)|| \
+                                           (((SWITCH) & SYSCFG_SWITCH_PA1) == SYSCFG_SWITCH_PA1) || \
+                                           (((SWITCH) & SYSCFG_SWITCH_PC2) == SYSCFG_SWITCH_PC2) || \
+                                           (((SWITCH) & SYSCFG_SWITCH_PC3) == SYSCFG_SWITCH_PC3))
+
+
+#define SYSCFG_SWITCH_PA0_OPEN                       SYSCFG_PMCR_PA0SO       /*!< PA0 analog switch opened */
+#define SYSCFG_SWITCH_PA0_CLOSE                      ((uint32_t)0x00000000)  /*!< PA0 analog switch closed */
+#define SYSCFG_SWITCH_PA1_OPEN                       SYSCFG_PMCR_PA1SO       /*!< PA1 analog switch opened */
+#define SYSCFG_SWITCH_PA1_CLOSE                      ((uint32_t)0x00000000)  /*!< PA1 analog switch closed*/
+#define SYSCFG_SWITCH_PC2_OPEN                       SYSCFG_PMCR_PC2SO       /*!< PC2 analog switch opened */
+#define SYSCFG_SWITCH_PC2_CLOSE                      ((uint32_t)0x00000000)  /*!< PC2 analog switch closed */
+#define SYSCFG_SWITCH_PC3_OPEN                       SYSCFG_PMCR_PC3SO       /*!< PC3 analog switch opened */
+#define SYSCFG_SWITCH_PC3_CLOSE                      ((uint32_t)0x00000000)  /*!< PC3 analog switch closed */
+
+#define IS_SYSCFG_SWITCH_STATE(STATE)      ((((STATE) & SYSCFG_SWITCH_PA0_OPEN) == SYSCFG_SWITCH_PA0_OPEN)    || \
+                                           (((STATE) & SYSCFG_SWITCH_PA0_CLOSE) == SYSCFG_SWITCH_PA0_CLOSE)   || \
+                                           (((STATE) & SYSCFG_SWITCH_PA1_OPEN) == SYSCFG_SWITCH_PA1_OPEN)     || \
+                                           (((STATE) & SYSCFG_SWITCH_PA1_CLOSE) == SYSCFG_SWITCH_PA1_CLOSE)   || \
+                                           (((STATE) & SYSCFG_SWITCH_PC2_OPEN) == SYSCFG_SWITCH_PC2_OPEN)     || \
+                                           (((STATE) & SYSCFG_SWITCH_PC2_CLOSE) == SYSCFG_SWITCH_PC2_CLOSE)   || \
+                                           (((STATE) & SYSCFG_SWITCH_PC3_OPEN) == SYSCFG_SWITCH_PC3_OPEN)     || \
+                                           (((STATE) & SYSCFG_SWITCH_PC3_CLOSE) == SYSCFG_SWITCH_PC3_CLOSE))
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_Boot_Config  Boot Config
+  * @{
+  */
+#define SYSCFG_BOOT_ADDR0                    ((uint32_t)0x00000000)  /*!< Select Boot address0 */
+#define SYSCFG_BOOT_ADDR1                    ((uint32_t)0x00000001)  /*!< Select Boot address1 */
+
+#define IS_SYSCFG_BOOT_REGISTER(REGISTER) (((REGISTER) == SYSCFG_BOOT_ADDR0)|| \
+                                          ((REGISTER) == SYSCFG_BOOT_ADDR1))
+
+#define IS_SYSCFG_BOOT_ADDRESS(ADDRESS) ((ADDRESS) < PERIPH_BASE)
+
+/**
+  * @}
+  */
+
+
+/** @defgroup SYSCFG_IOCompenstionCell_Config  IOCompenstionCell Config
+  * @{
+  */
+#define SYSCFG_CELL_CODE                    ((uint32_t)0x00000000)  /*!< Select Code from the cell */
+#define SYSCFG_REGISTER_CODE                 SYSCFG_CCCSR_CS        /*!< Code from the SYSCFG compensation cell code register */
+
+#define IS_SYSCFG_CODE_SELECT(SELECT) (((SELECT) == SYSCFG_CELL_CODE)|| \
+                                        ((SELECT) == SYSCFG_REGISTER_CODE))
+
+#define IS_SYSCFG_CODE_CONFIG(CONFIG) ((CONFIG) < (0x10UL))
+
+/**
+  * @}
+  */
+
+
+
+
+/** @defgroup EXTI_Event_Input_Config  Event Input Config
+  * @{
+  */
+
+#define EXTI_MODE_IT          ((uint32_t)0x00010000)
+#define EXTI_MODE_EVT         ((uint32_t)0x00020000)
+#define EXTI_RISING_EDGE      ((uint32_t)0x00100000)
+#define EXTI_FALLING_EDGE     ((uint32_t)0x00200000)
+
+#define IS_EXTI_EDGE_LINE(EDGE) (((EDGE) == EXTI_RISING_EDGE) || ((EDGE) == EXTI_FALLING_EDGE))
+#define IS_EXTI_MODE_LINE(MODE) (((MODE) == EXTI_MODE_IT) || ((MODE) == EXTI_MODE_EVT))
+
+#define EXTI_LINE0       ((uint32_t)0x00)  /*!< External interrupt LINE 0  */
+#define EXTI_LINE1       ((uint32_t)0x01)  /*!< External interrupt LINE 1  */
+#define EXTI_LINE2       ((uint32_t)0x02)  /*!< External interrupt LINE 2  */
+#define EXTI_LINE3       ((uint32_t)0x03)  /*!< External interrupt LINE 3  */
+#define EXTI_LINE4       ((uint32_t)0x04)  /*!< External interrupt LINE 4  */
+#define EXTI_LINE5       ((uint32_t)0x05)  /*!< External interrupt LINE 5  */
+#define EXTI_LINE6       ((uint32_t)0x06)  /*!< External interrupt LINE 6  */
+#define EXTI_LINE7       ((uint32_t)0x07)  /*!< External interrupt LINE 7  */
+#define EXTI_LINE8       ((uint32_t)0x08)  /*!< External interrupt LINE 8  */
+#define EXTI_LINE9       ((uint32_t)0x09)  /*!< External interrupt LINE 9  */
+#define EXTI_LINE10      ((uint32_t)0x0A)  /*!< External interrupt LINE 10 */
+#define EXTI_LINE11      ((uint32_t)0x0B)  /*!< External interrupt LINE 11 */
+#define EXTI_LINE12      ((uint32_t)0x0C)  /*!< External interrupt LINE 12 */
+#define EXTI_LINE13      ((uint32_t)0x0D)  /*!< External interrupt LINE 13 */
+#define EXTI_LINE14      ((uint32_t)0x0E)  /*!< External interrupt LINE 14 */
+#define EXTI_LINE15      ((uint32_t)0x0F)  /*!< External interrupt LINE 15 */
+#define EXTI_LINE16      ((uint32_t)0x10)
+#define EXTI_LINE17      ((uint32_t)0x11)
+#define EXTI_LINE18      ((uint32_t)0x12)
+#define EXTI_LINE19      ((uint32_t)0x13)
+#define EXTI_LINE20      ((uint32_t)0x14)
+#define EXTI_LINE21      ((uint32_t)0x15)
+#define EXTI_LINE22      ((uint32_t)0x16)
+#define EXTI_LINE23      ((uint32_t)0x17)
+#define EXTI_LINE24      ((uint32_t)0x18)
+#define EXTI_LINE25      ((uint32_t)0x19)
+#define EXTI_LINE26      ((uint32_t)0x1A)
+#define EXTI_LINE27      ((uint32_t)0x1B)
+#define EXTI_LINE28      ((uint32_t)0x1C)
+#define EXTI_LINE29      ((uint32_t)0x1D)
+#define EXTI_LINE30      ((uint32_t)0x1E)
+#define EXTI_LINE31      ((uint32_t)0x1F)
+#define EXTI_LINE32      ((uint32_t)0x20)
+#define EXTI_LINE33      ((uint32_t)0x21)
+#define EXTI_LINE34      ((uint32_t)0x22)
+#define EXTI_LINE35      ((uint32_t)0x23)
+#define EXTI_LINE36      ((uint32_t)0x24)
+#define EXTI_LINE37      ((uint32_t)0x25)
+#define EXTI_LINE38      ((uint32_t)0x26)
+#define EXTI_LINE39      ((uint32_t)0x27)
+
+#define EXTI_LINE40      ((uint32_t)0x28)
+#define EXTI_LINE41      ((uint32_t)0x29)
+#define EXTI_LINE42      ((uint32_t)0x2A)
+#define EXTI_LINE43      ((uint32_t)0x2B)
+#define EXTI_LINE44      ((uint32_t)0x2C)  /* Not available in all family lines */
+/* EXTI_LINE45 Reserved */
+#if defined(DUAL_CORE)
+#define EXTI_LINE46      ((uint32_t)0x2E)
+#else
+/* EXTI_LINE46 Reserved */
+#endif /* DUAL_CORE */
+#define EXTI_LINE47      ((uint32_t)0x2F)
+#define EXTI_LINE48      ((uint32_t)0x30)
+#define EXTI_LINE49      ((uint32_t)0x31)
+#define EXTI_LINE50      ((uint32_t)0x32)
+#define EXTI_LINE51      ((uint32_t)0x33)
+#define EXTI_LINE52      ((uint32_t)0x34)
+#define EXTI_LINE53      ((uint32_t)0x35)
+#define EXTI_LINE54      ((uint32_t)0x36)
+#define EXTI_LINE55      ((uint32_t)0x37)
+#define EXTI_LINE56      ((uint32_t)0x38)
+#define EXTI_LINE57      ((uint32_t)0x39)
+#define EXTI_LINE58      ((uint32_t)0x3A)
+#define EXTI_LINE59      ((uint32_t)0x3B)
+#define EXTI_LINE60      ((uint32_t)0x3C)
+#define EXTI_LINE61      ((uint32_t)0x3D)
+#define EXTI_LINE62      ((uint32_t)0x3E)
+#define EXTI_LINE63      ((uint32_t)0x3F)
+#define EXTI_LINE64      ((uint32_t)0x40)
+#define EXTI_LINE65      ((uint32_t)0x41)
+#define EXTI_LINE66      ((uint32_t)0x42)
+#define EXTI_LINE67      ((uint32_t)0x43)
+#define EXTI_LINE68      ((uint32_t)0x44)
+#define EXTI_LINE69      ((uint32_t)0x45)
+#define EXTI_LINE70      ((uint32_t)0x46)
+#define EXTI_LINE71      ((uint32_t)0x47)
+#define EXTI_LINE72      ((uint32_t)0x48)
+#define EXTI_LINE73      ((uint32_t)0x49)
+#define EXTI_LINE74      ((uint32_t)0x4A)
+#define EXTI_LINE75      ((uint32_t)0x4B)  /* Not available in all family lines */
+#define EXTI_LINE76      ((uint32_t)0x4C)  /* Not available in all family lines */
+#if defined(DUAL_CORE)
+#define EXTI_LINE77      ((uint32_t)0x4D)
+#define EXTI_LINE78      ((uint32_t)0x4E)
+#define EXTI_LINE79      ((uint32_t)0x4F)
+#define EXTI_LINE80      ((uint32_t)0x50)
+#else
+/* EXTI_LINE77 Reserved */
+/* EXTI_LINE78 Reserved */
+/* EXTI_LINE79 Reserved */
+/* EXTI_LINE80 Reserved */
+#endif /* DUAL_CORE */
+/* EXTI_LINE81   Reserved */
+#if defined(DUAL_CORE)
+#define EXTI_LINE82      ((uint32_t)0x52)
+#else
+/* EXTI_LINE82 Reserved */
+#endif /* DUAL_CORE */
+/* EXTI_LINE83   Reserved */
+#if defined(DUAL_CORE)
+#define EXTI_LINE84      ((uint32_t)0x54)
+#else
+/* EXTI_LINE84 Reserved */
+#endif /* DUAL_CORE */
+#define EXTI_LINE85      ((uint32_t)0x55)
+#define EXTI_LINE86      ((uint32_t)0x56)  /* Not available in all family lines */
+#define EXTI_LINE87      ((uint32_t)0x57)
+#define EXTI_LINE88      ((uint32_t)0x58)  /* Not available in all family lines */
+
+#if defined(DUAL_CORE)
+#define IS_HAL_EXTI_CONFIG_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \
+                                ((LINE) == EXTI_LINE2)  || ((LINE) == EXTI_LINE3)   || \
+                                ((LINE) == EXTI_LINE4)  || ((LINE) == EXTI_LINE5)   || \
+                                ((LINE) == EXTI_LINE6)  || ((LINE) == EXTI_LINE7)   || \
+                                ((LINE) == EXTI_LINE8)  || ((LINE) == EXTI_LINE9)   || \
+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11)  || \
+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13)  || \
+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15)  || \
+                                ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17)  || \
+                                ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19)  || \
+                                ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21)  || \
+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE51)  || \
+                                ((LINE) == EXTI_LINE82) || ((LINE) == EXTI_LINE84)  || \
+                                ((LINE) == EXTI_LINE85) || ((LINE) == EXTI_LINE86))
+#else
+#define IS_HAL_EXTI_CONFIG_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1)|| \
+                                ((LINE) == EXTI_LINE2)  || ((LINE) == EXTI_LINE3)   || \
+                                ((LINE) == EXTI_LINE4)  || ((LINE) == EXTI_LINE5)   || \
+                                ((LINE) == EXTI_LINE6)  || ((LINE) == EXTI_LINE7)   || \
+                                ((LINE) == EXTI_LINE8)  || ((LINE) == EXTI_LINE9)   || \
+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
+                                ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
+                                ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
+                                ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE51) || \
+                                ((LINE) == EXTI_LINE85) || ((LINE) == EXTI_LINE86))
+#endif /* DUAL_CORE */
+
+#if defined(DUAL_CORE)
+#define IS_EXTI_ALL_LINE(LINE) (((LINE) == EXTI_LINE0)  || ((LINE) == EXTI_LINE1)  || \
+                                ((LINE) == EXTI_LINE2)  || ((LINE) == EXTI_LINE3)  || \
+                                ((LINE) == EXTI_LINE4)  || ((LINE) == EXTI_LINE5)  || \
+                                ((LINE) == EXTI_LINE6)  || ((LINE) == EXTI_LINE7)  || \
+                                ((LINE) == EXTI_LINE8)  || ((LINE) == EXTI_LINE9)  || \
+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
+                                ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
+                                ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
+                                ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
+                                ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \
+                                ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \
+                                ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \
+                                ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \
+                                ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \
+                                ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \
+                                ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
+                                ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \
+                                ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \
+                                ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \
+                                ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \
+                                ((LINE) == EXTI_LINE44) || ((LINE) == EXTI_LINE46) || \
+                                ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \
+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
+                                ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
+                                ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \
+                                ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \
+                                ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \
+                                ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \
+                                ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \
+                                ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \
+                                ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \
+                                ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \
+                                ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \
+                                ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \
+                                ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \
+                                ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
+                                ((LINE) == EXTI_LINE77) || ((LINE) == EXTI_LINE79) || \
+                                ((LINE) == EXTI_LINE84) || ((LINE) == EXTI_LINE85) || \
+                                ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87) || \
+                                ((LINE) == EXTI_LINE78) || \
+                                ((LINE) == EXTI_LINE80) || ((LINE) == EXTI_LINE82))
+#else
+#define IS_EXTI_ALL_LINE(LINE) (((LINE) == EXTI_LINE0)  || ((LINE) == EXTI_LINE1)  || \
+                                ((LINE) == EXTI_LINE2)  || ((LINE) == EXTI_LINE3)  || \
+                                ((LINE) == EXTI_LINE4)  || ((LINE) == EXTI_LINE5)  || \
+                                ((LINE) == EXTI_LINE6)  || ((LINE) == EXTI_LINE7)  || \
+                                ((LINE) == EXTI_LINE8)  || ((LINE) == EXTI_LINE9)  || \
+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
+                                ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
+                                ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
+                                ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
+                                ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \
+                                ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \
+                                ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \
+                                ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \
+                                ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \
+                                ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \
+                                ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
+                                ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \
+                                ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \
+                                ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \
+                                ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \
+                                ((LINE) == EXTI_LINE44) || \
+                                ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \
+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
+                                ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
+                                ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \
+                                ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \
+                                ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \
+                                ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \
+                                ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \
+                                ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \
+                                ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \
+                                ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \
+                                ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \
+                                ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \
+                                ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \
+                                ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
+                                ((LINE) == EXTI_LINE85) || \
+                                ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87) || \
+                                ((LINE) == EXTI_LINE88))
+#endif /*DUAL_CORE*/
+
+#if defined(DUAL_CORE)
+#define IS_EXTI_D1_LINE(LINE) (((LINE) == EXTI_LINE0)  || ((LINE) == EXTI_LINE1)  || \
+                                ((LINE) == EXTI_LINE2)  || ((LINE) == EXTI_LINE3)  || \
+                                ((LINE) == EXTI_LINE4)  || ((LINE) == EXTI_LINE5)  || \
+                                ((LINE) == EXTI_LINE6)  || ((LINE) == EXTI_LINE7)  || \
+                                ((LINE) == EXTI_LINE8)  || ((LINE) == EXTI_LINE9)  || \
+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
+                                ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
+                                ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
+                                ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
+                                ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \
+                                ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \
+                                ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \
+                                ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \
+                                ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \
+                                ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \
+                                ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
+                                ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \
+                                ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \
+                                ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \
+                                ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \
+                                ((LINE) == EXTI_LINE44) || ((LINE) == EXTI_LINE46) || \
+                                ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \
+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
+                                ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
+                                ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \
+                                ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \
+                                ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \
+                                ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \
+                                ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \
+                                ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \
+                                ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \
+                                ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \
+                                ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \
+                                ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \
+                                ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \
+                                ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
+                                ((LINE) == EXTI_LINE77) || ((LINE) == EXTI_LINE79) || \
+                                ((LINE) == EXTI_LINE84) || ((LINE) == EXTI_LINE85) || \
+                                ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87))
+#else
+#define IS_EXTI_D1_LINE(LINE) (((LINE) == EXTI_LINE0)  || ((LINE) == EXTI_LINE1)  || \
+                                ((LINE) == EXTI_LINE2)  || ((LINE) == EXTI_LINE3)  || \
+                                ((LINE) == EXTI_LINE4)  || ((LINE) == EXTI_LINE5)  || \
+                                ((LINE) == EXTI_LINE6)  || ((LINE) == EXTI_LINE7)  || \
+                                ((LINE) == EXTI_LINE8)  || ((LINE) == EXTI_LINE9)  || \
+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
+                                ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
+                                ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
+                                ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
+                                ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \
+                                ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \
+                                ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \
+                                ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \
+                                ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \
+                                ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \
+                                ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
+                                ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \
+                                ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \
+                                ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \
+                                ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \
+                                ((LINE) == EXTI_LINE44) || \
+                                ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \
+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
+                                ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
+                                ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \
+                                ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \
+                                ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \
+                                ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \
+                                ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \
+                                ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \
+                                ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \
+                                ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \
+                                ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \
+                                ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \
+                                ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \
+                                ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
+                                ((LINE) == EXTI_LINE85) || \
+                                ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87) || \
+                                ((LINE) == EXTI_LINE88))
+#endif /*DUAL_CORE*/
+
+#if defined(DUAL_CORE)
+#define IS_EXTI_D2_LINE(LINE) (((LINE) == EXTI_LINE0)  || ((LINE) == EXTI_LINE1)    || \
+                                ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3)   || \
+                                ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5)   || \
+                                ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7)   || \
+                                ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9)   || \
+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
+                                ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
+                                ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
+                                ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
+                                ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \
+                                ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \
+                                ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \
+                                ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \
+                                ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \
+                                ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \
+                                ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
+                                ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \
+                                ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \
+                                ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \
+                                ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \
+                                ((LINE) == EXTI_LINE44) || ((LINE) == EXTI_LINE46) || \
+                                ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \
+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
+                                ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
+                                ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \
+                                ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \
+                                ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \
+                                ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \
+                                ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \
+                                ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \
+                                ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \
+                                ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \
+                                ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \
+                                ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \
+                                ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \
+                                ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
+                                ((LINE) == EXTI_LINE78) || ((LINE) == EXTI_LINE80) || \
+                                ((LINE) == EXTI_LINE82) || ((LINE) == EXTI_LINE85) || \
+                                ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87))
+#endif /*DUAL_CORE*/
+
+#if defined(DUAL_CORE)
+#define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1)    || \
+                                ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3)   || \
+                                ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5)   || \
+                                ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7)   || \
+                                ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9)   || \
+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
+                                ((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || \
+                                ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE25) || \
+                                ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
+                                ((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || \
+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
+                                ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
+                                ((LINE) == EXTI_LINE53))
+#elif (POWER_DOMAINS_NUMBER == 3U)
+#define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1)    || \
+                                ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3)   || \
+                                ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5)   || \
+                                ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7)   || \
+                                ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9)   || \
+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
+                                ((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || \
+                                ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE25) || \
+                                ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
+                                ((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || \
+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
+                                ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
+                                ((LINE) == EXTI_LINE53))
+#else
+#define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1)    || \
+                                ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3)   || \
+                                ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5)   || \
+                                ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7)   || \
+                                ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9)   || \
+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
+                                ((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || \
+                                ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE25) || \
+                                ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
+                                ((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || \
+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
+                                ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE88))
+#endif /*DUAL_CORE*/
+
+
+#define  BDMA_CH6_CLEAR           ((uint32_t)0x00000000)   /*!< BDMA ch6 event selected as D3 domain pendclear source*/
+#define  BDMA_CH7_CLEAR           ((uint32_t)0x00000001)   /*!< BDMA ch7 event selected as D3 domain pendclear source*/
+#if defined (LPTIM4)
+#define  LPTIM4_OUT_CLEAR         ((uint32_t)0x00000002)   /*!< LPTIM4 out selected as D3 domain pendclear source*/
+#else
+#define  LPTIM2_OUT_CLEAR         ((uint32_t)0x00000002)   /*!< LPTIM2 out selected as D3 domain pendclear source*/
+#endif /* LPTIM4 */
+#if defined (LPTIM5)
+#define  LPTIM5_OUT_CLEAR         ((uint32_t)0x00000003)   /*!< LPTIM5 out selected as D3 domain pendclear source*/
+#else
+#define  LPTIM3_OUT_CLEAR         ((uint32_t)0x00000003)   /*!< LPTIM3 out selected as D3 domain pendclear source*/
+#endif /* LPTIM5 */
+#if defined (LPTIM4) && defined (LPTIM5)
+#define IS_EXTI_D3_CLEAR(SOURCE) (((SOURCE) == BDMA_CH6_CLEAR) || ((SOURCE) == BDMA_CH7_CLEAR)    || \
+                                 ((SOURCE) == LPTIM4_OUT_CLEAR) || ((SOURCE) == LPTIM5_OUT_CLEAR))
+#else
+#define IS_EXTI_D3_CLEAR(SOURCE) (((SOURCE) == BDMA_CH6_CLEAR) || ((SOURCE) == BDMA_CH7_CLEAR)    || \
+                                 ((SOURCE) == LPTIM2_OUT_CLEAR) || ((SOURCE) == LPTIM3_OUT_CLEAR))
+#endif /* LPTIM4 LPTIM5 */
+/**
+  * @}
+  */
+
+
+/** @defgroup FMC_SwapBankMapping_Config  SwapBankMapping Config
+  * @{
+  */
+#define FMC_SWAPBMAP_DISABLE             (0x00000000U)
+#define FMC_SWAPBMAP_SDRAM_SRAM          FMC_BCR1_BMAP_0
+#define FMC_SWAPBMAP_SDRAMB2             FMC_BCR1_BMAP_1
+
+#define IS_FMC_SWAPBMAP_MODE(__MODE__) (((__MODE__) == FMC_SWAPBMAP_DISABLE)    || \
+                                        ((__MODE__) == FMC_SWAPBMAP_SDRAM_SRAM) || \
+                                        ((__MODE__) == FMC_SWAPBMAP_SDRAMB2))
+/**
+  * @}
+  */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup ART_Exported_Macros ART Exported Macros
+  * @{
+  */
+#if defined(DUAL_CORE)
+
+/** @brief  ART Enable Macro.
+  *         Enable the Cortex-M4 ART cache.
+  */
+#define __HAL_ART_ENABLE()   SET_BIT(ART->CTR, ART_CTR_EN)
+
+/** @brief  ART Disable Macro.
+  *         Disable the Cortex-M4 ART cache.
+  */
+#define __HAL_ART_DISABLE()   CLEAR_BIT(ART->CTR, ART_CTR_EN)
+
+/** @brief  ART Cache BaseAddress Config.
+  *         Configure the Cortex-M4 ART cache Base Address.
+  */
+#define __HAL_ART_CONFIG_BASE_ADDRESS(__BASE_ADDRESS__)   MODIFY_REG(ART->CTR, ART_CTR_PCACHEADDR, (((__BASE_ADDRESS__) >> 12U) & 0x000FFF00UL))
+
+#endif /* DUAL_CORE */
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
+  * @{
+  */
+
+/** @brief  SYSCFG Break AXIRAM double ECC lock.
+  *         Enable and lock the connection of AXIRAM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_AXISRAM_DBL_ECC_LOCK()     SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML)
+
+/** @brief  SYSCFG Break ITCM double ECC lock.
+  *         Enable and lock the connection of ITCM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_ITCM_DBL_ECC_LOCK()        SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_ITCML)
+
+/** @brief  SYSCFG Break DTCM double ECC lock.
+  *         Enable and lock the connection of DTCM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_DTCM_DBL_ECC_LOCK()        SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_DTCML)
+
+/** @brief  SYSCFG Break SRAM1 double ECC lock.
+  *         Enable and lock the connection of SRAM1 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_SRAM1_DBL_ECC_LOCK()       SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM1L)
+
+/** @brief  SYSCFG Break SRAM2 double ECC lock.
+  *         Enable and lock the connection of SRAM2 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_SRAM2_DBL_ECC_LOCK()       SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM2L)
+
+/** @brief  SYSCFG Break SRAM3 double ECC lock.
+  *         Enable and lock the connection of SRAM3 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_SRAM3_DBL_ECC_LOCK()       SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM3L)
+
+/** @brief  SYSCFG Break SRAM4 double ECC lock.
+  *         Enable and lock the connection of SRAM4 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_SRAM4_DBL_ECC_LOCK()       SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM4L)
+
+/** @brief  SYSCFG Break Backup SRAM double ECC lock.
+  *         Enable and lock the connection of Backup SRAM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_BKRAM_DBL_ECC_LOCK()       SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_BKRAML)
+
+/** @brief  SYSCFG Break Cortex-M7 Lockup lock.
+  *         Enable and lock the connection of Cortex-M7 LOCKUP output to TIM1/8/15/16/17 and HRTIMER Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_CM7_LOCKUP_LOCK()          SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_CM7L)
+
+/** @brief  SYSCFG Break FLASH double ECC lock.
+  *         Enable and lock the connection of Flash double ECC error connection to TIM1/8/15/16/17 and HRTIMER Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_FLASH_DBL_ECC_LOCK()       SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_FLASHL)
+
+/** @brief  SYSCFG Break PVD lock.
+  *         Enable and lock the PVD connection to Timer1/8/15/16/17 and HRTIMER Break input, as well as the PVDE and PLS[2:0] in the PWR_CR1 register.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_PVD_LOCK()                 SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_PVDL)
+
+#if defined(DUAL_CORE)
+/** @brief  SYSCFG Break Cortex-M4 Lockup lock.
+  *         Enable and lock the connection of Cortex-M4 LOCKUP output to TIM1/8/15/16/17 and HRTIMER Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_CM4_LOCKUP_LOCK()          SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_CM4L)
+#endif /* DUAL_CORE */
+
+#if !defined(SYSCFG_PMCR_BOOSTEN)
+/** @brief  Fast-mode Plus driving capability enable/disable macros
+  * @param __FASTMODEPLUS__  This parameter can be a value of :
+  *     @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6
+  *     @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7
+  *     @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8
+  *     @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9
+  */
+#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)  do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
+                                                                SET_BIT(SYSCFG->PMCR, (__FASTMODEPLUS__));\
+                                                               }while(0)
+
+#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
+                                                                CLEAR_BIT(SYSCFG->PMCR, (__FASTMODEPLUS__));\
+                                                               }while(0)
+
+#endif /* !SYSCFG_PMCR_BOOSTEN */
+/**
+  * @}
+  */
+
+/** @brief  Freeze/Unfreeze Peripherals in Debug mode
+  */
+#define __HAL_DBGMCU_FREEZE_WWDG1()          (DBGMCU->APB3FZ1 |= (DBGMCU_APB3FZ1_DBG_WWDG1))
+
+#define __HAL_DBGMCU_FREEZE_TIM2()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM2))
+#define __HAL_DBGMCU_FREEZE_TIM3()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM3))
+#define __HAL_DBGMCU_FREEZE_TIM4()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM4))
+#define __HAL_DBGMCU_FREEZE_TIM5()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM5))
+#define __HAL_DBGMCU_FREEZE_TIM6()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM6))
+#define __HAL_DBGMCU_FREEZE_TIM7()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM7))
+#define __HAL_DBGMCU_FREEZE_TIM12()          (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM12))
+#define __HAL_DBGMCU_FREEZE_TIM13()          (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM13))
+#define __HAL_DBGMCU_FREEZE_TIM14()          (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM14))
+#define __HAL_DBGMCU_FREEZE_LPTIM1()         (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_LPTIM1))
+#define __HAL_DBGMCU_FREEZE_I2C1()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C1))
+#define __HAL_DBGMCU_FREEZE_I2C2()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C2))
+#define __HAL_DBGMCU_FREEZE_I2C3()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C3))
+#define __HAL_DBGMCU_FREEZE_FDCAN()          (DBGMCU->APB1HFZ1 |= (DBGMCU_APB1HFZ1_DBG_FDCAN))
+
+
+#define __HAL_DBGMCU_FREEZE_TIM1()           (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM1))
+#define __HAL_DBGMCU_FREEZE_TIM8()           (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM8))
+#define __HAL_DBGMCU_FREEZE_TIM15()          (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM15))
+#define __HAL_DBGMCU_FREEZE_TIM16()          (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM16))
+#define __HAL_DBGMCU_FREEZE_TIM17()          (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM17))
+#define __HAL_DBGMCU_FREEZE_HRTIM()          (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_HRTIM))
+
+#define __HAL_DBGMCU_FREEZE_I2C4()           (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_I2C4))
+#define __HAL_DBGMCU_FREEZE_LPTIM2()         (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM2))
+#define __HAL_DBGMCU_FREEZE_LPTIM3()         (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM3))
+#define __HAL_DBGMCU_FREEZE_LPTIM4()         (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM4))
+#define __HAL_DBGMCU_FREEZE_LPTIM5()         (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM5))
+#define __HAL_DBGMCU_FREEZE_RTC()            (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_RTC))
+#define __HAL_DBGMCU_FREEZE_IWDG1()          (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_IWDG1))
+
+
+#define __HAL_DBGMCU_UnFreeze_WWDG1()          (DBGMCU->APB3FZ1  &= ~ (DBGMCU_APB3FZ1_DBG_WWDG1))
+
+#define __HAL_DBGMCU_UnFreeze_TIM2()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM2))
+#define __HAL_DBGMCU_UnFreeze_TIM3()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM3))
+#define __HAL_DBGMCU_UnFreeze_TIM4()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM4))
+#define __HAL_DBGMCU_UnFreeze_TIM5()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM5))
+#define __HAL_DBGMCU_UnFreeze_TIM6()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM6))
+#define __HAL_DBGMCU_UnFreeze_TIM7()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM7))
+#define __HAL_DBGMCU_UnFreeze_TIM12()          (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM12))
+#define __HAL_DBGMCU_UnFreeze_TIM13()          (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM13))
+#define __HAL_DBGMCU_UnFreeze_TIM14()          (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM14))
+#define __HAL_DBGMCU_UnFreeze_LPTIM1()         (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_LPTIM1))
+#define __HAL_DBGMCU_UnFreeze_I2C1()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_I2C1))
+#define __HAL_DBGMCU_UnFreeze_I2C2()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_I2C2))
+#define __HAL_DBGMCU_UnFreeze_I2C3()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_I2C3))
+#define __HAL_DBGMCU_UnFreeze_FDCAN()          (DBGMCU->APB1HFZ1  &= ~ (DBGMCU_APB1HFZ1_DBG_FDCAN))
+
+
+#define __HAL_DBGMCU_UnFreeze_TIM1()           (DBGMCU->APB2FZ1  &= ~ (DBGMCU_APB2FZ1_DBG_TIM1))
+#define __HAL_DBGMCU_UnFreeze_TIM8()           (DBGMCU->APB2FZ1  &= ~ (DBGMCU_APB2FZ1_DBG_TIM8))
+#define __HAL_DBGMCU_UnFreeze_TIM15()          (DBGMCU->APB2FZ1  &= ~ (DBGMCU_APB2FZ1_DBG_TIM15))
+#define __HAL_DBGMCU_UnFreeze_TIM16()          (DBGMCU->APB2FZ1  &= ~ (DBGMCU_APB2FZ1_DBG_TIM16))
+#define __HAL_DBGMCU_UnFreeze_TIM17()          (DBGMCU->APB2FZ1  &= ~ (DBGMCU_APB2FZ1_DBG_TIM17))
+#define __HAL_DBGMCU_UnFreeze_HRTIM()          (DBGMCU->APB2FZ1  &= ~ (DBGMCU_APB2FZ1_DBG_HRTIM))
+
+#define __HAL_DBGMCU_UnFreeze_I2C4()           (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_I2C4))
+#define __HAL_DBGMCU_UnFreeze_LPTIM2()         (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM2))
+#define __HAL_DBGMCU_UnFreeze_LPTIM3()         (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM3))
+#define __HAL_DBGMCU_UnFreeze_LPTIM4()         (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM4))
+#define __HAL_DBGMCU_UnFreeze_LPTIM5()         (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM5))
+#define __HAL_DBGMCU_UnFreeze_RTC()            (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_RTC))
+#define __HAL_DBGMCU_UnFreeze_IWDG1()          (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_IWDG1))
+
+
+#if defined(DUAL_CORE)
+#define __HAL_DBGMCU_FREEZE2_IWDG2()          (DBGMCU->APB4FZ2  |= (DBGMCU_APB4FZ2_DBG_IWDG2))
+#define __HAL_DBGMCU_FREEZE2_WWDG2()          (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_WWDG2))
+
+#define __HAL_DBGMCU_UnFreeze2_IWDG2()        (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_IWDG2))
+#define __HAL_DBGMCU_UnFreeze2_WWDG2()        (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_WWDG2))
+
+
+#define __HAL_DBGMCU_FREEZE2_WWDG1()          (DBGMCU->APB3FZ2 |= (DBGMCU_APB3FZ2_DBG_WWDG1))
+
+#define __HAL_DBGMCU_FREEZE2_TIM2()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM2))
+#define __HAL_DBGMCU_FREEZE2_TIM3()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM3))
+#define __HAL_DBGMCU_FREEZE2_TIM4()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM4))
+#define __HAL_DBGMCU_FREEZE2_TIM5()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM5))
+#define __HAL_DBGMCU_FREEZE2_TIM6()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM6))
+#define __HAL_DBGMCU_FREEZE2_TIM7()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM7))
+#define __HAL_DBGMCU_FREEZE2_TIM12()          (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM12))
+#define __HAL_DBGMCU_FREEZE2_TIM13()          (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM13))
+#define __HAL_DBGMCU_FREEZE2_TIM14()          (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM14))
+#define __HAL_DBGMCU_FREEZE2_LPTIM1()         (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_LPTIM1))
+#define __HAL_DBGMCU_FREEZE2_I2C1()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_I2C1))
+#define __HAL_DBGMCU_FREEZE2_I2C2()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_I2C2))
+#define __HAL_DBGMCU_FREEZE2_I2C3()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_I2C3))
+#define __HAL_DBGMCU_FREEZE2_FDCAN()          (DBGMCU->APB1HFZ2 |= (DBGMCU_APB1HFZ2_DBG_FDCAN))
+
+
+#define __HAL_DBGMCU_FREEZE2_TIM1()           (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM1))
+#define __HAL_DBGMCU_FREEZE2_TIM8()           (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM8))
+#define __HAL_DBGMCU_FREEZE2_TIM15()          (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM15))
+#define __HAL_DBGMCU_FREEZE2_TIM16()          (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM16))
+#define __HAL_DBGMCU_FREEZE2_TIM17()          (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM17))
+#define __HAL_DBGMCU_FREEZE2_HRTIM()          (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_HRTIM))
+
+#define __HAL_DBGMCU_FREEZE2_I2C4()           (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_I2C4))
+#define __HAL_DBGMCU_FREEZE2_LPTIM2()         (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM2))
+#define __HAL_DBGMCU_FREEZE2_LPTIM3()         (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM3))
+#define __HAL_DBGMCU_FREEZE2_LPTIM4()         (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM4))
+#define __HAL_DBGMCU_FREEZE2_LPTIM5()         (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM5))
+#define __HAL_DBGMCU_FREEZE2_RTC()            (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_RTC))
+#define __HAL_DBGMCU_FREEZE2_IWDG1()          (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_IWDG1))
+
+#define __HAL_DBGMCU_UnFreeze2_WWDG1()          (DBGMCU->APB3FZ2  &= ~ (DBGMCU_APB3FZ2_DBG_WWDG1))
+
+#define __HAL_DBGMCU_UnFreeze2_TIM2()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM2))
+#define __HAL_DBGMCU_UnFreeze2_TIM3()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM3))
+#define __HAL_DBGMCU_UnFreeze2_TIM4()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM4))
+#define __HAL_DBGMCU_UnFreeze2_TIM5()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM5))
+#define __HAL_DBGMCU_UnFreeze2_TIM6()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM6))
+#define __HAL_DBGMCU_UnFreeze2_TIM7()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM7))
+#define __HAL_DBGMCU_UnFreeze2_TIM12()          (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM12))
+#define __HAL_DBGMCU_UnFreeze2_TIM13()          (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM13))
+#define __HAL_DBGMCU_UnFreeze2_TIM14()          (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM14))
+#define __HAL_DBGMCU_UnFreeze2_LPTIM1()         (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_LPTIM1))
+#define __HAL_DBGMCU_UnFreeze2_I2C1()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_I2C1))
+#define __HAL_DBGMCU_UnFreeze2_I2C2()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_I2C2))
+#define __HAL_DBGMCU_UnFreeze2_I2C3()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_I2C3))
+#define __HAL_DBGMCU_UnFreeze2_FDCAN()          (DBGMCU->APB1HFZ2  &= ~ (DBGMCU_APB1HFZ2_DBG_FDCAN))
+
+
+#define __HAL_DBGMCU_UnFreeze2_TIM1()           (DBGMCU->APB2FZ2  &= ~ (DBGMCU_APB2FZ2_DBG_TIM1))
+#define __HAL_DBGMCU_UnFreeze2_TIM8()           (DBGMCU->APB2FZ2  &= ~ (DBGMCU_APB2FZ2_DBG_TIM8))
+#define __HAL_DBGMCU_UnFreeze2_TIM15()          (DBGMCU->APB2FZ2  &= ~ (DBGMCU_APB2FZ2_DBG_TIM15))
+#define __HAL_DBGMCU_UnFreeze2_TIM16()          (DBGMCU->APB2FZ2  &= ~ (DBGMCU_APB2FZ2_DBG_TIM16))
+#define __HAL_DBGMCU_UnFreeze2_TIM17()          (DBGMCU->APB2FZ2  &= ~ (DBGMCU_APB2FZ2_DBG_TIM17))
+#define __HAL_DBGMCU_UnFreeze2_HRTIM()          (DBGMCU->APB2FZ2  &= ~ (DBGMCU_APB2FZ2_DBG_HRTIM))
+
+#define __HAL_DBGMCU_UnFreeze2_I2C4()           (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_I2C4))
+#define __HAL_DBGMCU_UnFreeze2_LPTIM2()         (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM2))
+#define __HAL_DBGMCU_UnFreeze2_LPTIM3()         (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM3))
+#define __HAL_DBGMCU_UnFreeze2_LPTIM4()         (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM4))
+#define __HAL_DBGMCU_UnFreeze2_LPTIM5()         (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM5))
+#define __HAL_DBGMCU_UnFreeze2_RTC()            (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_RTC))
+#define __HAL_DBGMCU_UnFreeze2_IWDG1()          (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_IWDG1))
+
+#endif /*DUAL_CORE*/
+
+/** @defgroup HAL_Private_Macros HAL Private Macros
+  * @{
+  */
+#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ)  || \
+                           ((FREQ) == HAL_TICK_FREQ_100HZ) || \
+                           ((FREQ) == HAL_TICK_FREQ_1KHZ))
+/**
+  * @}
+  */
+
+/* Exported variables --------------------------------------------------------*/
+
+/** @addtogroup HAL_Exported_Variables
+  * @{
+  */
+extern __IO uint32_t uwTick;
+extern uint32_t uwTickPrio;
+extern HAL_TickFreqTypeDef uwTickFreq;
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization and de-initialization functions  ******************************/
+HAL_StatusTypeDef HAL_Init(void);
+HAL_StatusTypeDef HAL_DeInit(void);
+void HAL_MspInit(void);
+void HAL_MspDeInit(void);
+HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
+
+/* Peripheral Control functions  ************************************************/
+void HAL_IncTick(void);
+void HAL_Delay(uint32_t Delay);
+uint32_t HAL_GetTick(void);
+uint32_t HAL_GetTickPrio(void);
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
+HAL_TickFreqTypeDef HAL_GetTickFreq(void);
+void HAL_SuspendTick(void);
+void HAL_ResumeTick(void);
+uint32_t HAL_GetHalVersion(void);
+uint32_t HAL_GetREVID(void);
+uint32_t HAL_GetDEVID(void);
+uint32_t HAL_GetUIDw0(void);
+uint32_t HAL_GetUIDw1(void);
+uint32_t HAL_GetUIDw2(void);
+#if defined(SYSCFG_PMCR_EPIS_SEL)
+void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface);
+#endif /* SYSCFG_PMCR_EPIS_SEL */
+void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState );
+#if defined(SYSCFG_PMCR_BOOSTEN)
+void HAL_SYSCFG_EnableBOOST(void);
+void HAL_SYSCFG_DisableBOOST(void);
+#endif /* SYSCFG_PMCR_BOOSTEN */
+
+#if defined (SYSCFG_UR2_BOOT_ADD0) ||  defined (SYSCFG_UR2_BCM7_ADD0)
+void HAL_SYSCFG_CM7BootAddConfig(uint32_t BootRegister, uint32_t BootAddress);
+#endif /* SYSCFG_UR2_BOOT_ADD0 || SYSCFG_UR2_BCM7_ADD0*/
+
+#if defined(DUAL_CORE)
+void HAL_SYSCFG_CM4BootAddConfig(uint32_t BootRegister, uint32_t BootAddress);
+void HAL_SYSCFG_EnableCM7BOOT(void);
+void HAL_SYSCFG_DisableCM7BOOT(void);
+void HAL_SYSCFG_EnableCM4BOOT(void);
+void HAL_SYSCFG_DisableCM4BOOT(void);
+#endif /*DUAL_CORE*/
+void HAL_EnableCompensationCell(void);
+void HAL_DisableCompensationCell(void);
+void HAL_SYSCFG_EnableIOSpeedOptimize(void);
+void HAL_SYSCFG_DisableIOSpeedOptimize(void);
+void HAL_SYSCFG_CompensationCodeSelect(uint32_t SYSCFG_CompCode);
+void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode);
+#if defined(SYSCFG_CCCR_NCC_MMC)
+void HAL_SYSCFG_VDDMMC_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode);
+#endif /* SYSCFG_CCCR_NCC_MMC */
+void HAL_EnableDBGSleepMode(void);
+void HAL_DisableDBGSleepMode(void);
+void HAL_EnableDBGStopMode(void);
+void HAL_DisableDBGStopMode(void);
+void HAL_EnableDBGStandbyMode(void);
+void HAL_DisableDBGStandbyMode(void);
+#if defined(DUAL_CORE)
+void HAL_EnableDomain2DBGSleepMode(void);
+void HAL_DisableDomain2DBGSleepMode(void);
+void HAL_EnableDomain2DBGStopMode(void);
+void HAL_DisableDomain2DBGStopMode(void);
+void HAL_EnableDomain2DBGStandbyMode(void);
+void HAL_DisableDomain2DBGStandbyMode(void);
+#endif /*DUAL_CORE*/
+void HAL_EnableDomain3DBGStopMode(void);
+void HAL_DisableDomain3DBGStopMode(void);
+void HAL_EnableDomain3DBGStandbyMode(void);
+void HAL_DisableDomain3DBGStandbyMode(void);
+void HAL_EXTI_EdgeConfig(uint32_t EXTI_Line , uint32_t EXTI_Edge );
+void HAL_EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
+#if defined(DUAL_CORE)
+void HAL_EXTI_D2_ClearFlag(uint32_t EXTI_Line);
+#endif /*DUAL_CORE*/
+void HAL_EXTI_D1_ClearFlag(uint32_t EXTI_Line);
+void HAL_EXTI_D1_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode,  uint32_t EXTI_LineCmd);
+#if defined(DUAL_CORE)
+void HAL_EXTI_D2_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode,  uint32_t EXTI_LineCmd);
+#endif /*DUAL_CORE*/
+void HAL_EXTI_D3_EventInputConfig(uint32_t EXTI_Line, uint32_t EXTI_LineCmd , uint32_t EXTI_ClearSrc);
+void HAL_SetFMCMemorySwappingConfig(uint32_t BankMapConfig);
+uint32_t HAL_GetFMCMemorySwappingConfig(void);
+void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
+void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
+void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
+HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
+void HAL_SYSCFG_DisableVREFBUF(void);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h
new file mode 100644
index 00000000..4eca4390
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h
@@ -0,0 +1,461 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_cortex.h
+  * @author  MCD Application Team
+  * @brief   Header file of CORTEX HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_CORTEX_H
+#define STM32H7xx_HAL_CORTEX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup CORTEX
+  * @{
+  */
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Types Cortex Exported Types
+  * @{
+  */
+
+#if (__MPU_PRESENT == 1)
+/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
+  * @brief  MPU Region initialization structure
+  * @{
+  */
+typedef struct
+{
+  uint8_t                Enable;                /*!< Specifies the status of the region.
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */
+  uint8_t                Number;                /*!< Specifies the number of the region to protect.
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */
+  uint32_t               BaseAddress;           /*!< Specifies the base address of the region to protect.                           */
+  uint8_t                Size;                  /*!< Specifies the size of the region to protect.
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Size                   */
+  uint8_t                SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable.
+                                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */
+  uint8_t                TypeExtField;          /*!< Specifies the TEX field level.
+                                                     This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                    */
+  uint8_t                AccessPermission;      /*!< Specifies the region access permission type.
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */
+  uint8_t                DisableExec;           /*!< Specifies the instruction access status.
+                                                     This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */
+  uint8_t                IsShareable;           /*!< Specifies the shareability status of the protected region.
+                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */
+  uint8_t                IsCacheable;           /*!< Specifies the cacheable status of the region protected.
+                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable              */
+  uint8_t                IsBufferable;          /*!< Specifies the bufferable status of the protected region.
+                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable             */
+}MPU_Region_InitTypeDef;
+/**
+  * @}
+  */
+#endif /* __MPU_PRESENT */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
+  * @{
+  */
+
+/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
+  * @{
+  */
+#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority
+                                                                 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority
+                                                                 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority
+                                                                 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority
+                                                                 1 bits for subpriority */
+#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority
+                                                                 0 bits for subpriority */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
+  * @{
+  */
+#define SYSTICK_CLKSOURCE_HCLK_DIV8    ((uint32_t)0x00000000)
+#define SYSTICK_CLKSOURCE_HCLK         ((uint32_t)0x00000004)
+
+/**
+  * @}
+  */
+
+#if (__MPU_PRESENT == 1)
+/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
+  * @{
+  */
+#define  MPU_HFNMI_PRIVDEF_NONE      ((uint32_t)0x00000000)
+#define  MPU_HARDFAULT_NMI           ((uint32_t)0x00000002)
+#define  MPU_PRIVILEGED_DEFAULT      ((uint32_t)0x00000004)
+#define  MPU_HFNMI_PRIVDEF           ((uint32_t)0x00000006)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
+  * @{
+  */
+#define  MPU_REGION_ENABLE     ((uint8_t)0x01)
+#define  MPU_REGION_DISABLE    ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
+  * @{
+  */
+#define  MPU_INSTRUCTION_ACCESS_ENABLE      ((uint8_t)0x00)
+#define  MPU_INSTRUCTION_ACCESS_DISABLE     ((uint8_t)0x01)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
+  * @{
+  */
+#define  MPU_ACCESS_SHAREABLE        ((uint8_t)0x01)
+#define  MPU_ACCESS_NOT_SHAREABLE    ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
+  * @{
+  */
+#define  MPU_ACCESS_CACHEABLE         ((uint8_t)0x01)
+#define  MPU_ACCESS_NOT_CACHEABLE     ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
+  * @{
+  */
+#define  MPU_ACCESS_BUFFERABLE         ((uint8_t)0x01)
+#define  MPU_ACCESS_NOT_BUFFERABLE     ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
+  * @{
+  */
+#define  MPU_TEX_LEVEL0    ((uint8_t)0x00)
+#define  MPU_TEX_LEVEL1    ((uint8_t)0x01)
+#define  MPU_TEX_LEVEL2    ((uint8_t)0x02)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
+  * @{
+  */
+#define   MPU_REGION_SIZE_32B      ((uint8_t)0x04)
+#define   MPU_REGION_SIZE_64B      ((uint8_t)0x05)
+#define   MPU_REGION_SIZE_128B     ((uint8_t)0x06)
+#define   MPU_REGION_SIZE_256B     ((uint8_t)0x07)
+#define   MPU_REGION_SIZE_512B     ((uint8_t)0x08)
+#define   MPU_REGION_SIZE_1KB      ((uint8_t)0x09)
+#define   MPU_REGION_SIZE_2KB      ((uint8_t)0x0A)
+#define   MPU_REGION_SIZE_4KB      ((uint8_t)0x0B)
+#define   MPU_REGION_SIZE_8KB      ((uint8_t)0x0C)
+#define   MPU_REGION_SIZE_16KB     ((uint8_t)0x0D)
+#define   MPU_REGION_SIZE_32KB     ((uint8_t)0x0E)
+#define   MPU_REGION_SIZE_64KB     ((uint8_t)0x0F)
+#define   MPU_REGION_SIZE_128KB    ((uint8_t)0x10)
+#define   MPU_REGION_SIZE_256KB    ((uint8_t)0x11)
+#define   MPU_REGION_SIZE_512KB    ((uint8_t)0x12)
+#define   MPU_REGION_SIZE_1MB      ((uint8_t)0x13)
+#define   MPU_REGION_SIZE_2MB      ((uint8_t)0x14)
+#define   MPU_REGION_SIZE_4MB      ((uint8_t)0x15)
+#define   MPU_REGION_SIZE_8MB      ((uint8_t)0x16)
+#define   MPU_REGION_SIZE_16MB     ((uint8_t)0x17)
+#define   MPU_REGION_SIZE_32MB     ((uint8_t)0x18)
+#define   MPU_REGION_SIZE_64MB     ((uint8_t)0x19)
+#define   MPU_REGION_SIZE_128MB    ((uint8_t)0x1A)
+#define   MPU_REGION_SIZE_256MB    ((uint8_t)0x1B)
+#define   MPU_REGION_SIZE_512MB    ((uint8_t)0x1C)
+#define   MPU_REGION_SIZE_1GB      ((uint8_t)0x1D)
+#define   MPU_REGION_SIZE_2GB      ((uint8_t)0x1E)
+#define   MPU_REGION_SIZE_4GB      ((uint8_t)0x1F)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
+  * @{
+  */
+#define  MPU_REGION_NO_ACCESS      ((uint8_t)0x00)
+#define  MPU_REGION_PRIV_RW        ((uint8_t)0x01)
+#define  MPU_REGION_PRIV_RW_URO    ((uint8_t)0x02)
+#define  MPU_REGION_FULL_ACCESS    ((uint8_t)0x03)
+#define  MPU_REGION_PRIV_RO        ((uint8_t)0x05)
+#define  MPU_REGION_PRIV_RO_URO    ((uint8_t)0x06)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
+  * @{
+  */
+#define  MPU_REGION_NUMBER0    ((uint8_t)0x00)
+#define  MPU_REGION_NUMBER1    ((uint8_t)0x01)
+#define  MPU_REGION_NUMBER2    ((uint8_t)0x02)
+#define  MPU_REGION_NUMBER3    ((uint8_t)0x03)
+#define  MPU_REGION_NUMBER4    ((uint8_t)0x04)
+#define  MPU_REGION_NUMBER5    ((uint8_t)0x05)
+#define  MPU_REGION_NUMBER6    ((uint8_t)0x06)
+#define  MPU_REGION_NUMBER7    ((uint8_t)0x07)
+#if !defined(CORE_CM4)
+#define  MPU_REGION_NUMBER8    ((uint8_t)0x08)
+#define  MPU_REGION_NUMBER9    ((uint8_t)0x09)
+#define  MPU_REGION_NUMBER10   ((uint8_t)0x0A)
+#define  MPU_REGION_NUMBER11   ((uint8_t)0x0B)
+#define  MPU_REGION_NUMBER12   ((uint8_t)0x0C)
+#define  MPU_REGION_NUMBER13   ((uint8_t)0x0D)
+#define  MPU_REGION_NUMBER14   ((uint8_t)0x0E)
+#define  MPU_REGION_NUMBER15   ((uint8_t)0x0F)
+#endif /* !defined(CORE_CM4) */
+
+/**
+  * @}
+  */
+#endif /* __MPU_PRESENT */
+
+/**
+  * @}
+  */
+
+
+/* Exported Macros -----------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+
+/** @defgroup CORTEX_CPU_Identifier CORTEX_CPU_Identifier
+  * @{
+  */
+#define CM7_CPUID        ((uint32_t)0x00000003)
+
+#if defined(DUAL_CORE)
+#define CM4_CPUID        ((uint32_t)0x00000001)
+#endif /*DUAL_CORE*/
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CORTEX_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup CORTEX_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SystemReset(void);
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
+/**
+  * @}
+  */
+
+/** @addtogroup CORTEX_Exported_Functions_Group2
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+#if (__MPU_PRESENT == 1)
+void HAL_MPU_Enable(uint32_t MPU_Control);
+void HAL_MPU_Disable(void);
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
+#endif /* __MPU_PRESENT */
+uint32_t HAL_NVIC_GetPriorityGrouping(void);
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
+void HAL_SYSTICK_IRQHandler(void);
+void HAL_SYSTICK_Callback(void);
+uint32_t HAL_GetCurrentCPUID(void);
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
+  * @{
+  */
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_1) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_2) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_3) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10UL)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY)         ((PRIORITY) < 0x10UL)
+
+#define IS_NVIC_DEVICE_IRQ(IRQ)                (((int32_t)IRQ) >= 0x00)
+
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
+                                       ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
+
+#if (__MPU_PRESENT == 1)
+#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
+                                     ((STATE) == MPU_REGION_DISABLE))
+
+#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
+                                          ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
+
+#define IS_MPU_ACCESS_SHAREABLE(STATE)   (((STATE) == MPU_ACCESS_SHAREABLE) || \
+                                          ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
+
+#define IS_MPU_ACCESS_CACHEABLE(STATE)   (((STATE) == MPU_ACCESS_CACHEABLE) || \
+                                          ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
+
+#define IS_MPU_ACCESS_BUFFERABLE(STATE)   (((STATE) == MPU_ACCESS_BUFFERABLE) || \
+                                          ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
+
+#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0)  || \
+                                ((TYPE) == MPU_TEX_LEVEL1)  || \
+                                ((TYPE) == MPU_TEX_LEVEL2))
+
+#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS)   || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RW)     || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
+                                                  ((TYPE) == MPU_REGION_FULL_ACCESS) || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RO)     || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RO_URO))
+
+#if !defined(CORE_CM4)
+#define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER1)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER2)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER3)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER4)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER5)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER6)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER7)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER8)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER9)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER10) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER11) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER12) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER13) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER14) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER15))
+#else
+#define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER1)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER2)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER3)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER4)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER5)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER6)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER7))
+#endif /* !defined(CORE_CM4) */
+
+#define IS_MPU_REGION_SIZE(SIZE)    (((SIZE) == MPU_REGION_SIZE_32B)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_64B)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_128B)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_256B)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_512B)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_1KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_2KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_4KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_8KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_16KB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_32KB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_64KB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_128KB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_256KB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_512KB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_1MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_2MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_4MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_8MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_16MB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_32MB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_64MB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_128MB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_256MB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_512MB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_1GB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_2GB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_4GB))
+
+#define IS_MPU_SUB_REGION_DISABLE(SUBREGION)  ((SUBREGION) < (uint16_t)0x00FF)
+#endif /* __MPU_PRESENT */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_CORTEX_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h
new file mode 100644
index 00000000..fce605de
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h
@@ -0,0 +1,188 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_def.h
+  * @author  MCD Application Team
+  * @brief   This file contains HAL common defines, enumeration, macros and
+  *          structures definitions.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_DEF
+#define STM32H7xx_HAL_DEF
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+#include "Legacy/stm32_hal_legacy.h"
+#include <stddef.h>
+#include <math.h>
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+  * @brief  HAL Status structures definition
+  */
+typedef enum
+{
+  HAL_OK       = 0x00,
+  HAL_ERROR    = 0x01,
+  HAL_BUSY     = 0x02,
+  HAL_TIMEOUT  = 0x03
+} HAL_StatusTypeDef;
+
+/**
+  * @brief  HAL Lock structures definition
+  */
+typedef enum
+{
+  HAL_UNLOCKED = 0x00,
+  HAL_LOCKED   = 0x01
+} HAL_LockTypeDef;
+
+/* Exported macro ------------------------------------------------------------*/
+
+#define HAL_MAX_DELAY      0xFFFFFFFFU
+
+#define HAL_IS_BIT_SET(REG, BIT)         (((REG) & (BIT)) == (BIT))
+#define HAL_IS_BIT_CLR(REG, BIT)         (((REG) & (BIT)) == 0U)
+
+#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__)               \
+                        do{                                                      \
+                              (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
+                              (__DMA_HANDLE__).Parent = (__HANDLE__);             \
+                          } while(0)
+
+#define UNUSED(x) ((void)(x))
+
+/** @brief Reset the Handle's State field.
+  * @param __HANDLE__: specifies the Peripheral Handle.
+  * @note  This macro can be used for the following purpose: 
+  *          - When the Handle is declared as local variable; before passing it as parameter
+  *            to HAL_PPP_Init() for the first time, it is mandatory to use this macro 
+  *            to set to 0 the Handle's "State" field.
+  *            Otherwise, "State" field may have any random value and the first time the function 
+  *            HAL_PPP_Init() is called, the low level hardware initialization will be missed
+  *            (i.e. HAL_PPP_MspInit() will not be executed).
+  *          - When there is a need to reconfigure the low level hardware: instead of calling
+  *            HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
+  *            In this later function, when the Handle's "State" field is set to 0, it will execute the function
+  *            HAL_PPP_MspInit() which will reconfigure the low level hardware.
+  * @retval None
+  */
+#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
+
+#if (USE_RTOS == 1)
+  #error " USE_RTOS should be 0 in the current HAL release "
+#else
+  #define __HAL_LOCK(__HANDLE__)                                           \
+                                do{                                        \
+                                    if((__HANDLE__)->Lock == HAL_LOCKED)   \
+                                    {                                      \
+                                       return HAL_BUSY;                    \
+                                    }                                      \
+                                    else                                   \
+                                    {                                      \
+                                       (__HANDLE__)->Lock = HAL_LOCKED;    \
+                                    }                                      \
+                                  }while (0)
+
+  #define __HAL_UNLOCK(__HANDLE__)                                          \
+                                  do{                                       \
+                                      (__HANDLE__)->Lock = HAL_UNLOCKED;    \
+                                    }while (0)
+#endif /* USE_RTOS */
+
+#if  defined ( __GNUC__ )
+  #ifndef __weak
+    #define __weak   __attribute__((weak))
+  #endif /* __weak */
+  #ifndef __packed
+    #define __packed __attribute__((__packed__))
+  #endif /* __packed */
+#endif /* __GNUC__ */
+
+
+/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
+#if defined   (__GNUC__)        /* GNU Compiler */
+  #ifndef __ALIGN_END
+    #define __ALIGN_END    __attribute__ ((aligned (4)))
+  #endif /* __ALIGN_END */
+  #ifndef __ALIGN_BEGIN
+    #define __ALIGN_BEGIN
+  #endif /* __ALIGN_BEGIN */
+#else
+  #ifndef __ALIGN_END
+    #define __ALIGN_END
+  #endif /* __ALIGN_END */
+  #ifndef __ALIGN_BEGIN
+    #if defined   (__CC_ARM)      /* ARM Compiler */
+      #define __ALIGN_BEGIN    __align(4)
+    #elif defined (__ICCARM__)    /* IAR Compiler */
+      #define __ALIGN_BEGIN
+    #endif /* __CC_ARM */
+  #endif /* __ALIGN_BEGIN */
+#endif /* __GNUC__ */
+
+/* Macro to get variable aligned on 32-bytes,needed for cache maintenance purpose */
+#if defined   (__GNUC__)        /* GNU Compiler */
+  #define ALIGN_32BYTES(buf)  buf __attribute__ ((aligned (32)))                                    
+#elif defined (__ICCARM__)    /* IAR Compiler */
+  #define ALIGN_32BYTES(buf) _Pragma("data_alignment=32") buf  
+#elif defined   (__CC_ARM)      /* ARM Compiler */
+  #define ALIGN_32BYTES(buf) __align(32) buf  
+#endif
+
+/**
+  * @brief  __RAM_FUNC definition
+  */
+#if defined ( __CC_ARM   )
+/* ARM Compiler
+   ------------
+   RAM functions are defined using the toolchain options.
+   Functions that are executed in RAM should reside in a separate source module.
+   Using the 'Options for File' dialog you can simply change the 'Code / Const'
+   area of a module to a memory space in physical RAM.
+   Available memory areas are declared in the 'Target' tab of the 'Options for Target'
+   dialog.
+*/
+#define __RAM_FUNC
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+   ---------------
+   RAM functions are defined using a specific toolchain keyword "__ramfunc".
+*/
+#define __RAM_FUNC __ramfunc
+
+#elif defined   (  __GNUC__  )
+/* GNU Compiler
+   ------------
+  RAM functions are defined using a specific toolchain attribute
+   "__attribute__((section(".RamFunc")))".
+*/
+#define __RAM_FUNC __attribute__((section(".RamFunc")))
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_DEF */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h
new file mode 100644
index 00000000..36d553b0
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h
@@ -0,0 +1,1290 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_dma.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMA HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_DMA_H
+#define STM32H7xx_HAL_DMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DMA
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Types DMA Exported Types
+  * @brief    DMA Exported Types
+  * @{
+  */
+
+/**
+  * @brief  DMA Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t Request;               /*!< Specifies the request selected for the specified stream.
+                                           This parameter can be a value of @ref DMA_Request_selection              */
+
+  uint32_t Direction;            /*!< Specifies if the data will be transferred from memory to peripheral,
+                                      from memory to memory or from peripheral to memory.
+                                      This parameter can be a value of @ref DMA_Data_transfer_direction              */
+
+  uint32_t PeriphInc;            /*!< Specifies whether the Peripheral address register should be incremented or not.
+                                      This parameter can be a value of @ref DMA_Peripheral_incremented_mode          */
+
+  uint32_t MemInc;               /*!< Specifies whether the memory address register should be incremented or not.
+                                      This parameter can be a value of @ref DMA_Memory_incremented_mode              */
+
+  uint32_t PeriphDataAlignment;  /*!< Specifies the Peripheral data width.
+                                      This parameter can be a value of @ref DMA_Peripheral_data_size                 */
+
+  uint32_t MemDataAlignment;     /*!< Specifies the Memory data width.
+                                      This parameter can be a value of @ref DMA_Memory_data_size                     */
+
+  uint32_t Mode;                 /*!< Specifies the operation mode of the DMAy Streamx.
+                                      This parameter can be a value of @ref DMA_mode
+                                      @note The circular buffer mode cannot be used if the memory-to-memory
+                                            data transfer is configured on the selected Stream                        */
+
+  uint32_t Priority;             /*!< Specifies the software priority for the DMAy Streamx.
+                                      This parameter can be a value of @ref DMA_Priority_level                        */
+
+  uint32_t FIFOMode;             /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
+                                      This parameter can be a value of @ref DMA_FIFO_direct_mode
+                                      @note The Direct mode (FIFO mode disabled) cannot be used if the
+                                            memory-to-memory data transfer is configured on the selected stream       */
+
+  uint32_t FIFOThreshold;        /*!< Specifies the FIFO threshold level.
+                                      This parameter can be a value of @ref DMA_FIFO_threshold_level                  */
+
+  uint32_t MemBurst;             /*!< Specifies the Burst transfer configuration for the memory transfers.
+                                      It specifies the amount of data to be transferred in a single non interruptible
+                                      transaction.
+                                      This parameter can be a value of @ref DMA_Memory_burst
+                                      @note The burst mode is possible only if the address Increment mode is enabled. */
+
+  uint32_t PeriphBurst;          /*!< Specifies the Burst transfer configuration for the peripheral transfers.
+                                      It specifies the amount of data to be transferred in a single non interruptible
+                                      transaction.
+                                      This parameter can be a value of @ref DMA_Peripheral_burst
+                                      @note The burst mode is possible only if the address Increment mode is enabled. */
+}DMA_InitTypeDef;
+
+/**
+  * @brief  HAL DMA State structures definition
+  */
+typedef enum
+{
+  HAL_DMA_STATE_RESET             = 0x00U,  /*!< DMA not yet initialized or disabled */
+  HAL_DMA_STATE_READY             = 0x01U,  /*!< DMA initialized and ready for use   */
+  HAL_DMA_STATE_BUSY              = 0x02U,  /*!< DMA process is ongoing              */
+  HAL_DMA_STATE_ERROR             = 0x03U,  /*!< DMA error state                     */
+  HAL_DMA_STATE_ABORT             = 0x04U,  /*!< DMA Abort state                     */
+}HAL_DMA_StateTypeDef;
+
+/**
+  * @brief  HAL DMA Transfer complete level structure definition
+  */
+typedef enum
+{
+  HAL_DMA_FULL_TRANSFER      = 0x00U,    /*!< Full transfer     */
+  HAL_DMA_HALF_TRANSFER      = 0x01U,    /*!< Half Transfer     */
+}HAL_DMA_LevelCompleteTypeDef;
+
+/**
+  * @brief  HAL DMA Callbacks IDs structure definition
+  */
+typedef enum
+{
+  HAL_DMA_XFER_CPLT_CB_ID          = 0x00U,    /*!< Full transfer     */
+  HAL_DMA_XFER_HALFCPLT_CB_ID      = 0x01U,    /*!< Half Transfer     */
+  HAL_DMA_XFER_M1CPLT_CB_ID        = 0x02U,    /*!< M1 Full Transfer  */
+  HAL_DMA_XFER_M1HALFCPLT_CB_ID    = 0x03U,    /*!< M1 Half Transfer  */
+  HAL_DMA_XFER_ERROR_CB_ID         = 0x04U,    /*!< Error             */
+  HAL_DMA_XFER_ABORT_CB_ID         = 0x05U,    /*!< Abort             */
+  HAL_DMA_XFER_ALL_CB_ID           = 0x06U     /*!< All               */
+}HAL_DMA_CallbackIDTypeDef;
+
+/**
+  * @brief  DMA handle Structure definition
+  */
+typedef struct __DMA_HandleTypeDef
+{
+  void                            *Instance;                                                        /*!< Register base address                         */
+
+  DMA_InitTypeDef                 Init;                                                             /*!< DMA communication parameters                  */
+
+  HAL_LockTypeDef                 Lock;                                                             /*!< DMA locking object                            */
+
+  __IO HAL_DMA_StateTypeDef       State;                                                            /*!< DMA transfer state                            */
+
+  void                            *Parent;                                                          /*!< Parent object state                           */
+
+  void                            (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);         /*!< DMA transfer complete callback                */
+
+  void                            (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);     /*!< DMA Half transfer complete callback           */
+
+  void                            (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma);       /*!< DMA transfer complete Memory1 callback        */
+
+  void                            (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);   /*!< DMA transfer Half complete Memory1 callback   */
+
+  void                            (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);        /*!< DMA transfer error callback                   */
+
+  void                            (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma);        /*!< DMA transfer Abort callback                   */
+
+ __IO uint32_t                    ErrorCode;                                                        /*!< DMA Error code                                */
+
+ uint32_t                         StreamBaseAddress;                                                /*!< DMA Stream Base Address                       */
+
+ uint32_t                         StreamIndex;                                                      /*!< DMA Stream Index                              */
+
+ DMAMUX_Channel_TypeDef           *DMAmuxChannel;                                                   /*!< DMAMUX Channel Base Address                   */
+
+ DMAMUX_ChannelStatus_TypeDef     *DMAmuxChannelStatus;                                             /*!< DMAMUX Channels Status Base Address           */
+
+ uint32_t                         DMAmuxChannelStatusMask;                                          /*!< DMAMUX Channel Status Mask                    */
+
+
+ DMAMUX_RequestGen_TypeDef        *DMAmuxRequestGen;                                                /*!< DMAMUX request generator Base Address         */
+
+ DMAMUX_RequestGenStatus_TypeDef  *DMAmuxRequestGenStatus;                                          /*!< DMAMUX request generator Status Address       */
+
+ uint32_t                         DMAmuxRequestGenStatusMask;                                       /*!< DMAMUX request generator Status mask          */
+
+}DMA_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Constants DMA Exported Constants
+  * @brief    DMA Exported constants
+  * @{
+  */
+
+/** @defgroup DMA_Error_Code DMA Error Code
+  * @brief    DMA Error Code
+  * @{
+  */
+#define HAL_DMA_ERROR_NONE            (0x00000000U)    /*!< No error                                */
+#define HAL_DMA_ERROR_TE              (0x00000001U)    /*!< Transfer error                          */
+#define HAL_DMA_ERROR_FE              (0x00000002U)    /*!< FIFO error                              */
+#define HAL_DMA_ERROR_DME             (0x00000004U)    /*!< Direct Mode error                       */
+#define HAL_DMA_ERROR_TIMEOUT         (0x00000020U)    /*!< Timeout error                           */
+#define HAL_DMA_ERROR_PARAM           (0x00000040U)    /*!< Parameter error                         */
+#define HAL_DMA_ERROR_NO_XFER         (0x00000080U)    /*!< Abort requested with no Xfer ongoing    */
+#define HAL_DMA_ERROR_NOT_SUPPORTED   (0x00000100U)    /*!< Not supported mode                      */
+#define HAL_DMA_ERROR_SYNC            (0x00000200U)    /*!< DMAMUX sync overrun  error              */
+#define HAL_DMA_ERROR_REQGEN          (0x00000400U)    /*!< DMAMUX request generator overrun  error */
+#define HAL_DMA_ERROR_BUSY            (0x00000800U)    /*!< DMA Busy                          error */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Request_selection DMA Request selection
+  * @brief    DMA Request selection
+  * @{
+  */
+/* DMAMUX1 requests */
+#define DMA_REQUEST_MEM2MEM          0U  /*!< memory to memory transfer   */
+
+#define DMA_REQUEST_GENERATOR0       1U  /*!< DMAMUX1 request generator 0 */
+#define DMA_REQUEST_GENERATOR1       2U  /*!< DMAMUX1 request generator 1 */
+#define DMA_REQUEST_GENERATOR2       3U  /*!< DMAMUX1 request generator 2 */
+#define DMA_REQUEST_GENERATOR3       4U  /*!< DMAMUX1 request generator 3 */
+#define DMA_REQUEST_GENERATOR4       5U  /*!< DMAMUX1 request generator 4 */
+#define DMA_REQUEST_GENERATOR5       6U  /*!< DMAMUX1 request generator 5 */
+#define DMA_REQUEST_GENERATOR6       7U  /*!< DMAMUX1 request generator 6 */
+#define DMA_REQUEST_GENERATOR7       8U  /*!< DMAMUX1 request generator 7 */
+
+#define DMA_REQUEST_ADC1             9U  /*!< DMAMUX1 ADC1 request */
+#define DMA_REQUEST_ADC2             10U /*!< DMAMUX1 ADC2 request */
+
+#define DMA_REQUEST_TIM1_CH1         11U  /*!< DMAMUX1 TIM1 CH1 request  */
+#define DMA_REQUEST_TIM1_CH2         12U  /*!< DMAMUX1 TIM1 CH2 request  */
+#define DMA_REQUEST_TIM1_CH3         13U  /*!< DMAMUX1 TIM1 CH3 request  */
+#define DMA_REQUEST_TIM1_CH4         14U  /*!< DMAMUX1 TIM1 CH4 request  */
+#define DMA_REQUEST_TIM1_UP          15U  /*!< DMAMUX1 TIM1 UP request   */
+#define DMA_REQUEST_TIM1_TRIG        16U  /*!< DMAMUX1 TIM1 TRIG request */
+#define DMA_REQUEST_TIM1_COM         17U  /*!< DMAMUX1 TIM1 COM request  */
+
+#define DMA_REQUEST_TIM2_CH1         18U  /*!< DMAMUX1 TIM2 CH1 request  */
+#define DMA_REQUEST_TIM2_CH2         19U  /*!< DMAMUX1 TIM2 CH2 request  */
+#define DMA_REQUEST_TIM2_CH3         20U  /*!< DMAMUX1 TIM2 CH3 request  */
+#define DMA_REQUEST_TIM2_CH4         21U  /*!< DMAMUX1 TIM2 CH4 request  */
+#define DMA_REQUEST_TIM2_UP          22U  /*!< DMAMUX1 TIM2 UP request   */
+
+#define DMA_REQUEST_TIM3_CH1         23U  /*!< DMAMUX1 TIM3 CH1 request  */
+#define DMA_REQUEST_TIM3_CH2         24U  /*!< DMAMUX1 TIM3 CH2 request  */
+#define DMA_REQUEST_TIM3_CH3         25U  /*!< DMAMUX1 TIM3 CH3 request  */
+#define DMA_REQUEST_TIM3_CH4         26U  /*!< DMAMUX1 TIM3 CH4 request  */
+#define DMA_REQUEST_TIM3_UP          27U  /*!< DMAMUX1 TIM3 UP request   */
+#define DMA_REQUEST_TIM3_TRIG        28U  /*!< DMAMUX1 TIM3 TRIG request */
+
+#define DMA_REQUEST_TIM4_CH1         29U  /*!< DMAMUX1 TIM4 CH1 request  */
+#define DMA_REQUEST_TIM4_CH2         30U  /*!< DMAMUX1 TIM4 CH2 request  */
+#define DMA_REQUEST_TIM4_CH3         31U  /*!< DMAMUX1 TIM4 CH3 request  */
+#define DMA_REQUEST_TIM4_UP          32U  /*!< DMAMUX1 TIM4 UP request   */
+
+#define DMA_REQUEST_I2C1_RX          33U  /*!< DMAMUX1 I2C1 RX request   */
+#define DMA_REQUEST_I2C1_TX          34U  /*!< DMAMUX1 I2C1 TX request   */
+#define DMA_REQUEST_I2C2_RX          35U  /*!< DMAMUX1 I2C2 RX request   */
+#define DMA_REQUEST_I2C2_TX          36U  /*!< DMAMUX1 I2C2 TX request   */
+
+#define DMA_REQUEST_SPI1_RX          37U  /*!< DMAMUX1 SPI1 RX request   */
+#define DMA_REQUEST_SPI1_TX          38U  /*!< DMAMUX1 SPI1 TX request   */
+#define DMA_REQUEST_SPI2_RX          39U  /*!< DMAMUX1 SPI2 RX request   */
+#define DMA_REQUEST_SPI2_TX          40U  /*!< DMAMUX1 SPI2 TX request   */
+
+#define DMA_REQUEST_USART1_RX        41U  /*!< DMAMUX1 USART1 RX request */
+#define DMA_REQUEST_USART1_TX        42U  /*!< DMAMUX1 USART1 TX request */
+#define DMA_REQUEST_USART2_RX        43U  /*!< DMAMUX1 USART2 RX request */
+#define DMA_REQUEST_USART2_TX        44U  /*!< DMAMUX1 USART2 TX request */
+#define DMA_REQUEST_USART3_RX        45U  /*!< DMAMUX1 USART3 RX request */
+#define DMA_REQUEST_USART3_TX        46U  /*!< DMAMUX1 USART3 TX request */
+
+#define DMA_REQUEST_TIM8_CH1         47U  /*!< DMAMUX1 TIM8 CH1 request  */
+#define DMA_REQUEST_TIM8_CH2         48U  /*!< DMAMUX1 TIM8 CH2 request  */
+#define DMA_REQUEST_TIM8_CH3         49U  /*!< DMAMUX1 TIM8 CH3 request  */
+#define DMA_REQUEST_TIM8_CH4         50U  /*!< DMAMUX1 TIM8 CH4 request  */
+#define DMA_REQUEST_TIM8_UP          51U  /*!< DMAMUX1 TIM8 UP request   */
+#define DMA_REQUEST_TIM8_TRIG        52U  /*!< DMAMUX1 TIM8 TRIG request */
+#define DMA_REQUEST_TIM8_COM         53U  /*!< DMAMUX1 TIM8 COM request  */
+
+#define DMA_REQUEST_TIM5_CH1         55U  /*!< DMAMUX1 TIM5 CH1 request  */
+#define DMA_REQUEST_TIM5_CH2         56U  /*!< DMAMUX1 TIM5 CH2 request  */
+#define DMA_REQUEST_TIM5_CH3         57U  /*!< DMAMUX1 TIM5 CH3 request  */
+#define DMA_REQUEST_TIM5_CH4         58U  /*!< DMAMUX1 TIM5 CH4 request  */
+#define DMA_REQUEST_TIM5_UP          59U  /*!< DMAMUX1 TIM5 UP request   */
+#define DMA_REQUEST_TIM5_TRIG        60U  /*!< DMAMUX1 TIM5 TRIG request */
+
+#define DMA_REQUEST_SPI3_RX          61U  /*!< DMAMUX1 SPI3 RX request   */
+#define DMA_REQUEST_SPI3_TX          62U  /*!< DMAMUX1 SPI3 TX request   */
+
+#define DMA_REQUEST_UART4_RX         63U  /*!< DMAMUX1 UART4 RX request */
+#define DMA_REQUEST_UART4_TX         64U  /*!< DMAMUX1 UART4 TX request */
+#define DMA_REQUEST_UART5_RX         65U  /*!< DMAMUX1 UART5 RX request */
+#define DMA_REQUEST_UART5_TX         66U  /*!< DMAMUX1 UART5 TX request */
+
+#define DMA_REQUEST_DAC1_CH1         67U  /*!< DMAMUX1 DAC1 Channel 1 request */
+#define DMA_REQUEST_DAC1_CH2         68U  /*!< DMAMUX1 DAC1 Channel 2 request */
+
+#define DMA_REQUEST_TIM6_UP          69U  /*!< DMAMUX1 TIM6 UP request   */
+#define DMA_REQUEST_TIM7_UP          70U  /*!< DMAMUX1 TIM7 UP request   */
+
+#define DMA_REQUEST_USART6_RX        71U  /*!< DMAMUX1 USART6 RX request */
+#define DMA_REQUEST_USART6_TX        72U  /*!< DMAMUX1 USART6 TX request */
+
+#define DMA_REQUEST_I2C3_RX          73U  /*!< DMAMUX1 I2C3 RX request   */
+#define DMA_REQUEST_I2C3_TX          74U  /*!< DMAMUX1 I2C3 TX request   */
+
+#if defined (PSSI)
+#define DMA_REQUEST_DCMI_PSSI        75U  /*!< DMAMUX1 DCMI/PSSI request    */
+#define DMA_REQUEST_DCMI             DMA_REQUEST_DCMI_PSSI /* Legacy define */
+#else
+#define DMA_REQUEST_DCMI             75U  /*!< DMAMUX1 DCMI request         */
+#endif /* PSSI */
+
+#define DMA_REQUEST_CRYP_IN          76U  /*!< DMAMUX1 CRYP IN request   */
+#define DMA_REQUEST_CRYP_OUT         77U  /*!< DMAMUX1 CRYP OUT request  */
+
+#define DMA_REQUEST_HASH_IN          78U  /*!< DMAMUX1 HASH IN request   */
+
+#define DMA_REQUEST_UART7_RX         79U  /*!< DMAMUX1 UART7 RX request  */
+#define DMA_REQUEST_UART7_TX         80U  /*!< DMAMUX1 UART7 TX request  */
+#define DMA_REQUEST_UART8_RX         81U  /*!< DMAMUX1 UART8 RX request  */
+#define DMA_REQUEST_UART8_TX         82U  /*!< DMAMUX1 UART8 TX request  */
+
+#define DMA_REQUEST_SPI4_RX          83U  /*!< DMAMUX1 SPI4 RX request   */
+#define DMA_REQUEST_SPI4_TX          84U  /*!< DMAMUX1 SPI4 TX request   */
+#define DMA_REQUEST_SPI5_RX          85U  /*!< DMAMUX1 SPI5 RX request   */
+#define DMA_REQUEST_SPI5_TX          86U  /*!< DMAMUX1 SPI5 TX request   */
+
+#define DMA_REQUEST_SAI1_A           87U  /*!< DMAMUX1 SAI1 A request    */
+#define DMA_REQUEST_SAI1_B           88U  /*!< DMAMUX1 SAI1 B request    */
+#define DMA_REQUEST_SAI2_A           89U  /*!< DMAMUX1 SAI2 A request    */
+#define DMA_REQUEST_SAI2_B           90U  /*!< DMAMUX1 SAI2 B request    */
+
+#define DMA_REQUEST_SWPMI_RX         91U  /*!< DMAMUX1 SWPMI RX request  */
+#define DMA_REQUEST_SWPMI_TX         92U  /*!< DMAMUX1 SWPMI TX request  */
+
+#define DMA_REQUEST_SPDIF_RX_DT      93U  /*!< DMAMUX1 SPDIF RXDT request*/
+#define DMA_REQUEST_SPDIF_RX_CS      94U  /*!< DMAMUX1 SPDIF RXCS request*/
+
+#if defined(HRTIM1)
+#define DMA_REQUEST_HRTIM_MASTER     95U  /*!< DMAMUX1 HRTIM1 Master request 1 */
+#define DMA_REQUEST_HRTIM_TIMER_A    96U  /*!< DMAMUX1 HRTIM1 TimerA request 2 */
+#define DMA_REQUEST_HRTIM_TIMER_B    97U  /*!< DMAMUX1 HRTIM1 TimerB request 3 */
+#define DMA_REQUEST_HRTIM_TIMER_C    98U  /*!< DMAMUX1 HRTIM1 TimerC request 4 */
+#define DMA_REQUEST_HRTIM_TIMER_D    99U  /*!< DMAMUX1 HRTIM1 TimerD request 5 */
+#define DMA_REQUEST_HRTIM_TIMER_E   100U  /*!< DMAMUX1 HRTIM1 TimerE request 6 */
+#endif /* HRTIM1 */
+
+#define DMA_REQUEST_DFSDM1_FLT0     101U  /*!< DMAMUX1 DFSDM Filter0 request */
+#define DMA_REQUEST_DFSDM1_FLT1     102U  /*!< DMAMUX1 DFSDM Filter1 request */
+#define DMA_REQUEST_DFSDM1_FLT2     103U  /*!< DMAMUX1 DFSDM Filter2 request */
+#define DMA_REQUEST_DFSDM1_FLT3     104U  /*!< DMAMUX1 DFSDM Filter3 request */
+
+#define DMA_REQUEST_TIM15_CH1       105U  /*!< DMAMUX1 TIM15 CH1 request  */
+#define DMA_REQUEST_TIM15_UP        106U  /*!< DMAMUX1 TIM15 UP request   */
+#define DMA_REQUEST_TIM15_TRIG      107U  /*!< DMAMUX1 TIM15 TRIG request */
+#define DMA_REQUEST_TIM15_COM       108U  /*!< DMAMUX1 TIM15 COM request  */
+
+#define DMA_REQUEST_TIM16_CH1       109U  /*!< DMAMUX1 TIM16 CH1 request  */
+#define DMA_REQUEST_TIM16_UP        110U  /*!< DMAMUX1 TIM16 UP request   */
+
+#define DMA_REQUEST_TIM17_CH1       111U  /*!< DMAMUX1 TIM17 CH1 request  */
+#define DMA_REQUEST_TIM17_UP        112U  /*!< DMAMUX1 TIM17 UP request   */
+
+#if defined(SAI3)
+#define DMA_REQUEST_SAI3_A          113U  /*!< DMAMUX1 SAI3 A request  */
+#define DMA_REQUEST_SAI3_B          114U  /*!< DMAMUX1 SAI3 B request  */
+#endif /* SAI3 */
+
+#if defined(ADC3)
+#define DMA_REQUEST_ADC3            115U  /*!< DMAMUX1 ADC3 request  */
+#endif /* ADC3 */
+
+#if defined(UART9)
+#define DMA_REQUEST_UART9_RX        116U  /*!< DMAMUX1 UART9 request  */
+#define DMA_REQUEST_UART9_TX        117U  /*!< DMAMUX1 UART9 request  */
+#endif /* UART9 */
+
+#if defined(USART10)
+#define DMA_REQUEST_USART10_RX      118U  /*!< DMAMUX1 USART10 request  */
+#define DMA_REQUEST_USART10_TX      119U  /*!< DMAMUX1 USART10 request  */
+#endif /* USART10 */
+
+
+/* DMAMUX2 requests */
+#define BDMA_REQUEST_MEM2MEM          0U  /*!< memory to memory transfer   */
+#define BDMA_REQUEST_GENERATOR0       1U  /*!< DMAMUX2 request generator 0 */
+#define BDMA_REQUEST_GENERATOR1       2U  /*!< DMAMUX2 request generator 1 */
+#define BDMA_REQUEST_GENERATOR2       3U  /*!< DMAMUX2 request generator 2 */
+#define BDMA_REQUEST_GENERATOR3       4U  /*!< DMAMUX2 request generator 3 */
+#define BDMA_REQUEST_GENERATOR4       5U  /*!< DMAMUX2 request generator 4 */
+#define BDMA_REQUEST_GENERATOR5       6U  /*!< DMAMUX2 request generator 5 */
+#define BDMA_REQUEST_GENERATOR6       7U  /*!< DMAMUX2 request generator 6 */
+#define BDMA_REQUEST_GENERATOR7       8U  /*!< DMAMUX2 request generator 7 */
+#define BDMA_REQUEST_LPUART1_RX       9U  /*!< DMAMUX2 LP_UART1_RX request */
+#define BDMA_REQUEST_LPUART1_TX      10U  /*!< DMAMUX2 LP_UART1_TX request */
+#define BDMA_REQUEST_SPI6_RX         11U  /*!< DMAMUX2 SPI6 RX request     */
+#define BDMA_REQUEST_SPI6_TX         12U  /*!< DMAMUX2 SPI6 TX request     */
+#define BDMA_REQUEST_I2C4_RX         13U  /*!< DMAMUX2 I2C4 RX request     */
+#define BDMA_REQUEST_I2C4_TX         14U  /*!< DMAMUX2 I2C4 TX request     */
+#if defined(SAI4)
+#define BDMA_REQUEST_SAI4_A          15U  /*!< DMAMUX2 SAI4 A request      */
+#define BDMA_REQUEST_SAI4_B          16U  /*!< DMAMUX2 SAI4 B request      */
+#endif /* SAI4 */
+#if defined(ADC3)
+#define BDMA_REQUEST_ADC3            17U  /*!< DMAMUX2 ADC3 request        */
+#endif /* ADC3 */
+#if defined(DAC2)
+#define BDMA_REQUEST_DAC2_CH1        17U  /*!< DMAMUX2 DAC2 CH1 request    */
+#endif /* DAC2 */
+#if defined(DFSDM2_Channel0)
+#define BDMA_REQUEST_DFSDM2_FLT0     18U  /*!< DMAMUX2 DFSDM2 request      */
+#endif /* DFSDM1_Channel0 */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
+  * @brief    DMA data transfer direction
+  * @{
+  */
+#define DMA_PERIPH_TO_MEMORY         ((uint32_t)0x00000000U)      /*!< Peripheral to memory direction */
+#define DMA_MEMORY_TO_PERIPH         ((uint32_t)DMA_SxCR_DIR_0)  /*!< Memory to peripheral direction */
+#define DMA_MEMORY_TO_MEMORY         ((uint32_t)DMA_SxCR_DIR_1)  /*!< Memory to memory direction     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
+  * @brief    DMA peripheral incremented mode
+  * @{
+  */
+#define DMA_PINC_ENABLE        ((uint32_t)DMA_SxCR_PINC)  /*!< Peripheral increment mode enable  */
+#define DMA_PINC_DISABLE       ((uint32_t)0x00000000U)     /*!< Peripheral increment mode disable */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
+  * @brief    DMA memory incremented mode
+  * @{
+  */
+#define DMA_MINC_ENABLE         ((uint32_t)DMA_SxCR_MINC)  /*!< Memory increment mode enable  */
+#define DMA_MINC_DISABLE        ((uint32_t)0x00000000U)     /*!< Memory increment mode disable */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
+  * @brief    DMA peripheral data size
+  * @{
+  */
+#define DMA_PDATAALIGN_BYTE          ((uint32_t)0x00000000U)       /*!< Peripheral data alignment: Byte      */
+#define DMA_PDATAALIGN_HALFWORD      ((uint32_t)DMA_SxCR_PSIZE_0)  /*!< Peripheral data alignment: HalfWord  */
+#define DMA_PDATAALIGN_WORD          ((uint32_t)DMA_SxCR_PSIZE_1)  /*!< Peripheral data alignment: Word      */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Memory_data_size DMA Memory data size
+  * @brief    DMA memory data size
+  * @{
+  */
+#define DMA_MDATAALIGN_BYTE          ((uint32_t)0x00000000U)       /*!< Memory data alignment: Byte     */
+#define DMA_MDATAALIGN_HALFWORD      ((uint32_t)DMA_SxCR_MSIZE_0)  /*!< Memory data alignment: HalfWord */
+#define DMA_MDATAALIGN_WORD          ((uint32_t)DMA_SxCR_MSIZE_1)  /*!< Memory data alignment: Word     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_mode DMA mode
+  * @brief    DMA mode
+  * @{
+  */
+#define DMA_NORMAL              ((uint32_t)0x00000000U)                  /*!< Normal mode                                    */
+#define DMA_CIRCULAR            ((uint32_t)DMA_SxCR_CIRC)                /*!< Circular mode                                  */
+#define DMA_PFCTRL              ((uint32_t)DMA_SxCR_PFCTRL)              /*!< Peripheral flow control mode                   */
+#define DMA_DOUBLE_BUFFER_M0    ((uint32_t)DMA_SxCR_DBM)                 /*!< Double buffer mode with first target memory M0 */
+#define DMA_DOUBLE_BUFFER_M1    ((uint32_t)(DMA_SxCR_DBM | DMA_SxCR_CT)) /*!< Double buffer mode with first target memory M1 */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Priority_level DMA Priority level
+  * @brief    DMA priority levels
+  * @{
+  */
+#define DMA_PRIORITY_LOW             ((uint32_t)0x00000000U)    /*!< Priority level: Low       */
+#define DMA_PRIORITY_MEDIUM          ((uint32_t)DMA_SxCR_PL_0)  /*!< Priority level: Medium    */
+#define DMA_PRIORITY_HIGH            ((uint32_t)DMA_SxCR_PL_1)  /*!< Priority level: High      */
+#define DMA_PRIORITY_VERY_HIGH       ((uint32_t)DMA_SxCR_PL)    /*!< Priority level: Very High */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
+  * @brief    DMA FIFO direct mode
+  * @{
+  */
+#define DMA_FIFOMODE_DISABLE        ((uint32_t)0x00000000U)       /*!< FIFO mode disable */
+#define DMA_FIFOMODE_ENABLE         ((uint32_t)DMA_SxFCR_DMDIS)  /*!< FIFO mode enable  */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
+  * @brief    DMA FIFO level
+  * @{
+  */
+#define DMA_FIFO_THRESHOLD_1QUARTERFULL       ((uint32_t)0x00000000U)       /*!< FIFO threshold 1 quart full configuration  */
+#define DMA_FIFO_THRESHOLD_HALFFULL           ((uint32_t)DMA_SxFCR_FTH_0)  /*!< FIFO threshold half full configuration     */
+#define DMA_FIFO_THRESHOLD_3QUARTERSFULL      ((uint32_t)DMA_SxFCR_FTH_1)  /*!< FIFO threshold 3 quarts full configuration */
+#define DMA_FIFO_THRESHOLD_FULL               ((uint32_t)DMA_SxFCR_FTH)    /*!< FIFO threshold full configuration          */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Memory_burst DMA Memory burst
+  * @brief    DMA memory burst
+  * @{
+  */
+#define DMA_MBURST_SINGLE       ((uint32_t)0x00000000U)
+#define DMA_MBURST_INC4         ((uint32_t)DMA_SxCR_MBURST_0)
+#define DMA_MBURST_INC8         ((uint32_t)DMA_SxCR_MBURST_1)
+#define DMA_MBURST_INC16        ((uint32_t)DMA_SxCR_MBURST)
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Peripheral_burst DMA Peripheral burst
+  * @brief    DMA peripheral burst
+  * @{
+  */
+#define DMA_PBURST_SINGLE       ((uint32_t)0x00000000U)
+#define DMA_PBURST_INC4         ((uint32_t)DMA_SxCR_PBURST_0)
+#define DMA_PBURST_INC8         ((uint32_t)DMA_SxCR_PBURST_1)
+#define DMA_PBURST_INC16        ((uint32_t)DMA_SxCR_PBURST)
+/**
+  * @}
+  */
+
+/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
+  * @brief    DMA interrupts definition
+  * @{
+  */
+#define DMA_IT_TC                         ((uint32_t)DMA_SxCR_TCIE)
+#define DMA_IT_HT                         ((uint32_t)DMA_SxCR_HTIE)
+#define DMA_IT_TE                         ((uint32_t)DMA_SxCR_TEIE)
+#define DMA_IT_DME                        ((uint32_t)DMA_SxCR_DMEIE)
+#define DMA_IT_FE                         ((uint32_t)0x00000080U)
+/**
+  * @}
+  */
+
+/** @defgroup DMA_flag_definitions DMA flag definitions
+  * @brief    DMA flag definitions
+  * @{
+  */
+#define DMA_FLAG_FEIF0_4                    ((uint32_t)0x00000001U)
+#define DMA_FLAG_DMEIF0_4                   ((uint32_t)0x00000004U)
+#define DMA_FLAG_TEIF0_4                    ((uint32_t)0x00000008U)
+#define DMA_FLAG_HTIF0_4                    ((uint32_t)0x00000010U)
+#define DMA_FLAG_TCIF0_4                    ((uint32_t)0x00000020U)
+#define DMA_FLAG_FEIF1_5                    ((uint32_t)0x00000040U)
+#define DMA_FLAG_DMEIF1_5                   ((uint32_t)0x00000100U)
+#define DMA_FLAG_TEIF1_5                    ((uint32_t)0x00000200U)
+#define DMA_FLAG_HTIF1_5                    ((uint32_t)0x00000400U)
+#define DMA_FLAG_TCIF1_5                    ((uint32_t)0x00000800U)
+#define DMA_FLAG_FEIF2_6                    ((uint32_t)0x00010000U)
+#define DMA_FLAG_DMEIF2_6                   ((uint32_t)0x00040000U)
+#define DMA_FLAG_TEIF2_6                    ((uint32_t)0x00080000U)
+#define DMA_FLAG_HTIF2_6                    ((uint32_t)0x00100000U)
+#define DMA_FLAG_TCIF2_6                    ((uint32_t)0x00200000U)
+#define DMA_FLAG_FEIF3_7                    ((uint32_t)0x00400000U)
+#define DMA_FLAG_DMEIF3_7                   ((uint32_t)0x01000000U)
+#define DMA_FLAG_TEIF3_7                    ((uint32_t)0x02000000U)
+#define DMA_FLAG_HTIF3_7                    ((uint32_t)0x04000000U)
+#define DMA_FLAG_TCIF3_7                    ((uint32_t)0x08000000U)
+/**
+  * @}
+  */
+
+/** @defgroup BDMA_flag_definitions BDMA flag definitions
+  * @brief    BDMA flag definitions
+  * @{
+  */
+#define BDMA_FLAG_GL0                      ((uint32_t)0x00000001)
+#define BDMA_FLAG_TC0                      ((uint32_t)0x00000002)
+#define BDMA_FLAG_HT0                      ((uint32_t)0x00000004)
+#define BDMA_FLAG_TE0                      ((uint32_t)0x00000008)
+#define BDMA_FLAG_GL1                      ((uint32_t)0x00000010)
+#define BDMA_FLAG_TC1                      ((uint32_t)0x00000020)
+#define BDMA_FLAG_HT1                      ((uint32_t)0x00000040)
+#define BDMA_FLAG_TE1                      ((uint32_t)0x00000080)
+#define BDMA_FLAG_GL2                      ((uint32_t)0x00000100)
+#define BDMA_FLAG_TC2                      ((uint32_t)0x00000200)
+#define BDMA_FLAG_HT2                      ((uint32_t)0x00000400)
+#define BDMA_FLAG_TE2                      ((uint32_t)0x00000800)
+#define BDMA_FLAG_GL3                      ((uint32_t)0x00001000)
+#define BDMA_FLAG_TC3                      ((uint32_t)0x00002000)
+#define BDMA_FLAG_HT3                      ((uint32_t)0x00004000)
+#define BDMA_FLAG_TE3                      ((uint32_t)0x00008000)
+#define BDMA_FLAG_GL4                      ((uint32_t)0x00010000)
+#define BDMA_FLAG_TC4                      ((uint32_t)0x00020000)
+#define BDMA_FLAG_HT4                      ((uint32_t)0x00040000)
+#define BDMA_FLAG_TE4                      ((uint32_t)0x00080000)
+#define BDMA_FLAG_GL5                      ((uint32_t)0x00100000)
+#define BDMA_FLAG_TC5                      ((uint32_t)0x00200000)
+#define BDMA_FLAG_HT5                      ((uint32_t)0x00400000)
+#define BDMA_FLAG_TE5                      ((uint32_t)0x00800000)
+#define BDMA_FLAG_GL6                      ((uint32_t)0x01000000)
+#define BDMA_FLAG_TC6                      ((uint32_t)0x02000000)
+#define BDMA_FLAG_HT6                      ((uint32_t)0x04000000)
+#define BDMA_FLAG_TE6                      ((uint32_t)0x08000000)
+#define BDMA_FLAG_GL7                      ((uint32_t)0x10000000)
+#define BDMA_FLAG_TC7                      ((uint32_t)0x20000000)
+#define BDMA_FLAG_HT7                      ((uint32_t)0x40000000)
+#define BDMA_FLAG_TE7                      ((uint32_t)0x80000000)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DMA_Exported_Macros DMA Exported Macros
+  * @{
+  */
+
+/** @brief Reset DMA handle state
+  * @param  __HANDLE__: specifies the DMA handle.
+  * @retval None
+  */
+#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
+
+/**
+  * @brief  Return the current DMA Stream FIFO filled level.
+  * @param  __HANDLE__: DMA handle
+  * @retval The FIFO filling state.
+  *           - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
+  *                                              and not empty.
+  *           - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
+  *           - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
+  *           - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
+  *           - DMA_FIFOStatus_Empty: when FIFO is empty
+  *           - DMA_FIFOStatus_Full: when FIFO is full
+  */
+#define __HAL_DMA_GET_FS(__HANDLE__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (DMA_SxFCR_FS)) : 0)
+
+/**
+  * @brief  Enable the specified DMA Stream.
+  * @param  __HANDLE__: DMA handle
+  * @retval None
+  */
+#define __HAL_DMA_ENABLE(__HANDLE__) \
+((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |=  DMA_SxCR_EN) : \
+(((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |=  BDMA_CCR_EN))
+
+/**
+  * @brief  Disable the specified DMA Stream.
+  * @param  __HANDLE__: DMA handle
+  * @retval None
+  */
+#define __HAL_DMA_DISABLE(__HANDLE__) \
+((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &=  ~DMA_SxCR_EN) : \
+(((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &=  ~BDMA_CCR_EN))
+
+/* Interrupt & Flag management */
+
+/**
+  * @brief  Return the current DMA Stream transfer complete flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified transfer complete flag index.
+  */
+#if defined(BDMA1)
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TCIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TCIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TCIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TCIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_TC0  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_TC0  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_TC1  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_TC1  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_TC2  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_TC2  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_TC3  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_TC3  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_TC4  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_TC4  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_TC5  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_TC5  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_TC6  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_TC6  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_TC7  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_TC7  :\
+ (uint32_t)0x00000000)
+#else
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TCIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TCIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TCIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TCIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_TC0   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_TC1   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_TC2   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_TC3   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_TC4   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_TC5   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TC6   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TC7   :\
+ (uint32_t)0x00000000)
+#endif /* BDMA1 */
+
+/**
+  * @brief  Return the current DMA Stream half transfer complete flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified half transfer complete flag index.
+  */
+#if defined(BDMA1)
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_HTIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_HTIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_HTIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_HTIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_HT0  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_HT0  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_HT1  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_HT1  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_HT2  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_HT2  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_HT3  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_HT3  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_HT4  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_HT4  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_HT5  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_HT5  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_HT6  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_HT6  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_HT7  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_HT7  :\
+ (uint32_t)0x00000000)
+#else
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_HTIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_HTIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_HTIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_HTIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_HT0   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_HT1   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_HT2   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_HT3   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_HT4   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_HT5   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_HT6   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_HT7   :\
+ (uint32_t)0x00000000)
+#endif /* BDMA1 */
+
+/**
+  * @brief  Return the current DMA Stream transfer error flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified transfer error flag index.
+  */
+#if defined(BDMA1)
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_TE0  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_TE0  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_TE1  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_TE1  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_TE2  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_TE2  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_TE3  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_TE3  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_TE4  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_TE4  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_TE5  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_TE5  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_TE6  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_TE6  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_TE7  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_TE7  :\
+ (uint32_t)0x00000000)
+#else
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_TE0   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_TE1   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_TE2   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_TE3   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_TE4   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_TE5   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TE6   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TE7   :\
+ (uint32_t)0x00000000)
+#endif /* BDMA1 */
+
+/**
+  * @brief  Return the current DMA Stream FIFO error flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified FIFO error flag index.
+  */
+#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_FEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_FEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_FEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_FEIF3_7 :\
+  (uint32_t)0x00000000)
+
+/**
+  * @brief  Return the current DMA Stream direct mode error flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified direct mode error flag index.
+  */
+#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_DMEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_DMEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_DMEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_DMEIF3_7 :\
+  (uint32_t)0x00000000)
+
+/**
+  * @brief  Returns the current BDMA Channel Global interrupt flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified transfer error flag index.
+  */
+#if defined(BDMA1)
+#define __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_ISR_GIF0 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_ISR_GIF0 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_ISR_GIF1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_ISR_GIF1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_ISR_GIF2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_ISR_GIF2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_ISR_GIF3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_ISR_GIF3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_ISR_GIF4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_ISR_GIF4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_ISR_GIF5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_ISR_GIF5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_ISR_GIF6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_ISR_GIF6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_ISR_GIF7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_ISR_GIF7 :\
+ (uint32_t)0x00000000)
+#else
+#define __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_ISR_GIF0 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_ISR_GIF1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_ISR_GIF2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_ISR_GIF3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_ISR_GIF4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_ISR_GIF5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_ISR_GIF6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_ISR_GIF7 :\
+  (uint32_t)0x00000000)
+#endif /* BDMA1 */
+
+/**
+  * @brief  Get the DMA Stream pending flags.
+  * @param  __HANDLE__: DMA handle
+  * @param  __FLAG__: Get the specified flag.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
+  *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
+  *            @arg DMA_FLAG_TEIFx: Transfer error flag.
+  *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.
+  *            @arg DMA_FLAG_FEIFx: FIFO error flag.
+  *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
+  * @retval The state of FLAG (SET or RESET).
+  */
+#if defined(BDMA1)
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)BDMA1_Channel7)?  (BDMA2->ISR & (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7  )?  (BDMA1->ISR & (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3  )?  (DMA2->HISR & (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7  )?  (DMA2->LISR & (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3  )?  (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
+#else
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->ISR & (__FLAG__))  :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
+#endif /* BDMA1 */
+
+/**
+  * @brief  Clear the DMA Stream pending flags.
+  * @param  __HANDLE__: DMA handle
+  * @param  __FLAG__: specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
+  *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
+  *            @arg DMA_FLAG_TEIFx: Transfer error flag.
+  *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.
+  *            @arg DMA_FLAG_FEIFx: FIFO error flag.
+  *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
+  * @retval None
+  */
+#if defined(BDMA1)
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)BDMA1_Channel7)? (BDMA2->IFCR = (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)?  (BDMA1->IFCR = (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)?  (DMA2->HIFCR = (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)?  (DMA2->LIFCR = (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)?  (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
+#else
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->IFCR = (__FLAG__))  :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
+#endif /* BDMA1 */
+
+#define DMA_TO_BDMA_IT(__DMA_IT__) \
+((((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE |BDMA_CCR_TEIE) :\
+ (((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT)) == (DMA_IT_TC | DMA_IT_HT)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE) :\
+ (((__DMA_IT__) & (DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_HTIE |BDMA_CCR_TEIE)  :\
+ (((__DMA_IT__) & (DMA_IT_TC | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_TE)) ? (BDMA_CCR_TCIE |BDMA_CCR_TEIE)  :\
+ ((__DMA_IT__) == DMA_IT_TC) ? BDMA_CCR_TCIE :\
+ ((__DMA_IT__) == DMA_IT_HT) ? BDMA_CCR_HTIE :\
+ ((__DMA_IT__) == DMA_IT_TE) ? BDMA_CCR_TEIE :\
+ (uint32_t)0x00000000)
+
+
+#define __HAL_BDMA_CHANNEL_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
+(((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |= (DMA_TO_BDMA_IT(__INTERRUPT__)))
+
+#define __HAL_DMA_STREAM_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((__INTERRUPT__) != DMA_IT_FE)? \
+(((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |= (__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR |= (__INTERRUPT__)))
+
+/**
+  * @brief  Enable the specified DMA Stream interrupts.
+  * @param  __HANDLE__: DMA handle
+  * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+  *        This parameter can be one of the following values:
+  *           @arg DMA_IT_TC: Transfer complete interrupt mask.
+  *           @arg DMA_IT_HT: Half transfer complete interrupt mask.
+  *           @arg DMA_IT_TE: Transfer error interrupt mask.
+  *           @arg DMA_IT_FE: FIFO error interrupt mask.
+  *           @arg DMA_IT_DME: Direct mode error interrupt.
+  * @retval None
+  */
+#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))?\
+                                                        (__HAL_DMA_STREAM_ENABLE_IT((__HANDLE__), (__INTERRUPT__))) :\
+                                                        (__HAL_BDMA_CHANNEL_ENABLE_IT((__HANDLE__), (__INTERRUPT__))))
+
+
+#define __HAL_BDMA_CHANNEL_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &= ~(DMA_TO_BDMA_IT(__INTERRUPT__)))
+
+#define __HAL_DMA_STREAM_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \
+(((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &= ~(__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR &= ~(__INTERRUPT__)))
+
+/**
+  * @brief  Disable the specified DMA Stream interrupts.
+  * @param  __HANDLE__: DMA handle
+  * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+  *         This parameter can be one of the following values:
+  *            @arg DMA_IT_TC: Transfer complete interrupt mask.
+  *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
+  *            @arg DMA_IT_TE: Transfer error interrupt mask.
+  *            @arg DMA_IT_FE: FIFO error interrupt mask.
+  *            @arg DMA_IT_DME: Direct mode error interrupt.
+  * @retval None
+  */
+#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))?\
+                                                         (__HAL_DMA_STREAM_DISABLE_IT((__HANDLE__), (__INTERRUPT__))) :\
+                                                         (__HAL_BDMA_CHANNEL_DISABLE_IT((__HANDLE__), (__INTERRUPT__))))
+
+
+#define __HAL_BDMA_CHANNEL_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  ((((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR & (DMA_TO_BDMA_IT(__INTERRUPT__))))
+
+#define __HAL_DMA_STREAM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \
+                                                        (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR & (__INTERRUPT__)) : \
+                                                        (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (__INTERRUPT__)))
+
+/**
+  * @brief  Check whether the specified DMA Stream interrupt is enabled or not.
+  * @param  __HANDLE__: DMA handle
+  * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
+  *         This parameter can be one of the following values:
+  *            @arg DMA_IT_TC: Transfer complete interrupt mask.
+  *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
+  *            @arg DMA_IT_TE: Transfer error interrupt mask.
+  *            @arg DMA_IT_FE: FIFO error interrupt mask.
+  *            @arg DMA_IT_DME: Direct mode error interrupt.
+  * @retval The state of DMA_IT.
+  */
+#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \
+                                                            (__HAL_DMA_STREAM_GET_IT_SOURCE((__HANDLE__), (__INTERRUPT__))) :\
+                                                            (__HAL_BDMA_CHANNEL_GET_IT_SOURCE((__HANDLE__), (__INTERRUPT__))))
+
+/**
+  * @brief  Writes the number of data units to be transferred on the DMA Stream.
+  * @param  __HANDLE__: DMA handle
+  * @param  __COUNTER__: Number of data units to be transferred (from 0 to 65535)
+  *          Number of data items depends only on the Peripheral data format.
+  *
+  * @note   If Peripheral data format is Bytes: number of data units is equal
+  *         to total number of bytes to be transferred.
+  *
+  * @note   If Peripheral data format is Half-Word: number of data units is
+  *         equal to total number of bytes to be transferred / 2.
+  *
+  * @note   If Peripheral data format is Word: number of data units is equal
+  *         to total  number of bytes to be transferred / 4.
+  *
+  * @retval The number of remaining data units in the current DMAy Streamx transfer.
+  */
+#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \
+                                                        (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR = (uint16_t)(__COUNTER__)) :\
+                                                        (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CNDTR = (uint16_t)(__COUNTER__)))
+
+/**
+  * @brief  Returns the number of remaining data units in the current DMAy Streamx transfer.
+  * @param  __HANDLE__: DMA handle
+  *
+  * @retval The number of remaining data units in the current DMA Stream transfer.
+  */
+#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \
+                                           (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR) :\
+                                           (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CNDTR))
+
+/**
+  * @}
+  */
+
+/* Include DMA HAL Extension module */
+#include "stm32h7xx_hal_dma_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Functions DMA Exported Functions
+  * @brief    DMA Exported functions
+  * @{
+  */
+
+/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief   Initialization and de-initialization functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
+  * @brief   I/O operation functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
+void              HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
+  * @brief    Peripheral State functions
+  * @{
+  */
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
+uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+/* Private Constants -------------------------------------------------------------*/
+/** @defgroup DMA_Private_Constants DMA Private Constants
+  * @brief    DMA private defines and constants
+  * @{
+  */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DMA_Private_Macros DMA Private Macros
+  * @brief    DMA private macros
+  * @{
+  */
+
+#if defined(ADC3)
+#define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_ADC3))
+#else
+#define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_USART10_TX))
+#endif /* ADC3 */
+
+#if defined(ADC3)
+#define IS_BDMA_REQUEST(REQUEST) (((REQUEST) <= BDMA_REQUEST_ADC3))
+#else
+#define IS_BDMA_REQUEST(REQUEST) (((REQUEST) <= BDMA_REQUEST_DFSDM2_FLT0))
+#endif /* ADC3 */
+
+#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
+                                     ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
+                                     ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
+
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
+
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
+                                            ((STATE) == DMA_PINC_DISABLE))
+
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
+                                        ((STATE) == DMA_MINC_DISABLE))
+
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
+                                           ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
+                                           ((SIZE) == DMA_PDATAALIGN_WORD))
+
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
+                                       ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
+                                       ((SIZE) == DMA_MDATAALIGN_WORD ))
+
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )           || \
+                           ((MODE) == DMA_CIRCULAR)          || \
+                           ((MODE) == DMA_PFCTRL)            || \
+                           ((MODE) == DMA_DOUBLE_BUFFER_M0)  || \
+                           ((MODE) == DMA_DOUBLE_BUFFER_M1))
+
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
+                                   ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
+                                   ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
+                                   ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
+
+#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
+                                       ((STATE) == DMA_FIFOMODE_ENABLE))
+
+#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
+                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL)      || \
+                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
+                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
+
+#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
+                                    ((BURST) == DMA_MBURST_INC4)   || \
+                                    ((BURST) == DMA_MBURST_INC8)   || \
+                                    ((BURST) == DMA_MBURST_INC16))
+
+#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
+                                        ((BURST) == DMA_PBURST_INC4)   || \
+                                        ((BURST) == DMA_PBURST_INC8)   || \
+                                        ((BURST) == DMA_PBURST_INC16))
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DMA_Private_Functions DMA Private Functions
+  * @brief    DMA private  functions
+  * @{
+  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h
new file mode 100644
index 00000000..4125ae7e
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h
@@ -0,0 +1,312 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_dma_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMA HAL extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_DMA_EX_H
+#define STM32H7xx_HAL_DMA_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DMAEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DMAEx_Exported_Types DMAEx Exported Types
+  * @brief DMAEx Exported types
+  * @{
+  */
+
+/**
+  * @brief  HAL DMA Memory definition
+  */
+typedef enum
+{
+  MEMORY0      = 0x00U,    /*!< Memory 0     */
+  MEMORY1      = 0x01U,    /*!< Memory 1     */
+
+}HAL_DMA_MemoryTypeDef;
+
+/**
+  * @brief  HAL DMAMUX Synchronization configuration structure definition
+  */
+typedef struct
+{
+  uint32_t SyncSignalID;  /*!< Specifies the synchronization signal gating the DMA request in periodic mode.
+                              This parameter can be a value of @ref DMAEx_MUX_SyncSignalID_selection */
+
+  uint32_t SyncPolarity;  /*!< Specifies the polarity of the signal on which the DMA request is synchronized.
+                              This parameter can be a value of @ref DMAEx_MUX_SyncPolarity_selection */
+
+  FunctionalState SyncEnable;  /*!< Specifies if the synchronization shall be enabled or disabled
+                                    This parameter can take the value ENABLE or DISABLE*/
+
+
+  FunctionalState EventEnable;    /*!< Specifies if an event shall be generated once the RequestNumber is reached.
+                                       This parameter can take the value ENABLE or DISABLE */
+
+  uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be authorized after a sync event.
+                               This parameters can be in the range 1 to 32 */
+
+}HAL_DMA_MuxSyncConfigTypeDef;
+
+
+/**
+  * @brief  HAL DMAMUX request generator parameters structure definition
+  */
+typedef struct
+{
+ uint32_t SignalID;      /*!< Specifies the ID of the signal used for DMAMUX request generator
+                              This parameter can be a value of @ref DMAEx_MUX_SignalGeneratorID_selection */
+
+  uint32_t Polarity;       /*!< Specifies the polarity of the signal on which the request is generated.
+                             This parameter can be a value of @ref DMAEx_MUX_RequestGeneneratorPolarity_selection */
+
+  uint32_t RequestNumber;  /*!< Specifies the number of DMA request that will be generated after a signal event.
+                                This parameters can be in the range 1 to 32 */
+
+}HAL_DMA_MuxRequestGeneratorConfigTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMAEx_Exported_Constants DMA Exported Constants
+  * @brief    DMAEx Exported constants
+  * @{
+  */
+
+/** @defgroup DMAEx_MUX_SyncSignalID_selection DMAEx MUX SyncSignalID selection
+  * @brief    DMAEx MUX SyncSignalID selection
+  * @{
+  */
+#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT   0U   /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel0 Event */
+#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT   1U   /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel1 Event */
+#define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT   2U   /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel2 Event */
+#define HAL_DMAMUX1_SYNC_LPTIM1_OUT        3U   /*!< DMAMUX1 synchronization Signal is LPTIM1 OUT             */
+#define HAL_DMAMUX1_SYNC_LPTIM2_OUT        4U   /*!< DMAMUX1 synchronization Signal is LPTIM2 OUT             */
+#define HAL_DMAMUX1_SYNC_LPTIM3_OUT        5U   /*!< DMAMUX1 synchronization Signal is LPTIM3 OUT             */
+#define HAL_DMAMUX1_SYNC_EXTI0             6U   /*!< DMAMUX1 synchronization Signal is EXTI0 IT               */
+#define HAL_DMAMUX1_SYNC_TIM12_TRGO        7U   /*!< DMAMUX1 synchronization Signal is TIM12 TRGO             */
+
+#define HAL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT   0U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel0 Event */
+#define HAL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT   1U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel1 Event */
+#define HAL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT   2U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel2 Event */
+#define HAL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT   3U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel3 Event */
+#define HAL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT   4U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel4 Event */
+#define HAL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT   5U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel5 Event */
+#define HAL_DMAMUX2_SYNC_LPUART1_RX_WKUP   6U   /*!< DMAMUX2 synchronization Signal is LPUART1 RX Wakeup      */
+#define HAL_DMAMUX2_SYNC_LPUART1_TX_WKUP   7U   /*!< DMAMUX2 synchronization Signal is LPUART1 TX Wakeup      */
+#define HAL_DMAMUX2_SYNC_LPTIM2_OUT        8U   /*!< DMAMUX2 synchronization Signal is LPTIM2 output          */
+#define HAL_DMAMUX2_SYNC_LPTIM3_OUT        9U   /*!< DMAMUX2 synchronization Signal is LPTIM3 output          */
+#define HAL_DMAMUX2_SYNC_I2C4_WKUP        10U   /*!< DMAMUX2 synchronization Signal is I2C4 Wakeup            */
+#define HAL_DMAMUX2_SYNC_SPI6_WKUP        11U   /*!< DMAMUX2 synchronization Signal is SPI6 Wakeup            */
+#define HAL_DMAMUX2_SYNC_COMP1_OUT        12U   /*!< DMAMUX2 synchronization Signal is Comparator 1 output    */
+#define HAL_DMAMUX2_SYNC_RTC_WKUP         13U   /*!< DMAMUX2 synchronization Signal is RTC Wakeup             */
+#define HAL_DMAMUX2_SYNC_EXTI0            14U   /*!< DMAMUX2 synchronization Signal is EXTI0 IT               */
+#define HAL_DMAMUX2_SYNC_EXTI2            15U   /*!< DMAMUX2 synchronization Signal is EXTI2 IT               */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMAEx_MUX_SyncPolarity_selection DMAEx MUX SyncPolarity selection
+  * @brief    DMAEx MUX SyncPolarity selection
+  * @{
+  */
+#define HAL_DMAMUX_SYNC_NO_EVENT        0x00000000U             /*!< block synchronization events                    */
+#define HAL_DMAMUX_SYNC_RISING          DMAMUX_CxCR_SPOL_0      /*!< synchronize with rising edge events             */
+#define HAL_DMAMUX_SYNC_FALLING         DMAMUX_CxCR_SPOL_1      /*!< synchronize with falling edge events            */
+#define HAL_DMAMUX_SYNC_RISING_FALLING  DMAMUX_CxCR_SPOL        /*!< synchronize with rising and falling edge events */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup DMAEx_MUX_SignalGeneratorID_selection DMAEx MUX SignalGeneratorID selection
+  * @brief    DMAEx MUX SignalGeneratorID selection
+  * @{
+  */
+#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT   0U   /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel0 Event */
+#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT   1U   /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel1 Event */
+#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT   2U   /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel2 Event */
+#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT        3U   /*!< DMAMUX1 Request generator Signal is LPTIM1 OUT             */
+#define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT        4U   /*!< DMAMUX1 Request generator Signal is LPTIM2 OUT             */
+#define HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT        5U   /*!< DMAMUX1 Request generator Signal is LPTIM3 OUT             */
+#define HAL_DMAMUX1_REQ_GEN_EXTI0             6U   /*!< DMAMUX1 Request generator Signal is EXTI0 IT               */
+#define HAL_DMAMUX1_REQ_GEN_TIM12_TRGO        7U   /*!< DMAMUX1 Request generator Signal is TIM12 TRGO             */
+
+#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT   0U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel0 Event */
+#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT   1U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel1 Event */
+#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT   2U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel2 Event */
+#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT   3U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel3 Event */
+#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT   4U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel4 Event */
+#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT   5U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel5 Event */
+#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT   6U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel6 Event */
+#define HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP   7U   /*!< DMAMUX2 Request generator Signal is LPUART1 RX Wakeup      */
+#define HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP   8U   /*!< DMAMUX2 Request generator Signal is LPUART1 TX Wakeup      */
+#define HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP       9U   /*!< DMAMUX2 Request generator Signal is LPTIM2 Wakeup          */
+#define HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT       10U   /*!< DMAMUX2 Request generator Signal is LPTIM2 OUT             */
+#define HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP      11U   /*!< DMAMUX2 Request generator Signal is LPTIM3 Wakeup          */
+#define HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT       12U   /*!< DMAMUX2 Request generator Signal is LPTIM3 OUT             */
+#if defined(LPTIM4)
+#define HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP      13U   /*!< DMAMUX2 Request generator Signal is LPTIM4 Wakeup          */
+#endif /* LPTIM4 */
+#if defined(LPTIM5)
+#define HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP      14U   /*!< DMAMUX2 Request generator Signal is LPTIM5 Wakeup          */
+#endif /* LPTIM5 */
+#define HAL_DMAMUX2_REQ_GEN_I2C4_WKUP        15U   /*!< DMAMUX2 Request generator Signal is I2C4 Wakeup            */
+#define HAL_DMAMUX2_REQ_GEN_SPI6_WKUP        16U   /*!< DMAMUX2 Request generator Signal is SPI6 Wakeup            */
+#define HAL_DMAMUX2_REQ_GEN_COMP1_OUT        17U   /*!< DMAMUX2 Request generator Signal is Comparator 1 output    */
+#define HAL_DMAMUX2_REQ_GEN_COMP2_OUT        18U   /*!< DMAMUX2 Request generator Signal is Comparator 2 output    */
+#define HAL_DMAMUX2_REQ_GEN_RTC_WKUP         19U   /*!< DMAMUX2 Request generator Signal is RTC Wakeup             */
+#define HAL_DMAMUX2_REQ_GEN_EXTI0            20U   /*!< DMAMUX2 Request generator Signal is EXTI0                  */
+#define HAL_DMAMUX2_REQ_GEN_EXTI2            21U   /*!< DMAMUX2 Request generator Signal is EXTI2                  */
+#define HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT      22U   /*!< DMAMUX2 Request generator Signal is I2C4 IT Event          */
+#define HAL_DMAMUX2_REQ_GEN_SPI6_IT          23U   /*!< DMAMUX2 Request generator Signal is SPI6 IT                */
+#define HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT    24U   /*!< DMAMUX2 Request generator Signal is LPUART1 Tx IT          */
+#define HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT    25U   /*!< DMAMUX2 Request generator Signal is LPUART1 Rx IT          */
+#if defined(ADC3)
+#define HAL_DMAMUX2_REQ_GEN_ADC3_IT          26U   /*!< DMAMUX2 Request generator Signal is ADC3 IT                */
+#define HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT    27U   /*!< DMAMUX2 Request generator Signal is ADC3 Analog Watchdog 1 output */
+#endif /* ADC3 */
+#define HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT      28U   /*!< DMAMUX2 Request generator Signal is BDMA Channel 0 IT      */
+#define HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT      29U   /*!< DMAMUX2 Request generator Signal is BDMA Channel 1 IT      */
+
+
+/**
+  * @}
+  */
+
+/** @defgroup DMAEx_MUX_RequestGeneneratorPolarity_selection DMAEx MUX RequestGeneneratorPolarity selection
+  * @brief    DMAEx MUX RequestGeneneratorPolarity selection
+  * @{
+  */
+#define HAL_DMAMUX_REQ_GEN_NO_EVENT        0x00000000U           /*!< block request generator events                     */
+#define HAL_DMAMUX_REQ_GEN_RISING          DMAMUX_RGxCR_GPOL_0  /*!< generate request on rising edge events             */
+#define HAL_DMAMUX_REQ_GEN_FALLING         DMAMUX_RGxCR_GPOL_1  /*!< generate request on falling edge events            */
+#define HAL_DMAMUX_REQ_GEN_RISING_FALLING  DMAMUX_RGxCR_GPOL    /*!< generate request on rising and falling edge events */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
+  * @brief   DMAEx Exported functions
+  * @{
+  */
+
+/** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions
+  * @brief   Extended features functions
+  * @{
+  */
+
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory);
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig);
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig);
+HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma);
+
+void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DMAEx_Private_Macros DMA Private Macros
+  * @brief    DMAEx private macros
+  * @{
+  */
+
+#define IS_DMA_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_TIM12_TRGO)
+#define IS_BDMA_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX2_SYNC_EXTI2)
+
+#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
+
+#define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT)    || \
+                                           ((POLARITY) == HAL_DMAMUX_SYNC_RISING)   || \
+                                           ((POLARITY) == HAL_DMAMUX_SYNC_FALLING)  || \
+                                           ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING))
+
+#define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE)   || ((SYNC) == ENABLE))
+
+#define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE)   || \
+                                     ((EVENT) == ENABLE))
+
+#define IS_DMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_TIM12_TRGO)
+#define IS_BDMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT)
+
+#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
+
+#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT) || \
+                                                  ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING)   || \
+                                                  ((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING)   || \
+                                                  ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING))
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DMAEx_Private_Functions DMAEx Private Functions
+  * @brief DMAEx Private functions
+  * @{
+  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h
new file mode 100644
index 00000000..6273f3c3
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h
@@ -0,0 +1,507 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_exti.h
+  * @author  MCD Application Team
+  * @brief   Header file of EXTI HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_EXTI_H
+#define STM32H7xx_HAL_EXTI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup EXTI EXTI
+  * @brief EXTI HAL module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup EXTI_Exported_Types EXTI Exported Types
+  * @{
+  */
+typedef enum
+{
+  HAL_EXTI_COMMON_CB_ID          = 0x00U,
+} EXTI_CallbackIDTypeDef;
+
+
+/**
+  * @brief  EXTI Handle structure definition
+  */
+typedef struct
+{
+  uint32_t Line;                    /*!<  Exti line number */
+  void (* PendingCallback)(void);   /*!<  Exti pending callback */
+} EXTI_HandleTypeDef;
+
+/**
+  * @brief  EXTI Configuration structure definition
+  */
+typedef struct
+{
+  uint32_t Line;           /*!< The Exti line to be configured. This parameter
+                                can be a value of @ref EXTI_Line */
+  uint32_t Mode;           /*!< The Exit Mode to be configured for a core.
+                                This parameter can be a combination of @ref EXTI_Mode */
+  uint32_t Trigger;        /*!< The Exti Trigger to be configured. This parameter
+                                can be a value of @ref EXTI_Trigger */
+  uint32_t GPIOSel;        /*!< The Exti GPIO multiplexer selection to be configured.
+                                This parameter is only possible for line 0 to 15. It
+                                can be a value of @ref EXTI_GPIOSel */
+
+  uint32_t PendClearSource; /*!< Specifies the event pending clear source for D3/SRD
+                                 domain. This parameter can be a value of @ref
+                                 EXTI_PendClear_Source */
+
+} EXTI_ConfigTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
+  * @{
+  */
+
+/** @defgroup EXTI_Line  EXTI Line
+  * @{
+  */
+#define EXTI_LINE_0                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x00U)
+#define EXTI_LINE_1                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x01U)
+#define EXTI_LINE_2                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x02U)
+#define EXTI_LINE_3                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x03U)
+#define EXTI_LINE_4                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x04U)
+#define EXTI_LINE_5                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x05U)
+#define EXTI_LINE_6                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x06U)
+#define EXTI_LINE_7                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x07U)
+#define EXTI_LINE_8                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x08U)
+#define EXTI_LINE_9                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x09U)
+#define EXTI_LINE_10                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x0AU)
+#define EXTI_LINE_11                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x0BU)
+#define EXTI_LINE_12                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x0CU)
+#define EXTI_LINE_13                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x0DU)
+#define EXTI_LINE_14                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x0EU)
+#define EXTI_LINE_15                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x0FU)
+#define EXTI_LINE_16                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x10U)
+#define EXTI_LINE_17                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x11U)
+#define EXTI_LINE_18                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x12U)
+#define EXTI_LINE_19                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x13U)
+#define EXTI_LINE_20                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x14U)
+#define EXTI_LINE_21                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x15U)
+#define EXTI_LINE_22                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x16U)
+#define EXTI_LINE_23                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x17U)
+#define EXTI_LINE_24                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x18U)
+#define EXTI_LINE_25                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x19U)
+#define EXTI_LINE_26                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1AU)
+#define EXTI_LINE_27                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1BU)
+#define EXTI_LINE_28                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1CU)
+#define EXTI_LINE_29                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1DU)
+#define EXTI_LINE_30                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1EU)
+#define EXTI_LINE_31                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1FU)
+#define EXTI_LINE_32                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x00U)
+#define EXTI_LINE_33                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x01U)
+#define EXTI_LINE_34                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x02U)
+#define EXTI_LINE_35                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x03U)
+#define EXTI_LINE_36                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x04U)
+#define EXTI_LINE_37                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x05U)
+#define EXTI_LINE_38                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x06U)
+#define EXTI_LINE_39                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x07U)
+#define EXTI_LINE_40                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x08U)
+#define EXTI_LINE_41                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x09U)
+#define EXTI_LINE_42                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0AU)
+#define EXTI_LINE_43                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0BU)
+#if !defined(USB2_OTG_FS)
+#define EXTI_LINE_44                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE    | 0x0CU)
+#else
+#define EXTI_LINE_44                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0CU)
+#endif /* USB2_OTG_FS */
+#define EXTI_LINE_45                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE    | 0x0DU)
+#if defined(DSI)
+#define EXTI_LINE_46                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0EU)
+#else
+#define EXTI_LINE_46                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE    | 0x0EU)
+#endif /* DSI */
+#define EXTI_LINE_47                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0FU)
+#define EXTI_LINE_48                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x10U)
+#define EXTI_LINE_49                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x11U)
+#define EXTI_LINE_50                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x12U)
+#define EXTI_LINE_51                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x13U)
+#if !defined(UART9)
+#define EXTI_LINE_52                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x14U)
+#else
+#define EXTI_LINE_52                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x14U)
+#endif /* UART9 */
+#if !defined(USART10)
+#define EXTI_LINE_53                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x15U)
+#else
+#define EXTI_LINE_53                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x15U)
+#endif /* USART10 */
+#define EXTI_LINE_54                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x16U)
+#define EXTI_LINE_55                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x17U)
+#define EXTI_LINE_56                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x18U)
+#define EXTI_LINE_57                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x19U)
+#define EXTI_LINE_58                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1AU)
+#define EXTI_LINE_59                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1BU)
+#define EXTI_LINE_60                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1CU)
+#define EXTI_LINE_61                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1DU)
+#define EXTI_LINE_62                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1EU)
+#define EXTI_LINE_63                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1FU)
+#define EXTI_LINE_64                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x00U)
+#define EXTI_LINE_65                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x01U)
+#define EXTI_LINE_66                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x02U)
+#define EXTI_LINE_67                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x03U)
+#define EXTI_LINE_68                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x04U)
+#define EXTI_LINE_69                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x05U)
+#define EXTI_LINE_70                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x06U)
+#define EXTI_LINE_71                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x07U)
+#define EXTI_LINE_72                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x08U)
+#define EXTI_LINE_73                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x09U)
+#define EXTI_LINE_74                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0AU)
+#if defined(ADC3)
+#define EXTI_LINE_75                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0BU)
+#else
+#define EXTI_LINE_75                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 |  EXTI_TARGET_MSK_NONE   | 0x0BU)
+#endif /* ADC3 */
+#if defined(SAI4)
+#define EXTI_LINE_76                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0CU)
+#else
+#define EXTI_LINE_76                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 |  EXTI_TARGET_MSK_NONE   | 0x0CU)
+#endif /* SAI4 */
+#if defined (DUAL_CORE)
+#define EXTI_LINE_77                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x0DU)
+#define EXTI_LINE_78                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU2| 0x0EU)
+#define EXTI_LINE_79                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x0FU)
+#define EXTI_LINE_80                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU2| 0x10U)
+#else
+#define EXTI_LINE_77                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0DU)
+#define EXTI_LINE_78                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0EU)
+#define EXTI_LINE_79                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0FU)
+#define EXTI_LINE_80                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x10U)
+#endif /* DUAL_CORE */
+
+#define EXTI_LINE_81                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x11U)
+
+#if defined (DUAL_CORE)
+#define EXTI_LINE_82                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU2| 0x12U)
+#else
+#define EXTI_LINE_82                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x12U)
+#endif /* DUAL_CORE */
+
+#define EXTI_LINE_83                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x13U)
+#if defined (DUAL_CORE)
+#define EXTI_LINE_84                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x14U)
+#else
+#define EXTI_LINE_84                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x14U)
+#endif /* DUAL_CORE */
+#define EXTI_LINE_85                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x15U)
+#if defined(ETH)
+#define EXTI_LINE_86                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x16U)
+#else
+#define EXTI_LINE_86                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x16U)
+#endif /* ETH */
+#define EXTI_LINE_87                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x17U)
+#if defined(DTS)
+#define EXTI_LINE_88                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL | 0x18U)
+#endif /* DTS */
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Mode  EXTI Mode
+  * @{
+  */
+#define EXTI_MODE_NONE                      0x00000000U
+#define EXTI_MODE_INTERRUPT                 0x00000001U
+#define EXTI_MODE_EVENT                     0x00000002U
+#if defined(DUAL_CORE)
+#define EXTI_MODE_CORE1_INTERRUPT           EXTI_MODE_INTERRUPT
+#define EXTI_MODE_CORE1_EVENT               EXTI_MODE_EVENT
+#define EXTI_MODE_CORE2_INTERRUPT           0x00000010U
+#define EXTI_MODE_CORE2_EVENT               0x00000020U
+#endif /* DUAL_CORE */
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Trigger  EXTI Trigger
+  * @{
+  */
+#define EXTI_TRIGGER_NONE                   0x00000000U
+#define EXTI_TRIGGER_RISING                 0x00000001U
+#define EXTI_TRIGGER_FALLING                0x00000002U
+#define EXTI_TRIGGER_RISING_FALLING         (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_GPIOSel  EXTI GPIOSel
+  * @brief
+  * @{
+  */
+#define EXTI_GPIOA                          0x00000000U
+#define EXTI_GPIOB                          0x00000001U
+#define EXTI_GPIOC                          0x00000002U
+#define EXTI_GPIOD                          0x00000003U
+#define EXTI_GPIOE                          0x00000004U
+#define EXTI_GPIOF                          0x00000005U
+#define EXTI_GPIOG                          0x00000006U
+#define EXTI_GPIOH                          0x00000007U
+#define EXTI_GPIOI                          0x00000008U
+#define EXTI_GPIOJ                          0x00000009U
+#define EXTI_GPIOK                          0x0000000AU
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_PendClear_Source  EXTI PendClear Source
+  * @brief
+  * @{
+  */
+#define EXTI_D3_PENDCLR_SRC_NONE       0x00000000U /*!< No D3 domain pendclear source , PMRx register to be set to zero  */
+#define EXTI_D3_PENDCLR_SRC_DMACH6     0x00000001U /*!< DMA ch6 event selected as D3 domain pendclear source, PMRx register to be set to 1 */
+#define EXTI_D3_PENDCLR_SRC_DMACH7     0x00000002U /*!< DMA ch7 event selected as D3 domain pendclear source, PMRx register to be set to 1*/
+#if defined (LPTIM4)
+#define EXTI_D3_PENDCLR_SRC_LPTIM4     0x00000003U /*!< LPTIM4 out selected as D3 domain pendclear source, PMRx register to be set to 1    */
+#else
+#define EXTI_D3_PENDCLR_SRC_LPTIM2     0x00000003U /*!< LPTIM2 out selected as D3 domain pendclear source, PMRx register to be set to 1    */
+#endif
+#if defined (LPTIM5)
+#define EXTI_D3_PENDCLR_SRC_LPTIM5     0x00000004U /*!< LPTIM5 out selected as D3 domain pendclear source, PMRx register to be set to 1    */
+#else
+#define EXTI_D3_PENDCLR_SRC_LPTIM3     0x00000004U /*!< LPTIM3 out selected as D3 domain pendclear source, PMRx register to be set to 1    */
+#endif
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants --------------------------------------------------------*/
+/** @defgroup EXTI_Private_Constants EXTI Private Constants
+  * @{
+  */
+/**
+  * @brief  EXTI Line property definition
+  */
+#define EXTI_PROPERTY_SHIFT                 24U
+#define EXTI_DIRECT                         (0x01UL << EXTI_PROPERTY_SHIFT)
+#define EXTI_CONFIG                         (0x02UL << EXTI_PROPERTY_SHIFT)
+#define EXTI_GPIO                           ((0x04UL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
+#define EXTI_RESERVED                       (0x08UL << EXTI_PROPERTY_SHIFT)
+#define EXTI_PROPERTY_MASK                  (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
+
+/**
+  * @brief  EXTI Event presence definition
+  */
+#define EXTI_EVENT_PRESENCE_SHIFT           28U
+#define EXTI_EVENT                          (0x01UL << EXTI_EVENT_PRESENCE_SHIFT)
+#define EXTI_EVENT_PRESENCE_MASK            (EXTI_EVENT)
+
+/**
+  * @brief  EXTI Register and bit usage
+  */
+#define EXTI_REG_SHIFT                      16U
+#define EXTI_REG1                           (0x00UL << EXTI_REG_SHIFT)
+#define EXTI_REG2                           (0x01UL << EXTI_REG_SHIFT)
+#define EXTI_REG3                           (0x02UL << EXTI_REG_SHIFT)
+#define EXTI_REG_MASK                       (EXTI_REG1 | EXTI_REG2 | EXTI_REG3)
+#define EXTI_PIN_MASK                       0x0000001FUL
+
+/**
+  * @brief  EXTI Target and bit usage
+  */
+#define EXTI_TARGET_SHIFT                   20U
+#define EXTI_TARGET_MSK_NONE                (0x00UL << EXTI_TARGET_SHIFT)
+#define EXTI_TARGET_MSK_D3SRD               (0x01UL << EXTI_TARGET_SHIFT)
+#define EXTI_TARGET_MSK_CPU1                (0x02UL << EXTI_TARGET_SHIFT)
+#if defined (DUAL_CORE)
+#define EXTI_TARGET_MSK_CPU2                (0x04UL << EXTI_TARGET_SHIFT)
+#define EXTI_TARGET_MASK                    (EXTI_TARGET_MSK_D3SRD | EXTI_TARGET_MSK_CPU1 | EXTI_TARGET_MSK_CPU2)
+#define EXTI_TARGET_MSK_ALL_CPU             (EXTI_TARGET_MSK_CPU1 | EXTI_TARGET_MSK_CPU2)
+#else
+#define EXTI_TARGET_MASK                    (EXTI_TARGET_MSK_D3SRD | EXTI_TARGET_MSK_CPU1)
+#define EXTI_TARGET_MSK_ALL_CPU              EXTI_TARGET_MSK_CPU1
+#endif /* DUAL_CORE */
+#define EXTI_TARGET_MSK_ALL                  EXTI_TARGET_MASK
+
+/**
+  * @brief  EXTI Mask for interrupt & event mode
+  */
+#if defined (DUAL_CORE)
+#define EXTI_MODE_MASK                      (EXTI_MODE_CORE1_EVENT | EXTI_MODE_CORE1_INTERRUPT | EXTI_MODE_CORE2_INTERRUPT | EXTI_MODE_CORE2_EVENT)
+#else
+#define EXTI_MODE_MASK                      (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
+#endif /* DUAL_CORE */
+
+/**
+  * @brief  EXTI Mask for trigger possibilities
+  */
+#define EXTI_TRIGGER_MASK                   (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
+
+/**
+  * @brief  EXTI Line number
+  */
+#if defined (EXTI_LINE_88)
+#define EXTI_LINE_NB                        89UL
+#else
+#define EXTI_LINE_NB                        88UL
+#endif /* EXTI_LINE_88 */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup EXTI_Private_Macros EXTI Private Macros
+  * @{
+  */
+#define IS_EXTI_PROPERTY(__LINE__)      ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
+                                         (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG)          || \
+                                         (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO))
+#if defined (DUAL_CORE)
+#define IS_EXTI_TARGET(__LINE__)        ((((__LINE__) & EXTI_TARGET_MASK)   == EXTI_TARGET_MSK_CPU1)      || \
+                                         (((__LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_CPU2)    || \
+                                         (((__LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL_CPU) || \
+                                         (((__LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL))
+#else
+#define IS_EXTI_TARGET(__LINE__)        ((((__LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_CPU1)   || \
+                                         (((__LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL))
+#endif
+
+#define IS_EXTI_LINE(__LINE__)          ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_EVENT_PRESENCE_MASK | EXTI_REG_MASK | EXTI_PIN_MASK | EXTI_TARGET_MASK)) == 0x00UL) && \
+                                         IS_EXTI_PROPERTY(__LINE__) && IS_EXTI_TARGET(__LINE__) && \
+                                         (((__LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK))      < \
+                                         (((EXTI_LINE_NB / 32UL) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32UL))))
+
+#define IS_EXTI_MODE(__MODE__)          (((__MODE__) & ~EXTI_MODE_MASK) == 0x00UL)
+
+#define IS_EXTI_TRIGGER(__LINE__)       (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00UL)
+
+#define IS_EXTI_PENDING_EDGE(__LINE__)  (((__LINE__) == EXTI_TRIGGER_RISING) || \
+                                         ((__LINE__) == EXTI_TRIGGER_FALLING)|| \
+                                         ((__LINE__) == EXTI_TRIGGER_RISING_FALLING))
+
+#define IS_EXTI_CONFIG_LINE(__LINE__)   (((__LINE__) & EXTI_CONFIG) != 0x00UL)
+
+#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \
+                                         ((__PORT__) == EXTI_GPIOB) || \
+                                         ((__PORT__) == EXTI_GPIOC) || \
+                                         ((__PORT__) == EXTI_GPIOD) || \
+                                         ((__PORT__) == EXTI_GPIOE) || \
+                                         ((__PORT__) == EXTI_GPIOF) || \
+                                         ((__PORT__) == EXTI_GPIOG) || \
+                                         ((__PORT__) == EXTI_GPIOH) || \
+                                         ((__PORT__) == EXTI_GPIOI) || \
+                                         ((__PORT__) == EXTI_GPIOJ) || \
+                                         ((__PORT__) == EXTI_GPIOK))
+
+#define IS_EXTI_GPIO_PIN(__PIN__)       ((__PIN__) < 16UL)
+#if defined (LPTIM4) && defined (LPTIM5)
+#define IS_EXTI_D3_PENDCLR_SRC(__SRC__) (((__SRC__) == EXTI_D3_PENDCLR_SRC_NONE) || \
+                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH6) || \
+                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH7) || \
+                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM4) || \
+                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM5))
+#else
+#define IS_EXTI_D3_PENDCLR_SRC(__SRC__) (((__SRC__) == EXTI_D3_PENDCLR_SRC_NONE) || \
+                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH6) || \
+                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH7) || \
+                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM2) || \
+                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM3))
+#endif /* LPTIM4 && LPTIM5 */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
+  * @brief    EXTI Exported Functions
+  * @{
+  */
+
+/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
+  * @brief    Configuration functions
+  * @{
+  */
+/* Configuration functions ****************************************************/
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
+HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
+HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
+HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
+HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
+  * @brief    IO operation functions
+  * @{
+  */
+/* IO operation functions *****************************************************/
+void              HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
+uint32_t          HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
+void              HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
+void              HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_EXTI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h
new file mode 100644
index 00000000..cfe58cf7
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h
@@ -0,0 +1,2414 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_fdcan.h
+  * @author  MCD Application Team
+  * @brief   Header file of FDCAN HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_FDCAN_H
+#define STM32H7xx_HAL_FDCAN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FDCAN
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FDCAN_Exported_Types FDCAN Exported Types
+  * @{
+  */
+
+/**
+  * @brief HAL State structures definition
+  */
+typedef enum
+{
+  HAL_FDCAN_STATE_RESET      = 0x00U, /*!< FDCAN not yet initialized or disabled */
+  HAL_FDCAN_STATE_READY      = 0x01U, /*!< FDCAN initialized and ready for use   */
+  HAL_FDCAN_STATE_BUSY       = 0x02U, /*!< FDCAN process is ongoing              */
+  HAL_FDCAN_STATE_ERROR      = 0x03U  /*!< FDCAN error state                     */
+} HAL_FDCAN_StateTypeDef;
+
+/**
+  * @brief FDCAN Init structure definition
+  */
+typedef struct
+{
+  uint32_t FrameFormat;                  /*!< Specifies the FDCAN frame format.
+                                              This parameter can be a value of @ref FDCAN_frame_format     */
+
+  uint32_t Mode;                         /*!< Specifies the FDCAN mode.
+                                              This parameter can be a value of @ref FDCAN_operating_mode   */
+
+  FunctionalState AutoRetransmission;    /*!< Enable or disable the automatic retransmission mode.
+                                              This parameter can be set to ENABLE or DISABLE               */
+
+  FunctionalState TransmitPause;         /*!< Enable or disable the Transmit Pause feature.
+                                              This parameter can be set to ENABLE or DISABLE               */
+
+  FunctionalState ProtocolException;      /*!< Enable or disable the Protocol Exception Handling.
+                                              This parameter can be set to ENABLE or DISABLE               */
+
+  uint32_t NominalPrescaler;             /*!< Specifies the value by which the oscillator frequency is
+                                              divided for generating the nominal bit time quanta.
+                                              This parameter must be a number between 1 and 512            */
+
+  uint32_t NominalSyncJumpWidth;         /*!< Specifies the maximum number of time quanta the FDCAN
+                                              hardware is allowed to lengthen or shorten a bit to perform
+                                              resynchronization.
+                                              This parameter must be a number between 1 and 128            */
+
+  uint32_t NominalTimeSeg1;              /*!< Specifies the number of time quanta in Bit Segment 1.
+                                              This parameter must be a number between 2 and 256            */
+
+  uint32_t NominalTimeSeg2;              /*!< Specifies the number of time quanta in Bit Segment 2.
+                                              This parameter must be a number between 2 and 128            */
+
+  uint32_t DataPrescaler;                /*!< Specifies the value by which the oscillator frequency is
+                                              divided for generating the data bit time quanta.
+                                              This parameter must be a number between 1 and 32             */
+
+  uint32_t DataSyncJumpWidth;            /*!< Specifies the maximum number of time quanta the FDCAN
+                                              hardware is allowed to lengthen or shorten a data bit to
+                                              perform resynchronization.
+                                              This parameter must be a number between 1 and 16             */
+
+  uint32_t DataTimeSeg1;                 /*!< Specifies the number of time quanta in Data Bit Segment 1.
+                                              This parameter must be a number between 1 and 32             */
+
+  uint32_t DataTimeSeg2;                 /*!< Specifies the number of time quanta in Data Bit Segment 2.
+                                              This parameter must be a number between 1 and 16             */
+
+  uint32_t MessageRAMOffset;             /*!< Specifies the message RAM start address.
+                                              This parameter must be a number between 0 and 2560           */
+
+  uint32_t StdFiltersNbr;                /*!< Specifies the number of standard Message ID filters.
+                                              This parameter must be a number between 0 and 128            */
+
+  uint32_t ExtFiltersNbr;                /*!< Specifies the number of extended Message ID filters.
+                                              This parameter must be a number between 0 and 64             */
+
+  uint32_t RxFifo0ElmtsNbr;              /*!< Specifies the number of Rx FIFO0 Elements.
+                                              This parameter must be a number between 0 and 64             */
+
+  uint32_t RxFifo0ElmtSize;              /*!< Specifies the Data Field Size in an Rx FIFO 0 element.
+                                              This parameter can be a value of @ref FDCAN_data_field_size  */
+
+  uint32_t RxFifo1ElmtsNbr;              /*!< Specifies the number of Rx FIFO 1 Elements.
+                                              This parameter must be a number between 0 and 64             */
+
+  uint32_t RxFifo1ElmtSize;              /*!< Specifies the Data Field Size in an Rx FIFO 1 element.
+                                              This parameter can be a value of @ref FDCAN_data_field_size  */
+
+  uint32_t RxBuffersNbr;                 /*!< Specifies the number of Dedicated Rx Buffer elements.
+                                              This parameter must be a number between 0 and 64             */
+
+  uint32_t RxBufferSize;                 /*!< Specifies the Data Field Size in an Rx Buffer element.
+                                              This parameter can be a value of @ref FDCAN_data_field_size  */
+
+  uint32_t TxEventsNbr;                  /*!< Specifies the number of Tx Event FIFO elements.
+                                              This parameter must be a number between 0 and 32             */
+
+  uint32_t TxBuffersNbr;                 /*!< Specifies the number of Dedicated Tx Buffers.
+                                              This parameter must be a number between 0 and 32             */
+
+  uint32_t TxFifoQueueElmtsNbr;          /*!< Specifies the number of Tx Buffers used for Tx FIFO/Queue.
+                                              This parameter must be a number between 0 and 32             */
+
+  uint32_t TxFifoQueueMode;              /*!< Tx FIFO/Queue Mode selection.
+                                              This parameter can be a value of @ref FDCAN_txFifoQueue_Mode */
+
+  uint32_t TxElmtSize;                   /*!< Specifies the Data Field Size in a Tx Element.
+                                              This parameter can be a value of @ref FDCAN_data_field_size  */
+
+} FDCAN_InitTypeDef;
+
+/**
+  * @brief  FDCAN clock calibration unit structure definition
+  */
+typedef struct
+{
+  uint32_t ClockCalibration;     /*!< Enable or disable the clock calibration.
+                                      This parameter can be a value of @ref FDCAN_clock_calibration.       */
+
+  uint32_t ClockDivider;         /*!< Specifies the FDCAN kernel clock divider when the clock calibration
+                                      is bypassed.
+                                      This parameter can be a value of @ref FDCAN_clock_divider            */
+
+  uint32_t MinOscClkPeriods;     /*!< Configures the minimum number of periods in two CAN bit times. The
+                                      actual configured number of periods is MinOscClkPeriods x 32.
+                                      This parameter must be a number between 0x00 and 0xFF                */
+
+  uint32_t CalFieldLength;       /*!< Specifies the calibration field length.
+                                      This parameter can be a value of @ref FDCAN_calibration_field_length */
+
+  uint32_t TimeQuantaPerBitTime; /*!< Configures the number of time quanta per bit time.
+                                      This parameter must be a number between 4 and 25                     */
+
+  uint32_t WatchdogStartValue;   /*!< Start value of the Calibration Watchdog Counter.
+                                      If set to zero the counter is disabled.
+                                      This parameter must be a number between 0x0000 and 0xFFFF            */
+
+} FDCAN_ClkCalUnitTypeDef;
+
+/**
+  * @brief  FDCAN filter structure definition
+  */
+typedef struct
+{
+  uint32_t IdType;           /*!< Specifies the identifier type.
+                                  This parameter can be a value of @ref FDCAN_id_type       */
+
+  uint32_t FilterIndex;      /*!< Specifies the filter which will be initialized.
+                                  This parameter must be a number between:
+                                   - 0 and 127, if IdType is FDCAN_STANDARD_ID
+                                   - 0 and 63, if IdType is FDCAN_EXTENDED_ID               */
+
+  uint32_t FilterType;       /*!< Specifies the filter type.
+                                  This parameter can be a value of @ref FDCAN_filter_type.
+                                  The value FDCAN_EXT_FILTER_RANGE_NO_EIDM is permitted
+                                  only when IdType is FDCAN_EXTENDED_ID.
+                                  This parameter is ignored if FilterConfig is set to
+                                  FDCAN_FILTER_TO_RXBUFFER                                  */
+
+  uint32_t FilterConfig;     /*!< Specifies the filter configuration.
+                                  This parameter can be a value of @ref FDCAN_filter_config */
+
+  uint32_t FilterID1;        /*!< Specifies the filter identification 1.
+                                  This parameter must be a number between:
+                                   - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+                                   - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID       */
+
+  uint32_t FilterID2;        /*!< Specifies the filter identification 2.
+                                  This parameter is ignored if FilterConfig is set to
+                                  FDCAN_FILTER_TO_RXBUFFER.
+                                  This parameter must be a number between:
+                                   - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+                                   - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID       */
+
+  uint32_t RxBufferIndex;    /*!< Contains the index of the Rx buffer in which the
+                                  matching message will be stored.
+                                  This parameter must be a number between 0 and 63.
+                                  This parameter is ignored if FilterConfig is different
+                                  from FDCAN_FILTER_TO_RXBUFFER                             */
+
+  uint32_t IsCalibrationMsg; /*!< Specifies whether the filter is configured for
+                                  calibration messages.
+                                  This parameter is ignored if FilterConfig is different
+                                  from FDCAN_FILTER_TO_RXBUFFER.
+                                  This parameter can be:
+                                   - 0 : ordinary message
+                                   - 1 : calibration message                                */
+
+} FDCAN_FilterTypeDef;
+
+/**
+  * @brief  FDCAN Tx header structure definition
+  */
+typedef struct
+{
+  uint32_t Identifier;          /*!< Specifies the identifier.
+                                     This parameter must be a number between:
+                                      - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+                                      - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID               */
+
+  uint32_t IdType;              /*!< Specifies the identifier type for the message that will be
+                                     transmitted.
+                                     This parameter can be a value of @ref FDCAN_id_type               */
+
+  uint32_t TxFrameType;         /*!< Specifies the frame type of the message that will be transmitted.
+                                     This parameter can be a value of @ref FDCAN_frame_type            */
+
+  uint32_t DataLength;          /*!< Specifies the length of the frame that will be transmitted.
+                                      This parameter can be a value of @ref FDCAN_data_length_code     */
+
+  uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
+                                     This parameter can be a value of @ref FDCAN_error_state_indicator */
+
+  uint32_t BitRateSwitch;       /*!< Specifies whether the Tx frame will be transmitted with or without
+                                     bit rate switching.
+                                     This parameter can be a value of @ref FDCAN_bit_rate_switching    */
+
+  uint32_t FDFormat;            /*!< Specifies whether the Tx frame will be transmitted in classic or
+                                     FD format.
+                                     This parameter can be a value of @ref FDCAN_format                */
+
+  uint32_t TxEventFifoControl;  /*!< Specifies the event FIFO control.
+                                     This parameter can be a value of @ref FDCAN_EFC                   */
+
+  uint32_t MessageMarker;       /*!< Specifies the message marker to be copied into Tx Event FIFO
+                                     element for identification of Tx message status.
+                                     This parameter must be a number between 0 and 0xFF                */
+
+} FDCAN_TxHeaderTypeDef;
+
+/**
+  * @brief  FDCAN Rx header structure definition
+  */
+typedef struct
+{
+  uint32_t Identifier;            /*!< Specifies the identifier.
+                                       This parameter must be a number between:
+                                        - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+                                        - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID               */
+
+  uint32_t IdType;                /*!< Specifies the identifier type of the received message.
+                                       This parameter can be a value of @ref FDCAN_id_type               */
+
+  uint32_t RxFrameType;           /*!< Specifies the the received message frame type.
+                                       This parameter can be a value of @ref FDCAN_frame_type            */
+
+  uint32_t DataLength;            /*!< Specifies the received frame length.
+                                        This parameter can be a value of @ref FDCAN_data_length_code     */
+
+  uint32_t ErrorStateIndicator;   /*!< Specifies the error state indicator.
+                                       This parameter can be a value of @ref FDCAN_error_state_indicator */
+
+  uint32_t BitRateSwitch;         /*!< Specifies whether the Rx frame is received with or without bit
+                                       rate switching.
+                                       This parameter can be a value of @ref FDCAN_bit_rate_switching    */
+
+  uint32_t FDFormat;              /*!< Specifies whether the Rx frame is received in classic or FD
+                                       format.
+                                       This parameter can be a value of @ref FDCAN_format                */
+
+  uint32_t RxTimestamp;           /*!< Specifies the timestamp counter value captured on start of frame
+                                       reception.
+                                       This parameter must be a number between 0 and 0xFFFF              */
+
+  uint32_t FilterIndex;           /*!< Specifies the index of matching Rx acceptance filter element.
+                                       This parameter must be a number between:
+                                        - 0 and 127, if IdType is FDCAN_STANDARD_ID
+                                        - 0 and 63, if IdType is FDCAN_EXTENDED_ID                       */
+
+  uint32_t IsFilterMatchingFrame; /*!< Specifies whether the accepted frame did not match any Rx filter.
+                                         Acceptance of non-matching frames may be enabled via
+                                         HAL_FDCAN_ConfigGlobalFilter().
+                                         This parameter can be 0 or 1                                    */
+
+} FDCAN_RxHeaderTypeDef;
+
+/**
+  * @brief  FDCAN Tx event FIFO structure definition
+  */
+typedef struct
+{
+  uint32_t Identifier;          /*!< Specifies the identifier.
+                                     This parameter must be a number between:
+                                      - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+                                      - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID               */
+
+  uint32_t IdType;              /*!< Specifies the identifier type for the transmitted message.
+                                     This parameter can be a value of @ref FDCAN_id_type               */
+
+  uint32_t TxFrameType;         /*!< Specifies the frame type of the transmitted message.
+                                     This parameter can be a value of @ref FDCAN_frame_type            */
+
+  uint32_t DataLength;          /*!< Specifies the length of the transmitted frame.
+                                     This parameter can be a value of @ref FDCAN_data_length_code      */
+
+  uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
+                                     This parameter can be a value of @ref FDCAN_error_state_indicator */
+
+  uint32_t BitRateSwitch;       /*!< Specifies whether the Tx frame is transmitted with or without bit
+                                     rate switching.
+                                     This parameter can be a value of @ref FDCAN_bit_rate_switching    */
+
+  uint32_t FDFormat;            /*!< Specifies whether the Tx frame is transmitted in classic or FD
+                                     format.
+                                     This parameter can be a value of @ref FDCAN_format                */
+
+  uint32_t TxTimestamp;         /*!< Specifies the timestamp counter value captured on start of frame
+                                     transmission.
+                                     This parameter must be a number between 0 and 0xFFFF              */
+
+  uint32_t MessageMarker;       /*!< Specifies the message marker copied into Tx Event FIFO element
+                                     for identification of Tx message status.
+                                     This parameter must be a number between 0 and 0xFF                */
+
+  uint32_t EventType;           /*!< Specifies the event type.
+                                     This parameter can be a value of @ref FDCAN_event_type            */
+
+} FDCAN_TxEventFifoTypeDef;
+
+/**
+  * @brief  FDCAN High Priority Message Status structure definition
+  */
+typedef struct
+{
+  uint32_t FilterList;     /*!< Specifies the filter list of the matching filter element.
+                                This parameter can be:
+                                 - 0 : Standard Filter List
+                                 - 1 : Extended Filter List                                */
+
+  uint32_t FilterIndex;    /*!< Specifies the index of matching filter element.
+                                This parameter can be a number between:
+                                - 0 and 127, if FilterList is 0 (Standard)
+                                - 0 and 63, if FilterList is 1 (Extended)                  */
+
+  uint32_t MessageStorage; /*!< Specifies the HP Message Storage.
+                                This parameter can be a value of @ref FDCAN_hp_msg_storage */
+
+  uint32_t MessageIndex;   /*!< Specifies the Index of Rx FIFO element to which the
+                                message was stored.
+                                This parameter is valid only when MessageStorage is:
+                                  FDCAN_HP_STORAGE_RXFIFO0
+                                 or
+                                  FDCAN_HP_STORAGE_RXFIFO1                                 */
+
+} FDCAN_HpMsgStatusTypeDef;
+
+/**
+  * @brief FDCAN Protocol Status structure definition
+  */
+typedef struct
+{
+  uint32_t LastErrorCode;     /*!< Specifies the type of the last error that occurred on the FDCAN bus.
+                                   This parameter can be a value of @ref FDCAN_protocol_error_code                           */
+
+  uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase of a CAN FD format
+                                   frame with its BRS flag set.
+                                   This parameter can be a value of @ref FDCAN_protocol_error_code                           */
+
+  uint32_t Activity;          /*!< Specifies the FDCAN module communication state.
+                                   This parameter can be a value of @ref FDCAN_communication_state                           */
+
+  uint32_t ErrorPassive;      /*!< Specifies the FDCAN module error status.
+                                   This parameter can be:
+                                    - 0 : The FDCAN is in Error_Active state
+                                    - 1 : The FDCAN is in Error_Passive state                                                */
+
+  uint32_t Warning;           /*!< Specifies the FDCAN module warning status.
+                                   This parameter can be:
+                                    - 0 : error counters (RxErrorCnt and TxErrorCnt) are below the Error_Warning limit of 96
+                                    - 1 : at least one of error counters has reached the Error_Warning limit of 96           */
+
+  uint32_t BusOff;            /*!< Specifies the FDCAN module Bus_Off status.
+                                   This parameter can be:
+                                    - 0 : The FDCAN is not in Bus_Off state
+                                    - 1 : The FDCAN is in Bus_Off state                                                      */
+
+  uint32_t RxESIflag;         /*!< Specifies ESI flag of last received CAN FD message.
+                                   This parameter can be:
+                                    - 0 : Last received CAN FD message did not have its ESI flag set
+                                    - 1 : Last received CAN FD message had its ESI flag set                                  */
+
+  uint32_t RxBRSflag;         /*!< Specifies BRS flag of last received CAN FD message.
+                                   This parameter can be:
+                                    - 0 : Last received CAN FD message did not have its BRS flag set
+                                    - 1 : Last received CAN FD message had its BRS flag set                                  */
+
+  uint32_t RxFDFflag;         /*!< Specifies if CAN FD message (FDF flag set) has been received since last protocol status.
+                                   This parameter can be:
+                                    - 0 : no CAN FD message received
+                                    - 1 : CAN FD message received                                                            */
+
+  uint32_t ProtocolException; /*!< Specifies the FDCAN module Protocol Exception status.
+                                   This parameter can be:
+                                    - 0 : No protocol exception event occurred since last read access
+                                    - 1 : Protocol exception event occurred                                                  */
+
+  uint32_t TDCvalue;          /*!< Specifies the Transmitter Delay Compensation Value.
+                                   This parameter can be a number between 0 and 127                                          */
+
+} FDCAN_ProtocolStatusTypeDef;
+
+/**
+  * @brief FDCAN Error Counters structure definition
+  */
+typedef struct
+{
+  uint32_t TxErrorCnt;     /*!< Specifies the Transmit Error Counter Value.
+                                This parameter can be a number between 0 and 255                                         */
+
+  uint32_t RxErrorCnt;     /*!< Specifies the Receive Error Counter Value.
+                                This parameter can be a number between 0 and 127                                         */
+
+  uint32_t RxErrorPassive; /*!< Specifies the Receive Error Passive status.
+                                This parameter can be:
+                                 - 0 : The Receive Error Counter (RxErrorCnt) is below the error passive level of 128
+                                 - 1 : The Receive Error Counter (RxErrorCnt) has reached the error passive level of 128 */
+
+  uint32_t ErrorLogging;   /*!< Specifies the Transmit/Receive error logging counter value.
+                                This parameter can be a number between 0 and 255.
+                                This counter is incremented each time when a FDCAN protocol error causes the TxErrorCnt
+                                or the RxErrorCnt to be incremented. The counter stops at 255; the next increment of
+                                TxErrorCnt or RxErrorCnt sets interrupt flag FDCAN_FLAG_ERROR_LOGGING_OVERFLOW           */
+
+} FDCAN_ErrorCountersTypeDef;
+
+/**
+  * @brief FDCAN TT Init structure definition
+  */
+typedef struct
+{
+  uint32_t OperationMode;     /*!< Specifies the FDCAN Operation Mode.
+                                   This parameter can be a value of @ref FDCAN_operation_mode               */
+
+  uint32_t GapEnable;         /*!< Specifies the FDCAN TT Operation.
+                                   This parameter can be a value of @ref FDCAN_TT_operation.
+                                   This parameter is ignored if OperationMode is set to
+                                   FDCAN_TT_COMMUNICATION_LEVEL0                                            */
+
+  uint32_t TimeMaster;        /*!< Specifies whether the instance is a slave or a potential master.
+                                   This parameter can be a value of @ref FDCAN_TT_time_master               */
+
+  uint32_t SyncDevLimit;      /*!< Specifies the Synchronization Deviation Limit SDL of the TUR
+                                   numerator : TUR = (Numerator � SDL) / Denominator.
+                                   With : SDL = 2^(SyncDevLimit+5).
+                                   This parameter must be a number between 0 and 7                          */
+
+  uint32_t InitRefTrigOffset; /*!< Specifies the Initial Reference Trigger Offset.
+                                   This parameter must be a number between 0 and 127                        */
+
+  uint32_t ExternalClkSync;   /*!< Enable or disable External Clock Synchronization.
+                                   This parameter can be a value of @ref FDCAN_TT_external_clk_sync.
+                                   This parameter is ignored if OperationMode is set to
+                                   FDCAN_TT_COMMUNICATION_LEVEL1                                            */
+
+  uint32_t AppWdgLimit;       /*!< Specifies the Application Watchdog Limit : maximum time after
+                                   which the application has to serve the application watchdog.
+                                   The application watchdog is incremented once each 256 NTUs.
+                                   The application watchdog can be disabled by setting AppWdgLimit to 0.
+                                   This parameter must be a number between 0 and 255.
+                                   This parameter is ignored if OperationMode is set to
+                                   FDCAN_TT_COMMUNICATION_LEVEL0                                            */
+
+  uint32_t GlobalTimeFilter;  /*!< Enable or disable Global Time Filtering.
+                                   This parameter can be a value of @ref FDCAN_TT_global_time_filtering.
+                                   This parameter is ignored if OperationMode is set to
+                                   FDCAN_TT_COMMUNICATION_LEVEL1                                            */
+
+  uint32_t ClockCalibration;  /*!< Enable or disable Automatic Clock Calibration.
+                                   This parameter can be a value of @ref FDCAN_TT_auto_clk_calibration.
+                                   This parameter is ignored if OperationMode is set to
+                                   FDCAN_TT_COMMUNICATION_LEVEL1                                            */
+
+  uint32_t EvtTrigPolarity;   /*!< Specifies the Event Trigger Polarity.
+                                   This parameter can be a value of @ref FDCAN_TT_event_trig_polarity.
+                                   This parameter is ignored if OperationMode is set to
+                                   FDCAN_TT_COMMUNICATION_LEVEL0                                            */
+
+  uint32_t BasicCyclesNbr;    /*!< Specifies the nubmer of basic cycles in the system matrix.
+                                   This parameter can be a value of @ref FDCAN_TT_basic_cycle_number        */
+
+  uint32_t CycleStartSync;    /*!< Enable or disable synchronization pulse output at pin fdcan1_soc.
+                                   This parameter can be a value of @ref FDCAN_TT_cycle_start_sync          */
+
+  uint32_t TxEnableWindow;    /*!< Specifies the length of Tx enable window in NTUs.
+                                   This parameter must be a number between 1 and 16                         */
+
+  uint32_t ExpTxTrigNbr;      /*!< Specifies the number of expected Tx_Triggers in the system matrix.
+                                   This is the sum of Tx_Triggers for exclusive, single arbitrating and
+                                   merged arbitrating windows.
+                                   This parameter must be a number between 0 and 4095                       */
+
+  uint32_t TURNumerator;      /*!< Specifies the TUR (Time Unit Ratio) numerator.
+                                   It is adviced to set this parameter to the largest applicable value.
+                                   This parameter must be a number between 0x10000 and 0x1FFFF              */
+
+  uint32_t TURDenominator;    /*!< Specifies the TUR (Time Unit Ratio) denominator.
+                                   This parameter must be a number between 0x0001 and 0x3FFF                */
+
+  uint32_t TriggerMemoryNbr;  /*!< Specifies the number of trigger memory elements.
+                                   This parameter must be a number between 0 and 64                         */
+
+  uint32_t StopWatchTrigSel;  /*!< Specifies the input to be used as stop watch trigger.
+                                   This parameter can be a value of @ref FDCAN_TT_stop_watch_trig_selection */
+
+  uint32_t EventTrigSel;      /*!< Specifies the input to be used as event trigger.
+                                   This parameter can be a value of @ref FDCAN_TT_event_trig_selection      */
+
+} FDCAN_TT_ConfigTypeDef;
+
+/**
+  * @brief  FDCAN Trigger structure definition
+  */
+typedef struct
+{
+  uint32_t TriggerIndex;  /*!< Specifies the trigger which will be configured.
+                               This parameter must be a number between 0 and 63                                 */
+
+  uint32_t TimeMark;      /*!< Specifies the cycle time for which the trigger becomes active.
+                               This parameter must be a number between 0 and 0xFFFF                             */
+
+  uint32_t RepeatFactor;  /*!< Specifies the trigger repeat factor.
+                               This parameter can be a value of @ref FDCAN_TT_Repeat_Factor                     */
+
+  uint32_t StartCycle;    /*!< Specifies the index of the first cycle in which the trigger becomes active.
+                               This parameter is ignored if RepeatFactor is set to FDCAN_TT_REPEAT_EVERY_CYCLE.
+                               This parameter must be a number between 0 and RepeatFactor                       */
+
+  uint32_t TmEventInt;    /*!< Enable or disable the internal time mark event.
+                               If enabled, FDCAN_TT_FLAG_TRIG_TIME_MARK flag is set when trigger memory element
+                               becomes active.
+                               This parameter can be a value of @ref FDCAN_TT_Time_Mark_Event_Internal          */
+
+  uint32_t TmEventExt;    /*!< Enable or disable the external time mark event.
+                               If enabled, and if TTOCN.TTIE is set, a pulse is generated at fdcan1_tmp when
+                               trigger memory element becomes active.
+                               This parameter can be a value of @ref FDCAN_TT_Time_Mark_Event_External          */
+
+  uint32_t TriggerType;   /*!< Specifies the trigger type.
+                               This parameter can be a value of @ref FDCAN_TT_Trigger_Type                      */
+
+  uint32_t FilterType;    /*!< Specifies the filter identifier type.
+                               This parameter can be a value of @ref FDCAN_id_type                              */
+
+  uint32_t TxBufferIndex; /*!< Specifies the index of the Tx buffer for which the trigger is valid.
+                               This parameter can be a value of @ref FDCAN_Tx_location.
+                               This parameter is taken in consideration only if the trigger is configured for
+                               transmission.                                                                    */
+
+  uint32_t FilterIndex;   /*!< Specifies the filter for which the trigger is valid.
+                               This parameter is taken in consideration only if the trigger is configured for
+                               reception.
+                               This parameter must be a number between:
+                                - 0 and 127, if FilterType is FDCAN_STANDARD_ID
+                                - 0 and 63, if FilterType is FDCAN_EXTENDED_ID                                  */
+
+} FDCAN_TriggerTypeDef;
+
+/**
+  * @brief  FDCAN TT Operation Status structure definition
+  */
+typedef struct
+{
+  uint32_t ErrorLevel;       /*!< Specifies the type of the TT operation error level.
+                                  This parameter can be a value of @ref FDCAN_TT_error_level                    */
+
+  uint32_t MasterState;      /*!< Specifies the type of the TT master state.
+                                  This parameter can be a value of @ref FDCAN_TT_master_state                   */
+
+  uint32_t SyncState;        /*!< Specifies the type of the TT synchronization state.
+                                  This parameter can be a value of @ref FDCAN_TT_sync_state                     */
+
+  uint32_t GTimeQuality;     /*!< Specifies the Quality of Global Time Phase.
+                                  This parameter is only relevant in Level 0 and Level 2, otherwise fixed to 0.
+                                  This parameter can be:
+                                   - 0 : Global time not valid
+                                   - 1 : Global time in phase with Time Master                                  */
+
+  uint32_t ClockQuality;     /*!< Specifies the Quality of Clock Speed.
+                                  This parameter is only relevant in Level 0 and Level 2, otherwise fixed to 1.
+                                  This parameter can be:
+                                   - 0 : Local clock speed not synchronized to Time Master clock speed
+                                   - 1 : Synchronization Deviation = SDL                                        */
+
+  uint32_t RefTrigOffset;    /*!< Specifies the Actual Reference Trigger Offset Value.
+                                  This parameter can be a number between 0 and 0xFF                             */
+
+  uint32_t GTimeDiscPending; /*!< Specifies the Global Time Discontinuity State.
+                                  This parameter can be:
+                                   - 0 : No global time preset pending
+                                   - 1 : Node waits for the global time preset to take effect                   */
+
+  uint32_t GapFinished;      /*!< Specifies whether a Gap is finished.
+                                  This parameter can be:
+                                   - 0 : Reset at the end of each reference message
+                                   - 1 : Gap finished                                                           */
+
+  uint32_t MasterPriority;   /*!< Specifies the Priority of actual Time Master.
+                                  This parameter can be a number between 0 and 0x7                              */
+
+  uint32_t GapStarted;       /*!< Specifies whether a Gap is started.
+                                  This parameter can be:
+                                   - 0 : No Gap in schedule
+                                   - 1 : Gap time after Basic Cycle has started                                 */
+
+  uint32_t WaitForEvt;       /*!< Specifies whether a Gap is annouced.
+                                  This parameter can be:
+                                   - 0 : No Gap announced, reset by a reference message with Next_is_Gap = 0
+                                   - 1 : Reference message with Next_is_Gap = 1 received                        */
+
+  uint32_t AppWdgEvt;        /*!< Specifies the Application Watchdog State.
+                                  This parameter can be:
+                                   - 0 : Application Watchdog served in time
+                                   - 1 : Failed to serve Application Watchdog in time                           */
+
+  uint32_t ECSPending;       /*!< Specifies the External Clock Synchronization State.
+                                  This parameter can be:
+                                   - 0 : No external clock synchronization pending
+                                   - 1 : Node waits for external clock synchronization to take effect           */
+
+  uint32_t PhaseLock;        /*!< Specifies the Phase Lock State.
+                                  This parameter can be:
+                                   - 0 : Phase outside range
+                                   - 1 : Phase inside range                                                     */
+
+} FDCAN_TTOperationStatusTypeDef;
+
+/**
+  * @brief  FDCAN Message RAM blocks
+  */
+typedef struct
+{
+  uint32_t StandardFilterSA; /*!< Specifies the Standard Filter List Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t ExtendedFilterSA; /*!< Specifies the Extended Filter List Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t RxFIFO0SA;        /*!< Specifies the Rx FIFO 0 Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t RxFIFO1SA;        /*!< Specifies the Rx FIFO 1 Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t RxBufferSA;       /*!< Specifies the Rx Buffer Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t TxEventFIFOSA;    /*!< Specifies the Tx Event FIFO Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t TxBufferSA;       /*!< Specifies the Tx Buffers Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t TxFIFOQSA;        /*!< Specifies the Tx FIFO/Queue Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t TTMemorySA;       /*!< Specifies the Trigger Memory Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t EndAddress;       /*!< Specifies the End Address of the allocated RAM.
+                                  This parameter must be a 32-bit word address      */
+
+} FDCAN_MsgRamAddressTypeDef;
+
+/**
+  * @brief  FDCAN handle structure definition
+  */
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+typedef struct __FDCAN_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+{
+  FDCAN_GlobalTypeDef         *Instance;        /*!< Register base address     */
+
+  TTCAN_TypeDef               *ttcan;           /*!< TT register base address  */
+
+  FDCAN_InitTypeDef           Init;             /*!< FDCAN required parameters */
+
+  FDCAN_MsgRamAddressTypeDef  msgRam;           /*!< FDCAN Message RAM blocks  */
+
+  uint32_t                    LatestTxFifoQRequest; /*!< FDCAN Tx buffer index
+                                               of latest Tx FIFO/Queue request */
+
+  __IO HAL_FDCAN_StateTypeDef State;            /*!< FDCAN communication state */
+
+  HAL_LockTypeDef             Lock;             /*!< FDCAN locking object      */
+
+  __IO uint32_t               ErrorCode;        /*!< FDCAN Error code          */
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+  void (* ClockCalibrationCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs);         /*!< FDCAN Clock Calibration callback          */
+  void (* TxEventFifoCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs);                 /*!< FDCAN Tx Event Fifo callback              */
+  void (* RxFifo0Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs);                         /*!< FDCAN Rx Fifo 0 callback                  */
+  void (* RxFifo1Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs);                         /*!< FDCAN Rx Fifo 1 callback                  */
+  void (* TxFifoEmptyCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                          /*!< FDCAN Tx Fifo Empty callback              */
+  void (* TxBufferCompleteCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);             /*!< FDCAN Tx Buffer complete callback         */
+  void (* TxBufferAbortCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);                /*!< FDCAN Tx Buffer abort callback            */
+  void (* RxBufferNewMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                   /*!< FDCAN Rx Buffer New Message callback      */
+  void (* HighPriorityMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                  /*!< FDCAN High priority message callback      */
+  void (* TimestampWraparoundCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                  /*!< FDCAN Timestamp wraparound callback       */
+  void (* TimeoutOccurredCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                      /*!< FDCAN Timeout occurred callback           */
+  void (* ErrorCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                                /*!< FDCAN Error callback                      */
+  void (* ErrorStatusCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs);                 /*!< FDCAN Error status callback               */
+  void (* TT_ScheduleSyncCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs);             /*!< FDCAN T Schedule Synchronization callback */
+  void (* TT_TimeMarkCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs);                  /*!< FDCAN TT Time Mark callback               */
+  void (* TT_StopWatchCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount); /*!< FDCAN TT Stop Watch callback              */
+  void (* TT_GlobalTimeCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs);                /*!< FDCAN TT Global Time callback             */
+
+  void (* MspInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                              /*!< FDCAN Msp Init callback                   */
+  void (* MspDeInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                            /*!< FDCAN Msp DeInit callback                 */
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+} FDCAN_HandleTypeDef;
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+/**
+  * @brief  HAL FDCAN common Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_FDCAN_TX_FIFO_EMPTY_CB_ID        = 0x00U, /*!< FDCAN Tx Fifo Empty callback ID         */
+  HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID    = 0x01U, /*!< FDCAN Rx buffer new message callback ID */
+  HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID    = 0x02U, /*!< FDCAN High priority message callback ID */
+  HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID = 0x03U, /*!< FDCAN Timestamp wraparound callback ID  */
+  HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID     = 0x04U, /*!< FDCAN Timeout occurred callback ID      */
+  HAL_FDCAN_ERROR_CALLBACK_CB_ID       = 0x05U, /*!< FDCAN Error callback ID                 */
+
+  HAL_FDCAN_MSPINIT_CB_ID              = 0x06U, /*!< FDCAN MspInit callback ID               */
+  HAL_FDCAN_MSPDEINIT_CB_ID            = 0x07U, /*!< FDCAN MspDeInit callback ID             */
+
+} HAL_FDCAN_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL FDCAN Callback pointer definition
+  */
+typedef  void (*pFDCAN_CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan);                                                     /*!< pointer to a common FDCAN callback function                    */
+typedef  void (*pFDCAN_ClockCalibrationCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs);         /*!< pointer to Clock Calibration FDCAN callback function           */
+typedef  void (*pFDCAN_TxEventFifoCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs);                 /*!< pointer to Tx event Fifo FDCAN callback function               */
+typedef  void (*pFDCAN_RxFifo0CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs);                         /*!< pointer to Rx Fifo 0 FDCAN callback function                   */
+typedef  void (*pFDCAN_RxFifo1CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs);                         /*!< pointer to Rx Fifo 1 FDCAN callback function                   */
+typedef  void (*pFDCAN_TxBufferCompleteCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);             /*!< pointer to Tx Buffer complete FDCAN callback function          */
+typedef  void (*pFDCAN_TxBufferAbortCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);                /*!< pointer to Tx Buffer abort FDCAN callback function             */
+typedef  void (*pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs);                 /*!< pointer to Error Status callback function                      */
+typedef  void (*pFDCAN_TT_ScheduleSyncCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs);             /*!< pointer to TT Schedule Synchronization FDCAN callback function */
+typedef  void (*pFDCAN_TT_TimeMarkCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs);                  /*!< pointer to TT Time Mark FDCAN callback function                */
+typedef  void (*pFDCAN_TT_StopWatchCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount); /*!< pointer to TT Stop Watch FDCAN callback function               */
+typedef  void (*pFDCAN_TT_GlobalTimeCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs);                /*!< pointer to TT Global Time FDCAN callback function              */
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FDCAN_Exported_Constants FDCAN Exported Constants
+  * @{
+  */
+
+/** @defgroup HAL_FDCAN_Error_Code HAL FDCAN Error Code
+  * @{
+  */
+#define HAL_FDCAN_ERROR_NONE            ((uint32_t)0x00000000U) /*!< No error                                                               */
+#define HAL_FDCAN_ERROR_TIMEOUT         ((uint32_t)0x00000001U) /*!< Timeout error                                                          */
+#define HAL_FDCAN_ERROR_NOT_INITIALIZED ((uint32_t)0x00000002U) /*!< Peripheral not initialized                                             */
+#define HAL_FDCAN_ERROR_NOT_READY       ((uint32_t)0x00000004U) /*!< Peripheral not ready                                                   */
+#define HAL_FDCAN_ERROR_NOT_STARTED     ((uint32_t)0x00000008U) /*!< Peripheral not started                                                 */
+#define HAL_FDCAN_ERROR_NOT_SUPPORTED   ((uint32_t)0x00000010U) /*!< Mode not supported                                                     */
+#define HAL_FDCAN_ERROR_PARAM           ((uint32_t)0x00000020U) /*!< Parameter error                                                        */
+#define HAL_FDCAN_ERROR_PENDING         ((uint32_t)0x00000040U) /*!< Pending operation                                                      */
+#define HAL_FDCAN_ERROR_RAM_ACCESS      ((uint32_t)0x00000080U) /*!< Message RAM Access Failure                                             */
+#define HAL_FDCAN_ERROR_FIFO_EMPTY      ((uint32_t)0x00000100U) /*!< Put element in full FIFO                                               */
+#define HAL_FDCAN_ERROR_FIFO_FULL       ((uint32_t)0x00000200U) /*!< Get element from empty FIFO                                            */
+#define HAL_FDCAN_ERROR_LOG_OVERFLOW    FDCAN_IR_ELO            /*!< Overflow of CAN Error Logging Counter                                  */
+#define HAL_FDCAN_ERROR_RAM_WDG         FDCAN_IR_WDI            /*!< Message RAM Watchdog event occurred                                    */
+#define HAL_FDCAN_ERROR_PROTOCOL_ARBT   FDCAN_IR_PEA            /*!< Protocol Error in Arbitration Phase (Nominal Bit Time is used)         */
+#define HAL_FDCAN_ERROR_PROTOCOL_DATA   FDCAN_IR_PED            /*!< Protocol Error in Data Phase (Data Bit Time is used)                   */
+#define HAL_FDCAN_ERROR_RESERVED_AREA   FDCAN_IR_ARA            /*!< Access to Reserved Address                                             */
+#define HAL_FDCAN_ERROR_TT_GLOBAL_TIME  FDCAN_TTIR_GTE          /*!< Global Time Error : Synchronization deviation exceeded limit           */
+#define HAL_FDCAN_ERROR_TT_TX_UNDERFLOW FDCAN_TTIR_TXU          /*!< Tx Count Underflow : Less Tx trigger than expected in one matrix cycle */
+#define HAL_FDCAN_ERROR_TT_TX_OVERFLOW  FDCAN_TTIR_TXO          /*!< Tx Count Overflow : More Tx trigger than expected in one matrix cycle  */
+#define HAL_FDCAN_ERROR_TT_SCHEDULE1    FDCAN_TTIR_SE1          /*!< Scheduling error 1                                                     */
+#define HAL_FDCAN_ERROR_TT_SCHEDULE2    FDCAN_TTIR_SE2          /*!< Scheduling error 2                                                     */
+#define HAL_FDCAN_ERROR_TT_NO_INIT_REF  FDCAN_TTIR_IWT          /*!< No system startup due to missing reference message                     */
+#define HAL_FDCAN_ERROR_TT_NO_REF       FDCAN_TTIR_WT           /*!< Missing reference message                                              */
+#define HAL_FDCAN_ERROR_TT_APPL_WDG     FDCAN_TTIR_AW           /*!< Application watchdog not served in time                                */
+#define HAL_FDCAN_ERROR_TT_CONFIG       FDCAN_TTIR_CER          /*!< Error found in trigger list                                            */
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+#define HAL_FDCAN_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100U) /*!< Invalid Callback error                                                */
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_frame_format FDCAN Frame Format
+  * @{
+  */
+#define FDCAN_FRAME_CLASSIC   ((uint32_t)0x00000000U)                         /*!< Classic mode                      */
+#define FDCAN_FRAME_FD_NO_BRS ((uint32_t)FDCAN_CCCR_FDOE)                     /*!< FD mode without BitRate Switching */
+#define FDCAN_FRAME_FD_BRS    ((uint32_t)(FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE)) /*!< FD mode with BitRate Switching    */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_operating_mode FDCAN Operating Mode
+  * @{
+  */
+#define FDCAN_MODE_NORMAL               ((uint32_t)0x00000000U) /*!< Normal mode               */
+#define FDCAN_MODE_RESTRICTED_OPERATION ((uint32_t)0x00000001U) /*!< Restricted Operation mode */
+#define FDCAN_MODE_BUS_MONITORING       ((uint32_t)0x00000002U) /*!< Bus Monitoring mode       */
+#define FDCAN_MODE_INTERNAL_LOOPBACK    ((uint32_t)0x00000003U) /*!< Internal LoopBack mode    */
+#define FDCAN_MODE_EXTERNAL_LOOPBACK    ((uint32_t)0x00000004U) /*!< External LoopBack mode    */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_clock_calibration FDCAN Clock Calibration
+  * @{
+  */
+#define FDCAN_CLOCK_CALIBRATION_DISABLE ((uint32_t)0x00000000U) /*!< Disable Clock Calibration */
+#define FDCAN_CLOCK_CALIBRATION_ENABLE  ((uint32_t)0x00000001U) /*!< Enable Clock Calibration  */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_clock_divider FDCAN Clock Divider
+  * @{
+  */
+#define FDCAN_CLOCK_DIV1  ((uint32_t)0x00000000U) /*!< Divide kernel clock by 1  */
+#define FDCAN_CLOCK_DIV2  ((uint32_t)0x00010000U) /*!< Divide kernel clock by 2  */
+#define FDCAN_CLOCK_DIV4  ((uint32_t)0x00020000U) /*!< Divide kernel clock by 4  */
+#define FDCAN_CLOCK_DIV6  ((uint32_t)0x00030000U) /*!< Divide kernel clock by 6  */
+#define FDCAN_CLOCK_DIV8  ((uint32_t)0x00040000U) /*!< Divide kernel clock by 8  */
+#define FDCAN_CLOCK_DIV10 ((uint32_t)0x00050000U) /*!< Divide kernel clock by 10 */
+#define FDCAN_CLOCK_DIV12 ((uint32_t)0x00060000U) /*!< Divide kernel clock by 12 */
+#define FDCAN_CLOCK_DIV14 ((uint32_t)0x00070000U) /*!< Divide kernel clock by 14 */
+#define FDCAN_CLOCK_DIV16 ((uint32_t)0x00080000U) /*!< Divide kernel clock by 16 */
+#define FDCAN_CLOCK_DIV18 ((uint32_t)0x00090000U) /*!< Divide kernel clock by 18 */
+#define FDCAN_CLOCK_DIV20 ((uint32_t)0x000A0000U) /*!< Divide kernel clock by 20 */
+#define FDCAN_CLOCK_DIV22 ((uint32_t)0x000B0000U) /*!< Divide kernel clock by 22 */
+#define FDCAN_CLOCK_DIV24 ((uint32_t)0x000C0000U) /*!< Divide kernel clock by 24 */
+#define FDCAN_CLOCK_DIV26 ((uint32_t)0x000D0000U) /*!< Divide kernel clock by 26 */
+#define FDCAN_CLOCK_DIV28 ((uint32_t)0x000E0000U) /*!< Divide kernel clock by 28 */
+#define FDCAN_CLOCK_DIV30 ((uint32_t)0x000F0000U) /*!< Divide kernel clock by 30 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_calibration_field_length FDCAN Calibration Field Length
+  * @{
+  */
+#define FDCAN_CALIB_FIELD_LENGTH_32 ((uint32_t)0x00000000U)       /*!< Calibration field length is 32 bits */
+#define FDCAN_CALIB_FIELD_LENGTH_64 ((uint32_t)FDCANCCU_CCFG_CFL) /*!< Calibration field length is 64 bits */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_calibration_state FDCAN Calibration State
+  * @{
+  */
+#define FDCAN_CLOCK_NOT_CALIBRATED       ((uint32_t)0x00000000U) /*!< Clock not calibrated       */
+#define FDCAN_CLOCK_BASIC_CALIBRATED     ((uint32_t)0x40000000U) /*!< Clock basic calibrated     */
+#define FDCAN_CLOCK_PRECISION_CALIBRATED ((uint32_t)0x80000000U) /*!< Clock precision calibrated */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_calibration_counter FDCAN Calibration Counter
+  * @{
+  */
+#define FDCAN_CALIB_TIME_QUANTA_COUNTER  ((uint32_t)0x00000000U) /*!< Time Quanta Counter             */
+#define FDCAN_CALIB_CLOCK_PERIOD_COUNTER ((uint32_t)0x00000001U) /*!< Oscillator Clock Period Counter */
+#define FDCAN_CALIB_WATCHDOG_COUNTER     ((uint32_t)0x00000002U) /*!< Calibration Watchdog Counter    */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_data_field_size FDCAN Data Field Size
+  * @{
+  */
+#define FDCAN_DATA_BYTES_8  ((uint32_t)0x00000004U) /*!< 8 bytes data field  */
+#define FDCAN_DATA_BYTES_12 ((uint32_t)0x00000005U) /*!< 12 bytes data field */
+#define FDCAN_DATA_BYTES_16 ((uint32_t)0x00000006U) /*!< 16 bytes data field */
+#define FDCAN_DATA_BYTES_20 ((uint32_t)0x00000007U) /*!< 20 bytes data field */
+#define FDCAN_DATA_BYTES_24 ((uint32_t)0x00000008U) /*!< 24 bytes data field */
+#define FDCAN_DATA_BYTES_32 ((uint32_t)0x0000000AU) /*!< 32 bytes data field */
+#define FDCAN_DATA_BYTES_48 ((uint32_t)0x0000000EU) /*!< 48 bytes data field */
+#define FDCAN_DATA_BYTES_64 ((uint32_t)0x00000012U) /*!< 64 bytes data field */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_txFifoQueue_Mode FDCAN Tx FIFO/Queue Mode
+  * @{
+  */
+#define FDCAN_TX_FIFO_OPERATION  ((uint32_t)0x00000000U)     /*!< FIFO mode  */
+#define FDCAN_TX_QUEUE_OPERATION ((uint32_t)FDCAN_TXBC_TFQM) /*!< Queue mode */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_id_type FDCAN ID Type
+  * @{
+  */
+#define FDCAN_STANDARD_ID ((uint32_t)0x00000000U) /*!< Standard ID element */
+#define FDCAN_EXTENDED_ID ((uint32_t)0x40000000U) /*!< Extended ID element */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_frame_type FDCAN Frame Type
+  * @{
+  */
+#define FDCAN_DATA_FRAME   ((uint32_t)0x00000000U)  /*!< Data frame   */
+#define FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U)  /*!< Remote frame */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_data_length_code FDCAN Data Length Code
+  * @{
+  */
+#define FDCAN_DLC_BYTES_0  ((uint32_t)0x00000000U) /*!< 0 bytes data field  */
+#define FDCAN_DLC_BYTES_1  ((uint32_t)0x00010000U) /*!< 1 bytes data field  */
+#define FDCAN_DLC_BYTES_2  ((uint32_t)0x00020000U) /*!< 2 bytes data field  */
+#define FDCAN_DLC_BYTES_3  ((uint32_t)0x00030000U) /*!< 3 bytes data field  */
+#define FDCAN_DLC_BYTES_4  ((uint32_t)0x00040000U) /*!< 4 bytes data field  */
+#define FDCAN_DLC_BYTES_5  ((uint32_t)0x00050000U) /*!< 5 bytes data field  */
+#define FDCAN_DLC_BYTES_6  ((uint32_t)0x00060000U) /*!< 6 bytes data field  */
+#define FDCAN_DLC_BYTES_7  ((uint32_t)0x00070000U) /*!< 7 bytes data field  */
+#define FDCAN_DLC_BYTES_8  ((uint32_t)0x00080000U) /*!< 8 bytes data field  */
+#define FDCAN_DLC_BYTES_12 ((uint32_t)0x00090000U) /*!< 12 bytes data field */
+#define FDCAN_DLC_BYTES_16 ((uint32_t)0x000A0000U) /*!< 16 bytes data field */
+#define FDCAN_DLC_BYTES_20 ((uint32_t)0x000B0000U) /*!< 20 bytes data field */
+#define FDCAN_DLC_BYTES_24 ((uint32_t)0x000C0000U) /*!< 24 bytes data field */
+#define FDCAN_DLC_BYTES_32 ((uint32_t)0x000D0000U) /*!< 32 bytes data field */
+#define FDCAN_DLC_BYTES_48 ((uint32_t)0x000E0000U) /*!< 48 bytes data field */
+#define FDCAN_DLC_BYTES_64 ((uint32_t)0x000F0000U) /*!< 64 bytes data field */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_error_state_indicator FDCAN Error State Indicator
+  * @{
+  */
+#define FDCAN_ESI_ACTIVE  ((uint32_t)0x00000000U) /*!< Transmitting node is error active  */
+#define FDCAN_ESI_PASSIVE ((uint32_t)0x80000000U) /*!< Transmitting node is error passive */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_bit_rate_switching FDCAN Bit Rate Switching
+  * @{
+  */
+#define FDCAN_BRS_OFF ((uint32_t)0x00000000U) /*!< FDCAN frames transmitted/received without bit rate switching */
+#define FDCAN_BRS_ON  ((uint32_t)0x00100000U) /*!< FDCAN frames transmitted/received with bit rate switching    */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_format FDCAN format
+  * @{
+  */
+#define FDCAN_CLASSIC_CAN ((uint32_t)0x00000000U) /*!< Frame transmitted/received in Classic CAN format */
+#define FDCAN_FD_CAN      ((uint32_t)0x00200000U) /*!< Frame transmitted/received in FDCAN format       */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_EFC FDCAN Event FIFO control
+  * @{
+  */
+#define FDCAN_NO_TX_EVENTS    ((uint32_t)0x00000000U) /*!< Do not store Tx events */
+#define FDCAN_STORE_TX_EVENTS ((uint32_t)0x00800000U) /*!< Store Tx events        */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_filter_type FDCAN Filter Type
+  * @{
+  */
+#define FDCAN_FILTER_RANGE         ((uint32_t)0x00000000U) /*!< Range filter from FilterID1 to FilterID2                        */
+#define FDCAN_FILTER_DUAL          ((uint32_t)0x00000001U) /*!< Dual ID filter for FilterID1 or FilterID2                       */
+#define FDCAN_FILTER_MASK          ((uint32_t)0x00000002U) /*!< Classic filter: FilterID1 = filter, FilterID2 = mask            */
+#define FDCAN_FILTER_RANGE_NO_EIDM ((uint32_t)0x00000003U) /*!< Range filter from FilterID1 to FilterID2, EIDM mask not applied */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_filter_config FDCAN Filter Configuration
+  * @{
+  */
+#define FDCAN_FILTER_DISABLE       ((uint32_t)0x00000000U) /*!< Disable filter element                                    */
+#define FDCAN_FILTER_TO_RXFIFO0    ((uint32_t)0x00000001U) /*!< Store in Rx FIFO 0 if filter matches                      */
+#define FDCAN_FILTER_TO_RXFIFO1    ((uint32_t)0x00000002U) /*!< Store in Rx FIFO 1 if filter matches                      */
+#define FDCAN_FILTER_REJECT        ((uint32_t)0x00000003U) /*!< Reject ID if filter matches                               */
+#define FDCAN_FILTER_HP            ((uint32_t)0x00000004U) /*!< Set high priority if filter matches                       */
+#define FDCAN_FILTER_TO_RXFIFO0_HP ((uint32_t)0x00000005U) /*!< Set high priority and store in FIFO 0 if filter matches   */
+#define FDCAN_FILTER_TO_RXFIFO1_HP ((uint32_t)0x00000006U) /*!< Set high priority and store in FIFO 1 if filter matches   */
+#define FDCAN_FILTER_TO_RXBUFFER   ((uint32_t)0x00000007U) /*!< Store into Rx Buffer, configuration of FilterType ignored */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Tx_location FDCAN Tx Location
+  * @{
+  */
+#define FDCAN_TX_BUFFER0  ((uint32_t)0x00000001U) /*!< Add message to Tx Buffer 0  */
+#define FDCAN_TX_BUFFER1  ((uint32_t)0x00000002U) /*!< Add message to Tx Buffer 1  */
+#define FDCAN_TX_BUFFER2  ((uint32_t)0x00000004U) /*!< Add message to Tx Buffer 2  */
+#define FDCAN_TX_BUFFER3  ((uint32_t)0x00000008U) /*!< Add message to Tx Buffer 3  */
+#define FDCAN_TX_BUFFER4  ((uint32_t)0x00000010U) /*!< Add message to Tx Buffer 4  */
+#define FDCAN_TX_BUFFER5  ((uint32_t)0x00000020U) /*!< Add message to Tx Buffer 5  */
+#define FDCAN_TX_BUFFER6  ((uint32_t)0x00000040U) /*!< Add message to Tx Buffer 6  */
+#define FDCAN_TX_BUFFER7  ((uint32_t)0x00000080U) /*!< Add message to Tx Buffer 7  */
+#define FDCAN_TX_BUFFER8  ((uint32_t)0x00000100U) /*!< Add message to Tx Buffer 8  */
+#define FDCAN_TX_BUFFER9  ((uint32_t)0x00000200U) /*!< Add message to Tx Buffer 9  */
+#define FDCAN_TX_BUFFER10 ((uint32_t)0x00000400U) /*!< Add message to Tx Buffer 10 */
+#define FDCAN_TX_BUFFER11 ((uint32_t)0x00000800U) /*!< Add message to Tx Buffer 11 */
+#define FDCAN_TX_BUFFER12 ((uint32_t)0x00001000U) /*!< Add message to Tx Buffer 12 */
+#define FDCAN_TX_BUFFER13 ((uint32_t)0x00002000U) /*!< Add message to Tx Buffer 13 */
+#define FDCAN_TX_BUFFER14 ((uint32_t)0x00004000U) /*!< Add message to Tx Buffer 14 */
+#define FDCAN_TX_BUFFER15 ((uint32_t)0x00008000U) /*!< Add message to Tx Buffer 15 */
+#define FDCAN_TX_BUFFER16 ((uint32_t)0x00010000U) /*!< Add message to Tx Buffer 16 */
+#define FDCAN_TX_BUFFER17 ((uint32_t)0x00020000U) /*!< Add message to Tx Buffer 17 */
+#define FDCAN_TX_BUFFER18 ((uint32_t)0x00040000U) /*!< Add message to Tx Buffer 18 */
+#define FDCAN_TX_BUFFER19 ((uint32_t)0x00080000U) /*!< Add message to Tx Buffer 19 */
+#define FDCAN_TX_BUFFER20 ((uint32_t)0x00100000U) /*!< Add message to Tx Buffer 20 */
+#define FDCAN_TX_BUFFER21 ((uint32_t)0x00200000U) /*!< Add message to Tx Buffer 21 */
+#define FDCAN_TX_BUFFER22 ((uint32_t)0x00400000U) /*!< Add message to Tx Buffer 22 */
+#define FDCAN_TX_BUFFER23 ((uint32_t)0x00800000U) /*!< Add message to Tx Buffer 23 */
+#define FDCAN_TX_BUFFER24 ((uint32_t)0x01000000U) /*!< Add message to Tx Buffer 24 */
+#define FDCAN_TX_BUFFER25 ((uint32_t)0x02000000U) /*!< Add message to Tx Buffer 25 */
+#define FDCAN_TX_BUFFER26 ((uint32_t)0x04000000U) /*!< Add message to Tx Buffer 26 */
+#define FDCAN_TX_BUFFER27 ((uint32_t)0x08000000U) /*!< Add message to Tx Buffer 27 */
+#define FDCAN_TX_BUFFER28 ((uint32_t)0x10000000U) /*!< Add message to Tx Buffer 28 */
+#define FDCAN_TX_BUFFER29 ((uint32_t)0x20000000U) /*!< Add message to Tx Buffer 29 */
+#define FDCAN_TX_BUFFER30 ((uint32_t)0x40000000U) /*!< Add message to Tx Buffer 30 */
+#define FDCAN_TX_BUFFER31 ((uint32_t)0x80000000U) /*!< Add message to Tx Buffer 31 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Rx_location FDCAN Rx Location
+  * @{
+  */
+#define FDCAN_RX_FIFO0    ((uint32_t)0x00000040U) /*!< Get received message from Rx FIFO 0    */
+#define FDCAN_RX_FIFO1    ((uint32_t)0x00000041U) /*!< Get received message from Rx FIFO 1    */
+#define FDCAN_RX_BUFFER0  ((uint32_t)0x00000000U) /*!< Get received message from Rx Buffer 0  */
+#define FDCAN_RX_BUFFER1  ((uint32_t)0x00000001U) /*!< Get received message from Rx Buffer 1  */
+#define FDCAN_RX_BUFFER2  ((uint32_t)0x00000002U) /*!< Get received message from Rx Buffer 2  */
+#define FDCAN_RX_BUFFER3  ((uint32_t)0x00000003U) /*!< Get received message from Rx Buffer 3  */
+#define FDCAN_RX_BUFFER4  ((uint32_t)0x00000004U) /*!< Get received message from Rx Buffer 4  */
+#define FDCAN_RX_BUFFER5  ((uint32_t)0x00000005U) /*!< Get received message from Rx Buffer 5  */
+#define FDCAN_RX_BUFFER6  ((uint32_t)0x00000006U) /*!< Get received message from Rx Buffer 6  */
+#define FDCAN_RX_BUFFER7  ((uint32_t)0x00000007U) /*!< Get received message from Rx Buffer 7  */
+#define FDCAN_RX_BUFFER8  ((uint32_t)0x00000008U) /*!< Get received message from Rx Buffer 8  */
+#define FDCAN_RX_BUFFER9  ((uint32_t)0x00000009U) /*!< Get received message from Rx Buffer 9  */
+#define FDCAN_RX_BUFFER10 ((uint32_t)0x0000000AU) /*!< Get received message from Rx Buffer 10 */
+#define FDCAN_RX_BUFFER11 ((uint32_t)0x0000000BU) /*!< Get received message from Rx Buffer 11 */
+#define FDCAN_RX_BUFFER12 ((uint32_t)0x0000000CU) /*!< Get received message from Rx Buffer 12 */
+#define FDCAN_RX_BUFFER13 ((uint32_t)0x0000000DU) /*!< Get received message from Rx Buffer 13 */
+#define FDCAN_RX_BUFFER14 ((uint32_t)0x0000000EU) /*!< Get received message from Rx Buffer 14 */
+#define FDCAN_RX_BUFFER15 ((uint32_t)0x0000000FU) /*!< Get received message from Rx Buffer 15 */
+#define FDCAN_RX_BUFFER16 ((uint32_t)0x00000010U) /*!< Get received message from Rx Buffer 16 */
+#define FDCAN_RX_BUFFER17 ((uint32_t)0x00000011U) /*!< Get received message from Rx Buffer 17 */
+#define FDCAN_RX_BUFFER18 ((uint32_t)0x00000012U) /*!< Get received message from Rx Buffer 18 */
+#define FDCAN_RX_BUFFER19 ((uint32_t)0x00000013U) /*!< Get received message from Rx Buffer 19 */
+#define FDCAN_RX_BUFFER20 ((uint32_t)0x00000014U) /*!< Get received message from Rx Buffer 20 */
+#define FDCAN_RX_BUFFER21 ((uint32_t)0x00000015U) /*!< Get received message from Rx Buffer 21 */
+#define FDCAN_RX_BUFFER22 ((uint32_t)0x00000016U) /*!< Get received message from Rx Buffer 22 */
+#define FDCAN_RX_BUFFER23 ((uint32_t)0x00000017U) /*!< Get received message from Rx Buffer 23 */
+#define FDCAN_RX_BUFFER24 ((uint32_t)0x00000018U) /*!< Get received message from Rx Buffer 24 */
+#define FDCAN_RX_BUFFER25 ((uint32_t)0x00000019U) /*!< Get received message from Rx Buffer 25 */
+#define FDCAN_RX_BUFFER26 ((uint32_t)0x0000001AU) /*!< Get received message from Rx Buffer 26 */
+#define FDCAN_RX_BUFFER27 ((uint32_t)0x0000001BU) /*!< Get received message from Rx Buffer 27 */
+#define FDCAN_RX_BUFFER28 ((uint32_t)0x0000001CU) /*!< Get received message from Rx Buffer 28 */
+#define FDCAN_RX_BUFFER29 ((uint32_t)0x0000001DU) /*!< Get received message from Rx Buffer 29 */
+#define FDCAN_RX_BUFFER30 ((uint32_t)0x0000001EU) /*!< Get received message from Rx Buffer 30 */
+#define FDCAN_RX_BUFFER31 ((uint32_t)0x0000001FU) /*!< Get received message from Rx Buffer 31 */
+#define FDCAN_RX_BUFFER32 ((uint32_t)0x00000020U) /*!< Get received message from Rx Buffer 32 */
+#define FDCAN_RX_BUFFER33 ((uint32_t)0x00000021U) /*!< Get received message from Rx Buffer 33 */
+#define FDCAN_RX_BUFFER34 ((uint32_t)0x00000022U) /*!< Get received message from Rx Buffer 34 */
+#define FDCAN_RX_BUFFER35 ((uint32_t)0x00000023U) /*!< Get received message from Rx Buffer 35 */
+#define FDCAN_RX_BUFFER36 ((uint32_t)0x00000024U) /*!< Get received message from Rx Buffer 36 */
+#define FDCAN_RX_BUFFER37 ((uint32_t)0x00000025U) /*!< Get received message from Rx Buffer 37 */
+#define FDCAN_RX_BUFFER38 ((uint32_t)0x00000026U) /*!< Get received message from Rx Buffer 38 */
+#define FDCAN_RX_BUFFER39 ((uint32_t)0x00000027U) /*!< Get received message from Rx Buffer 39 */
+#define FDCAN_RX_BUFFER40 ((uint32_t)0x00000028U) /*!< Get received message from Rx Buffer 40 */
+#define FDCAN_RX_BUFFER41 ((uint32_t)0x00000029U) /*!< Get received message from Rx Buffer 41 */
+#define FDCAN_RX_BUFFER42 ((uint32_t)0x0000002AU) /*!< Get received message from Rx Buffer 42 */
+#define FDCAN_RX_BUFFER43 ((uint32_t)0x0000002BU) /*!< Get received message from Rx Buffer 43 */
+#define FDCAN_RX_BUFFER44 ((uint32_t)0x0000002CU) /*!< Get received message from Rx Buffer 44 */
+#define FDCAN_RX_BUFFER45 ((uint32_t)0x0000002DU) /*!< Get received message from Rx Buffer 45 */
+#define FDCAN_RX_BUFFER46 ((uint32_t)0x0000002EU) /*!< Get received message from Rx Buffer 46 */
+#define FDCAN_RX_BUFFER47 ((uint32_t)0x0000002FU) /*!< Get received message from Rx Buffer 47 */
+#define FDCAN_RX_BUFFER48 ((uint32_t)0x00000030U) /*!< Get received message from Rx Buffer 48 */
+#define FDCAN_RX_BUFFER49 ((uint32_t)0x00000031U) /*!< Get received message from Rx Buffer 49 */
+#define FDCAN_RX_BUFFER50 ((uint32_t)0x00000032U) /*!< Get received message from Rx Buffer 50 */
+#define FDCAN_RX_BUFFER51 ((uint32_t)0x00000033U) /*!< Get received message from Rx Buffer 51 */
+#define FDCAN_RX_BUFFER52 ((uint32_t)0x00000034U) /*!< Get received message from Rx Buffer 52 */
+#define FDCAN_RX_BUFFER53 ((uint32_t)0x00000035U) /*!< Get received message from Rx Buffer 53 */
+#define FDCAN_RX_BUFFER54 ((uint32_t)0x00000036U) /*!< Get received message from Rx Buffer 54 */
+#define FDCAN_RX_BUFFER55 ((uint32_t)0x00000037U) /*!< Get received message from Rx Buffer 55 */
+#define FDCAN_RX_BUFFER56 ((uint32_t)0x00000038U) /*!< Get received message from Rx Buffer 56 */
+#define FDCAN_RX_BUFFER57 ((uint32_t)0x00000039U) /*!< Get received message from Rx Buffer 57 */
+#define FDCAN_RX_BUFFER58 ((uint32_t)0x0000003AU) /*!< Get received message from Rx Buffer 58 */
+#define FDCAN_RX_BUFFER59 ((uint32_t)0x0000003BU) /*!< Get received message from Rx Buffer 59 */
+#define FDCAN_RX_BUFFER60 ((uint32_t)0x0000003CU) /*!< Get received message from Rx Buffer 60 */
+#define FDCAN_RX_BUFFER61 ((uint32_t)0x0000003DU) /*!< Get received message from Rx Buffer 61 */
+#define FDCAN_RX_BUFFER62 ((uint32_t)0x0000003EU) /*!< Get received message from Rx Buffer 62 */
+#define FDCAN_RX_BUFFER63 ((uint32_t)0x0000003FU) /*!< Get received message from Rx Buffer 63 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_event_type FDCAN Event Type
+  * @{
+  */
+#define FDCAN_TX_EVENT             ((uint32_t)0x00400000U) /*!< Tx event                              */
+#define FDCAN_TX_IN_SPITE_OF_ABORT ((uint32_t)0x00800000U) /*!< Transmission in spite of cancellation */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_hp_msg_storage FDCAN High Priority Message Storage
+  * @{
+  */
+#define FDCAN_HP_STORAGE_NO_FIFO  ((uint32_t)0x00000000U) /*!< No FIFO selected         */
+#define FDCAN_HP_STORAGE_MSG_LOST ((uint32_t)0x00000040U) /*!< FIFO message lost        */
+#define FDCAN_HP_STORAGE_RXFIFO0  ((uint32_t)0x00000080U) /*!< Message stored in FIFO 0 */
+#define FDCAN_HP_STORAGE_RXFIFO1  ((uint32_t)0x000000C0U) /*!< Message stored in FIFO 1 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_protocol_error_code FDCAN protocol error code
+  * @{
+  */
+#define FDCAN_PROTOCOL_ERROR_NONE      ((uint32_t)0x00000000U) /*!< No error occurred         */
+#define FDCAN_PROTOCOL_ERROR_STUFF     ((uint32_t)0x00000001U) /*!< Stuff error               */
+#define FDCAN_PROTOCOL_ERROR_FORM      ((uint32_t)0x00000002U) /*!< Form error                */
+#define FDCAN_PROTOCOL_ERROR_ACK       ((uint32_t)0x00000003U) /*!< Acknowledge error         */
+#define FDCAN_PROTOCOL_ERROR_BIT1      ((uint32_t)0x00000004U) /*!< Bit 1 (recessive) error   */
+#define FDCAN_PROTOCOL_ERROR_BIT0      ((uint32_t)0x00000005U) /*!< Bit 0 (dominant) error    */
+#define FDCAN_PROTOCOL_ERROR_CRC       ((uint32_t)0x00000006U) /*!< CRC check sum error       */
+#define FDCAN_PROTOCOL_ERROR_NO_CHANGE ((uint32_t)0x00000007U) /*!< No change since last read */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_communication_state FDCAN communication state
+  * @{
+  */
+#define FDCAN_COM_STATE_SYNC ((uint32_t)0x00000000U) /*!< Node is synchronizing on CAN communication */
+#define FDCAN_COM_STATE_IDLE ((uint32_t)0x00000008U) /*!< Node is neither receiver nor transmitter   */
+#define FDCAN_COM_STATE_RX   ((uint32_t)0x00000010U) /*!< Node is operating as receiver              */
+#define FDCAN_COM_STATE_TX   ((uint32_t)0x00000018U) /*!< Node is operating as transmitter           */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_FIFO_watermark FDCAN FIFO watermark
+  * @{
+  */
+#define FDCAN_CFG_TX_EVENT_FIFO ((uint32_t)0x00000000U) /*!< Tx event FIFO */
+#define FDCAN_CFG_RX_FIFO0      ((uint32_t)0x00000001U) /*!< Rx FIFO0      */
+#define FDCAN_CFG_RX_FIFO1      ((uint32_t)0x00000002U) /*!< Rx FIFO1      */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Rx_FIFO_operation_mode FDCAN FIFO operation mode
+  * @{
+  */
+#define FDCAN_RX_FIFO_BLOCKING  ((uint32_t)0x00000000U) /*!< Rx FIFO blocking mode  */
+#define FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x80000000U) /*!< Rx FIFO overwrite mode */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Non_Matching_Frames FDCAN non-matching frames
+  * @{
+  */
+#define FDCAN_ACCEPT_IN_RX_FIFO0 ((uint32_t)0x00000000U) /*!< Accept in Rx FIFO 0 */
+#define FDCAN_ACCEPT_IN_RX_FIFO1 ((uint32_t)0x00000001U) /*!< Accept in Rx FIFO 1 */
+#define FDCAN_REJECT             ((uint32_t)0x00000002U) /*!< Reject              */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Reject_Remote_Frames FDCAN reject remote frames
+  * @{
+  */
+#define FDCAN_FILTER_REMOTE ((uint32_t)0x00000000U) /*!< Filter remote frames */
+#define FDCAN_REJECT_REMOTE ((uint32_t)0x00000001U) /*!< Reject all remote frames */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Interrupt_Line FDCAN interrupt line
+  * @{
+  */
+#define FDCAN_INTERRUPT_LINE0 ((uint32_t)0x00000001U) /*!< Interrupt Line 0 */
+#define FDCAN_INTERRUPT_LINE1 ((uint32_t)0x00000002U) /*!< Interrupt Line 1 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Timestamp FDCAN timestamp
+  * @{
+  */
+#define FDCAN_TIMESTAMP_INTERNAL ((uint32_t)0x00000001U) /*!< Timestamp counter value incremented according to TCP */
+#define FDCAN_TIMESTAMP_EXTERNAL ((uint32_t)0x00000002U) /*!< External timestamp counter value used                */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Timestamp_Prescaler FDCAN timestamp prescaler
+  * @{
+  */
+#define FDCAN_TIMESTAMP_PRESC_1  ((uint32_t)0x00000000U) /*!< Timestamp counter time unit in equal to CAN bit time                 */
+#define FDCAN_TIMESTAMP_PRESC_2  ((uint32_t)0x00010000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 2  */
+#define FDCAN_TIMESTAMP_PRESC_3  ((uint32_t)0x00020000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 3  */
+#define FDCAN_TIMESTAMP_PRESC_4  ((uint32_t)0x00030000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 4  */
+#define FDCAN_TIMESTAMP_PRESC_5  ((uint32_t)0x00040000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 5  */
+#define FDCAN_TIMESTAMP_PRESC_6  ((uint32_t)0x00050000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 6  */
+#define FDCAN_TIMESTAMP_PRESC_7  ((uint32_t)0x00060000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 7  */
+#define FDCAN_TIMESTAMP_PRESC_8  ((uint32_t)0x00070000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 8  */
+#define FDCAN_TIMESTAMP_PRESC_9  ((uint32_t)0x00080000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 9  */
+#define FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 10 */
+#define FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 11 */
+#define FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 12 */
+#define FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 13 */
+#define FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 14 */
+#define FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 15 */
+#define FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 16 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Timeout_Operation FDCAN timeout operation
+  * @{
+  */
+#define FDCAN_TIMEOUT_CONTINUOUS    ((uint32_t)0x00000000U) /*!< Timeout continuous operation        */
+#define FDCAN_TIMEOUT_TX_EVENT_FIFO ((uint32_t)0x00000002U) /*!< Timeout controlled by Tx Event FIFO */
+#define FDCAN_TIMEOUT_RX_FIFO0      ((uint32_t)0x00000004U) /*!< Timeout controlled by Rx FIFO 0     */
+#define FDCAN_TIMEOUT_RX_FIFO1      ((uint32_t)0x00000006U) /*!< Timeout controlled by Rx FIFO 1     */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_Reference_Message_Payload FDCAN TT reference message payload
+  * @{
+  */
+#define FDCAN_TT_REF_MESSAGE_NO_PAYLOAD  ((uint32_t)0x00000000U)      /*!< Reference message has no additional payload  */
+#define FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD ((uint32_t)FDCAN_TTRMC_RMPS) /*!< Additional payload is taken from Tx Buffer 0 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_Repeat_Factor FDCAN TT repeat factor
+  * @{
+  */
+#define FDCAN_TT_REPEAT_EVERY_CYCLE      ((uint32_t)0x00000000U) /*!< Trigger valid for all cycles   */
+#define FDCAN_TT_REPEAT_EVERY_2ND_CYCLE  ((uint32_t)0x00000002U) /*!< Trigger valid every 2dn cycle  */
+#define FDCAN_TT_REPEAT_EVERY_4TH_CYCLE  ((uint32_t)0x00000004U) /*!< Trigger valid every 4th cycle  */
+#define FDCAN_TT_REPEAT_EVERY_8TH_CYCLE  ((uint32_t)0x00000008U) /*!< Trigger valid every 8th cycle  */
+#define FDCAN_TT_REPEAT_EVERY_16TH_CYCLE ((uint32_t)0x00000010U) /*!< Trigger valid every 16th cycle */
+#define FDCAN_TT_REPEAT_EVERY_32ND_CYCLE ((uint32_t)0x00000020U) /*!< Trigger valid every 32nd cycle */
+#define FDCAN_TT_REPEAT_EVERY_64TH_CYCLE ((uint32_t)0x00000040U) /*!< Trigger valid every 64th cycle */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_Trigger_Type FDCAN TT trigger type
+  * @{
+  */
+#define FDCAN_TT_TX_REF_TRIGGER         ((uint32_t)0x00000000U) /*!< Transmit reference message in strictly time-triggered operation                                                     */
+#define FDCAN_TT_TX_REF_TRIGGER_GAP     ((uint32_t)0x00000001U) /*!< Transmit reference message in external event-synchronized time-triggered operation                                  */
+#define FDCAN_TT_TX_TRIGGER_SINGLE      ((uint32_t)0x00000002U) /*!< Start a single transmission in an exclusive time window                                                             */
+#define FDCAN_TT_TX_TRIGGER_CONTINUOUS  ((uint32_t)0x00000003U) /*!< Start a continuous transmission in an exclusive time window                                                         */
+#define FDCAN_TT_TX_TRIGGER_ARBITRATION ((uint32_t)0x00000004U) /*!< Start a transmission in an arbitration time window                                                                  */
+#define FDCAN_TT_TX_TRIGGER_MERGED      ((uint32_t)0x00000005U) /*!< Start a merged arbitration window                                                                                   */
+#define FDCAN_TT_WATCH_TRIGGER          ((uint32_t)0x00000006U) /*!< Check for missing reference messages in strictly time-triggered operation                                           */
+#define FDCAN_TT_WATCH_TRIGGER_GAP      ((uint32_t)0x00000007U) /*!< Check for missing reference messages in external event-synchronized time-triggered operation                        */
+#define FDCAN_TT_RX_TRIGGER             ((uint32_t)0x00000008U) /*!< Check for the reception of periodic messages in exclusive time windows                                              */
+#define FDCAN_TT_TIME_BASE_TRIGGER      ((uint32_t)0x00000009U) /*!< Generate internal/external events depending on TmEventInt/TmEventExt configuration                                  */
+#define FDCAN_TT_END_OF_LIST            ((uint32_t)0x0000000AU) /*!< Illegal trigger, to be assigned to the unused triggers after a FDCAN_TT_WATCH_TRIGGER or FDCAN_TT_WATCH_TRIGGER_GAP */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_Time_Mark_Event_Internal FDCAN TT time mark event internal
+  * @{
+  */
+#define FDCAN_TT_TM_NO_INTERNAL_EVENT  ((uint32_t)0x00000000U) /*!< No action                                               */
+#define FDCAN_TT_TM_GEN_INTERNAL_EVENT ((uint32_t)0x00000020U) /*!< Internal event is generated when trigger becomes active */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_Time_Mark_Event_External FDCAN TT time mark event external
+  * @{
+  */
+#define FDCAN_TT_TM_NO_EXTERNAL_EVENT  ((uint32_t)0x00000000U) /*!< No action                                                       */
+#define FDCAN_TT_TM_GEN_EXTERNAL_EVENT ((uint32_t)0x00000010U) /*!< External event (pulse) is generated when trigger becomes active */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_operation_mode FDCAN Operation Mode
+  * @{
+  */
+#define FDCAN_TT_COMMUNICATION_LEVEL1    ((uint32_t)0x00000001U) /*!< Time triggered communication, level 1 */
+#define FDCAN_TT_COMMUNICATION_LEVEL2    ((uint32_t)0x00000002U) /*!< Time triggered communication, level 2 */
+#define FDCAN_TT_COMMUNICATION_LEVEL0    ((uint32_t)0x00000003U) /*!< Time triggered communication, level 0 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_operation FDCAN TT Operation
+  * @{
+  */
+#define FDCAN_STRICTLY_TT_OPERATION     ((uint32_t)0x00000000U)     /*!< Strictly time-triggered operation                    */
+#define FDCAN_EXT_EVT_SYNC_TT_OPERATION ((uint32_t)FDCAN_TTOCF_GEN) /*!< External event-synchronized time-triggered operation */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_time_master FDCAN TT Time Master
+  * @{
+  */
+#define FDCAN_TT_SLAVE            ((uint32_t)0x00000000U)    /*!< Time slave            */
+#define FDCAN_TT_POTENTIAL_MASTER ((uint32_t)FDCAN_TTOCF_TM) /*!< Potential time master */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_external_clk_sync FDCAN TT External Clock Synchronization
+  * @{
+  */
+#define FDCAN_TT_EXT_CLK_SYNC_DISABLE ((uint32_t)0x00000000U)      /*!< External clock synchronization in Level 0,2 disabled */
+#define FDCAN_TT_EXT_CLK_SYNC_ENABLE  ((uint32_t)FDCAN_TTOCF_EECS) /*!< External clock synchronization in Level 0,2 enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_global_time_filtering FDCAN TT Global Time Filtering
+  * @{
+  */
+#define FDCAN_TT_GLOB_TIME_FILT_DISABLE ((uint32_t)0x00000000U)      /*!< Global time filtering in Level 0,2 disabled */
+#define FDCAN_TT_GLOB_TIME_FILT_ENABLE  ((uint32_t)FDCAN_TTOCF_EGTF) /*!< Global time filtering in Level 0,2 enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_auto_clk_calibration FDCAN TT Automatic Clock Calibration
+  * @{
+  */
+#define FDCAN_TT_AUTO_CLK_CALIB_DISABLE ((uint32_t)0x00000000U)     /*!< Automatic clock calibration in Level 0,2 disabled */
+#define FDCAN_TT_AUTO_CLK_CALIB_ENABLE  ((uint32_t)FDCAN_TTOCF_ECC) /*!< Automatic clock calibration in Level 0,2 enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_event_trig_polarity FDCAN TT Event Trigger Polarity
+  * @{
+  */
+#define FDCAN_TT_EVT_TRIG_POL_RISING  ((uint32_t)0x00000000U)      /*!< Rising edge trigger  */
+#define FDCAN_TT_EVT_TRIG_POL_FALLING ((uint32_t)FDCAN_TTOCF_EVTP) /*!< Falling edge trigger */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_basic_cycle_number FDCAN TT Basic Cycle Number
+  * @{
+  */
+#define FDCAN_TT_CYCLES_PER_MATRIX_1  ((uint32_t)0x00000000U) /*!< 1 Basic Cycle per Matrix   */
+#define FDCAN_TT_CYCLES_PER_MATRIX_2  ((uint32_t)0x00000001U) /*!< 2 Basic Cycles per Matrix  */
+#define FDCAN_TT_CYCLES_PER_MATRIX_4  ((uint32_t)0x00000003U) /*!< 4 Basic Cycles per Matrix  */
+#define FDCAN_TT_CYCLES_PER_MATRIX_8  ((uint32_t)0x00000007U) /*!< 8 Basic Cycles per Matrix  */
+#define FDCAN_TT_CYCLES_PER_MATRIX_16 ((uint32_t)0x0000000FU) /*!< 16 Basic Cycles per Matrix */
+#define FDCAN_TT_CYCLES_PER_MATRIX_32 ((uint32_t)0x0000001FU) /*!< 32 Basic Cycles per Matrix */
+#define FDCAN_TT_CYCLES_PER_MATRIX_64 ((uint32_t)0x0000003FU) /*!< 64 Basic Cycles per Matrix */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_cycle_start_sync FDCAN TT Cycle Start Sync
+  * @{
+  */
+#define FDCAN_TT_NO_SYNC_PULSE          ((uint32_t)0x00000000U) /*!< No sync pulse                      */
+#define FDCAN_TT_SYNC_BASIC_CYCLE_START ((uint32_t)0x00000040U) /*!< Sync pulse at start of basic cycle */
+#define FDCAN_TT_SYNC_MATRIX_START      ((uint32_t)0x00000080U) /*!< Sync pulse at start of matrix      */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_stop_watch_trig_selection FDCAN TT Stop Watch Trigger Selection
+  * @{
+  */
+#define FDCAN_TT_STOP_WATCH_TRIGGER_0 ((uint32_t)0x00000000U) /*!< TIM2 selected as stop watch trigger  */
+#define FDCAN_TT_STOP_WATCH_TRIGGER_1 ((uint32_t)0x00000001U) /*!< TIM3 selected as stop watch trigger  */
+#define FDCAN_TT_STOP_WATCH_TRIGGER_2 ((uint32_t)0x00000002U) /*!< ETH selected as stop watch trigger   */
+#define FDCAN_TT_STOP_WATCH_TRIGGER_3 ((uint32_t)0x00000003U) /*!< HRTIM selected as stop watch trigger */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_event_trig_selection FDCAN TT Event Trigger Selection
+  * @{
+  */
+#define FDCAN_TT_EVENT_TRIGGER_0 ((uint32_t)0x00000000U) /*!< TIM2 selected as event trigger  */
+#define FDCAN_TT_EVENT_TRIGGER_1 ((uint32_t)0x00000010U) /*!< TIM3 selected as event trigger  */
+#define FDCAN_TT_EVENT_TRIGGER_2 ((uint32_t)0x00000020U) /*!< ETH selected as event trigger   */
+#define FDCAN_TT_EVENT_TRIGGER_3 ((uint32_t)0x00000030U) /*!< HRTIM selected as event trigger */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_stop_watch_source FDCAN TT Stop Watch Source
+  * @{
+  */
+#define FDCAN_TT_STOP_WATCH_DISABLED    ((uint32_t)0x00000000U) /*!< Stop Watch disabled                                                        */
+#define FDCAN_TT_STOP_WATCH_CYCLE_TIME  ((uint32_t)0x00000008U) /*!< Actual value of cycle time is copied to Capture Time register (TTCPT.SWV)  */
+#define FDCAN_TT_STOP_WATCH_LOCAL_TIME  ((uint32_t)0x00000010U) /*!< Actual value of local time is copied to Capture Time register (TTCPT.SWV)  */
+#define FDCAN_TT_STOP_WATCH_GLOBAL_TIME ((uint32_t)0x00000018U) /*!< Actual value of global time is copied to Capture Time register (TTCPT.SWV) */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_stop_watch_polarity FDCAN TT Stop Watch Polarity
+  * @{
+  */
+#define FDCAN_TT_STOP_WATCH_RISING  ((uint32_t)0x00000000U) /*!< Selected stop watch source is captured at rising edge of fdcan1_swt  */
+#define FDCAN_TT_STOP_WATCH_FALLING ((uint32_t)0x00000004U) /*!< Selected stop watch source is captured at falling edge of fdcan1_swt */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_time_mark_source FDCAN TT Time Mark Source
+  * @{
+  */
+#define FDCAN_TT_REG_TIMEMARK_DIABLED  ((uint32_t)0x00000000U) /*!< No Register Time Mark Interrupt generated               */
+#define FDCAN_TT_REG_TIMEMARK_CYC_TIME ((uint32_t)0x00000040U) /*!< Register Time Mark Interrupt if Time Mark = cycle time  */
+#define FDCAN_TT_REG_TIMEMARK_LOC_TIME ((uint32_t)0x00000080U) /*!< Register Time Mark Interrupt if Time Mark = local time  */
+#define FDCAN_TT_REG_TIMEMARK_GLO_TIME ((uint32_t)0x000000C0U) /*!< Register Time Mark Interrupt if Time Mark = global time */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_error_level FDCAN TT Error Level
+  * @{
+  */
+#define FDCAN_TT_NO_ERROR     ((uint32_t)0x00000000U) /*!< Severity 0 - No Error     */
+#define FDCAN_TT_WARNING      ((uint32_t)0x00000001U) /*!< Severity 1 - Warning      */
+#define FDCAN_TT_ERROR        ((uint32_t)0x00000002U) /*!< Severity 2 - Error        */
+#define FDCAN_TT_SEVERE_ERROR ((uint32_t)0x00000003U) /*!< Severity 3 - Severe Error */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_master_state FDCAN TT Master State
+  * @{
+  */
+#define FDCAN_TT_MASTER_OFF          ((uint32_t)0x00000000U) /*!< Master_Off, no master properties relevant */
+#define FDCAN_TT_TIME_SLAVE          ((uint32_t)0x00000004U) /*!< Operating as Time Slave                   */
+#define FDCAN_TT_BACKUP_TIME_MASTER  ((uint32_t)0x00000008U) /*!< Operating as Backup Time Master           */
+#define FDCAN_TT_CURRENT_TIME_MASTER ((uint32_t)0x0000000CU) /*!< Operating as current Time Master          */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_sync_state FDCAN TT Synchronization State
+  * @{
+  */
+#define FDCAN_TT_OUT_OF_SYNC   ((uint32_t)0x00000000U) /*!< Out of Synchronization         */
+#define FDCAN_TT_SYNCHRONIZING ((uint32_t)0x00000010U) /*!< Synchronizing to communication */
+#define FDCAN_TT_IN_GAP        ((uint32_t)0x00000020U) /*!< Schedule suspended by Gap      */
+#define FDCAN_TT_IN_SCHEDULE   ((uint32_t)0x00000030U) /*!< Synchronized to schedule       */
+/**
+  * @}
+  */
+
+/** @defgroup Interrupt_Masks Interrupt masks
+  * @{
+  */
+#define FDCAN_IR_MASK ((uint32_t)0x3FCFFFFFU) /*!< FDCAN interrupts mask */
+#define CCU_IR_MASK   ((uint32_t)0xC0000000U) /*!< CCU interrupts mask   */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_flags FDCAN Flags
+  * @{
+  */
+#define FDCAN_FLAG_TX_COMPLETE             FDCAN_IR_TC             /*!< Transmission Completed                                */
+#define FDCAN_FLAG_TX_ABORT_COMPLETE       FDCAN_IR_TCF            /*!< Transmission Cancellation Finished                    */
+#define FDCAN_FLAG_TX_FIFO_EMPTY           FDCAN_IR_TFE            /*!< Tx FIFO Empty                                         */
+#define FDCAN_FLAG_RX_HIGH_PRIORITY_MSG    FDCAN_IR_HPM            /*!< High priority message received                        */
+#define FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE   FDCAN_IR_DRX            /*!< At least one received message stored into a Rx Buffer */
+#define FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST    FDCAN_IR_TEFL           /*!< Tx Event FIFO element lost                            */
+#define FDCAN_FLAG_TX_EVT_FIFO_FULL        FDCAN_IR_TEFF           /*!< Tx Event FIFO full                                    */
+#define FDCAN_FLAG_TX_EVT_FIFO_WATERMARK   FDCAN_IR_TEFW           /*!< Tx Event FIFO fill level reached watermark            */
+#define FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA    FDCAN_IR_TEFN           /*!< Tx Handler wrote Tx Event FIFO element                */
+#define FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST   FDCAN_IR_RF0L           /*!< Rx FIFO 0 message lost                                */
+#define FDCAN_FLAG_RX_FIFO0_FULL           FDCAN_IR_RF0F           /*!< Rx FIFO 0 full                                        */
+#define FDCAN_FLAG_RX_FIFO0_WATERMARK      FDCAN_IR_RF0W           /*!< Rx FIFO 0 fill level reached watermark                */
+#define FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE    FDCAN_IR_RF0N           /*!< New message written to Rx FIFO 0                      */
+#define FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST   FDCAN_IR_RF1L           /*!< Rx FIFO 1 message lost                                */
+#define FDCAN_FLAG_RX_FIFO1_FULL           FDCAN_IR_RF1F           /*!< Rx FIFO 1 full                                        */
+#define FDCAN_FLAG_RX_FIFO1_WATERMARK      FDCAN_IR_RF1W           /*!< Rx FIFO 1 fill level reached watermark                */
+#define FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE    FDCAN_IR_RF1N           /*!< New message written to Rx FIFO 1                      */
+#define FDCAN_FLAG_RAM_ACCESS_FAILURE      FDCAN_IR_MRAF           /*!< Message RAM access failure occurred                   */
+#define FDCAN_FLAG_ERROR_LOGGING_OVERFLOW  FDCAN_IR_ELO            /*!< Overflow of FDCAN Error Logging Counter occurred      */
+#define FDCAN_FLAG_ERROR_PASSIVE           FDCAN_IR_EP             /*!< Error_Passive status changed                          */
+#define FDCAN_FLAG_ERROR_WARNING           FDCAN_IR_EW             /*!< Error_Warning status changed                          */
+#define FDCAN_FLAG_BUS_OFF                 FDCAN_IR_BO             /*!< Bus_Off status changed                                */
+#define FDCAN_FLAG_RAM_WATCHDOG            FDCAN_IR_WDI            /*!< Message RAM Watchdog event due to missing READY       */
+#define FDCAN_FLAG_ARB_PROTOCOL_ERROR      FDCAN_IR_PEA            /*!< Protocol error in arbitration phase detected          */
+#define FDCAN_FLAG_DATA_PROTOCOL_ERROR     FDCAN_IR_PED            /*!< Protocol error in data phase detected                 */
+#define FDCAN_FLAG_RESERVED_ADDRESS_ACCESS FDCAN_IR_ARA            /*!< Access to reserved address occurred                   */
+#define FDCAN_FLAG_TIMESTAMP_WRAPAROUND    FDCAN_IR_TSW            /*!< Timestamp counter wrapped around                      */
+#define FDCAN_FLAG_TIMEOUT_OCCURRED        FDCAN_IR_TOO            /*!< Timeout reached                                       */
+#define FDCAN_FLAG_CALIB_STATE_CHANGED     (FDCANCCU_IR_CSC << 30) /*!< Clock calibration state changed                       */
+#define FDCAN_FLAG_CALIB_WATCHDOG_EVENT    (FDCANCCU_IR_CWE << 30) /*!< Clock calibration watchdog event occurred             */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Interrupts FDCAN Interrupts
+  * @{
+  */
+
+/** @defgroup FDCAN_Tx_Interrupts FDCAN Tx Interrupts
+  * @{
+  */
+#define FDCAN_IT_TX_COMPLETE           FDCAN_IE_TCE   /*!< Transmission Completed                                */
+#define FDCAN_IT_TX_ABORT_COMPLETE     FDCAN_IE_TCFE  /*!< Transmission Cancellation Finished                    */
+#define FDCAN_IT_TX_FIFO_EMPTY         FDCAN_IE_TFEE  /*!< Tx FIFO Empty                                         */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Rx_Interrupts FDCAN Rx Interrupts
+  * @{
+  */
+#define FDCAN_IT_RX_HIGH_PRIORITY_MSG  FDCAN_IE_HPME  /*!< High priority message received                        */
+#define FDCAN_IT_RX_BUFFER_NEW_MESSAGE FDCAN_IE_DRXE  /*!< At least one received message stored into a Rx Buffer */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Counter_Interrupts FDCAN Counter Interrupts
+  * @{
+  */
+#define FDCAN_IT_TIMESTAMP_WRAPAROUND  FDCAN_IE_TSWE  /*!< Timestamp counter wrapped around                      */
+#define FDCAN_IT_TIMEOUT_OCCURRED      FDCAN_IE_TOOE  /*!< Timeout reached                                       */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Clock_Calibration_Interrupts Clock Calibration Interrupts
+  * @{
+  */
+#define FDCAN_IT_CALIB_STATE_CHANGED  (FDCANCCU_IE_CSCE << 30) /*!< Clock calibration state changed           */
+#define FDCAN_IT_CALIB_WATCHDOG_EVENT (FDCANCCU_IE_CWEE << 30) /*!< Clock calibration watchdog event occurred */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Tx_Event_Fifo_Interrupts FDCAN Tx Event FIFO Interrupts
+  * @{
+  */
+#define FDCAN_IT_TX_EVT_FIFO_ELT_LOST  FDCAN_IE_TEFLE /*!< Tx Event FIFO element lost                 */
+#define FDCAN_IT_TX_EVT_FIFO_FULL      FDCAN_IE_TEFFE /*!< Tx Event FIFO full                         */
+#define FDCAN_IT_TX_EVT_FIFO_WATERMARK FDCAN_IE_TEFWE /*!< Tx Event FIFO fill level reached watermark */
+#define FDCAN_IT_TX_EVT_FIFO_NEW_DATA  FDCAN_IE_TEFNE /*!< Tx Handler wrote Tx Event FIFO element     */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Rx_Fifo0_Interrupts FDCAN Rx FIFO 0 Interrupts
+  * @{
+  */
+#define FDCAN_IT_RX_FIFO0_MESSAGE_LOST FDCAN_IE_RF0LE /*!< Rx FIFO 0 message lost                 */
+#define FDCAN_IT_RX_FIFO0_FULL         FDCAN_IE_RF0FE /*!< Rx FIFO 0 full                         */
+#define FDCAN_IT_RX_FIFO0_WATERMARK    FDCAN_IE_RF0WE /*!< Rx FIFO 0 fill level reached watermark */
+#define FDCAN_IT_RX_FIFO0_NEW_MESSAGE  FDCAN_IE_RF0NE /*!< New message written to Rx FIFO 0       */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Rx_Fifo1_Interrupts FDCAN Rx FIFO 1 Interrupts
+  * @{
+  */
+#define FDCAN_IT_RX_FIFO1_MESSAGE_LOST FDCAN_IE_RF1LE /*!< Rx FIFO 1 message lost                 */
+#define FDCAN_IT_RX_FIFO1_FULL         FDCAN_IE_RF1FE /*!< Rx FIFO 1 full                         */
+#define FDCAN_IT_RX_FIFO1_WATERMARK    FDCAN_IE_RF1WE /*!< Rx FIFO 1 fill level reached watermark */
+#define FDCAN_IT_RX_FIFO1_NEW_MESSAGE  FDCAN_IE_RF1NE /*!< New message written to Rx FIFO 1       */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Error_Interrupts FDCAN Error Interrupts
+  * @{
+  */
+#define FDCAN_IT_RAM_ACCESS_FAILURE      FDCAN_IE_MRAFE /*!< Message RAM access failure occurred              */
+#define FDCAN_IT_ERROR_LOGGING_OVERFLOW  FDCAN_IE_ELOE  /*!< Overflow of FDCAN Error Logging Counter occurred */
+#define FDCAN_IT_RAM_WATCHDOG            FDCAN_IE_WDIE  /*!< Message RAM Watchdog event due to missing READY  */
+#define FDCAN_IT_ARB_PROTOCOL_ERROR      FDCAN_IE_PEAE  /*!< Protocol error in arbitration phase detected     */
+#define FDCAN_IT_DATA_PROTOCOL_ERROR     FDCAN_IE_PEDE  /*!< Protocol error in data phase detected            */
+#define FDCAN_IT_RESERVED_ADDRESS_ACCESS FDCAN_IE_ARAE  /*!< Access to reserved address occurred              */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Error_Status_Interrupts FDCAN Error Status Interrupts
+  * @{
+  */
+#define FDCAN_IT_ERROR_PASSIVE FDCAN_IE_EPE /*!< Error_Passive status changed */
+#define FDCAN_IT_ERROR_WARNING FDCAN_IE_EWE /*!< Error_Warning status changed */
+#define FDCAN_IT_BUS_OFF       FDCAN_IE_BOE /*!< Bus_Off status changed       */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TTflags FDCAN TT Flags
+  * @{
+  */
+#define FDCAN_TT_FLAG_BASIC_CYCLE_START    FDCAN_TTIR_SBC  /*!< Start of Basic Cycle             */
+#define FDCAN_TT_FLAG_MATRIX_CYCLE_START   FDCAN_TTIR_SMC  /*!< Start of Matrix Cycle            */
+#define FDCAN_TT_FLAG_SYNC_MODE_CHANGE     FDCAN_TTIR_CSM  /*!< Change of Synchronization Mode   */
+#define FDCAN_TT_FLAG_START_OF_GAP         FDCAN_TTIR_SOG  /*!< Start of Gap                     */
+#define FDCAN_TT_FLAG_REG_TIME_MARK        FDCAN_TTIR_RTMI /*!< Register Time Mark Interrupt     */
+#define FDCAN_TT_FLAG_TRIG_TIME_MARK       FDCAN_TTIR_TTMI /*!< Trigger Time Mark Event Internal */
+#define FDCAN_TT_FLAG_STOP_WATCH           FDCAN_TTIR_SWE  /*!< Stop Watch Event                 */
+#define FDCAN_TT_FLAG_GLOBAL_TIME_WRAP     FDCAN_TTIR_GTW  /*!< Global Time Wrap                 */
+#define FDCAN_TT_FLAG_GLOBAL_TIME_DISC     FDCAN_TTIR_GTD  /*!< Global Time Discontinuity        */
+#define FDCAN_TT_FLAG_GLOBAL_TIME_ERROR    FDCAN_TTIR_GTE  /*!< Global Time Error                */
+#define FDCAN_TT_FLAG_TX_COUNT_UNDERFLOW   FDCAN_TTIR_TXU  /*!< Tx Count Underflow               */
+#define FDCAN_TT_FLAG_TX_COUNT_OVERFLOW    FDCAN_TTIR_TXO  /*!< Tx Count Overflow                */
+#define FDCAN_TT_FLAG_SCHEDULING_ERROR_1   FDCAN_TTIR_SE1  /*!< Scheduling Error 1               */
+#define FDCAN_TT_FLAG_SCHEDULING_ERROR_2   FDCAN_TTIR_SE2  /*!< Scheduling Error 2               */
+#define FDCAN_TT_FLAG_ERROR_LEVEL_CHANGE   FDCAN_TTIR_ELC  /*!< Error Level Changed              */
+#define FDCAN_TT_FLAG_INIT_WATCH_TRIGGER   FDCAN_TTIR_IWT  /*!< Initialization Watch Trigger     */
+#define FDCAN_TT_FLAG_WATCH_TRIGGER        FDCAN_TTIR_WT   /*!< Watch Trigger                    */
+#define FDCAN_TT_FLAG_APPLICATION_WATCHDOG FDCAN_TTIR_AW   /*!< Application Watchdog             */
+#define FDCAN_TT_FLAG_CONFIG_ERROR         FDCAN_TTIR_CER  /*!< Configuration Error              */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TTInterrupts FDCAN TT Interrupts
+  * @{
+  */
+
+/** @defgroup FDCAN_TTScheduleSynchronization_Interrupts FDCAN TT Schedule Synchronization Interrupts
+  * @{
+  */
+#define FDCAN_TT_IT_BASIC_CYCLE_START  FDCAN_TTIE_SBCE /*!< Start of Basic Cycle           */
+#define FDCAN_TT_IT_MATRIX_CYCLE_START FDCAN_TTIE_SMCE /*!< Start of Matrix Cycle          */
+#define FDCAN_TT_IT_SYNC_MODE_CHANGE   FDCAN_TTIE_CSME /*!< Change of Synchronization Mode */
+#define FDCAN_TT_IT_START_OF_GAP       FDCAN_TTIE_SOGE /*!< Start of Gap                   */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TTTimeMark_Interrupts FDCAN TT Time Mark Interrupts
+  * @{
+  */
+#define FDCAN_TT_IT_REG_TIME_MARK  FDCAN_TTIE_RTMIE /*!< Register Time Mark Interrupt     */
+#define FDCAN_TT_IT_TRIG_TIME_MARK FDCAN_TTIE_TTMIE /*!< Trigger Time Mark Event Internal */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TTStopWatch_Interrupt FDCAN TT Stop Watch Interrupt
+  * @{
+  */
+#define FDCAN_TT_IT_STOP_WATCH FDCAN_TTIE_SWEE /*!< Stop Watch Event */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TTGlobalTime_Interrupts FDCAN TT Global Time Interrupts
+  * @{
+  */
+#define FDCAN_TT_IT_GLOBAL_TIME_WRAP FDCAN_TTIE_GTWE  /*!< Global Time Wrap          */
+#define FDCAN_TT_IT_GLOBAL_TIME_DISC FDCAN_TTIE_GTDE  /*!< Global Time Discontinuity */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TTDisturbingError_Interrupts FDCAN TT Disturbing Error Interrupts
+  * @{
+  */
+#define FDCAN_TT_IT_GLOBAL_TIME_ERROR  FDCAN_TTIE_GTEE /*!< Global Time Error   */
+#define FDCAN_TT_IT_TX_COUNT_UNDERFLOW FDCAN_TTIE_TXUE /*!< Tx Count Underflow  */
+#define FDCAN_TT_IT_TX_COUNT_OVERFLOW  FDCAN_TTIE_TXOE /*!< Tx Count Overflow   */
+#define FDCAN_TT_IT_SCHEDULING_ERROR_1 FDCAN_TTIE_SE1E /*!< Scheduling Error 1  */
+#define FDCAN_TT_IT_SCHEDULING_ERROR_2 FDCAN_TTIE_SE2E /*!< Scheduling Error 2  */
+#define FDCAN_TT_IT_ERROR_LEVEL_CHANGE FDCAN_TTIE_ELCE /*!< Error Level Changed */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TTFatalError_Interrupts FDCAN TT Fatal Error Interrupts
+  * @{
+  */
+#define FDCAN_TT_IT_INIT_WATCH_TRIGGER   FDCAN_TTIE_IWTE /*!< Initialization Watch Trigger */
+#define FDCAN_TT_IT_WATCH_TRIGGER        FDCAN_TTIE_WTE  /*!< Watch Trigger                */
+#define FDCAN_TT_IT_APPLICATION_WATCHDOG FDCAN_TTIE_AWE  /*!< Application Watchdog         */
+#define FDCAN_TT_IT_CONFIG_ERROR         FDCAN_TTIE_CERE /*!< Configuration Error          */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup FDCAN_Exported_Macros FDCAN Exported Macros
+  * @{
+  */
+
+/** @brief  Reset FDCAN handle state.
+  * @param  __HANDLE__ FDCAN handle.
+  * @retval None
+  */
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) do{                                                \
+                                                      (__HANDLE__)->State = HAL_FDCAN_STATE_RESET;    \
+                                                      (__HANDLE__)->MspInitCallback = NULL;           \
+                                                      (__HANDLE__)->MspDeInitCallback = NULL;         \
+                                                     } while(0)
+#else
+#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FDCAN_STATE_RESET)
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+/**
+  * @brief  Enable the specified FDCAN interrupts.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ FDCAN interrupt.
+  *         This parameter can be any combination of @arg FDCAN_Interrupts
+  * @retval None
+  */
+#define __HAL_FDCAN_ENABLE_IT(__HANDLE__, __INTERRUPT__)             \
+  do{                                                                \
+    (__HANDLE__)->Instance->IE |= ((__INTERRUPT__) & FDCAN_IR_MASK); \
+    FDCAN_CCU->IE |= (((__INTERRUPT__) & CCU_IR_MASK) >> 30);        \
+  }while(0)
+
+
+/**
+  * @brief  Disable the specified FDCAN interrupts.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ FDCAN interrupt.
+  *         This parameter can be any combination of @arg FDCAN_Interrupts
+  * @retval None
+  */
+#define __HAL_FDCAN_DISABLE_IT(__HANDLE__, __INTERRUPT__)               \
+  do{                                                                   \
+    ((__HANDLE__)->Instance->IE) &= ~((__INTERRUPT__) & FDCAN_IR_MASK); \
+    FDCAN_CCU->IE &= ~(((__INTERRUPT__) & CCU_IR_MASK) >> 30);          \
+  }while(0)
+
+/**
+  * @brief  Check whether the specified FDCAN interrupt is set or not.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ FDCAN interrupt.
+  *         This parameter can be one of @arg FDCAN_Interrupts
+  * @retval ITStatus
+  */
+#define __HAL_FDCAN_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__INTERRUPT__)) : ((FDCAN_CCU->IR << 30) & (__INTERRUPT__)))
+
+/**
+  * @brief  Clear the specified FDCAN interrupts.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ specifies the interrupts to clear.
+  *         This parameter can be any combination of @arg FDCAN_Interrupts
+  * @retval None
+  */
+#define __HAL_FDCAN_CLEAR_IT(__HANDLE__, __INTERRUPT__)               \
+do{                                                                   \
+    ((__HANDLE__)->Instance->IR) = ((__INTERRUPT__) & FDCAN_IR_MASK); \
+    FDCAN_CCU->IR = (((__INTERRUPT__) & CCU_IR_MASK) >> 30);          \
+  }while(0)
+
+/**
+  * @brief  Check whether the specified FDCAN flag is set or not.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __FLAG__ FDCAN flag.
+  *         This parameter can be one of @arg FDCAN_flags
+  * @retval FlagStatus
+  */
+#define __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) < FDCAN_FLAG_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__FLAG__)) : ((FDCAN_CCU->IR << 30) & (__FLAG__)))
+
+/**
+  * @brief  Clear the specified FDCAN flags.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __FLAG__ specifies the flags to clear.
+  *         This parameter can be any combination of @arg FDCAN_flags
+  * @retval None
+  */
+#define __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__)             \
+do{                                                              \
+    ((__HANDLE__)->Instance->IR) = ((__FLAG__) & FDCAN_IR_MASK); \
+    FDCAN_CCU->IR = (((__FLAG__) & CCU_IR_MASK) >> 30);          \
+  }while(0)
+
+/** @brief  Check if the specified FDCAN interrupt source is enabled or disabled.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ specifies the FDCAN interrupt source to check.
+  *         This parameter can be a value of @arg FDCAN_Interrupts
+  * @retval ITStatus
+  */
+#define __HAL_FDCAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IE & (__INTERRUPT__)) : ((FDCAN_CCU->IE << 30) & (__INTERRUPT__)))
+
+/**
+  * @brief  Enable the specified FDCAN TT interrupts.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ FDCAN TT interrupt.
+  *         This parameter can be any combination of @arg FDCAN_TTInterrupts
+  * @retval None
+  */
+#define __HAL_FDCAN_TT_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the specified FDCAN TT interrupts.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ FDCAN TT interrupt.
+  *         This parameter can be any combination of @arg FDCAN_TTInterrupts
+  * @retval None
+  */
+#define __HAL_FDCAN_TT_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified FDCAN TT interrupt is set or not.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ FDCAN TT interrupt.
+  *         This parameter can be one of @arg FDCAN_TTInterrupts
+  * @retval ITStatus
+  */
+#define __HAL_FDCAN_TT_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) & (__INTERRUPT__))
+
+/**
+  * @brief  Clear the specified FDCAN TT interrupts.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ specifies the TT interrupts to clear.
+  *         This parameter can be any combination of @arg FDCAN_TTInterrupts
+  * @retval None
+  */
+#define __HAL_FDCAN_TT_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) = (__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified FDCAN TT flag is set or not.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __FLAG__ FDCAN TT flag.
+  *         This parameter can be one of @arg FDCAN_TTflags
+  * @retval FlagStatus
+  */
+#define __HAL_FDCAN_TT_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) & (__FLAG__))
+
+/**
+  * @brief  Clear the specified FDCAN TT flags.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __FLAG__ specifies the TT flags to clear.
+  *         This parameter can be any combination of @arg FDCAN_TTflags
+  * @retval None
+  */
+#define __HAL_FDCAN_TT_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) = (__FLAG__))
+
+/** @brief  Check if the specified FDCAN TT interrupt source is enabled or disabled.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ specifies the FDCAN TT interrupt source to check.
+  *         This parameter can be a value of @arg FDCAN_TTInterrupts
+  * @retval ITStatus
+  */
+#define __HAL_FDCAN_TT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) & (__INTERRUPT__))
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FDCAN_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup FDCAN_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan);
+void              HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan);
+void              HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+/* Callbacks Register/UnRegister functions  ***********************************/
+HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, pFDCAN_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID);
+HAL_StatusTypeDef HAL_FDCAN_RegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ClockCalibrationCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxEventFifoCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo0CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo1CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferCompleteCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferAbortCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ErrorStatusCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_ScheduleSyncCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_TimeMarkCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_StopWatchCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_GlobalTimeCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @addtogroup FDCAN_Exported_Functions_Group2
+  * @{
+  */
+/* Configuration functions ****************************************************/
+HAL_StatusTypeDef HAL_FDCAN_ConfigClockCalibration(FDCAN_HandleTypeDef *hfdcan, FDCAN_ClkCalUnitTypeDef *sCcuConfig);
+uint32_t          HAL_FDCAN_GetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ResetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan);
+uint32_t          HAL_FDCAN_GetClockCalibrationCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t Counter);
+HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig);
+HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd, uint32_t NonMatchingExt, uint32_t RejectRemoteStd, uint32_t RejectRemoteExt);
+HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask);
+HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode);
+HAL_StatusTypeDef HAL_FDCAN_ConfigFifoWatermark(FDCAN_HandleTypeDef *hfdcan, uint32_t FIFO, uint32_t Watermark);
+HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue);
+HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler);
+HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation);
+HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
+uint16_t          HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod);
+HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
+uint16_t          HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter);
+HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan);
+/**
+  * @}
+  */
+
+/** @addtogroup FDCAN_Exported_Functions_Group3
+  * @{
+  */
+/* Control functions **********************************************************/
+HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData);
+HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxBuffer(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex);
+HAL_StatusTypeDef HAL_FDCAN_EnableTxBufferRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex);
+uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex);
+HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData);
+HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent);
+HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus);
+HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus);
+HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters);
+uint32_t HAL_FDCAN_IsRxBufferMessageAvailable(FDCAN_HandleTypeDef *hfdcan, uint32_t RxBufferIndex);
+uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex);
+uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo);
+uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan);
+uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan);
+/**
+  * @}
+  */
+
+/** @addtogroup FDCAN_Exported_Functions_Group4
+  * @{
+  */
+/* TT Configuration and control functions**************************************/
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigOperation(FDCAN_HandleTypeDef *hfdcan, FDCAN_TT_ConfigTypeDef *pTTParams);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigReferenceMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t IdType, uint32_t Identifier, uint32_t Payload);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigTrigger(FDCAN_HandleTypeDef *hfdcan, FDCAN_TriggerTypeDef *sTriggerConfig);
+HAL_StatusTypeDef HAL_FDCAN_TT_SetGlobalTime(FDCAN_HandleTypeDef *hfdcan, uint32_t TimePreset);
+HAL_StatusTypeDef HAL_FDCAN_TT_SetClockSynchronization(FDCAN_HandleTypeDef *hfdcan, uint32_t NewTURNumerator);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigStopWatch(FDCAN_HandleTypeDef *hfdcan, uint32_t Source, uint32_t Polarity);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigRegisterTimeMark(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeMarkSource, uint32_t TimeMarkValue, uint32_t RepeatFactor, uint32_t StartCycle);
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_SetNextIsGap(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_SetEndOfGap(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigExternalSyncPhase(FDCAN_HandleTypeDef *hfdcan, uint32_t TargetPhase);
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_GetOperationStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_TTOperationStatusTypeDef *TTOpStatus);
+/**
+  * @}
+  */
+
+/** @addtogroup FDCAN_Exported_Functions_Group5
+  * @{
+  */
+/* Interrupts management ******************************************************/
+HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t TTITList, uint32_t InterruptLine);
+HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes);
+HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs);
+HAL_StatusTypeDef HAL_FDCAN_TT_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveTTITs);
+HAL_StatusTypeDef HAL_FDCAN_TT_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveTTITs);
+void              HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan);
+/**
+  * @}
+  */
+
+/** @addtogroup FDCAN_Exported_Functions_Group6
+  * @{
+  */
+/* Callback functions *********************************************************/
+void HAL_FDCAN_ClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs);
+void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs);
+void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs);
+void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs);
+void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);
+void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);
+void HAL_FDCAN_RxBufferNewMessageCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs);
+void HAL_FDCAN_TT_ScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs);
+void HAL_FDCAN_TT_TimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs);
+void HAL_FDCAN_TT_StopWatchCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount);
+void HAL_FDCAN_TT_GlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs);
+/**
+  * @}
+  */
+
+/** @addtogroup FDCAN_Exported_Functions_Group7
+  * @{
+  */
+/* Peripheral State functions *************************************************/
+uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan);
+HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup FDCAN_Private_Types FDCAN Private Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup FDCAN_Private_Variables FDCAN Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup FDCAN_Private_Constants FDCAN Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FDCAN_Private_Macros FDCAN Private Macros
+  * @{
+  */
+#define IS_FDCAN_FRAME_FORMAT(FORMAT) (((FORMAT) == FDCAN_FRAME_CLASSIC  ) || \
+                                       ((FORMAT) == FDCAN_FRAME_FD_NO_BRS) || \
+                                       ((FORMAT) == FDCAN_FRAME_FD_BRS   ))
+#define IS_FDCAN_MODE(MODE) (((MODE) == FDCAN_MODE_NORMAL              ) || \
+                             ((MODE) == FDCAN_MODE_RESTRICTED_OPERATION) || \
+                             ((MODE) == FDCAN_MODE_BUS_MONITORING      ) || \
+                             ((MODE) == FDCAN_MODE_INTERNAL_LOOPBACK   ) || \
+                             ((MODE) == FDCAN_MODE_EXTERNAL_LOOPBACK   ))
+
+#define IS_FDCAN_CLOCK_CALIBRATION(CALIBRATION) (((CALIBRATION) == FDCAN_CLOCK_CALIBRATION_DISABLE) || \
+                                                 ((CALIBRATION) == FDCAN_CLOCK_CALIBRATION_ENABLE ))
+
+#define IS_FDCAN_CKDIV(CKDIV) (((CKDIV) == FDCAN_CLOCK_DIV1 ) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV2 ) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV4 ) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV6 ) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV8 ) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV10) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV12) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV14) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV16) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV18) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV20) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV22) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV24) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV26) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV28) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV30))
+#define IS_FDCAN_NOMINAL_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 512U))
+#define IS_FDCAN_NOMINAL_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 128U))
+#define IS_FDCAN_NOMINAL_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 256U))
+#define IS_FDCAN_NOMINAL_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 128U))
+#define IS_FDCAN_DATA_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 32U))
+#define IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 16U))
+#define IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 32U))
+#define IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 16U))
+#define IS_FDCAN_MAX_VALUE(VALUE, MAX) ((VALUE) <= (MAX))
+#define IS_FDCAN_MIN_VALUE(VALUE, MIN) ((VALUE) >= (MIN))
+#define IS_FDCAN_DATA_SIZE(SIZE) (((SIZE) == FDCAN_DATA_BYTES_8 ) || \
+                                  ((SIZE) == FDCAN_DATA_BYTES_12) || \
+                                  ((SIZE) == FDCAN_DATA_BYTES_16) || \
+                                  ((SIZE) == FDCAN_DATA_BYTES_20) || \
+                                  ((SIZE) == FDCAN_DATA_BYTES_24) || \
+                                  ((SIZE) == FDCAN_DATA_BYTES_32) || \
+                                  ((SIZE) == FDCAN_DATA_BYTES_48) || \
+                                  ((SIZE) == FDCAN_DATA_BYTES_64))
+#define IS_FDCAN_TX_FIFO_QUEUE_MODE(MODE) (((MODE) == FDCAN_TX_FIFO_OPERATION ) || \
+                                           ((MODE) == FDCAN_TX_QUEUE_OPERATION))
+#define IS_FDCAN_ID_TYPE(ID_TYPE) (((ID_TYPE) == FDCAN_STANDARD_ID) || \
+                                   ((ID_TYPE) == FDCAN_EXTENDED_ID))
+#define IS_FDCAN_FILTER_CFG(CONFIG) (((CONFIG) == FDCAN_FILTER_DISABLE      ) || \
+                                     ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0   ) || \
+                                     ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1   ) || \
+                                     ((CONFIG) == FDCAN_FILTER_REJECT       ) || \
+                                     ((CONFIG) == FDCAN_FILTER_HP           ) || \
+                                     ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0_HP) || \
+                                     ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1_HP) || \
+                                     ((CONFIG) == FDCAN_FILTER_TO_RXBUFFER  ))
+#define IS_FDCAN_TX_LOCATION(LOCATION) (((LOCATION) == FDCAN_TX_BUFFER0 ) || ((LOCATION) == FDCAN_TX_BUFFER1 ) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER2 ) || ((LOCATION) == FDCAN_TX_BUFFER3 ) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER4 ) || ((LOCATION) == FDCAN_TX_BUFFER5 ) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER6 ) || ((LOCATION) == FDCAN_TX_BUFFER7 ) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER8 ) || ((LOCATION) == FDCAN_TX_BUFFER9 ) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER10) || ((LOCATION) == FDCAN_TX_BUFFER11) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER12) || ((LOCATION) == FDCAN_TX_BUFFER13) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER14) || ((LOCATION) == FDCAN_TX_BUFFER15) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER16) || ((LOCATION) == FDCAN_TX_BUFFER17) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER18) || ((LOCATION) == FDCAN_TX_BUFFER19) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER20) || ((LOCATION) == FDCAN_TX_BUFFER21) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER22) || ((LOCATION) == FDCAN_TX_BUFFER23) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER24) || ((LOCATION) == FDCAN_TX_BUFFER25) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER26) || ((LOCATION) == FDCAN_TX_BUFFER27) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER28) || ((LOCATION) == FDCAN_TX_BUFFER29) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER30) || ((LOCATION) == FDCAN_TX_BUFFER31))
+#define IS_FDCAN_RX_FIFO(FIFO) (((FIFO) == FDCAN_RX_FIFO0) || \
+                                ((FIFO) == FDCAN_RX_FIFO1))
+#define IS_FDCAN_RX_FIFO_MODE(MODE) (((MODE) == FDCAN_RX_FIFO_BLOCKING ) || \
+                                     ((MODE) == FDCAN_RX_FIFO_OVERWRITE))
+#define IS_FDCAN_STD_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE) || \
+                                        ((TYPE) == FDCAN_FILTER_DUAL ) || \
+                                        ((TYPE) == FDCAN_FILTER_MASK ))
+#define IS_FDCAN_EXT_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE        ) || \
+                                        ((TYPE) == FDCAN_FILTER_DUAL         ) || \
+                                        ((TYPE) == FDCAN_FILTER_MASK         ) || \
+                                        ((TYPE) == FDCAN_FILTER_RANGE_NO_EIDM))
+#define IS_FDCAN_FRAME_TYPE(TYPE) (((TYPE) == FDCAN_DATA_FRAME  ) || \
+                                   ((TYPE) == FDCAN_REMOTE_FRAME))
+#define IS_FDCAN_DLC(DLC) (((DLC) == FDCAN_DLC_BYTES_0 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_1 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_2 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_3 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_4 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_5 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_6 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_7 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_8 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_12) || \
+                           ((DLC) == FDCAN_DLC_BYTES_16) || \
+                           ((DLC) == FDCAN_DLC_BYTES_20) || \
+                           ((DLC) == FDCAN_DLC_BYTES_24) || \
+                           ((DLC) == FDCAN_DLC_BYTES_32) || \
+                           ((DLC) == FDCAN_DLC_BYTES_48) || \
+                           ((DLC) == FDCAN_DLC_BYTES_64))
+#define IS_FDCAN_ESI(ESI) (((ESI) == FDCAN_ESI_ACTIVE ) || \
+                           ((ESI) == FDCAN_ESI_PASSIVE))
+#define IS_FDCAN_BRS(BRS) (((BRS) == FDCAN_BRS_OFF) || \
+                           ((BRS) == FDCAN_BRS_ON ))
+#define IS_FDCAN_FDF(FDF) (((FDF) == FDCAN_CLASSIC_CAN) || \
+                           ((FDF) == FDCAN_FD_CAN     ))
+#define IS_FDCAN_EFC(EFC) (((EFC) == FDCAN_NO_TX_EVENTS   ) || \
+                           ((EFC) == FDCAN_STORE_TX_EVENTS))
+#define IS_FDCAN_IT(IT) (((IT) & ~(FDCAN_IR_MASK | CCU_IR_MASK)) == 0U)
+#define IS_FDCAN_TT_IT(IT) (((IT) & 0xFFF80000U) == 0U)
+#define IS_FDCAN_FIFO_WATERMARK(FIFO) (((FIFO) == FDCAN_CFG_TX_EVENT_FIFO) || \
+                                       ((FIFO) == FDCAN_CFG_RX_FIFO0     ) || \
+                                       ((FIFO) == FDCAN_CFG_RX_FIFO1     ))
+#define IS_FDCAN_NON_MATCHING(DESTINATION) (((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO0) || \
+                                            ((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO1) || \
+                                            ((DESTINATION) == FDCAN_REJECT            ))
+#define IS_FDCAN_REJECT_REMOTE(DESTINATION) (((DESTINATION) == FDCAN_FILTER_REMOTE) || \
+                                             ((DESTINATION) == FDCAN_REJECT_REMOTE))
+#define IS_FDCAN_IT_LINE(IT_LINE) (((IT_LINE) == FDCAN_INTERRUPT_LINE0) || \
+                                   ((IT_LINE) == FDCAN_INTERRUPT_LINE1))
+#define IS_FDCAN_TIMESTAMP(OPERATION) (((OPERATION) == FDCAN_TIMESTAMP_INTERNAL) || \
+                                       ((OPERATION) == FDCAN_TIMESTAMP_EXTERNAL))
+#define IS_FDCAN_TIMESTAMP_PRESCALER(PRESCALER) (((PRESCALER) == FDCAN_TIMESTAMP_PRESC_1 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_2 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_3 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_4 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_5 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_6 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_7 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_8 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_9 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_10) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_11) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_12) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_13) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_14) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_15) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_16))
+#define IS_FDCAN_TIMEOUT(OPERATION) (((OPERATION) == FDCAN_TIMEOUT_CONTINUOUS   ) || \
+                                     ((OPERATION) == FDCAN_TIMEOUT_TX_EVENT_FIFO) || \
+                                     ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO0     ) || \
+                                     ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO1     ))
+#define IS_FDCAN_CALIBRATION_FIELD_LENGTH(LENGTH) (((LENGTH) == FDCAN_CALIB_FIELD_LENGTH_32) || \
+                                                   ((LENGTH) == FDCAN_CALIB_FIELD_LENGTH_64))
+#define IS_FDCAN_CALIBRATION_COUNTER(COUNTER) (((COUNTER) == FDCAN_CALIB_TIME_QUANTA_COUNTER ) || \
+                                               ((COUNTER) == FDCAN_CALIB_CLOCK_PERIOD_COUNTER) || \
+                                               ((COUNTER) == FDCAN_CALIB_WATCHDOG_COUNTER    ))
+#define IS_FDCAN_TT_REFERENCE_MESSAGE_PAYLOAD(PAYLOAD) (((PAYLOAD) == FDCAN_TT_REF_MESSAGE_NO_PAYLOAD ) || \
+                                                        ((PAYLOAD) == FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD))
+#define IS_FDCAN_TT_REPEAT_FACTOR(FACTOR) (((FACTOR) == FDCAN_TT_REPEAT_EVERY_CYCLE     ) || \
+                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_2ND_CYCLE ) || \
+                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_4TH_CYCLE ) || \
+                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_8TH_CYCLE ) || \
+                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_16TH_CYCLE) || \
+                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_32ND_CYCLE) || \
+                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_64TH_CYCLE))
+#define IS_FDCAN_TT_TRIGGER_TYPE(TYPE) (((TYPE) == FDCAN_TT_TX_REF_TRIGGER        ) || \
+                                        ((TYPE) == FDCAN_TT_TX_REF_TRIGGER_GAP    ) || \
+                                        ((TYPE) == FDCAN_TT_TX_TRIGGER_SINGLE     ) || \
+                                        ((TYPE) == FDCAN_TT_TX_TRIGGER_CONTINUOUS ) || \
+                                        ((TYPE) == FDCAN_TT_TX_TRIGGER_ARBITRATION) || \
+                                        ((TYPE) == FDCAN_TT_TX_TRIGGER_MERGED     ) || \
+                                        ((TYPE) == FDCAN_TT_WATCH_TRIGGER         ) || \
+                                        ((TYPE) == FDCAN_TT_WATCH_TRIGGER_GAP     ) || \
+                                        ((TYPE) == FDCAN_TT_RX_TRIGGER            ) || \
+                                        ((TYPE) == FDCAN_TT_TIME_BASE_TRIGGER     ) || \
+                                        ((TYPE) == FDCAN_TT_END_OF_LIST           ))
+#define IS_FDCAN_TT_TM_EVENT_INTERNAL(EVENT) (((EVENT) == FDCAN_TT_TM_NO_INTERNAL_EVENT ) || \
+                                              ((EVENT) == FDCAN_TT_TM_GEN_INTERNAL_EVENT))
+#define IS_FDCAN_TT_TM_EVENT_EXTERNAL(EVENT) (((EVENT) == FDCAN_TT_TM_NO_EXTERNAL_EVENT ) || \
+                                              ((EVENT) == FDCAN_TT_TM_GEN_EXTERNAL_EVENT))
+#define IS_FDCAN_OPERATION_MODE(MODE) (((MODE) == FDCAN_TT_COMMUNICATION_LEVEL1 ) || \
+                                       ((MODE) == FDCAN_TT_COMMUNICATION_LEVEL2 ) || \
+                                       ((MODE) == FDCAN_TT_COMMUNICATION_LEVEL0 ))
+#define IS_FDCAN_TT_OPERATION(OPERATION) (((OPERATION) == FDCAN_STRICTLY_TT_OPERATION      ) || \
+                                          ((OPERATION) == FDCAN_EXT_EVT_SYNC_TT_OPERATION))
+#define IS_FDCAN_TT_TIME_MASTER(FUNCTION) (((FUNCTION) == FDCAN_TT_SLAVE           ) || \
+                                           ((FUNCTION) == FDCAN_TT_POTENTIAL_MASTER))
+#define IS_FDCAN_TT_EXTERNAL_CLK_SYNC(SYNC) (((SYNC) == FDCAN_TT_EXT_CLK_SYNC_DISABLE) || \
+                                             ((SYNC) == FDCAN_TT_EXT_CLK_SYNC_ENABLE ))
+#define IS_FDCAN_TT_GLOBAL_TIME_FILTERING(FILTERING) (((FILTERING) == FDCAN_TT_GLOB_TIME_FILT_DISABLE) || \
+                                                      ((FILTERING) == FDCAN_TT_GLOB_TIME_FILT_ENABLE ))
+#define IS_FDCAN_TT_AUTO_CLK_CALIBRATION(CALIBRATION) (((CALIBRATION) == FDCAN_TT_AUTO_CLK_CALIB_DISABLE) || \
+                                                       ((CALIBRATION) == FDCAN_TT_AUTO_CLK_CALIB_ENABLE ))
+#define IS_FDCAN_TT_EVENT_TRIGGER_POLARITY(POLARITY) (((POLARITY) == FDCAN_TT_EVT_TRIG_POL_RISING ) || \
+                                                      ((POLARITY) == FDCAN_TT_EVT_TRIG_POL_FALLING))
+#define IS_FDCAN_TT_BASIC_CYCLES_NUMBER(NUMBER) (((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_1 ) || \
+                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_2 ) || \
+                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_4 ) || \
+                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_8 ) || \
+                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_16) || \
+                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_32) || \
+                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_64))
+#define IS_FDCAN_TT_CYCLE_START_SYNC(SYNC) (((SYNC) == FDCAN_TT_NO_SYNC_PULSE         ) || \
+                                            ((SYNC) == FDCAN_TT_SYNC_BASIC_CYCLE_START) || \
+                                            ((SYNC) == FDCAN_TT_SYNC_MATRIX_START     ))
+#define IS_FDCAN_TT_TX_ENABLE_WINDOW(NTU) (((NTU) >= 1U) && ((NTU) <= 16U))
+#define IS_FDCAN_TT_TUR_NUMERATOR(NUMERATOR) (((NUMERATOR) >= 0x10000U) && ((NUMERATOR) <= 0x1FFFFU))
+#define IS_FDCAN_TT_TUR_DENOMINATOR(DENOMINATOR) (((DENOMINATOR) >= 0x0001U) && ((DENOMINATOR) <= 0x3FFFU))
+#define IS_FDCAN_TT_TUR_LEVEL_1(NC,DC) ((NC) >= (4U * (DC)))
+#define IS_FDCAN_TT_TUR_LEVEL_0_2(NC,DC) ((NC) >= (8U * (DC)))
+#define IS_FDCAN_TT_STOP_WATCH_TRIGGER(TRIGGER) (((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_0) || \
+                                                 ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_1) || \
+                                                 ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_2) || \
+                                                 ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_3))
+#define IS_FDCAN_TT_EVENT_TRIGGER(TRIGGER) (((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_0) || \
+                                            ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_1) || \
+                                            ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_2) || \
+                                            ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_3))
+#define IS_FDCAN_TT_TIME_PRESET(TIME) (((TIME) <= 0xFFFFU) && ((TIME) != 0x8000U))
+#define IS_FDCAN_TT_STOP_WATCH_SOURCE(SOURCE) (((SOURCE) == FDCAN_TT_STOP_WATCH_DISABLED   ) || \
+                                               ((SOURCE) == FDCAN_TT_STOP_WATCH_CYCLE_TIME ) || \
+                                               ((SOURCE) == FDCAN_TT_STOP_WATCH_LOCAL_TIME ) || \
+                                               ((SOURCE) == FDCAN_TT_STOP_WATCH_GLOBAL_TIME))
+#define IS_FDCAN_TT_STOP_WATCH_POLARITY(POLARITY) (((POLARITY) == FDCAN_TT_STOP_WATCH_RISING ) || \
+                                                   ((POLARITY) == FDCAN_TT_STOP_WATCH_FALLING))
+#define IS_FDCAN_TT_REGISTER_TIME_MARK_SOURCE(SOURCE) (((SOURCE) == FDCAN_TT_REG_TIMEMARK_DIABLED ) || \
+                                                       ((SOURCE) == FDCAN_TT_REG_TIMEMARK_CYC_TIME) || \
+                                                       ((SOURCE) == FDCAN_TT_REG_TIMEMARK_LOC_TIME) || \
+                                                       ((SOURCE) == FDCAN_TT_REG_TIMEMARK_GLO_TIME))
+/**
+  * @}
+  */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup FDCAN_Private_Functions_Prototypes FDCAN Private Functions Prototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup FDCAN_Private_Functions FDCAN Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_FDCAN_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h
new file mode 100644
index 00000000..6bda249e
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h
@@ -0,0 +1,829 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_flash.h
+  * @author  MCD Application Team
+  * @brief   Header file of FLASH HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_FLASH_H
+#define STM32H7xx_HAL_FLASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FLASH
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Types FLASH Exported Types
+  * @{
+  */
+
+/**
+  * @brief  FLASH Procedure structure definition
+  */
+typedef enum
+{
+  FLASH_PROC_NONE = 0U,
+  FLASH_PROC_SECTERASE_BANK1,
+  FLASH_PROC_MASSERASE_BANK1,
+  FLASH_PROC_PROGRAM_BANK1,
+  FLASH_PROC_SECTERASE_BANK2,
+  FLASH_PROC_MASSERASE_BANK2,
+  FLASH_PROC_PROGRAM_BANK2,
+  FLASH_PROC_ALLBANK_MASSERASE
+} FLASH_ProcedureTypeDef;
+
+
+/**
+  * @brief  FLASH handle Structure definition
+  */
+typedef struct
+{
+  __IO FLASH_ProcedureTypeDef ProcedureOnGoing;   /*!< Internal variable to indicate which procedure is ongoing or not in IT context */
+
+  __IO uint32_t               NbSectorsToErase;   /*!< Internal variable to save the remaining sectors to erase in IT context        */
+
+  __IO uint32_t               VoltageForErase;    /*!< Internal variable to provide voltage range selected by user in IT context     */
+
+  __IO uint32_t               Sector;             /*!< Internal variable to define the current sector which is erasing               */
+
+  __IO uint32_t               Address;            /*!< Internal variable to save address selected for program                        */
+
+  HAL_LockTypeDef             Lock;               /*!< FLASH locking object                                                          */
+
+  __IO uint32_t               ErrorCode;          /*!< FLASH error code                                                              */
+
+}FLASH_ProcessTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
+  * @{
+  */
+
+/** @defgroup FLASH_Error_Code FLASH Error Code
+  * @brief    FLASH Error Code
+  * @{
+  */
+#define HAL_FLASH_ERROR_NONE         0x00000000U               /*!< No error                              */
+
+#define HAL_FLASH_ERROR_WRP          FLASH_FLAG_WRPERR         /*!< Write Protection Error                */
+#define HAL_FLASH_ERROR_PGS          FLASH_FLAG_PGSERR         /*!< Program Sequence Error                */
+#define HAL_FLASH_ERROR_STRB         FLASH_FLAG_STRBERR        /*!< Strobe Error                          */
+#define HAL_FLASH_ERROR_INC          FLASH_FLAG_INCERR         /*!< Inconsistency Error                   */
+#if defined (FLASH_SR_OPERR)
+#define HAL_FLASH_ERROR_OPE          FLASH_FLAG_OPERR          /*!< Operation Error                       */
+#endif /* FLASH_SR_OPERR */
+#define HAL_FLASH_ERROR_RDP          FLASH_FLAG_RDPERR         /*!< Read Protection Error                 */
+#define HAL_FLASH_ERROR_RDS          FLASH_FLAG_RDSERR         /*!< Read Secured Error                    */
+#define HAL_FLASH_ERROR_SNECC        FLASH_FLAG_SNECCERR       /*!< ECC Single Correction Error           */
+#define HAL_FLASH_ERROR_DBECC        FLASH_FLAG_DBECCERR       /*!< ECC Double Detection Error            */
+#define HAL_FLASH_ERROR_CRCRD        FLASH_FLAG_CRCRDERR       /*!< CRC Read Error                        */
+
+#define HAL_FLASH_ERROR_WRP_BANK1    FLASH_FLAG_WRPERR_BANK1   /*!< Write Protection Error on Bank 1      */
+#define HAL_FLASH_ERROR_PGS_BANK1    FLASH_FLAG_PGSERR_BANK1   /*!< Program Sequence Error on Bank 1      */
+#define HAL_FLASH_ERROR_STRB_BANK1   FLASH_FLAG_STRBERR_BANK1  /*!< Strobe Error on Bank 1                */
+#define HAL_FLASH_ERROR_INC_BANK1    FLASH_FLAG_INCERR_BANK1   /*!< Inconsistency Error on Bank 1         */
+#if defined (FLASH_SR_OPERR)
+#define HAL_FLASH_ERROR_OPE_BANK1    FLASH_FLAG_OPERR_BANK1    /*!< Operation Error on Bank 1             */
+#endif /* FLASH_SR_OPERR */
+#define HAL_FLASH_ERROR_RDP_BANK1    FLASH_FLAG_RDPERR_BANK1   /*!< Read Protection Error on Bank 1       */
+#define HAL_FLASH_ERROR_RDS_BANK1    FLASH_FLAG_RDSERR_BANK1   /*!< Read Secured Error on Bank 1          */
+#define HAL_FLASH_ERROR_SNECC_BANK1  FLASH_FLAG_SNECCERR_BANK1 /*!< ECC Single Correction Error on Bank 1 */
+#define HAL_FLASH_ERROR_DBECC_BANK1  FLASH_FLAG_DBECCERR_BANK1 /*!< ECC Double Detection Error on Bank 1  */
+#define HAL_FLASH_ERROR_CRCRD_BANK1  FLASH_FLAG_CRCRDERR_BANK1 /*!< CRC Read Error on Bank1               */
+
+#define HAL_FLASH_ERROR_WRP_BANK2    FLASH_FLAG_WRPERR_BANK2    /*!< Write Protection Error on Bank 2      */
+#define HAL_FLASH_ERROR_PGS_BANK2    FLASH_FLAG_PGSERR_BANK2    /*!< Program Sequence Error on Bank 2      */
+#define HAL_FLASH_ERROR_STRB_BANK2   FLASH_FLAG_STRBERR_BANK2   /*!< Strobe Error on Bank 2                */
+#define HAL_FLASH_ERROR_INC_BANK2    FLASH_FLAG_INCERR_BANK2    /*!< Inconsistency Error on Bank 2         */
+#if defined (FLASH_SR_OPERR)
+#define HAL_FLASH_ERROR_OPE_BANK2    FLASH_FLAG_OPERR_BANK2     /*!< Operation Error on Bank 2             */
+#endif /* FLASH_SR_OPERR */
+#define HAL_FLASH_ERROR_RDP_BANK2    FLASH_FLAG_RDPERR_BANK2    /*!< Read Protection Error on Bank 2       */
+#define HAL_FLASH_ERROR_RDS_BANK2    FLASH_FLAG_RDSERR_BANK2    /*!< Read Secured Error on Bank 2          */
+#define HAL_FLASH_ERROR_SNECC_BANK2  FLASH_FLAG_SNECCERR_BANK2  /*!< ECC Single Correction Error on Bank 2 */
+#define HAL_FLASH_ERROR_DBECC_BANK2  FLASH_FLAG_DBECCERR_BANK2  /*!< ECC Double Detection Error on Bank 2  */
+#define HAL_FLASH_ERROR_CRCRD_BANK2  FLASH_FLAG_CRCRDERR_BANK2  /*!< CRC Read Error on Bank2               */
+
+#define HAL_FLASH_ERROR_OB_CHANGE    FLASH_OPTSR_OPTCHANGEERR   /*!< Option Byte Change Error              */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Type_Program FLASH Type Program
+  * @{
+  */
+#define FLASH_TYPEPROGRAM_FLASHWORD  0x01U        /*!< Program a flash word at a specified address */
+#if defined (FLASH_OPTCR_PG_OTP)
+#define FLASH_TYPEPROGRAM_OTPWORD    0x02U        /*!< Program an OTP word at a specified address  */
+#endif /* FLASH_OPTCR_PG_OTP */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Flag_definition FLASH Flag definition
+  * @brief Flag definition
+  * @{
+  */
+#define FLASH_FLAG_BSY                     FLASH_SR_BSY             /*!< FLASH Busy flag */
+#define FLASH_FLAG_WBNE                    FLASH_SR_WBNE            /*!< Write Buffer Not Empty flag */
+#define FLASH_FLAG_QW                      FLASH_SR_QW              /*!< Wait Queue on flag */
+#define FLASH_FLAG_CRC_BUSY                FLASH_SR_CRC_BUSY        /*!< CRC Busy flag */
+#define FLASH_FLAG_EOP                     FLASH_SR_EOP             /*!< End Of Program on flag */
+#define FLASH_FLAG_WRPERR                  FLASH_SR_WRPERR          /*!< Write Protection Error on flag */
+#define FLASH_FLAG_PGSERR                  FLASH_SR_PGSERR          /*!< Program Sequence Error on flag */
+#define FLASH_FLAG_STRBERR                 FLASH_SR_STRBERR         /*!< Strobe Error flag */
+#define FLASH_FLAG_INCERR                  FLASH_SR_INCERR          /*!< Inconsistency Error on flag */
+#if defined (FLASH_SR_OPERR)
+#define FLASH_FLAG_OPERR                   FLASH_SR_OPERR           /*!< Operation Error on flag */
+#endif /* FLASH_SR_OPERR */
+#define FLASH_FLAG_RDPERR                  FLASH_SR_RDPERR          /*!< Read Protection Error on flag */
+#define FLASH_FLAG_RDSERR                  FLASH_SR_RDSERR          /*!< Read Secured Error on flag */
+#define FLASH_FLAG_SNECCERR                FLASH_SR_SNECCERR        /*!< Single ECC Error Correction on flag */
+#define FLASH_FLAG_DBECCERR                FLASH_SR_DBECCERR        /*!< Double Detection ECC Error on flag */
+#define FLASH_FLAG_CRCEND                  FLASH_SR_CRCEND          /*!< CRC End of Calculation flag */
+#define FLASH_FLAG_CRCRDERR                FLASH_SR_CRCRDERR        /*!< CRC Read Error on bank flag */
+
+#define FLASH_FLAG_BSY_BANK1               FLASH_SR_BSY             /*!< FLASH Bank 1 Busy flag */
+#define FLASH_FLAG_WBNE_BANK1              FLASH_SR_WBNE            /*!< Write Buffer Not Empty on Bank 1 flag */
+#define FLASH_FLAG_QW_BANK1                FLASH_SR_QW              /*!< Wait Queue on Bank 1 flag */
+#define FLASH_FLAG_CRC_BUSY_BANK1          FLASH_SR_CRC_BUSY        /*!< CRC Busy on Bank 1 flag */
+#define FLASH_FLAG_EOP_BANK1               FLASH_SR_EOP             /*!< End Of Program on Bank 1 flag */
+#define FLASH_FLAG_WRPERR_BANK1            FLASH_SR_WRPERR          /*!< Write Protection Error on Bank 1 flag */
+#define FLASH_FLAG_PGSERR_BANK1            FLASH_SR_PGSERR          /*!< Program Sequence Error on Bank 1 flag */
+#define FLASH_FLAG_STRBERR_BANK1           FLASH_SR_STRBERR         /*!< Strobe Error on Bank 1 flag */
+#define FLASH_FLAG_INCERR_BANK1            FLASH_SR_INCERR          /*!< Inconsistency Error on Bank 1 flag */
+#if defined (FLASH_SR_OPERR)
+#define FLASH_FLAG_OPERR_BANK1             FLASH_SR_OPERR           /*!< Operation Error on Bank 1 flag */
+#endif /* FLASH_SR_OPERR */
+#define FLASH_FLAG_RDPERR_BANK1            FLASH_SR_RDPERR          /*!< Read Protection Error on Bank 1 flag */
+#define FLASH_FLAG_RDSERR_BANK1            FLASH_SR_RDSERR          /*!< Read Secured Error on Bank 1 flag */
+#define FLASH_FLAG_SNECCERR_BANK1          FLASH_SR_SNECCERR        /*!< Single ECC Error Correction on Bank 1 flag */
+#define FLASH_FLAG_DBECCERR_BANK1          FLASH_SR_DBECCERR        /*!< Double Detection ECC Error on Bank 1 flag */
+#define FLASH_FLAG_CRCEND_BANK1            FLASH_SR_CRCEND          /*!< CRC End of Calculation on Bank 1 flag */
+#define FLASH_FLAG_CRCRDERR_BANK1          FLASH_SR_CRCRDERR        /*!< CRC Read error on Bank 1 flag */
+
+#if defined (FLASH_SR_OPERR)
+#define FLASH_FLAG_ALL_ERRORS_BANK1       (FLASH_FLAG_WRPERR_BANK1   | FLASH_FLAG_PGSERR_BANK1   | \
+                                           FLASH_FLAG_STRBERR_BANK1  | FLASH_FLAG_INCERR_BANK1   | \
+                                           FLASH_FLAG_OPERR_BANK1    | FLASH_FLAG_RDPERR_BANK1   | \
+                                           FLASH_FLAG_RDSERR_BANK1   | FLASH_FLAG_SNECCERR_BANK1 | \
+                                           FLASH_FLAG_DBECCERR_BANK1 | FLASH_FLAG_CRCRDERR_BANK1) /*!< All Bank 1 error flags */
+#else
+#define FLASH_FLAG_ALL_ERRORS_BANK1       (FLASH_FLAG_WRPERR_BANK1   | FLASH_FLAG_PGSERR_BANK1   | \
+                                           FLASH_FLAG_STRBERR_BANK1  | FLASH_FLAG_INCERR_BANK1   | \
+                                           FLASH_FLAG_RDPERR_BANK1   | FLASH_FLAG_RDSERR_BANK1   | \
+                                           FLASH_FLAG_SNECCERR_BANK1 | FLASH_FLAG_DBECCERR_BANK1 | \
+                                           FLASH_FLAG_CRCRDERR_BANK1) /*!< All Bank 1 error flags */
+#endif /* FLASH_SR_OPERR */
+
+#define FLASH_FLAG_ALL_BANK1              (FLASH_FLAG_BSY_BANK1      | FLASH_FLAG_WBNE_BANK1     | \
+                                           FLASH_FLAG_QW_BANK1       | FLASH_FLAG_CRC_BUSY_BANK1 | \
+                                           FLASH_FLAG_EOP_BANK1      | FLASH_FLAG_CRCEND_BANK1   | \
+                                           FLASH_FLAG_ALL_ERRORS_BANK1) /*!< All Bank 1 flags */
+
+#define FLASH_FLAG_BSY_BANK2               (FLASH_SR_BSY      | 0x80000000U)        /*!< FLASH Bank 2 Busy flag */
+#define FLASH_FLAG_WBNE_BANK2              (FLASH_SR_WBNE     | 0x80000000U)        /*!< Write Buffer Not Empty on Bank 2 flag */
+#define FLASH_FLAG_QW_BANK2                (FLASH_SR_QW       | 0x80000000U)        /*!< Wait Queue on Bank 2 flag */
+#define FLASH_FLAG_CRC_BUSY_BANK2          (FLASH_SR_CRC_BUSY | 0x80000000U)        /*!< CRC Busy on Bank 2 flag */
+#define FLASH_FLAG_EOP_BANK2               (FLASH_SR_EOP      | 0x80000000U)        /*!< End Of Program on Bank 2 flag */
+#define FLASH_FLAG_WRPERR_BANK2            (FLASH_SR_WRPERR   | 0x80000000U)        /*!< Write Protection Error on Bank 2 flag */
+#define FLASH_FLAG_PGSERR_BANK2            (FLASH_SR_PGSERR   | 0x80000000U)        /*!< Program Sequence Error on Bank 2 flag */
+#define FLASH_FLAG_STRBERR_BANK2           (FLASH_SR_STRBERR  | 0x80000000U)        /*!< Strobe Error on Bank 2 flag */
+#define FLASH_FLAG_INCERR_BANK2            (FLASH_SR_INCERR   | 0x80000000U)        /*!< Inconsistency Error on Bank 2 flag */
+#if defined (FLASH_SR_OPERR)
+#define FLASH_FLAG_OPERR_BANK2             (FLASH_SR_OPERR    | 0x80000000U)        /*!< Operation Error on Bank 2 flag */
+#endif /* FLASH_SR_OPERR */
+#define FLASH_FLAG_RDPERR_BANK2            (FLASH_SR_RDPERR   | 0x80000000U)        /*!< Read Protection Error on Bank 2 flag */
+#define FLASH_FLAG_RDSERR_BANK2            (FLASH_SR_RDSERR   | 0x80000000U)        /*!< Read Secured Error on Bank 2 flag */
+#define FLASH_FLAG_SNECCERR_BANK2          (FLASH_SR_SNECCERR | 0x80000000U)        /*!< Single ECC Error Correction on Bank 2 flag */
+#define FLASH_FLAG_DBECCERR_BANK2          (FLASH_SR_DBECCERR | 0x80000000U)        /*!< Double Detection ECC Error on Bank 2 flag */
+#define FLASH_FLAG_CRCEND_BANK2            (FLASH_SR_CRCEND   | 0x80000000U)        /*!< CRC End of Calculation on Bank 2 flag */
+#define FLASH_FLAG_CRCRDERR_BANK2          (FLASH_SR_CRCRDERR | 0x80000000U)        /*!< CRC Read error on Bank 2 flag */
+
+#if defined (FLASH_SR_OPERR)
+#define FLASH_FLAG_ALL_ERRORS_BANK2       (FLASH_FLAG_WRPERR_BANK2   | FLASH_FLAG_PGSERR_BANK2   | \
+                                           FLASH_FLAG_STRBERR_BANK2  | FLASH_FLAG_INCERR_BANK2   | \
+                                           FLASH_FLAG_OPERR_BANK2    | FLASH_FLAG_RDPERR_BANK2   | \
+                                           FLASH_FLAG_RDSERR_BANK2   | FLASH_FLAG_SNECCERR_BANK2 | \
+                                           FLASH_FLAG_DBECCERR_BANK2 | FLASH_FLAG_CRCRDERR_BANK2) /*!< All Bank 2 error flags */
+#else
+#define FLASH_FLAG_ALL_ERRORS_BANK2       (FLASH_FLAG_WRPERR_BANK2   | FLASH_FLAG_PGSERR_BANK2   | \
+                                           FLASH_FLAG_STRBERR_BANK2  | FLASH_FLAG_INCERR_BANK2   | \
+                                           FLASH_FLAG_RDPERR_BANK2   | FLASH_FLAG_RDSERR_BANK2   | \
+                                           FLASH_FLAG_SNECCERR_BANK2 | FLASH_FLAG_DBECCERR_BANK2 | \
+                                           FLASH_FLAG_CRCRDERR_BANK2) /*!< All Bank 2 error flags */
+#endif /* FLASH_SR_OPERR */
+
+#define FLASH_FLAG_ALL_BANK2              (FLASH_FLAG_BSY_BANK2      | FLASH_FLAG_WBNE_BANK2     | \
+                                           FLASH_FLAG_QW_BANK2       | FLASH_FLAG_CRC_BUSY_BANK2 | \
+                                           FLASH_FLAG_EOP_BANK2      | FLASH_FLAG_CRCEND_BANK2   | \
+                                           FLASH_FLAG_ALL_ERRORS_BANK2) /*!< All Bank 2 flags */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition
+  * @brief FLASH Interrupt definition
+  * @{
+  */
+#define FLASH_IT_EOP_BANK1                  FLASH_CR_EOPIE       /*!< End of FLASH Bank 1 Operation Interrupt source */
+#define FLASH_IT_WRPERR_BANK1               FLASH_CR_WRPERRIE    /*!< Write Protection Error on Bank 1 Interrupt source */
+#define FLASH_IT_PGSERR_BANK1               FLASH_CR_PGSERRIE    /*!< Program Sequence Error on Bank 1 Interrupt source */
+#define FLASH_IT_STRBERR_BANK1              FLASH_CR_STRBERRIE   /*!< Strobe Error on Bank 1 Interrupt source */
+#define FLASH_IT_INCERR_BANK1               FLASH_CR_INCERRIE    /*!< Inconsistency Error on Bank 1 Interrupt source */
+#if defined (FLASH_CR_OPERRIE)
+#define FLASH_IT_OPERR_BANK1                FLASH_CR_OPERRIE     /*!< Operation Error on Bank 1 Interrupt source */
+#endif /* FLASH_CR_OPERRIE */
+#define FLASH_IT_RDPERR_BANK1               FLASH_CR_RDPERRIE    /*!< Read protection Error on Bank 1 Interrupt source */
+#define FLASH_IT_RDSERR_BANK1               FLASH_CR_RDSERRIE    /*!< Read Secured Error on Bank 1 Interrupt source */
+#define FLASH_IT_SNECCERR_BANK1             FLASH_CR_SNECCERRIE  /*!< Single ECC Error Correction on Bank 1 Interrupt source */
+#define FLASH_IT_DBECCERR_BANK1             FLASH_CR_DBECCERRIE  /*!< Double Detection ECC Error on Bank 1 Interrupt source */
+#define FLASH_IT_CRCEND_BANK1               FLASH_CR_CRCENDIE    /*!< CRC End on Bank 1 Interrupt source */
+#define FLASH_IT_CRCRDERR_BANK1             FLASH_CR_CRCRDERRIE  /*!< CRC Read error on Bank 1 Interrupt source */
+
+#if defined (FLASH_CR_OPERRIE)
+#define FLASH_IT_ALL_BANK1                 (FLASH_IT_EOP_BANK1       | FLASH_IT_WRPERR_BANK1    | \
+                                            FLASH_IT_PGSERR_BANK1    | FLASH_IT_STRBERR_BANK1   | \
+                                            FLASH_IT_INCERR_BANK1    | FLASH_IT_OPERR_BANK1     | \
+                                            FLASH_IT_RDPERR_BANK1    | FLASH_IT_RDSERR_BANK1    | \
+                                            FLASH_IT_SNECCERR_BANK1  | FLASH_IT_DBECCERR_BANK1  | \
+                                            FLASH_IT_CRCEND_BANK1    | FLASH_IT_CRCRDERR_BANK1) /*!< All Bank 1 Interrupt sources */
+#else
+#define FLASH_IT_ALL_BANK1                 (FLASH_IT_EOP_BANK1       | FLASH_IT_WRPERR_BANK1    | \
+                                            FLASH_IT_PGSERR_BANK1    | FLASH_IT_STRBERR_BANK1   | \
+                                            FLASH_IT_INCERR_BANK1    | FLASH_IT_RDPERR_BANK1    | \
+                                            FLASH_IT_RDSERR_BANK1    | FLASH_IT_SNECCERR_BANK1  | \
+                                            FLASH_IT_DBECCERR_BANK1  | FLASH_IT_CRCEND_BANK1    | \
+                                            FLASH_IT_CRCRDERR_BANK1) /*!< All Bank 1 Interrupt sources */
+#endif /* FLASH_CR_OPERRIE */
+
+#define FLASH_IT_EOP_BANK2                 (FLASH_CR_EOPIE      | 0x80000000U)  /*!< End of FLASH Bank 2 Operation Interrupt source */
+#define FLASH_IT_WRPERR_BANK2              (FLASH_CR_WRPERRIE   | 0x80000000U)  /*!< Write Protection Error on Bank 2 Interrupt source */
+#define FLASH_IT_PGSERR_BANK2              (FLASH_CR_PGSERRIE   | 0x80000000U)  /*!< Program Sequence Error on Bank 2 Interrupt source */
+#define FLASH_IT_STRBERR_BANK2             (FLASH_CR_STRBERRIE  | 0x80000000U)  /*!< Strobe Error on Bank 2 Interrupt source */
+#define FLASH_IT_INCERR_BANK2              (FLASH_CR_INCERRIE   | 0x80000000U)  /*!< Inconsistency Error on Bank 2 Interrupt source */
+#if defined (FLASH_CR_OPERRIE)
+#define FLASH_IT_OPERR_BANK2               (FLASH_CR_OPERRIE    | 0x80000000U)  /*!< Operation Error on Bank 2 Interrupt source */
+#endif /* FLASH_CR_OPERRIE */
+#define FLASH_IT_RDPERR_BANK2              (FLASH_CR_RDPERRIE   | 0x80000000U)  /*!< Read protection Error on Bank 2 Interrupt source */
+#define FLASH_IT_RDSERR_BANK2              (FLASH_CR_RDSERRIE   | 0x80000000U)  /*!< Read Secured Error on Bank 2 Interrupt source */
+#define FLASH_IT_SNECCERR_BANK2            (FLASH_CR_SNECCERRIE | 0x80000000U)  /*!< Single ECC Error Correction on Bank 2 Interrupt source */
+#define FLASH_IT_DBECCERR_BANK2            (FLASH_CR_DBECCERRIE | 0x80000000U)  /*!< Double Detection ECC Error on Bank 2 Interrupt source */
+#define FLASH_IT_CRCEND_BANK2              (FLASH_CR_CRCENDIE   | 0x80000000U)  /*!< CRC End on Bank 2 Interrupt source */
+#define FLASH_IT_CRCRDERR_BANK2            (FLASH_CR_CRCRDERRIE | 0x80000000U)  /*!< CRC Read Error on Bank 2 Interrupt source */
+
+#if defined (FLASH_CR_OPERRIE)
+#define FLASH_IT_ALL_BANK2                 (FLASH_IT_EOP_BANK2       | FLASH_IT_WRPERR_BANK2    | \
+                                            FLASH_IT_PGSERR_BANK2    | FLASH_IT_STRBERR_BANK2   | \
+                                            FLASH_IT_INCERR_BANK2    | FLASH_IT_OPERR_BANK2     | \
+                                            FLASH_IT_RDPERR_BANK2    | FLASH_IT_RDSERR_BANK2    | \
+                                            FLASH_IT_SNECCERR_BANK2  | FLASH_IT_DBECCERR_BANK2  | \
+                                            FLASH_IT_CRCEND_BANK2    | FLASH_IT_CRCRDERR_BANK2) /*!< All Bank 2 Interrupt sources */
+#else
+#define FLASH_IT_ALL_BANK2                 (FLASH_IT_EOP_BANK2       | FLASH_IT_WRPERR_BANK2    | \
+                                            FLASH_IT_PGSERR_BANK2    | FLASH_IT_STRBERR_BANK2   | \
+                                            FLASH_IT_INCERR_BANK2    | FLASH_IT_RDPERR_BANK2    | \
+                                            FLASH_IT_RDSERR_BANK2    | FLASH_IT_SNECCERR_BANK2  | \
+                                            FLASH_IT_DBECCERR_BANK2  | FLASH_IT_CRCEND_BANK2    | \
+                                            FLASH_IT_CRCRDERR_BANK2) /*!< All Bank 2 Interrupt sources */
+#endif /* FLASH_CR_OPERRIE */
+/**
+  * @}
+  */
+
+#if defined (FLASH_CR_PSIZE)
+/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism
+  * @{
+  */
+#define FLASH_PSIZE_BYTE           0x00000000U       /*!< Flash program/erase by 8 bits  */
+#define FLASH_PSIZE_HALF_WORD      FLASH_CR_PSIZE_0  /*!< Flash program/erase by 16 bits */
+#define FLASH_PSIZE_WORD           FLASH_CR_PSIZE_1  /*!< Flash program/erase by 32 bits */
+#define FLASH_PSIZE_DOUBLE_WORD    FLASH_CR_PSIZE    /*!< Flash program/erase by 64 bits */
+/**
+  * @}
+  */
+#endif /* FLASH_CR_PSIZE */
+
+
+/** @defgroup FLASH_Keys FLASH Keys
+  * @{
+  */
+#define FLASH_KEY1                 0x45670123U
+#define FLASH_KEY2                 0xCDEF89ABU
+#define FLASH_OPT_KEY1             0x08192A3BU
+#define FLASH_OPT_KEY2             0x4C5D6E7FU
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Sectors FLASH Sectors
+  * @{
+  */
+#define FLASH_SECTOR_0             0U       /*!< Sector Number 0   */
+#define FLASH_SECTOR_1             1U       /*!< Sector Number 1   */
+#define FLASH_SECTOR_2             2U       /*!< Sector Number 2   */
+#define FLASH_SECTOR_3             3U       /*!< Sector Number 3   */
+#define FLASH_SECTOR_4             4U       /*!< Sector Number 4   */
+#define FLASH_SECTOR_5             5U       /*!< Sector Number 5   */
+#define FLASH_SECTOR_6             6U       /*!< Sector Number 6   */
+#define FLASH_SECTOR_7             7U       /*!< Sector Number 7   */
+#if (FLASH_SECTOR_TOTAL == 128)
+#define FLASH_SECTOR_8             8U       /*!< Sector Number 8   */
+#define FLASH_SECTOR_9             9U       /*!< Sector Number 9   */
+#define FLASH_SECTOR_10            10U      /*!< Sector Number 10  */
+#define FLASH_SECTOR_11            11U      /*!< Sector Number 11  */
+#define FLASH_SECTOR_12            12U      /*!< Sector Number 12  */
+#define FLASH_SECTOR_13            13U      /*!< Sector Number 13  */
+#define FLASH_SECTOR_14            14U      /*!< Sector Number 14  */
+#define FLASH_SECTOR_15            15U      /*!< Sector Number 15  */
+#define FLASH_SECTOR_16            16U      /*!< Sector Number 16  */
+#define FLASH_SECTOR_17            17U      /*!< Sector Number 17  */
+#define FLASH_SECTOR_18            18U      /*!< Sector Number 18  */
+#define FLASH_SECTOR_19            19U      /*!< Sector Number 19  */
+#define FLASH_SECTOR_20            20U      /*!< Sector Number 20  */
+#define FLASH_SECTOR_21            21U      /*!< Sector Number 21  */
+#define FLASH_SECTOR_22            22U      /*!< Sector Number 22  */
+#define FLASH_SECTOR_23            23U      /*!< Sector Number 23  */
+#define FLASH_SECTOR_24            24U      /*!< Sector Number 24  */
+#define FLASH_SECTOR_25            25U      /*!< Sector Number 25  */
+#define FLASH_SECTOR_26            26U      /*!< Sector Number 26  */
+#define FLASH_SECTOR_27            27U      /*!< Sector Number 27  */
+#define FLASH_SECTOR_28            28U      /*!< Sector Number 28  */
+#define FLASH_SECTOR_29            29U      /*!< Sector Number 29  */
+#define FLASH_SECTOR_30            30U      /*!< Sector Number 30  */
+#define FLASH_SECTOR_31            31U      /*!< Sector Number 31  */
+#define FLASH_SECTOR_32            32U      /*!< Sector Number 32  */
+#define FLASH_SECTOR_33            33U      /*!< Sector Number 33  */
+#define FLASH_SECTOR_34            34U      /*!< Sector Number 34  */
+#define FLASH_SECTOR_35            35U      /*!< Sector Number 35  */
+#define FLASH_SECTOR_36            36U      /*!< Sector Number 36  */
+#define FLASH_SECTOR_37            37U      /*!< Sector Number 37  */
+#define FLASH_SECTOR_38            38U      /*!< Sector Number 38  */
+#define FLASH_SECTOR_39            39U      /*!< Sector Number 39  */
+#define FLASH_SECTOR_40            40U      /*!< Sector Number 40  */
+#define FLASH_SECTOR_41            41U      /*!< Sector Number 41  */
+#define FLASH_SECTOR_42            42U      /*!< Sector Number 42  */
+#define FLASH_SECTOR_43            43U      /*!< Sector Number 43  */
+#define FLASH_SECTOR_44            44U      /*!< Sector Number 44  */
+#define FLASH_SECTOR_45            45U      /*!< Sector Number 45  */
+#define FLASH_SECTOR_46            46U      /*!< Sector Number 46  */
+#define FLASH_SECTOR_47            47U      /*!< Sector Number 47  */
+#define FLASH_SECTOR_48            48U      /*!< Sector Number 48  */
+#define FLASH_SECTOR_49            49U      /*!< Sector Number 49  */
+#define FLASH_SECTOR_50            50U      /*!< Sector Number 50  */
+#define FLASH_SECTOR_51            51U      /*!< Sector Number 51  */
+#define FLASH_SECTOR_52            52U      /*!< Sector Number 52  */
+#define FLASH_SECTOR_53            53U      /*!< Sector Number 53  */
+#define FLASH_SECTOR_54            54U      /*!< Sector Number 54  */
+#define FLASH_SECTOR_55            55U      /*!< Sector Number 55  */
+#define FLASH_SECTOR_56            56U      /*!< Sector Number 56  */
+#define FLASH_SECTOR_57            57U      /*!< Sector Number 57  */
+#define FLASH_SECTOR_58            58U      /*!< Sector Number 58  */
+#define FLASH_SECTOR_59            59U      /*!< Sector Number 59  */
+#define FLASH_SECTOR_60            60U      /*!< Sector Number 60  */
+#define FLASH_SECTOR_61            61U      /*!< Sector Number 61  */
+#define FLASH_SECTOR_62            62U      /*!< Sector Number 62  */
+#define FLASH_SECTOR_63            63U      /*!< Sector Number 63  */
+#define FLASH_SECTOR_64            64U      /*!< Sector Number 64  */
+#define FLASH_SECTOR_65            65U      /*!< Sector Number 65  */
+#define FLASH_SECTOR_66            66U      /*!< Sector Number 66  */
+#define FLASH_SECTOR_67            67U      /*!< Sector Number 67  */
+#define FLASH_SECTOR_68            68U      /*!< Sector Number 68  */
+#define FLASH_SECTOR_69            69U      /*!< Sector Number 69  */
+#define FLASH_SECTOR_70            70U      /*!< Sector Number 70  */
+#define FLASH_SECTOR_71            71U      /*!< Sector Number 71  */
+#define FLASH_SECTOR_72            72U      /*!< Sector Number 72  */
+#define FLASH_SECTOR_73            73U      /*!< Sector Number 73  */
+#define FLASH_SECTOR_74            74U      /*!< Sector Number 74  */
+#define FLASH_SECTOR_75            75U      /*!< Sector Number 75  */
+#define FLASH_SECTOR_76            76U      /*!< Sector Number 76  */
+#define FLASH_SECTOR_77            77U      /*!< Sector Number 77  */
+#define FLASH_SECTOR_78            78U      /*!< Sector Number 78  */
+#define FLASH_SECTOR_79            79U      /*!< Sector Number 79  */
+#define FLASH_SECTOR_80            80U      /*!< Sector Number 80  */
+#define FLASH_SECTOR_81            81U      /*!< Sector Number 81  */
+#define FLASH_SECTOR_82            82U      /*!< Sector Number 82  */
+#define FLASH_SECTOR_83            83U      /*!< Sector Number 83  */
+#define FLASH_SECTOR_84            84U      /*!< Sector Number 84  */
+#define FLASH_SECTOR_85            85U      /*!< Sector Number 85  */
+#define FLASH_SECTOR_86            86U      /*!< Sector Number 86  */
+#define FLASH_SECTOR_87            87U      /*!< Sector Number 87  */
+#define FLASH_SECTOR_88            88U      /*!< Sector Number 88  */
+#define FLASH_SECTOR_89            89U      /*!< Sector Number 89  */
+#define FLASH_SECTOR_90            90U      /*!< Sector Number 90  */
+#define FLASH_SECTOR_91            91U      /*!< Sector Number 91  */
+#define FLASH_SECTOR_92            92U      /*!< Sector Number 92  */
+#define FLASH_SECTOR_93            93U      /*!< Sector Number 93  */
+#define FLASH_SECTOR_94            94U      /*!< Sector Number 94  */
+#define FLASH_SECTOR_95            95U      /*!< Sector Number 95  */
+#define FLASH_SECTOR_96            96U      /*!< Sector Number 96  */
+#define FLASH_SECTOR_97            97U      /*!< Sector Number 97  */
+#define FLASH_SECTOR_98            98U      /*!< Sector Number 98  */
+#define FLASH_SECTOR_99            99U      /*!< Sector Number 99  */
+#define FLASH_SECTOR_100           100U     /*!< Sector Number 100 */
+#define FLASH_SECTOR_101           101U     /*!< Sector Number 101 */
+#define FLASH_SECTOR_102           102U     /*!< Sector Number 102 */
+#define FLASH_SECTOR_103           103U     /*!< Sector Number 103 */
+#define FLASH_SECTOR_104           104U     /*!< Sector Number 104 */
+#define FLASH_SECTOR_105           105U     /*!< Sector Number 105 */
+#define FLASH_SECTOR_106           106U     /*!< Sector Number 106 */
+#define FLASH_SECTOR_107           107U     /*!< Sector Number 107 */
+#define FLASH_SECTOR_108           108U     /*!< Sector Number 108 */
+#define FLASH_SECTOR_109           109U     /*!< Sector Number 109 */
+#define FLASH_SECTOR_110           110U     /*!< Sector Number 110 */
+#define FLASH_SECTOR_111           111U     /*!< Sector Number 111 */
+#define FLASH_SECTOR_112           112U     /*!< Sector Number 112 */
+#define FLASH_SECTOR_113           113U     /*!< Sector Number 113 */
+#define FLASH_SECTOR_114           114U     /*!< Sector Number 114 */
+#define FLASH_SECTOR_115           115U     /*!< Sector Number 115 */
+#define FLASH_SECTOR_116           116U     /*!< Sector Number 116 */
+#define FLASH_SECTOR_117           117U     /*!< Sector Number 117 */
+#define FLASH_SECTOR_118           118U     /*!< Sector Number 118 */
+#define FLASH_SECTOR_119           119U     /*!< Sector Number 119 */
+#define FLASH_SECTOR_120           120U     /*!< Sector Number 120 */
+#define FLASH_SECTOR_121           121U     /*!< Sector Number 121 */
+#define FLASH_SECTOR_122           122U     /*!< Sector Number 122 */
+#define FLASH_SECTOR_123           123U     /*!< Sector Number 123 */
+#define FLASH_SECTOR_124           124U     /*!< Sector Number 124 */
+#define FLASH_SECTOR_125           125U     /*!< Sector Number 125 */
+#define FLASH_SECTOR_126           126U     /*!< Sector Number 126 */
+#define FLASH_SECTOR_127           127U     /*!< Sector Number 127 */
+#endif /* FLASH_SECTOR_TOTAL == 128 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
+  * @{
+  */
+/**
+  * @brief  Set the FLASH Latency.
+  * @param  __LATENCY__: FLASH Latency
+  *         The value of this parameter depend on device used within the same series
+  * @retval none
+  */
+#define __HAL_FLASH_SET_LATENCY(__LATENCY__) \
+                  MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__))
+
+/**
+  * @brief  Get the FLASH Latency.
+  * @retval FLASH Latency
+  *          The value of this parameter depend on device used within the same series
+  */
+#define __HAL_FLASH_GET_LATENCY()     (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
+
+/**
+  * @brief  Enable the specified FLASH interrupt.
+  * @param  __INTERRUPT__ : FLASH interrupt
+  *   In case of Bank 1 This parameter can be any combination of the following values:
+  *     @arg FLASH_IT_EOP_BANK1       : End of FLASH Bank 1 Operation Interrupt source
+  *     @arg FLASH_IT_WRPERR_BANK1    : Write Protection Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_PGSERR_BANK1    : Program Sequence Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_STRBERR_BANK1   : Strobe Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_INCERR_BANK1    : Inconsistency Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_OPERR_BANK1     : Operation Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_RDPERR_BANK1    : Read protection Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_RDSERR_BANK1    : Read secure Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_SNECCERR_BANK1  : Single ECC Error Correction on Bank 1 Interrupt source
+  *     @arg FLASH_IT_DBECCERR_BANK1  : Double Detection ECC Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_CRCEND_BANK1    : CRC End on Bank 1 Interrupt source
+  *     @arg FLASH_IT_CRCRDERR_BANK1  : CRC Read error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_ALL_BANK1       : All Bank 1 Interrupt sources
+  *
+  *   In case of Bank 2, this parameter can be any combination of the following values:
+  *     @arg FLASH_IT_EOP_BANK2       : End of FLASH Bank 2 Operation Interrupt source
+  *     @arg FLASH_IT_WRPERR_BANK2    : Write Protection Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_PGSERR_BANK2    : Program Sequence Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_STRBERR_BANK2   : Strobe Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_INCERR_BANK2    : Inconsistency Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_OPERR_BANK2     : Operation Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_RDPERR_BANK2    : Read protection Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_RDSERR_BANK2    : Read secure Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_SNECCERR_BANK2  : Single ECC Error Correction on Bank 2 Interrupt source
+  *     @arg FLASH_IT_DBECCERR_BANK2  : Double Detection ECC Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_CRCEND_BANK2    : CRC End on Bank 2 Interrupt source
+  *     @arg FLASH_IT_CRCRDERR_BANK2  : CRC Read error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_ALL_BANK2       : All Bank 2 Interrupt sources
+  * @retval none
+  */
+
+#define __HAL_FLASH_ENABLE_IT_BANK1(__INTERRUPT__)      (FLASH->CR1 |= (__INTERRUPT__))
+
+#define __HAL_FLASH_ENABLE_IT_BANK2(__INTERRUPT__)      (FLASH->CR2 |= ((__INTERRUPT__) & 0x7FFFFFFFU))
+
+#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)    (IS_FLASH_IT_BANK1(__INTERRUPT__) ? \
+                                                 __HAL_FLASH_ENABLE_IT_BANK1(__INTERRUPT__) : \
+                                                 __HAL_FLASH_ENABLE_IT_BANK2(__INTERRUPT__))
+
+
+/**
+  * @brief  Disable the specified FLASH interrupt.
+  * @param  __INTERRUPT__ : FLASH interrupt
+  *   In case of Bank 1 This parameter can be any combination of the following values:
+  *     @arg FLASH_IT_EOP_BANK1       : End of FLASH Bank 1 Operation Interrupt source
+  *     @arg FLASH_IT_WRPERR_BANK1    : Write Protection Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_PGSERR_BANK1    : Program Sequence Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_STRBERR_BANK1   : Strobe Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_INCERR_BANK1    : Inconsistency Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_OPERR_BANK1     : Operation Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_RDPERR_BANK1    : Read protection Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_RDSERR_BANK1    : Read secure Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_SNECCERR_BANK1  : Single ECC Error Correction on Bank 1 Interrupt source
+  *     @arg FLASH_IT_DBECCERR_BANK1  : Double Detection ECC Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_CRCEND_BANK1    : CRC End on Bank 1 Interrupt source
+  *     @arg FLASH_IT_CRCRDERR_BANK1  : CRC Read error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_ALL_BANK1       : All Bank 1 Interrupt sources
+  *
+  *   In case of Bank 2, this parameter can be any combination of the following values:
+  *     @arg FLASH_IT_EOP_BANK2       : End of FLASH Bank 2 Operation Interrupt source
+  *     @arg FLASH_IT_WRPERR_BANK2    : Write Protection Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_PGSERR_BANK2    : Program Sequence Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_STRBERR_BANK2   : Strobe Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_INCERR_BANK2    : Inconsistency Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_OPERR_BANK2     : Operation Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_RDPERR_BANK2    : Read protection Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_RDSERR_BANK2    : Read secure Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_SNECCERR_BANK2  : Single ECC Error Correction on Bank 2 Interrupt source
+  *     @arg FLASH_IT_DBECCERR_BANK2  : Double Detection ECC Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_CRCEND_BANK2    : CRC End on Bank 2 Interrupt source
+  *     @arg FLASH_IT_CRCRDERR_BANK2  : CRC Read error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_ALL_BANK2       : All Bank 2 Interrupt sources
+  * @retval none
+  */
+
+#define __HAL_FLASH_DISABLE_IT_BANK1(__INTERRUPT__)  (FLASH->CR1 &= ~(uint32_t)(__INTERRUPT__))
+
+#define __HAL_FLASH_DISABLE_IT_BANK2(__INTERRUPT__)  (FLASH->CR2 &= ~(uint32_t)((__INTERRUPT__) & 0x7FFFFFFFU))
+
+#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)  (IS_FLASH_IT_BANK1(__INTERRUPT__) ? \
+                                                __HAL_FLASH_DISABLE_IT_BANK1(__INTERRUPT__) : \
+                                                __HAL_FLASH_DISABLE_IT_BANK2(__INTERRUPT__))
+
+
+/**
+  * @brief  Checks whether the specified FLASH flag is set or not.
+  * @param  __FLAG__: specifies the FLASH flag to check.
+  *   In case of Bank 1 This parameter can be one of the following values :
+  *     @arg FLASH_FLAG_BSY_BANK1      : FLASH Bank 1 Busy flag
+  *     @arg FLASH_FLAG_WBNE_BANK1     : Write Buffer Not Empty on Bank 1 flag
+  *     @arg FLASH_FLAG_QW_BANK1       : Wait Queue on Bank 1 flag
+  *     @arg FLASH_FLAG_CRC_BUSY_BANK1 : CRC module is working on Bank 1 flag
+  *     @arg FLASH_FLAG_EOP_BANK1      : End Of Program on Bank 1 flag
+  *     @arg FLASH_FLAG_WRPERR_BANK1   : Write Protection Error on Bank 1 flag
+  *     @arg FLASH_FLAG_PGSERR_BANK1   : Program Sequence Error on Bank 1 flag
+  *     @arg FLASH_FLAG_STRBER_BANK1   : Program Alignment Error on Bank 1 flag
+  *     @arg FLASH_FLAG_INCERR_BANK1   : Inconsistency Error on Bank 1 flag
+  *     @arg FLASH_FLAG_OPERR_BANK1    : Operation Error on Bank 1 flag
+  *     @arg FLASH_FLAG_RDPERR_BANK1   : Read Protection Error on Bank 1 flag
+  *     @arg FLASH_FLAG_RDSERR_BANK1   : Read secure  Error on Bank 1 flag
+  *     @arg FLASH_FLAG_SNECCE_BANK1   : Single ECC Error Correction on Bank 1 flag
+  *     @arg FLASH_FLAG_DBECCE_BANK1   : Double Detection ECC Error on Bank 1 flag
+  *     @arg FLASH_FLAG_CRCEND_BANK1   : CRC End on Bank 1 flag
+  *     @arg FLASH_FLAG_CRCRDERR_BANK1 : CRC Read error on Bank 1 flag
+  *
+  *   In case of Bank 2 This parameter can be one of the following values :
+  *     @arg FLASH_FLAG_BSY_BANK2      : FLASH Bank 2 Busy flag
+  *     @arg FLASH_FLAG_WBNE_BANK2     : Write Buffer Not Empty on Bank 2 flag
+  *     @arg FLASH_FLAG_QW_BANK2       : Wait Queue on Bank 2 flag
+  *     @arg FLASH_FLAG_CRC_BUSY_BANK2 : CRC module is working on Bank 2 flag
+  *     @arg FLASH_FLAG_EOP_BANK2      : End Of Program on Bank 2 flag
+  *     @arg FLASH_FLAG_WRPERR_BANK2   : Write Protection Error on Bank 2 flag
+  *     @arg FLASH_FLAG_PGSERR_BANK2   : Program Sequence Error on Bank 2 flag
+  *     @arg FLASH_FLAG_STRBER_BANK2   : Program Alignment Error on Bank 2 flag
+  *     @arg FLASH_FLAG_INCERR_BANK2   : Inconsistency Error on Bank 2 flag
+  *     @arg FLASH_FLAG_OPERR_BANK2    : Operation Error on Bank 2 flag
+  *     @arg FLASH_FLAG_RDPERR_BANK2   : Read Protection Error on Bank 2 flag
+  *     @arg FLASH_FLAG_RDSERR_BANK2   : Read secure  Error on Bank 2 flag
+  *     @arg FLASH_FLAG_SNECCE_BANK2   : Single ECC Error Correction on Bank 2 flag
+  *     @arg FLASH_FLAG_DBECCE_BANK2   : Double Detection ECC Error on Bank 2 flag
+  *     @arg FLASH_FLAG_CRCEND_BANK2   : CRC End on Bank 2 flag
+  *     @arg FLASH_FLAG_CRCRDERR_BANK2 : CRC Read error on Bank 2 flag
+  * @retval The new state of FLASH_FLAG (SET or RESET).
+  */
+#define __HAL_FLASH_GET_FLAG_BANK1(__FLAG__)     (READ_BIT(FLASH->SR1, (__FLAG__)) == (__FLAG__))
+
+#define __HAL_FLASH_GET_FLAG_BANK2(__FLAG__)     (READ_BIT(FLASH->SR2, ((__FLAG__) & 0x7FFFFFFFU)) == (((__FLAG__) & 0x7FFFFFFFU)))
+
+#define __HAL_FLASH_GET_FLAG(__FLAG__)           (IS_FLASH_FLAG_BANK1(__FLAG__) ?  __HAL_FLASH_GET_FLAG_BANK1(__FLAG__) : \
+                                                  __HAL_FLASH_GET_FLAG_BANK2(__FLAG__))
+
+
+/**
+  * @brief  Clear the specified FLASH flag.
+  * @param  __FLAG__: specifies the FLASH flags to clear.
+  *    In case of Bank 1, this parameter can be any combination of the following values:
+  *     @arg FLASH_FLAG_EOP_BANK1        : End Of Program on Bank 1 flag
+  *     @arg FLASH_FLAG_WRPERR_BANK1     : Write Protection Error on Bank 1 flag
+  *     @arg FLASH_FLAG_PGSERR_BANK1     : Program Sequence Error on Bank 1 flag
+  *     @arg FLASH_FLAG_STRBER_BANK1     : Program Alignment Error on Bank 1 flag
+  *     @arg FLASH_FLAG_INCERR_BANK1     : Inconsistency Error on Bank 1 flag
+  *     @arg FLASH_FLAG_OPERR_BANK1      : Operation Error on Bank 1 flag
+  *     @arg FLASH_FLAG_RDPERR_BANK1     : Read Protection Error on Bank 1 flag
+  *     @arg FLASH_FLAG_RDSERR_BANK1     : Read secure  Error on Bank 1 flag
+  *     @arg FLASH_FLAG_SNECCE_BANK1     : Single ECC Error Correction on Bank 1 flag
+  *     @arg FLASH_FLAG_DBECCE_BANK1     : Double Detection ECC Error on Bank 1 flag
+  *     @arg FLASH_FLAG_CRCEND_BANK1     : CRC End on Bank 1 flag
+  *     @arg FLASH_FLAG_CRCRDERR_BANK1   : CRC Read error on Bank 1 flag
+  *     @arg FLASH_FLAG_ALL_ERRORS_BANK1 : All Bank 1 error flags
+  *     @arg FLASH_FLAG_ALL_BANK1        : All Bank 1 flags
+  *
+  *   In case of Bank 2, this parameter can be any combination of the following values :
+  *     @arg FLASH_FLAG_EOP_BANK2        : End Of Program on Bank 2 flag
+  *     @arg FLASH_FLAG_WRPERR_BANK2     : Write Protection Error on Bank 2 flag
+  *     @arg FLASH_FLAG_PGSERR_BANK2     : Program Sequence Error on Bank 2 flag
+  *     @arg FLASH_FLAG_STRBER_BANK2     : Program Alignment Error on Bank 2 flag
+  *     @arg FLASH_FLAG_INCERR_BANK2     : Inconsistency Error on Bank 2 flag
+  *     @arg FLASH_FLAG_OPERR_BANK2      : Operation Error on Bank 2 flag
+  *     @arg FLASH_FLAG_RDPERR_BANK2     : Read Protection Error on Bank 2 flag
+  *     @arg FLASH_FLAG_RDSERR_BANK2     : Read secure  Error on Bank 2 flag
+  *     @arg FLASH_FLAG_SNECCE_BANK2     : Single ECC Error Correction on Bank 2 flag
+  *     @arg FLASH_FLAG_DBECCE_BANK2     : Double Detection ECC Error on Bank 2 flag
+  *     @arg FLASH_FLAG_CRCEND_BANK2     : CRC End on Bank 2 flag
+  *     @arg FLASH_FLAG_CRCRDERR_BANK2   : CRC Read error on Bank 2 flag
+  *     @arg FLASH_FLAG_ALL_ERRORS_BANK2 : All Bank 2 error flags
+  *     @arg FLASH_FLAG_ALL_BANK2        : All Bank 2 flags
+  * @retval none
+  */
+
+#define __HAL_FLASH_CLEAR_FLAG_BANK1(__FLAG__)    WRITE_REG(FLASH->CCR1, (__FLAG__))
+
+#define __HAL_FLASH_CLEAR_FLAG_BANK2(__FLAG__)    WRITE_REG(FLASH->CCR2, ((__FLAG__) & 0x7FFFFFFFU))
+
+#define __HAL_FLASH_CLEAR_FLAG(__FLAG__)         (IS_FLASH_FLAG_BANK1(__FLAG__) ?  __HAL_FLASH_CLEAR_FLAG_BANK1(__FLAG__) : \
+                                                   __HAL_FLASH_CLEAR_FLAG_BANK2(__FLAG__))
+
+/**
+  * @}
+  */
+
+/* Include FLASH HAL Extension module */
+#include "stm32h7xx_hal_flash_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASH_Exported_Functions
+  * @{
+  */
+/** @addtogroup FLASH_Exported_Functions_Group1
+  * @{
+  */
+/* Program operation functions  ***********************************************/
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress);
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress);
+/* FLASH IRQ handler method */
+void HAL_FLASH_IRQHandler(void);
+/* Callbacks in non blocking modes */
+void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
+void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
+/**
+  * @}
+  */
+
+/** @addtogroup FLASH_Exported_Functions_Group2
+  * @{
+  */
+/* Peripheral Control functions  **********************************************/
+HAL_StatusTypeDef HAL_FLASH_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_Lock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
+/* Option bytes control */
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
+/**
+  * @}
+  */
+
+/** @addtogroup FLASH_Exported_Functions_Group3
+  * @{
+  */
+/* Peripheral State functions  ************************************************/
+uint32_t HAL_FLASH_GetError(void);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup FLASH_Private_Variables FLASH Private Variables
+  * @{
+  */
+extern FLASH_ProcessTypeDef pFlash;
+/**
+  * @}
+  */
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup FLASH_Private_Constants FLASH Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FLASH_Private_Macros FLASH Private Macros
+  * @{
+  */
+
+#if defined (FLASH_OPTCR_PG_OTP)
+#define IS_FLASH_TYPEPROGRAM(VALUE)      (((VALUE) == FLASH_TYPEPROGRAM_FLASHWORD) || \
+                                          ((VALUE) == FLASH_TYPEPROGRAM_OTPWORD))
+#else
+#define IS_FLASH_TYPEPROGRAM(VALUE)      ((VALUE) == FLASH_TYPEPROGRAM_FLASHWORD)
+#endif /* FLASH_OPTCR_PG_OTP */
+
+#define IS_FLASH_IT_BANK1(IT)            (((IT) & FLASH_IT_ALL_BANK1) == (IT))
+
+#define IS_FLASH_IT_BANK2(IT)            (((IT) & FLASH_IT_ALL_BANK2) == (IT))
+
+#define IS_FLASH_FLAG_BANK1(FLAG)        (((FLAG) & FLASH_FLAG_ALL_BANK1) == (FLAG))
+
+#define IS_FLASH_FLAG_BANK2(FLAG)        (((FLAG) & FLASH_FLAG_ALL_BANK2) == (FLAG))
+
+#define IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) (((ADDRESS) >= FLASH_BANK1_BASE) && ((ADDRESS) < FLASH_BANK2_BASE))
+#define IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS) (((ADDRESS) >= FLASH_BANK2_BASE ) && ((ADDRESS) <= FLASH_END))
+
+#if defined (FLASH_OPTCR_PG_OTP)
+#define IS_FLASH_PROGRAM_ADDRESS_OTP(ADDRESS)   (((ADDRESS) >= 0x08FFF000U) && ((ADDRESS) <= 0x08FFF3FFU))
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS)       (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || \
+                                                 IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS) || \
+                                                 IS_FLASH_PROGRAM_ADDRESS_OTP(ADDRESS))
+#else
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS)       (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || \
+                                                 IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS))
+#endif /* FLASH_OPTCR_PG_OTP */
+
+#define IS_BOOT_ADDRESS(ADDRESS)           ((ADDRESS) <= (0x3FFF0000U))
+
+#define IS_FLASH_BANK(BANK)                (((BANK) == FLASH_BANK_1)  || \
+                                            ((BANK) == FLASH_BANK_2)  || \
+                                            ((BANK) == FLASH_BANK_BOTH))
+
+#define IS_FLASH_BANK_EXCLUSIVE(BANK)      (((BANK) == FLASH_BANK_1)  || \
+                                            ((BANK) == FLASH_BANK_2))
+
+
+/**
+  * @}
+  */
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup FLASH_Private_Functions FLASH Private functions
+  * @{
+  */
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout, uint32_t Bank);
+HAL_StatusTypeDef FLASH_OB_WaitForLastOperation(uint32_t Timeout);
+HAL_StatusTypeDef FLASH_CRC_WaitForLastOperation(uint32_t Timeout, uint32_t Bank);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_FLASH_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h
new file mode 100644
index 00000000..834c5d23
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h
@@ -0,0 +1,910 @@
+/**
+  ******************************************************************************
+  * @file    stm32H7xx_hal_flash_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of FLASH HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_FLASH_EX_H
+#define STM32H7xx_HAL_FLASH_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FLASHEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Types FLASH Exported Types
+  * @{
+  */
+
+/**
+  * @brief  FLASH Erase structure definition
+  */
+typedef struct
+{
+  uint32_t TypeErase;   /*!< Mass erase or sector Erase.
+                             This parameter can be a value of @ref FLASHEx_Type_Erase */
+
+  uint32_t Banks;       /*!< Select banks to erase when Mass erase is enabled.
+                             This parameter must be a value of @ref FLASHEx_Banks */
+
+  uint32_t Sector;      /*!< Initial FLASH sector to erase when Mass erase is disabled
+                             This parameter must be a value of @ref FLASH_Sectors */
+
+  uint32_t NbSectors;   /*!< Number of sectors to be erased.
+                             This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
+
+  uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism
+                             This parameter must be a value of @ref FLASHEx_Voltage_Range */
+
+} FLASH_EraseInitTypeDef;
+
+
+/**
+  * @brief  FLASH Option Bytes Program structure definition
+  */
+typedef struct
+{
+  uint32_t OptionType;     /*!< Option byte to be configured.
+                                This parameter can be a value of @ref FLASHEx_Option_Type */
+
+  uint32_t WRPState;       /*!< Write protection activation or deactivation.
+                                This parameter can be a value of @ref FLASHEx_WRP_State */
+
+  uint32_t WRPSector;      /*!< Specifies the sector(s) to be write protected.
+                                The value of this parameter depend on device used within the same series */
+
+  uint32_t RDPLevel;       /*!< Set the read protection level.
+                                This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
+
+  uint32_t BORLevel;       /*!< Set the BOR Level.
+                                This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */
+
+  uint32_t USERType;       /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER).
+                                This parameter can be a combination of @ref FLASHEx_OB_USER_Type */
+
+  uint32_t USERConfig;     /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY /
+                                IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / IO_HSLV / SWAP_BANK_OPT */
+
+  uint32_t Banks;          /*!< Select banks for WRP , PCROP and secure area config .
+                                This parameter must be a value of @ref FLASHEx_Banks */
+
+  uint32_t PCROPConfig;    /*!< specifies if the PCROP area shall be erased or not
+                                when RDP level decreased from Level 1 to Level 0 or during a mass erase.
+                                This parameter must be a value of @ref FLASHEx_OB_PCROP_RDP enumeration */
+
+  uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP).
+                                This parameter must be a value between begin and end of a bank */
+
+  uint32_t PCROPEndAddr;   /*!< PCROP End address (used for OPTIONBYTE_PCROP).
+                                This parameter must be a value between PCROP Start address and end of a bank */
+
+  uint32_t BootConfig;     /*!< Specifies if the Boot Address to be configured BOOT_ADD0, BOOT_ADD1
+                                or both. This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION enumeration */
+
+  uint32_t BootAddr0;      /*!< Boot Address 0.
+                                This parameter must be a value between begin and end of a bank */
+
+  uint32_t BootAddr1;      /*!< Boot Address 1.
+                                This parameter must be a value between begin and end of a bank */
+#if defined(DUAL_CORE)
+  uint32_t CM4BootConfig;  /*!< specifies if the CM4 boot Address to be configured BOOT_ADD0, BOOT_ADD1
+                                or both.
+                                This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION enumeration */
+
+  uint32_t CM4BootAddr0;   /*!< CM4 Boot Address 0.
+                                This parameter must be a value between begin and end of a bank */
+
+  uint32_t CM4BootAddr1;   /*!< CM4 Boot Address 1.
+                                This parameter must be a value between begin and end of a bank */
+#endif /*DUAL_CORE*/
+
+  uint32_t SecureAreaConfig;    /*!< specifies if the bank secured area shall be erased or not
+                                     when RDP level decreased from Level 1 to Level 0 or during a mass erase.
+                                     This parameter must be a value of @ref FLASHEx_OB_SECURE_RDP enumeration */
+
+  uint32_t SecureAreaStartAddr; /*!< Bank Secure area Start address.
+                                     This parameter must be a value between begin address and end address of bank1 */
+
+  uint32_t SecureAreaEndAddr;   /*!< Bank Secure area End address.
+                                     This parameter must be a value between Secure Area Start address and end address of a bank1 */
+
+#if defined (FLASH_OTPBL_LOCKBL)
+  uint32_t OTPBlockLock;   /*!< Specifies the OTP block(s) to be locked.
+                                This parameter must be a value of @ref FLASHEx_OTP_Blocks */
+#endif /* FLASH_OTPBL_LOCKBL */
+
+} FLASH_OBProgramInitTypeDef;
+
+/**
+  * @brief  FLASH Erase structure definition
+  */
+typedef struct
+{
+  uint32_t TypeCRC;      /*!< CRC Selection Type.
+                              This parameter can be a value of @ref FLASHEx_CRC_Selection_Type */
+
+  uint32_t BurstSize;    /*!< CRC Burst Size.
+                              This parameter can be a value of @ref FLASHEx_CRC_Burst_Size */
+
+  uint32_t Bank;         /*!< Select bank where CRC computation is enabled.
+                              This parameter must be FLASH_BANK_1 or FLASH_BANK_2 */
+
+  uint32_t Sector;       /*!< Initial FLASH sector from which starts the CRC computation
+                              This parameter must be a value of @ref FLASH_Sectors */
+
+  uint32_t NbSectors;    /*!< Number of sectors to be computed.
+                              This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
+
+  uint32_t CRCStartAddr; /*!< CRC Start address.
+                              This parameter must be a value between begin address and end address of a bank */
+
+  uint32_t CRCEndAddr;   /*!< CRC End address.
+                              This parameter must be a value between CRC Start address and end address of a bank */
+
+} FLASH_CRCInitTypeDef;
+
+/**
+  * @}
+  */
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants
+  * @{
+  */
+
+/** @defgroup FLASHEx_Type_Erase FLASH Type Erase
+  * @{
+  */
+#define FLASH_TYPEERASE_SECTORS      0x00U  /*!< Sectors erase only          */
+#define FLASH_TYPEERASE_MASSERASE    0x01U  /*!< Flash Mass erase activation */
+/**
+  * @}
+  */
+
+#if defined (FLASH_CR_PSIZE)
+/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range
+  * @{
+  */
+#define FLASH_VOLTAGE_RANGE_1        0x00000000U       /*!< Flash program/erase by 8 bits  */
+#define FLASH_VOLTAGE_RANGE_2        FLASH_CR_PSIZE_0  /*!< Flash program/erase by 16 bits */
+#define FLASH_VOLTAGE_RANGE_3        FLASH_CR_PSIZE_1  /*!< Flash program/erase by 32 bits */
+#define FLASH_VOLTAGE_RANGE_4        FLASH_CR_PSIZE    /*!< Flash program/erase by 64 bits */
+/**
+  * @}
+  */
+#endif /* FLASH_CR_PSIZE */
+
+/** @defgroup FLASHEx_WRP_State FLASH WRP State
+  * @{
+  */
+#define OB_WRPSTATE_DISABLE          0x00000000U  /*!< Disable the write protection of the desired bank 1 sectors */
+#define OB_WRPSTATE_ENABLE           0x00000001U  /*!< Enable the write protection of the desired bank 1 sectors  */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Option_Type FLASH Option Type
+  * @{
+  */
+#define OPTIONBYTE_WRP           0x01U  /*!< WRP option byte configuration  */
+#define OPTIONBYTE_RDP           0x02U  /*!< RDP option byte configuration  */
+#define OPTIONBYTE_USER          0x04U  /*!< USER option byte configuration */
+#define OPTIONBYTE_PCROP         0x08U  /*!< PCROP option byte configuration */
+#define OPTIONBYTE_BOR           0x10U  /*!< BOR option byte configuration */
+#define OPTIONBYTE_SECURE_AREA   0x20U  /*!< secure area option byte configuration */
+#if defined (DUAL_CORE)
+#define OPTIONBYTE_CM7_BOOTADD   0x40U  /*!< CM7 BOOT ADD option byte configuration */
+#define OPTIONBYTE_CM4_BOOTADD   0x80U  /*!< CM4 BOOT ADD option byte configuration */
+#define OPTIONBYTE_BOOTADD       OPTIONBYTE_CM7_BOOTADD  /*!< BOOT ADD option byte configuration */
+#else /* Single core */
+#define OPTIONBYTE_BOOTADD       0x40U  /*!< BOOT ADD option byte configuration */
+#endif /*DUAL_CORE*/
+#if defined (FLASH_OTPBL_LOCKBL)
+#define OPTIONBYTE_OTP_LOCK      0x80U  /*!< OTP Lock option byte configuration */
+#endif /* FLASH_OTPBL_LOCKBL */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection
+  * @{
+  */
+#define OB_RDP_LEVEL_0       0xAA00U
+#define OB_RDP_LEVEL_1       0x5500U
+#define OB_RDP_LEVEL_2       0xCC00U   /*!< Warning: When enabling read protection level 2
+                                            it s no more possible to go back to level 1 or 0 */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Option_Bytes_WWatchdog FLASH Option Bytes WWatchdog
+  * @{
+  */
+#define OB_WWDG_SW           0x10U  /*!< Software WWDG selected */
+#define OB_WWDG_HW           0x00U  /*!< Hardware WWDG selected */
+/**
+  * @}
+  */
+
+
+/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog
+  * @{
+  */
+#define OB_IWDG_SW           0x20U  /*!< Software IWDG selected */
+#define OB_IWDG_HW           0x00U  /*!< Hardware IWDG selected */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP
+  * @{
+  */
+#define OB_STOP_NO_RST       0x40U /*!< No reset generated when entering in STOP */
+#define OB_STOP_RST          0x00U /*!< Reset generated when entering in STOP    */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY
+  * @{
+  */
+#define OB_STDBY_NO_RST      0x80U /*!< No reset generated when entering in STANDBY */
+#define OB_STDBY_RST         0x00U /*!< Reset generated when entering in STANDBY    */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP
+  * @{
+  */
+#define OB_IWDG_STOP_FREEZE  0x00000000U /*!< Freeze IWDG counter in STOP mode */
+#define OB_IWDG_STOP_ACTIVE  FLASH_OPTSR_FZ_IWDG_STOP /*!< IWDG counter active in STOP mode */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY
+  * @{
+  */
+#define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Freeze IWDG counter in STANDBY mode */
+#define OB_IWDG_STDBY_ACTIVE FLASH_OPTSR_FZ_IWDG_SDBY  /*!< IWDG counter active in STANDBY mode */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level
+  * @{
+  */
+#define OB_BOR_LEVEL0        0x00000000U                /*!< Reset level threshold is set to 1.6V */
+#define OB_BOR_LEVEL1        FLASH_OPTSR_BOR_LEV_0      /*!< Reset level threshold is set to 2.1V */
+#define OB_BOR_LEVEL2        FLASH_OPTSR_BOR_LEV_1      /*!< Reset level threshold is set to 2.4V */
+#define OB_BOR_LEVEL3        (FLASH_OPTSR_BOR_LEV_1 | FLASH_OPTSR_BOR_LEV_0) /*!< Reset level threshold is set to 2.7V  */
+/**
+  * @}
+  */
+
+
+
+/** @defgroup FLASHEx_Boot_Address FLASH Boot Address
+  * @{
+  */
+#define OB_BOOTADDR_ITCM_RAM     0x0000U  /*!< Boot from ITCM RAM (0x00000000)                 */
+#define OB_BOOTADDR_SYSTEM       0x0040U  /*!< Boot from System memory bootloader (0x00100000) */
+#define OB_BOOTADDR_ITCM_FLASH   0x0080U  /*!< Boot from Flash on ITCM interface (0x00200000)  */
+#define OB_BOOTADDR_AXIM_FLASH   0x2000U  /*!< Boot from Flash on AXIM interface (0x08000000)  */
+#define OB_BOOTADDR_DTCM_RAM     0x8000U  /*!< Boot from DTCM RAM (0x20000000)                 */
+#define OB_BOOTADDR_SRAM1        0x8004U  /*!< Boot from SRAM1 (0x20010000)                    */
+#define OB_BOOTADDR_SRAM2        0x8013U  /*!< Boot from SRAM2 (0x2004C000)                    */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Latency FLASH Latency
+  * @{
+  */
+#define FLASH_LATENCY_0          FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero Latency cycle      */
+#define FLASH_LATENCY_1          FLASH_ACR_LATENCY_1WS   /*!< FLASH One Latency cycle       */
+#define FLASH_LATENCY_2          FLASH_ACR_LATENCY_2WS   /*!< FLASH Two Latency cycles      */
+#define FLASH_LATENCY_3          FLASH_ACR_LATENCY_3WS   /*!< FLASH Three Latency cycles    */
+#define FLASH_LATENCY_4          FLASH_ACR_LATENCY_4WS   /*!< FLASH Four Latency cycles     */
+#define FLASH_LATENCY_5          FLASH_ACR_LATENCY_5WS   /*!< FLASH Five Latency cycles     */
+#define FLASH_LATENCY_6          FLASH_ACR_LATENCY_6WS   /*!< FLASH Six Latency cycles      */
+#define FLASH_LATENCY_7          FLASH_ACR_LATENCY_7WS   /*!< FLASH Seven Latency cycles    */
+#define FLASH_LATENCY_8          FLASH_ACR_LATENCY_8WS   /*!< FLASH Eight Latency cycle     */
+#define FLASH_LATENCY_9          FLASH_ACR_LATENCY_9WS   /*!< FLASH Nine Latency cycle      */
+#define FLASH_LATENCY_10         FLASH_ACR_LATENCY_10WS  /*!< FLASH Ten Latency cycles      */
+#define FLASH_LATENCY_11         FLASH_ACR_LATENCY_11WS  /*!< FLASH Eleven Latency cycles   */
+#define FLASH_LATENCY_12         FLASH_ACR_LATENCY_12WS  /*!< FLASH Twelve Latency cycles   */
+#define FLASH_LATENCY_13         FLASH_ACR_LATENCY_13WS  /*!< FLASH Thirteen Latency cycles */
+#define FLASH_LATENCY_14         FLASH_ACR_LATENCY_14WS  /*!< FLASH Fourteen Latency cycles */
+#define FLASH_LATENCY_15         FLASH_ACR_LATENCY_15WS  /*!< FLASH Fifteen Latency cycles  */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Banks FLASH Banks
+  * @{
+  */
+#define FLASH_BANK_1             0x01U                         /*!< Bank 1   */
+#define FLASH_BANK_2             0x02U                         /*!< Bank 2   */
+#define FLASH_BANK_BOTH          (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2  */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_OB_PCROP_RDP  FLASHEx OB PCROP RDP
+  * @{
+  */
+#define OB_PCROP_RDP_NOT_ERASE   0x00000000U     /*!< PCROP area is not erased when the RDP level
+                                                      is decreased from Level 1 to Level 0 or during a mass erase */
+#define OB_PCROP_RDP_ERASE       FLASH_PRAR_DMEP /*!< PCROP area is erased when the RDP level is
+                                                      decreased from Level 1 to Level 0 (full mass erase) */
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
+  * @{
+  */
+#if (FLASH_SECTOR_TOTAL == 128)
+#define OB_WRP_SECTOR_0TO3       0x00000001U /*!< Write protection of Sector0  to Sector3    */
+#define OB_WRP_SECTOR_4TO7       0x00000002U /*!< Write protection of Sector4  to Sector7    */
+#define OB_WRP_SECTOR_8TO11      0x00000004U /*!< Write protection of Sector8  to Sector11   */
+#define OB_WRP_SECTOR_12TO15     0x00000008U /*!< Write protection of Sector12 to Sector15   */
+#define OB_WRP_SECTOR_16TO19     0x00000010U /*!< Write protection of Sector16 to Sector19   */
+#define OB_WRP_SECTOR_20TO23     0x00000020U /*!< Write protection of Sector20 to Sector23   */
+#define OB_WRP_SECTOR_24TO27     0x00000040U /*!< Write protection of Sector24 to Sector27   */
+#define OB_WRP_SECTOR_28TO31     0x00000080U /*!< Write protection of Sector28 to Sector31   */
+#define OB_WRP_SECTOR_32TO35     0x00000100U /*!< Write protection of Sector32 to Sector35   */
+#define OB_WRP_SECTOR_36TO39     0x00000200U /*!< Write protection of Sector36 to Sector39   */
+#define OB_WRP_SECTOR_40TO43     0x00000400U /*!< Write protection of Sector40 to Sector43   */
+#define OB_WRP_SECTOR_44TO47     0x00000800U /*!< Write protection of Sector44 to Sector47   */
+#define OB_WRP_SECTOR_48TO51     0x00001000U /*!< Write protection of Sector48 to Sector51   */
+#define OB_WRP_SECTOR_52TO55     0x00002000U /*!< Write protection of Sector52 to Sector55   */
+#define OB_WRP_SECTOR_56TO59     0x00004000U /*!< Write protection of Sector56 to Sector59   */
+#define OB_WRP_SECTOR_60TO63     0x00008000U /*!< Write protection of Sector60 to Sector63   */
+#define OB_WRP_SECTOR_64TO67     0x00010000U /*!< Write protection of Sector64 to Sector67   */
+#define OB_WRP_SECTOR_68TO71     0x00020000U /*!< Write protection of Sector68 to Sector71   */
+#define OB_WRP_SECTOR_72TO75     0x00040000U /*!< Write protection of Sector72 to Sector75   */
+#define OB_WRP_SECTOR_76TO79     0x00080000U /*!< Write protection of Sector76 to Sector79   */
+#define OB_WRP_SECTOR_80TO83     0x00100000U /*!< Write protection of Sector80 to Sector83   */
+#define OB_WRP_SECTOR_84TO87     0x00200000U /*!< Write protection of Sector84 to Sector87   */
+#define OB_WRP_SECTOR_88TO91     0x00400000U /*!< Write protection of Sector88 to Sector91   */
+#define OB_WRP_SECTOR_92TO95     0x00800000U /*!< Write protection of Sector92 to Sector95   */
+#define OB_WRP_SECTOR_96TO99     0x01000000U /*!< Write protection of Sector96  to Sector99  */
+#define OB_WRP_SECTOR_100TO103   0x02000000U /*!< Write protection of Sector100 to Sector103 */
+#define OB_WRP_SECTOR_104TO107   0x04000000U /*!< Write protection of Sector104 to Sector107 */
+#define OB_WRP_SECTOR_108TO111   0x08000000U /*!< Write protection of Sector108 to Sector111 */
+#define OB_WRP_SECTOR_112TO115   0x10000000U /*!< Write protection of Sector112 to Sector115 */
+#define OB_WRP_SECTOR_116TO119   0x20000000U /*!< Write protection of Sector116 to Sector119 */
+#define OB_WRP_SECTOR_120TO123   0x40000000U /*!< Write protection of Sector120 to Sector123 */
+#define OB_WRP_SECTOR_124TO127   0x80000000U /*!< Write protection of Sector124 to Sector127 */
+#define OB_WRP_SECTOR_ALL        0xFFFFFFFFU /*!< Write protection of all Sectors            */
+#else
+#define OB_WRP_SECTOR_0          0x00000001U /*!< Write protection of Sector0                */
+#define OB_WRP_SECTOR_1          0x00000002U /*!< Write protection of Sector1                */
+#define OB_WRP_SECTOR_2          0x00000004U /*!< Write protection of Sector2                */
+#define OB_WRP_SECTOR_3          0x00000008U /*!< Write protection of Sector3                */
+#define OB_WRP_SECTOR_4          0x00000010U /*!< Write protection of Sector4                */
+#define OB_WRP_SECTOR_5          0x00000020U /*!< Write protection of Sector5                */
+#define OB_WRP_SECTOR_6          0x00000040U /*!< Write protection of Sector6                */
+#define OB_WRP_SECTOR_7          0x00000080U /*!< Write protection of Sector7                */
+#define OB_WRP_SECTOR_ALL        0x000000FFU /*!< Write protection of all Sectors            */
+#endif /* FLASH_SECTOR_TOTAL == 128 */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_OB_SECURITY  FLASHEx OB SECURITY
+  * @{
+  */
+#define OB_SECURITY_DISABLE   0x00000000U             /*!< security enabled */
+#define OB_SECURITY_ENABLE    FLASH_OPTSR_SECURITY    /*!< security disabled */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_OB_ST_RAM_SIZE  FLASHEx OB ST RAM SIZE
+  * @{
+  */
+#define OB_ST_RAM_SIZE_2KB    0x00000000U               /*!< 2 Kbytes reserved to ST code */
+#define OB_ST_RAM_SIZE_4KB    FLASH_OPTSR_ST_RAM_SIZE_0 /*!< 4 Kbytes reserved to ST code */
+#define OB_ST_RAM_SIZE_8KB    FLASH_OPTSR_ST_RAM_SIZE_1 /*!< 8 Kbytes reserved to ST code */
+#define OB_ST_RAM_SIZE_16KB   FLASH_OPTSR_ST_RAM_SIZE   /*!< 16 Kbytes reserved to ST code */
+/**
+  * @}
+  */
+
+#if defined(DUAL_CORE)
+/** @defgroup FLASHEx_OB_BCM7  FLASHEx OB BCM7
+  * @{
+  */
+#define OB_BCM7_DISABLE       0x00000000U              /*!< CM7 Boot disabled */
+#define OB_BCM7_ENABLE        FLASH_OPTSR_BCM7         /*!< CM7 Boot enabled */
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_OB_BCM4  FLASHEx OB BCM4
+  * @{
+  */
+#define OB_BCM4_DISABLE       0x00000000U              /*!< CM4 Boot disabled */
+#define OB_BCM4_ENABLE        FLASH_OPTSR_BCM4         /*!< CM4 Boot enabled */
+/**
+  * @}
+  */
+#endif /* DUAL_CORE */
+
+/** @defgroup FLASHEx_OB_IWDG1_SW  FLASHEx OB IWDG1 SW
+  * @{
+  */
+#define OB_IWDG1_SW            FLASH_OPTSR_IWDG1_SW /*!< Hardware independent watchdog 1 */
+#define OB_IWDG1_HW            0x00000000U          /*!< Software independent watchdog 1 */
+/**
+  * @}
+  */
+
+#if defined(DUAL_CORE)
+/** @defgroup FLASHEx_OB_IWDG2_SW  FLASHEx OB IWDG2 SW
+  * @{
+  */
+#define OB_IWDG2_SW            FLASH_OPTSR_IWDG2_SW  /*!< Hardware independent watchdog 2*/
+#define OB_IWDG2_HW            0x00000000U           /*!< Software independent watchdog 2*/
+/**
+  * @}
+  */
+#endif
+
+/** @defgroup FLASHEx_OB_NRST_STOP_D1  FLASHEx OB NRST STOP D1
+  * @{
+  */
+#define OB_STOP_RST_D1         0x00000000U              /*!< Reset generated when entering the D1 to stop mode */
+#define OB_STOP_NO_RST_D1      FLASH_OPTSR_NRST_STOP_D1 /*!< No reset generated when entering the D1 to stop mode */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_OB_NRST_STDBY_D1  FLASHEx OB NRST STDBY D1
+  * @{
+  */
+#define OB_STDBY_RST_D1        0x00000000U              /*!< Reset generated when entering the D1 to standby mode */
+#define OB_STDBY_NO_RST_D1     FLASH_OPTSR_NRST_STBY_D1 /*!< No reset generated when entering the D1 to standby mode */
+/**
+  * @}
+  */
+
+#if defined (DUAL_CORE)
+/** @defgroup FLASHEx_OB_NRST_STOP_D2  FLASHEx OB NRST STOP D2
+  * @{
+  */
+#define OB_STOP_RST_D2         0x00000000U              /*!< Reset generated when entering the D2 to stop mode */
+#define OB_STOP_NO_RST_D2      FLASH_OPTSR_NRST_STOP_D2 /*!< No reset generated when entering the D2 to stop mode */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_OB_NRST_STDBY_D2  FLASHEx OB NRST STDBY D2
+  * @{
+  */
+#define OB_STDBY_RST_D2        0x00000000U              /*!< Reset generated when entering the D2 to standby mode */
+#define OB_STDBY_NO_RST_D2     FLASH_OPTSR_NRST_STBY_D2 /*!< No reset generated when entering the D2 to standby mode */
+/**
+  * @}
+  */
+#endif /* DUAL_CORE */
+
+/** @defgroup FLASHEx_OB_SWAP_BANK  FLASHEx OB SWAP BANK
+  * @{
+  */
+#define OB_SWAP_BANK_DISABLE   0x00000000U               /*!< Bank swap disabled */
+#define OB_SWAP_BANK_ENABLE    FLASH_OPTSR_SWAP_BANK_OPT /*!< Bank swap enabled */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_OB_IOHSLV FLASHEx OB IOHSLV
+  * @{
+  */
+#define OB_IOHSLV_DISABLE      0x00000000U         /*!< IOHSLV disabled */
+#define OB_IOHSLV_ENABLE       FLASH_OPTSR_IO_HSLV /*!< IOHSLV enabled */
+/**
+  * @}
+  */
+
+#if defined (FLASH_OPTSR_VDDMMC_HSLV)
+/** @defgroup FLASHEx_OB_VDDMMC_HSLV FLASHEx OB VDDMMC HSLV
+  * @{
+  */
+#define OB_VDDMMC_HSLV_DISABLE 0x00000000U             /*!< VDDMMC HSLV disabled */
+#define OB_VDDMMC_HSLV_ENABLE  FLASH_OPTSR_VDDMMC_HSLV /*!< VDDMMC HSLV enabled */
+/**
+  * @}
+  */
+#endif /* FLASH_OPTSR_VDDMMC_HSLV */
+
+/** @defgroup FLASHEx_OB_BOOT_OPTION  FLASHEx OB BOOT OPTION
+  * @{
+  */
+#define OB_BOOT_ADD0           0x01U       /*!< Select Boot Address 0 */
+#define OB_BOOT_ADD1           0x02U       /*!< Select Boot Address 1 */
+#define OB_BOOT_ADD_BOTH       0x03U       /*!< Select Boot Address 0 and 1 */
+/**
+  * @}
+  */
+
+ /** @defgroup FLASHEx_OB_USER_Type  FLASHEx OB USER Type
+  * @{
+  */
+#define OB_USER_IWDG1_SW          0x0001U /*!< Independent watchdog selection */
+#define OB_USER_NRST_STOP_D1      0x0002U /*!< Reset when entering Stop mode selection*/
+#define OB_USER_NRST_STDBY_D1     0x0004U /*!< Reset when entering standby mode selection*/
+#define OB_USER_IWDG_STOP         0x0008U /*!< Independent watchdog counter freeze in stop mode */
+#define OB_USER_IWDG_STDBY        0x0010U /*!< Independent watchdog counter freeze in standby mode */
+#define OB_USER_ST_RAM_SIZE       0x0020U /*!< dedicated DTCM Ram size selection */
+#define OB_USER_SECURITY          0x0040U /*!< security selection */
+#define OB_USER_IOHSLV            0x0080U /*!< IO HSLV selection */
+#define OB_USER_SWAP_BANK         0x0100U /*!< Bank swap selection */
+#if defined (FLASH_OPTSR_VDDMMC_HSLV)
+#define OB_USER_VDDMMC_HSLV       0x0200U /*!< VDDMMC HSLV selection */
+#endif /* FLASH_OPTSR_VDDMMC_HSLV */
+#if defined (DUAL_CORE)
+#define OB_USER_IWDG2_SW          0x0200U /*!< Window watchdog selection */
+#define OB_USER_BCM4              0x0400U /*!< CM4 boot selection */
+#define OB_USER_BCM7              0x0800U /*!< CM7 boot selection */
+#define OB_USER_NRST_STOP_D2      0x1000U /*!< Reset when entering Stop mode selection*/
+#define OB_USER_NRST_STDBY_D2     0x2000U /*!< Reset when entering standby mode selection*/
+#endif /*DUAL_CORE*/
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_OB_SECURE_RDP  FLASHEx OB SECURE RDP
+  * @{
+  */
+#define OB_SECURE_RDP_NOT_ERASE   0x00000000U     /*!< Secure area is not erased when the RDP level
+                                                       is decreased from Level 1 to Level 0 or during a mass erase */
+#define OB_SECURE_RDP_ERASE       FLASH_SCAR_DMES /*!< Secure area is erased when the RDP level is
+                                                       decreased from Level 1 to Level 0 (full mass erase) */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_CRC_Selection_Type FLASH CRC Selection Type
+  * @{
+  */
+#define FLASH_CRC_ADDR         0x00000000U              /*!< CRC selection type by address  */
+#define FLASH_CRC_SECTORS      FLASH_CRCCR_CRC_BY_SECT  /*!< CRC selection type by sectors  */
+#define FLASH_CRC_BANK         (FLASH_CRCCR_ALL_BANK | FLASH_CRCCR_CRC_BY_SECT) /*!< CRC selection type by bank */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_CRC_Burst_Size FLASH CRC Burst Size
+  * @{
+  */
+#define FLASH_CRC_BURST_SIZE_4    0x00000000U              /*!< Every burst has a size of 4 Flash words (256-bit)  */
+#define FLASH_CRC_BURST_SIZE_16   FLASH_CRCCR_CRC_BURST_0  /*!< Every burst has a size of 16 Flash words (256-bit)   */
+#define FLASH_CRC_BURST_SIZE_64   FLASH_CRCCR_CRC_BURST_1  /*!< Every burst has a size of 64 Flash words (256-bit)   */
+#define FLASH_CRC_BURST_SIZE_256  FLASH_CRCCR_CRC_BURST    /*!< Every burst has a size of 256 Flash words (256-bit) */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Programming_Delay FLASH Programming Delay
+  * @{
+  */
+#define FLASH_PROGRAMMING_DELAY_0   0x00000000U            /*!< programming delay set for Flash running at 70 MHz or below          */
+#define FLASH_PROGRAMMING_DELAY_1   FLASH_ACR_WRHIGHFREQ_0 /*!< programming delay set for Flash running between 70 MHz and 185 MHz  */
+#define FLASH_PROGRAMMING_DELAY_2   FLASH_ACR_WRHIGHFREQ_1 /*!< programming delay set for Flash running between 185 MHz and 225 MHz */
+#define FLASH_PROGRAMMING_DELAY_3   FLASH_ACR_WRHIGHFREQ   /*!< programming delay set for Flash at startup */
+/**
+  * @}
+  */
+
+#if defined (FLASH_OTPBL_LOCKBL)
+/** @defgroup FLASHEx_OTP_Blocks FLASH OTP blocks
+  * @{
+  */
+#define FLASH_OTP_BLOCK_0          0x00000001U /*!< OTP Block0     */
+#define FLASH_OTP_BLOCK_1          0x00000002U /*!< OTP Block1     */
+#define FLASH_OTP_BLOCK_2          0x00000004U /*!< OTP Block2     */
+#define FLASH_OTP_BLOCK_3          0x00000008U /*!< OTP Block3     */
+#define FLASH_OTP_BLOCK_4          0x00000010U /*!< OTP Block4     */
+#define FLASH_OTP_BLOCK_5          0x00000020U /*!< OTP Block5     */
+#define FLASH_OTP_BLOCK_6          0x00000040U /*!< OTP Block6     */
+#define FLASH_OTP_BLOCK_7          0x00000080U /*!< OTP Block7     */
+#define FLASH_OTP_BLOCK_8          0x00000100U /*!< OTP Block8     */
+#define FLASH_OTP_BLOCK_9          0x00000200U /*!< OTP Block9     */
+#define FLASH_OTP_BLOCK_10         0x00000400U /*!< OTP Block10    */
+#define FLASH_OTP_BLOCK_11         0x00000800U /*!< OTP Block11    */
+#define FLASH_OTP_BLOCK_12         0x00001000U /*!< OTP Block12    */
+#define FLASH_OTP_BLOCK_13         0x00002000U /*!< OTP Block13    */
+#define FLASH_OTP_BLOCK_14         0x00004000U /*!< OTP Block14    */
+#define FLASH_OTP_BLOCK_15         0x00008000U /*!< OTP Block15    */
+#define FLASH_OTP_BLOCK_ALL        0x0000FFFFU /*!< OTP All Blocks */
+/**
+  * @}
+  */
+#endif /* FLASH_OTPBL_LOCKBL */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Macros FLASH Exported Macros
+  * @{
+  */
+/**
+  * @brief  Calculate the FLASH Boot Base Adress (BOOT_ADD0 or BOOT_ADD1)
+  * @note   Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14].
+  * @param  __ADDRESS__: FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB)
+  * @retval The FLASH Boot Base Adress
+  */
+#define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14U)
+ /**
+  * @}
+  */
+
+#if defined (FLASH_CR_PSIZE)
+/**
+  * @brief  Set the FLASH Program/Erase parallelism.
+  * @param  __PSIZE__ FLASH Program/Erase parallelism
+  *         This parameter can be a value of @ref FLASH_Program_Parallelism
+  * @param  __BANK__: Flash bank (FLASH_BANK_1 or FLASH_BANK_2)
+  * @retval none
+  */
+#define __HAL_FLASH_SET_PSIZE(__PSIZE__, __BANK__) (((__BANK__) == FLASH_BANK_1)  ? \
+                              MODIFY_REG(FLASH->CR1, FLASH_CR_PSIZE, (__PSIZE__)) : \
+                              MODIFY_REG(FLASH->CR2, FLASH_CR_PSIZE, (__PSIZE__)))
+
+/**
+  * @brief  Get the FLASH Program/Erase parallelism.
+  * @param  __BANK__ Flash bank (FLASH_BANK_1 or FLASH_BANK_2)
+  * @retval FLASH Program/Erase parallelism
+  *         This return value can be a value of @ref FLASH_Program_Parallelism
+  */
+#define __HAL_FLASH_GET_PSIZE(__BANK__) (((__BANK__) == FLASH_BANK_1) ? \
+                              READ_BIT((FLASH->CR1), FLASH_CR_PSIZE)  : \
+                              READ_BIT((FLASH->CR2), FLASH_CR_PSIZE))
+#endif /* FLASH_CR_PSIZE */
+
+/**
+  * @brief  Set the FLASH Programming Delay.
+  * @param  __DELAY__ FLASH Programming Delay
+  *         This parameter can be a value of @ref FLASHEx_Programming_Delay
+  * @retval none
+  */
+#define __HAL_FLASH_SET_PROGRAM_DELAY(__DELAY__)  MODIFY_REG(FLASH->ACR, FLASH_ACR_WRHIGHFREQ, (__DELAY__))
+
+/**
+  * @brief  Get the FLASH Programming Delay.
+  * @retval FLASH Programming Delay
+  *         This return value can be a value of @ref FLASHEx_Programming_Delay
+  */
+#define __HAL_FLASH_GET_PROGRAM_DELAY()     READ_BIT(FLASH->ACR, FLASH_ACR_WRHIGHFREQ)
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASHEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup FLASHEx_Exported_Functions_Group1
+  * @{
+  */
+/* Extension Program operation functions  *************************************/
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError);
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
+void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
+
+HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank1(void);
+HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1(void);
+HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank2(void);
+HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank2(void);
+
+HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_t *CRC_Result);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros
+  * @{
+  */
+
+/** @defgroup FLASHEx_IS_FLASH_Definitions FLASHEx Private macros to check input parameters
+  * @{
+  */
+
+#define IS_FLASH_TYPEERASE(VALUE)        (((VALUE) == FLASH_TYPEERASE_SECTORS) || \
+                                          ((VALUE) == FLASH_TYPEERASE_MASSERASE))
+
+#if defined (FLASH_CR_PSIZE)
+#define IS_VOLTAGERANGE(RANGE)           (((RANGE) == FLASH_VOLTAGE_RANGE_1) || \
+                                          ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \
+                                          ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \
+                                          ((RANGE) == FLASH_VOLTAGE_RANGE_4))
+#endif /* FLASH_CR_PSIZE */
+
+#define IS_WRPSTATE(VALUE)               (((VALUE) == OB_WRPSTATE_DISABLE) || \
+                                          ((VALUE) == OB_WRPSTATE_ENABLE))
+
+#if defined (FLASH_OPTSR_VDDMMC_HSLV)
+#define IS_OPTIONBYTE(VALUE)             (((VALUE) <= 0x03FFU) && ((VALUE) != 0U))
+#elif defined (DUAL_CORE)
+#define IS_OPTIONBYTE(VALUE)             (((VALUE) <= 0x3FFFU) && ((VALUE) != 0U))
+#else
+#define IS_OPTIONBYTE(VALUE)             (((VALUE) <= 0x01FFU) && ((VALUE) != 0U))
+#endif /*DUAL_CORE*/
+
+#define IS_OB_BOOT_ADDRESS(ADDRESS)      ((ADDRESS) <= 0x8013U)
+
+#define IS_OB_RDP_LEVEL(LEVEL)           (((LEVEL) == OB_RDP_LEVEL_0)   ||\
+                                          ((LEVEL) == OB_RDP_LEVEL_1)   ||\
+                                          ((LEVEL) == OB_RDP_LEVEL_2))
+
+#define IS_OB_WWDG_SOURCE(SOURCE)        (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW))
+
+#define IS_OB_IWDG_SOURCE(SOURCE)        (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+
+#define IS_OB_STOP_SOURCE(SOURCE)        (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
+
+#define IS_OB_STDBY_SOURCE(SOURCE)       (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
+
+#define IS_OB_IWDG_STOP_FREEZE(FREEZE)   (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE))
+
+#define IS_OB_IWDG_STDBY_FREEZE(FREEZE)  (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE))
+
+#define IS_OB_BOR_LEVEL(LEVEL)           (((LEVEL) == OB_BOR_LEVEL0) || ((LEVEL) == OB_BOR_LEVEL1) || \
+                                          ((LEVEL) == OB_BOR_LEVEL2) || ((LEVEL) == OB_BOR_LEVEL3))
+
+#define IS_FLASH_LATENCY(LATENCY)        (((LATENCY) == FLASH_LATENCY_0)  || \
+                                          ((LATENCY) == FLASH_LATENCY_1)  || \
+                                          ((LATENCY) == FLASH_LATENCY_2)  || \
+                                          ((LATENCY) == FLASH_LATENCY_3)  || \
+                                          ((LATENCY) == FLASH_LATENCY_4)  || \
+                                          ((LATENCY) == FLASH_LATENCY_5)  || \
+                                          ((LATENCY) == FLASH_LATENCY_6)  || \
+                                          ((LATENCY) == FLASH_LATENCY_7)  || \
+                                          ((LATENCY) == FLASH_LATENCY_8)  || \
+                                          ((LATENCY) == FLASH_LATENCY_9)  || \
+                                          ((LATENCY) == FLASH_LATENCY_10) || \
+                                          ((LATENCY) == FLASH_LATENCY_11) || \
+                                          ((LATENCY) == FLASH_LATENCY_12) || \
+                                          ((LATENCY) == FLASH_LATENCY_13) || \
+                                          ((LATENCY) == FLASH_LATENCY_14) || \
+                                          ((LATENCY) == FLASH_LATENCY_15))
+
+#define IS_FLASH_SECTOR(SECTOR)          ((SECTOR) < FLASH_SECTOR_TOTAL)
+
+#if (FLASH_SECTOR_TOTAL == 8U)
+#define IS_OB_WRP_SECTOR(SECTOR)         ((((SECTOR) & 0xFFFFFF00U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
+#else
+#define IS_OB_WRP_SECTOR(SECTOR)         ((SECTOR) != 0x00000000U)
+#endif /* FLASH_SECTOR_TOTAL == 8U */
+
+#define IS_OB_PCROP_RDP(CONFIG)          (((CONFIG) == OB_PCROP_RDP_NOT_ERASE) || \
+                                          ((CONFIG) == OB_PCROP_RDP_ERASE))
+
+#define IS_OB_SECURE_RDP(CONFIG)         (((CONFIG) == OB_SECURE_RDP_NOT_ERASE) || \
+                                          ((CONFIG) == OB_SECURE_RDP_ERASE))
+
+#define IS_OB_USER_SWAP_BANK(VALUE)      (((VALUE) == OB_SWAP_BANK_DISABLE) || ((VALUE) == OB_SWAP_BANK_ENABLE))
+
+#define IS_OB_USER_IOHSLV(VALUE)         (((VALUE) == OB_IOHSLV_DISABLE) || ((VALUE) == OB_IOHSLV_ENABLE))
+
+#if defined (FLASH_OPTSR_VDDMMC_HSLV)
+#define IS_OB_USER_VDDMMC_HSLV(VALUE)    (((VALUE) == OB_VDDMMC_HSLV_DISABLE) || ((VALUE) == OB_VDDMMC_HSLV_ENABLE))
+#endif /* FLASH_OPTSR_VDDMMC_HSLV */
+
+#define IS_OB_IWDG1_SOURCE(SOURCE)       (((SOURCE) == OB_IWDG1_SW) || ((SOURCE) == OB_IWDG1_HW))
+#if defined (DUAL_CORE)
+#define IS_OB_IWDG2_SOURCE(SOURCE)       (((SOURCE) == OB_IWDG2_SW) || ((SOURCE) == OB_IWDG2_HW))
+#endif /* DUAL_CORE */
+#define IS_OB_STOP_D1_RESET(VALUE)       (((VALUE) == OB_STOP_NO_RST_D1) || ((VALUE) == OB_STOP_RST_D1))
+
+#define IS_OB_STDBY_D1_RESET(VALUE)      (((VALUE) == OB_STDBY_NO_RST_D1) || ((VALUE) == OB_STDBY_RST_D1))
+
+#define IS_OB_USER_IWDG_STOP(VALUE)      (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_ACTIVE))
+
+#define IS_OB_USER_IWDG_STDBY(VALUE)     (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_ACTIVE))
+
+#define IS_OB_USER_ST_RAM_SIZE(VALUE)    (((VALUE) == OB_ST_RAM_SIZE_2KB) || ((VALUE) == OB_ST_RAM_SIZE_4KB) || \
+                                          ((VALUE) == OB_ST_RAM_SIZE_8KB) || ((VALUE) == OB_ST_RAM_SIZE_16KB))
+
+#define IS_OB_USER_SECURITY(VALUE)       (((VALUE) == OB_SECURITY_ENABLE) || ((VALUE) == OB_SECURITY_DISABLE))
+
+#if defined (DUAL_CORE)
+#define IS_OB_USER_BCM4(VALUE)           (((VALUE) == OB_BCM4_DISABLE) || ((VALUE) == OB_BCM4_ENABLE))
+
+#define IS_OB_USER_BCM7(VALUE)           (((VALUE) == OB_BCM7_DISABLE) || ((VALUE) == OB_BCM7_ENABLE))
+
+#define IS_OB_STOP_D2_RESET(VALUE)       (((VALUE) == OB_STOP_NO_RST_D2) || ((VALUE) == OB_STOP_RST_D2))
+
+#define IS_OB_STDBY_D2_RESET(VALUE)      (((VALUE) == OB_STDBY_NO_RST_D2) || ((VALUE) == OB_STDBY_RST_D2))
+#endif /* DUAL_CORE */
+#if defined (DUAL_CORE)
+#define IS_OB_USER_TYPE(TYPE)            (((TYPE) <= (uint32_t)0x3FFFU) && ((TYPE) != 0U))
+#else
+#define IS_OB_USER_TYPE(TYPE)            (((TYPE) <= (uint32_t)0x73FU) && ((TYPE) != 0U))
+#endif /* DUAL_CORE */
+
+#define IS_OB_BOOT_ADD_OPTION(VALUE)     (((VALUE) == OB_BOOT_ADD0)  || \
+                                          ((VALUE) == OB_BOOT_ADD1)  || \
+                                          ((VALUE) == OB_BOOT_ADD_BOTH))
+
+#define IS_FLASH_TYPECRC(VALUE)          (((VALUE) == FLASH_CRC_ADDR)    || \
+                                          ((VALUE) == FLASH_CRC_SECTORS) || \
+                                          ((VALUE) == FLASH_CRC_BANK))
+
+#if defined (FLASH_OTPBL_LOCKBL)
+#define IS_OTP_BLOCK(VALUE)              ((((VALUE) & 0xFFFF0000U) == 0x00000000U) && ((VALUE) != 0x00000000U))
+#endif /* FLASH_OTPBL_LOCKBL */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
+  * @{
+  */
+void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_FLASH_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h
new file mode 100644
index 00000000..c1855665
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h
@@ -0,0 +1,346 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_gpio.h
+  * @author  MCD Application Team
+  * @brief   Header file of GPIO HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_GPIO_H
+#define STM32H7xx_HAL_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup GPIO
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Types GPIO Exported Types
+  * @{
+  */
+
+/**
+  * @brief   GPIO Init structure definition
+  */
+typedef struct
+{
+  uint32_t Pin;       /*!< Specifies the GPIO pins to be configured.
+                           This parameter can be any value of @ref GPIO_pins_define */
+
+  uint32_t Mode;      /*!< Specifies the operating mode for the selected pins.
+                           This parameter can be a value of @ref GPIO_mode_define */
+
+  uint32_t Pull;      /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
+                           This parameter can be a value of @ref GPIO_pull_define */
+
+  uint32_t Speed;     /*!< Specifies the speed for the selected pins.
+                           This parameter can be a value of @ref GPIO_speed_define */
+
+  uint32_t Alternate;  /*!< Peripheral to be connected to the selected pins.
+                            This parameter can be a value of @ref GPIO_Alternate_function_selection */
+} GPIO_InitTypeDef;
+
+/**
+  * @brief  GPIO Bit SET and Bit RESET enumeration
+  */
+typedef enum
+{
+  GPIO_PIN_RESET = 0U,
+  GPIO_PIN_SET
+} GPIO_PinState;
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Constants  GPIO Exported Constants
+  * @{
+  */
+
+/** @defgroup GPIO_pins_define  GPIO pins define
+  * @{
+  */
+#define GPIO_PIN_0                 ((uint16_t)0x0001)  /* Pin 0 selected    */
+#define GPIO_PIN_1                 ((uint16_t)0x0002)  /* Pin 1 selected    */
+#define GPIO_PIN_2                 ((uint16_t)0x0004)  /* Pin 2 selected    */
+#define GPIO_PIN_3                 ((uint16_t)0x0008)  /* Pin 3 selected    */
+#define GPIO_PIN_4                 ((uint16_t)0x0010)  /* Pin 4 selected    */
+#define GPIO_PIN_5                 ((uint16_t)0x0020)  /* Pin 5 selected    */
+#define GPIO_PIN_6                 ((uint16_t)0x0040)  /* Pin 6 selected    */
+#define GPIO_PIN_7                 ((uint16_t)0x0080)  /* Pin 7 selected    */
+#define GPIO_PIN_8                 ((uint16_t)0x0100)  /* Pin 8 selected    */
+#define GPIO_PIN_9                 ((uint16_t)0x0200)  /* Pin 9 selected    */
+#define GPIO_PIN_10                ((uint16_t)0x0400)  /* Pin 10 selected   */
+#define GPIO_PIN_11                ((uint16_t)0x0800)  /* Pin 11 selected   */
+#define GPIO_PIN_12                ((uint16_t)0x1000)  /* Pin 12 selected   */
+#define GPIO_PIN_13                ((uint16_t)0x2000)  /* Pin 13 selected   */
+#define GPIO_PIN_14                ((uint16_t)0x4000)  /* Pin 14 selected   */
+#define GPIO_PIN_15                ((uint16_t)0x8000)  /* Pin 15 selected   */
+#define GPIO_PIN_All               ((uint16_t)0xFFFF)  /* All pins selected */
+
+#define GPIO_PIN_MASK              (0x0000FFFFU) /* PIN mask for assert test */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_mode_define  GPIO mode define
+  * @brief GPIO Configuration Mode
+  *        Elements values convention: 0xX0yz00YZ
+  *           - X  : GPIO mode or EXTI Mode
+  *           - y  : External IT or Event trigger detection
+  *           - z  : IO configuration on External IT or Event
+  *           - Y  : Output type (Push Pull or Open Drain)
+  *           - Z  : IO Direction mode (Input, Output, Alternate or Analog)
+  * @{
+  */
+#define  GPIO_MODE_INPUT                        (0x00000000U)   /*!< Input Floating Mode                   */
+#define  GPIO_MODE_OUTPUT_PP                    (0x00000001U)   /*!< Output Push Pull Mode                 */
+#define  GPIO_MODE_OUTPUT_OD                    (0x00000011U)   /*!< Output Open Drain Mode                */
+#define  GPIO_MODE_AF_PP                        (0x00000002U)   /*!< Alternate Function Push Pull Mode     */
+#define  GPIO_MODE_AF_OD                        (0x00000012U)   /*!< Alternate Function Open Drain Mode    */
+
+#define  GPIO_MODE_ANALOG                       (0x00000003U)   /*!< Analog Mode  */
+
+#define  GPIO_MODE_IT_RISING                    (0x11110000U)   /*!< External Interrupt Mode with Rising edge trigger detection          */
+#define  GPIO_MODE_IT_FALLING                   (0x11210000U)   /*!< External Interrupt Mode with Falling edge trigger detection         */
+#define  GPIO_MODE_IT_RISING_FALLING            (0x11310000U)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */
+
+#define  GPIO_MODE_EVT_RISING                   (0x11120000U)   /*!< External Event Mode with Rising edge trigger detection               */
+#define  GPIO_MODE_EVT_FALLING                  (0x11220000U)   /*!< External Event Mode with Falling edge trigger detection              */
+#define  GPIO_MODE_EVT_RISING_FALLING           (0x11320000U)   /*!< External Event Mode with Rising/Falling edge trigger detection       */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_speed_define  GPIO speed define
+  * @brief GPIO Output Maximum frequency
+  * @{
+  */
+#define  GPIO_SPEED_FREQ_LOW         (0x00000000U)  /*!< Low speed     */
+#define  GPIO_SPEED_FREQ_MEDIUM      (0x00000001U)  /*!< Medium speed  */
+#define  GPIO_SPEED_FREQ_HIGH        (0x00000002U)  /*!< Fast speed    */
+#define  GPIO_SPEED_FREQ_VERY_HIGH   (0x00000003U)  /*!< High speed    */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_pull_define  GPIO pull define
+  * @brief GPIO Pull-Up or Pull-Down Activation
+  * @{
+  */
+#define  GPIO_NOPULL        (0x00000000U)   /*!< No Pull-up or Pull-down activation  */
+#define  GPIO_PULLUP        (0x00000001U)   /*!< Pull-up activation                  */
+#define  GPIO_PULLDOWN      (0x00000002U)   /*!< Pull-down activation                */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
+  * @{
+  */
+
+/**
+  * @brief  Checks whether the specified EXTI line flag is set or not.
+  * @param  __EXTI_LINE__: specifies the EXTI line flag to check.
+  *         This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval The new state of __EXTI_LINE__ (SET or RESET).
+  */
+#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
+
+/**
+  * @brief  Clears the EXTI's line pending flags.
+  * @param  __EXTI_LINE__: specifies the EXTI lines flags to clear.
+  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
+
+/**
+  * @brief  Checks whether the specified EXTI line is asserted or not.
+  * @param  __EXTI_LINE__: specifies the EXTI line to check.
+  *          This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval The new state of __EXTI_LINE__ (SET or RESET).
+  */
+#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
+
+/**
+  * @brief  Clears the EXTI's line pending bits.
+  * @param  __EXTI_LINE__: specifies the EXTI lines to clear.
+  *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Checks whether the specified EXTI line flag is set or not.
+  * @param  __EXTI_LINE__: specifies the EXTI line flag to check.
+  *         This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval The new state of __EXTI_LINE__ (SET or RESET).
+  */
+#define __HAL_GPIO_EXTID2_GET_FLAG(__EXTI_LINE__) (EXTI->C2PR1 & (__EXTI_LINE__))
+
+/**
+  * @brief  Clears the EXTI's line pending flags.
+  * @param  __EXTI_LINE__: specifies the EXTI lines flags to clear.
+  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTID2_CLEAR_FLAG(__EXTI_LINE__) (EXTI->C2PR1 = (__EXTI_LINE__))
+
+/**
+  * @brief  Checks whether the specified EXTI line is asserted or not.
+  * @param  __EXTI_LINE__: specifies the EXTI line to check.
+  *          This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval The new state of __EXTI_LINE__ (SET or RESET).
+  */
+#define __HAL_GPIO_EXTID2_GET_IT(__EXTI_LINE__) (EXTI->C2PR1 & (__EXTI_LINE__))
+
+/**
+  * @brief  Clears the EXTI's line pending bits.
+  * @param  __EXTI_LINE__: specifies the EXTI lines to clear.
+  *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTID2_CLEAR_IT(__EXTI_LINE__) (EXTI->C2PR1 = (__EXTI_LINE__))
+#endif
+
+/**
+  * @brief  Generates a Software interrupt on selected EXTI line.
+  * @param  __EXTI_LINE__: specifies the EXTI line to check.
+  *          This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__))
+/**
+  * @}
+  */
+
+/* Include GPIO HAL Extension module */
+#include "stm32h7xx_hal_gpio_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup GPIO_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup GPIO_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de-initialization functions *****************************/
+void  HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init);
+void  HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin);
+/**
+  * @}
+  */
+
+/** @addtogroup GPIO_Exported_Functions_Group2
+  * @{
+  */
+/* IO operation functions *****************************************************/
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
+void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup GPIO_Private_Constants GPIO Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup GPIO_Private_Macros GPIO Private Macros
+  * @{
+  */
+#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
+#define IS_GPIO_PIN(__PIN__)        ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
+                                     (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT)              ||\
+                            ((MODE) == GPIO_MODE_OUTPUT_PP)          ||\
+                            ((MODE) == GPIO_MODE_OUTPUT_OD)          ||\
+                            ((MODE) == GPIO_MODE_AF_PP)              ||\
+                            ((MODE) == GPIO_MODE_AF_OD)              ||\
+                            ((MODE) == GPIO_MODE_IT_RISING)          ||\
+                            ((MODE) == GPIO_MODE_IT_FALLING)         ||\
+                            ((MODE) == GPIO_MODE_IT_RISING_FALLING)  ||\
+                            ((MODE) == GPIO_MODE_EVT_RISING)         ||\
+                            ((MODE) == GPIO_MODE_EVT_FALLING)        ||\
+                            ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
+                            ((MODE) == GPIO_MODE_ANALOG))
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW)  || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \
+                              ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH))
+
+#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
+                            ((PULL) == GPIO_PULLDOWN))
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup GPIO_Private_Functions GPIO Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_GPIO_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h
new file mode 100644
index 00000000..ff2efb3c
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h
@@ -0,0 +1,428 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_gpio_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of GPIO HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_GPIO_EX_H
+#define STM32H7xx_HAL_GPIO_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup GPIOEx GPIOEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants
+  * @{
+  */
+
+/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection
+  * @{
+  */
+
+/**
+  * @brief   AF 0 selection
+  */
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                                                     */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping                                          */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping                                           */
+#define GPIO_AF0_LCDBIAS       ((uint8_t)0x00)  /* LCDBIAS Alternate Function mapping                                                      */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                                                        */
+#if defined (PWR_CPUCR_PDDS_D2) /* PWR D1 and D2 domains exists */
+#define GPIO_AF0_C1DSLEEP      ((uint8_t)0x00)  /* Cortex-M7 Deep Sleep Alternate Function mapping : available on STM32H7 Rev.B and above  */
+#define GPIO_AF0_C1SLEEP       ((uint8_t)0x00)  /* Cortex-M7 Sleep Alternate Function mapping : available on STM32H7 Rev.B and above       */
+#define GPIO_AF0_D1PWREN       ((uint8_t)0x00)  /* Domain 1 PWR enable Alternate Function mapping : available on STM32H7 Rev.B and above   */
+#define GPIO_AF0_D2PWREN       ((uint8_t)0x00)  /* Domain 2 PWR enable Alternate Function mapping : available on STM32H7 Rev.B and above   */
+#if defined(DUAL_CORE)
+#define GPIO_AF0_C2DSLEEP      ((uint8_t)0x00)  /* Cortex-M4 Deep Sleep Alternate Function mapping : available on STM32H7 Rev.B and above  */
+#define GPIO_AF0_C2SLEEP       ((uint8_t)0x00)  /* Cortex-M4 Sleep Alternate Function mapping : available on STM32H7 Rev.B and above       */
+#endif /* DUAL_CORE */
+#endif /* PWR_CPUCR_PDDS_D2 */
+
+/**
+  * @brief   AF 1 selection
+  */
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping   */
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping   */
+#define GPIO_AF1_TIM16         ((uint8_t)0x01)  /* TIM16 Alternate Function mapping  */
+#define GPIO_AF1_TIM17         ((uint8_t)0x01)  /* TIM17 Alternate Function mapping  */
+#define GPIO_AF1_LPTIM1        ((uint8_t)0x01)  /* LPTIM1 Alternate Function mapping */
+#if defined(HRTIM1)
+#define GPIO_AF1_HRTIM1        ((uint8_t)0x01)  /* HRTIM1 Alternate Function mapping */
+#endif /* HRTIM1 */
+
+/**
+  * @brief   AF 2 selection
+  */
+#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping   */
+#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping   */
+#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping   */
+#define GPIO_AF2_TIM12         ((uint8_t)0x02)  /* TIM12 Alternate Function mapping  */
+#define GPIO_AF2_SAI1          ((uint8_t)0x02)  /* SAI1 Alternate Function mapping   */
+#if defined(HRTIM1)
+#define GPIO_AF2_HRTIM1        ((uint8_t)0x02)  /* HRTIM1 Alternate Function mapping */
+#endif /* HRTIM1 */
+#define GPIO_AF2_TIM15         ((uint8_t)0x02)  /* TIM15 Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx */
+
+/**
+  * @brief   AF 3 selection
+  */
+#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping   */
+#define GPIO_AF3_LPTIM2        ((uint8_t)0x03)  /* LPTIM2 Alternate Function mapping */
+#define GPIO_AF3_DFSDM1        ((uint8_t)0x03)  /* DFSDM Alternate Function mapping  */
+#define GPIO_AF3_LPTIM3        ((uint8_t)0x03)  /* LPTIM3 Alternate Function mapping */
+#define GPIO_AF3_LPTIM4        ((uint8_t)0x03)  /* LPTIM4 Alternate Function mapping */
+#define GPIO_AF3_LPTIM5        ((uint8_t)0x03)  /* LPTIM5 Alternate Function mapping */
+#define GPIO_AF3_LPUART        ((uint8_t)0x03)  /* LPUART Alternate Function mapping */
+#if defined(OCTOSPIM)
+#define GPIO_AF3_OCTOSPIM_P1   ((uint8_t)0x03)  /* OCTOSPI Manager Port 1 Alternate Function mapping */
+#define GPIO_AF3_OCTOSPIM_P2   ((uint8_t)0x03)  /* OCTOSPI Manager Port 2 Alternate Function mapping */
+#endif /* OCTOSPIM */
+#if defined(HRTIM1)
+#define GPIO_AF3_HRTIM1        ((uint8_t)0x03)  /* HRTIM1 Alternate Function mapping */
+#endif /* HRTIM1 */
+
+/**
+  * @brief   AF 4 selection
+  */
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping   */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping   */
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping   */
+#define GPIO_AF4_I2C4          ((uint8_t)0x04)  /* I2C4 Alternate Function mapping   */
+#define GPIO_AF4_TIM15         ((uint8_t)0x04)  /* TIM15 Alternate Function mapping  */
+#define GPIO_AF4_CEC           ((uint8_t)0x04)  /* CEC Alternate Function mapping    */
+#define GPIO_AF4_LPTIM2        ((uint8_t)0x04)  /* LPTIM2 Alternate Function mapping */
+#define GPIO_AF4_USART1        ((uint8_t)0x04)  /* USART1 Alternate Function mapping */
+#define GPIO_AF4_DFSDM1        ((uint8_t)0x04)  /* DFSDM  Alternate Function mapping */
+#if defined(DFSDM2_BASE)
+#define GPIO_AF4_DFSDM2        ((uint8_t)0x04)  /* DFSDM2 Alternate Function mapping */
+#endif /* DFSDM2_BASE */
+#if defined(PSSI)
+#define GPIO_AF4_PSSI          ((uint8_t)0x04)  /* PSSI Alternate Function mapping   */
+#endif /* PSSI */
+
+/**
+  * @brief   AF 5 selection
+  */
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping   */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2 Alternate Function mapping   */
+#define GPIO_AF5_SPI3          ((uint8_t)0x05)  /* SPI3 Alternate Function mapping   */
+#define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4 Alternate Function mapping   */
+#define GPIO_AF5_SPI5          ((uint8_t)0x05)  /* SPI5 Alternate Function mapping   */
+#define GPIO_AF5_SPI6          ((uint8_t)0x05)  /* SPI6 Alternate Function mapping   */
+#define GPIO_AF5_CEC           ((uint8_t)0x05)  /* CEC  Alternate Function mapping   */
+
+/**
+  * @brief   AF 6 selection
+  */
+#define GPIO_AF6_SPI2          ((uint8_t)0x06)  /* SPI2 Alternate Function mapping   */
+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3 Alternate Function mapping   */
+#define GPIO_AF6_SAI1          ((uint8_t)0x06)  /* SAI1 Alternate Function mapping   */
+#define GPIO_AF6_I2C4          ((uint8_t)0x06)  /* I2C4 Alternate Function mapping   */
+#define GPIO_AF6_DFSDM1        ((uint8_t)0x06)  /* DFSDM Alternate Function mapping  */
+#define GPIO_AF6_UART4         ((uint8_t)0x06)  /* UART4 Alternate Function mapping  */
+#if defined(DFSDM2_BASE)
+#define GPIO_AF6_DFSDM2        ((uint8_t)0x06)  /* DFSDM2 Alternate Function mapping */
+#endif /* DFSDM2_BASE */
+#if defined(SAI3)
+#define GPIO_AF6_SAI3          ((uint8_t)0x06)  /* SAI3 Alternate Function mapping   */
+#endif /* SAI3 */
+#if defined(OCTOSPIM)
+#define GPIO_AF6_OCTOSPIM_P1   ((uint8_t)0x06)  /* OCTOSPI Manager Port 1 Alternate Function mapping */
+#endif /* OCTOSPIM */
+
+/**
+  * @brief   AF 7 selection
+  */
+#define GPIO_AF7_SPI2          ((uint8_t)0x07)  /* SPI2 Alternate Function mapping   */
+#define GPIO_AF7_SPI3          ((uint8_t)0x07)  /* SPI3 Alternate Function mapping   */
+#define GPIO_AF7_SPI6          ((uint8_t)0x07)  /* SPI6 Alternate Function mapping   */
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping */
+#define GPIO_AF7_USART6        ((uint8_t)0x07)  /* USART6 Alternate Function mapping */
+#define GPIO_AF7_UART7         ((uint8_t)0x07)  /* UART7 Alternate Function mapping  */
+#define GPIO_AF7_DFSDM1        ((uint8_t)0x07)  /* DFSDM Alternate Function mapping  */
+#define GPIO_AF7_SDMMC1        ((uint8_t)0x07)  /* SDMMC1 Alternate Function mapping */
+
+/**
+  * @brief   AF 8 selection
+  */
+#define GPIO_AF8_SPI6          ((uint8_t)0x08)  /* SPI6 Alternate Function mapping   */
+#define GPIO_AF8_SAI2          ((uint8_t)0x08)  /* SAI2 Alternate Function mapping   */
+#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */
+#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */
+#define GPIO_AF8_UART8         ((uint8_t)0x08)  /* UART8 Alternate Function mapping  */
+#define GPIO_AF8_SPDIF         ((uint8_t)0x08)  /* SPDIF Alternate Function mapping  */
+#define GPIO_AF8_LPUART        ((uint8_t)0x08)  /* LPUART Alternate Function mapping */
+#define GPIO_AF8_SDMMC1        ((uint8_t)0x08)  /* SDMMC1 Alternate Function mapping */
+#if defined(SAI4)
+#define GPIO_AF8_SAI4          ((uint8_t)0x08)  /* SAI4 Alternate Function mapping   */
+#endif /* SAI4 */
+
+/**
+  * @brief   AF 9 selection
+  */
+#define GPIO_AF9_FDCAN1        ((uint8_t)0x09)  /* FDCAN1 Alternate Function mapping   */
+#define GPIO_AF9_FDCAN2        ((uint8_t)0x09)  /* FDCAN2 Alternate Function mapping   */
+#define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping    */
+#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping    */
+#define GPIO_AF9_SDMMC2        ((uint8_t)0x09)  /* SDMMC2 Alternate Function mapping   */
+#define GPIO_AF9_LTDC          ((uint8_t)0x09)  /* LTDC Alternate Function mapping     */
+#define GPIO_AF9_SPDIF         ((uint8_t)0x09)  /* SPDIF Alternate Function mapping    */
+#define GPIO_AF9_FMC           ((uint8_t)0x09)  /* FMC Alternate Function mapping      */
+#if defined(QUADSPI)
+#define GPIO_AF9_QUADSPI       ((uint8_t)0x09)  /* QUADSPI Alternate Function mapping  */
+#endif /* QUADSPI */
+#if defined(SAI4)
+#define GPIO_AF9_SAI4          ((uint8_t)0x09)  /* SAI4 Alternate Function mapping     */
+#endif /* SAI4 */
+#if defined(OCTOSPIM)
+#define GPIO_AF9_OCTOSPIM_P1   ((uint8_t)0x09)  /* OCTOSPI Manager Port 1 Alternate Function mapping */
+#define GPIO_AF9_OCTOSPIM_P2   ((uint8_t)0x09)  /* OCTOSPI Manager Port 2 Alternate Function mapping */
+#endif /* OCTOSPIM */
+
+/**
+  * @brief   AF 10 selection
+  */
+#define GPIO_AF10_SAI2          ((uint8_t)0x0A)  /* SAI2 Alternate Function mapping                                             */
+#define GPIO_AF10_SDMMC2        ((uint8_t)0x0A)  /* SDMMC2 Alternate Function mapping                                           */
+#if defined(USB2_OTG_FS)
+#define GPIO_AF10_OTG2_FS       ((uint8_t)0x0A)  /* OTG2_FS Alternate Function mapping                                          */
+#endif /*USB2_OTG_FS*/
+#define GPIO_AF10_COMP1         ((uint8_t)0x0A)  /* COMP1 Alternate Function mapping                                            */
+#define GPIO_AF10_COMP2         ((uint8_t)0x0A)  /* COMP2 Alternate Function mapping                                            */
+#if defined(LTDC)
+#define GPIO_AF10_LTDC          ((uint8_t)0x0A)  /* LTDC Alternate Function mapping                                             */
+#endif /*LTDC*/
+#define GPIO_AF10_CRS_SYNC      ((uint8_t)0x0A)  /* CRS Sync Alternate Function mapping : available on STM32H7 Rev.B and above  */
+#if defined(QUADSPI)
+#define GPIO_AF10_QUADSPI       ((uint8_t)0x0A)  /* QUADSPI Alternate Function mapping                                          */
+#endif /* QUADSPI */
+#if defined(SAI4)
+#define GPIO_AF10_SAI4          ((uint8_t)0x0A)  /* SAI4 Alternate Function mapping                                             */
+#endif /* SAI4 */
+#if !defined(USB2_OTG_FS)
+#define GPIO_AF10_OTG1_FS       ((uint8_t)0x0A)  /* OTG1_FS Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx */
+#endif /* !USB2_OTG_FS */
+#define GPIO_AF10_OTG1_HS       ((uint8_t)0x0A)  /* OTG1_HS Alternate Function mapping                                          */
+#if defined(OCTOSPIM)
+#define GPIO_AF10_OCTOSPIM_P1   ((uint8_t)0x0A)  /* OCTOSPI Manager Port 1 Alternate Function mapping */
+#endif /* OCTOSPIM */
+#define GPIO_AF10_TIM8          ((uint8_t)0x0A)  /* TIM8 Alternate Function mapping                                             */
+
+/**
+  * @brief   AF 11 selection
+  */
+#define GPIO_AF11_SWP           ((uint8_t)0x0B)  /* SWP Alternate Function mapping     */
+#define GPIO_AF11_MDIOS         ((uint8_t)0x0B)  /* MDIOS Alternate Function mapping   */
+#define GPIO_AF11_UART7         ((uint8_t)0x0B)  /* UART7 Alternate Function mapping   */
+#define GPIO_AF11_SDMMC2        ((uint8_t)0x0B)  /* SDMMC2 Alternate Function mapping  */
+#define GPIO_AF11_DFSDM1        ((uint8_t)0x0B)  /* DFSDM1 Alternate Function mapping  */
+#define GPIO_AF11_COMP1         ((uint8_t)0x0B)  /* COMP1 Alternate Function mapping   */
+#define GPIO_AF11_COMP2         ((uint8_t)0x0B)  /* COMP2 Alternate Function mapping   */
+#define GPIO_AF11_TIM1          ((uint8_t)0x0B)  /* TIM1 Alternate Function mapping    */
+#define GPIO_AF11_TIM8          ((uint8_t)0x0B)  /* TIM8 Alternate Function mapping    */
+#define GPIO_AF11_I2C4          ((uint8_t)0x0B)  /* I2C4 Alternate Function mapping    */
+#if defined(DFSDM2_BASE)
+#define GPIO_AF11_DFSDM2        ((uint8_t)0x0B)  /* DFSDM2 Alternate Function mapping  */
+#endif /* DFSDM2_BASE */
+#if defined(USART10)
+#define GPIO_AF11_USART10       ((uint8_t)0x0B)  /* USART10 Alternate Function mapping */
+#endif /* USART10 */
+#if defined(UART9)
+#define GPIO_AF11_UART9         ((uint8_t)0x0B)  /* UART9 Alternate Function mapping   */
+#endif /* UART9 */
+#if defined(ETH)
+#define GPIO_AF11_ETH           ((uint8_t)0x0B)  /* ETH Alternate Function mapping     */
+#endif /* ETH */
+#if defined(LTDC)
+#define GPIO_AF11_LTDC          ((uint8_t)0x0B)  /* LTDC Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx  */
+#endif /*LTDC*/
+#if defined(OCTOSPIM)
+#define GPIO_AF11_OCTOSPIM_P1   ((uint8_t)0x0B)  /* OCTOSPI Manager Port 1 Alternate Function mapping */
+#endif /* OCTOSPIM */
+
+/**
+  * @brief   AF 12 selection
+  */
+#define GPIO_AF12_FMC           ((uint8_t)0x0C)  /* FMC Alternate Function mapping     */
+#define GPIO_AF12_SDMMC1        ((uint8_t)0x0C)  /* SDMMC1 Alternate Function mapping  */
+#define GPIO_AF12_MDIOS         ((uint8_t)0x0C)  /* MDIOS Alternate Function mapping   */
+#define GPIO_AF12_COMP1         ((uint8_t)0x0C)  /* COMP1 Alternate Function mapping   */
+#define GPIO_AF12_COMP2         ((uint8_t)0x0C)  /* COMP2 Alternate Function mapping   */
+#define GPIO_AF12_TIM1          ((uint8_t)0x0C)  /* TIM1 Alternate Function mapping    */
+#define GPIO_AF12_TIM8          ((uint8_t)0x0C)  /* TIM8 Alternate Function mapping    */
+#if defined(LTDC)
+#define GPIO_AF12_LTDC          ((uint8_t)0x0C)  /* LTDC Alternate Function mapping    */
+#endif /*LTDC*/
+#if defined(USB2_OTG_FS)
+#define GPIO_AF12_OTG1_FS       ((uint8_t)0x0C)  /* OTG1_FS Alternate Function mapping */
+#endif /* USB2_OTG_FS */
+
+/**
+  * @brief   AF 13 selection
+  */
+#define GPIO_AF13_DCMI          ((uint8_t)0x0D)   /* DCMI Alternate Function mapping  */
+#define GPIO_AF13_COMP1         ((uint8_t)0x0D)   /* COMP1 Alternate Function mapping */
+#define GPIO_AF13_COMP2         ((uint8_t)0x0D)   /* COMP2 Alternate Function mapping */
+#if defined(LTDC)
+#define GPIO_AF13_LTDC          ((uint8_t)0x0D)   /* LTDC Alternate Function mapping  */
+#endif /*LTDC*/
+#if defined(DSI)
+#define GPIO_AF13_DSI           ((uint8_t)0x0D)   /* DSI Alternate Function mapping   */
+#endif /* DSI */
+#if defined(PSSI)
+#define GPIO_AF13_PSSI          ((uint8_t)0x0D)   /* PSSI Alternate Function mapping  */
+#endif /* PSSI */
+#define GPIO_AF13_TIM1          ((uint8_t)0x0D)    /* TIM1 Alternate Function mapping */
+
+/**
+  * @brief   AF 14 selection
+  */
+#define GPIO_AF14_LTDC         ((uint8_t)0x0E)   /* LTDC Alternate Function mapping  */
+#define GPIO_AF14_UART5        ((uint8_t)0x0E)   /* UART5 Alternate Function mapping */
+
+/**
+  * @brief   AF 15 selection
+  */
+#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF)   ((AF) <= (uint8_t)0x0F)
+
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros
+  * @{
+  */
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions
+  * @{
+  */
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup GPIOEx_Private_Constants GPIO Private Constants
+  * @{
+  */
+
+/**
+  * @brief   GPIO pin available on the platform
+  */
+/* Defines the available pins per GPIOs */
+#define GPIOA_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOB_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOC_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOD_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOE_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOF_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOG_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOI_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOJ_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOH_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOK_PIN_AVAILABLE  (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | \
+                              GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7)
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup GPIOEx_Private_Macros GPIO Private Macros
+  * @{
+  */
+/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index
+  * @{
+  */
+#define GPIO_GET_INDEX(__GPIOx__)  (((__GPIOx__) == (GPIOA))? 0UL :\
+                                    ((__GPIOx__) == (GPIOB))? 1UL :\
+                                    ((__GPIOx__) == (GPIOC))? 2UL :\
+                                    ((__GPIOx__) == (GPIOD))? 3UL :\
+                                    ((__GPIOx__) == (GPIOE))? 4UL :\
+                                    ((__GPIOx__) == (GPIOF))? 5UL :\
+                                    ((__GPIOx__) == (GPIOG))? 6UL :\
+                                    ((__GPIOx__) == (GPIOH))? 7UL :\
+                                    ((__GPIOx__) == (GPIOI))? 8UL :\
+                                    ((__GPIOx__) == (GPIOJ))? 9UL : 10UL)
+/**
+  * @}
+  */
+
+/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function
+  * @{
+  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup GPIOEx_Private_Functions GPIO Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_GPIO_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h
new file mode 100644
index 00000000..1ef97f3d
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h
@@ -0,0 +1,214 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_hsem.h
+  * @author  MCD Application Team
+  * @brief   Header file of HSEM HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_HSEM_H
+#define STM32H7xx_HAL_HSEM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+   * @{
+   */
+
+/** @addtogroup HSEM
+   * @{
+   */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup HSEM_Exported_Macros HSEM Exported Macros
+  * @{
+  */
+
+/**
+  * @brief  SemID to mask helper Macro.
+  * @param  __SEMID__: semaphore ID from 0 to 31
+  * @retval Semaphore Mask.
+  */
+#define __HAL_HSEM_SEMID_TO_MASK(__SEMID__) (1 << (__SEMID__))
+
+/**
+  * @brief  Enables the specified HSEM interrupts.
+  * @param  __SEM_MASK__: semaphores Mask
+  * @retval None.
+  */
+#if defined(DUAL_CORE)
+#define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
+                                            (HSEM->C1IER |= (__SEM_MASK__)) : \
+                                            (HSEM->C2IER |= (__SEM_MASK__)))
+#else
+#define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) (HSEM->IER |= (__SEM_MASK__))
+#endif /* DUAL_CORE */
+/**
+  * @brief  Disables the specified HSEM interrupts.
+  * @param  __SEM_MASK__: semaphores Mask
+  * @retval None.
+  */
+#if defined(DUAL_CORE)
+#define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
+                                             (HSEM->C1IER &= ~(__SEM_MASK__)) :       \
+                                             (HSEM->C2IER &= ~(__SEM_MASK__)))
+#else
+#define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) (HSEM->IER &= ~(__SEM_MASK__))
+#endif /* DUAL_CORE */
+
+/**
+  * @brief  Checks whether interrupt has occurred or not for semaphores specified by a mask.
+  * @param  __SEM_MASK__: semaphores Mask
+  * @retval semaphores Mask : Semaphores where an interrupt occurred.
+  */
+#if defined(DUAL_CORE)
+#define __HAL_HSEM_GET_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
+                                         ((__SEM_MASK__) & HSEM->C1MISR) :        \
+                                         ((__SEM_MASK__) & HSEM->C2MISR1))
+#else
+#define __HAL_HSEM_GET_IT(__SEM_MASK__) ((__SEM_MASK__) & HSEM->MISR)
+#endif /* DUAL_CORE */
+
+/**
+  * @brief  Get the semaphores release status flags.
+  * @param  __SEM_MASK__: semaphores Mask
+  * @retval semaphores Mask : Semaphores where Release flags rise.
+  */
+#if defined(DUAL_CORE)
+#define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
+                                           (__SEM_MASK__) & HSEM->C1ISR :           \
+                                           (__SEM_MASK__) & HSEM->C2ISR)
+#else
+#define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((__SEM_MASK__) & HSEM->ISR)
+#endif /* DUAL_CORE */
+
+/**
+  * @brief  Clears the HSEM Interrupt flags.
+  * @param  __SEM_MASK__: semaphores Mask
+  * @retval None.
+  */
+#if defined(DUAL_CORE)
+#define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
+                                             (HSEM->C1ICR |= (__SEM_MASK__)) :        \
+                                             (HSEM->C2ICR |= (__SEM_MASK__)))
+#else
+#define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) (HSEM->ICR |= (__SEM_MASK__))
+#endif /* DUAL_CORE */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup HSEM_Exported_Functions HSEM Exported Functions
+  * @{
+  */
+
+/** @addtogroup HSEM_Exported_Functions_Group1 Take and Release functions
+  * @brief    HSEM Take and Release functions
+  * @{
+  */
+
+/* HSEM semaphore take (lock) using 2-Step  method ****************************/
+HAL_StatusTypeDef  HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID);
+/* HSEM semaphore fast take (lock) using 1-Step  method ***********************/
+HAL_StatusTypeDef  HAL_HSEM_FastTake(uint32_t SemID);
+/* HSEM Check semaphore state Taken or not   **********************************/
+uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID);
+/* HSEM Release  **************************************************************/
+void  HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID);
+/* HSEM Release All************************************************************/
+void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t CoreID);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HSEM_Exported_Functions_Group2 HSEM Set and Get Key functions
+  * @brief    HSEM Set and Get Key functions.
+  * @{
+  */
+/* HSEM Set Clear Key *********************************************************/
+void  HAL_HSEM_SetClearKey(uint32_t Key);
+/* HSEM Get Clear Key *********************************************************/
+uint32_t HAL_HSEM_GetClearKey(void);
+/**
+  * @}
+  */
+
+/** @addtogroup HSEM_Exported_Functions_Group3
+  * @brief   HSEM Notification functions
+  * @{
+  */
+/* HSEM Activate HSEM Notification (When a semaphore is released) ) *****************/
+void HAL_HSEM_ActivateNotification(uint32_t SemMask);
+/* HSEM Deactivate HSEM Notification (When a semaphore is released)  ****************/
+void HAL_HSEM_DeactivateNotification(uint32_t SemMask);
+/* HSEM Free Callback (When a semaphore is released)  *******************************/
+void HAL_HSEM_FreeCallback(uint32_t SemMask);
+/* HSEM IRQ Handler  **********************************************************/
+void HAL_HSEM_IRQHandler(void);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup HSEM_Private_Macros HSEM Private Macros
+  * @{
+  */
+
+#define IS_HSEM_SEMID(__SEMID__) ((__SEMID__) <= HSEM_SEMID_MAX )
+
+#define IS_HSEM_PROCESSID(__PROCESSID__) ((__PROCESSID__) <= HSEM_PROCESSID_MAX )
+
+#define IS_HSEM_KEY(__KEY__) ((__KEY__) <= HSEM_CLEAR_KEY_MAX )
+
+#if defined(DUAL_CORE)
+#define IS_HSEM_COREID(__COREID__) (((__COREID__) == HSEM_CPU1_COREID) || \
+                                    ((__COREID__) == HSEM_CPU2_COREID))
+#else
+#define IS_HSEM_COREID(__COREID__) ((__COREID__) == HSEM_CPU1_COREID)
+#endif
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_HSEM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h
new file mode 100644
index 00000000..ea2cd885
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h
@@ -0,0 +1,782 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_i2c.h
+  * @author  MCD Application Team
+  * @brief   Header file of I2C HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_I2C_H
+#define STM32H7xx_HAL_I2C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup I2C
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup I2C_Exported_Types I2C Exported Types
+  * @{
+  */
+
+/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
+  * @brief  I2C Configuration Structure definition
+  * @{
+  */
+typedef struct
+{
+  uint32_t Timing;              /*!< Specifies the I2C_TIMINGR_register value.
+                                  This parameter calculated by referring to I2C initialization
+                                         section in Reference manual */
+
+  uint32_t OwnAddress1;         /*!< Specifies the first device own address.
+                                  This parameter can be a 7-bit or 10-bit address. */
+
+  uint32_t AddressingMode;      /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
+                                  This parameter can be a value of @ref I2C_ADDRESSING_MODE */
+
+  uint32_t DualAddressMode;     /*!< Specifies if dual addressing mode is selected.
+                                  This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
+
+  uint32_t OwnAddress2;         /*!< Specifies the second device own address if dual addressing mode is selected
+                                  This parameter can be a 7-bit address. */
+
+  uint32_t OwnAddress2Masks;    /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
+                                  This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
+
+  uint32_t GeneralCallMode;     /*!< Specifies if general call mode is selected.
+                                  This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
+
+  uint32_t NoStretchMode;       /*!< Specifies if nostretch mode is selected.
+                                  This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
+
+} I2C_InitTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_state_structure_definition HAL state structure definition
+  * @brief  HAL State structure definition
+  * @note  HAL I2C State value coding follow below described bitmap :\n
+  *          b7-b6  Error information\n
+  *             00 : No Error\n
+  *             01 : Abort (Abort user request on going)\n
+  *             10 : Timeout\n
+  *             11 : Error\n
+  *          b5     Peripheral initialization status\n
+  *             0  : Reset (peripheral not initialized)\n
+  *             1  : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n
+  *          b4     (not used)\n
+  *             x  : Should be set to 0\n
+  *          b3\n
+  *             0  : Ready or Busy (No Listen mode ongoing)\n
+  *             1  : Listen (peripheral in Address Listen Mode)\n
+  *          b2     Intrinsic process state\n
+  *             0  : Ready\n
+  *             1  : Busy (peripheral busy with some configuration or internal operations)\n
+  *          b1     Rx state\n
+  *             0  : Ready (no Rx operation ongoing)\n
+  *             1  : Busy (Rx operation ongoing)\n
+  *          b0     Tx state\n
+  *             0  : Ready (no Tx operation ongoing)\n
+  *             1  : Busy (Tx operation ongoing)
+  * @{
+  */
+typedef enum
+{
+  HAL_I2C_STATE_RESET             = 0x00U,   /*!< Peripheral is not yet Initialized         */
+  HAL_I2C_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use  */
+  HAL_I2C_STATE_BUSY              = 0x24U,   /*!< An internal process is ongoing            */
+  HAL_I2C_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing      */
+  HAL_I2C_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing         */
+  HAL_I2C_STATE_LISTEN            = 0x28U,   /*!< Address Listen Mode is ongoing            */
+  HAL_I2C_STATE_BUSY_TX_LISTEN    = 0x29U,   /*!< Address Listen Mode and Data Transmission
+                                                 process is ongoing                         */
+  HAL_I2C_STATE_BUSY_RX_LISTEN    = 0x2AU,   /*!< Address Listen Mode and Data Reception
+                                                 process is ongoing                         */
+  HAL_I2C_STATE_ABORT             = 0x60U,   /*!< Abort user request ongoing                */
+  HAL_I2C_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state                             */
+  HAL_I2C_STATE_ERROR             = 0xE0U    /*!< Error                                     */
+
+} HAL_I2C_StateTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_mode_structure_definition HAL mode structure definition
+  * @brief  HAL Mode structure definition
+  * @note  HAL I2C Mode value coding follow below described bitmap :\n
+  *          b7     (not used)\n
+  *             x  : Should be set to 0\n
+  *          b6\n
+  *             0  : None\n
+  *             1  : Memory (HAL I2C communication is in Memory Mode)\n
+  *          b5\n
+  *             0  : None\n
+  *             1  : Slave (HAL I2C communication is in Slave Mode)\n
+  *          b4\n
+  *             0  : None\n
+  *             1  : Master (HAL I2C communication is in Master Mode)\n
+  *          b3-b2-b1-b0  (not used)\n
+  *             xxxx : Should be set to 0000
+  * @{
+  */
+typedef enum
+{
+  HAL_I2C_MODE_NONE               = 0x00U,   /*!< No I2C communication on going             */
+  HAL_I2C_MODE_MASTER             = 0x10U,   /*!< I2C communication is in Master Mode       */
+  HAL_I2C_MODE_SLAVE              = 0x20U,   /*!< I2C communication is in Slave Mode        */
+  HAL_I2C_MODE_MEM                = 0x40U    /*!< I2C communication is in Memory Mode       */
+
+} HAL_I2C_ModeTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Error_Code_definition I2C Error Code definition
+  * @brief  I2C Error Code definition
+  * @{
+  */
+#define HAL_I2C_ERROR_NONE      (0x00000000U)    /*!< No error              */
+#define HAL_I2C_ERROR_BERR      (0x00000001U)    /*!< BERR error            */
+#define HAL_I2C_ERROR_ARLO      (0x00000002U)    /*!< ARLO error            */
+#define HAL_I2C_ERROR_AF        (0x00000004U)    /*!< ACKF error            */
+#define HAL_I2C_ERROR_OVR       (0x00000008U)    /*!< OVR error             */
+#define HAL_I2C_ERROR_DMA       (0x00000010U)    /*!< DMA transfer error    */
+#define HAL_I2C_ERROR_TIMEOUT   (0x00000020U)    /*!< Timeout error         */
+#define HAL_I2C_ERROR_SIZE      (0x00000040U)    /*!< Size Management error */
+#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U)    /*!< DMA Parameter Error   */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+#define HAL_I2C_ERROR_INVALID_CALLBACK  (0x00000100U)    /*!< Invalid Callback error */
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+#define HAL_I2C_ERROR_INVALID_PARAM     (0x00000200U)    /*!< Invalid Parameters error  */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
+  * @brief  I2C handle Structure definition
+  * @{
+  */
+typedef struct __I2C_HandleTypeDef
+{
+  I2C_TypeDef                *Instance;      /*!< I2C registers base address                */
+
+  I2C_InitTypeDef            Init;           /*!< I2C communication parameters              */
+
+  uint8_t                    *pBuffPtr;      /*!< Pointer to I2C transfer buffer            */
+
+  uint16_t                   XferSize;       /*!< I2C transfer size                         */
+
+  __IO uint16_t              XferCount;      /*!< I2C transfer counter                      */
+
+  __IO uint32_t              XferOptions;    /*!< I2C sequantial transfer options, this parameter can
+                                                  be a value of @ref I2C_XFEROPTIONS */
+
+  __IO uint32_t              PreviousState;  /*!< I2C communication Previous state          */
+
+  HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);  /*!< I2C transfer IRQ handler function pointer */
+
+  DMA_HandleTypeDef          *hdmatx;        /*!< I2C Tx DMA handle parameters              */
+
+  DMA_HandleTypeDef          *hdmarx;        /*!< I2C Rx DMA handle parameters              */
+
+  HAL_LockTypeDef            Lock;           /*!< I2C locking object                        */
+
+  __IO HAL_I2C_StateTypeDef  State;          /*!< I2C communication state                   */
+
+  __IO HAL_I2C_ModeTypeDef   Mode;           /*!< I2C communication mode                    */
+
+  __IO uint32_t              ErrorCode;      /*!< I2C Error code                            */
+
+  __IO uint32_t              AddrEventCount; /*!< I2C Address Event counter                 */
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+  void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);           /*!< I2C Master Tx Transfer completed callback */
+  void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);           /*!< I2C Master Rx Transfer completed callback */
+  void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);            /*!< I2C Slave Tx Transfer completed callback  */
+  void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);            /*!< I2C Slave Rx Transfer completed callback  */
+  void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);             /*!< I2C Listen Complete callback              */
+  void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Memory Tx Transfer completed callback */
+  void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Memory Rx Transfer completed callback */
+  void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);                  /*!< I2C Error callback                        */
+  void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Abort callback                        */
+
+  void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);  /*!< I2C Slave Address Match callback */
+
+  void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);                /*!< I2C Msp Init callback                     */
+  void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Msp DeInit callback                   */
+
+#endif  /* USE_HAL_I2C_REGISTER_CALLBACKS */
+} I2C_HandleTypeDef;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL I2C Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_I2C_MASTER_TX_COMPLETE_CB_ID      = 0x00U,    /*!< I2C Master Tx Transfer completed callback ID  */
+  HAL_I2C_MASTER_RX_COMPLETE_CB_ID      = 0x01U,    /*!< I2C Master Rx Transfer completed callback ID  */
+  HAL_I2C_SLAVE_TX_COMPLETE_CB_ID       = 0x02U,    /*!< I2C Slave Tx Transfer completed callback ID   */
+  HAL_I2C_SLAVE_RX_COMPLETE_CB_ID       = 0x03U,    /*!< I2C Slave Rx Transfer completed callback ID   */
+  HAL_I2C_LISTEN_COMPLETE_CB_ID         = 0x04U,    /*!< I2C Listen Complete callback ID               */
+  HAL_I2C_MEM_TX_COMPLETE_CB_ID         = 0x05U,    /*!< I2C Memory Tx Transfer callback ID            */
+  HAL_I2C_MEM_RX_COMPLETE_CB_ID         = 0x06U,    /*!< I2C Memory Rx Transfer completed callback ID  */
+  HAL_I2C_ERROR_CB_ID                   = 0x07U,    /*!< I2C Error callback ID                         */
+  HAL_I2C_ABORT_CB_ID                   = 0x08U,    /*!< I2C Abort callback ID                         */
+
+  HAL_I2C_MSPINIT_CB_ID                 = 0x09U,    /*!< I2C Msp Init callback ID                      */
+  HAL_I2C_MSPDEINIT_CB_ID               = 0x0AU     /*!< I2C Msp DeInit callback ID                    */
+
+} HAL_I2C_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL I2C Callback pointer definition
+  */
+typedef  void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */
+typedef  void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */
+
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Constants I2C Exported Constants
+  * @{
+  */
+
+/** @defgroup I2C_XFEROPTIONS  I2C Sequential Transfer Options
+  * @{
+  */
+#define I2C_FIRST_FRAME                 ((uint32_t)I2C_SOFTEND_MODE)
+#define I2C_FIRST_AND_NEXT_FRAME        ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
+#define I2C_NEXT_FRAME                  ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
+#define I2C_FIRST_AND_LAST_FRAME        ((uint32_t)I2C_AUTOEND_MODE)
+#define I2C_LAST_FRAME                  ((uint32_t)I2C_AUTOEND_MODE)
+#define I2C_LAST_FRAME_NO_STOP          ((uint32_t)I2C_SOFTEND_MODE)
+
+/* List of XferOptions in usage of :
+ * 1- Restart condition in all use cases (direction change or not)
+ */
+#define  I2C_OTHER_FRAME                (0x000000AAU)
+#define  I2C_OTHER_AND_LAST_FRAME       (0x0000AA00U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
+  * @{
+  */
+#define I2C_ADDRESSINGMODE_7BIT         (0x00000001U)
+#define I2C_ADDRESSINGMODE_10BIT        (0x00000002U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
+  * @{
+  */
+#define I2C_DUALADDRESS_DISABLE         (0x00000000U)
+#define I2C_DUALADDRESS_ENABLE          I2C_OAR2_OA2EN
+/**
+  * @}
+  */
+
+/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
+  * @{
+  */
+#define I2C_OA2_NOMASK                  ((uint8_t)0x00U)
+#define I2C_OA2_MASK01                  ((uint8_t)0x01U)
+#define I2C_OA2_MASK02                  ((uint8_t)0x02U)
+#define I2C_OA2_MASK03                  ((uint8_t)0x03U)
+#define I2C_OA2_MASK04                  ((uint8_t)0x04U)
+#define I2C_OA2_MASK05                  ((uint8_t)0x05U)
+#define I2C_OA2_MASK06                  ((uint8_t)0x06U)
+#define I2C_OA2_MASK07                  ((uint8_t)0x07U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
+  * @{
+  */
+#define I2C_GENERALCALL_DISABLE         (0x00000000U)
+#define I2C_GENERALCALL_ENABLE          I2C_CR1_GCEN
+/**
+  * @}
+  */
+
+/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
+  * @{
+  */
+#define I2C_NOSTRETCH_DISABLE           (0x00000000U)
+#define I2C_NOSTRETCH_ENABLE            I2C_CR1_NOSTRETCH
+/**
+  * @}
+  */
+
+/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
+  * @{
+  */
+#define I2C_MEMADD_SIZE_8BIT            (0x00000001U)
+#define I2C_MEMADD_SIZE_16BIT           (0x00000002U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
+  * @{
+  */
+#define I2C_DIRECTION_TRANSMIT          (0x00000000U)
+#define I2C_DIRECTION_RECEIVE           (0x00000001U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
+  * @{
+  */
+#define  I2C_RELOAD_MODE                I2C_CR2_RELOAD
+#define  I2C_AUTOEND_MODE               I2C_CR2_AUTOEND
+#define  I2C_SOFTEND_MODE               (0x00000000U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
+  * @{
+  */
+#define  I2C_NO_STARTSTOP               (0x00000000U)
+#define  I2C_GENERATE_STOP              (uint32_t)(0x80000000U | I2C_CR2_STOP)
+#define  I2C_GENERATE_START_READ        (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
+#define  I2C_GENERATE_START_WRITE       (uint32_t)(0x80000000U | I2C_CR2_START)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
+  * @brief I2C Interrupt definition
+  *        Elements values convention: 0xXXXXXXXX
+  *           - XXXXXXXX  : Interrupt control mask
+  * @{
+  */
+#define I2C_IT_ERRI                     I2C_CR1_ERRIE
+#define I2C_IT_TCI                      I2C_CR1_TCIE
+#define I2C_IT_STOPI                    I2C_CR1_STOPIE
+#define I2C_IT_NACKI                    I2C_CR1_NACKIE
+#define I2C_IT_ADDRI                    I2C_CR1_ADDRIE
+#define I2C_IT_RXI                      I2C_CR1_RXIE
+#define I2C_IT_TXI                      I2C_CR1_TXIE
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Flag_definition I2C Flag definition
+  * @{
+  */
+#define I2C_FLAG_TXE                    I2C_ISR_TXE
+#define I2C_FLAG_TXIS                   I2C_ISR_TXIS
+#define I2C_FLAG_RXNE                   I2C_ISR_RXNE
+#define I2C_FLAG_ADDR                   I2C_ISR_ADDR
+#define I2C_FLAG_AF                     I2C_ISR_NACKF
+#define I2C_FLAG_STOPF                  I2C_ISR_STOPF
+#define I2C_FLAG_TC                     I2C_ISR_TC
+#define I2C_FLAG_TCR                    I2C_ISR_TCR
+#define I2C_FLAG_BERR                   I2C_ISR_BERR
+#define I2C_FLAG_ARLO                   I2C_ISR_ARLO
+#define I2C_FLAG_OVR                    I2C_ISR_OVR
+#define I2C_FLAG_PECERR                 I2C_ISR_PECERR
+#define I2C_FLAG_TIMEOUT                I2C_ISR_TIMEOUT
+#define I2C_FLAG_ALERT                  I2C_ISR_ALERT
+#define I2C_FLAG_BUSY                   I2C_ISR_BUSY
+#define I2C_FLAG_DIR                    I2C_ISR_DIR
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Macros I2C Exported Macros
+  * @{
+  */
+
+/** @brief Reset I2C handle state.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                do{                                                   \
+                                                                    (__HANDLE__)->State = HAL_I2C_STATE_RESET;       \
+                                                                    (__HANDLE__)->MspInitCallback = NULL;            \
+                                                                    (__HANDLE__)->MspDeInitCallback = NULL;          \
+                                                                  } while(0)
+#else
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
+#endif
+
+/** @brief  Enable the specified I2C interrupt.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __INTERRUPT__ specifies the interrupt source to enable.
+  *        This parameter can be one of the following values:
+  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
+  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
+  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
+  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
+  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
+  *            @arg @ref I2C_IT_RXI   RX interrupt enable
+  *            @arg @ref I2C_IT_TXI   TX interrupt enable
+  *
+  * @retval None
+  */
+#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)          ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
+
+/** @brief  Disable the specified I2C interrupt.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __INTERRUPT__ specifies the interrupt source to disable.
+  *        This parameter can be one of the following values:
+  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
+  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
+  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
+  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
+  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
+  *            @arg @ref I2C_IT_RXI   RX interrupt enable
+  *            @arg @ref I2C_IT_TXI   TX interrupt enable
+  *
+  * @retval None
+  */
+#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
+
+/** @brief  Check whether the specified I2C interrupt source is enabled or not.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __INTERRUPT__ specifies the I2C interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
+  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
+  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
+  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
+  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
+  *            @arg @ref I2C_IT_RXI   RX interrupt enable
+  *            @arg @ref I2C_IT_TXI   TX interrupt enable
+  *
+  * @retval The new state of __INTERRUPT__ (SET or RESET).
+  */
+#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)      ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief  Check whether the specified I2C flag is set or not.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg @ref I2C_FLAG_TXE     Transmit data register empty
+  *            @arg @ref I2C_FLAG_TXIS    Transmit interrupt status
+  *            @arg @ref I2C_FLAG_RXNE    Receive data register not empty
+  *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)
+  *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag
+  *            @arg @ref I2C_FLAG_STOPF   STOP detection flag
+  *            @arg @ref I2C_FLAG_TC      Transfer complete (master mode)
+  *            @arg @ref I2C_FLAG_TCR     Transfer complete reload
+  *            @arg @ref I2C_FLAG_BERR    Bus error
+  *            @arg @ref I2C_FLAG_ARLO    Arbitration lost
+  *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun
+  *            @arg @ref I2C_FLAG_PECERR  PEC error in reception
+  *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
+  *            @arg @ref I2C_FLAG_ALERT   SMBus alert
+  *            @arg @ref I2C_FLAG_BUSY    Bus busy
+  *            @arg @ref I2C_FLAG_DIR     Transfer direction (slave mode)
+  *
+  * @retval The new state of __FLAG__ (SET or RESET).
+  */
+#define I2C_FLAG_MASK  (0x0001FFFFU)
+#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+
+/** @brief  Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __FLAG__ specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg @ref I2C_FLAG_TXE     Transmit data register empty
+  *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)
+  *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag
+  *            @arg @ref I2C_FLAG_STOPF   STOP detection flag
+  *            @arg @ref I2C_FLAG_BERR    Bus error
+  *            @arg @ref I2C_FLAG_ARLO    Arbitration lost
+  *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun
+  *            @arg @ref I2C_FLAG_PECERR  PEC error in reception
+  *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
+  *            @arg @ref I2C_FLAG_ALERT   SMBus alert
+  *
+  * @retval None
+  */
+#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
+                                                                                 : ((__HANDLE__)->Instance->ICR = (__FLAG__)))
+
+/** @brief  Enable the specified I2C peripheral.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#define __HAL_I2C_ENABLE(__HANDLE__)                            (SET_BIT((__HANDLE__)->Instance->CR1,  I2C_CR1_PE))
+
+/** @brief  Disable the specified I2C peripheral.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#define __HAL_I2C_DISABLE(__HANDLE__)                           (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
+
+/** @brief  Generate a Non-Acknowledge I2C peripheral in Slave mode.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#define __HAL_I2C_GENERATE_NACK(__HANDLE__)                     (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
+/**
+  * @}
+  */
+
+/* Include I2C HAL Extended module */
+#include "stm32h7xx_hal_i2c_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2C_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+/* Initialization and de-initialization functions******************************/
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
+  * @{
+  */
+/* IO operation functions  ****************************************************/
+/******* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
+
+/******* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
+
+/******* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
+void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
+  * @{
+  */
+/* Peripheral State, Mode and Error functions  *********************************/
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
+HAL_I2C_ModeTypeDef  HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
+uint32_t             HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Constants I2C Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2C_Private_Macro I2C Private Macros
+  * @{
+  */
+
+#define IS_I2C_ADDRESSING_MODE(MODE)    (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
+                                         ((MODE) == I2C_ADDRESSINGMODE_10BIT))
+
+#define IS_I2C_DUAL_ADDRESS(ADDRESS)    (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
+                                         ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
+
+#define IS_I2C_OWN_ADDRESS2_MASK(MASK)  (((MASK) == I2C_OA2_NOMASK)  || \
+                                         ((MASK) == I2C_OA2_MASK01) || \
+                                         ((MASK) == I2C_OA2_MASK02) || \
+                                         ((MASK) == I2C_OA2_MASK03) || \
+                                         ((MASK) == I2C_OA2_MASK04) || \
+                                         ((MASK) == I2C_OA2_MASK05) || \
+                                         ((MASK) == I2C_OA2_MASK06) || \
+                                         ((MASK) == I2C_OA2_MASK07))
+
+#define IS_I2C_GENERAL_CALL(CALL)       (((CALL) == I2C_GENERALCALL_DISABLE) || \
+                                         ((CALL) == I2C_GENERALCALL_ENABLE))
+
+#define IS_I2C_NO_STRETCH(STRETCH)      (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
+                                         ((STRETCH) == I2C_NOSTRETCH_ENABLE))
+
+#define IS_I2C_MEMADD_SIZE(SIZE)        (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
+                                         ((SIZE) == I2C_MEMADD_SIZE_16BIT))
+
+#define IS_TRANSFER_MODE(MODE)          (((MODE) == I2C_RELOAD_MODE)   || \
+                                         ((MODE) == I2C_AUTOEND_MODE) || \
+                                         ((MODE) == I2C_SOFTEND_MODE))
+
+#define IS_TRANSFER_REQUEST(REQUEST)    (((REQUEST) == I2C_GENERATE_STOP)        || \
+                                         ((REQUEST) == I2C_GENERATE_START_READ)  || \
+                                         ((REQUEST) == I2C_GENERATE_START_WRITE) || \
+                                         ((REQUEST) == I2C_NO_STARTSTOP))
+
+#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)  (((REQUEST) == I2C_FIRST_FRAME)          || \
+                                                   ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
+                                                   ((REQUEST) == I2C_NEXT_FRAME)           || \
+                                                   ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
+                                                   ((REQUEST) == I2C_LAST_FRAME)           || \
+                                                   ((REQUEST) == I2C_LAST_FRAME_NO_STOP)   || \
+                                                   IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
+
+#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME)     || \
+                                                        ((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
+
+#define I2C_RESET_CR2(__HANDLE__)                 ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
+
+#define I2C_GET_ADDR_MATCH(__HANDLE__)            ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U))
+#define I2C_GET_DIR(__HANDLE__)                   ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U))
+#define I2C_GET_STOP_MODE(__HANDLE__)             ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
+#define I2C_GET_OWN_ADDRESS1(__HANDLE__)          ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
+#define I2C_GET_OWN_ADDRESS2(__HANDLE__)          ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
+
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1)             ((ADDRESS1) <= 0x000003FFU)
+#define IS_I2C_OWN_ADDRESS2(ADDRESS2)             ((ADDRESS2) <= (uint16_t)0x00FFU)
+
+#define I2C_MEM_ADD_MSB(__ADDRESS__)              ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
+#define I2C_MEM_ADD_LSB(__ADDRESS__)              ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
+
+#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
+                                                          (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
+
+#define I2C_CHECK_FLAG(__ISR__, __FLAG__)         ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
+#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__)      ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
+/**
+  * @}
+  */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Functions I2C Private Functions
+  * @{
+  */
+/* Private functions are defined in stm32h7xx_hal_i2c.c file */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32H7xx_HAL_I2C_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h
new file mode 100644
index 00000000..bf89420b
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h
@@ -0,0 +1,181 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_i2c_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of I2C HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_I2C_EX_H
+#define STM32H7xx_HAL_I2C_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup I2CEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
+  * @{
+  */
+
+/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
+  * @{
+  */
+#define I2C_ANALOGFILTER_ENABLE         0x00000000U
+#define I2C_ANALOGFILTER_DISABLE        I2C_CR1_ANFOFF
+/**
+  * @}
+  */
+
+/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
+  * @{
+  */
+#define I2C_FASTMODEPLUS_PB6            SYSCFG_PMCR_I2C_PB6_FMP                        /*!< Enable Fast Mode Plus on PB6       */
+#define I2C_FASTMODEPLUS_PB7            SYSCFG_PMCR_I2C_PB7_FMP                        /*!< Enable Fast Mode Plus on PB7       */
+#define I2C_FASTMODEPLUS_PB8            SYSCFG_PMCR_I2C_PB8_FMP                        /*!< Enable Fast Mode Plus on PB8       */
+#define I2C_FASTMODEPLUS_PB9            SYSCFG_PMCR_I2C_PB9_FMP                        /*!< Enable Fast Mode Plus on PB9       */
+#define I2C_FASTMODEPLUS_I2C1           SYSCFG_PMCR_I2C1_FMP                           /*!< Enable Fast Mode Plus on I2C1 pins */
+#define I2C_FASTMODEPLUS_I2C2           SYSCFG_PMCR_I2C2_FMP                           /*!< Enable Fast Mode Plus on I2C2 pins */
+#define I2C_FASTMODEPLUS_I2C3           SYSCFG_PMCR_I2C3_FMP                           /*!< Enable Fast Mode Plus on I2C3 pins */
+#define I2C_FASTMODEPLUS_I2C4           SYSCFG_PMCR_I2C4_FMP                           /*!< Enable Fast Mode Plus on I2C4 pins */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
+  * @{
+  */
+
+/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions
+  * @brief    Extended features functions
+  * @{
+  */
+
+/* Peripheral Control functions  ************************************************/
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
+HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
+void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
+void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
+  * @{
+  */
+#define IS_I2C_ANALOG_FILTER(FILTER)    (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
+                                          ((FILTER) == I2C_ANALOGFILTER_DISABLE))
+
+#define IS_I2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000FU)
+
+#if (defined(SYSCFG_PMCR_I2C1_FMP) && defined(SYSCFG_PMCR_I2C2_FMP) && defined(SYSCFG_PMCR_I2C3_FMP) && defined(SYSCFG_PMCR_I2C4_FMP))
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3) || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C4) == I2C_FASTMODEPLUS_I2C4))
+#elif defined(SYSCFG_PMCR_I2C1_FMP) && defined(SYSCFG_PMCR_I2C2_FMP) && defined(SYSCFG_PMCR_I2C3_FMP)
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3))
+#elif defined(SYSCFG_PMCR_I2C1_FMP) && defined(SYSCFG_PMCR_I2C2_FMP)
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2))
+#elif defined(SYSCFG_PMCR_I2C1_FMP)
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1))
+#endif /* SYSCFG_PMCR_I2C1_FMP && SYSCFG_PMCR_I2C2_FMP && SYSCFG_PMCR_I2C3_FMP && SYSCFG_PMCR_I2C4_FMP */
+
+
+
+/**
+  * @}
+  */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
+  * @{
+  */
+/* Private functions are defined in stm32h7xx_hal_i2c_ex.c file */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_I2C_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h
new file mode 100644
index 00000000..6c1d9b71
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h
@@ -0,0 +1,855 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_mdma.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMA HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_MDMA_H
+#define STM32H7xx_HAL_MDMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup MDMA
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup MDMA_Exported_Types MDMA Exported Types
+  * @brief    MDMA Exported Types
+  * @{
+  */
+
+/**
+  * @brief  MDMA Configuration Structure definition
+  */
+typedef struct
+{
+
+  uint32_t Request;                 /*!< Specifies the MDMA request.
+                                        This parameter can be a value of @ref MDMA_Request_selection*/
+
+  uint32_t TransferTriggerMode;     /*!< Specifies the Trigger Transfer mode : each request triggers a :
+                                         a buffer transfer, a block transfer, a repeated block transfer or a linked list transfer
+                                         This parameter can be a value of @ref MDMA_Transfer_TriggerMode  */
+
+  uint32_t Priority;                 /*!< Specifies the software priority for the MDMAy channelx.
+                                         This parameter can be a value of @ref MDMA_Priority_level */
+
+  uint32_t Endianness;                /*!< Specifies if the MDMA transactions preserve the Little endianness.
+                                         This parameter can be a value of @ref MDMA_Endianness */
+
+  uint32_t SourceInc;                /*!< Specifies if the Source increment mode .
+                                         This parameter can be a value of @ref MDMA_Source_increment_mode */
+
+  uint32_t DestinationInc;           /*!< Specifies if the Destination increment mode .
+                                         This parameter can be a value of @ref MDMA_Destination_increment_mode */
+
+  uint32_t SourceDataSize;           /*!< Specifies the source data size.
+                                         This parameter can be a value of @ref MDMA_Source_data_size */
+
+  uint32_t DestDataSize;             /*!< Specifies the destination data size.
+                                          This parameter can be a value of @ref MDMA_Destination_data_size */
+
+
+  uint32_t DataAlignment;            /*!< Specifies the source to destination Memory data packing/padding mode.
+                                            This parameter can be a value of @ref MDMA_data_Alignment */
+
+  uint32_t BufferTransferLength;      /*!< Specifies the buffer Transfer Length (number of bytes),
+                                          this is the number of bytes to be transferred in a single transfer (1 byte to 128 bytes)*/
+
+  uint32_t SourceBurst;              /*!< Specifies the Burst transfer configuration for the source memory transfers.
+                                         It specifies the amount of data to be transferred in a single non interruptable
+                                         transaction.
+                                         This parameter can be a value of @ref MDMA_Source_burst
+                                         @note : the burst may be FIXED/INCR based on SourceInc value ,
+                                         the BURST must be programmed as to ensure that the burst size will be lower than than
+                                         BufferTransferLength */
+
+  uint32_t DestBurst;                 /*!< Specifies the Burst transfer configuration for the destination memory transfers.
+                                           It specifies the amount of data to be transferred in a single non interruptable
+                                           transaction.
+                                           This parameter can be a value of @ref MDMA_Destination_burst
+                                           @note : the burst may be FIXED/INCR based on DestinationInc value ,
+                                           the BURST must be programmed as to ensure that the burst size will be lower than than
+                                           BufferTransferLength */
+
+  int32_t SourceBlockAddressOffset;   /*!< this field specifies the Next block source address offset
+                                           signed value : if > 0 then  increment the next block source Address by offset from where the last block ends
+                                                          if < 0 then  decrement the next block source Address by offset from where the last block ends
+                                                          if == 0, the next block source address starts from where the last block ends
+                                       */
+
+
+  int32_t DestBlockAddressOffset;      /*!< this field specifies the Next block destination address offset
+                                           signed value : if > 0 then  increment the next block destination Address by offset from where the last block ends
+                                                          if < 0 then  decrement the next block destination Address by offset from where the last block ends
+                                                          if == 0, the next block destination address starts from where the last block ends
+                                       */
+
+}MDMA_InitTypeDef;
+
+/**
+  * @brief  HAL MDMA linked list node structure definition
+  * @note   The Linked list node allows to define a new MDMA configuration
+  *         (CTCR ,CBNDTR ,CSAR ,CDAR ,CBRUR, CLAR, CTBR, CMAR and CMDR registers).
+  *         When CLAR register is configured to a non NULL value , each time a transfer ends,
+  *         a new configuration (linked list node) is automatically loaded from the address given in CLAR register.
+  */
+typedef struct
+{
+  __IO uint32_t CTCR;     /*!< New CTCR register configuration for the given MDMA linked list node   */
+  __IO uint32_t CBNDTR;   /*!< New CBNDTR register configuration for the given MDMA linked list node */
+  __IO uint32_t CSAR;     /*!< New CSAR register configuration for the given MDMA linked list node   */
+  __IO uint32_t CDAR;     /*!< New CDAR register configuration for the given MDMA linked list node   */
+  __IO uint32_t CBRUR;    /*!< New CBRUR register configuration for the given MDMA linked list node  */
+  __IO uint32_t CLAR;     /*!< New CLAR register configuration for the given MDMA linked list node   */
+  __IO uint32_t CTBR;     /*!< New CTBR register configuration for the given MDMA linked list node   */
+  __IO uint32_t Reserved; /*!< Reserved register                                                     */
+  __IO uint32_t CMAR;     /*!< New CMAR register configuration for the given MDMA linked list node   */
+  __IO uint32_t CMDR;     /*!< New CMDR register configuration for the given MDMA linked list node   */
+
+}MDMA_LinkNodeTypeDef;
+
+/**
+  * @brief  HAL MDMA linked list node configuration structure definition
+  * @note   used with HAL_MDMA_LinkedList_CreateNode function
+  */
+typedef struct
+{
+  MDMA_InitTypeDef Init;            /*!< configuration of the specified MDMA Linked List Node    */
+  uint32_t         SrcAddress;      /*!< The source memory address for the Linked list Node      */
+  uint32_t         DstAddress;      /*!< The destination memory address for the Linked list Node */
+  uint32_t         BlockDataLength; /*!< The data length of a block in bytes                     */
+  uint32_t         BlockCount;      /*!< The number of blocks to be transferred                  */
+
+  uint32_t PostRequestMaskAddress;  /*!< specifies the address to be updated (written) with PostRequestMaskData after a request is served.
+                                         PostRequestMaskAddress and PostRequestMaskData could be used to automatically clear a peripheral flag when the request is served  */
+
+  uint32_t PostRequestMaskData;     /*!< specifies the value to be written to PostRequestMaskAddress after a request is served.
+                                         PostRequestMaskAddress and PostRequestMaskData could be used to automatically clear a peripheral flag when the request is served  */
+
+
+}MDMA_LinkNodeConfTypeDef;
+
+
+/**
+  * @brief  HAL MDMA State structure definition
+  */
+typedef enum
+{
+  HAL_MDMA_STATE_RESET               = 0x00U,  /*!< MDMA not yet initialized or disabled */
+  HAL_MDMA_STATE_READY               = 0x01U,  /*!< MDMA initialized and ready for use   */
+  HAL_MDMA_STATE_BUSY                = 0x02U,  /*!< MDMA process is ongoing              */
+  HAL_MDMA_STATE_ERROR               = 0x03U,  /*!< MDMA error state                     */
+  HAL_MDMA_STATE_ABORT               = 0x04U,  /*!< MDMA Abort state                     */
+
+}HAL_MDMA_StateTypeDef;
+
+/**
+  * @brief  HAL MDMA Level Complete structure definition
+  */
+typedef enum
+{
+  HAL_MDMA_FULL_TRANSFER         = 0x00U,   /*!< Full transfer         */
+  HAL_MDMA_BUFFER_TRANSFER       = 0x01U,   /*!< Buffer Transfer       */
+  HAL_MDMA_BLOCK_TRANSFER        = 0x02U,   /*!< Block Transfer        */
+  HAL_MDMA_REPEAT_BLOCK_TRANSFER = 0x03U    /*!< repeat block Transfer */
+
+}HAL_MDMA_LevelCompleteTypeDef;
+
+/**
+  * @brief  HAL MDMA Callbacks IDs structure definition
+  */
+typedef enum
+{
+  HAL_MDMA_XFER_CPLT_CB_ID          = 0x00U,    /*!< Full transfer           */
+  HAL_MDMA_XFER_BUFFERCPLT_CB_ID    = 0x01U,    /*!< Buffer Transfer         */
+  HAL_MDMA_XFER_BLOCKCPLT_CB_ID     = 0x02U,    /*!< Block Transfer          */
+  HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID  = 0x03U,    /*!< Repeated Block Transfer */
+  HAL_MDMA_XFER_ERROR_CB_ID         = 0x04U,    /*!< Error                   */
+  HAL_MDMA_XFER_ABORT_CB_ID         = 0x05U,    /*!< Abort                   */
+  HAL_MDMA_XFER_ALL_CB_ID           = 0x06U     /*!< All                     */
+
+}HAL_MDMA_CallbackIDTypeDef;
+
+
+/**
+  * @brief  MDMA handle Structure definition
+  */
+typedef struct __MDMA_HandleTypeDef
+{
+  MDMA_Channel_TypeDef *Instance;                                                              /*!< Register base address                  */
+
+  MDMA_InitTypeDef      Init;                                                                  /*!< MDMA communication parameters          */
+
+  HAL_LockTypeDef       Lock;                                                                  /*!< MDMA locking object                    */
+
+  __IO HAL_MDMA_StateTypeDef  State;                                                           /*!< MDMA transfer state                    */
+
+  void                  *Parent;                                                               /*!< Parent object state                    */
+
+  void                  (* XferCpltCallback)( struct __MDMA_HandleTypeDef * hmdma);            /*!< MDMA transfer complete callback        */
+
+  void                  (* XferBufferCpltCallback)( struct __MDMA_HandleTypeDef * hmdma);      /*!< MDMA buffer transfer complete callback */
+
+  void                  (* XferBlockCpltCallback)( struct __MDMA_HandleTypeDef * hmdma);       /*!< MDMA block transfer complete callback  */
+
+  void                  (* XferRepeatBlockCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA block transfer repeat callback    */
+
+  void                  (* XferErrorCallback)( struct __MDMA_HandleTypeDef * hmdma);           /*!< MDMA transfer error callback           */
+
+  void                  (* XferAbortCallback)( struct __MDMA_HandleTypeDef * hmdma);           /*!< MDMA transfer Abort callback           */
+
+
+  MDMA_LinkNodeTypeDef *FirstLinkedListNodeAddress;                                             /*!< specifies the first node address of the transfer list
+                                                                                                     (after the initial node defined by the Init struct)
+                                                                                                     this parameter is used internally by the MDMA driver
+                                                                                                     to construct the linked list node
+                                                                                                */
+
+  MDMA_LinkNodeTypeDef *LastLinkedListNodeAddress;                                             /*!< specifies the last node address of the transfer list
+                                                                                                    this parameter is used internally by the MDMA driver
+                                                                                                    to construct the linked list node
+                                                                                                */
+  uint32_t LinkedListNodeCounter;                                                               /*!< Number of nodes in the MDMA linked list */
+
+  __IO uint32_t          ErrorCode;                                                            /*!< MDMA Error code                        */
+
+} MDMA_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup MDMA_Exported_Constants MDMA Exported Constants
+  * @brief    MDMA Exported constants
+  * @{
+  */
+
+/** @defgroup MDMA_Error_Codes MDMA Error Codes
+  * @brief    MDMA Error Codes
+  * @{
+  */
+#define HAL_MDMA_ERROR_NONE        ((uint32_t)0x00000000U)   /*!< No error                               */
+#define HAL_MDMA_ERROR_READ_XFER   ((uint32_t)0x00000001U)   /*!< Read Transfer error                    */
+#define HAL_MDMA_ERROR_WRITE_XFER  ((uint32_t)0x00000002U)   /*!< Write Transfer error                   */
+#define HAL_MDMA_ERROR_MASK_DATA   ((uint32_t)0x00000004U)   /*!< Error Mask Data error                  */
+#define HAL_MDMA_ERROR_LINKED_LIST ((uint32_t)0x00000008U)   /*!< Linked list Data error                 */
+#define HAL_MDMA_ERROR_ALIGNMENT   ((uint32_t)0x00000010U)   /*!< Address/Size alignment  error          */
+#define HAL_MDMA_ERROR_BLOCK_SIZE  ((uint32_t)0x00000020U)   /*!< Block Size error                       */
+#define HAL_MDMA_ERROR_TIMEOUT     ((uint32_t)0x00000040U)   /*!< Timeout error                          */
+#define HAL_MDMA_ERROR_NO_XFER     ((uint32_t)0x00000080U)   /*!< Abort or SW trigger requested with no Xfer ongoing   */
+#define HAL_MDMA_ERROR_BUSY        ((uint32_t)0x00000100U)   /*!< DeInit or SW trigger requested with Xfer ongoing   */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_Request_selection MDMA Request selection
+  * @brief    MDMA_Request_selection
+  * @{
+  */
+
+#define MDMA_REQUEST_DMA1_Stream0_TC      ((uint32_t)0x00000000U)  /*!< MDMA HW request is DMA1 Stream 0 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA1_Stream1_TC      ((uint32_t)0x00000001U)  /*!< MDMA HW request is DMA1 Stream 1 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA1_Stream2_TC      ((uint32_t)0x00000002U)  /*!< MDMA HW request is DMA1 Stream 2 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA1_Stream3_TC      ((uint32_t)0x00000003U)  /*!< MDMA HW request is DMA1 Stream 3 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA1_Stream4_TC      ((uint32_t)0x00000004U)  /*!< MDMA HW request is DMA1 Stream 4 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA1_Stream5_TC      ((uint32_t)0x00000005U)  /*!< MDMA HW request is DMA1 Stream 5 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA1_Stream6_TC      ((uint32_t)0x00000006U)  /*!< MDMA HW request is DMA1 Stream 6 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA1_Stream7_TC      ((uint32_t)0x00000007U)  /*!< MDMA HW request is DMA1 Stream 7 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA2_Stream0_TC      ((uint32_t)0x00000008U)  /*!< MDMA HW request is DMA2 Stream 0 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA2_Stream1_TC      ((uint32_t)0x00000009U)  /*!< MDMA HW request is DMA2 Stream 1 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA2_Stream2_TC      ((uint32_t)0x0000000AU)  /*!< MDMA HW request is DMA2 Stream 2 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA2_Stream3_TC      ((uint32_t)0x0000000BU)  /*!< MDMA HW request is DMA2 Stream 3 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA2_Stream4_TC      ((uint32_t)0x0000000CU)  /*!< MDMA HW request is DMA2 Stream 4 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA2_Stream5_TC      ((uint32_t)0x0000000DU)  /*!< MDMA HW request is DMA2 Stream 5 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA2_Stream6_TC      ((uint32_t)0x0000000EU)  /*!< MDMA HW request is DMA2 Stream 6 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA2_Stream7_TC      ((uint32_t)0x0000000FU)  /*!< MDMA HW request is DMA2 Stream 7 Transfer Complete Flag   */
+#if defined (LTDC)
+#define MDMA_REQUEST_LTDC_LINE_IT         ((uint32_t)0x00000010U)  /*!< MDMA HW request is LTDC Line interrupt Flag               */
+#endif /* LTDC */
+#if defined (JPEG)
+#define MDMA_REQUEST_JPEG_INFIFO_TH       ((uint32_t)0x00000011U)  /*!< MDMA HW request is JPEG Input FIFO threshold Flag         */
+#define MDMA_REQUEST_JPEG_INFIFO_NF       ((uint32_t)0x00000012U)  /*!< MDMA HW request is JPEG Input FIFO not full Flag          */
+#define MDMA_REQUEST_JPEG_OUTFIFO_TH      ((uint32_t)0x00000013U)  /*!< MDMA HW request is JPEG Output FIFO threshold Flag        */
+#define MDMA_REQUEST_JPEG_OUTFIFO_NE      ((uint32_t)0x00000014U)  /*!< MDMA HW request is JPEG Output FIFO not empty Flag        */
+#define MDMA_REQUEST_JPEG_END_CONVERSION  ((uint32_t)0x00000015U)  /*!< MDMA HW request is JPEG End of conversion Flag            */
+#endif /* JPEG */
+#if defined (OCTOSPI1)
+#define MDMA_REQUEST_OCTOSPI1_FIFO_TH     ((uint32_t)0x00000016U)  /*!< MDMA HW request is OCTOSPI1 FIFO threshold Flag           */
+#define MDMA_REQUEST_OCTOSPI1_TC          ((uint32_t)0x00000017U)  /*!< MDMA HW request is OCTOSPI1 Transfer complete Flag        */
+#endif /* OCTOSPI1 */
+#if defined (QUADSPI)
+#define MDMA_REQUEST_QUADSPI_FIFO_TH      ((uint32_t)0x00000016U)  /*!< MDMA HW request is QSPI FIFO threshold Flag               */
+#define MDMA_REQUEST_QUADSPI_TC           ((uint32_t)0x00000017U)  /*!< MDMA HW request is QSPI Transfer complete Flag            */
+#endif /* QUADSPI */
+#define MDMA_REQUEST_DMA2D_CLUT_TC        ((uint32_t)0x00000018U)  /*!< MDMA HW request is DMA2D CLUT Transfer Complete Flag      */
+#define MDMA_REQUEST_DMA2D_TC             ((uint32_t)0x00000019U)  /*!< MDMA HW request is DMA2D Transfer Complete Flag           */
+#define MDMA_REQUEST_DMA2D_TW             ((uint32_t)0x0000001AU)  /*!< MDMA HW request is DMA2D Transfer Watermark Flag          */
+
+#if defined (DSI)
+#define MDMA_REQUEST_DSI_TEARING_EFFECT   ((uint32_t)0x0000001BU)  /*!< MDMA HW request is DSI Tearing Effect Flag                */
+#define MDMA_REQUEST_DSI_END_REFRESH      ((uint32_t)0x0000001CU)  /*!< MDMA HW request is DSI End of refresh  Flag               */
+#endif /* DSI */
+
+#define MDMA_REQUEST_SDMMC1_END_DATA      ((uint32_t)0x0000001DU)  /*!< MDMA HW request is SDMMC1 End of Data Flag                */
+
+#define MDMA_REQUEST_SDMMC1_DMA_ENDBUFFER ((uint32_t)0x0000001EU)  /*!< MDMA HW request is SDMMC1 Internal DMA buffer End Flag    */
+#define MDMA_REQUEST_SDMMC1_COMMAND_END   ((uint32_t)0x0000001FU)  /*!< MDMA HW request is SDMMC1 Command End Flag                */
+
+#if defined (OCTOSPI2)
+#define MDMA_REQUEST_OCTOSPI2_FIFO_TH     ((uint32_t)0x00000020U)  /*!< MDMA HW request is OCTOSPI2 FIFO threshold Flag           */
+#define MDMA_REQUEST_OCTOSPI2_TC          ((uint32_t)0x00000021U)  /*!< MDMA HW request is OCTOSPI2 Transfer complete Flag        */
+#endif /* OCTOSPI2 */
+
+#define MDMA_REQUEST_SW                   ((uint32_t)0x40000000U) /*!< MDMA SW request                                            */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_Transfer_TriggerMode MDMA Transfer Trigger  Mode
+  * @brief    MDMA Transfer Trigger Mode
+  * @{
+  */
+#define MDMA_BUFFER_TRANSFER          ((uint32_t)0x00000000U)        /*!< Each MDMA request (SW or HW) triggers a buffer transfer                                */
+#define MDMA_BLOCK_TRANSFER           ((uint32_t)MDMA_CTCR_TRGM_0)   /*!< Each MDMA request (SW or HW) triggers a block transfer                                 */
+#define MDMA_REPEAT_BLOCK_TRANSFER    ((uint32_t)MDMA_CTCR_TRGM_1)   /*!< Each MDMA request (SW or HW) triggers a repeated block transfer                        */
+#define MDMA_FULL_TRANSFER            ((uint32_t)MDMA_CTCR_TRGM)     /*!< Each MDMA request (SW or HW) triggers a Full transfer or a linked list transfer if any */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_Priority_level MDMA Priority level
+  * @brief    MDMA Priority level
+  * @{
+  */
+#define MDMA_PRIORITY_LOW             ((uint32_t)0x00000000U)     /*!< Priority level: Low      */
+#define MDMA_PRIORITY_MEDIUM          ((uint32_t)MDMA_CCR_PL_0)  /*!< Priority level: Medium    */
+#define MDMA_PRIORITY_HIGH            ((uint32_t)MDMA_CCR_PL_1)  /*!< Priority level: High      */
+#define MDMA_PRIORITY_VERY_HIGH       ((uint32_t)MDMA_CCR_PL)    /*!< Priority level: Very High */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup MDMA_Endianness MDMA Endianness
+  * @brief    MDMA Endianness
+  * @{
+  */
+#define MDMA_LITTLE_ENDIANNESS_PRESERVE          ((uint32_t)0x00000000U)   /*!< little endianness preserve                                               */
+#define MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE     ((uint32_t)MDMA_CCR_BEX)  /*!< BYTEs endianness exchange when destination data size is > Byte           */
+#define MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_HEX)  /*!< HALF WORDs endianness exchange when destination data size is > HALF WORD */
+#define MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE     ((uint32_t)MDMA_CCR_WEX)  /*!< WORDs endianness exchange  when destination data size is > DOUBLE WORD   */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_Source_increment_mode MDMA Source increment mode
+  * @brief    MDMA Source increment mode
+  * @{
+  */
+#define MDMA_SRC_INC_DISABLE      ((uint32_t)0x00000000U)                                     /*!< Source address pointer is fixed                                   */
+#define MDMA_SRC_INC_BYTE         ((uint32_t)MDMA_CTCR_SINC_1)                                /*!< Source address pointer is incremented by a BYTE (8 bits)          */
+#define MDMA_SRC_INC_HALFWORD     ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits)    */
+#define MDMA_SRC_INC_WORD         ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits)         */
+#define MDMA_SRC_INC_DOUBLEWORD   ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS)   /*!< Source address pointer is incremented by a double Word (64 bits)) */
+#define MDMA_SRC_DEC_BYTE         ((uint32_t)MDMA_CTCR_SINC)                                  /*!< Source address pointer is decremented by a BYTE (8 bits)          */
+#define MDMA_SRC_DEC_HALFWORD     ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_0)   /*!< Source address pointer is decremented by a half Word (16 bits)    */
+#define MDMA_SRC_DEC_WORD         ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_1)   /*!< Source address pointer is decremented by a Word (32 bits)         */
+#define MDMA_SRC_DEC_DOUBLEWORD   ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS)     /*!< Source address pointer is decremented by a double Word (64 bits)) */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_Destination_increment_mode MDMA Destination increment mode
+  * @brief    MDMA Destination increment mode
+  * @{
+  */
+#define MDMA_DEST_INC_DISABLE      ((uint32_t)0x00000000U)                                     /*!< Source address pointer is fixed                                   */
+#define MDMA_DEST_INC_BYTE         ((uint32_t)MDMA_CTCR_DINC_1)                                /*!< Source address pointer is incremented by a BYTE (8 bits)          */
+#define MDMA_DEST_INC_HALFWORD     ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits)    */
+#define MDMA_DEST_INC_WORD         ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits)         */
+#define MDMA_DEST_INC_DOUBLEWORD   ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS)   /*!< Source address pointer is incremented by a double Word (64 bits)) */
+#define MDMA_DEST_DEC_BYTE         ((uint32_t)MDMA_CTCR_DINC)                                  /*!< Source address pointer is decremented by a BYTE (8 bits)          */
+#define MDMA_DEST_DEC_HALFWORD     ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_0)   /*!< Source address pointer is decremented by a half Word (16 bits)    */
+#define MDMA_DEST_DEC_WORD         ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_1)   /*!< Source address pointer is decremented by a Word (32 bits)         */
+#define MDMA_DEST_DEC_DOUBLEWORD   ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS)     /*!< Source address pointer is decremented by a double Word (64 bits)) */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_Source_data_size MDMA Source data size
+  * @brief    MDMA Source data size
+  * @{
+  */
+#define MDMA_SRC_DATASIZE_BYTE        ((uint32_t)0x00000000U)         /*!< Source data size is Byte        */
+#define MDMA_SRC_DATASIZE_HALFWORD    ((uint32_t)MDMA_CTCR_SSIZE_0)   /*!< Source data size is half word   */
+#define MDMA_SRC_DATASIZE_WORD        ((uint32_t)MDMA_CTCR_SSIZE_1)   /*!< Source data size is word        */
+#define MDMA_SRC_DATASIZE_DOUBLEWORD  ((uint32_t)MDMA_CTCR_SSIZE)     /*!< Source data size is double word */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_Destination_data_size MDMA Destination data size
+  * @brief    MDMA Destination data size
+  * @{
+  */
+#define MDMA_DEST_DATASIZE_BYTE        ((uint32_t)0x00000000U)         /*!< Destination data size is Byte        */
+#define MDMA_DEST_DATASIZE_HALFWORD    ((uint32_t)MDMA_CTCR_DSIZE_0)   /*!< Destination data size is half word   */
+#define MDMA_DEST_DATASIZE_WORD        ((uint32_t)MDMA_CTCR_DSIZE_1)   /*!< Destination data size is word        */
+#define MDMA_DEST_DATASIZE_DOUBLEWORD  ((uint32_t)MDMA_CTCR_DSIZE)     /*!< Destination data size is double word */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_data_Alignment MDMA data alignment
+  * @brief    MDMA data alignment
+  * @{
+  */
+#define MDMA_DATAALIGN_PACKENABLE        ((uint32_t)MDMA_CTCR_PKE)     /*!< The source data is packed/un-packed into the destination data size
+                                                                            All data are right aligned, in Little Endien mode.                                              */
+#define MDMA_DATAALIGN_RIGHT            ((uint32_t)0x00000000U)        /*!< Right Aligned, padded w/ 0s (default)                                                           */
+#define MDMA_DATAALIGN_RIGHT_SIGNED     ((uint32_t)MDMA_CTCR_PAM_0)    /*!< Right Aligned, Sign extended ,
+                                                                            Note : this mode is allowed only if the Source data size is smaller than Destination data size  */
+#define MDMA_DATAALIGN_LEFT             ((uint32_t)MDMA_CTCR_PAM_1)    /*!< Left Aligned (padded with 0s)                                                                   */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_Source_burst MDMA Source burst
+  * @brief    MDMA Source burst
+  * @{
+  */
+#define MDMA_SOURCE_BURST_SINGLE        ((uint32_t)0x00000000U)                                       /*!< single transfer */
+#define MDMA_SOURCE_BURST_2BEATS        ((uint32_t)MDMA_CTCR_SBURST_0)                                /*!< Burst 2 beats   */
+#define MDMA_SOURCE_BURST_4BEATS        ((uint32_t)MDMA_CTCR_SBURST_1)                                /*!< Burst 4 beats   */
+#define MDMA_SOURCE_BURST_8BEATS        ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_1) /*!< Burst 8 beats   */
+#define MDMA_SOURCE_BURST_16BEATS       ((uint32_t)MDMA_CTCR_SBURST_2)                                /*!< Burst 16 beats  */
+#define MDMA_SOURCE_BURST_32BEATS       ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 32 beats  */
+#define MDMA_SOURCE_BURST_64BEATS       ((uint32_t)MDMA_CTCR_SBURST_1 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 64 beats  */
+#define MDMA_SOURCE_BURST_128BEATS      ((uint32_t)MDMA_CTCR_SBURST)                                  /*!< Burst 128 beats */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_Destination_burst MDMA Destination burst
+  * @brief    MDMA Destination burst
+  * @{
+  */
+#define MDMA_DEST_BURST_SINGLE        ((uint32_t)0x00000000U)                                        /*!< single transfer */
+#define MDMA_DEST_BURST_2BEATS        ((uint32_t)MDMA_CTCR_DBURST_0)                                 /*!< Burst 2 beats   */
+#define MDMA_DEST_BURST_4BEATS        ((uint32_t)MDMA_CTCR_DBURST_1)                                 /*!< Burst 4 beats   */
+#define MDMA_DEST_BURST_8BEATS        ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_1)  /*!< Burst 8 beats   */
+#define MDMA_DEST_BURST_16BEATS       ((uint32_t)MDMA_CTCR_DBURST_2)                                 /*!< Burst 16 beats  */
+#define MDMA_DEST_BURST_32BEATS       ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_2)  /*!< Burst 32 beats  */
+#define MDMA_DEST_BURST_64BEATS       ((uint32_t)MDMA_CTCR_DBURST_1 | (uint32_t)MDMA_CTCR_DBURST_2)  /*!< Burst 64 beats  */
+#define MDMA_DEST_BURST_128BEATS      ((uint32_t)MDMA_CTCR_DBURST)                                   /*!< Burst 128 beats */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_interrupt_enable_definitions MDMA interrupt enable definitions
+  * @brief    MDMA interrupt enable definitions
+  * @{
+  */
+#define MDMA_IT_TE   ((uint32_t)MDMA_CCR_TEIE)   /*!< Transfer Error interrupt            */
+#define MDMA_IT_CTC  ((uint32_t)MDMA_CCR_CTCIE)  /*!< Channel Transfer Complete interrupt */
+#define MDMA_IT_BRT  ((uint32_t)MDMA_CCR_BRTIE)  /*!< Block Repeat Transfer interrupt     */
+#define MDMA_IT_BT   ((uint32_t)MDMA_CCR_BTIE)   /*!< Block Transfer interrupt            */
+#define MDMA_IT_BFTC ((uint32_t)MDMA_CCR_TCIE)   /*!< Buffer Transfer Complete interrupt  */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_flag_definitions MDMA flag definitions
+  * @brief    MDMA flag definitions
+  * @{
+  */
+#define MDMA_FLAG_TE    ((uint32_t)MDMA_CISR_TEIF)  /*!< Transfer Error flag                 */
+#define MDMA_FLAG_CTC   ((uint32_t)MDMA_CISR_CTCIF) /*!< Channel Transfer Complete flag      */
+#define MDMA_FLAG_BRT   ((uint32_t)MDMA_CISR_BRTIF) /*!< Block Repeat Transfer complete flag */
+#define MDMA_FLAG_BT    ((uint32_t)MDMA_CISR_BTIF)  /*!< Block Transfer complete flag        */
+#define MDMA_FLAG_BFTC  ((uint32_t)MDMA_CISR_TCIF)  /*!< BuFfer Transfer complete flag       */
+#define MDMA_FLAG_CRQA  ((uint32_t)MDMA_CISR_CRQA)  /*!< Channel ReQest Active flag          */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup MDMA_Exported_Macros MDMA Exported Macros
+  * @{
+  */
+
+/**
+  * @brief  Enable the specified MDMA Channel.
+  * @param  __HANDLE__: MDMA handle
+  * @retval None
+  */
+#define __HAL_MDMA_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CCR |=  MDMA_CCR_EN)
+
+/**
+  * @brief  Disable the specified MDMA Channel.
+  * @param  __HANDLE__: MDMA handle
+  * @retval None
+  */
+#define __HAL_MDMA_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CCR &=  ~MDMA_CCR_EN)
+
+/**
+  * @brief  Get the MDMA Channel pending flags.
+  * @param  __HANDLE__: MDMA handle
+  * @param  __FLAG__: Get the specified flag.
+  *          This parameter can be any combination of the following values:
+  *            @arg MDMA_FLAG_TE   : Transfer Error flag.
+  *            @arg MDMA_FLAG_CTC  : Channel Transfer Complete flag.
+  *            @arg MDMA_FLAG_BRT  : Block Repeat Transfer flag.
+  *            @arg MDMA_FLAG_BT   : Block Transfer complete flag.
+  *            @arg MDMA_FLAG_BFTC : BuFfer Transfer Complete flag.
+  *            @arg MDMA_FLAG_CRQA : Channel ReQest Active flag.
+  * @retval The state of FLAG (SET or RESET).
+  */
+#define __HAL_MDMA_GET_FLAG(__HANDLE__, __FLAG__)  ((__HANDLE__)->Instance->CISR & (__FLAG__))
+
+/**
+  * @brief  Clear the MDMA Stream pending flags.
+  * @param  __HANDLE__: MDMA handle
+  * @param  __FLAG__: specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg MDMA_FLAG_TE   : Transfer Error flag.
+  *            @arg MDMA_FLAG_CTC  : Channel Transfer Complete flag.
+  *            @arg MDMA_FLAG_BRT  : Block Repeat Transfer flag.
+  *            @arg MDMA_FLAG_BT   : Block Transfer complete flag.
+  *            @arg MDMA_FLAG_BFTC : BuFfer Transfer Complete flag.
+  * @retval None
+  */
+#define __HAL_MDMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CIFCR = (__FLAG__))
+
+/**
+  * @brief  Enables the specified MDMA Channel interrupts.
+  * @param  __HANDLE__: MDMA handle
+  * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg MDMA_IT_TE   :  Transfer Error interrupt mask
+  *            @arg MDMA_IT_CTC  :  Channel Transfer Complete interrupt mask
+  *            @arg MDMA_IT_BRT  :  Block Repeat Transfer interrupt mask
+  *            @arg MDMA_IT_BT   :  Block Transfer interrupt mask
+  *            @arg MDMA_IT_BFTC :  BuFfer Transfer Complete interrupt mask
+  * @retval None
+  */
+#define __HAL_MDMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
+
+/**
+  * @brief  Disables the specified MDMA Channel interrupts.
+  * @param  __HANDLE__: MDMA handle
+  * @param __INTERRUPT__: specifies the MDMA interrupt sources to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg MDMA_IT_TE   :  Transfer Error interrupt mask
+  *            @arg MDMA_IT_CTC  :  Channel Transfer Complete interrupt mask
+  *            @arg MDMA_IT_BRT  :  Block Repeat Transfer interrupt mask
+  *            @arg MDMA_IT_BT   :  Block Transfer interrupt mask
+  *            @arg MDMA_IT_BFTC :  BuFfer Transfer Complete interrupt mask
+  * @retval None
+  */
+#define __HAL_MDMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Checks whether the specified MDMA Channel interrupt is enabled or not.
+  * @param  __HANDLE__: DMA handle
+  * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
+  *            @arg MDMA_IT_TE   :  Transfer Error interrupt mask
+  *            @arg MDMA_IT_CTC  :  Channel Transfer Complete interrupt mask
+  *            @arg MDMA_IT_BRT  :  Block Repeat Transfer interrupt mask
+  *            @arg MDMA_IT_BT   :  Block Transfer interrupt mask
+  *            @arg MDMA_IT_BFTC :  BuFfer Transfer Complete interrupt mask
+  * @retval The state of MDMA_IT (SET or RESET).
+  */
+#define __HAL_MDMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup MDMA_Exported_Functions  MDMA Exported Functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions *****************************/
+/** @defgroup MDMA_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief   Initialization and de-initialization functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_MDMA_Init(MDMA_HandleTypeDef *hmdma);
+HAL_StatusTypeDef HAL_MDMA_DeInit (MDMA_HandleTypeDef *hmdma);
+HAL_StatusTypeDef HAL_MDMA_ConfigPostRequestMask(MDMA_HandleTypeDef *hmdma, uint32_t MaskAddress, uint32_t MaskData);
+
+HAL_StatusTypeDef HAL_MDMA_RegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID, void (* pCallback)(MDMA_HandleTypeDef *_hmdma));
+HAL_StatusTypeDef HAL_MDMA_UnRegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID);
+
+/**
+  * @}
+  */
+
+/* Linked list operation functions ********************************************/
+/** @defgroup MDMA_Exported_Functions_Group2 Linked List operation functions
+  * @brief   Linked list operation functions
+  * @{
+  */
+
+HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig);
+HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, MDMA_LinkNodeTypeDef *pPrevNode);
+HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNode);
+HAL_StatusTypeDef HAL_MDMA_LinkedList_EnableCircularMode(MDMA_HandleTypeDef *hmdma);
+HAL_StatusTypeDef HAL_MDMA_LinkedList_DisableCircularMode(MDMA_HandleTypeDef *hmdma);
+
+
+/**
+  * @}
+  */
+
+/* IO operation functions *****************************************************/
+/** @defgroup MDMA_Exported_Functions_Group3 I/O operation functions
+  * @brief   I/O operation functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_MDMA_Start (MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount);
+HAL_StatusTypeDef HAL_MDMA_Start_IT(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount);
+HAL_StatusTypeDef HAL_MDMA_Abort(MDMA_HandleTypeDef *hmdma);
+HAL_StatusTypeDef HAL_MDMA_Abort_IT(MDMA_HandleTypeDef *hmdma);
+HAL_StatusTypeDef HAL_MDMA_PollForTransfer(MDMA_HandleTypeDef *hmdma, HAL_MDMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
+HAL_StatusTypeDef HAL_MDMA_GenerateSWRequest(MDMA_HandleTypeDef *hmdma);
+void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma);
+
+/**
+  * @}
+  */
+
+/* Peripheral State and Error functions ***************************************/
+/** @defgroup MDMA_Exported_Functions_Group4 Peripheral State functions
+  * @brief    Peripheral State functions
+  * @{
+  */
+HAL_MDMA_StateTypeDef HAL_MDMA_GetState(MDMA_HandleTypeDef *hmdma);
+uint32_t              HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup MDMA_Private_Types MDMA Private Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup MDMA_Private_Defines MDMA Private Defines
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup MDMA_Private_Variables MDMA Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup MDMA_Private_Constants MDMA Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup MDMA_Private_Macros MDMA Private Macros
+  * @{
+  */
+
+#define IS_MDMA_LEVEL_COMPLETE(__LEVEL__) (((__LEVEL__) == HAL_MDMA_FULL_TRANSFER )  || \
+                                           ((__LEVEL__) == HAL_MDMA_BUFFER_TRANSFER )|| \
+                                           ((__LEVEL__) == HAL_MDMA_BLOCK_TRANSFER ) || \
+                                           ((__LEVEL__) == HAL_MDMA_REPEAT_BLOCK_TRANSFER ))
+
+
+#define IS_MDMA_PRIORITY(__PRIORITY__) (((__PRIORITY__) == MDMA_PRIORITY_LOW )   || \
+                                        ((__PRIORITY__) == MDMA_PRIORITY_MEDIUM) || \
+                                        ((__PRIORITY__) == MDMA_PRIORITY_HIGH)   || \
+                                        ((__PRIORITY__) == MDMA_PRIORITY_VERY_HIGH))
+
+#define IS_MDMA_ENDIANNESS_MODE(__ENDIANNESS__) (((__ENDIANNESS__) == MDMA_LITTLE_ENDIANNESS_PRESERVE )         || \
+                                                 ((__ENDIANNESS__) == MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE)     || \
+                                                 ((__ENDIANNESS__) == MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE) || \
+                                                 ((__ENDIANNESS__) == MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE))
+
+
+#if defined (OCTOSPI2)
+#define IS_MDMA_REQUEST(__REQUEST__) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_OCTOSPI2_TC))
+#else
+#define IS_MDMA_REQUEST(__REQUEST__) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_SDMMC1_COMMAND_END))
+#endif /* OCTOSPI2 */
+
+#define IS_MDMA_SOURCE_INC(__INC__) (((__INC__) == MDMA_SRC_INC_DISABLE )   || \
+                                     ((__INC__) == MDMA_SRC_INC_BYTE )      || \
+                                     ((__INC__) == MDMA_SRC_INC_HALFWORD )  || \
+                                     ((__INC__) == MDMA_SRC_INC_WORD )      || \
+                                     ((__INC__) == MDMA_SRC_INC_DOUBLEWORD) || \
+                                     ((__INC__) == MDMA_SRC_DEC_BYTE)       || \
+                                     ((__INC__) == MDMA_SRC_DEC_HALFWORD)   || \
+                                     ((__INC__) == MDMA_SRC_DEC_WORD)       || \
+                                     ((__INC__) == MDMA_SRC_DEC_DOUBLEWORD))
+
+#define IS_MDMA_DESTINATION_INC(__INC__) (((__INC__) == MDMA_DEST_INC_DISABLE )   || \
+                                          ((__INC__) == MDMA_DEST_INC_BYTE )      || \
+                                          ((__INC__) == MDMA_DEST_INC_HALFWORD )  || \
+                                          ((__INC__) == MDMA_DEST_INC_WORD )      || \
+                                          ((__INC__) == MDMA_DEST_INC_DOUBLEWORD) || \
+                                          ((__INC__) == MDMA_DEST_DEC_BYTE)       || \
+                                          ((__INC__) == MDMA_DEST_DEC_HALFWORD)   || \
+                                          ((__INC__) == MDMA_DEST_DEC_WORD)       || \
+                                          ((__INC__) == MDMA_DEST_DEC_DOUBLEWORD))
+
+#define IS_MDMA_SOURCE_DATASIZE(__SIZE__) (((__SIZE__) == MDMA_SRC_DATASIZE_BYTE )     || \
+                                           ((__SIZE__) == MDMA_SRC_DATASIZE_HALFWORD ) || \
+                                           ((__SIZE__) == MDMA_SRC_DATASIZE_WORD )     || \
+                                           ((__SIZE__) == MDMA_SRC_DATASIZE_DOUBLEWORD))
+
+#define IS_MDMA_DESTINATION_DATASIZE(__SIZE__) (((__SIZE__) == MDMA_DEST_DATASIZE_BYTE )     || \
+                                                ((__SIZE__) == MDMA_DEST_DATASIZE_HALFWORD ) || \
+                                                ((__SIZE__) == MDMA_DEST_DATASIZE_WORD )     || \
+                                                ((__SIZE__) == MDMA_DEST_DATASIZE_DOUBLEWORD))
+
+#define IS_MDMA_DATA_ALIGNMENT(__ALIGNMENT__) (((__ALIGNMENT__) == MDMA_DATAALIGN_PACKENABLE )    || \
+                                               ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT )         || \
+                                               ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT_SIGNED )  || \
+                                               ((__ALIGNMENT__) == MDMA_DATAALIGN_LEFT))
+
+
+#define IS_MDMA_SOURCE_BURST(__BURST__) (((__BURST__) == MDMA_SOURCE_BURST_SINGLE ) || \
+                                         ((__BURST__) == MDMA_SOURCE_BURST_2BEATS ) || \
+                                         ((__BURST__) == MDMA_SOURCE_BURST_4BEATS ) || \
+                                         ((__BURST__) == MDMA_SOURCE_BURST_8BEATS)  || \
+                                         ((__BURST__) == MDMA_SOURCE_BURST_16BEATS) || \
+                                         ((__BURST__) == MDMA_SOURCE_BURST_32BEATS) || \
+                                         ((__BURST__) == MDMA_SOURCE_BURST_64BEATS) || \
+                                         ((__BURST__) == MDMA_SOURCE_BURST_128BEATS))
+
+
+#define IS_MDMA_DESTINATION_BURST(__BURST__) (((__BURST__) == MDMA_DEST_BURST_SINGLE ) || \
+                                              ((__BURST__) == MDMA_DEST_BURST_2BEATS ) || \
+                                              ((__BURST__) == MDMA_DEST_BURST_4BEATS ) || \
+                                              ((__BURST__) == MDMA_DEST_BURST_8BEATS)  || \
+                                              ((__BURST__) == MDMA_DEST_BURST_16BEATS) || \
+                                              ((__BURST__) == MDMA_DEST_BURST_32BEATS) || \
+                                              ((__BURST__) == MDMA_DEST_BURST_64BEATS) || \
+                                              ((__BURST__) == MDMA_DEST_BURST_128BEATS))
+
+ #define IS_MDMA_TRANSFER_TRIGGER_MODE(__MODE__) (((__MODE__) == MDMA_BUFFER_TRANSFER )      || \
+                                                  ((__MODE__) == MDMA_BLOCK_TRANSFER )        || \
+                                                  ((__MODE__) == MDMA_REPEAT_BLOCK_TRANSFER ) || \
+                                                  ((__MODE__) == MDMA_FULL_TRANSFER))
+
+#define IS_MDMA_BUFFER_TRANSFER_LENGTH(__LENGTH__) (((__LENGTH__) >= 0x00000001U) && ((__LENGTH__) < 0x000000FFU))
+
+#define IS_MDMA_BLOCK_COUNT(__COUNT__) (((__COUNT__) > 0U ) && ((__COUNT__) <= 4096U))
+
+#define IS_MDMA_TRANSFER_LENGTH(SIZE) (((SIZE) > 0U) && ((SIZE) <= 65536U))
+
+#define IS_MDMA_BLOCK_ADDR_OFFSET(__BLOCK_ADD_OFFSET__) (((__BLOCK_ADD_OFFSET__) > (-65536)) && ((__BLOCK_ADD_OFFSET__) < 65536))
+
+/**
+  * @}
+  */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup MDMA_Private_Functions_Prototypes MDMA Private Functions Prototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup MDMA_Private_Functions MDMA Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_MDMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h
new file mode 100644
index 00000000..a47aaaef
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h
@@ -0,0 +1,436 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_pcd.h
+  * @author  MCD Application Team
+  * @brief   Header file of PCD HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_PCD_H
+#define STM32H7xx_HAL_PCD_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_ll_usb.h"
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup PCD
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup PCD_Exported_Types PCD Exported Types
+  * @{
+  */
+
+/**
+  * @brief  PCD State structure definition
+  */
+typedef enum
+{
+  HAL_PCD_STATE_RESET   = 0x00,
+  HAL_PCD_STATE_READY   = 0x01,
+  HAL_PCD_STATE_ERROR   = 0x02,
+  HAL_PCD_STATE_BUSY    = 0x03,
+  HAL_PCD_STATE_TIMEOUT = 0x04
+} PCD_StateTypeDef;
+
+/* Device LPM suspend state */
+typedef enum
+{
+  LPM_L0 = 0x00, /* on */
+  LPM_L1 = 0x01, /* LPM L1 sleep */
+  LPM_L2 = 0x02, /* suspend */
+  LPM_L3 = 0x03, /* off */
+} PCD_LPM_StateTypeDef;
+
+typedef enum
+{
+  PCD_LPM_L0_ACTIVE = 0x00, /* on */
+  PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
+} PCD_LPM_MsgTypeDef;
+
+typedef enum
+{
+  PCD_BCD_ERROR                     = 0xFF,
+  PCD_BCD_CONTACT_DETECTION         = 0xFE,
+  PCD_BCD_STD_DOWNSTREAM_PORT       = 0xFD,
+  PCD_BCD_CHARGING_DOWNSTREAM_PORT  = 0xFC,
+  PCD_BCD_DEDICATED_CHARGING_PORT   = 0xFB,
+  PCD_BCD_DISCOVERY_COMPLETED       = 0x00,
+
+} PCD_BCD_MsgTypeDef;
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+typedef USB_OTG_GlobalTypeDef  PCD_TypeDef;
+typedef USB_OTG_CfgTypeDef     PCD_InitTypeDef;
+typedef USB_OTG_EPTypeDef      PCD_EPTypeDef;
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+/**
+  * @brief  PCD Handle Structure definition
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+typedef struct __PCD_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  PCD_TypeDef             *Instance;   /*!< Register base address              */
+  PCD_InitTypeDef         Init;        /*!< PCD required parameters            */
+  __IO uint8_t            USB_Address; /*!< USB Address                        */
+  PCD_EPTypeDef           IN_ep[16];   /*!< IN endpoint parameters             */
+  PCD_EPTypeDef           OUT_ep[16];  /*!< OUT endpoint parameters            */
+  HAL_LockTypeDef         Lock;        /*!< PCD peripheral status              */
+  __IO PCD_StateTypeDef   State;       /*!< PCD communication state            */
+  __IO  uint32_t          ErrorCode;   /*!< PCD Error code                     */
+  uint32_t                Setup[12];   /*!< Setup packet buffer                */
+  PCD_LPM_StateTypeDef    LPM_State;   /*!< LPM State                          */
+  uint32_t                BESL;
+
+
+  uint32_t lpm_active;                 /*!< Enable or disable the Link Power Management .
+                                       This parameter can be set to ENABLE or DISABLE        */
+
+  uint32_t battery_charging_active;    /*!< Enable or disable Battery charging.
+                                       This parameter can be set to ENABLE or DISABLE        */
+  void                    *pData;      /*!< Pointer to upper stack Handler */
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+  void (* SOFCallback)(struct __PCD_HandleTypeDef *hpcd);                              /*!< USB OTG PCD SOF callback                */
+  void (* SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd);                       /*!< USB OTG PCD Setup Stage callback        */
+  void (* ResetCallback)(struct __PCD_HandleTypeDef *hpcd);                            /*!< USB OTG PCD Reset callback              */
+  void (* SuspendCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Suspend callback            */
+  void (* ResumeCallback)(struct __PCD_HandleTypeDef *hpcd);                           /*!< USB OTG PCD Resume callback             */
+  void (* ConnectCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Connect callback            */
+  void (* DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd);                       /*!< USB OTG PCD Disconnect callback         */
+
+  void (* DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);      /*!< USB OTG PCD Data OUT Stage callback     */
+  void (* DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);       /*!< USB OTG PCD Data IN Stage callback      */
+  void (* ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);  /*!< USB OTG PCD ISO OUT Incomplete callback */
+  void (* ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);   /*!< USB OTG PCD ISO IN Incomplete callback  */
+  void (* BCDCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);      /*!< USB OTG PCD BCD callback                */
+  void (* LPMCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);      /*!< USB OTG PCD LPM callback                */
+
+  void (* MspInitCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Msp Init callback           */
+  void (* MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd);                        /*!< USB OTG PCD Msp DeInit callback         */
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+} PCD_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Include PCD HAL Extended module */
+#include "stm32h7xx_hal_pcd_ex.h"
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PCD_Exported_Constants PCD Exported Constants
+  * @{
+  */
+
+/** @defgroup PCD_Speed PCD Speed
+  * @{
+  */
+#define PCD_SPEED_HIGH               USBD_HS_SPEED
+#define PCD_SPEED_HIGH_IN_FULL       USBD_HSINFS_SPEED
+#define PCD_SPEED_FULL               USBD_FS_SPEED
+/**
+  * @}
+  */
+
+/** @defgroup PCD_PHY_Module PCD PHY Module
+  * @{
+  */
+#define PCD_PHY_ULPI                 1U
+#define PCD_PHY_EMBEDDED             2U
+#define PCD_PHY_UTMI                 3U
+/**
+  * @}
+  */
+
+/** @defgroup PCD_Error_Code_definition PCD Error Code definition
+  * @brief  PCD Error Code definition
+  * @{
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+#define  HAL_PCD_ERROR_INVALID_CALLBACK                        (0x00000010U)    /*!< Invalid Callback error  */
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup PCD_Exported_Macros PCD Exported Macros
+ *  @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+#define __HAL_PCD_ENABLE(__HANDLE__)                       (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_PCD_DISABLE(__HANDLE__)                      (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
+
+#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) &=  (__INTERRUPT__))
+#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
+
+
+#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__)             *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
+                                                          ~(USB_OTG_PCGCCTL_STOPCLK)
+
+#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__)               *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
+
+#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__)            ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)
+
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT()    EXTI_D1->IMR2 |= (USB_OTG_HS_WAKEUP_EXTI_LINE)
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT()   EXTI_D1->IMR2 &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT()    EXTI_D1->IMR2 |= (USB_OTG_FS_WAKEUP_EXTI_LINE)
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT()   EXTI_D1->IMR2 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PCD_Exported_Functions PCD Exported Functions
+  * @{
+  */
+
+/* Initialization/de-initialization functions  ********************************/
+/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+/** @defgroup HAL_PCD_Callback_ID_enumeration_definition HAL USB OTG PCD Callback ID enumeration definition
+  * @brief  HAL USB OTG PCD Callback ID enumeration definition
+  * @{
+  */
+typedef enum
+{
+  HAL_PCD_SOF_CB_ID          = 0x01,      /*!< USB PCD SOF callback ID          */
+  HAL_PCD_SETUPSTAGE_CB_ID   = 0x02,      /*!< USB PCD Setup Stage callback ID  */
+  HAL_PCD_RESET_CB_ID        = 0x03,      /*!< USB PCD Reset callback ID        */
+  HAL_PCD_SUSPEND_CB_ID      = 0x04,      /*!< USB PCD Suspend callback ID      */
+  HAL_PCD_RESUME_CB_ID       = 0x05,      /*!< USB PCD Resume callback ID       */
+  HAL_PCD_CONNECT_CB_ID      = 0x06,      /*!< USB PCD Connect callback ID      */
+  HAL_PCD_DISCONNECT_CB_ID  = 0x07,      /*!< USB PCD Disconnect callback ID   */
+
+  HAL_PCD_MSPINIT_CB_ID      = 0x08,      /*!< USB PCD MspInit callback ID      */
+  HAL_PCD_MSPDEINIT_CB_ID    = 0x09       /*!< USB PCD MspDeInit callback ID    */
+
+} HAL_PCD_CallbackIDTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup HAL_PCD_Callback_pointer_definition HAL USB OTG PCD Callback pointer definition
+  * @brief  HAL USB OTG PCD Callback pointer definition
+  * @{
+  */
+
+typedef void (*pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd);                                   /*!< pointer to a common USB OTG PCD callback function  */
+typedef void (*pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);        /*!< pointer to USB OTG PCD Data OUT Stage callback     */
+typedef void (*pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);         /*!< pointer to USB OTG PCD Data IN Stage callback      */
+typedef void (*pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);        /*!< pointer to USB OTG PCD ISO OUT Incomplete callback */
+typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);         /*!< pointer to USB OTG PCD ISO IN Incomplete callback  */
+typedef void (*pPCD_LpmCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);        /*!< pointer to USB OTG PCD LPM callback                */
+typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);        /*!< pointer to USB OTG PCD BCD callback                */
+
+/**
+  * @}
+  */
+
+HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/* I/O operation functions  ***************************************************/
+/* Non-Blocking mode: Interrupt */
+/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
+
+void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
+
+void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+/**
+  * @}
+  */
+
+/* Peripheral Control functions  **********************************************/
+/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
+HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
+uint32_t          HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
+/**
+  * @}
+  */
+
+/* Peripheral State functions  ************************************************/
+/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
+  * @{
+  */
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup PCD_Private_Constants PCD Private Constants
+  * @{
+  */
+/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt
+  * @{
+  */
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE                            0x08U
+#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE                           0x0CU
+#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE                    0x10U
+
+#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE                            0x08U
+#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE                           0x0CU
+#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE                    0x10U
+
+#define USB_OTG_FS_WAKEUP_EXTI_LINE                                   (0x1U << 12)  /*!< USB FS EXTI Line WakeUp Interrupt */
+#define USB_OTG_HS_WAKEUP_EXTI_LINE                                   (0x1U << 11)  /*!< USB HS EXTI Line WakeUp Interrupt */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+#ifndef USB_OTG_DOEPINT_OTEPSPR
+#define USB_OTG_DOEPINT_OTEPSPR                (0x1UL << 5)      /*!< Status Phase Received interrupt */
+#endif
+
+#ifndef USB_OTG_DOEPMSK_OTEPSPRM
+#define USB_OTG_DOEPMSK_OTEPSPRM               (0x1UL << 5)      /*!< Setup Packet Received interrupt mask */
+#endif
+
+#ifndef USB_OTG_DOEPINT_NAK
+#define USB_OTG_DOEPINT_NAK                    (0x1UL << 13)      /*!< NAK interrupt */
+#endif
+
+#ifndef USB_OTG_DOEPMSK_NAKM
+#define USB_OTG_DOEPMSK_NAKM                   (0x1UL << 13)      /*!< OUT Packet NAK interrupt mask */
+#endif
+
+#ifndef USB_OTG_DOEPINT_STPKTRX
+#define USB_OTG_DOEPINT_STPKTRX                (0x1UL << 15)      /*!< Setup Packet Received interrupt */
+#endif
+
+#ifndef USB_OTG_DOEPMSK_NYETM
+#define USB_OTG_DOEPMSK_NYETM                  (0x1UL << 14)      /*!< Setup Packet Received interrupt mask */
+#endif
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PCD_Private_Macros PCD Private Macros
+ * @{
+ */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_PCD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h
new file mode 100644
index 00000000..21d5b92f
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h
@@ -0,0 +1,91 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_pcd_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of PCD HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_PCD_EX_H
+#define STM32H7xx_HAL_PCD_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup PCDEx
+  * @{
+  */
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
+  * @{
+  */
+/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
+  * @{
+  */
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
+HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+
+HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
+
+
+HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd);
+void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd);
+
+void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
+void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32H7xx_HAL_PCD_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h
new file mode 100644
index 00000000..0d462402
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h
@@ -0,0 +1,774 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_pwr.h
+  * @author  MCD Application Team
+  * @brief   Header file of PWR HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_PWR_H
+#define STM32H7xx_HAL_PWR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup PWR
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Types PWR Exported Types
+  * @{
+  */
+
+/**
+  * @brief  PWR PVD configuration structure definition
+  */
+typedef struct
+{
+  uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. This
+                                    parameter can be a value of @ref
+                                    PWR_PVD_detection_level.
+                     */
+
+  uint32_t Mode;     /*!< Mode: Specifies the EXTI operating mode for the PVD
+                                event. This parameter can be a value of @ref
+                                PWR_PVD_Mode.
+                     */
+}PWR_PVDTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PWR_Exported_Constants PWR Exported Constants
+  * @{
+  */
+
+/** @defgroup PWR_PVD_detection_level PWR PVD detection level
+  * @{
+  */
+#define PWR_PVDLEVEL_0  PWR_CR1_PLS_LEV0  /*!< Programmable voltage detector
+                                               level 0 selection : 1V95       */
+#define PWR_PVDLEVEL_1  PWR_CR1_PLS_LEV1  /*!< Programmable voltage detector
+                                               level 1 selection : 2V1        */
+#define PWR_PVDLEVEL_2  PWR_CR1_PLS_LEV2  /*!< Programmable voltage detector
+                                               level 2 selection : 2V25       */
+#define PWR_PVDLEVEL_3  PWR_CR1_PLS_LEV3  /*!< Programmable voltage detector
+                                               level 3 selection : 2V4        */
+#define PWR_PVDLEVEL_4  PWR_CR1_PLS_LEV4  /*!< Programmable voltage detector
+                                               level 4 selection : 2V55       */
+#define PWR_PVDLEVEL_5  PWR_CR1_PLS_LEV5  /*!< Programmable voltage detector
+                                               level 5 selection : 2V7        */
+#define PWR_PVDLEVEL_6  PWR_CR1_PLS_LEV6  /*!< Programmable voltage detector
+                                               level 6 selection : 2V85       */
+#define PWR_PVDLEVEL_7  PWR_CR1_PLS_LEV7  /*!< External input analog voltage
+                                               (Compare internally to VREF)   */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_PVD_Mode PWR PVD Mode
+  * @{
+  */
+#define PWR_PVD_MODE_NORMAL               (0x00000000U) /*!< Basic mode is used                                        */
+#define PWR_PVD_MODE_IT_RISING            (0x00010001U) /*!< Interrupt Mode with Rising edge trigger detection         */
+#define PWR_PVD_MODE_IT_FALLING           (0x00010002U) /*!< Interrupt Mode with Falling edge trigger detection        */
+#define PWR_PVD_MODE_IT_RISING_FALLING    (0x00010003U) /*!< Interrupt Mode with Rising/Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING         (0x00020001U) /*!< Event Mode with Rising edge trigger detection             */
+#define PWR_PVD_MODE_EVENT_FALLING        (0x00020002U) /*!< Event Mode with Falling edge trigger detection            */
+#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection     */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
+  * @{
+  */
+#define PWR_MAINREGULATOR_ON      (0U)
+#define PWR_LOWPOWERREGULATOR_ON  PWR_CR1_LPDS
+/**
+  * @}
+  */
+
+/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
+  * @{
+  */
+#define PWR_SLEEPENTRY_WFI  (0x01U)
+#define PWR_SLEEPENTRY_WFE  (0x02U)
+/**
+  * @}
+  */
+
+/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
+  * @{
+  */
+#define PWR_STOPENTRY_WFI  (0x01U)
+#define PWR_STOPENTRY_WFE  (0x02U)
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale
+  * @{
+  */
+#if defined(PWR_SRDCR_VOS)
+#define PWR_REGULATOR_VOLTAGE_SCALE0  (PWR_SRDCR_VOS_1 | PWR_SRDCR_VOS_0)
+#define PWR_REGULATOR_VOLTAGE_SCALE1  (PWR_SRDCR_VOS_1)
+#define PWR_REGULATOR_VOLTAGE_SCALE2  (PWR_SRDCR_VOS_0)
+#define PWR_REGULATOR_VOLTAGE_SCALE3  (0U)
+#else
+#define PWR_REGULATOR_VOLTAGE_SCALE0  (0U)
+#define PWR_REGULATOR_VOLTAGE_SCALE1  (PWR_D3CR_VOS_1 | PWR_D3CR_VOS_0)
+#define PWR_REGULATOR_VOLTAGE_SCALE2  (PWR_D3CR_VOS_1)
+#define PWR_REGULATOR_VOLTAGE_SCALE3  (PWR_D3CR_VOS_0)
+#endif /* PWR_SRDCR_VOS */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Flag PWR Flag
+  * @{
+  */
+/* PWR CPU flag */
+#define PWR_FLAG_STOP       (0x01U)
+#if defined (PWR_CPUCR_SBF_D2)
+#define PWR_FLAG_SB_D1      (0x02U)
+#define PWR_FLAG_SB_D2      (0x03U)
+#endif /* defined (PWR_CPUCR_SBF_D2) */
+#define PWR_FLAG_SB         (0x04U)
+#if defined (DUAL_CORE)
+#define PWR_FLAG_CPU_HOLD   (0x05U)
+#define PWR_FLAG_CPU2_HOLD  (0x06U)
+#define PWR_FLAG2_STOP      (0x07U)
+#define PWR_FLAG2_SB_D1     (0x08U)
+#define PWR_FLAG2_SB_D2     (0x09U)
+#define PWR_FLAG2_SB        (0x0AU)
+#endif /* defined (DUAL_CORE) */
+#define PWR_FLAG_PVDO       (0x0BU)
+#define PWR_FLAG_AVDO       (0x0CU)
+#define PWR_FLAG_ACTVOSRDY  (0x0DU)
+#define PWR_FLAG_ACTVOS     (0x0EU)
+#define PWR_FLAG_BRR        (0x0FU)
+#define PWR_FLAG_VOSRDY     (0x10U)
+#if defined (SMPS)
+#define PWR_FLAG_SMPSEXTRDY (0x11U)
+#else
+#define PWR_FLAG_SCUEN      (0x11U)
+#endif /* defined (SMPS) */
+#if defined (PWR_CSR1_MMCVDO)
+#define PWR_FLAG_MMCVDO     (0x12U)
+#endif /* defined (PWR_CSR1_MMCVDO) */
+#define PWR_FLAG_USB33RDY   (0x13U)
+#define PWR_FLAG_TEMPH      (0x14U)
+#define PWR_FLAG_TEMPL      (0x15U)
+#define PWR_FLAG_VBATH      (0x16U)
+#define PWR_FLAG_VBATL      (0x17U)
+
+/* PWR Wake up flag */
+#define PWR_FLAG_WKUP1 PWR_WKUPCR_WKUPC1
+#define PWR_FLAG_WKUP2 PWR_WKUPCR_WKUPC2
+#define PWR_FLAG_WKUP3 PWR_WKUPCR_WKUPC3
+#define PWR_FLAG_WKUP4 PWR_WKUPCR_WKUPC4
+#define PWR_FLAG_WKUP5 PWR_WKUPCR_WKUPC5
+#define PWR_FLAG_WKUP6 PWR_WKUPCR_WKUPC6
+/**
+  * @}
+  */
+
+/** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask
+  * @{
+  */
+#define  PWR_EWUP_MASK  (0x0FFF3F3FU)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PWR_Exported_Macro PWR Exported Macro
+  * @{
+  */
+
+/** @brief  Configure the main internal regulator output voltage.
+  * @param  __REGULATOR__ : Specifies the regulator output voltage to achieve a
+  *                         trade-off between performance and power consumption
+  *                         when the device does not operate at the maximum
+  *                         frequency (refer to the datasheet for more details).
+  *          This parameter can be one of the following values:
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE0 : Regulator voltage output
+  *                                                Scale 0 mode.
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output
+  *                                                Scale 1 mode.
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output
+  *                                                Scale 2 mode.
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output
+  *                                                Scale 3 mode.
+  * @note   For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines,
+  *         configuring Voltage Scale 0 is only possible when Vcore is supplied
+  *         from LDO (Low DropOut). The SYSCFG Clock must be enabled through
+  *         __HAL_RCC_SYSCFG_CLK_ENABLE() macro before configuring Voltage Scale
+  *         0 using __HAL_PWR_VOLTAGESCALING_CONFIG().
+  *         Transition to Voltage Scale 0 is only possible when the system is
+  *         already in Voltage Scale 1.
+  *         Transition from Voltage Scale 0 is only possible to Voltage Scale 1
+  *         then once in Voltage Scale 1 it is possible to switch to another
+  *         voltage scale.
+  *         After each regulator voltage setting, wait on VOSRDY flag to be set
+  *         using macro __HAL_PWR_GET_FLAG().
+  *         To enter low power mode , and if current regulator voltage is
+  *         Voltage Scale 0 then first switch to Voltage Scale 1 before entering
+  *         low power mode.
+  * @retval None.
+  */
+#if defined(PWR_SRDCR_VOS) /* STM32H7Axxx and STM32H7Bxxx lines */
+#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__)                         \
+do {                                                                           \
+      __IO uint32_t tmpreg = 0x00;                                             \
+      MODIFY_REG(PWR->SRDCR, PWR_SRDCR_VOS, (__REGULATOR__));                  \
+      /* Delay after setting the voltage scaling */                            \
+      tmpreg = READ_BIT(PWR->SRDCR, PWR_SRDCR_VOS);                            \
+      UNUSED(tmpreg);                                                          \
+} while(0)
+#else /* All H7 lines except STM32H7Axxx and STM32H7Bxxx lines */
+#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__)                         \
+do {                                                                           \
+      __IO uint32_t tmpreg = 0x00;                                             \
+      /* Check the voltage scaling to be configured */                         \
+      if((__REGULATOR__) == PWR_REGULATOR_VOLTAGE_SCALE0)                      \
+      {                                                                        \
+        /* Configure the Voltage Scaling 1 */                                  \
+        MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);     \
+        /* Delay after setting the voltage scaling */                          \
+        tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS);                            \
+        /* Enable the PWR overdrive */                                         \
+        SET_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);                             \
+        /* Delay after setting the syscfg boost setting */                     \
+        tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);                   \
+      }                                                                        \
+      else                                                                     \
+      {                                                                        \
+        /* Disable the PWR overdrive */                                        \
+        CLEAR_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);                           \
+        /* Delay after setting the syscfg boost setting */                     \
+        tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);                   \
+        /* Configure the Voltage Scaling x */                                  \
+        MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__));                  \
+        /* Delay after setting the voltage scaling */                          \
+        tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS);                            \
+      }                                                                        \
+      UNUSED(tmpreg);                                                          \
+} while(0)
+#endif /* PWR_SRDCR_VOS */
+
+/** @brief  Check PWR flags are set or not.
+  * @param  __FLAG__ : Specifies the flag to check.
+  *           This parameter can be one of the following values:
+  *            @arg PWR_FLAG_PVDO : PVD Output. This flag is valid only if PVD
+  *                                 is enabled by the HAL_PWR_EnablePVD()
+  *                                 function.
+  *                                 The PVD is stopped by STANDBY mode. For this
+  *                                 reason, this bit is equal to 0 after STANDBY
+  *                                 or reset until the PVDE bit is set.
+  *            @arg PWR_FLAG_AVDO : AVD Output. This flag is valid only if AVD
+  *                                 is enabled by the HAL_PWREx_EnableAVD()
+  *                                 function. The AVD is stopped by STANDBY mode.
+  *                                 For this reason, this bit is equal to 0
+  *                                 after STANDBY or reset until the AVDE bit
+  *                                 is set.
+  *            @arg PWR_FLAG_ACTVOSRDY : This flag indicates that the Regulator
+  *                                      voltage scaling output selection is
+  *                                      ready.
+  *            @arg PWR_FLAG_BRR : Backup regulator ready flag. This bit is not
+  *                                reset when the device wakes up from STANDBY
+  *                                mode or by a system reset or power-on reset.
+  *            @arg PWR_FLAG_VOSRDY : This flag indicates that the Regulator
+  *                                   voltage scaling output selection is ready.
+  *                                mode or by a system reset or power-on reset.
+  *            @arg PWR_FLAG_USB33RDY : This flag indicates that the USB supply
+  *                                     from regulator is ready.
+  *            @arg PWR_FLAG_TEMPH : This flag indicates that the temperature
+  *                                  equal or above high threshold level.
+  *            @arg PWR_FLAG_TEMPL : This flag indicates that the temperature
+  *                                  equal or below low threshold level.
+  *            @arg PWR_FLAG_VBATH : This flag indicates that VBAT level equal
+  *                                  or above high threshold level.
+  *            @arg PWR_FLAG_VBATL : This flag indicates that VBAT level equal
+  *                                  or below low threshold level.
+  *            @arg PWR_FLAG_STOP : This flag indicates that the system entered
+  *                                 in STOP mode.
+  *            @arg PWR_FLAG_SB : This flag indicates that the system entered in
+  *                               STANDBY mode.
+  *            @arg PWR_FLAG_SB_D1 : This flag indicates that the D1 domain
+  *                                  entered in STANDBY mode.
+  *            @arg PWR_FLAG_SB_D2 : This flag indicates that the D2 domain
+  *                                  entered in STANDBY mode.
+  *            @arg PWR_FLAG2_STOP : This flag indicates that the system entered
+  *                                 in STOP mode.
+  *            @arg PWR_FLAG2_SB : This flag indicates that the system entered
+  *                                in STANDBY mode.
+  *            @arg PWR_FLAG2_SB_D1 : This flag indicates that the D1 domain
+  *                                   entered in STANDBY mode.
+  *            @arg PWR_FLAG2_SB_D2 : This flag indicates that the D2 domain
+  *                                   entered in STANDBY mode.
+  *            @arg PWR_FLAG_CPU_HOLD : This flag indicates that the CPU1 wakes
+  *                                     up with hold.
+  *            @arg PWR_FLAG_CPU2_HOLD : This flag indicates that the CPU2 wakes
+  *                                      up with hold.
+  *            @arg PWR_FLAG_SMPSEXTRDY : This flag indicates that the SMPS
+  *                                       External supply is sready.
+  *            @arg PWR_FLAG_SCUEN : This flag indicates that the supply
+  *                                  configuration update is enabled.
+  *            @arg PWR_FLAG_MMCVDO : This flag indicates that the VDDMMC is
+  *                                   above or equal to 1.2 V.
+  * @note   The PWR_FLAG_PVDO, PWR_FLAG_AVDO, PWR_FLAG_ACTVOSRDY, PWR_FLAG_BRR,
+  *         PWR_FLAG_VOSRDY, PWR_FLAG_USB33RDY, PWR_FLAG_TEMPH, PWR_FLAG_TEMPL,
+  *         PWR_FLAG_VBATH, PWR_FLAG_VBATL, PWR_FLAG_STOP and PWR_FLAG_SB flags
+  *         are used for all H7 family lines.
+  *         The PWR_FLAG2_STOP, PWR_FLAG2_SB, PWR_FLAG2_SB_D1, PWR_FLAG2_SB_D2,
+  *         PWR_FLAG_CPU_HOLD and PWR_FLAG_CPU2_HOLD flags are used only for H7
+  *         dual core lines.
+  *         The PWR_FLAG_SB_D1 and PWR_FLAG_SB_D2 flags are used for all H7
+  *         family except STM32H7Axxx and STM32H7Bxxx lines.
+  *         The PWR_FLAG_MMCVDO flag is used only for STM32H7Axxx and
+  *         STM32H7Bxxx lines.
+  *         The PWR_FLAG_SCUEN flag is used for STM32H743, STM32H753, STM32H742,
+  *         STM32H750, STM32H7Axx and STM32H7Bxx lines.
+  *         The PWR_FLAG_SMPSEXTRDY flag is used for dual core and STM32H7AxxQ,
+  *         STM32H7BxxQ lines.
+  * @retval The (__FLAG__) state (TRUE or FALSE).
+  */
+#if defined (DUAL_CORE) /* Dual core lines */
+#define __HAL_PWR_GET_FLAG(__FLAG__)                                                              \
+(((__FLAG__) == PWR_FLAG_PVDO)       ? ((PWR->CSR1 & PWR_CSR1_PVDO)       == PWR_CSR1_PVDO)      :\
+ ((__FLAG__) == PWR_FLAG_AVDO)       ? ((PWR->CSR1 & PWR_CSR1_AVDO)       == PWR_CSR1_AVDO)      :\
+ ((__FLAG__) == PWR_FLAG_ACTVOSRDY)  ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY)  == PWR_CSR1_ACTVOSRDY) :\
+ ((__FLAG__) == PWR_FLAG_VOSRDY)     ? ((PWR->D3CR & PWR_D3CR_VOSRDY)     == PWR_D3CR_VOSRDY)    :\
+ ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_CR3_SMPSEXTRDY)   == PWR_CR3_SMPSEXTRDY) :\
+ ((__FLAG__) == PWR_FLAG_BRR)        ? ((PWR->CR2 & PWR_CR2_BRRDY)        == PWR_CR2_BRRDY)      :\
+ ((__FLAG__) == PWR_FLAG_CPU_HOLD)   ? ((PWR->CPU2CR & PWR_CPU2CR_HOLD1F) == PWR_CPU2CR_HOLD1F)  :\
+ ((__FLAG__) == PWR_FLAG_CPU2_HOLD)  ? ((PWR->CPUCR & PWR_CPUCR_HOLD2F)   == PWR_CPUCR_HOLD2F)   :\
+ ((__FLAG__) == PWR_FLAG_SB)         ? ((PWR->CPUCR & PWR_CPUCR_SBF)      == PWR_CPUCR_SBF)      :\
+ ((__FLAG__) == PWR_FLAG2_SB)        ? ((PWR->CPU2CR & PWR_CPU2CR_SBF)    == PWR_CPU2CR_SBF)     :\
+ ((__FLAG__) == PWR_FLAG_STOP)       ? ((PWR->CPUCR & PWR_CPUCR_STOPF)    == PWR_CPUCR_STOPF)    :\
+ ((__FLAG__) == PWR_FLAG2_STOP)      ? ((PWR->CPU2CR & PWR_CPU2CR_STOPF)  == PWR_CPU2CR_STOPF)   :\
+ ((__FLAG__) == PWR_FLAG_SB_D1)      ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1)   == PWR_CPUCR_SBF_D1)   :\
+ ((__FLAG__) == PWR_FLAG2_SB_D1)     ? ((PWR->CPU2CR & PWR_CPU2CR_SBF_D1) == PWR_CPU2CR_SBF_D1)  :\
+ ((__FLAG__) == PWR_FLAG_SB_D2)      ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2)   == PWR_CPUCR_SBF_D2)   :\
+ ((__FLAG__) == PWR_FLAG2_SB_D2)     ? ((PWR->CPU2CR & PWR_CPU2CR_SBF_D2) == PWR_CPU2CR_SBF_D2)  :\
+ ((__FLAG__) == PWR_FLAG_USB33RDY)   ? ((PWR->CR3 & PWR_CR3_USB33RDY)     == PWR_CR3_USB33RDY)   :\
+ ((__FLAG__) == PWR_FLAG_TEMPH)      ? ((PWR->CR2 & PWR_CR2_TEMPH)        == PWR_CR2_TEMPH)      :\
+ ((__FLAG__) == PWR_FLAG_TEMPL)      ? ((PWR->CR2 & PWR_CR2_TEMPL)        == PWR_CR2_TEMPL)      :\
+ ((__FLAG__) == PWR_FLAG_VBATH)      ? ((PWR->CR2 & PWR_CR2_VBATH)        == PWR_CR2_VBATH)      :\
+ ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
+#else /* Single core lines */
+#if defined (PWR_CPUCR_SBF_D2) /* STM32H743, STM32H753, STM32H742 and STM32H750 lines */
+#define __HAL_PWR_GET_FLAG(__FLAG__)                                                            \
+(((__FLAG__) == PWR_FLAG_PVDO)      ? ((PWR->CSR1 & PWR_CSR1_PVDO)      == PWR_CSR1_PVDO)      :\
+ ((__FLAG__) == PWR_FLAG_AVDO)      ? ((PWR->CSR1 & PWR_CSR1_AVDO)      == PWR_CSR1_AVDO)      :\
+ ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
+ ((__FLAG__) == PWR_FLAG_VOSRDY)    ? ((PWR->D3CR & PWR_D3CR_VOSRDY)    == PWR_D3CR_VOSRDY)    :\
+ ((__FLAG__) == PWR_FLAG_SCUEN)     ? ((PWR->CR3 & PWR_CR3_SCUEN)       == PWR_CR3_SCUEN)      :\
+ ((__FLAG__) == PWR_FLAG_BRR)       ? ((PWR->CR2 & PWR_CR2_BRRDY)       == PWR_CR2_BRRDY)      :\
+ ((__FLAG__) == PWR_FLAG_SB)        ? ((PWR->CPUCR & PWR_CPUCR_SBF)     == PWR_CPUCR_SBF)      :\
+ ((__FLAG__) == PWR_FLAG_STOP)      ? ((PWR->CPUCR & PWR_CPUCR_STOPF)   == PWR_CPUCR_STOPF)    :\
+ ((__FLAG__) == PWR_FLAG_SB_D1)     ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1)  == PWR_CPUCR_SBF_D1)   :\
+ ((__FLAG__) == PWR_FLAG_SB_D2)     ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2)  == PWR_CPUCR_SBF_D2)   :\
+ ((__FLAG__) == PWR_FLAG_USB33RDY)  ? ((PWR->CR3 & PWR_CR3_USB33RDY)    == PWR_CR3_USB33RDY)   :\
+ ((__FLAG__) == PWR_FLAG_TEMPH)     ? ((PWR->CR2 & PWR_CR2_TEMPH)       == PWR_CR2_TEMPH)      :\
+ ((__FLAG__) == PWR_FLAG_TEMPL)     ? ((PWR->CR2 & PWR_CR2_TEMPL)       == PWR_CR2_TEMPL)      :\
+ ((__FLAG__) == PWR_FLAG_VBATH)     ? ((PWR->CR2 & PWR_CR2_VBATH)       == PWR_CR2_VBATH)      :\
+ ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
+#else /* STM32H7Axxx and STM32H7Bxxx lines */
+#if defined (SMPS) /* STM32H7AxxQ and STM32H7BxxQ SMPS lines */
+#define __HAL_PWR_GET_FLAG(__FLAG__)                                                            \
+(((__FLAG__) == PWR_FLAG_PVDO)       ? ((PWR->CSR1 & PWR_CSR1_PVDO)      == PWR_CSR1_PVDO)      :\
+ ((__FLAG__) == PWR_FLAG_AVDO)       ? ((PWR->CSR1 & PWR_CSR1_AVDO)      == PWR_CSR1_AVDO)      :\
+ ((__FLAG__) == PWR_FLAG_ACTVOSRDY)  ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
+ ((__FLAG__) == PWR_FLAG_BRR)        ? ((PWR->CR2 & PWR_CR2_BRRDY)       == PWR_CR2_BRRDY)      :\
+ ((__FLAG__) == PWR_FLAG_VOSRDY)     ? ((PWR->SRDCR & PWR_SRDCR_VOSRDY)  == PWR_SRDCR_VOSRDY)   :\
+ ((__FLAG__) == PWR_FLAG_STOP)       ? ((PWR->CPUCR & PWR_CPUCR_STOPF)   == PWR_CPUCR_STOPF)    :\
+ ((__FLAG__) == PWR_FLAG_SB)         ? ((PWR->CPUCR & PWR_CPUCR_SBF)     == PWR_CPUCR_SBF)      :\
+ ((__FLAG__) == PWR_FLAG_MMCVDO)     ? ((PWR->CSR1 & PWR_CSR1_MMCVDO)    == PWR_CSR1_MMCVDO)    :\
+ ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_CR3_SMPSEXTRDY)  == PWR_CR3_SMPSEXTRDY) :\
+ ((__FLAG__) == PWR_FLAG_USB33RDY)   ? ((PWR->CR3 & PWR_CR3_USB33RDY)    == PWR_CR3_USB33RDY)   :\
+ ((__FLAG__) == PWR_FLAG_TEMPH)      ? ((PWR->CR2 & PWR_CR2_TEMPH)       == PWR_CR2_TEMPH)      :\
+ ((__FLAG__) == PWR_FLAG_TEMPL)      ? ((PWR->CR2 & PWR_CR2_TEMPL)       == PWR_CR2_TEMPL)      :\
+ ((__FLAG__) == PWR_FLAG_VBATH)      ? ((PWR->CR2 & PWR_CR2_VBATH)       == PWR_CR2_VBATH)      :\
+ ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
+#else /* STM32H7Axx and STM32H7Bxx LDO lines */
+#define __HAL_PWR_GET_FLAG(__FLAG__)                                    \
+(((__FLAG__) == PWR_FLAG_PVDO)      ? ((PWR->CSR1 & PWR_CSR1_PVDO)      == PWR_CSR1_PVDO)      :\
+ ((__FLAG__) == PWR_FLAG_AVDO)      ? ((PWR->CSR1 & PWR_CSR1_AVDO)      == PWR_CSR1_AVDO)      :\
+ ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
+ ((__FLAG__) == PWR_FLAG_BRR)       ? ((PWR->CR2 & PWR_CR2_BRRDY)       == PWR_CR2_BRRDY)      :\
+ ((__FLAG__) == PWR_FLAG_VOSRDY)    ? ((PWR->SRDCR & PWR_SRDCR_VOSRDY)  == PWR_SRDCR_VOSRDY)   :\
+ ((__FLAG__) == PWR_FLAG_SCUEN)     ? ((PWR->CR3 & PWR_CR3_SCUEN)       == PWR_CR3_SCUEN)      :\
+ ((__FLAG__) == PWR_FLAG_STOP)      ? ((PWR->CPUCR & PWR_CPUCR_STOPF)   == PWR_CPUCR_STOPF)    :\
+ ((__FLAG__) == PWR_FLAG_SB)        ? ((PWR->CPUCR & PWR_CPUCR_SBF)     == PWR_CPUCR_SBF)      :\
+ ((__FLAG__) == PWR_FLAG_MMCVDO)    ? ((PWR->CSR1 & PWR_CSR1_MMCVDO)    == PWR_CSR1_MMCVDO)    :\
+ ((__FLAG__) == PWR_FLAG_USB33RDY)  ? ((PWR->CR3 & PWR_CR3_USB33RDY)    == PWR_CR3_USB33RDY)   :\
+ ((__FLAG__) == PWR_FLAG_TEMPH)     ? ((PWR->CR2 & PWR_CR2_TEMPH)       == PWR_CR2_TEMPH)      :\
+ ((__FLAG__) == PWR_FLAG_TEMPL)     ? ((PWR->CR2 & PWR_CR2_TEMPL)       == PWR_CR2_TEMPL)      :\
+ ((__FLAG__) == PWR_FLAG_VBATH)     ? ((PWR->CR2 & PWR_CR2_VBATH)       == PWR_CR2_VBATH)      :\
+ ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
+#endif /* SMPS */
+#endif /* PWR_CPUCR_SBF_D2 */
+#endif /* DUAL_CORE */
+
+/** @brief  Check PWR wake up flags are set or not.
+  * @param  __FLAG__: specifies the wake up flag to check.
+  *           This parameter can be one of the following values:
+  *            @arg PWR_FLAG_WKUP1 : This parameter clear Wake up line 1 flag.
+  *            @arg PWR_FLAG_WKUP2 : This parameter clear Wake up line 2 flag.
+  *            @arg PWR_FLAG_WKUP3 : This parameter clear Wake up line 3 flag.
+  *            @arg PWR_FLAG_WKUP4 : This parameter clear Wake up line 4 flag.
+  *            @arg PWR_FLAG_WKUP5 : This parameter clear Wake up line 5 flag.
+  *            @arg PWR_FLAG_WKUP6 : This parameter clear Wake up line 6 flag.
+  * @retval The (__FLAG__) state (TRUE or FALSE).
+  */
+#define __HAL_PWR_GET_WAKEUPFLAG(__FLAG__) ((PWR->WKUPFR & (__FLAG__)) ? 0 : 1)
+
+#if defined (DUAL_CORE)
+/** @brief  Clear CPU PWR flags.
+  * @param  __FLAG__ : Specifies the flag to clear.
+  * @note   This parameter is not used for the STM32H7 family and is kept as
+  *         parameter just to maintain compatibility with other families.
+  * @note   This macro clear all CPU flags STOPF, SBF, SBF_D1, and SBF_D2.
+  *           This parameter can be one of the following values :
+  *            @arg PWR_CPU_FLAGS : Clear HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2
+  *                                 CPU flags.
+  * @retval None.
+  */
+#define __HAL_PWR_CLEAR_FLAG(__FLAG__)      \
+do {                                        \
+     SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF);   \
+     SET_BIT(PWR->CPU2CR, PWR_CPU2CR_CSSF); \
+} while(0)
+#else
+/** @brief  Clear CPU PWR flags.
+  * @param  __FLAG__ : Specifies the flag to clear.
+  * @note   This parameter is not used for the STM32H7 family and is kept as
+  *         parameter just to maintain compatibility with other families.
+  * @note   This macro clear all CPU flags.
+  *         For STM32H7Axxx and STM32H7Bxxx lines CPU flags are STOPF and SBF.
+  *         For dual core lines flags are HOLDxF, STOPF, SBF and SBF_Dx.
+  * @retval None.
+  */
+#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF)
+#endif /* defined (DUAL_CORE) */
+
+/** @brief  Clear PWR wake up flags.
+  * @param  __FLAG__ : Specifies the wake up flag to be cleared.
+  *           This parameter can be one of the following values :
+  *            @arg PWR_FLAG_WKUP1 : This parameter clear Wake up line 1 flag.
+  *            @arg PWR_FLAG_WKUP2 : This parameter clear Wake up line 2 flag.
+  *            @arg PWR_FLAG_WKUP3 : This parameter clear Wake up line 3 flag.
+  *            @arg PWR_FLAG_WKUP4 : This parameter clear Wake up line 4 flag.
+  *            @arg PWR_FLAG_WKUP5 : This parameter clear Wake up line 5 flag.
+  *            @arg PWR_FLAG_WKUP6 : This parameter clear Wake up line 6 flag.
+  * @retval None.
+  */
+#define __HAL_PWR_CLEAR_WAKEUPFLAG(__FLAG__) SET_BIT(PWR->WKUPCR, (__FLAG__))
+
+/**
+  * @brief Enable the PVD EXTI Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Enable the PVD EXTI D2 Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief Disable the PVD EXTI Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Disable the PVD EXTI D2 Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief   Enable event on PVD EXTI Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Enable event on PVD EXTI D2 Line.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief   Disable event on PVD EXTI Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Disable event on PVD EXTI D2 Line.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief Enable the PVD Rising Interrupt Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Disable the PVD Rising Interrupt Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Enable the PVD Falling Interrupt Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Disable the PVD Falling Interrupt Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Enable the PVD Rising & Falling Interrupt Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
+do {                                                    \
+      __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();          \
+      __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();         \
+} while(0);
+
+/**
+  * @brief Disable the PVD Rising & Falling Interrupt Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
+do {                                                     \
+      __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();          \
+      __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();         \
+} while(0);
+
+/**
+  * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
+  * @retval EXTI PVD Line Status.
+  */
+#define __HAL_PWR_PVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Checks whether the specified PVD EXTI interrupt flag is set or not.
+  * @retval EXTI D2 PVD Line Status.
+  */
+#define __HAL_PWR_PVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief Clear the PVD EXTI flag.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Clear the PVD EXTI D2 flag.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief  Generates a Software interrupt on PVD EXTI line.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
+/**
+  * @}
+  */
+
+/* Include PWR HAL Extension module */
+#include "stm32h7xx_hal_pwr_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PWR_Exported_Functions PWR Exported Functions
+  * @{
+  */
+
+/** @addtogroup PWR_Exported_Functions_Group1 Initialization and De-Initialization functions
+  * @{
+  */
+/* Initialization and de-initialization functions *****************************/
+void HAL_PWR_DeInit(void);
+void HAL_PWR_EnableBkUpAccess(void);
+void HAL_PWR_DisableBkUpAccess(void);
+/**
+  * @}
+  */
+
+/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
+  * @{
+  */
+/* Peripheral Control functions  **********************************************/
+/* PVD configuration */
+void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
+void HAL_PWR_EnablePVD(void);
+void HAL_PWR_DisablePVD(void);
+
+/* WakeUp pins configuration */
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
+
+/* Low Power modes entry */
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
+void HAL_PWR_EnterSTANDBYMode(void);
+
+/* Power PVD IRQ Handler */
+void HAL_PWR_PVD_IRQHandler(void);
+void HAL_PWR_PVDCallback(void);
+
+/* Cortex System Control functions  *******************************************/
+void HAL_PWR_EnableSleepOnExit(void);
+void HAL_PWR_DisableSleepOnExit(void);
+void HAL_PWR_EnableSEVOnPend(void);
+void HAL_PWR_DisableSEVOnPend(void);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup PWR_Private_Constants PWR Private Constants
+  * @{
+  */
+
+/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line
+  * @{
+  */
+#define PWR_EXTI_LINE_PVD  EXTI_IMR1_IM16 /*!< External interrupt line 16
+                                               Connected to the PVD EXTI Line */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PWR_Private_Macros PWR Private Macros
+  * @{
+  */
+
+/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters
+  * @{
+  */
+/* Check PVD level parameter */
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) ||\
+                                 ((LEVEL) == PWR_PVDLEVEL_1) ||\
+                                 ((LEVEL) == PWR_PVDLEVEL_2) ||\
+                                 ((LEVEL) == PWR_PVDLEVEL_3) ||\
+                                 ((LEVEL) == PWR_PVDLEVEL_4) ||\
+                                 ((LEVEL) == PWR_PVDLEVEL_5) ||\
+                                 ((LEVEL) == PWR_PVDLEVEL_6) ||\
+                                 ((LEVEL) == PWR_PVDLEVEL_7))
+
+/* Check PVD mode parameter */
+#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)            ||\
+                               ((MODE) == PWR_PVD_MODE_IT_FALLING)           ||\
+                               ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING)    ||\
+                               ((MODE) == PWR_PVD_MODE_EVENT_RISING)         ||\
+                               ((MODE) == PWR_PVD_MODE_EVENT_FALLING)        ||\
+                               ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) ||\
+                               ((MODE) == PWR_PVD_MODE_NORMAL))
+
+/* Check low power regulator parameter */
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON)   ||\
+                                     ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
+
+/* Check low power mode entry parameter */
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) ||\
+                                   ((ENTRY) == PWR_SLEEPENTRY_WFE))
+
+/* Check low power mode entry parameter */
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) ||\
+                                  ((ENTRY) == PWR_STOPENTRY_WFE))
+
+/* Check voltage scale level parameter */
+#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE0) || \
+                                           ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
+                                           ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
+                                           ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* STM32H7xx_HAL_PWR_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h
new file mode 100644
index 00000000..ebad73c5
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h
@@ -0,0 +1,743 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_pwr_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of PWR HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_PWR_EX_H
+#define STM32H7xx_HAL_PWR_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup PWREx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup PWREx_Exported_Types PWREx Exported Types
+  * @{
+  */
+/**
+  * @brief  PWREx AVD configuration structure definition
+  */
+typedef struct
+{
+  uint32_t AVDLevel; /*!< AVDLevel : Specifies the AVD detection level. This
+                          parameter can be a value of @ref
+                          PWREx_AVD_detection_level
+                     */
+
+  uint32_t Mode;     /*!< Mode : Specifies the EXTI operating mode for the AVD
+                                 event. This parameter can be a value of @ref
+                                 PWREx_AVD_Mode.
+                     */
+}PWREx_AVDTypeDef;
+
+/**
+  * @brief  PWREx Wakeup pin configuration structure definition
+  */
+typedef struct
+{
+  uint32_t WakeUpPin;   /*!< WakeUpPin: Specifies the Wake-Up pin to be enabled.
+                                        This parameter can be a value of @ref
+                                        PWREx_WakeUp_Pins
+                        */
+
+  uint32_t PinPolarity; /*!< PinPolarity: Specifies the Wake-Up pin polarity.
+                                          This parameter can be a value of @ref
+                                          PWREx_PIN_Polarity
+                        */
+
+  uint32_t PinPull;     /*!< PinPull: Specifies the Wake-Up pin pull. This
+                                      parameter can be a value of @ref
+                                      PWREx_PIN_Pull
+                        */
+}PWREx_WakeupPinTypeDef;
+
+#if defined (PWR_CSR1_MMCVDO)
+/**
+  * @brief  PWR VDDMMC voltage level enum definition
+  */
+typedef enum
+{
+  PWR_MMC_VOLTAGE_BELOW_1V2,      /*!< VDDMMC is below 1V2          */
+  PWR_MMC_VOLTAGE_EQUAL_ABOVE_1V2 /*!< VDDMMC is above or equal 1V2 */
+} PWREx_MMC_VoltageLevel;
+#endif /* defined (PWR_CSR1_MMCVDO) */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PWREx_Exported_Constants PWREx Exported Constants
+  * @{
+  */
+/** @defgroup PWREx_WakeUp_Pins PWREx Wake-Up Pins
+  * @{
+  */
+/* High level and No pull (default configuration) */
+#define PWR_WAKEUP_PIN6      PWR_WKUPEPR_WKUPEN6
+#define PWR_WAKEUP_PIN5      PWR_WKUPEPR_WKUPEN5
+#define PWR_WAKEUP_PIN4      PWR_WKUPEPR_WKUPEN4
+#define PWR_WAKEUP_PIN3      PWR_WKUPEPR_WKUPEN3
+#define PWR_WAKEUP_PIN2      PWR_WKUPEPR_WKUPEN2
+#define PWR_WAKEUP_PIN1      PWR_WKUPEPR_WKUPEN1
+
+/* High level and No pull */
+#define PWR_WAKEUP_PIN6_HIGH PWR_WKUPEPR_WKUPEN6
+#define PWR_WAKEUP_PIN5_HIGH PWR_WKUPEPR_WKUPEN5
+#define PWR_WAKEUP_PIN4_HIGH PWR_WKUPEPR_WKUPEN4
+#define PWR_WAKEUP_PIN3_HIGH PWR_WKUPEPR_WKUPEN3
+#define PWR_WAKEUP_PIN2_HIGH PWR_WKUPEPR_WKUPEN2
+#define PWR_WAKEUP_PIN1_HIGH PWR_WKUPEPR_WKUPEN1
+
+/* Low level and No pull */
+#define PWR_WAKEUP_PIN6_LOW  (PWR_WKUPEPR_WKUPP6 | PWR_WKUPEPR_WKUPEN6)
+#define PWR_WAKEUP_PIN5_LOW  (PWR_WKUPEPR_WKUPP5 | PWR_WKUPEPR_WKUPEN5)
+#define PWR_WAKEUP_PIN4_LOW  (PWR_WKUPEPR_WKUPP4 | PWR_WKUPEPR_WKUPEN4)
+#define PWR_WAKEUP_PIN3_LOW  (PWR_WKUPEPR_WKUPP3 | PWR_WKUPEPR_WKUPEN3)
+#define PWR_WAKEUP_PIN2_LOW  (PWR_WKUPEPR_WKUPP2 | PWR_WKUPEPR_WKUPEN2)
+#define PWR_WAKEUP_PIN1_LOW  (PWR_WKUPEPR_WKUPP1 | PWR_WKUPEPR_WKUPEN1)
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_PIN_Polarity PWREx Pin Polarity configuration
+  * @{
+  */
+#define PWR_PIN_POLARITY_HIGH (0x00000000U)
+#define PWR_PIN_POLARITY_LOW  (0x00000001U)
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_PIN_Pull PWREx Pin Pull configuration
+  * @{
+  */
+#define PWR_PIN_NO_PULL   (0x00000000U)
+#define PWR_PIN_PULL_UP   (0x00000001U)
+#define PWR_PIN_PULL_DOWN (0x00000002U)
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_Wakeup_Pins_Flags PWREx Wakeup Pins Flags.
+  * @{
+  */
+#define PWR_WAKEUP_FLAG1 PWR_WKUPFR_WKUPF1 /*!< Wakeup flag on PA0  */
+#define PWR_WAKEUP_FLAG2 PWR_WKUPFR_WKUPF2 /*!< Wakeup flag on PA2  */
+#define PWR_WAKEUP_FLAG3 PWR_WKUPFR_WKUPF3 /*!< Wakeup flag on PI8  */
+#define PWR_WAKEUP_FLAG4 PWR_WKUPFR_WKUPF4 /*!< Wakeup flag on PC13 */
+#define PWR_WAKEUP_FLAG5 PWR_WKUPFR_WKUPF5 /*!< Wakeup flag on PI11 */
+#define PWR_WAKEUP_FLAG6 PWR_WKUPFR_WKUPF6 /*!< Wakeup flag on PC1  */
+#define PWR_WAKEUP_FLAG_ALL (PWR_WKUPFR_WKUPF1 | PWR_WKUPFR_WKUPF2 |\
+                             PWR_WKUPFR_WKUPF3 | PWR_WKUPFR_WKUPF4 |\
+                             PWR_WKUPFR_WKUPF5 | PWR_WKUPFR_WKUPF6)
+/**
+  * @}
+  */
+
+#if defined (DUAL_CORE)
+/** @defgroup PWREx_Core_Select PWREx Core definition
+  * @{
+  */
+#define PWR_CORE_CPU1 (0x00000000U)
+#define PWR_CORE_CPU2 (0x00000001U)
+/**
+  * @}
+  */
+#endif /* defined (DUAL_CORE) */
+
+/** @defgroup PWREx_Domains PWREx Domains definition
+  * @{
+  */
+#define PWR_D1_DOMAIN (0x00000000U)
+#if defined (PWR_CPUCR_PDDS_D2)
+#define PWR_D2_DOMAIN (0x00000001U)
+#endif /* defined (PWR_CPUCR_PDDS_D2) */
+#define PWR_D3_DOMAIN (0x00000002U)
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_Domain_Flags PWREx Domain Flags definition
+  * @{
+  */
+#if defined (DUAL_CORE)
+#define PWR_D1_DOMAIN_FLAGS  (0x00000000U)
+#define PWR_D2_DOMAIN_FLAGS  (0x00000001U)
+#define PWR_ALL_DOMAIN_FLAGS (0x00000002U)
+#else
+#define PWR_CPU_FLAGS       (0x00000000U)
+#endif /* defined (DUAL_CORE) */
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_D3_State PWREx D3 Domain State
+  * @{
+  */
+#define PWR_D3_DOMAIN_STOP (0x00000000U)
+#define PWR_D3_DOMAIN_RUN  (0x00000800U)
+
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_Supply_configuration PWREx Supply configuration
+  * @{
+  */
+#define PWR_LDO_SUPPLY                      PWR_CR3_LDOEN                                                               /*!< Core domains are suppplied from the LDO                                                                     */
+#if defined (SMPS)
+#define PWR_DIRECT_SMPS_SUPPLY              PWR_CR3_SMPSEN                                                              /*!< Core domains are suppplied from the SMPS only                                                               */
+#define PWR_SMPS_1V8_SUPPLIES_LDO           (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN    | PWR_CR3_LDOEN)                   /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains                                       */
+#define PWR_SMPS_2V5_SUPPLIES_LDO           (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN    | PWR_CR3_LDOEN)                   /*!< The SMPS 2.5V output supplies the LDO which supplies the Core domains                                       */
+#define PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO   (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)  /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */
+#define PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO   (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)  /*!< The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */
+#define PWR_SMPS_1V8_SUPPLIES_EXT           (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 1.8V output supplies an external source which supplies the Core domains                            */
+#define PWR_SMPS_2V5_SUPPLIES_EXT           (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 2.5V output supplies an external source which supplies the Core domains                            */
+#endif /* defined (SMPS) */
+#define PWR_EXTERNAL_SOURCE_SUPPLY          PWR_CR3_BYPASS                                                              /*!< The SMPS disabled and the LDO Bypass. The Core domains are supplied from an external source                 */
+
+#if defined (SMPS)
+#define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | \
+                                PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)
+#else
+#define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)
+#endif /* defined (SMPS) */
+/**
+  * @}
+  */
+
+
+/** @defgroup PWREx_AVD_detection_level PWREx AVD detection level
+  * @{
+  */
+#define PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0 /*!< Analog voltage detector level 0
+                                             selection : 1V7                 */
+#define PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1 /*!< Analog voltage detector level 1
+                                             selection : 2V1                 */
+#define PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2 /*!< Analog voltage detector level 2
+                                             selection : 2V5                 */
+#define PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3 /*!< Analog voltage detector level 3
+                                             selection : 2V8                 */
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_AVD_Mode PWREx AVD Mode
+  * @{
+  */
+#define PWR_AVD_MODE_NORMAL               (0x00000000U)   /*!< Basic mode is used                                                 */
+#define PWR_AVD_MODE_IT_RISING            (0x00010001U)   /*!< External Interrupt Mode with Rising edge trigger detection         */
+#define PWR_AVD_MODE_IT_FALLING           (0x00010002U)   /*!< External Interrupt Mode with Falling edge trigger detection        */
+#define PWR_AVD_MODE_IT_RISING_FALLING    (0x00010003U)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define PWR_AVD_MODE_EVENT_RISING         (0x00020001U)   /*!< Event Mode with Rising edge trigger detection                      */
+#define PWR_AVD_MODE_EVENT_FALLING        (0x00020002U)   /*!< Event Mode with Falling edge trigger detection                     */
+#define PWR_AVD_MODE_EVENT_RISING_FALLING (0x00020003U)   /*!< Event Mode with Rising/Falling edge trigger detection              */
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale
+  * @{
+  */
+#define PWR_REGULATOR_SVOS_SCALE5 (PWR_CR1_SVOS_0)
+#define PWR_REGULATOR_SVOS_SCALE4 (PWR_CR1_SVOS_1)
+#define PWR_REGULATOR_SVOS_SCALE3 (PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1)
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_VBAT_Battery_Charging_Resistor PWR battery charging resistor selection
+  * @{
+  */
+#define PWR_BATTERY_CHARGING_RESISTOR_5    (0x00000000U) /*!< VBAT charging through a 5 kOhms resistor   */
+#define PWR_BATTERY_CHARGING_RESISTOR_1_5  PWR_CR3_VBRS  /*!< VBAT charging through a 1.5 kOhms resistor */
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_VBAT_Thresholds PWREx VBAT Thresholds
+  * @{
+  */
+#define PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD  (0x00000000U)
+#define PWR_VBAT_BELOW_LOW_THRESHOLD         PWR_CR2_VBATL
+#define PWR_VBAT_ABOVE_HIGH_THRESHOLD        PWR_CR2_VBATH
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_TEMP_Thresholds PWREx Temperature Thresholds
+  * @{
+  */
+#define PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD  (0x00000000U)
+#define PWR_TEMP_BELOW_LOW_THRESHOLD         PWR_CR2_TEMPL
+#define PWR_TEMP_ABOVE_HIGH_THRESHOLD        PWR_CR2_TEMPH
+/**
+  * @}
+  */
+/** @defgroup PWREx_AVD_EXTI_Line PWREx AVD EXTI Line 16
+  * @{
+  */
+#define PWR_EXTI_LINE_AVD EXTI_IMR1_IM16 /*!< External interrupt line 16
+                                              Connected to the AVD EXTI Line */
+/**
+  * @}
+  */
+
+#if defined (PWR_CR1_SRDRAMSO)
+/** @defgroup PWREx_Memory_Shut_Off Memory shut-off block selection
+  * @{
+  */
+#define PWR_SRD_AHB_MEMORY_BLOCK        PWR_CR1_SRDRAMSO    /*!< SmartRun domain AHB memory shut-off in DStop/DStop2 low-power mode         */
+#define PWR_USB_FDCAN_MEMORY_BLOCK      PWR_CR1_HSITFSO     /*!< High-speed interfaces USB and FDCAN memories shut-off in DStop/DStop2 mode */
+#define PWR_GFXMMU_JPEG_MEMORY_BLOCK    PWR_CR1_GFXSO       /*!< GFXMMU and JPEG memories shut-off in DStop/DStop2 mode                     */
+#define PWR_TCM_ECM_MEMORY_BLOCK        PWR_CR1_ITCMSO      /*!< Instruction TCM and ETM memories shut-off in DStop/DStop2 mode             */
+#define PWR_RAM1_AHB_MEMORY_BLOCK       PWR_CR1_AHBRAM1SO   /*!< AHB RAM1 shut-off in DStop/DStop2 mode                                     */
+#define PWR_RAM2_AHB_MEMORY_BLOCK       PWR_CR1_AHBRAM2SO   /*!< AHB RAM2 shut-off in DStop/DStop2 mode                                     */
+#define PWR_RAM1_AXI_MEMORY_BLOCK       PWR_CR1_AXIRAM1SO   /*!< AXI RAM1 shut-off in DStop/DStop2 mode                                     */
+#define PWR_RAM2_AXI_MEMORY_BLOCK       PWR_CR1_AXIRAM2SO   /*!< AXI RAM2 shut-off in DStop/DStop2 mode                                     */
+#define PWR_RAM3_AXI_MEMORY_BLOCK       PWR_CR1_AXIRAM3SO   /*!< AXI RAM3 shut-off in DStop/DStop2 mode                                     */
+#define PWR_MEMORY_BLOCK_KEEP_ON        0U                  /*!< Memory content is kept in DStop or DStop2 mode                             */
+#define PWR_MEMORY_BLOCK_SHUT_OFF       1U                  /*!< Memory content is lost in DStop or DStop2 mode                             */
+/**
+  * @}
+  */
+#endif /* defined (PWR_CR1_SRDRAMSO) */
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup PWREx_Exported_Macro PWREx Exported Macro
+  *  @{
+  */
+
+/**
+  * @brief Enable the AVD EXTI Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Enable the AVD EXTI D2 Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief Disable the AVD EXTI Line 16
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Disable the AVD EXTI D2 Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief Enable event on AVD EXTI Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Enable event on AVD EXTI D2 Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief Disable event on AVD EXTI Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Disable event on AVD EXTI D2 Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief Enable the AVD Extended Interrupt Rising Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)
+
+/**
+  * @brief Disable the AVD Extended Interrupt Rising Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)
+
+/**
+  * @brief Enable the AVD Extended Interrupt Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)
+
+/**
+  * @brief Disable the AVD Extended Interrupt Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)
+
+/**
+  * @brief Enable the AVD Extended Interrupt Rising and Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
+do {                                                    \
+     __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE();           \
+     __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE();          \
+} while(0);
+
+/**
+  * @brief Disable the AVD Extended Interrupt Rising & Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
+do {                                                     \
+     __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE();           \
+     __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE();          \
+} while(0);
+
+/**
+  * @brief Check whether the specified AVD EXTI interrupt flag is set or not.
+  * @retval EXTI AVD Line Status.
+  */
+#define __HAL_PWR_AVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? 1UL : 0UL)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Check whether the specified AVD EXTI D2 interrupt flag is set or not.
+  * @retval EXTI D2 AVD Line Status.
+  */
+#define __HAL_PWR_AVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? 1UL : 0UL)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief  Clear the AVD EXTI flag.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Clear the AVD EXTI D2 flag.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief  Generates a Software interrupt on AVD EXTI line.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_AVD)
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions
+  * @{
+  */
+
+/** @addtogroup PWREx_Exported_Functions_Group1 Power Supply Control Functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource);
+uint32_t HAL_PWREx_GetSupplyConfig(void);
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
+uint32_t HAL_PWREx_GetVoltageRange(void);
+HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling(uint32_t VoltageScaling);
+uint32_t HAL_PWREx_GetStopModeVoltageRange(void);
+/**
+  * @}
+  */
+
+/** @addtogroup PWREx_Exported_Functions_Group2 Low Power Control Functions
+  * @{
+  */
+/* System low power control functions */
+#if defined (PWR_CPUCR_RETDS_CD)
+void HAL_PWREx_EnterSTOP2Mode(uint32_t Regulator, uint8_t STOPEntry);
+#endif /* defined (PWR_CPUCR_RETDS_CD) */
+void HAL_PWREx_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain);
+void HAL_PWREx_EnterSTANDBYMode(uint32_t Domain);
+void HAL_PWREx_ConfigD3Domain(uint32_t D3State);
+/* Clear Cortex-Mx pending flag */
+void HAL_PWREx_ClearPendingEvent(void);
+#if defined (DUAL_CORE)
+/* Clear domain flags */
+void HAL_PWREx_ClearDomainFlags(uint32_t DomainFlags);
+/* Core Hold/Release functions */
+HAL_StatusTypeDef HAL_PWREx_HoldCore(uint32_t CPU);
+void HAL_PWREx_ReleaseCore(uint32_t CPU);
+#endif /* defined (DUAL_CORE) */
+/* Flash low power control functions */
+void HAL_PWREx_EnableFlashPowerDown(void);
+void HAL_PWREx_DisableFlashPowerDown(void);
+#if defined (PWR_CR1_SRDRAMSO)
+/* Memory shut-off functions */
+void HAL_PWREx_EnableMemoryShutOff(uint32_t MemoryBlock);
+void HAL_PWREx_DisableMemoryShutOff(uint32_t MemoryBlock);
+#endif /* defined(PWR_CR1_SRDRAMSO) */
+/* Wakeup Pins control functions */
+void HAL_PWREx_EnableWakeUpPin(PWREx_WakeupPinTypeDef *sPinParams);
+void HAL_PWREx_DisableWakeUpPin(uint32_t WakeUpPin);
+uint32_t HAL_PWREx_GetWakeupFlag(uint32_t WakeUpFlag);
+HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag(uint32_t WakeUpFlag);
+/* Power Wakeup PIN IRQ Handler */
+void HAL_PWREx_WAKEUP_PIN_IRQHandler(void);
+void HAL_PWREx_WKUP1_Callback(void);
+void HAL_PWREx_WKUP2_Callback(void);
+void HAL_PWREx_WKUP3_Callback(void);
+void HAL_PWREx_WKUP4_Callback(void);
+void HAL_PWREx_WKUP5_Callback(void);
+void HAL_PWREx_WKUP6_Callback(void);
+/**
+  * @}
+  */
+
+/** @addtogroup PWREx_Exported_Functions_Group3 Peripherals Control Functions
+  * @{
+  */
+/* Backup regulator control functions */
+HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);
+HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void);
+/* USB regulator control functions */
+HAL_StatusTypeDef HAL_PWREx_EnableUSBReg(void);
+HAL_StatusTypeDef HAL_PWREx_DisableUSBReg(void);
+void HAL_PWREx_EnableUSBVoltageDetector(void);
+void HAL_PWREx_DisableUSBVoltageDetector(void);
+/* Battery control functions */
+void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorValue);
+void HAL_PWREx_DisableBatteryCharging(void);
+#if defined(PWR_CR1_BOOSTE)
+/* Analog Booster functions */
+void HAL_PWREx_EnableAnalogBooster(void);
+void HAL_PWREx_DisableAnalogBooster(void);
+#endif /* PWR_CR1_BOOSTE */
+/**
+  * @}
+  */
+
+/** @addtogroup PWREx_Exported_Functions_Group4 Power Monitoring functions
+  * @{
+  */
+/* Power VBAT/Temperature monitoring functions */
+void HAL_PWREx_EnableMonitoring(void);
+void HAL_PWREx_DisableMonitoring(void);
+uint32_t HAL_PWREx_GetTemperatureLevel(void);
+uint32_t HAL_PWREx_GetVBATLevel(void);
+#if defined(PWR_CSR1_MMCVDO)
+PWREx_MMC_VoltageLevel HAL_PWREx_GetMMCVoltage(void);
+#endif /* PWR_CSR1_MMCVDO */
+/* Power AVD configuration functions */
+void HAL_PWREx_ConfigAVD(PWREx_AVDTypeDef *sConfigAVD);
+void HAL_PWREx_EnableAVD(void);
+void HAL_PWREx_DisableAVD(void);
+/* Power PVD/AVD IRQ Handler */
+void HAL_PWREx_PVD_AVD_IRQHandler(void);
+void HAL_PWREx_AVDCallback(void);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PWREx_Private_Macros PWREx Private Macros
+  * @{
+  */
+
+/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters
+  * @{
+  */
+/* Check PWR regulator configuration parameter */
+#if defined (SMPS)
+#define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY)                    ||\
+                                   ((PWR_SOURCE) == PWR_DIRECT_SMPS_SUPPLY)            ||\
+                                   ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_LDO)         ||\
+                                   ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_LDO)         ||\
+                                   ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) ||\
+                                   ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) ||\
+                                   ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT)         ||\
+                                   ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT)         ||\
+                                   ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY))
+
+#else
+#define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) ||\
+                                   ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY))
+#endif /* defined (SMPS) */
+
+/* Check PWR regulator configuration in STOP mode parameter */
+#define IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE3)  ||\
+                                                     ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE4)  ||\
+                                                     ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE5))
+
+/* Check PWR domain parameter */
+#if defined (PWR_CPUCR_PDDS_D2)
+#define IS_PWR_DOMAIN(DOMAIN) (((DOMAIN) == PWR_D1_DOMAIN) ||\
+                               ((DOMAIN) == PWR_D2_DOMAIN) ||\
+                               ((DOMAIN) == PWR_D3_DOMAIN))
+#else
+#define IS_PWR_DOMAIN(DOMAIN) (((DOMAIN) == PWR_D1_DOMAIN) ||\
+                               ((DOMAIN) == PWR_D3_DOMAIN))
+#endif /* defined (PWR_CPUCR_PDDS_D2) */
+
+/* Check D3/SRD domain state parameter */
+#define IS_D3_STATE(STATE) (((STATE) == PWR_D3_DOMAIN_STOP) ||\
+                            ((STATE) == PWR_D3_DOMAIN_RUN))
+
+/* Check wake up pin parameter */
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1)      ||\
+                                ((PIN) == PWR_WAKEUP_PIN2)      ||\
+                                ((PIN) == PWR_WAKEUP_PIN3)      ||\
+                                ((PIN) == PWR_WAKEUP_PIN4)      ||\
+                                ((PIN) == PWR_WAKEUP_PIN5)      ||\
+                                ((PIN) == PWR_WAKEUP_PIN6)      ||\
+                                ((PIN) == PWR_WAKEUP_PIN1_HIGH) ||\
+                                ((PIN) == PWR_WAKEUP_PIN2_HIGH) ||\
+                                ((PIN) == PWR_WAKEUP_PIN3_HIGH) ||\
+                                ((PIN) == PWR_WAKEUP_PIN4_HIGH) ||\
+                                ((PIN) == PWR_WAKEUP_PIN5_HIGH) ||\
+                                ((PIN) == PWR_WAKEUP_PIN6_HIGH) ||\
+                                ((PIN) == PWR_WAKEUP_PIN1_LOW)  ||\
+                                ((PIN) == PWR_WAKEUP_PIN2_LOW)  ||\
+                                ((PIN) == PWR_WAKEUP_PIN3_LOW)  ||\
+                                ((PIN) == PWR_WAKEUP_PIN4_LOW)  ||\
+                                ((PIN) == PWR_WAKEUP_PIN5_LOW)  ||\
+                                ((PIN) == PWR_WAKEUP_PIN6_LOW))
+
+/* Check wake up pin polarity parameter */
+#define IS_PWR_WAKEUP_PIN_POLARITY(POLARITY) (((POLARITY) == PWR_PIN_POLARITY_HIGH) ||\
+                                              ((POLARITY) == PWR_PIN_POLARITY_LOW))
+
+/* Check wake up pin pull configuration parameter */
+#define IS_PWR_WAKEUP_PIN_PULL(PULL) (((PULL) == PWR_PIN_NO_PULL) ||\
+                                      ((PULL) == PWR_PIN_PULL_UP) ||\
+                                      ((PULL) == PWR_PIN_PULL_DOWN))
+
+/* Check wake up flag parameter */
+#define IS_PWR_WAKEUP_FLAG(FLAG) (((FLAG) == PWR_WAKEUP_FLAG1) ||\
+                                  ((FLAG) == PWR_WAKEUP_FLAG2) ||\
+                                  ((FLAG) == PWR_WAKEUP_FLAG3) ||\
+                                  ((FLAG) == PWR_WAKEUP_FLAG4) ||\
+                                  ((FLAG) == PWR_WAKEUP_FLAG5) ||\
+                                  ((FLAG) == PWR_WAKEUP_FLAG6) ||\
+                                  ((FLAG) == PWR_WAKEUP_FLAG_ALL))
+
+/* Check wake up flag parameter */
+#define IS_PWR_AVD_LEVEL(LEVEL) (((LEVEL) == PWR_AVDLEVEL_0) ||\
+                                 ((LEVEL) == PWR_AVDLEVEL_1) ||\
+                                 ((LEVEL) == PWR_AVDLEVEL_2) ||\
+                                 ((LEVEL) == PWR_AVDLEVEL_3))
+
+/* Check AVD mode parameter */
+#define IS_PWR_AVD_MODE(MODE) (((MODE) == PWR_AVD_MODE_IT_RISING)         ||\
+                               ((MODE) == PWR_AVD_MODE_IT_FALLING)        ||\
+                               ((MODE) == PWR_AVD_MODE_IT_RISING_FALLING) ||\
+                               ((MODE) == PWR_AVD_MODE_EVENT_RISING)      ||\
+                               ((MODE) == PWR_AVD_MODE_EVENT_FALLING)     ||\
+                               ((MODE) == PWR_AVD_MODE_NORMAL)            ||\
+                               ((MODE) == PWR_AVD_MODE_EVENT_RISING_FALLING))
+
+/* Check resistor battery parameter */
+#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
+                                                  ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
+/* Check D1/CD CPU ID parameter */
+#define IS_PWR_D1_CPU(CPU) ((CPU) == CM7_CPUID)
+
+#if defined (DUAL_CORE)
+/* Check CPU parameter */
+#define IS_PWR_CORE(CPU)  (((CPU) == PWR_CORE_CPU1) || ((CPU) == PWR_CORE_CPU2))
+
+/* Check D2 CPU ID parameter */
+#define IS_PWR_D2_CPU(CPU) ((CPU) == CM4_CPUID)
+
+/* Check PWR domain flag parameter */
+#define IS_PWR_DOMAIN_FLAG(FLAG)  (((FLAG) == PWR_D1_DOMAIN_FLAGS) || \
+                                   ((FLAG) == PWR_D2_DOMAIN_FLAGS) || \
+                                   ((FLAG) == PWR_ALL_DOMAIN_FLAGS))
+#endif /* defined (DUAL_CORE) */
+
+#if defined (PWR_CR1_SRDRAMSO)
+/* Check memory block parameter */
+#define IS_PWR_MEMORY_BLOCK(BLOCK) (((BLOCK) == PWR_SRD_AHB_MEMORY_BLOCK)     || \
+                                    ((BLOCK) == PWR_USB_FDCAN_MEMORY_BLOCK)   || \
+                                    ((BLOCK) == PWR_GFXMMU_JPEG_MEMORY_BLOCK) || \
+                                    ((BLOCK) == PWR_TCM_ECM_MEMORY_BLOCK)     || \
+                                    ((BLOCK) == PWR_RAM1_AHB_MEMORY_BLOCK)    || \
+                                    ((BLOCK) == PWR_RAM2_AHB_MEMORY_BLOCK)    || \
+                                    ((BLOCK) == PWR_RAM1_AXI_MEMORY_BLOCK)    || \
+                                    ((BLOCK) == PWR_RAM2_AXI_MEMORY_BLOCK)    || \
+                                    ((BLOCK) == PWR_RAM3_AXI_MEMORY_BLOCK))
+#endif /* defined (PWR_CR1_SRDRAMSO) */
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* STM32H7xx_HAL_PWR_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h
new file mode 100644
index 00000000..ceb86440
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h
@@ -0,0 +1,7973 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_rcc.h
+  * @author  MCD Application Team
+  * @brief   Header file of RCC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_RCC_H
+#define STM32H7xx_HAL_RCC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup RCC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Types RCC Exported Types
+  * @{
+  */
+
+/**
+  * @brief  RCC PLL configuration structure definition
+  */
+typedef struct
+{
+  uint32_t PLLState;   /*!< The new state of the PLL.
+                            This parameter can be a value of @ref RCC_PLL_Config                      */
+
+  uint32_t PLLSource;  /*!< RCC_PLLSource: PLL entry clock source.
+                            This parameter must be a value of @ref RCC_PLL_Clock_Source               */
+
+  uint32_t PLLM;       /*!< PLLM: Division factor for PLL VCO input clock.
+                            This parameter must be a number between Min_Data = 1 and Max_Data = 63    */
+
+  uint32_t PLLN;       /*!< PLLN: Multiplication factor for PLL VCO output clock.
+                            This parameter must be a number between Min_Data = 4 and Max_Data = 512 
+                            or between Min_Data = 8 and Max_Data = 420(*)
+                            (*) : For stm32h7a3xx and stm32h7b3xx family lines.                       */                        
+
+  uint32_t PLLP;       /*!< PLLP: Division factor for system clock.
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 128
+                          odd division factors are not allowed                                        */
+
+  uint32_t PLLQ;       /*!< PLLQ: Division factor for peripheral clocks.
+                            This parameter must be a number between Min_Data = 1 and Max_Data = 128   */
+
+  uint32_t PLLR;       /*!< PLLR: Division factor for peripheral clocks.
+                            This parameter must be a number between Min_Data = 1 and Max_Data = 128   */
+  uint32_t PLLRGE;     /*!<PLLRGE: PLL1 clock Input range
+                         This parameter must be a value of @ref RCC_PLL1_VCI_Range                    */
+  uint32_t PLLVCOSEL;  /*!<PLLVCOSEL: PLL1 clock Output range
+                         This parameter must be a value of @ref RCC_PLL1_VCO_Range                    */
+
+  uint32_t PLLFRACN;   /*!<PLLFRACN: Specifies Fractional Part Of The Multiplication Factor for
+                        PLL1 VCO It should be a value between 0 and 8191                              */
+
+}RCC_PLLInitTypeDef;
+
+/**
+  * @brief  RCC Internal/External Oscillator (HSE, HSI, CSI, LSE and LSI) configuration structure definition
+  */
+typedef struct
+{
+  uint32_t OscillatorType;       /*!< The oscillators to be configured.
+                                      This parameter can be a value of @ref RCC_Oscillator_Type                   */
+
+  uint32_t HSEState;             /*!< The new state of the HSE.
+                                      This parameter can be a value of @ref RCC_HSE_Config                        */
+
+  uint32_t LSEState;             /*!< The new state of the LSE.
+                                      This parameter can be a value of @ref RCC_LSE_Config                        */
+
+  uint32_t HSIState;             /*!< The new state of the HSI.
+                                      This parameter can be a value of @ref RCC_HSI_Config                        */
+
+  uint32_t HSICalibrationValue;  /*!< The calibration trimming value.
+                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F for STM32H7 rev.Y
+                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F for STM32H7 rev.B and above */
+
+  uint32_t LSIState;             /*!< The new state of the LSI.
+                                      This parameter can be a value of @ref RCC_LSI_Config                        */
+
+ uint32_t HSI48State;            /*!< The new state of the HSI48.
+                                      This parameter can be a value of @ref RCC_HSI48_Config                      */
+
+  uint32_t CSIState;             /*!< The new state of the CSI.
+                                      This parameter can be a value of @ref RCC_CSI_Config */
+
+  uint32_t CSICalibrationValue;  /*!< The calibration trimming value.
+                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F for STM32H7 rev.Y
+                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F for STM32H7 rev.B and above */
+
+  RCC_PLLInitTypeDef PLL;        /*!< PLL structure parameters                                                    */
+
+}RCC_OscInitTypeDef;
+
+/**
+  * @brief  RCC System, AHB and APB busses clock configuration structure definition
+  */
+typedef struct
+{
+  uint32_t ClockType;             /*!< The clock to be configured.
+                                       This parameter can be a value of @ref RCC_System_Clock_Type                          */
+
+  uint32_t SYSCLKSource;          /*!< The clock source (SYSCLKS) used as system clock.
+                                       This parameter can be a value of @ref RCC_System_Clock_Source                        */
+
+  uint32_t SYSCLKDivider;         /*!< The system clock  divider. This parameter can be
+                                       a value of @ref RCC_SYS_Clock_Source                                                 */
+
+  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
+                                       This parameter can be a value of @ref RCC_HCLK_Clock_Source                          */
+
+  uint32_t APB3CLKDivider;        /*!< The APB3 clock (D1PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_APB3_Clock_Source                        */
+
+  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_APB1_Clock_Source                        */
+  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_APB2_Clock_Source                        */
+  uint32_t APB4CLKDivider;      /*!< The APB4 clock (D3PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_APB4_Clock_Source                        */
+}RCC_ClkInitTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Constants RCC Exported Constants
+  * @{
+  */
+
+/** @defgroup RCC_Oscillator_Type  RCC Oscillator Type
+  * @{
+  */
+#define RCC_OSCILLATORTYPE_NONE        (0x00000000U)
+#define RCC_OSCILLATORTYPE_HSE         (0x00000001U)
+#define RCC_OSCILLATORTYPE_HSI         (0x00000002U)
+#define RCC_OSCILLATORTYPE_LSE         (0x00000004U)
+#define RCC_OSCILLATORTYPE_LSI         (0x00000008U)
+#define RCC_OSCILLATORTYPE_CSI         (0x00000010U)
+#define RCC_OSCILLATORTYPE_HSI48       (0x00000020U)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_HSE_Config  RCC HSE Config
+  * @{
+  */
+#define RCC_HSE_OFF                    (0x00000000U)
+#define RCC_HSE_ON                     RCC_CR_HSEON
+#define RCC_HSE_BYPASS                 ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
+#if defined(RCC_CR_HSEEXT)
+#define RCC_HSE_BYPASS_DIGITAL         ((uint32_t)(RCC_CR_HSEEXT | RCC_CR_HSEBYP | RCC_CR_HSEON))
+#endif /* RCC_CR_HSEEXT */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LSE_Config  RCC LSE Config
+  * @{
+  */
+#define RCC_LSE_OFF                    (0x00000000U)
+#define RCC_LSE_ON                     RCC_BDCR_LSEON
+#define RCC_LSE_BYPASS                 ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
+#if defined(RCC_BDCR_LSEEXT)
+#define RCC_LSE_BYPASS_DIGITAL         ((uint32_t)(RCC_BDCR_LSEEXT | RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
+#endif /* RCC_BDCR_LSEEXT */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_HSI_Config  RCC HSI Config
+  * @{
+  */
+#define RCC_HSI_OFF                      (0x00000000U)           /*!< HSI clock deactivation */
+#define RCC_HSI_ON                       RCC_CR_HSION                     /*!< HSI clock activation */
+
+#define RCC_HSI_DIV1                     (RCC_CR_HSIDIV_1 | RCC_CR_HSION) /*!< HSI_DIV1 clock activation */
+#define RCC_HSI_DIV2                     (RCC_CR_HSIDIV_2 | RCC_CR_HSION) /*!< HSI_DIV2 clock activation */
+#define RCC_HSI_DIV4                     (RCC_CR_HSIDIV_4 | RCC_CR_HSION) /*!< HSI_DIV4 clock activation */
+#define RCC_HSI_DIV8                     (RCC_CR_HSIDIV | RCC_CR_HSION)   /*!< HSI_DIV8 clock activation */
+
+
+#if defined(RCC_HSICFGR_HSITRIM_6)
+#define RCC_HSICALIBRATION_DEFAULT     (0x40U)         /* Default HSI calibration trimming value, for STM32H7 rev.V and above  */
+#else
+#define RCC_HSICALIBRATION_DEFAULT     (0x20U)         /* Default HSI calibration trimming value, for STM32H7 rev.Y */
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup RCC_HSI48_Config  RCC HSI48 Config
+  * @{
+  */
+#define RCC_HSI48_OFF                      ((uint8_t)0x00)
+#define RCC_HSI48_ON                       ((uint8_t)0x01)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LSI_Config  RCC LSI Config
+  * @{
+  */
+#define RCC_LSI_OFF                    (0x00000000U)
+#define RCC_LSI_ON                     RCC_CSR_LSION
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_CSI_Config  RCC CSI Config
+  * @{
+  */
+#define RCC_CSI_OFF                    (0x00000000U)
+#define RCC_CSI_ON                     RCC_CR_CSION
+
+#if defined(RCC_CSICFGR_CSITRIM_5)
+#define RCC_CSICALIBRATION_DEFAULT     (0x20U)         /* Default CSI calibration trimming value */
+#else
+#define RCC_CSICALIBRATION_DEFAULT     (0x10U)         /* Default CSI calibration trimming value */
+#endif /* RCC_CSICFGR_CSITRIM_5 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLL_Config  RCC PLL Config
+  * @{
+  */
+#define RCC_PLL_NONE                   (0x00000000U)
+#define RCC_PLL_OFF                    (0x00000001U)
+#define RCC_PLL_ON                     (0x00000002U)
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_PLL_Clock_Source  RCC PLL Clock Source
+  * @{
+  */
+#define RCC_PLLSOURCE_HSI              (0x00000000U)
+#define RCC_PLLSOURCE_CSI              (0x00000001U)
+#define RCC_PLLSOURCE_HSE              (0x00000002U)
+#define RCC_PLLSOURCE_NONE             (0x00000003U)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLL_Clock_Output  RCC PLL Clock Output
+  * @{
+  */
+#define RCC_PLL1_DIVP                RCC_PLLCFGR_DIVP1EN
+#define RCC_PLL1_DIVQ                RCC_PLLCFGR_DIVQ1EN
+#define RCC_PLL1_DIVR                RCC_PLLCFGR_DIVR1EN
+
+/**
+  * @}
+  */
+
+
+
+/** @defgroup RCC_PLL1_VCI_Range  RCC PLL1 VCI Range
+  * @{
+  */
+#define RCC_PLL1VCIRANGE_0                RCC_PLLCFGR_PLL1RGE_0       /*!< Clock range frequency between 1 and 2 MHz  */
+#define RCC_PLL1VCIRANGE_1                RCC_PLLCFGR_PLL1RGE_1       /*!< Clock range frequency between 2 and 4 MHz  */
+#define RCC_PLL1VCIRANGE_2                RCC_PLLCFGR_PLL1RGE_2       /*!< Clock range frequency between 4 and 8 MHz  */
+#define RCC_PLL1VCIRANGE_3                RCC_PLLCFGR_PLL1RGE_3       /*!< Clock range frequency between 8 and 16 MHz */
+
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_PLL1_VCO_Range  RCC PLL1 VCO Range
+  * @{
+  */
+#define RCC_PLL1VCOWIDE                 (0x00000000U)
+#define RCC_PLL1VCOMEDIUM               RCC_PLLCFGR_PLL1VCOSEL
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_System_Clock_Type  RCC System Clock Type
+  * @{
+  */
+#define RCC_CLOCKTYPE_SYSCLK           (0x00000001U)
+#define RCC_CLOCKTYPE_HCLK             (0x00000002U)
+#define RCC_CLOCKTYPE_D1PCLK1          (0x00000004U)
+#define RCC_CLOCKTYPE_PCLK1            (0x00000008U)
+#define RCC_CLOCKTYPE_PCLK2            (0x00000010U)
+#define RCC_CLOCKTYPE_D3PCLK1          (0x00000020U)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_System_Clock_Source  RCC System Clock Source
+  * @{
+  */
+#define RCC_SYSCLKSOURCE_CSI           RCC_CFGR_SW_CSI
+#define RCC_SYSCLKSOURCE_HSI           RCC_CFGR_SW_HSI
+#define RCC_SYSCLKSOURCE_HSE           RCC_CFGR_SW_HSE
+#define RCC_SYSCLKSOURCE_PLLCLK        RCC_CFGR_SW_PLL1
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
+  * @{
+  */
+#define RCC_SYSCLKSOURCE_STATUS_CSI    RCC_CFGR_SWS_CSI   /*!< CSI used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL1  /*!< PLL1 used as system clock */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_SYS_Clock_Source  RCC SYS Clock Source
+  * @{
+  */
+#if defined(RCC_D1CFGR_D1CPRE_DIV1)
+#define RCC_SYSCLK_DIV1                RCC_D1CFGR_D1CPRE_DIV1
+#define RCC_SYSCLK_DIV2                RCC_D1CFGR_D1CPRE_DIV2
+#define RCC_SYSCLK_DIV4                RCC_D1CFGR_D1CPRE_DIV4
+#define RCC_SYSCLK_DIV8                RCC_D1CFGR_D1CPRE_DIV8
+#define RCC_SYSCLK_DIV16               RCC_D1CFGR_D1CPRE_DIV16
+#define RCC_SYSCLK_DIV64               RCC_D1CFGR_D1CPRE_DIV64
+#define RCC_SYSCLK_DIV128              RCC_D1CFGR_D1CPRE_DIV128
+#define RCC_SYSCLK_DIV256              RCC_D1CFGR_D1CPRE_DIV256
+#define RCC_SYSCLK_DIV512              RCC_D1CFGR_D1CPRE_DIV512
+#else
+#define RCC_SYSCLK_DIV1                RCC_CDCFGR1_CDCPRE_DIV1
+#define RCC_SYSCLK_DIV2                RCC_CDCFGR1_CDCPRE_DIV2
+#define RCC_SYSCLK_DIV4                RCC_CDCFGR1_CDCPRE_DIV4
+#define RCC_SYSCLK_DIV8                RCC_CDCFGR1_CDCPRE_DIV8
+#define RCC_SYSCLK_DIV16               RCC_CDCFGR1_CDCPRE_DIV16
+#define RCC_SYSCLK_DIV64               RCC_CDCFGR1_CDCPRE_DIV64
+#define RCC_SYSCLK_DIV128              RCC_CDCFGR1_CDCPRE_DIV128
+#define RCC_SYSCLK_DIV256              RCC_CDCFGR1_CDCPRE_DIV256
+#define RCC_SYSCLK_DIV512              RCC_CDCFGR1_CDCPRE_DIV512
+#endif
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_HCLK_Clock_Source  RCC HCLK Clock Source
+  * @{
+  */
+#if defined(RCC_D1CFGR_HPRE_DIV1)
+#define RCC_HCLK_DIV1                RCC_D1CFGR_HPRE_DIV1
+#define RCC_HCLK_DIV2                RCC_D1CFGR_HPRE_DIV2
+#define RCC_HCLK_DIV4                RCC_D1CFGR_HPRE_DIV4
+#define RCC_HCLK_DIV8                RCC_D1CFGR_HPRE_DIV8
+#define RCC_HCLK_DIV16               RCC_D1CFGR_HPRE_DIV16
+#define RCC_HCLK_DIV64               RCC_D1CFGR_HPRE_DIV64
+#define RCC_HCLK_DIV128              RCC_D1CFGR_HPRE_DIV128
+#define RCC_HCLK_DIV256              RCC_D1CFGR_HPRE_DIV256
+#define RCC_HCLK_DIV512              RCC_D1CFGR_HPRE_DIV512
+#else
+#define RCC_HCLK_DIV1                RCC_CDCFGR1_HPRE_DIV1
+#define RCC_HCLK_DIV2                RCC_CDCFGR1_HPRE_DIV2
+#define RCC_HCLK_DIV4                RCC_CDCFGR1_HPRE_DIV4
+#define RCC_HCLK_DIV8                RCC_CDCFGR1_HPRE_DIV8
+#define RCC_HCLK_DIV16               RCC_CDCFGR1_HPRE_DIV16
+#define RCC_HCLK_DIV64               RCC_CDCFGR1_HPRE_DIV64
+#define RCC_HCLK_DIV128              RCC_CDCFGR1_HPRE_DIV128
+#define RCC_HCLK_DIV256              RCC_CDCFGR1_HPRE_DIV256
+#define RCC_HCLK_DIV512              RCC_CDCFGR1_HPRE_DIV512
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB3_Clock_Source  RCC APB3 Clock Source
+  * @{
+  */
+#if defined (RCC_D1CFGR_D1PPRE_DIV1)
+#define RCC_APB3_DIV1                  RCC_D1CFGR_D1PPRE_DIV1
+#define RCC_APB3_DIV2                  RCC_D1CFGR_D1PPRE_DIV2
+#define RCC_APB3_DIV4                  RCC_D1CFGR_D1PPRE_DIV4
+#define RCC_APB3_DIV8                  RCC_D1CFGR_D1PPRE_DIV8
+#define RCC_APB3_DIV16                 RCC_D1CFGR_D1PPRE_DIV16
+#else
+#define RCC_APB3_DIV1                  RCC_CDCFGR1_CDPPRE_DIV1
+#define RCC_APB3_DIV2                  RCC_CDCFGR1_CDPPRE_DIV2
+#define RCC_APB3_DIV4                  RCC_CDCFGR1_CDPPRE_DIV4
+#define RCC_APB3_DIV8                  RCC_CDCFGR1_CDPPRE_DIV8
+#define RCC_APB3_DIV16                 RCC_CDCFGR1_CDPPRE_DIV16
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB1_Clock_Source  RCC APB1 Clock Source
+  * @{
+  */
+#if defined (RCC_D2CFGR_D2PPRE1_DIV1)
+#define RCC_APB1_DIV1                  RCC_D2CFGR_D2PPRE1_DIV1
+#define RCC_APB1_DIV2                  RCC_D2CFGR_D2PPRE1_DIV2
+#define RCC_APB1_DIV4                  RCC_D2CFGR_D2PPRE1_DIV4
+#define RCC_APB1_DIV8                  RCC_D2CFGR_D2PPRE1_DIV8
+#define RCC_APB1_DIV16                 RCC_D2CFGR_D2PPRE1_DIV16
+#else
+#define RCC_APB1_DIV1                  RCC_CDCFGR2_CDPPRE1_DIV1
+#define RCC_APB1_DIV2                  RCC_CDCFGR2_CDPPRE1_DIV2
+#define RCC_APB1_DIV4                  RCC_CDCFGR2_CDPPRE1_DIV4
+#define RCC_APB1_DIV8                  RCC_CDCFGR2_CDPPRE1_DIV8
+#define RCC_APB1_DIV16                 RCC_CDCFGR2_CDPPRE1_DIV16
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB2_Clock_Source  RCC APB2 Clock Source
+  * @{
+  */
+#if defined (RCC_D2CFGR_D2PPRE2_DIV1)
+#define RCC_APB2_DIV1                  RCC_D2CFGR_D2PPRE2_DIV1
+#define RCC_APB2_DIV2                  RCC_D2CFGR_D2PPRE2_DIV2
+#define RCC_APB2_DIV4                  RCC_D2CFGR_D2PPRE2_DIV4
+#define RCC_APB2_DIV8                  RCC_D2CFGR_D2PPRE2_DIV8
+#define RCC_APB2_DIV16                 RCC_D2CFGR_D2PPRE2_DIV16
+#else
+#define RCC_APB2_DIV1                  RCC_CDCFGR2_CDPPRE2_DIV1
+#define RCC_APB2_DIV2                  RCC_CDCFGR2_CDPPRE2_DIV2
+#define RCC_APB2_DIV4                  RCC_CDCFGR2_CDPPRE2_DIV4
+#define RCC_APB2_DIV8                  RCC_CDCFGR2_CDPPRE2_DIV8
+#define RCC_APB2_DIV16                 RCC_CDCFGR2_CDPPRE2_DIV16
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB4_Clock_Source  RCC APB4 Clock Source
+  * @{
+  */
+#if defined(RCC_D3CFGR_D3PPRE_DIV1)
+#define RCC_APB4_DIV1                  RCC_D3CFGR_D3PPRE_DIV1
+#define RCC_APB4_DIV2                  RCC_D3CFGR_D3PPRE_DIV2
+#define RCC_APB4_DIV4                  RCC_D3CFGR_D3PPRE_DIV4
+#define RCC_APB4_DIV8                  RCC_D3CFGR_D3PPRE_DIV8
+#define RCC_APB4_DIV16                 RCC_D3CFGR_D3PPRE_DIV16
+#else
+#define RCC_APB4_DIV1                  RCC_SRDCFGR_SRDPPRE_DIV1
+#define RCC_APB4_DIV2                  RCC_SRDCFGR_SRDPPRE_DIV2
+#define RCC_APB4_DIV4                  RCC_SRDCFGR_SRDPPRE_DIV4
+#define RCC_APB4_DIV8                  RCC_SRDCFGR_SRDPPRE_DIV8
+#define RCC_APB4_DIV16                 RCC_SRDCFGR_SRDPPRE_DIV16
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup RCC_RTC_Clock_Source  RCC RTC Clock Source
+  * @{
+  */
+#define RCC_RTCCLKSOURCE_NO_CLK          (0x00000000U)
+#define RCC_RTCCLKSOURCE_LSE             (0x00000100U)
+#define RCC_RTCCLKSOURCE_LSI             (0x00000200U)
+#define RCC_RTCCLKSOURCE_HSE_DIV2        (0x00002300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV3        (0x00003300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV4        (0x00004300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV5        (0x00005300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV6        (0x00006300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV7        (0x00007300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV8        (0x00008300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV9        (0x00009300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV10       (0x0000A300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV11       (0x0000B300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV12       (0x0000C300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV13       (0x0000D300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV14       (0x0000E300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV15       (0x0000F300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV16       (0x00010300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV17       (0x00011300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV18       (0x00012300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV19       (0x00013300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV20       (0x00014300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV21       (0x00015300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV22       (0x00016300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV23       (0x00017300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV24       (0x00018300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV25       (0x00019300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV26       (0x0001A300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV27       (0x0001B300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV28       (0x0001C300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV29       (0x0001D300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV30       (0x0001E300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV31       (0x0001F300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV32       (0x00020300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV33       (0x00021300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV34       (0x00022300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV35       (0x00023300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV36       (0x00024300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV37       (0x00025300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV38       (0x00026300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV39       (0x00027300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV40       (0x00028300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV41       (0x00029300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV42       (0x0002A300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV43       (0x0002B300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV44       (0x0002C300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV45       (0x0002D300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV46       (0x0002E300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV47       (0x0002F300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV48       (0x00030300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV49       (0x00031300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV50       (0x00032300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV51       (0x00033300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV52       (0x00034300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV53       (0x00035300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV54       (0x00036300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV55       (0x00037300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV56       (0x00038300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV57       (0x00039300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV58       (0x0003A300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV59       (0x0003B300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV60       (0x0003C300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV61       (0x0003D300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV62       (0x0003E300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV63       (0x0003F300U)
+
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_MCO_Index  RCC MCO Index
+  * @{
+  */
+#define RCC_MCO1                         (0x00000000U)
+#define RCC_MCO2                         (0x00000001U)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MCO1_Clock_Source  RCC MCO1 Clock Source
+  * @{
+  */
+#define RCC_MCO1SOURCE_HSI               (0x00000000U)
+#define RCC_MCO1SOURCE_LSE               RCC_CFGR_MCO1_0
+#define RCC_MCO1SOURCE_HSE               RCC_CFGR_MCO1_1
+#define RCC_MCO1SOURCE_PLL1QCLK          ((uint32_t)RCC_CFGR_MCO1_0 | RCC_CFGR_MCO1_1)
+#define RCC_MCO1SOURCE_HSI48              RCC_CFGR_MCO1_2
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MCO2_Clock_Source  RCC MCO2 Clock Source
+  * @{
+  */
+#define RCC_MCO2SOURCE_SYSCLK            (0x00000000U)
+#define RCC_MCO2SOURCE_PLL2PCLK          RCC_CFGR_MCO2_0
+#define RCC_MCO2SOURCE_HSE               RCC_CFGR_MCO2_1
+#define RCC_MCO2SOURCE_PLLCLK            ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_1)
+#define RCC_MCO2SOURCE_CSICLK            RCC_CFGR_MCO2_2
+#define RCC_MCO2SOURCE_LSICLK            ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_2)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MCOx_Clock_Prescaler  RCC MCOx Clock Prescaler
+  * @{
+  */
+#define RCC_MCODIV_1                    RCC_CFGR_MCO1PRE_0
+#define RCC_MCODIV_2                    RCC_CFGR_MCO1PRE_1
+#define RCC_MCODIV_3                    ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1)
+#define RCC_MCODIV_4                    RCC_CFGR_MCO1PRE_2
+#define RCC_MCODIV_5                    ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
+#define RCC_MCODIV_6                    ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
+#define RCC_MCODIV_7                    ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
+#define RCC_MCODIV_8                    RCC_CFGR_MCO1PRE_3
+#define RCC_MCODIV_9                    ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_3)
+#define RCC_MCODIV_10                   ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
+#define RCC_MCODIV_11                   ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
+#define RCC_MCODIV_12                   ((uint32_t)RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
+#define RCC_MCODIV_13                   ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
+#define RCC_MCODIV_14                   ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
+#define RCC_MCODIV_15                   RCC_CFGR_MCO1PRE
+
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Interrupt  RCC Interrupt
+  * @{
+  */
+#define RCC_IT_LSIRDY                  (0x00000001U)
+#define RCC_IT_LSERDY                  (0x00000002U)
+#define RCC_IT_HSIRDY                  (0x00000004U)
+#define RCC_IT_HSERDY                  (0x00000008U)
+#define RCC_IT_CSIRDY                  (0x00000010U)
+#define RCC_IT_HSI48RDY                (0x00000020U)
+#define RCC_IT_PLLRDY                  (0x00000040U)
+#define RCC_IT_PLL2RDY                 (0x00000080U)
+#define RCC_IT_PLL3RDY                 (0x00000100U)
+#define RCC_IT_LSECSS                  (0x00000200U)
+#define RCC_IT_CSS                     (0x00000400U)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Flag  RCC Flag
+  *        Elements values convention: XXXYYYYYb
+  *           - YYYYY  : Flag position in the register
+  *           - XXX  : Register index
+  *                 - 001: CR register
+  *                 - 010: BDCR register
+  *                 - 011: CSR register
+  *                 - 100: RSR register
+  * @{
+  */
+/* Flags in the CR register */
+#define RCC_FLAG_HSIRDY                ((uint8_t)0x22)
+#define RCC_FLAG_HSIDIV                ((uint8_t)0x25)
+#define RCC_FLAG_CSIRDY                ((uint8_t)0x28)
+#define RCC_FLAG_HSI48RDY              ((uint8_t)0x2D)
+#if defined(RCC_CR_D1CKRDY)
+#define RCC_FLAG_D1CKRDY               ((uint8_t)0x2E)
+#else
+#define RCC_FLAG_CPUCKRDY              ((uint8_t)0x2E)
+#define RCC_FLAG_D1CKRDY               RCC_FLAG_CPUCKRDY   /* alias */
+#endif /* RCC_CR_D1CKRDY */
+#if defined(RCC_CR_D2CKRDY)
+#define RCC_FLAG_D2CKRDY               ((uint8_t)0x2F)
+#else
+#define RCC_FLAG_CDCKRDY               ((uint8_t)0x2F)
+#define RCC_FLAG_D2CKRDY               RCC_FLAG_CDCKRDY    /* alias */
+#endif /* RCC_CR_D2CKRDY */
+#define RCC_FLAG_HSERDY                ((uint8_t)0x31)
+#define RCC_FLAG_PLLRDY                ((uint8_t)0x39)
+#define RCC_FLAG_PLL2RDY               ((uint8_t)0x3B)
+#define RCC_FLAG_PLL3RDY               ((uint8_t)0x3D)
+/* Flags in the BDCR register */
+#define RCC_FLAG_LSERDY                ((uint8_t)0x41)
+
+/* Flags in the CSR register */
+#define RCC_FLAG_LSIRDY                ((uint8_t)0x61)
+
+/* Flags in the RSR register */
+#if defined(RCC_RSR_CPURSTF)
+#define RCC_FLAG_CPURST                ((uint8_t)0x91)
+#endif /* RCC_RSR_CPURSTF */
+
+#if defined(RCC_RSR_D1RSTF)
+#define RCC_FLAG_D1RST                 ((uint8_t)0x93)
+#else
+#define RCC_FLAG_CDRST                 ((uint8_t)0x93)
+#endif /* RCC_RSR_D1RSTF */
+#if defined(RCC_RSR_D2RSTF)
+#define RCC_FLAG_D2RST                 ((uint8_t)0x94)
+#endif /* RCC_RSR_D2RSTF */
+#define RCC_FLAG_BORRST                ((uint8_t)0x95)
+#define RCC_FLAG_PINRST                ((uint8_t)0x96)
+#define RCC_FLAG_PORRST                ((uint8_t)0x97)
+#define RCC_FLAG_SFTRST                ((uint8_t)0x98)
+#define RCC_FLAG_IWDG1RST              ((uint8_t)0x9A)
+#define RCC_FLAG_WWDG1RST              ((uint8_t)0x9C)
+#define RCC_FLAG_LPWR1RST              ((uint8_t)0x9E)
+#define RCC_FLAG_LPWR2RST              ((uint8_t)0x9F)
+
+#if defined(DUAL_CORE)
+#define RCC_FLAG_C1RST                 (RCC_FLAG_CPURST)
+#define RCC_FLAG_C2RST                 ((uint8_t)0x92)
+#define RCC_FLAG_SFTR1ST               (RCC_FLAG_SFTRST)
+#define RCC_FLAG_SFTR2ST               ((uint8_t)0x99)
+#define RCC_FLAG_WWDG2RST              ((uint8_t)0x9D)
+#define RCC_FLAG_IWDG2RST              ((uint8_t)0x9B)
+#endif /*DUAL_CORE*/
+
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LSEDrive_Config LSE Drive Config
+  * @{
+  */
+#define RCC_LSEDRIVE_LOW                 (0x00000000U) /*!< LSE low drive capability */
+#define RCC_LSEDRIVE_MEDIUMLOW           RCC_BDCR_LSEDRV_0      /*!< LSE medium low drive capability */
+#define RCC_LSEDRIVE_MEDIUMHIGH          RCC_BDCR_LSEDRV_1      /*!< LSE medium high drive capability */
+#define RCC_LSEDRIVE_HIGH                RCC_BDCR_LSEDRV        /*!< LSE high drive capability */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Stop_WakeUpClock  RCC Stop WakeUpClock
+  * @{
+  */
+#define RCC_STOP_WAKEUPCLOCK_HSI       (0x00000000U)
+#define RCC_STOP_WAKEUPCLOCK_CSI       RCC_CFGR_STOPWUCK
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Stop_KernelWakeUpClock  RCC Stop KernelWakeUpClock
+  * @{
+  */
+#define RCC_STOP_KERWAKEUPCLOCK_HSI       (0x00000000U)
+#define RCC_STOP_KERWAKEUPCLOCK_CSI        RCC_CFGR_STOPKERWUCK
+
+
+/**
+  * @}
+  */
+
+#if defined(RCC_VER_X)
+#define HAL_RCC_REV_Y_HSITRIM_Pos  (12U)
+#define HAL_RCC_REV_Y_HSITRIM_Msk  (0x3F000U)
+#define HAL_RCC_REV_Y_CSITRIM_Pos  (26U)
+#define HAL_RCC_REV_Y_CSITRIM_Msk  (0x7C000000U)
+#endif /* RCC_VER_X */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Macros RCC Exported Macros
+  * @{
+  */
+
+/** @brief  Enable or disable the AHB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+#define __HAL_RCC_MDMA_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_DMA2D_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(JPEG)
+#define __HAL_RCC_JPGDECEN_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* JPEG */
+
+#define __HAL_RCC_FMC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* QUADSPI */
+#if defined(OCTOSPI1)
+#define __HAL_RCC_OSPI1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* OCTOSPI1 */
+#if defined(OCTOSPI2)
+#define __HAL_RCC_OSPI2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* OCTOSPI2 */
+#if defined(OCTOSPIM)
+#define __HAL_RCC_OCTOSPIM_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_IOMNGREN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_IOMNGREN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* OCTOSPIM */
+#if defined(OTFDEC1)
+#define __HAL_RCC_OTFDEC1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* OTFDEC1 */
+#if defined(OTFDEC2)
+#define __HAL_RCC_OTFDEC2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* OTFDEC2 */
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GFXMMUEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GFXMMUEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* GFXMMU */
+#define __HAL_RCC_SDMMC1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_MDMA_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN))
+#define __HAL_RCC_DMA2D_CLK_DISABLE()           (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN))
+#if defined(JPEG)
+#define __HAL_RCC_JPGDECEN_CLK_DISABLE()        (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN))
+#endif /* JPEG */
+#define __HAL_RCC_FMC_CLK_DISABLE()             (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))
+
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN))
+#endif /* QUADSPI */
+#if defined(OCTOSPI1)
+#define __HAL_RCC_OSPI1_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OSPI1EN))
+#endif /* OCTOSPII */
+#if defined(OCTOSPI2)
+#define __HAL_RCC_OSPI2_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OSPI2EN))
+#endif /* OCTOSPI2 */
+#define __HAL_RCC_SDMMC1_CLK_DISABLE()          (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN))
+#if defined(OCTOSPIM)
+#define __HAL_RCC_OCTOSPIM_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_IOMNGREN))
+#endif /* OCTOSPIM */
+#if defined(OTFDEC1)
+#define __HAL_RCC_OTFDEC1_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OTFDEC1EN))
+#endif /* OTOFDEC1 */
+#if defined(OTFDEC2)
+#define __HAL_RCC_OTFDEC2_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OTFDEC2EN))
+#endif /* OTOFDEC2 */
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_GFXMMUEN))
+#endif /* GFXMMU */
+
+/** @brief  Get the enable or disable status of the AHB3 peripheral clock
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_MDMA_IS_CLK_ENABLED()          ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN)   != 0U)
+#define __HAL_RCC_DMA2D_IS_CLK_ENABLED()         ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN)  != 0U)
+#if defined(JPEG)
+#define __HAL_RCC_JPGDECEN_IS_CLK_ENABLED()      ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) != 0U)
+#endif /* JPEG */
+#define __HAL_RCC_FMC_IS_CLK_ENABLED()           ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN)    != 0U)
+#if defined (QUADSPI)
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED()          ((RCC->AHB3ENR & RCC_AHB3ENR_QSPIEN)   != 0U)
+#endif /* QUADSPI */
+#if defined(OCTOSPI1)
+#define __HAL_RCC_OSPI1_IS_CLK_ENABLED()          ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI1EN)   != 0U)
+#endif /* OCTOSPII */
+#if defined(OCTOSPI2)
+#define __HAL_RCC_OSPI2_IS_CLK_ENABLED()          ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI2EN)   != 0U)
+#endif /* OCTOSPI2 */
+#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) != 0U)
+#if defined(OCTOSPIM)
+#define __HAL_RCC_OCTOSPIM_IS_CLK_ENABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_IOMNGREN) != 0U)
+#endif /* OCTOSPIM */
+#if defined(OTFDEC1)
+#define __HAL_RCC_OTFDEC1_IS_CLK_ENABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC1EN) != 0U)
+#endif /* OTOFDEC1 */
+#if defined(OTFDEC2)
+#define __HAL_RCC_OTFDEC2_IS_CLK_ENABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC2EN) != 0U)
+#endif /* OTOFDEC2 */
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_IS_CLK_ENABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_GFXMMUEN) != 0U)
+#endif /* GFXMMU */
+
+#define __HAL_RCC_MDMA_IS_CLK_DISABLED()         ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN)   == 0U)
+#define __HAL_RCC_DMA2D_IS_CLK_DISABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN)  == 0U)
+#if defined(JPEG)
+#define __HAL_RCC_JPGDECEN_IS_CLK_DISABLED()     ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) == 0U)
+#endif /* JPEG */
+#define __HAL_RCC_FMC_IS_CLK_DISABLED()          ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN)    == 0U)
+#if defined (QUADSPI)
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED()         ((RCC->AHB3ENR & RCC_AHB3ENR_QSPIEN)   == 0U)
+#endif /* QUADSPI */
+#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED()       ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) == 0U)
+#if defined(OCTOSPI1)
+#define __HAL_RCC_OSPI1_IS_CLK_DISABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI1EN) == 0U)
+#endif
+#if defined(OCTOSPI2)
+#define __HAL_RCC_OSPI2_IS_CLK_DISABLED()     ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI2EN) == 0U)
+#endif
+#if defined(OCTOSPIM)
+#define __HAL_RCC_OCTOSPIM_IS_CLK_DISABLED()     ((RCC->AHB3ENR & RCC_AHB3ENR_IOMNGREN) == 0U)
+#endif
+#if defined(OTFDEC1)
+#define __HAL_RCC_OTFDEC1_IS_CLK_DISABLED()      ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC1EN) == 0U)
+#endif
+#if defined(OTFDEC2)
+#define __HAL_RCC_OTFDEC2_IS_CLK_DISABLED()      ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC2EN) == 0U)
+#endif
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_IS_CLK_DISABLED()       ((RCC->AHB3ENR & RCC_AHB3ENR_GFXMMUEN) == 0U)
+#endif
+/** @brief  Enable or disable the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_DMA1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_DMA2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_ADC12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(DUAL_CORE)
+#define __HAL_RCC_ART_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ARTEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ARTEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /*DUAL_CORE*/
+
+#if defined(RCC_AHB1ENR_CRCEN)
+#define __HAL_RCC_CRC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif
+
+#if defined(ETH)
+#define __HAL_RCC_ETH1MAC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_ETH1TX_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_ETH1RX_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif
+
+#define __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(USB2_OTG_FS)
+#define __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif
+
+#define __HAL_RCC_DMA1_CLK_DISABLE()             (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN))
+#define __HAL_RCC_DMA2_CLK_DISABLE()             (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN))
+#define __HAL_RCC_ADC12_CLK_DISABLE()            (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN))
+#if defined(DUAL_CORE)
+#define __HAL_RCC_ART_CLK_DISABLE()              (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN))
+#endif /*DUAL_CORE*/
+#if defined(RCC_AHB1ENR_CRCEN)
+#define __HAL_RCC_CRC_CLK_DISABLE()              (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_CRCEN))
+#endif
+#if defined(ETH)
+#define __HAL_RCC_ETH1MAC_CLK_DISABLE()          (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN))
+#define __HAL_RCC_ETH1TX_CLK_DISABLE()           (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN))
+#define __HAL_RCC_ETH1RX_CLK_DISABLE()           (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN))
+#endif
+#define __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()      (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN))
+#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN))
+#if defined(USB2_OTG_FS)
+#define __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()      (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN))
+#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN))
+#endif /* USB2_OTG_FS */
+
+/** @brief  Get the enable or disable status of the AHB1 peripheral clock
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_DMA1_IS_CLK_ENABLED()              ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN)          != 0U)
+#define __HAL_RCC_DMA2_IS_CLK_ENABLED()              ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN)          != 0U)
+#define __HAL_RCC_ADC12_IS_CLK_ENABLED()             ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN)         != 0U)
+#if defined(DUAL_CORE)
+#define __HAL_RCC_ART_IS_CLK_ENABLED()               ((RCC->AHB1ENR & RCC_AHB1ENR_ARTEN)           != 0U)
+#endif /*DUAL_CORE*/
+#if defined(RCC_AHB1ENR_CRCEN)
+#define __HAL_RCC_CRC_IS_CLK_ENABLED()              ((RCC->AHB1ENR & RCC_AHB1ENR_CRCEN)       != 0U)
+#endif
+#if defined(ETH)
+#define __HAL_RCC_ETH1MAC_IS_CLK_ENABLED()           ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1MACEN)       != 0U)
+#define __HAL_RCC_ETH1TX_IS_CLK_ENABLED()            ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1TXEN)        != 0U)
+#define __HAL_RCC_ETH1RX_IS_CLK_ENABLED()            ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1RXEN)        != 0U)
+#endif
+#define __HAL_RCC_USB1_OTG_HS_IS_CLK_ENABLED()       ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN)     != 0U)
+#define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_ENABLED()  ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) != 0U)
+#if defined(USB2_OTG_FS)
+#define __HAL_RCC_USB2_OTG_FS_IS_CLK_ENABLED()       ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSEN)     != 0U)
+#define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_ENABLED()  ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSULPIEN) != 0U)
+#endif /* USB2_OTG_FS */
+
+#define __HAL_RCC_DMA1_IS_CLK_DISABLED()             ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN)          == 0U)
+#define __HAL_RCC_DMA2_IS_CLK_DISABLED()             ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN)          == 0U)
+#define __HAL_RCC_ADC12_IS_CLK_DISABLED()            ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN)         == 0U)
+#if defined(DUAL_CORE)
+#define __HAL_RCC_ART_IS_CLK_DISABLED()              ((RCC->AHB1ENR & RCC_AHB1ENR_ARTEN)           == 0U)
+#endif /*DUAL_CORE*/
+#if defined(RCC_AHB1ENR_CRCEN)
+#define __HAL_RCC_CRC_IS_CLK_DISABLED()              ((RCC->AHB1ENR & RCC_AHB1ENR_CRCEN)           == 0U)
+#endif
+#if defined(ETH)
+#define __HAL_RCC_ETH1MAC_IS_CLK_DISABLED()          ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1MACEN)       == 0U)
+#define __HAL_RCC_ETH1TX_IS_CLK_DISABLED()           ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1TXEN)        == 0U)
+#define __HAL_RCC_ETH1RX_IS_CLK_DISABLED()           ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1RXEN)        == 0U)
+#endif
+#define __HAL_RCC_USB1_OTG_HS_IS_CLK_DISABLED()      ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN)     == 0U)
+#define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) == 0U)
+#if defined(USB2_OTG_FS)
+#define __HAL_RCC_USB2_OTG_FS_IS_CLK_DISABLED()      ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSEN)     == 0U)
+#define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSULPIEN) == 0U)
+#endif /* USB2_OTG_FS */
+
+/** @brief  Enable or disable the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#if defined(DCMI) && defined(PSSI)
+#define __HAL_RCC_DCMI_PSSI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_DCMI_CLK_ENABLE()  __HAL_RCC_DCMI_PSSI_CLK_ENABLE()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_DCMI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* DCMI && PSSI */
+
+#if defined(CRYP)
+#define __HAL_RCC_CRYP_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* CRYP */
+
+#if defined(HASH)
+#define __HAL_RCC_HASH_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* HASH */
+
+#define __HAL_RCC_RNG_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_SDMMC2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(RCC_AHB2ENR_D2SRAM1EN)
+#define __HAL_RCC_D2SRAM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#else
+#define __HAL_RCC_AHBSRAM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* RCC_AHB2ENR_D2SRAM1EN */
+
+#if defined(RCC_AHB2ENR_D2SRAM2EN)
+#define __HAL_RCC_D2SRAM2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#else
+#define __HAL_RCC_AHBSRAM2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* RCC_AHB2ENR_D2SRAM2EN */
+
+#if defined(RCC_AHB2ENR_D2SRAM3EN)
+#define __HAL_RCC_D2SRAM3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif
+
+#if defined(RCC_AHB2ENR_HSEMEN)
+#define __HAL_RCC_HSEM_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* RCC_AHB2ENR_HSEMEN */
+
+#if defined(BDMA1)
+#define __HAL_RCC_BDMA1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_BDMA1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_BDMA1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* BDMA1 */
+
+#if defined(DCMI) && defined(PSSI)
+#define __HAL_RCC_DCMI_PSSI_CLK_DISABLE()         (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMI_PSSIEN))
+#define __HAL_RCC_DCMI_CLK_DISABLE()              __HAL_RCC_DCMI_PSSI_CLK_DISABLE()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_DCMI_CLK_DISABLE()             (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))
+#endif /* DCMI && PSSI */
+#if defined(CRYP)
+#define __HAL_RCC_CRYP_CLK_DISABLE()             (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_HASH_CLK_DISABLE()             (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))
+#endif /* HASH */
+#define __HAL_RCC_RNG_CLK_DISABLE()              (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))
+#define __HAL_RCC_SDMMC2_CLK_DISABLE()           (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))
+#if defined(RCC_AHB2ENR_D2SRAM1EN)
+#define __HAL_RCC_D2SRAM1_CLK_DISABLE()          (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN))
+#else
+#define __HAL_RCC_AHBSRAM1_CLK_DISABLE()         (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_AHBSRAM1EN))
+#endif /* RCC_AHB2ENR_D2SRAM1EN */
+#if defined(RCC_AHB2ENR_D2SRAM2EN)
+#define __HAL_RCC_D2SRAM2_CLK_DISABLE()          (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN))
+#else
+#define __HAL_RCC_AHBSRAM2_CLK_DISABLE()         (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_AHBSRAM2EN))
+#endif /* RCC_AHB2ENR_D2SRAM2EN */
+#if defined(RCC_AHB2ENR_D2SRAM3EN)
+#define __HAL_RCC_D2SRAM3_CLK_DISABLE()          (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN))
+#endif
+#if defined(RCC_AHB2ENR_HSEMEN)
+#define __HAL_RCC_HSEM_CLK_DISABLE()             (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HSEMEN))
+#endif
+#if defined(BDMA1)
+#define __HAL_RCC_BDMA1_CLK_DISABLE()            (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_BDMA1EN))
+#endif
+
+/** @brief  Get the enable or disable status of the AHB2 peripheral clock
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#if defined(DCMI) && defined(PSSI)
+#define __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED()         ((RCC->AHB2ENR & RCC_AHB2ENR_DCMI_PSSIEN)    != 0U)
+#define __HAL_RCC_DCMI_IS_CLK_ENABLED()              __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_DCMI_IS_CLK_ENABLED()              ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN)    != 0U)
+#endif /* DCMI && PSSI */
+#if defined(CRYP)
+#define __HAL_RCC_CRYP_IS_CLK_ENABLED()              ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN)    != 0U)
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_HASH_IS_CLK_ENABLED()              ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN)    != 0U)
+#endif /* HASH */
+#define __HAL_RCC_RNG_IS_CLK_ENABLED()               ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN)     != 0U)
+#define __HAL_RCC_SDMMC2_IS_CLK_ENABLED()            ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN)  != 0U)
+#if defined(RCC_AHB2ENR_D2SRAM1EN)
+#define __HAL_RCC_D2SRAM1_IS_CLK_ENABLED()           ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM1EN) != 0U)
+#else
+#define __HAL_RCC_AHBSRAM1_IS_CLK_ENABLED()          ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM1EN) != 0U)
+#endif /* RCC_AHB2ENR_D2SRAM1EN */
+#if defined(RCC_AHB2ENR_D2SRAM2EN)
+#define __HAL_RCC_D2SRAM2_IS_CLK_ENABLED()           ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM2EN) != 0U)
+#else
+#define __HAL_RCC_AHBSRAM2_IS_CLK_ENABLED()          ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM2EN) != 0U)
+#endif /* RCC_AHB2ENR_D2SRAM2EN */
+#if defined(RCC_AHB2ENR_D2SRAM3EN)
+#define __HAL_RCC_D2SRAM3_IS_CLK_ENABLED()           ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM3EN) != 0U)
+#endif
+#if defined(RCC_AHB2ENR_HSEMEN)
+#define __HAL_RCC_HSEM_IS_CLK_ENABLED()              ((RCC->AHB2ENR & RCC_AHB2ENR_HSEMEN)    != 0U)
+#endif
+#if defined(BDMA1)
+#define __HAL_RCC_BDMA1_IS_CLK_ENABLED()             ((RCC->AHB2ENR & RCC_AHB2ENR_BDMA1EN)  != 0U)
+#endif
+
+#if defined(DCMI) && defined(PSSI)
+#define __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED()        ((RCC->AHB2ENR & RCC_AHB2ENR_DCMI_PSSIEN)    == 0U)
+#define __HAL_RCC_DCMI_IS_CLK_DISABLED()             __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_DCMI_IS_CLK_DISABLED()             ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN)    == 0U)
+#endif /* DCMI && PSSI */
+#if defined(CRYP)
+#define __HAL_RCC_CRYP_IS_CLK_DISABLED()             ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN)    == 0U)
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_HASH_IS_CLK_DISABLED()             ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN)    == 0U)
+#endif /* HASH */
+#define __HAL_RCC_RNG_IS_CLK_DISABLED()              ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN)     == 0U)
+#define __HAL_RCC_SDMMC2_IS_CLK_DISABLED()           ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN)  == 0U)
+#if defined(RCC_AHB2ENR_D2SRAM1EN)
+#define __HAL_RCC_D2SRAM1_IS_CLK_DISABLED()          ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM1EN) == 0U)
+#else
+#define __HAL_RCC_AHBSRAM1_IS_CLK_DISABLED()         ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM1EN) == 0U)
+#endif /* RCC_AHB2ENR_D2SRAM1EN */
+#if defined(RCC_AHB2ENR_D2SRAM2EN)
+#define __HAL_RCC_D2SRAM2_IS_CLK_DISABLED()          ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM2EN) == 0U)
+#else
+#define __HAL_RCC_AHBSRAM2_IS_CLK_DISABLED()         ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM2EN) == 0U)
+#endif /* RCC_AHB2ENR_D2SRAM2EN */
+#if defined(RCC_AHB2ENR_D2SRAM3EN)
+#define __HAL_RCC_D2SRAM3_IS_CLK_DISABLED()          ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM3EN) == 0U)
+#endif
+#if defined(RCC_AHB2ENR_HSEMEN)
+#define __HAL_RCC_HSEM_IS_CLK_DISABLED()             ((RCC->AHB2ENR & RCC_AHB2ENR_HSEMEN)    == 0U)
+#endif
+#if defined(BDMA1)
+#define __HAL_RCC_BDMA1_IS_CLK_DISABLED()            ((RCC->AHB2ENR & RCC_AHB2ENR_BDMA1EN)   == 0U)
+#endif
+
+/** @brief  Enable or disable the AHB4 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_GPIOA_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_GPIOB_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_GPIOC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_GPIOF_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_GPIOG_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_GPIOH_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_GPIOI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_GPIOJ_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_GPIOK_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(RCC_AHB4ENR_CRCEN)
+#define __HAL_RCC_CRC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif
+
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMA2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMA2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_BDMA_CLK_ENABLE()  __HAL_RCC_BDMA2_CLK_ENABLE()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_BDMA_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif
+
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif
+
+#if defined(RCC_AHB4ENR_HSEMEN)
+#define __HAL_RCC_HSEM_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif
+
+#if defined(RCC_AHB4ENR_SRDSRAMEN)
+#define __HAL_RCC_SRDSRAM_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SRDSRAMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SRDSRAMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif
+
+#define __HAL_RCC_BKPRAM_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_GPIOA_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN)
+#define __HAL_RCC_GPIOB_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN)
+#define __HAL_RCC_GPIOC_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN)
+#define __HAL_RCC_GPIOD_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN)
+#define __HAL_RCC_GPIOE_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN)
+#define __HAL_RCC_GPIOF_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN)
+#define __HAL_RCC_GPIOG_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN)
+#define __HAL_RCC_GPIOH_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN)
+#define __HAL_RCC_GPIOI_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN)
+#define __HAL_RCC_GPIOJ_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN)
+#define __HAL_RCC_GPIOK_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN)
+#if defined(RCC_AHB4ENR_CRCEN)
+#define __HAL_RCC_CRC_CLK_DISABLE()             (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN)
+#endif
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMA2EN)
+#define __HAL_RCC_BDMA_CLK_DISABLE()            __HAL_RCC_BDMA2_CLK_DISABLE()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_BDMA_CLK_DISABLE()            (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN)
+#endif
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_CLK_DISABLE()            (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN)
+#endif
+#if defined(RCC_AHB4ENR_HSEMEN)
+#define __HAL_RCC_HSEM_CLK_DISABLE()            (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN)
+#endif
+#if defined(RCC_AHB4ENR_SRDSRAMEN)
+#define __HAL_RCC_SRDSRAM_CLK_DISABLE()         (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_SRDSRAMEN)
+#endif
+#define __HAL_RCC_BKPRAM_CLK_DISABLE()          (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN)
+
+
+/** @brief  Get the enable or disable status of the AHB4 peripheral clock
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_GPIOA_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN)  != 0U)
+#define __HAL_RCC_GPIOB_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN)  != 0U)
+#define __HAL_RCC_GPIOC_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN)  != 0U)
+#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN)  != 0U)
+#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN)  != 0U)
+#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN)  != 0U)
+#define __HAL_RCC_GPIOG_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN)  != 0U)
+#define __HAL_RCC_GPIOH_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN)  != 0U)
+#define __HAL_RCC_GPIOI_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN)  != 0U)
+#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN)  != 0U)
+#define __HAL_RCC_GPIOK_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN)  != 0U)
+#if defined(RCC_AHB4ENR_CRCEN)
+#define __HAL_RCC_CRC_IS_CLK_ENABLED()              ((RCC->AHB4ENR & RCC_AHB4ENR_CRCEN)    != 0U)
+#endif
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_BDMA2EN)   != 0U)
+#define __HAL_RCC_BDMA_IS_CLK_ENABLED()  __HAL_RCC_BDMA2_IS_CLK_ENABLED()            /* for API backward compatibility*/
+#else
+#define __HAL_RCC_BDMA_IS_CLK_ENABLED()             ((RCC->AHB4ENR & RCC_AHB4ENR_BDMAEN)   != 0U)
+#endif
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_IS_CLK_ENABLED()             ((RCC->AHB4ENR & RCC_AHB4ENR_ADC3EN)   != 0U)
+#endif
+#if defined(RCC_AHB4ENR_HSEMEN)
+#define __HAL_RCC_HSEM_IS_CLK_ENABLED()             ((RCC->AHB4ENR & RCC_AHB4ENR_HSEMEN)   != 0U)
+#endif
+#if defined(RCC_AHB4ENR_SRDSRAMEN)
+#define __HAL_RCC_SRDSRAM_IS_CLK_ENABLED()          ((RCC->AHB4ENR & RCC_AHB4ENR_SRDSRAMEN) != 0U)
+#endif
+#define __HAL_RCC_BKPRAM_IS_CLK_ENABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) != 0U)
+
+#define __HAL_RCC_GPIOA_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN)  == 0U)
+#define __HAL_RCC_GPIOB_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN)  == 0U)
+#define __HAL_RCC_GPIOC_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN)  == 0U)
+#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN)  == 0U)
+#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN)  == 0U)
+#define __HAL_RCC_GPIOF_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN)  == 0U)
+#define __HAL_RCC_GPIOG_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN)  == 0U)
+#define __HAL_RCC_GPIOH_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN)  == 0U)
+#define __HAL_RCC_GPIOI_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN)  == 0U)
+#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN)  == 0U)
+#define __HAL_RCC_GPIOK_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN)  == 0U)
+
+#if defined(RCC_AHB4ENR_CRCEN)
+#define __HAL_RCC_CRC_IS_CLK_DISABLED()             ((RCC->AHB4ENR & RCC_AHB4ENR_CRCEN)    == 0U)
+#endif
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_IS_CLK_DISABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_BDMA2EN)   == 0U)
+#define __HAL_RCC_BDMA_IS_CLK_DISABLED()  __HAL_RCC_BDMA2_IS_CLK_DISABLED()           /* for API backward compatibility*/
+#else
+#define __HAL_RCC_BDMA_IS_CLK_DISABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_BDMAEN)   == 0U)
+#endif
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_IS_CLK_DISABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_ADC3EN)   == 0U)
+#endif
+#if defined(RCC_AHB4ENR_HSEMEN)
+#define __HAL_RCC_HSEM_IS_CLK_DISABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_HSEMEN)   == 0U)
+#endif
+#if defined(RCC_AHB4ENR_SRDSRAMEN)
+#define __HAL_RCC_SRDSRAM_IS_CLK_DISABLED()         ((RCC->AHB4ENR & RCC_AHB4ENR_SRDSRAMEN)   == 0U)
+#endif
+#define __HAL_RCC_BKPRAM_IS_CLK_DISABLED()          ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) == 0U)
+
+
+/** @brief  Enable or disable the APB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LTDCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LTDCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* LTDC */
+
+#if defined(DSI)
+#define __HAL_RCC_DSI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB3ENR, RCC_APB3ENR_DSIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_DSIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /*DSI*/
+
+#define __HAL_RCC_WWDG1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_CLK_DISABLE()           (RCC->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN)
+#endif /* LTDC */
+#if defined(DSI)
+#define __HAL_RCC_DSI_CLK_DISABLE()            (RCC->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN)
+#endif /*DSI*/
+#define __HAL_RCC_WWDG1_CLK_DISABLE()          (RCC->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN)
+
+/** @brief  Get the enable or disable status of the APB3 peripheral clock
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_IS_CLK_ENABLED()            ((RCC->APB3ENR & RCC_APB3ENR_LTDCEN)  != 0U)
+#endif /* LTDC */
+#if defined(DSI)
+#define __HAL_RCC_DSI_IS_CLK_ENABLED()             ((RCC->APB3ENR & RCC_APB3ENR_DSIEN)   != 0U)
+#endif /*DSI*/
+#define __HAL_RCC_WWDG1_IS_CLK_ENABLED()           ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) != 0U)
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_IS_CLK_DISABLED()           ((RCC->APB3ENR & RCC_APB3ENR_LTDCEN)  == 0U)
+#endif /* LTDC */
+#if defined(DSI)
+#define __HAL_RCC_DSI_IS_CLK_DISABLED()            ((RCC->APB3ENR & RCC_APB3ENR_DSIEN)   == 0U)
+#endif /*DSI*/
+#define __HAL_RCC_WWDG1_IS_CLK_DISABLED()          ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) == 0U)
+
+
+/** @brief  Enable or disable the APB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_TIM2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM6_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM7_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM13_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM14_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_LPTIM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(DUAL_CORE)
+#define __HAL_RCC_WWDG2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDG2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDG2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /*DUAL_CORE*/
+
+#define __HAL_RCC_SPI2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_SPI3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_SPDIFRX_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_USART2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_USART3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_UART4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_UART5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_I2C1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_I2C2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_I2C3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_CEC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_DAC12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_UART7_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_UART8_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_CRS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_SWPMI1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_OPAMP_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_MDIOS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_FDCAN_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_TIM2_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN)
+#define __HAL_RCC_TIM3_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN)
+#define __HAL_RCC_TIM4_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN)
+#define __HAL_RCC_TIM5_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN)
+#define __HAL_RCC_TIM6_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN)
+#define __HAL_RCC_TIM7_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN)
+#define __HAL_RCC_TIM12_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN)
+#define __HAL_RCC_TIM13_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN)
+#define __HAL_RCC_TIM14_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN)
+#define __HAL_RCC_LPTIM1_CLK_DISABLE()         (RCC->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN)
+
+#if defined(DUAL_CORE)
+#define __HAL_RCC_WWDG2_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN)
+#endif /*DUAL_CORE*/
+
+#define __HAL_RCC_SPI2_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN)
+#define __HAL_RCC_SPI3_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN)
+#define __HAL_RCC_SPDIFRX_CLK_DISABLE()        (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN)
+#define __HAL_RCC_USART2_CLK_DISABLE()         (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN)
+#define __HAL_RCC_USART3_CLK_DISABLE()         (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN)
+#define __HAL_RCC_UART4_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN)
+#define __HAL_RCC_UART5_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN)
+#define __HAL_RCC_I2C1_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN)
+#define __HAL_RCC_I2C2_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN)
+#define __HAL_RCC_I2C3_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN)
+#define __HAL_RCC_CEC_CLK_DISABLE()            (RCC->APB1LENR) &= ~ (RCC_APB1LENR_CECEN)
+#define __HAL_RCC_DAC12_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN)
+#define __HAL_RCC_UART7_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN)
+#define __HAL_RCC_UART8_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN)
+#define __HAL_RCC_CRS_CLK_DISABLE()            (RCC->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN)
+#define __HAL_RCC_SWPMI1_CLK_DISABLE()          (RCC->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN)
+#define __HAL_RCC_OPAMP_CLK_DISABLE()          (RCC->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN)
+#define __HAL_RCC_MDIOS_CLK_DISABLE()          (RCC->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN)
+#define __HAL_RCC_FDCAN_CLK_DISABLE()          (RCC->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN)
+
+
+/** @brief  Get the enable or disable status of the APB1 peripheral clock
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_TIM2_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN)    != 0U)
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN)    != 0U)
+#define __HAL_RCC_TIM4_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN)    != 0U)
+#define __HAL_RCC_TIM5_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN)    != 0U)
+#define __HAL_RCC_TIM6_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN)    != 0U)
+#define __HAL_RCC_TIM7_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN)    != 0U)
+#define __HAL_RCC_TIM12_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN)   != 0U)
+#define __HAL_RCC_TIM13_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN)   != 0U)
+#define __HAL_RCC_TIM14_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN)   != 0U)
+#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED()          ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN)  != 0U)
+#if defined(DUAL_CORE)
+#define __HAL_RCC_WWDG2_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_WWDG2EN)   != 0U)
+#endif /*DUAL_CORE*/
+#define __HAL_RCC_SPI2_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN)    != 0U)
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN)    != 0U)
+#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED()         ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) != 0U)
+#define __HAL_RCC_USART2_IS_CLK_ENABLED()          ((RCC->APB1LENR & RCC_APB1LENR_USART2EN)  != 0U)
+#define __HAL_RCC_USART3_IS_CLK_ENABLED()          ((RCC->APB1LENR & RCC_APB1LENR_USART3EN)  != 0U)
+#define __HAL_RCC_UART4_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_UART4EN)   != 0U)
+#define __HAL_RCC_UART5_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_UART5EN)   != 0U)
+#define __HAL_RCC_I2C1_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN)    != 0U)
+#define __HAL_RCC_I2C2_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN)    != 0U)
+#define __HAL_RCC_I2C3_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN)    != 0U)
+#define __HAL_RCC_CEC_IS_CLK_ENABLED()             ((RCC->APB1LENR & RCC_APB1LENR_CECEN)     != 0U)
+#define __HAL_RCC_DAC12_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN)   != 0U)
+#define __HAL_RCC_UART7_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_UART7EN)   != 0U)
+#define __HAL_RCC_UART8_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_UART8EN)   != 0U)
+#define __HAL_RCC_CRS_IS_CLK_ENABLED()             ((RCC->APB1HENR & RCC_APB1HENR_CRSEN)     != 0U)
+#define __HAL_RCC_SWPMI1_IS_CLK_ENABLED()          ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN)   != 0U)
+#define __HAL_RCC_OPAMP_IS_CLK_ENABLED()           ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN)   != 0U)
+#define __HAL_RCC_MDIOS_IS_CLK_ENABLED()           ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN)   != 0U)
+#define __HAL_RCC_FDCAN_IS_CLK_ENABLED()           ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN)   != 0U)
+
+#define __HAL_RCC_TIM2_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN)    == 0U)
+#define __HAL_RCC_TIM3_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN)    == 0U)
+#define __HAL_RCC_TIM4_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN)    == 0U)
+#define __HAL_RCC_TIM5_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN)    == 0U)
+#define __HAL_RCC_TIM6_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN)    == 0U)
+#define __HAL_RCC_TIM7_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN)    == 0U)
+#define __HAL_RCC_TIM12_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN)   == 0U)
+#define __HAL_RCC_TIM13_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN)   == 0U)
+#define __HAL_RCC_TIM14_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN)   == 0U)
+#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED()         ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN)  == 0U)
+#if defined(DUAL_CORE)
+#define __HAL_RCC_WWDG2_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_WWDG2EN)   == 0U)
+#endif /*DUAL_CORE*/
+#define __HAL_RCC_SPI2_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN)    == 0U)
+#define __HAL_RCC_SPI3_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN)    == 0U)
+#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED()        ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) == 0U)
+#define __HAL_RCC_USART2_IS_CLK_DISABLED()         ((RCC->APB1LENR & RCC_APB1LENR_USART2EN)  == 0U)
+#define __HAL_RCC_USART3_IS_CLK_DISABLED()         ((RCC->APB1LENR & RCC_APB1LENR_USART3EN)  == 0U)
+#define __HAL_RCC_UART4_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_UART4EN)   == 0U)
+#define __HAL_RCC_UART5_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_UART5EN)   == 0U)
+#define __HAL_RCC_I2C1_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN)    == 0U)
+#define __HAL_RCC_I2C2_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN)    == 0U)
+#define __HAL_RCC_I2C3_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN)    == 0U)
+#define __HAL_RCC_CEC_IS_CLK_DISABLED()            ((RCC->APB1LENR & RCC_APB1LENR_CECEN)     == 0U)
+#define __HAL_RCC_DAC12_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN)   == 0U)
+#define __HAL_RCC_UART7_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_UART7EN)   == 0U)
+#define __HAL_RCC_UART8_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_UART8EN)   == 0U)
+#define __HAL_RCC_CRS_IS_CLK_DISABLED()            ((RCC->APB1HENR & RCC_APB1HENR_CRSEN)     == 0U)
+#define __HAL_RCC_SWPMI1_IS_CLK_DISABLED()         ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN)   == 0U)
+#define __HAL_RCC_OPAMP_IS_CLK_DISABLED()          ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN)   == 0U)
+#define __HAL_RCC_MDIOS_IS_CLK_DISABLED()          ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN)   == 0U)
+#define __HAL_RCC_FDCAN_IS_CLK_DISABLED()          ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN)   == 0U)
+
+
+/** @brief  Enable or disable the APB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_TIM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM8_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_USART1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_USART6_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(UART9)
+#define __HAL_RCC_UART9_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /*UART9*/
+
+#if defined(USART10)
+#define __HAL_RCC_USART10_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART10EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART10EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /*USART10*/
+
+#define __HAL_RCC_SPI1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_SPI4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM15_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM16_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM17_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_SPI5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_SAI1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_SAI2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(SAI3)
+#define __HAL_RCC_SAI3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /*SAI3*/
+
+#define __HAL_RCC_DFSDM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /*HRTIM1*/
+
+#define __HAL_RCC_TIM1_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)
+#define __HAL_RCC_TIM8_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)
+#define __HAL_RCC_USART1_CLK_DISABLE()         (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)
+#define __HAL_RCC_USART6_CLK_DISABLE()         (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)
+#if defined(UART9)
+#define __HAL_RCC_UART9_CLK_DISABLE()          (RCC->APB2ENR) &= ~ (RCC_APB2ENR_UART9EN)
+#endif /*UART9*/
+#if defined(USART10)
+#define __HAL_RCC_USART10_CLK_DISABLE()        (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART10EN)
+#endif /*USART10*/
+#define __HAL_RCC_SPI1_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)
+#define __HAL_RCC_SPI4_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)
+#define __HAL_RCC_TIM15_CLK_DISABLE()          (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)
+#define __HAL_RCC_TIM16_CLK_DISABLE()          (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)
+#define __HAL_RCC_TIM17_CLK_DISABLE()          (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)
+#define __HAL_RCC_SPI5_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)
+#define __HAL_RCC_SAI1_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)
+#define __HAL_RCC_SAI2_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN)
+#if defined(SAI3)
+#define __HAL_RCC_SAI3_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN)
+#endif /*SAI3*/
+#define __HAL_RCC_DFSDM1_CLK_DISABLE()         (RCC->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_CLK_DISABLE()         (RCC->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN)
+#endif /*HRTIM*/
+
+/** @brief  Get the enable or disable status of the APB2 peripheral clock
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_TIM1_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN)   != 0U)
+#define __HAL_RCC_TIM8_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN)   != 0U)
+#define __HAL_RCC_USART1_IS_CLK_ENABLED()          ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) != 0U)
+#define __HAL_RCC_USART6_IS_CLK_ENABLED()          ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) != 0U)
+#if defined(UART9)
+#define __HAL_RCC_UART9_IS_CLK_ENABLED()           ((RCC->APB2ENR & RCC_APB2ENR_UART9EN) != 0U)
+#endif /*UART9*/
+#if defined(USART10)
+#define __HAL_RCC_USART10_IS_CLK_ENABLED()         ((RCC->APB2ENR & RCC_APB2ENR_USART10EN) != 0U)
+#endif /*USART10*/
+#define __HAL_RCC_SPI1_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN)   != 0U)
+#define __HAL_RCC_SPI4_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN)   != 0U)
+#define __HAL_RCC_TIM15_IS_CLK_ENABLED()           ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN)  != 0U)
+#define __HAL_RCC_TIM16_IS_CLK_ENABLED()           ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN)  != 0U)
+#define __HAL_RCC_TIM17_IS_CLK_ENABLED()           ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN)  != 0U)
+#define __HAL_RCC_SPI5_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN)   != 0U)
+#define __HAL_RCC_SAI1_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN)   != 0U)
+#define __HAL_RCC_SAI2_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN)   != 0U)
+#if defined(SAI3)
+#define __HAL_RCC_SAI3_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_SAI3EN)   != 0U)
+#endif /* SAI3 */
+#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED()          ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) != 0U)
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_IS_CLK_ENABLED()          ((RCC->APB2ENR & RCC_APB2ENR_HRTIMEN)  != 0U)
+#endif /*HRTIM1*/
+
+#define __HAL_RCC_TIM1_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN)   == 0U)
+#define __HAL_RCC_TIM8_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN)   == 0U)
+#define __HAL_RCC_USART1_IS_CLK_DISABLED()         ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) == 0U)
+#define __HAL_RCC_USART6_IS_CLK_DISABLED()         ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) == 0U)
+#if defined(UART9)
+#define __HAL_RCC_UART9_IS_CLK_DISABLED()         ((RCC->APB2ENR & RCC_APB2ENR_UART9EN) == 0U)
+#endif /*UART9*/
+#if defined(USART10)
+#define __HAL_RCC_USART10_IS_CLK_DISABLED()         ((RCC->APB2ENR & RCC_APB2ENR_USART10EN) == 0U)
+#endif /*USART10*/
+#define __HAL_RCC_SPI1_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN)   == 0U)
+#define __HAL_RCC_SPI4_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN)   == 0U)
+#define __HAL_RCC_TIM15_IS_CLK_DISABLED()          ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN)  == 0U)
+#define __HAL_RCC_TIM16_IS_CLK_DISABLED()          ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN)  == 0U)
+#define __HAL_RCC_TIM17_IS_CLK_DISABLED()          ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN)  == 0U)
+#define __HAL_RCC_SPI5_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN)   == 0U)
+#define __HAL_RCC_SAI1_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN)   == 0U)
+#define __HAL_RCC_SAI2_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN)   == 0U)
+#if defined(SAI3)
+#define __HAL_RCC_SAI3_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_SAI3EN)   == 0U)
+#endif /*SAI3*/
+#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED()         ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) == 0U)
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_IS_CLK_DISABLED()         ((RCC->APB2ENR & RCC_APB2ENR_HRTIMEN)  == 0U)
+#endif /*HRTIM1*/
+
+/** @brief  Enable or disable the APB4 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_SYSCFG_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_LPUART1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_SPI6_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_I2C4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_LPTIM2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_LPTIM3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* LPTIM4 */
+
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* LPTIM5 */
+
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DAC2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DAC2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /*  DAC2 */
+
+#define __HAL_RCC_COMP12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_VREF_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SAI4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SAI4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* SAI4 */
+
+#define __HAL_RCC_RTC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(DTS)
+#define __HAL_RCC_DTS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DTSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DTSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /*DTS*/
+
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DFSDM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DFSDM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /*DFSDM2*/
+
+#define __HAL_RCC_SYSCFG_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN)
+#define __HAL_RCC_LPUART1_CLK_DISABLE()          (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN)
+#define __HAL_RCC_SPI6_CLK_DISABLE()             (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN)
+#define __HAL_RCC_I2C4_CLK_DISABLE()             (RCC->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN)
+#define __HAL_RCC_LPTIM2_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN)
+#define __HAL_RCC_LPTIM3_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN)
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN)
+#endif /*LPTIM4*/
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN)
+#endif /*LPTIM5*/
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_CLK_DISABLE()             (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DAC2EN)
+#endif /*DAC2*/
+#define __HAL_RCC_COMP12_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN)
+#define __HAL_RCC_VREF_CLK_DISABLE()             (RCC->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN)
+#define __HAL_RCC_RTC_CLK_DISABLE()              (RCC->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN)
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_CLK_DISABLE()             (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN)
+#endif /*SAI4*/
+#if defined(DTS)
+#define __HAL_RCC_DTS_CLK_DISABLE()              (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DTSEN)
+#endif /*DTS*/
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DFSDM2EN)
+#endif /*DFSDM2*/
+
+/** @brief  Get the enable or disable status of the APB4 peripheral clock
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED()            ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN)  != 0U)
+#define __HAL_RCC_LPUART1_IS_CLK_ENABLED()           ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) != 0U)
+#define __HAL_RCC_SPI6_IS_CLK_ENABLED()              ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN)    != 0U)
+#define __HAL_RCC_I2C4_IS_CLK_ENABLED()              ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN)    != 0U)
+#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED()            ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN)  != 0U)
+#define __HAL_RCC_LPTIM3_IS_CLK_ENABLED()            ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN)  != 0U)
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_IS_CLK_ENABLED()            ((RCC->APB4ENR & RCC_APB4ENR_LPTIM4EN)  != 0U)
+#endif /*LPTIM4*/
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_IS_CLK_ENABLED()            ((RCC->APB4ENR & RCC_APB4ENR_LPTIM5EN)  != 0U)
+#endif /*LPTIM5*/
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_IS_CLK_ENABLED()              ((RCC->APB4ENR & RCC_APB4ENR_DAC2EN)  != 0U)
+#endif /*DAC2*/
+#define __HAL_RCC_COMP12_IS_CLK_ENABLED()            ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN)  != 0U)
+#define __HAL_RCC_VREF_IS_CLK_ENABLED()              ((RCC->APB4ENR & RCC_APB4ENR_VREFEN)    != 0U)
+#define __HAL_RCC_RTC_IS_CLK_ENABLED()               ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN)  != 0U)
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_IS_CLK_ENABLED()              ((RCC->APB4ENR & RCC_APB4ENR_SAI4EN)    != 0U)
+#endif /*SAI4*/
+#if defined(DTS)
+#define __HAL_RCC_DTS_IS_CLK_ENABLED()               ((RCC->APB4ENR & RCC_APB4ENR_DTSEN)    != 0U)
+#endif /*DTS*/
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_IS_CLK_ENABLED()              ((RCC->APB4ENR & RCC_APB4ENR_DFSDM2EN)    != 0U)
+#endif /*DFSDM2*/
+
+#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED()           ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN)  == 0U)
+#define __HAL_RCC_LPUART1_IS_CLK_DISABLED()          ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) == 0U)
+#define __HAL_RCC_SPI6_IS_CLK_DISABLED()             ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN)    == 0U)
+#define __HAL_RCC_I2C4_IS_CLK_DISABLED()             ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN)    == 0U)
+#define __HAL_RCC_LPTIM2_IS_CLK_DISABLED()           ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN)  == 0U)
+#define __HAL_RCC_LPTIM3_IS_CLK_DISABLED()           ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN)  == 0U)
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_IS_CLK_DISABLED()           ((RCC->APB4ENR & RCC_APB4ENR_LPTIM4EN)  == 0U)
+#endif /*LPTIM4*/
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_IS_CLK_DISABLED()           ((RCC->APB4ENR & RCC_APB4ENR_LPTIM5EN)  == 0U)
+#endif /*LPTIM5*/
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_IS_CLK_DISABLED()             ((RCC->APB4ENR & RCC_APB4ENR_DAC2EN)  == 0U)
+#endif /*DAC2*/
+#define __HAL_RCC_COMP12_IS_CLK_DISABLED()           ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN)  == 0U)
+#define __HAL_RCC_VREF_IS_CLK_DISABLED()             ((RCC->APB4ENR & RCC_APB4ENR_VREFEN)    == 0U)
+#define __HAL_RCC_RTC_IS_CLK_DISABLED()              ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN)  == 0U)
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_IS_CLK_DISABLED()             ((RCC->APB4ENR & RCC_APB4ENR_SAI4EN)    == 0U)
+#endif /*SAI4*/
+#if defined(DTS)
+#define __HAL_RCC_DTS_IS_CLK_DISABLED()              ((RCC->APB4ENR & RCC_APB4ENR_DTSEN)    == 0U)
+#endif /*DTS*/
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_IS_CLK_DISABLED()          ((RCC->APB4ENR & RCC_APB4ENR_DFSDM2EN)    == 0U)
+#endif /*DFSDM2*/
+
+#if defined(DUAL_CORE)
+
+/* Exported macros for RCC_C1 -------------------------------------------------*/
+
+/** @brief  Enable or disable the AHB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C1_MDMA_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_DMA2D_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_JPGDECEN_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_C1_FMC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_QSPI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SDMMC1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+
+
+#define __HAL_RCC_C1_MDMA_CLK_DISABLE()            (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN))
+#define __HAL_RCC_C1_DMA2D_CLK_DISABLE()           (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN))
+#define __HAL_RCC_C1_JPGDECEN_CLK_DISABLE()        (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN))
+#define __HAL_RCC_C1_FMC_CLK_DISABLE()             (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))
+#define __HAL_RCC_C1_QSPI_CLK_DISABLE()            (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN))
+#define __HAL_RCC_C1_SDMMC1_CLK_DISABLE()          (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN))
+
+
+
+
+/** @brief  Enable or disable the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C1_DMA1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_DMA2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_ADC12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_ART_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ARTEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ARTEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_ETH1MAC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_ETH1TX_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_ETH1RX_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_C1_USB1_OTG_HS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_USB2_OTG_FS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_DMA1_CLK_DISABLE()             (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN))
+#define __HAL_RCC_C1_DMA2_CLK_DISABLE()             (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN))
+#define __HAL_RCC_C1_ADC12_CLK_DISABLE()            (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN))
+#define __HAL_RCC_C1_ART_CLK_DISABLE()              (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN))
+#define __HAL_RCC_C1_ETH1MAC_CLK_DISABLE()          (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN))
+#define __HAL_RCC_C1_ETH1TX_CLK_DISABLE()           (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN))
+#define __HAL_RCC_C1_ETH1RX_CLK_DISABLE()           (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN))
+#define __HAL_RCC_C1_USB1_OTG_HS_CLK_DISABLE()      (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN))
+#define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN))
+#define __HAL_RCC_C1_USB2_OTG_FS_CLK_DISABLE()      (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN))
+#define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN))
+
+/** @brief  Enable or disable the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C1_DCMI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#if defined(CRYP)
+#define __HAL_RCC_C1_CRYP_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* CRYP */
+
+#if defined(HASH)
+#define __HAL_RCC_C1_HASH_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* HASH */
+
+#define __HAL_RCC_C1_RNG_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SDMMC2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_D2SRAM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_D2SRAM2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_D2SRAM3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_DCMI_CLK_DISABLE()             (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))
+#if defined(CRYP)
+#define __HAL_RCC_C1_CRYP_CLK_DISABLE()             (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_C1_HASH_CLK_DISABLE()             (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))
+#endif /* HASH */
+#define __HAL_RCC_C1_RNG_CLK_DISABLE()              (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))
+#define __HAL_RCC_C1_SDMMC2_CLK_DISABLE()           (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))
+#define __HAL_RCC_C1_D2SRAM1_CLK_DISABLE()          (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN))
+#define __HAL_RCC_C1_D2SRAM2_CLK_DISABLE()          (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN))
+#define __HAL_RCC_C1_D2SRAM3_CLK_DISABLE()          (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN))
+
+/** @brief  Enable or disable the AHB4 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C1_GPIOA_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_GPIOB_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_GPIOC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_GPIOD_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_GPIOE_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_GPIOF_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_GPIOG_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_GPIOH_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_GPIOI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_GPIOJ_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_GPIOK_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_CRC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_CRCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_CRCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_BDMA_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_ADC3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_HSEM_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_BKPRAM_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_C1_GPIOA_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN)
+#define __HAL_RCC_C1_GPIOB_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN)
+#define __HAL_RCC_C1_GPIOC_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN)
+#define __HAL_RCC_C1_GPIOD_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN)
+#define __HAL_RCC_C1_GPIOE_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN)
+#define __HAL_RCC_C1_GPIOF_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN)
+#define __HAL_RCC_C1_GPIOG_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN)
+#define __HAL_RCC_C1_GPIOH_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN)
+#define __HAL_RCC_C1_GPIOI_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN)
+#define __HAL_RCC_C1_GPIOJ_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN)
+#define __HAL_RCC_C1_GPIOK_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN)
+#define __HAL_RCC_C1_CRC_CLK_DISABLE()             (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN)
+#define __HAL_RCC_C1_BDMA_CLK_DISABLE()            (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN)
+#define __HAL_RCC_C1_ADC3_CLK_DISABLE()            (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN)
+#define __HAL_RCC_C1_HSEM_CLK_DISABLE()            (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN)
+#define __HAL_RCC_C1_BKPRAM_CLK_DISABLE()          (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN)
+
+
+/** @brief  Enable or disable the APB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C1_LTDC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_LTDCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_LTDCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_DSI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_DSIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_DSIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_WWDG1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_WWDG1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_WWDG1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_LTDC_CLK_DISABLE()           (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN)
+#define __HAL_RCC_C1_DSI_CLK_DISABLE()            (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN)
+#define __HAL_RCC_C1_WWDG1_CLK_DISABLE()          (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN)
+
+/** @brief  Enable or disable the APB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C1_TIM2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM6_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM6EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM6EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM7_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM7EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM7EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM13_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM13EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM13EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM14_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM14EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM14EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_LPTIM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_WWDG2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_WWDG2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_WWDG2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SPI2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SPI3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SPDIFRX_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_USART2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_USART3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_UART4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_UART5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_I2C1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_I2C2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_I2C3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_CEC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_CECEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_CECEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_DAC12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_DAC12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_DAC12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_UART7_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART7EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART7EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_UART8_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART8EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART8EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_CRS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_CRSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_CRSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SWPMI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_SWPMIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_SWPMIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_OPAMP_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_OPAMPEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_OPAMPEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_MDIOS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_MDIOSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_MDIOSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_FDCAN_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_FDCANEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_FDCANEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_C1_TIM2_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN)
+#define __HAL_RCC_C1_TIM3_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN)
+#define __HAL_RCC_C1_TIM4_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN)
+#define __HAL_RCC_C1_TIM5_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN)
+#define __HAL_RCC_C1_TIM6_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN)
+#define __HAL_RCC_C1_TIM7_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN)
+#define __HAL_RCC_C1_TIM12_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN)
+#define __HAL_RCC_C1_TIM13_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN)
+#define __HAL_RCC_C1_TIM14_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN)
+#define __HAL_RCC_C1_LPTIM1_CLK_DISABLE()         (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN)
+#define __HAL_RCC_C1_WWDG2_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN)
+#define __HAL_RCC_C1_SPI2_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN)
+#define __HAL_RCC_C1_SPI3_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN)
+#define __HAL_RCC_C1_SPDIFRX_CLK_DISABLE()        (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN)
+#define __HAL_RCC_C1_USART2_CLK_DISABLE()         (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN)
+#define __HAL_RCC_C1_USART3_CLK_DISABLE()         (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN)
+#define __HAL_RCC_C1_UART4_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN)
+#define __HAL_RCC_C1_UART5_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN)
+#define __HAL_RCC_C1_I2C1_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN)
+#define __HAL_RCC_C1_I2C2_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN)
+#define __HAL_RCC_C1_I2C3_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN)
+#define __HAL_RCC_C1_CEC_CLK_DISABLE()            (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_CECEN)
+#define __HAL_RCC_C1_DAC12_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN)
+#define __HAL_RCC_C1_UART7_CLK_DISABLE()         (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN)
+#define __HAL_RCC_C1_UART8_CLK_DISABLE()         (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN)
+#define __HAL_RCC_C1_CRS_CLK_DISABLE()            (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN)
+#define __HAL_RCC_C1_SWPMI_CLK_DISABLE()          (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN)
+#define __HAL_RCC_C1_OPAMP_CLK_DISABLE()          (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN)
+#define __HAL_RCC_C1_MDIOS_CLK_DISABLE()          (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN)
+#define __HAL_RCC_C1_FDCAN_CLK_DISABLE()          (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN)
+
+/** @brief  Enable or disable the APB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C1_TIM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM8_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM8EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM8EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_USART1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_USART6_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART6EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART6EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SPI1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SPI4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM15_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM15EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM15EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM16_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM16EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM16EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM17_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM17EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM17EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SPI5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SAI1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SAI2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SAI3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_DFSDM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_HRTIM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_HRTIMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_HRTIMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM1_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)
+#define __HAL_RCC_C1_TIM8_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)
+#define __HAL_RCC_C1_USART1_CLK_DISABLE()         (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)
+#define __HAL_RCC_C1_USART6_CLK_DISABLE()         (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)
+#define __HAL_RCC_C1_SPI1_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)
+#define __HAL_RCC_C1_SPI4_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)
+#define __HAL_RCC_C1_TIM15_CLK_DISABLE()          (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)
+#define __HAL_RCC_C1_TIM16_CLK_DISABLE()          (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)
+#define __HAL_RCC_C1_TIM17_CLK_DISABLE()          (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)
+#define __HAL_RCC_C1_SPI5_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)
+#define __HAL_RCC_C1_SAI1_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)
+#define __HAL_RCC_C1_SAI2_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN)
+#define __HAL_RCC_C1_SAI3_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN)
+#define __HAL_RCC_C1_DFSDM1_CLK_DISABLE()         (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)
+#define __HAL_RCC_C1_HRTIM1_CLK_DISABLE()         (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN)
+
+/** @brief  Enable or disable the APB4 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C1_SYSCFG_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_LPUART1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPUART1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPUART1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SPI6_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SPI6EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SPI6EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_I2C4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_I2C4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_I2C4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_LPTIM2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_LPTIM3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_LPTIM4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_LPTIM5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_COMP12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_COMP12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_COMP12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_C1_VREF_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_VREFEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_VREFEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_RTC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SAI4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SAI4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SAI4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_C1_SYSCFG_CLK_DISABLE()           (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN)
+#define __HAL_RCC_C1_LPUART1_CLK_DISABLE()          (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN)
+#define __HAL_RCC_C1_SPI6_CLK_DISABLE()             (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN)
+#define __HAL_RCC_C1_I2C4_CLK_DISABLE()             (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN)
+#define __HAL_RCC_C1_LPTIM2_CLK_DISABLE()           (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN)
+#define __HAL_RCC_C1_LPTIM3_CLK_DISABLE()           (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN)
+#define __HAL_RCC_C1_LPTIM4_CLK_DISABLE()           (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN)
+#define __HAL_RCC_C1_LPTIM5_CLK_DISABLE()           (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN)
+#define __HAL_RCC_C1_COMP12_CLK_DISABLE()           (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN)
+#define __HAL_RCC_C1_VREF_CLK_DISABLE()             (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN)
+#define __HAL_RCC_C1_RTC_CLK_DISABLE()              (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN)
+#define __HAL_RCC_C1_SAI4_CLK_DISABLE()             (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN)
+
+/* Exported macros for RCC_C2 -------------------------------------------------*/
+
+/** @brief  Enable or disable the AHB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+
+#define __HAL_RCC_C2_MDMA_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_DMA2D_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_JPGDECEN_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_FLASH_C2_ALLOCATE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FLASHEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FLASHEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_DTCM1_C2_ALLOCATE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_DTCM2_C2_ALLOCATE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_ITCM_C2_ALLOCATE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_ITCMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_ITCMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_D1SRAM1_C2_ALLOCATE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_AXISRAMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_AXISRAMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_FMC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_QSPI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SDMMC1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+
+
+#define __HAL_RCC_C2_MDMA_CLK_DISABLE()            (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN))
+#define __HAL_RCC_C2_DMA2D_CLK_DISABLE()           (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN))
+#define __HAL_RCC_C2_JPGDECEN_CLK_DISABLE()        (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN))
+#define __HAL_RCC_C2_FMC_CLK_DISABLE()             (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))
+#define __HAL_RCC_C2_QSPI_CLK_DISABLE()            (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN))
+#define __HAL_RCC_C2_SDMMC1_CLK_DISABLE()          (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN))
+#define __HAL_RCC_FLASH_C2_DEALLOCATE()            (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_FLASHEN))
+#define __HAL_RCC_DTCM1_C2_DEALLOCATE()            (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DTCM1EN))
+#define __HAL_RCC_DTCM2_C2_DEALLOCATE()            (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DTCM2EN))
+#define __HAL_RCC_ITCM_C2_DEALLOCATE()             (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_ITCMEN))
+#define __HAL_RCC_D1SRAM1_C2_DEALLOCATE()          (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_AXISRAMEN))
+
+/** @brief  Enable or disable the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C2_DMA1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_DMA2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_ADC12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_ART_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ARTEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ARTEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_ETH1MAC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_ETH1TX_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_ETH1RX_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_USB1_OTG_HS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_USB2_OTG_FS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_C2_DMA1_CLK_DISABLE()             (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN))
+#define __HAL_RCC_C2_DMA2_CLK_DISABLE()             (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN))
+#define __HAL_RCC_C2_ADC12_CLK_DISABLE()            (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN))
+#define __HAL_RCC_C2_ART_CLK_DISABLE()              (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN))
+#define __HAL_RCC_C2_ETH1MAC_CLK_DISABLE()          (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN))
+#define __HAL_RCC_C2_ETH1TX_CLK_DISABLE()           (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN))
+#define __HAL_RCC_C2_ETH1RX_CLK_DISABLE()           (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN))
+#define __HAL_RCC_C2_USB1_OTG_HS_CLK_DISABLE()      (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN))
+#define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN))
+#define __HAL_RCC_C2_USB2_OTG_FS_CLK_DISABLE()      (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN))
+#define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN))
+
+/** @brief  Enable or disable the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C2_DCMI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(CRYP)
+#define __HAL_RCC_C2_CRYP_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* CRYP */
+
+#if defined(HASH)
+#define __HAL_RCC_C2_HASH_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* HASH */
+
+#define __HAL_RCC_C2_RNG_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SDMMC2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_D2SRAM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_D2SRAM2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_D2SRAM3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_DCMI_CLK_DISABLE()             (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))
+#if defined(CRYP)
+#define __HAL_RCC_C2_CRYP_CLK_DISABLE()             (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_C2_HASH_CLK_DISABLE()             (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))
+#endif /* HASH */
+#define __HAL_RCC_C2_RNG_CLK_DISABLE()              (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))
+#define __HAL_RCC_C2_SDMMC2_CLK_DISABLE()           (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))
+#define __HAL_RCC_C2_D2SRAM1_CLK_DISABLE()          (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN))
+#define __HAL_RCC_C2_D2SRAM2_CLK_DISABLE()          (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN))
+#define __HAL_RCC_C2_D2SRAM3_CLK_DISABLE()          (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN))
+
+/** @brief  Enable or disable the AHB4 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C2_GPIOA_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_GPIOB_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_GPIOC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_GPIOD_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_GPIOE_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_GPIOF_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_GPIOG_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_GPIOH_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_GPIOI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_GPIOJ_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_GPIOK_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_CRC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_CRCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_CRCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_BDMA_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_ADC3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_HSEM_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_BKPRAM_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_C2_GPIOA_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN)
+#define __HAL_RCC_C2_GPIOB_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN)
+#define __HAL_RCC_C2_GPIOC_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN)
+#define __HAL_RCC_C2_GPIOD_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN)
+#define __HAL_RCC_C2_GPIOE_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN)
+#define __HAL_RCC_C2_GPIOF_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN)
+#define __HAL_RCC_C2_GPIOG_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN)
+#define __HAL_RCC_C2_GPIOH_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN)
+#define __HAL_RCC_C2_GPIOI_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN)
+#define __HAL_RCC_C2_GPIOJ_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN)
+#define __HAL_RCC_C2_GPIOK_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN)
+#define __HAL_RCC_C2_CRC_CLK_DISABLE()             (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN)
+#define __HAL_RCC_C2_BDMA_CLK_DISABLE()            (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN)
+#define __HAL_RCC_C2_ADC3_CLK_DISABLE()            (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN)
+#define __HAL_RCC_C2_HSEM_CLK_DISABLE()            (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN)
+#define __HAL_RCC_C2_BKPRAM_CLK_DISABLE()          (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN)
+
+
+/** @brief  Enable or disable the APB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C2_LTDC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_LTDCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_LTDCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_DSI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_DSIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_DSIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_WWDG1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_WWDG1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_WWDG1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_LTDC_CLK_DISABLE()           (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN)
+#define __HAL_RCC_C2_DSI_CLK_DISABLE()            (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN)
+#define __HAL_RCC_C2_WWDG1_CLK_DISABLE()          (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN)
+
+/** @brief  Enable or disable the APB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C2_TIM2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM6_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM6EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM6EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM7_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM7EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM7EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM13_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM13EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM13EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM14_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM14EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM14EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_LPTIM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_WWDG2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_WWDG2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_WWDG2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SPI2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SPI3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SPDIFRX_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_USART2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_USART3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_UART4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_UART5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_I2C1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_I2C2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_I2C3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_CEC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_CECEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_CECEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_DAC12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_DAC12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_DAC12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_UART7_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART7EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART7EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_UART8_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART8EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART8EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_CRS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_CRSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_CRSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SWPMI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_SWPMIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_SWPMIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_OPAMP_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_OPAMPEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_OPAMPEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_MDIOS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_MDIOSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_MDIOSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_FDCAN_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_FDCANEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_FDCANEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_C2_TIM2_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN)
+#define __HAL_RCC_C2_TIM3_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN)
+#define __HAL_RCC_C2_TIM4_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN)
+#define __HAL_RCC_C2_TIM5_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN)
+#define __HAL_RCC_C2_TIM6_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN)
+#define __HAL_RCC_C2_TIM7_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN)
+#define __HAL_RCC_C2_TIM12_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN)
+#define __HAL_RCC_C2_TIM13_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN)
+#define __HAL_RCC_C2_TIM14_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN)
+#define __HAL_RCC_C2_LPTIM1_CLK_DISABLE()         (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN)
+#define __HAL_RCC_C2_WWDG2_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN)
+#define __HAL_RCC_C2_SPI2_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN)
+#define __HAL_RCC_C2_SPI3_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN)
+#define __HAL_RCC_C2_SPDIFRX_CLK_DISABLE()        (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN)
+#define __HAL_RCC_C2_USART2_CLK_DISABLE()         (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN)
+#define __HAL_RCC_C2_USART3_CLK_DISABLE()         (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN)
+#define __HAL_RCC_C2_UART4_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN)
+#define __HAL_RCC_C2_UART5_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN)
+#define __HAL_RCC_C2_I2C1_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN)
+#define __HAL_RCC_C2_I2C2_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN)
+#define __HAL_RCC_C2_I2C3_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN)
+#define __HAL_RCC_C2_CEC_CLK_DISABLE()            (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_CECEN)
+#define __HAL_RCC_C2_DAC12_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN)
+#define __HAL_RCC_C2_UART7_CLK_DISABLE()         (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN)
+#define __HAL_RCC_C2_UART8_CLK_DISABLE()         (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN)
+#define __HAL_RCC_C2_CRS_CLK_DISABLE()            (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN)
+#define __HAL_RCC_C2_SWPMI_CLK_DISABLE()          (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN)
+#define __HAL_RCC_C2_OPAMP_CLK_DISABLE()          (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN)
+#define __HAL_RCC_C2_MDIOS_CLK_DISABLE()          (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN)
+#define __HAL_RCC_C2_FDCAN_CLK_DISABLE()          (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN)
+
+/** @brief  Enable or disable the APB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C2_TIM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM8_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM8EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM8EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_USART1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_USART6_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART6EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART6EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SPI1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SPI4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM15_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM15EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM15EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM16_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM16EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM16EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM17_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM17EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM17EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SPI5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SAI1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SAI2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SAI3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_DFSDM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_HRTIM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_HRTIMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_HRTIMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM1_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)
+#define __HAL_RCC_C2_TIM8_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)
+#define __HAL_RCC_C2_USART1_CLK_DISABLE()         (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)
+#define __HAL_RCC_C2_USART6_CLK_DISABLE()         (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)
+#define __HAL_RCC_C2_SPI1_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)
+#define __HAL_RCC_C2_SPI4_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)
+#define __HAL_RCC_C2_TIM15_CLK_DISABLE()          (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)
+#define __HAL_RCC_C2_TIM16_CLK_DISABLE()          (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)
+#define __HAL_RCC_C2_TIM17_CLK_DISABLE()          (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)
+#define __HAL_RCC_C2_SPI5_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)
+#define __HAL_RCC_C2_SAI1_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)
+#define __HAL_RCC_C2_SAI2_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN)
+#define __HAL_RCC_C2_SAI3_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN)
+#define __HAL_RCC_C2_DFSDM1_CLK_DISABLE()         (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)
+#define __HAL_RCC_C2_HRTIM1_CLK_DISABLE()         (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN)
+
+/** @brief  Enable or disable the APB4 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C2_SYSCFG_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_LPUART1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPUART1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPUART1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SPI6_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SPI6EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SPI6EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_I2C4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_I2C4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_I2C4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_LPTIM2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_LPTIM3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_LPTIM4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_LPTIM5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_COMP12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_COMP12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_COMP12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_VREF_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_VREFEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_VREFEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_RTC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SAI4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SAI4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SAI4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+
+#define __HAL_RCC_C2_SYSCFG_CLK_DISABLE()           (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN)
+#define __HAL_RCC_C2_LPUART1_CLK_DISABLE()          (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN)
+#define __HAL_RCC_C2_SPI6_CLK_DISABLE()             (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN)
+#define __HAL_RCC_C2_I2C4_CLK_DISABLE()             (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN)
+#define __HAL_RCC_C2_LPTIM2_CLK_DISABLE()           (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN)
+#define __HAL_RCC_C2_LPTIM3_CLK_DISABLE()           (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN)
+#define __HAL_RCC_C2_LPTIM4_CLK_DISABLE()           (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN)
+#define __HAL_RCC_C2_LPTIM5_CLK_DISABLE()           (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN)
+#define __HAL_RCC_C2_COMP12_CLK_DISABLE()           (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN)
+#define __HAL_RCC_C2_VREF_CLK_DISABLE()             (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN)
+#define __HAL_RCC_C2_RTC_CLK_DISABLE()              (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN)
+#define __HAL_RCC_C2_SAI4_CLK_DISABLE()             (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN)
+
+#endif /*DUAL_CORE*/
+
+/** @brief  Enable or disable the AHB3 peripheral reset.
+  */
+
+#define __HAL_RCC_AHB3_FORCE_RESET()          (RCC->AHB3RSTR = 0x7FFFFFFFU)
+#define __HAL_RCC_MDMA_FORCE_RESET()          (RCC->AHB3RSTR |= (RCC_AHB3RSTR_MDMARST))
+#define __HAL_RCC_DMA2D_FORCE_RESET()         (RCC->AHB3RSTR |= (RCC_AHB3RSTR_DMA2DRST))
+#if defined(JPEG)
+#define __HAL_RCC_JPGDECRST_FORCE_RESET()     (RCC->AHB3RSTR |= (RCC_AHB3RSTR_JPGDECRST))
+#endif /* JPEG */
+#define __HAL_RCC_FMC_FORCE_RESET()           (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_FORCE_RESET()          (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
+#endif /*QUADSPI*/
+#if defined(OCTOSPI1)
+#define __HAL_RCC_OSPI1_FORCE_RESET()         (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OSPI1RST))
+#endif /*OCTOSPI1*/
+#define __HAL_RCC_SDMMC1_FORCE_RESET()        (RCC->AHB3RSTR |= (RCC_AHB3RSTR_SDMMC1RST))
+#if defined(OCTOSPI2)
+#define __HAL_RCC_OSPI2_FORCE_RESET()         (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OSPI2RST))
+#endif /*OCTOSPI2*/
+#if defined(OCTOSPIM)
+#define __HAL_RCC_IOMNGR_FORCE_RESET()      (RCC->AHB3RSTR |= (RCC_AHB3RSTR_IOMNGRRST))
+#endif /*OCTOSPIM*/
+#if defined(OTFDEC1)
+#define __HAL_RCC_OTFDEC1_FORCE_RESET()         (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OTFDEC1RST))
+#endif /*OTFDEC1*/
+#if defined(OTFDEC2)
+#define __HAL_RCC_OTFDEC2_FORCE_RESET()         (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OTFDEC2RST))
+#endif /*OTFDEC2*/
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_FORCE_RESET()        (RCC->AHB3RSTR |= (RCC_AHB3RSTR_GFXMMURST))
+#endif /*GFXMMU*/
+
+#define __HAL_RCC_AHB3_RELEASE_RESET()        (RCC->AHB3RSTR = 0x00)
+#define __HAL_RCC_MDMA_RELEASE_RESET()        (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_MDMARST))
+#define __HAL_RCC_DMA2D_RELEASE_RESET()       (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_DMA2DRST))
+#if defined(JPEG)
+#define __HAL_RCC_JPGDECRST_RELEASE_RESET()   (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_JPGDECRST))
+#endif /* JPEG */
+#define __HAL_RCC_FMC_RELEASE_RESET()         (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_FMCRST))
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_RELEASE_RESET()        (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_QSPIRST))
+#endif /*QUADSPI*/
+#if defined(OCTOSPI1)
+#define __HAL_RCC_OSPI1_RELEASE_RESET()       (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OSPI1RST))
+#endif /*OCTOSPI1*/
+#define __HAL_RCC_SDMMC1_RELEASE_RESET()      (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_SDMMC1RST))
+#if defined(OCTOSPI2)
+#define __HAL_RCC_OSPI2_RELEASE_RESET()       (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OSPI2RST))
+#endif /*OCTOSPI2*/
+#if defined(OCTOSPIM)
+#define __HAL_RCC_IOMNGR_RELEASE_RESET()      (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_IOMNGRRST))
+#endif /*OCTOSPIM*/
+#if defined(OTFDEC1)
+#define __HAL_RCC_OTFDEC1_RELEASE_RESET()       (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OTFDEC1RST))
+#endif /*OTFDEC1*/
+#if defined(OTFDEC2)
+#define __HAL_RCC_OTFDEC2_RELEASE_RESET()       (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OTFDEC2RST))
+#endif /*OTFDEC2*/
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_RELEASE_RESET()      (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_GFXMMURST))
+#endif /*GFXMMU*/
+
+
+
+/** @brief  Force or release the AHB1 peripheral reset.
+  */
+#define __HAL_RCC_AHB1_FORCE_RESET()             (RCC->AHB1RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_DMA1_FORCE_RESET()             (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
+#define __HAL_RCC_DMA2_FORCE_RESET()             (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
+#define __HAL_RCC_ADC12_FORCE_RESET()            (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ADC12RST))
+#if defined(DUAL_CORE)
+#define __HAL_RCC_ART_FORCE_RESET()              (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ARTRST))
+#endif /*DUAL_CORE*/
+#if defined(RCC_AHB1RSTR_CRCRST)
+#define __HAL_RCC_CRC_FORCE_RESET()            (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
+#endif
+#if defined(ETH)
+#define __HAL_RCC_ETH1MAC_FORCE_RESET()          (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETH1MACRST))
+#endif /*ETH*/
+#define __HAL_RCC_USB1_OTG_HS_FORCE_RESET()      (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB1OTGHSRST))
+#if defined(USB2_OTG_FS)
+#define __HAL_RCC_USB2_OTG_FS_FORCE_RESET()      (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB2OTGHSRST))
+#endif /*USB2_OTG_FS*/
+
+#define __HAL_RCC_AHB1_RELEASE_RESET()           (RCC->AHB1RSTR = 0x00U)
+#define __HAL_RCC_DMA1_RELEASE_RESET()             (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA1RST))
+#define __HAL_RCC_DMA2_RELEASE_RESET()             (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA2RST))
+#define __HAL_RCC_ADC12_RELEASE_RESET()            (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ADC12RST))
+#if defined(DUAL_CORE)
+#define __HAL_RCC_ART_RELEASE_RESET()              (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ARTRST))
+#endif /*DUAL_CORE*/
+#if defined(RCC_AHB1RSTR_CRCRST)
+#define __HAL_RCC_CRC_RELEASE_RESET()                (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_CRCRST))
+#endif
+#if defined(ETH)
+#define __HAL_RCC_ETH1MAC_RELEASE_RESET()          (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ETH1MACRST))
+#endif /*ETH*/
+#define __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()      (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB1OTGHSRST))
+#if defined(USB2_OTG_FS)
+#define __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()      (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB2OTGHSRST))
+#endif /*USB2_OTG_FS*/
+
+/** @brief  Force or release the AHB2 peripheral reset.
+  */
+#define __HAL_RCC_AHB2_FORCE_RESET()           (RCC->AHB2RSTR = 0xFFFFFFFFU)
+#if defined(DCMI) && defined(PSSI)
+#define __HAL_RCC_DCMI_PSSI_FORCE_RESET()        (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMI_PSSIRST))
+#define __HAL_RCC_DCMI_FORCE_RESET()             __HAL_RCC_DCMI_PSSI_FORCE_RESET()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_DCMI_FORCE_RESET()             (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
+#endif /* DCMI && PSSI */
+#if defined(CRYP)
+#define __HAL_RCC_CRYP_FORCE_RESET()             (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_HASH_FORCE_RESET()             (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
+#endif /* HASH */
+#define __HAL_RCC_RNG_FORCE_RESET()              (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
+#define __HAL_RCC_SDMMC2_FORCE_RESET()           (RCC->AHB2RSTR |= (RCC_AHB2RSTR_SDMMC2RST))
+#if defined(RCC_AHB2RSTR_HSEMRST)
+#define __HAL_RCC_HSEM_FORCE_RESET()             (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HSEMRST))
+#endif
+#if defined(BDMA1)
+#define __HAL_RCC_BDMA1_FORCE_RESET()           (RCC->AHB2RSTR |= (RCC_AHB2RSTR_BDMA1RST))
+#endif /*BDMA1*/
+
+#define __HAL_RCC_AHB2_RELEASE_RESET()           (RCC->AHB2RSTR = 0x00U)
+#if defined(DCMI) && defined(PSSI)
+#define __HAL_RCC_DCMI_PSSI_RELEASE_RESET()        (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMI_PSSIRST))
+#define __HAL_RCC_DCMI_RELEASE_RESET()             __HAL_RCC_DCMI_PSSI_RELEASE_RESET()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_DCMI_RELEASE_RESET()             (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMIRST))
+#endif /* DCMI && PSSI */
+#if defined(CRYP)
+#define __HAL_RCC_CRYP_RELEASE_RESET()             (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_CRYPRST))
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_HASH_RELEASE_RESET()             (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HASHRST))
+#endif /* HASH */
+#define __HAL_RCC_RNG_RELEASE_RESET()              (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_RNGRST))
+#define __HAL_RCC_SDMMC2_RELEASE_RESET()           (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_SDMMC2RST))
+#if defined(RCC_AHB2RSTR_HSEMRST)
+#define __HAL_RCC_HSEM_RELEASE_RESET()             (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HSEMRST))
+#endif
+#if defined(BDMA1)
+#define __HAL_RCC_BDMA1_RELEASE_RESET()           (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_BDMA1RST))
+#endif /*BDMA1*/
+
+
+/** @brief  Force or release the AHB4 peripheral reset.
+  */
+
+#define __HAL_RCC_AHB4_FORCE_RESET()            (RCC->AHB4RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_GPIOA_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOARST)
+#define __HAL_RCC_GPIOB_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOBRST)
+#define __HAL_RCC_GPIOC_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOCRST)
+#define __HAL_RCC_GPIOD_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIODRST)
+#define __HAL_RCC_GPIOE_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOERST)
+#define __HAL_RCC_GPIOF_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOFRST)
+#define __HAL_RCC_GPIOG_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOGRST)
+#define __HAL_RCC_GPIOH_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOHRST)
+#define __HAL_RCC_GPIOI_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOIRST)
+#define __HAL_RCC_GPIOJ_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOJRST)
+#define __HAL_RCC_GPIOK_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOKRST)
+#if defined(RCC_AHB4RSTR_CRCRST)
+#define __HAL_RCC_CRC_FORCE_RESET()             (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_CRCRST)
+#endif
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_BDMA2RST)
+#define __HAL_RCC_BDMA_FORCE_RESET()            __HAL_RCC_BDMA2_FORCE_RESET()         /* for API backward compatibility*/
+#else
+#define __HAL_RCC_BDMA_FORCE_RESET()            (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_BDMARST)
+#endif /*BDMA2*/
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_FORCE_RESET()            (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_ADC3RST)
+#endif /*ADC3*/
+#if defined(RCC_AHB4RSTR_HSEMRST)
+#define __HAL_RCC_HSEM_FORCE_RESET()            (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_HSEMRST)
+#endif
+
+#define __HAL_RCC_AHB4_RELEASE_RESET()          (RCC->AHB4RSTR = 0x00U)
+#define __HAL_RCC_GPIOA_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOARST)
+#define __HAL_RCC_GPIOB_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOBRST)
+#define __HAL_RCC_GPIOC_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOCRST)
+#define __HAL_RCC_GPIOD_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIODRST)
+#define __HAL_RCC_GPIOE_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOERST)
+#define __HAL_RCC_GPIOF_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOFRST)
+#define __HAL_RCC_GPIOG_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOGRST)
+#define __HAL_RCC_GPIOH_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOHRST)
+#define __HAL_RCC_GPIOI_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOIRST)
+#define __HAL_RCC_GPIOJ_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOJRST)
+#define __HAL_RCC_GPIOK_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOKRST)
+#if defined(RCC_AHB4RSTR_CRCRST)
+#define __HAL_RCC_CRC_RELEASE_RESET()             (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_CRCRST)
+#endif
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_RELEASE_RESET()            (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_BDMA2RST)
+#define __HAL_RCC_BDMA_RELEASE_RESET()   __HAL_RCC_BDMA2_RELEASE_RESET()      /* for API backward compatibility*/
+#else
+#define __HAL_RCC_BDMA_RELEASE_RESET()            (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_BDMARST)
+#endif /*BDMA2*/
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_RELEASE_RESET()            (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_ADC3RST)
+#endif /*ADC3*/
+#if defined(RCC_AHB4RSTR_HSEMRST)
+#define __HAL_RCC_HSEM_RELEASE_RESET()            (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_HSEMRST)
+#endif
+
+/** @brief  Force or release the APB3 peripheral reset.
+  */
+#define __HAL_RCC_APB3_FORCE_RESET()         (RCC->APB3RSTR = 0xFFFFFFFFU)
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_FORCE_RESET()           (RCC->APB3RSTR) |= (RCC_APB3RSTR_LTDCRST)
+#endif /* LTDC */
+#if defined(DSI)
+#define __HAL_RCC_DSI_FORCE_RESET()            (RCC->APB3RSTR) |= (RCC_APB3RSTR_DSIRST)
+#endif /*DSI*/
+
+#define __HAL_RCC_APB3_RELEASE_RESET()         (RCC->APB3RSTR = 0x00U)
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_RELEASE_RESET()           (RCC->APB3RSTR) &= ~ (RCC_APB3RSTR_LTDCRST)
+#endif /* LTDC */
+#if defined(DSI)
+#define __HAL_RCC_DSI_RELEASE_RESET()            (RCC->APB3RSTR) &= ~ (RCC_APB3RSTR_DSIRST)
+#endif /*DSI*/
+
+/** @brief  Force or release the APB1 peripheral reset.
+  */
+#define __HAL_RCC_APB1L_FORCE_RESET()        (RCC->APB1LRSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_APB1H_FORCE_RESET()        (RCC->APB1HRSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_TIM2_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM2RST)
+#define __HAL_RCC_TIM3_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM3RST)
+#define __HAL_RCC_TIM4_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM4RST)
+#define __HAL_RCC_TIM5_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM5RST)
+#define __HAL_RCC_TIM6_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM6RST)
+#define __HAL_RCC_TIM7_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM7RST)
+#define __HAL_RCC_TIM12_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM12RST)
+#define __HAL_RCC_TIM13_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM13RST)
+#define __HAL_RCC_TIM14_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM14RST)
+#define __HAL_RCC_LPTIM1_FORCE_RESET()         (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_LPTIM1RST)
+#define __HAL_RCC_SPI2_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI2RST)
+#define __HAL_RCC_SPI3_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI3RST)
+#define __HAL_RCC_SPDIFRX_FORCE_RESET()        (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPDIFRXRST)
+#define __HAL_RCC_USART2_FORCE_RESET()         (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART2RST)
+#define __HAL_RCC_USART3_FORCE_RESET()         (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART3RST)
+#define __HAL_RCC_UART4_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART4RST)
+#define __HAL_RCC_UART5_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART5RST)
+#define __HAL_RCC_I2C1_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C1RST)
+#define __HAL_RCC_I2C2_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C2RST)
+#define __HAL_RCC_I2C3_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C3RST)
+#define __HAL_RCC_CEC_FORCE_RESET()            (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_CECRST)
+#define __HAL_RCC_DAC12_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_DAC12RST)
+#define __HAL_RCC_UART7_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART7RST)
+#define __HAL_RCC_UART8_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART8RST)
+#define __HAL_RCC_CRS_FORCE_RESET()            (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_CRSRST)
+#define __HAL_RCC_SWPMI1_FORCE_RESET()          (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_SWPMIRST)
+#define __HAL_RCC_OPAMP_FORCE_RESET()          (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_OPAMPRST)
+#define __HAL_RCC_MDIOS_FORCE_RESET()          (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_MDIOSRST)
+#define __HAL_RCC_FDCAN_FORCE_RESET()          (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_FDCANRST)
+
+#define __HAL_RCC_APB1L_RELEASE_RESET()       (RCC->APB1LRSTR = 0x00U)
+#define __HAL_RCC_APB1H_RELEASE_RESET()       (RCC->APB1HRSTR = 0x00U)
+#define __HAL_RCC_TIM2_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM2RST)
+#define __HAL_RCC_TIM3_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM3RST)
+#define __HAL_RCC_TIM4_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM4RST)
+#define __HAL_RCC_TIM5_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM5RST)
+#define __HAL_RCC_TIM6_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM6RST)
+#define __HAL_RCC_TIM7_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM7RST)
+#define __HAL_RCC_TIM12_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM12RST)
+#define __HAL_RCC_TIM13_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM13RST)
+#define __HAL_RCC_TIM14_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM14RST)
+#define __HAL_RCC_LPTIM1_RELEASE_RESET()         (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_LPTIM1RST)
+#define __HAL_RCC_SPI2_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI2RST)
+#define __HAL_RCC_SPI3_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI3RST)
+#define __HAL_RCC_SPDIFRX_RELEASE_RESET()        (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPDIFRXRST)
+#define __HAL_RCC_USART2_RELEASE_RESET()         (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART2RST)
+#define __HAL_RCC_USART3_RELEASE_RESET()         (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART3RST)
+#define __HAL_RCC_UART4_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART4RST)
+#define __HAL_RCC_UART5_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART5RST)
+#define __HAL_RCC_I2C1_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C1RST)
+#define __HAL_RCC_I2C2_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C2RST)
+#define __HAL_RCC_I2C3_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C3RST)
+#define __HAL_RCC_CEC_RELEASE_RESET()            (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_CECRST)
+#define __HAL_RCC_DAC12_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_DAC12RST)
+#define __HAL_RCC_UART7_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART7RST)
+#define __HAL_RCC_UART8_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART8RST)
+#define __HAL_RCC_CRS_RELEASE_RESET()            (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_CRSRST)
+#define __HAL_RCC_SWPMI1_RELEASE_RESET()          (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_SWPMIRST)
+#define __HAL_RCC_OPAMP_RELEASE_RESET()          (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_OPAMPRST)
+#define __HAL_RCC_MDIOS_RELEASE_RESET()          (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_MDIOSRST)
+#define __HAL_RCC_FDCAN_RELEASE_RESET()          (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_FDCANRST)
+
+/** @brief  Force or release the APB2 peripheral reset.
+  */
+#define __HAL_RCC_APB2_FORCE_RESET()         (RCC->APB2RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_TIM1_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM1RST)
+#define __HAL_RCC_TIM8_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM8RST)
+#define __HAL_RCC_USART1_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART1RST)
+#define __HAL_RCC_USART6_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART6RST)
+#if defined(UART9)
+#define __HAL_RCC_UART9_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_UART9RST)
+#endif /*UART9*/
+#if defined(USART10)
+#define __HAL_RCC_USART10_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART10RST)
+#endif /*USART10*/
+#define __HAL_RCC_SPI1_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI1RST)
+#define __HAL_RCC_SPI4_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI4RST)
+#define __HAL_RCC_TIM15_FORCE_RESET()          (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM15RST)
+#define __HAL_RCC_TIM16_FORCE_RESET()          (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM16RST)
+#define __HAL_RCC_TIM17_FORCE_RESET()          (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM17RST)
+#define __HAL_RCC_SPI5_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI5RST)
+#define __HAL_RCC_SAI1_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI1RST)
+#define __HAL_RCC_SAI2_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI2RST)
+#if defined(SAI3)
+#define __HAL_RCC_SAI3_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI3RST)
+#endif /*SAI3*/
+#define __HAL_RCC_DFSDM1_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_DFSDM1RST)
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_HRTIMRST)
+#endif /*HRTIM1*/
+
+#define __HAL_RCC_APB2_RELEASE_RESET()         (RCC->APB2RSTR = 0x00U)
+#define __HAL_RCC_TIM1_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM1RST)
+#define __HAL_RCC_TIM8_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM8RST)
+#define __HAL_RCC_USART1_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART1RST)
+#define __HAL_RCC_USART6_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART6RST)
+#if defined(UART9)
+#define __HAL_RCC_UART9_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_UART9RST)
+#endif /*UART9*/
+#if defined(USART10)
+#define __HAL_RCC_USART10_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART10RST)
+#endif /*USART10*/
+#define __HAL_RCC_SPI1_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI1RST)
+#define __HAL_RCC_SPI4_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI4RST)
+#define __HAL_RCC_TIM15_RELEASE_RESET()          (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM15RST)
+#define __HAL_RCC_TIM16_RELEASE_RESET()          (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM16RST)
+#define __HAL_RCC_TIM17_RELEASE_RESET()          (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM17RST)
+#define __HAL_RCC_SPI5_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI5RST)
+#define __HAL_RCC_SAI1_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI1RST)
+#define __HAL_RCC_SAI2_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI2RST)
+#if defined(SAI3)
+#define __HAL_RCC_SAI3_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI3RST)
+#endif /*SAI3*/
+#define __HAL_RCC_DFSDM1_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_DFSDM1RST)
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_HRTIMRST)
+#endif /*HRTIM1*/
+
+/** @brief  Force or release the APB4 peripheral reset.
+  */
+
+#define __HAL_RCC_APB4_FORCE_RESET()           (RCC->APB4RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_SYSCFG_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_SYSCFGRST)
+#define __HAL_RCC_LPUART1_FORCE_RESET()          (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPUART1RST)
+#define __HAL_RCC_SPI6_FORCE_RESET()             (RCC->APB4RSTR) |= (RCC_APB4RSTR_SPI6RST)
+#define __HAL_RCC_I2C4_FORCE_RESET()             (RCC->APB4RSTR) |= (RCC_APB4RSTR_I2C4RST)
+#define __HAL_RCC_LPTIM2_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM2RST)
+#define __HAL_RCC_LPTIM3_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM3RST)
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM4RST)
+#endif /*LPTIM4*/
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM5RST)
+#endif /*LPTIM5*/
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_FORCE_RESET()             (RCC->APB4RSTR) |= (RCC_APB4RSTR_DAC2RST)
+#endif /*DAC2*/
+#define __HAL_RCC_COMP12_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_COMP12RST)
+#define __HAL_RCC_VREF_FORCE_RESET()             (RCC->APB4RSTR) |= (RCC_APB4RSTR_VREFRST)
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_FORCE_RESET()             (RCC->APB4RSTR) |= (RCC_APB4RSTR_SAI4RST)
+#endif /*SAI4*/
+#if defined(DTS)
+#define __HAL_RCC_DTS_FORCE_RESET()              (RCC->APB4RSTR) |= (RCC_APB4RSTR_DTSRST)
+#endif /*DTS*/
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_DFSDM2RST)
+#endif /*DFSDM2*/
+
+#define __HAL_RCC_APB4_RELEASE_RESET()           (RCC->APB4RSTR = 0x00U)
+#define __HAL_RCC_SYSCFG_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SYSCFGRST)
+#define __HAL_RCC_LPUART1_RELEASE_RESET()          (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPUART1RST)
+#define __HAL_RCC_SPI6_RELEASE_RESET()             (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SPI6RST)
+#define __HAL_RCC_I2C4_RELEASE_RESET()             (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_I2C4RST)
+#define __HAL_RCC_LPTIM2_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM2RST)
+#define __HAL_RCC_LPTIM3_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM3RST)
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM4RST)
+#endif /*LPTIM4*/
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM5RST)
+#endif /*LPTIM5*/
+#if defined(RCC_APB4RSTR_DAC2RST)
+#define __HAL_RCC_DAC2_RELEASE_RESET()             (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DAC2RST)
+#endif
+#define __HAL_RCC_COMP12_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_COMP12RST)
+#define __HAL_RCC_VREF_RELEASE_RESET()             (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_VREFRST)
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_RELEASE_RESET()             (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SAI4RST)
+#endif /*SAI4*/
+#if defined(DTS)
+#define __HAL_RCC_DTS_RELEASE_RESET()              (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DTSRST)
+#endif /*DTS*/
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DFSDM2RST)
+#endif /*DFSDM2*/
+
+/** @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+
+
+#define __HAL_RCC_MDMA_CLK_SLEEP_ENABLE()            (RCC->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN))
+#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE()           (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN))
+#if defined(JPEG)
+#define __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN))
+#endif /* JPEG */
+#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE()           (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN))
+#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE()             (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE()            (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
+#endif /*QUADSPI*/
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN))
+#if defined(OCTOSPI1)
+#define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OSPI1LPEN))
+#endif /*OCTOSPI1*/
+#if defined(OCTOSPI2)
+#define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OSPI2LPEN))
+#endif /*OCTOSPI2*/
+#if defined(OCTOSPIM)
+#define __HAL_RCC_IOMNGR_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_IOMNGRLPEN))
+#endif /*OCTOSPIM*/
+#if defined(OTFDEC1)
+#define __HAL_RCC_OTFDEC1_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OTFDEC1LPEN))
+#endif /*OTFDEC1*/
+#if defined(OTFDEC2)
+#define __HAL_RCC_OTFDEC2_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OTFDEC2LPEN))
+#endif /*OTFDEC2*/
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_GFXMMULPEN))
+#endif /*GFXMMU*/
+#if defined(CD_AXISRAM2_BASE)
+#define __HAL_RCC_AXISRAM2_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM2LPEN))
+#endif
+#if defined(CD_AXISRAM3_BASE)
+#define __HAL_RCC_AXISRAM3_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM3LPEN))
+#endif
+#define __HAL_RCC_DTCM1_CLK_SLEEP_ENABLE()           (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN))
+#define __HAL_RCC_DTCM2_CLK_SLEEP_ENABLE()           (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN))
+#define __HAL_RCC_ITCM_CLK_SLEEP_ENABLE()            (RCC->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN))
+#if defined(RCC_AHB3LPENR_AXISRAMLPEN)
+#define __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE()         (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN))
+#define __HAL_RCC_AXISRAM_CLK_SLEEP_ENABLE           __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE
+#else
+#define __HAL_RCC_AXISRAM1_CLK_SLEEP_ENABLE()        (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM1LPEN))
+#define __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE           __HAL_RCC_AXISRAM1_CLK_SLEEP_ENABLE  /* For backward compatibility */
+#endif /* RCC_AHB3LPENR_AXISRAMLPEN */
+
+#define __HAL_RCC_MDMA_CLK_SLEEP_DISABLE()            (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN))
+#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN))
+#if defined(JPEG)
+#define __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE()          (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN))
+#endif /* JPEG */
+#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN))
+#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE()             (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN))
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE()            (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN))
+#endif /*QUADSPI*/
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE()          (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN))
+#if defined(OCTOSPI1)
+#define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OSPI1LPEN))
+#endif /*OCTOSPI1*/
+#if defined(OCTOSPI2)
+#define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OSPI2LPEN))
+#endif /*OCTOSPI2*/
+#if defined(OCTOSPIM)
+#define __HAL_RCC_IOMNGR_CLK_SLEEP_DISABLE()          (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_IOMNGRLPEN))
+#endif /*OCTOSPIM*/
+#if defined(OTFDEC1)
+#define __HAL_RCC_OTFDEC1_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OTFDEC1LPEN))
+#endif /*OTFDEC1*/
+#if defined(OTFDEC2)
+#define __HAL_RCC_OTFDEC2_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OTFDEC2LPEN))
+#endif /*OTFDEC2*/
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_GFXMMULPEN))
+#endif /*GFXMMU*/
+#if defined(CD_AXISRAM2_BASE)
+#define __HAL_RCC_AXISRAM2_CLK_SLEEP_DISABLE()         (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM2LPEN))
+#endif
+#if defined(CD_AXISRAM3_BASE)
+#define __HAL_RCC_AXISRAM3_CLK_SLEEP_DISABLE()         (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM3LPEN))
+#endif
+#define __HAL_RCC_DTCM1_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN))
+#define __HAL_RCC_DTCM2_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN))
+#define __HAL_RCC_ITCM_CLK_SLEEP_DISABLE()            (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN))
+#if defined(RCC_AHB3LPENR_AXISRAMLPEN)
+#define __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE()         (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN))
+#define __HAL_RCC_AXISRAM_CLK_SLEEP_DISABLE           __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE
+#else
+#define __HAL_RCC_AXISRAM1_CLK_SLEEP_DISABLE()        (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM1LPEN))
+#define __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE          __HAL_RCC_AXISRAM1_CLK_SLEEP_DISABLE      /* For backward compatibility */
+#endif  /* RCC_AHB3LPENR_AXISRAMLPEN */
+
+/** @brief  Get the enable or disable status of the AHB3 peripheral clock during Low Poser (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+
+#define __HAL_RCC_MDMA_IS_CLK_SLEEP_ENABLED()             ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN)    != 0U)
+#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN)   != 0U)
+#if defined(JPEG)
+#define __HAL_RCC_JPGDEC_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_JPGDECLPEN)  != 0U)
+#endif /* JPEG */
+#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN)   != 0U)
+#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN)     != 0U)
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED()             ((RCC->AHB3LPENR & RCC_AHB3LPENR_QSPILPEN)    != 0U)
+#endif /*QUADSPI*/
+#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN)  != 0U)
+#if defined(OCTOSPI1)
+#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI1LPEN)    != 0U)
+#endif /*OCTOSPI1*/
+#if defined(OCTOSPI2)
+#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI2LPEN)    != 0U)
+#endif /*OCTOSPI2*/
+#if defined(OCTOSPIM)
+#define __HAL_RCC_IOMNGR_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_IOMNGRLPEN)   != 0U)
+#endif /*OCTOSPIM*/
+#if defined(OTFDEC1)
+#define __HAL_RCC_OTFDEC1_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC1LPEN) != 0U)
+#endif /*OTFDEC1*/
+#if defined(OTFDEC2)
+#define __HAL_RCC_OTFDEC2_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC2LPEN) != 0U)
+#endif /*OTFDEC2*/
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_GFXMMULPEN)    != 0U)
+#endif /*GFXMMU*/
+#if defined(CD_AXISRAM2_BASE)
+#define __HAL_RCC_AXISRAM2_IS_CLK_SLEEP_ENABLED()         ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM2LPEN)   != 0U)
+#endif
+#if defined(CD_AXISRAM3_BASE)
+#define __HAL_RCC_AXISRAM3_IS_CLK_SLEEP_ENABLED()         ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM3LPEN)   != 0U)
+#endif
+#define __HAL_RCC_DTCM1_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN)   != 0U)
+#define __HAL_RCC_DTCM2_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN)   != 0U)
+#define __HAL_RCC_ITCM_IS_CLK_SLEEP_ENABLED()             ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN)    != 0U)
+#if defined(RCC_AHB3LPENR_AXISRAMLPEN)
+#define __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_ENABLED()          ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAMLPEN) != 0U)
+#else
+#define __HAL_RCC_AXISRAM1_IS_CLK_SLEEP_ENABLED()         ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM1LPEN) != 0U)
+#endif
+
+#define __HAL_RCC_MDMA_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN)    == 0U)
+#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN)   == 0U)
+#if defined(JPEG)
+#define __HAL_RCC_JPGDEC_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB3LPENR & RCC_AHB3LPENR_JPGDECLPEN)  == 0U)
+#endif /* JPEG */
+#define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN)   == 0U)
+#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN)     == 0U)
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_QSPILPEN)    == 0U)
+#endif /*QUADSPI*/
+#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN)  == 0U)
+#if defined(OCTOSPI1)
+#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI1LPEN)  == 0U)
+#endif /*OCTOSPI1*/
+#if defined(OCTOSPI2)
+#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI2LPEN)  == 0U)
+#endif /*OCTOSPI2*/
+#if defined(OCTOSPIM)
+#define __HAL_RCC_IOMNGR_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_IOMNGRLPEN) == 0U)
+#endif /*OCTOSPIM*/
+#if defined(OTFDEC1)
+#define __HAL_RCC_OTFDEC1_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC1LPEN)  == 0U)
+#endif /*OTFDEC1*/
+#if defined(OTFDEC2)
+#define __HAL_RCC_OTFDEC2_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC2LPEN)  == 0U)
+#endif /*OTFDEC2*/
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_GFXMMULPEN)  == 0U)
+#endif /*GFXMMU*/
+#if defined(CD_AXISRAM2_BASE)
+#define __HAL_RCC_AXISRAM2_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM2LPEN)  == 0U)
+#endif
+#if defined(CD_AXISRAM3_BASE)
+#define __HAL_RCC_AXISRAM3_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM3LPEN)  == 0U)
+#endif
+#define __HAL_RCC_DTCM1_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN)   == 0U)
+#define __HAL_RCC_DTCM2_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN)   == 0U)
+#define __HAL_RCC_ITCM_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN)    == 0U)
+#if defined(RCC_AHB3LPENR_AXISRAMLPEN)
+#define __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAMLPEN) == 0U)
+#else
+#define __HAL_RCC_AXISRAM1_IS_CLK_SLEEP_DISABLED()        ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAML1PEN) == 0U)
+#endif /* RCC_AHB3LPENR_AXISRAMLPEN */
+
+/** @brief  ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE()             (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
+#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE()             (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
+#define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE()            (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN))
+#if defined(RCC_AHB1LPENR_CRCLPEN)
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()              (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
+#endif
+#if defined(ETH)
+#define __HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE()          (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN))
+#endif /*ETH*/
+#if defined(DUAL_CORE)
+#define __HAL_RCC_ART_CLK_SLEEP_ENABLE()              (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ARTLPEN))
+#endif /*DUAL_CORE*/
+#if defined(ETH)
+#define __HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE()           (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN))
+#define __HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE()           (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN))
+#endif /*ETH*/
+#define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN))
+#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
+#if defined(USB2_OTG_FS)
+#define __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN))
+#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
+#endif /* USB2_OTG_FS */
+
+#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE()             (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN))
+#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE()             (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN))
+#define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE()            (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN))
+#if defined(RCC_AHB1LPENR_CRCLPEN)
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()              (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_CRCLPEN))
+#endif
+#if defined(ETH)
+#define __HAL_RCC_ETH1MAC_CLK_SLEEP_DISABLE()          (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN))
+#endif  /*ETH*/
+#if defined(DUAL_CORE)
+#define __HAL_RCC_ART_CLK_SLEEP_DISABLE()              (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ARTLPEN))
+#endif /*DUAL_CORE*/
+#if defined(ETH)
+#define __HAL_RCC_ETH1TX_CLK_SLEEP_DISABLE()           (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN))
+#define __HAL_RCC_ETH1RX_CLK_SLEEP_DISABLE()           (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN))
+#endif  /*ETH*/
+#define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()      (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN))
+#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
+#if defined(USB2_OTG_FS)
+#define __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()      (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN))
+#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
+#endif /* USB2_OTG_FS */
+
+/** @brief  Get the enable or disable status of the AHB1 peripheral clock during Low Poser (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+
+#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN))          != 0U)
+#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN))          != 0U)
+#define __HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED()             ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN))         != 0U)
+#if defined(RCC_AHB1LPENR_CRCLPEN)
+#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED()                ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN))         != 0U)
+#endif
+#if defined(ETH)
+#define __HAL_RCC_ETH1MAC_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1MACLPEN))       != 0U)
+#endif  /*ETH*/
+#if defined(DUAL_CORE)
+#define __HAL_RCC_ART_IS_CLK_SLEEP_ENABLED()               ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ARTLPEN))       != 0U)
+#endif /*DUAL_CORE*/
+#if defined(ETH)
+#define __HAL_RCC_ETH1TX_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1TXLPEN))        != 0U)
+#define __HAL_RCC_ETH1RX_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1RXLPEN))        != 0U)
+#endif  /*ETH*/
+#define __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_ENABLED()       ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN))     != 0U)
+#define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED()  ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) != 0U)
+#if defined(USB2_OTG_FS)
+#define __HAL_RCC_USB2_OTG_FS_IS_CLK_SLEEP_ENABLED()       ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSLPEN))     != 0U)
+#define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_SLEEP_ENABLED()  ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) != 0U)
+#endif /* USB2_OTG_FS */
+
+#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN))          == 0U)
+#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN))          == 0U)
+#define __HAL_RCC_ADC12_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN))         == 0U)
+#if defined(RCC_AHB1LPENR_CRCLPEN)
+#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED()              ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN))           == 0U)
+#endif
+#if defined(ETH)
+#define __HAL_RCC_ETH1MAC_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1MACLPEN))       == 0U)
+#endif /* ETH */
+#if defined(DUAL_CORE)
+#define __HAL_RCC_ART_IS_CLK_SLEEP_DISABLED()              ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ARTLPEN))           == 0U)
+#endif /*DUAL_CORE*/
+#if defined(ETH)
+#define __HAL_RCC_ETH1TX_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1TXLPEN))        == 0U)
+#define __HAL_RCC_ETH1RX_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1RXLPEN))        == 0U)
+#endif /* ETH */
+#define __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_DISABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN))     == 0U)
+#define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) == 0U)
+#if defined(USB2_OTG_FS)
+#define __HAL_RCC_USB2_OTG_FS_IS_CLK_SLEEP_DISABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSLPEN))     == 0U)
+#define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) == 0U)
+#endif /* USB2_OTG_FS */
+
+
+/** @brief  ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#if defined(DCMI) && defined(PSSI)
+#define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE()        (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMI_PSSILPEN))
+#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE()             __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE()             (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
+#endif /* DCMI && PSSI */
+#if defined(CRYP)
+#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE()             (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE()             (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
+#endif /* HASH */
+#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()              (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
+#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE()           (RCC->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))
+#if defined(RCC_AHB2LPENR_DFSDMDMALPEN)
+#define __HAL_RCC_DFSDMDMA_CLK_SLEEP_ENABLE()         (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DFSDMDMALPEN))
+#endif
+#if defined(RCC_AHB2LPENR_D2SRAM1LPEN)
+#define __HAL_RCC_D2SRAM1_CLK_SLEEP_ENABLE()          (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN))
+#else
+#define __HAL_RCC_AHBSRAM1_CLK_SLEEP_ENABLE()         (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AHBSRAM1LPEN))
+#endif /* RCC_AHB2LPENR_D2SRAM1LPEN */
+#if defined(RCC_AHB2LPENR_D2SRAM2LPEN)
+#define __HAL_RCC_D2SRAM2_CLK_SLEEP_ENABLE()          (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN))
+#else
+#define __HAL_RCC_AHBSRAM2_CLK_SLEEP_ENABLE()         (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AHBSRAM2LPEN))
+#endif /* RCC_AHB2LPENR_D2SRAM2LPEN */
+#if defined(RCC_AHB2LPENR_D2SRAM3LPEN)
+#define __HAL_RCC_D2SRAM3_CLK_SLEEP_ENABLE()          (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN))
+#endif
+
+#if defined(DCMI) && defined(PSSI)
+#define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE()        (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMI_PSSILPEN))
+#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE()             __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE()             (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))
+#endif /* DCMI && PSSI */
+#if defined(CRYP)
+#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE()             (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE()             (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))
+#endif /* HASH */
+#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()              (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))
+#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE()           (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))
+#if defined(RCC_AHB2LPENR_DFSDMDMALPEN)
+#define __HAL_RCC_DFSDMDMA_CLK_SLEEP_DISABLE()         (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DFSDMDMALPEN))
+#endif
+#if defined(RCC_AHB2LPENR_D2SRAM1LPEN)
+#define __HAL_RCC_D2SRAM1_CLK_SLEEP_DISABLE()          (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN))
+#else
+#define __HAL_RCC_AHBSRAM1_CLK_SLEEP_DISABLE()         (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_AHBSRAM1LPEN))
+#endif /* RCC_AHB2LPENR_D2SRAM1LPEN */
+#if defined(RCC_AHB2LPENR_D2SRAM2LPEN)
+#define __HAL_RCC_D2SRAM2_CLK_SLEEP_DISABLE()          (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN))
+#else
+#define __HAL_RCC_AHBSRAM2_CLK_SLEEP_DISABLE()          (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_AHBSRAM2LPEN))
+#endif /* RCC_AHB2LPENR_D2SRAM2LPEN */
+#if defined(RCC_AHB2LPENR_D2SRAM3LPEN)
+#define __HAL_RCC_D2SRAM3_CLK_SLEEP_DISABLE()          (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN))
+#endif
+
+/** @brief  Get the enable or disable status of the AHB2 peripheral clock during Low Poser (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+
+#if defined(DCMI) && defined(PSSI)
+#define __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_ENABLED()         ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMI_PSSILPEN))    != 0U)
+#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED()              __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_ENABLED()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN))    != 0U)
+#endif /* DCMI && PSSI */
+#if defined(CRYP)
+#define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN))    != 0U)
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN))    != 0U)
+#endif /* HASH */
+#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED()               ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN))     != 0U)
+#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN))  != 0U)
+#if defined(RCC_AHB2LPENR_DFSDMDMALPEN)
+#define __HAL_RCC_DFSDMDMA_IS_CLK_SLEEP_ENABLED()          ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DFSDMDMALPEN)) != 0U)
+#endif
+#if defined(RCC_AHB2LPENR_D2SRAM1LPEN)
+#define __HAL_RCC_D2SRAM1_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM1LPEN)) != 0U)
+#else
+#define __HAL_RCC_AHBSRAM1_IS_CLK_SLEEP_ENABLED()          ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM1LPEN)) != 0U)
+#endif /* RCC_AHB2LPENR_D2SRAM1LPEN */
+#if defined(RCC_AHB2LPENR_D2SRAM2LPEN)
+#define __HAL_RCC_D2SRAM2_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM2LPEN)) != 0U)
+#else
+#define __HAL_RCC_AHBSRAM2_IS_CLK_SLEEP_ENABLED()          ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM2LPEN)) != 0U)
+#endif /* RCC_AHB2LPENR_D2SRAM2LPEN */
+#if defined(RCC_AHB2LPENR_D2SRAM3LPEN)
+#define __HAL_RCC_D2SRAM3_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM3LPEN)) != 0U)
+#endif /* RCC_AHB2LPENR_D2SRAM3LPEN */
+
+#if defined(DCMI) && defined(PSSI)
+#define __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_DISABLED()        ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMI_PSSILPEN))    == 0U)
+#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED()             __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_DISABLED()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN))    == 0U)
+#endif /* DCMI && PSSI */
+#if defined(CRYP)
+#define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN))    == 0U)
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN))    == 0U)
+#endif /* HASH */
+#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED()              ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN))     == 0U)
+#if defined(RCC_AHB2LPENR_DFSDMDMALPEN)
+#define __HAL_RCC_DFSDMDMA_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DFSDMDMALPEN)) == 0U)
+#endif
+#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN))  == 0U)
+#if defined(RCC_AHB2LPENR_D2SRAM1LPEN)
+#define __HAL_RCC_D2SRAM1_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM1LPEN)) == 0U)
+#else
+#define __HAL_RCC_AHBSRAM1_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM1LPEN)) == 0U)
+#endif /* RCC_AHB2LPENR_D2SRAM1LPEN */
+#if defined(RCC_AHB2LPENR_D2SRAM2LPEN)
+#define __HAL_RCC_D2SRAM2_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM2LPEN)) == 0U)
+#else
+#define __HAL_RCC_AHBSRAM2_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM2LPEN)) == 0U)
+#endif /* RCC_AHB2LPENR_D2SRAM2LPEN */
+#if defined(RCC_AHB2LPENR_D2SRAM3LPEN)
+#define __HAL_RCC_D2SRAM3_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM3LPEN)) == 0U)
+#endif /* RCC_AHB2LPENR_D2SRAM1LPEN*/
+
+
+/** @brief  ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN)
+#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN)
+#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN)
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN)
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN)
+#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN)
+#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN)
+#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN)
+#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN)
+#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN)
+#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN)
+#if defined(RCC_AHB4LPENR_CRCLPEN)
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()             (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN)
+#endif
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_CLK_SLEEP_ENABLE()            (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BDMA2LPEN)
+#define __HAL_RCC_BDMA_CLK_SLEEP_ENABLE  __HAL_RCC_BDMA2_CLK_SLEEP_ENABLE /* for API backward compatibility*/
+#else
+#define __HAL_RCC_BDMA_CLK_SLEEP_ENABLE()            (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN)
+#endif /* BDMA2 */
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE()            (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN)
+#endif /* ADC3 */
+#define __HAL_RCC_BKPRAM_CLK_SLEEP_ENABLE()          (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN)
+#if defined(RCC_AHB4LPENR_SRDSRAMLPEN)
+#define __HAL_RCC_SRDSRAM_CLK_SLEEP_ENABLE()         (RCC->AHB4LPENR  |= (RCC_AHB4LPENR_SRDSRAMLPEN))
+#define __HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE  __HAL_RCC_SRDSRAM_CLK_SLEEP_ENABLE /* for API backward compatibility*/
+#else
+#define __HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE()         (RCC->AHB4LPENR  |= (RCC_AHB4LPENR_D3SRAM1LPEN))
+#endif /* RCC_AHB4LPENR_SRDSRAMLPEN */
+
+#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN)
+#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN)
+#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN)
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN)
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN)
+#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN)
+#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN)
+#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN)
+#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN)
+#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN)
+#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN)
+#if defined(RCC_AHB4LPENR_CRCLPEN)
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()             (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN)
+#endif
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_CLK_SLEEP_DISABLE()            (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMA2LPEN)
+#define __HAL_RCC_BDMA_CLK_SLEEP_DISABLE  __HAL_RCC_BDMA2_CLK_SLEEP_DISABLE  /* For API backward compatibility*/
+#else
+#define __HAL_RCC_BDMA_CLK_SLEEP_DISABLE()            (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN)
+#endif /*BDMA2*/
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE()            (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN)
+#endif /*ADC3*/
+#define __HAL_RCC_BKPRAM_CLK_SLEEP_DISABLE()          (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN)
+#if defined(RCC_AHB4LPENR_SRDSRAMLPEN)
+#define __HAL_RCC_SRDSRAM_CLK_SLEEP_DISABLE()         (RCC->AHB4LPENR  &= ~ (RCC_AHB4LPENR_SRDSRAMLPEN))
+#define __HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE  __HAL_RCC_SRDSRAM_CLK_SLEEP_DISABLE
+#else
+#define __HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE()         (RCC->AHB4LPENR  &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN))
+#endif
+
+
+/** @brief  Get the enable or disable status of the AHB4 peripheral clock during Low Poser (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+
+#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN))   != 0U)
+#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN))   != 0U)
+#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN))   != 0U)
+#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN))   != 0U)
+#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN))   != 0U)
+#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN))   != 0U)
+#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN))   != 0U)
+#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN))   != 0U)
+#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN))   != 0U)
+#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN))   != 0U)
+#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN))   != 0U)
+#if defined(RCC_AHB4LPENR_CRCLPEN)
+#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB4LPENR & (RCC_AHB4LPENR_CRCLPEN))     != 0U)
+#endif
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMA2LPEN))    != 0U)
+#define __HAL_RCC_BDMA_IS_CLK_SLEEP_ENABLED __HAL_RCC_BDMA2_IS_CLK_SLEEP_ENABLED  /* For API backward compatibility*/
+#else
+#define __HAL_RCC_BDMA_IS_CLK_SLEEP_ENABLED()             ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMALPEN))    != 0U)
+#endif /*BDMA2*/
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED()             ((RCC->AHB4LPENR & (RCC_AHB4LPENR_ADC3LPEN))    != 0U)
+#endif /*ADC3*/
+#define __HAL_RCC_BKPRAM_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN))  != 0U)
+#if defined(RCC_AHB4LPENR_SRDSRAMLPEN)
+#define __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_ENABLED()          ((RCC->AHB4LPENR & (RCC_AHB4LPENR_SRDSRAMLPEN)) != 0U)
+#define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_ENABLED  __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_ENABLED  /* For API backward compatibility*/
+#else
+#define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_ENABLED()          ((RCC->AHB4LPENR & (RCC_AHB4LPENR_D3SRAM1LPEN)) != 0U)
+#endif
+
+#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN))   == 0U)
+#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN))   == 0U)
+#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN))   == 0U)
+#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN))   == 0U)
+#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN))   == 0U)
+#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN))   == 0U)
+#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN))   == 0U)
+#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN))   == 0U)
+#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN))   == 0U)
+#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN))   == 0U)
+#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN))   == 0U)
+#if defined(RCC_AHB4LPENR_CRCLPEN)
+#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB4LPENR & (RCC_AHB4LPENR_CRCLPEN))     == 0U)
+#endif
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMA2LPEN))  == 0U)
+#define __HAL_RCC_BDMA_IS_CLK_SLEEP_DISABLED __HAL_RCC_BDMA2_IS_CLK_SLEEP_DISABLED  /* For API backward compatibility*/
+#else
+#define __HAL_RCC_BDMA_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMALPEN))    == 0U)
+#endif /*BDMA2*/
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_ADC3LPEN))    == 0U)
+#endif /*ADC3*/
+#define __HAL_RCC_BKPRAM_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN))  == 0U)
+#if defined(RCC_AHB4LPENR_SRDSRAMLPEN)
+#define __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB4LPENR & (RCC_AHB4LPENR_SRDSRAMLPEN)) == 0U)
+#define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_DISABLED  __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_DISABLED  /* For API backward compatibility*/
+#else
+#define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB4LPENR & (RCC_AHB4LPENR_D3SRAM1LPEN)) == 0U)
+#endif
+
+
+/** @brief  ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE()           (RCC->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN)
+#endif /* LTDC */
+#if defined(DSI)
+#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE()            (RCC->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN)
+#endif /*DSI*/
+#define __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE()          (RCC->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN)
+
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE()           (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN)
+#endif /* LTDC */
+#if defined(DSI)
+#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE()            (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN)
+#endif /*DSI*/
+#define __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE()          (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN)
+
+
+/** @brief  Get the enable or disable status of the APB3 peripheral clock during Low Poser (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED()            ((RCC->APB3LPENR & (RCC_APB3LPENR_LTDCLPEN))  != 0U)
+#endif /* LTDC */
+#if defined(DSI)
+#define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED()             ((RCC->APB3LPENR & (RCC_APB3LPENR_DSILPEN))   != 0U)
+#endif /*DSI*/
+#define __HAL_RCC_WWDG1_IS_CLK_SLEEP_ENABLED()           ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) != 0U)
+
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED()           ((RCC->APB3LPENR & (RCC_APB3LPENR_LTDCLPEN))  == 0U)
+#endif /* LTDC */
+#if defined(DSI)
+#define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED()            ((RCC->APB3LPENR & (RCC_APB3LPENR_DSILPEN))   == 0U)
+#endif /*DSI*/
+#define __HAL_RCC_WWDG1_IS_CLK_SLEEP_DISABLED()          ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) == 0U)
+
+
+/** @brief  ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN)
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN)
+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN)
+#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN)
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN)
+#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN)
+#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN)
+#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN)
+#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN)
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE()         (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN)
+
+#if defined(DUAL_CORE)
+#define __HAL_RCC_WWDG2_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN)
+#endif /*DUAL_CORE*/
+
+#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN)
+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN)
+#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE()        (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN)
+#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE()         (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN)
+#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()         (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN)
+#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN)
+#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN)
+#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN)
+#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN)
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN)
+#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE()            (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN)
+#define __HAL_RCC_DAC12_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN)
+#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN)
+#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN)
+#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE()            (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN)
+#define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE()          (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN)
+#define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE()          (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN)
+#define __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE()          (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN)
+#define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE()          (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN)
+
+
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN)
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN)
+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN)
+#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN)
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN)
+#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN)
+#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN)
+#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN)
+#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN)
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE()         (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN)
+
+#if defined(DUAL_CORE)
+#define __HAL_RCC_WWDG2_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN)
+#endif /*DUAL_CORE*/
+
+#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN)
+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN)
+#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()        (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN)
+#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE()         (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN)
+#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE()         (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN)
+#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN)
+#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN)
+#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN)
+#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN)
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN)
+#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE()            (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN)
+#define __HAL_RCC_DAC12_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN)
+#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN)
+#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN)
+#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE()            (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN)
+#define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE()          (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN)
+#define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE()          (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN)
+#define __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE()          (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN)
+#define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE()          (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN)
+
+
+/** @brief  Get the enable or disable status of the APB1 peripheral clock during Low Poser (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+
+#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN))    != 0U)
+#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN))    != 0U)
+#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN))    != 0U)
+#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN))    != 0U)
+#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN))    != 0U)
+#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN))    != 0U)
+#define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN))   != 0U)
+#define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN))   != 0U)
+#define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN))   != 0U)
+#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN))  != 0U)
+#if defined(DUAL_CORE)
+#define __HAL_RCC_WWDG2_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_WWDG2LPEN))   != 0U)
+#endif /*DUAL_CORE*/
+#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN))    != 0U)
+#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN))    != 0U)
+#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED()         ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) != 0U)
+#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN))  != 0U)
+#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN))  != 0U)
+#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN))   != 0U)
+#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN))   != 0U)
+#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN))    != 0U)
+#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN))    != 0U)
+#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN))    != 0U)
+#define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED()             ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN))     != 0U)
+#define __HAL_RCC_DAC12_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN))   != 0U)
+#define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN))   != 0U)
+#define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN))   != 0U)
+#define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED()             ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN))     != 0U)
+#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED()          ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN))   != 0U)
+#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN))   != 0U)
+#define __HAL_RCC_MDIOS_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN))   != 0U)
+#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN))   != 0U)
+
+#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN))    == 0U)
+#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN))    == 0U)
+#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN))    == 0U)
+#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN))    == 0U)
+#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN))    == 0U)
+#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN))    == 0U)
+#define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN))   == 0U)
+#define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN))   == 0U)
+#define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN))   == 0U)
+#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED()         ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN))  == 0U)
+#if defined(DUAL_CORE)
+#define __HAL_RCC_WWDG2_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_WWDG2LPEN))   == 0U)
+#endif /*DUAL_CORE*/
+#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN))    == 0U)
+#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN))    == 0U)
+#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED()        ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) == 0U)
+#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED()         ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN))  == 0U)
+#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED()         ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN))  == 0U)
+#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN))   == 0U)
+#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN))   == 0U)
+#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN))    == 0U)
+#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN))    == 0U)
+#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN))    == 0U)
+#define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN))     == 0U)
+#define __HAL_RCC_DAC12_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN))   == 0U)
+#define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN))   == 0U)
+#define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN))   == 0U)
+#define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED()            ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN))     == 0U)
+#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED()         ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN))   == 0U)
+#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN))   == 0U)
+#define __HAL_RCC_MDIOS_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN))   == 0U)
+#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN))   == 0U)
+
+
+/** @brief  ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN)
+#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN)
+#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE()         (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN)
+#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE()         (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN)
+#if defined(UART9)
+#define __HAL_RCC_UART9_CLK_SLEEP_ENABLE()          (RCC->APB2LPENR) |= (RCC_APB2LPENR_UART9LPEN)
+#endif /*UART9*/
+#if defined(USART10)
+#define __HAL_RCC_USART10_CLK_SLEEP_ENABLE()        (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART10LPEN)
+#endif /*USART10*/
+#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN)
+#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN)
+#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE()          (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN)
+#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE()          (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN)
+#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE()          (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN)
+#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN)
+#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN)
+#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN)
+#if defined(SAI3)
+#define __HAL_RCC_SAI3_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN)
+#endif /*SAI3*/
+#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE()         (RCC->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN)
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_CLK_SLEEP_ENABLE()         (RCC->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN)
+#endif /*HRTIM1*/
+
+#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN)
+#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN)
+#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE()         (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN)
+#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE()         (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN)
+#if defined(UART9)
+#define __HAL_RCC_UART9_CLK_SLEEP_DISABLE()          (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_UART9LPEN)
+#endif /*UART9*/
+#if defined(USART10)
+#define __HAL_RCC_USART10_CLK_SLEEP_DISABLE()         (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART10LPEN)
+#endif /*USART10*/
+#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN)
+#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN)
+#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE()          (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN)
+#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE()          (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN)
+#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE()          (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN)
+#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN)
+#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN)
+#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN)
+#if defined(SAI3)
+#define __HAL_RCC_SAI3_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN)
+#endif /*SAI3*/
+#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE()         (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN)
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_CLK_SLEEP_DISABLE()         (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN)
+#endif /*HRTIM1*/
+
+
+/** @brief  Get the enable or disable status of the APB2 peripheral clock during Low Poser (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+
+#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN))   != 0U)
+#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN))   != 0U)
+#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != 0U)
+#define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != 0U)
+#if defined(UART9)
+#define __HAL_RCC_UART9_IS_CLK_SLEEP_ENABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_UART9LPEN)) != 0U)
+#endif /*UART9*/
+#if defined(USART10)
+#define __HAL_RCC_USART10_IS_CLK_SLEEP_ENABLED()         ((RCC->APB2LPENR & (RCC_APB2LPENR_USART10LPEN)) != 0U)
+#endif /*USART10*/
+#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN))   != 0U)
+#define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN))   != 0U)
+#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN))  != 0U)
+#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN))  != 0U)
+#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN))  != 0U)
+#define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN))   != 0U)
+#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN))   != 0U)
+#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN))   != 0U)
+#if defined(SAI3)
+#define __HAL_RCC_SAI3_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI3LPEN))   != 0U)
+#endif /*SAI3*/
+#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != 0U)
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_ENABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_HRTIMLPEN))  != 0U)
+#endif /*HRTIM1*/
+
+#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN))   == 0U)
+#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN))   == 0U)
+#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED()         ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == 0U)
+#define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED()         ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == 0U)
+#if defined(UART9)
+#define __HAL_RCC_USART9_IS_CLK_SLEEP_DISABLED()         ((RCC->APB2LPENR & (RCC_APB2LPENR_USART9LPEN)) == 0U)
+#endif /*UART9*/
+#if defined(USART10)
+#define __HAL_RCC_USART10_IS_CLK_SLEEP_DISABLED()        ((RCC->APB2LPENR & (RCC_APB2LPENR_USART10LPEN)) == 0U)
+#endif /*USART10*/
+#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN))   == 0U)
+#define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN))   == 0U)
+#define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN))  == 0U)
+#define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN))  == 0U)
+#define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN))  == 0U)
+#define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN))   == 0U)
+#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN))   == 0U)
+#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN))   == 0U)
+#if defined(SAI3)
+#define __HAL_RCC_SAI3_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI3LPEN))   == 0U)
+#endif /*SAI3*/
+#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED()         ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == 0U)
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_DISABLED()         ((RCC->APB2LPENR & (RCC_APB2LPENR_HRTIMLPEN))  == 0U)
+#endif /*HRTIM1*/
+
+/** @brief  ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN)
+#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE()          (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN)
+#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE()             (RCC->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN)
+#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE()             (RCC->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN)
+#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN)
+#define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN)
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN)
+#endif /*LPTIM4*/
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN)
+#endif /*LPTIM5*/
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_DAC2LPEN)
+#endif /*DAC2*/
+#define __HAL_RCC_COMP12_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN)
+#define __HAL_RCC_VREF_CLK_SLEEP_ENABLE()             (RCC->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN)
+#define __HAL_RCC_RTC_CLK_SLEEP_ENABLE()              (RCC->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN)
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_CLK_SLEEP_ENABLE()             (RCC->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN)
+#endif /*SAI4*/
+#if defined(DTS)
+#define __HAL_RCC_DTS_CLK_SLEEP_ENABLE()              (RCC->APB4LPENR) |= (RCC_APB4LPENR_DTSLPEN)
+#endif /*DTS*/
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_DFSDM2LPEN)
+#endif /*DFSDM2*/
+
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN)
+#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE()          (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN)
+#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE()             (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN)
+#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE()             (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN)
+#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN)
+#define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN)
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN)
+#endif /*LPTIM4*/
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN)
+#endif /*LPTIM5*/
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_CLK_SLEEP_DISABLE()             (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DAC2LPEN)
+#endif /*DAC2*/
+#define __HAL_RCC_COMP12_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN)
+#define __HAL_RCC_VREF_CLK_SLEEP_DISABLE()             (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN)
+#define __HAL_RCC_RTC_CLK_SLEEP_DISABLE()              (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN)
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_CLK_SLEEP_DISABLE()             (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN)
+#endif /*SAI4*/
+#if defined(DTS)
+#define __HAL_RCC_DTS_CLK_SLEEP_DISABLE()              (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DTSLPEN)
+#endif /*DTS*/
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_CLK_SLEEP_DISABLE()          (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DFSDM2LPEN)
+#endif /*DFSDM2*/
+
+
+/** @brief  Get the enable or disable status of the APB4 peripheral clock during Low Poser (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+
+#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN))  != 0U)
+#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) != 0U)
+#define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN))    != 0U)
+#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN))    != 0U)
+#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN))  != 0U)
+#define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN))  != 0U)
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM4LPEN))  != 0U)
+#endif /*LPTIM4*/
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM5LPEN))  != 0U)
+#endif /*LPTIM5*/
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_IS_CLK_SLEEP_ENABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_DAC2LPEN))  != 0U)
+#endif /*DAC2*/
+#define __HAL_RCC_COMP12_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN))  != 0U)
+#define __HAL_RCC_VREF_IS_CLK_SLEEP_ENABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN))    != 0U)
+#define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED()               ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN))  != 0U)
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_IS_CLK_SLEEP_ENABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_SAI4LPEN))    != 0U)
+#endif /*SAI4*/
+#if defined(DTS)
+#define __HAL_RCC_DTS_IS_CLK_SLEEP_ENABLED()               ((RCC->APB4LPENR & (RCC_APB4LPENR_DTSLPEN))    != 0U)
+#endif /*DTS*/
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_DFSDM2LPEN)) != 0U)
+#endif /*DFSDM2*/
+
+#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN))  == 0U)
+#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED()          ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) == 0U)
+#define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED()             ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN))    == 0U)
+#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED()             ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN))    == 0U)
+#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN))  == 0U)
+#define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN))  == 0U)
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM4LPEN))  == 0U)
+#endif /*LPTIM4*/
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM5LPEN))  == 0U)
+#endif /*LPTIM5*/
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_IS_CLK_SLEEP_DISABLED()             ((RCC->APB4LPENR & (RCC_APB4LPENR_DAC2LPEN))  == 0U)
+#endif /*DAC2*/
+#define __HAL_RCC_COMP12_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN))  == 0U)
+#define __HAL_RCC_VREF_IS_CLK_SLEEP_DISABLED()             ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN))    == 0U)
+#define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN))  == 0U)
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_IS_CLK_SLEEP_DISABLED()             ((RCC->APB4LPENR & (RCC_APB4LPENR_SAI4LPEN))    == 0U)
+#endif /*SAI4*/
+#if defined(DTS)
+#define __HAL_RCC_DTS_IS_CLK_SLEEP_DISABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_DTSLPEN))    == 0U)
+#endif /*DTS*/
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_DFSDM2LPEN)) == 0U)
+#endif /*DFSDM2*/
+
+
+#if defined(DUAL_CORE)
+
+/** @brief  Enable or disable the RCC_C1 AHB3 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+#define __HAL_RCC_C1_MDMA_CLK_SLEEP_ENABLE()            (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN))
+#define __HAL_RCC_C1_DMA2D_CLK_SLEEP_ENABLE()           (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN))
+#define __HAL_RCC_C1_JPGDEC_CLK_SLEEP_ENABLE()          (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN))
+#define __HAL_RCC_C1_FLASH_CLK_SLEEP_ENABLE()           (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN))
+#define __HAL_RCC_C1_FMC_CLK_SLEEP_ENABLE()             (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
+#define __HAL_RCC_C1_QSPI_CLK_SLEEP_ENABLE()            (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
+#define __HAL_RCC_C1_SDMMC1_CLK_SLEEP_ENABLE()          (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN))
+#define __HAL_RCC_C1_DTCM1_CLK_SLEEP_ENABLE()           (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN))
+#define __HAL_RCC_C1_DTCM2_CLK_SLEEP_ENABLE()           (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN))
+#define __HAL_RCC_C1_ITCM_CLK_SLEEP_ENABLE()            (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN))
+#define __HAL_RCC_C1_D1SRAM1_CLK_SLEEP_ENABLE()         (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN))
+
+
+#define __HAL_RCC_C1_MDMA_CLK_SLEEP_DISABLE()            (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN))
+#define __HAL_RCC_C1_DMA2D_CLK_SLEEP_DISABLE()           (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN))
+#define __HAL_RCC_C1_JPGDEC_CLK_SLEEP_DISABLE()          (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN))
+#define __HAL_RCC_C1_FLASH_CLK_SLEEP_DISABLE()           (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN))
+#define __HAL_RCC_C1_FMC_CLK_SLEEP_DISABLE()             (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN))
+#define __HAL_RCC_C1_QSPI_CLK_SLEEP_DISABLE()            (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN))
+#define __HAL_RCC_C1_SDMMC1_CLK_SLEEP_DISABLE()          (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN))
+#define __HAL_RCC_C1_DTCM1_CLK_SLEEP_DISABLE()           (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN))
+#define __HAL_RCC_C1_DTCM2_CLK_SLEEP_DISABLE()           (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN))
+#define __HAL_RCC_C1_ITCM_CLK_SLEEP_DISABLE()            (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN))
+#define __HAL_RCC_C1_D1SRAM1_CLK_SLEEP_DISABLE()         (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN))
+
+
+
+/** @brief  ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C1_DMA1_CLK_SLEEP_ENABLE()             (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
+#define __HAL_RCC_C1_DMA2_CLK_SLEEP_ENABLE()             (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
+#define __HAL_RCC_C1_ADC12_CLK_SLEEP_ENABLE()            (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN))
+#define __HAL_RCC_C1_ETH1MAC_CLK_SLEEP_ENABLE()          (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN))
+#define __HAL_RCC_C1_ETH1TX_CLK_SLEEP_ENABLE()           (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN))
+#define __HAL_RCC_C1_ETH1RX_CLK_SLEEP_ENABLE()           (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN))
+#define __HAL_RCC_C1_USB1_OTG_HS_CLK_SLEEP_ENABLE()      (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN))
+#define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
+#define __HAL_RCC_C1_USB2_OTG_FS_CLK_SLEEP_ENABLE()      (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN))
+#define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
+
+#define __HAL_RCC_C1_DMA1_CLK_SLEEP_DISABLE()             (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN))
+#define __HAL_RCC_C1_DMA2_CLK_SLEEP_DISABLE()             (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN))
+#define __HAL_RCC_C1_ADC12_CLK_SLEEP_DISABLE()            (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN))
+#define __HAL_RCC_C1_ETH1MAC_CLK_SLEEP_DISABLE()          (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN))
+#define __HAL_RCC_C1_ETH1TX_CLK_SLEEP_DISABLE()           (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN))
+#define __HAL_RCC_C1_ETH1RX_CLK_SLEEP_DISABLE()           (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN))
+#define __HAL_RCC_C1_USB1_OTG_HS_CLK_SLEEP_DISABLE()      (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN))
+#define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
+#define __HAL_RCC_C1_USB2_OTG_FS_CLK_SLEEP_DISABLE()      (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN))
+#define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
+
+/** @brief  ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C1_DCMI_CLK_SLEEP_ENABLE()             (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
+#if defined(CRYP)
+#define __HAL_RCC_C1_CRYP_CLK_SLEEP_ENABLE()             (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_C1_HASH_CLK_SLEEP_ENABLE()             (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
+#endif /* HASH */
+#define __HAL_RCC_C1_RNG_CLK_SLEEP_ENABLE()              (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
+#define __HAL_RCC_C1_SDMMC2_CLK_SLEEP_ENABLE()           (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))
+#define __HAL_RCC_C1_D2SRAM1_CLK_SLEEP_ENABLE()          (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN))
+#define __HAL_RCC_C1_D2SRAM2_CLK_SLEEP_ENABLE()          (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN))
+#define __HAL_RCC_C1_D2SRAM3_CLK_SLEEP_ENABLE()          (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN))
+
+#define __HAL_RCC_C1_DCMI_CLK_SLEEP_DISABLE()             (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))
+#if defined(CRYP)
+#define __HAL_RCC_C1_CRYP_CLK_SLEEP_DISABLE()             (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_C1_HASH_CLK_SLEEP_DISABLE()             (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))
+#endif /* HASH */
+#define __HAL_RCC_C1_RNG_CLK_SLEEP_DISABLE()              (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))
+#define __HAL_RCC_C1_SDMMC2_CLK_SLEEP_DISABLE()           (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))
+#define __HAL_RCC_C1_D2SRAM1_CLK_SLEEP_DISABLE()          (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN))
+#define __HAL_RCC_C1_D2SRAM2_CLK_SLEEP_DISABLE()          (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN))
+#define __HAL_RCC_C1_D2SRAM3_CLK_SLEEP_DISABLE()          (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN))
+
+/** @brief  ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C1_GPIOA_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN)
+#define __HAL_RCC_C1_GPIOB_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN)
+#define __HAL_RCC_C1_GPIOC_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN)
+#define __HAL_RCC_C1_GPIOD_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN)
+#define __HAL_RCC_C1_GPIOE_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN)
+#define __HAL_RCC_C1_GPIOF_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN)
+#define __HAL_RCC_C1_GPIOG_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN)
+#define __HAL_RCC_C1_GPIOH_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN)
+#define __HAL_RCC_C1_GPIOI_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN)
+#define __HAL_RCC_C1_GPIOJ_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN)
+#define __HAL_RCC_C1_GPIOK_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN)
+#define __HAL_RCC_C1_CRC_CLK_SLEEP_ENABLE()             (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN)
+#define __HAL_RCC_C1_BDMA_CLK_SLEEP_ENABLE()            (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN)
+#define __HAL_RCC_C1_ADC3_CLK_SLEEP_ENABLE()            (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN)
+#define __HAL_RCC_C1_BKPRAM_CLK_SLEEP_ENABLE()          (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN)
+#define __HAL_RCC_C1_D3SRAM1_CLK_SLEEP_ENABLE()         (RCC_C1->AHB4LPENR  |= (RCC_AHB4LPENR_D3SRAM1LPEN))
+
+#define __HAL_RCC_C1_GPIOA_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN)
+#define __HAL_RCC_C1_GPIOB_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN)
+#define __HAL_RCC_C1_GPIOC_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN)
+#define __HAL_RCC_C1_GPIOD_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN)
+#define __HAL_RCC_C1_GPIOE_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN)
+#define __HAL_RCC_C1_GPIOF_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN)
+#define __HAL_RCC_C1_GPIOG_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN)
+#define __HAL_RCC_C1_GPIOH_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN)
+#define __HAL_RCC_C1_GPIOI_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN)
+#define __HAL_RCC_C1_GPIOJ_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN)
+#define __HAL_RCC_C1_GPIOK_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN)
+#define __HAL_RCC_C1_CRC_CLK_SLEEP_DISABLE()             (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN)
+#define __HAL_RCC_C1_BDMA_CLK_SLEEP_DISABLE()            (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN)
+#define __HAL_RCC_C1_ADC3_CLK_SLEEP_DISABLE()            (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN)
+#define __HAL_RCC_C1_BKPRAM_CLK_SLEEP_DISABLE()          (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN)
+#define __HAL_RCC_C1_D3SRAM1_CLK_SLEEP_DISABLE()         (RCC_C1->AHB4LPENR  &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN))
+
+/** @brief  ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C1_LTDC_CLK_SLEEP_ENABLE()           (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN)
+#define __HAL_RCC_C1_DSI_CLK_SLEEP_ENABLE()            (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN)
+#define __HAL_RCC_C1_WWDG1_CLK_SLEEP_ENABLE()          (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN)
+
+#define __HAL_RCC_C1_LTDC_CLK_SLEEP_DISABLE()           (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN)
+#define __HAL_RCC_C1_DSI_CLK_SLEEP_DISABLE()            (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN)
+#define __HAL_RCC_C1_WWDG1_CLK_SLEEP_DISABLE()          (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN)
+
+/** @brief  ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C1_TIM2_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN)
+#define __HAL_RCC_C1_TIM3_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN)
+#define __HAL_RCC_C1_TIM4_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN)
+#define __HAL_RCC_C1_TIM5_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN)
+#define __HAL_RCC_C1_TIM6_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN)
+#define __HAL_RCC_C1_TIM7_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN)
+#define __HAL_RCC_C1_TIM12_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN)
+#define __HAL_RCC_C1_TIM13_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN)
+#define __HAL_RCC_C1_TIM14_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN)
+#define __HAL_RCC_C1_LPTIM1_CLK_SLEEP_ENABLE()         (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN)
+#define __HAL_RCC_C1_WWDG2_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN)
+#define __HAL_RCC_C1_SPI2_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN)
+#define __HAL_RCC_C1_SPI3_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN)
+#define __HAL_RCC_C1_SPDIFRX_CLK_SLEEP_ENABLE()        (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN)
+#define __HAL_RCC_C1_USART2_CLK_SLEEP_ENABLE()         (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN)
+#define __HAL_RCC_C1_USART3_CLK_SLEEP_ENABLE()         (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN)
+#define __HAL_RCC_C1_UART4_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN)
+#define __HAL_RCC_C1_UART5_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN)
+#define __HAL_RCC_C1_I2C1_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN)
+#define __HAL_RCC_C1_I2C2_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN)
+#define __HAL_RCC_C1_I2C3_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN)
+#define __HAL_RCC_C1_CEC_CLK_SLEEP_ENABLE()            (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN)
+#define __HAL_RCC_C1_DAC12_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN)
+#define __HAL_RCC_C1_UART7_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN)
+#define __HAL_RCC_C1_UART8_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN)
+#define __HAL_RCC_C1_CRS_CLK_SLEEP_ENABLE()            (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN)
+#define __HAL_RCC_C1_SWPMI_CLK_SLEEP_ENABLE()          (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN)
+#define __HAL_RCC_C1_OPAMP_CLK_SLEEP_ENABLE()          (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN)
+#define __HAL_RCC_C1_MDIOS_CLK_SLEEP_ENABLE()          (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN)
+#define __HAL_RCC_C1_FDCAN_CLK_SLEEP_ENABLE()          (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN)
+
+
+#define __HAL_RCC_C1_TIM2_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN)
+#define __HAL_RCC_C1_TIM3_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN)
+#define __HAL_RCC_C1_TIM4_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN)
+#define __HAL_RCC_C1_TIM5_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN)
+#define __HAL_RCC_C1_TIM6_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN)
+#define __HAL_RCC_C1_TIM7_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN)
+#define __HAL_RCC_C1_TIM12_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN)
+#define __HAL_RCC_C1_TIM13_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN)
+#define __HAL_RCC_C1_TIM14_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN)
+#define __HAL_RCC_C1_LPTIM1_CLK_SLEEP_DISABLE()         (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN)
+#define __HAL_RCC_C1_WWDG2_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN)
+#define __HAL_RCC_C1_SPI2_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN)
+#define __HAL_RCC_C1_SPI3_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN)
+#define __HAL_RCC_C1_SPDIFRX_CLK_SLEEP_DISABLE()        (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN)
+#define __HAL_RCC_C1_USART2_CLK_SLEEP_DISABLE()         (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN)
+#define __HAL_RCC_C1_USART3_CLK_SLEEP_DISABLE()         (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN)
+#define __HAL_RCC_C1_UART4_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN)
+#define __HAL_RCC_C1_UART5_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN)
+#define __HAL_RCC_C1_I2C1_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN)
+#define __HAL_RCC_C1_I2C2_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN)
+#define __HAL_RCC_C1_I2C3_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN)
+#define __HAL_RCC_C1_CEC_CLK_SLEEP_DISABLE()            (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN)
+#define __HAL_RCC_C1_DAC12_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN)
+#define __HAL_RCC_C1_UART7_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN)
+#define __HAL_RCC_C1_UART8_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN)
+#define __HAL_RCC_C1_CRS_CLK_SLEEP_DISABLE()            (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN)
+#define __HAL_RCC_C1_SWPMI_CLK_SLEEP_DISABLE()          (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN)
+#define __HAL_RCC_C1_OPAMP_CLK_SLEEP_DISABLE()          (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN)
+#define __HAL_RCC_C1_MDIOS_CLK_SLEEP_DISABLE()          (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN)
+#define __HAL_RCC_C1_FDCAN_CLK_SLEEP_DISABLE()          (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN)
+
+/** @brief  ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C1_TIM1_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN)
+#define __HAL_RCC_C1_TIM8_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN)
+#define __HAL_RCC_C1_USART1_CLK_SLEEP_ENABLE()         (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN)
+#define __HAL_RCC_C1_USART6_CLK_SLEEP_ENABLE()         (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN)
+#define __HAL_RCC_C1_SPI1_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN)
+#define __HAL_RCC_C1_SPI4_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN)
+#define __HAL_RCC_C1_TIM15_CLK_SLEEP_ENABLE()          (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN)
+#define __HAL_RCC_C1_TIM16_CLK_SLEEP_ENABLE()          (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN)
+#define __HAL_RCC_C1_TIM17_CLK_SLEEP_ENABLE()          (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN)
+#define __HAL_RCC_C1_SPI5_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN)
+#define __HAL_RCC_C1_SAI1_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN)
+#define __HAL_RCC_C1_SAI2_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN)
+#define __HAL_RCC_C1_SAI3_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN)
+#define __HAL_RCC_C1_DFSDM1_CLK_SLEEP_ENABLE()         (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN)
+#define __HAL_RCC_C1_HRTIM1_CLK_SLEEP_ENABLE()         (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN)
+
+#define __HAL_RCC_C1_TIM1_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN)
+#define __HAL_RCC_C1_TIM8_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN)
+#define __HAL_RCC_C1_USART1_CLK_SLEEP_DISABLE()         (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN)
+#define __HAL_RCC_C1_USART6_CLK_SLEEP_DISABLE()         (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN)
+#define __HAL_RCC_C1_SPI1_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN)
+#define __HAL_RCC_C1_SPI4_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN)
+#define __HAL_RCC_C1_TIM15_CLK_SLEEP_DISABLE()          (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN)
+#define __HAL_RCC_C1_TIM16_CLK_SLEEP_DISABLE()          (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN)
+#define __HAL_RCC_C1_TIM17_CLK_SLEEP_DISABLE()          (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN)
+#define __HAL_RCC_C1_SPI5_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN)
+#define __HAL_RCC_C1_SAI1_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN)
+#define __HAL_RCC_C1_SAI2_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN)
+#define __HAL_RCC_C1_SAI3_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN)
+#define __HAL_RCC_C1_DFSDM1_CLK_SLEEP_DISABLE()         (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN)
+#define __HAL_RCC_C1_HRTIM1_CLK_SLEEP_DISABLE()         (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN)
+
+/** @brief  ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C1_SYSCFG_CLK_SLEEP_ENABLE()           (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN)
+#define __HAL_RCC_C1_LPUART1_CLK_SLEEP_ENABLE()          (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN)
+#define __HAL_RCC_C1_SPI6_CLK_SLEEP_ENABLE()             (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN)
+#define __HAL_RCC_C1_I2C4_CLK_SLEEP_ENABLE()             (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN)
+#define __HAL_RCC_C1_LPTIM2_CLK_SLEEP_ENABLE()           (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN)
+#define __HAL_RCC_C1_LPTIM3_CLK_SLEEP_ENABLE()           (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN)
+#define __HAL_RCC_C1_LPTIM4_CLK_SLEEP_ENABLE()           (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN)
+#define __HAL_RCC_C1_LPTIM5_CLK_SLEEP_ENABLE()           (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN)
+#define __HAL_RCC_C1_COMP12_CLK_SLEEP_ENABLE()           (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN)
+#define __HAL_RCC_C1_VREF_CLK_SLEEP_ENABLE()             (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN)
+#define __HAL_RCC_C1_SAI4_CLK_SLEEP_ENABLE()             (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN)
+#define __HAL_RCC_C1_RTC_CLK_SLEEP_ENABLE()              (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN)
+
+
+#define __HAL_RCC_C1_SYSCFG_CLK_SLEEP_DISABLE()           (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN)
+#define __HAL_RCC_C1_LPUART1_CLK_SLEEP_DISABLE()          (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN)
+#define __HAL_RCC_C1_SPI6_CLK_SLEEP_DISABLE()             (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN)
+#define __HAL_RCC_C1_I2C4_CLK_SLEEP_DISABLE()             (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN)
+#define __HAL_RCC_C1_LPTIM2_CLK_SLEEP_DISABLE()           (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN)
+#define __HAL_RCC_C1_LPTIM3_CLK_SLEEP_DISABLE()           (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN)
+#define __HAL_RCC_C1_LPTIM4_CLK_SLEEP_DISABLE()           (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN)
+#define __HAL_RCC_C1_LPTIM5_CLK_SLEEP_DISABLE()           (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN)
+#define __HAL_RCC_C1_COMP12_CLK_SLEEP_DISABLE()           (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN)
+#define __HAL_RCC_C1_VREF_CLK_SLEEP_DISABLE()             (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN)
+#define __HAL_RCC_C1_SAI4_CLK_SLEEP_DISABLE()             (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN)
+#define __HAL_RCC_C1_RTC_CLK_SLEEP_DISABLE()              (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN)
+
+/** @brief  Enable or disable the RCC_C2 AHB3 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+
+
+#define __HAL_RCC_C2_MDMA_CLK_SLEEP_ENABLE()            (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN))
+#define __HAL_RCC_C2_DMA2D_CLK_SLEEP_ENABLE()           (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN))
+#define __HAL_RCC_C2_JPGDEC_CLK_SLEEP_ENABLE()          (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN))
+#define __HAL_RCC_C2_FLASH_CLK_SLEEP_ENABLE()           (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN))
+#define __HAL_RCC_C2_FMC_CLK_SLEEP_ENABLE()             (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
+#define __HAL_RCC_C2_QSPI_CLK_SLEEP_ENABLE()            (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
+#define __HAL_RCC_C2_SDMMC1_CLK_SLEEP_ENABLE()          (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN))
+#define __HAL_RCC_C2_DTCM1_CLK_SLEEP_ENABLE()           (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN))
+#define __HAL_RCC_C2_DTCM2_CLK_SLEEP_ENABLE()           (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN))
+#define __HAL_RCC_C2_ITCM_CLK_SLEEP_ENABLE()            (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN))
+#define __HAL_RCC_C2_D1SRAM1_CLK_SLEEP_ENABLE()         (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN))
+
+
+#define __HAL_RCC_C2_MDMA_CLK_SLEEP_DISABLE()            (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN))
+#define __HAL_RCC_C2_DMA2D_CLK_SLEEP_DISABLE()           (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN))
+#define __HAL_RCC_C2_JPGDEC_CLK_SLEEP_DISABLE()          (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN))
+#define __HAL_RCC_C2_FLASH_CLK_SLEEP_DISABLE()           (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN))
+#define __HAL_RCC_C2_FMC_CLK_SLEEP_DISABLE()             (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN))
+#define __HAL_RCC_C2_QSPI_CLK_SLEEP_DISABLE()            (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN))
+#define __HAL_RCC_C2_SDMMC1_CLK_SLEEP_DISABLE()          (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN))
+#define __HAL_RCC_C2_DTCM1_CLK_SLEEP_DISABLE()           (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN))
+#define __HAL_RCC_C2_DTCM2_CLK_SLEEP_DISABLE()           (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN))
+#define __HAL_RCC_C2_ITCM_CLK_SLEEP_DISABLE()            (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN))
+#define __HAL_RCC_C2_D1SRAM1_CLK_SLEEP_DISABLE()         (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN))
+
+
+
+/** @brief  ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C2_DMA1_CLK_SLEEP_ENABLE()             (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
+#define __HAL_RCC_C2_DMA2_CLK_SLEEP_ENABLE()             (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
+#define __HAL_RCC_C2_ADC12_CLK_SLEEP_ENABLE()            (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN))
+#define __HAL_RCC_C2_ETH1MAC_CLK_SLEEP_ENABLE()          (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN))
+#define __HAL_RCC_C2_ETH1TX_CLK_SLEEP_ENABLE()           (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN))
+#define __HAL_RCC_C2_ETH1RX_CLK_SLEEP_ENABLE()           (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN))
+#define __HAL_RCC_C2_USB1_OTG_HS_CLK_SLEEP_ENABLE()      (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN))
+#define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
+#define __HAL_RCC_C2_USB2_OTG_FS_CLK_SLEEP_ENABLE()      (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN))
+#define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
+
+#define __HAL_RCC_C2_DMA1_CLK_SLEEP_DISABLE()             (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN))
+#define __HAL_RCC_C2_DMA2_CLK_SLEEP_DISABLE()             (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN))
+#define __HAL_RCC_C2_ADC12_CLK_SLEEP_DISABLE()            (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN))
+#define __HAL_RCC_C2_ETH1MAC_CLK_SLEEP_DISABLE()          (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN))
+#define __HAL_RCC_C2_ETH1TX_CLK_SLEEP_DISABLE()           (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN))
+#define __HAL_RCC_C2_ETH1RX_CLK_SLEEP_DISABLE()           (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN))
+#define __HAL_RCC_C2_USB1_OTG_HS_CLK_SLEEP_DISABLE()      (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN))
+#define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
+#define __HAL_RCC_C2_USB2_OTG_FS_CLK_SLEEP_DISABLE()      (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN))
+#define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
+
+/** @brief  ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C2_DCMI_CLK_SLEEP_ENABLE()             (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
+#if defined(CRYP)
+#define __HAL_RCC_C2_CRYP_CLK_SLEEP_ENABLE()             (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_C2_HASH_CLK_SLEEP_ENABLE()             (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
+#endif /* HASH */
+#define __HAL_RCC_C2_RNG_CLK_SLEEP_ENABLE()              (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
+#define __HAL_RCC_C2_SDMMC2_CLK_SLEEP_ENABLE()           (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))
+#define __HAL_RCC_C2_D2SRAM1_CLK_SLEEP_ENABLE()          (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN))
+#define __HAL_RCC_C2_D2SRAM2_CLK_SLEEP_ENABLE()          (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN))
+#define __HAL_RCC_C2_D2SRAM3_CLK_SLEEP_ENABLE()          (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN))
+
+#define __HAL_RCC_C2_DCMI_CLK_SLEEP_DISABLE()             (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))
+#if defined(CRYP)
+#define __HAL_RCC_C2_CRYP_CLK_SLEEP_DISABLE()             (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_C2_HASH_CLK_SLEEP_DISABLE()             (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))
+#endif /* HASH */
+#define __HAL_RCC_C2_RNG_CLK_SLEEP_DISABLE()              (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))
+#define __HAL_RCC_C2_SDMMC2_CLK_SLEEP_DISABLE()           (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))
+#define __HAL_RCC_C2_D2SRAM1_CLK_SLEEP_DISABLE()          (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN))
+#define __HAL_RCC_C2_D2SRAM2_CLK_SLEEP_DISABLE()          (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN))
+#define __HAL_RCC_C2_D2SRAM3_CLK_SLEEP_DISABLE()          (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN))
+
+/** @brief  ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C2_GPIOA_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN)
+#define __HAL_RCC_C2_GPIOB_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN)
+#define __HAL_RCC_C2_GPIOC_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN)
+#define __HAL_RCC_C2_GPIOD_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN)
+#define __HAL_RCC_C2_GPIOE_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN)
+#define __HAL_RCC_C2_GPIOF_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN)
+#define __HAL_RCC_C2_GPIOG_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN)
+#define __HAL_RCC_C2_GPIOH_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN)
+#define __HAL_RCC_C2_GPIOI_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN)
+#define __HAL_RCC_C2_GPIOJ_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN)
+#define __HAL_RCC_C2_GPIOK_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN)
+#define __HAL_RCC_C2_CRC_CLK_SLEEP_ENABLE()             (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN)
+#define __HAL_RCC_C2_BDMA_CLK_SLEEP_ENABLE()            (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN)
+#define __HAL_RCC_C2_ADC3_CLK_SLEEP_ENABLE()            (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN)
+#define __HAL_RCC_C2_BKPRAM_CLK_SLEEP_ENABLE()          (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN)
+#define __HAL_RCC_C2_D3SRAM1_CLK_SLEEP_ENABLE()         (RCC_C2->AHB4LPENR  |= (RCC_AHB4LPENR_D3SRAM1LPEN))
+
+#define __HAL_RCC_C2_GPIOA_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN)
+#define __HAL_RCC_C2_GPIOB_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN)
+#define __HAL_RCC_C2_GPIOC_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN)
+#define __HAL_RCC_C2_GPIOD_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN)
+#define __HAL_RCC_C2_GPIOE_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN)
+#define __HAL_RCC_C2_GPIOF_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN)
+#define __HAL_RCC_C2_GPIOG_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN)
+#define __HAL_RCC_C2_GPIOH_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN)
+#define __HAL_RCC_C2_GPIOI_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN)
+#define __HAL_RCC_C2_GPIOJ_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN)
+#define __HAL_RCC_C2_GPIOK_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN)
+#define __HAL_RCC_C2_CRC_CLK_SLEEP_DISABLE()             (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN)
+#define __HAL_RCC_C2_BDMA_CLK_SLEEP_DISABLE()            (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN)
+#define __HAL_RCC_C2_ADC3_CLK_SLEEP_DISABLE()            (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN)
+#define __HAL_RCC_C2_BKPRAM_CLK_SLEEP_DISABLE()          (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN)
+#define __HAL_RCC_C2_D3SRAM1_CLK_SLEEP_DISABLE()         (RCC_C2->AHB4LPENR  &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN))
+
+/** @brief  ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C2_LTDC_CLK_SLEEP_ENABLE()           (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN)
+#define __HAL_RCC_C2_DSI_CLK_SLEEP_ENABLE()            (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN)
+#define __HAL_RCC_C2_WWDG1_CLK_SLEEP_ENABLE()          (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN)
+
+#define __HAL_RCC_C2_LTDC_CLK_SLEEP_DISABLE()           (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN)
+#define __HAL_RCC_C2_DSI_CLK_SLEEP_DISABLE()            (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN)
+#define __HAL_RCC_C2_WWDG1_CLK_SLEEP_DISABLE()          (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN)
+
+/** @brief  ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C2_TIM2_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN)
+#define __HAL_RCC_C2_TIM3_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN)
+#define __HAL_RCC_C2_TIM4_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN)
+#define __HAL_RCC_C2_TIM5_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN)
+#define __HAL_RCC_C2_TIM6_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN)
+#define __HAL_RCC_C2_TIM7_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN)
+#define __HAL_RCC_C2_TIM12_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN)
+#define __HAL_RCC_C2_TIM13_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN)
+#define __HAL_RCC_C2_TIM14_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN)
+#define __HAL_RCC_C2_LPTIM1_CLK_SLEEP_ENABLE()         (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN)
+#define __HAL_RCC_C2_WWDG2_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN)
+#define __HAL_RCC_C2_SPI2_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN)
+#define __HAL_RCC_C2_SPI3_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN)
+#define __HAL_RCC_C2_SPDIFRX_CLK_SLEEP_ENABLE()        (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN)
+#define __HAL_RCC_C2_USART2_CLK_SLEEP_ENABLE()         (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN)
+#define __HAL_RCC_C2_USART3_CLK_SLEEP_ENABLE()         (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN)
+#define __HAL_RCC_C2_UART4_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN)
+#define __HAL_RCC_C2_UART5_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN)
+#define __HAL_RCC_C2_I2C1_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN)
+#define __HAL_RCC_C2_I2C2_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN)
+#define __HAL_RCC_C2_I2C3_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN)
+#define __HAL_RCC_C2_CEC_CLK_SLEEP_ENABLE()            (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN)
+#define __HAL_RCC_C2_DAC12_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN)
+#define __HAL_RCC_C2_UART7_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN)
+#define __HAL_RCC_C2_UART8_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN)
+#define __HAL_RCC_C2_CRS_CLK_SLEEP_ENABLE()            (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN)
+#define __HAL_RCC_C2_SWPMI_CLK_SLEEP_ENABLE()          (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN)
+#define __HAL_RCC_C2_OPAMP_CLK_SLEEP_ENABLE()          (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN)
+#define __HAL_RCC_C2_MDIOS_CLK_SLEEP_ENABLE()          (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN)
+#define __HAL_RCC_C2_FDCAN_CLK_SLEEP_ENABLE()          (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN)
+
+
+#define __HAL_RCC_C2_TIM2_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN)
+#define __HAL_RCC_C2_TIM3_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN)
+#define __HAL_RCC_C2_TIM4_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN)
+#define __HAL_RCC_C2_TIM5_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN)
+#define __HAL_RCC_C2_TIM6_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN)
+#define __HAL_RCC_C2_TIM7_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN)
+#define __HAL_RCC_C2_TIM12_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN)
+#define __HAL_RCC_C2_TIM13_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN)
+#define __HAL_RCC_C2_TIM14_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN)
+#define __HAL_RCC_C2_LPTIM1_CLK_SLEEP_DISABLE()         (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN)
+#define __HAL_RCC_C2_WWDG2_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN)
+#define __HAL_RCC_C2_SPI2_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN)
+#define __HAL_RCC_C2_SPI3_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN)
+#define __HAL_RCC_C2_SPDIFRX_CLK_SLEEP_DISABLE()        (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN)
+#define __HAL_RCC_C2_USART2_CLK_SLEEP_DISABLE()         (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN)
+#define __HAL_RCC_C2_USART3_CLK_SLEEP_DISABLE()         (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN)
+#define __HAL_RCC_C2_UART4_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN)
+#define __HAL_RCC_C2_UART5_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN)
+#define __HAL_RCC_C2_I2C1_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN)
+#define __HAL_RCC_C2_I2C2_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN)
+#define __HAL_RCC_C2_I2C3_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN)
+#define __HAL_RCC_C2_CEC_CLK_SLEEP_DISABLE()            (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN)
+#define __HAL_RCC_C2_DAC12_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN)
+#define __HAL_RCC_C2_UART7_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN)
+#define __HAL_RCC_C2_UART8_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN)
+#define __HAL_RCC_C2_CRS_CLK_SLEEP_DISABLE()            (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN)
+#define __HAL_RCC_C2_SWPMI_CLK_SLEEP_DISABLE()          (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN)
+#define __HAL_RCC_C2_OPAMP_CLK_SLEEP_DISABLE()          (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN)
+#define __HAL_RCC_C2_MDIOS_CLK_SLEEP_DISABLE()          (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN)
+#define __HAL_RCC_C2_FDCAN_CLK_SLEEP_DISABLE()          (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN)
+
+/** @brief  ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C2_TIM1_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN)
+#define __HAL_RCC_C2_TIM8_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN)
+#define __HAL_RCC_C2_USART1_CLK_SLEEP_ENABLE()         (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN)
+#define __HAL_RCC_C2_USART6_CLK_SLEEP_ENABLE()         (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN)
+#define __HAL_RCC_C2_SPI1_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN)
+#define __HAL_RCC_C2_SPI4_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN)
+#define __HAL_RCC_C2_TIM15_CLK_SLEEP_ENABLE()          (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN)
+#define __HAL_RCC_C2_TIM16_CLK_SLEEP_ENABLE()          (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN)
+#define __HAL_RCC_C2_TIM17_CLK_SLEEP_ENABLE()          (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN)
+#define __HAL_RCC_C2_SPI5_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN)
+#define __HAL_RCC_C2_SAI1_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN)
+#define __HAL_RCC_C2_SAI2_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN)
+#define __HAL_RCC_C2_SAI3_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN)
+#define __HAL_RCC_C2_DFSDM1_CLK_SLEEP_ENABLE()         (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN)
+#define __HAL_RCC_C2_HRTIM1_CLK_SLEEP_ENABLE()         (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN)
+
+#define __HAL_RCC_C2_TIM1_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN)
+#define __HAL_RCC_C2_TIM8_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN)
+#define __HAL_RCC_C2_USART1_CLK_SLEEP_DISABLE()         (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN)
+#define __HAL_RCC_C2_USART6_CLK_SLEEP_DISABLE()         (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN)
+#define __HAL_RCC_C2_SPI1_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN)
+#define __HAL_RCC_C2_SPI4_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN)
+#define __HAL_RCC_C2_TIM15_CLK_SLEEP_DISABLE()          (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN)
+#define __HAL_RCC_C2_TIM16_CLK_SLEEP_DISABLE()          (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN)
+#define __HAL_RCC_C2_TIM17_CLK_SLEEP_DISABLE()          (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN)
+#define __HAL_RCC_C2_SPI5_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN)
+#define __HAL_RCC_C2_SAI1_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN)
+#define __HAL_RCC_C2_SAI2_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN)
+#define __HAL_RCC_C2_SAI3_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN)
+#define __HAL_RCC_C2_DFSDM1_CLK_SLEEP_DISABLE()         (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN)
+#define __HAL_RCC_C2_HRTIM1_CLK_SLEEP_DISABLE()         (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN)
+
+/** @brief  ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C2_SYSCFG_CLK_SLEEP_ENABLE()           (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN)
+#define __HAL_RCC_C2_LPUART1_CLK_SLEEP_ENABLE()          (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN)
+#define __HAL_RCC_C2_SPI6_CLK_SLEEP_ENABLE()             (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN)
+#define __HAL_RCC_C2_I2C4_CLK_SLEEP_ENABLE()             (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN)
+#define __HAL_RCC_C2_LPTIM2_CLK_SLEEP_ENABLE()           (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN)
+#define __HAL_RCC_C2_LPTIM3_CLK_SLEEP_ENABLE()           (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN)
+#define __HAL_RCC_C2_LPTIM4_CLK_SLEEP_ENABLE()           (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN)
+#define __HAL_RCC_C2_LPTIM5_CLK_SLEEP_ENABLE()           (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN)
+#define __HAL_RCC_C2_COMP12_CLK_SLEEP_ENABLE()           (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN)
+#define __HAL_RCC_C2_VREF_CLK_SLEEP_ENABLE()             (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN)
+#define __HAL_RCC_C2_SAI4_CLK_SLEEP_ENABLE()             (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN)
+#define __HAL_RCC_C2_RTC_CLK_SLEEP_ENABLE()              (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN)
+
+#define __HAL_RCC_C2_SYSCFG_CLK_SLEEP_DISABLE()           (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN)
+#define __HAL_RCC_C2_LPUART1_CLK_SLEEP_DISABLE()          (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN)
+#define __HAL_RCC_C2_SPI6_CLK_SLEEP_DISABLE()             (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN)
+#define __HAL_RCC_C2_I2C4_CLK_SLEEP_DISABLE()             (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN)
+#define __HAL_RCC_C2_LPTIM2_CLK_SLEEP_DISABLE()           (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN)
+#define __HAL_RCC_C2_LPTIM3_CLK_SLEEP_DISABLE()           (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN)
+#define __HAL_RCC_C2_LPTIM4_CLK_SLEEP_DISABLE()           (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN)
+#define __HAL_RCC_C2_LPTIM5_CLK_SLEEP_DISABLE()           (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN)
+#define __HAL_RCC_C2_COMP12_CLK_SLEEP_DISABLE()           (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN)
+#define __HAL_RCC_C2_VREF_CLK_SLEEP_DISABLE()             (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN)
+#define __HAL_RCC_C2_SAI4_CLK_SLEEP_DISABLE()             (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN)
+#define __HAL_RCC_C2_RTC_CLK_SLEEP_DISABLE()              (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN)
+
+#endif /*DUAL_CORE*/
+
+#if defined(DUAL_CORE)
+/** @brief  Enable or disable peripheral bus clock  when D3 domain is in DRUN
+  * @note   After reset (default config), peripheral clock is disabled when both CPUs are in CSTOP
+  */
+#else
+/** @brief  Enable or disable peripheral bus clock  when D3 domain is in DRUN
+  * @note   After reset (default config), peripheral clock is disabled when CPU is in CSTOP
+  */
+#endif /*DUAL_CORE*/
+
+#if defined(RCC_D3AMR_BDMAAMEN)
+#define __HAL_RCC_BDMA_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_BDMAAMEN)
+#endif
+#if defined(RCC_D3AMR_LPUART1AMEN)
+#define __HAL_RCC_LPUART1_CLKAM_ENABLE()          (RCC->D3AMR) |= (RCC_D3AMR_LPUART1AMEN)
+#endif
+#if defined(RCC_D3AMR_SPI6AMEN)
+#define __HAL_RCC_SPI6_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_SPI6AMEN)
+#endif
+#if defined(RCC_D3AMR_I2C4AMEN)
+#define __HAL_RCC_I2C4_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_I2C4AMEN)
+#endif
+#if defined(RCC_D3AMR_LPTIM2AMEN)
+#define __HAL_RCC_LPTIM2_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_LPTIM2AMEN)
+#endif
+#if defined(RCC_D3AMR_LPTIM3AMEN)
+#define __HAL_RCC_LPTIM3_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_LPTIM3AMEN)
+#endif
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_LPTIM4AMEN)
+#endif
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_LPTIM5AMEN)
+#endif
+#if defined(RCC_D3AMR_COMP12AMEN)
+#define __HAL_RCC_COMP12_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_COMP12AMEN)
+#endif
+#if defined(RCC_D3AMR_VREFAMEN)
+#define __HAL_RCC_VREF_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_VREFAMEN)
+#endif
+#if defined(RCC_D3AMR_RTCAMEN)
+#define __HAL_RCC_RTC_CLKAM_ENABLE()              (RCC->D3AMR) |= (RCC_D3AMR_RTCAMEN)
+#endif
+#if defined(RCC_D3AMR_CRCAMEN)
+#define __HAL_RCC_CRC_CLKAM_ENABLE()              (RCC->D3AMR) |= (RCC_D3AMR_CRCAMEN)
+#endif
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_SAI4AMEN)
+#endif
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_ADC3AMEN)
+#endif
+#if defined(RCC_D3AMR_BKPRAMAMEN)
+#define __HAL_RCC_BKPRAM_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_BKPRAMAMEN)
+#endif
+#if defined(RCC_D3AMR_SRAM4AMEN)
+#define __HAL_RCC_D3SRAM1_CLKAM_ENABLE()          (RCC->D3AMR) |= (RCC_D3AMR_SRAM4AMEN)
+#endif
+
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_CLKAM_ENABLE()            (RCC->SRDAMR) |= (RCC_SRDAMR_BDMA2AMEN)
+#endif
+#if defined(RCC_SRDAMR_GPIOAMEN)
+#define __HAL_RCC_GPIO_CLKAM_ENABLE()             (RCC->SRDAMR) |= (RCC_SRDAMR_GPIOAMEN)
+#endif
+#if defined(RCC_SRDAMR_LPUART1AMEN)
+#define __HAL_RCC_LPUART1_CLKAM_ENABLE()          (RCC->SRDAMR) |= (RCC_SRDAMR_LPUART1AMEN)
+#endif
+#if defined(RCC_SRDAMR_SPI6AMEN)
+#define __HAL_RCC_SPI6_CLKAM_ENABLE()             (RCC->SRDAMR) |= (RCC_SRDAMR_SPI6AMEN)
+#endif
+#if defined(RCC_SRDAMR_I2C4AMEN)
+#define __HAL_RCC_I2C4_CLKAM_ENABLE()             (RCC->SRDAMR) |= (RCC_SRDAMR_I2C4AMEN)
+#endif
+#if defined(RCC_SRDAMR_LPTIM2AMEN)
+#define __HAL_RCC_LPTIM2_CLKAM_ENABLE()           (RCC->SRDAMR) |= (RCC_SRDAMR_LPTIM2AMEN)
+#endif
+#if defined(RCC_SRDAMR_LPTIM3AMEN)
+#define __HAL_RCC_LPTIM3_CLKAM_ENABLE()           (RCC->SRDAMR) |= (RCC_SRDAMR_LPTIM3AMEN)
+#endif
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_CLKAM_ENABLE()             (RCC->SRDAMR) |= (RCC_SRDAMR_DAC2AMEN)
+#endif
+#if defined(RCC_SRDAMR_COMP12AMEN)
+#define __HAL_RCC_COMP12_CLKAM_ENABLE()           (RCC->SRDAMR) |= (RCC_SRDAMR_COMP12AMEN)
+#endif
+#if defined(RCC_SRDAMR_VREFAMEN)
+#define __HAL_RCC_VREF_CLKAM_ENABLE()             (RCC->SRDAMR) |= (RCC_SRDAMR_VREFAMEN)
+#endif
+#if defined(RCC_SRDAMR_RTCAMEN)
+#define __HAL_RCC_RTC_CLKAM_ENABLE()              (RCC->SRDAMR) |= (RCC_SRDAMR_RTCAMEN)
+#endif
+#if defined(RCC_SRDAMR_DTSAMEN)
+#define __HAL_RCC_DTS_CLKAM_ENABLE()              (RCC->SRDAMR) |= (RCC_SRDAMR_DTSAMEN)
+#endif
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_CLKAM_ENABLE()           (RCC->SRDAMR) |= (RCC_SRDAMR_DFSDM2AMEN)
+#endif
+#if defined(RCC_SRDAMR_BKPRAMAMEN)
+#define __HAL_RCC_BKPRAM_CLKAM_ENABLE()           (RCC->SRDAMR) |= (RCC_SRDAMR_BKPRAMAMEN)
+#endif
+#if defined(RCC_SRDAMR_SRDSRAMAMEN)
+#define __HAL_RCC_SRDSRAM_CLKAM_ENABLE()          (RCC->SRDAMR) |= (RCC_SRDAMR_SRDSRAMAMEN)
+#endif
+
+#if defined(RCC_D3AMR_BDMAAMEN)
+#define __HAL_RCC_BDMA_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_BDMAAMEN)
+#endif
+#if defined(RCC_D3AMR_LPUART1AMEN)
+#define __HAL_RCC_LPUART1_CLKAM_DISABLE()          (RCC->D3AMR) &= ~ (RCC_D3AMR_LPUART1AMEN)
+#endif
+#if defined(RCC_D3AMR_SPI6AMEN)
+#define __HAL_RCC_SPI6_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_SPI6AMEN)
+#endif
+#if defined(RCC_D3AMR_I2C4AMEN)
+#define __HAL_RCC_I2C4_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_I2C4AMEN)
+#endif
+#if defined(RCC_D3AMR_LPTIM2AMEN)
+#define __HAL_RCC_LPTIM2_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM2AMEN)
+#endif
+#if defined(RCC_D3AMR_LPTIM3AMEN)
+#define __HAL_RCC_LPTIM3_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM3AMEN)
+#endif
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM4AMEN)
+#endif
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM5AMEN)
+#endif
+#if defined(RCC_D3AMR_COMP12AMEN)
+#define __HAL_RCC_COMP12_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_COMP12AMEN)
+#endif
+#if defined(RCC_D3AMR_VREFAMEN)
+#define __HAL_RCC_VREF_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_VREFAMEN)
+#endif
+#if defined(RCC_D3AMR_RTCAMEN)
+#define __HAL_RCC_RTC_CLKAM_DISABLE()              (RCC->D3AMR) &= ~ (RCC_D3AMR_RTCAMEN)
+#endif
+#if defined(RCC_D3AMR_CRCAMEN)
+#define __HAL_RCC_CRC_CLKAM_DISABLE()              (RCC->D3AMR) &= ~ (RCC_D3AMR_CRCAMEN)
+#endif
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_SAI4AMEN)
+#endif
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_ADC3AMEN)
+#endif
+#if defined(RCC_D3AMR_BKPRAMAMEN)
+#define __HAL_RCC_BKPRAM_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_BKPRAMAMEN)
+#endif
+#if defined(RCC_D3AMR_SRAM4AMEN)
+#define __HAL_RCC_D3SRAM1_CLKAM_DISABLE()          (RCC->D3AMR)&= ~ (RCC_D3AMR_SRAM4AMEN)
+#endif
+
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_CLKAM_DISABLE()            (RCC->SRDAMR) &= ~ (RCC_SRDAMR_BDMA2AMEN)
+#endif
+#if defined(RCC_SRDAMR_GPIOAMEN)
+#define __HAL_RCC_GPIO_CLKAM_DISABLE()             (RCC->SRDAMR) &= ~ (RCC_SRDAMR_GPIOAMEN)
+#endif
+#if defined(RCC_SRDAMR_LPUART1AMEN)
+#define __HAL_RCC_LPUART1_CLKAM_DISABLE()          (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPUART1AMEN)
+#endif
+#if defined(RCC_SRDAMR_SPI6AMEN)
+#define __HAL_RCC_SPI6_CLKAM_DISABLE()             (RCC->SRDAMR) &= ~ (RCC_SRDAMR_SPI6AMEN)
+#endif
+#if defined(RCC_SRDAMR_I2C4AMEN)
+#define __HAL_RCC_I2C4_CLKAM_DISABLE()             (RCC->SRDAMR) &= ~ (RCC_SRDAMR_I2C4AMEN)
+#endif
+#if defined(RCC_SRDAMR_LPTIM2AMEN)
+#define __HAL_RCC_LPTIM2_CLKAM_DISABLE()           (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPTIM2AMEN)
+#endif
+#if defined(RCC_SRDAMR_LPTIM3AMEN)
+#define __HAL_RCC_LPTIM3_CLKAM_DISABLE()           (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPTIM3AMEN)
+#endif
+#if defined(RCC_SRDAMR_DAC2AMEN)
+#define __HAL_RCC_DAC2_CLKAM_DISABLE()             (RCC->SRDAMR) &= ~ (RCC_SRDAMR_DAC2AMEN)
+#endif
+#if defined(RCC_SRDAMR_COMP12AMEN)
+#define __HAL_RCC_COMP12_CLKAM_DISABLE()           (RCC->SRDAMR) &= ~ (RCC_SRDAMR_COMP12AMEN)
+#endif
+#if defined(RCC_SRDAMR_VREFAMEN)
+#define __HAL_RCC_VREF_CLKAM_DISABLE()             (RCC->SRDAMR) &= ~ (RCC_SRDAMR_VREFAMEN)
+#endif
+#if defined(RCC_SRDAMR_RTCAMEN)
+#define __HAL_RCC_RTC_CLKAM_DISABLE()              (RCC->SRDAMR) &= ~(RCC_SRDAMR_RTCAMEN)
+#endif
+#if defined(RCC_SRDAMR_DTSAMEN)
+#define __HAL_RCC_DTS_CLKAM_DISABLE()              (RCC->SRDAMR) &= ~(RCC_SRDAMR_DTSAMEN)
+#endif
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_CLKAM_DISABLE()           (RCC->SRDAMR) &= ~(RCC_SRDAMR_DFSDM2AMEN)
+#endif
+#if defined(RCC_SRDAMR_BKPRAMAMEN)
+#define __HAL_RCC_BKPRAM_CLKAM_DISABLE()           (RCC->SRDAMR) &= ~ (RCC_SRDAMR_BKPRAMAMEN)
+#endif
+#if defined(RCC_SRDAMR_SRDSRAMAMEN)
+#define __HAL_RCC_SRDSRAM_CLKAM_DISABLE()          (RCC->SRDAMR) &= ~ (RCC_SRDAMR_SRDSRAMAMEN)
+#endif
+
+
+#if defined(RCC_CKGAENR_AXICKG)
+    /** @brief  Macro to enable or disable the RCC_CKGAENR bits (AXI clocks gating enable register).
+  * @note
+  * @note
+  * @note
+  * @param
+  * @note
+  */
+
+#define __HAL_RCC_AXI_CLKGA_ENABLE()             (RCC->CKGAENR) |= (RCC_CKGAENR_AXICKG)
+#define __HAL_RCC_AHB_CLKGA_ENABLE()             (RCC->CKGAENR) |= (RCC_CKGAENR_AHBCKG)
+#define __HAL_RCC_CPU_CLKGA_ENABLE()             (RCC->CKGAENR) |= (RCC_CKGAENR_CPUCKG)
+#define __HAL_RCC_SDMMC_CLKGA_ENABLE()           (RCC->CKGAENR) |= (RCC_CKGAENR_SDMMCCKG)
+#define __HAL_RCC_MDMA_CLKGA_ENABLE()            (RCC->CKGAENR) |= (RCC_CKGAENR_MDMACKG)
+#define __HAL_RCC_DMA2D_CLKGA_ENABLE()           (RCC->CKGAENR) |= (RCC_CKGAENR_DMA2DCKG)
+#define __HAL_RCC_LTDC_CLKGA_ENABLE()            (RCC->CKGAENR) |= (RCC_CKGAENR_LTDCCKG)
+#define __HAL_RCC_GFXMMUM_CLKGA_ENABLE()         (RCC->CKGAENR) |= (RCC_CKGAENR_GFXMMUMCKG)
+#define __HAL_RCC_AHB12_CLKGA_ENABLE()           (RCC->CKGAENR) |= (RCC_CKGAENR_AHB12CKG)
+#define __HAL_RCC_AHB34_CLKGA_ENABLE()           (RCC->CKGAENR) |= (RCC_CKGAENR_AHB34CKG)
+#define __HAL_RCC_FLIFT_CLKGA_ENABLE()           (RCC->CKGAENR) |= (RCC_CKGAENR_FLIFTCKG)
+#define __HAL_RCC_OCTOSPI2_CLKGA_ENABLE()        (RCC->CKGAENR) |= (RCC_CKGAENR_OCTOSPI2CKG)
+#define __HAL_RCC_FMC_CLKGA_ENABLE()             (RCC->CKGAENR) |= (RCC_CKGAENR_FMCCKG)
+#define __HAL_RCC_OCTOSPI1_CLKGA_ENABLE()        (RCC->CKGAENR) |= (RCC_CKGAENR_OCTOSPI1CKG)
+#define __HAL_RCC_AXIRAM1_CLKGA_ENABLE()         (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM1CKG)
+#define __HAL_RCC_AXIRAM2_CLKGA_ENABLE()         (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM2CKG)
+#define __HAL_RCC_AXIRAM3_CLKGA_ENABLE()         (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM3CKG)
+#define __HAL_RCC_GFXMMUS_CLKGA_ENABLE()         (RCC->CKGAENR) |= (RCC_CKGAENR_GFXMMUSCKG)
+#define __HAL_RCC_ECCRAM_CLKGA_ENABLE()          (RCC->CKGAENR) |= (RCC_CKGAENR_ECCRAMCKG)
+#define __HAL_RCC_EXTI_CLKGA_ENABLE()            (RCC->CKGAENR) |= (RCC_CKGAENR_EXTICKG)
+#define __HAL_RCC_JTAG_CLKGA_ENABLE()            (RCC->CKGAENR) |= (RCC_CKGAENR_JTAGCKG)
+
+
+#define __HAL_RCC_AXI_CLKGA_DISABLE()             (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXICKG)
+#define __HAL_RCC_AHB_CLKGA_DISABLE()             (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHBCKG)
+#define __HAL_RCC_CPU_CLKGA_DISABLE()             (RCC->CKGAENR) &= ~ (RCC_CKGAENR_CPUCKG)
+#define __HAL_RCC_SDMMC_CLKGA_DISABLE()           (RCC->CKGAENR) &= ~ (RCC_CKGAENR_SDMMCCKG)
+#define __HAL_RCC_MDMA_CLKGA_DISABLE()            (RCC->CKGAENR) &= ~ (RCC_CKGAENR_MDMACKG)
+#define __HAL_RCC_DMA2D_CLKGA_DISABLE()           (RCC->CKGAENR) &= ~ (RCC_CKGAENR_DMA2DCKG)
+#define __HAL_RCC_LTDC_CLKGA_DISABLE()            (RCC->CKGAENR) &= ~ (RCC_CKGAENR_LTDCCKG)
+#define __HAL_RCC_GFXMMUM_CLKGA_DISABLE()         (RCC->CKGAENR) &= ~ (RCC_CKGAENR_GFXMMUMCKG)
+#define __HAL_RCC_AHB12_CLKGA_DISABLE()           (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHB12CKG)
+#define __HAL_RCC_AHB34_CLKGA_DISABLE()           (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHB34CKG)
+#define __HAL_RCC_FLIFT_CLKGA_DISABLE()           (RCC->CKGAENR) &= ~ (RCC_CKGAENR_FLIFTCKG)
+#define __HAL_RCC_OCTOSPI2_CLKGA_DISABLE()        (RCC->CKGAENR) &= ~ (RCC_CKGAENR_OCTOSPI2CKG)
+#define __HAL_RCC_FMC_CLKGA_DISABLE()             (RCC->CKGAENR) &= ~ (RCC_CKGAENR_FMCCKG)
+#define __HAL_RCC_OCTOSPI1_CLKGA_DISABLE()        (RCC->CKGAENR) &= ~ (RCC_CKGAENR_OCTOSPI1CKG)
+#define __HAL_RCC_AXIRAM1_CLKGA_DISABLE()         (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM1CKG)
+#define __HAL_RCC_AXIRAM2_CLKGA_DISABLE()         (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM2CKG)
+#define __HAL_RCC_AXIRAM3_CLKGA_DISABLE()         (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM3CKG)
+#define __HAL_RCC_GFXMMUS_CLKGA_DISABLE()         (RCC->CKGAENR) &= ~ (RCC_CKGAENR_GFXMMUSCKG)
+#define __HAL_RCC_ECCRAM_CLKGA_DISABLE()          (RCC->CKGAENR) &= ~ (RCC_CKGAENR_ECCRAMCKG)
+#define __HAL_RCC_EXTI_CLKGA_DISABLE()            (RCC->CKGAENR) &= ~ (RCC_CKGAENR_EXTICKG)
+#define __HAL_RCC_JTAG_CLKGA_DISABLE()            (RCC->CKGAENR) &= ~ (RCC_CKGAENR_JTAGCKG)
+
+#endif /* RCC_CKGAENR_AXICKG */
+
+
+
+
+/** @brief  Macro to enable or disable the Internal High Speed oscillator (HSI).
+  * @note     After enabling the HSI, the application software should wait on
+  *           HSIRDY flag to be set indicating that HSI clock is stable and can
+  *           be used to clock the PLL and/or system clock.
+  * @note     HSI can not be stopped if it is used directly or through the PLL
+  *           as system clock. In this case, you have to select another source
+  *           of the system clock then stop the HSI.
+  * @note     The HSI is stopped by hardware when entering STOP and STANDBY modes.
+  * @param    __STATE__ specifies the new state of the HSI.
+  *           This parameter can be one of the following values:
+  *            @arg RCC_HSI_OFF turn OFF the HSI oscillator
+  *            @arg RCC_HSI_ON turn ON the HSI oscillator
+  *            @arg RCC_HSI_DIV1 turn ON the HSI oscillator and divide it by 1 (default after reset)
+  *            @arg RCC_HSI_DIV2 turn ON the HSI oscillator and divide it by 2
+  *            @arg RCC_HSI_DIV4 turn ON the HSI oscillator and divide it by 4
+  *            @arg RCC_HSI_DIV8 turn ON the HSI oscillator and divide it by 8
+  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
+  *         clock cycles.
+  */
+#define __HAL_RCC_HSI_CONFIG(__STATE__) \
+                  MODIFY_REG(RCC->CR, RCC_CR_HSION | RCC_CR_HSIDIV , (uint32_t)(__STATE__))
+
+
+/** @brief  Macro to get the HSI divider.
+  * @retval The HSI divider. The returned value can be one
+  *         of the following:
+  *            - RCC_CR_HSIDIV_1  HSI oscillator divided by 1 (default after reset)
+  *            - RCC_CR_HSIDIV_2  HSI oscillator divided by 2
+  *            - RCC_CR_HSIDIV_4  HSI oscillator divided by 4
+  *            - RCC_CR_HSIDIV_8  HSI oscillator divided by 8
+  */
+#define __HAL_RCC_GET_HSI_DIVIDER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV)))
+
+/** @brief  Macros to enable or disable the Internal High Speed oscillator (HSI).
+  * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
+  *         It is used (enabled by hardware) as system clock source after start-up
+  *         from Reset, wakeup from STOP and STANDBY mode, or in case of failure
+  *         of the HSE used directly or indirectly as system clock (if the Clock
+  *         Security System CSS is enabled).
+  * @note   HSI can not be stopped if it is used as system clock source. In this case,
+  *         you have to select another source of the system clock then stop the HSI.
+  * @note   After enabling the HSI, the application software should wait on HSIRDY
+  *         flag to be set indicating that HSI clock is stable and can be used as
+  *         system clock source.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
+  *         clock cycles.
+  */
+#define __HAL_RCC_HSI_ENABLE()  SET_BIT(RCC->CR, RCC_CR_HSION)
+#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
+
+
+/** @brief  Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
+  * @note   The calibration is used to compensate for the variations in voltage
+  *         and temperature that influence the frequency of the internal HSI RC.
+  * @param  __HSICalibrationValue__: specifies the calibration trimming value.
+  *         This parameter must be a number between 0 and 0x7F (3F for Rev Y device).
+  */
+#if defined(RCC_VER_X)
+#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__)                                                                   \
+           do {                                                                                                                          \
+              if(HAL_GetREVID() <= REV_ID_Y)                                                                                             \
+             {                                                                                                                           \
+               MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk, (uint32_t)(__HSICalibrationValue__) << HAL_RCC_REV_Y_HSITRIM_Pos);    \
+             }                                                                                                                           \
+             else                                                                                                                        \
+             {                                                                                                                           \
+               MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_HSICFGR_HSITRIM_Pos);            \
+             }                                                                                                                           \
+           } while(0)
+
+#else
+#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__)                                                                   \
+               MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_HSICFGR_HSITRIM_Pos);
+#endif /*RCC_VER_X*/
+/**
+  * @brief    Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
+  *           in STOP mode to be quickly available as kernel clock for some peripherals.
+  * @note     Keeping the HSI ON in STOP mode allows to avoid slowing down the communication
+  *           speed because of the HSI start-up time.
+  * @note     The enable of this function has not effect on the HSION bit.
+  *           This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+#define __HAL_RCC_HSISTOP_ENABLE()     SET_BIT(RCC->CR, RCC_CR_HSIKERON)
+#define __HAL_RCC_HSISTOP_DISABLE()    CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
+
+
+/**
+  * @brief  Macro to enable or disable the Internal High Speed oscillator for USB (HSI48).
+  * @note   After enabling the HSI48, the application software should wait on
+  *         HSI48RDY flag to be set indicating that HSI48 clock is stable and can
+  *         be used to clock the USB.
+  * @note   The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
+  */
+#define __HAL_RCC_HSI48_ENABLE()    SET_BIT(RCC->CR, RCC_CR_HSI48ON);
+
+#define __HAL_RCC_HSI48_DISABLE()   CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON);
+
+/**
+  * @brief  Macros to enable or disable the Internal  oscillator (CSI).
+  * @note     The CSI is stopped by hardware when entering STOP and STANDBY modes.
+  *           It is used (enabled by hardware) as system clock source after
+  *           start-up from Reset, wakeup from STOP and STANDBY mode, or in case
+  *           of failure of the HSE used directly or indirectly as system clock
+  *           (if the Clock Security System CSS is enabled).
+  * @note     CSI can not be stopped if it is used as system clock source.
+  *           In this case, you have to select another source of the system
+  *           clock then stop the CSI.
+  * @note     After enabling the CSI, the application software should wait on
+  *           CSIRDY flag to be set indicating that CSI clock is stable and can
+  *           be used as system clock source.
+  * @note     When the CSI is stopped, CSIRDY flag goes low after 6 CSI oscillator
+  *           clock cycles.
+  */
+#define __HAL_RCC_CSI_ENABLE()  SET_BIT(RCC->CR, RCC_CR_CSION)
+#define __HAL_RCC_CSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSION)
+
+/** @brief  Macro Adjusts the Internal  oscillator (CSI) calibration value.
+  * @note   The calibration is used to compensate for the variations in voltage
+  *         and temperature that influence the frequency of the internal CSI RC.
+  * @param  __CSICalibrationValue__: specifies the calibration trimming value.
+  *         This parameter must be a number between 0 and 0x1F.
+  */
+#if defined(RCC_VER_X)
+#define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__)                                                                   \
+           do {                                                                                                                          \
+             if(HAL_GetREVID() <= REV_ID_Y)                                                                                              \
+             {                                                                                                                           \
+               MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk, (uint32_t)(__CSICalibrationValue__) << HAL_RCC_REV_Y_CSITRIM_Pos);    \
+             }                                                                                                                           \
+             else                                                                                                                        \
+             {                                                                                                                           \
+               MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, (uint32_t)(__CSICalibrationValue__) << RCC_CSICFGR_CSITRIM_Pos);            \
+             }                                                                                                                           \
+           } while(0)
+
+#else
+#define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__)                                                                   \
+           do {                                                                                                                          \
+               MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, (uint32_t)(__CSICalibrationValue__) << RCC_CSICFGR_CSITRIM_Pos);            \
+               } while(0)
+
+#endif /*RCC_VER_X*/
+/**
+  * @brief    Macros to enable or disable the force of the Low-power Internal oscillator (CSI)
+  *           in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
+  * @note     Keeping the CSI ON in STOP mode allows to avoid slowing down the communication
+  *           speed because of the CSI start-up time.
+  * @note     The enable of this function has not effect on the CSION bit.
+  *           This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+#define __HAL_RCC_CSISTOP_ENABLE()     SET_BIT(RCC->CR, RCC_CR_CSIKERON)
+#define __HAL_RCC_CSISTOP_DISABLE()    CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON)
+
+
+/** @brief  Macros to enable or disable the Internal Low Speed oscillator (LSI).
+  * @note   After enabling the LSI, the application software should wait on
+  *         LSIRDY flag to be set indicating that LSI clock is stable and can
+  *         be used to clock the IWDG and/or the RTC.
+  * @note   LSI can not be disabled if the IWDG is running.
+  * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
+  *         clock cycles.
+  */
+#define __HAL_RCC_LSI_ENABLE()         SET_BIT(RCC->CSR, RCC_CSR_LSION)
+#define __HAL_RCC_LSI_DISABLE()        CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
+
+/**
+  * @brief  Macro to configure the External High Speed oscillator (__HSE__).
+  * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
+  *         software should wait on HSERDY flag to be set indicating that HSE clock
+  *         is stable and can be used to clock the PLL and/or system clock.
+  * @note   HSE state can not be changed if it is used directly or through the
+  *         PLL as system clock. In this case, you have to select another source
+  *         of the system clock then change the HSE state (ex. disable it).
+  * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
+  * @note   This function reset the CSSON bit, so if the clock security system(CSS)
+  *         was previously enabled you have to enable it again after calling this
+  *         function.
+  * @param  __STATE__: specifies the new state of the HSE.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
+  *                              6 HSE oscillator clock cycles.
+  *            @arg RCC_HSE_ON: turn ON the HSE oscillator.
+  *            @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
+  */
+#if defined(RCC_CR_HSEEXT)
+#define __HAL_RCC_HSE_CONFIG(__STATE__)                                \
+                    do {                                               \
+                      if ((__STATE__) == RCC_HSE_ON)                   \
+                      {                                                \
+                        SET_BIT(RCC->CR, RCC_CR_HSEON);                \
+                      }                                                \
+                      else if ((__STATE__) == RCC_HSE_OFF)             \
+                      {                                                \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);              \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT);             \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);             \
+                      }                                                \
+                      else if ((__STATE__) == RCC_HSE_BYPASS)          \
+                      {                                                \
+                        SET_BIT(RCC->CR, RCC_CR_HSEBYP);               \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT);             \
+                        SET_BIT(RCC->CR, RCC_CR_HSEON);                \
+                      }                                                \
+                      else if((__STATE__) == RCC_HSE_BYPASS_DIGITAL)   \
+                      {                                                \
+                        SET_BIT(RCC->CR, RCC_CR_HSEBYP);               \
+                        SET_BIT(RCC->CR, RCC_CR_HSEEXT);               \
+                        SET_BIT(RCC->CR, RCC_CR_HSEON);                \
+                      }                                                \
+                      else                                             \
+                      {                                                \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);              \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);             \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT);             \
+                      }                                                \
+                    } while(0)
+#else
+#define __HAL_RCC_HSE_CONFIG(__STATE__)                         \
+                    do {                                        \
+                      if ((__STATE__) == RCC_HSE_ON)            \
+                      {                                         \
+                        SET_BIT(RCC->CR, RCC_CR_HSEON);         \
+                      }                                         \
+                      else if ((__STATE__) == RCC_HSE_OFF)      \
+                      {                                         \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);       \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);      \
+                      }                                         \
+                      else if ((__STATE__) == RCC_HSE_BYPASS)   \
+                      {                                         \
+                        SET_BIT(RCC->CR, RCC_CR_HSEBYP);        \
+                        SET_BIT(RCC->CR, RCC_CR_HSEON);         \
+                      }                                         \
+                      else                                      \
+                      {                                         \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);       \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);      \
+                      }                                         \
+                    } while(0)
+#endif /* RCC_CR_HSEEXT */
+
+/** @defgroup RCC_LSE_Configuration LSE Configuration
+  * @{
+  */
+
+/**
+  * @brief  Macro to configure the External Low Speed oscillator (LSE).
+  * @note   Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
+  *         User should request a transition to LSE Off first and then LSE On or LSE Bypass.
+  * @note   The external input clock can have a frequency up to 1 MHz and be low swing (analog) or digital(*).
+            A duty cycle close to 50% is recommended.
+  * @note   As the LSE is in the Backup domain and write access is denied to
+  *         this domain after reset, you have to enable write access using
+  *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE
+  *         (to be done once after reset).
+  * @note   After enabling the LSE (RCC_LSE_ON, RCC_LSE_BYPASS or RCC_LSE_BYPASS_DIGITAL*), the application
+  *         software should wait on LSERDY flag to be set indicating that LSE clock
+  *         is stable and can be used to clock the RTC.
+  * @note   If the RTC is used, the LSE bypass must not be configured in digital mode but in low swing analog mode (*)
+  * @param  __STATE__: specifies the new state of the LSE.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
+  *                              6 LSE oscillator clock cycles.
+  *            @arg RCC_LSE_ON: turn ON the LSE oscillator.
+  *            @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
+  *            @arg RCC_LSE_BYPASS_DIGITAL: LSE oscillator bypassed with external digital clock. (*)
+  *
+  *         (*) Available on some STM32H7 lines only.
+  */
+#if defined(RCC_BDCR_LSEEXT)
+#define __HAL_RCC_LSE_CONFIG(__STATE__) \
+                    do {                                               \
+                      if((__STATE__) == RCC_LSE_ON)                    \
+                      {                                                \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);            \
+                      }                                                \
+                      else if((__STATE__) == RCC_LSE_OFF)              \
+                      {                                                \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);          \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);         \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);         \
+                      }                                                \
+                      else if((__STATE__) == RCC_LSE_BYPASS)           \
+                      {                                                \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);           \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);         \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);            \
+                      }                                                \
+                      else if((__STATE__) == RCC_LSE_BYPASS_DIGITAL)   \
+                      {                                                \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);           \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);           \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);            \
+                      }                                                \
+                      else                                             \
+                      {                                                \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);          \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);         \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);         \
+                      }                                                \
+                    } while(0)
+#else
+
+#define __HAL_RCC_LSE_CONFIG(__STATE__) \
+                    do {                                       \
+                      if((__STATE__) == RCC_LSE_ON)            \
+                      {                                        \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \
+                      }                                        \
+                      else if((__STATE__) == RCC_LSE_OFF)      \
+                      {                                        \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);  \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
+                      }                                        \
+                      else if((__STATE__) == RCC_LSE_BYPASS)   \
+                      {                                        \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);   \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \
+                      }                                        \
+                      else                                     \
+                      {                                        \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);  \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
+                      }                                        \
+                    } while(0)
+
+#endif /* RCC_BDCR_LSEEXT */
+/**
+  * @}
+  */
+
+/** @brief  Macros to enable or disable the the RTC clock.
+  * @note   These macros must be used only after the RTC clock source was selected.
+  */
+#define __HAL_RCC_RTC_ENABLE()         SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
+#define __HAL_RCC_RTC_DISABLE()        CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
+
+/** @brief  Macros to configure the RTC clock (RTCCLK).
+  * @note   As the RTC clock configuration bits are in the Backup domain and write
+  *         access is denied to this domain after reset, you have to enable write
+  *         access using the Power Backup Access macro before to configure
+  *         the RTC clock source (to be done once after reset).
+  * @note   Once the RTC clock is configured it can't be changed unless the
+  *         Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
+  *         a Power On Reset (POR).
+  * @param  __RTCCLKSource__: specifies the RTC clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
+  *            @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
+  *            @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
+  *                                            as RTC clock, where x:[2,31]
+  * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
+  *         work in STOP and STANDBY modes, and can be used as wakeup source.
+  *         However, when the HSE clock is used as RTC clock source, the RTC
+  *         cannot be used in STOP and STANDBY modes.
+  * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as
+  *         RTC clock source).
+  */
+#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ?    \
+                                                 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, (((__RTCCLKSource__) & 0xFFFFCFFU) >> 4)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
+
+#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__);    \
+                                                    RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU);  \
+                                                   } while (0)
+
+#define  __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
+
+
+/** @brief  Macros to force or release the Backup domain reset.
+  * @note   This function resets the RTC peripheral (including the backup registers)
+  *         and the RTC clock source selection in RCC_BDCR register.
+  * @note   The BKPSRAM is not affected by this reset.
+  */
+#define __HAL_RCC_BACKUPRESET_FORCE()   SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
+#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
+
+/** @brief  Macros to enable or disable the main PLL.
+  * @note   After enabling the main PLL, the application software should wait on
+  *         PLLRDY flag to be set indicating that PLL clock is stable and can
+  *         be used as system clock source.
+  * @note   The main PLL can not be disabled if it is used as system clock source
+  * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.
+  */
+#define __HAL_RCC_PLL_ENABLE()         SET_BIT(RCC->CR, RCC_CR_PLL1ON)
+#define __HAL_RCC_PLL_DISABLE()        CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON)
+
+/**
+  * @brief  Enables or disables each clock output (PLL_P_CLK, PLL_Q_CLK, PLL_R_CLK)
+  * @note   Enabling/disabling  those Clocks can be done only when the PLL is disabled.
+  *         This is mainly used to save Power.
+  *        (The ck_pll_p of the System PLL cannot be stopped if used as System Clock).
+  * @param  __RCC_PLL1ClockOut__: specifies the PLL clock to be outputted
+  *          This parameter can be one of the following values:
+  *            @arg RCC_PLL1_DIVP: This clock is used to generate system clock up to 400MHZ or 280MHZ(*)
+  *            @arg RCC_PLL1_DIVQ: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
+  *            @arg RCC_PLL1_DIVR: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
+  *
+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  *
+  * @retval None
+  */
+#define __HAL_RCC_PLLCLKOUT_ENABLE(__RCC_PLL1ClockOut__)   SET_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__))
+
+#define __HAL_RCC_PLLCLKOUT_DISABLE(__RCC_PLL1ClockOut__)  CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__))
+
+
+/**
+  * @brief  Enables or disables Fractional Part Of The Multiplication Factor of PLL1 VCO
+  * @note   Enabling/disabling  Fractional Part can be any time  without the need to stop the PLL1
+  * @retval None
+  */
+#define __HAL_RCC_PLLFRACN_ENABLE()   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN)
+
+#define __HAL_RCC_PLLFRACN_DISABLE()  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN)
+
+
+/**
+  * @brief  Macro to configures the main PLL clock source, multiplication and division factors.
+  * @note   This function must be used only when the main PLL is disabled.
+  *
+  * @param  __RCC_PLLSOURCE__: specifies the PLL entry clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_PLLSOURCE_CSI: CSI oscillator clock selected as PLL clock entry
+  *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
+  *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
+  * @note   This clock source (__RCC_PLLSource__) is common for the main PLL1 (main PLL) and PLL2 & PLL3 .
+  *
+  * @param  __PLLM1__: specifies the division factor for PLL VCO input clock
+  *          This parameter must be a number between 1 and 63.
+  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
+  *         frequency ranges from 1 to 16 MHz.
+  *
+  * @param  __PLLN1__: specifies the multiplication factor for PLL VCO output clock
+  *          This parameter must be a number between 4 and 512 or between 8 and 420(*).
+  * @note   You have to set the PLLN parameter correctly to ensure that the VCO
+  *         output frequency is between 150 and 420 MHz (when in medium VCO range) or
+  *         between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range)
+  *
+  * @param  __PLLP1__: specifies the division factor for system  clock.
+  *          This parameter must be a number between 2 and 128 (where odd numbers are not allowed)
+  *
+  * @param  __PLLQ1__: specifies the division factor for peripheral kernel clocks
+  *          This parameter must be a number between 1 and 128
+  *
+  * @param  __PLLR1__: specifies the division factor for peripheral kernel clocks
+  *          This parameter must be a number between 1 and 128
+  *
+  * @note   To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR)
+  *         is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible 
+  *         value to  __PLL1P__, __PLL1Q__ or __PLL1R__ parameters.
+  * @retval None
+  *
+  *  (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  */
+
+
+#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLM1__, __PLLN1__, __PLLP1__, __PLLQ1__,__PLLR1__ ) \
+                  do{ MODIFY_REG(RCC->PLLCKSELR, (RCC_PLLCKSELR_PLLSRC | RCC_PLLCKSELR_DIVM1) , ((__RCC_PLLSOURCE__) | ( (__PLLM1__) <<4U)));  \
+                      WRITE_REG (RCC->PLL1DIVR , ( (((__PLLN1__) - 1U )& RCC_PLL1DIVR_N1) | ((((__PLLP1__) -1U ) << 9U) & RCC_PLL1DIVR_P1) | \
+                                ((((__PLLQ1__) -1U) << 16U)& RCC_PLL1DIVR_Q1) | ((((__PLLR1__) - 1U) << 24U)& RCC_PLL1DIVR_R1))); \
+                    } while(0)
+
+
+/** @brief  Macro to configure the PLLs clock source.
+  * @note   This function must be used only when all PLLs are disabled.
+  * @param  __PLLSOURCE__: specifies the PLLs entry clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PLLSOURCE_CSI: CSI oscillator clock selected as PLL clock entry
+  *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
+  *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
+  *
+  */
+#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, (__PLLSOURCE__))
+
+
+/**
+  * @brief  Macro to configures the main PLL clock Fractional Part Of The Multiplication Factor
+  *
+  * @note   These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO
+  *
+  * @param  __RCC_PLL1FRACN__: specifies Fractional Part Of The Multiplication Factor for PLL1 VCO
+  *                            It should be a value between 0 and 8191
+  * @note   Warning: The software has to set correctly these bits to insure that the VCO
+  *                  output frequency is between its valid frequency range, which is:
+  *                   192 to 836 MHz or 128 to 560 MHz(*) if PLL1VCOSEL = 0
+  *                   150 to 420 MHz if PLL1VCOSEL = 1.
+  *
+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  *
+  * @retval None
+  */
+ #define  __HAL_RCC_PLLFRACN_CONFIG(__RCC_PLL1FRACN__) MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, (uint32_t)(__RCC_PLL1FRACN__) << RCC_PLL1FRACR_FRACN1_Pos)
+
+
+/** @brief  Macro to select  the PLL1  reference frequency range.
+  * @param  __RCC_PLL1VCIRange__: specifies the PLL1 input frequency range
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PLL1VCIRANGE_0: Range frequency is between 1 and 2 MHz
+  *            @arg RCC_PLL1VCIRANGE_1: Range frequency is between 2 and 4 MHz
+  *            @arg RCC_PLL1VCIRANGE_2: Range frequency is between 4 and 8 MHz
+  *            @arg RCC_PLL1VCIRANGE_3: Range frequency is between 8 and 16 MHz
+  * @retval None
+  */
+#define __HAL_RCC_PLL_VCIRANGE(__RCC_PLL1VCIRange__) \
+                  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, (__RCC_PLL1VCIRange__))
+
+
+/** @brief  Macro to select  the PLL1  reference frequency range.
+  * @param  __RCC_PLL1VCORange__: specifies the PLL1 input frequency range
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PLL1VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*)
+  *            @arg RCC_PLL1VCOMEDIUM: Range frequency is between 150 and 420 MHz
+  *
+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  *
+  * @retval None
+  */
+#define __HAL_RCC_PLL_VCORANGE(__RCC_PLL1VCORange__) \
+                  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, (__RCC_PLL1VCORange__))
+
+
+
+/** @brief  Macro to get the clock source used as system clock.
+  * @retval The clock source used as system clock. The returned value can be one
+  *         of the following:
+  *              - RCC_CFGR_SWS_CSI: CSI used as system clock.
+  *              - RCC_CFGR_SWS_HSI: HSI used as system clock.
+  *              - RCC_CFGR_SWS_HSE: HSE used as system clock.
+  *              - RCC_CFGR_SWS_PLL: PLL used as system clock.
+  */
+#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
+
+
+/**
+  * @brief Macro to configure the system clock source.
+  * @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
+  * This parameter can be one of the following values:
+  *              - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
+  *              - RCC_SYSCLKSOURCE_CSI: CSI oscillator is used as system clock source.
+  *              - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
+  *              - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
+  */
+#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
+
+/** @brief  Macro to get the oscillator used as PLL clock source.
+  * @retval The oscillator used as PLL clock source. The returned value can be one
+  *         of the following:
+  *              - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.
+  *              - RCC_PLLSOURCE_CSI: CSI oscillator is used as PLL clock source.
+  *              - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
+  *              - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
+  */
+#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC))
+
+/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
+  * @{
+  */
+
+/** @brief  Macro to configure the MCO1 clock.
+  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_PLL1QCLK:  PLL1Q clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_HSI48: HSI48 (48MHZ) selected as MCO1 source
+  * @param  __MCODIV__ specifies the MCO clock prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCODIV_1 up to RCC_MCODIV_15  : divider applied to MCO1 clock
+  */
+#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
+                 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
+
+/** @brief  Macro to configure the MCO2 clock.
+  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_PLL2PCLK: PLL2P clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_PLLCLK:  PLL1P clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_CSICLK:  CSI clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_LSICLK:  LSI clock selected as MCO2 source
+  * @param  __MCODIV__ specifies the MCO clock prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCODIV_1 up to RCC_MCODIV_15  : divider applied to MCO2 clock
+  */
+#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
+    MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 7)));
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Macro to configure the External Low Speed oscillator (LSE) drive capability.
+  * @note   As the LSE is in the Backup domain and write access is denied to
+  *         this domain after reset, you have to enable write access using
+  *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE
+  *         (to be done once after reset).
+  * @note   On STM32H7 Rev.B and above devices this can't be updated while LSE is ON.
+  * @param  __LSEDRIVE__: specifies the new state of the LSE drive capability.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.
+  *            @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.
+  *            @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.
+  *            @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.
+  * @retval None
+  */
+#if defined(RCC_VER_X)
+#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
+           do{                                                                                                                                \
+             if((HAL_GetREVID() <= REV_ID_Y) && (((__LSEDRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || ((__LSEDRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH)))  \
+             {                                                                                                                                \
+              MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (~(uint32_t)(__LSEDRIVE__)) & RCC_BDCR_LSEDRV_Msk);                                      \
+             }                                                                                                                                \
+             else                                                                                                                             \
+             {                                                                                                                                \
+               MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__));                                                              \
+             }                                                                                                                                \
+           } while(0)
+#else
+#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
+               MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__));
+#endif /*RCC_VER_X*/
+/**
+  * @brief  Macro to configure the wake up from stop clock.
+  * @param  __RCC_STOPWUCLK__: specifies the clock source used after wake up from stop
+  *         This parameter can be one of the following values:
+  *            @arg RCC_STOP_WAKEUPCLOCK_CSI: CSI selected as system clock source
+  *            @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI selected as system clock source
+  * @retval None
+  */
+#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) \
+                  MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__RCC_STOPWUCLK__))
+
+/**
+  * @brief  Macro to configure the Kernel wake up from stop clock.
+  * @param  __RCC_STOPKERWUCLK__: specifies the Kernel clock source used after wake up from stop
+  *         This parameter can be one of the following values:
+  *            @arg RCC_STOP_KERWAKEUPCLOCK_CSI: CSI selected as Kernel clock source
+  *            @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI selected as Kernel clock source
+  * @retval None
+  */
+#define __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(__RCC_STOPKERWUCLK__) \
+                  MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, (__RCC_STOPKERWUCLK__))
+
+/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
+  * @brief macros to manage the specified RCC Flags and interrupts.
+  * @{
+  */
+/** @brief  Enable RCC interrupt.
+  * @param  __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
+  *         This parameter can be any combination of the following values:
+  *            @arg RCC_IT_LSIRDY: LSI ready interrupt
+  *            @arg RCC_IT_LSERDY: LSE ready interrupt
+  *            @arg RCC_IT_CSIRDY: HSI ready interrupt
+  *            @arg RCC_IT_HSIRDY: HSI ready interrupt
+  *            @arg RCC_IT_HSERDY: HSE ready interrupt
+  *            @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
+  *            @arg RCC_IT_PLLRDY: main PLL ready interrupt
+  *            @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
+  *            @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
+  *            @arg RCC_IT_LSECSS: Clock security system interrupt
+  */
+#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
+
+/** @brief Disable RCC interrupt
+  * @param  __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
+  *         This parameter can be any combination of the following values:
+  *            @arg RCC_IT_LSIRDY: LSI ready interrupt
+  *            @arg RCC_IT_LSERDY: LSE ready interrupt
+  *            @arg RCC_IT_CSIRDY: HSI ready interrupt
+  *            @arg RCC_IT_HSIRDY: HSI ready interrupt
+  *            @arg RCC_IT_HSERDY: HSE ready interrupt
+  *            @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
+  *            @arg RCC_IT_PLLRDY: main PLL ready interrupt
+  *            @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
+  *            @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
+  *            @arg RCC_IT_LSECSS: Clock security system interrupt
+  */
+#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
+
+/** @brief  Clear the RCC's interrupt pending bits
+  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
+  *         This parameter can be any combination of the following values:
+  *            @arg RCC_IT_LSIRDY: LSI ready interrupt
+  *            @arg RCC_IT_LSERDY: LSE ready interrupt
+  *            @arg RCC_IT_CSIRDY: CSI ready interrupt
+  *            @arg RCC_IT_HSIRDY: HSI ready interrupt
+  *            @arg RCC_IT_HSERDY: HSE ready interrupt
+  *            @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
+  *            @arg RCC_IT_PLLRDY: main PLL ready interrupt
+  *            @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
+  *            @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
+  *            @arg RCC_IT_HSECSS: HSE Clock Security interrupt
+  *            @arg RCC_IT_LSECSS: Clock security system interrupt
+  */
+#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
+
+/** @brief  Check the RCC's interrupt has occurred or not.
+  * @param  __INTERRUPT__: specifies the RCC interrupt source to check.
+  *         This parameter can be any combination of the following values:
+  *            @arg RCC_IT_LSIRDY: LSI ready interrupt
+  *            @arg RCC_IT_LSERDY: LSE ready interrupt
+  *            @arg RCC_IT_CSIRDY: CSI ready interrupt
+  *            @arg RCC_IT_HSIRDY: HSI ready interrupt
+  *            @arg RCC_IT_HSERDY: HSE ready interrupt
+  *            @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
+  *            @arg RCC_IT_PLLRDY: main PLL ready interrupt
+  *            @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
+  *            @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
+  *            @arg RCC_IT_HSECSS: HSE Clock Security interrupt
+  *            @arg RCC_IT_LSECSS: Clock security system interrupt
+  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+  */
+#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/** @brief Set RMVF bit to clear the reset flags.
+  */
+#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->RSR |= RCC_RSR_RMVF)
+
+#if defined(DUAL_CORE)
+#define __HAL_RCC_C1_CLEAR_RESET_FLAGS() (RCC_C1->RSR |= RCC_RSR_RMVF)
+
+#define __HAL_RCC_C2_CLEAR_RESET_FLAGS() (RCC_C2->RSR |= RCC_RSR_RMVF)
+#endif /*DUAL_CORE*/
+
+#if defined(DUAL_CORE)
+/** @brief  Check RCC flag is set or not.
+  * @param  __FLAG__: specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
+  *            @arg RCC_FLAG_HSIDIV: HSI divider flag
+  *            @arg RCC_FLAG_CSIRDY: CSI oscillator clock ready
+  *            @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready
+  *            @arg RCC_FLAG_HSERDY:  HSE oscillator clock ready
+  *            @arg RCC_FLAG_D1CKRDY:  Domain1 clock ready
+  *            @arg RCC_FLAG_D2CKRDY:  Domain2 clock ready
+  *            @arg RCC_FLAG_PLLRDY:  PLL1 clock ready
+  *            @arg RCC_FLAG_PLL2RDY: PLL2 clock ready
+  *            @arg RCC_FLAG_PLL3RDY: PLL3 clock ready
+  *            @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
+  *            @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
+  *            @arg RCC_FLAG_C1RST:  CPU reset flag
+  *            @arg RCC_FLAG_C2RST:  CPU2 reset flag
+  *            @arg RCC_FLAG_D1RST:  D1 domain power switch reset flag
+  *            @arg RCC_FLAG_D2RST:  D2 domain power switch reset flag
+  *            @arg RCC_FLAG_BORRST: BOR reset flag
+  *            @arg RCC_FLAG_PINRST: Pin reset
+  *            @arg RCC_FLAG_PORRST: POR/PDR  reset
+  *            @arg RCC_FLAG_SFTR1ST: System reset from CPU reset flag
+  *            @arg RCC_FLAG_SFTR2ST: System reset from CPU2 reset flag
+  *            @arg RCC_FLAG_BORRST:   D2 domain power switch reset flag
+  *            @arg RCC_FLAG_IWDG1RST: CPU Independent Watchdog reset
+  *            @arg RCC_FLAG_IWDG2RST: CPU2 Independent Watchdog reset
+  *            @arg RCC_FLAG_WWDG2RST: Window Watchdog2 reset
+  *            @arg RCC_FLAG_WWDG1RST: Window Watchdog1 reset
+  *            @arg RCC_FLAG_LPWR1RST: Reset due to illegal D1 DSTANDBY or CPU CSTOP flag
+  *            @arg RCC_FLAG_LPWR2RST: Reset due to illegal D2 DSTANDBY or CPU2 CSTOP flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define RCC_FLAG_MASK  ((uint8_t)0x1F)
+#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
+((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC->RSR :RCC->CIFR))))  & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
+
+#define __HAL_RCC_C1_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
+((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC_C1->RSR :RCC->CIFR))))  & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
+
+#define __HAL_RCC_C2_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
+((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC_C2->RSR :RCC->CIFR))))  & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
+
+#else
+
+/** @brief  Check RCC flag is set or not.
+  * @param  __FLAG__: specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
+  *            @arg RCC_FLAG_HSIDIV: HSI divider flag
+  *            @arg RCC_FLAG_CSIRDY: CSI oscillator clock ready
+  *            @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready
+  *            @arg RCC_FLAG_HSERDY:  HSE oscillator clock ready
+  *            @arg RCC_FLAG_D1CKRDY:  Domain1 clock ready (*)
+  *            @arg RCC_FLAG_D2CKRDY:  Domain2 clock ready (*)
+  *            @arg RCC_FLAG_CPUCKRDY: CPU Domain clock ready (CPU, APB3, bus matrix1 and related memories) (*)
+  *            @arg RCC_FLAG_CDCKRDY:  CPU Domain clock ready (*)
+  *            @arg RCC_FLAG_PLLRDY:  PLL1 clock ready
+  *            @arg RCC_FLAG_PLL2RDY: PLL2 clock ready
+  *            @arg RCC_FLAG_PLL3RDY: PLL3 clock ready
+  *            @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
+  *            @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
+  *            @arg RCC_FLAG_CPURST: CPU reset flag
+  *            @arg RCC_FLAG_D1RST:  D1 domain power switch reset flag (*)
+  *            @arg RCC_FLAG_D2RST:  D2 domain power switch reset flag (*)
+  *            @arg RCC_FLAG_CDRST:  CD domain power switch reset flag (*)
+  *            @arg RCC_FLAG_BORRST: BOR reset flag
+  *            @arg RCC_FLAG_PINRST: Pin reset
+  *            @arg RCC_FLAG_PORRST: POR/PDR  reset
+  *            @arg RCC_FLAG_SFTRST: System reset from CPU reset flag
+  *            @arg RCC_FLAG_BORRST:   D2 domain power switch reset flag
+  *            @arg RCC_FLAG_IWDG1RST: CPU Independent Watchdog reset
+  *            @arg RCC_FLAG_WWDG1RST: Window Watchdog1 reset
+  *            @arg RCC_FLAG_LPWR1RST: Reset due to illegal D1 DSTANDBY or CPU CSTOP flag
+  *            @arg RCC_FLAG_LPWR2RST: Reset due to illegal D2 DSTANDBY flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  *
+  *  (*) Available on some STM32H7 lines only.
+  */
+#define RCC_FLAG_MASK  ((uint8_t)0x1F)
+#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
+((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC->RSR :RCC->CIFR))))  & (1UL << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
+#endif /*DUAL_CORE*/
+
+/**
+  * @}
+  */
+
+#define RCC_GET_PLL_OSCSOURCE() ((RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC) >> RCC_PLLCKSELR_PLLSRC_Pos)
+
+/**
+  * @}
+  */
+
+/* Include RCC HAL Extension module */
+#include "stm32h7xx_hal_rcc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+ /** @addtogroup RCC_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup RCC_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de-initialization functions  ******************************/
+HAL_StatusTypeDef HAL_RCC_DeInit(void);
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
+
+/**
+  * @}
+  */
+
+/** @addtogroup RCC_Exported_Functions_Group2
+  * @{
+  */
+/* Peripheral Control functions  ************************************************/
+void     HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
+void     HAL_RCC_EnableCSS(void);
+void     HAL_RCC_DisableCSS(void);
+uint32_t HAL_RCC_GetSysClockFreq(void);
+uint32_t HAL_RCC_GetHCLKFreq(void);
+uint32_t HAL_RCC_GetPCLK1Freq(void);
+uint32_t HAL_RCC_GetPCLK2Freq(void);
+void     HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
+void     HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
+/* CSS NMI IRQ handler */
+void     HAL_RCC_NMI_IRQHandler(void);
+/* User Callbacks in non blocking mode (IT mode) */
+void     HAL_RCC_CCSCallback(void);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RCC_Private_Constants RCC Private Constants
+  * @{
+  */
+
+#define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT
+#define HSI_TIMEOUT_VALUE          (2U)    /* 2 ms */
+#define HSI48_TIMEOUT_VALUE        (2U)    /* 2 ms */
+#define CSI_TIMEOUT_VALUE          (2U)    /* 2 ms */
+#define LSI_TIMEOUT_VALUE          (2U)    /* 2 ms */
+#define PLL_TIMEOUT_VALUE          (2U)    /* 2 ms */
+#define CLOCKSWITCH_TIMEOUT_VALUE  (5000U) /* 5 s  */
+#define RCC_DBP_TIMEOUT_VALUE      (100U)
+#define RCC_LSE_TIMEOUT_VALUE      LSE_STARTUP_TIMEOUT
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RCC_Private_Macros RCC Private Macros
+  * @{
+  */
+
+/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
+  * @{
+  */
+
+#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE)                           || \
+                                           (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
+                                           (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
+                                           (((OSCILLATOR) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) || \
+                                           (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
+                                           (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \
+                                           (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48))
+
+#if defined(RCC_CR_HSEEXT)
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
+                         ((HSE) == RCC_HSE_BYPASS) || ((HSE) == RCC_HSE_BYPASS_DIGITAL))
+#else
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
+                         ((HSE) == RCC_HSE_BYPASS))
+#endif /* RCC_CR_HSEEXT */
+
+#if defined(RCC_BDCR_LSEEXT)
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
+                         ((LSE) == RCC_LSE_BYPASS) || ((LSE) == RCC_LSE_BYPASS_DIGITAL))
+#else
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
+                         ((LSE) == RCC_LSE_BYPASS))
+#endif /* RCC_BDCR_LSEEXT */
+
+#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON)    || \
+                         ((HSI) == RCC_HSI_DIV1) || ((HSI) == RCC_HSI_DIV2) || \
+                         ((HSI) == RCC_HSI_DIV4) || ((HSI) == RCC_HSI_DIV8))
+
+#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON))
+
+#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
+
+#define IS_RCC_CSI(CSI) (((CSI) == RCC_CSI_OFF) || ((CSI) == RCC_CSI_ON))
+
+#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || \
+                         ((PLL) == RCC_PLL_ON))
+
+#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_CSI)  || \
+                                  ((SOURCE) == RCC_PLLSOURCE_HSI)  || \
+                                  ((SOURCE) == RCC_PLLSOURCE_NONE) || \
+                                  ((SOURCE) == RCC_PLLSOURCE_HSE))
+#define IS_RCC_PLLM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))
+#if !defined(RCC_VER_2_0)
+#define IS_RCC_PLLN_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))
+#else
+#define IS_RCC_PLLN_VALUE(VALUE) ((8U <= (VALUE)) && ((VALUE) <= 420U))
+#endif /* !RCC_VER_2_0 */
+#define IS_RCC_PLLP_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
+#define IS_RCC_PLLQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
+#define IS_RCC_PLLR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
+
+#define IS_RCC_PLLCLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL1_DIVP) || \
+                                         ((VALUE) == RCC_PLL1_DIVQ) || \
+                                         ((VALUE) == RCC_PLL1_DIVR))
+
+#define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 0x3FU))
+
+#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_CSI) || \
+                                     ((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
+                                     ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
+                                     ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
+
+#define IS_RCC_SYSCLK(SYSCLK) (((SYSCLK) == RCC_SYSCLK_DIV1)   || ((SYSCLK) == RCC_SYSCLK_DIV2)   || \
+                               ((SYSCLK) == RCC_SYSCLK_DIV4)   || ((SYSCLK) == RCC_SYSCLK_DIV8)   || \
+                               ((SYSCLK) == RCC_SYSCLK_DIV16)  || ((SYSCLK) == RCC_SYSCLK_DIV64)  || \
+                               ((SYSCLK) == RCC_SYSCLK_DIV128) || ((SYSCLK) == RCC_SYSCLK_DIV256) || \
+                               ((SYSCLK) == RCC_SYSCLK_DIV512))
+
+
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_HCLK_DIV1)   || ((HCLK) == RCC_HCLK_DIV2)   || \
+                           ((HCLK) == RCC_HCLK_DIV4)   || ((HCLK) == RCC_HCLK_DIV8)   || \
+                           ((HCLK) == RCC_HCLK_DIV16)  || ((HCLK) == RCC_HCLK_DIV64)  || \
+                           ((HCLK) == RCC_HCLK_DIV128) || ((HCLK) == RCC_HCLK_DIV256) || \
+                           ((HCLK) == RCC_HCLK_DIV512))
+
+#define IS_RCC_CDPCLK1(CDPCLK1) (((CDPCLK1) == RCC_APB3_DIV1) || ((CDPCLK1) == RCC_APB3_DIV2) || \
+                                 ((CDPCLK1) == RCC_APB3_DIV4) || ((CDPCLK1) == RCC_APB3_DIV8) || \
+                                 ((CDPCLK1) == RCC_APB3_DIV16))
+
+#define IS_RCC_D1PCLK1 IS_RCC_CDPCLK1  /* for legacy compatibility between H7 lines */
+
+#define IS_RCC_PCLK1(PCLK1) (((PCLK1) == RCC_APB1_DIV1) || ((PCLK1) == RCC_APB1_DIV2) || \
+                             ((PCLK1) == RCC_APB1_DIV4) || ((PCLK1) == RCC_APB1_DIV8) || \
+                            ((PCLK1) == RCC_APB1_DIV16))
+
+#define IS_RCC_PCLK2(PCLK2) (((PCLK2) == RCC_APB2_DIV1) || ((PCLK2) == RCC_APB2_DIV2) || \
+                             ((PCLK2) == RCC_APB2_DIV4) || ((PCLK2) == RCC_APB2_DIV8) || \
+                             ((PCLK2) == RCC_APB2_DIV16))
+
+#define IS_RCC_SRDPCLK1(SRDPCLK1) (((SRDPCLK1) == RCC_APB4_DIV1) || ((SRDPCLK1) == RCC_APB4_DIV2) || \
+                                  ((SRDPCLK1) == RCC_APB4_DIV4)  || ((SRDPCLK1) == RCC_APB4_DIV8) || \
+                                  ((SRDPCLK1) == RCC_APB4_DIV16))
+
+#define IS_RCC_D3PCLK1 IS_RCC_SRDPCLK1 /* for legacy compatibility between H7 lines*/
+
+#define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE)       || ((SOURCE) == RCC_RTCCLKSOURCE_LSI)       || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2)  || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3)  || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4)  || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5)  || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6)  || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7)  || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8)  || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9)  || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV33) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV34) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV35) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV36) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV37) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV38) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV39) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV40) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV41) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV42) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV43) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV44) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV45) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV46) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV47) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV48) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV49) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV50) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV51) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV52) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV53) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV54) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV55) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV56) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV57) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV58) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV59) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV60) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV61) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV62) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV63))
+
+#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
+
+#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE)       || \
+                                   ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLL1QCLK)  || \
+                                   ((SOURCE) == RCC_MCO1SOURCE_HSI48))
+
+#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK)    || ((SOURCE) == RCC_MCO2SOURCE_PLL2PCLK) || \
+                                   ((SOURCE) == RCC_MCO2SOURCE_HSE)       || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK)   || \
+                                   ((SOURCE) == RCC_MCO2SOURCE_CSICLK)    || ((SOURCE) == RCC_MCO2SOURCE_LSICLK))
+
+#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1)  || ((DIV) == RCC_MCODIV_2)   || \
+                            ((DIV) == RCC_MCODIV_3)  || ((DIV) == RCC_MCODIV_4)   || \
+                            ((DIV) == RCC_MCODIV_5)  || ((DIV) == RCC_MCODIV_6)   || \
+                            ((DIV) == RCC_MCODIV_7)  || ((DIV) == RCC_MCODIV_8)   || \
+                            ((DIV) == RCC_MCODIV_9)  || ((DIV) == RCC_MCODIV_10)  || \
+                            ((DIV) == RCC_MCODIV_11) || ((DIV) == RCC_MCODIV_12)  || \
+                            ((DIV) == RCC_MCODIV_13) || ((DIV) == RCC_MCODIV_14)  || \
+                            ((DIV) == RCC_MCODIV_15))
+
+#if defined(DUAL_CORE)
+#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY)    || ((FLAG) == RCC_FLAG_CSIRDY)  || \
+                           ((FLAG) == RCC_FLAG_HSI48RDY)  || ((FLAG) == RCC_FLAG_HSERDY)  || \
+                           ((FLAG) == RCC_FLAG_D1CKRDY)   || ((FLAG) == RCC_FLAG_D2CKRDY) || \
+                           ((FLAG) == RCC_FLAG_PLLRDY)    || ((FLAG) == RCC_FLAG_PLL2RDY) || \
+                           ((FLAG) == RCC_FLAG_PLL3RDY)   || ((FLAG) == RCC_FLAG_LSERDY)  || \
+                           ((FLAG) == RCC_FLAG_LSIRDY)    || \
+                           ((FLAG) == RCC_FLAG_C1RST)     || ((FLAG) == RCC_FLAG_C2RST)   || \
+                           ((FLAG) == RCC_FLAG_SFTR2ST)   || ((FLAG) == RCC_FLAG_WWDG2RST)|| \
+                           ((FLAG) == RCC_FLAG_IWDG2RST)  || ((FLAG) == RCC_FLAG_D1RST)   || \
+                           ((FLAG) == RCC_FLAG_D2RST)     || ((FLAG) == RCC_FLAG_BORRST)  || \
+                           ((FLAG) == RCC_FLAG_PINRST)    || ((FLAG) == RCC_FLAG_PORRST)  || \
+                           ((FLAG) == RCC_FLAG_SFTR1ST)   || ((FLAG) == RCC_FLAG_IWDG1RST)|| \
+                           ((FLAG) == RCC_FLAG_WWDG1RST)  || ((FLAG) == RCC_FLAG_LPWR1RST)|| \
+                           ((FLAG) == RCC_FLAG_LPWR2RST)  || ((FLAG) == RCC_FLAG_HSIDIV))
+
+#else
+
+#if defined(RCC_CR_D2CKRDY)
+#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY)    || ((FLAG) == RCC_FLAG_CSIRDY)  || \
+                           ((FLAG) == RCC_FLAG_HSI48RDY)  || ((FLAG) == RCC_FLAG_HSERDY)  || \
+                           ((FLAG) == RCC_FLAG_D1CKRDY)   || ((FLAG) == RCC_FLAG_D2CKRDY) || \
+                           ((FLAG) == RCC_FLAG_PLLRDY)    || ((FLAG) == RCC_FLAG_PLL2RDY) || \
+                           ((FLAG) == RCC_FLAG_PLL3RDY)   || ((FLAG) == RCC_FLAG_LSERDY)  || \
+                           ((FLAG) == RCC_FLAG_LSIRDY)    || \
+                           ((FLAG) == RCC_FLAG_CPURST)    || ((FLAG) == RCC_FLAG_D1RST)   || \
+                           ((FLAG) == RCC_FLAG_D2RST)     || ((FLAG) == RCC_FLAG_BORRST)  || \
+                           ((FLAG) == RCC_FLAG_PINRST)    || ((FLAG) == RCC_FLAG_PORRST)  || \
+                           ((FLAG) == RCC_FLAG_SFTRST)    || ((FLAG) == RCC_FLAG_IWDG1RST)|| \
+                           ((FLAG) == RCC_FLAG_WWDG1RST)  || ((FLAG) == RCC_FLAG_LPWR1RST)|| \
+                           ((FLAG) == RCC_FLAG_LPWR2RST)  || ((FLAG) == RCC_FLAG_HSIDIV ))
+#else
+#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY)    || ((FLAG) == RCC_FLAG_CSIRDY)  || \
+                           ((FLAG) == RCC_FLAG_HSI48RDY)  || ((FLAG) == RCC_FLAG_HSERDY)  || \
+                           ((FLAG) == RCC_FLAG_CPUCKRDY)  || ((FLAG) == RCC_FLAG_CDCKRDY) || \
+                           ((FLAG) == RCC_FLAG_PLLRDY)    || ((FLAG) == RCC_FLAG_PLL2RDY) || \
+                           ((FLAG) == RCC_FLAG_PLL3RDY)   || ((FLAG) == RCC_FLAG_LSERDY)  || \
+                           ((FLAG) == RCC_FLAG_LSIRDY)    || \
+                           ((FLAG) == RCC_FLAG_CDRST)     || ((FLAG) == RCC_FLAG_BORRST)  || \
+                           ((FLAG) == RCC_FLAG_PINRST)    || ((FLAG) == RCC_FLAG_PORRST)  || \
+                           ((FLAG) == RCC_FLAG_SFTRST)    || ((FLAG) == RCC_FLAG_IWDG1RST)|| \
+                           ((FLAG) == RCC_FLAG_WWDG1RST)  || ((FLAG) == RCC_FLAG_LPWR1RST)|| \
+                           ((FLAG) == RCC_FLAG_LPWR2RST)  || ((FLAG) == RCC_FLAG_HSIDIV ))
+#endif /* RCC_CR_D2CKRDY */
+
+#endif /*DUAL_CORE*/
+
+#define IS_RCC_HSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7FU)
+#define IS_RCC_CSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x3FU)
+
+#define IS_RCC_STOP_WAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_WAKEUPCLOCK_CSI) || \
+                                         ((SOURCE) == RCC_STOP_WAKEUPCLOCK_HSI))
+
+#define IS_RCC_STOP_KERWAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_CSI) || \
+                                          ((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_HSI))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_RCC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h
new file mode 100644
index 00000000..42beccc8
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h
@@ -0,0 +1,4262 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_rcc_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of RCC HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_RCC_EX_H
+#define STM32H7xx_HAL_RCC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup RCCEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
+  * @{
+  */
+
+/**
+  * @brief  PLL2 Clock structure definition
+  */
+typedef struct
+{
+
+  uint32_t PLL2M;       /*!< PLL2M: Division factor for PLL2 VCO input clock.
+                             This parameter must be a number between Min_Data = 1 and Max_Data = 63    */
+
+  uint32_t PLL2N;       /*!< PLL2N: Multiplication factor for PLL2 VCO output clock.
+                             This parameter must be a number between Min_Data = 4 and Max_Data = 512
+                             or between Min_Data = 8 and Max_Data = 420(*)
+                             (*) : For stm32h7a3xx and stm32h7b3xx family lines.                       */   
+
+  uint32_t PLL2P;       /*!< PLL2P: Division factor for system clock.
+                             This parameter must be a number between Min_Data = 2 and Max_Data = 128
+                             odd division factors are not allowed                                      */
+
+  uint32_t PLL2Q;        /*!< PLL2Q: Division factor for peripheral clocks.
+                             This parameter must be a number between Min_Data = 1 and Max_Data = 128   */
+
+  uint32_t PLL2R;        /*!< PLL2R: Division factor for peripheral clocks.
+                             This parameter must be a number between Min_Data = 1 and Max_Data = 128   */
+  uint32_t PLL2RGE;      /*!<PLL2RGE: PLL2 clock Input range
+                          This parameter must be a value of @ref RCC_PLL2_VCI_Range                    */
+  uint32_t PLL2VCOSEL;   /*!<PLL2VCOSEL: PLL2 clock Output range
+                          This parameter must be a value of @ref RCC_PLL2_VCO_Range                    */
+
+  uint32_t PLL2FRACN;    /*!<PLL2FRACN: Specifies Fractional Part Of The Multiplication Factor for
+                            PLL2 VCO It should be a value between 0 and 8191                           */
+}RCC_PLL2InitTypeDef;
+
+/**
+  * @brief  PLL3 Clock structure definition
+  */
+typedef struct
+{
+
+  uint32_t PLL3M;       /*!< PLL3M: Division factor for PLL3 VCO input clock.
+                             This parameter must be a number between Min_Data = 1 and Max_Data = 63    */
+
+  uint32_t PLL3N;       /*!< PLL3N: Multiplication factor for PLL3 VCO output clock.
+                             This parameter must be a number between Min_Data = 4 and Max_Data = 512
+                             or between Min_Data = 8 and Max_Data = 420(*)
+                             (*) : For stm32h7a3xx and stm32h7b3xx family lines.                       */  
+
+  uint32_t PLL3P;       /*!< PLL3P: Division factor for system clock.
+                             This parameter must be a number between Min_Data = 2 and Max_Data = 128
+                             odd division factors are not allowed                                      */
+
+  uint32_t PLL3Q;        /*!< PLL3Q: Division factor for peripheral clocks.
+                             This parameter must be a number between Min_Data = 1 and Max_Data = 128   */
+
+  uint32_t PLL3R;        /*!< PLL3R: Division factor for peripheral clocks.
+                             This parameter must be a number between Min_Data = 1 and Max_Data = 128   */
+  uint32_t PLL3RGE;      /*!<PLL3RGE: PLL3 clock Input range
+                          This parameter must be a value of @ref RCC_PLL3_VCI_Range                    */
+  uint32_t PLL3VCOSEL;   /*!<PLL3VCOSEL: PLL3 clock Output range
+                          This parameter must be a value of @ref RCC_PLL3_VCO_Range                    */
+
+  uint32_t PLL3FRACN;    /*!<PLL3FRACN: Specifies Fractional Part Of The Multiplication Factor for
+                            PLL3 VCO It should be a value between 0 and 8191                           */
+}RCC_PLL3InitTypeDef;
+
+/**
+  * @brief  RCC PLL1 Clocks structure definition
+  */
+typedef struct
+{
+  uint32_t PLL1_P_Frequency;
+  uint32_t PLL1_Q_Frequency;
+  uint32_t PLL1_R_Frequency;
+}PLL1_ClocksTypeDef;
+
+/**
+  * @brief  RCC PLL2 Clocks structure definition
+  */
+typedef struct
+{
+  uint32_t PLL2_P_Frequency;
+  uint32_t PLL2_Q_Frequency;
+  uint32_t PLL2_R_Frequency;
+}PLL2_ClocksTypeDef;
+
+/**
+  * @brief  RCC PLL3 Clocks structure definition
+  */
+typedef struct
+{
+  uint32_t PLL3_P_Frequency;
+  uint32_t PLL3_Q_Frequency;
+  uint32_t PLL3_R_Frequency;
+}PLL3_ClocksTypeDef;
+
+
+/**
+  * @brief  RCC extended clocks structure definition
+  */
+typedef struct
+{
+  uint32_t PeriphClockSelection;   /*!< The Extended Clock to be configured.
+                                        This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+  RCC_PLL2InitTypeDef PLL2;        /*!< PLL2structure parameters.
+                                        This parameter will be used only when PLL2 is selected as kernel clock Source for some peripherals */
+
+  RCC_PLL3InitTypeDef PLL3;        /*!< PLL3 structure parameters.
+                                        This parameter will be used only when PLL2 is selected as kernel clock Source for some peripherals */
+
+  uint32_t FmcClockSelection;     /*!< Specifies FMC clock source
+                                        This parameter can be a value of @ref RCCEx_FMC_Clock_Source     */
+
+#if defined(QUADSPI)
+  uint32_t QspiClockSelection;    /*!< Specifies QSPI clock source
+                                        This parameter can be a value of @ref RCCEx_QSPI_Clock_Source    */
+#endif /* QUADSPI */
+
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+  uint32_t OspiClockSelection;    /*!< Specifies OSPI clock source
+                                        This parameter can be a value of @ref RCCEx_OSPI_Clock_Source    */
+#endif /*(OCTOSPI1) || (OCTOSPI2)*/
+
+
+#if defined(DSI)
+  uint32_t DsiClockSelection;     /*!< Specifies DSI clock source
+                                     This parameter can be a value of @ref RCCEx_DSI_Clock_Source        */
+#endif /* DSI */
+
+  uint32_t SdmmcClockSelection;    /*!< Specifies SDMMC clock source
+                                        This parameter can be a value of @ref RCCEx_SDMMC_Clock_Source   */
+
+  uint32_t CkperClockSelection;   /*!< Specifies CKPER clock source
+                                        This parameter can be a value of @ref RCCEx_CLKP_Clock_Source   */
+
+  uint32_t Sai1ClockSelection;     /*!< Specifies SAI1 clock source
+                                        This parameter can be a value of @ref RCCEx_SAI1_Clock_Source    */
+
+#if defined(SAI3)
+  uint32_t Sai23ClockSelection;     /*!< Specifies SAI2/3 clock source
+                                         This parameter can be a value of @ref RCCEx_SAI23_Clock_Source  */
+#endif /* SAI3 */
+
+#if defined(RCC_CDCCIP1R_SAI2ASEL)
+  uint32_t Sai2AClockSelection;     /*!< Specifies SAI2A clock source
+                                        This parameter can be a value of @ref RCCEx_SAI2A_Clock_Source  */
+#endif /* RCC_CDCCIP1R_SAI2ASEL */
+
+#if defined(RCC_CDCCIP1R_SAI2BSEL)
+  uint32_t Sai2BClockSelection;     /*!< Specifies SAI2B clock source
+                                         This parameter can be a value of @ref RCCEx_SAI2B_Clock_Source    */
+#endif /* RCC_CDCCIP1R_SAI2BSEL */
+
+  uint32_t Spi123ClockSelection;     /*!< Specifies SPI1/2/3 clock source
+                                          This parameter can be a value of @ref RCCEx_SPI123_Clock_Source    */
+
+  uint32_t Spi45ClockSelection;     /*!< Specifies SPI4/5 clock source
+                                         This parameter can be a value of @ref RCCEx_SPI45_Clock_Source    */
+
+  uint32_t SpdifrxClockSelection;   /*!< Specifies SPDIFRX Clock clock source
+                                        This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */
+
+  uint32_t Dfsdm1ClockSelection;    /*!< Specifies DFSDM1 Clock clock source
+                                        This parameter can be a value of @ref RCCEx_DFSDM1_Clock_Source  */
+
+#if defined(DFSDM2_BASE)
+  uint32_t Dfsdm2ClockSelection;    /*!< Specifies DFSDM2 Clock clock source
+                                        This parameter can be a value of @ref RCCEx_DFSDM2_Clock_Source  */
+#endif /* DFSDM2_BASE */
+
+#if defined(FDCAN1) || defined(FDCAN2)
+  uint32_t FdcanClockSelection;   /*!< Specifies FDCAN Clock clock source
+                                        This parameter can be a value of @ref RCCEx_FDCAN_Clock_Source   */
+#endif /*FDCAN1 || FDCAN2*/
+
+  uint32_t Swpmi1ClockSelection;   /*!< Specifies SWPMI1 Clock clock source
+                                        This parameter can be a value of @ref RCCEx_SWPMI1_Clock_Source  */
+
+  uint32_t Usart234578ClockSelection;   /*!< Specifies USART2/3/4/5/7/8 clock source
+                                             This parameter can be a value of @ref RCCEx_USART234578_Clock_Source  */
+
+  uint32_t Usart16ClockSelection;  /*!< Specifies USART1/6 clock source
+                                        This parameter can be a value of @ref RCCEx_USART16_Clock_Source  */
+
+   uint32_t RngClockSelection;      /*!< Specifies RNG clock source
+                                        This parameter can be a value of @ref RCCEx_RNG_Clock_Source     */
+
+   uint32_t I2c123ClockSelection;   /*!< Specifies I2C1/2/3 clock source
+                                        This parameter can be a value of @ref RCCEx_I2C123_Clock_Source    */
+
+  uint32_t UsbClockSelection;      /*!< Specifies USB clock source
+                                        This parameter can be a value of @ref RCCEx_USB_Clock_Source     */
+
+  uint32_t CecClockSelection;     /*!< Specifies CEC clock source
+                                        This parameter can be a value of @ref RCCEx_CEC_Clock_Source     */
+
+  uint32_t Lptim1ClockSelection;   /*!< Specifies LPTIM1 clock source
+                                        This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source  */
+
+  uint32_t Lpuart1ClockSelection;  /*!< Specifies LPUART1 clock source
+                                        This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
+
+  uint32_t I2c4ClockSelection;     /*!< Specifies I2C4 clock source
+                                        This parameter can be a value of @ref RCCEx_I2C4_Clock_Source    */
+
+  uint32_t Lptim2ClockSelection;   /*!< Specifies LPTIM2 clock source
+                                        This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source  */
+
+  uint32_t Lptim345ClockSelection;   /*!< Specifies LPTIM3/4/5 clock source
+                                          This parameter can be a value of @ref RCCEx_LPTIM345_Clock_Source  */
+
+  uint32_t AdcClockSelection;      /*!< Specifies ADC interface clock source
+                                        This parameter can be a value of @ref RCCEx_ADC_Clock_Source     */
+#if defined(SAI4)
+  uint32_t Sai4AClockSelection;     /*!< Specifies SAI4A clock source
+                                        This parameter can be a value of @ref RCCEx_SAI4A_Clock_Source   */
+
+  uint32_t Sai4BClockSelection;     /*!< Specifies SAI4B clock source
+                                        This parameter can be a value of @ref RCCEx_SAI4B_Clock_Source   */
+#endif /* SAI4 */
+
+  uint32_t Spi6ClockSelection;     /*!< Specifies SPI6 clock source
+                                        This parameter can be a value of @ref RCCEx_SPI6_Clock_Source    */
+
+  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock clock source
+                                        This parameter can be a value of @ref RCC_RTC_Clock_Source       */
+
+#if defined(HRTIM1)
+  uint32_t Hrtim1ClockSelection;      /*!< Specifies HRTIM1 Clock clock source
+                                        This parameter can be a value of @ref RCCEx_HRTIM1_Clock_Source   */
+#endif /* HRTIM1 */
+
+  uint32_t TIMPresSelection;       /*!< Specifies TIM Clock Prescalers Selection.
+                                       This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */
+}RCC_PeriphCLKInitTypeDef;
+
+
+/**
+  * @brief RCC_CRS Init structure definition
+  */
+typedef struct
+{
+  uint32_t Prescaler;             /*!< Specifies the division factor of the SYNC signal.
+                                     This parameter can be a value of @ref RCCEx_CRS_SynchroDivider  */
+
+  uint32_t Source;                /*!< Specifies the SYNC signal source.
+                                     This parameter can be a value of @ref RCCEx_CRS_SynchroSource   */
+
+  uint32_t Polarity;              /*!< Specifies the input polarity for the SYNC signal source.
+                                     This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
+
+  uint32_t ReloadValue;           /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
+                                      It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)
+                                     This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
+
+  uint32_t ErrorLimitValue;       /*!< Specifies the value to be used to evaluate the captured frequency error value.
+                                     This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
+
+  uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
+                                     This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
+
+}RCC_CRSInitTypeDef;
+
+/**
+  * @brief RCC_CRS Synchronization structure definition
+  */
+typedef struct
+{
+  uint32_t ReloadValue;           /*!< Specifies the value loaded in the Counter reload value.
+                                     This parameter must be a number between 0 and 0xFFFF */
+
+  uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
+                                     This parameter must be a number between 0 and 0x3F */
+
+  uint32_t FreqErrorCapture;      /*!< Specifies the value loaded in the .FECAP, the frequency error counter
+                                                                    value latched in the time of the last SYNC event.
+                                    This parameter must be a number between 0 and 0xFFFF */
+
+  uint32_t FreqErrorDirection;    /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
+                                                                    frequency error counter latched in the time of the last SYNC event.
+                                                                    It shows whether the actual frequency is below or above the target.
+                                    This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
+
+}RCC_CRSSynchroInfoTypeDef;
+
+/**
+  * @}
+  */
+
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Constants  RCCEx Exported Constants
+  * @{
+  */
+
+/** @defgroup RCCEx_Periph_Clock_Selection  RCCEx Periph Clock Selection
+  * @{
+  */
+
+#if defined(UART9) && defined(USART10)
+#define RCC_PERIPHCLK_USART16910       (0x00000001U)
+#define RCC_PERIPHCLK_USART1           RCC_PERIPHCLK_USART16910
+#define RCC_PERIPHCLK_USART6           RCC_PERIPHCLK_USART16910
+#define RCC_PERIPHCLK_UART9            RCC_PERIPHCLK_USART16910
+#define RCC_PERIPHCLK_USART10          RCC_PERIPHCLK_USART16910
+/*alias*/
+#define RCC_PERIPHCLK_USART16          RCC_PERIPHCLK_USART16910
+#else
+#define RCC_PERIPHCLK_USART16          (0x00000001U)
+#define RCC_PERIPHCLK_USART1           RCC_PERIPHCLK_USART16
+#define RCC_PERIPHCLK_USART6           RCC_PERIPHCLK_USART16
+/* alias */
+#define RCC_PERIPHCLK_USART16910       RCC_PERIPHCLK_USART16
+#endif /* UART9 && USART10*/
+#define RCC_PERIPHCLK_USART234578      (0x00000002U)
+#define RCC_PERIPHCLK_USART2           RCC_PERIPHCLK_USART234578
+#define RCC_PERIPHCLK_USART3           RCC_PERIPHCLK_USART234578
+#define RCC_PERIPHCLK_UART4            RCC_PERIPHCLK_USART234578
+#define RCC_PERIPHCLK_UART5            RCC_PERIPHCLK_USART234578
+#define RCC_PERIPHCLK_UART7            RCC_PERIPHCLK_USART234578
+#define RCC_PERIPHCLK_UART8            RCC_PERIPHCLK_USART234578
+#define RCC_PERIPHCLK_LPUART1          (0x00000004U)
+#define RCC_PERIPHCLK_I2C123           (0x00000008U)
+#define RCC_PERIPHCLK_I2C1             RCC_PERIPHCLK_I2C123
+#define RCC_PERIPHCLK_I2C2             RCC_PERIPHCLK_I2C123
+#define RCC_PERIPHCLK_I2C3             RCC_PERIPHCLK_I2C123
+#define RCC_PERIPHCLK_I2C4             (0x00000010U)
+#define RCC_PERIPHCLK_LPTIM1           (0x00000020U)
+#define RCC_PERIPHCLK_LPTIM2           (0x00000040U)
+#define RCC_PERIPHCLK_LPTIM345         (0x00000080U)
+#define RCC_PERIPHCLK_LPTIM3           RCC_PERIPHCLK_LPTIM345
+#if defined(LPTIM4)
+#define RCC_PERIPHCLK_LPTIM4           RCC_PERIPHCLK_LPTIM345
+#endif /*LPTIM4*/
+#if defined(LPTIM5)
+#define RCC_PERIPHCLK_LPTIM5           RCC_PERIPHCLK_LPTIM345
+#endif /*LPTIM5*/
+#define RCC_PERIPHCLK_SAI1             (0x00000100U)
+#if defined(SAI3)
+#define RCC_PERIPHCLK_SAI23            (0x00000200U)
+#define RCC_PERIPHCLK_SAI2             RCC_PERIPHCLK_SAI23
+#define RCC_PERIPHCLK_SAI3             RCC_PERIPHCLK_SAI23
+#endif /* SAI3 */
+#if defined(RCC_CDCCIP1R_SAI2ASEL_0)
+#define RCC_PERIPHCLK_SAI2A            (0x00000200U)
+#endif /* RCC_CDCCIP1R_SAI2ASEL_0 */
+#if defined(RCC_CDCCIP1R_SAI2BSEL_0)
+#define RCC_PERIPHCLK_SAI2B            (0x00000400U)
+#endif /* RCC_CDCCIP1R_SAI2BSEL_0 */
+#if defined(SAI4)
+#define RCC_PERIPHCLK_SAI4A            (0x00000400U)
+#define RCC_PERIPHCLK_SAI4B            (0x00000800U)
+#endif /* SAI4 */
+#define RCC_PERIPHCLK_SPI123           (0x00001000U)
+#define RCC_PERIPHCLK_SPI1             RCC_PERIPHCLK_SPI123
+#define RCC_PERIPHCLK_SPI2             RCC_PERIPHCLK_SPI123
+#define RCC_PERIPHCLK_SPI3             RCC_PERIPHCLK_SPI123
+#define RCC_PERIPHCLK_SPI45            (0x00002000U)
+#define RCC_PERIPHCLK_SPI4             RCC_PERIPHCLK_SPI45
+#define RCC_PERIPHCLK_SPI5             RCC_PERIPHCLK_SPI45
+#define RCC_PERIPHCLK_SPI6             (0x00004000U)
+#define RCC_PERIPHCLK_FDCAN            (0x00008000U)
+#define RCC_PERIPHCLK_SDMMC            (0x00010000U)
+#define RCC_PERIPHCLK_RNG              (0x00020000U)
+#define RCC_PERIPHCLK_USB              (0x00040000U)
+#define RCC_PERIPHCLK_ADC              (0x00080000U)
+#define RCC_PERIPHCLK_SWPMI1           (0x00100000U)
+#define RCC_PERIPHCLK_DFSDM1           (0x00200000U)
+#if defined(DFSDM2_BASE)
+#define RCC_PERIPHCLK_DFSDM2           (0x00000800U)
+#endif /* DFSDM2 */
+#define RCC_PERIPHCLK_RTC              (0x00400000U)
+#define RCC_PERIPHCLK_CEC              (0x00800000U)
+#define RCC_PERIPHCLK_FMC              (0x01000000U)
+#if defined(QUADSPI)
+#define RCC_PERIPHCLK_QSPI             (0x02000000U)
+#endif /* QUADSPI */
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+#define RCC_PERIPHCLK_OSPI             (0x02000000U)
+#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
+#define RCC_PERIPHCLK_DSI              (0x04000000U)
+#define RCC_PERIPHCLK_SPDIFRX          (0x08000000U)
+#if defined(HRTIM1)
+#define RCC_PERIPHCLK_HRTIM1           (0x10000000U)
+#endif /* HRTIM1 */
+#if defined(LTDC)
+#define RCC_PERIPHCLK_LTDC             (0x20000000U)
+#endif /* LTDC */
+#define RCC_PERIPHCLK_TIM              (0x40000000U)
+#define RCC_PERIPHCLK_CKPER            (0x80000000U)
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_PLL2_Clock_Output  RCC PLL2 Clock Output
+  * @{
+  */
+#define RCC_PLL2_DIVP                RCC_PLLCFGR_DIVP2EN
+#define RCC_PLL2_DIVQ                RCC_PLLCFGR_DIVQ2EN
+#define RCC_PLL2_DIVR                RCC_PLLCFGR_DIVR2EN
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLL3_Clock_Output  RCC PLL3 Clock Output
+  * @{
+  */
+#define RCC_PLL3_DIVP                RCC_PLLCFGR_DIVP3EN
+#define RCC_PLL3_DIVQ                RCC_PLLCFGR_DIVQ3EN
+#define RCC_PLL3_DIVR                RCC_PLLCFGR_DIVR3EN
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLL2_VCI_Range  RCC PLL2 VCI Range
+  * @{
+  */
+#define RCC_PLL2VCIRANGE_0                RCC_PLLCFGR_PLL2RGE_0        /*!< Clock range frequency between 1 and 2 MHz  */
+#define RCC_PLL2VCIRANGE_1                RCC_PLLCFGR_PLL2RGE_1        /*!< Clock range frequency between 2 and 4 MHz  */
+#define RCC_PLL2VCIRANGE_2                RCC_PLLCFGR_PLL2RGE_2        /*!< Clock range frequency between 4 and 8 MHz  */
+#define RCC_PLL2VCIRANGE_3                RCC_PLLCFGR_PLL2RGE_3        /*!< Clock range frequency between 8 and 16 MHz */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_PLL2_VCO_Range  RCC PLL2 VCO Range
+  * @{
+  */
+#define RCC_PLL2VCOWIDE                 (0x00000000U)
+#define RCC_PLL2VCOMEDIUM               RCC_PLLCFGR_PLL2VCOSEL
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLL3_VCI_Range  RCC PLL3 VCI Range
+  * @{
+  */
+#define RCC_PLL3VCIRANGE_0                RCC_PLLCFGR_PLL3RGE_0         /*!< Clock range frequency between 1 and 2 MHz  */
+#define RCC_PLL3VCIRANGE_1                RCC_PLLCFGR_PLL3RGE_1         /*!< Clock range frequency between 2 and 4 MHz  */
+#define RCC_PLL3VCIRANGE_2                RCC_PLLCFGR_PLL3RGE_2         /*!< Clock range frequency between 4 and 8 MHz  */
+#define RCC_PLL3VCIRANGE_3                RCC_PLLCFGR_PLL3RGE_3         /*!< Clock range frequency between 8 and 16 MHz */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_PLL3_VCO_Range  RCC PLL3 VCO Range
+  * @{
+  */
+#define RCC_PLL3VCOWIDE                 (0x00000000U)
+#define RCC_PLL3VCOMEDIUM               RCC_PLLCFGR_PLL3VCOSEL
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_USART16_Clock_Source  RCCEx USART1/6 Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP2R_USART16SEL)
+#define RCC_USART16CLKSOURCE_D2PCLK2    (0x00000000U)
+/* alias */
+#define RCC_USART16CLKSOURCE_PCLK2        RCC_USART16CLKSOURCE_D2PCLK2
+#define RCC_USART16CLKSOURCE_PLL2         RCC_D2CCIP2R_USART16SEL_0
+#define RCC_USART16CLKSOURCE_PLL3         RCC_D2CCIP2R_USART16SEL_1
+#define RCC_USART16CLKSOURCE_HSI         (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_1)
+#define RCC_USART16CLKSOURCE_CSI          RCC_D2CCIP2R_USART16SEL_2
+#define RCC_USART16CLKSOURCE_LSE         (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_2)
+
+#else
+#define RCC_USART16910CLKSOURCE_CDPCLK2   (0x00000000U)
+/* alias */
+#define RCC_USART16910CLKSOURCE_D2PCLK2   RCC_USART16910CLKSOURCE_CDPCLK2
+#define RCC_USART16910CLKSOURCE_PLL2      RCC_CDCCIP2R_USART16910SEL_0
+#define RCC_USART16910CLKSOURCE_PLL3      RCC_CDCCIP2R_USART16910SEL_1
+#define RCC_USART16910CLKSOURCE_HSI      (RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_1)
+#define RCC_USART16910CLKSOURCE_CSI       RCC_CDCCIP2R_USART16910SEL_2
+#define RCC_USART16910CLKSOURCE_LSE      (RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_2)
+
+/*  Aliases */
+#define RCC_USART16CLKSOURCE_CDPCLK2     RCC_USART16910CLKSOURCE_CDPCLK2
+#define RCC_USART16CLKSOURCE_PCLK2       RCC_USART16CLKSOURCE_CDPCLK2
+#define RCC_USART16CLKSOURCE_D2PCLK2     RCC_USART16CLKSOURCE_CDPCLK2
+#define RCC_USART16CLKSOURCE_PLL2        RCC_USART16910CLKSOURCE_PLL2
+#define RCC_USART16CLKSOURCE_PLL3        RCC_USART16910CLKSOURCE_PLL3
+#define RCC_USART16CLKSOURCE_HSI         RCC_USART16910CLKSOURCE_HSI
+#define RCC_USART16CLKSOURCE_CSI         RCC_USART16910CLKSOURCE_CSI
+#define RCC_USART16CLKSOURCE_LSE         RCC_USART16910CLKSOURCE_LSE
+#endif /* RCC_D2CCIP2R_USART16SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_USART1_Clock_Source  RCCEx USART1 Clock Source
+  * @{
+  */
+#define RCC_USART1CLKSOURCE_D2PCLK2   RCC_USART16CLKSOURCE_D2PCLK2
+#define RCC_USART1CLKSOURCE_PLL2      RCC_USART16CLKSOURCE_PLL2
+#define RCC_USART1CLKSOURCE_PLL3      RCC_USART16CLKSOURCE_PLL3
+#define RCC_USART1CLKSOURCE_HSI       RCC_USART16CLKSOURCE_HSI
+#define RCC_USART1CLKSOURCE_CSI       RCC_USART16CLKSOURCE_CSI
+#define RCC_USART1CLKSOURCE_LSE       RCC_USART16CLKSOURCE_LSE
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_USART6_Clock_Source  RCCEx USART6 Clock Source
+  * @{
+  */
+#define RCC_USART6CLKSOURCE_D2PCLK2   RCC_USART16CLKSOURCE_D2PCLK2
+#define RCC_USART6CLKSOURCE_PLL2      RCC_USART16CLKSOURCE_PLL2
+#define RCC_USART6CLKSOURCE_PLL3      RCC_USART16CLKSOURCE_PLL3
+#define RCC_USART6CLKSOURCE_HSI       RCC_USART16CLKSOURCE_HSI
+#define RCC_USART6CLKSOURCE_CSI       RCC_USART16CLKSOURCE_CSI
+#define RCC_USART6CLKSOURCE_LSE       RCC_USART16CLKSOURCE_LSE
+
+/**
+  * @}
+  */
+
+#if defined(UART9)
+/** @defgroup RCCEx_UART9_Clock_Source  RCCEx UART9 Clock Source
+  * @{
+  */
+#define RCC_UART9CLKSOURCE_D2PCLK2   RCC_USART16CLKSOURCE_D2PCLK2
+#define RCC_UART9CLKSOURCE_PLL2      RCC_USART16CLKSOURCE_PLL2
+#define RCC_UART9CLKSOURCE_PLL3      RCC_USART16CLKSOURCE_PLL3
+#define RCC_UART9CLKSOURCE_HSI       RCC_USART16CLKSOURCE_HSI
+#define RCC_UART9CLKSOURCE_CSI       RCC_USART16CLKSOURCE_CSI
+#define RCC_UART9CLKSOURCE_LSE       RCC_USART16CLKSOURCE_LSE
+/**
+  * @}
+  */
+#endif /* UART9 */
+
+#if defined(USART10)
+/** @defgroup RCCEx_USART10_Clock_Source  RCCEx USART10 Clock Source
+  * @{
+  */
+#define RCC_USART10CLKSOURCE_D2PCLK2   RCC_USART16CLKSOURCE_D2PCLK2
+#define RCC_USART10CLKSOURCE_PLL2      RCC_USART16CLKSOURCE_PLL2
+#define RCC_USART10CLKSOURCE_PLL3      RCC_USART16CLKSOURCE_PLL3
+#define RCC_USART10CLKSOURCE_HSI       RCC_USART16CLKSOURCE_HSI
+#define RCC_USART10CLKSOURCE_CSI       RCC_USART16CLKSOURCE_CSI
+#define RCC_USART10CLKSOURCE_LSE       RCC_USART16CLKSOURCE_LSE
+/**
+  * @}
+  */
+#endif /* USART10 */
+
+/** @defgroup RCCEx_USART234578_Clock_Source  RCCEx USART2/3/4/5/7/8 Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP2R_USART28SEL)
+#define RCC_USART234578CLKSOURCE_D2PCLK1    (0x00000000U)
+/* alias */
+#define RCC_USART234578CLKSOURCE_PCLK1      RCC_USART234578CLKSOURCE_D2PCLK1
+#define RCC_USART234578CLKSOURCE_PLL2       RCC_D2CCIP2R_USART28SEL_0
+#define RCC_USART234578CLKSOURCE_PLL3       RCC_D2CCIP2R_USART28SEL_1
+#define RCC_USART234578CLKSOURCE_HSI        (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)
+#define RCC_USART234578CLKSOURCE_CSI        RCC_D2CCIP2R_USART28SEL_2
+#define RCC_USART234578CLKSOURCE_LSE        (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)
+#else
+#define RCC_USART234578CLKSOURCE_CDPCLK1   (0x00000000U)
+/* alias */
+#define RCC_USART234578CLKSOURCE_PCLK1     RCC_USART234578CLKSOURCE_CDPCLK1
+#define RCC_USART234578CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_CDPCLK1
+#define RCC_USART234578CLKSOURCE_PLL2      RCC_CDCCIP2R_USART234578SEL_0
+#define RCC_USART234578CLKSOURCE_PLL3      RCC_CDCCIP2R_USART234578SEL_1
+#define RCC_USART234578CLKSOURCE_HSI      (RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_1)
+#define RCC_USART234578CLKSOURCE_CSI       RCC_CDCCIP2R_USART234578SEL_2
+#define RCC_USART234578CLKSOURCE_LSE      (RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_2)
+#endif /* RCC_D2CCIP2R_USART28SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_USART2_Clock_Source  RCCEx USART2 Clock Source
+  * @{
+  */
+#define RCC_USART2CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1
+#define RCC_USART2CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2
+#define RCC_USART2CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3
+#define RCC_USART2CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI
+#define RCC_USART2CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI
+#define RCC_USART2CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_USART3_Clock_Source  RCCEx USART3 Clock Source
+  * @{
+  */
+#define RCC_USART3CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1
+#define RCC_USART3CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2
+#define RCC_USART3CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3
+#define RCC_USART3CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI
+#define RCC_USART3CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI
+#define RCC_USART3CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_UART4_Clock_Source  RCCEx UART4 Clock Source
+  * @{
+  */
+#define RCC_UART4CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1
+#define RCC_UART4CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2
+#define RCC_UART4CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3
+#define RCC_UART4CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI
+#define RCC_UART4CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI
+#define RCC_UART4CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_UART5_Clock_Source  RCCEx UART5 Clock Source
+  * @{
+  */
+#define RCC_UART5CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1
+#define RCC_UART5CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2
+#define RCC_UART5CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3
+#define RCC_UART5CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI
+#define RCC_UART5CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI
+#define RCC_UART5CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_UART7_Clock_Source  RCCEx UART7 Clock Source
+  * @{
+  */
+#define RCC_UART7CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1
+#define RCC_UART7CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2
+#define RCC_UART7CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3
+#define RCC_UART7CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI
+#define RCC_UART7CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI
+#define RCC_UART7CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_UART8_Clock_Source  RCCEx UART8 Clock Source
+  * @{
+  */
+#define RCC_UART8CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1
+#define RCC_UART8CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2
+#define RCC_UART8CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3
+#define RCC_UART8CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI
+#define RCC_UART8CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI
+#define RCC_UART8CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_LPUART1_Clock_Source  RCCEx LPUART1 Clock Source
+  * @{
+  */
+#if defined(RCC_D3CCIPR_LPUART1SEL)
+#define RCC_LPUART1CLKSOURCE_D3PCLK1    (0x00000000U)
+/* alias */
+#define RCC_LPUART1CLKSOURCE_PCLK4     RCC_LPUART1CLKSOURCE_D3PCLK1
+#define RCC_LPUART1CLKSOURCE_PLL2      RCC_D3CCIPR_LPUART1SEL_0
+#define RCC_LPUART1CLKSOURCE_PLL3      RCC_D3CCIPR_LPUART1SEL_1
+#define RCC_LPUART1CLKSOURCE_HSI       (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_1)
+#define RCC_LPUART1CLKSOURCE_CSI        RCC_D3CCIPR_LPUART1SEL_2
+#define RCC_LPUART1CLKSOURCE_LSE       (RCC_D3CCIPR_LPUART1SEL_2 | RCC_D3CCIPR_LPUART1SEL_0)
+#else
+#define RCC_LPUART1CLKSOURCE_SRDPCLK4   (0x00000000U)
+/* alias*/
+#define RCC_LPUART1CLKSOURCE_PCLK4     RCC_LPUART1CLKSOURCE_SRDPCLK4
+#define RCC_LPUART1CLKSOURCE_D3PCLK1   RCC_LPUART1CLKSOURCE_SRDPCLK4
+#define RCC_LPUART1CLKSOURCE_PLL2      RCC_SRDCCIPR_LPUART1SEL_0
+#define RCC_LPUART1CLKSOURCE_PLL3      RCC_SRDCCIPR_LPUART1SEL_1
+#define RCC_LPUART1CLKSOURCE_HSI       (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_1)
+#define RCC_LPUART1CLKSOURCE_CSI        RCC_SRDCCIPR_LPUART1SEL_2
+#define RCC_LPUART1CLKSOURCE_LSE       (RCC_SRDCCIPR_LPUART1SEL_2 | RCC_SRDCCIPR_LPUART1SEL_0)
+#endif /* RCC_D3CCIPR_LPUART1SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_I2C123_Clock_Source  RCCEx I2C1/2/3 Clock Source
+  * @{
+  */
+#if defined (RCC_D2CCIP2R_I2C123SEL)
+#define RCC_I2C123CLKSOURCE_D2PCLK1      (0x00000000U)
+#define RCC_I2C123CLKSOURCE_PLL3         RCC_D2CCIP2R_I2C123SEL_0
+#define RCC_I2C123CLKSOURCE_HSI          RCC_D2CCIP2R_I2C123SEL_1
+#define RCC_I2C123CLKSOURCE_CSI         (RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1)
+#else
+#define RCC_I2C123CLKSOURCE_CDPCLK1      (0x00000000U)
+/* alias */
+#define RCC_I2C123CLKSOURCE_D2PCLK1      RCC_I2C123CLKSOURCE_CDPCLK1
+#define RCC_I2C123CLKSOURCE_PLL3         RCC_CDCCIP2R_I2C123SEL_0
+#define RCC_I2C123CLKSOURCE_HSI          RCC_CDCCIP2R_I2C123SEL_1
+#define RCC_I2C123CLKSOURCE_CSI         (RCC_CDCCIP2R_I2C123SEL_0 | RCC_CDCCIP2R_I2C123SEL_1)
+#endif /* RCC_D2CCIP2R_I2C123SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_I2C1_Clock_Source  RCCEx I2C1 Clock Source
+  * @{
+  */
+#define RCC_I2C1CLKSOURCE_D2PCLK1     RCC_I2C123CLKSOURCE_D2PCLK1
+#define RCC_I2C1CLKSOURCE_PLL3        RCC_I2C123CLKSOURCE_PLL3
+#define RCC_I2C1CLKSOURCE_HSI         RCC_I2C123CLKSOURCE_HSI
+#define RCC_I2C1CLKSOURCE_CSI         RCC_I2C123CLKSOURCE_CSI
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_I2C2_Clock_Source  RCCEx I2C2 Clock Source
+  * @{
+  */
+#define RCC_I2C2CLKSOURCE_D2PCLK1     RCC_I2C123CLKSOURCE_D2PCLK1
+#define RCC_I2C2CLKSOURCE_PLL3        RCC_I2C123CLKSOURCE_PLL3
+#define RCC_I2C2CLKSOURCE_HSI         RCC_I2C123CLKSOURCE_HSI
+#define RCC_I2C2CLKSOURCE_CSI         RCC_I2C123CLKSOURCE_CSI
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_I2C3_Clock_Source  RCCEx I2C3 Clock Source
+  * @{
+  */
+#define RCC_I2C3CLKSOURCE_D2PCLK1     RCC_I2C123CLKSOURCE_D2PCLK1
+#define RCC_I2C3CLKSOURCE_PLL3        RCC_I2C123CLKSOURCE_PLL3
+#define RCC_I2C3CLKSOURCE_HSI         RCC_I2C123CLKSOURCE_HSI
+#define RCC_I2C3CLKSOURCE_CSI         RCC_I2C123CLKSOURCE_CSI
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_I2C4_Clock_Source  RCCEx I2C4 Clock Source
+  * @{
+  */
+#if defined(RCC_D3CCIPR_I2C4SEL)
+#define RCC_I2C4CLKSOURCE_D3PCLK1      (0x00000000U)
+#define RCC_I2C4CLKSOURCE_PLL3         RCC_D3CCIPR_I2C4SEL_0
+#define RCC_I2C4CLKSOURCE_HSI          RCC_D3CCIPR_I2C4SEL_1
+#define RCC_I2C4CLKSOURCE_CSI         (RCC_D3CCIPR_I2C4SEL_0 | RCC_D3CCIPR_I2C4SEL_1)
+#else
+#define RCC_I2C4CLKSOURCE_SRDPCLK4     (0x00000000U)
+/* alias */
+#define RCC_I2C4CLKSOURCE_D3PCLK1     RCC_I2C4CLKSOURCE_SRDPCLK4
+#define RCC_I2C4CLKSOURCE_PLL3         RCC_SRDCCIPR_I2C4SEL_0
+#define RCC_I2C4CLKSOURCE_HSI          RCC_SRDCCIPR_I2C4SEL_1
+#define RCC_I2C4CLKSOURCE_CSI         (RCC_SRDCCIPR_I2C4SEL_0 | RCC_SRDCCIPR_I2C4SEL_1)
+#endif /* RCC_D3CCIPR_I2C4SEL */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_RNG_Clock_Source  RCCEx RNG Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP2R_RNGSEL)
+#define RCC_RNGCLKSOURCE_HSI48        (0x00000000U)
+#define RCC_RNGCLKSOURCE_PLL           RCC_D2CCIP2R_RNGSEL_0
+#define RCC_RNGCLKSOURCE_LSE           RCC_D2CCIP2R_RNGSEL_1
+#define RCC_RNGCLKSOURCE_LSI           RCC_D2CCIP2R_RNGSEL
+#else
+#define RCC_RNGCLKSOURCE_HSI48        (0x00000000U)
+#define RCC_RNGCLKSOURCE_PLL           RCC_CDCCIP2R_RNGSEL_0
+#define RCC_RNGCLKSOURCE_LSE           RCC_CDCCIP2R_RNGSEL_1
+#define RCC_RNGCLKSOURCE_LSI           RCC_CDCCIP2R_RNGSEL
+#endif /* RCC_D2CCIP2R_RNGSEL */
+
+/**
+  * @}
+  */
+#if defined(HRTIM1)
+
+/** @defgroup RCCEx_HRTIM1_Clock_Source RCC Extended HRTIM1 Clock Source
+  * @{
+  */
+#define RCC_HRTIM1CLK_TIMCLK                (0x00000000U)
+#define RCC_HRTIM1CLK_CPUCLK                RCC_CFGR_HRTIMSEL
+
+/**
+  * @}
+  */
+#endif /*HRTIM1*/
+
+/** @defgroup RCCEx_USB_Clock_Source  RCCEx USB Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP2R_USBSEL)
+#define RCC_USBCLKSOURCE_PLL                  RCC_D2CCIP2R_USBSEL_0
+#define RCC_USBCLKSOURCE_PLL3                 RCC_D2CCIP2R_USBSEL_1
+#define RCC_USBCLKSOURCE_HSI48                RCC_D2CCIP2R_USBSEL
+#else
+#define RCC_USBCLKSOURCE_PLL                  RCC_CDCCIP2R_USBSEL_0
+#define RCC_USBCLKSOURCE_PLL3                 RCC_CDCCIP2R_USBSEL_1
+#define RCC_USBCLKSOURCE_HSI48                RCC_CDCCIP2R_USBSEL
+#endif /* RCC_D2CCIP2R_USBSEL */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_SAI1SEL)
+#define RCC_SAI1CLKSOURCE_PLL         (0x00000000U)
+#define RCC_SAI1CLKSOURCE_PLL2         RCC_D2CCIP1R_SAI1SEL_0
+#define RCC_SAI1CLKSOURCE_PLL3         RCC_D2CCIP1R_SAI1SEL_1
+#define RCC_SAI1CLKSOURCE_PIN         (RCC_D2CCIP1R_SAI1SEL_0 | RCC_D2CCIP1R_SAI1SEL_1)
+#define RCC_SAI1CLKSOURCE_CLKP         RCC_D2CCIP1R_SAI1SEL_2
+#else
+#define RCC_SAI1CLKSOURCE_PLL         (0x00000000U)
+#define RCC_SAI1CLKSOURCE_PLL2         RCC_CDCCIP1R_SAI1SEL_0
+#define RCC_SAI1CLKSOURCE_PLL3         RCC_CDCCIP1R_SAI1SEL_1
+#define RCC_SAI1CLKSOURCE_PIN         (RCC_CDCCIP1R_SAI1SEL_0 | RCC_CDCCIP1R_SAI1SEL_1)
+#define RCC_SAI1CLKSOURCE_CLKP         RCC_CDCCIP1R_SAI1SEL_2
+#endif /* RCC_D2CCIP1R_SAI1SEL */
+/**
+  * @}
+  */
+
+#if defined(SAI3)
+/** @defgroup RCCEx_SAI23_Clock_Source SAI2/3 Clock Source
+  * @{
+  */
+#define RCC_SAI23CLKSOURCE_PLL         (0x00000000U)
+#define RCC_SAI23CLKSOURCE_PLL2         RCC_D2CCIP1R_SAI23SEL_0
+#define RCC_SAI23CLKSOURCE_PLL3         RCC_D2CCIP1R_SAI23SEL_1
+#define RCC_SAI23CLKSOURCE_PIN         (RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1)
+#define RCC_SAI23CLKSOURCE_CLKP         RCC_D2CCIP1R_SAI23SEL_2
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source
+  * @{
+  */
+#define RCC_SAI2CLKSOURCE_PLL         RCC_SAI23CLKSOURCE_PLL
+#define RCC_SAI2CLKSOURCE_PLL2        RCC_SAI23CLKSOURCE_PLL2
+#define RCC_SAI2CLKSOURCE_PLL3        RCC_SAI23CLKSOURCE_PLL3
+#define RCC_SAI2CLKSOURCE_PIN         RCC_SAI23CLKSOURCE_PIN
+#define RCC_SAI2CLKSOURCE_CLKP        RCC_SAI23CLKSOURCE_CLKP
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SAI3_Clock_Source SAI3 Clock Source
+  * @{
+  */
+#define RCC_SAI3CLKSOURCE_PLL         RCC_SAI23CLKSOURCE_PLL
+#define RCC_SAI3CLKSOURCE_PLL2        RCC_SAI23CLKSOURCE_PLL2
+#define RCC_SAI3CLKSOURCE_PLL3        RCC_SAI23CLKSOURCE_PLL3
+#define RCC_SAI3CLKSOURCE_PIN         RCC_SAI23CLKSOURCE_PIN
+#define RCC_SAI3CLKSOURCE_CLKP        RCC_SAI23CLKSOURCE_CLKP
+/**
+  * @}
+  */
+#endif /* SAI3 */
+
+#if defined(RCC_CDCCIP1R_SAI2ASEL)
+/** @defgroup RCCEx_SAI2_Clock_A Source SAI2A Clock Source
+  * @{
+  */
+#define RCC_SAI2ACLKSOURCE_PLL         (0x00000000U)
+#define RCC_SAI2ACLKSOURCE_PLL2         RCC_CDCCIP1R_SAI2ASEL_0
+#define RCC_SAI2ACLKSOURCE_PLL3         RCC_CDCCIP1R_SAI2ASEL_1
+#define RCC_SAI2ACLKSOURCE_PIN         (RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_1)
+#define RCC_SAI2ACLKSOURCE_CLKP         RCC_CDCCIP1R_SAI2ASEL_2
+#define RCC_SAI2ACLKSOURCE_SPDIF       (RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_2)
+ /**
+  * @}
+  */
+#endif /* RCC_CDCCIP1R_SAI2ASEL */
+
+#if defined(RCC_CDCCIP1R_SAI2BSEL)
+/** @defgroup RCCEx_SAI2_Block_B Clock_Source SAI2B Clock Source
+  * @{
+  */
+#define RCC_SAI2BCLKSOURCE_PLL         (0x00000000U)
+#define RCC_SAI2BCLKSOURCE_PLL2         RCC_CDCCIP1R_SAI2BSEL_0
+#define RCC_SAI2BCLKSOURCE_PLL3         RCC_CDCCIP1R_SAI2BSEL_1
+#define RCC_SAI2BCLKSOURCE_PIN         (RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_1)
+#define RCC_SAI2BCLKSOURCE_CLKP         RCC_CDCCIP1R_SAI2BSEL_2
+#define RCC_SAI2BCLKSOURCE_SPDIF       (RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_2)
+/**
+  * @}
+  */
+#endif /* RCC_CDCCIP1R_SAI2BSEL */
+
+
+/** @defgroup RCCEx_SPI123_Clock_Source SPI1/2/3 Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_SPI123SEL)
+#define RCC_SPI123CLKSOURCE_PLL         (0x00000000U)
+#define RCC_SPI123CLKSOURCE_PLL2         RCC_D2CCIP1R_SPI123SEL_0
+#define RCC_SPI123CLKSOURCE_PLL3         RCC_D2CCIP1R_SPI123SEL_1
+#define RCC_SPI123CLKSOURCE_PIN         (RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1)
+#define RCC_SPI123CLKSOURCE_CLKP         RCC_D2CCIP1R_SPI123SEL_2
+#else
+#define RCC_SPI123CLKSOURCE_PLL         (0x00000000U)
+#define RCC_SPI123CLKSOURCE_PLL2         RCC_CDCCIP1R_SPI123SEL_0
+#define RCC_SPI123CLKSOURCE_PLL3         RCC_CDCCIP1R_SPI123SEL_1
+#define RCC_SPI123CLKSOURCE_PIN         (RCC_CDCCIP1R_SPI123SEL_0 | RCC_CDCCIP1R_SPI123SEL_1)
+#define RCC_SPI123CLKSOURCE_CLKP         RCC_CDCCIP1R_SPI123SEL_2
+#endif /* RCC_D2CCIP1R_SPI123SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SPI1_Clock_Source SPI1 Clock Source
+  * @{
+  */
+#define RCC_SPI1CLKSOURCE_PLL         RCC_SPI123CLKSOURCE_PLL
+#define RCC_SPI1CLKSOURCE_PLL2        RCC_SPI123CLKSOURCE_PLL2
+#define RCC_SPI1CLKSOURCE_PLL3        RCC_SPI123CLKSOURCE_PLL3
+#define RCC_SPI1CLKSOURCE_PIN         RCC_SPI123CLKSOURCE_PIN
+#define RCC_SPI1CLKSOURCE_CLKP        RCC_SPI123CLKSOURCE_CLKP
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SPI2_Clock_Source SPI2 Clock Source
+  * @{
+  */
+#define RCC_SPI2CLKSOURCE_PLL         RCC_SPI123CLKSOURCE_PLL
+#define RCC_SPI2CLKSOURCE_PLL2        RCC_SPI123CLKSOURCE_PLL2
+#define RCC_SPI2CLKSOURCE_PLL3        RCC_SPI123CLKSOURCE_PLL3
+#define RCC_SPI2CLKSOURCE_PIN         RCC_SPI123CLKSOURCE_PIN
+#define RCC_SPI2CLKSOURCE_CLKP        RCC_SPI123CLKSOURCE_CLKP
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SPI3_Clock_Source SPI3 Clock Source
+  * @{
+  */
+#define RCC_SPI3CLKSOURCE_PLL         RCC_SPI123CLKSOURCE_PLL
+#define RCC_SPI3CLKSOURCE_PLL2        RCC_SPI123CLKSOURCE_PLL2
+#define RCC_SPI3CLKSOURCE_PLL3        RCC_SPI123CLKSOURCE_PLL3
+#define RCC_SPI3CLKSOURCE_PIN         RCC_SPI123CLKSOURCE_PIN
+#define RCC_SPI3CLKSOURCE_CLKP        RCC_SPI123CLKSOURCE_CLKP
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SPI45_Clock_Source SPI4/5 Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_SPI45SEL)
+#define RCC_SPI45CLKSOURCE_D2PCLK1     (0x00000000U)
+#define RCC_SPI45CLKSOURCE_PCLK1        RCC_SPI45CLKSOURCE_D2PCLK1
+#define RCC_SPI45CLKSOURCE_PLL2         RCC_D2CCIP1R_SPI45SEL_0
+#define RCC_SPI45CLKSOURCE_PLL3         RCC_D2CCIP1R_SPI45SEL_1
+#define RCC_SPI45CLKSOURCE_HSI         (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_1)
+#define RCC_SPI45CLKSOURCE_CSI          RCC_D2CCIP1R_SPI45SEL_2
+#define RCC_SPI45CLKSOURCE_HSE         (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_2)
+#else
+#define RCC_SPI45CLKSOURCE_CDPCLK1     (0x00000000U)
+/* aliases */
+#define RCC_SPI45CLKSOURCE_D2PCLK1      RCC_SPI45CLKSOURCE_CDPCLK1  /* D2PCLK1 is used in STM32H74xxx, STM32H75xxx, STM32H72xxx and STM32H73xxx family lines */
+#define RCC_SPI45CLKSOURCE_PCLK1        RCC_SPI45CLKSOURCE_CDPCLK1
+#define RCC_SPI45CLKSOURCE_PLL2         RCC_CDCCIP1R_SPI45SEL_0
+#define RCC_SPI45CLKSOURCE_PLL3         RCC_CDCCIP1R_SPI45SEL_1
+#define RCC_SPI45CLKSOURCE_HSI         (RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_1)
+#define RCC_SPI45CLKSOURCE_CSI          RCC_CDCCIP1R_SPI45SEL_2
+#define RCC_SPI45CLKSOURCE_HSE         (RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_2)
+#endif /* RCC_D2CCIP1R_SPI45SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SPI4_Clock_Source SPI4 Clock Source
+  * @{
+  */
+#define RCC_SPI4CLKSOURCE_D2PCLK1     RCC_SPI45CLKSOURCE_D2PCLK1
+#define RCC_SPI4CLKSOURCE_PLL2        RCC_SPI45CLKSOURCE_PLL2
+#define RCC_SPI4CLKSOURCE_PLL3        RCC_SPI45CLKSOURCE_PLL3
+#define RCC_SPI4CLKSOURCE_HSI         RCC_SPI45CLKSOURCE_HSI
+#define RCC_SPI4CLKSOURCE_CSI         RCC_SPI45CLKSOURCE_CSI
+#define RCC_SPI4CLKSOURCE_HSE         RCC_SPI45CLKSOURCE_HSE
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SPI5_Clock_Source SPI5 Clock Source
+  * @{
+  */
+#define RCC_SPI5CLKSOURCE_D2PCLK1     RCC_SPI45CLKSOURCE_D2PCLK1
+#define RCC_SPI5CLKSOURCE_PLL2        RCC_SPI45CLKSOURCE_PLL2
+#define RCC_SPI5CLKSOURCE_PLL3        RCC_SPI45CLKSOURCE_PLL3
+#define RCC_SPI5CLKSOURCE_HSI         RCC_SPI45CLKSOURCE_HSI
+#define RCC_SPI5CLKSOURCE_CSI         RCC_SPI45CLKSOURCE_CSI
+#define RCC_SPI5CLKSOURCE_HSE         RCC_SPI45CLKSOURCE_HSE
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SPI6_Clock_Source SPI6 Clock Source
+  * @{
+  */
+#if defined(RCC_D3CCIPR_SPI6SEL)
+#define RCC_SPI6CLKSOURCE_D3PCLK1     (0x00000000U)
+#define RCC_SPI6CLKSOURCE_PCLK4        RCC_SPI6CLKSOURCE_D3PCLK1
+#define RCC_SPI6CLKSOURCE_PLL2         RCC_D3CCIPR_SPI6SEL_0
+#define RCC_SPI6CLKSOURCE_PLL3         RCC_D3CCIPR_SPI6SEL_1
+#define RCC_SPI6CLKSOURCE_HSI         (RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_1)
+#define RCC_SPI6CLKSOURCE_CSI          RCC_D3CCIPR_SPI6SEL_2
+#define RCC_SPI6CLKSOURCE_HSE         (RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_2)
+#else
+#define RCC_SPI6CLKSOURCE_SRDPCLK4    (0x00000000U)
+/* alias */
+#define RCC_SPI6CLKSOURCE_D3PCLK1      RCC_SPI6CLKSOURCE_SRDPCLK4  /* D3PCLK1 is used in STM32H74xxx, STM32H75xxx, STM32H72xxx and STM32H73xxx family lines */
+#define RCC_SPI6CLKSOURCE_PCLK4        RCC_SPI6CLKSOURCE_SRDPCLK4
+#define RCC_SPI6CLKSOURCE_PLL2         RCC_SRDCCIPR_SPI6SEL_0
+#define RCC_SPI6CLKSOURCE_PLL3         RCC_SRDCCIPR_SPI6SEL_1
+#define RCC_SPI6CLKSOURCE_HSI         (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_1)
+#define RCC_SPI6CLKSOURCE_CSI          RCC_SRDCCIPR_SPI6SEL_2
+#define RCC_SPI6CLKSOURCE_HSE         (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_2)
+#define RCC_SPI6CLKSOURCE_PIN         (RCC_SRDCCIPR_SPI6SEL_1 | RCC_SRDCCIPR_SPI6SEL_2)
+#endif /* RCC_D3CCIPR_SPI6SEL */
+
+/**
+  * @}
+  */
+
+
+#if defined(SAI4_Block_A)
+/** @defgroup RCCEx_SAI4A_Clock_Source SAI4A Clock Source
+  * @{
+  */
+#define RCC_SAI4ACLKSOURCE_PLL         (0x00000000U)
+#define RCC_SAI4ACLKSOURCE_PLL2         RCC_D3CCIPR_SAI4ASEL_0
+#define RCC_SAI4ACLKSOURCE_PLL3         RCC_D3CCIPR_SAI4ASEL_1
+#define RCC_SAI4ACLKSOURCE_PIN         (RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1)
+#define RCC_SAI4ACLKSOURCE_CLKP         RCC_D3CCIPR_SAI4ASEL_2
+
+/**
+  * @}
+  */
+#endif /* SAI4_Block_A */
+
+
+
+#if defined(SAI4_Block_B)
+/** @defgroup RCCEx_SAI4B_Clock_Source SAI4B Clock Source
+  * @{
+  */
+#define RCC_SAI4BCLKSOURCE_PLL         (0x00000000U)
+#define RCC_SAI4BCLKSOURCE_PLL2         RCC_D3CCIPR_SAI4BSEL_0
+#define RCC_SAI4BCLKSOURCE_PLL3         RCC_D3CCIPR_SAI4BSEL_1
+#define RCC_SAI4BCLKSOURCE_PIN         (RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1)
+#define RCC_SAI4BCLKSOURCE_CLKP         RCC_D3CCIPR_SAI4BSEL_2
+
+/**
+  * @}
+  */
+#endif /* SAI4_Block_B */
+
+
+/** @defgroup RCCEx_LPTIM1_Clock_Source  RCCEx LPTIM1 Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP2R_LPTIM1SEL)
+#define RCC_LPTIM1CLKSOURCE_D2PCLK1        (0x00000000U)
+/* alias */
+#define RCC_LPTIM1CLKSOURCE_PCLK1         RCC_LPTIM1CLKSOURCE_D2PCLK1
+#define RCC_LPTIM1CLKSOURCE_PLL2          RCC_D2CCIP2R_LPTIM1SEL_0
+#define RCC_LPTIM1CLKSOURCE_PLL3          RCC_D2CCIP2R_LPTIM1SEL_1
+#define RCC_LPTIM1CLKSOURCE_LSE          (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_1)
+#define RCC_LPTIM1CLKSOURCE_LSI           RCC_D2CCIP2R_LPTIM1SEL_2
+#define RCC_LPTIM1CLKSOURCE_CLKP         (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_2)
+#else
+#define RCC_LPTIM1CLKSOURCE_CDPCLK1        (0x00000000U)
+/* alias */
+#define RCC_LPTIM1CLKSOURCE_PCLK1         RCC_LPTIM1CLKSOURCE_CDPCLK1
+#define RCC_LPTIM1CLKSOURCE_D2PCLK1       RCC_LPTIM1CLKSOURCE_CDPCLK1
+#define RCC_LPTIM1CLKSOURCE_PLL2          RCC_CDCCIP2R_LPTIM1SEL_0
+#define RCC_LPTIM1CLKSOURCE_PLL3          RCC_CDCCIP2R_LPTIM1SEL_1
+#define RCC_LPTIM1CLKSOURCE_LSE          (RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_1)
+#define RCC_LPTIM1CLKSOURCE_LSI           RCC_CDCCIP2R_LPTIM1SEL_2
+#define RCC_LPTIM1CLKSOURCE_CLKP         (RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_2)
+#endif /* RCC_D2CCIP2R_LPTIM1SEL */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_LPTIM2_Clock_Source  RCCEx LPTIM2 Clock Source
+  * @{
+  */
+#if defined(RCC_D3CCIPR_LPTIM2SEL)
+#define RCC_LPTIM2CLKSOURCE_D3PCLK1       (0x00000000U)
+/* alias */
+#define RCC_LPTIM2CLKSOURCE_PCLK4         RCC_LPTIM2CLKSOURCE_D3PCLK1
+#define RCC_LPTIM2CLKSOURCE_PLL2          RCC_D3CCIPR_LPTIM2SEL_0
+#define RCC_LPTIM2CLKSOURCE_PLL3          RCC_D3CCIPR_LPTIM2SEL_1
+#define RCC_LPTIM2CLKSOURCE_LSE          (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_1)
+#define RCC_LPTIM2CLKSOURCE_LSI           RCC_D3CCIPR_LPTIM2SEL_2
+#define RCC_LPTIM2CLKSOURCE_CLKP         (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_2)
+#else
+#define RCC_LPTIM2CLKSOURCE_SRDPCLK4       (0x00000000U)
+/*alias*/
+#define RCC_LPTIM2CLKSOURCE_PCLK4         RCC_LPTIM2CLKSOURCE_SRDPCLK4
+#define RCC_LPTIM2CLKSOURCE_D3PCLK1       RCC_LPTIM2CLKSOURCE_SRDPCLK4
+#define RCC_LPTIM2CLKSOURCE_PLL2          RCC_SRDCCIPR_LPTIM2SEL_0
+#define RCC_LPTIM2CLKSOURCE_PLL3          RCC_SRDCCIPR_LPTIM2SEL_1
+#define RCC_LPTIM2CLKSOURCE_LSE          (RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_1)
+#define RCC_LPTIM2CLKSOURCE_LSI           RCC_SRDCCIPR_LPTIM2SEL_2
+#define RCC_LPTIM2CLKSOURCE_CLKP         (RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_2)
+#endif /* RCC_D3CCIPR_LPTIM2SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_LPTIM345_Clock_Source  RCCEx LPTIM3/4/5 Clock Source
+  * @{
+  */
+#if defined(RCC_D3CCIPR_LPTIM345SEL)
+#define RCC_LPTIM345CLKSOURCE_D3PCLK1        (0x00000000U)
+/* alias*/
+#define RCC_LPTIM345CLKSOURCE_PCLK4         RCC_LPTIM345CLKSOURCE_D3PCLK1
+#define RCC_LPTIM345CLKSOURCE_PLL2          RCC_D3CCIPR_LPTIM345SEL_0
+#define RCC_LPTIM345CLKSOURCE_PLL3          RCC_D3CCIPR_LPTIM345SEL_1
+#define RCC_LPTIM345CLKSOURCE_LSE          (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1)
+#define RCC_LPTIM345CLKSOURCE_LSI           RCC_D3CCIPR_LPTIM345SEL_2
+#define RCC_LPTIM345CLKSOURCE_CLKP         (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2)
+#else
+#define RCC_LPTIM345CLKSOURCE_SRDPCLK4      (0x00000000U)
+/* alias */
+#define RCC_LPTIM345CLKSOURCE_PCLK4         RCC_LPTIM345CLKSOURCE_SRDPCLK4
+#define RCC_LPTIM345CLKSOURCE_D3PCLK1       RCC_LPTIM345CLKSOURCE_SRDPCLK4
+#define RCC_LPTIM345CLKSOURCE_PLL2          RCC_SRDCCIPR_LPTIM3SEL_0
+#define RCC_LPTIM345CLKSOURCE_PLL3          RCC_SRDCCIPR_LPTIM3SEL_1
+#define RCC_LPTIM345CLKSOURCE_LSE          (RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_1)
+#define RCC_LPTIM345CLKSOURCE_LSI           RCC_SRDCCIPR_LPTIM3SEL_2
+#define RCC_LPTIM345CLKSOURCE_CLKP         (RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_2)
+#endif /* RCC_D3CCIPR_LPTIM345SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_LPTIM3_Clock_Source  RCCEx LPTIM3 Clock Source
+  * @{
+  */
+#define RCC_LPTIM3CLKSOURCE_D3PCLK1       RCC_LPTIM345CLKSOURCE_D3PCLK1
+#define RCC_LPTIM3CLKSOURCE_PLL2          RCC_LPTIM345CLKSOURCE_PLL2
+#define RCC_LPTIM3CLKSOURCE_PLL3          RCC_LPTIM345CLKSOURCE_PLL3
+#define RCC_LPTIM3CLKSOURCE_LSE           RCC_LPTIM345CLKSOURCE_LSE
+#define RCC_LPTIM3CLKSOURCE_LSI           RCC_LPTIM345CLKSOURCE_LSI
+#define RCC_LPTIM3CLKSOURCE_CLKP          RCC_LPTIM345CLKSOURCE_CLKP
+
+/**
+  * @}
+  */
+#if defined(LPTIM4)
+/** @defgroup RCCEx_LPTIM4_Clock_Source  RCCEx LPTIM4 Clock Source
+  * @{
+  */
+#define RCC_LPTIM4CLKSOURCE_D3PCLK1       RCC_LPTIM345CLKSOURCE_D3PCLK1
+#define RCC_LPTIM4CLKSOURCE_PLL2          RCC_LPTIM345CLKSOURCE_PLL2
+#define RCC_LPTIM4CLKSOURCE_PLL3          RCC_LPTIM345CLKSOURCE_PLL3
+#define RCC_LPTIM4CLKSOURCE_LSE           RCC_LPTIM345CLKSOURCE_LSE
+#define RCC_LPTIM4CLKSOURCE_LSI           RCC_LPTIM345CLKSOURCE_LSI
+#define RCC_LPTIM4CLKSOURCE_CLKP          RCC_LPTIM345CLKSOURCE_CLKP
+/**
+  * @}
+  */
+#endif /* LPTIM4 */
+
+#if defined(LPTIM5)
+/** @defgroup RCCEx_LPTIM5_Clock_Source  RCCEx LPTIM5 Clock Source
+  * @{
+  */
+#define RCC_LPTIM5CLKSOURCE_D3PCLK1       RCC_LPTIM345CLKSOURCE_D3PCLK1
+#define RCC_LPTIM5CLKSOURCE_PLL2          RCC_LPTIM345CLKSOURCE_PLL2
+#define RCC_LPTIM5CLKSOURCE_PLL3          RCC_LPTIM345CLKSOURCE_PLL3
+#define RCC_LPTIM5CLKSOURCE_LSE           RCC_LPTIM345CLKSOURCE_LSE
+#define RCC_LPTIM5CLKSOURCE_LSI           RCC_LPTIM345CLKSOURCE_LSI
+#define RCC_LPTIM5CLKSOURCE_CLKP          RCC_LPTIM345CLKSOURCE_CLKP
+
+/**
+  * @}
+  */
+#endif /* LPTIM5 */
+
+#if defined(QUADSPI)
+/** @defgroup RCCEx_QSPI_Clock_Source  RCCEx QSPI Clock Source
+  * @{
+  */
+#define RCC_QSPICLKSOURCE_D1HCLK       (0x00000000U)
+#define RCC_QSPICLKSOURCE_PLL          RCC_D1CCIPR_QSPISEL_0
+#define RCC_QSPICLKSOURCE_PLL2         RCC_D1CCIPR_QSPISEL_1
+#define RCC_QSPICLKSOURCE_CLKP         RCC_D1CCIPR_QSPISEL
+
+/**
+  * @}
+  */
+#endif /* QUADSPI */
+
+
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+/** @defgroup RCCEx_OSPI_Clock_Source  RCCEx OSPI Clock Source
+  * @{
+  */
+#define RCC_OSPICLKSOURCE_CDHCLK       (0x00000000U)
+/*aliases*/
+#define RCC_OSPICLKSOURCE_D1HCLK       RCC_OSPICLKSOURCE_CDHCLK
+#define RCC_OSPICLKSOURCE_HCLK         RCC_OSPICLKSOURCE_CDHCLK
+#define RCC_OSPICLKSOURCE_PLL          RCC_CDCCIPR_OCTOSPISEL_0
+#define RCC_OSPICLKSOURCE_PLL2         RCC_CDCCIPR_OCTOSPISEL_1
+#define RCC_OSPICLKSOURCE_CLKP         RCC_CDCCIPR_OCTOSPISEL
+
+/**
+  * @}
+  */
+#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
+
+#if defined(DSI)
+/** @defgroup RCCEx_DSI_Clock_Source  RCCEx DSI Clock Source
+  * @{
+  */
+#define RCC_DSICLKSOURCE_PHY       (0x00000000U)
+#define RCC_DSICLKSOURCE_PLL2       RCC_D1CCIPR_DSISEL
+
+/**
+  * @}
+  */
+#endif /* DSI */
+
+/** @defgroup RCCEx_FMC_Clock_Source  RCCEx FMC Clock Source
+  * @{
+  */
+#if defined(RCC_D1CCIPR_FMCSEL)
+#define RCC_FMCCLKSOURCE_D1HCLK       (0x00000000U)
+#define RCC_FMCCLKSOURCE_HCLK         RCC_FMCCLKSOURCE_D1HCLK
+#define RCC_FMCCLKSOURCE_PLL          RCC_D1CCIPR_FMCSEL_0
+#define RCC_FMCCLKSOURCE_PLL2         RCC_D1CCIPR_FMCSEL_1
+#define RCC_FMCCLKSOURCE_CLKP         RCC_D1CCIPR_FMCSEL
+#else
+#define RCC_FMCCLKSOURCE_CDHCLK       (0x00000000U)
+#define RCC_FMCCLKSOURCE_HCLK         RCC_FMCCLKSOURCE_CDHCLK
+/*alias*/
+#define RCC_FMCCLKSOURCE_D1HCLK       RCC_FMCCLKSOURCE_CDHCLK
+#define RCC_FMCCLKSOURCE_PLL          RCC_CDCCIPR_FMCSEL_0
+#define RCC_FMCCLKSOURCE_PLL2         RCC_CDCCIPR_FMCSEL_1
+#define RCC_FMCCLKSOURCE_CLKP         RCC_CDCCIPR_FMCSEL
+#endif /* RCC_D1CCIPR_FMCSEL */
+/**
+  * @}
+  */
+
+#if defined(FDCAN1) || defined(FDCAN2)
+/** @defgroup RCCEx_FDCAN_Clock_Source  RCCEx FDCAN Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_FDCANSEL)
+#define RCC_FDCANCLKSOURCE_HSE         (0x00000000U)
+#define RCC_FDCANCLKSOURCE_PLL          RCC_D2CCIP1R_FDCANSEL_0
+#define RCC_FDCANCLKSOURCE_PLL2         RCC_D2CCIP1R_FDCANSEL_1
+#else
+#define RCC_FDCANCLKSOURCE_HSE         (0x00000000U)
+#define RCC_FDCANCLKSOURCE_PLL          RCC_CDCCIP1R_FDCANSEL_0
+#define RCC_FDCANCLKSOURCE_PLL2         RCC_CDCCIP1R_FDCANSEL_1
+#endif /* D3_SRAM_BASE */
+/**
+  * @}
+  */
+#endif /*FDCAN1 || FDCAN2*/
+
+
+/** @defgroup RCCEx_SDMMC_Clock_Source  RCCEx SDMMC Clock Source
+  * @{
+  */
+#if defined(RCC_D1CCIPR_SDMMCSEL)
+#define RCC_SDMMCCLKSOURCE_PLL           (0x00000000U)
+#define RCC_SDMMCCLKSOURCE_PLL2           RCC_D1CCIPR_SDMMCSEL
+#else
+#define RCC_SDMMCCLKSOURCE_PLL           (0x00000000U)
+#define RCC_SDMMCCLKSOURCE_PLL2           RCC_CDCCIPR_SDMMCSEL
+#endif /* RCC_D1CCIPR_SDMMCSEL */
+/**
+  * @}
+  */
+
+
+/** @defgroup RCCEx_ADC_Clock_Source  RCCEx ADC Clock Source
+  * @{
+  */
+#if defined(RCC_D3CCIPR_ADCSEL_0)
+#define RCC_ADCCLKSOURCE_PLL2       (0x00000000U)
+#define RCC_ADCCLKSOURCE_PLL3       RCC_D3CCIPR_ADCSEL_0
+#define RCC_ADCCLKSOURCE_CLKP       RCC_D3CCIPR_ADCSEL_1
+#else
+#define RCC_ADCCLKSOURCE_PLL2       (0x00000000U)
+#define RCC_ADCCLKSOURCE_PLL3       RCC_SRDCCIPR_ADCSEL_0
+#define RCC_ADCCLKSOURCE_CLKP       RCC_SRDCCIPR_ADCSEL_1
+#endif /* RCC_D3CCIPR_ADCSEL_0  */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SWPMI1_Clock_Source  RCCEx SWPMI1 Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_SWPSEL)
+#define RCC_SWPMI1CLKSOURCE_D2PCLK1       (0x00000000U)
+#define RCC_SWPMI1CLKSOURCE_HSI            RCC_D2CCIP1R_SWPSEL
+#else
+#define RCC_SWPMI1CLKSOURCE_CDPCLK1       (0x00000000U)
+/* alias */
+#define RCC_SWPMI1CLKSOURCE_D2PCLK1        RCC_SWPMI1CLKSOURCE_CDPCLK1
+#define RCC_SWPMI1CLKSOURCE_HSI            RCC_CDCCIP1R_SWPSEL
+#endif /* RCC_D2CCIP1R_SWPSEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_DFSDM1_Clock_Source  RCCEx DFSDM1 Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_DFSDM1SEL)
+#define RCC_DFSDM1CLKSOURCE_D2PCLK1        (0x00000000U)
+#define RCC_DFSDM1CLKSOURCE_SYS            RCC_D2CCIP1R_DFSDM1SEL
+#else
+#define RCC_DFSDM1CLKSOURCE_CDPCLK1        (0x00000000U)
+/* alias */
+#define RCC_DFSDM1CLKSOURCE_D2PCLK1        RCC_DFSDM1CLKSOURCE_CDPCLK1
+#define RCC_DFSDM1CLKSOURCE_SYS            RCC_CDCCIP1R_DFSDM1SEL
+#endif /* RCC_D2CCIP1R_DFSDM1SEL */
+/**
+  * @}
+  */
+
+#if defined(DFSDM2_BASE)
+/** @defgroup RCCEx_DFSDM2_Clock_Source  RCCEx DFSDM2 Clock Source
+  * @{
+  */
+#define RCC_DFSDM2CLKSOURCE_SRDPCLK4       (0x00000000U)
+/* alias */
+#define RCC_DFSDM2CLKSOURCE_SRDPCLK1       RCC_DFSDM2CLKSOURCE_SRDPCLK4
+#define RCC_DFSDM2CLKSOURCE_SYS            RCC_SRDCCIPR_DFSDM2SEL
+/**
+  * @}
+  */
+#endif /* DFSDM2 */
+
+/** @defgroup RCCEx_SPDIFRX_Clock_Source  RCCEx SPDIFRX Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_SPDIFSEL_0)
+#define RCC_SPDIFRXCLKSOURCE_PLL        (0x00000000U)
+#define RCC_SPDIFRXCLKSOURCE_PLL2       RCC_D2CCIP1R_SPDIFSEL_0
+#define RCC_SPDIFRXCLKSOURCE_PLL3       RCC_D2CCIP1R_SPDIFSEL_1
+#define RCC_SPDIFRXCLKSOURCE_HSI        RCC_D2CCIP1R_SPDIFSEL
+#else
+#define RCC_SPDIFRXCLKSOURCE_PLL        (0x00000000U)
+#define RCC_SPDIFRXCLKSOURCE_PLL2       RCC_CDCCIP1R_SPDIFSEL_0
+#define RCC_SPDIFRXCLKSOURCE_PLL3       RCC_CDCCIP1R_SPDIFSEL_1
+#define RCC_SPDIFRXCLKSOURCE_HSI        RCC_CDCCIP1R_SPDIFSEL
+#endif /* RCC_D2CCIP1R_SPDIFSEL_0 */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CEC_Clock_Source  RCCEx CEC Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP2R_CECSEL_0)
+#define RCC_CECCLKSOURCE_LSE        (0x00000000U)
+#define RCC_CECCLKSOURCE_LSI         RCC_D2CCIP2R_CECSEL_0
+#define RCC_CECCLKSOURCE_CSI         RCC_D2CCIP2R_CECSEL_1
+#else
+#define RCC_CECCLKSOURCE_LSE        (0x00000000U)
+#define RCC_CECCLKSOURCE_LSI         RCC_CDCCIP2R_CECSEL_0
+#define RCC_CECCLKSOURCE_CSI         RCC_CDCCIP2R_CECSEL_1
+#endif /* RCC_D2CCIP2R_CECSEL_0 */
+/**
+  * @}
+  */
+
+
+/** @defgroup RCCEx_CLKP_Clock_Source  RCCEx CLKP Clock Source
+  * @{
+  */
+#if defined(RCC_D1CCIPR_CKPERSEL_0)
+#define RCC_CLKPSOURCE_HSI        (0x00000000U)
+#define RCC_CLKPSOURCE_CSI         RCC_D1CCIPR_CKPERSEL_0
+#define RCC_CLKPSOURCE_HSE         RCC_D1CCIPR_CKPERSEL_1
+#else
+#define RCC_CLKPSOURCE_HSI        (0x00000000U)
+#define RCC_CLKPSOURCE_CSI         RCC_CDCCIPR_CKPERSEL_0
+#define RCC_CLKPSOURCE_HSE         RCC_CDCCIPR_CKPERSEL_1
+#endif /* RCC_D1CCIPR_CKPERSEL_0 */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection
+  * @{
+  */
+#define RCC_TIMPRES_DESACTIVATED        (0x00000000U)
+#define RCC_TIMPRES_ACTIVATED            RCC_CFGR_TIMPRE
+
+/**
+  * @}
+  */
+
+#if defined(DUAL_CORE)
+
+/** @defgroup RCCEx_RCC_BootCx RCCEx RCC BootCx
+  * @{
+  */
+#define RCC_BOOT_C1        RCC_GCR_BOOT_C1
+#define RCC_BOOT_C2        RCC_GCR_BOOT_C2
+
+/**
+  * @}
+  */
+#endif /*DUAL_CORE*/
+
+#if defined(DUAL_CORE)
+/** @defgroup RCCEx_RCC_WWDGx  RCCEx RCC WWDGx
+  * @{
+  */
+#define RCC_WWDG1        RCC_GCR_WW1RSC
+#define RCC_WWDG2        RCC_GCR_WW2RSC
+
+/**
+  * @}
+  */
+
+#else
+
+/** @defgroup RCCEx_RCC_WWDGx  RCCEx RCC WWDGx
+  * @{
+  */
+#define RCC_WWDG1        RCC_GCR_WW1RSC
+
+/**
+  * @}
+  */
+
+#endif /*DUAL_CORE*/
+
+/** @defgroup RCCEx_EXTI_LINE_LSECSS  RCC LSE CSS external interrupt line
+  * @{
+  */
+#define RCC_EXTI_LINE_LSECSS           EXTI_IMR1_IM18        /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_Status RCCEx CRS Status
+  * @{
+  */
+#define RCC_CRS_NONE                   (0x00000000U)
+#define RCC_CRS_TIMEOUT                (0x00000001U)
+#define RCC_CRS_SYNCOK                 (0x00000002U)
+#define RCC_CRS_SYNCWARN               (0x00000004U)
+#define RCC_CRS_SYNCERR                (0x00000008U)
+#define RCC_CRS_SYNCMISS               (0x00000010U)
+#define RCC_CRS_TRIMOVF                (0x00000020U)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
+  * @{
+  */
+#define RCC_CRS_SYNC_SOURCE_PIN       (0x00000000U)                            /*!< Synchro Signal source external pin, Available on STM32H7 Rev.B and above devices only */
+#define RCC_CRS_SYNC_SOURCE_LSE        CRS_CFGR_SYNCSRC_0                      /*!< Synchro Signal source LSE */
+#define RCC_CRS_SYNC_SOURCE_USB1       CRS_CFGR_SYNCSRC_1                      /*!< Synchro Signal source USB1 SOF (default) */
+#define RCC_CRS_SYNC_SOURCE_USB2      (CRS_CFGR_SYNCSRC_1|CRS_CFGR_SYNCSRC_0)  /*!< Synchro Signal source USB2 SOF */
+
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider
+  * @{
+  */
+#define RCC_CRS_SYNC_DIV1        (0x00000000U)           /*!< Synchro Signal not divided (default) */
+#define RCC_CRS_SYNC_DIV2        CRS_CFGR_SYNCDIV_0                         /*!< Synchro Signal divided by 2 */
+#define RCC_CRS_SYNC_DIV4        CRS_CFGR_SYNCDIV_1                         /*!< Synchro Signal divided by 4 */
+#define RCC_CRS_SYNC_DIV8        (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0)  /*!< Synchro Signal divided by 8 */
+#define RCC_CRS_SYNC_DIV16       CRS_CFGR_SYNCDIV_2                        /*!< Synchro Signal divided by 16 */
+#define RCC_CRS_SYNC_DIV32       (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
+#define RCC_CRS_SYNC_DIV64       (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
+#define RCC_CRS_SYNC_DIV128      CRS_CFGR_SYNCDIV                         /*!< Synchro Signal divided by 128 */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity
+  * @{
+  */
+#define RCC_CRS_SYNC_POLARITY_RISING   (0x00000000U) /*!< Synchro Active on rising edge (default) */
+#define RCC_CRS_SYNC_POLARITY_FALLING  CRS_CFGR_SYNCPOL        /*!< Synchro Active on falling edge */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault
+  * @{
+  */
+#define RCC_CRS_RELOADVALUE_DEFAULT    (0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds
+                                                                    to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault
+  * @{
+  */
+#define RCC_CRS_ERRORLIMIT_DEFAULT     (0x00000022U) /*!< Default Frequency error limit */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault
+  * @{
+  */
+#define RCC_CRS_HSI48CALIBRATION_DEFAULT (0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
+                                                                      The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
+                                                                      corresponds to a higher output frequency */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection
+  * @{
+  */
+#define RCC_CRS_FREQERRORDIR_UP        (0x00000000U)   /*!< Upcounting direction, the actual frequency is above the target */
+#define RCC_CRS_FREQERRORDIR_DOWN      (CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
+  * @{
+  */
+#define RCC_CRS_IT_SYNCOK              CRS_CR_SYNCOKIE       /*!< SYNC event OK */
+#define RCC_CRS_IT_SYNCWARN            CRS_CR_SYNCWARNIE     /*!< SYNC warning */
+#define RCC_CRS_IT_ERR                 CRS_CR_ERRIE          /*!< Error */
+#define RCC_CRS_IT_ESYNC               CRS_CR_ESYNCIE        /*!< Expected SYNC */
+#define RCC_CRS_IT_SYNCERR             CRS_CR_ERRIE          /*!< SYNC error */
+#define RCC_CRS_IT_SYNCMISS            CRS_CR_ERRIE          /*!< SYNC missed */
+#define RCC_CRS_IT_TRIMOVF             CRS_CR_ERRIE          /*!< Trimming overflow or underflow */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
+  * @{
+  */
+#define RCC_CRS_FLAG_SYNCOK            CRS_ISR_SYNCOKF       /*!< SYNC event OK flag     */
+#define RCC_CRS_FLAG_SYNCWARN          CRS_ISR_SYNCWARNF     /*!< SYNC warning flag      */
+#define RCC_CRS_FLAG_ERR               CRS_ISR_ERRF          /*!< Error flag        */
+#define RCC_CRS_FLAG_ESYNC             CRS_ISR_ESYNCF        /*!< Expected SYNC flag     */
+#define RCC_CRS_FLAG_SYNCERR           CRS_ISR_SYNCERR       /*!< SYNC error */
+#define RCC_CRS_FLAG_SYNCMISS          CRS_ISR_SYNCMISS      /*!< SYNC missed*/
+#define RCC_CRS_FLAG_TRIMOVF           CRS_ISR_TRIMOVF       /*!< Trimming overflow or underflow */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
+  * @{
+  */
+
+/** @brief  Macros to enable or disable PLL2.
+  * @note   After enabling PLL2, the application software should wait on
+  *         PLL2RDY flag to be set indicating that PLL2 clock is stable and can
+  *         be used as kernel clock source.
+  * @note   PLL2 is disabled by hardware when entering STOP and STANDBY modes.
+  */
+#define __HAL_RCC_PLL2_ENABLE()         SET_BIT(RCC->CR, RCC_CR_PLL2ON)
+#define __HAL_RCC_PLL2_DISABLE()        CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON)
+
+/**
+  * @brief  Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK)
+  * @note   Enabling/disabling  those Clocks can be done only when the PLL2 is disabled,
+  *         This is mainly used to save Power.
+  * @param  __RCC_PLL2ClockOut__ Specifies the PLL2 clock to be outputted
+  *          This parameter can be one of the following values:
+  *            @arg RCC_PLL2_DIVP: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
+  *            @arg RCC_PLL2_DIVQ: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
+  *            @arg RCC_PLL2_DIVR: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
+  *
+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  *
+  * @retval None
+  */
+#define __HAL_RCC_PLL2CLKOUT_ENABLE(__RCC_PLL2ClockOut__)   SET_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))
+
+#define __HAL_RCC_PLL2CLKOUT_DISABLE(__RCC_PLL2ClockOut__)  CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))
+
+/**
+  * @brief  Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO
+  * @note   Enabling/disabling  Fractional Part can be any time  without the need to stop the PLL2
+  * @retval None
+  */
+#define __HAL_RCC_PLL2FRACN_ENABLE()   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)
+
+#define __HAL_RCC_PLL2FRACN_DISABLE()  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)
+
+/**
+  * @brief  Macro to configures the PLL2  multiplication and division factors.
+  * @note   This function must be used only when PLL2 is disabled.
+  *
+  * @param  __PLL2M__ specifies the division factor for PLL2 VCO input clock
+  *          This parameter must be a number between 1 and 63.
+  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
+  *         frequency ranges from 1 to 16 MHz.
+  *
+  * @param  __PLL2N__ specifies the multiplication factor for PLL2 VCO output clock
+  *          This parameter must be a number between 4 and 512 or between 8 and 420(*).
+  * @note   You have to set the PLL2N parameter correctly to ensure that the VCO
+  *         output frequency is between 150 and 420 MHz (when in medium VCO range) or
+  *         between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range)
+  *
+  * @param  __PLL2P__ specifies the division factor for peripheral kernel clocks
+  *          This parameter must be a number between 1 and 128.
+  *
+  * @param  __PLL2Q__ specifies the division factor for peripheral kernel clocks
+  *          This parameter must be a number between 1 and 128.
+  *
+  * @param  __PLL2R__ specifies the division factor for peripheral kernel clocks
+  *          This parameter must be a number between 1 and 128.
+  *
+  * @note   To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR)
+  *         is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible
+  *         value to  __PLL2P__, __PLL2Q__ or __PLL2R__ parameters.
+  * @retval None
+  *
+  *  (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  */
+
+#define __HAL_RCC_PLL2_CONFIG(__PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__,__PLL2R__ ) \
+                  do{ \
+                       MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM2) , ( (__PLL2M__) <<12U));  \
+                       WRITE_REG (RCC->PLL2DIVR , ( (((__PLL2N__) - 1U ) & RCC_PLL2DIVR_N2) | ((((__PLL2P__) -1U ) << 9U) & RCC_PLL2DIVR_P2) | \
+                       ((((__PLL2Q__) -1U) << 16U) & RCC_PLL2DIVR_Q2) | ((((__PLL2R__)- 1U) << 24U) & RCC_PLL2DIVR_R2))); \
+                    } while(0)
+
+/**
+  * @brief  Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor
+  *
+  * @note   These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO
+  *
+  * @param  __RCC_PLL2FRACN__ Specifies Fractional Part Of The Multiplication factor for PLL2 VCO
+  *                           It should be a value between 0 and 8191
+  * @note   Warning: the software has to set correctly these bits to insure that the VCO
+  *                  output frequency is between its valid frequency range, which is:
+  *                  192 to 836 MHz or 128 to 560 MHz(*) if PLL2VCOSEL = 0
+  *                  150 to 420 MHz if PLL2VCOSEL = 1.
+  *
+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  *
+  * @retval None
+  */
+#define  __HAL_RCC_PLL2FRACN_CONFIG(__RCC_PLL2FRACN__) \
+                 MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2,((uint32_t)(__RCC_PLL2FRACN__) << RCC_PLL2FRACR_FRACN2_Pos))
+
+/** @brief  Macro to select  the PLL2  reference frequency range.
+  * @param  __RCC_PLL2VCIRange__ specifies the PLL2 input frequency range
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PLL2VCIRANGE_0: Range frequency is between 1 and 2 MHz
+  *            @arg RCC_PLL2VCIRANGE_1: Range frequency is between 2 and 4 MHz
+  *            @arg RCC_PLL2VCIRANGE_2: Range frequency is between 4 and 8 MHz
+  *            @arg RCC_PLL2VCIRANGE_3: Range frequency is between 8 and 16 MHz
+  * @retval None
+  */
+#define __HAL_RCC_PLL2_VCIRANGE(__RCC_PLL2VCIRange__) \
+                  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, (__RCC_PLL2VCIRange__))
+
+
+/** @brief  Macro to select  the PLL2  reference frequency range.
+  * @param  __RCC_PLL2VCORange__ Specifies the PLL2 input frequency range
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PLL2VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*)
+  *            @arg RCC_PLL2VCOMEDIUM: Range frequency is between 150 and 420 MHz
+  *
+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  *
+  * @retval None
+  */
+#define __HAL_RCC_PLL2_VCORANGE(__RCC_PLL2VCORange__) \
+                  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, (__RCC_PLL2VCORange__))
+
+/** @brief  Macros to enable or disable the main PLL3.
+  * @note   After enabling  PLL3, the application software should wait on
+  *         PLL3RDY flag to be set indicating that PLL3 clock is stable and can
+  *         be used as kernel clock source.
+  * @note   PLL3 is disabled by hardware when entering STOP and STANDBY modes.
+  */
+#define __HAL_RCC_PLL3_ENABLE()         SET_BIT(RCC->CR, RCC_CR_PLL3ON)
+#define __HAL_RCC_PLL3_DISABLE()        CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON)
+
+/**
+  * @brief  Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO
+  * @note   Enabling/disabling  Fractional Part can be any time  without the need to stop the PLL3
+  * @retval None
+  */
+#define __HAL_RCC_PLL3FRACN_ENABLE()   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)
+
+#define __HAL_RCC_PLL3FRACN_DISABLE()  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)
+
+/**
+  * @brief  Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK)
+  * @note   Enabling/disabling  those Clocks can be done only when the PLL3 is disabled,
+  *         This is mainly used to save Power.
+  * @param  __RCC_PLL3ClockOut__ specifies the PLL3 clock to be outputted
+  *          This parameter can be one of the following values:
+  *            @arg RCC_PLL3_DIVP: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
+  *            @arg RCC_PLL3_DIVQ: This clock is used to generate peripherals clock  up to 400MHZ or 280MHZ(*)
+  *            @arg RCC_PLL3_DIVR: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
+  *
+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  *
+  * @retval None
+  */
+#define __HAL_RCC_PLL3CLKOUT_ENABLE(__RCC_PLL3ClockOut__)   SET_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))
+
+#define __HAL_RCC_PLL3CLKOUT_DISABLE(__RCC_PLL3ClockOut__)  CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))
+
+/**
+  * @brief  Macro to configures the PLL3  multiplication and division factors.
+  * @note   This function must be used only when PLL3 is disabled.
+  *
+  * @param  __PLL3M__ specifies the division factor for PLL3 VCO input clock
+  *          This parameter must be a number between 1 and 63.
+  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
+  *         frequency ranges from 1 to 16 MHz.
+  *
+  * @param  __PLL3N__ specifies the multiplication factor for PLL3 VCO output clock
+  *          This parameter must be a number between 4 and 512.
+  * @note   You have to set the PLL3N parameter correctly to ensure that the VCO
+  *         output frequency is between 150 and 420 MHz (when in medium VCO range) or
+  *         between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range)
+  *
+  * @param  __PLL3P__ specifies the division factor for peripheral kernel clocks
+  *          This parameter must be a number between 2 and 128 (where odd numbers not allowed)
+  *
+  * @param  __PLL3Q__ specifies the division factor for peripheral kernel clocks
+  *          This parameter must be a number between 1 and 128
+  *
+  * @param  __PLL3R__ specifies the division factor for peripheral kernel clocks
+  *          This parameter must be a number between 1 and 128
+  *
+  * @note   To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR)
+  *         is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible
+  *         value to  __PLL3P__, __PLL3Q__ or __PLL3R__ parameters.
+  * @retval None
+  *
+  *  (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  */
+
+#define __HAL_RCC_PLL3_CONFIG(__PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__,__PLL3R__ ) \
+                  do{ MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM3) , ( (__PLL3M__) <<20U));  \
+                         WRITE_REG (RCC->PLL3DIVR , ( (((__PLL3N__) - 1U ) & RCC_PLL3DIVR_N3) | ((((__PLL3P__) -1U ) << 9U) & RCC_PLL3DIVR_P3) | \
+                                   ((((__PLL3Q__) -1U) << 16U) & RCC_PLL3DIVR_Q3) | ((((__PLL3R__) - 1U) << 24U) & RCC_PLL3DIVR_R3))); \
+                       } while(0)
+
+
+
+/**
+  * @brief  Macro to configures  PLL3 clock Fractional Part of The Multiplication Factor
+  *
+  * @note   These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO
+  *
+  * @param  __RCC_PLL3FRACN__ specifies Fractional Part Of The Multiplication Factor for PLL3 VCO
+  *                            It should be a value between 0 and 8191
+  * @note   Warning: the software has to set correctly these bits to insure that the VCO
+  *                  output frequency is between its valid frequency range, which is:
+  *                  192 to 836 MHz or 128 to 560 MHz(*) if PLL3VCOSEL = 0
+  *                  150 to 420 MHz if PLL3VCOSEL = 1.
+  *
+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  *
+  * @retval None
+  */
+ #define  __HAL_RCC_PLL3FRACN_CONFIG(__RCC_PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << RCC_PLL3FRACR_FRACN3_Pos)
+
+/** @brief  Macro to select  the PLL3  reference frequency range.
+  * @param  __RCC_PLL3VCIRange__ specifies the PLL1 input frequency range
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PLL3VCIRANGE_0: Range frequency is between 1 and 2 MHz
+  *            @arg RCC_PLL3VCIRANGE_1: Range frequency is between 2 and 4 MHz
+  *            @arg RCC_PLL3VCIRANGE_2: Range frequency is between 4 and 8 MHz
+  *            @arg RCC_PLL3VCIRANGE_3: Range frequency is between 8 and 16 MHz
+  * @retval None
+  */
+#define __HAL_RCC_PLL3_VCIRANGE(__RCC_PLL3VCIRange__) \
+                  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, (__RCC_PLL3VCIRange__))
+
+
+/** @brief  Macro to select  the PLL3  reference frequency range.
+  * @param  __RCC_PLL3VCORange__ specifies the PLL1 input frequency range
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PLL3VCOWIDE: Range frequency is between 192 and 836 MHz  or between 128 to 560 MHz(*)
+  *            @arg RCC_PLL3VCOMEDIUM: Range frequency is between 150 and 420 MHz
+  *
+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  *
+  * @retval None
+  */
+#define __HAL_RCC_PLL3_VCORANGE(__RCC_PLL3VCORange__) \
+                  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__))
+/**
+  * @brief  Macro to Configure the SAI1 clock source.
+  * @param  __RCC_SAI1CLKSource__ defines the SAI1 clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL
+  *             @arg RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2
+  *             @arg RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3
+  *             @arg RCC_SAI1CLKSOURCE_OSC: SAI1 clock  = OSC
+  *             @arg RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock
+  * @retval None
+  */
+#if defined(RCC_D2CCIP1R_SAI1SEL)
+#define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__ )\
+                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__))
+#else
+#define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__ )\
+                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__))
+#endif /* RCC_D2CCIP1R_SAI1SEL */
+
+/** @brief  Macro to get the SAI1 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL
+  *             @arg RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2
+  *             @arg RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3
+  *             @arg RCC_SAI1CLKSOURCE_CLKP: SAI1 clock  = CLKP
+  *             @arg RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock
+  */
+#if defined(RCC_D2CCIP1R_SAI1SEL)
+#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL)))
+#else
+#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL)))
+#endif /* RCC_D2CCIP1R_SAI1SEL */
+
+/**
+  * @brief  Macro to Configure the SPDIFRX clock source.
+  * @param  __RCC_SPDIFCLKSource__ defines the SPDIFRX clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3,  or internal OSC clock
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SPDIFRXCLKSOURCE_PLL:  SPDIFRX clock = PLL
+  *             @arg RCC_SPDIFRXCLKSOURCE_PLL2: SPDIFRX clock = PLL2
+  *             @arg RCC_SPDIFRXCLKSOURCE_PLL3: SPDIFRX clock = PLL3
+  *             @arg RCC_SPDIFRXCLKSOURCE_HSI:  SPDIFRX clock  = HSI
+  * @retval None
+  */
+#if defined(RCC_D2CCIP1R_SPDIFSEL)
+#define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__ )\
+                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__))
+#else
+#define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__ )\
+                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__))
+#endif /* RCC_D2CCIP1R_SPDIFSEL */
+
+/**
+  * @brief  Macro to get the SPDIFRX clock source.
+  * @retval None
+  */
+#if defined(RCC_D2CCIP1R_SPDIFSEL)
+#define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL)))
+#else
+#define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL)))
+#endif /* RCC_D2CCIP1R_SPDIFSEL */
+
+#if defined(SAI3)
+/**
+  * @brief  Macro to Configure the SAI2/3 clock source.
+  * @param  __RCC_SAI23CLKSource__ defines the SAI2/3 clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SAI23CLKSOURCE_PLL: SAI2/3 clock = PLL
+  *             @arg RCC_SAI23CLKSOURCE_PLL2: SAI2/3 clock = PLL2
+  *             @arg RCC_SAI23CLKSOURCE_PLL3: SAI2/3 clock = PLL3
+  *             @arg RCC_SAI23CLKSOURCE_CLKP: SAI2/3 clock  = CLKP
+  *             @arg RCC_SAI23CLKSOURCE_PIN: SAI2/3 clock = External Clock
+  * @retval None
+  */
+#define __HAL_RCC_SAI23_CONFIG(__RCC_SAI23CLKSource__ )\
+                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL, (__RCC_SAI23CLKSource__))
+
+/** @brief  Macro to get the SAI2/3 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SAI23CLKSOURCE_PLL: SAI2/3 clock = PLL
+  *             @arg RCC_SAI23CLKSOURCE_PLL2: SAI2/3 clock = PLL2
+  *             @arg RCC_SAI23CLKSOURCE_PLL3: SAI2/3 clock = PLL3
+  *             @arg RCC_SAI23CLKSOURCE_CLKP: SAI2/3 clock  = CLKP
+  *             @arg RCC_SAI23CLKSOURCE_PIN: SAI2/3 clock = External Clock
+  */
+#define __HAL_RCC_GET_SAI23_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL)))
+
+/**
+  * @brief  Macro to Configure the SAI2 clock source.
+  * @param  __RCC_SAI2CLKSource__ defines the SAI2 clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SAI2CLKSOURCE_PLL: SAI2 clock = PLL
+  *             @arg RCC_SAI2CLKSOURCE_PLL2: SAI2 clock = PLL2
+  *             @arg RCC_SAI2CLKSOURCE_PLL3: SAI2 clock = PLL3
+  *             @arg RCC_SAI2CLKSOURCE_CLKP: SAI2 clock  = CLKP
+  *             @arg RCC_SAI2CLKSOURCE_PIN: SAI2 clock = External Clock
+  * @retval None
+  */
+#define __HAL_RCC_SAI2_CONFIG  __HAL_RCC_SAI23_CONFIG
+
+/** @brief  Macro to get the SAI2 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SAI2CLKSOURCE_PLL: SAI2 clock = PLL
+  *             @arg RCC_SAI2CLKSOURCE_PLL2: SAI2 clock = PLL2
+  *             @arg RCC_SAI2CLKSOURCE_PLL3: SAI2 clock = PLL3
+  *             @arg RCC_SAI2CLKSOURCE_CLKP: SAI2 clock  = CLKP
+  *             @arg RCC_SAI2CLKSOURCE_PIN: SAI2 clock = External Clock
+  */
+#define __HAL_RCC_GET_SAI2_SOURCE  __HAL_RCC_GET_SAI23_SOURCE
+
+/**
+  * @brief  Macro to Configure the SAI3 clock source.
+  * @param  __RCC_SAI3CLKSource__ defines the SAI3 clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SAI3CLKSOURCE_PLL: SAI3 clock = PLL
+  *             @arg RCC_SAI3CLKSOURCE_PLL2: SAI3 clock = PLL2
+  *             @arg RCC_SAI3CLKSOURCE_PLL3: SAI3 clock = PLL3
+  *             @arg RCC_SAI3CLKSOURCE_CLKP: SAI3 clock  = CLKP
+  *             @arg RCC_SAI3CLKSOURCE_PIN: SAI3 clock = External Clock
+  * @retval None
+  */
+#define __HAL_RCC_SAI3_CONFIG __HAL_RCC_SAI23_CONFIG
+
+/** @brief  Macro to get the SAI3 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SAI3CLKSOURCE_PLL: SAI3 clock = PLL
+  *             @arg RCC_SAI3CLKSOURCE_PLL2: SAI3 clock = PLL2
+  *             @arg RCC_SAI3CLKSOURCE_PLL3: SAI3 clock = PLL3
+  *             @arg RCC_SAI3CLKSOURCE_CLKP: SAI3 clock  = CLKP
+  *             @arg RCC_SAI3CLKSOURCE_PIN: SAI3 clock = External Clock
+  */
+#define __HAL_RCC_GET_SAI3_SOURCE  __HAL_RCC_GET_SAI23_SOURCE
+#endif /* SAI3 */
+
+#if defined(RCC_CDCCIP1R_SAI2ASEL)
+/**
+  * @brief  Macro to Configure the SAI2A clock source.
+  * @param  __RCC_SAI2ACLKSource__ defines the SAI2A clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SAI2ACLKSOURCE_PLL: SAI2A clock = PLL
+  *             @arg RCC_SAI2ACLKSOURCE_PLL2: SAI2A clock = PLL2
+  *             @arg RCC_SAI2ACLKSOURCE_PLL3: SAI2A clock = PLL3
+  *             @arg RCC_SAI2ACLKSOURCE_CLKP: SAI2A clock  = CLKP
+  *             @arg RCC_SAI2ACLKSOURCE_PIN: SAI2A clock = External Clock
+  *             @arg RCC_SAI2ACLKSOURCE_SPDIF: SAI2A clock = SPDIF Clock
+  * @retval None
+  */
+#define __HAL_RCC_SAI2A_CONFIG(__RCC_SAI2ACLKSource__ )\
+                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2ASEL, (__RCC_SAI2ACLKSource__))
+
+/** @brief  Macro to get the SAI2A clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SAI2CLKSOURCE_PLL: SAI2A clock = PLL
+  *             @arg RCC_SAI2CLKSOURCE_PLL2: SAI2A clock = PLL2
+  *             @arg RCC_SAI2CLKSOURCE_PLL3: SAI2A clock = PLL3
+  *             @arg RCC_SAI2CLKSOURCE_CLKP: SAI2A clock  = CLKP
+  *             @arg RCC_SAI2CLKSOURCE_PIN: SAI2A clock = External Clock
+  *             @arg RCC_SAI2ACLKSOURCE_SPDIF: SAI2A clock = SPDIF Clock
+  */
+#define __HAL_RCC_GET_SAI2A_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2ASEL)))
+#endif /* defined(RCC_CDCCIP1R_SAI2ASEL) */
+
+#if defined(RCC_CDCCIP1R_SAI2BSEL)
+/**
+  * @brief  Macro to Configure the SAI2B clock source.
+  * @param  __RCC_SAI2BCLKSource__ defines the SAI2B clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SAI2BCLKSOURCE_PLL: SAI2B clock = PLL
+  *             @arg RCC_SAI2BCLKSOURCE_PLL2: SAI2B clock = PLL2
+  *             @arg RCC_SAI2BCLKSOURCE_PLL3: SAI2B clock = PLL3
+  *             @arg RCC_SAI2BCLKSOURCE_CLKP: SAI2B clock  = CLKP
+  *             @arg RCC_SAI2BCLKSOURCE_PIN: SAI2B clock = External Clock
+  *             @arg RCC_SAI2BCLKSOURCE_SPDIF: SAI2B clock = SPDIF Clock
+  * @retval None
+  */
+#define __HAL_RCC_SAI2B_CONFIG(__RCC_SAI2BCLKSource__ )\
+                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2BSEL, (__RCC_SAI2BCLKSource__))
+
+/** @brief  Macro to get the SAI2B clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SAI2BCLKSOURCE_PLL: SAI2B clock = PLL
+  *             @arg RCC_SAI2BCLKSOURCE_PLL2: SAI2B clock = PLL2
+  *             @arg RCC_SAI2BCLKSOURCE_PLL3: SAI2B clock = PLL3
+  *             @arg RCC_SAI2BCLKSOURCE_CLKP: SAI2B clock  = CLKP
+  *             @arg RCC_SAI2BCLKSOURCE_PIN: SAI2B clock = External Clock
+  *             @arg RCC_SAI2BCLKSOURCE_SPDIF: SAI2B clock = SPDIF Clock
+  */
+#define __HAL_RCC_GET_SAI2B_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2BSEL)))
+#endif /* defined(RCC_CDCCIP1R_SAI2BSEL) */
+
+
+#if defined(SAI4_Block_A)
+/**
+  * @brief  Macro to Configure the SAI4A clock source.
+  * @param  __RCC_SAI4ACLKSource__ defines the SAI4A clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SAI4ACLKSOURCE_PLL: SAI4A clock = PLL
+  *             @arg RCC_SAI4ACLKSOURCE_PLL2: SAI4A clock = PLL2
+  *             @arg RCC_SAI4ACLKSOURCE_PLL3: SAI4A clock = PLL3
+  *             @arg RCC_SAI4ACLKSOURCE_CLKP: SAI4A clock  = CLKP
+  *             @arg RCC_SAI4ACLKSOURCE_PIN: SAI4A clock = External Clock
+  * @retval None
+  */
+#define __HAL_RCC_SAI4A_CONFIG(__RCC_SAI4ACLKSource__ )\
+                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL, (__RCC_SAI4ACLKSource__))
+
+/** @brief  Macro to get the SAI4A clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SAI4ACLKSOURCE_PLL: SAI4B clock = PLL
+  *             @arg RCC_SAI4ACLKSOURCE_PLL2: SAI4B clock = PLL2
+  *             @arg RCC_SAI4ACLKSOURCE_PLL3: SAI4B clock = PLL3
+  *             @arg RCC_SAI4ACLKSOURCE_CLKP: SAI4B clock  = CLKP
+  *             @arg RCC_SAI4ACLKSOURCE_PIN: SAI4B clock = External Clock
+  */
+#define __HAL_RCC_GET_SAI4A_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL)))
+#endif /* SAI4_Block_A */
+
+#if defined(SAI4_Block_B)
+/**
+  * @brief  Macro to Configure the SAI4B clock source.
+  * @param  __RCC_SAI4BCLKSource__ defines the SAI4B clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SAI4BCLKSOURCE_PLL: SAI4B clock = PLL
+  *             @arg RCC_SAI4BCLKSOURCE_PLL2: SAI4B clock = PLL2
+  *             @arg RCC_SAI4BCLKSOURCE_PLL3: SAI4B clock = PLL3
+  *             @arg RCC_SAI4BCLKSOURCE_CLKP: SAI4B clock  = CLKP
+  *             @arg RCC_SAI4BCLKSOURCE_PIN: SAI4B clock = External Clock
+  * @retval None
+  */
+#define __HAL_RCC_SAI4B_CONFIG(__RCC_SAI4BCLKSource__ )\
+                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL, (__RCC_SAI4BCLKSource__))
+
+/** @brief  Macro to get the SAI4B clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SAI4BCLKSOURCE_PLL: SAI4B clock = PLL
+  *             @arg RCC_SAI4BCLKSOURCE_PLL2: SAI4B clock = PLL2
+  *             @arg RCC_SAI4BCLKSOURCE_PLL3: SAI4B clock = PLL3
+  *             @arg RCC_SAI4BCLKSOURCE_CLKP: SAI4B clock  = CLKP
+  *             @arg RCC_SAI4BCLKSOURCE_PIN: SAI4B clock = External Clock
+  */
+#define __HAL_RCC_GET_SAI4B_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL)))
+#endif /* SAI4_Block_B */
+
+/** @brief macro to configure the I2C1/2/3 clock (I2C123CLK).
+  *
+  * @param  __I2C123CLKSource__ specifies the I2C1/2/3 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3 clock
+  *            @arg RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3 clock
+  *            @arg RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3 clock
+  *            @arg RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3 clock
+  */
+#if defined(RCC_D2CCIP2R_I2C123SEL)
+#define __HAL_RCC_I2C123_CONFIG(__I2C123CLKSource__) \
+                  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C123CLKSource__))
+#else
+#define __HAL_RCC_I2C123_CONFIG(__I2C123CLKSource__) \
+                  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_I2C123SEL, (uint32_t)(__I2C123CLKSource__))
+#endif /* RCC_D2CCIP2R_I2C123SEL */
+
+/** @brief  macro to get the I2C1/2/3 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3 clock
+  *            @arg RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3 clock
+  *            @arg RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3 clock
+  *            @arg RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3 clock
+  */
+#if defined(RCC_D2CCIP2R_I2C123SEL)
+#define __HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL)))
+#else
+#define __HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_I2C123SEL)))
+#endif /* RCC_D2CCIP2R_I2C123SEL */
+
+/** @brief macro to configure the I2C1 clock (I2C1CLK).
+  *
+  * @param  __I2C1CLKSource__ specifies the I2C1 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock
+  *            @arg RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock
+  *            @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
+  *            @arg RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock
+  */
+#define __HAL_RCC_I2C1_CONFIG  __HAL_RCC_I2C123_CONFIG
+
+/** @brief  macro to get the I2C1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock
+  *            @arg RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock
+  *            @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
+  *            @arg RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock
+  */
+#define __HAL_RCC_GET_I2C1_SOURCE __HAL_RCC_GET_I2C123_SOURCE
+
+/** @brief macro to configure the I2C2 clock (I2C2CLK).
+  *
+  * @param  __I2C2CLKSource__ specifies the I2C2 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock
+  *            @arg RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock
+  *            @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
+  *            @arg RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock
+  */
+#define __HAL_RCC_I2C2_CONFIG __HAL_RCC_I2C123_CONFIG
+
+/** @brief  macro to get the I2C2 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock
+  *            @arg RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock
+  *            @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
+  *            @arg RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock
+  */
+#define __HAL_RCC_GET_I2C2_SOURCE __HAL_RCC_GET_I2C123_SOURCE
+
+/** @brief macro to configure the I2C3 clock (I2C3CLK).
+  *
+  * @param  __I2C3CLKSource__ specifies the I2C3 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock
+  *            @arg RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock
+  *            @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
+  *            @arg RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock
+  */
+#define __HAL_RCC_I2C3_CONFIG __HAL_RCC_I2C123_CONFIG
+
+/** @brief  macro to get the I2C3 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock
+  *            @arg RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock
+  *            @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
+  *            @arg RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock
+  */
+#define __HAL_RCC_GET_I2C3_SOURCE __HAL_RCC_GET_I2C123_SOURCE
+
+/** @brief macro to configure the I2C4 clock (I2C4CLK).
+  *
+  * @param  __I2C4CLKSource__ specifies the I2C4 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock
+  *            @arg RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock
+  *            @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
+  *            @arg RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock
+  */
+#if defined(RCC_D3CCIPR_I2C4SEL)
+#define __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) \
+                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__))
+#else
+#define __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) \
+                  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__))
+#endif /* RCC_D3CCIPR_I2C4SEL */
+
+/** @brief  macro to get the I2C4 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock
+  *            @arg RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock
+  *            @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
+  *            @arg RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock
+  */
+#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL)))
+
+/** @brief macro to configure the USART1/6/9* /10* clock (USART16CLK).
+  *
+  * @param  __USART16CLKSource__ specifies the USART1/6/9* /10* clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6/9* /10* clock
+  *            @arg RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6/9* /10* clock
+  *            @arg RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6/9* /10* clock
+  *            @arg RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6/9* /10* clock
+  *            @arg RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6/9* /10* clock
+  *            @arg RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6/9* /10* clock
+  *
+  * (*) : Available on some STM32H7 lines only.
+  */
+#if defined(RCC_D2CCIP2R_USART16SEL)
+#define __HAL_RCC_USART16_CONFIG(__USART16CLKSource__) \
+                  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART16CLKSource__))
+#else
+#define __HAL_RCC_USART16910_CONFIG(__USART16910CLKSource__) \
+                  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART16910SEL, (uint32_t)(__USART16910CLKSource__))
+/* alias */
+#define __HAL_RCC_USART16_CONFIG  __HAL_RCC_USART16910_CONFIG
+#endif /* RCC_D2CCIP2R_USART16SEL */
+
+/** @brief  macro to get the USART1/6/9* /10* clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6/9* /10* clock
+  *            @arg RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6/9* /10* clock
+  *            @arg RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6/9* /10* clock
+  *            @arg RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6/9* /10* clock
+  *            @arg RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6/9* /10* clock
+  *            @arg RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6/9* /10* clock
+  *
+  * (*) : Available on some STM32H7 lines only.
+  */
+#if defined(RCC_D2CCIP2R_USART16SEL)
+#define __HAL_RCC_GET_USART16_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL)))
+#else
+#define __HAL_RCC_GET_USART16910_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART16910SEL)))
+/* alias*/
+#define  __HAL_RCC_GET_USART16_SOURCE  __HAL_RCC_GET_USART16910_SOURCE
+#endif /* RCC_D2CCIP2R_USART16SEL */
+
+/** @brief macro to configure the USART234578 clock (USART234578CLK).
+  *
+  * @param  __USART234578CLKSource__ specifies the USART2/3/4/5/7/8 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock
+  *            @arg RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock
+  *            @arg RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock
+  *            @arg RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock
+  *            @arg RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock
+  *            @arg RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock
+  */
+#if defined(RCC_D2CCIP2R_USART28SEL)
+#define __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) \
+                  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART234578CLKSource__))
+#else
+#define __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) \
+                  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL, (uint32_t)(__USART234578CLKSource__))
+#endif /* RCC_D2CCIP2R_USART28SEL */
+
+/** @brief  macro to get the USART2/3/4/5/7/8 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock
+  *            @arg RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock
+  *            @arg RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock
+  *            @arg RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock
+  *            @arg RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock
+  *            @arg RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock
+  */
+#if defined(RCC_D2CCIP2R_USART28SEL)
+#define __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
+#else
+#define __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL)))
+#endif /* RCC_D2CCIP2R_USART28SEL */
+
+/** @brief macro to configure the USART1 clock (USART1CLK).
+  *
+  * @param  __USART1CLKSource__ specifies the USART1 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
+  */
+#define __HAL_RCC_USART1_CONFIG  __HAL_RCC_USART16_CONFIG
+
+/** @brief  macro to get the USART1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
+  */
+#define __HAL_RCC_GET_USART1_SOURCE  __HAL_RCC_GET_USART16_SOURCE
+
+/** @brief macro to configure the USART2 clock (USART2CLK).
+  *
+  * @param  __USART2CLKSource__ specifies the USART2 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
+  */
+#define __HAL_RCC_USART2_CONFIG  __HAL_RCC_USART234578_CONFIG
+
+/** @brief  macro to get the USART2 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
+  */
+#define __HAL_RCC_GET_USART2_SOURCE __HAL_RCC_GET_USART234578_SOURCE
+
+/** @brief macro to configure the USART3 clock (USART3CLK).
+  *
+  * @param  __USART3CLKSource__ specifies the USART3 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_USART3CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
+  */
+#define __HAL_RCC_USART3_CONFIG  __HAL_RCC_USART234578_CONFIG
+
+/** @brief  macro to get the USART3 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
+  */
+#define __HAL_RCC_GET_USART3_SOURCE  __HAL_RCC_GET_USART234578_SOURCE
+
+/** @brief macro to configure the UART4 clock (UART4CLK).
+  *
+  * @param  __UART4CLKSource__ specifies the UART4 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
+  */
+#define __HAL_RCC_UART4_CONFIG  __HAL_RCC_USART234578_CONFIG
+
+/** @brief  macro to get the UART4 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
+  */
+#define __HAL_RCC_GET_UART4_SOURCE  __HAL_RCC_GET_USART234578_SOURCE
+
+/** @brief macro to configure the UART5 clock (UART5CLK).
+  *
+  * @param  __UART5CLKSource__ specifies the UART5 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
+  */
+#define __HAL_RCC_UART5_CONFIG  __HAL_RCC_USART234578_CONFIG
+
+/** @brief  macro to get the UART5 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
+  */
+#define __HAL_RCC_GET_UART5_SOURCE  __HAL_RCC_GET_USART234578_SOURCE
+
+/** @brief macro to configure the USART6 clock (USART6CLK).
+  *
+  * @param  __USART6CLKSource__ specifies the USART6 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
+  */
+#define __HAL_RCC_USART6_CONFIG  __HAL_RCC_USART16_CONFIG
+
+/** @brief  macro to get the USART6 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
+  */
+#define __HAL_RCC_GET_USART6_SOURCE  __HAL_RCC_GET_USART16_SOURCE
+
+/** @brief macro to configure the UART5 clock (UART7CLK).
+  *
+  * @param  __UART7CLKSource__ specifies the UART7 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
+  */
+#define __HAL_RCC_UART7_CONFIG  __HAL_RCC_USART234578_CONFIG
+
+/** @brief  macro to get the UART7 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
+  */
+#define __HAL_RCC_GET_UART7_SOURCE  __HAL_RCC_GET_USART234578_SOURCE
+
+/** @brief macro to configure the UART8 clock (UART8CLK).
+  *
+  * @param  __UART8CLKSource__ specifies the UART8 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
+  */
+#define __HAL_RCC_UART8_CONFIG  __HAL_RCC_USART234578_CONFIG
+
+/** @brief  macro to get the UART8 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
+  */
+#define __HAL_RCC_GET_UART8_SOURCE  __HAL_RCC_GET_USART234578_SOURCE
+
+#if defined(UART9)
+/** @brief macro to configure the UART9 clock (UART9CLK).
+  *
+  * @param  __UART8CLKSource__ specifies the UART8 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_UART9CLKSOURCE_D2PCLK1: APB1 Clock selected as UART9 clock
+  *            @arg RCC_UART9CLKSOURCE_PLL2: PLL2_Q Clock selected as UART9 clock
+  *            @arg RCC_UART9CLKSOURCE_PLL3: PLL3_Q Clock selected as UART9 clock
+  *            @arg RCC_UART9CLKSOURCE_HSI: HSI selected as UART9 clock
+  *            @arg RCC_UART9CLKSOURCE_CSI: CSI Clock selected as UART9 clock
+  *            @arg RCC_UART9CLKSOURCE_LSE: LSE selected as UART9 clock
+  */
+#define __HAL_RCC_UART9_CONFIG  __HAL_RCC_USART16_CONFIG
+
+/** @brief  macro to get the UART9 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_UART9CLKSOURCE_D2PCLK1: APB1 Clock selected as UART99 clock
+  *            @arg RCC_UART9CLKSOURCE_PLL2: PLL2_Q Clock selected as UART99 clock
+  *            @arg RCC_UART9CLKSOURCE_PLL3: PLL3_Q Clock selected as UART99 clock
+  *            @arg RCC_UART9CLKSOURCE_HSI: HSI selected as UART9 clock
+  *            @arg RCC_UART9CLKSOURCE_CSI: CSI Clock selected as UART9 clock
+  *            @arg RCC_UART9CLKSOURCE_LSE: LSE selected as UART9 clock
+  */
+#define __HAL_RCC_GET_UART9_SOURCE  __HAL_RCC_GET_USART16_SOURCE
+#endif /* UART9 */
+
+#if defined(USART10)
+/** @brief macro to configure the USART10 clock (USART10CLK).
+  *
+  * @param  __UART8CLKSource__ specifies the UART8 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_USART10CLKSOURCE_D2PCLK1: APB1 Clock selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_PLL2: PLL2_Q Clock selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_PLL3: PLL3_Q Clock selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_HSI: HSI selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_CSI: CSI Clock selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_LSE: LSE selected as USART10 clock
+  */
+#define __HAL_RCC_USART10_CONFIG  __HAL_RCC_USART16_CONFIG
+
+/** @brief  macro to get the USART10 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_USART10CLKSOURCE_D2PCLK1: APB1 Clock selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_PLL2: PLL2_Q Clock selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_PLL3: PLL3_Q Clock selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_HSI: HSI selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_CSI: CSI Clock selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_LSE: LSE selected as USART10 clock
+  */
+#define __HAL_RCC_GET_USART10_SOURCE  __HAL_RCC_GET_USART16_SOURCE
+#endif /* USART10 */
+
+/** @brief macro to configure the LPUART1 clock (LPUART1CLK).
+  *
+  * @param  __LPUART1CLKSource__ specifies the LPUART1 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock
+  */
+#if defined (RCC_D3CCIPR_LPUART1SEL)
+#define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \
+                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))
+#else
+#define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \
+                  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))
+#endif /* RCC_D3CCIPR_LPUART1SEL */
+
+/** @brief  macro to get the LPUART1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock
+  */
+#if defined (RCC_D3CCIPR_LPUART1SEL)
+#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL)))
+#else
+#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL)))
+#endif /* RCC_D3CCIPR_LPUART1SEL */
+
+/** @brief  macro to configure the LPTIM1 clock source.
+  *
+  * @param  __LPTIM1CLKSource__ specifies the LPTIM1 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock
+  */
+#if defined(RCC_D2CCIP2R_LPTIM1SEL)
+#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \
+                  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))
+#else
+#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \
+                  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))
+#endif /* RCC_D2CCIP2R_LPTIM1SEL */
+
+/** @brief  macro to get the LPTIM1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock
+  */
+#if defined(RCC_D2CCIP2R_LPTIM1SEL)
+#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL)))
+#else
+#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL)))
+#endif /* RCC_D2CCIP2R_LPTIM1SEL */
+
+/** @brief  macro to configure the LPTIM2 clock source.
+  *
+  * @param  __LPTIM2CLKSource__ specifies the LPTIM2 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock
+  */
+#if defined(RCC_D3CCIPR_LPTIM2SEL)
+#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) \
+                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__))
+#else
+#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) \
+                  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__))
+#endif /* RCC_D3CCIPR_LPTIM2SEL */
+
+/** @brief  macro to get the LPTIM2 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock
+  */
+#if defined(RCC_D3CCIPR_LPTIM2SEL)
+#define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL)))
+#else
+#define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL)))
+#endif /* RCC_D3CCIPR_LPTIM2SEL */
+
+/** @brief  macro to configure the LPTIM3/4/5 clock source.
+  *
+  * @param  __LPTIM345CLKSource__ specifies the LPTIM3/4/5 clock source.
+  *            @arg RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock
+  *            @arg RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock
+  *            @arg RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock
+  *            @arg RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock
+  *            @arg RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock
+  *            @arg RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock
+  */
+#if defined(RCC_D3CCIPR_LPTIM345SEL)
+#define __HAL_RCC_LPTIM345_CONFIG(__LPTIM345CLKSource__) \
+                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM345CLKSource__))
+#else
+#define __HAL_RCC_LPTIM345_CONFIG(__LPTIM3CLKSource__) \
+                  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL, (uint32_t)(__LPTIM3CLKSource__))
+#endif /* RCC_D3CCIPR_LPTIM345SEL */
+
+/** @brief  macro to get the LPTIM3/4/5 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock
+  *            @arg RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock
+  *            @arg RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock
+  *            @arg RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock
+  *            @arg RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock
+  *            @arg RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock
+  */
+#if defined(RCC_D3CCIPR_LPTIM345SEL)
+#define __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL)))
+#else
+#define __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL)))
+#endif /* RCC_D3CCIPR_LPTIM345SEL */
+
+/** @brief  macro to configure the LPTIM3 clock source.
+  *
+  * @param  __LPTIM3CLKSource__ specifies the LPTIM3 clock source.
+  *            @arg RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock
+  */
+#define __HAL_RCC_LPTIM3_CONFIG  __HAL_RCC_LPTIM345_CONFIG
+
+/** @brief  macro to get the LPTIM3 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock
+  */
+#define __HAL_RCC_GET_LPTIM3_SOURCE  __HAL_RCC_GET_LPTIM345_SOURCE
+
+#if defined(LPTIM4)
+/** @brief  macro to configure the LPTIM4 clock source.
+  *
+  * @param  __LPTIM4CLKSource__ specifies the LPTIM4 clock source.
+  *            @arg RCC_LPTIM4CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_LSE: LSE selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_LSI: LSI Clock selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_CLKP: CLKP selected as LPTIM4 clock
+  */
+#define __HAL_RCC_LPTIM4_CONFIG  __HAL_RCC_LPTIM345_CONFIG
+
+
+/** @brief  macro to get the LPTIM4 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_LPTIM4CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_LSE: LSE selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_LSI: LSI Clock selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_CLKP: CLKP selected as LPTIM4 clock
+  */
+#define __HAL_RCC_GET_LPTIM4_SOURCE  __HAL_RCC_GET_LPTIM345_SOURCE
+#endif /* LPTIM4 */
+
+#if defined(LPTIM5)
+/** @brief  macro to configure the LPTIM5 clock source.
+  *
+  * @param  __LPTIM5CLKSource__ specifies the LPTIM5 clock source.
+  *            @arg RCC_LPTIM5CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_LSE: LSE selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_LSI: LSI Clock selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_CLKP: CLKP selected as LPTIM5 clock
+  */
+#define __HAL_RCC_LPTIM5_CONFIG  __HAL_RCC_LPTIM345_CONFIG
+
+
+/** @brief  macro to get the LPTIM5 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_LPTIM5CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_LSE: LSE selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_LSI: LSI Clock selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_CLKP: CLKP selected as LPTIM5 clock
+  */
+#define __HAL_RCC_GET_LPTIM5_SOURCE  __HAL_RCC_GET_LPTIM345_SOURCE
+#endif /* LPTIM5 */
+
+#if defined(QUADSPI)
+/** @brief  macro to configure the QSPI clock source.
+  *
+  * @param  __QSPICLKSource__ specifies the QSPI clock source.
+  *            @arg RCC_RCC_QSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as QSPI clock
+  *            @arg RCC_RCC_QSPICLKSOURCE_PLL   : PLL1_Q Clock selected as QSPI clock
+  *            @arg RCC_RCC_QSPICLKSOURCE_PLL2  : PLL2_R Clock selected as QSPI clock
+  *            @arg RCC_RCC_QSPICLKSOURCE_CLKP    CLKP selected as QSPI clock
+  */
+#define __HAL_RCC_QSPI_CONFIG(__QSPICLKSource__) \
+                  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL, (uint32_t)(__QSPICLKSource__))
+
+
+/** @brief  macro to get the QSPI clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_RCC_QSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as QSPI clock
+  *            @arg RCC_RCC_QSPICLKSOURCE_PLL   : PLL1_Q Clock selected as QSPI clock
+  *            @arg RCC_RCC_QSPICLKSOURCE_PLL2  : PLL2_R Clock selected as QSPI clock
+  *            @arg RCC_RCC_QSPICLKSOURCE_CLKP    CLKP selected as QSPI clock
+  */
+#define __HAL_RCC_GET_QSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL)))
+#endif /* QUADSPI */
+
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+/** @brief  macro to configure the OSPI clock source.
+  *
+  * @param  __OSPICLKSource__ specifies the OSPI clock source.
+  *            @arg RCC_RCC_OSPICLKSOURCE_CDHCLK: Domain1 HCLK Clock selected as OSPI clock
+  *            @arg RCC_RCC_OSPICLKSOURCE_PLL   : PLL1_Q Clock selected as OSPI clock
+  *            @arg RCC_RCC_OSPICLKSOURCE_PLL2  : PLL2_R Clock selected as OSPI clock
+  *            @arg RCC_RCC_OSPICLKSOURCE_CLKP    CLKP selected as OSPI clock
+  */
+#define __HAL_RCC_OSPI_CONFIG(__OSPICLKSource__) \
+                  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL, (uint32_t)(__OSPICLKSource__))
+
+
+/** @brief  macro to get the OSPI clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_RCC_OSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as OSPI clock
+  *            @arg RCC_RCC_OSPICLKSOURCE_PLL   : PLL1_Q Clock selected as OSPI clock
+  *            @arg RCC_RCC_OSPICLKSOURCE_PLL2  : PLL2_R Clock selected as OSPI clock
+  *            @arg RCC_RCC_OSPICLKSOURCE_CLKP    CLKP selected as OSPI clock
+  */
+#define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL)))
+#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
+
+
+#if defined(DSI)
+/** @brief  macro to configure the DSI clock source.
+  *
+  * @param  __DSICLKSource__ specifies the DSI clock source.
+  *            @arg RCC_RCC_DSICLKSOURCE_PHY:DSI clock from PHY is selected as DSI byte lane clock
+  *            @arg RCC_RCC_DSICLKSOURCE_PLL2   : PLL2_Q Clock clock is selected as DSI byte lane clock
+  */
+#define __HAL_RCC_DSI_CONFIG(__DSICLKSource__) \
+                  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL, (uint32_t)(__DSICLKSource__))
+
+
+/** @brief  macro to get the DSI clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_RCC_DSICLKSOURCE_PHY: DSI clock from PHY is selected as DSI byte lane clock
+  *            @arg RCC_RCC_DSICLKSOURCE_PLL2: PLL2_Q Clock clock is selected as DSI byte lane clock
+  */
+#define __HAL_RCC_GET_DSI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL)))
+#endif /*DSI*/
+
+/** @brief  macro to configure the FMC clock source.
+  *
+  * @param  __FMCCLKSource__ specifies the FMC clock source.
+  *            @arg RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock
+  *            @arg RCC_RCC_FMCCLKSOURCE_PLL   : PLL1_Q Clock selected as FMC clock
+  *            @arg RCC_RCC_FMCCLKSOURCE_PLL2  : PLL2_R Clock selected as FMC clock
+  *            @arg RCC_RCC_FMCCLKSOURCE_CLKP    CLKP selected as FMC clock
+  */
+#if defined(RCC_D1CCIPR_FMCSEL)
+#define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) \
+                  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__))
+#else
+#define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) \
+                  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__))
+#endif /* RCC_D1CCIPR_FMCSEL */
+
+/** @brief  macro to get the FMC clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock
+  *            @arg RCC_RCC_FMCCLKSOURCE_PLL   : PLL1_Q Clock selected as FMC clock
+  *            @arg RCC_RCC_FMCCLKSOURCE_PLL2  : PLL2_R Clock selected as FMC clock
+  *            @arg RCC_RCC_FMCCLKSOURCE_CLKP    CLKP selected as FMC clock
+  */
+#if defined(RCC_D1CCIPR_FMCSEL)
+#define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL)))
+#else
+#define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL)))
+#endif /* RCC_D1CCIPR_FMCSEL */
+
+/** @brief  Macro to configure the USB clock (USBCLK).
+  * @param  __USBCLKSource__ specifies the USB clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_USBCLKSOURCE_PLL:   PLL1Q selected as USB clock
+  *            @arg RCC_USBCLKSOURCE_PLL3:  PLL3Q Clock selected as USB clock
+  *            @arg RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock
+  */
+#if defined(RCC_D2CCIP2R_USBSEL)
+#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
+                  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, (uint32_t)(__USBCLKSource__))
+#else
+#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
+                  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL, (uint32_t)(__USBCLKSource__))
+#endif /* RCC_D2CCIP2R_USBSEL */
+
+/** @brief  Macro to get the USB clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_USBCLKSOURCE_PLL:   PLL1Q selected as USB clock
+  *            @arg RCC_USBCLKSOURCE_PLL3:  PLL3Q Clock selected as USB clock
+  *            @arg RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock
+  */
+#if defined(RCC_D2CCIP2R_USBSEL)
+#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL)))
+#else
+#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL)))
+#endif /* RCC_D2CCIP2R_USBSEL */
+
+/** @brief  Macro to configure the ADC clock
+  * @param  __ADCCLKSource__ specifies the ADC digital interface clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock
+  *            @arg RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock
+  *            @arg RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock
+  */
+#if defined(RCC_D3CCIPR_ADCSEL)
+#define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \
+                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__))
+#else
+#define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \
+                  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__))
+#endif /* RCC_D3CCIPR_ADCSEL */
+
+/** @brief  Macro to get the ADC clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock
+  *            @arg RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock
+  *            @arg RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock
+  */
+#if defined(RCC_D3CCIPR_ADCSEL)
+#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL)))
+#else
+#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL)))
+#endif /* RCC_D3CCIPR_ADCSEL */
+
+ /** @brief  Macro to configure the SWPMI1 clock
+  * @param  __SWPMI1CLKSource__ specifies the SWPMI1  clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_SWPMI1CLKSOURCE_D2PCLK1:  D2PCLK1 Clock selected as SWPMI1 clock
+  *            @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock
+  */
+#if defined(RCC_D2CCIP1R_SWPSEL)
+#define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) \
+                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__))
+#else
+#define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) \
+                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__))
+#endif /* RCC_D2CCIP1R_SWPSEL */
+
+/** @brief  Macro to get the SWPMI1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_SWPMI1CLKSOURCE_D2PCLK1:  D2PCLK1 Clock selected as SWPMI1 clock
+  *            @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock
+  */
+#if defined(RCC_D2CCIP1R_SWPSEL)
+#define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL)))
+#else
+#define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL)))
+#endif /* RCC_D2CCIP1R_SWPSEL */
+
+ /** @brief  Macro to configure the DFSDM1 clock
+  * @param  __DFSDM1CLKSource__ specifies the DFSDM1  clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_DFSDM1CLKSOURCE_D2PCLK:  D2PCLK Clock selected as DFSDM1 clock
+  *            @arg RCC_DFSDM1CLKSOURCE_SYS:     System Clock selected as DFSDM1 clock
+  */
+#if defined(RCC_D2CCIP1R_DFSDM1SEL)
+#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) \
+                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__))
+#else
+#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) \
+                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__))
+#endif /* RCC_D2CCIP1R_DFSDM1SEL */
+
+/** @brief  Macro to get the DFSDM1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_DFSDM1CLKSOURCE_D2PCLK:  D2PCLK Clock selected as DFSDM1 clock
+  *            @arg RCC_DFSDM1CLKSOURCE_SYS:   System Clock selected as DFSDM1 clock
+  */
+#if defined (RCC_D2CCIP1R_DFSDM1SEL)
+#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL)))
+#else
+#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL)))
+#endif /* RCC_D2CCIP1R_DFSDM1SEL */
+
+#if defined(DFSDM2_BASE)
+ /** @brief  Macro to configure the DFSDM2 clock
+  * @param  __DFSDM2CLKSource__ specifies the DFSDM2  clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_DFSDM2CLKSOURCE_SRDPCLK1:  SRDPCLK1 (APB4) selected as DFSDM2 clock
+  *            @arg RCC_DFSDM2CLKSOURCE_SYS:   System Clock selected as DFSDM2 clock
+  */
+#define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2CLKSource__) \
+                  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL, (uint32_t)(__DFSDM2CLKSource__))
+
+/** @brief  Macro to get the DFSDM2 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_DFSDM2CLKSOURCE_SRDPCLK1:  SRDPCLK1 (APB4) Clock selected as DFSDM2 clock
+  *            @arg RCC_DFSDM2CLKSOURCE_SYS:   System Clock selected as DFSDM2 clock
+  */
+#define __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL)))
+#endif /* DFSDM2 */
+
+/** @brief macro to configure the CEC clock (CECCLK).
+  *
+  * @param  __CECCLKSource__ specifies the CEC clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
+  *            @arg RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock
+  *            @arg RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock
+  */
+#if defined(RCC_D2CCIP2R_CECSEL)
+#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
+                  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, (uint32_t)(__CECCLKSource__))
+#else
+#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
+                  MODIFY_REG(RCC->D2CCIP2R, RCC_CDCCIP2R_CECSEL, (uint32_t)(__CECCLKSource__))
+#endif /* RCC_D2CCIP2R_CECSEL */
+
+/** @brief  macro to get the CEC clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
+  *            @arg RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock
+  *            @arg RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock
+  */
+#if defined(RCC_D2CCIP2R_CECSEL)
+#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL)))
+#else
+#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL)))
+#endif /* RCC_D2CCIP2R_CECSEL */
+
+/** @brief  Macro to configure the CLKP : Oscillator clock for peripheral
+  * @param  __CLKPSource__ specifies Oscillator clock for peripheral
+  *         This parameter can be one of the following values:
+  *            @arg RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral
+  *            @arg RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral
+  *            @arg RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral
+  */
+#if defined(RCC_D1CCIPR_CKPERSEL)
+#define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \
+                  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, (uint32_t)(__CLKPSource__))
+#else
+#define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \
+                  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL, (uint32_t)(__CLKPSource__))
+#endif /* RCC_D1CCIPR_CKPERSEL */
+
+/** @brief  Macro to get the Oscillator clock for peripheral  source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral
+  *            @arg RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral
+  *            @arg RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral
+  */
+#if defined(RCC_D1CCIPR_CKPERSEL)
+#define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL)))
+#else
+#define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL)))
+#endif /* RCC_D1CCIPR_CKPERSEL */
+
+#if defined(FDCAN1) || defined(FDCAN2)
+/** @brief  Macro to configure the FDCAN clock
+  * @param  __FDCANCLKSource__ specifies  clock source  for FDCAN
+  *         This parameter can be one of the following values:
+  *            @arg RCC_FDCANCLKSOURCE_HSE: HSE selected as FDCAN clock
+  *            @arg RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock
+  *            @arg RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock
+  */
+#if defined(RCC_D2CCIP1R_FDCANSEL)
+#define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) \
+                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__))
+#else
+#define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) \
+                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__))
+#endif /* RCC_D2CCIP1R_FDCANSEL */
+
+/** @brief  Macro to get the FDCAN clock
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_FDCANCLKSOURCE_HSE: HSE selected as FDCAN clock
+  *            @arg RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock
+  *            @arg RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock
+  */
+#if defined(RCC_D2CCIP1R_FDCANSEL)
+#define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL)))
+#else
+#define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL)))
+#endif /* RCC_D2CCIP1R_FDCANSEL */
+
+#endif /*FDCAN1 || FDCAN2*/
+
+/**
+  * @brief  Macro to Configure the SPI1/2/3 clock source.
+  * @param  __RCC_SPI123CLKSource__ defines the SPI1/2/3 clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL
+  *             @arg RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2
+  *             @arg RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3
+  *             @arg RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock  = CLKP
+  *             @arg RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock
+  * @retval None
+  */
+#if defined(RCC_D2CCIP1R_SPI123SEL)
+#define __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__ )\
+                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__))
+#else
+#define __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__ )\
+                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__))
+#endif /* RCC_D2CCIP1R_SPI123SEL */
+
+/** @brief  Macro to get the SPI1/2/3 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL
+  *             @arg RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2
+  *             @arg RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3
+  *             @arg RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock  = CLKP
+  *             @arg RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock
+  */
+#if defined(RCC_D2CCIP1R_SPI123SEL)
+#define __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL)))
+#else
+#define __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL)))
+#endif /* RCC_D2CCIP1R_SPI123SEL */
+
+/**
+  * @brief  Macro to Configure the SPI1 clock source.
+  * @param  __RCC_SPI1CLKSource__ defines the SPI1 clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL
+  *             @arg RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2
+  *             @arg RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3
+  *             @arg RCC_SPI1CLKSOURCE_CLKP: SPI1 clock  = CLKP
+  *             @arg RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock
+  * @retval None
+  */
+#define __HAL_RCC_SPI1_CONFIG  __HAL_RCC_SPI123_CONFIG
+
+/** @brief  Macro to get the SPI1 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL
+  *             @arg RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2
+  *             @arg RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3
+  *             @arg RCC_SPI1CLKSOURCE_CLKP: SPI1 clock  = CLKP
+  *             @arg RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock
+  */
+#define __HAL_RCC_GET_SPI1_SOURCE  __HAL_RCC_GET_SPI123_SOURCE
+
+/**
+  * @brief  Macro to Configure the SPI2 clock source.
+  * @param  __RCC_SPI2CLKSource__ defines the SPI2 clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL
+  *             @arg RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2
+  *             @arg RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3
+  *             @arg RCC_SPI2CLKSOURCE_CLKP: SPI2 clock  = CLKP
+  *             @arg RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock
+  * @retval None
+  */
+#define __HAL_RCC_SPI2_CONFIG  __HAL_RCC_SPI123_CONFIG
+
+/** @brief  Macro to get the SPI2 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL
+  *             @arg RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2
+  *             @arg RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3
+  *             @arg RCC_SPI2CLKSOURCE_CLKP: SPI2 clock  = CLKP
+  *             @arg RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock
+  */
+#define __HAL_RCC_GET_SPI2_SOURCE  __HAL_RCC_GET_SPI123_SOURCE
+
+/**
+  * @brief  Macro to Configure the SPI3 clock source.
+  * @param  __RCC_SPI3CLKSource__ defines the SPI3 clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL
+  *             @arg RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2
+  *             @arg RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3
+  *             @arg RCC_SPI3CLKSOURCE_CLKP: SPI3 clock  = CLKP
+  *             @arg RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock
+  * @retval None
+  */
+#define __HAL_RCC_SPI3_CONFIG  __HAL_RCC_SPI123_CONFIG
+
+/** @brief  Macro to get the SPI3 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL
+  *             @arg RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2
+  *             @arg RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3
+  *             @arg RCC_SPI3CLKSOURCE_CLKP: SPI3 clock  = CLKP
+  *             @arg RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock
+  */
+#define __HAL_RCC_GET_SPI3_SOURCE  __HAL_RCC_GET_SPI123_SOURCE
+
+/**
+  * @brief  Macro to Configure the SPI4/5 clock source.
+  * @param  __RCC_SPI45CLKSource__ defines the SPI4/5 clock source. This clock is derived
+  *         from system PCLK, PLL2, PLL3, OSC
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SPI45CLKSOURCE_D2PCLK1:SPI4/5 clock = D2PCLK1
+  *             @arg RCC_SPI45CLKSOURCE_PLL2:   SPI4/5 clock = PLL2
+  *             @arg RCC_SPI45CLKSOURCE_PLL3:   SPI4/5 clock = PLL3
+  *             @arg RCC_SPI45CLKSOURCE_HSI:    SPI4/5 clock = HSI
+  *             @arg RCC_SPI45CLKSOURCE_CSI:    SPI4/5 clock = CSI
+  *             @arg RCC_SPI45CLKSOURCE_HSE:    SPI4/5 clock = HSE
+  * @retval None
+  */
+#if defined(RCC_D2CCIP1R_SPI45SEL)
+#define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__ )\
+                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__))
+#else
+#define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__ )\
+                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__))
+#endif /* RCC_D2CCIP1R_SPI45SEL */
+
+/** @brief  Macro to get the SPI4/5 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SPI45CLKSOURCE_D2PCLK1:SPI4/5 clock = D2PCLK1
+  *             @arg RCC_SPI45CLKSOURCE_PLL2:   SPI4/5 clock = PLL2
+  *             @arg RCC_SPI45CLKSOURCE_PLL3:   SPI4/5 clock = PLL3
+  *             @arg RCC_SPI45CLKSOURCE_HSI:    SPI4/5 clock = HSI
+  *             @arg RCC_SPI45CLKSOURCE_CSI:    SPI4/5 clock = CSI
+  *             @arg RCC_SPI45CLKSOURCE_HSE:    SPI4/5 clock = HSE
+*/
+#if defined(RCC_D2CCIP1R_SPI45SEL)
+#define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL)))
+#else
+#define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL)))
+#endif /* RCC_D2CCIP1R_SPI45SEL */
+
+/**
+  * @brief  Macro to Configure the SPI4 clock source.
+  * @param  __RCC_SPI4CLKSource__ defines the SPI4 clock source. This clock is derived
+  *         from system PCLK, PLL2, PLL3, OSC
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1
+  *             @arg RCC_SPI4CLKSOURCE_PLL2:   SPI4 clock = PLL2
+  *             @arg RCC_SPI4CLKSOURCE_PLL3:   SPI4 clock = PLL3
+  *             @arg RCC_SPI4CLKSOURCE_HSI:    SPI4 clock = HSI
+  *             @arg RCC_SPI4CLKSOURCE_CSI:    SPI4 clock = CSI
+  *             @arg RCC_SPI4CLKSOURCE_HSE:    SPI4 clock = HSE
+  * @retval None
+  */
+#define __HAL_RCC_SPI4_CONFIG  __HAL_RCC_SPI45_CONFIG
+
+/** @brief  Macro to get the SPI4 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1
+  *             @arg RCC_SPI4CLKSOURCE_PLL2:   SPI4 clock = PLL2
+  *             @arg RCC_SPI4CLKSOURCE_PLL3:   SPI4 clock = PLL3
+  *             @arg RCC_SPI4CLKSOURCE_HSI:    SPI4 clock = HSI
+  *             @arg RCC_SPI4CLKSOURCE_CSI:    SPI4 clock = CSI
+  *             @arg RCC_SPI4CLKSOURCE_HSE:    SPI4 clock = HSE
+*/
+#define __HAL_RCC_GET_SPI4_SOURCE  __HAL_RCC_GET_SPI45_SOURCE
+
+/**
+  * @brief  Macro to Configure the SPI5 clock source.
+  * @param  __RCC_SPI5CLKSource__ defines the SPI5 clock source. This clock is derived
+  *         from system PCLK, PLL2, PLL3, OSC
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1
+  *             @arg RCC_SPI5CLKSOURCE_PLL2:   SPI5 clock = PLL2
+  *             @arg RCC_SPI5CLKSOURCE_PLL3:   SPI5 clock = PLL3
+  *             @arg RCC_SPI5CLKSOURCE_HSI:    SPI5 clock = HSI
+  *             @arg RCC_SPI5CLKSOURCE_CSI:    SPI5 clock = CSI
+  *             @arg RCC_SPI5CLKSOURCE_HSE:    SPI5 clock = HSE
+  * @retval None
+  */
+#define __HAL_RCC_SPI5_CONFIG  __HAL_RCC_SPI45_CONFIG
+
+/** @brief  Macro to get the SPI5 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1
+  *             @arg RCC_SPI5CLKSOURCE_PLL2:   SPI5 clock = PLL2
+  *             @arg RCC_SPI5CLKSOURCE_PLL3:   SPI5 clock = PLL3
+  *             @arg RCC_SPI5CLKSOURCE_HSI:    SPI5 clock = HSI
+  *             @arg RCC_SPI5CLKSOURCE_CSI:    SPI5 clock = CSI
+  *             @arg RCC_SPI5CLKSOURCE_HSE:    SPI5 clock = HSE
+*/
+#define __HAL_RCC_GET_SPI5_SOURCE  __HAL_RCC_GET_SPI45_SOURCE
+
+/**
+  * @brief  Macro to Configure the SPI6 clock source.
+  * @param  __RCC_SPI6CLKSource__ defines the SPI6 clock source. This clock is derived
+  *         from system PCLK, PLL2, PLL3, OSC
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1
+  *             @arg RCC_SPI6CLKSOURCE_PLL2:   SPI6 clock = PLL2
+  *             @arg RCC_SPI6CLKSOURCE_PLL3:   SPI6 clock = PLL3
+  *             @arg RCC_SPI6CLKSOURCE_HSI:    SPI6 clock = HSI
+  *             @arg RCC_SPI6CLKSOURCE_CSI:    SPI6 clock = CSI
+  *             @arg RCC_SPI6CLKSOURCE_HSE:    SPI6 clock = HSE
+  *             @arg RCC_SPI6CLKSOURCE_PIN:    SPI6 clock = I2S_CKIN (*)
+  *
+  * @retval None
+  *
+  * (*) : Available on stm32h7a3xx and stm32h7b3xx family lines.
+  *
+  */
+#if defined(RCC_D3CCIPR_SPI6SEL)
+#define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__ )\
+                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL, (__RCC_SPI6CLKSource__))
+#else
+#define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__ )\
+                  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL, (__RCC_SPI6CLKSource__))
+#endif /* RCC_D3CCIPR_SPI6SEL */
+
+/** @brief  Macro to get the SPI6 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1
+  *             @arg RCC_SPI6CLKSOURCE_PLL2:   SPI6 clock = PLL2
+  *             @arg RCC_SPI6CLKSOURCE_PLL3:   SPI6 clock = PLL3
+  *             @arg RCC_SPI6CLKSOURCE_HSI:    SPI6 clock = HSI
+  *             @arg RCC_SPI6CLKSOURCE_CSI:    SPI6 clock = CSI
+  *             @arg RCC_SPI6CLKSOURCE_HSE:    SPI6 clock = HSE
+  *                @arg RCC_SPI6CLKSOURCE_PIN:    SPI6 clock = I2S_CKIN
+*/
+#if defined(RCC_D3CCIPR_SPI6SEL)
+#define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL)))
+#else
+#define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL)))
+#endif /* RCC_D3CCIPR_SPI6SEL */
+
+/** @brief  Macro to configure the SDMMC clock
+  * @param  __SDMMCCLKSource__ specifies  clock source  for SDMMC
+  *         This parameter can be one of the following values:
+  *            @arg RCC_SDMMCCLKSOURCE_PLL:  PLLQ selected as SDMMC clock
+  *            @arg RCC_SDMMCCLKSOURCE_PLL2: PLL2R selected as SDMMC clock
+  */
+#if defined(RCC_D1CCIPR_SDMMCSEL)
+#define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) \
+                  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__))
+#else
+#define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) \
+                  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__))
+#endif /* RCC_D1CCIPR_SDMMCSEL */
+
+/** @brief  Macro to get the SDMMC clock
+  */
+#if defined(RCC_D1CCIPR_SDMMCSEL)
+#define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL)))
+#else
+#define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL)))
+#endif /* RCC_D1CCIPR_SDMMCSEL */
+
+/** @brief macro to configure the RNG clock (RNGCLK).
+  *
+  * @param  __RNGCLKSource__ specifies the RNG clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
+  *            @arg RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock
+  *            @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock
+  *            @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock
+  */
+#if defined(RCC_D2CCIP2R_RNGSEL)
+#define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \
+                  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__))
+#else
+#define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \
+                  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__))
+#endif /* RCC_D2CCIP2R_RNGSEL */
+
+/** @brief  macro to get the RNG clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
+  *            @arg RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock
+  *            @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock
+  *            @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock
+  */
+#if defined(RCC_D2CCIP2R_RNGSEL)
+#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL)))
+#else
+#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL)))
+#endif /* RCC_D2CCIP2R_RNGSEL */
+
+#if defined(HRTIM1)
+/** @defgroup RCCEx_HRTIMx_Clock_Config RCC Extended HRTIMx Clock Config
+  * @{
+  */
+/** @brief  Macro to configure the HRTIM1 prescaler clock source.
+  * @param  __HRTIM1CLKSource__ specifies the HRTIM1 prescaler clock source.
+  *         This parameter can be one of the following values:
+  *            @arg @ref RCC_HRTIM1CLK_TIMCLK    Timers  clock  selected as HRTIM1 prescaler clock
+  *            @arg @ref RCC_HRTIM1CLK_CPUCLK CPU Clock selected as HRTIM1 clock
+  */
+#define __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) \
+                  MODIFY_REG(RCC->CFGR, RCC_CFGR_HRTIMSEL, (uint32_t)(__HRTIM1CLKSource__))
+
+/** @brief  Macro to get the HRTIM1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg @ref RCC_HRTIM1CLK_TIMCLK   Timers  clock  selected as HRTIM1 prescaler clock
+  *            @arg @ref RCC_HRTIM1CLK_CPUCLK CPU Clock selected as HRTIM1 clock
+  */
+#define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HRTIMSEL)))
+#endif /* HRTIM1 */
+
+/** @brief  Macro to configure the Timers clocks prescalers
+  * @param  __PRESC__  specifies the Timers clocks prescalers selection
+  *         This parameter can be one of the following values:
+  *            @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
+  *                 equal to rcc_hclk1 if D2PPREx is corresponding to division by 1 or 2,
+  *                 else it is equal to 2 x Frcc_pclkx_d2 (default after reset)
+  *            @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
+  *                 equal to rcc_hclk1 if D2PPREx is corresponding to division by 1, 2 or 4,
+  *                 else it is equal to 4 x Frcc_pclkx_d2
+  */
+#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->CFGR &= ~(RCC_CFGR_TIMPRE);\
+                                                 RCC->CFGR |= (__PRESC__);       \
+                                                }while(0)
+
+/**
+  * @}
+  */
+    
+/**
+  * @brief Enable the RCC LSE CSS Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT()      SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Disable the RCC LSE CSS Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT()     CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Enable the RCC LSE CSS Event Line.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Disable the RCC LSE CSS Event Line.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
+
+#if defined(DUAL_CORE)
+/**
+  * @brief Enable the RCC LSE CSS Extended Interrupt Line for CM4.
+  * @retval None
+  */
+#define __HAL_RCC_C2_LSECSS_EXTI_ENABLE_IT()       SET_BIT(EXTI->C2IMR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Disable the RCC LSE CSS Extended Interrupt Line for CM4.
+  * @retval None
+  */
+#define __HAL_RCC_C2_LSECSS_EXTI_DISABLE_IT()      CLEAR_BIT(EXTI->C2IMR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Enable the RCC LSE CSS Event Line for CM4.
+  * @retval None.
+  */
+#define __HAL_RCC_C2_LSECSS_EXTI_ENABLE_EVENT()    SET_BIT(EXTI->C2EMR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Disable the RCC LSE CSS Event Line for CM4.
+  * @retval None.
+  */
+#define __HAL_RCC_C2_LSECSS_EXTI_DISABLE_EVENT()   CLEAR_BIT(EXTI->C2EMR1, RCC_EXTI_LINE_LSECSS)
+#endif /* DUAL_CORE */
+
+/**
+  * @brief  Enable the RCC LSE CSS Extended Interrupt Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE()  SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
+
+
+/**
+  * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
+
+
+/**
+  * @brief  Enable the RCC LSE CSS Extended Interrupt Rising Trigger.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE()  \
+  do {                                                      \
+    __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();             \
+    __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE();            \
+  } while(0)
+
+/**
+  * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE()  \
+  do {                                                       \
+    __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE();             \
+    __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE();            \
+  } while(0)
+
+/**
+  * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
+  * @retval EXTI RCC LSE CSS Line Status.
+  */
+#define __HAL_RCC_LSECSS_EXTI_GET_FLAG()       (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Clear the RCC LSE CSS EXTI flag.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG()     WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS)
+
+#if defined(DUAL_CORE)
+/**
+  * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not for CM4.
+  * @retval EXTI RCC LSE CSS Line Status.
+  */
+#define __HAL_RCC_C2_LSECSS_EXTI_GET_FLAG()       (READ_BIT(EXTI->C2PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Clear the RCC LSE CSS EXTI flag or not for CM4.
+  * @retval None.
+  */
+#define __HAL_RCC_C2_LSECSS_EXTI_CLEAR_FLAG()     WRITE_REG(EXTI->C2PR1, RCC_EXTI_LINE_LSECSS)
+#endif /* DUAL_CORE */
+/**
+  * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT()  SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS)
+ 
+/**
+  * @brief  Enable the specified CRS interrupts.
+  * @param  __INTERRUPT__ specifies the CRS interrupt sources to be enabled.
+  *          This parameter can be any combination of the following values:
+  *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
+  *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
+  *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
+  *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
+  * @retval None
+  */
+#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__)   SET_BIT(CRS->CR, (__INTERRUPT__))
+
+/**
+  * @brief  Disable the specified CRS interrupts.
+  * @param  __INTERRUPT__ specifies the CRS interrupt sources to be disabled.
+  *          This parameter can be any combination of the following values:
+  *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
+  *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
+  *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
+  *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
+  * @retval None
+  */
+#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__)  CLEAR_BIT(CRS->CR, (__INTERRUPT__))
+
+/** @brief  Check whether the CRS interrupt has occurred or not.
+  * @param  __INTERRUPT__ specifies the CRS interrupt source to check.
+  *         This parameter can be one of the following values:
+  *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
+  *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
+  *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
+  *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
+  * @retval The new state of __INTERRUPT__ (SET or RESET).
+  */
+#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__)  ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET)
+
+/** @brief  Clear the CRS interrupt pending bits
+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
+  *         This parameter can be any combination of the following values:
+  *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
+  *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
+  *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
+  *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
+  *              @arg @ref RCC_CRS_IT_TRIMOVF  Trimming overflow or underflow interrupt
+  *              @arg @ref RCC_CRS_IT_SYNCERR  SYNC error interrupt
+  *              @arg @ref RCC_CRS_IT_SYNCMISS  SYNC missed interrupt
+  */
+/* CRS IT Error Mask */
+#define  RCC_CRS_IT_ERROR_MASK                 ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))
+
+#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__)  do { \
+                                                 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \
+                                                 { \
+                                                   WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
+                                                 } \
+                                                 else \
+                                                 { \
+                                                   WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
+                                                 } \
+                                               } while(0)
+
+/**
+  * @brief  Check whether the specified CRS flag is set or not.
+  * @param  __FLAG__ specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *              @arg @ref RCC_CRS_FLAG_SYNCOK  SYNC event OK
+  *              @arg @ref RCC_CRS_FLAG_SYNCWARN  SYNC warning
+  *              @arg @ref RCC_CRS_FLAG_ERR  Error
+  *              @arg @ref RCC_CRS_FLAG_ESYNC  Expected SYNC
+  *              @arg @ref RCC_CRS_FLAG_TRIMOVF  Trimming overflow or underflow
+  *              @arg @ref RCC_CRS_FLAG_SYNCERR  SYNC error
+  *              @arg @ref RCC_CRS_FLAG_SYNCMISS  SYNC missed
+  * @retval The new state of _FLAG_ (TRUE or FALSE).
+  */
+#define __HAL_RCC_CRS_GET_FLAG(__FLAG__)  (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
+
+/**
+  * @brief  Clear the CRS specified FLAG.
+  * @param __FLAG__ specifies the flag to clear.
+  *          This parameter can be one of the following values:
+  *              @arg @ref RCC_CRS_FLAG_SYNCOK  SYNC event OK
+  *              @arg @ref RCC_CRS_FLAG_SYNCWARN  SYNC warning
+  *              @arg @ref RCC_CRS_FLAG_ERR  Error
+  *              @arg @ref RCC_CRS_FLAG_ESYNC  Expected SYNC
+  *              @arg @ref RCC_CRS_FLAG_TRIMOVF  Trimming overflow or underflow
+  *              @arg @ref RCC_CRS_FLAG_SYNCERR  SYNC error
+  *              @arg @ref RCC_CRS_FLAG_SYNCMISS  SYNC missed
+  * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR
+  * @retval None
+  */
+
+/* CRS Flag Error Mask */
+#define RCC_CRS_FLAG_ERROR_MASK                ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))
+
+#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__)     do { \
+                                                 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \
+                                                 { \
+                                                   WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
+                                                 } \
+                                                 else \
+                                                 { \
+                                                   WRITE_REG(CRS->ICR, (__FLAG__)); \
+                                                 } \
+                                               } while(0)
+
+ /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
+  * @{
+  */
+/**
+  * @brief  Enable the oscillator clock for frequency error counter.
+  * @note   when the CEN bit is set the CRS_CFGR register becomes write-protected.
+  * @retval None
+  */
+#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE()  SET_BIT(CRS->CR, CRS_CR_CEN)
+
+/**
+  * @brief  Disable the oscillator clock for frequency error counter.
+  * @retval None
+  */
+#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
+
+/**
+  * @brief  Enable the automatic hardware adjustment of TRIM bits.
+  * @note   When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
+  * @retval None
+  */
+#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE()     SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
+
+/**
+  * @brief  Enable or disable the automatic hardware adjustment of TRIM bits.
+  * @retval None
+  */
+#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE()    CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
+
+/**
+  * @brief  Macro to calculate reload value to be set in CRS register according to target and sync frequencies
+  * @note   The RELOAD value should be selected according to the ratio between the target frequency and the frequency
+  *             of the synchronization source after pre-scaling. It is then decreased by one in order to
+  *             reach the expected synchronization on the zero value. The formula is the following:
+  *             RELOAD = (fTARGET / fSYNC) -1
+  * @param  __FTARGET__ Target frequency (value in Hz)
+  * @param  __FSYNC__ Synchronization signal frequency (value in Hz)
+  * @retval None
+  */
+#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)  (((__FTARGET__) / (__FSYNC__)) - 1U)
+
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCCEx_Exported_Functions_Group1
+  * @{
+  */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
+uint32_t HAL_RCCEx_GetD1PCLK1Freq(void);
+uint32_t HAL_RCCEx_GetD3PCLK1Freq(void);
+uint32_t HAL_RCCEx_GetD1SysClockFreq(void);
+void     HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef* PLL1_Clocks);
+void     HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef* PLL2_Clocks);
+void     HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef* PLL3_Clocks);
+/**
+  * @}
+  */
+
+/** @addtogroup RCCEx_Exported_Functions_Group2
+  * @{
+  */
+void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk);
+void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk);
+void HAL_RCCEx_EnableLSECSS(void);
+void HAL_RCCEx_DisableLSECSS(void);
+void HAL_RCCEx_EnableLSECSS_IT(void);
+void HAL_RCCEx_LSECSS_IRQHandler(void);
+void HAL_RCCEx_LSECSS_Callback(void);
+#if defined(DUAL_CORE)
+void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx);
+#endif /*DUAL_CORE*/
+#if defined(RCC_GCR_WW1RSC)
+void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx);
+#endif /*RCC_GCR_WW1RSC*/
+/**
+  * @}
+  */
+
+
+/** @addtogroup RCCEx_Exported_Functions_Group3
+  * @{
+  */
+
+void     HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
+void     HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
+void     HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
+uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
+void     HAL_RCCEx_CRS_IRQHandler(void);
+void     HAL_RCCEx_CRS_SyncOkCallback(void);
+void     HAL_RCCEx_CRS_SyncWarnCallback(void);
+void     HAL_RCCEx_CRS_ExpectedSyncCallback(void);
+void     HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
+
+/**
+  * @}
+  */
+
+ /* Private macros ------------------------------------------------------------*/
+/** @addtogroup RCCEx_Private_Macros RCCEx Private Macros
+  * @{
+  */
+/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
+  * @{
+  */
+
+#define IS_RCC_PLL2CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL2_DIVP) || \
+                                         ((VALUE) == RCC_PLL2_DIVQ)  || \
+                                         ((VALUE) == RCC_PLL2_DIVR))
+
+#define IS_RCC_PLL3CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL3_DIVP) || \
+                                          ((VALUE) == RCC_PLL3_DIVQ) || \
+                                          ((VALUE) == RCC_PLL3_DIVR))
+
+#if defined(RCC_D2CCIP2R_USART16SEL)
+#define IS_RCC_USART16CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART16CLKSOURCE_D2PCLK2)|| \
+                                         ((SOURCE) == RCC_USART16CLKSOURCE_PLL2)   || \
+                                         ((SOURCE) == RCC_USART16CLKSOURCE_PLL3)   || \
+                                         ((SOURCE) == RCC_USART16CLKSOURCE_CSI)    || \
+                                         ((SOURCE) == RCC_USART16CLKSOURCE_LSE)    || \
+                                         ((SOURCE) == RCC_USART16CLKSOURCE_HSI))
+#else
+#define IS_RCC_USART16CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART16CLKSOURCE_D2PCLK2)|| \
+                                         ((SOURCE) == RCC_USART16CLKSOURCE_CDPCLK2)|| \
+                                         ((SOURCE) == RCC_USART16CLKSOURCE_PLL2)   || \
+                                         ((SOURCE) == RCC_USART16CLKSOURCE_PLL3)   || \
+                                         ((SOURCE) == RCC_USART16CLKSOURCE_CSI)    || \
+                                         ((SOURCE) == RCC_USART16CLKSOURCE_LSE)    || \
+                                         ((SOURCE) == RCC_USART16CLKSOURCE_HSI))
+/* alias*/
+#define IS_RCC_USART16910CLKSOURCE    IS_RCC_USART16CLKSOURCE
+#endif /* RCC_D2CCIP2R_USART16SEL */
+
+#if defined(RCC_D2CCIP2R_USART28SEL)
+#define IS_RCC_USART234578CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART234578CLKSOURCE_D2PCLK1)|| \
+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_PLL2)   || \
+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_PLL3)   || \
+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_CSI)    || \
+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_LSE)    || \
+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_HSI))
+#else
+#define IS_RCC_USART234578CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART234578CLKSOURCE_D2PCLK1)|| \
+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_CDPCLK1)|| \
+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_PLL2)   || \
+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_PLL3)   || \
+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_CSI)    || \
+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_LSE)    || \
+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_HSI))
+#endif /* RCC_D2CCIP2R_USART28SEL */
+
+#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_D2PCLK2)|| \
+                                        ((SOURCE) == RCC_USART1CLKSOURCE_PLL2)   || \
+                                        ((SOURCE) == RCC_USART1CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_USART1CLKSOURCE_CSI)    || \
+                                        ((SOURCE) == RCC_USART1CLKSOURCE_LSE)    || \
+                                        ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
+
+#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_D2PCLK1)|| \
+                                        ((SOURCE) == RCC_USART2CLKSOURCE_PLL2)   || \
+                                        ((SOURCE) == RCC_USART2CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_USART2CLKSOURCE_CSI)    || \
+                                        ((SOURCE) == RCC_USART2CLKSOURCE_LSE)    || \
+                                        ((SOURCE) == RCC_USART2CLKSOURCE_HSI))
+
+#define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_D2PCLK1)|| \
+                                        ((SOURCE) == RCC_USART3CLKSOURCE_PLL2)   || \
+                                        ((SOURCE) == RCC_USART3CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_USART3CLKSOURCE_CSI)    || \
+                                        ((SOURCE) == RCC_USART3CLKSOURCE_LSE)    || \
+                                        ((SOURCE) == RCC_USART3CLKSOURCE_HSI))
+
+#define IS_RCC_UART4CLKSOURCE(SOURCE)  (((SOURCE) == RCC_UART4CLKSOURCE_D2PCLK1) || \
+                                        ((SOURCE) == RCC_UART4CLKSOURCE_PLL2)    || \
+                                        ((SOURCE) == RCC_UART4CLKSOURCE_PLL3)    || \
+                                        ((SOURCE) == RCC_UART4CLKSOURCE_CSI)     || \
+                                        ((SOURCE) == RCC_UART4CLKSOURCE_LSE)     || \
+                                        ((SOURCE) == RCC_UART4CLKSOURCE_HSI))
+
+#define IS_RCC_UART5CLKSOURCE(SOURCE)  (((SOURCE) == RCC_UART5CLKSOURCE_D2PCLK1) || \
+                                        ((SOURCE) == RCC_UART5CLKSOURCE_PLL2)    || \
+                                        ((SOURCE) == RCC_UART5CLKSOURCE_PLL3)    || \
+                                        ((SOURCE) == RCC_UART5CLKSOURCE_CSI)     || \
+                                        ((SOURCE) == RCC_UART5CLKSOURCE_LSE)     || \
+                                        ((SOURCE) == RCC_UART5CLKSOURCE_HSI))
+
+#define IS_RCC_USART6CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART6CLKSOURCE_D2PCLK2)|| \
+                                        ((SOURCE) == RCC_USART6CLKSOURCE_PLL2)   || \
+                                        ((SOURCE) == RCC_USART6CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_USART6CLKSOURCE_CSI)    || \
+                                        ((SOURCE) == RCC_USART6CLKSOURCE_LSE)    || \
+                                        ((SOURCE) == RCC_USART6CLKSOURCE_HSI))
+
+#define IS_RCC_UART7CLKSOURCE(SOURCE)  (((SOURCE) == RCC_UART7CLKSOURCE_D2PCLK1) || \
+                                        ((SOURCE) == RCC_UART7CLKSOURCE_PLL2)    || \
+                                        ((SOURCE) == RCC_UART7CLKSOURCE_PLL3)    || \
+                                        ((SOURCE) == RCC_UART7CLKSOURCE_CSI)     || \
+                                        ((SOURCE) == RCC_UART7CLKSOURCE_LSE)     || \
+                                        ((SOURCE) == RCC_UART7CLKSOURCE_HSI))
+
+#define IS_RCC_UART8CLKSOURCE(SOURCE)  (((SOURCE) == RCC_UART8CLKSOURCE_D2PCLK1) || \
+                                        ((SOURCE) == RCC_UART8CLKSOURCE_PLL2)    || \
+                                        ((SOURCE) == RCC_UART8CLKSOURCE_PLL3)    || \
+                                        ((SOURCE) == RCC_UART8CLKSOURCE_CSI)     || \
+                                        ((SOURCE) == RCC_UART8CLKSOURCE_LSE)     || \
+                                        ((SOURCE) == RCC_UART8CLKSOURCE_HSI))
+
+#if defined(UART9)
+#define IS_RCC_UART9CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART9CLKSOURCE_D2PCLK2)|| \
+                                        ((SOURCE) == RCC_UART9CLKSOURCE_PLL2)  || \
+                                        ((SOURCE) == RCC_UART9CLKSOURCE_PLL3)  || \
+                                        ((SOURCE) == RCC_UART9CLKSOURCE_CSI)   || \
+                                        ((SOURCE) == RCC_UART9CLKSOURCE_LSE)   || \
+                                        ((SOURCE) == RCC_UART9CLKSOURCE_HSI))
+#endif
+
+#if defined(USART10)
+#define IS_RCC_USART10CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART10CLKSOURCE_D2PCLK2)|| \
+                                        ((SOURCE) == RCC_USART10CLKSOURCE_PLL2)    || \
+                                        ((SOURCE) == RCC_USART10CLKSOURCE_PLL3)    || \
+                                        ((SOURCE) == RCC_USART10CLKSOURCE_CSI)     || \
+                                        ((SOURCE) == RCC_USART10CLKSOURCE_LSE)     || \
+                                        ((SOURCE) == RCC_USART10CLKSOURCE_HSI))
+#endif
+
+#define IS_RCC_LPUART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPUART1CLKSOURCE_D3PCLK1) || \
+                                         ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL2)    || \
+                                         ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL3)    || \
+                                         ((SOURCE) == RCC_LPUART1CLKSOURCE_CSI)     || \
+                                         ((SOURCE) == RCC_LPUART1CLKSOURCE_LSE)     || \
+                                         ((SOURCE) == RCC_LPUART1CLKSOURCE_HSI))
+
+#define IS_RCC_I2C123CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C123CLKSOURCE_PLL3)   || \
+                                          ((SOURCE) == RCC_I2C123CLKSOURCE_HSI)    || \
+                                          ((SOURCE) == RCC_I2C123CLKSOURCE_D2PCLK1)|| \
+                                          ((SOURCE) == RCC_I2C123CLKSOURCE_CSI))
+
+#define IS_RCC_I2C1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C1CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_I2C1CLKSOURCE_HSI)    || \
+                                        ((SOURCE) == RCC_I2C1CLKSOURCE_D2PCLK1)|| \
+                                        ((SOURCE) == RCC_I2C1CLKSOURCE_CSI))
+
+#define IS_RCC_I2C2CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C2CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_I2C2CLKSOURCE_HSI)    || \
+                                        ((SOURCE) == RCC_I2C2CLKSOURCE_D2PCLK1)|| \
+                                        ((SOURCE) == RCC_I2C2CLKSOURCE_CSI))
+
+#define IS_RCC_I2C3CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C3CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_I2C3CLKSOURCE_HSI)    || \
+                                        ((SOURCE) == RCC_I2C3CLKSOURCE_D2PCLK1)|| \
+                                        ((SOURCE) == RCC_I2C3CLKSOURCE_CSI))
+
+#define IS_RCC_I2C4CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C4CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_I2C4CLKSOURCE_HSI)    || \
+                                        ((SOURCE) == RCC_I2C4CLKSOURCE_D3PCLK1)|| \
+                                        ((SOURCE) == RCC_I2C3CLKSOURCE_CSI))
+
+#define IS_RCC_RNGCLKSOURCE(SOURCE)    (((SOURCE) == RCC_RNGCLKSOURCE_HSI48)|| \
+                                        ((SOURCE) == RCC_RNGCLKSOURCE_PLL)  || \
+                                        ((SOURCE) == RCC_RNGCLKSOURCE_LSE)  || \
+                                        ((SOURCE) == RCC_RNGCLKSOURCE_LSI))
+
+#if defined(HRTIM1)
+#define IS_RCC_HRTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_HRTIM1CLK_TIMCLK) || \
+                                        ((SOURCE) == RCC_HRTIM1CLK_CPUCLK))
+#endif
+
+#define IS_RCC_USBCLKSOURCE(SOURCE)    (((SOURCE) == RCC_USBCLKSOURCE_PLL)  || \
+                                        ((SOURCE) == RCC_USBCLKSOURCE_PLL3) || \
+                                        ((SOURCE) == RCC_USBCLKSOURCE_HSI48))
+
+#define IS_RCC_SAI1CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SAI1CLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))
+
+#if defined(SAI3)
+#define IS_RCC_SAI23CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SAI23CLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SAI23CLKSOURCE_PIN))
+
+#define IS_RCC_SAI2CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SAI2CLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN))
+
+
+#define IS_RCC_SAI3CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SAI3CLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SAI3CLKSOURCE_PIN))
+#endif
+
+#if defined(RCC_CDCCIP1R_SAI2ASEL)
+#define IS_RCC_SAI2ACLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SAI2ACLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PIN) || \
+                ((__SOURCE__) == RCC_SAI2ACLKSOURCE_SPDIF))
+#endif
+
+#if defined(RCC_CDCCIP1R_SAI2BSEL)
+#define IS_RCC_SAI2BCLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SAI2BCLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PIN) || \
+                ((__SOURCE__) == RCC_SAI2BCLKSOURCE_SPDIF))
+#endif
+
+#define IS_RCC_SPI123CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SPI123CLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SPI123CLKSOURCE_PIN))
+
+#define IS_RCC_SPI1CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SPI1CLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SPI1CLKSOURCE_PIN))
+
+#define IS_RCC_SPI2CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SPI2CLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SPI2CLKSOURCE_PIN))
+
+#define IS_RCC_SPI3CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SPI3CLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SPI3CLKSOURCE_PIN))
+
+#define IS_RCC_SPI45CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SPI45CLKSOURCE_D2PCLK1)  || \
+                ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL2)     || \
+                ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL3)     || \
+                ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSI)      || \
+                ((__SOURCE__) == RCC_SPI45CLKSOURCE_CSI)      || \
+                ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSE))
+
+#define IS_RCC_SPI4CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SPI4CLKSOURCE_D2PCLK1)  || \
+                ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL2)     || \
+                ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL3)     || \
+                ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSI)      || \
+                ((__SOURCE__) == RCC_SPI4CLKSOURCE_CSI)      || \
+                ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSE))
+
+#define IS_RCC_SPI5CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SPI5CLKSOURCE_D2PCLK1)|| \
+                ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL2)   || \
+                ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL3)   || \
+                ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSI)    || \
+                ((__SOURCE__) == RCC_SPI5CLKSOURCE_CSI)    || \
+                ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSE))
+
+#if defined(RCC_D3CCIPR_SPI6SEL)
+#define IS_RCC_SPI6CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) || \
+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2)    || \
+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3)    || \
+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI)     || \
+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI)     || \
+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE))
+#else
+#define IS_RCC_SPI6CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) || \
+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2)    || \
+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3)    || \
+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI)     || \
+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI)     || \
+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE)     || \
+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_PIN))
+#endif /* RCC_D3CCIPR_SPI6SEL */
+
+#if defined(SAI4)
+#define IS_RCC_SAI4ACLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SAI4ACLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PIN))
+
+#define IS_RCC_SAI4BCLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SAI4BCLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PIN))
+#endif /*SAI4*/
+
+#define IS_RCC_PLL3M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))
+#define IS_RCC_PLL3N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))
+#define IS_RCC_PLL3P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
+#define IS_RCC_PLL3Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
+#define IS_RCC_PLL3R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
+
+#define IS_RCC_PLL2M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))
+#define IS_RCC_PLL2N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))
+#define IS_RCC_PLL2P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
+#define IS_RCC_PLL2Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
+#define IS_RCC_PLL2R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
+
+#define IS_RCC_PLL2RGE_VALUE(VALUE) (((VALUE) == RCC_PLL2VCIRANGE_0)  || \
+                                    ((VALUE) == RCC_PLL2VCIRANGE_1)   || \
+                                    ((VALUE) == RCC_PLL2VCIRANGE_2)   || \
+                                    ((VALUE) == RCC_PLL2VCIRANGE_3))
+
+#define IS_RCC_PLL3RGE_VALUE(VALUE) (((VALUE) == RCC_PLL3VCIRANGE_0)  || \
+                                    ((VALUE) == RCC_PLL3VCIRANGE_1)   || \
+                                    ((VALUE) == RCC_PLL3VCIRANGE_2)   || \
+                                    ((VALUE) == RCC_PLL3VCIRANGE_3))
+
+#define IS_RCC_PLL2VCO_VALUE(VALUE) (((VALUE) == RCC_PLL2VCOWIDE)  || \
+                                    ((VALUE) == RCC_PLL2VCOMEDIUM))
+
+#define IS_RCC_PLL3VCO_VALUE(VALUE) (((VALUE) == RCC_PLL3VCOWIDE)  || \
+                                    ((VALUE) == RCC_PLL3VCOMEDIUM))
+
+#define IS_RCC_PLLFRACN_VALUE(VALUE) ((VALUE) <=8191U)
+
+#define IS_RCC_LPTIM1CLK(SOURCE)       (((SOURCE) == RCC_LPTIM1CLKSOURCE_D2PCLK1)|| \
+                                        ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL2)   || \
+                                        ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)    || \
+                                        ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI)    || \
+                                        ((SOURCE) == RCC_LPTIM1CLKSOURCE_CLKP))
+
+#define IS_RCC_LPTIM2CLK(SOURCE)       (((SOURCE) == RCC_LPTIM2CLKSOURCE_D3PCLK1)|| \
+                                        ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL2)   || \
+                                        ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSE)    || \
+                                        ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSI)    || \
+                                        ((SOURCE) == RCC_LPTIM2CLKSOURCE_CLKP))
+
+#define IS_RCC_LPTIM345CLK(SOURCE)     (((SOURCE) == RCC_LPTIM345CLKSOURCE_D3PCLK1)|| \
+                                        ((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL2)   || \
+                                        ((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_LPTIM345CLKSOURCE_LSE)    || \
+                                        ((SOURCE) == RCC_LPTIM345CLKSOURCE_LSI)    || \
+                                        ((SOURCE) == RCC_LPTIM345CLKSOURCE_CLKP))
+
+#define IS_RCC_LPTIM3CLK(SOURCE)       (((SOURCE) == RCC_LPTIM3CLKSOURCE_D3PCLK1)  || \
+                                        ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL2)     || \
+                                        ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL3)     || \
+                                        ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSE)      || \
+                                        ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSI)      || \
+                                        ((SOURCE) == RCC_LPTIM3CLKSOURCE_CLKP))
+
+#if defined(LPTIM4)
+#define IS_RCC_LPTIM4CLK(SOURCE)       (((SOURCE) == RCC_LPTIM4CLKSOURCE_D3PCLK1)|| \
+                                        ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL2)   || \
+                                        ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSE)    || \
+                                        ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSI)    || \
+                                        ((SOURCE) == RCC_LPTIM4CLKSOURCE_CLKP))
+#endif /* LPTIM4*/
+
+#if defined(LPTIM5)
+#define IS_RCC_LPTIM5CLK(SOURCE)       (((SOURCE) == RCC_LPTIM5CLKSOURCE_D3PCLK1)|| \
+                                        ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL2)   || \
+                                        ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSE)    || \
+                                        ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSI)    || \
+                                        ((SOURCE) == RCC_LPTIM5CLKSOURCE_CLKP))
+#endif /*LPTIM5*/
+
+#if defined(QUADSPI)
+#define IS_RCC_QSPICLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_QSPICLKSOURCE_D1HCLK)  || \
+                ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL)     || \
+                ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL2)    || \
+                ((__SOURCE__) == RCC_QSPICLKSOURCE_CLKP))
+#endif /*QUADSPI*/
+
+#if defined(OCTOSPI1) || defined(OCTOSPI1)
+#define IS_RCC_OSPICLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_OSPICLKSOURCE_D1HCLK)  || \
+                ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL)     || \
+                ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL2)    || \
+                ((__SOURCE__) == RCC_OSPICLKSOURCE_CLKP))
+#endif /*OCTOSPI1 || OCTOSPI1*/
+
+#if defined(DSI)
+#define IS_RCC_DSICLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_DSICLKSOURCE_PHY)  || \
+                ((__SOURCE__) == RCC_DSICLKSOURCE_PLL2))
+#endif /*DSI*/
+
+#define IS_RCC_FMCCLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_FMCCLKSOURCE_D1HCLK)  || \
+                ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL)     || \
+                ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL2)    || \
+                ((__SOURCE__) == RCC_FMCCLKSOURCE_CLKP))
+
+#if defined(FDCAN1) || defined(FDCAN2)
+#define IS_RCC_FDCANCLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE)  || \
+                ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL2))
+#endif /*FDCAN1 || FDCAN2*/
+
+#define IS_RCC_SDMMC(__SOURCE__)   \
+                (((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL2))
+
+#define IS_RCC_ADCCLKSOURCE(SOURCE)    (((SOURCE) == RCC_ADCCLKSOURCE_PLL2) || \
+                                        ((SOURCE) == RCC_ADCCLKSOURCE_PLL3) || \
+                                        ((SOURCE) == RCC_ADCCLKSOURCE_CLKP))
+
+#define IS_RCC_SWPMI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SWPMI1CLKSOURCE_D2PCLK1) || \
+                                        ((SOURCE) == RCC_SWPMI1CLKSOURCE_HSI))
+
+#define IS_RCC_DFSDM1CLKSOURCE(SOURCE)  (((SOURCE) == RCC_DFSDM1CLKSOURCE_D2PCLK1) || \
+                                         ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYS))
+
+#if defined(DFSDM2_BASE)
+#define IS_RCC_DFSDM2CLKSOURCE(SOURCE)  (((SOURCE) == RCC_DFSDM2CLKSOURCE_SRDPCLK1) || \
+                                        ((SOURCE) == RCC_DFSDM2CLKSOURCE_SYS))
+#endif /*DFSDM2*/
+
+#define IS_RCC_SPDIFRXCLKSOURCE(SOURCE)(((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL)  || \
+                                        ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL2) || \
+                                        ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL3) || \
+                                        ((SOURCE) == RCC_SPDIFRXCLKSOURCE_HSI))
+
+#define IS_RCC_CECCLKSOURCE(SOURCE)  (((SOURCE) == RCC_CECCLKSOURCE_LSE) || \
+                                      ((SOURCE) == RCC_CECCLKSOURCE_LSI) || \
+                                      ((SOURCE) == RCC_CECCLKSOURCE_CSI))
+
+#define IS_RCC_CLKPSOURCE(SOURCE)   (((SOURCE) == RCC_CLKPSOURCE_HSI)  || \
+                                      ((SOURCE) == RCC_CLKPSOURCE_CSI) || \
+                                      ((SOURCE) == RCC_CLKPSOURCE_HSE))
+#define IS_RCC_TIMPRES(VALUE)  \
+               (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \
+                ((VALUE) == RCC_TIMPRES_ACTIVATED))
+
+#if defined(DUAL_CORE)
+#define IS_RCC_BOOT_CORE(CORE)   (((CORE) == RCC_BOOT_C1)  || \
+                                  ((CORE) == RCC_BOOT_C2))
+#endif /*DUAL_CORE*/
+
+#if defined(DUAL_CORE)
+#define IS_RCC_SCOPE_WWDG(WWDG)   (((WWDG) == RCC_WWDG1)  || \
+                                  ((WWDG) == RCC_WWDG2))
+#else
+#define IS_RCC_SCOPE_WWDG(WWDG)   ((WWDG) == RCC_WWDG1)
+
+#endif /*DUAL_CORE*/
+
+#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB2) || \
+                                            ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE)  || \
+                                            ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB1) || \
+                                            ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_PIN))
+
+#define IS_RCC_CRS_SYNC_DIV(__DIV__)       (((__DIV__) == RCC_CRS_SYNC_DIV1)  || ((__DIV__) == RCC_CRS_SYNC_DIV2)  || \
+                                            ((__DIV__) == RCC_CRS_SYNC_DIV4)  || ((__DIV__) == RCC_CRS_SYNC_DIV8)  || \
+                                            ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
+                                            ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))
+
+#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
+                                                ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
+
+#define IS_RCC_CRS_RELOADVALUE(__VALUE__)  (((__VALUE__) <= 0xFFFFU))
+
+#define IS_RCC_CRS_ERRORLIMIT(__VALUE__)   (((__VALUE__) <= 0xFFU))
+
+#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))
+
+#define IS_RCC_CRS_FREQERRORDIR(__DIR__)   (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
+                                            ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_RCC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h
new file mode 100644
index 00000000..37a7ada8
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h
@@ -0,0 +1,2285 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_tim.h
+  * @author  MCD Application Team
+  * @brief   Header file of TIM HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_TIM_H
+#define STM32H7xx_HAL_TIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup TIM
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TIM_Exported_Types TIM Exported Types
+  * @{
+  */
+
+/**
+  * @brief  TIM Time base Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
+                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+  uint32_t CounterMode;       /*!< Specifies the counter mode.
+                                   This parameter can be a value of @ref TIM_Counter_Mode */
+
+  uint32_t Period;            /*!< Specifies the period value to be loaded into the active
+                                   Auto-Reload Register at the next update event.
+                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.  */
+
+  uint32_t ClockDivision;     /*!< Specifies the clock division.
+                                   This parameter can be a value of @ref TIM_ClockDivision */
+
+  uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
+                                    reaches zero, an update event is generated and counting restarts
+                                    from the RCR value (N).
+                                    This means in PWM mode that (N+1) corresponds to:
+                                        - the number of PWM periods in edge-aligned mode
+                                        - the number of half PWM period in center-aligned mode
+                                     GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+                                     Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+  uint32_t AutoReloadPreload;  /*!< Specifies the auto-reload preload.
+                                   This parameter can be a value of @ref TIM_AutoReloadPreload */
+} TIM_Base_InitTypeDef;
+
+/**
+  * @brief  TIM Output Compare Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t OCMode;        /*!< Specifies the TIM mode.
+                               This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+  uint32_t OCPolarity;    /*!< Specifies the output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t OCFastMode;    /*!< Specifies the Fast mode state.
+                               This parameter can be a value of @ref TIM_Output_Fast_State
+                               @note This parameter is valid only in PWM1 and PWM2 mode. */
+
+
+  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+                               @note This parameter is valid only for timer instances supporting break feature. */
+} TIM_OC_InitTypeDef;
+
+/**
+  * @brief  TIM One Pulse Mode Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t OCMode;        /*!< Specifies the TIM mode.
+                               This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+  uint32_t OCPolarity;    /*!< Specifies the output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint32_t ICSelection;   /*!< Specifies the input.
+                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t ICFilter;      /*!< Specifies the input capture filter.
+                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_OnePulse_InitTypeDef;
+
+/**
+  * @brief  TIM Input Capture Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t  ICPolarity;  /*!< Specifies the active edge of the input signal.
+                              This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint32_t ICSelection;  /*!< Specifies the input.
+                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
+                              This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t ICFilter;     /*!< Specifies the input capture filter.
+                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_IC_InitTypeDef;
+
+/**
+  * @brief  TIM Encoder Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t EncoderMode;   /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Encoder_Mode */
+
+  uint32_t IC1Polarity;   /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
+
+  uint32_t IC1Selection;  /*!< Specifies the input.
+                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t IC1Prescaler;  /*!< Specifies the Input Capture Prescaler.
+                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t IC1Filter;     /*!< Specifies the input capture filter.
+                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+  uint32_t IC2Polarity;   /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
+
+  uint32_t IC2Selection;  /*!< Specifies the input.
+                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t IC2Prescaler;  /*!< Specifies the Input Capture Prescaler.
+                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t IC2Filter;     /*!< Specifies the input capture filter.
+                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_Encoder_InitTypeDef;
+
+/**
+  * @brief  Clock Configuration Handle Structure definition
+  */
+typedef struct
+{
+  uint32_t ClockSource;     /*!< TIM clock sources
+                                 This parameter can be a value of @ref TIM_Clock_Source */
+  uint32_t ClockPolarity;   /*!< TIM clock polarity
+                                 This parameter can be a value of @ref TIM_Clock_Polarity */
+  uint32_t ClockPrescaler;  /*!< TIM clock prescaler
+                                 This parameter can be a value of @ref TIM_Clock_Prescaler */
+  uint32_t ClockFilter;     /*!< TIM clock filter
+                                 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_ClockConfigTypeDef;
+
+/**
+  * @brief  TIM Clear Input Configuration Handle Structure definition
+  */
+typedef struct
+{
+  uint32_t ClearInputState;      /*!< TIM clear Input state
+                                      This parameter can be ENABLE or DISABLE */
+  uint32_t ClearInputSource;     /*!< TIM clear Input sources
+                                      This parameter can be a value of @ref TIM_ClearInput_Source */
+  uint32_t ClearInputPolarity;   /*!< TIM Clear Input polarity
+                                      This parameter can be a value of @ref TIM_ClearInput_Polarity */
+  uint32_t ClearInputPrescaler;  /*!< TIM Clear Input prescaler
+                                      This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */
+  uint32_t ClearInputFilter;     /*!< TIM Clear Input filter
+                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_ClearInputConfigTypeDef;
+
+/**
+  * @brief  TIM Master configuration Structure definition
+  * @note   Advanced timers provide TRGO2 internal line which is redirected
+  *         to the ADC
+  */
+typedef struct
+{
+  uint32_t  MasterOutputTrigger;   /*!< Trigger output (TRGO) selection
+                                        This parameter can be a value of @ref TIM_Master_Mode_Selection */
+  uint32_t  MasterOutputTrigger2;  /*!< Trigger output2 (TRGO2) selection
+                                        This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */
+  uint32_t  MasterSlaveMode;       /*!< Master/slave mode selection
+                                        This parameter can be a value of @ref TIM_Master_Slave_Mode
+                                        @note When the Master/slave mode is enabled, the effect of
+                                        an event on the trigger input (TRGI) is delayed to allow a
+                                        perfect synchronization between the current timer and its
+                                        slaves (through TRGO). It is not mandatory in case of timer
+                                        synchronization mode. */
+} TIM_MasterConfigTypeDef;
+
+/**
+  * @brief  TIM Slave configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t  SlaveMode;         /*!< Slave mode selection
+                                    This parameter can be a value of @ref TIM_Slave_Mode */
+  uint32_t  InputTrigger;      /*!< Input Trigger source
+                                    This parameter can be a value of @ref TIM_Trigger_Selection */
+  uint32_t  TriggerPolarity;   /*!< Input Trigger polarity
+                                    This parameter can be a value of @ref TIM_Trigger_Polarity */
+  uint32_t  TriggerPrescaler;  /*!< Input trigger prescaler
+                                    This parameter can be a value of @ref TIM_Trigger_Prescaler */
+  uint32_t  TriggerFilter;     /*!< Input trigger filter
+                                    This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF  */
+
+} TIM_SlaveConfigTypeDef;
+
+/**
+  * @brief  TIM Break input(s) and Dead time configuration Structure definition
+  * @note   2 break inputs can be configured (BKIN and BKIN2) with configurable
+  *        filter and polarity.
+  */
+typedef struct
+{
+  uint32_t OffStateRunMode;      /*!< TIM off state in run mode
+                                      This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
+  uint32_t OffStateIDLEMode;     /*!< TIM off state in IDLE mode
+                                      This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
+  uint32_t LockLevel;            /*!< TIM Lock level
+                                      This parameter can be a value of @ref TIM_Lock_level */
+  uint32_t DeadTime;             /*!< TIM dead Time
+                                      This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+  uint32_t BreakState;           /*!< TIM Break State
+                                      This parameter can be a value of @ref TIM_Break_Input_enable_disable */
+  uint32_t BreakPolarity;        /*!< TIM Break input polarity
+                                      This parameter can be a value of @ref TIM_Break_Polarity */
+  uint32_t BreakFilter;          /*!< Specifies the break input filter.
+                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+  uint32_t Break2State;          /*!< TIM Break2 State
+                                      This parameter can be a value of @ref TIM_Break2_Input_enable_disable */
+  uint32_t Break2Polarity;       /*!< TIM Break2 input polarity
+                                      This parameter can be a value of @ref TIM_Break2_Polarity */
+  uint32_t Break2Filter;         /*!< TIM break2 input filter.
+                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+  uint32_t AutomaticOutput;      /*!< TIM Automatic Output Enable state
+                                      This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+} TIM_BreakDeadTimeConfigTypeDef;
+
+/**
+  * @brief  HAL State structures definition
+  */
+typedef enum
+{
+  HAL_TIM_STATE_RESET             = 0x00U,    /*!< Peripheral not yet initialized or disabled  */
+  HAL_TIM_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */
+  HAL_TIM_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */
+  HAL_TIM_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */
+  HAL_TIM_STATE_ERROR             = 0x04U     /*!< Reception process is ongoing                */
+} HAL_TIM_StateTypeDef;
+
+/**
+  * @brief  HAL Active channel structures definition
+  */
+typedef enum
+{
+  HAL_TIM_ACTIVE_CHANNEL_1        = 0x01U,    /*!< The active channel is 1     */
+  HAL_TIM_ACTIVE_CHANNEL_2        = 0x02U,    /*!< The active channel is 2     */
+  HAL_TIM_ACTIVE_CHANNEL_3        = 0x04U,    /*!< The active channel is 3     */
+  HAL_TIM_ACTIVE_CHANNEL_4        = 0x08U,    /*!< The active channel is 4     */
+  HAL_TIM_ACTIVE_CHANNEL_5        = 0x10U,    /*!< The active channel is 5     */
+  HAL_TIM_ACTIVE_CHANNEL_6        = 0x20U,    /*!< The active channel is 6     */
+  HAL_TIM_ACTIVE_CHANNEL_CLEARED  = 0x00U     /*!< All active channels cleared */
+} HAL_TIM_ActiveChannel;
+
+/**
+  * @brief  TIM Time Base Handle Structure definition
+  */
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+typedef struct __TIM_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+{
+  TIM_TypeDef                 *Instance;     /*!< Register base address             */
+  TIM_Base_InitTypeDef        Init;          /*!< TIM Time Base required parameters */
+  HAL_TIM_ActiveChannel       Channel;       /*!< Active channel                    */
+  DMA_HandleTypeDef           *hdma[7];      /*!< DMA Handlers array
+                                                  This array is accessed by a @ref DMA_Handle_index */
+  HAL_LockTypeDef             Lock;          /*!< Locking object                    */
+  __IO HAL_TIM_StateTypeDef   State;         /*!< TIM operation state               */
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM Base Msp Init Callback                              */
+  void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);            /*!< TIM Base Msp DeInit Callback                            */
+  void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM IC Msp Init Callback                                */
+  void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM IC Msp DeInit Callback                              */
+  void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM OC Msp Init Callback                                */
+  void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM OC Msp DeInit Callback                              */
+  void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM PWM Msp Init Callback                               */
+  void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM PWM Msp DeInit Callback                             */
+  void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim);          /*!< TIM One Pulse Msp Init Callback                         */
+  void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM One Pulse Msp DeInit Callback                       */
+  void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Encoder Msp Init Callback                           */
+  void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM Encoder Msp DeInit Callback                         */
+  void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Hall Sensor Msp Init Callback                       */
+  void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);      /*!< TIM Hall Sensor Msp DeInit Callback                     */
+  void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM Period Elapsed Callback                             */
+  void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);     /*!< TIM Period Elapsed half complete Callback               */
+  void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim);                   /*!< TIM Trigger Callback                                    */
+  void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Trigger half complete Callback                      */
+  void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM Input Capture Callback                              */
+  void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Input Capture half complete Callback                */
+  void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Output Compare Delay Elapsed Callback               */
+  void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM PWM Pulse Finished Callback                         */
+  void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback           */
+  void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Error Callback                                      */
+  void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM Commutation Callback                                */
+  void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);       /*!< TIM Commutation half complete Callback                  */
+  void (* BreakCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Break Callback                                      */
+  void (* Break2Callback)(struct __TIM_HandleTypeDef *htim);                    /*!< TIM Break2 Callback                                     */
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+} TIM_HandleTypeDef;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL TIM Callback ID enumeration definition
+  */
+typedef enum
+{
+   HAL_TIM_BASE_MSPINIT_CB_ID            = 0x00U    /*!< TIM Base MspInit Callback ID                              */
+  ,HAL_TIM_BASE_MSPDEINIT_CB_ID          = 0x01U    /*!< TIM Base MspDeInit Callback ID                            */
+  ,HAL_TIM_IC_MSPINIT_CB_ID              = 0x02U    /*!< TIM IC MspInit Callback ID                                */
+  ,HAL_TIM_IC_MSPDEINIT_CB_ID            = 0x03U    /*!< TIM IC MspDeInit Callback ID                              */
+  ,HAL_TIM_OC_MSPINIT_CB_ID              = 0x04U    /*!< TIM OC MspInit Callback ID                                */
+  ,HAL_TIM_OC_MSPDEINIT_CB_ID            = 0x05U    /*!< TIM OC MspDeInit Callback ID                              */
+  ,HAL_TIM_PWM_MSPINIT_CB_ID             = 0x06U    /*!< TIM PWM MspInit Callback ID                               */
+  ,HAL_TIM_PWM_MSPDEINIT_CB_ID           = 0x07U    /*!< TIM PWM MspDeInit Callback ID                             */
+  ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID       = 0x08U    /*!< TIM One Pulse MspInit Callback ID                         */
+  ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID     = 0x09U    /*!< TIM One Pulse MspDeInit Callback ID                       */
+  ,HAL_TIM_ENCODER_MSPINIT_CB_ID         = 0x0AU    /*!< TIM Encoder MspInit Callback ID                           */
+  ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID       = 0x0BU    /*!< TIM Encoder MspDeInit Callback ID                         */
+  ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID     = 0x0CU    /*!< TIM Hall Sensor MspDeInit Callback ID                     */
+  ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID   = 0x0DU    /*!< TIM Hall Sensor MspDeInit Callback ID                     */
+  ,HAL_TIM_PERIOD_ELAPSED_CB_ID          = 0x0EU    /*!< TIM Period Elapsed Callback ID                             */
+  ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID     = 0x0FU    /*!< TIM Period Elapsed half complete Callback ID               */
+  ,HAL_TIM_TRIGGER_CB_ID                 = 0x10U    /*!< TIM Trigger Callback ID                                    */
+  ,HAL_TIM_TRIGGER_HALF_CB_ID            = 0x11U    /*!< TIM Trigger half complete Callback ID                      */
+
+  ,HAL_TIM_IC_CAPTURE_CB_ID              = 0x12U    /*!< TIM Input Capture Callback ID                              */
+  ,HAL_TIM_IC_CAPTURE_HALF_CB_ID         = 0x13U    /*!< TIM Input Capture half complete Callback ID                */
+  ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID        = 0x14U    /*!< TIM Output Compare Delay Elapsed Callback ID               */
+  ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID      = 0x15U    /*!< TIM PWM Pulse Finished Callback ID           */
+  ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U    /*!< TIM PWM Pulse Finished half complete Callback ID           */
+  ,HAL_TIM_ERROR_CB_ID                   = 0x17U    /*!< TIM Error Callback ID                                      */
+  ,HAL_TIM_COMMUTATION_CB_ID             = 0x18U    /*!< TIM Commutation Callback ID                                */
+  ,HAL_TIM_COMMUTATION_HALF_CB_ID        = 0x19U    /*!< TIM Commutation half complete Callback ID                  */
+  ,HAL_TIM_BREAK_CB_ID                   = 0x1AU    /*!< TIM Break Callback ID                                      */
+  ,HAL_TIM_BREAK2_CB_ID                  = 0x1BU    /*!< TIM Break2 Callback ID                                     */
+} HAL_TIM_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL TIM Callback pointer definition
+  */
+typedef  void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);  /*!< pointer to the TIM callback function */
+
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+/* End of exported types -----------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIM_Exported_Constants TIM Exported Constants
+  * @{
+  */
+
+/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
+  * @{
+  */
+#define TIM_CLEARINPUTSOURCE_NONE           0x00000000U   /*!< OCREF_CLR is disabled */
+#define TIM_CLEARINPUTSOURCE_ETR            0x00000001U   /*!< OCREF_CLR is connected to ETRF input */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
+  * @{
+  */
+#define TIM_DMABASE_CR1                    0x00000000U
+#define TIM_DMABASE_CR2                    0x00000001U
+#define TIM_DMABASE_SMCR                   0x00000002U
+#define TIM_DMABASE_DIER                   0x00000003U
+#define TIM_DMABASE_SR                     0x00000004U
+#define TIM_DMABASE_EGR                    0x00000005U
+#define TIM_DMABASE_CCMR1                  0x00000006U
+#define TIM_DMABASE_CCMR2                  0x00000007U
+#define TIM_DMABASE_CCER                   0x00000008U
+#define TIM_DMABASE_CNT                    0x00000009U
+#define TIM_DMABASE_PSC                    0x0000000AU
+#define TIM_DMABASE_ARR                    0x0000000BU
+#define TIM_DMABASE_RCR                    0x0000000CU
+#define TIM_DMABASE_CCR1                   0x0000000DU
+#define TIM_DMABASE_CCR2                   0x0000000EU
+#define TIM_DMABASE_CCR3                   0x0000000FU
+#define TIM_DMABASE_CCR4                   0x00000010U
+#define TIM_DMABASE_BDTR                   0x00000011U
+#define TIM_DMABASE_DCR                    0x00000012U
+#define TIM_DMABASE_DMAR                   0x00000013U
+#define TIM_DMABASE_CCMR3                  0x00000015U
+#define TIM_DMABASE_CCR5                   0x00000016U
+#define TIM_DMABASE_CCR6                   0x00000017U
+#if   defined(TIM_BREAK_INPUT_SUPPORT)
+#define TIM_DMABASE_AF1                    0x00000018U
+#define TIM_DMABASE_AF2                    0x00000019U
+#endif /* TIM_BREAK_INPUT_SUPPORT */
+#define TIM_DMABASE_TISEL                  0x0000001AU
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Event_Source TIM Event Source
+  * @{
+  */
+#define TIM_EVENTSOURCE_UPDATE              TIM_EGR_UG     /*!< Reinitialize the counter and generates an update of the registers */
+#define TIM_EVENTSOURCE_CC1                 TIM_EGR_CC1G   /*!< A capture/compare event is generated on channel 1 */
+#define TIM_EVENTSOURCE_CC2                 TIM_EGR_CC2G   /*!< A capture/compare event is generated on channel 2 */
+#define TIM_EVENTSOURCE_CC3                 TIM_EGR_CC3G   /*!< A capture/compare event is generated on channel 3 */
+#define TIM_EVENTSOURCE_CC4                 TIM_EGR_CC4G   /*!< A capture/compare event is generated on channel 4 */
+#define TIM_EVENTSOURCE_COM                 TIM_EGR_COMG   /*!< A commutation event is generated */
+#define TIM_EVENTSOURCE_TRIGGER             TIM_EGR_TG     /*!< A trigger event is generated */
+#define TIM_EVENTSOURCE_BREAK               TIM_EGR_BG     /*!< A break event is generated */
+#define TIM_EVENTSOURCE_BREAK2              TIM_EGR_B2G    /*!< A break 2 event is generated */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
+  * @{
+  */
+#define  TIM_INPUTCHANNELPOLARITY_RISING      0x00000000U                       /*!< Polarity for TIx source */
+#define  TIM_INPUTCHANNELPOLARITY_FALLING     TIM_CCER_CC1P                     /*!< Polarity for TIx source */
+#define  TIM_INPUTCHANNELPOLARITY_BOTHEDGE    (TIM_CCER_CC1P | TIM_CCER_CC1NP)  /*!< Polarity for TIx source */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
+  * @{
+  */
+#define TIM_ETRPOLARITY_INVERTED              TIM_SMCR_ETP                      /*!< Polarity for ETR source */
+#define TIM_ETRPOLARITY_NONINVERTED           0x00000000U                       /*!< Polarity for ETR source */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
+  * @{
+  */
+#define TIM_ETRPRESCALER_DIV1                 0x00000000U                       /*!< No prescaler is used */
+#define TIM_ETRPRESCALER_DIV2                 TIM_SMCR_ETPS_0                   /*!< ETR input source is divided by 2 */
+#define TIM_ETRPRESCALER_DIV4                 TIM_SMCR_ETPS_1                   /*!< ETR input source is divided by 4 */
+#define TIM_ETRPRESCALER_DIV8                 TIM_SMCR_ETPS                     /*!< ETR input source is divided by 8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Counter_Mode TIM Counter Mode
+  * @{
+  */
+#define TIM_COUNTERMODE_UP                 0x00000000U                          /*!< Counter used as up-counter   */
+#define TIM_COUNTERMODE_DOWN               TIM_CR1_DIR                          /*!< Counter used as down-counter */
+#define TIM_COUNTERMODE_CENTERALIGNED1     TIM_CR1_CMS_0                        /*!< Center-aligned mode 1        */
+#define TIM_COUNTERMODE_CENTERALIGNED2     TIM_CR1_CMS_1                        /*!< Center-aligned mode 2        */
+#define TIM_COUNTERMODE_CENTERALIGNED3     TIM_CR1_CMS                          /*!< Center-aligned mode 3        */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap
+  * @{
+  */
+#define TIM_UIFREMAP_DISABLE               0x00000000U                          /*!< Update interrupt flag remap disabled */
+#define TIM_UIFREMAP_ENABLE                TIM_CR1_UIFREMAP                     /*!< Update interrupt flag remap enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ClockDivision TIM Clock Division
+  * @{
+  */
+#define TIM_CLOCKDIVISION_DIV1             0x00000000U                          /*!< Clock division: tDTS=tCK_INT   */
+#define TIM_CLOCKDIVISION_DIV2             TIM_CR1_CKD_0                        /*!< Clock division: tDTS=2*tCK_INT */
+#define TIM_CLOCKDIVISION_DIV4             TIM_CR1_CKD_1                        /*!< Clock division: tDTS=4*tCK_INT */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_State TIM Output Compare State
+  * @{
+  */
+#define TIM_OUTPUTSTATE_DISABLE            0x00000000U                          /*!< Capture/Compare 1 output disabled */
+#define TIM_OUTPUTSTATE_ENABLE             TIM_CCER_CC1E                        /*!< Capture/Compare 1 output enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
+  * @{
+  */
+#define TIM_AUTORELOAD_PRELOAD_DISABLE                0x00000000U               /*!< TIMx_ARR register is not buffered */
+#define TIM_AUTORELOAD_PRELOAD_ENABLE                 TIM_CR1_ARPE              /*!< TIMx_ARR register is buffered */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Fast_State TIM Output Fast State
+  * @{
+  */
+#define TIM_OCFAST_DISABLE                 0x00000000U                          /*!< Output Compare fast disable */
+#define TIM_OCFAST_ENABLE                  TIM_CCMR1_OC1FE                      /*!< Output Compare fast enable  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
+  * @{
+  */
+#define TIM_OUTPUTNSTATE_DISABLE           0x00000000U                          /*!< OCxN is disabled  */
+#define TIM_OUTPUTNSTATE_ENABLE            TIM_CCER_CC1NE                       /*!< OCxN is enabled   */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
+  * @{
+  */
+#define TIM_OCPOLARITY_HIGH                0x00000000U                          /*!< Capture/Compare output polarity  */
+#define TIM_OCPOLARITY_LOW                 TIM_CCER_CC1P                        /*!< Capture/Compare output polarity  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
+  * @{
+  */
+#define TIM_OCNPOLARITY_HIGH               0x00000000U                          /*!< Capture/Compare complementary output polarity */
+#define TIM_OCNPOLARITY_LOW                TIM_CCER_CC1NP                       /*!< Capture/Compare complementary output polarity */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
+  * @{
+  */
+#define TIM_OCIDLESTATE_SET                TIM_CR2_OIS1                         /*!< Output Idle state: OCx=1 when MOE=0 */
+#define TIM_OCIDLESTATE_RESET              0x00000000U                          /*!< Output Idle state: OCx=0 when MOE=0 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
+  * @{
+  */
+#define TIM_OCNIDLESTATE_SET               TIM_CR2_OIS1N                        /*!< Complementary output Idle state: OCxN=1 when MOE=0 */
+#define TIM_OCNIDLESTATE_RESET             0x00000000U                          /*!< Complementary output Idle state: OCxN=0 when MOE=0 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
+  * @{
+  */
+#define  TIM_ICPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING      /*!< Capture triggered by rising edge on timer input                  */
+#define  TIM_ICPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Capture triggered by falling edge on timer input                 */
+#define  TIM_ICPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE    /*!< Capture triggered by both rising and falling edges on timer input*/
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
+  * @{
+  */
+#define  TIM_ENCODERINPUTPOLARITY_RISING   TIM_INPUTCHANNELPOLARITY_RISING      /*!< Encoder input with rising edge polarity  */
+#define  TIM_ENCODERINPUTPOLARITY_FALLING  TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Encoder input with falling edge polarity */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
+  * @{
+  */
+#define TIM_ICSELECTION_DIRECTTI           TIM_CCMR1_CC1S_0                     /*!< TIM Input 1, 2, 3 or 4 is selected to be
+                                                                                     connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSELECTION_INDIRECTTI         TIM_CCMR1_CC1S_1                     /*!< TIM Input 1, 2, 3 or 4 is selected to be
+                                                                                     connected to IC2, IC1, IC4 or IC3, respectively */
+#define TIM_ICSELECTION_TRC                TIM_CCMR1_CC1S                       /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
+  * @{
+  */
+#define TIM_ICPSC_DIV1                     0x00000000U                          /*!< Capture performed each time an edge is detected on the capture input */
+#define TIM_ICPSC_DIV2                     TIM_CCMR1_IC1PSC_0                   /*!< Capture performed once every 2 events                                */
+#define TIM_ICPSC_DIV4                     TIM_CCMR1_IC1PSC_1                   /*!< Capture performed once every 4 events                                */
+#define TIM_ICPSC_DIV8                     TIM_CCMR1_IC1PSC                     /*!< Capture performed once every 8 events                                */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
+  * @{
+  */
+#define TIM_OPMODE_SINGLE                  TIM_CR1_OPM                          /*!< Counter stops counting at the next update event */
+#define TIM_OPMODE_REPETITIVE              0x00000000U                          /*!< Counter is not stopped at update event          */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
+  * @{
+  */
+#define TIM_ENCODERMODE_TI1                      TIM_SMCR_SMS_0                                                      /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level  */
+#define TIM_ENCODERMODE_TI2                      TIM_SMCR_SMS_1                                                      /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */
+#define TIM_ENCODERMODE_TI12                     (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                                   /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
+  * @{
+  */
+#define TIM_IT_UPDATE                      TIM_DIER_UIE                         /*!< Update interrupt            */
+#define TIM_IT_CC1                         TIM_DIER_CC1IE                       /*!< Capture/Compare 1 interrupt */
+#define TIM_IT_CC2                         TIM_DIER_CC2IE                       /*!< Capture/Compare 2 interrupt */
+#define TIM_IT_CC3                         TIM_DIER_CC3IE                       /*!< Capture/Compare 3 interrupt */
+#define TIM_IT_CC4                         TIM_DIER_CC4IE                       /*!< Capture/Compare 4 interrupt */
+#define TIM_IT_COM                         TIM_DIER_COMIE                       /*!< Commutation interrupt       */
+#define TIM_IT_TRIGGER                     TIM_DIER_TIE                         /*!< Trigger interrupt           */
+#define TIM_IT_BREAK                       TIM_DIER_BIE                         /*!< Break interrupt             */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Commutation_Source  TIM Commutation Source
+  * @{
+  */
+#define TIM_COMMUTATION_TRGI              TIM_CR2_CCUS                          /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */
+#define TIM_COMMUTATION_SOFTWARE          0x00000000U                           /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_DMA_sources TIM DMA Sources
+  * @{
+  */
+#define TIM_DMA_UPDATE                     TIM_DIER_UDE                         /*!< DMA request is triggered by the update event */
+#define TIM_DMA_CC1                        TIM_DIER_CC1DE                       /*!< DMA request is triggered by the capture/compare macth 1 event */
+#define TIM_DMA_CC2                        TIM_DIER_CC2DE                       /*!< DMA request is triggered by the capture/compare macth 2 event event */
+#define TIM_DMA_CC3                        TIM_DIER_CC3DE                       /*!< DMA request is triggered by the capture/compare macth 3 event event */
+#define TIM_DMA_CC4                        TIM_DIER_CC4DE                       /*!< DMA request is triggered by the capture/compare macth 4 event event */
+#define TIM_DMA_COM                        TIM_DIER_COMDE                       /*!< DMA request is triggered by the commutation event */
+#define TIM_DMA_TRIGGER                    TIM_DIER_TDE                         /*!< DMA request is triggered by the trigger event */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Flag_definition TIM Flag Definition
+  * @{
+  */
+#define TIM_FLAG_UPDATE                    TIM_SR_UIF                           /*!< Update interrupt flag         */
+#define TIM_FLAG_CC1                       TIM_SR_CC1IF                         /*!< Capture/Compare 1 interrupt flag */
+#define TIM_FLAG_CC2                       TIM_SR_CC2IF                         /*!< Capture/Compare 2 interrupt flag */
+#define TIM_FLAG_CC3                       TIM_SR_CC3IF                         /*!< Capture/Compare 3 interrupt flag */
+#define TIM_FLAG_CC4                       TIM_SR_CC4IF                         /*!< Capture/Compare 4 interrupt flag */
+#define TIM_FLAG_CC5                       TIM_SR_CC5IF                         /*!< Capture/Compare 5 interrupt flag */
+#define TIM_FLAG_CC6                       TIM_SR_CC6IF                         /*!< Capture/Compare 6 interrupt flag */
+#define TIM_FLAG_COM                       TIM_SR_COMIF                         /*!< Commutation interrupt flag    */
+#define TIM_FLAG_TRIGGER                   TIM_SR_TIF                           /*!< Trigger interrupt flag        */
+#define TIM_FLAG_BREAK                     TIM_SR_BIF                           /*!< Break interrupt flag          */
+#define TIM_FLAG_BREAK2                    TIM_SR_B2IF                          /*!< Break 2 interrupt flag        */
+#define TIM_FLAG_SYSTEM_BREAK              TIM_SR_SBIF                          /*!< System Break interrupt flag   */
+#define TIM_FLAG_CC1OF                     TIM_SR_CC1OF                         /*!< Capture 1 overcapture flag    */
+#define TIM_FLAG_CC2OF                     TIM_SR_CC2OF                         /*!< Capture 2 overcapture flag    */
+#define TIM_FLAG_CC3OF                     TIM_SR_CC3OF                         /*!< Capture 3 overcapture flag    */
+#define TIM_FLAG_CC4OF                     TIM_SR_CC4OF                         /*!< Capture 4 overcapture flag    */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Channel TIM Channel
+  * @{
+  */
+#define TIM_CHANNEL_1                      0x00000000U                          /*!< Capture/compare channel 1 identifier      */
+#define TIM_CHANNEL_2                      0x00000004U                          /*!< Capture/compare channel 2 identifier      */
+#define TIM_CHANNEL_3                      0x00000008U                          /*!< Capture/compare channel 3 identifier      */
+#define TIM_CHANNEL_4                      0x0000000CU                          /*!< Capture/compare channel 4 identifier      */
+#define TIM_CHANNEL_5                      0x00000010U                          /*!< Compare channel 5 identifier              */
+#define TIM_CHANNEL_6                      0x00000014U                          /*!< Compare channel 6 identifier              */
+#define TIM_CHANNEL_ALL                    0x0000003CU                          /*!< Global Capture/compare channel identifier  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Clock_Source TIM Clock Source
+  * @{
+  */
+#define TIM_CLOCKSOURCE_ETRMODE2    TIM_SMCR_ETPS_1      /*!< External clock source mode 2                          */
+#define TIM_CLOCKSOURCE_INTERNAL    TIM_SMCR_ETPS_0      /*!< Internal clock source                                 */
+#define TIM_CLOCKSOURCE_ITR0        TIM_TS_ITR0          /*!< External clock source mode 1 (ITR0)                   */
+#define TIM_CLOCKSOURCE_ITR1        TIM_TS_ITR1          /*!< External clock source mode 1 (ITR1)                   */
+#define TIM_CLOCKSOURCE_ITR2        TIM_TS_ITR2          /*!< External clock source mode 1 (ITR2)                   */
+#define TIM_CLOCKSOURCE_ITR3        TIM_TS_ITR3          /*!< External clock source mode 1 (ITR3)                   */
+#define TIM_CLOCKSOURCE_TI1ED       TIM_TS_TI1F_ED       /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
+#define TIM_CLOCKSOURCE_TI1         TIM_TS_TI1FP1        /*!< External clock source mode 1 (TTI1FP1)                */
+#define TIM_CLOCKSOURCE_TI2         TIM_TS_TI2FP2        /*!< External clock source mode 1 (TTI2FP2)                */
+#define TIM_CLOCKSOURCE_ETRMODE1    TIM_TS_ETRF          /*!< External clock source mode 1 (ETRF)                   */
+#define TIM_CLOCKSOURCE_ITR4        TIM_TS_ITR4          /*!< External clock source mode 1 (ITR4)                   */
+#define TIM_CLOCKSOURCE_ITR5        TIM_TS_ITR5          /*!< External clock source mode 1 (ITR5)                   */
+#define TIM_CLOCKSOURCE_ITR6        TIM_TS_ITR6          /*!< External clock source mode 1 (ITR6)                   */
+#define TIM_CLOCKSOURCE_ITR7        TIM_TS_ITR7          /*!< External clock source mode 1 (ITR7)                   */
+#define TIM_CLOCKSOURCE_ITR8        TIM_TS_ITR8          /*!< External clock source mode 1 (ITR8)                   */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
+  * @{
+  */
+#define TIM_CLOCKPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED           /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED        /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING    /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING   /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE  /*!< Polarity for TIx clock sources */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
+  * @{
+  */
+#define TIM_CLOCKPRESCALER_DIV1                 TIM_ETRPRESCALER_DIV1           /*!< No prescaler is used                                                     */
+#define TIM_CLOCKPRESCALER_DIV2                 TIM_ETRPRESCALER_DIV2           /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
+#define TIM_CLOCKPRESCALER_DIV4                 TIM_ETRPRESCALER_DIV4           /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
+#define TIM_CLOCKPRESCALER_DIV8                 TIM_ETRPRESCALER_DIV8           /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
+  * @{
+  */
+#define TIM_CLEARINPUTPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED      /*!< Polarity for ETRx pin */
+#define TIM_CLEARINPUTPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED   /*!< Polarity for ETRx pin */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
+  * @{
+  */
+#define TIM_CLEARINPUTPRESCALER_DIV1              TIM_ETRPRESCALER_DIV1         /*!< No prescaler is used                                                   */
+#define TIM_CLEARINPUTPRESCALER_DIV2              TIM_ETRPRESCALER_DIV2         /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV4              TIM_ETRPRESCALER_DIV4         /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV8              TIM_ETRPRESCALER_DIV8         /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
+  * @{
+  */
+#define TIM_OSSR_ENABLE                          TIM_BDTR_OSSR                  /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer)           */
+#define TIM_OSSR_DISABLE                         0x00000000U                    /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
+  * @{
+  */
+#define TIM_OSSI_ENABLE                          TIM_BDTR_OSSI                  /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer)           */
+#define TIM_OSSI_DISABLE                         0x00000000U                    /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
+/**
+  * @}
+  */
+/** @defgroup TIM_Lock_level  TIM Lock level
+  * @{
+  */
+#define TIM_LOCKLEVEL_OFF                  0x00000000U                          /*!< LOCK OFF     */
+#define TIM_LOCKLEVEL_1                    TIM_BDTR_LOCK_0                      /*!< LOCK Level 1 */
+#define TIM_LOCKLEVEL_2                    TIM_BDTR_LOCK_1                      /*!< LOCK Level 2 */
+#define TIM_LOCKLEVEL_3                    TIM_BDTR_LOCK                        /*!< LOCK Level 3 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
+  * @{
+  */
+#define TIM_BREAK_ENABLE                   TIM_BDTR_BKE                         /*!< Break input BRK is enabled  */
+#define TIM_BREAK_DISABLE                  0x00000000U                          /*!< Break input BRK is disabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
+  * @{
+  */
+#define TIM_BREAKPOLARITY_LOW              0x00000000U                          /*!< Break input BRK is active low  */
+#define TIM_BREAKPOLARITY_HIGH             TIM_BDTR_BKP                         /*!< Break input BRK is active high */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable
+  * @{
+  */
+#define TIM_BREAK2_DISABLE                 0x00000000U                          /*!< Break input BRK2 is disabled  */
+#define TIM_BREAK2_ENABLE                  TIM_BDTR_BK2E                        /*!< Break input BRK2 is enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity
+  * @{
+  */
+#define TIM_BREAK2POLARITY_LOW             0x00000000U                          /*!< Break input BRK2 is active low   */
+#define TIM_BREAK2POLARITY_HIGH            TIM_BDTR_BK2P                        /*!< Break input BRK2 is active high  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
+  * @{
+  */
+#define TIM_AUTOMATICOUTPUT_DISABLE        0x00000000U                          /*!< MOE can be set only by software */
+#define TIM_AUTOMATICOUTPUT_ENABLE         TIM_BDTR_AOE                         /*!< MOE can be set by software or automatically at the next update event 
+                                                                                    (if none of the break inputs BRK and BRK2 is active) */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3
+  * @{
+  */
+#define TIM_GROUPCH5_NONE                  0x00000000U                          /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
+#define TIM_GROUPCH5_OC1REFC               TIM_CCR5_GC5C1                       /* !< OC1REFC is the logical AND of OC1REFC and OC5REF    */
+#define TIM_GROUPCH5_OC2REFC               TIM_CCR5_GC5C2                       /* !< OC2REFC is the logical AND of OC2REFC and OC5REF    */
+#define TIM_GROUPCH5_OC3REFC               TIM_CCR5_GC5C3                       /* !< OC3REFC is the logical AND of OC3REFC and OC5REF    */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
+  * @{
+  */
+#define TIM_TRGO_RESET            0x00000000U                                      /*!< TIMx_EGR.UG bit is used as trigger output (TRGO)              */
+#define TIM_TRGO_ENABLE           TIM_CR2_MMS_0                                    /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO)             */
+#define TIM_TRGO_UPDATE           TIM_CR2_MMS_1                                    /*!< Update event is used as trigger output (TRGO)                 */
+#define TIM_TRGO_OC1              (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                  /*!< Capture or a compare match 1 is used as trigger output (TRGO) */
+#define TIM_TRGO_OC1REF           TIM_CR2_MMS_2                                    /*!< OC1REF signal is used as trigger output (TRGO)                */
+#define TIM_TRGO_OC2REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                  /*!< OC2REF signal is used as trigger output(TRGO)                 */
+#define TIM_TRGO_OC3REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                  /*!< OC3REF signal is used as trigger output(TRGO)                 */
+#define TIM_TRGO_OC4REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)  /*!< OC4REF signal is used as trigger output(TRGO)                 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2)
+  * @{
+  */
+#define TIM_TRGO2_RESET                          0x00000000U                                                         /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2)              */
+#define TIM_TRGO2_ENABLE                         TIM_CR2_MMS2_0                                                      /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2)             */
+#define TIM_TRGO2_UPDATE                         TIM_CR2_MMS2_1                                                      /*!< Update event is used as trigger output (TRGO2)                 */
+#define TIM_TRGO2_OC1                            (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                                   /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */
+#define TIM_TRGO2_OC1REF                         TIM_CR2_MMS2_2                                                      /*!< OC1REF signal is used as trigger output (TRGO2)                */
+#define TIM_TRGO2_OC2REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                                   /*!< OC2REF signal is used as trigger output (TRGO2)                */
+#define TIM_TRGO2_OC3REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)                                   /*!< OC3REF signal is used as trigger output (TRGO2)                */
+#define TIM_TRGO2_OC4REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC4REF signal is used as trigger output (TRGO2)                */
+#define TIM_TRGO2_OC5REF                         TIM_CR2_MMS2_3                                                      /*!< OC5REF signal is used as trigger output (TRGO2)                */
+#define TIM_TRGO2_OC6REF                         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)                                   /*!< OC6REF signal is used as trigger output (TRGO2)                */
+#define TIM_TRGO2_OC4REF_RISINGFALLING           (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)                                   /*!< OC4REF rising or falling edges generate pulses on TRGO2        */
+#define TIM_TRGO2_OC6REF_RISINGFALLING           (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC6REF rising or falling edges generate pulses on TRGO2        */
+#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)                                   /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2         */
+#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING   (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                  /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */
+#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)                   /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2         */
+#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING   (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2         */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
+  * @{
+  */
+#define TIM_MASTERSLAVEMODE_ENABLE         TIM_SMCR_MSM                         /*!< No action */
+#define TIM_MASTERSLAVEMODE_DISABLE        0x00000000U                          /*!< Master/slave mode is selected */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Slave_Mode TIM Slave mode
+  * @{
+  */
+#define TIM_SLAVEMODE_DISABLE                0x00000000U                                        /*!< Slave mode disabled           */
+#define TIM_SLAVEMODE_RESET                  TIM_SMCR_SMS_2                                     /*!< Reset Mode                    */
+#define TIM_SLAVEMODE_GATED                  (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)                  /*!< Gated Mode                    */
+#define TIM_SLAVEMODE_TRIGGER                (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)                  /*!< Trigger Mode                  */
+#define TIM_SLAVEMODE_EXTERNAL1              (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1         */
+#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER  TIM_SMCR_SMS_3                                     /*!< Combined reset + trigger mode */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
+  * @{
+  */
+#define TIM_OCMODE_TIMING                   0x00000000U                                              /*!< Frozen                                 */
+#define TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!< Set channel to active level on match   */
+#define TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!< Set channel to inactive level on match */
+#define TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!< Toggle                                 */
+#define TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!< PWM mode 1                             */
+#define TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2                             */
+#define TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!< Force active level                     */
+#define TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                         /*!< Force inactive level                   */
+#define TIM_OCMODE_RETRIGERRABLE_OPM1      TIM_CCMR1_OC1M_3                                          /*!< Retrigerrable OPM mode 1               */
+#define TIM_OCMODE_RETRIGERRABLE_OPM2      (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)                     /*!< Retrigerrable OPM mode 2               */
+#define TIM_OCMODE_COMBINED_PWM1           (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)                     /*!< Combined PWM mode 1                    */
+#define TIM_OCMODE_COMBINED_PWM2           (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)  /*!< Combined PWM mode 2                    */
+#define TIM_OCMODE_ASSYMETRIC_PWM1         (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)  /*!< Asymmetric PWM mode 1                  */
+#define TIM_OCMODE_ASSYMETRIC_PWM2         TIM_CCMR1_OC1M                                            /*!< Asymmetric PWM mode 2                  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
+  * @{
+  */
+#define TIM_TS_ITR0          0x00000000U                                                       /*!< Internal Trigger 0 (ITR0)              */
+#define TIM_TS_ITR1          TIM_SMCR_TS_0                                                     /*!< Internal Trigger 1 (ITR1)              */
+#define TIM_TS_ITR2          TIM_SMCR_TS_1                                                     /*!< Internal Trigger 2 (ITR2)              */
+#define TIM_TS_ITR3          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                   /*!< Internal Trigger 3 (ITR3)              */
+#define TIM_TS_TI1F_ED       TIM_SMCR_TS_2                                                     /*!< TI1 Edge Detector (TI1F_ED)            */
+#define TIM_TS_TI1FP1        (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 1 (TI1FP1)        */
+#define TIM_TS_TI2FP2        (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 2 (TI2FP2)        */
+#define TIM_TS_ETRF          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                   /*!< Filtered External Trigger input (ETRF) */
+#define TIM_TS_ITR4          (TIM_SMCR_TS_3)                                                   /*!< Internal Trigger 4 (ITR4)              */
+#define TIM_TS_ITR5          (TIM_SMCR_TS_0 | TIM_SMCR_TS_3)                                   /*!< Internal Trigger 5 (ITR5)              */
+#define TIM_TS_ITR6          (TIM_SMCR_TS_1 | TIM_SMCR_TS_3)                                   /*!< Internal Trigger 6 (ITR6)              */
+#define TIM_TS_ITR7          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3)                   /*!< Internal Trigger 7 (ITR7)              */
+#define TIM_TS_ITR8          (TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                                   /*!< Internal Trigger 8 (ITR8)              */
+#define TIM_TS_ITR9          (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                   /*!< Internal Trigger 9 (ITR9)              */
+#define TIM_TS_ITR10         (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                   /*!< Internal Trigger 10 (ITR10)            */
+#define TIM_TS_ITR11         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)   /*!< Internal Trigger 11 (ITR11)            */
+#define TIM_TS_ITR12         (TIM_SMCR_TS_4)                                                   /*!< Internal Trigger 12 (ITR12)            */
+#define TIM_TS_ITR13         (TIM_SMCR_TS_0 | TIM_SMCR_TS_4)                                   /*!< Internal Trigger 13 (ITR13)            */
+#define TIM_TS_NONE          0x0000FFFFU                                                       /*!< No trigger selected                    */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
+  * @{
+  */
+#define TIM_TRIGGERPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED               /*!< Polarity for ETRx trigger sources             */
+#define TIM_TRIGGERPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED            /*!< Polarity for ETRx trigger sources             */
+#define TIM_TRIGGERPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING        /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING       /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE      /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
+  * @{
+  */
+#define TIM_TRIGGERPRESCALER_DIV1             TIM_ETRPRESCALER_DIV1             /*!< No prescaler is used                                                       */
+#define TIM_TRIGGERPRESCALER_DIV2             TIM_ETRPRESCALER_DIV2             /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
+#define TIM_TRIGGERPRESCALER_DIV4             TIM_ETRPRESCALER_DIV4             /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
+#define TIM_TRIGGERPRESCALER_DIV8             TIM_ETRPRESCALER_DIV8             /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
+  * @{
+  */
+#define TIM_TI1SELECTION_CH1               0x00000000U                          /*!< The TIMx_CH1 pin is connected to TI1 input */
+#define TIM_TI1SELECTION_XORCOMBINATION    TIM_CR2_TI1S                         /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
+  * @{
+  */
+#define TIM_DMABURSTLENGTH_1TRANSFER       0x00000000U                          /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA   */
+#define TIM_DMABURSTLENGTH_2TRANSFERS      0x00000100U                          /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_3TRANSFERS      0x00000200U                          /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_4TRANSFERS      0x00000300U                          /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_5TRANSFERS      0x00000400U                          /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_6TRANSFERS      0x00000500U                          /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_7TRANSFERS      0x00000600U                          /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_8TRANSFERS      0x00000700U                          /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_9TRANSFERS      0x00000800U                          /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_10TRANSFERS     0x00000900U                          /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_11TRANSFERS     0x00000A00U                          /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_12TRANSFERS     0x00000B00U                          /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_13TRANSFERS     0x00000C00U                          /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_14TRANSFERS     0x00000D00U                          /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_15TRANSFERS     0x00000E00U                          /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_16TRANSFERS     0x00000F00U                          /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_17TRANSFERS     0x00001000U                          /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_18TRANSFERS     0x00001100U                          /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Handle_index TIM DMA Handle Index
+  * @{
+  */
+#define TIM_DMA_ID_UPDATE                ((uint16_t) 0x0000)       /*!< Index of the DMA handle used for Update DMA requests */
+#define TIM_DMA_ID_CC1                   ((uint16_t) 0x0001)       /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
+#define TIM_DMA_ID_CC2                   ((uint16_t) 0x0002)       /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
+#define TIM_DMA_ID_CC3                   ((uint16_t) 0x0003)       /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
+#define TIM_DMA_ID_CC4                   ((uint16_t) 0x0004)       /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
+#define TIM_DMA_ID_COMMUTATION           ((uint16_t) 0x0005)       /*!< Index of the DMA handle used for Commutation DMA requests */
+#define TIM_DMA_ID_TRIGGER               ((uint16_t) 0x0006)       /*!< Index of the DMA handle used for Trigger DMA requests */
+/**
+  * @}
+  */
+
+/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
+  * @{
+  */
+#define TIM_CCx_ENABLE                   0x00000001U                            /*!< Input or output channel is enabled */
+#define TIM_CCx_DISABLE                  0x00000000U                            /*!< Input or output channel is disabled */
+#define TIM_CCxN_ENABLE                  0x00000004U                            /*!< Complementary output channel is enabled */
+#define TIM_CCxN_DISABLE                 0x00000000U                            /*!< Complementary output channel is enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break_System TIM Break System
+  * @{
+  */
+#define TIM_BREAK_SYSTEM_ECC                 SYSCFG_CFGR2_ECCL   /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */
+#define TIM_BREAK_SYSTEM_PVD                 SYSCFG_CFGR2_PVDL   /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */
+#define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR   SYSCFG_CFGR2_SPL    /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17 */
+#define TIM_BREAK_SYSTEM_LOCKUP              SYSCFG_CFGR2_CLL    /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported constants -------------------------------------------------*/
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup TIM_Exported_Macros TIM Exported Macros
+  * @{
+  */
+
+/** @brief  Reset TIM handle state.
+  * @param  __HANDLE__ TIM handle.
+  * @retval None
+  */
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                        \
+                                                      (__HANDLE__)->State             = HAL_TIM_STATE_RESET; \
+                                                      (__HANDLE__)->Base_MspInitCallback         = NULL;     \
+                                                      (__HANDLE__)->Base_MspDeInitCallback       = NULL;     \
+                                                      (__HANDLE__)->IC_MspInitCallback           = NULL;     \
+                                                      (__HANDLE__)->IC_MspDeInitCallback         = NULL;     \
+                                                      (__HANDLE__)->OC_MspInitCallback           = NULL;     \
+                                                      (__HANDLE__)->OC_MspDeInitCallback         = NULL;     \
+                                                      (__HANDLE__)->PWM_MspInitCallback          = NULL;     \
+                                                      (__HANDLE__)->PWM_MspDeInitCallback        = NULL;     \
+                                                      (__HANDLE__)->OnePulse_MspInitCallback     = NULL;     \
+                                                      (__HANDLE__)->OnePulse_MspDeInitCallback   = NULL;     \
+                                                      (__HANDLE__)->Encoder_MspInitCallback      = NULL;     \
+                                                      (__HANDLE__)->Encoder_MspDeInitCallback    = NULL;     \
+                                                      (__HANDLE__)->HallSensor_MspInitCallback   = NULL;     \
+                                                      (__HANDLE__)->HallSensor_MspDeInitCallback = NULL;     \
+                                                     } while(0)
+#else
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @brief  Enable the TIM peripheral.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
+
+/**
+  * @brief  Enable the TIM main Output.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  */
+#define __HAL_TIM_MOE_ENABLE(__HANDLE__)             ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
+
+/**
+  * @brief  Disable the TIM peripheral.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE(__HANDLE__) \
+  do { \
+    if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
+    { \
+      if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
+      { \
+        (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
+      } \
+    } \
+  } while(0)
+
+/**
+  * @brief  Disable the TIM main Output.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
+  */
+#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
+  do { \
+    if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
+    { \
+      if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
+      { \
+        (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
+      } \
+    } \
+  } while(0)
+
+/**
+  * @brief  Disable the TIM main Output.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  * @note The Main Output Enable of a timer instance is disabled unconditionally
+  */
+#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__)  (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
+
+/** @brief  Enable the specified TIM interrupt.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __INTERRUPT__ specifies the TIM interrupt source to enable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_COM:   Commutation interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  *            @arg TIM_IT_BREAK: Break interrupt
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
+
+/** @brief  Disable the specified TIM interrupt.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __INTERRUPT__ specifies the TIM interrupt source to disable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_COM:   Commutation interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  *            @arg TIM_IT_BREAK: Break interrupt
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
+
+/** @brief  Enable the specified DMA request.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __DMA__ specifies the TIM DMA request to enable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: Update DMA request
+  *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
+  *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
+  *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
+  *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
+  *            @arg TIM_DMA_COM:   Commutation DMA request
+  *            @arg TIM_DMA_TRIGGER: Trigger DMA request
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__)         ((__HANDLE__)->Instance->DIER |= (__DMA__))
+
+/** @brief  Disable the specified DMA request.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __DMA__ specifies the TIM DMA request to disable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: Update DMA request
+  *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
+  *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
+  *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
+  *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
+  *            @arg TIM_DMA_COM:   Commutation DMA request
+  *            @arg TIM_DMA_TRIGGER: Trigger DMA request
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__)        ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
+
+/** @brief  Check whether the specified TIM interrupt flag is set or not.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __FLAG__ specifies the TIM interrupt flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg TIM_FLAG_UPDATE: Update interrupt flag
+  *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
+  *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
+  *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
+  *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
+  *            @arg TIM_FLAG_CC5: Compare 5 interrupt flag
+  *            @arg TIM_FLAG_CC6: Compare 6 interrupt flag
+  *            @arg TIM_FLAG_COM:  Commutation interrupt flag
+  *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
+  *            @arg TIM_FLAG_BREAK: Break interrupt flag
+  *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
+  *            @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
+  *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
+  *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
+  *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
+  *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
+
+/** @brief  Clear the specified TIM interrupt flag.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __FLAG__ specifies the TIM interrupt flag to clear.
+  *        This parameter can be one of the following values:
+  *            @arg TIM_FLAG_UPDATE: Update interrupt flag
+  *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
+  *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
+  *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
+  *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
+  *            @arg TIM_FLAG_CC5: Compare 5 interrupt flag
+  *            @arg TIM_FLAG_CC6: Compare 6 interrupt flag
+  *            @arg TIM_FLAG_COM:  Commutation interrupt flag
+  *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
+  *            @arg TIM_FLAG_BREAK: Break interrupt flag
+  *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
+  *            @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
+  *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
+  *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
+  *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
+  *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->SR = ~(__FLAG__))
+
+/**
+  * @brief  Check whether the specified TIM interrupt source is enabled or not.
+  * @param  __HANDLE__ TIM handle
+  * @param  __INTERRUPT__ specifies the TIM interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_COM:   Commutation interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  *            @arg TIM_IT_BREAK: Break interrupt
+  * @retval The state of TIM_IT (SET or RESET).
+  */
+#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
+                                                             == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Clear the TIM interrupt pending bits.
+  * @param  __HANDLE__ TIM handle
+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_COM:   Commutation interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  *            @arg TIM_IT_BREAK: Break interrupt
+  * @retval None
+  */
+#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
+
+/**
+  * @brief  Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
+  * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
+  * @param  __HANDLE__ TIM handle.
+  * @retval None
+mode.
+  */
+#define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__)    (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP))
+
+/**
+  * @brief  Disable update interrupt flag (UIF) remapping.
+  * @param  __HANDLE__ TIM handle.
+  * @retval None
+mode.
+  */
+#define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__)    (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP))
+
+/**
+  * @brief  Get update interrupt flag (UIF) copy status.
+  * @param  __COUNTER__ Counter value.
+  * @retval The state of UIFCPY (TRUE or FALSE).
+mode.
+  */
+#define __HAL_TIM_GET_UIFCPY(__COUNTER__)    (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY))
+
+/**
+  * @brief  Indicates whether or not the TIM Counter is used as downcounter.
+  * @param  __HANDLE__ TIM handle.
+  * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
+  * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
+mode.
+  */
+#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__)    (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
+
+/**
+  * @brief  Set the TIM Prescaler on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __PRESC__ specifies the Prescaler new value.
+  * @retval None
+  */
+#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__)       ((__HANDLE__)->Instance->PSC = (__PRESC__))
+
+/**
+  * @brief  Set the TIM Counter Register value on runtime.
+  * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in case of 32 bits counter TIM instance.
+  *      Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __COUNTER__ specifies the Counter register new value.
+  * @retval None
+  */
+#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__)  ((__HANDLE__)->Instance->CNT = (__COUNTER__))
+
+/**
+  * @brief  Get the TIM Counter Register value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
+  */
+#define __HAL_TIM_GET_COUNTER(__HANDLE__)  ((__HANDLE__)->Instance->CNT)
+
+/**
+  * @brief  Set the TIM Autoreload Register value on runtime without calling another time any Init function.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __AUTORELOAD__ specifies the Counter register new value.
+  * @retval None
+  */
+#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
+  do{                                                    \
+    (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
+    (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
+  } while(0)
+
+/**
+  * @brief  Get the TIM Autoreload Register value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
+  */
+#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__)  ((__HANDLE__)->Instance->ARR)
+
+/**
+  * @brief  Set the TIM Clock Division value on runtime without calling another time any Init function.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CKD__ specifies the clock division value.
+  *          This parameter can be one of the following value:
+  *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
+  * @retval None
+  */
+#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
+  do{                                                   \
+    (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD);  \
+    (__HANDLE__)->Instance->CR1 |= (__CKD__);       \
+    (__HANDLE__)->Init.ClockDivision = (__CKD__);   \
+  } while(0)
+
+/**
+  * @brief  Get the TIM Clock Division value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @retval The clock division can be one of the following values:
+  *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
+  */
+#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__)  ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
+
+/**
+  * @brief  Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  __ICPSC__ specifies the Input Capture4 prescaler new value.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPSC_DIV1: no prescaler
+  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+  * @retval None
+  */
+#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
+  do{                                                    \
+    TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \
+    TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
+  } while(0)
+
+/**
+  * @brief  Get the TIM Input Capture prescaler on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: get input capture 1 prescaler value
+  *            @arg TIM_CHANNEL_2: get input capture 2 prescaler value
+  *            @arg TIM_CHANNEL_3: get input capture 3 prescaler value
+  *            @arg TIM_CHANNEL_4: get input capture 4 prescaler value
+  * @retval The input capture prescaler can be one of the following values:
+  *            @arg TIM_ICPSC_DIV1: no prescaler
+  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+  */
+#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)  \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
+   (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
+
+/**
+  * @brief  Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @param  __COMPARE__ specifies the Capture Compare register new value.
+  * @retval None
+  */
+#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
+   ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
+
+/**
+  * @brief  Get the TIM Capture Compare Register value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channel associated with the capture compare register
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: get capture/compare 1 register value
+  *            @arg TIM_CHANNEL_2: get capture/compare 2 register value
+  *            @arg TIM_CHANNEL_3: get capture/compare 3 register value
+  *            @arg TIM_CHANNEL_4: get capture/compare 4 register value
+  *            @arg TIM_CHANNEL_5: get capture/compare 5 register value
+  *            @arg TIM_CHANNEL_6: get capture/compare 6 register value
+  * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
+  */
+#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
+   ((__HANDLE__)->Instance->CCR6))
+
+/**
+  * @brief  Set the TIM Output compare preload.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
+   ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))
+
+/**
+  * @brief  Reset the TIM Output compare preload.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\
+   ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE))
+
+/**
+  * @brief  Enable fast mode for a given channel.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @note  When fast mode is enabled an active edge on the trigger input acts
+  *        like a compare match on CCx output. Delay to sample the trigger
+  *        input and to activate CCx output is reduced to 3 clock cycles.
+  * @note  Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\
+   ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE))
+
+/**
+  * @brief  Disable fast mode for a given channel.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @note  When fast mode is disabled CCx output behaves normally depending
+  *        on counter and CCRx values even when the trigger is ON. The minimum
+  *        delay to activate CCx output when an active edge occurs on the
+  *        trigger input is 5 clock cycles.
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\
+   ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE))
+
+/**
+  * @brief  Set the Update Request Source (URS) bit of the TIMx_CR1 register.
+  * @param  __HANDLE__ TIM handle.
+  * @note  When the URS bit of the TIMx_CR1 register is set, only counter
+  *        overflow/underflow generates an update interrupt or DMA request (if
+  *        enabled)
+  * @retval None
+  */
+#define __HAL_TIM_URS_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
+
+/**
+  * @brief  Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
+  * @param  __HANDLE__ TIM handle.
+  * @note  When the URS bit of the TIMx_CR1 register is reset, any of the
+  *        following events generate an update interrupt or DMA request (if
+  *        enabled):
+  *           _ Counter overflow underflow
+  *           _ Setting the UG bit
+  *           _ Update generation through the slave mode controller
+  * @retval None
+  */
+#define __HAL_TIM_URS_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
+
+/**
+  * @brief  Set the TIM Capture x input polarity on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  __POLARITY__ Polarity for TIx source
+  *            @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
+  *            @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
+  *            @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
+  * @retval None
+  */
+#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)    \
+  do{                                                                     \
+    TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \
+    TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
+  }while(0)
+
+/**
+  * @}
+  */
+/* End of exported macros ----------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup TIM_Private_Constants TIM Private Constants
+  * @{
+  */
+/* The counter of a timer instance is disabled only if all the CCx and CCxN
+   channels have been disabled */
+#define TIM_CCER_CCxE_MASK  ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
+#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
+/**
+  * @}
+  */
+/* End of private constants --------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TIM_Private_Macros TIM Private Macros
+  * @{
+  */
+#define IS_TIM_CLEARINPUT_SOURCE(__MODE__)  (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)      || \
+                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))
+
+#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1)   || \
+                                   ((__BASE__) == TIM_DMABASE_CR2)   || \
+                                   ((__BASE__) == TIM_DMABASE_SMCR)  || \
+                                   ((__BASE__) == TIM_DMABASE_DIER)  || \
+                                   ((__BASE__) == TIM_DMABASE_SR)    || \
+                                   ((__BASE__) == TIM_DMABASE_EGR)   || \
+                                   ((__BASE__) == TIM_DMABASE_CCMR1) || \
+                                   ((__BASE__) == TIM_DMABASE_CCMR2) || \
+                                   ((__BASE__) == TIM_DMABASE_CCER)  || \
+                                   ((__BASE__) == TIM_DMABASE_CNT)   || \
+                                   ((__BASE__) == TIM_DMABASE_PSC)   || \
+                                   ((__BASE__) == TIM_DMABASE_ARR)   || \
+                                   ((__BASE__) == TIM_DMABASE_RCR)   || \
+                                   ((__BASE__) == TIM_DMABASE_CCR1)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCR2)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCR3)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCR4)  || \
+                                   ((__BASE__) == TIM_DMABASE_BDTR)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCMR3) || \
+                                   ((__BASE__) == TIM_DMABASE_CCR5)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCR6)  || \
+                                   ((__BASE__) == TIM_DMABASE_AF1)   || \
+                                   ((__BASE__) == TIM_DMABASE_AF2)   || \
+                                   ((__BASE__) == TIM_DMABASE_TISEL))
+
+
+#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
+
+#define IS_TIM_COUNTER_MODE(__MODE__)      (((__MODE__) == TIM_COUNTERMODE_UP)              || \
+                                            ((__MODE__) == TIM_COUNTERMODE_DOWN)            || \
+                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
+                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
+                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
+
+#define IS_TIM_UIFREMAP_MODE(__MODE__)     (((__MODE__) == TIM_UIFREMAP_DISABLE) || \
+                                            ((__MODE__) == TIM_UIFREMAP_ENALE))
+
+#define IS_TIM_CLOCKDIVISION_DIV(__DIV__)  (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
+                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
+                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
+
+#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
+                                            ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
+
+#define IS_TIM_FAST_STATE(__STATE__)       (((__STATE__) == TIM_OCFAST_DISABLE) || \
+                                            ((__STATE__) == TIM_OCFAST_ENABLE))
+
+#define IS_TIM_OC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
+                                            ((__POLARITY__) == TIM_OCPOLARITY_LOW))
+
+#define IS_TIM_OCN_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
+                                            ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
+
+#define IS_TIM_OCIDLE_STATE(__STATE__)     (((__STATE__) == TIM_OCIDLESTATE_SET) || \
+                                            ((__STATE__) == TIM_OCIDLESTATE_RESET))
+
+#define IS_TIM_OCNIDLE_STATE(__STATE__)    (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
+                                            ((__STATE__) == TIM_OCNIDLESTATE_RESET))
+
+#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING)   || \
+                                                      ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
+
+#define IS_TIM_IC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ICPOLARITY_RISING)   || \
+                                            ((__POLARITY__) == TIM_ICPOLARITY_FALLING)  || \
+                                            ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
+
+#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
+                                            ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
+                                            ((__SELECTION__) == TIM_ICSELECTION_TRC))
+
+#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
+                                            ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
+                                            ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
+                                            ((__PRESCALER__) == TIM_ICPSC_DIV8))
+
+#define IS_TIM_OPM_MODE(__MODE__)          (((__MODE__) == TIM_OPMODE_SINGLE) || \
+                                            ((__MODE__) == TIM_OPMODE_REPETITIVE))
+
+#define IS_TIM_ENCODER_MODE(__MODE__)      (((__MODE__) == TIM_ENCODERMODE_TI1) || \
+                                            ((__MODE__) == TIM_ENCODERMODE_TI2) || \
+                                            ((__MODE__) == TIM_ENCODERMODE_TI12))
+
+#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
+
+#define IS_TIM_CHANNELS(__CHANNEL__)       (((__CHANNEL__) == TIM_CHANNEL_1) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_2) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_3) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_4) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_5) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_6) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_ALL))
+
+#define IS_TIM_OPM_CHANNELS(__CHANNEL__)   (((__CHANNEL__) == TIM_CHANNEL_1) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_2))
+
+#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
+                                                    ((__CHANNEL__) == TIM_CHANNEL_2) || \
+                                                    ((__CHANNEL__) == TIM_CHANNEL_3))
+
+#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
+
+#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED)    || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING)      || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING)     || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
+
+#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
+                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
+                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
+                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
+
+#define IS_TIM_CLOCKFILTER(__ICFILTER__)      ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
+                                                  ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
+
+#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
+                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
+                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
+                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
+
+#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_OSSR_STATE(__STATE__)       (((__STATE__) == TIM_OSSR_ENABLE) || \
+                                            ((__STATE__) == TIM_OSSR_DISABLE))
+
+#define IS_TIM_OSSI_STATE(__STATE__)       (((__STATE__) == TIM_OSSI_ENABLE) || \
+                                            ((__STATE__) == TIM_OSSI_DISABLE))
+
+#define IS_TIM_LOCK_LEVEL(__LEVEL__)       (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
+                                            ((__LEVEL__) == TIM_LOCKLEVEL_1)   || \
+                                            ((__LEVEL__) == TIM_LOCKLEVEL_2)   || \
+                                            ((__LEVEL__) == TIM_LOCKLEVEL_3))
+
+#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
+
+
+#define IS_TIM_BREAK_STATE(__STATE__)      (((__STATE__) == TIM_BREAK_ENABLE) || \
+                                            ((__STATE__) == TIM_BREAK_DISABLE))
+
+#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
+                                             ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
+
+#define IS_TIM_BREAK2_STATE(__STATE__)     (((__STATE__) == TIM_BREAK2_ENABLE) || \
+                                            ((__STATE__) == TIM_BREAK2_DISABLE))
+
+#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
+                                              ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
+
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
+                                                  ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
+
+#define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))
+
+#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET)  || \
+                                        ((__SOURCE__) == TIM_TRGO_ENABLE) || \
+                                        ((__SOURCE__) == TIM_TRGO_UPDATE) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC1)    || \
+                                        ((__SOURCE__) == TIM_TRGO_OC1REF) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC2REF) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC3REF) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC4REF))
+
+#define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET)                        || \
+                                         ((__SOURCE__) == TIM_TRGO2_ENABLE)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_UPDATE)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC1)                          || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC1REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC2REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC4REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC5REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC6REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING)         || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING)         || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING)  || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING)  || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
+
+#define IS_TIM_MSM_STATE(__STATE__)      (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
+                                          ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
+
+#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE)   || \
+                                     ((__MODE__) == TIM_SLAVEMODE_RESET)     || \
+                                     ((__MODE__) == TIM_SLAVEMODE_GATED)     || \
+                                     ((__MODE__) == TIM_SLAVEMODE_TRIGGER)   || \
+                                     ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \
+                                     ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
+
+#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1)               || \
+                                   ((__MODE__) == TIM_OCMODE_PWM2)               || \
+                                   ((__MODE__) == TIM_OCMODE_COMBINED_PWM1)      || \
+                                   ((__MODE__) == TIM_OCMODE_COMBINED_PWM2)      || \
+                                   ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1)    || \
+                                   ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))
+
+#define IS_TIM_OC_MODE(__MODE__)  (((__MODE__) == TIM_OCMODE_TIMING)             || \
+                                   ((__MODE__) == TIM_OCMODE_ACTIVE)             || \
+                                   ((__MODE__) == TIM_OCMODE_INACTIVE)           || \
+                                   ((__MODE__) == TIM_OCMODE_TOGGLE)             || \
+                                   ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE)      || \
+                                   ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)    || \
+                                   ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
+                                   ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2))
+
+#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR1) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR2) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR3) || \
+                                                 ((__SELECTION__) == TIM_TS_TI1F_ED) || \
+                                                 ((__SELECTION__) == TIM_TS_TI1FP1) || \
+                                                 ((__SELECTION__) == TIM_TS_TI2FP2) || \
+                                                 ((__SELECTION__) == TIM_TS_ETRF) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR4) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR5) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR6) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR7) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR8) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR12) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR13))
+
+#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR1) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR2) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR3) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR4) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR5) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR6) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR7) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR8) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR12) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR13) || \
+                                                               ((__SELECTION__) == TIM_TS_NONE))
+
+#define IS_TIM_TRIGGERPOLARITY(__POLARITY__)   (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING     ) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING    ) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))
+
+#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
+                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
+                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
+                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
+
+#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_TI1SELECTION(__TI1SELECTION__)  (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
+                                                ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
+
+#define IS_TIM_DMA_LENGTH(__LENGTH__)      (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
+
+#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
+
+#define IS_TIM_IC_FILTER(__ICFILTER__)   ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_DEADTIME(__DEADTIME__)    ((__DEADTIME__) <= 0xFFU)
+
+#define IS_TIM_BREAK_SYSTEM(__CONFIG__)    (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC)                  || \
+                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD)                  || \
+                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR)    || \
+                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))
+
+#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \
+                                                       ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
+
+#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
+   ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
+
+#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
+   ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
+
+#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
+   ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
+
+#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
+   ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
+
+/**
+  * @}
+  */
+/* End of private macros -----------------------------------------------------*/
+
+/* Include TIM HAL Extended module */
+#include "stm32h7xx_hal_tim_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIM_Exported_Functions TIM Exported Functions
+  * @{
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
+  *  @brief   Time Base functions
+  * @{
+  */
+/* Time Base functions ********************************************************/
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
+  *  @brief   TIM Output Compare functions
+  * @{
+  */
+/* Timer Output Compare functions *********************************************/
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
+  *  @brief   TIM PWM functions
+  * @{
+  */
+/* Timer PWM functions ********************************************************/
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
+  *  @brief   TIM Input Capture functions
+  * @{
+  */
+/* Timer Input Capture functions **********************************************/
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
+  *  @brief   TIM One Pulse functions
+  * @{
+  */
+/* Timer One Pulse functions **************************************************/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
+  *  @brief   TIM Encoder functions
+  * @{
+  */
+/* Timer Encoder functions ****************************************************/
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef *sConfig);
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
+                                            uint32_t *pData2, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
+  *  @brief   IRQ handler management
+  * @{
+  */
+/* Interrupt Handler functions  ***********************************************/
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
+  *  @brief   Peripheral Control functions
+  * @{
+  */
+/* Control functions  *********************************************************/
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
+                                                 uint32_t OutputChannel,  uint32_t InputChannel);
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,
+                                           uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                              uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                                   uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
+                                                   uint32_t DataLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                             uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                                  uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength,
+                                                  uint32_t  DataLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
+  *  @brief   TIM Callbacks functions
+  * @{
+  */
+/* Callback in non blocking modes (Interrupt and DMA) *************************/
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
+                                           pTIM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
+  *  @brief  Peripheral State functions
+  * @{
+  */
+/* Peripheral State functions  ************************************************/
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private functions----------------------------------------------------------*/
+/** @defgroup TIM_Private_Functions TIM Private Functions
+  * @{
+  */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
+                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
+
+void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMAError(DMA_HandleTypeDef *hdma);
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
+void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+void TIM_ResetCallback(TIM_HandleTypeDef *htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+/* End of private functions --------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_TIM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h
new file mode 100644
index 00000000..0a7ef48a
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h
@@ -0,0 +1,529 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_tim_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of TIM HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_TIM_EX_H
+#define STM32H7xx_HAL_TIM_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup TIMEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
+  * @{
+  */
+
+/**
+  * @brief  TIM Hall sensor Configuration Structure definition
+  */
+
+typedef struct
+{
+  uint32_t IC1Polarity;         /*!< Specifies the active edge of the input signal.
+                                     This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint32_t IC1Prescaler;        /*!< Specifies the Input Capture Prescaler.
+                                     This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t IC1Filter;           /*!< Specifies the input capture filter.
+                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+  uint32_t Commutation_Delay;   /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+                                     This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+} TIM_HallSensor_InitTypeDef;
+#if defined(TIM_BREAK_INPUT_SUPPORT)
+
+/**
+  * @brief  TIM Break/Break2 input configuration
+  */
+typedef struct
+{
+  uint32_t Source;         /*!< Specifies the source of the timer break input.
+                                This parameter can be a value of @ref TIMEx_Break_Input_Source */
+  uint32_t Enable;         /*!< Specifies whether or not the break input source is enabled.
+                                This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */
+  uint32_t Polarity;       /*!< Specifies the break input source polarity.
+                                This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity
+                                Not relevant when analog watchdog output of the DFSDM1 used as break input source */
+}
+TIMEx_BreakInputConfigTypeDef;
+
+#endif /* TIM_BREAK_INPUT_SUPPORT */
+/**
+  * @}
+  */
+/* End of exported types -----------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
+  * @{
+  */
+
+/** @defgroup TIMEx_Remap TIM Extended Remapping
+  * @{
+  */
+#define TIM_TIM1_ETR_GPIO        0x00000000U                                                 /* !< TIM1_ETR is connected to GPIO */
+#define TIM_TIM1_ETR_COMP1       TIM1_AF1_ETRSEL_0                                           /* !< TIM1_ETR is connected to COMP1 OUT */
+#define TIM_TIM1_ETR_COMP2       TIM1_AF1_ETRSEL_1                                           /* !< TIM1_ETR is connected to COMP2 OUT */
+#define TIM_TIM1_ETR_ADC1_AWD1   (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                     /* !< TIM1_ETR is connected to ADC1 AWD1 */
+#define TIM_TIM1_ETR_ADC1_AWD2   (TIM1_AF1_ETRSEL_2)                                         /* !< TIM1_ETR is connected to ADC1 AWD2 */
+#define TIM_TIM1_ETR_ADC1_AWD3   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                     /* !< TIM1_ETR is connected to ADC1 AWD3 */
+#define TIM_TIM1_ETR_ADC3_AWD1   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                     /* !< TIM1_ETR is connected to ADC3 AWD1 */
+#define TIM_TIM1_ETR_ADC3_AWD2   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC3 AWD2 */
+#define TIM_TIM1_ETR_ADC3_AWD3   TIM1_AF1_ETRSEL_3                                           /* !< TIM1_ETR is connected to ADC3 AWD3 */
+
+#define TIM_TIM8_ETR_GPIO        0x00000000U                                                 /* !< TIM8_ETR is connected to GPIO */
+#define TIM_TIM8_ETR_COMP1       TIM8_AF1_ETRSEL_0                                           /* !< TIM8_ETR is connected to COMP1 OUT */
+#define TIM_TIM8_ETR_COMP2       TIM8_AF1_ETRSEL_1                                           /* !< TIM8_ETR is connected to COMP2 OUT */
+#define TIM_TIM8_ETR_ADC2_AWD1   (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)                     /* !< TIM8_ETR is connected to ADC2 AWD1 */
+#define TIM_TIM8_ETR_ADC2_AWD2   (TIM8_AF1_ETRSEL_2)                                         /* !< TIM8_ETR is connected to ADC2 AWD2 */
+#define TIM_TIM8_ETR_ADC2_AWD3   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0)                     /* !< TIM8_ETR is connected to ADC2 AWD3 */
+#define TIM_TIM8_ETR_ADC3_AWD1   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1)                     /* !< TIM8_ETR is connected to ADC3 AWD1 */
+#define TIM_TIM8_ETR_ADC3_AWD2   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC3 AWD2 */
+#define TIM_TIM8_ETR_ADC3_AWD3   TIM8_AF1_ETRSEL_3                                           /* !< TIM8_ETR is connected to ADC3 AWD3 */
+
+#define TIM_TIM2_ETR_GPIO        0x00000000U                             /* !< TIM2_ETR is connected to GPIO */
+#define TIM_TIM2_ETR_COMP1       (TIM2_AF1_ETRSEL_0)                     /* !< TIM2_ETR is connected to COMP1 OUT */
+#define TIM_TIM2_ETR_COMP2       (TIM2_AF1_ETRSEL_1)                     /* !< TIM2_ETR is connected to COMP2 OUT */
+#define TIM_TIM2_ETR_RCC_LSE     (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to RCC LSE */
+#define TIM_TIM2_ETR_SAI1_FSA    TIM2_AF1_ETRSEL_2                       /* !< TIM2_ETR is connected to SAI1 FS_A */
+#define TIM_TIM2_ETR_SAI1_FSB    (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to SAI1 FS_B */
+
+#define TIM_TIM3_ETR_GPIO        0x00000000U          /* !< TIM3_ETR is connected to GPIO */
+#define TIM_TIM3_ETR_COMP1       TIM3_AF1_ETRSEL_0    /* !< TIM3_ETR is connected to COMP1 OUT */
+
+#define TIM_TIM5_ETR_GPIO        0x00000000U          /* !< TIM5_ETR is connected to GPIO */
+#define TIM_TIM5_ETR_SAI2_FSA    TIM5_AF1_ETRSEL_0    /* !< TIM5_ETR is connected to SAI2 FS_A */
+#define TIM_TIM5_ETR_SAI2_FSB    TIM5_AF1_ETRSEL_1    /* !< TIM5_ETR is connected to SAI2 FS_B */
+#define TIM_TIM5_ETR_SAI4_FSA    TIM5_AF1_ETRSEL_0    /* !< TIM5_ETR is connected to SAI4 FS_A */
+#define TIM_TIM5_ETR_SAI4_FSB    TIM5_AF1_ETRSEL_1    /* !< TIM5_ETR is connected to SAI4 FS_B */
+
+#define TIM_TIM23_ETR_GPIO       0x00000000U          /* !< TIM23_ETR is connected to GPIO */
+#define TIM_TIM23_ETR_COMP1      (TIM2_AF1_ETRSEL_0)  /* !< TIM23_ETR is connected to COMP1 OUT */
+#define TIM_TIM23_ETR_COMP2      (TIM2_AF1_ETRSEL_1)  /* !< TIM23_ETR is connected to COMP2 OUT */
+
+#define TIM_TIM24_ETR_GPIO        0x00000000U                                /* !< TIM24_ETR is connected to GPIO */
+#define TIM_TIM24_ETR_SAI4_FSA    TIM5_AF1_ETRSEL_0                          /* !< TIM24_ETR is connected to SAI4 FS_A */
+#define TIM_TIM24_ETR_SAI4_FSB    TIM5_AF1_ETRSEL_1                          /* !< TIM24_ETR is connected to SAI4 FS_B */
+#define TIM_TIM24_ETR_SAI1_FSA    (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)    /* !< TIM24_ETR is connected to SAI1 FS_A */
+#define TIM_TIM24_ETR_SAI1_FSB    TIM2_AF1_ETRSEL_2                          /* !< TIM24_ETR is connected to SAI1 FS_B */
+/**
+  * @}
+  */
+#if defined(TIM_BREAK_INPUT_SUPPORT)
+
+/** @defgroup TIMEx_Break_Input TIM Extended Break input
+  * @{
+  */
+#define TIM_BREAKINPUT_BRK     0x00000001U                                      /* !< Timer break input  */
+#define TIM_BREAKINPUT_BRK2    0x00000002U                                      /* !< Timer break2 input */
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source
+  * @{
+  */
+#define TIM_BREAKINPUTSOURCE_BKIN     0x00000001U                               /* !< An external source (GPIO) is connected to the BKIN pin  */
+#define TIM_BREAKINPUTSOURCE_COMP1    0x00000002U                               /* !< The COMP1 output is connected to the break input */
+#define TIM_BREAKINPUTSOURCE_COMP2    0x00000004U                               /* !< The COMP2 output is connected to the break input */
+#define TIM_BREAKINPUTSOURCE_DFSDM1   0x00000008U                               /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling
+  * @{
+  */
+#define TIM_BREAKINPUTSOURCE_DISABLE     0x00000000U                            /* !< Break input source is disabled */
+#define TIM_BREAKINPUTSOURCE_ENABLE      0x00000001U                            /* !< Break input source is enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity
+  * @{
+  */
+#define TIM_BREAKINPUTSOURCE_POLARITY_LOW     0x00000001U                       /* !< Break input source is active low */
+#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH    0x00000000U                       /* !< Break input source is active_high */
+/**
+  * @}
+  */
+#endif /* TIM_BREAK_INPUT_SUPPORT */
+
+/** @defgroup TIMEx_Timer_Input_Selection TIM Extended Timer input selection
+  * @{
+  */
+#define TIM_TIM1_TI1_GPIO                          0x00000000U                               /* !< TIM1_TI1 is connected to GPIO */
+#define TIM_TIM1_TI1_COMP1                         TIM_TISEL_TI1SEL_0                        /* !< TIM1_TI1 is connected to COMP1 OUT */
+
+#define TIM_TIM8_TI1_GPIO                          0x00000000U                               /* !< TIM8_TI1 is connected to GPIO */
+#define TIM_TIM8_TI1_COMP2                         TIM_TISEL_TI1SEL_0                        /* !< TIM8_TI1 is connected to COMP2 OUT */
+
+#define TIM_TIM2_TI4_GPIO                          0x00000000U                               /* !< TIM2_TI4 is connected to GPIO */
+#define TIM_TIM2_TI4_COMP1                         TIM_TISEL_TI4SEL_0                        /* !< TIM2_TI4 is connected to COMP1 OUT */
+#define TIM_TIM2_TI4_COMP2                         TIM_TISEL_TI4SEL_1                        /* !< TIM2_TI4 is connected to COMP2 OUT */
+#define TIM_TIM2_TI4_COMP1_COMP2                   (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM2_TI4 is connected to COMP2 OUT OR COMP2 OUT */
+
+#define TIM_TIM3_TI1_GPIO                          0x00000000U                               /* !< TIM3_TI1 is connected to GPIO */
+#define TIM_TIM3_TI1_COMP1                         TIM_TISEL_TI1SEL_0                        /* !< TIM3_TI1 is connected to COMP1 OUT */
+#define TIM_TIM3_TI1_COMP2                         TIM_TISEL_TI1SEL_1                        /* !< TIM3_TI1 is connected to COMP2 OUT */
+#define TIM_TIM3_TI1_COMP1_COMP2                   (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM3_TI1 is connected to COMP1 OUT or COMP2 OUT */
+
+#define TIM_TIM5_TI1_GPIO                          0x00000000U                               /* !< TIM5_TI1 is connected to GPIO */
+#define TIM_TIM5_TI1_CAN_TMP                       TIM_TISEL_TI1SEL_0                        /* !< TIM5_TI1 is connected to CAN TMP */
+#define TIM_TIM5_TI1_CAN_RTP                       TIM_TISEL_TI1SEL_1                        /* !< TIM5_TI1 is connected to CAN RTP */
+
+#define TIM_TIM12_TI1_GPIO                         0x00000000U                               /* !< TIM12 TI1 is connected to GPIO */
+#define TIM_TIM12_TI1_SPDIF_FS                     TIM_TISEL_TI1SEL_0                        /* !< TIM12 TI1 is connected to SPDIF FS */
+
+#define TIM_TIM15_TI1_GPIO                         0x00000000U                               /* !< TIM15_TI1 is connected to GPIO */
+#define TIM_TIM15_TI1_TIM2_CH1                     TIM_TISEL_TI1SEL_0                        /* !< TIM15_TI1 is connected to TIM2 CH1 */
+#define TIM_TIM15_TI1_TIM3_CH1                     TIM_TISEL_TI1SEL_1                        /* !< TIM15_TI1 is connected to TIM3 CH1 */
+#define TIM_TIM15_TI1_TIM4_CH1                     (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM15_TI1 is connected to TIM4 CH1 */
+#define TIM_TIM15_TI1_RCC_LSE                      (TIM_TISEL_TI1SEL_2)                      /* !< TIM15_TI1 is connected to RCC LSE  */
+#define TIM_TIM15_TI1_RCC_CSI                      (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /* !< TIM15_TI1 is connected to RCC CSI  */
+#define TIM_TIM15_TI1_RCC_MCO2                     (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /* !< TIM15_TI1 is connected to RCC MCO2 */
+
+#define TIM_TIM15_TI2_GPIO                         0x00000000U                               /* !< TIM15_TI2 is connected to GPIO */
+#define TIM_TIM15_TI2_TIM2_CH2                     (TIM_TISEL_TI2SEL_0)                      /* !< TIM15_TI2 is connected to TIM2 CH2 */
+#define TIM_TIM15_TI2_TIM3_CH2                     (TIM_TISEL_TI2SEL_1)                      /* !< TIM15_TI2 is connected to TIM3 CH2 */
+#define TIM_TIM15_TI2_TIM4_CH2                     (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1) /* !< TIM15_TI2 is connected to TIM4 CH2 */
+
+#define TIM_TIM16_TI1_GPIO                         0x00000000U                               /* !< TIM16 TI1 is connected to GPIO */
+#define TIM_TIM16_TI1_RCC_LSI                      TIM_TISEL_TI1SEL_0                        /* !< TIM16 TI1 is connected to RCC LSI */
+#define TIM_TIM16_TI1_RCC_LSE                      TIM_TISEL_TI1SEL_1                        /* !< TIM16 TI1 is connected to RCC LSE */
+#define TIM_TIM16_TI1_WKUP_IT                      (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM16 TI1 is connected to WKUP_IT */
+
+#define TIM_TIM17_TI1_GPIO                         0x00000000U                               /* !< TIM17 TI1 is connected to GPIO */
+#define TIM_TIM17_TI1_SPDIF_FS                     TIM_TISEL_TI1SEL_0                        /* !< TIM17 TI1 is connected to SPDIF FS */
+#define TIM_TIM17_TI1_RCC_HSE1MHZ                  TIM_TISEL_TI1SEL_1                        /* !< TIM17 TI1 is connected to RCC HSE 1Mhz */
+#define TIM_TIM17_TI1_RCC_MCO1                     (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM17 TI1 is connected to RCC MCO1 */
+
+#define TIM_TIM23_TI4_GPIO                         0x00000000U                               /* !< TIM23_TI4 is connected to GPIO */
+#define TIM_TIM23_TI4_COMP1                        TIM_TISEL_TI4SEL_0                        /* !< TIM23_TI4 is connected to COMP1 OUT */
+#define TIM_TIM23_TI4_COMP2                        TIM_TISEL_TI4SEL_1                        /* !< TIM23_TI4 is connected to COMP2 OUT */
+#define TIM_TIM23_TI4_COMP1_COMP2                  (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM23_TI4 is connected to COMP1 OUT or COMP2 OUT */
+
+#define TIM_TIM24_TI1_GPIO                         0x00000000U                               /* !< TIM24_TI1 is connected to GPIO */
+#define TIM_TIM24_TI1_CAN_TMP                      TIM_TISEL_TI1SEL_0                        /* !< TIM24_TI1 is connected to CAN TMP  */
+#define TIM_TIM24_TI1_CAN_RTP                      TIM_TISEL_TI1SEL_1                        /* !< TIM24_TI1 is connected to CAN RTP  */
+#define TIM_TIM24_TI1_CAN_SOC                      (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM24_TI1 is connected to CAN SOC */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported constants -------------------------------------------------*/
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+/* End of exported macro -----------------------------------------------------*/
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
+  * @{
+  */
+#define IS_TIM_BREAKINPUT(__BREAKINPUT__)  (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK)  || \
+                                            ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
+
+#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__)  (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)  || \
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM1))
+
+#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__)  (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE)  || \
+                                                   ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
+
+#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW)  || \
+                                                         ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
+
+#define IS_TIM_TISEL(__TISEL__)  (((__TISEL__) == TIM_TIM1_TI1_GPIO)         ||\
+                                  ((__TISEL__) == TIM_TIM1_TI1_COMP1)        ||\
+                                  ((__TISEL__) == TIM_TIM8_TI1_GPIO)         ||\
+                                  ((__TISEL__) == TIM_TIM8_TI1_COMP2)        ||\
+                                  ((__TISEL__) == TIM_TIM2_TI4_GPIO)         ||\
+                                  ((__TISEL__) == TIM_TIM2_TI4_COMP1)        ||\
+                                  ((__TISEL__) == TIM_TIM2_TI4_COMP2)        ||\
+                                  ((__TISEL__) == TIM_TIM2_TI4_COMP1_COMP2)  ||\
+                                  ((__TISEL__) == TIM_TIM3_TI1_GPIO)         ||\
+                                  ((__TISEL__) == TIM_TIM3_TI1_COMP1)        ||\
+                                  ((__TISEL__) == TIM_TIM3_TI1_COMP2)        ||\
+                                  ((__TISEL__) == TIM_TIM3_TI1_COMP1_COMP2)  ||\
+                                  ((__TISEL__) == TIM_TIM5_TI1_GPIO)         ||\
+                                  ((__TISEL__) == TIM_TIM5_TI1_CAN_TMP)      ||\
+                                  ((__TISEL__) == TIM_TIM5_TI1_CAN_RTP)      ||\
+                                  ((__TISEL__) == TIM_TIM12_TI1_SPDIF_FS)    ||\
+                                  ((__TISEL__) == TIM_TIM12_TI1_GPIO)        ||\
+                                  ((__TISEL__) == TIM_TIM15_TI1_GPIO)        ||\
+                                  ((__TISEL__) == TIM_TIM15_TI1_TIM2_CH1)    ||\
+                                  ((__TISEL__) == TIM_TIM15_TI1_TIM3_CH1)    ||\
+                                  ((__TISEL__) == TIM_TIM15_TI1_TIM4_CH1)    ||\
+                                  ((__TISEL__) == TIM_TIM15_TI1_RCC_LSE)     ||\
+                                  ((__TISEL__) == TIM_TIM15_TI1_RCC_CSI)     ||\
+                                  ((__TISEL__) == TIM_TIM15_TI1_RCC_MCO2)    ||\
+                                  ((__TISEL__) == TIM_TIM15_TI2_GPIO)        ||\
+                                  ((__TISEL__) == TIM_TIM15_TI2_TIM2_CH2)    ||\
+                                  ((__TISEL__) == TIM_TIM15_TI2_TIM3_CH2)    ||\
+                                  ((__TISEL__) == TIM_TIM15_TI2_TIM4_CH2)    ||\
+                                  ((__TISEL__) == TIM_TIM16_TI1_GPIO)        ||\
+                                  ((__TISEL__) == TIM_TIM16_TI1_RCC_LSI)     ||\
+                                  ((__TISEL__) == TIM_TIM16_TI1_RCC_LSE)     ||\
+                                  ((__TISEL__) == TIM_TIM16_TI1_WKUP_IT)     ||\
+                                  ((__TISEL__) == TIM_TIM17_TI1_GPIO)        ||\
+                                  ((__TISEL__) == TIM_TIM17_TI1_SPDIF_FS)    ||\
+                                  ((__TISEL__) == TIM_TIM17_TI1_RCC_HSE1MHZ) ||\
+                                  ((__TISEL__) == TIM_TIM17_TI1_RCC_MCO1)    ||\
+                                  ((__TISEL__) == TIM_TIM23_TI4_GPIO)        ||\
+                                  ((__TISEL__) == TIM_TIM23_TI4_COMP1)       ||\
+                                  ((__TISEL__) == TIM_TIM23_TI4_COMP2)       ||\
+                                  ((__TISEL__) == TIM_TIM23_TI4_COMP1_COMP2) ||\
+                                  ((__TISEL__) == TIM_TIM24_TI1_GPIO)        ||\
+                                  ((__TISEL__) == TIM_TIM24_TI1_CAN_TMP)     ||\
+                                  ((__TISEL__) == TIM_TIM24_TI1_CAN_RTP)     ||\
+                                  ((__TISEL__) == TIM_TIM24_TI1_CAN_SOC))
+
+#define IS_TIM_REMAP(__RREMAP__)     (((__RREMAP__) == TIM_TIM1_ETR_GPIO)      ||\
+                                      ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD1) ||\
+                                      ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD2) ||\
+                                      ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD3) ||\
+                                      ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD1) ||\
+                                      ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD2) ||\
+                                      ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD3) ||\
+                                      ((__RREMAP__) == TIM_TIM1_ETR_COMP1)     ||\
+                                      ((__RREMAP__) == TIM_TIM1_ETR_COMP2)     ||\
+                                      ((__RREMAP__) == TIM_TIM8_ETR_GPIO)      ||\
+                                      ((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD1) ||\
+                                      ((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD2) ||\
+                                      ((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD3) ||\
+                                      ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD1) ||\
+                                      ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD2) ||\
+                                      ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD3) ||\
+                                      ((__RREMAP__) == TIM_TIM8_ETR_COMP1)     ||\
+                                      ((__RREMAP__) == TIM_TIM8_ETR_COMP2)     ||\
+                                      ((__RREMAP__) == TIM_TIM2_ETR_GPIO)      ||\
+                                      ((__RREMAP__) == TIM_TIM2_ETR_COMP1)     ||\
+                                      ((__RREMAP__) == TIM_TIM2_ETR_COMP2)     ||\
+                                      ((__RREMAP__) == TIM_TIM2_ETR_RCC_LSE)   ||\
+                                      ((__RREMAP__) == TIM_TIM2_ETR_SAI1_FSA)  ||\
+                                      ((__RREMAP__) == TIM_TIM2_ETR_SAI1_FSB)  ||\
+                                      ((__RREMAP__) == TIM_TIM3_ETR_GPIO)      ||\
+                                      ((__RREMAP__) == TIM_TIM3_ETR_COMP1)     ||\
+                                      ((__RREMAP__) == TIM_TIM5_ETR_GPIO)      ||\
+                                      ((__RREMAP__) == TIM_TIM5_ETR_SAI2_FSA)  ||\
+                                      ((__RREMAP__) == TIM_TIM5_ETR_SAI2_FSB)  ||\
+                                      ((__RREMAP__) == TIM_TIM23_ETR_GPIO)     ||\
+                                      ((__RREMAP__) == TIM_TIM23_ETR_COMP1)    ||\
+                                      ((__RREMAP__) == TIM_TIM23_ETR_COMP2)    ||\
+                                      ((__RREMAP__) == TIM_TIM24_ETR_GPIO)     ||\
+                                      ((__RREMAP__) == TIM_TIM24_ETR_SAI4_FSA) ||\
+                                      ((__RREMAP__) == TIM_TIM24_ETR_SAI4_FSB) ||\
+                                      ((__RREMAP__) == TIM_TIM24_ETR_SAI1_FSA) ||\
+                                      ((__RREMAP__) == TIM_TIM24_ETR_SAI1_FSB))
+
+/**
+  * @}
+  */
+/* End of private macro ------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
+  * @{
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
+  *  @brief    Timer Hall Sensor functions
+  * @{
+  */
+/*  Timer Hall Sensor functions  **********************************************/
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
+
+void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
+
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
+  *  @brief   Timer Complementary Output Compare functions
+  * @{
+  */
+/*  Timer Complementary Output Compare functions  *****************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
+  *  @brief    Timer Complementary PWM functions
+  * @{
+  */
+/*  Timer Complementary PWM functions  ****************************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
+  *  @brief    Timer Complementary One Pulse functions
+  * @{
+  */
+/*  Timer Complementary One Pulse functions  **********************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
+  *  @brief    Peripheral Control functions
+  * @{
+  */
+/* Extended Control functions  ************************************************/
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                              uint32_t  CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                                 uint32_t  CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                                  uint32_t  CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+                                                        TIM_MasterConfigTypeDef *sMasterConfig);
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
+                                                TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
+#if defined(TIM_BREAK_INPUT_SUPPORT)
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput,
+                                             TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
+#endif /* TIM_BREAK_INPUT_SUPPORT */
+HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
+HAL_StatusTypeDef  HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
+  * @brief    Extended Callbacks functions
+  * @{
+  */
+/* Extended Callback **********************************************************/
+void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
+  * @brief    Extended Peripheral State functions
+  * @{
+  */
+/* Extended Peripheral State functions  ***************************************/
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private functions----------------------------------------------------------*/
+/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions
+  * @{
+  */
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
+void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+/* End of private functions --------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32H7xx_HAL_TIM_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bus.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bus.h
new file mode 100644
index 00000000..6ee1528a
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bus.h
@@ -0,0 +1,6635 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_bus.h
+  * @author  MCD Application Team
+  * @version $VERSION$
+  * @date    $DATE$
+  * @brief   Header file of BUS LL module.
+
+  @verbatim
+                      ##### RCC Limitations #####
+  ==============================================================================
+    [..]
+      A delay between an RCC peripheral clock enable and the effective peripheral
+      enabling should be taken into account in order to manage the peripheral read/write
+      from/to registers.
+      (+) This delay depends on the peripheral mapping.
+        (++) AHB & APB peripherals, 1 dummy read is necessary
+
+    [..]
+      Workarounds:
+      (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
+          inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_LL_BUS_H
+#define STM32H7xx_LL_BUS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined(RCC)
+
+/** @defgroup BUS_LL BUS
+  * @{
+  */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
+  * @{
+  */
+
+/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH  AHB3 GRP1 PERIPH
+  * @{
+  */
+#define LL_AHB3_GRP1_PERIPH_MDMA           RCC_AHB3ENR_MDMAEN
+#define LL_AHB3_GRP1_PERIPH_DMA2D          RCC_AHB3ENR_DMA2DEN
+
+#if defined(JPEG)
+#define LL_AHB3_GRP1_PERIPH_JPGDEC         RCC_AHB3ENR_JPGDECEN
+#endif /* JPEG */
+
+#define LL_AHB3_GRP1_PERIPH_FMC            RCC_AHB3ENR_FMCEN
+#if defined(QUADSPI)
+#define LL_AHB3_GRP1_PERIPH_QSPI           RCC_AHB3ENR_QSPIEN
+#endif /* QUADSPI */
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+#define LL_AHB3_GRP1_PERIPH_OSPI1          RCC_AHB3ENR_OSPI1EN
+#define LL_AHB3_GRP1_PERIPH_OSPI2          RCC_AHB3ENR_OSPI2EN
+#endif /*(OCTOSPI1) || (OCTOSPI2)*/
+#if defined(OCTOSPIM)
+#define LL_AHB3_GRP1_PERIPH_OCTOSPIM       RCC_AHB3ENR_IOMNGREN
+#endif /* OCTOSPIM */
+#if defined(OTFDEC1) || defined(OTFDEC2)
+#define LL_AHB3_GRP1_PERIPH_OTFDEC1        RCC_AHB3ENR_OTFDEC1EN
+#define LL_AHB3_GRP1_PERIPH_OTFDEC2        RCC_AHB3ENR_OTFDEC2EN
+#endif /* (OTFDEC1) || (OTFDEC2) */
+#if defined(GFXMMU)
+#define LL_AHB3_GRP1_PERIPH_GFXMMU         RCC_AHB3ENR_GFXMMUEN
+#endif /* GFXMMU */
+#define LL_AHB3_GRP1_PERIPH_SDMMC1         RCC_AHB3ENR_SDMMC1EN
+#define LL_AHB3_GRP1_PERIPH_FLASH          RCC_AHB3LPENR_FLASHLPEN
+#define LL_AHB3_GRP1_PERIPH_DTCM1          RCC_AHB3LPENR_DTCM1LPEN
+#define LL_AHB3_GRP1_PERIPH_DTCM2          RCC_AHB3LPENR_DTCM2LPEN
+#define LL_AHB3_GRP1_PERIPH_ITCM           RCC_AHB3LPENR_ITCMLPEN
+#if defined(RCC_AHB3LPENR_AXISRAMLPEN)
+#define LL_AHB3_GRP1_PERIPH_AXISRAM        RCC_AHB3LPENR_AXISRAMLPEN
+#else
+#define LL_AHB3_GRP1_PERIPH_AXISRAM1       RCC_AHB3LPENR_AXISRAM1LPEN
+#define LL_AHB3_GRP1_PERIPH_AXISRAM        LL_AHB3_GRP1_PERIPH_AXISRAM1   /* for backward compatibility*/
+#endif /* RCC_AHB3LPENR_AXISRAMLPEN */
+#if defined(CD_AXISRAM2_BASE)
+#define LL_AHB3_GRP1_PERIPH_AXISRAM2       RCC_AHB3LPENR_AXISRAM2LPEN
+#endif /* CD_AXISRAM2_BASE */
+#if defined(CD_AXISRAM3_BASE)
+#define LL_AHB3_GRP1_PERIPH_AXISRAM3       RCC_AHB3LPENR_AXISRAM3LPEN
+#endif /* CD_AXISRAM3_BASE */
+/**
+  * @}
+  */
+
+
+/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH  AHB1 GRP1 PERIPH
+  * @{
+  */
+#define LL_AHB1_GRP1_PERIPH_DMA1           RCC_AHB1ENR_DMA1EN
+#define LL_AHB1_GRP1_PERIPH_DMA2           RCC_AHB1ENR_DMA2EN
+#define LL_AHB1_GRP1_PERIPH_ADC12          RCC_AHB1ENR_ADC12EN
+#if defined(DUAL_CORE)
+#define LL_AHB1_GRP1_PERIPH_ART            RCC_AHB1ENR_ARTEN
+#endif /* DUAL_CORE */
+#if defined(RCC_AHB1ENR_CRCEN)
+#define LL_AHB1_GRP1_PERIPH_CRC            RCC_AHB1ENR_CRCEN
+#endif /* RCC_AHB1ENR_CRCEN */
+#if defined(ETH)
+#define LL_AHB1_GRP1_PERIPH_ETH1MAC        RCC_AHB1ENR_ETH1MACEN
+#define LL_AHB1_GRP1_PERIPH_ETH1TX         RCC_AHB1ENR_ETH1TXEN
+#define LL_AHB1_GRP1_PERIPH_ETH1RX         RCC_AHB1ENR_ETH1RXEN
+#endif /* ETH */
+#define LL_AHB1_GRP1_PERIPH_USB1OTGHS      RCC_AHB1ENR_USB1OTGHSEN
+#define LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI  RCC_AHB1ENR_USB1OTGHSULPIEN
+#if defined(USB2_OTG_FS)
+#define LL_AHB1_GRP1_PERIPH_USB2OTGHS      RCC_AHB1ENR_USB2OTGHSEN
+#define LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI  RCC_AHB1ENR_USB2OTGHSULPIEN
+#endif /* USB2_OTG_FS */
+/**
+  * @}
+  */
+
+
+/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH  AHB2 GRP1 PERIPH
+  * @{
+  */
+#define LL_AHB2_GRP1_PERIPH_DCMI           RCC_AHB2ENR_DCMIEN
+#if defined(HSEM) && defined(RCC_AHB2ENR_HSEMEN)
+#define LL_AHB2_GRP1_PERIPH_HSEM           RCC_AHB2ENR_HSEMEN
+#endif /* HSEM && RCC_AHB2ENR_HSEMEN */
+#if defined(CRYP)
+#define LL_AHB2_GRP1_PERIPH_CRYP           RCC_AHB2ENR_CRYPEN
+#endif /* CRYP */
+#if defined(HASH)
+#define LL_AHB2_GRP1_PERIPH_HASH           RCC_AHB2ENR_HASHEN
+#endif /* HASH */
+#define LL_AHB2_GRP1_PERIPH_RNG            RCC_AHB2ENR_RNGEN
+#define LL_AHB2_GRP1_PERIPH_SDMMC2         RCC_AHB2ENR_SDMMC2EN
+#if defined(BDMA1)
+#define LL_AHB2_GRP1_PERIPH_BDMA1          RCC_AHB2ENR_BDMA1EN
+#endif /* BDMA1 */
+#if defined(RCC_AHB2ENR_D2SRAM1EN)
+#define LL_AHB2_GRP1_PERIPH_D2SRAM1        RCC_AHB2ENR_D2SRAM1EN
+#else
+#define LL_AHB2_GRP1_PERIPH_AHBSRAM1       RCC_AHB2ENR_AHBSRAM1EN
+#define LL_AHB2_GRP1_PERIPH_D2SRAM1        LL_AHB2_GRP1_PERIPH_AHBSRAM1    /* for backward compatibility*/
+#endif /* RCC_AHB2ENR_D2SRAM1EN */
+#if defined(RCC_AHB2ENR_D2SRAM2EN)
+#define LL_AHB2_GRP1_PERIPH_D2SRAM2        RCC_AHB2ENR_D2SRAM2EN
+#else
+#define LL_AHB2_GRP1_PERIPH_AHBSRAM2       RCC_AHB2ENR_AHBSRAM2EN
+#define LL_AHB2_GRP1_PERIPH_D2SRAM2        LL_AHB2_GRP1_PERIPH_AHBSRAM2    /* for backward compatibility*/
+#endif /* RCC_AHB2ENR_D2SRAM2EN */
+#if defined(RCC_AHB2ENR_D2SRAM3EN)
+#define LL_AHB2_GRP1_PERIPH_D2SRAM3        RCC_AHB2ENR_D2SRAM3EN
+#endif /* RCC_AHB2ENR_D2SRAM3EN */
+/**
+  * @}
+  */
+
+
+/** @defgroup BUS_LL_EC_AHB4_GRP1_PERIPH  AHB4 GRP1 PERIPH
+  * @{
+  */
+#define LL_AHB4_GRP1_PERIPH_GPIOA          RCC_AHB4ENR_GPIOAEN
+#define LL_AHB4_GRP1_PERIPH_GPIOB          RCC_AHB4ENR_GPIOBEN
+#define LL_AHB4_GRP1_PERIPH_GPIOC          RCC_AHB4ENR_GPIOCEN
+#define LL_AHB4_GRP1_PERIPH_GPIOD          RCC_AHB4ENR_GPIODEN
+#define LL_AHB4_GRP1_PERIPH_GPIOE          RCC_AHB4ENR_GPIOEEN
+#define LL_AHB4_GRP1_PERIPH_GPIOF          RCC_AHB4ENR_GPIOFEN
+#define LL_AHB4_GRP1_PERIPH_GPIOG          RCC_AHB4ENR_GPIOGEN
+#define LL_AHB4_GRP1_PERIPH_GPIOH          RCC_AHB4ENR_GPIOHEN
+#define LL_AHB4_GRP1_PERIPH_GPIOI          RCC_AHB4ENR_GPIOIEN
+#define LL_AHB4_GRP1_PERIPH_GPIOJ          RCC_AHB4ENR_GPIOJEN
+#define LL_AHB4_GRP1_PERIPH_GPIOK          RCC_AHB4ENR_GPIOKEN
+#if defined(RCC_AHB4ENR_CRCEN)
+#define LL_AHB4_GRP1_PERIPH_CRC            RCC_AHB4ENR_CRCEN
+#endif /* RCC_AHB4ENR_CRCEN */
+#if defined(BDMA2)
+#define LL_AHB4_GRP1_PERIPH_BDMA2          RCC_AHB4ENR_BDMA2EN
+#define LL_AHB4_GRP1_PERIPH_BDMA           LL_AHB4_GRP1_PERIPH_BDMA2  /* for backward compatibility*/
+#else
+#define LL_AHB4_GRP1_PERIPH_BDMA           RCC_AHB4ENR_BDMAEN
+#endif /* BDMA2 */
+#if defined(ADC3)
+#define LL_AHB4_GRP1_PERIPH_ADC3           RCC_AHB4ENR_ADC3EN
+#endif /* ADC3 */
+#if defined(HSEM) && defined(RCC_AHB4ENR_HSEMEN)
+#define LL_AHB4_GRP1_PERIPH_HSEM           RCC_AHB4ENR_HSEMEN
+#endif /* HSEM && RCC_AHB4ENR_HSEMEN*/
+#define LL_AHB4_GRP1_PERIPH_BKPRAM         RCC_AHB4ENR_BKPRAMEN
+#if defined(RCC_AHB4LPENR_SRAM4LPEN)
+#define LL_AHB4_GRP1_PERIPH_SRAM4          RCC_AHB4LPENR_SRAM4LPEN
+#define LL_AHB4_GRP1_PERIPH_D3SRAM1        LL_AHB4_GRP1_PERIPH_SRAM4
+#else
+#define LL_AHB4_GRP1_PERIPH_SRDSRAM        RCC_AHB4ENR_SRDSRAMEN
+#define LL_AHB4_GRP1_PERIPH_SRAM4          LL_AHB4_GRP1_PERIPH_SRDSRAM  /* for backward compatibility*/
+#define LL_AHB4_GRP1_PERIPH_D3SRAM1        LL_AHB4_GRP1_PERIPH_SRDSRAM  /* for backward compatibility*/
+#endif /* RCC_AHB4ENR_D3SRAM1EN */
+/**
+  * @}
+  */
+
+
+/** @defgroup BUS_LL_EC_APB3_GRP1_PERIPH  APB3 GRP1 PERIPH
+  * @{
+  */
+#define LL_APB3_GRP1_PERIPH_LTDC           RCC_APB3ENR_LTDCEN
+#if defined(DSI)
+#define LL_APB3_GRP1_PERIPH_DSI            RCC_APB3ENR_DSIEN
+#endif /* DSI */
+#define LL_APB3_GRP1_PERIPH_WWDG1          RCC_APB3ENR_WWDG1EN
+#if defined(RCC_APB3ENR_WWDGEN)
+#define LL_APB3_GRP1_PERIPH_WWDG           LL_APB3_GRP1_PERIPH_WWDG1   /* for backward compatibility*/
+#endif
+/**
+  * @}
+  */
+
+
+/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH  APB1 GRP1 PERIPH
+  * @{
+  */
+#define LL_APB1_GRP1_PERIPH_TIM2           RCC_APB1LENR_TIM2EN
+#define LL_APB1_GRP1_PERIPH_TIM3           RCC_APB1LENR_TIM3EN
+#define LL_APB1_GRP1_PERIPH_TIM4           RCC_APB1LENR_TIM4EN
+#define LL_APB1_GRP1_PERIPH_TIM5           RCC_APB1LENR_TIM5EN
+#define LL_APB1_GRP1_PERIPH_TIM6           RCC_APB1LENR_TIM6EN
+#define LL_APB1_GRP1_PERIPH_TIM7           RCC_APB1LENR_TIM7EN
+#define LL_APB1_GRP1_PERIPH_TIM12          RCC_APB1LENR_TIM12EN
+#define LL_APB1_GRP1_PERIPH_TIM13          RCC_APB1LENR_TIM13EN
+#define LL_APB1_GRP1_PERIPH_TIM14          RCC_APB1LENR_TIM14EN
+#define LL_APB1_GRP1_PERIPH_LPTIM1         RCC_APB1LENR_LPTIM1EN
+#if defined(DUAL_CORE)
+#define LL_APB1_GRP1_PERIPH_WWDG2          RCC_APB1LENR_WWDG2EN
+#endif /*DUAL_CORE*/
+#define LL_APB1_GRP1_PERIPH_SPI2           RCC_APB1LENR_SPI2EN
+#define LL_APB1_GRP1_PERIPH_SPI3           RCC_APB1LENR_SPI3EN
+#define LL_APB1_GRP1_PERIPH_SPDIFRX        RCC_APB1LENR_SPDIFRXEN
+#define LL_APB1_GRP1_PERIPH_USART2         RCC_APB1LENR_USART2EN
+#define LL_APB1_GRP1_PERIPH_USART3         RCC_APB1LENR_USART3EN
+#define LL_APB1_GRP1_PERIPH_UART4          RCC_APB1LENR_UART4EN
+#define LL_APB1_GRP1_PERIPH_UART5          RCC_APB1LENR_UART5EN
+#define LL_APB1_GRP1_PERIPH_I2C1           RCC_APB1LENR_I2C1EN
+#define LL_APB1_GRP1_PERIPH_I2C2           RCC_APB1LENR_I2C2EN
+#define LL_APB1_GRP1_PERIPH_I2C3           RCC_APB1LENR_I2C3EN
+#define LL_APB1_GRP1_PERIPH_CEC            RCC_APB1LENR_CECEN
+#define LL_APB1_GRP1_PERIPH_DAC12          RCC_APB1LENR_DAC12EN
+#define LL_APB1_GRP1_PERIPH_UART7          RCC_APB1LENR_UART7EN
+#define LL_APB1_GRP1_PERIPH_UART8          RCC_APB1LENR_UART8EN
+/**
+  * @}
+  */
+
+
+/** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH  APB1 GRP2 PERIPH
+  * @{
+  */
+#define LL_APB1_GRP2_PERIPH_CRS            RCC_APB1HENR_CRSEN
+#define LL_APB1_GRP2_PERIPH_SWPMI1         RCC_APB1HENR_SWPMIEN
+#define LL_APB1_GRP2_PERIPH_OPAMP          RCC_APB1HENR_OPAMPEN
+#define LL_APB1_GRP2_PERIPH_MDIOS          RCC_APB1HENR_MDIOSEN
+#define LL_APB1_GRP2_PERIPH_FDCAN          RCC_APB1HENR_FDCANEN
+/**
+  * @}
+  */
+
+
+/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH  APB2 GRP1 PERIPH
+  * @{
+  */
+#define LL_APB2_GRP1_PERIPH_TIM1           RCC_APB2ENR_TIM1EN
+#define LL_APB2_GRP1_PERIPH_TIM8           RCC_APB2ENR_TIM8EN
+#define LL_APB2_GRP1_PERIPH_USART1         RCC_APB2ENR_USART1EN
+#define LL_APB2_GRP1_PERIPH_USART6         RCC_APB2ENR_USART6EN
+#if defined(UART9)
+#define LL_APB2_GRP1_PERIPH_UART9          RCC_APB2ENR_UART9EN
+#endif /* UART9 */
+#if defined(USART10)
+#define LL_APB2_GRP1_PERIPH_USART10        RCC_APB2ENR_USART10EN
+#endif /* USART10 */
+#define LL_APB2_GRP1_PERIPH_SPI1           RCC_APB2ENR_SPI1EN
+#define LL_APB2_GRP1_PERIPH_SPI4           RCC_APB2ENR_SPI4EN
+#define LL_APB2_GRP1_PERIPH_TIM15          RCC_APB2ENR_TIM15EN
+#define LL_APB2_GRP1_PERIPH_TIM16          RCC_APB2ENR_TIM16EN
+#define LL_APB2_GRP1_PERIPH_TIM17          RCC_APB2ENR_TIM17EN
+#define LL_APB2_GRP1_PERIPH_SPI5           RCC_APB2ENR_SPI5EN
+#define LL_APB2_GRP1_PERIPH_SAI1           RCC_APB2ENR_SAI1EN
+#define LL_APB2_GRP1_PERIPH_SAI2           RCC_APB2ENR_SAI2EN
+#if defined(SAI3)
+#define LL_APB2_GRP1_PERIPH_SAI3           RCC_APB2ENR_SAI3EN
+#endif /* SAI3 */
+#define LL_APB2_GRP1_PERIPH_DFSDM1         RCC_APB2ENR_DFSDM1EN
+#if defined(HRTIM1)
+#define LL_APB2_GRP1_PERIPH_HRTIM          RCC_APB2ENR_HRTIMEN
+#endif /* HRTIM1 */
+/**
+  * @}
+  */
+
+
+/** @defgroup BUS_LL_EC_APB4_GRP1_PERIPH  APB4 GRP1 PERIPH
+  * @{
+  */
+#define LL_APB4_GRP1_PERIPH_SYSCFG         RCC_APB4ENR_SYSCFGEN
+#define LL_APB4_GRP1_PERIPH_LPUART1        RCC_APB4ENR_LPUART1EN
+#define LL_APB4_GRP1_PERIPH_SPI6           RCC_APB4ENR_SPI6EN
+#define LL_APB4_GRP1_PERIPH_I2C4           RCC_APB4ENR_I2C4EN
+#define LL_APB4_GRP1_PERIPH_LPTIM2         RCC_APB4ENR_LPTIM2EN
+#define LL_APB4_GRP1_PERIPH_LPTIM3         RCC_APB4ENR_LPTIM3EN
+#if defined(LPTIM4)
+#define LL_APB4_GRP1_PERIPH_LPTIM4         RCC_APB4ENR_LPTIM4EN
+#endif /* LPTIM4 */
+#if defined(LPTIM5)
+#define LL_APB4_GRP1_PERIPH_LPTIM5         RCC_APB4ENR_LPTIM5EN
+#endif /* LPTIM5 */
+#if defined(DAC2)
+#define LL_APB4_GRP1_PERIPH_DAC2           RCC_APB4ENR_DAC2EN
+#endif /* DAC2 */
+#define LL_APB4_GRP1_PERIPH_COMP12         RCC_APB4ENR_COMP12EN
+#define LL_APB4_GRP1_PERIPH_VREF           RCC_APB4ENR_VREFEN
+#define LL_APB4_GRP1_PERIPH_RTCAPB         RCC_APB4ENR_RTCAPBEN
+#if defined(SAI4)
+#define LL_APB4_GRP1_PERIPH_SAI4           RCC_APB4ENR_SAI4EN
+#endif /* SAI4 */
+#if defined(DTS)
+#define LL_APB4_GRP1_PERIPH_DTS            RCC_APB4ENR_DTSEN
+#endif /*DTS*/
+#if defined(DFSDM2_BASE)
+#define LL_APB4_GRP1_PERIPH_DFSDM2         RCC_APB4ENR_DFSDM2EN
+#endif /* DFSDM2_BASE */
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EC_CLKAM_PERIPH  CLKAM PERIPH
+  * @{
+  */
+#if defined(RCC_D3AMR_BDMAAMEN)
+#define LL_CLKAM_PERIPH_BDMA          RCC_D3AMR_BDMAAMEN
+#else
+#define LL_CLKAM_PERIPH_BDMA2         RCC_SRDAMR_BDMA2AMEN
+#define LL_CLKAM_PERIPH_BDMA          LL_CLKAM_PERIPH_BDMA2 /* for backward compatibility*/
+#endif /* RCC_D3AMR_BDMAAMEN */
+#if defined(RCC_SRDAMR_GPIOAMEN)
+#define LL_CLKAM_PERIPH_GPIO          RCC_SRDAMR_GPIOAMEN
+#endif /* RCC_SRDAMR_GPIOAMEN */
+#if defined(RCC_D3AMR_LPUART1AMEN)
+#define LL_CLKAM_PERIPH_LPUART1       RCC_D3AMR_LPUART1AMEN
+#else
+#define LL_CLKAM_PERIPH_LPUART1       RCC_SRDAMR_LPUART1AMEN
+#endif /* RCC_D3AMR_LPUART1AMEN */
+#if defined(RCC_D3AMR_SPI6AMEN)
+#define LL_CLKAM_PERIPH_SPI6          RCC_D3AMR_SPI6AMEN
+#else
+#define LL_CLKAM_PERIPH_SPI6          RCC_SRDAMR_SPI6AMEN
+#endif /* RCC_D3AMR_SPI6AMEN */
+#if defined(RCC_D3AMR_I2C4AMEN)
+#define LL_CLKAM_PERIPH_I2C4          RCC_D3AMR_I2C4AMEN
+#else
+#define LL_CLKAM_PERIPH_I2C4          RCC_SRDAMR_I2C4AMEN
+#endif /* RCC_D3AMR_I2C4AMEN */
+#if defined(RCC_D3AMR_LPTIM2AMEN)
+#define LL_CLKAM_PERIPH_LPTIM2        RCC_D3AMR_LPTIM2AMEN
+#else
+#define LL_CLKAM_PERIPH_LPTIM2        RCC_SRDAMR_LPTIM2AMEN
+#endif /* RCC_D3AMR_LPTIM2AMEN */
+#if defined(RCC_D3AMR_LPTIM3AMEN)
+#define LL_CLKAM_PERIPH_LPTIM3        RCC_D3AMR_LPTIM3AMEN
+#else
+#define LL_CLKAM_PERIPH_LPTIM3        RCC_SRDAMR_LPTIM3AMEN
+#endif /* RCC_D3AMR_LPTIM3AMEN */
+#if defined(RCC_D3AMR_LPTIM4AMEN)
+#define LL_CLKAM_PERIPH_LPTIM4        RCC_D3AMR_LPTIM4AMEN
+#endif /* RCC_D3AMR_LPTIM4AMEN */
+#if defined(RCC_D3AMR_LPTIM5AMEN)
+#define LL_CLKAM_PERIPH_LPTIM5        RCC_D3AMR_LPTIM5AMEN
+#endif /* RCC_D3AMR_LPTIM5AMEN */
+#if defined(DAC2)
+#define LL_CLKAM_PERIPH_DAC2          RCC_SRDAMR_DAC2AMEN
+#endif /* DAC2 */
+#if defined(RCC_D3AMR_COMP12AMEN)
+#define LL_CLKAM_PERIPH_COMP12        RCC_D3AMR_COMP12AMEN
+#else
+#define LL_CLKAM_PERIPH_COMP12        RCC_SRDAMR_COMP12AMEN
+#endif /* RCC_D3AMR_COMP12AMEN */
+#if defined(RCC_D3AMR_VREFAMEN)
+#define LL_CLKAM_PERIPH_VREF          RCC_D3AMR_VREFAMEN
+#else
+#define LL_CLKAM_PERIPH_VREF          RCC_SRDAMR_VREFAMEN
+#endif /* RCC_D3AMR_VREFAMEN */
+#if defined(RCC_D3AMR_RTCAMEN)
+#define LL_CLKAM_PERIPH_RTC           RCC_D3AMR_RTCAMEN
+#else
+#define LL_CLKAM_PERIPH_RTC           RCC_SRDAMR_RTCAMEN
+#endif /* RCC_D3AMR_RTCAMEN */
+#if defined(RCC_D3AMR_CRCAMEN)
+#define LL_CLKAM_PERIPH_CRC           RCC_D3AMR_CRCAMEN
+#endif /* RCC_D3AMR_CRCAMEN */
+#if defined(SAI4)
+#define LL_CLKAM_PERIPH_SAI4          RCC_D3AMR_SAI4AMEN
+#endif /* SAI4 */
+#if defined(ADC3)
+#define LL_CLKAM_PERIPH_ADC3          RCC_D3AMR_ADC3AMEN
+#endif /* ADC3 */
+#if defined(DTS)
+#define LL_CLKAM_PERIPH_DTS           RCC_SRDAMR_DTSAMEN
+#endif /* DTS */
+#if defined(DFSDM2_BASE)
+#define LL_CLKAM_PERIPH_DFSDM2        RCC_SRDAMR_DFSDM2AMEN
+#endif /* DFSDM2_BASE */
+#if defined(RCC_D3AMR_BKPRAMAMEN)
+#define LL_CLKAM_PERIPH_BKPRAM        RCC_D3AMR_BKPRAMAMEN
+#else
+#define LL_CLKAM_PERIPH_BKPRAM        RCC_SRDAMR_BKPRAMAMEN
+#endif /* RCC_D3AMR_BKPRAMAMEN */
+#if defined(RCC_D3AMR_SRAM4AMEN)
+#define LL_CLKAM_PERIPH_SRAM4         RCC_D3AMR_SRAM4AMEN
+#else
+#define LL_CLKAM_PERIPH_SRDSRAM       RCC_SRDAMR_SRDSRAMAMEN
+#define LL_CLKAM_PERIPH_SRAM4         LL_CLKAM_PERIPH_SRDSRAM
+#endif /* RCC_D3AMR_SRAM4AMEN */
+/**
+  * @}
+  */
+
+#if defined(RCC_CKGAENR_AXICKG)
+/** @defgroup BUS_LL_EC_CKGA_PERIPH  CKGA (AXI Clocks Gating) PERIPH
+  * @{
+  */
+#define LL_CKGA_PERIPH_AXI            RCC_CKGAENR_AXICKG
+#define LL_CKGA_PERIPH_AHB            RCC_CKGAENR_AHBCKG
+#define LL_CKGA_PERIPH_CPU            RCC_CKGAENR_CPUCKG
+#define LL_CKGA_PERIPH_SDMMC          RCC_CKGAENR_SDMMCCKG
+#define LL_CKGA_PERIPH_MDMA           RCC_CKGAENR_MDMACKG
+#define LL_CKGA_PERIPH_DMA2D          RCC_CKGAENR_DMA2DCKG
+#define LL_CKGA_PERIPH_LTDC           RCC_CKGAENR_LTDCCKG
+#define LL_CKGA_PERIPH_GFXMMUM        RCC_CKGAENR_GFXMMUMCKG
+#define LL_CKGA_PERIPH_AHB12          RCC_CKGAENR_AHB12CKG
+#define LL_CKGA_PERIPH_AHB34          RCC_CKGAENR_AHB34CKG
+#define LL_CKGA_PERIPH_FLIFT          RCC_CKGAENR_FLIFTCKG
+#define LL_CKGA_PERIPH_OCTOSPI2       RCC_CKGAENR_OCTOSPI2CKG
+#define LL_CKGA_PERIPH_FMC            RCC_CKGAENR_FMCCKG
+#define LL_CKGA_PERIPH_OCTOSPI1       RCC_CKGAENR_OCTOSPI1CKG
+#define LL_CKGA_PERIPH_AXIRAM1        RCC_CKGAENR_AXIRAM1CKG
+#define LL_CKGA_PERIPH_AXIRAM2        RCC_CKGAENR_AXIRAM2CKG
+#define LL_CKGA_PERIPH_AXIRAM3        RCC_CKGAENR_AXIRAM3CKG
+#define LL_CKGA_PERIPH_GFXMMUS        RCC_CKGAENR_GFXMMUSCKG
+#define LL_CKGA_PERIPH_ECCRAM         RCC_CKGAENR_ECCRAMCKG
+#define LL_CKGA_PERIPH_EXTI           RCC_CKGAENR_EXTICKG
+#define LL_CKGA_PERIPH_JTAG           RCC_CKGAENR_JTAGCKG
+/**
+  * @}
+  */
+#endif /* RCC_CKGAENR_AXICKG */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
+  * @{
+  */
+
+/** @defgroup BUS_LL_EF_AHB3 AHB3
+  * @{
+  */
+
+/**
+  * @brief  Enable AHB3 peripherals clock.
+  * @rmtoll AHB3ENR      MDMAEN        LL_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      DMA2DEN       LL_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      JPGDECEN      LL_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      FMCEN         LL_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_EnableClock\n  (*)
+  *         AHB3ENR      OSPI1EN       LL_AHB3_GRP1_EnableClock\n  (*)
+  *         AHB3ENR      OSPI2EN       LL_AHB3_GRP1_EnableClock\n  (*)
+  *         AHB3ENR      IOMNGREN      LL_AHB3_GRP1_EnableClock\n  (*)
+  *         AHB3ENR      OTFDEC1EN     LL_AHB3_GRP1_EnableClock\n  (*)
+  *         AHB3ENR      OTFDEC2EN     LL_AHB3_GRP1_EnableClock\n  (*)
+  *         AHB3ENR      GFXMMU        LL_AHB3_GRP1_EnableClock\n  (*)
+  *         AHB3ENR      SDMMC1EN      LL_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      FLASHEN       LL_AHB3_GRP1_EnableClock\n  (*)
+  *         AHB3ENR      DTCM1EN       LL_AHB3_GRP1_EnableClock\n  (*)
+  *         AHB3ENR      DTCM2EN       LL_AHB3_GRP1_EnableClock\n  (*)
+  *         AHB3ENR      ITCMEN        LL_AHB3_GRP1_EnableClock\n  (*)
+  *         AHB3ENR      AXISRAMEN     LL_AHB3_GRP1_EnableClock    (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB3ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if AHB3 peripheral clock is enabled or not
+  * @rmtoll AHB3ENR      MDMAEN        LL_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      DMA2DEN       LL_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      JPGDECEN      LL_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      FMCEN         LL_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      OSPI1EN       LL_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      OSPI2EN       LL_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      IOMNGREN      LL_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      OTFDEC1EN     LL_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      OTFDEC2EN     LL_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      GFXMMU        LL_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      SDMMC1EN      LL_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      FLASHEN       LL_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      DTCM1EN       LL_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      DTCM2EN       LL_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      ITCMEN        LL_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      AXISRAMEN     LL_AHB3_GRP1_IsEnabledClock   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1   (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2   (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_IOMNGR  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable AHB3 peripherals clock.
+  * @rmtoll AHB3ENR      MDMAEN        LL_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      DMA2DEN       LL_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      JPGDECEN      LL_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      FMCEN         LL_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      OSPI1EN       LL_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      OSPI2EN       LL_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      IOMNGREN      LL_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      OTFDEC1EN     LL_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      OTFDEC2EN     LL_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      GFXMMU        LL_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      SDMMC1EN      LL_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      FLASHEN       LL_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      DTCM1EN       LL_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      DTCM2EN       LL_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      ITCMEN        LL_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      AXISRAMEN     LL_AHB3_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1   (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2   (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_IOMNGR  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB3ENR, Periphs);
+}
+
+/**
+  * @brief  Force AHB3 peripherals reset.
+  * @rmtoll AHB3RSTR     MDMARST       LL_AHB3_GRP1_ForceReset\n
+  *         AHB3RSTR     DMA2DRST      LL_AHB3_GRP1_ForceReset\n
+  *         AHB3RSTR     JPGDECRST     LL_AHB3_GRP1_ForceReset\n
+  *         AHB3RSTR     FMCRST        LL_AHB3_GRP1_ForceReset\n
+  *         AHB3RSTR     QSPIRST       LL_AHB3_GRP1_ForceReset\n (*)
+  *         AHB3RSTR     OSPI1RST      LL_AHB3_GRP1_ForceReset\n (*)
+  *         AHB3RSTR     OSPI2RST      LL_AHB3_GRP1_ForceReset\n (*)
+  *         AHB3RSTR     IOMNGRRST     LL_AHB3_GRP1_ForceReset\n (*)
+  *         AHB3RSTR     OTFDEC1RST    LL_AHB3_GRP1_ForceReset\n (*)
+  *         AHB3RSTR     OTFDEC2RST    LL_AHB3_GRP1_ForceReset\n (*)
+  *         AHB3RSTR     GFXMMURST     LL_AHB3_GRP1_ForceReset\n (*)
+  *         AHB3RSTR     SDMMC1RST     LL_AHB3_GRP1_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI     (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU   (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->AHB3RSTR, Periphs);
+}
+
+/**
+  * @brief  Release AHB3 peripherals reset.
+  * @rmtoll AHB3RSTR     MDMARST       LL_AHB3_GRP1_ReleaseReset\n
+  *         AHB3RSTR     DMA2DRST      LL_AHB3_GRP1_ReleaseReset\n
+  *         AHB3RSTR     JPGDECRST     LL_AHB3_GRP1_ReleaseReset\n
+  *         AHB3RSTR     FMCRST        LL_AHB3_GRP1_ReleaseReset\n
+  *         AHB3RSTR     QSPIRST       LL_AHB3_GRP1_ReleaseReset\n
+  *         AHB3RSTR     OSPI1RST      LL_AHB3_GRP1_ReleaseReset\n (*)
+  *         AHB3RSTR     OSPI2RST      LL_AHB3_GRP1_ReleaseReset\n (*)
+  *         AHB3RSTR     IOMNGRRST     LL_AHB3_GRP1_ReleaseReset\n (*)
+  *         AHB3RSTR     OTFDEC1RST    LL_AHB3_GRP1_ReleaseReset\n (*)
+  *         AHB3RSTR     OTFDEC2RST    LL_AHB3_GRP1_ReleaseReset\n (*)
+  *         AHB3RSTR     GFXMMURST     LL_AHB3_GRP1_ReleaseReset\n (*)
+  *         AHB3RSTR     SDMMC1RST     LL_AHB3_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI     (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU   (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB3RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable AHB3 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB3LPENR    MDMALPEN      LL_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    DMA2DLPEN     LL_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    JPGDECLPEN    LL_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    FMCLPEN       LL_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    QSPILPEN      LL_AHB3_GRP1_EnableClockSleep\n  (*)
+  *         AHB3LPENR    OSPI1LPEN     LL_AHB3_GRP1_EnableClockSleep\n  (*)
+  *         AHB3LPENR    OSPI2LPEN     LL_AHB3_GRP1_EnableClockSleep\n  (*)
+  *         AHB3LPENR    IOMNGRLPEN    LL_AHB3_GRP1_EnableClockSleep\n  (*)
+  *         AHB3LPENR    OTFDEC1LPEN   LL_AHB3_GRP1_EnableClockSleep\n  (*)
+  *         AHB3LPENR    OTFDEC1LPEN   LL_AHB3_GRP1_EnableClockSleep\n  (*)
+  *         AHB3LPENR    GFXMMULPEN    LL_AHB3_GRP1_EnableClockSleep\n  (*)
+  *         AHB3LPENR    SDMMC1LPEN    LL_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    FLASHLPEN     LL_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    DTCM1LPEN     LL_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    DTCM2LPEN     LL_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    ITCMLPEN      LL_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    AXISRAMLPEN   LL_AHB3_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI     (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU   (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB3LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable AHB3 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB3LPENR    MDMALPEN      LL_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    DMA2DLPEN     LL_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    JPGDECLPEN    LL_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    FMCLPEN       LL_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    QSPILPEN      LL_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    OSPI1LPEN     LL_AHB3_GRP1_DisableClockSleep\n  (*)
+  *         AHB3LPENR    OSPI2LPEN     LL_AHB3_GRP1_DisableClockSleep\n  (*)
+  *         AHB3LPENR    IOMNGRLPEN    LL_AHB3_GRP1_DisableClockSleep\n  (*)
+  *         AHB3LPENR    OTFDEC1LPEN   LL_AHB3_GRP1_DisableClockSleep\n  (*)
+  *         AHB3LPENR    OTFDEC1LPEN   LL_AHB3_GRP1_DisableClockSleep\n  (*)
+  *         AHB3LPENR    GFXMMULPEN    LL_AHB3_GRP1_DisableClockSleep\n  (*)
+  *         AHB3LPENR    SDMMC1LPEN    LL_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    FLASHLPEN     LL_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    DTCM1LPEN     LL_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    DTCM2LPEN     LL_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    ITCMLPEN      LL_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    AXISRAMLPEN   LL_AHB3_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI     (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU   (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB3LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_AHB1 AHB1
+  * @{
+  */
+
+/**
+  * @brief  Enable AHB1 peripherals clock.
+  * @rmtoll AHB1ENR      DMA1EN        LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      DMA2EN        LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      ADC12EN       LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      ARTEN         LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      ETH1MACEN     LL_AHB1_GRP1_EnableClock\n (*)
+  *         AHB1ENR      ETH1TXEN      LL_AHB1_GRP1_EnableClock\n (*)
+  *         AHB1ENR      ETH1RXEN      LL_AHB1_GRP1_EnableClock\n (*)
+  *         AHB1ENR      USB1OTGHSEN   LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      USB1OTGHSULPIEN  LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      USB2OTGHSEN   LL_AHB1_GRP1_EnableClock\n  (*)
+  *         AHB1ENR      USB2OTGHSULPIEN  LL_AHB1_GRP1_EnableClock (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB1ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if AHB1 peripheral clock is enabled or not
+  * @rmtoll AHB1ENR      DMA1EN        LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      DMA2EN        LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      ADC12EN       LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      ARTEN         LL_AHB1_GRP1_IsEnabledClock\n (*)
+  *         AHB1ENR      CRCEN         LL_AHB1_GRP1_IsEnabledClock\n (*)
+  *         AHB1ENR      ETH1MACEN     LL_AHB1_GRP1_IsEnabledClock\n (*)
+  *         AHB1ENR      ETH1TXEN      LL_AHB1_GRP1_IsEnabledClock\n (*)
+  *         AHB1ENR      ETH1RXEN      LL_AHB1_GRP1_IsEnabledClock\n (*)
+  *         AHB1ENR      USB1OTGHSEN   LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      USB1OTGHSULPIEN  LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      USB2OTGHSEN   LL_AHB1_GRP1_IsEnabledClock\n  (*)
+  *         AHB1ENR      USB2OTGHSULPIEN  LL_AHB1_GRP1_IsEnabledClock (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable AHB1 peripherals clock.
+  * @rmtoll AHB1ENR      DMA1EN        LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      DMA2EN        LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      ADC12EN       LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      ARTEN         LL_AHB1_GRP1_DisableClock\n (*)
+  *         AHB1ENR      ETH1MACEN     LL_AHB1_GRP1_DisableClock\n (*)
+  *         AHB1ENR      ETH1TXEN      LL_AHB1_GRP1_DisableClock\n (*)
+  *         AHB1ENR      ETH1RXEN      LL_AHB1_GRP1_DisableClock\n (*)
+  *         AHB1ENR      USB1OTGHSEN   LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      USB1OTGHSULPIEN  LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      USB2OTGHSEN   LL_AHB1_GRP1_DisableClock\n  (*)
+  *         AHB1ENR      USB2OTGHSULPIEN  LL_AHB1_GRP1_DisableClock (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB1ENR, Periphs);
+}
+
+/**
+  * @brief  Force AHB1 peripherals reset.
+  * @rmtoll AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     ADC12RST      LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     ARTRST        LL_AHB1_GRP1_ForceReset\n (*)
+  *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ForceReset\n (*)
+  *         AHB1RSTR     ETH1MACRST    LL_AHB1_GRP1_ForceReset\n (*)
+  *         AHB1RSTR     USB1OTGHSRST  LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     USB2OTGHSRST  LL_AHB1_GRP1_ForceReset   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->AHB1RSTR, Periphs);
+}
+
+/**
+  * @brief  Release AHB1 peripherals reset.
+  * @rmtoll AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     ADC12RST      LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     ARTRST        LL_AHB1_GRP1_ReleaseReset\n (*)
+  *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ReleaseReset\n (*)
+  *         AHB1RSTR     ETH1MACRST    LL_AHB1_GRP1_ReleaseReset\n (*)
+  *         AHB1RSTR     USB1OTGHSRST  LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     USB2OTGHSRST  LL_AHB1_GRP1_ReleaseReset   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB1RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable AHB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB1LPENR    DMA1LPEN      LL_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    DMA2LPEN      LL_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    ADC12LPEN     LL_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    ARTLPEN       LL_AHB1_GRP1_EnableClockSleep\n (*)
+  *         AHB1LPENR    CRCLPEN       LL_AHB1_GRP1_EnableClockSleep\n (*)
+  *         AHB1LPENR    ETH1MACLPEN   LL_AHB1_GRP1_EnableClockSleep\n (*)
+  *         AHB1LPENR    ETH1TXLPEN    LL_AHB1_GRP1_EnableClockSleep\n (*)
+  *         AHB1LPENR    ETH1RXLPEN    LL_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    USB1OTGHSLPEN  LL_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    USB1OTGHSULPILPEN  LL_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    USB2OTGHSLPEN  LL_AHB1_GRP1_EnableClockSleep\n   (*)
+  *         AHB1LPENR    USB2OTGHSULPILPEN  LL_AHB1_GRP1_EnableClockSleep (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB1LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable AHB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB1LPENR    DMA1LPEN      LL_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    DMA2LPEN      LL_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    ADC12LPEN     LL_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    ARTLPEN       LL_AHB1_GRP1_DisableClockSleep\n (*)
+  *         AHB1LPENR    CRCLPEN       LL_AHB1_GRP1_DisableClockSleep\n (*)
+  *         AHB1LPENR    ETH1MACLPEN   LL_AHB1_GRP1_DisableClockSleep\n (*)
+  *         AHB1LPENR    ETH1TXLPEN    LL_AHB1_GRP1_DisableClockSleep\n (*)
+  *         AHB1LPENR    ETH1RXLPEN    LL_AHB1_GRP1_DisableClockSleep\n (*)
+  *         AHB1LPENR    USB1OTGHSLPEN  LL_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    USB1OTGHSULPILPEN  LL_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    USB2OTGHSLPEN  LL_AHB1_GRP1_DisableClockSleep\n   (*)
+  *         AHB1LPENR    USB2OTGHSULPILPEN  LL_AHB1_GRP1_DisableClockSleep (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB1LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_AHB2 AHB2
+  * @{
+  */
+
+/**
+  * @brief  Enable AHB2 peripherals clock.
+  * @rmtoll AHB2ENR      DCMIEN        LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      HSEMEN        LL_AHB2_GRP1_EnableClock\n (*)
+  *         AHB2ENR      CRYPEN        LL_AHB2_GRP1_EnableClock\n (*)
+  *         AHB2ENR      HASHEN        LL_AHB2_GRP1_EnableClock\n (*)
+  *         AHB2ENR      RNGEN         LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      SDMMC2EN      LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      BDMA1EN       LL_AHB2_GRP1_EnableClock\n (*)
+  *         AHB2ENR      D2SRAM1EN     LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      D2SRAM2EN     LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      D2SRAM3EN     LL_AHB2_GRP1_EnableClock   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1   (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB2ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if AHB2 peripheral clock is enabled or not
+  * @rmtoll AHB2ENR      DCMIEN        LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      HSEMEN        LL_AHB2_GRP1_IsEnabledClock\n (*)
+  *         AHB2ENR      CRYPEN        LL_AHB2_GRP1_IsEnabledClock\n (*)
+  *         AHB2ENR      HASHEN        LL_AHB2_GRP1_IsEnabledClock\n (*)
+  *         AHB2ENR      RNGEN         LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      SDMMC2EN      LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      BDMA1EN       LL_AHB2_GRP1_IsEnabledClock\n (*)
+  *         AHB2ENR      D2SRAM1EN     LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      D2SRAM2EN     LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      D2SRAM3EN     LL_AHB2_GRP1_IsEnabledClock   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEMEN (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1   (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable AHB2 peripherals clock.
+  * @rmtoll AHB2ENR      DCMIEN        LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      HSEMEN        LL_AHB2_GRP1_DisableClock\n (*)
+  *         AHB2ENR      CRYPEN        LL_AHB2_GRP1_DisableClock\n (*)
+  *         AHB2ENR      HASHEN        LL_AHB2_GRP1_DisableClock\n (*)
+  *         AHB2ENR      RNGEN         LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      SDMMC2EN      LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      BDMA1EN       LL_AHB2_GRP1_DisableClock\n (*)
+  *         AHB2ENR      D2SRAM1EN     LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      D2SRAM2EN     LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      D2SRAM3EN     LL_AHB2_GRP1_DisableClock   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEMEN (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1   (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB2ENR, Periphs);
+}
+
+/**
+  * @brief  Force AHB2 peripherals reset.
+  * @rmtoll AHB2RSTR     DCMIRST       LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR     HSEMRST       LL_AHB2_GRP1_ForceReset\n (*)
+  *         AHB2RSTR     CRYPRST       LL_AHB2_GRP1_ForceReset\n (*)
+  *         AHB2RSTR     HASHRST       LL_AHB2_GRP1_ForceReset\n (*)
+  *         AHB2RSTR     RNGRST        LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR     SDMMC2RST     LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR     BDMA1RST      LL_AHB2_GRP1_ForceReset   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->AHB2RSTR, Periphs);
+}
+
+/**
+  * @brief  Release AHB2 peripherals reset.
+  * @rmtoll AHB2RSTR     DCMIRST       LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR     HSEMRST       LL_AHB2_GRP1_ReleaseReset\n (*)
+  *         AHB2RSTR     CRYPRST       LL_AHB2_GRP1_ReleaseReset\n (*)
+  *         AHB2RSTR     HASHRST       LL_AHB2_GRP1_ReleaseReset\n (*)
+  *         AHB2RSTR     RNGRST        LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR     SDMMC2RST     LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR     BDMA1RST      LL_AHB2_GRP1_ReleaseReset   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB2RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable AHB2 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB2LPENR    DCMILPEN      LL_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    CRYPLPEN      LL_AHB2_GRP1_EnableClockSleep\n (*)
+  *         AHB2LPENR    HASHLPEN      LL_AHB2_GRP1_EnableClockSleep\n (*)
+  *         AHB2LPENR    RNGLPEN       LL_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    SDMMC2LPEN    LL_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    BDMA1LPEN     LL_AHB2_GRP1_EnableClockSleep\n (*)
+  *         AHB2LPENR    D2SRAM1LPEN   LL_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    D2SRAM2LPEN   LL_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    D2SRAM3LPEN   LL_AHB2_GRP1_EnableClockSleep   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1   (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB2LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable AHB2 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB2LPENR    DCMILPEN      LL_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    CRYPLPEN      LL_AHB2_GRP1_DisableClockSleep\n (*)
+  *         AHB2LPENR    HASHLPEN      LL_AHB2_GRP1_DisableClockSleep\n (*)
+  *         AHB2LPENR    RNGLPEN       LL_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    SDMMC2LPEN    LL_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    BDMA1LPEN     LL_AHB2_GRP1_DisableClockSleep\n (*)
+  *         AHB2LPENR    D2SRAM1LPEN   LL_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    D2SRAM2LPEN   LL_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    D2SRAM3LPEN   LL_AHB2_GRP1_DisableClockSleep   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB2LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_AHB4 AHB4
+  * @{
+  */
+
+/**
+  * @brief  Enable AHB4 peripherals clock.
+  * @rmtoll AHB4ENR      GPIOAEN       LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOBEN       LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOCEN       LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIODEN       LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOEEN       LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOFEN       LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOGEN       LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOHEN       LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOIEN       LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOJEN       LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOKEN       LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      CRCEN         LL_AHB4_GRP1_EnableClock\n (*)
+  *         AHB4ENR      BDMAEN        LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      ADC3EN        LL_AHB4_GRP1_EnableClock\n (*)
+  *         AHB4ENR      HSEMEN        LL_AHB4_GRP1_EnableClock\n (*)
+  *         AHB4ENR      BKPRAMEN      LL_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      SRAM4EN       LL_AHB4_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC   (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB4_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB4ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB4ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if AHB4 peripheral clock is enabled or not
+  * @rmtoll AHB4ENR      GPIOAEN       LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOBEN       LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOCEN       LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIODEN       LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOEEN       LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOFEN       LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOGEN       LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOHEN       LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOIEN       LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOJEN       LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOKEN       LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      CRCEN         LL_AHB4_GRP1_IsEnabledClock\n (*)
+  *         AHB4ENR      BDMAEN        LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      ADC3EN        LL_AHB4_GRP1_IsEnabledClock\n (*)
+  *         AHB4ENR      HSEMEN        LL_AHB4_GRP1_IsEnabledClock\n (*)
+  *         AHB4ENR      BKPRAMEN      LL_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      SRAM4EN       LL_AHB4_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->AHB4ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable AHB4 peripherals clock.
+  * @rmtoll AHB4ENR      GPIOAEN       LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOBEN       LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOCEN       LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIODEN       LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOEEN       LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOFEN       LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOGEN       LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOHEN       LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOIEN       LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOJEN       LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOKEN       LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      CRCEN         LL_AHB4_GRP1_DisableClock\n (*)
+  *         AHB4ENR      BDMAEN        LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      ADC3EN        LL_AHB4_GRP1_DisableClock\n (*)
+  *         AHB4ENR      HSEMEN        LL_AHB4_GRP1_DisableClock\n (*)
+  *         AHB4ENR      BKPRAMEN      LL_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      SRAM4EN       LL_AHB4_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB4_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB4ENR, Periphs);
+}
+
+/**
+  * @brief  Force AHB4 peripherals reset.
+  * @rmtoll AHB4RSTR     GPIOARST      LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTR     GPIOBRST      LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTR     GPIOCRST      LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTR     GPIODRST      LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTR     GPIOERST      LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTR     GPIOFRST      LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTR     GPIOGRST      LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTR     GPIOHRST      LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTR     GPIOIRST      LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTR     GPIOJRST      LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTR     GPIOKRST      LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTR     CRCRST        LL_AHB4_GRP1_ForceReset\n (*)
+  *         AHB4RSTR     BDMARST       LL_AHB4_GRP1_ForceReset\n
+  *         AHB4RSTR     ADC3RST       LL_AHB4_GRP1_ForceReset\n (*)
+  *         AHB4RSTR     HSEMRST       LL_AHB4_GRP1_ForceReset   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB4_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->AHB4RSTR, Periphs);
+}
+
+/**
+  * @brief  Release AHB4 peripherals reset.
+  * @rmtoll AHB4RSTR     GPIOARST      LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTR     GPIOBRST      LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTR     GPIOCRST      LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTR     GPIODRST      LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTR     GPIOERST      LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTR     GPIOFRST      LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTR     GPIOGRST      LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTR     GPIOHRST      LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTR     GPIOIRST      LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTR     GPIOJRST      LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTR     GPIOKRST      LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTR     CRCRST        LL_AHB4_GRP1_ReleaseReset\n (*)
+  *         AHB4RSTR     BDMARST       LL_AHB4_GRP1_ReleaseReset\n
+  *         AHB4RSTR     ADC3RST       LL_AHB4_GRP1_ReleaseReset\n (*)
+  *         AHB4RSTR     HSEMRST       LL_AHB4_GRP1_ReleaseReset   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB4_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB4RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable AHB4 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB4LPENR    GPIOALPEN     LL_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOBLPEN     LL_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOCLPEN     LL_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIODLPEN     LL_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOELPEN     LL_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOFLPEN     LL_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOGLPEN     LL_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOHLPEN     LL_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOILPEN     LL_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOJLPEN     LL_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOKLPEN     LL_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    CRCLPEN       LL_AHB4_GRP1_EnableClockSleep\n (*)
+  *         AHB4LPENR    BDMALPEN      LL_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    ADC3LPEN      LL_AHB4_GRP1_EnableClockSleep\n (*)
+  *         AHB4LPENR    BKPRAMLPEN    LL_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    SRAM4LPEN     LL_AHB4_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB4_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB4LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB4LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable AHB4 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB4LPENR    GPIOALPEN     LL_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOBLPEN     LL_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOCLPEN     LL_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIODLPEN     LL_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOELPEN     LL_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOFLPEN     LL_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOGLPEN     LL_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOHLPEN     LL_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOILPEN     LL_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOJLPEN     LL_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOKLPEN     LL_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    CRCLPEN       LL_AHB4_GRP1_DisableClockSleep\n (*)
+  *         AHB4LPENR    BDMALPEN      LL_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    ADC3LPEN      LL_AHB4_GRP1_DisableClockSleep\n (*)
+  *         AHB4LPENR    BKPRAMLPEN    LL_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    SRAM4LPEN   LL_AHB4_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB4_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB4LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_APB3 APB3
+  * @{
+  */
+
+/**
+  * @brief  Enable APB3 peripherals clock.
+  * @rmtoll APB3ENR      LTDCEN        LL_APB3_GRP1_EnableClock\n (*)
+  *         APB3ENR      DSIEN         LL_APB3_GRP1_EnableClock\n (*)
+  *         APB3ENR      WWDG1EN       LL_APB3_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB3_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB3ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB3ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if APB3 peripheral clock is enabled or not
+  * @rmtoll APB3ENR      LTDCEN        LL_APB3_GRP1_IsEnabledClock\n (*)
+  *         APB3ENR      DSIEN         LL_APB3_GRP1_IsEnabledClock\n (*)
+  *         APB3ENR      WWDG1EN       LL_APB3_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->APB3ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable APB3 peripherals clock.
+  * @rmtoll APB3ENR      LTDCEN        LL_APB3_GRP1_DisableClock\n
+  *         APB3ENR      DSIEN         LL_APB3_GRP1_DisableClock\n
+  *         APB3ENR      WWDG1EN       LL_APB3_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB3_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB3ENR, Periphs);
+}
+
+/**
+  * @brief  Force APB3 peripherals reset.
+  * @rmtoll APB3RSTR     LTDCRST       LL_APB3_GRP1_ForceReset\n (*)
+  *         APB3RSTR     DSIRST        LL_APB3_GRP1_ForceReset   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB3_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->APB3RSTR, Periphs);
+}
+
+/**
+  * @brief  Release APB3 peripherals reset.
+  * @rmtoll APB3RSTR     LTDCRST       LL_APB3_GRP1_ReleaseReset\n
+  *         APB3RSTR     DSIRST        LL_APB3_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB3_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB3RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable APB3 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB3LPENR    LTDCLPEN      LL_APB3_GRP1_EnableClockSleep\n (*)
+  *         APB3LPENR    DSILPEN       LL_APB3_GRP1_EnableClockSleep\n (*)
+  *         APB3LPENR    WWDG1LPEN     LL_APB3_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB3_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB3LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB3LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable APB3 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB3LPENR    LTDCLPEN      LL_APB3_GRP1_DisableClockSleep\n (*)
+  *         APB3LPENR    DSILPEN       LL_APB3_GRP1_DisableClockSleep\n (*)
+  *         APB3LPENR    WWDG1LPEN     LL_APB3_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB3_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB3LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_APB1 APB1
+  * @{
+  */
+
+/**
+  * @brief  Enable APB1 peripherals clock.
+  * @rmtoll APB1LENR     TIM2EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM3EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM4EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM5EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM6EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM7EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM12EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM13EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM14EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     LPTIM1EN      LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     WWDG2EN       LL_APB1_GRP1_EnableClock\n (*)
+  *         APB1LENR     SPI2EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     SPI3EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     SPDIFRXEN     LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     USART2EN      LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     USART3EN      LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     UART4EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     UART5EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     I2C1EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     I2C2EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     I2C3EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     CECEN         LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     DAC12EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     UART7EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1LENR     UART8EN       LL_APB1_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB1LENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB1LENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if APB1 peripheral clock is enabled or not
+  * @rmtoll APB1LENR     TIM2EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM3EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM4EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM5EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM6EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM7EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM12EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM13EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM14EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     LPTIM1EN      LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     WWDG2EN       LL_APB1_GRP1_IsEnabledClock\n (*)
+  *         APB1LENR     SPI2EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     SPI3EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     SPDIFRXEN     LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     USART2EN      LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     USART3EN      LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     UART4EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     UART5EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     I2C1EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     I2C2EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     I2C3EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     CECEN         LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     DAC12EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     UART7EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     UART8EN       LL_APB1_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->APB1LENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable APB1 peripherals clock.
+  * @rmtoll APB1LENR     TIM2EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM3EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM4EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM5EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM6EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM7EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM12EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM13EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM14EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     LPTIM1EN      LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     WWDG2EN       LL_APB1_GRP1_DisableClock\n (*)
+  *         APB1LENR     SPI2EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     SPI3EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     SPDIFRXEN     LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     USART2EN      LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     USART3EN      LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     UART4EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     UART5EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     I2C1EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     I2C2EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     I2C3EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     CECEN         LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     DAC12EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     UART7EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1LENR     UART8EN       LL_APB1_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB1LENR, Periphs);
+}
+
+/**
+  * @brief  Force APB1 peripherals reset.
+  * @rmtoll APB1LRSTR    TIM2RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    TIM3RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    TIM4RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    TIM5RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    TIM6RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    TIM7RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    TIM12RST      LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    TIM13RST      LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    TIM14RST      LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    LPTIM1RST     LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    SPI2RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    SPI3RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    SPDIFRXRST    LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    USART2RST     LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    USART3RST     LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    UART4RST      LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    UART5RST      LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    I2C1RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    I2C2RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    I2C3RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    CECRST        LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    DAC12RST      LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    UART7RST      LL_APB1_GRP1_ForceReset\n
+  *         APB1LRSTR    UART8RST      LL_APB1_GRP1_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->APB1LRSTR, Periphs);
+}
+
+/**
+  * @brief  Release APB1 peripherals reset.
+  * @rmtoll APB1LRSTR    TIM2RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    TIM3RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    TIM4RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    TIM5RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    TIM6RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    TIM7RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    TIM12RST      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    TIM13RST      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    TIM14RST      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    LPTIM1RST     LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    SPI2RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    SPI3RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    SPDIFRXRST    LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    USART2RST     LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    USART3RST     LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    UART4RST      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    UART5RST      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    I2C1RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    I2C2RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    I2C3RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    CECRST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    DAC12RST      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    UART7RST      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1LRSTR    UART8RST      LL_APB1_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB1LRSTR, Periphs);
+}
+
+/**
+  * @brief  Enable APB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB1LLPENR   TIM2LPEN      LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM3LPEN      LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM4LPEN      LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM5LPEN      LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM6LPEN      LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM7LPEN      LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM12LPEN     LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM13LPEN     LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM14LPEN     LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   LPTIM1LPEN    LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   WWDG2LPEN     LL_APB1_GRP1_EnableClockSleep\n (*)
+  *         APB1LLPENR   SPI2LPEN      LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   SPI3LPEN      LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   SPDIFRXLPEN   LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   USART2LPEN    LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   USART3LPEN    LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   UART4LPEN     LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   UART5LPEN     LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   I2C1LPEN      LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   I2C2LPEN      LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   I2C3LPEN      LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   CECLPEN       LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   DAC12LPEN     LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   UART7LPEN     LL_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   UART8LPEN     LL_APB1_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB1LLPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB1LLPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable APB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB1LLPENR   TIM2LPEN      LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM3LPEN      LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM4LPEN      LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM5LPEN      LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM6LPEN      LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM7LPEN      LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM12LPEN     LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM13LPEN     LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM14LPEN     LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   LPTIM1LPEN    LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   WWDG2LPEN     LL_APB1_GRP1_DisableClockSleep\n (*)
+  *         APB1LLPENR   SPI2LPEN      LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   SPI3LPEN      LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   SPDIFRXLPEN   LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   USART2LPEN    LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   USART3LPEN    LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   UART4LPEN     LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   UART5LPEN     LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   I2C1LPEN      LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   I2C2LPEN      LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   I2C3LPEN      LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   CECLPEN       LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   DAC12LPEN     LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   UART7LPEN     LL_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   UART8LPEN     LL_APB1_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB1LLPENR, Periphs);
+}
+
+/**
+  * @brief  Enable APB1 peripherals clock.
+  * @rmtoll APB1HENR     CRSEN         LL_APB1_GRP2_EnableClock\n
+  *         APB1HENR     SWPMIEN       LL_APB1_GRP2_EnableClock\n
+  *         APB1HENR     OPAMPEN       LL_APB1_GRP2_EnableClock\n
+  *         APB1HENR     MDIOSEN       LL_APB1_GRP2_EnableClock\n
+  *         APB1HENR     FDCANEN       LL_APB1_GRP2_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB1HENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB1HENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if APB1 peripheral clock is enabled or not
+  * @rmtoll APB1HENR     CRSEN         LL_APB1_GRP2_IsEnabledClock\n
+  *         APB1HENR     SWPMIEN       LL_APB1_GRP2_IsEnabledClock\n
+  *         APB1HENR     OPAMPEN       LL_APB1_GRP2_IsEnabledClock\n
+  *         APB1HENR     MDIOSEN       LL_APB1_GRP2_IsEnabledClock\n
+  *         APB1HENR     FDCANEN       LL_APB1_GRP2_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->APB1HENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable APB1 peripherals clock.
+  * @rmtoll APB1HENR     CRSEN         LL_APB1_GRP2_DisableClock\n
+  *         APB1HENR     SWPMIEN       LL_APB1_GRP2_DisableClock\n
+  *         APB1HENR     OPAMPEN       LL_APB1_GRP2_DisableClock\n
+  *         APB1HENR     MDIOSEN       LL_APB1_GRP2_DisableClock\n
+  *         APB1HENR     FDCANEN       LL_APB1_GRP2_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB1HENR, Periphs);
+}
+
+/**
+  * @brief  Force APB1 peripherals reset.
+  * @rmtoll APB1HRSTR    CRSRST        LL_APB1_GRP2_ForceReset\n
+  *         APB1HRSTR    SWPMIRST      LL_APB1_GRP2_ForceReset\n
+  *         APB1HRSTR    OPAMPRST      LL_APB1_GRP2_ForceReset\n
+  *         APB1HRSTR    MDIOSRST      LL_APB1_GRP2_ForceReset\n
+  *         APB1HRSTR    FDCANRST      LL_APB1_GRP2_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->APB1HRSTR, Periphs);
+}
+
+/**
+  * @brief  Release APB1 peripherals reset.
+  * @rmtoll APB1HRSTR    CRSRST        LL_APB1_GRP2_ReleaseReset\n
+  *         APB1HRSTR    SWPMIRST      LL_APB1_GRP2_ReleaseReset\n
+  *         APB1HRSTR    OPAMPRST      LL_APB1_GRP2_ReleaseReset\n
+  *         APB1HRSTR    MDIOSRST      LL_APB1_GRP2_ReleaseReset\n
+  *         APB1HRSTR    FDCANRST      LL_APB1_GRP2_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB1HRSTR, Periphs);
+}
+
+/**
+  * @brief  Enable APB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB1HLPENR   CRSLPEN       LL_APB1_GRP2_EnableClockSleep\n
+  *         APB1HLPENR   SWPMILPEN     LL_APB1_GRP2_EnableClockSleep\n
+  *         APB1HLPENR   OPAMPLPEN     LL_APB1_GRP2_EnableClockSleep\n
+  *         APB1HLPENR   MDIOSLPEN     LL_APB1_GRP2_EnableClockSleep\n
+  *         APB1HLPENR   FDCANLPEN     LL_APB1_GRP2_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP2_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB1HLPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB1HLPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable APB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB1HLPENR   CRSLPEN       LL_APB1_GRP2_DisableClockSleep\n
+  *         APB1HLPENR   SWPMILPEN     LL_APB1_GRP2_DisableClockSleep\n
+  *         APB1HLPENR   OPAMPLPEN     LL_APB1_GRP2_DisableClockSleep\n
+  *         APB1HLPENR   MDIOSLPEN     LL_APB1_GRP2_DisableClockSleep\n
+  *         APB1HLPENR   FDCANLPEN     LL_APB1_GRP2_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP2_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB1HLPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_APB2 APB2
+  * @{
+  */
+
+/**
+  * @brief  Enable APB2 peripherals clock.
+  * @rmtoll APB2ENR      TIM1EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM8EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      USART1EN      LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      USART6EN      LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      UART9EN       LL_APB2_GRP1_EnableClock\n (*)
+  *         APB2ENR      USART10EN     LL_APB2_GRP1_EnableClock\n (*)
+  *         APB2ENR      SPI1EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SPI4EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM15EN       LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM16EN       LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM17EN       LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SPI5EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SAI1EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SAI2EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SAI3EN        LL_APB2_GRP1_EnableClock\n (*)
+  *         APB2ENR      DFSDM1EN      LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR      HRTIMEN       LL_APB2_GRP1_EnableClock   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB2ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if APB2 peripheral clock is enabled or not
+  * @rmtoll APB2ENR      TIM1EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM8EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      USART1EN      LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      USART6EN      LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      UART9EN       LL_APB2_GRP1_IsEnabledClock\n (*)
+  *         APB2ENR      USART10EN     LL_APB2_GRP1_IsEnabledClock\n (*)
+  *         APB2ENR      SPI1EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SPI4EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM15EN       LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM16EN       LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM17EN       LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SPI5EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SAI1EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SAI2EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SAI3EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      DFSDM1EN      LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      HRTIMEN       LL_APB2_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable APB2 peripherals clock.
+  * @rmtoll APB2ENR      TIM1EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM8EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      USART1EN      LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      USART6EN      LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      UART9EN       LL_APB2_GRP1_DisableClock\n (*)
+  *         APB2ENR      USART10EN     LL_APB2_GRP1_DisableClock\n (*)
+  *         APB2ENR      SPI1EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SPI4EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM15EN       LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM16EN       LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM17EN       LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SPI5EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SAI1EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SAI2EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SAI3EN        LL_APB2_GRP1_DisableClock\n (*)
+  *         APB2ENR      DFSDM1EN      LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR      HRTIMEN       LL_APB2_GRP1_DisableClock   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB2ENR, Periphs);
+}
+
+/**
+  * @brief  Force APB2 peripherals reset.
+  * @rmtoll APB2RSTR     TIM1RST       LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     TIM8RST       LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     USART1RST     LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     USART6RST     LL_APB2_GRP1_ForceReset\n
+  *         APB2ENR      UART9RST      LL_APB2_GRP1_ForceReset\n (*)
+  *         APB2ENR      USART10RST    LL_APB2_GRP1_ForceReset\n (*)
+  *         APB2RSTR     SPI1RST       LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     SPI4RST       LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     TIM15RST      LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     TIM16RST      LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     TIM17RST      LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     SPI5RST       LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     SAI1RST       LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     SAI2RST       LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     SAI3RST       LL_APB2_GRP1_ForceReset\n (*)
+  *         APB2RSTR     DFSDM1RST     LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     HRTIMRST      LL_APB2_GRP1_ForceReset   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3   (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM  (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->APB2RSTR, Periphs);
+}
+
+/**
+  * @brief  Release APB2 peripherals reset.
+  * @rmtoll APB2RSTR     TIM1RST       LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     TIM8RST       LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     USART1RST     LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     USART6RST     LL_APB2_GRP1_ReleaseReset\n
+  *         APB2ENR      UART9RST      LL_APB2_GRP1_ReleaseReset\n (*)
+  *         APB2ENR      USART10RST    LL_APB2_GRP1_ReleaseReset\n (*)
+  *         APB2RSTR     SPI1RST       LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     SPI4RST       LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     TIM15RST      LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     TIM16RST      LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     TIM17RST      LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     SPI5RST       LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     SAI1RST       LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     SAI2RST       LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     SAI3RST       LL_APB2_GRP1_ReleaseReset\n (*)
+  *         APB2RSTR     DFSDM1RST     LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     HRTIMRST      LL_APB2_GRP1_ReleaseReset   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3   (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM  (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB2RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable APB2 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB2LPENR    TIM1LPEN      LL_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    TIM8LPEN      LL_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    USART1LPEN    LL_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    USART6LPEN    LL_APB2_GRP1_EnableClockSleep\n
+  *         APB2ENR      UART9LPEN     LL_APB2_GRP1_EnableClockSleep\n (*)
+  *         APB2ENR      USART10LPEN   LL_APB2_GRP1_EnableClockSleep\n (*)
+  *         APB2LPENR    SPI1LPEN      LL_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SPI4LPEN      LL_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    TIM15LPEN     LL_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    TIM16LPEN     LL_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    TIM17LPEN     LL_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SPI5LPEN      LL_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SAI1LPEN      LL_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SAI2LPEN      LL_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SAI3LPEN      LL_APB2_GRP1_EnableClockSleep\n (*)
+  *         APB2LPENR    DFSDM1LPEN    LL_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    HRTIMLPEN     LL_APB2_GRP1_EnableClockSleep   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB2LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB2LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable APB2 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB2LPENR    TIM1LPEN      LL_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    TIM8LPEN      LL_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    USART1LPEN    LL_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    USART6LPEN    LL_APB2_GRP1_DisableClockSleep\n
+  *         APB2ENR      UART9LPEN     LL_APB2_GRP1_DisableClockSleep\n (*)
+  *         APB2ENR      USART10LPEN   LL_APB2_GRP1_DisableClockSleep\n (*)
+  *         APB2LPENR    SPI1LPEN      LL_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SPI4LPEN      LL_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    TIM15LPEN     LL_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    TIM16LPEN     LL_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    TIM17LPEN     LL_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SPI5LPEN      LL_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SAI1LPEN      LL_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SAI2LPEN      LL_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SAI3LPEN      LL_APB2_GRP1_DisableClockSleep\n (*)
+  *         APB2LPENR    DFSDM1LPEN    LL_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    HRTIMLPEN     LL_APB2_GRP1_DisableClockSleep   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB2LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_APB4 APB4
+  * @{
+  */
+
+/**
+  * @brief  Enable APB4 peripherals clock.
+  * @rmtoll APB4ENR      SYSCFGEN      LL_APB4_GRP1_EnableClock\n
+  *         APB4ENR      LPUART1EN     LL_APB4_GRP1_EnableClock\n
+  *         APB4ENR      SPI6EN        LL_APB4_GRP1_EnableClock\n
+  *         APB4ENR      I2C4EN        LL_APB4_GRP1_EnableClock\n
+  *         APB4ENR      LPTIM2EN      LL_APB4_GRP1_EnableClock\n
+  *         APB4ENR      LPTIM3EN      LL_APB4_GRP1_EnableClock\n
+  *         APB4ENR      LPTIM4EN      LL_APB4_GRP1_EnableClock\n  (*)
+  *         APB4ENR      LPTIM5EN      LL_APB4_GRP1_EnableClock\n  (*)
+  *         APB4ENR      DAC2EN        LL_APB4_GRP1_EnableClock\n  (*)
+  *         APB4ENR      COMP12EN      LL_APB4_GRP1_EnableClock\n
+  *         APB4ENR      VREFEN        LL_APB4_GRP1_EnableClock\n
+  *         APB4ENR      RTCAPBEN      LL_APB4_GRP1_EnableClock\n
+  *         APB4ENR      SAI4EN        LL_APB4_GRP1_EnableClock\n  (*)
+  *         APB4ENR      DTSEN         LL_APB4_GRP1_EnableClock\n  (*)
+  *         APB4ENR      DFSDM2EN      LL_APB4_GRP1_EnableClock    (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DAC2   (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB4_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB4ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB4ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if APB4 peripheral clock is enabled or not
+  * @rmtoll APB4ENR      SYSCFGEN      LL_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      LPUART1EN     LL_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      SPI6EN        LL_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      I2C4EN        LL_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      LPTIM2EN      LL_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      LPTIM3EN      LL_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      LPTIM4EN      LL_APB4_GRP1_IsEnabledClock\n (*)
+  *         APB4ENR      LPTIM5EN      LL_APB4_GRP1_IsEnabledClock\n (*)
+  *         APB4ENR      DAC2EN        LL_APB4_GRP1_IsEnabledClock\n (*)
+  *         APB4ENR      COMP12EN      LL_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      VREFEN        LL_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      RTCAPBEN      LL_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      SAI4EN        LL_APB4_GRP1_IsEnabledClock\n (*)
+  *         APB4ENR      DTSEN         LL_APB4_GRP1_IsEnabledClock\n (*)
+  *         APB4ENR      DFSDM2EN      LL_APB4_GRP1_IsEnabledClock   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DAC2   (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_APB4_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC->APB4ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable APB4 peripherals clock.
+  * @rmtoll APB4ENR      SYSCFGEN      LL_APB4_GRP1_DisableClock\n
+  *         APB4ENR      LPUART1EN     LL_APB4_GRP1_DisableClock\n
+  *         APB4ENR      SPI6EN        LL_APB4_GRP1_DisableClock\n
+  *         APB4ENR      I2C4EN        LL_APB4_GRP1_DisableClock\n
+  *         APB4ENR      LPTIM2EN      LL_APB4_GRP1_DisableClock\n
+  *         APB4ENR      LPTIM3EN      LL_APB4_GRP1_DisableClock\n
+  *         APB4ENR      LPTIM4EN      LL_APB4_GRP1_DisableClock\n  (*)
+  *         APB4ENR      LPTIM5EN      LL_APB4_GRP1_DisableClock\n  (*)
+  *         APB4ENR      DAC2EN        LL_APB4_GRP1_DisableClock\n  (*)
+  *         APB4ENR      COMP12EN      LL_APB4_GRP1_DisableClock\n
+  *         APB4ENR      VREFEN        LL_APB4_GRP1_DisableClock\n
+  *         APB4ENR      RTCAPBEN      LL_APB4_GRP1_DisableClock\n
+  *         APB4ENR      SAI4EN        LL_APB4_GRP1_DisableClock\n  (*)
+  *         APB4ENR      DTSEN         LL_APB4_GRP1_DisableClock\n  (*)
+  *         APB4ENR      DFSDM2EN      LL_APB4_GRP1_DisableClock    (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DAC2   (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB4_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB4ENR, Periphs);
+}
+
+/**
+  * @brief  Force APB4 peripherals reset.
+  * @rmtoll APB4RSTR     SYSCFGRST     LL_APB4_GRP1_ForceReset\n
+  *         APB4RSTR     LPUART1RST    LL_APB4_GRP1_ForceReset\n
+  *         APB4RSTR     SPI6RST       LL_APB4_GRP1_ForceReset\n
+  *         APB4RSTR     I2C4RST       LL_APB4_GRP1_ForceReset\n
+  *         APB4RSTR     LPTIM2RST     LL_APB4_GRP1_ForceReset\n
+  *         APB4RSTR     LPTIM3RST     LL_APB4_GRP1_ForceReset\n
+  *         APB4RSTR     LPTIM4RST     LL_APB4_GRP1_ForceReset\n  (*)
+  *         APB4RSTR     LPTIM5RST     LL_APB4_GRP1_ForceReset\n  (*)
+  *         APB4RSTR     DAC2EN        LL_APB4_GRP1_ForceReset\n  (*)
+  *         APB4RSTR     COMP12RST     LL_APB4_GRP1_ForceReset\n
+  *         APB4RSTR     VREFRST       LL_APB4_GRP1_ForceReset\n
+  *         APB4RSTR     SAI4RST       LL_APB4_GRP1_ForceReset\n  (*)
+  *         APB4RSTR     DTSRST        LL_APB4_GRP1_ForceReset\n  (*)
+  *         APB4RSTR      DFSDM2RST    LL_APB4_GRP1_ForceReset    (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DAC2   (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB4_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->APB4RSTR, Periphs);
+}
+
+/**
+  * @brief  Release APB4 peripherals reset.
+  * @rmtoll APB4RSTR     SYSCFGRST     LL_APB4_GRP1_ReleaseReset\n
+  *         APB4RSTR     LPUART1RST    LL_APB4_GRP1_ReleaseReset\n
+  *         APB4RSTR     SPI6RST       LL_APB4_GRP1_ReleaseReset\n
+  *         APB4RSTR     I2C4RST       LL_APB4_GRP1_ReleaseReset\n
+  *         APB4RSTR     LPTIM2RST     LL_APB4_GRP1_ReleaseReset\n
+  *         APB4RSTR     LPTIM3RST     LL_APB4_GRP1_ReleaseReset\n
+  *         APB4RSTR     LPTIM4RST     LL_APB4_GRP1_ReleaseReset\n  (*)
+  *         APB4RSTR     LPTIM5RST     LL_APB4_GRP1_ReleaseReset\n  (*)
+  *         APB4RSTR     DAC2RST       LL_APB4_GRP1_ReleaseReset\n  (*)
+  *         APB4RSTR     COMP12RST     LL_APB4_GRP1_ReleaseReset\n
+  *         APB4RSTR     VREFRST       LL_APB4_GRP1_ReleaseReset\n
+  *         APB4RSTR     SAI4RST       LL_APB4_GRP1_ReleaseReset\n
+  *         APB4RSTR     DTSRST        LL_APB4_GRP1_ReleaseReset\n  (*)
+  *         APB4RSTR     DFSDM2RST     LL_APB4_GRP1_ReleaseReset    (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DAC2   (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB4_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB4RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable APB4 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB4LPENR    SYSCFGLPEN    LL_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    LPUART1LPEN   LL_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    SPI6LPEN      LL_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    I2C4LPEN      LL_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    LPTIM2LPEN    LL_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    LPTIM3LPEN    LL_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    LPTIM4LPEN    LL_APB4_GRP1_EnableClockSleep\n (*)
+  *         APB4LPENR    LPTIM5LPEN    LL_APB4_GRP1_EnableClockSleep\n (*)
+  *         APB4LPENR    DAC2LPEN      LL_APB4_GRP1_EnableClockSleep\n (*)
+  *         APB4LPENR    COMP12LPEN    LL_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    VREFLPEN      LL_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    RTCAPBLPEN    LL_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    SAI4LPEN      LL_APB4_GRP1_EnableClockSleep\n (*)
+  *         APB4LPENR    DTSLPEN       LL_APB4_GRP1_EnableClockSleep\n (*)
+  *         APB4LPENR    DFSDM2LPEN    LL_APB4_GRP1_EnableClockSleep   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DAC2   (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB4_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB4LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB4LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable APB4 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB4LPENR    SYSCFGLPEN    LL_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    LPUART1LPEN   LL_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    SPI6LPEN      LL_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    I2C4LPEN      LL_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    LPTIM2LPEN    LL_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    LPTIM3LPEN    LL_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    LPTIM4LPEN    LL_APB4_GRP1_DisableClockSleep\n (*)
+  *         APB4LPENR    LPTIM5LPEN    LL_APB4_GRP1_DisableClockSleep\n (*)
+  *         APB4LPENR    DAC2LPEN      LL_APB4_GRP1_DisableClockSleep\n (*)
+  *         APB4LPENR    COMP12LPEN    LL_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    VREFLPEN      LL_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    RTCAPBLPEN    LL_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    SAI4LPEN      LL_APB4_GRP1_DisableClockSleep\n (*)
+  *         APB4LPENR    DTSLPEN       LL_APB4_GRP1_DisableClockSleep\n (*)
+  *         APB4LPENR    DFSDM2LPEN    LL_APB4_GRP1_DisableClockSleep   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DAC2   (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB4_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB4LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_CLKAM
+  * @{
+  */
+
+/**
+  * @brief  Enable peripherals clock for CLKAM Mode.
+  * @rmtoll D3AMR / SRDAMR         BDMA          LL_CLKAM_Enable\n
+  *         D3AMR / SRDAMR         LPUART1       LL_CLKAM_Enable\n
+  *         D3AMR / SRDAMR         SPI6          LL_CLKAM_Enable\n
+  *         D3AMR / SRDAMR         I2C4          LL_CLKAM_Enable\n
+  *         D3AMR / SRDAMR         LPTIM2        LL_CLKAM_Enable\n
+  *         D3AMR / SRDAMR         LPTIM3        LL_CLKAM_Enable\n
+  *         D3AMR / SRDAMR         LPTIM4        LL_CLKAM_Enable\n  (*)
+  *         D3AMR / SRDAMR         LPTIM5        LL_CLKAM_Enable\n  (*)
+  *         D3AMR / SRDAMR         DAC2          LL_CLKAM_Enable\n  (*)
+  *         D3AMR / SRDAMR         COMP12        LL_CLKAM_Enable\n
+  *         D3AMR / SRDAMR         VREF          LL_CLKAM_Enable\n
+  *         D3AMR / SRDAMR         RTC           LL_CLKAM_Enable\n
+  *         D3AMR / SRDAMR         CRC           LL_CLKAM_Enable\n
+  *         D3AMR / SRDAMR         SAI4          LL_CLKAM_Enable\n  (*)
+  *         D3AMR / SRDAMR         ADC3          LL_CLKAM_Enable\n  (*)
+  *         D3AMR / SRDAMR         DTS           LL_CLKAM_Enable\n  (*)
+  *         D3AMR / SRDAMR         DFSDM2        LL_CLKAM_Enable\n  (*)
+  *         D3AMR / SRDAMR         BKPRAM        LL_CLKAM_Enable\n
+  *         D3AMR / SRDAMR         SRAM4         LL_CLKAM_Enable
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_CLKAM_PERIPH_BDMA
+  *         @arg @ref LL_CLKAM_PERIPH_LPUART1
+  *         @arg @ref LL_CLKAM_PERIPH_SPI6
+  *         @arg @ref LL_CLKAM_PERIPH_I2C4
+  *         @arg @ref LL_CLKAM_PERIPH_LPTIM2
+  *         @arg @ref LL_CLKAM_PERIPH_LPTIM3
+  *         @arg @ref LL_CLKAM_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_CLKAM_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_CLKAM_PERIPH_DAC2   (*)
+  *         @arg @ref LL_CLKAM_PERIPH_COMP12
+  *         @arg @ref LL_CLKAM_PERIPH_VREF
+  *         @arg @ref LL_CLKAM_PERIPH_RTC
+  *         @arg @ref LL_CLKAM_PERIPH_CRC
+  *         @arg @ref LL_CLKAM_PERIPH_SAI4   (*)
+  *         @arg @ref LL_CLKAM_PERIPH_ADC3   (*)
+  *         @arg @ref LL_CLKAM_PERIPH_DTS    (*)
+  *         @arg @ref LL_CLKAM_PERIPH_DFSDM2 (*)
+  *         @arg @ref LL_CLKAM_PERIPH_BKPRAM
+  *         @arg @ref LL_CLKAM_PERIPH_SRAM4
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_CLKAM_Enable(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+
+#if defined(RCC_D3AMR_BDMAAMEN)
+  SET_BIT(RCC->D3AMR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->D3AMR, Periphs);
+#else
+  SET_BIT(RCC->SRDAMR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->SRDAMR, Periphs);
+#endif /* RCC_D3AMR_BDMAAMEN */
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable peripherals clock for CLKAM Mode.
+  * @rmtoll D3AMR / SRDAMR        BDMA          LL_CLKAM_Disable\n
+  *         D3AMR / SRDAMR        LPUART1       LL_CLKAM_Disable\n
+  *         D3AMR / SRDAMR        SPI6          LL_CLKAM_Disable\n
+  *         D3AMR / SRDAMR        I2C4          LL_CLKAM_Disable\n
+  *         D3AMR / SRDAMR        LPTIM2        LL_CLKAM_Disable\n
+  *         D3AMR / SRDAMR        LPTIM3        LL_CLKAM_Disable\n
+  *         D3AMR / SRDAMR        LPTIM4        LL_CLKAM_Disable\n (*)
+  *         D3AMR / SRDAMR        LPTIM5        LL_CLKAM_Disable\n (*)
+  *         D3AMR / SRDAMR        DAC2          LL_CLKAM_Disable\n (*)
+  *         D3AMR / SRDAMR        COMP12        LL_CLKAM_Disable\n
+  *         D3AMR / SRDAMR        VREF          LL_CLKAM_Disable\n
+  *         D3AMR / SRDAMR        RTC           LL_CLKAM_Disable\n
+  *         D3AMR / SRDAMR        CRC           LL_CLKAM_Disable\n
+  *         D3AMR / SRDAMR        SAI4          LL_CLKAM_Disable\n (*)
+  *         D3AMR / SRDAMR        ADC3          LL_CLKAM_Disable\n (*)
+  *         D3AMR / SRDAMR        DTS           LL_CLKAM_Disable\n (*)
+  *         D3AMR / SRDAMR        DFSDM2        LL_CLKAM_Disable\n (*)
+  *         D3AMR / SRDAMR        BKPRAM        LL_CLKAM_Disable\n
+  *         D3AMR / SRDAMR        SRAM4         LL_CLKAM_Disable
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_CLKAM_PERIPH_BDMA
+  *         @arg @ref LL_CLKAM_PERIPH_LPUART1
+  *         @arg @ref LL_CLKAM_PERIPH_SPI6
+  *         @arg @ref LL_CLKAM_PERIPH_I2C4
+  *         @arg @ref LL_CLKAM_PERIPH_LPTIM2
+  *         @arg @ref LL_CLKAM_PERIPH_LPTIM3
+  *         @arg @ref LL_CLKAM_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_CLKAM_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_CLKAM_PERIPH_DAC2   (*)
+  *         @arg @ref LL_CLKAM_PERIPH_COMP12
+  *         @arg @ref LL_CLKAM_PERIPH_VREF
+  *         @arg @ref LL_CLKAM_PERIPH_RTC
+  *         @arg @ref LL_CLKAM_PERIPH_CRC
+  *         @arg @ref LL_CLKAM_PERIPH_SAI4 (*)
+  *         @arg @ref LL_CLKAM_PERIPH_ADC3 (*)
+  *         @arg @ref LL_CLKAM_PERIPH_DTS  (*)
+  *         @arg @ref LL_CLKAM_PERIPH_DFSDM2  (*)
+  *         @arg @ref LL_CLKAM_PERIPH_BKPRAM
+  *         @arg @ref LL_CLKAM_PERIPH_SRAM4
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_CLKAM_Disable(uint32_t Periphs)
+{
+#if defined(RCC_D3AMR_BDMAAMEN)
+  CLEAR_BIT(RCC->D3AMR, Periphs);
+#else
+  CLEAR_BIT(RCC->SRDAMR, Periphs);
+#endif /* RCC_D3AMR_BDMAAMEN */
+}
+
+#if defined(RCC_CKGAENR_AXICKG)
+/**
+  * @}
+  */
+
+/**
+  * @brief  Enable clock gating for AXI bus peripherals.
+  * @rmtoll
+  * @param :
+  * @retval None
+*/
+__STATIC_INLINE void LL_CKGA_Enable(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->CKGAENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->CKGAENR, Periphs);
+  (void)tmpreg;
+}
+/**
+  * @}
+  */
+#endif /* RCC_CKGAENR_AXICKG */
+
+#if defined(RCC_CKGAENR_AXICKG)
+/**
+  * @}
+  */
+
+/**
+  * @brief  Disable  clock gating for AXI bus peripherals.
+  * @rmtoll
+  * @param :
+  * @retval None
+*/
+__STATIC_INLINE void LL_CKGA_Disable(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->CKGAENR, Periphs);
+}
+/**
+  * @}
+  */
+#endif /* RCC_CKGAENR_AXICKG */
+
+
+#if defined(DUAL_CORE)
+/** @defgroup BUS_LL_EF_AHB3 AHB3
+  * @{
+  */
+
+/**
+  * @brief  Enable C1 AHB3 peripherals clock.
+  * @rmtoll AHB3ENR      MDMAEN        LL_C1_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      DMA2DEN       LL_C1_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      JPGDECEN      LL_C1_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      FMCEN         LL_C1_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      QSPIEN        LL_C1_AHB3_GRP1_EnableClock\n (*)
+  *         AHB3ENR      OSPI1EN       LL_C1_AHB3_GRP1_EnableClock\n (*)
+  *         AHB3ENR      OSPI2EN       LL_C1_AHB3_GRP1_EnableClock\n (*)
+  *         AHB3ENR      IOMNGREN      LL_C1_AHB3_GRP1_EnableClock\n (*)
+  *         AHB3ENR      OTFDEC1EN     LL_C1_AHB3_GRP1_EnableClock\n (*)
+  *         AHB3ENR      OTFDEC2EN     LL_C1_AHB3_GRP1_EnableClock\n (*)
+  *         AHB3ENR      GFXMMU        LL_C1_AHB3_GRP1_EnableClock\n (*)
+  *         AHB3ENR      SDMMC1EN      LL_C1_AHB3_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1   (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2   (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_IOMNGR  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB3_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->AHB3ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->AHB3ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C1 AHB3 peripheral clock is enabled or not
+  * @rmtoll AHB3ENR      MDMAEN        LL_C1_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      DMA2DEN       LL_C1_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      JPGDECEN      LL_C1_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      FMCEN         LL_C1_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      QSPIEN        LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      OSPI1EN       LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      OSPI2EN       LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      IOMNGREN      LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      OTFDEC1EN     LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      OTFDEC2EN     LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      GFXMMU        LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      SDMMC1EN      LL_C1_AHB3_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1   (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2   (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_IOMNGR  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C1_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C1->AHB3ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C1 AHB3 peripherals clock.
+  * @rmtoll AHB3ENR      MDMAEN        LL_C1_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      DMA2DEN       LL_C1_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      JPGDECEN      LL_C1_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      FMCEN         LL_C1_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      QSPIEN        LL_C1_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      OSPI1EN       LL_C1_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      OSPI2EN       LL_C1_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      IOMNGREN      LL_C1_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      OTFDEC1EN     LL_C1_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      OTFDEC2EN     LL_C1_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      GFXMMU        LL_C1_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      SDMMC1EN      LL_C1_AHB3_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1   (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2   (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_IOMNGR  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB3_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->AHB3ENR, Periphs);
+}
+
+/**
+  * @brief  Enable C1 AHB3 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB3LPENR    MDMALPEN      LL_C1_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    DMA2DLPEN     LL_C1_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    JPGDECLPEN    LL_C1_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    FMCLPEN       LL_C1_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    QSPILPEN      LL_C1_AHB3_GRP1_EnableClockSleep\n  (*)
+  *         AHB3LPENR    OSPI1LPEN     LL_C1_AHB3_GRP1_EnableClockSleep\n  (*)
+  *         AHB3LPENR    OSPI2LPEN     LL_C1_AHB3_GRP1_EnableClockSleep\n  (*)
+  *         AHB3LPENR    IOMNGRLPEN    LL_C1_AHB3_GRP1_EnableClockSleep\n  (*)
+  *         AHB3LPENR    OTFDEC1LPEN   LL_C1_AHB3_GRP1_EnableClockSleep\n  (*)
+  *         AHB3LPENR    OTFDEC1LPEN   LL_C1_AHB3_GRP1_EnableClockSleep\n  (*)
+  *         AHB3LPENR    GFXMMULPEN    LL_C1_AHB3_GRP1_EnableClockSleep\n  (*)
+  *         AHB3LPENR    SDMMC1LPEN    LL_C1_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    FLASHLPEN     LL_C1_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    DTCM1LPEN     LL_C1_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    DTCM2LPEN     LL_C1_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    ITCMLPEN      LL_C1_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    AXISRAMLPEN   LL_C1_AHB3_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI     (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU   (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->AHB3LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->AHB3LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C1 AHB3 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB3LPENR    MDMALPEN      LL_C1_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    DMA2DLPEN     LL_C1_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    JPGDECLPEN    LL_C1_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    FMCLPEN       LL_C1_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    QSPILPEN      LL_C1_AHB3_GRP1_DisableClockSleep\n  (*)
+  *         AHB3LPENR    OSPI1LPEN     LL_C1_AHB3_GRP1_DisableClockSleep\n  (*)
+  *         AHB3LPENR    OSPI2LPEN     LL_C1_AHB3_GRP1_DisableClockSleep\n  (*)
+  *         AHB3LPENR    IOMNGRLPEN    LL_C1_AHB3_GRP1_DisableClockSleep\n  (*)
+  *         AHB3LPENR    OTFDEC1LPEN   LL_C1_AHB3_GRP1_DisableClockSleep\n  (*)
+  *         AHB3LPENR    OTFDEC1LPEN   LL_C1_AHB3_GRP1_DisableClockSleep\n  (*)
+  *         AHB3LPENR    GFXMMULPEN    LL_C1_AHB3_GRP1_DisableClockSleep\n  (*)
+  *         AHB3LPENR    SDMMC1LPEN    LL_C1_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    FLASHLPEN     LL_C1_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    DTCM1LPEN     LL_C1_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    DTCM2LPEN     LL_C1_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    ITCMLPEN      LL_C1_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    AXISRAMLPEN   LL_C1_AHB3_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI     (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2    (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2  (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU   (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->AHB3LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_AHB1 AHB1
+  * @{
+  */
+
+/**
+  * @brief  Enable C1 AHB1 peripherals clock.
+  * @rmtoll AHB1ENR      DMA1EN        LL_C1_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      DMA2EN        LL_C1_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      ADC12EN       LL_C1_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      CRCEN         LL_C1_AHB1_GRP1_EnableClock\n  (*)
+  *         AHB1ENR      ARTEN         LL_C1_AHB1_GRP1_EnableClock\n  (*)
+  *         AHB1ENR      ETH1MACEN     LL_C1_AHB1_GRP1_EnableClock\n  (*)
+  *         AHB1ENR      ETH1TXEN      LL_C1_AHB1_GRP1_EnableClock\n  (*)
+  *         AHB1ENR      ETH1RXEN      LL_C1_AHB1_GRP1_EnableClock\n  (*)
+  *         AHB1ENR      USB1OTGHSEN   LL_C1_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      USB1OTGHSULPIEN  LL_C1_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      USB2OTGHSEN   LL_C1_AHB1_GRP1_EnableClock\n   (*)
+  *         AHB1ENR      USB2OTGHSULPIEN  LL_C1_AHB1_GRP1_EnableClock  (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX   (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX   (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB1_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->AHB1ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->AHB1ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C1 AHB1 peripheral clock is enabled or not
+  * @rmtoll AHB1ENR      DMA1EN        LL_C1_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      DMA2EN        LL_C1_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      ADC12EN       LL_C1_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      CRCEN         LL_C1_AHB1_GRP1_IsEnabledClock\n  (*)
+  *         AHB1ENR      ARTEN         LL_C1_AHB1_GRP1_IsEnabledClock\n  (*)
+  *         AHB1ENR      ETH1MACEN     LL_C1_AHB1_GRP1_IsEnabledClock\n  (*)
+  *         AHB1ENR      ETH1TXEN      LL_C1_AHB1_GRP1_IsEnabledClock\n  (*)
+  *         AHB1ENR      ETH1RXEN      LL_C1_AHB1_GRP1_IsEnabledClock\n  (*)
+  *         AHB1ENR      USB1OTGHSEN   LL_C1_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      USB1OTGHSULPIEN  LL_C1_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      USB2OTGHSEN   LL_C1_AHB1_GRP1_IsEnabledClock\n  (*)
+  *         AHB1ENR      USB2OTGHSULPIEN  LL_C1_AHB1_GRP1_IsEnabledClock (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX   (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX   (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C1_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C1->AHB1ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C1 AHB1 peripherals clock.
+  * @rmtoll AHB1ENR      DMA1EN        LL_C1_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      DMA2EN        LL_C1_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      ADC12EN       LL_C1_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      CRCEN         LL_C1_AHB1_GRP1_DisableClock\n (*)
+  *         AHB1ENR      ARTEN         LL_C1_AHB1_GRP1_DisableClock\n (*)
+  *         AHB1ENR      ETH1MACEN     LL_C1_AHB1_GRP1_DisableClock\n (*)
+  *         AHB1ENR      ETH1TXEN      LL_C1_AHB1_GRP1_DisableClock\n (*)
+  *         AHB1ENR      ETH1RXEN      LL_C1_AHB1_GRP1_DisableClock\n (*)
+  *         AHB1ENR      USB1OTGHSEN   LL_C1_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      USB1OTGHSULPIEN  LL_C1_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      USB2OTGHSEN   LL_C1_AHB1_GRP1_DisableClock\n (*)
+  *         AHB1ENR      USB2OTGHSULPIEN  LL_C1_AHB1_GRP1_DisableClock (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX   (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX   (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB1_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->AHB1ENR, Periphs);
+}
+
+/**
+  * @brief  Enable C1 AHB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB1LPENR    DMA1LPEN      LL_C1_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    DMA2LPEN      LL_C1_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    ADC12LPEN     LL_C1_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    CRCLPEN       LL_C1_AHB1_GRP1_EnableClockSleep\n (*)
+  *         AHB1LPENR    ARTLPEN       LL_C1_AHB1_GRP1_EnableClockSleep\n (*)
+  *         AHB1LPENR    ETH1MACLPEN   LL_C1_AHB1_GRP1_EnableClockSleep\n (*)
+  *         AHB1LPENR    ETH1TXLPEN    LL_C1_AHB1_GRP1_EnableClockSleep\n (*)
+  *         AHB1LPENR    ETH1RXLPEN    LL_C1_AHB1_GRP1_EnableClockSleep\n (*)
+  *         AHB1LPENR    USB1OTGHSLPEN  LL_C1_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    USB1OTGHSULPILPEN  LL_C1_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    USB2OTGHSLPEN  LL_C1_AHB1_GRP1_EnableClockSleep\n   (*)
+  *         AHB1LPENR    USB2OTGHSULPILPEN  LL_C1_AHB1_GRP1_EnableClockSleep (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX   (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX   (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->AHB1LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->AHB1LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C1 AHB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB1LPENR    DMA1LPEN      LL_C1_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    DMA2LPEN      LL_C1_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    ADC12LPEN     LL_C1_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    CRCLPEN       LL_C1_AHB1_GRP1_DisableClockSleep\n (*)
+  *         AHB1LPENR    ARTLPEN       LL_C1_AHB1_GRP1_DisableClockSleep\n (*)
+  *         AHB1LPENR    ETH1MACLPEN   LL_C1_AHB1_GRP1_DisableClockSleep\n (*)
+  *         AHB1LPENR    ETH1TXLPEN    LL_C1_AHB1_GRP1_DisableClockSleep\n (*)
+  *         AHB1LPENR    ETH1RXLPEN    LL_C1_AHB1_GRP1_DisableClockSleep\n (*)
+  *         AHB1LPENR    USB1OTGHSLPEN  LL_C1_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    USB1OTGHSULPILPEN  LL_C1_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    USB2OTGHSLPEN  LL_C1_AHB1_GRP1_DisableClockSleep\n   (*)
+  *         AHB1LPENR    USB2OTGHSULPILPEN  LL_C1_AHB1_GRP1_DisableClockSleep (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC  (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX   (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX   (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->AHB1LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_AHB2 AHB2
+  * @{
+  */
+
+/**
+  * @brief  Enable C1 AHB2 peripherals clock.
+  * @rmtoll AHB2ENR      DCMIEN        LL_C1_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      HSEMEN        LL_C1_AHB2_GRP1_EnableClock\n (*)
+  *         AHB2ENR      CRYPEN        LL_C1_AHB2_GRP1_EnableClock\n (*)
+  *         AHB2ENR      HASHEN        LL_C1_AHB2_GRP1_EnableClock\n (*)
+  *         AHB2ENR      RNGEN         LL_C1_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      SDMMC2EN      LL_C1_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      BDMA1EN       LL_C1_AHB2_GRP1_EnableClock\n (*)
+  *         AHB2ENR      D2SRAM1EN     LL_C1_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      D2SRAM2EN     LL_C1_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      D2SRAM3EN     LL_C1_AHB2_GRP1_EnableClock   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB2_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->AHB2ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->AHB2ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C1 AHB2 peripheral clock is enabled or not
+  * @rmtoll AHB2ENR      DCMIEN        LL_C1_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      HSEMEN        LL_C1_AHB2_GRP1_IsEnabledClock\n (*)
+  *         AHB2ENR      CRYPEN        LL_C1_AHB2_GRP1_IsEnabledClock\n (*)
+  *         AHB2ENR      HASHEN        LL_C1_AHB2_GRP1_IsEnabledClock\n (*)
+  *         AHB2ENR      RNGEN         LL_C1_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      SDMMC2EN      LL_C1_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      BDMA1EN       LL_C1_AHB2_GRP1_IsEnabledClock\n (*)
+  *         AHB2ENR      D2SRAM1EN     LL_C1_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      D2SRAM2EN     LL_C1_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      D2SRAM3EN     LL_C1_AHB2_GRP1_IsEnabledClock   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C1_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C1->AHB2ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C1 AHB2 peripherals clock.
+  * @rmtoll AHB2ENR      DCMIEN        LL_C1_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      HSEMEN        LL_C1_AHB2_GRP1_DisableClock\n (*)
+  *         AHB2ENR      CRYPEN        LL_C1_AHB2_GRP1_DisableClock\n (*)
+  *         AHB2ENR      HASHEN        LL_C1_AHB2_GRP1_DisableClock\n (*)
+  *         AHB2ENR      RNGEN         LL_C1_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      SDMMC2EN      LL_C1_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      BDMA1EN       LL_C1_AHB2_GRP1_DisableClock\n (*)
+  *         AHB2ENR      D2SRAM1EN     LL_C1_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      D2SRAM2EN     LL_C1_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      D2SRAM3EN     LL_C1_AHB2_GRP1_DisableClock   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB2_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->AHB2ENR, Periphs);
+}
+
+/**
+  * @brief  Enable C1 AHB2 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB2LPENR    DCMILPEN      LL_C1_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    CRYPLPEN      LL_C1_AHB2_GRP1_EnableClockSleep\n (*)
+  *         AHB2LPENR    HASHLPEN      LL_C1_AHB2_GRP1_EnableClockSleep\n (*)
+  *         AHB2LPENR    RNGLPEN       LL_C1_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    SDMMC2LPEN    LL_C1_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    SDMMC2LPEN    LL_C1_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    BDAM1LPEN     LL_C1_AHB2_GRP1_EnableClockSleep\n (*)
+  *         AHB2LPENR    D2SRAM2LPEN   LL_C1_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    D2SRAM3LPEN   LL_C1_AHB2_GRP1_EnableClockSleep   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDAM1 (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->AHB2LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->AHB2LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C1 AHB2 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB2LPENR    DCMILPEN      LL_C1_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    CRYPLPEN      LL_C1_AHB2_GRP1_DisableClockSleep\n (*)
+  *         AHB2LPENR    HASHLPEN      LL_C1_AHB2_GRP1_DisableClockSleep\n (*)
+  *         AHB2LPENR    RNGLPEN       LL_C1_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    SDMMC2LPEN    LL_C1_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    BDAM1LPEN     LL_C1_AHB2_GRP1_DisableClockSleep\n (*)
+  *         AHB2LPENR    D2SRAM1LPEN   LL_C1_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    D2SRAM2LPEN   LL_C1_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    D2SRAM3LPEN   LL_C1_AHB2_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDAM1 (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->AHB2LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_AHB4 AHB4
+  * @{
+  */
+
+/**
+  * @brief  Enable C1 AHB4 peripherals clock.
+  * @rmtoll AHB4ENR      GPIOAEN       LL_C1_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOBEN       LL_C1_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOCEN       LL_C1_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIODEN       LL_C1_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOEEN       LL_C1_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOFEN       LL_C1_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOGEN       LL_C1_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOHEN       LL_C1_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOIEN       LL_C1_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOJEN       LL_C1_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOKEN       LL_C1_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      CRCEN         LL_C1_AHB4_GRP1_EnableClock\n (*)
+  *         AHB4ENR      BDMAEN        LL_C1_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      ADC3EN        LL_C1_AHB4_GRP1_EnableClock\n (*)
+  *         AHB4ENR      HSEMEN        LL_C1_AHB4_GRP1_EnableClock\n (*)
+  *         AHB4ENR      BKPRAMEN      LL_C1_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      SRAM4EN       LL_C1_AHB4_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB4_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->AHB4ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->AHB4ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C1 AHB4 peripheral clock is enabled or not
+  * @rmtoll AHB4ENR      GPIOAEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOBEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOCEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIODEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOEEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOFEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOGEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOHEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOIEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOJEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOKEN       LL_C1_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      CRCEN         LL_C1_AHB4_GRP1_IsEnabledClock\n (*)
+  *         AHB4ENR      BDMAEN        LL_C1_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      ADC3EN        LL_C1_AHB4_GRP1_IsEnabledClock\n (*)
+  *         AHB4ENR      HSEMEN        LL_C1_AHB4_GRP1_IsEnabledClock\n (*)
+  *         AHB4ENR      BKPRAMEN      LL_C1_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      SRAM4EN       LL_C1_AHB4_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C1_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C1->AHB4ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C1 AHB4 peripherals clock.
+  * @rmtoll AHB4ENR      GPIOAEN       LL_C1_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOBEN       LL_C1_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOCEN       LL_C1_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIODEN       LL_C1_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOEEN       LL_C1_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOFEN       LL_C1_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOGEN       LL_C1_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOHEN       LL_C1_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOIEN       LL_C1_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOJEN       LL_C1_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOKEN       LL_C1_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      CRCEN         LL_C1_AHB4_GRP1_DisableClock\n (*)
+  *         AHB4ENR      BDMAEN        LL_C1_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      ADC3EN        LL_C1_AHB4_GRP1_DisableClock\n (*)
+  *         AHB4ENR      HSEMEN        LL_C1_AHB4_GRP1_DisableClock\n (*)
+  *         AHB4ENR      BKPRAMEN      LL_C1_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      SRAM4EN       LL_C1_AHB4_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB4_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->AHB4ENR, Periphs);
+}
+
+/**
+  * @brief  Enable C1 AHB4 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB4LPENR    GPIOALPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOBLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOCLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIODLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOELPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOFLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOGLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOHLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOILPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOJLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOKLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    CRCLPEN       LL_C1_AHB4_GRP1_EnableClockSleep\n (*)
+  *         AHB4LPENR    BDMALPEN      LL_C1_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    ADC3LPEN      LL_C1_AHB4_GRP1_EnableClockSleep\n (*)
+  *         AHB4LPENR    BKPRAMLPEN    LL_C1_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    SRAM4LPEN     LL_C1_AHB4_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB4_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->AHB4LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->AHB4LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C1 AHB4 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB4LPENR    GPIOALPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOBLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOCLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIODLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOELPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOFLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOGLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOHLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOILPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOJLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOKLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    CRCLPEN       LL_C1_AHB4_GRP1_DisableClockSleep\n (*)
+  *         AHB4LPENR    BDMALPEN      LL_C1_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    ADC3LPEN      LL_C1_AHB4_GRP1_DisableClockSleep\n (*)
+  *         AHB4LPENR    BKPRAMLPEN    LL_C1_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    SRAM4LPEN     LL_C1_AHB4_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC  (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_AHB4_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->AHB4LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_APB3 APB3
+  * @{
+  */
+
+/**
+  * @brief  Enable C1 APB3 peripherals clock.
+  * @rmtoll APB3ENR      LTDCEN        LL_C1_APB3_GRP1_EnableClock\n (*)
+  *         APB3ENR      DSIEN         LL_C1_APB3_GRP1_EnableClock\n (*)
+  *         APB3ENR      WWDG1EN       LL_C1_APB3_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI  (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB3_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->APB3ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->APB3ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C1 APB3 peripheral clock is enabled or not
+  * @rmtoll APB3ENR      LTDCEN        LL_C1_APB3_GRP1_IsEnabledClock\n (*)
+  *         APB3ENR      DSIEN         LL_C1_APB3_GRP1_IsEnabledClock\n (*)
+  *         APB3ENR      WWDG1EN       LL_C1_APB3_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI  (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C1_APB3_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C1->APB3ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C1 APB3 peripherals clock.
+  * @rmtoll APB3ENR      LTDCEN        LL_C1_APB3_GRP1_DisableClock\n (*)
+  *         APB3ENR      DSIEN         LL_C1_APB3_GRP1_DisableClock\n (*)
+  *         APB3ENR      WWDG1EN       LL_C1_APB3_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI  (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB3_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->APB3ENR, Periphs);
+}
+
+/**
+  * @brief  Enable C1 APB3 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB3LPENR    LTDCLPEN      LL_C1_APB3_GRP1_EnableClockSleep\n (*)
+  *         APB3LPENR    DSILPEN       LL_C1_APB3_GRP1_EnableClockSleep\n (*)
+  *         APB3LPENR    WWDG1LPEN     LL_C1_APB3_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI  (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB3_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->APB3LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->APB3LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C1 APB3 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB3LPENR    LTDCLPEN      LL_C1_APB3_GRP1_DisableClockSleep\n (*)
+  *         APB3LPENR    DSILPEN       LL_C1_APB3_GRP1_DisableClockSleep\n (*)
+  *         APB3LPENR    WWDG1LPEN     LL_C1_APB3_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI  (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB3_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->APB3LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_APB1 APB1
+  * @{
+  */
+
+/**
+  * @brief  Enable C1 APB1 peripherals clock.
+  * @rmtoll APB1LENR     TIM2EN        LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM3EN        LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM4EN        LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM5EN        LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM6EN        LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM7EN        LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM12EN       LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM13EN       LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM14EN       LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     LPTIM1EN      LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     WWDG2EN       LL_C1_APB1_GRP1_EnableClock\n (*)
+  *         APB1LENR     SPI2EN        LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     SPI3EN        LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     SPDIFRXEN     LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     USART2EN      LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     USART3EN      LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     UART4EN       LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     UART5EN       LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     I2C1EN        LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     I2C2EN        LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     I2C3EN        LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     CECEN         LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     DAC12EN       LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     UART7EN       LL_C1_APB1_GRP1_EnableClock\n
+  *         APB1LENR     UART8EN       LL_C1_APB1_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB1_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->APB1LENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->APB1LENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C1 APB1 peripheral clock is enabled or not
+  * @rmtoll APB1LENR     TIM2EN        LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM3EN        LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM4EN        LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM5EN        LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM6EN        LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM7EN        LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM12EN       LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM13EN       LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM14EN       LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     LPTIM1EN      LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     WWDG2EN       LL_C1_APB1_GRP1_IsEnabledClock\n (*)
+  *         APB1LENR     SPI2EN        LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     SPI3EN        LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     SPDIFRXEN     LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     USART2EN      LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     USART3EN      LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     UART4EN       LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     UART5EN       LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     I2C1EN        LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     I2C2EN        LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     I2C3EN        LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     CECEN         LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     DAC12EN       LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     UART7EN       LL_C1_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     UART8EN       LL_C1_APB1_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C1_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C1->APB1LENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C1 APB1 peripherals clock.
+  * @rmtoll APB1LENR     TIM2EN        LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM3EN        LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM4EN        LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM5EN        LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM6EN        LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM7EN        LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM12EN       LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM13EN       LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM14EN       LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     LPTIM1EN      LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     WWDG2EN       LL_C1_APB1_GRP1_DisableClock\n (*)
+  *         APB1LENR     SPI2EN        LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     SPI3EN        LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     SPDIFRXEN     LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     USART2EN      LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     USART3EN      LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     UART4EN       LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     UART5EN       LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     I2C1EN        LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     I2C2EN        LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     I2C3EN        LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     CECEN         LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     DAC12EN       LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     UART7EN       LL_C1_APB1_GRP1_DisableClock\n
+  *         APB1LENR     UART8EN       LL_C1_APB1_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE void LL_C1_APB1_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->APB1LENR, Periphs);
+}
+
+/**
+  * @brief  Enable C1 APB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB1LLPENR   TIM2LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM3LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM4LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM5LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM6LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM7LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM12LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM13LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM14LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   LPTIM1LPEN    LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   WWDG2LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n (*)
+  *         APB1LLPENR   SPI2LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   SPI3LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   SPDIFRXLPEN   LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   USART2LPEN    LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   USART3LPEN    LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   UART4LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   UART5LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   I2C1LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   I2C2LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   I2C3LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   CECLPEN       LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   DAC12LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   UART7LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   UART8LPEN     LL_C1_APB1_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->APB1LLPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->APB1LLPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C1 APB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB1LLPENR   TIM2LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM3LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM4LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM5LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM6LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM7LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM12LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM13LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM14LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   LPTIM1LPEN    LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   WWDG2LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n (*)
+  *         APB1LLPENR   SPI2LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   SPI3LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   SPDIFRXLPEN   LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   USART2LPEN    LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   USART3LPEN    LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   UART4LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   UART5LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   I2C1LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   I2C2LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   I2C3LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   CECLPEN       LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   DAC12LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   UART7LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   UART8LPEN     LL_C1_APB1_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->APB1LLPENR, Periphs);
+}
+
+/**
+  * @brief  Enable C1 APB1 peripherals clock.
+  * @rmtoll APB1HENR     CRSEN         LL_C1_APB1_GRP2_EnableClock\n
+  *         APB1HENR     SWPMIEN       LL_C1_APB1_GRP2_EnableClock\n
+  *         APB1HENR     OPAMPEN       LL_C1_APB1_GRP2_EnableClock\n
+  *         APB1HENR     MDIOSEN       LL_C1_APB1_GRP2_EnableClock\n
+  *         APB1HENR     FDCANEN       LL_C1_APB1_GRP2_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB1_GRP2_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->APB1HENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->APB1HENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C1 APB1 peripheral clock is enabled or not
+  * @rmtoll APB1HENR     CRSEN         LL_C1_APB1_GRP2_IsEnabledClock\n
+  *         APB1HENR     SWPMIEN       LL_C1_APB1_GRP2_IsEnabledClock\n
+  *         APB1HENR     OPAMPEN       LL_C1_APB1_GRP2_IsEnabledClock\n
+  *         APB1HENR     MDIOSEN       LL_C1_APB1_GRP2_IsEnabledClock\n
+  *         APB1HENR     FDCANEN       LL_C1_APB1_GRP2_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C1_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C1->APB1HENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C1 APB1 peripherals clock.
+  * @rmtoll APB1HENR     CRSEN         LL_C1_APB1_GRP2_DisableClock\n
+  *         APB1HENR     SWPMIEN       LL_C1_APB1_GRP2_DisableClock\n
+  *         APB1HENR     OPAMPEN       LL_C1_APB1_GRP2_DisableClock\n
+  *         APB1HENR     MDIOSEN       LL_C1_APB1_GRP2_DisableClock\n
+  *         APB1HENR     FDCANEN       LL_C1_APB1_GRP2_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB1_GRP2_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->APB1HENR, Periphs);
+}
+
+/**
+  * @brief  Enable C1 APB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB1HLPENR   CRSLPEN       LL_C1_APB1_GRP2_EnableClockSleep\n
+  *         APB1HLPENR   SWPMILPEN     LL_C1_APB1_GRP2_EnableClockSleep\n
+  *         APB1HLPENR   OPAMPLPEN     LL_C1_APB1_GRP2_EnableClockSleep\n
+  *         APB1HLPENR   MDIOSLPEN     LL_C1_APB1_GRP2_EnableClockSleep\n
+  *         APB1HLPENR   FDCANLPEN     LL_C1_APB1_GRP2_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB1_GRP2_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->APB1HLPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->APB1HLPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C1 APB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB1HLPENR   CRSLPEN       LL_C1_APB1_GRP2_DisableClockSleep\n
+  *         APB1HLPENR   SWPMILPEN     LL_C1_APB1_GRP2_DisableClockSleep\n
+  *         APB1HLPENR   OPAMPLPEN     LL_C1_APB1_GRP2_DisableClockSleep\n
+  *         APB1HLPENR   MDIOSLPEN     LL_C1_APB1_GRP2_DisableClockSleep\n
+  *         APB1HLPENR   FDCANLPEN     LL_C1_APB1_GRP2_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB1_GRP2_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->APB1HLPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_APB2 APB2
+  * @{
+  */
+
+/**
+  * @brief  Enable C1 APB2 peripherals clock.
+  * @rmtoll APB2ENR      TIM1EN        LL_C1_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM8EN        LL_C1_APB2_GRP1_EnableClock\n
+  *         APB2ENR      USART1EN      LL_C1_APB2_GRP1_EnableClock\n
+  *         APB2ENR      USART6EN      LL_C1_APB2_GRP1_EnableClock\n
+  *         APB2ENR      UART9EN       LL_C1_APB2_GRP1_EnableClock\n (*)
+  *         APB2ENR      USART10EN     LL_C1_APB2_GRP1_EnableClock\n (*)
+  *         APB2ENR      SPI1EN        LL_C1_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SPI4EN        LL_C1_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM15EN       LL_C1_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM16EN       LL_C1_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM17EN       LL_C1_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SPI5EN        LL_C1_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SAI1EN        LL_C1_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SAI2EN        LL_C1_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SAI3EN        LL_C1_APB2_GRP1_EnableClock\n (*)
+  *         APB2ENR      DFSDM1EN      LL_C1_APB2_GRP1_EnableClock\n
+  *         APB2ENR      HRTIMEN       LL_C1_APB2_GRP1_EnableClock   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB2_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->APB2ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->APB2ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C1 APB2 peripheral clock is enabled or not
+  * @rmtoll APB2ENR      TIM1EN        LL_C1_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM8EN        LL_C1_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      USART1EN      LL_C1_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      USART6EN      LL_C1_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      UART9EN       LL_C1_APB2_GRP1_IsEnabledClock\n (*)
+  *         APB2ENR      USART10EN     LL_C1_APB2_GRP1_IsEnabledClock\n (*)
+  *         APB2ENR      SPI1EN        LL_C1_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SPI4EN        LL_C1_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM15EN       LL_C1_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM16EN       LL_C1_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM17EN       LL_C1_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SPI5EN        LL_C1_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SAI1EN        LL_C1_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SAI2EN        LL_C1_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SAI3EN        LL_C1_APB2_GRP1_IsEnabledClock\n (*)
+  *         APB2ENR      DFSDM1EN      LL_C1_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      HRTIMEN       LL_C1_APB2_GRP1_IsEnabledClock   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE uint32_t LL_C1_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C1->APB2ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C1 APB2 peripherals clock.
+  * @rmtoll APB2ENR      TIM1EN        LL_C1_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM8EN        LL_C1_APB2_GRP1_DisableClock\n
+  *         APB2ENR      USART1EN      LL_C1_APB2_GRP1_DisableClock\n
+  *         APB2ENR      USART6EN      LL_C1_APB2_GRP1_DisableClock\n
+  *         APB2ENR      UART9EN       LL_C1_APB2_GRP1_DisableClock\n (*)
+  *         APB2ENR      USART10EN     LL_C1_APB2_GRP1_DisableClock\n (*)
+  *         APB2ENR      SPI1EN        LL_C1_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SPI4EN        LL_C1_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM15EN       LL_C1_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM16EN       LL_C1_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM17EN       LL_C1_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SPI5EN        LL_C1_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SAI1EN        LL_C1_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SAI2EN        LL_C1_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SAI3EN        LL_C1_APB2_GRP1_DisableClock\n  (*)
+  *         APB2ENR      DFSDM1EN      LL_C1_APB2_GRP1_DisableClock\n
+  *         APB2ENR      HRTIMEN       LL_C1_APB2_GRP1_DisableClock    (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB2_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->APB2ENR, Periphs);
+}
+
+/**
+  * @brief  Enable C1 APB2 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB2LPENR    TIM1LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    TIM8LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    USART1LPEN    LL_C1_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    USART6LPEN    LL_C1_APB2_GRP1_EnableClockSleep\n
+  *         APB2ENR      UART9EN       LL_C1_APB2_GRP1_EnableClockSleep\n (*)
+  *         APB2ENR      USART10EN     LL_C1_APB2_GRP1_EnableClockSleep\n (*)
+  *         APB2LPENR    SPI1LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SPI4LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    TIM15LPEN     LL_C1_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    TIM16LPEN     LL_C1_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    TIM17LPEN     LL_C1_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SPI5LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SAI1LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SAI2LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SAI3LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n (*)
+  *         APB2LPENR    DFSDM1LPEN    LL_C1_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    HRTIMLPEN     LL_C1_APB2_GRP1_EnableClockSleep   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->APB2LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->APB2LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C1 APB2 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB2LPENR    TIM1LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    TIM8LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    USART1LPEN    LL_C1_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    UART9LPEN     LL_C1_APB2_GRP1_DisableClockSleep\n (*)
+  *         APB2LPENR    USART10LPEN   LL_C1_APB2_GRP1_DisableClockSleep\n (*)
+  *         APB2LPENR    USART6LPEN    LL_C1_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SPI1LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SPI4LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    TIM15LPEN     LL_C1_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    TIM16LPEN     LL_C1_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    TIM17LPEN     LL_C1_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SPI5LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SAI1LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SAI2LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SAI3LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n (*)
+  *         APB2LPENR    DFSDM1LPEN    LL_C1_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    HRTIMLPEN     LL_C1_APB2_GRP1_DisableClockSleep   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->APB2LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_APB4 APB4
+  * @{
+  */
+
+/**
+  * @brief  Enable C1 APB4 peripherals clock.
+  * @rmtoll APB4ENR      SYSCFGEN      LL_C1_APB4_GRP1_EnableClock\n
+  *         APB4ENR      LPUART1EN     LL_C1_APB4_GRP1_EnableClock\n
+  *         APB4ENR      SPI6EN        LL_C1_APB4_GRP1_EnableClock\n
+  *         APB4ENR      I2C4EN        LL_C1_APB4_GRP1_EnableClock\n
+  *         APB4ENR      LPTIM2EN      LL_C1_APB4_GRP1_EnableClock\n
+  *         APB4ENR      LPTIM3EN      LL_C1_APB4_GRP1_EnableClock\n
+  *         APB4ENR      LPTIM4EN      LL_C1_APB4_GRP1_EnableClock\n (*)
+  *         APB4ENR      LPTIM5EN      LL_C1_APB4_GRP1_EnableClock\n (*)
+  *         APB4ENR      DAC2EN        LL_C1_APB4_GRP1_EnableClock\n (*)
+  *         APB4ENR      COMP12EN      LL_C1_APB4_GRP1_EnableClock\n
+  *         APB4ENR      VREFEN        LL_C1_APB4_GRP1_EnableClock\n
+  *         APB4ENR      RTCAPBEN      LL_C1_APB4_GRP1_EnableClock\n
+  *         APB4ENR      SAI4EN        LL_C1_APB4_GRP1_EnableClock\n (*)
+  *         APB4ENR      DTSEN         LL_C1_APB4_GRP1_EnableClock\n (*)
+  *         APB4ENR      DFSDM2EN      LL_C1_APB4_GRP1_EnableClock   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB4_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->APB4ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->APB4ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C1 APB4 peripheral clock is enabled or not
+  * @rmtoll APB4ENR      SYSCFGEN      LL_C1_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      LPUART1EN     LL_C1_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      SPI6EN        LL_C1_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      I2C4EN        LL_C1_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      LPTIM2EN      LL_C1_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      LPTIM3EN      LL_C1_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      LPTIM4EN      LL_C1_APB4_GRP1_IsEnabledClock\n (*)
+  *         APB4ENR      LPTIM5EN      LL_C1_APB4_GRP1_IsEnabledClock\n (*)
+  *         APB4ENR      COMP12EN      LL_C1_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      VREFEN        LL_C1_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      RTCAPBEN      LL_C1_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      SAI4EN        LL_C1_APB4_GRP1_IsEnabledClock\n (*)
+  *         APB4ENR      DTSEN         LL_C1_APB4_GRP1_IsEnabledClock\n (*)
+  *         APB4ENR      DFSDM2EN      LL_C1_APB4_GRP1_IsEnabledClock   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C1_APB4_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C1->APB4ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C1 APB4 peripherals clock.
+  * @rmtoll APB4ENR      SYSCFGEN      LL_C1_APB4_GRP1_DisableClock\n
+  *         APB4ENR      LPUART1EN     LL_C1_APB4_GRP1_DisableClock\n
+  *         APB4ENR      SPI6EN        LL_C1_APB4_GRP1_DisableClock\n
+  *         APB4ENR      I2C4EN        LL_C1_APB4_GRP1_DisableClock\n
+  *         APB4ENR      LPTIM2EN      LL_C1_APB4_GRP1_DisableClock\n
+  *         APB4ENR      LPTIM3EN      LL_C1_APB4_GRP1_DisableClock\n
+  *         APB4ENR      LPTIM4EN      LL_C1_APB4_GRP1_DisableClock\n (*)
+  *         APB4ENR      LPTIM5EN      LL_C1_APB4_GRP1_DisableClock\n (*)
+  *         APB4ENR      COMP12EN      LL_C1_APB4_GRP1_DisableClock\n
+  *         APB4ENR      VREFEN        LL_C1_APB4_GRP1_DisableClock\n
+  *         APB4ENR      RTCAPBEN      LL_C1_APB4_GRP1_DisableClock\n
+  *         APB4ENR      SAI4EN        LL_C1_APB4_GRP1_DisableClock\n (*)
+  *         APB4ENR      DTSEN         LL_C1_APB4_GRP1_DisableClock\n (*)
+  *         APB4ENR      DFSDM2EN      LL_C1_APB4_GRP1_DisableClock   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB4_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->APB4ENR, Periphs);
+}
+
+/**
+  * @brief  Enable C1 APB4 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB4LPENR    SYSCFGLPEN    LL_C1_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    LPUART1LPEN   LL_C1_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    SPI6LPEN      LL_C1_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    I2C4LPEN      LL_C1_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    LPTIM2LPEN    LL_C1_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    LPTIM3LPEN    LL_C1_APB4_GRP1_EnableClockSleep\n (*)
+  *         APB4LPENR    LPTIM4LPEN    LL_C1_APB4_GRP1_EnableClockSleep\n (*)
+  *         APB4LPENR    LPTIM5LPEN    LL_C1_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    COMP12LPEN    LL_C1_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    VREFLPEN      LL_C1_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    RTCAPBLPEN    LL_C1_APB4_GRP1_EnableClockSleep\n
+  *         APB4ENR      SAI4EN        LL_C1_APB4_GRP1_EnableClockSleep\n (*)
+  *         APB4ENR      DTSEN         LL_C1_APB4_GRP1_EnableClockSleep\n (*)
+  *         APB4ENR      DFSDM2EN      LL_C1_APB4_GRP1_EnableClockSleep   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB4_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C1->APB4LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C1->APB4LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C1 APB4 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB4LPENR    SYSCFGLPEN    LL_C1_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    LPUART1LPEN   LL_C1_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    SPI6LPEN      LL_C1_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    I2C4LPEN      LL_C1_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    LPTIM2LPEN    LL_C1_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    LPTIM3LPEN    LL_C1_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    LPTIM4LPEN    LL_C1_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    LPTIM5LPEN    LL_C1_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    COMP12LPEN    LL_C1_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    VREFLPEN      LL_C1_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    RTCAPBLPEN    LL_C1_APB4_GRP1_DisableClockSleep\n
+  *         APB4ENR      SAI4EN        LL_C1_APB4_GRP1_DisableClockSleep\n (*)
+  *         APB4ENR      DTSEN         LL_C1_APB4_GRP1_DisableClockSleep\n (*)
+  *         APB4ENR      DFSDM2EN      LL_C1_APB4_GRP1_DisableClockSleep   (*)
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)
+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C1_APB4_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C1->APB4LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_AHB3 AHB3
+  * @{
+  */
+
+/**
+  * @brief  Enable C2 AHB3 peripherals clock.
+  * @rmtoll AHB3ENR      MDMAEN        LL_C2_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      DMA2DEN       LL_C2_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      JPGDECEN      LL_C2_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      FMCEN         LL_C2_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      QSPIEN        LL_C2_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      SDMMC1EN      LL_C2_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      FLASHEN       LL_C2_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      DTCM1EN       LL_C2_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      DTCM2EN       LL_C2_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      ITCMEN        LL_C2_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      AXISRAMEN     LL_C2_AHB3_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->AHB3ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->AHB3ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C2 AHB3 peripheral clock is enabled or not
+  * @rmtoll AHB3ENR      MDMAEN        LL_C2_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      DMA2DEN       LL_C2_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      JPGDECEN      LL_C2_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      FMCEN         LL_C2_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      QSPIEN        LL_C2_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      SDMMC1EN      LL_C2_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      FLASHEN       LL_C2_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      DTCM1EN       LL_C2_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      DTCM2EN       LL_C2_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      ITCMEN        LL_C2_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      AXISRAMEN     LL_C2_AHB3_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C2_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C2->AHB3ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C2 AHB3 peripherals clock.
+  * @rmtoll AHB3ENR      MDMAEN        LL_C2_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      DMA2DEN       LL_C2_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      JPGDECEN      LL_C2_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      FMCEN         LL_C2_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      QSPIEN        LL_C2_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      SDMMC1EN      LL_C2_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      FLASHEN       LL_C2_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      DTCM1EN       LL_C2_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      DTCM2EN       LL_C2_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      ITCMEN        LL_C2_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      AXISRAMEN     LL_C2_AHB3_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->AHB3ENR, Periphs);
+}
+
+/**
+  * @brief  Enable C2 AHB3 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB3LPENR    MDMALPEN      LL_C2_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    DMA2DLPEN     LL_C2_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    JPGDECLPEN    LL_C2_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    FMCLPEN       LL_C2_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    QSPILPEN      LL_C2_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    SDMMC1LPEN    LL_C2_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    FLASHLPEN     LL_C2_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    DTCM1LPEN     LL_C2_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    DTCM2LPEN     LL_C2_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    ITCMLPEN      LL_C2_AHB3_GRP1_EnableClockSleep\n
+  *         AHB3LPENR    AXISRAMLPEN   LL_C2_AHB3_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->AHB3LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->AHB3LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C2 AHB3 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB3LPENR    MDMALPEN      LL_C2_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    DMA2DLPEN     LL_C2_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    JPGDECLPEN    LL_C2_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    FMCLPEN       LL_C2_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    QSPILPEN      LL_C2_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    SDMMC1LPEN    LL_C2_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    FLASHLPEN     LL_C2_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    DTCM1LPEN     LL_C2_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    DTCM2LPEN     LL_C2_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    ITCMLPEN      LL_C2_AHB3_GRP1_DisableClockSleep\n
+  *         AHB3LPENR    AXISRAMLPEN   LL_C2_AHB3_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->AHB3LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_AHB1 AHB1
+  * @{
+  */
+
+/**
+  * @brief  Enable C2 AHB1 peripherals clock.
+  * @rmtoll AHB1ENR      DMA1EN        LL_C2_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      DMA2EN        LL_C2_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      ADC12EN       LL_C2_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      ARTEN         LL_C2_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      ETH1MACEN     LL_C2_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      ETH1TXEN      LL_C2_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      ETH1RXEN      LL_C2_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      USB1OTGHSEN   LL_C2_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      USB1OTGHSULPIEN  LL_C2_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      USB2OTGHSEN   LL_C2_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      USB2OTGHSULPIEN  LL_C2_AHB1_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->AHB1ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->AHB1ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C2 AHB1 peripheral clock is enabled or not
+  * @rmtoll AHB1ENR      DMA1EN        LL_C2_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      DMA2EN        LL_C2_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      ADC12EN       LL_C2_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      ARTEN         LL_C2_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      ETH1MACEN     LL_C2_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      ETH1TXEN      LL_C2_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      ETH1RXEN      LL_C2_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      USB1OTGHSEN   LL_C2_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      USB1OTGHSULPIEN  LL_C2_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      USB2OTGHSEN   LL_C2_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      USB2OTGHSULPIEN  LL_C2_AHB1_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C2_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C2->AHB1ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C2 AHB1 peripherals clock.
+  * @rmtoll AHB1ENR      DMA1EN        LL_C2_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      DMA2EN        LL_C2_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      ADC12EN       LL_C2_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      ARTEN         LL_C2_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      ETH1MACEN     LL_C2_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      ETH1TXEN      LL_C2_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      ETH1RXEN      LL_C2_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      USB1OTGHSEN   LL_C2_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      USB1OTGHSULPIEN  LL_C2_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      USB2OTGHSEN   LL_C2_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      USB2OTGHSULPIEN  LL_C2_AHB1_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->AHB1ENR, Periphs);
+}
+
+/**
+  * @brief  Enable C2 AHB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB1LPENR    DMA1LPEN      LL_C2_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    DMA2LPEN      LL_C2_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    ADC12LPEN     LL_C2_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    ARTLPEN       LL_C2_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    ETH1MACLPEN   LL_C2_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    ETH1TXLPEN    LL_C2_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    ETH1RXLPEN    LL_C2_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    USB1OTGHSLPEN  LL_C2_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    USB1OTGHSULPILPEN  LL_C2_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    USB2OTGHSLPEN  LL_C2_AHB1_GRP1_EnableClockSleep\n
+  *         AHB1LPENR    USB2OTGHSULPILPEN  LL_C2_AHB1_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->AHB1LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->AHB1LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C2 AHB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB1LPENR    DMA1LPEN      LL_C2_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    DMA2LPEN      LL_C2_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    ADC12LPEN     LL_C2_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    ARTLPEN       LL_C2_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    ETH1MACLPEN   LL_C2_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    ETH1TXLPEN    LL_C2_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    ETH1RXLPEN    LL_C2_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    USB1OTGHSLPEN  LL_C2_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    USB1OTGHSULPILPEN  LL_C2_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    USB2OTGHSLPEN  LL_C2_AHB1_GRP1_DisableClockSleep\n
+  *         AHB1LPENR    USB2OTGHSULPILPEN  LL_C2_AHB1_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->AHB1LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_AHB2 AHB2
+  * @{
+  */
+
+/**
+  * @brief  Enable C2 AHB2 peripherals clock.
+  * @rmtoll AHB2ENR      DCMIEN        LL_C2_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      CRYPEN        LL_C2_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      HASHEN        LL_C2_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      RNGEN         LL_C2_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      SDMMC2EN      LL_C2_AHB2_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->AHB2ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->AHB2ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C2 AHB2 peripheral clock is enabled or not
+  * @rmtoll AHB2ENR      DCMIEN        LL_C2_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      CRYPEN        LL_C2_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      HASHEN        LL_C2_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      RNGEN         LL_C2_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      SDMMC2EN      LL_C2_AHB2_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C2_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C2->AHB2ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C2 AHB2 peripherals clock.
+  * @rmtoll AHB2ENR      DCMIEN        LL_C2_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      CRYPEN        LL_C2_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      HASHEN        LL_C2_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      RNGEN         LL_C2_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      SDMMC2EN      LL_C2_AHB2_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->AHB2ENR, Periphs);
+}
+
+/**
+  * @brief  Enable C2 AHB2 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB2LPENR    DCMILPEN      LL_C2_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    CRYPLPEN      LL_C2_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    HASHLPEN      LL_C2_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    RNGLPEN       LL_C2_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    SDMMC2LPEN    LL_C2_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    D2SRAM1LPEN   LL_C2_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    D2SRAM2LPEN   LL_C2_AHB2_GRP1_EnableClockSleep\n
+  *         AHB2LPENR    D2SRAM3LPEN   LL_C2_AHB2_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->AHB2LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->AHB2LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C2 AHB2 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB2LPENR    DCMILPEN      LL_C2_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    CRYPLPEN      LL_C2_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    HASHLPEN      LL_C2_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    RNGLPEN       LL_C2_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    SDMMC2LPEN    LL_C2_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    D2SRAM1LPEN   LL_C2_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    D2SRAM2LPEN   LL_C2_AHB2_GRP1_DisableClockSleep\n
+  *         AHB2LPENR    D2SRAM3LPEN   LL_C2_AHB2_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->AHB2LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_AHB4 AHB4
+  * @{
+  */
+
+/**
+  * @brief  Enable C2 AHB4 peripherals clock.
+  * @rmtoll AHB4ENR      GPIOAEN       LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOBEN       LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOCEN       LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIODEN       LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOEEN       LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOFEN       LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOGEN       LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOHEN       LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOIEN       LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOJEN       LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      GPIOKEN       LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      CRCEN         LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      BDMAEN        LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      ADC3EN        LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      HSEMEN        LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      BKPRAMEN      LL_C2_AHB4_GRP1_EnableClock\n
+  *         AHB4ENR      SRAM4EN     LL_C2_AHB4_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB4_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->AHB4ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->AHB4ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C2 AHB4 peripheral clock is enabled or not
+  * @rmtoll AHB4ENR      GPIOAEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOBEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOCEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIODEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOEEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOFEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOGEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOHEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOIEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOJEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      GPIOKEN       LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      CRCEN         LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      BDMAEN        LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      ADC3EN        LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      HSEMEN        LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      BKPRAMEN      LL_C2_AHB4_GRP1_IsEnabledClock\n
+  *         AHB4ENR      SRAM4EN       LL_C2_AHB4_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C2_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C2->AHB4ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C2 AHB4 peripherals clock.
+  * @rmtoll AHB4ENR      GPIOAEN       LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOBEN       LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOCEN       LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIODEN       LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOEEN       LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOFEN       LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOGEN       LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOHEN       LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOIEN       LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOJEN       LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      GPIOKEN       LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      CRCEN         LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      BDMAEN        LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      ADC3EN        LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      HSEMEN        LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      BKPRAMEN      LL_C2_AHB4_GRP1_DisableClock\n
+  *         AHB4ENR      SRAM4EN       LL_C2_AHB4_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB4_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->AHB4ENR, Periphs);
+}
+
+/**
+  * @brief  Enable C2 AHB4 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB4LPENR    GPIOALPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOBLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOCLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIODLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOELPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOFLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOGLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOHLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOILPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOJLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    GPIOKLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    CRCLPEN       LL_C2_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    BDMALPEN      LL_C2_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    ADC3LPEN      LL_C2_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    BKPRAMLPEN    LL_C2_AHB4_GRP1_EnableClockSleep\n
+  *         AHB4LPENR    SRAM4LPEN     LL_C2_AHB4_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB4_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->AHB4LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->AHB4LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C2 AHB4 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll AHB4LPENR    GPIOALPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOBLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOCLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIODLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOELPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOFLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOGLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOHLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOILPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOJLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    GPIOKLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    CRCLPEN       LL_C2_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    BDMALPEN      LL_C2_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    ADC3LPEN      LL_C2_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    BKPRAMLPEN    LL_C2_AHB4_GRP1_DisableClockSleep\n
+  *         AHB4LPENR    SRAM4LPEN     LL_C2_AHB4_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_AHB4_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->AHB4LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_APB3 APB3
+  * @{
+  */
+
+/**
+  * @brief  Enable C2 APB3 peripherals clock.
+  * @rmtoll APB3ENR      LTDCEN        LL_C2_APB3_GRP1_EnableClock\n
+  *         APB3ENR      DSIEN         LL_C2_APB3_GRP1_EnableClock\n
+  *         APB3ENR      WWDG1EN       LL_C2_APB3_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB3_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->APB3ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->APB3ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C2 APB3 peripheral clock is enabled or not
+  * @rmtoll APB3ENR      LTDCEN        LL_C2_APB3_GRP1_IsEnabledClock\n
+  *         APB3ENR      DSIEN         LL_C2_APB3_GRP1_IsEnabledClock\n
+  *         APB3ENR      WWDG1EN       LL_C2_APB3_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
+  *
+  *         (*) value not defined in all devices.
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C2_APB3_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C2->APB3ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C2 APB3 peripherals clock.
+  * @rmtoll APB3ENR      LTDCEN        LL_C2_APB3_GRP1_DisableClock\n
+  *         APB3ENR      DSIEN         LL_C2_APB3_GRP1_DisableClock\n
+  *         APB3ENR      WWDG1EN       LL_C2_APB3_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB3_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->APB3ENR, Periphs);
+}
+
+/**
+  * @brief  Enable C2 APB3 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB3LPENR    LTDCLPEN      LL_C2_APB3_GRP1_EnableClockSleep\n
+  *         APB3LPENR    DSILPEN       LL_C2_APB3_GRP1_EnableClockSleep\n
+  *         APB3LPENR    WWDG1LPEN     LL_C2_APB3_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB3_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->APB3LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->APB3LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C2 APB3 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB3LPENR    LTDCLPEN      LL_C2_APB3_GRP1_DisableClockSleep\n
+  *         APB3LPENR    DSILPEN       LL_C2_APB3_GRP1_DisableClockSleep\n
+  *         APB3LPENR    WWDG1LPEN     LL_C2_APB3_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC
+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)
+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB3_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->APB3LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_APB1 APB1
+  * @{
+  */
+
+/**
+  * @brief  Enable C2 APB1 peripherals clock.
+  * @rmtoll APB1LENR     TIM2EN        LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM3EN        LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM4EN        LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM5EN        LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM6EN        LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM7EN        LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM12EN       LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM13EN       LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     TIM14EN       LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     LPTIM1EN      LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     WWDG2EN       LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     SPI2EN        LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     SPI3EN        LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     SPDIFRXEN     LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     USART2EN      LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     USART3EN      LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     UART4EN       LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     UART5EN       LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     I2C1EN        LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     I2C2EN        LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     I2C3EN        LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     CECEN         LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     DAC12EN       LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     UART7EN       LL_C2_APB1_GRP1_EnableClock\n
+  *         APB1LENR     UART8EN       LL_C2_APB1_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB1_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->APB1LENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->APB1LENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C2 APB1 peripheral clock is enabled or not
+  * @rmtoll APB1LENR     TIM2EN        LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM3EN        LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM4EN        LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM5EN        LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM6EN        LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM7EN        LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM12EN       LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM13EN       LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     TIM14EN       LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     LPTIM1EN      LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     WWDG2EN       LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     SPI2EN        LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     SPI3EN        LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     SPDIFRXEN     LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     USART2EN      LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     USART3EN      LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     UART4EN       LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     UART5EN       LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     I2C1EN        LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     I2C2EN        LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     I2C3EN        LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     CECEN         LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     DAC12EN       LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     UART7EN       LL_C2_APB1_GRP1_IsEnabledClock\n
+  *         APB1LENR     UART8EN       LL_C2_APB1_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C2_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C2->APB1LENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C2 APB1 peripherals clock.
+  * @rmtoll APB1LENR     TIM2EN        LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM3EN        LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM4EN        LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM5EN        LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM6EN        LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM7EN        LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM12EN       LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM13EN       LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     TIM14EN       LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     LPTIM1EN      LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     WWDG2EN       LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     SPI2EN        LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     SPI3EN        LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     SPDIFRXEN     LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     USART2EN      LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     USART3EN      LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     UART4EN       LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     UART5EN       LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     I2C1EN        LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     I2C2EN        LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     I2C3EN        LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     CECEN         LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     DAC12EN       LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     UART7EN       LL_C2_APB1_GRP1_DisableClock\n
+  *         APB1LENR     UART8EN       LL_C2_APB1_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB1_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->APB1LENR, Periphs);
+}
+
+/**
+  * @brief  Enable C2 APB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB1LLPENR   TIM2LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM3LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM4LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM5LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM6LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM7LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM12LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM13LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   TIM14LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   LPTIM1LPEN    LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   WWDG2LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   SPI2LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   SPI3LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   SPDIFRXLPEN   LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   USART2LPEN    LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   USART3LPEN    LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   UART4LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   UART5LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   I2C1LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   I2C2LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   I2C3LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   CECLPEN       LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   DAC12LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   UART7LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n
+  *         APB1LLPENR   UART8LPEN     LL_C2_APB1_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->APB1LLPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->APB1LLPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C2 APB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB1LLPENR   TIM2LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM3LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM4LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM5LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM6LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM7LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM12LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM13LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   TIM14LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   LPTIM1LPEN    LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   WWDG2LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   SPI2LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   SPI3LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   SPDIFRXLPEN   LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   USART2LPEN    LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   USART3LPEN    LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   UART4LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   UART5LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   I2C1LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   I2C2LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   I2C3LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   CECLPEN       LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   DAC12LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   UART7LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n
+  *         APB1LLPENR   UART8LPEN     LL_C2_APB1_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->APB1LLPENR, Periphs);
+}
+
+/**
+  * @brief  Enable C2 APB1 peripherals clock.
+  * @rmtoll APB1HENR     CRSEN         LL_C2_APB1_GRP2_EnableClock\n
+  *         APB1HENR     SWPMIEN       LL_C2_APB1_GRP2_EnableClock\n
+  *         APB1HENR     OPAMPEN       LL_C2_APB1_GRP2_EnableClock\n
+  *         APB1HENR     MDIOSEN       LL_C2_APB1_GRP2_EnableClock\n
+  *         APB1HENR     FDCANEN       LL_C2_APB1_GRP2_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB1_GRP2_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->APB1HENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->APB1HENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C2 APB1 peripheral clock is enabled or not
+  * @rmtoll APB1HENR     CRSEN         LL_C2_APB1_GRP2_IsEnabledClock\n
+  *         APB1HENR     SWPMIEN       LL_C2_APB1_GRP2_IsEnabledClock\n
+  *         APB1HENR     OPAMPEN       LL_C2_APB1_GRP2_IsEnabledClock\n
+  *         APB1HENR     MDIOSEN       LL_C2_APB1_GRP2_IsEnabledClock\n
+  *         APB1HENR     FDCANEN       LL_C2_APB1_GRP2_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C2_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C2->APB1HENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C2 APB1 peripherals clock.
+  * @rmtoll APB1HENR     CRSEN         LL_C2_APB1_GRP2_DisableClock\n
+  *         APB1HENR     SWPMIEN       LL_C2_APB1_GRP2_DisableClock\n
+  *         APB1HENR     OPAMPEN       LL_C2_APB1_GRP2_DisableClock\n
+  *         APB1HENR     MDIOSEN       LL_C2_APB1_GRP2_DisableClock\n
+  *         APB1HENR     FDCANEN       LL_C2_APB1_GRP2_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB1_GRP2_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->APB1HENR, Periphs);
+}
+
+/**
+  * @brief  Enable C2 APB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB1HLPENR   CRSLPEN       LL_C2_APB1_GRP2_EnableClockSleep\n
+  *         APB1HLPENR   SWPMILPEN     LL_C2_APB1_GRP2_EnableClockSleep\n
+  *         APB1HLPENR   OPAMPLPEN     LL_C2_APB1_GRP2_EnableClockSleep\n
+  *         APB1HLPENR   MDIOSLPEN     LL_C2_APB1_GRP2_EnableClockSleep\n
+  *         APB1HLPENR   FDCANLPEN     LL_C2_APB1_GRP2_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB1_GRP2_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->APB1HLPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->APB1HLPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C2 APB1 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB1HLPENR   CRSLPEN       LL_C2_APB1_GRP2_DisableClockSleep\n
+  *         APB1HLPENR   SWPMILPEN     LL_C2_APB1_GRP2_DisableClockSleep\n
+  *         APB1HLPENR   OPAMPLPEN     LL_C2_APB1_GRP2_DisableClockSleep\n
+  *         APB1HLPENR   MDIOSLPEN     LL_C2_APB1_GRP2_DisableClockSleep\n
+  *         APB1HLPENR   FDCANLPEN     LL_C2_APB1_GRP2_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB1_GRP2_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->APB1HLPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_APB2 APB2
+  * @{
+  */
+
+/**
+  * @brief  Enable C2 APB2 peripherals clock.
+  * @rmtoll APB2ENR      TIM1EN        LL_C2_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM8EN        LL_C2_APB2_GRP1_EnableClock\n
+  *         APB2ENR      USART1EN      LL_C2_APB2_GRP1_EnableClock\n
+  *         APB2ENR      USART6EN      LL_C2_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SPI1EN        LL_C2_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SPI4EN        LL_C2_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM15EN       LL_C2_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM16EN       LL_C2_APB2_GRP1_EnableClock\n
+  *         APB2ENR      TIM17EN       LL_C2_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SPI5EN        LL_C2_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SAI1EN        LL_C2_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SAI2EN        LL_C2_APB2_GRP1_EnableClock\n
+  *         APB2ENR      SAI3EN        LL_C2_APB2_GRP1_EnableClock\n
+  *         APB2ENR      DFSDM1EN      LL_C2_APB2_GRP1_EnableClock\n
+  *         APB2ENR      HRTIMEN       LL_C2_APB2_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB2_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->APB2ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->APB2ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C2 APB2 peripheral clock is enabled or not
+  * @rmtoll APB2ENR      TIM1EN        LL_C2_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM8EN        LL_C2_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      USART1EN      LL_C2_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      USART6EN      LL_C2_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SPI1EN        LL_C2_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SPI4EN        LL_C2_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM15EN       LL_C2_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM16EN       LL_C2_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      TIM17EN       LL_C2_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SPI5EN        LL_C2_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SAI1EN        LL_C2_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SAI2EN        LL_C2_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      SAI3EN        LL_C2_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      DFSDM1EN      LL_C2_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR      HRTIMEN       LL_C2_APB2_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C2_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C2->APB2ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C2 APB2 peripherals clock.
+  * @rmtoll APB2ENR      TIM1EN        LL_C2_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM8EN        LL_C2_APB2_GRP1_DisableClock\n
+  *         APB2ENR      USART1EN      LL_C2_APB2_GRP1_DisableClock\n
+  *         APB2ENR      USART6EN      LL_C2_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SPI1EN        LL_C2_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SPI4EN        LL_C2_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM15EN       LL_C2_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM16EN       LL_C2_APB2_GRP1_DisableClock\n
+  *         APB2ENR      TIM17EN       LL_C2_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SPI5EN        LL_C2_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SAI1EN        LL_C2_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SAI2EN        LL_C2_APB2_GRP1_DisableClock\n
+  *         APB2ENR      SAI3EN        LL_C2_APB2_GRP1_DisableClock\n
+  *         APB2ENR      DFSDM1EN      LL_C2_APB2_GRP1_DisableClock\n
+  *         APB2ENR      HRTIMEN       LL_C2_APB2_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB2_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->APB2ENR, Periphs);
+}
+
+/**
+  * @brief  Enable C2 APB2 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB2LPENR    TIM1LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    TIM8LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    USART1LPEN    LL_C2_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    USART6LPEN    LL_C2_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SPI1LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SPI4LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    TIM15LPEN     LL_C2_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    TIM16LPEN     LL_C2_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    TIM17LPEN     LL_C2_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SPI5LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SAI1LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SAI2LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    SAI3LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    DFSDM1LPEN    LL_C2_APB2_GRP1_EnableClockSleep\n
+  *         APB2LPENR    HRTIMLPEN     LL_C2_APB2_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->APB2LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->APB2LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C2 APB2 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB2LPENR    TIM1LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    TIM8LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    USART1LPEN    LL_C2_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    USART6LPEN    LL_C2_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SPI1LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SPI4LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    TIM15LPEN     LL_C2_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    TIM16LPEN     LL_C2_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    TIM17LPEN     LL_C2_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SPI5LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SAI1LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SAI2LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    SAI3LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    DFSDM1LPEN    LL_C2_APB2_GRP1_DisableClockSleep\n
+  *         APB2LPENR    HRTIMLPEN     LL_C2_APB2_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->APB2LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_APB4 APB4
+  * @{
+  */
+
+/**
+  * @brief  Enable C2 APB4 peripherals clock.
+  * @rmtoll APB4ENR      SYSCFGEN      LL_C2_APB4_GRP1_EnableClock\n
+  *         APB4ENR      LPUART1EN     LL_C2_APB4_GRP1_EnableClock\n
+  *         APB4ENR      SPI6EN        LL_C2_APB4_GRP1_EnableClock\n
+  *         APB4ENR      I2C4EN        LL_C2_APB4_GRP1_EnableClock\n
+  *         APB4ENR      LPTIM2EN      LL_C2_APB4_GRP1_EnableClock\n
+  *         APB4ENR      LPTIM3EN      LL_C2_APB4_GRP1_EnableClock\n
+  *         APB4ENR      LPTIM4EN      LL_C2_APB4_GRP1_EnableClock\n
+  *         APB4ENR      LPTIM5EN      LL_C2_APB4_GRP1_EnableClock\n
+  *         APB4ENR      COMP12EN      LL_C2_APB4_GRP1_EnableClock\n
+  *         APB4ENR      VREFEN        LL_C2_APB4_GRP1_EnableClock\n
+  *         APB4ENR      RTCAPBEN      LL_C2_APB4_GRP1_EnableClock\n
+  *         APB4ENR      SAI4EN        LL_C2_APB4_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB4_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->APB4ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->APB4ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if C2 APB4 peripheral clock is enabled or not
+  * @rmtoll APB4ENR      SYSCFGEN      LL_C2_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      LPUART1EN     LL_C2_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      SPI6EN        LL_C2_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      I2C4EN        LL_C2_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      LPTIM2EN      LL_C2_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      LPTIM3EN      LL_C2_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      LPTIM4EN      LL_C2_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      LPTIM5EN      LL_C2_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      COMP12EN      LL_C2_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      VREFEN        LL_C2_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      RTCAPBEN      LL_C2_APB4_GRP1_IsEnabledClock\n
+  *         APB4ENR      SAI4EN        LL_C2_APB4_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4
+  * @retval uint32_t
+*/
+__STATIC_INLINE uint32_t LL_C2_APB4_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return ((READ_BIT(RCC_C2->APB4ENR, Periphs) == Periphs)?1U:0U);
+}
+
+/**
+  * @brief  Disable C2 APB4 peripherals clock.
+  * @rmtoll APB4ENR      SYSCFGEN      LL_C2_APB4_GRP1_DisableClock\n
+  *         APB4ENR      LPUART1EN     LL_C2_APB4_GRP1_DisableClock\n
+  *         APB4ENR      SPI6EN        LL_C2_APB4_GRP1_DisableClock\n
+  *         APB4ENR      I2C4EN        LL_C2_APB4_GRP1_DisableClock\n
+  *         APB4ENR      LPTIM2EN      LL_C2_APB4_GRP1_DisableClock\n
+  *         APB4ENR      LPTIM3EN      LL_C2_APB4_GRP1_DisableClock\n
+  *         APB4ENR      LPTIM4EN      LL_C2_APB4_GRP1_DisableClock\n
+  *         APB4ENR      LPTIM5EN      LL_C2_APB4_GRP1_DisableClock\n
+  *         APB4ENR      COMP12EN      LL_C2_APB4_GRP1_DisableClock\n
+  *         APB4ENR      VREFEN        LL_C2_APB4_GRP1_DisableClock\n
+  *         APB4ENR      RTCAPBEN      LL_C2_APB4_GRP1_DisableClock\n
+  *         APB4ENR      SAI4EN        LL_C2_APB4_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB4_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->APB4ENR, Periphs);
+}
+
+/**
+  * @brief  Enable C2 APB4 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB4LPENR    SYSCFGLPEN    LL_C2_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    LPUART1LPEN   LL_C2_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    SPI6LPEN      LL_C2_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    I2C4LPEN      LL_C2_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    LPTIM2LPEN    LL_C2_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    LPTIM3LPEN    LL_C2_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    LPTIM4LPEN    LL_C2_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    LPTIM5LPEN    LL_C2_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    COMP12LPEN    LL_C2_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    VREFLPEN      LL_C2_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    RTCAPBLPEN    LL_C2_APB4_GRP1_EnableClockSleep\n
+  *         APB4LPENR    SAI4LPEN      LL_C2_APB4_GRP1_EnableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB4_GRP1_EnableClockSleep(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC_C2->APB4LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC_C2->APB4LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable C2 APB4 peripherals clock during Low Power (Sleep) mode.
+  * @rmtoll APB4LPENR    SYSCFGLPEN    LL_C2_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    LPUART1LPEN   LL_C2_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    SPI6LPEN      LL_C2_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    I2C4LPEN      LL_C2_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    LPTIM2LPEN    LL_C2_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    LPTIM3LPEN    LL_C2_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    LPTIM4LPEN    LL_C2_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    LPTIM5LPEN    LL_C2_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    COMP12LPEN    LL_C2_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    VREFLPEN      LL_C2_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    RTCAPBLPEN    LL_C2_APB4_GRP1_DisableClockSleep\n
+  *         APB4LPENR    SAI4LPEN      LL_C2_APB4_GRP1_DisableClockSleep
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6
+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12
+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF
+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4
+  * @retval None
+*/
+__STATIC_INLINE void LL_C2_APB4_GRP1_DisableClockSleep(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC_C2->APB4LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+#endif /*DUAL_CORE*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(RCC) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_LL_BUS_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cortex.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cortex.h
new file mode 100644
index 00000000..c7363b9c
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cortex.h
@@ -0,0 +1,669 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_cortex.h
+  * @author  MCD Application Team
+  * @brief   Header file of CORTEX LL module.
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The LL CORTEX driver contains a set of generic APIs that can be
+    used by user:
+      (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
+          functions
+      (+) Low power mode configuration (SCB register of Cortex-MCU)
+      (+) MPU API to configure and enable regions
+      (+) API to access to MCU info (CPUID register)
+      (+) API to enable fault handler (SHCSR accesses)
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_LL_CORTEX_H
+#define STM32H7xx_LL_CORTEX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+/** @defgroup CORTEX_LL CORTEX
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
+  * @{
+  */
+
+/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
+  * @{
+  */
+#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8     0x00000000UL                /*!< AHB clock divided by 8 selected as SysTick clock source.*/
+#define LL_SYSTICK_CLKSOURCE_HCLK          SysTick_CTRL_CLKSOURCE_Msk  /*!< AHB clock selected as SysTick clock source. */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
+  * @{
+  */
+#define LL_HANDLER_FAULT_USG               SCB_SHCSR_USGFAULTENA_Msk              /*!< Usage fault */
+#define LL_HANDLER_FAULT_BUS               SCB_SHCSR_BUSFAULTENA_Msk              /*!< Bus fault */
+#define LL_HANDLER_FAULT_MEM               SCB_SHCSR_MEMFAULTENA_Msk              /*!< Memory management fault */
+/**
+  * @}
+  */
+
+#if __MPU_PRESENT
+
+/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
+  * @{
+  */
+#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE     0x00000000UL                                      /*!< Disable NMI and privileged SW access */
+#define LL_MPU_CTRL_HARDFAULT_NMI          MPU_CTRL_HFNMIENA_Msk                             /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
+#define LL_MPU_CTRL_PRIVILEGED_DEFAULT     MPU_CTRL_PRIVDEFENA_Msk                           /*!< Enable privileged software access to default memory map */
+#define LL_MPU_CTRL_HFNMI_PRIVDEF          (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_REGION MPU Region Number
+  * @{
+  */
+#define LL_MPU_REGION_NUMBER0              0x00UL /*!< REGION Number 0  */
+#define LL_MPU_REGION_NUMBER1              0x01UL /*!< REGION Number 1  */
+#define LL_MPU_REGION_NUMBER2              0x02UL /*!< REGION Number 2  */
+#define LL_MPU_REGION_NUMBER3              0x03UL /*!< REGION Number 3  */
+#define LL_MPU_REGION_NUMBER4              0x04UL /*!< REGION Number 4  */
+#define LL_MPU_REGION_NUMBER5              0x05UL /*!< REGION Number 5  */
+#define LL_MPU_REGION_NUMBER6              0x06UL /*!< REGION Number 6  */
+#define LL_MPU_REGION_NUMBER7              0x07UL /*!< REGION Number 7  */
+#if !defined(CORE_CM4)
+#define LL_MPU_REGION_NUMBER8              0x08UL /*!< REGION Number 8  */
+#define LL_MPU_REGION_NUMBER9              0x09UL /*!< REGION Number 9  */
+#define LL_MPU_REGION_NUMBER10             0x0AUL /*!< REGION Number 10 */
+#define LL_MPU_REGION_NUMBER11             0x0BUL /*!< REGION Number 11 */
+#define LL_MPU_REGION_NUMBER12             0x0CUL /*!< REGION Number 12 */
+#define LL_MPU_REGION_NUMBER13             0x0DUL /*!< REGION Number 13 */
+#define LL_MPU_REGION_NUMBER14             0x0EUL /*!< REGION Number 14 */
+#define LL_MPU_REGION_NUMBER15             0x0FUL /*!< REGION Number 15 */
+#endif /* !defined(CORE_CM4) */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
+  * @{
+  */
+#define LL_MPU_REGION_SIZE_32B             (0x04UL << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64B             (0x05UL << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128B            (0x06UL << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256B            (0x07UL << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512B            (0x08UL << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1KB             (0x09UL << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2KB             (0x0AUL << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4KB             (0x0BUL << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_8KB             (0x0CUL << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_16KB            (0x0DUL << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_32KB            (0x0EUL << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64KB            (0x0FUL << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128KB           (0x10UL << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256KB           (0x11UL << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512KB           (0x12UL << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1MB             (0x13UL << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2MB             (0x14UL << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4MB             (0x15UL << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_8MB             (0x16UL << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_16MB            (0x17UL << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_32MB            (0x18UL << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64MB            (0x19UL << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128MB           (0x1AUL << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256MB           (0x1BUL << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512MB           (0x1CUL << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1GB             (0x1DUL << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2GB             (0x1EUL << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4GB             (0x1FUL << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
+  * @{
+  */
+#define LL_MPU_REGION_NO_ACCESS            (0x00UL << MPU_RASR_AP_Pos) /*!< No access*/
+#define LL_MPU_REGION_PRIV_RW              (0x01UL << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
+#define LL_MPU_REGION_PRIV_RW_URO          (0x02UL << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
+#define LL_MPU_REGION_FULL_ACCESS          (0x03UL << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
+#define LL_MPU_REGION_PRIV_RO              (0x05UL << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
+#define LL_MPU_REGION_PRIV_RO_URO          (0x06UL << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
+  * @{
+  */
+#define LL_MPU_TEX_LEVEL0                  (0x00UL << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
+#define LL_MPU_TEX_LEVEL1                  (0x01UL << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
+#define LL_MPU_TEX_LEVEL2                  (0x02UL << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
+#define LL_MPU_TEX_LEVEL4                  (0x04UL << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
+  * @{
+  */
+#define LL_MPU_INSTRUCTION_ACCESS_ENABLE   0x00UL            /*!< Instruction fetches enabled */
+#define LL_MPU_INSTRUCTION_ACCESS_DISABLE  MPU_RASR_XN_Msk  /*!< Instruction fetches disabled*/
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
+  * @{
+  */
+#define LL_MPU_ACCESS_SHAREABLE            MPU_RASR_S_Msk   /*!< Shareable memory attribute */
+#define LL_MPU_ACCESS_NOT_SHAREABLE        0x00UL           /*!< Not Shareable memory attribute */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
+  * @{
+  */
+#define LL_MPU_ACCESS_CACHEABLE            MPU_RASR_C_Msk   /*!< Cacheable memory attribute */
+#define LL_MPU_ACCESS_NOT_CACHEABLE        0x00UL           /*!< Not Cacheable memory attribute */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
+  * @{
+  */
+#define LL_MPU_ACCESS_BUFFERABLE           MPU_RASR_B_Msk   /*!< Bufferable memory attribute */
+#define LL_MPU_ACCESS_NOT_BUFFERABLE       0x00UL           /*!< Not Bufferable memory attribute */
+/**
+  * @}
+  */
+#endif /* __MPU_PRESENT */
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
+  * @{
+  */
+
+/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
+  * @{
+  */
+
+/**
+  * @brief  This function checks if the Systick counter flag is active or not.
+  * @note   It can be used in timeout function on application side.
+  * @rmtoll STK_CTRL     COUNTFLAG     LL_SYSTICK_IsActiveCounterFlag
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
+{
+  return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configures the SysTick clock source
+  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_SetClkSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
+{
+  MODIFY_REG(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK, Source);
+}
+
+/**
+  * @brief  Get the SysTick clock source
+  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_GetClkSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
+  */
+__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
+{
+  return (uint32_t)(READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK));
+}
+
+/**
+  * @brief  Enable SysTick exception request
+  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_EnableIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
+{
+  SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+  * @brief  Disable SysTick exception request
+  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_DisableIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
+{
+  CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+  * @brief  Checks if the SYSTICK interrupt is enabled or disabled.
+  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_IsEnabledIT
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
+{
+  return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
+  * @{
+  */
+
+/**
+  * @brief  Processor uses sleep as its low power mode
+  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableSleep
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_EnableSleep(void)
+{
+  /* Clear SLEEPDEEP bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+}
+
+/**
+  * @brief  Processor uses deep sleep as its low power mode
+  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableDeepSleep
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
+{
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+}
+
+/**
+  * @brief  Configures sleep-on-exit when returning from Handler mode to Thread mode.
+  * @note   Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
+  *         empty main application.
+  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_EnableSleepOnExit
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
+{
+  /* Set SLEEPONEXIT bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
+}
+
+/**
+  * @brief  Do not sleep when returning to Thread mode.
+  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_DisableSleepOnExit
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
+{
+  /* Clear SLEEPONEXIT bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
+}
+
+/**
+  * @brief  Enabled events and all interrupts, including disabled interrupts, can wakeup the
+  *         processor.
+  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_EnableEventOnPend
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
+{
+  /* Set SEVEONPEND bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk);
+}
+
+/**
+  * @brief  Only enabled interrupts or events can wakeup the processor, disabled interrupts are
+  *         excluded
+  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_DisableEventOnPend
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
+{
+  /* Clear SEVEONPEND bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EF_HANDLER HANDLER
+  * @{
+  */
+
+/**
+  * @brief  Enable a fault in System handler control register (SHCSR)
+  * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_EnableFault
+  * @param  Fault This parameter can be a combination of the following values:
+  *         @arg @ref LL_HANDLER_FAULT_USG
+  *         @arg @ref LL_HANDLER_FAULT_BUS
+  *         @arg @ref LL_HANDLER_FAULT_MEM
+  * @retval None
+  */
+__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
+{
+  /* Enable the system handler fault */
+  SET_BIT(SCB->SHCSR, Fault);
+}
+
+/**
+  * @brief  Disable a fault in System handler control register (SHCSR)
+  * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_DisableFault
+  * @param  Fault This parameter can be a combination of the following values:
+  *         @arg @ref LL_HANDLER_FAULT_USG
+  *         @arg @ref LL_HANDLER_FAULT_BUS
+  *         @arg @ref LL_HANDLER_FAULT_MEM
+  * @retval None
+  */
+__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
+{
+  /* Disable the system handler fault */
+  CLEAR_BIT(SCB->SHCSR, Fault);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
+  * @{
+  */
+
+/**
+  * @brief  Get Implementer code
+  * @rmtoll SCB_CPUID    IMPLEMENTER   LL_CPUID_GetImplementer
+  * @retval Value should be equal to 0x41 for ARM
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
+}
+
+/**
+  * @brief  Get Variant number (The r value in the rnpn product revision identifier)
+  * @rmtoll SCB_CPUID    VARIANT       LL_CPUID_GetVariant
+  * @retval Value between 0 and 255 (0x0: revision 0)
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
+}
+
+/**
+  * @brief  Get Constant number
+  * @rmtoll SCB_CPUID    ARCHITECTURE  LL_CPUID_GetConstant
+  * @retval Value should be equal to 0xF for Cortex-M7 and Cortex-M4 devices
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
+}
+
+/**
+  * @brief  Get Part number
+  * @rmtoll SCB_CPUID    PARTNO        LL_CPUID_GetParNo
+  * @retval Value should be equal to 0xC27 for Cortex-M7 and equal to 0xC24 for Cortex-M4
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
+}
+
+/**
+  * @brief  Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
+  * @rmtoll SCB_CPUID    REVISION      LL_CPUID_GetRevision
+  * @retval Value between 0 and 255 (0x1: patch 1)
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
+}
+
+/**
+  * @}
+  */
+
+#if __MPU_PRESENT
+/** @defgroup CORTEX_LL_EF_MPU MPU
+  * @{
+  */
+
+/**
+  * @brief  Enable MPU with input options
+  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Enable
+  * @param  Options This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
+  *         @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
+  *         @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
+  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
+{
+  /* Enable the MPU*/
+  WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
+  /* Ensure MPU settings take effects */
+  __DSB();
+  /* Sequence instruction fetches using update settings */
+  __ISB();
+}
+
+/**
+  * @brief  Disable MPU
+  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_Disable(void)
+{
+  /* Make sure outstanding transfers are done */
+  __DMB();
+  /* Disable MPU*/
+  WRITE_REG(MPU->CTRL, 0U);
+}
+
+/**
+  * @brief  Check if MPU is enabled or not
+  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
+{
+  return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable a MPU region
+  * @rmtoll MPU_RASR     ENABLE        LL_MPU_EnableRegion
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  *         @arg @ref LL_MPU_REGION_NUMBER8
+  *         @arg @ref LL_MPU_REGION_NUMBER9
+  *         @arg @ref LL_MPU_REGION_NUMBER10
+  *         @arg @ref LL_MPU_REGION_NUMBER11
+  *         @arg @ref LL_MPU_REGION_NUMBER12
+  *         @arg @ref LL_MPU_REGION_NUMBER13
+  *         @arg @ref LL_MPU_REGION_NUMBER14
+  *         @arg @ref LL_MPU_REGION_NUMBER15
+  * @note   For cortex-M4 only 8 regions are available i.e only values from LL_MPU_REGION_NUMBER0 to LL_MPU_REGION_NUMBER7 are possible.
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
+{
+  /* Set Region number */
+  WRITE_REG(MPU->RNR, Region);
+  /* Enable the MPU region */
+  SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+  * @brief  Configure and enable a region
+  * @rmtoll MPU_RNR      REGION        LL_MPU_ConfigRegion\n
+  *         MPU_RBAR     REGION        LL_MPU_ConfigRegion\n
+  *         MPU_RBAR     ADDR          LL_MPU_ConfigRegion\n
+  *         MPU_RASR     XN            LL_MPU_ConfigRegion\n
+  *         MPU_RASR     AP            LL_MPU_ConfigRegion\n
+  *         MPU_RASR     S             LL_MPU_ConfigRegion\n
+  *         MPU_RASR     C             LL_MPU_ConfigRegion\n
+  *         MPU_RASR     B             LL_MPU_ConfigRegion\n
+  *         MPU_RASR     SIZE          LL_MPU_ConfigRegion
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  *         @arg @ref LL_MPU_REGION_NUMBER8
+  *         @arg @ref LL_MPU_REGION_NUMBER9
+  *         @arg @ref LL_MPU_REGION_NUMBER10
+  *         @arg @ref LL_MPU_REGION_NUMBER11
+  *         @arg @ref LL_MPU_REGION_NUMBER12
+  *         @arg @ref LL_MPU_REGION_NUMBER13
+  *         @arg @ref LL_MPU_REGION_NUMBER14
+  *         @arg @ref LL_MPU_REGION_NUMBER15
+  * @param  Address Value of region base address
+  * @param  SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
+  * @param  Attributes This parameter can be a combination of the following values:
+  *         @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
+  *           or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
+  *           or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
+  *           or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
+  *           or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
+  *           or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
+  *         @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
+  *           or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
+  *         @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
+  *         @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or  @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
+  *         @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
+  *         @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
+  *         @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
+  * @note   For cortex-M4 only 8 regions are available i.e only values from LL_MPU_REGION_NUMBER0 to LL_MPU_REGION_NUMBER7 are possible.
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
+{
+  /* Set Region number */
+  WRITE_REG(MPU->RNR, Region);
+  /* Set base address */
+  WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
+  /* Configure MPU */
+  WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos)));
+}
+
+/**
+  * @brief  Disable a region
+  * @rmtoll MPU_RNR      REGION        LL_MPU_DisableRegion\n
+  *         MPU_RASR     ENABLE        LL_MPU_DisableRegion
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  *         @arg @ref LL_MPU_REGION_NUMBER8
+  *         @arg @ref LL_MPU_REGION_NUMBER9
+  *         @arg @ref LL_MPU_REGION_NUMBER10
+  *         @arg @ref LL_MPU_REGION_NUMBER11
+  *         @arg @ref LL_MPU_REGION_NUMBER12
+  *         @arg @ref LL_MPU_REGION_NUMBER13
+  *         @arg @ref LL_MPU_REGION_NUMBER14
+  *         @arg @ref LL_MPU_REGION_NUMBER15
+  * @note   For cortex-M4 only 8 regions are available i.e only values from LL_MPU_REGION_NUMBER0 to LL_MPU_REGION_NUMBER7 are possible.
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
+{
+  /* Set Region number */
+  WRITE_REG(MPU->RNR, Region);
+  /* Disable the MPU region */
+  CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+  * @}
+  */
+
+#endif /* __MPU_PRESENT */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_LL_CORTEX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_crs.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_crs.h
new file mode 100644
index 00000000..40baadd1
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_crs.h
@@ -0,0 +1,783 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_crs.h
+  * @author  MCD Application Team
+  * @brief   Header file of CRS LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_LL_CRS_H
+#define STM32H7xx_LL_CRS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined(CRS)
+
+/** @defgroup CRS_LL CRS
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
+  * @{
+  */
+
+/** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_CRS_ReadReg function
+  * @{
+  */
+#define LL_CRS_ISR_SYNCOKF                 CRS_ISR_SYNCOKF
+#define LL_CRS_ISR_SYNCWARNF               CRS_ISR_SYNCWARNF
+#define LL_CRS_ISR_ERRF                    CRS_ISR_ERRF
+#define LL_CRS_ISR_ESYNCF                  CRS_ISR_ESYNCF
+#define LL_CRS_ISR_SYNCERR                 CRS_ISR_SYNCERR
+#define LL_CRS_ISR_SYNCMISS                CRS_ISR_SYNCMISS
+#define LL_CRS_ISR_TRIMOVF                 CRS_ISR_TRIMOVF
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_CRS_ReadReg and  LL_CRS_WriteReg functions
+  * @{
+  */
+#define LL_CRS_CR_SYNCOKIE                 CRS_CR_SYNCOKIE
+#define LL_CRS_CR_SYNCWARNIE               CRS_CR_SYNCWARNIE
+#define LL_CRS_CR_ERRIE                    CRS_CR_ERRIE
+#define LL_CRS_CR_ESYNCIE                  CRS_CR_ESYNCIE
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
+  * @{
+  */
+#define LL_CRS_SYNC_DIV_1                  0x00000000U                               /*!< Synchro Signal not divided (default) */
+#define LL_CRS_SYNC_DIV_2                  CRS_CFGR_SYNCDIV_0                        /*!< Synchro Signal divided by 2 */
+#define LL_CRS_SYNC_DIV_4                  CRS_CFGR_SYNCDIV_1                        /*!< Synchro Signal divided by 4 */
+#define LL_CRS_SYNC_DIV_8                  (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
+#define LL_CRS_SYNC_DIV_16                 CRS_CFGR_SYNCDIV_2                        /*!< Synchro Signal divided by 16 */
+#define LL_CRS_SYNC_DIV_32                 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
+#define LL_CRS_SYNC_DIV_64                 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
+#define LL_CRS_SYNC_DIV_128                CRS_CFGR_SYNCDIV                          /*!< Synchro Signal divided by 128 */
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
+  * @{
+  */
+#define LL_CRS_SYNC_SOURCE_GPIO            0x00000000U             /*!< Synchro Signal soucre GPIO */
+#define LL_CRS_SYNC_SOURCE_LSE             CRS_CFGR_SYNCSRC_0      /*!< Synchro Signal source LSE */
+#define LL_CRS_SYNC_SOURCE_USB             CRS_CFGR_SYNCSRC_1      /*!< Synchro Signal source USB SOF (default)*/
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
+  * @{
+  */
+#define LL_CRS_SYNC_POLARITY_RISING        0x00000000U           /*!< Synchro Active on rising edge (default) */
+#define LL_CRS_SYNC_POLARITY_FALLING       CRS_CFGR_SYNCPOL      /*!< Synchro Active on falling edge */
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
+  * @{
+  */
+#define LL_CRS_FREQ_ERROR_DIR_UP           0x00000000U         /*!< Upcounting direction, the actual frequency is above the target */
+#define LL_CRS_FREQ_ERROR_DIR_DOWN         CRS_ISR_FEDIR       /*!< Downcounting direction, the actual frequency is below the target */
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
+  * @{
+  */
+/**
+  * @brief Reset value of the RELOAD field
+  * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz
+  *       and a synchronization signal frequency of 1 kHz (SOF signal from USB)
+  */
+#define LL_CRS_RELOADVALUE_DEFAULT         0x0000BB7FU
+
+/**
+  * @brief Reset value of Frequency error limit.
+  */
+#define LL_CRS_ERRORLIMIT_DEFAULT          0x00000022U
+
+/**
+  * @brief Reset value of the HSI48 Calibration field
+  * @note The default value is 64, which corresponds to the middle of the trimming interval.
+  *       The trimming step is specified in the product datasheet.
+  *       A higher TRIM value corresponds to a higher output frequency.
+  */
+#define LL_CRS_HSI48CALIBRATION_DEFAULT    0x00000020U
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
+  * @{
+  */
+
+/** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in CRS register
+  * @param  __INSTANCE__ CRS Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in CRS register
+  * @param  __INSTANCE__ CRS Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload
+  * @{
+  */
+
+/**
+  * @brief  Macro to calculate reload value to be set in CRS register according to target and sync frequencies
+  * @note   The RELOAD value should be selected according to the ratio between
+  *         the target frequency and the frequency of the synchronization source after
+  *         prescaling. It is then decreased by one in order to reach the expected
+  *         synchronization on the zero value. The formula is the following:
+  *              RELOAD = (fTARGET / fSYNC) -1
+  * @param  __FTARGET__ Target frequency (value in Hz)
+  * @param  __FSYNC__ Synchronization signal frequency (value in Hz)
+  * @retval Reload value (in Hz)
+  */
+#define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
+  * @{
+  */
+
+/** @defgroup CRS_LL_EF_Configuration Configuration
+  * @{
+  */
+
+/**
+  * @brief  Enable Frequency error counter
+  * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
+  * @rmtoll CR           CEN           LL_CRS_EnableFreqErrorCounter
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_CEN);
+}
+
+/**
+  * @brief  Disable Frequency error counter
+  * @rmtoll CR           CEN           LL_CRS_DisableFreqErrorCounter
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)
+{
+  CLEAR_BIT(CRS->CR, CRS_CR_CEN);
+}
+
+/**
+  * @brief  Check if Frequency error counter is enabled or not
+  * @rmtoll CR           CEN           LL_CRS_IsEnabledFreqErrorCounter
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
+{
+  return ((READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Automatic trimming counter
+  * @rmtoll CR           AUTOTRIMEN    LL_CRS_EnableAutoTrimming
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
+}
+
+/**
+  * @brief  Disable Automatic trimming counter
+  * @rmtoll CR           AUTOTRIMEN    LL_CRS_DisableAutoTrimming
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)
+{
+  CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
+}
+
+/**
+  * @brief  Check if Automatic trimming is enabled or not
+  * @rmtoll CR           AUTOTRIMEN    LL_CRS_IsEnabledAutoTrimming
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)
+{
+  return ((READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set HSI48 oscillator smooth trimming
+  * @note   When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
+  * @rmtoll CR           TRIM          LL_CRS_SetHSI48SmoothTrimming
+  * @param  Value a number between Min_Data = 0 and Max_Data = 127
+  * @note   Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
+{
+  MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos);
+}
+
+/**
+  * @brief  Get HSI48 oscillator smooth trimming
+  * @rmtoll CR           TRIM          LL_CRS_GetHSI48SmoothTrimming
+  * @retval a number between Min_Data = 0 and Max_Data = 127
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
+{
+  return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
+}
+
+/**
+  * @brief  Set counter reload value
+  * @rmtoll CFGR         RELOAD        LL_CRS_SetReloadCounter
+  * @param  Value a number between Min_Data = 0 and Max_Data = 0xFFFF
+  * @note   Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT
+  *         Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)
+{
+  MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
+}
+
+/**
+  * @brief  Get counter reload value
+  * @rmtoll CFGR         RELOAD        LL_CRS_GetReloadCounter
+  * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)
+{
+  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
+}
+
+/**
+  * @brief  Set frequency error limit
+  * @rmtoll CFGR         FELIM         LL_CRS_SetFreqErrorLimit
+  * @param  Value a number between Min_Data = 0 and Max_Data = 255
+  * @note   Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
+{
+  MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos);
+}
+
+/**
+  * @brief  Get frequency error limit
+  * @rmtoll CFGR         FELIM         LL_CRS_GetFreqErrorLimit
+  * @retval A number between Min_Data = 0 and Max_Data = 255
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
+{
+  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos);
+}
+
+/**
+  * @brief  Set division factor for SYNC signal
+  * @rmtoll CFGR         SYNCDIV       LL_CRS_SetSyncDivider
+  * @param  Divider This parameter can be one of the following values:
+  *         @arg @ref LL_CRS_SYNC_DIV_1
+  *         @arg @ref LL_CRS_SYNC_DIV_2
+  *         @arg @ref LL_CRS_SYNC_DIV_4
+  *         @arg @ref LL_CRS_SYNC_DIV_8
+  *         @arg @ref LL_CRS_SYNC_DIV_16
+  *         @arg @ref LL_CRS_SYNC_DIV_32
+  *         @arg @ref LL_CRS_SYNC_DIV_64
+  *         @arg @ref LL_CRS_SYNC_DIV_128
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)
+{
+  MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
+}
+
+/**
+  * @brief  Get division factor for SYNC signal
+  * @rmtoll CFGR         SYNCDIV       LL_CRS_GetSyncDivider
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_CRS_SYNC_DIV_1
+  *         @arg @ref LL_CRS_SYNC_DIV_2
+  *         @arg @ref LL_CRS_SYNC_DIV_4
+  *         @arg @ref LL_CRS_SYNC_DIV_8
+  *         @arg @ref LL_CRS_SYNC_DIV_16
+  *         @arg @ref LL_CRS_SYNC_DIV_32
+  *         @arg @ref LL_CRS_SYNC_DIV_64
+  *         @arg @ref LL_CRS_SYNC_DIV_128
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)
+{
+  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
+}
+
+/**
+  * @brief  Set SYNC signal source
+  * @rmtoll CFGR         SYNCSRC       LL_CRS_SetSyncSignalSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO
+  *         @arg @ref LL_CRS_SYNC_SOURCE_LSE
+  *         @arg @ref LL_CRS_SYNC_SOURCE_USB
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)
+{
+  MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
+}
+
+/**
+  * @brief  Get SYNC signal source
+  * @rmtoll CFGR         SYNCSRC       LL_CRS_GetSyncSignalSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO
+  *         @arg @ref LL_CRS_SYNC_SOURCE_LSE
+  *         @arg @ref LL_CRS_SYNC_SOURCE_USB
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)
+{
+  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
+}
+
+/**
+  * @brief  Set input polarity for the SYNC signal source
+  * @rmtoll CFGR         SYNCPOL       LL_CRS_SetSyncPolarity
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_CRS_SYNC_POLARITY_RISING
+  *         @arg @ref LL_CRS_SYNC_POLARITY_FALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)
+{
+  MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
+}
+
+/**
+  * @brief  Get input polarity for the SYNC signal source
+  * @rmtoll CFGR         SYNCPOL       LL_CRS_GetSyncPolarity
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_CRS_SYNC_POLARITY_RISING
+  *         @arg @ref LL_CRS_SYNC_POLARITY_FALLING
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
+{
+  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
+}
+
+/**
+  * @brief  Configure CRS for the synchronization
+  * @rmtoll CR           TRIM          LL_CRS_ConfigSynchronization\n
+  *         CFGR         RELOAD        LL_CRS_ConfigSynchronization\n
+  *         CFGR         FELIM         LL_CRS_ConfigSynchronization\n
+  *         CFGR         SYNCDIV       LL_CRS_ConfigSynchronization\n
+  *         CFGR         SYNCSRC       LL_CRS_ConfigSynchronization\n
+  *         CFGR         SYNCPOL       LL_CRS_ConfigSynchronization
+  * @param  HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63
+  * @param  ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF
+  * @param  ReloadValue a number between Min_Data = 0 and Max_Data = 255
+  * @param  Settings This parameter can be a combination of the following values:
+  *         @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8
+  *              or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128
+  *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB
+  *         @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings)
+{
+  MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue);
+  MODIFY_REG(CRS->CFGR,
+             CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
+             ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EF_CRS_Management CRS_Management
+  * @{
+  */
+
+/**
+  * @brief  Generate software SYNC event
+  * @rmtoll CR           SWSYNC        LL_CRS_GenerateEvent_SWSYNC
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_SWSYNC);
+}
+
+/**
+  * @brief  Get the frequency error direction latched in the time of the last
+  * SYNC event
+  * @rmtoll ISR          FEDIR         LL_CRS_GetFreqErrorDirection
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
+  *         @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)
+{
+  return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
+}
+
+/**
+  * @brief  Get the frequency error counter value latched in the time of the last SYNC event
+  * @rmtoll ISR          FECAP         LL_CRS_GetFreqErrorCapture
+  * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
+{
+  return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Check if SYNC event OK signal occurred or not
+  * @rmtoll ISR          SYNCOKF       LL_CRS_IsActiveFlag_SYNCOK
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
+{
+  return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if SYNC warning signal occurred or not
+  * @rmtoll ISR          SYNCWARNF     LL_CRS_IsActiveFlag_SYNCWARN
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
+{
+  return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Synchronization or trimming error signal occurred or not
+  * @rmtoll ISR          ERRF          LL_CRS_IsActiveFlag_ERR
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)
+{
+  return ((READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Expected SYNC signal occurred or not
+  * @rmtoll ISR          ESYNCF        LL_CRS_IsActiveFlag_ESYNC
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
+{
+  return ((READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if SYNC error signal occurred or not
+  * @rmtoll ISR          SYNCERR       LL_CRS_IsActiveFlag_SYNCERR
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
+{
+  return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if SYNC missed error signal occurred or not
+  * @rmtoll ISR          SYNCMISS      LL_CRS_IsActiveFlag_SYNCMISS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
+{
+  return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if Trimming overflow or underflow occurred or not
+  * @rmtoll ISR          TRIMOVF       LL_CRS_IsActiveFlag_TRIMOVF
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
+{
+  return ((READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the SYNC event OK flag
+  * @rmtoll ICR          SYNCOKC       LL_CRS_ClearFlag_SYNCOK
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)
+{
+  WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
+}
+
+/**
+  * @brief  Clear the  SYNC warning flag
+  * @rmtoll ICR          SYNCWARNC     LL_CRS_ClearFlag_SYNCWARN
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)
+{
+  WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
+}
+
+/**
+  * @brief  Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
+  * the ERR flag
+  * @rmtoll ICR          ERRC          LL_CRS_ClearFlag_ERR
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)
+{
+  WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
+}
+
+/**
+  * @brief  Clear Expected SYNC flag
+  * @rmtoll ICR          ESYNCC        LL_CRS_ClearFlag_ESYNC
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)
+{
+  WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRS_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable SYNC event OK interrupt
+  * @rmtoll CR           SYNCOKIE      LL_CRS_EnableIT_SYNCOK
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
+}
+
+/**
+  * @brief  Disable SYNC event OK interrupt
+  * @rmtoll CR           SYNCOKIE      LL_CRS_DisableIT_SYNCOK
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)
+{
+  CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
+}
+
+/**
+  * @brief  Check if SYNC event OK interrupt is enabled or not
+  * @rmtoll CR           SYNCOKIE      LL_CRS_IsEnabledIT_SYNCOK
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
+{
+  return ((READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable SYNC warning interrupt
+  * @rmtoll CR           SYNCWARNIE    LL_CRS_EnableIT_SYNCWARN
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
+}
+
+/**
+  * @brief  Disable SYNC warning interrupt
+  * @rmtoll CR           SYNCWARNIE    LL_CRS_DisableIT_SYNCWARN
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)
+{
+  CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
+}
+
+/**
+  * @brief  Check if SYNC warning interrupt is enabled or not
+  * @rmtoll CR           SYNCWARNIE    LL_CRS_IsEnabledIT_SYNCWARN
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
+{
+  return ((READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Synchronization or trimming error interrupt
+  * @rmtoll CR           ERRIE         LL_CRS_EnableIT_ERR
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_EnableIT_ERR(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_ERRIE);
+}
+
+/**
+  * @brief  Disable Synchronization or trimming error interrupt
+  * @rmtoll CR           ERRIE         LL_CRS_DisableIT_ERR
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_DisableIT_ERR(void)
+{
+  CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
+}
+
+/**
+  * @brief  Check if Synchronization or trimming error interrupt is enabled or not
+  * @rmtoll CR           ERRIE         LL_CRS_IsEnabledIT_ERR
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)
+{
+  return ((READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Expected SYNC interrupt
+  * @rmtoll CR           ESYNCIE       LL_CRS_EnableIT_ESYNC
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
+}
+
+/**
+  * @brief  Disable Expected SYNC interrupt
+  * @rmtoll CR           ESYNCIE       LL_CRS_DisableIT_ESYNC
+  * @retval None
+  */
+__STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)
+{
+  CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
+}
+
+/**
+  * @brief  Check if Expected SYNC interrupt is enabled or not
+  * @rmtoll CR           ESYNCIE       LL_CRS_IsEnabledIT_ESYNC
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
+{
+  return ((READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_CRS_DeInit(void);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(CRS) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_LL_CRS_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma.h
new file mode 100644
index 00000000..342f7d4e
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma.h
@@ -0,0 +1,3246 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_dma.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMA LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_LL_DMA_H
+#define STM32H7xx_LL_DMA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+#include "stm32h7xx_ll_dmamux.h"
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined (DMA1) || defined (DMA2)
+
+/** @defgroup DMA_LL DMA
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup DMA_LL_Private_Variables DMA Private Variables
+  * @{
+  */
+/* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */
+static const uint8_t LL_DMA_STR_OFFSET_TAB[] =
+{
+  (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE)
+};
+
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+
+/**
+  * @brief  Helper macro to convert DMA Instance DMAx into DMAMUX channel
+  * @note   DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7.
+  *         DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7.
+  * @param  __DMA_INSTANCE__ DMAx
+  * @retval Channel_Offset (LL_DMAMUX_CHANNEL_8 or 0).
+  */
+#define LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__)   \
+(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0UL : 8UL)
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
+  * @{
+  */
+typedef struct
+{
+  uint32_t PeriphOrM2MSrcAddress;  /*!< Specifies the peripheral base address for DMA transfer
+                                        or as Source base address in case of memory to memory transfer direction.
+
+                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
+
+  uint32_t MemoryOrM2MDstAddress;  /*!< Specifies the memory base address for DMA transfer
+                                        or as Destination base address in case of memory to memory transfer direction.
+
+                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
+
+  uint32_t Direction;              /*!< Specifies if the data will be transferred from memory to peripheral,
+                                        from memory to memory or from peripheral to memory.
+                                        This parameter can be a value of @ref DMA_LL_EC_DIRECTION
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
+
+  uint32_t Mode;                   /*!< Specifies the normal or circular operation mode.
+                                        This parameter can be a value of @ref DMA_LL_EC_MODE
+                                        @note The circular buffer mode cannot be used if the memory to memory
+                                              data transfer direction is configured on the selected Stream
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
+
+  uint32_t PeriphOrM2MSrcIncMode;  /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
+                                        is incremented or not.
+                                        This parameter can be a value of @ref DMA_LL_EC_PERIPH
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
+
+  uint32_t MemoryOrM2MDstIncMode;  /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
+                                        is incremented or not.
+                                        This parameter can be a value of @ref DMA_LL_EC_MEMORY
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
+
+  uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
+                                        in case of memory to memory transfer direction.
+                                        This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
+
+  uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
+                                        in case of memory to memory transfer direction.
+                                        This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
+
+  uint32_t NbData;                 /*!< Specifies the number of data to transfer, in data unit.
+                                        The data unit is equal to the source buffer configuration set in PeripheralSize
+                                        or MemorySize parameters depending in the transfer direction.
+                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
+
+  uint32_t PeriphRequest;          /*!< Specifies the peripheral request.
+                                        This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
+
+  uint32_t Priority;               /*!< Specifies the channel priority level.
+                                        This parameter can be a value of @ref DMA_LL_EC_PRIORITY
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */
+
+  uint32_t FIFOMode;               /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
+                                        This parameter can be a value of @ref DMA_LL_FIFOMODE
+                                        @note The Direct mode (FIFO mode disabled) cannot be used if the
+                                        memory-to-memory data transfer is configured on the selected stream
+
+                                        This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */
+
+  uint32_t FIFOThreshold;          /*!< Specifies the FIFO threshold level.
+                                        This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */
+
+  uint32_t MemBurst;               /*!< Specifies the Burst transfer configuration for the memory transfers.
+                                        It specifies the amount of data to be transferred in a single non interruptible
+                                        transaction.
+                                        This parameter can be a value of @ref DMA_LL_EC_MBURST
+                                        @note The burst mode is possible only if the address Increment mode is enabled.
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */
+
+  uint32_t PeriphBurst;            /*!< Specifies the Burst transfer configuration for the peripheral transfers.
+                                        It specifies the amount of data to be transferred in a single non interruptible
+                                        transaction.
+                                        This parameter can be a value of @ref DMA_LL_EC_PBURST
+                                        @note The burst mode is possible only if the address Increment mode is enabled.
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */
+
+} LL_DMA_InitTypeDef;
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
+  * @{
+  */
+
+/** @defgroup DMA_LL_EC_STREAM STREAM
+  * @{
+  */
+#define LL_DMA_STREAM_0                   0x00000000U
+#define LL_DMA_STREAM_1                   0x00000001U
+#define LL_DMA_STREAM_2                   0x00000002U
+#define LL_DMA_STREAM_3                   0x00000003U
+#define LL_DMA_STREAM_4                   0x00000004U
+#define LL_DMA_STREAM_5                   0x00000005U
+#define LL_DMA_STREAM_6                   0x00000006U
+#define LL_DMA_STREAM_7                   0x00000007U
+#define LL_DMA_STREAM_ALL                 0xFFFF0000U
+/**
+  * @}
+  */
+
+
+/** @defgroup DMA_LL_EC_DIRECTION DIRECTION
+  * @{
+  */
+#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U               /*!< Peripheral to memory direction */
+#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0            /*!< Memory to peripheral direction */
+#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1            /*!< Memory to memory direction     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_MODE MODE
+  * @{
+  */
+#define LL_DMA_MODE_NORMAL                0x00000000U               /*!< Normal Mode                  */
+#define LL_DMA_MODE_CIRCULAR              DMA_SxCR_CIRC             /*!< Circular Mode                */
+#define LL_DMA_MODE_PFCTRL                DMA_SxCR_PFCTRL           /*!< Peripheral flow control mode */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE
+  * @{
+  */
+#define LL_DMA_DOUBLEBUFFER_MODE_DISABLE  0x00000000U               /*!< Disable double buffering mode */
+#define LL_DMA_DOUBLEBUFFER_MODE_ENABLE   DMA_SxCR_DBM              /*!< Enable double buffering mode  */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_PERIPH PERIPH
+  * @{
+  */
+#define LL_DMA_PERIPH_NOINCREMENT         0x00000000U               /*!< Peripheral increment mode Disable */
+#define LL_DMA_PERIPH_INCREMENT           DMA_SxCR_PINC             /*!< Peripheral increment mode Enable  */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_MEMORY MEMORY
+  * @{
+  */
+#define LL_DMA_MEMORY_NOINCREMENT         0x00000000U               /*!< Memory increment mode Disable */
+#define LL_DMA_MEMORY_INCREMENT           DMA_SxCR_MINC             /*!< Memory increment mode Enable  */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN
+  * @{
+  */
+#define LL_DMA_PDATAALIGN_BYTE            0x00000000U               /*!< Peripheral data alignment : Byte     */
+#define LL_DMA_PDATAALIGN_HALFWORD        DMA_SxCR_PSIZE_0          /*!< Peripheral data alignment : HalfWord */
+#define LL_DMA_PDATAALIGN_WORD            DMA_SxCR_PSIZE_1          /*!< Peripheral data alignment : Word     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN
+  * @{
+  */
+#define LL_DMA_MDATAALIGN_BYTE            0x00000000U               /*!< Memory data alignment : Byte     */
+#define LL_DMA_MDATAALIGN_HALFWORD        DMA_SxCR_MSIZE_0          /*!< Memory data alignment : HalfWord */
+#define LL_DMA_MDATAALIGN_WORD            DMA_SxCR_MSIZE_1          /*!< Memory data alignment : Word     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE
+  * @{
+  */
+#define LL_DMA_OFFSETSIZE_PSIZE           0x00000000U               /*!< Peripheral increment offset size is linked to the PSIZE           */
+#define LL_DMA_OFFSETSIZE_FIXEDTO4        DMA_SxCR_PINCOS           /*!< Peripheral increment offset size is fixed to 4 (32-bit alignment) */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_PRIORITY PRIORITY
+  * @{
+  */
+#define LL_DMA_PRIORITY_LOW               0x00000000U               /*!< Priority level : Low       */
+#define LL_DMA_PRIORITY_MEDIUM            DMA_SxCR_PL_0             /*!< Priority level : Medium    */
+#define LL_DMA_PRIORITY_HIGH              DMA_SxCR_PL_1             /*!< Priority level : High      */
+#define LL_DMA_PRIORITY_VERYHIGH          DMA_SxCR_PL               /*!< Priority level : Very_High */
+/**
+  * @}
+  */
+
+
+/** @defgroup DMA_LL_EC_MBURST MBURST
+  * @{
+  */
+#define LL_DMA_MBURST_SINGLE              0x00000000U                             /*!< Memory burst single transfer configuration      */
+#define LL_DMA_MBURST_INC4                DMA_SxCR_MBURST_0                       /*!< Memory burst of 4 beats transfer configuration  */
+#define LL_DMA_MBURST_INC8                DMA_SxCR_MBURST_1                       /*!< Memory burst of 8 beats transfer configuration  */
+#define LL_DMA_MBURST_INC16               (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst of 16 beats transfer configuration */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_PBURST PBURST
+  * @{
+  */
+#define LL_DMA_PBURST_SINGLE              0x00000000U                             /*!< Peripheral burst single transfer configuration      */
+#define LL_DMA_PBURST_INC4                DMA_SxCR_PBURST_0                       /*!< Peripheral burst of 4 beats transfer configuration  */
+#define LL_DMA_PBURST_INC8                DMA_SxCR_PBURST_1                       /*!< Peripheral burst of 8 beats transfer configuration  */
+#define LL_DMA_PBURST_INC16               (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral burst of 16 beats transfer configuration */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE
+  * @{
+  */
+#define LL_DMA_FIFOMODE_DISABLE           0x00000000U                             /*!< FIFO mode disable (direct mode is enabled) */
+#define LL_DMA_FIFOMODE_ENABLE            DMA_SxFCR_DMDIS                         /*!< FIFO mode enable                           */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0
+  * @{
+  */
+#define LL_DMA_FIFOSTATUS_0_25            0x00000000U                             /*!< 0 < fifo_level < 1/4    */
+#define LL_DMA_FIFOSTATUS_25_50           DMA_SxFCR_FS_0                          /*!< 1/4 < fifo_level < 1/2  */
+#define LL_DMA_FIFOSTATUS_50_75           DMA_SxFCR_FS_1                          /*!< 1/2 < fifo_level < 3/4  */
+#define LL_DMA_FIFOSTATUS_75_100          (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0)       /*!< 3/4 < fifo_level < full */
+#define LL_DMA_FIFOSTATUS_EMPTY           DMA_SxFCR_FS_2                          /*!< FIFO is empty           */
+#define LL_DMA_FIFOSTATUS_FULL            (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0)       /*!< FIFO is full            */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD
+  * @{
+  */
+#define LL_DMA_FIFOTHRESHOLD_1_4          0x00000000U                             /*!< FIFO threshold 1 quart full configuration  */
+#define LL_DMA_FIFOTHRESHOLD_1_2          DMA_SxFCR_FTH_0                         /*!< FIFO threshold half full configuration     */
+#define LL_DMA_FIFOTHRESHOLD_3_4          DMA_SxFCR_FTH_1                         /*!< FIFO threshold 3 quarts full configuration */
+#define LL_DMA_FIFOTHRESHOLD_FULL         DMA_SxFCR_FTH                           /*!< FIFO threshold full configuration          */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
+  * @{
+  */
+#define LL_DMA_CURRENTTARGETMEM0          0x00000000U                             /*!< Set CurrentTarget Memory to Memory 0  */
+#define LL_DMA_CURRENTTARGETMEM1          DMA_SxCR_CT                             /*!< Set CurrentTarget Memory to Memory 1  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
+  * @{
+  */
+
+/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
+  * @{
+  */
+/**
+  * @brief  Write a value in DMA register
+  * @param  __INSTANCE__ DMA Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in DMA register
+  * @param  __INSTANCE__ DMA Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy
+  * @{
+  */
+/**
+  * @brief  Convert DMAx_Streamy into DMAx
+  * @param  __STREAM_INSTANCE__ DMAx_Streamy
+  * @retval DMAx
+  */
+#define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__)   \
+(((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ?  DMA2 : DMA1)
+
+/**
+  * @brief  Convert DMAx_Streamy into LL_DMA_STREAM_y
+  * @param  __STREAM_INSTANCE__ DMAx_Streamy
+  * @retval LL_DMA_STREAM_y
+  */
+#define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__)   \
+(((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \
+ LL_DMA_STREAM_7)
+
+/**
+  * @brief  Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy
+  * @param  __DMA_INSTANCE__ DMAx
+  * @param  __STREAM__ LL_DMA_STREAM_y
+  * @retval DMAx_Streamy
+  */
+#define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__)   \
+((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \
+ DMA2_Stream7)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
+ * @{
+ */
+
+/** @defgroup DMA_LL_EF_Configuration Configuration
+  * @{
+  */
+/**
+  * @brief Enable DMA stream.
+  * @rmtoll CR          EN            LL_DMA_EnableStream
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN);
+}
+
+/**
+  * @brief Disable DMA stream.
+  * @rmtoll CR          EN            LL_DMA_DisableStream
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN);
+}
+
+/**
+  * @brief Check if DMA stream is enabled or disabled.
+  * @rmtoll CR          EN            LL_DMA_IsEnabledStream
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure all parameters linked to DMA transfer.
+  * @rmtoll CR          DIR           LL_DMA_ConfigTransfer\n
+  *         CR          CIRC          LL_DMA_ConfigTransfer\n
+  *         CR          PINC          LL_DMA_ConfigTransfer\n
+  *         CR          MINC          LL_DMA_ConfigTransfer\n
+  *         CR          PSIZE         LL_DMA_ConfigTransfer\n
+  *         CR          MSIZE         LL_DMA_ConfigTransfer\n
+  *         CR          PL            LL_DMA_ConfigTransfer\n
+  *         CR          PFCTRL        LL_DMA_ConfigTransfer
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Configuration This parameter must be a combination of all the following values:
+  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+  *         @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR  or @ref LL_DMA_MODE_PFCTRL
+  *         @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
+  *         @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
+  *         @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
+  *         @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
+  *         @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
+  *@retval None
+  */
+__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR,
+             DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL,
+             Configuration);
+}
+
+/**
+  * @brief Set Data transfer direction (read from peripheral or from memory).
+  * @rmtoll CR          DIR           LL_DMA_SetDataTransferDirection
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Direction This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Direction)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DIR, Direction);
+}
+
+/**
+  * @brief Get Data transfer direction (read from peripheral or from memory).
+  * @rmtoll CR          DIR           LL_DMA_GetDataTransferDirection
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DIR));
+}
+
+/**
+  * @brief Set DMA mode normal, circular or peripheral flow control.
+  * @rmtoll CR          CIRC           LL_DMA_SetMode\n
+  *         CR          PFCTRL         LL_DMA_SetMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_MODE_NORMAL
+  *         @arg @ref LL_DMA_MODE_CIRCULAR
+  *         @arg @ref LL_DMA_MODE_PFCTRL
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL, Mode);
+}
+
+/**
+  * @brief Get DMA mode normal, circular or peripheral flow control.
+  * @rmtoll CR          CIRC           LL_DMA_GetMode\n
+  *         CR          PFCTRL         LL_DMA_GetMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_MODE_NORMAL
+  *         @arg @ref LL_DMA_MODE_CIRCULAR
+  *         @arg @ref LL_DMA_MODE_PFCTRL
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL));
+}
+
+/**
+  * @brief Set Peripheral increment mode.
+  * @rmtoll CR          PINC           LL_DMA_SetPeriphIncMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  IncrementMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
+  *         @arg @ref LL_DMA_PERIPH_INCREMENT
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINC, IncrementMode);
+}
+
+/**
+  * @brief Get Peripheral increment mode.
+  * @rmtoll CR          PINC           LL_DMA_GetPeriphIncMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
+  *         @arg @ref LL_DMA_PERIPH_INCREMENT
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINC));
+}
+
+/**
+  * @brief Set Memory increment mode.
+  * @rmtoll CR          MINC           LL_DMA_SetMemoryIncMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  IncrementMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
+  *         @arg @ref LL_DMA_MEMORY_INCREMENT
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MINC, IncrementMode);
+}
+
+/**
+  * @brief Get Memory increment mode.
+  * @rmtoll CR          MINC           LL_DMA_GetMemoryIncMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
+  *         @arg @ref LL_DMA_MEMORY_INCREMENT
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MINC));
+}
+
+/**
+  * @brief Set Peripheral size.
+  * @rmtoll CR          PSIZE           LL_DMA_SetPeriphSize
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Size This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_PDATAALIGN_BYTE
+  *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
+  *         @arg @ref LL_DMA_PDATAALIGN_WORD
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Size)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PSIZE, Size);
+}
+
+/**
+  * @brief Get Peripheral size.
+  * @rmtoll CR          PSIZE           LL_DMA_GetPeriphSize
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_PDATAALIGN_BYTE
+  *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
+  *         @arg @ref LL_DMA_PDATAALIGN_WORD
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PSIZE));
+}
+
+/**
+  * @brief Set Memory size.
+  * @rmtoll CR          MSIZE           LL_DMA_SetMemorySize
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Size This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_MDATAALIGN_BYTE
+  *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
+  *         @arg @ref LL_DMA_MDATAALIGN_WORD
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Size)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MSIZE, Size);
+}
+
+/**
+  * @brief Get Memory size.
+  * @rmtoll CR          MSIZE           LL_DMA_GetMemorySize
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_MDATAALIGN_BYTE
+  *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
+  *         @arg @ref LL_DMA_MDATAALIGN_WORD
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MSIZE));
+}
+
+/**
+  * @brief Set Peripheral increment offset size.
+  * @rmtoll CR          PINCOS           LL_DMA_SetIncOffsetSize
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  OffsetSize This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_OFFSETSIZE_PSIZE
+  *         @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINCOS, OffsetSize);
+}
+
+/**
+  * @brief Get Peripheral increment offset size.
+  * @rmtoll CR          PINCOS           LL_DMA_GetIncOffsetSize
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_OFFSETSIZE_PSIZE
+  *         @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINCOS));
+}
+
+/**
+  * @brief Set Stream priority level.
+  * @rmtoll CR          PL           LL_DMA_SetStreamPriorityLevel
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Priority This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_PRIORITY_LOW
+  *         @arg @ref LL_DMA_PRIORITY_MEDIUM
+  *         @arg @ref LL_DMA_PRIORITY_HIGH
+  *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Priority)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PL, Priority);
+}
+
+/**
+  * @brief Get Stream priority level.
+  * @rmtoll CR          PL           LL_DMA_GetStreamPriorityLevel
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_PRIORITY_LOW
+  *         @arg @ref LL_DMA_PRIORITY_MEDIUM
+  *         @arg @ref LL_DMA_PRIORITY_HIGH
+  *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PL));
+}
+
+/**
+  * @brief Enable DMA stream bufferable transfer.
+  * @rmtoll CR          TRBUFF            LL_DMA_EnableBufferableTransfer
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableBufferableTransfer(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TRBUFF);
+}
+
+/**
+  * @brief Disable DMA stream bufferable transfer.
+  * @rmtoll CR          TRBUFF            LL_DMA_DisableBufferableTransfer
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableBufferableTransfer(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TRBUFF);
+}
+
+/**
+  * @brief Set Number of data to transfer.
+  * @rmtoll NDTR          NDT           LL_DMA_SetDataLength
+  * @note   This action has no effect if
+  *         stream is enabled.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  NbData Between 0 to 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t NbData)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->NDTR, DMA_SxNDT, NbData);
+}
+
+/**
+  * @brief Get Number of data to transfer.
+  * @rmtoll NDTR          NDT           LL_DMA_GetDataLength
+  * @note   Once the stream is enabled, the return value indicate the
+  *         remaining bytes to be transmitted.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Between 0 to 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->NDTR, DMA_SxNDT));
+}
+/**
+  * @brief  Set DMA request for DMA Streams on DMAMUX Channel x.
+  * @note   DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7.
+  *         DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7.
+  * @rmtoll CxCR         DMAREQ_ID     LL_DMA_SetPeriphRequest
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Request This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX1_REQ_MEM2MEM
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR0
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR1
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR2
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR3
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR4
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR5
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR6
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR7
+  *         @arg @ref LL_DMAMUX1_REQ_ADC1
+  *         @arg @ref LL_DMAMUX1_REQ_ADC2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_COM
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_UP
+  *         @arg @ref LL_DMAMUX1_REQ_I2C1_RX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C1_TX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C2_RX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C2_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI1_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI1_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI2_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI2_TX
+  *         @arg @ref LL_DMAMUX1_REQ_USART1_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART1_TX
+  *         @arg @ref LL_DMAMUX1_REQ_USART2_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART2_TX
+  *         @arg @ref LL_DMAMUX1_REQ_USART3_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART3_TX
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_COM
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_SPI3_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI3_TX
+  *         @arg @ref LL_DMAMUX1_REQ_UART4_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART4_TX
+  *         @arg @ref LL_DMAMUX1_REQ_UART5_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART5_TX
+  *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM6_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM7_UP
+  *         @arg @ref LL_DMAMUX1_REQ_USART6_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART6_TX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C3_RX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C3_TX
+  *         @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI
+  *         @arg @ref LL_DMAMUX1_REQ_CRYP_IN
+  *         @arg @ref LL_DMAMUX1_REQ_CRYP_OUT
+  *         @arg @ref LL_DMAMUX1_REQ_HASH_IN
+  *         @arg @ref LL_DMAMUX1_REQ_UART7_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART7_TX
+  *         @arg @ref LL_DMAMUX1_REQ_UART8_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART8_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI4_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI4_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI5_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI5_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SAI1_A
+  *         @arg @ref LL_DMAMUX1_REQ_SAI1_B
+  *         @arg @ref LL_DMAMUX1_REQ_SAI2_A
+  *         @arg @ref LL_DMAMUX1_REQ_SAI2_B
+  *         @arg @ref LL_DMAMUX1_REQ_SWPMI_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SWPMI_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
+  *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*)
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_COM
+  *         @arg @ref LL_DMAMUX1_REQ_TIM16_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM16_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM17_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM17_UP
+  *         @arg @ref LL_DMAMUX1_REQ_SAI3_A (*)
+  *         @arg @ref LL_DMAMUX1_REQ_SAI3_B (*)
+  *         @arg @ref LL_DMAMUX1_REQ_ADC3 (*)
+  *         @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
+  *         @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
+  *         @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
+  *         @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
+  * @note   (*) Availability depends on devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Request)
+{
+  MODIFY_REG(((DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Stream)) + (uint32_t)(DMAMUX_CCR_SIZE * LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
+}
+
+/**
+  * @brief  Get DMA request for DMA Channels on DMAMUX Channel x.
+  * @note   DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7.
+  *         DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7.
+  * @rmtoll CxCR         DMAREQ_ID     LL_DMA_GetPeriphRequest
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMAMUX1_REQ_MEM2MEM
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR0
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR1
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR2
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR3
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR4
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR5
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR6
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR7
+  *         @arg @ref LL_DMAMUX1_REQ_ADC1
+  *         @arg @ref LL_DMAMUX1_REQ_ADC2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_COM
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_UP
+  *         @arg @ref LL_DMAMUX1_REQ_I2C1_RX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C1_TX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C2_RX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C2_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI1_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI1_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI2_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI2_TX
+  *         @arg @ref LL_DMAMUX1_REQ_USART1_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART1_TX
+  *         @arg @ref LL_DMAMUX1_REQ_USART2_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART2_TX
+  *         @arg @ref LL_DMAMUX1_REQ_USART3_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART3_TX
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_COM
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_SPI3_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI3_TX
+  *         @arg @ref LL_DMAMUX1_REQ_UART4_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART4_TX
+  *         @arg @ref LL_DMAMUX1_REQ_UART5_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART5_TX
+  *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM6_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM7_UP
+  *         @arg @ref LL_DMAMUX1_REQ_USART6_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART6_TX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C3_RX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C3_TX
+  *         @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI
+  *         @arg @ref LL_DMAMUX1_REQ_CRYP_IN
+  *         @arg @ref LL_DMAMUX1_REQ_CRYP_OUT
+  *         @arg @ref LL_DMAMUX1_REQ_HASH_IN
+  *         @arg @ref LL_DMAMUX1_REQ_UART7_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART7_TX
+  *         @arg @ref LL_DMAMUX1_REQ_UART8_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART8_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI4_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI4_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI5_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI5_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SAI1_A
+  *         @arg @ref LL_DMAMUX1_REQ_SAI1_B
+  *         @arg @ref LL_DMAMUX1_REQ_SAI2_A
+  *         @arg @ref LL_DMAMUX1_REQ_SAI2_B
+  *         @arg @ref LL_DMAMUX1_REQ_SWPMI_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SWPMI_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
+  *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*)
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_COM
+  *         @arg @ref LL_DMAMUX1_REQ_TIM16_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM16_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM17_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM17_UP
+  *         @arg @ref LL_DMAMUX1_REQ_SAI3_A (*)
+  *         @arg @ref LL_DMAMUX1_REQ_SAI3_B (*)
+  *         @arg @ref LL_DMAMUX1_REQ_ADC3 (*)
+  *         @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
+  *         @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
+  *         @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
+  *         @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
+  * @note   (*) Availability depends on devices.
+  */
+__STATIC_INLINE  uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Stream)) + (uint32_t)(DMAMUX_CCR_SIZE * LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx)))))->CCR, DMAMUX_CxCR_DMAREQ_ID));
+}
+
+/**
+  * @brief Set Memory burst transfer configuration.
+  * @rmtoll CR          MBURST           LL_DMA_SetMemoryBurstxfer
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Mburst This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_MBURST_SINGLE
+  *         @arg @ref LL_DMA_MBURST_INC4
+  *         @arg @ref LL_DMA_MBURST_INC8
+  *         @arg @ref LL_DMA_MBURST_INC16
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MBURST, Mburst);
+}
+
+/**
+  * @brief Get Memory burst transfer configuration.
+  * @rmtoll CR          MBURST           LL_DMA_GetMemoryBurstxfer
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_MBURST_SINGLE
+  *         @arg @ref LL_DMA_MBURST_INC4
+  *         @arg @ref LL_DMA_MBURST_INC8
+  *         @arg @ref LL_DMA_MBURST_INC16
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MBURST));
+}
+
+/**
+  * @brief Set  Peripheral burst transfer configuration.
+  * @rmtoll CR          PBURST           LL_DMA_SetPeriphBurstxfer
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Pburst This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_PBURST_SINGLE
+  *         @arg @ref LL_DMA_PBURST_INC4
+  *         @arg @ref LL_DMA_PBURST_INC8
+  *         @arg @ref LL_DMA_PBURST_INC16
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PBURST, Pburst);
+}
+
+/**
+  * @brief Get Peripheral burst transfer configuration.
+  * @rmtoll CR          PBURST           LL_DMA_GetPeriphBurstxfer
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_PBURST_SINGLE
+  *         @arg @ref LL_DMA_PBURST_INC4
+  *         @arg @ref LL_DMA_PBURST_INC8
+  *         @arg @ref LL_DMA_PBURST_INC16
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PBURST));
+}
+
+/**
+  * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
+  * @rmtoll CR          CT           LL_DMA_SetCurrentTargetMem
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param CurrentMemory This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CURRENTTARGETMEM0
+  *         @arg @ref LL_DMA_CURRENTTARGETMEM1
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CT, CurrentMemory);
+}
+
+/**
+  * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
+  * @rmtoll CR          CT           LL_DMA_GetCurrentTargetMem
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_CURRENTTARGETMEM0
+  *         @arg @ref LL_DMA_CURRENTTARGETMEM1
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CT));
+}
+
+/**
+  * @brief Enable the double buffer mode.
+  * @rmtoll CR          DBM           LL_DMA_EnableDoubleBufferMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM);
+}
+
+/**
+  * @brief Disable the double buffer mode.
+  * @rmtoll CR          DBM           LL_DMA_DisableDoubleBufferMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM);
+}
+
+/**
+  * @brief Get FIFO status.
+  * @rmtoll FCR          FS          LL_DMA_GetFIFOStatus
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_FIFOSTATUS_0_25
+  *         @arg @ref LL_DMA_FIFOSTATUS_25_50
+  *         @arg @ref LL_DMA_FIFOSTATUS_50_75
+  *         @arg @ref LL_DMA_FIFOSTATUS_75_100
+  *         @arg @ref LL_DMA_FIFOSTATUS_EMPTY
+  *         @arg @ref LL_DMA_FIFOSTATUS_FULL
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FS));
+}
+
+/**
+  * @brief Disable Fifo mode.
+  * @rmtoll FCR          DMDIS          LL_DMA_DisableFifoMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_DMDIS);
+}
+
+/**
+  * @brief Enable Fifo mode.
+  * @rmtoll FCR          DMDIS          LL_DMA_EnableFifoMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_DMDIS);
+}
+
+/**
+  * @brief Select FIFO threshold.
+  * @rmtoll FCR         FTH          LL_DMA_SetFIFOThreshold
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Threshold This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH, Threshold);
+}
+
+/**
+  * @brief Get FIFO threshold.
+  * @rmtoll FCR         FTH          LL_DMA_GetFIFOThreshold
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH));
+}
+
+/**
+  * @brief Configure the FIFO .
+  * @rmtoll FCR         FTH          LL_DMA_ConfigFifo\n
+  *         FCR         DMDIS        LL_DMA_ConfigFifo
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  FifoMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_FIFOMODE_ENABLE
+  *         @arg @ref LL_DMA_FIFOMODE_DISABLE
+  * @param  FifoThreshold This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH | DMA_SxFCR_DMDIS, FifoMode | FifoThreshold);
+}
+
+/**
+  * @brief Configure the Source and Destination addresses.
+  * @note   This API must not be called when the DMA stream is enabled.
+  * @rmtoll M0AR        M0A         LL_DMA_ConfigAddresses\n
+  *         PAR         PA          LL_DMA_ConfigAddresses
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  SrcAddress Between 0 to 0xFFFFFFFF
+  * @param  DstAddress Between 0 to 0xFFFFFFFF
+  * @param  Direction This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  /* Direction Memory to Periph */
+  if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
+  {
+    WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, SrcAddress);
+    WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, DstAddress);
+  }
+  /* Direction Periph to Memory and Memory to Memory */
+  else
+  {
+    WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, SrcAddress);
+    WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, DstAddress);
+  }
+}
+
+/**
+  * @brief  Set the Memory address.
+  * @rmtoll M0AR        M0A         LL_DMA_SetMemoryAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+  * @note   This API must not be called when the DMA stream is enabled.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  MemoryAddress Between 0 to 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, MemoryAddress);
+}
+
+/**
+  * @brief  Set the Peripheral address.
+  * @rmtoll PAR        PA         LL_DMA_SetPeriphAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+  * @note   This API must not be called when the DMA stream is enabled.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  PeriphAddress Between 0 to 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t PeriphAddress)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, PeriphAddress);
+}
+
+/**
+  * @brief  Get the Memory address.
+  * @rmtoll M0AR        M0A         LL_DMA_GetMemoryAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Between 0 to 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR));
+}
+
+/**
+  * @brief  Get the Peripheral address.
+  * @rmtoll PAR        PA         LL_DMA_GetPeriphAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Between 0 to 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR));
+}
+
+/**
+  * @brief  Set the Memory to Memory Source address.
+  * @rmtoll PAR        PA         LL_DMA_SetM2MSrcAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+  * @note   This API must not be called when the DMA stream is enabled.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  MemoryAddress Between 0 to 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, MemoryAddress);
+}
+
+/**
+  * @brief  Set the Memory to Memory Destination address.
+  * @rmtoll M0AR        M0A         LL_DMA_SetM2MDstAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+  * @note   This API must not be called when the DMA stream is enabled.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  MemoryAddress Between 0 to 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, MemoryAddress);
+}
+
+/**
+  * @brief  Get the Memory to Memory Source address.
+  * @rmtoll PAR        PA         LL_DMA_GetM2MSrcAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Between 0 to 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR));
+}
+
+/**
+  * @brief  Get the Memory to Memory Destination address.
+  * @rmtoll M0AR        M0A         LL_DMA_GetM2MDstAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Between 0 to 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR));
+}
+
+/**
+  * @brief Set Memory 1 address (used in case of Double buffer mode).
+  * @rmtoll M1AR        M1A         LL_DMA_SetMemory1Address
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Address Between 0 to 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M1AR, DMA_SxM1AR_M1A, Address);
+}
+
+/**
+  * @brief Get Memory 1 address (used in case of Double buffer mode).
+  * @rmtoll M1AR        M1A         LL_DMA_GetMemory1Address
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Between 0 to 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return (((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M1AR);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief Get Stream 0 half transfer flag.
+  * @rmtoll LISR  HTIF0    LL_DMA_IsActiveFlag_HT0
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF0) == (DMA_LISR_HTIF0)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 1 half transfer flag.
+  * @rmtoll LISR  HTIF1    LL_DMA_IsActiveFlag_HT1
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF1) == (DMA_LISR_HTIF1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 2 half transfer flag.
+  * @rmtoll LISR  HTIF2    LL_DMA_IsActiveFlag_HT2
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF2) == (DMA_LISR_HTIF2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 3 half transfer flag.
+  * @rmtoll LISR  HTIF3    LL_DMA_IsActiveFlag_HT3
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF3) == (DMA_LISR_HTIF3)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 4 half transfer flag.
+  * @rmtoll HISR  HTIF4    LL_DMA_IsActiveFlag_HT4
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF4) == (DMA_HISR_HTIF4)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 5 half transfer flag.
+  * @rmtoll HISR  HTIF0    LL_DMA_IsActiveFlag_HT5
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF5) == (DMA_HISR_HTIF5)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 6 half transfer flag.
+  * @rmtoll HISR  HTIF6    LL_DMA_IsActiveFlag_HT6
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF6) == (DMA_HISR_HTIF6)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 7 half transfer flag.
+  * @rmtoll HISR  HTIF7    LL_DMA_IsActiveFlag_HT7
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF7) == (DMA_HISR_HTIF7)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 0 transfer complete flag.
+  * @rmtoll LISR  TCIF0    LL_DMA_IsActiveFlag_TC0
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF0) == (DMA_LISR_TCIF0)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 1 transfer complete flag.
+  * @rmtoll LISR  TCIF1    LL_DMA_IsActiveFlag_TC1
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF1) == (DMA_LISR_TCIF1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 2 transfer complete flag.
+  * @rmtoll LISR  TCIF2    LL_DMA_IsActiveFlag_TC2
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF2) == (DMA_LISR_TCIF2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 3 transfer complete flag.
+  * @rmtoll LISR  TCIF3    LL_DMA_IsActiveFlag_TC3
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF3) == (DMA_LISR_TCIF3)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 4 transfer complete flag.
+  * @rmtoll HISR  TCIF4    LL_DMA_IsActiveFlag_TC4
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF4) == (DMA_HISR_TCIF4)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 5 transfer complete flag.
+  * @rmtoll HISR  TCIF0    LL_DMA_IsActiveFlag_TC5
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF5) == (DMA_HISR_TCIF5)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 6 transfer complete flag.
+  * @rmtoll HISR  TCIF6    LL_DMA_IsActiveFlag_TC6
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF6) == (DMA_HISR_TCIF6)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 7 transfer complete flag.
+  * @rmtoll HISR  TCIF7    LL_DMA_IsActiveFlag_TC7
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF7) == (DMA_HISR_TCIF7)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 0 transfer error flag.
+  * @rmtoll LISR  TEIF0    LL_DMA_IsActiveFlag_TE0
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF0) == (DMA_LISR_TEIF0)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 1 transfer error flag.
+  * @rmtoll LISR  TEIF1    LL_DMA_IsActiveFlag_TE1
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF1) == (DMA_LISR_TEIF1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 2 transfer error flag.
+  * @rmtoll LISR  TEIF2    LL_DMA_IsActiveFlag_TE2
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF2) == (DMA_LISR_TEIF2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 3 transfer error flag.
+  * @rmtoll LISR  TEIF3    LL_DMA_IsActiveFlag_TE3
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF3) == (DMA_LISR_TEIF3)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 4 transfer error flag.
+  * @rmtoll HISR  TEIF4    LL_DMA_IsActiveFlag_TE4
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF4) == (DMA_HISR_TEIF4)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 5 transfer error flag.
+  * @rmtoll HISR  TEIF0    LL_DMA_IsActiveFlag_TE5
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF5) == (DMA_HISR_TEIF5)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 6 transfer error flag.
+  * @rmtoll HISR  TEIF6    LL_DMA_IsActiveFlag_TE6
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF6) == (DMA_HISR_TEIF6)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 7 transfer error flag.
+  * @rmtoll HISR  TEIF7    LL_DMA_IsActiveFlag_TE7
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF7) == (DMA_HISR_TEIF7)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 0 direct mode error flag.
+  * @rmtoll LISR  DMEIF0    LL_DMA_IsActiveFlag_DME0
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF0) == (DMA_LISR_DMEIF0)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 1 direct mode error flag.
+  * @rmtoll LISR  DMEIF1    LL_DMA_IsActiveFlag_DME1
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF1) == (DMA_LISR_DMEIF1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 2 direct mode error flag.
+  * @rmtoll LISR  DMEIF2    LL_DMA_IsActiveFlag_DME2
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF2) == (DMA_LISR_DMEIF2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 3 direct mode error flag.
+  * @rmtoll LISR  DMEIF3    LL_DMA_IsActiveFlag_DME3
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF3) == (DMA_LISR_DMEIF3)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 4 direct mode error flag.
+  * @rmtoll HISR  DMEIF4    LL_DMA_IsActiveFlag_DME4
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF4) == (DMA_HISR_DMEIF4)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 5 direct mode error flag.
+  * @rmtoll HISR  DMEIF0    LL_DMA_IsActiveFlag_DME5
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF5) == (DMA_HISR_DMEIF5)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 6 direct mode error flag.
+  * @rmtoll HISR  DMEIF6    LL_DMA_IsActiveFlag_DME6
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF6) == (DMA_HISR_DMEIF6)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 7 direct mode error flag.
+  * @rmtoll HISR  DMEIF7    LL_DMA_IsActiveFlag_DME7
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF7) == (DMA_HISR_DMEIF7)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 0 FIFO error flag.
+  * @rmtoll LISR  FEIF0    LL_DMA_IsActiveFlag_FE0
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF0) == (DMA_LISR_FEIF0)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 1 FIFO error flag.
+  * @rmtoll LISR  FEIF1    LL_DMA_IsActiveFlag_FE1
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF1) == (DMA_LISR_FEIF1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 2 FIFO error flag.
+  * @rmtoll LISR  FEIF2    LL_DMA_IsActiveFlag_FE2
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF2) == (DMA_LISR_FEIF2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 3 FIFO error flag.
+  * @rmtoll LISR  FEIF3    LL_DMA_IsActiveFlag_FE3
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF3) == (DMA_LISR_FEIF3)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 4 FIFO error flag.
+  * @rmtoll HISR  FEIF4    LL_DMA_IsActiveFlag_FE4
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF4) == (DMA_HISR_FEIF4)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 5 FIFO error flag.
+  * @rmtoll HISR  FEIF0    LL_DMA_IsActiveFlag_FE5
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF5) == (DMA_HISR_FEIF5)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 6 FIFO error flag.
+  * @rmtoll HISR  FEIF6    LL_DMA_IsActiveFlag_FE6
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF6) == (DMA_HISR_FEIF6)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Get Stream 7 FIFO error flag.
+  * @rmtoll HISR  FEIF7    LL_DMA_IsActiveFlag_FE7
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx)
+{
+  return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF7) == (DMA_HISR_FEIF7)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Clear Stream 0 half transfer flag.
+  * @rmtoll LIFCR  CHTIF0    LL_DMA_ClearFlag_HT0
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF0);
+}
+
+/**
+  * @brief Clear Stream 1 half transfer flag.
+  * @rmtoll LIFCR  CHTIF1    LL_DMA_ClearFlag_HT1
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF1);
+}
+
+/**
+  * @brief Clear Stream 2 half transfer flag.
+  * @rmtoll LIFCR  CHTIF2    LL_DMA_ClearFlag_HT2
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF2);
+}
+
+/**
+  * @brief Clear Stream 3 half transfer flag.
+  * @rmtoll LIFCR  CHTIF3    LL_DMA_ClearFlag_HT3
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF3);
+}
+
+/**
+  * @brief Clear Stream 4 half transfer flag.
+  * @rmtoll HIFCR  CHTIF4    LL_DMA_ClearFlag_HT4
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF4);
+}
+
+/**
+  * @brief Clear Stream 5 half transfer flag.
+  * @rmtoll HIFCR  CHTIF5    LL_DMA_ClearFlag_HT5
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF5);
+}
+
+/**
+  * @brief Clear Stream 6 half transfer flag.
+  * @rmtoll HIFCR  CHTIF6    LL_DMA_ClearFlag_HT6
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF6);
+}
+
+/**
+  * @brief Clear Stream 7 half transfer flag.
+  * @rmtoll HIFCR  CHTIF7    LL_DMA_ClearFlag_HT7
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF7);
+}
+
+/**
+  * @brief Clear Stream 0 transfer complete flag.
+  * @rmtoll LIFCR  CTCIF0    LL_DMA_ClearFlag_TC0
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF0);
+}
+
+/**
+  * @brief Clear Stream 1 transfer complete flag.
+  * @rmtoll LIFCR  CTCIF1    LL_DMA_ClearFlag_TC1
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF1);
+}
+
+/**
+  * @brief Clear Stream 2 transfer complete flag.
+  * @rmtoll LIFCR  CTCIF2    LL_DMA_ClearFlag_TC2
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF2);
+}
+
+/**
+  * @brief Clear Stream 3 transfer complete flag.
+  * @rmtoll LIFCR  CTCIF3    LL_DMA_ClearFlag_TC3
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF3);
+}
+
+/**
+  * @brief Clear Stream 4 transfer complete flag.
+  * @rmtoll HIFCR  CTCIF4    LL_DMA_ClearFlag_TC4
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF4);
+}
+
+/**
+  * @brief Clear Stream 5 transfer complete flag.
+  * @rmtoll HIFCR  CTCIF5    LL_DMA_ClearFlag_TC5
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF5);
+}
+
+/**
+  * @brief Clear Stream 6 transfer complete flag.
+  * @rmtoll HIFCR  CTCIF6    LL_DMA_ClearFlag_TC6
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF6);
+}
+
+/**
+  * @brief Clear Stream 7 transfer complete flag.
+  * @rmtoll HIFCR  CTCIF7    LL_DMA_ClearFlag_TC7
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF7);
+}
+
+/**
+  * @brief Clear Stream 0 transfer error flag.
+  * @rmtoll LIFCR  CTEIF0    LL_DMA_ClearFlag_TE0
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF0);
+}
+
+/**
+  * @brief Clear Stream 1 transfer error flag.
+  * @rmtoll LIFCR  CTEIF1    LL_DMA_ClearFlag_TE1
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF1);
+}
+
+/**
+  * @brief Clear Stream 2 transfer error flag.
+  * @rmtoll LIFCR  CTEIF2    LL_DMA_ClearFlag_TE2
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF2);
+}
+
+/**
+  * @brief Clear Stream 3 transfer error flag.
+  * @rmtoll LIFCR  CTEIF3    LL_DMA_ClearFlag_TE3
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF3);
+}
+
+/**
+  * @brief Clear Stream 4 transfer error flag.
+  * @rmtoll HIFCR  CTEIF4    LL_DMA_ClearFlag_TE4
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF4);
+}
+
+/**
+  * @brief Clear Stream 5 transfer error flag.
+  * @rmtoll HIFCR  CTEIF5    LL_DMA_ClearFlag_TE5
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF5);
+}
+
+/**
+  * @brief Clear Stream 6 transfer error flag.
+  * @rmtoll HIFCR  CTEIF6    LL_DMA_ClearFlag_TE6
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF6);
+}
+
+/**
+  * @brief Clear Stream 7 transfer error flag.
+  * @rmtoll HIFCR  CTEIF7    LL_DMA_ClearFlag_TE7
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF7);
+}
+
+/**
+  * @brief Clear Stream 0 direct mode error flag.
+  * @rmtoll LIFCR  CDMEIF0    LL_DMA_ClearFlag_DME0
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF0);
+}
+
+/**
+  * @brief Clear Stream 1 direct mode error flag.
+  * @rmtoll LIFCR  CDMEIF1    LL_DMA_ClearFlag_DME1
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF1);
+}
+
+/**
+  * @brief Clear Stream 2 direct mode error flag.
+  * @rmtoll LIFCR  CDMEIF2    LL_DMA_ClearFlag_DME2
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF2);
+}
+
+/**
+  * @brief Clear Stream 3 direct mode error flag.
+  * @rmtoll LIFCR  CDMEIF3    LL_DMA_ClearFlag_DME3
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF3);
+}
+
+/**
+  * @brief Clear Stream 4 direct mode error flag.
+  * @rmtoll HIFCR  CDMEIF4    LL_DMA_ClearFlag_DME4
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF4);
+}
+
+/**
+  * @brief Clear Stream 5 direct mode error flag.
+  * @rmtoll HIFCR  CDMEIF5    LL_DMA_ClearFlag_DME5
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF5);
+}
+
+/**
+  * @brief Clear Stream 6 direct mode error flag.
+  * @rmtoll HIFCR  CDMEIF6    LL_DMA_ClearFlag_DME6
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF6);
+}
+
+/**
+  * @brief Clear Stream 7 direct mode error flag.
+  * @rmtoll HIFCR  CDMEIF7    LL_DMA_ClearFlag_DME7
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF7);
+}
+
+/**
+  * @brief Clear Stream 0 FIFO error flag.
+  * @rmtoll LIFCR  CFEIF0    LL_DMA_ClearFlag_FE0
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF0);
+}
+
+/**
+  * @brief Clear Stream 1 FIFO error flag.
+  * @rmtoll LIFCR  CFEIF1    LL_DMA_ClearFlag_FE1
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF1);
+}
+
+/**
+  * @brief Clear Stream 2 FIFO error flag.
+  * @rmtoll LIFCR  CFEIF2    LL_DMA_ClearFlag_FE2
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF2);
+}
+
+/**
+  * @brief Clear Stream 3 FIFO error flag.
+  * @rmtoll LIFCR  CFEIF3    LL_DMA_ClearFlag_FE3
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF3);
+}
+
+/**
+  * @brief Clear Stream 4 FIFO error flag.
+  * @rmtoll HIFCR  CFEIF4    LL_DMA_ClearFlag_FE4
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF4);
+}
+
+/**
+  * @brief Clear Stream 5 FIFO error flag.
+  * @rmtoll HIFCR  CFEIF5    LL_DMA_ClearFlag_FE5
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF5);
+}
+
+/**
+  * @brief Clear Stream 6 FIFO error flag.
+  * @rmtoll HIFCR  CFEIF6    LL_DMA_ClearFlag_FE6
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF6);
+}
+
+/**
+  * @brief Clear Stream 7 FIFO error flag.
+  * @rmtoll HIFCR  CFEIF7    LL_DMA_ClearFlag_FE7
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF7);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief Enable Half transfer interrupt.
+  * @rmtoll CR        HTIE         LL_DMA_EnableIT_HT
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE);
+}
+
+/**
+  * @brief Enable Transfer error interrupt.
+  * @rmtoll CR        TEIE         LL_DMA_EnableIT_TE
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE);
+}
+
+/**
+  * @brief Enable Transfer complete interrupt.
+  * @rmtoll CR        TCIE         LL_DMA_EnableIT_TC
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE);
+}
+
+/**
+  * @brief Enable Direct mode error interrupt.
+  * @rmtoll CR        DMEIE         LL_DMA_EnableIT_DME
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE);
+}
+
+/**
+  * @brief Enable FIFO error interrupt.
+  * @rmtoll FCR        FEIE         LL_DMA_EnableIT_FE
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE);
+}
+
+/**
+  * @brief Disable Half transfer interrupt.
+  * @rmtoll CR        HTIE         LL_DMA_DisableIT_HT
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE);
+}
+
+/**
+  * @brief Disable Transfer error interrupt.
+  * @rmtoll CR        TEIE         LL_DMA_DisableIT_TE
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE);
+}
+
+/**
+  * @brief Disable Transfer complete interrupt.
+  * @rmtoll CR        TCIE         LL_DMA_DisableIT_TC
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE);
+}
+
+/**
+  * @brief Disable Direct mode error interrupt.
+  * @rmtoll CR        DMEIE         LL_DMA_DisableIT_DME
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE);
+}
+
+/**
+  * @brief Disable FIFO error interrupt.
+  * @rmtoll FCR        FEIE         LL_DMA_DisableIT_FE
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE);
+}
+
+/**
+  * @brief Check if Half transfer interrup is enabled.
+  * @rmtoll CR        HTIE         LL_DMA_IsEnabledIT_HT
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Check if Transfer error nterrup is enabled.
+  * @rmtoll CR        TEIE         LL_DMA_IsEnabledIT_TE
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Check if Transfer complete interrup is enabled.
+  * @rmtoll CR        TCIE         LL_DMA_IsEnabledIT_TC
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Check if Direct mode error interrupt is enabled.
+  * @rmtoll CR        DMEIE         LL_DMA_IsEnabledIT_DME
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief Check if FIFO error interrup is enabled.
+  * @rmtoll FCR        FEIE         LL_DMA_IsEnabledIT_FE
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct);
+uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream);
+void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* DMA1 || DMA2 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32H7xx_LL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dmamux.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dmamux.h
new file mode 100644
index 00000000..13f81186
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dmamux.h
@@ -0,0 +1,2363 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_dmamux.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMAMUX LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_LL_DMAMUX_H
+#define STM32H7xx_LL_DMAMUX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined (DMAMUX1) || defined (DMAMUX2)
+
+/** @defgroup DMAMUX_LL DMAMUX
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup DMAMUX_LL_Private_Constants DMAMUX Private Constants
+  * @{
+  */
+/* Define used to get DMAMUX CCR register size */
+#define DMAMUX_CCR_SIZE                   0x00000004U
+
+/* Define used to get DMAMUX RGCR register size */
+#define DMAMUX_RGCR_SIZE                  0x00000004U
+
+/* Define used to get DMAMUX RequestGenerator offset */
+#define DMAMUX_REQ_GEN_OFFSET             (DMAMUX1_RequestGenerator0_BASE - DMAMUX1_BASE)
+/* Define used to get DMAMUX Channel Status offset */
+#define DMAMUX_CH_STATUS_OFFSET           (DMAMUX1_ChannelStatus_BASE - DMAMUX1_BASE)
+/* Define used to get DMAMUX RequestGenerator status offset */
+#define DMAMUX_REQ_GEN_STATUS_OFFSET      (DMAMUX1_RequestGenStatus_BASE - DMAMUX1_BASE)
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DMAMUX_LL_Exported_Constants DMAMUX Exported Constants
+  * @{
+  */
+/** @defgroup DMAMUX_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_DMAMUX_WriteReg function
+  * @{
+  */
+#define LL_DMAMUX_CFR_CSOF0               DMAMUX_CFR_CSOF0       /*!< Synchronization Event Overrun Flag Channel 0   */
+#define LL_DMAMUX_CFR_CSOF1               DMAMUX_CFR_CSOF1       /*!< Synchronization Event Overrun Flag Channel 1   */
+#define LL_DMAMUX_CFR_CSOF2               DMAMUX_CFR_CSOF2       /*!< Synchronization Event Overrun Flag Channel 2   */
+#define LL_DMAMUX_CFR_CSOF3               DMAMUX_CFR_CSOF3       /*!< Synchronization Event Overrun Flag Channel 3   */
+#define LL_DMAMUX_CFR_CSOF4               DMAMUX_CFR_CSOF4       /*!< Synchronization Event Overrun Flag Channel 4   */
+#define LL_DMAMUX_CFR_CSOF5               DMAMUX_CFR_CSOF5       /*!< Synchronization Event Overrun Flag Channel 5   */
+#define LL_DMAMUX_CFR_CSOF6               DMAMUX_CFR_CSOF6       /*!< Synchronization Event Overrun Flag Channel 6   */
+#define LL_DMAMUX_CFR_CSOF7               DMAMUX_CFR_CSOF7       /*!< Synchronization Event Overrun Flag Channel 7   */
+#define LL_DMAMUX_CFR_CSOF8               DMAMUX_CFR_CSOF8       /*!< Synchronization Event Overrun Flag Channel 8   */
+#define LL_DMAMUX_CFR_CSOF9               DMAMUX_CFR_CSOF9       /*!< Synchronization Event Overrun Flag Channel 9   */
+#define LL_DMAMUX_CFR_CSOF10              DMAMUX_CFR_CSOF10      /*!< Synchronization Event Overrun Flag Channel 10  */
+#define LL_DMAMUX_CFR_CSOF11              DMAMUX_CFR_CSOF11      /*!< Synchronization Event Overrun Flag Channel 11  */
+#define LL_DMAMUX_CFR_CSOF12              DMAMUX_CFR_CSOF12      /*!< Synchronization Event Overrun Flag Channel 12  */
+#define LL_DMAMUX_CFR_CSOF13              DMAMUX_CFR_CSOF13      /*!< Synchronization Event Overrun Flag Channel 13  */
+#define LL_DMAMUX_CFR_CSOF14              DMAMUX_CFR_CSOF14      /*!< Synchronization Event Overrun Flag Channel 14  */
+#define LL_DMAMUX_CFR_CSOF15              DMAMUX_CFR_CSOF15      /*!< Synchronization Event Overrun Flag Channel 15  */
+#define LL_DMAMUX_RGCFR_RGCOF0            DMAMUX_RGCFR_COF0      /*!< Request Generator 0 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGCFR_RGCOF1            DMAMUX_RGCFR_COF1      /*!< Request Generator 1 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGCFR_RGCOF2            DMAMUX_RGCFR_COF2      /*!< Request Generator 2 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGCFR_RGCOF3            DMAMUX_RGCFR_COF3      /*!< Request Generator 3 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGCFR_RGCOF4            DMAMUX_RGCFR_COF4      /*!< Request Generator 4 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGCFR_RGCOF5            DMAMUX_RGCFR_COF5      /*!< Request Generator 5 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGCFR_RGCOF6            DMAMUX_RGCFR_COF6      /*!< Request Generator 6 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGCFR_RGCOF7            DMAMUX_RGCFR_COF7      /*!< Request Generator 7 Trigger Event Overrun Flag */
+/**
+  * @}
+  */
+
+/** @defgroup DMAMUX_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_DMAMUX_ReadReg function
+  * @{
+  */
+#define LL_DMAMUX_CSR_SOF0                DMAMUX_CSR_SOF0       /*!< Synchronization Event Overrun Flag Channel 0   */
+#define LL_DMAMUX_CSR_SOF1                DMAMUX_CSR_SOF1       /*!< Synchronization Event Overrun Flag Channel 1   */
+#define LL_DMAMUX_CSR_SOF2                DMAMUX_CSR_SOF2       /*!< Synchronization Event Overrun Flag Channel 2   */
+#define LL_DMAMUX_CSR_SOF3                DMAMUX_CSR_SOF3       /*!< Synchronization Event Overrun Flag Channel 3   */
+#define LL_DMAMUX_CSR_SOF4                DMAMUX_CSR_SOF4       /*!< Synchronization Event Overrun Flag Channel 4   */
+#define LL_DMAMUX_CSR_SOF5                DMAMUX_CSR_SOF5       /*!< Synchronization Event Overrun Flag Channel 5   */
+#define LL_DMAMUX_CSR_SOF6                DMAMUX_CSR_SOF6       /*!< Synchronization Event Overrun Flag Channel 6   */
+#define LL_DMAMUX_CSR_SOF7                DMAMUX_CSR_SOF7       /*!< Synchronization Event Overrun Flag Channel 7   */
+#define LL_DMAMUX_CSR_SOF8                DMAMUX_CSR_SOF8       /*!< Synchronization Event Overrun Flag Channel 8   */
+#define LL_DMAMUX_CSR_SOF9                DMAMUX_CSR_SOF9       /*!< Synchronization Event Overrun Flag Channel 9   */
+#define LL_DMAMUX_CSR_SOF10               DMAMUX_CSR_SOF10      /*!< Synchronization Event Overrun Flag Channel 10  */
+#define LL_DMAMUX_CSR_SOF11               DMAMUX_CSR_SOF11      /*!< Synchronization Event Overrun Flag Channel 11  */
+#define LL_DMAMUX_CSR_SOF12               DMAMUX_CSR_SOF12      /*!< Synchronization Event Overrun Flag Channel 12  */
+#define LL_DMAMUX_CSR_SOF13               DMAMUX_CSR_SOF13      /*!< Synchronization Event Overrun Flag Channel 13  */
+#define LL_DMAMUX_CSR_SOF14               DMAMUX_CSR_SOF14      /*!< Synchronization Event Overrun Flag Channel 14  */
+#define LL_DMAMUX_CSR_SOF15               DMAMUX_CSR_SOF15      /*!< Synchronization Event Overrun Flag Channel 15  */
+#define LL_DMAMUX_RGSR_RGOF0              DMAMUX_RGSR_OF0       /*!< Request Generator 0 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGSR_RGOF1              DMAMUX_RGSR_OF1       /*!< Request Generator 1 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGSR_RGOF2              DMAMUX_RGSR_OF2       /*!< Request Generator 2 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGSR_RGOF3              DMAMUX_RGSR_OF3       /*!< Request Generator 3 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGSR_RGOF4              DMAMUX_RGSR_OF4       /*!< Request Generator 4 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGSR_RGOF5              DMAMUX_RGSR_OF5       /*!< Request Generator 5 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGSR_RGOF6              DMAMUX_RGSR_OF6       /*!< Request Generator 6 Trigger Event Overrun Flag */
+#define LL_DMAMUX_RGSR_RGOF7              DMAMUX_RGSR_OF7       /*!< Request Generator 7 Trigger Event Overrun Flag */
+/**
+  * @}
+  */
+
+/** @defgroup DMAMUX_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_DMA_ReadReg and  LL_DMAMUX_WriteReg functions
+  * @{
+  */
+#define LL_DMAMUX_CCR_SOIE                DMAMUX_CxCR_SOIE          /*!< Synchronization Event Overrun Interrupt               */
+#define LL_DMAMUX_RGCR_RGOIE              DMAMUX_RGxCR_OIE          /*!< Request Generation Trigger Event Overrun Interrupt    */
+/**
+  * @}
+  */
+
+/** @defgroup DMAMUX_Request_selection DMAMUX Request selection
+  * @brief    DMA Request selection
+  * @{
+  */
+/* DMAMUX1 requests */
+#define LL_DMAMUX1_REQ_MEM2MEM          0U   /*!< memory to memory transfer       */
+#define LL_DMAMUX1_REQ_GENERATOR0       1U   /*!< DMAMUX1 request generator 0     */
+#define LL_DMAMUX1_REQ_GENERATOR1       2U   /*!< DMAMUX1 request generator 1     */
+#define LL_DMAMUX1_REQ_GENERATOR2       3U   /*!< DMAMUX1 request generator 2     */
+#define LL_DMAMUX1_REQ_GENERATOR3       4U   /*!< DMAMUX1 request generator 3     */
+#define LL_DMAMUX1_REQ_GENERATOR4       5U   /*!< DMAMUX1 request generator 4     */
+#define LL_DMAMUX1_REQ_GENERATOR5       6U   /*!< DMAMUX1 request generator 5     */
+#define LL_DMAMUX1_REQ_GENERATOR6       7U   /*!< DMAMUX1 request generator 6     */
+#define LL_DMAMUX1_REQ_GENERATOR7       8U   /*!< DMAMUX1 request generator 7     */
+#define LL_DMAMUX1_REQ_ADC1             9U   /*!< DMAMUX1 ADC1 request            */
+#define LL_DMAMUX1_REQ_ADC2             10U  /*!< DMAMUX1 ADC2 request            */
+#define LL_DMAMUX1_REQ_TIM1_CH1         11U  /*!< DMAMUX1 TIM1 CH1 request        */
+#define LL_DMAMUX1_REQ_TIM1_CH2         12U  /*!< DMAMUX1 TIM1 CH2 request        */
+#define LL_DMAMUX1_REQ_TIM1_CH3         13U  /*!< DMAMUX1 TIM1 CH3 request        */
+#define LL_DMAMUX1_REQ_TIM1_CH4         14U  /*!< DMAMUX1 TIM1 CH4 request        */
+#define LL_DMAMUX1_REQ_TIM1_UP          15U  /*!< DMAMUX1 TIM1 UP request         */
+#define LL_DMAMUX1_REQ_TIM1_TRIG        16U  /*!< DMAMUX1 TIM1 TRIG request       */
+#define LL_DMAMUX1_REQ_TIM1_COM         17U  /*!< DMAMUX1 TIM1 COM request        */
+#define LL_DMAMUX1_REQ_TIM2_CH1         18U  /*!< DMAMUX1 TIM2 CH1 request        */
+#define LL_DMAMUX1_REQ_TIM2_CH2         19U  /*!< DMAMUX1 TIM2 CH2 request        */
+#define LL_DMAMUX1_REQ_TIM2_CH3         20U  /*!< DMAMUX1 TIM2 CH3 request        */
+#define LL_DMAMUX1_REQ_TIM2_CH4         21U  /*!< DMAMUX1 TIM2 CH4 request        */
+#define LL_DMAMUX1_REQ_TIM2_UP          22U  /*!< DMAMUX1 TIM2 UP request         */
+#define LL_DMAMUX1_REQ_TIM3_CH1         23U  /*!< DMAMUX1 TIM3 CH1 request        */
+#define LL_DMAMUX1_REQ_TIM3_CH2         24U  /*!< DMAMUX1 TIM3 CH2 request        */
+#define LL_DMAMUX1_REQ_TIM3_CH3         25U  /*!< DMAMUX1 TIM3 CH3 request        */
+#define LL_DMAMUX1_REQ_TIM3_CH4         26U  /*!< DMAMUX1 TIM3 CH4 request        */
+#define LL_DMAMUX1_REQ_TIM3_UP          27U  /*!< DMAMUX1 TIM3 UP request         */
+#define LL_DMAMUX1_REQ_TIM3_TRIG        28U  /*!< DMAMUX1 TIM3 TRIG request       */
+#define LL_DMAMUX1_REQ_TIM4_CH1         29U  /*!< DMAMUX1 TIM4 CH1 request        */
+#define LL_DMAMUX1_REQ_TIM4_CH2         30U  /*!< DMAMUX1 TIM4 CH2 request        */
+#define LL_DMAMUX1_REQ_TIM4_CH3         31U  /*!< DMAMUX1 TIM4 CH3 request        */
+#define LL_DMAMUX1_REQ_TIM4_UP          32U  /*!< DMAMUX1 TIM4 UP request         */
+#define LL_DMAMUX1_REQ_I2C1_RX          33U  /*!< DMAMUX1 I2C1 RX request         */
+#define LL_DMAMUX1_REQ_I2C1_TX          34U  /*!< DMAMUX1 I2C1 TX request         */
+#define LL_DMAMUX1_REQ_I2C2_RX          35U  /*!< DMAMUX1 I2C2 RX request         */
+#define LL_DMAMUX1_REQ_I2C2_TX          36U  /*!< DMAMUX1 I2C2 TX request         */
+#define LL_DMAMUX1_REQ_SPI1_RX          37U  /*!< DMAMUX1 SPI1 RX request         */
+#define LL_DMAMUX1_REQ_SPI1_TX          38U  /*!< DMAMUX1 SPI1 TX request         */
+#define LL_DMAMUX1_REQ_SPI2_RX          39U  /*!< DMAMUX1 SPI2 RX request         */
+#define LL_DMAMUX1_REQ_SPI2_TX          40U  /*!< DMAMUX1 SPI2 TX request         */
+#define LL_DMAMUX1_REQ_USART1_RX        41U  /*!< DMAMUX1 USART1 RX request       */
+#define LL_DMAMUX1_REQ_USART1_TX        42U  /*!< DMAMUX1 USART1 TX request       */
+#define LL_DMAMUX1_REQ_USART2_RX        43U  /*!< DMAMUX1 USART2 RX request       */
+#define LL_DMAMUX1_REQ_USART2_TX        44U  /*!< DMAMUX1 USART2 TX request       */
+#define LL_DMAMUX1_REQ_USART3_RX        45U  /*!< DMAMUX1 USART3 RX request       */
+#define LL_DMAMUX1_REQ_USART3_TX        46U  /*!< DMAMUX1 USART3 TX request       */
+#define LL_DMAMUX1_REQ_TIM8_CH1         47U  /*!< DMAMUX1 TIM8 CH1 request        */
+#define LL_DMAMUX1_REQ_TIM8_CH2         48U  /*!< DMAMUX1 TIM8 CH2 request        */
+#define LL_DMAMUX1_REQ_TIM8_CH3         49U  /*!< DMAMUX1 TIM8 CH3 request        */
+#define LL_DMAMUX1_REQ_TIM8_CH4         50U  /*!< DMAMUX1 TIM8 CH4 request        */
+#define LL_DMAMUX1_REQ_TIM8_UP          51U  /*!< DMAMUX1 TIM8 UP request         */
+#define LL_DMAMUX1_REQ_TIM8_TRIG        52U  /*!< DMAMUX1 TIM8 TRIG request       */
+#define LL_DMAMUX1_REQ_TIM8_COM         53U  /*!< DMAMUX1 TIM8 COM request        */
+#define LL_DMAMUX1_REQ_TIM5_CH1         55U  /*!< DMAMUX1 TIM5 CH1 request        */
+#define LL_DMAMUX1_REQ_TIM5_CH2         56U  /*!< DMAMUX1 TIM5 CH2 request        */
+#define LL_DMAMUX1_REQ_TIM5_CH3         57U  /*!< DMAMUX1 TIM5 CH3 request        */
+#define LL_DMAMUX1_REQ_TIM5_CH4         58U  /*!< DMAMUX1 TIM5 CH4 request        */
+#define LL_DMAMUX1_REQ_TIM5_UP          59U  /*!< DMAMUX1 TIM5 UP request         */
+#define LL_DMAMUX1_REQ_TIM5_TRIG        60U  /*!< DMAMUX1 TIM5 TRIG request       */
+#define LL_DMAMUX1_REQ_SPI3_RX          61U  /*!< DMAMUX1 SPI3 RX request         */
+#define LL_DMAMUX1_REQ_SPI3_TX          62U  /*!< DMAMUX1 SPI3 TX request         */
+#define LL_DMAMUX1_REQ_UART4_RX         63U  /*!< DMAMUX1 UART4 RX request        */
+#define LL_DMAMUX1_REQ_UART4_TX         64U  /*!< DMAMUX1 UART4 TX request        */
+#define LL_DMAMUX1_REQ_UART5_RX         65U  /*!< DMAMUX1 UART5 RX request        */
+#define LL_DMAMUX1_REQ_UART5_TX         66U  /*!< DMAMUX1 UART5 TX request        */
+#define LL_DMAMUX1_REQ_DAC1_CH1         67U  /*!< DMAMUX1 DAC1 Channel 1 request  */
+#define LL_DMAMUX1_REQ_DAC1_CH2         68U  /*!< DMAMUX1 DAC1 Channel 2 request  */
+#define LL_DMAMUX1_REQ_TIM6_UP          69U  /*!< DMAMUX1 TIM6 UP request         */
+#define LL_DMAMUX1_REQ_TIM7_UP          70U  /*!< DMAMUX1 TIM7 UP request         */
+#define LL_DMAMUX1_REQ_USART6_RX        71U  /*!< DMAMUX1 USART6 RX request       */
+#define LL_DMAMUX1_REQ_USART6_TX        72U  /*!< DMAMUX1 USART6 TX request       */
+#define LL_DMAMUX1_REQ_I2C3_RX          73U  /*!< DMAMUX1 I2C3 RX request         */
+#define LL_DMAMUX1_REQ_I2C3_TX          74U  /*!< DMAMUX1 I2C3 TX request         */
+#if defined (PSSI)
+#define LL_DMAMUX1_REQ_DCMI_PSSI        75U  /*!< DMAMUX1 DCMI/PSSI request       */
+#define LL_DMAMUX1_REQ_DCMI             LL_DMAMUX1_REQ_DCMI_PSSI /* Legacy define */
+#else
+#define LL_DMAMUX1_REQ_DCMI             75U  /*!< DMAMUX1 DCMI request            */
+#endif /* PSSI */
+#define LL_DMAMUX1_REQ_CRYP_IN          76U  /*!< DMAMUX1 CRYP IN request         */
+#define LL_DMAMUX1_REQ_CRYP_OUT         77U  /*!< DMAMUX1 CRYP OUT request        */
+#define LL_DMAMUX1_REQ_HASH_IN          78U  /*!< DMAMUX1 HASH IN request         */
+#define LL_DMAMUX1_REQ_UART7_RX         79U  /*!< DMAMUX1 UART7 RX request        */
+#define LL_DMAMUX1_REQ_UART7_TX         80U  /*!< DMAMUX1 UART7 TX request        */
+#define LL_DMAMUX1_REQ_UART8_RX         81U  /*!< DMAMUX1 UART8 RX request        */
+#define LL_DMAMUX1_REQ_UART8_TX         82U  /*!< DMAMUX1 UART8 TX request        */
+#define LL_DMAMUX1_REQ_SPI4_RX          83U  /*!< DMAMUX1 SPI4 RX request         */
+#define LL_DMAMUX1_REQ_SPI4_TX          84U  /*!< DMAMUX1 SPI4 TX request         */
+#define LL_DMAMUX1_REQ_SPI5_RX          85U  /*!< DMAMUX1 SPI5 RX request         */
+#define LL_DMAMUX1_REQ_SPI5_TX          86U  /*!< DMAMUX1 SPI5 TX request         */
+#define LL_DMAMUX1_REQ_SAI1_A           87U  /*!< DMAMUX1 SAI1 A request          */
+#define LL_DMAMUX1_REQ_SAI1_B           88U  /*!< DMAMUX1 SAI1 B request          */
+#define LL_DMAMUX1_REQ_SAI2_A           89U  /*!< DMAMUX1 SAI2 A request          */
+#define LL_DMAMUX1_REQ_SAI2_B           90U  /*!< DMAMUX1 SAI2 B request          */
+#define LL_DMAMUX1_REQ_SWPMI_RX         91U  /*!< DMAMUX1 SWPMI RX request        */
+#define LL_DMAMUX1_REQ_SWPMI_TX         92U  /*!< DMAMUX1 SWPMI TX request        */
+#define LL_DMAMUX1_REQ_SPDIF_RX_DT      93U  /*!< DMAMUX1 SPDIF RXDT request      */
+#define LL_DMAMUX1_REQ_SPDIF_RX_CS      94U  /*!< DMAMUX1 SPDIF RXCS request      */
+#if defined (HRTIM1)
+#define LL_DMAMUX1_REQ_HRTIM_MASTER     95U  /*!< DMAMUX1 HRTIM1 Master request 1 */
+#define LL_DMAMUX1_REQ_HRTIM_TIMER_A    96U  /*!< DMAMUX1 HRTIM1 TimerA request 2 */
+#define LL_DMAMUX1_REQ_HRTIM_TIMER_B    97U  /*!< DMAMUX1 HRTIM1 TimerB request 3 */
+#define LL_DMAMUX1_REQ_HRTIM_TIMER_C    98U  /*!< DMAMUX1 HRTIM1 TimerC request 4 */
+#define LL_DMAMUX1_REQ_HRTIM_TIMER_D    99U  /*!< DMAMUX1 HRTIM1 TimerD request 5 */
+#define LL_DMAMUX1_REQ_HRTIM_TIMER_E   100U  /*!< DMAMUX1 HRTIM1 TimerE request 6 */
+#endif /* HRTIM1 */
+#define LL_DMAMUX1_REQ_DFSDM1_FLT0     101U  /*!< DMAMUX1 DFSDM1 Filter0 request  */
+#define LL_DMAMUX1_REQ_DFSDM1_FLT1     102U  /*!< DMAMUX1 DFSDM1 Filter1 request  */
+#define LL_DMAMUX1_REQ_DFSDM1_FLT2     103U  /*!< DMAMUX1 DFSDM1 Filter2 request  */
+#define LL_DMAMUX1_REQ_DFSDM1_FLT3     104U  /*!< DMAMUX1 DFSDM1 Filter3 request  */
+#define LL_DMAMUX1_REQ_TIM15_CH1       105U  /*!< DMAMUX1 TIM15 CH1 request       */
+#define LL_DMAMUX1_REQ_TIM15_UP        106U  /*!< DMAMUX1 TIM15 UP request        */
+#define LL_DMAMUX1_REQ_TIM15_TRIG      107U  /*!< DMAMUX1 TIM15 TRIG request      */
+#define LL_DMAMUX1_REQ_TIM15_COM       108U  /*!< DMAMUX1 TIM15 COM request       */
+#define LL_DMAMUX1_REQ_TIM16_CH1       109U  /*!< DMAMUX1 TIM16 CH1 request       */
+#define LL_DMAMUX1_REQ_TIM16_UP        110U  /*!< DMAMUX1 TIM16 UP request        */
+#define LL_DMAMUX1_REQ_TIM17_CH1       111U  /*!< DMAMUX1 TIM17 CH1 request       */
+#define LL_DMAMUX1_REQ_TIM17_UP        112U  /*!< DMAMUX1 TIM17 UP request        */
+#if defined (SAI3)
+#define LL_DMAMUX1_REQ_SAI3_A          113U  /*!< DMAMUX1 SAI3 A request          */
+#define LL_DMAMUX1_REQ_SAI3_B          114U  /*!< DMAMUX1 SAI3 B request          */
+#endif /* SAI3 */
+#if defined (ADC3)
+#define LL_DMAMUX1_REQ_ADC3            115U  /*!< DMAMUX1 ADC3  request           */
+#endif /* ADC3 */
+#if defined (UART9)
+#define LL_DMAMUX1_REQ_UART9_RX        116U  /*!< DMAMUX1 UART9 RX request        */
+#define LL_DMAMUX1_REQ_UART9_TX        117U  /*!< DMAMUX1 UART9 TX request        */
+#endif /* UART9 */
+#if defined (USART10)
+#define LL_DMAMUX1_REQ_USART10_RX      118U  /*!< DMAMUX1 USART10 RX request      */
+#define LL_DMAMUX1_REQ_USART10_TX      119U  /*!< DMAMUX1 USART10 TX request      */
+#endif /* USART10 */
+
+/* DMAMUX2 requests */
+#define LL_DMAMUX2_REQ_MEM2MEM          0U  /*!< memory to memory transfer        */
+#define LL_DMAMUX2_REQ_GENERATOR0       1U  /*!< DMAMUX2 request generator 0      */
+#define LL_DMAMUX2_REQ_GENERATOR1       2U  /*!< DMAMUX2 request generator 1      */
+#define LL_DMAMUX2_REQ_GENERATOR2       3U  /*!< DMAMUX2 request generator 2      */
+#define LL_DMAMUX2_REQ_GENERATOR3       4U  /*!< DMAMUX2 request generator 3      */
+#define LL_DMAMUX2_REQ_GENERATOR4       5U  /*!< DMAMUX2 request generator 4      */
+#define LL_DMAMUX2_REQ_GENERATOR5       6U  /*!< DMAMUX2 request generator 5      */
+#define LL_DMAMUX2_REQ_GENERATOR6       7U  /*!< DMAMUX2 request generator 6      */
+#define LL_DMAMUX2_REQ_GENERATOR7       8U  /*!< DMAMUX2 request generator 7      */
+#define LL_DMAMUX2_REQ_LPUART1_RX       9U  /*!< DMAMUX2 LP_UART1_RX request      */
+#define LL_DMAMUX2_REQ_LPUART1_TX      10U  /*!< DMAMUX2 LP_UART1_TX request      */
+#define LL_DMAMUX2_REQ_SPI6_RX         11U  /*!< DMAMUX2 SPI6 RX request          */
+#define LL_DMAMUX2_REQ_SPI6_TX         12U  /*!< DMAMUX2 SPI6 TX request          */
+#define LL_DMAMUX2_REQ_I2C4_RX         13U  /*!< DMAMUX2 I2C4 RX request          */
+#define LL_DMAMUX2_REQ_I2C4_TX         14U  /*!< DMAMUX2 I2C4 TX request          */
+#if defined (SAI4)
+#define LL_DMAMUX2_REQ_SAI4_A          15U  /*!< DMAMUX2 SAI4 A request           */
+#define LL_DMAMUX2_REQ_SAI4_B          16U  /*!< DMAMUX2 SAI4 B request           */
+#endif /* SAI4 */
+#if defined (ADC3)
+#define LL_DMAMUX2_REQ_ADC3            17U  /*!< DMAMUX2 ADC3 request             */
+#endif /* ADC3 */
+#if defined (DAC2)
+#define LL_DMAMUX2_REQ_DAC2_CH1        17U  /*!< DMAMUX2 DAC2 CH1 request         */
+#endif /* DAC2 */
+#if defined (DFSDM2_Channel0)
+#define LL_DMAMUX2_REQ_DFSDM2_FLT0     18U  /*!< DMAMUX2 DFSDM2 Filter0 request   */
+#endif /* DFSDM2_Channel0 */
+/**
+  * @}
+  */
+
+
+/** @defgroup DMAMUX_LL_EC_CHANNEL DMAMUX Channel
+  * @{
+  */
+#define LL_DMAMUX_CHANNEL_0     0x00000000U  /*!< DMAMUX1 Channel 0  connected to DMA1 Channel 0 , DMAMUX2 Channel 0 connected to BDMA Channel 0 */
+#define LL_DMAMUX_CHANNEL_1     0x00000001U  /*!< DMAMUX1 Channel 1  connected to DMA1 Channel 1 , DMAMUX2 Channel 1 connected to BDMA Channel 1 */
+#define LL_DMAMUX_CHANNEL_2     0x00000002U  /*!< DMAMUX1 Channel 2  connected to DMA1 Channel 2 , DMAMUX2 Channel 2 connected to BDMA Channel 2 */
+#define LL_DMAMUX_CHANNEL_3     0x00000003U  /*!< DMAMUX1 Channel 3  connected to DMA1 Channel 3 , DMAMUX2 Channel 3 connected to BDMA Channel 3 */
+#define LL_DMAMUX_CHANNEL_4     0x00000004U  /*!< DMAMUX1 Channel 4  connected to DMA1 Channel 4 , DMAMUX2 Channel 4 connected to BDMA Channel 4 */
+#define LL_DMAMUX_CHANNEL_5     0x00000005U  /*!< DMAMUX1 Channel 5  connected to DMA1 Channel 5 , DMAMUX2 Channel 5 connected to BDMA Channel 5 */
+#define LL_DMAMUX_CHANNEL_6     0x00000006U  /*!< DMAMUX1 Channel 6  connected to DMA1 Channel 6 , DMAMUX2 Channel 6 connected to BDMA Channel 6 */
+#define LL_DMAMUX_CHANNEL_7     0x00000007U  /*!< DMAMUX1 Channel 7  connected to DMA1 Channel 7 , DMAMUX2 Channel 7 connected to BDMA Channel 7 */
+#define LL_DMAMUX_CHANNEL_8     0x00000008U  /*!< DMAMUX1 Channel 8  connected to DMA2 Channel 0 */
+#define LL_DMAMUX_CHANNEL_9     0x00000009U  /*!< DMAMUX1 Channel 9  connected to DMA2 Channel 1 */
+#define LL_DMAMUX_CHANNEL_10    0x0000000AU  /*!< DMAMUX1 Channel 10 connected to DMA2 Channel 2 */
+#define LL_DMAMUX_CHANNEL_11    0x0000000BU  /*!< DMAMUX1 Channel 11 connected to DMA2 Channel 3 */
+#define LL_DMAMUX_CHANNEL_12    0x0000000CU  /*!< DMAMUX1 Channel 12 connected to DMA2 Channel 4 */
+#define LL_DMAMUX_CHANNEL_13    0x0000000DU  /*!< DMAMUX1 Channel 13 connected to DMA2 Channel 5 */
+#define LL_DMAMUX_CHANNEL_14    0x0000000EU  /*!< DMAMUX1 Channel 14 connected to DMA2 Channel 6 */
+#define LL_DMAMUX_CHANNEL_15    0x0000000FU  /*!< DMAMUX1 Channel 15 connected to DMA2 Channel 7 */
+/**
+  * @}
+  */
+
+/** @defgroup DMAMUX_LL_EC_SYNC_NO Synchronization Signal Polarity
+  * @{
+  */
+#define LL_DMAMUX_SYNC_NO_EVENT            0x00000000U                               /*!< All requests are blocked                            */
+#define LL_DMAMUX_SYNC_POL_RISING          DMAMUX_CxCR_SPOL_0                        /*!< Synchronization on event on rising edge             */
+#define LL_DMAMUX_SYNC_POL_FALLING         DMAMUX_CxCR_SPOL_1                        /*!< Synchronization on event on falling edge            */
+#define LL_DMAMUX_SYNC_POL_RISING_FALLING  (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1) /*!< Synchronization on event on rising and falling edge */
+/**
+  * @}
+  */
+
+/** @defgroup DMAMUX_LL_EC_SYNC_EVT Synchronization Signal Event
+  * @{
+  */
+#define LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT   0x00000000U   /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel0 Event */
+#define LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT   0x01000000U   /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel1 Event */
+#define LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT   0x02000000U   /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel2 Event */
+#define LL_DMAMUX1_SYNC_LPTIM1_OUT        0x03000000U   /*!< DMAMUX1 synchronization Signal is LPTIM1 OUT             */
+#define LL_DMAMUX1_SYNC_LPTIM2_OUT        0x04000000U   /*!< DMAMUX1 synchronization Signal is LPTIM2 OUT             */
+#define LL_DMAMUX1_SYNC_LPTIM3_OUT        0x05000000U   /*!< DMAMUX1 synchronization Signal is LPTIM3 OUT             */
+#define LL_DMAMUX1_SYNC_EXTI0             0x06000000U   /*!< DMAMUX1 synchronization Signal is EXTI0 IT               */
+#define LL_DMAMUX1_SYNC_TIM12_TRGO        0x07000000U   /*!< DMAMUX1 synchronization Signal is TIM12 TRGO             */
+
+#define LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT   0x00000000U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel0 Event */
+#define LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT   0x01000000U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel1 Event */
+#define LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT   0x02000000U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel2 Event */
+#define LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT   0x03000000U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel3 Event */
+#define LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT   0x04000000U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel4 Event */
+#define LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT   0x05000000U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel5 Event */
+#define LL_DMAMUX2_SYNC_LPUART1_RX_WKUP   0x06000000U   /*!< DMAMUX2 synchronization Signal is LPUART1 RX Wakeup      */
+#define LL_DMAMUX2_SYNC_LPUART1_TX_WKUP   0x07000000U   /*!< DMAMUX2 synchronization Signal is LPUART1 TX Wakeup      */
+#define LL_DMAMUX2_SYNC_LPTIM2_OUT        0x08000000U   /*!< DMAMUX2 synchronization Signal is LPTIM2 output          */
+#define LL_DMAMUX2_SYNC_LPTIM3_OUT        0x09000000U   /*!< DMAMUX2 synchronization Signal is LPTIM3 output          */
+#define LL_DMAMUX2_SYNC_I2C4_WKUP         0x0A000000U   /*!< DMAMUX2 synchronization Signal is I2C4 Wakeup            */
+#define LL_DMAMUX2_SYNC_SPI6_WKUP         0x0B000000U   /*!< DMAMUX2 synchronization Signal is SPI6 Wakeup            */
+#define LL_DMAMUX2_SYNC_COMP1_OUT         0x0C000000U   /*!< DMAMUX2 synchronization Signal is Comparator 1 output    */
+#define LL_DMAMUX2_SYNC_RTC_WKUP          0x0D000000U   /*!< DMAMUX2 synchronization Signal is RTC Wakeup             */
+#define LL_DMAMUX2_SYNC_EXTI0             0x0E000000U   /*!< DMAMUX2 synchronization Signal is EXTI0 IT               */
+#define LL_DMAMUX2_SYNC_EXTI2             0x0F000000U   /*!< DMAMUX2 synchronization Signal is EXTI2 IT               */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMAMUX_LL_EC_REQUEST_GENERATOR Request Generator Channel
+  * @{
+  */
+#define LL_DMAMUX_REQ_GEN_0           0x00000000U
+#define LL_DMAMUX_REQ_GEN_1           0x00000001U
+#define LL_DMAMUX_REQ_GEN_2           0x00000002U
+#define LL_DMAMUX_REQ_GEN_3           0x00000003U
+#define LL_DMAMUX_REQ_GEN_4           0x00000004U
+#define LL_DMAMUX_REQ_GEN_5           0x00000005U
+#define LL_DMAMUX_REQ_GEN_6           0x00000006U
+#define LL_DMAMUX_REQ_GEN_7           0x00000007U
+/**
+  * @}
+  */
+
+/** @defgroup DMAMUX_LL_EC_REQUEST_GEN_POLARITY External Request Signal Generation Polarity
+  * @{
+  */
+#define LL_DMAMUX_REQ_GEN_NO_EVENT             0x00000000U                                  /*!< No external DMA request  generation                        */
+#define LL_DMAMUX_REQ_GEN_POL_RISING           DMAMUX_RGxCR_GPOL_0                          /*!< External DMA request generation on event on rising edge    */
+#define LL_DMAMUX_REQ_GEN_POL_FALLING          DMAMUX_RGxCR_GPOL_1                          /*!< External DMA request generation on event on falling edge   */
+#define LL_DMAMUX_REQ_GEN_POL_RISING_FALLING   (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1)  /*!< External DMA request generation on rising and falling edge */
+/**
+  * @}
+  */
+
+/** @defgroup DMAMUX_LL_EC_REQUEST_GEN External Request Signal Generation
+  * @{
+  */
+#define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT   0U   /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel0 Event        */
+#define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT   1U   /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel1 Event        */
+#define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT   2U   /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel2 Event        */
+#define LL_DMAMUX1_REQ_GEN_LPTIM1_OUT        3U   /*!< DMAMUX1 Request generator Signal is LPTIM1 OUT                    */
+#define LL_DMAMUX1_REQ_GEN_LPTIM2_OUT        4U   /*!< DMAMUX1 Request generator Signal is LPTIM2 OUT                    */
+#define LL_DMAMUX1_REQ_GEN_LPTIM3_OUT        5U   /*!< DMAMUX1 Request generator Signal is LPTIM3 OUT                    */
+#define LL_DMAMUX1_REQ_GEN_EXTI0             6U   /*!< DMAMUX1 Request generator Signal is EXTI0 IT                      */
+#define LL_DMAMUX1_REQ_GEN_TIM12_TRGO        7U   /*!< DMAMUX1 Request generator Signal is TIM12 TRGO                    */
+
+#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT   0U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel0 Event        */
+#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT   1U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel1 Event        */
+#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT   2U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel2 Event        */
+#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT   3U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel3 Event        */
+#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT   4U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel4 Event        */
+#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT   5U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel5 Event        */
+#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT   6U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel6 Event        */
+#define LL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP   7U   /*!< DMAMUX2 Request generator Signal is LPUART1 RX Wakeup             */
+#define LL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP   8U   /*!< DMAMUX2 Request generator Signal is LPUART1 TX Wakeup             */
+#define LL_DMAMUX2_REQ_GEN_LPTIM2_WKUP       9U   /*!< DMAMUX2 Request generator Signal is LPTIM2 Wakeup                 */
+#define LL_DMAMUX2_REQ_GEN_LPTIM2_OUT       10U   /*!< DMAMUX2 Request generator Signal is LPTIM2 OUT                    */
+#define LL_DMAMUX2_REQ_GEN_LPTIM3_WKUP      11U   /*!< DMAMUX2 Request generator Signal is LPTIM3 Wakeup                 */
+#define LL_DMAMUX2_REQ_GEN_LPTIM3_OUT       12U   /*!< DMAMUX2 Request generator Signal is LPTIM3 OUT                    */
+#if defined (LPTIM4)
+#define LL_DMAMUX2_REQ_GEN_LPTIM4_WKUP      13U   /*!< DMAMUX2 Request generator Signal is LPTIM4 Wakeup                 */
+#endif /* LPTIM4 */
+#if defined (LPTIM5)
+#define LL_DMAMUX2_REQ_GEN_LPTIM5_WKUP      14U   /*!< DMAMUX2 Request generator Signal is LPTIM5 Wakeup                 */
+#endif /* LPTIM5 */
+#define LL_DMAMUX2_REQ_GEN_I2C4_WKUP        15U   /*!< DMAMUX2 Request generator Signal is I2C4 Wakeup                   */
+#define LL_DMAMUX2_REQ_GEN_SPI6_WKUP        16U   /*!< DMAMUX2 Request generator Signal is SPI6 Wakeup                   */
+#define LL_DMAMUX2_REQ_GEN_COMP1_OUT        17U   /*!< DMAMUX2 Request generator Signal is Comparator 1 output           */
+#define LL_DMAMUX2_REQ_GEN_COMP2_OUT        18U   /*!< DMAMUX2 Request generator Signal is Comparator 2 output           */
+#define LL_DMAMUX2_REQ_GEN_RTC_WKUP         19U   /*!< DMAMUX2 Request generator Signal is RTC Wakeup                    */
+#define LL_DMAMUX2_REQ_GEN_EXTI0            20U   /*!< DMAMUX2 Request generator Signal is EXTI0                         */
+#define LL_DMAMUX2_REQ_GEN_EXTI2            21U   /*!< DMAMUX2 Request generator Signal is EXTI2                         */
+#define LL_DMAMUX2_REQ_GEN_I2C4_IT_EVT      22U   /*!< DMAMUX2 Request generator Signal is I2C4 IT Event                 */
+#define LL_DMAMUX2_REQ_GEN_SPI6_IT          23U   /*!< DMAMUX2 Request generator Signal is SPI6 IT                       */
+#define LL_DMAMUX2_REQ_GEN_LPUART1_TX_IT    24U   /*!< DMAMUX2 Request generator Signal is LPUART1 Tx IT                 */
+#define LL_DMAMUX2_REQ_GEN_LPUART1_RX_IT    25U   /*!< DMAMUX2 Request generator Signal is LPUART1 Rx IT                 */
+#if defined (ADC3)
+#define LL_DMAMUX2_REQ_GEN_ADC3_IT          26U   /*!< DMAMUX2 Request generator Signal is ADC3 IT                       */
+#define LL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT    27U   /*!< DMAMUX2 Request generator Signal is ADC3 Analog Watchdog 1 output */
+#endif /* ADC3 */
+#define LL_DMAMUX2_REQ_GEN_BDMA_CH0_IT      28U   /*!< DMAMUX2 Request generator Signal is BDMA Channel 0 IT             */
+#define LL_DMAMUX2_REQ_GEN_BDMA_CH1_IT      29U   /*!< DMAMUX2 Request generator Signal is BDMA Channel 1 IT             */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DMAMUX_LL_Exported_Macros DMAMUX Exported Macros
+  * @{
+  */
+
+/** @defgroup DMAMUX_LL_EM_WRITE_READ Common Write and read registers macros
+  * @{
+  */
+/**
+  * @brief  Write a value in DMAMUX register
+  * @param  __INSTANCE__ DMAMUX Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_DMAMUX_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in DMAMUX register
+  * @param  __INSTANCE__ DMAMUX Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_DMAMUX_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DMAMUX_LL_Exported_Functions DMAMUX Exported Functions
+ * @{
+ */
+
+/** @defgroup DMAMUX_LL_EF_Configuration Configuration
+  * @{
+  */
+/**
+  * @brief  Set DMAMUX request ID for DMAMUX Channel x.
+  * @note   DMAMUX1 channel 0 to 7 are mapped to DMA1 channel 0 to 7.
+  *         DMAMUX1 channel 8 to 15 are mapped to DMA2 channel 0 to 7.
+  *         DMAMUX2 channel 0 to 7 are mapped to  BDMA channel 0 to 7.
+  * @rmtoll CxCR         DMAREQ_ID     LL_DMAMUX_SetRequestID
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @param  Request This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX1_REQ_MEM2MEM
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR0
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR1
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR2
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR3
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR4
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR5
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR6
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR7
+  *         @arg @ref LL_DMAMUX1_REQ_ADC1
+  *         @arg @ref LL_DMAMUX1_REQ_ADC2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_COM
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_UP
+  *         @arg @ref LL_DMAMUX1_REQ_I2C1_RX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C1_TX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C2_RX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C2_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI1_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI1_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI2_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI2_TX
+  *         @arg @ref LL_DMAMUX1_REQ_USART1_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART1_TX
+  *         @arg @ref LL_DMAMUX1_REQ_USART2_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART2_TX
+  *         @arg @ref LL_DMAMUX1_REQ_USART3_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART3_TX
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_COM
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_SPI3_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI3_TX
+  *         @arg @ref LL_DMAMUX1_REQ_UART4_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART4_TX
+  *         @arg @ref LL_DMAMUX1_REQ_UART5_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART5_TX
+  *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM6_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM7_UP
+  *         @arg @ref LL_DMAMUX1_REQ_USART6_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART6_TX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C3_RX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C3_TX
+  *         @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI
+  *         @arg @ref LL_DMAMUX1_REQ_CRYP_IN
+  *         @arg @ref LL_DMAMUX1_REQ_CRYP_OUT
+  *         @arg @ref LL_DMAMUX1_REQ_HASH_IN
+  *         @arg @ref LL_DMAMUX1_REQ_UART7_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART7_TX
+  *         @arg @ref LL_DMAMUX1_REQ_UART8_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART8_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI4_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI4_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI5_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI5_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SAI1_A
+  *         @arg @ref LL_DMAMUX1_REQ_SAI1_B
+  *         @arg @ref LL_DMAMUX1_REQ_SAI2_A
+  *         @arg @ref LL_DMAMUX1_REQ_SAI2_B
+  *         @arg @ref LL_DMAMUX1_REQ_SWPMI_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SWPMI_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
+  *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*)
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_COM
+  *         @arg @ref LL_DMAMUX1_REQ_TIM16_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM16_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM17_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM17_UP
+  *         @arg @ref LL_DMAMUX1_REQ_SAI3_A (*)
+  *         @arg @ref LL_DMAMUX1_REQ_SAI3_B (*)
+  *         @arg @ref LL_DMAMUX1_REQ_ADC3 (*)
+  *         @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
+  *         @arg @ref LL_DMAMUX1_REQ_UART9_TX (*)
+  *         @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
+  *         @arg @ref LL_DMAMUX1_REQ_USART10_TX (*)
+  *         @arg @ref LL_DMAMUX2_REQ_MEM2MEM
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR0
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR1
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR2
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR3
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR4
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR5
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR6
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR7
+  *         @arg @ref LL_DMAMUX2_REQ_LPUART1_RX
+  *         @arg @ref LL_DMAMUX2_REQ_LPUART1_TX
+  *         @arg @ref LL_DMAMUX2_REQ_SPI6_RX
+  *         @arg @ref LL_DMAMUX2_REQ_SPI6_TX
+  *         @arg @ref LL_DMAMUX2_REQ_I2C4_RX
+  *         @arg @ref LL_DMAMUX2_REQ_I2C4_TX
+  *         @arg @ref LL_DMAMUX2_REQ_SAI4_A (*)
+  *         @arg @ref LL_DMAMUX2_REQ_SAI4_B (*)
+  *         @arg @ref LL_DMAMUX2_REQ_ADC3 (*)
+  *         @arg @ref LL_DMAMUX2_REQ_DAC2_CH1 (*)
+  *         @arg @ref LL_DMAMUX2_REQ_DFSDM2_FLT0 (*)
+  * @note   (*) Availability depends on devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
+}
+
+/**
+  * @brief  Get DMAMUX request ID for DMAMUX Channel x.
+  * @note   DMAMUX1 channel 0 to 7  are mapped to DMA1 channel 0 to 7.
+  *         DMAMUX1 channel 8 to 15 are mapped to DMA2 channel 0 to 7.
+  *         DMAMUX2 channel 0 to 7  are mapped to BDMA channel 0 to 7.
+  * @rmtoll CxCR         DMAREQ_ID     LL_DMAMUX_GetRequestID
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMAMUX1_REQ_MEM2MEM
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR0
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR1
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR2
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR3
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR4
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR5
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR6
+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR7
+  *         @arg @ref LL_DMAMUX1_REQ_ADC1
+  *         @arg @ref LL_DMAMUX1_REQ_ADC2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_COM
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_UP
+  *         @arg @ref LL_DMAMUX1_REQ_I2C1_RX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C1_TX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C2_RX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C2_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI1_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI1_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI2_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI2_TX
+  *         @arg @ref LL_DMAMUX1_REQ_USART1_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART1_TX
+  *         @arg @ref LL_DMAMUX1_REQ_USART2_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART2_TX
+  *         @arg @ref LL_DMAMUX1_REQ_USART3_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART3_TX
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_COM
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH4
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_SPI3_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI3_TX
+  *         @arg @ref LL_DMAMUX1_REQ_UART4_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART4_TX
+  *         @arg @ref LL_DMAMUX1_REQ_UART5_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART5_TX
+  *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH2
+  *         @arg @ref LL_DMAMUX1_REQ_TIM6_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM7_UP
+  *         @arg @ref LL_DMAMUX1_REQ_USART6_RX
+  *         @arg @ref LL_DMAMUX1_REQ_USART6_TX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C3_RX
+  *         @arg @ref LL_DMAMUX1_REQ_I2C3_TX
+  *         @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI
+  *         @arg @ref LL_DMAMUX1_REQ_CRYP_IN
+  *         @arg @ref LL_DMAMUX1_REQ_CRYP_OUT
+  *         @arg @ref LL_DMAMUX1_REQ_HASH_IN
+  *         @arg @ref LL_DMAMUX1_REQ_UART7_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART7_TX
+  *         @arg @ref LL_DMAMUX1_REQ_UART8_RX
+  *         @arg @ref LL_DMAMUX1_REQ_UART8_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI4_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI4_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI5_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SPI5_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SAI1_A
+  *         @arg @ref LL_DMAMUX1_REQ_SAI1_B
+  *         @arg @ref LL_DMAMUX1_REQ_SAI2_A
+  *         @arg @ref LL_DMAMUX1_REQ_SAI2_B
+  *         @arg @ref LL_DMAMUX1_REQ_SWPMI_RX
+  *         @arg @ref LL_DMAMUX1_REQ_SWPMI_TX
+  *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
+  *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*)
+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*)
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2
+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG
+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_COM
+  *         @arg @ref LL_DMAMUX1_REQ_TIM16_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM16_UP
+  *         @arg @ref LL_DMAMUX1_REQ_TIM17_CH1
+  *         @arg @ref LL_DMAMUX1_REQ_TIM17_UP
+  *         @arg @ref LL_DMAMUX1_REQ_SAI3_A (*)
+  *         @arg @ref LL_DMAMUX1_REQ_SAI3_B (*)
+  *         @arg @ref LL_DMAMUX1_REQ_ADC3 (*)
+  *         @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
+  *         @arg @ref LL_DMAMUX1_REQ_UART9_TX (*)
+  *         @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
+  *         @arg @ref LL_DMAMUX1_REQ_USART10_TX (*)
+  *         @arg @ref LL_DMAMUX2_REQ_MEM2MEM
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR0
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR1
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR2
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR3
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR4
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR5
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR6
+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR7
+  *         @arg @ref LL_DMAMUX2_REQ_LPUART1_RX
+  *         @arg @ref LL_DMAMUX2_REQ_LPUART1_TX
+  *         @arg @ref LL_DMAMUX2_REQ_SPI6_RX
+  *         @arg @ref LL_DMAMUX2_REQ_SPI6_TX
+  *         @arg @ref LL_DMAMUX2_REQ_I2C4_RX
+  *         @arg @ref LL_DMAMUX2_REQ_I2C4_TX
+  *         @arg @ref LL_DMAMUX2_REQ_SAI4_A (*)
+  *         @arg @ref LL_DMAMUX2_REQ_SAI4_B (*)
+  *         @arg @ref LL_DMAMUX2_REQ_ADC3 (*)
+  *         @arg @ref LL_DMAMUX2_REQ_DAC2_CH1 (*)
+  *         @arg @ref LL_DMAMUX2_REQ_DFSDM2_FLT0 (*)
+  * @note   (*) Availability depends on devices.
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID));
+}
+
+/**
+  * @brief  Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
+  * @rmtoll CxCR         NBREQ         LL_DMAMUX_SetSyncRequestNb
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @param  RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_NBREQ, (RequestNb - 1U) << DMAMUX_CxCR_NBREQ_Pos);
+}
+
+/**
+  * @brief  Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
+  * @rmtoll CxCR         NBREQ         LL_DMAMUX_GetSyncRequestNb
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval Between Min_Data = 1 and Max_Data = 32
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return (uint32_t)((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_NBREQ) >> DMAMUX_CxCR_NBREQ_Pos) + 1U);
+}
+
+/**
+  * @brief  Set the polarity of the signal on which the DMA request is synchronized.
+  * @rmtoll CxCR         SPOL          LL_DMAMUX_SetSyncPolarity
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_SYNC_NO_EVENT
+  *         @arg @ref LL_DMAMUX_SYNC_POL_RISING
+  *         @arg @ref LL_DMAMUX_SYNC_POL_FALLING
+  *         @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SPOL, Polarity);
+}
+
+/**
+  * @brief  Get the polarity of the signal on which the DMA request is synchronized.
+  * @rmtoll CxCR         SPOL          LL_DMAMUX_GetSyncPolarity
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMAMUX_SYNC_NO_EVENT
+  *         @arg @ref LL_DMAMUX_SYNC_POL_RISING
+  *         @arg @ref LL_DMAMUX_SYNC_POL_FALLING
+  *         @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SPOL));
+}
+
+/**
+  * @brief  Enable the Event Generation on DMAMUX channel x.
+  * @rmtoll CxCR         EGE           LL_DMAMUX_EnableEventGeneration
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE);
+}
+
+/**
+  * @brief  Disable the Event Generation on DMAMUX channel x.
+  * @rmtoll CxCR         EGE           LL_DMAMUX_DisableEventGeneration
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  CLEAR_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE);
+}
+
+/**
+  * @brief  Check if the Event Generation on DMAMUX channel x is enabled or disabled.
+  * @rmtoll CxCR         EGE           LL_DMAMUX_IsEnabledEventGeneration
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the synchronization mode.
+  * @rmtoll CxCR         SE            LL_DMAMUX_EnableSync
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE);
+}
+
+/**
+  * @brief  Disable the synchronization mode.
+  * @rmtoll CxCR         SE            LL_DMAMUX_DisableSync
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  CLEAR_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE);
+}
+
+/**
+  * @brief  Check if the synchronization mode is enabled or disabled.
+  * @rmtoll CxCR         SE            LL_DMAMUX_IsEnabledSync
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set DMAMUX synchronization ID  on DMAMUX Channel x.
+  * @rmtoll CxCR         SYNC_ID       LL_DMAMUX_SetSyncID
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @param  SyncID This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT
+  *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT
+  *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT
+  *         @arg @ref LL_DMAMUX1_SYNC_LPTIM1_OUT
+  *         @arg @ref LL_DMAMUX1_SYNC_LPTIM2_OUT
+  *         @arg @ref LL_DMAMUX1_SYNC_LPTIM3_OUT
+  *         @arg @ref LL_DMAMUX1_SYNC_EXTI0
+  *         @arg @ref LL_DMAMUX1_SYNC_TIM12_TRGO
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_LPUART1_RX_WKUP
+  *         @arg @ref LL_DMAMUX2_SYNC_LPUART1_TX_WKUP
+  *         @arg @ref LL_DMAMUX2_SYNC_LPTIM2_OUT
+  *         @arg @ref LL_DMAMUX2_SYNC_LPTIM3_OUT
+  *         @arg @ref LL_DMAMUX2_SYNC_I2C4_WKUP
+  *         @arg @ref LL_DMAMUX2_SYNC_SPI6_WKUP
+  *         @arg @ref LL_DMAMUX2_SYNC_COMP1_OUT
+  *         @arg @ref LL_DMAMUX2_SYNC_RTC_WKUP
+  *         @arg @ref LL_DMAMUX2_SYNC_EXTI0
+  *         @arg @ref LL_DMAMUX2_SYNC_EXTI2
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SYNC_ID, SyncID);
+}
+
+/**
+  * @brief  Get DMAMUX synchronization ID  on DMAMUX Channel x.
+  * @rmtoll CxCR         SYNC_ID       LL_DMAMUX_GetSyncID
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT
+  *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT
+  *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT
+  *         @arg @ref LL_DMAMUX1_SYNC_LPTIM1_OUT
+  *         @arg @ref LL_DMAMUX1_SYNC_LPTIM2_OUT
+  *         @arg @ref LL_DMAMUX1_SYNC_LPTIM3_OUT
+  *         @arg @ref LL_DMAMUX1_SYNC_EXTI0
+  *         @arg @ref LL_DMAMUX1_SYNC_TIM12_TRGO
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_LPUART1_RX_WKUP
+  *         @arg @ref LL_DMAMUX2_SYNC_LPUART1_TX_WKUP
+  *         @arg @ref LL_DMAMUX2_SYNC_LPTIM2_OUT
+  *         @arg @ref LL_DMAMUX2_SYNC_LPTIM3_OUT
+  *         @arg @ref LL_DMAMUX2_SYNC_I2C4_WKUP
+  *         @arg @ref LL_DMAMUX2_SYNC_SPI6_WKUP
+  *         @arg @ref LL_DMAMUX2_SYNC_COMP1_OUT
+  *         @arg @ref LL_DMAMUX2_SYNC_RTC_WKUP
+  *         @arg @ref LL_DMAMUX2_SYNC_EXTI0
+  *         @arg @ref LL_DMAMUX2_SYNC_EXTI2
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SYNC_ID));
+}
+
+/**
+  * @brief  Enable the Request Generator.
+  * @rmtoll RGxCR        GE            LL_DMAMUX_EnableRequestGen
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  *         @arg @ref LL_DMAMUX_REQ_GEN_4
+  *         @arg @ref LL_DMAMUX_REQ_GEN_5
+  *         @arg @ref LL_DMAMUX_REQ_GEN_6
+  *         @arg @ref LL_DMAMUX_REQ_GEN_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * (RequestGenChannel))))->RGCR, DMAMUX_RGxCR_GE);
+}
+
+/**
+  * @brief  Disable the Request Generator.
+  * @rmtoll RGxCR        GE            LL_DMAMUX_DisableRequestGen
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * (RequestGenChannel))))->RGCR, DMAMUX_RGxCR_GE);
+}
+
+/**
+  * @brief  Check if the Request Generator is enabled or disabled.
+  * @rmtoll RGxCR        GE            LL_DMAMUX_IsEnabledRequestGen
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  *         @arg @ref LL_DMAMUX_REQ_GEN_4
+  *         @arg @ref LL_DMAMUX_REQ_GEN_5
+  *         @arg @ref LL_DMAMUX_REQ_GEN_6
+  *         @arg @ref LL_DMAMUX_REQ_GEN_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the polarity of the signal on which the DMA request is generated.
+  * @rmtoll RGxCR        GPOL          LL_DMAMUX_SetRequestGenPolarity
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  *         @arg @ref LL_DMAMUX_REQ_GEN_4
+  *         @arg @ref LL_DMAMUX_REQ_GEN_5
+  *         @arg @ref LL_DMAMUX_REQ_GEN_6
+  *         @arg @ref LL_DMAMUX_REQ_GEN_7
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
+  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
+  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
+  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GPOL, Polarity);
+}
+
+/**
+  * @brief  Get the polarity of the signal on which the DMA request is generated.
+  * @rmtoll RGxCR        GPOL          LL_DMAMUX_GetRequestGenPolarity
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  *         @arg @ref LL_DMAMUX_REQ_GEN_4
+  *         @arg @ref LL_DMAMUX_REQ_GEN_5
+  *         @arg @ref LL_DMAMUX_REQ_GEN_6
+  *         @arg @ref LL_DMAMUX_REQ_GEN_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
+  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
+  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
+  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GPOL));
+}
+
+/**
+  * @brief  Set the number of DMA request that will be autorized after a generation event.
+  * @note   This field can only be written when Generator is disabled.
+  * @rmtoll RGxCR        GNBREQ        LL_DMAMUX_SetGenRequestNb
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  *         @arg @ref LL_DMAMUX_REQ_GEN_4
+  *         @arg @ref LL_DMAMUX_REQ_GEN_5
+  *         @arg @ref LL_DMAMUX_REQ_GEN_6
+  *         @arg @ref LL_DMAMUX_REQ_GEN_7
+  * @param  RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GNBREQ, (RequestNb - 1U) << DMAMUX_RGxCR_GNBREQ_Pos);
+}
+
+/**
+  * @brief  Get the number of DMA request that will be autorized after a generation event.
+  * @rmtoll RGxCR        GNBREQ        LL_DMAMUX_GetGenRequestNb
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  *         @arg @ref LL_DMAMUX_REQ_GEN_4
+  *         @arg @ref LL_DMAMUX_REQ_GEN_5
+  *         @arg @ref LL_DMAMUX_REQ_GEN_6
+  *         @arg @ref LL_DMAMUX_REQ_GEN_7
+  * @retval Between Min_Data = 1 and Max_Data = 32
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return (uint32_t)((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1U);
+}
+
+/**
+  * @brief  Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x.
+  * @rmtoll RGxCR        SIG_ID        LL_DMAMUX_SetRequestSignalID
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  *         @arg @ref LL_DMAMUX_REQ_GEN_4
+  *         @arg @ref LL_DMAMUX_REQ_GEN_5
+  *         @arg @ref LL_DMAMUX_REQ_GEN_6
+  *         @arg @ref LL_DMAMUX_REQ_GEN_7
+  * @param  RequestSignalID This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
+  *         @arg @ref LL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
+  *         @arg @ref LL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
+  *         @arg @ref LL_DMAMUX1_REQ_GEN_LPTIM1_OUT
+  *         @arg @ref LL_DMAMUX1_REQ_GEN_LPTIM2_OUT
+  *         @arg @ref LL_DMAMUX1_REQ_GEN_LPTIM3_OUT
+  *         @arg @ref LL_DMAMUX1_REQ_GEN_EXTI0
+  *         @arg @ref LL_DMAMUX1_REQ_GEN_TIM12_TRGO
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM2_OUT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM3_OUT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM4_WKUP (*)
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM5_WKUP (*)
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_I2C4_WKUP
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_SPI6_WKUP
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_COMP1_OUT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_COMP2_OUT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_RTC_WKUP
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_EXTI0
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_EXTI2
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_SPI6_IT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_ADC3_IT (*)
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT (*)
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
+  *         @arg @ref LL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
+  * @note   (*) Availability depends on devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_SIG_ID, RequestSignalID);
+}
+
+/**
+  * @brief  Get DMAMUX external Request Signal ID set on DMAMUX Channel x.
+  * @rmtoll RGxCR        SIG_ID        LL_DMAMUX_GetRequestSignalID
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  *         @arg @ref LL_DMAMUX_REQ_GEN_4
+  *         @arg @ref LL_DMAMUX_REQ_GEN_5
+  *         @arg @ref LL_DMAMUX_REQ_GEN_6
+  *         @arg @ref LL_DMAMUX_REQ_GEN_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT
+  *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT
+  *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT
+  *         @arg @ref LL_DMAMUX1_SYNC_LPTIM1_OUT
+  *         @arg @ref LL_DMAMUX1_SYNC_LPTIM2_OUT
+  *         @arg @ref LL_DMAMUX1_SYNC_LPTIM3_OUT
+  *         @arg @ref LL_DMAMUX1_SYNC_EXTI0
+  *         @arg @ref LL_DMAMUX1_SYNC_TIM12_TRGO
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT
+  *         @arg @ref LL_DMAMUX2_SYNC_LPUART1_RX_WKUP
+  *         @arg @ref LL_DMAMUX2_SYNC_LPUART1_TX_WKUP
+  *         @arg @ref LL_DMAMUX2_SYNC_LPTIM2_OUT
+  *         @arg @ref LL_DMAMUX2_SYNC_LPTIM3_OUT
+  *         @arg @ref LL_DMAMUX2_SYNC_I2C4_WKUP
+  *         @arg @ref LL_DMAMUX2_SYNC_SPI6_WKUP
+  *         @arg @ref LL_DMAMUX2_SYNC_COMP1_OUT
+  *         @arg @ref LL_DMAMUX2_SYNC_RTC_WKUP
+  *         @arg @ref LL_DMAMUX2_SYNC_EXTI0
+  *         @arg @ref LL_DMAMUX2_SYNC_EXTI2
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_SIG_ID));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMAMUX_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 0.
+  * @rmtoll CSR          SOF0          LL_DMAMUX_IsActiveFlag_SO0
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF0) == (DMAMUX_CSR_SOF0)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 1.
+  * @rmtoll CSR          SOF1          LL_DMAMUX_IsActiveFlag_SO1
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF1) == (DMAMUX_CSR_SOF1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 2.
+  * @rmtoll CSR          SOF2          LL_DMAMUX_IsActiveFlag_SO2
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF2) == (DMAMUX_CSR_SOF2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 3.
+  * @rmtoll CSR          SOF3          LL_DMAMUX_IsActiveFlag_SO3
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF3) == (DMAMUX_CSR_SOF3)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 4.
+  * @rmtoll CSR          SOF4          LL_DMAMUX_IsActiveFlag_SO4
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF4) == (DMAMUX_CSR_SOF4)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 5.
+  * @rmtoll CSR          SOF5          LL_DMAMUX_IsActiveFlag_SO5
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF5) == (DMAMUX_CSR_SOF5)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 6.
+  * @rmtoll CSR          SOF6          LL_DMAMUX_IsActiveFlag_SO6
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 7.
+  * @rmtoll CSR          SOF7          LL_DMAMUX_IsActiveFlag_SO7
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 8.
+  * @rmtoll CSR          SOF8          LL_DMAMUX_IsActiveFlag_SO8
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 9.
+  * @rmtoll CSR          SOF9          LL_DMAMUX_IsActiveFlag_SO9
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 10.
+  * @rmtoll CSR          SOF10         LL_DMAMUX_IsActiveFlag_SO10
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 11.
+  * @rmtoll CSR          SOF11         LL_DMAMUX_IsActiveFlag_SO11
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 12.
+  * @rmtoll CSR          SOF12         LL_DMAMUX_IsActiveFlag_SO12
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF12) == (DMAMUX_CSR_SOF12)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 13.
+  * @rmtoll CSR          SOF13         LL_DMAMUX_IsActiveFlag_SO13
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF13) == (DMAMUX_CSR_SOF13)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 14.
+  * @rmtoll CSR          SOF14         LL_DMAMUX_IsActiveFlag_SO14
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF14) == (DMAMUX_CSR_SOF14)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Synchronization Event Overrun Flag Channel 15.
+  * @rmtoll CSR          SOF15         LL_DMAMUX_IsActiveFlag_SO15
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF15) == (DMAMUX_CSR_SOF15)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Request Generator 0 Trigger Event Overrun Flag.
+  * @rmtoll RGSR         OF0           LL_DMAMUX_IsActiveFlag_RGO0
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF0) == (DMAMUX_RGSR_OF0)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Request Generator 1 Trigger Event Overrun Flag.
+  * @rmtoll RGSR         OF1           LL_DMAMUX_IsActiveFlag_RGO1
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF1) == (DMAMUX_RGSR_OF1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Request Generator 2 Trigger Event Overrun Flag.
+  * @rmtoll RGSR         OF2           LL_DMAMUX_IsActiveFlag_RGO2
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF2) == (DMAMUX_RGSR_OF2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Request Generator 3 Trigger Event Overrun Flag.
+  * @rmtoll RGSR         OF3           LL_DMAMUX_IsActiveFlag_RGO3
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF3) == (DMAMUX_RGSR_OF3)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Request Generator 4 Trigger Event Overrun Flag.
+  * @rmtoll RGSR         OF4           LL_DMAMUX_IsActiveFlag_RGO4
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO4(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF4) == (DMAMUX_RGSR_OF4)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Request Generator 5 Trigger Event Overrun Flag.
+  * @rmtoll RGSR         OF5           LL_DMAMUX_IsActiveFlag_RGO5
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO5(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF5) == (DMAMUX_RGSR_OF5)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Request Generator 6 Trigger Event Overrun Flag.
+  * @rmtoll RGSR         OF6           LL_DMAMUX_IsActiveFlag_RGO6
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO6(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF6) == (DMAMUX_RGSR_OF6)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Request Generator 7 Trigger Event Overrun Flag.
+  * @rmtoll RGSR         OF7           LL_DMAMUX_IsActiveFlag_RGO7
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO7(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF7) == (DMAMUX_RGSR_OF7)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 0.
+  * @rmtoll CFR          CSOF0         LL_DMAMUX_ClearFlag_SO0
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF0);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 1.
+  * @rmtoll CFR          CSOF1         LL_DMAMUX_ClearFlag_SO1
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF1);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 2.
+  * @rmtoll CFR          CSOF2         LL_DMAMUX_ClearFlag_SO2
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF2);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 3.
+  * @rmtoll CFR          CSOF3         LL_DMAMUX_ClearFlag_SO3
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF3);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 4.
+  * @rmtoll CFR          CSOF4         LL_DMAMUX_ClearFlag_SO4
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF4);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 5.
+  * @rmtoll CFR          CSOF5         LL_DMAMUX_ClearFlag_SO5
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF5);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 6.
+  * @rmtoll CFR          CSOF6         LL_DMAMUX_ClearFlag_SO6
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF6);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 7.
+  * @rmtoll CFR          CSOF7         LL_DMAMUX_ClearFlag_SO7
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF7);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 8.
+  * @rmtoll CFR          CSOF8         LL_DMAMUX_ClearFlag_SO8
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF8);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 9.
+  * @rmtoll CFR          CSOF9         LL_DMAMUX_ClearFlag_SO9
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF9);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 10.
+  * @rmtoll CFR          CSOF10        LL_DMAMUX_ClearFlag_SO10
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF10);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 11.
+  * @rmtoll CFR          CSOF11        LL_DMAMUX_ClearFlag_SO11
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF11);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 12.
+  * @rmtoll CFR          CSOF12        LL_DMAMUX_ClearFlag_SO12
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF12);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 13.
+  * @rmtoll CFR          CSOF13        LL_DMAMUX_ClearFlag_SO13
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF13);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 14.
+  * @rmtoll CFR          CSOF14        LL_DMAMUX_ClearFlag_SO14
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF14);
+}
+
+/**
+  * @brief  Clear Synchronization Event Overrun Flag Channel 15.
+  * @rmtoll CFR          CSOF15        LL_DMAMUX_ClearFlag_SO15
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF15);
+}
+
+/**
+  * @brief  Clear Request Generator 0 Trigger Event Overrun Flag.
+  * @rmtoll RGCFR        COF0          LL_DMAMUX_ClearFlag_RGO0
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF0);
+}
+
+/**
+  * @brief  Clear Request Generator 1 Trigger Event Overrun Flag.
+  * @rmtoll RGCFR        COF1          LL_DMAMUX_ClearFlag_RGO1
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF1);
+}
+
+/**
+  * @brief  Clear Request Generator 2 Trigger Event Overrun Flag.
+  * @rmtoll RGCFR        COF2          LL_DMAMUX_ClearFlag_RGO2
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF2);
+}
+
+/**
+  * @brief  Clear Request Generator 3 Trigger Event Overrun Flag.
+  * @rmtoll RGCFR        COF3          LL_DMAMUX_ClearFlag_RGO3
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF3);
+}
+
+/**
+  * @brief  Clear Request Generator 4 Trigger Event Overrun Flag.
+  * @rmtoll RGCFR        COF4          LL_DMAMUX_ClearFlag_RGO4
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO4(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF4);
+}
+
+/**
+  * @brief  Clear Request Generator 5 Trigger Event Overrun Flag.
+  * @rmtoll RGCFR        COF5          LL_DMAMUX_ClearFlag_RGO5
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO5(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF5);
+}
+
+/**
+  * @brief  Clear Request Generator 6 Trigger Event Overrun Flag.
+  * @rmtoll RGCFR        COF6          LL_DMAMUX_ClearFlag_RGO6
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO6(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF6);
+}
+
+/**
+  * @brief  Clear Request Generator 7 Trigger Event Overrun Flag.
+  * @rmtoll RGCFR        COF7          LL_DMAMUX_ClearFlag_RGO7
+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO7(DMAMUX_Channel_TypeDef *DMAMUXx)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF7);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMAMUX_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
+  * @rmtoll CxCR         SOIE          LL_DMAMUX_EnableIT_SO
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SOIE);
+}
+
+/**
+  * @brief  Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
+  * @rmtoll CxCR         SOIE          LL_DMAMUX_DisableIT_SO
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  CLEAR_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SOIE);
+}
+
+/**
+  * @brief  Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
+  * @rmtoll CxCR         SOIE          LL_DMAMUX_IsEnabledIT_SO
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_CHANNEL_0
+  *         @arg @ref LL_DMAMUX_CHANNEL_1
+  *         @arg @ref LL_DMAMUX_CHANNEL_2
+  *         @arg @ref LL_DMAMUX_CHANNEL_3
+  *         @arg @ref LL_DMAMUX_CHANNEL_4
+  *         @arg @ref LL_DMAMUX_CHANNEL_5
+  *         @arg @ref LL_DMAMUX_CHANNEL_6
+  *         @arg @ref LL_DMAMUX_CHANNEL_7
+  *         @arg @ref LL_DMAMUX_CHANNEL_8
+  *         @arg @ref LL_DMAMUX_CHANNEL_9
+  *         @arg @ref LL_DMAMUX_CHANNEL_10
+  *         @arg @ref LL_DMAMUX_CHANNEL_11
+  *         @arg @ref LL_DMAMUX_CHANNEL_12
+  *         @arg @ref LL_DMAMUX_CHANNEL_13
+  *         @arg @ref LL_DMAMUX_CHANNEL_14
+  *         @arg @ref LL_DMAMUX_CHANNEL_15
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return (READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SOIE));
+}
+
+/**
+  * @brief  Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
+  * @rmtoll RGxCR        OIE           LL_DMAMUX_EnableIT_RGO
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  *         @arg @ref LL_DMAMUX_REQ_GEN_4
+  *         @arg @ref LL_DMAMUX_REQ_GEN_5
+  *         @arg @ref LL_DMAMUX_REQ_GEN_6
+  *         @arg @ref LL_DMAMUX_REQ_GEN_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  SET_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE);
+}
+
+/**
+  * @brief  Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
+  * @rmtoll RGxCR        OIE           LL_DMAMUX_DisableIT_RGO
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  *         @arg @ref LL_DMAMUX_REQ_GEN_4
+  *         @arg @ref LL_DMAMUX_REQ_GEN_5
+  *         @arg @ref LL_DMAMUX_REQ_GEN_6
+  *         @arg @ref LL_DMAMUX_REQ_GEN_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE);
+}
+
+/**
+  * @brief  Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
+  * @rmtoll RGxCR        OIE           LL_DMAMUX_IsEnabledIT_RGO
+  * @param  DMAMUXx DMAMUXx Instance
+  * @param  RequestGenChannel This parameter can be one of the following values:
+  *         @arg @ref LL_DMAMUX_REQ_GEN_0
+  *         @arg @ref LL_DMAMUX_REQ_GEN_1
+  *         @arg @ref LL_DMAMUX_REQ_GEN_2
+  *         @arg @ref LL_DMAMUX_REQ_GEN_3
+  *         @arg @ref LL_DMAMUX_REQ_GEN_4
+  *         @arg @ref LL_DMAMUX_REQ_GEN_5
+  *         @arg @ref LL_DMAMUX_REQ_GEN_6
+  *         @arg @ref LL_DMAMUX_REQ_GEN_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
+{
+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
+
+  return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* DMAMUX1 || DMAMUX2 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32H7xx_LL_DMAMUX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_exti.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_exti.h
new file mode 100644
index 00000000..294f03a6
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_exti.h
@@ -0,0 +1,3159 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_exti.h
+  * @author  MCD Application Team
+  * @brief   Header file of EXTI LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32H7xx_LL_EXTI_H
+#define __STM32H7xx_LL_EXTI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined (EXTI)
+
+/** @defgroup EXTI_LL EXTI
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private Macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
+  * @{
+  */
+typedef struct
+{
+
+  uint32_t Line_0_31;           /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31
+                                     This parameter can be any combination of @ref EXTI_LL_EC_LINE */
+
+  uint32_t Line_32_63;          /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 32 to 63
+                                     This parameter can be any combination of @ref EXTI_LL_EC_LINE */
+
+  uint32_t Line_64_95;          /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 64 to 95
+                                     This parameter can be any combination of @ref EXTI_LL_EC_LINE */
+
+  FunctionalState LineCommand;  /*!< Specifies the new state of the selected EXTI lines.
+                                     This parameter can be set either to ENABLE or DISABLE */
+
+  uint8_t Mode;                 /*!< Specifies the mode for the EXTI lines.
+                                     This parameter can be a value of @ref EXTI_LL_EC_MODE. */
+
+  uint8_t Trigger;              /*!< Specifies the trigger signal active edge for the EXTI lines.
+                                     This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
+} LL_EXTI_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
+  * @{
+  */
+
+/** @defgroup EXTI_LL_EC_LINE LINE
+  * @{
+  */
+#define LL_EXTI_LINE_0                 EXTI_IMR1_IM0           /*!< Extended line 0 */
+#define LL_EXTI_LINE_1                 EXTI_IMR1_IM1           /*!< Extended line 1 */
+#define LL_EXTI_LINE_2                 EXTI_IMR1_IM2           /*!< Extended line 2 */
+#define LL_EXTI_LINE_3                 EXTI_IMR1_IM3           /*!< Extended line 3 */
+#define LL_EXTI_LINE_4                 EXTI_IMR1_IM4           /*!< Extended line 4 */
+#define LL_EXTI_LINE_5                 EXTI_IMR1_IM5           /*!< Extended line 5 */
+#define LL_EXTI_LINE_6                 EXTI_IMR1_IM6           /*!< Extended line 6 */
+#define LL_EXTI_LINE_7                 EXTI_IMR1_IM7           /*!< Extended line 7 */
+#define LL_EXTI_LINE_8                 EXTI_IMR1_IM8           /*!< Extended line 8 */
+#define LL_EXTI_LINE_9                 EXTI_IMR1_IM9           /*!< Extended line 9 */
+#define LL_EXTI_LINE_10                EXTI_IMR1_IM10          /*!< Extended line 10 */
+#define LL_EXTI_LINE_11                EXTI_IMR1_IM11          /*!< Extended line 11 */
+#define LL_EXTI_LINE_12                EXTI_IMR1_IM12          /*!< Extended line 12 */
+#define LL_EXTI_LINE_13                EXTI_IMR1_IM13          /*!< Extended line 13 */
+#define LL_EXTI_LINE_14                EXTI_IMR1_IM14          /*!< Extended line 14 */
+#define LL_EXTI_LINE_15                EXTI_IMR1_IM15          /*!< Extended line 15 */
+#define LL_EXTI_LINE_16                EXTI_IMR1_IM16          /*!< Extended line 16 */
+#define LL_EXTI_LINE_17                EXTI_IMR1_IM17          /*!< Extended line 17 */
+#define LL_EXTI_LINE_18                EXTI_IMR1_IM18          /*!< Extended line 18 */
+#define LL_EXTI_LINE_19                EXTI_IMR1_IM19          /*!< Extended line 19 */
+#define LL_EXTI_LINE_20                EXTI_IMR1_IM20          /*!< Extended line 20 */
+#define LL_EXTI_LINE_21                EXTI_IMR1_IM21          /*!< Extended line 21 */
+#define LL_EXTI_LINE_22                EXTI_IMR1_IM22          /*!< Extended line 22 */
+#define LL_EXTI_LINE_23                EXTI_IMR1_IM23          /*!< Extended line 23 */
+#define LL_EXTI_LINE_24                EXTI_IMR1_IM24          /*!< Extended line 24 */
+#define LL_EXTI_LINE_25                EXTI_IMR1_IM25          /*!< Extended line 25 */
+#define LL_EXTI_LINE_26                EXTI_IMR1_IM26          /*!< Extended line 26 */
+#define LL_EXTI_LINE_27                EXTI_IMR1_IM27          /*!< Extended line 27 */
+#define LL_EXTI_LINE_28                EXTI_IMR1_IM28          /*!< Extended line 28 */
+#define LL_EXTI_LINE_29                EXTI_IMR1_IM29          /*!< Extended line 29 */
+#define LL_EXTI_LINE_30                EXTI_IMR1_IM30          /*!< Extended line 30 */
+#define LL_EXTI_LINE_31                EXTI_IMR1_IM31          /*!< Extended line 31 */
+#define LL_EXTI_LINE_ALL_0_31          EXTI_IMR1_IM            /*!< All Extended line not reserved*/
+
+#define LL_EXTI_LINE_32                EXTI_IMR2_IM32          /*!< Extended line 32 */
+#define LL_EXTI_LINE_33                EXTI_IMR2_IM33          /*!< Extended line 33 */
+#define LL_EXTI_LINE_34                EXTI_IMR2_IM34          /*!< Extended line 34 */
+#define LL_EXTI_LINE_35                EXTI_IMR2_IM35          /*!< Extended line 35 */
+#define LL_EXTI_LINE_36                EXTI_IMR2_IM36          /*!< Extended line 36 */
+#define LL_EXTI_LINE_37                EXTI_IMR2_IM37          /*!< Extended line 37 */
+#define LL_EXTI_LINE_38                EXTI_IMR2_IM38          /*!< Extended line 38 */
+#define LL_EXTI_LINE_39                EXTI_IMR2_IM39          /*!< Extended line 39 */
+#define LL_EXTI_LINE_40                EXTI_IMR2_IM40          /*!< Extended line 40 */
+#define LL_EXTI_LINE_41                EXTI_IMR2_IM41          /*!< Extended line 41 */
+#define LL_EXTI_LINE_42                EXTI_IMR2_IM42          /*!< Extended line 42 */
+#define LL_EXTI_LINE_43                EXTI_IMR2_IM43          /*!< Extended line 43 */
+#if defined(USB2_OTG_FS)
+#define LL_EXTI_LINE_44                EXTI_IMR2_IM44          /*!< Extended line 44 */
+#endif /* USB2_OTG_FS */
+#if defined(DSI)
+#define LL_EXTI_LINE_46                EXTI_IMR2_IM46          /*!< Extended line 46 */
+#endif /* DSI */
+#define LL_EXTI_LINE_47                EXTI_IMR2_IM47          /*!< Extended line 47 */
+#define LL_EXTI_LINE_48                EXTI_IMR2_IM48          /*!< Extended line 48 */
+#define LL_EXTI_LINE_49                EXTI_IMR2_IM49          /*!< Extended line 49 */
+#define LL_EXTI_LINE_50                EXTI_IMR2_IM50          /*!< Extended line 50 */
+#define LL_EXTI_LINE_51                EXTI_IMR2_IM51          /*!< Extended line 51 */
+#define LL_EXTI_LINE_52                EXTI_IMR2_IM52          /*!< Extended line 52 */
+#define LL_EXTI_LINE_53                EXTI_IMR2_IM53          /*!< Extended line 53 */
+#define LL_EXTI_LINE_54                EXTI_IMR2_IM54          /*!< Extended line 54 */
+#define LL_EXTI_LINE_55                EXTI_IMR2_IM55          /*!< Extended line 55 */
+#define LL_EXTI_LINE_56                EXTI_IMR2_IM56          /*!< Extended line 56 */
+#define LL_EXTI_LINE_57                EXTI_IMR2_IM57          /*!< Extended line 57 */
+#define LL_EXTI_LINE_58                EXTI_IMR2_IM58          /*!< Extended line 58 */
+#define LL_EXTI_LINE_59                EXTI_IMR2_IM59          /*!< Extended line 59 */
+#define LL_EXTI_LINE_60                EXTI_IMR2_IM60          /*!< Extended line 60 */
+#define LL_EXTI_LINE_61                EXTI_IMR2_IM61          /*!< Extended line 61 */
+#define LL_EXTI_LINE_62                EXTI_IMR2_IM62          /*!< Extended line 62 */
+#define LL_EXTI_LINE_63                EXTI_IMR2_IM63          /*!< Extended line 63 */
+#define LL_EXTI_LINE_ALL_32_63         EXTI_IMR2_IM            /*!< All Extended line not reserved*/
+
+#define LL_EXTI_LINE_64                EXTI_IMR3_IM64          /*!< Extended line 64 */
+#define LL_EXTI_LINE_65                EXTI_IMR3_IM65          /*!< Extended line 65 */
+#define LL_EXTI_LINE_66                EXTI_IMR3_IM66          /*!< Extended line 66 */
+#define LL_EXTI_LINE_67                EXTI_IMR3_IM67          /*!< Extended line 67 */
+#define LL_EXTI_LINE_68                EXTI_IMR3_IM68          /*!< Extended line 68 */
+#define LL_EXTI_LINE_69                EXTI_IMR3_IM69          /*!< Extended line 69 */
+#define LL_EXTI_LINE_70                EXTI_IMR3_IM70          /*!< Extended line 70 */
+#define LL_EXTI_LINE_71                EXTI_IMR3_IM71          /*!< Extended line 71 */
+#define LL_EXTI_LINE_72                EXTI_IMR3_IM72          /*!< Extended line 72 */
+#define LL_EXTI_LINE_73                EXTI_IMR3_IM73          /*!< Extended line 73 */
+#define LL_EXTI_LINE_74                EXTI_IMR3_IM74          /*!< Extended line 74 */
+#if defined(ADC3)
+#define LL_EXTI_LINE_75                EXTI_IMR3_IM75          /*!< Extended line 75 */
+#endif /* ADC3 */
+#if defined(SAI4)
+#define LL_EXTI_LINE_76                EXTI_IMR3_IM76          /*!< Extended line 76 */
+#endif /* SAI4 */
+#if defined(DUAL_CORE)
+#define LL_EXTI_LINE_77                EXTI_IMR3_IM77          /*!< Extended line 77 */
+#define LL_EXTI_LINE_78                EXTI_IMR3_IM78          /*!< Extended line 78 */
+#define LL_EXTI_LINE_79                EXTI_IMR3_IM79          /*!< Extended line 79 */
+#define LL_EXTI_LINE_80                EXTI_IMR3_IM80          /*!< Extended line 80 */
+#define LL_EXTI_LINE_82                EXTI_IMR3_IM82          /*!< Extended line 82 */
+#define LL_EXTI_LINE_84                EXTI_IMR3_IM84          /*!< Extended line 84 */
+#endif /* DUAL_CORE */
+#define LL_EXTI_LINE_85                EXTI_IMR3_IM85          /*!< Extended line 85 */
+#if defined(ETH)
+#define LL_EXTI_LINE_86                EXTI_IMR3_IM86          /*!< Extended line 86 */
+#endif /* ETH */
+#define LL_EXTI_LINE_87                EXTI_IMR3_IM87          /*!< Extended line 87 */
+#if defined(DTS)
+#define LL_EXTI_LINE_88                EXTI_IMR3_IM88          /*!< Extended line 87 */
+#endif /* DTS */
+#define LL_EXTI_LINE_ALL_64_95         EXTI_IMR3_IM            /*!< All Extended line not reserved*/
+
+
+#define LL_EXTI_LINE_ALL               (0xFFFFFFFFU)  /*!< All Extended line */
+
+#if defined(USE_FULL_LL_DRIVER)
+#define LL_EXTI_LINE_NONE              (0x00000000U)  /*!< None Extended line */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/**
+  * @}
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/** @defgroup EXTI_LL_EC_MODE Mode
+  * @{
+  */
+#define LL_EXTI_MODE_IT               ((uint8_t)0x01U)      /*!< Cortex-M7 Interrupt Mode  */
+#define LL_EXTI_MODE_EVENT            ((uint8_t)0x02U)      /*!< Cortex-M7 Event Mode */
+#define LL_EXTI_MODE_IT_EVENT         ((uint8_t)0x03U)      /*!< Cortex-M7 Interrupt & Event Mode */
+
+#if defined(DUAL_CORE)
+#define LL_EXTI_MODE_C1_IT            LL_EXTI_MODE_IT       /*!< Cortex-M7 Interrupt Mode */
+#define LL_EXTI_MODE_C1_EVENT         LL_EXTI_MODE_EVENT    /*!< Cortex-M7 Event Mode */
+#define LL_EXTI_MODE_C1_IT_EVENT      LL_EXTI_MODE_IT_EVENT /*!< Cortex-M7 Interrupt & Event Mode */
+
+#define LL_EXTI_MODE_C2_IT            ((uint8_t)0x10U)      /*!< Cortex-M4 Interrupt Mode  */
+#define LL_EXTI_MODE_C2_EVENT         ((uint8_t)0x20U)      /*!< Cortex-M4 Event Mode  */
+#define LL_EXTI_MODE_C2_IT_EVENT      ((uint8_t)0x30U)      /*!< Cortex-M4 Interrupt & Event Mode */
+#endif /* DUAL_CORE */
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
+  * @{
+  */
+#define LL_EXTI_TRIGGER_NONE            ((uint8_t)0x00U) /*!< No Trigger Mode */
+#define LL_EXTI_TRIGGER_RISING          ((uint8_t)0x01U) /*!< Trigger Rising Mode */
+#define LL_EXTI_TRIGGER_FALLING         ((uint8_t)0x02U) /*!< Trigger Falling Mode */
+#define LL_EXTI_TRIGGER_RISING_FALLING  ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_D3_PEND_CLR D3 Pend Clear Source
+  * @{
+  */
+#define LL_EXTI_D3_PEND_CLR_DMACH6      ((uint8_t)0x00U) /*!< DMA ch6 event selected as D3 domain pendclear source */
+#define LL_EXTI_D3_PEND_CLR_DMACH7      ((uint8_t)0x01U) /*!< DMA ch7 event selected as D3 domain pendclear source */
+#if defined (LPTIM4)
+#define LL_EXTI_D3_PEND_CLR_LPTIM4      ((uint8_t)0x02U) /*!< LPTIM4 out selected as D3 domain pendclear source */
+#else
+#define LL_EXTI_D3_PEND_CLR_LPTIM2      ((uint8_t)0x02U) /*!< LPTIM2 out selected as D3 domain pendclear source */
+#endif /*LPTIM4*/
+#if defined (LPTIM5)
+#define LL_EXTI_D3_PEND_CLR_LPTIM5      ((uint8_t)0x03U) /*!< LPTIM5 out selected as D3 domain pendclear source */
+#else
+#define LL_EXTI_D3_PEND_CLR_LPTIM3      ((uint8_t)0x02U) /*!< LPTIM3 out selected as D3 domain pendclear source */
+#endif /*LPTIM5*/
+/**
+  * @}
+  */
+
+
+#endif /*USE_FULL_LL_DRIVER*/
+
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
+  * @{
+  */
+
+/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in EXTI register
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in EXTI register
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
+ * @{
+ */
+/** @defgroup EXTI_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable ExtiLine Interrupt request for Lines in range 0 to 31
+  * @rmtoll IMR1         IMx           LL_EXTI_EnableIT_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->IMR1, ExtiLine);
+}
+
+/**
+  * @brief  Enable ExtiLine Interrupt request for Lines in range 32 to 63
+  * @rmtoll IMR2         IMx           LL_EXTI_EnableIT_32_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44
+  *         @arg @ref LL_EXTI_LINE_46
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_59
+  *         @arg @ref LL_EXTI_LINE_60
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->IMR2, ExtiLine);
+}
+
+
+/**
+  * @brief  Enable ExtiLine Interrupt request for Lines in range 64 to 95
+  * @rmtoll IMR3         IMx           LL_EXTI_EnableIT_64_95
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_67
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_75
+  *         @arg @ref LL_EXTI_LINE_76
+  *         @arg @ref LL_EXTI_LINE_77
+  *         @arg @ref LL_EXTI_LINE_78
+  *         @arg @ref LL_EXTI_LINE_79
+  *         @arg @ref LL_EXTI_LINE_80
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  *         @arg @ref LL_EXTI_LINE_87
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableIT_64_95(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->IMR3, ExtiLine);
+}
+
+
+/**
+  * @brief  Disable ExtiLine Interrupt request for Lines in range 0 to 31
+  * @rmtoll IMR1         IMx           LL_EXTI_DisableIT_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->IMR1, ExtiLine);
+}
+
+
+/**
+  * @brief  Disable ExtiLine Interrupt request for Lines in range 32 to 63
+  * @rmtoll IMR2         IMx           LL_EXTI_DisableIT_32_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44
+  *         @arg @ref LL_EXTI_LINE_46
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_59
+  *         @arg @ref LL_EXTI_LINE_60
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->IMR2, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Interrupt request for Lines in range 64 to 95
+  * @rmtoll IMR3         IMx           LL_EXTI_DisableIT_64_95
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_67
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_75
+  *         @arg @ref LL_EXTI_LINE_76
+  *         @arg @ref LL_EXTI_LINE_77
+  *         @arg @ref LL_EXTI_LINE_78
+  *         @arg @ref LL_EXTI_LINE_79
+  *         @arg @ref LL_EXTI_LINE_80
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  *         @arg @ref LL_EXTI_LINE_87
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableIT_64_95(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->IMR3, ExtiLine);
+}
+
+
+/**
+  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
+  * @rmtoll IMR1         IMx           LL_EXTI_IsEnabledIT_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->IMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+
+/**
+  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63
+  * @rmtoll IMR2         IMx           LL_EXTI_IsEnabledIT_32_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44
+  *         @arg @ref LL_EXTI_LINE_46
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_59
+  *         @arg @ref LL_EXTI_LINE_60
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->IMR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+
+/**
+  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 64 to 95
+  * @rmtoll IMR3         IMx           LL_EXTI_IsEnabledIT_64_95
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_67
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_75
+  *         @arg @ref LL_EXTI_LINE_76
+  *         @arg @ref LL_EXTI_LINE_77
+  *         @arg @ref LL_EXTI_LINE_78
+  *         @arg @ref LL_EXTI_LINE_79
+  *         @arg @ref LL_EXTI_LINE_80
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  *         @arg @ref LL_EXTI_LINE_87
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_64_95(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->IMR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Enable ExtiLine Interrupt request for Lines in range 0 to 31 for cpu2
+  * @rmtoll C2IMR1         IMx           LL_C2_EXTI_EnableIT_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_EXTI_EnableIT_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->C2IMR1, ExtiLine);
+}
+
+
+/**
+  * @brief  Enable ExtiLine Interrupt request for Lines in range 32 to 63 for cpu2
+  * @rmtoll C2IMR2         IMx           LL_C2_EXTI_EnableIT_32_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44
+  *         @arg @ref LL_EXTI_LINE_46
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_59
+  *         @arg @ref LL_EXTI_LINE_60
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_EXTI_EnableIT_32_63(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->C2IMR2, ExtiLine);
+}
+
+
+/**
+  * @brief  Enable ExtiLine Interrupt request for Lines in range 64 to 95
+  * @rmtoll C2IMR3         IMx           LL_C2_EXTI_EnableIT_64_95
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_67
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_75
+  *         @arg @ref LL_EXTI_LINE_76
+  *         @arg @ref LL_EXTI_LINE_77
+  *         @arg @ref LL_EXTI_LINE_78
+  *         @arg @ref LL_EXTI_LINE_79
+  *         @arg @ref LL_EXTI_LINE_80
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  *         @arg @ref LL_EXTI_LINE_87
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_EXTI_EnableIT_64_95(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->C2IMR3, ExtiLine);
+}
+
+
+/**
+  * @brief  Disable ExtiLine Interrupt request for Lines in range 0 to 31 for cpu2
+  * @rmtoll C2IMR1         IMx           LL_C2_EXTI_DisableIT_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_EXTI_DisableIT_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->C2IMR1, ExtiLine);
+}
+
+
+
+/**
+  * @brief  Disable ExtiLine Interrupt request for Lines in range 32 to 63 for cpu2
+  * @rmtoll C2IMR2         IMx           LL_C2_EXTI_DisableIT_32_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44
+  *         @arg @ref LL_EXTI_LINE_46
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_59
+  *         @arg @ref LL_EXTI_LINE_60
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_EXTI_DisableIT_32_63(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->C2IMR2, ExtiLine);
+}
+
+
+/**
+  * @brief  Disable ExtiLine Interrupt request for Lines in range 64 to 95 for cpu2
+  * @rmtoll C2IMR3         IMx           LL_C2_EXTI_DisableIT_64_95
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_67
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_75
+  *         @arg @ref LL_EXTI_LINE_76
+  *         @arg @ref LL_EXTI_LINE_77
+  *         @arg @ref LL_EXTI_LINE_78
+  *         @arg @ref LL_EXTI_LINE_79
+  *         @arg @ref LL_EXTI_LINE_80
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  *         @arg @ref LL_EXTI_LINE_87
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_EXTI_DisableIT_64_95(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->C2IMR3, ExtiLine);
+}
+
+
+/**
+  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 for cpu2
+  * @rmtoll C2IMR1         IMx           LL_C2_EXTI_IsEnabledIT_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->C2IMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+
+/**
+  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63 for cpu2
+  * @rmtoll C2IMR2         IMx           LL_C2_EXTI_IsEnabledIT_32_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44
+  *         @arg @ref LL_EXTI_LINE_46
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_59
+  *         @arg @ref LL_EXTI_LINE_60
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->C2IMR2, ExtiLine) == (ExtiLine))? 1U : 0U);
+}
+
+
+/**
+  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 64 to 95
+  * @rmtoll C2IMR3         IMx           LL_C2_EXTI_IsEnabledIT_64_95
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_67
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_75
+  *         @arg @ref LL_EXTI_LINE_76
+  *         @arg @ref LL_EXTI_LINE_77
+  *         @arg @ref LL_EXTI_LINE_78
+  *         @arg @ref LL_EXTI_LINE_79
+  *         @arg @ref LL_EXTI_LINE_80
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  *         @arg @ref LL_EXTI_LINE_87
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_64_95(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->C2IMR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+#endif /* DUAL_CORE */
+
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Event_Management Event_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable ExtiLine Event request for Lines in range 0 to 31
+  * @rmtoll EMR1         EMx           LL_EXTI_EnableEvent_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->EMR1, ExtiLine);
+}
+
+/**
+  * @brief  Enable ExtiLine Event request for Lines in range 32 to 63
+  * @rmtoll EMR2         EMx           LL_EXTI_EnableEvent_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44
+  *         @arg @ref LL_EXTI_LINE_46
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_59
+  *         @arg @ref LL_EXTI_LINE_60
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->EMR2, ExtiLine);
+}
+
+/**
+  * @brief  Enable ExtiLine Event request for Lines in range 64 to 95
+  * @rmtoll EMR3         EMx           LL_EXTI_EnableEvent_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_67
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_75
+  *         @arg @ref LL_EXTI_LINE_76
+  *         @arg @ref LL_EXTI_LINE_77
+  *         @arg @ref LL_EXTI_LINE_78
+  *         @arg @ref LL_EXTI_LINE_79
+  *         @arg @ref LL_EXTI_LINE_80
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  *         @arg @ref LL_EXTI_LINE_87
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableEvent_64_95(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->EMR3, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Event request for Lines in range 0 to 31
+  * @rmtoll EMR1         EMx           LL_EXTI_DisableEvent_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->EMR1, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Event request for Lines in range 32 to 63
+  * @rmtoll EMR2         EMx           LL_EXTI_DisableEvent_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44
+  *         @arg @ref LL_EXTI_LINE_46
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_59
+  *         @arg @ref LL_EXTI_LINE_60
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->EMR2, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Event request for Lines in range 64 to 95
+  * @rmtoll EMR3         EMx           LL_EXTI_DisableEvent_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_67
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_75
+  *         @arg @ref LL_EXTI_LINE_76
+  *         @arg @ref LL_EXTI_LINE_77
+  *         @arg @ref LL_EXTI_LINE_78
+  *         @arg @ref LL_EXTI_LINE_79
+  *         @arg @ref LL_EXTI_LINE_80
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  *         @arg @ref LL_EXTI_LINE_87
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableEvent_64_95(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->EMR3, ExtiLine);
+}
+
+/**
+  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
+  * @rmtoll EMR1         EMx           LL_EXTI_IsEnabledEvent_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->EMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63
+  * @rmtoll EMR2         EMx           LL_EXTI_IsEnabledEvent_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44
+  *         @arg @ref LL_EXTI_LINE_46
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_59
+  *         @arg @ref LL_EXTI_LINE_60
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->EMR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 64 to 95
+  * @rmtoll EMR3         EMx           LL_EXTI_IsEnabledEvent_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_67
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_75
+  *         @arg @ref LL_EXTI_LINE_76
+  *         @arg @ref LL_EXTI_LINE_77
+  *         @arg @ref LL_EXTI_LINE_78
+  *         @arg @ref LL_EXTI_LINE_79
+  *         @arg @ref LL_EXTI_LINE_80
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  *         @arg @ref LL_EXTI_LINE_87
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_64_95(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->EMR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+#if defined(DUAL_CORE)
+
+/**
+  * @brief  Enable ExtiLine Event request for Lines in range 0 to 31 for cpu2
+  * @rmtoll C2EMR1         EMx           LL_C2_EXTI_EnableEvent_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->C2EMR1, ExtiLine);
+}
+
+
+/**
+  * @brief  Enable ExtiLine Event request for Lines in range 32 to 63 for cpu2
+  * @rmtoll C2EMR2         EMx           LL_C2_EXTI_EnableEvent_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44
+  *         @arg @ref LL_EXTI_LINE_46
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_59
+  *         @arg @ref LL_EXTI_LINE_60
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_EXTI_EnableEvent_32_63(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->C2EMR2, ExtiLine);
+}
+
+/**
+  * @brief  Enable ExtiLine Event request for Lines in range 64 to 95 for cpu2
+  * @rmtoll C2EMR3         EMx           LL_C2_EXTI_EnableEvent_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_67
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_75
+  *         @arg @ref LL_EXTI_LINE_76
+  *         @arg @ref LL_EXTI_LINE_77
+  *         @arg @ref LL_EXTI_LINE_78
+  *         @arg @ref LL_EXTI_LINE_79
+  *         @arg @ref LL_EXTI_LINE_80
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  *         @arg @ref LL_EXTI_LINE_87
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_EXTI_EnableEvent_64_95(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->C2EMR3, ExtiLine);
+}
+
+
+/**
+  * @brief  Disable ExtiLine Event request for Lines in range 0 to 31 for cpu2
+  * @rmtoll C2EMR1         EMx           LL_C2_EXTI_DisableEvent_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->C2EMR1, ExtiLine);
+}
+
+
+/**
+  * @brief  Disable ExtiLine Event request for Lines in range 32 to 63 for cpu2
+  * @rmtoll C2EMR2         EMx           LL_C2_EXTI_DisableEvent_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44
+  *         @arg @ref LL_EXTI_LINE_46
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_59
+  *         @arg @ref LL_EXTI_LINE_60
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_EXTI_DisableEvent_32_63(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->C2EMR2, ExtiLine);
+}
+
+
+/**
+  * @brief  Disable ExtiLine Event request for Lines in range 64 to 95 for cpu2
+  * @rmtoll C2EMR3         EMx           LL_C2_EXTI_DisableEvent_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_67
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_75
+  *         @arg @ref LL_EXTI_LINE_76
+  *         @arg @ref LL_EXTI_LINE_77
+  *         @arg @ref LL_EXTI_LINE_78
+  *         @arg @ref LL_EXTI_LINE_79
+  *         @arg @ref LL_EXTI_LINE_80
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  *         @arg @ref LL_EXTI_LINE_87
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_EXTI_DisableEvent_64_95(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->C2EMR3, ExtiLine);
+}
+
+
+/**
+  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 for cpu2
+  * @rmtoll C2EMR1         EMx           LL_C2_EXTI_IsEnabledEvent_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23
+  *         @arg @ref LL_EXTI_LINE_24
+  *         @arg @ref LL_EXTI_LINE_25
+  *         @arg @ref LL_EXTI_LINE_26
+  *         @arg @ref LL_EXTI_LINE_27
+  *         @arg @ref LL_EXTI_LINE_28
+  *         @arg @ref LL_EXTI_LINE_29
+  *         @arg @ref LL_EXTI_LINE_30
+  *         @arg @ref LL_EXTI_LINE_31
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->C2EMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+
+/**
+  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63 for cpu2
+  * @rmtoll C2EMR2         EMx           LL_C2_EXTI_IsEnabledEvent_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_32
+  *         @arg @ref LL_EXTI_LINE_33
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_36
+  *         @arg @ref LL_EXTI_LINE_37
+  *         @arg @ref LL_EXTI_LINE_38
+  *         @arg @ref LL_EXTI_LINE_39
+  *         @arg @ref LL_EXTI_LINE_40
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_42
+  *         @arg @ref LL_EXTI_LINE_43
+  *         @arg @ref LL_EXTI_LINE_44
+  *         @arg @ref LL_EXTI_LINE_46
+  *         @arg @ref LL_EXTI_LINE_47
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  *         @arg @ref LL_EXTI_LINE_54
+  *         @arg @ref LL_EXTI_LINE_55
+  *         @arg @ref LL_EXTI_LINE_56
+  *         @arg @ref LL_EXTI_LINE_57
+  *         @arg @ref LL_EXTI_LINE_58
+  *         @arg @ref LL_EXTI_LINE_59
+  *         @arg @ref LL_EXTI_LINE_60
+  *         @arg @ref LL_EXTI_LINE_61
+  *         @arg @ref LL_EXTI_LINE_62
+  *         @arg @ref LL_EXTI_LINE_63
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->C2EMR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+
+/**
+  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 64 to 95 for cpu2
+  * @rmtoll C2EMR3         EMx           LL_C2_EXTI_IsEnabledEvent_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_64
+  *         @arg @ref LL_EXTI_LINE_65
+  *         @arg @ref LL_EXTI_LINE_66
+  *         @arg @ref LL_EXTI_LINE_67
+  *         @arg @ref LL_EXTI_LINE_68
+  *         @arg @ref LL_EXTI_LINE_69
+  *         @arg @ref LL_EXTI_LINE_70
+  *         @arg @ref LL_EXTI_LINE_71
+  *         @arg @ref LL_EXTI_LINE_72
+  *         @arg @ref LL_EXTI_LINE_73
+  *         @arg @ref LL_EXTI_LINE_74
+  *         @arg @ref LL_EXTI_LINE_75
+  *         @arg @ref LL_EXTI_LINE_76
+  *         @arg @ref LL_EXTI_LINE_77
+  *         @arg @ref LL_EXTI_LINE_78
+  *         @arg @ref LL_EXTI_LINE_79
+  *         @arg @ref LL_EXTI_LINE_80
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  *         @arg @ref LL_EXTI_LINE_87
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledEvent_64_95(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->C2EMR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+
+#endif /* DUAL_CORE */
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a rising edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_RTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll RTSR1        RTx           LL_EXTI_EnableRisingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->RTSR1, ExtiLine);
+
+}
+
+/**
+  * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a rising edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_RTSR register, the
+  *       pending bit is not set.Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll RTSR2        RTx           LL_EXTI_EnableRisingTrig_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_51
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->RTSR2, ExtiLine);
+}
+
+/**
+  * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 64 to 95
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a rising edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_RTSR register, the
+  *       pending bit is not set.Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll RTSR3        RTx           LL_EXTI_EnableRisingTrig_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableRisingTrig_64_95(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->RTSR3, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a rising edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_RTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll RTSR1        RTx           LL_EXTI_DisableRisingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->RTSR1, ExtiLine);
+
+}
+
+/**
+  * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a rising edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_RTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll RTSR2        RTx           LL_EXTI_DisableRisingTrig_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_51
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->RTSR2, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 64 to 95
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a rising edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_RTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll RTSR3        RTx           LL_EXTI_DisableRisingTrig_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableRisingTrig_64_95(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->RTSR3, ExtiLine);
+}
+
+/**
+  * @brief  Check if rising edge trigger is enabled for Lines in range 0 to 31
+  * @rmtoll RTSR1        RTx           LL_EXTI_IsEnabledRisingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->RTSR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+
+/**
+  * @brief  Check if rising edge trigger is enabled for Lines in range 32 to 63
+  * @rmtoll RTSR2        RTx           LL_EXTI_IsEnabledRisingTrig_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_51
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->RTSR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Check if rising edge trigger is enabled for Lines in range 64 to 95
+  * @rmtoll RTSR3        RTx           LL_EXTI_IsEnabledRisingTrig_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_64_95(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->RTSR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a falling edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_FTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll FTSR1        FTx           LL_EXTI_EnableFallingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->FTSR1, ExtiLine);
+}
+
+/**
+  * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a Falling edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_FTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll FTSR2        FTx           LL_EXTI_EnableFallingTrig_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_51
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->FTSR2, ExtiLine);
+}
+
+/**
+  * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 64 to 95
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a Falling edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_FTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll FTSR3        FTx           LL_EXTI_EnableFallingTrig_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableFallingTrig_64_95(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->FTSR3, ExtiLine);
+}
+
+
+/**
+  * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a Falling edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_FTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for the same interrupt line.
+  *       In this case, both generate a trigger condition.
+  * @rmtoll FTSR1        FTx           LL_EXTI_DisableFallingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->FTSR1, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a Falling edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_FTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for the same interrupt line.
+  *       In this case, both generate a trigger condition.
+  * @rmtoll FTSR2        FTx           LL_EXTI_DisableFallingTrig_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_51
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->FTSR2, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 64 to 95
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a Falling edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_FTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for the same interrupt line.
+  *       In this case, both generate a trigger condition.
+  * @rmtoll FTSR3        FTx           LL_EXTI_DisableFallingTrig_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableFallingTrig_64_95(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->FTSR3, ExtiLine);
+}
+
+
+/**
+  * @brief  Check if falling edge trigger is enabled for Lines in range 0 to 31
+  * @rmtoll FTSR1        FTx           LL_EXTI_IsEnabledFallingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->FTSR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Check if falling edge trigger is enabled for Lines in range 32 to 63
+  * @rmtoll FTSR2        FTx           LL_EXTI_IsEnabledFallingTrig_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_51
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->FTSR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Check if falling edge trigger is enabled for Lines in range 64 to 95
+  * @rmtoll FTSR3        FTx           LL_EXTI_IsEnabledFallingTrig_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_64_95(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->FTSR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management
+  * @{
+  */
+
+/**
+  * @brief  Generate a software Interrupt Event for Lines in range 0 to 31
+  * @note If the interrupt is enabled on this line in the EXTI_C1IMR1, writing a 1 to
+  *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR1
+  *       resulting in an interrupt request generation.
+  *       This bit is cleared by clearing the corresponding bit in the EXTI_PR1
+  *       register (by writing a 1 into the bit)
+  * @rmtoll SWIER1       SWIx          LL_EXTI_GenerateSWI_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->SWIER1, ExtiLine);
+}
+
+/**
+  * @brief  Generate a software Interrupt Event for Lines in range 32 to 63
+  * @note If the interrupt is enabled on this line in the EXTI_IMR2, writing a 1 to
+  *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2
+  *       resulting in an interrupt request generation.
+  *       This bit is cleared by clearing the corresponding bit in the EXTI_PR2
+  *       register (by writing a 1 into the bit)
+  * @rmtoll SWIER2       SWIx          LL_EXTI_GenerateSWI_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_51
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->SWIER2, ExtiLine);
+}
+
+/**
+  * @brief  Generate a software Interrupt Event for Lines in range 64 to 95
+  * @note If the interrupt is enabled on this line in the EXTI_IMR2, writing a 1 to
+  *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2
+  *       resulting in an interrupt request generation.
+  *       This bit is cleared by clearing the corresponding bit in the EXTI_PR3
+  *       register (by writing a 1 into the bit)
+  * @rmtoll SWIER3       SWIx          LL_EXTI_GenerateSWI_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_GenerateSWI_64_95(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->SWIER3, ExtiLine);
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
+  * @{
+  */
+
+/**
+  * @brief  Check if the ExtLine Flag is set or not for Lines in range 0 to 31
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR1          PIFx           LL_EXTI_IsActiveFlag_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->PR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Check if the ExtLine Flag is set or not for  Lines in range 32 to 63
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR2          PIFx           LL_EXTI_IsActiveFlag_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->PR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Check if the ExtLine Flag is set or not for  Lines in range 64 to 95
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR3          PIFx           LL_EXTI_IsActiveFlag_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_64_95(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->PR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+
+/**
+  * @brief  Read ExtLine Combination Flag for Lines in range 0 to 31
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR1          PIFx           LL_EXTI_ReadFlag_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @retval @note This bit is set when the selected edge event arrives on the interrupt
+  */
+__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
+{
+  return (uint32_t)(READ_BIT(EXTI->PR1, ExtiLine));
+}
+
+
+/**
+  * @brief  Read ExtLine Combination Flag for  Lines in range 32 to 63
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR2          PIFx           LL_EXTI_ReadFlag_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_51
+  * @retval @note This bit is set when the selected edge event arrives on the interrupt
+  */
+__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_32_63(uint32_t ExtiLine)
+{
+  return (uint32_t)(READ_BIT(EXTI->PR2, ExtiLine));
+}
+
+
+/**
+  * @brief  Read ExtLine Combination Flag for  Lines in range 64 to 95
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR3          PIFx           LL_EXTI_ReadFlag_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  * @retval @note This bit is set when the selected edge event arrives on the interrupt
+  */
+__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_64_95(uint32_t ExtiLine)
+{
+  return (uint32_t)(READ_BIT(EXTI->PR3, ExtiLine));
+}
+
+/**
+  * @brief  Clear ExtLine Flags for Lines in range 0 to 31
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR1          PIFx           LL_EXTI_ClearFlag_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
+{
+  WRITE_REG(EXTI->PR1, ExtiLine);
+}
+
+/**
+  * @brief  Clear ExtLine Flags for Lines in range 32 to 63
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR2          PIFx           LL_EXTI_ClearFlag_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_51
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_ClearFlag_32_63(uint32_t ExtiLine)
+{
+  WRITE_REG(EXTI->PR2, ExtiLine);
+}
+
+/**
+  * @brief  Clear ExtLine Flags for Lines in range 64 to 95
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR3          PIFx           LL_EXTI_ClearFlag_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_ClearFlag_64_95(uint32_t ExtiLine)
+{
+  WRITE_REG(EXTI->PR3, ExtiLine);
+}
+
+#if defined(DUAL_CORE)
+
+/**
+  * @brief  Check if the ExtLine Flag is set or not for Lines in range 0 to 31 for cpu2
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll C2PR1          PIFx           LL_C2_EXTI_IsActiveFlag_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->C2PR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Check if the ExtLine Flag is set or not for  Lines in range 32 to 63 for cpu2
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll C2PR2          PIFx           LL_C2_EXTI_IsActiveFlag_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_ALL_32_63
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->C2PR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Check if the ExtLine Flag is set or not for  Lines in range 64 to 95 for cpu2
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll C2PR3          PIFx           LL_C2_EXTI_IsActiveFlag_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  *         @arg @ref LL_EXTI_LINE_ALL_64_95
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_EXTI_IsActiveFlag_64_95(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->C2PR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Read ExtLine Combination Flag for Lines in range 0 to 31 for cpu2
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll C2PR1          PIFx           LL_C2_EXTI_ReadFlag_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @retval @note This bit is set when the selected edge event arrives on the interrupt
+  */
+__STATIC_INLINE uint32_t LL_C2_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
+{
+  return (uint32_t)(READ_BIT(EXTI->C2PR1, ExtiLine));
+}
+
+/**
+  * @brief  Read ExtLine Combination Flag for  Lines in range 32 to 63 for cpu2
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll C2PR2          PIFx           LL_C2_EXTI_ReadFlag_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_51
+  * @retval @note This bit is set when the selected edge event arrives on the interrupt
+  */
+__STATIC_INLINE uint32_t LL_C2_EXTI_ReadFlag_32_63(uint32_t ExtiLine)
+{
+  return (uint32_t)(READ_BIT(EXTI->C2PR2, ExtiLine));
+}
+
+
+/**
+  * @brief  Read ExtLine Combination Flag for  Lines in range 64 to 95 for cpu2
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll C2PR3          PIFx           LL_C2_EXTI_ReadFlag_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  * @retval @note This bit is set when the selected edge event arrives on the interrupt
+  */
+__STATIC_INLINE uint32_t LL_C2_EXTI_ReadFlag_64_95(uint32_t ExtiLine)
+{
+  return (uint32_t)(READ_BIT(EXTI->C2PR3, ExtiLine));
+}
+/**
+  * @brief  Clear ExtLine Flags for Lines in range 0 to 31 for cpu2
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll C2PR1          PIFx           LL_C2_EXTI_ClearFlag_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
+{
+  WRITE_REG(EXTI->C2PR1, ExtiLine);
+}
+
+/**
+  * @brief  Clear ExtLine Flags for Lines in range 32 to 63 for cpu2
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll C2PR2          PIFx           LL_C2_EXTI_ClearFlag_32_63
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_51
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_EXTI_ClearFlag_32_63(uint32_t ExtiLine)
+{
+  WRITE_REG(EXTI->C2PR2, ExtiLine);
+}
+
+/**
+  * @brief  Clear ExtLine Flags for Lines in range 64 to 95 for cpu2
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll C2PR3          PIFx           LL_C2_EXTI_ClearFlag_64_95
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_82
+  *         @arg @ref LL_EXTI_LINE_84
+  *         @arg @ref LL_EXTI_LINE_85
+  *         @arg @ref LL_EXTI_LINE_86
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_EXTI_ClearFlag_64_95(uint32_t ExtiLine)
+{
+  WRITE_REG(EXTI->C2PR3, ExtiLine);
+}
+
+#endif /* DUAL_CORE */
+
+/**
+  * @brief  Enable ExtiLine D3 Pending Mask for Lines in range 0 to 31
+  * @rmtoll D3PMR1         MRx           LL_D3_EXTI_EnablePendMask_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_25
+  * @retval None
+  */
+__STATIC_INLINE void LL_D3_EXTI_EnablePendMask_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->D3PMR1, ExtiLine);
+}
+
+/**
+  * @brief  Enable ExtiLine D3 Pending Mask for Lines in range 32 to 63
+  * @rmtoll D3PMR2         MRx           LL_D3_EXTI_EnablePendMask_32_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  * @retval None
+  */
+__STATIC_INLINE void LL_D3_EXTI_EnablePendMask_32_63(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->D3PMR2, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine D3 Pending Mask for Lines in range 0 to 31
+  * @rmtoll D3PMR1         MRx           LL_D3_EXTI_DisablePendMask_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_25
+  * @retval None
+  */
+__STATIC_INLINE void LL_D3_EXTI_DisablePendMask_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->D3PMR1, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine D3 Pending Mask for Lines in range 32 to 63
+  * @rmtoll D3PMR2         MRx           LL_D3_EXTI_DisablePendMask_32_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  * @retval None
+  */
+__STATIC_INLINE void LL_D3_EXTI_DisablePendMask_32_63(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->D3PMR2, ExtiLine);
+}
+
+/**
+  * @brief  Indicate if ExtiLine D3 Pending Mask is enabled for Lines in range 0 to 31
+  * @rmtoll D3PMR1         MRx           LL_D3_EXTI_IsEnabledPendMask_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_25
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_D3_EXTI_IsEnabledPendMask_0_31(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->D3PMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Indicate if ExtiLine D3 Pending Mask is enabled for Lines in range 32 to 63
+  * @rmtoll D3PMR2         MRx           LL_D3_EXTI_IsEnabledPendMask_32_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_41
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_D3_EXTI_IsEnabledPendMask_32_63(uint32_t ExtiLine)
+{
+  return ((READ_BIT(EXTI->D3PMR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 0 to 15
+  * @rmtoll D3PCR1L          PCSx           LL_D3_EXTI_SetPendClearSel_0_15
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  * @param  ClrSrc This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5
+  * @retval None
+  */
+__STATIC_INLINE void LL_D3_EXTI_SetPendClearSel_0_15(uint32_t ExtiLine, uint32_t ClrSrc)
+{
+  MODIFY_REG(EXTI->D3PCR1L, ((ExtiLine * ExtiLine) * 3UL), ((ExtiLine * ExtiLine) * ClrSrc));
+}
+
+/**
+  * @brief  Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 16 to 31
+  * @rmtoll D3PCR1H          PCSx           LL_D3_EXTI_SetPendClearSel_16_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_25
+  * @param  ClrSrc This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5
+  * @retval None
+  */
+__STATIC_INLINE void LL_D3_EXTI_SetPendClearSel_16_31(uint32_t ExtiLine, uint32_t ClrSrc)
+{
+  MODIFY_REG(EXTI->D3PCR1H, (((ExtiLine >> EXTI_IMR1_IM16_Pos) * (ExtiLine >> EXTI_IMR1_IM16_Pos)) * 3UL), (((ExtiLine >> EXTI_IMR1_IM16_Pos) * (ExtiLine >> EXTI_IMR1_IM16_Pos)) * ClrSrc));
+}
+
+
+/**
+  * @brief  Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 32 to 47
+  * @rmtoll D3PCR2L          PCSx           LL_D3_EXTI_SetPendClearSel_32_47
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_41
+  * @param  ClrSrc This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5
+  * @retval None
+  */
+__STATIC_INLINE void LL_D3_EXTI_SetPendClearSel_32_47(uint32_t ExtiLine, uint32_t ClrSrc)
+{
+  MODIFY_REG(EXTI->D3PCR2L, ((ExtiLine * ExtiLine) * 3UL), ((ExtiLine * ExtiLine) * ClrSrc));
+}
+
+/**
+  * @brief  Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 48 to 63
+  * @rmtoll D3PCR2H          PCSx           LL_D3_EXTI_SetPendClearSel_48_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  * @param  ClrSrc This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5
+  * @retval None
+  */
+__STATIC_INLINE void LL_D3_EXTI_SetPendClearSel_48_63(uint32_t ExtiLine, uint32_t ClrSrc)
+{
+  MODIFY_REG(EXTI->D3PCR2H, (((ExtiLine >> EXTI_IMR2_IM48_Pos) * (ExtiLine >> EXTI_IMR2_IM48_Pos)) * 3UL), (((ExtiLine >> EXTI_IMR2_IM48_Pos) * (ExtiLine >> EXTI_IMR2_IM48_Pos)) * ClrSrc));
+}
+
+/**
+  * @brief  Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 0 to 15
+  * @rmtoll D3PCR1L          PCSx           LL_D3_EXTI_GetPendClearSel_0_15
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5
+  */
+__STATIC_INLINE uint32_t LL_D3_EXTI_GetPendClearSel_0_15(uint32_t ExtiLine)
+{
+  return (uint32_t)(READ_BIT(EXTI->D3PCR1L, ((ExtiLine * ExtiLine) * 3UL)) / (ExtiLine * ExtiLine));
+}
+
+/**
+  * @brief  Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 16 to 31
+  * @rmtoll D3PCR1H          PCSx           LL_D3_EXTI_GetPendClearSel_16_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_19
+  *         @arg @ref LL_EXTI_LINE_20
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_25
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5
+  */
+__STATIC_INLINE uint32_t LL_D3_EXTI_GetPendClearSel_16_31(uint32_t ExtiLine)
+{
+  return (uint32_t)(READ_BIT(EXTI->D3PCR1H, (((ExtiLine >> EXTI_IMR1_IM16_Pos) * (ExtiLine >> EXTI_IMR1_IM16_Pos)) * 3UL)) / ((ExtiLine >> EXTI_IMR1_IM16_Pos) * (ExtiLine >> EXTI_IMR1_IM16_Pos)));
+}
+
+/**
+  * @brief  Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 32 to 47
+  * @rmtoll D3PCR2L          PCSx           LL_D3_EXTI_GetPendClearSel_32_47
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_34
+  *         @arg @ref LL_EXTI_LINE_35
+  *         @arg @ref LL_EXTI_LINE_41
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5
+  */
+__STATIC_INLINE uint32_t LL_D3_EXTI_GetPendClearSel_32_47(uint32_t ExtiLine)
+{
+  return (uint32_t)(READ_BIT(EXTI->D3PCR2L, ((ExtiLine * ExtiLine) * 3UL)) / (ExtiLine * ExtiLine));
+}
+
+/**
+  * @brief  Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 48 to 63
+  * @rmtoll D3PCR2H          PCSx           LL_D3_EXTI_GetPendClearSel_48_63
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_48
+  *         @arg @ref LL_EXTI_LINE_49
+  *         @arg @ref LL_EXTI_LINE_50
+  *         @arg @ref LL_EXTI_LINE_51
+  *         @arg @ref LL_EXTI_LINE_52
+  *         @arg @ref LL_EXTI_LINE_53
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4
+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5
+  */
+__STATIC_INLINE uint32_t LL_D3_EXTI_GetPendClearSel_48_63(uint32_t ExtiLine)
+{
+  return (uint32_t)(READ_BIT(EXTI->D3PCR2H, (((ExtiLine >> EXTI_IMR2_IM48_Pos) * (ExtiLine >> EXTI_IMR2_IM48_Pos)) * 3UL)) / ((ExtiLine >> EXTI_IMR2_IM48_Pos) * (ExtiLine >> EXTI_IMR2_IM48_Pos)));
+}
+
+
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
+  * @{,
+  */
+
+ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
+ErrorStatus LL_EXTI_DeInit(void);
+void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
+
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* EXTI */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32H7xx_LL_EXTI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_gpio.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_gpio.h
new file mode 100644
index 00000000..a375a124
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_gpio.h
@@ -0,0 +1,985 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_gpio.h
+  * @author  MCD Application Team
+  * @brief   Header file of GPIO LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_LL_GPIO_H
+#define STM32H7xx_LL_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK)
+
+/** @defgroup GPIO_LL GPIO
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
+  * @{
+  */
+
+/**
+  * @brief LL GPIO Init Structure definition
+  */
+typedef struct
+{
+  uint32_t Pin;          /*!< Specifies the GPIO pins to be configured.
+                              This parameter can be any value of @ref GPIO_LL_EC_PIN */
+
+  uint32_t Mode;         /*!< Specifies the operating mode for the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_MODE.
+
+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/
+
+  uint32_t Speed;        /*!< Specifies the speed for the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_SPEED.
+
+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/
+
+  uint32_t OutputType;   /*!< Specifies the operating output type for the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
+
+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/
+
+  uint32_t Pull;         /*!< Specifies the operating Pull-up/Pull down for the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_PULL.
+
+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/
+
+  uint32_t Alternate;    /*!< Specifies the Peripheral to be connected to the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_AF.
+
+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/
+} LL_GPIO_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
+  * @{
+  */
+
+/** @defgroup GPIO_LL_EC_PIN PIN
+  * @{
+  */
+#define LL_GPIO_PIN_0                      GPIO_BSRR_BS0 /*!< Select pin 0 */
+#define LL_GPIO_PIN_1                      GPIO_BSRR_BS1 /*!< Select pin 1 */
+#define LL_GPIO_PIN_2                      GPIO_BSRR_BS2 /*!< Select pin 2 */
+#define LL_GPIO_PIN_3                      GPIO_BSRR_BS3 /*!< Select pin 3 */
+#define LL_GPIO_PIN_4                      GPIO_BSRR_BS4 /*!< Select pin 4 */
+#define LL_GPIO_PIN_5                      GPIO_BSRR_BS5 /*!< Select pin 5 */
+#define LL_GPIO_PIN_6                      GPIO_BSRR_BS6 /*!< Select pin 6 */
+#define LL_GPIO_PIN_7                      GPIO_BSRR_BS7 /*!< Select pin 7 */
+#define LL_GPIO_PIN_8                      GPIO_BSRR_BS8 /*!< Select pin 8 */
+#define LL_GPIO_PIN_9                      GPIO_BSRR_BS9 /*!< Select pin 9 */
+#define LL_GPIO_PIN_10                     GPIO_BSRR_BS10 /*!< Select pin 10 */
+#define LL_GPIO_PIN_11                     GPIO_BSRR_BS11 /*!< Select pin 11 */
+#define LL_GPIO_PIN_12                     GPIO_BSRR_BS12 /*!< Select pin 12 */
+#define LL_GPIO_PIN_13                     GPIO_BSRR_BS13 /*!< Select pin 13 */
+#define LL_GPIO_PIN_14                     GPIO_BSRR_BS14 /*!< Select pin 14 */
+#define LL_GPIO_PIN_15                     GPIO_BSRR_BS15 /*!< Select pin 15 */
+#define LL_GPIO_PIN_ALL                    (GPIO_BSRR_BS0 | GPIO_BSRR_BS1  | GPIO_BSRR_BS2  | \
+                                           GPIO_BSRR_BS3  | GPIO_BSRR_BS4  | GPIO_BSRR_BS5  | \
+                                           GPIO_BSRR_BS6  | GPIO_BSRR_BS7  | GPIO_BSRR_BS8  | \
+                                           GPIO_BSRR_BS9  | GPIO_BSRR_BS10 | GPIO_BSRR_BS11 | \
+                                           GPIO_BSRR_BS12 | GPIO_BSRR_BS13 | GPIO_BSRR_BS14 | \
+                                           GPIO_BSRR_BS15) /*!< Select all pins */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EC_MODE Mode
+  * @{
+  */
+#define LL_GPIO_MODE_INPUT                 (0x00000000U) /*!< Select input mode */
+#define LL_GPIO_MODE_OUTPUT                GPIO_MODER_MODE0_0  /*!< Select output mode */
+#define LL_GPIO_MODE_ALTERNATE             GPIO_MODER_MODE0_1  /*!< Select alternate function mode */
+#define LL_GPIO_MODE_ANALOG                GPIO_MODER_MODE0    /*!< Select analog mode */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EC_OUTPUT Output Type
+  * @{
+  */
+#define LL_GPIO_OUTPUT_PUSHPULL            (0x00000000U) /*!< Select push-pull as output type */
+#define LL_GPIO_OUTPUT_OPENDRAIN           GPIO_OTYPER_OT0 /*!< Select open-drain as output type */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EC_SPEED Output Speed
+  * @{
+  */
+#define LL_GPIO_SPEED_FREQ_LOW             (0x00000000U) /*!< Select I/O low output speed    */
+#define LL_GPIO_SPEED_FREQ_MEDIUM          GPIO_OSPEEDR_OSPEED0_0 /*!< Select I/O medium output speed */
+#define LL_GPIO_SPEED_FREQ_HIGH            GPIO_OSPEEDR_OSPEED0_1 /*!< Select I/O fast output speed   */
+#define LL_GPIO_SPEED_FREQ_VERY_HIGH       GPIO_OSPEEDR_OSPEED0   /*!< Select I/O high output speed   */
+/**
+  * @}
+  */
+#define LL_GPIO_SPEED_LOW                  LL_GPIO_SPEED_FREQ_LOW
+#define LL_GPIO_SPEED_MEDIUM               LL_GPIO_SPEED_FREQ_MEDIUM
+#define LL_GPIO_SPEED_FAST                 LL_GPIO_SPEED_FREQ_HIGH
+#define LL_GPIO_SPEED_HIGH                 LL_GPIO_SPEED_FREQ_VERY_HIGH
+
+
+/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
+  * @{
+  */
+#define LL_GPIO_PULL_NO                    (0x00000000U) /*!< Select I/O no pull */
+#define LL_GPIO_PULL_UP                    GPIO_PUPDR_PUPD0_0 /*!< Select I/O pull up */
+#define LL_GPIO_PULL_DOWN                  GPIO_PUPDR_PUPD0_1 /*!< Select I/O pull down */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EC_AF Alternate Function
+  * @{
+  */
+#define LL_GPIO_AF_0                       (0x0000000U) /*!< Select alternate function 0 */
+#define LL_GPIO_AF_1                       (0x0000001U) /*!< Select alternate function 1 */
+#define LL_GPIO_AF_2                       (0x0000002U) /*!< Select alternate function 2 */
+#define LL_GPIO_AF_3                       (0x0000003U) /*!< Select alternate function 3 */
+#define LL_GPIO_AF_4                       (0x0000004U) /*!< Select alternate function 4 */
+#define LL_GPIO_AF_5                       (0x0000005U) /*!< Select alternate function 5 */
+#define LL_GPIO_AF_6                       (0x0000006U) /*!< Select alternate function 6 */
+#define LL_GPIO_AF_7                       (0x0000007U) /*!< Select alternate function 7 */
+#define LL_GPIO_AF_8                       (0x0000008U) /*!< Select alternate function 8 */
+#define LL_GPIO_AF_9                       (0x0000009U) /*!< Select alternate function 9 */
+#define LL_GPIO_AF_10                      (0x000000AU) /*!< Select alternate function 10 */
+#define LL_GPIO_AF_11                      (0x000000BU) /*!< Select alternate function 11 */
+#define LL_GPIO_AF_12                      (0x000000CU) /*!< Select alternate function 12 */
+#define LL_GPIO_AF_13                      (0x000000DU) /*!< Select alternate function 13 */
+#define LL_GPIO_AF_14                      (0x000000EU) /*!< Select alternate function 14 */
+#define LL_GPIO_AF_15                      (0x000000FU) /*!< Select alternate function 15 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
+  * @{
+  */
+
+/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in GPIO register
+  * @param  __INSTANCE__ GPIO Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in GPIO register
+  * @param  __INSTANCE__ GPIO Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
+  * @{
+  */
+
+/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
+  * @{
+  */
+
+/**
+  * @brief  Configure gpio mode for a dedicated pin on dedicated port.
+  * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll MODER        MODEy         LL_GPIO_SetPinMode
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_MODE_INPUT
+  *         @arg @ref LL_GPIO_MODE_OUTPUT
+  *         @arg @ref LL_GPIO_MODE_ALTERNATE
+  *         @arg @ref LL_GPIO_MODE_ANALOG
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
+{
+  MODIFY_REG(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0), ((Pin * Pin) * Mode));
+}
+
+/**
+  * @brief  Return gpio mode for a dedicated pin on dedicated port.
+  * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll MODER        MODEy         LL_GPIO_GetPinMode
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_MODE_INPUT
+  *         @arg @ref LL_GPIO_MODE_OUTPUT
+  *         @arg @ref LL_GPIO_MODE_ALTERNATE
+  *         @arg @ref LL_GPIO_MODE_ANALOG
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0)) / (Pin * Pin));
+}
+
+/**
+  * @brief  Configure gpio output type for several pins on dedicated port.
+  * @note   Output type as to be set when gpio pin is in output or
+  *         alternate modes. Possible type are Push-pull or Open-drain.
+  * @rmtoll OTYPER       OTy           LL_GPIO_SetPinOutputType
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @param  OutputType This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
+  *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
+{
+  MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
+}
+
+/**
+  * @brief  Return gpio output type for several pins on dedicated port.
+  * @note   Output type as to be set when gpio pin is in output or
+  *         alternate modes. Possible type are Push-pull or Open-drain.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll OTYPER       OTy           LL_GPIO_GetPinOutputType
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
+  *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) / Pin);
+}
+
+/**
+  * @brief  Configure gpio speed for a dedicated pin on dedicated port.
+  * @note   I/O speed can be Low, Medium, Fast or High speed.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @note   Refer to datasheet for frequency specifications and the power
+  *         supply and load conditions for each speed.
+  * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_SetPinSpeed
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @param  Speed This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
+  *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
+  *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
+  *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t  Speed)
+{
+  MODIFY_REG(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEED0), ((Pin * Pin) * Speed));
+}
+
+/**
+  * @brief  Return gpio speed for a dedicated pin on dedicated port.
+  * @note   I/O speed can be Low, Medium, Fast or High speed.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @note   Refer to datasheet for frequency specifications and the power
+  *         supply and load conditions for each speed.
+  * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_GetPinSpeed
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
+  *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
+  *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
+  *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEED0)) / (Pin * Pin));
+}
+
+/**
+  * @brief  Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll PUPDR        PUPDy         LL_GPIO_SetPinPull
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @param  Pull This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PULL_NO
+  *         @arg @ref LL_GPIO_PULL_UP
+  *         @arg @ref LL_GPIO_PULL_DOWN
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
+{
+  MODIFY_REG(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0), ((Pin * Pin) * Pull));
+}
+
+/**
+  * @brief  Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll PUPDR        PUPDy         LL_GPIO_GetPinPull
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_PULL_NO
+  *         @arg @ref LL_GPIO_PULL_UP
+  *         @arg @ref LL_GPIO_PULL_DOWN
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0)) / (Pin * Pin));
+}
+
+/**
+  * @brief  Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
+  * @note   Possible values are from AF0 to AF15 depending on target.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll AFRL         AFSELy        LL_GPIO_SetAFPin_0_7
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  * @param  Alternate This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_AF_0
+  *         @arg @ref LL_GPIO_AF_1
+  *         @arg @ref LL_GPIO_AF_2
+  *         @arg @ref LL_GPIO_AF_3
+  *         @arg @ref LL_GPIO_AF_4
+  *         @arg @ref LL_GPIO_AF_5
+  *         @arg @ref LL_GPIO_AF_6
+  *         @arg @ref LL_GPIO_AF_7
+  *         @arg @ref LL_GPIO_AF_8
+  *         @arg @ref LL_GPIO_AF_9
+  *         @arg @ref LL_GPIO_AF_10
+  *         @arg @ref LL_GPIO_AF_11
+  *         @arg @ref LL_GPIO_AF_12
+  *         @arg @ref LL_GPIO_AF_13
+  *         @arg @ref LL_GPIO_AF_14
+  *         @arg @ref LL_GPIO_AF_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
+{
+  MODIFY_REG(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0),
+             ((((Pin * Pin) * Pin) * Pin) * Alternate));
+}
+
+/**
+  * @brief  Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
+  * @rmtoll AFRL         AFSELy        LL_GPIO_GetAFPin_0_7
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_AF_0
+  *         @arg @ref LL_GPIO_AF_1
+  *         @arg @ref LL_GPIO_AF_2
+  *         @arg @ref LL_GPIO_AF_3
+  *         @arg @ref LL_GPIO_AF_4
+  *         @arg @ref LL_GPIO_AF_5
+  *         @arg @ref LL_GPIO_AF_6
+  *         @arg @ref LL_GPIO_AF_7
+  *         @arg @ref LL_GPIO_AF_8
+  *         @arg @ref LL_GPIO_AF_9
+  *         @arg @ref LL_GPIO_AF_10
+  *         @arg @ref LL_GPIO_AF_11
+  *         @arg @ref LL_GPIO_AF_12
+  *         @arg @ref LL_GPIO_AF_13
+  *         @arg @ref LL_GPIO_AF_14
+  *         @arg @ref LL_GPIO_AF_15
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->AFR[0],
+                             ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0)) / (((Pin * Pin) * Pin) * Pin));
+}
+
+/**
+  * @brief  Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
+  * @note   Possible values are from AF0 to AF15 depending on target.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll AFRH         AFSELy        LL_GPIO_SetAFPin_8_15
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @param  Alternate This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_AF_0
+  *         @arg @ref LL_GPIO_AF_1
+  *         @arg @ref LL_GPIO_AF_2
+  *         @arg @ref LL_GPIO_AF_3
+  *         @arg @ref LL_GPIO_AF_4
+  *         @arg @ref LL_GPIO_AF_5
+  *         @arg @ref LL_GPIO_AF_6
+  *         @arg @ref LL_GPIO_AF_7
+  *         @arg @ref LL_GPIO_AF_8
+  *         @arg @ref LL_GPIO_AF_9
+  *         @arg @ref LL_GPIO_AF_10
+  *         @arg @ref LL_GPIO_AF_11
+  *         @arg @ref LL_GPIO_AF_12
+  *         @arg @ref LL_GPIO_AF_13
+  *         @arg @ref LL_GPIO_AF_14
+  *         @arg @ref LL_GPIO_AF_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
+{
+  MODIFY_REG(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8),
+             (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * Alternate));
+}
+
+/**
+  * @brief  Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
+  * @note   Possible values are from AF0 to AF15 depending on target.
+  * @rmtoll AFRH         AFSELy        LL_GPIO_GetAFPin_8_15
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_AF_0
+  *         @arg @ref LL_GPIO_AF_1
+  *         @arg @ref LL_GPIO_AF_2
+  *         @arg @ref LL_GPIO_AF_3
+  *         @arg @ref LL_GPIO_AF_4
+  *         @arg @ref LL_GPIO_AF_5
+  *         @arg @ref LL_GPIO_AF_6
+  *         @arg @ref LL_GPIO_AF_7
+  *         @arg @ref LL_GPIO_AF_8
+  *         @arg @ref LL_GPIO_AF_9
+  *         @arg @ref LL_GPIO_AF_10
+  *         @arg @ref LL_GPIO_AF_11
+  *         @arg @ref LL_GPIO_AF_12
+  *         @arg @ref LL_GPIO_AF_13
+  *         @arg @ref LL_GPIO_AF_14
+  *         @arg @ref LL_GPIO_AF_15
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->AFR[1],
+                             (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8)) / ((((Pin >> 8U) *
+                                 (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)));
+}
+
+
+/**
+  * @brief  Lock configuration of several pins for a dedicated port.
+  * @note   When the lock sequence has been applied on a port bit, the
+  *         value of this port bit can no longer be modified until the
+  *         next reset.
+  * @note   Each lock bit freezes a specific configuration register
+  *         (control and alternate function registers).
+  * @rmtoll LCKR         LCKK          LL_GPIO_LockPin
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  __IO uint32_t temp;
+  WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
+  WRITE_REG(GPIOx->LCKR, PinMask);
+  WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
+  /* Read LCKK register. This read is mandatory to complete key lock sequence */
+  temp = READ_REG(GPIOx->LCKR);
+  (void) temp;
+}
+
+/**
+  * @brief  Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
+  * @rmtoll LCKR         LCKy          LL_GPIO_IsPinLocked
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Return 1 if one of the pin of a dedicated port is locked. else return 0.
+  * @rmtoll LCKR         LCKK          LL_GPIO_IsAnyPinLocked
+  * @param  GPIOx GPIO Port
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
+{
+  return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EF_Data_Access Data Access
+  * @{
+  */
+
+/**
+  * @brief  Return full input data register value for a dedicated port.
+  * @rmtoll IDR          IDy           LL_GPIO_ReadInputPort
+  * @param  GPIOx GPIO Port
+  * @retval Input data register value of port
+  */
+__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
+{
+  return (uint32_t)(READ_REG(GPIOx->IDR));
+}
+
+/**
+  * @brief  Return if input data level for several pins of dedicated port is high or low.
+  * @rmtoll IDR          IDy           LL_GPIO_IsInputPinSet
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Write output data register for the port.
+  * @rmtoll ODR          ODy           LL_GPIO_WriteOutputPort
+  * @param  GPIOx GPIO Port
+  * @param  PortValue Level value for each pin of the port
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
+{
+  WRITE_REG(GPIOx->ODR, PortValue);
+}
+
+/**
+  * @brief  Return full output data register value for a dedicated port.
+  * @rmtoll ODR          ODy           LL_GPIO_ReadOutputPort
+  * @param  GPIOx GPIO Port
+  * @retval Output data register value of port
+  */
+__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
+{
+  return (uint32_t)(READ_REG(GPIOx->ODR));
+}
+
+/**
+  * @brief  Return if input data level for several pins of dedicated port is high or low.
+  * @rmtoll ODR          ODy           LL_GPIO_IsOutputPinSet
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set several pins to high level on dedicated gpio port.
+  * @rmtoll BSRR         BSy           LL_GPIO_SetOutputPin
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  WRITE_REG(GPIOx->BSRR, PinMask);
+}
+
+/**
+  * @brief  Set several pins to low level on dedicated gpio port.
+  * @rmtoll BSRR         BRy           LL_GPIO_ResetOutputPin
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  WRITE_REG(GPIOx->BSRR, PinMask << 16U);
+}
+
+/**
+  * @brief  Toggle data value for several pin of dedicated port.
+  * @rmtoll ODR          ODy           LL_GPIO_TogglePin
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ PinMask);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
+ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
+void        LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /*defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) */
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_LL_GPIO_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_pwr.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_pwr.h
new file mode 100644
index 00000000..19169584
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_pwr.h
@@ -0,0 +1,2249 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_pwr.h
+  * @author  MCD Application Team
+  * @brief   Header file of PWR LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_LL_PWR_H
+#define STM32H7xx_LL_PWR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined (PWR)
+
+/** @defgroup PWR_LL PWR
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup PWR_LL_Private_Constants PWR Private Constants
+  * @{
+  */
+
+/** @defgroup PWR_LL_WAKEUP_PIN_OFFSET Wake-Up Pins register offsets Defines
+  * @brief    Flags defines which can be used with LL_PWR_WriteReg function
+  * @{
+  */
+/* Wake-Up Pins PWR register offsets */
+#define LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET    2UL
+#define LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK       0x1FU
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+/* Private macros ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
+  * @{
+  */
+
+/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_PWR_WriteReg function
+  * @{
+  */
+#define LL_PWR_FLAG_CPU_CSSF          PWR_CPUCR_CSSF      /*!< Clear flags for CPU  */
+#if defined (DUAL_CORE)
+#define LL_PWR_FLAG_CPU2_CSSF         PWR_CPU2CR_CSSF     /*!< Clear flags for CPU2 */
+#endif /* DUAL_CORE */
+#define LL_PWR_FLAG_WKUPCR_WKUPC6     PWR_WKUPCR_WKUPC6   /*!< Clear PC1 WKUP flag  */
+#define LL_PWR_FLAG_WKUPCR_WKUPC5     PWR_WKUPCR_WKUPC5   /*!< Clear PI11 WKUP flag */
+#define LL_PWR_FLAG_WKUPCR_WKUPC4     PWR_WKUPCR_WKUPC4   /*!< Clear PC13 WKUP flag */
+#define LL_PWR_FLAG_WKUPCR_WKUPC3     PWR_WKUPCR_WKUPC3   /*!< Clear PI8 WKUP flag  */
+#define LL_PWR_FLAG_WKUPCR_WKUPC2     PWR_WKUPCR_WKUPC2   /*!< Clear PA2 WKUP flag  */
+#define LL_PWR_FLAG_WKUPCR_WKUPC1     PWR_WKUPCR_WKUPC1   /*!< Clear PA0 WKUP flag  */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_PWR_ReadReg function
+  * @{
+  */
+#define LL_PWR_FLAG_AVDO              PWR_CSR1_AVDO       /*!< Analog voltage detector output on VDDA flag                          */
+#define LL_PWR_FLAG_PVDO              PWR_CSR1_PVDO       /*!< Programmable voltage detect output flag                              */
+#define LL_PWR_FLAG_ACTVOS            PWR_CSR1_ACTVOS     /*!< Current VOS applied for VCORE voltage scaling flag                   */
+#define LL_PWR_FLAG_ACTVOSRDY         PWR_CSR1_ACTVOSRDY  /*!< Ready bit for current actual used VOS for VCORE voltage scaling flag */
+#if defined (PWR_CSR1_MMCVDO)
+#define LL_PWR_FLAG_MMCVDO            PWR_CSR1_MMCVDO     /*!< Voltage detector output on VDDMMC flag                               */
+#endif /* PWR_CSR1_MMCVDO */
+
+#define LL_PWR_FLAG_TEMPH             PWR_CR2_TEMPH       /*!< Temperature high threshold flag */
+#define LL_PWR_FLAG_TEMPL             PWR_CR2_TEMPL       /*!< Temperature low threshold flag  */
+#define LL_PWR_FLAG_VBATH             PWR_CR2_VBATH       /*!< VBAT high threshold flag        */
+#define LL_PWR_FLAG_VBATL             PWR_CR2_VBATL       /*!< VBAT low threshold flag         */
+#define LL_PWR_FLAG_BRRDY             PWR_CR2_BRRDY       /*!< Backup Regulator ready flag     */
+
+#define LL_PWR_FLAG_USBRDY            PWR_CR3_USB33RDY    /*!< USB supply ready flag           */
+#define LL_PWR_FLAG_SMPSEXTRDY        PWR_CR3_SMPSEXTRDY  /*!< SMPS External supply ready flag */
+
+#if defined (PWR_CPUCR_SBF_D2)
+#define LL_PWR_FLAG_CPU_SBF_D2        PWR_CPUCR_SBF_D2    /*!< D2 domain DSTANDBY Flag  */
+#endif /* PWR_CPUCR_SBF_D2 */
+#if defined (PWR_CPUCR_SBF_D1)
+#define LL_PWR_FLAG_CPU_SBF_D1        PWR_CPUCR_SBF_D1    /*!< D1 domain DSTANDBY Flag  */
+#endif /* PWR_CPUCR_SBF_D1 */
+#define LL_PWR_FLAG_CPU_SBF           PWR_CPUCR_SBF       /*!< System STANDBY Flag      */
+#define LL_PWR_FLAG_CPU_STOPF         PWR_CPUCR_STOPF     /*!< STOP Flag                */
+#if defined (DUAL_CORE)
+#define LL_PWR_FLAG_CPU_HOLD2F        PWR_CPUCR_HOLD2F    /*!< CPU2 in hold wakeup flag */
+#endif /* DUAL_CORE */
+
+#if defined (DUAL_CORE)
+#define LL_PWR_FLAG_CPU2_SBF_D2       PWR_CPU2CR_SBF_D2   /*!< D2 domain DSTANDBY Flag  */
+#define LL_PWR_FLAG_CPU2_SBF_D1       PWR_CPU2CR_SBF_D1   /*!< D1 domain DSTANDBY Flag  */
+#define LL_PWR_FLAG_CPU2_SBF          PWR_CPU2CR_SBF      /*!< System STANDBY Flag      */
+#define LL_PWR_FLAG_CPU2_STOPF        PWR_CPU2CR_STOPF    /*!< STOP Flag                */
+#define LL_PWR_FLAG_CPU2_HOLD1F       PWR_CPU2CR_HOLD1F   /*!< CPU1 in hold wakeup flag */
+#endif /* DUAL_CORE */
+
+#if defined (PWR_CPUCR_PDDS_D2)
+#define LL_PWR_D3CR_VOSRDY            PWR_D3CR_VOSRDY     /*!< Voltage scaling ready flag */
+#else
+#define LL_PWR_SRDCR_VOSRDY           PWR_SRDCR_VOSRDY    /*!< Voltage scaling ready flag */
+#endif /* PWR_CPUCR_PDDS_D2 */
+
+#define LL_PWR_WKUPFR_WKUPF6          PWR_WKUPFR_WKUPF6   /*!< Wakeup flag on PC1  */
+#define LL_PWR_WKUPFR_WKUPF5          PWR_WKUPFR_WKUPF5   /*!< Wakeup flag on PI11 */
+#define LL_PWR_WKUPFR_WKUPF4          PWR_WKUPFR_WKUPF4   /*!< Wakeup flag on PC13 */
+#define LL_PWR_WKUPFR_WKUPF3          PWR_WKUPFR_WKUPF3   /*!< Wakeup flag on PI8  */
+#define LL_PWR_WKUPFR_WKUPF2          PWR_WKUPFR_WKUPF2   /*!< Wakeup flag on PA2  */
+#define LL_PWR_WKUPFR_WKUPF1          PWR_WKUPFR_WKUPF1   /*!< Wakeup flag on PA0  */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_MODE_PWR Power mode
+  * @{
+  */
+#if defined (PWR_CPUCR_PDDS_D2)
+#define LL_PWR_CPU_MODE_D1STOP        0x00000000U           /*!< Enter D1 domain to Stop mode when the CPU enters deepsleep       */
+#define LL_PWR_CPU_MODE_D1STANDBY     PWR_CPUCR_PDDS_D1     /*!< Enter D1 domain to Standby mode when the CPU enters deepsleep    */
+#else
+#define LL_PWR_CPU_MODE_CDSTOP        0x00000000U           /*!< Enter CD domain to Stop mode when the CPU enters deepsleep       */
+#define LL_PWR_CPU_MODE_CDSTOP2       PWR_CPUCR_RETDS_CD    /*!< Enter CD domain to Stop2 mode when the CPU enters deepsleep      */
+#endif /* PWR_CPUCR_PDDS_D2 */
+
+#if defined (PWR_CPUCR_PDDS_D2)
+#define LL_PWR_CPU_MODE_D2STOP        0x00000000U           /*!< Enter D2 domain to Stop mode when the CPU enters deepsleep       */
+#define LL_PWR_CPU_MODE_D2STANDBY     PWR_CPUCR_PDDS_D2     /*!< Enter D2 domain to Standby mode when the CPU enters deepsleep    */
+#endif /* PWR_CPUCR_PDDS_D2 */
+
+#if defined (PWR_CPUCR_PDDS_D2)
+#define LL_PWR_CPU_MODE_D3RUN         PWR_CPUCR_RUN_D3      /*!< Keep system D3 domain in Run mode when the CPU enter deepsleep   */
+#define LL_PWR_CPU_MODE_D3STOP        0x00000000U           /*!< Enter D3 domain to Stop mode when the CPU enters deepsleep       */
+#define LL_PWR_CPU_MODE_D3STANDBY     PWR_CPUCR_PDDS_D3     /*!< Enter D3 domain to Standby mode when the CPU enters deepsleep    */
+#else
+#define LL_PWR_CPU_MODE_SRDRUN        PWR_CPUCR_RUN_SRD     /*!< Keep system SRD domain in Run mode when the CPU enter deepsleep  */
+#define LL_PWR_CPU_MODE_SRDSTOP       0x00000000U           /*!< Enter SRD domain to Stop mode when the CPU enters deepsleep      */
+#define LL_PWR_CPU_MODE_SRDSTANDBY    PWR_CPUCR_PDDS_SRD    /*!< Enter SRD domain to Standby mode when the CPU enters deepsleep   */
+#endif /* PWR_CPUCR_PDDS_D2 */
+
+#if defined (DUAL_CORE)
+#define LL_PWR_CPU2_MODE_D1STOP       0x00000000U           /*!< Enter D1 domain to Stop mode when the CPU2 enters deepsleep      */
+#define LL_PWR_CPU2_MODE_D1STANDBY    PWR_CPU2CR_PDDS_D1    /*!< Enter D1 domain to Standby mode when the CPU2 enters deepsleep   */
+#define LL_PWR_CPU2_MODE_D2STOP       0x00000000U           /*!< Enter D2 domain to Stop mode when the CPU2 enters deepsleep      */
+#define LL_PWR_CPU2_MODE_D2STANDBY    PWR_CPU2CR_PDDS_D2    /*!< Enter D2 domain to Standby mode when the CPU2 enters deepsleep   */
+#define LL_PWR_CPU2_MODE_D3RUN        PWR_CPU2CR_RUN_D3     /*!< Keep system D3 domain in RUN mode when the CPU2 enter deepsleep  */
+#define LL_PWR_CPU2_MODE_D3STOP       0x00000000U           /*!< Enter D3 domain to Stop mode when the CPU2 enters deepsleep      */
+#define LL_PWR_CPU2_MODE_D3STANDBY    PWR_CPU2CR_PDDS_D3    /*!< Enter D3 domain to Standby mode when the CPU2 enter deepsleep    */
+#endif /* DUAL_CORE */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_REGU_VOLTAGE Run mode Regulator Voltage Scaling
+  * @{
+  */
+#if defined (PWR_CPUCR_PDDS_D2)
+#define LL_PWR_REGU_VOLTAGE_SCALE3      PWR_D3CR_VOS_0                    /*!< Select voltage scale 3 */
+#define LL_PWR_REGU_VOLTAGE_SCALE2      PWR_D3CR_VOS_1                    /*!< Select voltage scale 2 */
+#define LL_PWR_REGU_VOLTAGE_SCALE1      (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 1 */
+#define LL_PWR_REGU_VOLTAGE_SCALE0      (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 0 */
+#else
+#define LL_PWR_REGU_VOLTAGE_SCALE3      0x00000000U                       /*!< Select voltage scale 3 */
+#define LL_PWR_REGU_VOLTAGE_SCALE2      PWR_D3CR_VOS_0                    /*!< Select voltage scale 2 */
+#define LL_PWR_REGU_VOLTAGE_SCALE1      PWR_D3CR_VOS_1                    /*!< Select voltage scale 1 */
+#define LL_PWR_REGU_VOLTAGE_SCALE0      (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 0 */
+#endif /* PWR_CPUCR_PDDS_D2 */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_STOP_MODE_REGU_VOLTAGE Stop mode Regulator Voltage Scaling
+  * @{
+  */
+#define LL_PWR_REGU_VOLTAGE_SVOS_SCALE5   PWR_CR1_SVOS_0                    /*!< Select voltage scale 5 when system enters STOP mode */
+#define LL_PWR_REGU_VOLTAGE_SVOS_SCALE4   PWR_CR1_SVOS_1                    /*!< Select voltage scale 4 when system enters STOP mode */
+#define LL_PWR_REGU_VOLTAGE_SVOS_SCALE3   (PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1) /*!< Select voltage scale 3 when system enters STOP mode */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE  Regulator Mode In Deep Sleep Mode
+  * @{
+  */
+#define LL_PWR_REGU_DSMODE_MAIN           0x00000000U   /*!< Voltage Regulator in main mode during deepsleep mode      */
+#define LL_PWR_REGU_DSMODE_LOW_POWER      PWR_CR1_LPDS  /*!< Voltage Regulator in low-power mode during deepsleep mode */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_PVDLEVEL Power Digital Voltage Level Detector
+  * @{
+  */
+#define LL_PWR_PVDLEVEL_0   PWR_CR1_PLS_LEV0  /*!< Voltage threshold detected by PVD 1.95 V */
+#define LL_PWR_PVDLEVEL_1   PWR_CR1_PLS_LEV1  /*!< Voltage threshold detected by PVD 2.1 V  */
+#define LL_PWR_PVDLEVEL_2   PWR_CR1_PLS_LEV2  /*!< Voltage threshold detected by PVD 2.25 V */
+#define LL_PWR_PVDLEVEL_3   PWR_CR1_PLS_LEV3  /*!< Voltage threshold detected by PVD 2.4 V  */
+#define LL_PWR_PVDLEVEL_4   PWR_CR1_PLS_LEV4  /*!< Voltage threshold detected by PVD 2.55 V */
+#define LL_PWR_PVDLEVEL_5   PWR_CR1_PLS_LEV5  /*!< Voltage threshold detected by PVD 2.7 V  */
+#define LL_PWR_PVDLEVEL_6   PWR_CR1_PLS_LEV6  /*!< Voltage threshold detected by PVD 2.85 V */
+#define LL_PWR_PVDLEVEL_7   PWR_CR1_PLS_LEV7  /*!< External voltage level on PVD_IN pin, compared to internal VREFINT level. */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_AVDLEVEL Power Analog Voltage Level Detector
+  * @{
+  */
+#define LL_PWR_AVDLEVEL_0   PWR_CR1_ALS_LEV0  /*!< Analog Voltage threshold detected by AVD 1.7 V */
+#define LL_PWR_AVDLEVEL_1   PWR_CR1_ALS_LEV1  /*!< Analog Voltage threshold detected by AVD 2.1 V */
+#define LL_PWR_AVDLEVEL_2   PWR_CR1_ALS_LEV2  /*!< Analog Voltage threshold detected by AVD 2.5 V */
+#define LL_PWR_AVDLEVEL_3   PWR_CR1_ALS_LEV3  /*!< Analog Voltage threshold detected by AVD 2.8 V */
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR Battery Charge Resistor
+  * @{
+  */
+#define LL_PWR_BATT_CHARG_RESISTOR_5K     0x00000000U   /*!< Charge the Battery through a 5 kO resistor    */
+#define LL_PWR_BATT_CHARGRESISTOR_1_5K    PWR_CR3_VBRS  /*!< Charge the Battery through a 1.5 kO resistor  */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_WAKEUP_PIN  Wakeup Pins
+  * @{
+  */
+#define LL_PWR_WAKEUP_PIN1    PWR_WKUPEPR_WKUPEN1  /*!< Wake-Up pin 1 : PA0  */
+#define LL_PWR_WAKEUP_PIN2    PWR_WKUPEPR_WKUPEN2  /*!< Wake-Up pin 2 : PA2  */
+#define LL_PWR_WAKEUP_PIN3    PWR_WKUPEPR_WKUPEN3  /*!< Wake-Up pin 3 : PI8  */
+#define LL_PWR_WAKEUP_PIN4    PWR_WKUPEPR_WKUPEN4  /*!< Wake-Up pin 4 : PC13 */
+#define LL_PWR_WAKEUP_PIN5    PWR_WKUPEPR_WKUPEN5  /*!< Wake-Up pin 5 : PI11 */
+#define LL_PWR_WAKEUP_PIN6    PWR_WKUPEPR_WKUPEN6  /*!< Wake-Up pin 6 : PC1  */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_WAKEUP_PIN_PULL  Wakeup Pins pull configuration
+  * @{
+  */
+#define LL_PWR_WAKEUP_PIN_NOPULL      0x00000000UL   /*!< Configure Wake-Up pin in no pull   */
+#define LL_PWR_WAKEUP_PIN_PULLUP      0x00000001UL   /*!< Configure Wake-Up pin in pull Up   */
+#define LL_PWR_WAKEUP_PIN_PULLDOWN    0x00000002UL   /*!< Configure Wake-Up pin in pull Down */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_SUPPLY_PWR Power supply source configuration
+  * @{
+  */
+#define LL_PWR_LDO_SUPPLY                     PWR_CR3_LDOEN                                                               /*!< Core domains are suppplied from the LDO                                                                     */
+#if defined (SMPS)                                                                                                                                                                                                                       
+#define LL_PWR_DIRECT_SMPS_SUPPLY             PWR_CR3_SMPSEN                                                              /*!< Core domains are suppplied from the SMPS                                                                    */
+#define LL_PWR_SMPS_1V8_SUPPLIES_LDO          (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)                      /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains                                       */
+#define LL_PWR_SMPS_2V5_SUPPLIES_LDO          (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)                      /*!< The SMPS 2.5V output supplies the LDO which supplies the Core domains                                       */
+#define LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO  (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)  /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */
+#define LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO  (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)  /*!< The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */
+#define LL_PWR_SMPS_1V8_SUPPLIES_EXT          (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 1.8V output supplies an external source which supplies the Core domains                            */
+#define LL_PWR_SMPS_2V5_SUPPLIES_EXT          (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 2.5V output supplies an external source which supplies the Core domains                            */
+#endif /* SMPS */
+#define LL_PWR_EXTERNAL_SOURCE_SUPPLY         PWR_CR3_BYPASS                                                              /*!< The SMPS and the LDO are Bypassed. The Core domains are supplied from an external source                    */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
+  * @{
+  */
+
+/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in PWR register
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in PWR register
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
+  * @{
+  */
+
+/** @defgroup PWR_LL_EF_Configuration Configuration
+  * @{
+  */
+
+  /**
+  * @brief  Set the voltage Regulator mode during deep sleep mode
+  * @rmtoll CR1    LPDS         LL_PWR_SetRegulModeDS
+  * @param  RegulMode This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_REGU_DSMODE_MAIN
+  *         @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
+{
+  MODIFY_REG(PWR->CR1, PWR_CR1_LPDS, RegulMode);
+}
+
+/**
+  * @brief  Get the voltage Regulator mode during deep sleep mode
+  * @rmtoll CR1    LPDS         LL_PWR_GetRegulModeDS
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_REGU_DSMODE_MAIN
+  *         @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPDS));
+}
+
+/**
+  * @brief  Enable Power Voltage Detector
+  * @rmtoll CR1    PVDEN       LL_PWR_EnablePVD
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnablePVD(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_PVDEN);
+}
+
+/**
+  * @brief  Disable Power Voltage Detector
+  * @rmtoll CR1    PVDEN       LL_PWR_DisablePVD
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisablePVD(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_PVDEN);
+}
+
+/**
+  * @brief  Check if Power Voltage Detector is enabled
+  * @rmtoll CR1    PVDEN       LL_PWR_IsEnabledPVD
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
+{
+  return ((READ_BIT(PWR->CR1, PWR_CR1_PVDEN) == (PWR_CR1_PVDEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure the voltage threshold detected by the Power Voltage Detector
+  * @rmtoll CR1    PLS       LL_PWR_SetPVDLevel
+  * @param  PVDLevel This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_PVDLEVEL_0
+  *         @arg @ref LL_PWR_PVDLEVEL_1
+  *         @arg @ref LL_PWR_PVDLEVEL_2
+  *         @arg @ref LL_PWR_PVDLEVEL_3
+  *         @arg @ref LL_PWR_PVDLEVEL_4
+  *         @arg @ref LL_PWR_PVDLEVEL_5
+  *         @arg @ref LL_PWR_PVDLEVEL_6
+  *         @arg @ref LL_PWR_PVDLEVEL_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
+{
+  MODIFY_REG(PWR->CR1, PWR_CR1_PLS, PVDLevel);
+}
+
+/**
+  * @brief  Get the voltage threshold detection
+  * @rmtoll CR1    PLS       LL_PWR_GetPVDLevel
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_PVDLEVEL_0
+  *         @arg @ref LL_PWR_PVDLEVEL_1
+  *         @arg @ref LL_PWR_PVDLEVEL_2
+  *         @arg @ref LL_PWR_PVDLEVEL_3
+  *         @arg @ref LL_PWR_PVDLEVEL_4
+  *         @arg @ref LL_PWR_PVDLEVEL_5
+  *         @arg @ref LL_PWR_PVDLEVEL_6
+  *         @arg @ref LL_PWR_PVDLEVEL_7
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_PLS));
+}
+
+/**
+  * @brief  Enable access to the backup domain
+  * @rmtoll CR1    DBP       LL_PWR_EnableBkUpAccess
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_DBP);
+}
+
+/**
+  * @brief  Disable access to the backup domain
+  * @rmtoll CR1    DBP       LL_PWR_DisableBkUpAccess
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
+}
+
+/**
+  * @brief  Check if the backup domain is enabled
+  * @rmtoll CR1    DBP       LL_PWR_IsEnabledBkUpAccess
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
+{
+  return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the Flash Power Down in Stop Mode
+  * @rmtoll CR1    FLPS       LL_PWR_EnableFlashPowerDown
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_FLPS);
+}
+
+/**
+  * @brief  Disable the Flash Power Down in Stop Mode
+  * @rmtoll CR1    FLPS       LL_PWR_DisableFlashPowerDown
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_FLPS);
+}
+
+/**
+  * @brief  Check if the Flash Power Down in Stop Mode is enabled
+  * @rmtoll CR1    FLPS       LL_PWR_IsEnabledFlashPowerDown
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void)
+{
+  return ((READ_BIT(PWR->CR1, PWR_CR1_FLPS) == (PWR_CR1_FLPS)) ? 1UL : 0UL);
+}
+
+#if defined (PWR_CR1_BOOSTE)
+/**
+  * @brief  Enable the Analog Voltage Booster (VDDA)
+  * @rmtoll CR1    BOOSTE     LL_PWR_EnableAnalogBooster
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableAnalogBooster(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_BOOSTE);
+}
+
+/**
+  * @brief  Disable the Analog Voltage Booster (VDDA)
+  * @rmtoll CR1    BOOSTE     LL_PWR_DisableAnalogBooster
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableAnalogBooster(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_BOOSTE);
+}
+
+/**
+  * @brief  Check if the Analog Voltage Booster (VDDA) is enabled
+  * @rmtoll CR1    BOOSTE     LL_PWR_IsEnabledAnalogBooster
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledAnalogBooster(void)
+{
+  return ((READ_BIT(PWR->CR1, PWR_CR1_BOOSTE) == (PWR_CR1_BOOSTE)) ? 1UL : 0UL);
+}
+#endif /* PWR_CR1_BOOSTE */
+
+#if defined (PWR_CR1_AVD_READY)
+/**
+  * @brief  Enable the Analog Voltage Ready to isolate the BOOST IP untill VDDA will be ready
+  * @rmtoll CR1    AVD_READY  LL_PWR_EnableAnalogVoltageReady
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableAnalogVoltageReady(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_AVD_READY);
+}
+
+/**
+  * @brief  Disable the Analog Voltage Ready (VDDA)
+  * @rmtoll CR1    AVD_READY  LL_PWR_DisableAnalogVoltageReady
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableAnalogVoltageReady(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_AVD_READY);
+}
+
+/**
+  * @brief  Check if the Analog Voltage Booster (VDDA) is enabled
+  * @rmtoll CR1    AVD_READY  LL_PWR_IsEnabledAnalogVoltageReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledAnalogVoltageReady(void)
+{
+  return ((READ_BIT(PWR->CR1, PWR_CR1_AVD_READY) == (PWR_CR1_AVD_READY)) ? 1UL : 0UL);
+}
+#endif /* PWR_CR1_AVD_READY */
+
+/**
+  * @brief  Set the internal Regulator output voltage in STOP mode
+  * @rmtoll CR1    SVOS       LL_PWR_SetStopModeRegulVoltageScaling
+  * @param  VoltageScaling This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE3
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE4
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE5
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetStopModeRegulVoltageScaling(uint32_t VoltageScaling)
+{
+  MODIFY_REG(PWR->CR1, PWR_CR1_SVOS, VoltageScaling);
+}
+
+/**
+  * @brief  Get the internal Regulator output voltage in STOP mode
+  * @rmtoll CR1    SVOS       LL_PWR_GetStopModeRegulVoltageScaling
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE3
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE4
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE5
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetStopModeRegulVoltageScaling(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_SVOS));
+}
+
+/**
+  * @brief  Enable Analog Power Voltage Detector
+  * @rmtoll CR1    AVDEN       LL_PWR_EnableAVD
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableAVD(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_AVDEN);
+}
+
+/**
+  * @brief  Disable Analog Power Voltage Detector
+  * @rmtoll CR1    AVDEN       LL_PWR_DisableAVD
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableAVD(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_AVDEN);
+}
+
+/**
+  * @brief  Check if Analog Power Voltage Detector is enabled
+  * @rmtoll CR1    AVDEN       LL_PWR_IsEnabledAVD
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledAVD(void)
+{
+  return ((READ_BIT(PWR->CR1, PWR_CR1_AVDEN) == (PWR_CR1_AVDEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure the voltage threshold to be detected by the Analog Power Voltage Detector
+  * @rmtoll CR1    ALS       LL_PWR_SetAVDLevel
+  * @param  AVDLevel This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_AVDLEVEL_0
+  *         @arg @ref LL_PWR_AVDLEVEL_1
+  *         @arg @ref LL_PWR_AVDLEVEL_2
+  *         @arg @ref LL_PWR_AVDLEVEL_3
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetAVDLevel(uint32_t AVDLevel)
+{
+  MODIFY_REG(PWR->CR1, PWR_CR1_ALS, AVDLevel);
+}
+
+/**
+  * @brief  Get the Analog Voltage threshold to be detected by the Analog Power Voltage Detector
+  * @rmtoll CR1    ALS       LL_PWR_GetAVDLevel
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_AVDLEVEL_0
+  *         @arg @ref LL_PWR_AVDLEVEL_1
+  *         @arg @ref LL_PWR_AVDLEVEL_2
+  *         @arg @ref LL_PWR_AVDLEVEL_3
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetAVDLevel(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_ALS));
+}
+
+#if defined (PWR_CR1_AXIRAM1SO)
+/**
+  * @brief  Enable the AXI RAM1 shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    AXIRAM1SO     LL_PWR_EnableAXIRAM1ShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableAXIRAM1ShutOff(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO);
+}
+
+/**
+  * @brief  Disable the AXI RAM1 shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    AXIRAM1SO     LL_PWR_DisableAXIRAM1ShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableAXIRAM1ShutOff(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO);
+}
+
+/**
+  * @brief  Check if the AXI RAM1 shut-off in DStop/DStop2 mode is enabled
+  * @rmtoll CR1    AXIRAM1SO     LL_PWR_IsEnabledAXIRAM1ShutOff
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM1ShutOff(void)
+{
+  return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO) == (PWR_CR1_AXIRAM1SO)) ? 1UL : 0UL);
+}
+#endif /* PWR_CR1_AXIRAM1SO */
+
+#if defined (PWR_CR1_AXIRAM2SO)
+/**
+  * @brief  Enable the AXI RAM2 shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    AXIRAM2SO     LL_PWR_EnableAXIRAM2ShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableAXIRAM2ShutOff(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO);
+}
+
+/**
+  * @brief  Disable the AXI RAM2 shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    AXIRAM2SO     LL_PWR_DisableAXIRAM2ShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableAXIRAM2ShutOff(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO);
+}
+
+/**
+  * @brief  Check if the AXI RAM2 shut-off in DStop/DStop2 mode is enabled
+  * @rmtoll CR1    AXIRAM2SO     LL_PWR_IsEnabledAXIRAM2ShutOff
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM2ShutOff(void)
+{
+  return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO) == (PWR_CR1_AXIRAM2SO)) ? 1UL : 0UL);
+}
+#endif /* PWR_CR1_AXIRAM2SO */
+
+#if defined (PWR_CR1_AXIRAM3SO)
+/**
+  * @brief  Enable the AXI RAM3 shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    AXIRAM3SO     LL_PWR_EnableAXIRAM3ShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableAXIRAM3ShutOff(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO);
+}
+
+/**
+  * @brief  Disable the AXI RAM3 shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    AXIRAM3SO     LL_PWR_DisableAXIRAM3ShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableAXIRAM3ShutOff(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO);
+}
+
+/**
+  * @brief  Check if the AXI RAM3 shut-off in DStop/DStop2 mode is enabled
+  * @rmtoll CR1    AXIRAM3SO     LL_PWR_IsEnabledAXIRAM3ShutOff
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM3ShutOff(void)
+{
+  return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO) == (PWR_CR1_AXIRAM3SO)) ? 1UL : 0UL);
+}
+#endif /* PWR_CR1_AXIRAM3SO */
+
+#if defined (PWR_CR1_AHBRAM1SO)
+/**
+  * @brief  Enable the AHB RAM1 shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    AHBRAM1SO     LL_PWR_EnableAHBRAM1ShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableAHBRAM1ShutOff(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO);
+}
+
+/**
+  * @brief  Disable the AHB RAM1 shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    AHBRAM1SO     LL_PWR_DisableAHBRAM1ShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableAHBRAM1ShutOff(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO);
+}
+
+/**
+  * @brief  Check if the AHB RAM1 shut-off in DStop/DStop2 mode is enabled
+  * @rmtoll CR1    AHBRAM1SO     LL_PWR_IsEnabledAHBRAM1ShutOff
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM1ShutOff(void)
+{
+  return ((READ_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO) == (PWR_CR1_AHBRAM1SO)) ? 1UL : 0UL);
+}
+#endif /* PWR_CR1_AHBRAM1SO */
+
+#if defined (PWR_CR1_AHBRAM2SO)
+/**
+  * @brief  Enable the AHB RAM2 shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    AHBRAM2SO     LL_PWR_EnableAHBRAM2ShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableAHBRAM2ShutOff(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO);
+}
+
+/**
+  * @brief  Disable the AHB RAM2 shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    AHBRAM2SO     LL_PWR_DisableAHBRAM2ShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableAHBRAM2ShutOff(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO);
+}
+
+/**
+  * @brief  Check if the AHB RAM2 shut-off in DStop/DStop2 mode is enabled
+  * @rmtoll CR1    AHBRAM2SO     LL_PWR_IsEnabledAHBRAM2ShutOff
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM2ShutOff(void)
+{
+  return ((READ_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO) == (PWR_CR1_AHBRAM2SO)) ? 1UL : 0UL);
+}
+#endif /* PWR_CR1_AHBRAM2SO */
+
+#if defined (PWR_CR1_ITCMSO)
+/**
+  * @brief  Enable the ITCM shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    ITCMSO     LL_PWR_EnableITCMSOShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableITCMSOShutOff(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_ITCMSO);
+}
+
+/**
+  * @brief  Disable the ITCM shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    ITCMSO     LL_PWR_DisableITCMSOShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableITCMSOShutOff(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_ITCMSO);
+}
+
+/**
+  * @brief  Check if the ITCM shut-off in DStop/DStop2 mode is enabled
+  * @rmtoll CR1    ITCMSO     LL_PWR_IsEnabledITCMShutOff
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledITCMShutOff(void)
+{
+  return ((READ_BIT(PWR->CR1, PWR_CR1_ITCMSO) == (PWR_CR1_ITCMSO)) ? 1UL : 0UL);
+}
+#endif /* PWR_CR1_ITCMSO */
+
+#if defined (PWR_CR1_HSITFSO)
+/**
+  * @brief  Enable the USB and FDCAN shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    HSITFSO     LL_PWR_EnableHSITFShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableHSITFShutOff(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_HSITFSO);
+}
+
+/**
+  * @brief  Disable the USB and FDCAN shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    HSITFSO     LL_PWR_DisableHSITFShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableHSITFShutOff(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_HSITFSO);
+}
+
+/**
+  * @brief  Check if the USB and FDCAN shut-off in DStop/DStop2 mode is enabled
+  * @rmtoll CR1    HSITFSO     LL_PWR_IsEnabledHSITFShutOff
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledHSITFShutOff(void)
+{
+  return ((READ_BIT(PWR->CR1, PWR_CR1_HSITFSO) == (PWR_CR1_HSITFSO)) ? 1UL : 0UL);
+}
+#endif /* PWR_CR1_HSITFSO */
+
+#if defined (PWR_CR1_SRDRAMSO)
+/**
+  * @brief  Enable the SRD AHB RAM shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    SRDRAMSO     LL_PWR_EnableSRDRAMShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableSRDRAMShutOff(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_SRDRAMSO);
+}
+
+/**
+  * @brief  Disable the SRD AHB RAM shut-off in DStop/DStop2 mode
+  * @rmtoll CR1    SRDRAMSO     LL_PWR_DisableSRDRAMShutOff
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableSRDRAMShutOff(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_SRDRAMSO);
+}
+
+/**
+  * @brief  Check if the SRD AHB RAM shut-off in DStop/DStop2 mode is enabled
+  * @rmtoll CR1    SRDRAMSO     LL_PWR_IsEnabledSRDRAMShutOff
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledSRDRAMShutOff(void)
+{
+  return ((READ_BIT(PWR->CR1, PWR_CR1_SRDRAMSO) == (PWR_CR1_SRDRAMSO)) ? 1UL : 0UL);
+}
+#endif /* PWR_CR1_SRDRAMSO */
+
+/**
+  * @brief  Enable Backup Regulator
+  * @rmtoll CR2    BREN       LL_PWR_EnableBkUpRegulator
+  * @note When set, the Backup Regulator (used to maintain backup SRAM content in Standby and
+  *       VBAT modes) is enabled. If BRE is reset, the backup Regulator is switched off. The backup
+  *       SRAM can still be used but its content will be lost in the Standby and VBAT modes. Once set,
+  *       the application must wait that the Backup Regulator Ready flag (BRR) is set to indicate that
+  *       the data written into the RAM will be maintained in the Standby and VBAT modes.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void)
+{
+  SET_BIT(PWR->CR2, PWR_CR2_BREN);
+}
+
+/**
+  * @brief  Disable Backup Regulator
+  * @rmtoll CR2    BREN       LL_PWR_DisableBkUpRegulator
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void)
+{
+  CLEAR_BIT(PWR->CR2, PWR_CR2_BREN);
+}
+
+/**
+  * @brief  Check if the backup Regulator is enabled
+  * @rmtoll CR2    BREN      LL_PWR_IsEnabledBkUpRegulator
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void)
+{
+  return ((READ_BIT(PWR->CR2, PWR_CR2_BREN) == (PWR_CR2_BREN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable VBAT and Temperature monitoring
+  * @rmtoll CR2    MONEN       LL_PWR_EnableMonitoring
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableMonitoring(void)
+{
+  SET_BIT(PWR->CR2, PWR_CR2_MONEN);
+}
+
+/**
+  * @brief  Disable VBAT and Temperature monitoring
+  * @rmtoll CR2    MONEN       LL_PWR_DisableMonitoring
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableMonitoring(void)
+{
+  CLEAR_BIT(PWR->CR2, PWR_CR2_MONEN);
+}
+
+/**
+  * @brief  Check if the VBAT and Temperature monitoring is enabled
+  * @rmtoll CR2    MONEN      LL_PWR_IsEnabledMonitoring
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledMonitoring(void)
+{
+  return ((READ_BIT(PWR->CR2, PWR_CR2_MONEN) == (PWR_CR2_MONEN)) ? 1UL : 0UL);
+}
+
+#if defined (SMPS)
+/**
+  * @brief  Configure the PWR supply
+  * @rmtoll CR3          BYPASS          LL_PWR_ConfigSupply
+  * @rmtoll CR3          LDOEN           LL_PWR_ConfigSupply
+  * @rmtoll CR3          SMPSEN          LL_PWR_ConfigSupply
+  * @rmtoll CR3          SMPSEXTHP       LL_PWR_ConfigSupply
+  * @rmtoll CR3          SMPSLEVEL       LL_PWR_ConfigSupply
+  * @param  SupplySource This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_LDO_SUPPLY
+  *         @arg @ref LL_PWR_DIRECT_SMPS_SUPPLY
+  *         @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_LDO
+  *         @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_LDO
+  *         @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO
+  *         @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO
+  *         @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT
+  *         @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT
+  *         @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ConfigSupply(uint32_t SupplySource)
+{
+  /* Set the power supply configuration */
+  MODIFY_REG(PWR->CR3, (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS), SupplySource);
+}
+#else
+/**
+  * @brief  Configure the PWR supply
+  * @rmtoll CR3          BYPASS          LL_PWR_ConfigSupply
+  * @rmtoll CR3          LDOEN           LL_PWR_ConfigSupply
+  * @rmtoll CR3          SCUEN           LL_PWR_ConfigSupply
+  * @param  SupplySource This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_LDO_SUPPLY
+  *         @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ConfigSupply(uint32_t SupplySource)
+{
+  /* Set the power supply configuration */
+  MODIFY_REG(PWR->CR3, (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS), SupplySource);
+}
+#endif /* defined (SMPS) */
+
+#if defined (SMPS)
+/**
+  * @brief  Get the PWR supply
+  * @rmtoll CR3          BYPASS          LL_PWR_GetSupply
+  * @rmtoll CR3          LDOEN           LL_PWR_GetSupply
+  * @rmtoll CR3          SMPSEN          LL_PWR_GetSupply
+  * @rmtoll CR3          SMPSEXTHP       LL_PWR_GetSupply
+  * @rmtoll CR3          SMPSLEVEL       LL_PWR_GetSupply
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_LDO_SUPPLY
+  *         @arg @ref LL_PWR_DIRECT_SMPS_SUPPLY
+  *         @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_LDO
+  *         @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_LDO
+  *         @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO
+  *         @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO
+  *         @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT
+  *         @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT
+  *         @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetSupply(void)
+{
+  /* Get the power supply configuration */
+  return(uint32_t)(READ_BIT(PWR->CR3, (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)));
+}
+#else
+/**
+  * @brief  Get the PWR supply
+  * @rmtoll CR3          BYPASS          LL_PWR_GetSupply
+  * @rmtoll CR3          LDOEN           LL_PWR_GetSupply
+  * @rmtoll CR3          SCUEN           LL_PWR_GetSupply
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_LDO_SUPPLY
+  *         @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetSupply(void)
+{
+  /* Get the power supply configuration */
+  return(uint32_t)(READ_BIT(PWR->CR3, (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)));
+}
+#endif /* defined (SMPS) */
+
+/**
+  * @brief  Enable battery charging
+  * @rmtoll CR3          VBE           LL_PWR_EnableBatteryCharging
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableBatteryCharging(void)
+{
+  SET_BIT(PWR->CR3, PWR_CR3_VBE);
+}
+
+/**
+  * @brief  Disable battery charging
+  * @rmtoll CR3          VBE           LL_PWR_DisableBatteryCharging
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableBatteryCharging(void)
+{
+  CLEAR_BIT(PWR->CR3, PWR_CR3_VBE);
+}
+
+/**
+  * @brief  Check if battery charging is enabled
+  * @rmtoll CR3          VBE           LL_PWR_IsEnabledBatteryCharging
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)
+{
+  return ((READ_BIT(PWR->CR3, PWR_CR3_VBE) == (PWR_CR3_VBE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the Battery charge resistor impedance
+  * @rmtoll CR3          VBRS          LL_PWR_SetBattChargResistor
+  * @param  Resistor This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
+  *         @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor)
+{
+  MODIFY_REG(PWR->CR3, PWR_CR3_VBRS, Resistor);
+}
+
+/**
+  * @brief  Get the Battery charge resistor impedance
+  * @rmtoll CR3          VBRS          LL_PWR_GetBattChargResistor
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
+  *         @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CR3, PWR_CR3_VBRS));
+}
+
+/**
+  * @brief  Enable the USB regulator
+  * @rmtoll CR3          USBREGEN           LL_PWR_EnableUSBReg
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableUSBReg(void)
+{
+  SET_BIT(PWR->CR3, PWR_CR3_USBREGEN);
+}
+
+/**
+  * @brief  Disable the USB regulator
+  * @rmtoll CR3          USBREGEN           LL_PWR_DisableUSBReg
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableUSBReg(void)
+{
+  CLEAR_BIT(PWR->CR3, PWR_CR3_USBREGEN);
+}
+
+/**
+  * @brief  Check if the USB regulator is enabled
+  * @rmtoll CR3          USBREGEN           LL_PWR_IsEnabledUSBReg
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBReg(void)
+{
+  return ((READ_BIT(PWR->CR3, PWR_CR3_USBREGEN) == (PWR_CR3_USBREGEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the USB voltage detector
+  * @rmtoll CR3          USB33DEN           LL_PWR_EnableUSBVoltageDetector
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableUSBVoltageDetector(void)
+{
+  SET_BIT(PWR->CR3, PWR_CR3_USB33DEN);
+}
+
+/**
+  * @brief  Disable the USB voltage detector
+  * @rmtoll CR3          USB33DEN           LL_PWR_DisableUSBVoltageDetector
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableUSBVoltageDetector(void)
+{
+  CLEAR_BIT(PWR->CR3, PWR_CR3_USB33DEN);
+}
+
+/**
+  * @brief  Check if the USB voltage detector is enabled
+  * @rmtoll CR3          USB33DEN           LL_PWR_IsEnabledUSBVoltageDetector
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBVoltageDetector(void)
+{
+  return ((READ_BIT(PWR->CR3, PWR_CR3_USB33DEN) == (PWR_CR3_USB33DEN)) ? 1UL : 0UL);
+}
+
+#if defined (PWR_CPUCR_PDDS_D2)
+/**
+  * @brief  Set the D1 domain Power Down mode when the CPU enters deepsleep
+  * @rmtoll CPUCR     PDDS_D1       LL_PWR_CPU_SetD1PowerMode
+  * @param  PDMode This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_CPU_MODE_D1STOP
+  *         @arg @ref LL_PWR_CPU_MODE_D1STANDBY
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_CPU_SetD1PowerMode(uint32_t PDMode)
+{
+  MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D1, PDMode);
+}
+#else
+/**
+  * @brief  Set the CPU domain Power Down mode when the CPU enters deepsleep
+  * @rmtoll CPUCR     RETDS_CD       LL_PWR_CPU_SetCDPowerMode
+  * @param  PDMode This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_CPU_MODE_CDSTOP
+  *         @arg @ref LL_PWR_CPU_MODE_CDSTOP2
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_CPU_SetCDPowerMode(uint32_t PDMode)
+{
+  MODIFY_REG(PWR->CPUCR, PWR_CPUCR_RETDS_CD, PDMode);
+}
+#endif /* PWR_CPUCR_PDDS_D2 */
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Set the D1 domain Power Down mode when the CPU2 enters deepsleep
+  * @rmtoll CPU2CR     PDDS_D1       LL_PWR_CPU2_SetD1PowerMode
+  * @param  PDMode This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_CPU2_MODE_D1STOP
+  *         @arg @ref LL_PWR_CPU2_MODE_D1STANDBY
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_CPU2_SetD1PowerMode(uint32_t PDMode)
+{
+  MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D1, PDMode);
+}
+#endif /* DUAL_CORE */
+
+#if defined (PWR_CPUCR_PDDS_D2)
+/**
+  * @brief  Get the D1 Domain Power Down mode when the CPU enters deepsleep
+  * @rmtoll CPUCR     PDDS_D1       LL_PWR_CPU_GetD1PowerMode
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_CPU_MODE_D1STOP
+  *         @arg @ref LL_PWR_CPU_MODE_D1STANDBY
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU_GetD1PowerMode(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1));
+}
+#else
+/**
+  * @brief  Get the CD Domain Power Down mode when the CPU enters deepsleep
+  * @rmtoll CPUCR     RETDS_CD       LL_PWR_CPU_GetCDPowerMode
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_CPU_MODE_CDSTOP
+  *         @arg @ref LL_PWR_CPU_MODE_CDSTOP2
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU_GetCDPowerMode(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_RETDS_CD));
+}
+#endif /* PWR_CPUCR_PDDS_D2 */
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Get the D1 Domain Power Down mode when the CPU2 enters deepsleep
+  * @rmtoll CPU2CR     PDDS_D1       LL_PWR_CPU2_GetD1PowerMode
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_CPU2_MODE_D1STOP
+  *         @arg @ref LL_PWR_CPU2_MODE_D1STANDBY
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU2_GetD1PowerMode(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D1));
+}
+#endif /* DUAL_CORE */
+
+#if defined (PWR_CPUCR_PDDS_D2)
+/**
+  * @brief  Set the D2 domain Power Down mode when the CPU enters deepsleep
+  * @rmtoll CPUCR     PDDS_D2       LL_PWR_CPU_SetD2PowerMode
+  * @param  PDMode This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_CPU_MODE_D2STOP
+  *         @arg @ref LL_PWR_CPU_MODE_D2STANDBY
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_CPU_SetD2PowerMode(uint32_t PDMode)
+{
+  MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D2, PDMode);
+}
+#endif /* PWR_CPUCR_PDDS_D2 */
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Set the D2 domain Power Down mode when the CPU2 enters deepsleep
+  * @rmtoll CPU2CR     PDDS_D2       LL_PWR_CPU2_SetD2PowerMode
+  * @param  PDMode This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_CPU2_MODE_D2STOP
+  *         @arg @ref LL_PWR_CPU2_MODE_D2STANDBY
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_CPU2_SetD2PowerMode(uint32_t PDMode)
+{
+  MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D2, PDMode);
+}
+#endif /* DUAL_CORE */
+
+#if defined (PWR_CPUCR_PDDS_D2)
+/**
+  * @brief  Get the D2 Domain Power Down mode when the CPU enters deepsleep
+  * @rmtoll CPUCR     PDDS_D2       LL_PWR_CPU_GetD2PowerMode
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_CPU_MODE_D2STOP
+  *         @arg @ref LL_PWR_CPU_MODE_D2STANDBY
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU_GetD2PowerMode(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D2));
+}
+#endif /* PWR_CPUCR_PDDS_D2 */
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Get the D2 Domain Power Down mode when the CPU2 enters deepsleep
+  * @rmtoll CPU2CR     PDDS_D2       LL_PWR_CPU2_GetD2PowerMode
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_CPU2_MODE_D2STOP
+  *         @arg @ref LL_PWR_CPU2_MODE_D2STANDBY
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU2_GetD2PowerMode(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D2));
+}
+#endif /* DUAL_CORE */
+
+#if defined (PWR_CPUCR_PDDS_D2)
+/**
+  * @brief  Set the D3 domain Power Down mode when the CPU enters deepsleep
+  * @rmtoll CPUCR     PDDS_D3       LL_PWR_CPU_SetD3PowerMode
+  * @param  PDMode This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_CPU_MODE_D3STOP
+  *         @arg @ref LL_PWR_CPU_MODE_D3STANDBY
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_CPU_SetD3PowerMode(uint32_t PDMode)
+{
+  MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D3 , PDMode);
+}
+#else
+/**
+  * @brief  Set the SRD domain Power Down mode when the CPU enters deepsleep
+  * @rmtoll CPUCR     PDDS_SRD       LL_PWR_CPU_SetSRDPowerMode
+  * @param  PDMode This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_CPU_MODE_SRDSTOP
+  *         @arg @ref LL_PWR_CPU_MODE_SRDSTANDBY
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_CPU_SetSRDPowerMode(uint32_t PDMode)
+{
+  MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_SRD , PDMode);
+}
+#endif /* PWR_CPUCR_PDDS_D2 */
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Set the D3 domain Power Down mode when the CPU2 enters deepsleep
+  * @rmtoll CPU2CR     PDDS_D3       LL_PWR_CPU2_SetD3PowerMode
+  * @param  PDMode This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_CPU2_MODE_D3STOP
+  *         @arg @ref LL_PWR_CPU2_MODE_D3STANDBY
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_CPU2_SetD3PowerMode(uint32_t PDMode)
+{
+  MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D3, PDMode);
+}
+#endif /* DUAL_CORE */
+
+#if defined (PWR_CPUCR_PDDS_D3)
+/**
+  * @brief  Get the D3 Domain Power Down mode when the CPU enters deepsleep
+  * @rmtoll CPUCR     PDDS_D3       LL_PWR_CPU_GetD3PowerMode
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_CPU_MODE_D3STOP
+  *         @arg @ref LL_PWR_CPU_MODE_D3STANDBY
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU_GetD3PowerMode(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D3));
+}
+#else
+/**
+  * @brief  Get the SRD Domain Power Down mode when the CPU enters deepsleep
+  * @rmtoll CPUCR     PDDS_SRD       LL_PWR_CPU_GetSRDPowerMode
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_CPU_MODE_SRDSTOP
+  *         @arg @ref LL_PWR_CPU_MODE_SRDSTANDBY
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU_GetSRDPowerMode(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_SRD));
+}
+#endif /* PWR_CPUCR_PDDS_D3 */
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Get the D3 Domain Power Down mode when the CPU2 enters deepsleep
+  * @rmtoll CPU2CR     PDDS_D3       LL_PWR_CPU2_GetD3PowerMode
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_CPU2_MODE_D3STOP
+  *         @arg @ref LL_PWR_CPU2_MODE_D3STANDBY
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU2_GetD3PowerMode(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D3));
+}
+#endif /* DUAL_CORE */
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Hold the CPU1 and allocated peripherals when exiting from STOP mode
+  * @rmtoll CPU2CR     HOLD1       LL_PWR_HoldCPU1
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_HoldCPU1(void)
+{
+  SET_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1);
+}
+
+/**
+  * @brief  Release the CPU1 and allocated peripherals
+  * @rmtoll CPU2CR     HOLD1       LL_PWR_ReleaseCPU1
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ReleaseCPU1(void)
+{
+  CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1);
+}
+
+/**
+  * @brief  Ckeck if the CPU1 and allocated peripherals are held
+  * @rmtoll CPU2CR     HOLD1       LL_PWR_IsCPU1Held
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsCPU1Held(void)
+{
+  return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1) == (PWR_CPU2CR_HOLD1))  ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Hold the CPU2 and allocated peripherals when exiting from STOP mode
+  * @rmtoll CPUCR     HOLD2       LL_PWR_HoldCPU2
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_HoldCPU2(void)
+{
+  SET_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2);
+}
+
+/**
+  * @brief  Release the CPU2 and allocated peripherals
+  * @rmtoll CPUCR     HOLD2       LL_PWR_ReleaseCPU2
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ReleaseCPU2(void)
+{
+  CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2);
+}
+
+/**
+  * @brief  Ckeck if the CPU2 and allocated peripherals are held
+  * @rmtoll CPUCR     HOLD2       LL_PWR_IsCPU2Held
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsCPU2Held(void)
+{
+  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2) == (PWR_CPUCR_HOLD2)) ? 1UL : 0UL);
+}
+#endif /* DUAL_CORE */
+
+#if defined (PWR_CPUCR_PDDS_D2)
+/**
+  * @brief  D3 domain remains in Run mode regardless of CPU subsystem modes
+  * @rmtoll CPUCR     RUN_D3       LL_PWR_CPU_EnableD3RunInLowPowerMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_CPU_EnableD3RunInLowPowerMode(void)
+{
+  SET_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3);
+}
+#else
+/**
+  * @brief  SRD domain remains in Run mode regardless of CPU subsystem modes
+  * @rmtoll CPUCR     RUN_SRD      LL_PWR_CPU_EnableSRDRunInLowPowerMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_CPU_EnableSRDRunInLowPowerMode(void)
+{
+  SET_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD);
+}
+#endif /* PWR_CPUCR_PDDS_D2 */
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  D3 domain remains in Run mode regardless of CPU2 subsystem modes
+  * @rmtoll CPU2CR     RUN_D3       LL_PWR_CPU2_EnableD3RunInLowPowerMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_CPU2_EnableD3RunInLowPowerMode(void)
+{
+  SET_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3);
+}
+#endif /* DUAL_CORE */
+
+#if defined (PWR_CPUCR_PDDS_D2)
+/**
+  * @brief  D3 domain follows CPU subsystem modes
+  * @rmtoll CPUCR     RUN_D3       LL_PWR_CPU_DisableD3RunInLowPowerMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_CPU_DisableD3RunInLowPowerMode(void)
+{
+  CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3);
+}
+#else
+/**
+  * @brief  SRD domain follows CPU subsystem modes
+  * @rmtoll CPUCR     RUN_SRD      LL_PWR_CPU_DisableSRDRunInLowPowerMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_CPU_DisableSRDRunInLowPowerMode(void)
+{
+  CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD);
+}
+#endif /* PWR_CPUCR_PDDS_D2 */
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  D3 domain follows CPU2 subsystem modes
+  * @rmtoll CPU2CR     RUN_D3       LL_PWR_CPU2_DisableD3RunInLowPowerMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_CPU2_DisableD3RunInLowPowerMode(void)
+{
+  CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3);
+}
+#endif /* DUAL_CORE */
+
+#if defined (PWR_CPUCR_PDDS_D2)
+/**
+  * @brief  Check if D3 is kept in Run mode when CPU enters low power mode
+  * @rmtoll CPUCR     RUN_D3    LL_PWR_CPU_IsEnabledD3RunInLowPowerMode
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU_IsEnabledD3RunInLowPowerMode(void)
+{
+  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3) == (PWR_CPUCR_RUN_D3)) ? 1UL : 0UL);
+}
+#else
+/**
+  * @brief  Check if SRD is kept in Run mode when CPU enters low power mode
+  * @rmtoll CPUCR     RUN_SRD    LL_PWR_CPU_IsEnabledSRDRunInLowPowerMode
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU_IsEnabledSRDRunInLowPowerMode(void)
+{
+  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD) == (PWR_CPUCR_RUN_SRD)) ? 1UL : 0UL);
+}
+#endif /* PWR_CPUCR_PDDS_D2 */
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Check if D3 is kept in Run mode when CPU2 enters low power mode
+  * @rmtoll CPU2CR     RUN_D3    LL_PWR_CPU2_IsEnabledD3RunInLowPowerMode
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU2_IsEnabledD3RunInLowPowerMode(void)
+{
+  return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3) == (PWR_CPU2CR_RUN_D3)) ? 1UL : 0UL);
+}
+#endif /* DUAL_CORE */
+
+/**
+  * @brief  Set the main internal Regulator output voltage
+  * @rmtoll D3CR    VOS       LL_PWR_SetRegulVoltageScaling
+  * @param  VoltageScaling This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
+  * @note   For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines, VOS0 
+  *         is applied when PWR_D3CR_VOS[1:0] = 0b11 and  SYSCFG_PWRCR_ODEN = 0b1.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
+{
+#if defined (PWR_CPUCR_PDDS_D2)
+  MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, VoltageScaling);
+#else
+  MODIFY_REG(PWR->SRDCR, PWR_SRDCR_VOS, VoltageScaling);
+#endif /* PWR_CPUCR_PDDS_D2 */
+}
+
+/**
+  * @brief  Get the main internal Regulator output voltage
+  * @rmtoll D3CR    VOS       LL_PWR_GetRegulVoltageScaling
+  * @note   For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines, checking 
+  *         VOS0 need the check of PWR_D3CR_VOS[1:0] field and SYSCFG_PWRCR_ODEN bit.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
+{
+#if defined (PWR_CPUCR_PDDS_D2)
+  return (uint32_t)(READ_BIT(PWR->D3CR, PWR_D3CR_VOS));
+#else
+  return (uint32_t)(READ_BIT(PWR->SRDCR, PWR_SRDCR_VOS));
+#endif /* PWR_CPUCR_PDDS_D2 */
+}
+
+/**
+  * @brief  Enable the WakeUp PINx functionality
+  * @rmtoll WKUPEPR   WKUPEN1       LL_PWR_EnableWakeUpPin\n
+  *         WKUPEPR   WKUPEN2       LL_PWR_EnableWakeUpPin\n
+  *         WKUPEPR   WKUPEN3       LL_PWR_EnableWakeUpPin\n
+  *         WKUPEPR   WKUPEN4       LL_PWR_EnableWakeUpPin\n
+  *         WKUPEPR   WKUPEN5       LL_PWR_EnableWakeUpPin\n
+  *         WKUPEPR   WKUPEN6       LL_PWR_EnableWakeUpPin
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  *         @arg @ref LL_PWR_WAKEUP_PIN6
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
+{
+  SET_BIT(PWR->WKUPEPR, WakeUpPin);
+}
+
+/**
+  * @brief  Disable the WakeUp PINx functionality
+  * @rmtoll WKUPEPR   WKUPEN1       LL_PWR_DisableWakeUpPin\n
+  *         WKUPEPR   WKUPEN2       LL_PWR_DisableWakeUpPin\n
+  *         WKUPEPR   WKUPEN3       LL_PWR_DisableWakeUpPin\n
+  *         WKUPEPR   WKUPEN4       LL_PWR_DisableWakeUpPin\n
+  *         WKUPEPR   WKUPEN5       LL_PWR_DisableWakeUpPin\n
+  *         WKUPEPR   WKUPEN6       LL_PWR_DisableWakeUpPin
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  *         @arg @ref LL_PWR_WAKEUP_PIN6
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
+{
+  CLEAR_BIT(PWR->WKUPEPR, WakeUpPin);
+}
+
+/**
+  * @brief  Check if the WakeUp PINx functionality is enabled
+  * @rmtoll WKUPEPR   WKUPEN1       LL_PWR_IsEnabledWakeUpPin\n
+  *         WKUPEPR   WKUPEN2       LL_PWR_IsEnabledWakeUpPin\n
+  *         WKUPEPR   WKUPEN3       LL_PWR_IsEnabledWakeUpPin\n
+  *         WKUPEPR   WKUPEN4       LL_PWR_IsEnabledWakeUpPin\n
+  *         WKUPEPR   WKUPEN5       LL_PWR_IsEnabledWakeUpPin\n
+  *         WKUPEPR   WKUPEN6       LL_PWR_IsEnabledWakeUpPin
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  *         @arg @ref LL_PWR_WAKEUP_PIN6
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
+{
+  return ((READ_BIT(PWR->WKUPEPR, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the Wake-Up pin polarity low for the event detection
+  * @rmtoll WKUPEPR   WKUPP1       LL_PWR_SetWakeUpPinPolarityLow\n
+  *         WKUPEPR   WKUPP2       LL_PWR_SetWakeUpPinPolarityLow\n
+  *         WKUPEPR   WKUPP3       LL_PWR_SetWakeUpPinPolarityLow\n
+  *         WKUPEPR   WKUPP4       LL_PWR_SetWakeUpPinPolarityLow\n
+  *         WKUPEPR   WKUPP5       LL_PWR_SetWakeUpPinPolarityLow\n
+  *         WKUPEPR   WKUPP6       LL_PWR_SetWakeUpPinPolarityLow
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  *         @arg @ref LL_PWR_WAKEUP_PIN6
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
+{
+  SET_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos));
+}
+
+/**
+  * @brief  Set the Wake-Up pin polarity high for the event detection
+  * @rmtoll WKUPEPR   WKUPP1       LL_PWR_SetWakeUpPinPolarityHigh\n
+  *         WKUPEPR   WKUPP2       LL_PWR_SetWakeUpPinPolarityHigh\n
+  *         WKUPEPR   WKUPP3       LL_PWR_SetWakeUpPinPolarityHigh\n
+  *         WKUPEPR   WKUPP4       LL_PWR_SetWakeUpPinPolarityHigh\n
+  *         WKUPEPR   WKUPP5       LL_PWR_SetWakeUpPinPolarityHigh\n
+  *         WKUPEPR   WKUPP6       LL_PWR_SetWakeUpPinPolarityHigh
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  *         @arg @ref LL_PWR_WAKEUP_PIN6
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
+{
+  CLEAR_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos));
+}
+
+/**
+  * @brief  Get the Wake-Up pin polarity for the event detection
+  * @rmtoll WKUPEPR   WKUPP1       LL_PWR_IsWakeUpPinPolarityLow\n
+  *         WKUPEPR   WKUPP2       LL_PWR_IsWakeUpPinPolarityLow\n
+  *         WKUPEPR   WKUPP3       LL_PWR_IsWakeUpPinPolarityLow\n
+  *         WKUPEPR   WKUPP4       LL_PWR_IsWakeUpPinPolarityLow\n
+  *         WKUPEPR   WKUPP5       LL_PWR_IsWakeUpPinPolarityLow\n
+  *         WKUPEPR   WKUPP6       LL_PWR_IsWakeUpPinPolarityLow
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  *         @arg @ref LL_PWR_WAKEUP_PIN6
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
+{
+  return ((READ_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) == (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the Wake-Up pin Pull None
+  * @rmtoll WKUPEPR   WKUPPUPD1       LL_PWR_SetWakeUpPinPullNone\n
+  *         WKUPEPR   WKUPPUPD2       LL_PWR_SetWakeUpPinPullNone\n
+  *         WKUPEPR   WKUPPUPD3       LL_PWR_SetWakeUpPinPullNone\n
+  *         WKUPEPR   WKUPPUPD4       LL_PWR_SetWakeUpPinPullNone\n
+  *         WKUPEPR   WKUPPUPD5       LL_PWR_SetWakeUpPinPullNone\n
+  *         WKUPEPR   WKUPPUPD6       LL_PWR_SetWakeUpPinPullNone
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  *         @arg @ref LL_PWR_WAKEUP_PIN6
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetWakeUpPinPullNone(uint32_t WakeUpPin)
+{
+  MODIFY_REG(PWR->WKUPEPR, \
+            (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \
+            (LL_PWR_WAKEUP_PIN_NOPULL << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
+}
+
+/**
+  * @brief  Set the Wake-Up pin Pull Up
+  * @rmtoll WKUPEPR   WKUPPUPD1       LL_PWR_SetWakeUpPinPullUp\n
+  *         WKUPEPR   WKUPPUPD2       LL_PWR_SetWakeUpPinPullUp\n
+  *         WKUPEPR   WKUPPUPD3       LL_PWR_SetWakeUpPinPullUp\n
+  *         WKUPEPR   WKUPPUPD4       LL_PWR_SetWakeUpPinPullUp\n
+  *         WKUPEPR   WKUPPUPD5       LL_PWR_SetWakeUpPinPullUp\n
+  *         WKUPEPR   WKUPPUPD6       LL_PWR_SetWakeUpPinPullUp
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  *         @arg @ref LL_PWR_WAKEUP_PIN6
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetWakeUpPinPullUp(uint32_t WakeUpPin)
+{
+  MODIFY_REG(PWR->WKUPEPR, \
+            (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \
+            (LL_PWR_WAKEUP_PIN_PULLUP << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
+}
+
+/**
+  * @brief  Set the Wake-Up pin Pull Down
+  * @rmtoll WKUPEPR   WKUPPUPD1       LL_PWR_SetWakeUpPinPullDown\n
+  *         WKUPEPR   WKUPPUPD2       LL_PWR_SetWakeUpPinPullDown\n
+  *         WKUPEPR   WKUPPUPD3       LL_PWR_SetWakeUpPinPullDown\n
+  *         WKUPEPR   WKUPPUPD4       LL_PWR_SetWakeUpPinPullDown\n
+  *         WKUPEPR   WKUPPUPD5       LL_PWR_SetWakeUpPinPullDown\n
+  *         WKUPEPR   WKUPPUPD6       LL_PWR_SetWakeUpPinPullDown
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  *         @arg @ref LL_PWR_WAKEUP_PIN6
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetWakeUpPinPullDown(uint32_t WakeUpPin)
+{
+  MODIFY_REG(PWR->WKUPEPR, \
+            (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \
+            (LL_PWR_WAKEUP_PIN_PULLDOWN << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
+}
+
+/**
+  * @brief  Get the Wake-Up pin pull
+  * @rmtoll WKUPEPR   WKUPPUPD1       LL_PWR_GetWakeUpPinPull\n
+  *         WKUPEPR   WKUPPUPD2       LL_PWR_GetWakeUpPinPull\n
+  *         WKUPEPR   WKUPPUPD3       LL_PWR_GetWakeUpPinPull\n
+  *         WKUPEPR   WKUPPUPD4       LL_PWR_GetWakeUpPinPull\n
+  *         WKUPEPR   WKUPPUPD5       LL_PWR_GetWakeUpPinPull\n
+  *         WKUPEPR   WKUPPUPD6       LL_PWR_GetWakeUpPinPull
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2
+  *         @arg @ref LL_PWR_WAKEUP_PIN3
+  *         @arg @ref LL_PWR_WAKEUP_PIN4
+  *         @arg @ref LL_PWR_WAKEUP_PIN5
+  *         @arg @ref LL_PWR_WAKEUP_PIN6
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN_NOPULL
+  *         @arg @ref LL_PWR_WAKEUP_PIN_PULLUP
+  *         @arg @ref LL_PWR_WAKEUP_PIN_PULLDOWN
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinPull(uint32_t WakeUpPin)
+{
+  register uint32_t regValue = READ_BIT(PWR->WKUPEPR, (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
+
+  return (uint32_t)(regValue >> ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Indicate whether VDD voltage is below the selected PVD threshold
+  * @rmtoll CSR1   PVDO       LL_PWR_IsActiveFlag_PVDO
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
+{
+  return ((READ_BIT(PWR->CSR1, PWR_CSR1_PVDO) == (PWR_CSR1_PVDO)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate whether the voltage level is ready for current actual used VOS
+  * @rmtoll CSR1   ACTVOSRDY       LL_PWR_IsActiveFlag_ACTVOS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ACTVOS(void)
+{
+  return ((READ_BIT(PWR->CSR1, PWR_CSR1_ACTVOSRDY) == (PWR_CSR1_ACTVOSRDY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate whether VDDA voltage is below the selected AVD threshold
+  * @rmtoll CSR1   AVDO       LL_PWR_IsActiveFlag_AVDO
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_AVDO(void)
+{
+  return ((READ_BIT(PWR->CSR1, PWR_CSR1_AVDO) == (PWR_CSR1_AVDO)) ? 1UL : 0UL);
+}
+
+#if defined (PWR_CSR1_MMCVDO)
+/**
+  * @brief  Indicate whether VDDMMC voltage is below 1V2
+  * @rmtoll CSR1   MMCVDO     LL_PWR_IsActiveFlag_MMCVDO
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_MMCVDO(void)
+{
+  return ((READ_BIT(PWR->CSR1, PWR_CSR1_MMCVDO) == (PWR_CSR1_MMCVDO)) ? 1UL : 0UL);
+}
+#endif /* PWR_CSR1_MMCVDO */
+
+/**
+  * @brief  Get Backup Regulator ready Flag
+  * @rmtoll CR2   BRRDY       LL_PWR_IsActiveFlag_BRR
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void)
+{
+  return ((READ_BIT(PWR->CR2, PWR_CR2_BRRDY) == (PWR_CR2_BRRDY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate whether the VBAT level is above or below low threshold
+  * @rmtoll CR2   VBATL       LL_PWR_IsActiveFlag_VBATL
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATL(void)
+{
+  return ((READ_BIT(PWR->CR2, PWR_CR2_VBATL) == (PWR_CR2_VBATL)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate whether the VBAT level is above or below high threshold
+  * @rmtoll CR2   VBATH       LL_PWR_IsActiveFlag_VBATH
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATH(void)
+{
+  return ((READ_BIT(PWR->CR2, PWR_CR2_VBATH) == (PWR_CR2_VBATH)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate whether the CPU temperature level is above or below low threshold
+  * @rmtoll CR2   TEMPL       LL_PWR_IsActiveFlag_TEMPL
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPL(void)
+{
+  return ((READ_BIT(PWR->CR2, PWR_CR2_TEMPL) == (PWR_CR2_TEMPL)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicate whether the CPU temperature level is above or below high threshold
+  * @rmtoll CR2   TEMPH       LL_PWR_IsActiveFlag_TEMPH
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPH(void)
+{
+  return ((READ_BIT(PWR->CR2, PWR_CR2_TEMPH) == (PWR_CR2_TEMPH)) ? 1UL : 0UL);
+}
+
+#if defined (SMPS)
+/**
+  * @brief  Indicate whether the SMPS external supply is ready or not
+  * @rmtoll CR3   SMPSEXTRDY       LL_PWR_IsActiveFlag_SMPSEXT
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SMPSEXT(void)
+{
+  return ((READ_BIT(PWR->CR3, PWR_CR3_SMPSEXTRDY) == (PWR_CR3_SMPSEXTRDY)) ? 1UL : 0UL);
+}
+#endif /* SMPS */
+
+/**
+  * @brief  Indicate whether the USB supply is ready or not
+  * @rmtoll CR3   USBRDY       LL_PWR_IsActiveFlag_USB
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_USB(void)
+{
+  return ((READ_BIT(PWR->CR3, PWR_CR3_USB33RDY) == (PWR_CR3_USB33RDY)) ? 1UL : 0UL);
+}
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Get HOLD2 Flag
+  * @rmtoll CPUCR   HOLD2F       LL_PWR_IsActiveFlag_HOLD2
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_HOLD2(void)
+{
+  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2F) == (PWR_CPUCR_HOLD2F)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get HOLD1 Flag
+  * @rmtoll CPU2CR   HOLD1F       LL_PWR_IsActiveFlag_HOLD1
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_HOLD1(void)
+{
+  return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1F) == (PWR_CPU2CR_HOLD1F)) ? 1UL : 0UL);
+}
+#endif /* DUAL_CORE */
+
+/**
+  * @brief  Get CPU System Stop Flag
+  * @rmtoll CPUCR   STOPF       LL_PWR_CPU_IsActiveFlag_STOP
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_STOP(void)
+{
+  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_STOPF) == (PWR_CPUCR_STOPF)) ? 1UL : 0UL);
+}
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Get CPU2 System Stop Flag
+  * @rmtoll CPU2CR   STOPF       LL_PWR_CPU2_IsActiveFlag_STOP
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_STOP(void)
+{
+  return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_STOPF) == (PWR_CPU2CR_STOPF)) ? 1UL : 0UL);
+}
+#endif /* DUAL_CORE */
+
+/**
+  * @brief  Get CPU System Standby Flag
+  * @rmtoll CPUCR   SBF       LL_PWR_CPU_IsActiveFlag_SB
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB(void)
+{
+  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF) == (PWR_CPUCR_SBF)) ? 1UL : 0UL);
+}
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Get CPU2 System Standby Flag
+  * @rmtoll CPU2CR   SBF       LL_PWR_CPU2_IsActiveFlag_SB
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_SB(void)
+{
+  return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF) == (PWR_CPU2CR_SBF)) ? 1UL : 0UL);
+}
+#endif /* DUAL_CORE */
+
+#if defined (PWR_CPUCR_SBF_D1)
+/**
+  * @brief  Get CPU D1 Domain Standby Flag
+  * @rmtoll CPUCR   SBF_D1       LL_PWR_CPU_IsActiveFlag_SB_D1
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB_D1(void)
+{
+  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D1) == (PWR_CPUCR_SBF_D1)) ? 1UL : 0UL);
+}
+#endif /* PWR_CPUCR_SBF_D1 */
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Get CPU2 D1 Domain Standby Flag
+  * @rmtoll CPU2CR   SBF_D1       LL_PWR_CPU2_IsActiveFlag_SB_D1
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_SB_D1(void)
+{
+  return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D1) == (PWR_CPU2CR_SBF_D1)) ? 1UL : 0UL);
+}
+#endif /* DUAL_CORE */
+
+#if defined (PWR_CPUCR_SBF_D2)
+/**
+  * @brief  Get CPU D2 Domain Standby Flag
+  * @rmtoll CPUCR   SBF_D2       LL_PWR_CPU_IsActiveFlag_SB_D2
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB_D2(void)
+{
+  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D2) == (PWR_CPUCR_SBF_D2)) ? 1UL : 0UL);
+}
+#endif /* PWR_CPUCR_SBF_D2 */
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Get CPU2 D2 Domain Standby Flag
+  * @rmtoll CPU2CR   SBF_D2       LL_PWR_CPU2_IsActiveFlag_SB_D2
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_SB_D2(void)
+{
+  return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D2) == (PWR_CPU2CR_SBF_D2)) ? 1UL : 0UL);
+}
+#endif /* DUAL_CORE */
+
+
+/**
+  * @brief  Indicate whether the Regulator is ready in the selected voltage range
+  *         or if its output voltage is still changing to the required voltage level
+  * @rmtoll D3CR   VOSRDY       LL_PWR_IsActiveFlag_VOS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
+{
+#if defined (PWR_CPUCR_PDDS_D2)
+  return ((READ_BIT(PWR->D3CR, PWR_D3CR_VOSRDY) == (PWR_D3CR_VOSRDY)) ? 1UL : 0UL);
+#else
+  return ((READ_BIT(PWR->SRDCR, PWR_SRDCR_VOSRDY) == (PWR_SRDCR_VOSRDY)) ? 1UL : 0UL);
+#endif /* PWR_CPUCR_PDDS_D2 */
+}
+
+/**
+  * @brief  Get Wake-up Flag 6
+  * @rmtoll WKUPFR          WKUPF6          LL_PWR_IsActiveFlag_WU6
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void)
+{
+  return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF6) == (PWR_WKUPFR_WKUPF6)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Wake-up Flag 5
+  * @rmtoll WKUPFR          WKUPF5          LL_PWR_IsActiveFlag_WU5
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
+{
+  return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF5) == (PWR_WKUPFR_WKUPF5)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Wake-up Flag 4
+  * @rmtoll WKUPFR          WKUPF4          LL_PWR_IsActiveFlag_WU4
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
+{
+  return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF4) == (PWR_WKUPFR_WKUPF4)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Wake-up Flag 3
+  * @rmtoll WKUPFR          WKUPF3          LL_PWR_IsActiveFlag_WU3
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
+{
+  return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF3) == (PWR_WKUPFR_WKUPF3)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Wake-up Flag 2
+  * @rmtoll WKUPFR          WKUPF2          LL_PWR_IsActiveFlag_WU2
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
+{
+  return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF2) == (PWR_WKUPFR_WKUPF2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Wake-up Flag 1
+  * @rmtoll WKUPFR          WKUPF1          LL_PWR_IsActiveFlag_WU1
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
+{
+  return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF1) == (PWR_WKUPFR_WKUPF1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear CPU STANDBY, STOP and HOLD flags
+  * @rmtoll CPUCR   CSSF       LL_PWR_ClearFlag_CPU
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_CPU(void)
+{
+  SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF);
+}
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Clear CPU2 STANDBY, STOP and HOLD flags
+  * @rmtoll CPU2CR   CSSF       LL_PWR_ClearFlag_CPU2
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_CPU2(void)
+{
+  SET_BIT(PWR->CPU2CR, PWR_CPU2CR_CSSF);
+}
+#endif /* DUAL_CORE */
+
+/**
+  * @brief  Clear Wake-up Flag 6
+  * @rmtoll WKUPCR          WKUPC6         LL_PWR_ClearFlag_WU6
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU6(void)
+{
+  WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC6);
+}
+
+/**
+  * @brief  Clear Wake-up Flag 5
+  * @rmtoll WKUPCR          WKUPC5         LL_PWR_ClearFlag_WU5
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
+{
+  WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC5);
+}
+
+/**
+  * @brief  Clear Wake-up Flag 4
+  * @rmtoll WKUPCR          WKUPC4         LL_PWR_ClearFlag_WU4
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
+{
+  WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC4);
+}
+
+/**
+  * @brief  Clear Wake-up Flag 3
+  * @rmtoll WKUPCR          WKUPC3         LL_PWR_ClearFlag_WU3
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
+{
+  WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC3);
+}
+
+/**
+  * @brief  Clear Wake-up Flag 2
+  * @rmtoll WKUPCR          WKUPC2         LL_PWR_ClearFlag_WU2
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
+{
+  WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC2);
+}
+
+/**
+  * @brief  Clear Wake-up Flag 1
+  * @rmtoll WKUPCR          WKUPC1         LL_PWR_ClearFlag_WU1
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
+{
+  WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC1);
+}
+
+#if defined (USE_FULL_LL_DRIVER)
+/** @defgroup PWR_LL_EF_Init De-initialization function
+  * @{
+  */
+ErrorStatus LL_PWR_DeInit(void);
+/**
+  * @}
+  */
+#endif /* defined (USE_FULL_LL_DRIVER) */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (PWR) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_LL_PWR_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rcc.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rcc.h
new file mode 100644
index 00000000..2fdd1d02
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rcc.h
@@ -0,0 +1,6326 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_rcc.h
+  * @author  MCD Application Team
+  * @version $VERSION$
+  * @date    $DATE$
+  * @brief   Header file of RCC LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_LL_RCC_H
+#define STM32H7xx_LL_RCC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+#include <math.h>
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined(RCC)
+
+/** @defgroup RCC_LL RCC
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup RCC_LL_Private_Variables RCC Private Variables
+  * @{
+  */
+extern const uint8_t LL_RCC_PrescTable[16];
+
+/**
+  * @}
+  */
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+#if !defined(UNUSED)
+#define UNUSED(x) ((void)(x))
+#endif
+
+/* 32            24           16            8             0
+   --------------------------------------------------------
+   | Mask        | ClkSource   |  Bit       | Register    |
+   |             |  Config     | Position   | Offset      |
+   --------------------------------------------------------*/
+
+#if defined(RCC_VER_2_0)
+/* Clock source register offset Vs CDCCIPR regsiter */
+#define CDCCIP    0x0UL
+#define CDCCIP1   0x4UL
+#define CDCCIP2   0x8UL
+#define SRDCCIP   0xCUL
+#else
+/* Clock source register offset Vs D1CCIPR regsiter */
+#define D1CCIP    0x0UL
+#define D2CCIP1   0x4UL
+#define D2CCIP2   0x8UL
+#define D3CCIP    0xCUL
+#endif /* RCC_VER_2_0 */
+
+#define LL_RCC_REG_SHIFT     0U
+#define LL_RCC_POS_SHIFT     8U
+#define LL_RCC_CONFIG_SHIFT  16U
+#define LL_RCC_MASK_SHIFT    24U
+
+#define LL_CLKSOURCE_SHIFT(__CLKSOURCE__)   (((__CLKSOURCE__) >> LL_RCC_POS_SHIFT   ) & 0x1FUL)
+
+#define LL_CLKSOURCE_MASK(__CLKSOURCE__)   ((((__CLKSOURCE__) >> LL_RCC_MASK_SHIFT  ) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__))
+
+#define LL_CLKSOURCE_CONFIG(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_CONFIG_SHIFT) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__))
+
+#define LL_CLKSOURCE_REG(__CLKSOURCE__)     (((__CLKSOURCE__) >> LL_RCC_REG_SHIFT   ) & 0xFFUL)
+
+#define LL_CLKSOURCE(__REG__, __MSK__, __POS__, __CLK__) ((uint32_t)((((__MSK__) >> (__POS__)) << LL_RCC_MASK_SHIFT) | \
+                                                                     (( __POS__              ) << LL_RCC_POS_SHIFT)  | \
+                                                                     (( __REG__              ) << LL_RCC_REG_SHIFT)  | \
+                                                                     (((__CLK__) >> (__POS__)) << LL_RCC_CONFIG_SHIFT)))
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_Private_Macros RCC Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_Exported_Types RCC Exported Types
+  * @{
+  */
+
+/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
+  * @{
+  */
+
+/**
+  * @brief  RCC Clocks Frequency Structure
+  */
+typedef struct
+{
+  uint32_t SYSCLK_Frequency;
+  uint32_t CPUCLK_Frequency;
+  uint32_t HCLK_Frequency;
+  uint32_t PCLK1_Frequency;
+  uint32_t PCLK2_Frequency;
+  uint32_t PCLK3_Frequency;
+  uint32_t PCLK4_Frequency;
+} LL_RCC_ClocksTypeDef;
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  PLL Clocks Frequency Structure
+  */
+typedef struct
+{
+  uint32_t PLL_P_Frequency;
+  uint32_t PLL_Q_Frequency;
+  uint32_t PLL_R_Frequency;
+} LL_PLL_ClocksTypeDef;
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
+  * @{
+  */
+
+/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
+  * @brief    Defines used to adapt values of different oscillators
+  * @note     These values could be modified in the user environment according to
+  *           HW set-up.
+  * @{
+  */
+#if !defined  (HSE_VALUE)
+#if defined(RCC_VER_X)
+#define HSE_VALUE    25000000U  /*!< Value of the HSE oscillator in Hz */
+#else
+#define HSE_VALUE    24000000U  /*!< Value of the HSE oscillator in Hz */
+#endif /* RCC_VER_X */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    64000000U  /*!< Value of the HSI oscillator in Hz */
+#endif /* HSI_VALUE */
+
+#if !defined  (CSI_VALUE)
+#define CSI_VALUE    4000000U   /*!< Value of the CSI oscillator in Hz */
+#endif /* CSI_VALUE */
+
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U     /*!< Value of the LSE oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined  (LSI_VALUE)
+#define LSI_VALUE    32000U     /*!< Value of the LSI oscillator in Hz */
+#endif /* LSI_VALUE */
+
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+#define EXTERNAL_CLOCK_VALUE    12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+#if !defined  (HSI48_VALUE)
+#define HSI48_VALUE  48000000U  /*!< Value of the HSI48 oscillator in Hz */
+#endif /* HSI48_VALUE */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_HSIDIV  HSI oscillator divider
+  * @{
+  */
+#define LL_RCC_HSI_DIV1                   RCC_CR_HSIDIV_1
+#define LL_RCC_HSI_DIV2                   RCC_CR_HSIDIV_2
+#define LL_RCC_HSI_DIV4                   RCC_CR_HSIDIV_4
+#define LL_RCC_HSI_DIV8                   RCC_CR_HSIDIV_8
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_LSEDRIVE  LSE oscillator drive capability
+  * @{
+  */
+#define LL_RCC_LSEDRIVE_LOW                (uint32_t)(0x00000000U)
+#define LL_RCC_LSEDRIVE_MEDIUMLOW          (uint32_t)(RCC_BDCR_LSEDRV_0)
+#define LL_RCC_LSEDRIVE_MEDIUMHIGH         (uint32_t)(RCC_BDCR_LSEDRV_1)
+#define LL_RCC_LSEDRIVE_HIGH               (uint32_t)(RCC_BDCR_LSEDRV)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SYS_CLKSOURCE  System clock switch
+  * @{
+  */
+#define LL_RCC_SYS_CLKSOURCE_HSI           RCC_CFGR_SW_HSI
+#define LL_RCC_SYS_CLKSOURCE_CSI           RCC_CFGR_SW_CSI
+#define LL_RCC_SYS_CLKSOURCE_HSE           RCC_CFGR_SW_HSE
+#define LL_RCC_SYS_CLKSOURCE_PLL1          RCC_CFGR_SW_PLL1
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS  System clock switch status
+  * @{
+  */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_CSI    RCC_CFGR_SWS_CSI   /*!< CSI used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL1   RCC_CFGR_SWS_PLL1  /*!< PLL1 used as system clock */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SYSWAKEUP_CLKSOURCE  System wakeup clock source
+  * @{
+  */
+#define LL_RCC_SYSWAKEUP_CLKSOURCE_HSI     (uint32_t)(0x00000000U)
+#define LL_RCC_SYSWAKEUP_CLKSOURCE_CSI     (uint32_t)(RCC_CFGR_STOPWUCK)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_KERWAKEUP_CLKSOURCE  Kernel wakeup clock source
+  * @{
+  */
+#define LL_RCC_KERWAKEUP_CLKSOURCE_HSI     (uint32_t)(0x00000000U)
+#define LL_RCC_KERWAKEUP_CLKSOURCE_CSI     (uint32_t)(RCC_CFGR_STOPKERWUCK)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SYSCLK_DIV  System prescaler
+  * @{
+  */
+#if defined(RCC_D1CFGR_D1CPRE_DIV1)
+#define LL_RCC_SYSCLK_DIV_1                RCC_D1CFGR_D1CPRE_DIV1
+#define LL_RCC_SYSCLK_DIV_2                RCC_D1CFGR_D1CPRE_DIV2
+#define LL_RCC_SYSCLK_DIV_4                RCC_D1CFGR_D1CPRE_DIV4
+#define LL_RCC_SYSCLK_DIV_8                RCC_D1CFGR_D1CPRE_DIV8
+#define LL_RCC_SYSCLK_DIV_16               RCC_D1CFGR_D1CPRE_DIV16
+#define LL_RCC_SYSCLK_DIV_64               RCC_D1CFGR_D1CPRE_DIV64
+#define LL_RCC_SYSCLK_DIV_128              RCC_D1CFGR_D1CPRE_DIV128
+#define LL_RCC_SYSCLK_DIV_256              RCC_D1CFGR_D1CPRE_DIV256
+#define LL_RCC_SYSCLK_DIV_512              RCC_D1CFGR_D1CPRE_DIV512
+#else
+#define LL_RCC_SYSCLK_DIV_1                RCC_CDCFGR1_CDCPRE_DIV1
+#define LL_RCC_SYSCLK_DIV_2                RCC_CDCFGR1_CDCPRE_DIV2
+#define LL_RCC_SYSCLK_DIV_4                RCC_CDCFGR1_CDCPRE_DIV4
+#define LL_RCC_SYSCLK_DIV_8                RCC_CDCFGR1_CDCPRE_DIV8
+#define LL_RCC_SYSCLK_DIV_16               RCC_CDCFGR1_CDCPRE_DIV16
+#define LL_RCC_SYSCLK_DIV_64               RCC_CDCFGR1_CDCPRE_DIV64
+#define LL_RCC_SYSCLK_DIV_128              RCC_CDCFGR1_CDCPRE_DIV128
+#define LL_RCC_SYSCLK_DIV_256              RCC_CDCFGR1_CDCPRE_DIV256
+#define LL_RCC_SYSCLK_DIV_512              RCC_CDCFGR1_CDCPRE_DIV512
+#endif /* RCC_D1CFGR_D1CPRE_DIV1 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_AHB_DIV  AHB prescaler
+  * @{
+  */
+#if defined(RCC_D1CFGR_HPRE_DIV1)
+#define LL_RCC_AHB_DIV_1                   RCC_D1CFGR_HPRE_DIV1
+#define LL_RCC_AHB_DIV_2                   RCC_D1CFGR_HPRE_DIV2
+#define LL_RCC_AHB_DIV_4                   RCC_D1CFGR_HPRE_DIV4
+#define LL_RCC_AHB_DIV_8                   RCC_D1CFGR_HPRE_DIV8
+#define LL_RCC_AHB_DIV_16                  RCC_D1CFGR_HPRE_DIV16
+#define LL_RCC_AHB_DIV_64                  RCC_D1CFGR_HPRE_DIV64
+#define LL_RCC_AHB_DIV_128                 RCC_D1CFGR_HPRE_DIV128
+#define LL_RCC_AHB_DIV_256                 RCC_D1CFGR_HPRE_DIV256
+#define LL_RCC_AHB_DIV_512                 RCC_D1CFGR_HPRE_DIV512
+#else
+#define LL_RCC_AHB_DIV_1                   RCC_CDCFGR1_HPRE_DIV1
+#define LL_RCC_AHB_DIV_2                   RCC_CDCFGR1_HPRE_DIV2
+#define LL_RCC_AHB_DIV_4                   RCC_CDCFGR1_HPRE_DIV4
+#define LL_RCC_AHB_DIV_8                   RCC_CDCFGR1_HPRE_DIV8
+#define LL_RCC_AHB_DIV_16                  RCC_CDCFGR1_HPRE_DIV16
+#define LL_RCC_AHB_DIV_64                  RCC_CDCFGR1_HPRE_DIV64
+#define LL_RCC_AHB_DIV_128                 RCC_CDCFGR1_HPRE_DIV128
+#define LL_RCC_AHB_DIV_256                 RCC_CDCFGR1_HPRE_DIV256
+#define LL_RCC_AHB_DIV_512                 RCC_CDCFGR1_HPRE_DIV512
+#endif /* RCC_D1CFGR_HPRE_DIV1 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_APB1_DIV  APB low-speed prescaler (APB1)
+  * @{
+  */
+#if defined(RCC_D2CFGR_D2PPRE1_DIV1)
+#define LL_RCC_APB1_DIV_1                  RCC_D2CFGR_D2PPRE1_DIV1
+#define LL_RCC_APB1_DIV_2                  RCC_D2CFGR_D2PPRE1_DIV2
+#define LL_RCC_APB1_DIV_4                  RCC_D2CFGR_D2PPRE1_DIV4
+#define LL_RCC_APB1_DIV_8                  RCC_D2CFGR_D2PPRE1_DIV8
+#define LL_RCC_APB1_DIV_16                 RCC_D2CFGR_D2PPRE1_DIV16
+#else
+#define LL_RCC_APB1_DIV_1                  RCC_CDCFGR2_CDPPRE1_DIV1
+#define LL_RCC_APB1_DIV_2                  RCC_CDCFGR2_CDPPRE1_DIV2
+#define LL_RCC_APB1_DIV_4                  RCC_CDCFGR2_CDPPRE1_DIV4
+#define LL_RCC_APB1_DIV_8                  RCC_CDCFGR2_CDPPRE1_DIV8
+#define LL_RCC_APB1_DIV_16                 RCC_CDCFGR2_CDPPRE1_DIV16
+#endif /* RCC_D2CFGR_D2PPRE1_DIV1 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_APB2_DIV  APB low-speed prescaler (APB2)
+  * @{
+  */
+#if defined(RCC_D2CFGR_D2PPRE2_DIV1)
+#define LL_RCC_APB2_DIV_1                  RCC_D2CFGR_D2PPRE2_DIV1
+#define LL_RCC_APB2_DIV_2                  RCC_D2CFGR_D2PPRE2_DIV2
+#define LL_RCC_APB2_DIV_4                  RCC_D2CFGR_D2PPRE2_DIV4
+#define LL_RCC_APB2_DIV_8                  RCC_D2CFGR_D2PPRE2_DIV8
+#define LL_RCC_APB2_DIV_16                 RCC_D2CFGR_D2PPRE2_DIV16
+#else
+#define LL_RCC_APB2_DIV_1                  RCC_CDCFGR2_CDPPRE2_DIV1
+#define LL_RCC_APB2_DIV_2                  RCC_CDCFGR2_CDPPRE2_DIV2
+#define LL_RCC_APB2_DIV_4                  RCC_CDCFGR2_CDPPRE2_DIV4
+#define LL_RCC_APB2_DIV_8                  RCC_CDCFGR2_CDPPRE2_DIV8
+#define LL_RCC_APB2_DIV_16                 RCC_CDCFGR2_CDPPRE2_DIV16
+#endif /* RCC_D2CFGR_D2PPRE2_DIV1 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_APB3_DIV  APB low-speed prescaler (APB3)
+  * @{
+  */
+#if defined(RCC_D1CFGR_D1PPRE_DIV1)
+#define LL_RCC_APB3_DIV_1                  RCC_D1CFGR_D1PPRE_DIV1
+#define LL_RCC_APB3_DIV_2                  RCC_D1CFGR_D1PPRE_DIV2
+#define LL_RCC_APB3_DIV_4                  RCC_D1CFGR_D1PPRE_DIV4
+#define LL_RCC_APB3_DIV_8                  RCC_D1CFGR_D1PPRE_DIV8
+#define LL_RCC_APB3_DIV_16                 RCC_D1CFGR_D1PPRE_DIV16
+#else
+#define LL_RCC_APB3_DIV_1                  RCC_CDCFGR1_CDPPRE_DIV1
+#define LL_RCC_APB3_DIV_2                  RCC_CDCFGR1_CDPPRE_DIV2
+#define LL_RCC_APB3_DIV_4                  RCC_CDCFGR1_CDPPRE_DIV4
+#define LL_RCC_APB3_DIV_8                  RCC_CDCFGR1_CDPPRE_DIV8
+#define LL_RCC_APB3_DIV_16                 RCC_CDCFGR1_CDPPRE_DIV16
+#endif /* RCC_D1CFGR_D1PPRE_DIV1 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_APB4_DIV  APB low-speed prescaler (APB4)
+  * @{
+  */
+#if defined(RCC_D3CFGR_D3PPRE_DIV1)
+#define LL_RCC_APB4_DIV_1                  RCC_D3CFGR_D3PPRE_DIV1
+#define LL_RCC_APB4_DIV_2                  RCC_D3CFGR_D3PPRE_DIV2
+#define LL_RCC_APB4_DIV_4                  RCC_D3CFGR_D3PPRE_DIV4
+#define LL_RCC_APB4_DIV_8                  RCC_D3CFGR_D3PPRE_DIV8
+#define LL_RCC_APB4_DIV_16                 RCC_D3CFGR_D3PPRE_DIV16
+#else
+#define LL_RCC_APB4_DIV_1                  RCC_SRDCFGR_SRDPPRE_DIV1
+#define LL_RCC_APB4_DIV_2                  RCC_SRDCFGR_SRDPPRE_DIV2
+#define LL_RCC_APB4_DIV_4                  RCC_SRDCFGR_SRDPPRE_DIV4
+#define LL_RCC_APB4_DIV_8                  RCC_SRDCFGR_SRDPPRE_DIV8
+#define LL_RCC_APB4_DIV_16                 RCC_SRDCFGR_SRDPPRE_DIV16
+#endif /* RCC_D3CFGR_D3PPRE_DIV1 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_MCOxSOURCE  MCO source selection
+  * @{
+  */
+#define LL_RCC_MCO1SOURCE_HSI              (uint32_t)((RCC_CFGR_MCO1>>16U) | 0x00000000U)
+#define LL_RCC_MCO1SOURCE_LSE              (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_0)
+#define LL_RCC_MCO1SOURCE_HSE              (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_1)
+#define LL_RCC_MCO1SOURCE_PLL1QCLK         (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0)
+#define LL_RCC_MCO1SOURCE_HSI48            (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_2)
+#define LL_RCC_MCO2SOURCE_SYSCLK           (uint32_t)((RCC_CFGR_MCO2>>16U) | 0x00000000U)
+#define LL_RCC_MCO2SOURCE_PLL2PCLK         (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_0)
+#define LL_RCC_MCO2SOURCE_HSE              (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_1)
+#define LL_RCC_MCO2SOURCE_PLL1PCLK         (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0)
+#define LL_RCC_MCO2SOURCE_CSI              (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_2)
+#define LL_RCC_MCO2SOURCE_LSI              (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_2|RCC_CFGR_MCO2_0)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_MCOx_DIV  MCO prescaler
+  * @{
+  */
+#define LL_RCC_MCO1_DIV_1                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0)
+#define LL_RCC_MCO1_DIV_2                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1)
+#define LL_RCC_MCO1_DIV_3                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1)
+#define LL_RCC_MCO1_DIV_4                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2)
+#define LL_RCC_MCO1_DIV_5                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
+#define LL_RCC_MCO1_DIV_6                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
+#define LL_RCC_MCO1_DIV_7                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
+#define LL_RCC_MCO1_DIV_8                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_3)
+#define LL_RCC_MCO1_DIV_9                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_3)
+#define LL_RCC_MCO1_DIV_10                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
+#define LL_RCC_MCO1_DIV_11                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
+#define LL_RCC_MCO1_DIV_12                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
+#define LL_RCC_MCO1_DIV_13                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
+#define LL_RCC_MCO1_DIV_14                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
+#define LL_RCC_MCO1_DIV_15                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE)
+#define LL_RCC_MCO2_DIV_1                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0)
+#define LL_RCC_MCO2_DIV_2                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1)
+#define LL_RCC_MCO2_DIV_3                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1)
+#define LL_RCC_MCO2_DIV_4                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2)
+#define LL_RCC_MCO2_DIV_5                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_2)
+#define LL_RCC_MCO2_DIV_6                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2)
+#define LL_RCC_MCO2_DIV_7                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2)
+#define LL_RCC_MCO2_DIV_8                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_3)
+#define LL_RCC_MCO2_DIV_9                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_3)
+#define LL_RCC_MCO2_DIV_10                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_3)
+#define LL_RCC_MCO2_DIV_11                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_3)
+#define LL_RCC_MCO2_DIV_12                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3)
+#define LL_RCC_MCO2_DIV_13                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3)
+#define LL_RCC_MCO2_DIV_14                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3)
+#define LL_RCC_MCO2_DIV_15                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_RTC_HSEDIV  HSE prescaler for RTC clock
+  * @{
+  */
+#define LL_RCC_RTC_NOCLOCK                  (uint32_t)(0x00000000U)
+#define LL_RCC_RTC_HSE_DIV_2                (uint32_t)(RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_3                (uint32_t)(RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_4                (uint32_t)(RCC_CFGR_RTCPRE_2)
+#define LL_RCC_RTC_HSE_DIV_5                (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_6                (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_7                (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_8                (uint32_t)(RCC_CFGR_RTCPRE_3)
+#define LL_RCC_RTC_HSE_DIV_9                (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_10               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_11               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_12               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
+#define LL_RCC_RTC_HSE_DIV_13               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_14               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_15               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_16               (uint32_t)(RCC_CFGR_RTCPRE_4)
+#define LL_RCC_RTC_HSE_DIV_17               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_18               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_19               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_20               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2)
+#define LL_RCC_RTC_HSE_DIV_21               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_22               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_23               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_24               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3)
+#define LL_RCC_RTC_HSE_DIV_25               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_26               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_27               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_28               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
+#define LL_RCC_RTC_HSE_DIV_29               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_30               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_31               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_32               (uint32_t)(RCC_CFGR_RTCPRE_5)
+#define LL_RCC_RTC_HSE_DIV_33               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_34               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_35               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_36               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2)
+#define LL_RCC_RTC_HSE_DIV_37               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_38               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_39               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_40               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3)
+#define LL_RCC_RTC_HSE_DIV_41               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_42               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_43               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_44               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
+#define LL_RCC_RTC_HSE_DIV_45               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_46               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_47               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_48               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4)
+#define LL_RCC_RTC_HSE_DIV_49               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_50               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_51               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_52               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2)
+#define LL_RCC_RTC_HSE_DIV_53               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_54               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_55               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_56               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3)
+#define LL_RCC_RTC_HSE_DIV_57               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_58               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_59               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_60               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
+#define LL_RCC_RTC_HSE_DIV_61               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
+#define LL_RCC_RTC_HSE_DIV_62               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
+#define LL_RCC_RTC_HSE_DIV_63               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_USARTx_CLKSOURCE  Peripheral USART clock source selection
+  * @{
+  */
+#if defined(RCC_D2CCIP2R_USART16SEL)
+#define LL_RCC_USART16_CLKSOURCE_PCLK2         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, 0x00000000U)
+#define LL_RCC_USART16_CLKSOURCE_PLL2Q         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0)
+#define LL_RCC_USART16_CLKSOURCE_PLL3Q         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_1)
+#define LL_RCC_USART16_CLKSOURCE_HSI           LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_1)
+#define LL_RCC_USART16_CLKSOURCE_CSI           LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_2)
+#define LL_RCC_USART16_CLKSOURCE_LSE           LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_2)
+#else
+#define LL_RCC_USART16910_CLKSOURCE_PCLK2      LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, 0x00000000U)
+#define LL_RCC_USART16910_CLKSOURCE_PLL2Q      LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0)
+#define LL_RCC_USART16910_CLKSOURCE_PLL3Q      LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_1)
+#define LL_RCC_USART16910_CLKSOURCE_HSI        LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_1)
+#define LL_RCC_USART16910_CLKSOURCE_CSI        LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_2)
+#define LL_RCC_USART16910_CLKSOURCE_LSE        LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_2)
+/*  Aliases */
+#define LL_RCC_USART16_CLKSOURCE_PCLK2         LL_RCC_USART16910_CLKSOURCE_PCLK2
+#define LL_RCC_USART16_CLKSOURCE_PLL2Q         LL_RCC_USART16910_CLKSOURCE_PLL2Q
+#define LL_RCC_USART16_CLKSOURCE_PLL3Q         LL_RCC_USART16910_CLKSOURCE_PLL3Q
+#define LL_RCC_USART16_CLKSOURCE_HSI           LL_RCC_USART16910_CLKSOURCE_HSI
+#define LL_RCC_USART16_CLKSOURCE_CSI           LL_RCC_USART16910_CLKSOURCE_CSI
+#define LL_RCC_USART16_CLKSOURCE_LSE           LL_RCC_USART16910_CLKSOURCE_LSE
+#endif  /* RCC_D2CCIP2R_USART16SEL */
+#if defined(RCC_D2CCIP2R_USART28SEL)
+#define LL_RCC_USART234578_CLKSOURCE_PCLK1     LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, 0x00000000U)
+#define LL_RCC_USART234578_CLKSOURCE_PLL2Q     LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0)
+#define LL_RCC_USART234578_CLKSOURCE_PLL3Q     LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_1)
+#define LL_RCC_USART234578_CLKSOURCE_HSI       LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)
+#define LL_RCC_USART234578_CLKSOURCE_CSI       LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_2)
+#define LL_RCC_USART234578_CLKSOURCE_LSE       LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)
+#else
+#define LL_RCC_USART234578_CLKSOURCE_PCLK1     LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, 0x00000000U)
+#define LL_RCC_USART234578_CLKSOURCE_PLL2Q     LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0)
+#define LL_RCC_USART234578_CLKSOURCE_PLL3Q     LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_1)
+#define LL_RCC_USART234578_CLKSOURCE_HSI       LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_1)
+#define LL_RCC_USART234578_CLKSOURCE_CSI       LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_2)
+#define LL_RCC_USART234578_CLKSOURCE_LSE       LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_2)
+#endif /* RCC_D2CCIP2R_USART28SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_LPUARTx_CLKSOURCE  Peripheral LPUART clock source selection
+  * @{
+  */
+#if defined(RCC_D3CCIPR_LPUART1SEL)
+#define LL_RCC_LPUART1_CLKSOURCE_PCLK4         (0x00000000U)
+#define LL_RCC_LPUART1_CLKSOURCE_PLL2Q         (RCC_D3CCIPR_LPUART1SEL_0)
+#define LL_RCC_LPUART1_CLKSOURCE_PLL3Q         (RCC_D3CCIPR_LPUART1SEL_1)
+#define LL_RCC_LPUART1_CLKSOURCE_HSI           (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_1)
+#define LL_RCC_LPUART1_CLKSOURCE_CSI           (RCC_D3CCIPR_LPUART1SEL_2)
+#define LL_RCC_LPUART1_CLKSOURCE_LSE           (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_2)
+#else
+#define LL_RCC_LPUART1_CLKSOURCE_PCLK4         (0x00000000U)
+#define LL_RCC_LPUART1_CLKSOURCE_PLL2Q         (RCC_SRDCCIPR_LPUART1SEL_0)
+#define LL_RCC_LPUART1_CLKSOURCE_PLL3Q         (RCC_SRDCCIPR_LPUART1SEL_1)
+#define LL_RCC_LPUART1_CLKSOURCE_HSI           (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_1)
+#define LL_RCC_LPUART1_CLKSOURCE_CSI           (RCC_SRDCCIPR_LPUART1SEL_2)
+#define LL_RCC_LPUART1_CLKSOURCE_LSE           (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_2)
+#endif /* RCC_D3CCIPR_LPUART1SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE  Peripheral I2C clock source selection
+  * @{
+  */
+#if defined (RCC_D2CCIP2R_I2C123SEL)
+#define LL_RCC_I2C123_CLKSOURCE_PCLK1          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, 0x00000000U)
+#define LL_RCC_I2C123_CLKSOURCE_PLL3R          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_0)
+#define LL_RCC_I2C123_CLKSOURCE_HSI            LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_1)
+#define LL_RCC_I2C123_CLKSOURCE_CSI            LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1)
+#else
+#define LL_RCC_I2C123_CLKSOURCE_PCLK1          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, 0x00000000U)
+#define LL_RCC_I2C123_CLKSOURCE_PLL3R          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_0)
+#define LL_RCC_I2C123_CLKSOURCE_HSI            LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_1)
+#define LL_RCC_I2C123_CLKSOURCE_CSI            LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_0 | RCC_CDCCIP2R_I2C123SEL_1)
+#endif /* RCC_D2CCIP2R_I2C123SEL */
+#if defined (RCC_D3CCIPR_I2C4SEL)
+#define LL_RCC_I2C4_CLKSOURCE_PCLK4            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_I2C4SEL,    RCC_D3CCIPR_I2C4SEL_Pos,    0x00000000U)
+#define LL_RCC_I2C4_CLKSOURCE_PLL3R            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_I2C4SEL,    RCC_D3CCIPR_I2C4SEL_Pos,    RCC_D3CCIPR_I2C4SEL_0)
+#define LL_RCC_I2C4_CLKSOURCE_HSI              LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_I2C4SEL,    RCC_D3CCIPR_I2C4SEL_Pos,    RCC_D3CCIPR_I2C4SEL_1)
+#define LL_RCC_I2C4_CLKSOURCE_CSI              LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_I2C4SEL,    RCC_D3CCIPR_I2C4SEL_Pos,    RCC_D3CCIPR_I2C4SEL_0 | RCC_D3CCIPR_I2C4SEL_1)
+#else
+#define LL_RCC_I2C4_CLKSOURCE_PCLK4            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_I2C4SEL,    RCC_SRDCCIPR_I2C4SEL_Pos,    0x00000000U)
+#define LL_RCC_I2C4_CLKSOURCE_PLL3R            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_I2C4SEL,    RCC_SRDCCIPR_I2C4SEL_Pos,    RCC_SRDCCIPR_I2C4SEL_0)
+#define LL_RCC_I2C4_CLKSOURCE_HSI              LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_I2C4SEL,    RCC_SRDCCIPR_I2C4SEL_Pos,    RCC_SRDCCIPR_I2C4SEL_1)
+#define LL_RCC_I2C4_CLKSOURCE_CSI              LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_I2C4SEL,    RCC_SRDCCIPR_I2C4SEL_Pos,    RCC_SRDCCIPR_I2C4SEL_0 | RCC_SRDCCIPR_I2C4SEL_1)
+#endif /* RCC_D3CCIPR_I2C4SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_LPTIMx_CLKSOURCE  Peripheral LPTIM clock source selection
+  * @{
+  */
+#if defined(RCC_D2CCIP2R_LPTIM1SEL)
+#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  0x00000000U)
+#define LL_RCC_LPTIM1_CLKSOURCE_PLL2P          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  RCC_D2CCIP2R_LPTIM1SEL_0)
+#define LL_RCC_LPTIM1_CLKSOURCE_PLL3R          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  RCC_D2CCIP2R_LPTIM1SEL_1)
+#define LL_RCC_LPTIM1_CLKSOURCE_LSE            LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_1)
+#define LL_RCC_LPTIM1_CLKSOURCE_LSI            LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  RCC_D2CCIP2R_LPTIM1SEL_2)
+#define LL_RCC_LPTIM1_CLKSOURCE_CLKP           LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_2)
+#else
+#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  0x00000000U)
+#define LL_RCC_LPTIM1_CLKSOURCE_PLL2P          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  RCC_CDCCIP2R_LPTIM1SEL_0)
+#define LL_RCC_LPTIM1_CLKSOURCE_PLL3R          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  RCC_CDCCIP2R_LPTIM1SEL_1)
+#define LL_RCC_LPTIM1_CLKSOURCE_LSE            LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_1)
+#define LL_RCC_LPTIM1_CLKSOURCE_LSI            LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  RCC_CDCCIP2R_LPTIM1SEL_2)
+#define LL_RCC_LPTIM1_CLKSOURCE_CLKP           LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_2)
+#endif /* RCC_D2CCIP2R_LPTIM1SEL */
+#if defined(RCC_D3CCIPR_LPTIM2SEL)
+#define LL_RCC_LPTIM2_CLKSOURCE_PCLK4          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   0x00000000U)
+#define LL_RCC_LPTIM2_CLKSOURCE_PLL2P          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   RCC_D3CCIPR_LPTIM2SEL_0)
+#define LL_RCC_LPTIM2_CLKSOURCE_PLL3R          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   RCC_D3CCIPR_LPTIM2SEL_1)
+#define LL_RCC_LPTIM2_CLKSOURCE_LSE            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_1)
+#define LL_RCC_LPTIM2_CLKSOURCE_LSI            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   RCC_D3CCIPR_LPTIM2SEL_2)
+#define LL_RCC_LPTIM2_CLKSOURCE_CLKP           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_2)
+#else
+#define LL_RCC_LPTIM2_CLKSOURCE_PCLK4          LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   0x00000000U)
+#define LL_RCC_LPTIM2_CLKSOURCE_PLL2P          LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   RCC_SRDCCIPR_LPTIM2SEL_0)
+#define LL_RCC_LPTIM2_CLKSOURCE_PLL3R          LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   RCC_SRDCCIPR_LPTIM2SEL_1)
+#define LL_RCC_LPTIM2_CLKSOURCE_LSE            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_1)
+#define LL_RCC_LPTIM2_CLKSOURCE_LSI            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   RCC_SRDCCIPR_LPTIM2SEL_2)
+#define LL_RCC_LPTIM2_CLKSOURCE_CLKP           LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_2)
+#endif /* RCC_D3CCIPR_LPTIM2SEL */
+#if defined(RCC_D3CCIPR_LPTIM345SEL)
+#define LL_RCC_LPTIM345_CLKSOURCE_PCLK4        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, 0x00000000U)
+#define LL_RCC_LPTIM345_CLKSOURCE_PLL2P        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0)
+#define LL_RCC_LPTIM345_CLKSOURCE_PLL3R        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_1)
+#define LL_RCC_LPTIM345_CLKSOURCE_LSE          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1)
+#define LL_RCC_LPTIM345_CLKSOURCE_LSI          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_2)
+#define LL_RCC_LPTIM345_CLKSOURCE_CLKP         LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2)
+#else
+#define LL_RCC_LPTIM345_CLKSOURCE_PCLK4        LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, 0x00000000U)
+#define LL_RCC_LPTIM345_CLKSOURCE_PLL2P        LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0)
+#define LL_RCC_LPTIM345_CLKSOURCE_PLL3R        LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_1)
+#define LL_RCC_LPTIM345_CLKSOURCE_LSE          LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_1)
+#define LL_RCC_LPTIM345_CLKSOURCE_LSI          LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_2)
+#define LL_RCC_LPTIM345_CLKSOURCE_CLKP         LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_2)
+/* aliases*/
+#define LL_RCC_LPTIM3_CLKSOURCE_PCLK4          LL_RCC_LPTIM345_CLKSOURCE_PCLK4
+#define LL_RCC_LPTIM3_CLKSOURCE_PLL2P          LL_RCC_LPTIM345_CLKSOURCE_PLL2P
+#define LL_RCC_LPTIM3_CLKSOURCE_PLL3R          LL_RCC_LPTIM345_CLKSOURCE_PLL3R
+#define LL_RCC_LPTIM3_CLKSOURCE_LSE            LL_RCC_LPTIM345_CLKSOURCE_LSE
+#define LL_RCC_LPTIM3_CLKSOURCE_LSI            LL_RCC_LPTIM345_CLKSOURCE_LSI
+#define LL_RCC_LPTIM3_CLKSOURCE_CLKP           LL_RCC_LPTIM345_CLKSOURCE_CLKP
+#endif /* RCC_D3CCIPR_LPTIM345SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SAIx_CLKSOURCE  Peripheral SAI clock source selection
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_SAI1SEL)
+#define LL_RCC_SAI1_CLKSOURCE_PLL1Q            LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  0x00000000U)
+#define LL_RCC_SAI1_CLKSOURCE_PLL2P            LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  RCC_D2CCIP1R_SAI1SEL_0)
+#define LL_RCC_SAI1_CLKSOURCE_PLL3P            LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  RCC_D2CCIP1R_SAI1SEL_1)
+#define LL_RCC_SAI1_CLKSOURCE_I2S_CKIN         LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  RCC_D2CCIP1R_SAI1SEL_0 | RCC_D2CCIP1R_SAI1SEL_1)
+#define LL_RCC_SAI1_CLKSOURCE_CLKP             LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  RCC_D2CCIP1R_SAI1SEL_2)
+#else
+#define LL_RCC_SAI1_CLKSOURCE_PLL1Q            LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  0x00000000U)
+#define LL_RCC_SAI1_CLKSOURCE_PLL2P            LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  RCC_CDCCIP1R_SAI1SEL_0)
+#define LL_RCC_SAI1_CLKSOURCE_PLL3P            LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  RCC_CDCCIP1R_SAI1SEL_1)
+#define LL_RCC_SAI1_CLKSOURCE_I2S_CKIN         LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  RCC_CDCCIP1R_SAI1SEL_0 | RCC_CDCCIP1R_SAI1SEL_1)
+#define LL_RCC_SAI1_CLKSOURCE_CLKP             LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  RCC_CDCCIP1R_SAI1SEL_2)
+#endif
+#if defined(SAI3)
+#define LL_RCC_SAI23_CLKSOURCE_PLL1Q           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, 0x00000000U)
+#define LL_RCC_SAI23_CLKSOURCE_PLL2P           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_0)
+#define LL_RCC_SAI23_CLKSOURCE_PLL3P           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_1)
+#define LL_RCC_SAI23_CLKSOURCE_I2S_CKIN        LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1)
+#define LL_RCC_SAI23_CLKSOURCE_CLKP            LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_2)
+#endif /* SAI3 */
+#if defined(RCC_CDCCIP1R_SAI2ASEL)
+#define LL_RCC_SAI2A_CLKSOURCE_PLL1Q           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  0x00000000U)
+#define LL_RCC_SAI2A_CLKSOURCE_PLL2P           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  RCC_CDCCIP1R_SAI2ASEL_0)
+#define LL_RCC_SAI2A_CLKSOURCE_PLL3P           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  RCC_CDCCIP1R_SAI2ASEL_1)
+#define LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN        LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_1)
+#define LL_RCC_SAI2A_CLKSOURCE_CLKP            LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  RCC_CDCCIP1R_SAI2ASEL_2)
+#define LL_RCC_SAI2A_CLKSOURCE_SPDIF           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_2)
+#endif /* RCC_CDCCIP1R_SAI2ASEL */
+#if defined(RCC_CDCCIP1R_SAI2BSEL)
+#define LL_RCC_SAI2B_CLKSOURCE_PLL1Q           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  0x00000000U)
+#define LL_RCC_SAI2B_CLKSOURCE_PLL2P           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  RCC_CDCCIP1R_SAI2BSEL_0)
+#define LL_RCC_SAI2B_CLKSOURCE_PLL3P           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  RCC_CDCCIP1R_SAI2BSEL_1)
+#define LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN        LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_1)
+#define LL_RCC_SAI2B_CLKSOURCE_CLKP            LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  RCC_CDCCIP1R_SAI2BSEL_2)
+#define LL_RCC_SAI2B_CLKSOURCE_SPDIF           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_2)
+#endif /* RCC_CDCCIP1R_SAI2BSEL */
+#if defined(SAI4_Block_A)
+#define LL_RCC_SAI4A_CLKSOURCE_PLL1Q           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  0x00000000U)
+#define LL_RCC_SAI4A_CLKSOURCE_PLL2P           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  RCC_D3CCIPR_SAI4ASEL_0)
+#define LL_RCC_SAI4A_CLKSOURCE_PLL3P           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  RCC_D3CCIPR_SAI4ASEL_1)
+#define LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1)
+#define LL_RCC_SAI4A_CLKSOURCE_CLKP            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  RCC_D3CCIPR_SAI4ASEL_2)
+#endif /* SAI4_Block_A */
+#if defined(SAI4_Block_B)
+#define LL_RCC_SAI4B_CLKSOURCE_PLL1Q           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  0x00000000U)
+#define LL_RCC_SAI4B_CLKSOURCE_PLL2P           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  RCC_D3CCIPR_SAI4BSEL_0)
+#define LL_RCC_SAI4B_CLKSOURCE_PLL3P           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  RCC_D3CCIPR_SAI4BSEL_1)
+#define LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1)
+#define LL_RCC_SAI4B_CLKSOURCE_CLKP            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  RCC_D3CCIPR_SAI4BSEL_2)
+#endif /* SAI4_Block_B */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SDMMC_CLKSOURCE  Peripheral SDMMC clock source selection
+  * @{
+  */
+#if defined(RCC_D1CCIPR_SDMMCSEL)
+#define LL_RCC_SDMMC_CLKSOURCE_PLL1Q           (0x00000000U)
+#define LL_RCC_SDMMC_CLKSOURCE_PLL2R           (RCC_D1CCIPR_SDMMCSEL)
+#else
+#define LL_RCC_SDMMC_CLKSOURCE_PLL1Q           (0x00000000U)
+#define LL_RCC_SDMMC_CLKSOURCE_PLL2R           (RCC_CDCCIPR_SDMMCSEL)
+#endif /* RCC_D1CCIPR_SDMMCSEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_RNG_CLKSOURCE  Peripheral RNG clock source selection
+  * @{
+  */
+#if defined(RCC_D2CCIP2R_RNGSEL)
+#define LL_RCC_RNG_CLKSOURCE_HSI48             (0x00000000U)
+#define LL_RCC_RNG_CLKSOURCE_PLL1Q             (RCC_D2CCIP2R_RNGSEL_0)
+#define LL_RCC_RNG_CLKSOURCE_LSE               (RCC_D2CCIP2R_RNGSEL_1)
+#define LL_RCC_RNG_CLKSOURCE_LSI               (RCC_D2CCIP2R_RNGSEL_1 | RCC_D2CCIP2R_RNGSEL_0)
+#else
+#define LL_RCC_RNG_CLKSOURCE_HSI48             (0x00000000U)
+#define LL_RCC_RNG_CLKSOURCE_PLL1Q             (RCC_CDCCIP2R_RNGSEL_0)
+#define LL_RCC_RNG_CLKSOURCE_LSE               (RCC_CDCCIP2R_RNGSEL_1)
+#define LL_RCC_RNG_CLKSOURCE_LSI               (RCC_CDCCIP2R_RNGSEL_1 | RCC_CDCCIP2R_RNGSEL_0)
+#endif /* RCC_D2CCIP2R_RNGSEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_USB_CLKSOURCE  Peripheral USB clock source selection
+  * @{
+  */
+#if defined(RCC_D2CCIP2R_USBSEL)
+#define LL_RCC_USB_CLKSOURCE_DISABLE           (0x00000000U)
+#define LL_RCC_USB_CLKSOURCE_PLL1Q             (RCC_D2CCIP2R_USBSEL_0)
+#define LL_RCC_USB_CLKSOURCE_PLL3Q             (RCC_D2CCIP2R_USBSEL_1)
+#define LL_RCC_USB_CLKSOURCE_HSI48             (RCC_D2CCIP2R_USBSEL_1 | RCC_D2CCIP2R_USBSEL_0)
+#else
+#define LL_RCC_USB_CLKSOURCE_DISABLE           (0x00000000U)
+#define LL_RCC_USB_CLKSOURCE_PLL1Q             (RCC_CDCCIP2R_USBSEL_0)
+#define LL_RCC_USB_CLKSOURCE_PLL3Q             (RCC_CDCCIP2R_USBSEL_1)
+#define LL_RCC_USB_CLKSOURCE_HSI48             (RCC_CDCCIP2R_USBSEL_1 | RCC_CDCCIP2R_USBSEL_0)
+#endif /* RCC_D2CCIP2R_USBSEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_CEC_CLKSOURCE  Peripheral CEC clock source selection
+  * @{
+  */
+#if defined(RCC_D2CCIP2R_CECSEL)
+#define LL_RCC_CEC_CLKSOURCE_LSE               (0x00000000U)
+#define LL_RCC_CEC_CLKSOURCE_LSI               (RCC_D2CCIP2R_CECSEL_0)
+#define LL_RCC_CEC_CLKSOURCE_CSI_DIV122        (RCC_D2CCIP2R_CECSEL_1)
+#else
+#define LL_RCC_CEC_CLKSOURCE_LSE               (0x00000000U)
+#define LL_RCC_CEC_CLKSOURCE_LSI               (RCC_CDCCIP2R_CECSEL_0)
+#define LL_RCC_CEC_CLKSOURCE_CSI_DIV122        (RCC_CDCCIP2R_CECSEL_1)
+#endif
+/**
+  * @}
+  */
+
+#if defined(DSI)
+/** @defgroup RCC_LL_EC_DSI_CLKSOURCE  Peripheral DSI clock source selection
+  * @{
+  */
+#define LL_RCC_DSI_CLKSOURCE_PHY               (0x00000000U)
+#define LL_RCC_DSI_CLKSOURCE_PLL2Q             (RCC_D1CCIPR_DSISEL)
+/**
+  * @}
+  */
+#endif /* DSI */
+
+/** @defgroup RCC_LL_EC_DFSDM_CLKSOURCE  Peripheral DFSDM clock source selection
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_DFSDM1SEL)
+#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2          (0x00000000U)
+#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK         (RCC_D2CCIP1R_DFSDM1SEL)
+#else
+#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2          (0x00000000U)
+#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK         (RCC_CDCCIP1R_DFSDM1SEL)
+#endif /* RCC_D2CCIP1R_DFSDM1SEL */
+/**
+  * @}
+  */
+
+#if defined(DFSDM2_BASE)
+/** @defgroup RCC_LL_EC_DFSDM2_CLKSOURCE  Peripheral DFSDM2 clock source selection
+  * @{
+  */
+#define LL_RCC_DFSDM2_CLKSOURCE_PCLK4          (0x00000000U)
+#define LL_RCC_DFSDM2_CLKSOURCE_SYSCLK         (RCC_SRDCCIPR_DFSDM2SEL)
+/**
+  * @}
+  */
+#endif /* DFSDM2_BASE */
+
+/** @defgroup RCC_LL_EC_FMC_CLKSOURCE  Peripheral FMC clock source selection
+  * @{
+  */
+#if defined(RCC_D1CCIPR_FMCSEL)
+#define LL_RCC_FMC_CLKSOURCE_HCLK              (0x00000000U)
+#define LL_RCC_FMC_CLKSOURCE_PLL1Q             (RCC_D1CCIPR_FMCSEL_0)
+#define LL_RCC_FMC_CLKSOURCE_PLL2R             (RCC_D1CCIPR_FMCSEL_1)
+#define LL_RCC_FMC_CLKSOURCE_CLKP              (RCC_D1CCIPR_FMCSEL_0 | RCC_D1CCIPR_FMCSEL_1)
+#else
+#define LL_RCC_FMC_CLKSOURCE_HCLK              (0x00000000U)
+#define LL_RCC_FMC_CLKSOURCE_PLL1Q             (RCC_CDCCIPR_FMCSEL_0)
+#define LL_RCC_FMC_CLKSOURCE_PLL2R             (RCC_CDCCIPR_FMCSEL_1)
+#define LL_RCC_FMC_CLKSOURCE_CLKP              (RCC_CDCCIPR_FMCSEL_0 | RCC_CDCCIPR_FMCSEL_1)
+#endif /* RCC_D1CCIPR_FMCSEL */
+/**
+  * @}
+  */
+
+#if defined(QUADSPI)
+/** @defgroup RCC_LL_EC_QSPI_CLKSOURCE  Peripheral QSPI clock source selection
+  * @{
+  */
+#define LL_RCC_QSPI_CLKSOURCE_HCLK             (0x00000000U)
+#define LL_RCC_QSPI_CLKSOURCE_PLL1Q            (RCC_D1CCIPR_QSPISEL_0)
+#define LL_RCC_QSPI_CLKSOURCE_PLL2R            (RCC_D1CCIPR_QSPISEL_1)
+#define LL_RCC_QSPI_CLKSOURCE_CLKP             (RCC_D1CCIPR_QSPISEL_0 | RCC_D1CCIPR_QSPISEL_1)
+/**
+  * @}
+  */
+#endif /* QUADSPI */
+
+
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+/** @defgroup RCC_LL_EC_OSPI_CLKSOURCE  Peripheral OSPI clock source selection
+  * @{
+  */
+#define LL_RCC_OSPI_CLKSOURCE_HCLK             (0x00000000U)
+#define LL_RCC_OSPI_CLKSOURCE_PLL1Q            (RCC_CDCCIPR_OCTOSPISEL_0)
+#define LL_RCC_OSPI_CLKSOURCE_PLL2R            (RCC_CDCCIPR_OCTOSPISEL_1)
+#define LL_RCC_OSPI_CLKSOURCE_CLKP             (RCC_CDCCIPR_OCTOSPISEL_0 | RCC_CDCCIPR_OCTOSPISEL_1)
+/**
+  * @}
+  */
+#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
+
+
+/** @defgroup RCC_LL_EC_CLKP_CLKSOURCE  Peripheral CLKP clock source selection
+  * @{
+  */
+#if defined(RCC_D1CCIPR_CKPERSEL)
+#define LL_RCC_CLKP_CLKSOURCE_HSI              (0x00000000U)
+#define LL_RCC_CLKP_CLKSOURCE_CSI              (RCC_D1CCIPR_CKPERSEL_0)
+#define LL_RCC_CLKP_CLKSOURCE_HSE              (RCC_D1CCIPR_CKPERSEL_1)
+#else
+#define LL_RCC_CLKP_CLKSOURCE_HSI              (0x00000000U)
+#define LL_RCC_CLKP_CLKSOURCE_CSI              (RCC_CDCCIPR_CKPERSEL_0)
+#define LL_RCC_CLKP_CLKSOURCE_HSE              (RCC_CDCCIPR_CKPERSEL_1)
+#endif /* RCC_D1CCIPR_CKPERSEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SPIx_CLKSOURCE  Peripheral SPI clock source selection
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_SPI123SEL)
+#define LL_RCC_SPI123_CLKSOURCE_PLL1Q          LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, 0x00000000U)
+#define LL_RCC_SPI123_CLKSOURCE_PLL2P          LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_0)
+#define LL_RCC_SPI123_CLKSOURCE_PLL3P          LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_1)
+#define LL_RCC_SPI123_CLKSOURCE_I2S_CKIN       LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1)
+#define LL_RCC_SPI123_CLKSOURCE_CLKP           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_2)
+#else
+#define LL_RCC_SPI123_CLKSOURCE_PLL1Q          LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, 0x00000000U)
+#define LL_RCC_SPI123_CLKSOURCE_PLL2P          LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_0)
+#define LL_RCC_SPI123_CLKSOURCE_PLL3P          LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_1)
+#define LL_RCC_SPI123_CLKSOURCE_I2S_CKIN       LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_0 | RCC_CDCCIP1R_SPI123SEL_1)
+#define LL_RCC_SPI123_CLKSOURCE_CLKP           LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_2)
+#endif /* RCC_D2CCIP1R_SPI123SEL */
+#if defined(RCC_D2CCIP1R_SPI45SEL)
+#define LL_RCC_SPI45_CLKSOURCE_PCLK2           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  0x00000000U)
+#define LL_RCC_SPI45_CLKSOURCE_PLL2Q           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  RCC_D2CCIP1R_SPI45SEL_0)
+#define LL_RCC_SPI45_CLKSOURCE_PLL3Q           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  RCC_D2CCIP1R_SPI45SEL_1)
+#define LL_RCC_SPI45_CLKSOURCE_HSI             LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_1)
+#define LL_RCC_SPI45_CLKSOURCE_CSI             LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  RCC_D2CCIP1R_SPI45SEL_2)
+#define LL_RCC_SPI45_CLKSOURCE_HSE             LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_2)
+#else
+#define LL_RCC_SPI45_CLKSOURCE_PCLK2           LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  0x00000000U)
+#define LL_RCC_SPI45_CLKSOURCE_PLL2Q           LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  RCC_CDCCIP1R_SPI45SEL_0)
+#define LL_RCC_SPI45_CLKSOURCE_PLL3Q           LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  RCC_CDCCIP1R_SPI45SEL_1)
+#define LL_RCC_SPI45_CLKSOURCE_HSI             LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_1)
+#define LL_RCC_SPI45_CLKSOURCE_CSI             LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  RCC_CDCCIP1R_SPI45SEL_2)
+#define LL_RCC_SPI45_CLKSOURCE_HSE             LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_2)
+#endif /* (RCC_D2CCIP1R_SPI45SEL */
+#if defined(RCC_D3CCIPR_SPI6SEL)
+#define LL_RCC_SPI6_CLKSOURCE_PCLK4            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    0x00000000U)
+#define LL_RCC_SPI6_CLKSOURCE_PLL2Q            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    RCC_D3CCIPR_SPI6SEL_0)
+#define LL_RCC_SPI6_CLKSOURCE_PLL3Q            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    RCC_D3CCIPR_SPI6SEL_1)
+#define LL_RCC_SPI6_CLKSOURCE_HSI              LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_1)
+#define LL_RCC_SPI6_CLKSOURCE_CSI              LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    RCC_D3CCIPR_SPI6SEL_2)
+#define LL_RCC_SPI6_CLKSOURCE_HSE              LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_2)
+#else
+#define LL_RCC_SPI6_CLKSOURCE_PCLK4            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    0x00000000U)
+#define LL_RCC_SPI6_CLKSOURCE_PLL2Q            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_0)
+#define LL_RCC_SPI6_CLKSOURCE_PLL3Q            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_1)
+#define LL_RCC_SPI6_CLKSOURCE_HSI              LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_1)
+#define LL_RCC_SPI6_CLKSOURCE_CSI              LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_2)
+#define LL_RCC_SPI6_CLKSOURCE_HSE              LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_2)
+#define LL_RCC_SPI6_CLKSOURCE_I2S_CKIN         LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_1 | RCC_SRDCCIPR_SPI6SEL_2)
+#endif /* RCC_D3CCIPR_SPI6SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SPDIF_CLKSOURCE  Peripheral SPDIF clock source selection
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_SPDIFSEL)
+#define LL_RCC_SPDIF_CLKSOURCE_PLL1Q           (0x00000000U)
+#define LL_RCC_SPDIF_CLKSOURCE_PLL2R           (RCC_D2CCIP1R_SPDIFSEL_0)
+#define LL_RCC_SPDIF_CLKSOURCE_PLL3R           (RCC_D2CCIP1R_SPDIFSEL_1)
+#define LL_RCC_SPDIF_CLKSOURCE_HSI             (RCC_D2CCIP1R_SPDIFSEL_0 | RCC_D2CCIP1R_SPDIFSEL_1)
+#else
+#define LL_RCC_SPDIF_CLKSOURCE_PLL1Q           (0x00000000U)
+#define LL_RCC_SPDIF_CLKSOURCE_PLL2R           (RCC_CDCCIP1R_SPDIFSEL_0)
+#define LL_RCC_SPDIF_CLKSOURCE_PLL3R           (RCC_CDCCIP1R_SPDIFSEL_1)
+#define LL_RCC_SPDIF_CLKSOURCE_HSI             (RCC_CDCCIP1R_SPDIFSEL_0 | RCC_CDCCIP1R_SPDIFSEL_1)
+#endif /* RCC_D2CCIP1R_SPDIFSEL */
+/**
+  * @}
+  */
+
+#if defined(FDCAN1) || defined(FDCAN2)
+/** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE  Peripheral FDCAN clock source selection
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_FDCANSEL)
+#define LL_RCC_FDCAN_CLKSOURCE_HSE             (0x00000000U)
+#define LL_RCC_FDCAN_CLKSOURCE_PLL1Q           (RCC_D2CCIP1R_FDCANSEL_0)
+#define LL_RCC_FDCAN_CLKSOURCE_PLL2Q           (RCC_D2CCIP1R_FDCANSEL_1)
+#else
+#define LL_RCC_FDCAN_CLKSOURCE_HSE             (0x00000000U)
+#define LL_RCC_FDCAN_CLKSOURCE_PLL1Q           (RCC_CDCCIP1R_FDCANSEL_0)
+#define LL_RCC_FDCAN_CLKSOURCE_PLL2Q           (RCC_CDCCIP1R_FDCANSEL_1)
+#endif /* RCC_D2CCIP1R_FDCANSEL */
+/**
+  * @}
+  */
+#endif /*FDCAN1 || FDCAN2*/
+
+/** @defgroup RCC_LL_EC_SWP_CLKSOURCE  Peripheral SWP clock source selection
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_SWPSEL)
+#define LL_RCC_SWP_CLKSOURCE_PCLK1             (0x00000000U)
+#define LL_RCC_SWP_CLKSOURCE_HSI               (RCC_D2CCIP1R_SWPSEL)
+#else
+#define LL_RCC_SWP_CLKSOURCE_PCLK1             (0x00000000U)
+#define LL_RCC_SWP_CLKSOURCE_HSI               (RCC_CDCCIP1R_SWPSEL)
+#endif /* RCC_D2CCIP1R_SWPSEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_ADC_CLKSOURCE  Peripheral ADC clock source selection
+  * @{
+  */
+#if defined(RCC_D3CCIPR_ADCSEL)
+#define LL_RCC_ADC_CLKSOURCE_PLL2P             (0x00000000U)
+#define LL_RCC_ADC_CLKSOURCE_PLL3R             (RCC_D3CCIPR_ADCSEL_0)
+#define LL_RCC_ADC_CLKSOURCE_CLKP              (RCC_D3CCIPR_ADCSEL_1)
+#else
+#define LL_RCC_ADC_CLKSOURCE_PLL2P             (0x00000000U)
+#define LL_RCC_ADC_CLKSOURCE_PLL3R             (RCC_SRDCCIPR_ADCSEL_0)
+#define LL_RCC_ADC_CLKSOURCE_CLKP              (RCC_SRDCCIPR_ADCSEL_1)
+#endif /* RCC_D3CCIPR_ADCSEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_USARTx_CLKSOURCE  Peripheral USART get clock source
+  * @{
+  */
+#if defined (RCC_D2CCIP2R_USART16SEL)
+#define LL_RCC_USART16_CLKSOURCE         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, 0x00000000U)
+#else
+#define LL_RCC_USART16_CLKSOURCE         LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, 0x00000000U)
+/* alias*/
+#define LL_RCC_USART16910_CLKSOURCE      LL_RCC_USART16_CLKSOURCE
+#endif /* RCC_D2CCIP2R_USART16SEL */
+#if defined (RCC_D2CCIP2R_USART28SEL)
+#define LL_RCC_USART234578_CLKSOURCE     LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, 0x00000000U)
+#else
+#define LL_RCC_USART234578_CLKSOURCE     LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, 0x00000000U)
+#endif /* RCC_D2CCIP2R_USART28SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_LPUARTx_CLKSOURCE  Peripheral LPUART get clock source
+  * @{
+  */
+#if defined(RCC_D3CCIPR_LPUART1SEL)
+#define LL_RCC_LPUART1_CLKSOURCE         RCC_D3CCIPR_LPUART1SEL
+#else
+#define LL_RCC_LPUART1_CLKSOURCE         RCC_SRDCCIPR_LPUART1SEL
+#endif /* RCC_D3CCIPR_LPUART1SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE  Peripheral I2C get clock source
+  * @{
+  */
+#if defined(RCC_D2CCIP2R_I2C123SEL)
+#define LL_RCC_I2C123_CLKSOURCE          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, 0x00000000U)
+#else
+#define LL_RCC_I2C123_CLKSOURCE          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, 0x00000000U)
+#endif /* RCC_D2CCIP2R_I2C123SEL */
+#if defined(RCC_D3CCIPR_I2C4SEL)
+#define LL_RCC_I2C4_CLKSOURCE            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_I2C4SEL,    RCC_D3CCIPR_I2C4SEL_Pos,    0x00000000U)
+#else
+#define LL_RCC_I2C4_CLKSOURCE            LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL,   RCC_SRDCCIPR_I2C4SEL_Pos,   0x00000000U)
+#endif /* RCC_D3CCIPR_I2C4SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_LPTIMx_CLKSOURCE  Peripheral LPTIM get clock source
+  * @{
+  */
+#if defined(RCC_D2CCIP2R_LPTIM1SEL)
+#define LL_RCC_LPTIM1_CLKSOURCE          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,   0x00000000U)
+#else
+#define LL_RCC_LPTIM1_CLKSOURCE          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,   0x00000000U)
+#endif /* RCC_D2CCIP2R_LPTIM1SEL) */
+#if defined(RCC_D3CCIPR_LPTIM2SEL)
+#define LL_RCC_LPTIM2_CLKSOURCE          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,    0x00000000U)
+#else
+#define LL_RCC_LPTIM2_CLKSOURCE          LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL,  RCC_SRDCCIPR_LPTIM2SEL_Pos,   0x00000000U)
+#endif /* RCC_D3CCIPR_LPTIM2SEL */
+#if defined(RCC_D3CCIPR_LPTIM345SEL)
+#define LL_RCC_LPTIM345_CLKSOURCE        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos,  0x00000000U)
+#else
+#define LL_RCC_LPTIM345_CLKSOURCE        LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos,   0x00000000U)
+#define LL_RCC_LPTIM3_CLKSOURCE          LL_RCC_LPTIM345_CLKSOURCE  /* alias */
+#endif /* RCC_D3CCIPR_LPTIM345SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SAIx_CLKSOURCE  Peripheral SAI get clock source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_SAI1SEL)
+#define LL_RCC_SAI1_CLKSOURCE            LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  0x00000000U)
+#else
+#define LL_RCC_SAI1_CLKSOURCE            LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  0x00000000U)
+#endif /* RCC_D2CCIP1R_SAI1SEL */
+#if defined(RCC_D2CCIP1R_SAI23SEL)
+#define LL_RCC_SAI23_CLKSOURCE           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, 0x00000000U)
+#endif /* RCC_D2CCIP1R_SAI23SEL */
+#if defined(RCC_CDCCIP1R_SAI2ASEL)
+#define LL_RCC_SAI2A_CLKSOURCE           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  0x00000000U)
+#endif /* RCC_CDCCIP1R_SAI2ASEL */
+#if defined(RCC_CDCCIP1R_SAI2BSEL)
+#define LL_RCC_SAI2B_CLKSOURCE           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  0x00000000U)
+#endif /*  RCC_CDCCIP1R_SAI2BSEL */
+#if defined(RCC_D3CCIPR_SAI4ASEL)
+#define LL_RCC_SAI4A_CLKSOURCE           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  0x00000000U)
+#endif /* RCC_D3CCIPR_SAI4ASEL */
+#if defined(RCC_D3CCIPR_SAI4BSEL)
+#define LL_RCC_SAI4B_CLKSOURCE           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  0x00000000U)
+#endif /*  RCC_D3CCIPR_SAI4BSEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SDMMC_CLKSOURCE  Peripheral SDMMC get clock source
+  * @{
+  */
+#if defined(RCC_D1CCIPR_SDMMCSEL)
+#define LL_RCC_SDMMC_CLKSOURCE           RCC_D1CCIPR_SDMMCSEL
+#else
+#define LL_RCC_SDMMC_CLKSOURCE           RCC_CDCCIPR_SDMMCSEL
+#endif /* RCC_D1CCIPR_SDMMCSEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_RNG_CLKSOURCE  Peripheral RNG get clock source
+  * @{
+  */
+#if (RCC_D2CCIP2R_RNGSEL)
+#define LL_RCC_RNG_CLKSOURCE             RCC_D2CCIP2R_RNGSEL
+#else
+#define LL_RCC_RNG_CLKSOURCE             RCC_CDCCIP2R_RNGSEL
+#endif /* RCC_D2CCIP2R_RNGSEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_USB_CLKSOURCE  Peripheral USB get clock source
+  * @{
+  */
+#if (RCC_D2CCIP2R_USBSEL)
+#define LL_RCC_USB_CLKSOURCE             RCC_D2CCIP2R_USBSEL
+#else
+#define LL_RCC_USB_CLKSOURCE             RCC_CDCCIP2R_USBSEL
+#endif  /* RCC_D2CCIP2R_USBSEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_CEC_CLKSOURCE  Peripheral CEC get clock source
+  * @{
+  */
+#if (RCC_D2CCIP2R_CECSEL)
+#define LL_RCC_CEC_CLKSOURCE             RCC_D2CCIP2R_CECSEL
+#else
+#define LL_RCC_CEC_CLKSOURCE             RCC_CDCCIP2R_CECSEL
+#endif /* RCC_D2CCIP2R_CECSEL */
+/**
+  * @}
+  */
+
+#if defined(DSI)
+/** @defgroup RCC_LL_EC_DSI_CLKSOURCE  Peripheral DSI get clock source
+  * @{
+  */
+#define LL_RCC_DSI_CLKSOURCE             RCC_D1CCIPR_DSISEL
+/**
+  * @}
+  */
+#endif /* DSI */
+
+/** @defgroup RCC_LL_EC_DFSDM_CLKSOURCE  Peripheral DFSDM get clock source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_DFSDM1SEL)
+#define LL_RCC_DFSDM1_CLKSOURCE          RCC_D2CCIP1R_DFSDM1SEL
+#else
+#define LL_RCC_DFSDM1_CLKSOURCE          RCC_CDCCIP1R_DFSDM1SEL
+#endif /* RCC_D2CCIP1R_DFSDM1SEL */
+/**
+  * @}
+  */
+
+#if defined(DFSDM2_BASE)
+/** @defgroup RCC_LL_EC_DFSDM2_CLKSOURCE  Peripheral DFSDM2 get clock source
+  * @{
+  */
+#define LL_RCC_DFSDM2_CLKSOURCE          RCC_SRDCCIPR_DFSDM2SEL
+/**
+  * @}
+  */
+#endif /* DFSDM2 */
+
+
+/** @defgroup RCC_LL_EC_FMC_CLKSOURCE  Peripheral FMC get clock source
+  * @{
+  */
+#if defined(RCC_D1CCIPR_FMCSEL)
+#define LL_RCC_FMC_CLKSOURCE             RCC_D1CCIPR_FMCSEL
+#else
+#define LL_RCC_FMC_CLKSOURCE             RCC_CDCCIPR_FMCSEL
+#endif
+/**
+  * @}
+  */
+
+#if defined(QUADSPI)
+/** @defgroup RCC_LL_EC_QSPI_CLKSOURCE  Peripheral QSPI get clock source
+  * @{
+  */
+#define LL_RCC_QSPI_CLKSOURCE            RCC_D1CCIPR_QSPISEL
+/**
+  * @}
+  */
+#endif /* QUADSPI */
+
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+/** @defgroup RCC_LL_EC_OSPI_CLKSOURCE  Peripheral OSPI get clock source
+  * @{
+  */
+#define LL_RCC_OSPI_CLKSOURCE            RCC_CDCCIPR_OCTOSPISEL
+/**
+  * @}
+  */
+#endif /* OCTOSPI1 || OCTOSPI2 */
+
+/** @defgroup RCC_LL_EC_CLKP_CLKSOURCE  Peripheral CLKP get clock source
+  * @{
+  */
+#if defined(RCC_D1CCIPR_CKPERSEL)
+#define LL_RCC_CLKP_CLKSOURCE            RCC_D1CCIPR_CKPERSEL
+#else
+#define LL_RCC_CLKP_CLKSOURCE            RCC_CDCCIPR_CKPERSEL
+#endif /* RCC_D1CCIPR_CKPERSEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SPIx_CLKSOURCE  Peripheral SPI get clock source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_SPI123SEL)
+#define LL_RCC_SPI123_CLKSOURCE          LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, 0x00000000U)
+#else
+#define LL_RCC_SPI123_CLKSOURCE          LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, 0x00000000U)
+#endif /* RCC_D2CCIP1R_SPI123SEL */
+#if defined(RCC_D2CCIP1R_SPI45SEL)
+#define LL_RCC_SPI45_CLKSOURCE           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  0x00000000U)
+#else
+#define LL_RCC_SPI45_CLKSOURCE           LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  0x00000000U)
+#endif /* RCC_D2CCIP1R_SPI45SEL */
+#if defined(RCC_D3CCIPR_SPI6SEL)
+#define LL_RCC_SPI6_CLKSOURCE            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    0x00000000U)
+#else
+#define LL_RCC_SPI6_CLKSOURCE            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,   RCC_SRDCCIPR_SPI6SEL_Pos,  0x00000000U)
+#endif /* RCC_D3CCIPR_SPI6SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SPDIF_CLKSOURCE  Peripheral SPDIF get clock source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_SPDIFSEL)
+#define LL_RCC_SPDIF_CLKSOURCE           RCC_D2CCIP1R_SPDIFSEL
+#else
+#define LL_RCC_SPDIF_CLKSOURCE           RCC_CDCCIP1R_SPDIFSEL
+#endif /* RCC_D2CCIP1R_SPDIFSEL */
+/**
+  * @}
+  */
+
+#if defined(FDCAN1) || defined(FDCAN2)
+/** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE  Peripheral FDCAN get clock source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_FDCANSEL)
+#define LL_RCC_FDCAN_CLKSOURCE           RCC_D2CCIP1R_FDCANSEL
+#else
+#define LL_RCC_FDCAN_CLKSOURCE           RCC_CDCCIP1R_FDCANSEL
+#endif
+/**
+  * @}
+  */
+#endif /*FDCAN1 || FDCAN2*/
+
+/** @defgroup RCC_LL_EC_SWP_CLKSOURCE  Peripheral SWP get clock source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_SWPSEL)
+#define LL_RCC_SWP_CLKSOURCE             RCC_D2CCIP1R_SWPSEL
+#else
+#define LL_RCC_SWP_CLKSOURCE             RCC_CDCCIP1R_SWPSEL
+#endif /* RCC_D2CCIP1R_SWPSEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_ADC_CLKSOURCE  Peripheral ADC get clock source
+  * @{
+  */
+#if defined(RCC_D3CCIPR_ADCSEL)
+#define LL_RCC_ADC_CLKSOURCE             RCC_D3CCIPR_ADCSEL
+#else
+#define LL_RCC_ADC_CLKSOURCE             RCC_SRDCCIPR_ADCSEL
+#endif /* RCC_D3CCIPR_ADCSEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_RTC_CLKSOURCE  RTC clock source selection
+  * @{
+  */
+#define LL_RCC_RTC_CLKSOURCE_NONE          (uint32_t)(0x00000000U)
+#define LL_RCC_RTC_CLKSOURCE_LSE           (uint32_t)(RCC_BDCR_RTCSEL_0)
+#define LL_RCC_RTC_CLKSOURCE_LSI           (uint32_t)(RCC_BDCR_RTCSEL_1)
+#define LL_RCC_RTC_CLKSOURCE_HSE           (uint32_t)(RCC_BDCR_RTCSEL_0 | RCC_BDCR_RTCSEL_1)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_TIM_CLKPRESCALER  Timers clocks prescalers selection
+  * @{
+  */
+#define LL_RCC_TIM_PRESCALER_TWICE          (uint32_t)(0x00000000U)
+#define LL_RCC_TIM_PRESCALER_FOUR_TIMES     (uint32_t)(RCC_CFGR_TIMPRE)
+/**
+  * @}
+  */
+
+#if defined(HRTIM1)
+/** @defgroup RCC_LL_EC_HRTIM_CLKSOURCE  High Resolution Timers clock selection
+  * @{
+  */
+#define LL_RCC_HRTIM_CLKSOURCE_TIM          (uint32_t)(0x00000000U)           /* HRTIM Clock source is same as other timers */
+#define LL_RCC_HRTIM_CLKSOURCE_CPU          (uint32_t)(RCC_CFGR_HRTIMSEL)     /* HRTIM Clock source is the CPU clock */
+/**
+  * @}
+  */
+#endif /* HRTIM1 */
+
+/** @defgroup RCC_LL_EC_PLLSOURCE   All PLLs entry clock source
+  * @{
+  */
+#define LL_RCC_PLLSOURCE_HSI               RCC_PLLCKSELR_PLLSRC_HSI
+#define LL_RCC_PLLSOURCE_CSI               RCC_PLLCKSELR_PLLSRC_CSI
+#define LL_RCC_PLLSOURCE_HSE               RCC_PLLCKSELR_PLLSRC_HSE
+#define LL_RCC_PLLSOURCE_NONE              RCC_PLLCKSELR_PLLSRC_NONE
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_PLLINPUTRANGE   All PLLs input range
+  * @{
+  */
+#define LL_RCC_PLLINPUTRANGE_1_2           (uint32_t)(0x00000000U)
+#define LL_RCC_PLLINPUTRANGE_2_4           (uint32_t)(0x00000001)
+#define LL_RCC_PLLINPUTRANGE_4_8           (uint32_t)(0x00000002)
+#define LL_RCC_PLLINPUTRANGE_8_16          (uint32_t)(0x00000003)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_PLLVCORANGE   All PLLs VCO range
+  * @{
+  */
+#define LL_RCC_PLLVCORANGE_WIDE            (uint32_t)(0x00000000U)      /* VCO output range: 192 to 836 MHz   OR  128 to 544 MHz (*) */
+#define LL_RCC_PLLVCORANGE_MEDIUM          (uint32_t)(0x00000001)       /* VCO output range: 150 to 420 MHz */
+/**
+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
+  * @{
+  */
+
+/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in RCC register
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in RCC register
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
+  * @{
+  */
+
+/**
+  * @brief  Helper macro to calculate the SYSCLK frequency
+  * @param  __SYSINPUTCLKFREQ__ Frequency of the input of sys_ck (based on HSE/CSI/HSI/PLL1P)
+  * @param  __SYSPRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SYSCLK_DIV_1
+  *         @arg @ref LL_RCC_SYSCLK_DIV_2
+  *         @arg @ref LL_RCC_SYSCLK_DIV_4
+  *         @arg @ref LL_RCC_SYSCLK_DIV_8
+  *         @arg @ref LL_RCC_SYSCLK_DIV_16
+  *         @arg @ref LL_RCC_SYSCLK_DIV_64
+  *         @arg @ref LL_RCC_SYSCLK_DIV_128
+  *         @arg @ref LL_RCC_SYSCLK_DIV_256
+  *         @arg @ref LL_RCC_SYSCLK_DIV_512
+  * @retval SYSCLK clock frequency (in Hz)
+  */
+#if defined(RCC_D1CFGR_D1CPRE)
+#define LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> ((LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_D1CFGR_D1CPRE) >>  RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU))
+#else
+#define LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> ((LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU))
+#endif /* RCC_D1CFGR_D1CPRE */
+
+/**
+  * @brief  Helper macro to calculate the HCLK frequency
+  * @param  __SYSCLKFREQ__ SYSCLK frequency.
+  * @param  __HPRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_AHB_DIV_1
+  *         @arg @ref LL_RCC_AHB_DIV_2
+  *         @arg @ref LL_RCC_AHB_DIV_4
+  *         @arg @ref LL_RCC_AHB_DIV_8
+  *         @arg @ref LL_RCC_AHB_DIV_16
+  *         @arg @ref LL_RCC_AHB_DIV_64
+  *         @arg @ref LL_RCC_AHB_DIV_128
+  *         @arg @ref LL_RCC_AHB_DIV_256
+  *         @arg @ref LL_RCC_AHB_DIV_512
+  * @retval HCLK clock frequency (in Hz)
+  */
+#if defined(RCC_D1CFGR_HPRE)
+#define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> ((LL_RCC_PrescTable[((__HPRESCALER__) & RCC_D1CFGR_HPRE) >>  RCC_D1CFGR_HPRE_Pos]) & 0x1FU))
+#else
+#define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> ((LL_RCC_PrescTable[((__HPRESCALER__) & RCC_CDCFGR1_HPRE) >>  RCC_CDCFGR1_HPRE_Pos]) & 0x1FU))
+#endif  /* RCC_D1CFGR_HPRE */
+
+/**
+  * @brief  Helper macro to calculate the PCLK1 frequency (ABP1)
+  * @param  __HCLKFREQ__ HCLK frequency
+  * @param  __APB1PRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB1_DIV_1
+  *         @arg @ref LL_RCC_APB1_DIV_2
+  *         @arg @ref LL_RCC_APB1_DIV_4
+  *         @arg @ref LL_RCC_APB1_DIV_8
+  *         @arg @ref LL_RCC_APB1_DIV_16
+  * @retval PCLK1 clock frequency (in Hz)
+  */
+#if defined(RCC_D2CFGR_D2PPRE1)
+#define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_D2CFGR_D2PPRE1) >>  RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU))
+#else
+#define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_CDCFGR2_CDPPRE1) >>  RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU))
+#endif /* RCC_D2CFGR_D2PPRE1 */
+
+/**
+  * @brief  Helper macro to calculate the PCLK2 frequency (ABP2)
+  * @param  __HCLKFREQ__ HCLK frequency
+  * @param  __APB2PRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB2_DIV_1
+  *         @arg @ref LL_RCC_APB2_DIV_2
+  *         @arg @ref LL_RCC_APB2_DIV_4
+  *         @arg @ref LL_RCC_APB2_DIV_8
+  *         @arg @ref LL_RCC_APB2_DIV_16
+  * @retval PCLK2 clock frequency (in Hz)
+  */
+#if defined(RCC_D2CFGR_D2PPRE2)
+#define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_D2CFGR_D2PPRE2) >>  RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU))
+#else
+#define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU))
+#endif /* RCC_D2CFGR_D2PPRE2 */
+
+/**
+  * @brief  Helper macro to calculate the PCLK3 frequency (APB3)
+  * @param  __HCLKFREQ__ HCLK frequency
+  * @param  __APB3PRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB3_DIV_1
+  *         @arg @ref LL_RCC_APB3_DIV_2
+  *         @arg @ref LL_RCC_APB3_DIV_4
+  *         @arg @ref LL_RCC_APB3_DIV_8
+  *         @arg @ref LL_RCC_APB3_DIV_16
+  * @retval PCLK1 clock frequency (in Hz)
+  */
+#if defined(RCC_D1CFGR_D1PPRE)
+#define LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_D1CFGR_D1PPRE) >>  RCC_D1CFGR_D1PPRE_Pos]) & 0x1FU))
+#else
+#define LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_CDCFGR1_CDPPRE) >> RCC_CDCFGR1_CDPPRE_Pos]) & 0x1FU))
+#endif /* RCC_D1CFGR_D1PPRE */
+
+/**
+  * @brief  Helper macro to calculate the PCLK4 frequency (ABP4)
+  * @param  __HCLKFREQ__ HCLK frequency
+  * @param  __APB4PRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB4_DIV_1
+  *         @arg @ref LL_RCC_APB4_DIV_2
+  *         @arg @ref LL_RCC_APB4_DIV_4
+  *         @arg @ref LL_RCC_APB4_DIV_8
+  *         @arg @ref LL_RCC_APB4_DIV_16
+  * @retval PCLK1 clock frequency (in Hz)
+  */
+#if defined(RCC_D3CFGR_D3PPRE)
+#define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_D3CFGR_D3PPRE) >>  RCC_D3CFGR_D3PPRE_Pos]) & 0x1FU))
+#else
+#define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_SRDCFGR_SRDPPRE) >>  RCC_SRDCFGR_SRDPPRE_Pos]) & 0x1FU))
+#endif /* RCC_D3CFGR_D3PPRE */
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
+  * @{
+  */
+#define LL_RCC_PERIPH_FREQUENCY_NO         0x00000000U                 /*!< No clock enabled for the peripheral            */
+#define LL_RCC_PERIPH_FREQUENCY_NA         0xFFFFFFFFU                 /*!< Frequency cannot be provided as external clock */
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
+  * @{
+  */
+
+/** @defgroup RCC_LL_EF_HSE HSE
+  * @{
+  */
+
+/**
+  * @brief  Enable the Clock Security System.
+  * @note Once HSE Clock Security System is enabled it cannot be changed anymore unless
+  *       a reset occurs or system enter in standby mode.
+  * @rmtoll CR           CSSHSEON         LL_RCC_HSE_EnableCSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_CSSHSEON);
+}
+
+/**
+  * @brief  Enable HSE external oscillator (HSE Bypass)
+  * @rmtoll CR           HSEBYP        LL_RCC_HSE_EnableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_HSEBYP);
+}
+
+/**
+  * @brief  Disable HSE external oscillator (HSE Bypass)
+  * @rmtoll CR           HSEBYP        LL_RCC_HSE_DisableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
+}
+
+#if defined(RCC_CR_HSEEXT)
+/**
+  * @brief  Select the Analog HSE external clock type in Bypass mode
+  * @rmtoll CR           HSEEXT        LL_RCC_HSE_SelectAnalogClock
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_SelectAnalogClock(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT);
+}
+
+/**
+  * @brief  Select the Digital HSE external clock type in Bypass mode
+  * @rmtoll CR           HSEEXT        LL_RCC_HSE_SelectDigitalClock
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_SelectDigitalClock(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_HSEEXT);
+}
+#endif /* RCC_CR_HSEEXT */
+
+/**
+  * @brief  Enable HSE crystal oscillator (HSE ON)
+  * @rmtoll CR           HSEON         LL_RCC_HSE_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_HSEON);
+}
+
+/**
+  * @brief  Disable HSE crystal oscillator (HSE ON)
+  * @rmtoll CR           HSEON         LL_RCC_HSE_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
+}
+
+/**
+  * @brief  Check if HSE oscillator Ready
+  * @rmtoll CR           HSERDY        LL_RCC_HSE_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
+{
+  return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY))?1UL:0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_HSI HSI
+  * @{
+  */
+
+/**
+  * @brief  Enable HSI oscillator
+  * @rmtoll CR           HSION         LL_RCC_HSI_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_HSION);
+}
+
+/**
+  * @brief  Disable HSI oscillator
+  * @rmtoll CR           HSION         LL_RCC_HSI_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_HSION);
+}
+
+/**
+  * @brief  Check if HSI clock is ready
+  * @rmtoll CR           HSIRDY        LL_RCC_HSI_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
+{
+  return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if HSI new divider applied and ready
+  * @rmtoll CR           HSIDIVF        LL_RCC_HSI_IsDividerReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI_IsDividerReady(void)
+{
+  return ((READ_BIT(RCC->CR, RCC_CR_HSIDIVF) == (RCC_CR_HSIDIVF))?1UL:0UL);
+}
+
+/**
+  * @brief  Set HSI divider
+  * @rmtoll CR           HSIDIV        LL_RCC_HSI_SetDivider
+  * @param  Divider This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_HSI_DIV1
+  *         @arg @ref LL_RCC_HSI_DIV2
+  *         @arg @ref LL_RCC_HSI_DIV4
+  *         @arg @ref LL_RCC_HSI_DIV8
+  * @retval None.
+  */
+__STATIC_INLINE void LL_RCC_HSI_SetDivider(uint32_t Divider)
+{
+  MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, Divider);
+}
+
+/**
+  * @brief  Get HSI divider
+  * @rmtoll CR           HSIDIV        LL_RCC_HSI_GetDivider
+  * @retval can be one of the following values:
+  *         @arg @ref LL_RCC_HSI_DIV1
+  *         @arg @ref LL_RCC_HSI_DIV2
+  *         @arg @ref LL_RCC_HSI_DIV4
+  *         @arg @ref LL_RCC_HSI_DIV8
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI_GetDivider(void)
+{
+  return (READ_BIT(RCC->CR, RCC_CR_HSIDIV));
+}
+
+/**
+  * @brief  Enable HSI oscillator in Stop mode
+  * @rmtoll CR           HSIKERON         LL_RCC_HSI_EnableStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_EnableStopMode(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_HSIKERON);
+}
+
+/**
+  * @brief  Disable HSI oscillator in Stop mode
+  * @rmtoll CR           HSION         LL_RCC_HSI_DisableStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_DisableStopMode(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
+}
+
+/**
+  * @brief  Get HSI Calibration value
+  * @note When HSITRIM is written, HSICAL is updated with the sum of
+  *       HSITRIM and the factory trim value
+  * @rmtoll HSICFGR        HSICAL        LL_RCC_HSI_GetCalibration
+  * @retval A value between 0 and 4095 (0xFFF)
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
+{
+  return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSICAL) >> RCC_HSICFGR_HSICAL_Pos);
+}
+
+/**
+  * @brief  Set HSI Calibration trimming
+  * @note user-programmable trimming value that is added to the HSICAL
+  * @note Default value is 64 (32 for Cut1.x), which, when added to the HSICAL value,
+  *       should trim the HSI to 64 MHz +/- 1 %
+  * @rmtoll HSICFGR        HSITRIM       LL_RCC_HSI_SetCalibTrimming
+  * @param  Parameter can be a value between 0 and 127 (63 for Cut1.x)
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
+{
+#if defined(RCC_VER_X)
+  if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)
+  {
+    /* STM32H7 Rev.Y */
+    MODIFY_REG(RCC->HSICFGR, 0x3F000U, Value << 12U);
+  }
+  else
+  {
+    /* STM32H7 Rev.V */
+    MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, Value << RCC_HSICFGR_HSITRIM_Pos);
+  }
+#else
+    MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, Value << RCC_HSICFGR_HSITRIM_Pos);
+#endif /* RCC_VER_X */
+}
+
+/**
+  * @brief  Get HSI Calibration trimming
+  * @rmtoll HSICFGR        HSITRIM       LL_RCC_HSI_GetCalibTrimming
+  * @retval A value between 0 and 127 (63 for Cut1.x)
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
+{
+#if defined(RCC_VER_X)
+  if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)
+  {
+    /* STM32H7 Rev.Y */
+    return (uint32_t)(READ_BIT(RCC->HSICFGR, 0x3F000U) >> 12U);
+  }
+  else
+  {
+    /* STM32H7 Rev.V */
+    return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
+  }
+#else
+    return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
+#endif /* RCC_VER_X */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_CSI CSI
+  * @{
+  */
+
+/**
+  * @brief  Enable CSI oscillator
+  * @rmtoll CR           CSION         LL_RCC_CSI_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_CSI_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_CSION);
+}
+
+/**
+  * @brief  Disable CSI oscillator
+  * @rmtoll CR           CSION         LL_RCC_CSI_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_CSI_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_CSION);
+}
+
+/**
+  * @brief  Check if CSI clock is ready
+  * @rmtoll CR           CSIRDY        LL_RCC_CSI_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_CSI_IsReady(void)
+{
+  return ((READ_BIT(RCC->CR, RCC_CR_CSIRDY) == (RCC_CR_CSIRDY))?1UL:0UL);
+}
+
+/**
+  * @brief  Enable CSI oscillator in Stop mode
+  * @rmtoll CR           CSIKERON         LL_RCC_CSI_EnableStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_CSI_EnableStopMode(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_CSIKERON);
+}
+
+/**
+  * @brief  Disable CSI oscillator in Stop mode
+  * @rmtoll CR           CSIKERON         LL_RCC_CSI_DisableStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_CSI_DisableStopMode(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON);
+}
+
+/**
+  * @brief  Get CSI Calibration value
+  * @note When CSITRIM is written, CSICAL is updated with the sum of
+  *       CSITRIM and the factory trim value
+  * @rmtoll CSICFGR        CSICAL        LL_RCC_CSI_GetCalibration
+  * @retval A value between 0 and 255 (0xFF)
+  */
+__STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibration(void)
+{
+#if defined(RCC_VER_X)
+  if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)
+  {
+    /* STM32H7 Rev.Y */
+    return (uint32_t)(READ_BIT(RCC->HSICFGR, 0x3FC0000U) >> 18U);
+  }
+  else
+  {
+    /* STM32H7 Rev.V */
+    return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSICAL) >> RCC_CSICFGR_CSICAL_Pos);
+  }
+#else
+    return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSICAL) >> RCC_CSICFGR_CSICAL_Pos);
+#endif /* RCC_VER_X */
+}
+
+/**
+  * @brief  Set CSI Calibration trimming
+  * @note user-programmable trimming value that is added to the CSICAL
+  * @note Default value is 16, which, when added to the CSICAL value,
+  *       should trim the CSI to 4 MHz +/- 1 %
+  * @rmtoll CSICFGR        CSITRIM       LL_RCC_CSI_SetCalibTrimming
+  * @param  Value can be a value between 0 and 31
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_CSI_SetCalibTrimming(uint32_t Value)
+{
+#if defined(RCC_VER_X)
+  if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)
+  {
+    /* STM32H7 Rev.Y */
+    MODIFY_REG(RCC->HSICFGR, 0x7C000000U, Value << 26U);
+  }
+  else
+  {
+    /* STM32H7 Rev.V */
+    MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, Value << RCC_CSICFGR_CSITRIM_Pos);
+  }
+#else
+    MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, Value << RCC_CSICFGR_CSITRIM_Pos);
+#endif /* RCC_VER_X */
+}
+
+/**
+  * @brief  Get CSI Calibration trimming
+  * @rmtoll CSICFGR        CSITRIM       LL_RCC_CSI_GetCalibTrimming
+  * @retval A value between 0 and 31
+  */
+__STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibTrimming(void)
+{
+#if defined(RCC_VER_X)
+  if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)
+  {
+    /* STM32H7 Rev.Y */
+    return (uint32_t)(READ_BIT(RCC->HSICFGR, 0x7C000000U) >> 26U);
+  }
+  else
+  {
+    /* STM32H7 Rev.V */
+    return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
+  }
+#else
+    return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
+#endif /* RCC_VER_X */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_HSI48 HSI48
+  * @{
+  */
+
+/**
+  * @brief  Enable HSI48 oscillator
+  * @rmtoll CR           HSI48ON         LL_RCC_HSI48_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI48_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_HSI48ON);
+}
+
+/**
+  * @brief  Disable HSI48 oscillator
+  * @rmtoll CR           HSI48ON         LL_RCC_HSI48_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI48_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON);
+}
+
+/**
+  * @brief  Check if HSI48 clock is ready
+  * @rmtoll CR           HSI48RDY        LL_RCC_HSI48_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
+{
+  return ((READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == (RCC_CR_HSI48RDY))?1UL:0UL);
+}
+
+/**
+  * @brief  Get HSI48 Calibration value
+  * @note When HSI48TRIM is written, HSI48CAL is updated with the sum of
+  *       HSI48TRIM and the factory trim value
+  * @rmtoll CRRCR        HSI48CAL        LL_RCC_HSI48_GetCalibration
+  * @retval A value between 0 and 1023 (0x3FF)
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos);
+}
+/**
+  * @}
+  */
+
+#if defined(RCC_CR_D1CKRDY)
+
+/** @defgroup RCC_LL_EF_D1CLK D1CKREADY
+  * @{
+  */
+
+/**
+  * @brief  Check if D1 clock is ready
+  * @rmtoll CR           D1CKRDY        LL_RCC_D1CK_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_D1CK_IsReady(void)
+{
+  return ((READ_BIT(RCC->CR, RCC_CR_D1CKRDY) == (RCC_CR_D1CKRDY))?1UL:0UL);
+}
+
+/**
+  * @}
+  */
+#else
+
+/** @defgroup RCC_LL_EF_CPUCLK CPUCKREADY
+  * @{
+  */
+
+/**
+  * @brief  Check if CPU clock is ready
+  * @rmtoll CR           CPUCKRDY        LL_RCC_CPUCK_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_CPUCK_IsReady(void)
+{
+  return ((READ_BIT(RCC->CR, RCC_CR_CPUCKRDY) == (RCC_CR_CPUCKRDY))?1UL:0UL);
+}
+ /* alias */
+#define LL_RCC_D1CK_IsReady  LL_RCC_CPUCK_IsReady
+/**
+  * @}
+  */
+#endif /* RCC_CR_D1CKRDY */
+
+#if defined(RCC_CR_D2CKRDY)
+
+/** @defgroup RCC_LL_EF_D2CLK D2CKREADY
+  * @{
+  */
+
+/**
+  * @brief  Check if D2 clock is ready
+  * @rmtoll CR           D2CKRDY        LL_RCC_D2CK_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_D2CK_IsReady(void)
+{
+  return ((READ_BIT(RCC->CR, RCC_CR_D2CKRDY) == (RCC_CR_D2CKRDY))?1UL:0UL);
+}
+/**
+  * @}
+  */
+#else
+
+/** @defgroup RCC_LL_EF_CDCLK CDCKREADY
+  * @{
+  */
+
+/**
+  * @brief  Check if CD clock is ready
+  * @rmtoll CR           CDCKRDY        LL_RCC_CDCK_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_CDCK_IsReady(void)
+{
+  return ((READ_BIT(RCC->CR, RCC_CR_CDCKRDY) == (RCC_CR_CDCKRDY))?1UL:0UL);
+}
+#define LL_RCC_D2CK_IsReady LL_RCC_CDCK_IsReady
+/**
+  * @}
+  */
+#endif /* RCC_CR_D2CKRDY */
+
+/** @defgroup RCC_LL_EF_SYSTEM_WIDE_RESET RESET
+  * @{
+  */
+#if defined(RCC_GCR_WW1RSC)
+
+/**
+  * @brief  Enable system wide reset for Window Watch Dog 1
+  * @rmtoll GCR          WW1RSC        LL_RCC_WWDG1_EnableSystemReset
+  * @retval None.
+  */
+__STATIC_INLINE void LL_RCC_WWDG1_EnableSystemReset(void)
+{
+  SET_BIT(RCC->GCR, RCC_GCR_WW1RSC);
+}
+
+/**
+  * @brief  Check if Window Watch Dog 1 reset is system wide
+  * @rmtoll GCR          WW1RSC        LL_RCC_WWDG1_IsSystemReset
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_WWDG1_IsSystemReset(void)
+{
+  return ((READ_BIT(RCC->GCR, RCC_GCR_WW1RSC) == RCC_GCR_WW1RSC)?1UL:0UL);
+}
+#endif  /* RCC_GCR_WW1RSC */
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Enable system wide reset for Window Watch Dog 2
+  * @rmtoll GCR          WW1RSC        LL_RCC_WWDG2_EnableSystemReset
+  * @retval None.
+  */
+__STATIC_INLINE void LL_RCC_WWDG2_EnableSystemReset(void)
+{
+  SET_BIT(RCC->GCR, RCC_GCR_WW2RSC);
+}
+
+/**
+  * @brief  Check if Window Watch Dog 2 reset is system wide
+  * @rmtoll GCR          WW2RSC        LL_RCC_WWDG2_IsSystemReset
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_WWDG2_IsSystemReset(void)
+{
+  return ((READ_BIT(RCC->GCR, RCC_GCR_WW2RSC) == RCC_GCR_WW2RSC)?1UL:0UL);
+}
+#endif  /*DUAL_CORE*/
+/**
+  * @}
+  */
+
+#if defined(DUAL_CORE)
+/** @defgroup RCC_LL_EF_BOOT_CPU CPU
+  * @{
+  */
+
+/**
+  * @brief  Force CM4 boot (if hold by option byte BCM4 = 0)
+  * @rmtoll GCR          BOOT_C2        LL_RCC_ForceCM4Boot
+  * @retval None.
+  */
+__STATIC_INLINE void LL_RCC_ForceCM4Boot(void)
+{
+  SET_BIT(RCC->GCR, RCC_GCR_BOOT_C2);
+}
+
+/**
+  * @brief  Check if CM4 boot is forced
+  * @rmtoll GCR          BOOT_C2        LL_RCC_IsCM4BootForced
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsCM4BootForced(void)
+{
+  return ((READ_BIT(RCC->GCR, RCC_GCR_BOOT_C2) == RCC_GCR_BOOT_C2)?1UL:0UL);
+}
+
+/**
+  * @brief  Force CM7 boot (if hold by option byte BCM7 = 0)
+  * @rmtoll GCR          BOOT_C1        LL_RCC_ForceCM7Boot
+  * @retval None.
+  */
+__STATIC_INLINE void LL_RCC_ForceCM7Boot(void)
+{
+  SET_BIT(RCC->GCR, RCC_GCR_BOOT_C1);
+}
+
+/**
+  * @brief  Check if CM7 boot is forced
+  * @rmtoll GCR          BOOT_C1        LL_RCC_IsCM7BootForced
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsCM7BootForced(void)
+{
+  return ((READ_BIT(RCC->GCR, RCC_GCR_BOOT_C1) == RCC_GCR_BOOT_C1)?1UL:0UL);
+}
+
+/**
+  * @}
+  */
+#endif  /*DUAL_CORE*/
+
+/** @defgroup RCC_LL_EF_LSE LSE
+  * @{
+  */
+
+/**
+  * @brief  Enable the Clock Security System on LSE.
+  * @note Once LSE Clock Security System is enabled it cannot be changed anymore unless
+  *       a clock failure is detected.
+  * @rmtoll BDCR          LSECSSON         LL_RCC_LSE_EnableCSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
+}
+
+/**
+  * @brief  Check if LSE failure is detected by Clock Security System
+  * @rmtoll BDCR         LSECSSD       LL_RCC_LSE_IsFailureDetected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_LSE_IsFailureDetected(void)
+{
+  return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD))?1UL:0UL);
+}
+
+/**
+  * @brief  Enable  Low Speed External (LSE) crystal.
+  * @rmtoll BDCR         LSEON         LL_RCC_LSE_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_Enable(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
+}
+
+/**
+  * @brief  Disable  Low Speed External (LSE) crystal.
+  * @rmtoll BDCR         LSEON         LL_RCC_LSE_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_Disable(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
+}
+
+/**
+  * @brief  Enable external clock source (LSE bypass).
+  * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_EnableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
+}
+
+/**
+  * @brief  Disable external clock source (LSE bypass).
+  * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_DisableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
+}
+
+#if defined(RCC_BDCR_LSEEXT)
+/**
+  * @brief  Enable Low-speed external DIGITAL clock type in Bypass mode (not to be used if RTC is active).
+  * @note   The external clock must be enabled with the LSEON bit, to be used by the device.
+  *         The LSEEXT bit can be written only if the LSE oscillator is disabled.
+  * @rmtoll BDCR         LSEEXT        LL_RCC_LSE_SelectDigitalClock
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_SelectDigitalClock(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);
+}
+
+/**
+  * @brief  Enable Low-speed external ANALOG clock type in Bypass mode (default after Backup domain reset).
+  * @note   The external clock must be enabled with the LSEON bit, to be used by the device.
+  *         The LSEEXT bit can be written only if the LSE oscillator is disabled.
+  * @rmtoll BDCR         LSEEXT        LL_RCC_LSE_SelectAnalogClock
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_SelectAnalogClock(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);
+}
+#endif /* RCC_BDCR_LSEEXT */
+
+/**
+  * @brief  Set LSE oscillator drive capability
+  * @note The oscillator is in Xtal mode when it is not in bypass mode.
+  * @rmtoll BDCR         LSEDRV        LL_RCC_LSE_SetDriveCapability
+  * @param  LSEDrive This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LSEDRIVE_LOW
+  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
+  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
+  *         @arg @ref LL_RCC_LSEDRIVE_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
+{
+  MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
+}
+
+/**
+  * @brief  Get LSE oscillator drive capability
+  * @rmtoll BDCR         LSEDRV        LL_RCC_LSE_GetDriveCapability
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_LSEDRIVE_LOW
+  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
+  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
+  *         @arg @ref LL_RCC_LSEDRIVE_HIGH
+  */
+__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
+{
+  return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
+}
+
+/**
+  * @brief  Check if LSE oscillator Ready
+  * @rmtoll BDCR         LSERDY        LL_RCC_LSE_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
+{
+  return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY))?1UL:0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_LSI LSI
+  * @{
+  */
+
+/**
+  * @brief  Enable LSI Oscillator
+  * @rmtoll CSR          LSION         LL_RCC_LSI_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSI_Enable(void)
+{
+  SET_BIT(RCC->CSR, RCC_CSR_LSION);
+}
+
+/**
+  * @brief  Disable LSI Oscillator
+  * @rmtoll CSR          LSION         LL_RCC_LSI_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSI_Disable(void)
+{
+  CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
+}
+
+/**
+  * @brief  Check if LSI is Ready
+  * @rmtoll CSR          LSIRDY        LL_RCC_LSI_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
+{
+  return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY))?1UL:0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_System System
+  * @{
+  */
+
+/**
+  * @brief  Configure the system clock source
+  * @rmtoll CFGR         SW            LL_RCC_SetSysClkSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_PLL1
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
+}
+
+/**
+  * @brief  Get the system clock source
+  * @rmtoll CFGR         SWS           LL_RCC_GetSysClkSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_CSI
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL1
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
+}
+
+/**
+  * @brief  Configure the system wakeup clock source
+  * @rmtoll CFGR         STOPWUCK       LL_RCC_SetSysWakeUpClkSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_CSI
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSysWakeUpClkSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Source);
+}
+
+/**
+  * @brief  Get the system wakeup clock source
+  * @rmtoll CFGR         STOPWUCK           LL_RCC_GetSysWakeUpClkSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_CSI
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSysWakeUpClkSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK));
+}
+
+/**
+  * @brief  Configure the kernel wakeup clock source
+  * @rmtoll CFGR         STOPKERWUCK       LL_RCC_SetKerWakeUpClkSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_CSI
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetKerWakeUpClkSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, Source);
+}
+
+/**
+  * @brief  Get the kernel wakeup clock source
+  * @rmtoll CFGR         STOPKERWUCK           LL_RCC_GetKerWakeUpClkSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_CSI
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetKerWakeUpClkSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPKERWUCK));
+}
+
+/**
+  * @brief  Set System prescaler
+  * @rmtoll D1CFGR/CDCFGR1        D1CPRE/CDCPRE          LL_RCC_SetSysPrescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SYSCLK_DIV_1
+  *         @arg @ref LL_RCC_SYSCLK_DIV_2
+  *         @arg @ref LL_RCC_SYSCLK_DIV_4
+  *         @arg @ref LL_RCC_SYSCLK_DIV_8
+  *         @arg @ref LL_RCC_SYSCLK_DIV_16
+  *         @arg @ref LL_RCC_SYSCLK_DIV_64
+  *         @arg @ref LL_RCC_SYSCLK_DIV_128
+  *         @arg @ref LL_RCC_SYSCLK_DIV_256
+  *         @arg @ref LL_RCC_SYSCLK_DIV_512
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSysPrescaler(uint32_t Prescaler)
+{
+#if defined(RCC_D1CFGR_D1CPRE)
+  MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, Prescaler);
+#else
+  MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, Prescaler);
+#endif /* RCC_D1CFGR_D1CPRE */
+}
+
+/**
+  * @brief  Set AHB prescaler
+  * @rmtoll D1CFGR/CDCFGR1        HPRE         LL_RCC_SetAHBPrescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_AHB_DIV_1
+  *         @arg @ref LL_RCC_AHB_DIV_2
+  *         @arg @ref LL_RCC_AHB_DIV_4
+  *         @arg @ref LL_RCC_AHB_DIV_8
+  *         @arg @ref LL_RCC_AHB_DIV_16
+  *         @arg @ref LL_RCC_AHB_DIV_64
+  *         @arg @ref LL_RCC_AHB_DIV_128
+  *         @arg @ref LL_RCC_AHB_DIV_256
+  *         @arg @ref LL_RCC_AHB_DIV_512
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
+{
+#if defined(RCC_D1CFGR_HPRE)
+  MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, Prescaler);
+#else
+  MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, Prescaler);
+#endif /* RCC_D1CFGR_HPRE */
+}
+
+/**
+  * @brief  Set APB1 prescaler
+  * @rmtoll D2CFGR/CDCFGR2         D2PPRE1/CDPPRE1         LL_RCC_SetAPB1Prescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB1_DIV_1
+  *         @arg @ref LL_RCC_APB1_DIV_2
+  *         @arg @ref LL_RCC_APB1_DIV_4
+  *         @arg @ref LL_RCC_APB1_DIV_8
+  *         @arg @ref LL_RCC_APB1_DIV_16
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
+{
+#if defined(RCC_D2CFGR_D2PPRE1)
+  MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, Prescaler);
+#else
+  MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, Prescaler);
+#endif /* RCC_D2CFGR_D2PPRE1 */
+}
+
+/**
+  * @brief  Set APB2 prescaler
+  * @rmtoll D2CFGR/CDCFGR2         D2PPRE2/CDPPRE2         LL_RCC_SetAPB2Prescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB2_DIV_1
+  *         @arg @ref LL_RCC_APB2_DIV_2
+  *         @arg @ref LL_RCC_APB2_DIV_4
+  *         @arg @ref LL_RCC_APB2_DIV_8
+  *         @arg @ref LL_RCC_APB2_DIV_16
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
+{
+#if defined(RCC_D2CFGR_D2PPRE2)
+  MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, Prescaler);
+#else
+  MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, Prescaler);
+#endif /* RCC_D2CFGR_D2PPRE2 */
+}
+
+/**
+  * @brief  Set APB3 prescaler
+  * @rmtoll D1CFGR/CDCFGR1         D1PPRE/CDPPRE         LL_RCC_SetAPB3Prescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB3_DIV_1
+  *         @arg @ref LL_RCC_APB3_DIV_2
+  *         @arg @ref LL_RCC_APB3_DIV_4
+  *         @arg @ref LL_RCC_APB3_DIV_8
+  *         @arg @ref LL_RCC_APB3_DIV_16
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetAPB3Prescaler(uint32_t Prescaler)
+{
+#if defined(RCC_D1CFGR_D1PPRE)
+  MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, Prescaler);
+#else
+  MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, Prescaler);
+#endif /* RCC_D1CFGR_D1PPRE */
+}
+
+/**
+  * @brief  Set APB4 prescaler
+  * @rmtoll D3CFGR/SRDCFGR         D3PPRE/SRDPPRE         LL_RCC_SetAPB4Prescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB4_DIV_1
+  *         @arg @ref LL_RCC_APB4_DIV_2
+  *         @arg @ref LL_RCC_APB4_DIV_4
+  *         @arg @ref LL_RCC_APB4_DIV_8
+  *         @arg @ref LL_RCC_APB4_DIV_16
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetAPB4Prescaler(uint32_t Prescaler)
+{
+#if defined(RCC_D3CFGR_D3PPRE)
+  MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, Prescaler);
+#else
+  MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, Prescaler);
+#endif /* RCC_D3CFGR_D3PPRE */
+}
+
+/**
+  * @brief  Get System prescaler
+  * @rmtoll D1CFGR/CDCFGR1        D1CPRE/CDCPRE          LL_RCC_GetSysPrescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SYSCLK_DIV_1
+  *         @arg @ref LL_RCC_SYSCLK_DIV_2
+  *         @arg @ref LL_RCC_SYSCLK_DIV_4
+  *         @arg @ref LL_RCC_SYSCLK_DIV_8
+  *         @arg @ref LL_RCC_SYSCLK_DIV_16
+  *         @arg @ref LL_RCC_SYSCLK_DIV_64
+  *         @arg @ref LL_RCC_SYSCLK_DIV_128
+  *         @arg @ref LL_RCC_SYSCLK_DIV_256
+  *         @arg @ref LL_RCC_SYSCLK_DIV_512
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSysPrescaler(void)
+{
+#if defined(RCC_D1CFGR_D1CPRE)
+  return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_D1CPRE));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE));
+#endif /* RCC_D1CFGR_D1CPRE */
+}
+
+/**
+  * @brief  Get AHB prescaler
+  * @rmtoll D1CFGR/ CDCFGR1       HPRE         LL_RCC_GetAHBPrescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_AHB_DIV_1
+  *         @arg @ref LL_RCC_AHB_DIV_2
+  *         @arg @ref LL_RCC_AHB_DIV_4
+  *         @arg @ref LL_RCC_AHB_DIV_8
+  *         @arg @ref LL_RCC_AHB_DIV_16
+  *         @arg @ref LL_RCC_AHB_DIV_64
+  *         @arg @ref LL_RCC_AHB_DIV_128
+  *         @arg @ref LL_RCC_AHB_DIV_256
+  *         @arg @ref LL_RCC_AHB_DIV_512
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
+{
+#if defined(RCC_D1CFGR_HPRE)
+  return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_HPRE));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCFGR1, RCC_CDCFGR1_HPRE));
+#endif /* RCC_D1CFGR_HPRE */
+}
+
+/**
+  * @brief  Get APB1 prescaler
+  * @rmtoll D2CFGR/CDCFGR2         D2PPRE1/CDPPRE1         LL_RCC_GetAPB1Prescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_APB1_DIV_1
+  *         @arg @ref LL_RCC_APB1_DIV_2
+  *         @arg @ref LL_RCC_APB1_DIV_4
+  *         @arg @ref LL_RCC_APB1_DIV_8
+  *         @arg @ref LL_RCC_APB1_DIV_16
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
+{
+#if defined(RCC_D2CFGR_D2PPRE1)
+  return (uint32_t)(READ_BIT(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1));
+#endif /* RCC_D2CFGR_D2PPRE1 */
+}
+
+/**
+  * @brief  Get APB2 prescaler
+  * @rmtoll D2CFGR/CDCFGR2         D2PPRE2/CDPPRE2         LL_RCC_GetAPB2Prescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_APB2_DIV_1
+  *         @arg @ref LL_RCC_APB2_DIV_2
+  *         @arg @ref LL_RCC_APB2_DIV_4
+  *         @arg @ref LL_RCC_APB2_DIV_8
+  *         @arg @ref LL_RCC_APB2_DIV_16
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
+{
+#if defined(RCC_D2CFGR_D2PPRE2)
+  return (uint32_t)(READ_BIT(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2));
+#endif /* RCC_D2CFGR_D2PPRE2 */
+}
+
+/**
+  * @brief  Get APB3 prescaler
+  * @rmtoll D1CFGR/CDCFGR1         D1PPRE/CDPPRE         LL_RCC_GetAPB3Prescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_APB3_DIV_1
+  *         @arg @ref LL_RCC_APB3_DIV_2
+  *         @arg @ref LL_RCC_APB3_DIV_4
+  *         @arg @ref LL_RCC_APB3_DIV_8
+  *         @arg @ref LL_RCC_APB3_DIV_16
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetAPB3Prescaler(void)
+{
+#if defined(RCC_D1CFGR_D1PPRE)
+  return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_D1PPRE));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE));
+#endif /* RCC_D1CFGR_D1PPRE */
+}
+
+/**
+  * @brief  Get APB4 prescaler
+  * @rmtoll D3CFGR/SRDCFGR         D3PPRE/SRDPPRE         LL_RCC_GetAPB4Prescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_APB4_DIV_1
+  *         @arg @ref LL_RCC_APB4_DIV_2
+  *         @arg @ref LL_RCC_APB4_DIV_4
+  *         @arg @ref LL_RCC_APB4_DIV_8
+  *         @arg @ref LL_RCC_APB4_DIV_16
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetAPB4Prescaler(void)
+{
+#if defined(RCC_D3CFGR_D3PPRE)
+  return (uint32_t)(READ_BIT(RCC->D3CFGR, RCC_D3CFGR_D3PPRE));
+#else
+  return (uint32_t)(READ_BIT(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE));
+#endif /* RCC_D3CFGR_D3PPRE */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_MCO MCO
+  * @{
+  */
+
+/**
+  * @brief  Configure MCOx
+  * @rmtoll CFGR         MCO1          LL_RCC_ConfigMCO\n
+  *         CFGR         MCO1PRE       LL_RCC_ConfigMCO\n
+  *         CFGR         MCO2          LL_RCC_ConfigMCO\n
+  *         CFGR         MCO2PRE       LL_RCC_ConfigMCO
+  * @param  MCOxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_MCO1SOURCE_HSI
+  *         @arg @ref LL_RCC_MCO1SOURCE_LSE
+  *         @arg @ref LL_RCC_MCO1SOURCE_HSE
+  *         @arg @ref LL_RCC_MCO1SOURCE_PLL1QCLK
+  *         @arg @ref LL_RCC_MCO1SOURCE_HSI48
+  *         @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
+  *         @arg @ref LL_RCC_MCO2SOURCE_PLL2PCLK
+  *         @arg @ref LL_RCC_MCO2SOURCE_HSE
+  *         @arg @ref LL_RCC_MCO2SOURCE_PLL1PCLK
+  *         @arg @ref LL_RCC_MCO2SOURCE_CSI
+  *         @arg @ref LL_RCC_MCO2SOURCE_LSI
+  * @param  MCOxPrescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_MCO1_DIV_1
+  *         @arg @ref LL_RCC_MCO1_DIV_2
+  *         @arg @ref LL_RCC_MCO1_DIV_3
+  *         @arg @ref LL_RCC_MCO1_DIV_4
+  *         @arg @ref LL_RCC_MCO1_DIV_5
+  *         @arg @ref LL_RCC_MCO1_DIV_6
+  *         @arg @ref LL_RCC_MCO1_DIV_7
+  *         @arg @ref LL_RCC_MCO1_DIV_8
+  *         @arg @ref LL_RCC_MCO1_DIV_9
+  *         @arg @ref LL_RCC_MCO1_DIV_10
+  *         @arg @ref LL_RCC_MCO1_DIV_11
+  *         @arg @ref LL_RCC_MCO1_DIV_12
+  *         @arg @ref LL_RCC_MCO1_DIV_13
+  *         @arg @ref LL_RCC_MCO1_DIV_14
+  *         @arg @ref LL_RCC_MCO1_DIV_15
+  *         @arg @ref LL_RCC_MCO2_DIV_1
+  *         @arg @ref LL_RCC_MCO2_DIV_2
+  *         @arg @ref LL_RCC_MCO2_DIV_3
+  *         @arg @ref LL_RCC_MCO2_DIV_4
+  *         @arg @ref LL_RCC_MCO2_DIV_5
+  *         @arg @ref LL_RCC_MCO2_DIV_6
+  *         @arg @ref LL_RCC_MCO2_DIV_7
+  *         @arg @ref LL_RCC_MCO2_DIV_8
+  *         @arg @ref LL_RCC_MCO2_DIV_9
+  *         @arg @ref LL_RCC_MCO2_DIV_10
+  *         @arg @ref LL_RCC_MCO2_DIV_11
+  *         @arg @ref LL_RCC_MCO2_DIV_12
+  *         @arg @ref LL_RCC_MCO2_DIV_13
+  *         @arg @ref LL_RCC_MCO2_DIV_14
+  *         @arg @ref LL_RCC_MCO2_DIV_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
+{
+  MODIFY_REG(RCC->CFGR,  (MCOxSource << 16U) | (MCOxPrescaler << 16U), (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
+  * @{
+  */
+
+/**
+  * @brief  Configure periph clock source
+  * @rmtoll D2CCIP1R/CDCCIP1R        *     LL_RCC_SetClockSource\n
+  *         D2CCIP2R/CDCCIP2R        *     LL_RCC_SetClockSource\n
+  *         D3CCIPR/SRDCCIPR         *     LL_RCC_SetClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P  (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P  (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN  (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q  (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P  (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P  (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN  (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP  (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_SPDIF  (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q  (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF  (*)
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetClockSource(uint32_t ClkSource)
+{
+#if defined(RCC_D1CCIPR_FMCSEL)
+  register uint32_t * pReg = (uint32_t *)((uint32_t)&RCC->D1CCIPR + LL_CLKSOURCE_REG(ClkSource));
+#else
+  register uint32_t * pReg = (uint32_t *)((uint32_t)&RCC->CDCCIPR + LL_CLKSOURCE_REG(ClkSource));
+#endif /*  */
+  MODIFY_REG(*pReg, LL_CLKSOURCE_MASK(ClkSource), LL_CLKSOURCE_CONFIG(ClkSource));
+}
+
+/**
+  * @brief  Configure USARTx clock source
+  * @rmtoll D2CCIP2R / D2CCIP2R        USART16SEL     LL_RCC_SetUSARTClockSource\n
+  *         D2CCIP2R / D2CCIP2R        USART28SEL     LL_RCC_SetUSARTClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t ClkSource)
+{
+  LL_RCC_SetClockSource(ClkSource);
+}
+
+/**
+  * @brief  Configure LPUARTx clock source
+  * @rmtoll D3CCIPR / SRDCCIPR        LPUART1SEL     LL_RCC_SetLPUARTClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t ClkSource)
+{
+#if defined(RCC_D3CCIPR_LPUART1SEL)
+  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, ClkSource);
+#else
+  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL, ClkSource);
+#endif /* RCC_D3CCIPR_LPUART1SEL */
+}
+
+/**
+  * @brief  Configure I2Cx clock source
+  * @rmtoll D2CCIP2R / CDCCIP2R       I2C123SEL       LL_RCC_SetI2CClockSource\n
+  *         D3CCIPR / SRDCCIPR        I2C4SEL         LL_RCC_SetI2CClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t ClkSource)
+{
+  LL_RCC_SetClockSource(ClkSource);
+}
+
+/**
+  * @brief  Configure LPTIMx clock source
+  * @rmtoll D2CCIP2R / CDCCIP2R      LPTIM1SEL     LL_RCC_SetLPTIMClockSource
+  *         D3CCIPR  / SRDCCIPR      LPTIM2SEL     LL_RCC_SetLPTIMClockSource\n
+  *         D3CCIPR  / SRDCCIPR      LPTIM345SEL   LL_RCC_SetLPTIMClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t ClkSource)
+{
+  LL_RCC_SetClockSource(ClkSource);
+}
+
+/**
+  * @brief  Configure SAIx clock source
+  * @rmtoll D2CCIP1R / CDCCIP1R       SAI1SEL       LL_RCC_SetSAIClockSource\n
+  *         D2CCIP1R / CDCCIP1R       SAI23SEL      LL_RCC_SetSAIClockSource
+  *         D3CCIPR  / SRDCCIPR       SAI4ASEL      LL_RCC_SetSAI4xClockSource\n
+  *         D3CCIPR  / SRDCCIPR       SAI4BSEL      LL_RCC_SetSAI4xClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P  (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P  (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN  (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q  (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P  (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P  (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN  (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP  (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_SPDIF  (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q  (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF  (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t ClkSource)
+{
+  LL_RCC_SetClockSource(ClkSource);
+}
+
+/**
+  * @brief  Configure SDMMCx clock source
+  * @rmtoll D1CCIPR / CDCCIPR       SDMMCSEL      LL_RCC_SetSDMMCClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL2R
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t ClkSource)
+{
+#if defined(RCC_D1CCIPR_SDMMCSEL)
+  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, ClkSource);
+#else
+  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL, ClkSource);
+#endif /* RCC_D1CCIPR_SDMMCSEL */
+}
+
+/**
+  * @brief  Configure RNGx clock source
+  * @rmtoll D2CCIP2R / CDCCIP2R       RNGSEL      LL_RCC_SetRNGClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_LSI
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t ClkSource)
+{
+#if defined(RCC_D2CCIP2R_RNGSEL)
+  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, ClkSource);
+#else
+  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL, ClkSource);
+#endif /* RCC_D2CCIP2R_RNGSEL */
+}
+
+/**
+  * @brief  Configure USBx clock source
+  * @rmtoll D2CCIP2R / CDCCIP2R      USBSEL      LL_RCC_SetUSBClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_DISABLE
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t ClkSource)
+{
+#if defined(RCC_D2CCIP2R_USBSEL)
+  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, ClkSource);
+#else
+  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL, ClkSource);
+#endif /* RCC_D2CCIP2R_USBSEL */
+}
+
+/**
+  * @brief  Configure CECx clock source
+  * @rmtoll D2CCIP2R / CDCCIP2R         CECSEL        LL_RCC_SetCECClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_CEC_CLKSOURCE_CSI_DIV122
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t ClkSource)
+{
+#if defined(RCC_D2CCIP2R_CECSEL)
+  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, ClkSource);
+#else
+  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL, ClkSource);
+#endif /* RCC_D2CCIP2R_CECSEL */
+}
+
+#if defined(DSI)
+/**
+  * @brief  Configure DSIx clock source
+  * @rmtoll D1CCIPR         DSISEL        LL_RCC_SetDSIClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
+  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PLL2Q
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t ClkSource)
+{
+  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL, ClkSource);
+}
+#endif /* DSI */
+
+/**
+  * @brief  Configure DFSDMx Kernel clock source
+  * @rmtoll D2CCIP1R / CDCCIP1R         DFSDM1SEL        LL_RCC_SetDFSDMClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t ClkSource)
+{
+#if defined(RCC_D2CCIP1R_DFSDM1SEL)
+  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, ClkSource);
+#else
+  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, ClkSource);
+#endif /* RCC_D2CCIP1R_DFSDM1SEL */
+}
+
+#if defined(DFSDM2_BASE)
+/**
+  * @brief  Configure DFSDMx Kernel clock source
+  * @rmtoll SRDCCIPR                   DFSDM2SEL        LL_RCC_SetDFSDM2ClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetDFSDM2ClockSource(uint32_t ClkSource)
+{
+   MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL, ClkSource);
+}
+#endif /* DFSDM2 */
+
+/**
+  * @brief  Configure FMCx Kernel clock source
+  * @rmtoll D1CCIPR / CDCCIPR        FMCSEL        LL_RCC_SetFMCClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_FMC_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_FMC_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_FMC_CLKSOURCE_PLL2R
+  *         @arg @ref LL_RCC_FMC_CLKSOURCE_CLKP
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetFMCClockSource(uint32_t ClkSource)
+{
+#if defined(RCC_D1CCIPR_FMCSEL)
+  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, ClkSource);
+#else
+  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL, ClkSource);
+#endif /* RCC_D1CCIPR_FMCSEL */
+}
+
+#if defined(QUADSPI)
+/**
+  * @brief  Configure QSPIx Kernel clock source
+  * @rmtoll D1CCIPR         QSPISEL        LL_RCC_SetQSPIClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_QSPI_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL2R
+  *         @arg @ref LL_RCC_QSPI_CLKSOURCE_CLKP
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetQSPIClockSource(uint32_t ClkSource)
+{
+  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL, ClkSource);
+}
+#endif /* QUADSPI */
+
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+/**
+  * @brief  Configure OSPIx Kernel clock source
+  * @rmtoll D1CCIPR         OPISEL        LL_RCC_SetOSPIClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_OSPI_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL2R
+  *         @arg @ref LL_RCC_OSPI_CLKSOURCE_CLKP
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetOSPIClockSource(uint32_t ClkSource)
+{
+  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL, ClkSource);
+}
+#endif /* OCTOSPI1 || OCTOSPI2 */
+
+/**
+  * @brief  Configure CLKP Kernel clock source
+  * @rmtoll D1CCIPR / CDCCIPR         CKPERSEL        LL_RCC_SetCLKPClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetCLKPClockSource(uint32_t ClkSource)
+{
+#if defined(RCC_D1CCIPR_CKPERSEL)
+  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, ClkSource);
+#else
+  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL, ClkSource);
+#endif /* RCC_D1CCIPR_CKPERSEL */
+}
+
+/**
+  * @brief  Configure SPIx Kernel clock source
+  * @rmtoll D2CCIP1R / CDCCIP1R       SPI123SEL        LL_RCC_SetSPIClockSource\n
+  *         D2CCIP1R / CDCCIP1R       SPI45SEL         LL_RCC_SetSPIClockSource\n
+  *         D3CCIPR  / SRDCCIPR       SPI6SEL          LL_RCC_SetSPIClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSPIClockSource(uint32_t ClkSource)
+{
+  LL_RCC_SetClockSource(ClkSource);
+}
+
+/**
+  * @brief  Configure SPDIFx Kernel clock source
+  * @rmtoll D2CCIP1R / CDCCIP1R       SPDIFSEL        LL_RCC_SetSPDIFClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL2R
+  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_HSI
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSPDIFClockSource(uint32_t ClkSource)
+{
+#if defined(RCC_D2CCIP1R_SPDIFSEL)
+  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, ClkSource);
+#else
+  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL, ClkSource);
+#endif /* RCC_D2CCIP1R_SPDIFSEL */
+}
+
+/**
+  * @brief  Configure FDCANx Kernel clock source
+  * @rmtoll D2CCIP1R / CDCCIP1R      FDCANSEL        LL_RCC_SetFDCANClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2Q
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t ClkSource)
+{
+#if defined(RCC_D2CCIP1R_FDCANSEL)
+  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, ClkSource);
+#else
+  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL, ClkSource);
+#endif /* RCC_D2CCIP1R_FDCANSEL */
+}
+
+/**
+  * @brief  Configure SWPx Kernel clock source
+  * @rmtoll D2CCIP1R /  CDCCIP1R       SWPSEL        LL_RCC_SetSWPClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SWP_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_SWP_CLKSOURCE_HSI
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSWPClockSource(uint32_t ClkSource)
+{
+#if defined(RCC_D2CCIP1R_SWPSEL)
+  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, ClkSource);
+#else
+  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL, ClkSource);
+#endif /* RCC_D2CCIP1R_SWPSEL */
+}
+
+/**
+  * @brief  Configure ADCx Kernel clock source
+  * @rmtoll D3CCIPR / SRDCCIPR        ADCSEL        LL_RCC_SetADCClockSource
+  * @param  ClkSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_CLKP
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ClkSource)
+{
+#if defined(RCC_D3CCIPR_ADCSEL)
+  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, ClkSource);
+#else
+  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL, ClkSource);
+#endif /* RCC_D3CCIPR_ADCSEL */
+}
+
+/**
+  * @brief  Get periph clock source
+  * @rmtoll D1CCIPR  / CDCCIPR       *     LL_RCC_GetClockSource\n
+  *         D2CCIP1R / CDCCIP1R      *     LL_RCC_GetClockSource\n
+  *         D2CCIP2R / CDCCIP2R      *     LL_RCC_GetClockSource\n
+  *         D3CCIPR  / SRDCCIPR      *     LL_RCC_GetClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE (*)
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE (*)
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE (*)
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE (*)
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*)
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*)
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*)
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*)
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_CLKP (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*)
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetClockSource(uint32_t Periph)
+{
+#if defined(RCC_D1CCIPR_FMCSEL)
+  register const uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->D1CCIPR) + LL_CLKSOURCE_REG(Periph)));
+#else
+  register const uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->CDCCIPR) + LL_CLKSOURCE_REG(Periph)));
+#endif /* RCC_D1CCIPR_FMCSEL */
+  return (uint32_t) (Periph | (((READ_BIT(*pReg, LL_CLKSOURCE_MASK(Periph))) >> LL_CLKSOURCE_SHIFT(Periph)) << LL_RCC_CONFIG_SHIFT) );
+}
+
+/**
+  * @brief  Get USARTx clock source
+  * @rmtoll D2CCIP2R / CDCCIP2R      USART16SEL     LL_RCC_GetUSARTClockSource\n
+  *         D2CCIP2R / CDCCIP2R      USART28SEL     LL_RCC_GetUSARTClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t Periph)
+{
+  return LL_RCC_GetClockSource(Periph);
+}
+
+/**
+  * @brief  Get LPUART clock source
+  * @rmtoll D3CCIPR / SRDCCIPR       LPUART1SEL     LL_RCC_GetLPUARTClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+#if defined(RCC_D3CCIPR_LPUART1SEL)
+  return (uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL));
+#else
+  return (uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL));
+#endif  /* RCC_D3CCIPR_LPUART1SEL */
+}
+
+/**
+  * @brief  Get I2Cx clock source
+  * @rmtoll D2CCIP2R / CDCCIP2R     I2C123SEL       LL_RCC_GetI2CClockSource\n
+  *         D3CCIPR  / SRDCCIPR     I2C4SEL         LL_RCC_GetI2CClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t Periph)
+{
+  return LL_RCC_GetClockSource(Periph);
+}
+
+/**
+  * @brief  Get LPTIM clock source
+  * @rmtoll D2CCIP2R / CDCCIP2R      LPTIM1SEL     LL_RCC_GetLPTIMClockSource\n
+  *         D3CCIPR  / SRDCCIPR      LPTIM2SEL     LL_RCC_GetLPTIMClockSource\n
+  *         D3CCIPR  / SRDCCIPR      LPTIM345SEL   LL_RCC_GetLPTIMClockSource
+  * @param  Perihp This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t Periph)
+{
+  return LL_RCC_GetClockSource(Periph);
+}
+
+/**
+  * @brief  Get SAIx clock source
+  * @rmtoll D2CCIP1R / CDCCIP1R     SAI1SEL       LL_RCC_GetSAIClockSource\n
+  *         D2CCIP1R / CDCCIP1R     SAI23SEL      LL_RCC_GetSAIClockSource
+  *         D3CCIPR  / SRDCCIPR     SAI4ASEL      LL_RCC_GetSAIClockSource\n
+  *         D3CCIPR  / SRDCCIPR     SAI4BSEL      LL_RCC_GetSAIClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*)
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*)
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*)
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*)
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_SPDIF (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_CLKP (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*)
+  * 
+  *  (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t Periph)
+{
+  return LL_RCC_GetClockSource(Periph);
+}
+
+/**
+  * @brief  Get SDMMC clock source
+  * @rmtoll D1CCIPR / CDCCIPR      SDMMCSEL      LL_RCC_GetSDMMCClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SDMMC_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL2R
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+#if defined(RCC_D1CCIPR_SDMMCSEL)
+  return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL));
+#endif /* RCC_D1CCIPR_SDMMCSEL */
+}
+
+/**
+  * @brief  Get RNG clock source
+  * @rmtoll D2CCIP2R        RNGSEL      LL_RCC_GetRNGClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_LSI
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+#if defined(RCC_D2CCIP2R_RNGSEL)
+  return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL));
+#endif /* RCC_D2CCIP2R_RNGSEL */
+}
+
+/**
+  * @brief  Get USB clock source
+  * @rmtoll D2CCIP2R / CDCCIP2R      USBSEL      LL_RCC_GetUSBClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USB_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_DISABLE
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+#if defined(RCC_D2CCIP2R_USBSEL)
+  return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL));
+#endif /* RCC_D2CCIP2R_USBSEL */
+}
+
+/**
+  * @brief  Get CEC clock source
+  * @rmtoll D2CCIP2R / CDCCIP2R        CECSEL        LL_RCC_GetCECClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_CEC_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_CEC_CLKSOURCE_CSI_DIV122
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+#if defined(RCC_D2CCIP2R_CECSEL)
+  return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL));
+#endif  /* RCC_D2CCIP2R_CECSEL */
+}
+
+#if defined(DSI)
+/**
+  * @brief  Get DSI clock source
+  * @rmtoll D1CCIPR         DSISEL        LL_RCC_GetDSIClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DSI_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
+  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PLL2Q
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+  return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL));
+}
+#endif /* DSI */
+
+/**
+  * @brief  Get DFSDM Kernel clock source
+  * @rmtoll D2CCIP1R / CDCCIP1R         DFSDM1SEL        LL_RCC_GetDFSDMClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+#if defined(RCC_D2CCIP1R_DFSDM1SEL)
+  return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL));
+#endif /* RCC_D2CCIP1R_DFSDM1SEL */
+}
+
+#if defined(DFSDM2_BASE)
+/**
+  * @brief  Get DFSDM2 Kernel clock source
+  * @rmtoll SRDCCIPR         DFSDM2SEL        LL_RCC_GetDFSDM2ClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetDFSDM2ClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+  return (uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL));
+}
+#endif /* DFSDM2_BASE */
+
+/**
+  * @brief  Get FMC Kernel clock source
+  * @rmtoll D1CCIPR / D1CCIPR         FMCSEL        LL_RCC_GetFMCClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_FMC_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_FMC_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_FMC_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_FMC_CLKSOURCE_PLL2R
+  *         @arg @ref LL_RCC_FMC_CLKSOURCE_CLKP
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetFMCClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+#if defined(RCC_D1CCIPR_FMCSEL)
+  return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL));
+#endif /* RCC_D1CCIPR_FMCSEL */
+}
+
+#if defined(QUADSPI)
+/**
+  * @brief  Get QSPI Kernel clock source
+  * @rmtoll D1CCIPR / CDCCIPR      QSPISEL        LL_RCC_GetQSPIClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_QSPI_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_QSPI_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL2R
+  *         @arg @ref LL_RCC_QSPI_CLKSOURCE_CLKP
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetQSPIClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+  return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL));
+}
+#endif /* QUADSPI */
+
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+/**
+  * @brief  Get OSPI Kernel clock source
+  * @rmtoll CDCCIPR      OSPISEL        LL_RCC_GetOSPIClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_OSPI_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_OSPI_CLKSOURCE_HCLK
+  *         @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL2R
+  *         @arg @ref LL_RCC_OSPI_CLKSOURCE_CLKP
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetOSPIClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+  return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL));
+}
+#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
+
+/**
+  * @brief  Get CLKP Kernel clock source
+  * @rmtoll D1CCIPR / CDCCIPR       CKPERSEL        LL_RCC_GetCLKPClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetCLKPClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+#if defined(RCC_D1CCIPR_CKPERSEL)
+  return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL));
+#endif /* RCC_D1CCIPR_CKPERSEL */
+}
+
+/**
+  * @brief  Get SPIx Kernel clock source
+  * @rmtoll D2CCIP1R / CDCCIP1R     SPI123SEL       LL_RCC_GetSPIClockSource\n
+  *         D2CCIP1R / CDCCIP1R     SPI45SEL        LL_RCC_GetSPIClockSource\n
+  *         D3CCIPR  / SRDCCIPR     SPI6SEL         LL_RCC_GetSPIClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*)
+  *
+  *         (*) value not defined in all stm32h7xx lines.
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSPIClockSource(uint32_t Periph)
+{
+  return LL_RCC_GetClockSource(Periph);
+}
+
+/**
+  * @brief  Get SPDIF Kernel clock source
+  * @rmtoll D2CCIP1R / CDCCIP1R      SPDIFSEL        LL_RCC_GetSPDIFClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL2R
+  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_HSI
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSPDIFClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+#if defined(RCC_D2CCIP1R_SPDIFSEL)
+  return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL));
+#endif /* RCC_D2CCIP1R_SPDIFSEL */
+}
+
+/**
+  * @brief  Get FDCAN Kernel clock source
+  * @rmtoll D2CCIP1R / CDCCIP1R       FDCANSEL        LL_RCC_GetFDCANClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1Q
+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2Q
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+#if defined(RCC_D2CCIP1R_FDCANSEL)
+  return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL));
+#endif /* RCC_D2CCIP1R_FDCANSEL */
+}
+
+/**
+  * @brief  Get SWP Kernel clock source
+  * @rmtoll D2CCIP1R / CDCCIP1R       SWPSEL        LL_RCC_GetSWPClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SWP_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SWP_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_SWP_CLKSOURCE_HSI
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSWPClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+#if defined(RCC_D2CCIP1R_SWPSEL)
+  return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL));
+#else
+  return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL));
+#endif /* RCC_D2CCIP1R_SWPSEL */
+}
+
+/**
+  * @brief  Get ADC Kernel clock source
+  * @rmtoll D3CCIPR / SRDCCIPR       ADCSEL        LL_RCC_GetADCClockSource
+  * @param  Periph This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLL2P
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLL3R
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_CLKP
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t Periph)
+{
+  UNUSED(Periph);
+#if defined (RCC_D3CCIPR_ADCSEL)
+  return (uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL));
+#else
+  return (uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL));
+#endif /* RCC_D3CCIPR_ADCSEL */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_RTC RTC
+  * @{
+  */
+
+/**
+  * @brief  Set RTC Clock Source
+  * @note   Once the RTC clock source has been selected, it cannot be changed anymore unless
+  *         the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
+  *         set). The BDRST bit can be used to reset them.
+  * @rmtoll BDCR         RTCSEL        LL_RCC_SetRTCClockSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
+}
+
+/**
+  * @brief  Get RTC Clock Source
+  * @rmtoll BDCR         RTCSEL        LL_RCC_GetRTCClockSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
+}
+
+/**
+  * @brief  Enable RTC
+  * @rmtoll BDCR         RTCEN         LL_RCC_EnableRTC
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableRTC(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
+}
+
+/**
+  * @brief  Disable RTC
+  * @rmtoll BDCR         RTCEN         LL_RCC_DisableRTC
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableRTC(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
+}
+
+/**
+  * @brief  Check if RTC has been enabled or not
+  * @rmtoll BDCR         RTCEN         LL_RCC_IsEnabledRTC
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
+{
+  return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN))?1UL:0UL);
+}
+
+/**
+  * @brief  Force the Backup domain reset
+  * @rmtoll BDCR         BDRST / VSWRST         LL_RCC_ForceBackupDomainReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
+}
+
+/**
+  * @brief  Release the Backup domain reset
+  * @rmtoll BDCR         BDRST / VSWRST          LL_RCC_ReleaseBackupDomainReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
+{
+#if defined(RCC_BDCR_BDRST)
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
+#else
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_VSWRST);
+#endif /* RCC_BDCR_BDRST */
+}
+
+/**
+  * @brief  Set HSE Prescalers for RTC Clock
+  * @rmtoll CFGR         RTCPRE        LL_RCC_SetRTC_HSEPrescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_RTC_NOCLOCK
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_2
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_3
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_4
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_5
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_6
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_7
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_8
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_9
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_10
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_11
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_12
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_13
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_14
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_15
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_16
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_17
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_18
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_19
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_20
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_21
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_22
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_23
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_24
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_25
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_26
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_27
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_28
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_29
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_30
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_31
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_32
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_33
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_34
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_35
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_36
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_37
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_38
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_39
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_40
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_41
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_42
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_43
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_44
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_45
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_46
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_47
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_48
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_49
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_50
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_51
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_52
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_53
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_54
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_55
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_56
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_57
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_58
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_59
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_60
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_61
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_62
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_63
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler);
+}
+
+/**
+  * @brief  Get HSE Prescalers for RTC Clock
+  * @rmtoll CFGR         RTCPRE        LL_RCC_GetRTC_HSEPrescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_RTC_NOCLOCK
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_2
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_3
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_4
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_5
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_6
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_7
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_8
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_9
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_10
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_11
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_12
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_13
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_14
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_15
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_16
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_17
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_18
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_19
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_20
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_21
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_22
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_23
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_24
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_25
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_26
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_27
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_28
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_29
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_30
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_31
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_32
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_33
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_34
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_35
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_36
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_37
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_38
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_39
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_40
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_41
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_42
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_43
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_44
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_45
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_46
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_47
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_48
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_49
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_50
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_51
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_52
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_53
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_54
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_55
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_56
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_57
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_58
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_59
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_60
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_61
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_62
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_63
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM
+  * @{
+  */
+
+/**
+  * @brief  Set Timers Clock Prescalers
+  * @rmtoll CFGR         TIMPRE        LL_RCC_SetTIMPrescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_TIM_PRESCALER_TWICE
+  *         @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_TIMPRE, Prescaler);
+}
+
+/**
+  * @brief  Get Timers Clock Prescalers
+  * @rmtoll CFGR         TIMPRE        LL_RCC_GetTIMPrescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_TIM_PRESCALER_TWICE
+  *         @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_TIMPRE));
+}
+
+/**
+  * @}
+  */
+
+#if defined(HRTIM1)
+/** @defgroup RCC_LL_EF_HRTIM_SET_CLOCK_SOURCE HRTIM
+  * @{
+  */
+
+/**
+  * @brief  Set High Resolution Timers Clock Source
+  * @rmtoll CFGR         HRTIMSEL        LL_RCC_SetHRTIMClockSource
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_HRTIM_CLKSOURCE_TIM
+  *         @arg @ref LL_RCC_HRTIM_CLKSOURCE_CPU
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetHRTIMClockSource(uint32_t Prescaler)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_HRTIMSEL, Prescaler);
+}
+#endif /* HRTIM1 */
+
+#if defined(HRTIM1)
+/**
+  * @brief  Get High Resolution Timers Clock Source
+  * @rmtoll CFGR         HRTIMSEL        LL_RCC_GetHRTIMClockSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_HRTIM_CLKSOURCE_TIM
+  *         @arg @ref LL_RCC_HRTIM_CLKSOURCE_CPU
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetHRTIMClockSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HRTIMSEL));
+}
+/**
+  * @}
+  */
+#endif /* HRTIM1 */
+
+/** @defgroup RCC_LL_EF_PLL PLL
+  * @{
+  */
+
+/**
+  * @brief  Set the oscillator used as PLL clock source.
+  * @note   PLLSRC can be written only when All PLLs are disabled.
+  * @rmtoll PLLCKSELR      PLLSRC        LL_RCC_PLL_SetSource
+  * @param  PLLSource parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_CSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  *         @arg @ref LL_RCC_PLLSOURCE_NONE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_SetSource(uint32_t PLLSource)
+{
+  MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, PLLSource);
+}
+
+/**
+  * @brief  Get the oscillator used as PLL clock source.
+  * @rmtoll PLLCKSELR      PLLSRC        LL_RCC_PLL_GetSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_CSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  *         @arg @ref LL_RCC_PLLSOURCE_NONE
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC));
+}
+
+/**
+  * @brief  Enable PLL1
+  * @rmtoll CR           PLL1ON         LL_RCC_PLL1_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_PLL1ON);
+}
+
+/**
+  * @brief  Disable PLL1
+  * @note Cannot be disabled if the PLL1 clock is used as the system clock
+  * @rmtoll CR           PLL1ON         LL_RCC_PLL1_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON);
+}
+
+/**
+  * @brief  Check if PLL1 Ready
+  * @rmtoll CR           PLL1RDY        LL_RCC_PLL1_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL1_IsReady(void)
+{
+  return ((READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == (RCC_CR_PLL1RDY))?1UL:0UL);
+}
+
+/**
+  * @brief  Enable PLL1P
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLLCFGR           DIVP1EN         LL_RCC_PLL1P_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1P_Enable(void)
+{
+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN);
+}
+
+/**
+  * @brief  Enable PLL1Q
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLLCFGR           DIVQ1EN         LL_RCC_PLL1Q_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1Q_Enable(void)
+{
+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN);
+}
+
+/**
+  * @brief  Enable PLL1R
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLLCFGR           DIVR1EN         LL_RCC_PLL1R_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1R_Enable(void)
+{
+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN);
+}
+
+/**
+  * @brief  Enable PLL1 FRACN
+  * @rmtoll PLLCFGR           PLL1FRACEN         LL_RCC_PLL1FRACN_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1FRACN_Enable(void)
+{
+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN);
+}
+
+/**
+  * @brief  Check if PLL1 P is enabled
+  * @rmtoll PLLCFGR           DIVP1EN         LL_RCC_PLL1P_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL1P_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN) == RCC_PLLCFGR_DIVP1EN)?1UL:0UL);
+}
+
+/**
+  * @brief  Check if PLL1 Q is enabled
+  * @rmtoll PLLCFGR           DIVQ1EN         LL_RCC_PLL1Q_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL1Q_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN) == RCC_PLLCFGR_DIVQ1EN)?1UL:0UL);
+}
+
+/**
+  * @brief  Check if PLL1 R is enabled
+  * @rmtoll PLLCFGR           DIVR1EN         LL_RCC_PLL1R_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL1R_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN) == RCC_PLLCFGR_DIVR1EN)?1UL:0UL);
+}
+
+/**
+  * @brief  Check if PLL1 FRACN is enabled
+  * @rmtoll PLLCFGR           PLL1FRACEN         LL_RCC_PLL1FRACN_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL1FRACN_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN) == RCC_PLLCFGR_PLL1FRACEN)?1UL:0UL);
+}
+
+/**
+  * @brief  Disable PLL1P
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLLCFGR           DIVP1EN         LL_RCC_PLL1P_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1P_Disable(void)
+{
+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN);
+}
+
+/**
+  * @brief  Disable PLL1Q
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLLCFGR           DIVQ1EN         LL_RCC_PLL1Q_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1Q_Disable(void)
+{
+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN);
+}
+
+/**
+  * @brief  Disable PLL1R
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLLCFGR           DIVR1EN         LL_RCC_PLL1R_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1R_Disable(void)
+{
+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN);
+}
+
+/**
+  * @brief  Disable PLL1 FRACN
+  * @rmtoll PLLCFGR           PLL1FRACEN         LL_RCC_PLL1FRACN_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1FRACN_Disable(void)
+{
+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN);
+}
+
+/**
+  * @brief  Set PLL1 VCO OutputRange
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLLCFGR        PLL1VCOSEL       LL_RCC_PLL1_SetVCOOuputRange
+  * @param  VCORange This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLVCORANGE_WIDE
+  *         @arg @ref LL_RCC_PLLVCORANGE_MEDIUM
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1_SetVCOOutputRange(uint32_t VCORange)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, VCORange << RCC_PLLCFGR_PLL1VCOSEL_Pos);
+}
+
+/**
+  * @brief  Set PLL1 VCO Input Range
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLLCFGR        PLL1RGE       LL_RCC_PLL1_SetVCOInputRange
+  * @param  InputRange This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLINPUTRANGE_1_2
+  *         @arg @ref LL_RCC_PLLINPUTRANGE_2_4
+  *         @arg @ref LL_RCC_PLLINPUTRANGE_4_8
+  *         @arg @ref LL_RCC_PLLINPUTRANGE_8_16
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL1_SetVCOInputRange(uint32_t InputRange)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, InputRange << RCC_PLLCFGR_PLL1RGE_Pos);
+}
+
+/**
+  * @brief  Get PLL1 N Coefficient
+  * @rmtoll PLL1DIVR        N1          LL_RCC_PLL1_GetN
+  * @retval A value between 4 and 512
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL1_GetN(void)
+{
+  return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_N1) >>  RCC_PLL1DIVR_N1_Pos) + 1UL);
+}
+
+/**
+  * @brief  Get PLL1 M Coefficient
+  * @rmtoll PLLCKSELR       DIVM1          LL_RCC_PLL1_GetM
+  * @retval A value between 0 and 63
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL1_GetM(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1) >>  RCC_PLLCKSELR_DIVM1_Pos);
+}
+
+/**
+  * @brief  Get PLL1 P Coefficient
+  * @rmtoll PLL1DIVR        P1          LL_RCC_PLL1_GetP
+  * @retval A value between 2 and 128
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL1_GetP(void)
+{
+  return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_P1) >>  RCC_PLL1DIVR_P1_Pos) + 1UL);
+}
+
+/**
+  * @brief  Get PLL1 Q Coefficient
+  * @rmtoll PLL1DIVR        Q1          LL_RCC_PLL1_GetQ
+  * @retval A value between 1 and 128
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL1_GetQ(void)
+{
+  return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_Q1) >>  RCC_PLL1DIVR_Q1_Pos) + 1UL);
+}
+
+/**
+  * @brief  Get PLL1 R Coefficient
+  * @rmtoll PLL1DIVR        R1          LL_RCC_PLL1_GetR
+  * @retval A value between 1 and 128
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL1_GetR(void)
+{
+  return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_R1) >>  RCC_PLL1DIVR_R1_Pos) + 1UL);
+}
+
+/**
+  * @brief  Get PLL1 FRACN Coefficient
+  * @rmtoll PLL1FRACR      FRACN1          LL_RCC_PLL1_GetFRACN
+  * @retval A value between 0 and 8191 (0x1FFF)
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL1_GetFRACN(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1) >>  RCC_PLL1FRACR_FRACN1_Pos);
+}
+
+/**
+  * @brief  Set PLL1 N Coefficient
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLL1DIVR        N1          LL_RCC_PLL1_SetN
+  * @param  N parameter can be a value between 4 and 512
+  */
+__STATIC_INLINE void LL_RCC_PLL1_SetN(uint32_t N)
+{
+  MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_N1, (N-1UL) << RCC_PLL1DIVR_N1_Pos);
+}
+
+/**
+  * @brief  Set PLL1 M Coefficient
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLLCKSELR       DIVM1          LL_RCC_PLL1_SetM
+  * @param  M parameter can be a value between 0 and 63
+  */
+__STATIC_INLINE void LL_RCC_PLL1_SetM(uint32_t M)
+{
+  MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1, M << RCC_PLLCKSELR_DIVM1_Pos);
+}
+
+/**
+  * @brief  Set PLL1 P Coefficient
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLL1DIVR        P1          LL_RCC_PLL1_SetP
+  * @param  P parameter can be a value between 2 and 128 (ODD division factor not supportted)
+  */
+__STATIC_INLINE void LL_RCC_PLL1_SetP(uint32_t P)
+{
+  MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_P1, (P-1UL) << RCC_PLL1DIVR_P1_Pos);
+}
+
+/**
+  * @brief  Set PLL1 Q Coefficient
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLL1DIVR        Q1          LL_RCC_PLL1_SetQ
+  * @param  Q parameter can be a value between 1 and 128
+  */
+__STATIC_INLINE void LL_RCC_PLL1_SetQ(uint32_t Q)
+{
+  MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_Q1, (Q-1UL) << RCC_PLL1DIVR_Q1_Pos);
+}
+
+/**
+  * @brief  Set PLL1 R Coefficient
+  * @note   This API shall be called only when PLL1 is disabled.
+  * @rmtoll PLL1DIVR        R1          LL_RCC_PLL1_SetR
+  * @param  R parameter can be a value between 1 and 128
+  */
+__STATIC_INLINE void LL_RCC_PLL1_SetR(uint32_t R)
+{
+  MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_R1, (R-1UL) << RCC_PLL1DIVR_R1_Pos);
+}
+
+/**
+  * @brief  Set PLL1 FRACN Coefficient
+  * @rmtoll PLL1FRACR        FRACN1          LL_RCC_PLL1_SetFRACN
+  * @param  FRACN parameter can be a value between 0 and 8191 (0x1FFF)
+  */
+__STATIC_INLINE void LL_RCC_PLL1_SetFRACN(uint32_t FRACN)
+{
+  MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, FRACN << RCC_PLL1FRACR_FRACN1_Pos);
+}
+
+/**
+  * @brief  Enable PLL2
+  * @rmtoll CR           PLL2ON         LL_RCC_PLL2_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_PLL2ON);
+}
+
+/**
+  * @brief  Disable PLL2
+  * @note Cannot be disabled if the PLL2 clock is used as the system clock
+  * @rmtoll CR           PLL2ON         LL_RCC_PLL2_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
+}
+
+/**
+  * @brief  Check if PLL2 Ready
+  * @rmtoll CR           PLL2RDY        LL_RCC_PLL2_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void)
+{
+  return ((READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == (RCC_CR_PLL2RDY))?1UL:0UL);
+}
+
+/**
+  * @brief  Enable PLL2P
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLLCFGR           DIVP2EN         LL_RCC_PLL2P_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2P_Enable(void)
+{
+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN);
+}
+
+/**
+  * @brief  Enable PLL2Q
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLLCFGR           DIVQ2EN         LL_RCC_PLL2Q_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2Q_Enable(void)
+{
+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN);
+}
+
+/**
+  * @brief  Enable PLL2R
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLLCFGR           DIVR2EN         LL_RCC_PLL2R_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2R_Enable(void)
+{
+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN);
+}
+
+/**
+  * @brief  Enable PLL2 FRACN
+  * @rmtoll PLLCFGR           PLL2FRACEN         LL_RCC_PLL2FRACN_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2FRACN_Enable(void)
+{
+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN);
+}
+
+/**
+  * @brief  Check if PLL2 P is enabled
+  * @rmtoll PLLCFGR           DIVP2EN         LL_RCC_PLL2P_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL2P_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN) == RCC_PLLCFGR_DIVP2EN)?1UL:0UL);
+}
+
+/**
+  * @brief  Check if PLL2 Q is enabled
+  * @rmtoll PLLCFGR           DIVQ2EN         LL_RCC_PLL2Q_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL2Q_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN) == RCC_PLLCFGR_DIVQ2EN)?1UL:0UL);
+}
+
+/**
+  * @brief  Check if PLL2 R is enabled
+  * @rmtoll PLLCFGR           DIVR2EN         LL_RCC_PLL2R_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL2R_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN) == RCC_PLLCFGR_DIVR2EN)?1UL:0UL);
+}
+
+/**
+  * @brief  Check if PLL2 FRACN is enabled
+  * @rmtoll PLLCFGR           PLL2FRACEN         LL_RCC_PLL2FRACN_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL2FRACN_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) == RCC_PLLCFGR_PLL2FRACEN)?1UL:0UL);
+}
+
+/**
+  * @brief  Disable PLL2P
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLLCFGR           DIVP2EN         LL_RCC_PLL2P_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2P_Disable(void)
+{
+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN);
+}
+
+/**
+  * @brief  Disable PLL2Q
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLLCFGR           DIVQ2EN         LL_RCC_PLL2Q_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2Q_Disable(void)
+{
+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN);
+}
+
+/**
+  * @brief  Disable PLL2R
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLLCFGR           DIVR2EN         LL_RCC_PLL2R_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2R_Disable(void)
+{
+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN);
+}
+
+/**
+  * @brief  Disable PLL2 FRACN
+  * @rmtoll PLLCFGR           PLL2FRACEN         LL_RCC_PLL2FRACN_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2FRACN_Disable(void)
+{
+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN);
+}
+
+/**
+  * @brief  Set PLL2 VCO OutputRange
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLLCFGR        PLL2VCOSEL       LL_RCC_PLL2_SetVCOOuputRange
+  * @param  VCORange This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLVCORANGE_WIDE
+  *         @arg @ref LL_RCC_PLLVCORANGE_MEDIUM
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2_SetVCOOutputRange(uint32_t VCORange)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, VCORange << RCC_PLLCFGR_PLL2VCOSEL_Pos);
+}
+
+/**
+  * @brief  Set PLL2 VCO Input Range
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLLCFGR        PLL2RGE       LL_RCC_PLL2_SetVCOInputRange
+  * @param  InputRange This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLINPUTRANGE_1_2
+  *         @arg @ref LL_RCC_PLLINPUTRANGE_2_4
+  *         @arg @ref LL_RCC_PLLINPUTRANGE_4_8
+  *         @arg @ref LL_RCC_PLLINPUTRANGE_8_16
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL2_SetVCOInputRange(uint32_t InputRange)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, InputRange << RCC_PLLCFGR_PLL2RGE_Pos);
+}
+
+/**
+  * @brief  Get PLL2 N Coefficient
+  * @rmtoll PLL2DIVR        N2          LL_RCC_PLL2_GetN
+  * @retval A value between 4 and 512
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL2_GetN(void)
+{
+  return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_N2) >>  RCC_PLL2DIVR_N2_Pos) + 1UL);
+}
+
+/**
+  * @brief  Get PLL2 M Coefficient
+  * @rmtoll PLLCKSELR       DIVM2          LL_RCC_PLL2_GetM
+  * @retval A value between 0 and 63
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL2_GetM(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM2) >>  RCC_PLLCKSELR_DIVM2_Pos);
+}
+
+/**
+  * @brief  Get PLL2 P Coefficient
+  * @rmtoll PLL2DIVR        P2          LL_RCC_PLL2_GetP
+  * @retval A value between 1 and 128
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL2_GetP(void)
+{
+  return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_P2) >>  RCC_PLL2DIVR_P2_Pos) + 1UL);
+}
+
+/**
+  * @brief  Get PLL2 Q Coefficient
+  * @rmtoll PLL2DIVR        Q2          LL_RCC_PLL2_GetQ
+  * @retval A value between 1 and 128
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL2_GetQ(void)
+{
+  return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_Q2) >>  RCC_PLL2DIVR_Q2_Pos) + 1UL);
+}
+
+/**
+  * @brief  Get PLL2 R Coefficient
+  * @rmtoll PLL2DIVR        R2          LL_RCC_PLL2_GetR
+  * @retval A value between 1 and 128
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL2_GetR(void)
+{
+  return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_R2) >>  RCC_PLL2DIVR_R2_Pos) + 1UL);
+}
+
+/**
+  * @brief  Get PLL2 FRACN Coefficient
+  * @rmtoll PLL2FRACR      FRACN2          LL_RCC_PLL2_GetFRACN
+  * @retval A value between 0 and 8191 (0x1FFF)
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL2_GetFRACN(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2) >>  RCC_PLL2FRACR_FRACN2_Pos);
+}
+
+/**
+  * @brief  Set PLL2 N Coefficient
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLL2DIVR        N2          LL_RCC_PLL2_SetN
+  * @param  N parameter can be a value between 4 and 512
+  */
+__STATIC_INLINE void LL_RCC_PLL2_SetN(uint32_t N)
+{
+  MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_N2, (N-1UL) << RCC_PLL2DIVR_N2_Pos);
+}
+
+/**
+  * @brief  Set PLL2 M Coefficient
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLLCKSELR       DIVM2          LL_RCC_PLL2_SetM
+  * @param  M parameter can be a value between 0 and 63
+  */
+__STATIC_INLINE void LL_RCC_PLL2_SetM(uint32_t M)
+{
+  MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM2, M << RCC_PLLCKSELR_DIVM2_Pos);
+}
+
+/**
+  * @brief  Set PLL2 P Coefficient
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLL2DIVR        P2          LL_RCC_PLL2_SetP
+  * @param  P parameter can be a value between 1 and 128
+  */
+__STATIC_INLINE void LL_RCC_PLL2_SetP(uint32_t P)
+{
+  MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_P2, (P-1UL) << RCC_PLL2DIVR_P2_Pos);
+}
+
+/**
+  * @brief  Set PLL2 Q Coefficient
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLL2DIVR        Q2          LL_RCC_PLL2_SetQ
+  * @param  Q parameter can be a value between 1 and 128
+  */
+__STATIC_INLINE void LL_RCC_PLL2_SetQ(uint32_t Q)
+{
+  MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_Q2, (Q-1UL) << RCC_PLL2DIVR_Q2_Pos);
+}
+
+/**
+  * @brief  Set PLL2 R Coefficient
+  * @note   This API shall be called only when PLL2 is disabled.
+  * @rmtoll PLL2DIVR        R2          LL_RCC_PLL2_SetR
+  * @param  R parameter can be a value between 1 and 128
+  */
+__STATIC_INLINE void LL_RCC_PLL2_SetR(uint32_t R)
+{
+  MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_R2, (R-1UL) << RCC_PLL2DIVR_R2_Pos);
+}
+
+/**
+  * @brief  Set PLL2 FRACN Coefficient
+  * @rmtoll PLL2FRACR        FRACN2          LL_RCC_PLL2_SetFRACN
+  * @param  FRACN parameter can be a value between 0 and 8191 (0x1FFF)
+  */
+__STATIC_INLINE void LL_RCC_PLL2_SetFRACN(uint32_t FRACN)
+{
+  MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2, FRACN << RCC_PLL2FRACR_FRACN2_Pos);
+}
+
+/**
+  * @brief  Enable PLL3
+  * @rmtoll CR           PLL3ON         LL_RCC_PLL3_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_PLL3ON);
+}
+
+/**
+  * @brief  Disable PLL3
+  * @note Cannot be disabled if the PLL3 clock is used as the system clock
+  * @rmtoll CR           PLL3ON         LL_RCC_PLL3_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
+}
+
+/**
+  * @brief  Check if PLL3 Ready
+  * @rmtoll CR           PLL3RDY        LL_RCC_PLL3_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL3_IsReady(void)
+{
+  return ((READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == (RCC_CR_PLL3RDY))?1UL:0UL);
+}
+
+/**
+  * @brief  Enable PLL3P
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLLCFGR           DIVP3EN         LL_RCC_PLL3P_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3P_Enable(void)
+{
+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN);
+}
+
+/**
+  * @brief  Enable PLL3Q
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLLCFGR           DIVQ3EN         LL_RCC_PLL3Q_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3Q_Enable(void)
+{
+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN);
+}
+
+/**
+  * @brief  Enable PLL3R
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLLCFGR           DIVR3EN         LL_RCC_PLL3R_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3R_Enable(void)
+{
+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN);
+}
+
+/**
+  * @brief  Enable PLL3 FRACN
+  * @rmtoll PLLCFGR           PLL3FRACEN         LL_RCC_PLL3FRACN_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3FRACN_Enable(void)
+{
+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN);
+}
+
+/**
+  * @brief  Check if PLL3 P is enabled
+  * @rmtoll PLLCFGR           DIVP3EN         LL_RCC_PLL3P_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL3P_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN) == RCC_PLLCFGR_DIVP3EN)?1UL:0UL);
+}
+
+/**
+  * @brief  Check if PLL3 Q is enabled
+  * @rmtoll PLLCFGR           DIVQ3EN         LL_RCC_PLL3Q_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL3Q_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN) == RCC_PLLCFGR_DIVQ3EN)?1UL:0UL);
+}
+
+/**
+  * @brief  Check if PLL3 R is enabled
+  * @rmtoll PLLCFGR           DIVR3EN         LL_RCC_PLL3R_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL3R_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN) == RCC_PLLCFGR_DIVR3EN)?1UL:0UL);
+}
+
+/**
+  * @brief  Check if PLL3 FRACN is enabled
+  * @rmtoll PLLCFGR           PLL3FRACEN         LL_RCC_PLL3FRACN_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL3FRACN_IsEnabled(void)
+{
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) == RCC_PLLCFGR_PLL3FRACEN)?1UL:0UL);
+}
+
+/**
+  * @brief  Disable PLL3P
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLLCFGR           DIVP2EN         LL_RCC_PLL3P_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3P_Disable(void)
+{
+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN);
+}
+
+/**
+  * @brief  Disable PLL3Q
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLLCFGR           DIVQ3EN         LL_RCC_PLL3Q_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3Q_Disable(void)
+{
+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN);
+}
+
+/**
+  * @brief  Disable PLL3R
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLLCFGR           DIVR3EN         LL_RCC_PLL3R_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3R_Disable(void)
+{
+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN);
+}
+
+/**
+  * @brief  Disable PLL3 FRACN
+  * @rmtoll PLLCFGR           PLL3FRACEN         LL_RCC_PLL3FRACN_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3FRACN_Disable(void)
+{
+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN);
+}
+
+/**
+  * @brief  Set PLL3 VCO OutputRange
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLLCFGR        PLL3VCOSEL       LL_RCC_PLL3_SetVCOOuputRange
+  * @param  VCORange This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLVCORANGE_WIDE
+  *         @arg @ref LL_RCC_PLLVCORANGE_MEDIUM
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3_SetVCOOutputRange(uint32_t VCORange)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, VCORange << RCC_PLLCFGR_PLL3VCOSEL_Pos);
+}
+
+/**
+  * @brief  Set PLL3 VCO Input Range
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLLCFGR        PLL3RGE       LL_RCC_PLL3_SetVCOInputRange
+  * @param  InputRange This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLINPUTRANGE_1_2
+  *         @arg @ref LL_RCC_PLLINPUTRANGE_2_4
+  *         @arg @ref LL_RCC_PLLINPUTRANGE_4_8
+  *         @arg @ref LL_RCC_PLLINPUTRANGE_8_16
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL3_SetVCOInputRange(uint32_t InputRange)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, InputRange << RCC_PLLCFGR_PLL3RGE_Pos);
+}
+
+/**
+  * @brief  Get PLL3 N Coefficient
+  * @rmtoll PLL3DIVR        N3          LL_RCC_PLL3_GetN
+  * @retval A value between 4 and 512
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL3_GetN(void)
+{
+  return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_N3) >>  RCC_PLL3DIVR_N3_Pos) + 1UL);
+}
+
+/**
+  * @brief  Get PLL3 M Coefficient
+  * @rmtoll PLLCKSELR       DIVM3          LL_RCC_PLL3_GetM
+  * @retval A value between 0 and 63
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL3_GetM(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM3) >>  RCC_PLLCKSELR_DIVM3_Pos);
+}
+
+/**
+  * @brief  Get PLL3 P Coefficient
+  * @rmtoll PLL3DIVR        P3          LL_RCC_PLL3_GetP
+  * @retval A value between 1 and 128
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL3_GetP(void)
+{
+  return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_P3) >>  RCC_PLL3DIVR_P3_Pos) + 1UL);
+}
+
+/**
+  * @brief  Get PLL3 Q Coefficient
+  * @rmtoll PLL3DIVR        Q3          LL_RCC_PLL3_GetQ
+  * @retval A value between 1 and 128
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL3_GetQ(void)
+{
+  return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_Q3) >>  RCC_PLL3DIVR_Q3_Pos) + 1UL);
+}
+
+/**
+  * @brief  Get PLL3 R Coefficient
+  * @rmtoll PLL3DIVR        R3          LL_RCC_PLL3_GetR
+  * @retval A value between 1 and 128
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL3_GetR(void)
+{
+  return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_R3) >>  RCC_PLL3DIVR_R3_Pos) + 1UL);
+}
+
+/**
+  * @brief  Get PLL3 FRACN Coefficient
+  * @rmtoll PLL3FRACR      FRACN3          LL_RCC_PLL3_GetFRACN
+  * @retval A value between 0 and 8191 (0x1FFF)
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL3_GetFRACN(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3) >>  RCC_PLL3FRACR_FRACN3_Pos);
+}
+
+/**
+  * @brief  Set PLL3 N Coefficient
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLL3DIVR        N3          LL_RCC_PLL3_SetN
+  * @param  N parameter can be a value between 4 and 512
+  */
+__STATIC_INLINE void LL_RCC_PLL3_SetN(uint32_t N)
+{
+  MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_N3, (N-1UL) << RCC_PLL3DIVR_N3_Pos);
+}
+
+/**
+  * @brief  Set PLL3 M Coefficient
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLLCKSELR       DIVM3          LL_RCC_PLL3_SetM
+  * @param  M parameter can be a value between 0 and 63
+  */
+__STATIC_INLINE void LL_RCC_PLL3_SetM(uint32_t M)
+{
+  MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM3, M << RCC_PLLCKSELR_DIVM3_Pos);
+}
+
+/**
+  * @brief  Set PLL3 P Coefficient
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLL3DIVR        P3          LL_RCC_PLL3_SetP
+  * @param  P parameter can be a value between 1 and 128
+  */
+__STATIC_INLINE void LL_RCC_PLL3_SetP(uint32_t P)
+{
+  MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_P3, (P-1UL) << RCC_PLL3DIVR_P3_Pos);
+}
+
+/**
+  * @brief  Set PLL3 Q Coefficient
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLL3DIVR        Q3          LL_RCC_PLL3_SetQ
+  * @param  Q parameter can be a value between 1 and 128
+  */
+__STATIC_INLINE void LL_RCC_PLL3_SetQ(uint32_t Q)
+{
+  MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_Q3, (Q-1UL) << RCC_PLL3DIVR_Q3_Pos);
+}
+
+/**
+  * @brief  Set PLL3 R Coefficient
+  * @note   This API shall be called only when PLL3 is disabled.
+  * @rmtoll PLL3DIVR        R3          LL_RCC_PLL3_SetR
+  * @param  R parameter can be a value between 1 and 128
+  */
+__STATIC_INLINE void LL_RCC_PLL3_SetR(uint32_t R)
+{
+  MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_R3, (R-1UL) << RCC_PLL3DIVR_R3_Pos);
+}
+
+/**
+  * @brief  Set PLL3 FRACN Coefficient
+  * @rmtoll PLL3FRACR        FRACN3          LL_RCC_PLL3_SetFRACN
+  * @param  FRACN parameter can be a value between 0 and 8191 (0x1FFF)
+  */
+__STATIC_INLINE void LL_RCC_PLL3_SetFRACN(uint32_t FRACN)
+{
+  MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, FRACN << RCC_PLL3FRACR_FRACN3_Pos);
+}
+
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
+  * @{
+  */
+
+/**
+  * @brief  Clear LSI ready interrupt flag
+  * @rmtoll CICR         LSIRDYC       LL_RCC_ClearFlag_LSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
+}
+
+/**
+  * @brief  Clear LSE ready interrupt flag
+  * @rmtoll CICR         LSERDYC       LL_RCC_ClearFlag_LSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
+}
+
+/**
+  * @brief  Clear HSI ready interrupt flag
+  * @rmtoll CICR         HSIRDYC       LL_RCC_ClearFlag_HSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
+}
+
+/**
+  * @brief  Clear HSE ready interrupt flag
+  * @rmtoll CICR         HSERDYC       LL_RCC_ClearFlag_HSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
+}
+
+/**
+  * @brief  Clear CSI ready interrupt flag
+  * @rmtoll CICR         CSIRDYC       LL_RCC_ClearFlag_CSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_CSIRDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_CSIRDYC);
+}
+
+/**
+  * @brief  Clear HSI48 ready interrupt flag
+  * @rmtoll CICR         HSI48RDYC       LL_RCC_ClearFlag_HSI48RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
+}
+
+/**
+  * @brief  Clear PLL1 ready interrupt flag
+  * @rmtoll CICR         PLL1RDYC       LL_RCC_ClearFlag_PLL1RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_PLL1RDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
+}
+
+/**
+  * @brief  Clear PLL2 ready interrupt flag
+  * @rmtoll CICR         PLL2RDYC       LL_RCC_ClearFlag_PLL2RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_PLL2RDYC);
+}
+
+/**
+  * @brief  Clear PLL3 ready interrupt flag
+  * @rmtoll CICR         PLL3RDYC       LL_RCC_ClearFlag_PLL3RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_PLL3RDY(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_PLL3RDYC);
+}
+
+/**
+  * @brief  Clear LSE Clock security system interrupt flag
+  * @rmtoll CICR         LSECSSC         LL_RCC_ClearFlag_LSECSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
+}
+
+/**
+  * @brief  Clear HSE Clock security system interrupt flag
+  * @rmtoll CICR         HSECSSC         LL_RCC_ClearFlag_HSECSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
+{
+  SET_BIT(RCC->CICR, RCC_CICR_HSECSSC);
+}
+
+/**
+  * @brief  Check if LSI ready interrupt occurred or not
+  * @rmtoll CIFR         LSIRDYF       LL_RCC_IsActiveFlag_LSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if LSE ready interrupt occurred or not
+  * @rmtoll CIFR         LSERDYF       LL_RCC_IsActiveFlag_LSERDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if HSI ready interrupt occurred or not
+  * @rmtoll CIFR         HSIRDYF       LL_RCC_IsActiveFlag_HSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if HSE ready interrupt occurred or not
+  * @rmtoll CIFR         HSERDYF       LL_RCC_IsActiveFlag_HSERDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if CSI ready interrupt occurred or not
+  * @rmtoll CIFR         CSIRDYF       LL_RCC_IsActiveFlag_CSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CSIRDY(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSIRDYF) == (RCC_CIFR_CSIRDYF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if HSI48 ready interrupt occurred or not
+  * @rmtoll CIFR         HSI48RDYF       LL_RCC_IsActiveFlag_HSI48RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if PLL1 ready interrupt occurred or not
+  * @rmtoll CIFR         PLLRDYF       LL_RCC_IsActiveFlag_PLL1RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL1RDY(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if PLL2 ready interrupt occurred or not
+  * @rmtoll CIFR         PLL2RDYF       LL_RCC_IsActiveFlag_PLL2RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL2RDYF) == (RCC_CIFR_PLL2RDYF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if PLL3 ready interrupt occurred or not
+  * @rmtoll CIFR         PLL3RDYF       LL_RCC_IsActiveFlag_PLL3RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL3RDY(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL3RDYF) == (RCC_CIFR_PLL3RDYF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if LSE Clock security system interrupt occurred or not
+  * @rmtoll CIFR         LSECSSF          LL_RCC_IsActiveFlag_LSECSS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if HSE Clock security system interrupt occurred or not
+  * @rmtoll CIFR         HSECSSF          LL_RCC_IsActiveFlag_HSECSS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
+{
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSECSSF) == (RCC_CIFR_HSECSSF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC flag Low Power D1 reset is set or not.
+  * @rmtoll RSR          LPWRRSTF       LL_RCC_IsActiveFlag_LPWRRST (*)\n
+  *         RSR          LPWR1RSTF      LL_RCC_IsActiveFlag_LPWRRST (**)
+  *
+  * (*) Only available for single core devices
+  * (**) Only available for Dual core devices
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
+{
+#if defined(DUAL_CORE)
+  return ((READ_BIT(RCC->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF))?1UL:0UL);
+#else
+  return ((READ_BIT(RCC->RSR, RCC_RSR_LPWRRSTF) == (RCC_RSR_LPWRRSTF))?1UL:0UL);
+#endif /*DUAL_CORE*/
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Check if RCC flag Low Power D2 reset is set or not.
+  * @rmtoll RSR          LPWR2RSTF      LL_RCC_IsActiveFlag_LPWR2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWR2RST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF))?1UL:0UL);
+}
+#endif  /*DUAL_CORE*/
+
+/**
+  * @brief  Check if RCC flag Window Watchdog 1 reset is set or not.
+  * @rmtoll RSR          WWDG1RSTF      LL_RCC_IsActiveFlag_WWDG1RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDG1RST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF))?1UL:0UL);
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Check if RCC flag Window Watchdog 2 reset is set or not.
+  * @rmtoll RSR          WWDG2RSTF      LL_RCC_IsActiveFlag_WWDG2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDG2RST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF))?1UL:0UL);
+}
+#endif  /*DUAL_CORE*/
+
+/**
+  * @brief  Check if RCC flag Independent Watchdog 1 reset is set or not.
+  * @rmtoll RSR          IWDG1RSTF      LL_RCC_IsActiveFlag_IWDG1RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDG1RST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF))?1UL:0UL);
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Check if RCC flag Independent Watchdog 2 reset is set or not.
+  * @rmtoll RSR          IWDG2RSTF      LL_RCC_IsActiveFlag_IWDG2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDG2RST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF))?1UL:0UL);
+}
+#endif  /*DUAL_CORE*/
+
+/**
+  * @brief  Check if RCC flag Software reset is set or not.
+  * @rmtoll RSR          SFTRSTF        LL_RCC_IsActiveFlag_SFTRST (*)\n
+  *         RSR          SFT1RSTF       LL_RCC_IsActiveFlag_SFTRST (**)
+  *
+  * (*) Only available for single core devices
+  * (**) Only available for Dual core devices
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
+{
+#if defined(DUAL_CORE)
+  return ((READ_BIT(RCC->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF))?1UL:0UL);
+#else
+  return ((READ_BIT(RCC->RSR, RCC_RSR_SFTRSTF) == (RCC_RSR_SFTRSTF))?1UL:0UL);
+#endif  /*DUAL_CORE*/
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Check if RCC flag Software reset is set or not.
+  * @rmtoll RSR          SFT2RSTF       LL_RCC_IsActiveFlag_SFT2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFT2RST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF))?1UL:0UL);
+}
+#endif  /*DUAL_CORE*/
+
+/**
+  * @brief  Check if RCC flag POR/PDR reset is set or not.
+  * @rmtoll RSR          PORRSTF       LL_RCC_IsActiveFlag_PORRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC flag Pin reset is set or not.
+  * @rmtoll RSR          PINRSTF       LL_RCC_IsActiveFlag_PINRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC flag BOR reset is set or not.
+  * @rmtoll RSR          BORRSTF       LL_RCC_IsActiveFlag_BORRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF))?1UL:0UL);
+}
+
+#if defined(RCC_RSR_D1RSTF)
+/**
+  * @brief  Check if RCC flag D1 reset is set or not.
+  * @rmtoll RSR          D1RSTF       LL_RCC_IsActiveFlag_D1RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_D1RST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF))?1UL:0UL);
+}
+#endif /* RCC_RSR_D1RSTF */
+
+#if defined(RCC_RSR_CDRSTF)
+/**
+  * @brief  Check if RCC flag CD reset is set or not.
+  * @rmtoll RSR          CDRSTF       LL_RCC_IsActiveFlag_CDRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CDRST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_CDRSTF) == (RCC_RSR_CDRSTF))?1UL:0UL);
+}
+#endif /* RCC_RSR_CDRSTF */
+
+#if defined(RCC_RSR_D2RSTF)
+/**
+  * @brief  Check if RCC flag D2 reset is set or not.
+  * @rmtoll RSR          D2RSTF       LL_RCC_IsActiveFlag_D2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_D2RST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF))?1UL:0UL);
+}
+#endif /* RCC_RSR_D2RSTF */
+
+#if defined(RCC_RSR_C1RSTF) || defined(RCC_RSR_CPURSTF)
+/**
+  * @brief  Check if RCC flag CPU reset is set or not.
+  * @rmtoll RSR          CPURSTF       LL_RCC_IsActiveFlag_CPURST (*)\n
+  *         RSR          C1RSTF        LL_RCC_IsActiveFlag_CPURST (**)
+  *
+  * (*) Only available for single core devices
+  * (**) Only available for Dual core devices
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CPURST(void)
+{
+#if defined(DUAL_CORE)
+  return ((READ_BIT(RCC->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF))?1UL:0UL);
+#else
+  return ((READ_BIT(RCC->RSR, RCC_RSR_CPURSTF) == (RCC_RSR_CPURSTF))?1UL:0UL);
+#endif/*DUAL_CORE*/
+}
+#endif /* defined(RCC_RSR_C1RSTF) || defined(RCC_RSR_CPURSTF) */
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Check if RCC flag CPU2 reset is set or not.
+  * @rmtoll RSR          C2RSTF       LL_RCC_IsActiveFlag_CPU2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CPU2RST(void)
+{
+  return ((READ_BIT(RCC->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF))?1UL:0UL);
+}
+#endif  /*DUAL_CORE*/
+
+/**
+  * @brief  Set RMVF bit to clear all reset flags.
+  * @rmtoll RSR          RMVF          LL_RCC_ClearResetFlags
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
+{
+  SET_BIT(RCC->RSR, RCC_RSR_RMVF);
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Check if RCC_C1 flag Low Power D1 reset is set or not.
+  * @rmtoll RSR          LPWR1RSTF      LL_C1_RCC_IsActiveFlag_LPWRRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_LPWRRST(void)
+{
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C1 flag Low Power D2 reset is set or not.
+  * @rmtoll RSR          LPWR2RSTF      LL_C1_RCC_IsActiveFlag_LPWR2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_LPWR2RST(void)
+{
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C1 flag Window Watchdog 1 reset is set or not.
+  * @rmtoll RSR          WWDG1RSTF      LL_C1_RCC_IsActiveFlag_WWDG1RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_WWDG1RST(void)
+{
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C1 flag Window Watchdog 2 reset is set or not.
+  * @rmtoll RSR          WWDG2RSTF      LL_C1_RCC_IsActiveFlag_WWDG2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_WWDG2RST(void)
+{
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C1 flag Independent Watchdog 1 reset is set or not.
+  * @rmtoll RSR          IWDG1RSTF      LL_C1_RCC_IsActiveFlag_IWDG1RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_IWDG1RST(void)
+{
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C1 flag Independent Watchdog 2 reset is set or not.
+  * @rmtoll RSR          IWDG2RSTF      LL_C1_RCC_IsActiveFlag_IWDG2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_IWDG2RST(void)
+{
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C1 flag Software reset is set or not.
+  * @rmtoll RSR          SFT1RSTF       LL_C1_RCC_IsActiveFlag_SFTRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_SFTRST(void)
+{
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C1 flag Software reset is set or not.
+  * @rmtoll RSR          SFT2RSTF       LL_C1_RCC_IsActiveFlag_SFT2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_SFT2RST(void)
+{
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C1 flag POR/PDR reset is set or not.
+  * @rmtoll RSR          PORRSTF       LL_C1_RCC_IsActiveFlag_PORRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_PORRST(void)
+{
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C1 flag Pin reset is set or not.
+  * @rmtoll RSR          PINRSTF       LL_C1_RCC_IsActiveFlag_PINRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_PINRST(void)
+{
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C1 flag BOR reset is set or not.
+  * @rmtoll RSR          BORRSTF       LL_C1_RCC_IsActiveFlag_BORRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_BORRST(void)
+{
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C1 flag D1 reset is set or not.
+  * @rmtoll RSR          D1RSTF       LL_C1_RCC_IsActiveFlag_D1RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_D1RST(void)
+{
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C1 flag D2 reset is set or not.
+  * @rmtoll RSR          D2RSTF       LL_C1_RCC_IsActiveFlag_D2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_D2RST(void)
+{
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C1 flag CPU reset is set or not.
+  * @rmtoll RSR          C1RSTF       LL_C1_RCC_IsActiveFlag_CPURST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_CPURST(void)
+{
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C1 flag CPU2 reset is set or not.
+  * @rmtoll RSR          C2RSTF       LL_C1_RCC_IsActiveFlag_CPU2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_CPU2RST(void)
+{
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Set RMVF bit to clear the reset flags.
+  * @rmtoll RSR          RMVF          LL_C1_RCC_ClearResetFlags
+  * @retval None
+  */
+__STATIC_INLINE void LL_C1_RCC_ClearResetFlags(void)
+{
+  SET_BIT(RCC_C1->RSR, RCC_RSR_RMVF);
+}
+
+/**
+  * @brief  Check if RCC_C2 flag Low Power D1 reset is set or not.
+  * @rmtoll RSR          LPWR1RSTF      LL_C2_RCC_IsActiveFlag_LPWRRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_LPWRRST(void)
+{
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C2 flag Low Power D2 reset is set or not.
+  * @rmtoll RSR          LPWR2RSTF      LL_C2_RCC_IsActiveFlag_LPWR2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_LPWR2RST(void)
+{
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C2 flag Window Watchdog 1 reset is set or not.
+  * @rmtoll RSR          WWDG1RSTF      LL_C2_RCC_IsActiveFlag_WWDG1RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_WWDG1RST(void)
+{
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C2 flag Window Watchdog 2 reset is set or not.
+  * @rmtoll RSR          WWDG2RSTF      LL_C2_RCC_IsActiveFlag_WWDG2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_WWDG2RST(void)
+{
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C2 flag Independent Watchdog 1 reset is set or not.
+  * @rmtoll RSR          IWDG1RSTF      LL_C2_RCC_IsActiveFlag_IWDG1RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_IWDG1RST(void)
+{
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C2 flag Independent Watchdog 2 reset is set or not.
+  * @rmtoll RSR          IWDG2RSTF      LL_C2_RCC_IsActiveFlag_IWDG2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_IWDG2RST(void)
+{
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C2 flag Software reset is set or not.
+  * @rmtoll RSR          SFT1RSTF       LL_C2_RCC_IsActiveFlag_SFTRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_SFTRST(void)
+{
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C2 flag Software reset is set or not.
+  * @rmtoll RSR          SFT2RSTF       LL_C2_RCC_IsActiveFlag_SFT2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_SFT2RST(void)
+{
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C2 flag POR/PDR reset is set or not.
+  * @rmtoll RSR          PORRSTF       LL_C2_RCC_IsActiveFlag_PORRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_PORRST(void)
+{
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C2 flag Pin reset is set or not.
+  * @rmtoll RSR          PINRSTF       LL_C2_RCC_IsActiveFlag_PINRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_PINRST(void)
+{
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C2 flag BOR reset is set or not.
+  * @rmtoll RSR          BORRSTF       LL_C2_RCC_IsActiveFlag_BORRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_BORRST(void)
+{
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C2 flag D1 reset is set or not.
+  * @rmtoll RSR          D1RSTF       LL_C2_RCC_IsActiveFlag_D1RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_D1RST(void)
+{
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C2 flag D2 reset is set or not.
+  * @rmtoll RSR          D2RSTF       LL_C2_RCC_IsActiveFlag_D2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_D2RST(void)
+{
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C2 flag CPU reset is set or not.
+  * @rmtoll RSR          C1RSTF       LL_C2_RCC_IsActiveFlag_CPURST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_CPURST(void)
+{
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Check if RCC_C2 flag CPU2 reset is set or not.
+  * @rmtoll RSR          C2RSTF       LL_C2_RCC_IsActiveFlag_CPU2RST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_CPU2RST(void)
+{
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF))?1UL:0UL);
+}
+
+/**
+  * @brief  Set RMVF bit to clear the reset flags.
+  * @rmtoll RSR          RMVF          LL_C2_RCC_ClearResetFlags
+  * @retval None
+  */
+__STATIC_INLINE void LL_C2_RCC_ClearResetFlags(void)
+{
+  SET_BIT(RCC_C2->RSR, RCC_RSR_RMVF);
+}
+#endif /*DUAL_CORE*/
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_IT_Management IT Management
+  * @{
+  */
+
+/**
+  * @brief  Enable LSI ready interrupt
+  * @rmtoll CIER         LSIRDYIE      LL_RCC_EnableIT_LSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
+}
+
+/**
+  * @brief  Enable LSE ready interrupt
+  * @rmtoll CIER         LSERDYIE      LL_RCC_EnableIT_LSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
+}
+
+/**
+  * @brief  Enable HSI ready interrupt
+  * @rmtoll CIER         HSIRDYIE      LL_RCC_EnableIT_HSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
+}
+
+/**
+  * @brief  Enable HSE ready interrupt
+  * @rmtoll CIER         HSERDYIE      LL_RCC_EnableIT_HSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
+}
+
+/**
+  * @brief  Enable CSI ready interrupt
+  * @rmtoll CIER         CSIRDYIE      LL_RCC_EnableIT_CSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_CSIRDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_CSIRDYIE);
+}
+
+/**
+  * @brief  Enable HSI48 ready interrupt
+  * @rmtoll CIER         HSI48RDYIE      LL_RCC_EnableIT_HSI48RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
+}
+
+/**
+  * @brief  Enable PLL1 ready interrupt
+  * @rmtoll CIER         PLL1RDYIE      LL_RCC_EnableIT_PLL1RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_PLL1RDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE);
+}
+
+/**
+  * @brief  Enable PLL2 ready interrupt
+  * @rmtoll CIER         PLL2RDYIE  LL_RCC_EnableIT_PLL2RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE);
+}
+
+/**
+  * @brief  Enable PLL3 ready interrupt
+  * @rmtoll CIER         PLL3RDYIE  LL_RCC_EnableIT_PLL3RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_PLL3RDY(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE);
+}
+
+/**
+  * @brief  Enable LSECSS interrupt
+  * @rmtoll CIER         LSECSSIE  LL_RCC_EnableIT_LSECSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
+{
+  SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
+}
+
+/**
+  * @brief  Disable LSI ready interrupt
+  * @rmtoll CIER         LSIRDYIE      LL_RCC_DisableIT_LSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
+}
+
+/**
+  * @brief  Disable LSE ready interrupt
+  * @rmtoll CIER         LSERDYIE      LL_RCC_DisableIT_LSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
+}
+
+/**
+  * @brief  Disable HSI ready interrupt
+  * @rmtoll CIER         HSIRDYIE      LL_RCC_DisableIT_HSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
+}
+
+/**
+  * @brief  Disable HSE ready interrupt
+  * @rmtoll CIER         HSERDYIE      LL_RCC_DisableIT_HSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
+}
+
+/**
+  * @brief  Disable CSI ready interrupt
+  * @rmtoll CIER         CSIRDYIE      LL_RCC_DisableIT_CSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_CSIRDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_CSIRDYIE);
+}
+
+/**
+  * @brief  Disable HSI48 ready interrupt
+  * @rmtoll CIER         HSI48RDYIE      LL_RCC_DisableIT_HSI48RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
+}
+
+/**
+  * @brief  Disable PLL1 ready interrupt
+  * @rmtoll CIER         PLL1RDYIE      LL_RCC_DisableIT_PLL1RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_PLL1RDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE);
+}
+
+/**
+  * @brief  Disable PLL2 ready interrupt
+  * @rmtoll CIER         PLL2RDYIE  LL_RCC_DisableIT_PLL2RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE);
+}
+
+/**
+  * @brief  Disable PLL3 ready interrupt
+  * @rmtoll CIER         PLL3RDYIE  LL_RCC_DisableIT_PLL3RDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_PLL3RDY(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE);
+}
+
+/**
+  * @brief  Disable LSECSS interrupt
+  * @rmtoll CIER         LSECSSIE  LL_RCC_DisableIT_LSECSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
+{
+  CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
+}
+
+/**
+  * @brief  Checks if LSI ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         LSIRDYIE      LL_RCC_IsEnableIT_LSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSIRDY(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE)?1UL:0UL);
+}
+
+/**
+  * @brief  Checks if LSE ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         LSERDYIE      LL_RCC_IsEnableIT_LSERDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSERDY(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE)?1UL:0UL);
+}
+
+/**
+  * @brief  Checks if HSI ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         HSIRDYIE      LL_RCC_IsEnableIT_HSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSIRDY(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE)?1UL:0UL);
+}
+
+/**
+  * @brief  Checks if HSE ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         HSERDYIE      LL_RCC_IsEnableIT_HSERDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSERDY(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE)?1UL:0UL);
+}
+
+/**
+  * @brief  Checks if CSI ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         CSIRDYIE      LL_RCC_IsEnableIT_CSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_CSIRDY(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_CSIRDYIE) == RCC_CIER_CSIRDYIE)?1UL:0UL);
+}
+
+/**
+  * @brief  Checks if HSI48 ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         HSI48RDYIE      LL_RCC_IsEnableIT_HSI48RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSI48RDY(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == RCC_CIER_HSI48RDYIE)?1UL:0UL);
+}
+
+/**
+  * @brief  Checks if PLL1 ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         PLL1RDYIE      LL_RCC_IsEnableIT_PLL1RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL1RDY(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE) == RCC_CIER_PLL1RDYIE)?1UL:0UL);
+}
+
+/**
+  * @brief  Checks if PLL2 ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         PLL2RDYIE  LL_RCC_IsEnableIT_PLL2RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL2RDY(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE) == RCC_CIER_PLL2RDYIE)?1UL:0UL);
+}
+
+/**
+  * @brief  Checks if PLL3 ready interrupt source is enabled or disabled.
+  * @rmtoll CIER         PLL3RDYIE  LL_RCC_IsEnableIT_PLL3RDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL3RDY(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE) == RCC_CIER_PLL3RDYIE)?1UL:0UL);
+}
+
+/**
+  * @brief  Checks if LSECSS interrupt source is enabled or disabled.
+  * @rmtoll CIER         LSECSSIE  LL_RCC_IsEnableIT_LSECSS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSECSS(void)
+{
+  return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == RCC_CIER_LSECSSIE)?1UL:0UL);
+}
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_EF_Init De-initialization function
+  * @{
+  */
+void LL_RCC_DeInit(void);
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
+  * @{
+  */
+uint32_t    LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t PQR);
+
+void        LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks);
+void        LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks);
+void        LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks);
+void        LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
+
+uint32_t    LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
+uint32_t    LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
+uint32_t    LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
+uint32_t    LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
+uint32_t    LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
+uint32_t    LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
+uint32_t    LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource);
+uint32_t    LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
+uint32_t    LL_RCC_GetCECClockFreq(uint32_t CECxSource);
+uint32_t    LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
+uint32_t    LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
+#if defined(DFSDM2_BASE)
+uint32_t    LL_RCC_GetDFSDM2ClockFreq(uint32_t DFSDMxSource);
+#endif /* DFSDM2 */
+#if defined(DSI)
+uint32_t    LL_RCC_GetDSIClockFreq(uint32_t DSIxSource);
+#endif /* DSI */
+uint32_t    LL_RCC_GetSPDIFClockFreq(uint32_t SPDIFxSource);
+uint32_t    LL_RCC_GetSPIClockFreq(uint32_t SPIxSource);
+uint32_t    LL_RCC_GetSWPClockFreq(uint32_t SWPxSource);
+uint32_t    LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource);
+uint32_t    LL_RCC_GetFMCClockFreq(uint32_t FMCxSource);
+#if defined(QUADSPI)
+uint32_t    LL_RCC_GetQSPIClockFreq(uint32_t QSPIxSource);
+#endif /* QUADSPI */
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+uint32_t    LL_RCC_GetOSPIClockFreq(uint32_t OSPIxSource);
+#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
+uint32_t    LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource);
+
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+#endif /* defined(RCC) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_LL_RCC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_system.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_system.h
new file mode 100644
index 00000000..77fc4ff5
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_system.h
@@ -0,0 +1,2274 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_system.h
+  * @author  MCD Application Team
+  * @brief   Header file of SYSTEM LL module.
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The LL SYSTEM driver contains a set of generic APIs that can be
+    used by user:
+      (+) Some of the FLASH features need to be handled in the SYSTEM file.
+      (+) Access to DBGCMU registers
+      (+) Access to SYSCFG registers
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32H7xx_LL_SYSTEM_H
+#define __STM32H7xx_LL_SYSTEM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)
+
+/** @defgroup SYSTEM_LL SYSTEM
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
+  * @{
+  */
+/** @defgroup SYSTEM_LL_EC_FLASH_BANK1_SECTORS SYSCFG Flash Bank1 sectors bits status
+  * @{
+  */
+#define LL_SYSCFG_FLASH_B1_SECTOR0_STATUS_BIT   0x10000U
+#define LL_SYSCFG_FLASH_B1_SECTOR1_STATUS_BIT   0x20000U
+#define LL_SYSCFG_FLASH_B1_SECTOR2_STATUS_BIT   0x40000U
+#define LL_SYSCFG_FLASH_B1_SECTOR3_STATUS_BIT   0x80000U
+#define LL_SYSCFG_FLASH_B1_SECTOR4_STATUS_BIT   0x100000U
+#define LL_SYSCFG_FLASH_B1_SECTOR5_STATUS_BIT   0x200000U
+#define LL_SYSCFG_FLASH_B1_SECTOR6_STATUS_BIT   0x400000U
+#define LL_SYSCFG_FLASH_B1_SECTOR7_STATUS_BIT   0x800000U
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_FLASH_BANK2_SECTORS SYSCFG Flash Bank2 sectors bits status
+  * @{
+  */
+#define LL_SYSCFG_FLASH_B2_SECTOR0_STATUS_BIT   0x10000U
+#define LL_SYSCFG_FLASH_B2_SECTOR1_STATUS_BIT   0x20000U
+#define LL_SYSCFG_FLASH_B2_SECTOR2_STATUS_BIT   0x40000U
+#define LL_SYSCFG_FLASH_B2_SECTOR3_STATUS_BIT   0x80000U
+#define LL_SYSCFG_FLASH_B2_SECTOR4_STATUS_BIT   0x100000U
+#define LL_SYSCFG_FLASH_B2_SECTOR5_STATUS_BIT   0x200000U
+#define LL_SYSCFG_FLASH_B2_SECTOR6_STATUS_BIT   0x400000U
+#define LL_SYSCFG_FLASH_B2_SECTOR7_STATUS_BIT   0x800000U
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
+  * @{
+  */
+
+/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
+  * @{
+  */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1        SYSCFG_PMCR_I2C1_FMP       /*!< Enable Fast Mode Plus for I2C1      */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2        SYSCFG_PMCR_I2C2_FMP       /*!< Enable Fast Mode Plus for I2C2      */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3        SYSCFG_PMCR_I2C3_FMP       /*!< Enable Fast Mode Plus for I2C3      */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4        SYSCFG_PMCR_I2C4_FMP       /*!< Enable Fast Mode Plus for I2C4      */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6         SYSCFG_PMCR_I2C_PB6_FMP    /*!< Enable Fast Mode Plus on PB6        */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7         SYSCFG_PMCR_I2C_PB7_FMP    /*!< Enable Fast Mode Plus on PB7        */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8         SYSCFG_PMCR_I2C_PB8_FMP    /*!< Enable Fast Mode Plus on PB8        */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9         SYSCFG_PMCR_I2C_PB9_FMP    /*!< Enable Fast Mode Plus on PB9        */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_ANALOG_SWITCH Analog Switch control
+* @{
+*/
+#define LL_SYSCFG_ANALOG_SWITCH_BOOSTEN           SYSCFG_PMCR_BOOSTEN               /*!< I/O analog switch voltage booster enable */
+#define LL_SYSCFG_ANALOG_SWITCH_PA0               SYSCFG_PMCR_PA0SO                 /*!< PA0 Switch Open */
+#define LL_SYSCFG_ANALOG_SWITCH_PA1               SYSCFG_PMCR_PA1SO                 /*!< PA1 Switch Open */
+#define LL_SYSCFG_ANALOG_SWITCH_PC2               SYSCFG_PMCR_PC2SO                 /*!< PC2 Switch Open */
+#define LL_SYSCFG_ANALOG_SWITCH_PC3               SYSCFG_PMCR_PC3SO                 /*!< PC3 Switch Open */
+/**
+  * @}
+  */
+
+#if defined(SYSCFG_PMCR_EPIS_SEL)
+/** @defgroup SYSTEM_LL_EC_EPIS Ethernet PHY Interface Selection
+* @{
+*/
+#define LL_SYSCFG_ETH_MII               0x00000000U                           /*!< ETH Media MII interface */
+#define LL_SYSCFG_ETH_RMII              SYSCFG_PMCR_EPIS_SEL                   /*!< ETH Media RMII interface */
+/**
+  * @}
+  */
+#endif /* SYSCFG_PMCR_EPIS_SEL */
+
+/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
+  * @{
+  */
+#define LL_SYSCFG_EXTI_PORTA               0U               /*!< EXTI PORT A                        */
+#define LL_SYSCFG_EXTI_PORTB               1U               /*!< EXTI PORT B                        */
+#define LL_SYSCFG_EXTI_PORTC               2U               /*!< EXTI PORT C                        */
+#define LL_SYSCFG_EXTI_PORTD               3U               /*!< EXTI PORT D                        */
+#define LL_SYSCFG_EXTI_PORTE               4U               /*!< EXTI PORT E                        */
+#define LL_SYSCFG_EXTI_PORTF               5U               /*!< EXTI PORT F                        */
+#define LL_SYSCFG_EXTI_PORTG               6U               /*!< EXTI PORT G                        */
+#define LL_SYSCFG_EXTI_PORTH               7U               /*!< EXTI PORT H                        */
+#define LL_SYSCFG_EXTI_PORTI               8U               /*!< EXTI PORT I                        */
+#define LL_SYSCFG_EXTI_PORTJ               9U               /*!< EXTI PORT J                        */
+#define LL_SYSCFG_EXTI_PORTK               10U              /*!< EXTI PORT k                        */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
+  * @{
+  */
+#define LL_SYSCFG_EXTI_LINE0               ((0x000FUL << 16U) | 0U)  /*!< EXTI_POSITION_0  | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE1               ((0x00F0UL << 16U) | 0U)  /*!< EXTI_POSITION_4  | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE2               ((0x0F00UL << 16U) | 0U)  /*!< EXTI_POSITION_8  | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE3               ((0xF000UL << 16U) | 0U)  /*!< EXTI_POSITION_12 | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE4               ((0x000FUL << 16U) | 1U)  /*!< EXTI_POSITION_0  | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE5               ((0x00F0UL << 16U) | 1U)  /*!< EXTI_POSITION_4  | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE6               ((0x0F00UL << 16U) | 1U)  /*!< EXTI_POSITION_8  | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE7               ((0xF000UL << 16U) | 1U)  /*!< EXTI_POSITION_12 | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE8               ((0x000FUL << 16U) | 2U)  /*!< EXTI_POSITION_0  | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE9               ((0x00F0UL << 16U) | 2U)  /*!< EXTI_POSITION_4  | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE10              ((0x0F00UL << 16U) | 2U)  /*!< EXTI_POSITION_8  | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE11              ((0xF000UL << 16U) | 2U)  /*!< EXTI_POSITION_12 | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE12              ((0x000FUL << 16U) | 3U)  /*!< EXTI_POSITION_0  | EXTICR[3] */
+#define LL_SYSCFG_EXTI_LINE13              ((0x00F0UL << 16U) | 3U)  /*!< EXTI_POSITION_4  | EXTICR[3] */
+#define LL_SYSCFG_EXTI_LINE14              ((0x0F00UL << 16U) | 3U)  /*!< EXTI_POSITION_8  | EXTICR[3] */
+#define LL_SYSCFG_EXTI_LINE15              ((0xF000UL << 16U) | 3U)  /*!< EXTI_POSITION_12 | EXTICR[3] */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
+  * @{
+  */
+#define LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC SYSCFG_CFGR_AXISRAML /*!< Enables and locks the AXIRAM double ECC error signal
+                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */
+
+#define LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC    SYSCFG_CFGR_ITCML    /*!< Enables and locks the ITCM double ECC error signal
+                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */
+
+#define LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC    SYSCFG_CFGR_DTCML    /*!< Enables and locks the DTCM double ECC error signal
+                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */
+
+#define LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC   SYSCFG_CFGR_SRAM1L   /*!< Enables and locks the SRAM1 double ECC error signal
+                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */
+
+#define LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC   SYSCFG_CFGR_SRAM2L   /*!< Enables and locks the SRAM2 double ECC error signal
+                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */
+
+#define LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC   SYSCFG_CFGR_SRAM3L   /*!< Enables and locks the SRAM3 double ECC error signal
+                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */
+
+#define LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC   SYSCFG_CFGR_SRAM4L   /*!< Enables and locks the SRAM4 double ECC error signal
+                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */
+
+#define LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC   SYSCFG_CFGR_BKRAML   /*!< Enables and locks the BKRAM double ECC error signal
+                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */
+
+#define LL_SYSCFG_TIMBREAK_CM7_LOCKUP      SYSCFG_CFGR_CM7L     /*!< Enables and locks the Cortex-M7 LOCKUP signal
+                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */
+
+#define LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC   SYSCFG_CFGR_FLASHL   /*!< Enables and locks the FLASH double ECC error signal
+                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */
+
+#define LL_SYSCFG_TIMBREAK_PVD             SYSCFG_CFGR_PVDL     /*!< Enables and locks the PVD connection
+                                                                     with TIM1/8/15/16/17 and HRTIM Break Input
+                                                                     and also the PVDE and PLS bits of the Power Control Interface */
+#if defined(DUAL_CORE)
+#define LL_SYSCFG_TIMBREAK_CM4_LOCKUP      SYSCFG_CFGR_CM4L     /*!< Enables and locks the Cortex-M4 LOCKUP signal
+                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */
+#endif /* DUAL_CORE */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_CS SYSCFG I/O compensation cell Code selection
+  * @{
+  */
+#define LL_SYSCFG_CELL_CODE               0U
+#define LL_SYSCFG_REGISTER_CODE           SYSCFG_CCCSR_CS
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_IWDG1_CONTROL_MODES SYSCFG IWDG1 control modes
+  * @{
+  */
+#define LL_SYSCFG_IWDG1_SW_CONTROL_MODE   0U
+#define LL_SYSCFG_IWDG1_HW_CONTROL_MODE   SYSCFG_UR11_IWDG1M
+/**
+  * @}
+  */
+
+#if defined (DUAL_CORE)
+/** @defgroup SYSTEM_LL_IWDG2_CONTROL_MODES SYSCFG IWDG2 control modes
+  * @{
+  */
+#define LL_SYSCFG_IWDG2_SW_CONTROL_MODE   0U
+#define LL_SYSCFG_IWDG2_HW_CONTROL_MODE   SYSCFG_UR12_IWDG2M
+/**
+  * @}
+  */
+#endif /* DUAL_CORE */
+
+/** @defgroup SYSTEM_LL_DTCM_RAM_SIZE SYSCFG DTCM RAM size configuration
+  * @{
+  */
+#define LL_SYSCFG_DTCM_RAM_SIZE_2KB     0U
+#define LL_SYSCFG_DTCM_RAM_SIZE_4KB     1U
+#define LL_SYSCFG_DTCM_RAM_SIZE_8KB     2U
+#define LL_SYSCFG_DTCM_RAM_SIZE_16KB    3U
+/**
+  * @}
+  */
+#ifdef SYSCFG_PKGR_PKG
+/** @defgroup SYSTEM_LL_PACKAGE SYSCFG device package
+  * @{
+  */
+#define LL_SYSCFG_LQFP100_PACKAGE             0U
+#define LL_SYSCFG_TQFP144_PACKAGE             2U
+#define LL_SYSCFG_TQFP176_UFBGA176_PACKAGE    5U
+#define LL_SYSCFG_LQFP208_TFBGA240_PACKAGE    8U
+/**
+  * @}
+  */
+#endif /* SYSCFG_PKGR_PKG */
+
+/** @defgroup SYSTEM_LL_SYSCFG_BOR SYSCFG Brownout Reset Threshold Level
+  * @{
+  */
+#define LL_SYSCFG_BOR_OFF_RESET_LEVEL      0x00000000U
+#define LL_SYSCFG_BOR_LOW_RESET_LEVEL      SYSCFG_UR2_BORH_0
+#define LL_SYSCFG_BOR_MEDIUM_RESET_LEVEL   SYSCFG_UR2_BORH_1
+#define LL_SYSCFG_BOR_HIGH_RESET_LEVEL     SYSCFG_UR2_BORH
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
+  * @{
+  */
+#define LL_DBGMCU_TRACE_NONE               0x00000000U                                     /*!< TRACE pins not assigned (default state) */
+#define LL_DBGMCU_TRACE_ASYNCH             DBGMCU_CR_TRACE_IOEN                            /*!< TRACE pin assignment for Asynchronous Mode */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE1        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE2        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE4        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)   /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
+  * @{
+  */
+#define LL_DBGMCU_APB1_GRP1_TIM2_STOP      DBGMCU_APB1LFZ1_DBG_TIM2     /*!< TIM2 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_TIM3_STOP      DBGMCU_APB1LFZ1_DBG_TIM3     /*!< TIM3 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_TIM4_STOP      DBGMCU_APB1LFZ1_DBG_TIM4     /*!< TIM4 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_TIM5_STOP      DBGMCU_APB1LFZ1_DBG_TIM5     /*!< TIM5 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_TIM6_STOP      DBGMCU_APB1LFZ1_DBG_TIM6     /*!< TIM6 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_TIM7_STOP      DBGMCU_APB1LFZ1_DBG_TIM7     /*!< TIM7 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_TIM12_STOP     DBGMCU_APB1LFZ1_DBG_TIM12    /*!< TIM12 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_TIM13_STOP     DBGMCU_APB1LFZ1_DBG_TIM13    /*!< TIM13 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_TIM14_STOP     DBGMCU_APB1LFZ1_DBG_TIM14    /*!< TIM14 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP    DBGMCU_APB1LFZ1_DBG_LPTIM1   /*!< LPTIM1 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_I2C1_STOP      DBGMCU_APB1LFZ1_DBG_I2C1     /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+#define LL_DBGMCU_APB1_GRP1_I2C2_STOP      DBGMCU_APB1LFZ1_DBG_I2C2     /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
+#define LL_DBGMCU_APB1_GRP1_I2C3_STOP      DBGMCU_APB1LFZ1_DBG_I2C3     /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
+  * @{
+  */
+#define LL_DBGMCU_APB1_GRP2_FDCAN_STOP    DBGMCU_APB1HFZ1_DBG_FDCAN    /*!< FDCAN is frozen while the core is in debug mode */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
+  * @{
+  */
+#define LL_DBGMCU_APB2_GRP1_TIM1_STOP      DBGMCU_APB2FZ1_DBG_TIM1    /*!< TIM1 counter stopped when core is halted */
+#define LL_DBGMCU_APB2_GRP1_TIM8_STOP      DBGMCU_APB2FZ1_DBG_TIM8    /*!< TIM8 counter stopped when core is halted */
+#define LL_DBGMCU_APB2_GRP1_TIM15_STOP     DBGMCU_APB2FZ1_DBG_TIM15   /*!< TIM15 counter stopped when core is halted */
+#define LL_DBGMCU_APB2_GRP1_TIM16_STOP     DBGMCU_APB2FZ1_DBG_TIM16   /*!< TIM16 counter stopped when core is halted */
+#define LL_DBGMCU_APB2_GRP1_TIM17_STOP     DBGMCU_APB2FZ1_DBG_TIM17   /*!< TIM17 counter stopped when core is halted */
+#define LL_DBGMCU_APB2_GRP1_HRTIM_STOP     DBGMCU_APB2FZ1_DBG_HRTIM   /*!< HRTIM counter stopped when core is halted */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_APB3_GRP1_STOP_IP DBGMCU APB3 GRP1 STOP IP
+  * @{
+  */
+#define LL_DBGMCU_APB3_GRP1_WWDG1_STOP      DBGMCU_APB3FZ1_DBG_WWDG1   /*!< WWDG1 is frozen while the core is in debug mode */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_APB4_GRP1_STOP_IP DBGMCU APB4 GRP1 STOP IP
+  * @{
+  */
+#define LL_DBGMCU_APB4_GRP1_I2C4_STOP       DBGMCU_APB4FZ1_DBG_I2C4     /*!< I2C4 is frozen while the core is in debug mode */
+#define LL_DBGMCU_APB4_GRP1_LPTIM2_STOP     DBGMCU_APB4FZ1_DBG_LPTIM2   /*!< LPTIM2 is frozen while the core is in debug mode */
+#define LL_DBGMCU_APB4_GRP1_LPTIM3_STOP     DBGMCU_APB4FZ1_DBG_LPTIM3   /*!< LPTIM3 is frozen while the core is in debug mode */
+#define LL_DBGMCU_APB4_GRP1_LPTIM4_STOP     DBGMCU_APB4FZ1_DBG_LPTIM4   /*!< LPTIM4 is frozen while the core is in debug mode */
+#define LL_DBGMCU_APB4_GRP1_LPTIM5_STOP     DBGMCU_APB4FZ1_DBG_LPTIM5   /*!< LPTIM5 is frozen while the core is in debug mode */
+#define LL_DBGMCU_APB4_GRP1_RTC_STOP        DBGMCU_APB4FZ1_DBG_RTC      /*!< RTC is frozen while the core is in debug mode */
+#define LL_DBGMCU_APB4_GRP1_IWDG1_STOP      DBGMCU_APB4FZ1_DBG_IWDG1    /*!< IWDG1 is frozen while the core is in debug mode */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
+  * @{
+  */
+#define LL_FLASH_LATENCY_0                 FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero wait state */
+#define LL_FLASH_LATENCY_1                 FLASH_ACR_LATENCY_1WS   /*!< FLASH One wait state */
+#define LL_FLASH_LATENCY_2                 FLASH_ACR_LATENCY_2WS   /*!< FLASH Two wait states */
+#define LL_FLASH_LATENCY_3                 FLASH_ACR_LATENCY_3WS   /*!< FLASH Three wait states */
+#define LL_FLASH_LATENCY_4                 FLASH_ACR_LATENCY_4WS   /*!< FLASH Four wait states */
+#define LL_FLASH_LATENCY_5                 FLASH_ACR_LATENCY_5WS   /*!< FLASH five wait state */
+#define LL_FLASH_LATENCY_6                 FLASH_ACR_LATENCY_6WS   /*!< FLASH six wait state */
+#define LL_FLASH_LATENCY_7                 FLASH_ACR_LATENCY_7WS   /*!< FLASH seven wait states */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
+  * @{
+  */
+
+/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
+  * @{
+  */
+
+#if defined(SYSCFG_PMCR_EPIS_SEL)
+/**
+  * @brief  Select Ethernet PHY interface
+  * @rmtoll PMCR    EPIS_SEL    LL_SYSCFG_SetPHYInterface
+  * @param  Interface This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_ETH_MII
+  *         @arg @ref LL_SYSCFG_ETH_RMII
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface)
+{
+  MODIFY_REG(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL, Interface);
+}
+
+/**
+  * @brief  Get Ethernet PHY interface
+  * @rmtoll PMCR    EPIS_SEL    LL_SYSCFG_GetPHYInterface
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_ETH_MII
+  *         @arg @ref LL_SYSCFG_ETH_RMII
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL));
+}
+
+#endif /* SYSCFG_PMCR_EPIS_SEL */
+/**
+  * @brief  Open an Analog Switch
+  * @rmtoll PMCR    PA0SO   LL_SYSCFG_OpenAnalogSwitch
+  * @rmtoll PMCR    PA1SO   LL_SYSCFG_OpenAnalogSwitch
+  * @rmtoll PMCR    PC2SO   LL_SYSCFG_OpenAnalogSwitch
+  * @rmtoll PMCR    PC3SO   LL_SYSCFG_OpenAnalogSwitch
+  * @param  AnalogSwitch This parameter can be one of the following values:
+  *         @arg LL_SYSCFG_ANALOG_SWITCH_PA0 : PA0 analog switch
+  *         @arg LL_SYSCFG_ANALOG_SWITCH_PA1:  PA1 analog switch
+  *         @arg LL_SYSCFG_ANALOG_SWITCH_PC2 : PC2 analog switch
+  *         @arg LL_SYSCFG_ANALOG_SWITCH_PC3:  PC3 analog switch
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_OpenAnalogSwitch(uint32_t AnalogSwitch)
+{
+  SET_BIT(SYSCFG->PMCR, AnalogSwitch);
+}
+
+/**
+  * @brief  Close an Analog Switch
+  * @rmtoll PMCR    PA0SO   LL_SYSCFG_CloseAnalogSwitch
+  * @rmtoll PMCR    PA1SO   LL_SYSCFG_CloseAnalogSwitch
+  * @rmtoll PMCR    PC2SO   LL_SYSCFG_CloseAnalogSwitch
+  * @rmtoll PMCR    PC3SO   LL_SYSCFG_CloseAnalogSwitch
+  * @param  AnalogSwitch This parameter can be one of the following values:
+  *         @arg LL_SYSCFG_ANALOG_SWITCH_PA0 : PA0 analog switch
+  *         @arg LL_SYSCFG_ANALOG_SWITCH_PA1:  PA1 analog switch
+  *         @arg LL_SYSCFG_ANALOG_SWITCH_PC2 : PC2 analog switch
+  *         @arg LL_SYSCFG_ANALOG_SWITCH_PC3:  PC3 analog switch
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_CloseAnalogSwitch(uint32_t AnalogSwitch)
+{
+  CLEAR_BIT(SYSCFG->PMCR, AnalogSwitch);
+}
+#ifdef SYSCFG_PMCR_BOOSTEN
+/**
+  * @brief  Enable the Analog booster to reduce the total harmonic distortion
+  *         of the analog switch when the supply voltage is lower than 2.7 V
+  * @rmtoll PMCR    BOOSTEN   LL_SYSCFG_EnableAnalogBooster
+  * @note   Activating the booster allows to guaranty the analog switch AC performance
+  *         when the supply voltage is below 2.7 V: in this case, the analog switch
+  *         performance is the same on the full voltage range
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)
+{
+ SET_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
+}
+
+/**
+  * @brief  Disable the Analog booster
+  * @rmtoll PMCR    BOOSTEN   LL_SYSCFG_DisableAnalogBooster
+  * @note   Activating the booster allows to guaranty the analog switch AC performance
+  *         when the supply voltage is below 2.7 V: in this case, the analog switch
+  *         performance is the same on the full voltage range
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
+{
+ CLEAR_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
+}
+#endif /*SYSCFG_PMCR_BOOSTEN*/
+/**
+  * @brief  Enable the I2C fast mode plus driving capability.
+  * @rmtoll SYSCFG_PMCR   I2C_PBx_FMP   LL_SYSCFG_EnableFastModePlus\n
+  *         SYSCFG_PMCR   I2Cx_FMP      LL_SYSCFG_EnableFastModePlus
+  * @param  ConfigFastModePlus This parameter can be a combination of the following values:
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4(*)
+  *
+  *         (*) value not defined in all devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
+{
+  SET_BIT(SYSCFG->PMCR, ConfigFastModePlus);
+}
+
+/**
+  * @brief  Disable the I2C fast mode plus driving capability.
+  * @rmtoll SYSCFG_PMCR    I2C_PBx_FMP   LL_SYSCFG_DisableFastModePlus\n
+  *         SYSCFG_PMCR    I2Cx_FMP      LL_SYSCFG_DisableFastModePlus
+  * @param  ConfigFastModePlus This parameter can be a combination of the following values:
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4
+  *         (*) value not defined in all devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
+{
+  CLEAR_BIT(SYSCFG->PMCR, ConfigFastModePlus);
+}
+
+/**
+  * @brief  Configure source input for the EXTI external interrupt.
+  * @rmtoll SYSCFG_EXTICR1  EXTIx         LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR2 EXTIx         LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR3 EXTIx         LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR4 EXTIx         LL_SYSCFG_SetEXTISource
+  * @param  Port This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_EXTI_PORTA
+  *         @arg @ref LL_SYSCFG_EXTI_PORTB
+  *         @arg @ref LL_SYSCFG_EXTI_PORTC
+  *         @arg @ref LL_SYSCFG_EXTI_PORTD
+  *         @arg @ref LL_SYSCFG_EXTI_PORTE
+  *         @arg @ref LL_SYSCFG_EXTI_PORTF
+  *         @arg @ref LL_SYSCFG_EXTI_PORTG
+  *         @arg @ref LL_SYSCFG_EXTI_PORTH
+  *         @arg @ref LL_SYSCFG_EXTI_PORTI
+  *         @arg @ref LL_SYSCFG_EXTI_PORTJ
+  *         @arg @ref LL_SYSCFG_EXTI_PORTK
+  *
+  *         (*) value not defined in all devices
+  * @param  Line This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_EXTI_LINE0
+  *         @arg @ref LL_SYSCFG_EXTI_LINE1
+  *         @arg @ref LL_SYSCFG_EXTI_LINE2
+  *         @arg @ref LL_SYSCFG_EXTI_LINE3
+  *         @arg @ref LL_SYSCFG_EXTI_LINE4
+  *         @arg @ref LL_SYSCFG_EXTI_LINE5
+  *         @arg @ref LL_SYSCFG_EXTI_LINE6
+  *         @arg @ref LL_SYSCFG_EXTI_LINE7
+  *         @arg @ref LL_SYSCFG_EXTI_LINE8
+  *         @arg @ref LL_SYSCFG_EXTI_LINE9
+  *         @arg @ref LL_SYSCFG_EXTI_LINE10
+  *         @arg @ref LL_SYSCFG_EXTI_LINE11
+  *         @arg @ref LL_SYSCFG_EXTI_LINE12
+  *         @arg @ref LL_SYSCFG_EXTI_LINE13
+  *         @arg @ref LL_SYSCFG_EXTI_LINE14
+  *         @arg @ref LL_SYSCFG_EXTI_LINE15
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
+{
+  MODIFY_REG(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U), Port << ((POSITION_VAL(Line >> 16U)) & 31U));
+}
+
+/**
+  * @brief  Get the configured defined for specific EXTI Line
+  * @rmtoll SYSCFG_EXTICR1 EXTIx         LL_SYSCFG_GetEXTISource\n
+  *         SYSCFG_EXTICR2 EXTIx         LL_SYSCFG_GetEXTISource\n
+  *         SYSCFG_EXTICR3 EXTIx         LL_SYSCFG_GetEXTISource\n
+  *         SYSCFG_EXTICR4 EXTIx         LL_SYSCFG_GetEXTISource
+  * @param  Line This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_EXTI_LINE0
+  *         @arg @ref LL_SYSCFG_EXTI_LINE1
+  *         @arg @ref LL_SYSCFG_EXTI_LINE2
+  *         @arg @ref LL_SYSCFG_EXTI_LINE3
+  *         @arg @ref LL_SYSCFG_EXTI_LINE4
+  *         @arg @ref LL_SYSCFG_EXTI_LINE5
+  *         @arg @ref LL_SYSCFG_EXTI_LINE6
+  *         @arg @ref LL_SYSCFG_EXTI_LINE7
+  *         @arg @ref LL_SYSCFG_EXTI_LINE8
+  *         @arg @ref LL_SYSCFG_EXTI_LINE9
+  *         @arg @ref LL_SYSCFG_EXTI_LINE10
+  *         @arg @ref LL_SYSCFG_EXTI_LINE11
+  *         @arg @ref LL_SYSCFG_EXTI_LINE12
+  *         @arg @ref LL_SYSCFG_EXTI_LINE13
+  *         @arg @ref LL_SYSCFG_EXTI_LINE14
+  *         @arg @ref LL_SYSCFG_EXTI_LINE15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_EXTI_PORTA
+  *         @arg @ref LL_SYSCFG_EXTI_PORTB
+  *         @arg @ref LL_SYSCFG_EXTI_PORTC
+  *         @arg @ref LL_SYSCFG_EXTI_PORTD
+  *         @arg @ref LL_SYSCFG_EXTI_PORTE
+  *         @arg @ref LL_SYSCFG_EXTI_PORTF
+  *         @arg @ref LL_SYSCFG_EXTI_PORTG
+  *         @arg @ref LL_SYSCFG_EXTI_PORTH
+  *         @arg @ref LL_SYSCFG_EXTI_PORTI
+  *         @arg @ref LL_SYSCFG_EXTI_PORTJ
+  *         @arg @ref LL_SYSCFG_EXTI_PORTK
+  *         (*) value not defined in all devices
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U)) >> (POSITION_VAL(Line >> 16U) & 31U));
+}
+
+/**
+  * @brief  Set connections to TIM1/8/15/16/17 and HRTIM Break inputs
+  * @note this feature is available on STM32H7 rev.B and above
+  * @rmtoll SYSCFG_CFGR AXISRAML       LL_SYSCFG_SetTIMBreakInputs\n
+  *         SYSCFG_CFGR ITCML          LL_SYSCFG_SetTIMBreakInputs\n
+  *         SYSCFG_CFGR DTCML          LL_SYSCFG_SetTIMBreakInputs\n
+  *         SYSCFG_CFGR SRAM1L         LL_SYSCFG_SetTIMBreakInputs\n
+  *         SYSCFG_CFGR SRAM2L         LL_SYSCFG_SetTIMBreakInputs\n
+  *         SYSCFG_CFGR SRAM3L         LL_SYSCFG_SetTIMBreakInputs\n
+  *         SYSCFG_CFGR SRAM4L         LL_SYSCFG_SetTIMBreakInputs\n
+  *         SYSCFG_CFGR BKRAML         LL_SYSCFG_SetTIMBreakInputs\n
+  *         SYSCFG_CFGR CM7L           LL_SYSCFG_SetTIMBreakInputs\n
+  *         SYSCFG_CFGR FLASHL         LL_SYSCFG_SetTIMBreakInputs\n
+  *         SYSCFG_CFGR PVDL           LL_SYSCFG_SetTIMBreakInputs\n
+  *         SYSCFG_CFGR_CM4L           LL_SYSCFG_SetTIMBreakInputs
+  * @param  Break This parameter can be a combination of the following values:
+  *         @arg @ref LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_CM7_LOCKUP
+  *         @arg @ref LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_PVD
+  *         @arg @ref LL_SYSCFG_TIMBREAK_CM4_LOCKUP (available for dual core lines only)
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
+{
+#if defined(DUAL_CORE)
+  MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML  | SYSCFG_CFGR_DTCML  | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \
+                           SYSCFG_CFGR_SRAM3L   | SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L   | SYSCFG_CFGR_FLASHL | \
+                           SYSCFG_CFGR_PVDL     | SYSCFG_CFGR_CM4L, Break);
+#elif defined (SYSCFG_CFGR_AXISRAML)
+  MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML  | SYSCFG_CFGR_DTCML  | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \
+                           SYSCFG_CFGR_SRAM3L   | SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L   | SYSCFG_CFGR_FLASHL | \
+                           SYSCFG_CFGR_PVDL, Break);
+#else
+  MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_ITCML  | SYSCFG_CFGR_DTCML  |\
+                           SYSCFG_CFGR_CM7L   | SYSCFG_CFGR_FLASHL | \
+                           SYSCFG_CFGR_PVDL, Break);
+#endif /* DUAL_CORE */
+}
+
+/**
+  * @brief  Get connections to TIM1/8/15/16/17 and HRTIM Break inputs
+  * @note this feature is available on STM32H7 rev.B and above
+  * @rmtoll SYSCFG_CFGR AXISRAML       LL_SYSCFG_GetTIMBreakInputs\n
+  *         SYSCFG_CFGR ITCML          LL_SYSCFG_GetTIMBreakInputs\n
+  *         SYSCFG_CFGR DTCML          LL_SYSCFG_GetTIMBreakInputs\n
+  *         SYSCFG_CFGR SRAM1L         LL_SYSCFG_GetTIMBreakInputs\n
+  *         SYSCFG_CFGR SRAM2L         LL_SYSCFG_GetTIMBreakInputs\n
+  *         SYSCFG_CFGR SRAM3L         LL_SYSCFG_GetTIMBreakInputs\n
+  *         SYSCFG_CFGR SRAM4L         LL_SYSCFG_GetTIMBreakInputs\n
+  *         SYSCFG_CFGR BKRAML         LL_SYSCFG_GetTIMBreakInputs\n
+  *         SYSCFG_CFGR CM7L           LL_SYSCFG_GetTIMBreakInputs\n
+  *         SYSCFG_CFGR FLASHL         LL_SYSCFG_GetTIMBreakInputs\n
+  *         SYSCFG_CFGR PVDL           LL_SYSCFG_GetTIMBreakInputs\n
+  *         SYSCFG_CFGR_CM4L           LL_SYSCFG_GetTIMBreakInputs
+  * @retval Returned value can be can be a combination of the following values:
+  *         @arg @ref LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_CM7_LOCKUP
+  *         @arg @ref LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC
+  *         @arg @ref LL_SYSCFG_TIMBREAK_PVD
+  *         @arg @ref LL_SYSCFG_TIMBREAK_CM4_LOCKUP (available for dual core lines only)
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
+{
+#if defined(DUAL_CORE)
+  return (uint32_t)(READ_BIT(SYSCFG->CFGR,  SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML  | SYSCFG_CFGR_DTCML  | \
+                                            SYSCFG_CFGR_SRAM1L   | SYSCFG_CFGR_SRAM2L | SYSCFG_CFGR_SRAM3L | \
+                                            SYSCFG_CFGR_SRAM4L   | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L   | \
+                                            SYSCFG_CFGR_FLASHL   | SYSCFG_CFGR_PVDL   | SYSCFG_CFGR_CM4L));
+#elif defined (SYSCFG_CFGR_AXISRAML)
+  return (uint32_t)(READ_BIT(SYSCFG->CFGR,  SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML  | SYSCFG_CFGR_DTCML  | \
+                                            SYSCFG_CFGR_SRAM1L   | SYSCFG_CFGR_SRAM2L | SYSCFG_CFGR_SRAM3L | \
+                                            SYSCFG_CFGR_SRAM4L   | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L   | \
+                                            SYSCFG_CFGR_FLASHL   | SYSCFG_CFGR_PVDL ));
+#else
+  return (uint32_t)(READ_BIT(SYSCFG->CFGR,  SYSCFG_CFGR_ITCML    | SYSCFG_CFGR_DTCML  | SYSCFG_CFGR_CM7L   | \
+                                            SYSCFG_CFGR_FLASHL   | SYSCFG_CFGR_PVDL ));
+#endif /* DUAL_CORE */
+}
+
+/**
+  * @brief  Enable the Compensation Cell
+  * @rmtoll CCCSR   EN    LL_SYSCFG_EnableCompensationCell
+  * @note   The I/O compensation cell can be used only when the device supply
+  *         voltage ranges from 2.4 to 3.6 V
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void)
+{
+  SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN);
+}
+
+/**
+  * @brief  Disable the Compensation Cell
+  * @rmtoll CCCSR   EN    LL_SYSCFG_DisableCompensationCell
+  * @note   The I/O compensation cell can be used only when the device supply
+  *         voltage ranges from 2.4 to 3.6 V
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void)
+{
+  CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN);
+}
+
+/**
+  * @brief  Check if the Compensation Cell is enabled
+  * @rmtoll CCCSR   EN    LL_SYSCFG_IsEnabledCompensationCell
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledCompensationCell(void)
+{
+  return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN) == SYSCFG_CCCSR_EN) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get Compensation Cell ready Flag
+  * @rmtoll CCCSR   READY   LL_SYSCFG_IsActiveFlag_CMPCR
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void)
+{
+  return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_READY) == (SYSCFG_CCCSR_READY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the I/O speed optimization when the product voltage is low.
+  * @rmtoll CCCSR   HSLV    LL_SYSCFG_EnableIOSpeedOptimize
+  * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the
+  *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
+  *         might be destructive.
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization(void)
+{
+#if defined(SYSCFG_CCCSR_HSLV)
+  SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);
+#else
+  SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0);
+#endif   /* SYSCFG_CCCSR_HSLV */
+}
+
+#if defined(SYSCFG_CCCSR_HSLV1)
+/**
+  * @brief  Enable the I/O speed optimization when the product voltage is low.
+  * @rmtoll CCCSR   HSLV1    LL_SYSCFG_EnableIOSpeedOptimize
+  * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the
+  *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
+  *         might be destructive.
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization1(void)
+{
+  SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1);
+}
+
+/**
+  * @brief  Enable the I/O speed optimization when the product voltage is low.
+  * @rmtoll CCCSR   HSLV2    LL_SYSCFG_EnableIOSpeedOptimize
+  * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the
+  *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
+  *         might be destructive.
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization2(void)
+{
+  SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2);
+}
+
+/**
+  * @brief  Enable the I/O speed optimization when the product voltage is low.
+  * @rmtoll CCCSR   HSLV3    LL_SYSCFG_EnableIOSpeedOptimize
+  * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the
+  *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
+  *         might be destructive.
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization3(void)
+{
+  SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3);
+}
+#endif /*SYSCFG_CCCSR_HSLV1*/
+
+
+/**
+  * @brief  To Disable optimize the I/O speed when the product voltage is low.
+  * @rmtoll CCCSR   HSLV    LL_SYSCFG_DisableIOSpeedOptimize
+  * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the
+  *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
+  *         might be destructive.
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization(void)
+{
+#if defined(SYSCFG_CCCSR_HSLV)
+  CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);
+#else
+  CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0);
+#endif   /* SYSCFG_CCCSR_HSLV */
+}
+
+#if defined(SYSCFG_CCCSR_HSLV1)
+/**
+  * @brief  To Disable optimize the I/O speed when the product voltage is low.
+  * @rmtoll CCCSR   HSLV1    LL_SYSCFG_DisableIOSpeedOptimize
+  * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the
+  *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
+  *         might be destructive.
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization1(void)
+{
+  CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1);
+}
+
+/**
+  * @brief  To Disable optimize the I/O speed when the product voltage is low.
+  * @rmtoll CCCSR   HSLV2    LL_SYSCFG_DisableIOSpeedOptimize
+  * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the
+  *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
+  *         might be destructive.
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization2(void)
+{
+  CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2);
+}
+
+/**
+  * @brief  To Disable optimize the I/O speed when the product voltage is low.
+  * @rmtoll CCCSR   HSLV3    LL_SYSCFG_DisableIOSpeedOptimize
+  * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the
+  *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
+  *         might be destructive.
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization3(void)
+{
+  CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3);
+}
+#endif /*SYSCFG_CCCSR_HSLV1*/
+
+/**
+  * @brief  Check if the I/O speed optimization is enabled
+  * @rmtoll CCCSR   HSLV    LL_SYSCFG_IsEnabledIOSpeedOptimization
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization(void)
+{
+#if defined(SYSCFG_CCCSR_HSLV)
+  return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV) == SYSCFG_CCCSR_HSLV) ? 1UL : 0UL);
+#else
+  return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0) == SYSCFG_CCCSR_HSLV0) ? 1UL : 0UL);
+#endif /*SYSCFG_CCCSR_HSLV*/
+}
+
+#if defined(SYSCFG_CCCSR_HSLV1)
+/**
+  * @brief  Check if the I/O speed optimization is enabled
+  * @rmtoll CCCSR   HSLV1    LL_SYSCFG_IsEnabledIOSpeedOptimization
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization1(void)
+{
+  return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1) == SYSCFG_CCCSR_HSLV1) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the I/O speed optimization is enabled
+  * @rmtoll CCCSR   HSLV2    LL_SYSCFG_IsEnabledIOSpeedOptimization
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization2(void)
+{
+  return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2) == SYSCFG_CCCSR_HSLV2) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the I/O speed optimization is enabled
+  * @rmtoll CCCSR   HSLV3    LL_SYSCFG_IsEnabledIOSpeedOptimization
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization3(void)
+{
+  return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3) == SYSCFG_CCCSR_HSLV3) ? 1UL : 0UL);
+}
+#endif /*SYSCFG_CCCSR_HSLV1*/
+
+/**
+  * @brief  Set the code selection for the I/O Compensation cell
+  * @rmtoll CCCSR   CS    LL_SYSCFG_SetCellCompensationCode
+  * @param  CompCode: Selects the code to be applied for the I/O compensation cell
+  *   This parameter can be one of the following values:
+  *   @arg LL_SYSCFG_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR)
+  *   @arg LL_SYSCFG_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR)
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetCellCompensationCode(uint32_t CompCode)
+{
+  SET_BIT(SYSCFG->CCCSR, CompCode);
+}
+
+/**
+  * @brief  Get the code selected for the I/O Compensation cell
+  * @rmtoll CCCSR   CS    LL_SYSCFG_GetCellCompensationCode
+  * @retval Returned value can be one of the following values:
+  *   @arg LL_SYSCFG_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR)
+  *   @arg LL_SYSCFG_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register (SYSCFG_CCCR)
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetCellCompensationCode(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS));
+}
+
+#ifdef SYSCFG_CCCSR_CS_MMC
+
+/**
+  * @brief  Get the code selected for the I/O Compensation cell on the VDDMMC power rail
+  * @rmtoll CCCSR   CS    LL_SYSCFG_GetCellCompensationCode
+  * @retval Returned value can be one of the following values:
+  *   @arg LL_SYSCFG_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR)
+  *   @arg LL_SYSCFG_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register (SYSCFG_CCCR)
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_MMCGetCellCompensationCode(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS_MMC));
+}
+#endif /*SYSCFG_CCCSR_CS_MMC*/
+
+/**
+  * @brief  Get I/O compensation cell value for PMOS transistors
+  * @rmtoll CCVR    PCV   LL_SYSCFG_GetPMOSCompensationValue
+  * @retval Returned value is the I/O compensation cell value for PMOS transistors
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSCompensationValue(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_PCV));
+}
+
+/**
+  * @brief  Get I/O compensation cell value for NMOS transistors
+  * @rmtoll CCVR    NCV   LL_SYSCFG_GetNMOSCompensationValue
+  * @retval Returned value is the I/O compensation cell value for NMOS transistors
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSCompensationValue(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_NCV));
+}
+
+/**
+  * @brief  Set I/O compensation cell code for PMOS transistors
+  * @rmtoll CCCR    PCC   LL_SYSCFG_SetPMOSCompensationCode
+  * @param  PMOSCode PMOS compensation code
+  *         This code is applied to the I/O compensation cell when the CS bit of the
+  *         SYSCFG_CMPCR is set
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetPMOSCompensationCode(uint32_t PMOSCode)
+{
+  MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC, PMOSCode);
+}
+
+/**
+  * @brief  Get I/O compensation cell code for PMOS transistors
+  * @rmtoll CCCR    PCC   LL_SYSCFG_GetPMOSCompensationCode
+  * @retval Returned value is the I/O compensation cell code for PMOS transistors
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSCompensationCode(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC));
+}
+
+#ifdef SYSCFG_CCCR_PCC_MMC
+
+/**
+  * @brief  Set I/O compensation cell code for PMOS transistors corresponding to the VDDMMC power rail
+  * @rmtoll CCCR    PCC   LL_SYSCFG_SetPMOSCompensationCode
+  * @param  PMOSCode PMOS compensation code
+  *         This code is applied to the I/O compensation cell when the CS bit of the
+  *         SYSCFG_CMPCR is set
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_MMCSetPMOSCompensationCode(uint32_t PMOSCode)
+{
+  MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC_MMC, PMOSCode);
+}
+
+/**
+  * @brief  Get I/O compensation cell code for PMOS transistors corresponding to the VDDMMC power rail
+  * @rmtoll CCCR    PCC   LL_SYSCFG_GetPMOSCompensationCode
+  * @retval Returned value is the I/O compensation cell code for PMOS transistors
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_MMCGetPMOSCompensationCode(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC_MMC));
+}
+#endif /* SYSCFG_CCCR_PCC_MMC */
+
+/**
+  * @brief  Set I/O compensation cell code for NMOS transistors
+  * @rmtoll CCCR    NCC   LL_SYSCFG_SetNMOSCompensationCode
+  * @param  NMOSCode NMOS compensation code
+  *         This code is applied to the I/O compensation cell when the CS bit of the
+  *         SYSCFG_CMPCR is set
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetNMOSCompensationCode(uint32_t NMOSCode)
+{
+  MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC, NMOSCode);
+}
+
+/**
+  * @brief  Get I/O compensation cell code for NMOS transistors
+  * @rmtoll CCCR    NCC   LL_SYSCFG_GetNMOSCompensationCode
+  * @retval Returned value is the I/O compensation cell code for NMOS transistors
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSCompensationCode(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC));
+}
+
+#ifdef SYSCFG_CCCR_NCC_MMC
+
+/**
+  * @brief  Set I/O compensation cell code for NMOS transistors on the VDDMMC power rail.
+  * @rmtoll CCCR    NCC   LL_SYSCFG_SetNMOSCompensationCode
+  * @param  NMOSCode: NMOS compensation code
+  *         This code is applied to the I/O compensation cell when the CS bit of the
+  *         SYSCFG_CMPCR is set
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_VDMMCSetNMOSCompensationCode(uint32_t NMOSCode)
+{
+  MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC_MMC, NMOSCode);
+}
+
+/**
+  * @brief  Get I/O compensation cell code for NMOS transistors on the VDDMMC power rail.
+  * @rmtoll CCCR    NCC   LL_SYSCFG_GetNMOSCompensationCode
+  * @retval Returned value is the I/O compensation cell code for NMOS transistors
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_VDMMCGetNMOSCompensationCode(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC_MMC));
+}
+#endif /*SYSCFG_CCCR_NCC_MMC*/
+
+#ifdef SYSCFG_PKGR_PKG
+/**
+  * @brief  Get the device package
+  * @rmtoll PKGR    PKG   LL_SYSCFG_GetPackage
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_LQFP100_PACKAGE
+  *         @arg @ref LL_SYSCFG_TQFP144_PACKAGE
+  *         @arg @ref LL_SYSCFG_TQFP176_UFBGA176_PACKAGE
+  *         @arg @ref LL_SYSCFG_LQFP208_TFBGA240_PACKAGE
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetPackage(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->PKGR, SYSCFG_PKGR_PKG));
+}
+#endif /*SYSCFG_PKGR_PKG*/
+
+#ifdef SYSCFG_UR0_RDP
+/**
+  * @brief  Get the Flash memory protection level
+  * @rmtoll UR0   RDP   LL_SYSCFG_GetFLashProtectionLevel
+  * @retval Returned value can be one of the following values:
+  *         0xAA : RDP level 0
+  *         0xCC : RDP level 2
+  *         Any other value : RDP level 1
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetFLashProtectionLevel(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->UR0, SYSCFG_UR0_RDP));
+}
+/**
+  * @brief  Indicate if the Flash memory bank addresses are inverted or not
+  * @rmtoll UR0   BKS   LL_SYSCFG_IsFLashBankAddressesSwaped
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFLashBankAddressesSwaped(void)
+{
+  return ((READ_BIT(SYSCFG->UR0, SYSCFG_UR0_BKS) == 0U) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get the BOR Threshold Reset Level
+  * @rmtoll UR2   BORH    LL_SYSCFG_GetBrownoutResetLevel
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_BOR_HIGH_RESET_LEVEL
+  *         @arg @ref LL_SYSCFG_BOR_MEDIUM_RESET_LEVEL
+  *         @arg @ref LL_SYSCFG_BOR_LOW_RESET_LEVEL
+  *         @arg @ref LL_SYSCFG_BOR_OFF_RESET_LEVEL
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetBrownoutResetLevel(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BORH));
+}
+/**
+  * @brief  BootCM7 address 0 configuration
+  * @rmtoll UR2   BOOT_ADD0   LL_SYSCFG_SetCM7BootAddress0
+  * @param  BootAddress :Specifies the CM7 Boot Address to be loaded in Address0
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetCM7BootAddress0(uint16_t BootAddress)
+{
+  /* Configure CM7 BOOT ADD0 */
+#if defined(DUAL_CORE)
+  MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0, ((uint32_t)BootAddress << SYSCFG_UR2_BCM7_ADD0_Pos));
+#else
+  MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0, ((uint32_t)BootAddress << SYSCFG_UR2_BOOT_ADD0_Pos));
+#endif /*DUAL_CORE*/
+
+}
+
+/**
+  * @brief  Get BootCM7 address 0
+  * @rmtoll UR2   BOOT_ADD0   LL_SYSCFG_GetCM7BootAddress0
+  * @retval Returned the CM7 Boot Address0
+  */
+__STATIC_INLINE uint16_t LL_SYSCFG_GetCM7BootAddress0(void)
+{
+  /* Get CM7 BOOT ADD0 */
+#if defined(DUAL_CORE)
+  return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0) >> SYSCFG_UR2_BCM7_ADD0_Pos);
+#else
+  return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0) >> SYSCFG_UR2_BOOT_ADD0_Pos);
+#endif /*DUAL_CORE*/
+}
+
+/**
+  * @brief  BootCM7 address 1 configuration
+  * @rmtoll UR3   BOOT_ADD1   LL_SYSCFG_SetCM7BootAddress1
+  * @param  BootAddress :Specifies the CM7 Boot Address to be loaded in Address1
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetCM7BootAddress1(uint16_t BootAddress)
+{
+  /* Configure CM7 BOOT ADD1 */
+#if defined(DUAL_CORE)
+  MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1, BootAddress);
+#else
+  MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1, BootAddress);
+#endif /*DUAL_CORE*/
+}
+
+/**
+  * @brief  Get BootCM7 address 1
+  * @rmtoll UR3   BOOT_ADD1   LL_SYSCFG_GetCM7BootAddress1
+  * @retval Returned the CM7 Boot Address0
+  */
+__STATIC_INLINE uint16_t LL_SYSCFG_GetCM7BootAddress1(void)
+{
+  /* Get CM7 BOOT ADD0 */
+#if defined(DUAL_CORE)
+  return (uint16_t)(READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1));
+#else
+  return (uint16_t)(READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1));
+#endif /* DUAL_CORE */
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  BootCM4 address 0 configuration
+  * @rmtoll UR3   BCM4_ADD0   LL_SYSCFG_SetCM4BootAddress0
+  * @param  BootAddress :Specifies the CM4 Boot Address to be loaded in Address0
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetCM4BootAddress0(uint16_t BootAddress)
+{
+  /* Configure CM4 BOOT ADD0 */
+  MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0, ((uint32_t)BootAddress << SYSCFG_UR3_BCM4_ADD0_Pos));
+}
+
+/**
+  * @brief  Get BootCM4 address 0
+  * @rmtoll UR3   BCM4_ADD0   LL_SYSCFG_GetCM4BootAddress0
+  * @retval Returned the CM4 Boot Address0
+  */
+__STATIC_INLINE uint16_t LL_SYSCFG_GetCM4BootAddress0(void)
+{
+  /* Get CM4 BOOT ADD0 */
+  return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0) >> SYSCFG_UR3_BCM4_ADD0_Pos);
+}
+
+/**
+  * @brief  BootCM4 address 1 configuration
+  * @rmtoll UR4   BCM4_ADD1   LL_SYSCFG_SetCM4BootAddress1
+  * @param  BootAddress :Specifies the CM4 Boot Address to be loaded in Address1
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetCM4BootAddress1(uint16_t BootAddress)
+{
+  /* Configure CM4 BOOT ADD1 */
+  MODIFY_REG(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1, BootAddress);
+}
+
+/**
+  * @brief  Get BootCM4 address 1
+  * @rmtoll UR4   BCM4_ADD1   LL_SYSCFG_GetCM4BootAddress1
+  * @retval Returned the CM4 Boot Address0
+  */
+__STATIC_INLINE uint16_t LL_SYSCFG_GetCM4BootAddress1(void)
+{
+  /* Get CM4 BOOT ADD0 */
+  return (uint16_t)(READ_BIT(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1));
+}
+#endif /*DUAL_CORE*/
+
+/**
+  * @brief  Indicates if the flash protected area (Bank 1) is erased by a mass erase
+  * @rmtoll UR4   MEPAD_BANK1   LL_SYSCFG_IsFlashB1ProtectedAreaErasable
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1ProtectedAreaErasable(void)
+{
+  return ((READ_BIT(SYSCFG->UR4, SYSCFG_UR4_MEPAD_BANK1) == SYSCFG_UR4_MEPAD_BANK1) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the flash secured area (Bank 1) is erased by a mass erase
+  * @rmtoll UR5   MESAD_BANK1   LL_SYSCFG_IsFlashB1SecuredAreaErasable
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1SecuredAreaErasable(void)
+{
+  return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_MESAD_BANK1) == SYSCFG_UR5_MESAD_BANK1) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 0 of the Flash memory bank 1 is write protected
+  * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector0WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector0WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR0_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 1 of the Flash memory bank 1 is write protected
+  * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector1WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector1WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR1_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 2 of the Flash memory bank 1 is write protected
+  * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector2WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector2WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR2_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 3 of the Flash memory bank 1 is write protected
+  * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector3WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector3WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR3_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 4 of the Flash memory bank 1 is write protected
+  * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector4WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector4WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR4_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 5 of the Flash memory bank 1 is write protected
+  * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector5WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector5WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR5_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 6 of the Flash memory bank 1 is write protected
+  * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector6WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector6WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR6_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 7 of the Flash memory bank 1 is write protected
+  * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector7WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector7WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR7_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get the protected area start address for Flash bank 1
+  * @rmtoll UR6   PABEG_BANK1    LL_SYSCFG_GetFlashB1ProtectedAreaStartAddress
+  * @retval Returned the protected area start address for Flash bank 1
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1ProtectedAreaStartAddress(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->UR6, SYSCFG_UR6_PABEG_BANK1));
+}
+
+/**
+  * @brief  Get the protected area end address for Flash bank 1
+  * @rmtoll UR6   PAEND_BANK1   LL_SYSCFG_GetFlashB1ProtectedAreaEndAddress
+  * @retval Returned the protected area end address for Flash bank 1
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1ProtectedAreaEndAddress(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->UR6, SYSCFG_UR6_PAEND_BANK1));
+}
+
+/**
+  * @brief  Get the secured area start address for Flash bank 1
+  * @rmtoll UR7   SABEG_BANK1   LL_SYSCFG_GetFlashB1SecuredAreaStartAddress
+  * @retval Returned the secured area start address for Flash bank 1
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1SecuredAreaStartAddress(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->UR7, SYSCFG_UR7_SABEG_BANK1));
+}
+
+/**
+  * @brief  Get the secured area end address for Flash bank 1
+  * @rmtoll UR7   SAEND_BANK1   LL_SYSCFG_GetFlashB1SecuredAreaEndAddress
+  * @retval Returned the secured area end address for Flash bank 1
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1SecuredAreaEndAddress(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->UR7, SYSCFG_UR7_SAEND_BANK1));
+}
+
+/**
+  * @brief  Indicates if the flash protected area (Bank 2) is erased by a mass erase
+  * @rmtoll UR8   MEPAD_BANK2   LL_SYSCFG_IsFlashB2ProtectedAreaErasable
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2ProtectedAreaErasable(void)
+{
+  return ((READ_BIT(SYSCFG->UR8, SYSCFG_UR8_MEPAD_BANK2) == SYSCFG_UR8_MEPAD_BANK2) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the flash secured area (Bank 2) is erased by a mass erase
+  * @rmtoll UR8   MESAD_BANK2   LL_SYSCFG_IsFlashB2SecuredAreaErasable
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2SecuredAreaErasable(void)
+{
+  return ((READ_BIT(SYSCFG->UR8, SYSCFG_UR8_MESAD_BANK2) == SYSCFG_UR8_MESAD_BANK2) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 0 of the Flash memory bank 2 is write protected
+  * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector0WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector0WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR0_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 1 of the Flash memory bank 2 is write protected
+  * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector1WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector1WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR1_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 2 of the Flash memory bank 2 is write protected
+  * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector2WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector2WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR2_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 3 of the Flash memory bank 2 is write protected
+  * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector3WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector3WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR3_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 4 of the Flash memory bank 2 is write protected
+  * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector4WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector4WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR4_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 5 of the Flash memory bank 2 is write protected
+  * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector5WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector5WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR5_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 6 of the Flash memory bank 2 is write protected
+  * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector6WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector6WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR6_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the sector 7 of the Flash memory bank 2 is write protected
+  * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector7WriteProtected
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector7WriteProtected(void)
+{
+  return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR7_STATUS_BIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get the protected area start address for Flash bank 2
+  * @rmtoll UR9   PABEG_BANK2   LL_SYSCFG_GetFlashB2ProtectedAreaStartAddress
+  * @retval Returned the protected area start address for Flash bank 2
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2ProtectedAreaStartAddress(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->UR9, SYSCFG_UR9_PABEG_BANK2));
+}
+
+/**
+  * @brief  Get the protected area end address for Flash bank 2
+  * @rmtoll UR10    PAEND_BANK2   LL_SYSCFG_GetFlashB2ProtectedAreaEndAddress
+  * @retval Returned the protected area end address for Flash bank 2
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2ProtectedAreaEndAddress(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->UR10, SYSCFG_UR10_PAEND_BANK2));
+}
+
+/**
+  * @brief  Get the secured area start address for Flash bank 2
+  * @rmtoll UR10    SABEG_BANK2   LL_SYSCFG_GetFlashB2SecuredAreaStartAddress
+  * @retval Returned the secured area start address for Flash bank 2
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2SecuredAreaStartAddress(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->UR10, SYSCFG_UR10_SABEG_BANK2));
+}
+
+/**
+  * @brief  Get the secured area end address for Flash bank 2
+  * @rmtoll UR11    SAEND_BANK2   LL_SYSCFG_GetFlashB2SecuredAreaEndAddress
+  * @retval Returned the secured area end address for Flash bank 2
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2SecuredAreaEndAddress(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->UR11, SYSCFG_UR11_SAEND_BANK2));
+}
+
+/**
+  * @brief  Get the Independent Watchdog 1 control mode (Software or Hardware)
+  * @rmtoll UR11    IWDG1M    LL_SYSCFG_GetIWDG1ControlMode
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_IWDG1_SW_CONTROL_MODE
+  *         @arg @ref LL_SYSCFG_IWDG1_HW_CONTROL_MODE
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetIWDG1ControlMode(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->UR11, SYSCFG_UR11_IWDG1M));
+}
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Get the Independent Watchdog 2 control mode (Software or Hardware)
+  * @rmtoll UR12    IWDG2M    LL_SYSCFG_GetIWDG2ControlMode
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_IWDG2_SW_CONTROL_MODE
+  *         @arg @ref LL_SYSCFG_IWDG2_HW_CONTROL_MODE
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetIWDG2ControlMode(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->UR12, SYSCFG_UR12_IWDG2M));
+}
+#endif /* DUAL_CORE */
+
+/**
+  * @brief  Indicates the Secure mode status
+  * @rmtoll UR12    SECURE    LL_SYSCFG_IsSecureModeEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsSecureModeEnabled(void)
+{
+  return ((READ_BIT(SYSCFG->UR12, SYSCFG_UR12_SECURE) == SYSCFG_UR12_SECURE) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if a reset is generated when D1 domain enters DStandby mode
+  * @rmtoll UR13    D1SBRST   LL_SYSCFG_IsD1StandbyGenerateReset
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsD1StandbyGenerateReset(void)
+{
+  return ((READ_BIT(SYSCFG->UR13, SYSCFG_UR13_D1SBRST) == 0U) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get the secured DTCM RAM size
+  * @rmtoll UR13    SDRS    LL_SYSCFG_GetSecuredDTCMSize
+  * @retval Returned value can be one of the following values:
+  *           @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_2KB
+  *           @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_4KB
+  *           @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_8KB
+  *           @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_16KB
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetSecuredDTCMSize(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->UR13, SYSCFG_UR13_SDRS));
+}
+
+/**
+  * @brief  Indicates if a reset is generated when D1 domain enters DStop mode
+  * @rmtoll UR14    D1STPRST    LL_SYSCFG_IsD1StopGenerateReset
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsD1StopGenerateReset(void)
+{
+  return ((READ_BIT(SYSCFG->UR14, SYSCFG_UR14_D1STPRST) == 0U) ? 1UL : 0UL);
+}
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Indicates if a reset is generated when D2 domain enters DStandby mode
+  * @rmtoll UR14    D2SBRST   LL_SYSCFG_IsD2StandbyGenerateReset
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsD2StandbyGenerateReset(void)
+{
+  return ((READ_BIT(SYSCFG->UR14, SYSCFG_UR14_D2SBRST) == 0U) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if a reset is generated when D2 domain enters DStop mode
+  * @rmtoll UR15    D2STPRST    LL_SYSCFG_IsD2StopGenerateReset
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsD2StopGenerateReset(void)
+{
+  return ((READ_BIT(SYSCFG->UR15, SYSCFG_UR15_D2STPRST) == 0U) ? 1UL : 0UL);
+}
+#endif /* DUAL_CORE */
+
+/**
+  * @brief  Indicates if the independent watchdog is frozen in Standby mode
+  * @rmtoll UR15    FZIWDGSTB   LL_SYSCFG_IsIWDGFrozenInStandbyMode
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsIWDGFrozenInStandbyMode(void)
+{
+  return ((READ_BIT(SYSCFG->UR15, SYSCFG_UR15_FZIWDGSTB) == 0U) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the independent watchdog is frozen in Stop mode
+  * @rmtoll UR16    FZIWDGSTP   LL_SYSCFG_IsIWDGFrozenInStopMode
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsIWDGFrozenInStopMode(void)
+{
+  return ((READ_BIT(SYSCFG->UR16, SYSCFG_UR16_FZIWDGSTP) == 0U) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the device private key is programmed
+  * @rmtoll UR16    PKP   LL_SYSCFG_IsPrivateKeyProgrammed
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsPrivateKeyProgrammed(void)
+{
+  return ((READ_BIT(SYSCFG->UR16, SYSCFG_UR16_PKP) == SYSCFG_UR16_PKP) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates if the Product is working on the full voltage range or not
+  * @rmtoll UR17    IOHSLV    LL_SYSCFG_IsActiveFlag_IOHSLV
+  * @note   When the IOHSLV option bit is set the Product is working below 2.7 V.
+  *         When the IOHSLV option bit is reset the Product is working on the
+  *         full voltage range.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_IOHSLV(void)
+{
+  return ((READ_BIT(SYSCFG->UR17, SYSCFG_UR17_IOHSLV) == SYSCFG_UR17_IOHSLV) ? 1UL : 0UL);
+}
+#endif /*SYSCFG_UR0_RDP*/
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
+  * @{
+  */
+
+/**
+  * @brief  Return the device identifier
+  * @rmtoll DBGMCU_IDCODE DEV_ID        LL_DBGMCU_GetDeviceID
+  * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
+  */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
+{
+  return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
+}
+
+/**
+  * @brief  Return the device revision identifier
+  * @note This field indicates the revision of the device.
+          For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001
+  * @rmtoll DBGMCU_IDCODE REV_ID        LL_DBGMCU_GetRevisionID
+  * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
+{
+  return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
+}
+
+/**
+  * @brief  Enable D1 Domain/CDomain debug during SLEEP mode
+  * @rmtoll DBGMCU_CR    DBGSLEEP_D1/DBGSLEEP_CD     LL_DBGMCU_EnableD1DebugInSleepMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableD1DebugInSleepMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
+}
+
+/**
+  * @brief  Disable D1 Domain/CDomain debug during SLEEP mode
+  * @rmtoll DBGMCU_CR    DBGSLEEP_D1/DBGSLEEP_CD     LL_DBGMCU_DisableD1DebugInSleepMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableD1DebugInSleepMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
+}
+
+/**
+  * @brief  Enable D1 Domain/CDomain debug during STOP mode
+  * @rmtoll DBGMCU_CR    DBGSTOP_D1/DBGSLEEP_CD     LL_DBGMCU_EnableD1DebugInStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableD1DebugInStopMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
+}
+
+/**
+  * @brief  Disable D1 Domain/CDomain debug during STOP mode
+  * @rmtoll DBGMCU_CR    DBGSTOP_D1/DBGSLEEP_CD     LL_DBGMCU_DisableD1DebugInStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableD1DebugInStopMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
+}
+
+/**
+  * @brief  Enable D1 Domain/CDomain debug during STANDBY mode
+  * @rmtoll DBGMCU_CR    DBGSTBY_D1/DBGSLEEP_CD     LL_DBGMCU_EnableD1DebugInStandbyMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableD1DebugInStandbyMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
+}
+
+/**
+  * @brief  Disable D1 Domain/CDomain debug during STANDBY mode
+  * @rmtoll DBGMCU_CR    DBGSTBY_D1/DBGSLEEP_CD     LL_DBGMCU_DisableD1DebugInStandbyMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableD1DebugInStandbyMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
+}
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Enable D2 Domain debug during SLEEP mode
+  * @rmtoll DBGMCU_CR    DBGSLEEP_D2     LL_DBGMCU_EnableD2DebugInSleepMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableD2DebugInSleepMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2);
+}
+
+/**
+  * @brief  Disable D2 Domain debug during SLEEP mode
+  * @rmtoll DBGMCU_CR    DBGSLEEP_D2     LL_DBGMCU_DisableD2DebugInSleepMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableD2DebugInSleepMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2);
+}
+
+/**
+  * @brief  Enable D2 Domain debug during STOP mode
+  * @rmtoll DBGMCU_CR    DBGSTOP_D2     LL_DBGMCU_EnableD2DebugInStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableD2DebugInStopMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2);
+}
+
+/**
+  * @brief  Disable D2 Domain debug during STOP mode
+  * @rmtoll DBGMCU_CR    DBGSTOP_D2     LL_DBGMCU_DisableD2DebugInStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableD2DebugInStopMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2);
+}
+
+/**
+  * @brief  Enable D2 Domain debug during STANDBY mode
+  * @rmtoll DBGMCU_CR    DBGSTBY_D2     LL_DBGMCU_EnableD2DebugInStandbyMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableD2DebugInStandbyMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2);
+}
+
+/**
+  * @brief  Disable D2 Domain debug during STANDBY mode
+  * @rmtoll DBGMCU_CR    DBGSTBY_D2     LL_DBGMCU_DisableD2DebugInStandbyMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableD2DebugInStandbyMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2);
+}
+#endif /* DUAL_CORE */
+
+
+/**
+  * @brief  Enable D3 Domain/SRDomain debug during STOP mode
+  * @rmtoll DBGMCU_CR    DBGSTOP_D3/DBGSTOP_SRD    LL_DBGMCU_EnableD3DebugInStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableD3DebugInStopMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
+}
+
+/**
+  * @brief  Disable D3 Domain/SRDomain debug during STOP mode
+  * @rmtoll DBGMCU_CR    DBGSTOP_D3/DBGSTOP_SRD     LL_DBGMCU_DisableD3DebugInStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableD3DebugInStopMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
+}
+
+/**
+  * @brief  Enable D3 Domain/SRDomain debug during STANDBY mode
+  * @rmtoll DBGMCU_CR    DBGSTBY_D3/DBGSTBY_SRD     LL_DBGMCU_EnableD3DebugInStandbyMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableD3DebugInStandbyMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
+}
+
+/**
+  * @brief  Disable D3 Domain/SRDomain debug during STANDBY mode
+  * @rmtoll DBGMCU_CR    DBGSTBY_D3/DBGSTBY_SRD     LL_DBGMCU_DisableD3DebugInStandbyMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableD3DebugInStandbyMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
+}
+
+/**
+  * @brief  Enable the trace port clock
+  * @rmtoll DBGMCU_CR    TRACECKEN     LL_DBGMCU_EnableTracePortClock
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableTracePortClock(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRACECKEN);
+}
+
+/**
+  * @brief  Disable the trace port clock
+  * @rmtoll DBGMCU_CR    TRACECKEN     LL_DBGMCU_DisableTracePortClock
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableTracePortClock(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRACECKEN);
+}
+
+/**
+  * @brief  Enable the Domain1/CDomain debug clock enable
+  * @rmtoll DBGMCU_CR    CKD1EN/CKCDEN     LL_DBGMCU_EnableD1DebugClock
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableD1DebugClock(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD1EN);
+}
+
+/**
+  * @brief  Disable the Domain1/CDomain debug clock enable
+  * @rmtoll DBGMCU_CR    CKD1EN/CKCDEN     LL_DBGMCU_DisableD1DebugClock
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableD1DebugClock(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD1EN);
+}
+
+/**
+  * @brief  Enable the Domain3/SRDomain debug clock enable
+  * @rmtoll DBGMCU_CR    CKD3EN/CKSRDEN     LL_DBGMCU_EnableD3DebugClock
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableD3DebugClock(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD3EN);
+}
+
+/**
+  * @brief  Disable the Domain3/SRDomain debug clock enable
+  * @rmtoll DBGMCU_CR    CKD3EN/CKSRDEN    LL_DBGMCU_DisableD3DebugClock
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableD3DebugClock(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD3EN);
+}
+
+#define LL_DBGMCU_TRGIO_INPUT_DIRECTION   0U
+#define LL_DBGMCU_TRGIO_OUTPUT_DIRECTION  DBGMCU_CR_DBG_TRGOEN
+/**
+  * @brief  Set the direction of the bi-directional trigger pin TRGIO
+  * @rmtoll DBGMCU_CR    TRGOEN    LL_DBGMCU_SetExternalTriggerPinDirection\n
+  * @param  PinDirection This parameter can be one of the following values:
+  *         @arg @ref LL_DBGMCU_TRGIO_INPUT_DIRECTION
+  *         @arg @ref LL_DBGMCU_TRGIO_OUTPUT_DIRECTION
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_SetExternalTriggerPinDirection(uint32_t PinDirection)
+{
+  MODIFY_REG(DBGMCU->CR, DBGMCU_CR_DBG_TRGOEN, PinDirection);
+}
+
+/**
+  * @brief  Get the direction of the bi-directional trigger pin TRGIO
+  * @rmtoll DBGMCU_CR    TRGOEN    LL_DBGMCU_GetExternalTriggerPinDirection\n
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DBGMCU_TRGIO_INPUT_DIRECTION
+  *         @arg @ref LL_DBGMCU_TRGIO_OUTPUT_DIRECTION
+  */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetExternalTriggerPinDirection(void)
+{
+  return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRGOEN));
+}
+
+/**
+  * @brief  Freeze APB1 group1 peripherals
+  * @rmtoll DBGMCU_APB1LFZ1   TIM2      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM3      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM4      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM5      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM6      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM7      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM12     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM13     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM14     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   LPTIM1    LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   I2C1      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   I2C2      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   I2C3      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
+{
+  SET_BIT(DBGMCU->APB1LFZ1, Periphs);
+}
+
+/**
+  * @brief  Unfreeze APB1 peripherals (group1 peripherals)
+  * @rmtoll DBGMCU_APB1LFZ1   TIM2      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM3      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM4      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM5      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM6      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM7      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM12     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM13     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   TIM14     LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   LPTIM1    LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   I2C1      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   I2C2      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1LFZ1   I2C3      LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
+{
+  CLEAR_BIT(DBGMCU->APB1LFZ1, Periphs);
+}
+
+/**
+  * @brief  Freeze APB1 group2 peripherals
+  * @rmtoll DBGMCU_APB1HFZ1   FDCAN   LL_DBGMCU_APB1_GRP2_FreezePeriph\n
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB1_GRP2_FDCAN_STOP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
+{
+  SET_BIT(DBGMCU->APB1HFZ1, Periphs);
+}
+
+/**
+  * @brief  Unfreeze APB1 group2 peripherals
+  * @rmtoll DBGMCU_APB1HFZ1   FDCAN   LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB1_GRP2_FDCAN_STOP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
+{
+  CLEAR_BIT(DBGMCU->APB1HFZ1, Periphs);
+}
+
+/**
+  * @brief  Freeze APB2 peripherals
+  * @rmtoll DBGMCU_APB2FZ1    TIM1     LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+  *         DBGMCU_APB2FZ1    TIM8     LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+  *         DBGMCU_APB2FZ1    TIM15    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+  *         DBGMCU_APB2FZ1    TIM16    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+  *         DBGMCU_APB2FZ1    TIM17    LL_DBGMCU_APB2_GRP1_FreezePeriph
+  *         DBGMCU_APB2FZ1    HRTIM    LL_DBGMCU_APB2_GRP1_FreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM_STOP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
+{
+  SET_BIT(DBGMCU->APB2FZ1, Periphs);
+}
+
+/**
+  * @brief  Unfreeze APB2 peripherals
+  * @rmtoll DBGMCU_APB2FZ1    TIM1     LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+  *         DBGMCU_APB2FZ1    TIM8     LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+  *         DBGMCU_APB2FZ1    TIM15    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+  *         DBGMCU_APB2FZ1    TIM16    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+  *         DBGMCU_APB2FZ1    TIM17    LL_DBGMCU_APB2_GRP1_FreezePeriph
+  *         DBGMCU_APB2FZ1    HRTIM    LL_DBGMCU_APB2_GRP1_FreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM_STOP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
+{
+  CLEAR_BIT(DBGMCU->APB2FZ1, Periphs);
+}
+
+/**
+  * @brief  Freeze APB3 peripherals
+  * @rmtoll DBGMCU_APB3FZ1    WWDG1     LL_DBGMCU_APB3_GRP1_FreezePeriph\n
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB3_GRP1_WWDG1_STOP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB3_GRP1_FreezePeriph(uint32_t Periphs)
+{
+  SET_BIT(DBGMCU->APB3FZ1, Periphs);
+}
+
+/**
+  * @brief  Unfreeze APB3 peripherals
+  * @rmtoll DBGMCU_APB3FZ1    WWDG1     LL_DBGMCU_APB3_GRP1_UnFreezePeriph\n
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB3_GRP1_WWDG1_STOP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB3_GRP1_UnFreezePeriph(uint32_t Periphs)
+{
+  CLEAR_BIT(DBGMCU->APB3FZ1, Periphs);
+}
+
+/**
+  * @brief  Freeze APB4 peripherals
+  * @rmtoll DBGMCU_APB4FZ1    I2C4      LL_DBGMCU_APB4_GRP1_FreezePeriph\n
+  * @rmtoll DBGMCU_APB4FZ1    LPTIM2    LL_DBGMCU_APB4_GRP1_FreezePeriph\n
+  * @rmtoll DBGMCU_APB4FZ1    LPTIM3    LL_DBGMCU_APB4_GRP1_FreezePeriph\n
+  * @rmtoll DBGMCU_APB4FZ1    LPTIM4    LL_DBGMCU_APB4_GRP1_FreezePeriph\n
+  * @rmtoll DBGMCU_APB4FZ1    LPTIM5    LL_DBGMCU_APB4_GRP1_FreezePeriph\n
+  * @rmtoll DBGMCU_APB4FZ1    RTC       LL_DBGMCU_APB4_GRP1_FreezePeriph\n
+  * @rmtoll DBGMCU_APB4FZ1    WDGLSD1   LL_DBGMCU_APB4_GRP1_FreezePeriph\n
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_I2C4_STOP
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_IWDG1_STOP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB4_GRP1_FreezePeriph(uint32_t Periphs)
+{
+  SET_BIT(DBGMCU->APB4FZ1, Periphs);
+}
+
+/**
+  * @brief  Unfreeze APB4 peripherals
+  * @rmtoll DBGMCU_APB4FZ1    I2C4      LL_DBGMCU_APB4_GRP1_FreezePeriph\n
+  * @rmtoll DBGMCU_APB4FZ1    LPTIM2    LL_DBGMCU_APB4_GRP1_FreezePeriph\n
+  * @rmtoll DBGMCU_APB4FZ1    LPTIM3    LL_DBGMCU_APB4_GRP1_FreezePeriph\n
+  * @rmtoll DBGMCU_APB4FZ1    LPTIM4    LL_DBGMCU_APB4_GRP1_FreezePeriph\n
+  * @rmtoll DBGMCU_APB4FZ1    LPTIM5    LL_DBGMCU_APB4_GRP1_FreezePeriph\n
+  * @rmtoll DBGMCU_APB4FZ1    RTC       LL_DBGMCU_APB4_GRP1_FreezePeriph\n
+  * @rmtoll DBGMCU_APB4FZ1    WDGLSD1   LL_DBGMCU_APB4_GRP1_FreezePeriph\n
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_I2C4_STOP
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP
+  *         @arg @ref LL_DBGMCU_APB4_GRP1_IWDG1_STOP
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB4_GRP1_UnFreezePeriph(uint32_t Periphs)
+{
+  CLEAR_BIT(DBGMCU->APB4FZ1, Periphs);
+}
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EF_FLASH FLASH
+  * @{
+  */
+
+/**
+  * @brief  Set FLASH Latency
+  * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_SetLatency
+  * @param  Latency This parameter can be one of the following values:
+  *         @arg @ref LL_FLASH_LATENCY_0
+  *         @arg @ref LL_FLASH_LATENCY_1
+  *         @arg @ref LL_FLASH_LATENCY_2
+  *         @arg @ref LL_FLASH_LATENCY_3
+  *         @arg @ref LL_FLASH_LATENCY_4
+  *         @arg @ref LL_FLASH_LATENCY_5
+  *         @arg @ref LL_FLASH_LATENCY_6
+  *         @arg @ref LL_FLASH_LATENCY_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
+{
+  MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
+}
+
+/**
+  * @brief  Get FLASH Latency
+  * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_GetLatency
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_FLASH_LATENCY_0
+  *         @arg @ref LL_FLASH_LATENCY_1
+  *         @arg @ref LL_FLASH_LATENCY_2
+  *         @arg @ref LL_FLASH_LATENCY_3
+  *         @arg @ref LL_FLASH_LATENCY_4
+  *         @arg @ref LL_FLASH_LATENCY_5
+  *         @arg @ref LL_FLASH_LATENCY_6
+  *         @arg @ref LL_FLASH_LATENCY_7
+  */
+__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
+{
+  return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
+}
+
+/**
+  * @}
+  */
+
+#if defined(DUAL_CORE)
+/** @defgroup SYSTEM_LL_EF_ART ART
+  * @{
+  */
+
+/**
+  * @brief  Enable the Cortex-M4 ART cache.
+  * @rmtoll ART_CTR    EN   LL_ART_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_ART_Enable(void)
+{
+ SET_BIT(ART->CTR, ART_CTR_EN);
+}
+
+/**
+  * @brief  Disable the Cortex-M4 ART cache.
+  * @rmtoll ART_CTR    EN   LL_ART_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_ART_Disable(void)
+{
+ CLEAR_BIT(ART->CTR, ART_CTR_EN);
+}
+
+/**
+  * @brief  Check if the Cortex-M4 ART cache is enabled
+  * @rmtoll ART_CTR   EN    LL_ART_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ART_IsEnabled(void)
+{
+  return ((READ_BIT(ART->CTR, ART_CTR_EN) == ART_CTR_EN) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the Cortex-M4 ART cache Base Address.
+  * @rmtoll ART_CTR    PCACHEADDR   LL_ART_SetBaseAddress
+  * @param  BaseAddress Specifies the Base address of 1 Mbyte address page (cacheable page)
+            from which the ART accelerator loads code to the cache.
+  * @retval None
+  */
+__STATIC_INLINE void LL_ART_SetBaseAddress(uint32_t BaseAddress)
+{
+ MODIFY_REG(ART->CTR, ART_CTR_PCACHEADDR, (((BaseAddress) >> 12U) & 0x000FFF00UL));
+}
+
+/**
+  * @brief  Get the Cortex-M4 ART cache Base Address.
+  * @rmtoll ART_CTR    PCACHEADDR   LL_ART_GetBaseAddress
+  * @retval the Base address of 1 Mbyte address page (cacheable page)
+            from which the ART accelerator loads code to the cache
+  */
+__STATIC_INLINE uint32_t LL_ART_GetBaseAddress(void)
+{
+  return (uint32_t)(READ_BIT(ART->CTR, ART_CTR_PCACHEADDR) << 12U);
+}
+#endif /* DUAL_CORE */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32H7xx_LL_SYSTEM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usart.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usart.h
new file mode 100644
index 00000000..63941018
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usart.h
@@ -0,0 +1,4385 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_usart.h
+  * @author  MCD Application Team
+  * @brief   Header file of USART LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_LL_USART_H
+#define STM32H7xx_LL_USART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5) || defined (UART7) || defined (UART8) || defined (UART9) || defined (USART10)
+
+/** @defgroup USART_LL USART
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup USART_LL_Private_Variables USART Private Variables
+  * @{
+  */
+/* Array used to get the USART prescaler division decimal values versus @ref USART_LL_EC_PRESCALER values */
+static const uint32_t USART_PRESCALER_TAB[] =
+{
+  1UL,
+  2UL,
+  4UL,
+  6UL,
+  8UL,
+  10UL,
+  12UL,
+  16UL,
+  32UL,
+  64UL,
+  128UL,
+  256UL
+};
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_Private_Macros USART Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_ES_INIT USART Exported Init structures
+  * @{
+  */
+
+/**
+  * @brief LL USART Init Structure definition
+  */
+typedef struct
+{
+  uint32_t PrescalerValue;            /*!< Specifies the Prescaler to compute the communication baud rate.
+                                           This parameter can be a value of @ref USART_LL_EC_PRESCALER.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetPrescaler().*/
+
+  uint32_t BaudRate;                  /*!< This field defines expected Usart communication baud rate.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/
+
+  uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/
+
+  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
+                                           This parameter can be a value of @ref USART_LL_EC_STOPBITS.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/
+
+  uint32_t Parity;                    /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref USART_LL_EC_PARITY.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/
+
+  uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref USART_LL_EC_DIRECTION.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/
+
+  uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.
+                                           This parameter can be a value of @ref USART_LL_EC_HWCONTROL.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/
+
+  uint32_t OverSampling;              /*!< Specifies whether USART oversampling mode is 16 or 8.
+                                           This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/
+
+} LL_USART_InitTypeDef;
+
+/**
+  * @brief LL USART Clock Init Structure definition
+  */
+typedef struct
+{
+  uint32_t ClockOutput;               /*!< Specifies whether the USART clock is enabled or disabled.
+                                           This parameter can be a value of @ref USART_LL_EC_CLOCK.
+
+                                           USART HW configuration can be modified afterwards using unitary functions
+                                           @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput().
+                                           For more details, refer to description of this function. */
+
+  uint32_t ClockPolarity;             /*!< Specifies the steady state of the serial clock.
+                                           This parameter can be a value of @ref USART_LL_EC_POLARITY.
+
+                                           USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity().
+                                           For more details, refer to description of this function. */
+
+  uint32_t ClockPhase;                /*!< Specifies the clock transition on which the bit capture is made.
+                                           This parameter can be a value of @ref USART_LL_EC_PHASE.
+
+                                           USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase().
+                                           For more details, refer to description of this function. */
+
+  uint32_t LastBitClockPulse;         /*!< Specifies whether the clock pulse corresponding to the last transmitted
+                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+                                           This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.
+
+                                           USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput().
+                                           For more details, refer to description of this function. */
+
+} LL_USART_ClockInitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup USART_LL_Exported_Constants USART Exported Constants
+  * @{
+  */
+
+/** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_USART_WriteReg function
+  * @{
+  */
+#define LL_USART_ICR_PECF                       USART_ICR_PECF                /*!< Parity error flag */
+#define LL_USART_ICR_FECF                       USART_ICR_FECF                /*!< Framing error flag */
+#define LL_USART_ICR_NECF                       USART_ICR_NECF                /*!< Noise error detected flag */
+#define LL_USART_ICR_ORECF                      USART_ICR_ORECF               /*!< Overrun error flag */
+#define LL_USART_ICR_IDLECF                     USART_ICR_IDLECF              /*!< Idle line detected flag */
+#define LL_USART_ICR_TXFECF                     USART_ICR_TXFECF              /*!< TX FIFO Empty Clear flag */
+#define LL_USART_ICR_TCCF                       USART_ICR_TCCF                /*!< Transmission complete flag */
+#define LL_USART_ICR_TCBGTCF                    USART_ICR_TCBGTCF             /*!< Transmission completed before guard time flag */
+#define LL_USART_ICR_LBDCF                      USART_ICR_LBDCF               /*!< LIN break detection flag */
+#define LL_USART_ICR_CTSCF                      USART_ICR_CTSCF               /*!< CTS flag */
+#define LL_USART_ICR_RTOCF                      USART_ICR_RTOCF               /*!< Receiver timeout flag */
+#define LL_USART_ICR_EOBCF                      USART_ICR_EOBCF               /*!< End of block flag */
+#define LL_USART_ICR_UDRCF                      USART_ICR_UDRCF               /*!< SPI Slave Underrun Clear flag */
+#define LL_USART_ICR_CMCF                       USART_ICR_CMCF                /*!< Character match flag */
+#define LL_USART_ICR_WUCF                       USART_ICR_WUCF                /*!< Wakeup from Stop mode flag */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_USART_ReadReg function
+  * @{
+  */
+#define LL_USART_ISR_PE                         USART_ISR_PE                  /*!< Parity error flag */
+#define LL_USART_ISR_FE                         USART_ISR_FE                  /*!< Framing error flag */
+#define LL_USART_ISR_NE                         USART_ISR_NE                  /*!< Noise detected flag */
+#define LL_USART_ISR_ORE                        USART_ISR_ORE                 /*!< Overrun error flag */
+#define LL_USART_ISR_IDLE                       USART_ISR_IDLE                /*!< Idle line detected flag */
+#define LL_USART_ISR_RXNE_RXFNE                 USART_ISR_RXNE_RXFNE          /*!< Read data register or RX FIFO not empty flag */
+#define LL_USART_ISR_TC                         USART_ISR_TC                  /*!< Transmission complete flag */
+#define LL_USART_ISR_TXE_TXFNF                  USART_ISR_TXE_TXFNF           /*!< Transmit data register empty or TX FIFO Not Full flag*/
+#define LL_USART_ISR_LBDF                       USART_ISR_LBDF                /*!< LIN break detection flag */
+#define LL_USART_ISR_CTSIF                      USART_ISR_CTSIF               /*!< CTS interrupt flag */
+#define LL_USART_ISR_CTS                        USART_ISR_CTS                 /*!< CTS flag */
+#define LL_USART_ISR_RTOF                       USART_ISR_RTOF                /*!< Receiver timeout flag */
+#define LL_USART_ISR_EOBF                       USART_ISR_EOBF                /*!< End of block flag */
+#define LL_USART_ISR_UDR                        USART_ISR_UDR                 /*!< SPI Slave underrun error flag */
+#define LL_USART_ISR_ABRE                       USART_ISR_ABRE                /*!< Auto baud rate error flag */
+#define LL_USART_ISR_ABRF                       USART_ISR_ABRF                /*!< Auto baud rate flag */
+#define LL_USART_ISR_BUSY                       USART_ISR_BUSY                /*!< Busy flag */
+#define LL_USART_ISR_CMF                        USART_ISR_CMF                 /*!< Character match flag */
+#define LL_USART_ISR_SBKF                       USART_ISR_SBKF                /*!< Send break flag */
+#define LL_USART_ISR_RWU                        USART_ISR_RWU                 /*!< Receiver wakeup from Mute mode flag */
+#define LL_USART_ISR_WUF                        USART_ISR_WUF                 /*!< Wakeup from Stop mode flag */
+#define LL_USART_ISR_TEACK                      USART_ISR_TEACK               /*!< Transmit enable acknowledge flag */
+#define LL_USART_ISR_REACK                      USART_ISR_REACK               /*!< Receive enable acknowledge flag */
+#define LL_USART_ISR_TXFE                       USART_ISR_TXFE                /*!< TX FIFO empty flag */
+#define LL_USART_ISR_RXFF                       USART_ISR_RXFF                /*!< RX FIFO full flag */
+#define LL_USART_ISR_TCBGT                      USART_ISR_TCBGT               /*!< Transmission complete before guard time completion flag */
+#define LL_USART_ISR_RXFT                       USART_ISR_RXFT                /*!< RX FIFO threshold flag */
+#define LL_USART_ISR_TXFT                       USART_ISR_TXFT                /*!< TX FIFO threshold flag */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_USART_ReadReg and  LL_USART_WriteReg functions
+  * @{
+  */
+#define LL_USART_CR1_IDLEIE                     USART_CR1_IDLEIE              /*!< IDLE interrupt enable */
+#define LL_USART_CR1_RXNEIE_RXFNEIE             USART_CR1_RXNEIE_RXFNEIE      /*!< Read data register and RXFIFO not empty interrupt enable */
+#define LL_USART_CR1_TCIE                       USART_CR1_TCIE                /*!< Transmission complete interrupt enable */
+#define LL_USART_CR1_TXEIE_TXFNFIE              USART_CR1_TXEIE_TXFNFIE       /*!< Transmit data register empty and TX FIFO not full interrupt enable */
+#define LL_USART_CR1_PEIE                       USART_CR1_PEIE                /*!< Parity error */
+#define LL_USART_CR1_CMIE                       USART_CR1_CMIE                /*!< Character match interrupt enable */
+#define LL_USART_CR1_RTOIE                      USART_CR1_RTOIE               /*!< Receiver timeout interrupt enable */
+#define LL_USART_CR1_EOBIE                      USART_CR1_EOBIE               /*!< End of Block interrupt enable */
+#define LL_USART_CR1_TXFEIE                     USART_CR1_TXFEIE              /*!< TX FIFO empty interrupt enable */
+#define LL_USART_CR1_RXFFIE                     USART_CR1_RXFFIE              /*!< RX FIFO full interrupt enable */
+#define LL_USART_CR2_LBDIE                      USART_CR2_LBDIE               /*!< LIN break detection interrupt enable */
+#define LL_USART_CR3_EIE                        USART_CR3_EIE                 /*!< Error interrupt enable */
+#define LL_USART_CR3_CTSIE                      USART_CR3_CTSIE               /*!< CTS interrupt enable */
+#define LL_USART_CR3_WUFIE                      USART_CR3_WUFIE               /*!< Wakeup from Stop mode interrupt enable */
+#define LL_USART_CR3_TXFTIE                     USART_CR3_TXFTIE              /*!< TX FIFO threshold interrupt enable */
+#define LL_USART_CR3_TCBGTIE                    USART_CR3_TCBGTIE             /*!< Transmission complete before guard time interrupt enable */
+#define LL_USART_CR3_RXFTIE                     USART_CR3_RXFTIE              /*!< RX FIFO threshold interrupt enable */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_FIFOTHRESHOLD FIFO Threshold
+  * @{
+  */
+#define LL_USART_FIFOTHRESHOLD_1_8              0x00000000U /*!< FIFO reaches 1/8 of its depth */
+#define LL_USART_FIFOTHRESHOLD_1_4              0x00000001U /*!< FIFO reaches 1/4 of its depth */
+#define LL_USART_FIFOTHRESHOLD_1_2              0x00000002U /*!< FIFO reaches 1/2 of its depth */
+#define LL_USART_FIFOTHRESHOLD_3_4              0x00000003U /*!< FIFO reaches 3/4 of its depth */
+#define LL_USART_FIFOTHRESHOLD_7_8              0x00000004U /*!< FIFO reaches 7/8 of its depth */
+#define LL_USART_FIFOTHRESHOLD_8_8              0x00000005U /*!< FIFO becomes empty for TX and full for RX */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_DIRECTION Communication Direction
+  * @{
+  */
+#define LL_USART_DIRECTION_NONE                 0x00000000U                        /*!< Transmitter and Receiver are disabled */
+#define LL_USART_DIRECTION_RX                   USART_CR1_RE                       /*!< Transmitter is disabled and Receiver is enabled */
+#define LL_USART_DIRECTION_TX                   USART_CR1_TE                       /*!< Transmitter is enabled and Receiver is disabled */
+#define LL_USART_DIRECTION_TX_RX                (USART_CR1_TE |USART_CR1_RE)       /*!< Transmitter and Receiver are enabled */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_PARITY Parity Control
+  * @{
+  */
+#define LL_USART_PARITY_NONE                    0x00000000U                          /*!< Parity control disabled */
+#define LL_USART_PARITY_EVEN                    USART_CR1_PCE                        /*!< Parity control enabled and Even Parity is selected */
+#define LL_USART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)       /*!< Parity control enabled and Odd Parity is selected */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_WAKEUP Wakeup
+  * @{
+  */
+#define LL_USART_WAKEUP_IDLELINE                0x00000000U           /*!<  USART wake up from Mute mode on Idle Line */
+#define LL_USART_WAKEUP_ADDRESSMARK             USART_CR1_WAKE        /*!<  USART wake up from Mute mode on Address Mark */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_DATAWIDTH Datawidth
+  * @{
+  */
+#define LL_USART_DATAWIDTH_7B                   USART_CR1_M1            /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
+#define LL_USART_DATAWIDTH_8B                   0x00000000U             /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
+#define LL_USART_DATAWIDTH_9B                   USART_CR1_M0            /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling
+  * @{
+  */
+#define LL_USART_OVERSAMPLING_16                0x00000000U            /*!< Oversampling by 16 */
+#define LL_USART_OVERSAMPLING_8                 USART_CR1_OVER8        /*!< Oversampling by 8 */
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_EC_CLOCK Clock Signal
+  * @{
+  */
+
+#define LL_USART_CLOCK_DISABLE                  0x00000000U            /*!< Clock signal not provided */
+#define LL_USART_CLOCK_ENABLE                   USART_CR2_CLKEN        /*!< Clock signal provided */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse
+  * @{
+  */
+#define LL_USART_LASTCLKPULSE_NO_OUTPUT         0x00000000U           /*!< The clock pulse of the last data bit is not output to the SCLK pin */
+#define LL_USART_LASTCLKPULSE_OUTPUT            USART_CR2_LBCL        /*!< The clock pulse of the last data bit is output to the SCLK pin */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_PHASE Clock Phase
+  * @{
+  */
+#define LL_USART_PHASE_1EDGE                    0x00000000U           /*!< The first clock transition is the first data capture edge */
+#define LL_USART_PHASE_2EDGE                    USART_CR2_CPHA        /*!< The second clock transition is the first data capture edge */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_POLARITY Clock Polarity
+  * @{
+  */
+#define LL_USART_POLARITY_LOW                   0x00000000U           /*!< Steady low value on SCLK pin outside transmission window*/
+#define LL_USART_POLARITY_HIGH                  USART_CR2_CPOL        /*!< Steady high value on SCLK pin outside transmission window */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_PRESCALER Clock Source Prescaler
+  * @{
+  */
+#define LL_USART_PRESCALER_DIV1                 0x00000000U                                                                   /*!< Input clock not devided   */
+#define LL_USART_PRESCALER_DIV2                 (USART_PRESC_PRESCALER_0)                                                     /*!< Input clock devided by 2  */
+#define LL_USART_PRESCALER_DIV4                 (USART_PRESC_PRESCALER_1)                                                     /*!< Input clock devided by 4  */
+#define LL_USART_PRESCALER_DIV6                 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)                           /*!< Input clock devided by 6  */
+#define LL_USART_PRESCALER_DIV8                 (USART_PRESC_PRESCALER_2)                                                     /*!< Input clock devided by 8  */
+#define LL_USART_PRESCALER_DIV10                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0)                           /*!< Input clock devided by 10 */
+#define LL_USART_PRESCALER_DIV12                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1)                           /*!< Input clock devided by 12 */
+#define LL_USART_PRESCALER_DIV16                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 16 */
+#define LL_USART_PRESCALER_DIV32                (USART_PRESC_PRESCALER_3)                                                     /*!< Input clock devided by 32 */
+#define LL_USART_PRESCALER_DIV64                (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0)                           /*!< Input clock devided by 64 */
+#define LL_USART_PRESCALER_DIV128               (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1)                           /*!< Input clock devided by 128 */
+#define LL_USART_PRESCALER_DIV256               (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 256 */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_STOPBITS Stop Bits
+  * @{
+  */
+#define LL_USART_STOPBITS_0_5                   USART_CR2_STOP_0                           /*!< 0.5 stop bit */
+#define LL_USART_STOPBITS_1                     0x00000000U                                /*!< 1 stop bit */
+#define LL_USART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1)      /*!< 1.5 stop bits */
+#define LL_USART_STOPBITS_2                     USART_CR2_STOP_1                           /*!< 2 stop bits */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_TXRX TX RX Pins Swap
+  * @{
+  */
+#define LL_USART_TXRX_STANDARD                  0x00000000U           /*!< TX/RX pins are used as defined in standard pinout */
+#define LL_USART_TXRX_SWAPPED                   (USART_CR2_SWAP)      /*!< TX and RX pins functions are swapped.             */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
+  * @{
+  */
+#define LL_USART_RXPIN_LEVEL_STANDARD           0x00000000U           /*!< RX pin signal works using the standard logic levels */
+#define LL_USART_RXPIN_LEVEL_INVERTED           (USART_CR2_RXINV)     /*!< RX pin signal values are inverted.                  */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
+  * @{
+  */
+#define LL_USART_TXPIN_LEVEL_STANDARD           0x00000000U           /*!< TX pin signal works using the standard logic levels */
+#define LL_USART_TXPIN_LEVEL_INVERTED           (USART_CR2_TXINV)     /*!< TX pin signal values are inverted.                  */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion
+  * @{
+  */
+#define LL_USART_BINARY_LOGIC_POSITIVE          0x00000000U           /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */
+#define LL_USART_BINARY_LOGIC_NEGATIVE          USART_CR2_DATAINV     /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_BITORDER Bit Order
+  * @{
+  */
+#define LL_USART_BITORDER_LSBFIRST              0x00000000U           /*!< data is transmitted/received with data bit 0 first, following the start bit */
+#define LL_USART_BITORDER_MSBFIRST              USART_CR2_MSBFIRST    /*!< data is transmitted/received with the MSB first, following the start bit */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection
+  * @{
+  */
+#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT    0x00000000U                                 /*!< Measurement of the start bit is used to detect the baud rate */
+#define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0                         /*!< Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx */
+#define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME    USART_CR2_ABRMODE_1                         /*!< 0x7F frame detection */
+#define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME    (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x55 frame detection */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection
+  * @{
+  */
+#define LL_USART_ADDRESS_DETECT_4B              0x00000000U           /*!< 4-bit address detection method selected */
+#define LL_USART_ADDRESS_DETECT_7B              USART_CR2_ADDM7       /*!< 7-bit address detection (in 8-bit data mode) method selected */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_HWCONTROL Hardware Control
+  * @{
+  */
+#define LL_USART_HWCONTROL_NONE                 0x00000000U                          /*!< CTS and RTS hardware flow control disabled */
+#define LL_USART_HWCONTROL_RTS                  USART_CR3_RTSE                       /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
+#define LL_USART_HWCONTROL_CTS                  USART_CR3_CTSE                       /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
+#define LL_USART_HWCONTROL_RTS_CTS              (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< CTS and RTS hardware flow control enabled */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation
+  * @{
+  */
+#define LL_USART_WAKEUP_ON_ADDRESS              0x00000000U                             /*!< Wake up active on address match */
+#define LL_USART_WAKEUP_ON_STARTBIT             USART_CR3_WUS_1                         /*!< Wake up active on Start bit detection */
+#define LL_USART_WAKEUP_ON_RXNE                 (USART_CR3_WUS_0 | USART_CR3_WUS_1)     /*!< Wake up active on RXNE */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
+  * @{
+  */
+#define LL_USART_IRDA_POWER_NORMAL              0x00000000U           /*!< IrDA normal power mode */
+#define LL_USART_IRDA_POWER_LOW                 USART_CR3_IRLP        /*!< IrDA low power mode */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length
+  * @{
+  */
+#define LL_USART_LINBREAK_DETECT_10B            0x00000000U           /*!< 10-bit break detection method selected */
+#define LL_USART_LINBREAK_DETECT_11B            USART_CR2_LBDL        /*!< 11-bit break detection method selected */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity
+  * @{
+  */
+#define LL_USART_DE_POLARITY_HIGH               0x00000000U           /*!< DE signal is active high */
+#define LL_USART_DE_POLARITY_LOW                USART_CR3_DEP         /*!< DE signal is active low */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data
+  * @{
+  */
+#define LL_USART_DMA_REG_DATA_TRANSMIT          0x00000000U          /*!< Get address of data register used for transmission */
+#define LL_USART_DMA_REG_DATA_RECEIVE           0x00000001U          /*!< Get address of data register used for reception */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup USART_LL_Exported_Macros USART Exported Macros
+  * @{
+  */
+
+/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in USART register
+  * @param  __INSTANCE__ USART Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in USART register
+  * @param  __INSTANCE__ USART Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
+  * @{
+  */
+
+/**
+  * @brief  Compute USARTDIV value according to Peripheral Clock and
+  *         expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
+  * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
+  * @param  __PRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PRESCALER_DIV1
+  *         @arg @ref LL_USART_PRESCALER_DIV2
+  *         @arg @ref LL_USART_PRESCALER_DIV4
+  *         @arg @ref LL_USART_PRESCALER_DIV6
+  *         @arg @ref LL_USART_PRESCALER_DIV8
+  *         @arg @ref LL_USART_PRESCALER_DIV10
+  *         @arg @ref LL_USART_PRESCALER_DIV12
+  *         @arg @ref LL_USART_PRESCALER_DIV16
+  *         @arg @ref LL_USART_PRESCALER_DIV32
+  *         @arg @ref LL_USART_PRESCALER_DIV64
+  *         @arg @ref LL_USART_PRESCALER_DIV128
+  *         @arg @ref LL_USART_PRESCALER_DIV256
+  * @param  __BAUDRATE__ Baud rate value to achieve
+  * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
+  */
+#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\
+                                                                               + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
+
+/**
+  * @brief  Compute USARTDIV value according to Peripheral Clock and
+  *         expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
+  * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
+  * @param  __PRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PRESCALER_DIV1
+  *         @arg @ref LL_USART_PRESCALER_DIV2
+  *         @arg @ref LL_USART_PRESCALER_DIV4
+  *         @arg @ref LL_USART_PRESCALER_DIV6
+  *         @arg @ref LL_USART_PRESCALER_DIV8
+  *         @arg @ref LL_USART_PRESCALER_DIV10
+  *         @arg @ref LL_USART_PRESCALER_DIV12
+  *         @arg @ref LL_USART_PRESCALER_DIV16
+  *         @arg @ref LL_USART_PRESCALER_DIV32
+  *         @arg @ref LL_USART_PRESCALER_DIV64
+  *         @arg @ref LL_USART_PRESCALER_DIV128
+  *         @arg @ref LL_USART_PRESCALER_DIV256
+  * @param  __BAUDRATE__ Baud rate value to achieve
+  * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
+  */
+#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) ((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\
+                                                                                + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup USART_LL_Exported_Functions USART Exported Functions
+  * @{
+  */
+
+/** @defgroup USART_LL_EF_Configuration Configuration functions
+  * @{
+  */
+
+/**
+  * @brief  USART Enable
+  * @rmtoll CR1          UE            LL_USART_Enable
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_UE);
+}
+
+/**
+  * @brief  USART Disable (all USART prescalers and outputs are disabled)
+  * @note   When USART is disabled, USART prescalers and outputs are stopped immediately,
+  *         and current operations are discarded. The configuration of the USART is kept, but all the status
+  *         flags, in the USARTx_ISR are set to their default values.
+  * @rmtoll CR1          UE            LL_USART_Disable
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_UE);
+}
+
+/**
+  * @brief  Indicate if USART is enabled
+  * @rmtoll CR1          UE            LL_USART_IsEnabled
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  FIFO Mode Enable
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          FIFOEN        LL_USART_EnableFIFO
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableFIFO(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_FIFOEN);
+}
+
+/**
+  * @brief  FIFO Mode Disable
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          FIFOEN        LL_USART_DisableFIFO
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableFIFO(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_FIFOEN);
+}
+
+/**
+  * @brief  Indicate if FIFO Mode is enabled
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          FIFOEN        LL_USART_IsEnabledFIFO
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure TX FIFO Threshold
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          TXFTCFG       LL_USART_SetTXFIFOThreshold
+  * @param  USARTx USART Instance
+  * @param  Threshold This parameter can be one of the following values:
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
+}
+
+/**
+  * @brief  Return TX FIFO Threshold Configuration
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          TXFTCFG       LL_USART_GetTXFIFOThreshold
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
+}
+
+/**
+  * @brief  Configure RX FIFO Threshold
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          RXFTCFG       LL_USART_SetRXFIFOThreshold
+  * @param  USARTx USART Instance
+  * @param  Threshold This parameter can be one of the following values:
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
+}
+
+/**
+  * @brief  Return RX FIFO Threshold Configuration
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          RXFTCFG       LL_USART_GetRXFIFOThreshold
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+  */
+__STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
+}
+
+/**
+  * @brief  Configure TX and RX FIFOs Threshold
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          TXFTCFG       LL_USART_ConfigFIFOsThreshold\n
+  *         CR3          RXFTCFG       LL_USART_ConfigFIFOsThreshold
+  * @param  USARTx USART Instance
+  * @param  TXThreshold This parameter can be one of the following values:
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+  * @param  RXThreshold This parameter can be one of the following values:
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | (RXThreshold << USART_CR3_RXFTCFG_Pos));
+}
+
+/**
+  * @brief  USART enabled in STOP Mode.
+  * @note   When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that
+  *         USART clock selection is HSI or LSE in RCC.
+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          UESM          LL_USART_EnableInStopMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+  * @brief  USART disabled in STOP Mode.
+  * @note   When this function is disabled, USART is not able to wake up the MCU from Stop mode
+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          UESM          LL_USART_DisableInStopMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+  * @brief  Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          UESM          LL_USART_IsEnabledInStopMode
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)
+  * @rmtoll CR1          RE            LL_USART_EnableDirectionRx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_RE);
+}
+
+/**
+  * @brief  Receiver Disable
+  * @rmtoll CR1          RE            LL_USART_DisableDirectionRx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
+}
+
+/**
+  * @brief  Transmitter Enable
+  * @rmtoll CR1          TE            LL_USART_EnableDirectionTx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_TE);
+}
+
+/**
+  * @brief  Transmitter Disable
+  * @rmtoll CR1          TE            LL_USART_DisableDirectionTx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
+}
+
+/**
+  * @brief  Configure simultaneously enabled/disabled states
+  *         of Transmitter and Receiver
+  * @rmtoll CR1          RE            LL_USART_SetTransferDirection\n
+  *         CR1          TE            LL_USART_SetTransferDirection
+  * @param  USARTx USART Instance
+  * @param  TransferDirection This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DIRECTION_NONE
+  *         @arg @ref LL_USART_DIRECTION_RX
+  *         @arg @ref LL_USART_DIRECTION_TX
+  *         @arg @ref LL_USART_DIRECTION_TX_RX
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
+}
+
+/**
+  * @brief  Return enabled/disabled states of Transmitter and Receiver
+  * @rmtoll CR1          RE            LL_USART_GetTransferDirection\n
+  *         CR1          TE            LL_USART_GetTransferDirection
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_DIRECTION_NONE
+  *         @arg @ref LL_USART_DIRECTION_RX
+  *         @arg @ref LL_USART_DIRECTION_TX
+  *         @arg @ref LL_USART_DIRECTION_TX_RX
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
+}
+
+/**
+  * @brief  Configure Parity (enabled/disabled and parity mode if enabled).
+  * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.
+  *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
+  *         (9th or 8th bit depending on data width) and parity is checked on the received data.
+  * @rmtoll CR1          PS            LL_USART_SetParity\n
+  *         CR1          PCE           LL_USART_SetParity
+  * @param  USARTx USART Instance
+  * @param  Parity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PARITY_NONE
+  *         @arg @ref LL_USART_PARITY_EVEN
+  *         @arg @ref LL_USART_PARITY_ODD
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
+}
+
+/**
+  * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)
+  * @rmtoll CR1          PS            LL_USART_GetParity\n
+  *         CR1          PCE           LL_USART_GetParity
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_PARITY_NONE
+  *         @arg @ref LL_USART_PARITY_EVEN
+  *         @arg @ref LL_USART_PARITY_ODD
+  */
+__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
+}
+
+/**
+  * @brief  Set Receiver Wake Up method from Mute mode.
+  * @rmtoll CR1          WAKE          LL_USART_SetWakeUpMethod
+  * @param  USARTx USART Instance
+  * @param  Method This parameter can be one of the following values:
+  *         @arg @ref LL_USART_WAKEUP_IDLELINE
+  *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);
+}
+
+/**
+  * @brief  Return Receiver Wake Up method from Mute mode
+  * @rmtoll CR1          WAKE          LL_USART_GetWakeUpMethod
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_WAKEUP_IDLELINE
+  *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
+  */
+__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
+}
+
+/**
+  * @brief  Set Word length (i.e. nb of data bits, excluding start and stop bits)
+  * @rmtoll CR1          M0            LL_USART_SetDataWidth\n
+  *         CR1          M1            LL_USART_SetDataWidth
+  * @param  USARTx USART Instance
+  * @param  DataWidth This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DATAWIDTH_7B
+  *         @arg @ref LL_USART_DATAWIDTH_8B
+  *         @arg @ref LL_USART_DATAWIDTH_9B
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);
+}
+
+/**
+  * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)
+  * @rmtoll CR1          M0            LL_USART_GetDataWidth\n
+  *         CR1          M1            LL_USART_GetDataWidth
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_DATAWIDTH_7B
+  *         @arg @ref LL_USART_DATAWIDTH_8B
+  *         @arg @ref LL_USART_DATAWIDTH_9B
+  */
+__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
+}
+
+/**
+  * @brief  Allow switch between Mute Mode and Active mode
+  * @rmtoll CR1          MME           LL_USART_EnableMuteMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_MME);
+}
+
+/**
+  * @brief  Prevent Mute Mode use. Set Receiver in active mode permanently.
+  * @rmtoll CR1          MME           LL_USART_DisableMuteMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_MME);
+}
+
+/**
+  * @brief  Indicate if switch between Mute Mode and Active mode is allowed
+  * @rmtoll CR1          MME           LL_USART_IsEnabledMuteMode
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set Oversampling to 8-bit or 16-bit mode
+  * @rmtoll CR1          OVER8         LL_USART_SetOverSampling
+  * @param  USARTx USART Instance
+  * @param  OverSampling This parameter can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);
+}
+
+/**
+  * @brief  Return Oversampling mode
+  * @rmtoll CR1          OVER8         LL_USART_GetOverSampling
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  */
+__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
+}
+
+/**
+  * @brief  Configure if Clock pulse of the last data bit is output to the SCLK pin or not
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          LBCL          LL_USART_SetLastClkPulseOutput
+  * @param  USARTx USART Instance
+  * @param  LastBitClockPulse This parameter can be one of the following values:
+  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);
+}
+
+/**
+  * @brief  Retrieve Clock pulse of the last data bit output configuration
+  *         (Last bit Clock pulse output to the SCLK pin or not)
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          LBCL          LL_USART_GetLastClkPulseOutput
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+  */
+__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
+}
+
+/**
+  * @brief  Select the phase of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPHA          LL_USART_SetClockPhase
+  * @param  USARTx USART Instance
+  * @param  ClockPhase This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PHASE_1EDGE
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);
+}
+
+/**
+  * @brief  Return phase of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPHA          LL_USART_GetClockPhase
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_PHASE_1EDGE
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  */
+__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
+}
+
+/**
+  * @brief  Select the polarity of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPOL          LL_USART_SetClockPolarity
+  * @param  USARTx USART Instance
+  * @param  ClockPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_POLARITY_LOW
+  *         @arg @ref LL_USART_POLARITY_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);
+}
+
+/**
+  * @brief  Return polarity of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPOL          LL_USART_GetClockPolarity
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_POLARITY_LOW
+  *         @arg @ref LL_USART_POLARITY_HIGH
+  */
+__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
+}
+
+/**
+  * @brief  Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
+  *         - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function
+  *         - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function
+  * @rmtoll CR2          CPHA          LL_USART_ConfigClock\n
+  *         CR2          CPOL          LL_USART_ConfigClock\n
+  *         CR2          LBCL          LL_USART_ConfigClock
+  * @param  USARTx USART Instance
+  * @param  Phase This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PHASE_1EDGE
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_POLARITY_LOW
+  *         @arg @ref LL_USART_POLARITY_HIGH
+  * @param  LBCPOutput This parameter can be one of the following values:
+  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput);
+}
+
+/**
+  * @brief  Configure Clock source prescaler for baudrate generator and oversampling
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll PRESC        PRESCALER     LL_USART_SetPrescaler
+  * @param  USARTx USART Instance
+  * @param  PrescalerValue This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PRESCALER_DIV1
+  *         @arg @ref LL_USART_PRESCALER_DIV2
+  *         @arg @ref LL_USART_PRESCALER_DIV4
+  *         @arg @ref LL_USART_PRESCALER_DIV6
+  *         @arg @ref LL_USART_PRESCALER_DIV8
+  *         @arg @ref LL_USART_PRESCALER_DIV10
+  *         @arg @ref LL_USART_PRESCALER_DIV12
+  *         @arg @ref LL_USART_PRESCALER_DIV16
+  *         @arg @ref LL_USART_PRESCALER_DIV32
+  *         @arg @ref LL_USART_PRESCALER_DIV64
+  *         @arg @ref LL_USART_PRESCALER_DIV128
+  *         @arg @ref LL_USART_PRESCALER_DIV256
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+{
+  MODIFY_REG(USARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
+}
+
+/**
+  * @brief  Retrieve the Clock source prescaler for baudrate generator and oversampling
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll PRESC        PRESCALER     LL_USART_GetPrescaler
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_PRESCALER_DIV1
+  *         @arg @ref LL_USART_PRESCALER_DIV2
+  *         @arg @ref LL_USART_PRESCALER_DIV4
+  *         @arg @ref LL_USART_PRESCALER_DIV6
+  *         @arg @ref LL_USART_PRESCALER_DIV8
+  *         @arg @ref LL_USART_PRESCALER_DIV10
+  *         @arg @ref LL_USART_PRESCALER_DIV12
+  *         @arg @ref LL_USART_PRESCALER_DIV16
+  *         @arg @ref LL_USART_PRESCALER_DIV32
+  *         @arg @ref LL_USART_PRESCALER_DIV64
+  *         @arg @ref LL_USART_PRESCALER_DIV128
+  *         @arg @ref LL_USART_PRESCALER_DIV256
+  */
+__STATIC_INLINE uint32_t LL_USART_GetPrescaler(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->PRESC, USART_PRESC_PRESCALER));
+}
+
+/**
+  * @brief  Enable Clock output on SCLK pin
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CLKEN         LL_USART_EnableSCLKOutput
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+  * @brief  Disable Clock output on SCLK pin
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CLKEN         LL_USART_DisableSCLKOutput
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+  * @brief  Indicate if Clock output on SCLK pin is enabled
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CLKEN         LL_USART_IsEnabledSCLKOutput
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the length of the stop bits
+  * @rmtoll CR2          STOP          LL_USART_SetStopBitsLength
+  * @param  USARTx USART Instance
+  * @param  StopBits This parameter can be one of the following values:
+  *         @arg @ref LL_USART_STOPBITS_0_5
+  *         @arg @ref LL_USART_STOPBITS_1
+  *         @arg @ref LL_USART_STOPBITS_1_5
+  *         @arg @ref LL_USART_STOPBITS_2
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+  * @brief  Retrieve the length of the stop bits
+  * @rmtoll CR2          STOP          LL_USART_GetStopBitsLength
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_STOPBITS_0_5
+  *         @arg @ref LL_USART_STOPBITS_1
+  *         @arg @ref LL_USART_STOPBITS_1_5
+  *         @arg @ref LL_USART_STOPBITS_2
+  */
+__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
+}
+
+/**
+  * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Data Width configuration using @ref LL_USART_SetDataWidth() function
+  *         - Parity Control and mode configuration using @ref LL_USART_SetParity() function
+  *         - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function
+  * @rmtoll CR1          PS            LL_USART_ConfigCharacter\n
+  *         CR1          PCE           LL_USART_ConfigCharacter\n
+  *         CR1          M0            LL_USART_ConfigCharacter\n
+  *         CR1          M1            LL_USART_ConfigCharacter\n
+  *         CR2          STOP          LL_USART_ConfigCharacter
+  * @param  USARTx USART Instance
+  * @param  DataWidth This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DATAWIDTH_7B
+  *         @arg @ref LL_USART_DATAWIDTH_8B
+  *         @arg @ref LL_USART_DATAWIDTH_9B
+  * @param  Parity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PARITY_NONE
+  *         @arg @ref LL_USART_PARITY_EVEN
+  *         @arg @ref LL_USART_PARITY_ODD
+  * @param  StopBits This parameter can be one of the following values:
+  *         @arg @ref LL_USART_STOPBITS_0_5
+  *         @arg @ref LL_USART_STOPBITS_1
+  *         @arg @ref LL_USART_STOPBITS_1_5
+  *         @arg @ref LL_USART_STOPBITS_2
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity,
+                                              uint32_t StopBits)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
+  MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+  * @brief  Configure TX/RX pins swapping setting.
+  * @rmtoll CR2          SWAP          LL_USART_SetTXRXSwap
+  * @param  USARTx USART Instance
+  * @param  SwapConfig This parameter can be one of the following values:
+  *         @arg @ref LL_USART_TXRX_STANDARD
+  *         @arg @ref LL_USART_TXRX_SWAPPED
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig);
+}
+
+/**
+  * @brief  Retrieve TX/RX pins swapping configuration.
+  * @rmtoll CR2          SWAP          LL_USART_GetTXRXSwap
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_TXRX_STANDARD
+  *         @arg @ref LL_USART_TXRX_SWAPPED
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP));
+}
+
+/**
+  * @brief  Configure RX pin active level logic
+  * @rmtoll CR2          RXINV         LL_USART_SetRXPinLevel
+  * @param  USARTx USART Instance
+  * @param  PinInvMethod This parameter can be one of the following values:
+  *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod);
+}
+
+/**
+  * @brief  Retrieve RX pin active level logic configuration
+  * @rmtoll CR2          RXINV         LL_USART_GetRXPinLevel
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
+  */
+__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV));
+}
+
+/**
+  * @brief  Configure TX pin active level logic
+  * @rmtoll CR2          TXINV         LL_USART_SetTXPinLevel
+  * @param  USARTx USART Instance
+  * @param  PinInvMethod This parameter can be one of the following values:
+  *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod);
+}
+
+/**
+  * @brief  Retrieve TX pin active level logic configuration
+  * @rmtoll CR2          TXINV         LL_USART_GetTXPinLevel
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV));
+}
+
+/**
+  * @brief  Configure Binary data logic.
+  * @note   Allow to define how Logical data from the data register are send/received :
+  *         either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
+  * @rmtoll CR2          DATAINV       LL_USART_SetBinaryDataLogic
+  * @param  USARTx USART Instance
+  * @param  DataLogic This parameter can be one of the following values:
+  *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
+  *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic);
+}
+
+/**
+  * @brief  Retrieve Binary data configuration
+  * @rmtoll CR2          DATAINV       LL_USART_GetBinaryDataLogic
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
+  *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
+  */
+__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV));
+}
+
+/**
+  * @brief  Configure transfer bit order (either Less or Most Significant Bit First)
+  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
+  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
+  * @rmtoll CR2          MSBFIRST      LL_USART_SetTransferBitOrder
+  * @param  USARTx USART Instance
+  * @param  BitOrder This parameter can be one of the following values:
+  *         @arg @ref LL_USART_BITORDER_LSBFIRST
+  *         @arg @ref LL_USART_BITORDER_MSBFIRST
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
+}
+
+/**
+  * @brief  Return transfer bit order (either Less or Most Significant Bit First)
+  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
+  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
+  * @rmtoll CR2          MSBFIRST      LL_USART_GetTransferBitOrder
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_BITORDER_LSBFIRST
+  *         @arg @ref LL_USART_BITORDER_MSBFIRST
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST));
+}
+
+/**
+  * @brief  Enable Auto Baud-Rate Detection
+  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABREN         LL_USART_EnableAutoBaudRate
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_ABREN);
+}
+
+/**
+  * @brief  Disable Auto Baud-Rate Detection
+  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABREN         LL_USART_DisableAutoBaudRate
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN);
+}
+
+/**
+  * @brief  Indicate if Auto Baud-Rate Detection mechanism is enabled
+  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABREN         LL_USART_IsEnabledAutoBaud
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set Auto Baud-Rate mode bits
+  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABRMODE       LL_USART_SetAutoBaudRateMode
+  * @param  USARTx USART Instance
+  * @param  AutoBaudRateMode This parameter can be one of the following values:
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode);
+}
+
+/**
+  * @brief  Return Auto Baud-Rate mode
+  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABRMODE       LL_USART_GetAutoBaudRateMode
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
+  */
+__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE));
+}
+
+/**
+  * @brief  Enable Receiver Timeout
+  * @rmtoll CR2          RTOEN         LL_USART_EnableRxTimeout
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_RTOEN);
+}
+
+/**
+  * @brief  Disable Receiver Timeout
+  * @rmtoll CR2          RTOEN         LL_USART_DisableRxTimeout
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN);
+}
+
+/**
+  * @brief  Indicate if Receiver Timeout feature is enabled
+  * @rmtoll CR2          RTOEN         LL_USART_IsEnabledRxTimeout
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set Address of the USART node.
+  * @note   This is used in multiprocessor communication during Mute mode or Stop mode,
+  *         for wake up with address mark detection.
+  * @note   4bits address node is used when 4-bit Address Detection is selected in ADDM7.
+  *         (b7-b4 should be set to 0)
+  *         8bits address node is used when 7-bit Address Detection is selected in ADDM7.
+  *         (This is used in multiprocessor communication during Mute mode or Stop mode,
+  *         for wake up with 7-bit address mark detection.
+  *         The MSB of the character sent by the transmitter should be equal to 1.
+  *         It may also be used for character detection during normal reception,
+  *         Mute mode inactive (for example, end of block detection in ModBus protocol).
+  *         In this case, the whole received character (8-bit) is compared to the ADD[7:0]
+  *         value and CMF flag is set on match)
+  * @rmtoll CR2          ADD           LL_USART_ConfigNodeAddress\n
+  *         CR2          ADDM7         LL_USART_ConfigNodeAddress
+  * @param  USARTx USART Instance
+  * @param  AddressLen This parameter can be one of the following values:
+  *         @arg @ref LL_USART_ADDRESS_DETECT_4B
+  *         @arg @ref LL_USART_ADDRESS_DETECT_7B
+  * @param  NodeAddress 4 or 7 bit Address of the USART node.
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
+             (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
+}
+
+/**
+  * @brief  Return 8 bit Address of the USART node as set in ADD field of CR2.
+  * @note   If 4-bit Address Detection is selected in ADDM7,
+  *         only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
+  *         If 7-bit Address Detection is selected in ADDM7,
+  *         only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
+  * @rmtoll CR2          ADD           LL_USART_GetNodeAddress
+  * @param  USARTx USART Instance
+  * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
+}
+
+/**
+  * @brief  Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
+  * @rmtoll CR2          ADDM7         LL_USART_GetNodeAddressLen
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_ADDRESS_DETECT_4B
+  *         @arg @ref LL_USART_ADDRESS_DETECT_7B
+  */
+__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7));
+}
+
+/**
+  * @brief  Enable RTS HW Flow Control
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_EnableRTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+  * @brief  Disable RTS HW Flow Control
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_DisableRTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+  * @brief  Enable CTS HW Flow Control
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSE          LL_USART_EnableCTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+  * @brief  Disable CTS HW Flow Control
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSE          LL_USART_DisableCTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+  * @brief  Configure HW Flow Control mode (both CTS and RTS)
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_SetHWFlowCtrl\n
+  *         CR3          CTSE          LL_USART_SetHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @param  HardwareFlowControl This parameter can be one of the following values:
+  *         @arg @ref LL_USART_HWCONTROL_NONE
+  *         @arg @ref LL_USART_HWCONTROL_RTS
+  *         @arg @ref LL_USART_HWCONTROL_CTS
+  *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
+}
+
+/**
+  * @brief  Return HW Flow Control configuration (both CTS and RTS)
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_GetHWFlowCtrl\n
+  *         CR3          CTSE          LL_USART_GetHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_HWCONTROL_NONE
+  *         @arg @ref LL_USART_HWCONTROL_RTS
+  *         @arg @ref LL_USART_HWCONTROL_CTS
+  *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
+  */
+__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
+}
+
+/**
+  * @brief  Enable One bit sampling method
+  * @rmtoll CR3          ONEBIT        LL_USART_EnableOneBitSamp
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);
+}
+
+/**
+  * @brief  Disable One bit sampling method
+  * @rmtoll CR3          ONEBIT        LL_USART_DisableOneBitSamp
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);
+}
+
+/**
+  * @brief  Indicate if One bit sampling method is enabled
+  * @rmtoll CR3          ONEBIT        LL_USART_IsEnabledOneBitSamp
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Overrun detection
+  * @rmtoll CR3          OVRDIS        LL_USART_EnableOverrunDetect
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+  * @brief  Disable Overrun detection
+  * @rmtoll CR3          OVRDIS        LL_USART_DisableOverrunDetect
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+  * @brief  Indicate if Overrun detection is enabled
+  * @rmtoll CR3          OVRDIS        LL_USART_IsEnabledOverrunDetect
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUS           LL_USART_SetWKUPType
+  * @param  USARTx USART Instance
+  * @param  Type This parameter can be one of the following values:
+  *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
+  *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
+  *         @arg @ref LL_USART_WAKEUP_ON_RXNE
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type);
+}
+
+/**
+  * @brief  Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUS           LL_USART_GetWKUPType
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
+  *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
+  *         @arg @ref LL_USART_WAKEUP_ON_RXNE
+  */
+__STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS));
+}
+
+/**
+  * @brief  Configure USART BRR register for achieving expected Baud Rate value.
+  * @note   Compute and set USARTDIV value in BRR Register (full BRR content)
+  *         according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
+  * @note   Peripheral clock and Baud rate values provided as function parameters should be valid
+  *         (Baud rate value != 0)
+  * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
+  * @rmtoll BRR          BRR           LL_USART_SetBaudRate
+  * @param  USARTx USART Instance
+  * @param  PeriphClk Peripheral Clock
+  * @param  PrescalerValue This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PRESCALER_DIV1
+  *         @arg @ref LL_USART_PRESCALER_DIV2
+  *         @arg @ref LL_USART_PRESCALER_DIV4
+  *         @arg @ref LL_USART_PRESCALER_DIV6
+  *         @arg @ref LL_USART_PRESCALER_DIV8
+  *         @arg @ref LL_USART_PRESCALER_DIV10
+  *         @arg @ref LL_USART_PRESCALER_DIV12
+  *         @arg @ref LL_USART_PRESCALER_DIV16
+  *         @arg @ref LL_USART_PRESCALER_DIV32
+  *         @arg @ref LL_USART_PRESCALER_DIV64
+  *         @arg @ref LL_USART_PRESCALER_DIV128
+  *         @arg @ref LL_USART_PRESCALER_DIV256
+  * @param  OverSampling This parameter can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  * @param  BaudRate Baud Rate
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
+                                          uint32_t OverSampling,
+                                          uint32_t BaudRate)
+{
+  uint32_t usartdiv;
+  register uint32_t brrtemp;
+
+  if (PrescalerValue > LL_USART_PRESCALER_DIV256)
+  {
+    /* Do not overstep the size of USART_PRESCALER_TAB */
+  }
+  else if (OverSampling == LL_USART_OVERSAMPLING_8)
+  {
+    usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint8_t)PrescalerValue, BaudRate));
+    brrtemp = usartdiv & 0xFFF0U;
+    brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+    USARTx->BRR = brrtemp;
+  }
+  else
+  {
+    USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, (uint8_t)PrescalerValue, BaudRate));
+  }
+}
+
+/**
+  * @brief  Return current Baud Rate value, according to USARTDIV present in BRR register
+  *         (full BRR content), and to used Peripheral Clock and Oversampling mode values
+  * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
+  * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
+  * @rmtoll BRR          BRR           LL_USART_GetBaudRate
+  * @param  USARTx USART Instance
+  * @param  PeriphClk Peripheral Clock
+  * @param  PrescalerValue This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PRESCALER_DIV1
+  *         @arg @ref LL_USART_PRESCALER_DIV2
+  *         @arg @ref LL_USART_PRESCALER_DIV4
+  *         @arg @ref LL_USART_PRESCALER_DIV6
+  *         @arg @ref LL_USART_PRESCALER_DIV8
+  *         @arg @ref LL_USART_PRESCALER_DIV10
+  *         @arg @ref LL_USART_PRESCALER_DIV12
+  *         @arg @ref LL_USART_PRESCALER_DIV16
+  *         @arg @ref LL_USART_PRESCALER_DIV32
+  *         @arg @ref LL_USART_PRESCALER_DIV64
+  *         @arg @ref LL_USART_PRESCALER_DIV128
+  *         @arg @ref LL_USART_PRESCALER_DIV256
+  * @param  OverSampling This parameter can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  * @retval Baud Rate
+  */
+__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
+                                              uint32_t OverSampling)
+{
+  register uint32_t usartdiv;
+  register uint32_t brrresult = 0x0U;
+  register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (USART_PRESCALER_TAB[(uint8_t)PrescalerValue]));
+
+  usartdiv = USARTx->BRR;
+
+  if (usartdiv == 0U)
+  {
+    /* Do not perform a division by 0 */
+  }
+  else if (OverSampling == LL_USART_OVERSAMPLING_8)
+  {
+    usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
+    if (usartdiv != 0U)
+    {
+      brrresult = (periphclkpresc * 2U) / usartdiv;
+    }
+  }
+  else
+  {
+    if ((usartdiv & 0xFFFFU) != 0U)
+    {
+      brrresult = periphclkpresc / usartdiv;
+    }
+  }
+  return (brrresult);
+}
+
+/**
+  * @brief  Set Receiver Time Out Value (expressed in nb of bits duration)
+  * @rmtoll RTOR         RTO           LL_USART_SetRxTimeout
+  * @param  USARTx USART Instance
+  * @param  Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout)
+{
+  MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout);
+}
+
+/**
+  * @brief  Get Receiver Time Out Value (expressed in nb of bits duration)
+  * @rmtoll RTOR         RTO           LL_USART_GetRxTimeout
+  * @param  USARTx USART Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
+  */
+__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO));
+}
+
+/**
+  * @brief  Set Block Length value in reception
+  * @rmtoll RTOR         BLEN          LL_USART_SetBlockLength
+  * @param  USARTx USART Instance
+  * @param  BlockLength Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength)
+{
+  MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos);
+}
+
+/**
+  * @brief  Get Block Length value in reception
+  * @rmtoll RTOR         BLEN          LL_USART_GetBlockLength
+  * @param  USARTx USART Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_USART_GetBlockLength(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature
+  * @{
+  */
+
+/**
+  * @brief  Enable IrDA mode
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IREN          LL_USART_EnableIrda
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+  * @brief  Disable IrDA mode
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IREN          LL_USART_DisableIrda
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+  * @brief  Indicate if IrDA mode is enabled
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IREN          LL_USART_IsEnabledIrda
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure IrDA Power Mode (Normal or Low Power)
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IRLP          LL_USART_SetIrdaPowerMode
+  * @param  USARTx USART Instance
+  * @param  PowerMode This parameter can be one of the following values:
+  *         @arg @ref LL_USART_IRDA_POWER_NORMAL
+  *         @arg @ref LL_USART_IRDA_POWER_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);
+}
+
+/**
+  * @brief  Retrieve IrDA Power Mode configuration (Normal or Low Power)
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IRLP          LL_USART_GetIrdaPowerMode
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_IRDA_POWER_NORMAL
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  */
+__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
+}
+
+/**
+  * @brief  Set Irda prescaler value, used for dividing the USART clock source
+  *         to achieve the Irda Low Power frequency (8 bits value)
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_SetIrdaPrescaler
+  * @param  USARTx USART Instance
+  * @param  PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+{
+  MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)PrescalerValue);
+}
+
+/**
+  * @brief  Return Irda prescaler value, used for dividing the USART clock source
+  *         to achieve the Irda Low Power frequency (8 bits value)
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_GetIrdaPrescaler
+  * @param  USARTx USART Instance
+  * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature
+  * @{
+  */
+
+/**
+  * @brief  Enable Smartcard NACK transmission
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          NACK          LL_USART_EnableSmartcardNACK
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_NACK);
+}
+
+/**
+  * @brief  Disable Smartcard NACK transmission
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          NACK          LL_USART_DisableSmartcardNACK
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);
+}
+
+/**
+  * @brief  Indicate if Smartcard NACK transmission is enabled
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          NACK          LL_USART_IsEnabledSmartcardNACK
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Smartcard mode
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCEN          LL_USART_EnableSmartcard
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+  * @brief  Disable Smartcard mode
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCEN          LL_USART_DisableSmartcard
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+  * @brief  Indicate if Smartcard mode is enabled
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCEN          LL_USART_IsEnabledSmartcard
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @note   This bit-field specifies the number of retries in transmit and receive, in Smartcard mode.
+  *         In transmission mode, it specifies the number of automatic retransmission retries, before
+  *         generating a transmission error (FE bit set).
+  *         In reception mode, it specifies the number or erroneous reception trials, before generating a
+  *         reception error (RXNE and PE bits set)
+  * @rmtoll CR3          SCARCNT       LL_USART_SetSmartcardAutoRetryCount
+  * @param  USARTx USART Instance
+  * @param  AutoRetryCount Value between Min_Data=0 and Max_Data=7
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos);
+}
+
+/**
+  * @brief  Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCARCNT       LL_USART_GetSmartcardAutoRetryCount
+  * @param  USARTx USART Instance
+  * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos);
+}
+
+/**
+  * @brief  Set Smartcard prescaler value, used for dividing the USART clock
+  *         source to provide the SMARTCARD Clock (5 bits value)
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_SetSmartcardPrescaler
+  * @param  USARTx USART Instance
+  * @param  PrescalerValue Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+{
+  MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)PrescalerValue);
+}
+
+/**
+  * @brief  Return Smartcard prescaler value, used for dividing the USART clock
+  *         source to provide the SMARTCARD Clock (5 bits value)
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_GetSmartcardPrescaler
+  * @param  USARTx USART Instance
+  * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
+}
+
+/**
+  * @brief  Set Smartcard Guard time value, expressed in nb of baud clocks periods
+  *         (GT[7:0] bits : Guard time value)
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         GT            LL_USART_SetSmartcardGuardTime
+  * @param  USARTx USART Instance
+  * @param  GuardTime Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
+{
+  MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos));
+}
+
+/**
+  * @brief  Return Smartcard Guard time value, expressed in nb of baud clocks periods
+  *         (GT[7:0] bits : Guard time value)
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         GT            LL_USART_GetSmartcardGuardTime
+  * @param  USARTx USART Instance
+  * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
+  * @{
+  */
+
+/**
+  * @brief  Enable Single Wire Half-Duplex mode
+  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @rmtoll CR3          HDSEL         LL_USART_EnableHalfDuplex
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Disable Single Wire Half-Duplex mode
+  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @rmtoll CR3          HDSEL         LL_USART_DisableHalfDuplex
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Indicate if Single Wire Half-Duplex mode is enabled
+  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @rmtoll CR3          HDSEL         LL_USART_IsEnabledHalfDuplex
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_SPI_SLAVE Configuration functions related to SPI Slave feature
+  * @{
+  */
+/**
+  * @brief  Enable SPI Synchronous Slave mode
+  * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @rmtoll CR2          SLVEN         LL_USART_EnableSPISlave
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSPISlave(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_SLVEN);
+}
+
+/**
+  * @brief  Disable SPI Synchronous Slave mode
+  * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @rmtoll CR2          SLVEN         LL_USART_DisableSPISlave
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_SLVEN);
+}
+
+/**
+  * @brief  Indicate if  SPI Synchronous Slave mode is enabled
+  * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @rmtoll CR2          SLVEN         LL_USART_IsEnabledSPISlave
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_SLVEN) == (USART_CR2_SLVEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable SPI Slave Selection using NSS input pin
+  * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @note   SPI Slave Selection depends on NSS input pin
+  *         (The slave is selected when NSS is low and deselected when NSS is high).
+  * @rmtoll CR2          DIS_NSS       LL_USART_EnableSPISlaveSelect
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSPISlaveSelect(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_DIS_NSS);
+}
+
+/**
+  * @brief  Disable SPI Slave Selection using NSS input pin
+  * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @note   SPI Slave will be always selected and NSS input pin will be ignored.
+  * @rmtoll CR2          DIS_NSS       LL_USART_DisableSPISlaveSelect
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_DIS_NSS);
+}
+
+/**
+  * @brief  Indicate if  SPI Slave Selection depends on NSS input pin
+  * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @rmtoll CR2          DIS_NSS       LL_USART_IsEnabledSPISlaveSelect
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_DIS_NSS) != (USART_CR2_DIS_NSS)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature
+  * @{
+  */
+
+/**
+  * @brief  Set LIN Break Detection Length
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDL          LL_USART_SetLINBrkDetectionLen
+  * @param  USARTx USART Instance
+  * @param  LINBDLength This parameter can be one of the following values:
+  *         @arg @ref LL_USART_LINBREAK_DETECT_10B
+  *         @arg @ref LL_USART_LINBREAK_DETECT_11B
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);
+}
+
+/**
+  * @brief  Return LIN Break Detection Length
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDL          LL_USART_GetLINBrkDetectionLen
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_LINBREAK_DETECT_10B
+  *         @arg @ref LL_USART_LINBREAK_DETECT_11B
+  */
+__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
+}
+
+/**
+  * @brief  Enable LIN mode
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LINEN         LL_USART_EnableLIN
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+  * @brief  Disable LIN mode
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LINEN         LL_USART_DisableLIN
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+  * @brief  Indicate if LIN mode is enabled
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LINEN         LL_USART_IsEnabledLIN
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
+  * @{
+  */
+
+/**
+  * @brief  Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR1          DEDT          LL_USART_SetDEDeassertionTime
+  * @param  USARTx USART Instance
+  * @param  Time Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
+}
+
+/**
+  * @brief  Return DEDT (Driver Enable De-Assertion Time)
+  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR1          DEDT          LL_USART_GetDEDeassertionTime
+  * @param  USARTx USART Instance
+  * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
+  */
+__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
+}
+
+/**
+  * @brief  Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR1          DEAT          LL_USART_SetDEAssertionTime
+  * @param  USARTx USART Instance
+  * @param  Time Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
+}
+
+/**
+  * @brief  Return DEAT (Driver Enable Assertion Time)
+  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR1          DEAT          LL_USART_GetDEAssertionTime
+  * @param  USARTx USART Instance
+  * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
+  */
+__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
+}
+
+/**
+  * @brief  Enable Driver Enable (DE) Mode
+  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEM           LL_USART_EnableDEMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+  * @brief  Disable Driver Enable (DE) Mode
+  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEM           LL_USART_DisableDEMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+  * @brief  Indicate if Driver Enable (DE) Mode is enabled
+  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEM           LL_USART_IsEnabledDEMode
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Select Driver Enable Polarity
+  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEP           LL_USART_SetDESignalPolarity
+  * @param  USARTx USART Instance
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DE_POLARITY_HIGH
+  *         @arg @ref LL_USART_DE_POLARITY_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity);
+}
+
+/**
+  * @brief  Return Driver Enable Polarity
+  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEP           LL_USART_GetDESignalPolarity
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_DE_POLARITY_HIGH
+  *         @arg @ref LL_USART_DE_POLARITY_LOW
+  */
+__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services
+  * @{
+  */
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
+  * @note   In UART mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - CLKEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  * @note   Other remaining configurations items related to Asynchronous Mode
+  *         (as Baud Rate, Word length, Parity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigAsyncMode\n
+  *         CR2          CLKEN         LL_USART_ConfigAsyncMode\n
+  *         CR3          SCEN          LL_USART_ConfigAsyncMode\n
+  *         CR3          IREN          LL_USART_ConfigAsyncMode\n
+  *         CR3          HDSEL         LL_USART_ConfigAsyncMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
+{
+  /* In Asynchronous mode, the following bits must be kept cleared:
+  - LINEN, CLKEN bits in the USART_CR2 register,
+  - SCEN, IREN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Synchronous Mode
+  * @note   In Synchronous mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also sets the USART in Synchronous mode.
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
+  * @note   Other remaining configurations items related to Synchronous Mode
+  *         (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigSyncMode\n
+  *         CR2          CLKEN         LL_USART_ConfigSyncMode\n
+  *         CR3          SCEN          LL_USART_ConfigSyncMode\n
+  *         CR3          IREN          LL_USART_ConfigSyncMode\n
+  *         CR3          HDSEL         LL_USART_ConfigSyncMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
+{
+  /* In Synchronous mode, the following bits must be kept cleared:
+  - LINEN bit in the USART_CR2 register,
+  - SCEN, IREN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
+  /* set the UART/USART in Synchronous mode */
+  SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in LIN Mode
+  * @note   In LIN mode, the following bits must be kept cleared:
+  *           - STOP and CLKEN bits in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also set the UART/USART in LIN mode.
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function
+  * @note   Other remaining configurations items related to LIN Mode
+  *         (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          CLKEN         LL_USART_ConfigLINMode\n
+  *         CR2          STOP          LL_USART_ConfigLINMode\n
+  *         CR2          LINEN         LL_USART_ConfigLINMode\n
+  *         CR3          IREN          LL_USART_ConfigLINMode\n
+  *         CR3          SCEN          LL_USART_ConfigLINMode\n
+  *         CR3          HDSEL         LL_USART_ConfigLINMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
+{
+  /* In LIN mode, the following bits must be kept cleared:
+  - STOP and CLKEN bits in the USART_CR2 register,
+  - IREN, SCEN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
+  /* Set the UART/USART in LIN mode */
+  SET_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Half Duplex Mode
+  * @note   In Half Duplex mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - CLKEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *         This function also sets the UART/USART in Half Duplex mode.
+  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function
+  * @note   Other remaining configurations items related to Half Duplex Mode
+  *         (as Baud Rate, Word length, Parity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigHalfDuplexMode\n
+  *         CR2          CLKEN         LL_USART_ConfigHalfDuplexMode\n
+  *         CR3          HDSEL         LL_USART_ConfigHalfDuplexMode\n
+  *         CR3          SCEN          LL_USART_ConfigHalfDuplexMode\n
+  *         CR3          IREN          LL_USART_ConfigHalfDuplexMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
+{
+  /* In Half Duplex mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - SCEN and IREN bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
+  /* set the UART/USART in Half Duplex mode */
+  SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Smartcard Mode
+  * @note   In Smartcard mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also configures Stop bits to 1.5 bits and
+  *         sets the USART in Smartcard mode (SCEN bit).
+  *         Clock Output is also enabled (CLKEN).
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+  *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
+  *         - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function
+  * @note   Other remaining configurations items related to Smartcard Mode
+  *         (as Baud Rate, Word length, Parity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigSmartcardMode\n
+  *         CR2          STOP          LL_USART_ConfigSmartcardMode\n
+  *         CR2          CLKEN         LL_USART_ConfigSmartcardMode\n
+  *         CR3          HDSEL         LL_USART_ConfigSmartcardMode\n
+  *         CR3          SCEN          LL_USART_ConfigSmartcardMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
+{
+  /* In Smartcard mode, the following bits must be kept cleared:
+  - LINEN bit in the USART_CR2 register,
+  - IREN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
+  /* Configure Stop bits to 1.5 bits */
+  /* Synchronous mode is activated by default */
+  SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));
+  /* set the UART/USART in Smartcard mode */
+  SET_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Irda Mode
+  * @note   In IRDA mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - STOP and CLKEN bits in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also sets the UART/USART in IRDA mode (IREN bit).
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+  *         - Set IREN in CR3 using @ref LL_USART_EnableIrda() function
+  * @note   Other remaining configurations items related to Irda Mode
+  *         (as Baud Rate, Word length, Power mode, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigIrdaMode\n
+  *         CR2          CLKEN         LL_USART_ConfigIrdaMode\n
+  *         CR2          STOP          LL_USART_ConfigIrdaMode\n
+  *         CR3          SCEN          LL_USART_ConfigIrdaMode\n
+  *         CR3          HDSEL         LL_USART_ConfigIrdaMode\n
+  *         CR3          IREN          LL_USART_ConfigIrdaMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)
+{
+  /* In IRDA mode, the following bits must be kept cleared:
+  - LINEN, STOP and CLKEN bits in the USART_CR2 register,
+  - SCEN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
+  /* set the UART/USART in IRDA mode */
+  SET_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Multi processor Mode
+  *         (several USARTs connected in a network, one of the USARTs can be the master,
+  *         its TX output connected to the RX inputs of the other slaves USARTs).
+  * @note   In MultiProcessor mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - CLKEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  * @note   Other remaining configurations items related to Multi processor Mode
+  *         (as Baud Rate, Wake Up Method, Node address, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigMultiProcessMode\n
+  *         CR2          CLKEN         LL_USART_ConfigMultiProcessMode\n
+  *         CR3          SCEN          LL_USART_ConfigMultiProcessMode\n
+  *         CR3          HDSEL         LL_USART_ConfigMultiProcessMode\n
+  *         CR3          IREN          LL_USART_ConfigMultiProcessMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
+{
+  /* In Multi Processor mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - IREN, SCEN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Check if the USART Parity Error Flag is set or not
+  * @rmtoll ISR          PE            LL_USART_IsActiveFlag_PE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Framing Error Flag is set or not
+  * @rmtoll ISR          FE            LL_USART_IsActiveFlag_FE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Noise error detected Flag is set or not
+  * @rmtoll ISR          NE            LL_USART_IsActiveFlag_NE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART OverRun Error Flag is set or not
+  * @rmtoll ISR          ORE           LL_USART_IsActiveFlag_ORE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART IDLE line detected Flag is set or not
+  * @rmtoll ISR          IDLE          LL_USART_IsActiveFlag_IDLE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
+}
+
+/* Legacy define */
+#define LL_USART_IsActiveFlag_RXNE  LL_USART_IsActiveFlag_RXNE_RXFNE
+
+/**
+  * @brief  Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          RXNE_RXFNE    LL_USART_IsActiveFlag_RXNE_RXFNE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Transmission Complete Flag is set or not
+  * @rmtoll ISR          TC            LL_USART_IsActiveFlag_TC
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
+}
+
+/* Legacy define */
+#define LL_USART_IsActiveFlag_TXE  LL_USART_IsActiveFlag_TXE_TXFNF
+
+/**
+  * @brief  Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          TXE_TXFNF     LL_USART_IsActiveFlag_TXE_TXFNF
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART LIN Break Detection Flag is set or not
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll ISR          LBDF          LL_USART_IsActiveFlag_LBD
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART CTS interrupt Flag is set or not
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll ISR          CTSIF         LL_USART_IsActiveFlag_nCTS
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART CTS Flag is set or not
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll ISR          CTS           LL_USART_IsActiveFlag_CTS
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Receiver Time Out Flag is set or not
+  * @rmtoll ISR          RTOF          LL_USART_IsActiveFlag_RTO
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART End Of Block Flag is set or not
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll ISR          EOBF          LL_USART_IsActiveFlag_EOB
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the SPI Slave Underrun error flag is set or not
+  * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          UDR           LL_USART_IsActiveFlag_UDR
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Auto-Baud Rate Error Flag is set or not
+  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll ISR          ABRE          LL_USART_IsActiveFlag_ABRE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Auto-Baud Rate Flag is set or not
+  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll ISR          ABRF          LL_USART_IsActiveFlag_ABR
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Busy Flag is set or not
+  * @rmtoll ISR          BUSY          LL_USART_IsActiveFlag_BUSY
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Character Match Flag is set or not
+  * @rmtoll ISR          CMF           LL_USART_IsActiveFlag_CM
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Send Break Flag is set or not
+  * @rmtoll ISR          SBKF          LL_USART_IsActiveFlag_SBK
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Receive Wake Up from mute mode Flag is set or not
+  * @rmtoll ISR          RWU           LL_USART_IsActiveFlag_RWU
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Wake Up from stop mode Flag is set or not
+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          WUF           LL_USART_IsActiveFlag_WKUP
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Transmit Enable Acknowledge Flag is set or not
+  * @rmtoll ISR          TEACK         LL_USART_IsActiveFlag_TEACK
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Receive Enable Acknowledge Flag is set or not
+  * @rmtoll ISR          REACK         LL_USART_IsActiveFlag_REACK
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART TX FIFO Empty Flag is set or not
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          TXFE          LL_USART_IsActiveFlag_TXFE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART RX FIFO Full Flag is set or not
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          RXFF          LL_USART_IsActiveFlag_RXFF
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not
+  * @rmtoll ISR          TCBGT         LL_USART_IsActiveFlag_TCBGT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART TX FIFO Threshold Flag is set or not
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          TXFT          LL_USART_IsActiveFlag_TXFT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART RX FIFO Threshold Flag is set or not
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          RXFT          LL_USART_IsActiveFlag_RXFT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear Parity Error Flag
+  * @rmtoll ICR          PECF          LL_USART_ClearFlag_PE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_PECF);
+}
+
+/**
+  * @brief  Clear Framing Error Flag
+  * @rmtoll ICR          FECF          LL_USART_ClearFlag_FE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_FECF);
+}
+
+/**
+  * @brief  Clear Noise Error detected Flag
+  * @rmtoll ICR          NECF          LL_USART_ClearFlag_NE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_NECF);
+}
+
+/**
+  * @brief  Clear OverRun Error Flag
+  * @rmtoll ICR          ORECF         LL_USART_ClearFlag_ORE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_ORECF);
+}
+
+/**
+  * @brief  Clear IDLE line detected Flag
+  * @rmtoll ICR          IDLECF        LL_USART_ClearFlag_IDLE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_IDLECF);
+}
+
+/**
+  * @brief  Clear TX FIFO Empty Flag
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ICR          TXFECF        LL_USART_ClearFlag_TXFE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_TXFE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_TXFECF);
+}
+
+/**
+  * @brief  Clear Transmission Complete Flag
+  * @rmtoll ICR          TCCF          LL_USART_ClearFlag_TC
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_TCCF);
+}
+
+/**
+  * @brief  Clear Smartcard Transmission Complete Before Guard Time Flag
+  * @rmtoll ICR          TCBGTCF       LL_USART_ClearFlag_TCBGT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF);
+}
+
+/**
+  * @brief  Clear LIN Break Detection Flag
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll ICR          LBDCF         LL_USART_ClearFlag_LBD
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_LBDCF);
+}
+
+/**
+  * @brief  Clear CTS Interrupt Flag
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll ICR          CTSCF         LL_USART_ClearFlag_nCTS
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_CTSCF);
+}
+
+/**
+  * @brief  Clear Receiver Time Out Flag
+  * @rmtoll ICR          RTOCF         LL_USART_ClearFlag_RTO
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_RTOCF);
+}
+
+/**
+  * @brief  Clear End Of Block Flag
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll ICR          EOBCF         LL_USART_ClearFlag_EOB
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_EOBCF);
+}
+
+/**
+  * @brief  Clear SPI Slave Underrun Flag
+  * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @rmtoll ICR          UDRCF         LL_USART_ClearFlag_UDR
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_UDR(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_UDRCF);
+}
+
+/**
+  * @brief  Clear Character Match Flag
+  * @rmtoll ICR          CMCF          LL_USART_ClearFlag_CM
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_CMCF);
+}
+
+/**
+  * @brief  Clear Wake Up from stop mode Flag
+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll ICR          WUCF          LL_USART_ClearFlag_WKUP
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_WUCF);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable IDLE Interrupt
+  * @rmtoll CR1          IDLEIE        LL_USART_EnableIT_IDLE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+}
+
+/* Legacy define */
+#define LL_USART_EnableIT_RXNE  LL_USART_EnableIT_RXNE_RXFNE
+
+/**
+  * @brief  Enable RX Not Empty and RX FIFO Not Empty Interrupt
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_EnableIT_RXNE_RXFNE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+}
+
+/**
+  * @brief  Enable Transmission Complete Interrupt
+  * @rmtoll CR1          TCIE          LL_USART_EnableIT_TC
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_TCIE);
+}
+
+/* Legacy define */
+#define LL_USART_EnableIT_TXE  LL_USART_EnableIT_TXE_TXFNF
+
+/**
+  * @brief  Enable TX Empty and TX FIFO Not Full Interrupt
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1         TXEIE_TXFNFIE  LL_USART_EnableIT_TXE_TXFNF
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+}
+
+/**
+  * @brief  Enable Parity Error Interrupt
+  * @rmtoll CR1          PEIE          LL_USART_EnableIT_PE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+  * @brief  Enable Character Match Interrupt
+  * @rmtoll CR1          CMIE          LL_USART_EnableIT_CM
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+  * @brief  Enable Receiver Timeout Interrupt
+  * @rmtoll CR1          RTOIE         LL_USART_EnableIT_RTO
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_RTOIE);
+}
+
+/**
+  * @brief  Enable End Of Block Interrupt
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR1          EOBIE         LL_USART_EnableIT_EOB
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_EOBIE);
+}
+
+/**
+  * @brief  Enable TX FIFO Empty Interrupt
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          TXFEIE        LL_USART_EnableIT_TXFE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TXFE(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_TXFEIE);
+}
+
+/**
+  * @brief  Enable RX FIFO Full Interrupt
+  * @rmtoll CR1          RXFFIE        LL_USART_EnableIT_RXFF
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_RXFF(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_RXFFIE);
+}
+
+/**
+  * @brief  Enable LIN Break Detection Interrupt
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDIE         LL_USART_EnableIT_LBD
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_LBDIE);
+}
+
+/**
+  * @brief  Enable Error Interrupt
+  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
+  *           0: Interrupt is inhibited
+  *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
+  * @rmtoll CR3          EIE           LL_USART_EnableIT_ERROR
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+  * @brief  Enable CTS Interrupt
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSIE         LL_USART_EnableIT_CTS
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+  * @brief  Enable Wake Up from Stop Mode Interrupt
+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUFIE         LL_USART_EnableIT_WKUP
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_WUFIE);
+}
+
+/**
+  * @brief  Enable TX FIFO Threshold Interrupt
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          TXFTIE        LL_USART_EnableIT_TXFT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_TXFTIE);
+}
+
+/**
+  * @brief  Enable Smartcard Transmission Complete Before Guard Time Interrupt
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          TCBGTIE       LL_USART_EnableIT_TCBGT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
+}
+
+/**
+  * @brief  Enable RX FIFO Threshold Interrupt
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          RXFTIE        LL_USART_EnableIT_RXFT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_RXFT(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_RXFTIE);
+}
+
+/**
+  * @brief  Disable IDLE Interrupt
+  * @rmtoll CR1          IDLEIE        LL_USART_DisableIT_IDLE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+}
+
+/* Legacy define */
+#define LL_USART_DisableIT_RXNE  LL_USART_DisableIT_RXNE_RXFNE
+
+/**
+  * @brief  Disable RX Not Empty and RX FIFO Not Empty Interrupt
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_DisableIT_RXNE_RXFNE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+}
+
+/**
+  * @brief  Disable Transmission Complete Interrupt
+  * @rmtoll CR1          TCIE          LL_USART_DisableIT_TC
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
+}
+
+/* Legacy define */
+#define LL_USART_DisableIT_TXE  LL_USART_DisableIT_TXE_TXFNF
+
+/**
+  * @brief  Disable TX Empty and TX FIFO Not Full Interrupt
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1        TXEIE_TXFNFIE  LL_USART_DisableIT_TXE_TXFNF
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+}
+
+/**
+  * @brief  Disable Parity Error Interrupt
+  * @rmtoll CR1          PEIE          LL_USART_DisableIT_PE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+  * @brief  Disable Character Match Interrupt
+  * @rmtoll CR1          CMIE          LL_USART_DisableIT_CM
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+  * @brief  Disable Receiver Timeout Interrupt
+  * @rmtoll CR1          RTOIE         LL_USART_DisableIT_RTO
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE);
+}
+
+/**
+  * @brief  Disable End Of Block Interrupt
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR1          EOBIE         LL_USART_DisableIT_EOB
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE);
+}
+
+/**
+  * @brief  Disable TX FIFO Empty Interrupt
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          TXFEIE        LL_USART_DisableIT_TXFE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TXFE(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_TXFEIE);
+}
+
+/**
+  * @brief  Disable RX FIFO Full Interrupt
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          RXFFIE        LL_USART_DisableIT_RXFF
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_RXFF(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_RXFFIE);
+}
+
+/**
+  * @brief  Disable LIN Break Detection Interrupt
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDIE         LL_USART_DisableIT_LBD
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);
+}
+
+/**
+  * @brief  Disable Error Interrupt
+  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
+  *           0: Interrupt is inhibited
+  *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
+  * @rmtoll CR3          EIE           LL_USART_DisableIT_ERROR
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+  * @brief  Disable CTS Interrupt
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSIE         LL_USART_DisableIT_CTS
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+  * @brief  Disable Wake Up from Stop Mode Interrupt
+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUFIE         LL_USART_DisableIT_WKUP
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE);
+}
+
+/**
+  * @brief  Disable TX FIFO Threshold Interrupt
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          TXFTIE        LL_USART_DisableIT_TXFT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_TXFTIE);
+}
+
+/**
+  * @brief  Disable Smartcard Transmission Complete Before Guard Time Interrupt
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          TCBGTIE       LL_USART_DisableIT_TCBGT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
+}
+
+/**
+  * @brief  Disable RX FIFO Threshold Interrupt
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          RXFTIE        LL_USART_DisableIT_RXFT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_RXFTIE);
+}
+
+/**
+  * @brief  Check if the USART IDLE Interrupt  source is enabled or disabled.
+  * @rmtoll CR1          IDLEIE        LL_USART_IsEnabledIT_IDLE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
+}
+
+/* Legacy define */
+#define LL_USART_IsEnabledIT_RXNE  LL_USART_IsEnabledIT_RXNE_RXFNE
+
+/**
+  * @brief  Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled.
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_IsEnabledIT_RXNE_RXFNE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Transmission Complete Interrupt is enabled or disabled.
+  * @rmtoll CR1          TCIE          LL_USART_IsEnabledIT_TC
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
+}
+
+/* Legacy define */
+#define LL_USART_IsEnabledIT_TXE  LL_USART_IsEnabledIT_TXE_TXFNF
+
+/**
+  * @brief  Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1         TXEIE_TXFNFIE  LL_USART_IsEnabledIT_TXE_TXFNF
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Parity Error Interrupt is enabled or disabled.
+  * @rmtoll CR1          PEIE          LL_USART_IsEnabledIT_PE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Character Match Interrupt is enabled or disabled.
+  * @rmtoll CR1          CMIE          LL_USART_IsEnabledIT_CM
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Receiver Timeout Interrupt is enabled or disabled.
+  * @rmtoll CR1          RTOIE         LL_USART_IsEnabledIT_RTO
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART End Of Block Interrupt is enabled or disabled.
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR1          EOBIE         LL_USART_IsEnabledIT_EOB
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART TX FIFO Empty Interrupt is enabled or disabled
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          TXFEIE        LL_USART_IsEnabledIT_TXFE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART RX FIFO Full Interrupt is enabled or disabled
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          RXFFIE        LL_USART_IsEnabledIT_RXFF
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART LIN Break Detection Interrupt is enabled or disabled.
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDIE         LL_USART_IsEnabledIT_LBD
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Error Interrupt is enabled or disabled.
+  * @rmtoll CR3          EIE           LL_USART_IsEnabledIT_ERROR
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART CTS Interrupt is enabled or disabled.
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSIE         LL_USART_IsEnabledIT_CTS
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.
+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUFIE         LL_USART_IsEnabledIT_WKUP
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if USART TX FIFO Threshold Interrupt is enabled or disabled
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          TXFTIE        LL_USART_IsEnabledIT_TXFT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled.
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          TCBGTIE       LL_USART_IsEnabledIT_TCBGT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if USART RX FIFO Threshold Interrupt is enabled or disabled
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          RXFTIE        LL_USART_IsEnabledIT_RXFT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_DMA_Management DMA_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable DMA Mode for reception
+  * @rmtoll CR3          DMAR          LL_USART_EnableDMAReq_RX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+  * @brief  Disable DMA Mode for reception
+  * @rmtoll CR3          DMAR          LL_USART_DisableDMAReq_RX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+  * @brief  Check if DMA Mode is enabled for reception
+  * @rmtoll CR3          DMAR          LL_USART_IsEnabledDMAReq_RX
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable DMA Mode for transmission
+  * @rmtoll CR3          DMAT          LL_USART_EnableDMAReq_TX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+  * @brief  Disable DMA Mode for transmission
+  * @rmtoll CR3          DMAT          LL_USART_DisableDMAReq_TX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+  * @brief  Check if DMA Mode is enabled for transmission
+  * @rmtoll CR3          DMAT          LL_USART_IsEnabledDMAReq_TX
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable DMA Disabling on Reception Error
+  * @rmtoll CR3          DDRE          LL_USART_EnableDMADeactOnRxErr
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+  * @brief  Disable DMA Disabling on Reception Error
+  * @rmtoll CR3          DDRE          LL_USART_DisableDMADeactOnRxErr
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+  * @brief  Indicate if DMA Disabling on Reception Error is disabled
+  * @rmtoll CR3          DDRE          LL_USART_IsEnabledDMADeactOnRxErr
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get the data register address used for DMA transfer
+  * @rmtoll RDR          RDR           LL_USART_DMA_GetRegAddr\n
+  * @rmtoll TDR          TDR           LL_USART_DMA_GetRegAddr
+  * @param  USARTx USART Instance
+  * @param  Direction This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT
+  *         @arg @ref LL_USART_DMA_REG_DATA_RECEIVE
+  * @retval Address of data register
+  */
+__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction)
+{
+  register uint32_t data_reg_addr;
+
+  if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT)
+  {
+    /* return address of TDR register */
+    data_reg_addr = (uint32_t) &(USARTx->TDR);
+  }
+  else
+  {
+    /* return address of RDR register */
+    data_reg_addr = (uint32_t) &(USARTx->RDR);
+  }
+
+  return data_reg_addr;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Data_Management Data_Management
+  * @{
+  */
+
+/**
+  * @brief  Read Receiver Data register (Receive Data value, 8 bits)
+  * @rmtoll RDR          RDR           LL_USART_ReceiveData8
+  * @param  USARTx USART Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)
+{
+  return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU);
+}
+
+/**
+  * @brief  Read Receiver Data register (Receive Data value, 9 bits)
+  * @rmtoll RDR          RDR           LL_USART_ReceiveData9
+  * @param  USARTx USART Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x1FF
+  */
+__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx)
+{
+  return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
+}
+
+/**
+  * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)
+  * @rmtoll TDR          TDR           LL_USART_TransmitData8
+  * @param  USARTx USART Instance
+  * @param  Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value)
+{
+  USARTx->TDR = Value;
+}
+
+/**
+  * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)
+  * @rmtoll TDR          TDR           LL_USART_TransmitData9
+  * @param  USARTx USART Instance
+  * @param  Value between Min_Data=0x00 and Max_Data=0x1FF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)
+{
+  USARTx->TDR = (uint16_t)(Value & 0x1FFUL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Execution Execution
+  * @{
+  */
+
+/**
+  * @brief  Request an Automatic Baud Rate measurement on next received data frame
+  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll RQR          ABRRQ         LL_USART_RequestAutoBaudRate
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_ABRRQ);
+}
+
+/**
+  * @brief  Request Break sending
+  * @rmtoll RQR          SBKRQ         LL_USART_RequestBreakSending
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
+}
+
+/**
+  * @brief  Put USART in mute mode and set the RWU flag
+  * @rmtoll RQR          MMRQ          LL_USART_RequestEnterMuteMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_MMRQ);
+}
+
+/**
+  * @brief  Request a Receive Data and FIFO flush
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @note   Allows to discard the received data without reading them, and avoid an overrun
+  *         condition.
+  * @rmtoll RQR          RXFRQ         LL_USART_RequestRxDataFlush
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
+}
+
+/**
+  * @brief  Request a Transmit data and FIFO flush
+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll RQR          TXFRQ         LL_USART_RequestTxDataFlush
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_TXFRQ);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx);
+ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct);
+void        LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
+ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
+void        LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 || UART9 || USART10 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_LL_USART_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h
new file mode 100644
index 00000000..503b12f3
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h
@@ -0,0 +1,510 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_usb.h
+  * @author  MCD Application Team
+  * @brief   Header file of USB Low Layer HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_LL_USB_H
+#define STM32H7xx_LL_USB_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup USB_LL
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+  * @brief  USB Mode definition
+  */
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+
+typedef enum
+{
+  USB_DEVICE_MODE  = 0,
+  USB_HOST_MODE    = 1,
+  USB_DRD_MODE     = 2
+} USB_OTG_ModeTypeDef;
+
+/**
+  * @brief  URB States definition
+  */
+typedef enum
+{
+  URB_IDLE = 0,
+  URB_DONE,
+  URB_NOTREADY,
+  URB_NYET,
+  URB_ERROR,
+  URB_STALL
+} USB_OTG_URBStateTypeDef;
+
+/**
+  * @brief  Host channel States  definition
+  */
+typedef enum
+{
+  HC_IDLE = 0,
+  HC_XFRC,
+  HC_HALTED,
+  HC_NAK,
+  HC_NYET,
+  HC_STALL,
+  HC_XACTERR,
+  HC_BBLERR,
+  HC_DATATGLERR
+} USB_OTG_HCStateTypeDef;
+
+/**
+  * @brief  USB OTG Initialization Structure definition
+  */
+typedef struct
+{
+  uint32_t dev_endpoints;           /*!< Device Endpoints number.
+                                         This parameter depends on the used USB core.
+                                         This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+
+  uint32_t Host_channels;           /*!< Host Channels number.
+                                         This parameter Depends on the used USB core.
+                                         This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+
+  uint32_t speed;                   /*!< USB Core speed.
+                                         This parameter can be any value of @ref USB_Core_Speed_                */
+
+  uint32_t dma_enable;              /*!< Enable or disable of the USB embedded DMA used only for OTG HS.        */
+
+  uint32_t ep0_mps;                 /*!< Set the Endpoint 0 Max Packet size.                                    */
+
+  uint32_t phy_itface;              /*!< Select the used PHY interface.
+                                         This parameter can be any value of @ref USB_Core_PHY_                  */
+
+  uint32_t Sof_enable;              /*!< Enable or disable the output of the SOF signal.                        */
+
+  uint32_t low_power_enable;        /*!< Enable or disable the low power mode.                                  */
+
+  uint32_t lpm_enable;              /*!< Enable or disable Link Power Management.                               */
+
+  uint32_t battery_charging_enable; /*!< Enable or disable Battery charging.                                    */
+
+  uint32_t vbus_sensing_enable;     /*!< Enable or disable the VBUS Sensing feature.                            */
+
+  uint32_t use_dedicated_ep1;       /*!< Enable or disable the use of the dedicated EP1 interrupt.              */
+
+  uint32_t use_external_vbus;       /*!< Enable or disable the use of the external VBUS.                        */
+} USB_OTG_CfgTypeDef;
+
+typedef struct
+{
+  uint8_t   num;                  /*!< Endpoint number
+                                       This parameter must be a number between Min_Data = 1 and Max_Data = 15   */
+
+  uint8_t   is_in;                /*!< Endpoint direction
+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 1    */
+
+  uint8_t   is_stall;             /*!< Endpoint stall condition
+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 1    */
+
+  uint8_t   type;                 /*!< Endpoint type
+                                       This parameter can be any value of @ref USB_EP_Type_                     */
+
+  uint8_t   data_pid_start;       /*!< Initial data PID
+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 1    */
+
+  uint8_t   even_odd_frame;       /*!< IFrame parity
+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 1    */
+
+  uint16_t  tx_fifo_num;          /*!< Transmission FIFO number
+                                       This parameter must be a number between Min_Data = 1 and Max_Data = 15   */
+
+  uint32_t  maxpacket;            /*!< Endpoint Max packet size
+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
+
+  uint8_t   *xfer_buff;           /*!< Pointer to transfer buffer                                               */
+
+  uint32_t  dma_addr;             /*!< 32 bits aligned transfer buffer address                                  */
+
+  uint32_t  xfer_len;             /*!< Current transfer length                                                  */
+
+  uint32_t  xfer_count;           /*!< Partial transfer length in case of multi packet transfer                 */
+} USB_OTG_EPTypeDef;
+
+typedef struct
+{
+  uint8_t   dev_addr ;          /*!< USB device address.
+                                     This parameter must be a number between Min_Data = 1 and Max_Data = 255    */
+
+  uint8_t   ch_num;             /*!< Host channel number.
+                                     This parameter must be a number between Min_Data = 1 and Max_Data = 15     */
+
+  uint8_t   ep_num;             /*!< Endpoint number.
+                                     This parameter must be a number between Min_Data = 1 and Max_Data = 15     */
+
+  uint8_t   ep_is_in;           /*!< Endpoint direction
+                                     This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
+
+  uint8_t   speed;              /*!< USB Host speed.
+                                     This parameter can be any value of @ref USB_Core_Speed_                    */
+
+  uint8_t   do_ping;            /*!< Enable or disable the use of the PING protocol for HS mode.                */
+
+  uint8_t   process_ping;       /*!< Execute the PING protocol for HS mode.                                     */
+
+  uint8_t   ep_type;            /*!< Endpoint Type.
+                                     This parameter can be any value of @ref USB_EP_Type_                       */
+
+  uint16_t  max_packet;         /*!< Endpoint Max packet size.
+                                     This parameter must be a number between Min_Data = 0 and Max_Data = 64KB   */
+
+  uint8_t   data_pid;           /*!< Initial data PID.
+                                     This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
+
+  uint8_t   *xfer_buff;         /*!< Pointer to transfer buffer.                                                */
+
+  uint32_t  xfer_len;           /*!< Current transfer length.                                                   */
+
+  uint32_t  xfer_count;         /*!< Partial transfer length in case of multi packet transfer.                  */
+
+  uint8_t   toggle_in;          /*!< IN transfer current toggle flag.
+                                     This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
+
+  uint8_t   toggle_out;         /*!< OUT transfer current toggle flag
+                                     This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
+
+  uint32_t  dma_addr;           /*!< 32 bits aligned transfer buffer address.                                   */
+
+  uint32_t  ErrCnt;             /*!< Host channel error count.*/
+
+  USB_OTG_URBStateTypeDef  urb_state;  /*!< URB state.
+                                            This parameter can be any value of @ref USB_OTG_URBStateTypeDef */
+
+  USB_OTG_HCStateTypeDef   state;     /*!< Host Channel state.
+                                           This parameter can be any value of @ref USB_OTG_HCStateTypeDef   */
+} USB_OTG_HCTypeDef;
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PCD_Exported_Constants PCD Exported Constants
+  * @{
+  */
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+/** @defgroup USB_OTG_CORE VERSION ID
+  * @{
+  */
+#define USB_OTG_CORE_ID_300A          0x4F54300AU
+#define USB_OTG_CORE_ID_310A          0x4F54310AU
+/**
+  * @}
+  */
+
+/** @defgroup USB_Core_Mode_ USB Core Mode
+  * @{
+  */
+#define USB_OTG_MODE_DEVICE                    0U
+#define USB_OTG_MODE_HOST                      1U
+#define USB_OTG_MODE_DRD                       2U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL Device Speed
+  * @{
+  */
+#define USBD_HS_SPEED               0U
+#define USBD_HSINFS_SPEED           1U
+#define USBH_HS_SPEED               0U
+#define USBD_FS_SPEED               2U
+#define USBH_FS_SPEED               1U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed
+  * @{
+  */
+#define USB_OTG_SPEED_HIGH                     0U
+#define USB_OTG_SPEED_HIGH_IN_FULL             1U
+#define USB_OTG_SPEED_FULL                     3U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY
+  * @{
+  */
+#define USB_OTG_ULPI_PHY                       1U
+#define USB_OTG_EMBEDDED_PHY                   2U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_Turnaround_Timeout Turnaround Timeout Value
+  * @{
+  */
+#ifndef USBD_HS_TRDT_VALUE
+#define USBD_HS_TRDT_VALUE           9U
+#endif /* USBD_HS_TRDT_VALUE */
+#ifndef USBD_FS_TRDT_VALUE
+#define USBD_FS_TRDT_VALUE           5U
+#define USBD_DEFAULT_TRDT_VALUE      9U
+#endif /* USBD_HS_TRDT_VALUE */
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS
+  * @{
+  */
+#define USB_OTG_HS_MAX_PACKET_SIZE             512U
+#define USB_OTG_FS_MAX_PACKET_SIZE             64U
+#define USB_OTG_MAX_EP0_SIZE                   64U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency
+  * @{
+  */
+#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ     (0U << 1)
+#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ     (1U << 1)
+#define DSTS_ENUMSPD_FS_PHY_48MHZ              (3U << 1)
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval
+  * @{
+  */
+#define DCFG_FRAME_INTERVAL_80                 0U
+#define DCFG_FRAME_INTERVAL_85                 1U
+#define DCFG_FRAME_INTERVAL_90                 2U
+#define DCFG_FRAME_INTERVAL_95                 3U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
+  * @{
+  */
+#define DEP0CTL_MPS_64                         0U
+#define DEP0CTL_MPS_32                         1U
+#define DEP0CTL_MPS_16                         2U
+#define DEP0CTL_MPS_8                          3U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed
+  * @{
+  */
+#define EP_SPEED_LOW                           0U
+#define EP_SPEED_FULL                          1U
+#define EP_SPEED_HIGH                          2U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_EP_Type USB Low Layer EP Type
+  * @{
+  */
+#define EP_TYPE_CTRL                           0U
+#define EP_TYPE_ISOC                           1U
+#define EP_TYPE_BULK                           2U
+#define EP_TYPE_INTR                           3U
+#define EP_TYPE_MSK                            3U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines
+  * @{
+  */
+#define STS_GOUT_NAK                           1U
+#define STS_DATA_UPDT                          2U
+#define STS_XFER_COMP                          3U
+#define STS_SETUP_COMP                         4U
+#define STS_SETUP_UPDT                         6U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines
+  * @{
+  */
+#define HCFG_30_60_MHZ                         0U
+#define HCFG_48_MHZ                            1U
+#define HCFG_6_MHZ                             2U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines
+  * @{
+  */
+#define HPRT0_PRTSPD_HIGH_SPEED                0U
+#define HPRT0_PRTSPD_FULL_SPEED                1U
+#define HPRT0_PRTSPD_LOW_SPEED                 2U
+/**
+  * @}
+  */
+
+#define HCCHAR_CTRL                            0U
+#define HCCHAR_ISOC                            1U
+#define HCCHAR_BULK                            2U
+#define HCCHAR_INTR                            3U
+
+#define HC_PID_DATA0                           0U
+#define HC_PID_DATA2                           1U
+#define HC_PID_DATA1                           2U
+#define HC_PID_SETUP                           3U
+
+#define GRXSTS_PKTSTS_IN                       2U
+#define GRXSTS_PKTSTS_IN_XFER_COMP             3U
+#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR          5U
+#define GRXSTS_PKTSTS_CH_HALTED                7U
+
+#define USBx_PCGCCTL    *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE)
+#define USBx_HPRT0      *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE)
+
+#define USBx_DEVICE     ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE))
+#define USBx_INEP(i)    ((USB_OTG_INEndpointTypeDef *)(USBx_BASE + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
+#define USBx_OUTEP(i)   ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
+#define USBx_DFIFO(i)   *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE))
+
+#define USBx_HOST       ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE))
+#define USBx_HC(i)      ((USB_OTG_HostChannelTypeDef *)(USBx_BASE + USB_OTG_HOST_CHANNEL_BASE + ((i) * USB_OTG_HOST_CHANNEL_SIZE)))
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+#define EP_ADDR_MSK                            0xFU
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup USB_LL_Exported_Macros USB Low Layer Exported Macros
+  * @{
+  */
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__)     ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))
+#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__)   ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))
+
+#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__)          (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__))
+#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__)         (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions
+  * @{
+  */
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
+HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
+HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed);
+HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode);
+HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed);
+HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num);
+HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma);
+HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma);
+HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma);
+void             *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
+HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address);
+HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup);
+uint8_t           USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_GetMode(USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
+uint32_t          USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
+void              USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);
+
+HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
+HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq);
+HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state);
+uint32_t          USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
+                              uint8_t ch_num,
+                              uint8_t epnum,
+                              uint8_t dev_address,
+                              uint8_t speed,
+                              uint8_t ep_type,
+                              uint16_t mps);
+HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma);
+uint32_t          USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num);
+HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num);
+HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32H7xx_LL_USB_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_utils.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_utils.h
new file mode 100644
index 00000000..ca336c26
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_utils.h
@@ -0,0 +1,382 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_utils.h
+  * @author  MCD Application Team
+  * @brief   Header file of UTILS LL module.
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The LL UTILS driver contains a set of generic APIs that can be
+    used by user:
+      (+) Device electronic signature
+      (+) Timing functions
+      (+) PLL configuration functions
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_LL_UTILS_H
+#define STM32H7xx_LL_UTILS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+#include "stm32h7xx_ll_system.h"
+#include "stm32h7xx_ll_bus.h"
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+/** @defgroup UTILS_LL UTILS
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
+  * @{
+  */
+
+/* Max delay can be used in LL_mDelay */
+#define LL_MAX_DELAY                  0xFFFFFFFFU
+
+/**
+ * @brief Unique device ID register base address
+ */
+#define UID_BASE_ADDRESS              UID_BASE
+
+/**
+ * @brief Flash size data register base address
+ */
+#define FLASHSIZE_BASE_ADDRESS        FLASHSIZE_BASE
+
+/**
+ * @brief Package data register base address
+ */
+#define PACKAGE_BASE_ADDRESS          PACKAGE_BASE
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
+  * @{
+  */
+/**
+  * @brief  UTILS PLL structure definition
+  */
+typedef struct
+{
+  uint32_t PLLM;   /*!< Division factor for PLL VCO input clock.
+                        This parameter must be a number between Min_Data = 0 and Max_Data = 63
+
+                        This feature can be modified afterwards using unitary function
+                        @ref LL_RCC_PLL1_SetM(). */
+
+  uint32_t PLLN;   /*!< Multiplication factor for PLL VCO output clock.
+                        This parameter must be a number between Min_Data = 4 and Max_Data = 512
+
+                        This feature can be modified afterwards using unitary function
+                        @ref LL_RCC_PLL1_SetN(). */
+
+  uint32_t PLLP;   /*!< Division for the main system clock.
+                        This parameter must be a number between Min_Data = 2 and Max_Data = 128
+                          odd division factors are not allowed
+
+                        This feature can be modified afterwards using unitary function
+                        @ref LL_RCC_PLL1_SetP(). */
+
+  uint32_t FRACN;  /*!< Fractional part of the multiplication factor for PLL VCO.
+                        This parameter can be a value between 0 and 8191
+
+                        This feature can be modified afterwards using unitary function
+                        @ref LL_RCC_PLL1_SetFRACN(). */
+
+  uint32_t VCO_Input;  /*!< PLL clock Input range.
+                        This parameter can be a value of @ref RCC_LL_EC_PLLINPUTRANGE
+
+                        This feature can be modified afterwards using unitary function
+                        @ref LL_RCC_PLL1_SetVCOInputRange(). */
+
+  uint32_t VCO_Output;  /*!< PLL clock Output range.
+                        This parameter can be a value of @ref RCC_LL_EC_PLLVCORANGE
+
+                      This feature can be modified afterwards using unitary function
+                      @ref LL_RCC_PLL1_SetVCOOutputRange(). */
+
+} LL_UTILS_PLLInitTypeDef;
+
+/**
+  * @brief  UTILS System, AHB and APB buses clock configuration structure definition
+  */
+typedef struct
+{
+  uint32_t SYSCLKDivider;         /*!< The System clock (SYSCLK) divider. This clock is derived from the PLL output.
+                                     This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
+
+                                     This feature can be modified afterwards using unitary function
+                                     @ref LL_RCC_SetSysPrescaler(). */
+
+  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
+                                       This parameter can be a value of @ref RCC_LL_EC_AHB_DIV
+
+                                       This feature can be modified afterwards using unitary function
+                                       @ref LL_RCC_SetAHBPrescaler(). */
+
+  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
+
+                                       This feature can be modified afterwards using unitary function
+                                       @ref LL_RCC_SetAPB1Prescaler(). */
+
+  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
+
+                                       This feature can be modified afterwards using unitary function
+                                       @ref LL_RCC_SetAPB2Prescaler(). */
+
+  uint32_t APB3CLKDivider;        /*!< The APB2 clock (PCLK3) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_LL_EC_APB3_DIV
+
+                                       This feature can be modified afterwards using unitary function
+                                       @ref LL_RCC_SetAPB3Prescaler(). */
+
+  uint32_t APB4CLKDivider;        /*!< The APB4 clock (PCLK4) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_LL_EC_APB4_DIV
+
+                                       This feature can be modified afterwards using unitary function
+                                       @ref LL_RCC_SetAPB4Prescaler(). */
+
+} LL_UTILS_ClkInitTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
+  * @{
+  */
+
+/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
+  * @{
+  */
+#define LL_UTILS_HSEBYPASS_OFF        0x00000000U       /*!< HSE Bypass is not enabled                */
+#define LL_UTILS_HSEBYPASS_ON         0x00000001U       /*!< HSE Bypass is enabled                    */
+/**
+  * @}
+  */
+
+/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
+  * @{
+  */
+#if defined(SYSCFG_PKGR_PKG)
+#define LL_UTILS_PACKAGETYPE_LQFP100            LL_SYSCFG_LQFP100_PACKAGE          /*!< LQFP100 package type             */
+#define LL_UTILS_PACKAGETYPE_TQFP144            LL_SYSCFG_TQFP144_PACKAGE          /*!< TQFP144 package type             */
+#define LL_UTILS_PACKAGETYPE_TQFP176_UFBGA176   LL_SYSCFG_TQFP176_UFBGA176_PACKAGE /*!< TQFP176 or UFBGA176 package type */
+#define LL_UTILS_PACKAGETYPE_LQFP208_TFBGA240   LL_SYSCFG_LQFP208_TFBGA240_PACKAGE /*!< LQFP208 or TFBGA240 package type */
+#else
+#define LL_UTILS_PACKAGETYPE_LQFP64                  0x00000000UL                  /*!< LQFP64 package type              */
+#define LL_UTILS_PACKAGETYPE_TFBGA100_LQFP100        0x00000001UL                  /*!< TFBGA100 or LQFP100 package type */
+#define LL_UTILS_PACKAGETYPE_LQFP100_SMPS            0x00000002UL                  /*!< LQFP100  with SMPS package type  */
+#define LL_UTILS_PACKAGETYPE_TFBGA100_SMPS           0x00000003UL                  /*!< TFBGA100 with SMPS package type  */
+#define LL_UTILS_PACKAGETYPE_WLCSP132_SMPS           0x00000004UL                  /*!< WLCSP132 package type            */
+#define LL_UTILS_PACKAGETYPE_LQFP144                 0x00000005UL                  /*!< LQFP144 package type             */
+#define LL_UTILS_PACKAGETYPE_LQFP144_SMPS            0x00000006UL                  /*!< LQFP144 with SMPS package type   */
+#define LL_UTILS_PACKAGETYPE_UFBGA169                0x00000007UL                  /*!< UFBGA169 package type            */
+#define LL_UTILS_PACKAGETYPE_UFBGA176_LQFP176        0x00000008UL                  /*!< UFBGA176 or LQFP176 package type */
+#define LL_UTILS_PACKAGETYPE_LQFP176_SMPS            0x00000009UL                  /*!< LQFP176 with SMPS package type   */
+#define LL_UTILS_PACKAGETYPE_UFBGA176_SMPS           0x0000000AUL                  /*!< UFBGA176 with SMPS package type  */
+#define LL_UTILS_PACKAGETYPE_TFBGA216                0x0000000CUL                  /*!< TFBGA216  package type           */
+#define LL_UTILS_PACKAGETYPE_TFBGA225                0x0000000EUL                  /*!< TFBGA225  package type           */
+#endif /* SYSCFG_PKGR_PKG */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
+  * @{
+  */
+
+/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
+  * @{
+  */
+
+/**
+  * @brief  Get Word0 of the unique device identifier (UID based on 96 bits)
+  * @retval UID[31:0]
+  */
+__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
+{
+  return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
+}
+
+/**
+  * @brief  Get Word1 of the unique device identifier (UID based on 96 bits)
+  * @retval UID[63:32]
+  */
+__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
+{
+  return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
+}
+
+/**
+  * @brief  Get Word2 of the unique device identifier (UID based on 96 bits)
+  * @retval UID[95:64]
+  */
+__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
+{
+  return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
+}
+
+/**
+  * @brief  Get Flash memory size
+  * @note   This bitfield indicates the size of the device Flash memory expressed in
+  *         Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
+  * @retval FLASH_SIZE[15:0]: Flash memory size
+  */
+__STATIC_INLINE uint32_t LL_GetFlashSize(void)
+{
+  return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));
+}
+
+/**
+  * @brief  Get Package type
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP100
+  *         @arg @ref LL_UTILS_PACKAGETYPE_TQFP144
+  *         @arg @ref LL_UTILS_PACKAGETYPE_TQFP176_UFBGA176
+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP208_TFBGA240
+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP64 (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_TFBGA100_LQFP100  (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_SMPS  (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_TFBGA100_SMPS  (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_WLCSP132_SMPS  (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP144     (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_SMPS (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169  (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176_LQFP176  (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP176_SMPS    (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176_SMPS   (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_TFBGA216   (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_TFBGA225   (*)
+  *
+  *        (*) Packages available on some STM32H7 lines only.
+  * @note   For some SM32H7 lines, enabling the SYSCFG clock is mandatory.
+            the SYSCFG clock enabling is ensured by LL_APB4_GRP1_EnableClock
+  */
+__STATIC_INLINE uint32_t LL_GetPackageType(void)
+{
+#if defined(SYSCFG_PKGR_PKG)
+
+  return LL_SYSCFG_GetPackage();
+#else
+   return (uint16_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)));
+
+#endif  /* SYSCFG_PKGR_PKG */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UTILS_LL_EF_DELAY DELAY
+  * @{
+  */
+
+/**
+  * @brief  This function configures the Cortex-M SysTick source of the time base.
+  * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
+  * @note   When a RTOS is used, it is recommended to avoid changing the SysTick
+  *         configuration by calling this function, for a delay use rather osDelay RTOS service.
+  * @param  Ticks Number of ticks
+  * @retval None
+  */
+__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
+{
+  /* Configure the SysTick to have interrupt in 1ms time base */
+  SysTick->LOAD  = (uint32_t)((HCLKFrequency / Ticks) - 1UL);  /* set reload register */
+  SysTick->VAL   = 0UL;                                       /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_ENABLE_Msk;                   /* Enable the Systick Timer */
+}
+
+void        LL_Init1msTick(uint32_t CPU_Frequency);
+void        LL_mDelay(uint32_t Delay);
+
+/**
+  * @}
+  */
+
+/** @defgroup UTILS_EF_SYSTEM SYSTEM
+  * @{
+  */
+
+void        LL_SetSystemCoreClock(uint32_t CPU_Frequency);
+ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
+                                         LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency,
+                                         uint32_t HSEBypass,
+                                         LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
+                                         LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_LL_UTILS_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c
new file mode 100644
index 00000000..3e92312e
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c
@@ -0,0 +1,1276 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal.c
+  * @author  MCD Application Team
+  * @brief   HAL module driver.
+  *          This is the common part of the HAL initialization
+  *
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The common HAL driver contains a set of generic and common APIs that can be
+    used by the PPP peripheral drivers and the user to start using the HAL.
+    [..]
+    The HAL contains two APIs' categories:
+         (+) Common HAL APIs
+         (+) Services HAL APIs
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup HAL  HAL
+  * @brief HAL module driver.
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/**
+ * @brief STM32H7xx HAL Driver version number V1.8.0
+   */
+#define __STM32H7xx_HAL_VERSION_MAIN   (0x01UL) /*!< [31:24] main version */
+#define __STM32H7xx_HAL_VERSION_SUB1   (0x08UL) /*!< [23:16] sub1 version */
+#define __STM32H7xx_HAL_VERSION_SUB2   (0x00UL) /*!< [15:8]  sub2 version */
+#define __STM32H7xx_HAL_VERSION_RC     (0x00UL) /*!< [7:0]  release candidate */
+#define __STM32H7xx_HAL_VERSION         ((__STM32H7xx_HAL_VERSION_MAIN << 24)\
+                                        |(__STM32H7xx_HAL_VERSION_SUB1 << 16)\
+                                        |(__STM32H7xx_HAL_VERSION_SUB2 << 8 )\
+                                        |(__STM32H7xx_HAL_VERSION_RC))
+
+#define IDCODE_DEVID_MASK    ((uint32_t)0x00000FFF)
+#define VREFBUF_TIMEOUT_VALUE     (uint32_t)10   /* 10 ms  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Exported variables --------------------------------------------------------*/
+
+/** @defgroup HAL_Exported_Variables HAL Exported Variables
+  * @{
+  */
+__IO uint32_t uwTick;
+uint32_t uwTickPrio   = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
+HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT;  /* 1KHz */
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup HAL_Private_Functions  HAL Private Functions
+  * @{
+  */
+
+/** @defgroup HAL_Group1 Initialization and de-initialization Functions
+ *  @brief    Initialization and de-initialization functions
+ *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initializes the Flash interface the NVIC allocation and initial clock
+          configuration. It initializes the systick also when timeout is needed
+          and the backup domain when enabled.
+      (+) De-Initializes common part of the HAL.
+      (+) Configure The time base source to have 1ms time base with a dedicated
+          Tick interrupt priority.
+        (++) SysTick timer is used by default as source of time base, but user
+             can eventually implement his proper time base source (a general purpose
+             timer for example or other time source), keeping in mind that Time base
+             duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
+             handled in milliseconds basis.
+        (++) Time base configuration function (HAL_InitTick ()) is called automatically
+             at the beginning of the program after reset by HAL_Init() or at any time
+             when clock is configured, by HAL_RCC_ClockConfig().
+        (++) Source of time base is configured  to generate interrupts at regular
+             time intervals. Care must be taken if HAL_Delay() is called from a
+             peripheral ISR process, the Tick interrupt line must have higher priority
+            (numerically lower) than the peripheral interrupt. Otherwise the caller
+            ISR process will be blocked.
+       (++) functions affecting time base configurations are declared as __weak
+             to make  override possible  in case of other  implementations in user file.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function is used to initialize the HAL Library; it must be the first
+  *         instruction to be executed in the main program (before to call any other
+  *         HAL function), it performs the following:
+  *           Configures the SysTick to generate an interrupt each 1 millisecond,
+  *           which is clocked by the HSI (at this stage, the clock is not yet
+  *           configured and thus the system is running from the internal HSI at 16 MHz).
+  *           Set NVIC Group Priority to 4.
+  *           Calls the HAL_MspInit() callback function defined in user file
+  *           "stm32h7xx_hal_msp.c" to do the global low level hardware initialization
+  *
+  * @note   SysTick is used as time base for the HAL_Delay() function, the application
+  *         need to ensure that the SysTick time base is always set to 1 millisecond
+  *         to have correct HAL operation.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_Init(void)
+{
+
+uint32_t common_system_clock;
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+   /* Configure Cortex-M4 Instruction cache through ART accelerator */
+   __HAL_RCC_ART_CLK_ENABLE();                   /* Enable the Cortex-M4 ART Clock */
+   __HAL_ART_CONFIG_BASE_ADDRESS(0x08100000UL);  /* Configure the Cortex-M4 ART Base address to the Flash Bank 2 : */
+   __HAL_ART_ENABLE();                           /* Enable the Cortex-M4 ART */
+#endif /* DUAL_CORE &&  CORE_CM4 */
+
+  /* Set Interrupt Group Priority */
+  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+  /* Update the SystemCoreClock global variable */
+#if defined(RCC_D1CFGR_D1CPRE)
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
+#else
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
+#endif
+
+  /* Update the SystemD2Clock global variable */
+#if defined(RCC_D1CFGR_HPRE)
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+#else
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+#endif
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  SystemCoreClock = SystemD2Clock;
+#else
+  SystemCoreClock = common_system_clock;
+#endif /* DUAL_CORE && CORE_CM4 */
+
+  /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
+  if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Init the low level hardware */
+  HAL_MspInit();
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function de-Initializes common part of the HAL and stops the systick.
+  *         This function is optional.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DeInit(void)
+{
+  /* Reset of all peripherals */
+  __HAL_RCC_AHB3_FORCE_RESET();
+  __HAL_RCC_AHB3_RELEASE_RESET();
+
+  __HAL_RCC_AHB1_FORCE_RESET();
+  __HAL_RCC_AHB1_RELEASE_RESET();
+
+  __HAL_RCC_AHB2_FORCE_RESET();
+  __HAL_RCC_AHB2_RELEASE_RESET();
+
+  __HAL_RCC_AHB4_FORCE_RESET();
+ __HAL_RCC_AHB4_RELEASE_RESET();
+
+  __HAL_RCC_APB3_FORCE_RESET();
+  __HAL_RCC_APB3_RELEASE_RESET();
+
+  __HAL_RCC_APB1L_FORCE_RESET();
+  __HAL_RCC_APB1L_RELEASE_RESET();
+
+  __HAL_RCC_APB1H_FORCE_RESET();
+  __HAL_RCC_APB1H_RELEASE_RESET();
+
+   __HAL_RCC_APB2_FORCE_RESET();
+   __HAL_RCC_APB2_RELEASE_RESET();
+
+  __HAL_RCC_APB4_FORCE_RESET();
+  __HAL_RCC_APB4_RELEASE_RESET();
+
+  /* De-Init the low level hardware */
+  HAL_MspDeInit();
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the MSP.
+  * @retval None
+  */
+__weak void HAL_MspInit(void)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes the MSP.
+  * @retval None
+  */
+__weak void HAL_MspDeInit(void)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief This function configures the source of the time base.
+  *        The time source is configured  to have 1ms time base with a dedicated
+  *        Tick interrupt priority.
+  * @note This function is called  automatically at the beginning of program after
+  *       reset by HAL_Init() or at any time when clock is reconfigured  by HAL_RCC_ClockConfig().
+  * @note In the default implementation, SysTick timer is the source of time base.
+  *       It is used to generate interrupts at regular time intervals.
+  *       Care must be taken if HAL_Delay() is called from a peripheral ISR process,
+  *       The the SysTick interrupt must have higher priority (numerically lower)
+  *       than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+  *       The function is declared as __weak  to be overwritten  in case of other
+  *       implementation  in user file.
+  * @param TickPriority: Tick interrupt priority.
+  * @retval HAL status
+  */
+__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+  /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/
+  if((uint32_t)uwTickFreq == 0UL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Configure the SysTick to have interrupt in 1ms time basis*/
+  if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Configure the SysTick IRQ priority */
+  if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+  {
+    HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
+    uwTickPrio = TickPriority;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Group2 HAL Control functions
+ *  @brief    HAL Control functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### HAL Control functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Provide a tick value in millisecond
+      (+) Provide a blocking delay in millisecond
+      (+) Suspend the time base source interrupt
+      (+) Resume the time base source interrupt
+      (+) Get the HAL API driver version
+      (+) Get the device identifier
+      (+) Get the device revision identifier
+      (+) Enable/Disable Debug module during SLEEP mode
+      (+) Enable/Disable Debug module during STOP mode
+      (+) Enable/Disable Debug module during STANDBY mode
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief This function is called to increment  a global variable "uwTick"
+  *        used as application time base.
+  * @note In the default implementation, this variable is incremented each 1ms
+  *       in Systick ISR.
+ * @note This function is declared as __weak to be overwritten in case of other
+  *      implementations in user file.
+  * @retval None
+  */
+__weak void HAL_IncTick(void)
+{
+  uwTick += (uint32_t)uwTickFreq;
+}
+
+/**
+  * @brief Provides a tick value in millisecond.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @retval tick value
+  */
+__weak uint32_t HAL_GetTick(void)
+{
+  return uwTick;
+}
+
+/**
+  * @brief This function returns a tick priority.
+  * @retval tick priority
+  */
+uint32_t HAL_GetTickPrio(void)
+{
+  return uwTickPrio;
+}
+
+/**
+  * @brief Set new tick Freq.
+  * @retval Status
+  */
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
+{
+  HAL_StatusTypeDef status  = HAL_OK;
+  HAL_TickFreqTypeDef prevTickFreq;
+
+  assert_param(IS_TICKFREQ(Freq));
+
+  if (uwTickFreq != Freq)
+  {
+
+    /* Back up uwTickFreq frequency */
+    prevTickFreq = uwTickFreq;
+
+    /* Update uwTickFreq global variable used by HAL_InitTick() */
+    uwTickFreq = Freq;
+
+    /* Apply the new tick Freq  */
+    status = HAL_InitTick(uwTickPrio);
+    if (status != HAL_OK)
+    {
+      /* Restore previous tick frequency */
+      uwTickFreq = prevTickFreq;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief Return tick frequency.
+  * @retval tick period in Hz
+  */
+HAL_TickFreqTypeDef HAL_GetTickFreq(void)
+{
+  return uwTickFreq;
+}
+
+/**
+  * @brief This function provides minimum delay (in milliseconds) based
+  *        on variable incremented.
+  * @note In the default implementation , SysTick timer is the source of time base.
+  *       It is used to generate interrupts at regular time intervals where uwTick
+  *       is incremented.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @param Delay  specifies the delay time length, in milliseconds.
+  * @retval None
+  */
+__weak void HAL_Delay(uint32_t Delay)
+{
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t wait = Delay;
+
+  /* Add a freq to guarantee minimum wait */
+  if (wait < HAL_MAX_DELAY)
+  {
+    wait += (uint32_t)(uwTickFreq);
+  }
+
+  while ((HAL_GetTick() - tickstart) < wait)
+  {
+  }
+}
+
+/**
+  * @brief Suspend Tick increment.
+  * @note In the default implementation , SysTick timer is the source of time base. It is
+  *       used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
+  *       is called, the the SysTick interrupt will be disabled and so Tick increment
+  *       is suspended.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @retval None
+  */
+__weak void HAL_SuspendTick(void)
+{
+  /* Disable SysTick Interrupt */
+  SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
+}
+
+/**
+  * @brief Resume Tick increment.
+  * @note In the default implementation , SysTick timer is the source of time base. It is
+  *       used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
+  *       is called, the the SysTick interrupt will be enabled and so Tick increment
+  *       is resumed.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @retval None
+  */
+__weak void HAL_ResumeTick(void)
+{
+  /* Enable SysTick Interrupt */
+  SysTick->CTRL  |= SysTick_CTRL_TICKINT_Msk;
+}
+
+/**
+  * @brief  Returns the HAL revision
+  * @retval version : 0xXYZR (8bits for each decimal, R for RC)
+  */
+uint32_t HAL_GetHalVersion(void)
+{
+ return __STM32H7xx_HAL_VERSION;
+}
+
+/**
+  * @brief  Returns the device revision identifier.
+  * @retval Device revision identifier
+  */
+uint32_t HAL_GetREVID(void)
+{
+   return((DBGMCU->IDCODE) >> 16);
+}
+
+/**
+  * @brief  Returns the device identifier.
+  * @retval Device identifier
+  */
+uint32_t HAL_GetDEVID(void)
+{
+   return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
+}
+
+/**
+  * @brief  Return the first word of the unique device identifier (UID based on 96 bits)
+  * @retval Device identifier
+  */
+uint32_t HAL_GetUIDw0(void)
+{
+  return(READ_REG(*((uint32_t *)UID_BASE)));
+}
+
+/**
+  * @brief  Return the second word of the unique device identifier (UID based on 96 bits)
+  * @retval Device identifier
+  */
+uint32_t HAL_GetUIDw1(void)
+{
+  return(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
+}
+
+/**
+  * @brief  Return the third word of the unique device identifier (UID based on 96 bits)
+  * @retval Device identifier
+  */
+uint32_t HAL_GetUIDw2(void)
+{
+  return(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
+}
+
+/**
+  * @brief Configure the internal voltage reference buffer voltage scale.
+  * @param VoltageScaling  specifies the output voltage to achieve
+  *          This parameter can be one of the following values:
+  *            @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 2.048 V.
+  *                                                This requires VDDA equal to or higher than 2.4 V.
+  *            @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT2 around 2.5 V.
+  *                                                This requires VDDA equal to or higher than 2.8 V.
+  *            @arg SYSCFG_VREFBUF_VOLTAGE_SCALE2: VREF_OUT3 around 1.5 V.
+  *                                                This requires VDDA equal to or higher than 1.8 V.
+  *            @arg SYSCFG_VREFBUF_VOLTAGE_SCALE3: VREF_OUT4 around 1.8 V.
+  *                                                This requires VDDA equal to or higher than 2.1 V.
+  * @retval None
+  */
+void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling));
+
+  MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling);
+}
+
+/**
+  * @brief Configure the internal voltage reference buffer high impedance mode.
+  * @param Mode  specifies the high impedance mode
+  *          This parameter can be one of the following values:
+  *            @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output.
+  *            @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance.
+  * @retval None
+  */
+void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode));
+
+  MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode);
+}
+
+/**
+  * @brief  Tune the Internal Voltage Reference buffer (VREFBUF).
+  * @retval None
+  */
+void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue));
+
+  MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue);
+}
+
+/**
+  * @brief  Enable the Internal Voltage Reference buffer (VREFBUF).
+  * @retval HAL_OK/HAL_TIMEOUT
+  */
+HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void)
+{
+  uint32_t  tickstart;
+
+  SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
+
+  /* Get Start Tick*/
+  tickstart = HAL_GetTick();
+
+  /* Wait for VRR bit  */
+  while(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0UL)
+  {
+    if((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the Internal Voltage Reference buffer (VREFBUF).
+  *
+  * @retval None
+  */
+void HAL_SYSCFG_DisableVREFBUF(void)
+{
+  CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
+}
+
+#if defined(SYSCFG_PMCR_EPIS_SEL)
+/**
+  * @brief  Ethernet PHY Interface Selection either MII or RMII
+  * @param  SYSCFG_ETHInterface: Selects the Ethernet PHY interface
+  *   This parameter can be one of the following values:
+  *   @arg SYSCFG_ETH_MII : Select the Media Independent Interface
+  *   @arg SYSCFG_ETH_RMII: Select the Reduced Media Independent Interface
+  * @retval None
+  */
+void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface)
+{
+  /* Check the parameter */
+  assert_param(IS_SYSCFG_ETHERNET_CONFIG(SYSCFG_ETHInterface));
+
+  MODIFY_REG(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL, (uint32_t)(SYSCFG_ETHInterface));
+}
+#endif /* SYSCFG_PMCR_EPIS_SEL */
+
+/**
+  * @brief  Analog Switch control for dual analog pads.
+  * @param  SYSCFG_AnalogSwitch: Selects the analog pad
+  *   This parameter can be one or a combination of the following values:
+  *   @arg SYSCFG_SWITCH_PA0 : Select PA0 analog switch
+  *   @arg SYSCFG_SWITCH_PA1:  Select PA1 analog switch
+  *   @arg SYSCFG_SWITCH_PC2 : Select PC2 analog switch
+  *   @arg SYSCFG_SWITCH_PC3:  Select PC3 analog switch
+  * @param  SYSCFG_SwitchState: Open or Close the analog switch between dual pads (PXn and PXn_C)
+  *   This parameter can be one or a combination of the following values:
+  *   @arg SYSCFG_SWITCH_PA0_OPEN
+  *   @arg SYSCFG_SWITCH_PA0_CLOSE
+  *   @arg SYSCFG_SWITCH_PA1_OPEN
+  *   @arg SYSCFG_SWITCH_PA1_CLOSE
+  *   @arg SYSCFG_SWITCH_PC2_OPEN
+  *   @arg SYSCFG_SWITCH_PC2_CLOSE
+  *   @arg SYSCFG_SWITCH_PC3_OPEN
+  *   @arg SYSCFG_SWITCH_PC3_CLOSE
+  * @retval None
+  */
+
+void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState )
+{
+  /* Check the parameter */
+  assert_param(IS_SYSCFG_ANALOG_SWITCH(SYSCFG_AnalogSwitch));
+  assert_param(IS_SYSCFG_SWITCH_STATE(SYSCFG_SwitchState));
+
+  MODIFY_REG(SYSCFG->PMCR, (uint32_t) SYSCFG_AnalogSwitch, (uint32_t)(SYSCFG_SwitchState));
+}
+
+#if defined(SYSCFG_PMCR_BOOSTEN)
+/**
+  * @brief  Enables the booster to reduce the total harmonic distortion of the analog
+  *         switch when the supply voltage is lower than 2.7 V.
+  * @note   Activating the booster allows to guaranty the analog switch AC performance
+  *         when the supply voltage is below 2.7 V: in this case, the analog switch
+  *         performance is the same on the full voltage range
+  * @retval None
+  */
+void HAL_SYSCFG_EnableBOOST(void)
+{
+ SET_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
+}
+
+/**
+  * @brief  Disables the booster
+  * @note   Activating the booster allows to guaranty the analog switch AC performance
+  *         when the supply voltage is below 2.7 V: in this case, the analog switch
+  *         performance is the same on the full voltage range
+  * @retval None
+  */
+void HAL_SYSCFG_DisableBOOST(void)
+{
+ CLEAR_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
+}
+#endif /* SYSCFG_PMCR_BOOSTEN */
+
+#if defined (SYSCFG_UR2_BOOT_ADD0) ||  defined (SYSCFG_UR2_BCM7_ADD0)
+/**
+  * @brief  BootCM7 address 0 configuration
+  * @param  BootRegister :Specifies the Boot Address register (Address0 or Address1)
+  *   This parameter can be one of the following values:
+  *   @arg SYSCFG_BOOT_ADDR0 : Select the boot address0
+  *   @arg SYSCFG_BOOT_ADDR1:  Select the boot address1
+  * @param  BootAddress :Specifies the CM7 Boot Address to be loaded in Address0 or Address1
+  * @retval None
+  */
+void HAL_SYSCFG_CM7BootAddConfig(uint32_t BootRegister, uint32_t BootAddress)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_BOOT_REGISTER(BootRegister));
+  assert_param(IS_SYSCFG_BOOT_ADDRESS(BootAddress));
+  if ( BootRegister == SYSCFG_BOOT_ADDR0 )
+  {
+    /* Configure CM7 BOOT ADD0 */
+#if defined(DUAL_CORE)
+    MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0, ((BootAddress >> 16) << SYSCFG_UR2_BCM7_ADD0_Pos));
+#else
+    MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0, ((BootAddress >> 16) << SYSCFG_UR2_BOOT_ADD0_Pos));
+#endif /*DUAL_CORE*/
+  }
+  else
+  {
+    /* Configure CM7 BOOT ADD1 */
+#if defined(DUAL_CORE)
+    MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1, (BootAddress >> 16));
+#else
+    MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1, (BootAddress >> 16));
+#endif /*DUAL_CORE*/
+  }
+}
+#endif /* SYSCFG_UR2_BOOT_ADD0 || SYSCFG_UR2_BCM7_ADD0 */
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  BootCM4 address 0 configuration
+  * @param  BootRegister :Specifies the Boot Address register (Address0 or Address1)
+  *   This parameter can be one of the following values:
+  *   @arg SYSCFG_BOOT_ADDR0 : Select the boot address0
+  *   @arg SYSCFG_BOOT_ADDR1:  Select the boot address1
+  * @param  BootAddress :Specifies the CM4 Boot Address to be loaded in Address0 or Address1
+  * @retval None
+  */
+void HAL_SYSCFG_CM4BootAddConfig(uint32_t BootRegister, uint32_t BootAddress)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_BOOT_REGISTER(BootRegister));
+  assert_param(IS_SYSCFG_BOOT_ADDRESS(BootAddress));
+
+  if ( BootRegister == SYSCFG_BOOT_ADDR0 )
+  {
+    /* Configure CM4 BOOT ADD0 */
+    MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0, ((BootAddress >> 16)<< SYSCFG_UR3_BCM4_ADD0_Pos));
+  }
+
+  else
+  {
+    /* Configure CM4 BOOT ADD1 */
+    MODIFY_REG(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1, (BootAddress >> 16));
+  }
+}
+
+/**
+  * @brief  Enables the Cortex-M7 boot
+  * @retval None
+  */
+void HAL_SYSCFG_EnableCM7BOOT(void)
+{
+ SET_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM7);
+}
+
+/**
+  * @brief  Disables the Cortex-M7 boot
+  * @note   Disabling the boot will gate the CPU clock
+  * @retval None
+  */
+void HAL_SYSCFG_DisableCM7BOOT(void)
+{
+ CLEAR_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM7) ;
+}
+
+/**
+  * @brief  Enables the Cortex-M4 boot
+  * @retval None
+  */
+void HAL_SYSCFG_EnableCM4BOOT(void)
+{
+ SET_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4);
+}
+
+/**
+  * @brief  Disables the Cortex-M4 boot
+  * @note   Disabling the boot will gate the CPU clock
+  * @retval None
+  */
+void HAL_SYSCFG_DisableCM4BOOT(void)
+{
+  CLEAR_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4);
+}
+#endif /*DUAL_CORE*/
+/**
+  * @brief  Enables the I/O Compensation Cell.
+  * @note   The I/O compensation cell can be used only when the device supply
+  *         voltage ranges from 2.4 to 3.6 V.
+  * @retval None
+  */
+void HAL_EnableCompensationCell(void)
+{
+  SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN) ;
+}
+
+/**
+  * @brief  Power-down the I/O Compensation Cell.
+  * @note   The I/O compensation cell can be used only when the device supply
+  *         voltage ranges from 2.4 to 3.6 V.
+  * @retval None
+  */
+void HAL_DisableCompensationCell(void)
+{
+  CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN);
+}
+
+
+/**
+  * @brief  To Enable optimize the I/O speed when the product voltage is low.
+  * @note   This bit is active only if PRODUCT_BELOW_25V user option bit is set. It must be
+  *         used only if the product supply voltage is below 2.5 V. Setting this bit when VDD is
+  *         higher than 2.5 V might be destructive.
+  * @retval None
+  */
+void HAL_SYSCFG_EnableIOSpeedOptimize(void)
+{
+#if defined(SYSCFG_CCCSR_HSLV)
+  SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);
+#else
+  SET_BIT(SYSCFG->CCCSR, (SYSCFG_CCCSR_HSLV0| SYSCFG_CCCSR_HSLV1 | SYSCFG_CCCSR_HSLV2  | SYSCFG_CCCSR_HSLV3));
+#endif   /* SYSCFG_CCCSR_HSLV */
+}
+
+/**
+  * @brief  To Disable optimize the I/O speed when the product voltage is low.
+  * @note   This bit is active only if PRODUCT_BELOW_25V user option bit is set. It must be
+  *         used only if the product supply voltage is below 2.5 V. Setting this bit when VDD is
+  *         higher than 2.5 V might be destructive.
+  * @retval None
+  */
+void HAL_SYSCFG_DisableIOSpeedOptimize(void)
+{
+#if defined(SYSCFG_CCCSR_HSLV)
+  CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);
+#else
+  CLEAR_BIT(SYSCFG->CCCSR, (SYSCFG_CCCSR_HSLV0| SYSCFG_CCCSR_HSLV1 | SYSCFG_CCCSR_HSLV2  | SYSCFG_CCCSR_HSLV3));
+#endif   /* SYSCFG_CCCSR_HSLV */
+}
+
+/**
+  * @brief  Code selection for the I/O Compensation cell
+  * @param  SYSCFG_CompCode: Selects the code to be applied for the I/O compensation cell
+  *   This parameter can be one of the following values:
+  *   @arg SYSCFG_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR)
+  *   @arg SYSCFG_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR)
+  * @retval None
+  */
+void HAL_SYSCFG_CompensationCodeSelect(uint32_t SYSCFG_CompCode)
+{
+  /* Check the parameter */
+  assert_param(IS_SYSCFG_CODE_SELECT(SYSCFG_CompCode));
+  MODIFY_REG(SYSCFG->CCCSR, SYSCFG_CCCSR_CS, (uint32_t)(SYSCFG_CompCode));
+}
+
+/**
+  * @brief  Code selection for the I/O Compensation cell
+  * @param  SYSCFG_PMOSCode: PMOS compensation code
+  *         This code is applied to the I/O compensation cell when the CS bit of the
+  *          SYSCFG_CMPCR is set
+  * @param  SYSCFG_NMOSCode: NMOS compensation code
+  *         This code is applied to the I/O compensation cell when the CS bit of the
+  *          SYSCFG_CMPCR is set
+  * @retval None
+  */
+void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode )
+{
+  /* Check the parameter */
+  assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_PMOSCode));
+  assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_NMOSCode));
+  MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC|SYSCFG_CCCR_PCC, (((uint32_t)(SYSCFG_PMOSCode)<< 4)|(uint32_t)(SYSCFG_NMOSCode)) );
+}
+
+#if defined(SYSCFG_CCCR_NCC_MMC)
+/**
+  * @brief  Code selection for the I/O Compensation cell
+  * @param  SYSCFG_PMOSCode: VDDMMC PMOS compensation code
+  *         This code is applied to the I/O compensation cell when the CS bit of the
+  *          SYSCFG_CMPCR is set
+  * @param  SYSCFG_NMOSCode: VDDMMC NMOS compensation code
+  *         This code is applied to the I/O compensation cell when the CS bit of the
+  *          SYSCFG_CMPCR is set
+  * @retval None
+  */
+void HAL_SYSCFG_VDDMMC_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode )
+{
+  /* Check the parameter */
+  assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_PMOSCode));
+  assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_NMOSCode));
+  MODIFY_REG(SYSCFG->CCCR, (SYSCFG_CCCR_NCC_MMC | SYSCFG_CCCR_PCC_MMC), (((uint32_t)(SYSCFG_PMOSCode)<< 4)|(uint32_t)(SYSCFG_NMOSCode)) );
+}
+#endif /* SYSCFG_CCCR_NCC_MMC */
+
+/**
+  * @brief  Enable the Debug Module during Domain1/CDomain SLEEP mode
+  * @retval None
+  */
+void HAL_EnableDBGSleepMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
+}
+
+/**
+  * @brief  Disable the Debug Module during Domain1/CDomain SLEEP mode
+  * @retval None
+  */
+void HAL_DisableDBGSleepMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
+}
+
+
+/**
+  * @brief  Enable the Debug Module during Domain1/CDomain STOP mode
+  * @retval None
+  */
+void HAL_EnableDBGStopMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
+}
+
+/**
+  * @brief  Disable the Debug Module during Domain1/CDomain STOP mode
+  * @retval None
+  */
+void HAL_DisableDBGStopMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
+}
+
+/**
+  * @brief  Enable the Debug Module during Domain1/CDomain STANDBY mode
+  * @retval None
+  */
+void HAL_EnableDBGStandbyMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
+}
+
+/**
+  * @brief  Disable the Debug Module during Domain1/CDomain STANDBY mode
+  * @retval None
+  */
+void HAL_DisableDBGStandbyMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Enable the Debug Module during Domain1 SLEEP mode
+  * @retval None
+  */
+void HAL_EnableDomain2DBGSleepMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2);
+}
+
+/**
+  * @brief  Disable the Debug Module during Domain2 SLEEP mode
+  * @retval None
+  */
+void HAL_DisableDomain2DBGSleepMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2);
+}
+
+/**
+  * @brief  Enable the Debug Module during Domain2 STOP mode
+  * @retval None
+  */
+void HAL_EnableDomain2DBGStopMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2);
+}
+
+/**
+  * @brief  Disable the Debug Module during Domain2 STOP mode
+  * @retval None
+  */
+void HAL_DisableDomain2DBGStopMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2);
+}
+
+/**
+  * @brief  Enable the Debug Module during Domain2 STANDBY mode
+  * @retval None
+  */
+void HAL_EnableDomain2DBGStandbyMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2);
+}
+
+/**
+  * @brief  Disable the Debug Module during Domain2 STANDBY mode
+  * @retval None
+  */
+void HAL_DisableDomain2DBGStandbyMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2);
+}
+#endif /*DUAL_CORE*/
+
+/**
+  * @brief  Enable the Debug Module during Domain3/SRDomain STOP mode
+  * @retval None
+  */
+void HAL_EnableDomain3DBGStopMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
+}
+/**
+  * @brief  Disable the Debug Module during Domain3/SRDomain STOP mode
+  * @retval None
+  */
+void HAL_DisableDomain3DBGStopMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
+}
+
+/**
+  * @brief  Enable the Debug Module during Domain3/SRDomain STANDBY mode
+  * @retval None
+  */
+void HAL_EnableDomain3DBGStandbyMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
+}
+
+/**
+  * @brief  Disable the Debug Module during Domain3/SRDomain STANDBY mode
+  * @retval None
+  */
+void HAL_DisableDomain3DBGStandbyMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
+}
+
+/**
+  * @brief  Set the FMC Memory Mapping Swapping config.
+  * @param  BankMapConfig: Defines the FMC Bank mapping configuration. This parameter can be
+            FMC_SWAPBMAP_DISABLE, FMC_SWAPBMAP_SDRAM_SRAM, FMC_SWAPBMAP_SDRAMB2
+  * @retval HAL state
+  */
+void HAL_SetFMCMemorySwappingConfig(uint32_t BankMapConfig)
+{
+  /* Check the parameter */
+  assert_param(IS_FMC_SWAPBMAP_MODE(BankMapConfig));
+  MODIFY_REG(FMC_Bank1_R->BTCR[0], FMC_BCR1_BMAP, BankMapConfig);
+}
+
+/**
+  * @brief  Get FMC Bank mapping mode.
+  * @retval The FMC Bank mapping mode. This parameter can be
+            FMC_SWAPBMAP_DISABLE, FMC_SWAPBMAP_SDRAM_SRAM, FMC_SWAPBMAP_SDRAMB2
+*/
+uint32_t HAL_GetFMCMemorySwappingConfig(void)
+{
+  return READ_BIT(FMC_Bank1_R->BTCR[0], FMC_BCR1_BMAP);
+}
+
+/**
+  * @brief  Configure the EXTI input event line edge
+  * @note    No edge configuration for direct lines but for configurable lines:(EXTI_LINE0..EXTI_LINE21),
+  *          EXTI_LINE49,EXTI_LINE51,EXTI_LINE82,EXTI_LINE84,EXTI_LINE85 and EXTI_LINE86.
+  * @param   EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
+  *         (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
+  * @param   EXTI_Edge: Specifies  EXTI line Edge used.
+  *          This parameter can be one of the following values :
+  *   @arg EXTI_RISING_EDGE : Configurable line, with Rising edge trigger detection
+  *   @arg EXTI_FALLING_EDGE: Configurable line, with Falling edge trigger detection
+  * @retval None
+  */
+void HAL_EXTI_EdgeConfig(uint32_t EXTI_Line , uint32_t EXTI_Edge )
+{
+  /* Check the parameter */
+  assert_param(IS_HAL_EXTI_CONFIG_LINE(EXTI_Line));
+  assert_param(IS_EXTI_EDGE_LINE(EXTI_Edge));
+
+  /* Clear Rising Falling edge configuration */
+  CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+  CLEAR_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+
+  if( (EXTI_Edge & EXTI_RISING_EDGE) == EXTI_RISING_EDGE)
+  {
+   SET_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+  }
+  if( (EXTI_Edge & EXTI_FALLING_EDGE) == EXTI_FALLING_EDGE)
+  {
+   SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+  }
+}
+
+/**
+  * @brief  Generates a Software interrupt on selected EXTI line.
+  * @param   EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
+  *          (EXTI_LINE0..EXTI_LINE21),EXTI_LINE49,EXTI_LINE51,EXTI_LINE82,EXTI_LINE84,EXTI_LINE85 and EXTI_LINE86.
+  * @retval None
+  */
+void HAL_EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
+{
+  /* Check the parameters */
+  assert_param(IS_HAL_EXTI_CONFIG_LINE(EXTI_Line));
+
+  SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->SWIER1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+}
+
+
+/**
+  * @brief  Clears the EXTI's line pending flags for Domain D1
+  * @param   EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
+  *         (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
+  * @retval None
+  */
+void HAL_EXTI_D1_ClearFlag(uint32_t EXTI_Line)
+{
+  /* Check the parameters */
+ assert_param(IS_EXTI_D1_LINE(EXTI_Line));
+ WRITE_REG(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->PR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Clears the EXTI's line pending flags for Domain D2
+  * @param   EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
+  *         (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
+  * @retval None
+  */
+void HAL_EXTI_D2_ClearFlag(uint32_t EXTI_Line)
+{
+  /* Check the parameters */
+ assert_param(IS_EXTI_D2_LINE(EXTI_Line));
+ WRITE_REG(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->PR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+}
+
+#endif /*DUAL_CORE*/
+/**
+  * @brief  Configure the EXTI input event line for Domain D1
+  * @param   EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
+  *         (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
+  * @param   EXTI_Mode: Specifies which EXTI line is used as interrupt or an event.
+  *          This parameter can be one or a combination of the following values :
+  *   @arg EXTI_MODE_IT :  Interrupt Mode selected
+  *   @arg EXTI_MODE_EVT : Event Mode selected
+  * @param   EXTI_LineCmd controls (Enable/Disable) the EXTI line.
+
+  * @retval None
+  */
+void HAL_EXTI_D1_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode,  uint32_t EXTI_LineCmd )
+{
+  /* Check the parameter */
+  assert_param(IS_EXTI_D1_LINE(EXTI_Line));
+  assert_param(IS_EXTI_MODE_LINE(EXTI_Mode));
+
+  if( (EXTI_Mode & EXTI_MODE_IT) == EXTI_MODE_IT)
+  {
+     if( EXTI_LineCmd == 0UL)
+     {
+       /* Clear EXTI line configuration */
+        CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)),(uint32_t)(1UL << (EXTI_Line & 0x1FUL)) );
+     }
+     else
+     {
+        SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+     }
+  }
+
+  if( (EXTI_Mode & EXTI_MODE_EVT) == EXTI_MODE_EVT)
+  {
+    if( EXTI_LineCmd == 0UL)
+    {
+      /* Clear EXTI line configuration */
+      CLEAR_BIT(  *(__IO uint32_t *) (((uint32_t) &(EXTI_D1->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+    }
+    else
+    {
+      SET_BIT(  *(__IO uint32_t *) (((uint32_t) &(EXTI_D1->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+    }
+  }
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Configure the EXTI input event line for Domain D2
+  * @param   EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
+  *         (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
+  * @param   EXTI_Mode: Specifies which EXTI line is used as interrupt or an event.
+  *          This parameter can be one or a combination of the following values :
+  *   @arg EXTI_MODE_IT :  Interrupt Mode selected
+  *   @arg EXTI_MODE_EVT : Event Mode selected
+  * @param   EXTI_LineCmd controls (Enable/Disable) the EXTI line.
+
+  * @retval None
+  */
+void HAL_EXTI_D2_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode,  uint32_t EXTI_LineCmd )
+{
+  /* Check the parameter */
+  assert_param(IS_EXTI_D2_LINE(EXTI_Line));
+  assert_param(IS_EXTI_MODE_LINE(EXTI_Mode));
+
+  if( (EXTI_Mode & EXTI_MODE_IT) == EXTI_MODE_IT)
+  {
+    if( EXTI_LineCmd == 0UL)
+    {
+    /* Clear EXTI line configuration */
+     CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)),(uint32_t)(1UL << (EXTI_Line & 0x1FUL)) );
+    }
+    else
+    {
+     SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+    }
+  }
+
+  if( (EXTI_Mode & EXTI_MODE_EVT) == EXTI_MODE_EVT)
+  {
+    if( EXTI_LineCmd == 0UL)
+    {
+      /* Clear EXTI line configuration */
+      CLEAR_BIT(  *(__IO uint32_t *) (((uint32_t) &(EXTI_D2->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+    }
+    else
+    {
+      SET_BIT(  *(__IO uint32_t *) (((uint32_t) &(EXTI_D2->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+    }
+  }
+}
+#endif /*DUAL_CORE*/
+
+/**
+  * @brief  Configure the EXTI input event line for Domain D3
+  * @param   EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
+  *         (EXTI_LINE0...EXTI_LINE15),(EXTI_LINE19...EXTI_LINE21),EXTI_LINE25, EXTI_LINE34,
+  *          EXTI_LINE35,EXTI_LINE41,(EXTI_LINE48...EXTI_LINE53)
+  * @param   EXTI_LineCmd controls (Enable/Disable) the EXTI line.
+  * @param   EXTI_ClearSrc: Specifies the clear source of D3 pending event.
+  *          This parameter can be one of the following values :
+  *   @arg BDMA_CH6_CLEAR : BDMA ch6 event selected as D3 domain pendclear source
+  *   @arg BDMA_CH7_CLEAR : BDMA ch7 event selected as D3 domain pendclear source
+  *   @arg LPTIM4_OUT_CLEAR : LPTIM4 out selected as D3 domain pendclear source
+  *   @arg LPTIM5_OUT_CLEAR : LPTIM5 out selected as D3 domain pendclear source
+  * @retval None
+  */
+void HAL_EXTI_D3_EventInputConfig(uint32_t EXTI_Line, uint32_t EXTI_LineCmd , uint32_t EXTI_ClearSrc  )
+{
+  __IO uint32_t *pRegv;
+
+  /* Check the parameter */
+  assert_param(IS_EXTI_D3_LINE(EXTI_Line));
+  assert_param(IS_EXTI_D3_CLEAR(EXTI_ClearSrc));
+
+  if( EXTI_LineCmd == 0UL)
+  {
+    /* Clear EXTI line configuration */
+    CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->D3PMR1)) + ((EXTI_Line >> 5 ) * 0x20UL)),(uint32_t)(1UL << (EXTI_Line & 0x1FUL)) );
+  }
+  else
+  {
+    SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->D3PMR1)) +((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+  }
+
+  if(((EXTI_Line>>4)%2UL) == 0UL)
+  {
+    pRegv = (__IO uint32_t *) (((uint32_t) &(EXTI->D3PCR1L)) + ((EXTI_Line >> 5 ) * 0x20UL));
+  }
+  else
+  {
+    pRegv = (__IO uint32_t *) (((uint32_t) &(EXTI->D3PCR1H)) + ((EXTI_Line >> 5 ) * 0x20UL));
+  }
+  MODIFY_REG(*pRegv, (uint32_t)(3UL << ((EXTI_Line*2UL) & 0x1FUL)), (uint32_t)(EXTI_ClearSrc << ((EXTI_Line*2UL) & 0x1FUL)));
+
+}
+
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c
new file mode 100644
index 00000000..631f432f
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c
@@ -0,0 +1,533 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_cortex.c
+  * @author  MCD Application Team
+  * @brief   CORTEX HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the CORTEX:
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions
+  *
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+
+    [..]
+    *** How to configure Interrupts using CORTEX HAL driver ***
+    ===========================================================
+    [..]
+    This section provides functions allowing to configure the NVIC interrupts (IRQ).
+    The Cortex-M exceptions are managed by CMSIS functions.
+
+    (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
+        function according to the following table.
+    (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
+    (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
+    (#) please refer to programming manual for details in how to configure priority.
+
+     -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
+         The pending IRQ priority will be managed only by the sub priority.
+
+     -@- IRQ priority order (sorted by highest to lowest priority):
+        (+@) Lowest preemption priority
+        (+@) Lowest sub priority
+        (+@) Lowest hardware priority (IRQ number)
+
+    [..]
+    *** How to configure Systick using CORTEX HAL driver ***
+    ========================================================
+    [..]
+    Setup SysTick Timer for time base.
+
+   (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
+       is a CMSIS function that:
+        (++) Configures the SysTick Reload register with value passed as function parameter.
+        (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
+        (++) Resets the SysTick Counter register.
+        (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
+        (++) Enables the SysTick Interrupt.
+        (++) Starts the SysTick Counter.
+
+   (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
+       HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
+       HAL_SYSTICK_Config() function call. The HAL_SYSTICK_CLKSourceConfig() macro is defined
+       inside the stm32h7xx_hal_cortex.h file.
+
+   (+) You can change the SysTick IRQ priority by calling the
+       HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
+       call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
+
+   (+) To adjust the SysTick time base, use the following formula:
+
+       Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
+       (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
+       (++) Reload Value should not exceed 0xFFFFFF
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup CORTEX CORTEX
+  * @brief CORTEX HAL module driver
+  * @{
+  */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
+  * @{
+  */
+
+
+/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+  ==============================================================================
+              ##### Initialization and de-initialization functions #####
+  ==============================================================================
+    [..]
+      This section provides the CORTEX HAL driver functions allowing to configure Interrupts
+      Systick functionalities
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Sets the priority grouping field (preemption priority and subpriority)
+  *         using the required unlock sequence.
+  * @param  PriorityGroup The priority grouping bits length.
+  *         This parameter can be one of the following values:
+  *         @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
+  *                                    4 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
+  *                                    3 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
+  *                                    2 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
+  *                                    1 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
+  *                                    0 bits for subpriority
+  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
+  *         The pending IRQ priority will be managed only by the subpriority.
+  * @retval None
+  */
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+
+  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
+  NVIC_SetPriorityGrouping(PriorityGroup);
+}
+
+/**
+  * @brief  Sets the priority of an interrupt.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
+  * @param  PreemptPriority The preemption priority for the IRQn channel.
+  *         This parameter can be a value between 0 and 15
+  *         A lower priority value indicates a higher priority
+  * @param  SubPriority the subpriority level for the IRQ channel.
+  *         This parameter can be a value between 0 and 15
+  *         A lower priority value indicates a higher priority.
+  * @retval None
+  */
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t prioritygroup;
+
+  /* Check the parameters */
+  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
+  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
+
+  prioritygroup = NVIC_GetPriorityGrouping();
+
+  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
+}
+
+/**
+  * @brief  Enables a device specific interrupt in the NVIC interrupt controller.
+  * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
+  *         function should be called before.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+  /* Enable interrupt */
+  NVIC_EnableIRQ(IRQn);
+}
+
+/**
+  * @brief  Disables a device specific interrupt in the NVIC interrupt controller.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+  /* Disable interrupt */
+  NVIC_DisableIRQ(IRQn);
+}
+
+/**
+  * @brief  Initiates a system reset request to reset the MCU.
+  * @retval None
+  */
+void HAL_NVIC_SystemReset(void)
+{
+  /* System Reset */
+  NVIC_SystemReset();
+}
+
+/**
+  * @brief  Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+  *         Counter is in free running mode to generate periodic interrupts.
+  * @param  TicksNumb Specifies the ticks Number of ticks between two interrupts.
+  * @retval status   - 0  Function succeeded.
+  *                  - 1  Function failed.
+  */
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
+{
+   return SysTick_Config(TicksNumb);
+}
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
+ *  @brief   Cortex control functions
+ *
+@verbatim
+  ==============================================================================
+                      ##### Peripheral Control functions #####
+  ==============================================================================
+    [..]
+      This subsection provides a set of functions allowing to control the CORTEX
+      (NVIC, SYSTICK, MPU) functionalities.
+
+
+@endverbatim
+  * @{
+  */
+#if (__MPU_PRESENT == 1)
+/**
+  * @brief  Disables the MPU
+  * @retval None
+  */
+void HAL_MPU_Disable(void)
+{
+  /* Make sure outstanding transfers are done */
+  __DMB();
+
+  /* Disable fault exceptions */
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+
+  /* Disable the MPU and clear the control register*/
+  MPU->CTRL = 0;
+}
+
+/**
+  * @brief  Enables the MPU
+  * @param  MPU_Control Specifies the control mode of the MPU during hard fault,
+  *         NMI, FAULTMASK and privileged access to the default memory
+  *         This parameter can be one of the following values:
+  *            @arg MPU_HFNMI_PRIVDEF_NONE
+  *            @arg MPU_HARDFAULT_NMI
+  *            @arg MPU_PRIVILEGED_DEFAULT
+  *            @arg MPU_HFNMI_PRIVDEF
+  * @retval None
+  */
+void HAL_MPU_Enable(uint32_t MPU_Control)
+{
+  /* Enable the MPU */
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+
+  /* Enable fault exceptions */
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+
+  /* Ensure MPU setting take effects */
+  __DSB();
+  __ISB();
+}
+/**
+  * @brief  Initializes and configures the Region and the memory to be protected.
+  * @param  MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
+  *                  the initialization and configuration information.
+  * @retval None
+  */
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
+{
+  /* Check the parameters */
+  assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
+  assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
+
+  /* Set the Region number */
+  MPU->RNR = MPU_Init->Number;
+
+  if ((MPU_Init->Enable) != 0UL)
+  {
+    /* Check the parameters */
+    assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
+    assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
+    assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
+    assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
+    assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
+    assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
+    assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
+    assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
+
+    MPU->RBAR = MPU_Init->BaseAddress;
+    MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
+                ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
+                ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
+                ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
+                ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
+                ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
+                ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
+                ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
+                ((uint32_t)MPU_Init->Enable                  << MPU_RASR_ENABLE_Pos);
+  }
+  else
+  {
+    MPU->RBAR = 0x00;
+    MPU->RASR = 0x00;
+  }
+}
+#endif /* __MPU_PRESENT */
+
+/**
+  * @brief  Gets the priority grouping field from the NVIC Interrupt Controller.
+  * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
+  */
+uint32_t HAL_NVIC_GetPriorityGrouping(void)
+{
+  /* Get the PRIGROUP[10:8] field value */
+  return NVIC_GetPriorityGrouping();
+}
+
+/**
+  * @brief  Gets the priority of an interrupt.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
+  * @param   PriorityGroup the priority grouping bits length.
+  *         This parameter can be one of the following values:
+  *           @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
+  *                                      4 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
+  *                                      3 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
+  *                                      2 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
+  *                                      1 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
+  *                                      0 bits for subpriority
+  * @param  pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
+  * @param  pSubPriority Pointer on the Subpriority value (starting from 0).
+  * @retval None
+  */
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+ /* Get priority for Cortex-M system or device specific interrupts */
+  NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
+}
+
+/**
+  * @brief  Sets Pending bit of an external interrupt.
+  * @param  IRQn External interrupt number
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+  /* Set interrupt pending */
+  NVIC_SetPendingIRQ(IRQn);
+}
+
+/**
+  * @brief  Gets Pending Interrupt (reads the pending register in the NVIC
+  *         and returns the pending bit for the specified interrupt).
+  * @param  IRQn External interrupt number.
+  *          This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
+  * @retval status  - 0  Interrupt status is not pending.
+  *                 - 1  Interrupt status is pending.
+  */
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+  /* Return 1 if pending else 0 */
+  return NVIC_GetPendingIRQ(IRQn);
+}
+
+/**
+  * @brief  Clears the pending bit of an external interrupt.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+  /* Clear pending interrupt */
+  NVIC_ClearPendingIRQ(IRQn);
+}
+
+/**
+  * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
+  * @param IRQn External interrupt number
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
+  * @retval status  - 0  Interrupt status is not pending.
+  *                 - 1  Interrupt status is pending.
+  */
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+  /* Return 1 if active else 0 */
+  return NVIC_GetActive(IRQn);
+}
+
+/**
+  * @brief  Configures the SysTick clock source.
+  * @param  CLKSource specifies the SysTick clock source.
+  *         This parameter can be one of the following values:
+  *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
+  *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
+  * @retval None
+  */
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
+  if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
+  {
+    SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
+  }
+  else
+  {
+    SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
+  }
+}
+
+/**
+  * @brief  This function handles SYSTICK interrupt request.
+  * @retval None
+  */
+void HAL_SYSTICK_IRQHandler(void)
+{
+  HAL_SYSTICK_Callback();
+}
+
+/**
+  * @brief  SYSTICK callback.
+  * @retval None
+  */
+__weak void HAL_SYSTICK_Callback(void)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SYSTICK_Callback could be implemented in the user file
+   */
+}
+
+#if defined(DUAL_CORE)
+
+/**
+  * @brief  Returns the current CPU ID.
+  * @retval CPU identifier
+  */
+uint32_t HAL_GetCurrentCPUID(void)
+{
+  if (((SCB->CPUID & 0x000000F0U) >> 4 )== 0x7U)
+  {
+    return  CM7_CPUID;
+  }
+  else
+  {
+    return CM4_CPUID;
+  }
+}
+
+#else
+
+/**
+* @brief  Returns the current CPU ID.
+* @retval CPU identifier
+*/
+uint32_t HAL_GetCurrentCPUID(void)
+{
+  return  CM7_CPUID;
+}
+
+#endif /*DUAL_CORE*/
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c
new file mode 100644
index 00000000..e2bbea73
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c
@@ -0,0 +1,2055 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_dma.c
+  * @author  MCD Application Team
+  * @brief   DMA HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Direct Memory Access (DMA) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral State and errors functions
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+   (#) Enable and configure the peripheral to be connected to the DMA Stream
+       (except for internal SRAM/FLASH memories: no initialization is
+       necessary) please refer to Reference manual for connection between peripherals
+       and DMA requests .
+
+   (#) For a given Stream, program the required configuration through the following parameters:
+       Transfer Direction, Source and Destination data formats,
+       Circular, Normal or peripheral flow control mode, Stream Priority level,
+       Source and Destination Increment mode, FIFO mode and its Threshold (if needed),
+       Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.
+
+     *** Polling mode IO operation ***
+     =================================
+    [..]
+          (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
+              address and destination address and the Length of data to be transferred
+          (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
+              case a fixed Timeout can be configured by User depending from his application.
+
+     *** Interrupt mode IO operation ***
+     ===================================
+    [..]
+          (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
+          (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
+          (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
+              Source address and destination address and the Length of data to be transferred. In this
+              case the DMA interrupt is configured
+          (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
+          (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
+              add his own function by customization of function pointer XferCpltCallback and
+              XferErrorCallback (i.e a member of DMA handle structure).
+    [..]
+     (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
+         detection.
+
+     (#) Use HAL_DMA_Abort() function to abort the current transfer
+
+     -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.
+
+     -@-   The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is
+           possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set
+           Half-Word data size for the peripheral to access its data register and set Word data size
+           for the Memory to gain in access time. Each two half words will be packed and written in
+           a single access to a Word in the Memory).
+
+     -@-   When FIFO is disabled, it is not allowed to configure different Data Sizes for Source
+           and Destination. In this case the Peripheral Data Size will be applied to both Source
+           and Destination.
+
+     *** DMA HAL driver macros list ***
+     =============================================
+     [..]
+       Below the list of most used macros in DMA HAL driver.
+
+      (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.
+      (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.
+      (+) __HAL_DMA_GET_FS: Return the current DMA Stream FIFO filled level.
+      (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Stream interrupts.
+      (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts.
+      (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not.
+
+     [..]
+      (@) You can refer to the DMA HAL driver header file for more useful macros.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup DMA DMA
+  * @brief DMA HAL module driver
+  * @{
+  */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+typedef struct
+{
+  __IO uint32_t ISR;   /*!< DMA interrupt status register */
+  __IO uint32_t Reserved0;
+  __IO uint32_t IFCR;  /*!< DMA interrupt flag clear register */
+} DMA_Base_Registers;
+
+typedef struct
+{
+  __IO uint32_t ISR;   /*!< BDMA interrupt status register */
+  __IO uint32_t IFCR;  /*!< BDMA interrupt flag clear register */
+} BDMA_Base_Registers;
+
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup DMA_Private_Constants
+ * @{
+ */
+#define HAL_TIMEOUT_DMA_ABORT         (5U)  /* 5 ms */
+
+#define BDMA_PERIPH_TO_MEMORY         (0x00000000U)                /*!< Peripheral to memory direction */
+#define BDMA_MEMORY_TO_PERIPH         ((uint32_t)BDMA_CCR_DIR)     /*!< Memory to peripheral direction */
+#define BDMA_MEMORY_TO_MEMORY         ((uint32_t)BDMA_CCR_MEM2MEM) /*!< Memory to memory direction     */
+
+/* DMA to BDMA conversion */
+#define DMA_TO_BDMA_DIRECTION(__DMA_DIRECTION__) (((__DMA_DIRECTION__) == DMA_MEMORY_TO_PERIPH)? BDMA_MEMORY_TO_PERIPH: \
+                                                  ((__DMA_DIRECTION__) == DMA_MEMORY_TO_MEMORY)? BDMA_MEMORY_TO_MEMORY: \
+                                                  BDMA_PERIPH_TO_MEMORY)
+
+#define DMA_TO_BDMA_PERIPHERAL_INC(__DMA_PERIPHERAL_INC__) ((__DMA_PERIPHERAL_INC__) >> 3U)
+#define DMA_TO_BDMA_MEMORY_INC(__DMA_MEMORY_INC__) ((__DMA_MEMORY_INC__) >> 3U)
+
+#define DMA_TO_BDMA_PDATA_SIZE(__DMA_PDATA_SIZE__) ((__DMA_PDATA_SIZE__) >> 3U)
+#define DMA_TO_BDMA_MDATA_SIZE(__DMA_MDATA_SIZE__) ((__DMA_MDATA_SIZE__) >> 3U)
+
+#define DMA_TO_BDMA_MODE(__DMA_MODE__) ((__DMA_MODE__) >> 3U)
+
+#define DMA_TO_BDMA_PRIORITY(__DMA_PRIORITY__) ((__DMA_PRIORITY__) >> 4U)
+
+#if defined(UART9)
+#define IS_DMA_UART_USART_REQUEST(__REQUEST__) ((((__REQUEST__) >= DMA_REQUEST_USART1_RX)  &&  ((__REQUEST__) <= DMA_REQUEST_USART3_TX)) || \
+                                                 (((__REQUEST__) >= DMA_REQUEST_UART4_RX)  &&  ((__REQUEST__) <= DMA_REQUEST_UART5_TX )) || \
+                                                 (((__REQUEST__) >= DMA_REQUEST_USART6_RX) &&  ((__REQUEST__) <= DMA_REQUEST_USART6_TX)) || \
+                                                 (((__REQUEST__) >= DMA_REQUEST_UART7_RX)  &&  ((__REQUEST__) <= DMA_REQUEST_UART8_TX )) || \
+                                                 (((__REQUEST__) >= DMA_REQUEST_UART9_RX)  &&  ((__REQUEST__) <= DMA_REQUEST_USART10_TX )))
+#else
+#define IS_DMA_UART_USART_REQUEST(__REQUEST__) ((((__REQUEST__) >= DMA_REQUEST_USART1_RX)  &&  ((__REQUEST__) <= DMA_REQUEST_USART3_TX)) || \
+                                                 (((__REQUEST__) >= DMA_REQUEST_UART4_RX)  &&  ((__REQUEST__) <= DMA_REQUEST_UART5_TX )) || \
+                                                 (((__REQUEST__) >= DMA_REQUEST_USART6_RX) &&  ((__REQUEST__) <= DMA_REQUEST_USART6_TX)) || \
+                                                 (((__REQUEST__) >= DMA_REQUEST_UART7_RX)  &&  ((__REQUEST__) <= DMA_REQUEST_UART8_TX )))
+
+#endif
+/**
+  * @}
+  */
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup DMA_Private_Functions
+  * @{
+  */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma);
+static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma);
+static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma);
+
+/**
+  * @}
+  */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @addtogroup DMA_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group1
+  *
+@verbatim
+ ===============================================================================
+             ##### Initialization and de-initialization functions  #####
+ ===============================================================================
+    [..]
+    This section provides functions allowing to initialize the DMA Stream source
+    and destination incrementation and data sizes, transfer direction,
+    circular/normal mode selection, memory-to-memory mode selection and Stream priority value.
+    [..]
+    The HAL_DMA_Init() function follows the DMA configuration procedures as described in
+    reference manual.
+    The HAL_DMA_DeInit function allows to deinitialize the DMA stream.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the DMA according to the specified
+  *         parameters in the DMA_InitTypeDef and create the associated handle.
+  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
+{
+  uint32_t registerValue;
+  uint32_t tickstart = HAL_GetTick();
+  DMA_Base_Registers *regs_dma;
+  BDMA_Base_Registers *regs_bdma;
+
+  /* Check the DMA peripheral handle */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+  assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
+  assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
+  assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
+  assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
+  assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
+  assert_param(IS_DMA_MODE(hdma->Init.Mode));
+  assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
+
+  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+  {
+    assert_param(IS_DMA_REQUEST(hdma->Init.Request));
+    assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode));
+    /* Check the memory burst, peripheral burst and FIFO threshold parameters only
+       when FIFO mode is enabled */
+    if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE)
+    {
+      assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold));
+      assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
+      assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
+    }
+
+    /* Allocate lock resource */
+    __HAL_UNLOCK(hdma);
+
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+
+    /* Disable the peripheral */
+    __HAL_DMA_DISABLE(hdma);
+
+    /* Check if the DMA Stream is effectively disabled */
+    while((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U)
+    {
+      /* Check for the Timeout */
+      if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
+      {
+        /* Update error code */
+        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+
+        /* Change the DMA state */
+        hdma->State = HAL_DMA_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+    }
+
+    /* Get the CR register value */
+    registerValue = ((DMA_Stream_TypeDef   *)hdma->Instance)->CR;
+
+    /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
+    registerValue &= ((uint32_t)~(DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
+                        DMA_SxCR_PL    | DMA_SxCR_MSIZE  | DMA_SxCR_PSIZE  | \
+                        DMA_SxCR_MINC  | DMA_SxCR_PINC   | DMA_SxCR_CIRC   | \
+                        DMA_SxCR_DIR   | DMA_SxCR_CT     | DMA_SxCR_DBM));
+
+    /* Prepare the DMA Stream configuration */
+    registerValue |=  hdma->Init.Direction           |
+            hdma->Init.PeriphInc           | hdma->Init.MemInc           |
+            hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
+            hdma->Init.Mode                | hdma->Init.Priority;
+
+    /* the Memory burst and peripheral burst are not used when the FIFO is disabled */
+    if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
+    {
+      /* Get memory burst and peripheral burst */
+      registerValue |=  hdma->Init.MemBurst | hdma->Init.PeriphBurst;
+    }
+
+    /* Work around for Errata 2.22: UART/USART- DMA transfer lock: DMA stream could be
+                                    lock when transfering data to/from USART/UART */
+#if (STM32H7_DEV_ID == 0x450UL)
+    if((DBGMCU->IDCODE & 0xFFFF0000U) >= 0x20000000U)
+    {
+#endif /* STM32H7_DEV_ID == 0x450UL */
+      if(IS_DMA_UART_USART_REQUEST(hdma->Init.Request) != 0U)
+      {
+        registerValue |= DMA_SxCR_TRBUFF;
+      }
+#if (STM32H7_DEV_ID == 0x450UL)
+    }
+#endif /* STM32H7_DEV_ID == 0x450UL */
+
+    /* Write to DMA Stream CR register */
+    ((DMA_Stream_TypeDef   *)hdma->Instance)->CR = registerValue;
+
+    /* Get the FCR register value */
+    registerValue = ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR;
+
+    /* Clear Direct mode and FIFO threshold bits */
+    registerValue &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
+
+    /* Prepare the DMA Stream FIFO configuration */
+    registerValue |= hdma->Init.FIFOMode;
+
+    /* the FIFO threshold is not used when the FIFO mode is disabled */
+    if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
+    {
+      /* Get the FIFO threshold */
+      registerValue |= hdma->Init.FIFOThreshold;
+
+      /* Check compatibility between FIFO threshold level and size of the memory burst */
+      /* for INCR4, INCR8, INCR16 */
+      if(hdma->Init.MemBurst != DMA_MBURST_SINGLE)
+      {
+        if (DMA_CheckFifoParam(hdma) != HAL_OK)
+        {
+          /* Update error code */
+          hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
+
+          /* Change the DMA state */
+          hdma->State = HAL_DMA_STATE_READY;
+
+          return HAL_ERROR;
+        }
+      }
+    }
+
+    /* Write to DMA Stream FCR */
+    ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR = registerValue;
+
+    /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
+       DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
+    regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
+
+    /* Clear all interrupt flags */
+    regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
+  }
+  else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */
+  {
+    if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U)
+    {
+      /* Check the request parameter */
+      assert_param(IS_BDMA_REQUEST(hdma->Init.Request));
+    }
+
+    /* Allocate lock resource */
+    __HAL_UNLOCK(hdma);
+
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+
+    /* Get the CR register value */
+    registerValue = ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR;
+
+    /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, MEM2MEM, DBM and CT bits */
+    registerValue &= ((uint32_t)~(BDMA_CCR_PL    | BDMA_CCR_MSIZE   | BDMA_CCR_PSIZE  | \
+                                  BDMA_CCR_MINC  | BDMA_CCR_PINC    | BDMA_CCR_CIRC   | \
+                                  BDMA_CCR_DIR   | BDMA_CCR_MEM2MEM | BDMA_CCR_DBM    | \
+                                  BDMA_CCR_CT));
+
+    /* Prepare the DMA Channel configuration */
+    registerValue |=  DMA_TO_BDMA_DIRECTION(hdma->Init.Direction)            |
+                      DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc)       |
+                      DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc)              |
+                      DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) |
+                      DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment)    |
+                      DMA_TO_BDMA_MODE(hdma->Init.Mode)                      |
+                      DMA_TO_BDMA_PRIORITY(hdma->Init.Priority);
+
+    /* Write to DMA Channel CR register */
+    ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR = registerValue;
+
+    /* calculation of the channel index */
+    hdma->StreamIndex = (((uint32_t)((uint32_t*)hdma->Instance) - (uint32_t)BDMA_Channel0) / ((uint32_t)BDMA_Channel1 - (uint32_t)BDMA_Channel0)) << 2U;
+
+    /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
+    DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
+    regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
+
+    /* Clear all interrupt flags */
+    regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
+  }
+  else
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
+    hdma->State     = HAL_DMA_STATE_ERROR;
+
+    return HAL_ERROR;
+  }
+
+  if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+  {
+    /* Initialize parameters for DMAMUX channel :
+    DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask
+    */
+    DMA_CalcDMAMUXChannelBaseAndMask(hdma);
+
+    if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
+    {
+      /* if memory to memory force the request to 0*/
+      hdma->Init.Request = DMA_REQUEST_MEM2MEM;
+    }
+
+    /* Set peripheral request  to DMAMUX channel */
+    hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);
+
+    /* Clear the DMAMUX synchro overrun flag */
+    hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+    /* Initialize parameters for DMAMUX request generator :
+    if the DMA request is DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR7
+    */
+    if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7))
+    {
+      /* Initialize parameters for DMAMUX request generator :
+      DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */
+      DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
+
+      /* Reset the DMAMUX request generator register */
+      hdma->DMAmuxRequestGen->RGCR = 0U;
+
+      /* Clear the DMAMUX request generator overrun flag */
+      hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+    }
+    else
+    {
+      hdma->DMAmuxRequestGen = 0U;
+      hdma->DMAmuxRequestGenStatus = 0U;
+      hdma->DMAmuxRequestGenStatusMask = 0U;
+    }
+  }
+
+  /* Initialize the error code */
+  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+  /* Initialize the DMA state */
+  hdma->State = HAL_DMA_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the DMA peripheral
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
+{
+  DMA_Base_Registers *regs_dma;
+  BDMA_Base_Registers *regs_bdma;
+
+  /* Check the DMA peripheral handle */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Disable the selected DMA Streamx */
+  __HAL_DMA_DISABLE(hdma);
+
+  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+  {
+    /* Reset DMA Streamx control register */
+    ((DMA_Stream_TypeDef   *)hdma->Instance)->CR   = 0U;
+
+    /* Reset DMA Streamx number of data to transfer register */
+    ((DMA_Stream_TypeDef   *)hdma->Instance)->NDTR = 0U;
+
+    /* Reset DMA Streamx peripheral address register */
+    ((DMA_Stream_TypeDef   *)hdma->Instance)->PAR  = 0U;
+
+    /* Reset DMA Streamx memory 0 address register */
+    ((DMA_Stream_TypeDef   *)hdma->Instance)->M0AR = 0U;
+
+    /* Reset DMA Streamx memory 1 address register */
+    ((DMA_Stream_TypeDef   *)hdma->Instance)->M1AR = 0U;
+
+    /* Reset DMA Streamx FIFO control register */
+    ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR  = (uint32_t)0x00000021U;
+
+    /* Get DMA steam Base Address */
+    regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
+
+    /* Clear all interrupt flags at correct offset within the register */
+    regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
+  }
+  else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */
+  {
+    /* Reset DMA Channel control register */
+    ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR  = 0U;
+
+    /* Reset DMA Channel Number of Data to Transfer register */
+    ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = 0U;
+
+    /* Reset DMA Channel peripheral address register */
+    ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR  = 0U;
+
+    /* Reset DMA Channel memory 0 address register */
+    ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = 0U;
+
+    /* Reset DMA Channel memory 1 address register */
+    ((BDMA_Channel_TypeDef *)hdma->Instance)->CM1AR = 0U;
+
+    /* Get DMA steam Base Address */
+    regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
+
+    /* Clear all interrupt flags at correct offset within the register */
+    regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
+  }
+  else
+  {
+    /* Return error status */
+    return HAL_ERROR;
+  }
+
+  if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+  {
+    /* Initialize parameters for DMAMUX channel :
+    DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */
+    DMA_CalcDMAMUXChannelBaseAndMask(hdma);
+
+    if(hdma->DMAmuxChannel != 0U)
+    {
+      /* Resett he DMAMUX channel that corresponds to the DMA stream */
+      hdma->DMAmuxChannel->CCR = 0U;
+
+      /* Clear the DMAMUX synchro overrun flag */
+      hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+    }
+
+    if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7))
+    {
+      /* Initialize parameters for DMAMUX request generator :
+      DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */
+      DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
+
+      /* Reset the DMAMUX request generator register */
+      hdma->DMAmuxRequestGen->RGCR = 0U;
+
+      /* Clear the DMAMUX request generator overrun flag */
+      hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+    }
+
+    hdma->DMAmuxRequestGen = 0U;
+    hdma->DMAmuxRequestGenStatus = 0U;
+    hdma->DMAmuxRequestGenStatusMask = 0U;
+  }
+
+
+  /* Clean callbacks */
+  hdma->XferCpltCallback       = NULL;
+  hdma->XferHalfCpltCallback   = NULL;
+  hdma->XferM1CpltCallback     = NULL;
+  hdma->XferM1HalfCpltCallback = NULL;
+  hdma->XferErrorCallback      = NULL;
+  hdma->XferAbortCallback      = NULL;
+
+  /* Initialize the error code */
+  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+  /* Initialize the DMA state */
+  hdma->State = HAL_DMA_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdma);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group2
+  *
+@verbatim
+ ===============================================================================
+                      #####  IO operation functions  #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure the source, destination address and data length and Start DMA transfer
+      (+) Configure the source, destination address and data length and
+          Start DMA transfer with interrupt
+      (+) Register and Unregister DMA callbacks
+      (+) Abort DMA transfer
+      (+) Poll for transfer complete
+      (+) Handle DMA interrupt request
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the DMA Transfer.
+  * @param  hdma      : pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @param  SrcAddress: The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  DataLength: The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+  /* Check the DMA peripheral handle */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hdma);
+
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+
+    /* Initialize the error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+    /* Disable the peripheral */
+    __HAL_DMA_DISABLE(hdma);
+
+    /* Configure the source, destination address and the data length */
+    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+    /* Enable the Peripheral */
+    __HAL_DMA_ENABLE(hdma);
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hdma);
+
+    /* Set the error code to busy */
+    hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  return status;
+}
+
+/**
+  * @brief  Start the DMA Transfer with interrupt enabled.
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @param  SrcAddress: The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  DataLength: The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+  /* Check the DMA peripheral handle */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hdma);
+
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+
+    /* Initialize the error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+    /* Disable the peripheral */
+    __HAL_DMA_DISABLE(hdma);
+
+    /* Configure the source, destination address and the data length */
+    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+    {
+      /* Enable Common interrupts*/
+      MODIFY_REG(((DMA_Stream_TypeDef   *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME));
+
+      if(hdma->XferHalfCpltCallback != NULL)
+      {
+        /* Enable Half Transfer IT if corresponding Callback is set */
+        ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  |= DMA_IT_HT;
+      }
+    }
+    else /* BDMA channel */
+    {
+      /* Enable Common interrupts */
+      MODIFY_REG(((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR, (BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE), (BDMA_CCR_TCIE | BDMA_CCR_TEIE));
+
+      if(hdma->XferHalfCpltCallback != NULL)
+      {
+        /*Enable Half Transfer IT if corresponding Callback is set */
+        ((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR  |= BDMA_CCR_HTIE;
+      }
+    }
+
+    if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+    {
+      /* Check if DMAMUX Synchronization is enabled */
+      if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
+      {
+        /* Enable DMAMUX sync overrun IT*/
+        hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
+      }
+
+      if(hdma->DMAmuxRequestGen != 0U)
+      {
+        /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
+        /* enable the request gen overrun IT */
+        hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
+      }
+    }
+
+    /* Enable the Peripheral */
+    __HAL_DMA_ENABLE(hdma);
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hdma);
+
+    /* Set the error code to busy */
+    hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Aborts the DMA Transfer.
+  * @param  hdma  : pointer to a DMA_HandleTypeDef structure that contains
+  *                 the configuration information for the specified DMA Stream.
+  *
+  * @note  After disabling a DMA Stream, a check for wait until the DMA Stream is
+  *        effectively disabled is added. If a Stream is disabled
+  *        while a data transfer is ongoing, the current data will be transferred
+  *        and the Stream will be effectively disabled only after the transfer of
+  *        this single data is finished.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
+{
+  /* calculate DMA base and stream number */
+  DMA_Base_Registers *regs_dma;
+  BDMA_Base_Registers *regs_bdma;
+  const __IO uint32_t *enableRegister;
+
+  uint32_t tickstart = HAL_GetTick();
+
+ /* Check the DMA peripheral handle */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the DMA peripheral state */
+  if(hdma->State != HAL_DMA_STATE_BUSY)
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Disable all the transfer interrupts */
+    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+    {
+       /* Disable DMA All Interrupts  */
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT);
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR &= ~(DMA_IT_FE);
+
+      enableRegister = (__IO uint32_t *)(&(((DMA_Stream_TypeDef   *)hdma->Instance)->CR));
+    }
+    else /* BDMA channel */
+    {
+      /* Disable DMA All Interrupts */
+      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR  &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE);
+
+      enableRegister = (__IO uint32_t *)(&(((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR));
+    }
+
+    if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+    {
+      /* disable the DMAMUX sync overrun IT */
+      hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
+    }
+
+    /* Disable the stream */
+    __HAL_DMA_DISABLE(hdma);
+
+    /* Check if the DMA Stream is effectively disabled */
+    while(((*enableRegister) & DMA_SxCR_EN) != 0U)
+    {
+      /* Check for the Timeout */
+      if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
+      {
+        /* Update error code */
+        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdma);
+
+        /* Change the DMA state */
+        hdma->State = HAL_DMA_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+    }
+
+    /* Clear all interrupt flags at correct offset within the register */
+    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+    {
+      regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+      regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
+    }
+    else /* BDMA channel */
+    {
+      regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
+      regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
+    }
+
+    if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+    {
+      /* Clear the DMAMUX synchro overrun flag */
+      hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+      if(hdma->DMAmuxRequestGen != 0U)
+      {
+        /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT */
+        /* disable the request gen overrun IT */
+        hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
+
+        /* Clear the DMAMUX request generator overrun flag */
+        hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+      }
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+
+    /* Change the DMA state */
+    hdma->State = HAL_DMA_STATE_READY;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Aborts the DMA Transfer in Interrupt mode.
+  * @param  hdma  : pointer to a DMA_HandleTypeDef structure that contains
+  *                 the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
+{
+  BDMA_Base_Registers *regs_bdma;
+
+  /* Check the DMA peripheral handle */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if(hdma->State != HAL_DMA_STATE_BUSY)
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+    return HAL_ERROR;
+  }
+  else
+  {
+    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+    {
+      /* Set Abort State  */
+      hdma->State = HAL_DMA_STATE_ABORT;
+
+      /* Disable the stream */
+      __HAL_DMA_DISABLE(hdma);
+    }
+    else /* BDMA channel */
+    {
+      /* Disable DMA All Interrupts  */
+      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR  &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE);
+
+      /* Disable the channel */
+      __HAL_DMA_DISABLE(hdma);
+
+      if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+      {
+        /* disable the DMAMUX sync overrun IT */
+        hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
+
+        /* Clear all flags */
+        regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
+        regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
+
+        /* Clear the DMAMUX synchro overrun flag */
+        hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+        if(hdma->DMAmuxRequestGen != 0U)
+        {
+          /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
+          /* disable the request gen overrun IT */
+          hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
+
+          /* Clear the DMAMUX request generator overrun flag */
+          hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+        }
+      }
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma);
+
+      /* Change the DMA state */
+      hdma->State = HAL_DMA_STATE_READY;
+
+      /* Call User Abort callback */
+      if(hdma->XferAbortCallback != NULL)
+      {
+        hdma->XferAbortCallback(hdma);
+      }
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Polling for transfer complete.
+  * @param  hdma:          pointer to a DMA_HandleTypeDef structure that contains
+  *                        the configuration information for the specified DMA Stream.
+  * @param  CompleteLevel: Specifies the DMA level complete.
+  * @note   The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead.
+  *         This model could be used for debug purpose.
+  * @note   The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode).
+  * @param  Timeout:       Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t cpltlevel_mask;
+  uint32_t tickstart = HAL_GetTick();
+
+  /* IT status register */
+  __IO uint32_t *isr_reg;
+  /* IT clear flag register */
+  __IO uint32_t *ifcr_reg;
+
+  /* Check the DMA peripheral handle */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if(HAL_DMA_STATE_BUSY != hdma->State)
+  {
+    /* No transfer ongoing */
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+    __HAL_UNLOCK(hdma);
+
+    return HAL_ERROR;
+  }
+
+  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+  {
+    /* Polling mode not supported in circular mode and double buffering mode */
+    if ((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CIRC) != 0U)
+    {
+      hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+      return HAL_ERROR;
+    }
+
+    /* Get the level transfer complete flag */
+    if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
+    {
+      /* Transfer Complete flag */
+      cpltlevel_mask = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU);
+    }
+    else
+    {
+      /* Half Transfer Complete flag */
+      cpltlevel_mask = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU);
+    }
+
+    isr_reg  = &(((DMA_Base_Registers *)hdma->StreamBaseAddress)->ISR);
+    ifcr_reg = &(((DMA_Base_Registers *)hdma->StreamBaseAddress)->IFCR);
+  }
+  else /* BDMA channel */
+  {
+    /* Polling mode not supported in circular mode */
+    if ((((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR & BDMA_CCR_CIRC) != 0U)
+    {
+      hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+      return HAL_ERROR;
+    }
+
+    /* Get the level transfer complete flag */
+    if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
+    {
+      /* Transfer Complete flag */
+      cpltlevel_mask = BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU);
+    }
+    else
+    {
+      /* Half Transfer Complete flag */
+      cpltlevel_mask = BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU);
+    }
+
+    isr_reg  = &(((BDMA_Base_Registers *)hdma->StreamBaseAddress)->ISR);
+    ifcr_reg = &(((BDMA_Base_Registers *)hdma->StreamBaseAddress)->IFCR);
+  }
+
+  while(((*isr_reg) & cpltlevel_mask) == 0U)
+  {
+    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+    {
+      if(((*isr_reg) & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
+      {
+        /* Update error code */
+        hdma->ErrorCode |= HAL_DMA_ERROR_FE;
+
+        /* Clear the FIFO error flag */
+        (*ifcr_reg) = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU);
+      }
+
+      if(((*isr_reg) & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
+      {
+        /* Update error code */
+        hdma->ErrorCode |= HAL_DMA_ERROR_DME;
+
+        /* Clear the Direct Mode error flag */
+        (*ifcr_reg) = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU);
+      }
+
+      if(((*isr_reg) & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
+      {
+        /* Update error code */
+        hdma->ErrorCode |= HAL_DMA_ERROR_TE;
+
+        /* Clear the transfer error flag */
+        (*ifcr_reg) = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU);
+
+        /* Change the DMA state */
+        hdma->State = HAL_DMA_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdma);
+
+        return HAL_ERROR;
+      }
+    }
+    else /* BDMA channel */
+    {
+      if(((*isr_reg) & (BDMA_FLAG_TE0 << (hdma->StreamIndex & 0x1FU))) != 0U)
+      {
+        /* When a DMA transfer error occurs */
+        /* A hardware clear of its EN bits is performed */
+        /* Clear all flags */
+        (*isr_reg) = ((BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU));
+
+        /* Update error code */
+        hdma->ErrorCode = HAL_DMA_ERROR_TE;
+
+        /* Change the DMA state */
+        hdma->State = HAL_DMA_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdma);
+
+        return HAL_ERROR;
+      }
+    }
+
+    /* Check for the Timeout (Not applicable in circular mode)*/
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
+      {
+        /* Update error code */
+        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+
+        /* if timeout then abort the current transfer */
+        /* No need to check return value: as in this case we will return HAL_ERROR with HAL_DMA_ERROR_TIMEOUT error code  */
+        (void) HAL_DMA_Abort(hdma);
+          /*
+            Note that the Abort function will
+              - Clear the transfer error flags
+              - Unlock
+              - Set the State
+          */
+
+        return HAL_ERROR;
+      }
+    }
+
+    if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+    {
+      /* Check for DMAMUX Request generator (if used) overrun status */
+      if(hdma->DMAmuxRequestGen != 0U)
+      {
+        /* if using DMAMUX request generator Check for DMAMUX request generator overrun */
+        if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
+        {
+          /* Clear the DMAMUX request generator overrun flag */
+          hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+
+          /* Update error code */
+          hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
+        }
+      }
+
+      /* Check for DMAMUX Synchronization overrun */
+      if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
+      {
+        /* Clear the DMAMUX synchro overrun flag */
+        hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+        /* Update error code */
+        hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
+      }
+    }
+  }
+
+
+  /* Get the level transfer complete flag */
+  if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
+  {
+    /* Clear the half transfer and transfer complete flags */
+    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+    {
+      (*ifcr_reg) = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << (hdma->StreamIndex & 0x1FU);
+    }
+    else /* BDMA channel */
+    {
+      (*ifcr_reg) = (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU));
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+
+    hdma->State = HAL_DMA_STATE_READY;
+  }
+  else /*CompleteLevel = HAL_DMA_HALF_TRANSFER*/
+  {
+    /* Clear the half transfer and transfer complete flags */
+    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+    {
+      (*ifcr_reg) = (DMA_FLAG_HTIF0_4) << (hdma->StreamIndex & 0x1FU);
+    }
+    else /* BDMA channel */
+    {
+      (*ifcr_reg) = (BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU));
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Handles DMA interrupt request.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Stream.
+  * @retval None
+  */
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
+{
+  uint32_t tmpisr_dma, tmpisr_bdma;
+  uint32_t ccr_reg;
+  __IO uint32_t count = 0U;
+  uint32_t timeout = SystemCoreClock / 9600U;
+
+  /* calculate DMA base and stream number */
+  DMA_Base_Registers  *regs_dma  = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+  BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
+
+  tmpisr_dma  = regs_dma->ISR;
+  tmpisr_bdma = regs_bdma->ISR;
+
+  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U)  /* DMA1 or DMA2 instance */
+  {
+    /* Transfer Error Interrupt management ***************************************/
+    if ((tmpisr_dma & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
+    {
+      if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != 0U)
+      {
+        /* Disable the transfer error interrupt */
+        ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_TE);
+
+        /* Clear the transfer error flag */
+        regs_dma->IFCR = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU);
+
+        /* Update error code */
+        hdma->ErrorCode |= HAL_DMA_ERROR_TE;
+      }
+    }
+    /* FIFO Error Interrupt management ******************************************/
+    if ((tmpisr_dma & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
+    {
+      if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != 0U)
+      {
+        /* Clear the FIFO error flag */
+        regs_dma->IFCR = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU);
+
+        /* Update error code */
+        hdma->ErrorCode |= HAL_DMA_ERROR_FE;
+      }
+    }
+    /* Direct Mode Error Interrupt management ***********************************/
+    if ((tmpisr_dma & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
+    {
+      if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != 0U)
+      {
+        /* Clear the direct mode error flag */
+        regs_dma->IFCR = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU);
+
+        /* Update error code */
+        hdma->ErrorCode |= HAL_DMA_ERROR_DME;
+      }
+    }
+    /* Half Transfer Complete Interrupt management ******************************/
+    if ((tmpisr_dma & (DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
+    {
+      if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U)
+      {
+        /* Clear the half transfer complete flag */
+        regs_dma->IFCR = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU);
+
+        /* Multi_Buffering mode enabled */
+        if(((((DMA_Stream_TypeDef   *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U)
+        {
+          /* Current memory buffer used is Memory 0 */
+          if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U)
+          {
+            if(hdma->XferHalfCpltCallback != NULL)
+            {
+              /* Half transfer callback */
+              hdma->XferHalfCpltCallback(hdma);
+            }
+          }
+          /* Current memory buffer used is Memory 1 */
+          else
+          {
+            if(hdma->XferM1HalfCpltCallback != NULL)
+            {
+              /* Half transfer callback */
+              hdma->XferM1HalfCpltCallback(hdma);
+            }
+          }
+        }
+        else
+        {
+          /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
+          if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U)
+          {
+            /* Disable the half transfer interrupt */
+            ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_HT);
+          }
+
+          if(hdma->XferHalfCpltCallback != NULL)
+          {
+            /* Half transfer callback */
+            hdma->XferHalfCpltCallback(hdma);
+          }
+        }
+      }
+    }
+    /* Transfer Complete Interrupt management ***********************************/
+    if ((tmpisr_dma & (DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
+    {
+      if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U)
+      {
+        /* Clear the transfer complete flag */
+        regs_dma->IFCR = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU);
+
+        if(HAL_DMA_STATE_ABORT == hdma->State)
+        {
+          /* Disable all the transfer interrupts */
+          ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
+          ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR &= ~(DMA_IT_FE);
+
+          if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
+          {
+            ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_HT);
+          }
+
+          /* Clear all interrupt flags at correct offset within the register */
+          regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hdma);
+
+          /* Change the DMA state */
+          hdma->State = HAL_DMA_STATE_READY;
+
+          if(hdma->XferAbortCallback != NULL)
+          {
+            hdma->XferAbortCallback(hdma);
+          }
+          return;
+        }
+
+        if(((((DMA_Stream_TypeDef   *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U)
+        {
+          /* Current memory buffer used is Memory 0 */
+          if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U)
+          {
+            if(hdma->XferM1CpltCallback != NULL)
+            {
+              /* Transfer complete Callback for memory1 */
+              hdma->XferM1CpltCallback(hdma);
+            }
+          }
+          /* Current memory buffer used is Memory 1 */
+          else
+          {
+            if(hdma->XferCpltCallback != NULL)
+            {
+              /* Transfer complete Callback for memory0 */
+              hdma->XferCpltCallback(hdma);
+            }
+          }
+        }
+        /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
+        else
+        {
+          if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U)
+          {
+            /* Disable the transfer complete interrupt */
+            ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_TC);
+
+            /* Process Unlocked */
+            __HAL_UNLOCK(hdma);
+
+            /* Change the DMA state */
+            hdma->State = HAL_DMA_STATE_READY;
+          }
+
+          if(hdma->XferCpltCallback != NULL)
+          {
+            /* Transfer complete callback */
+            hdma->XferCpltCallback(hdma);
+          }
+        }
+      }
+    }
+
+    /* manage error case */
+    if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
+    {
+      if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != 0U)
+      {
+        hdma->State = HAL_DMA_STATE_ABORT;
+
+        /* Disable the stream */
+        __HAL_DMA_DISABLE(hdma);
+
+        do
+        {
+          if (++count > timeout)
+          {
+            break;
+          }
+        }
+        while((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U);
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdma);
+
+        if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U)
+        {
+          /* Change the DMA state to error if DMA disable fails */
+          hdma->State = HAL_DMA_STATE_ERROR;
+        }
+        else
+        {
+          /* Change the DMA state to Ready if DMA disable success */
+          hdma->State = HAL_DMA_STATE_READY;
+        }
+      }
+
+      if(hdma->XferErrorCallback != NULL)
+      {
+        /* Transfer error callback */
+        hdma->XferErrorCallback(hdma);
+      }
+    }
+  }
+  else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U)  /* BDMA instance(s) */
+  {
+    ccr_reg = (((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR);
+
+    /* Half Transfer Complete Interrupt management ******************************/
+    if (((tmpisr_bdma & (BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_HTIE) != 0U))
+    {
+      /* Clear the half transfer complete flag */
+      regs_bdma->IFCR = (BDMA_ISR_HTIF0 << (hdma->StreamIndex & 0x1FU));
+
+      /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */
+      if((ccr_reg & BDMA_CCR_DBM) != 0U)
+      {
+        /* Current memory buffer used is Memory 0 */
+        if((ccr_reg & BDMA_CCR_CT) == 0U)
+        {
+          if(hdma->XferM1HalfCpltCallback != NULL)
+          {
+            /* Half transfer Callback for Memory 1 */
+            hdma->XferM1HalfCpltCallback(hdma);
+          }
+        }
+        /* Current memory buffer used is Memory 1 */
+        else
+        {
+          if(hdma->XferHalfCpltCallback != NULL)
+          {
+            /* Half transfer Callback for Memory 0 */
+            hdma->XferHalfCpltCallback(hdma);
+          }
+        }
+      }
+      else
+      {
+        if((ccr_reg & BDMA_CCR_CIRC) == 0U)
+        {
+          /* Disable the half transfer interrupt */
+          __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
+        }
+
+        /* DMA peripheral state is not updated in Half Transfer */
+        /* but in Transfer Complete case */
+
+       if(hdma->XferHalfCpltCallback != NULL)
+        {
+          /* Half transfer callback */
+          hdma->XferHalfCpltCallback(hdma);
+        }
+      }
+    }
+
+    /* Transfer Complete Interrupt management ***********************************/
+    else if (((tmpisr_bdma & (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TCIE) != 0U))
+    {
+      /* Clear the transfer complete flag */
+      regs_bdma->IFCR = (BDMA_ISR_TCIF0) << (hdma->StreamIndex & 0x1FU);
+
+      /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */
+      if((ccr_reg & BDMA_CCR_DBM) != 0U)
+      {
+        /* Current memory buffer used is Memory 0 */
+        if((ccr_reg & BDMA_CCR_CT) == 0U)
+        {
+          if(hdma->XferM1CpltCallback != NULL)
+          {
+            /* Transfer complete Callback for Memory 1 */
+            hdma->XferM1CpltCallback(hdma);
+          }
+        }
+        /* Current memory buffer used is Memory 1 */
+        else
+        {
+          if(hdma->XferCpltCallback != NULL)
+          {
+            /* Transfer complete Callback for Memory 0 */
+            hdma->XferCpltCallback(hdma);
+          }
+        }
+      }
+      else
+      {
+        if((ccr_reg & BDMA_CCR_CIRC) == 0U)
+        {
+          /* Disable the transfer complete and error interrupt, if the DMA mode is not CIRCULAR */
+          __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hdma);
+
+          /* Change the DMA state */
+          hdma->State = HAL_DMA_STATE_READY;
+        }
+
+        if(hdma->XferCpltCallback != NULL)
+        {
+          /* Transfer complete callback */
+          hdma->XferCpltCallback(hdma);
+        }
+      }
+    }
+    /* Transfer Error Interrupt management **************************************/
+    else if (((tmpisr_bdma & (BDMA_FLAG_TE0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TEIE) != 0U))
+    {
+      /* When a DMA transfer error occurs */
+      /* A hardware clear of its EN bits is performed */
+      /* Disable ALL DMA IT */
+      __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+
+      /* Clear all flags */
+      regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);
+
+      /* Update error code */
+      hdma->ErrorCode = HAL_DMA_ERROR_TE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma);
+
+      /* Change the DMA state */
+      hdma->State = HAL_DMA_STATE_READY;
+
+      if (hdma->XferErrorCallback != NULL)
+      {
+        /* Transfer error callback */
+        hdma->XferErrorCallback(hdma);
+      }
+    }
+    else
+    {
+      /* Nothing To Do */
+    }
+  }
+  else
+  {
+    /* Nothing To Do */
+  }
+}
+
+/**
+  * @brief  Register callbacks
+  * @param  hdma:                 pointer to a DMA_HandleTypeDef structure that contains
+  *                               the configuration information for the specified DMA Stream.
+  * @param  CallbackID:           User Callback identifier
+  *                               a DMA_HandleTypeDef structure as parameter.
+  * @param  pCallback:            pointer to private callback function which has pointer to
+  *                               a DMA_HandleTypeDef structure as parameter.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))
+{
+
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the DMA peripheral handle */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hdma);
+
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    switch (CallbackID)
+    {
+    case  HAL_DMA_XFER_CPLT_CB_ID:
+      hdma->XferCpltCallback = pCallback;
+      break;
+
+    case  HAL_DMA_XFER_HALFCPLT_CB_ID:
+      hdma->XferHalfCpltCallback = pCallback;
+      break;
+
+    case  HAL_DMA_XFER_M1CPLT_CB_ID:
+      hdma->XferM1CpltCallback = pCallback;
+      break;
+
+    case  HAL_DMA_XFER_M1HALFCPLT_CB_ID:
+      hdma->XferM1HalfCpltCallback = pCallback;
+      break;
+
+    case  HAL_DMA_XFER_ERROR_CB_ID:
+      hdma->XferErrorCallback = pCallback;
+      break;
+
+    case  HAL_DMA_XFER_ABORT_CB_ID:
+      hdma->XferAbortCallback = pCallback;
+      break;
+
+    default:
+      break;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdma);
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister callbacks
+  * @param  hdma:                 pointer to a DMA_HandleTypeDef structure that contains
+  *                               the configuration information for the specified DMA Stream.
+  * @param  CallbackID:           User Callback identifier
+  *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the DMA peripheral handle */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hdma);
+
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    switch (CallbackID)
+    {
+    case  HAL_DMA_XFER_CPLT_CB_ID:
+      hdma->XferCpltCallback = NULL;
+      break;
+
+    case  HAL_DMA_XFER_HALFCPLT_CB_ID:
+      hdma->XferHalfCpltCallback = NULL;
+      break;
+
+    case  HAL_DMA_XFER_M1CPLT_CB_ID:
+      hdma->XferM1CpltCallback = NULL;
+      break;
+
+    case  HAL_DMA_XFER_M1HALFCPLT_CB_ID:
+      hdma->XferM1HalfCpltCallback = NULL;
+      break;
+
+    case  HAL_DMA_XFER_ERROR_CB_ID:
+      hdma->XferErrorCallback = NULL;
+      break;
+
+    case  HAL_DMA_XFER_ABORT_CB_ID:
+      hdma->XferAbortCallback = NULL;
+      break;
+
+    case   HAL_DMA_XFER_ALL_CB_ID:
+      hdma->XferCpltCallback = NULL;
+      hdma->XferHalfCpltCallback = NULL;
+      hdma->XferM1CpltCallback = NULL;
+      hdma->XferM1HalfCpltCallback = NULL;
+      hdma->XferErrorCallback = NULL;
+      hdma->XferAbortCallback = NULL;
+      break;
+
+    default:
+      status = HAL_ERROR;
+      break;
+    }
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdma);
+
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group3
+  *
+@verbatim
+ ===============================================================================
+                    ##### State and Errors functions #####
+ ===============================================================================
+    [..]
+    This subsection provides functions allowing to
+      (+) Check the DMA state
+      (+) Get error code
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the DMA state.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Stream.
+  * @retval HAL state
+  */
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
+{
+  return hdma->State;
+}
+
+/**
+  * @brief  Return the DMA error code
+  * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA Stream.
+  * @retval DMA Error Code
+  */
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
+{
+  return hdma->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMA_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Sets the DMA Transfer parameter.
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @param  SrcAddress: The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  DataLength: The length of data to be transferred from source to destination
+  * @retval None
+  */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+  /* calculate DMA base and stream number */
+  DMA_Base_Registers  *regs_dma  = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+  BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
+
+  if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+  {
+    /* Clear the DMAMUX synchro overrun flag */
+    hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+    if(hdma->DMAmuxRequestGen != 0U)
+    {
+      /* Clear the DMAMUX request generator overrun flag */
+      hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+    }
+  }
+
+  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+  {
+    /* Clear all interrupt flags at correct offset within the register */
+    regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
+
+    /* Clear DBM bit */
+    ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= (uint32_t)(~DMA_SxCR_DBM);
+
+    /* Configure DMA Stream data length */
+    ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = DataLength;
+
+    /* Peripheral to Memory */
+    if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+    {
+      /* Configure DMA Stream destination address */
+      ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = DstAddress;
+
+      /* Configure DMA Stream source address */
+      ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = SrcAddress;
+    }
+    /* Memory to Peripheral */
+    else
+    {
+      /* Configure DMA Stream source address */
+      ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = SrcAddress;
+
+      /* Configure DMA Stream destination address */
+      ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = DstAddress;
+    }
+  }
+  else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */
+  {
+    /* Clear all flags */
+    regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);
+
+    /* Configure DMA Channel data length */
+    ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = DataLength;
+
+    /* Peripheral to Memory */
+    if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+    {
+      /* Configure DMA Channel destination address */
+      ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = DstAddress;
+
+      /* Configure DMA Channel source address */
+      ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = SrcAddress;
+    }
+    /* Memory to Peripheral */
+    else
+    {
+      /* Configure DMA Channel source address */
+      ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = SrcAddress;
+
+      /* Configure DMA Channel destination address */
+      ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = DstAddress;
+    }
+  }
+  else
+  {
+    /* Nothing To Do */
+  }
+}
+
+/**
+  * @brief  Returns the DMA Stream base address depending on stream number
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @retval Stream base address
+  */
+static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
+{
+  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+  {
+    uint32_t stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U;
+
+    /* lookup table for necessary bitshift of flags within status registers */
+    static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};
+    hdma->StreamIndex = flagBitshiftOffset[stream_number & 0x7U];
+
+    if (stream_number > 3U)
+    {
+      /* return pointer to HISR and HIFCR */
+      hdma->StreamBaseAddress = (((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)) + 4U);
+    }
+    else
+    {
+      /* return pointer to LISR and LIFCR */
+      hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU));
+    }
+  }
+  else /* BDMA instance(s) */
+  {
+    /* return pointer to ISR and IFCR */
+    hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0xFFU));
+  }
+
+  return hdma->StreamBaseAddress;
+}
+
+/**
+  * @brief  Check compatibility between FIFO threshold level and size of the memory burst
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Memory Data size equal to Byte */
+  if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)
+  {
+    switch (hdma->Init.FIFOThreshold)
+    {
+      case DMA_FIFO_THRESHOLD_1QUARTERFULL:
+      case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
+
+        if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+        {
+          status = HAL_ERROR;
+        }
+        break;
+
+      case DMA_FIFO_THRESHOLD_HALFFULL:
+        if (hdma->Init.MemBurst == DMA_MBURST_INC16)
+        {
+          status = HAL_ERROR;
+        }
+        break;
+
+      case DMA_FIFO_THRESHOLD_FULL:
+        break;
+
+      default:
+        break;
+    }
+  }
+
+  /* Memory Data size equal to Half-Word */
+  else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
+  {
+    switch (hdma->Init.FIFOThreshold)
+    {
+      case DMA_FIFO_THRESHOLD_1QUARTERFULL:
+      case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
+        status = HAL_ERROR;
+        break;
+
+      case DMA_FIFO_THRESHOLD_HALFFULL:
+        if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+        {
+          status = HAL_ERROR;
+        }
+        break;
+
+      case DMA_FIFO_THRESHOLD_FULL:
+        if (hdma->Init.MemBurst == DMA_MBURST_INC16)
+        {
+          status = HAL_ERROR;
+        }
+        break;
+
+      default:
+        break;
+    }
+  }
+
+  /* Memory Data size equal to Word */
+  else
+  {
+    switch (hdma->Init.FIFOThreshold)
+    {
+      case DMA_FIFO_THRESHOLD_1QUARTERFULL:
+      case DMA_FIFO_THRESHOLD_HALFFULL:
+      case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
+        status = HAL_ERROR;
+        break;
+
+      case DMA_FIFO_THRESHOLD_FULL:
+        if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+        {
+          status = HAL_ERROR;
+        }
+    break;
+
+      default:
+        break;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Updates the DMA handle with the DMAMUX  channel and status mask depending on stream number
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)
+{
+  uint32_t stream_number;
+  uint32_t stream_baseaddress = (uint32_t)((uint32_t*)hdma->Instance);
+
+  if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U)
+  {
+    /* BDMA Channels are connected to DMAMUX2 channels */
+    stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 8U) / 20U;
+    hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_Channel0) + (stream_number * 4U)));
+    hdma->DMAmuxChannelStatus = DMAMUX2_ChannelStatus;
+    hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU);
+  }
+  else
+  {
+    /* DMA1/DMA2 Streams are connected to DMAMUX1 channels */
+    stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U;
+
+    if((stream_baseaddress <= ((uint32_t)DMA2_Stream7) ) && \
+       (stream_baseaddress >= ((uint32_t)DMA2_Stream0)))
+    {
+      stream_number += 8U;
+    }
+    hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U)));
+    hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
+    hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU);
+  }
+}
+
+/**
+  * @brief  Updates the DMA handle with the DMAMUX  request generator params
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma)
+{
+  uint32_t request =  hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID;
+
+  if((request >= DMA_REQUEST_GENERATOR0) && (request <= DMA_REQUEST_GENERATOR7))
+  {
+    if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U)
+    {
+      /* BDMA Channels are connected to DMAMUX2 request generator blocks */
+      hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_RequestGenerator0) + ((request - 1U) * 4U)));
+
+      hdma->DMAmuxRequestGenStatus = DMAMUX2_RequestGenStatus;
+    }
+    else
+    {
+      /* DMA1 and DMA2 Streams use DMAMUX1 request generator blocks */
+      hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U)));
+
+      hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
+    }
+
+    hdma->DMAmuxRequestGenStatusMask = 1UL << (request - 1U);
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c
new file mode 100644
index 00000000..6a48d942
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c
@@ -0,0 +1,714 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_dma_ex.c
+  * @author  MCD Application Team
+  * @brief   DMA Extension HAL module driver
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the DMA Extension peripheral:
+  *           + Extended features functions
+  *
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+  The DMA Extension HAL driver can be used as follows:
+   (+) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function
+       for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.
+
+   (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
+   (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
+       Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
+       to respectively enable/disable the request generator.
+
+   (+) To handle the DMAMUX Interrupts, the function  HAL_DMAEx_MUX_IRQHandler should be called from
+       the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler or DMAMUX2_OVR_IRQHandler .
+       As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMA_MUX_IRQHandler should be
+       called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project
+      (exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator)
+
+     -@-  In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.
+     -@-  When Multi (Double) Buffer mode is enabled, the transfer is circular by default.
+     -@-  In Multi (Double) buffer mode, it is possible to update the base address for
+          the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.
+     -@-  Multi (Double) buffer mode is possible with DMA and BDMA instances.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup DMAEx DMAEx
+  * @brief DMA Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private Constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup DMAEx_Private_Functions
+  * @{
+  */
+
+static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+
+/**
+  * @}
+  */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @addtogroup DMAEx_Exported_Functions
+  * @{
+  */
+
+
+/** @addtogroup DMAEx_Exported_Functions_Group1
+  *
+@verbatim
+ ===============================================================================
+                #####  Extended features functions  #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure the source, destination address and data length and
+          Start MultiBuffer DMA transfer
+      (+) Configure the source, destination address and data length and
+          Start MultiBuffer DMA transfer with interrupt
+      (+) Change on the fly the memory0 or memory1 address.
+      (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
+      (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
+      (+) Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
+          to respectively enable/disable the request generator.
+      (+) Handle DMAMUX interrupts using HAL_DMAEx_MUX_IRQHandler : should be called from
+          the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler or DMAMUX2_OVR_IRQHandler
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Starts the multi_buffer DMA Transfer.
+  * @param  hdma      : pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @param  SrcAddress: The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer
+  * @param  DataLength: The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  __IO uint32_t *ifcRegister_Base; /* DMA Stream Interrupt Clear register */
+
+  /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+
+  /* Memory-to-memory transfer not supported in double buffering mode */
+  if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Process Locked */
+    __HAL_LOCK(hdma);
+
+    if(HAL_DMA_STATE_READY == hdma->State)
+    {
+      /* Change DMA peripheral state */
+      hdma->State = HAL_DMA_STATE_BUSY;
+
+      /* Initialize the error code */
+      hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+      if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+      {
+        /* Enable the Double buffer mode */
+        ((DMA_Stream_TypeDef   *)hdma->Instance)->CR |= DMA_SxCR_DBM;
+
+        /* Configure DMA Stream destination address */
+        ((DMA_Stream_TypeDef   *)hdma->Instance)->M1AR = SecondMemAddress;
+
+        /* Calculate the interrupt clear flag register (IFCR) base address  */
+        ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 8U));
+
+        /* Clear all flags */
+        *ifcRegister_Base = 0x3FUL << (hdma->StreamIndex & 0x1FU);
+      }
+      else /* BDMA instance(s) */
+      {
+        /* Enable the Double buffer mode */
+        ((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR |= (BDMA_CCR_DBM | BDMA_CCR_CIRC);
+
+        /* Configure DMA Stream destination address */
+        ((BDMA_Channel_TypeDef   *)hdma->Instance)->CM1AR = SecondMemAddress;
+
+        /* Calculate the interrupt clear flag register (IFCR) base address  */
+        ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 4U));
+
+        /* Clear all flags */
+        *ifcRegister_Base = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);
+      }
+
+      if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+      {
+        /* Configure the source, destination address and the data length */
+        DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+        /* Clear the DMAMUX synchro overrun flag */
+        hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+        if(hdma->DMAmuxRequestGen != 0U)
+        {
+          /* Clear the DMAMUX request generator overrun flag */
+          hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+        }
+      }
+
+      /* Enable the peripheral */
+      __HAL_DMA_ENABLE(hdma);
+    }
+    else
+    {
+      /* Set the error code to busy */
+      hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+      /* Return error status */
+      status = HAL_ERROR;
+    }
+  }
+  return status;
+}
+
+/**
+  * @brief  Starts the multi_buffer DMA Transfer with interrupt enabled.
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @param  SrcAddress: The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer
+  * @param  DataLength: The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  __IO uint32_t *ifcRegister_Base; /* DMA Stream Interrupt Clear register */
+
+  /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+
+  /* Memory-to-memory transfer not supported in double buffering mode */
+  if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hdma);
+
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+
+    /* Initialize the error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+    {
+      /* Enable the Double buffer mode */
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->CR |= DMA_SxCR_DBM;
+
+      /* Configure DMA Stream destination address */
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->M1AR = SecondMemAddress;
+
+      /* Calculate the interrupt clear flag register (IFCR) base address  */
+      ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 8U));
+
+      /* Clear all flags */
+      *ifcRegister_Base = 0x3FUL << (hdma->StreamIndex & 0x1FU);
+    }
+    else /* BDMA instance(s) */
+    {
+      /* Enable the Double buffer mode */
+      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR |= (BDMA_CCR_DBM | BDMA_CCR_CIRC);
+
+      /* Configure DMA Stream destination address */
+      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CM1AR = SecondMemAddress;
+
+      /* Calculate the interrupt clear flag register (IFCR) base address  */
+      ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 4U));
+
+      /* Clear all flags */
+      *ifcRegister_Base = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);
+    }
+
+    /* Configure the source, destination address and the data length */
+    DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+    if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+    {
+      /* Clear the DMAMUX synchro overrun flag */
+      hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+      if(hdma->DMAmuxRequestGen != 0U)
+      {
+        /* Clear the DMAMUX request generator overrun flag */
+        hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+      }
+    }
+
+    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+    {
+      /* Enable Common interrupts*/
+      MODIFY_REG(((DMA_Stream_TypeDef   *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME));
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR |= DMA_IT_FE;
+
+      if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
+      {
+        /*Enable Half Transfer IT if corresponding Callback is set*/
+        ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  |= DMA_IT_HT;
+      }
+    }
+    else /* BDMA instance(s) */
+    {
+      /* Enable Common interrupts*/
+      MODIFY_REG(((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR, (BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE), (BDMA_CCR_TCIE | BDMA_CCR_TEIE));
+
+      if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
+      {
+        /*Enable Half Transfer IT if corresponding Callback is set*/
+        ((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR  |= BDMA_CCR_HTIE;
+      }
+    }
+
+    if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+    {
+      /* Check if DMAMUX Synchronization is enabled*/
+      if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
+      {
+        /* Enable DMAMUX sync overrun IT*/
+        hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
+      }
+
+      if(hdma->DMAmuxRequestGen != 0U)
+      {
+        /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
+        /* enable the request gen overrun IT*/
+        hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
+      }
+    }
+
+    /* Enable the peripheral */
+    __HAL_DMA_ENABLE(hdma);
+  }
+  else
+  {
+    /* Set the error code to busy */
+    hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  return status;
+}
+
+/**
+  * @brief  Change the memory0 or memory1 address on the fly.
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @param  Address:    The new address
+  * @param  memory:     the memory to be changed, This parameter can be one of
+  *                     the following values:
+  *                      MEMORY0 /
+  *                      MEMORY1
+  * @note   The MEMORY0 address can be changed only when the current transfer use
+  *         MEMORY1 and the MEMORY1 address can be changed only when the current
+  *         transfer use MEMORY0.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)
+{
+  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+  {
+    if(memory == MEMORY0)
+    {
+      /* change the memory0 address */
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->M0AR = Address;
+    }
+    else
+    {
+      /* change the memory1 address */
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->M1AR = Address;
+    }
+  }
+  else /* BDMA instance(s) */
+  {
+    if(memory == MEMORY0)
+    {
+      /* change the memory0 address */
+      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CM0AR = Address;
+    }
+    else
+    {
+      /* change the memory1 address */
+      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CM1AR = Address;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the DMAMUX synchronization parameters for a given DMA stream (instance).
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @param  pSyncConfig : pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the DMAMUX synchronization parameters
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)
+{
+  uint32_t syncSignalID = 0;
+  uint32_t syncPolarity = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));
+  assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable));
+  assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable));
+  assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber));
+
+  if(pSyncConfig->SyncEnable == ENABLE)
+  {
+    assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig->SyncPolarity));
+
+    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+    {
+      assert_param(IS_DMA_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));
+    }
+    else
+    {
+      assert_param(IS_BDMA_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));
+    }
+    syncSignalID = pSyncConfig->SyncSignalID;
+    syncPolarity = pSyncConfig->SyncPolarity;
+  }
+
+  /*Check if the DMA state is ready */
+  if(hdma->State == HAL_DMA_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hdma);
+
+    /* Disable the synchronization and event generation before applying a new config */
+    CLEAR_BIT(hdma->DMAmuxChannel->CCR,(DMAMUX_CxCR_SE | DMAMUX_CxCR_EGE));
+
+    /* Set the new synchronization parameters (and keep the request ID filled during the Init)*/
+    MODIFY_REG( hdma->DMAmuxChannel->CCR, \
+               (~DMAMUX_CxCR_DMAREQ_ID) , \
+               (syncSignalID << DMAMUX_CxCR_SYNC_ID_Pos)       | \
+               ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \
+               syncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos)    | \
+               ((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos));
+
+      /* Process Locked */
+    __HAL_UNLOCK(hdma);
+
+    return HAL_OK;
+  }
+  else
+  {
+    /* Set the error code to busy */
+    hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+    /* Return error status */
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the DMAMUX request generator block used by the given DMA stream (instance).
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @param  pRequestGeneratorConfig : pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef :
+  *         contains the request generator parameters.
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
+{
+  HAL_StatusTypeDef status;
+  HAL_DMA_StateTypeDef temp_state = hdma->State;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));
+
+  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+  {
+    assert_param(IS_DMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));
+  }
+  else
+  {
+    assert_param(IS_BDMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));
+  }
+
+
+  assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity));
+  assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber));
+
+  /* check if the DMA state is ready
+     and DMA is using a DMAMUX request generator block
+  */
+  if(hdma->DMAmuxRequestGen == 0U)
+  {
+    /* Set the error code to busy */
+    hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
+
+    /* error status */
+    status = HAL_ERROR;
+  }
+  else if(((hdma->DMAmuxRequestGen->RGCR & DMAMUX_RGxCR_GE) == 0U) && (temp_state == HAL_DMA_STATE_READY))
+  {
+    /* RequestGenerator must be disable prior to the configuration i.e GE bit is 0 */
+
+    /* Process Locked */
+    __HAL_LOCK(hdma);
+
+    /* Set the request generator new parameters */
+    hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \
+                                  ((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GNBREQ_Pos)| \
+                                  pRequestGeneratorConfig->Polarity;
+    /* Process Locked */
+    __HAL_UNLOCK(hdma);
+
+    return HAL_OK;
+  }
+  else
+  {
+    /* Set the error code to busy */
+    hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+    /* error status */
+    status = HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Enable the DMAMUX request generator block used by the given DMA stream (instance).
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));
+
+  /* check if the DMA state is ready
+     and DMA is using a DMAMUX request generator block */
+  if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0U))
+  {
+    /* Enable the request generator*/
+    hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE;
+
+   return HAL_OK;
+ }
+ else
+ {
+   return HAL_ERROR;
+ }
+}
+
+/**
+  * @brief  Disable the DMAMUX request generator block used by the given DMA stream (instance).
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));
+
+  /* check if the DMA state is ready
+     and DMA is using a DMAMUX request generator block */
+  if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0U))
+  {
+    /* Disable the request generator*/
+    hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE;
+
+   return HAL_OK;
+ }
+ else
+ {
+   return HAL_ERROR;
+ }
+}
+
+/**
+  * @brief  Handles DMAMUX interrupt request.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Stream.
+  * @retval None
+  */
+void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma)
+{
+  /* Check for DMAMUX Synchronization overrun */
+  if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
+  {
+    /* Disable the synchro overrun interrupt */
+    hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
+
+    /* Clear the DMAMUX synchro overrun flag */
+    hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+    /* Update error code */
+    hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
+
+    if(hdma->XferErrorCallback != NULL)
+    {
+      /* Transfer error callback */
+      hdma->XferErrorCallback(hdma);
+    }
+  }
+
+  if(hdma->DMAmuxRequestGen != 0)
+  {
+   /* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */
+    if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
+    {
+      /* Disable the request gen overrun interrupt */
+      hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
+
+      /* Clear the DMAMUX request generator overrun flag */
+      hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+
+      /* Update error code */
+      hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
+
+      if(hdma->XferErrorCallback != NULL)
+      {
+        /* Transfer error callback */
+        hdma->XferErrorCallback(hdma);
+      }
+    }
+  }
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMAEx_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Set the DMA Transfer parameter.
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @param  SrcAddress: The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  DataLength: The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+  {
+    /* Configure DMA Stream data length */
+    ((DMA_Stream_TypeDef   *)hdma->Instance)->NDTR = DataLength;
+
+    /* Peripheral to Memory */
+    if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+    {
+      /* Configure DMA Stream destination address */
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->PAR = DstAddress;
+
+      /* Configure DMA Stream source address */
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->M0AR = SrcAddress;
+    }
+    /* Memory to Peripheral */
+    else
+    {
+      /* Configure DMA Stream source address */
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->PAR = SrcAddress;
+
+      /* Configure DMA Stream destination address */
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->M0AR = DstAddress;
+    }
+  }
+  else /* BDMA instance(s) */
+  {
+    /* Configure DMA Stream data length */
+    ((BDMA_Channel_TypeDef   *)hdma->Instance)->CNDTR = DataLength;
+
+    /* Peripheral to Memory */
+    if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+    {
+      /* Configure DMA Stream destination address */
+      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CPAR = DstAddress;
+
+      /* Configure DMA Stream source address */
+      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CM0AR = SrcAddress;
+    }
+    /* Memory to Peripheral */
+    else
+    {
+      /* Configure DMA Stream source address */
+      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CPAR = SrcAddress;
+
+      /* Configure DMA Stream destination address */
+      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CM0AR = DstAddress;
+    }
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c
new file mode 100644
index 00000000..ffb5deef
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c
@@ -0,0 +1,877 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_exti.c
+  * @author  MCD Application Team
+  * @brief   EXTI HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the General Purpose Input/Output (EXTI) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *
+  @verbatim
+  ==============================================================================
+                    ##### EXTI Peripheral features #####
+  ==============================================================================
+  [..]
+    (+) Each Exti line can be configured within this driver.
+
+    (+) Exti line can be configured in 3 different modes
+        (++) Interrupt (CORE1 or CORE2 in case of dual core line )
+        (++) Event (CORE1 or CORE2 in case of dual core line )
+        (++) a combination of the previous
+
+    (+) Configurable Exti lines can be configured with 3 different triggers
+        (++) Rising
+        (++) Falling
+        (++) Both of them
+
+    (+) When set in interrupt mode, configurable Exti lines have two diffenrents
+        interrupt pending registers which allow to distinguish which transition
+        occurs:
+        (++) Rising edge pending interrupt
+        (++) Falling
+
+    (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
+        be selected throught multiplexer.
+
+    (+) PendClearSource used to set the D3 Smart Run Domain autoamtic pend clear soure.
+        It is applicable for line with wkaeup target is Any (CPU1 , CPU2 and D3 smart run domain).
+        Value can be one of the following:
+        (++)  EXTI_D3_PENDCLR_SRC_NONE : no pend clear source is selcted :
+              In this case corresponding bit of D2PMRx register is set to 0
+                (+++) On a configurable Line : the D3 domain wakeup signal is
+                      automatically cleared after after the Delay + Rising Edge detect
+                (+++) On a direct Line : the D3 domain wakeup signal is
+                      cleared after the direct event input signal is cleared
+
+        (++)  EXTI_D3_PENDCLR_SRC_DMACH6 : no pend clear source is selcted :
+              In this case corresponding bit of D2PMRx register is set to 1
+              and corresponding bits(2) of D3PCRxL/H is set to b00 :
+                DMA ch6 event selected as D3 domain pendclear source
+
+        (++)  EXTI_D3_PENDCLR_SRC_DMACH7 : no pend clear source is selcted :
+              In this case corresponding bit of D2PMRx register is set to 1
+              and corresponding bits(2) of D3PCRxL/H is set to b01 :
+                DMA ch7 event selected as D3 domain pendclear source
+
+        (++)  EXTI_D3_PENDCLR_SRC_LPTIM4 : no pend clear source is selcted :
+              In this case corresponding bit of D2PMRx register is set to 1
+              and corresponding bits(2) of D3PCRxL/H is set to b10 :
+                LPTIM4 out selected as D3 domain pendclear source
+
+        (++)  EXTI_D3_PENDCLR_SRC_LPTIM5 : no pend clear source is selcted :
+              In this case corresponding bit of D2PMRx register is set to 1
+              and corresponding bits(2) of D3PCRxL/H is set to b11 :
+                LPTIM5 out selected as D3 domain pendclear source
+
+
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+
+    (#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
+        (++) Choose the interrupt line number by setting "Line" member from
+             EXTI_ConfigTypeDef structure.
+        (++) Configure the interrupt and/or event mode using "Mode" member from
+             EXTI_ConfigTypeDef structure.
+        (++) For configurable lines, configure rising and/or falling trigger
+             "Trigger" member from EXTI_ConfigTypeDef structure.
+        (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
+             member from GPIO_InitTypeDef structure.
+        (++) For Exti lines with wkaeup target is Any (CPU1 , CPU2 and D3 smart run domain),
+             choose gpio D3 PendClearSource using PendClearSource
+             member from EXTI_PendClear_Source structure.
+
+    (#) Get current Exti configuration of a dedicated line using
+        HAL_EXTI_GetConfigLine().
+        (++) Provide exiting handle as parameter.
+        (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
+
+    (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
+        (++) Provide exiting handle as parameter.
+
+    (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
+        (++) Provide exiting handle as first parameter.
+        (++) Provide which callback will be registered using one value from
+             EXTI_CallbackIDTypeDef.
+        (++) Provide callback function pointer.
+
+    (#) Get interrupt pending bit using HAL_EXTI_GetPending().
+
+    (#) Clear interrupt pending bit using HAL_EXTI_GetPending().
+
+    (#) Generate software interrupt using HAL_EXTI_GenerateSWI().
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup EXTI
+  * @{
+  */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines ------------------------------------------------------------*/
+/** @defgroup EXTI_Private_Constants EXTI Private Constants
+  * @{
+  */
+#define EXTI_MODE_OFFSET                    0x04U   /* 0x10: offset between CPU IMR/EMR registers */
+#define EXTI_CONFIG_OFFSET                  0x08U   /* 0x20: offset between CPU Rising/Falling configuration registers */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup EXTI_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup EXTI_Exported_Functions_Group1
+ *  @brief    Configuration functions
+ *
+@verbatim
+ ===============================================================================
+              ##### Configuration functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Set configuration of a dedicated Exti line.
+  * @param  hexti Exti handle.
+  * @param  pExtiConfig Pointer on EXTI configuration to be set.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
+{
+  __IO uint32_t *regaddr;
+  uint32_t regval;
+  uint32_t linepos;
+  uint32_t maskline;
+  uint32_t offset;
+  uint32_t pcrlinepos;
+
+  /* Check null pointer */
+  if ((hexti == NULL) || (pExtiConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(pExtiConfig->Line));
+  assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
+
+  /* Assign line number to handle */
+  hexti->Line = pExtiConfig->Line;
+
+  /* compute line register offset and line mask */
+  offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
+  maskline = (1UL << linepos);
+
+  /* Configure triggers for configurable lines */
+  if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00U)
+  {
+    assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
+
+    /* Configure rising trigger */
+    regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = *regaddr;
+
+    /* Mask or set line */
+    if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00U)
+    {
+      regval |= maskline;
+    }
+    else
+    {
+      regval &= ~maskline;
+    }
+
+    /* Store rising trigger mode */
+    *regaddr = regval;
+
+    /* Configure falling trigger */
+    regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = *regaddr;
+
+    /* Mask or set line */
+    if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00U)
+    {
+      regval |= maskline;
+    }
+    else
+    {
+      regval &= ~maskline;
+    }
+
+    /* Store falling trigger mode */
+    *regaddr = regval;
+
+    /* Configure gpio port selection in case of gpio exti line */
+    if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
+    {
+      assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
+      assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+      regval = SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL];
+      regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03U)));
+      regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03U)));
+      SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL] = regval;
+    }
+  }
+
+  /* Configure interrupt mode : read current mode */
+  regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = *regaddr;
+
+  /* Mask or set line */
+  if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00U)
+  {
+    regval |= maskline;
+  }
+  else
+  {
+    regval &= ~maskline;
+  }
+
+  /* Store interrupt mode */
+  *regaddr = regval;
+
+  /* The event mode cannot be configured if the line does not support it */
+  assert_param(((pExtiConfig->Line & EXTI_EVENT) == EXTI_EVENT) || ((pExtiConfig->Mode & EXTI_MODE_EVENT) != EXTI_MODE_EVENT));
+
+  /* Configure event mode : read current mode */
+  regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = *regaddr;
+
+  /* Mask or set line */
+  if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00U)
+  {
+    regval |= maskline;
+  }
+  else
+  {
+    regval &= ~maskline;
+  }
+
+  /* Store event mode */
+  *regaddr = regval;
+
+#if defined (DUAL_CORE)
+  /* Configure interrupt mode for Core2 : read current mode */
+  regaddr = (__IO uint32_t *)(&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = *regaddr;
+
+  /* Mask or set line */
+  if ((pExtiConfig->Mode & EXTI_MODE_CORE2_INTERRUPT) != 0x00U)
+  {
+    regval |= maskline;
+  }
+  else
+  {
+    regval &= ~maskline;
+  }
+
+  /* Store interrupt mode */
+  *regaddr = regval;
+
+  /* The event mode cannot be configured if the line does not support it */
+  assert_param(((pExtiConfig->Line & EXTI_EVENT) == EXTI_EVENT) || ((pExtiConfig->Mode & EXTI_MODE_CORE2_EVENT) != EXTI_MODE_CORE2_EVENT));
+
+  /* Configure event mode : read current mode */
+  regaddr = (__IO uint32_t *)(&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = *regaddr;
+
+  /* Mask or set line */
+  if ((pExtiConfig->Mode & EXTI_MODE_CORE2_EVENT) != 0x00U)
+  {
+    regval |= maskline;
+  }
+  else
+  {
+    regval &= ~maskline;
+  }
+
+  /* Store event mode */
+  *regaddr = regval;
+#endif /* DUAL_CORE */
+
+  /* Configure the D3 PendClear source in case of Wakeup target is Any */
+  if ((pExtiConfig->Line & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL)
+  {
+    assert_param(IS_EXTI_D3_PENDCLR_SRC(pExtiConfig->PendClearSource));
+
+    /*Calc the PMR register address for the given line */
+    regaddr = (__IO uint32_t *)(&EXTI->D3PMR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = *regaddr;
+
+    if(pExtiConfig->PendClearSource == EXTI_D3_PENDCLR_SRC_NONE)
+    {
+      /* Clear D3PMRx register for the given line */
+      regval &= ~maskline;
+      /* Store D3PMRx register value */
+      *regaddr = regval;
+    }
+    else
+    {
+      /* Set D3PMRx register to 1 for the given line */
+      regval |= maskline;
+      /* Store D3PMRx register value */
+      *regaddr = regval;
+
+      if(linepos < 16UL)
+      {
+        regaddr = (__IO uint32_t *)(&EXTI->D3PCR1L + (EXTI_CONFIG_OFFSET * offset));
+        pcrlinepos = 1UL << linepos;
+      }
+      else
+      {
+        regaddr = (__IO uint32_t *)(&EXTI->D3PCR1H + (EXTI_CONFIG_OFFSET * offset));
+        pcrlinepos = 1UL << (linepos - 16UL);
+      }
+
+      regval = (*regaddr & (~(pcrlinepos * pcrlinepos * 3UL))) | (pcrlinepos * pcrlinepos * (pExtiConfig->PendClearSource - 1UL));
+      *regaddr = regval;
+    }
+  }
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Get configuration of a dedicated Exti line.
+  * @param  hexti Exti handle.
+  * @param  pExtiConfig Pointer on structure to store Exti configuration.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
+{
+  __IO uint32_t *regaddr;
+  uint32_t regval;
+  uint32_t linepos;
+  uint32_t maskline;
+  uint32_t offset;
+  uint32_t pcrlinepos;
+
+  /* Check null pointer */
+  if ((hexti == NULL) || (pExtiConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameter */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+
+  /* Store handle line number to configuration structure */
+  pExtiConfig->Line = hexti->Line;
+
+  /* compute line register offset and line mask */
+  offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
+  maskline = (1UL << linepos);
+
+  /* 1] Get core mode : interrupt */
+  regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = *regaddr;
+
+  pExtiConfig->Mode = EXTI_MODE_NONE;
+
+  /* Check if selected line is enable */
+  if ((regval & maskline) != 0x00U)
+  {
+    pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
+  }
+
+  /* Get event mode */
+  regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = *regaddr;
+
+  /* Check if selected line is enable */
+  if ((regval & maskline) != 0x00U)
+  {
+    pExtiConfig->Mode |= EXTI_MODE_EVENT;
+  }
+#if defined (DUAL_CORE)
+  regaddr = (__IO uint32_t *)(&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = *regaddr;
+
+  /* Check if selected line is enable */
+  if ((regval & maskline) != 0x00U)
+  {
+    pExtiConfig->Mode = EXTI_MODE_CORE2_INTERRUPT;
+  }
+
+  /* Get event mode */
+  regaddr = (__IO uint32_t *)(&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = *regaddr;
+
+  /* Check if selected line is enable */
+  if ((regval & maskline) != 0x00U)
+  {
+    pExtiConfig->Mode |= EXTI_MODE_CORE2_EVENT;
+  }
+#endif /*DUAL_CORE*/
+
+  /* 2] Get trigger for configurable lines : rising */
+  if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00U)
+  {
+    regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = *regaddr;
+
+    /* Check if configuration of selected line is enable */
+    if ((regval & maskline) != 0x00U)
+    {
+      pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
+    }
+    else
+    {
+      pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
+    }
+
+    /* Get falling configuration */
+    regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = *regaddr;
+
+    /* Check if configuration of selected line is enable */
+    if ((regval & maskline) != 0x00U)
+    {
+      pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
+    }
+
+    /* Get Gpio port selection for gpio lines */
+    if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
+    {
+      assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+      regval = SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL];
+      pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3UL - (linepos & 0x03UL)))) >> 24U);
+    }
+    else
+    {
+      pExtiConfig->GPIOSel = 0x00U;
+    }
+  }
+  else
+  {
+    pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
+    pExtiConfig->GPIOSel = 0x00U;
+  }
+
+  /* 3] Get D3 Pend Clear source */
+  if ((pExtiConfig->Line & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL)
+  {
+    regaddr = (__IO uint32_t *)(&EXTI->D3PMR1 + (EXTI_CONFIG_OFFSET * offset));
+    if(((*regaddr) & linepos) == 0UL)
+    {
+      /* if PMR unset, then no pend clear source is used */
+      pExtiConfig->PendClearSource = EXTI_D3_PENDCLR_SRC_NONE;
+    }
+    else
+    {
+      /* if wakeup target is any and PMR set, the read pend clear source from  D3PCRxL/H */
+      if(linepos < 16UL)
+      {
+        regaddr = (__IO uint32_t *)(&EXTI->D3PCR1L + (EXTI_CONFIG_OFFSET * offset));
+        pcrlinepos = 1UL << linepos;
+      }
+      else
+      {
+        regaddr = (__IO uint32_t *)(&EXTI->D3PCR1H + (EXTI_CONFIG_OFFSET * offset));
+        pcrlinepos = 1UL << (linepos - 16UL);
+      }
+
+      pExtiConfig->PendClearSource = 1UL + ((*regaddr & (pcrlinepos * pcrlinepos * 3UL)) / (pcrlinepos * pcrlinepos));
+    }
+  }
+  else
+  {
+    /* if line wakeup target is not any, then no pend clear source is used  */
+    pExtiConfig->PendClearSource = EXTI_D3_PENDCLR_SRC_NONE;
+  }
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Clear whole configuration of a dedicated Exti line.
+  * @param  hexti Exti handle.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
+{
+  __IO uint32_t *regaddr;
+  uint32_t regval;
+  uint32_t linepos;
+  uint32_t maskline;
+  uint32_t offset;
+  uint32_t pcrlinepos;
+
+  /* Check null pointer */
+  if (hexti == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameter */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+
+  /* compute line register offset and line mask */
+  offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  linepos = (hexti->Line & EXTI_PIN_MASK);
+  maskline = (1UL << linepos);
+
+  /* 1] Clear interrupt mode */
+  regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = (*regaddr & ~maskline);
+  *regaddr = regval;
+
+  /* 2] Clear event mode */
+  regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = (*regaddr & ~maskline);
+  *regaddr = regval;
+
+#if defined (DUAL_CORE)
+    /* 1] Clear CM4 interrupt mode */
+  regaddr = (__IO uint32_t *)(&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = (*regaddr & ~maskline);
+  *regaddr = regval;
+
+  /* 2] Clear CM4 event mode */
+  regaddr = (__IO uint32_t *)(&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = (*regaddr & ~maskline);
+  *regaddr = regval;
+#endif /* DUAL_CORE */
+
+  /* 3] Clear triggers in case of configurable lines */
+  if ((hexti->Line & EXTI_CONFIG) != 0x00U)
+  {
+    regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = (*regaddr & ~maskline);
+    *regaddr = regval;
+
+    regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = (*regaddr & ~maskline);
+    *regaddr = regval;
+
+    /* Get Gpio port selection for gpio lines */
+    if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
+    {
+      assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+      regval = SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL];
+      regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03UL)));
+      SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL] = regval;
+    }
+  }
+
+  /* 4] Clear D3 Config lines */
+  if ((hexti->Line & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL)
+  {
+    regaddr = (__IO uint32_t *)(&EXTI->D3PMR1 + (EXTI_CONFIG_OFFSET * offset));
+    *regaddr = (*regaddr & ~maskline);
+
+    if(linepos < 16UL)
+    {
+      regaddr = (__IO uint32_t *)(&EXTI->D3PCR1L + (EXTI_CONFIG_OFFSET * offset));
+      pcrlinepos = 1UL << linepos;
+    }
+    else
+    {
+      regaddr = (__IO uint32_t *)(&EXTI->D3PCR1H + (EXTI_CONFIG_OFFSET * offset));
+      pcrlinepos = 1UL << (linepos - 16UL);
+    }
+
+    /*Clear D3 PendClear source */
+    *regaddr &= (~(pcrlinepos * pcrlinepos * 3UL));
+  }
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Register callback for a dedicated Exti line.
+  * @param  hexti Exti handle.
+  * @param  CallbackID User callback identifier.
+  *         This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
+  * @param  pPendingCbfn function pointer to be stored as callback.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check null pointer */
+  if (hexti == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  switch (CallbackID)
+  {
+    case  HAL_EXTI_COMMON_CB_ID:
+      hexti->PendingCallback = pPendingCbfn;
+      break;
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  return status;
+}
+
+
+/**
+  * @brief  Store line number as handle private field.
+  * @param  hexti Exti handle.
+  * @param  ExtiLine Exti line number.
+  *         This parameter can be from 0 to @ref EXTI_LINE_NB.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
+{
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(ExtiLine));
+
+  /* Check null pointer */
+  if (hexti == NULL)
+  {
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Store line number as handle private field */
+    hexti->Line = ExtiLine;
+
+    return HAL_OK;
+  }
+}
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup EXTI_Exported_Functions_Group2
+ *  @brief EXTI IO functions.
+ *
+@verbatim
+ ===============================================================================
+                       ##### IO operation functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Handle EXTI interrupt request.
+  * @param  hexti Exti handle.
+  * @retval none.
+  */
+void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
+{
+  __IO uint32_t *regaddr;
+  uint32_t regval;
+  uint32_t maskline;
+  uint32_t offset;
+
+  /* Compute line register offset and line mask */
+  offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  maskline = (1UL << (hexti->Line & EXTI_PIN_MASK));
+
+#if defined(DUAL_CORE)
+  if (HAL_GetCurrentCPUID() == CM7_CPUID)
+  {
+    /* Get pending register address */
+    regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
+  }
+  else /* Cortex-M4*/
+  {
+    /* Get pending register address */
+    regaddr = (__IO uint32_t *)(&EXTI->C2PR1 + (EXTI_MODE_OFFSET * offset));
+  }
+#else
+  regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
+#endif /* DUAL_CORE */
+
+  /* Get pending bit  */
+  regval = (*regaddr & maskline);
+
+  if (regval != 0x00U)
+  {
+    /* Clear pending bit */
+    *regaddr = maskline;
+
+    /* Call callback */
+    if (hexti->PendingCallback != NULL)
+    {
+      hexti->PendingCallback();
+    }
+  }
+}
+
+
+/**
+  * @brief  Get interrupt pending bit of a dedicated line.
+  * @param  hexti Exti handle.
+  * @param  Edge Specify which pending edge as to be checked.
+  *         This parameter can be one of the following values:
+  *           @arg @ref EXTI_TRIGGER_RISING_FALLING
+  *         This parameter is kept for compatibility with other series.
+  * @retval 1 if interrupt is pending else 0.
+  */
+uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
+{
+  __IO uint32_t *regaddr;
+  uint32_t regval;
+  uint32_t linepos;
+  uint32_t maskline;
+  uint32_t offset;
+
+  /* Check parameters */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+  assert_param(IS_EXTI_PENDING_EDGE(Edge));
+
+  /* compute line register offset and line mask */
+  offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  linepos = (hexti->Line & EXTI_PIN_MASK);
+  maskline = (1UL << linepos);
+
+#if defined(DUAL_CORE)
+  if (HAL_GetCurrentCPUID() == CM7_CPUID)
+  {
+    /* Get pending register address */
+    regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
+  }
+  else /* Cortex-M4 */
+  {
+    /* Get pending register address */
+    regaddr = (__IO uint32_t *)(&EXTI->C2PR1 + (EXTI_MODE_OFFSET * offset));
+  }
+#else
+  regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
+#endif /* DUAL_CORE */
+
+  /* return 1 if bit is set else 0 */
+  regval = ((*regaddr & maskline) >> linepos);
+  return regval;
+}
+
+
+/**
+  * @brief  Clear interrupt pending bit of a dedicated line.
+  * @param  hexti Exti handle.
+  * @param  Edge Specify which pending edge as to be clear.
+  *         This parameter can be one of the following values:
+  *           @arg @ref EXTI_TRIGGER_RISING_FALLING
+  *         This parameter is kept for compatibility with other series.
+  * @retval None.
+  */
+void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
+{
+  __IO uint32_t *regaddr;
+  uint32_t maskline;
+  uint32_t offset;
+
+  /* Check parameters */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+  assert_param(IS_EXTI_PENDING_EDGE(Edge));
+
+  /* compute line register offset and line mask */
+  offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  maskline = (1UL << (hexti->Line & EXTI_PIN_MASK));
+
+#if defined(DUAL_CORE)
+  if (HAL_GetCurrentCPUID() == CM7_CPUID)
+  {
+    /* Get pending register address */
+    regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
+  }
+  else /* Cortex-M4 */
+  {
+    /* Get pending register address */
+    regaddr = (__IO uint32_t *)(&EXTI->C2PR1 + (EXTI_MODE_OFFSET * offset));
+  }
+#else
+  regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
+#endif /* DUAL_CORE */
+
+  /* Clear Pending bit */
+  *regaddr =  maskline;
+}
+
+/**
+  * @brief  Generate a software interrupt for a dedicated line.
+  * @param  hexti Exti handle.
+  * @retval None.
+  */
+void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
+{
+  __IO uint32_t *regaddr;
+  uint32_t maskline;
+  uint32_t offset;
+
+  /* Check parameters */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+
+  /* compute line register offset and line mask */
+  offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  maskline = (1UL << (hexti->Line & EXTI_PIN_MASK));
+
+  regaddr = (__IO uint32_t *)(&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset));
+  *regaddr = maskline;
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_EXTI_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c
new file mode 100644
index 00000000..7505fd5a
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c
@@ -0,0 +1,6169 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_fdcan.c
+  * @author  MCD Application Team
+  * @brief   FDCAN HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Flexible DataRate Controller Area Network
+  *          (FDCAN) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Configuration and Control functions
+  *           + Peripheral State and Error functions
+  *
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      (#) Initialize the FDCAN peripheral using HAL_FDCAN_Init function.
+
+      (#) If needed , configure the reception filters and optional features using
+          the following configuration functions:
+            (++) HAL_FDCAN_ConfigClockCalibration
+            (++) HAL_FDCAN_ConfigFilter
+            (++) HAL_FDCAN_ConfigGlobalFilter
+            (++) HAL_FDCAN_ConfigExtendedIdMask
+            (++) HAL_FDCAN_ConfigRxFifoOverwrite
+            (++) HAL_FDCAN_ConfigFifoWatermark
+            (++) HAL_FDCAN_ConfigRamWatchdog
+            (++) HAL_FDCAN_ConfigTimestampCounter
+            (++) HAL_FDCAN_EnableTimestampCounter
+            (++) HAL_FDCAN_DisableTimestampCounter
+            (++) HAL_FDCAN_ConfigTimeoutCounter
+            (++) HAL_FDCAN_EnableTimeoutCounter
+            (++) HAL_FDCAN_DisableTimeoutCounter
+            (++) HAL_FDCAN_ConfigTxDelayCompensation
+            (++) HAL_FDCAN_EnableTxDelayCompensation
+            (++) HAL_FDCAN_DisableTxDelayCompensation
+            (++) HAL_FDCAN_EnableISOMode
+            (++) HAL_FDCAN_DisableISOMode
+            (++) HAL_FDCAN_EnableEdgeFiltering
+            (++) HAL_FDCAN_DisableEdgeFiltering
+            (++) HAL_FDCAN_TT_ConfigOperation
+            (++) HAL_FDCAN_TT_ConfigReferenceMessage
+            (++) HAL_FDCAN_TT_ConfigTrigger
+
+      (#) Start the FDCAN module using HAL_FDCAN_Start function. At this level
+          the node is active on the bus: it can send and receive messages.
+
+      (#) The following Tx control functions can only be called when the FDCAN
+          module is started:
+            (++) HAL_FDCAN_AddMessageToTxFifoQ
+            (++) HAL_FDCAN_EnableTxBufferRequest
+            (++) HAL_FDCAN_AbortTxRequest
+
+      (#) After having submitted a Tx request in Tx Fifo or Queue, it is possible to
+          get Tx buffer location used to place the Tx request thanks to
+          HAL_FDCAN_GetLatestTxFifoQRequestBuffer API.
+          It is then possible to abort later on the corresponding Tx Request using
+          HAL_FDCAN_AbortTxRequest API.
+
+      (#) When a message is received into the FDCAN message RAM, it can be
+          retrieved using the HAL_FDCAN_GetRxMessage function.
+
+      (#) Calling the HAL_FDCAN_Stop function stops the FDCAN module by entering
+          it to initialization mode and re-enabling access to configuration
+          registers through the configuration functions listed here above.
+
+      (#) All other control functions can be called any time after initialization
+          phase, no matter if the FDCAN module is started or stoped.
+
+      *** Polling mode operation ***
+      ==============================
+
+    [..]
+        (#) Reception and transmission states can be monitored via the following
+            functions:
+              (++) HAL_FDCAN_IsRxBufferMessageAvailable
+              (++) HAL_FDCAN_IsTxBufferMessagePending
+              (++) HAL_FDCAN_GetRxFifoFillLevel
+              (++) HAL_FDCAN_GetTxFifoFreeLevel
+
+      *** Interrupt mode operation ***
+      ================================
+      [..]
+        (#) There are two interrupt lines: line 0 and 1.
+            By default, all interrupts are assigned to line 0. Interrupt lines
+            can be configured using HAL_FDCAN_ConfigInterruptLines function.
+
+        (#) Notifications are activated using HAL_FDCAN_ActivateNotification
+            function. Then, the process can be controlled through one of the
+            available user callbacks: HAL_FDCAN_xxxCallback.
+
+  *** Callback registration ***
+  =============================================
+
+  The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS when set to 1
+  allows the user to configure dynamically the driver callbacks.
+  Use Function @ref HAL_FDCAN_RegisterCallback() or HAL_FDCAN_RegisterXXXCallback()
+  to register an interrupt callback.
+
+  Function @ref HAL_FDCAN_RegisterCallback() allows to register following callbacks:
+    (+) TxFifoEmptyCallback          : Tx Fifo Empty Callback.
+    (+) RxBufferNewMessageCallback   : Rx Buffer New Message Callback.
+    (+) HighPriorityMessageCallback  : High Priority Message Callback.
+    (+) TimestampWraparoundCallback  : Timestamp Wraparound Callback.
+    (+) TimeoutOccurredCallback      : Timeout Occurred Callback.
+    (+) ErrorCallback                : Error Callback.
+    (+) MspInitCallback              : FDCAN MspInit.
+    (+) MspDeInitCallback            : FDCAN MspDeInit.
+  This function takes as parameters the HAL peripheral handle, the Callback ID
+  and a pointer to the user callback function.
+
+  For specific callbacks ClockCalibrationCallback, TxEventFifoCallback, RxFifo0Callback, RxFifo1Callback,
+  TxBufferCompleteCallback, TxBufferAbortCallback, ErrorStatusCallback, TT_ScheduleSyncCallback, TT_TimeMarkCallback,
+  TT_StopWatchCallback and TT_GlobalTimeCallback, use dedicated register callbacks :
+  respectively @ref HAL_FDCAN_RegisterClockCalibrationCallback(), @ref HAL_FDCAN_RegisterTxEventFifoCallback(),
+  @ref HAL_FDCAN_RegisterRxFifo0Callback(), @ref HAL_FDCAN_RegisterRxFifo1Callback(),
+  @ref HAL_FDCAN_RegisterTxBufferCompleCallback(), @ref HAL_FDCAN_RegisterTxBufferAbortCallback(),
+  @ref HAL_FDCAN_RegisterErrorStatusCallback(), @ref HAL_FDCAN_TT_RegisterScheduleSyncCallback(),
+  @ref HAL_FDCAN_TT_RegisterTimeMarkCallback(), @ref HAL_FDCAN_TT_RegisterStopWatchCallback() and
+  @ref HAL_FDCAN_TT_RegisterGlobalTimeCallback().
+
+  Use function @ref HAL_FDCAN_UnRegisterCallback() to reset a callback to the default
+  weak function.
+  @ref HAL_FDCAN_UnRegisterCallback takes as parameters the HAL peripheral handle,
+  and the Callback ID.
+  This function allows to reset following callbacks:
+    (+) TxFifoEmptyCallback          : Tx Fifo Empty Callback.
+    (+) RxBufferNewMessageCallback   : Rx Buffer New Message Callback.
+    (+) HighPriorityMessageCallback  : High Priority Message Callback.
+    (+) TimestampWraparoundCallback  : Timestamp Wraparound Callback.
+    (+) TimeoutOccurredCallback      : Timeout Occurred Callback.
+    (+) ErrorCallback                : Error Callback.
+    (+) MspInitCallback              : FDCAN MspInit.
+    (+) MspDeInitCallback            : FDCAN MspDeInit.
+
+  For specific callbacks ClockCalibrationCallback, TxEventFifoCallback, RxFifo0Callback,
+  RxFifo1Callback, TxBufferCompleteCallback, TxBufferAbortCallback, TT_ScheduleSyncCallback,
+  TT_TimeMarkCallback, TT_StopWatchCallback and TT_GlobalTimeCallback, use dedicated
+  register callbacks : respectively @ref HAL_FDCAN_UnRegisterClockCalibrationCallback(),
+  @ref HAL_FDCAN_UnRegisterTxEventFifoCallback(), @ref HAL_FDCAN_UnRegisterRxFifo0Callback(),
+  @ref HAL_FDCAN_UnRegisterRxFifo1Callback(), @ref HAL_FDCAN_UnRegisterTxBufferCompleCallback(),
+  @ref HAL_FDCAN_UnRegisterTxBufferAbortCallback(), @ref HAL_FDCAN_UnRegisterErrorStatusCallback(),
+  @ref HAL_FDCAN_TT_UnRegisterScheduleSyncCallback(), @ref HAL_FDCAN_TT_UnRegisterTimeMarkCallback(),
+  @ref HAL_FDCAN_TT_UnRegisterStopWatchCallback() and @ref HAL_FDCAN_TT_UnRegisterGlobalTimeCallback().
+
+  By default, after the @ref HAL_FDCAN_Init() and when the state is HAL_FDCAN_STATE_RESET,
+  all callbacks are set to the corresponding weak functions:
+  examples @ref HAL_FDCAN_ErrorCallback().
+  Exception done for MspInit and MspDeInit functions that are
+  reset to the legacy weak function in the @ref HAL_FDCAN_Init()/ @ref HAL_FDCAN_DeInit() only when
+  these callbacks are null (not registered beforehand).
+  if not, MspInit or MspDeInit are not null, the @ref HAL_FDCAN_Init()/ @ref HAL_FDCAN_DeInit()
+  keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+  Callbacks can be registered/unregistered in HAL_FDCAN_STATE_READY state only.
+  Exception done MspInit/MspDeInit that can be registered/unregistered
+  in HAL_FDCAN_STATE_READY or HAL_FDCAN_STATE_RESET state,
+  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+  In that case first register the MspInit/MspDeInit user callbacks
+  using @ref HAL_FDCAN_RegisterCallback() before calling @ref HAL_FDCAN_DeInit()
+  or @ref HAL_FDCAN_Init() function.
+
+  When The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS is set to 0 or
+  not defined, the callback registration feature is not available and all callbacks
+  are set to the corresponding weak functions.
+
+  @endverbatim
+
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup FDCAN FDCAN
+  * @brief FDCAN HAL module driver
+  * @{
+  */
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup FDCAN_Private_Constants
+  * @{
+  */
+#define FDCAN_TIMEOUT_VALUE 10U
+
+#define FDCAN_TX_EVENT_FIFO_MASK (FDCAN_IR_TEFL | FDCAN_IR_TEFF | FDCAN_IR_TEFW | FDCAN_IR_TEFN)
+#define FDCAN_RX_FIFO0_MASK (FDCAN_IR_RF0L | FDCAN_IR_RF0F | FDCAN_IR_RF0W | FDCAN_IR_RF0N)
+#define FDCAN_RX_FIFO1_MASK (FDCAN_IR_RF1L | FDCAN_IR_RF1F | FDCAN_IR_RF1W | FDCAN_IR_RF1N)
+#define FDCAN_ERROR_MASK (FDCAN_IR_ELO | FDCAN_IR_WDI | FDCAN_IR_PEA | FDCAN_IR_PED | FDCAN_IR_ARA)
+#define FDCAN_ERROR_STATUS_MASK (FDCAN_IR_EP | FDCAN_IR_EW | FDCAN_IR_BO)
+#define FDCAN_TT_SCHEDULE_SYNC_MASK (FDCAN_TTIR_SBC | FDCAN_TTIR_SMC | FDCAN_TTIR_CSM | FDCAN_TTIR_SOG)
+#define FDCAN_TT_TIME_MARK_MASK (FDCAN_TTIR_RTMI | FDCAN_TTIR_TTMI)
+#define FDCAN_TT_GLOBAL_TIME_MASK (FDCAN_TTIR_GTW | FDCAN_TTIR_GTD)
+#define FDCAN_TT_DISTURBING_ERROR_MASK (FDCAN_TTIR_GTE | FDCAN_TTIR_TXU | FDCAN_TTIR_TXO | \
+                                        FDCAN_TTIR_SE1 | FDCAN_TTIR_SE2 | FDCAN_TTIR_ELC)
+#define FDCAN_TT_FATAL_ERROR_MASK (FDCAN_TTIR_IWT | FDCAN_TTIR_WT | FDCAN_TTIR_AW | FDCAN_TTIR_CER)
+
+#define FDCAN_ELEMENT_MASK_STDID ((uint32_t)0x1FFC0000U) /* Standard Identifier         */
+#define FDCAN_ELEMENT_MASK_EXTID ((uint32_t)0x1FFFFFFFU) /* Extended Identifier         */
+#define FDCAN_ELEMENT_MASK_RTR   ((uint32_t)0x20000000U) /* Remote Transmission Request */
+#define FDCAN_ELEMENT_MASK_XTD   ((uint32_t)0x40000000U) /* Extended Identifier         */
+#define FDCAN_ELEMENT_MASK_ESI   ((uint32_t)0x80000000U) /* Error State Indicator       */
+#define FDCAN_ELEMENT_MASK_TS    ((uint32_t)0x0000FFFFU) /* Timestamp                   */
+#define FDCAN_ELEMENT_MASK_DLC   ((uint32_t)0x000F0000U) /* Data Length Code            */
+#define FDCAN_ELEMENT_MASK_BRS   ((uint32_t)0x00100000U) /* Bit Rate Switch             */
+#define FDCAN_ELEMENT_MASK_FDF   ((uint32_t)0x00200000U) /* FD Format                   */
+#define FDCAN_ELEMENT_MASK_EFC   ((uint32_t)0x00800000U) /* Event FIFO Control          */
+#define FDCAN_ELEMENT_MASK_MM    ((uint32_t)0xFF000000U) /* Message Marker              */
+#define FDCAN_ELEMENT_MASK_FIDX  ((uint32_t)0x7F000000U) /* Filter Index                */
+#define FDCAN_ELEMENT_MASK_ANMF  ((uint32_t)0x80000000U) /* Accepted Non-matching Frame */
+#define FDCAN_ELEMENT_MASK_ET    ((uint32_t)0x00C00000U) /* Event type                  */
+
+#define FDCAN_MESSAGE_RAM_SIZE 0x2800U
+#define FDCAN_MESSAGE_RAM_END_ADDRESS (SRAMCAN_BASE + FDCAN_MESSAGE_RAM_SIZE - 0x4U) /* The Message RAM has a width of 4 Bytes */
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+static const uint8_t DLCtoBytes[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64};
+
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup FDCAN_Private_Functions_Prototypes
+  * @{
+  */
+static HAL_StatusTypeDef FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan);
+static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup FDCAN_Exported_Functions FDCAN Exported Functions
+  * @{
+  */
+
+/** @defgroup FDCAN_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+  ==============================================================================
+              ##### Initialization and de-initialization functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize and configure the FDCAN.
+      (+) De-initialize the FDCAN.
+      (+) Enter FDCAN peripheral in power down mode.
+      (+) Exit power down mode.
+      (+) Register callbacks.
+      (+) Unregister callbacks.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the FDCAN peripheral according to the specified
+  *         parameters in the FDCAN_InitTypeDef structure.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t tickstart;
+  HAL_StatusTypeDef status;
+  const uint32_t CvtEltSize[] = {0, 0, 0, 0, 0, 1, 2, 3, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0, 7};
+
+  /* Check FDCAN handle */
+  if (hfdcan == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check FDCAN instance */
+  if (hfdcan->Instance == FDCAN1)
+  {
+    hfdcan->ttcan = (TTCAN_TypeDef *)((uint32_t)hfdcan->Instance + 0x100U);
+  }
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_FRAME_FORMAT(hfdcan->Init.FrameFormat));
+  assert_param(IS_FDCAN_MODE(hfdcan->Init.Mode));
+  assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.AutoRetransmission));
+  assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.TransmitPause));
+  assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.ProtocolException));
+  assert_param(IS_FDCAN_NOMINAL_PRESCALER(hfdcan->Init.NominalPrescaler));
+  assert_param(IS_FDCAN_NOMINAL_SJW(hfdcan->Init.NominalSyncJumpWidth));
+  assert_param(IS_FDCAN_NOMINAL_TSEG1(hfdcan->Init.NominalTimeSeg1));
+  assert_param(IS_FDCAN_NOMINAL_TSEG2(hfdcan->Init.NominalTimeSeg2));
+  if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS)
+  {
+    assert_param(IS_FDCAN_DATA_PRESCALER(hfdcan->Init.DataPrescaler));
+    assert_param(IS_FDCAN_DATA_SJW(hfdcan->Init.DataSyncJumpWidth));
+    assert_param(IS_FDCAN_DATA_TSEG1(hfdcan->Init.DataTimeSeg1));
+    assert_param(IS_FDCAN_DATA_TSEG2(hfdcan->Init.DataTimeSeg2));
+  }
+  assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.StdFiltersNbr, 128U));
+  assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.ExtFiltersNbr, 64U));
+  assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.RxFifo0ElmtsNbr, 64U));
+  if (hfdcan->Init.RxFifo0ElmtsNbr > 0U)
+  {
+    assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.RxFifo0ElmtSize));
+  }
+  assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.RxFifo1ElmtsNbr, 64U));
+  if (hfdcan->Init.RxFifo1ElmtsNbr > 0U)
+  {
+    assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.RxFifo1ElmtSize));
+  }
+  assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.RxBuffersNbr, 64U));
+  if (hfdcan->Init.RxBuffersNbr > 0U)
+  {
+    assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.RxBufferSize));
+  }
+  assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.TxEventsNbr, 32U));
+  assert_param(IS_FDCAN_MAX_VALUE((hfdcan->Init.TxBuffersNbr + hfdcan->Init.TxFifoQueueElmtsNbr), 32U));
+  if (hfdcan->Init.TxFifoQueueElmtsNbr > 0U)
+  {
+    assert_param(IS_FDCAN_TX_FIFO_QUEUE_MODE(hfdcan->Init.TxFifoQueueMode));
+  }
+  if ((hfdcan->Init.TxBuffersNbr + hfdcan->Init.TxFifoQueueElmtsNbr) > 0U)
+  {
+    assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.TxElmtSize));
+  }
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+  if (hfdcan->State == HAL_FDCAN_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hfdcan->Lock = HAL_UNLOCKED;
+
+    /* Reset callbacks to legacy functions */
+    hfdcan->ClockCalibrationCallback    = HAL_FDCAN_ClockCalibrationCallback;    /* Legacy weak ClockCalibrationCallback    */
+    hfdcan->TxEventFifoCallback         = HAL_FDCAN_TxEventFifoCallback;         /* Legacy weak TxEventFifoCallback         */
+    hfdcan->RxFifo0Callback             = HAL_FDCAN_RxFifo0Callback;             /* Legacy weak RxFifo0Callback             */
+    hfdcan->RxFifo1Callback             = HAL_FDCAN_RxFifo1Callback;             /* Legacy weak RxFifo1Callback             */
+    hfdcan->TxFifoEmptyCallback         = HAL_FDCAN_TxFifoEmptyCallback;         /* Legacy weak TxFifoEmptyCallback         */
+    hfdcan->TxBufferCompleteCallback    = HAL_FDCAN_TxBufferCompleteCallback;    /* Legacy weak TxBufferCompleteCallback    */
+    hfdcan->TxBufferAbortCallback       = HAL_FDCAN_TxBufferAbortCallback;       /* Legacy weak TxBufferAbortCallback       */
+    hfdcan->RxBufferNewMessageCallback  = HAL_FDCAN_RxBufferNewMessageCallback;  /* Legacy weak RxBufferNewMessageCallback  */
+    hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback; /* Legacy weak HighPriorityMessageCallback */
+    hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback; /* Legacy weak TimestampWraparoundCallback */
+    hfdcan->TimeoutOccurredCallback     = HAL_FDCAN_TimeoutOccurredCallback;     /* Legacy weak TimeoutOccurredCallback     */
+    hfdcan->ErrorCallback               = HAL_FDCAN_ErrorCallback;               /* Legacy weak ErrorCallback               */
+    hfdcan->ErrorStatusCallback         = HAL_FDCAN_ErrorStatusCallback;         /* Legacy weak ErrorStatusCallback         */
+    hfdcan->TT_ScheduleSyncCallback     = HAL_FDCAN_TT_ScheduleSyncCallback;     /* Legacy weak TT_ScheduleSyncCallback     */
+    hfdcan->TT_TimeMarkCallback         = HAL_FDCAN_TT_TimeMarkCallback;         /* Legacy weak TT_TimeMarkCallback         */
+    hfdcan->TT_StopWatchCallback        = HAL_FDCAN_TT_StopWatchCallback;        /* Legacy weak TT_StopWatchCallback        */
+    hfdcan->TT_GlobalTimeCallback       = HAL_FDCAN_TT_GlobalTimeCallback;       /* Legacy weak TT_GlobalTimeCallback       */
+
+    if (hfdcan->MspInitCallback == NULL)
+    {
+      hfdcan->MspInitCallback = HAL_FDCAN_MspInit;  /* Legacy weak MspInit */
+    }
+
+    /* Init the low level hardware: CLOCK, NVIC */
+    hfdcan->MspInitCallback(hfdcan);
+  }
+#else
+  if (hfdcan->State == HAL_FDCAN_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hfdcan->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware: CLOCK, NVIC */
+    HAL_FDCAN_MspInit(hfdcan);
+  }
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+  /* Exit from Sleep mode */
+  CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Check Sleep mode acknowledge */
+  while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
+  {
+    if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+      /* Change FDCAN state */
+      hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+      return HAL_ERROR;
+    }
+  }
+
+  /* Request initialisation */
+  SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait until the INIT bit into CCCR register is set */
+  while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U)
+  {
+    /* Check for the Timeout */
+    if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+      /* Change FDCAN state */
+      hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+      return HAL_ERROR;
+    }
+  }
+
+  /* Enable configuration change */
+  SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE);
+
+  /* Set the no automatic retransmission */
+  if (hfdcan->Init.AutoRetransmission == ENABLE)
+  {
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR);
+  }
+  else
+  {
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR);
+  }
+
+  /* Set the transmit pause feature */
+  if (hfdcan->Init.TransmitPause == ENABLE)
+  {
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP);
+  }
+  else
+  {
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP);
+  }
+
+  /* Set the Protocol Exception Handling */
+  if (hfdcan->Init.ProtocolException == ENABLE)
+  {
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD);
+  }
+  else
+  {
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD);
+  }
+
+  /* Set FDCAN Frame Format */
+  MODIFY_REG(hfdcan->Instance->CCCR, FDCAN_FRAME_FD_BRS, hfdcan->Init.FrameFormat);
+
+  /* Reset FDCAN Operation Mode */
+  CLEAR_BIT(hfdcan->Instance->CCCR, (FDCAN_CCCR_TEST | FDCAN_CCCR_MON | FDCAN_CCCR_ASM));
+  CLEAR_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK);
+
+  /* Set FDCAN Operating Mode:
+               | Normal | Restricted |    Bus     | Internal | External
+               |        | Operation  | Monitoring | LoopBack | LoopBack
+     CCCR.TEST |   0    |     0      |     0      |    1     |    1
+     CCCR.MON  |   0    |     0      |     1      |    1     |    0
+     TEST.LBCK |   0    |     0      |     0      |    1     |    1
+     CCCR.ASM  |   0    |     1      |     0      |    0     |    0
+  */
+  if (hfdcan->Init.Mode == FDCAN_MODE_RESTRICTED_OPERATION)
+  {
+    /* Enable Restricted Operation mode */
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM);
+  }
+  else if (hfdcan->Init.Mode != FDCAN_MODE_NORMAL)
+  {
+    if (hfdcan->Init.Mode != FDCAN_MODE_BUS_MONITORING)
+    {
+      /* Enable write access to TEST register */
+      SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TEST);
+
+      /* Enable LoopBack mode */
+      SET_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK);
+
+      if (hfdcan->Init.Mode == FDCAN_MODE_INTERNAL_LOOPBACK)
+      {
+        SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON);
+      }
+    }
+    else
+    {
+      /* Enable bus monitoring mode */
+      SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON);
+    }
+  }
+  else
+  {
+    /* Nothing to do: normal mode */
+  }
+
+  /* Set the nominal bit timing register */
+  hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U) << FDCAN_NBTP_NSJW_Pos) | \
+                            (((uint32_t)hfdcan->Init.NominalTimeSeg1 - 1U) << FDCAN_NBTP_NTSEG1_Pos)    | \
+                            (((uint32_t)hfdcan->Init.NominalTimeSeg2 - 1U) << FDCAN_NBTP_NTSEG2_Pos)    | \
+                            (((uint32_t)hfdcan->Init.NominalPrescaler - 1U) << FDCAN_NBTP_NBRP_Pos));
+
+  /* If FD operation with BRS is selected, set the data bit timing register */
+  if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS)
+  {
+    hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos) | \
+                              (((uint32_t)hfdcan->Init.DataTimeSeg1 - 1U) << FDCAN_DBTP_DTSEG1_Pos)    | \
+                              (((uint32_t)hfdcan->Init.DataTimeSeg2 - 1U) << FDCAN_DBTP_DTSEG2_Pos)    | \
+                              (((uint32_t)hfdcan->Init.DataPrescaler - 1U) << FDCAN_DBTP_DBRP_Pos));
+  }
+
+  if (hfdcan->Init.TxFifoQueueElmtsNbr > 0U)
+  {
+    /* Select between Tx FIFO and Tx Queue operation modes */
+    SET_BIT(hfdcan->Instance->TXBC, hfdcan->Init.TxFifoQueueMode);
+  }
+
+  /* Configure Tx element size */
+  if ((hfdcan->Init.TxBuffersNbr + hfdcan->Init.TxFifoQueueElmtsNbr) > 0U)
+  {
+    MODIFY_REG(hfdcan->Instance->TXESC, FDCAN_TXESC_TBDS, CvtEltSize[hfdcan->Init.TxElmtSize]);
+  }
+
+  /* Configure Rx FIFO 0 element size */
+  if (hfdcan->Init.RxFifo0ElmtsNbr > 0U)
+  {
+    MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_F0DS, (CvtEltSize[hfdcan->Init.RxFifo0ElmtSize] << FDCAN_RXESC_F0DS_Pos));
+  }
+
+  /* Configure Rx FIFO 1 element size */
+  if (hfdcan->Init.RxFifo1ElmtsNbr > 0U)
+  {
+    MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_F1DS, (CvtEltSize[hfdcan->Init.RxFifo1ElmtSize] << FDCAN_RXESC_F1DS_Pos));
+  }
+
+  /* Configure Rx buffer element size */
+  if (hfdcan->Init.RxBuffersNbr > 0U)
+  {
+    MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_RBDS, (CvtEltSize[hfdcan->Init.RxBufferSize] << FDCAN_RXESC_RBDS_Pos));
+  }
+
+  /* By default operation mode is set to Event-driven communication.
+     If Time-triggered communication is needed, user should call the
+     HAL_FDCAN_TT_ConfigOperation function just after the HAL_FDCAN_Init */
+  if (hfdcan->Instance == FDCAN1)
+  {
+    CLEAR_BIT(hfdcan->ttcan->TTOCF, FDCAN_TTOCF_OM);
+  }
+
+  /* Initialize the Latest Tx FIFO/Queue request buffer index */
+  hfdcan->LatestTxFifoQRequest = 0U;
+
+  /* Initialize the error code */
+  hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
+
+  /* Initialize the FDCAN state */
+  hfdcan->State = HAL_FDCAN_STATE_READY;
+
+  /* Calculate each RAM block address */
+  status = FDCAN_CalcultateRamBlockAddresses(hfdcan);
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Deinitializes the FDCAN peripheral registers to their default reset values.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Check FDCAN handle */
+  if (hfdcan == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance));
+
+  /* Stop the FDCAN module: return value is voluntary ignored */
+  (void)HAL_FDCAN_Stop(hfdcan);
+
+  /* Disable Interrupt lines */
+  CLEAR_BIT(hfdcan->Instance->ILE, (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1));
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+  if (hfdcan->MspDeInitCallback == NULL)
+  {
+    hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit; /* Legacy weak MspDeInit */
+  }
+
+  /* DeInit the low level hardware: CLOCK, NVIC */
+  hfdcan->MspDeInitCallback(hfdcan);
+#else
+  /* DeInit the low level hardware: CLOCK, NVIC */
+  HAL_FDCAN_MspDeInit(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+  /* Reset the FDCAN ErrorCode */
+  hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
+
+  /* Change FDCAN state */
+  hfdcan->State = HAL_FDCAN_STATE_RESET;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the FDCAN MSP.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes the FDCAN MSP.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Enter FDCAN peripheral in sleep mode.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t tickstart;
+
+  /* Request clock stop */
+  SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait until FDCAN is ready for power down */
+  while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+      /* Change FDCAN state */
+      hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+      return HAL_ERROR;
+    }
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Exit power down mode.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t tickstart;
+
+  /* Reset clock stop request */
+  CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait until FDCAN exits sleep mode */
+  while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
+  {
+    if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+      /* Change FDCAN state */
+      hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+      return HAL_ERROR;
+    }
+  }
+
+  /* Enter normal operation */
+  CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+/**
+  * @brief  Register a FDCAN CallBack.
+  *         To be used instead of the weak predefined callback
+  * @param  hfdcan pointer to a FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for FDCAN module
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_FDCAN_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty callback ID
+  *           @arg @ref HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID Rx buffer new message callback ID
+  *           @arg @ref HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID High priority message callback ID
+  *           @arg @ref HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID Timestamp wraparound callback ID
+  *           @arg @ref HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID Timeout occurred callback ID
+  *           @arg @ref HAL_FDCAN_ERROR_CALLBACK_CB_ID Error callback ID
+  *           @arg @ref HAL_FDCAN_MSPINIT_CB_ID MspInit callback ID
+  *           @arg @ref HAL_FDCAN_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, void (* pCallback)(FDCAN_HandleTypeDef *_hFDCAN))
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_FDCAN_TX_FIFO_EMPTY_CB_ID :
+        hfdcan->TxFifoEmptyCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID :
+        hfdcan->RxBufferNewMessageCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID :
+        hfdcan->HighPriorityMessageCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID :
+        hfdcan->TimestampWraparoundCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID :
+        hfdcan->TimeoutOccurredCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_ERROR_CALLBACK_CB_ID :
+        hfdcan->ErrorCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_MSPINIT_CB_ID :
+        hfdcan->MspInitCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_MSPDEINIT_CB_ID :
+        hfdcan->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hfdcan->State == HAL_FDCAN_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_FDCAN_MSPINIT_CB_ID :
+        hfdcan->MspInitCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_MSPDEINIT_CB_ID :
+        hfdcan->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a FDCAN CallBack.
+  *         FDCAN callback is redirected to the weak predefined callback
+  * @param  hfdcan pointer to a FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for FDCAN module
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_FDCAN_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty callback ID
+  *           @arg @ref HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID Rx buffer new message callback ID
+  *           @arg @ref HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID High priority message callback ID
+  *           @arg @ref HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID Timestamp wraparound callback ID
+  *           @arg @ref HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID Timeout occurred callback ID
+  *           @arg @ref HAL_FDCAN_ERROR_CALLBACK_CB_ID Error callback ID
+  *           @arg @ref HAL_FDCAN_MSPINIT_CB_ID MspInit callback ID
+  *           @arg @ref HAL_FDCAN_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_FDCAN_TX_FIFO_EMPTY_CB_ID :
+        hfdcan->TxFifoEmptyCallback = HAL_FDCAN_TxFifoEmptyCallback;
+        break;
+
+      case HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID :
+        hfdcan->RxBufferNewMessageCallback = HAL_FDCAN_RxBufferNewMessageCallback;
+        break;
+
+      case HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID :
+        hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback;
+        break;
+
+      case HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID :
+        hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback;
+        break;
+
+      case HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID :
+        hfdcan->TimeoutOccurredCallback = HAL_FDCAN_TimeoutOccurredCallback;
+        break;
+
+      case HAL_FDCAN_ERROR_CALLBACK_CB_ID :
+        hfdcan->ErrorCallback = HAL_FDCAN_ErrorCallback;
+        break;
+
+      case HAL_FDCAN_MSPINIT_CB_ID :
+        hfdcan->MspInitCallback = HAL_FDCAN_MspInit;
+        break;
+
+      case HAL_FDCAN_MSPDEINIT_CB_ID :
+        hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hfdcan->State == HAL_FDCAN_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_FDCAN_MSPINIT_CB_ID :
+        hfdcan->MspInitCallback = HAL_FDCAN_MspInit;
+        break;
+
+      case HAL_FDCAN_MSPDEINIT_CB_ID :
+        hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register Clock Calibration FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_ClockCalibrationCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the Clock Calibration Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ClockCalibrationCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->ClockCalibrationCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Clock Calibration FDCAN Callback
+  *         Clock Calibration FDCAN Callback is redirected to the weak HAL_FDCAN_ClockCalibrationCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->ClockCalibrationCallback = HAL_FDCAN_ClockCalibrationCallback; /* Legacy weak ClockCalibrationCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register Tx Event Fifo FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_TxEventFifoCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the Tx Event Fifo Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxEventFifoCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TxEventFifoCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Tx Event Fifo FDCAN Callback
+  *         Tx Event Fifo FDCAN Callback is redirected to the weak HAL_FDCAN_TxEventFifoCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TxEventFifoCallback = HAL_FDCAN_TxEventFifoCallback; /* Legacy weak TxEventFifoCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register Rx Fifo 0 FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_RxFifo0Callback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the Rx Fifo 0 Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo0CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->RxFifo0Callback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Rx Fifo 0 FDCAN Callback
+  *         Rx Fifo 0 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo0Callback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->RxFifo0Callback = HAL_FDCAN_RxFifo0Callback; /* Legacy weak RxFifo0Callback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register Rx Fifo 1 FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_RxFifo1Callback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the Rx Fifo 1 Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo1CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->RxFifo1Callback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Rx Fifo 1 FDCAN Callback
+  *         Rx Fifo 1 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo1Callback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->RxFifo1Callback = HAL_FDCAN_RxFifo1Callback; /* Legacy weak RxFifo1Callback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register Tx Buffer Complete FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the Tx Buffer Complete Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferCompleteCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TxBufferCompleteCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Tx Buffer Complete FDCAN Callback
+  *         Tx Buffer Complete FDCAN Callback is redirected to the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TxBufferCompleteCallback = HAL_FDCAN_TxBufferCompleteCallback; /* Legacy weak TxBufferCompleteCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register Tx Buffer Abort FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the Tx Buffer Abort Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferAbortCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TxBufferAbortCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Tx Buffer Abort FDCAN Callback
+  *         Tx Buffer Abort FDCAN Callback is redirected to the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TxBufferAbortCallback = HAL_FDCAN_TxBufferAbortCallback; /* Legacy weak TxBufferAbortCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register Error Status FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_ErrorStatusCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the Error Status Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ErrorStatusCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->ErrorStatusCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Error Status FDCAN Callback
+  *         Error Status FDCAN Callback is redirected to the weak HAL_FDCAN_ErrorStatusCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->ErrorStatusCallback = HAL_FDCAN_ErrorStatusCallback; /* Legacy weak ErrorStatusCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register TT Schedule Synchronization FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_TT_ScheduleSyncCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the TT Schedule Synchronization Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_ScheduleSyncCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_ScheduleSyncCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the TT Schedule Synchronization FDCAN Callback
+  *         TT Schedule Synchronization Callback is redirected to the weak HAL_FDCAN_TT_ScheduleSyncCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_ScheduleSyncCallback = HAL_FDCAN_TT_ScheduleSyncCallback; /* Legacy weak TT_ScheduleSyncCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register TT Time Mark FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_TT_TimeMarkCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the TT Time Mark Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_TimeMarkCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_TimeMarkCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the TT Time Mark FDCAN Callback
+  *         TT Time Mark Callback is redirected to the weak HAL_FDCAN_TT_TimeMarkCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_TimeMarkCallback = HAL_FDCAN_TT_TimeMarkCallback; /* Legacy weak TT_TimeMarkCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register TT Stop Watch FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_TT_StopWatchCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the TT Stop Watch Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_StopWatchCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_StopWatchCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the TT Stop Watch FDCAN Callback
+  *         TT Stop Watch Callback is redirected to the weak HAL_FDCAN_TT_StopWatchCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_StopWatchCallback = HAL_FDCAN_TT_StopWatchCallback; /* Legacy weak TT_StopWatchCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register TT Global Time FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_TT_GlobalTimeCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the TT Global Time Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_GlobalTimeCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_GlobalTimeCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the TT Global Time FDCAN Callback
+  *         TT Global Time Callback is redirected to the weak HAL_FDCAN_TT_GlobalTimeCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_GlobalTimeCallback = HAL_FDCAN_TT_GlobalTimeCallback; /* Legacy weak TT_GlobalTimeCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Exported_Functions_Group2 Configuration functions
+ *  @brief    FDCAN Configuration functions.
+ *
+@verbatim
+  ==============================================================================
+              ##### Configuration functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) HAL_FDCAN_ConfigClockCalibration        : Configure the FDCAN clock calibration unit
+        (+) HAL_FDCAN_GetClockCalibrationState      : Get the clock calibration state
+        (+) HAL_FDCAN_ResetClockCalibrationState    : Reset the clock calibration state
+        (+) HAL_FDCAN_GetClockCalibrationCounter    : Get the clock calibration counters values
+      (+) HAL_FDCAN_ConfigFilter                  : Configure the FDCAN reception filters
+      (+) HAL_FDCAN_ConfigGlobalFilter            : Configure the FDCAN global filter
+      (+) HAL_FDCAN_ConfigExtendedIdMask          : Configure the extended ID mask
+      (+) HAL_FDCAN_ConfigRxFifoOverwrite         : Configure the Rx FIFO operation mode
+      (+) HAL_FDCAN_ConfigFifoWatermark           : Configure the FIFO watermark
+      (+) HAL_FDCAN_ConfigRamWatchdog             : Configure the RAM watchdog
+      (+) HAL_FDCAN_ConfigTimestampCounter        : Configure the timestamp counter
+        (+) HAL_FDCAN_EnableTimestampCounter        : Enable the timestamp counter
+        (+) HAL_FDCAN_DisableTimestampCounter       : Disable the timestamp counter
+        (+) HAL_FDCAN_GetTimestampCounter           : Get the timestamp counter value
+        (+) HAL_FDCAN_ResetTimestampCounter         : Reset the timestamp counter to zero
+      (+) HAL_FDCAN_ConfigTimeoutCounter          : Configure the timeout counter
+        (+) HAL_FDCAN_EnableTimeoutCounter          : Enable the timeout counter
+        (+) HAL_FDCAN_DisableTimeoutCounter         : Disable the timeout counter
+        (+) HAL_FDCAN_GetTimeoutCounter             : Get the timeout counter value
+        (+) HAL_FDCAN_ResetTimeoutCounter           : Reset the timeout counter to its start value
+      (+) HAL_FDCAN_ConfigTxDelayCompensation     : Configure the transmitter delay compensation
+        (+) HAL_FDCAN_EnableTxDelayCompensation     : Enable the transmitter delay compensation
+        (+) HAL_FDCAN_DisableTxDelayCompensation    : Disable the transmitter delay compensation
+      (+) HAL_FDCAN_EnableISOMode                 : Enable ISO 11898-1 protocol mode
+      (+) HAL_FDCAN_DisableISOMode                : Disable ISO 11898-1 protocol mode
+      (+) HAL_FDCAN_EnableEdgeFiltering           : Enable edge filtering during bus integration
+      (+) HAL_FDCAN_DisableEdgeFiltering          : Disable edge filtering during bus integration
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the FDCAN clock calibration unit according to the specified
+  *         parameters in the FDCAN_ClkCalUnitTypeDef structure.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  sCcuConfig pointer to an FDCAN_ClkCalUnitTypeDef structure that
+  *         contains the clock calibration information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigClockCalibration(FDCAN_HandleTypeDef *hfdcan, FDCAN_ClkCalUnitTypeDef *sCcuConfig)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_CLOCK_CALIBRATION(sCcuConfig->ClockCalibration));
+  if (sCcuConfig->ClockCalibration == FDCAN_CLOCK_CALIBRATION_DISABLE)
+  {
+    assert_param(IS_FDCAN_CKDIV(sCcuConfig->ClockDivider));
+  }
+  else
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(sCcuConfig->MinOscClkPeriods, 0xFFU));
+    assert_param(IS_FDCAN_CALIBRATION_FIELD_LENGTH(sCcuConfig->CalFieldLength));
+    assert_param(IS_FDCAN_MIN_VALUE(sCcuConfig->TimeQuantaPerBitTime, 4U));
+    assert_param(IS_FDCAN_MAX_VALUE(sCcuConfig->TimeQuantaPerBitTime, 0x25U));
+    assert_param(IS_FDCAN_MAX_VALUE(sCcuConfig->WatchdogStartValue, 0xFFFFU));
+  }
+
+  /* FDCAN1 should be initialized in order to use clock calibration */
+  if (hfdcan->Instance != FDCAN1)
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    if (sCcuConfig->ClockCalibration == FDCAN_CLOCK_CALIBRATION_DISABLE)
+    {
+      /* Bypass clock calibration */
+      SET_BIT(FDCAN_CCU->CCFG, FDCANCCU_CCFG_BCC);
+
+      /* Configure clock divider */
+      MODIFY_REG(FDCAN_CCU->CCFG, FDCANCCU_CCFG_CDIV, sCcuConfig->ClockDivider);
+    }
+    else /* sCcuConfig->ClockCalibration == ENABLE */
+    {
+      /* Clock calibration unit generates time quanta clock */
+      CLEAR_BIT(FDCAN_CCU->CCFG, FDCANCCU_CCFG_BCC);
+
+      /* Configure clock calibration unit */
+      MODIFY_REG(FDCAN_CCU->CCFG,
+                 (FDCANCCU_CCFG_TQBT | FDCANCCU_CCFG_CFL | FDCANCCU_CCFG_OCPM),
+                 ((sCcuConfig->TimeQuantaPerBitTime << FDCANCCU_CCFG_TQBT_Pos) | sCcuConfig->CalFieldLength | (sCcuConfig->MinOscClkPeriods << FDCANCCU_CCFG_OCPM_Pos)));
+
+      /* Configure the start value of the calibration watchdog counter */
+      MODIFY_REG(FDCAN_CCU->CWD, FDCANCCU_CWD_WDC, sCcuConfig->WatchdogStartValue);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get the clock calibration state.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval State clock calibration state (can be a value of @arg FDCAN_calibration_state)
+  */
+uint32_t HAL_FDCAN_GetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  return (FDCAN_CCU->CSTAT & FDCANCCU_CSTAT_CALS);
+}
+
+/**
+  * @brief  Reset the clock calibration state.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ResetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* FDCAN1 should be initialized in order to use clock calibration */
+  if (hfdcan->Instance != FDCAN1)
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Calibration software reset */
+    SET_BIT(FDCAN_CCU->CCFG, FDCANCCU_CCFG_SWR);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get the clock calibration counter value.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  Counter clock calibration counter.
+  *         This parameter can be a value of @arg FDCAN_calibration_counter.
+  * @retval Value clock calibration counter value
+  */
+uint32_t HAL_FDCAN_GetClockCalibrationCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t Counter)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_CALIBRATION_COUNTER(Counter));
+
+  if (Counter == FDCAN_CALIB_TIME_QUANTA_COUNTER)
+  {
+    return ((FDCAN_CCU->CSTAT & FDCANCCU_CSTAT_TQC) >> FDCANCCU_CSTAT_TQC_Pos);
+  }
+  else if (Counter == FDCAN_CALIB_CLOCK_PERIOD_COUNTER)
+  {
+    return (FDCAN_CCU->CSTAT & FDCANCCU_CSTAT_OCPC);
+  }
+  else /* Counter == FDCAN_CALIB_WATCHDOG_COUNTER */
+  {
+    return ((FDCAN_CCU->CWD & FDCANCCU_CWD_WDV) >> FDCANCCU_CWD_WDV_Pos);
+  }
+}
+
+/**
+  * @brief  Configure the FDCAN reception filter according to the specified
+  *         parameters in the FDCAN_FilterTypeDef structure.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  sFilterConfig pointer to an FDCAN_FilterTypeDef structure that
+  *         contains the filter configuration information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig)
+{
+  uint32_t FilterElementW1;
+  uint32_t FilterElementW2;
+  uint32_t *FilterAddress;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Check function parameters */
+    assert_param(IS_FDCAN_ID_TYPE(sFilterConfig->IdType));
+    assert_param(IS_FDCAN_FILTER_CFG(sFilterConfig->FilterConfig));
+    if (sFilterConfig->FilterConfig == FDCAN_FILTER_TO_RXBUFFER)
+    {
+      assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->RxBufferIndex, 63U));
+      assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->IsCalibrationMsg, 1U));
+    }
+
+    if (sFilterConfig->IdType == FDCAN_STANDARD_ID)
+    {
+      /* Check function parameters */
+      assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.StdFiltersNbr - 1U)));
+      assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x7FFU));
+      if (sFilterConfig->FilterConfig != FDCAN_FILTER_TO_RXBUFFER)
+      {
+        assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x7FFU));
+        assert_param(IS_FDCAN_STD_FILTER_TYPE(sFilterConfig->FilterType));
+      }
+
+      /* Build filter element */
+      if (sFilterConfig->FilterConfig == FDCAN_FILTER_TO_RXBUFFER)
+      {
+        FilterElementW1 = ((FDCAN_FILTER_TO_RXBUFFER << 27U)       |
+                           (sFilterConfig->FilterID1 << 16U)       |
+                           (sFilterConfig->IsCalibrationMsg << 8U) |
+                           sFilterConfig->RxBufferIndex);
+      }
+      else
+      {
+        FilterElementW1 = ((sFilterConfig->FilterType << 30U)   |
+                           (sFilterConfig->FilterConfig << 27U) |
+                           (sFilterConfig->FilterID1 << 16U)    |
+                           sFilterConfig->FilterID2);
+      }
+
+      /* Calculate filter address */
+      FilterAddress = (uint32_t *)(hfdcan->msgRam.StandardFilterSA + (sFilterConfig->FilterIndex * 4U));
+
+      /* Write filter element to the message RAM */
+      *FilterAddress = FilterElementW1;
+    }
+    else /* sFilterConfig->IdType == FDCAN_EXTENDED_ID */
+    {
+      /* Check function parameters */
+      assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.ExtFiltersNbr - 1U)));
+      assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x1FFFFFFFU));
+      if (sFilterConfig->FilterConfig != FDCAN_FILTER_TO_RXBUFFER)
+      {
+        assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x1FFFFFFFU));
+        assert_param(IS_FDCAN_EXT_FILTER_TYPE(sFilterConfig->FilterType));
+      }
+
+      /* Build first word of filter element */
+      FilterElementW1 = ((sFilterConfig->FilterConfig << 29U) | sFilterConfig->FilterID1);
+
+      /* Build second word of filter element */
+      if (sFilterConfig->FilterConfig == FDCAN_FILTER_TO_RXBUFFER)
+      {
+        FilterElementW2 = sFilterConfig->RxBufferIndex;
+      }
+      else
+      {
+        FilterElementW2 = ((sFilterConfig->FilterType << 30U) | sFilterConfig->FilterID2);
+      }
+
+      /* Calculate filter address */
+      FilterAddress = (uint32_t *)(hfdcan->msgRam.ExtendedFilterSA + (sFilterConfig->FilterIndex * 4U * 2U));
+
+      /* Write filter element to the message RAM */
+      *FilterAddress = FilterElementW1;
+      FilterAddress++;
+      *FilterAddress = FilterElementW2;
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the FDCAN global filter.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  NonMatchingStd Defines how received messages with 11-bit IDs that
+  *         do not match any element of the filter list are treated.
+  *         This parameter can be a value of @arg FDCAN_Non_Matching_Frames.
+  * @param  NonMatchingExt Defines how received messages with 29-bit IDs that
+  *         do not match any element of the filter list are treated.
+  *         This parameter can be a value of @arg FDCAN_Non_Matching_Frames.
+  * @param  RejectRemoteStd Filter or reject all the remote 11-bit IDs frames.
+  *         This parameter can be a value of @arg FDCAN_Reject_Remote_Frames.
+  * @param  RejectRemoteExt Filter or reject all the remote 29-bit IDs frames.
+  *         This parameter can be a value of @arg FDCAN_Reject_Remote_Frames.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan,
+                                               uint32_t NonMatchingStd,
+                                               uint32_t NonMatchingExt,
+                                               uint32_t RejectRemoteStd,
+                                               uint32_t RejectRemoteExt)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_NON_MATCHING(NonMatchingStd));
+  assert_param(IS_FDCAN_NON_MATCHING(NonMatchingExt));
+  assert_param(IS_FDCAN_REJECT_REMOTE(RejectRemoteStd));
+  assert_param(IS_FDCAN_REJECT_REMOTE(RejectRemoteExt));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Configure global filter */
+    hfdcan->Instance->GFC = ((NonMatchingStd << FDCAN_GFC_ANFS_Pos)  |
+                             (NonMatchingExt << FDCAN_GFC_ANFE_Pos)  |
+                             (RejectRemoteStd << FDCAN_GFC_RRFS_Pos) |
+                             (RejectRemoteExt << FDCAN_GFC_RRFE_Pos));
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the extended ID mask.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  Mask Extended ID Mask.
+  *         This parameter must be a number between 0 and 0x1FFFFFFF
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_MAX_VALUE(Mask, 0x1FFFFFFFU));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Configure the extended ID mask */
+    hfdcan->Instance->XIDAM = Mask;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the Rx FIFO operation mode.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  RxFifo Rx FIFO.
+  *         This parameter can be one of the following values:
+  *           @arg FDCAN_RX_FIFO0: Rx FIFO 0
+  *           @arg FDCAN_RX_FIFO1: Rx FIFO 1
+  * @param  OperationMode operation mode.
+  *         This parameter can be a value of @arg FDCAN_Rx_FIFO_operation_mode.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_RX_FIFO(RxFifo));
+  assert_param(IS_FDCAN_RX_FIFO_MODE(OperationMode));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    if (RxFifo == FDCAN_RX_FIFO0)
+    {
+      /* Select FIFO 0 Operation Mode */
+      MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0OM, OperationMode);
+    }
+    else /* RxFifo == FDCAN_RX_FIFO1 */
+    {
+      /* Select FIFO 1 Operation Mode */
+      MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1OM, OperationMode);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the FIFO watermark.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  FIFO select the FIFO to be configured.
+  *         This parameter can be a value of @arg FDCAN_FIFO_watermark.
+  * @param  Watermark level for FIFO watermark interrupt.
+  *         This parameter must be a number between:
+  *           - 0 and 32, if FIFO is FDCAN_CFG_TX_EVENT_FIFO
+  *           - 0 and 64, if FIFO is FDCAN_CFG_RX_FIFO0 or FDCAN_CFG_RX_FIFO1
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigFifoWatermark(FDCAN_HandleTypeDef *hfdcan, uint32_t FIFO, uint32_t Watermark)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_FIFO_WATERMARK(FIFO));
+  if (FIFO == FDCAN_CFG_TX_EVENT_FIFO)
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(Watermark, 32U));
+  }
+  else /* (FIFO == FDCAN_CFG_RX_FIFO0) || (FIFO == FDCAN_CFG_RX_FIFO1) */
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(Watermark, 64U));
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Set the level for FIFO watermark interrupt */
+    if (FIFO == FDCAN_CFG_TX_EVENT_FIFO)
+    {
+      MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFWM, (Watermark << FDCAN_TXEFC_EFWM_Pos));
+    }
+    else if (FIFO == FDCAN_CFG_RX_FIFO0)
+    {
+      MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0WM, (Watermark << FDCAN_RXF0C_F0WM_Pos));
+    }
+    else /* FIFO == FDCAN_CFG_RX_FIFO1 */
+    {
+      MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1WM, (Watermark << FDCAN_RXF1C_F1WM_Pos));
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the RAM watchdog.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  CounterStartValue Start value of the Message RAM Watchdog Counter,
+  *         This parameter must be a number between 0x00 and 0xFF,
+  *         with the reset value of 0x00 the counter is disabled.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_MAX_VALUE(CounterStartValue, 0xFFU));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Configure the RAM watchdog counter start value */
+    MODIFY_REG(hfdcan->Instance->RWD, FDCAN_RWD_WDC, CounterStartValue);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the timestamp counter.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TimestampPrescaler Timestamp Counter Prescaler.
+  *         This parameter can be a value of @arg FDCAN_Timestamp_Prescaler.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TIMESTAMP_PRESCALER(TimestampPrescaler));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Configure prescaler */
+    MODIFY_REG(hfdcan->Instance->TSCC, FDCAN_TSCC_TCP, TimestampPrescaler);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable the timestamp counter.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TimestampOperation Timestamp counter operation.
+  *         This parameter can be a value of @arg FDCAN_Timestamp.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TIMESTAMP(TimestampOperation));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Enable timestamp counter */
+    MODIFY_REG(hfdcan->Instance->TSCC, FDCAN_TSCC_TSS, TimestampOperation);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable the timestamp counter.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Disable timestamp counter */
+    CLEAR_BIT(hfdcan->Instance->TSCC, FDCAN_TSCC_TSS);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get the timestamp counter value.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval Value Timestamp counter value
+  */
+uint16_t HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+  return (uint16_t)(hfdcan->Instance->TSCV);
+}
+
+/**
+  * @brief  Reset the timestamp counter to zero.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+  if ((hfdcan->Instance->TSCC & FDCAN_TSCC_TSS) != FDCAN_TIMESTAMP_EXTERNAL)
+  {
+    /* Reset timestamp counter.
+       Actually any write operation to TSCV clears the counter */
+    CLEAR_REG(hfdcan->Instance->TSCV);
+  }
+  else
+  {
+    /* Update error code.
+       Unable to reset external counter */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+    return HAL_ERROR;
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the timeout counter.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TimeoutOperation Timeout counter operation.
+  *         This parameter can be a value of @arg FDCAN_Timeout_Operation.
+  * @param  TimeoutPeriod Start value of the timeout down-counter.
+  *         This parameter must be a number between 0x0000 and 0xFFFF
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TIMEOUT(TimeoutOperation));
+  assert_param(IS_FDCAN_MAX_VALUE(TimeoutPeriod, 0xFFFFU));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Select timeout operation and configure period */
+    MODIFY_REG(hfdcan->Instance->TOCC, (FDCAN_TOCC_TOS | FDCAN_TOCC_TOP), (TimeoutOperation | (TimeoutPeriod << FDCAN_TOCC_TOP_Pos)));
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable the timeout counter.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Enable timeout counter */
+    SET_BIT(hfdcan->Instance->TOCC, FDCAN_TOCC_ETOC);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable the timeout counter.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Disable timeout counter */
+    CLEAR_BIT(hfdcan->Instance->TOCC, FDCAN_TOCC_ETOC);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get the timeout counter value.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval Value Timeout counter value
+  */
+uint16_t HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+  return (uint16_t)(hfdcan->Instance->TOCV);
+}
+
+/**
+  * @brief  Reset the timeout counter to its start value.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+  if ((hfdcan->Instance->TOCC & FDCAN_TOCC_TOS) == FDCAN_TIMEOUT_CONTINUOUS)
+  {
+    /* Reset timeout counter to start value */
+    CLEAR_REG(hfdcan->Instance->TOCV);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code.
+       Unable to reset counter: controlled only by FIFO empty state */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the transmitter delay compensation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TdcOffset Transmitter Delay Compensation Offset.
+  *         This parameter must be a number between 0x00 and 0x7F.
+  * @param  TdcFilter Transmitter Delay Compensation Filter Window Length.
+  *         This parameter must be a number between 0x00 and 0x7F.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_MAX_VALUE(TdcOffset, 0x7FU));
+  assert_param(IS_FDCAN_MAX_VALUE(TdcFilter, 0x7FU));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Configure TDC offset and filter window */
+    hfdcan->Instance->TDCR = ((TdcFilter << FDCAN_TDCR_TDCF_Pos) | (TdcOffset << FDCAN_TDCR_TDCO_Pos));
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable the transmitter delay compensation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Enable transmitter delay compensation */
+    SET_BIT(hfdcan->Instance->DBTP, FDCAN_DBTP_TDC);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable the transmitter delay compensation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Disable transmitter delay compensation */
+    CLEAR_BIT(hfdcan->Instance->DBTP, FDCAN_DBTP_TDC);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable ISO 11898-1 protocol mode.
+  *         CAN FD frame format is according to ISO 11898-1 standard.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Disable Non ISO protocol mode */
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_NISO);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable ISO 11898-1 protocol mode.
+  *         CAN FD frame format is according to Bosch CAN FD specification V1.0.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Enable Non ISO protocol mode */
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_NISO);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable edge filtering during bus integration.
+  *         Two consecutive dominant tq are required to detect an edge for hard synchronization.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Enable edge filtering */
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_EFBI);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable edge filtering during bus integration.
+  *         One dominant tq is required to detect an edge for hard synchronization.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Disable edge filtering */
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_EFBI);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Exported_Functions_Group3 Control functions
+ *  @brief    Control functions
+ *
+@verbatim
+  ==============================================================================
+                          ##### Control functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) HAL_FDCAN_Start                         : Start the FDCAN module
+      (+) HAL_FDCAN_Stop                          : Stop the FDCAN module and enable access to configuration registers
+      (+) HAL_FDCAN_AddMessageToTxFifoQ           : Add a message to the Tx FIFO/Queue and activate the corresponding transmission request
+      (+) HAL_FDCAN_AddMessageToTxBuffer          : Add a message to a dedicated Tx buffer
+      (+) HAL_FDCAN_EnableTxBufferRequest         : Enable transmission request
+      (+) HAL_FDCAN_GetLatestTxFifoQRequestBuffer : Get Tx buffer index of latest Tx FIFO/Queue request
+      (+) HAL_FDCAN_AbortTxRequest                : Abort transmission request
+      (+) HAL_FDCAN_GetRxMessage                  : Get an FDCAN frame from the Rx Buffer/FIFO zone into the message RAM
+      (+) HAL_FDCAN_GetTxEvent                    : Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM
+      (+) HAL_FDCAN_GetHighPriorityMessageStatus  : Get high priority message status
+      (+) HAL_FDCAN_GetProtocolStatus             : Get protocol status
+      (+) HAL_FDCAN_GetErrorCounters              : Get error counter values
+      (+) HAL_FDCAN_IsRxBufferMessageAvailable    : Check if a new message is received in the selected Rx buffer
+      (+) HAL_FDCAN_IsTxBufferMessagePending      : Check if a transmission request is pending on the selected Tx buffer
+      (+) HAL_FDCAN_GetRxFifoFillLevel            : Return Rx FIFO fill level
+      (+) HAL_FDCAN_GetTxFifoFreeLevel            : Return Tx FIFO free level
+      (+) HAL_FDCAN_IsRestrictedOperationMode     : Check if the FDCAN peripheral entered Restricted Operation Mode
+      (+) HAL_FDCAN_ExitRestrictedOperationMode   : Exit Restricted Operation Mode
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Start the FDCAN module.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Change FDCAN peripheral state */
+    hfdcan->State = HAL_FDCAN_STATE_BUSY;
+
+    /* Request leave initialisation */
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
+
+    /* Reset the FDCAN ErrorCode */
+    hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Stop the FDCAN module and enable access to configuration registers.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
+  {
+    /* Request initialisation */
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
+
+    /* Wait until the INIT bit into CCCR register is set */
+    while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Reset counter */
+    Counter = 0U;
+
+    /* Exit from Sleep mode */
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
+
+    /* Wait until FDCAN exits sleep mode */
+    while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Enable configuration change */
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE);
+
+    /* Reset Latest Tx FIFO/Queue Request Buffer Index */
+    hfdcan->LatestTxFifoQRequest = 0U;
+
+    /* Change FDCAN peripheral state */
+    hfdcan->State = HAL_FDCAN_STATE_READY;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Add a message to the Tx FIFO/Queue and activate the corresponding transmission request
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure.
+  * @param  pTxData pointer to a buffer containing the payload of the Tx frame.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData)
+{
+  uint32_t PutIndex;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_ID_TYPE(pTxHeader->IdType));
+  if (pTxHeader->IdType == FDCAN_STANDARD_ID)
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x7FFU));
+  }
+  else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x1FFFFFFFU));
+  }
+  assert_param(IS_FDCAN_FRAME_TYPE(pTxHeader->TxFrameType));
+  assert_param(IS_FDCAN_DLC(pTxHeader->DataLength));
+  assert_param(IS_FDCAN_ESI(pTxHeader->ErrorStateIndicator));
+  assert_param(IS_FDCAN_BRS(pTxHeader->BitRateSwitch));
+  assert_param(IS_FDCAN_FDF(pTxHeader->FDFormat));
+  assert_param(IS_FDCAN_EFC(pTxHeader->TxEventFifoControl));
+  assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->MessageMarker, 0xFFU));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
+  {
+    /* Check that the Tx FIFO/Queue has an allocated area into the RAM */
+    if ((hfdcan->Instance->TXBC & FDCAN_TXBC_TFQS) == 0U)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+      return HAL_ERROR;
+    }
+
+    /* Check that the Tx FIFO/Queue is not full */
+    if ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQF) != 0U)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_FULL;
+
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Retrieve the Tx FIFO PutIndex */
+      PutIndex = ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQPI) >> FDCAN_TXFQS_TFQPI_Pos);
+
+      /* Add the message to the Tx FIFO/Queue */
+      FDCAN_CopyMessageToRAM(hfdcan, pTxHeader, pTxData, PutIndex);
+
+      /* Activate the corresponding transmission request */
+      hfdcan->Instance->TXBAR = ((uint32_t)1 << PutIndex);
+
+      /* Store the Latest Tx FIFO/Queue Request Buffer Index */
+      hfdcan->LatestTxFifoQRequest = ((uint32_t)1 << PutIndex);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Add a message to a dedicated Tx buffer
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure.
+  * @param  pTxData pointer to a buffer containing the payload of the Tx frame.
+  * @param  BufferIndex index of the buffer to be configured.
+  *         This parameter can be a value of @arg FDCAN_Tx_location.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxBuffer(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex)
+{
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_ID_TYPE(pTxHeader->IdType));
+  if (pTxHeader->IdType == FDCAN_STANDARD_ID)
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x7FFU));
+  }
+  else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x1FFFFFFFU));
+  }
+  assert_param(IS_FDCAN_FRAME_TYPE(pTxHeader->TxFrameType));
+  assert_param(IS_FDCAN_DLC(pTxHeader->DataLength));
+  assert_param(IS_FDCAN_ESI(pTxHeader->ErrorStateIndicator));
+  assert_param(IS_FDCAN_BRS(pTxHeader->BitRateSwitch));
+  assert_param(IS_FDCAN_FDF(pTxHeader->FDFormat));
+  assert_param(IS_FDCAN_EFC(pTxHeader->TxEventFifoControl));
+  assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->MessageMarker, 0xFFU));
+  assert_param(IS_FDCAN_TX_LOCATION(BufferIndex));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Check that the selected buffer has an allocated area into the RAM */
+    if (POSITION_VAL(BufferIndex) >= ((hfdcan->Instance->TXBC & FDCAN_TXBC_NDTB) >> FDCAN_TXBC_NDTB_Pos))
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+      return HAL_ERROR;
+    }
+
+    /* Check that there is no transmittion request pending for the selected buffer */
+    if ((hfdcan->Instance->TXBRP & BufferIndex) != 0U)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING;
+
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Add the message to the Tx buffer */
+      FDCAN_CopyMessageToRAM(hfdcan, pTxHeader, pTxData, POSITION_VAL(BufferIndex));
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable transmission request.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  BufferIndex buffer index.
+  *         This parameter can be any combination of @arg FDCAN_Tx_location.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_EnableTxBufferRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
+  {
+    /* Add transmission request */
+    hfdcan->Instance->TXBAR = BufferIndex;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get Tx buffer index of latest Tx FIFO/Queue request
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval Tx buffer index of last Tx FIFO/Queue request
+  *          - Any value of @arg FDCAN_Tx_location if Tx request has been submitted.
+  *          - 0 if no Tx FIFO/Queue request have been submitted.
+  */
+uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Return Last Tx FIFO/Queue Request Buffer */
+  return hfdcan->LatestTxFifoQRequest;
+}
+
+/**
+  * @brief  Abort transmission request
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  BufferIndex buffer index.
+  *         This parameter can be any combination of @arg FDCAN_Tx_location.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
+  {
+    /* Add cancellation request */
+    hfdcan->Instance->TXBCR = BufferIndex;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get an FDCAN frame from the Rx Buffer/FIFO zone into the message RAM.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  RxLocation Location of the received message to be read.
+  *         This parameter can be a value of @arg FDCAN_Rx_location.
+  * @param  pRxHeader pointer to a FDCAN_RxHeaderTypeDef structure.
+  * @param  pRxData pointer to a buffer where the payload of the Rx frame will be stored.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData)
+{
+  uint32_t *RxAddress;
+  uint8_t  *pData;
+  uint32_t ByteCounter;
+  uint32_t GetIndex = 0;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  if (state == HAL_FDCAN_STATE_BUSY)
+  {
+    if (RxLocation == FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */
+    {
+      /* Check that the Rx FIFO 0 has an allocated area into the RAM */
+      if ((hfdcan->Instance->RXF0C & FDCAN_RXF0C_F0S) == 0U)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+        return HAL_ERROR;
+      }
+
+      /* Check that the Rx FIFO 0 is not empty */
+      if ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0FL) == 0U)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
+
+        return HAL_ERROR;
+      }
+      else
+      {
+        /* Calculate Rx FIFO 0 element address */
+        GetIndex = ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0GI) >> FDCAN_RXF0S_F0GI_Pos);
+        RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO0SA + (GetIndex * hfdcan->Init.RxFifo0ElmtSize * 4U));
+      }
+    }
+    else if (RxLocation == FDCAN_RX_FIFO1) /* Rx element is assigned to the Rx FIFO 1 */
+    {
+      /* Check that the Rx FIFO 1 has an allocated area into the RAM */
+      if ((hfdcan->Instance->RXF1C & FDCAN_RXF1C_F1S) == 0U)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+        return HAL_ERROR;
+      }
+
+      /* Check that the Rx FIFO 0 is not empty */
+      if ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL) == 0U)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
+
+        return HAL_ERROR;
+      }
+      else
+      {
+        /* Calculate Rx FIFO 1 element address */
+        GetIndex = ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1GI) >> FDCAN_RXF1S_F1GI_Pos);
+        RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO1SA + (GetIndex * hfdcan->Init.RxFifo1ElmtSize * 4U));
+      }
+    }
+    else /* Rx element is assigned to a dedicated Rx buffer */
+    {
+      /* Check that the selected buffer has an allocated area into the RAM */
+      if (RxLocation >= hfdcan->Init.RxBuffersNbr)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+        return HAL_ERROR;
+      }
+      else
+      {
+        /* Calculate Rx buffer address */
+        RxAddress = (uint32_t *)(hfdcan->msgRam.RxBufferSA + (RxLocation * hfdcan->Init.RxBufferSize * 4U));
+      }
+    }
+
+    /* Retrieve IdType */
+    pRxHeader->IdType = *RxAddress & FDCAN_ELEMENT_MASK_XTD;
+
+    /* Retrieve Identifier */
+    if (pRxHeader->IdType == FDCAN_STANDARD_ID) /* Standard ID element */
+    {
+      pRxHeader->Identifier = ((*RxAddress & FDCAN_ELEMENT_MASK_STDID) >> 18);
+    }
+    else /* Extended ID element */
+    {
+      pRxHeader->Identifier = (*RxAddress & FDCAN_ELEMENT_MASK_EXTID);
+    }
+
+    /* Retrieve RxFrameType */
+    pRxHeader->RxFrameType = (*RxAddress & FDCAN_ELEMENT_MASK_RTR);
+
+    /* Retrieve ErrorStateIndicator */
+    pRxHeader->ErrorStateIndicator = (*RxAddress & FDCAN_ELEMENT_MASK_ESI);
+
+    /* Increment RxAddress pointer to second word of Rx FIFO element */
+    RxAddress++;
+
+    /* Retrieve RxTimestamp */
+    pRxHeader->RxTimestamp = (*RxAddress & FDCAN_ELEMENT_MASK_TS);
+
+    /* Retrieve DataLength */
+    pRxHeader->DataLength = (*RxAddress & FDCAN_ELEMENT_MASK_DLC);
+
+    /* Retrieve BitRateSwitch */
+    pRxHeader->BitRateSwitch = (*RxAddress & FDCAN_ELEMENT_MASK_BRS);
+
+    /* Retrieve FDFormat */
+    pRxHeader->FDFormat = (*RxAddress & FDCAN_ELEMENT_MASK_FDF);
+
+    /* Retrieve FilterIndex */
+    pRxHeader->FilterIndex = ((*RxAddress & FDCAN_ELEMENT_MASK_FIDX) >> 24);
+
+    /* Retrieve NonMatchingFrame */
+    pRxHeader->IsFilterMatchingFrame = ((*RxAddress & FDCAN_ELEMENT_MASK_ANMF) >> 31);
+
+    /* Increment RxAddress pointer to payload of Rx FIFO element */
+    RxAddress++;
+
+    /* Retrieve Rx payload */
+    pData = (uint8_t *)RxAddress;
+    for (ByteCounter = 0; ByteCounter < DLCtoBytes[pRxHeader->DataLength >> 16]; ByteCounter++)
+    {
+      pRxData[ByteCounter] = pData[ByteCounter];
+    }
+
+    if (RxLocation == FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */
+    {
+      /* Acknowledge the Rx FIFO 0 that the oldest element is read so that it increments the GetIndex */
+      hfdcan->Instance->RXF0A = GetIndex;
+    }
+    else if (RxLocation == FDCAN_RX_FIFO1) /* Rx element is assigned to the Rx FIFO 1 */
+    {
+      /* Acknowledge the Rx FIFO 1 that the oldest element is read so that it increments the GetIndex */
+      hfdcan->Instance->RXF1A = GetIndex;
+    }
+    else /* Rx element is assigned to a dedicated Rx buffer */
+    {
+      /* Clear the New Data flag of the current Rx buffer */
+      if (RxLocation < FDCAN_RX_BUFFER32)
+      {
+        hfdcan->Instance->NDAT1 = ((uint32_t)1 << RxLocation);
+      }
+      else /* FDCAN_RX_BUFFER32 <= RxLocation <= FDCAN_RX_BUFFER63 */
+      {
+        hfdcan->Instance->NDAT2 = ((uint32_t)1 << (RxLocation & 0x1FU));
+      }
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  pTxEvent pointer to a FDCAN_TxEventFifoTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent)
+{
+  uint32_t *TxEventAddress;
+  uint32_t GetIndex;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_MIN_VALUE(hfdcan->Init.TxEventsNbr, 1U));
+
+  if (state == HAL_FDCAN_STATE_BUSY)
+  {
+    /* Check that the Tx Event FIFO has an allocated area into the RAM */
+    if ((hfdcan->Instance->TXEFC & FDCAN_TXEFC_EFS) == 0U)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+      return HAL_ERROR;
+    }
+
+    /* Check that the Tx event FIFO is not empty */
+    if ((hfdcan->Instance->TXEFS & FDCAN_TXEFS_EFFL) == 0U)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
+
+      return HAL_ERROR;
+    }
+
+    /* Calculate Tx event FIFO element address */
+    GetIndex = ((hfdcan->Instance->TXEFS & FDCAN_TXEFS_EFGI) >> FDCAN_TXEFS_EFGI_Pos);
+    TxEventAddress = (uint32_t *)(hfdcan->msgRam.TxEventFIFOSA + (GetIndex * 2U * 4U));
+
+    /* Retrieve IdType */
+    pTxEvent->IdType = *TxEventAddress & FDCAN_ELEMENT_MASK_XTD;
+
+    /* Retrieve Identifier */
+    if (pTxEvent->IdType == FDCAN_STANDARD_ID) /* Standard ID element */
+    {
+      pTxEvent->Identifier = ((*TxEventAddress & FDCAN_ELEMENT_MASK_STDID) >> 18U);
+    }
+    else /* Extended ID element */
+    {
+      pTxEvent->Identifier = (*TxEventAddress & FDCAN_ELEMENT_MASK_EXTID);
+    }
+
+    /* Retrieve RxFrameType */
+    pTxEvent->TxFrameType = (*TxEventAddress & FDCAN_ELEMENT_MASK_RTR);
+
+    /* Retrieve ErrorStateIndicator */
+    pTxEvent->ErrorStateIndicator = (*TxEventAddress & FDCAN_ELEMENT_MASK_ESI);
+
+    /* Increment TxEventAddress pointer to second word of Tx Event FIFO element */
+    TxEventAddress++;
+
+    /* Retrieve RxTimestamp */
+    pTxEvent->TxTimestamp = (*TxEventAddress & FDCAN_ELEMENT_MASK_TS);
+
+    /* Retrieve DataLength */
+    pTxEvent->DataLength = (*TxEventAddress & FDCAN_ELEMENT_MASK_DLC);
+
+    /* Retrieve BitRateSwitch */
+    pTxEvent->BitRateSwitch = (*TxEventAddress & FDCAN_ELEMENT_MASK_BRS);
+
+    /* Retrieve FDFormat */
+    pTxEvent->FDFormat = (*TxEventAddress & FDCAN_ELEMENT_MASK_FDF);
+
+    /* Retrieve EventType */
+    pTxEvent->EventType = (*TxEventAddress & FDCAN_ELEMENT_MASK_ET);
+
+    /* Retrieve MessageMarker */
+    pTxEvent->MessageMarker = ((*TxEventAddress & FDCAN_ELEMENT_MASK_MM) >> 24);
+
+    /* Acknowledge the Tx Event FIFO that the oldest element is read so that it increments the GetIndex */
+    hfdcan->Instance->TXEFA = GetIndex;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get high priority message status.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  HpMsgStatus pointer to an FDCAN_HpMsgStatusTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus)
+{
+  HpMsgStatus->FilterList = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FLST) >> FDCAN_HPMS_FLST_Pos);
+  HpMsgStatus->FilterIndex = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FIDX) >> FDCAN_HPMS_FIDX_Pos);
+  HpMsgStatus->MessageStorage = (hfdcan->Instance->HPMS & FDCAN_HPMS_MSI);
+  HpMsgStatus->MessageIndex = (hfdcan->Instance->HPMS & FDCAN_HPMS_BIDX);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get protocol status.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  ProtocolStatus pointer to an FDCAN_ProtocolStatusTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus)
+{
+  uint32_t StatusReg;
+
+  /* Read the protocol status register */
+  StatusReg = READ_REG(hfdcan->Instance->PSR);
+
+  /* Fill the protocol status structure */
+  ProtocolStatus->LastErrorCode = (StatusReg & FDCAN_PSR_LEC);
+  ProtocolStatus->DataLastErrorCode = ((StatusReg & FDCAN_PSR_DLEC) >> FDCAN_PSR_DLEC_Pos);
+  ProtocolStatus->Activity = (StatusReg & FDCAN_PSR_ACT);
+  ProtocolStatus->ErrorPassive = ((StatusReg & FDCAN_PSR_EP) >> FDCAN_PSR_EP_Pos);
+  ProtocolStatus->Warning = ((StatusReg & FDCAN_PSR_EW) >> FDCAN_PSR_EW_Pos);
+  ProtocolStatus->BusOff = ((StatusReg & FDCAN_PSR_BO) >> FDCAN_PSR_BO_Pos);
+  ProtocolStatus->RxESIflag = ((StatusReg & FDCAN_PSR_RESI) >> FDCAN_PSR_RESI_Pos);
+  ProtocolStatus->RxBRSflag = ((StatusReg & FDCAN_PSR_RBRS) >> FDCAN_PSR_RBRS_Pos);
+  ProtocolStatus->RxFDFflag = ((StatusReg & FDCAN_PSR_REDL) >> FDCAN_PSR_REDL_Pos);
+  ProtocolStatus->ProtocolException = ((StatusReg & FDCAN_PSR_PXE) >> FDCAN_PSR_PXE_Pos);
+  ProtocolStatus->TDCvalue = ((StatusReg & FDCAN_PSR_TDCV) >> FDCAN_PSR_TDCV_Pos);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get error counter values.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  ErrorCounters pointer to an FDCAN_ErrorCountersTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters)
+{
+  uint32_t CountersReg;
+
+  /* Read the error counters register */
+  CountersReg = READ_REG(hfdcan->Instance->ECR);
+
+  /* Fill the error counters structure */
+  ErrorCounters->TxErrorCnt = ((CountersReg & FDCAN_ECR_TEC) >> FDCAN_ECR_TEC_Pos);
+  ErrorCounters->RxErrorCnt = ((CountersReg & FDCAN_ECR_REC) >> FDCAN_ECR_REC_Pos);
+  ErrorCounters->RxErrorPassive = ((CountersReg & FDCAN_ECR_RP) >> FDCAN_ECR_RP_Pos);
+  ErrorCounters->ErrorLogging = ((CountersReg & FDCAN_ECR_CEL) >> FDCAN_ECR_CEL_Pos);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Check if a new message is received in the selected Rx buffer.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  RxBufferIndex Rx buffer index.
+  *         This parameter must be a number between 0 and 63.
+  * @retval Status
+  *          - 0 : No new message on RxBufferIndex.
+  *          - 1 : New message received on RxBufferIndex.
+  */
+uint32_t HAL_FDCAN_IsRxBufferMessageAvailable(FDCAN_HandleTypeDef *hfdcan, uint32_t RxBufferIndex)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_MAX_VALUE(RxBufferIndex, 63U));
+  uint32_t NewData1 = hfdcan->Instance->NDAT1;
+  uint32_t NewData2 = hfdcan->Instance->NDAT2;
+
+  /* Check new message reception on the selected buffer */
+  if (((RxBufferIndex < 32U) && ((NewData1 & (uint32_t)((uint32_t)1 << RxBufferIndex)) == 0U)) ||
+      ((RxBufferIndex >= 32U) && ((NewData2 & (uint32_t)((uint32_t)1 << (RxBufferIndex & 0x1FU))) == 0U)))
+  {
+    return 0;
+  }
+
+  /* Clear the New Data flag of the current Rx buffer */
+  if (RxBufferIndex < 32U)
+  {
+    hfdcan->Instance->NDAT1 = ((uint32_t)1 << RxBufferIndex);
+  }
+  else /* 32 <= RxBufferIndex <= 63 */
+  {
+    hfdcan->Instance->NDAT2 = ((uint32_t)1 << (RxBufferIndex & 0x1FU));
+  }
+
+  return 1;
+}
+
+/**
+  * @brief  Check if a transmission request is pending on the selected Tx buffer.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TxBufferIndex Tx buffer index.
+  *         This parameter can be any combination of @arg FDCAN_Tx_location.
+  * @retval Status
+  *          - 0 : No pending transmission request on TxBufferIndex.
+  *          - 1 : Pending transmission request on TxBufferIndex.
+  */
+uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex)
+{
+  /* Check pending transmittion request on the selected buffer */
+  if ((hfdcan->Instance->TXBRP & TxBufferIndex) == 0U)
+  {
+    return 0;
+  }
+  return 1;
+}
+
+/**
+  * @brief  Return Rx FIFO fill level.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  RxFifo Rx FIFO.
+  *         This parameter can be one of the following values:
+  *           @arg FDCAN_RX_FIFO0: Rx FIFO 0
+  *           @arg FDCAN_RX_FIFO1: Rx FIFO 1
+  * @retval Level Rx FIFO fill level.
+  */
+uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo)
+{
+  uint32_t FillLevel;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_RX_FIFO(RxFifo));
+
+  if (RxFifo == FDCAN_RX_FIFO0)
+  {
+    FillLevel = hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0FL;
+  }
+  else /* RxFifo == FDCAN_RX_FIFO1 */
+  {
+    FillLevel = hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL;
+  }
+
+  /* Return Rx FIFO fill level */
+  return FillLevel;
+}
+
+/**
+  * @brief  Return Tx FIFO free level: number of consecutive free Tx FIFO
+  *         elements starting from Tx FIFO GetIndex.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval Level Tx FIFO free level.
+  */
+uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t FreeLevel;
+
+  FreeLevel = hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFFL;
+
+  /* Return Tx FIFO free level */
+  return FreeLevel;
+}
+
+/**
+  * @brief  Check if the FDCAN peripheral entered Restricted Operation Mode.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval Status
+  *          - 0 : Normal FDCAN operation.
+  *          - 1 : Restricted Operation Mode active.
+  */
+uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t OperationMode;
+
+  /* Get Operation Mode */
+  OperationMode = ((hfdcan->Instance->CCCR & FDCAN_CCCR_ASM) >> FDCAN_CCCR_ASM_Pos);
+
+  return OperationMode;
+}
+
+/**
+  * @brief  Exit Restricted Operation Mode.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Exit Restricted Operation mode */
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Exported_Functions_Group4 TT Configuration and control functions
+ *  @brief    TT Configuration and control functions
+ *
+@verbatim
+  ==============================================================================
+              ##### TT Configuration and control functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) HAL_FDCAN_TT_ConfigOperation                  : Initialize TT operation parameters
+      (+) HAL_FDCAN_TT_ConfigReferenceMessage           : Configure the reference message
+      (+) HAL_FDCAN_TT_ConfigTrigger                    : Configure the FDCAN trigger
+      (+) HAL_FDCAN_TT_SetGlobalTime                    : Schedule global time adjustment
+      (+) HAL_FDCAN_TT_SetClockSynchronization          : Schedule TUR numerator update
+      (+) HAL_FDCAN_TT_ConfigStopWatch                  : Configure stop watch source and polarity
+      (+) HAL_FDCAN_TT_ConfigRegisterTimeMark           : Configure register time mark pulse generation
+        (+) HAL_FDCAN_TT_EnableRegisterTimeMarkPulse      : Enable register time mark pulse generation
+        (+) HAL_FDCAN_TT_DisableRegisterTimeMarkPulse     : Disable register time mark pulse generation
+      (+) HAL_FDCAN_TT_EnableTriggerTimeMarkPulse       : Enable trigger time mark pulse generation
+      (+) HAL_FDCAN_TT_DisableTriggerTimeMarkPulse      : Disable trigger time mark pulse generation
+      (+) HAL_FDCAN_TT_EnableHardwareGapControl         : Enable gap control by input pin fdcan1_evt
+      (+) HAL_FDCAN_TT_DisableHardwareGapControl        : Disable gap control by input pin fdcan1_evt
+      (+) HAL_FDCAN_TT_EnableTimeMarkGapControl         : Enable gap control (finish only) by register time mark interrupt
+      (+) HAL_FDCAN_TT_DisableTimeMarkGapControl        : Disable gap control by register time mark interrupt
+      (+) HAL_FDCAN_TT_SetNextIsGap                     : Transmit next reference message with Next_is_Gap = "1"
+      (+) HAL_FDCAN_TT_SetEndOfGap                      : Finish a Gap by requesting start of reference message
+      (+) HAL_FDCAN_TT_ConfigExternalSyncPhase          : Configure target phase used for external synchronization
+        (+) HAL_FDCAN_TT_EnableExternalSynchronization    : Synchronize the phase of the FDCAN schedule to an external schedule
+        (+) HAL_FDCAN_TT_DisableExternalSynchronization   : Disable external schedule synchronization
+      (+) HAL_FDCAN_TT_GetOperationStatus               : Get TT operation status
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize TT operation parameters.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  pTTParams pointer to a FDCAN_TT_ConfigTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigOperation(FDCAN_HandleTypeDef *hfdcan, FDCAN_TT_ConfigTypeDef *pTTParams)
+{
+  uint32_t tickstart;
+  uint32_t RAMcounter;
+  uint32_t StartAddress;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_TUR_NUMERATOR(pTTParams->TURNumerator));
+  assert_param(IS_FDCAN_TT_TUR_DENOMINATOR(pTTParams->TURDenominator));
+  assert_param(IS_FDCAN_TT_TIME_MASTER(pTTParams->TimeMaster));
+  assert_param(IS_FDCAN_MAX_VALUE(pTTParams->SyncDevLimit, 7U));
+  assert_param(IS_FDCAN_MAX_VALUE(pTTParams->InitRefTrigOffset, 127U));
+  assert_param(IS_FDCAN_MAX_VALUE(pTTParams->TriggerMemoryNbr, 64U));
+  assert_param(IS_FDCAN_TT_CYCLE_START_SYNC(pTTParams->CycleStartSync));
+  assert_param(IS_FDCAN_TT_STOP_WATCH_TRIGGER(pTTParams->StopWatchTrigSel));
+  assert_param(IS_FDCAN_TT_EVENT_TRIGGER(pTTParams->EventTrigSel));
+  if (pTTParams->TimeMaster == FDCAN_TT_POTENTIAL_MASTER)
+  {
+    assert_param(IS_FDCAN_TT_BASIC_CYCLES_NUMBER(pTTParams->BasicCyclesNbr));
+  }
+  if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL0)
+  {
+    assert_param(IS_FDCAN_TT_OPERATION(pTTParams->GapEnable));
+    assert_param(IS_FDCAN_MAX_VALUE(pTTParams->AppWdgLimit, 255U));
+    assert_param(IS_FDCAN_TT_EVENT_TRIGGER_POLARITY(pTTParams->EvtTrigPolarity));
+    assert_param(IS_FDCAN_TT_TX_ENABLE_WINDOW(pTTParams->TxEnableWindow));
+    assert_param(IS_FDCAN_MAX_VALUE(pTTParams->ExpTxTrigNbr, 4095U));
+  }
+  if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL1)
+  {
+    assert_param(IS_FDCAN_TT_TUR_LEVEL_0_2(pTTParams->TURNumerator, pTTParams->TURDenominator));
+    assert_param(IS_FDCAN_TT_EXTERNAL_CLK_SYNC(pTTParams->ExternalClkSync));
+    assert_param(IS_FDCAN_TT_GLOBAL_TIME_FILTERING(pTTParams->GlobalTimeFilter));
+    assert_param(IS_FDCAN_TT_AUTO_CLK_CALIBRATION(pTTParams->ClockCalibration));
+  }
+  else
+  {
+    assert_param(IS_FDCAN_TT_TUR_LEVEL_1(pTTParams->TURNumerator, pTTParams->TURDenominator));
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Stop local time in order to enable write access to the other bits of TURCF register */
+    CLEAR_BIT(hfdcan->ttcan->TURCF, FDCAN_TURCF_ELT);
+
+    /* Get tick */
+    tickstart = HAL_GetTick();
+
+    /* Wait until the ELT bit into TURCF register is reset */
+    while ((hfdcan->ttcan->TURCF & FDCAN_TURCF_ELT) != 0U)
+    {
+      /* Check for the Timeout */
+      if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+    }
+
+    /* Configure TUR (Time Unit Ratio) */
+    MODIFY_REG(hfdcan->ttcan->TURCF,
+               (FDCAN_TURCF_NCL | FDCAN_TURCF_DC),
+               (((pTTParams->TURNumerator - 0x10000U) << FDCAN_TURCF_NCL_Pos) | (pTTParams->TURDenominator << FDCAN_TURCF_DC_Pos)));
+
+    /* Enable local time */
+    SET_BIT(hfdcan->ttcan->TURCF, FDCAN_TURCF_ELT);
+
+    /* Configure TT operation */
+    MODIFY_REG(hfdcan->ttcan->TTOCF,
+               (FDCAN_TTOCF_OM | FDCAN_TTOCF_TM | FDCAN_TTOCF_LDSDL | FDCAN_TTOCF_IRTO),
+               (pTTParams->OperationMode                           | \
+                pTTParams->TimeMaster                              | \
+                (pTTParams->SyncDevLimit << FDCAN_TTOCF_LDSDL_Pos) | \
+                (pTTParams->InitRefTrigOffset << FDCAN_TTOCF_IRTO_Pos)));
+    if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      MODIFY_REG(hfdcan->ttcan->TTOCF,
+                 (FDCAN_TTOCF_GEN | FDCAN_TTOCF_AWL | FDCAN_TTOCF_EVTP),
+                 (pTTParams->GapEnable                            | \
+                  (pTTParams->AppWdgLimit << FDCAN_TTOCF_AWL_Pos) | \
+                  pTTParams->EvtTrigPolarity));
+    }
+    if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL1)
+    {
+      MODIFY_REG(hfdcan->ttcan->TTOCF,
+                 (FDCAN_TTOCF_EECS | FDCAN_TTOCF_EGTF | FDCAN_TTOCF_ECC),
+                 (pTTParams->ExternalClkSync  | \
+                  pTTParams->GlobalTimeFilter | \
+                  pTTParams->ClockCalibration));
+    }
+
+    /* Configure system matrix limits */
+    MODIFY_REG(hfdcan->ttcan->TTMLM, FDCAN_TTMLM_CSS, pTTParams->CycleStartSync);
+    if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      MODIFY_REG(hfdcan->ttcan->TTMLM,
+                 (FDCAN_TTMLM_TXEW | FDCAN_TTMLM_ENTT),
+                 (((pTTParams->TxEnableWindow - 1U) << FDCAN_TTMLM_TXEW_Pos) | (pTTParams->ExpTxTrigNbr << FDCAN_TTMLM_ENTT_Pos)));
+    }
+    if (pTTParams->TimeMaster == FDCAN_TT_POTENTIAL_MASTER)
+    {
+      MODIFY_REG(hfdcan->ttcan->TTMLM, FDCAN_TTMLM_CCM, pTTParams->BasicCyclesNbr);
+    }
+
+    /* Configure input triggers: Stop watch and Event */
+    MODIFY_REG(hfdcan->ttcan->TTTS,
+               (FDCAN_TTTS_SWTSEL | FDCAN_TTTS_EVTSEL),
+               (pTTParams->StopWatchTrigSel | pTTParams->EventTrigSel));
+
+    /* Configure trigger memory start address */
+    StartAddress = (hfdcan->msgRam.EndAddress - SRAMCAN_BASE) / 4U;
+    MODIFY_REG(hfdcan->ttcan->TTTMC, FDCAN_TTTMC_TMSA, (StartAddress << FDCAN_TTTMC_TMSA_Pos));
+
+    /* Trigger memory elements number */
+    MODIFY_REG(hfdcan->ttcan->TTTMC, FDCAN_TTTMC_TME, (pTTParams->TriggerMemoryNbr << FDCAN_TTTMC_TME_Pos));
+
+    /* Recalculate End Address */
+    hfdcan->msgRam.TTMemorySA = hfdcan->msgRam.EndAddress;
+    hfdcan->msgRam.EndAddress = hfdcan->msgRam.TTMemorySA + (pTTParams->TriggerMemoryNbr * 2U * 4U);
+
+    if (hfdcan->msgRam.EndAddress > FDCAN_MESSAGE_RAM_END_ADDRESS) /* Last address of the Message RAM */
+    {
+      /* Update error code.
+         Message RAM overflow */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Flush the allocated Message RAM area */
+      for (RAMcounter = hfdcan->msgRam.TTMemorySA; RAMcounter < hfdcan->msgRam.EndAddress; RAMcounter += 4U)
+      {
+        *(uint32_t *)(RAMcounter) = 0x00000000;
+      }
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the reference message.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  IdType Identifier Type.
+  *         This parameter can be a value of @arg FDCAN_id_type.
+  * @param  Identifier Reference Identifier.
+  *         This parameter must be a number between:
+  *           - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+  *           - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID
+  * @param  Payload Enable or disable the additional payload.
+  *         This parameter can be a value of @arg FDCAN_TT_Reference_Message_Payload.
+  *         This parameter is ignored in case of time slaves.
+  *         If this parameter is set to FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD, the
+  *         following elements are taken from Tx Buffer 0:
+  *          - MessageMarker
+  *          - TxEventFifoControl
+  *          - DataLength
+  *          - Data Bytes (payload):
+  *             - bytes 2-8, for Level 1
+  *             - bytes 5-8, for Level 0 and Level 2
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigReferenceMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t IdType, uint32_t Identifier, uint32_t Payload)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_ID_TYPE(IdType));
+  if (IdType == FDCAN_STANDARD_ID)
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(Identifier, 0x7FFU));
+  }
+  else /* IdType == FDCAN_EXTENDED_ID */
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(Identifier, 0x1FFFFFFFU));
+  }
+  assert_param(IS_FDCAN_TT_REFERENCE_MESSAGE_PAYLOAD(Payload));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Configure reference message identifier type, identifier and payload */
+    if (IdType == FDCAN_EXTENDED_ID)
+    {
+      MODIFY_REG(hfdcan->ttcan->TTRMC, (FDCAN_TTRMC_RID | FDCAN_TTRMC_XTD | FDCAN_TTRMC_RMPS), (Payload | IdType | Identifier));
+    }
+    else /* IdType == FDCAN_STANDARD_ID */
+    {
+      MODIFY_REG(hfdcan->ttcan->TTRMC, (FDCAN_TTRMC_RID | FDCAN_TTRMC_XTD | FDCAN_TTRMC_RMPS), (Payload | IdType | (Identifier << 18)));
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the FDCAN trigger according to the specified
+  *         parameters in the FDCAN_TriggerTypeDef structure.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  sTriggerConfig pointer to an FDCAN_TriggerTypeDef structure that
+  *         contains the trigger configuration information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigTrigger(FDCAN_HandleTypeDef *hfdcan, FDCAN_TriggerTypeDef *sTriggerConfig)
+{
+  uint32_t CycleCode;
+  uint32_t MessageNumber;
+  uint32_t TriggerElementW1;
+  uint32_t TriggerElementW2;
+  uint32_t *TriggerAddress;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->TriggerIndex, 63U));
+  assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->TimeMark, 0xFFFFU));
+  assert_param(IS_FDCAN_TT_REPEAT_FACTOR(sTriggerConfig->RepeatFactor));
+  if (sTriggerConfig->RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE)
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->StartCycle, (sTriggerConfig->RepeatFactor - 1U)));
+  }
+  assert_param(IS_FDCAN_TT_TM_EVENT_INTERNAL(sTriggerConfig->TmEventInt));
+  assert_param(IS_FDCAN_TT_TM_EVENT_EXTERNAL(sTriggerConfig->TmEventExt));
+  assert_param(IS_FDCAN_TT_TRIGGER_TYPE(sTriggerConfig->TriggerType));
+  assert_param(IS_FDCAN_ID_TYPE(sTriggerConfig->FilterType));
+  if ((sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_SINGLE) ||
+      (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_CONTINUOUS) ||
+      (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_ARBITRATION) ||
+      (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_MERGED))
+  {
+    assert_param(IS_FDCAN_TX_LOCATION(sTriggerConfig->TxBufferIndex));
+  }
+  if (sTriggerConfig->TriggerType == FDCAN_TT_RX_TRIGGER)
+  {
+    if (sTriggerConfig->FilterType == FDCAN_STANDARD_ID)
+    {
+      assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->FilterIndex, 63U));
+    }
+    else /* sTriggerConfig->FilterType == FDCAN_EXTENDED_ID */
+    {
+      assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->FilterIndex, 127U));
+    }
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Calculate cycle code */
+    if (sTriggerConfig->RepeatFactor == FDCAN_TT_REPEAT_EVERY_CYCLE)
+    {
+      CycleCode = FDCAN_TT_REPEAT_EVERY_CYCLE;
+    }
+    else /* sTriggerConfig->RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE */
+    {
+      CycleCode = sTriggerConfig->RepeatFactor + sTriggerConfig->StartCycle;
+    }
+
+    /* Build first word of trigger element */
+    TriggerElementW1 = ((sTriggerConfig->TimeMark << 16) | \
+                        (CycleCode << 8)                 | \
+                        sTriggerConfig->TmEventInt       | \
+                        sTriggerConfig->TmEventExt       | \
+                        sTriggerConfig->TriggerType);
+
+    /* Select message number depending on trigger type (transmission or reception) */
+    if (sTriggerConfig->TriggerType == FDCAN_TT_RX_TRIGGER)
+    {
+      MessageNumber = sTriggerConfig->FilterIndex;
+    }
+    else if ((sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_SINGLE) ||
+             (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_CONTINUOUS) ||
+             (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_ARBITRATION) ||
+             (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_MERGED))
+    {
+      MessageNumber = POSITION_VAL(sTriggerConfig->TxBufferIndex);
+    }
+    else
+    {
+      MessageNumber = 0U;
+    }
+
+    /* Build second word of trigger element */
+    TriggerElementW2 = ((sTriggerConfig->FilterType >> 7) | (MessageNumber << 16));
+
+    /* Calculate trigger address */
+    TriggerAddress = (uint32_t *)(hfdcan->msgRam.TTMemorySA + (sTriggerConfig->TriggerIndex * 4U * 2U));
+
+    /* Write trigger element to the message RAM */
+    *TriggerAddress = TriggerElementW1;
+    TriggerAddress++;
+    *TriggerAddress = TriggerElementW2;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Schedule global time adjustment for the next reference message.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TimePreset time preset value.
+  *         This parameter must be a number between:
+  *           - 0x0000 and 0x7FFF, Next_Master_Ref_Mark = Current_Master_Ref_Mark + TimePreset
+  *           or
+  *           - 0x8001 and 0xFFFF, Next_Master_Ref_Mark = Current_Master_Ref_Mark - (0x10000 - TimePreset)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_SetGlobalTime(FDCAN_HandleTypeDef *hfdcan, uint32_t TimePreset)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_TIME_PRESET(TimePreset));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Check that the external clock synchronization is enabled */
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_EECS) != FDCAN_TTOCF_EECS)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+
+    /* Check that no global time preset is pending */
+    if ((hfdcan->ttcan->TTOST & FDCAN_TTOST_WGTD) == FDCAN_TTOST_WGTD)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING;
+
+      return HAL_ERROR;
+    }
+
+    /* Configure time preset */
+    MODIFY_REG(hfdcan->ttcan->TTGTP, FDCAN_TTGTP_TP, (TimePreset << FDCAN_TTGTP_TP_Pos));
+
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Schedule time preset to take effect by the next reference message */
+    SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_SGT);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Schedule TUR numerator update for the next reference message.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  NewTURNumerator new value of the TUR numerator.
+  *         This parameter must be a number between 0x10000 and 0x1FFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_SetClockSynchronization(FDCAN_HandleTypeDef *hfdcan, uint32_t NewTURNumerator)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_TUR_NUMERATOR(NewTURNumerator));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Check that the external clock synchronization is enabled */
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_EECS) != FDCAN_TTOCF_EECS)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+
+    /* Check that no external clock synchronization is pending */
+    if ((hfdcan->ttcan->TTOST & FDCAN_TTOST_WECS) == FDCAN_TTOST_WECS)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING;
+
+      return HAL_ERROR;
+    }
+
+    /* Configure new TUR numerator */
+    MODIFY_REG(hfdcan->ttcan->TURCF, FDCAN_TURCF_NCL, (NewTURNumerator - 0x10000U));
+
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Schedule TUR numerator update by the next reference message */
+    SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_ECS);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure stop watch source and polarity.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  Source stop watch source.
+  *         This parameter can be a value of @arg FDCAN_TT_stop_watch_source.
+  * @param  Polarity stop watch polarity.
+  *         This parameter can be a value of @arg FDCAN_TT_stop_watch_polarity.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigStopWatch(FDCAN_HandleTypeDef *hfdcan, uint32_t Source, uint32_t Polarity)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_STOP_WATCH_SOURCE(Source));
+  assert_param(IS_FDCAN_TT_STOP_WATCH_POLARITY(Polarity));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Select stop watch source and polarity */
+    MODIFY_REG(hfdcan->ttcan->TTOCN, (FDCAN_TTOCN_SWS | FDCAN_TTOCN_SWP), (Source | Polarity));
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure register time mark pulse generation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TimeMarkSource time mark source.
+  *         This parameter can be a value of @arg FDCAN_TT_time_mark_source.
+  * @param  TimeMarkValue time mark value (reference).
+  *         This parameter must be a number between 0 and 0xFFFF.
+  * @param  RepeatFactor repeat factor of the cycle for which the time mark is valid.
+  *         This parameter can be a value of @arg FDCAN_TT_Repeat_Factor.
+  * @param  StartCycle index of the first cycle in which the time mark becomes valid.
+  *         This parameter is ignored if RepeatFactor is set to FDCAN_TT_REPEAT_EVERY_CYCLE.
+  *         This parameter must be a number between 0 and RepeatFactor.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigRegisterTimeMark(FDCAN_HandleTypeDef *hfdcan,
+                                                      uint32_t TimeMarkSource, uint32_t TimeMarkValue,
+                                                      uint32_t RepeatFactor, uint32_t StartCycle)
+{
+  uint32_t Counter = 0U;
+  uint32_t CycleCode;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_REGISTER_TIME_MARK_SOURCE(TimeMarkSource));
+  assert_param(IS_FDCAN_MAX_VALUE(TimeMarkValue, 0xFFFFU));
+  assert_param(IS_FDCAN_TT_REPEAT_FACTOR(RepeatFactor));
+  if (RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE)
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(StartCycle, (RepeatFactor - 1U)));
+  }
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Disable the time mark compare function */
+    CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMC);
+
+    if (TimeMarkSource != FDCAN_TT_REG_TIMEMARK_DIABLED)
+    {
+      /* Calculate cycle code */
+      if (RepeatFactor == FDCAN_TT_REPEAT_EVERY_CYCLE)
+      {
+        CycleCode = FDCAN_TT_REPEAT_EVERY_CYCLE;
+      }
+      else /* RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE */
+      {
+        CycleCode = RepeatFactor + StartCycle;
+      }
+
+      Counter = 0U;
+
+      /* Wait until the LCKM bit into TTTMK register is reset */
+      while ((hfdcan->ttcan->TTTMK & FDCAN_TTTMK_LCKM) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_VALUE)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Configure time mark value and cycle code */
+      hfdcan->ttcan->TTTMK = ((TimeMarkValue << FDCAN_TTTMK_TM_Pos) | (CycleCode << FDCAN_TTTMK_TICC_Pos));
+
+      Counter = 0U;
+
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_VALUE)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Update the register time mark compare source */
+      MODIFY_REG(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMC, TimeMarkSource);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable register time mark pulse generation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Enable Register Time Mark Interrupt output on fdcan1_rtp */
+    SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_RTIE);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable register time mark pulse generation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Disable Register Time Mark Interrupt output on fdcan1_rtp */
+    CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_RTIE);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable trigger time mark pulse generation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_VALUE)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Enable Trigger Time Mark Interrupt output on fdcan1_tmp */
+      SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TTIE);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable trigger time mark pulse generation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_VALUE)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Disable Trigger Time Mark Interrupt output on fdcan1_rtp */
+      CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TTIE);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable gap control by input pin fdcan1_evt.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_VALUE)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Enable gap control by pin fdcan1_evt */
+      SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_GCS);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable gap control by input pin fdcan1_evt.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_VALUE)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Disable gap control by pin fdcan1_evt */
+      CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_GCS);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable gap control (finish only) by register time mark interrupt.
+  *         The next register time mark interrupt (TTIR.RTMI = "1") will finish
+  *         the Gap and start the reference message.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_VALUE)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Enable gap control by register time mark interrupt */
+      SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMG);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable gap control by register time mark interrupt.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_VALUE)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Disable gap control by register time mark interrupt */
+      CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMG);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Transmit next reference message with Next_is_Gap = "1".
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_SetNextIsGap(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Check that the node is configured for external event-synchronized TT operation */
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_GEN) != FDCAN_TTOCF_GEN)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_VALUE)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Set Next is Gap */
+      SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_NIG);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Finish a Gap by requesting start of reference message.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_SetEndOfGap(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Check that the node is configured for external event-synchronized TT operation */
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_GEN) != FDCAN_TTOCF_GEN)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_VALUE)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Set Finish Gap */
+      SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_FGP);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure target phase used for external synchronization by event
+  *         trigger input pin fdcan1_evt.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TargetPhase defines target value of cycle time when a rising edge
+  *         of fdcan1_evt is expected.
+  *         This parameter must be a number between 0 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigExternalSyncPhase(FDCAN_HandleTypeDef *hfdcan, uint32_t TargetPhase)
+{
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_MAX_VALUE(TargetPhase, 0xFFFFU));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Check that no external schedule synchronization is pending */
+    if ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_ESCN) == FDCAN_TTOCN_ESCN)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING;
+
+      return HAL_ERROR;
+    }
+
+    /* Configure cycle time target phase */
+    MODIFY_REG(hfdcan->ttcan->TTGTP, FDCAN_TTGTP_CTP, (TargetPhase << FDCAN_TTGTP_CTP_Pos));
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Synchronize the phase of the FDCAN schedule to an external schedule
+  *         using event trigger input pin fdcan1_evt.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Enable external synchronization */
+    SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_ESCN);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable external schedule synchronization.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Disable external synchronization */
+    CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_ESCN);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get TT operation status.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TTOpStatus pointer to an FDCAN_TTOperationStatusTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_GetOperationStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_TTOperationStatusTypeDef *TTOpStatus)
+{
+  uint32_t TTStatusReg;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  /* Read the TT operation status register */
+  TTStatusReg = READ_REG(hfdcan->ttcan->TTOST);
+
+  /* Fill the TT operation status structure */
+  TTOpStatus->ErrorLevel = (TTStatusReg & FDCAN_TTOST_EL);
+  TTOpStatus->MasterState = (TTStatusReg & FDCAN_TTOST_MS);
+  TTOpStatus->SyncState = (TTStatusReg & FDCAN_TTOST_SYS);
+  TTOpStatus->GTimeQuality = ((TTStatusReg & FDCAN_TTOST_QGTP) >> FDCAN_TTOST_QGTP_Pos);
+  TTOpStatus->ClockQuality = ((TTStatusReg & FDCAN_TTOST_QCS) >> FDCAN_TTOST_QCS_Pos);
+  TTOpStatus->RefTrigOffset = ((TTStatusReg & FDCAN_TTOST_RTO) >> FDCAN_TTOST_RTO_Pos);
+  TTOpStatus->GTimeDiscPending = ((TTStatusReg & FDCAN_TTOST_WGTD) >> FDCAN_TTOST_WGTD_Pos);
+  TTOpStatus->GapFinished = ((TTStatusReg & FDCAN_TTOST_GFI) >> FDCAN_TTOST_GFI_Pos);
+  TTOpStatus->MasterPriority = ((TTStatusReg & FDCAN_TTOST_TMP) >> FDCAN_TTOST_TMP_Pos);
+  TTOpStatus->GapStarted = ((TTStatusReg & FDCAN_TTOST_GSI) >> FDCAN_TTOST_GSI_Pos);
+  TTOpStatus->WaitForEvt = ((TTStatusReg & FDCAN_TTOST_WFE) >> FDCAN_TTOST_WFE_Pos);
+  TTOpStatus->AppWdgEvt = ((TTStatusReg & FDCAN_TTOST_AWE) >> FDCAN_TTOST_AWE_Pos);
+  TTOpStatus->ECSPending = ((TTStatusReg & FDCAN_TTOST_WECS) >> FDCAN_TTOST_WECS_Pos);
+  TTOpStatus->PhaseLock = ((TTStatusReg & FDCAN_TTOST_SPL) >> FDCAN_TTOST_SPL_Pos);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Exported_Functions_Group5 Interrupts management
+ *  @brief    Interrupts management
+ *
+@verbatim
+  ==============================================================================
+                       ##### Interrupts management #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) HAL_FDCAN_ConfigInterruptLines      : Assign interrupts to either Interrupt line 0 or 1
+      (+) HAL_FDCAN_TT_ConfigInterruptLines   : Assign TT interrupts to either Interrupt line 0 or 1
+      (+) HAL_FDCAN_ActivateNotification      : Enable interrupts
+      (+) HAL_FDCAN_DeactivateNotification    : Disable interrupts
+      (+) HAL_FDCAN_TT_ActivateNotification   : Enable TT interrupts
+      (+) HAL_FDCAN_TT_DeactivateNotification : Disable TT interrupts
+      (+) HAL_FDCAN_IRQHandler                : Handles FDCAN interrupt request
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Assign interrupts to either Interrupt line 0 or 1.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  ITList indicates which interrupts will be assigned to the selected interrupt line.
+  *         This parameter can be any combination of @arg FDCAN_Interrupts.
+  * @param  InterruptLine Interrupt line.
+  *         This parameter can be a value of @arg FDCAN_Interrupt_Line.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine)
+{
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_IT(ITList));
+  assert_param(IS_FDCAN_IT_LINE(InterruptLine));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Assign list of interrupts to the selected line */
+    if (InterruptLine == FDCAN_INTERRUPT_LINE0)
+    {
+      CLEAR_BIT(hfdcan->Instance->ILS, ITList);
+    }
+    else /* InterruptLine == FDCAN_INTERRUPT_LINE1 */
+    {
+      SET_BIT(hfdcan->Instance->ILS, ITList);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Assign TT interrupts to either Interrupt line 0 or 1.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TTITList indicates which interrupts will be assigned to the selected interrupt line.
+  *         This parameter can be any combination of @arg FDCAN_TTInterrupts.
+  * @param  InterruptLine Interrupt line.
+  *         This parameter can be a value of @arg FDCAN_Interrupt_Line.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t TTITList, uint32_t InterruptLine)
+{
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_IT(TTITList));
+  assert_param(IS_FDCAN_IT_LINE(InterruptLine));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Assign list of interrupts to the selected line */
+    if (InterruptLine == FDCAN_INTERRUPT_LINE0)
+    {
+      CLEAR_BIT(hfdcan->ttcan->TTILS, TTITList);
+    }
+    else /* InterruptLine == FDCAN_INTERRUPT_LINE1 */
+    {
+      SET_BIT(hfdcan->ttcan->TTILS, TTITList);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable interrupts.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  ActiveITs indicates which interrupts will be enabled.
+  *         This parameter can be any combination of @arg FDCAN_Interrupts.
+  * @param  BufferIndexes Tx Buffer Indexes.
+  *         This parameter can be any combination of @arg FDCAN_Tx_location.
+  *         This parameter is ignored if ActiveITs does not include one of the following:
+  *           - FDCAN_IT_TX_COMPLETE
+  *           - FDCAN_IT_TX_ABORT_COMPLETE
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes)
+{
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_IT(ActiveITs));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Enable Interrupt lines */
+    if ((ActiveITs & hfdcan->Instance->ILS) == 0U)
+    {
+      /* Enable Interrupt line 0 */
+      SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
+    }
+    else if ((ActiveITs & hfdcan->Instance->ILS) == ActiveITs)
+    {
+      /* Enable Interrupt line 1 */
+      SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
+    }
+    else
+    {
+      /* Enable Interrupt lines 0 and 1 */
+      hfdcan->Instance->ILE = (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1);
+    }
+
+    if ((ActiveITs & FDCAN_IT_TX_COMPLETE) != 0U)
+    {
+      /* Enable Tx Buffer Transmission Interrupt to set TC flag in IR register,
+         but interrupt will only occure if TC is enabled in IE register */
+      SET_BIT(hfdcan->Instance->TXBTIE, BufferIndexes);
+    }
+
+    if ((ActiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != 0U)
+    {
+      /* Enable Tx Buffer Cancellation Finished Interrupt to set TCF flag in IR register,
+         but interrupt will only occure if TCF is enabled in IE register */
+      SET_BIT(hfdcan->Instance->TXBCIE, BufferIndexes);
+    }
+
+    /* Enable the selected interrupts */
+    __HAL_FDCAN_ENABLE_IT(hfdcan, ActiveITs);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable interrupts.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  InactiveITs indicates which interrupts will be disabled.
+  *         This parameter can be any combination of @arg FDCAN_Interrupts.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs)
+{
+  uint32_t ITLineSelection;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_IT(InactiveITs));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Disable the selected interrupts */
+    __HAL_FDCAN_DISABLE_IT(hfdcan, InactiveITs);
+
+    if ((InactiveITs & FDCAN_IT_TX_COMPLETE) != 0U)
+    {
+      /* Disable Tx Buffer Transmission Interrupts */
+      CLEAR_REG(hfdcan->Instance->TXBTIE);
+    }
+
+    if ((InactiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != 0U)
+    {
+      /* Disable Tx Buffer Cancellation Finished Interrupt */
+      CLEAR_REG(hfdcan->Instance->TXBCIE);
+    }
+
+    ITLineSelection = hfdcan->Instance->ILS;
+
+    if ((hfdcan->Instance->IE | ITLineSelection) == ITLineSelection)
+    {
+      /* Disable Interrupt line 0 */
+      CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
+    }
+
+    if ((hfdcan->Instance->IE & ITLineSelection) == 0U)
+    {
+      /* Disable Interrupt line 1 */
+      CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable TT interrupts.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  ActiveTTITs indicates which TT interrupts will be enabled.
+  *         This parameter can be any combination of @arg FDCAN_TTInterrupts.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveTTITs)
+{
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_IT(ActiveTTITs));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Enable Interrupt lines */
+    if ((ActiveTTITs & hfdcan->ttcan->TTILS) == 0U)
+    {
+      /* Enable Interrupt line 0 */
+      SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
+    }
+    else if ((ActiveTTITs & hfdcan->ttcan->TTILS) == ActiveTTITs)
+    {
+      /* Enable Interrupt line 1 */
+      SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
+    }
+    else
+    {
+      /* Enable Interrupt lines 0 and 1 */
+      hfdcan->Instance->ILE = (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1);
+    }
+
+    /* Enable the selected TT interrupts */
+    __HAL_FDCAN_TT_ENABLE_IT(hfdcan, ActiveTTITs);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable TT interrupts.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  InactiveTTITs indicates which TT interrupts will be disabled.
+  *         This parameter can be any combination of @arg FDCAN_TTInterrupts.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveTTITs)
+{
+  uint32_t ITLineSelection;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_IT(InactiveTTITs));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Disable the selected TT interrupts */
+    __HAL_FDCAN_TT_DISABLE_IT(hfdcan, InactiveTTITs);
+
+    ITLineSelection = hfdcan->ttcan->TTILS;
+
+    if ((hfdcan->ttcan->TTIE | ITLineSelection) == ITLineSelection)
+    {
+      /* Disable Interrupt line 0 */
+      CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
+    }
+
+    if ((hfdcan->ttcan->TTIE & ITLineSelection) == 0U)
+    {
+      /* Disable Interrupt line 1 */
+      CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Handles FDCAN interrupt request.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t ClkCalibrationITs;
+  uint32_t TxEventFifoITs;
+  uint32_t RxFifo0ITs;
+  uint32_t RxFifo1ITs;
+  uint32_t Errors;
+  uint32_t ErrorStatusITs;
+  uint32_t TransmittedBuffers;
+  uint32_t AbortedBuffers;
+  uint32_t TTSchedSyncITs;
+  uint32_t TTTimeMarkITs;
+  uint32_t TTGlobTimeITs;
+  uint32_t TTDistErrors;
+  uint32_t TTFatalErrors;
+  uint32_t SWTime;
+  uint32_t SWCycleCount;
+
+  ClkCalibrationITs = (FDCAN_CCU->IR << 30);
+  ClkCalibrationITs &= (FDCAN_CCU->IE << 30);
+  TxEventFifoITs = hfdcan->Instance->IR & FDCAN_TX_EVENT_FIFO_MASK;
+  TxEventFifoITs &= hfdcan->Instance->IE;
+  RxFifo0ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO0_MASK;
+  RxFifo0ITs &= hfdcan->Instance->IE;
+  RxFifo1ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO1_MASK;
+  RxFifo1ITs &= hfdcan->Instance->IE;
+  Errors = hfdcan->Instance->IR & FDCAN_ERROR_MASK;
+  Errors &= hfdcan->Instance->IE;
+  ErrorStatusITs = hfdcan->Instance->IR & FDCAN_ERROR_STATUS_MASK;
+  ErrorStatusITs &= hfdcan->Instance->IE;
+
+  /* High Priority Message interrupt management *******************************/
+  if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RX_HIGH_PRIORITY_MSG) != 0U)
+  {
+    if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG) != 0U)
+    {
+      /* Clear the High Priority Message flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->HighPriorityMessageCallback(hfdcan);
+#else
+      /* High Priority Message Callback */
+      HAL_FDCAN_HighPriorityMessageCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Transmission Abort interrupt management **********************************/
+  if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_ABORT_COMPLETE) != 0U)
+  {
+    if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE) != 0U)
+    {
+      /* List of aborted monitored buffers */
+      AbortedBuffers = hfdcan->Instance->TXBCF;
+      AbortedBuffers &= hfdcan->Instance->TXBCIE;
+
+      /* Clear the Transmission Cancellation flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->TxBufferAbortCallback(hfdcan, AbortedBuffers);
+#else
+      /* Transmission Cancellation Callback */
+      HAL_FDCAN_TxBufferAbortCallback(hfdcan, AbortedBuffers);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Clock calibration unit interrupts management *****************************/
+  if (ClkCalibrationITs != 0U)
+  {
+    /* Clear the Clock Calibration flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, ClkCalibrationITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->ClockCalibrationCallback(hfdcan, ClkCalibrationITs);
+#else
+    /* Clock Calibration Callback */
+    HAL_FDCAN_ClockCalibrationCallback(hfdcan, ClkCalibrationITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+
+  /* Tx event FIFO interrupts management **************************************/
+  if (TxEventFifoITs != 0U)
+  {
+    /* Clear the Tx Event FIFO flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, TxEventFifoITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->TxEventFifoCallback(hfdcan, TxEventFifoITs);
+#else
+    /* Tx Event FIFO Callback */
+    HAL_FDCAN_TxEventFifoCallback(hfdcan, TxEventFifoITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+
+  /* Rx FIFO 0 interrupts management ******************************************/
+  if (RxFifo0ITs != 0U)
+  {
+    /* Clear the Rx FIFO 0 flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo0ITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->RxFifo0Callback(hfdcan, RxFifo0ITs);
+#else
+    /* Rx FIFO 0 Callback */
+    HAL_FDCAN_RxFifo0Callback(hfdcan, RxFifo0ITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+
+  /* Rx FIFO 1 interrupts management ******************************************/
+  if (RxFifo1ITs != 0U)
+  {
+    /* Clear the Rx FIFO 1 flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo1ITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->RxFifo1Callback(hfdcan, RxFifo1ITs);
+#else
+    /* Rx FIFO 1 Callback */
+    HAL_FDCAN_RxFifo1Callback(hfdcan, RxFifo1ITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+
+  /* Tx FIFO empty interrupt management ***************************************/
+  if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_FIFO_EMPTY) != 0U)
+  {
+    if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY) != 0U)
+    {
+      /* Clear the Tx FIFO empty flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->TxFifoEmptyCallback(hfdcan);
+#else
+      /* Tx FIFO empty Callback */
+      HAL_FDCAN_TxFifoEmptyCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Transmission Complete interrupt management *******************************/
+  if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_COMPLETE) != 0U)
+  {
+    if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_COMPLETE) != 0U)
+    {
+      /* List of transmitted monitored buffers */
+      TransmittedBuffers = hfdcan->Instance->TXBTO;
+      TransmittedBuffers &= hfdcan->Instance->TXBTIE;
+
+      /* Clear the Transmission Complete flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_COMPLETE);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->TxBufferCompleteCallback(hfdcan, TransmittedBuffers);
+#else
+      /* Transmission Complete Callback */
+      HAL_FDCAN_TxBufferCompleteCallback(hfdcan, TransmittedBuffers);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Rx Buffer New Message interrupt management *******************************/
+  if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RX_BUFFER_NEW_MESSAGE) != 0U)
+  {
+    if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE) != 0U)
+    {
+      /* Clear the Rx Buffer New Message flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->RxBufferNewMessageCallback(hfdcan);
+#else
+      /* Rx Buffer New Message Callback */
+      HAL_FDCAN_RxBufferNewMessageCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Timestamp Wraparound interrupt management ********************************/
+  if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TIMESTAMP_WRAPAROUND) != 0U)
+  {
+    if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND) != 0U)
+    {
+      /* Clear the Timestamp Wraparound flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->TimestampWraparoundCallback(hfdcan);
+#else
+      /* Timestamp Wraparound Callback */
+      HAL_FDCAN_TimestampWraparoundCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Timeout Occurred interrupt management ************************************/
+  if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TIMEOUT_OCCURRED) != 0U)
+  {
+    if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED) != 0U)
+    {
+      /* Clear the Timeout Occurred flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->TimeoutOccurredCallback(hfdcan);
+#else
+      /* Timeout Occurred Callback */
+      HAL_FDCAN_TimeoutOccurredCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Message RAM access failure interrupt management **************************/
+  if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RAM_ACCESS_FAILURE) != 0U)
+  {
+    if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE) != 0U)
+    {
+      /* Clear the Message RAM access failure flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE);
+
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_RAM_ACCESS;
+    }
+  }
+
+  /* Error Status interrupts management ***************************************/
+  if (ErrorStatusITs != 0U)
+  {
+    /* Clear the Error flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, ErrorStatusITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->ErrorStatusCallback(hfdcan, ErrorStatusITs);
+#else
+    /* Error Status Callback */
+    HAL_FDCAN_ErrorStatusCallback(hfdcan, ErrorStatusITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+
+  /* Error interrupts management **********************************************/
+  if (Errors != 0U)
+  {
+    /* Clear the Error flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, Errors);
+
+    /* Update error code */
+    hfdcan->ErrorCode |= Errors;
+  }
+
+  if (hfdcan->Instance == FDCAN1)
+  {
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != 0U)
+    {
+      TTSchedSyncITs = hfdcan->ttcan->TTIR & FDCAN_TT_SCHEDULE_SYNC_MASK;
+      TTSchedSyncITs &= hfdcan->ttcan->TTIE;
+      TTTimeMarkITs = hfdcan->ttcan->TTIR & FDCAN_TT_TIME_MARK_MASK;
+      TTTimeMarkITs &= hfdcan->ttcan->TTIE;
+      TTGlobTimeITs = hfdcan->ttcan->TTIR & FDCAN_TT_GLOBAL_TIME_MASK;
+      TTGlobTimeITs &= hfdcan->ttcan->TTIE;
+      TTDistErrors = hfdcan->ttcan->TTIR & FDCAN_TT_DISTURBING_ERROR_MASK;
+      TTDistErrors &= hfdcan->ttcan->TTIE;
+      TTFatalErrors = hfdcan->ttcan->TTIR & FDCAN_TT_FATAL_ERROR_MASK;
+      TTFatalErrors &= hfdcan->ttcan->TTIE;
+
+      /* TT Schedule Synchronization interrupts management **********************/
+      if (TTSchedSyncITs != 0U)
+      {
+        /* Clear the TT Schedule Synchronization flags */
+        __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTSchedSyncITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+        /* Call registered callback*/
+        hfdcan->TT_ScheduleSyncCallback(hfdcan, TTSchedSyncITs);
+#else
+        /* TT Schedule Synchronization Callback */
+        HAL_FDCAN_TT_ScheduleSyncCallback(hfdcan, TTSchedSyncITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+      }
+
+      /* TT Time Mark interrupts management *************************************/
+      if (TTTimeMarkITs != 0U)
+      {
+        /* Clear the TT Time Mark flags */
+        __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTTimeMarkITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+        /* Call registered callback*/
+        hfdcan->TT_TimeMarkCallback(hfdcan, TTTimeMarkITs);
+#else
+        /* TT Time Mark Callback */
+        HAL_FDCAN_TT_TimeMarkCallback(hfdcan, TTTimeMarkITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+      }
+
+      /* TT Stop Watch interrupt management *************************************/
+      if (__HAL_FDCAN_TT_GET_IT_SOURCE(hfdcan, FDCAN_TT_IT_STOP_WATCH) != 0U)
+      {
+        if (__HAL_FDCAN_TT_GET_FLAG(hfdcan, FDCAN_TT_FLAG_STOP_WATCH) != 0U)
+        {
+          /* Retrieve Stop watch Time and Cycle count */
+          SWTime = ((hfdcan->ttcan->TTCPT & FDCAN_TTCPT_SWV) >> FDCAN_TTCPT_SWV_Pos);
+          SWCycleCount = ((hfdcan->ttcan->TTCPT & FDCAN_TTCPT_CCV) >> FDCAN_TTCPT_CCV_Pos);
+
+          /* Clear the TT Stop Watch flag */
+          __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, FDCAN_TT_FLAG_STOP_WATCH);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+          /* Call registered callback*/
+          hfdcan->TT_StopWatchCallback(hfdcan, SWTime, SWCycleCount);
+#else
+          /* TT Stop Watch Callback */
+          HAL_FDCAN_TT_StopWatchCallback(hfdcan, SWTime, SWCycleCount);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+        }
+      }
+
+      /* TT Global Time interrupts management ***********************************/
+      if (TTGlobTimeITs != 0U)
+      {
+        /* Clear the TT Global Time flags */
+        __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTGlobTimeITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+        /* Call registered callback*/
+        hfdcan->TT_GlobalTimeCallback(hfdcan, TTGlobTimeITs);
+#else
+        /* TT Global Time Callback */
+        HAL_FDCAN_TT_GlobalTimeCallback(hfdcan, TTGlobTimeITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+      }
+
+      /* TT Disturbing Error interrupts management ******************************/
+      if (TTDistErrors != 0U)
+      {
+        /* Clear the TT Disturbing Error flags */
+        __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTDistErrors);
+
+        /* Update error code */
+        hfdcan->ErrorCode |= TTDistErrors;
+      }
+
+      /* TT Fatal Error interrupts management ***********************************/
+      if (TTFatalErrors != 0U)
+      {
+        /* Clear the TT Fatal Error flags */
+        __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTFatalErrors);
+
+        /* Update error code */
+        hfdcan->ErrorCode |= TTFatalErrors;
+      }
+    }
+  }
+
+  if (hfdcan->ErrorCode != HAL_FDCAN_ERROR_NONE)
+  {
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->ErrorCallback(hfdcan);
+#else
+    /* Error Callback */
+    HAL_FDCAN_ErrorCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Exported_Functions_Group6 Callback functions
+ *  @brief   FDCAN Callback functions
+ *
+@verbatim
+  ==============================================================================
+                          ##### Callback functions #####
+  ==============================================================================
+    [..]
+    This subsection provides the following callback functions:
+      (+) HAL_FDCAN_ClockCalibrationCallback
+      (+) HAL_FDCAN_TxEventFifoCallback
+      (+) HAL_FDCAN_RxFifo0Callback
+      (+) HAL_FDCAN_RxFifo1Callback
+      (+) HAL_FDCAN_TxFifoEmptyCallback
+      (+) HAL_FDCAN_TxBufferCompleteCallback
+      (+) HAL_FDCAN_TxBufferAbortCallback
+      (+) HAL_FDCAN_RxBufferNewMessageCallback
+      (+) HAL_FDCAN_HighPriorityMessageCallback
+      (+) HAL_FDCAN_TimestampWraparoundCallback
+      (+) HAL_FDCAN_TimeoutOccurredCallback
+      (+) HAL_FDCAN_ErrorCallback
+      (+) HAL_FDCAN_ErrorStatusCallback
+      (+) HAL_FDCAN_TT_ScheduleSyncCallback
+      (+) HAL_FDCAN_TT_TimeMarkCallback
+      (+) HAL_FDCAN_TT_StopWatchCallback
+      (+) HAL_FDCAN_TT_GlobalTimeCallback
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Clock Calibration callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  ClkCalibrationITs indicates which Clock Calibration interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_Clock_Calibration_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_ClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(ClkCalibrationITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_ClockCalibrationCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Tx Event callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TxEventFifoITs indicates which Tx Event FIFO interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_Tx_Event_Fifo_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(TxEventFifoITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TxEventFifoCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Rx FIFO 0 callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  RxFifo0ITs indicates which Rx FIFO 0 interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_Rx_Fifo0_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(RxFifo0ITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_RxFifo0Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Rx FIFO 1 callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  RxFifo1ITs indicates which Rx FIFO 1 interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_Rx_Fifo1_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(RxFifo1ITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_RxFifo1Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Tx FIFO Empty callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TxFifoEmptyCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Transmission Complete callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  BufferIndexes Indexes of the transmitted buffers.
+  *         This parameter can be any combination of @arg FDCAN_Tx_location.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(BufferIndexes);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TxBufferCompleteCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Transmission Cancellation callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  BufferIndexes Indexes of the aborted buffers.
+  *         This parameter can be any combination of @arg FDCAN_Tx_location.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(BufferIndexes);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TxBufferAbortCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Rx Buffer New Message callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_RxBufferNewMessageCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_RxBufferNewMessageCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Timestamp Wraparound callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TimestampWraparoundCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Timeout Occurred callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TimeoutOccurredCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  High Priority Message callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_HighPriorityMessageCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Error callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Error status callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  ErrorStatusITs indicates which Error Status interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_Error_Status_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(ErrorStatusITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_ErrorStatusCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  TT Schedule Synchronization callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TTSchedSyncITs indicates which TT Schedule Synchronization interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_TTScheduleSynchronization_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TT_ScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(TTSchedSyncITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TT_ScheduleSyncCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  TT Time Mark callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TTTimeMarkITs indicates which TT Schedule Synchronization interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_TTTimeMark_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TT_TimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(TTTimeMarkITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TT_TimeMarkCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  TT Stop Watch callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  SWTime Time Value captured at the Stop Watch Trigger pin (fdcan1_swt) falling/rising
+  *         edge (as configured via HAL_FDCAN_TTConfigStopWatch).
+  *         This parameter is a number between 0 and 0xFFFF.
+  * @param  SWCycleCount Cycle count value captured together with SWTime.
+  *         This parameter is a number between 0 and 0x3F.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TT_StopWatchCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(SWTime);
+  UNUSED(SWCycleCount);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TT_StopWatchCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  TT Global Time callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TTGlobTimeITs indicates which TT Global Time interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_TTGlobalTime_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TT_GlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(TTGlobTimeITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TT_GlobalTimeCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Exported_Functions_Group7 Peripheral State functions
+ *  @brief   FDCAN Peripheral State functions
+ *
+@verbatim
+  ==============================================================================
+                      ##### Peripheral State functions #####
+  ==============================================================================
+    [..]
+    This subsection provides functions allowing to :
+      (+) HAL_FDCAN_GetState()  : Return the FDCAN state.
+      (+) HAL_FDCAN_GetError()  : Return the FDCAN error code if any.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Return the FDCAN state
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL state
+  */
+HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Return FDCAN state */
+  return hfdcan->State;
+}
+
+/**
+  * @brief  Return the FDCAN error code
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval FDCAN Error Code
+  */
+uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Return FDCAN error code */
+  return hfdcan->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup FDCAN_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Calculate each RAM block start address and size
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+ */
+static HAL_StatusTypeDef FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t RAMcounter;
+  uint32_t StartAddress;
+
+  StartAddress = hfdcan->Init.MessageRAMOffset;
+
+  /* Standard filter list start address */
+  MODIFY_REG(hfdcan->Instance->SIDFC, FDCAN_SIDFC_FLSSA, (StartAddress << FDCAN_SIDFC_FLSSA_Pos));
+
+  /* Standard filter elements number */
+  MODIFY_REG(hfdcan->Instance->SIDFC, FDCAN_SIDFC_LSS, (hfdcan->Init.StdFiltersNbr << FDCAN_SIDFC_LSS_Pos));
+
+  /* Extended filter list start address */
+  StartAddress += hfdcan->Init.StdFiltersNbr;
+  MODIFY_REG(hfdcan->Instance->XIDFC, FDCAN_XIDFC_FLESA, (StartAddress << FDCAN_XIDFC_FLESA_Pos));
+
+  /* Extended filter elements number */
+  MODIFY_REG(hfdcan->Instance->XIDFC, FDCAN_XIDFC_LSE, (hfdcan->Init.ExtFiltersNbr << FDCAN_XIDFC_LSE_Pos));
+
+  /* Rx FIFO 0 start address */
+  StartAddress += (hfdcan->Init.ExtFiltersNbr * 2U);
+  MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0SA, (StartAddress << FDCAN_RXF0C_F0SA_Pos));
+
+  /* Rx FIFO 0 elements number */
+  MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0S, (hfdcan->Init.RxFifo0ElmtsNbr << FDCAN_RXF0C_F0S_Pos));
+
+  /* Rx FIFO 1 start address */
+  StartAddress += (hfdcan->Init.RxFifo0ElmtsNbr * hfdcan->Init.RxFifo0ElmtSize);
+  MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1SA, (StartAddress << FDCAN_RXF1C_F1SA_Pos));
+
+  /* Rx FIFO 1 elements number */
+  MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1S, (hfdcan->Init.RxFifo1ElmtsNbr << FDCAN_RXF1C_F1S_Pos));
+
+  /* Rx buffer list start address */
+  StartAddress += (hfdcan->Init.RxFifo1ElmtsNbr * hfdcan->Init.RxFifo1ElmtSize);
+  MODIFY_REG(hfdcan->Instance->RXBC, FDCAN_RXBC_RBSA, (StartAddress << FDCAN_RXBC_RBSA_Pos));
+
+  /* Tx event FIFO start address */
+  StartAddress += (hfdcan->Init.RxBuffersNbr * hfdcan->Init.RxBufferSize);
+  MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFSA, (StartAddress << FDCAN_TXEFC_EFSA_Pos));
+
+  /* Tx event FIFO elements number */
+  MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFS, (hfdcan->Init.TxEventsNbr << FDCAN_TXEFC_EFS_Pos));
+
+  /* Tx buffer list start address */
+  StartAddress += (hfdcan->Init.TxEventsNbr * 2U);
+  MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_TBSA, (StartAddress << FDCAN_TXBC_TBSA_Pos));
+
+  /* Dedicated Tx buffers number */
+  MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_NDTB, (hfdcan->Init.TxBuffersNbr << FDCAN_TXBC_NDTB_Pos));
+
+  /* Tx FIFO/queue elements number */
+  MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_TFQS, (hfdcan->Init.TxFifoQueueElmtsNbr << FDCAN_TXBC_TFQS_Pos));
+
+  hfdcan->msgRam.StandardFilterSA = SRAMCAN_BASE + (hfdcan->Init.MessageRAMOffset * 4U);
+  hfdcan->msgRam.ExtendedFilterSA = hfdcan->msgRam.StandardFilterSA + (hfdcan->Init.StdFiltersNbr * 4U);
+  hfdcan->msgRam.RxFIFO0SA = hfdcan->msgRam.ExtendedFilterSA + (hfdcan->Init.ExtFiltersNbr * 2U * 4U);
+  hfdcan->msgRam.RxFIFO1SA = hfdcan->msgRam.RxFIFO0SA + (hfdcan->Init.RxFifo0ElmtsNbr * hfdcan->Init.RxFifo0ElmtSize * 4U);
+  hfdcan->msgRam.RxBufferSA = hfdcan->msgRam.RxFIFO1SA + (hfdcan->Init.RxFifo1ElmtsNbr * hfdcan->Init.RxFifo1ElmtSize * 4U);
+  hfdcan->msgRam.TxEventFIFOSA = hfdcan->msgRam.RxBufferSA + (hfdcan->Init.RxBuffersNbr * hfdcan->Init.RxBufferSize * 4U);
+  hfdcan->msgRam.TxBufferSA = hfdcan->msgRam.TxEventFIFOSA + (hfdcan->Init.TxEventsNbr * 2U * 4U);
+  hfdcan->msgRam.TxFIFOQSA = hfdcan->msgRam.TxBufferSA + (hfdcan->Init.TxBuffersNbr * hfdcan->Init.TxElmtSize * 4U);
+
+  hfdcan->msgRam.EndAddress = hfdcan->msgRam.TxFIFOQSA + (hfdcan->Init.TxFifoQueueElmtsNbr * hfdcan->Init.TxElmtSize * 4U);
+
+  if (hfdcan->msgRam.EndAddress > FDCAN_MESSAGE_RAM_END_ADDRESS) /* Last address of the Message RAM */
+  {
+    /* Update error code.
+       Message RAM overflow */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+    /* Change FDCAN state */
+    hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Flush the allocated Message RAM area */
+    for (RAMcounter = hfdcan->msgRam.StandardFilterSA; RAMcounter < hfdcan->msgRam.EndAddress; RAMcounter += 4U)
+    {
+      *(uint32_t *)(RAMcounter) = 0x00000000;
+    }
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Copy Tx message to the message RAM.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure.
+  * @param  pTxData pointer to a buffer containing the payload of the Tx frame.
+  * @param  BufferIndex index of the buffer to be configured.
+  * @retval HAL status
+ */
+static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex)
+{
+  uint32_t TxElementW1;
+  uint32_t TxElementW2;
+  uint32_t *TxAddress;
+  uint32_t ByteCounter;
+
+  /* Build first word of Tx header element */
+  if (pTxHeader->IdType == FDCAN_STANDARD_ID)
+  {
+    TxElementW1 = (pTxHeader->ErrorStateIndicator |
+                   FDCAN_STANDARD_ID |
+                   pTxHeader->TxFrameType |
+                   (pTxHeader->Identifier << 18));
+  }
+  else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
+  {
+    TxElementW1 = (pTxHeader->ErrorStateIndicator |
+                   FDCAN_EXTENDED_ID |
+                   pTxHeader->TxFrameType |
+                   pTxHeader->Identifier);
+  }
+
+  /* Build second word of Tx header element */
+  TxElementW2 = ((pTxHeader->MessageMarker << 24) |
+                 pTxHeader->TxEventFifoControl |
+                 pTxHeader->FDFormat |
+                 pTxHeader->BitRateSwitch |
+                 pTxHeader->DataLength);
+
+  /* Calculate Tx element address */
+  TxAddress = (uint32_t *)(hfdcan->msgRam.TxBufferSA + (BufferIndex * hfdcan->Init.TxElmtSize * 4U));
+
+  /* Write Tx element header to the message RAM */
+  *TxAddress = TxElementW1;
+  TxAddress++;
+  *TxAddress = TxElementW2;
+  TxAddress++;
+
+  /* Write Tx payload to the message RAM */
+  for (ByteCounter = 0; ByteCounter < DLCtoBytes[pTxHeader->DataLength >> 16]; ByteCounter += 4U)
+  {
+    *TxAddress = (((uint32_t)pTxData[ByteCounter + 3U] << 24) |
+                  ((uint32_t)pTxData[ByteCounter + 2U] << 16) |
+                  ((uint32_t)pTxData[ByteCounter + 1U] << 8) |
+                  (uint32_t)pTxData[ByteCounter]);
+    TxAddress++;
+  }
+}
+
+/**
+  * @}
+  */
+#endif /* HAL_FDCAN_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c
new file mode 100644
index 00000000..3a6b651f
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c
@@ -0,0 +1,1099 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_flash.c
+  * @author  MCD Application Team
+  * @brief   FLASH HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the internal FLASH memory:
+  *           + Program operations functions
+  *           + Memory Control functions
+  *           + Peripheral Errors functions
+  *
+ @verbatim
+  ==============================================================================
+                        ##### FLASH peripheral features #####
+  ==============================================================================
+
+  [..] The Flash memory interface manages CPU AXI I-Code and D-Code accesses
+       to the Flash memory. It implements the erase and program Flash memory operations
+       and the read and write protection mechanisms.
+
+  [..] The FLASH main features are:
+      (+) Flash memory read operations
+      (+) Flash memory program/erase operations
+      (+) Read / write protections
+      (+) Option bytes programming
+      (+) Error code correction (ECC) : Data in flash are 266-bits word
+          (10 bits added per flash word)
+
+                        ##### How to use this driver #####
+ ==============================================================================
+    [..]
+      This driver provides functions and macros to configure and program the FLASH
+      memory of all STM32H7xx devices.
+
+      (#) FLASH Memory IO Programming functions:
+           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
+                HAL_FLASH_Lock() functions
+           (++) Program functions: 256-bit word only
+           (++) There Two modes of programming :
+            (+++) Polling mode using HAL_FLASH_Program() function
+            (+++) Interrupt mode using HAL_FLASH_Program_IT() function
+
+      (#) Interrupts and flags management functions :
+           (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
+           (++) Callback functions are called when the flash operations are finished :
+                HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise
+                HAL_FLASH_OperationErrorCallback()
+           (++) Get error flag status by calling HAL_FLASH_GetError()
+
+      (#) Option bytes management functions :
+           (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and
+                HAL_FLASH_OB_Lock() functions
+           (++) Launch the reload of the option bytes using HAL_FLASH_OB_Launch() function.
+                In this case, a reset is generated
+    [..]
+      In addition to these functions, this driver includes a set of macros allowing
+      to handle the following operations:
+       (+) Set the latency
+       (+) Enable/Disable the FLASH interrupts
+       (+) Monitor the FLASH flags status
+     [..]
+    (@) For any Flash memory program operation (erase or program), the CPU clock frequency
+        (HCLK) must be at least 1MHz.
+    (@) The contents of the Flash memory are not guaranteed if a device reset occurs during
+        a Flash memory operation.
+    (@) The application can simultaneously request a read and a write operation through each AXI
+        interface.
+        As the Flash memory is divided into two independent banks, the embedded Flash
+        memory interface can drive different operations at the same time on each bank. For
+        example a read, write or erase operation can be executed on bank 1 while another read,
+        write or erase operation is executed on bank 2.
+
+ @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup FLASH FLASH
+  * @brief FLASH HAL module driver
+  * @{
+  */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup FLASH_Private_Constants
+  * @{
+  */
+#define FLASH_TIMEOUT_VALUE              50000U /* 50 s */
+
+/**
+  * @}
+  */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+FLASH_ProcessTypeDef pFlash;
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup FLASH_Exported_Functions FLASH Exported functions
+  * @{
+  */
+
+/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
+ *  @brief   Programming operation functions
+ *
+@verbatim
+ ===============================================================================
+                  ##### Programming operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the FLASH
+    program operations.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Program flash word at a specified address
+  * @param  TypeProgram Indicate the way to program at a specified address.
+  *         This parameter can be a value of @ref FLASH_Type_Program
+  * @param  FlashAddress specifies the address to be programmed.
+  * @param  DataAddress specifies the address of data to be programmed
+  *
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress)
+{
+  HAL_StatusTypeDef status;
+  __IO uint32_t *dest_addr = (__IO uint32_t *)FlashAddress;
+  __IO uint32_t *src_addr = (__IO uint32_t*)DataAddress;
+  uint32_t bank;
+  uint8_t row_index = FLASH_NB_32BITWORD_IN_FLASHWORD;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+  assert_param(IS_FLASH_PROGRAM_ADDRESS(FlashAddress));
+
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+#if defined (FLASH_OPTCR_PG_OTP)
+  if((IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress)) || (IS_FLASH_PROGRAM_ADDRESS_OTP(FlashAddress)))
+#else
+  if(IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress))
+#endif /* FLASH_OPTCR_PG_OTP */
+  {
+    bank = FLASH_BANK_1;
+  }
+  else
+  {
+    bank = FLASH_BANK_2;
+  }
+
+  /* Reset error code */
+  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, bank);
+
+  if(status == HAL_OK)
+  {
+    if(bank == FLASH_BANK_1)
+    {
+#if defined (FLASH_OPTCR_PG_OTP)
+      if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD)
+      {
+        /* Set OTP_PG bit */
+        SET_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP);
+      }
+      else
+#endif /* FLASH_OPTCR_PG_OTP */
+      {
+        /* Set PG bit */
+        SET_BIT(FLASH->CR1, FLASH_CR_PG);
+      }
+    }
+    else
+    {
+      /* Set PG bit */
+      SET_BIT(FLASH->CR2, FLASH_CR_PG);
+    }
+
+    __ISB();
+    __DSB();
+
+#if defined (FLASH_OPTCR_PG_OTP)
+    if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD)
+    {
+      /* Program an OTP word (16 bits) */
+      *(__IO uint16_t *)FlashAddress = *(__IO uint16_t*)DataAddress;
+    }
+    else
+#endif /* FLASH_OPTCR_PG_OTP */
+    {
+      /* Program the flash word */
+      do
+      {
+        *dest_addr = *src_addr;
+        dest_addr++;
+        src_addr++;
+        row_index--;
+     } while (row_index != 0U);
+    }
+
+    __ISB();
+    __DSB();
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, bank);
+
+#if defined (FLASH_OPTCR_PG_OTP)
+    if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD)
+    {
+      /* If the program operation is completed, disable the OTP_PG */
+      CLEAR_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP);
+    }
+    else
+#endif /* FLASH_OPTCR_PG_OTP */
+    {
+      if(bank == FLASH_BANK_1)
+      {
+        /* If the program operation is completed, disable the PG */
+        CLEAR_BIT(FLASH->CR1, FLASH_CR_PG);
+      }
+      else
+      {
+        /* If the program operation is completed, disable the PG */
+        CLEAR_BIT(FLASH->CR2, FLASH_CR_PG);
+      }
+    }
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(&pFlash);
+
+  return status;
+}
+
+/**
+  * @brief  Program flash words of 256 bits at a specified address with interrupt enabled.
+  * @param  TypeProgram Indicate the way to program at a specified address.
+  *                      This parameter can be a value of @ref FLASH_Type_Program
+  * @param  FlashAddress specifies the address to be programmed.
+  * @param  DataAddress specifies the address of data (256 bits) to be programmed
+  *
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress)
+{
+  HAL_StatusTypeDef status;
+  __IO uint32_t *dest_addr = (__IO uint32_t*)FlashAddress;
+  __IO uint32_t *src_addr = (__IO uint32_t*)DataAddress;
+  uint32_t bank;
+  uint8_t row_index = FLASH_NB_32BITWORD_IN_FLASHWORD;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+  assert_param(IS_FLASH_PROGRAM_ADDRESS(FlashAddress));
+
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Reset error code */
+  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+#if defined (FLASH_OPTCR_PG_OTP)
+  if((IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress)) || (IS_FLASH_PROGRAM_ADDRESS_OTP(FlashAddress)))
+#else
+  if(IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress))
+#endif /* FLASH_OPTCR_PG_OTP */
+  {
+    bank = FLASH_BANK_1;
+  }
+  else
+  {
+    bank = FLASH_BANK_2;
+  }
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, bank);
+
+  if (status != HAL_OK)
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(&pFlash);
+  }
+  else
+  {
+    pFlash.Address = FlashAddress;
+
+    if(bank == FLASH_BANK_1)
+    {
+      /* Set internal variables used by the IRQ handler */
+      pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_BANK1;
+
+#if defined (FLASH_OPTCR_PG_OTP)
+      if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD)
+      {
+        /* Set OTP_PG bit */
+        SET_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP);
+      }
+      else
+#endif /* FLASH_OPTCR_PG_OTP */
+      {
+        /* Set PG bit */
+        SET_BIT(FLASH->CR1, FLASH_CR_PG);
+      }
+
+      /* Enable End of Operation and Error interrupts for Bank 1 */
+#if defined (FLASH_CR_OPERRIE)
+      __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1     | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
+                                  FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1);
+#else
+      __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1     | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
+                                  FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1);
+#endif /* FLASH_CR_OPERRIE */
+    }
+    else
+    {
+      /* Set internal variables used by the IRQ handler */
+      pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_BANK2;
+
+      /* Set PG bit */
+      SET_BIT(FLASH->CR2, FLASH_CR_PG);
+
+      /* Enable End of Operation and Error interrupts for Bank2 */
+#if defined (FLASH_CR_OPERRIE)
+      __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2     | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
+                                  FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2);
+#else
+      __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2     | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
+                                  FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2);
+#endif /* FLASH_CR_OPERRIE */
+    }
+
+    __ISB();
+    __DSB();
+
+#if defined (FLASH_OPTCR_PG_OTP)
+    if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD)
+    {
+      /* Program an OTP word (16 bits) */
+      *(__IO uint16_t *)FlashAddress = *(__IO uint16_t*)DataAddress;
+    }
+    else
+#endif /* FLASH_OPTCR_PG_OTP */
+    {
+      /* Program the flash word */
+      do
+      {
+        *dest_addr = *src_addr;
+        dest_addr++;
+        src_addr++;
+        row_index--;
+      } while (row_index != 0U);
+    }
+
+    __ISB();
+    __DSB();
+  }
+
+  return status;
+}
+
+/**
+  * @brief This function handles FLASH interrupt request.
+  * @retval None
+  */
+void HAL_FLASH_IRQHandler(void)
+{
+  uint32_t temp;
+  uint32_t errorflag;
+  FLASH_ProcedureTypeDef procedure;
+
+  /* Check FLASH Bank1 End of Operation flag  */
+  if(__HAL_FLASH_GET_FLAG_BANK1(FLASH_SR_EOP) != RESET)
+  {
+    if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE_BANK1)
+    {
+      /* Nb of sector to erased can be decreased */
+      pFlash.NbSectorsToErase--;
+
+      /* Check if there are still sectors to erase */
+      if(pFlash.NbSectorsToErase != 0U)
+      {
+        /* Indicate user which sector has been erased */
+        HAL_FLASH_EndOfOperationCallback(pFlash.Sector);
+
+        /* Clear bank 1 End of Operation pending bit */
+        __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1);
+
+        /* Increment sector number */
+        pFlash.Sector++;
+        temp = pFlash.Sector;
+        FLASH_Erase_Sector(temp, FLASH_BANK_1, pFlash.VoltageForErase);
+      }
+      else
+      {
+        /* No more sectors to Erase, user callback can be called */
+        /* Reset Sector and stop Erase sectors procedure */
+        pFlash.Sector = 0xFFFFFFFFU;
+        pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+
+        /* FLASH EOP interrupt user callback */
+        HAL_FLASH_EndOfOperationCallback(pFlash.Sector);
+
+        /* Clear FLASH End of Operation pending bit */
+        __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1);
+      }
+    }
+    else
+    {
+      procedure = pFlash.ProcedureOnGoing;
+
+      if((procedure == FLASH_PROC_MASSERASE_BANK1) || (procedure == FLASH_PROC_ALLBANK_MASSERASE))
+      {
+        /* MassErase ended. Return the selected bank */
+        /* FLASH EOP interrupt user callback */
+        HAL_FLASH_EndOfOperationCallback(FLASH_BANK_1);
+      }
+      else if(procedure == FLASH_PROC_PROGRAM_BANK1)
+      {
+        /* Program ended. Return the selected address */
+        /* FLASH EOP interrupt user callback */
+        HAL_FLASH_EndOfOperationCallback(pFlash.Address);
+      }
+      else
+      {
+        /* Nothing to do */
+      }
+
+      if((procedure != FLASH_PROC_SECTERASE_BANK2) && \
+         (procedure != FLASH_PROC_MASSERASE_BANK2) && \
+         (procedure != FLASH_PROC_PROGRAM_BANK2))
+      {
+        pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+        /* Clear FLASH End of Operation pending bit */
+        __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1);
+      }
+    }
+  }
+
+  /* Check FLASH Bank2 End of Operation flag  */
+  if(__HAL_FLASH_GET_FLAG_BANK2(FLASH_SR_EOP) != RESET)
+  {
+    if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE_BANK2)
+    {
+      /*Nb of sector to erased can be decreased*/
+      pFlash.NbSectorsToErase--;
+
+      /* Check if there are still sectors to erase*/
+      if(pFlash.NbSectorsToErase != 0U)
+      {
+        /*Indicate user which sector has been erased*/
+        HAL_FLASH_EndOfOperationCallback(pFlash.Sector);
+
+        /* Clear bank 2 End of Operation pending bit */
+        __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2);
+
+        /*Increment sector number*/
+        pFlash.Sector++;
+        temp = pFlash.Sector;
+        FLASH_Erase_Sector(temp, FLASH_BANK_2, pFlash.VoltageForErase);
+      }
+      else
+      {
+        /* No more sectors to Erase, user callback can be called */
+        /* Reset Sector and stop Erase sectors procedure */
+        pFlash.Sector = 0xFFFFFFFFU;
+        pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+
+        /* FLASH EOP interrupt user callback */
+        HAL_FLASH_EndOfOperationCallback(pFlash.Sector);
+
+        /* Clear FLASH End of Operation pending bit */
+        __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2);
+      }
+    }
+    else
+    {
+      procedure = pFlash.ProcedureOnGoing;
+
+      if((procedure == FLASH_PROC_MASSERASE_BANK2) || (procedure == FLASH_PROC_ALLBANK_MASSERASE))
+      {
+        /*MassErase ended. Return the selected bank*/
+        /* FLASH EOP interrupt user callback */
+        HAL_FLASH_EndOfOperationCallback(FLASH_BANK_2);
+      }
+      else if(procedure == FLASH_PROC_PROGRAM_BANK2)
+      {
+        /* Program ended. Return the selected address */
+        /* FLASH EOP interrupt user callback */
+        HAL_FLASH_EndOfOperationCallback(pFlash.Address);
+      }
+      else
+      {
+        /* Nothing to do */
+      }
+
+      if((procedure != FLASH_PROC_SECTERASE_BANK1) && \
+         (procedure != FLASH_PROC_MASSERASE_BANK1) && \
+         (procedure != FLASH_PROC_PROGRAM_BANK1))
+      {
+        pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+        /* Clear FLASH End of Operation pending bit */
+        __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2);
+      }
+    }
+  }
+
+  /* Check FLASH Bank1 operation error flags */
+#if defined (FLASH_SR_OPERR)
+  errorflag = FLASH->SR1 & (FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | FLASH_FLAG_STRBERR_BANK1 | \
+                            FLASH_FLAG_INCERR_BANK1 | FLASH_FLAG_OPERR_BANK1);
+#else
+  errorflag = FLASH->SR1 & (FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | FLASH_FLAG_STRBERR_BANK1 | \
+                            FLASH_FLAG_INCERR_BANK1);
+#endif /* FLASH_SR_OPERR */
+
+  if(errorflag != 0U)
+  {
+    /* Save the error code */
+    pFlash.ErrorCode |= errorflag;
+
+    /* Clear error programming flags */
+    __HAL_FLASH_CLEAR_FLAG_BANK1(errorflag);
+
+    procedure = pFlash.ProcedureOnGoing;
+
+    if(procedure == FLASH_PROC_SECTERASE_BANK1)
+    {
+      /* Return the faulty sector */
+      temp = pFlash.Sector;
+      pFlash.Sector = 0xFFFFFFFFU;
+    }
+    else if((procedure == FLASH_PROC_MASSERASE_BANK1) || (procedure == FLASH_PROC_ALLBANK_MASSERASE))
+    {
+      /* Return the faulty bank */
+      temp = FLASH_BANK_1;
+    }
+    else
+    {
+      /* Return the faulty address */
+      temp = pFlash.Address;
+    }
+
+    /* Stop the procedure ongoing*/
+    pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+
+    /* FLASH error interrupt user callback */
+    HAL_FLASH_OperationErrorCallback(temp);
+  }
+
+  /* Check FLASH Bank2 operation error flags */
+#if defined (FLASH_SR_OPERR)
+  errorflag = FLASH->SR2 & ((FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | FLASH_FLAG_STRBERR_BANK2 | \
+                             FLASH_FLAG_INCERR_BANK2 | FLASH_FLAG_OPERR_BANK2) & 0x7FFFFFFFU);
+#else
+  errorflag = FLASH->SR2 & ((FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | FLASH_FLAG_STRBERR_BANK2 | \
+                             FLASH_FLAG_INCERR_BANK2) & 0x7FFFFFFFU);
+#endif /* FLASH_SR_OPERR */
+
+  if(errorflag != 0U)
+  {
+    /* Save the error code */
+    pFlash.ErrorCode |= (errorflag | 0x80000000U);
+
+    /* Clear error programming flags */
+    __HAL_FLASH_CLEAR_FLAG_BANK2(errorflag);
+
+    procedure = pFlash.ProcedureOnGoing;
+
+    if(procedure== FLASH_PROC_SECTERASE_BANK2)
+    {
+      /*return the faulty sector*/
+      temp = pFlash.Sector;
+      pFlash.Sector = 0xFFFFFFFFU;
+    }
+    else if((procedure == FLASH_PROC_MASSERASE_BANK2) || (procedure == FLASH_PROC_ALLBANK_MASSERASE))
+    {
+      /*return the faulty bank*/
+      temp = FLASH_BANK_2;
+    }
+    else
+    {
+      /*return the faulty address*/
+      temp = pFlash.Address;
+    }
+
+    /*Stop the procedure ongoing*/
+    pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+
+    /* FLASH error interrupt user callback */
+    HAL_FLASH_OperationErrorCallback(temp);
+  }
+
+  if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
+  {
+#if defined (FLASH_CR_OPERRIE)
+    /* Disable Bank1 Operation and Error source interrupt */
+    __HAL_FLASH_DISABLE_IT_BANK1(FLASH_IT_EOP_BANK1    | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
+                                 FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1);
+
+    /* Disable Bank2 Operation and Error source interrupt */
+    __HAL_FLASH_DISABLE_IT_BANK2(FLASH_IT_EOP_BANK2    | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
+                                 FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2);
+#else
+    /* Disable Bank1 Operation and Error source interrupt */
+    __HAL_FLASH_DISABLE_IT_BANK1(FLASH_IT_EOP_BANK1    | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
+                                 FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1);
+
+    /* Disable Bank2 Operation and Error source interrupt */
+    __HAL_FLASH_DISABLE_IT_BANK2(FLASH_IT_EOP_BANK2    | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
+                                 FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2);
+#endif /* FLASH_CR_OPERRIE */
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(&pFlash);
+  }
+}
+
+/**
+  * @brief  FLASH end of operation interrupt callback
+  * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure
+  *                  Mass Erase: Bank number which has been requested to erase
+  *                  Sectors Erase: Sector which has been erased
+  *                    (if 0xFFFFFFFF, it means that all the selected sectors have been erased)
+  *                  Program: Address which was selected for data program
+  * @retval None
+  */
+__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(ReturnValue);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  FLASH operation error interrupt callback
+  * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure
+  *                 Mass Erase: Bank number which has been requested to erase
+  *                 Sectors Erase: Sector number which returned an error
+  *                 Program: Address which was selected for data program
+  * @retval None
+  */
+__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(ReturnValue);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FLASH_OperationErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
+ *  @brief   Management functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the FLASH
+    memory operations.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Unlock the FLASH control registers access
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Unlock(void)
+{
+  if(READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != 0U)
+  {
+    /* Authorize the FLASH Bank1 Registers access */
+    WRITE_REG(FLASH->KEYR1, FLASH_KEY1);
+    WRITE_REG(FLASH->KEYR1, FLASH_KEY2);
+
+    /* Verify Flash Bank1 is unlocked */
+    if (READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != 0U)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  if(READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != 0U)
+  {
+    /* Authorize the FLASH Bank2 Registers access */
+    WRITE_REG(FLASH->KEYR2, FLASH_KEY1);
+    WRITE_REG(FLASH->KEYR2, FLASH_KEY2);
+
+    /* Verify Flash Bank2 is unlocked */
+    if (READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != 0U)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Locks the FLASH control registers access
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Lock(void)
+{
+  /* Set the LOCK Bit to lock the FLASH Bank1 Control Register access */
+  SET_BIT(FLASH->CR1, FLASH_CR_LOCK);
+
+  /* Verify Flash Bank1 is locked */
+  if (READ_BIT(FLASH->CR1, FLASH_CR_LOCK) == 0U)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the LOCK Bit to lock the FLASH Bank2 Control Register access */
+  SET_BIT(FLASH->CR2, FLASH_CR_LOCK);
+
+  /* Verify Flash Bank2 is locked */
+  if (READ_BIT(FLASH->CR2, FLASH_CR_LOCK) == 0U)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Unlock the FLASH Option Control Registers access.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
+{
+  if(READ_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK) != 0U)
+  {
+    /* Authorizes the Option Byte registers programming */
+    WRITE_REG(FLASH->OPTKEYR, FLASH_OPT_KEY1);
+    WRITE_REG(FLASH->OPTKEYR, FLASH_OPT_KEY2);
+
+    /* Verify that the Option Bytes are unlocked */
+    if (READ_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK) != 0U)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Lock the FLASH Option Control Registers access.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
+{
+  /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
+  SET_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK);
+
+  /* Verify that the Option Bytes are locked */
+  if (READ_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK) == 0U)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Launch the option bytes loading.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
+{
+  HAL_StatusTypeDef status;
+
+  /* Wait for CRC computation to be completed */
+  if (FLASH_CRC_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK)
+  {
+    status = HAL_ERROR;
+  }
+  else if (FLASH_CRC_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    status = HAL_OK;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Set OPTSTRT Bit */
+    SET_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTSTART);
+
+    /* Wait for OB change operation to be completed */
+    status = FLASH_OB_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+  }
+
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions
+ *  @brief   Peripheral Errors functions
+ *
+@verbatim
+ ===============================================================================
+                ##### Peripheral Errors functions #####
+ ===============================================================================
+    [..]
+    This subsection permits to get in run-time Errors of the FLASH peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Get the specific FLASH error flag.
+  * @retval HAL_FLASH_ERRORCode The returned value can be:
+  *            @arg HAL_FLASH_ERROR_NONE       : No error set
+  *
+  *            @arg HAL_FLASH_ERROR_WRP_BANK1  : Write Protection Error on Bank 1
+  *            @arg HAL_FLASH_ERROR_PGS_BANK1  : Program Sequence Error on Bank 1
+  *            @arg HAL_FLASH_ERROR_STRB_BANK1 : Strobe Error on Bank 1
+  *            @arg HAL_FLASH_ERROR_INC_BANK1  : Inconsistency Error on Bank 1
+  *            @arg HAL_FLASH_ERROR_OPE_BANK1  : Operation Error on Bank 1
+  *            @arg HAL_FLASH_ERROR_RDP_BANK1  : Read Protection Error on Bank 1
+  *            @arg HAL_FLASH_ERROR_RDS_BANK1  : Read Secured Error on Bank 1
+  *            @arg HAL_FLASH_ERROR_SNECC_BANK1: ECC Single Correction Error on Bank 1
+  *            @arg HAL_FLASH_ERROR_DBECC_BANK1: ECC Double Detection Error on Bank 1
+  *            @arg HAL_FLASH_ERROR_CRCRD_BANK1: CRC Read Error on Bank 1
+  *
+  *            @arg HAL_FLASH_ERROR_WRP_BANK2  : Write Protection Error on Bank 2
+  *            @arg HAL_FLASH_ERROR_PGS_BANK2  : Program Sequence Error on Bank 2
+  *            @arg HAL_FLASH_ERROR_STRB_BANK2 : Strobe Error on Bank 2
+  *            @arg HAL_FLASH_ERROR_INC_BANK2  : Inconsistency Error on Bank 2
+  *            @arg HAL_FLASH_ERROR_OPE_BANK2  : Operation Error on Bank 2
+  *            @arg HAL_FLASH_ERROR_RDP_BANK2  : Read Protection Error on Bank 2
+  *            @arg HAL_FLASH_ERROR_RDS_BANK2  : Read Secured Error on Bank 2
+  *            @arg HAL_FLASH_ERROR_SNECC_BANK2: SNECC Error on Bank 2
+  *            @arg HAL_FLASH_ERROR_DBECC_BANK2: Double Detection ECC on Bank 2
+  *            @arg HAL_FLASH_ERROR_CRCRD_BANK2: CRC Read Error on Bank 2
+*/
+
+uint32_t HAL_FLASH_GetError(void)
+{
+   return pFlash.ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @addtogroup FLASH_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Wait for a FLASH operation to complete.
+  * @param  Timeout maximum flash operation timeout
+  * @param  Bank flash FLASH_BANK_1 or FLASH_BANK_2
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout, uint32_t Bank)
+{
+  /* Wait for the FLASH operation to complete by polling on QW flag to be reset.
+     Even if the FLASH operation fails, the QW flag will be reset and an error
+     flag will be set */
+
+  uint32_t bsyflag, errorflag;
+  uint32_t tickstart = HAL_GetTick();
+
+  assert_param(IS_FLASH_BANK_EXCLUSIVE(Bank));
+
+  /* Select bsyflag depending on Bank */
+  if(Bank == FLASH_BANK_1)
+  {
+    bsyflag = FLASH_FLAG_QW_BANK1;
+  }
+  else
+  {
+    bsyflag = FLASH_FLAG_QW_BANK2;
+  }
+
+  while(__HAL_FLASH_GET_FLAG(bsyflag))
+  {
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  /* Get Error Flags */
+  if (Bank == FLASH_BANK_1)
+  {
+    errorflag = FLASH->SR1 & FLASH_FLAG_ALL_ERRORS_BANK1;
+  }
+  else
+  {
+    errorflag = (FLASH->SR2 & FLASH_FLAG_ALL_ERRORS_BANK2) | 0x80000000U;
+  }
+
+  /* In case of error reported in Flash SR1 or SR2 registers (ECCC not managed as an error) */
+  if((errorflag & 0x7DFFFFFFU) != 0U)
+  {
+    /*Save the error code*/
+    pFlash.ErrorCode |= errorflag;
+
+    /* Clear error programming flags */
+    __HAL_FLASH_CLEAR_FLAG(errorflag);
+
+    return HAL_ERROR;
+  }
+
+  /* Check FLASH End of Operation flag  */
+  if(Bank == FLASH_BANK_1)
+  {
+    if (__HAL_FLASH_GET_FLAG_BANK1(FLASH_FLAG_EOP_BANK1))
+    {
+      /* Clear FLASH End of Operation pending bit */
+      __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1);
+    }
+  }
+  else
+  {
+    if (__HAL_FLASH_GET_FLAG_BANK2(FLASH_FLAG_EOP_BANK2))
+    {
+      /* Clear FLASH End of Operation pending bit */
+      __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2);
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Wait for a FLASH Option Bytes change operation to complete.
+  * @param  Timeout maximum flash operation timeout
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef FLASH_OB_WaitForLastOperation(uint32_t Timeout)
+{
+  /* Get timeout */
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Wait for the FLASH Option Bytes change operation to complete by polling on OPT_BUSY flag to be reset */
+  while(READ_BIT(FLASH->OPTSR_CUR, FLASH_OPTSR_OPT_BUSY) != 0U)
+  {
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  /* Check option byte change error */
+  if(READ_BIT(FLASH->OPTSR_CUR, FLASH_OPTSR_OPTCHANGEERR) != 0U)
+  {
+    /* Save the error code */
+    pFlash.ErrorCode |= HAL_FLASH_ERROR_OB_CHANGE;
+
+    /* Clear the OB error flag */
+    FLASH->OPTCCR |= FLASH_OPTCCR_CLR_OPTCHANGEERR;
+
+    return HAL_ERROR;
+  }
+
+  /* If there is no error flag set */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Wait for a FLASH CRC computation to complete.
+  * @param  Timeout maximum flash operation timeout
+  * @param  Bank flash FLASH_BANK_1 or FLASH_BANK_2
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef FLASH_CRC_WaitForLastOperation(uint32_t Timeout, uint32_t Bank)
+{
+  uint32_t bsyflag;
+  uint32_t tickstart = HAL_GetTick();
+
+  assert_param(IS_FLASH_BANK_EXCLUSIVE(Bank));
+
+  /* Select bsyflag depending on Bank */
+  if(Bank == FLASH_BANK_1)
+  {
+    bsyflag = FLASH_FLAG_CRC_BUSY_BANK1;
+  }
+  else
+  {
+    bsyflag = FLASH_FLAG_CRC_BUSY_BANK2;
+  }
+
+  /* Wait for the FLASH CRC computation to complete by polling on CRC_BUSY flag to be reset */
+  while(__HAL_FLASH_GET_FLAG(bsyflag))
+  {
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  /* Check FLASH CRC read error flag  */
+  if(Bank == FLASH_BANK_1)
+  {
+    if (__HAL_FLASH_GET_FLAG_BANK1(FLASH_FLAG_CRCRDERR_BANK1))
+    {
+      /* Save the error code */
+      pFlash.ErrorCode |= HAL_FLASH_ERROR_CRCRD_BANK1;
+
+      /* Clear FLASH CRC read error pending bit */
+      __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_CRCRDERR_BANK1);
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    if (__HAL_FLASH_GET_FLAG_BANK2(FLASH_FLAG_CRCRDERR_BANK2))
+    {
+      /* Save the error code */
+      pFlash.ErrorCode |= HAL_FLASH_ERROR_CRCRD_BANK2;
+
+      /* Clear FLASH CRC read error pending bit */
+      __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_CRCRDERR_BANK2);
+
+      return HAL_ERROR;
+    }
+  }
+
+  /* If there is no error flag set */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c
new file mode 100644
index 00000000..77b809f7
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c
@@ -0,0 +1,1709 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_flash_ex.c
+  * @author  MCD Application Team
+  * @brief   Extended FLASH HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the FLASH extension peripheral:
+  *           + Extended programming operations functions
+  *
+ @verbatim
+ ==============================================================================
+                   ##### Flash Extension features #####
+  ==============================================================================
+
+  [..] Comparing to other previous devices, the FLASH interface for STM32H7xx
+       devices contains the following additional features
+
+       (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
+           capability (RWW)
+       (+) Dual bank memory organization
+       (+) PCROP protection for all banks
+       (+) Global readout protection (RDP)
+       (+) Write protection
+       (+) Secure access only protection
+       (+) Bank / register swapping
+       (+) Cyclic Redundancy Check (CRC)
+
+                        ##### How to use this driver #####
+ ==============================================================================
+  [..] This driver provides functions to configure and program the FLASH memory
+       of all STM32H7xx devices. It includes
+      (#) FLASH Memory Erase functions:
+           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
+                HAL_FLASH_Lock() functions
+           (++) Erase function: Sector erase, bank erase and dual-bank mass erase
+           (++) There are two modes of erase :
+             (+++) Polling Mode using HAL_FLASHEx_Erase()
+             (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
+
+      (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to:
+        (++) Set/Reset the write protection per bank
+        (++) Set the Read protection Level
+        (++) Set the BOR level
+        (++) Program the user Option Bytes
+        (++) PCROP protection configuration and control per bank
+        (++) Secure area configuration and control per bank
+        (++) Core Boot address configuration
+
+      (#) FLASH Memory Lock and unlock per Bank: HAL_FLASHEx_Lock_Bank1(), HAL_FLASHEx_Unlock_Bank1(),
+          HAL_FLASHEx_Lock_Bank2() and HAL_FLASHEx_Unlock_Bank2() functions
+
+      (#) FLASH CRC computation function: Use HAL_FLASHEx_ComputeCRC() to:
+          (++) Enable CRC feature
+          (++) Program the desired burst size
+          (++) Define the user Flash Area on which the CRC has be computed
+          (++) Perform the CRC computation
+          (++) Disable CRC feature
+
+ @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup FLASHEx  FLASHEx
+  * @brief FLASH HAL Extension module driver
+  * @{
+  */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup FLASHEx_Private_Constants
+  * @{
+  */
+#define FLASH_TIMEOUT_VALUE       50000U /* 50 s */
+
+/**
+  * @}
+  */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
+  * @{
+  */
+static void FLASH_MassErase(uint32_t VoltageRange, uint32_t Banks);
+static void FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks);
+static void FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Bank);
+static void FLASH_OB_GetWRP(uint32_t *WRPState, uint32_t *WRPSector, uint32_t Bank);
+static void FLASH_OB_RDPConfig(uint32_t RDPLevel);
+static uint32_t FLASH_OB_GetRDP(void);
+static void FLASH_OB_PCROPConfig(uint32_t PCROConfigRDP, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr, uint32_t Banks);
+static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROPStartAddr,uint32_t *PCROPEndAddr, uint32_t Bank);
+static void FLASH_OB_BOR_LevelConfig(uint32_t Level);
+static uint32_t FLASH_OB_GetBOR(void);
+static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig);
+static uint32_t FLASH_OB_GetUser(void);
+static void FLASH_OB_BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1);
+static void FLASH_OB_GetBootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1);
+static void FLASH_OB_SecureAreaConfig(uint32_t SecureAreaConfig, uint32_t SecureAreaStartAddr, uint32_t SecureAreaEndAddr, uint32_t Banks);
+static void FLASH_OB_GetSecureArea(uint32_t *SecureAreaConfig, uint32_t *SecureAreaStartAddr, uint32_t *SecureAreaEndAddr, uint32_t Bank);
+static void FLASH_CRC_AddSector(uint32_t Sector, uint32_t Bank);
+static void FLASH_CRC_SelectAddress(uint32_t CRCStartAddr, uint32_t CRCEndAddr, uint32_t Bank);
+
+#if defined (DUAL_CORE)
+static void FLASH_OB_CM4BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1);
+static void FLASH_OB_GetCM4BootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1);
+#endif /* DUAL_CORE */
+
+#if defined (FLASH_OTPBL_LOCKBL)
+static void FLASH_OB_OTP_LockConfig(uint32_t OTP_Block);
+static uint32_t FLASH_OB_OTP_GetLock(void);
+#endif /* FLASH_OTPBL_LOCKBL */
+/**
+  * @}
+  */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
+  * @{
+  */
+
+/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
+ *  @brief   Extended IO operation functions
+ *
+@verbatim
+ ===============================================================================
+                ##### Extended programming operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the Extension FLASH
+    programming operations Operations.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Perform a mass erase or erase the specified FLASH memory sectors
+  * @param[in]  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
+  *         contains the configuration information for the erasing.
+  *
+  * @param[out]  SectorError pointer to variable  that contains the configuration
+  *          information on faulty sector in case of error (0xFFFFFFFF means that all
+  *          the sectors have been correctly erased)
+  *
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t sector_index;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
+  assert_param(IS_FLASH_BANK(pEraseInit->Banks));
+
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Reset error code */
+  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+  /* Wait for last operation to be completed on Bank1 */
+  if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
+  {
+    if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK)
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  /* Wait for last operation to be completed on Bank2 */
+  if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
+  {
+    if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK)
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  if(status == HAL_OK)
+  {
+    if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
+    {
+      /* Mass erase to be done */
+      FLASH_MassErase(pEraseInit->VoltageRange, pEraseInit->Banks);
+
+      /* Wait for last operation to be completed */
+      if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
+      {
+        if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK)
+        {
+          status = HAL_ERROR;
+        }
+        /* if the erase operation is completed, disable the Bank1 BER Bit */
+        FLASH->CR1 &= (~FLASH_CR_BER);
+      }
+      if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
+      {
+        if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK)
+        {
+          status = HAL_ERROR;
+        }
+        /* if the erase operation is completed, disable the Bank2 BER Bit */
+        FLASH->CR2 &= (~FLASH_CR_BER);
+      }
+    }
+    else
+    {
+      /*Initialization of SectorError variable*/
+      *SectorError = 0xFFFFFFFFU;
+
+      /* Erase by sector by sector to be done*/
+      for(sector_index = pEraseInit->Sector; sector_index < (pEraseInit->NbSectors + pEraseInit->Sector); sector_index++)
+      {
+        FLASH_Erase_Sector(sector_index, pEraseInit->Banks, pEraseInit->VoltageRange);
+
+        if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
+        {
+          /* Wait for last operation to be completed */
+          status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
+
+          /* If the erase operation is completed, disable the SER Bit */
+          FLASH->CR1 &= (~(FLASH_CR_SER | FLASH_CR_SNB));
+        }
+        if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
+        {
+          /* Wait for last operation to be completed */
+          status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
+
+          /* If the erase operation is completed, disable the SER Bit */
+          FLASH->CR2 &= (~(FLASH_CR_SER | FLASH_CR_SNB));
+        }
+
+        if(status != HAL_OK)
+        {
+          /* In case of error, stop erase procedure and return the faulty sector */
+          *SectorError = sector_index;
+          break;
+        }
+      }
+    }
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(&pFlash);
+
+  return status;
+}
+
+/**
+  * @brief  Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled
+  * @param  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
+  *         contains the configuration information for the erasing.
+  *
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
+  assert_param(IS_FLASH_BANK(pEraseInit->Banks));
+
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Reset error code */
+  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+  /* Wait for last operation to be completed */
+  if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
+  {
+    if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK)
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
+  {
+    if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK)
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  if (status != HAL_OK)
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(&pFlash);
+  }
+  else
+  {
+    if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
+    {
+      /* Enable End of Operation and Error interrupts for Bank 1 */
+#if defined (FLASH_CR_OPERRIE)
+      __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1     | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
+                                  FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1);
+#else
+      __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1     | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
+                                  FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1);
+#endif /* FLASH_CR_OPERRIE */
+    }
+    if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
+    {
+      /* Enable End of Operation and Error interrupts for Bank 2 */
+#if defined (FLASH_CR_OPERRIE)
+      __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2     | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
+                                  FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2);
+#else
+      __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2     | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
+                                  FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2);
+#endif /* FLASH_CR_OPERRIE */
+    }
+
+    if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
+    {
+      /*Mass erase to be done*/
+      if(pEraseInit->Banks == FLASH_BANK_1)
+      {
+        pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE_BANK1;
+      }
+      else if(pEraseInit->Banks == FLASH_BANK_2)
+      {
+        pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE_BANK2;
+      }
+      else
+      {
+        pFlash.ProcedureOnGoing = FLASH_PROC_ALLBANK_MASSERASE;
+      }
+
+      FLASH_MassErase(pEraseInit->VoltageRange, pEraseInit->Banks);
+    }
+    else
+    {
+      /* Erase by sector to be done */
+      if(pEraseInit->Banks == FLASH_BANK_1)
+      {
+        pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE_BANK1;
+      }
+      else
+      {
+        pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE_BANK2;
+      }
+
+      pFlash.NbSectorsToErase = pEraseInit->NbSectors;
+      pFlash.Sector = pEraseInit->Sector;
+      pFlash.VoltageForErase = pEraseInit->VoltageRange;
+
+      /* Erase first sector and wait for IT */
+      FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->Banks, pEraseInit->VoltageRange);
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Program option bytes
+  * @param  pOBInit pointer to an FLASH_OBInitStruct structure that
+  *         contains the configuration information for the programming.
+  *
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check the parameters */
+  assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
+
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Reset Error Code */
+  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+  /* Wait for last operation to be completed */
+  if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK)
+  {
+    status = HAL_ERROR;
+  }
+  else if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    status = HAL_OK;
+  }
+
+  if(status == HAL_OK)
+  {
+    /*Write protection configuration*/
+    if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
+    {
+      assert_param(IS_WRPSTATE(pOBInit->WRPState));
+
+      if(pOBInit->WRPState == OB_WRPSTATE_ENABLE)
+      {
+        /*Enable of Write protection on the selected Sector*/
+        FLASH_OB_EnableWRP(pOBInit->WRPSector,pOBInit->Banks);
+      }
+      else
+      {
+        /*Disable of Write protection on the selected Sector*/
+        FLASH_OB_DisableWRP(pOBInit->WRPSector, pOBInit->Banks);
+      }
+    }
+
+    /* Read protection configuration */
+    if((pOBInit->OptionType & OPTIONBYTE_RDP) != 0U)
+    {
+      /* Configure the Read protection level */
+      FLASH_OB_RDPConfig(pOBInit->RDPLevel);
+    }
+
+    /* User Configuration */
+    if((pOBInit->OptionType & OPTIONBYTE_USER) != 0U)
+    {
+      /* Configure the user option bytes */
+      FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig);
+    }
+
+    /* PCROP Configuration */
+    if((pOBInit->OptionType & OPTIONBYTE_PCROP) != 0U)
+    {
+      assert_param(IS_FLASH_BANK(pOBInit->Banks));
+
+      /*Configure the Proprietary code readout protection */
+      FLASH_OB_PCROPConfig(pOBInit->PCROPConfig, pOBInit->PCROPStartAddr, pOBInit->PCROPEndAddr, pOBInit->Banks);
+    }
+
+    /* BOR Level configuration */
+    if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR)
+    {
+      FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel);
+    }
+
+#if defined(DUAL_CORE)
+    /* CM7 Boot Address  configuration */
+    if((pOBInit->OptionType & OPTIONBYTE_CM7_BOOTADD) == OPTIONBYTE_CM7_BOOTADD)
+    {
+      FLASH_OB_BootAddConfig(pOBInit->BootConfig, pOBInit->BootAddr0, pOBInit->BootAddr1);
+    }
+
+    /* CM4 Boot Address  configuration */
+    if((pOBInit->OptionType & OPTIONBYTE_CM4_BOOTADD) == OPTIONBYTE_CM4_BOOTADD)
+    {
+      FLASH_OB_CM4BootAddConfig(pOBInit->CM4BootConfig, pOBInit->CM4BootAddr0, pOBInit->CM4BootAddr1);
+    }
+#else /* Single Core*/
+    /* Boot Address  configuration */
+    if((pOBInit->OptionType & OPTIONBYTE_BOOTADD) == OPTIONBYTE_BOOTADD)
+    {
+      FLASH_OB_BootAddConfig(pOBInit->BootConfig, pOBInit->BootAddr0, pOBInit->BootAddr1);
+    }
+#endif /*DUAL_CORE*/
+
+    /* Secure area configuration */
+    if((pOBInit->OptionType & OPTIONBYTE_SECURE_AREA) == OPTIONBYTE_SECURE_AREA)
+    {
+      FLASH_OB_SecureAreaConfig(pOBInit->SecureAreaConfig, pOBInit->SecureAreaStartAddr, pOBInit->SecureAreaEndAddr,pOBInit->Banks);
+    }
+
+#if defined(FLASH_OTPBL_LOCKBL)
+    /* OTP Block Lock configuration */
+    if((pOBInit->OptionType & OPTIONBYTE_OTP_LOCK) == OPTIONBYTE_OTP_LOCK)
+    {
+      FLASH_OB_OTP_LockConfig(pOBInit->OTPBlockLock);
+    }
+#endif /* FLASH_OTPBL_LOCKBL */
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(&pFlash);
+
+  return status;
+}
+
+/**
+  * @brief Get the Option byte configuration
+  * @param  pOBInit pointer to an FLASH_OBInitStruct structure that
+  *         contains the configuration information for the programming.
+  * @note   The parameter Banks of the pOBInit structure must be set exclusively to FLASH_BANK_1 or FLASH_BANK_2,
+  *         as this parameter is use to get the given Bank WRP, PCROP and secured area configuration.
+  *
+  * @retval None
+  */
+void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
+{
+  pOBInit->OptionType = (OPTIONBYTE_USER | OPTIONBYTE_RDP | OPTIONBYTE_BOR);
+
+  /* Get Read protection level */
+  pOBInit->RDPLevel = FLASH_OB_GetRDP();
+
+  /* Get the user option bytes */
+  pOBInit->USERConfig = FLASH_OB_GetUser();
+
+  /*Get BOR Level*/
+  pOBInit->BORLevel = FLASH_OB_GetBOR();
+
+  if ((pOBInit->Banks == FLASH_BANK_1) || (pOBInit->Banks == FLASH_BANK_2))
+  {
+    pOBInit->OptionType |= (OPTIONBYTE_WRP | OPTIONBYTE_PCROP | OPTIONBYTE_SECURE_AREA);
+
+    /* Get write protection on the selected area */
+    FLASH_OB_GetWRP(&(pOBInit->WRPState), &(pOBInit->WRPSector), pOBInit->Banks);
+
+    /* Get the Proprietary code readout protection */
+    FLASH_OB_GetPCROP(&(pOBInit->PCROPConfig), &(pOBInit->PCROPStartAddr), &(pOBInit->PCROPEndAddr), pOBInit->Banks);
+
+    /*Get Bank Secure area*/
+    FLASH_OB_GetSecureArea(&(pOBInit->SecureAreaConfig), &(pOBInit->SecureAreaStartAddr), &(pOBInit->SecureAreaEndAddr), pOBInit->Banks);
+  }
+
+  /*Get Boot Address*/
+  FLASH_OB_GetBootAdd(&(pOBInit->BootAddr0), &(pOBInit->BootAddr1));
+#if defined(DUAL_CORE)
+  pOBInit->OptionType |= OPTIONBYTE_CM7_BOOTADD | OPTIONBYTE_CM4_BOOTADD;
+
+  /*Get CM4 Boot Address*/
+  FLASH_OB_GetCM4BootAdd(&(pOBInit->CM4BootAddr0), &(pOBInit->CM4BootAddr1));
+#else
+  pOBInit->OptionType |= OPTIONBYTE_BOOTADD;
+#endif /*DUAL_CORE*/
+
+#if defined (FLASH_OTPBL_LOCKBL)
+  pOBInit->OptionType |= OPTIONBYTE_OTP_LOCK;
+
+  /* Get OTP Block Lock */
+  pOBInit->OTPBlockLock = FLASH_OB_OTP_GetLock();
+#endif /* FLASH_OTPBL_LOCKBL */
+}
+
+/**
+  * @brief  Unlock the FLASH Bank1 control registers access
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank1(void)
+{
+  if(READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != 0U)
+  {
+    /* Authorize the FLASH Bank1 Registers access */
+    WRITE_REG(FLASH->KEYR1, FLASH_KEY1);
+    WRITE_REG(FLASH->KEYR1, FLASH_KEY2);
+
+    /* Verify Flash Bank1 is unlocked */
+    if (READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != 0U)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Locks the FLASH Bank1 control registers access
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1(void)
+{
+  /* Set the LOCK Bit to lock the FLASH Bank1 Registers access */
+  SET_BIT(FLASH->CR1, FLASH_CR_LOCK);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Unlock the FLASH Bank2 control registers access
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank2(void)
+{
+  if(READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != 0U)
+  {
+    /* Authorize the FLASH Bank2 Registers access */
+    WRITE_REG(FLASH->KEYR2, FLASH_KEY1);
+    WRITE_REG(FLASH->KEYR2, FLASH_KEY2);
+
+    /* Verify Flash Bank1 is unlocked */
+    if (READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != 0U)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Locks the FLASH Bank2 control registers access
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank2(void)
+{
+  /* Set the LOCK Bit to lock the FLASH Bank2 Registers access */
+  SET_BIT(FLASH->CR2, FLASH_CR_LOCK);
+  return HAL_OK;
+}
+
+/*
+  * @brief  Perform a CRC computation on the specified FLASH memory area
+  * @param  pCRCInit pointer to an FLASH_CRCInitTypeDef structure that
+  *         contains the configuration information for the CRC computation.
+  * @note   CRC computation uses CRC-32 (Ethernet) polynomial 0x4C11DB7
+  * @note   The application should avoid running a CRC on PCROP or secure-only
+  *         user Flash memory area since it may alter the expected CRC value.
+  *         A special error flag (CRC read error: CRCRDERR) can be used to
+  *         detect such a case.
+  * @retval HAL Status
+*/
+HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_t *CRC_Result)
+{
+  HAL_StatusTypeDef status;
+  uint32_t sector_index;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_BANK_EXCLUSIVE(pCRCInit->Bank));
+  assert_param(IS_FLASH_TYPECRC(pCRCInit->TypeCRC));
+
+  /* Wait for OB change operation to be completed */
+  status = FLASH_OB_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if (status == HAL_OK)
+  {
+    if (pCRCInit->Bank == FLASH_BANK_1)
+    {
+      /* Enable CRC feature */
+      FLASH->CR1 |= FLASH_CR_CRC_EN;
+
+      /* Clear CRC flags in Status Register: CRC end of calculation and CRC read error */
+      FLASH->CCR1 |= (FLASH_CCR_CLR_CRCEND | FLASH_CCR_CLR_CRCRDERR);
+
+      /* Clear current CRC result, program burst size and define memory area on which CRC has to be computed */
+      FLASH->CRCCR1 |= FLASH_CRCCR_CLEAN_CRC | pCRCInit->BurstSize | pCRCInit->TypeCRC;
+
+      if (pCRCInit->TypeCRC == FLASH_CRC_SECTORS)
+      {
+        /* Clear sectors list */
+        FLASH->CRCCR1 |= FLASH_CRCCR_CLEAN_SECT;
+
+        /* Select CRC sectors */
+        for(sector_index = pCRCInit->Sector; sector_index < (pCRCInit->NbSectors + pCRCInit->Sector); sector_index++)
+        {
+          FLASH_CRC_AddSector(sector_index, FLASH_BANK_1);
+        }
+      }
+      else if (pCRCInit->TypeCRC == FLASH_CRC_BANK)
+      {
+        /* Enable Bank 1 CRC select bit */
+        FLASH->CRCCR1 |= FLASH_CRCCR_ALL_BANK;
+      }
+      else
+      {
+        /* Select CRC start and end addresses */
+        FLASH_CRC_SelectAddress(pCRCInit->CRCStartAddr, pCRCInit->CRCEndAddr, FLASH_BANK_1);
+      }
+
+      /* Start the CRC calculation */
+      FLASH->CRCCR1 |= FLASH_CRCCR_START_CRC;
+
+      /* Wait on CRC busy flag */
+      status = FLASH_CRC_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
+
+      /* Return CRC result */
+      (*CRC_Result) = FLASH->CRCDATA;
+
+      /* Disable CRC feature */
+      FLASH->CR1 &= (~FLASH_CR_CRC_EN);
+
+      /* Clear CRC flags */
+      __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_CRCEND_BANK1 | FLASH_FLAG_CRCRDERR_BANK1);
+    }
+    else
+    {
+      /* Enable CRC feature */
+      FLASH->CR2 |= FLASH_CR_CRC_EN;
+
+      /* Clear CRC flags in Status Register: CRC end of calculation and CRC read error */
+      FLASH->CCR2 |= (FLASH_CCR_CLR_CRCEND | FLASH_CCR_CLR_CRCRDERR);
+
+      /* Clear current CRC result, program burst size and define memory area on which CRC has to be computed */
+      FLASH->CRCCR2 |= FLASH_CRCCR_CLEAN_CRC | pCRCInit->BurstSize | pCRCInit->TypeCRC;
+
+      if (pCRCInit->TypeCRC == FLASH_CRC_SECTORS)
+      {
+        /* Clear sectors list */
+        FLASH->CRCCR2 |= FLASH_CRCCR_CLEAN_SECT;
+
+        /* Add CRC sectors */
+        for(sector_index = pCRCInit->Sector; sector_index < (pCRCInit->NbSectors + pCRCInit->Sector); sector_index++)
+        {
+          FLASH_CRC_AddSector(sector_index, FLASH_BANK_2);
+        }
+      }
+      else if (pCRCInit->TypeCRC == FLASH_CRC_BANK)
+      {
+        /* Enable Bank 2 CRC select bit */
+        FLASH->CRCCR2 |= FLASH_CRCCR_ALL_BANK;
+      }
+      else
+      {
+        /* Select CRC start and end addresses */
+        FLASH_CRC_SelectAddress(pCRCInit->CRCStartAddr, pCRCInit->CRCEndAddr, FLASH_BANK_2);
+      }
+
+      /* Start the CRC calculation */
+      FLASH->CRCCR2 |= FLASH_CRCCR_START_CRC;
+
+      /* Wait on CRC busy flag */
+      status = FLASH_CRC_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
+
+      /* Return CRC result */
+      (*CRC_Result) = FLASH->CRCDATA;
+
+      /* Disable CRC feature */
+      FLASH->CR2 &= (~FLASH_CR_CRC_EN);
+
+      /* Clear CRC flags */
+      __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_CRCEND_BANK2 | FLASH_FLAG_CRCRDERR_BANK2);
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @addtogroup FLASHEx_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Mass erase of FLASH memory
+  * @param  VoltageRange The device program/erase parallelism.
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_VOLTAGE_RANGE_1 : Flash program/erase by 8 bits
+  *            @arg FLASH_VOLTAGE_RANGE_2 : Flash program/erase by 16 bits
+  *            @arg FLASH_VOLTAGE_RANGE_3 : Flash program/erase by 32 bits
+  *            @arg FLASH_VOLTAGE_RANGE_4 : Flash program/erase by 64 bits
+  *
+  * @param  Banks Banks to be erased
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: Bank1 to be erased
+  *            @arg FLASH_BANK_2: Bank2 to be erased
+  *            @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
+  *
+  * @retval HAL Status
+  */
+static void FLASH_MassErase(uint32_t VoltageRange, uint32_t Banks)
+{
+  /* Check the parameters */
+#if defined (FLASH_CR_PSIZE)
+  assert_param(IS_VOLTAGERANGE(VoltageRange));
+#else
+  UNUSED(VoltageRange);
+#endif /* FLASH_CR_PSIZE */
+  assert_param(IS_FLASH_BANK(Banks));
+
+  /* Flash Mass Erase */
+  if((Banks & FLASH_BANK_BOTH) == FLASH_BANK_BOTH)
+  {
+#if defined (FLASH_CR_PSIZE)
+    /* Reset Program/erase VoltageRange for Bank1 and Bank2 */
+    FLASH->CR1 &= (~FLASH_CR_PSIZE);
+    FLASH->CR2 &= (~FLASH_CR_PSIZE);
+
+    /* Set voltage range */
+    FLASH->CR1 |= VoltageRange;
+    FLASH->CR2 |= VoltageRange;
+#endif /* FLASH_CR_PSIZE */
+
+    /* Set Mass Erase Bit */
+    FLASH->OPTCR |= FLASH_OPTCR_MER;
+  }
+  else
+  {
+    /* Proceed to erase Flash Bank  */
+    if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
+    {
+#if defined (FLASH_CR_PSIZE)
+      /* Set Program/erase VoltageRange for Bank1 */
+      FLASH->CR1 &= (~FLASH_CR_PSIZE);
+      FLASH->CR1 |=  VoltageRange;
+#endif /* FLASH_CR_PSIZE */
+
+      /* Erase Bank1 */
+      FLASH->CR1 |= (FLASH_CR_BER | FLASH_CR_START);
+    }
+    if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
+    {
+#if defined (FLASH_CR_PSIZE)
+      /* Set Program/erase VoltageRange for Bank2 */
+      FLASH->CR2 &= (~FLASH_CR_PSIZE);
+      FLASH->CR2 |= VoltageRange;
+#endif /* FLASH_CR_PSIZE */
+
+      /* Erase Bank2 */
+      FLASH->CR2 |= (FLASH_CR_BER | FLASH_CR_START);
+    }
+  }
+}
+
+/**
+  * @brief  Erase the specified FLASH memory sector
+  * @param  Sector FLASH sector to erase
+  *          This parameter can be a value of @ref FLASH_Sectors
+  * @param  Banks Banks to be erased
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: Bank1 to be erased
+  *            @arg FLASH_BANK_2: Bank2 to be erased
+  *            @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
+  * @param  VoltageRange The device program/erase parallelism.
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_VOLTAGE_RANGE_1 : Flash program/erase by 8 bits
+  *            @arg FLASH_VOLTAGE_RANGE_2 : Flash program/erase by 16 bits
+  *            @arg FLASH_VOLTAGE_RANGE_3 : Flash program/erase by 32 bits
+  *            @arg FLASH_VOLTAGE_RANGE_4 : Flash program/erase by 64 bits
+  *
+  * @retval None
+  */
+void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange)
+{
+  assert_param(IS_FLASH_SECTOR(Sector));
+  assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks));
+#if defined (FLASH_CR_PSIZE)
+  assert_param(IS_VOLTAGERANGE(VoltageRange));
+#else
+  UNUSED(VoltageRange);
+#endif /* FLASH_CR_PSIZE */
+
+  if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
+  {
+#if defined (FLASH_CR_PSIZE)
+    /* Reset Program/erase VoltageRange and Sector Number for Bank1 */
+    FLASH->CR1 &= ~(FLASH_CR_PSIZE | FLASH_CR_SNB);
+
+    FLASH->CR1 |= (FLASH_CR_SER | VoltageRange | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START);
+#else
+    /* Reset Sector Number for Bank1 */
+    FLASH->CR1 &= ~(FLASH_CR_SNB);
+
+    FLASH->CR1 |= (FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START);
+#endif /* FLASH_CR_PSIZE */
+  }
+
+  if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
+  {
+#if defined (FLASH_CR_PSIZE)
+    /* Reset Program/erase VoltageRange and Sector Number for Bank2 */
+    FLASH->CR2 &= ~(FLASH_CR_PSIZE | FLASH_CR_SNB);
+
+    FLASH->CR2 |= (FLASH_CR_SER | VoltageRange  | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START);
+#else
+    /* Reset Sector Number for Bank2 */
+    FLASH->CR2 &= ~(FLASH_CR_SNB);
+
+    FLASH->CR2 |= (FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START);
+#endif /* FLASH_CR_PSIZE */
+  }
+}
+
+/**
+  * @brief  Enable the write protection of the desired bank1 or bank 2 sectors
+  * @param  WRPSector specifies the sector(s) to be write protected.
+  *          This parameter can be one of the following values:
+  *            @arg WRPSector:  A combination of OB_WRP_SECTOR_0 to OB_WRP_SECTOR_7 or OB_WRP_SECTOR_All
+  *
+  * @param  Banks the specific bank to apply WRP sectors
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: enable WRP on specified bank1 sectors
+  *            @arg FLASH_BANK_2: enable WRP on specified bank2 sectors
+  *            @arg FLASH_BANK_BOTH: enable WRP on both bank1 and bank2 specified sectors
+  *
+  * @retval HAL FLASH State
+  */
+static void FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
+{
+  /* Check the parameters */
+  assert_param(IS_OB_WRP_SECTOR(WRPSector));
+  assert_param(IS_FLASH_BANK(Banks));
+
+  if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
+  {
+    /* Enable Write Protection for bank 1 */
+    FLASH->WPSN_PRG1 &= (~(WRPSector & FLASH_WPSN_WRPSN));
+  }
+
+  if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
+  {
+    /* Enable Write Protection for bank 2 */
+    FLASH->WPSN_PRG2 &= (~(WRPSector & FLASH_WPSN_WRPSN));
+  }
+}
+
+/**
+  * @brief  Disable the write protection of the desired bank1 or bank 2 sectors
+  * @param  WRPSector specifies the sector(s) to disable write protection.
+  *          This parameter can be one of the following values:
+  *            @arg WRPSector:  A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_All
+  *
+  * @param  Banks the specific bank to apply WRP sectors
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: disable WRP on specified bank1 sectors
+  *            @arg FLASH_BANK_2: disable WRP on specified bank2 sectors
+  *            @arg FLASH_BANK_BOTH: disable WRP on both bank1 and bank2 specified sectors
+  *
+  * @retval HAL FLASH State
+  */
+static void FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)
+{
+  /* Check the parameters */
+  assert_param(IS_OB_WRP_SECTOR(WRPSector));
+  assert_param(IS_FLASH_BANK(Banks));
+
+  if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
+  {
+    /* Disable Write Protection for bank 1 */
+    FLASH->WPSN_PRG1 |= (WRPSector & FLASH_WPSN_WRPSN);
+  }
+
+  if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
+  {
+    /* Disable Write Protection for bank 2 */
+    FLASH->WPSN_PRG2 |= (WRPSector & FLASH_WPSN_WRPSN);
+  }
+}
+
+/**
+  * @brief  Get the write protection of the given bank 1 or bank 2 sectors
+  * @param  WRPState gives the write protection state on the given bank.
+  *          This parameter can be one of the following values:
+  *          @arg WRPState: OB_WRPSTATE_DISABLE or OB_WRPSTATE_ENABLE
+
+  * @param  WRPSector gives the write protected sector(s) on the given bank .
+  *          This parameter can be one of the following values:
+  *          @arg WRPSector: A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_All
+  *
+  * @param  Bank the specific bank to apply WRP sectors
+  *          This parameter can be exclusively one of the following values:
+  *            @arg FLASH_BANK_1: Get bank1 WRP sectors
+  *            @arg FLASH_BANK_2: Get bank2 WRP sectors
+  *            @arg FLASH_BANK_BOTH: note allowed in this functions
+  *
+  * @retval HAL FLASH State
+  */
+static void FLASH_OB_GetWRP(uint32_t *WRPState, uint32_t *WRPSector, uint32_t Bank)
+{
+  uint32_t regvalue = 0U;
+
+  if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_1)
+  {
+    regvalue = FLASH->WPSN_CUR1;
+  }
+
+  if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_2)
+  {
+    regvalue = FLASH->WPSN_CUR2;
+  }
+
+  (*WRPSector) = (~regvalue) & FLASH_WPSN_WRPSN;
+
+  if(*WRPSector == 0U)
+  {
+    (*WRPState) = OB_WRPSTATE_DISABLE;
+  }
+  else
+  {
+    (*WRPState) = OB_WRPSTATE_ENABLE;
+  }
+}
+
+/**
+  * @brief  Set the read protection level.
+  *
+  * @note   To configure the RDP level, the option lock bit OPTLOCK must be
+  *         cleared with the call of the HAL_FLASH_OB_Unlock() function.
+  * @note   To validate the RDP level, the option bytes must be reloaded
+  *         through the call of the HAL_FLASH_OB_Launch() function.
+  * @note   !!! Warning : When enabling OB_RDP level 2 it's no more possible
+  *         to go back to level 1 or 0 !!!
+  *
+  * @param  RDPLevel specifies the read protection level.
+  *         This parameter can be one of the following values:
+  *            @arg OB_RDP_LEVEL_0: No protection
+  *            @arg OB_RDP_LEVEL_1: Read protection of the memory
+  *            @arg OB_RDP_LEVEL_2: Full chip protection
+  *
+  * @retval HAL status
+  */
+static void FLASH_OB_RDPConfig(uint32_t RDPLevel)
+{
+  /* Check the parameters */
+  assert_param(IS_OB_RDP_LEVEL(RDPLevel));
+
+  /* Configure the RDP level in the option bytes register */
+  MODIFY_REG(FLASH->OPTSR_PRG, FLASH_OPTSR_RDP, RDPLevel);
+}
+
+/**
+  * @brief  Get the read protection level.
+  * @retval RDPLevel specifies the read protection level.
+  *         This return value can be one of the following values:
+  *            @arg OB_RDP_LEVEL_0: No protection
+  *            @arg OB_RDP_LEVEL_1: Read protection of the memory
+  *            @arg OB_RDP_LEVEL_2: Full chip protection
+  */
+static uint32_t FLASH_OB_GetRDP(void)
+{
+  uint32_t rdp_level = READ_BIT(FLASH->OPTSR_CUR, FLASH_OPTSR_RDP);
+  
+  if ((rdp_level != OB_RDP_LEVEL_0) && (rdp_level != OB_RDP_LEVEL_2))
+  {
+    return (OB_RDP_LEVEL_1);
+  }
+  else
+  {
+    return rdp_level;
+  }
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Program the FLASH User Option Byte.
+  *
+  * @note   To configure the user option bytes, the option lock bit OPTLOCK must
+  *         be cleared with the call of the HAL_FLASH_OB_Unlock() function.
+  *
+  * @note   To validate the user option bytes, the option bytes must be reloaded
+  *         through the call of the HAL_FLASH_OB_Launch() function.
+  *
+  * @param  UserType The FLASH User Option Bytes to be modified :
+  *                   a combination of @ref FLASHEx_OB_USER_Type
+  *
+  * @param  UserConfig The FLASH User Option Bytes values:
+  *         IWDG1_SW(Bit4), IWDG2_SW(Bit 5), nRST_STOP_D1(Bit 6), nRST_STDY_D1(Bit 7),
+  *         FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]),
+  *         SECURITY(Bit 21), BCM4(Bit 22), BCM7(Bit 23), nRST_STOP_D2(Bit 24),
+  *         nRST_STDY_D2(Bit 25), IO_HSLV (Bit 29) and SWAP_BANK_OPT(Bit 31).
+  *
+  * @retval HAL status
+  */
+#else
+/**
+  * @brief  Program the FLASH User Option Byte.
+  *
+  * @note   To configure the user option bytes, the option lock bit OPTLOCK must
+  *         be cleared with the call of the HAL_FLASH_OB_Unlock() function.
+  *
+  * @note   To validate the user option bytes, the option bytes must be reloaded
+  *         through the call of the HAL_FLASH_OB_Launch() function.
+  *
+  * @param  UserType The FLASH User Option Bytes to be modified :
+  *                   a combination of @arg FLASHEx_OB_USER_Type
+  *
+  * @param  UserConfig The FLASH User Option Bytes values:
+  *         IWDG_SW(Bit4), nRST_STOP_D1(Bit 6), nRST_STDY_D1(Bit 7),
+  *         FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]),
+  *         SECURITY(Bit 21), IO_HSLV (Bit 29) and SWAP_BANK_OPT(Bit 31).
+  *
+  * @retval HAL status
+  */
+#endif /*DUAL_CORE*/
+static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig)
+{
+  uint32_t optr_reg_val = 0;
+  uint32_t optr_reg_mask = 0;
+
+  /* Check the parameters */
+  assert_param(IS_OB_USER_TYPE(UserType));
+
+  if((UserType & OB_USER_IWDG1_SW) != 0U)
+  {
+    /* IWDG_HW option byte should be modified */
+    assert_param(IS_OB_IWDG1_SOURCE(UserConfig & FLASH_OPTSR_IWDG1_SW));
+
+    /* Set value and mask for IWDG_HW option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_IWDG1_SW);
+    optr_reg_mask |= FLASH_OPTSR_IWDG1_SW;
+  }
+#if defined(DUAL_CORE)
+  if((UserType & OB_USER_IWDG2_SW) != 0U)
+  {
+    /* IWDG2_SW option byte should be modified */
+    assert_param(IS_OB_IWDG2_SOURCE(UserConfig & FLASH_OPTSR_IWDG2_SW));
+
+    /* Set value and mask for IWDG2_SW option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_IWDG2_SW);
+    optr_reg_mask |= FLASH_OPTSR_IWDG2_SW;
+  }
+#endif /*DUAL_CORE*/
+  if((UserType & OB_USER_NRST_STOP_D1) != 0U)
+  {
+    /* NRST_STOP option byte should be modified */
+    assert_param(IS_OB_STOP_D1_RESET(UserConfig & FLASH_OPTSR_NRST_STOP_D1));
+
+    /* Set value and mask for NRST_STOP option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STOP_D1);
+    optr_reg_mask |= FLASH_OPTSR_NRST_STOP_D1;
+  }
+
+  if((UserType & OB_USER_NRST_STDBY_D1) != 0U)
+  {
+    /* NRST_STDBY option byte should be modified */
+    assert_param(IS_OB_STDBY_D1_RESET(UserConfig & FLASH_OPTSR_NRST_STBY_D1));
+
+    /* Set value and mask for NRST_STDBY option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STBY_D1);
+    optr_reg_mask |= FLASH_OPTSR_NRST_STBY_D1;
+  }
+
+  if((UserType & OB_USER_IWDG_STOP) != 0U)
+  {
+    /* IWDG_STOP option byte should be modified */
+    assert_param(IS_OB_USER_IWDG_STOP(UserConfig & FLASH_OPTSR_FZ_IWDG_STOP));
+
+    /* Set value and mask for IWDG_STOP option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_FZ_IWDG_STOP);
+    optr_reg_mask |= FLASH_OPTSR_FZ_IWDG_STOP;
+  }
+
+  if((UserType & OB_USER_IWDG_STDBY) != 0U)
+  {
+    /* IWDG_STDBY option byte should be modified */
+    assert_param(IS_OB_USER_IWDG_STDBY(UserConfig & FLASH_OPTSR_FZ_IWDG_SDBY));
+
+    /* Set value and mask for IWDG_STDBY option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_FZ_IWDG_SDBY);
+    optr_reg_mask |= FLASH_OPTSR_FZ_IWDG_SDBY;
+  }
+
+  if((UserType & OB_USER_ST_RAM_SIZE) != 0U)
+  {
+    /* ST_RAM_SIZE option byte should be modified */
+    assert_param(IS_OB_USER_ST_RAM_SIZE(UserConfig & FLASH_OPTSR_ST_RAM_SIZE));
+
+    /* Set value and mask for ST_RAM_SIZE option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_ST_RAM_SIZE);
+    optr_reg_mask |= FLASH_OPTSR_ST_RAM_SIZE;
+  }
+
+  if((UserType & OB_USER_SECURITY) != 0U)
+  {
+    /* SECURITY option byte should be modified */
+    assert_param(IS_OB_USER_SECURITY(UserConfig & FLASH_OPTSR_SECURITY));
+
+    /* Set value and mask for SECURITY option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_SECURITY);
+    optr_reg_mask |= FLASH_OPTSR_SECURITY;
+  }
+
+#if defined(DUAL_CORE)
+  if((UserType & OB_USER_BCM4) != 0U)
+  {
+    /* BCM4 option byte should be modified */
+    assert_param(IS_OB_USER_BCM4(UserConfig & FLASH_OPTSR_BCM4));
+
+    /* Set value and mask for BCM4 option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_BCM4);
+    optr_reg_mask |= FLASH_OPTSR_BCM4;
+  }
+
+  if((UserType & OB_USER_BCM7) != 0U)
+  {
+    /* BCM7 option byte should be modified */
+    assert_param(IS_OB_USER_BCM7(UserConfig & FLASH_OPTSR_BCM7));
+
+    /* Set value and mask for BCM7 option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_BCM7);
+    optr_reg_mask |= FLASH_OPTSR_BCM7;
+  }
+
+  if((UserType & OB_USER_NRST_STOP_D2) != 0U)
+  {
+    /* NRST_STOP option byte should be modified */
+    assert_param(IS_OB_STOP_D2_RESET(UserConfig & FLASH_OPTSR_NRST_STOP_D2));
+
+    /* Set value and mask for NRST_STOP option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STOP_D2);
+    optr_reg_mask |= FLASH_OPTSR_NRST_STOP_D2;
+  }
+
+  if((UserType & OB_USER_NRST_STDBY_D2) != 0U)
+  {
+    /* NRST_STDBY option byte should be modified */
+    assert_param(IS_OB_STDBY_D2_RESET(UserConfig & FLASH_OPTSR_NRST_STBY_D2));
+
+    /* Set value and mask for NRST_STDBY option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STBY_D2);
+    optr_reg_mask |= FLASH_OPTSR_NRST_STBY_D2;
+  }
+#endif /* DUAL_CORE */
+  if((UserType & OB_USER_SWAP_BANK) != 0U)
+  {
+    /* SWAP_BANK_OPT option byte should be modified */
+    assert_param(IS_OB_USER_SWAP_BANK(UserConfig & FLASH_OPTSR_SWAP_BANK_OPT));
+
+    /* Set value and mask for SWAP_BANK_OPT option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_SWAP_BANK_OPT);
+    optr_reg_mask |= FLASH_OPTSR_SWAP_BANK_OPT;
+  }
+
+  if((UserType & OB_USER_IOHSLV) != 0U)
+  {
+    /* IOHSLV_OPT option byte should be modified */
+    assert_param(IS_OB_USER_IOHSLV(UserConfig & FLASH_OPTSR_IO_HSLV));
+
+    /* Set value and mask for IOHSLV_OPT option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_IO_HSLV);
+    optr_reg_mask |= FLASH_OPTSR_IO_HSLV;
+  }
+
+#if defined (FLASH_OPTSR_VDDMMC_HSLV)
+  if((UserType & OB_USER_VDDMMC_HSLV) != 0U)
+  {
+    /* VDDMMC_HSLV option byte should be modified */
+    assert_param(IS_OB_USER_VDDMMC_HSLV(UserConfig & FLASH_OPTSR_VDDMMC_HSLV));
+
+    /* Set value and mask for VDDMMC_HSLV option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_VDDMMC_HSLV);
+    optr_reg_mask |= FLASH_OPTSR_VDDMMC_HSLV;
+  }
+#endif /* FLASH_OPTSR_VDDMMC_HSLV */
+
+  /* Configure the option bytes register */
+  MODIFY_REG(FLASH->OPTSR_PRG, optr_reg_mask, optr_reg_val);
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Return the FLASH User Option Byte value.
+  * @retval The FLASH User Option Bytes values
+  *         IWDG1_SW(Bit4), IWDG2_SW(Bit 5), nRST_STOP_D1(Bit 6), nRST_STDY_D1(Bit 7),
+  *         FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]),
+  *         SECURITY(Bit 21), BCM4(Bit 22), BCM7(Bit 23), nRST_STOP_D2(Bit 24),
+  *         nRST_STDY_D2(Bit 25), IO_HSLV (Bit 29) and SWAP_BANK_OPT(Bit 31).
+  */
+#else
+/**
+  * @brief  Return the FLASH User Option Byte value.
+  * @retval The FLASH User Option Bytes values
+  *         IWDG_SW(Bit4), nRST_STOP_D1(Bit 6), nRST_STDY_D1(Bit 7),
+  *         FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]),
+  *         SECURITY(Bit 21), IO_HSLV (Bit 29) and SWAP_BANK_OPT(Bit 31).
+  */
+#endif /*DUAL_CORE*/
+static uint32_t FLASH_OB_GetUser(void)
+{
+  uint32_t userConfig = READ_REG(FLASH->OPTSR_CUR);
+  userConfig &= (~(FLASH_OPTSR_BOR_LEV | FLASH_OPTSR_RDP));
+
+  return userConfig;
+}
+
+/**
+  * @brief  Configure the Proprietary code readout protection of the desired addresses
+  *
+  * @note   To configure the PCROP options, the option lock bit OPTLOCK must be
+  *         cleared with the call of the HAL_FLASH_OB_Unlock() function.
+  * @note   To validate the PCROP options, the option bytes must be reloaded
+  *         through the call of the HAL_FLASH_OB_Launch() function.
+  *
+  * @param  PCROPConfig specifies if the PCROP area for the given Bank shall be erased or not
+  *         when RDP level decreased from Level 1 to Level 0, or after a bank erase with protection removal
+  *         This parameter must be a value of @arg FLASHEx_OB_PCROP_RDP enumeration
+  *
+  * @param  PCROPStartAddr specifies the start address of the Proprietary code readout protection
+  *          This parameter can be an address between begin and end of the bank
+  *
+  * @param  PCROPEndAddr specifies the end address of the Proprietary code readout protection
+  *          This parameter can be an address between PCROPStartAddr and end of the bank
+  *
+  * @param  Banks the specific bank to apply PCROP protection
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: PCROP on specified bank1 area
+  *            @arg FLASH_BANK_2: PCROP on specified bank2 area
+  *            @arg FLASH_BANK_BOTH: PCROP on specified bank1 and bank2 area (same config will be applied on both banks)
+  *
+  * @retval None
+  */
+static void FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr, uint32_t Banks)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_BANK(Banks));
+  assert_param(IS_OB_PCROP_RDP(PCROPConfig));
+
+  if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
+  {
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(PCROPStartAddr));
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(PCROPEndAddr));
+
+    /* Configure the Proprietary code readout protection */
+    FLASH->PRAR_PRG1 = ((PCROPStartAddr - FLASH_BANK1_BASE) >> 8)                                 | \
+                       (((PCROPEndAddr - FLASH_BANK1_BASE) >> 8) << FLASH_PRAR_PROT_AREA_END_Pos) | \
+                       PCROPConfig;
+  }
+
+  if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
+  {
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(PCROPStartAddr));
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(PCROPEndAddr));
+
+    /* Configure the Proprietary code readout protection */
+    FLASH->PRAR_PRG2 = ((PCROPStartAddr - FLASH_BANK2_BASE) >> 8)                                 | \
+                       (((PCROPEndAddr - FLASH_BANK2_BASE) >> 8) << FLASH_PRAR_PROT_AREA_END_Pos) | \
+                       PCROPConfig;
+  }
+}
+
+/**
+  * @brief  Get the Proprietary code readout protection configuration on a given Bank
+  *
+  * @param  PCROPConfig indicates if the PCROP area for the given Bank shall be erased or not
+  *         when RDP level decreased from Level 1 to Level 0 or after a bank erase with protection removal
+  *
+  * @param  PCROPStartAddr gives the start address of the Proprietary code readout protection of the bank
+  *
+  * @param  PCROPEndAddr gives the end address of the Proprietary code readout protection of the bank
+  *
+  * @param  Bank the specific bank to apply PCROP protection
+  *          This parameter can be exclusively one of the following values:
+  *            @arg FLASH_BANK_1: PCROP on specified bank1 area
+  *            @arg FLASH_BANK_2: PCROP on specified bank2 area
+  *            @arg FLASH_BANK_BOTH: is  not allowed here
+  *
+  * @retval None
+  */
+static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROPStartAddr, uint32_t *PCROPEndAddr, uint32_t Bank)
+{
+  uint32_t regvalue = 0;
+  uint32_t bankBase = 0;
+
+  if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_1)
+  {
+    regvalue = FLASH->PRAR_CUR1;
+    bankBase = FLASH_BANK1_BASE;
+  }
+
+  if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_2)
+  {
+    regvalue = FLASH->PRAR_CUR2;
+    bankBase = FLASH_BANK2_BASE;
+  }
+
+  (*PCROPConfig) =  (regvalue & FLASH_PRAR_DMEP);
+
+  (*PCROPStartAddr) = ((regvalue & FLASH_PRAR_PROT_AREA_START) << 8) + bankBase;
+  (*PCROPEndAddr) = (regvalue & FLASH_PRAR_PROT_AREA_END) >> FLASH_PRAR_PROT_AREA_END_Pos;
+  (*PCROPEndAddr) = ((*PCROPEndAddr) << 8) + bankBase;
+}
+
+/**
+  * @brief  Set the BOR Level.
+  * @param  Level specifies the Option Bytes BOR Reset Level.
+  *          This parameter can be one of the following values:
+  *            @arg OB_BOR_LEVEL0: Reset level threshold is set to 1.6V
+  *            @arg OB_BOR_LEVEL1: Reset level threshold is set to 2.1V
+  *            @arg OB_BOR_LEVEL2: Reset level threshold is set to 2.4V
+  *            @arg OB_BOR_LEVEL3: Reset level threshold is set to 2.7V
+  * @retval None
+  */
+static void FLASH_OB_BOR_LevelConfig(uint32_t Level)
+{
+  assert_param(IS_OB_BOR_LEVEL(Level));
+
+  /* Configure BOR_LEV option byte */
+  MODIFY_REG(FLASH->OPTSR_PRG, FLASH_OPTSR_BOR_LEV, Level);
+}
+
+/**
+  * @brief  Get the BOR Level.
+  * @retval The Option Bytes BOR Reset Level.
+  *            This parameter can be one of the following values:
+  *            @arg OB_BOR_LEVEL0: Reset level threshold is set to 1.6V
+  *            @arg OB_BOR_LEVEL1: Reset level threshold is set to 2.1V
+  *            @arg OB_BOR_LEVEL2: Reset level threshold is set to 2.4V
+  *            @arg OB_BOR_LEVEL3: Reset level threshold is set to 2.7V
+  */
+static uint32_t FLASH_OB_GetBOR(void)
+{
+  return (FLASH->OPTSR_CUR & FLASH_OPTSR_BOR_LEV);
+}
+
+/**
+  * @brief  Set Boot address
+  * @param  BootOption Boot address option byte to be programmed,
+  *                     This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION
+                        (OB_BOOT_ADD0, OB_BOOT_ADD1 or OB_BOOT_ADD_BOTH)
+  *
+  * @param  BootAddress0 Specifies the Boot Address 0
+  * @param  BootAddress1 Specifies the Boot Address 1
+  * @retval HAL Status
+  */
+static void FLASH_OB_BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1)
+{
+  /* Check the parameters */
+  assert_param(IS_OB_BOOT_ADD_OPTION(BootOption));
+
+  if((BootOption & OB_BOOT_ADD0) == OB_BOOT_ADD0)
+  {
+    /* Check the parameters */
+    assert_param(IS_BOOT_ADDRESS(BootAddress0));
+
+    /* Configure CM7 BOOT ADD0 */
+#if defined(DUAL_CORE)
+    MODIFY_REG(FLASH->BOOT7_PRG, FLASH_BOOT7_BCM7_ADD0, (BootAddress0 >> 16));
+#else /* Single Core*/
+    MODIFY_REG(FLASH->BOOT_PRG, FLASH_BOOT_ADD0, (BootAddress0 >> 16));
+#endif /* DUAL_CORE */
+  }
+
+  if((BootOption & OB_BOOT_ADD1) == OB_BOOT_ADD1)
+  {
+    /* Check the parameters */
+    assert_param(IS_BOOT_ADDRESS(BootAddress1));
+
+    /* Configure CM7 BOOT ADD1 */
+#if defined(DUAL_CORE)
+    MODIFY_REG(FLASH->BOOT7_PRG, FLASH_BOOT7_BCM7_ADD1, BootAddress1);
+#else /* Single Core*/
+    MODIFY_REG(FLASH->BOOT_PRG, FLASH_BOOT_ADD1, BootAddress1);
+#endif /* DUAL_CORE */
+  }
+}
+
+/**
+  * @brief  Get Boot address
+  * @param  BootAddress0 Specifies the Boot Address 0.
+  * @param  BootAddress1 Specifies the Boot Address 1.
+  * @retval HAL Status
+  */
+static void FLASH_OB_GetBootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1)
+{
+  uint32_t regvalue;
+
+#if defined(DUAL_CORE)
+  regvalue = FLASH->BOOT7_CUR;
+
+  (*BootAddress0) = (regvalue & FLASH_BOOT7_BCM7_ADD0) << 16;
+  (*BootAddress1) = (regvalue & FLASH_BOOT7_BCM7_ADD1);
+#else /* Single Core */
+  regvalue = FLASH->BOOT_CUR;
+
+  (*BootAddress0) = (regvalue & FLASH_BOOT_ADD0) << 16;
+  (*BootAddress1) = (regvalue & FLASH_BOOT_ADD1);
+#endif /* DUAL_CORE */
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Set CM4 Boot address
+  * @param  BootOption Boot address option byte to be programmed,
+  *                     This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION
+                        (OB_BOOT_ADD0, OB_BOOT_ADD1 or OB_BOOT_ADD_BOTH)
+  *
+  * @param  BootAddress0 Specifies the CM4 Boot Address 0.
+  * @param  BootAddress1 Specifies the CM4 Boot Address 1.
+  * @retval HAL Status
+  */
+static void FLASH_OB_CM4BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1)
+{
+  /* Check the parameters */
+  assert_param(IS_OB_BOOT_ADD_OPTION(BootOption));
+
+  if((BootOption & OB_BOOT_ADD0) == OB_BOOT_ADD0)
+  {
+    /* Check the parameters */
+    assert_param(IS_BOOT_ADDRESS(BootAddress0));
+
+    /* Configure CM4 BOOT ADD0 */
+    MODIFY_REG(FLASH->BOOT4_PRG, FLASH_BOOT4_BCM4_ADD0, (BootAddress0 >> 16));
+
+  }
+
+  if((BootOption & OB_BOOT_ADD1) == OB_BOOT_ADD1)
+  {
+    /* Check the parameters */
+    assert_param(IS_BOOT_ADDRESS(BootAddress1));
+
+    /* Configure CM4 BOOT ADD1 */
+    MODIFY_REG(FLASH->BOOT4_PRG, FLASH_BOOT4_BCM4_ADD1, BootAddress1);
+  }
+}
+
+/**
+  * @brief  Get CM4 Boot address
+  * @param  BootAddress0 Specifies the CM4 Boot Address 0.
+  * @param  BootAddress1 Specifies the CM4 Boot Address 1.
+  * @retval HAL Status
+  */
+static void FLASH_OB_GetCM4BootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1)
+{
+  uint32_t regvalue;
+
+  regvalue = FLASH->BOOT4_CUR;
+
+  (*BootAddress0) = (regvalue & FLASH_BOOT4_BCM4_ADD0) << 16;
+  (*BootAddress1) = (regvalue & FLASH_BOOT4_BCM4_ADD1);
+}
+#endif /*DUAL_CORE*/
+
+/**
+  * @brief  Set secure area configuration
+  * @param  SecureAreaConfig specify if the secure area will be deleted or not
+  *         when RDP level decreased from Level 1 to Level 0 or during a mass erase.
+  *
+  * @param  SecureAreaStartAddr Specifies the secure area start address
+  * @param  SecureAreaEndAddr Specifies the secure area end address
+  * @param  Banks the specific bank to apply Security protection
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: Secure area on specified bank1 area
+  *            @arg FLASH_BANK_2: Secure area on specified bank2 area
+  *            @arg FLASH_BANK_BOTH: Secure area on specified bank1 and bank2 area (same config will be applied on both banks)
+  * @retval None
+  */
+static void FLASH_OB_SecureAreaConfig(uint32_t SecureAreaConfig, uint32_t SecureAreaStartAddr, uint32_t SecureAreaEndAddr, uint32_t Banks)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_BANK(Banks));
+  assert_param(IS_OB_SECURE_RDP(SecureAreaConfig));
+
+  if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
+  {
+    /* Check the parameters */
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(SecureAreaStartAddr));
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(SecureAreaEndAddr));
+
+    /* Configure the secure area */
+    FLASH->SCAR_PRG1 = ((SecureAreaStartAddr - FLASH_BANK1_BASE) >> 8)                                | \
+                       (((SecureAreaEndAddr - FLASH_BANK1_BASE) >> 8) << FLASH_SCAR_SEC_AREA_END_Pos) | \
+                       (SecureAreaConfig & FLASH_SCAR_DMES);
+  }
+
+  if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
+  {
+    /* Check the parameters */
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(SecureAreaStartAddr));
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(SecureAreaEndAddr));
+
+    /* Configure the secure area */
+    FLASH->SCAR_PRG2 = ((SecureAreaStartAddr - FLASH_BANK2_BASE) >> 8)                                | \
+                       (((SecureAreaEndAddr - FLASH_BANK2_BASE) >> 8) << FLASH_SCAR_SEC_AREA_END_Pos) | \
+                       (SecureAreaConfig & FLASH_SCAR_DMES);
+  }
+}
+
+/**
+  * @brief  Get secure area configuration
+  * @param  SecureAreaConfig indicates if the secure area will be deleted or not
+  *         when RDP level decreased from Level 1 to Level 0 or during a mass erase.
+  * @param  SecureAreaStartAddr gives the secure area start address
+  * @param  SecureAreaEndAddr gives the secure area end address
+  * @param  Bank Specifies the Bank
+  * @retval None
+  */
+static void FLASH_OB_GetSecureArea(uint32_t *SecureAreaConfig, uint32_t *SecureAreaStartAddr, uint32_t *SecureAreaEndAddr, uint32_t Bank)
+{
+  uint32_t regvalue = 0;
+  uint32_t bankBase = 0;
+
+  /* Check Bank parameter value */
+  if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_1)
+  {
+    regvalue = FLASH->SCAR_CUR1;
+    bankBase = FLASH_BANK1_BASE;
+  }
+
+  if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_2)
+  {
+    regvalue = FLASH->SCAR_CUR2;
+    bankBase = FLASH_BANK2_BASE;
+  }
+
+  /* Get the secure area settings */
+  (*SecureAreaConfig) = (regvalue & FLASH_SCAR_DMES);
+  (*SecureAreaStartAddr) = ((regvalue & FLASH_SCAR_SEC_AREA_START) << 8) + bankBase;
+  (*SecureAreaEndAddr) = (regvalue & FLASH_SCAR_SEC_AREA_END) >> FLASH_SCAR_SEC_AREA_END_Pos;
+  (*SecureAreaEndAddr) = ((*SecureAreaEndAddr) << 8) + bankBase;
+}
+
+/**
+  * @brief  Add a CRC sector to the list of sectors on which the CRC will be calculated
+  * @param  Sector Specifies the CRC sector number
+  * @param  Bank Specifies the Bank
+  * @retval None
+  */
+static void FLASH_CRC_AddSector(uint32_t Sector, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_SECTOR(Sector));
+
+  if (Bank == FLASH_BANK_1)
+  {
+    /* Clear CRC sector */
+    FLASH->CRCCR1 &= (~FLASH_CRCCR_CRC_SECT);
+
+    /* Select CRC Sector and activate ADD_SECT bit */
+    FLASH->CRCCR1 |= Sector | FLASH_CRCCR_ADD_SECT;
+  }
+  else
+  {
+    /* Clear CRC sector */
+    FLASH->CRCCR2 &= (~FLASH_CRCCR_CRC_SECT);
+
+    /* Select CRC Sector and activate ADD_SECT bit */
+    FLASH->CRCCR2 |= Sector | FLASH_CRCCR_ADD_SECT;
+  }
+}
+
+/**
+  * @brief  Select CRC start and end memory addresses on which the CRC will be calculated
+  * @param  CRCStartAddr Specifies the CRC start address
+  * @param  CRCEndAddr Specifies the CRC end address
+  * @param  Bank Specifies the Bank
+  * @retval None
+  */
+static void FLASH_CRC_SelectAddress(uint32_t CRCStartAddr, uint32_t CRCEndAddr, uint32_t Bank)
+{
+  if (Bank == FLASH_BANK_1)
+  {
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(CRCStartAddr));
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(CRCEndAddr));
+
+    /* Write CRC Start and End addresses */
+    FLASH->CRCSADD1 = CRCStartAddr;
+    FLASH->CRCEADD1 = CRCEndAddr;
+  }
+  else
+  {
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(CRCStartAddr));
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(CRCEndAddr));
+
+    /* Write CRC Start and End addresses */
+    FLASH->CRCSADD2 = CRCStartAddr;
+    FLASH->CRCEADD2 = CRCEndAddr;
+  }
+}
+/**
+  * @}
+  */
+
+#if defined (FLASH_OTPBL_LOCKBL)
+/**
+  * @brief  Configure the OTP Block Lock.
+  * @param  OTP_Block specifies the OTP Block to lock.
+  *         This parameter can be a value of @ref FLASHEx_OTP_Blocks
+  * @retval None
+  */
+static void FLASH_OB_OTP_LockConfig(uint32_t OTP_Block)
+{
+  /* Check the parameters */
+  assert_param(IS_OTP_BLOCK(OTP_Block));
+
+  /* Configure the OTP Block lock in the option bytes register */
+  FLASH->OTPBL_PRG |= (OTP_Block & FLASH_OTPBL_LOCKBL);
+}
+
+/**
+  * @brief  Get the OTP Block Lock.
+  * @retval OTP_Block specifies the OTP Block to lock.
+  *         This return value can be a value of @ref FLASHEx_OTP_Blocks
+  */
+static uint32_t FLASH_OB_OTP_GetLock(void)
+{
+  return (FLASH->OTPBL_CUR);
+}
+#endif /* FLASH_OTPBL_LOCKBL */
+
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c
new file mode 100644
index 00000000..13dcc40d
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c
@@ -0,0 +1,560 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_gpio.c
+  * @author  MCD Application Team
+  * @brief   GPIO HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *
+  @verbatim
+  ==============================================================================
+                    ##### GPIO Peripheral features #####
+  ==============================================================================
+  [..]
+    (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
+        configured by software in several modes:
+        (++) Input mode
+        (++) Analog mode
+        (++) Output mode
+        (++) Alternate function mode
+        (++) External interrupt/event lines
+
+    (+) During and just after reset, the alternate functions and external interrupt
+        lines are not active and the I/O ports are configured in input floating mode.
+
+    (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
+        activated or not.
+
+    (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
+        type and the IO speed can be selected depending on the VDD value.
+
+    (+) The microcontroller IO pins are connected to onboard peripherals/modules through a
+        multiplexer that allows only one peripheral alternate function (AF) connected
+       to an IO pin at a time. In this way, there can be no conflict between peripherals
+       sharing the same IO pin.
+
+    (+) All ports have external interrupt/event capability. To use external interrupt
+        lines, the port must be configured in input mode. All available GPIO pins are
+        connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
+
+  The external interrupt/event controller consists of up to 23 edge detectors
+        (16 lines are connected to GPIO) for generating event/interrupt requests (each
+        input line can be independently configured to select the type (interrupt or event)
+        and the corresponding trigger event (rising or falling or both). Each line can
+        also be masked independently.
+
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
+
+    (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
+        (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
+        (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
+             structure.
+        (++) In case of Output or alternate function mode selection: the speed is
+             configured through "Speed" member from GPIO_InitTypeDef structure.
+        (++) In alternate mode is selection, the alternate function connected to the IO
+             is configured through "Alternate" member from GPIO_InitTypeDef structure.
+        (++) Analog mode is required when a pin is to be used as ADC channel
+             or DAC output.
+        (++) In case of external interrupt/event selection the "Mode" member from
+             GPIO_InitTypeDef structure select the type (interrupt or event) and
+             the corresponding trigger event (rising or falling or both).
+
+    (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
+        mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
+        HAL_NVIC_EnableIRQ().
+
+    (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
+
+    (#) To set/reset the level of a pin configured in output mode use
+        HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
+
+   (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
+
+
+    (#) During and just after reset, the alternate functions are not
+        active and the GPIO pins are configured in input floating mode (except JTAG
+        pins).
+
+    (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
+        (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
+        priority over the GPIO function.
+
+    (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
+        general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
+        The HSE has priority over the GPIO function.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup GPIO  GPIO
+  * @brief GPIO HAL module driver
+  * @{
+  */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines ------------------------------------------------------------*/
+/** @addtogroup GPIO_Private_Constants GPIO Private Constants
+  * @{
+  */
+#define GPIO_MODE             (0x00000003U)
+#define ANALOG_MODE           (0x00000008U)
+#define EXTI_MODE             (0x10000000U)
+#define GPIO_MODE_IT          (0x00010000U)
+#define GPIO_MODE_EVT         (0x00020000U)
+#define RISING_EDGE           (0x00100000U)
+#define FALLING_EDGE          (0x00200000U)
+#define GPIO_OUTPUT_TYPE      (0x00000010U)
+
+#if defined(DUAL_CORE)
+#define EXTI_CPU1             (0x01000000U)
+#define EXTI_CPU2             (0x02000000U)
+#endif /*DUAL_CORE*/
+#define GPIO_NUMBER           (16U)
+/**
+  * @}
+  */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
+  * @{
+  */
+
+/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+  [..]
+    This section provides functions allowing to initialize and de-initialize the GPIOs
+    to be ready for use.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
+  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral.
+  * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
+  *         the configuration information for the specified GPIO peripheral.
+  * @retval None
+  */
+void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
+{
+  uint32_t position = 0x00U;
+  uint32_t iocurrent;
+  uint32_t temp;
+  EXTI_Core_TypeDef *EXTI_CurrentCPU;
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */
+#else
+  EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */
+#endif
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
+  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
+  assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
+
+  /* Configure the port pins */
+  while (((GPIO_Init->Pin) >> position) != 0x00U)
+  {
+    /* Get current io position */
+    iocurrent = (GPIO_Init->Pin) & (1UL << position);
+
+    if (iocurrent != 0x00U)
+    {
+      /*--------------------- GPIO Mode Configuration ------------------------*/
+      /* In case of Output or Alternate function mode selection */
+      if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
+          (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+      {
+        /* Check the Speed parameter */
+        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+        /* Configure the IO Speed */
+        temp = GPIOx->OSPEEDR;
+        temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
+        temp |= (GPIO_Init->Speed << (position * 2U));
+        GPIOx->OSPEEDR = temp;
+
+        /* Configure the IO Output Type */
+        temp = GPIOx->OTYPER;
+        temp &= ~(GPIO_OTYPER_OT0 << position) ;
+        temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
+        GPIOx->OTYPER = temp;
+      }
+
+      /* Activate the Pull-up or Pull down resistor for the current IO */
+      temp = GPIOx->PUPDR;
+      temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
+      temp |= ((GPIO_Init->Pull) << (position * 2U));
+      GPIOx->PUPDR = temp;
+
+      /* In case of Alternate function mode selection */
+      if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+      {
+        /* Check the Alternate function parameters */
+        assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
+        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
+
+        /* Configure Alternate function mapped with the current IO */
+        temp = GPIOx->AFR[position >> 3U];
+        temp &= ~(0xFU << ((position & 0x07U) * 4U));
+        temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
+        GPIOx->AFR[position >> 3U] = temp;
+      }
+
+      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+      temp = GPIOx->MODER;
+      temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
+      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
+      GPIOx->MODER = temp;
+
+      /*--------------------- EXTI Mode Configuration ------------------------*/
+      /* Configure the External Interrupt or event for the current IO */
+      if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
+      {
+        /* Enable SYSCFG Clock */
+        __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+        temp = SYSCFG->EXTICR[position >> 2U];
+        temp &= ~(0x0FUL << (4U * (position & 0x03U)));
+        temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
+        SYSCFG->EXTICR[position >> 2U] = temp;
+
+        /* Clear EXTI line configuration */
+        temp = EXTI_CurrentCPU->IMR1;
+        temp &= ~(iocurrent);
+        if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
+        {
+          temp |= iocurrent;
+        }
+        EXTI_CurrentCPU->IMR1 = temp;
+
+        temp = EXTI_CurrentCPU->EMR1;
+        temp &= ~(iocurrent);
+        if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
+        {
+          temp |= iocurrent;
+        }
+        EXTI_CurrentCPU->EMR1 = temp;
+
+        /* Clear Rising Falling edge configuration */
+        temp = EXTI->RTSR1;
+        temp &= ~(iocurrent);
+        if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
+        {
+          temp |= iocurrent;
+        }
+        EXTI->RTSR1 = temp;
+
+        temp = EXTI->FTSR1;
+        temp &= ~(iocurrent);
+        if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
+        {
+          temp |= iocurrent;
+        }
+        EXTI->FTSR1 = temp;
+      }
+    }
+
+    position++;
+  }
+}
+
+/**
+  * @brief  De-initializes the GPIOx peripheral registers to their default reset values.
+  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bit to be written.
+  *          This parameter can be one of GPIO_PIN_x where x can be (0..15).
+  * @retval None
+  */
+void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
+{
+  uint32_t position = 0x00U;
+  uint32_t iocurrent;
+  uint32_t tmp;
+  EXTI_Core_TypeDef *EXTI_CurrentCPU;
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */
+#else
+  EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */
+#endif
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  /* Configure the port pins */
+  while ((GPIO_Pin >> position) != 0x00U)
+  {
+    /* Get current io position */
+    iocurrent = GPIO_Pin & (1UL << position) ;
+
+    if (iocurrent != 0x00U)
+    {
+      /*------------------------- EXTI Mode Configuration --------------------*/
+      /* Clear the External Interrupt or Event for the current IO */
+      tmp = SYSCFG->EXTICR[position >> 2U];
+      tmp &= (0x0FUL << (4U * (position & 0x03U)));
+      if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
+      {
+        /* Clear EXTI line configuration for Current CPU */
+        EXTI_CurrentCPU->IMR1 &= ~(iocurrent);
+        EXTI_CurrentCPU->EMR1 &= ~(iocurrent);
+
+        /* Clear Rising Falling edge configuration */
+        EXTI->RTSR1 &= ~(iocurrent);
+        EXTI->FTSR1 &= ~(iocurrent);
+
+        tmp = 0x0FUL << (4U * (position & 0x03U));
+        SYSCFG->EXTICR[position >> 2U] &= ~tmp;
+      }
+
+      /*------------------------- GPIO Mode Configuration --------------------*/
+      /* Configure IO in Analog Mode */
+      GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2U));
+
+      /* Configure the default Alternate Function in current IO */
+      GPIOx->AFR[position >> 3U] &= ~(0xFU << ((position & 0x07U) * 4U)) ;
+
+      /* Deactivate the Pull-up and Pull-down resistor for the current IO */
+      GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
+
+      /* Configure the default value IO Output Type */
+      GPIOx->OTYPER  &= ~(GPIO_OTYPER_OT0 << position) ;
+
+      /* Configure the default value for IO Speed */
+      GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
+    }
+
+    position++;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
+ *  @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
+ *
+@verbatim
+ ===============================================================================
+                       ##### IO operation functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Reads the specified input port pin.
+  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bit to read.
+  *         This parameter can be GPIO_PIN_x where x can be (0..15).
+  * @retval The input port pin value.
+  */
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+  GPIO_PinState bitstatus;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  if ((GPIOx->IDR & GPIO_Pin) != 0x00U)
+  {
+    bitstatus = GPIO_PIN_SET;
+  }
+  else
+  {
+    bitstatus = GPIO_PIN_RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Sets or clears the selected data port bit.
+  *
+  * @note   This function uses GPIOx_BSRR register to allow atomic read/modify
+  *         accesses. In this way, there is no risk of an IRQ occurring between
+  *         the read and the modify access.
+  *
+  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bit to be written.
+  *          This parameter can be one of GPIO_PIN_x where x can be (0..15).
+  * @param  PinState: specifies the value to be written to the selected bit.
+  *          This parameter can be one of the GPIO_PinState enum values:
+  *            @arg GPIO_PIN_RESET: to clear the port pin
+  *            @arg GPIO_PIN_SET: to set the port pin
+  * @retval None
+  */
+void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+  assert_param(IS_GPIO_PIN_ACTION(PinState));
+
+  if (PinState != GPIO_PIN_RESET)
+  {
+    GPIOx->BSRR = GPIO_Pin;
+  }
+  else
+  {
+    GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
+  }
+}
+
+/**
+  * @brief  Toggles the specified GPIO pins.
+  * @param  GPIOx: Where x can be (A..K) to select the GPIO peripheral.
+  * @param  GPIO_Pin: Specifies the pins to be toggled.
+  * @retval None
+  */
+void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  if ((GPIOx->ODR & GPIO_Pin) == GPIO_Pin)
+  {
+    GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
+  }
+  else
+  {
+    GPIOx->BSRR = GPIO_Pin;
+  }
+}
+
+/**
+  * @brief  Locks GPIO Pins configuration registers.
+  * @note   The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
+  *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
+  * @note   The configuration of the locked GPIO pins can no longer be modified
+  *         until the next reset.
+  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32H7 family
+  * @param  GPIO_Pin: specifies the port bit to be locked.
+  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+  __IO uint32_t tmp = GPIO_LCKR_LCKK;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  /* Apply lock key write sequence */
+  tmp |= GPIO_Pin;
+  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+  GPIOx->LCKR = tmp;
+  /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
+  GPIOx->LCKR = GPIO_Pin;
+  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+  GPIOx->LCKR = tmp;
+  /* Read LCKK register. This read is mandatory to complete key lock sequence*/
+  tmp = GPIOx->LCKR;
+
+  /* read again in order to confirm lock is active */
+  if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00U)
+  {
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Handle EXTI interrupt request.
+  * @param  GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
+  * @retval None
+  */
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
+{
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  if (__HAL_GPIO_EXTID2_GET_IT(GPIO_Pin) != 0x00U)
+  {
+    __HAL_GPIO_EXTID2_CLEAR_IT(GPIO_Pin);
+    HAL_GPIO_EXTI_Callback(GPIO_Pin);
+  }
+#else
+  /* EXTI line interrupt detected */
+  if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00U)
+  {
+    __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
+    HAL_GPIO_EXTI_Callback(GPIO_Pin);
+  }
+#endif
+}
+
+/**
+  * @brief  EXTI line detection callback.
+  * @param  GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
+  * @retval None
+  */
+__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(GPIO_Pin);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+           the HAL_GPIO_EXTI_Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+#endif /* HAL_GPIO_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c
new file mode 100644
index 00000000..1fab0cef
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c
@@ -0,0 +1,441 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_hsem.c
+  * @author  MCD Application Team
+  * @brief   HSEM HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the semaphore peripheral:
+  *           + Semaphore Take function (2-Step Procedure) , non blocking
+  *           + Semaphore FastTake function (1-Step Procedure) , non blocking
+  *           + Semaphore Status check
+  *           + Semaphore Clear Key Set and Get
+  *           + Release and release all functions
+  *           + Semaphore notification enabling and disabling and callnack functions
+  *           + IRQ handler management
+  *
+  *
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+      (#)Take a semaphore In 2-Step mode Using function HAL_HSEM_Take. This function takes as parameters :
+           (++) the semaphore ID from 0 to 31
+           (++) the process ID from 0 to 255
+      (#) Fast Take semaphore In 1-Step mode Using function HAL_HSEM_FastTake. This function takes as parameter :
+           (++) the semaphore ID from 0_ID to 31. Note that the process ID value is implicitly assumed as zero
+      (#) Check if a semaphore is Taken using function HAL_HSEM_IsSemTaken. This function takes as parameter :
+          (++) the semaphore ID from 0_ID to 31
+          (++) It returns 1 if the given semaphore is taken otherwise (Free) zero
+      (#)Release a semaphore using function with HAL_HSEM_Release. This function takes as parameters :
+           (++) the semaphore ID from 0 to 31
+           (++) the process ID from 0 to 255:
+           (++) Note: If ProcessID and MasterID match, semaphore is freed, and an interrupt
+         may be generated when enabled (notification activated). If ProcessID or MasterID does not match,
+         semaphore remains taken (locked)
+
+      (#)Release all semaphores at once taken by a given Master using function HAL_HSEM_Release_All
+          This function takes as parameters :
+           (++) the Release Key (value from 0 to 0xFFFF) can be Set or Get respectively by
+              HAL_HSEM_SetClearKey() or HAL_HSEM_GetClearKey functions
+           (++) the Master ID:
+           (++) Note: If the Key and MasterID match, all semaphores taken by the given CPU that corresponds
+           to MasterID  will be freed, and an interrupt may be generated when enabled (notification activated). If the
+           Key or the MasterID doesn't match, semaphores remains taken (locked)
+
+      (#)Semaphores Release all key functions:
+         (++)  HAL_HSEM_SetClearKey() to set semaphore release all Key
+         (++)  HAL_HSEM_GetClearKey() to get release all Key
+      (#)Semaphores notification functions :
+         (++)  HAL_HSEM_ActivateNotification to activate a notification callback on
+               a given semaphores Mask (bitfield). When one or more semaphores defined by the mask are released
+               the callback HAL_HSEM_FreeCallback will be asserted giving as parameters a mask of the released
+               semaphores (bitfield).
+
+         (++)  HAL_HSEM_DeactivateNotification to deactivate the notification of a given semaphores Mask (bitfield).
+         (++) See the description of the macro __HAL_HSEM_SEMID_TO_MASK to check how to calculate a semaphore mask
+                Used by the notification functions
+     *** HSEM HAL driver macros list ***
+     =============================================
+     [..] Below the list of most used macros in HSEM HAL driver.
+
+      (+) __HAL_HSEM_SEMID_TO_MASK: Helper macro to convert a Semaphore ID to a Mask.
+      [..] Example of use :
+      [..] mask = __HAL_HSEM_SEMID_TO_MASK(8)  |  __HAL_HSEM_SEMID_TO_MASK(21) | __HAL_HSEM_SEMID_TO_MASK(25).
+      [..] All next macros take as parameter a semaphore Mask (bitfiled) that can be constructed using  __HAL_HSEM_SEMID_TO_MASK as the above example.
+      (+) __HAL_HSEM_ENABLE_IT: Enable the specified semaphores Mask interrupts.
+      (+) __HAL_HSEM_DISABLE_IT: Disable the specified semaphores Mask interrupts.
+      (+) __HAL_HSEM_GET_IT: Checks whether the specified semaphore interrupt has occurred or not.
+      (+) __HAL_HSEM_GET_FLAG: Get the semaphores status release flags.
+      (+) __HAL_HSEM_CLEAR_FLAG: Clear the semaphores status release flags.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup HSEM HSEM
+  * @brief HSEM HAL module driver
+  * @{
+  */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#if defined(DUAL_CORE)
+#ifndef HSEM_R_MASTERID
+#define HSEM_R_MASTERID HSEM_R_COREID
+#endif
+
+#ifndef HSEM_RLR_MASTERID
+#define HSEM_RLR_MASTERID HSEM_RLR_COREID
+#endif
+
+#ifndef HSEM_CR_MASTERID
+#define HSEM_CR_MASTERID HSEM_CR_COREID
+#endif
+#endif /* DUAL_CORE */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup HSEM_Exported_Functions  HSEM Exported Functions
+  * @{
+  */
+
+/** @defgroup HSEM_Exported_Functions_Group1 Take and Release functions
+  *  @brief    HSEM Take and Release functions
+  *
+@verbatim
+ ==============================================================================
+              ##### HSEM Take and Release functions #####
+ ==============================================================================
+[..] This section provides functions allowing to:
+      (+) Take a semaphore with 2 Step method
+      (+) Fast Take a semaphore with 1 Step method
+      (+) Check semaphore state Taken or not
+      (+) Release a semaphore
+      (+) Release all semaphore at once
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Take a semaphore in 2 Step mode.
+  * @param  SemID: semaphore ID from 0 to 31
+  * @param  ProcessID: Process ID from 0 to 255
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID)
+{
+  /* Check the parameters */
+  assert_param(IS_HSEM_SEMID(SemID));
+  assert_param(IS_HSEM_PROCESSID(ProcessID));
+
+#if  USE_MULTI_CORE_SHARED_CODE != 0U
+  /* First step  write R register with MasterID, processID and take bit=1*/
+  HSEM->R[SemID] = ((ProcessID & HSEM_R_PROCID) | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID) | HSEM_R_LOCK);
+
+  /* second step : read the R register . Take achieved if MasterID and processID match and take bit set to 1 */
+  if (HSEM->R[SemID] == ((ProcessID & HSEM_R_PROCID) | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID) | HSEM_R_LOCK))
+  {
+    /*take success when MasterID and ProcessID match and take bit set*/
+    return HAL_OK;
+  }
+#else
+  /* First step  write R register with MasterID, processID and take bit=1*/
+  HSEM->R[SemID] = (ProcessID | HSEM_CR_COREID_CURRENT | HSEM_R_LOCK);
+
+  /* second step : read the R register . Take achieved if MasterID and processID match and take bit set to 1 */
+  if (HSEM->R[SemID] == (ProcessID | HSEM_CR_COREID_CURRENT | HSEM_R_LOCK))
+  {
+    /*take success when MasterID and ProcessID match and take bit set*/
+    return HAL_OK;
+  }
+#endif
+
+  /* Semaphore take fails*/
+  return HAL_ERROR;
+}
+
+/**
+  * @brief  Fast Take a semaphore with 1 Step mode.
+  * @param  SemID: semaphore ID from 0 to 31
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HSEM_FastTake(uint32_t SemID)
+{
+  /* Check the parameters */
+  assert_param(IS_HSEM_SEMID(SemID));
+
+#if  USE_MULTI_CORE_SHARED_CODE != 0U
+  /* Read the RLR register to take the semaphore */
+  if (HSEM->RLR[SemID] == (((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_RLR_MASTERID) | HSEM_RLR_LOCK))
+  {
+    /*take success when MasterID match and take bit set*/
+    return HAL_OK;
+  }
+#else
+  /* Read the RLR register to take the semaphore */
+  if (HSEM->RLR[SemID] == (HSEM_CR_COREID_CURRENT | HSEM_RLR_LOCK))
+  {
+    /*take success when MasterID match and take bit set*/
+    return HAL_OK;
+  }
+#endif
+
+  /* Semaphore take fails */
+  return HAL_ERROR;
+}
+/**
+  * @brief  Check semaphore state Taken or not.
+  * @param  SemID: semaphore ID
+  * @retval HAL HSEM state
+  */
+uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID)
+{
+  return (((HSEM->R[SemID] & HSEM_R_LOCK) != 0U) ? 1UL : 0UL);
+}
+
+
+/**
+  * @brief  Release a semaphore.
+  * @param  SemID: semaphore ID from 0 to 31
+  * @param  ProcessID: Process ID from 0 to 255
+  * @retval None
+  */
+void  HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID)
+{
+  /* Check the parameters */
+  assert_param(IS_HSEM_SEMID(SemID));
+  assert_param(IS_HSEM_PROCESSID(ProcessID));
+
+  /* Clear the semaphore by writing to the R register : the MasterID , the processID and take bit = 0  */
+#if  USE_MULTI_CORE_SHARED_CODE != 0U
+  HSEM->R[SemID] = (ProcessID | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID));
+#else
+  HSEM->R[SemID] = (ProcessID | HSEM_CR_COREID_CURRENT);
+#endif
+
+}
+
+/**
+  * @brief  Release All semaphore used by a given Master .
+  * @param  Key: Semaphore Key , value from 0 to 0xFFFF
+  * @param  CoreID: CoreID of the CPU that is using semaphores to be released
+  * @retval None
+  */
+void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t CoreID)
+{
+  assert_param(IS_HSEM_KEY(Key));
+  assert_param(IS_HSEM_COREID(CoreID));
+
+  HSEM->CR = ((Key << HSEM_CR_KEY_Pos) | (CoreID << HSEM_CR_COREID_Pos));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HSEM_Exported_Functions_Group2 HSEM Set and Get Key functions
+  *  @brief    HSEM Set and Get Key functions.
+  *
+@verbatim
+  ==============================================================================
+              ##### HSEM Set and Get Key functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Set semaphore Key
+      (+) Get semaphore Key
+@endverbatim
+
+  * @{
+  */
+
+/**
+  * @brief  Set semaphore Key .
+  * @param  Key: Semaphore Key , value from 0 to 0xFFFF
+  * @retval None
+  */
+void  HAL_HSEM_SetClearKey(uint32_t Key)
+{
+  assert_param(IS_HSEM_KEY(Key));
+
+  MODIFY_REG(HSEM->KEYR, HSEM_KEYR_KEY, (Key << HSEM_KEYR_KEY_Pos));
+
+}
+
+/**
+  * @brief  Get semaphore Key .
+  * @retval Semaphore Key , value from 0 to 0xFFFF
+  */
+uint32_t HAL_HSEM_GetClearKey(void)
+{
+  return (HSEM->KEYR >> HSEM_KEYR_KEY_Pos);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HSEM_Exported_Functions_Group3 HSEM IRQ handler management
+  *  @brief    HSEM Notification functions.
+  *
+@verbatim
+  ==============================================================================
+      ##### HSEM IRQ handler management and Notification functions #####
+  ==============================================================================
+[..]  This section provides HSEM IRQ handler and Notification function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Activate Semaphore release Notification for a given Semaphores Mask .
+  * @param  SemMask: Mask of Released semaphores
+  * @retval Semaphore Key
+  */
+void HAL_HSEM_ActivateNotification(uint32_t SemMask)
+{
+#if  USE_MULTI_CORE_SHARED_CODE != 0U
+  /*enable the semaphore mask interrupts */
+  if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID)
+  {
+    /*Use interrupt line 0 for CPU1 Master */
+    HSEM->C1IER |= SemMask;
+  }
+  else /* HSEM_CPU2_COREID */
+  {
+    /*Use interrupt line 1 for CPU2 Master*/
+    HSEM->C2IER |= SemMask;
+  }
+#else
+  HSEM_COMMON->IER |= SemMask;
+#endif
+}
+
+/**
+  * @brief  Deactivate Semaphore release Notification for a given Semaphores Mask .
+  * @param  SemMask: Mask of Released semaphores
+  * @retval Semaphore Key
+  */
+void HAL_HSEM_DeactivateNotification(uint32_t SemMask)
+{
+#if  USE_MULTI_CORE_SHARED_CODE != 0U
+  /*enable the semaphore mask interrupts */
+  if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID)
+  {
+    /*Use interrupt line 0 for CPU1 Master */
+    HSEM->C1IER &= ~SemMask;
+  }
+  else /* HSEM_CPU2_COREID */
+  {
+    /*Use interrupt line 1 for CPU2 Master*/
+    HSEM->C2IER &= ~SemMask;
+  }
+#else
+  HSEM_COMMON->IER &= ~SemMask;
+#endif
+}
+
+/**
+  * @brief  This function handles HSEM interrupt request
+  * @retval None
+  */
+void HAL_HSEM_IRQHandler(void)
+{
+  uint32_t statusreg;
+#if  USE_MULTI_CORE_SHARED_CODE != 0U
+  if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID)
+  {
+    /* Get the list of masked freed semaphores*/
+    statusreg = HSEM->C1MISR; /*Use interrupt line 0 for CPU1 Master*/
+
+    /*Disable Interrupts*/
+    HSEM->C1IER &= ~((uint32_t)statusreg);
+
+    /*Clear Flags*/
+    HSEM->C1ICR = ((uint32_t)statusreg);
+  }
+  else /* HSEM_CPU2_COREID */
+  {
+    /* Get the list of masked freed semaphores*/
+    statusreg = HSEM->C2MISR;/*Use interrupt line 1 for CPU2 Master*/
+
+    /*Disable Interrupts*/
+    HSEM->C2IER &= ~((uint32_t)statusreg);
+
+    /*Clear Flags*/
+    HSEM->C2ICR = ((uint32_t)statusreg);
+  }
+#else
+  /* Get the list of masked freed semaphores*/
+  statusreg = HSEM_COMMON->MISR;
+
+  /*Disable Interrupts*/
+  HSEM_COMMON->IER &= ~((uint32_t)statusreg);
+
+  /*Clear Flags*/
+  HSEM_COMMON->ICR = ((uint32_t)statusreg);
+
+#endif
+  /* Call FreeCallback */
+  HAL_HSEM_FreeCallback(statusreg);
+}
+
+/**
+  * @brief Semaphore Released Callback.
+  * @param SemMask: Mask of Released semaphores
+  * @retval None
+  */
+__weak void HAL_HSEM_FreeCallback(uint32_t SemMask)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(SemMask);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+  the HAL_HSEM_FreeCallback can be implemented in the user file
+    */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_HSEM_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c
new file mode 100644
index 00000000..7c05d16f
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c
@@ -0,0 +1,6635 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_i2c.c
+  * @author  MCD Application Team
+  * @brief   I2C HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Inter Integrated Circuit (I2C) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral State and Errors functions
+  *
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The I2C HAL driver can be used as follows:
+
+    (#) Declare a I2C_HandleTypeDef handle structure, for example:
+        I2C_HandleTypeDef  hi2c;
+
+    (#)Initialize the I2C low level resources by implementing the @ref HAL_I2C_MspInit() API:
+        (##) Enable the I2Cx interface clock
+        (##) I2C pins configuration
+            (+++) Enable the clock for the I2C GPIOs
+            (+++) Configure I2C pins as alternate function open-drain
+        (##) NVIC configuration if you need to use interrupt process
+            (+++) Configure the I2Cx interrupt priority
+            (+++) Enable the NVIC I2C IRQ Channel
+        (##) DMA Configuration if you need to use DMA process
+            (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream or channel depends on Instance
+            (+++) Enable the DMAx interface clock using
+            (+++) Configure the DMA handle parameters
+            (+++) Configure the DMA Tx or Rx stream or channel depends on Instance
+            (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
+            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
+                  the DMA Tx or Rx stream or channel depends on Instance
+
+    (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
+        Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
+
+    (#) Initialize the I2C registers by calling the @ref HAL_I2C_Init(), configures also the low level Hardware
+        (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_I2C_MspInit(&hi2c) API.
+
+    (#) To check if target device is ready for communication, use the function @ref HAL_I2C_IsDeviceReady()
+
+    (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
+
+    *** Polling mode IO operation ***
+    =================================
+    [..]
+      (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Transmit()
+      (+) Receive in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Receive()
+      (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Transmit()
+      (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Receive()
+
+    *** Polling mode IO MEM operation ***
+    =====================================
+    [..]
+      (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_I2C_Mem_Write()
+      (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_I2C_Mem_Read()
+
+
+    *** Interrupt mode IO operation ***
+    ===================================
+    [..]
+      (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Transmit_IT()
+      (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
+      (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Receive_IT()
+      (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
+      (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Transmit_IT()
+      (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
+      (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Receive_IT()
+      (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
+      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
+      (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
+      (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
+      (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.
+           This action will inform Master to generate a Stop condition to discard the communication.
+
+
+    *** Interrupt mode or DMA mode IO sequential operation ***
+    ==========================================================
+    [..]
+      (@) These interfaces allow to manage a sequential transfer with a repeated start condition
+          when a direction change during transfer
+    [..]
+      (+) A specific option field manage the different steps of a sequential transfer
+      (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:
+      (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
+      (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
+                            and data to transfer without a final stop condition
+      (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
+                            and data to transfer without a final stop condition, an then permit a call the same master sequential interface
+                            several times (like @ref HAL_I2C_Master_Seq_Transmit_IT() then @ref HAL_I2C_Master_Seq_Transmit_IT()
+                            or @ref HAL_I2C_Master_Seq_Transmit_DMA() then @ref HAL_I2C_Master_Seq_Transmit_DMA())
+      (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
+                            and with new data to transfer if the direction change or manage only the new data to transfer
+                            if no direction change and without a final stop condition in both cases
+      (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
+                            and with new data to transfer if the direction change or manage only the new data to transfer
+                            if no direction change and with a final stop condition in both cases
+      (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential
+                            interface several times (link with option I2C_FIRST_AND_NEXT_FRAME).
+                            Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
+                              or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
+                              or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
+                              or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME).
+                            Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit
+                              without stopping the communication and so generate a restart condition.
+      (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential
+                            interface.
+                            Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
+                              or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
+                              or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
+                              or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME).
+                            Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition.
+
+      (+) Differents sequential I2C interfaces are listed below:
+      (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT()
+            or using @ref HAL_I2C_Master_Seq_Transmit_DMA()
+      (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
+      (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Receive_IT()
+            or using @ref HAL_I2C_Master_Seq_Receive_DMA()
+      (+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
+      (++) Abort a master IT or DMA I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
+      (+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
+      (++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen_IT() @ref HAL_I2C_DisableListen_IT()
+      (+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and user can
+           add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
+      (+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback()
+      (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Transmit_IT()
+            or using @ref HAL_I2C_Slave_Seq_Transmit_DMA()
+      (+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
+      (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Receive_IT()
+            or using @ref HAL_I2C_Slave_Seq_Receive_DMA()
+      (+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
+      (++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
+      (++) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.
+           This action will inform Master to generate a Stop condition to discard the communication.
+
+    *** Interrupt mode IO MEM operation ***
+    =======================================
+    [..]
+      (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
+          @ref HAL_I2C_Mem_Write_IT()
+      (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()
+      (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
+          @ref HAL_I2C_Mem_Read_IT()
+      (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()
+      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
+
+    *** DMA mode IO operation ***
+    ==============================
+    [..]
+      (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
+          @ref HAL_I2C_Master_Transmit_DMA()
+      (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
+      (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
+          @ref HAL_I2C_Master_Receive_DMA()
+      (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
+      (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
+          @ref HAL_I2C_Slave_Transmit_DMA()
+      (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
+      (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
+          @ref HAL_I2C_Slave_Receive_DMA()
+      (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
+      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
+      (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
+      (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
+      (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.
+           This action will inform Master to generate a Stop condition to discard the communication.
+
+    *** DMA mode IO MEM operation ***
+    =================================
+    [..]
+      (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
+          @ref HAL_I2C_Mem_Write_DMA()
+      (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()
+      (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
+          @ref HAL_I2C_Mem_Read_DMA()
+      (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()
+      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
+
+
+     *** I2C HAL driver macros list ***
+     ==================================
+     [..]
+       Below the list of most used macros in I2C HAL driver.
+
+      (+) @ref __HAL_I2C_ENABLE: Enable the I2C peripheral
+      (+) @ref __HAL_I2C_DISABLE: Disable the I2C peripheral
+      (+) @ref __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
+      (+) @ref __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
+      (+) @ref __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
+      (+) @ref __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
+      (+) @ref __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
+
+     *** Callback registration ***
+     =============================================
+    [..]
+     The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
+     allows the user to configure dynamically the driver callbacks.
+     Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback()
+     to register an interrupt callback.
+    [..]
+     Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks:
+       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+       (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
+       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
+       (+) ListenCpltCallback   : callback for end of listen mode.
+       (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.
+       (+) MemRxCpltCallback    : callback for Memory reception end of transfer.
+       (+) ErrorCallback        : callback for error detection.
+       (+) AbortCpltCallback    : callback for abort completion process.
+       (+) MspInitCallback      : callback for Msp Init.
+       (+) MspDeInitCallback    : callback for Msp DeInit.
+     This function takes as parameters the HAL peripheral handle, the Callback ID
+     and a pointer to the user callback function.
+    [..]
+     For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback().
+    [..]
+     Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default
+     weak function.
+     @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
+     and the Callback ID.
+     This function allows to reset following callbacks:
+       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+       (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
+       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
+       (+) ListenCpltCallback   : callback for end of listen mode.
+       (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.
+       (+) MemRxCpltCallback    : callback for Memory reception end of transfer.
+       (+) ErrorCallback        : callback for error detection.
+       (+) AbortCpltCallback    : callback for abort completion process.
+       (+) MspInitCallback      : callback for Msp Init.
+       (+) MspDeInitCallback    : callback for Msp DeInit.
+    [..]
+     For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback().
+    [..]
+     By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET
+     all callbacks are set to the corresponding weak functions:
+     examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback().
+     Exception done for MspInit and MspDeInit functions that are
+     reset to the legacy weak functions in the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() only when
+     these callbacks are null (not registered beforehand).
+     If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit()
+     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+    [..]
+     Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.
+     Exception done MspInit/MspDeInit functions that can be registered/unregistered
+     in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,
+     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+     Then, the user first registers the MspInit/MspDeInit user callbacks
+     using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit()
+     or @ref HAL_I2C_Init() function.
+    [..]
+     When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
+     not defined, the callback registration feature is not available and all callbacks
+     are set to the corresponding weak functions.
+
+     [..]
+       (@) You can refer to the I2C HAL driver header file for more useful macros
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup I2C I2C
+  * @brief I2C HAL module driver
+  * @{
+  */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup I2C_Private_Define I2C Private Define
+  * @{
+  */
+#define TIMING_CLEAR_MASK   (0xF0FFFFFFU)  /*!< I2C TIMING clear register Mask */
+#define I2C_TIMEOUT_ADDR    (10000U)       /*!< 10 s  */
+#define I2C_TIMEOUT_BUSY    (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_DIR     (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_RXNE    (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_STOPF   (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_TC      (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_TCR     (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_TXIS    (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_FLAG    (25U)          /*!< 25 ms */
+
+#define MAX_NBYTE_SIZE      255U
+#define SlaveAddr_SHIFT     7U
+#define SlaveAddr_MSK       0x06U
+
+/* Private define for @ref PreviousState usage */
+#define I2C_STATE_MSK             ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits            */
+#define I2C_STATE_NONE            ((uint32_t)(HAL_I2C_MODE_NONE))                                                        /*!< Default Value                                          */
+#define I2C_STATE_MASTER_BUSY_TX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER))            /*!< Master Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MASTER_BUSY_RX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER))            /*!< Master Busy RX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_SLAVE_BUSY_TX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE))             /*!< Slave Busy TX, combinaison of State LSB and Mode enum  */
+#define I2C_STATE_SLAVE_BUSY_RX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE))             /*!< Slave Busy RX, combinaison of State LSB and Mode enum  */
+#define I2C_STATE_MEM_BUSY_TX     ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM))               /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MEM_BUSY_RX     ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM))               /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
+
+
+/* Private define to centralize the enable/disable of Interrupts */
+#define I2C_XFER_TX_IT          (uint16_t)(0x0001U)   /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */
+#define I2C_XFER_RX_IT          (uint16_t)(0x0002U)   /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */
+#define I2C_XFER_LISTEN_IT      (uint16_t)(0x8000U)   /* Bit field can be combinated with @ref I2C_XFER_TX_IT and @ref I2C_XFER_RX_IT */
+
+#define I2C_XFER_ERROR_IT       (uint16_t)(0x0010U)   /* Bit definition to manage addition of global Error and NACK treatment */
+#define I2C_XFER_CPLT_IT        (uint16_t)(0x0020U)   /* Bit definition to manage only STOP evenement */
+#define I2C_XFER_RELOAD_IT      (uint16_t)(0x0040U)   /* Bit definition to manage only Reload of NBYTE */
+
+/* Private define Sequential Transfer Options default/reset value */
+#define I2C_NO_OPTION_FRAME     (0xFFFF0000U)
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/** @defgroup I2C_Private_Functions I2C Private Functions
+  * @{
+  */
+/* Private functions to handle DMA transfer */
+static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMAError(DMA_HandleTypeDef *hdma);
+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
+
+/* Private functions to handle IT transfer */
+static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c);
+static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c);
+static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
+
+/* Private functions to handle IT transfer */
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
+
+/* Private functions for I2C transfer IRQ handler */
+static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
+
+/* Private functions to handle flags during polling transfer */
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+
+/* Private functions to centralize the enable/disable of Interrupts */
+static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
+static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
+
+/* Private function to treat different error callback */
+static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c);
+
+/* Private function to flush TXDR register */
+static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
+
+/* Private function to handle  start, restart or stop a transfer */
+static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
+
+/* Private function to Convert Specific options */
+static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Functions I2C Exported Functions
+  * @{
+  */
+
+/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This subsection provides a set of functions allowing to initialize and
+          deinitialize the I2Cx peripheral:
+
+      (+) User must Implement HAL_I2C_MspInit() function in which he configures
+          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+      (+) Call the function HAL_I2C_Init() to configure the selected device with
+          the selected configuration:
+        (++) Clock Timing
+        (++) Own Address 1
+        (++) Addressing mode (Master, Slave)
+        (++) Dual Addressing mode
+        (++) Own Address 2
+        (++) Own Address 2 Mask
+        (++) General call mode
+        (++) Nostretch mode
+
+      (+) Call the function HAL_I2C_DeInit() to restore the default configuration
+          of the selected I2Cx peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the I2C according to the specified parameters
+  *         in the I2C_InitTypeDef and initialize the associated handle.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
+{
+  /* Check the I2C handle allocation */
+  if (hi2c == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
+  assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
+  assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
+  assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
+  assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
+  assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
+  assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
+
+  if (hi2c->State == HAL_I2C_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hi2c->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    /* Init the I2C Callback settings */
+    hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
+    hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
+    hi2c->SlaveTxCpltCallback  = HAL_I2C_SlaveTxCpltCallback;  /* Legacy weak SlaveTxCpltCallback  */
+    hi2c->SlaveRxCpltCallback  = HAL_I2C_SlaveRxCpltCallback;  /* Legacy weak SlaveRxCpltCallback  */
+    hi2c->ListenCpltCallback   = HAL_I2C_ListenCpltCallback;   /* Legacy weak ListenCpltCallback   */
+    hi2c->MemTxCpltCallback    = HAL_I2C_MemTxCpltCallback;    /* Legacy weak MemTxCpltCallback    */
+    hi2c->MemRxCpltCallback    = HAL_I2C_MemRxCpltCallback;    /* Legacy weak MemRxCpltCallback    */
+    hi2c->ErrorCallback        = HAL_I2C_ErrorCallback;        /* Legacy weak ErrorCallback        */
+    hi2c->AbortCpltCallback    = HAL_I2C_AbortCpltCallback;    /* Legacy weak AbortCpltCallback    */
+    hi2c->AddrCallback         = HAL_I2C_AddrCallback;         /* Legacy weak AddrCallback         */
+
+    if (hi2c->MspInitCallback == NULL)
+    {
+      hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit  */
+    }
+
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+    hi2c->MspInitCallback(hi2c);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+    HAL_I2C_MspInit(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+
+  hi2c->State = HAL_I2C_STATE_BUSY;
+
+  /* Disable the selected I2C peripheral */
+  __HAL_I2C_DISABLE(hi2c);
+
+  /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
+  /* Configure I2Cx: Frequency range */
+  hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
+
+  /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
+  /* Disable Own Address1 before set the Own Address1 configuration */
+  hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
+
+  /* Configure I2Cx: Own Address1 and ack own address1 mode */
+  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
+  {
+    hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
+  }
+  else /* I2C_ADDRESSINGMODE_10BIT */
+  {
+    hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
+  }
+
+  /*---------------------------- I2Cx CR2 Configuration ----------------------*/
+  /* Configure I2Cx: Addressing Master mode */
+  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+  {
+    hi2c->Instance->CR2 = (I2C_CR2_ADD10);
+  }
+  /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
+  hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
+
+  /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
+  /* Disable Own Address2 before set the Own Address2 configuration */
+  hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
+
+  /* Configure I2Cx: Dual mode and Own Address2 */
+  hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));
+
+  /*---------------------------- I2Cx CR1 Configuration ----------------------*/
+  /* Configure I2Cx: Generalcall and NoStretch mode */
+  hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
+
+  /* Enable the selected I2C peripheral */
+  __HAL_I2C_ENABLE(hi2c);
+
+  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+  hi2c->State = HAL_I2C_STATE_READY;
+  hi2c->PreviousState = I2C_STATE_NONE;
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the I2C peripheral.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
+{
+  /* Check the I2C handle allocation */
+  if (hi2c == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+
+  hi2c->State = HAL_I2C_STATE_BUSY;
+
+  /* Disable the I2C Peripheral Clock */
+  __HAL_I2C_DISABLE(hi2c);
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+  if (hi2c->MspDeInitCallback == NULL)
+  {
+    hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit  */
+  }
+
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  hi2c->MspDeInitCallback(hi2c);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_I2C_MspDeInit(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+
+  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+  hi2c->State = HAL_I2C_STATE_RESET;
+  hi2c->PreviousState = I2C_STATE_NONE;
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Initialize the I2C MSP.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief DeInitialize the I2C MSP.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MspDeInit could be implemented in the user file
+   */
+}
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User I2C Callback
+  *         To be used instead of the weak predefined callback
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+  *          @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
+  *          @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
+  *          @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
+  *          @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hi2c);
+
+  if (HAL_I2C_STATE_READY == hi2c->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
+        hi2c->MasterTxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
+        hi2c->MasterRxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
+        hi2c->SlaveTxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
+        hi2c->SlaveRxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_LISTEN_COMPLETE_CB_ID :
+        hi2c->ListenCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
+        hi2c->MemTxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
+        hi2c->MemRxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_ERROR_CB_ID :
+        hi2c->ErrorCallback = pCallback;
+        break;
+
+      case HAL_I2C_ABORT_CB_ID :
+        hi2c->AbortCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_MSPINIT_CB_ID :
+        hi2c->MspInitCallback = pCallback;
+        break;
+
+      case HAL_I2C_MSPDEINIT_CB_ID :
+        hi2c->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_I2C_STATE_RESET == hi2c->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_I2C_MSPINIT_CB_ID :
+        hi2c->MspInitCallback = pCallback;
+        break;
+
+      case HAL_I2C_MSPDEINIT_CB_ID :
+        hi2c->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hi2c);
+  return status;
+}
+
+/**
+  * @brief  Unregister an I2C Callback
+  *         I2C callback is redirected to the weak predefined callback
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+  *          @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
+  *          @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
+  *          @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
+  *          @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hi2c);
+
+  if (HAL_I2C_STATE_READY == hi2c->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
+        hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
+        break;
+
+      case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
+        hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
+        break;
+
+      case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
+        hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback;   /* Legacy weak SlaveTxCpltCallback  */
+        break;
+
+      case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
+        hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback;   /* Legacy weak SlaveRxCpltCallback  */
+        break;
+
+      case HAL_I2C_LISTEN_COMPLETE_CB_ID :
+        hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback;     /* Legacy weak ListenCpltCallback   */
+        break;
+
+      case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
+        hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback;       /* Legacy weak MemTxCpltCallback    */
+        break;
+
+      case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
+        hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback;       /* Legacy weak MemRxCpltCallback    */
+        break;
+
+      case HAL_I2C_ERROR_CB_ID :
+        hi2c->ErrorCallback = HAL_I2C_ErrorCallback;               /* Legacy weak ErrorCallback        */
+        break;
+
+      case HAL_I2C_ABORT_CB_ID :
+        hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback;       /* Legacy weak AbortCpltCallback    */
+        break;
+
+      case HAL_I2C_MSPINIT_CB_ID :
+        hi2c->MspInitCallback = HAL_I2C_MspInit;                   /* Legacy weak MspInit              */
+        break;
+
+      case HAL_I2C_MSPDEINIT_CB_ID :
+        hi2c->MspDeInitCallback = HAL_I2C_MspDeInit;               /* Legacy weak MspDeInit            */
+        break;
+
+      default :
+        /* Update the error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_I2C_STATE_RESET == hi2c->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_I2C_MSPINIT_CB_ID :
+        hi2c->MspInitCallback = HAL_I2C_MspInit;                   /* Legacy weak MspInit              */
+        break;
+
+      case HAL_I2C_MSPDEINIT_CB_ID :
+        hi2c->MspDeInitCallback = HAL_I2C_MspDeInit;               /* Legacy weak MspDeInit            */
+        break;
+
+      default :
+        /* Update the error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hi2c);
+  return status;
+}
+
+/**
+  * @brief  Register the Slave Address Match I2C Callback
+  *         To be used instead of the weak HAL_I2C_AddrCallback() predefined callback
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pCallback pointer to the Address Match Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hi2c);
+
+  if (HAL_I2C_STATE_READY == hi2c->State)
+  {
+    hi2c->AddrCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hi2c);
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Slave Address Match I2C Callback
+  *         Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hi2c);
+
+  if (HAL_I2C_STATE_READY == hi2c->State)
+  {
+    hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hi2c);
+  return status;
+}
+
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
+ *  @brief   Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the I2C data
+    transfers.
+
+    (#) There are two modes of transfer:
+       (++) Blocking mode : The communication is performed in the polling mode.
+            The status of all data processing is returned by the same function
+            after finishing transfer.
+       (++) No-Blocking mode : The communication is performed using Interrupts
+            or DMA. These functions return the status of the transfer startup.
+            The end of the data processing will be indicated through the
+            dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
+            using DMA mode.
+
+    (#) Blocking mode functions are :
+        (++) HAL_I2C_Master_Transmit()
+        (++) HAL_I2C_Master_Receive()
+        (++) HAL_I2C_Slave_Transmit()
+        (++) HAL_I2C_Slave_Receive()
+        (++) HAL_I2C_Mem_Write()
+        (++) HAL_I2C_Mem_Read()
+        (++) HAL_I2C_IsDeviceReady()
+
+    (#) No-Blocking mode functions with Interrupt are :
+        (++) HAL_I2C_Master_Transmit_IT()
+        (++) HAL_I2C_Master_Receive_IT()
+        (++) HAL_I2C_Slave_Transmit_IT()
+        (++) HAL_I2C_Slave_Receive_IT()
+        (++) HAL_I2C_Mem_Write_IT()
+        (++) HAL_I2C_Mem_Read_IT()
+        (++) HAL_I2C_Master_Seq_Transmit_IT()
+        (++) HAL_I2C_Master_Seq_Receive_IT()
+        (++) HAL_I2C_Slave_Seq_Transmit_IT()
+        (++) HAL_I2C_Slave_Seq_Receive_IT()
+        (++) HAL_I2C_EnableListen_IT()
+        (++) HAL_I2C_DisableListen_IT()
+        (++) HAL_I2C_Master_Abort_IT()
+
+    (#) No-Blocking mode functions with DMA are :
+        (++) HAL_I2C_Master_Transmit_DMA()
+        (++) HAL_I2C_Master_Receive_DMA()
+        (++) HAL_I2C_Slave_Transmit_DMA()
+        (++) HAL_I2C_Slave_Receive_DMA()
+        (++) HAL_I2C_Mem_Write_DMA()
+        (++) HAL_I2C_Mem_Read_DMA()
+        (++) HAL_I2C_Master_Seq_Transmit_DMA()
+        (++) HAL_I2C_Master_Seq_Receive_DMA()
+        (++) HAL_I2C_Slave_Seq_Transmit_DMA()
+        (++) HAL_I2C_Slave_Seq_Receive_DMA()
+
+    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+        (++) HAL_I2C_MasterTxCpltCallback()
+        (++) HAL_I2C_MasterRxCpltCallback()
+        (++) HAL_I2C_SlaveTxCpltCallback()
+        (++) HAL_I2C_SlaveRxCpltCallback()
+        (++) HAL_I2C_MemTxCpltCallback()
+        (++) HAL_I2C_MemRxCpltCallback()
+        (++) HAL_I2C_AddrCallback()
+        (++) HAL_I2C_ListenCpltCallback()
+        (++) HAL_I2C_ErrorCallback()
+        (++) HAL_I2C_AbortCpltCallback()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Transmits in master mode an amount of data in blocking mode.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferISR   = NULL;
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
+    }
+
+    while (hi2c->XferCount > 0U)
+    {
+      /* Wait until TXIS flag is set */
+      if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+
+      if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+      {
+        /* Wait until TCR flag is set */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        if (hi2c->XferCount > MAX_NBYTE_SIZE)
+        {
+          hi2c->XferSize = MAX_NBYTE_SIZE;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+        }
+        else
+        {
+          hi2c->XferSize = hi2c->XferCount;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+        }
+      }
+    }
+
+    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+    /* Wait until STOPF flag is set */
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Clear STOP Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Clear Configuration Register 2 */
+    I2C_RESET_CR2(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receives in master mode an amount of data in blocking mode.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferISR   = NULL;
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+    }
+
+    while (hi2c->XferCount > 0U)
+    {
+      /* Wait until RXNE flag is set */
+      if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Read data from RXDR */
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+
+      if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+      {
+        /* Wait until TCR flag is set */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        if (hi2c->XferCount > MAX_NBYTE_SIZE)
+        {
+          hi2c->XferSize = MAX_NBYTE_SIZE;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+        }
+        else
+        {
+          hi2c->XferSize = hi2c->XferCount;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+        }
+      }
+    }
+
+    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+    /* Wait until STOPF flag is set */
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Clear STOP Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Clear Configuration Register 2 */
+    I2C_RESET_CR2(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmits in slave mode an amount of data in blocking mode.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferISR   = NULL;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Wait until ADDR flag is set */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+
+    /* If 10bit addressing mode is selected */
+    if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+    {
+      /* Wait until ADDR flag is set */
+      if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+      {
+        /* Disable Address Acknowledge */
+        hi2c->Instance->CR2 |= I2C_CR2_NACK;
+        return HAL_ERROR;
+      }
+
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+    }
+
+    /* Wait until DIR flag is set Transmitter mode */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    while (hi2c->XferCount > 0U)
+    {
+      /* Wait until TXIS flag is set */
+      if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        /* Disable Address Acknowledge */
+        hi2c->Instance->CR2 |= I2C_CR2_NACK;
+        return HAL_ERROR;
+      }
+
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+    }
+
+    /* Wait until STOP flag is set */
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      {
+        /* Normal use case for Transmitter mode */
+        /* A NACK is generated to confirm the end of transfer */
+        hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+      }
+      else
+      {
+        return HAL_ERROR;
+      }
+    }
+
+    /* Clear STOP flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Wait until BUSY flag is reset */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    /* Disable Address Acknowledge */
+    hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in slave mode an amount of data in blocking mode
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferISR   = NULL;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Wait until ADDR flag is set */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+
+    /* Wait until DIR flag is reset Receiver mode */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    while (hi2c->XferCount > 0U)
+    {
+      /* Wait until RXNE flag is set */
+      if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        /* Disable Address Acknowledge */
+        hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+        /* Store Last receive data if any */
+        if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+        {
+          /* Read data from RXDR */
+          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+          /* Increment Buffer pointer */
+          hi2c->pBuffPtr++;
+
+          hi2c->XferCount--;
+        }
+
+        return HAL_ERROR;
+      }
+
+      /* Read data from RXDR */
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+    }
+
+    /* Wait until STOP flag is set */
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    /* Clear STOP flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Wait until BUSY flag is reset */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    /* Disable Address Acknowledge */
+    hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit in master mode an amount of data in non-blocking mode with Interrupt
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+  uint32_t xfermode;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_IT;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in master mode an amount of data in non-blocking mode with Interrupt
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+  uint32_t xfermode;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_IT;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit in slave mode an amount of data in non-blocking mode with Interrupt
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Slave_ISR_IT;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in slave mode an amount of data in non-blocking mode with Interrupt
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Slave_ISR_IT;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit in master mode an amount of data in non-blocking mode with DMA
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+  uint32_t xfermode;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_DMA;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    if (hi2c->XferSize > 0U)
+    {
+      if (hi2c->hdmatx != NULL)
+      {
+        /* Set the I2C DMA transfer complete callback */
+        hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+
+        /* Set the DMA error callback */
+        hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hi2c->hdmatx->XferHalfCpltCallback = NULL;
+        hi2c->hdmatx->XferAbortCallback = NULL;
+
+        /* Enable the DMA stream or channel depends on Instance */
+        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+
+      if (dmaxferstatus == HAL_OK)
+      {
+        /* Send Slave Address */
+        /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
+
+        /* Update XferCount value */
+        hi2c->XferCount -= hi2c->XferSize;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Note : The I2C interrupts must be enabled after unlocking current process
+                  to avoid the risk of I2C interrupt handle execution before current
+                  process unlock */
+        /* Enable ERR and NACK interrupts */
+        I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+        /* Enable DMA Request */
+        hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Update Transfer ISR function pointer */
+      hi2c->XferISR = I2C_Master_ISR_IT;
+
+      /* Send Slave Address */
+      /* Set NBYTES to write and generate START condition */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+      /* possible to enable all of these */
+      /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in master mode an amount of data in non-blocking mode with DMA
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+  uint32_t xfermode;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_DMA;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    if (hi2c->XferSize > 0U)
+    {
+      if (hi2c->hdmarx != NULL)
+      {
+        /* Set the I2C DMA transfer complete callback */
+        hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+
+        /* Set the DMA error callback */
+        hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hi2c->hdmarx->XferHalfCpltCallback = NULL;
+        hi2c->hdmarx->XferAbortCallback = NULL;
+
+        /* Enable the DMA stream or channel depends on Instance */
+        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+
+      if (dmaxferstatus == HAL_OK)
+      {
+        /* Send Slave Address */
+        /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+
+        /* Update XferCount value */
+        hi2c->XferCount -= hi2c->XferSize;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Note : The I2C interrupts must be enabled after unlocking current process
+                  to avoid the risk of I2C interrupt handle execution before current
+                  process unlock */
+        /* Enable ERR and NACK interrupts */
+        I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+        /* Enable DMA Request */
+        hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Update Transfer ISR function pointer */
+      hi2c->XferISR = I2C_Master_ISR_IT;
+
+      /* Send Slave Address */
+      /* Set NBYTES to read and generate START condition */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+      /* possible to enable all of these */
+      /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit in slave mode an amount of data in non-blocking mode with DMA
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef dmaxferstatus;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Slave_ISR_DMA;
+
+    if (hi2c->hdmatx != NULL)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmatx->XferHalfCpltCallback = NULL;
+      hi2c->hdmatx->XferAbortCallback = NULL;
+
+      /* Enable the DMA stream or channel depends on Instance */
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Enable Address Acknowledge */
+      hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, STOP, NACK, ADDR interrupts */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+      /* Enable DMA Request */
+      hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in slave mode an amount of data in non-blocking mode with DMA
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef dmaxferstatus;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Slave_ISR_DMA;
+
+    if (hi2c->hdmarx != NULL)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmarx->XferHalfCpltCallback = NULL;
+      hi2c->hdmarx->XferAbortCallback = NULL;
+
+      /* Enable the DMA stream or channel depends on Instance */
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Enable Address Acknowledge */
+      hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, STOP, NACK, ADDR interrupts */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+      /* Enable DMA Request */
+      hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+/**
+  * @brief  Write an amount of data in blocking mode to a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferISR   = NULL;
+
+    /* Send Slave Address and Memory Address */
+    if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+      return HAL_ERROR;
+    }
+
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+    }
+
+    do
+    {
+      /* Wait until TXIS flag is set */
+      if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+
+      if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+      {
+        /* Wait until TCR flag is set */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        if (hi2c->XferCount > MAX_NBYTE_SIZE)
+        {
+          hi2c->XferSize = MAX_NBYTE_SIZE;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+        }
+        else
+        {
+          hi2c->XferSize = hi2c->XferCount;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+        }
+      }
+
+    }
+    while (hi2c->XferCount > 0U);
+
+    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+    /* Wait until STOPF flag is reset */
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Clear STOP Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Clear Configuration Register 2 */
+    I2C_RESET_CR2(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Read an amount of data in blocking mode from a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferISR   = NULL;
+
+    /* Send Slave Address and Memory Address */
+    if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+      return HAL_ERROR;
+    }
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+    }
+
+    do
+    {
+      /* Wait until RXNE flag is set */
+      if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Read data from RXDR */
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+
+      if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+      {
+        /* Wait until TCR flag is set */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        if (hi2c->XferCount > MAX_NBYTE_SIZE)
+        {
+          hi2c->XferSize = MAX_NBYTE_SIZE;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+        }
+        else
+        {
+          hi2c->XferSize = hi2c->XferCount;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+        }
+      }
+    }
+    while (hi2c->XferCount > 0U);
+
+    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+    /* Wait until STOPF flag is reset */
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Clear STOP Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Clear Configuration Register 2 */
+    I2C_RESET_CR2(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+/**
+  * @brief  Write an amount of data in non-blocking mode with Interrupt to a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+  uint32_t tickstart;
+  uint32_t xfermode;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_IT;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    /* Send Slave Address and Memory Address */
+    if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+      return HAL_ERROR;
+    }
+
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Read an amount of data in non-blocking mode with Interrupt from a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+  uint32_t tickstart;
+  uint32_t xfermode;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_IT;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    /* Send Slave Address and Memory Address */
+    if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+      return HAL_ERROR;
+    }
+
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+/**
+  * @brief  Write an amount of data in non-blocking mode with DMA to a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+  uint32_t tickstart;
+  uint32_t xfermode;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_DMA;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    /* Send Slave Address and Memory Address */
+    if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+      return HAL_ERROR;
+    }
+
+
+    if (hi2c->hdmatx != NULL)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmatx->XferHalfCpltCallback = NULL;
+      hi2c->hdmatx->XferAbortCallback = NULL;
+
+      /* Enable the DMA stream or channel depends on Instance */
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_READY;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Send Slave Address */
+      /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+
+      /* Update XferCount value */
+      hi2c->XferCount -= hi2c->XferSize;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR and NACK interrupts */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+      /* Enable DMA Request */
+      hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_READY;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Reads an amount of data in non-blocking mode with DMA from a specific memory address.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be read
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+  uint32_t tickstart;
+  uint32_t xfermode;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_DMA;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    /* Send Slave Address and Memory Address */
+    if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+      return HAL_ERROR;
+    }
+
+    if (hi2c->hdmarx != NULL)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmarx->XferHalfCpltCallback = NULL;
+      hi2c->hdmarx->XferAbortCallback = NULL;
+
+      /* Enable the DMA stream or channel depends on Instance */
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_READY;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+
+      /* Update XferCount value */
+      hi2c->XferCount -= hi2c->XferSize;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR and NACK interrupts */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+      /* Enable DMA Request */
+      hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_READY;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Checks if target device is ready for communication.
+  * @note   This function is used with Memory devices
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  Trials Number of trials
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  __IO uint32_t I2C_Trials = 0UL;
+
+  FlagStatus tmp1;
+  FlagStatus tmp2;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    do
+    {
+      /* Generate Start */
+      hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress);
+
+      /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+      /* Wait until STOPF flag is set or a NACK flag is set*/
+      tickstart = HAL_GetTick();
+
+      tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
+      tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
+
+      while ((tmp1 == RESET) && (tmp2 == RESET))
+      {
+        if (Timeout != HAL_MAX_DELAY)
+        {
+          if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+          {
+            /* Update I2C state */
+            hi2c->State = HAL_I2C_STATE_READY;
+
+            /* Update I2C error code */
+            hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+
+            /* Process Unlocked */
+            __HAL_UNLOCK(hi2c);
+
+            return HAL_ERROR;
+          }
+        }
+
+        tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
+        tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
+      }
+
+      /* Check if the NACKF flag has not been set */
+      if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
+      {
+        /* Wait until STOPF flag is reset */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        /* Clear STOP Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+        /* Device is ready */
+        hi2c->State = HAL_I2C_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_OK;
+      }
+      else
+      {
+        /* Wait until STOPF flag is reset */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        /* Clear NACK Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+        /* Clear STOP Flag, auto generated with autoend*/
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+      }
+
+      /* Check if the maximum allowed number of trials has been reached */
+      if (I2C_Trials == Trials)
+      {
+        /* Generate Stop */
+        hi2c->Instance->CR2 |= I2C_CR2_STOP;
+
+        /* Wait until STOPF flag is reset */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        /* Clear STOP Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+      }
+
+      /* Increment Trials */
+      I2C_Trials++;
+    }
+    while (I2C_Trials < Trials);
+
+    /* Update I2C state */
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Update I2C error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_ERROR;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  uint32_t xfermode;
+  uint32_t xferrequest = I2C_GENERATE_START_WRITE;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Master_ISR_IT;
+
+    /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = hi2c->XferOptions;
+    }
+
+    /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+    /* Mean Previous state is same as current state */
+    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+    {
+      xferrequest = I2C_NO_STARTSTOP;
+    }
+    else
+    {
+      /* Convert OTHER_xxx XferOptions if any */
+      I2C_ConvertOtherXferOptions(hi2c);
+
+      /* Update xfermode accordingly if no reload is necessary */
+      if (hi2c->XferCount < MAX_NBYTE_SIZE)
+      {
+        xfermode = hi2c->XferOptions;
+      }
+    }
+
+    /* Send Slave Address and set NBYTES to write */
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  uint32_t xfermode;
+  uint32_t xferrequest = I2C_GENERATE_START_WRITE;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Master_ISR_DMA;
+
+    /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = hi2c->XferOptions;
+    }
+
+    /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+    /* Mean Previous state is same as current state */
+    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+    {
+      xferrequest = I2C_NO_STARTSTOP;
+    }
+    else
+    {
+      /* Convert OTHER_xxx XferOptions if any */
+      I2C_ConvertOtherXferOptions(hi2c);
+
+      /* Update xfermode accordingly if no reload is necessary */
+      if (hi2c->XferCount < MAX_NBYTE_SIZE)
+      {
+        xfermode = hi2c->XferOptions;
+      }
+    }
+
+    if (hi2c->XferSize > 0U)
+    {
+      if (hi2c->hdmatx != NULL)
+      {
+        /* Set the I2C DMA transfer complete callback */
+        hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+
+        /* Set the DMA error callback */
+        hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hi2c->hdmatx->XferHalfCpltCallback = NULL;
+        hi2c->hdmatx->XferAbortCallback = NULL;
+
+        /* Enable the DMA stream or channel depends on Instance */
+        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+
+      if (dmaxferstatus == HAL_OK)
+      {
+        /* Send Slave Address and set NBYTES to write */
+        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+
+        /* Update XferCount value */
+        hi2c->XferCount -= hi2c->XferSize;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Note : The I2C interrupts must be enabled after unlocking current process
+                  to avoid the risk of I2C interrupt handle execution before current
+                  process unlock */
+        /* Enable ERR and NACK interrupts */
+        I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+        /* Enable DMA Request */
+        hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Update Transfer ISR function pointer */
+      hi2c->XferISR = I2C_Master_ISR_IT;
+
+      /* Send Slave Address */
+      /* Set NBYTES to write and generate START condition */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+      /* possible to enable all of these */
+      /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  uint32_t xfermode;
+  uint32_t xferrequest = I2C_GENERATE_START_READ;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Master_ISR_IT;
+
+    /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = hi2c->XferOptions;
+    }
+
+    /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+    /* Mean Previous state is same as current state */
+    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+    {
+      xferrequest = I2C_NO_STARTSTOP;
+    }
+    else
+    {
+      /* Convert OTHER_xxx XferOptions if any */
+      I2C_ConvertOtherXferOptions(hi2c);
+
+      /* Update xfermode accordingly if no reload is necessary */
+      if (hi2c->XferCount < MAX_NBYTE_SIZE)
+      {
+        xfermode = hi2c->XferOptions;
+      }
+    }
+
+    /* Send Slave Address and set NBYTES to read */
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  uint32_t xfermode;
+  uint32_t xferrequest = I2C_GENERATE_START_READ;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Master_ISR_DMA;
+
+    /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = hi2c->XferOptions;
+    }
+
+    /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+    /* Mean Previous state is same as current state */
+    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+    {
+      xferrequest = I2C_NO_STARTSTOP;
+    }
+    else
+    {
+      /* Convert OTHER_xxx XferOptions if any */
+      I2C_ConvertOtherXferOptions(hi2c);
+
+      /* Update xfermode accordingly if no reload is necessary */
+      if (hi2c->XferCount < MAX_NBYTE_SIZE)
+      {
+        xfermode = hi2c->XferOptions;
+      }
+    }
+
+    if (hi2c->XferSize > 0U)
+    {
+      if (hi2c->hdmarx != NULL)
+      {
+        /* Set the I2C DMA transfer complete callback */
+        hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+
+        /* Set the DMA error callback */
+        hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hi2c->hdmarx->XferHalfCpltCallback = NULL;
+        hi2c->hdmarx->XferAbortCallback = NULL;
+
+        /* Enable the DMA stream or channel depends on Instance */
+        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+
+      if (dmaxferstatus == HAL_OK)
+      {
+        /* Send Slave Address and set NBYTES to read */
+        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+
+        /* Update XferCount value */
+        hi2c->XferCount -= hi2c->XferSize;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Note : The I2C interrupts must be enabled after unlocking current process
+                  to avoid the risk of I2C interrupt handle execution before current
+                  process unlock */
+        /* Enable ERR and NACK interrupts */
+        I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+        /* Enable DMA Request */
+        hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Update Transfer ISR function pointer */
+      hi2c->XferISR = I2C_Master_ISR_IT;
+
+      /* Send Slave Address */
+      /* Set NBYTES to read and generate START condition */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+      /* possible to enable all of these */
+      /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+    /* and then toggle the HAL slave RX state to TX state */
+    if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+    {
+      /* Disable associated Interrupts */
+      I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+      /* Abort DMA Xfer if any */
+      if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+      {
+        hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+        if (hi2c->hdmarx != NULL)
+        {
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA RX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+          }
+        }
+      }
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Slave_ISR_IT;
+
+    if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+    {
+      /* Clear ADDR flag after prepare the transfer parameters */
+      /* This action will generate an acknowledge to the Master */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
+    /* REnable ADDR interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+
+    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+    /* and then toggle the HAL slave RX state to TX state */
+    if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+    {
+      /* Disable associated Interrupts */
+      I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+      if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+      {
+        /* Abort DMA Xfer if any */
+        if (hi2c->hdmarx != NULL)
+        {
+          hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA RX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+          }
+        }
+      }
+    }
+    else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+    {
+      if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+      {
+        hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+        /* Abort DMA Xfer if any */
+        if (hi2c->hdmatx != NULL)
+        {
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA TX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+          }
+        }
+      }
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Slave_ISR_DMA;
+
+    if (hi2c->hdmatx != NULL)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmatx->XferHalfCpltCallback = NULL;
+      hi2c->hdmatx->XferAbortCallback = NULL;
+
+      /* Enable the DMA stream or channel depends on Instance */
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Update XferCount value */
+      hi2c->XferCount -= hi2c->XferSize;
+
+      /* Reset XferSize */
+      hi2c->XferSize = 0;
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+    {
+      /* Clear ADDR flag after prepare the transfer parameters */
+      /* This action will generate an acknowledge to the Master */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
+    /* Enable ERR, STOP, NACK, ADDR interrupts */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+    /* Enable DMA Request */
+    hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+    /* and then toggle the HAL slave TX state to RX state */
+    if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+    {
+      /* Disable associated Interrupts */
+      I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+      if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+      {
+        hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+        /* Abort DMA Xfer if any */
+        if (hi2c->hdmatx != NULL)
+        {
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA TX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+          }
+        }
+      }
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Slave_ISR_IT;
+
+    if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
+    {
+      /* Clear ADDR flag after prepare the transfer parameters */
+      /* This action will generate an acknowledge to the Master */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
+    /* REnable ADDR interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+    /* and then toggle the HAL slave TX state to RX state */
+    if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+    {
+      /* Disable associated Interrupts */
+      I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+      if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+      {
+        /* Abort DMA Xfer if any */
+        if (hi2c->hdmatx != NULL)
+        {
+          hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA TX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+          }
+        }
+      }
+    }
+    else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+    {
+      if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+      {
+        hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+        /* Abort DMA Xfer if any */
+        if (hi2c->hdmarx != NULL)
+        {
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA RX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+          }
+        }
+      }
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Slave_ISR_DMA;
+
+    if (hi2c->hdmarx != NULL)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmarx->XferHalfCpltCallback = NULL;
+      hi2c->hdmarx->XferAbortCallback = NULL;
+
+      /* Enable the DMA stream or channel depends on Instance */
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Update XferCount value */
+      hi2c->XferCount -= hi2c->XferSize;
+
+      /* Reset XferSize */
+      hi2c->XferSize = 0;
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
+    {
+      /* Clear ADDR flag after prepare the transfer parameters */
+      /* This action will generate an acknowledge to the Master */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
+    /* REnable ADDR interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
+
+    /* Enable DMA Request */
+    hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable the Address listen mode with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
+{
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    hi2c->State = HAL_I2C_STATE_LISTEN;
+    hi2c->XferISR = I2C_Slave_ISR_IT;
+
+    /* Enable the Address Match interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Disable the Address listen mode with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
+{
+  /* Declaration of tmp to prevent undefined behavior of volatile usage */
+  uint32_t tmp;
+
+  /* Disable Address listen mode only if a transfer is not ongoing */
+  if (hi2c->State == HAL_I2C_STATE_LISTEN)
+  {
+    tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
+    hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode = HAL_I2C_MODE_NONE;
+    hi2c->XferISR = NULL;
+
+    /* Disable the Address Match interrupt */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Abort a master I2C IT or DMA process communication with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
+{
+  if (hi2c->Mode == HAL_I2C_MODE_MASTER)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Disable Interrupts and Store Previous state */
+    if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+    {
+      I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+      hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+    }
+    else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+    {
+      I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+      hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+    }
+    else
+    {
+      /* Do nothing */
+    }
+
+    /* Set State at HAL_I2C_STATE_ABORT */
+    hi2c->State = HAL_I2C_STATE_ABORT;
+
+    /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
+    /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
+    I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    /* Wrong usage of abort function */
+    /* This function should be used only in case of abort monitored by master device */
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+
+/**
+  * @brief  This function handles I2C event interrupt request.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
+{
+  /* Get current IT Flags and IT sources value */
+  uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
+  uint32_t itsources = READ_REG(hi2c->Instance->CR1);
+
+  /* I2C events treatment -------------------------------------*/
+  if (hi2c->XferISR != NULL)
+  {
+    hi2c->XferISR(hi2c, itflags, itsources);
+  }
+}
+
+/**
+  * @brief  This function handles I2C error interrupt request.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
+{
+  uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
+  uint32_t itsources = READ_REG(hi2c->Instance->CR1);
+  uint32_t tmperror;
+
+  /* I2C Bus error interrupt occurred ------------------------------------*/
+  if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+  {
+    hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
+
+    /* Clear BERR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
+  }
+
+  /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
+  if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+  {
+    hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
+
+    /* Clear OVR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
+  }
+
+  /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
+  if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+  {
+    hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
+
+    /* Clear ARLO flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
+  }
+
+  /* Store current volatile hi2c->ErrorCode, misra rule */
+  tmperror = hi2c->ErrorCode;
+
+  /* Call the Error Callback in case of Error detected */
+  if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) !=  HAL_I2C_ERROR_NONE)
+  {
+    I2C_ITError(hi2c, tmperror);
+  }
+}
+
+/**
+  * @brief  Master Tx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Master Rx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
+   */
+}
+
+/** @brief  Slave Tx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Slave Rx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Slave Address Match callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
+  * @param  AddrMatchCode Address Match Code
+  * @retval None
+  */
+__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+  UNUSED(TransferDirection);
+  UNUSED(AddrMatchCode);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_AddrCallback() could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Listen Complete callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_ListenCpltCallback() could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Memory Tx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MemTxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Memory Rx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MemRxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  I2C error callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  I2C abort callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_AbortCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
+ *  @brief   Peripheral State, Mode and Error functions
+ *
+@verbatim
+ ===============================================================================
+            ##### Peripheral State, Mode and Error functions #####
+ ===============================================================================
+    [..]
+    This subsection permit to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the I2C handle state.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL state
+  */
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
+{
+  /* Return I2C handle state */
+  return hi2c->State;
+}
+
+/**
+  * @brief  Returns the I2C Master, Slave, Memory or no mode.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval HAL mode
+  */
+HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
+{
+  return hi2c->Mode;
+}
+
+/**
+* @brief  Return the I2C error code.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *              the configuration information for the specified I2C.
+* @retval I2C Error Code
+*/
+uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
+{
+  return hi2c->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  ITFlags Interrupt flags to handle.
+  * @param  ITSources Interrupt sources enabled.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
+{
+  uint16_t devaddress;
+  uint32_t tmpITFlags = ITFlags;
+
+  /* Process Locked */
+  __HAL_LOCK(hi2c);
+
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+  {
+    /* Clear NACK Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    /* Set corresponding Error Code */
+    /* No need to generate STOP, it is automatically done */
+    /* Error callback will be send during stop flag treatment */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+    /* Flush TX register */
+    I2C_Flush_TXDR(hi2c);
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+  {
+    /* Remove RXNE flag on temporary variable as read done */
+    tmpITFlags &= ~I2C_FLAG_RXNE;
+
+    /* Read data from RXDR */
+    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    hi2c->XferSize--;
+    hi2c->XferCount--;
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+  {
+    /* Write data to TXDR */
+    hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    hi2c->XferSize--;
+    hi2c->XferCount--;
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+  {
+    if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+    {
+      devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
+
+      if (hi2c->XferCount > MAX_NBYTE_SIZE)
+      {
+        hi2c->XferSize = MAX_NBYTE_SIZE;
+        I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+      }
+      else
+      {
+        hi2c->XferSize = hi2c->XferCount;
+        if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+        {
+          I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP);
+        }
+        else
+        {
+          I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+        }
+      }
+    }
+    else
+    {
+      /* Call TxCpltCallback() if no stop mode is set */
+      if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+      {
+        /* Call I2C Master Sequential complete process */
+        I2C_ITMasterSeqCplt(hi2c);
+      }
+      else
+      {
+        /* Wrong size Status regarding TCR flag event */
+        /* Call the corresponding callback to inform upper layer of End of Transfer */
+        I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+      }
+    }
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+  {
+    if (hi2c->XferCount == 0U)
+    {
+      if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+      {
+        /* Generate a stop condition in case of no transfer option */
+        if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
+        {
+          /* Generate Stop */
+          hi2c->Instance->CR2 |= I2C_CR2_STOP;
+        }
+        else
+        {
+          /* Call I2C Master Sequential complete process */
+          I2C_ITMasterSeqCplt(hi2c);
+        }
+      }
+    }
+    else
+    {
+      /* Wrong size Status regarding TC flag event */
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+      I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+    }
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+  {
+    /* Call I2C Master complete process */
+    I2C_ITMasterCplt(hi2c, tmpITFlags);
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  ITFlags Interrupt flags to handle.
+  * @param  ITSources Interrupt sources enabled.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
+{
+  uint32_t tmpoptions = hi2c->XferOptions;
+  uint32_t tmpITFlags = ITFlags;
+
+  /* Process locked */
+  __HAL_LOCK(hi2c);
+
+  /* Check if STOPF is set */
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+  {
+    /* Call I2C Slave complete process */
+    I2C_ITSlaveCplt(hi2c, tmpITFlags);
+  }
+
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+  {
+    /* Check that I2C transfer finished */
+    /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+    /* Mean XferCount == 0*/
+    /* So clear Flag NACKF only */
+    if (hi2c->XferCount == 0U)
+    {
+      if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */
+      {
+        /* Call I2C Listen complete process */
+        I2C_ITListenCplt(hi2c, tmpITFlags);
+      }
+      else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
+      {
+        /* Clear NACK Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+        /* Flush TX register */
+        I2C_Flush_TXDR(hi2c);
+
+        /* Last Byte is Transmitted */
+        /* Call I2C Slave Sequential complete process */
+        I2C_ITSlaveSeqCplt(hi2c);
+      }
+      else
+      {
+        /* Clear NACK Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+      }
+    }
+    else
+    {
+      /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
+      /* Clear NACK Flag */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+      /* Set ErrorCode corresponding to a Non-Acknowledge */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+      if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
+      {
+        /* Call the corresponding callback to inform upper layer of End of Transfer */
+        I2C_ITError(hi2c, hi2c->ErrorCode);
+      }
+    }
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+  {
+    if (hi2c->XferCount > 0U)
+    {
+      /* Read data from RXDR */
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+    }
+
+    if ((hi2c->XferCount == 0U) && \
+        (tmpoptions != I2C_NO_OPTION_FRAME))
+    {
+      /* Call I2C Slave Sequential complete process */
+      I2C_ITSlaveSeqCplt(hi2c);
+    }
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
+  {
+    I2C_ITAddrCplt(hi2c, tmpITFlags);
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+  {
+    /* Write data to TXDR only if XferCount not reach "0" */
+    /* A TXIS flag can be set, during STOP treatment      */
+    /* Check if all Datas have already been sent */
+    /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
+    if (hi2c->XferCount > 0U)
+    {
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+    }
+    else
+    {
+      if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
+      {
+        /* Last Byte is Transmitted */
+        /* Call I2C Slave Sequential complete process */
+        I2C_ITSlaveSeqCplt(hi2c);
+      }
+    }
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  ITFlags Interrupt flags to handle.
+  * @param  ITSources Interrupt sources enabled.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
+{
+  uint16_t devaddress;
+  uint32_t xfermode;
+
+  /* Process Locked */
+  __HAL_LOCK(hi2c);
+
+  if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+  {
+    /* Clear NACK Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    /* Set corresponding Error Code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+    /* No need to generate STOP, it is automatically done */
+    /* But enable STOP interrupt, to treat it */
+    /* Error callback will be send during stop flag treatment */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+
+    /* Flush TX register */
+    I2C_Flush_TXDR(hi2c);
+  }
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+  {
+    /* Disable TC interrupt */
+    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
+
+    if (hi2c->XferCount != 0U)
+    {
+      /* Recover Slave address */
+      devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
+
+      /* Prepare the new XferSize to transfer */
+      if (hi2c->XferCount > MAX_NBYTE_SIZE)
+      {
+        hi2c->XferSize = MAX_NBYTE_SIZE;
+        xfermode = I2C_RELOAD_MODE;
+      }
+      else
+      {
+        hi2c->XferSize = hi2c->XferCount;
+        if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+        {
+          xfermode = hi2c->XferOptions;
+        }
+        else
+        {
+          xfermode = I2C_AUTOEND_MODE;
+        }
+      }
+
+      /* Set the new XferSize in Nbytes register */
+      I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+
+      /* Update XferCount value */
+      hi2c->XferCount -= hi2c->XferSize;
+
+      /* Enable DMA Request */
+      if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+      {
+        hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+      }
+      else
+      {
+        hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+      }
+    }
+    else
+    {
+      /* Call TxCpltCallback() if no stop mode is set */
+      if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+      {
+        /* Call I2C Master Sequential complete process */
+        I2C_ITMasterSeqCplt(hi2c);
+      }
+      else
+      {
+        /* Wrong size Status regarding TCR flag event */
+        /* Call the corresponding callback to inform upper layer of End of Transfer */
+        I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+      }
+    }
+  }
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+  {
+    if (hi2c->XferCount == 0U)
+    {
+      if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+      {
+        /* Generate a stop condition in case of no transfer option */
+        if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
+        {
+          /* Generate Stop */
+          hi2c->Instance->CR2 |= I2C_CR2_STOP;
+        }
+        else
+        {
+          /* Call I2C Master Sequential complete process */
+          I2C_ITMasterSeqCplt(hi2c);
+        }
+      }
+    }
+    else
+    {
+      /* Wrong size Status regarding TC flag event */
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+      I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+    }
+  }
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+  {
+    /* Call I2C Master complete process */
+    I2C_ITMasterCplt(hi2c, ITFlags);
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  ITFlags Interrupt flags to handle.
+  * @param  ITSources Interrupt sources enabled.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
+{
+  uint32_t tmpoptions = hi2c->XferOptions;
+  uint32_t treatdmanack = 0U;
+  HAL_I2C_StateTypeDef tmpstate;
+
+  /* Process locked */
+  __HAL_LOCK(hi2c);
+
+  /* Check if STOPF is set */
+  if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+  {
+    /* Call I2C Slave complete process */
+    I2C_ITSlaveCplt(hi2c, ITFlags);
+  }
+
+  if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+  {
+    /* Check that I2C transfer finished */
+    /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+    /* Mean XferCount == 0 */
+    /* So clear Flag NACKF only */
+    if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
+        (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))
+    {
+      /* Split check of hdmarx, for MISRA compliance */
+      if (hi2c->hdmarx != NULL)
+      {
+        if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)
+        {
+          if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U)
+          {
+            treatdmanack = 1U;
+          }
+        }
+      }
+
+      /* Split check of hdmatx, for MISRA compliance  */
+      if (hi2c->hdmatx != NULL)
+      {
+        if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)
+        {
+          if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U)
+          {
+            treatdmanack = 1U;
+          }
+        }
+      }
+
+      if (treatdmanack == 1U)
+      {
+        if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */
+        {
+          /* Call I2C Listen complete process */
+          I2C_ITListenCplt(hi2c, ITFlags);
+        }
+        else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
+        {
+          /* Clear NACK Flag */
+          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+          /* Flush TX register */
+          I2C_Flush_TXDR(hi2c);
+
+          /* Last Byte is Transmitted */
+          /* Call I2C Slave Sequential complete process */
+          I2C_ITSlaveSeqCplt(hi2c);
+        }
+        else
+        {
+          /* Clear NACK Flag */
+          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+        }
+      }
+      else
+      {
+        /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
+        /* Clear NACK Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+        /* Set ErrorCode corresponding to a Non-Acknowledge */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+        /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */
+        tmpstate = hi2c->State;
+
+        if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
+        {
+          if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
+          {
+            hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+          }
+          else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+          {
+            hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+          }
+          else
+          {
+            /* Do nothing */
+          }
+
+          /* Call the corresponding callback to inform upper layer of End of Transfer */
+          I2C_ITError(hi2c, hi2c->ErrorCode);
+        }
+      }
+    }
+    else
+    {
+      /* Only Clear NACK Flag, no DMA treatment is pending */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+    }
+  }
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
+  {
+    I2C_ITAddrCplt(hi2c, ITFlags);
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Master sends target device address followed by internal memory address for write request.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
+{
+  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
+
+  /* Wait until TXIS flag is set */
+  if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* If Memory address size is 8Bit */
+  if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
+  {
+    /* Send Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+  }
+  /* If Memory address size is 16Bit */
+  else
+  {
+    /* Send MSB of Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+
+    /* Wait until TXIS flag is set */
+    if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Send LSB of Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+  }
+
+  /* Wait until TCR flag is set */
+  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Master sends target device address followed by internal memory address for read request.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
+{
+  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
+
+  /* Wait until TXIS flag is set */
+  if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* If Memory address size is 8Bit */
+  if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
+  {
+    /* Send Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+  }
+  /* If Memory address size is 16Bit */
+  else
+  {
+    /* Send MSB of Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+
+    /* Wait until TXIS flag is set */
+    if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Send LSB of Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+  }
+
+  /* Wait until TC flag is set */
+  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  I2C Address complete process callback.
+  * @param  hi2c I2C handle.
+  * @param  ITFlags Interrupt flags to handle.
+  * @retval None
+  */
+static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+  uint8_t transferdirection;
+  uint16_t slaveaddrcode;
+  uint16_t ownadd1code;
+  uint16_t ownadd2code;
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(ITFlags);
+
+  /* In case of Listen state, need to inform upper layer of address match code event */
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    transferdirection = I2C_GET_DIR(hi2c);
+    slaveaddrcode     = I2C_GET_ADDR_MATCH(hi2c);
+    ownadd1code       = I2C_GET_OWN_ADDRESS1(hi2c);
+    ownadd2code       = I2C_GET_OWN_ADDRESS2(hi2c);
+
+    /* If 10bits addressing mode is selected */
+    if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+    {
+      if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK))
+      {
+        slaveaddrcode = ownadd1code;
+        hi2c->AddrEventCount++;
+        if (hi2c->AddrEventCount == 2U)
+        {
+          /* Reset Address Event counter */
+          hi2c->AddrEventCount = 0U;
+
+          /* Clear ADDR flag */
+          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2c);
+
+          /* Call Slave Addr callback */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+          hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#else
+          HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+        }
+      }
+      else
+      {
+        slaveaddrcode = ownadd2code;
+
+        /* Disable ADDR Interrupts */
+        I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Call Slave Addr callback */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+        hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#else
+        HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+      }
+    }
+    /* else 7 bits addressing mode is selected */
+    else
+    {
+      /* Disable ADDR Interrupts */
+      I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Call Slave Addr callback */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#else
+      HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+  }
+  /* Else clear address flag only */
+  else
+  {
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+  }
+}
+
+/**
+  * @brief  I2C Master sequential complete process.
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c)
+{
+  /* Reset I2C handle mode */
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+
+  /* No Generate Stop, to permit restart mode */
+  /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
+  if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+  {
+    hi2c->State         = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+    hi2c->XferISR       = NULL;
+
+    /* Disable Interrupts */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->MasterTxCpltCallback(hi2c);
+#else
+    HAL_I2C_MasterTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+  /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
+  else
+  {
+    hi2c->State         = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+    hi2c->XferISR       = NULL;
+
+    /* Disable Interrupts */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->MasterRxCpltCallback(hi2c);
+#else
+    HAL_I2C_MasterRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief  I2C Slave sequential complete process.
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
+{
+  uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
+
+  /* Reset I2C handle mode */
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+
+  /* If a DMA is ongoing, Update handle size context */
+  if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+  }
+  else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+  }
+  else
+  {
+    /* Do nothing */
+  }
+
+  if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+  {
+    /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
+    hi2c->State         = HAL_I2C_STATE_LISTEN;
+    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+
+    /* Disable Interrupts */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->SlaveTxCpltCallback(hi2c);
+#else
+    HAL_I2C_SlaveTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+
+  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+  {
+    /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
+    hi2c->State         = HAL_I2C_STATE_LISTEN;
+    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+
+    /* Disable Interrupts */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->SlaveRxCpltCallback(hi2c);
+#else
+    HAL_I2C_SlaveRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+}
+
+/**
+  * @brief  I2C Master complete process.
+  * @param  hi2c I2C handle.
+  * @param  ITFlags Interrupt flags to handle.
+  * @retval None
+  */
+static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+  uint32_t tmperror;
+  uint32_t tmpITFlags = ITFlags;
+  uint32_t tmp;
+
+  /* Clear STOP Flag */
+  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+  /* Disable Interrupts and Store Previous state */
+  if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+  {
+    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+    hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+  }
+  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+  {
+    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+    hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+  }
+  else
+  {
+    /* Do nothing */
+  }
+
+  /* Clear Configuration Register 2 */
+  I2C_RESET_CR2(hi2c);
+
+  /* Reset handle parameters */
+  hi2c->XferISR       = NULL;
+  hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
+
+  if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET)
+  {
+    /* Clear NACK Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    /* Set acknowledge error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+  }
+
+  /* Fetch Last receive data if any */
+  if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET))
+  {
+    /* Read data from RXDR */
+    tmp = (uint8_t)hi2c->Instance->RXDR;
+
+    UNUSED(tmp);
+  }
+
+  /* Flush TX register */
+  I2C_Flush_TXDR(hi2c);
+
+  /* Store current volatile hi2c->ErrorCode, misra rule */
+  tmperror = hi2c->ErrorCode;
+
+  /* Call the corresponding callback to inform upper layer of End of Transfer */
+  if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE))
+  {
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    I2C_ITError(hi2c, hi2c->ErrorCode);
+  }
+  /* hi2c->State == HAL_I2C_STATE_BUSY_TX */
+  else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    if (hi2c->Mode == HAL_I2C_MODE_MEM)
+    {
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->MemTxCpltCallback(hi2c);
+#else
+      HAL_I2C_MemTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+    else
+    {
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->MasterTxCpltCallback(hi2c);
+#else
+      HAL_I2C_MasterTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+  }
+  /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
+  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    if (hi2c->Mode == HAL_I2C_MODE_MEM)
+    {
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->MemRxCpltCallback(hi2c);
+#else
+      HAL_I2C_MemRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+    else
+    {
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->MasterRxCpltCallback(hi2c);
+#else
+      HAL_I2C_MasterRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+}
+
+/**
+  * @brief  I2C Slave complete process.
+  * @param  hi2c I2C handle.
+  * @param  ITFlags Interrupt flags to handle.
+  * @retval None
+  */
+static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+  uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
+  uint32_t tmpITFlags = ITFlags;
+  HAL_I2C_StateTypeDef tmpstate = hi2c->State;
+
+  /* Clear STOP Flag */
+  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+  /* Disable Interrupts and Store Previous state */
+  if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
+  {
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+  }
+  else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+  {
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
+    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+  }
+  else
+  {
+    /* Do nothing */
+  }
+
+  /* Disable Address Acknowledge */
+  hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+  /* Clear Configuration Register 2 */
+  I2C_RESET_CR2(hi2c);
+
+  /* Flush TX register */
+  I2C_Flush_TXDR(hi2c);
+
+  /* If a DMA is ongoing, Update handle size context */
+  if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+    if (hi2c->hdmatx != NULL)
+    {
+      hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx);
+    }
+  }
+  else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+    if (hi2c->hdmarx != NULL)
+    {
+      hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx);
+    }
+  }
+  else
+  {
+    /* Do nothing */
+  }
+
+  /* Store Last receive data if any */
+  if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)
+  {
+    /* Remove RXNE flag on temporary variable as read done */
+    tmpITFlags &= ~I2C_FLAG_RXNE;
+
+    /* Read data from RXDR */
+    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    if ((hi2c->XferSize > 0U))
+    {
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+    }
+  }
+
+  /* All data are not transferred, so set error code accordingly */
+  if (hi2c->XferCount != 0U)
+  {
+    /* Set ErrorCode corresponding to a Non-Acknowledge */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+  }
+
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+  hi2c->XferISR = NULL;
+
+  if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+  {
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    I2C_ITError(hi2c, hi2c->ErrorCode);
+
+    /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+    if (hi2c->State == HAL_I2C_STATE_LISTEN)
+    {
+      /* Call I2C Listen complete process */
+      I2C_ITListenCplt(hi2c, tmpITFlags);
+    }
+  }
+  else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+  {
+    /* Call the Sequential Complete callback, to inform upper layer of the end of Tranfer */
+    I2C_ITSlaveSeqCplt(hi2c);
+
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->ListenCpltCallback(hi2c);
+#else
+    HAL_I2C_ListenCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+  /* Call the corresponding callback to inform upper layer of End of Transfer */
+  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->SlaveRxCpltCallback(hi2c);
+#else
+    HAL_I2C_SlaveRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->SlaveTxCpltCallback(hi2c);
+#else
+    HAL_I2C_SlaveTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief  I2C Listen complete process.
+  * @param  hi2c I2C handle.
+  * @param  ITFlags Interrupt flags to handle.
+  * @retval None
+  */
+static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+  /* Reset handle parameters */
+  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+  hi2c->PreviousState = I2C_STATE_NONE;
+  hi2c->State = HAL_I2C_STATE_READY;
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+  hi2c->XferISR = NULL;
+
+  /* Store Last receive data if any */
+  if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET)
+  {
+    /* Read data from RXDR */
+    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    if ((hi2c->XferSize > 0U))
+    {
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+
+      /* Set ErrorCode corresponding to a Non-Acknowledge */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+    }
+  }
+
+  /* Disable all Interrupts*/
+  I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
+
+  /* Clear NACK Flag */
+  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+  hi2c->ListenCpltCallback(hi2c);
+#else
+  HAL_I2C_ListenCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  I2C interrupts error process.
+  * @param  hi2c I2C handle.
+  * @param  ErrorCode Error code to handle.
+  * @retval None
+  */
+static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
+{
+  HAL_I2C_StateTypeDef tmpstate = hi2c->State;
+  uint32_t tmppreviousstate;
+
+  /* Reset handle parameters */
+  hi2c->Mode          = HAL_I2C_MODE_NONE;
+  hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
+  hi2c->XferCount     = 0U;
+
+  /* Set new error code */
+  hi2c->ErrorCode |= ErrorCode;
+
+  /* Disable Interrupts */
+  if ((tmpstate == HAL_I2C_STATE_LISTEN)         ||
+      (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
+      (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+  {
+    /* Disable all interrupts, except interrupts related to LISTEN state */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
+
+    /* keep HAL_I2C_STATE_LISTEN if set */
+    hi2c->State         = HAL_I2C_STATE_LISTEN;
+    hi2c->XferISR       = I2C_Slave_ISR_IT;
+  }
+  else
+  {
+    /* Disable all interrupts */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
+
+    /* If state is an abort treatment on goind, don't change state */
+    /* This change will be do later */
+    if (hi2c->State != HAL_I2C_STATE_ABORT)
+    {
+      /* Set HAL_I2C_STATE_READY */
+      hi2c->State         = HAL_I2C_STATE_READY;
+    }
+    hi2c->XferISR       = NULL;
+  }
+
+  /* Abort DMA TX transfer if any */
+  tmppreviousstate = hi2c->PreviousState;
+  if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
+  {
+    if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+    {
+      hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+    }
+
+    if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
+    {
+      /* Set the I2C DMA Abort callback :
+       will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+      hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Abort DMA TX */
+      if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+      {
+        /* Call Directly XferAbortCallback function in case of error */
+        hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+      }
+    }
+    else
+    {
+      I2C_TreatErrorCallback(hi2c);
+    }
+  }
+  /* Abort DMA RX transfer if any */
+  else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
+  {
+    if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+    {
+      hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+    }
+
+    if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
+    {
+      /* Set the I2C DMA Abort callback :
+        will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+      hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Abort DMA RX */
+      if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+      {
+        /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
+        hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+      }
+    }
+    else
+    {
+      I2C_TreatErrorCallback(hi2c);
+    }
+  }
+  else
+  {
+    I2C_TreatErrorCallback(hi2c);
+  }
+}
+
+/**
+  * @brief  I2C Error callback treatment.
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c)
+{
+  if (hi2c->State == HAL_I2C_STATE_ABORT)
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->AbortCpltCallback(hi2c);
+#else
+    HAL_I2C_AbortCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->ErrorCallback(hi2c);
+#else
+    HAL_I2C_ErrorCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief  I2C Tx data register flush process.
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
+{
+  /* If a pending TXIS flag is set */
+  /* Write a dummy data in TXDR to clear it */
+  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
+  {
+    hi2c->Instance->TXDR = 0x00U;
+  }
+
+  /* Flush TX register if not empty */
+  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
+  {
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
+  }
+}
+
+/**
+  * @brief  DMA I2C master transmit process complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+
+  /* Disable DMA Request */
+  hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+  /* If last transfer, enable STOP interrupt */
+  if (hi2c->XferCount == 0U)
+  {
+    /* Enable STOP interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+  }
+  /* else prepare a new DMA transfer and enable TCReload interrupt */
+  else
+  {
+    /* Update Buffer pointer */
+    hi2c->pBuffPtr += hi2c->XferSize;
+
+    /* Set the XferSize to transfer */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+    }
+
+    /* Enable the DMA stream or channel depends on Instance */
+    if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize) != HAL_OK)
+    {
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+      I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+    }
+    else
+    {
+      /* Enable TC interrupts */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
+    }
+  }
+}
+
+/**
+  * @brief  DMA I2C slave transmit process complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+  uint32_t tmpoptions = hi2c->XferOptions;
+
+  if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+    /* Last Byte is Transmitted */
+    /* Call I2C Slave Sequential complete process */
+    I2C_ITSlaveSeqCplt(hi2c);
+  }
+  else
+  {
+    /* No specific action, Master fully manage the generation of STOP condition */
+    /* Mean that this generation can arrive at any time, at the end or during DMA process */
+    /* So STOP condition should be manage through Interrupt treatment */
+  }
+}
+
+/**
+  * @brief DMA I2C master receive process complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+
+  /* Disable DMA Request */
+  hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+  /* If last transfer, enable STOP interrupt */
+  if (hi2c->XferCount == 0U)
+  {
+    /* Enable STOP interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+  }
+  /* else prepare a new DMA transfer and enable TCReload interrupt */
+  else
+  {
+    /* Update Buffer pointer */
+    hi2c->pBuffPtr += hi2c->XferSize;
+
+    /* Set the XferSize to transfer */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+    }
+
+    /* Enable the DMA stream or channel depends on Instance */
+    if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize) != HAL_OK)
+    {
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+      I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+    }
+    else
+    {
+      /* Enable TC interrupts */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
+    }
+  }
+}
+
+/**
+  * @brief  DMA I2C slave receive process complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+  uint32_t tmpoptions = hi2c->XferOptions;
+
+  if ((__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) && \
+      (tmpoptions != I2C_NO_OPTION_FRAME))
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+    /* Call I2C Slave Sequential complete process */
+    I2C_ITSlaveSeqCplt(hi2c);
+  }
+  else
+  {
+    /* No specific action, Master fully manage the generation of STOP condition */
+    /* Mean that this generation can arrive at any time, at the end or during DMA process */
+    /* So STOP condition should be manage through Interrupt treatment */
+  }
+}
+
+/**
+  * @brief  DMA I2C communication error callback.
+  * @param hdma DMA handle
+  * @retval None
+  */
+static void I2C_DMAError(DMA_HandleTypeDef *hdma)
+{
+  uint32_t treatdmaerror = 0U;
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+
+  if (hi2c->hdmatx != NULL)
+  {
+    if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U)
+    {
+      treatdmaerror = 1U;
+    }
+  }
+
+  if (hi2c->hdmarx != NULL)
+  {
+    if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U)
+    {
+      treatdmaerror = 1U;
+    }
+  }
+
+  /* Check if a FIFO error is detected, if true normal use case, so no specific action to perform */
+  if (!((HAL_DMA_GetError(hdma) == HAL_DMA_ERROR_FE)) && (treatdmaerror != 0U))
+  {
+    /* Disable Acknowledge */
+    hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+  }
+}
+
+/**
+  * @brief DMA I2C communication abort callback
+  *        (To be called at end of DMA Abort procedure).
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
+{
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+
+  /* Reset AbortCpltCallback */
+  if (hi2c->hdmatx != NULL)
+  {
+    hi2c->hdmatx->XferAbortCallback = NULL;
+  }
+  if (hi2c->hdmarx != NULL)
+  {
+    hi2c->hdmarx->XferAbortCallback = NULL;
+  }
+
+  I2C_TreatErrorCallback(hi2c);
+}
+
+/**
+  * @brief  This function handles I2C Communication Timeout.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Flag Specifies the I2C flag to check.
+  * @param  Status The new Flag status (SET or RESET).
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
+{
+  while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
+  {
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+      {
+        hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+        hi2c->State = HAL_I2C_STATE_READY;
+        hi2c->Mode = HAL_I2C_MODE_NONE;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        return HAL_ERROR;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles I2C Communication Timeout for specific usage of TXIS flag.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+{
+  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
+  {
+    /* Check if a NACK is detected */
+    if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+      {
+        hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+        hi2c->State = HAL_I2C_STATE_READY;
+        hi2c->Mode = HAL_I2C_MODE_NONE;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles I2C Communication Timeout for specific usage of STOP flag.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+{
+  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+  {
+    /* Check if a NACK is detected */
+    if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Check for the Timeout */
+    if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+    {
+      hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+      hi2c->State = HAL_I2C_STATE_READY;
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles I2C Communication Timeout for specific usage of RXNE flag.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+{
+  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
+  {
+    /* Check if a NACK is detected */
+    if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Check if a STOPF is detected */
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
+    {
+      /* Check if an RXNE is pending */
+      /* Store Last receive data if any */
+      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U))
+      {
+        /* Return HAL_OK */
+        /* The Reading of data from RXDR will be done in caller function */
+        return HAL_OK;
+      }
+      else
+      {
+        /* Clear STOP Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+        /* Clear Configuration Register 2 */
+        I2C_RESET_CR2(hi2c);
+
+        hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+        hi2c->State = HAL_I2C_STATE_READY;
+        hi2c->Mode = HAL_I2C_MODE_NONE;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+
+    /* Check for the Timeout */
+    if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+    {
+      hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+      hi2c->State = HAL_I2C_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles Acknowledge failed detection during an I2C Communication.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+{
+  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+  {
+    /* Wait until STOP Flag is reset */
+    /* AutoEnd should be initiate after AF */
+    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+    {
+      /* Check for the Timeout */
+      if (Timeout != HAL_MAX_DELAY)
+      {
+        if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+        {
+          hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+          hi2c->State = HAL_I2C_STATE_READY;
+          hi2c->Mode = HAL_I2C_MODE_NONE;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2c);
+
+          return HAL_ERROR;
+        }
+      }
+    }
+
+    /* Clear NACKF Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    /* Clear STOP Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Flush TX register */
+    I2C_Flush_TXDR(hi2c);
+
+    /* Clear Configuration Register 2 */
+    I2C_RESET_CR2(hi2c);
+
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_ERROR;
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
+  * @param  hi2c I2C handle.
+  * @param  DevAddress Specifies the slave address to be programmed.
+  * @param  Size Specifies the number of bytes to be programmed.
+  *   This parameter must be a value between 0 and 255.
+  * @param  Mode New state of the I2C START condition generation.
+  *   This parameter can be one of the following values:
+  *     @arg @ref I2C_RELOAD_MODE Enable Reload mode .
+  *     @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.
+  *     @arg @ref I2C_SOFTEND_MODE Enable Software end mode.
+  * @param  Request New state of the I2C START condition generation.
+  *   This parameter can be one of the following values:
+  *     @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.
+  *     @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
+  *     @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
+  *     @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
+  * @retval None
+  */
+static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  assert_param(IS_TRANSFER_MODE(Mode));
+  assert_param(IS_TRANSFER_REQUEST(Request));
+
+  /* update CR2 register */
+  MODIFY_REG(hi2c->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \
+             (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
+}
+
+/**
+  * @brief  Manage the enabling of Interrupts.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
+  * @retval None
+  */
+static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
+{
+  uint32_t tmpisr = 0U;
+
+  if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \
+      (hi2c->XferISR == I2C_Slave_ISR_DMA))
+  {
+    if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+    {
+      /* Enable ERR, STOP, NACK and ADDR interrupts */
+      tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+    }
+
+    if (InterruptRequest == I2C_XFER_ERROR_IT)
+    {
+      /* Enable ERR and NACK interrupts */
+      tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
+    }
+
+    if (InterruptRequest == I2C_XFER_CPLT_IT)
+    {
+      /* Enable STOP interrupts */
+      tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
+    }
+
+    if (InterruptRequest == I2C_XFER_RELOAD_IT)
+    {
+      /* Enable TC interrupts */
+      tmpisr |= I2C_IT_TCI;
+    }
+  }
+  else
+  {
+    if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+    {
+      /* Enable ERR, STOP, NACK, and ADDR interrupts */
+      tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+    }
+
+    if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
+    {
+      /* Enable ERR, TC, STOP, NACK and RXI interrupts */
+      tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
+    }
+
+    if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
+    {
+      /* Enable ERR, TC, STOP, NACK and TXI interrupts */
+      tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
+    }
+
+    if (InterruptRequest == I2C_XFER_CPLT_IT)
+    {
+      /* Enable STOP interrupts */
+      tmpisr |= I2C_IT_STOPI;
+    }
+  }
+
+  /* Enable interrupts only at the end */
+  /* to avoid the risk of I2C interrupt handle execution before */
+  /* all interrupts requested done */
+  __HAL_I2C_ENABLE_IT(hi2c, tmpisr);
+}
+
+/**
+  * @brief  Manage the disabling of Interrupts.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
+  * @retval None
+  */
+static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
+{
+  uint32_t tmpisr = 0U;
+
+  if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
+  {
+    /* Disable TC and TXI interrupts */
+    tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
+
+    if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
+    {
+      /* Disable NACK and STOP interrupts */
+      tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+    }
+  }
+
+  if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
+  {
+    /* Disable TC and RXI interrupts */
+    tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
+
+    if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
+    {
+      /* Disable NACK and STOP interrupts */
+      tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+    }
+  }
+
+  if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+  {
+    /* Disable ADDR, NACK and STOP interrupts */
+    tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+  }
+
+  if (InterruptRequest == I2C_XFER_ERROR_IT)
+  {
+    /* Enable ERR and NACK interrupts */
+    tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
+  }
+
+  if (InterruptRequest == I2C_XFER_CPLT_IT)
+  {
+    /* Enable STOP interrupts */
+    tmpisr |= I2C_IT_STOPI;
+  }
+
+  if (InterruptRequest == I2C_XFER_RELOAD_IT)
+  {
+    /* Enable TC interrupts */
+    tmpisr |= I2C_IT_TCI;
+  }
+
+  /* Disable interrupts only at the end */
+  /* to avoid a breaking situation like at "t" time */
+  /* all disable interrupts request are not done */
+  __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
+}
+
+/**
+  * @brief  Convert I2Cx OTHER_xxx XferOptions to functionnal XferOptions.
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
+{
+  /* if user set XferOptions to I2C_OTHER_FRAME            */
+  /* it request implicitly to generate a restart condition */
+  /* set XferOptions to I2C_FIRST_FRAME                    */
+  if (hi2c->XferOptions == I2C_OTHER_FRAME)
+  {
+    hi2c->XferOptions = I2C_FIRST_FRAME;
+  }
+  /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
+  /* it request implicitly to generate a restart condition    */
+  /* then generate a stop condition at the end of transfer    */
+  /* set XferOptions to I2C_FIRST_AND_LAST_FRAME              */
+  else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
+  {
+    hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_I2C_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c
new file mode 100644
index 00000000..ea50ce31
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c
@@ -0,0 +1,339 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_i2c_ex.c
+  * @author  MCD Application Team
+  * @brief   I2C Extended HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of I2C Extended peripheral:
+  *           + Extended features functions
+  *
+  @verbatim
+  ==============================================================================
+               ##### I2C peripheral Extended features  #####
+  ==============================================================================
+
+  [..] Comparing to other previous devices, the I2C interface for STM32H7xx
+       devices contains the following additional features
+
+       (+) Possibility to disable or enable Analog Noise Filter
+       (+) Use of a configured Digital Noise Filter
+       (+) Disable or enable wakeup from Stop mode(s)
+       (+) Disable or enable Fast Mode Plus
+
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..] This driver provides functions to configure Noise Filter and Wake Up Feature
+    (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
+    (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
+    (#) Configure the enable or disable of I2C Wake Up Mode using the functions :
+          (++) HAL_I2CEx_EnableWakeUp()
+          (++) HAL_I2CEx_DisableWakeUp()
+    (#) Configure the enable or disable of fast mode plus driving capability using the functions :
+          (++) HAL_I2CEx_EnableFastModePlus()
+          (++) HAL_I2CEx_DisableFastModePlus()
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup I2CEx I2CEx
+  * @brief I2C Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions
+  * @brief    Extended features functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### Extended features functions #####
+ ===============================================================================
+    [..] This section provides functions allowing to:
+      (+) Configure Noise Filters
+      (+) Configure Wake Up Feature
+      (+) Configure Fast Mode Plus
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure I2C Analog noise filter.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2Cx peripheral.
+  * @param  AnalogFilter New state of the Analog filter.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+
+    /* Disable the selected I2C peripheral */
+    __HAL_I2C_DISABLE(hi2c);
+
+    /* Reset I2Cx ANOFF bit */
+    hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
+
+    /* Set analog filter bit*/
+    hi2c->Instance->CR1 |= AnalogFilter;
+
+    __HAL_I2C_ENABLE(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Configure I2C Digital noise filter.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2Cx peripheral.
+  * @param  DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
+{
+  uint32_t tmpreg;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+
+    /* Disable the selected I2C peripheral */
+    __HAL_I2C_DISABLE(hi2c);
+
+    /* Get the old register value */
+    tmpreg = hi2c->Instance->CR1;
+
+    /* Reset I2Cx DNF bits [11:8] */
+    tmpreg &= ~(I2C_CR1_DNF);
+
+    /* Set I2Cx DNF coefficient */
+    tmpreg |= DigitalFilter << 8U;
+
+    /* Store the new register value */
+    hi2c->Instance->CR1 = tmpreg;
+
+    __HAL_I2C_ENABLE(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Enable I2C wakeup from Stop mode(s).
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2Cx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+
+    /* Disable the selected I2C peripheral */
+    __HAL_I2C_DISABLE(hi2c);
+
+    /* Enable wakeup from stop mode */
+    hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
+
+    __HAL_I2C_ENABLE(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Disable I2C wakeup from Stop mode(s).
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2Cx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+
+    /* Disable the selected I2C peripheral */
+    __HAL_I2C_DISABLE(hi2c);
+
+    /* Enable wakeup from stop mode */
+    hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
+
+    __HAL_I2C_ENABLE(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Enable the I2C fast mode plus driving capability.
+  * @param ConfigFastModePlus Selects the pin.
+  *   This parameter can be one of the @ref I2CEx_FastModePlus values
+  * @note  For I2C1, fast mode plus driving capability can be enabled on all selected
+  *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
+  *        on each one of the following pins PB6, PB7, PB8 and PB9.
+  * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
+  *        can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
+  * @note  For all I2C2 pins fast mode plus driving capability can be enabled
+  *        only by using I2C_FASTMODEPLUS_I2C2 parameter.
+  * @note  For all I2C3 pins fast mode plus driving capability can be enabled
+  *        only by using I2C_FASTMODEPLUS_I2C3 parameter.
+  * @note  For all I2C4 pins fast mode plus driving capability can be enabled
+  *        only by using I2C_FASTMODEPLUS_I2C4 parameter.
+  * @retval None
+  */
+void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
+{
+  /* Check the parameter */
+  assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
+
+  /* Enable SYSCFG clock */
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+  /* Enable fast mode plus driving capability for selected pin */
+  SET_BIT(SYSCFG->PMCR, (uint32_t)ConfigFastModePlus);
+}
+
+/**
+  * @brief Disable the I2C fast mode plus driving capability.
+  * @param ConfigFastModePlus Selects the pin.
+  *   This parameter can be one of the @ref I2CEx_FastModePlus values
+  * @note  For I2C1, fast mode plus driving capability can be disabled on all selected
+  *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
+  *        on each one of the following pins PB6, PB7, PB8 and PB9.
+  * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
+  *        can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
+  * @note  For all I2C2 pins fast mode plus driving capability can be disabled
+  *        only by using I2C_FASTMODEPLUS_I2C2 parameter.
+  * @note  For all I2C3 pins fast mode plus driving capability can be disabled
+  *        only by using I2C_FASTMODEPLUS_I2C3 parameter.
+  * @note  For all I2C4 pins fast mode plus driving capability can be disabled
+  *        only by using I2C_FASTMODEPLUS_I2C4 parameter.
+  * @retval None
+  */
+void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
+{
+  /* Check the parameter */
+  assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
+
+  /* Enable SYSCFG clock */
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+  /* Disable fast mode plus driving capability for selected pin */
+  CLEAR_BIT(SYSCFG->PMCR, (uint32_t)ConfigFastModePlus);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_I2C_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c
new file mode 100644
index 00000000..08498c46
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c
@@ -0,0 +1,1901 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_mdma.c
+  * @author  MCD Application Team
+  * @brief  This file provides firmware functions to manage the following
+  *         functionalities of the Master Direct Memory Access (MDMA) peripheral:
+  *           + Initialization/de-initialization functions
+  *           + I/O operation functions
+  *           + Peripheral State and errors functions
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+   (#) Enable and configure the peripheral to be connected to the MDMA Channel
+       (except for internal SRAM/FLASH memories: no initialization is
+       necessary) please refer to Reference manual for connection between peripherals
+       and MDMA requests.
+
+   (#)
+       For a given Channel use HAL_MDMA_Init function to program the required configuration through the following parameters:
+       transfer request , channel priority, data endianness, Source increment, destination increment ,
+       source data size, destination data size, data alignment, source Burst, destination Burst ,
+       buffer Transfer Length, Transfer Trigger Mode (buffer transfer, block transfer, repeated block transfer
+       or full transfer) source and destination block address offset, mask address and data.
+
+       If using the MDMA in linked list mode then use function HAL_MDMA_LinkedList_CreateNode to fill a transfer node.
+       Note that parameters given to the function HAL_MDMA_Init corresponds always to the node zero.
+       Use function HAL_MDMA_LinkedList_AddNode to connect the created node to the linked list at a given position.
+       User can make a linked list circular using function HAL_MDMA_LinkedList_EnableCircularMode , this function will automatically connect the
+       last node of the list to the first one in order to make the list circular.
+       In this case the linked list will loop on node 1 : first node connected after the initial transfer defined by the HAL_MDMA_Init
+
+      -@-   The initial transfer itself (node 0 corresponding to the Init).
+            User can disable the circular mode using function HAL_MDMA_LinkedList_DisableCircularMode, this function will then remove
+            the connection between last node and first one.
+
+       Function HAL_MDMA_LinkedList_RemoveNode can be used to remove (disconnect) a node from the transfer linked list.
+       When a linked list is circular (last node connected to first one), if removing node1  (node where the linked list loops),
+       the linked list remains circular and node 2 becomes the first one.
+       Note that if the linked list is made circular the transfer will loop infinitely (or until aborted by the user).
+
+    [..]
+       (+) User can select the transfer trigger mode (parameter TransferTriggerMode) to define the amount of data to be
+           transfer upon a request :
+             (++) MDMA_BUFFER_TRANSFER : each request triggers a transfer of BufferTransferLength data
+               with BufferTransferLength defined within the HAL_MDMA_Init.
+             (++) MDMA_BLOCK_TRANSFER : each request triggers a transfer of a block
+               with block size defined within the function HAL_MDMA_Start/HAL_MDMA_Start_IT
+               or within the current linked list node parameters.
+             (++) MDMA_REPEAT_BLOCK_TRANSFER : each request triggers a transfer of a number of blocks
+               with block size and number of blocks defined within the function HAL_MDMA_Start/HAL_MDMA_Start_IT
+               or within the current linked list node parameters.
+             (++) MDMA_FULL_TRANSFER : each request triggers a full transfer
+              all blocks and all nodes(if a linked list has been created using HAL_MDMA_LinkedList_CreateNode \ HAL_MDMA_LinkedList_AddNode).
+
+     *** Polling mode IO operation ***
+     =================================
+    [..]
+          (+) Use HAL_MDMA_Start() to start MDMA transfer after the configuration of Source
+              address and destination address and the Length of data to be transferred.
+          (+) Use HAL_MDMA_PollForTransfer() to poll for the end of current transfer or a transfer level
+             In this case a fixed Timeout can be configured by User depending from his application.
+          (+) Use HAL_MDMA_Abort() function to abort the current transfer : blocking method this API returns
+              when the abort ends or timeout (should not be called from an interrupt service routine).
+
+     *** Interrupt mode IO operation ***
+     ===================================
+    [..]
+          (+) Configure the MDMA interrupt priority using HAL_NVIC_SetPriority()
+          (+) Enable the MDMA IRQ handler using HAL_NVIC_EnableIRQ()
+          (+) Use HAL_MDMA_Start_IT() to start MDMA transfer after the configuration of
+              Source address and destination address and the Length of data to be transferred. In this
+              case the MDMA interrupt is configured.
+          (+) Use HAL_MDMA_IRQHandler() called under MDMA_IRQHandler() Interrupt subroutine
+          (+) At the end of data transfer HAL_MDMA_IRQHandler() function is executed and user can
+              add his own function by customization of function pointer XferCpltCallback and
+              XferErrorCallback (i.e a member of MDMA handle structure).
+
+          (+) Use HAL_MDMA_Abort_IT() function to abort the current transfer : non-blocking method. This API will finish the execution immediately
+              then the callback XferAbortCallback (if specified  by the user) is asserted once the MDMA channel has effectively aborted.
+              (could be called from an interrupt service routine).
+
+          (+) Use functions HAL_MDMA_RegisterCallback and HAL_MDMA_UnRegisterCallback respectevely to register unregister user callbacks
+              from the following list :
+              (++) XferCpltCallback            : transfer complete callback.
+              (++) XferBufferCpltCallback      : buffer transfer complete callback.
+              (++) XferBlockCpltCallback       : block transfer complete callback.
+              (++) XferRepeatBlockCpltCallback : repeated block transfer complete callback.
+              (++) XferErrorCallback           : transfer error callback.
+              (++) XferAbortCallback           : transfer abort complete callback.
+
+    [..]
+         (+)  If the transfer Request corresponds to SW request (MDMA_REQUEST_SW) User can use function HAL_MDMA_GenerateSWRequest to
+              trigger requests manually. Function HAL_MDMA_GenerateSWRequest must be used with the following precautions:
+              (++) This function returns an error if used while the Transfer has ended or not started.
+              (++) If used while the current request has not been served yet (current request transfer on going)
+                this function returns an error and the new request is ignored.
+
+              Generally this function should be used in conjunctions with the MDMA callbacks:
+              (++) example 1:
+                 (+++) Configure a transfer with request set to MDMA_REQUEST_SW and trigger mode set to MDMA_BUFFER_TRANSFER
+                 (+++) Register a callback for buffer transfer complete (using callback ID set to HAL_MDMA_XFER_BUFFERCPLT_CB_ID)
+                 (+++) After calling HAL_MDMA_Start_IT the MDMA will issue the transfer of a first BufferTransferLength data.
+                 (+++) When the buffer transfer complete callback is asserted first buffer has been transferred and user can ask for a new buffer transfer
+                   request using HAL_MDMA_GenerateSWRequest.
+
+              (++) example 2:
+                 (+++) Configure a transfer with request set to MDMA_REQUEST_SW and trigger mode set to MDMA_BLOCK_TRANSFER
+                 (+++) Register a callback for block transfer complete (using callback ID HAL_MDMA_XFER_BLOCKCPLT_CB_ID)
+                 (+++) After calling HAL_MDMA_Start_IT the MDMA will issue the transfer of a first block of data.
+                 (+++) When the block transfer complete callback is asserted the first block has been transferred and user can ask
+                   for a new block transfer request using HAL_MDMA_GenerateSWRequest.
+
+    [..]  Use HAL_MDMA_GetState() function to return the MDMA state and HAL_MDMA_GetError() in case of error detection.
+
+     *** MDMA HAL driver macros list ***
+     =============================================
+     [..]
+       Below the list of most used macros in MDMA HAL driver.
+
+      (+) __HAL_MDMA_ENABLE: Enable the specified MDMA Channel.
+      (+) __HAL_MDMA_DISABLE: Disable the specified MDMA Channel.
+      (+) __HAL_MDMA_GET_FLAG: Get the MDMA Channel pending flags.
+      (+) __HAL_MDMA_CLEAR_FLAG: Clear the MDMA Channel pending flags.
+      (+) __HAL_MDMA_ENABLE_IT: Enable the specified MDMA Channel interrupts.
+      (+) __HAL_MDMA_DISABLE_IT: Disable the specified MDMA Channel interrupts.
+      (+) __HAL_MDMA_GET_IT_SOURCE: Check whether the specified MDMA Channel interrupt has occurred or not.
+
+     [..]
+      (@) You can refer to the header file of the MDMA HAL driver for more useful macros.
+
+    [..]
+
+    @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup MDMA  MDMA
+  * @brief MDMA HAL module driver
+  * @{
+  */
+
+#ifdef HAL_MDMA_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup MDMA_Private_Constants
+ * @{
+ */
+#define HAL_TIMEOUT_MDMA_ABORT    5U    /* 5 ms */
+#define HAL_MDMA_CHANNEL_SIZE     0x40U /* an MDMA instance channel size is 64 byte  */
+/**
+  * @}
+  */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup MDMA_Private_Functions_Prototypes
+  * @{
+  */
+static void MDMA_SetConfig(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount);
+static void MDMA_Init(MDMA_HandleTypeDef *hmdma);
+
+/**
+  * @}
+  */
+
+/** @addtogroup MDMA_Exported_Functions MDMA Exported Functions
+  * @{
+  */
+
+/** @addtogroup MDMA_Exported_Functions_Group1
+  *
+@verbatim
+ ===============================================================================
+             ##### Initialization and de-initialization functions  #####
+ ===============================================================================
+    [..]
+    This section provides functions allowing to :
+      Initialize and de-initialize the MDMA channel.
+      Register and Unregister MDMA callbacks
+    [..]
+    The HAL_MDMA_Init() function follows the MDMA channel configuration procedures as described in
+    reference manual.
+    The HAL_MDMA_DeInit function allows to deinitialize the MDMA channel.
+    HAL_MDMA_RegisterCallback and  HAL_MDMA_UnRegisterCallback functions allows
+    respectevely to register/unregister an MDMA callback function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the MDMA according to the specified
+  *         parameters in the MDMA_InitTypeDef and create the associated handle.
+  * @param  hmdma: Pointer to a MDMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified MDMA Channel.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_Init(MDMA_HandleTypeDef *hmdma)
+{
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_MDMA_STREAM_ALL_INSTANCE(hmdma->Instance));
+  assert_param(IS_MDMA_PRIORITY(hmdma->Init.Priority));
+  assert_param(IS_MDMA_ENDIANNESS_MODE(hmdma->Init.Endianness));
+  assert_param(IS_MDMA_REQUEST(hmdma->Init.Request));
+  assert_param(IS_MDMA_SOURCE_INC(hmdma->Init.SourceInc));
+  assert_param(IS_MDMA_DESTINATION_INC(hmdma->Init.DestinationInc));
+  assert_param(IS_MDMA_SOURCE_DATASIZE(hmdma->Init.SourceDataSize));
+  assert_param(IS_MDMA_DESTINATION_DATASIZE(hmdma->Init.DestDataSize));
+  assert_param(IS_MDMA_DATA_ALIGNMENT(hmdma->Init.DataAlignment));
+  assert_param(IS_MDMA_SOURCE_BURST(hmdma->Init.SourceBurst));
+  assert_param(IS_MDMA_DESTINATION_BURST(hmdma->Init.DestBurst));
+  assert_param(IS_MDMA_BUFFER_TRANSFER_LENGTH(hmdma->Init.BufferTransferLength));
+  assert_param(IS_MDMA_TRANSFER_TRIGGER_MODE(hmdma->Init.TransferTriggerMode));
+  assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(hmdma->Init.SourceBlockAddressOffset));
+  assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(hmdma->Init.DestBlockAddressOffset));
+
+
+  /* Allocate lock resource */
+  __HAL_UNLOCK(hmdma);
+
+  /* Change MDMA peripheral state */
+  hmdma->State = HAL_MDMA_STATE_BUSY;
+
+  /* Disable the MDMA channel */
+  __HAL_MDMA_DISABLE(hmdma);
+
+  /* Check if the MDMA channel is effectively disabled */
+  while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U)
+  {
+    /* Check for the Timeout */
+    if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_MDMA_ABORT)
+    {
+      /* Update error code */
+      hmdma->ErrorCode = HAL_MDMA_ERROR_TIMEOUT;
+
+      /* Change the MDMA state */
+      hmdma->State = HAL_MDMA_STATE_ERROR;
+
+      return HAL_ERROR;
+    }
+  }
+
+  /* Initialize the MDMA channel registers */
+  MDMA_Init(hmdma);
+
+  /* Reset the MDMA first/last linkedlist node addresses and node counter */
+  hmdma->FirstLinkedListNodeAddress  = 0;
+  hmdma->LastLinkedListNodeAddress   = 0;
+  hmdma->LinkedListNodeCounter  = 0;
+
+  /* Initialize the error code */
+  hmdma->ErrorCode = HAL_MDMA_ERROR_NONE;
+
+  /* Initialize the MDMA state */
+  hmdma->State = HAL_MDMA_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the MDMA peripheral
+  * @param  hmdma: pointer to a MDMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified MDMA Channel.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_DeInit(MDMA_HandleTypeDef *hmdma)
+{
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Disable the selected MDMA Channelx */
+  __HAL_MDMA_DISABLE(hmdma);
+
+  /* Reset MDMA Channel control register */
+  hmdma->Instance->CCR  = 0;
+  hmdma->Instance->CTCR = 0;
+  hmdma->Instance->CBNDTR = 0;
+  hmdma->Instance->CSAR = 0;
+  hmdma->Instance->CDAR = 0;
+  hmdma->Instance->CBRUR = 0;
+  hmdma->Instance->CLAR = 0;
+  hmdma->Instance->CTBR = 0;
+  hmdma->Instance->CMAR = 0;
+  hmdma->Instance->CMDR = 0;
+
+  /* Clear all flags */
+  __HAL_MDMA_CLEAR_FLAG(hmdma,(MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_FLAG_BRT | MDMA_FLAG_BT | MDMA_FLAG_BFTC));
+
+  /* Reset the  MDMA first/last linkedlist node addresses and node counter */
+  hmdma->FirstLinkedListNodeAddress  = 0;
+  hmdma->LastLinkedListNodeAddress   = 0;
+  hmdma->LinkedListNodeCounter  = 0;
+
+  /* Initialize the error code */
+  hmdma->ErrorCode = HAL_MDMA_ERROR_NONE;
+
+  /* Initialize the MDMA state */
+  hmdma->State = HAL_MDMA_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hmdma);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Config the Post request Mask address and Mask data
+  * @param  hmdma      : pointer to a MDMA_HandleTypeDef structure that contains
+  *                               the configuration information for the specified MDMA Channel.
+  * @param  MaskAddress: specifies the address to be updated (written) with MaskData after a request is served.
+  * @param  MaskData:    specifies the value to be written to MaskAddress after a request is served.
+  *                      MaskAddress and MaskData could be used to automatically clear a peripheral flag when the request is served.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_ConfigPostRequestMask(MDMA_HandleTypeDef *hmdma, uint32_t MaskAddress, uint32_t MaskData)
+{
+  HAL_StatusTypeDef  status = HAL_OK;
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hmdma);
+
+  if(HAL_MDMA_STATE_READY == hmdma->State)
+  {
+    /* if HW request set Post Request MaskAddress and MaskData,  */
+    if((hmdma->Instance->CTCR & MDMA_CTCR_SWRM) == 0U)
+    {
+      /* Set the HW request clear Mask and Data */
+      hmdma->Instance->CMAR = MaskAddress;
+      hmdma->Instance->CMDR = MaskData;
+
+      /*
+      -If the request is done by SW : BWM could be set to 1 or 0.
+      -If the request is done by a peripheral :
+         If mask address not set (0) => BWM must be set to 0
+         If mask address set (different than 0) => BWM could be set to 1 or 0
+      */
+      if(MaskAddress == 0U)
+      {
+        hmdma->Instance->CTCR &=  ~MDMA_CTCR_BWM;
+      }
+      else
+      {
+        hmdma->Instance->CTCR |=  MDMA_CTCR_BWM;
+      }
+    }
+    else
+    {
+      /* Return error status */
+      status =  HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+  /* Release Lock */
+  __HAL_UNLOCK(hmdma);
+
+  return status;
+}
+
+/**
+  * @brief  Register callbacks
+  * @param  hmdma:                pointer to a MDMA_HandleTypeDef structure that contains
+  *                               the configuration information for the specified MDMA Channel.
+  * @param  CallbackID:           User Callback identifier
+  * @param  pCallback:            pointer to callbacsk function.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_RegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID, void (* pCallback)(MDMA_HandleTypeDef *_hmdma))
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hmdma);
+
+  if(HAL_MDMA_STATE_READY == hmdma->State)
+  {
+    switch (CallbackID)
+    {
+    case  HAL_MDMA_XFER_CPLT_CB_ID:
+      hmdma->XferCpltCallback = pCallback;
+      break;
+
+    case  HAL_MDMA_XFER_BUFFERCPLT_CB_ID:
+      hmdma->XferBufferCpltCallback = pCallback;
+      break;
+
+    case  HAL_MDMA_XFER_BLOCKCPLT_CB_ID:
+      hmdma->XferBlockCpltCallback = pCallback;
+      break;
+
+    case  HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID:
+      hmdma->XferRepeatBlockCpltCallback = pCallback;
+      break;
+
+    case  HAL_MDMA_XFER_ERROR_CB_ID:
+      hmdma->XferErrorCallback = pCallback;
+      break;
+
+    case  HAL_MDMA_XFER_ABORT_CB_ID:
+      hmdma->XferAbortCallback = pCallback;
+      break;
+
+    default:
+      break;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hmdma);
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister callbacks
+  * @param  hmdma:                 pointer to a MDMA_HandleTypeDef structure that contains
+  *                               the configuration information for the specified MDMA Channel.
+  * @param  CallbackID:           User Callback identifier
+  *                               a HAL_MDMA_CallbackIDTypeDef ENUM as parameter.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_UnRegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hmdma);
+
+  if(HAL_MDMA_STATE_READY == hmdma->State)
+  {
+    switch (CallbackID)
+    {
+    case  HAL_MDMA_XFER_CPLT_CB_ID:
+      hmdma->XferCpltCallback = NULL;
+      break;
+
+    case  HAL_MDMA_XFER_BUFFERCPLT_CB_ID:
+      hmdma->XferBufferCpltCallback = NULL;
+      break;
+
+    case  HAL_MDMA_XFER_BLOCKCPLT_CB_ID:
+      hmdma->XferBlockCpltCallback = NULL;
+      break;
+
+    case  HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID:
+      hmdma->XferRepeatBlockCpltCallback = NULL;
+      break;
+
+    case  HAL_MDMA_XFER_ERROR_CB_ID:
+      hmdma->XferErrorCallback = NULL;
+      break;
+
+    case  HAL_MDMA_XFER_ABORT_CB_ID:
+      hmdma->XferAbortCallback = NULL;
+      break;
+
+    case   HAL_MDMA_XFER_ALL_CB_ID:
+      hmdma->XferCpltCallback = NULL;
+      hmdma->XferBufferCpltCallback = NULL;
+      hmdma->XferBlockCpltCallback = NULL;
+      hmdma->XferRepeatBlockCpltCallback = NULL;
+      hmdma->XferErrorCallback = NULL;
+      hmdma->XferAbortCallback = NULL;
+      break;
+
+    default:
+      status = HAL_ERROR;
+      break;
+    }
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hmdma);
+
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup MDMA_Exported_Functions_Group2
+ *
+@verbatim
+ ===============================================================================
+                      #####  Linked list operation functions  #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Create a linked list node
+      (+) Add a node to the MDMA linked list
+      (+) Remove a node from the MDMA linked list
+      (+) Enable/Disable linked list circular mode
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes an MDMA Link Node according to the specified
+  *         parameters in the pMDMA_LinkedListNodeConfig .
+  * @param  pNode: Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node
+  *         registers configurations.
+  * @param  pNodeConfig: Pointer to a MDMA_LinkNodeConfTypeDef structure that contains
+  *               the configuration information for the specified MDMA Linked List Node.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig)
+{
+  uint32_t addressMask;
+  uint32_t blockoffset;
+
+  /* Check the MDMA peripheral state */
+  if((pNode == NULL) || (pNodeConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_MDMA_PRIORITY(pNodeConfig->Init.Priority));
+  assert_param(IS_MDMA_ENDIANNESS_MODE(pNodeConfig->Init.Endianness));
+  assert_param(IS_MDMA_REQUEST(pNodeConfig->Init.Request));
+  assert_param(IS_MDMA_SOURCE_INC(pNodeConfig->Init.SourceInc));
+  assert_param(IS_MDMA_DESTINATION_INC(pNodeConfig->Init.DestinationInc));
+  assert_param(IS_MDMA_SOURCE_DATASIZE(pNodeConfig->Init.SourceDataSize));
+  assert_param(IS_MDMA_DESTINATION_DATASIZE(pNodeConfig->Init.DestDataSize));
+  assert_param(IS_MDMA_DATA_ALIGNMENT(pNodeConfig->Init.DataAlignment));
+  assert_param(IS_MDMA_SOURCE_BURST(pNodeConfig->Init.SourceBurst));
+  assert_param(IS_MDMA_DESTINATION_BURST(pNodeConfig->Init.DestBurst));
+  assert_param(IS_MDMA_BUFFER_TRANSFER_LENGTH(pNodeConfig->Init.BufferTransferLength));
+  assert_param(IS_MDMA_TRANSFER_TRIGGER_MODE(pNodeConfig->Init.TransferTriggerMode));
+  assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(pNodeConfig->Init.SourceBlockAddressOffset));
+  assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(pNodeConfig->Init.DestBlockAddressOffset));
+
+  assert_param(IS_MDMA_TRANSFER_LENGTH(pNodeConfig->BlockDataLength));
+  assert_param(IS_MDMA_BLOCK_COUNT(pNodeConfig->BlockCount));
+
+
+  /* Configure next Link node Address Register to zero */
+  pNode->CLAR =  0;
+
+  /* Configure the Link Node registers*/
+  pNode->CTBR   = 0;
+  pNode->CMAR   = 0;
+  pNode->CMDR   = 0;
+  pNode->Reserved = 0;
+
+  /* Write new CTCR Register value */
+  pNode->CTCR =  pNodeConfig->Init.SourceInc | pNodeConfig->Init.DestinationInc | \
+    pNodeConfig->Init.SourceDataSize | pNodeConfig->Init.DestDataSize           | \
+      pNodeConfig->Init.DataAlignment| pNodeConfig->Init.SourceBurst            | \
+        pNodeConfig->Init.DestBurst                                             | \
+          ((pNodeConfig->Init.BufferTransferLength - 1U) << MDMA_CTCR_TLEN_Pos) | \
+            pNodeConfig->Init.TransferTriggerMode;
+
+  /* If SW request set the CTCR register to SW Request Mode*/
+  if(pNodeConfig->Init.Request == MDMA_REQUEST_SW)
+  {
+    pNode->CTCR |= MDMA_CTCR_SWRM;
+  }
+
+  /*
+  -If the request is done by SW : BWM could be set to 1 or 0.
+  -If the request is done by a peripheral :
+     If mask address not set (0) => BWM must be set to 0
+     If mask address set (different than 0) => BWM could be set to 1 or 0
+  */
+  if((pNodeConfig->Init.Request == MDMA_REQUEST_SW) || (pNodeConfig->PostRequestMaskAddress != 0U))
+  {
+    pNode->CTCR |=  MDMA_CTCR_BWM;
+  }
+
+  /* Set the new CBNDTR Register value */
+  pNode->CBNDTR = ((pNodeConfig->BlockCount - 1U) << MDMA_CBNDTR_BRC_Pos) & MDMA_CBNDTR_BRC;
+
+  /* if block source address offset is negative set the Block Repeat Source address Update Mode to decrement */
+  if(pNodeConfig->Init.SourceBlockAddressOffset < 0)
+  {
+    pNode->CBNDTR |= MDMA_CBNDTR_BRSUM;
+    /*write new CBRUR Register value : source repeat block offset */
+    blockoffset = (uint32_t)(- pNodeConfig->Init.SourceBlockAddressOffset);
+    pNode->CBRUR = blockoffset & 0x0000FFFFU;
+  }
+  else
+  {
+    /*write new CBRUR Register value : source repeat block offset */
+    pNode->CBRUR = (((uint32_t) pNodeConfig->Init.SourceBlockAddressOffset) & 0x0000FFFFU);
+  }
+
+  /* if block destination address offset is negative set the Block Repeat destination address Update Mode to decrement */
+  if(pNodeConfig->Init.DestBlockAddressOffset < 0)
+  {
+    pNode->CBNDTR |= MDMA_CBNDTR_BRDUM;
+    /*write new CBRUR Register value : destination repeat block offset */
+    blockoffset = (uint32_t)(- pNodeConfig->Init.DestBlockAddressOffset);
+    pNode->CBRUR |= ((blockoffset & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos);
+  }
+  else
+  {
+    /*write new CBRUR Register value : destination repeat block offset */
+    pNode->CBRUR |= ((((uint32_t)pNodeConfig->Init.DestBlockAddressOffset) & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos);
+  }
+
+  /* Configure MDMA Link Node data length */
+  pNode->CBNDTR |=  pNodeConfig->BlockDataLength;
+
+  /* Configure MDMA Link Node destination address */
+  pNode->CDAR = pNodeConfig->DstAddress;
+
+  /* Configure MDMA Link Node Source address */
+  pNode->CSAR = pNodeConfig->SrcAddress;
+
+  /* if HW request set the HW request and the requet CleraMask and ClearData MaskData,  */
+  if(pNodeConfig->Init.Request != MDMA_REQUEST_SW)
+  {
+    /* Set the HW request in CTBR register  */
+    pNode->CTBR = pNodeConfig->Init.Request & MDMA_CTBR_TSEL;
+    /* Set the HW request clear Mask and Data */
+    pNode->CMAR = pNodeConfig->PostRequestMaskAddress;
+    pNode->CMDR = pNodeConfig->PostRequestMaskData;
+  }
+
+  addressMask = pNodeConfig->SrcAddress & 0xFF000000U;
+  if((addressMask == 0x20000000U) || (addressMask == 0x00000000U))
+  {
+    /*The AHBSbus is used as source (read operation) on channel x */
+    pNode->CTBR |= MDMA_CTBR_SBUS;
+  }
+
+  addressMask = pNodeConfig->DstAddress & 0xFF000000U;
+  if((addressMask == 0x20000000U) || (addressMask == 0x00000000U))
+  {
+    /*The AHB bus is used as destination (write operation) on channel x */
+    pNode->CTBR |= MDMA_CTBR_DBUS;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Connect a node to the linked list.
+  * @param  hmdma    : Pointer to a MDMA_HandleTypeDef structure that contains
+  *                    the configuration information for the specified MDMA Channel.
+  * @param  pNewNode : Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node
+  *                    to be add to the list.
+  * @param pPrevNode : Pointer to the new node position in the linked list or zero to insert the new node
+  *                    at the end of the list
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, MDMA_LinkNodeTypeDef *pPrevNode)
+{
+  MDMA_LinkNodeTypeDef *pNode;
+  uint32_t counter = 0, nodeInserted = 0;
+  HAL_StatusTypeDef hal_status = HAL_OK;
+
+  /* Check the MDMA peripheral handle */
+  if((hmdma == NULL) || (pNewNode == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hmdma);
+
+  if(HAL_MDMA_STATE_READY == hmdma->State)
+  {
+    /* Change MDMA peripheral state */
+    hmdma->State = HAL_MDMA_STATE_BUSY;
+
+    /* Check if this is the first node (after the Inititlization node) */
+    if((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U)
+    {
+      if(pPrevNode == NULL)
+      {
+        /* if this is the first node after the initialization
+        connect this node to the node 0 by updating
+        the MDMA channel CLAR register to this node address */
+        hmdma->Instance->CLAR = (uint32_t)pNewNode;
+        /* Set the MDMA handle First linked List node*/
+        hmdma->FirstLinkedListNodeAddress = pNewNode;
+
+        /*reset New node link */
+        pNewNode->CLAR = 0;
+
+        /* Update the Handle last node address */
+        hmdma->LastLinkedListNodeAddress = pNewNode;
+
+        hmdma->LinkedListNodeCounter = 1;
+      }
+      else
+      {
+        hal_status = HAL_ERROR;
+      }
+    }
+    else if(hmdma->FirstLinkedListNodeAddress != pNewNode)
+    {
+      /* Check if the node to insert already exists*/
+      pNode = hmdma->FirstLinkedListNodeAddress;
+      while((counter < hmdma->LinkedListNodeCounter) && (hal_status == HAL_OK))
+      {
+        if(pNode->CLAR == (uint32_t)pNewNode)
+        {
+          hal_status = HAL_ERROR; /* error this node already exist in the linked list and it is not first node */
+        }
+        pNode = (MDMA_LinkNodeTypeDef *)pNode->CLAR;
+        counter++;
+      }
+
+      if(hal_status == HAL_OK)
+      {
+        /* Check if the previous node is the last one in the current list or zero */
+        if((pPrevNode == hmdma->LastLinkedListNodeAddress) || (pPrevNode == NULL))
+        {
+          /* insert the new node at the end of the list */
+          pNewNode->CLAR = hmdma->LastLinkedListNodeAddress->CLAR;
+          hmdma->LastLinkedListNodeAddress->CLAR = (uint32_t)pNewNode;
+          /* Update the Handle last node address */
+          hmdma->LastLinkedListNodeAddress = pNewNode;
+          /* Increment the linked list node counter */
+          hmdma->LinkedListNodeCounter++;
+        }
+        else
+        {
+          /*insert the new node after the pPreviousNode node */
+          pNode = hmdma->FirstLinkedListNodeAddress;
+          counter = 0;
+          while((counter < hmdma->LinkedListNodeCounter) && (nodeInserted == 0U))
+          {
+            counter++;
+            if(pNode == pPrevNode)
+            {
+              /*Insert the new node after the previous one */
+              pNewNode->CLAR = pNode->CLAR;
+              pNode->CLAR = (uint32_t)pNewNode;
+              /* Increment the linked list node counter */
+              hmdma->LinkedListNodeCounter++;
+              nodeInserted = 1;
+            }
+            else
+            {
+              pNode = (MDMA_LinkNodeTypeDef *)pNode->CLAR;
+            }
+          }
+
+          if(nodeInserted == 0U)
+          {
+            hal_status = HAL_ERROR;
+          }
+        }
+      }
+    }
+    else
+    {
+      hal_status = HAL_ERROR;
+    }
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hmdma);
+
+    hmdma->State = HAL_MDMA_STATE_READY;
+
+    return hal_status;
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hmdma);
+
+    /* Return error status */
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Disconnect/Remove a node from the transfer linked list.
+  * @param  hmdma : Pointer to a MDMA_HandleTypeDef structure that contains
+  *                 the configuration information for the specified MDMA Channel.
+  * @param  pNode : Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node
+  *                 to be removed from the list.
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNode)
+{
+  MDMA_LinkNodeTypeDef *ptmpNode;
+  uint32_t counter = 0, nodeDeleted = 0;
+  HAL_StatusTypeDef hal_status = HAL_OK;
+
+  /* Check the MDMA peripheral handle */
+  if((hmdma == NULL) || (pNode == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hmdma);
+
+  if(HAL_MDMA_STATE_READY == hmdma->State)
+  {
+    /* Change MDMA peripheral state */
+    hmdma->State = HAL_MDMA_STATE_BUSY;
+
+    /* If first and last node are null (no nodes in the list) : return error*/
+    if(((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U) || ((uint32_t)hmdma->LastLinkedListNodeAddress == 0U) || (hmdma->LinkedListNodeCounter == 0U))
+    {
+      hal_status = HAL_ERROR;
+    }
+    else if(hmdma->FirstLinkedListNodeAddress == pNode) /* Deleting first node */
+    {
+      /* Delete 1st node */
+      if(hmdma->LastLinkedListNodeAddress == pNode)
+      {
+        /*if the last node is at the same time the first one (1 single node after the init node 0)
+        then update the last node too */
+
+        hmdma->FirstLinkedListNodeAddress = 0;
+        hmdma->LastLinkedListNodeAddress  = 0;
+        hmdma->LinkedListNodeCounter = 0;
+
+        hmdma->Instance->CLAR = 0;
+      }
+      else
+      {
+        if((uint32_t)hmdma->FirstLinkedListNodeAddress == hmdma->LastLinkedListNodeAddress->CLAR)
+        {
+          /* if last node is looping to first (circular list) one update the last node connection */
+          hmdma->LastLinkedListNodeAddress->CLAR = pNode->CLAR;
+        }
+
+        /* if deleting the first node after the initialization
+        connect the next node to the node 0 by updating
+        the MDMA channel CLAR register to this node address */
+        hmdma->Instance->CLAR = pNode->CLAR;
+        hmdma->FirstLinkedListNodeAddress = (MDMA_LinkNodeTypeDef *)hmdma->Instance->CLAR;
+        /* Update the Handle node counter */
+        hmdma->LinkedListNodeCounter--;
+      }
+    }
+    else /* Deleting any other node */
+    {
+      /*Deleted node is not the first one : find it  */
+      ptmpNode = hmdma->FirstLinkedListNodeAddress;
+      while((counter < hmdma->LinkedListNodeCounter) && (nodeDeleted == 0U))
+      {
+        counter++;
+        if(ptmpNode->CLAR == ((uint32_t)pNode))
+        {
+          /* if deleting the last node */
+          if(pNode == hmdma->LastLinkedListNodeAddress)
+          {
+            /*Update the linked list last node address in the handle*/
+            hmdma->LastLinkedListNodeAddress = ptmpNode;
+          }
+          /* update the next node link after deleting pMDMA_LinkedListNode */
+          ptmpNode->CLAR = pNode->CLAR;
+          nodeDeleted = 1;
+          /* Update the Handle node counter */
+          hmdma->LinkedListNodeCounter--;
+        }
+        else
+        {
+          ptmpNode = (MDMA_LinkNodeTypeDef *)ptmpNode->CLAR;
+        }
+      }
+
+      if(nodeDeleted == 0U)
+      {
+        /* last node reashed without finding the node to delete : return error */
+        hal_status = HAL_ERROR;
+      }
+    }
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hmdma);
+
+    hmdma->State = HAL_MDMA_STATE_READY;
+
+    return hal_status;
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hmdma);
+
+    /* Return error status */
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Make the linked list circular by connecting the last node to the first.
+  * @param  hmdma : Pointer to a MDMA_HandleTypeDef structure that contains
+  *                 the configuration information for the specified MDMA Channel.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_LinkedList_EnableCircularMode(MDMA_HandleTypeDef *hmdma)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hmdma);
+
+  if(HAL_MDMA_STATE_READY == hmdma->State)
+  {
+    /* Change MDMA peripheral state */
+    hmdma->State = HAL_MDMA_STATE_BUSY;
+
+    /* If first and last node are null (no nodes in the list) : return error*/
+    if(((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U) || ((uint32_t)hmdma->LastLinkedListNodeAddress == 0U) || (hmdma->LinkedListNodeCounter == 0U))
+    {
+      hal_status = HAL_ERROR;
+    }
+    else
+    {
+      /* to enable circular mode Last Node should be connected to first node */
+      hmdma->LastLinkedListNodeAddress->CLAR = (uint32_t)hmdma->FirstLinkedListNodeAddress;
+    }
+
+  }
+  /* Process unlocked */
+  __HAL_UNLOCK(hmdma);
+
+  hmdma->State = HAL_MDMA_STATE_READY;
+
+  return hal_status;
+}
+
+/**
+  * @brief  Disable the linked list circular mode by setting the last node connection to null
+  * @param  hmdma : Pointer to a MDMA_HandleTypeDef structure that contains
+  *                 the configuration information for the specified MDMA Channel.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_LinkedList_DisableCircularMode(MDMA_HandleTypeDef *hmdma)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hmdma);
+
+  if(HAL_MDMA_STATE_READY == hmdma->State)
+  {
+    /* Change MDMA peripheral state */
+    hmdma->State = HAL_MDMA_STATE_BUSY;
+
+    /* If first and last node are null (no nodes in the list) : return error*/
+    if(((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U) || ((uint32_t)hmdma->LastLinkedListNodeAddress == 0U) || (hmdma->LinkedListNodeCounter == 0U))
+    {
+      hal_status = HAL_ERROR;
+    }
+    else
+    {
+      /* to disable circular mode Last Node should be connected to NULL */
+      hmdma->LastLinkedListNodeAddress->CLAR = 0;
+    }
+
+  }
+  /* Process unlocked */
+  __HAL_UNLOCK(hmdma);
+
+  hmdma->State = HAL_MDMA_STATE_READY;
+
+  return hal_status;
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup MDMA_Exported_Functions_Group3
+ *
+@verbatim
+ ===============================================================================
+                      #####  IO operation functions  #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure the source, destination address and data length and Start MDMA transfer
+      (+) Configure the source, destination address and data length and
+          Start MDMA transfer with interrupt
+      (+) Abort MDMA transfer
+      (+) Poll for transfer complete
+      (+) Generate a SW request (when Request is set to MDMA_REQUEST_SW)
+      (+) Handle MDMA interrupt request
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the MDMA Transfer.
+  * @param  hmdma           : pointer to a MDMA_HandleTypeDef structure that contains
+  *                           the configuration information for the specified MDMA Channel.
+  * @param  SrcAddress      : The source memory Buffer address
+  * @param  DstAddress      : The destination memory Buffer address
+  * @param  BlockDataLength : The length of a block transfer in bytes
+  * @param  BlockCount      : The number of a blocks to be transfer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_Start(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
+{
+  /* Check the parameters */
+  assert_param(IS_MDMA_TRANSFER_LENGTH(BlockDataLength));
+  assert_param(IS_MDMA_BLOCK_COUNT(BlockCount));
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hmdma);
+
+  if(HAL_MDMA_STATE_READY == hmdma->State)
+  {
+    /* Change MDMA peripheral state */
+    hmdma->State = HAL_MDMA_STATE_BUSY;
+
+    /* Initialize the error code */
+    hmdma->ErrorCode = HAL_MDMA_ERROR_NONE;
+
+    /* Disable the peripheral */
+    __HAL_MDMA_DISABLE(hmdma);
+
+    /* Configure the source, destination address and the data length */
+    MDMA_SetConfig(hmdma, SrcAddress, DstAddress, BlockDataLength, BlockCount);
+
+    /* Enable the Peripheral */
+    __HAL_MDMA_ENABLE(hmdma);
+
+    if(hmdma->Init.Request == MDMA_REQUEST_SW)
+    {
+      /* activate If SW request mode*/
+      hmdma->Instance->CCR |=  MDMA_CCR_SWRQ;
+    }
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hmdma);
+
+    /* Return error status */
+    return HAL_BUSY;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the MDMA Transfer with interrupts enabled.
+  * @param  hmdma           : pointer to a MDMA_HandleTypeDef structure that contains
+  *                           the configuration information for the specified MDMA Channel.
+  * @param  SrcAddress      : The source memory Buffer address
+  * @param  DstAddress      : The destination memory Buffer address
+  * @param  BlockDataLength : The length of a block transfer in bytes
+  * @param  BlockCount      : The number of a blocks to be transfer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_Start_IT(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
+{
+  /* Check the parameters */
+  assert_param(IS_MDMA_TRANSFER_LENGTH(BlockDataLength));
+  assert_param(IS_MDMA_BLOCK_COUNT(BlockCount));
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hmdma);
+
+  if(HAL_MDMA_STATE_READY == hmdma->State)
+  {
+    /* Change MDMA peripheral state */
+    hmdma->State = HAL_MDMA_STATE_BUSY;
+
+    /* Initialize the error code */
+    hmdma->ErrorCode = HAL_MDMA_ERROR_NONE;
+
+    /* Disable the peripheral */
+    __HAL_MDMA_DISABLE(hmdma);
+
+    /* Configure the source, destination address and the data length */
+    MDMA_SetConfig(hmdma, SrcAddress, DstAddress, BlockDataLength, BlockCount);
+
+    /* Enable Common interrupts i.e Transfer Error IT and Channel Transfer Complete IT*/
+    __HAL_MDMA_ENABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC));
+
+    if(hmdma->XferBlockCpltCallback != NULL)
+    {
+      /* if Block transfer complete Callback is set enable the corresponding IT*/
+      __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BT);
+    }
+
+    if(hmdma->XferRepeatBlockCpltCallback != NULL)
+    {
+      /* if Repeated Block transfer complete Callback is set enable the corresponding IT*/
+      __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BRT);
+    }
+
+    if(hmdma->XferBufferCpltCallback != NULL)
+    {
+      /* if buffer transfer complete Callback is set enable the corresponding IT*/
+      __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BFTC);
+    }
+
+    /* Enable the Peripheral */
+    __HAL_MDMA_ENABLE(hmdma);
+
+    if(hmdma->Init.Request == MDMA_REQUEST_SW)
+    {
+      /* activate If SW request mode*/
+      hmdma->Instance->CCR |=  MDMA_CCR_SWRQ;
+    }
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hmdma);
+
+    /* Return error status */
+    return HAL_BUSY;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Aborts the MDMA Transfer.
+  * @param  hmdma  : pointer to a MDMA_HandleTypeDef structure that contains
+  *                 the configuration information for the specified MDMA Channel.
+  *
+  * @note  After disabling a MDMA Channel, a check for wait until the MDMA Channel is
+  *        effectively disabled is added. If a Channel is disabled
+  *        while a data transfer is ongoing, the current data will be transferred
+  *        and the Channel will be effectively disabled only after the transfer of
+  *        this single data is finished.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_Abort(MDMA_HandleTypeDef *hmdma)
+{
+  uint32_t tickstart =  HAL_GetTick();
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if(HAL_MDMA_STATE_BUSY != hmdma->State)
+  {
+    hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hmdma);
+
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Disable all the transfer interrupts */
+    __HAL_MDMA_DISABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC | MDMA_IT_BT | MDMA_IT_BRT | MDMA_IT_BFTC));
+
+    /* Disable the channel */
+    __HAL_MDMA_DISABLE(hmdma);
+
+    /* Check if the MDMA Channel is effectively disabled */
+    while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U)
+    {
+      /* Check for the Timeout */
+      if( (HAL_GetTick()  - tickstart ) > HAL_TIMEOUT_MDMA_ABORT)
+      {
+        /* Update error code */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_TIMEOUT;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hmdma);
+
+        /* Change the MDMA state */
+        hmdma->State = HAL_MDMA_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+    }
+
+    /* Clear all interrupt flags */
+    __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_FLAG_BT | MDMA_FLAG_BRT | MDMA_FLAG_BFTC));
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hmdma);
+
+    /* Change the MDMA state*/
+    hmdma->State = HAL_MDMA_STATE_READY;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Aborts the MDMA Transfer in Interrupt mode.
+  * @param  hmdma  : pointer to a MDMA_HandleTypeDef structure that contains
+  *                 the configuration information for the specified MDMA Channel.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_Abort_IT(MDMA_HandleTypeDef *hmdma)
+{
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if(HAL_MDMA_STATE_BUSY != hmdma->State)
+  {
+    /* No transfer ongoing */
+    hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER;
+
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Set Abort State  */
+    hmdma->State = HAL_MDMA_STATE_ABORT;
+
+    /* Disable the stream */
+    __HAL_MDMA_DISABLE(hmdma);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Polling for transfer complete.
+  * @param  hmdma:          pointer to a MDMA_HandleTypeDef structure that contains
+  *                        the configuration information for the specified MDMA Channel.
+  * @param  CompleteLevel: Specifies the MDMA level complete.
+  * @param  Timeout:       Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_PollForTransfer(MDMA_HandleTypeDef *hmdma, HAL_MDMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
+{
+  uint32_t levelFlag, errorFlag;
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param(IS_MDMA_LEVEL_COMPLETE(CompleteLevel));
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if(HAL_MDMA_STATE_BUSY != hmdma->State)
+  {
+    /* No transfer ongoing */
+    hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER;
+
+    return HAL_ERROR;
+  }
+
+  /* Get the level transfer complete flag */
+  levelFlag = ((CompleteLevel == HAL_MDMA_FULL_TRANSFER)  ? MDMA_FLAG_CTC  : \
+               (CompleteLevel == HAL_MDMA_BUFFER_TRANSFER)? MDMA_FLAG_BFTC : \
+               (CompleteLevel == HAL_MDMA_BLOCK_TRANSFER) ? MDMA_FLAG_BT   : \
+               MDMA_FLAG_BRT);
+
+
+  /* Get timeout */
+  tickstart = HAL_GetTick();
+
+  while(__HAL_MDMA_GET_FLAG(hmdma, levelFlag) == 0U)
+  {
+    if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_TE) != 0U))
+    {
+      /* Get the transfer error source flag */
+      errorFlag = hmdma->Instance->CESR;
+
+      if((errorFlag & MDMA_CESR_TED) == 0U)
+      {
+        /* Update error code : Read Transfer error  */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_READ_XFER;
+      }
+      else
+      {
+        /* Update error code : Write Transfer error */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_WRITE_XFER;
+      }
+
+      if((errorFlag & MDMA_CESR_TEMD) != 0U)
+      {
+        /* Update error code : Error Mask Data */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_MASK_DATA;
+      }
+
+      if((errorFlag & MDMA_CESR_TELD) != 0U)
+      {
+        /* Update error code : Error Linked list */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_LINKED_LIST;
+      }
+
+      if((errorFlag & MDMA_CESR_ASE) != 0U)
+      {
+        /* Update error code : Address/Size alignment error */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_ALIGNMENT;
+      }
+
+      if((errorFlag & MDMA_CESR_BSE) != 0U)
+      {
+        /* Update error code : Block Size error */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_BLOCK_SIZE;
+      }
+
+      (void) HAL_MDMA_Abort(hmdma); /* if error then abort the current transfer */
+
+      /*
+        Note that the Abort function will
+          - Clear all transfer flags
+          - Unlock
+          - Set the State
+      */
+
+      return HAL_ERROR;
+
+    }
+
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(((HAL_GetTick() - tickstart ) > Timeout) || (Timeout == 0U))
+      {
+        /* Update error code */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_TIMEOUT;
+
+        (void) HAL_MDMA_Abort(hmdma); /* if timeout then abort the current transfer */
+
+        /*
+          Note that the Abort function will
+            - Clear all transfer flags
+            - Unlock
+            - Set the State
+        */
+
+        return HAL_ERROR;
+      }
+    }
+  }
+
+  /* Clear the transfer level flag */
+  if(CompleteLevel == HAL_MDMA_BUFFER_TRANSFER)
+  {
+    __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BFTC);
+
+  }
+  else if(CompleteLevel == HAL_MDMA_BLOCK_TRANSFER)
+  {
+    __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BFTC | MDMA_FLAG_BT));
+
+  }
+  else if(CompleteLevel == HAL_MDMA_REPEAT_BLOCK_TRANSFER)
+  {
+    __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BFTC | MDMA_FLAG_BT | MDMA_FLAG_BRT));
+  }
+  else if(CompleteLevel == HAL_MDMA_FULL_TRANSFER)
+  {
+    __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BRT | MDMA_FLAG_BT | MDMA_FLAG_BFTC | MDMA_FLAG_CTC));
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hmdma);
+
+    hmdma->State = HAL_MDMA_STATE_READY;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Generate an MDMA SW request trigger to activate the request on the given Channel.
+  * @param  hmdma:       pointer to a MDMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified MDMA Stream.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_GenerateSWRequest(MDMA_HandleTypeDef *hmdma)
+{
+  uint32_t request_mode;
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Get the softawre request mode */
+  request_mode = hmdma->Instance->CTCR & MDMA_CTCR_SWRM;
+
+  if((hmdma->Instance->CCR &  MDMA_CCR_EN) == 0U)
+  {
+    /* if no Transfer on going (MDMA enable bit not set) retrun error */
+    hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER;
+
+    return HAL_ERROR;
+  }
+  else if(((hmdma->Instance->CISR &  MDMA_CISR_CRQA) != 0U) || (request_mode == 0U))
+  {
+    /* if an MDMA ongoing request has not yet end or if request mode is not SW request retrun error */
+    hmdma->ErrorCode = HAL_MDMA_ERROR_BUSY;
+
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Set the SW request bit to activate the request on the Channel */
+    hmdma->Instance->CCR |= MDMA_CCR_SWRQ;
+
+    return HAL_OK;
+  }
+}
+
+/**
+  * @brief  Handles MDMA interrupt request.
+  * @param  hmdma: pointer to a MDMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified MDMA Channel.
+  * @retval None
+  */
+void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma)
+{
+  __IO uint32_t count = 0;
+  uint32_t timeout = SystemCoreClock / 9600U;
+
+  uint32_t generalIntFlag, errorFlag;
+
+  /* General Interrupt Flag management ****************************************/
+  generalIntFlag =  1UL << ((((uint32_t)hmdma->Instance - (uint32_t)(MDMA_Channel0))/HAL_MDMA_CHANNEL_SIZE) & 0x1FU);
+  if((MDMA->GISR0 & generalIntFlag) == 0U)
+  {
+    return; /* the  General interrupt flag for the current channel is down , nothing to do */
+  }
+
+  /* Transfer Error Interrupt management ***************************************/
+  if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_TE) != 0U))
+  {
+    if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_TE) != 0U)
+    {
+      /* Disable the transfer error interrupt */
+      __HAL_MDMA_DISABLE_IT(hmdma, MDMA_IT_TE);
+
+      /* Get the transfer error source flag */
+      errorFlag = hmdma->Instance->CESR;
+
+      if((errorFlag & MDMA_CESR_TED) == 0U)
+      {
+        /* Update error code : Read Transfer error  */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_READ_XFER;
+      }
+      else
+      {
+        /* Update error code : Write Transfer error */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_WRITE_XFER;
+      }
+
+      if((errorFlag & MDMA_CESR_TEMD) != 0U)
+      {
+        /* Update error code : Error Mask Data */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_MASK_DATA;
+      }
+
+      if((errorFlag & MDMA_CESR_TELD) != 0U)
+      {
+        /* Update error code : Error Linked list */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_LINKED_LIST;
+      }
+
+      if((errorFlag & MDMA_CESR_ASE) != 0U)
+      {
+        /* Update error code : Address/Size alignment error */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_ALIGNMENT;
+      }
+
+      if((errorFlag & MDMA_CESR_BSE) != 0U)
+      {
+        /* Update error code : Block Size error error */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_BLOCK_SIZE;
+      }
+
+      /* Clear the transfer error flags */
+      __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_TE);
+    }
+  }
+
+  /* Buffer Transfer Complete Interrupt management ******************************/
+  if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BFTC) != 0U))
+  {
+    if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BFTC) != 0U)
+    {
+      /* Clear the buffer transfer complete flag */
+      __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BFTC);
+
+      if(hmdma->XferBufferCpltCallback != NULL)
+      {
+        /* Buffer transfer callback */
+        hmdma->XferBufferCpltCallback(hmdma);
+      }
+    }
+  }
+
+  /* Block Transfer Complete Interrupt management ******************************/
+  if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BT) != 0U))
+  {
+    if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BT) != 0U)
+    {
+      /* Clear the block transfer complete flag */
+      __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BT);
+
+      if(hmdma->XferBlockCpltCallback != NULL)
+      {
+        /* Block transfer callback */
+        hmdma->XferBlockCpltCallback(hmdma);
+      }
+    }
+  }
+
+  /* Repeated Block Transfer Complete Interrupt management ******************************/
+  if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BRT) != 0U))
+  {
+    if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BRT) != 0U)
+    {
+      /* Clear the repeat block transfer complete flag */
+      __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BRT);
+
+      if(hmdma->XferRepeatBlockCpltCallback != NULL)
+      {
+        /* Repeated Block transfer callback */
+        hmdma->XferRepeatBlockCpltCallback(hmdma);
+      }
+    }
+  }
+
+  /* Channel Transfer Complete Interrupt management ***********************************/
+  if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_CTC) != 0U))
+  {
+    if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_CTC) != 0U)
+    {
+      /* Disable all the transfer interrupts */
+      __HAL_MDMA_DISABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC | MDMA_IT_BT | MDMA_IT_BRT | MDMA_IT_BFTC));
+
+      if(HAL_MDMA_STATE_ABORT == hmdma->State)
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hmdma);
+
+        /* Change the DMA state */
+        hmdma->State = HAL_MDMA_STATE_READY;
+
+        if(hmdma->XferAbortCallback != NULL)
+        {
+          hmdma->XferAbortCallback(hmdma);
+        }
+        return;
+      }
+
+      /* Clear the Channel Transfer Complete flag */
+      __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_CTC);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hmdma);
+
+      /* Change MDMA peripheral state */
+      hmdma->State = HAL_MDMA_STATE_READY;
+
+      if(hmdma->XferCpltCallback != NULL)
+      {
+        /* Channel Transfer Complete callback */
+        hmdma->XferCpltCallback(hmdma);
+      }
+    }
+  }
+
+  /* manage error case */
+  if(hmdma->ErrorCode != HAL_MDMA_ERROR_NONE)
+  {
+    hmdma->State = HAL_MDMA_STATE_ABORT;
+
+    /* Disable the channel */
+    __HAL_MDMA_DISABLE(hmdma);
+
+    do
+    {
+      if (++count > timeout)
+      {
+        break;
+      }
+    }
+    while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hmdma);
+
+    if((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U)
+    {
+      /* Change the MDMA state to error if MDMA disable fails */
+      hmdma->State = HAL_MDMA_STATE_ERROR;
+    }
+    else
+    {
+      /* Change the MDMA state to Ready if MDMA disable success */
+      hmdma->State = HAL_MDMA_STATE_READY;
+    }
+
+
+    if (hmdma->XferErrorCallback != NULL)
+    {
+      /* Transfer error callback */
+      hmdma->XferErrorCallback(hmdma);
+    }
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup MDMA_Exported_Functions_Group4
+ *
+@verbatim
+ ===============================================================================
+                    ##### State and Errors functions #####
+ ===============================================================================
+    [..]
+    This subsection provides functions allowing to
+      (+) Check the MDMA state
+      (+) Get error code
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the MDMA state.
+  * @param  hmdma: pointer to a MDMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified MDMA Channel.
+  * @retval HAL state
+  */
+HAL_MDMA_StateTypeDef HAL_MDMA_GetState(MDMA_HandleTypeDef *hmdma)
+{
+  return hmdma->State;
+}
+
+/**
+  * @brief  Return the MDMA error code
+  * @param  hmdma : pointer to a MDMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified MDMA Channel.
+  * @retval MDMA Error Code
+  */
+uint32_t HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma)
+{
+  return hmdma->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup MDMA_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Sets the MDMA Transfer parameter.
+  * @param  hmdma:       pointer to a MDMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified MDMA Channel.
+  * @param  SrcAddress: The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  BlockDataLength : The length of a block transfer in bytes
+  * @param  BlockCount: The number of blocks to be transfered
+  * @retval HAL status
+  */
+static void MDMA_SetConfig(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
+{
+  uint32_t addressMask;
+
+  /* Configure the MDMA Channel data length */
+  MODIFY_REG(hmdma->Instance->CBNDTR ,MDMA_CBNDTR_BNDT, (BlockDataLength & MDMA_CBNDTR_BNDT));
+
+  /* Configure the MDMA block repeat count */
+  MODIFY_REG(hmdma->Instance->CBNDTR , MDMA_CBNDTR_BRC , ((BlockCount - 1U) << MDMA_CBNDTR_BRC_Pos) & MDMA_CBNDTR_BRC);
+
+  /* Clear all interrupt flags */
+  __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_CISR_BRTIF | MDMA_CISR_BTIF | MDMA_CISR_TCIF);
+
+  /* Configure MDMA Channel destination address */
+  hmdma->Instance->CDAR = DstAddress;
+
+  /* Configure MDMA Channel Source address */
+  hmdma->Instance->CSAR = SrcAddress;
+
+  addressMask = SrcAddress & 0xFF000000U;
+  if((addressMask == 0x20000000U) || (addressMask == 0x00000000U))
+  {
+    /*The AHBSbus is used as source (read operation) on channel x */
+    hmdma->Instance->CTBR |= MDMA_CTBR_SBUS;
+  }
+  else
+  {
+    /*The AXI bus is used as source (read operation) on channel x */
+    hmdma->Instance->CTBR &= (~MDMA_CTBR_SBUS);
+  }
+
+  addressMask = DstAddress & 0xFF000000U;
+  if((addressMask == 0x20000000U) || (addressMask == 0x00000000U))
+  {
+    /*The AHB bus is used as destination (write operation) on channel x */
+    hmdma->Instance->CTBR |= MDMA_CTBR_DBUS;
+  }
+  else
+  {
+    /*The AXI bus is used as destination (write operation) on channel x */
+    hmdma->Instance->CTBR &= (~MDMA_CTBR_DBUS);
+  }
+
+  /* Set the linked list register to the first node of the list */
+  hmdma->Instance->CLAR = (uint32_t)hmdma->FirstLinkedListNodeAddress;
+}
+
+/**
+  * @brief  Initializes the MDMA handle according to the specified
+  *         parameters in the MDMA_InitTypeDef
+  * @param  hmdma:       pointer to a MDMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified MDMA Channel.
+  * @retval None
+  */
+static void MDMA_Init(MDMA_HandleTypeDef *hmdma)
+{
+  uint32_t blockoffset;
+
+  /* Prepare the MDMA Channel configuration */
+  hmdma->Instance->CCR = hmdma->Init.Priority  | hmdma->Init.Endianness;
+
+  /* Write new CTCR Register value */
+  hmdma->Instance->CTCR =  hmdma->Init.SourceInc      | hmdma->Init.DestinationInc | \
+                           hmdma->Init.SourceDataSize | hmdma->Init.DestDataSize   | \
+                           hmdma->Init.DataAlignment  | hmdma->Init.SourceBurst    | \
+                           hmdma->Init.DestBurst                                   | \
+                           ((hmdma->Init.BufferTransferLength - 1U) << MDMA_CTCR_TLEN_Pos) | \
+                           hmdma->Init.TransferTriggerMode;
+
+  /* If SW request set the CTCR register to SW Request Mode */
+  if(hmdma->Init.Request == MDMA_REQUEST_SW)
+  {
+    /*
+    -If the request is done by SW : BWM could be set to 1 or 0.
+    -If the request is done by a peripheral :
+    If mask address not set (0) => BWM must be set to 0
+    If mask address set (different than 0) => BWM could be set to 1 or 0
+    */
+    hmdma->Instance->CTCR |= (MDMA_CTCR_SWRM | MDMA_CTCR_BWM);
+  }
+
+  /* Reset CBNDTR Register */
+  hmdma->Instance->CBNDTR = 0;
+
+  /* if block source address offset is negative set the Block Repeat Source address Update Mode to decrement */
+  if(hmdma->Init.SourceBlockAddressOffset < 0)
+  {
+    hmdma->Instance->CBNDTR |= MDMA_CBNDTR_BRSUM;
+    /* Write new CBRUR Register value : source repeat block offset */
+    blockoffset = (uint32_t)(- hmdma->Init.SourceBlockAddressOffset);
+    hmdma->Instance->CBRUR = (blockoffset & 0x0000FFFFU);
+  }
+  else
+  {
+    /* Write new CBRUR Register value : source repeat block offset */
+    hmdma->Instance->CBRUR = (((uint32_t)hmdma->Init.SourceBlockAddressOffset) & 0x0000FFFFU);
+  }
+
+  /* If block destination address offset is negative set the Block Repeat destination address Update Mode to decrement */
+  if(hmdma->Init.DestBlockAddressOffset < 0)
+  {
+    hmdma->Instance->CBNDTR |= MDMA_CBNDTR_BRDUM;
+    /* Write new CBRUR Register value : destination repeat block offset */
+    blockoffset = (uint32_t)(- hmdma->Init.DestBlockAddressOffset);
+    hmdma->Instance->CBRUR |= ((blockoffset & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos);
+  }
+  else
+  {
+    /*write new CBRUR Register value : destination repeat block offset */
+    hmdma->Instance->CBRUR |= ((((uint32_t)hmdma->Init.DestBlockAddressOffset) & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos);
+  }
+
+  /* if HW request set the HW request and the requet CleraMask and ClearData MaskData, */
+  if(hmdma->Init.Request != MDMA_REQUEST_SW)
+  {
+    /* Set the HW request in CTRB register  */
+    hmdma->Instance->CTBR = hmdma->Init.Request & MDMA_CTBR_TSEL;
+  }
+  else /* SW request : reset the CTBR register */
+  {
+    hmdma->Instance->CTBR = 0;
+  }
+
+  /* Write Link Address Register */
+  hmdma->Instance->CLAR =  0;
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_MDMA_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c
new file mode 100644
index 00000000..3a847e87
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c
@@ -0,0 +1,2201 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_pcd.c
+  * @author  MCD Application Team
+  * @brief   PCD HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the USB Peripheral Controller:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State functions
+  *
+  @verbatim
+  ==============================================================================
+                    ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      The PCD HAL driver can be used as follows:
+
+     (#) Declare a PCD_HandleTypeDef handle structure, for example:
+         PCD_HandleTypeDef  hpcd;
+
+     (#) Fill parameters of Init structure in HCD handle
+
+     (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...)
+
+     (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
+         (##) Enable the PCD/USB Low Level interface clock using
+              (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
+              (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode)
+
+         (##) Initialize the related GPIO clocks
+         (##) Configure PCD pin-out
+         (##) Configure PCD NVIC interrupt
+
+     (#)Associate the Upper USB device stack to the HAL PCD Driver:
+         (##) hpcd.pData = pdev;
+
+     (#)Enable PCD transmission and reception:
+         (##) HAL_PCD_Start();
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup PCD PCD
+  * @brief PCD HAL module driver
+  * @{
+  */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PCD_Private_Macros PCD Private Macros
+  * @{
+  */
+#define PCD_MIN(a, b)  (((a) < (b)) ? (a) : (b))
+#define PCD_MAX(a, b)  (((a) > (b)) ? (a) : (b))
+/**
+  * @}
+  */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup PCD_Private_Functions PCD Private Functions
+  * @{
+  */
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum);
+static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum);
+static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum);
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup PCD_Exported_Functions PCD Exported Functions
+  * @{
+  */
+
+/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+            ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the PCD according to the specified
+  *         parameters in the PCD_InitTypeDef and initialize the associated handle.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
+{
+  USB_OTG_GlobalTypeDef *USBx;
+  uint8_t i;
+
+  /* Check the PCD handle allocation */
+  if (hpcd == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
+
+  USBx = hpcd->Instance;
+
+  if (hpcd->State == HAL_PCD_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hpcd->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+    hpcd->SOFCallback = HAL_PCD_SOFCallback;
+    hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;
+    hpcd->ResetCallback = HAL_PCD_ResetCallback;
+    hpcd->SuspendCallback = HAL_PCD_SuspendCallback;
+    hpcd->ResumeCallback = HAL_PCD_ResumeCallback;
+    hpcd->ConnectCallback = HAL_PCD_ConnectCallback;
+    hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;
+    hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback;
+    hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback;
+    hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback;
+    hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback;
+    hpcd->LPMCallback = HAL_PCDEx_LPM_Callback;
+    hpcd->BCDCallback = HAL_PCDEx_BCD_Callback;
+
+    if (hpcd->MspInitCallback == NULL)
+    {
+      hpcd->MspInitCallback = HAL_PCD_MspInit;
+    }
+
+    /* Init the low level hardware */
+    hpcd->MspInitCallback(hpcd);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+    HAL_PCD_MspInit(hpcd);
+#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
+  }
+
+  hpcd->State = HAL_PCD_STATE_BUSY;
+
+  /* Disable DMA mode for FS instance */
+  if ((USBx->CID & (0x1U << 8)) == 0U)
+  {
+    hpcd->Init.dma_enable = 0U;
+  }
+
+  /* Disable the Interrupts */
+  __HAL_PCD_DISABLE(hpcd);
+
+  /*Init the Core (common init.) */
+  if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK)
+  {
+    hpcd->State = HAL_PCD_STATE_ERROR;
+    return HAL_ERROR;
+  }
+
+  /* Force Device Mode*/
+  (void)USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE);
+
+  /* Init endpoints structures */
+  for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
+  {
+    /* Init ep structure */
+    hpcd->IN_ep[i].is_in = 1U;
+    hpcd->IN_ep[i].num = i;
+    hpcd->IN_ep[i].tx_fifo_num = i;
+    /* Control until ep is activated */
+    hpcd->IN_ep[i].type = EP_TYPE_CTRL;
+    hpcd->IN_ep[i].maxpacket = 0U;
+    hpcd->IN_ep[i].xfer_buff = 0U;
+    hpcd->IN_ep[i].xfer_len = 0U;
+  }
+
+  for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
+  {
+    hpcd->OUT_ep[i].is_in = 0U;
+    hpcd->OUT_ep[i].num = i;
+    /* Control until ep is activated */
+    hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
+    hpcd->OUT_ep[i].maxpacket = 0U;
+    hpcd->OUT_ep[i].xfer_buff = 0U;
+    hpcd->OUT_ep[i].xfer_len = 0U;
+  }
+
+  /* Init Device */
+  if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK)
+  {
+    hpcd->State = HAL_PCD_STATE_ERROR;
+    return HAL_ERROR;
+  }
+
+  hpcd->USB_Address = 0U;
+  hpcd->State = HAL_PCD_STATE_READY;
+  
+  /* Activate LPM */
+  if (hpcd->Init.lpm_enable == 1U)
+  {
+    (void)HAL_PCDEx_ActivateLPM(hpcd);
+  }
+  
+  (void)USB_DevDisconnect(hpcd->Instance);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the PCD peripheral.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
+{
+  /* Check the PCD handle allocation */
+  if (hpcd == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  hpcd->State = HAL_PCD_STATE_BUSY;
+
+  /* Stop Device */
+  (void)HAL_PCD_Stop(hpcd);
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+  if (hpcd->MspDeInitCallback == NULL)
+  {
+    hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; /* Legacy weak MspDeInit  */
+  }
+
+  /* DeInit the low level hardware */
+  hpcd->MspDeInitCallback(hpcd);
+#else
+  /* DeInit the low level hardware: CLOCK, NVIC.*/
+  HAL_PCD_MspDeInit(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+  hpcd->State = HAL_PCD_STATE_RESET;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the PCD MSP.
+  * @param  hpcd PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes PCD MSP.
+  * @param  hpcd PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_MspDeInit could be implemented in the user file
+   */
+}
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+/**
+  * @brief  Register a User USB PCD Callback
+  *         To be used instead of the weak predefined callback
+  * @param  hpcd USB PCD handle
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
+  *          @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
+  *          @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
+  *          @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
+  *          @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
+  *          @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
+  *          @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
+  *          @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
+  *          @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_PCD_SOF_CB_ID :
+        hpcd->SOFCallback = pCallback;
+        break;
+
+      case HAL_PCD_SETUPSTAGE_CB_ID :
+        hpcd->SetupStageCallback = pCallback;
+        break;
+
+      case HAL_PCD_RESET_CB_ID :
+        hpcd->ResetCallback = pCallback;
+        break;
+
+      case HAL_PCD_SUSPEND_CB_ID :
+        hpcd->SuspendCallback = pCallback;
+        break;
+
+      case HAL_PCD_RESUME_CB_ID :
+        hpcd->ResumeCallback = pCallback;
+        break;
+
+      case HAL_PCD_CONNECT_CB_ID :
+        hpcd->ConnectCallback = pCallback;
+        break;
+
+      case HAL_PCD_DISCONNECT_CB_ID :
+        hpcd->DisconnectCallback = pCallback;
+        break;
+
+      case HAL_PCD_MSPINIT_CB_ID :
+        hpcd->MspInitCallback = pCallback;
+        break;
+
+      case HAL_PCD_MSPDEINIT_CB_ID :
+        hpcd->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hpcd->State == HAL_PCD_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_PCD_MSPINIT_CB_ID :
+        hpcd->MspInitCallback = pCallback;
+        break;
+
+      case HAL_PCD_MSPDEINIT_CB_ID :
+        hpcd->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+  return status;
+}
+
+/**
+  * @brief  Unregister an USB PCD Callback
+  *         USB PCD callabck is redirected to the weak predefined callback
+  * @param  hpcd USB PCD handle
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
+  *          @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
+  *          @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
+  *          @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
+  *          @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
+  *          @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
+  *          @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
+  *          @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
+  *          @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  /* Setup Legacy weak Callbacks  */
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_PCD_SOF_CB_ID :
+        hpcd->SOFCallback = HAL_PCD_SOFCallback;
+        break;
+
+      case HAL_PCD_SETUPSTAGE_CB_ID :
+        hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;
+        break;
+
+      case HAL_PCD_RESET_CB_ID :
+        hpcd->ResetCallback = HAL_PCD_ResetCallback;
+        break;
+
+      case HAL_PCD_SUSPEND_CB_ID :
+        hpcd->SuspendCallback = HAL_PCD_SuspendCallback;
+        break;
+
+      case HAL_PCD_RESUME_CB_ID :
+        hpcd->ResumeCallback = HAL_PCD_ResumeCallback;
+        break;
+
+      case HAL_PCD_CONNECT_CB_ID :
+        hpcd->ConnectCallback = HAL_PCD_ConnectCallback;
+        break;
+
+      case HAL_PCD_DISCONNECT_CB_ID :
+        hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;
+        break;
+
+      case HAL_PCD_MSPINIT_CB_ID :
+        hpcd->MspInitCallback = HAL_PCD_MspInit;
+        break;
+
+      case HAL_PCD_MSPDEINIT_CB_ID :
+        hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hpcd->State == HAL_PCD_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_PCD_MSPINIT_CB_ID :
+        hpcd->MspInitCallback = HAL_PCD_MspInit;
+        break;
+
+      case HAL_PCD_MSPDEINIT_CB_ID :
+        hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+  return status;
+}
+
+/**
+  * @brief  Register USB PCD Data OUT Stage Callback
+  *         To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback
+  * @param  hpcd PCD handle
+  * @param  pCallback pointer to the USB PCD Data OUT Stage Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->DataOutStageCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the USB PCD Data OUT Stage Callback
+  *         USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; /* Legacy weak DataOutStageCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  Register USB PCD Data IN Stage Callback
+  *         To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback
+  * @param  hpcd PCD handle
+  * @param  pCallback pointer to the USB PCD Data IN Stage Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->DataInStageCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the USB PCD Data IN Stage Callback
+  *         USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; /* Legacy weak DataInStageCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  Register USB PCD Iso OUT incomplete Callback
+  *         To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
+  * @param  hpcd PCD handle
+  * @param  pCallback pointer to the USB PCD Iso OUT incomplete Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->ISOOUTIncompleteCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the USB PCD Iso OUT incomplete Callback
+  *         USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; /* Legacy weak ISOOUTIncompleteCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  Register USB PCD Iso IN incomplete Callback
+  *         To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
+  * @param  hpcd PCD handle
+  * @param  pCallback pointer to the USB PCD Iso IN incomplete Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->ISOINIncompleteCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the USB PCD Iso IN incomplete Callback
+  *         USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; /* Legacy weak ISOINIncompleteCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  Register USB PCD BCD Callback
+  *         To be used instead of the weak HAL_PCDEx_BCD_Callback() predefined callback
+  * @param  hpcd PCD handle
+  * @param  pCallback pointer to the USB PCD BCD Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->BCDCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the USB PCD BCD Callback
+  *         USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->BCDCallback = HAL_PCDEx_BCD_Callback; /* Legacy weak HAL_PCDEx_BCD_Callback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  Register USB PCD LPM Callback
+  *         To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined callback
+  * @param  hpcd PCD handle
+  * @param  pCallback pointer to the USB PCD LPM Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->LPMCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the USB PCD LPM Callback
+  *         USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->LPMCallback = HAL_PCDEx_LPM_Callback; /* Legacy weak HAL_PCDEx_LPM_Callback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions
+ *  @brief   Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the PCD data
+    transfers.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Start the USB device
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
+{
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+  __HAL_LOCK(hpcd);
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+  if ((hpcd->Init.battery_charging_enable == 1U) &&
+      (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY))
+  {
+    /* Enable USB Transceiver */
+    USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
+  }
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+  (void)USB_DevConnect(hpcd->Instance);
+  __HAL_PCD_ENABLE(hpcd);
+  __HAL_UNLOCK(hpcd);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the USB device.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
+{
+  __HAL_LOCK(hpcd);
+  __HAL_PCD_DISABLE(hpcd);
+
+  if (USB_StopDevice(hpcd->Instance) != HAL_OK)
+  {
+    __HAL_UNLOCK(hpcd);
+    return HAL_ERROR;
+  }
+
+  (void)USB_DevDisconnect(hpcd->Instance);
+  __HAL_UNLOCK(hpcd);
+
+  return HAL_OK;
+}
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+/**
+  * @brief  Handles PCD interrupt request.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t i, ep_intr, epint, epnum;
+  uint32_t fifoemptymsk, temp;
+  USB_OTG_EPTypeDef *ep;
+
+  /* ensure that we are in device mode */
+  if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
+  {
+    /* avoid spurious interrupt */
+    if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd))
+    {
+      return;
+    }
+
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))
+    {
+      /* incorrect mode, acknowledge the interrupt */
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);
+    }
+
+     /* Handle RxQLevel Interrupt */
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
+    {
+      USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
+
+      temp = USBx->GRXSTSP;
+
+      ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];
+
+      if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) ==  STS_DATA_UPDT)
+      {
+        if ((temp & USB_OTG_GRXSTSP_BCNT) != 0U)
+        {
+          (void)USB_ReadPacket(USBx, ep->xfer_buff,
+                               (uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4));
+
+          ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
+          ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
+        }
+      }
+      else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) ==  STS_SETUP_UPDT)
+      {
+        (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U);
+        ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
+      }
+      else
+      {
+        /* ... */
+      }
+      USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
+    }
+
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))
+    {
+      epnum = 0U;
+
+      /* Read in the device interrupt bits */
+      ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance);
+
+      while (ep_intr != 0U)
+      {
+        if ((ep_intr & 0x1U) != 0U)
+        {
+          epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum);
+
+          if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC)
+          {
+            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC);
+            (void)PCD_EP_OutXfrComplete_int(hpcd, epnum);
+          }
+
+          if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)
+          {
+            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
+            /* Class B setup phase done for previous decoded setup */
+            (void)PCD_EP_OutSetupPacket_int(hpcd, epnum);
+          }
+
+          if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)
+          {
+            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);
+          }
+
+          /* Clear Status Phase Received interrupt */
+          if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
+          {
+            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
+          }
+
+          /* Clear OUT NAK interrupt */
+          if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK)
+          {
+            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK);
+          }
+        }
+        epnum++;
+        ep_intr >>= 1U;
+      }
+    }
+
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT))
+    {
+      /* Read in the device interrupt bits */
+      ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance);
+
+      epnum = 0U;
+
+      while (ep_intr != 0U)
+      {
+        if ((ep_intr & 0x1U) != 0U) /* In ITR */
+        {
+          epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum);
+
+          if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)
+          {
+            fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK));
+            USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
+
+            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);
+
+            if (hpcd->Init.dma_enable == 1U)
+            {
+              hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket;
+
+              /* this is ZLP, so prepare EP0 for next setup */
+              if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U))
+              {
+                /* prepare to rx more setup packets */
+                (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
+              }
+            }
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+            hpcd->DataInStageCallback(hpcd, (uint8_t)epnum);
+#else
+            HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+          }
+          if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)
+          {
+            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC);
+          }
+          if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE)
+          {
+            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE);
+          }
+          if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE)
+          {
+            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE);
+          }
+          if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD)
+          {
+            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD);
+          }
+          if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)
+          {
+            (void)PCD_WriteEmptyTxFifo(hpcd, epnum);
+          }
+        }
+        epnum++;
+        ep_intr >>= 1U;
+      }
+    }
+
+    /* Handle Resume Interrupt */
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))
+    {
+      /* Clear the Remote Wake-up Signaling */
+      USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
+
+      if (hpcd->LPM_State == LPM_L1)
+      {
+        hpcd->LPM_State = LPM_L0;
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+        hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE);
+#else
+        HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+      }
+      else
+      {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+        hpcd->ResumeCallback(hpcd);
+#else
+        HAL_PCD_ResumeCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+      }
+
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);
+    }
+
+    /* Handle Suspend Interrupt */
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))
+    {
+      if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
+      {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+        hpcd->SuspendCallback(hpcd);
+#else
+        HAL_PCD_SuspendCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+      }
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);
+    }
+    
+    /* Handle LPM Interrupt */
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT))
+    {
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT);
+
+      if (hpcd->LPM_State == LPM_L0)
+      {
+        hpcd->LPM_State = LPM_L1;
+        hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U;
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+        hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE);
+#else
+        HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+      }
+      else
+      {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+        hpcd->SuspendCallback(hpcd);
+#else
+        HAL_PCD_SuspendCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+      }
+    }
+    
+    /* Handle Reset Interrupt */
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
+    {
+      USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
+      (void)USB_FlushTxFifo(hpcd->Instance, 0x10U);
+
+      for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
+      {
+        USBx_INEP(i)->DIEPINT = 0xFB7FU;
+        USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
+        USBx_INEP(i)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
+        USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
+        USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
+        USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
+      }
+      USBx_DEVICE->DAINTMSK |= 0x10001U;
+
+      if (hpcd->Init.use_dedicated_ep1 != 0U)
+      {
+        USBx_DEVICE->DOUTEP1MSK |= USB_OTG_DOEPMSK_STUPM |
+                                   USB_OTG_DOEPMSK_XFRCM |
+                                   USB_OTG_DOEPMSK_EPDM;
+
+        USBx_DEVICE->DINEP1MSK |= USB_OTG_DIEPMSK_TOM |
+                                  USB_OTG_DIEPMSK_XFRCM |
+                                  USB_OTG_DIEPMSK_EPDM;
+      }
+      else
+      {
+        USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM |
+                                USB_OTG_DOEPMSK_XFRCM |
+                                USB_OTG_DOEPMSK_EPDM |
+                                USB_OTG_DOEPMSK_OTEPSPRM |
+                                USB_OTG_DOEPMSK_NAKM;
+
+        USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM |
+                                USB_OTG_DIEPMSK_XFRCM |
+                                USB_OTG_DIEPMSK_EPDM;
+      }
+
+      /* Set Default Address to 0 */
+      USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD;
+
+      /* setup EP0 to receive SETUP packets */
+      (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable,
+                             (uint8_t *)hpcd->Setup);
+
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST);
+    }
+
+    /* Handle Enumeration done Interrupt */
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))
+    {
+      (void)USB_ActivateSetup(hpcd->Instance);
+      hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance);
+
+      /* Set USB Turnaround time */
+      (void)USB_SetTurnaroundTime(hpcd->Instance,
+                                  HAL_RCC_GetHCLKFreq(),
+                                  (uint8_t)hpcd->Init.speed);
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+      hpcd->ResetCallback(hpcd);
+#else
+      HAL_PCD_ResetCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);
+    }
+
+    /* Handle SOF Interrupt */
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))
+    {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+      hpcd->SOFCallback(hpcd);
+#else
+      HAL_PCD_SOFCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF);
+    }
+
+    /* Handle Incomplete ISO IN Interrupt */
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))
+    {
+      /* Keep application checking the corresponding Iso IN endpoint
+      causing the incomplete Interrupt */
+      epnum = 0U;
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+      hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
+#else
+      HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR);
+    }
+
+    /* Handle Incomplete ISO OUT Interrupt */
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
+    {
+      /* Keep application checking the corresponding Iso OUT endpoint
+      causing the incomplete Interrupt */
+      epnum = 0U;
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+      hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
+#else
+      HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
+    }
+
+    /* Handle Connection event Interrupt */
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT))
+    {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+      hpcd->ConnectCallback(hpcd);
+#else
+      HAL_PCD_ConnectCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT);
+    }
+
+    /* Handle Disconnection event Interrupt */
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))
+    {
+      temp = hpcd->Instance->GOTGINT;
+
+      if ((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)
+      {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+        hpcd->DisconnectCallback(hpcd);
+#else
+        HAL_PCD_DisconnectCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+      }
+      hpcd->Instance->GOTGINT |= temp;
+    }
+  }
+}
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+
+/**
+  * @brief  Data OUT stage callback.
+  * @param  hpcd PCD handle
+  * @param  epnum endpoint number
+  * @retval None
+  */
+__weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(epnum);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_DataOutStageCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Data IN stage callback
+  * @param  hpcd PCD handle
+  * @param  epnum endpoint number
+  * @retval None
+  */
+__weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(epnum);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_DataInStageCallback could be implemented in the user file
+   */
+}
+/**
+  * @brief  Setup stage callback
+  * @param  hpcd PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_SetupStageCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  USB Start Of Frame callback.
+  * @param  hpcd PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_SOFCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  USB Reset callback.
+  * @param  hpcd PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_ResetCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Suspend event callback.
+  * @param  hpcd PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_SuspendCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Resume event callback.
+  * @param  hpcd PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_ResumeCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Incomplete ISO OUT callback.
+  * @param  hpcd PCD handle
+  * @param  epnum endpoint number
+  * @retval None
+  */
+__weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(epnum);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Incomplete ISO IN callback.
+  * @param  hpcd PCD handle
+  * @param  epnum endpoint number
+  * @retval None
+  */
+__weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(epnum);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Connection event callback.
+  * @param  hpcd PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_ConnectCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Disconnection event callback.
+  * @param  hpcd PCD handle
+  * @retval None
+  */
+__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCD_DisconnectCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
+ *  @brief   management functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the PCD data
+    transfers.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Connect the USB device
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
+{
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+  __HAL_LOCK(hpcd);
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+  if ((hpcd->Init.battery_charging_enable == 1U) &&
+      (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY))
+  {
+    /* Enable USB Transceiver */
+    USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
+  }
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+  (void)USB_DevConnect(hpcd->Instance);
+  __HAL_UNLOCK(hpcd);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disconnect the USB device.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
+{
+  __HAL_LOCK(hpcd);
+  (void)USB_DevDisconnect(hpcd->Instance);
+  __HAL_UNLOCK(hpcd);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the USB Device address.
+  * @param  hpcd PCD handle
+  * @param  address new device address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
+{
+  __HAL_LOCK(hpcd);
+  hpcd->USB_Address = address;
+  (void)USB_SetDevAddress(hpcd->Instance, address);
+  __HAL_UNLOCK(hpcd);
+  return HAL_OK;
+}
+/**
+  * @brief  Open and configure an endpoint.
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
+  * @param  ep_mps endpoint max packet size
+  * @param  ep_type endpoint type
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
+{
+  HAL_StatusTypeDef  ret = HAL_OK;
+  PCD_EPTypeDef *ep;
+
+  if ((ep_addr & 0x80U) == 0x80U)
+  {
+    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+    ep->is_in = 1U;
+  }
+  else
+  {
+    ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
+    ep->is_in = 0U;
+  }
+
+  ep->num = ep_addr & EP_ADDR_MSK;
+  ep->maxpacket = ep_mps;
+  ep->type = ep_type;
+
+  if (ep->is_in != 0U)
+  {
+    /* Assign a Tx FIFO */
+    ep->tx_fifo_num = ep->num;
+  }
+  /* Set initial data PID. */
+  if (ep_type == EP_TYPE_BULK)
+  {
+    ep->data_pid_start = 0U;
+  }
+
+  __HAL_LOCK(hpcd);
+  (void)USB_ActivateEndpoint(hpcd->Instance, ep);
+  __HAL_UNLOCK(hpcd);
+
+  return ret;
+}
+
+/**
+  * @brief  Deactivate an endpoint.
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+  PCD_EPTypeDef *ep;
+
+  if ((ep_addr & 0x80U) == 0x80U)
+  {
+    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+    ep->is_in = 1U;
+  }
+  else
+  {
+    ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
+    ep->is_in = 0U;
+  }
+  ep->num   = ep_addr & EP_ADDR_MSK;
+
+  __HAL_LOCK(hpcd);
+  (void)USB_DeactivateEndpoint(hpcd->Instance, ep);
+  __HAL_UNLOCK(hpcd);
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Receive an amount of data.
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
+  * @param  pBuf pointer to the reception buffer
+  * @param  len amount of data to be received
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
+{
+  PCD_EPTypeDef *ep;
+
+  ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
+
+  /*setup and start the Xfer */
+  ep->xfer_buff = pBuf;
+  ep->xfer_len = len;
+  ep->xfer_count = 0U;
+  ep->is_in = 0U;
+  ep->num = ep_addr & EP_ADDR_MSK;
+
+  if (hpcd->Init.dma_enable == 1U)
+  {
+    ep->dma_addr = (uint32_t)pBuf;
+  }
+
+  if ((ep_addr & EP_ADDR_MSK) == 0U)
+  {
+    (void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
+  }
+  else
+  {
+    (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get Received Data Size
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
+  * @retval Data Size
+  */
+uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+  return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count;
+}
+/**
+  * @brief  Send an amount of data
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
+  * @param  pBuf pointer to the transmission buffer
+  * @param  len amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
+{
+  PCD_EPTypeDef *ep;
+
+  ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+
+  /*setup and start the Xfer */
+  ep->xfer_buff = pBuf;
+  ep->xfer_len = len;
+  ep->xfer_count = 0U;
+  ep->is_in = 1U;
+  ep->num = ep_addr & EP_ADDR_MSK;
+
+  if (hpcd->Init.dma_enable == 1U)
+  {
+    ep->dma_addr = (uint32_t)pBuf;
+  }
+
+  if ((ep_addr & EP_ADDR_MSK) == 0U)
+  {
+    (void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
+  }
+  else
+  {
+    (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set a STALL condition over an endpoint
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+  PCD_EPTypeDef *ep;
+
+  if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints)
+  {
+    return HAL_ERROR;
+  }
+
+  if ((0x80U & ep_addr) == 0x80U)
+  {
+    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+    ep->is_in = 1U;
+  }
+  else
+  {
+    ep = &hpcd->OUT_ep[ep_addr];
+    ep->is_in = 0U;
+  }
+
+  ep->is_stall = 1U;
+  ep->num = ep_addr & EP_ADDR_MSK;
+
+  __HAL_LOCK(hpcd);
+
+  (void)USB_EPSetStall(hpcd->Instance, ep);
+  if ((ep_addr & EP_ADDR_MSK) == 0U)
+  {
+    (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
+  }
+  __HAL_UNLOCK(hpcd);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Clear a STALL condition over in an endpoint
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+  PCD_EPTypeDef *ep;
+
+  if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints)
+  {
+    return HAL_ERROR;
+  }
+
+  if ((0x80U & ep_addr) == 0x80U)
+  {
+    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+    ep->is_in = 1U;
+  }
+  else
+  {
+    ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
+    ep->is_in = 0U;
+  }
+
+  ep->is_stall = 0U;
+  ep->num = ep_addr & EP_ADDR_MSK;
+
+  __HAL_LOCK(hpcd);
+  (void)USB_EPClearStall(hpcd->Instance, ep);
+  __HAL_UNLOCK(hpcd);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Flush an endpoint
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+  __HAL_LOCK(hpcd);
+
+  if ((ep_addr & 0x80U) == 0x80U)
+  {
+    (void)USB_FlushTxFifo(hpcd->Instance, (uint32_t)ep_addr & EP_ADDR_MSK);
+  }
+  else
+  {
+    (void)USB_FlushRxFifo(hpcd->Instance);
+  }
+
+  __HAL_UNLOCK(hpcd);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Activate remote wakeup signalling
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
+{
+  return (USB_ActivateRemoteWakeup(hpcd->Instance));
+}
+
+/**
+  * @brief  De-activate remote wakeup signalling.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
+{
+  return (USB_DeActivateRemoteWakeup(hpcd->Instance));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
+ *  @brief   Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral State functions #####
+ ===============================================================================
+    [..]
+    This subsection permits to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the PCD handle state.
+  * @param  hpcd PCD handle
+  * @retval HAL state
+  */
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
+{
+  return hpcd->State;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup PCD_Private_Functions
+  * @{
+  */
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+/**
+  * @brief  Check FIFO for the next packet to be loaded.
+  * @param  hpcd PCD handle
+  * @param  epnum endpoint number
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  USB_OTG_EPTypeDef *ep;
+  uint32_t len;
+  uint32_t len32b;
+  uint32_t fifoemptymsk;
+
+  ep = &hpcd->IN_ep[epnum];
+
+  if (ep->xfer_count > ep->xfer_len)
+  {
+    return HAL_ERROR;
+  }
+
+  len = ep->xfer_len - ep->xfer_count;
+
+  if (len > ep->maxpacket)
+  {
+    len = ep->maxpacket;
+  }
+
+  len32b = (len + 3U) / 4U;
+
+  while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) &&
+         (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U))
+  {
+    /* Write the FIFO */
+    len = ep->xfer_len - ep->xfer_count;
+
+    if (len > ep->maxpacket)
+    {
+      len = ep->maxpacket;
+    }
+    len32b = (len + 3U) / 4U;
+
+    (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len,
+                          (uint8_t)hpcd->Init.dma_enable);
+
+    ep->xfer_buff  += len;
+    ep->xfer_count += len;
+  }
+
+  if (ep->xfer_len <= ep->xfer_count)
+  {
+    fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK));
+    USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
+  }
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  process EP OUT transfer complete interrupt.
+  * @param  hpcd PCD handle
+  * @param  epnum endpoint number
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
+  uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
+
+  if (hpcd->Init.dma_enable == 1U)
+  {
+    if ((DoepintReg & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) /* Class C */
+    {
+      /* StupPktRcvd = 1 this is a setup packet */
+      if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
+          ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
+      {
+        CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
+      }
+    }
+    else if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) /* Class E */
+    {
+      CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
+    }
+    else if ((DoepintReg & (USB_OTG_DOEPINT_STUP | USB_OTG_DOEPINT_OTEPSPR)) == 0U)
+    {
+      /* StupPktRcvd = 1 this is a setup packet */
+      if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
+          ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
+      {
+        CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
+      }
+      else
+      {
+        /* out data packet received over EP0 */
+        hpcd->OUT_ep[epnum].xfer_count =
+          hpcd->OUT_ep[epnum].maxpacket -
+          (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ);
+
+        hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket;
+
+        if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U))
+        {
+          /* this is ZLP, so prepare EP0 for next setup */
+          (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
+        }
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+        hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
+#else
+        HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+      }
+    }
+    else
+    {
+      /* ... */
+    }
+  }
+  else
+  {
+    if (gSNPSiD == USB_OTG_CORE_ID_310A)
+    {
+      /* StupPktRcvd = 1 this is a setup packet */
+      if ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)
+      {
+        CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
+      }
+      else
+      {
+        if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
+        {
+          CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
+        }
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+        hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
+#else
+        HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+      }
+    }
+    else
+    {
+      if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U))
+      {
+        /* this is ZLP, so prepare EP0 for next setup */
+        (void)USB_EP0_OutStart(hpcd->Instance, 0U, (uint8_t *)hpcd->Setup);
+      }
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+      hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
+#else
+      HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+    }
+  }
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  process EP OUT setup packet received interrupt.
+  * @param  hpcd PCD handle
+  * @param  epnum endpoint number
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
+  uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
+
+  if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
+      ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
+  {
+    CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
+  }
+
+  /* Inform the upper layer that a setup packet is available */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+  hpcd->SetupStageCallback(hpcd);
+#else
+  HAL_PCD_SetupStageCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+  if ((gSNPSiD > USB_OTG_CORE_ID_300A) && (hpcd->Init.dma_enable == 1U))
+  {
+    (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
+  }
+
+  return HAL_OK;
+}
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+
+/**
+  * @}
+  */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c
new file mode 100644
index 00000000..17d3d5b0
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c
@@ -0,0 +1,348 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_pcd_ex.c
+  * @author  MCD Application Team
+  * @brief   PCD Extended HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the USB Peripheral Controller:
+  *           + Extended features functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup PCDEx PCDEx
+  * @brief PCD Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
+  * @{
+  */
+
+/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
+  * @brief    PCDEx control functions
+ *
+@verbatim
+ ===============================================================================
+                 ##### Extended features functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Update FIFO configuration
+
+@endverbatim
+  * @{
+  */
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+/**
+  * @brief  Set Tx FIFO
+  * @param  hpcd PCD handle
+  * @param  fifo The number of Tx fifo
+  * @param  size Fifo size
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
+{
+  uint8_t i;
+  uint32_t Tx_Offset;
+
+  /*  TXn min size = 16 words. (n  : Transmit FIFO index)
+      When a TxFIFO is not used, the Configuration should be as follows:
+          case 1 :  n > m    and Txn is not used    (n,m  : Transmit FIFO indexes)
+         --> Txm can use the space allocated for Txn.
+         case2  :  n < m    and Txn is not used    (n,m  : Transmit FIFO indexes)
+         --> Txn should be configured with the minimum space of 16 words
+     The FIFO is used optimally when used TxFIFOs are allocated in the top
+         of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
+     When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */
+
+  Tx_Offset = hpcd->Instance->GRXFSIZ;
+
+  if (fifo == 0U)
+  {
+    hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset;
+  }
+  else
+  {
+    Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;
+    for (i = 0U; i < (fifo - 1U); i++)
+    {
+      Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16);
+    }
+
+    /* Multiply Tx_Size by 2 to get higher performance */
+    hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set Rx FIFO
+  * @param  hpcd PCD handle
+  * @param  size Size of Rx fifo
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
+{
+  hpcd->Instance->GRXFSIZ = size;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Activate LPM feature.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+
+  hpcd->lpm_active = 1U;
+  hpcd->LPM_State = LPM_L0;
+  USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;
+  USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deactivate LPM feature.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+
+  hpcd->lpm_active = 0U;
+  USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM;
+  USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Handle BatteryCharging Process.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Enable DCD : Data Contact Detect */
+  USBx->GCCFG |= USB_OTG_GCCFG_DCDEN;
+
+  /* Wait Detect flag or a timeout is happen*/
+  while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0U)
+  {
+    /* Check for the Timeout */
+    if ((HAL_GetTick() - tickstart) > 1000U)
+    {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+      hpcd->BCDCallback(hpcd, PCD_BCD_ERROR);
+#else
+      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+      return;
+    }
+  }
+
+  /* Right response got */
+  HAL_Delay(200U);
+
+  /* Check Detect flag*/
+  if ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == USB_OTG_GCCFG_DCDET)
+  {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+    hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION);
+#else
+    HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+  }
+
+  /*Primary detection: checks if connected to Standard Downstream Port
+  (without charging capability) */
+  USBx->GCCFG &= ~ USB_OTG_GCCFG_DCDEN;
+  HAL_Delay(50U);
+  USBx->GCCFG |=  USB_OTG_GCCFG_PDEN;
+  HAL_Delay(50U);
+
+  if ((USBx->GCCFG & USB_OTG_GCCFG_PDET) == 0U)
+  {
+    /* Case of Standard Downstream Port */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+    hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
+#else
+    HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    /* start secondary detection to check connection to Charging Downstream
+    Port or Dedicated Charging Port */
+    USBx->GCCFG &= ~ USB_OTG_GCCFG_PDEN;
+    HAL_Delay(50U);
+    USBx->GCCFG |=  USB_OTG_GCCFG_SDEN;
+    HAL_Delay(50U);
+
+    if ((USBx->GCCFG & USB_OTG_GCCFG_SDET) == USB_OTG_GCCFG_SDET)
+    {
+      /* case Dedicated Charging Port  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+      hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
+#else
+      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+    }
+    else
+    {
+      /* case Charging Downstream Port  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+      hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
+#else
+      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Battery Charging capability discovery finished */
+  (void)HAL_PCDEx_DeActivateBCD(hpcd);
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+  hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
+#else
+  HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  Activate BatteryCharging feature.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+
+  USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN);
+  USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN);
+
+  /* Power Down USB tranceiver  */
+  USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
+
+  /* Enable Battery charging */
+  USBx->GCCFG |= USB_OTG_GCCFG_BCDEN;
+
+  hpcd->battery_charging_active = 1U;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deactivate BatteryCharging feature.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+
+  USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN);
+  USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN);
+
+  /* Disable Battery charging */
+  USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN);
+
+  hpcd->battery_charging_active = 0U;
+
+  return HAL_OK;
+}
+
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+/**
+  * @brief  Send LPM message to user layer callback.
+  * @param  hpcd PCD handle
+  * @param  msg LPM message
+  * @retval HAL status
+  */
+__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(msg);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCDEx_LPM_Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Send BatteryCharging message to user layer callback.
+  * @param  hpcd PCD handle
+  * @param  msg LPM message
+  * @retval HAL status
+  */
+__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(msg);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCDEx_BCD_Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c
new file mode 100644
index 00000000..43d9052a
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c
@@ -0,0 +1,868 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_pwr.c
+  * @author  MCD Application Team
+  * @brief   PWR HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Power Controller (PWR) peripheral:
+  *           + Initialization and de-initialization functions.
+  *           + Peripheral Control functions.
+  *           + Interrupt Handling functions.
+  @verbatim
+  ==============================================================================
+                        ##### PWR peripheral overview #####
+  ==============================================================================
+  [..]
+   (#) The Power control (PWR) provides an overview of the supply architecture
+       for the different power domains and of the supply configuration
+       controller.
+       In the H7 family, the number of power domains is different between
+       device lines. This difference is due to characteristics of each device.
+
+   (#) Domain architecture overview for the different H7 lines:
+      (+) Dual core lines are STM32H745, STM32H747, STM32H755 and STM32H757.
+          These devices have 3 power domains (D1, D2 and D3).
+          The domain D1 contains a CPU (Cortex-M7), a Flash memory and some
+          peripherals. The D2 domain contains peripherals and a CPU
+          (Cortex-M4). The D3 domain contains the system control, I/O logic
+          and low-power peripherals.
+      (+) STM32H743, STM32H753, STM32H742 and STM32H750 devices have 3 power
+          domains (D1, D2 and D3).
+          The domain D1 contains a CPU (Cortex-M7), a Flash memory and some
+          peripherals. The D2 domain contains peripherals. The D3 domains
+          contains the system control, I/O logic and low-power peripherals.
+      (+) STM32H7AxxQ, STM32H7BxxQ, STM32H7Axxx and STM32H7Bxxx devices have 2
+          power domains (CD and SRD).
+          The core domain (CD) contains a CPU (Cortex-M7), a Flash
+          memory and peripherals. The SmartRun domain contains the system
+          control, I/O logic and low-power peripherals.
+
+   (#) Every entity have low power mode as decribed below :
+   (#) The CPU low power modes are :
+      (+) CPU CRUN.
+      (+) CPU CSLEEP.
+      (+) CPU CSTOP.
+   (#) The domain low power modes are :
+      (+) DRUN.
+      (+) DSTOP.
+      (+) DSTANDBY.
+   (#) The SYSTEM low power modes are :
+      (+) RUN* : The Run* mode is entered after a POR reset and a wakeup from
+                 Standby. In Run* mode, the performance is limited and the
+                 system supply configuration shall be programmed. The system
+                 enters Run mode only when the ACTVOSRDY bit in PWR control
+                 status register 1 (PWR_CSR1) is set to 1.
+      (+) RUN.
+      (+) STOP.
+      (+) STANDBY.
+
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+   (#) Power management peripheral is active by default at startup level in
+       STM32h7xx lines.
+
+   (#) Call HAL_PWR_EnableBkUpAccess() and HAL_PWR_DisableBkUpAccess() functions
+       to enable/disable access to the backup domain (RTC registers, RTC backup
+       data registers and backup SRAM).
+
+   (#) Call HAL_PWR_ConfigPVD() after setting parameters to be configured (event
+       mode and voltage threshold) in order to set up the Power Voltage Detector,
+       then use HAL_PWR_EnablePVD() and  HAL_PWR_DisablePVD() functions to start
+       and stop the PVD detection.
+       (+) PVD level could be one of the following values :
+             (++) 1V95
+             (++) 2V1
+             (++) 2V25
+             (++) 2V4
+             (++) 2V55
+             (++) 2V7
+             (++) 2V85
+             (++) External voltage level
+
+   (#) Call HAL_PWR_EnableWakeUpPin() and HAL_PWR_DisableWakeUpPin() functions
+       with the right parameter to configure the wake up pin polarity (Low or
+       High) and to enable and disable it.
+
+   (#) Call HAL_PWR_EnterSLEEPMode() function to enter the current Core in SLEEP
+       mode. Wake-up from SLEEP mode could be following to an event or an
+       interrupt according to low power mode intrinsic request called (__WFI()
+       or __WFE()).
+       Please ensure to clear all CPU pending events by calling
+       HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx
+       in SLEEP mode with __WFE() entry.
+
+   (#) Call HAL_PWR_EnterSTOPMode() function to enter the whole system to Stop 0
+       mode for single core devices. For dual core devices, this API will enter
+       the domain (containing Cortex-Mx that executing this function) in DSTOP
+       mode. According to the used parameter, user could select the regulator to
+       be kept actif in low power mode and wake-up event type.
+       Please ensure to clear all CPU pending events by calling
+       HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx
+       in CSTOP mode with __WFE() entry.
+
+   (#) Call HAL_PWR_EnterSTANDBYMode() function to enter the whole system in
+       STANDBY mode for single core devices. For dual core devices, this API
+       will enter the domain (containing Cortex-Mx that executing this function)
+       in DSTANDBY mode.
+
+   (#) Call HAL_PWR_EnableSleepOnExit() and HAL_PWR_DisableSleepOnExit() APIs to
+       enable and disable the Cortex-Mx re-entring in SLEEP mode after an
+       interruption handling is over.
+
+   (#) Call HAL_PWR_EnableSEVOnPend() and HAL_PWR_DisableSEVOnPend() functions
+       to configure the Cortex-Mx to wake-up after any pending event / interrupt
+       even if it's disabled or has insufficient priority to cause exception
+       entry.
+
+   (#) Call HAL_PWR_PVD_IRQHandler() function to handle the PWR PVD interrupt
+       request.
+
+     *** PWR HAL driver macros list ***
+     =============================================
+     [..]
+       Below the list of most used macros in PWR HAL driver.
+
+      (+) __HAL_PWR_VOLTAGESCALING_CONFIG() : Configure the main internal
+                                              regulator output voltage.
+      (+) __HAL_PWR_GET_FLAG()              : Get the PWR pending flags.
+      (+) __HAL_PWR_CLEAR_FLAG()            : Clear the PWR pending flags.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup PWR PWR
+  * @brief PWR HAL module driver
+  * @{
+  */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @addtogroup PWR_Private_Constants PWR Private Constants
+  * @{
+  */
+
+/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
+  * @{
+  */
+#if !defined (DUAL_CORE)
+#define PVD_MODE_IT              (0x00010000U)
+#define PVD_MODE_EVT             (0x00020000U)
+#endif /* !defined (DUAL_CORE) */
+
+#define PVD_RISING_EDGE          (0x00000001U)
+#define PVD_FALLING_EDGE         (0x00000002U)
+#define PVD_RISING_FALLING_EDGE  (0x00000003U)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Functions PWR Exported Functions
+  * @{
+  */
+
+/** @defgroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions
+  * @brief    Initialization and De-Initialization functions
+  *
+@verbatim
+ ===============================================================================
+              ##### Initialization and De-Initialization Functions #####
+ ===============================================================================
+    [..]
+      This section provides functions allowing to deinitialize power peripheral.
+
+    [..]
+      After system reset, the backup domain (RTC registers, RTC backup data
+      registers and backup SRAM) is protected against possible unwanted write
+      accesses.
+      The HAL_PWR_EnableBkUpAccess() function enables the access to the backup
+      domain.
+      The HAL_PWR_DisableBkUpAccess() function disables the access to the backup
+      domain.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitialize the HAL PWR peripheral registers to their default reset
+  *         values.
+  * @note   This functionality is not available in this product.
+  *         The prototype is kept just to maintain compatibility with other
+  *         products.
+  * @retval None.
+  */
+void HAL_PWR_DeInit (void)
+{
+}
+
+/**
+  * @brief  Enable access to the backup domain (RTC registers, RTC backup data
+  *         registers and backup SRAM).
+  * @note   If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
+  *         Backup Domain Access should be kept enabled.
+  * @retval None.
+  */
+void HAL_PWR_EnableBkUpAccess (void)
+{
+  /* Enable access to RTC and backup registers */
+  SET_BIT (PWR->CR1, PWR_CR1_DBP);
+}
+
+/**
+  * @brief  Disable access to the backup domain (RTC registers, RTC backup data
+  *         registers and backup SRAM).
+  * @note   If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
+  *         Backup Domain Access should be kept enabled.
+  * @retval None.
+  */
+void HAL_PWR_DisableBkUpAccess (void)
+{
+  /* Disable access to RTC and backup registers */
+  CLEAR_BIT (PWR->CR1, PWR_CR1_DBP);
+}
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control Functions
+  *  @brief   Power Control functions
+  *
+@verbatim
+ ===============================================================================
+                 ##### Peripheral Control Functions #####
+ ===============================================================================
+    [..]
+      This section provides functions allowing to control power peripheral.
+
+    *** PVD configuration ***
+    =========================
+    [..]
+      (+) The PVD is used to monitor the VDD power supply by comparing it to a
+          threshold selected by the PVD Level (PLS[7:0] bits in the PWR_CR1
+          register).
+
+      (+) A PVDO flag is available to indicate if VDD is higher or lower
+          than the PVD threshold. This event is internally connected to the EXTI
+          line 16 to generate an interrupt if enabled.
+          It is configurable through __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
+
+      (+) The PVD is stopped in STANDBY mode.
+
+    *** Wake-up pin configuration ***
+    =================================
+    [..]
+      (+) Wake-up pin is used to wake up the system from STANDBY mode.
+          The pin pull is configurable through the WKUPEPR register to be in
+          No-pull, Pull-up and Pull-down.
+          The pin polarity is configurable through the WKUPEPR register to be
+          active on rising or falling edges.
+
+      (+) There are up to six Wake-up pin in the STM32H7 devices family.
+
+    *** Low Power modes configuration ***
+    =====================================
+    [..]
+     The device present 3 principles low-power modes features:
+      (+) SLEEP mode   : Cortex-Mx is stopped and all PWR domains are remaining
+                         active (Powered and Clocked).
+
+      (+) STOP mode    : Cortex-Mx is stopped, clocks are stopped and the
+                         regulator is running. The Main regulator or the LP
+                         regulator could be selected.
+
+      (+) STANDBY mode : All PWR domains enter DSTANDBY mode and the VCORE
+                         supply regulator is powered off.
+
+   *** SLEEP mode ***
+   ==================
+    [..]
+      (+) Entry:
+        The SLEEP mode is entered by using the HAL_PWR_EnterSLEEPMode(Regulator,
+        SLEEPEntry) function.
+
+          (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction.
+          (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction.
+
+      -@@- The Regulator parameter is not used for the STM32H7 family
+              and is kept as parameter just to maintain compatibility with the
+              lower power families (STM32L).
+
+      (+) Exit:
+        Any peripheral interrupt acknowledged by the nested vectored interrupt
+        controller (NVIC) can wake up the device from SLEEP mode.
+
+   *** STOP mode ***
+   =================
+    [..]
+      In system STOP mode, all clocks in the 1.2V domain are stopped, the PLL,
+      the HSI, and the HSE RC oscillators are disabled. Internal SRAM and
+      register contents are preserved.
+      The voltage regulator can be configured either in normal or low-power mode.
+      To minimize the consumption in STOP mode, FLASH can be powered off before
+      entering the STOP mode using the HAL_PWREx_EnableFlashPowerDown() function.
+      It can be switched on again by software after exiting the STOP mode using
+      the HAL_PWREx_DisableFlashPowerDown() function.
+
+      (+) Entry:
+         The STOP mode is entered using the HAL_PWR_EnterSTOPMode(Regulator,
+         STOPEntry) function with:
+
+         (++) Regulator:
+          (+++) PWR_MAINREGULATOR_ON: Main regulator ON.
+          (+++) PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON.
+
+         (++) STOPEntry:
+          (+++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction.
+          (+++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction.
+
+      (+) Exit:
+         Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
+
+   *** STANDBY mode ***
+   ====================
+    [..]
+    (+)
+      The system STANDBY mode allows to achieve the lowest power consumption.
+      It is based on the Cortex-Mx deep SLEEP mode, with the voltage regulator
+      disabled. The system is consequently powered off. The PLL, the HSI
+      oscillator and the HSE oscillator are also switched off. SRAM and register
+      contents are lost except for the RTC registers, RTC backup registers,
+      backup SRAM and standby circuitry.
+
+    [..]
+      The voltage regulator is OFF.
+
+      (++) Entry:
+        (+++) The STANDBY mode is entered using the HAL_PWR_EnterSTANDBYMode()
+              function.
+
+      (++) Exit:
+        (+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B),
+              RTC wakeup, tamper event, time stamp event, external reset in NRST
+              pin, IWDG reset.
+
+   *** Auto-wakeup (AWU) from low-power mode ***
+   =============================================
+    [..]
+     (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an
+         RTC Wakeup event, a tamper event or a time-stamp event, without
+         depending on an external interrupt (Auto-wakeup mode).
+
+     (+) RTC auto-wakeup (AWU) from the STOP and STANDBY modes
+
+       (++) To wake up from the STOP mode with an RTC alarm event, it is
+            necessary to configure the RTC to generate the RTC alarm using the
+            HAL_RTC_SetAlarm_IT() function.
+
+       (++) To wake up from the STOP mode with an RTC Tamper or time stamp event,
+            it is necessary to configure the RTC to detect the tamper or time
+            stamp event using the HAL_RTCEx_SetTimeStamp_IT() or
+            HAL_RTCEx_SetTamper_IT() functions.
+
+       (++) To wake up from the STOP mode with an RTC WakeUp event, it is
+            necessary to configure the RTC to generate the RTC WakeUp event
+            using the HAL_RTCEx_SetWakeUpTimer_IT() function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the event mode and the voltage threshold detected by the
+  *         Programmable Voltage Detector(PVD).
+  * @param  sConfigPVD : Pointer to an PWR_PVDTypeDef structure that contains
+  *                      the configuration information for the PVD.
+  * @note   Refer to the electrical characteristics of your device datasheet for
+  *         more details about the voltage threshold corresponding to each
+  *         detection level.
+  * @note   For dual core devices, please ensure to configure the EXTI lines for
+  *         the different Cortex-Mx through PWR_Exported_Macro provided by this
+  *         driver. All combination are allowed: wake up only Cortex-M7, wake up
+  *         only Cortex-M4 or wake up Cortex-M7 and Cortex-M4.
+  * @retval None.
+  */
+void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD)
+{
+  /* Check the PVD configuration parameter */
+  if (sConfigPVD == NULL)
+  {
+    return;
+  }
+
+  /* Check the parameters */
+  assert_param (IS_PWR_PVD_LEVEL (sConfigPVD->PVDLevel));
+  assert_param (IS_PWR_PVD_MODE (sConfigPVD->Mode));
+
+  /* Set PLS[7:5] bits according to PVDLevel value */
+  MODIFY_REG (PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel);
+
+  /* Clear previous config */
+#if !defined (DUAL_CORE)
+  __HAL_PWR_PVD_EXTI_DISABLE_EVENT ();
+  __HAL_PWR_PVD_EXTI_DISABLE_IT ();
+#endif /* !defined (DUAL_CORE) */
+
+  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE ();
+  __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE ();
+
+#if !defined (DUAL_CORE)
+  /* Interrupt mode configuration */
+  if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
+  {
+    __HAL_PWR_PVD_EXTI_ENABLE_IT ();
+  }
+
+  /* Event mode configuration */
+  if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
+  {
+    __HAL_PWR_PVD_EXTI_ENABLE_EVENT ();
+  }
+#endif /* !defined (DUAL_CORE) */
+
+  /* Rising edge configuration */
+  if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
+  {
+    __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE ();
+  }
+
+  /* Falling edge configuration */
+  if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
+  {
+    __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE ();
+  }
+}
+
+/**
+  * @brief Enable the Programmable Voltage Detector (PVD).
+  * @retval None.
+  */
+void HAL_PWR_EnablePVD (void)
+{
+  /* Enable the power voltage detector */
+  SET_BIT (PWR->CR1, PWR_CR1_PVDEN);
+}
+
+/**
+  * @brief Disable the Programmable Voltage Detector (PVD).
+  * @retval None.
+  */
+void HAL_PWR_DisablePVD (void)
+{
+  /* Disable the power voltage detector */
+  CLEAR_BIT (PWR->CR1, PWR_CR1_PVDEN);
+}
+
+/**
+  * @brief  Enable the WakeUp PINx functionality.
+  * @param  WakeUpPinPolarity : Specifies which Wake-Up pin to enable.
+  *          This parameter can be one of the following legacy values, which
+  *          sets the default (rising edge):
+  *            @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3,
+  *                 PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6.
+  *          or one of the following values where the user can explicitly states
+  *          the enabled pin and the chosen polarity:
+  *            @arg PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW,
+  *                 PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW,
+  *                 PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW,
+  *                 PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW,
+  *                 PWR_WAKEUP_PIN5_HIGH, PWR_WAKEUP_PIN5_LOW,
+  *                 PWR_WAKEUP_PIN6_HIGH, PWR_WAKEUP_PIN6_LOW.
+  * @note   PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
+  * @retval None.
+  */
+void HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity)
+{
+  /* Check the parameters */
+  assert_param (IS_PWR_WAKEUP_PIN (WakeUpPinPolarity));
+
+  /*
+     Enable and Specify the Wake-Up pin polarity and the pull configuration
+     for the event detection (rising or falling edge).
+  */
+  MODIFY_REG (PWR->WKUPEPR, PWR_EWUP_MASK, WakeUpPinPolarity);
+}
+
+/**
+  * @brief  Disable the WakeUp PINx functionality.
+  * @param  WakeUpPinx : Specifies the Power Wake-Up pin to disable.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3,
+  *                 PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6,
+  *                 PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW,
+  *                 PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW,
+  *                 PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW,
+  *                 PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW,
+  *                 PWR_WAKEUP_PIN5_HIGH, PWR_WAKEUP_PIN5_LOW,
+  *                 PWR_WAKEUP_PIN6_HIGH, PWR_WAKEUP_PIN6_LOW.
+  * @retval None.
+  */
+void HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx)
+{
+  /* Check the parameters */
+  assert_param (IS_PWR_WAKEUP_PIN (WakeUpPinx));
+
+  /* Disable the wake up pin selected */
+  CLEAR_BIT (PWR->WKUPEPR, (PWR_WKUPEPR_WKUPEN & WakeUpPinx));
+}
+
+/**
+  * @brief  Enter the current core in SLEEP mode (CSLEEP).
+  * @param  Regulator : Specifies the regulator state in SLEEP mode.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_MAINREGULATOR_ON     : SLEEP mode with regulator ON.
+  *            @arg PWR_LOWPOWERREGULATOR_ON : SLEEP mode with low power
+  *                                           regulator ON.
+  * @note   This parameter is not used for the STM32H7 family and is kept as
+  *         parameter just to maintain compatibility with the lower power
+  *         families.
+  * @param  SLEEPEntry : Specifies if SLEEP mode is entered with WFI or WFE
+  *                      intrinsic instruction.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_SLEEPENTRY_WFI : enter SLEEP mode with WFI instruction.
+  *            @arg PWR_SLEEPENTRY_WFE : enter SLEEP mode with WFE instruction.
+  * @note   Ensure to clear pending events before calling this API through
+  *         HAL_PWREx_ClearPendingEvent() when the SLEEP entry is WFE.
+  * @retval None.
+  */
+void HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry)
+{
+  /* Check the parameters */
+  assert_param (IS_PWR_REGULATOR (Regulator));
+  assert_param (IS_PWR_SLEEP_ENTRY (SLEEPEntry));
+
+  /* Clear SLEEPDEEP bit of Cortex System Control Register */
+  CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+
+  /* Select SLEEP mode entry */
+  if (SLEEPEntry == PWR_SLEEPENTRY_WFI)
+  {
+    /* Request Wait For Interrupt */
+    __WFI ();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __WFE ();
+  }
+}
+
+/**
+  * @brief  Enter STOP mode.
+  * @note   For single core devices, this API will enter the system in STOP mode
+  *         with all domains in DSTOP, if RUN_D3/RUN_SRD bit in CPUCR regiter is
+  *         cleared.
+  *         For dual core devices, this API will enter the domain (containing
+  *         Cortex-Mx that executing this function) in DSTOP mode. If all
+  *         Cortex-Mx domains are in DSTOP and RUN_D3 bit in CPUCR register is
+  *         cleared, all the system will enter in STOP mode.
+  * @param  Regulator : Specifies the regulator state in STOP mode.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_MAINREGULATOR_ON     : STOP mode with regulator ON.
+  *            @arg PWR_LOWPOWERREGULATOR_ON : STOP mode with low power
+  *                                            regulator ON.
+  * @param  STOPEntry : Specifies if STOP mode in entered with WFI or WFE
+  *                     intrinsic instruction.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction.
+  *            @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction.
+  * @note   In System STOP mode, all I/O pins keep the same state as in Run mode.
+  * @note   When exiting System STOP mode by issuing an interrupt or a wakeup
+  *         event, the HSI RC oscillator is selected as default system wakeup
+  *         clock.
+  * @note   In System STOP mode, when the voltage regulator operates in low
+  *         power mode, an additional startup delay is incurred when the system
+  *         is waking up. By keeping the internal regulator ON during STOP mode,
+  *         the consumption is higher although the startup time is reduced.
+  * @retval None.
+  */
+void HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry)
+{
+  /* Check the parameters */
+  assert_param (IS_PWR_REGULATOR (Regulator));
+  assert_param (IS_PWR_STOP_ENTRY (STOPEntry));
+
+  /* Select the regulator state in STOP mode */
+  MODIFY_REG (PWR->CR1, PWR_CR1_LPDS, Regulator);
+
+  /* Configure the PWR mode for the different Domains */
+#if defined (DUAL_CORE)
+  /* Check CPU ID */
+  if (HAL_GetCurrentCPUID () == CM7_CPUID)
+  {
+    /* Keep DSTOP mode when Cortex-M7 enters DEEP-SLEEP */
+    CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
+  }
+  else
+  {
+    /* Keep DSTOP mode when Cortex-M4 enters DEEP-SLEEP */
+    CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D2 | PWR_CPUCR_PDDS_D3));
+  }
+#else /* Single core devices */
+  /* Keep DSTOP mode when Cortex-M7 enter in DEEP-SLEEP */
+  CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
+
+#if defined (PWR_CPUCR_PDDS_D2)
+  /* Keep DSTOP mode when Cortex-M7 enter in DEEP-SLEEP */
+  CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2);
+#endif /* PWR_CPUCR_PDDS_D2 */
+#endif /* defined (DUAL_CORE) */
+
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+
+  /* Ensure that all instructions are done before entering STOP mode */
+  __DSB ();
+  __ISB ();
+
+  /* Select STOP mode entry */
+  if (STOPEntry == PWR_STOPENTRY_WFI)
+  {
+    /* Request Wait For Interrupt */
+    __WFI ();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __WFE ();
+  }
+
+  /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */
+  CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+}
+
+/**
+  * @brief  Enter STANDBY mode.
+  * @note   For single core devices, this API will enter the system in STANDBY
+  *         mode with all domains in DSTANDBY, if RUN_D3/RUN_SRD bit in CPUCR
+  *         regiter is cleared.
+  *         For dual core devices, this API will enter the domain (containing
+  *         Cortex-Mx that executing this function) in DSTANDBY mode. If all
+  *         Cortex-Mx domains are in DSTANDBY and RUN_D3 bit in CPUCR register
+  *         is cleared, all the system will enter in STANDBY mode.
+  * @note   The system enters Standby mode only when all domains are in DSTANDBY.
+  * @note   When the System exit STANDBY mode by issuing an interrupt or a
+  *         wakeup event, the HSI RC oscillator is selected as system clock.
+  * @retval None.
+  */
+void HAL_PWR_EnterSTANDBYMode (void)
+{
+  /* Configure the PWR mode for the different Domains */
+#if defined (DUAL_CORE)
+  /* Check CPU ID */
+  if (HAL_GetCurrentCPUID () == CM7_CPUID)
+  {
+    /* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */
+    SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
+    SET_BIT (PWR->CPU2CR, (PWR_CPU2CR_PDDS_D1 | PWR_CPU2CR_PDDS_D3));
+  }
+  else
+  {
+    /* Enter DSTANDBY mode when Cortex-M4 enters DEEP-SLEEP */
+    SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D2 | PWR_CPUCR_PDDS_D3));
+    SET_BIT (PWR->CPU2CR, (PWR_CPU2CR_PDDS_D2 | PWR_CPU2CR_PDDS_D3));
+  }
+#else /* Single core devices */
+  /* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */
+  SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
+
+#if defined (PWR_CPUCR_PDDS_D2)
+  /* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */
+  SET_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2);
+#endif /* PWR_CPUCR_PDDS_D2 */
+#endif /* defined (DUAL_CORE) */
+
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+
+  /* Ensure that all instructions are done before entering STOP mode */
+  __DSB ();
+  __ISB ();
+
+  /* This option is used to ensure that store operations are completed */
+#if defined (__CC_ARM)
+  __force_stores();
+#endif /* defined (__CC_ARM) */
+
+  /* Request Wait For Interrupt */
+  __WFI ();
+}
+
+/**
+  * @brief  Indicate Sleep-On-Exit feature when returning from Handler mode to
+  *         Thread mode.
+  * @note   Set SLEEPONEXIT bit of SCR register. When this bit is set, the
+  *         processor re-enters SLEEP mode when an interruption handling is over.
+  *         Setting this bit is useful when the processor is expected to run
+  *         only on interruptions handling.
+  * @retval None.
+  */
+void HAL_PWR_EnableSleepOnExit (void)
+{
+  /* Set SLEEPONEXIT bit of Cortex-Mx System Control Register */
+  SET_BIT (SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
+}
+
+/**
+  * @brief  Disable Sleep-On-Exit feature when returning from Handler mode to
+  *         Thread mode.
+  * @note   Clears SLEEPONEXIT bit of SCR register. When this bit is set, the
+  *         processor re-enters SLEEP mode when an interruption handling is over.
+  * @retval None
+  */
+void HAL_PWR_DisableSleepOnExit (void)
+{
+  /* Clear SLEEPONEXIT bit of Cortex-Mx System Control Register */
+  CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
+}
+
+/**
+  * @brief  Enable CORTEX SEVONPEND feature.
+  * @note   Sets SEVONPEND bit of SCR register. When this bit is set, any
+  *         pending event / interrupt even if it's disabled or has insufficient
+  *         priority to cause exception entry wakes up the Cortex-Mx.
+  * @retval None.
+  */
+void HAL_PWR_EnableSEVOnPend (void)
+{
+  /* Set SEVONPEND bit of Cortex-Mx System Control Register */
+  SET_BIT (SCB->SCR, SCB_SCR_SEVONPEND_Msk);
+}
+
+/**
+  * @brief  Disable CORTEX SEVONPEND feature.
+  * @note   Resets SEVONPEND bit of SCR register. When this bit is reset, only
+  *         enabled pending causes exception entry wakes up the Cortex-Mx.
+  * @retval None.
+  */
+void HAL_PWR_DisableSEVOnPend (void)
+{
+  /* Clear SEVONPEND bit of Cortex System Control Register */
+  CLEAR_BIT (SCB->SCR, SCB_SCR_SEVONPEND_Msk);
+}
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Exported_Functions_Group3 Interrupt Handling Functions
+  *  @brief   Interrupt Handling functions
+  *
+@verbatim
+ ===============================================================================
+                    ##### Interrupt Handling Functions #####
+ ===============================================================================
+    [..]
+    This section provides functions allowing to handle the PVD pending
+    interrupts.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function handles the PWR PVD interrupt request.
+  * @note   This API should be called under the PVD_AVD_IRQHandler().
+  * @retval None.
+  */
+void HAL_PWR_PVD_IRQHandler (void)
+{
+#if defined (DUAL_CORE)
+  /* Check Cortex-Mx ID */
+  if (HAL_GetCurrentCPUID () == CM7_CPUID)
+  {
+    /* Check PWR EXTI D1 flag */
+    if(__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U)
+    {
+      /* Clear PWR EXTI D1 pending bit */
+      __HAL_PWR_PVD_EXTI_CLEAR_FLAG ();
+
+      /* PWR PVD interrupt user callback */
+      HAL_PWR_PVDCallback ();
+    }
+  }
+  else
+  {
+    /* Check PWR EXTI D2 flag */
+    if (__HAL_PWR_PVD_EXTID2_GET_FLAG () != 0U)
+    {
+      /* Clear PWR EXTI D2 pending bit */
+      __HAL_PWR_PVD_EXTID2_CLEAR_FLAG ();
+
+      /* PWR PVD interrupt user callback */
+      HAL_PWR_PVDCallback ();
+    }
+  }
+#else /* Single core devices */
+  /* PVD EXTI line interrupt detected */
+  if (__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U)
+  {
+    /* Clear PWR EXTI pending bit */
+    __HAL_PWR_PVD_EXTI_CLEAR_FLAG ();
+
+    /* PWR PVD interrupt user callback */
+    HAL_PWR_PVDCallback ();
+  }
+#endif /* defined (DUAL_CORE) */
+}
+
+/**
+  * @brief  PWR PVD interrupt callback.
+  * @retval None.
+  */
+__weak void HAL_PWR_PVDCallback (void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PWR_PVDCallback can be implemented in the user file
+  */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_PWR_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c
new file mode 100644
index 00000000..82288f9e
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c
@@ -0,0 +1,2100 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_pwr_ex.c
+  * @author  MCD Application Team
+  * @brief   Extended PWR HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of PWR extension peripheral:
+  *           + Peripheral Extended features functions
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+   (#) Call HAL_PWREx_ConfigSupply() function to configure the regulator supply
+       with the following different setups according to hardware (support SMPS):
+       (+) PWR_DIRECT_SMPS_SUPPLY
+       (+) PWR_SMPS_1V8_SUPPLIES_LDO
+       (+) PWR_SMPS_2V5_SUPPLIES_LDO
+       (+) PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO
+       (+) PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO
+       (+) PWR_SMPS_1V8_SUPPLIES_EXT
+       (+) PWR_SMPS_2V5_SUPPLIES_EXT
+       (+) PWR_LDO_SUPPLY
+       (+) PWR_EXTERNAL_SOURCE_SUPPLY
+
+   (#) Call HAL_PWREx_GetSupplyConfig() function to get the current supply setup.
+
+   (#) Call HAL_PWREx_ControlVoltageScaling() function to configure the main
+       internal regulator output voltage. The voltage scaling could be one of
+       the following scales :
+       (+) PWR_REGULATOR_VOLTAGE_SCALE0
+       (+) PWR_REGULATOR_VOLTAGE_SCALE1
+       (+) PWR_REGULATOR_VOLTAGE_SCALE2
+       (+) PWR_REGULATOR_VOLTAGE_SCALE3
+
+   (#) Call HAL_PWREx_GetVoltageRange() function to get the current output
+       voltage applied to the main regulator.
+
+   (#) Call HAL_PWREx_ControlStopModeVoltageScaling() function to configure the
+       main internal regulator output voltage in STOP mode. The voltage scaling
+       in STOP mode could be one of the following scales :
+       (+) PWR_REGULATOR_SVOS_SCALE3
+       (+) PWR_REGULATOR_SVOS_SCALE4
+       (+) PWR_REGULATOR_SVOS_SCALE5
+
+   (#) Call HAL_PWREx_GetStopModeVoltageRange() function to get the current
+       output voltage applied to the main regulator in STOP mode.
+
+   (#) Call HAL_PWREx_EnterSTOP2Mode() function to enter the system in STOP mode
+       with core domain in D2STOP mode. This API is used only for STM32H7Axxx
+       and STM32H7Bxxx devices.
+       Please ensure to clear all CPU pending events by calling
+       HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx
+       in DEEP-SLEEP mode with __WFE() entry.
+
+   (#) Call HAL_PWREx_EnterSTOPMode() function to enter the selected domain in
+       DSTOP mode. Call this API with all available power domains to enter the
+       system in STOP mode.
+       Please ensure to clear all CPU pending events by calling
+       HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx
+       in DEEP-SLEEP mode with __WFE() entry.
+
+   (#) Call HAL_PWREx_ClearPendingEvent() function always before entring the
+       Cortex-Mx in any low power mode (SLEEP/DEEP-SLEEP) using WFE entry.
+
+   (#) Call HAL_PWREx_EnterSTANDBYMode() function to enter the selected domain
+       in DSTANDBY mode. Call this API with all available power domains to enter
+       the system in STANDBY mode.
+
+   (#) Call HAL_PWREx_ConfigD3Domain() function to setup the D3/SRD domain state
+       (RUN/STOP) when the system enter to low power mode.
+
+   (#) Call HAL_PWREx_ClearDomainFlags() function to clear the CPU flags for the
+       selected power domain. This API is used only for dual core devices.
+
+   (#) Call HAL_PWREx_HoldCore() and HAL_PWREx_ReleaseCore() functions to hold
+       and release the selected CPU and and their domain peripherals when
+       exiting STOP mode. These APIs are used only for dual core devices.
+
+   (#) Call HAL_PWREx_EnableFlashPowerDown() and
+       HAL_PWREx_DisableFlashPowerDown() functions to enable and disable the
+       Flash Power Down in STOP mode.
+
+   (#) Call HAL_PWREx_EnableMemoryShutOff() and
+       HAL_PWREx_DisableMemoryShutOff() functions to enable and disable the
+       memory block shut-off in DStop or DStop2. These APIs are used only for
+       STM32H7Axxx and STM32H7Bxxx lines.
+
+   (#) Call HAL_PWREx_EnableWakeUpPin() and HAL_PWREx_DisableWakeUpPin()
+       functions to enable and disable the Wake-up pin functionality for
+       the selected pin.
+
+   (#) Call HAL_PWREx_GetWakeupFlag() and HAL_PWREx_ClearWakeupFlag()
+       functions to manage wake-up flag for the selected pin.
+
+   (#) Call HAL_PWREx_WAKEUP_PIN_IRQHandler() function to handle all wake-up
+       pins interrupts.
+
+   (#) Call HAL_PWREx_EnableBkUpReg() and HAL_PWREx_DisableBkUpReg() functions
+       to enable and disable the backup domain regulator.
+
+   (#) Call HAL_PWREx_EnableUSBReg(), HAL_PWREx_DisableUSBReg(),
+       HAL_PWREx_EnableUSBVoltageDetector() and
+       HAL_PWREx_DisableUSBVoltageDetector() functions to manage USB power
+       regulation functionnalities.
+
+   (#) Call HAL_PWREx_EnableBatteryCharging() and
+       HAL_PWREx_DisableBatteryCharging() functions to enable and disable the
+       battery charging feature with the selected resistor.
+
+   (#) Call HAL_PWREx_EnableAnalogBooster() and
+       HAL_PWREx_DisableAnalogBooster() functions to enable and disable the
+       AVD boost feature when the VDD supply voltage is below 2V7.
+
+   (#) Call HAL_PWREx_EnableMonitoring() and HAL_PWREx_DisableMonitoring()
+       functions to enable and disable the VBAT and Temperature monitoring.
+       When VBAT and Temperature monitoring feature is enables, use
+       HAL_PWREx_GetTemperatureLevel() and HAL_PWREx_GetVBATLevel() to get
+       respectively the Temperature level and VBAT level.
+
+   (#) Call HAL_PWREx_GetMMCVoltage() and HAL_PWREx_DisableMonitoring()
+       function to get VDDMMC voltage level. This API is used only for
+       STM32H7AxxQ, STM32H7BxxQ, STM32H7Axxx and STM32H7Bxxx lines
+
+   (#) Call HAL_PWREx_ConfigAVD() after setting parameter to be configured
+       (event mode and voltage threshold) in order to set up the Analog Voltage
+       Detector then use HAL_PWREx_EnableAVD() and  HAL_PWREx_DisableAVD()
+       functions to start and stop the AVD detection.
+       (+) AVD level could be one of the following values :
+             (++) 1V7
+             (++) 2V1
+             (++) 2V5
+             (++) 2V8
+
+   (#) Call HAL_PWREx_PVD_AVD_IRQHandler() function to handle the PWR PVD and
+       AVD interrupt request.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup PWREx PWREx
+  * @brief PWR Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @addtogroup PWREx_Private_Constants
+  * @{
+  */
+
+/** @defgroup PWREx_AVD_Mode_Mask PWR Extended AVD Mode Mask
+  * @{
+  */
+#define AVD_MODE_IT              (0x00010000U)
+#define AVD_MODE_EVT             (0x00020000U)
+#define AVD_RISING_EDGE          (0x00000001U)
+#define AVD_FALLING_EDGE         (0x00000002U)
+#define AVD_RISING_FALLING_EDGE  (0x00000003U)
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_REG_SET_TIMEOUT PWR Extended Flag Setting Time Out Value
+  * @{
+  */
+#define PWR_FLAG_SETTING_DELAY   (1000U)
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_WakeUp_Pins_Offsets PWREx Wake-Up Pins masks and offsets
+  * @{
+  */
+/* Wake-Up Pins EXTI register mask */
+#define PWR_EXTI_WAKEUP_PINS_MASK  (EXTI_IMR2_IM55 | EXTI_IMR2_IM56 |\
+                                    EXTI_IMR2_IM57 | EXTI_IMR2_IM58 |\
+                                    EXTI_IMR2_IM59 | EXTI_IMR2_IM60)
+
+/* Wake-Up Pins PWR Pin Pull shift offsets */
+#define PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET (2U)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup PWREx_Exported_Functions PWREx Exported Functions
+  * @{
+  */
+
+/** @defgroup PWREx_Exported_Functions_Group1 Power Supply Control Functions
+  * @brief    Power supply control functions
+  *
+@verbatim
+ ===============================================================================
+                  ##### Power supply control functions #####
+ ===============================================================================
+    [..]
+   (#) When the system is powered on, the POR monitors VDD supply. Once VDD is
+       above the POR threshold level, the voltage regulator is enabled in the
+       default supply configuration:
+      (+) The Voltage converter output level is set at 1V0 in accordance with
+          the VOS3 level configured in PWR (D3/SRD) domain control register
+          (PWR_D3CR/PWR_SRDCR).
+      (+) The system is kept in reset mode as long as VCORE is not ok.
+      (+) Once VCORE is ok, the system is taken out of reset and the HSI
+          oscillator is enabled.
+      (+) Once the oscillator is stable, the system is initialized: Flash memory
+          and option bytes are loaded and the CPU starts in Run* mode.
+      (+) The software shall then initialize the system including supply
+          configuration programming using the HAL_PWREx_ConfigSupply().
+      (+) Once the supply configuration has been configured, the
+          HAL_PWREx_ConfigSupply() function checks the ACTVOSRDY bit in PWR
+          control status register 1 (PWR_CSR1) to guarantee a valid voltage
+          levels:
+       (++) As long as ACTVOSRDY indicates that voltage levels are invalid, the
+            system is in limited Run* mode, write accesses to the RAMs are not
+            permitted and VOS shall not be changed.
+       (++) Once ACTVOSRDY indicates that voltage levels are valid, the system
+            is in normal Run mode, write accesses to RAMs are allowed and VOS
+            can be changed.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Configure the system Power Supply.
+  * @param  SupplySource : Specifies the Power Supply source to set after a
+  *                        system startup.
+  *         This parameter can be one of the following values :
+  *            @arg PWR_DIRECT_SMPS_SUPPLY : The SMPS supplies the Vcore Power
+  *                                          Domains. The LDO is Bypassed.
+  *            @arg PWR_SMPS_1V8_SUPPLIES_LDO : The SMPS 1.8V output supplies
+  *                                             the LDO. The Vcore Power Domains
+  *                                             are supplied from the LDO.
+  *            @arg PWR_SMPS_2V5_SUPPLIES_LDO : The SMPS 2.5V output supplies
+  *                                             the LDO. The Vcore Power Domains
+  *                                             are supplied from the LDO.
+  *            @arg PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO : The SMPS 1.8V output
+  *                                                     supplies external
+  *                                                     circuits and the LDO.
+  *                                                     The Vcore Power Domains
+  *                                                     are supplied from the
+  *                                                     LDO.
+  *            @arg PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO : The SMPS 2.5V output
+  *                                                     supplies external
+  *                                                     circuits and the LDO.
+  *                                                     The Vcore Power Domains
+  *                                                     are supplied from the
+  *                                                     LDO.
+  *            @arg PWR_SMPS_1V8_SUPPLIES_EXT : The SMPS 1.8V output supplies
+  *                                             external circuits. The LDO is
+  *                                             Bypassed. The Vcore Power
+  *                                             Domains are supplied from
+  *                                             external source.
+  *            @arg PWR_SMPS_2V5_SUPPLIES_EXT : The SMPS 2.5V output supplies
+  *                                             external circuits. The LDO is
+  *                                             Bypassed. The Vcore Power
+  *                                             Domains are supplied from
+  *                                             external source.
+  *            @arg PWR_LDO_SUPPLY : The LDO regulator supplies the Vcore Power
+  *                                  Domains. The SMPS regulator is Bypassed.
+  *            @arg PWR_EXTERNAL_SOURCE_SUPPLY : The SMPS and the LDO are
+  *                                              Bypassed. The Vcore Power
+  *                                              Domains are supplied from
+  *                                              external source.
+  * @note   The PWR_LDO_SUPPLY and PWR_EXTERNAL_SOURCE_SUPPLY are used by all
+  *         H7 lines.
+  *         The PWR_DIRECT_SMPS_SUPPLY, PWR_SMPS_1V8_SUPPLIES_LDO,
+  *         PWR_SMPS_2V5_SUPPLIES_LDO, PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO,
+  *         PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO, PWR_SMPS_1V8_SUPPLIES_EXT and
+  *         PWR_SMPS_2V5_SUPPLIES_EXT are used only for lines that supports SMPS
+  *         regulator.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource)
+{
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param (IS_PWR_SUPPLY (SupplySource));
+
+  /* Check if supply source was configured */
+#if defined (PWR_FLAG_SCUEN)
+  if (__HAL_PWR_GET_FLAG (PWR_FLAG_SCUEN) == 0U)
+#else
+  if ((PWR->CR3 & (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)) != (PWR_CR3_SMPSEN | PWR_CR3_LDOEN))
+#endif /* defined (PWR_FLAG_SCUEN) */
+  {
+    /* Check supply configuration */
+    if ((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource)
+    {
+      /* Supply configuration update locked, can't apply a new supply config */
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Supply configuration update locked, but new supply configuration
+         matches with old supply configuration : nothing to do
+      */
+      return HAL_OK;
+    }
+  }
+
+  /* Set the power supply configuration */
+  MODIFY_REG (PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource);
+
+  /* Get tick */
+  tickstart = HAL_GetTick ();
+
+  /* Wait till voltage level flag is set */
+  while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
+  {
+    if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+#if defined (SMPS)
+  /* When the SMPS supplies external circuits verify that SDEXTRDY flag is set */
+  if ((SupplySource == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) ||
+      (SupplySource == PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) ||
+      (SupplySource == PWR_SMPS_1V8_SUPPLIES_EXT)         ||
+      (SupplySource == PWR_SMPS_2V5_SUPPLIES_EXT))
+  {
+    /* Get the current tick number */
+    tickstart = HAL_GetTick ();
+
+    /* Wait till SMPS external supply ready flag is set */
+    while (__HAL_PWR_GET_FLAG (PWR_FLAG_SMPSEXTRDY) == 0U)
+    {
+      if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY)
+      {
+        return HAL_ERROR;
+      }
+    }
+  }
+#endif /* defined (SMPS) */
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Get the power supply configuration.
+  * @retval The supply configuration.
+  */
+uint32_t HAL_PWREx_GetSupplyConfig (void)
+{
+  return (PWR->CR3 & PWR_SUPPLY_CONFIG_MASK);
+}
+
+/**
+  * @brief Configure the main internal regulator output voltage.
+  * @note   For STM32H7x3, STM32H7x5, STM32H7x7, STM32H742 and STM32H750 lines,
+  *         configuring Voltage Scale 0 is only possible when Vcore is supplied
+  *         from LDO (Low DropOut). The SYSCFG Clock must be enabled through
+  *         __HAL_RCC_SYSCFG_CLK_ENABLE() macro before configuring Voltage
+  *         Scale 0.
+  * @param  VoltageScaling : Specifies the regulator output voltage to achieve
+  *                          a tradeoff between performance and power
+  *                          consumption.
+  *          This parameter can be one of the following values :
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE0 : Regulator voltage output
+  *                                                Scale 0 mode.
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output
+  *                                                range 1 mode.
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output
+  *                                                range 2 mode.
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output
+  *                                                range 3 mode.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling)
+{
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param (IS_PWR_REGULATOR_VOLTAGE (VoltageScaling));
+
+  /* Get the voltage scaling  */
+  if ((PWR->CSR1 & PWR_CSR1_ACTVOS) == VoltageScaling)
+  {
+    /* Old and new voltage scaling configuration match : nothing to do */
+    return HAL_OK;
+  }
+
+#if defined (PWR_SRDCR_VOS)
+  /* Set the voltage range */
+  MODIFY_REG (PWR->SRDCR, PWR_SRDCR_VOS, VoltageScaling);
+#else
+  if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE0)
+  {
+    if ((PWR->CR3 & PWR_CR3_LDOEN) == PWR_CR3_LDOEN)
+    {
+      /* Set the voltage range */
+      MODIFY_REG (PWR->D3CR, PWR_D3CR_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
+
+      /* Get tick */
+      tickstart = HAL_GetTick ();
+
+      /* Wait till voltage level flag is set */
+      while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
+      {
+        if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY)
+        {
+          return HAL_ERROR;
+        }
+      }
+
+      /* Enable the PWR overdrive */
+      SET_BIT (SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);
+    }
+    else
+    {
+      /* The voltage scale 0 is only possible when LDO regulator is enabled */
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    if ((PWR->CSR1 & PWR_CSR1_ACTVOS) == PWR_REGULATOR_VOLTAGE_SCALE1)
+    {
+      if ((SYSCFG->PWRCR & SYSCFG_PWRCR_ODEN) != 0U)
+      {
+        /* Disable the PWR overdrive */
+        CLEAR_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);
+
+        /* Get tick */
+        tickstart = HAL_GetTick ();
+
+        /* Wait till voltage level flag is set */
+        while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
+        {
+          if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY)
+          {
+            return HAL_ERROR;
+          }
+        }
+      }
+    }
+
+    /* Set the voltage range */
+    MODIFY_REG (PWR->D3CR, PWR_D3CR_VOS, VoltageScaling);
+  }
+#endif /* defined (PWR_SRDCR_VOS) */
+
+  /* Get tick */
+  tickstart = HAL_GetTick ();
+
+  /* Wait till voltage level flag is set */
+  while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > PWR_FLAG_SETTING_DELAY)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Get the main internal regulator output voltage. Reflecting the last
+  *        VOS value applied to the PMU.
+  * @retval The current applied VOS selection.
+  */
+uint32_t HAL_PWREx_GetVoltageRange (void)
+{
+  /* Get the active voltage scaling */
+  return (PWR->CSR1 & PWR_CSR1_ACTVOS);
+}
+
+/**
+  * @brief Configure the main internal regulator output voltage in STOP mode.
+  * @param  VoltageScaling : Specifies the regulator output voltage when the
+  *         system enters Stop mode to achieve a tradeoff between performance
+  *         and power consumption.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_REGULATOR_SVOS_SCALE3 : Regulator voltage output range
+  *                                             3 mode.
+  *            @arg PWR_REGULATOR_SVOS_SCALE4 : Regulator voltage output range
+  *                                             4 mode.
+  *            @arg PWR_REGULATOR_SVOS_SCALE5 : Regulator voltage output range
+  *                                             5 mode.
+  * @note   The Stop mode voltage scaling for SVOS4 and SVOS5 sets the voltage
+  *         regulator in Low-power (LP) mode to further reduce power consumption.
+  *         When preselecting SVOS3, the use of the voltage regulator low-power
+  *         mode (LP) can be selected by LPDS register bit.
+  * @note   The selected SVOS4 and SVOS5 levels add an additional startup delay
+  *         when exiting from system Stop mode.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling (uint32_t VoltageScaling)
+{
+  /* Check the parameters */
+  assert_param (IS_PWR_STOP_MODE_REGULATOR_VOLTAGE (VoltageScaling));
+
+  /* Return the stop mode voltage range */
+  MODIFY_REG (PWR->CR1, PWR_CR1_SVOS, VoltageScaling);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Get the main internal regulator output voltage in STOP mode.
+  * @retval The actual applied VOS selection.
+  */
+uint32_t HAL_PWREx_GetStopModeVoltageRange (void)
+{
+  /* Return the stop voltage scaling */
+  return (PWR->CR1 & PWR_CR1_SVOS);
+}
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_Exported_Functions_Group2 Low Power Control Functions
+  * @brief    Low power control functions
+  *
+@verbatim
+ ===============================================================================
+                     ##### Low power control functions #####
+ ===============================================================================
+
+    *** Domains Low Power modes configuration ***
+    =============================================
+    [..]
+      This section provides the extended low power mode control APIs.
+      The system presents 3 principles domains (D1, D2 and D3) that can be
+      operated in low-power modes (DSTOP or DSTANDBY mode):
+
+      (+) DSTOP mode to enters a domain to STOP mode:
+       (++) D1 domain and/or D2 domain enters DSTOP mode only when the CPU
+            subsystem is in CSTOP mode and has allocated peripheral in the
+            domain.
+            In DSTOP mode the domain bus matrix clock is stopped.
+       (++) The system enters STOP mode using one of the following scenarios:
+        (+++) D1 domain enters DSTANDBY mode (powered off) and D2, D3 domains
+              enter DSTOP mode.
+        (+++) D2 domain enters DSTANDBY mode (powered off) and D1, D3 domains
+              enter DSTOP mode.
+        (+++) D3 domain enters DSTANDBY mode (powered off) and D1, D2 domains
+              enter DSTOP mode.
+        (+++) D1 and D2 domains enter DSTANDBY mode (powered off) and D3 domain
+              enters DSTOP mode.
+        (+++) D1 and D3 domains enter DSTANDBY mode (powered off) and D2 domain
+              enters DSTOP mode.
+        (+++) D2 and D3 domains enter DSTANDBY mode (powered off) and D1 domain
+              enters DSTOP mode.
+        (+++) D1, D2 and D3 domains enter DSTOP mode.
+       (++) When the system enters STOP mode, the clocks are stopped and the
+            regulator is running in main or low power mode.
+       (++) D3 domain can be kept in Run mode regardless of the CPU status when
+            enter STOP mode by using HAL_PWREx_ConfigD3Domain(D3State) function.
+
+      (+) DSTANDBY mode to enters a domain to STANDBY mode:
+       (++) The DSTANDBY mode is entered when the PDDS_Dn bit in PWR CPU control
+            register (PWR_CPUCR) for the Dn domain selects Standby mode.
+       (++) The system enters STANDBY mode only when D1, D2 and D3 domains enter
+            DSTANDBY mode. Consequently the VCORE supply regulator is powered
+            off.
+
+   *** DSTOP mode ***
+   ==================
+    [..]
+      In DStop mode the domain bus matrix clock is stopped.
+      The Flash memory can enter low-power Stop mode when it is enabled through
+      FLPS in PWR_CR1 register. This allows a trade-off between domain DStop
+      restart time and low power consumption.
+    [..]
+      In DStop mode domain peripherals using the LSI or LSE clock and
+      peripherals having a kernel clock request are still able to operate.
+    [..]
+      Before entering DSTOP mode it is recommended to call SCB_CleanDCache
+      function in order to clean the D-Cache and guarantee the data integrity
+      for the SRAM memories.
+
+      (+) Entry:
+         The DSTOP mode is entered using the HAL_PWREx_EnterSTOPMode(Regulator,
+         STOPEntry, Domain) function with:
+         (++) Regulator:
+          (+++) PWR_MAINREGULATOR_ON     : Main regulator ON.
+          (+++) PWR_LOWPOWERREGULATOR_ON : Low Power regulator ON.
+         (++) STOPEntry:
+          (+++) PWR_STOPENTRY_WFI : enter STOP mode with WFI instruction
+          (+++) PWR_STOPENTRY_WFE : enter STOP mode with WFE instruction
+         (++) Domain:
+          (+++) PWR_D1_DOMAIN : Enters D1 domain to DSTOP mode.
+          (+++) PWR_D2_DOMAIN : Enters D2 domain to DSTOP mode.
+          (+++) PWR_D3_DOMAIN : Enters D3 domain to DSTOP mode.
+
+      (+) Exit:
+        Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
+
+   *** DSTANDBY mode ***
+   =====================
+    [..]
+      In DStandby mode:
+        (+) The domain bus matrix clock is stopped.
+        (+) The domain is powered down and the domain RAM and register contents
+            are lost.
+    [..]
+      Before entering DSTANDBY mode it is recommended to call SCB_CleanDCache
+      function in order to clean the D-Cache and guarantee the data integrity
+      for the SRAM memories.
+
+      (+) Entry:
+         The DSTANDBY mode is entered using the HAL_PWREx_EnterSTANDBYMode
+         (Domain) function with:
+       (++) Domain:
+        (+++) PWR_D1_DOMAIN : Enters D1 domain to DSTANDBY mode.
+        (+++) PWR_D2_DOMAIN : Enters D2 domain to DSTANDBY mode.
+        (+++) PWR_D3_DOMAIN : Enters D3 domain to DSTANDBY mode.
+
+      (+) Exit:
+        WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC
+        wakeup, tamper event, time stamp event, external reset in NRST pin,
+        IWDG reset.
+
+   *** Keep D3/SRD in RUN mode ***
+   ===============================
+    [..]
+      D3/SRD domain can be kept in Run mode regardless of the CPU status when
+      entering STOP mode by using HAL_PWREx_ConfigD3Domain(D3State) function
+      with :
+       (+) D3State:
+        (++) PWR_D3_DOMAIN_STOP : D3/SDR domain follows the CPU sub-system
+                                  mode.
+        (++) PWR_D3_DOMAIN_RUN : D3/SRD domain remains in Run mode regardless
+                                 of CPU subsystem mode.
+
+    *** FLASH Power Down configuration ****
+    =======================================
+    [..]
+      By setting the FLPS bit in the PWR_CR1 register using the
+      HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters
+      power down mode when the device enters STOP mode. When the Flash memory is
+      in power down mode, an additional startup delay is incurred when waking up
+      from STOP mode.
+
+    *** Wakeup Pins configuration ****
+    ===================================
+    [..]
+      Wakeup pins allow the system to exit from Standby mode. The configuration
+      of wakeup pins is done with the HAL_PWREx_EnableWakeUpPin(sPinParams)
+      function with:
+       (+) sPinParams: structure to enable and configure a wakeup pin:
+        (++) WakeUpPin: Wakeup pin to be enabled.
+        (++) PinPolarity: Wakeup pin polarity (rising or falling edge).
+        (++) PinPull: Wakeup pin pull (no pull, pull-up or pull-down).
+    [..]
+      The wakeup pins are internally connected to the EXTI lines [55-60] to
+      generate an interrupt if enabled. The EXTI lines configuration is done by
+      the HAL_EXTI_Dx_EventInputConfig() functions defined in the stm32h7xxhal.c
+      file.
+    [..]
+      When a wakeup pin event is received the HAL_PWREx_WAKEUP_PIN_IRQHandler is
+      called and the appropriate flag is set in the PWR_WKUPFR register. Then in
+      the HAL_PWREx_WAKEUP_PIN_IRQHandler function the wakeup pin flag will be
+      cleared and the appropriate user callback will be called. The user can add
+      his own code by customization of function pointer HAL_PWREx_WKUPx_Callback.
+
+@endverbatim
+  * @{
+  */
+
+#if defined (PWR_CPUCR_RETDS_CD)
+/**
+  * @brief Enter the system to STOP mode with main domain in DSTOP2.
+  * @note   In STOP mode, the domain bus matrix clock is stalled.
+  * @note   In STOP mode, memories and registers are maintained and peripherals
+  *         in CPU domain are no longer operational.
+  * @note   All clocks in the VCORE domain are stopped, the PLL, the HSI and the
+  *         HSE oscillators are disabled. Only Peripherals that have wakeup
+  *         capability can switch on the HSI to receive a frame, and switch off
+  *         the HSI after receiving the frame if it is not a wakeup frame. In
+  *         this case the HSI clock is propagated only to the peripheral
+  *         requesting it.
+  * @note   When exiting STOP mode by issuing an interrupt or a wakeup event,
+  *         the HSI RC oscillator is selected as system clock if STOPWUCK bit in
+  *         RCC_CFGR register is set.
+  * @param  Regulator : Specifies the regulator state in STOP mode.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_MAINREGULATOR_ON     : STOP mode with regulator ON.
+  *            @arg PWR_LOWPOWERREGULATOR_ON : STOP mode with low power
+  *                                            regulator ON.
+  * @param  STOPEntry : Specifies if STOP mode in entered with WFI or WFE
+  *                     intrinsic instruction.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction.
+  *            @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction.
+  * @retval None.
+  */
+void HAL_PWREx_EnterSTOP2Mode (uint32_t Regulator, uint8_t STOPEntry)
+{
+  /* Check the parameters */
+  assert_param (IS_PWR_REGULATOR (Regulator));
+  assert_param (IS_PWR_STOP_ENTRY (STOPEntry));
+
+  /* Select the regulator state in Stop mode */
+  MODIFY_REG (PWR->CR1, PWR_CR1_LPDS, Regulator);
+
+  /* Go to DStop2 mode (deep retention) when CPU domain enters Deepsleep */
+  SET_BIT (PWR->CPUCR, PWR_CPUCR_RETDS_CD);
+
+  /* Keep DSTOP mode when SmartRun domain enters Deepsleep */
+  CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_SRD);
+
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+
+  /* Ensure that all instructions are done before entering STOP mode */
+  __ISB ();
+  __DSB ();
+
+  /* Select Stop mode entry */
+  if (STOPEntry == PWR_STOPENTRY_WFI)
+  {
+    /* Request Wait For Interrupt */
+    __WFI ();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __WFE ();
+  }
+
+  /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */
+  CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+}
+#endif /* defined (PWR_CPUCR_RETDS_CD) */
+
+/**
+  * @brief Enter a Domain to DSTOP mode.
+  * @note   This API gives flexibility to manage independently each domain STOP
+  *         mode. For dual core lines, this API should be executed with the
+  *         corresponding Cortex-Mx to enter domain to DSTOP mode. When it is
+  *         executed by all available Cortex-Mx, the system enter to STOP mode.
+  *         For single core lines, calling this API with domain parameter set to
+  *         PWR_D1_DOMAIN (D1/CD), the whole system will enter in STOP mode
+  *         independently of PWR_CPUCR_PDDS_Dx bits values if RUN_D3 bit in the
+  *         CPUCR_RUN_D3 is cleared.
+  * @note   In DStop mode the domain bus matrix clock is stopped.
+  * @note   The system D3/SRD domain enter Stop mode only when the CPU subsystem
+  *         is in CStop mode, the EXTI wakeup sources are inactive and at least
+  *         one PDDS_Dn bit in PWR CPU control register (PWR_CPUCR) for
+  *         any domain request Stop.
+  * @note   Before entering DSTOP mode it is recommended to call SCB_CleanDCache
+  *         function in order to clean the D-Cache and guarantee the data
+  *         integrity for the SRAM memories.
+  * @note   In System Stop mode, the domain peripherals that use the LSI or LSE
+  *         clock, and the peripherals that have a kernel clock request to
+  *         select HSI or CSI as source, are still able to operate.
+  * @param  Regulator : Specifies the regulator state in STOP mode.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_MAINREGULATOR_ON     : STOP mode with regulator ON.
+  *            @arg PWR_LOWPOWERREGULATOR_ON : STOP mode with low power
+  *                                            regulator ON.
+  * @param  STOPEntry : Specifies if STOP mode in entered with WFI or WFE
+  *                     intrinsic instruction.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction.
+  *            @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction.
+  * @param  Domain : Specifies the Domain to enter in DSTOP mode.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_D1_DOMAIN : Enter D1/CD Domain to DSTOP mode.
+  *            @arg PWR_D2_DOMAIN : Enter D2 Domain to DSTOP mode.
+  *            @arg PWR_D3_DOMAIN : Enter D3/SRD Domain to DSTOP mode.
+  * @retval None.
+  */
+void HAL_PWREx_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain)
+{
+  /* Check the parameters */
+  assert_param (IS_PWR_REGULATOR (Regulator));
+  assert_param (IS_PWR_STOP_ENTRY (STOPEntry));
+  assert_param (IS_PWR_DOMAIN (Domain));
+
+  /* Select the regulator state in Stop mode */
+  MODIFY_REG (PWR->CR1, PWR_CR1_LPDS, Regulator);
+
+  /* Select the domain Power Down DeepSleep */
+  if (Domain == PWR_D1_DOMAIN)
+  {
+#if defined (DUAL_CORE)
+    /* Check current core */
+    if (HAL_GetCurrentCPUID () != CM7_CPUID)
+    {
+      /*
+         When the domain selected and the cortex-mx don't match, entering stop
+         mode will not be performed
+      */
+      return;
+    }
+#endif /* defined (DUAL_CORE) */
+
+    /* Keep DSTOP mode when D1/CD domain enters Deepsleep */
+    CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D1);
+
+    /* Set SLEEPDEEP bit of Cortex System Control Register */
+    SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+
+    /* Ensure that all instructions are done before entering STOP mode */
+    __DSB ();
+    __ISB ();
+
+    /* Select Stop mode entry */
+    if (STOPEntry == PWR_STOPENTRY_WFI)
+    {
+      /* Request Wait For Interrupt */
+      __WFI ();
+    }
+    else
+    {
+      /* Request Wait For Event */
+      __WFE ();
+    }
+
+    /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */
+    CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+  }
+#if defined (PWR_CPUCR_PDDS_D2)
+  else if (Domain == PWR_D2_DOMAIN)
+  {
+    /* Keep DSTOP mode when D2 domain enters Deepsleep */
+    CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2);
+
+#if defined (DUAL_CORE)
+    /* Check current core */
+    if (HAL_GetCurrentCPUID () != CM4_CPUID)
+    {
+      /*
+         When the domain selected and the cortex-mx don't match, entering stop
+         mode will not be performed
+      */
+      return;
+    }
+
+    /* Set SLEEPDEEP bit of Cortex System Control Register */
+    SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+
+    /* Ensure that all instructions are done before entering STOP mode */
+    __DSB ();
+    __ISB ();
+
+    /* Select Stop mode entry */
+    if (STOPEntry == PWR_STOPENTRY_WFI)
+    {
+      /* Request Wait For Interrupt */
+      __WFI ();
+    }
+    else
+    {
+      /* Request Wait For Event */
+      __WFE ();
+    }
+
+    /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */
+    CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+#endif /* defined (DUAL_CORE) */
+  }
+#endif /* defined (PWR_CPUCR_PDDS_D2) */
+  else
+  {
+    /* Keep DSTOP mode when D3/SRD domain enters Deepsleep */
+    CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D3);
+  }
+}
+
+/**
+  * @brief Clear pending event.
+  * @note   This API clears the pending event in order to enter a given CPU
+  *         to CSLEEP or CSTOP. It should be called just before APIs performing
+  *         enter low power mode using Wait For Event request.
+  * @retval None.
+  */
+void HAL_PWREx_ClearPendingEvent (void)
+{
+#if defined (DUAL_CORE)
+  /* Check the current Core */
+  if (HAL_GetCurrentCPUID () == CM7_CPUID)
+  {
+    __WFE ();
+  }
+  else
+  {
+    __SEV ();
+    __WFE ();
+  }
+#else
+  __WFE ();
+#endif /* defined (DUAL_CORE) */
+}
+
+/**
+  * @brief Enter a Domain to DSTANDBY mode.
+  * @note   This API gives flexibility to manage independently each domain
+  *         STANDBY mode. For dual core lines, this API should be executed with
+  *         the corresponding Cortex-Mx to enter domain to DSTANDBY mode. When
+  *         it is executed by all available Cortex-Mx, the system enter STANDBY
+  *         mode.
+  *         For single core lines, calling this API with D1/SRD the selected
+  *         domain will enter the whole system in STOP if PWR_CPUCR_PDDS_D3 = 0
+  *         and enter the whole system in STANDBY if PWR_CPUCR_PDDS_D3 = 1.
+  * @note   The DStandby mode is entered when all PDDS_Dn bits in PWR_CPUCR for
+  *         the Dn domain select Standby mode. When the system enters Standby
+  *         mode, the voltage regulator is disabled.
+  * @note   When D2 or D3 domain is in DStandby mode and the CPU sets the
+  *         domain PDDS_Dn bit to select Stop mode, the domain remains in
+  *         DStandby mode. The domain will only exit DStandby when the CPU
+  *         allocates a peripheral in the domain.
+  * @note   The system D3/SRD domain enters Standby mode only when the D1 and D2
+  *         domain are in DStandby.
+  * @note   Before entering DSTANDBY mode it is recommended to call
+  *         SCB_CleanDCache function in order to clean the D-Cache and guarantee
+  *         the data integrity for the SRAM memories.
+  * @param  Domain : Specifies the Domain to enter to STANDBY mode.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_D1_DOMAIN: Enter D1/CD Domain to DSTANDBY mode.
+  *            @arg PWR_D2_DOMAIN: Enter D2 Domain to DSTANDBY mode.
+  *            @arg PWR_D3_DOMAIN: Enter D3/SRD Domain to DSTANDBY mode.
+  * @retval None
+  */
+void HAL_PWREx_EnterSTANDBYMode (uint32_t Domain)
+{
+  /* Check the parameters */
+  assert_param (IS_PWR_DOMAIN (Domain));
+
+  /* Select the domain Power Down DeepSleep */
+  if (Domain == PWR_D1_DOMAIN)
+  {
+#if defined (DUAL_CORE)
+    /* Check current core */
+    if (HAL_GetCurrentCPUID () != CM7_CPUID)
+    {
+      /*
+         When the domain selected and the cortex-mx don't match, entering
+         standby mode will not be performed
+      */
+      return;
+    }
+#endif /* defined (DUAL_CORE) */
+
+    /* Allow DSTANDBY mode when D1/CD domain enters Deepsleep */
+    SET_BIT (PWR-> CPUCR, PWR_CPUCR_PDDS_D1);
+
+#if defined (DUAL_CORE)
+    /* Allow DSTANDBY mode when D1/CD domain enters Deepsleep */
+    SET_BIT (PWR-> CPU2CR, PWR_CPU2CR_PDDS_D1);
+#endif /*DUAL_CORE*/
+
+    /* Set SLEEPDEEP bit of Cortex System Control Register */
+    SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+
+    /* This option is used to ensure that store operations are completed */
+#if defined (__CC_ARM)
+    __force_stores ();
+#endif /* defined (__CC_ARM) */
+
+    /* Request Wait For Interrupt */
+    __WFI ();
+  }
+#if defined (PWR_CPUCR_PDDS_D2)
+  else if (Domain == PWR_D2_DOMAIN)
+  {
+    /* Allow DSTANDBY mode when D2 domain enters Deepsleep */
+    SET_BIT (PWR-> CPUCR, PWR_CPUCR_PDDS_D2);
+
+#if defined (DUAL_CORE)
+    /* Check current core */
+    if (HAL_GetCurrentCPUID () != CM4_CPUID)
+    {
+      /*
+         When the domain selected and the cortex-mx don't match, entering
+         standby mode will not be performed
+      */
+      return;
+    }
+
+    /* Allow DSTANDBY mode when D2 domain enters Deepsleep */
+    SET_BIT (PWR-> CPU2CR, PWR_CPU2CR_PDDS_D2);
+
+    /* Set SLEEPDEEP bit of Cortex System Control Register */
+    SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+
+    /* This option is used to ensure that store operations are completed */
+#if defined (__CC_ARM)
+    __force_stores ();
+#endif /* defined (__CC_ARM) */
+
+    /* Request Wait For Interrupt */
+    __WFI ();
+#endif /* defined (DUAL_CORE) */
+  }
+#endif /* defined (PWR_CPUCR_PDDS_D2) */
+  else
+  {
+    /* Allow DSTANDBY mode when D3/SRD domain enters Deepsleep */
+    SET_BIT (PWR-> CPUCR, PWR_CPUCR_PDDS_D3);
+
+#if defined (DUAL_CORE)
+    /* Allow DSTANDBY mode when D3/SRD domain enters Deepsleep */
+    SET_BIT (PWR-> CPU2CR, PWR_CPU2CR_PDDS_D3);
+#endif /* defined (DUAL_CORE) */
+  }
+}
+
+/**
+  * @brief Configure the D3/SRD Domain state when the System in low power mode.
+  * @param  D3State : Specifies the D3/SRD state.
+  *          This parameter can be one of the following values :
+  *            @arg PWR_D3_DOMAIN_STOP : D3/SRD domain will follow the most deep
+  *                                      CPU sub-system low power mode.
+  *            @arg PWR_D3_DOMAIN_RUN : D3/SRD domain will stay in RUN mode
+  *                                     regardless of the CPU sub-system low
+  *                                     power mode.
+  * @retval None
+  */
+void HAL_PWREx_ConfigD3Domain (uint32_t D3State)
+{
+  /* Check the parameter */
+  assert_param (IS_D3_STATE (D3State));
+
+  /* Keep D3/SRD in run mode */
+  MODIFY_REG (PWR->CPUCR, PWR_CPUCR_RUN_D3, D3State);
+}
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Clear HOLD2F, HOLD1F, STOPF, SBF, SBF_D1, and SBF_D2 flags for a
+  *        given domain.
+  * @param  DomainFlags : Specifies the Domain flags to be cleared.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_D1_DOMAIN_FLAGS : Clear D1 Domain flags.
+  *            @arg PWR_D2_DOMAIN_FLAGS : Clear D2 Domain flags.
+  *            @arg PWR_ALL_DOMAIN_FLAGS : Clear D1 and D2 Domain flags.
+  * @retval None.
+  */
+void HAL_PWREx_ClearDomainFlags (uint32_t DomainFlags)
+{
+  /* Check the parameter */
+  assert_param (IS_PWR_DOMAIN_FLAG (DomainFlags));
+
+  /* D1 CPU flags */
+  if (DomainFlags == PWR_D1_DOMAIN_FLAGS)
+  {
+    /* Clear D1 domain flags (HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2) */
+    SET_BIT (PWR->CPUCR, PWR_CPUCR_CSSF);
+  }
+  /* D2 CPU flags */
+  else if (DomainFlags == PWR_D2_DOMAIN_FLAGS)
+  {
+    /* Clear D2 domain flags (HOLD1F, STOPF, SBF, SBF_D1, and SBF_D2) */
+    SET_BIT (PWR->CPU2CR, PWR_CPU2CR_CSSF);
+  }
+  else
+  {
+    /* Clear D1 domain flags (HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2) */
+    SET_BIT (PWR->CPUCR, PWR_CPUCR_CSSF);
+    /* Clear D2 domain flags (HOLD1F, STOPF, SBF, SBF_D1, and SBF_D2) */
+    SET_BIT (PWR->CPU2CR, PWR_CPU2CR_CSSF);
+  }
+}
+
+/**
+  * @brief Hold the CPU and their domain peripherals when exiting STOP mode.
+  * @param  CPU : Specifies the core to be held.
+  *         This parameter can be one of the following values:
+  *             @arg PWR_CORE_CPU1: Hold CPU1 and set CPU2 as master.
+  *             @arg PWR_CORE_CPU2: Hold CPU2 and set CPU1 as master.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PWREx_HoldCore (uint32_t CPU)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param (IS_PWR_CORE (CPU));
+
+  /* Check CPU index */
+  if (CPU == PWR_CORE_CPU2)
+  {
+    /* If CPU1 is not held */
+    if ((PWR->CPU2CR & PWR_CPU2CR_HOLD1) != PWR_CPU2CR_HOLD1)
+    {
+      /* Set HOLD2 bit */
+      SET_BIT (PWR->CPUCR, PWR_CPUCR_HOLD2);
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* If CPU2 is not held */
+    if ((PWR->CPUCR & PWR_CPUCR_HOLD2) != PWR_CPUCR_HOLD2)
+    {
+      /* Set HOLD1 bit */
+      SET_BIT (PWR->CPU2CR, PWR_CPU2CR_HOLD1);
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief Release the CPU and their domain peripherals after a wake-up from
+  *        STOP mode.
+  * @param  CPU: Specifies the core to be released.
+  *         This parameter can be one of the following values:
+  *             @arg  PWR_CORE_CPU1: Release the CPU1 and their domain
+  *                   peripherals from holding.
+  *             @arg  PWR_CORE_CPU2: Release the CPU2 and their domain
+  *                   peripherals from holding.
+  * @retval None
+  */
+void HAL_PWREx_ReleaseCore (uint32_t CPU)
+{
+  /* Check the parameters */
+  assert_param (IS_PWR_CORE (CPU));
+
+  /* Check CPU index */
+  if (CPU == PWR_CORE_CPU2)
+  {
+    /* Reset HOLD2 bit */
+    CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_HOLD2);
+  }
+  else
+  {
+    /* Reset HOLD1 bit */
+    CLEAR_BIT (PWR->CPU2CR, PWR_CPU2CR_HOLD1);
+  }
+}
+#endif /* defined (DUAL_CORE) */
+
+
+/**
+  * @brief Enable the Flash Power Down in Stop mode.
+  * @note   When Flash Power Down is enabled  the Flash memory enters low-power
+  *         mode when D1/SRD domain is in DStop mode. This feature allows to
+  *         obtain the best trade-off between low-power consumption and restart
+  *         time when exiting from DStop mode.
+  * @retval None.
+  */
+void HAL_PWREx_EnableFlashPowerDown (void)
+{
+  /* Enable the Flash Power Down */
+  SET_BIT (PWR->CR1, PWR_CR1_FLPS);
+}
+
+/**
+  * @brief Disable the Flash Power Down in Stop mode.
+  * @note   When Flash Power Down is disabled  the Flash memory is kept on
+  *         normal mode when D1/SRD domain is in DStop mode. This feature allows
+  *         to obtain the best trade-off between low-power consumption and
+  *         restart time when exiting from DStop mode.
+  * @retval None.
+  */
+void HAL_PWREx_DisableFlashPowerDown (void)
+{
+  /* Disable the Flash Power Down */
+  CLEAR_BIT (PWR->CR1, PWR_CR1_FLPS);
+}
+
+#if defined (PWR_CR1_SRDRAMSO)
+/**
+  * @brief Enable memory block shut-off in DStop or DStop2 modes
+  * @note   In DStop or DStop2 mode, the content of the memory blocks is
+  *         maintained. Further power optimization can be obtained by switching
+  *         off some memory blocks. This optimization implies loss of the memory
+  *         content. The user can select which memory is discarded during STOP
+  *         mode by means of xxSO bits.
+  * @param  MemoryBlock : Specifies the memory block to shut-off during DStop or
+  *                       DStop2 mode.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_SRD_AHB_MEMORY_BLOCK : SmartRun domain AHB memory.
+  *            @arg PWR_USB_FDCAN_MEMORY_BLOCK : High-speed interfaces USB and
+  *                                              FDCAN memories.
+  *            @arg PWR_GFXMMU_JPEG_MEMORY_BLOCK : GFXMMU and JPEG memories.
+  *            @arg PWR_TCM_ECM_MEMORY_BLOCK : Instruction TCM and ETM memories.
+  *            @arg PWR_RAM1_AHB_MEMORY_BLOCK : AHB RAM1 memory.
+  *            @arg PWR_RAM2_AHB_MEMORY_BLOCK : AHB RAM2 memory.
+  *            @arg PWR_RAM1_AXI_MEMORY_BLOCK : AXI RAM1 memory.
+  *            @arg PWR_RAM2_AXI_MEMORY_BLOCK : AXI RAM2 memory.
+  *            @arg PWR_RAM3_AXI_MEMORY_BLOCK : AXI RAM3 memory.
+  * @retval None.
+  */
+void HAL_PWREx_EnableMemoryShutOff (uint32_t MemoryBlock)
+{
+  /* Check the parameter */
+  assert_param (IS_PWR_MEMORY_BLOCK (MemoryBlock));
+
+  /* Enable memory block shut-off */
+  SET_BIT (PWR->CR1, MemoryBlock);
+}
+
+/**
+  * @brief Disable memory block shut-off in DStop or DStop2 modes
+  * @param  MemoryBlock : Specifies the memory block to keep content during
+  *                       DStop or DStop2 mode.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_SRD_AHB_MEMORY_BLOCK : SmartRun domain AHB memory.
+  *            @arg PWR_USB_FDCAN_MEMORY_BLOCK : High-speed interfaces USB and
+  *                                              FDCAN memories.
+  *            @arg PWR_GFXMMU_JPEG_MEMORY_BLOCK : GFXMMU and JPEG memories.
+  *            @arg PWR_TCM_ECM_MEMORY_BLOCK : Instruction TCM and ETM memories.
+  *            @arg PWR_RAM1_AHB_MEMORY_BLOCK : AHB RAM1 memory.
+  *            @arg PWR_RAM2_AHB_MEMORY_BLOCK : AHB RAM2 memory.
+  *            @arg PWR_RAM1_AXI_MEMORY_BLOCK : AXI RAM1 memory.
+  *            @arg PWR_RAM2_AXI_MEMORY_BLOCK : AXI RAM2 memory.
+  *            @arg PWR_RAM3_AXI_MEMORY_BLOCK : AXI RAM3 memory.
+  * @retval None.
+  */
+void HAL_PWREx_DisableMemoryShutOff (uint32_t MemoryBlock)
+{
+  /* Check the parameter */
+  assert_param (IS_PWR_MEMORY_BLOCK (MemoryBlock));
+
+  /* Disable memory block shut-off */
+  CLEAR_BIT (PWR->CR1, MemoryBlock);
+}
+#endif /* defined (PWR_CR1_SRDRAMSO) */
+
+/**
+  * @brief Enable the Wake-up PINx functionality.
+  * @param  sPinParams : Pointer to a PWREx_WakeupPinTypeDef structure that
+  *                      contains the configuration information for the wake-up
+  *                      Pin.
+  * @note   For dual core devices, please ensure to configure the EXTI lines for
+  *         the different Cortex-Mx. All combination are allowed: wake up only
+  *         Cortex-M7, wake up only Cortex-M4 and wake up Cortex-M7 and
+  *         Cortex-M4.
+  * @retval None.
+  */
+void HAL_PWREx_EnableWakeUpPin (PWREx_WakeupPinTypeDef *sPinParams)
+{
+  uint32_t pinConfig;
+  uint32_t regMask;
+  const uint32_t pullMask = PWR_WKUPEPR_WKUPPUPD1;
+
+  /* Check the parameters */
+  assert_param (IS_PWR_WAKEUP_PIN (sPinParams->WakeUpPin));
+  assert_param (IS_PWR_WAKEUP_PIN_POLARITY (sPinParams->PinPolarity));
+  assert_param (IS_PWR_WAKEUP_PIN_PULL (sPinParams->PinPull));
+
+  pinConfig = sPinParams->WakeUpPin | \
+              (sPinParams->PinPolarity << ((POSITION_VAL(sPinParams->WakeUpPin) + PWR_WKUPEPR_WKUPP1_Pos) & 0x1FU)) | \
+              (sPinParams->PinPull << (((POSITION_VAL(sPinParams->WakeUpPin) * PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET) + PWR_WKUPEPR_WKUPPUPD1_Pos) & 0x1FU));
+
+  regMask   = sPinParams->WakeUpPin | \
+              (PWR_WKUPEPR_WKUPP1 << (POSITION_VAL(sPinParams->WakeUpPin) & 0x1FU)) | \
+              (pullMask << ((POSITION_VAL(sPinParams->WakeUpPin) * PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET) & 0x1FU));
+
+  /* Enable and Specify the Wake-Up pin polarity and the pull configuration
+     for the event detection (rising or falling edge) */
+  MODIFY_REG (PWR->WKUPEPR, regMask, pinConfig);
+#ifndef DUAL_CORE
+  /* Configure the Wakeup Pin EXTI Line */
+  MODIFY_REG (EXTI->IMR2, PWR_EXTI_WAKEUP_PINS_MASK, (sPinParams->WakeUpPin << EXTI_IMR2_IM55_Pos));
+#endif /* !DUAL_CORE */
+}
+
+/**
+  * @brief Disable the Wake-up PINx functionality.
+  * @param  WakeUpPin : Specifies the Wake-Up pin to be disabled.
+  *          This parameter can be one of the following values:
+  *           @arg PWR_WAKEUP_PIN1 : Disable PA0  wake-up PIN.
+  *           @arg PWR_WAKEUP_PIN2 : Disable PA2  wake-up PIN.
+  *           @arg PWR_WAKEUP_PIN3 : Disable PI8  wake-up PIN.
+  *           @arg PWR_WAKEUP_PIN4 : Disable PC13 wake-up PIN.
+  *           @arg PWR_WAKEUP_PIN5 : Disable PI11 wake-up PIN.
+  *           @arg PWR_WAKEUP_PIN6 : Disable PC1  wake-up PIN.
+  * @retval None
+  */
+void HAL_PWREx_DisableWakeUpPin (uint32_t WakeUpPin)
+{
+  /* Check the parameter */
+  assert_param (IS_PWR_WAKEUP_PIN (WakeUpPin));
+
+  /* Disable the WakeUpPin */
+  CLEAR_BIT (PWR->WKUPEPR, WakeUpPin);
+}
+
+/**
+  * @brief Get the Wake-Up Pin pending flags.
+  * @param  WakeUpFlag : Specifies the Wake-Up PIN flag to be checked.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_WAKEUP_FLAG1    : Get wakeup event received from PA0.
+  *            @arg PWR_WAKEUP_FLAG2    : Get wakeup event received from PA2.
+  *            @arg PWR_WAKEUP_FLAG3    : Get wakeup event received from PI8.
+  *            @arg PWR_WAKEUP_FLAG4    : Get wakeup event received from PC13.
+  *            @arg PWR_WAKEUP_FLAG5    : Get wakeup event received from PI11.
+  *            @arg PWR_WAKEUP_FLAG6    : Get wakeup event received from PC1.
+  *            @arg PWR_WAKEUP_FLAG_ALL : Get Wakeup event received from all
+  *                                      wake up pins.
+  * @retval The Wake-Up pin flag.
+  */
+uint32_t HAL_PWREx_GetWakeupFlag (uint32_t WakeUpFlag)
+{
+  /* Check the parameters */
+  assert_param (IS_PWR_WAKEUP_FLAG (WakeUpFlag));
+
+  /* Return the wake up pin flag */
+  return (PWR->WKUPFR & WakeUpFlag);
+}
+
+/**
+  * @brief Clear the Wake-Up pin pending flag.
+  * @param  WakeUpFlag: Specifies the Wake-Up PIN flag to clear.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_WAKEUP_FLAG1 : Clear the wakeup event received from PA0.
+  *            @arg PWR_WAKEUP_FLAG2 : Clear the wakeup event received from PA2.
+  *            @arg PWR_WAKEUP_FLAG3 : Clear the wakeup event received from PI8.
+  *            @arg PWR_WAKEUP_FLAG4 : Clear the wakeup event received from PC13.
+  *            @arg PWR_WAKEUP_FLAG5 : Clear the wakeup event received from PI11.
+  *            @arg PWR_WAKEUP_FLAG6 : Clear the wakeup event received from PC1.
+  *            @arg PWR_WAKEUP_FLAG_ALL : Clear the wakeup events received from
+  *                                      all wake up pins.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag (uint32_t WakeUpFlag)
+{
+  /* Check the parameter */
+  assert_param (IS_PWR_WAKEUP_FLAG (WakeUpFlag));
+
+  /* Clear the wake up event received from wake up pin x */
+  SET_BIT (PWR->WKUPCR, WakeUpFlag);
+
+  /* Check if the wake up event is well cleared */
+  if ((PWR->WKUPFR & WakeUpFlag) != 0U)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief This function handles the PWR WAKEUP PIN interrupt request.
+  * @note   This API should be called under the WAKEUP_PIN_IRQHandler().
+  * @retval None.
+  */
+void HAL_PWREx_WAKEUP_PIN_IRQHandler (void)
+{
+  /* Wakeup pin EXTI line interrupt detected */
+  if (READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF1) != 0U)
+  {
+    /* Clear PWR WKUPF1 flag */
+    __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP1);
+
+    /* PWR WKUP1 interrupt user callback */
+    HAL_PWREx_WKUP1_Callback ();
+  }
+  else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF2) != 0U)
+  {
+    /* Clear PWR WKUPF2 flag */
+    __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP2);
+
+    /* PWR WKUP2 interrupt user callback */
+    HAL_PWREx_WKUP2_Callback ();
+  }
+  else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF3) != 0U)
+  {
+    /* Clear PWR WKUPF3 flag */
+    __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP3);
+
+    /* PWR WKUP3 interrupt user callback */
+    HAL_PWREx_WKUP3_Callback ();
+  }
+  else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF4) != 0U)
+  {
+    /* Clear PWR WKUPF4 flag */
+    __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP4);
+
+    /* PWR WKUP4 interrupt user callback */
+    HAL_PWREx_WKUP4_Callback ();
+  }
+  else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF5) != 0U)
+  {
+    /* Clear PWR WKUPF5 flag */
+    __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP5);
+
+    /* PWR WKUP5 interrupt user callback */
+    HAL_PWREx_WKUP5_Callback ();
+  }
+  else
+  {
+    /* Clear PWR WKUPF6 flag */
+    __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP6);
+
+    /* PWR WKUP6 interrupt user callback */
+    HAL_PWREx_WKUP6_Callback ();
+  }
+}
+
+/**
+  * @brief PWR WKUP1 interrupt callback.
+  * @retval None.
+  */
+__weak void HAL_PWREx_WKUP1_Callback (void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PWREx_WKUP1Callback can be implemented in the user file
+  */
+}
+
+/**
+  * @brief PWR WKUP2 interrupt callback.
+  * @retval None.
+  */
+__weak void HAL_PWREx_WKUP2_Callback (void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PWREx_WKUP2Callback can be implemented in the user file
+  */
+}
+
+/**
+  * @brief PWR WKUP3 interrupt callback.
+  * @retval None.
+  */
+__weak void HAL_PWREx_WKUP3_Callback (void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PWREx_WKUP3Callback can be implemented in the user file
+  */
+}
+
+/**
+  * @brief PWR WKUP4 interrupt callback.
+  * @retval None.
+  */
+__weak void HAL_PWREx_WKUP4_Callback (void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PWREx_WKUP4Callback can be implemented in the user file
+  */
+}
+
+/**
+  * @brief PWR WKUP5 interrupt callback.
+  * @retval None.
+  */
+__weak void HAL_PWREx_WKUP5_Callback (void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PWREx_WKUP5Callback can be implemented in the user file
+  */
+}
+
+/**
+  * @brief PWR WKUP6 interrupt callback.
+  * @retval None.
+  */
+__weak void HAL_PWREx_WKUP6_Callback (void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PWREx_WKUP6Callback can be implemented in the user file
+  */
+}
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_Exported_Functions_Group3 Peripherals control functions
+  * @brief    Peripherals control functions
+  *
+@verbatim
+ ===============================================================================
+                 ##### Peripherals control functions #####
+ ===============================================================================
+
+    *** Main and Backup Regulators configuration ***
+    ================================================
+    [..]
+      (+) The backup domain includes 4 Kbytes of backup SRAM accessible only
+          from the CPU, and addressed in 32-bit, 16-bit or 8-bit mode. Its
+          content is retained even in Standby or VBAT mode when the low power
+          backup regulator is enabled. It can be considered as an internal
+          EEPROM when VBAT is always present. You can use the
+          HAL_PWREx_EnableBkUpReg() function to enable the low power backup
+          regulator.
+      (+) When the backup domain is supplied by VDD (analog switch connected to
+          VDD) the backup SRAM is powered from VDD which replaces the VBAT power
+          supply to save battery life.
+      (+) The backup SRAM is not mass erased by a tamper event. It is read
+          protected to prevent confidential data, such as cryptographic private
+          key, from being accessed. The backup SRAM can be erased only through
+          the Flash interface when a protection level change from level 1 to
+          level 0 is requested.
+      -@- Refer to the description of Read protection (RDP) in the Flash
+          programming manual.
+      (+) The main internal regulator can be configured to have a tradeoff
+          between performance and power consumption when the device does not
+          operate at the maximum frequency. This is done through
+          HAL_PWREx_ControlVoltageScaling(VOS) function which configure the VOS
+          bit in PWR_D3CR register.
+      (+) The main internal regulator can be configured to operate in Low Power
+          mode when the system enters STOP mode to further reduce power
+          consumption.
+          This is done through HAL_PWREx_ControlStopModeVoltageScaling(SVOS)
+          function which configure the SVOS bit in PWR_CR1 register.
+          The selected SVOS4 and SVOS5 levels add an additional startup delay
+          when exiting from system Stop mode.
+    -@- Refer to the product datasheets for more details.
+
+    *** USB Regulator configuration ***
+    ===================================
+    [..]
+      (+) The USB transceivers are supplied from a dedicated VDD33USB supply
+          that can be provided either by the integrated USB regulator, or by an
+          external USB supply.
+      (+) The USB regulator is enabled by HAL_PWREx_EnableUSBReg() function, the
+          VDD33USB is then provided from the USB regulator.
+      (+) When the USB regulator is enabled, the VDD33USB supply level detector
+          shall be enabled through  HAL_PWREx_EnableUSBVoltageDetector()
+          function.
+      (+) The USB regulator is disabled through HAL_PWREx_DisableUSBReg()
+          function and VDD33USB can be provided from an external supply. In this
+          case VDD33USB and VDD50USB shall be connected together.
+
+    *** VBAT battery charging ***
+    =============================
+    [..]
+      (+) When VDD is present, the external battery connected to VBAT can be
+          charged through an internal resistance. VBAT charging can be performed
+          either through a 5 KOhm resistor or through a 1.5 KOhm resistor.
+      (+) VBAT charging is enabled by HAL_PWREx_EnableBatteryCharging
+          (ResistorValue) function with:
+       (++) ResistorValue:
+        (+++) PWR_BATTERY_CHARGING_RESISTOR_5: 5 KOhm resistor.
+        (+++) PWR_BATTERY_CHARGING_RESISTOR_1_5: 1.5 KOhm resistor.
+      (+) VBAT charging is disabled by HAL_PWREx_DisableBatteryCharging()
+          function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Enable the Backup Regulator.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg (void)
+{
+  uint32_t tickstart;
+
+  /* Enable the Backup regulator */
+  SET_BIT (PWR->CR2, PWR_CR2_BREN);
+
+  /* Get tick */
+  tickstart = HAL_GetTick ();
+
+  /* Wait till Backup regulator ready flag is set */
+  while (__HAL_PWR_GET_FLAG (PWR_FLAG_BRR) == 0U)
+  {
+    if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Disable the Backup Regulator.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg (void)
+{
+  uint32_t tickstart;
+
+  /* Disable the Backup regulator */
+  CLEAR_BIT (PWR->CR2, PWR_CR2_BREN);
+
+  /* Get tick */
+  tickstart = HAL_GetTick ();
+
+  /* Wait till Backup regulator ready flag is reset */
+  while (__HAL_PWR_GET_FLAG (PWR_FLAG_BRR) != 0U)
+  {
+    if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Enable the USB Regulator.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_PWREx_EnableUSBReg (void)
+{
+  uint32_t tickstart;
+
+  /* Enable the USB regulator */
+  SET_BIT (PWR->CR3, PWR_CR3_USBREGEN);
+
+  /* Get tick */
+  tickstart = HAL_GetTick ();
+
+  /* Wait till the USB regulator ready flag is set */
+  while (__HAL_PWR_GET_FLAG (PWR_FLAG_USB33RDY) == 0U)
+  {
+    if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Disable the USB Regulator.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_PWREx_DisableUSBReg (void)
+{
+  uint32_t tickstart;
+
+  /* Disable the USB regulator */
+  CLEAR_BIT (PWR->CR3, PWR_CR3_USBREGEN);
+
+  /* Get tick */
+  tickstart = HAL_GetTick ();
+
+  /* Wait till the USB regulator ready flag is reset */
+  while(__HAL_PWR_GET_FLAG (PWR_FLAG_USB33RDY) != 0U)
+  {
+    if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Enable the USB voltage level detector.
+  * @retval None.
+  */
+void HAL_PWREx_EnableUSBVoltageDetector (void)
+{
+  /* Enable the USB voltage detector */
+  SET_BIT (PWR->CR3, PWR_CR3_USB33DEN);
+}
+
+/**
+  * @brief Disable the USB voltage level detector.
+  * @retval None.
+  */
+void HAL_PWREx_DisableUSBVoltageDetector (void)
+{
+  /* Disable the USB voltage detector */
+  CLEAR_BIT (PWR->CR3, PWR_CR3_USB33DEN);
+}
+
+/**
+  * @brief Enable the Battery charging.
+  * @note   When VDD is present, charge the external battery through an internal
+  *         resistor.
+  * @param  ResistorValue : Specifies the charging resistor.
+  *          This parameter can be one of the following values :
+  *            @arg PWR_BATTERY_CHARGING_RESISTOR_5 : 5 KOhm resistor.
+  *            @arg PWR_BATTERY_CHARGING_RESISTOR_1_5 : 1.5 KOhm resistor.
+  * @retval None.
+  */
+void HAL_PWREx_EnableBatteryCharging (uint32_t ResistorValue)
+{
+  /* Check the parameter */
+  assert_param (IS_PWR_BATTERY_RESISTOR_SELECT (ResistorValue));
+
+  /* Specify the charging resistor */
+  MODIFY_REG (PWR->CR3, PWR_CR3_VBRS, ResistorValue);
+
+  /* Enable the Battery charging */
+  SET_BIT (PWR->CR3, PWR_CR3_VBE);
+}
+
+/**
+  * @brief Disable the Battery charging.
+  * @retval None.
+  */
+void HAL_PWREx_DisableBatteryCharging (void)
+{
+  /* Disable the Battery charging */
+  CLEAR_BIT (PWR->CR3, PWR_CR3_VBE);
+}
+
+#if defined (PWR_CR1_BOOSTE)
+/**
+  * @brief Enable the booster to guarantee the analog switch AC performance when
+  *        the VDD supply voltage is below 2V7.
+  * @note   The VDD supply voltage can be monitored through the PVD and the PLS
+  *         field bits.
+  * @retval None.
+  */
+void HAL_PWREx_EnableAnalogBooster (void)
+{
+  /* Enable the Analog voltage */
+  SET_BIT (PWR->CR1, PWR_CR1_AVD_READY);
+
+  /* Enable VDDA booster */
+  SET_BIT (PWR->CR1, PWR_CR1_BOOSTE);
+}
+
+/**
+  * @brief Disable the analog booster.
+  * @retval None.
+  */
+void HAL_PWREx_DisableAnalogBooster (void)
+{
+  /* Disable VDDA booster */
+  CLEAR_BIT (PWR->CR1, PWR_CR1_BOOSTE);
+
+  /* Disable the Analog voltage */
+  CLEAR_BIT (PWR->CR1, PWR_CR1_AVD_READY);
+}
+#endif /* defined (PWR_CR1_BOOSTE) */
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_Exported_Functions_Group4 Power Monitoring functions
+  * @brief    Power Monitoring functions
+  *
+@verbatim
+ ===============================================================================
+                 ##### Power Monitoring functions #####
+ ===============================================================================
+
+    *** VBAT and Temperature supervision ***
+    ========================================
+    [..]
+      (+) The VBAT battery voltage supply can be monitored by comparing it with
+          two threshold levels: VBAThigh and VBATlow. VBATH flag and VBATL flags
+          in the PWR control register 2 (PWR_CR2), indicate if VBAT is higher or
+          lower than the threshold.
+      (+) The temperature can be monitored by comparing it with two threshold
+          levels, TEMPhigh and TEMPlow. TEMPH and TEMPL flags, in the PWR
+          control register 2 (PWR_CR2), indicate whether the device temperature
+          is higher or lower than the threshold.
+      (+) The VBAT and the temperature monitoring is enabled by
+          HAL_PWREx_EnableMonitoring() function and disabled by
+          HAL_PWREx_DisableMonitoring() function.
+      (+) The HAL_PWREx_GetVBATLevel() function returns the VBAT level which can
+          be : PWR_VBAT_BELOW_LOW_THRESHOLD or PWR_VBAT_ABOVE_HIGH_THRESHOLD or
+          PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD.
+      (+) The HAL_PWREx_GetTemperatureLevel() function returns the Temperature
+          level which can be :
+          PWR_TEMP_BELOW_LOW_THRESHOLD or PWR_TEMP_ABOVE_HIGH_THRESHOLD or
+          PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD.
+
+    *** AVD configuration ***
+    =========================
+    [..]
+      (+) The AVD is used to monitor the VDDA power supply by comparing it to a
+          threshold selected by the AVD Level (ALS[3:0] bits in the PWR_CR1
+          register).
+      (+) A AVDO flag is available to indicate if VDDA is higher or lower
+          than the AVD threshold. This event is internally connected to the EXTI
+          line 16 to generate an interrupt if enabled.
+          It is configurable through __HAL_PWR_AVD_EXTI_ENABLE_IT() macro.
+      (+) The AVD is stopped in System Standby mode.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Enable the VBAT and temperature monitoring.
+  * @retval HAL status.
+  */
+void HAL_PWREx_EnableMonitoring (void)
+{
+  /* Enable the VBAT and Temperature monitoring */
+  SET_BIT (PWR->CR2, PWR_CR2_MONEN);
+}
+
+/**
+  * @brief Disable the VBAT and temperature monitoring.
+  * @retval HAL status.
+  */
+void HAL_PWREx_DisableMonitoring (void)
+{
+  /* Disable the VBAT and Temperature monitoring */
+  CLEAR_BIT (PWR->CR2, PWR_CR2_MONEN);
+}
+
+/**
+  * @brief Indicate whether the junction temperature is between, above or below
+  *        the thresholds.
+  * @retval Temperature level.
+  */
+uint32_t HAL_PWREx_GetTemperatureLevel (void)
+{
+  uint32_t tempLevel, regValue;
+
+  /* Read the temperature flags */
+  regValue = READ_BIT (PWR->CR2, (PWR_CR2_TEMPH | PWR_CR2_TEMPL));
+
+  /* Check if the temperature is below the threshold */
+  if (regValue == PWR_CR2_TEMPL)
+  {
+    tempLevel = PWR_TEMP_BELOW_LOW_THRESHOLD;
+  }
+  /* Check if the temperature is above the threshold */
+  else if (regValue == PWR_CR2_TEMPH)
+  {
+    tempLevel = PWR_TEMP_ABOVE_HIGH_THRESHOLD;
+  }
+  /* The temperature is between the thresholds */
+  else
+  {
+    tempLevel = PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD;
+  }
+
+  return tempLevel;
+}
+
+/**
+  * @brief Indicate whether the Battery voltage level is between, above or below
+  *        the thresholds.
+  * @retval VBAT level.
+  */
+uint32_t HAL_PWREx_GetVBATLevel (void)
+{
+  uint32_t VBATLevel, regValue;
+
+  /* Read the VBAT flags */
+  regValue = READ_BIT (PWR->CR2, (PWR_CR2_VBATH | PWR_CR2_VBATL));
+
+  /* Check if the VBAT is below the threshold */
+  if (regValue == PWR_CR2_VBATL)
+  {
+    VBATLevel = PWR_VBAT_BELOW_LOW_THRESHOLD;
+  }
+  /* Check if the VBAT is above the threshold */
+  else if (regValue == PWR_CR2_VBATH)
+  {
+    VBATLevel = PWR_VBAT_ABOVE_HIGH_THRESHOLD;
+  }
+  /* The VBAT is between the thresholds */
+  else
+  {
+    VBATLevel = PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD;
+  }
+
+  return VBATLevel;
+}
+
+#if defined (PWR_CSR1_MMCVDO)
+/**
+  * @brief Get the VDDMMC voltage level.
+  * @retval The VDDMMC voltage level.
+  */
+PWREx_MMC_VoltageLevel HAL_PWREx_GetMMCVoltage (void)
+{
+  PWREx_MMC_VoltageLevel mmc_voltage;
+
+  /* Check voltage detector output on VDDMMC value */
+  if ((PWR->CSR1 & PWR_CSR1_MMCVDO_Msk) == 0U)
+  {
+    mmc_voltage = PWR_MMC_VOLTAGE_BELOW_1V2;
+  }
+  else
+  {
+    mmc_voltage = PWR_MMC_VOLTAGE_EQUAL_ABOVE_1V2;
+  }
+
+  return mmc_voltage;
+}
+#endif /* defined (PWR_CSR1_MMCVDO) */
+
+/**
+  * @brief  Configure the event mode and the voltage threshold detected by the
+  *         Analog Voltage Detector (AVD).
+  * @param  sConfigAVD : Pointer to an PWREx_AVDTypeDef structure that contains
+  *                      the configuration information for the AVD.
+  * @note   Refer to the electrical characteristics of your device datasheet for
+  *         more details about the voltage threshold corresponding to each
+  *         detection level.
+  * @note   For dual core devices, please ensure to configure the EXTI lines for
+  *         the different Cortex-Mx through PWR_Exported_Macro provided by this
+  *         driver. All combination are allowed: wake up only Cortex-M7, wake up
+  *         only Cortex-M4 and wake up Cortex-M7 and Cortex-M4.
+  * @retval None.
+  */
+void HAL_PWREx_ConfigAVD (PWREx_AVDTypeDef *sConfigAVD)
+{
+  /* Check the parameters */
+  assert_param (IS_PWR_AVD_LEVEL (sConfigAVD->AVDLevel));
+  assert_param (IS_PWR_AVD_MODE (sConfigAVD->Mode));
+
+  /* Set the ALS[18:17] bits according to AVDLevel value */
+  MODIFY_REG (PWR->CR1, PWR_CR1_ALS, sConfigAVD->AVDLevel);
+
+  /* Clear any previous config */
+#if !defined (DUAL_CORE)
+  __HAL_PWR_AVD_EXTI_DISABLE_EVENT ();
+  __HAL_PWR_AVD_EXTI_DISABLE_IT ();
+#endif /* !defined (DUAL_CORE) */
+
+  __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE ();
+  __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE ();
+
+#if !defined (DUAL_CORE)
+  /* Configure the interrupt mode */
+  if ((sConfigAVD->Mode & AVD_MODE_IT) == AVD_MODE_IT)
+  {
+    __HAL_PWR_AVD_EXTI_ENABLE_IT ();
+  }
+
+  /* Configure the event mode */
+  if ((sConfigAVD->Mode & AVD_MODE_EVT) == AVD_MODE_EVT)
+  {
+    __HAL_PWR_AVD_EXTI_ENABLE_EVENT ();
+  }
+#endif /* !defined (DUAL_CORE) */
+
+  /* Rising edge configuration */
+  if ((sConfigAVD->Mode & AVD_RISING_EDGE) == AVD_RISING_EDGE)
+  {
+    __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE ();
+  }
+
+  /* Falling edge configuration */
+  if ((sConfigAVD->Mode & AVD_FALLING_EDGE) == AVD_FALLING_EDGE)
+  {
+    __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE ();
+  }
+}
+
+/**
+  * @brief Enable the Analog Voltage Detector (AVD).
+  * @retval None.
+  */
+void HAL_PWREx_EnableAVD (void)
+{
+  /* Enable the Analog Voltage Detector */
+  SET_BIT (PWR->CR1, PWR_CR1_AVDEN);
+}
+
+/**
+  * @brief Disable the Analog Voltage Detector(AVD).
+  * @retval None.
+  */
+void HAL_PWREx_DisableAVD (void)
+{
+  /* Disable the Analog Voltage Detector */
+  CLEAR_BIT (PWR->CR1, PWR_CR1_AVDEN);
+}
+
+/**
+  * @brief  This function handles the PWR PVD/AVD interrupt request.
+  * @note   This API should be called under the PVD_AVD_IRQHandler().
+  * @retval None
+  */
+void HAL_PWREx_PVD_AVD_IRQHandler (void)
+{
+  /* Check if the Programmable Voltage Detector is enabled (PVD) */
+  if(READ_BIT (PWR->CR1, PWR_CR1_PVDEN) != 0U)
+  {
+#if defined (DUAL_CORE)
+    if (HAL_GetCurrentCPUID () == CM7_CPUID)
+#endif /* defined (DUAL_CORE) */
+    {
+      /* Check PWR D1/CD EXTI flag */
+      if(__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U)
+      {
+        /* PWR PVD interrupt user callback */
+        HAL_PWR_PVDCallback ();
+
+        /* Clear PWR EXTI D1/CD pending bit */
+        __HAL_PWR_PVD_EXTI_CLEAR_FLAG ();
+      }
+    }
+#if defined (DUAL_CORE)
+    else
+    {
+      /* Check PWR EXTI D2 flag */
+      if (__HAL_PWR_PVD_EXTID2_GET_FLAG () != 0U)
+      {
+        /* PWR PVD interrupt user callback */
+        HAL_PWR_PVDCallback ();
+
+        /* Clear PWR EXTI D2 pending bit */
+        __HAL_PWR_PVD_EXTID2_CLEAR_FLAG();
+      }
+    }
+#endif /* defined (DUAL_CORE) */
+  }
+
+  /* Check if the Analog Voltage Detector is enabled (AVD) */
+  if (READ_BIT (PWR->CR1, PWR_CR1_AVDEN) != 0U)
+  {
+#if defined (DUAL_CORE)
+    if (HAL_GetCurrentCPUID () == CM7_CPUID)
+#endif /* defined (DUAL_CORE) */
+    {
+      /* Check PWR EXTI D1/CD flag */
+      if (__HAL_PWR_AVD_EXTI_GET_FLAG () != 0U)
+      {
+        /* PWR AVD interrupt user callback */
+        HAL_PWREx_AVDCallback ();
+
+        /* Clear PWR EXTI D1/CD pending bit */
+        __HAL_PWR_AVD_EXTI_CLEAR_FLAG ();
+      }
+    }
+#if defined (DUAL_CORE)
+    else
+    {
+      /* Check PWR EXTI D2 flag */
+      if (__HAL_PWR_AVD_EXTID2_GET_FLAG () != 0U)
+      {
+        /* PWR AVD interrupt user callback */
+        HAL_PWREx_AVDCallback ();
+
+        /* Clear PWR EXTI D2 pending bit */
+        __HAL_PWR_AVD_EXTID2_CLEAR_FLAG ();
+      }
+    }
+#endif /* defined (DUAL_CORE) */
+  }
+}
+
+/**
+  * @brief PWR AVD interrupt callback.
+  * @retval None.
+  */
+__weak void HAL_PWREx_AVDCallback (void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PWR_AVDCallback can be implemented in the user file
+  */
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c
new file mode 100644
index 00000000..7d73fa57
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c
@@ -0,0 +1,1775 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_rcc.c
+  * @author  MCD Application Team
+  * @brief   RCC HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Reset and Clock Control (RCC) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions
+  *
+  @verbatim
+  ==============================================================================
+                      ##### RCC specific features #####
+  ==============================================================================
+    [..]
+      After reset the device is running from Internal High Speed oscillator
+      (HSI 64MHz) with Flash 0 wait state,and all peripherals are off except
+      internal SRAM, Flash, JTAG and PWR
+      (+) There is no pre-scaler on High speed (AHB) and Low speed (APB) buses;
+          all peripherals mapped on these buses are running at HSI speed.
+      (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
+      (+) All GPIOs are in analogue mode , except the JTAG pins which
+          are assigned to be used for debug purpose.
+
+    [..]
+      Once the device started from reset, the user application has to:
+      (+) Configure the clock source to be used to drive the System clock
+          (if the application needs higher frequency/performance)
+      (+) Configure the System clock frequency and Flash settings
+      (+) Configure the AHB and APB buses pre-scalers
+      (+) Enable the clock for the peripheral(s) to be used
+      (+) Configure the clock kernel source(s) for peripherals which clocks are not
+          derived from the System clock through :RCC_D1CCIPR,RCC_D2CCIP1R,RCC_D2CCIP2R
+          and RCC_D3CCIPR registers
+
+                      ##### RCC Limitations #####
+  ==============================================================================
+    [..]
+      A delay between an RCC peripheral clock enable and the effective peripheral
+      enabling should be taken into account in order to manage the peripheral read/write
+      from/to registers.
+      (+) This delay depends on the peripheral mapping.
+      (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
+          after the clock enable bit is set on the hardware register
+      (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
+          after the clock enable bit is set on the hardware register
+
+    [..]
+      Implemented Workaround:
+      (+) For AHB & APB peripherals, a dummy read to the peripheral register has been
+          inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
+
+  @endverbatim
+ ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup RCC  RCC
+  * @brief RCC HAL module driver
+  * @{
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup RCC_Private_Macros RCC Private Macros
+  * @{
+  */
+#define MCO1_CLK_ENABLE()     __HAL_RCC_GPIOA_CLK_ENABLE()
+#define MCO1_GPIO_PORT        GPIOA
+#define MCO1_PIN              GPIO_PIN_8
+
+#define MCO2_CLK_ENABLE()      __HAL_RCC_GPIOC_CLK_ENABLE()
+#define MCO2_GPIO_PORT         GPIOC
+#define MCO2_PIN               GPIO_PIN_9
+
+/**
+  * @}
+  */
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup RCC_Private_Variables RCC Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Functions RCC Exported Functions
+  * @{
+  */
+
+/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+           ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]
+      This section provides functions allowing to configure the internal/external oscillators
+      (HSE, HSI, LSE,CSI, LSI,HSI48, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB3, AHB1
+       AHB2,AHB4,APB3, APB1L, APB1H, APB2, and APB4).
+
+    [..] Internal/external clock and PLL configuration
+         (#) HSI (high-speed internal), 64 MHz factory-trimmed RC used directly or through
+             the PLL as System clock source.
+         (#) CSI is a low-power RC oscillator which can be used directly as system clock, peripheral
+             clock, or PLL input.But even with frequency calibration, is less accurate than an
+             external crystal oscillator or ceramic resonator.
+         (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
+             clock source.
+
+         (#) HSE (high-speed external), 4 to 48 MHz crystal oscillator used directly or
+             through the PLL as System clock source. Can be used also as RTC clock source.
+
+         (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
+
+         (#) PLL , The RCC features three independent PLLs (clocked by HSI , HSE or CSI),
+             featuring three different output clocks and able  to work either in integer or Fractional mode.
+           (++) A main PLL, PLL1, which is generally used to provide clocks to the CPU
+                and to some peripherals.
+           (++) Two dedicated PLLs, PLL2 and PLL3, which are used to generate the kernel clock for peripherals.
+
+
+         (#) CSS (Clock security system), once enabled and if a HSE clock failure occurs
+            (HSE used directly or through PLL as System clock source), the System clock
+             is automatically switched to HSI and an interrupt is generated if enabled.
+             The interrupt is linked to the Cortex-M NMI (Non-Mask-able Interrupt)
+             exception vector.
+
+         (#) MCO1 (micro controller clock output), used to output HSI, LSE, HSE, PLL1(PLL1_Q)
+             or HSI48 clock (through a configurable pre-scaler) on PA8 pin.
+
+         (#) MCO2 (micro controller clock output), used to output HSE, PLL2(PLL2_P), SYSCLK,
+             LSI, CSI, or PLL1(PLL1_P) clock (through a configurable pre-scaler) on PC9 pin.
+
+    [..] System, AHB and APB buses clocks configuration
+         (#) Several clock sources can be used to drive the System clock (SYSCLK): CSI,HSI,
+             HSE and PLL.
+             The AHB clock (HCLK) is derived from System core clock through configurable
+             pre-scaler and used to clock the CPU, memory and peripherals mapped
+             on AHB and APB bus of the 3 Domains (D1, D2, D3)* through configurable pre-scalers
+             and used to clock the peripherals mapped on these buses. You can use
+             "HAL_RCC_GetSysClockFreq()" function to retrieve system clock frequency.
+
+         -@- All the peripheral clocks are derived from the System clock (SYSCLK) except those
+             with dual clock domain where kernel source clock could be selected through
+             RCC_D1CCIPR,RCC_D2CCIP1R,RCC_D2CCIP2R and RCC_D3CCIPR registers.
+
+     (*) : 2 Domains (CD and SRD) for stm32h7a3xx and stm32h7b3xx family lines.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Resets the RCC clock configuration to the default reset state.
+  * @note   The default reset state of the clock configuration is given below:
+  *            - HSI ON and used as system clock source
+  *            - HSE, PLL1, PLL2 and PLL3 OFF
+  *            - AHB, APB Bus pre-scaler set to 1.
+  *            - CSS, MCO1 and MCO2 OFF
+  *            - All interrupts disabled
+  * @note   This function doesn't modify the configuration of the
+  *            - Peripheral clocks
+  *            - LSI, LSE and RTC clocks
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCC_DeInit(void)
+{
+  uint32_t tickstart;
+
+        /* Increasing the CPU frequency */
+  if(FLASH_LATENCY_DEFAULT  > __HAL_FLASH_GET_LATENCY())
+  {
+    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+    __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT);
+
+    /* Check that the new number of wait states is taken into account to access the Flash
+    memory by reading the FLASH_ACR register */
+    if(__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT)
+    {
+      return HAL_ERROR;
+    }
+
+  }
+
+
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Set HSION bit */
+  SET_BIT(RCC->CR, RCC_CR_HSION);
+
+  /* Wait till HSI is ready */
+  while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Set HSITRIM[6:0] bits to the reset value */
+  SET_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM_6);
+
+  /* Reset CFGR register */
+  CLEAR_REG(RCC->CFGR);
+
+  /* Update the SystemCoreClock and SystemD2Clock global variables */
+  SystemCoreClock = HSI_VALUE;
+  SystemD2Clock = HSI_VALUE;
+
+  /* Adapt Systick interrupt period */
+  if(HAL_InitTick(uwTickPrio) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait till clock switch is ready */
+  while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Reset CSION, CSIKERON, HSEON, HSI48ON, HSECSSON, HSIDIV bits */
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSIKERON| RCC_CR_HSIDIV| RCC_CR_HSIDIVF| RCC_CR_CSION | RCC_CR_CSIKERON  \
+  | RCC_CR_HSI48ON | RCC_CR_CSSHSEON);
+
+  /* Wait till HSE is disabled */
+  while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Clear PLLON bit */
+  CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON);
+
+  /* Wait till PLL is disabled */
+  while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) != 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Reset PLL2ON bit */
+  CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
+
+  /* Wait till PLL2 is disabled */
+  while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Reset PLL3 bit */
+  CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
+
+  /* Wait till PLL3 is disabled */
+  while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+#if defined(RCC_D1CFGR_HPRE)
+  /* Reset D1CFGR register */
+  CLEAR_REG(RCC->D1CFGR);
+
+  /* Reset D2CFGR register */
+  CLEAR_REG(RCC->D2CFGR);
+
+  /* Reset D3CFGR register */
+  CLEAR_REG(RCC->D3CFGR);
+#else
+  /* Reset CDCFGR1 register */
+  CLEAR_REG(RCC->CDCFGR1);
+
+  /* Reset CDCFGR2 register */
+  CLEAR_REG(RCC->CDCFGR2);
+
+  /* Reset SRDCFGR register */
+  CLEAR_REG(RCC->SRDCFGR);
+#endif
+
+  /* Reset PLLCKSELR register to default value */
+  RCC->PLLCKSELR= RCC_PLLCKSELR_DIVM1_5|RCC_PLLCKSELR_DIVM2_5|RCC_PLLCKSELR_DIVM3_5;
+
+  /* Reset PLLCFGR register to default value */
+  WRITE_REG(RCC->PLLCFGR, 0x01FF0000U);
+
+  /* Reset PLL1DIVR register to default value */
+  WRITE_REG(RCC->PLL1DIVR,0x01010280U);
+
+  /* Reset PLL1FRACR register */
+  CLEAR_REG(RCC->PLL1FRACR);
+
+  /* Reset PLL2DIVR register to default value */
+  WRITE_REG(RCC->PLL2DIVR,0x01010280U);
+
+  /* Reset PLL2FRACR register */
+  CLEAR_REG(RCC->PLL2FRACR);
+
+  /* Reset PLL3DIVR register to default value */
+  WRITE_REG(RCC->PLL3DIVR,0x01010280U);
+
+  /* Reset PLL3FRACR register */
+  CLEAR_REG(RCC->PLL3FRACR);
+
+  /* Reset HSEBYP bit */
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
+
+  /* Disable all interrupts */
+  CLEAR_REG(RCC->CIER);
+
+  /* Clear all interrupts flags */
+  WRITE_REG(RCC->CICR,0xFFFFFFFFU);
+
+  /* Reset all RSR flags */
+  SET_BIT(RCC->RSR, RCC_RSR_RMVF);
+
+      /* Decreasing the number of wait states because of lower CPU frequency */
+  if(FLASH_LATENCY_DEFAULT  < __HAL_FLASH_GET_LATENCY())
+  {
+    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+    __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT);
+
+    /* Check that the new number of wait states is taken into account to access the Flash
+    memory by reading the FLASH_ACR register */
+    if(__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT)
+    {
+      return HAL_ERROR;
+    }
+
+}
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the RCC Oscillators according to the specified parameters in the
+  *         RCC_OscInitTypeDef.
+  * @param  RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
+  *         contains the configuration information for the RCC Oscillators.
+  * @note   The PLL is not disabled when used as system clock.
+  * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
+  *         supported by this function. User should request a transition to LSE Off
+  *         first and then LSE On or LSE Bypass.
+  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
+  *         supported by this function. User should request a transition to HSE Off
+  *         first and then HSE On or HSE Bypass.
+  * @retval HAL status
+  */
+__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
+{
+  uint32_t tickstart;
+  uint32_t temp1_pllckcfg, temp2_pllckcfg;
+
+    /* Check Null pointer */
+  if(RCC_OscInitStruct == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
+  /*------------------------------- HSE Configuration ------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
+
+    const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
+    const uint32_t temp_pllckselr = RCC->PLLCKSELR;
+    /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
+    if((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE)))
+    {
+      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
+      {
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Set the new HSE configuration ---------------------------------------*/
+      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
+
+      /* Check the HSE State */
+      if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
+      {
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSE is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
+        {
+          if((uint32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+      else
+      {
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSE is disabled */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
+        {
+          if((uint32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+  }
+  /*----------------------------- HSI Configuration --------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
+    assert_param(IS_RCC_HSICALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
+
+    /* When the HSI is used as system clock it will not be disabled */
+    const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
+    const uint32_t temp_pllckselr = RCC->PLLCKSELR;
+    if((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI)))
+    {
+      /* When HSI is used as system clock it will not be disabled */
+      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
+      {
+        return HAL_ERROR;
+      }
+      /* Otherwise, just the calibration is allowed */
+      else
+      {
+        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+      }
+    }
+
+    else
+    {
+      /* Check the HSI State */
+      if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
+      {
+     /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */
+        __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSI is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
+        {
+          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+
+        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+      }
+      else
+      {
+        /* Disable the Internal High Speed oscillator (HSI). */
+        __HAL_RCC_HSI_DISABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSI is disabled */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
+        {
+          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+  }
+  /*----------------------------- CSI Configuration --------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState));
+    assert_param(IS_RCC_CSICALIBRATION_VALUE(RCC_OscInitStruct->CSICalibrationValue));
+
+    /* When the CSI is used as system clock it will not disabled */
+    const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
+    const uint32_t temp_pllckselr = RCC->PLLCKSELR;
+    if((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI)))
+    {
+      /* When CSI is used as system clock it will not disabled */
+      if((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON))
+      {
+        return HAL_ERROR;
+      }
+      /* Otherwise, just the calibration is allowed */
+      else
+      {
+        /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/
+        __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
+      }
+    }
+    else
+    {
+      /* Check the CSI State */
+      if((RCC_OscInitStruct->CSIState)!= RCC_CSI_OFF)
+      {
+        /* Enable the Internal High Speed oscillator (CSI). */
+        __HAL_RCC_CSI_ENABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till CSI is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)
+        {
+          if((HAL_GetTick() - tickstart ) > CSI_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+
+        /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/
+        __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
+      }
+      else
+      {
+        /* Disable the Internal High Speed oscillator (CSI). */
+        __HAL_RCC_CSI_DISABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till CSI is disabled */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U)
+        {
+          if((HAL_GetTick() - tickstart ) > CSI_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+  }
+  /*------------------------------ LSI Configuration -------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
+
+    /* Check the LSI State */
+    if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
+    {
+      /* Enable the Internal Low Speed oscillator (LSI). */
+      __HAL_RCC_LSI_ENABLE();
+
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSI is ready */
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
+      {
+        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    else
+    {
+      /* Disable the Internal Low Speed oscillator (LSI). */
+      __HAL_RCC_LSI_DISABLE();
+
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSI is ready */
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
+      {
+        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /*------------------------------ HSI48 Configuration -------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
+
+    /* Check the HSI48 State */
+    if((RCC_OscInitStruct->HSI48State)!= RCC_HSI48_OFF)
+    {
+      /* Enable the Internal Low Speed oscillator (HSI48). */
+      __HAL_RCC_HSI48_ENABLE();
+
+      /* Get time-out */
+      tickstart = HAL_GetTick();
+
+      /* Wait till HSI48 is ready */
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U)
+      {
+        if((HAL_GetTick() - tickstart ) > HSI48_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    else
+    {
+      /* Disable the Internal Low Speed oscillator (HSI48). */
+      __HAL_RCC_HSI48_DISABLE();
+
+      /* Get time-out */
+      tickstart = HAL_GetTick();
+
+      /* Wait till HSI48 is ready */
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U)
+      {
+        if((HAL_GetTick() - tickstart ) > HSI48_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  /*------------------------------ LSE Configuration -------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
+
+    /* Enable write access to Backup domain */
+    PWR->CR1 |= PWR_CR1_DBP;
+
+    /* Wait for Backup domain Write protection disable */
+    tickstart = HAL_GetTick();
+
+    while((PWR->CR1 & PWR_CR1_DBP) == 0U)
+    {
+      if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Set the new LSE configuration -----------------------------------------*/
+    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
+    /* Check the LSE State */
+    if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
+    {
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSE is ready */
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
+      {
+        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    else
+    {
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSE is disabled */
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
+      {
+        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  /*-------------------------------- PLL Configuration -----------------------*/
+  /* Check the parameters */
+  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
+  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
+  {
+    /* Check if the PLL is used as system clock or not */
+    if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1)
+    {
+      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
+      {
+        /* Check the parameters */
+        assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
+        assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
+        assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
+        assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
+        assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
+        assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
+        assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN));
+
+        /* Disable the main PLL. */
+        __HAL_RCC_PLL_DISABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till PLL is disabled */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
+        {
+          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+
+        /* Configure the main PLL clock source, multiplication and division factors. */
+        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
+                             RCC_OscInitStruct->PLL.PLLM,
+                             RCC_OscInitStruct->PLL.PLLN,
+                             RCC_OscInitStruct->PLL.PLLP,
+                             RCC_OscInitStruct->PLL.PLLQ,
+                             RCC_OscInitStruct->PLL.PLLR);
+
+         /* Disable PLLFRACN . */
+         __HAL_RCC_PLLFRACN_DISABLE();
+
+         /* Configure PLL PLL1FRACN */
+         __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN);
+
+        /* Select PLL1 input reference frequency range: VCI */
+        __HAL_RCC_PLL_VCIRANGE(RCC_OscInitStruct->PLL.PLLRGE) ;
+
+        /* Select PLL1 output frequency range : VCO */
+        __HAL_RCC_PLL_VCORANGE(RCC_OscInitStruct->PLL.PLLVCOSEL) ;
+
+        /* Enable PLL System Clock output. */
+         __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
+
+        /* Enable PLL1Q Clock output. */
+         __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+        /* Enable PLL1R  Clock output. */
+         __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR);
+
+        /* Enable PLL1FRACN . */
+         __HAL_RCC_PLLFRACN_ENABLE();
+
+        /* Enable the main PLL. */
+        __HAL_RCC_PLL_ENABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till PLL is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
+        {
+          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+      else
+      {
+        /* Disable the main PLL. */
+        __HAL_RCC_PLL_DISABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till PLL is disabled */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
+        {
+          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+    else
+    {
+      /* Do not return HAL_ERROR if request repeats the current configuration */
+      temp1_pllckcfg = RCC->PLLCKSELR;
+      temp2_pllckcfg = RCC->PLL1DIVR;
+      if(((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
+	 (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
+         ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) ||
+         (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) ||
+         ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) ||
+         ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) ||
+         ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U)))
+      {
+        return HAL_ERROR;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CPU, AHB and APB buses clocks according to the specified
+  *         parameters in the RCC_ClkInitStruct.
+  * @param  RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
+  *         contains the configuration information for the RCC peripheral.
+  * @param  FLatency: FLASH Latency, this parameter depend on device selected
+  *
+  * @note   The SystemCoreClock CMSIS variable is used to store System Core Clock Frequency
+  *         and updated by HAL_InitTick() function called within this function
+  *
+  * @note   The HSI is used (enabled by hardware) as system clock source after
+  *         start-up from Reset, wake-up from STOP and STANDBY mode, or in case
+  *         of failure of the HSE used directly or indirectly as system clock
+  *         (if the Clock Security System CSS is enabled).
+  *
+  * @note   A switch from one clock source to another occurs only if the target
+  *         clock source is ready (clock stable after start-up delay or PLL locked).
+  *         If a clock source which is not yet ready is selected, the switch will
+  *         occur when the clock source will be ready.
+  *         You can use HAL_RCC_GetClockConfig() function to know which clock is
+  *         currently used as system clock source.
+  * @note   Depending on the device voltage range, the software has to set correctly
+  *         D1CPRE[3:0] bits to ensure that  Domain1 core clock not exceed the maximum allowed frequency
+  *         (for more details refer to section above "Initialization/de-initialization functions")
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
+{
+  HAL_StatusTypeDef halstatus;
+  uint32_t tickstart;
+  uint32_t common_system_clock;
+
+   /* Check Null pointer */
+  if(RCC_ClkInitStruct == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
+  assert_param(IS_FLASH_LATENCY(FLatency));
+
+  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
+    must be correctly programmed according to the frequency of the CPU clock
+    (HCLK) and the supply voltage of the device. */
+
+  /* Increasing the CPU frequency */
+  if(FLatency > __HAL_FLASH_GET_LATENCY())
+  {
+    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+    __HAL_FLASH_SET_LATENCY(FLatency);
+
+    /* Check that the new number of wait states is taken into account to access the Flash
+    memory by reading the FLASH_ACR register */
+    if(__HAL_FLASH_GET_LATENCY() != FLatency)
+    {
+      return HAL_ERROR;
+    }
+
+  }
+
+  /* Increasing the BUS frequency divider */
+  /*-------------------------- D1PCLK1/CDPCLK1 Configuration ---------------------------*/
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1)
+  {
+#if defined (RCC_D1CFGR_D1PPRE)
+    if((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_D1PPRE))
+    {
+      assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider));
+      MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider);
+    }
+#else
+    if((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE))
+    {
+      assert_param(IS_RCC_CDPCLK1(RCC_ClkInitStruct->APB3CLKDivider));
+      MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, RCC_ClkInitStruct->APB3CLKDivider);
+    }
+#endif
+  }
+
+  /*-------------------------- PCLK1 Configuration ---------------------------*/
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+  {
+#if defined (RCC_D2CFGR_D2PPRE1)
+    if((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1))
+    {
+      assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
+      MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
+    }
+#else
+    if((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1))
+    {
+      assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
+      MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
+  }
+#endif
+    }
+  /*-------------------------- PCLK2 Configuration ---------------------------*/
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+  {
+#if defined(RCC_D2CFGR_D2PPRE2)
+    if((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2))
+    {
+      assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
+      MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
+    }
+#else
+     if((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2))
+    {
+      assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
+      MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
+    }
+#endif
+  }
+
+  /*-------------------------- D3PCLK1 Configuration ---------------------------*/
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1)
+  {
+#if defined(RCC_D3CFGR_D3PPRE)
+    if((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->D3CFGR & RCC_D3CFGR_D3PPRE))
+    {
+      assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider));
+      MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider) );
+    }
+#else
+    if((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE))
+    {
+      assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider));
+      MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, (RCC_ClkInitStruct->APB4CLKDivider) );
+    }
+#endif
+  }
+
+   /*-------------------------- HCLK Configuration --------------------------*/
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+  {
+#if defined (RCC_D1CFGR_HPRE)
+    if((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_HPRE))
+    {
+      /* Set the new HCLK clock divider */
+      assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+      MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+    }
+#else
+        if((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->CDCFGR1 & RCC_CDCFGR1_HPRE))
+    {
+      /* Set the new HCLK clock divider */
+      assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+      MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+    }
+#endif
+  }
+
+    /*------------------------- SYSCLK Configuration -------------------------*/
+    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
+    {
+      assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider));
+      assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
+#if defined(RCC_D1CFGR_D1CPRE)
+      MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider);
+#else
+      MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, RCC_ClkInitStruct->SYSCLKDivider);
+#endif
+      /* HSE is selected as System Clock Source */
+      if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+      {
+        /* Check the HSE ready flag */
+        if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
+        {
+          return HAL_ERROR;
+        }
+      }
+      /* PLL is selected as System Clock Source */
+      else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+      {
+        /* Check the PLL ready flag */
+        if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
+        {
+          return HAL_ERROR;
+        }
+      }
+      /* CSI is selected as System Clock Source */
+      else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI)
+      {
+        /* Check the PLL ready flag */
+        if(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)
+        {
+          return HAL_ERROR;
+        }
+      }
+      /* HSI is selected as System Clock Source */
+      else
+      {
+        /* Check the HSI ready flag */
+        if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
+        {
+          return HAL_ERROR;
+        }
+      }
+      MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
+
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+        while (__HAL_RCC_GET_SYSCLK_SOURCE() !=  (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
+        {
+          if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+
+    }
+
+    /* Decreasing the BUS frequency divider */
+   /*-------------------------- HCLK Configuration --------------------------*/
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+  {
+#if defined(RCC_D1CFGR_HPRE)
+    if((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_HPRE))
+    {
+      /* Set the new HCLK clock divider */
+      assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+      MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+    }
+#else
+    if((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->CDCFGR1 & RCC_CDCFGR1_HPRE))
+    {
+      /* Set the new HCLK clock divider */
+      assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+      MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+    }
+#endif
+  }
+
+  /* Decreasing the number of wait states because of lower CPU frequency */
+  if(FLatency < __HAL_FLASH_GET_LATENCY())
+  {
+    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+    __HAL_FLASH_SET_LATENCY(FLatency);
+
+    /* Check that the new number of wait states is taken into account to access the Flash
+    memory by reading the FLASH_ACR register */
+    if(__HAL_FLASH_GET_LATENCY() != FLatency)
+    {
+      return HAL_ERROR;
+    }
+ }
+
+  /*-------------------------- D1PCLK1/CDPCLK Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1)
+ {
+#if defined(RCC_D1CFGR_D1PPRE)
+   if((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_D1PPRE))
+   {
+     assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider));
+     MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider);
+   }
+#else
+   if((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE))
+   {
+     assert_param(IS_RCC_CDPCLK1(RCC_ClkInitStruct->APB3CLKDivider));
+     MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, RCC_ClkInitStruct->APB3CLKDivider);
+   }
+#endif
+ }
+
+  /*-------------------------- PCLK1 Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ {
+#if defined(RCC_D2CFGR_D2PPRE1)
+   if((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1))
+   {
+     assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
+     MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
+   }
+#else
+   if((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1))
+   {
+     assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
+     MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
+   }
+#endif
+ }
+
+  /*-------------------------- PCLK2 Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+ {
+#if defined (RCC_D2CFGR_D2PPRE2)
+   if((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2))
+   {
+     assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
+     MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
+   }
+#else
+   if((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2))
+   {
+     assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
+     MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
+   }
+#endif
+ }
+
+  /*-------------------------- D3PCLK1/SRDPCLK1 Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1)
+ {
+#if defined(RCC_D3CFGR_D3PPRE)
+   if((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->D3CFGR & RCC_D3CFGR_D3PPRE))
+   {
+     assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider));
+     MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider) );
+   }
+#else
+   if((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE))
+   {
+     assert_param(IS_RCC_SRDPCLK1(RCC_ClkInitStruct->APB4CLKDivider));
+     MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, (RCC_ClkInitStruct->APB4CLKDivider) );
+   }
+#endif
+ }
+
+  /* Update the SystemCoreClock global variable */
+#if defined(RCC_D1CFGR_D1CPRE)
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
+#else
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
+#endif
+
+#if defined(RCC_D1CFGR_HPRE)
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+#else
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+#endif
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  SystemCoreClock = SystemD2Clock;
+#else
+  SystemCoreClock = common_system_clock;
+#endif /* DUAL_CORE && CORE_CM4 */
+
+  /* Configure the source of time base considering new system clocks settings*/
+  halstatus = HAL_InitTick (uwTickPrio);
+
+  return halstatus;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Group2 Peripheral Control functions
+ *  @brief   RCC clocks control functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the RCC Clocks
+    frequencies.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
+  * @note   PA8/PC9 should be configured in alternate function mode.
+  * @param  RCC_MCOx: specifies the output direction for the clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
+  *            @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
+  * @param  RCC_MCOSource: specifies the clock source to output.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_PLL1QCLK:  PLL1Q clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_HSI48: HSI48 (48MHZ) selected as MCO1 source
+  *            @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_PLL2PCLK: PLL2P clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_PLLCLK:  PLL1P clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_CSICLK:  CSI clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_LSICLK:  LSI clock selected as MCO2 source
+  * @param  RCC_MCODiv: specifies the MCOx pre-scaler.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCODIV_1 up to RCC_MCODIV_15  : divider applied to MCOx clock
+  * @retval None
+  */
+void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
+{
+  GPIO_InitTypeDef GPIO_InitStruct;
+  /* Check the parameters */
+  assert_param(IS_RCC_MCO(RCC_MCOx));
+  assert_param(IS_RCC_MCODIV(RCC_MCODiv));
+  /* RCC_MCO1 */
+  if(RCC_MCOx == RCC_MCO1)
+  {
+    assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
+
+    /* MCO1 Clock Enable */
+    MCO1_CLK_ENABLE();
+
+    /* Configure the MCO1 pin in alternate function mode */
+    GPIO_InitStruct.Pin = MCO1_PIN;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
+    HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
+
+    /* Mask MCO1 and MCO1PRE[3:0] bits then Select MCO1 clock source and pre-scaler */
+    MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
+  }
+  else
+  {
+    assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
+
+    /* MCO2 Clock Enable */
+    MCO2_CLK_ENABLE();
+
+    /* Configure the MCO2 pin in alternate function mode */
+    GPIO_InitStruct.Pin = MCO2_PIN;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
+    HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
+
+    /* Mask MCO2 and MCO2PRE[3:0] bits then Select MCO2 clock source and pre-scaler */
+    MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 7U)));
+  }
+}
+
+/**
+  * @brief  Enables the Clock Security System.
+  * @note   If a failure is detected on the HSE oscillator clock, this oscillator
+  *         is automatically disabled and an interrupt is generated to inform the
+  *         software about the failure (Clock Security System Interrupt, CSSI),
+  *         allowing the MCU to perform rescue operations. The CSSI is linked to
+  *         the Cortex-M NMI (Non-Mask-able Interrupt) exception vector.
+  * @retval None
+  */
+void HAL_RCC_EnableCSS(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_CSSHSEON) ;
+}
+
+/**
+  * @brief  Disables the Clock Security System.
+  * @retval None
+  */
+void HAL_RCC_DisableCSS(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_CSSHSEON);
+}
+
+/**
+  * @brief  Returns the SYSCLK frequency
+  *
+  * @note   The system frequency computed by this function is not the real
+  *         frequency in the chip. It is calculated based on the predefined
+  *         constant and the selected clock source:
+  * @note     If SYSCLK source is CSI, function returns values based on CSI_VALUE(*)
+  * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
+  * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
+  * @note     If SYSCLK source is PLL, function returns values based on CSI_VALUE(*),
+  *           HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
+  * @note     (*) CSI_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value
+  *               4 MHz) but the real value may vary depending on the variations
+  *               in voltage and temperature.
+  * @note     (**) HSI_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value
+  *               64 MHz) but the real value may vary depending on the variations
+  *               in voltage and temperature.
+  * @note     (***) HSE_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value
+  *                25 MHz), user has to ensure that HSE_VALUE is same as the real
+  *                frequency of the crystal used. Otherwise, this function may
+  *                have wrong result.
+  *
+  * @note   The result of this function could be not correct when using fractional
+  *         value for HSE crystal.
+  *
+  * @note   This function can be used by the user application to compute the
+  *         baud rate for the communication peripherals or configure other parameters.
+  *
+  * @note   Each time SYSCLK changes, this function must be called to update the
+  *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
+  *
+  *
+  * @retval SYSCLK frequency
+  */
+uint32_t HAL_RCC_GetSysClockFreq(void)
+{
+  uint32_t pllp, pllsource, pllm, pllfracen, hsivalue;
+  float_t fracn1, pllvco;
+  uint32_t sysclockfreq;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+  case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */
+
+   if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+      {
+        sysclockfreq = (uint32_t) (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
+      }
+      else
+      {
+        sysclockfreq = (uint32_t) HSI_VALUE;
+      }
+
+    break;
+
+  case RCC_CFGR_SWS_CSI:  /* CSI used as system clock  source */
+    sysclockfreq = CSI_VALUE;
+    break;
+
+  case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
+    sysclockfreq = HSE_VALUE;
+    break;
+
+  case RCC_CFGR_SWS_PLL1:  /* PLL1 used as system clock  source */
+
+    /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
+    SYSCLK = PLL_VCO / PLLR
+    */
+    pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+    pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4)  ;
+    pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
+    fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
+
+    if (pllm != 0U)
+    {
+      switch (pllsource)
+      {
+      case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
+
+       if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+        {
+          hsivalue= (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
+          pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+        }
+        else
+        {
+          pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+        }
+        break;
+
+      case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
+        pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+        break;
+
+      case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
+        pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+        break;
+
+      default:
+        pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+        break;
+      }
+      pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
+      sysclockfreq =  (uint32_t)(float_t)(pllvco/(float_t)pllp);
+    }
+    else
+    {
+      sysclockfreq = 0U;
+    }
+    break;
+
+  default:
+    sysclockfreq = CSI_VALUE;
+    break;
+  }
+
+  return sysclockfreq;
+}
+
+
+/**
+  * @brief  Returns the HCLK frequency
+  * @note   Each time HCLK changes, this function must be called to update the
+  *         right HCLK value. Otherwise, any configuration based on this function will be incorrect.
+  *
+  * @note   The SystemD2Clock CMSIS variable is used to store System domain2 Clock Frequency
+  *         and updated within this function
+  * @retval HCLK frequency
+  */
+uint32_t HAL_RCC_GetHCLKFreq(void)
+{
+uint32_t common_system_clock;
+
+#if defined(RCC_D1CFGR_D1CPRE)
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
+#else
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU);
+#endif
+
+#if defined(RCC_D1CFGR_HPRE)
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+#else
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+#endif
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  SystemCoreClock = SystemD2Clock;
+#else
+  SystemCoreClock = common_system_clock;
+#endif /* DUAL_CORE && CORE_CM4 */
+
+  return SystemD2Clock;
+}
+
+
+/**
+  * @brief  Returns the PCLK1 frequency
+  * @note   Each time PCLK1 changes, this function must be called to update the
+  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
+  * @retval PCLK1 frequency
+  */
+uint32_t HAL_RCC_GetPCLK1Freq(void)
+{
+#if defined (RCC_D2CFGR_D2PPRE1)
+  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)>> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU));
+#else
+ /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1)>> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU));
+#endif
+}
+
+
+/**
+  * @brief  Returns the PCLK2 frequency
+  * @note   Each time PCLK2 changes, this function must be called to update the
+  *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
+  * @retval PCLK1 frequency
+  */
+uint32_t HAL_RCC_GetPCLK2Freq(void)
+{
+  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
+#if defined(RCC_D2CFGR_D2PPRE2)
+  return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)>> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU));
+#else
+  return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2)>> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU));
+#endif
+}
+
+/**
+  * @brief  Configures the RCC_OscInitStruct according to the internal
+  * RCC configuration registers.
+  * @param  RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
+  * will be configured.
+  * @retval None
+  */
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
+{
+  /* Set all possible values for the Oscillator type parameter ---------------*/
+  RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_CSI | \
+                                      RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI| RCC_OSCILLATORTYPE_HSI48;
+
+  /* Get the HSE configuration -----------------------------------------------*/
+#if defined(RCC_CR_HSEEXT)
+  if((RCC->CR &(RCC_CR_HSEBYP | RCC_CR_HSEEXT)) == RCC_CR_HSEBYP)
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
+  }
+  else if((RCC->CR &(RCC_CR_HSEBYP | RCC_CR_HSEEXT)) == (RCC_CR_HSEBYP | RCC_CR_HSEEXT))
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS_DIGITAL;
+  }
+  else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
+  }
+#else
+  if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
+  }
+  else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
+  }
+#endif /* RCC_CR_HSEEXT */
+
+   /* Get the CSI configuration -----------------------------------------------*/
+  if((RCC->CR &RCC_CR_CSION) == RCC_CR_CSION)
+  {
+    RCC_OscInitStruct->CSIState = RCC_CSI_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->CSIState = RCC_CSI_OFF;
+  }
+
+#if defined(RCC_VER_X)
+  if(HAL_GetREVID() <= REV_ID_Y)
+  {
+    RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk) >> HAL_RCC_REV_Y_CSITRIM_Pos);
+  }
+  else
+  {
+    RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
+  }
+#else
+ RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
+#endif /*RCC_VER_X*/
+
+  /* Get the HSI configuration -----------------------------------------------*/
+  if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
+  {
+    RCC_OscInitStruct->HSIState = RCC_HSI_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
+  }
+
+#if defined(RCC_VER_X)
+  if(HAL_GetREVID() <= REV_ID_Y)
+  {
+    RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk) >> HAL_RCC_REV_Y_HSITRIM_Pos);
+  }
+  else
+  {
+    RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
+  }
+#else
+    RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
+#endif /*RCC_VER_X*/
+
+  /* Get the LSE configuration -----------------------------------------------*/
+#if defined(RCC_BDCR_LSEEXT)
+  if((RCC->BDCR &(RCC_BDCR_LSEBYP|RCC_BDCR_LSEEXT)) == RCC_BDCR_LSEBYP)
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
+  }
+  else if((RCC->BDCR &(RCC_BDCR_LSEBYP|RCC_BDCR_LSEEXT)) == (RCC_BDCR_LSEBYP|RCC_BDCR_LSEEXT))
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS_DIGITAL;
+  }
+  else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
+  }
+#else
+  if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
+  }
+  else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
+  }
+#endif /* RCC_BDCR_LSEEXT */
+
+  /* Get the LSI configuration -----------------------------------------------*/
+  if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
+  {
+    RCC_OscInitStruct->LSIState = RCC_LSI_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
+  }
+
+  /* Get the HSI48 configuration ---------------------------------------------*/
+  if((RCC->CR & RCC_CR_HSI48ON) == RCC_CR_HSI48ON)
+  {
+    RCC_OscInitStruct->HSI48State = RCC_HSI48_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF;
+  }
+
+  /* Get the PLL configuration -----------------------------------------------*/
+  if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
+  {
+    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
+  }
+  RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+  RCC_OscInitStruct->PLL.PLLM = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> RCC_PLLCKSELR_DIVM1_Pos);
+  RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) >> RCC_PLL1DIVR_N1_Pos)+ 1U;
+  RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos)+ 1U;
+  RCC_OscInitStruct->PLL.PLLP = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos)+ 1U;
+  RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos)+ 1U;
+  RCC_OscInitStruct->PLL.PLLRGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL1RGE));
+  RCC_OscInitStruct->PLL.PLLVCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL1VCOSEL) >> RCC_PLLCFGR_PLL1VCOSEL_Pos);
+  RCC_OscInitStruct->PLL.PLLFRACN = (uint32_t)(((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos));
+}
+
+/**
+  * @brief  Configures the RCC_ClkInitStruct according to the internal
+  * RCC configuration registers.
+  * @param  RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
+  * will be configured.
+  * @param  pFLatency: Pointer on the Flash Latency.
+  * @retval None
+  */
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
+{
+  /* Set all possible values for the Clock type parameter --------------------*/
+  RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 |
+                                 RCC_CLOCKTYPE_PCLK2 |  RCC_CLOCKTYPE_D3PCLK1  ;
+
+  /* Get the SYSCLK configuration --------------------------------------------*/
+  RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
+
+#if defined(RCC_D1CFGR_D1CPRE)
+  /* Get the SYSCLK configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1CPRE);
+
+  /* Get the D1HCLK configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_HPRE);
+
+  /* Get the APB3 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1PPRE);
+
+  /* Get the APB1 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1);
+
+  /* Get the APB2 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2);
+
+  /* Get the APB4 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->D3CFGR & RCC_D3CFGR_D3PPRE);
+#else
+  /* Get the SYSCLK configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE);
+
+  /* Get the D1HCLK configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE);
+
+  /* Get the APB3 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE);
+
+  /* Get the APB1 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1);
+
+  /* Get the APB2 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2);
+
+  /* Get the APB4 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE);
+#endif
+
+  /* Get the Flash Wait State (Latency) configuration ------------------------*/
+  *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
+}
+
+/**
+  * @brief This function handles the RCC CSS interrupt request.
+  * @note This API should be called under the NMI_Handler().
+  * @retval None
+  */
+void HAL_RCC_NMI_IRQHandler(void)
+{
+  /* Check RCC CSSF flag  */
+  if(__HAL_RCC_GET_IT(RCC_IT_CSS))
+  {
+    /* RCC Clock Security System interrupt user callback */
+    HAL_RCC_CCSCallback();
+
+    /* Clear RCC CSS pending bit */
+    __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
+  }
+}
+
+/**
+  * @brief  RCC Clock Security System interrupt callback
+  * @retval none
+  */
+__weak void HAL_RCC_CCSCallback(void)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_RCC_CCSCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_RCC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c
new file mode 100644
index 00000000..fa08e692
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c
@@ -0,0 +1,3437 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_rcc_ex.c
+  * @author  MCD Application Team
+  * @brief   Extended RCC HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities RCC extension peripheral:
+  *           + Extended Peripheral Control functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup RCCEx  RCCEx
+  * @brief RCC HAL module driver
+  * @{
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup RCCEx_Private_defines Private Defines
+ * @{
+ */
+#define PLL2_TIMEOUT_VALUE         PLL_TIMEOUT_VALUE    /* 2 ms */
+#define PLL3_TIMEOUT_VALUE         PLL_TIMEOUT_VALUE    /* 2 ms */
+
+#define DIVIDER_P_UPDATE          0U
+#define DIVIDER_Q_UPDATE          1U
+#define DIVIDER_R_UPDATE          2U
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider);
+static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider);
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Functions Exported Functions
+  * @{
+  */
+
+/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
+ *  @brief  Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+                ##### Extended Peripheral Control functions  #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the RCC Clocks
+    frequencies.
+    [..]
+    (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
+        select the RTC clock source; in this case the Backup domain will be reset in
+        order to modify the RTC Clock source, as consequence RTC registers (including
+        the backup registers) and RCC_BDCR register are set to their reset values.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the RCC extended peripherals clocks according to the specified
+  *         parameters in the RCC_PeriphCLKInitTypeDef.
+  * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
+  *         contains the configuration information for the Extended Peripherals
+  *         clocks (SDMMC, CKPER, FMC, QSPI*, OSPI*, DSI, SPI45, SPDIF, DFSDM1, DFSDM2*, FDCAN, SWPMI, SAI23*,SAI2A*, SAI2B*, SAI1, SPI123,
+  *         USART234578, USART16 (USART16910*), RNG, HRTIM1*, I2C123, USB, CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC,
+  *         SAI4A*, SAI4B*, SPI6, RTC).
+  * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
+  *         the RTC clock source; in this case the Backup domain will be reset in
+  *         order to modify the RTC Clock source, as consequence RTC registers (including
+  *         the backup registers) are set to their reset values.
+  *
+  * (*) : Available on some STM32H7 lines only.
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  uint32_t tmpreg;
+  uint32_t tickstart;
+  HAL_StatusTypeDef ret = HAL_OK;      /* Intermediate status */
+  HAL_StatusTypeDef status = HAL_OK;   /* Final status */
+
+  /*---------------------------- SPDIFRX configuration -------------------------------*/
+
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
+  {
+
+    switch(PeriphClkInit->SpdifrxClockSelection)
+    {
+    case RCC_SPDIFRXCLKSOURCE_PLL:      /* PLL is used as clock source for SPDIFRX*/
+      /* Enable PLL1Q Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* SPDIFRX clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPDIFRXCLKSOURCE_PLL2: /* PLL2 is used as clock source for SPDIFRX*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
+
+      /* SPDIFRX clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPDIFRXCLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPDIFRX*/
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
+
+      /* SPDIFRX clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPDIFRXCLKSOURCE_HSI:
+      /* Internal OSC clock is used as source of SPDIFRX clock*/
+      /* SPDIFRX clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SPDIFRX clock*/
+      __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+  /*---------------------------- SAI1 configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
+  {
+    switch(PeriphClkInit->Sai1ClockSelection)
+    {
+    case RCC_SAI1CLKSOURCE_PLL:      /* PLL is used as clock source for SAI1*/
+      /* Enable SAI Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* SAI1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+
+      /* SAI1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI1CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI1*/
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
+
+      /* SAI1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI1CLKSOURCE_PIN:
+      /* External clock is used as source of SAI1 clock*/
+      /* SAI1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI1CLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */
+      /* SAI1 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SAI1 clock*/
+      __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+#if defined(SAI3)
+  /*---------------------------- SAI2/3 configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23)
+  {
+    switch(PeriphClkInit->Sai23ClockSelection)
+    {
+    case RCC_SAI23CLKSOURCE_PLL:      /* PLL is used as clock source for SAI2/3 */
+      /* Enable SAI Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* SAI2/3 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2/3 */
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+
+      /* SAI2/3 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI23CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2/3 */
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
+
+      /* SAI2/3 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI23CLKSOURCE_PIN:
+      /* External clock is used as source of SAI2/3 clock*/
+      /* SAI2/3 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI23CLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of SAI2/3 clock */
+      /* SAI2/3 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SAI2/3 clock*/
+      __HAL_RCC_SAI23_CONFIG(PeriphClkInit->Sai23ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+#endif /* SAI3 */
+
+#if defined(RCC_CDCCIP1R_SAI2ASEL)
+  /*---------------------------- SAI2A configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2A) == RCC_PERIPHCLK_SAI2A)
+  {
+    switch(PeriphClkInit->Sai2AClockSelection)
+    {
+    case RCC_SAI2ACLKSOURCE_PLL:      /* PLL is used as clock source for SAI2A */
+      /* Enable SAI2A Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* SAI2A clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI2ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2A */
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+
+      /* SAI2A clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI2ACLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2A */
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
+
+      /* SAI2A clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI2ACLKSOURCE_PIN:
+      /* External clock is used as source of SAI2A clock*/
+      /* SAI2A clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI2ACLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of SAI2A clock */
+      /* SAI2A clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI2ACLKSOURCE_SPDIF:
+      /* SPDIF clock is used as source of SAI2A clock */
+      /* SAI2A clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SAI2A clock*/
+      __HAL_RCC_SAI2A_CONFIG(PeriphClkInit->Sai2AClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+#endif  /*SAI2A*/
+
+#if defined(RCC_CDCCIP1R_SAI2BSEL)
+
+  /*---------------------------- SAI2B configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2B) == RCC_PERIPHCLK_SAI2B)
+  {
+    switch(PeriphClkInit->Sai2BClockSelection)
+    {
+    case RCC_SAI2BCLKSOURCE_PLL:      /* PLL is used as clock source for SAI2B */
+      /* Enable SAI Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* SAI2B clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI2BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2B */
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+
+      /* SAI2B clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI2BCLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2B */
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
+
+      /* SAI2B clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI2BCLKSOURCE_PIN:
+      /* External clock is used as source of SAI2B clock*/
+      /* SAI2B clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI2BCLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of SAI2B clock */
+      /* SAI2B clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI2BCLKSOURCE_SPDIF:
+      /* SPDIF clock is used as source of SAI2B clock */
+      /* SAI2B clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SAI2B clock*/
+      __HAL_RCC_SAI2B_CONFIG(PeriphClkInit->Sai2BClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+#endif  /*SAI2B*/
+
+#if defined(SAI4)
+  /*---------------------------- SAI4A configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A)
+  {
+    switch(PeriphClkInit->Sai4AClockSelection)
+    {
+    case RCC_SAI4ACLKSOURCE_PLL:      /* PLL is used as clock source for SAI2*/
+      /* Enable SAI Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* SAI1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI4ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+
+      /* SAI2 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI4ACLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2*/
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
+
+      /* SAI1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI4ACLKSOURCE_PIN:
+      /* External clock is used as source of SAI2 clock*/
+      /* SAI2 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI4ACLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */
+      /* SAI1 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SAI4A clock*/
+      __HAL_RCC_SAI4A_CONFIG(PeriphClkInit->Sai4AClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+  /*---------------------------- SAI4B configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B)
+  {
+    switch(PeriphClkInit->Sai4BClockSelection)
+    {
+    case RCC_SAI4BCLKSOURCE_PLL:      /* PLL is used as clock source for SAI2*/
+      /* Enable SAI Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* SAI1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI4BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+
+      /* SAI2 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI4BCLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2*/
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
+
+      /* SAI1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI4BCLKSOURCE_PIN:
+      /* External clock is used as source of SAI2 clock*/
+      /* SAI2 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI4BCLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */
+      /* SAI1 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SAI4B clock*/
+      __HAL_RCC_SAI4B_CONFIG(PeriphClkInit->Sai4BClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+#endif  /*SAI4*/
+
+#if defined(QUADSPI)
+  /*---------------------------- QSPI configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI)
+  {
+    switch(PeriphClkInit->QspiClockSelection)
+    {
+    case RCC_QSPICLKSOURCE_PLL:      /* PLL is used as clock source for QSPI*/
+      /* Enable QSPI Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* QSPI clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_QSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for QSPI*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
+
+      /* QSPI clock source configuration done later after clock selection check */
+      break;
+
+
+    case RCC_QSPICLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of QSPI clock */
+      /* QSPI clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_QSPICLKSOURCE_D1HCLK:
+      /* Domain1 HCLK  clock selected as QSPI kernel peripheral clock */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of QSPI clock*/
+      __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+#endif  /*QUADSPI*/
+
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+  /*---------------------------- OCTOSPI configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI)
+  {
+    switch(PeriphClkInit->OspiClockSelection)
+    {
+    case RCC_OSPICLKSOURCE_PLL:      /* PLL is used as clock source for OSPI*/
+      /* Enable OSPI Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* OSPI clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_OSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for OSPI*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
+
+      /* OSPI clock source configuration done later after clock selection check */
+      break;
+
+
+    case RCC_OSPICLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of OSPI clock */
+      /* OSPI clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_OSPICLKSOURCE_HCLK:
+      /* HCLK clock selected as OSPI kernel peripheral clock */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of OSPI clock*/
+      __HAL_RCC_OSPI_CONFIG(PeriphClkInit->OspiClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+#endif  /*OCTOSPI*/
+
+  /*---------------------------- SPI1/2/3 configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123)
+  {
+    switch(PeriphClkInit->Spi123ClockSelection)
+    {
+    case RCC_SPI123CLKSOURCE_PLL:      /* PLL is used as clock source for SPI1/2/3 */
+      /* Enable SPI Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* SPI1/2/3 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI1/2/3 */
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+
+      /* SPI1/2/3 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI123CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPI1/2/3 */
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
+
+      /* SPI1/2/3 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI123CLKSOURCE_PIN:
+      /* External clock is used as source of SPI1/2/3 clock*/
+      /* SPI1/2/3 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI123CLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of SPI1/2/3 clock */
+      /* SPI1/2/3 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SPI1/2/3 clock*/
+      __HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+  /*---------------------------- SPI4/5 configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45)
+  {
+    switch(PeriphClkInit->Spi45ClockSelection)
+    {
+    case RCC_SPI45CLKSOURCE_PCLK1:      /* CD/D2 PCLK1 as clock source for SPI4/5 */
+      /* SPI4/5 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI4/5 */
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
+
+      /* SPI4/5 clock source configuration done later after clock selection check */
+      break;
+    case RCC_SPI45CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPI4/5 */
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
+      /* SPI4/5 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI45CLKSOURCE_HSI:
+      /* HSI oscillator clock is used as source of SPI4/5 clock*/
+      /* SPI4/5 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI45CLKSOURCE_CSI:
+      /*  CSI oscillator clock is used as source of SPI4/5 clock */
+      /* SPI4/5 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI45CLKSOURCE_HSE:
+      /* HSE,  oscillator is used as source of SPI4/5 clock */
+      /* SPI4/5 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SPI4/5 clock*/
+      __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+  /*---------------------------- SPI6 configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6)
+  {
+    switch(PeriphClkInit->Spi6ClockSelection)
+    {
+    case RCC_SPI6CLKSOURCE_PCLK4:      /* SRD/D3 PCLK1 (PCLK4) as clock source for SPI6*/
+      /* SPI6 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI6*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
+
+      /* SPI6 clock source configuration done later after clock selection check */
+      break;
+    case RCC_SPI6CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPI6*/
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
+      /* SPI6 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI6CLKSOURCE_HSI:
+      /* HSI oscillator clock is used as source of SPI6 clock*/
+      /* SPI6 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI6CLKSOURCE_CSI:
+      /*  CSI oscillator clock is used as source of SPI6 clock */
+      /* SPI6 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI6CLKSOURCE_HSE:
+      /* HSE,  oscillator is used as source of SPI6 clock */
+      /* SPI6 clock source configuration done later after clock selection check */
+      break;
+#if defined(RCC_SPI6CLKSOURCE_PIN)
+    case RCC_SPI6CLKSOURCE_PIN:
+      /* 2S_CKIN is used as source of SPI6 clock */
+      /* SPI6 clock source configuration done later after clock selection check */
+      break;
+#endif
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SPI6 clock*/
+      __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+#if defined(DSI)
+  /*---------------------------- DSI configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI)
+  {
+    switch(PeriphClkInit->DsiClockSelection)
+    {
+
+    case RCC_DSICLKSOURCE_PLL2: /* PLL2 is used as clock source for DSI*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
+
+      /* DSI clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_DSICLKSOURCE_PHY:
+      /* PHY is used as clock source for DSI*/
+      /* DSI clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of DSI clock*/
+      __HAL_RCC_DSI_CONFIG(PeriphClkInit->DsiClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+#endif /*DSI*/
+
+#if defined(FDCAN1) || defined(FDCAN2)
+  /*---------------------------- FDCAN configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
+  {
+    switch(PeriphClkInit->FdcanClockSelection)
+    {
+    case RCC_FDCANCLKSOURCE_PLL:      /* PLL is used as clock source for FDCAN*/
+      /* Enable FDCAN Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* FDCAN clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
+
+      /* FDCAN clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_FDCANCLKSOURCE_HSE:
+      /* HSE is used as clock source for FDCAN*/
+      /* FDCAN clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of FDCAN clock*/
+      __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+#endif /*FDCAN1 || FDCAN2*/
+
+  /*---------------------------- FMC configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC)
+  {
+    switch(PeriphClkInit->FmcClockSelection)
+    {
+    case RCC_FMCCLKSOURCE_PLL:      /* PLL is used as clock source for FMC*/
+      /* Enable FMC Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* FMC clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_FMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for FMC*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
+
+      /* FMC clock source configuration done later after clock selection check */
+      break;
+
+
+    case RCC_FMCCLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of FMC clock */
+      /* FMC clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_FMCCLKSOURCE_HCLK:
+      /* D1/CD HCLK  clock selected as FMC kernel peripheral clock */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of FMC clock*/
+      __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+  /*---------------------------- RTC configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
+  {
+    /* check for RTC Parameters used to output RTCCLK */
+    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+
+    /* Enable write access to Backup domain */
+    SET_BIT(PWR->CR1, PWR_CR1_DBP);
+
+    /* Wait for Backup domain Write protection disable */
+    tickstart = HAL_GetTick();
+
+    while((PWR->CR1 & PWR_CR1_DBP) == 0U)
+    {
+      if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+      {
+        ret = HAL_TIMEOUT;
+        break;
+      }
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Reset the Backup domain only if the RTC Clock source selection is modified */
+      if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
+      {
+        /* Store the content of BDCR register before the reset of Backup Domain */
+        tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+        /* RTC Clock selection can be changed only if the Backup Domain is reset */
+        __HAL_RCC_BACKUPRESET_FORCE();
+        __HAL_RCC_BACKUPRESET_RELEASE();
+        /* Restore the Content of BDCR register */
+        RCC->BDCR = tmpreg;
+      }
+
+      /* If LSE is selected as RTC clock source (and enabled prior to Backup Domain reset), wait for LSE reactivation */
+      if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
+      {
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till LSE is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
+        {
+          if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
+          {
+            ret = HAL_TIMEOUT;
+            break;
+          }
+        }
+      }
+
+      if(ret == HAL_OK)
+      {
+        __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+      }
+      else
+      {
+        /* set overall return value */
+        status = ret;
+      }
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+
+  /*-------------------------- USART1/6 configuration --------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16)
+  {
+    switch(PeriphClkInit->Usart16ClockSelection)
+    {
+    case RCC_USART16CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for USART1/6 */
+      /* USART1/6 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USART16CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART1/6 */
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
+      /* USART1/6 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USART16CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1/6 */
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
+      /* USART1/6 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USART16CLKSOURCE_HSI:
+      /* HSI oscillator clock is used as source of USART1/6 clock */
+      /* USART1/6 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USART16CLKSOURCE_CSI:
+      /* CSI oscillator clock is used as source of USART1/6 clock */
+      /* USART1/6 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USART16CLKSOURCE_LSE:
+      /* LSE,  oscillator is used as source of USART1/6 clock */
+      /* USART1/6 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of USART1/6 clock */
+      __HAL_RCC_USART16_CONFIG(PeriphClkInit->Usart16ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+  /*-------------------------- USART2/3/4/5/7/8 Configuration --------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578)
+  {
+    switch(PeriphClkInit->Usart234578ClockSelection)
+    {
+    case RCC_USART234578CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for USART2/3/4/5/7/8 */
+      /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USART234578CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART2/3/4/5/7/8 */
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
+      /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USART234578CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART2/3/4/5/7/8 */
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
+      /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USART234578CLKSOURCE_HSI:
+      /* HSI oscillator clock is used as source of USART2/3/4/5/7/8 clock */
+      /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USART234578CLKSOURCE_CSI:
+      /* CSI oscillator clock is used as source of USART2/3/4/5/7/8 clock */
+      /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USART234578CLKSOURCE_LSE:
+      /* LSE,  oscillator is used as source of USART2/3/4/5/7/8 clock */
+      /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of USART2/3/4/5/7/8 clock */
+      __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+  /*-------------------------- LPUART1 Configuration -------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
+  {
+    switch(PeriphClkInit->Lpuart1ClockSelection)
+    {
+    case RCC_LPUART1CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPUART1 */
+      /* LPUART1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPUART1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPUART1 */
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
+      /* LPUART1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPUART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPUART1 */
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
+      /* LPUART1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPUART1CLKSOURCE_HSI:
+      /* HSI oscillator clock is used as source of LPUART1 clock */
+      /* LPUART1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPUART1CLKSOURCE_CSI:
+      /* CSI oscillator clock is used as source of LPUART1 clock */
+      /* LPUART1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPUART1CLKSOURCE_LSE:
+      /* LSE,  oscillator is used as source of LPUART1 clock */
+      /* LPUART1 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of LPUART1 clock */
+      __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+  /*---------------------------- LPTIM1 configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
+  {
+    switch(PeriphClkInit->Lptim1ClockSelection)
+    {
+    case RCC_LPTIM1CLKSOURCE_PCLK1:      /* CD/D2 PCLK1 as clock source for LPTIM1*/
+      /* LPTIM1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM1*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+
+      /* LPTIM1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM1CLKSOURCE_PLL3:  /* PLL3 is used as clock source for LPTIM1*/
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
+
+      /* LPTIM1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM1CLKSOURCE_LSE:
+      /* External low speed OSC clock is used as source of LPTIM1 clock*/
+      /* LPTIM1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM1CLKSOURCE_LSI:
+      /* Internal  low speed OSC clock is used  as source of LPTIM1 clock*/
+      /* LPTIM1 clock source configuration done later after clock selection check */
+      break;
+    case RCC_LPTIM1CLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of LPTIM1 clock */
+      /* LPTIM1 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of LPTIM1 clock*/
+      __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+  /*---------------------------- LPTIM2 configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2)
+  {
+    switch(PeriphClkInit->Lptim2ClockSelection)
+    {
+    case RCC_LPTIM2CLKSOURCE_PCLK4:      /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM2*/
+      /* LPTIM2 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM2CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM2*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+
+      /* LPTIM2 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM2CLKSOURCE_PLL3:  /* PLL3 is used as clock source for LPTIM2*/
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
+
+      /* LPTIM2 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM2CLKSOURCE_LSE:
+      /* External low speed OSC clock is used as source of LPTIM2 clock*/
+      /* LPTIM2 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM2CLKSOURCE_LSI:
+      /* Internal  low speed OSC clock is used  as source of LPTIM2 clock*/
+      /* LPTIM2 clock source configuration done later after clock selection check */
+      break;
+    case RCC_LPTIM2CLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */
+      /* LPTIM2 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of LPTIM2 clock*/
+      __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+  /*---------------------------- LPTIM345 configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345)
+  {
+    switch(PeriphClkInit->Lptim345ClockSelection)
+    {
+
+    case RCC_LPTIM345CLKSOURCE_PCLK4:      /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM3/4/5 */
+      /* LPTIM3/4/5 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM345CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM3/4/5 */
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+
+      /* LPTIM3/4/5 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM345CLKSOURCE_PLL3:  /* PLL3 is used as clock source for LPTIM3/4/5 */
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
+
+      /* LPTIM3/4/5 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM345CLKSOURCE_LSE:
+      /* External low speed OSC clock is used as source of LPTIM3/4/5 clock */
+      /* LPTIM3/4/5 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM345CLKSOURCE_LSI:
+      /* Internal  low speed OSC clock is used  as source of LPTIM3/4/5 clock */
+      /* LPTIM3/4/5 clock source configuration done later after clock selection check */
+      break;
+    case RCC_LPTIM345CLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of LPTIM3/4/5 clock */
+      /* LPTIM3/4/5 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of LPTIM3/4/5 clock */
+      __HAL_RCC_LPTIM345_CONFIG(PeriphClkInit->Lptim345ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+  /*------------------------------ I2C1/2/3 Configuration ------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2C123CLKSOURCE(PeriphClkInit->I2c123ClockSelection));
+
+    if ((PeriphClkInit->I2c123ClockSelection )== RCC_I2C123CLKSOURCE_PLL3 )
+    {
+        if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!= HAL_OK)
+        {
+          status = HAL_ERROR;
+        }
+    }
+
+      __HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection);
+
+  }
+
+  /*------------------------------ I2C4 Configuration ------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
+
+    if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3 )
+    {
+      if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!= HAL_OK)
+      {
+        status = HAL_ERROR;
+      }
+    }
+
+      __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
+
+  }
+
+  /*---------------------------- ADC configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
+  {
+    switch(PeriphClkInit->AdcClockSelection)
+    {
+
+    case RCC_ADCCLKSOURCE_PLL2: /* PLL2 is used as clock source for ADC*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+
+      /* ADC clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_ADCCLKSOURCE_PLL3:  /* PLL3 is used as clock source for ADC*/
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
+
+      /* ADC clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_ADCCLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of ADC clock */
+      /* ADC clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of ADC clock*/
+      __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+  /*------------------------------ USB Configuration -------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
+  {
+
+    switch(PeriphClkInit->UsbClockSelection)
+    {
+    case RCC_USBCLKSOURCE_PLL:      /* PLL is used as clock source for USB*/
+      /* Enable USB Clock output generated form System USB . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* USB clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USBCLKSOURCE_PLL3: /* PLL3 is used as clock source for USB*/
+
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
+
+      /* USB clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USBCLKSOURCE_HSI48:
+      /* HSI48 oscillator is used as source of USB clock */
+      /* USB clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of USB clock*/
+      __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+
+  }
+
+  /*------------------------------------- SDMMC Configuration ------------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SDMMC(PeriphClkInit->SdmmcClockSelection));
+
+    switch(PeriphClkInit->SdmmcClockSelection)
+    {
+    case RCC_SDMMCCLKSOURCE_PLL:      /* PLL is used as clock source for SDMMC*/
+      /* Enable SDMMC Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* SDMMC clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for SDMMC*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
+
+      /* SDMMC clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SDMMC clock*/
+      __HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+#if defined(LTDC)
+  /*-------------------------------------- LTDC Configuration -----------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
+  {
+    if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!=HAL_OK)
+    {
+      status=HAL_ERROR;
+    }
+  }
+#endif /* LTDC */
+
+  /*------------------------------ RNG Configuration -------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG)
+  {
+
+    switch(PeriphClkInit->RngClockSelection)
+    {
+    case RCC_RNGCLKSOURCE_PLL:     /* PLL is used as clock source for RNG*/
+      /* Enable RNG Clock output generated form System RNG . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* RNG clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_RNGCLKSOURCE_LSE: /* LSE is used as clock source for RNG*/
+
+      /* RNG clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_RNGCLKSOURCE_LSI: /* LSI is used as clock source for RNG*/
+
+      /* RNG clock source configuration done later after clock selection check */
+      break;
+    case RCC_RNGCLKSOURCE_HSI48:
+      /* HSI48 oscillator is used as source of RNG clock */
+      /* RNG clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of RNG clock*/
+      __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+
+  }
+
+  /*------------------------------ SWPMI1 Configuration ------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection));
+
+    /* Configure the SWPMI1 interface clock source */
+    __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);
+  }
+#if defined(HRTIM)
+  /*------------------------------ HRTIM1 clock Configuration ----------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection));
+
+    /* Configure the HRTIM1 clock source */
+    __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection);
+  }
+#endif  /*HRTIM*/
+  /*------------------------------ DFSDM1 Configuration ------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
+
+    /* Configure the DFSDM1 interface clock source */
+    __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
+  }
+
+#if defined(DFSDM2_BASE)
+  /*------------------------------ DFSDM2 Configuration ------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2) == RCC_PERIPHCLK_DFSDM2)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_DFSDM2CLKSOURCE(PeriphClkInit->Dfsdm2ClockSelection));
+
+    /* Configure the DFSDM2 interface clock source */
+    __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection);
+  }
+#endif  /* DFSDM2 */
+
+  /*------------------------------------ TIM configuration --------------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
+
+    /* Configure Timer Prescaler */
+    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
+  }
+
+  /*------------------------------------ CKPER configuration --------------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_CLKPSOURCE(PeriphClkInit->CkperClockSelection));
+
+    /* Configure the CKPER clock source */
+    __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection);
+  }
+
+  if (status == HAL_OK)
+  {
+    return HAL_OK;
+  }
+  return HAL_ERROR;
+}
+
+/**
+  * @brief  Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
+  * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
+  *         returns the configuration information for the Extended Peripherals clocks :
+  *         (SDMMC, CKPER, FMC, QSPI*, OSPI*, DSI*, SPI45, SPDIF, DFSDM1, DFSDM2*, FDCAN, SWPMI, SAI23*, SAI1, SPI123,
+  *         USART234578, USART16, RNG, HRTIM1*, I2C123, USB, CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC.
+  *         SAI4A*, SAI4B*, SPI6, RTC, TIM).
+  * @retval None
+  *
+  *   (*) : Available on some STM32H7 lines only.
+  */
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  /* Set all possible values for the extended clock type parameter------------*/
+  PeriphClkInit->PeriphClockSelection =
+                 RCC_PERIPHCLK_USART16 | RCC_PERIPHCLK_USART234578 | RCC_PERIPHCLK_LPUART1 |
+                 RCC_PERIPHCLK_I2C4    | RCC_PERIPHCLK_LPTIM1      | RCC_PERIPHCLK_LPTIM2  | RCC_PERIPHCLK_LPTIM345 |
+                 RCC_PERIPHCLK_SAI1    | RCC_PERIPHCLK_SPI123      | RCC_PERIPHCLK_SPI45   | RCC_PERIPHCLK_SPI6     |
+	         RCC_PERIPHCLK_FDCAN   | RCC_PERIPHCLK_SDMMC       | RCC_PERIPHCLK_RNG     | RCC_PERIPHCLK_USB      |
+	         RCC_PERIPHCLK_ADC     | RCC_PERIPHCLK_SWPMI1      | RCC_PERIPHCLK_DFSDM1  | RCC_PERIPHCLK_RTC      |
+	         RCC_PERIPHCLK_CEC     | RCC_PERIPHCLK_FMC         | RCC_PERIPHCLK_SPDIFRX | RCC_PERIPHCLK_TIM      |
+	         RCC_PERIPHCLK_CKPER;
+
+PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C123;
+#if defined(RCC_CDCCIP1R_SAI2ASEL)
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI2A;
+#endif /* RCC_CDCCIP1R_SAI2ASEL */
+#if defined(RCC_CDCCIP1R_SAI2BSEL)
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI2B;
+#endif /* RCC_CDCCIP1R_SAI2BSEL */
+#if defined(SAI3)
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI23;
+#endif /* SAI3 */
+#if defined(SAI4)
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI4A;
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI4B;
+#endif /* SAI4 */
+#if defined(DFSDM2_BASE)
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_DFSDM2;
+#endif /* DFSDM2 */
+#if defined(QUADSPI)
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_QSPI;
+#endif /* QUADSPI */
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_OSPI;
+#endif /* OCTOSPI1 || OCTOSPI2 */
+#if defined(HRTIM)
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_HRTIM1;
+#endif /* HRTIM */
+#if defined(LTDC)
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LTDC;
+#endif /* LTDC */
+#if defined(DSI)
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_DSI;
+#endif /* DSI */
+
+  /* Get the PLL3 Clock configuration -----------------------------------------------*/
+  PeriphClkInit->PLL3.PLL3M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3)>> RCC_PLLCKSELR_DIVM3_Pos);
+  PeriphClkInit->PLL3.PLL3N = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_N3) >> RCC_PLL3DIVR_N3_Pos)+ 1U;
+  PeriphClkInit->PLL3.PLL3R = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> RCC_PLL3DIVR_R3_Pos)+ 1U;
+  PeriphClkInit->PLL3.PLL3P = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> RCC_PLL3DIVR_P3_Pos)+ 1U;
+  PeriphClkInit->PLL3.PLL3Q = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> RCC_PLL3DIVR_Q3_Pos)+ 1U;
+  PeriphClkInit->PLL3.PLL3RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3RGE) >> RCC_PLLCFGR_PLL3RGE_Pos);
+  PeriphClkInit->PLL3.PLL3VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3VCOSEL) >> RCC_PLLCFGR_PLL3VCOSEL_Pos);
+
+  /* Get the PLL2 Clock configuration -----------------------------------------------*/
+  PeriphClkInit->PLL2.PLL2M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2)>> RCC_PLLCKSELR_DIVM2_Pos);
+  PeriphClkInit->PLL2.PLL2N = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_N2) >> RCC_PLL2DIVR_N2_Pos)+ 1U;
+  PeriphClkInit->PLL2.PLL2R = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> RCC_PLL2DIVR_R2_Pos)+ 1U;
+  PeriphClkInit->PLL2.PLL2P = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> RCC_PLL2DIVR_P2_Pos)+ 1U;
+  PeriphClkInit->PLL2.PLL2Q = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> RCC_PLL2DIVR_Q2_Pos)+ 1U;
+  PeriphClkInit->PLL2.PLL2RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2RGE) >> RCC_PLLCFGR_PLL2RGE_Pos);
+  PeriphClkInit->PLL2.PLL2VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2VCOSEL) >> RCC_PLLCFGR_PLL2VCOSEL_Pos);
+
+  /* Get the USART1 configuration --------------------------------------------*/
+  PeriphClkInit->Usart16ClockSelection      = __HAL_RCC_GET_USART16_SOURCE();
+  /* Get the USART2/3/4/5/7/8 clock source -----------------------------------*/
+  PeriphClkInit->Usart234578ClockSelection  = __HAL_RCC_GET_USART234578_SOURCE();
+  /* Get the LPUART1 clock source --------------------------------------------*/
+  PeriphClkInit->Lpuart1ClockSelection      = __HAL_RCC_GET_LPUART1_SOURCE();
+  /* Get the I2C1/2/3 clock source -------------------------------------------*/
+  PeriphClkInit->I2c123ClockSelection       = __HAL_RCC_GET_I2C1_SOURCE();
+  /* Get the LPTIM1 clock source ---------------------------------------------*/
+  PeriphClkInit->Lptim1ClockSelection       = __HAL_RCC_GET_LPTIM1_SOURCE();
+  /* Get the LPTIM2 clock source ---------------------------------------------*/
+  PeriphClkInit->Lptim2ClockSelection       = __HAL_RCC_GET_LPTIM2_SOURCE();
+  /* Get the LPTIM3/4/5 clock source -----------------------------------------*/
+  PeriphClkInit->Lptim345ClockSelection     = __HAL_RCC_GET_LPTIM345_SOURCE();
+  /* Get the SAI1 clock source -----------------------------------------------*/
+  PeriphClkInit->Sai1ClockSelection         = __HAL_RCC_GET_SAI1_SOURCE();
+#if defined(SAI3)
+  /* Get the SAI2/3 clock source ---------------------------------------------*/
+  PeriphClkInit->Sai23ClockSelection        = __HAL_RCC_GET_SAI23_SOURCE();
+#endif  /*SAI3*/
+#if defined(RCC_CDCCIP1R_SAI2ASEL_0)
+  /* Get the SAI2A clock source ---------------------------------------------*/
+  PeriphClkInit->Sai2AClockSelection        = __HAL_RCC_GET_SAI2A_SOURCE();
+#endif  /*SAI2A*/
+#if defined(RCC_CDCCIP1R_SAI2BSEL_0)
+  /* Get the SAI2B clock source ---------------------------------------------*/
+  PeriphClkInit->Sai2BClockSelection        = __HAL_RCC_GET_SAI2B_SOURCE();
+#endif  /*SAI2B*/
+#if defined(SAI4)
+  /* Get the SAI4A clock source ----------------------------------------------*/
+  PeriphClkInit->Sai4AClockSelection        = __HAL_RCC_GET_SAI4A_SOURCE();
+  /* Get the SAI4B clock source ----------------------------------------------*/
+  PeriphClkInit->Sai4BClockSelection        = __HAL_RCC_GET_SAI4B_SOURCE();
+#endif  /*SAI4*/
+  /* Get the RTC clock source ------------------------------------------------*/
+  PeriphClkInit->RTCClockSelection          = __HAL_RCC_GET_RTC_SOURCE();
+  /* Get the USB clock source ------------------------------------------------*/
+  PeriphClkInit->UsbClockSelection          = __HAL_RCC_GET_USB_SOURCE();
+  /* Get the SDMMC clock source ----------------------------------------------*/
+  PeriphClkInit->SdmmcClockSelection        = __HAL_RCC_GET_SDMMC_SOURCE();
+  /* Get the RNG clock source ------------------------------------------------*/
+  PeriphClkInit->RngClockSelection          = __HAL_RCC_GET_RNG_SOURCE();
+#if defined(HRTIM1)
+  /* Get the HRTIM1 clock source ---------------------------------------------*/
+  PeriphClkInit->Hrtim1ClockSelection       = __HAL_RCC_GET_HRTIM1_SOURCE();
+#endif /* HRTIM1 */
+  /* Get the ADC clock source ------------------------------------------------*/
+  PeriphClkInit->AdcClockSelection          = __HAL_RCC_GET_ADC_SOURCE();
+  /* Get the SWPMI1 clock source ---------------------------------------------*/
+  PeriphClkInit->Swpmi1ClockSelection       = __HAL_RCC_GET_SWPMI1_SOURCE();
+  /* Get the DFSDM1 clock source ---------------------------------------------*/
+  PeriphClkInit->Dfsdm1ClockSelection       = __HAL_RCC_GET_DFSDM1_SOURCE();
+#if defined(DFSDM2_BASE)
+  /* Get the DFSDM2 clock source ---------------------------------------------*/
+  PeriphClkInit->Dfsdm2ClockSelection       = __HAL_RCC_GET_DFSDM2_SOURCE();
+#endif /* DFSDM2 */
+  /* Get the SPDIFRX clock source --------------------------------------------*/
+  PeriphClkInit->SpdifrxClockSelection      = __HAL_RCC_GET_SPDIFRX_SOURCE();
+  /* Get the SPI1/2/3 clock source -------------------------------------------*/
+  PeriphClkInit->Spi123ClockSelection       = __HAL_RCC_GET_SPI123_SOURCE();
+  /* Get the SPI4/5 clock source ---------------------------------------------*/
+  PeriphClkInit->Spi45ClockSelection        = __HAL_RCC_GET_SPI45_SOURCE();
+  /* Get the SPI6 clock source -----------------------------------------------*/
+  PeriphClkInit->Spi6ClockSelection         = __HAL_RCC_GET_SPI6_SOURCE();
+  /* Get the FDCAN clock source ----------------------------------------------*/
+  PeriphClkInit->FdcanClockSelection        = __HAL_RCC_GET_FDCAN_SOURCE();
+  /* Get the CEC clock source ------------------------------------------------*/
+  PeriphClkInit->CecClockSelection          = __HAL_RCC_GET_CEC_SOURCE();
+  /* Get the FMC clock source ------------------------------------------------*/
+  PeriphClkInit->FmcClockSelection          = __HAL_RCC_GET_FMC_SOURCE();
+#if defined(QUADSPI)
+  /* Get the QSPI clock source -----------------------------------------------*/
+  PeriphClkInit->QspiClockSelection         = __HAL_RCC_GET_QSPI_SOURCE();
+#endif /* QUADSPI */
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+  /* Get the OSPI clock source -----------------------------------------------*/
+  PeriphClkInit->OspiClockSelection         = __HAL_RCC_GET_OSPI_SOURCE();
+#endif /* OCTOSPI1 || OCTOSPI2 */
+
+#if defined(DSI)
+  /* Get the DSI clock source ------------------------------------------------*/
+  PeriphClkInit->DsiClockSelection          = __HAL_RCC_GET_DSI_SOURCE();
+#endif /*DSI*/
+
+  /* Get the CKPER clock source ----------------------------------------------*/
+  PeriphClkInit->CkperClockSelection        = __HAL_RCC_GET_CLKP_SOURCE();
+
+  /* Get the TIM Prescaler configuration -------------------------------------*/
+  if ((RCC->CFGR & RCC_CFGR_TIMPRE) == 0U)
+  {
+    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
+  }
+  else
+  {
+    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
+  }
+}
+
+/**
+  * @brief  Return the peripheral clock frequency for a given peripheral(SAI..)
+  * @note   Return 0 if peripheral clock identifier not managed by this API
+  * @param  PeriphClk: Peripheral clock identifier
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PERIPHCLK_SAI1  : SAI1 peripheral clock
+  *            @arg RCC_PERIPHCLK_SAI23 : SAI2/3  peripheral clock (*)
+  *            @arg RCC_PERIPHCLK_SAI2A : SAI2A peripheral clock (*)
+  *            @arg RCC_PERIPHCLK_SAI2B : SAI2B peripheral clock (*)
+  *            @arg RCC_PERIPHCLK_SAI4A : SAI4A peripheral clock (*)
+  *            @arg RCC_PERIPHCLK_SAI4B : SAI4B peripheral clock (*)
+  *            @arg RCC_PERIPHCLK_SPI123: SPI1/2/3 peripheral clock
+  *            @arg RCC_PERIPHCLK_ADC   : ADC peripheral clock
+  *            @arg RCC_PERIPHCLK_SDMMC : SDMMC peripheral clock
+  *            @arg RCC_PERIPHCLK_SPI6  : SPI6 peripheral clock
+  * @retval Frequency in KHz
+  *
+  *  (*) : Available on some STM32H7 lines only.
+  */
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
+{
+  PLL1_ClocksTypeDef pll1_clocks;
+  PLL2_ClocksTypeDef pll2_clocks;
+  PLL3_ClocksTypeDef pll3_clocks;
+
+  /* This variable is used to store the SAI clock frequency (value in Hz) */
+  uint32_t frequency;
+  /* This variable is used to store the SAI and CKP clock source */
+  uint32_t saiclocksource;
+  uint32_t ckpclocksource;
+  uint32_t srcclk;
+
+  if (PeriphClk == RCC_PERIPHCLK_SAI1)
+    {
+
+      saiclocksource= __HAL_RCC_GET_SAI1_SOURCE();
+
+      switch (saiclocksource)
+      {
+      case RCC_SAI1CLKSOURCE_PLL: /* PLL1 is the clock source for SAI1 */
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+          break;
+        }
+      case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI1 */
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_P_Frequency;
+          break;
+        }
+
+      case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI1 */
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+          frequency = pll3_clocks.PLL3_P_Frequency;
+          break;
+        }
+
+      case RCC_SAI1CLKSOURCE_CLKP: /* CKPER is the clock source for SAI1*/
+        {
+
+          ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
+
+          if(ckpclocksource== RCC_CLKPSOURCE_HSI)
+          {
+            /* In Case the CKPER Source is HSI */
+            frequency = HSI_VALUE;
+          }
+
+          else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
+          {
+            /* In Case the CKPER Source is CSI */
+            frequency = CSI_VALUE;
+          }
+
+          else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
+          {
+            /* In Case the CKPER Source is HSE */
+            frequency = HSE_VALUE;
+          }
+
+          else
+          {
+            /* In Case the CKPER is disabled*/
+            frequency = 0;
+          }
+
+          break;
+        }
+
+      case (RCC_SAI1CLKSOURCE_PIN): /* External clock is the clock source for SAI1 */
+        {
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+      default :
+        {
+          frequency = 0;
+          break;
+        }
+      }
+    }
+
+#if defined(SAI3)
+  else if (PeriphClk == RCC_PERIPHCLK_SAI23)
+    {
+
+      saiclocksource= __HAL_RCC_GET_SAI23_SOURCE();
+
+      switch (saiclocksource)
+      {
+      case 0: /* PLL1 is the clock source for SAI2/3 */
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+          break;
+        }
+      case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI2/3 */
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_P_Frequency;
+          break;
+        }
+
+      case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI2/3 */
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+          frequency = pll3_clocks.PLL3_P_Frequency;
+          break;
+        }
+
+      case RCC_SAI23CLKSOURCE_CLKP: /* CKPER is the clock source for SAI2/3 */
+        {
+
+          ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
+
+          if(ckpclocksource== RCC_CLKPSOURCE_HSI)
+          {
+            /* In Case the CKPER Source is HSI */
+            frequency = HSI_VALUE;
+          }
+
+          else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
+          {
+            /* In Case the CKPER Source is CSI */
+            frequency = CSI_VALUE;
+          }
+
+          else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
+          {
+            /* In Case the CKPER Source is HSE */
+            frequency = HSE_VALUE;
+          }
+
+          else
+          {
+            /* In Case the CKPER is disabled*/
+            frequency = 0;
+          }
+
+          break;
+        }
+
+      case (RCC_SAI23CLKSOURCE_PIN): /* External clock is the clock source for SAI2/3 */
+        {
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+      default :
+        {
+          frequency = 0;
+          break;
+        }
+      }
+    }
+#endif /* SAI3 */
+
+#if  defined(RCC_CDCCIP1R_SAI2ASEL)
+
+    else if (PeriphClk == RCC_PERIPHCLK_SAI2A)
+    {
+      saiclocksource= __HAL_RCC_GET_SAI2A_SOURCE();
+
+      switch (saiclocksource)
+      {
+      case 0: /* PLL1 is the clock source for SAI2A */
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+          break;
+        }
+      case RCC_SAI2ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI2A */
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_P_Frequency;
+          break;
+        }
+
+      case RCC_SAI2ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI2A  */
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+          frequency = pll3_clocks.PLL3_P_Frequency;
+          break;
+        }
+
+      case RCC_SAI2ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI2A  */
+        {
+
+          ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
+
+          if(ckpclocksource== RCC_CLKPSOURCE_HSI)
+          {
+            /* In Case the CKPER Source is HSI */
+            frequency = HSI_VALUE;
+          }
+
+          else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
+          {
+            /* In Case the CKPER Source is CSI */
+            frequency = CSI_VALUE;
+          }
+
+          else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
+          {
+            /* In Case the CKPER Source is HSE */
+            frequency = HSE_VALUE;
+          }
+
+          else
+          {
+            /* In Case the CKPER is disabled*/
+            frequency = 0;
+          }
+
+          break;
+        }
+
+      case (RCC_SAI2ACLKSOURCE_PIN): /* External clock is the clock source for SAI2A */
+        {
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+
+      default :
+        {
+          frequency = 0;
+          break;
+        }
+      }
+
+    }
+#endif
+
+#if  defined(RCC_CDCCIP1R_SAI2BSEL_0)
+  else if (PeriphClk == RCC_PERIPHCLK_SAI2B)
+    {
+
+      saiclocksource= __HAL_RCC_GET_SAI2B_SOURCE();
+
+      switch (saiclocksource)
+      {
+      case 0: /* PLL1 is the clock source for SAI2B */
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+          break;
+        }
+      case RCC_SAI2BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI2B */
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_P_Frequency;
+          break;
+        }
+
+      case RCC_SAI2BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI2B */
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+          frequency = pll3_clocks.PLL3_P_Frequency;
+          break;
+        }
+
+      case RCC_SAI2BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI2B*/
+        {
+
+          ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
+
+          if(ckpclocksource== RCC_CLKPSOURCE_HSI)
+          {
+            /* In Case the CKPER Source is HSI */
+            frequency = HSI_VALUE;
+          }
+
+          else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
+          {
+            /* In Case the CKPER Source is CSI */
+            frequency = CSI_VALUE;
+          }
+
+          else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
+          {
+            /* In Case the CKPER Source is HSE */
+            frequency = HSE_VALUE;
+          }
+
+          else
+          {
+            /* In Case the CKPER is disabled*/
+            frequency = 0;
+          }
+          break;
+        }
+
+      case (RCC_SAI2BCLKSOURCE_PIN): /* External clock is the clock source for SAI2B */
+        {
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+
+      default :
+        {
+          frequency = 0;
+          break;
+        }
+      }
+    }
+#endif
+
+#if defined(SAI4)
+  else if (PeriphClk == RCC_PERIPHCLK_SAI4A)
+    {
+
+      saiclocksource= __HAL_RCC_GET_SAI4A_SOURCE();
+
+      switch (saiclocksource)
+      {
+      case 0: /* PLL1 is the clock source for SAI4A */
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+          break;
+        }
+      case RCC_D3CCIPR_SAI4ASEL_0: /* PLLI2 is the clock source for SAI4A */
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_P_Frequency;
+          break;
+        }
+
+      case RCC_D3CCIPR_SAI4ASEL_1: /* PLLI3 is the clock source for SAI4A */
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+          frequency = pll3_clocks.PLL3_P_Frequency;
+          break;
+        }
+
+      case RCC_D3CCIPR_SAI4ASEL_2: /* CKPER is the clock source for SAI4A*/
+        {
+
+          ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
+
+          if(ckpclocksource== RCC_CLKPSOURCE_HSI)
+          {
+            /* In Case the CKPER Source is HSI */
+            frequency = HSI_VALUE;
+          }
+
+          else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
+          {
+            /* In Case the CKPER Source is CSI */
+            frequency = CSI_VALUE;
+          }
+
+          else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
+          {
+            /* In Case the CKPER Source is HSE */
+            frequency = HSE_VALUE;
+          }
+
+          else
+          {
+            /* In Case the CKPER is disabled*/
+            frequency = 0;
+          }
+
+          break;
+        }
+
+      case (RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1 ): /* External clock is the clock source for SAI4A */
+        {
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+
+      default :
+        {
+          frequency = 0;
+          break;
+        }
+      }
+    }
+
+  else if (PeriphClk == RCC_PERIPHCLK_SAI4B)
+    {
+
+      saiclocksource= __HAL_RCC_GET_SAI4B_SOURCE();
+
+      switch (saiclocksource)
+      {
+      case 0: /* PLL1 is the clock source for SAI4B */
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+          break;
+        }
+      case RCC_D3CCIPR_SAI4BSEL_0: /* PLLI2 is the clock source for SAI4B */
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_P_Frequency;
+          break;
+        }
+
+      case RCC_D3CCIPR_SAI4BSEL_1: /* PLLI3 is the clock source for SAI4B */
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+          frequency = pll3_clocks.PLL3_P_Frequency;
+          break;
+        }
+
+      case RCC_D3CCIPR_SAI4BSEL_2: /* CKPER is the clock source for SAI4B*/
+        {
+
+          ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
+
+          if(ckpclocksource== RCC_CLKPSOURCE_HSI)
+          {
+            /* In Case the CKPER Source is HSI */
+            frequency = HSI_VALUE;
+          }
+
+          else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
+          {
+            /* In Case the CKPER Source is CSI */
+            frequency = CSI_VALUE;
+          }
+
+          else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
+          {
+            /* In Case the CKPER Source is HSE */
+            frequency = HSE_VALUE;
+          }
+
+          else
+          {
+            /* In Case the CKPER is disabled*/
+            frequency = 0;
+          }
+
+          break;
+        }
+
+      case (RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1 ): /* External clock is the clock source for SAI4B */
+        {
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+
+      default :
+        {
+          frequency = 0;
+          break;
+        }
+      }
+    }
+#endif /*SAI4*/
+  else if (PeriphClk == RCC_PERIPHCLK_SPI123)
+    {
+      /* Get SPI1/2/3 clock source */
+      srcclk= __HAL_RCC_GET_SPI123_SOURCE();
+
+      switch (srcclk)
+      {
+      case RCC_SPI123CLKSOURCE_PLL: /* PLL1 is the clock source for I2S */
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+          break;
+        }
+      case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is the clock source for I2S */
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_P_Frequency;
+          break;
+        }
+
+      case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is the clock source for I2S */
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+          frequency = pll3_clocks.PLL3_P_Frequency;
+          break;
+        }
+
+      case RCC_SPI123CLKSOURCE_CLKP: /* CKPER is the clock source for I2S */
+        {
+
+          ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
+
+          if(ckpclocksource== RCC_CLKPSOURCE_HSI)
+          {
+            /* In Case the CKPER Source is HSI */
+            frequency = HSI_VALUE;
+          }
+
+          else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
+          {
+            /* In Case the CKPER Source is CSI */
+            frequency = CSI_VALUE;
+          }
+
+          else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
+          {
+            /* In Case the CKPER Source is HSE */
+            frequency = HSE_VALUE;
+          }
+
+          else
+          {
+            /* In Case the CKPER is disabled*/
+            frequency = 0;
+          }
+
+          break;
+        }
+
+      case (RCC_SPI123CLKSOURCE_PIN): /* External clock is the clock source for I2S */
+        {
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+      default :
+        {
+          frequency = 0;
+          break;
+        }
+      }
+    }
+  else if (PeriphClk == RCC_PERIPHCLK_ADC)
+    {
+      /* Get ADC clock source */
+      srcclk= __HAL_RCC_GET_ADC_SOURCE();
+
+      switch (srcclk)
+      {
+      case RCC_ADCCLKSOURCE_PLL2:
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_P_Frequency;
+          break;
+        }
+      case RCC_ADCCLKSOURCE_PLL3:
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+          frequency = pll3_clocks.PLL3_R_Frequency;
+          break;
+        }
+
+      case RCC_ADCCLKSOURCE_CLKP:
+        {
+
+          ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
+
+          if(ckpclocksource== RCC_CLKPSOURCE_HSI)
+          {
+            /* In Case the CKPER Source is HSI */
+            frequency = HSI_VALUE;
+          }
+
+          else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
+          {
+            /* In Case the CKPER Source is CSI */
+            frequency = CSI_VALUE;
+          }
+
+          else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
+          {
+            /* In Case the CKPER Source is HSE */
+            frequency = HSE_VALUE;
+          }
+
+          else
+          {
+            /* In Case the CKPER is disabled*/
+            frequency = 0;
+          }
+
+          break;
+        }
+
+      default :
+        {
+          frequency = 0;
+          break;
+        }
+      }
+    }
+  else if (PeriphClk == RCC_PERIPHCLK_SDMMC)
+    {
+      /* Get SDMMC clock source */
+      srcclk= __HAL_RCC_GET_SDMMC_SOURCE();
+
+      switch (srcclk)
+      {
+      case RCC_SDMMCCLKSOURCE_PLL: /* PLL1 is the clock source for SDMMC */
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+          break;
+        }
+      case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is the clock source for SDMMC */
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_R_Frequency;
+          break;
+        }
+
+      default :
+        {
+          frequency = 0;
+          break;
+        }
+      }
+    }
+  else if (PeriphClk == RCC_PERIPHCLK_SPI6)
+    {
+      /* Get SPI6 clock source */
+      srcclk= __HAL_RCC_GET_SPI6_SOURCE();
+
+      switch (srcclk)
+      {
+      case RCC_SPI6CLKSOURCE_D3PCLK1: /* D3PCLK1 (PCLK4) is the clock source for SPI6 */
+        {
+          frequency = HAL_RCCEx_GetD3PCLK1Freq();
+          break;
+        }
+      case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI6 */
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_Q_Frequency;
+          break;
+        }
+      case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI6 */
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+          frequency = pll3_clocks.PLL3_Q_Frequency;
+          break;
+        }
+      case RCC_SPI6CLKSOURCE_HSI: /* HSI is the clock source for SPI6 */
+        {
+          frequency = HSI_VALUE;
+          break;
+        }
+      case RCC_SPI6CLKSOURCE_CSI: /* CSI is the clock source for SPI6 */
+        {
+          frequency = CSI_VALUE;
+          break;
+        }
+      case RCC_SPI6CLKSOURCE_HSE: /* HSE is the clock source for SPI6 */
+        {
+          frequency = HSE_VALUE;
+          break;
+        }
+#if defined(RCC_SPI6CLKSOURCE_PIN)
+      case RCC_SPI6CLKSOURCE_PIN: /* External clock is the clock source for SPI6 */
+        {
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+#endif /* RCC_SPI6CLKSOURCE_PIN */
+      default :
+        {
+          frequency = 0;
+          break;
+        }
+      }
+    }
+  else
+    {
+      frequency = 0;
+    }
+
+  return frequency;
+}
+
+
+/**
+  * @brief  Returns the D1PCLK1 frequency
+  * @note   Each time D1PCLK1 changes, this function must be called to update the
+  *         right D1PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
+  * @retval D1PCLK1 frequency
+  */
+uint32_t HAL_RCCEx_GetD1PCLK1Freq(void)
+{
+#if defined(RCC_D1CFGR_D1PPRE)
+  /* Get HCLK source and Compute D1PCLK1 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1PPRE)>> RCC_D1CFGR_D1PPRE_Pos] & 0x1FU));
+#else
+/* Get HCLK source and Compute D1PCLK1 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE)>> RCC_CDCFGR1_CDPPRE_Pos] & 0x1FU));
+#endif
+}
+
+/**
+  * @brief  Returns the D3PCLK1 frequency
+  * @note   Each time D3PCLK1 changes, this function must be called to update the
+  *         right D3PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
+  * @retval D3PCLK1 frequency
+  */
+uint32_t HAL_RCCEx_GetD3PCLK1Freq(void)
+{
+#if defined(RCC_D3CFGR_D3PPRE)
+  /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE)>> RCC_D3CFGR_D3PPRE_Pos] & 0x1FU));
+#else
+  /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE)>> RCC_SRDCFGR_SRDPPRE_Pos] & 0x1FU));
+#endif
+}
+/**
+* @brief  Returns the PLL2 clock frequencies :PLL2_P_Frequency,PLL2_R_Frequency and PLL2_Q_Frequency
+  * @note   The PLL2 clock frequencies computed by this function is not the real
+  *         frequency in the chip. It is calculated based on the predefined
+  *         constant and the selected clock source:
+  * @note     The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors.
+  * @note   This function can be used by the user application to compute the
+  *         baud-rate for the communication peripherals or configure other parameters.
+  *
+  * @note   Each time PLL2CLK changes, this function must be called to update the
+  *         right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect.
+  * @param  PLL2_Clocks structure.
+  * @retval None
+  */
+void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef* PLL2_Clocks)
+{
+  uint32_t  pllsource, pll2m,  pll2fracen, hsivalue;
+  float_t fracn2, pll2vco;
+
+  /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL2M) * PLL2N
+     PLL2xCLK = PLL2_VCO / PLL2x
+  */
+  pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+  pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2)>> 12);
+  pll2fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) >> RCC_PLLCFGR_PLL2FRACEN_Pos;
+  fracn2 =(float_t)(uint32_t)(pll2fracen* ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2)>> 3));
+
+  if (pll2m != 0U)
+  {
+    switch (pllsource)
+    {
+
+    case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
+
+      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+      {
+        hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
+        pll2vco = ( (float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );
+      }
+      else
+      {
+        pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );
+      }
+      break;
+
+    case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
+      pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );
+      break;
+
+    case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
+      pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );
+      break;
+
+    default:
+      pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );
+      break;
+    }
+    PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >>9)  + (float_t)1 )) ;
+    PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >>16) + (float_t)1 )) ;
+    PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >>24) + (float_t)1 )) ;
+  }
+  else
+  {
+    PLL2_Clocks->PLL2_P_Frequency = 0U;
+    PLL2_Clocks->PLL2_Q_Frequency = 0U;
+    PLL2_Clocks->PLL2_R_Frequency = 0U;
+  }
+}
+
+/**
+* @brief  Returns the PLL3 clock frequencies :PLL3_P_Frequency,PLL3_R_Frequency and PLL3_Q_Frequency
+  * @note   The PLL3 clock frequencies computed by this function is not the real
+  *         frequency in the chip. It is calculated based on the predefined
+  *         constant and the selected clock source:
+  * @note     The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors.
+  * @note   This function can be used by the user application to compute the
+  *         baud-rate for the communication peripherals or configure other parameters.
+  *
+  * @note   Each time PLL3CLK changes, this function must be called to update the
+  *         right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect.
+  * @param  PLL3_Clocks structure.
+  * @retval None
+  */
+void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef* PLL3_Clocks)
+{
+  uint32_t pllsource, pll3m, pll3fracen, hsivalue;
+  float_t fracn3, pll3vco;
+
+  /* PLL3_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL3M) * PLL3N
+     PLL3xCLK = PLL3_VCO / PLLxR
+  */
+  pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+  pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3)>> 20)  ;
+  pll3fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) >> RCC_PLLCFGR_PLL3FRACEN_Pos;
+  fracn3 = (float_t)(uint32_t)(pll3fracen* ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3)>> 3));
+
+  if (pll3m != 0U)
+  {
+    switch (pllsource)
+    {
+    case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
+
+      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+      {
+        hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
+        pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );
+      }
+      else
+      {
+        pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );
+      }
+      break;
+    case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
+      pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );
+      break;
+
+    case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
+      pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );
+      break;
+
+    default:
+      pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );
+      break;
+    }
+    PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >>9)  + (float_t)1 )) ;
+    PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >>16) + (float_t)1 )) ;
+    PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >>24) + (float_t)1 )) ;
+  }
+  else
+  {
+    PLL3_Clocks->PLL3_P_Frequency = 0U;
+    PLL3_Clocks->PLL3_Q_Frequency = 0U;
+    PLL3_Clocks->PLL3_R_Frequency = 0U;
+  }
+
+}
+
+/**
+* @brief  Returns the PLL1 clock frequencies :PLL1_P_Frequency,PLL1_R_Frequency and PLL1_Q_Frequency
+  * @note   The PLL1 clock frequencies computed by this function is not the real
+  *         frequency in the chip. It is calculated based on the predefined
+  *         constant and the selected clock source:
+  * @note     The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors.
+  * @note   This function can be used by the user application to compute the
+  *         baud-rate for the communication peripherals or configure other parameters.
+  *
+  * @note   Each time PLL1CLK changes, this function must be called to update the
+  *         right PLL1CLK value. Otherwise, any configuration based on this function will be incorrect.
+  * @param  PLL1_Clocks structure.
+  * @retval None
+  */
+void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef* PLL1_Clocks)
+{
+  uint32_t pllsource, pll1m, pll1fracen, hsivalue;
+  float_t fracn1, pll1vco;
+
+  pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+  pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4);
+  pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN;
+  fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
+
+  if (pll1m != 0U)
+  {
+    switch (pllsource)
+    {
+
+    case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
+
+      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+      {
+        hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
+        pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+      }
+      else
+      {
+        pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+      }
+      break;
+    case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
+      pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+      break;
+
+    case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
+      pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+      break;
+
+    default:
+      pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+      break;
+    }
+
+    PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9)  + (float_t)1 )) ;
+    PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >>16) + (float_t)1 )) ;
+    PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >>24) + (float_t)1 )) ;
+  }
+  else
+  {
+    PLL1_Clocks->PLL1_P_Frequency = 0U;
+    PLL1_Clocks->PLL1_Q_Frequency = 0U;
+    PLL1_Clocks->PLL1_R_Frequency = 0U;
+  }
+
+}
+
+/**
+  * @brief  Returns the main System frequency
+  * @note   Each time System clock changes, this function must be called to update the
+  *         right core clock value. Otherwise, any configuration based on this function will be incorrect.
+  * @note   The SystemCoreClock CMSIS variable is used to store System current Core Clock Frequency
+  *         and updated within this function
+  * @retval HCLK frequency
+  */
+uint32_t HAL_RCCEx_GetD1SysClockFreq(void)
+{
+uint32_t common_system_clock;
+
+#if defined(RCC_D1CFGR_D1CPRE)
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
+#else
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU);
+#endif
+
+  /* Update the SystemD2Clock global variable */
+#if defined(RCC_D1CFGR_HPRE)
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+#else
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+#endif
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  SystemCoreClock = SystemD2Clock;
+#else
+  SystemCoreClock = common_system_clock;
+#endif /* DUAL_CORE && CORE_CM4 */
+
+  return common_system_clock;
+}
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_Exported_Functions_Group2 Extended System Control functions
+ *  @brief  Extended Peripheral Control functions
+  * @{
+  */
+/**
+  * @brief  Enables the LSE Clock Security System.
+  * @note   Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled
+  *         with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC
+  *         clock with HAL_RCCEx_PeriphCLKConfig().
+  * @retval None
+  */
+void HAL_RCCEx_EnableLSECSS(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
+}
+
+/**
+  * @brief  Disables the LSE Clock Security System.
+  * @note   LSE Clock Security System can only be disabled after a LSE failure detection.
+  * @retval None
+  */
+void HAL_RCCEx_DisableLSECSS(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
+  /* Disable LSE CSS IT if any */
+  __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS);
+}
+
+/**
+  * @brief  Enable the LSE Clock Security System Interrupt & corresponding EXTI line.
+  * @note   LSE Clock Security System Interrupt is mapped on EXTI line 18
+  * @retval None
+  */
+void HAL_RCCEx_EnableLSECSS_IT(void)
+{
+  /* Enable LSE CSS */
+  SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
+
+  /* Enable LSE CSS IT */
+  __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS);
+
+  /* Enable IT on EXTI Line 18 */
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  __HAL_RCC_C2_LSECSS_EXTI_ENABLE_IT();
+#else
+  __HAL_RCC_LSECSS_EXTI_ENABLE_IT();
+#endif /* DUAL_CORE && CORE_CM4 */
+  __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();
+}
+
+/**
+  * @brief  Configure the oscillator clock source for wakeup from Stop and CSS backup clock
+  * @param  WakeUpClk: Wakeup clock
+  *         This parameter can be one of the following values:
+  *            @arg RCC_STOP_WAKEUPCLOCK_CSI: CSI oscillator selection
+  *            @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI oscillator selection
+  * @note   This function shall not be called after the Clock Security System on HSE has been
+  *         enabled.
+  * @retval None
+  */
+void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)
+{
+  assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk));
+
+  __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk);
+}
+
+/**
+  * @brief  Configure the oscillator Kernel clock source for wakeup from Stop
+  * @param  WakeUpClk: Kernel Wakeup clock
+  *         This parameter can be one of the following values:
+  *            @arg RCC_STOP_KERWAKEUPCLOCK_CSI: CSI oscillator selection
+  *            @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI oscillator selection
+  * @retval None
+  */
+void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk)
+{
+  assert_param(IS_RCC_STOP_KERWAKEUPCLOCK(WakeUpClk));
+
+  __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(WakeUpClk);
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Enable COREx boot independently of CMx_B option byte value
+  * @param  RCC_BootCx: Boot Core to be enabled
+  *         This parameter can be one of the following values:
+  *            @arg RCC_BOOT_C1: CM7 core selection
+  *            @arg RCC_BOOT_C2: CM4 core selection
+  * @note   This bit can be set by software but is cleared by hardware after a system reset or STANDBY
+  *
+  * @retval None
+  */
+void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx)
+{
+  assert_param(IS_RCC_BOOT_CORE(RCC_BootCx));
+  SET_BIT(RCC->GCR, RCC_BootCx) ;
+}
+
+#endif /*DUAL_CORE*/
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Configure WWDGx to generate a system reset not only CPUx reset(default) when a time-out occurs
+  * @param  RCC_WWDGx: WWDGx to be configured
+  *         This parameter can be one of the following values:
+  *            @arg RCC_WWDG1: WWDG1 generates system reset
+  *            @arg RCC_WWDG2: WWDG2 generates system reset
+  * @note   This bit can be set by software but is cleared by hardware during a system reset
+  *
+  * @retval None
+  */
+void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx)
+{
+  assert_param(IS_RCC_SCOPE_WWDG(RCC_WWDGx));
+  SET_BIT(RCC->GCR, RCC_WWDGx) ;
+}
+
+#else
+#if defined(RCC_GCR_WW1RSC)
+/**
+  * @brief  Configure WWDG1 to generate a system reset not only CPU reset(default) when a time-out occurs
+  * @param  RCC_WWDGx: WWDGx to be configured
+  *         This parameter can be one of the following values:
+  *            @arg RCC_WWDG1: WWDG1 generates system reset
+  * @note   This bit can be set by software but is cleared by hardware during a system reset
+  *
+  * @retval None
+  */
+void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx)
+{
+  assert_param(IS_RCC_SCOPE_WWDG(RCC_WWDGx));
+  SET_BIT(RCC->GCR, RCC_WWDGx) ;
+}
+#endif
+#endif /*DUAL_CORE*/
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions
+ *  @brief  Extended Clock Recovery System Control functions
+ *
+@verbatim
+ ===============================================================================
+                ##### Extended Clock Recovery System Control functions  #####
+ ===============================================================================
+    [..]
+      For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows:
+
+      (#) In System clock config, HSI48 needs to be enabled
+
+      (#) Enable CRS clock in IP MSP init which will use CRS functions
+
+      (#) Call CRS functions as follows:
+          (##) Prepare synchronization configuration necessary for HSI48 calibration
+              (+++) Default values can be set for frequency Error Measurement (reload and error limit)
+                        and also HSI48 oscillator smooth trimming.
+              (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
+                        directly reload value with target and synchronization frequencies values
+          (##) Call function HAL_RCCEx_CRSConfig which
+              (+++) Resets CRS registers to their default values.
+              (+++) Configures CRS registers with synchronization configuration
+              (+++) Enables automatic calibration and frequency error counter feature
+           Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the
+           periodic USB SOF will not be generated by the host. No SYNC signal will therefore be
+           provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock
+           precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs
+           should be used as SYNC signal.
+
+          (##) A polling function is provided to wait for complete synchronization
+              (+++) Call function HAL_RCCEx_CRSWaitSynchronization()
+              (+++) According to CRS status, user can decide to adjust again the calibration or continue
+                        application if synchronization is OK
+
+      (#) User can retrieve information related to synchronization in calling function
+            HAL_RCCEx_CRSGetSynchronizationInfo()
+
+      (#) Regarding synchronization status and synchronization information, user can try a new calibration
+           in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
+           Note: When the SYNC event is detected during the down-counting phase (before reaching the zero value),
+           it means that the actual frequency is lower than the target (and so, that the TRIM value should be
+           incremented), while when it is detected during the up-counting phase it means that the actual frequency
+           is higher (and that the TRIM value should be decremented).
+
+      (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go
+          through CRS Handler (CRS_IRQn/CRS_IRQHandler)
+              (++) Call function HAL_RCCEx_CRSConfig()
+              (++) Enable CRS_IRQn (thanks to NVIC functions)
+              (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT)
+              (++) Implement CRS status management in the following user callbacks called from
+                   HAL_RCCEx_CRS_IRQHandler():
+                   (+++) HAL_RCCEx_CRS_SyncOkCallback()
+                   (+++) HAL_RCCEx_CRS_SyncWarnCallback()
+                   (+++) HAL_RCCEx_CRS_ExpectedSyncCallback()
+                   (+++) HAL_RCCEx_CRS_ErrorCallback()
+
+      (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate().
+          This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler)
+
+@endverbatim
+ * @{
+ */
+
+/**
+  * @brief  Start automatic synchronization for polling mode
+  * @param  pInit Pointer on RCC_CRSInitTypeDef structure
+  * @retval None
+  */
+void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
+{
+  uint32_t value;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));
+  assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));
+  assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));
+  assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));
+  assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));
+  assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));
+
+  /* CONFIGURATION */
+
+  /* Before configuration, reset CRS registers to their default values*/
+  __HAL_RCC_CRS_FORCE_RESET();
+  __HAL_RCC_CRS_RELEASE_RESET();
+
+  /* Set the SYNCDIV[2:0] bits according to Pre-scaler value */
+  /* Set the SYNCSRC[1:0] bits according to Source value */
+  /* Set the SYNCSPOL bit according to Polarity value */
+  if ((HAL_GetREVID() <= REV_ID_Y) && (pInit->Source == RCC_CRS_SYNC_SOURCE_USB2))
+  {
+    /* Use Rev.Y value of USB2 */
+    value = (pInit->Prescaler | RCC_CRS_SYNC_SOURCE_PIN | pInit->Polarity);
+  }
+  else
+  {
+    value = (pInit->Prescaler | pInit->Source | pInit->Polarity);
+  }
+  /* Set the RELOAD[15:0] bits according to ReloadValue value */
+  value |= pInit->ReloadValue;
+  /* Set the FELIM[7:0] bits according to ErrorLimitValue value */
+  value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos);
+  WRITE_REG(CRS->CFGR, value);
+
+  /* Adjust HSI48 oscillator smooth trimming */
+  /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */
+  MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos));
+
+  /* START AUTOMATIC SYNCHRONIZATION*/
+
+  /* Enable Automatic trimming & Frequency error counter */
+  SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN);
+}
+
+/**
+  * @brief  Generate the software synchronization event
+  * @retval None
+  */
+void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_SWSYNC);
+}
+
+/**
+  * @brief  Return synchronization info
+  * @param  pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
+  * @retval None
+  */
+void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
+{
+  /* Check the parameter */
+  assert_param(pSynchroInfo != (void *)NULL);
+
+  /* Get the reload value */
+  pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
+
+  /* Get HSI48 oscillator smooth trimming */
+  pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
+
+  /* Get Frequency error capture */
+  pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
+
+  /* Get Frequency error direction */
+  pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
+}
+
+/**
+* @brief Wait for CRS Synchronization status.
+* @param Timeout  Duration of the time-out
+* @note  Timeout is based on the maximum time to receive a SYNC event based on synchronization
+*        frequency.
+* @note    If Time-out set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
+* @retval Combination of Synchronization status
+*          This parameter can be a combination of the following values:
+*            @arg @ref RCC_CRS_TIMEOUT
+*            @arg @ref RCC_CRS_SYNCOK
+*            @arg @ref RCC_CRS_SYNCWARN
+*            @arg @ref RCC_CRS_SYNCERR
+*            @arg @ref RCC_CRS_SYNCMISS
+*            @arg @ref RCC_CRS_TRIMOVF
+*/
+uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
+{
+  uint32_t crsstatus = RCC_CRS_NONE;
+  uint32_t tickstart;
+
+  /* Get time-out */
+  tickstart = HAL_GetTick();
+
+  /* Wait for CRS flag or time-out detection */
+  do
+  {
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+      {
+        crsstatus = RCC_CRS_TIMEOUT;
+      }
+    }
+    /* Check CRS SYNCOK flag  */
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))
+    {
+      /* CRS SYNC event OK */
+      crsstatus |= RCC_CRS_SYNCOK;
+
+      /* Clear CRS SYNC event OK bit */
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);
+    }
+
+    /* Check CRS SYNCWARN flag  */
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))
+    {
+      /* CRS SYNC warning */
+      crsstatus |= RCC_CRS_SYNCWARN;
+
+      /* Clear CRS SYNCWARN bit */
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);
+    }
+
+    /* Check CRS TRIM overflow flag  */
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))
+    {
+      /* CRS SYNC Error */
+      crsstatus |= RCC_CRS_TRIMOVF;
+
+      /* Clear CRS Error bit */
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);
+    }
+
+    /* Check CRS Error flag  */
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))
+    {
+      /* CRS SYNC Error */
+      crsstatus |= RCC_CRS_SYNCERR;
+
+      /* Clear CRS Error bit */
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);
+    }
+
+    /* Check CRS SYNC Missed flag  */
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))
+    {
+      /* CRS SYNC Missed */
+      crsstatus |= RCC_CRS_SYNCMISS;
+
+      /* Clear CRS SYNC Missed bit */
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);
+    }
+
+    /* Check CRS Expected SYNC flag  */
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))
+    {
+      /* frequency error counter reached a zero value */
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
+    }
+  } while(RCC_CRS_NONE == crsstatus);
+
+  return crsstatus;
+}
+
+/**
+  * @brief Handle the Clock Recovery System interrupt request.
+  * @retval None
+  */
+void HAL_RCCEx_CRS_IRQHandler(void)
+{
+  uint32_t crserror = RCC_CRS_NONE;
+  /* Get current IT flags and IT sources values */
+  uint32_t itflags = READ_REG(CRS->ISR);
+  uint32_t itsources = READ_REG(CRS->CR);
+
+  /* Check CRS SYNCOK flag  */
+  if(((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U))
+  {
+    /* Clear CRS SYNC event OK flag */
+    WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
+
+    /* user callback */
+    HAL_RCCEx_CRS_SyncOkCallback();
+  }
+  /* Check CRS SYNCWARN flag  */
+  else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U))
+  {
+    /* Clear CRS SYNCWARN flag */
+    WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
+
+    /* user callback */
+    HAL_RCCEx_CRS_SyncWarnCallback();
+  }
+  /* Check CRS Expected SYNC flag  */
+  else if(((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U))
+  {
+    /* frequency error counter reached a zero value */
+    WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
+
+    /* user callback */
+    HAL_RCCEx_CRS_ExpectedSyncCallback();
+  }
+  /* Check CRS Error flags  */
+  else
+  {
+    if(((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U))
+    {
+      if((itflags & RCC_CRS_FLAG_SYNCERR) != 0U)
+      {
+        crserror |= RCC_CRS_SYNCERR;
+      }
+      if((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U)
+      {
+        crserror |= RCC_CRS_SYNCMISS;
+      }
+      if((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U)
+      {
+        crserror |= RCC_CRS_TRIMOVF;
+      }
+
+      /* Clear CRS Error flags */
+      WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
+
+      /* user error callback */
+      HAL_RCCEx_CRS_ErrorCallback(crserror);
+    }
+  }
+}
+
+/**
+  * @brief  RCCEx Clock Recovery System SYNCOK interrupt callback.
+  * @retval none
+  */
+__weak void HAL_RCCEx_CRS_SyncOkCallback(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file
+   */
+}
+
+/**
+  * @brief  RCCEx Clock Recovery System SYNCWARN interrupt callback.
+  * @retval none
+  */
+__weak void HAL_RCCEx_CRS_SyncWarnCallback(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file
+   */
+}
+
+/**
+  * @brief  RCCEx Clock Recovery System Expected SYNC interrupt callback.
+  * @retval none
+  */
+__weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file
+   */
+}
+
+/**
+  * @brief  RCCEx Clock Recovery System Error interrupt callback.
+  * @param  Error Combination of Error status.
+  *         This parameter can be a combination of the following values:
+  *           @arg @ref RCC_CRS_SYNCERR
+  *           @arg @ref RCC_CRS_SYNCMISS
+  *           @arg @ref RCC_CRS_TRIMOVF
+  * @retval none
+  */
+__weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(Error);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file
+   */
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_Private_functions Private Functions
+ * @{
+ */
+/**
+  * @brief  Configure the PLL2 VCI,VCO ranges, multiplication and division factors and enable it
+  * @param  pll2: Pointer to an RCC_PLL2InitTypeDef structure that
+  *         contains the configuration parameters  as well as VCI, VCO clock ranges.
+  * @param  Divider  divider parameter to be updated
+  * @note   PLL2 is temporary disabled to apply new parameters
+  *
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider)
+{
+
+  uint32_t tickstart;
+  HAL_StatusTypeDef status = HAL_OK;
+  assert_param(IS_RCC_PLL2M_VALUE(pll2->PLL2M));
+  assert_param(IS_RCC_PLL2N_VALUE(pll2->PLL2N));
+  assert_param(IS_RCC_PLL2P_VALUE(pll2->PLL2P));
+  assert_param(IS_RCC_PLL2R_VALUE(pll2->PLL2R));
+  assert_param(IS_RCC_PLL2Q_VALUE(pll2->PLL2Q));
+  assert_param(IS_RCC_PLL2RGE_VALUE(pll2->PLL2RGE));
+  assert_param(IS_RCC_PLL2VCO_VALUE(pll2->PLL2VCOSEL));
+  assert_param(IS_RCC_PLLFRACN_VALUE(pll2->PLL2FRACN));
+
+  /* Check that PLL2 OSC clock source is already set */
+  if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
+  {
+    return HAL_ERROR;
+  }
+
+
+  else
+  {
+    /* Disable  PLL2. */
+    __HAL_RCC_PLL2_DISABLE();
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+
+    /* Wait till PLL is disabled */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U)
+    {
+      if( (HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Configure PLL2 multiplication and division factors. */
+    __HAL_RCC_PLL2_CONFIG(pll2->PLL2M,
+                          pll2->PLL2N,
+                          pll2->PLL2P,
+                          pll2->PLL2Q,
+                          pll2->PLL2R);
+
+    /* Select PLL2 input reference frequency range: VCI */
+    __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE) ;
+
+    /* Select PLL2 output frequency range : VCO */
+    __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ;
+
+    /* Disable PLL2FRACN . */
+    __HAL_RCC_PLL2FRACN_DISABLE();
+
+    /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */
+    __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN);
+
+    /* Enable PLL2FRACN . */
+    __HAL_RCC_PLL2FRACN_ENABLE();
+
+    /* Enable the PLL2 clock output */
+    if(Divider == DIVIDER_P_UPDATE)
+    {
+      __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP);
+    }
+    else if(Divider == DIVIDER_Q_UPDATE)
+    {
+      __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ);
+    }
+    else
+    {
+      __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR);
+    }
+
+    /* Enable  PLL2. */
+    __HAL_RCC_PLL2_ENABLE();
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+
+    /* Wait till PLL2 is ready */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U)
+    {
+      if( (HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+
+  }
+
+
+  return status;
+}
+
+
+/**
+  * @brief  Configure the PLL3 VCI,VCO ranges, multiplication and division factors and enable it
+  * @param  pll3: Pointer to an RCC_PLL3InitTypeDef structure that
+  *         contains the configuration parameters  as well as VCI, VCO clock ranges.
+  * @param  Divider  divider parameter to be updated
+  * @note   PLL3 is temporary disabled to apply new parameters
+  *
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider)
+{
+  uint32_t tickstart;
+  HAL_StatusTypeDef status = HAL_OK;
+  assert_param(IS_RCC_PLL3M_VALUE(pll3->PLL3M));
+  assert_param(IS_RCC_PLL3N_VALUE(pll3->PLL3N));
+  assert_param(IS_RCC_PLL3P_VALUE(pll3->PLL3P));
+  assert_param(IS_RCC_PLL3R_VALUE(pll3->PLL3R));
+  assert_param(IS_RCC_PLL3Q_VALUE(pll3->PLL3Q));
+  assert_param(IS_RCC_PLL3RGE_VALUE(pll3->PLL3RGE));
+  assert_param(IS_RCC_PLL3VCO_VALUE(pll3->PLL3VCOSEL));
+  assert_param(IS_RCC_PLLFRACN_VALUE(pll3->PLL3FRACN));
+
+  /* Check that PLL3 OSC clock source is already set */
+  if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
+  {
+    return HAL_ERROR;
+  }
+
+
+  else
+  {
+    /* Disable  PLL3. */
+    __HAL_RCC_PLL3_DISABLE();
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+    /* Wait till PLL3 is ready */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U)
+    {
+      if( (HAL_GetTick() - tickstart ) > PLL3_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Configure the PLL3  multiplication and division factors. */
+    __HAL_RCC_PLL3_CONFIG(pll3->PLL3M,
+                          pll3->PLL3N,
+                          pll3->PLL3P,
+                          pll3->PLL3Q,
+                          pll3->PLL3R);
+
+    /* Select PLL3 input reference frequency range: VCI */
+    __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ;
+
+    /* Select PLL3 output frequency range : VCO */
+    __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ;
+
+    /* Disable PLL3FRACN . */
+    __HAL_RCC_PLL3FRACN_DISABLE();
+
+    /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */
+    __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN);
+
+    /* Enable PLL3FRACN . */
+    __HAL_RCC_PLL3FRACN_ENABLE();
+
+    /* Enable the PLL3 clock output */
+    if(Divider == DIVIDER_P_UPDATE)
+    {
+      __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP);
+    }
+    else if(Divider == DIVIDER_Q_UPDATE)
+    {
+      __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
+    }
+    else
+    {
+      __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
+    }
+
+    /* Enable  PLL3. */
+    __HAL_RCC_PLL3_ENABLE();
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+
+    /* Wait till PLL3 is ready */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U)
+    {
+      if( (HAL_GetTick() - tickstart ) > PLL3_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+
+  }
+
+
+  return status;
+}
+
+/**
+  * @brief Handle the RCC LSE Clock Security System interrupt request.
+  * @retval None
+  */
+void HAL_RCCEx_LSECSS_IRQHandler(void)
+{
+  /* Check RCC LSE CSSF flag  */
+  if(__HAL_RCC_GET_IT(RCC_IT_LSECSS))
+  {
+
+    /* Clear RCC LSE CSS pending bit */
+    __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS);
+
+    /* RCC LSE Clock Security System interrupt user callback */
+    HAL_RCCEx_LSECSS_Callback();
+
+  }
+}
+
+/**
+  * @brief  RCCEx LSE Clock Security System interrupt callback.
+  * @retval none
+  */
+__weak void HAL_RCCEx_LSECSS_Callback(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file
+   */
+}
+
+
+
+/**
+  * @}
+  */
+
+#endif /* HAL_RCC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c
new file mode 100644
index 00000000..1885d04b
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c
@@ -0,0 +1,7047 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_tim.c
+  * @author  MCD Application Team
+  * @brief   TIM HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Timer (TIM) peripheral:
+  *           + TIM Time Base Initialization
+  *           + TIM Time Base Start
+  *           + TIM Time Base Start Interruption
+  *           + TIM Time Base Start DMA
+  *           + TIM Output Compare/PWM Initialization
+  *           + TIM Output Compare/PWM Channel Configuration
+  *           + TIM Output Compare/PWM  Start
+  *           + TIM Output Compare/PWM  Start Interruption
+  *           + TIM Output Compare/PWM Start DMA
+  *           + TIM Input Capture Initialization
+  *           + TIM Input Capture Channel Configuration
+  *           + TIM Input Capture Start
+  *           + TIM Input Capture Start Interruption
+  *           + TIM Input Capture Start DMA
+  *           + TIM One Pulse Initialization
+  *           + TIM One Pulse Channel Configuration
+  *           + TIM One Pulse Start
+  *           + TIM Encoder Interface Initialization
+  *           + TIM Encoder Interface Start
+  *           + TIM Encoder Interface Start Interruption
+  *           + TIM Encoder Interface Start DMA
+  *           + Commutation Event configuration with Interruption and DMA
+  *           + TIM OCRef clear configuration
+  *           + TIM External Clock configuration
+  @verbatim
+  ==============================================================================
+                      ##### TIMER Generic features #####
+  ==============================================================================
+  [..] The Timer features include:
+       (#) 16-bit up, down, up/down auto-reload counter.
+       (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
+           counter clock frequency either by any factor between 1 and 65536.
+       (#) Up to 4 independent channels for:
+           (++) Input Capture
+           (++) Output Compare
+           (++) PWM generation (Edge and Center-aligned Mode)
+           (++) One-pulse mode output
+       (#) Synchronization circuit to control the timer with external signals and to interconnect
+            several timers together.
+       (#) Supports incremental encoder for positioning purposes
+
+            ##### How to use this driver #####
+  ==============================================================================
+    [..]
+     (#) Initialize the TIM low level resources by implementing the following functions
+         depending on the selected feature:
+           (++) Time Base : HAL_TIM_Base_MspInit()
+           (++) Input Capture : HAL_TIM_IC_MspInit()
+           (++) Output Compare : HAL_TIM_OC_MspInit()
+           (++) PWM generation : HAL_TIM_PWM_MspInit()
+           (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
+           (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
+
+     (#) Initialize the TIM low level resources :
+        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
+        (##) TIM pins configuration
+            (+++) Enable the clock for the TIM GPIOs using the following function:
+             __HAL_RCC_GPIOx_CLK_ENABLE();
+            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
+
+     (#) The external Clock can be configured, if needed (the default clock is the
+         internal clock from the APBx), using the following function:
+         HAL_TIM_ConfigClockSource, the clock configuration should be done before
+         any start function.
+
+     (#) Configure the TIM in the desired functioning mode using one of the
+       Initialization function of this driver:
+       (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
+       (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
+            Output Compare signal.
+       (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
+            PWM signal.
+       (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
+            external signal.
+       (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
+            in One Pulse Mode.
+       (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
+
+     (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
+           (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
+           (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
+           (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
+           (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
+           (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
+           (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
+
+     (#) The DMA Burst is managed with the two following functions:
+         HAL_TIM_DMABurst_WriteStart()
+         HAL_TIM_DMABurst_ReadStart()
+
+    *** Callback registration ***
+  =============================================
+
+  [..]
+  The compilation define  USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
+  allows the user to configure dynamically the driver callbacks.
+
+  [..]
+  Use Function @ref HAL_TIM_RegisterCallback() to register a callback.
+  @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
+  the Callback ID and a pointer to the user callback function.
+
+  [..]
+  Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default
+  weak function.
+  @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
+  and the Callback ID.
+
+  [..]
+  These functions allow to register/unregister following callbacks:
+    (+) Base_MspInitCallback              : TIM Base Msp Init Callback.
+    (+) Base_MspDeInitCallback            : TIM Base Msp DeInit Callback.
+    (+) IC_MspInitCallback                : TIM IC Msp Init Callback.
+    (+) IC_MspDeInitCallback              : TIM IC Msp DeInit Callback.
+    (+) OC_MspInitCallback                : TIM OC Msp Init Callback.
+    (+) OC_MspDeInitCallback              : TIM OC Msp DeInit Callback.
+    (+) PWM_MspInitCallback               : TIM PWM Msp Init Callback.
+    (+) PWM_MspDeInitCallback             : TIM PWM Msp DeInit Callback.
+    (+) OnePulse_MspInitCallback          : TIM One Pulse Msp Init Callback.
+    (+) OnePulse_MspDeInitCallback        : TIM One Pulse Msp DeInit Callback.
+    (+) Encoder_MspInitCallback           : TIM Encoder Msp Init Callback.
+    (+) Encoder_MspDeInitCallback         : TIM Encoder Msp DeInit Callback.
+    (+) HallSensor_MspInitCallback        : TIM Hall Sensor Msp Init Callback.
+    (+) HallSensor_MspDeInitCallback      : TIM Hall Sensor Msp DeInit Callback.
+    (+) PeriodElapsedCallback             : TIM Period Elapsed Callback.
+    (+) PeriodElapsedHalfCpltCallback     : TIM Period Elapsed half complete Callback.
+    (+) TriggerCallback                   : TIM Trigger Callback.
+    (+) TriggerHalfCpltCallback           : TIM Trigger half complete Callback.
+    (+) IC_CaptureCallback                : TIM Input Capture Callback.
+    (+) IC_CaptureHalfCpltCallback        : TIM Input Capture half complete Callback.
+    (+) OC_DelayElapsedCallback           : TIM Output Compare Delay Elapsed Callback.
+    (+) PWM_PulseFinishedCallback         : TIM PWM Pulse Finished Callback.
+    (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
+    (+) ErrorCallback                     : TIM Error Callback.
+    (+) CommutationCallback               : TIM Commutation Callback.
+    (+) CommutationHalfCpltCallback       : TIM Commutation half complete Callback.
+    (+) BreakCallback                     : TIM Break Callback.
+    (+) Break2Callback                    : TIM Break2 Callback.
+
+  [..]
+By default, after the Init and when the state is HAL_TIM_STATE_RESET
+all interrupt callbacks are set to the corresponding weak functions:
+  examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().
+
+  [..]
+  Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
+  functionalities in the Init / DeInit only when these callbacks are null
+  (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
+    keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
+
+  [..]
+    Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
+    Exception done MspInit / MspDeInit that can be registered / unregistered
+    in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
+    thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
+  In that case first register the MspInit/MspDeInit user callbacks
+      using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.
+
+  [..]
+      When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
+      not defined, the callback registration feature is not available and all callbacks
+      are set to the corresponding weak functions.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup TIM TIM
+  * @brief TIM HAL module driver
+  * @{
+  */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup TIM_Private_Functions
+  * @{
+  */
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter);
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter);
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter);
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+                                                  TIM_SlaveConfigTypeDef *sSlaveConfig);
+/**
+  * @}
+  */
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup TIM_Exported_Functions TIM Exported Functions
+  * @{
+  */
+
+/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
+  *  @brief    Time Base functions
+  *
+@verbatim
+  ==============================================================================
+              ##### Time Base functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM base.
+    (+) De-initialize the TIM base.
+    (+) Start the Time Base.
+    (+) Stop the Time Base.
+    (+) Start the Time Base and enable interrupt.
+    (+) Stop the Time Base and disable interrupt.
+    (+) Start the Time Base and enable DMA transfer.
+    (+) Stop the Time Base and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Time base Unit according to the specified
+  *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->Base_MspInitCallback == NULL)
+    {
+      htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->Base_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    HAL_TIM_Base_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Set the Time Base configuration */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM Base peripheral
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->Base_MspDeInitCallback == NULL)
+  {
+    htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->Base_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIM_Base_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Base MSP.
+  * @param  htim TIM Base handle
+  * @retval None
+  */
+__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_Base_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Base MSP.
+  * @param  htim TIM Base handle
+  * @retval None
+  */
+__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_Base_MspDeInit could be implemented in the user file
+   */
+}
+
+
+/**
+  * @brief  Starts the TIM Base generation.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Change the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Base generation.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Base generation in interrupt mode.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  /* Enable the TIM Update interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Base generation in interrupt mode.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  /* Disable the TIM Update interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Base generation in DMA mode.
+  * @param  htim TIM Base handle
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if ((pData == NULL) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+  /* Set the DMA Period elapsed callbacks */
+  htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+  htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+
+  /* Set the DMA error callback */
+  htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+  /* Enable the DMA stream */
+  if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Enable the TIM Update DMA request */
+  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Base generation in DMA mode.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+
+  /* Disable the TIM Update DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
+
+  (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
+  *  @brief    TIM Output Compare functions
+  *
+@verbatim
+  ==============================================================================
+                  ##### TIM Output Compare functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM Output Compare.
+    (+) De-initialize the TIM Output Compare.
+    (+) Start the TIM Output Compare.
+    (+) Stop the TIM Output Compare.
+    (+) Start the TIM Output Compare and enable interrupt.
+    (+) Stop the TIM Output Compare and disable interrupt.
+    (+) Start the TIM Output Compare and enable DMA transfer.
+    (+) Stop the TIM Output Compare and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Output Compare according to the specified
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
+  * @param  htim TIM Output Compare handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->OC_MspInitCallback == NULL)
+    {
+      htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->OC_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_OC_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Init the base time for the Output Compare */
+  TIM_Base_SetConfig(htim->Instance,  &htim->Init);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM peripheral
+  * @param  htim TIM Output Compare handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->OC_MspDeInitCallback == NULL)
+  {
+    htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->OC_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+  HAL_TIM_OC_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Output Compare MSP.
+  * @param  htim TIM Output Compare handle
+  * @retval None
+  */
+__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OC_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Output Compare MSP.
+  * @param  htim TIM Output Compare handle
+  * @retval None
+  */
+__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OC_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Enable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in interrupt mode.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Enable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Enable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in interrupt mode.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Disable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in DMA mode.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if ((pData == NULL) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Enable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 4 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Enable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in DMA mode.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Disable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
+  *  @brief    TIM PWM functions
+  *
+@verbatim
+  ==============================================================================
+                          ##### TIM PWM functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM PWM.
+    (+) De-initialize the TIM PWM.
+    (+) Start the TIM PWM.
+    (+) Stop the TIM PWM.
+    (+) Start the TIM PWM and enable interrupt.
+    (+) Stop the TIM PWM and disable interrupt.
+    (+) Start the TIM PWM and enable DMA transfer.
+    (+) Stop the TIM PWM and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM PWM Time Base according to the specified
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
+  * @param  htim TIM PWM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->PWM_MspInitCallback == NULL)
+    {
+      htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->PWM_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_PWM_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Init the base time for the PWM */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM peripheral
+  * @param  htim TIM PWM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->PWM_MspDeInitCallback == NULL)
+  {
+    htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->PWM_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+  HAL_TIM_PWM_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM PWM MSP.
+  * @param  htim TIM PWM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM PWM MSP.
+  * @param  htim TIM PWM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the PWM signal generation.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Enable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the PWM signal generation.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the PWM signal generation in interrupt mode.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Enable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Enable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the PWM signal generation in interrupt mode.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Disable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM PWM signal generation in DMA mode.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if ((pData == NULL) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Output Capture/Compare 3 request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 4 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Enable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM PWM signal generation in DMA mode.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Disable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
+  *  @brief    TIM Input Capture functions
+  *
+@verbatim
+  ==============================================================================
+              ##### TIM Input Capture functions #####
+  ==============================================================================
+ [..]
+   This section provides functions allowing to:
+   (+) Initialize and configure the TIM Input Capture.
+   (+) De-initialize the TIM Input Capture.
+   (+) Start the TIM Input Capture.
+   (+) Stop the TIM Input Capture.
+   (+) Start the TIM Input Capture and enable interrupt.
+   (+) Stop the TIM Input Capture and disable interrupt.
+   (+) Start the TIM Input Capture and enable DMA transfer.
+   (+) Stop the TIM Input Capture and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Input Capture Time base according to the specified
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
+  * @param  htim TIM Input Capture handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->IC_MspInitCallback == NULL)
+    {
+      htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->IC_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_IC_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Init the base time for the input capture */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM peripheral
+  * @param  htim TIM Input Capture handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->IC_MspDeInitCallback == NULL)
+  {
+    htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->IC_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+  HAL_TIM_IC_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Input Capture MSP.
+  * @param  htim TIM Input Capture handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Input Capture MSP.
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Input Capture measurement.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Enable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Input Capture measurement.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Input Capture measurement in interrupt mode.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Enable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      break;
+  }
+  /* Enable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Input Capture measurement in interrupt mode.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Disable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Input Capture measurement in DMA mode.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  pData The destination Buffer address.
+  * @param  Length The length of data to be transferred from TIM peripheral to memory.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if ((pData == NULL) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 2  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 3  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 4  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Enable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Input Capture measurement in DMA mode.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3  DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4  DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Disable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
+  *  @brief    TIM One Pulse functions
+  *
+@verbatim
+  ==============================================================================
+                        ##### TIM One Pulse functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM One Pulse.
+    (+) De-initialize the TIM One Pulse.
+    (+) Start the TIM One Pulse.
+    (+) Stop the TIM One Pulse.
+    (+) Start the TIM One Pulse and enable interrupt.
+    (+) Stop the TIM One Pulse and disable interrupt.
+    (+) Start the TIM One Pulse and enable DMA transfer.
+    (+) Stop the TIM One Pulse and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM One Pulse Time Base according to the specified
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
+  * @param  htim TIM One Pulse handle
+  * @param  OnePulseMode Select the One pulse mode.
+  *         This parameter can be one of the following values:
+  *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
+  *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_OPM_MODE(OnePulseMode));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->OnePulse_MspInitCallback == NULL)
+    {
+      htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->OnePulse_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_OnePulse_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Configure the Time base in the One Pulse Mode */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Reset the OPM Bit */
+  htim->Instance->CR1 &= ~TIM_CR1_OPM;
+
+  /* Configure the OPM Mode */
+  htim->Instance->CR1 |= OnePulseMode;
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM One Pulse
+  * @param  htim TIM One Pulse handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->OnePulse_MspDeInitCallback == NULL)
+  {
+    htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->OnePulse_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIM_OnePulse_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM One Pulse MSP.
+  * @param  htim TIM One Pulse handle
+  * @retval None
+  */
+__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OnePulse_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM One Pulse MSP.
+  * @param  htim TIM One Pulse handle
+  * @retval None
+  */
+__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation.
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Enable the Capture compare and the Input Capture channels
+    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+    in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+
+    No need to enable the counter, it's enabled automatically by hardware
+    (the counter starts in response to a stimulus and generate a pulse */
+
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM One Pulse signal generation.
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channels to be disable
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Disable the Capture compare and the Input Capture channels
+  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+  in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation in interrupt mode.
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Enable the Capture compare and the Input Capture channels
+    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+    in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+
+    No need to enable the counter, it's enabled automatically by hardware
+    (the counter starts in response to a stimulus and generate a pulse */
+
+  /* Enable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+  /* Enable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM One Pulse signal generation in interrupt mode.
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Disable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+  /* Disable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+
+  /* Disable the Capture compare and the Input Capture channels
+  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+  in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
+  *  @brief    TIM Encoder functions
+  *
+@verbatim
+  ==============================================================================
+                          ##### TIM Encoder functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM Encoder.
+    (+) De-initialize the TIM Encoder.
+    (+) Start the TIM Encoder.
+    (+) Stop the TIM Encoder.
+    (+) Start the TIM Encoder and enable interrupt.
+    (+) Stop the TIM Encoder and disable interrupt.
+    (+) Start the TIM Encoder and enable DMA transfer.
+    (+) Stop the TIM Encoder and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Encoder Interface and initialize the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
+  * @note   Encoder mode and External clock mode 2 are not compatible and must not be selected together
+  *         Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
+  *         using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
+  * @param  htim TIM Encoder Interface handle
+  * @param  sConfig TIM Encoder Interface configuration structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef *sConfig)
+{
+  uint32_t tmpsmcr;
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+  assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
+  assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
+  assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
+  assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
+  assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
+  assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+  assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->Encoder_MspInitCallback == NULL)
+    {
+      htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->Encoder_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_Encoder_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Reset the SMS and ECE bits */
+  htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
+
+  /* Configure the Time base in the Encoder Mode */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = htim->Instance->SMCR;
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmr1 = htim->Instance->CCMR1;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = htim->Instance->CCER;
+
+  /* Set the encoder Mode */
+  tmpsmcr |= sConfig->EncoderMode;
+
+  /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+  tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
+  tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
+
+  /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
+  tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
+  tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
+  tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
+  tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
+
+  /* Set the TI1 and the TI2 Polarities */
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
+  tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
+  tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
+
+  /* Write to TIMx SMCR */
+  htim->Instance->SMCR = tmpsmcr;
+
+  /* Write to TIMx CCMR1 */
+  htim->Instance->CCMR1 = tmpccmr1;
+
+  /* Write to TIMx CCER */
+  htim->Instance->CCER = tmpccer;
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  DeInitializes the TIM Encoder interface
+  * @param  htim TIM Encoder Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->Encoder_MspDeInitCallback == NULL)
+  {
+    htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->Encoder_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIM_Encoder_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Encoder Interface MSP.
+  * @param  htim TIM Encoder Interface handle
+  * @retval None
+  */
+__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_Encoder_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Encoder Interface MSP.
+  * @param  htim TIM Encoder Interface handle
+  * @retval None
+  */
+__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Encoder Interface.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Enable the encoder interface channels */
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      break;
+    }
+
+    default :
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      break;
+    }
+  }
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Encoder Interface.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channels 1 and 2
+    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+      break;
+    }
+
+    default :
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+      break;
+    }
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Encoder Interface in interrupt mode.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Enable the encoder interface channels */
+  /* Enable the capture compare Interrupts 1 and/or 2 */
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    default :
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+  }
+
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Encoder Interface in interrupt mode.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channels 1 and 2
+    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+  if (Channel == TIM_CHANNEL_1)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare Interrupts 1 */
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare Interrupts 2 */
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+  }
+  else
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare Interrupts 1 and 2 */
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Encoder Interface in DMA mode.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @param  pData1 The destination Buffer address for IC1.
+  * @param  pData2 The destination Buffer address for IC2.
+  * @param  Length The length of data to be transferred from TIM peripheral to memory.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
+                                            uint32_t *pData2, uint16_t Length)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Input Capture DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+
+      /* Enable the Peripheral */
+      __HAL_TIM_ENABLE(htim);
+
+      /* Enable the Capture compare channel */
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Input Capture  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+
+      /* Enable the Peripheral */
+      __HAL_TIM_ENABLE(htim);
+
+      /* Enable the Capture compare channel */
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      break;
+    }
+
+    case TIM_CHANNEL_ALL:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the Peripheral */
+      __HAL_TIM_ENABLE(htim);
+
+      /* Enable the Capture compare channel */
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+      /* Enable the TIM Input Capture  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      /* Enable the TIM Input Capture  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    default:
+      break;
+  }
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Encoder Interface in DMA mode.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channels 1 and 2
+    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+  if (Channel == TIM_CHANNEL_1)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare DMA Request 1 */
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare DMA Request 2 */
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+  }
+  else
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare DMA Request 1 and 2 */
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
+  *  @brief    TIM IRQ handler management
+  *
+@verbatim
+  ==============================================================================
+                        ##### IRQ handler management #####
+  ==============================================================================
+  [..]
+    This section provides Timer IRQ handler function.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  This function handles TIM interrupts requests.
+  * @param  htim TIM  handle
+  * @retval None
+  */
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
+{
+  /* Capture compare 1 event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
+    {
+      {
+        __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
+        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+        /* Input capture event */
+        if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
+        {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+          htim->IC_CaptureCallback(htim);
+#else
+          HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+        }
+        /* Output compare event */
+        else
+        {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+          htim->OC_DelayElapsedCallback(htim);
+          htim->PWM_PulseFinishedCallback(htim);
+#else
+          HAL_TIM_OC_DelayElapsedCallback(htim);
+          HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+        }
+        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+      }
+    }
+  }
+  /* Capture compare 2 event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+      /* Input capture event */
+      if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->IC_CaptureCallback(htim);
+#else
+        HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      /* Output compare event */
+      else
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->OC_DelayElapsedCallback(htim);
+        htim->PWM_PulseFinishedCallback(htim);
+#else
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+    }
+  }
+  /* Capture compare 3 event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+      /* Input capture event */
+      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->IC_CaptureCallback(htim);
+#else
+        HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      /* Output compare event */
+      else
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->OC_DelayElapsedCallback(htim);
+        htim->PWM_PulseFinishedCallback(htim);
+#else
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+    }
+  }
+  /* Capture compare 4 event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+      /* Input capture event */
+      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->IC_CaptureCallback(htim);
+#else
+        HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      /* Output compare event */
+      else
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->OC_DelayElapsedCallback(htim);
+        htim->PWM_PulseFinishedCallback(htim);
+#else
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+    }
+  }
+  /* TIM Update event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->PeriodElapsedCallback(htim);
+#else
+      HAL_TIM_PeriodElapsedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM Break input event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->BreakCallback(htim);
+#else
+      HAL_TIMEx_BreakCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM Break2 input event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->Break2Callback(htim);
+#else
+      HAL_TIMEx_Break2Callback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM Trigger detection event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->TriggerCallback(htim);
+#else
+      HAL_TIM_TriggerCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM commutation event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->CommutationCallback(htim);
+#else
+      HAL_TIMEx_CommutCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
+  *  @brief    TIM Peripheral Control functions
+  *
+@verbatim
+  ==============================================================================
+                   ##### Peripheral Control functions #####
+  ==============================================================================
+ [..]
+   This section provides functions allowing to:
+      (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
+      (+) Configure External Clock source.
+      (+) Configure Complementary channels, break features and dead time.
+      (+) Configure Master and the Slave synchronization.
+      (+) Configure the DMA Burst Mode.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the TIM Output Compare Channels according to the specified
+  *         parameters in the TIM_OC_InitTypeDef.
+  * @param  htim TIM Output Compare handle
+  * @param  sConfig TIM Output Compare configuration structure
+  * @param  Channel TIM Channels to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
+                                           TIM_OC_InitTypeDef *sConfig,
+                                           uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CHANNELS(Channel));
+  assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
+  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 1 in Output Compare */
+      TIM_OC1_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 2 in Output Compare */
+      TIM_OC2_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 3 in Output Compare */
+      TIM_OC3_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 4 in Output Compare */
+      TIM_OC4_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    case TIM_CHANNEL_5:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 5 in Output Compare */
+      TIM_OC5_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    case TIM_CHANNEL_6:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 6 in Output Compare */
+      TIM_OC6_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Input Capture Channels according to the specified
+  *         parameters in the TIM_IC_InitTypeDef.
+  * @param  htim TIM IC handle
+  * @param  sConfig TIM Input Capture configuration structure
+  * @param  Channel TIM Channel to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
+  assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
+  assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  if (Channel == TIM_CHANNEL_1)
+  {
+    /* TI1 Configuration */
+    TIM_TI1_SetConfig(htim->Instance,
+                      sConfig->ICPolarity,
+                      sConfig->ICSelection,
+                      sConfig->ICFilter);
+
+    /* Reset the IC1PSC Bits */
+    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+
+    /* Set the IC1PSC value */
+    htim->Instance->CCMR1 |= sConfig->ICPrescaler;
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    /* TI2 Configuration */
+    assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+    TIM_TI2_SetConfig(htim->Instance,
+                      sConfig->ICPolarity,
+                      sConfig->ICSelection,
+                      sConfig->ICFilter);
+
+    /* Reset the IC2PSC Bits */
+    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+    /* Set the IC2PSC value */
+    htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
+  }
+  else if (Channel == TIM_CHANNEL_3)
+  {
+    /* TI3 Configuration */
+    assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+    TIM_TI3_SetConfig(htim->Instance,
+                      sConfig->ICPolarity,
+                      sConfig->ICSelection,
+                      sConfig->ICFilter);
+
+    /* Reset the IC3PSC Bits */
+    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
+
+    /* Set the IC3PSC value */
+    htim->Instance->CCMR2 |= sConfig->ICPrescaler;
+  }
+  else
+  {
+    /* TI4 Configuration */
+    assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+    TIM_TI4_SetConfig(htim->Instance,
+                      sConfig->ICPolarity,
+                      sConfig->ICSelection,
+                      sConfig->ICFilter);
+
+    /* Reset the IC4PSC Bits */
+    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
+
+    /* Set the IC4PSC value */
+    htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
+  }
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM PWM  channels according to the specified
+  *         parameters in the TIM_OC_InitTypeDef.
+  * @param  htim TIM PWM handle
+  * @param  sConfig TIM PWM configuration structure
+  * @param  Channel TIM Channels to be configured
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
+                                            TIM_OC_InitTypeDef *sConfig,
+                                            uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CHANNELS(Channel));
+  assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
+  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+  assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 1 in PWM mode */
+      TIM_OC1_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel1 */
+      htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
+      htim->Instance->CCMR1 |= sConfig->OCFastMode;
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 2 in PWM mode */
+      TIM_OC2_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel2 */
+      htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
+      htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 3 in PWM mode */
+      TIM_OC3_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel3 */
+      htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
+      htim->Instance->CCMR2 |= sConfig->OCFastMode;
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 4 in PWM mode */
+      TIM_OC4_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel4 */
+      htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
+      htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
+      break;
+    }
+
+    case TIM_CHANNEL_5:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 5 in PWM mode */
+      TIM_OC5_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel5*/
+      htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
+      htim->Instance->CCMR3 |= sConfig->OCFastMode;
+      break;
+    }
+
+    case TIM_CHANNEL_6:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 6 in PWM mode */
+      TIM_OC6_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel6 */
+      htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
+      htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM One Pulse Channels according to the specified
+  *         parameters in the TIM_OnePulse_InitTypeDef.
+  * @param  htim TIM One Pulse handle
+  * @param  sConfig TIM One Pulse configuration structure
+  * @param  OutputChannel TIM output channel to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @param  InputChannel TIM input Channel to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @note  To output a waveform with a minimum delay user can enable the fast
+  *        mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
+  *        output is forced in response to the edge detection on TIx input,
+  *        without taking in account the comparison.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef *sConfig,
+                                                 uint32_t OutputChannel,  uint32_t InputChannel)
+{
+  TIM_OC_InitTypeDef temp1;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
+  assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
+
+  if (OutputChannel != InputChannel)
+  {
+    /* Process Locked */
+    __HAL_LOCK(htim);
+
+    htim->State = HAL_TIM_STATE_BUSY;
+
+    /* Extract the Output compare configuration from sConfig structure */
+    temp1.OCMode = sConfig->OCMode;
+    temp1.Pulse = sConfig->Pulse;
+    temp1.OCPolarity = sConfig->OCPolarity;
+    temp1.OCNPolarity = sConfig->OCNPolarity;
+    temp1.OCIdleState = sConfig->OCIdleState;
+    temp1.OCNIdleState = sConfig->OCNIdleState;
+
+    switch (OutputChannel)
+    {
+      case TIM_CHANNEL_1:
+      {
+        assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+        TIM_OC1_SetConfig(htim->Instance, &temp1);
+        break;
+      }
+      case TIM_CHANNEL_2:
+      {
+        assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+        TIM_OC2_SetConfig(htim->Instance, &temp1);
+        break;
+      }
+      default:
+        break;
+    }
+
+    switch (InputChannel)
+    {
+      case TIM_CHANNEL_1:
+      {
+        assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+        TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
+                          sConfig->ICSelection, sConfig->ICFilter);
+
+        /* Reset the IC1PSC Bits */
+        htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+
+        /* Select the Trigger source */
+        htim->Instance->SMCR &= ~TIM_SMCR_TS;
+        htim->Instance->SMCR |= TIM_TS_TI1FP1;
+
+        /* Select the Slave Mode */
+        htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+        htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+        break;
+      }
+      case TIM_CHANNEL_2:
+      {
+        assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+        TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
+                          sConfig->ICSelection, sConfig->ICFilter);
+
+        /* Reset the IC2PSC Bits */
+        htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+        /* Select the Trigger source */
+        htim->Instance->SMCR &= ~TIM_SMCR_TS;
+        htim->Instance->SMCR |= TIM_TS_TI2FP2;
+
+        /* Select the Slave Mode */
+        htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+        htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+        break;
+      }
+
+      default:
+        break;
+    }
+
+    htim->State = HAL_TIM_STATE_READY;
+
+    __HAL_UNLOCK(htim);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data write
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMABASE_CR1
+  *            @arg TIM_DMABASE_CR2
+  *            @arg TIM_DMABASE_SMCR
+  *            @arg TIM_DMABASE_DIER
+  *            @arg TIM_DMABASE_SR
+  *            @arg TIM_DMABASE_EGR
+  *            @arg TIM_DMABASE_CCMR1
+  *            @arg TIM_DMABASE_CCMR2
+  *            @arg TIM_DMABASE_CCER
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
+  *            @arg TIM_DMABASE_ARR
+  *            @arg TIM_DMABASE_RCR
+  *            @arg TIM_DMABASE_CCR1
+  *            @arg TIM_DMABASE_CCR2
+  *            @arg TIM_DMABASE_CCR3
+  *            @arg TIM_DMABASE_CCR4
+  *            @arg TIM_DMABASE_BDTR
+  *            @arg TIM_DMABASE_CCMR3 
+  *            @arg TIM_DMABASE_CCR5 
+  *            @arg TIM_DMABASE_CCR6 
+  *            @arg TIM_DMABASE_AF1  
+  *            @arg TIM_DMABASE_AF2  
+  *            @arg TIM_DMABASE_TISEL
+  *         
+  * @param  BurstRequestSrc TIM DMA Request sources
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+  * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                              uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t  BurstLength)
+{
+  return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+                                          ((BurstLength) >> 8U) + 1U);
+}
+
+/**
+  * @brief  Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA will start the Data write
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMABASE_CR1
+  *            @arg TIM_DMABASE_CR2
+  *            @arg TIM_DMABASE_SMCR
+  *            @arg TIM_DMABASE_DIER
+  *            @arg TIM_DMABASE_SR
+  *            @arg TIM_DMABASE_EGR
+  *            @arg TIM_DMABASE_CCMR1
+  *            @arg TIM_DMABASE_CCMR2
+  *            @arg TIM_DMABASE_CCER
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
+  *            @arg TIM_DMABASE_ARR
+  *            @arg TIM_DMABASE_RCR
+  *            @arg TIM_DMABASE_CCR1
+  *            @arg TIM_DMABASE_CCR2
+  *            @arg TIM_DMABASE_CCR3
+  *            @arg TIM_DMABASE_CCR4
+  *            @arg TIM_DMABASE_BDTR
+  *            @arg TIM_DMABASE_CCMR3 
+  *            @arg TIM_DMABASE_CCR5 
+  *            @arg TIM_DMABASE_CCR6 
+  *            @arg TIM_DMABASE_AF1  
+  *            @arg TIM_DMABASE_AF2  
+  *            @arg TIM_DMABASE_TISEL
+  *         
+  * @param  BurstRequestSrc TIM DMA Request sources
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+  * @param  DataLength Data length. This parameter can be one value
+  *         between 1 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                                   uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
+                                                   uint32_t  BurstLength,  uint32_t  DataLength)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+  assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+  assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if ((BurstBuffer == NULL) && (BurstLength > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+  switch (BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      /* Set the DMA Period elapsed callbacks */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC4:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_COM:
+    {
+      /* Set the DMA commutation callbacks */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_TRIGGER:
+    {
+      /* Set the DMA trigger callbacks */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    default:
+      break;
+  }
+
+  /* Configure the DMA Burst Mode */
+  htim->Instance->DCR = (BurstBaseAddress | BurstLength);
+  /* Enable the TIM DMA Request */
+  __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM DMA Burst mode
+  * @param  htim TIM handle
+  * @param  BurstRequestSrc TIM DMA Request sources to disable
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+
+  /* Abort the DMA transfer (at least disable the DMA stream) */
+  switch (BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+      break;
+    }
+    case TIM_DMA_CC1:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+    case TIM_DMA_CC2:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+    case TIM_DMA_CC3:
+    {
+      status =  HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+    case TIM_DMA_CC4:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+    case TIM_DMA_COM:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+      break;
+    }
+    case TIM_DMA_TRIGGER:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+      break;
+    }
+    default:
+      break;
+  }
+
+  if (HAL_OK == status)
+  {
+    /* Disable the TIM Update DMA request */
+    __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMABASE_CR1
+  *            @arg TIM_DMABASE_CR2
+  *            @arg TIM_DMABASE_SMCR
+  *            @arg TIM_DMABASE_DIER
+  *            @arg TIM_DMABASE_SR
+  *            @arg TIM_DMABASE_EGR
+  *            @arg TIM_DMABASE_CCMR1
+  *            @arg TIM_DMABASE_CCMR2
+  *            @arg TIM_DMABASE_CCER
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
+  *            @arg TIM_DMABASE_ARR
+  *            @arg TIM_DMABASE_RCR
+  *            @arg TIM_DMABASE_CCR1
+  *            @arg TIM_DMABASE_CCR2
+  *            @arg TIM_DMABASE_CCR3
+  *            @arg TIM_DMABASE_CCR4
+  *            @arg TIM_DMABASE_BDTR
+  *            @arg TIM_DMABASE_CCMR3 
+  *            @arg TIM_DMABASE_CCR5 
+  *            @arg TIM_DMABASE_CCR6 
+  *            @arg TIM_DMABASE_AF1  
+  *            @arg TIM_DMABASE_AF2  
+  *            @arg TIM_DMABASE_TISEL
+  *         
+  * @param  BurstRequestSrc TIM DMA Request sources
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+  * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                             uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength)
+{
+  return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+                                         ((BurstLength) >> 8U) + 1U);
+}
+
+/**
+  * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMABASE_CR1
+  *            @arg TIM_DMABASE_CR2
+  *            @arg TIM_DMABASE_SMCR
+  *            @arg TIM_DMABASE_DIER
+  *            @arg TIM_DMABASE_SR
+  *            @arg TIM_DMABASE_EGR
+  *            @arg TIM_DMABASE_CCMR1
+  *            @arg TIM_DMABASE_CCMR2
+  *            @arg TIM_DMABASE_CCER
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
+  *            @arg TIM_DMABASE_ARR
+  *            @arg TIM_DMABASE_RCR
+  *            @arg TIM_DMABASE_CCR1
+  *            @arg TIM_DMABASE_CCR2
+  *            @arg TIM_DMABASE_CCR3
+  *            @arg TIM_DMABASE_CCR4
+  *            @arg TIM_DMABASE_BDTR
+  *            @arg TIM_DMABASE_CCMR3 
+  *            @arg TIM_DMABASE_CCR5 
+  *            @arg TIM_DMABASE_CCR6 
+  *            @arg TIM_DMABASE_AF1  
+  *            @arg TIM_DMABASE_AF2  
+  *            @arg TIM_DMABASE_TISEL
+  *         
+  * @param  BurstRequestSrc TIM DMA Request sources
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+  * @param  DataLength Data length. This parameter can be one value
+  *         between 1 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                                  uint32_t BurstRequestSrc, uint32_t  *BurstBuffer,
+                                                  uint32_t  BurstLength, uint32_t  DataLength)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+  assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+  assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if ((BurstBuffer == NULL) && (BurstLength > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+  switch (BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      /* Set the DMA Period elapsed callbacks */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC1:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC2:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC3:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC4:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_COM:
+    {
+      /* Set the DMA commutation callbacks */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_TRIGGER:
+    {
+      /* Set the DMA trigger callbacks */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    default:
+      break;
+  }
+
+  /* Configure the DMA Burst Mode */
+  htim->Instance->DCR = (BurstBaseAddress | BurstLength);
+
+  /* Enable the TIM DMA Request */
+  __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the DMA burst reading
+  * @param  htim TIM handle
+  * @param  BurstRequestSrc TIM DMA Request sources to disable.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+
+  /* Abort the DMA transfer (at least disable the DMA stream) */
+  switch (BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+      break;
+    }
+    case TIM_DMA_CC1:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+    case TIM_DMA_CC2:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+    case TIM_DMA_CC3:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+    case TIM_DMA_CC4:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+    case TIM_DMA_COM:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+      break;
+    }
+    case TIM_DMA_TRIGGER:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+      break;
+    }
+    default:
+      break;
+  }
+
+  if (HAL_OK == status)
+  {
+    /* Disable the TIM Update DMA request */
+    __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Generate a software event
+  * @param  htim TIM handle
+  * @param  EventSource specifies the event source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
+  *            @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
+  *            @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
+  *            @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
+  *            @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
+  *            @arg TIM_EVENTSOURCE_COM: Timer COM event source
+  *            @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
+  *            @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
+  *            @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
+  * @note   Basic timers can only generate an update event.
+  * @note   TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
+  * @note   TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant
+  *         only for timer instances supporting break input(s).
+  * @retval HAL status
+  */
+
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_EVENT_SOURCE(EventSource));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  /* Change the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Set the event sources */
+  htim->Instance->EGR = EventSource;
+
+  /* Change the TIM state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the OCRef clear feature
+  * @param  htim TIM handle
+  * @param  sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
+  *         contains the OCREF clear feature and parameters for the TIM peripheral.
+  * @param  Channel specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1
+  *            @arg TIM_CHANNEL_2: TIM Channel 2
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  *            @arg TIM_CHANNEL_4: TIM Channel 4
+  *            @arg TIM_CHANNEL_5: TIM Channel 5
+  *            @arg TIM_CHANNEL_6: TIM Channel 6
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
+                                           TIM_ClearInputConfigTypeDef *sClearInputConfig,
+                                           uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  switch (sClearInputConfig->ClearInputSource)
+  {
+    case TIM_CLEARINPUTSOURCE_NONE:
+    {
+      /* Clear the OCREF clear selection bit and the the ETR Bits */
+      CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
+      break;
+    }
+
+    case TIM_CLEARINPUTSOURCE_ETR:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
+      assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
+      assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
+
+      /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
+      if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
+      {
+        htim->State = HAL_TIM_STATE_READY;
+        __HAL_UNLOCK(htim);
+        return HAL_ERROR;
+      }
+
+      TIM_ETR_SetConfig(htim->Instance,
+                        sClearInputConfig->ClearInputPrescaler,
+                        sClearInputConfig->ClearInputPolarity,
+                        sClearInputConfig->ClearInputFilter);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+      {
+        /* Enable the OCREF clear feature for Channel 1 */
+        SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
+      }
+      else
+      {
+        /* Disable the OCREF clear feature for Channel 1 */
+        CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
+      }
+      break;
+    }
+    case TIM_CHANNEL_2:
+    {
+      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+      {
+        /* Enable the OCREF clear feature for Channel 2 */
+        SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
+      }
+      else
+      {
+        /* Disable the OCREF clear feature for Channel 2 */
+        CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
+      }
+      break;
+    }
+    case TIM_CHANNEL_3:
+    {
+      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+      {
+        /* Enable the OCREF clear feature for Channel 3 */
+        SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
+      }
+      else
+      {
+        /* Disable the OCREF clear feature for Channel 3 */
+        CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
+      }
+      break;
+    }
+    case TIM_CHANNEL_4:
+    {
+      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+      {
+        /* Enable the OCREF clear feature for Channel 4 */
+        SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
+      }
+      else
+      {
+        /* Disable the OCREF clear feature for Channel 4 */
+        CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
+      }
+      break;
+    }
+    case TIM_CHANNEL_5:
+    {
+      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+      {
+        /* Enable the OCREF clear feature for Channel 5 */
+        SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
+      }
+      else
+      {
+        /* Disable the OCREF clear feature for Channel 5 */
+        CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
+      }
+      break;
+    }
+    case TIM_CHANNEL_6:
+    {
+      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+      {
+        /* Enable the OCREF clear feature for Channel 6 */
+        SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
+      }
+      else
+      {
+        /* Disable the OCREF clear feature for Channel 6 */
+        CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
+      }
+      break;
+    }
+    default:
+      break;
+  }
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief   Configures the clock source to be used
+  * @param  htim TIM handle
+  * @param  sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
+  *         contains the clock source information for the TIM peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
+{
+  uint32_t tmpsmcr;
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
+
+  /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
+  tmpsmcr = htim->Instance->SMCR;
+  tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+  htim->Instance->SMCR = tmpsmcr;
+
+  switch (sClockSourceConfig->ClockSource)
+  {
+    case TIM_CLOCKSOURCE_INTERNAL:
+    {
+      assert_param(IS_TIM_INSTANCE(htim->Instance));
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_ETRMODE1:
+    {
+      /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
+      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
+
+      /* Check ETR input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      /* Configure the ETR Clock source */
+      TIM_ETR_SetConfig(htim->Instance,
+                        sClockSourceConfig->ClockPrescaler,
+                        sClockSourceConfig->ClockPolarity,
+                        sClockSourceConfig->ClockFilter);
+
+      /* Select the External clock mode1 and the ETRF trigger */
+      tmpsmcr = htim->Instance->SMCR;
+      tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
+      /* Write to TIMx SMCR */
+      htim->Instance->SMCR = tmpsmcr;
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_ETRMODE2:
+    {
+      /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
+      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
+
+      /* Check ETR input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      /* Configure the ETR Clock source */
+      TIM_ETR_SetConfig(htim->Instance,
+                        sClockSourceConfig->ClockPrescaler,
+                        sClockSourceConfig->ClockPolarity,
+                        sClockSourceConfig->ClockFilter);
+      /* Enable the External clock mode2 */
+      htim->Instance->SMCR |= TIM_SMCR_ECE;
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_TI1:
+    {
+      /* Check whether or not the timer instance supports external clock mode 1 */
+      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+      /* Check TI1 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI1_ConfigInputStage(htim->Instance,
+                               sClockSourceConfig->ClockPolarity,
+                               sClockSourceConfig->ClockFilter);
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_TI2:
+    {
+      /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
+      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+      /* Check TI2 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI2_ConfigInputStage(htim->Instance,
+                               sClockSourceConfig->ClockPolarity,
+                               sClockSourceConfig->ClockFilter);
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_TI1ED:
+    {
+      /* Check whether or not the timer instance supports external clock mode 1 */
+      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+      /* Check TI1 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI1_ConfigInputStage(htim->Instance,
+                               sClockSourceConfig->ClockPolarity,
+                               sClockSourceConfig->ClockFilter);
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_ITR0:
+    case TIM_CLOCKSOURCE_ITR1:
+    case TIM_CLOCKSOURCE_ITR2:
+    case TIM_CLOCKSOURCE_ITR3:
+    case TIM_CLOCKSOURCE_ITR4:
+    case TIM_CLOCKSOURCE_ITR5:
+    case TIM_CLOCKSOURCE_ITR6:
+    case TIM_CLOCKSOURCE_ITR7:
+    case TIM_CLOCKSOURCE_ITR8:
+    {
+      /* Check whether or not the timer instance supports internal trigger input */
+      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
+
+      TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
+      break;
+    }
+
+    default:
+      break;
+  }
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Selects the signal connected to the TI1 input: direct from CH1_input
+  *         or a XOR combination between CH1_input, CH2_input & CH3_input
+  * @param  htim TIM handle.
+  * @param  TI1_Selection Indicate whether or not channel 1 is connected to the
+  *         output of a XOR gate.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
+  *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
+  *            pins are connected to the TI1 input (XOR combination)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
+{
+  uint32_t tmpcr2;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = htim->Instance->CR2;
+
+  /* Reset the TI1 selection */
+  tmpcr2 &= ~TIM_CR2_TI1S;
+
+  /* Set the TI1 selection */
+  tmpcr2 |= TI1_Selection;
+
+  /* Write to TIMxCR2 */
+  htim->Instance->CR2 = tmpcr2;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the TIM in Slave mode
+  * @param  htim TIM handle.
+  * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
+  *         contains the selected trigger (internal trigger input, filtered
+  *         timer input or external trigger input) and the Slave mode
+  *         (Disable, Reset, Gated, Trigger, External clock mode 1).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+  assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
+  {
+    htim->State = HAL_TIM_STATE_READY;
+    __HAL_UNLOCK(htim);
+    return HAL_ERROR;
+  }
+
+  /* Disable Trigger Interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
+
+  /* Disable Trigger DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the TIM in Slave mode in interrupt mode
+  * @param  htim TIM handle.
+  * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
+  *         contains the selected trigger (internal trigger input, filtered
+  *         timer input or external trigger input) and the Slave mode
+  *         (Disable, Reset, Gated, Trigger, External clock mode 1).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
+                                                TIM_SlaveConfigTypeDef *sSlaveConfig)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+  assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
+  {
+    htim->State = HAL_TIM_STATE_READY;
+    __HAL_UNLOCK(htim);
+    return HAL_ERROR;
+  }
+
+  /* Enable Trigger Interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
+
+  /* Disable Trigger DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Read the captured value from Capture Compare unit
+  * @param  htim TIM handle.
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval Captured value
+  */
+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpreg = 0U;
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+      /* Return the capture 1 value */
+      tmpreg =  htim->Instance->CCR1;
+
+      break;
+    }
+    case TIM_CHANNEL_2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+      /* Return the capture 2 value */
+      tmpreg =   htim->Instance->CCR2;
+
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+      /* Return the capture 3 value */
+      tmpreg =   htim->Instance->CCR3;
+
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+      /* Return the capture 4 value */
+      tmpreg =   htim->Instance->CCR4;
+
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  return tmpreg;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
+  *  @brief    TIM Callbacks functions
+  *
+@verbatim
+  ==============================================================================
+                        ##### TIM Callbacks functions #####
+  ==============================================================================
+ [..]
+   This section provides TIM callback functions:
+   (+) TIM Period elapsed callback
+   (+) TIM Output Compare callback
+   (+) TIM Input capture callback
+   (+) TIM Trigger callback
+   (+) TIM Error callback
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Period elapsed callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Period elapsed half complete callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Output Compare callback in non-blocking mode
+  * @param  htim TIM OC handle
+  * @retval None
+  */
+__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Input Capture callback in non-blocking mode
+  * @param  htim TIM IC handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_CaptureCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Input Capture half complete callback in non-blocking mode
+  * @param  htim TIM IC handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  PWM Pulse finished callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  PWM Pulse finished half complete callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Hall Trigger detection callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_TriggerCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Hall Trigger detection half complete callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Timer error callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_ErrorCallback could be implemented in the user file
+   */
+}
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User TIM callback to be used instead of the weak predefined callback
+  * @param htim tim handle
+  * @param CallbackID ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
+  *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
+  *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
+  *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
+  *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
+  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
+  *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
+  *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
+  *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
+  *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
+  *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
+  *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
+  *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
+  *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
+  *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
+  *          @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
+  *          @param pCallback pointer to the callback function
+  *          @retval status
+  */
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
+                                           pTIM_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(htim);
+
+  if (htim->State == HAL_TIM_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_TIM_BASE_MSPINIT_CB_ID :
+        htim->Base_MspInitCallback                 = pCallback;
+        break;
+
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+        htim->Base_MspDeInitCallback               = pCallback;
+        break;
+
+      case HAL_TIM_IC_MSPINIT_CB_ID :
+        htim->IC_MspInitCallback                   = pCallback;
+        break;
+
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :
+        htim->IC_MspDeInitCallback                 = pCallback;
+        break;
+
+      case HAL_TIM_OC_MSPINIT_CB_ID :
+        htim->OC_MspInitCallback                   = pCallback;
+        break;
+
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :
+        htim->OC_MspDeInitCallback                 = pCallback;
+        break;
+
+      case HAL_TIM_PWM_MSPINIT_CB_ID :
+        htim->PWM_MspInitCallback                  = pCallback;
+        break;
+
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+        htim->PWM_MspDeInitCallback                = pCallback;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+        htim->OnePulse_MspInitCallback             = pCallback;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+        htim->OnePulse_MspDeInitCallback           = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+        htim->Encoder_MspInitCallback              = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+        htim->Encoder_MspDeInitCallback            = pCallback;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+        htim->HallSensor_MspInitCallback           = pCallback;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+        htim->HallSensor_MspDeInitCallback         = pCallback;
+        break;
+
+      case HAL_TIM_PERIOD_ELAPSED_CB_ID :
+        htim->PeriodElapsedCallback                = pCallback;
+        break;
+
+      case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
+        htim->PeriodElapsedHalfCpltCallback        = pCallback;
+        break;
+
+      case HAL_TIM_TRIGGER_CB_ID :
+        htim->TriggerCallback                      = pCallback;
+        break;
+
+      case HAL_TIM_TRIGGER_HALF_CB_ID :
+        htim->TriggerHalfCpltCallback              = pCallback;
+        break;
+
+      case HAL_TIM_IC_CAPTURE_CB_ID :
+        htim->IC_CaptureCallback                   = pCallback;
+        break;
+
+      case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
+        htim->IC_CaptureHalfCpltCallback           = pCallback;
+        break;
+
+      case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
+        htim->OC_DelayElapsedCallback              = pCallback;
+        break;
+
+      case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
+        htim->PWM_PulseFinishedCallback            = pCallback;
+        break;
+
+      case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
+        htim->PWM_PulseFinishedHalfCpltCallback    = pCallback;
+        break;
+
+      case HAL_TIM_ERROR_CB_ID :
+        htim->ErrorCallback                        = pCallback;
+        break;
+
+      case HAL_TIM_COMMUTATION_CB_ID :
+        htim->CommutationCallback                  = pCallback;
+        break;
+
+      case HAL_TIM_COMMUTATION_HALF_CB_ID :
+        htim->CommutationHalfCpltCallback          = pCallback;
+        break;
+
+      case HAL_TIM_BREAK_CB_ID :
+        htim->BreakCallback                        = pCallback;
+        break;
+
+      case HAL_TIM_BREAK2_CB_ID :
+        htim->Break2Callback                       = pCallback;
+        break;
+
+      default :
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_TIM_BASE_MSPINIT_CB_ID :
+        htim->Base_MspInitCallback         = pCallback;
+        break;
+
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+        htim->Base_MspDeInitCallback       = pCallback;
+        break;
+
+      case HAL_TIM_IC_MSPINIT_CB_ID :
+        htim->IC_MspInitCallback           = pCallback;
+        break;
+
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :
+        htim->IC_MspDeInitCallback         = pCallback;
+        break;
+
+      case HAL_TIM_OC_MSPINIT_CB_ID :
+        htim->OC_MspInitCallback           = pCallback;
+        break;
+
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :
+        htim->OC_MspDeInitCallback         = pCallback;
+        break;
+
+      case HAL_TIM_PWM_MSPINIT_CB_ID :
+        htim->PWM_MspInitCallback          = pCallback;
+        break;
+
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+        htim->PWM_MspDeInitCallback        = pCallback;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+        htim->OnePulse_MspInitCallback     = pCallback;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+        htim->OnePulse_MspDeInitCallback   = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+        htim->Encoder_MspInitCallback      = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+        htim->Encoder_MspDeInitCallback    = pCallback;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+        htim->HallSensor_MspInitCallback   = pCallback;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+        htim->HallSensor_MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a TIM callback
+  *         TIM callback is redirected to the weak predefined callback
+  * @param htim tim handle
+  * @param CallbackID ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
+  *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
+  *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
+  *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
+  *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
+  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
+  *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
+  *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
+  *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
+  *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
+  *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
+  *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
+  *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
+  *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
+  *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
+  *          @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
+  *          @retval status
+  */
+HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(htim);
+
+  if (htim->State == HAL_TIM_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_TIM_BASE_MSPINIT_CB_ID :
+        htim->Base_MspInitCallback              = HAL_TIM_Base_MspInit;                      /* Legacy weak Base MspInit Callback */
+        break;
+
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+        htim->Base_MspDeInitCallback            = HAL_TIM_Base_MspDeInit;                    /* Legacy weak Base Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_IC_MSPINIT_CB_ID :
+        htim->IC_MspInitCallback                = HAL_TIM_IC_MspInit;                        /* Legacy weak IC Msp Init Callback */
+        break;
+
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :
+        htim->IC_MspDeInitCallback              = HAL_TIM_IC_MspDeInit;                      /* Legacy weak IC Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_OC_MSPINIT_CB_ID :
+        htim->OC_MspInitCallback                = HAL_TIM_OC_MspInit;                        /* Legacy weak OC Msp Init Callback */
+        break;
+
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :
+        htim->OC_MspDeInitCallback              = HAL_TIM_OC_MspDeInit;                      /* Legacy weak OC Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_PWM_MSPINIT_CB_ID :
+        htim->PWM_MspInitCallback               = HAL_TIM_PWM_MspInit;                       /* Legacy weak PWM Msp Init Callback */
+        break;
+
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+        htim->PWM_MspDeInitCallback             = HAL_TIM_PWM_MspDeInit;                     /* Legacy weak PWM Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+        htim->OnePulse_MspInitCallback          = HAL_TIM_OnePulse_MspInit;                  /* Legacy weak One Pulse Msp Init Callback */
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+        htim->OnePulse_MspDeInitCallback        = HAL_TIM_OnePulse_MspDeInit;                /* Legacy weak One Pulse Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+        htim->Encoder_MspInitCallback           = HAL_TIM_Encoder_MspInit;                   /* Legacy weak Encoder Msp Init Callback */
+        break;
+
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+        htim->Encoder_MspDeInitCallback         = HAL_TIM_Encoder_MspDeInit;                 /* Legacy weak Encoder Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+        htim->HallSensor_MspInitCallback        = HAL_TIMEx_HallSensor_MspInit;              /* Legacy weak Hall Sensor Msp Init Callback */
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+        htim->HallSensor_MspDeInitCallback      = HAL_TIMEx_HallSensor_MspDeInit;            /* Legacy weak Hall Sensor Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_PERIOD_ELAPSED_CB_ID :
+        htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;             /* Legacy weak Period Elapsed Callback */
+        break;
+
+      case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
+        htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;     /* Legacy weak Period Elapsed half complete Callback */
+        break;
+
+      case HAL_TIM_TRIGGER_CB_ID :
+        htim->TriggerCallback                   = HAL_TIM_TriggerCallback;                   /* Legacy weak Trigger Callback */
+        break;
+
+      case HAL_TIM_TRIGGER_HALF_CB_ID :
+        htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;           /* Legacy weak Trigger half complete Callback */
+        break;
+
+      case HAL_TIM_IC_CAPTURE_CB_ID :
+        htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;                /* Legacy weak IC Capture Callback */
+        break;
+
+      case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
+        htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;        /* Legacy weak IC Capture half complete Callback */
+        break;
+
+      case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
+        htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;           /* Legacy weak OC Delay Elapsed Callback */
+        break;
+
+      case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
+        htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;         /* Legacy weak PWM Pulse Finished Callback */
+        break;
+
+      case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
+        htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */
+        break;
+
+      case HAL_TIM_ERROR_CB_ID :
+        htim->ErrorCallback                     = HAL_TIM_ErrorCallback;                     /* Legacy weak Error Callback */
+        break;
+
+      case HAL_TIM_COMMUTATION_CB_ID :
+        htim->CommutationCallback               = HAL_TIMEx_CommutCallback;                  /* Legacy weak Commutation Callback */
+        break;
+
+      case HAL_TIM_COMMUTATION_HALF_CB_ID :
+        htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;          /* Legacy weak Commutation half complete Callback */
+        break;
+
+      case HAL_TIM_BREAK_CB_ID :
+        htim->BreakCallback                     = HAL_TIMEx_BreakCallback;                   /* Legacy weak Break Callback */
+        break;
+
+      case HAL_TIM_BREAK2_CB_ID :
+        htim->Break2Callback                    = HAL_TIMEx_Break2Callback;                  /* Legacy weak Break2 Callback */
+        break;
+
+      default :
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_TIM_BASE_MSPINIT_CB_ID :
+        htim->Base_MspInitCallback         = HAL_TIM_Base_MspInit;              /* Legacy weak Base MspInit Callback */
+        break;
+
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+        htim->Base_MspDeInitCallback       = HAL_TIM_Base_MspDeInit;            /* Legacy weak Base Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_IC_MSPINIT_CB_ID :
+        htim->IC_MspInitCallback           = HAL_TIM_IC_MspInit;                /* Legacy weak IC Msp Init Callback */
+        break;
+
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :
+        htim->IC_MspDeInitCallback         = HAL_TIM_IC_MspDeInit;              /* Legacy weak IC Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_OC_MSPINIT_CB_ID :
+        htim->OC_MspInitCallback           = HAL_TIM_OC_MspInit;                /* Legacy weak OC Msp Init Callback */
+        break;
+
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :
+        htim->OC_MspDeInitCallback         = HAL_TIM_OC_MspDeInit;              /* Legacy weak OC Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_PWM_MSPINIT_CB_ID :
+        htim->PWM_MspInitCallback          = HAL_TIM_PWM_MspInit;               /* Legacy weak PWM Msp Init Callback */
+        break;
+
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+        htim->PWM_MspDeInitCallback        = HAL_TIM_PWM_MspDeInit;             /* Legacy weak PWM Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+        htim->OnePulse_MspInitCallback     = HAL_TIM_OnePulse_MspInit;          /* Legacy weak One Pulse Msp Init Callback */
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+        htim->OnePulse_MspDeInitCallback   = HAL_TIM_OnePulse_MspDeInit;        /* Legacy weak One Pulse Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+        htim->Encoder_MspInitCallback      = HAL_TIM_Encoder_MspInit;           /* Legacy weak Encoder Msp Init Callback */
+        break;
+
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+        htim->Encoder_MspDeInitCallback    = HAL_TIM_Encoder_MspDeInit;         /* Legacy weak Encoder Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+        htim->HallSensor_MspInitCallback   = HAL_TIMEx_HallSensor_MspInit;      /* Legacy weak Hall Sensor Msp Init Callback */
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+        htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;    /* Legacy weak Hall Sensor Msp DeInit Callback */
+        break;
+
+      default :
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
+  *  @brief   TIM Peripheral State functions
+  *
+@verbatim
+  ==============================================================================
+                        ##### Peripheral State functions #####
+  ==============================================================================
+    [..]
+    This subsection permits to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the TIM Base handle state.
+  * @param  htim TIM Base handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM OC handle state.
+  * @param  htim TIM Output Compare handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM PWM handle state.
+  * @param  htim TIM handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM Input Capture handle state.
+  * @param  htim TIM IC handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM One Pulse Mode handle state.
+  * @param  htim TIM OPM handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM Encoder Mode handle state.
+  * @param  htim TIM Encoder Interface handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Private_Functions TIM Private Functions
+  * @{
+  */
+
+/**
+  * @brief  TIM DMA error callback
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMAError(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->ErrorCallback(htim);
+#else
+  HAL_TIM_ErrorCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Delay Pulse complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PWM_PulseFinishedCallback(htim);
+#else
+  HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Delay Pulse half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PWM_PulseFinishedHalfCpltCallback(htim);
+#else
+  HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Capture complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->IC_CaptureCallback(htim);
+#else
+  HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Capture half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->IC_CaptureHalfCpltCallback(htim);
+#else
+  HAL_TIM_IC_CaptureHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Period Elapse complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PeriodElapsedCallback(htim);
+#else
+  HAL_TIM_PeriodElapsedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Period Elapse half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PeriodElapsedHalfCpltCallback(htim);
+#else
+  HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Trigger callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->TriggerCallback(htim);
+#else
+  HAL_TIM_TriggerCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Trigger half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->TriggerHalfCpltCallback(htim);
+#else
+  HAL_TIM_TriggerHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  Time Base configuration
+  * @param  TIMx TIM peripheral
+  * @param  Structure TIM Base configuration structure
+  * @retval None
+  */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
+{
+  uint32_t tmpcr1;
+  tmpcr1 = TIMx->CR1;
+
+  /* Set TIM Time Base Unit parameters ---------------------------------------*/
+  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
+  {
+    /* Select the Counter Mode */
+    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
+    tmpcr1 |= Structure->CounterMode;
+  }
+
+  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
+  {
+    /* Set the clock division */
+    tmpcr1 &= ~TIM_CR1_CKD;
+    tmpcr1 |= (uint32_t)Structure->ClockDivision;
+  }
+
+  /* Set the auto-reload preload */
+  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
+
+  TIMx->CR1 = tmpcr1;
+
+  /* Set the Autoreload value */
+  TIMx->ARR = (uint32_t)Structure->Period ;
+
+  /* Set the Prescaler value */
+  TIMx->PSC = Structure->Prescaler;
+
+  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
+  {
+    /* Set the Repetition Counter value */
+    TIMx->RCR = Structure->RepetitionCounter;
+  }
+
+  /* Generate an update event to reload the Prescaler
+     and the repetition counter (only for advanced timer) value immediately */
+  TIMx->EGR = TIM_EGR_UG;
+}
+
+/**
+  * @brief  Timer Output Compare 1 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The ouput configuration structure
+  * @retval None
+  */
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR1;
+
+  /* Reset the Output Compare Mode Bits */
+  tmpccmrx &= ~TIM_CCMR1_OC1M;
+  tmpccmrx &= ~TIM_CCMR1_CC1S;
+  /* Select the Output Compare Mode */
+  tmpccmrx |= OC_Config->OCMode;
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC1P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= OC_Config->OCPolarity;
+
+  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+    /* Reset the Output N Polarity level */
+    tmpccer &= ~TIM_CCER_CC1NP;
+    /* Set the Output N Polarity */
+    tmpccer |= OC_Config->OCNPolarity;
+    /* Reset the Output N State */
+    tmpccer &= ~TIM_CCER_CC1NE;
+  }
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS1;
+    tmpcr2 &= ~TIM_CR2_OIS1N;
+    /* Set the Output Idle state */
+    tmpcr2 |= OC_Config->OCIdleState;
+    /* Set the Output N Idle state */
+    tmpcr2 |= OC_Config->OCNIdleState;
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR1 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Output Compare 2 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The ouput configuration structure
+  * @retval None
+  */
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR1;
+
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= ~TIM_CCMR1_OC2M;
+  tmpccmrx &= ~TIM_CCMR1_CC2S;
+
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (OC_Config->OCMode << 8U);
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC2P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 4U);
+
+  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
+  {
+    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+    /* Reset the Output N Polarity level */
+    tmpccer &= ~TIM_CCER_CC2NP;
+    /* Set the Output N Polarity */
+    tmpccer |= (OC_Config->OCNPolarity << 4U);
+    /* Reset the Output N State */
+    tmpccer &= ~TIM_CCER_CC2NE;
+
+  }
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS2;
+    tmpcr2 &= ~TIM_CR2_OIS2N;
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 2U);
+    /* Set the Output N Idle state */
+    tmpcr2 |= (OC_Config->OCNIdleState << 2U);
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR2 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Output Compare 3 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The ouput configuration structure
+  * @retval None
+  */
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Disable the Channel 3: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC3E;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+
+  /* Get the TIMx CCMR2 register value */
+  tmpccmrx = TIMx->CCMR2;
+
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= ~TIM_CCMR2_OC3M;
+  tmpccmrx &= ~TIM_CCMR2_CC3S;
+  /* Select the Output Compare Mode */
+  tmpccmrx |= OC_Config->OCMode;
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC3P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 8U);
+
+  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
+  {
+    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+    /* Reset the Output N Polarity level */
+    tmpccer &= ~TIM_CCER_CC3NP;
+    /* Set the Output N Polarity */
+    tmpccer |= (OC_Config->OCNPolarity << 8U);
+    /* Reset the Output N State */
+    tmpccer &= ~TIM_CCER_CC3NE;
+  }
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS3;
+    tmpcr2 &= ~TIM_CR2_OIS3N;
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 4U);
+    /* Set the Output N Idle state */
+    tmpcr2 |= (OC_Config->OCNIdleState << 4U);
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR2 */
+  TIMx->CCMR2 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR3 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Output Compare 4 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The ouput configuration structure
+  * @retval None
+  */
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Disable the Channel 4: Reset the CC4E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC4E;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+
+  /* Get the TIMx CCMR2 register value */
+  tmpccmrx = TIMx->CCMR2;
+
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= ~TIM_CCMR2_OC4M;
+  tmpccmrx &= ~TIM_CCMR2_CC4S;
+
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (OC_Config->OCMode << 8U);
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC4P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 12U);
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+    /* Reset the Output Compare IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS4;
+
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 6U);
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR2 */
+  TIMx->CCMR2 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR4 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Output Compare 5 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The ouput configuration structure
+  * @retval None
+  */
+static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
+                              TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Disable the output: Reset the CCxE Bit */
+  TIMx->CCER &= ~TIM_CCER_CC5E;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR3;
+
+  /* Reset the Output Compare Mode Bits */
+  tmpccmrx &= ~(TIM_CCMR3_OC5M);
+  /* Select the Output Compare Mode */
+  tmpccmrx |= OC_Config->OCMode;
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC5P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 16U);
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Reset the Output Compare IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS5;
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 8U);
+  }
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR3 */
+  TIMx->CCMR3 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR5 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Output Compare 6 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The ouput configuration structure
+  * @retval None
+  */
+static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
+                              TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Disable the output: Reset the CCxE Bit */
+  TIMx->CCER &= ~TIM_CCER_CC6E;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR3;
+
+  /* Reset the Output Compare Mode Bits */
+  tmpccmrx &= ~(TIM_CCMR3_OC6M);
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (OC_Config->OCMode << 8U);
+
+  /* Reset the Output Polarity level */
+  tmpccer &= (uint32_t)~TIM_CCER_CC6P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 20U);
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Reset the Output Compare IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS6;
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 10U);
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR3 */
+  TIMx->CCMR3 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR6 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Slave Timer configuration function
+  * @param  htim TIM handle
+  * @param  sSlaveConfig Slave timer configuration
+  * @retval None
+  */
+static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+                                                  TIM_SlaveConfigTypeDef *sSlaveConfig)
+{
+  uint32_t tmpsmcr;
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = htim->Instance->SMCR;
+
+  /* Reset the Trigger Selection Bits */
+  tmpsmcr &= ~TIM_SMCR_TS;
+  /* Set the Input Trigger source */
+  tmpsmcr |= sSlaveConfig->InputTrigger;
+
+  /* Reset the slave mode Bits */
+  tmpsmcr &= ~TIM_SMCR_SMS;
+  /* Set the slave mode */
+  tmpsmcr |= sSlaveConfig->SlaveMode;
+
+  /* Write to TIMx SMCR */
+  htim->Instance->SMCR = tmpsmcr;
+
+  /* Configure the trigger prescaler, filter, and polarity */
+  switch (sSlaveConfig->InputTrigger)
+  {
+    case TIM_TS_ETRF:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
+      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+      /* Configure the ETR Trigger source */
+      TIM_ETR_SetConfig(htim->Instance,
+                        sSlaveConfig->TriggerPrescaler,
+                        sSlaveConfig->TriggerPolarity,
+                        sSlaveConfig->TriggerFilter);
+      break;
+    }
+
+    case TIM_TS_TI1F_ED:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+      if(sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Disable the Channel 1: Reset the CC1E Bit */
+      tmpccer = htim->Instance->CCER;
+      htim->Instance->CCER &= ~TIM_CCER_CC1E;
+      tmpccmr1 = htim->Instance->CCMR1;
+
+      /* Set the filter */
+      tmpccmr1 &= ~TIM_CCMR1_IC1F;
+      tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
+
+      /* Write to TIMx CCMR1 and CCER registers */
+      htim->Instance->CCMR1 = tmpccmr1;
+      htim->Instance->CCER = tmpccer;
+      break;
+    }
+
+    case TIM_TS_TI1FP1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+      /* Configure TI1 Filter and Polarity */
+      TIM_TI1_ConfigInputStage(htim->Instance,
+                               sSlaveConfig->TriggerPolarity,
+                               sSlaveConfig->TriggerFilter);
+      break;
+    }
+
+    case TIM_TS_TI2FP2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+      /* Configure TI2 Filter and Polarity */
+      TIM_TI2_ConfigInputStage(htim->Instance,
+                               sSlaveConfig->TriggerPolarity,
+                               sSlaveConfig->TriggerFilter);
+      break;
+    }
+
+    case TIM_TS_ITR0:
+    case TIM_TS_ITR1:
+    case TIM_TS_ITR2:
+    case TIM_TS_ITR3:
+    case TIM_TS_ITR4:
+    case TIM_TS_ITR5:
+    case TIM_TS_ITR6:
+    case TIM_TS_ITR7:
+    case TIM_TS_ITR8:
+    case TIM_TS_ITR9:
+    case TIM_TS_ITR10:
+    case TIM_TS_ITR11:
+    case TIM_TS_ITR12:
+    case TIM_TS_ITR13:
+    {
+      /* Check the parameter */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+      break;
+    }
+
+    default:
+      break;
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the TI1 as Input.
+  * @param  TIMx to select the TIM peripheral.
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICSelection specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
+  *       (on channel2 path) is used as the input signal. Therefore CCMR1 must be
+  *        protected against un-initialized filter and polarity values.
+  */
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                       uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+  tmpccmr1 = TIMx->CCMR1;
+  tmpccer = TIMx->CCER;
+
+  /* Select the Input */
+  if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
+  {
+    tmpccmr1 &= ~TIM_CCMR1_CC1S;
+    tmpccmr1 |= TIM_ICSelection;
+  }
+  else
+  {
+    tmpccmr1 |= TIM_CCMR1_CC1S_0;
+  }
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC1F;
+  tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
+
+  /* Select the Polarity and set the CC1E Bit */
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+  tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the Polarity and Filter for TI1.
+  * @param  TIMx to select the TIM peripheral.
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  tmpccer = TIMx->CCER;
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC1F;
+  tmpccmr1 |= (TIM_ICFilter << 4U);
+
+  /* Select the Polarity and set the CC1E Bit */
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+  tmpccer |= TIM_ICPolarity;
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI2 as Input.
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICSelection specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
+  *       (on channel1 path) is used as the input signal. Therefore CCMR1 must be
+  *        protected against un-initialized filter and polarity values.
+  */
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+  tmpccmr1 = TIMx->CCMR1;
+  tmpccer = TIMx->CCER;
+
+  /* Select the Input */
+  tmpccmr1 &= ~TIM_CCMR1_CC2S;
+  tmpccmr1 |= (TIM_ICSelection << 8U);
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC2F;
+  tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
+
+  /* Select the Polarity and set the CC2E Bit */
+  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+  tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1 ;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the Polarity and Filter for TI2.
+  * @param  TIMx to select the TIM peripheral.
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+  tmpccmr1 = TIMx->CCMR1;
+  tmpccer = TIMx->CCER;
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC2F;
+  tmpccmr1 |= (TIM_ICFilter << 12U);
+
+  /* Select the Polarity and set the CC2E Bit */
+  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+  tmpccer |= (TIM_ICPolarity << 4U);
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1 ;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI3 as Input.
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICSelection specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
+  *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+  *        protected against un-initialized filter and polarity values.
+  */
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr2;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 3: Reset the CC3E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC3E;
+  tmpccmr2 = TIMx->CCMR2;
+  tmpccer = TIMx->CCER;
+
+  /* Select the Input */
+  tmpccmr2 &= ~TIM_CCMR2_CC3S;
+  tmpccmr2 |= TIM_ICSelection;
+
+  /* Set the filter */
+  tmpccmr2 &= ~TIM_CCMR2_IC3F;
+  tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
+
+  /* Select the Polarity and set the CC3E Bit */
+  tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
+  tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
+
+  /* Write to TIMx CCMR2 and CCER registers */
+  TIMx->CCMR2 = tmpccmr2;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI4 as Input.
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICSelection specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
+  *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+  *        protected against un-initialized filter and polarity values.
+  * @retval None
+  */
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr2;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 4: Reset the CC4E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC4E;
+  tmpccmr2 = TIMx->CCMR2;
+  tmpccer = TIMx->CCER;
+
+  /* Select the Input */
+  tmpccmr2 &= ~TIM_CCMR2_CC4S;
+  tmpccmr2 |= (TIM_ICSelection << 8U);
+
+  /* Set the filter */
+  tmpccmr2 &= ~TIM_CCMR2_IC4F;
+  tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
+
+  /* Select the Polarity and set the CC4E Bit */
+  tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
+  tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
+
+  /* Write to TIMx CCMR2 and CCER registers */
+  TIMx->CCMR2 = tmpccmr2;
+  TIMx->CCER = tmpccer ;
+}
+
+/**
+  * @brief  Selects the Input Trigger source
+  * @param  TIMx to select the TIM peripheral
+  * @param  InputTriggerSource The Input Trigger source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal Trigger 0
+  *            @arg TIM_TS_ITR1: Internal Trigger 1
+  *            @arg TIM_TS_ITR2: Internal Trigger 2
+  *            @arg TIM_TS_ITR3: Internal Trigger 3
+  *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
+  *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
+  *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
+  *            @arg TIM_TS_ETRF: External Trigger input
+  *            @arg TIM_TS_ITR4: Internal Trigger 4  (*)
+  *            @arg TIM_TS_ITR5: Internal Trigger 5
+  *            @arg TIM_TS_ITR6: Internal Trigger 6
+  *            @arg TIM_TS_ITR7: Internal Trigger 7
+  *            @arg TIM_TS_ITR8: Internal Trigger 8  (*)
+  *            @arg TIM_TS_ITR9: Internal Trigger 9  (*)
+  *            @arg TIM_TS_ITR10: Internal Trigger 10 (*)
+  *            @arg TIM_TS_ITR11: Internal Trigger 11 (*)
+  *            @arg TIM_TS_ITR12: Internal Trigger 12 (*)
+  *            @arg TIM_TS_ITR13: Internal Trigger 13 (*)
+  *
+  *       (*)  Value not defined in all devices.
+  *
+  * @retval None
+  */
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
+{
+  uint32_t tmpsmcr;
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = TIMx->SMCR;
+  /* Reset the TS Bits */
+  tmpsmcr &= ~TIM_SMCR_TS;
+  /* Set the Input Trigger source and the slave mode*/
+  tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+}
+/**
+  * @brief  Configures the TIMx External Trigger (ETR).
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ExtTRGPrescaler The external Trigger Prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
+  *            @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
+  *            @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
+  *            @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
+  * @param  TIM_ExtTRGPolarity The external Trigger Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
+  *            @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
+  * @param  ExtTRGFilter External Trigger Filter.
+  *          This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
+                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
+{
+  uint32_t tmpsmcr;
+
+  tmpsmcr = TIMx->SMCR;
+
+  /* Reset the ETR Bits */
+  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+
+  /* Set the Prescaler, the Filter value and the Polarity */
+  tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
+
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+}
+
+/**
+  * @brief  Enables or disables the TIM Capture Compare Channel x.
+  * @param  TIMx to select the TIM peripheral
+  * @param  Channel specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1
+  *            @arg TIM_CHANNEL_2: TIM Channel 2
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  *            @arg TIM_CHANNEL_4: TIM Channel 4
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @param  ChannelState specifies the TIM Channel CCxE bit new state.
+  *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
+  * @retval None
+  */
+void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
+{
+  uint32_t tmp;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+  assert_param(IS_TIM_CHANNELS(Channel));
+
+  tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
+
+  /* Reset the CCxE Bit */
+  TIMx->CCER &= ~tmp;
+
+  /* Set or reset the CCxE Bit */
+  TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
+}
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Reset interrupt callbacks to the legacy weak callbacks.
+  * @param  htim pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval None
+  */
+void TIM_ResetCallback(TIM_HandleTypeDef *htim)
+{
+  /* Reset the TIM callback to the legacy weak callbacks */
+  htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;             /* Legacy weak PeriodElapsedCallback             */
+  htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;     /* Legacy weak PeriodElapsedHalfCpltCallback     */
+  htim->TriggerCallback                   = HAL_TIM_TriggerCallback;                   /* Legacy weak TriggerCallback                   */
+  htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;           /* Legacy weak TriggerHalfCpltCallback           */
+  htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;                /* Legacy weak IC_CaptureCallback                */
+  htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;        /* Legacy weak IC_CaptureHalfCpltCallback        */
+  htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;           /* Legacy weak OC_DelayElapsedCallback           */
+  htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;         /* Legacy weak PWM_PulseFinishedCallback         */
+  htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */
+  htim->ErrorCallback                     = HAL_TIM_ErrorCallback;                     /* Legacy weak ErrorCallback                     */
+  htim->CommutationCallback               = HAL_TIMEx_CommutCallback;                  /* Legacy weak CommutationCallback               */
+  htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;          /* Legacy weak CommutationHalfCpltCallback       */
+  htim->BreakCallback                     = HAL_TIMEx_BreakCallback;                   /* Legacy weak BreakCallback                     */
+  htim->Break2Callback                    = HAL_TIMEx_Break2Callback;                  /* Legacy weak Break2Callback                    */
+}
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_TIM_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c
new file mode 100644
index 00000000..1dcd7704
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c
@@ -0,0 +1,2324 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_tim_ex.c
+  * @author  MCD Application Team
+  * @brief   TIM HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Timer Extended peripheral:
+  *           + Time Hall Sensor Interface Initialization
+  *           + Time Hall Sensor Interface Start
+  *           + Time Complementary signal break and dead time configuration
+  *           + Time Master and Slave synchronization configuration
+  *           + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
+  *           + Timer remapping capabilities configuration
+  @verbatim
+  ==============================================================================
+                      ##### TIMER Extended features #####
+  ==============================================================================
+  [..]
+    The Timer Extended features include:
+    (#) Complementary outputs with programmable dead-time for :
+        (++) Output Compare
+        (++) PWM generation (Edge and Center-aligned Mode)
+        (++) One-pulse mode output
+    (#) Synchronization circuit to control the timer with external signals and to
+        interconnect several timers together.
+    (#) Break input to put the timer output signals in reset state or in a known state.
+    (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
+        positioning purposes
+
+            ##### How to use this driver #####
+  ==============================================================================
+    [..]
+     (#) Initialize the TIM low level resources by implementing the following functions
+         depending on the selected feature:
+           (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
+
+     (#) Initialize the TIM low level resources :
+        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
+        (##) TIM pins configuration
+            (+++) Enable the clock for the TIM GPIOs using the following function:
+              __HAL_RCC_GPIOx_CLK_ENABLE();
+            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
+
+     (#) The external Clock can be configured, if needed (the default clock is the
+         internal clock from the APBx), using the following function:
+         HAL_TIM_ConfigClockSource, the clock configuration should be done before
+         any start function.
+
+     (#) Configure the TIM in the desired functioning mode using one of the
+         initialization function of this driver:
+          (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the
+               Timer Hall Sensor Interface and the commutation event with the corresponding
+               Interrupt and DMA request if needed (Note that One Timer is used to interface
+               with the Hall sensor Interface and another Timer should be used to use
+               the commutation event).
+
+     (#) Activate the TIM peripheral using one of the start functions:
+           (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()
+           (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
+           (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
+           (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup TIMEx TIMEx
+  * @brief TIM Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
+  * @brief    Timer Hall Sensor functions
+  *
+@verbatim
+  ==============================================================================
+                      ##### Timer Hall Sensor functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure TIM HAL Sensor.
+    (+) De-initialize TIM HAL Sensor.
+    (+) Start the Hall Sensor Interface.
+    (+) Stop the Hall Sensor Interface.
+    (+) Start the Hall Sensor Interface and enable interrupts.
+    (+) Stop the Hall Sensor Interface and disable interrupts.
+    (+) Start the Hall Sensor Interface and enable DMA transfers.
+    (+) Stop the Hall Sensor Interface and disable DMA transfers.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Hall Sensor Interface and initialize the associated handle.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @param  sConfig TIM Hall Sensor configuration structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
+{
+  TIM_OC_InitTypeDef OC_Config;
+
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+  assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+  assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy week callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->HallSensor_MspInitCallback == NULL)
+    {
+      htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->HallSensor_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIMEx_HallSensor_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Configure the Time base in the Encoder Mode */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the  Hall sensor */
+  TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
+
+  /* Reset the IC1PSC Bits */
+  htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+  /* Set the IC1PSC value */
+  htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
+
+  /* Enable the Hall sensor interface (XOR function of the three inputs) */
+  htim->Instance->CR2 |= TIM_CR2_TI1S;
+
+  /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
+  htim->Instance->SMCR &= ~TIM_SMCR_TS;
+  htim->Instance->SMCR |= TIM_TS_TI1F_ED;
+
+  /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
+  htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+  htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
+
+  /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
+  OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
+  OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
+  OC_Config.OCMode = TIM_OCMODE_PWM2;
+  OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
+  OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
+  OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
+  OC_Config.Pulse = sConfig->Commutation_Delay;
+
+  TIM_OC2_SetConfig(htim->Instance, &OC_Config);
+
+  /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
+    register to 101 */
+  htim->Instance->CR2 &= ~TIM_CR2_MMS;
+  htim->Instance->CR2 |= TIM_TRGO_OC2REF;
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM Hall Sensor interface
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->HallSensor_MspDeInitCallback == NULL)
+  {
+    htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->HallSensor_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIMEx_HallSensor_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Hall Sensor MSP.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Hall Sensor MSP.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Hall Sensor Interface.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Enable the Input Capture channel 1
+    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Hall sensor Interface.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channels 1, 2 and 3
+    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Hall Sensor Interface in interrupt mode.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Enable the capture compare Interrupts 1 event */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+  /* Enable the Input Capture channel 1
+    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Hall Sensor Interface in interrupt mode.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channel 1
+    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+  /* Disable the capture compare Interrupts event */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Hall Sensor Interface in DMA mode.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @param  pData The destination Buffer address.
+  * @param  Length The length of data to be transferred from TIM peripheral to memory.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if (((uint32_t)pData == 0U) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+  /* Enable the Input Capture channel 1
+    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+  /* Set the DMA Input Capture 1 Callbacks */
+  htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+  htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+  /* Set the DMA error callback */
+  htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+  /* Enable the DMA stream for Capture 1*/
+  if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  /* Enable the capture compare 1 Interrupt */
+  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Hall Sensor Interface in DMA mode.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channel 1
+    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+
+  /* Disable the capture compare Interrupts 1 event */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+
+  (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
+  *  @brief   Timer Complementary Output Compare functions
+  *
+@verbatim
+  ==============================================================================
+              ##### Timer Complementary Output Compare functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Start the Complementary Output Compare/PWM.
+    (+) Stop the Complementary Output Compare/PWM.
+    (+) Start the Complementary Output Compare/PWM and enable interrupts.
+    (+) Stop the Complementary Output Compare/PWM and disable interrupts.
+    (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
+    (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation on the complementary
+  *         output.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Enable the Capture compare channel N */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation on the complementary
+  *         output.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the Capture compare channel N */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in interrupt mode
+  *         on the complementary output.
+  * @param  htim TIM OC handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Output Compare interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Output Compare interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Output Compare interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+
+    default:
+      break;
+  }
+
+  /* Enable the TIM Break interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+
+  /* Enable the Capture compare channel N */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in interrupt mode
+  *         on the complementary output.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpccer;
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Output Compare interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Output Compare interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Output Compare interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Disable the Capture compare channel N */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+  /* Disable the TIM Break interrupt (only if no more channel is active) */
+  tmpccer = htim->Instance->CCER;
+  if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
+  {
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+  }
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in DMA mode
+  *         on the complementary output.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if (((uint32_t)pData == 0U) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do  */
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Output Compare DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Output Compare DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Output Compare DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Enable the Capture compare channel N */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in DMA mode
+  *         on the complementary output.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Output Compare DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Output Compare DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Output Compare DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Disable the Capture compare channel N */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
+  * @brief    Timer Complementary PWM functions
+  *
+@verbatim
+  ==============================================================================
+                 ##### Timer Complementary PWM functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Start the Complementary PWM.
+    (+) Stop the Complementary PWM.
+    (+) Start the Complementary PWM and enable interrupts.
+    (+) Stop the Complementary PWM and disable interrupts.
+    (+) Start the Complementary PWM and enable DMA transfers.
+    (+) Stop the Complementary PWM and disable DMA transfers.
+    (+) Start the Complementary Input Capture measurement.
+    (+) Stop the Complementary Input Capture.
+    (+) Start the Complementary Input Capture and enable interrupts.
+    (+) Stop the Complementary Input Capture and disable interrupts.
+    (+) Start the Complementary Input Capture and enable DMA transfers.
+    (+) Stop the Complementary Input Capture and disable DMA transfers.
+    (+) Start the Complementary One Pulse generation.
+    (+) Stop the Complementary One Pulse.
+    (+) Start the Complementary One Pulse and enable interrupts.
+    (+) Stop the Complementary One Pulse and disable interrupts.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the PWM signal generation on the complementary output.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Enable the complementary PWM output  */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the PWM signal generation on the complementary output.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the complementary PWM output  */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the PWM signal generation in interrupt mode on the
+  *         complementary output.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Enable the TIM Break interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+
+  /* Enable the complementary PWM output  */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the PWM signal generation in interrupt mode on the
+  *         complementary output.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpccer;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Disable the complementary PWM output  */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+  /* Disable the TIM Break interrupt (only if no more channel is active) */
+  tmpccer = htim->Instance->CCER;
+  if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
+  {
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+  }
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM PWM signal generation in DMA mode on the
+  *         complementary output
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if (((uint32_t)pData == 0U) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Enable the complementary PWM output  */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM PWM signal generation in DMA mode on the complementary
+  *         output
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Disable the complementary PWM output */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
+  * @brief    Timer Complementary One Pulse functions
+  *
+@verbatim
+  ==============================================================================
+                ##### Timer Complementary One Pulse functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Start the Complementary One Pulse generation.
+    (+) Stop the Complementary One Pulse.
+    (+) Start the Complementary One Pulse and enable interrupts.
+    (+) Stop the Complementary One Pulse and disable interrupts.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation on the complementary
+  *         output.
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+  /* Enable the complementary One Pulse output */
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM One Pulse signal generation on the complementary
+  *         output.
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+  /* Disable the complementary One Pulse output */
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation in interrupt mode on the
+  *         complementary channel.
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+  /* Enable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+  /* Enable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+
+  /* Enable the complementary One Pulse output */
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM One Pulse signal generation in interrupt mode on the
+  *         complementary channel.
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+  /* Disable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+  /* Disable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+
+  /* Disable the complementary One Pulse output */
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
+  * @brief    Peripheral Control functions
+  *
+@verbatim
+  ==============================================================================
+                    ##### Peripheral Control functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+      (+) Configure the commutation event in case of use of the Hall sensor interface.
+      (+) Configure Output channels for OC and PWM mode.
+
+      (+) Configure Complementary channels, break features and dead time.
+      (+) Configure Master synchronization.
+      (+) Configure timer remapping capabilities.
+      (+) Select timer input source.
+      (+) Enable or disable channel grouping.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the TIM commutation event sequence.
+  * @note  This function is mandatory to use the commutation event in order to
+  *        update the configuration at each commutation detection on the TRGI input of the Timer,
+  *        the typical use of this feature is with the use of another Timer(interface Timer)
+  *        configured in Hall sensor interface, this interface Timer will generate the
+  *        commutation at its TRGO output (connected to Timer used in this function) each time
+  *        the TI1 of the Interface Timer detect a commutation at its input TI1.
+  * @param  htim TIM handle
+  * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal trigger 0 selected
+  *            @arg TIM_TS_ITR1: Internal trigger 1 selected
+  *            @arg TIM_TS_ITR2: Internal trigger 2 selected
+  *            @arg TIM_TS_ITR3: Internal trigger 3 selected
+  *            @arg TIM_TS_ITR12: Internal trigger 12 selected (*)
+  *            @arg TIM_TS_ITR13: Internal trigger 13 selected (*)
+  *            @arg TIM_TS_NONE: No trigger is needed
+  * @param  CommutationSource the Commutation Event source
+  *          This parameter can be one of the following values:
+  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                              uint32_t  CommutationSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
+      (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
+      (InputTrigger == TIM_TS_ITR12)  || (InputTrigger == TIM_TS_ITR13))
+  {
+    /* Select the Input trigger */
+    htim->Instance->SMCR &= ~TIM_SMCR_TS;
+    htim->Instance->SMCR |= InputTrigger;
+  }
+
+  /* Select the Capture Compare preload feature */
+  htim->Instance->CR2 |= TIM_CR2_CCPC;
+  /* Select the Commutation event source */
+  htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+  htim->Instance->CR2 |= CommutationSource;
+
+  /* Disable Commutation Interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
+
+  /* Disable Commutation DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the TIM commutation event sequence with interrupt.
+  * @note  This function is mandatory to use the commutation event in order to
+  *        update the configuration at each commutation detection on the TRGI input of the Timer,
+  *        the typical use of this feature is with the use of another Timer(interface Timer)
+  *        configured in Hall sensor interface, this interface Timer will generate the
+  *        commutation at its TRGO output (connected to Timer used in this function) each time
+  *        the TI1 of the Interface Timer detect a commutation at its input TI1.
+  * @param  htim TIM handle
+  * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal trigger 0 selected
+  *            @arg TIM_TS_ITR1: Internal trigger 1 selected
+  *            @arg TIM_TS_ITR2: Internal trigger 2 selected
+  *            @arg TIM_TS_ITR3: Internal trigger 3 selected
+  *            @arg TIM_TS_ITR2: Internal trigger 12 selected (*)
+  *            @arg TIM_TS_ITR3: Internal trigger 13 selected (*)
+  *            @arg TIM_TS_NONE: No trigger is needed
+  * @param  CommutationSource the Commutation Event source
+  *          This parameter can be one of the following values:
+  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                                 uint32_t  CommutationSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
+      (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
+      (InputTrigger == TIM_TS_ITR12)  || (InputTrigger == TIM_TS_ITR13))
+  {
+    /* Select the Input trigger */
+    htim->Instance->SMCR &= ~TIM_SMCR_TS;
+    htim->Instance->SMCR |= InputTrigger;
+  }
+
+  /* Select the Capture Compare preload feature */
+  htim->Instance->CR2 |= TIM_CR2_CCPC;
+  /* Select the Commutation event source */
+  htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+  htim->Instance->CR2 |= CommutationSource;
+
+  /* Disable Commutation DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
+
+  /* Enable the Commutation Interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the TIM commutation event sequence with DMA.
+  * @note  This function is mandatory to use the commutation event in order to
+  *        update the configuration at each commutation detection on the TRGI input of the Timer,
+  *        the typical use of this feature is with the use of another Timer(interface Timer)
+  *        configured in Hall sensor interface, this interface Timer will generate the
+  *        commutation at its TRGO output (connected to Timer used in this function) each time
+  *        the TI1 of the Interface Timer detect a commutation at its input TI1.
+  * @note  The user should configure the DMA in his own software, in This function only the COMDE bit is set
+  * @param  htim TIM handle
+  * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal trigger 0 selected
+  *            @arg TIM_TS_ITR1: Internal trigger 1 selected
+  *            @arg TIM_TS_ITR2: Internal trigger 2 selected
+  *            @arg TIM_TS_ITR3: Internal trigger 3 selected
+  *            @arg TIM_TS_ITR2: Internal trigger 12 selected (*)
+  *            @arg TIM_TS_ITR3: Internal trigger 13 selected (*)
+  *            @arg TIM_TS_NONE: No trigger is needed
+  *
+  *         (*)  Value not defined in all devices.
+  *
+  * @param  CommutationSource the Commutation Event source
+  *          This parameter can be one of the following values:
+  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                                  uint32_t  CommutationSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
+      (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
+      (InputTrigger == TIM_TS_ITR12)  || (InputTrigger == TIM_TS_ITR13))
+  {
+    /* Select the Input trigger */
+    htim->Instance->SMCR &= ~TIM_SMCR_TS;
+    htim->Instance->SMCR |= InputTrigger;
+  }
+
+  /* Select the Capture Compare preload feature */
+  htim->Instance->CR2 |= TIM_CR2_CCPC;
+  /* Select the Commutation event source */
+  htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+  htim->Instance->CR2 |= CommutationSource;
+
+  /* Enable the Commutation DMA Request */
+  /* Set the DMA Commutation Callback */
+  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
+  /* Set the DMA error callback */
+  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
+
+  /* Disable Commutation Interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
+
+  /* Enable the Commutation DMA Request */
+  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the TIM in master mode.
+  * @param  htim TIM handle.
+  * @param  sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
+  *         contains the selected trigger output (TRGO) and the Master/Slave
+  *         mode.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+                                                        TIM_MasterConfigTypeDef *sMasterConfig)
+{
+  uint32_t tmpcr2;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
+  assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
+
+  /* Check input state */
+  __HAL_LOCK(htim);
+
+  /* Change the handler state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = htim->Instance->CR2;
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = htim->Instance->SMCR;
+
+  /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
+  if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
+  {
+    /* Check the parameters */
+    assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
+
+    /* Clear the MMS2 bits */
+    tmpcr2 &= ~TIM_CR2_MMS2;
+    /* Select the TRGO2 source*/
+    tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
+  }
+
+  /* Reset the MMS Bits */
+  tmpcr2 &= ~TIM_CR2_MMS;
+  /* Select the TRGO source */
+  tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
+
+  /* Update TIMx CR2 */
+  htim->Instance->CR2 = tmpcr2;
+
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    /* Reset the MSM Bit */
+    tmpsmcr &= ~TIM_SMCR_MSM;
+    /* Set master mode */
+    tmpsmcr |= sMasterConfig->MasterSlaveMode;
+
+    /* Update TIMx SMCR */
+    htim->Instance->SMCR = tmpsmcr;
+  }
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the Break feature, dead time, Lock level, OSSI/OSSR State
+  *         and the AOE(automatic output enable).
+  * @param  htim TIM handle
+  * @param  sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
+  *         contains the BDTR Register configuration  information for the TIM peripheral.
+  * @note   Interrupts can be generated when an active level is detected on the
+  *         break input, the break 2 input or the system break input. Break
+  *         interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
+                                                TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
+{
+  /* Keep this variable initialized to 0 as it is used to configure BDTR register */
+  uint32_t tmpbdtr = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
+  assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
+  assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
+  assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
+  assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
+  assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
+  assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
+  assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
+
+  /* Check input state */
+  __HAL_LOCK(htim);
+
+  /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
+     the OSSI State, the dead time value and the Automatic Output Enable Bit */
+
+  /* Set the BDTR bits */
+  MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
+
+  if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
+  {
+    /* Check the parameters */
+    assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
+    assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
+    assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
+
+    /* Set the BREAK2 input related BDTR bits */
+    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
+    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
+    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
+  }
+
+  /* Set TIMx_BDTR */
+  htim->Instance->BDTR = tmpbdtr;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+#if defined(TIM_BREAK_INPUT_SUPPORT)
+
+/**
+  * @brief  Configures the break input source.
+  * @param  htim TIM handle.
+  * @param  BreakInput Break input to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_BREAKINPUT_BRK: Timer break input
+  *            @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
+  * @param  sBreakInputConfig Break input source configuration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
+                                             uint32_t BreakInput,
+                                             TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
+
+{
+  uint32_t tmporx;
+  uint32_t bkin_enable_mask;
+  uint32_t bkin_polarity_mask;
+  uint32_t bkin_enable_bitpos;
+  uint32_t bkin_polarity_bitpos;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_BREAKINPUT(BreakInput));
+  assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
+  assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
+  if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
+  {
+    assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
+  }
+
+  /* Check input state */
+  __HAL_LOCK(htim);
+
+  switch (sBreakInputConfig->Source)
+  {
+    case TIM_BREAKINPUTSOURCE_BKIN:
+    {
+      bkin_enable_mask = TIM1_AF1_BKINE;
+      bkin_enable_bitpos = TIM1_AF1_BKINE_Pos;
+      bkin_polarity_mask = TIM1_AF1_BKINP;
+      bkin_polarity_bitpos = TIM1_AF1_BKINP_Pos;
+      break;
+    }
+    case TIM_BREAKINPUTSOURCE_COMP1:
+    {
+      bkin_enable_mask = TIM1_AF1_BKCMP1E;
+      bkin_enable_bitpos = TIM1_AF1_BKCMP1E_Pos;
+      bkin_polarity_mask = TIM1_AF1_BKCMP1P;
+      bkin_polarity_bitpos = TIM1_AF1_BKCMP1P_Pos;
+      break;
+    }
+    case TIM_BREAKINPUTSOURCE_COMP2:
+    {
+      bkin_enable_mask = TIM1_AF1_BKCMP2E;
+      bkin_enable_bitpos = TIM1_AF1_BKCMP2E_Pos;
+      bkin_polarity_mask = TIM1_AF1_BKCMP2P;
+      bkin_polarity_bitpos = TIM1_AF1_BKCMP2P_Pos;
+      break;
+    }
+    case TIM_BREAKINPUTSOURCE_DFSDM1:
+    {
+      bkin_enable_mask = TIM1_AF1_BKDF1BK0E;
+      bkin_enable_bitpos = 8U;
+      bkin_polarity_mask = 0U;
+      bkin_polarity_bitpos = 0U;
+      break;
+    }
+
+    default:
+    {
+      bkin_enable_mask = 0U;
+      bkin_polarity_mask = 0U;
+      bkin_enable_bitpos = 0U;
+      bkin_polarity_bitpos = 0U;
+      break;
+    }
+  }
+
+  switch (BreakInput)
+  {
+    case TIM_BREAKINPUT_BRK:
+    {
+      /* Get the TIMx_AF1 register value */
+      tmporx = htim->Instance->AF1;
+
+      /* Enable the break input */
+      tmporx &= ~bkin_enable_mask;
+      tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
+
+      /* Set the break input polarity */
+      if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
+      {
+        tmporx &= ~bkin_polarity_mask;
+        tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
+      }
+
+      /* Set TIMx_AF1 */
+      htim->Instance->AF1 = tmporx;
+      break;
+    }
+    case TIM_BREAKINPUT_BRK2:
+    {
+      /* Get the TIMx_AF2 register value */
+      tmporx = htim->Instance->AF2;
+
+      /* Enable the break input */
+      tmporx &= ~bkin_enable_mask;
+      tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
+
+      /* Set the break input polarity */
+      if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
+      {
+        tmporx &= ~bkin_polarity_mask;
+        tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
+      }
+
+      /* Set TIMx_AF2 */
+      htim->Instance->AF2 = tmporx;
+      break;
+    }
+    default:
+      break;
+  }
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+#endif /*TIM_BREAK_INPUT_SUPPORT */
+
+/**
+  * @brief  Configures the TIMx Remapping input capabilities.
+  * @param  htim TIM handle.
+  * @param  Remap specifies the TIM remapping source.
+  *         For TIM1, the parameter is one of the following values:
+  *            @arg TIM_TIM1_ETR_GPIO:               TIM1_ETR is connected to GPIO
+  *            @arg TIM_TIM1_ETR_COMP1:              TIM1_ETR is connected to COMP1 output
+  *            @arg TIM_TIM1_ETR_COMP2:              TIM1_ETR is connected to COMP2 output
+  *            @arg TIM_TIM1_ETR_ADC1_AWD1:          TIM1_ETR is connected to ADC1 AWD1
+  *            @arg TIM_TIM1_ETR_ADC1_AWD2:          TIM1_ETR is connected to ADC1 AWD2
+  *            @arg TIM_TIM1_ETR_ADC1_AWD3:          TIM1_ETR is connected to ADC1 AWD3
+  *            @arg TIM_TIM1_ETR_ADC3_AWD1:          TIM1_ETR is connected to ADC3 AWD1
+  *            @arg TIM_TIM1_ETR_ADC3_AWD2:          TIM1_ETR is connected to ADC3 AWD2
+  *            @arg TIM_TIM1_ETR_ADC3_AWD3:          TIM1_ETR is connected to ADC3 AWD3
+  *
+  *         For TIM2, the parameter is one of the following values:
+  *            @arg TIM_TIM2_ETR_GPIO:               TIM2_ETR is connected to GPIO
+  *            @arg TIM_TIM2_ETR_COMP1:              TIM2_ETR is connected to COMP1 output
+  *            @arg TIM_TIM2_ETR_COMP2:              TIM2_ETR is connected to COMP2 output
+  *            @arg TIM_TIM2_ETR_LSE:                TIM2_ETR is connected to LSE
+  *            @arg TIM_TIM2_ETR_SAI1_FSA:           TIM2_ETR is connected to SAI1 FS_A
+  *            @arg TIM_TIM2_ETR_SAI1_FSB:           TIM2_ETR is connected to SAI1 FS_B
+  *
+  *         For TIM3, the parameter is one of the following values:
+  *            @arg TIM_TIM3_ETR_GPIO:               TIM3_ETR is connected to GPIO
+  *            @arg TIM_TIM3_ETR_COMP1:              TIM3_ETR is connected to COMP1 output
+  *
+  *         For TIM5, the parameter is one of the following values:
+  *            @arg TIM_TIM5_ETR_GPIO:               TIM5_ETR is connected to GPIO
+  *            @arg TIM_TIM5_ETR_SAI2_FSA:           TIM5_ETR is connected to SAI2 FS_A (*)
+  *            @arg TIM_TIM5_ETR_SAI2_FSB:           TIM5_ETR is connected to SAI2 FS_B (*)
+  *            @arg TIM_TIM5_ETR_SAI4_FSA:           TIM5_ETR is connected to SAI2 FS_A (*)
+  *            @arg TIM_TIM5_ETR_SAI4_FSB:           TIM5_ETR is connected to SAI2 FS_B (*)
+  *
+  *         For TIM8, the parameter is one of the following values:
+  *            @arg TIM_TIM8_ETR_GPIO:               TIM8_ETR is connected to GPIO
+  *            @arg TIM_TIM8_ETR_COMP1:              TIM8_ETR is connected to COMP1 output
+  *            @arg TIM_TIM8_ETR_COMP2:              TIM8_ETR is connected to COMP2 output
+  *            @arg TIM_TIM8_ETR_ADC2_AWD1:          TIM8_ETR is connected to ADC2 AWD1
+  *            @arg TIM_TIM8_ETR_ADC2_AWD2:          TIM8_ETR is connected to ADC2 AWD2
+  *            @arg TIM_TIM8_ETR_ADC2_AWD3:          TIM8_ETR is connected to ADC2 AWD3
+  *            @arg TIM_TIM8_ETR_ADC3_AWD1:          TIM8_ETR is connected to ADC3 AWD1
+  *            @arg TIM_TIM8_ETR_ADC3_AWD2:          TIM8_ETR is connected to ADC3 AWD2
+  *            @arg TIM_TIM8_ETR_ADC3_AWD3:          TIM8_ETR is connected to ADC3 AWD3
+  *
+  *         For TIM23, the parameter is one of the following values: (*)
+  *            @arg TIM_TIM23_ETR_GPIO               TIM23_ETR is connected to GPIO
+  *            @arg TIM_TIM23_ETR_COMP1              TIM23_ETR is connected to COMP1 output
+  *            @arg TIM_TIM23_ETR_COMP2              TIM23_ETR is connected to COMP2 output
+  *
+  *         For TIM24, the parameter is one of the following values: (*)
+  *           @arg TIM_TIM24_ETR_GPIO                TIM24_ETR is connected to GPIO
+  *           @arg TIM_TIM24_ETR_SAI4_FSA            TIM24_ETR is connected to SAI4 FS_A
+  *           @arg TIM_TIM24_ETR_SAI4_FSB            TIM24_ETR is connected to SAI4 FS_B
+  *           @arg TIM_TIM24_ETR_SAI1_FSA            TIM24_ETR is connected to SAI1 FS_A
+  *           @arg TIM_TIM24_ETR_SAI1_FSB            TIM24_ETR is connected to SAI1 FS_B
+  *
+  *         (*)  Value not defined in all devices.
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
+{
+  /* Check parameters */
+  assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_REMAP(Remap));
+
+  __HAL_LOCK(htim);
+
+  MODIFY_REG(htim->Instance->AF1, TIM1_AF1_ETRSEL_Msk, Remap);
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Select the timer input source
+  * @param  htim TIM handle.
+  * @param  Channel specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TI1 input channel
+  *            @arg TIM_CHANNEL_2: TI2 input channel
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  *            @arg TIM_CHANNEL_4: TIM Channel 4
+  * @param  TISelection parameter of the TIM_TISelectionStruct structure is detailed as follows:
+  *         For TIM1, the parameter is one of the following values:
+  *            @arg TIM_TIM1_TI1_GPIO:                TIM1 TI1 is connected to GPIO
+  *            @arg TIM_TIM1_TI1_COMP1:               TIM1 TI1 is connected to COMP1 output
+  *
+  *         For TIM2, the parameter is one of the following values:
+  *            @arg TIM_TIM2_TI4_GPIO:                TIM2 TI4 is connected to GPIO
+  *            @arg TIM_TIM2_TI4_COMP1:               TIM2 TI4 is connected to COMP1 output
+  *            @arg TIM_TIM2_TI4_COMP2:               TIM2 TI4 is connected to COMP2 output
+  *            @arg TIM_TIM2_TI4_COMP1_COMP2:         TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output
+  *
+  *         For TIM3, the parameter is one of the following values:
+  *            @arg TIM_TIM3_TI1_GPIO:                TIM3 TI1 is connected to GPIO
+  *            @arg TIM_TIM3_TI1_COMP1:               TIM3 TI1 is connected to COMP1 output
+  *            @arg TIM_TIM3_TI1_COMP2:               TIM3 TI1 is connected to COMP2 output
+  *            @arg TIM_TIM3_TI1_COMP1_COMP2:         TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output
+  *
+  *         For TIM5, the parameter is one of the following values:
+  *            @arg TIM_TIM5_TI1_GPIO:                TIM5 TI1 is connected to GPIO
+  *            @arg TIM_TIM5_TI1_CAN_TMP:             TIM5 TI1 is connected to CAN TMP
+  *            @arg TIM_TIM5_TI1_CAN_RTP:             TIM5 TI1 is connected to CAN RTP
+  *
+  *         For TIM8, the parameter is one of the following values:
+  *            @arg TIM_TIM8_TI1_GPIO:               TIM8 TI1 is connected to GPIO
+  *            @arg TIM_TIM8_TI1_COMP2:              TIM8 TI1 is connected to COMP2 output
+  *
+  *         For TIM12, the parameter can have the following values: (*)
+  *            @arg TIM_TIM12_TI1_GPIO:              TIM12 TI1 is connected to GPIO
+  *            @arg TIM_TIM12_TI1_SPDIF_FS:          TIM12 TI1 is connected to SPDIF FS
+  *
+  *         For TIM15, the parameter is one of the following values:
+  *            @arg TIM_TIM15_TI1_GPIO:              TIM15 TI1 is connected to GPIO
+  *            @arg TIM_TIM15_TI1_TIM2:              TIM15 TI1 is connected to TIM2 CH1
+  *            @arg TIM_TIM15_TI1_TIM3:              TIM15 TI1 is connected to TIM3 CH1
+  *            @arg TIM_TIM15_TI1_TIM4:              TIM15 TI1 is connected to TIM4 CH1
+  *            @arg TIM_TIM15_TI1_LSE:               TIM15 TI1 is connected to LSE
+  *            @arg TIM_TIM15_TI1_CSI:               TIM15 TI1 is connected to CSI
+  *            @arg TIM_TIM15_TI1_MCO2:              TIM15 TI1 is connected to MCO2
+  *            @arg TIM_TIM15_TI2_GPIO:              TIM15 TI2 is connected to GPIO
+  *            @arg TIM_TIM15_TI2_TIM2:              TIM15 TI2 is connected to TIM2 CH2
+  *            @arg TIM_TIM15_TI2_TIM3:              TIM15 TI2 is connected to TIM3 CH2
+  *            @arg TIM_TIM15_TI2_TIM4:              TIM15 TI2 is connected to TIM4 CH2
+  *
+  *         For TIM16, the parameter can have the following values:
+  *            @arg TIM_TIM16_TI1_GPIO:              TIM16 TI1 is connected to GPIO
+  *            @arg TIM_TIM16_TI1_LSI:               TIM16 TI1 is connected to LSI
+  *            @arg TIM_TIM16_TI1_LSE:               TIM16 TI1 is connected to LSE
+  *            @arg TIM_TIM16_TI1_RTC:               TIM16 TI1 is connected to RTC wakeup interrupt
+  *
+  *         For TIM17, the parameter can have the following values:
+  *            @arg TIM_TIM17_TI1_GPIO:              TIM17 TI1 is connected to GPIO
+  *            @arg TIM_TIM17_TI1_SPDIF_FS:          TIM17 TI1 is connected to SPDIF FS (*)
+  *            @arg TIM_TIM17_TI1_HSE_1MHZ:          TIM17 TI1 is connected to HSE 1MHz
+  *            @arg TIM_TIM17_TI1_MCO1:              TIM17 TI1 is connected to MCO1
+  *
+  *         For TIM23, the parameter can have the following values: (*)
+  *            @arg TIM_TIM23_TI4_GPIO               TIM23_TI4 is connected to GPIO
+  *            @arg TIM_TIM23_TI4_COMP1              TIM23_TI4 is connected to COMP1 output
+  *            @arg TIM_TIM23_TI4_COMP2              TIM23_TI4 is connected to COMP2 output
+  *            @arg TIM_TIM23_TI4_COMP1_COMP2        TIM23_TI4 is connected to COMP2 output
+  *
+  *         For TIM24, the parameter can have the following values: (*)
+  *            @arg TIM_TIM24_TI1_GPIO               TIM24_TI1 is connected to GPIO
+  *            @arg TIM_TIM24_TI1_CAN_TMP            TIM24_TI1 is connected to CAN_TMP
+  *            @arg TIM_TIM24_TI1_CAN_RTP            TIM24_TI1 is connected to CAN_RTP
+  *            @arg TIM_TIM24_TI1_CAN_SOC            TIM24_TI1 is connected to CAN_SOC
+  *
+  *         (*)  Value not defined in all devices. \n
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_TIM_TISEL_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_TISEL(TISelection));
+
+  __HAL_LOCK(htim);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+      MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI1SEL, TISelection);
+      break;
+    case TIM_CHANNEL_2:
+      MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI2SEL, TISelection);
+      break;
+    case TIM_CHANNEL_3:
+      MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI3SEL, TISelection);
+      break;
+    case TIM_CHANNEL_4:
+      MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI4SEL, TISelection);
+      break;
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+
+/**
+  * @brief  Group channel 5 and channel 1, 2 or 3
+  * @param  htim TIM handle.
+  * @param  Channels specifies the reference signal(s) the OC5REF is combined with.
+  *         This parameter can be any combination of the following values:
+  *         TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
+  *         TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
+  *         TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
+  *         TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)
+{
+  /* Check parameters */
+  assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_GROUPCH5(Channels));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Clear GC5Cx bit fields */
+  htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1);
+
+  /* Set GC5Cx bit fields */
+  htim->Instance->CCR5 |= Channels;
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
+  * @brief    Extended Callbacks functions
+  *
+@verbatim
+  ==============================================================================
+                    ##### Extended Callbacks functions #####
+  ==============================================================================
+  [..]
+    This section provides Extended TIM callback functions:
+    (+) Timer Commutation callback
+    (+) Timer Break callback
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Hall commutation changed callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_CommutCallback could be implemented in the user file
+   */
+}
+/**
+  * @brief  Hall commutation changed half complete callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Hall Break detection callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_BreakCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Hall Break2 detection callback in non blocking mode
+  * @param  htim: TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_TIMEx_Break2Callback could be implemented in the user file
+   */
+}
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
+  * @brief    Extended Peripheral State functions
+  *
+@verbatim
+  ==============================================================================
+                ##### Extended Peripheral State functions #####
+  ==============================================================================
+  [..]
+    This subsection permits to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the TIM Hall Sensor interface handle state.
+  * @param  htim TIM Hall Sensor handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
+  * @{
+  */
+
+/**
+  * @brief  TIM DMA Commutation callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->CommutationCallback(htim);
+#else
+  HAL_TIMEx_CommutCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Commutation half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->CommutationHalfCpltCallback(htim);
+#else
+  HAL_TIMEx_CommutHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+
+/**
+  * @brief  Enables or disables the TIM Capture Compare Channel xN.
+  * @param  TIMx to select the TIM peripheral
+  * @param  Channel specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1
+  *            @arg TIM_CHANNEL_2: TIM Channel 2
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  * @param  ChannelNState specifies the TIM Channel CCxNE bit new state.
+  *          This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
+  * @retval None
+  */
+static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
+{
+  uint32_t tmp;
+
+  tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
+
+  /* Reset the CCxNE Bit */
+  TIMx->CCER &=  ~tmp;
+
+  /* Set or reset the CCxNE Bit */
+  TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
+}
+/**
+  * @}
+  */
+
+#endif /* HAL_TIM_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_dma.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_dma.c
new file mode 100644
index 00000000..51dafc51
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_dma.c
@@ -0,0 +1,423 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_dma.c
+  * @author  MCD Application Team
+  * @brief   DMA LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_ll_dma.h"
+#include "stm32h7xx_ll_bus.h"
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined (DMA1) || defined (DMA2)
+
+/** @addtogroup DMA_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup DMA_LL_Private_Macros
+  * @{
+  */
+#define IS_LL_DMA_DIRECTION(__VALUE__)          (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
+                                                 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
+                                                 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
+
+#define IS_LL_DMA_MODE(__VALUE__)               (((__VALUE__) == LL_DMA_MODE_NORMAL)    || \
+                                                 ((__VALUE__) == LL_DMA_MODE_CIRCULAR)  || \
+                                                 ((__VALUE__) == LL_DMA_MODE_PFCTRL))
+
+#define IS_LL_DMA_PERIPHINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
+                                                 ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
+
+#define IS_LL_DMA_MEMORYINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
+                                                 ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
+
+#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE)      || \
+                                                 ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD)  || \
+                                                 ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
+
+#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE)      || \
+                                                 ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD)  || \
+                                                 ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
+
+#define IS_LL_DMA_NBDATA(__VALUE__)             ((__VALUE__)  <= 0x0000FFFFU)
+
+#if defined(ADC3)
+#define IS_LL_DMA_REQUEST(REQUEST)              (((REQUEST)   <= LL_DMAMUX1_REQ_ADC3))
+#else
+#define IS_LL_DMA_REQUEST(REQUEST)              (((REQUEST)   <= LL_DMAMUX1_REQ_USART10_TX))
+#endif /* ADC3 */
+
+#define IS_LL_DMA_PRIORITY(__VALUE__)           (((__VALUE__) == LL_DMA_PRIORITY_LOW)    || \
+                                                 ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
+                                                 ((__VALUE__) == LL_DMA_PRIORITY_HIGH)   || \
+                                                 ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
+
+#define IS_LL_DMA_ALL_STREAM_INSTANCE(INSTANCE, STREAM)   ((((INSTANCE) == DMA1) && \
+                                                           (((STREAM) == LL_DMA_STREAM_0)     || \
+                                                            ((STREAM) == LL_DMA_STREAM_1)     || \
+                                                            ((STREAM) == LL_DMA_STREAM_2)     || \
+                                                            ((STREAM) == LL_DMA_STREAM_3)     || \
+                                                            ((STREAM) == LL_DMA_STREAM_4)     || \
+                                                            ((STREAM) == LL_DMA_STREAM_5)     || \
+                                                            ((STREAM) == LL_DMA_STREAM_6)     || \
+                                                            ((STREAM) == LL_DMA_STREAM_7)     || \
+                                                            ((STREAM) == LL_DMA_STREAM_ALL))) || \
+                                                           (((INSTANCE) == DMA2) && \
+                                                           (((STREAM) == LL_DMA_STREAM_0)     || \
+                                                            ((STREAM) == LL_DMA_STREAM_1)     || \
+                                                            ((STREAM) == LL_DMA_STREAM_2)     || \
+                                                            ((STREAM) == LL_DMA_STREAM_3)     || \
+                                                            ((STREAM) == LL_DMA_STREAM_4)     || \
+                                                            ((STREAM) == LL_DMA_STREAM_5)     || \
+                                                            ((STREAM) == LL_DMA_STREAM_6)     || \
+                                                            ((STREAM) == LL_DMA_STREAM_7)     || \
+                                                            ((STREAM) == LL_DMA_STREAM_ALL))))
+
+#define IS_LL_DMA_FIFO_MODE_STATE(STATE)    (((STATE) == LL_DMA_FIFOMODE_DISABLE ) || \
+                                             ((STATE) == LL_DMA_FIFOMODE_ENABLE))
+
+#define IS_LL_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_4)  || \
+                                             ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_2)  || \
+                                             ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_3_4)  || \
+                                             ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_FULL))
+
+#define IS_LL_DMA_MEMORY_BURST(BURST)       (((BURST) == LL_DMA_MBURST_SINGLE) || \
+                                             ((BURST) == LL_DMA_MBURST_INC4)   || \
+                                             ((BURST) == LL_DMA_MBURST_INC8)   || \
+                                             ((BURST) == LL_DMA_MBURST_INC16))
+
+#define IS_LL_DMA_PERIPHERAL_BURST(BURST)  (((BURST) == LL_DMA_PBURST_SINGLE) || \
+                                            ((BURST) == LL_DMA_PBURST_INC4)   || \
+                                            ((BURST) == LL_DMA_PBURST_INC8)   || \
+                                            ((BURST) == LL_DMA_PBURST_INC16))
+
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DMA_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup DMA_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize the DMA registers to their default reset values.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  *         @arg @ref LL_DMA_STREAM_ALL
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: DMA registers are de-initialized
+  *          - ERROR: DMA registers are not de-initialized
+  */
+uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  DMA_Stream_TypeDef *tmp;
+  ErrorStatus status = SUCCESS;
+
+  /* Check the DMA Instance DMAx and Stream parameters */
+  assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
+
+  if (Stream == LL_DMA_STREAM_ALL)
+  {
+    if (DMAx == DMA1)
+    {
+      /* Force reset of DMA clock */
+      LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
+
+      /* Release reset of DMA clock */
+      LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
+    }
+    else if (DMAx == DMA2)
+    {
+      /* Force reset of DMA clock */
+       LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2);
+
+      /* Release reset of DMA clock */
+      LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2);
+    }
+    else
+    {
+      status = ERROR;
+    }
+  }
+  else
+  {
+    /* Disable the selected Stream */
+    LL_DMA_DisableStream(DMAx, Stream);
+
+    /* Get the DMA Stream Instance */
+    tmp = (DMA_Stream_TypeDef *)(__LL_DMA_GET_STREAM_INSTANCE(DMAx, Stream));
+
+    /* Reset DMAx_Streamy configuration register */
+    LL_DMA_WriteReg(tmp, CR, 0U);
+
+    /* Reset DMAx_Streamy remaining bytes register */
+    LL_DMA_WriteReg(tmp, NDTR, 0U);
+
+    /* Reset DMAx_Streamy peripheral address register */
+    LL_DMA_WriteReg(tmp, PAR, 0U);
+
+    /* Reset DMAx_Streamy memory address register */
+    LL_DMA_WriteReg(tmp, M0AR, 0U);
+
+    /* Reset DMAx_Streamy memory address register */
+    LL_DMA_WriteReg(tmp, M1AR, 0U);
+
+    /* Reset DMAx_Streamy FIFO control register */
+    LL_DMA_WriteReg(tmp, FCR, 0x00000021U);
+
+    /* Reset Channel register field for DMAx Stream */
+    LL_DMA_SetPeriphRequest(DMAx, Stream, LL_DMAMUX1_REQ_MEM2MEM);
+
+    if (Stream == LL_DMA_STREAM_0)
+    {
+      /* Reset the Stream0 pending flags */
+      DMAx->LIFCR = 0x0000003FU;
+    }
+    else if (Stream == LL_DMA_STREAM_1)
+    {
+      /* Reset the Stream1 pending flags */
+      DMAx->LIFCR = 0x00000F40U;
+    }
+    else if (Stream == LL_DMA_STREAM_2)
+    {
+      /* Reset the Stream2 pending flags */
+      DMAx->LIFCR = 0x003F0000U;
+    }
+    else if (Stream == LL_DMA_STREAM_3)
+    {
+      /* Reset the Stream3 pending flags */
+      DMAx->LIFCR = 0x0F400000U;
+    }
+    else if (Stream == LL_DMA_STREAM_4)
+    {
+      /* Reset the Stream4 pending flags */
+      DMAx->HIFCR = 0x0000003FU;
+    }
+    else if (Stream == LL_DMA_STREAM_5)
+    {
+      /* Reset the Stream5 pending flags */
+      DMAx->HIFCR = 0x00000F40U;
+    }
+    else if (Stream == LL_DMA_STREAM_6)
+    {
+      /* Reset the Stream6 pending flags */
+      DMAx->HIFCR = 0x003F0000U;
+    }
+    else if (Stream == LL_DMA_STREAM_7)
+    {
+      /* Reset the Stream7 pending flags */
+      DMAx->HIFCR = 0x0F400000U;
+    }
+    else
+    {
+      status = ERROR;
+    }
+  }
+
+  return (uint32_t)status;
+}
+
+/**
+  * @brief  Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
+  * @note   To convert DMAx_Streamy Instance to DMAx Instance and Streamy, use helper macros :
+  *         @arg @ref __LL_DMA_GET_INSTANCE
+  *         @arg @ref __LL_DMA_GET_STREAM
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: DMA registers are initialized
+  *          - ERROR: Not applicable
+  */
+uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct)
+{
+  /* Check the DMA Instance DMAx and Stream parameters */
+  assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
+
+  /* Check the DMA parameters from DMA_InitStruct */
+  assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
+  assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
+  assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
+  assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
+  assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
+  assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
+  assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
+  assert_param(IS_LL_DMA_REQUEST(DMA_InitStruct->PeriphRequest));
+  assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
+  assert_param(IS_LL_DMA_FIFO_MODE_STATE(DMA_InitStruct->FIFOMode));
+
+  /* Check the memory burst, peripheral burst and FIFO threshold parameters only
+     when FIFO mode is enabled */
+  if (DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
+  {
+    assert_param(IS_LL_DMA_FIFO_THRESHOLD(DMA_InitStruct->FIFOThreshold));
+    assert_param(IS_LL_DMA_MEMORY_BURST(DMA_InitStruct->MemBurst));
+    assert_param(IS_LL_DMA_PERIPHERAL_BURST(DMA_InitStruct->PeriphBurst));
+  }
+
+  /*---------------------------- DMAx SxCR Configuration ------------------------
+   * Configure DMAx_Streamy: data transfer direction, data transfer mode,
+   *                          peripheral and memory increment mode,
+   *                          data size alignment and  priority level with parameters :
+   * - Direction:      DMA_SxCR_DIR[1:0] bits
+   * - Mode:           DMA_SxCR_CIRC bit
+   * - PeriphOrM2MSrcIncMode:  DMA_SxCR_PINC bit
+   * - MemoryOrM2MDstIncMode:  DMA_SxCR_MINC bit
+   * - PeriphOrM2MSrcDataSize: DMA_SxCR_PSIZE[1:0] bits
+   * - MemoryOrM2MDstDataSize: DMA_SxCR_MSIZE[1:0] bits
+   * - Priority:               DMA_SxCR_PL[1:0] bits
+   */
+  LL_DMA_ConfigTransfer(DMAx, Stream, DMA_InitStruct->Direction | \
+                        DMA_InitStruct->Mode                    | \
+                        DMA_InitStruct->PeriphOrM2MSrcIncMode   | \
+                        DMA_InitStruct->MemoryOrM2MDstIncMode   | \
+                        DMA_InitStruct->PeriphOrM2MSrcDataSize  | \
+                        DMA_InitStruct->MemoryOrM2MDstDataSize  | \
+                        DMA_InitStruct->Priority
+                       );
+
+  if (DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
+  {
+    /*---------------------------- DMAx SxFCR Configuration ------------------------
+     * Configure DMAx_Streamy:  fifo mode and fifo threshold with parameters :
+     * - FIFOMode:                DMA_SxFCR_DMDIS bit
+     * - FIFOThreshold:           DMA_SxFCR_FTH[1:0] bits
+     */
+    LL_DMA_ConfigFifo(DMAx, Stream, DMA_InitStruct->FIFOMode, DMA_InitStruct->FIFOThreshold);
+
+    /*---------------------------- DMAx SxCR Configuration --------------------------
+     * Configure DMAx_Streamy:  memory burst transfer with parameters :
+     * - MemBurst:                DMA_SxCR_MBURST[1:0] bits
+     */
+    LL_DMA_SetMemoryBurstxfer(DMAx, Stream, DMA_InitStruct->MemBurst);
+
+    /*---------------------------- DMAx SxCR Configuration --------------------------
+     * Configure DMAx_Streamy:  peripheral burst transfer with parameters :
+     * - PeriphBurst:             DMA_SxCR_PBURST[1:0] bits
+     */
+    LL_DMA_SetPeriphBurstxfer(DMAx, Stream, DMA_InitStruct->PeriphBurst);
+  }
+
+  /*-------------------------- DMAx SxM0AR Configuration --------------------------
+   * Configure the memory or destination base address with parameter :
+   * - MemoryOrM2MDstAddress:     DMA_SxM0AR_M0A[31:0] bits
+   */
+  LL_DMA_SetMemoryAddress(DMAx, Stream, DMA_InitStruct->MemoryOrM2MDstAddress);
+
+  /*-------------------------- DMAx SxPAR Configuration ---------------------------
+   * Configure the peripheral or source base address with parameter :
+   * - PeriphOrM2MSrcAddress:     DMA_SxPAR_PA[31:0] bits
+   */
+  LL_DMA_SetPeriphAddress(DMAx, Stream, DMA_InitStruct->PeriphOrM2MSrcAddress);
+
+  /*--------------------------- DMAx SxNDTR Configuration -------------------------
+   * Configure the peripheral base address with parameter :
+   * - NbData:                    DMA_SxNDT[15:0] bits
+   */
+  LL_DMA_SetDataLength(DMAx, Stream, DMA_InitStruct->NbData);
+
+  /*--------------------------- DMA SxCR_CHSEL Configuration ----------------------
+   * Configure the peripheral base address with parameter :
+   * - PeriphRequest:             DMA_SxCR_CHSEL[3:0] bits
+   */
+  LL_DMA_SetPeriphRequest(DMAx, Stream, DMA_InitStruct->PeriphRequest);
+
+  return (uint32_t)SUCCESS;
+}
+
+/**
+  * @brief  Set each @ref LL_DMA_InitTypeDef field to default value.
+  * @param  DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
+  * @retval None
+  */
+void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
+{
+  /* Set DMA_InitStruct fields to default values */
+  DMA_InitStruct->PeriphOrM2MSrcAddress  = 0x00000000U;
+  DMA_InitStruct->MemoryOrM2MDstAddress  = 0x00000000U;
+  DMA_InitStruct->Direction              = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
+  DMA_InitStruct->Mode                   = LL_DMA_MODE_NORMAL;
+  DMA_InitStruct->PeriphOrM2MSrcIncMode  = LL_DMA_PERIPH_NOINCREMENT;
+  DMA_InitStruct->MemoryOrM2MDstIncMode  = LL_DMA_MEMORY_NOINCREMENT;
+  DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
+  DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
+  DMA_InitStruct->NbData                 = 0x00000000U;
+  DMA_InitStruct->PeriphRequest          = LL_DMAMUX1_REQ_MEM2MEM;
+  DMA_InitStruct->Priority               = LL_DMA_PRIORITY_LOW;
+  DMA_InitStruct->FIFOMode               = LL_DMA_FIFOMODE_DISABLE;
+  DMA_InitStruct->FIFOThreshold          = LL_DMA_FIFOTHRESHOLD_1_4;
+  DMA_InitStruct->MemBurst               = LL_DMA_MBURST_SINGLE;
+  DMA_InitStruct->PeriphBurst            = LL_DMA_PBURST_SINGLE;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* DMA1 || DMA2 */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_exti.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_exti.c
new file mode 100644
index 00000000..f4c6320d
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_exti.c
@@ -0,0 +1,458 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_exti.c
+  * @author  MCD Application Team
+  * @brief   EXTI LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_ll_exti.h"
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined (EXTI)
+
+/** @defgroup EXTI_LL EXTI
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup EXTI_LL_Private_Macros
+  * @{
+  */
+
+#define IS_LL_EXTI_LINE_0_31(__VALUE__)              (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31)  == 0x00000000U)
+#define IS_LL_EXTI_LINE_32_63(__VALUE__)             (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U)
+#define IS_LL_EXTI_LINE_64_95(__VALUE__)             (((__VALUE__) & ~LL_EXTI_LINE_ALL_64_95) == 0x00000000U)
+
+#define IS_LL_EXTI_MODE(__VALUE__)                   (((__VALUE__) == LL_EXTI_MODE_IT)            \
+                                                   || ((__VALUE__) == LL_EXTI_MODE_EVENT)         \
+                                                   || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
+
+
+#define IS_LL_EXTI_TRIGGER(__VALUE__)                (((__VALUE__) == LL_EXTI_TRIGGER_NONE)       \
+                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_RISING)     \
+                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING)    \
+                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))
+
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup EXTI_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup EXTI_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize the EXTI registers to their default reset values.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: EXTI registers are de-initialized
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_EXTI_DeInit(void)
+{
+  /* Rising Trigger selection register set to default reset values */
+  LL_EXTI_WriteReg(RTSR1,  0x00000000U);
+  LL_EXTI_WriteReg(RTSR2,  0x00000000U);
+  LL_EXTI_WriteReg(RTSR3,  0x00000000U);
+
+  /* Falling Trigger selection register set to default reset values */
+  LL_EXTI_WriteReg(FTSR1,  0x00000000U);
+  LL_EXTI_WriteReg(FTSR2,  0x00000000U);
+  LL_EXTI_WriteReg(FTSR3,  0x00000000U);
+
+  /* Software interrupt event register set to default reset values */
+  LL_EXTI_WriteReg(SWIER1, 0x00000000U);
+  LL_EXTI_WriteReg(SWIER2, 0x00000000U);
+  LL_EXTI_WriteReg(SWIER3, 0x00000000U);
+
+  /* D3 Pending register set to default reset values */
+  LL_EXTI_WriteReg(D3PMR1, 0x00000000U);
+  LL_EXTI_WriteReg(D3PMR2, 0x00000000U);
+  LL_EXTI_WriteReg(D3PMR3, 0x00000000U);
+
+  /* D3 Pending clear selection register low to default reset values */
+  LL_EXTI_WriteReg(D3PCR1L, 0x00000000U);
+  LL_EXTI_WriteReg(D3PCR2L, 0x00000000U);
+  LL_EXTI_WriteReg(D3PCR3L, 0x00000000U);
+
+  /* D3 Pending clear selection register high to default reset values */
+  LL_EXTI_WriteReg(D3PCR1H, 0x00000000U);
+  LL_EXTI_WriteReg(D3PCR2H, 0x00000000U);
+  LL_EXTI_WriteReg(D3PCR3H, 0x00000000U);
+
+  /* Interrupt mask register set to default reset values */
+  LL_EXTI_WriteReg(IMR1, 0x00000000U);
+  LL_EXTI_WriteReg(IMR2, 0x00000000U);
+  LL_EXTI_WriteReg(IMR3, 0x00000000U);
+
+  /*  Event mask register set to default reset values */
+  LL_EXTI_WriteReg(EMR1, 0x00000000U);
+  LL_EXTI_WriteReg(EMR2, 0x00000000U);
+  LL_EXTI_WriteReg(EMR3, 0x00000000U);
+
+  /* Clear Pending requests */
+  LL_EXTI_WriteReg(PR1, EXTI_PR1_PR_Msk);
+  LL_EXTI_WriteReg(PR2, EXTI_PR2_PR_Msk);
+  LL_EXTI_WriteReg(PR3, EXTI_PR3_PR_Msk);
+
+#if defined(DUAL_CORE)
+  /* Interrupt mask register set to default reset values  for Core 2 (Coretx-M4)*/
+  LL_EXTI_WriteReg(C2IMR1, 0x00000000U);
+  LL_EXTI_WriteReg(C2IMR2, 0x00000000U);
+  LL_EXTI_WriteReg(C2IMR3, 0x00000000U);
+
+  /*  Event mask register set to default reset values */
+  LL_EXTI_WriteReg(C2EMR1, 0x00000000U);
+  LL_EXTI_WriteReg(C2EMR2, 0x00000000U);
+  LL_EXTI_WriteReg(C2EMR3, 0x00000000U);
+
+  /* Clear Pending requests */
+  LL_EXTI_WriteReg(C2PR1, EXTI_PR1_PR_Msk);
+  LL_EXTI_WriteReg(C2PR2, EXTI_PR2_PR_Msk);
+  LL_EXTI_WriteReg(C2PR3, EXTI_PR3_PR_Msk);
+
+#endif /* DUAL_CORE*/
+  return SUCCESS;
+}
+
+/**
+  * @brief  Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
+  * @param  EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: EXTI registers are initialized
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
+{
+  ErrorStatus status = SUCCESS;
+  /* Check the parameters */
+  assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31));
+  assert_param(IS_LL_EXTI_LINE_32_63(EXTI_InitStruct->Line_32_63));
+  assert_param(IS_LL_EXTI_LINE_64_95(EXTI_InitStruct->Line_64_95));
+  assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand));
+  assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode));
+
+  /* ENABLE LineCommand */
+  if (EXTI_InitStruct->LineCommand != DISABLE)
+  {
+    assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger));
+
+    /* Configure EXTI Lines in range from 0 to 31 */
+    if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE)
+    {
+      if((EXTI_InitStruct->Mode & LL_EXTI_MODE_IT) == LL_EXTI_MODE_IT)
+      {
+        /* Enable IT on provided Lines for Cortex-M7*/
+        LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
+      }
+      else
+      {
+        /* Disable IT on provided Lines for Cortex-M7*/
+        LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
+      }
+
+      if((EXTI_InitStruct->Mode & LL_EXTI_MODE_EVENT) == LL_EXTI_MODE_EVENT)
+      {
+        /* Enable event on provided Lines for Cortex-M7 */
+        LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
+      }
+      else
+      {
+        /* Disable event on provided Lines for Cortex-M7 */
+        LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
+      }
+#if defined(DUAL_CORE)
+      if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_IT) == LL_EXTI_MODE_C2_IT)
+      {
+        /* Enable IT on provided Lines for Cortex-M4 */
+        LL_C2_EXTI_EnableIT_0_31 (EXTI_InitStruct->Line_0_31);
+      }
+      else
+      {
+        /* Disable IT on provided Lines for Cortex-M4*/
+        LL_C2_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
+      }
+
+      if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_EVENT) == LL_EXTI_MODE_C2_EVENT)
+      {
+        /* Enable event on provided Lines for Cortex-M4 */
+        LL_C2_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
+      }
+      else
+      {
+        /* Disable event on provided Lines for Cortex-M4*/
+        LL_C2_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
+      }
+#endif /* DUAL_CORE */
+
+      if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
+      {
+        switch (EXTI_InitStruct->Trigger)
+        {
+          case LL_EXTI_TRIGGER_RISING:
+            /* First Disable Falling Trigger on provided Lines */
+            LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+            /* Then Enable Rising Trigger on provided Lines */
+            LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+            break;
+          case LL_EXTI_TRIGGER_FALLING:
+            /* First Disable Rising Trigger on provided Lines */
+            LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+            /* Then Enable Falling Trigger on provided Lines */
+            LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+            break;
+          case LL_EXTI_TRIGGER_RISING_FALLING:
+            LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+            LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+            break;
+          default:
+            status = ERROR;
+            break;
+        }
+      }
+    }
+    /* Configure EXTI Lines in range from 32 to 63 */
+    if (EXTI_InitStruct->Line_32_63 != LL_EXTI_LINE_NONE)
+    {
+      if((EXTI_InitStruct->Mode & LL_EXTI_MODE_IT) == LL_EXTI_MODE_IT)
+      {
+        /* Enable IT on provided Lines for Cortex-M7*/
+        LL_EXTI_EnableIT_32_63(EXTI_InitStruct->Line_32_63);
+      }
+      else
+      {
+        /* Disable IT on provided Lines for Cortex-M7*/
+        LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
+      }
+
+      if((EXTI_InitStruct->Mode & LL_EXTI_MODE_EVENT) == LL_EXTI_MODE_EVENT)
+      {
+        /* Enable event on provided Lines for Cortex-M7 */
+        LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63);
+      }
+      else
+      {
+        /* Disable event on provided Lines for Cortex-M7 */
+        LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
+      }
+#if defined(DUAL_CORE)
+      if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_IT) == LL_EXTI_MODE_C2_IT)
+      {
+        /* Enable IT on provided Lines for Cortex-M4 */
+        LL_C2_EXTI_EnableIT_32_63 (EXTI_InitStruct->Line_32_63);
+      }
+      else
+      {
+        /* Disable IT on provided Lines for Cortex-M4 */
+        LL_C2_EXTI_DisableIT_32_63 (EXTI_InitStruct->Line_32_63);
+      }
+
+      if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_EVENT) == LL_EXTI_MODE_C2_EVENT)
+      {
+        /* Enable event on provided Lines for Cortex-M4 */
+        LL_C2_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63);
+      }
+      else
+      {
+        /* Disable event on provided Lines for Cortex-M4 */
+        LL_C2_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
+      }
+#endif /* DUAL_CORE */
+
+      if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
+      {
+        switch (EXTI_InitStruct->Trigger)
+        {
+          case LL_EXTI_TRIGGER_RISING:
+            /* First Disable Falling Trigger on provided Lines */
+            LL_EXTI_DisableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
+            /* Then Enable IT on provided Lines */
+            LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
+            break;
+          case LL_EXTI_TRIGGER_FALLING:
+            /* First Disable Rising Trigger on provided Lines */
+            LL_EXTI_DisableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
+            /* Then Enable Falling Trigger on provided Lines */
+            LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
+            break;
+          case LL_EXTI_TRIGGER_RISING_FALLING:
+            LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
+            LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
+            break;
+          default:
+            status = ERROR;
+            break;
+        }
+      }
+    }
+    /* Configure EXTI Lines in range from 64 to 95 */
+    if (EXTI_InitStruct->Line_64_95 != LL_EXTI_LINE_NONE)
+    {
+      if((EXTI_InitStruct->Mode & LL_EXTI_MODE_IT) == LL_EXTI_MODE_IT)
+      {
+        /* Enable IT on provided Lines for Cortex-M7*/
+        LL_EXTI_EnableIT_64_95(EXTI_InitStruct->Line_64_95);
+      }
+      else
+      {
+        /* Disable IT on provided Lines for Cortex-M7*/
+        LL_EXTI_DisableIT_64_95(EXTI_InitStruct->Line_64_95);
+      }
+
+      if((EXTI_InitStruct->Mode & LL_EXTI_MODE_EVENT) == LL_EXTI_MODE_EVENT)
+      {
+        /* Enable event on provided Lines for Cortex-M7 */
+        LL_EXTI_EnableEvent_64_95(EXTI_InitStruct->Line_64_95);
+      }
+      else
+      {
+        /* Disable event on provided Lines for Cortex-M7 */
+        LL_EXTI_DisableEvent_64_95(EXTI_InitStruct->Line_64_95);
+      }
+
+#if defined(DUAL_CORE)
+      if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_IT) == LL_EXTI_MODE_C2_IT)
+      {
+        /* Enable IT on provided Lines for Cortex-M4 */
+        LL_C2_EXTI_EnableIT_64_95 (EXTI_InitStruct->Line_64_95);
+      }
+      else
+      {
+        /* Disable IT on provided Lines for Cortex-M4 */
+        LL_C2_EXTI_DisableIT_64_95 (EXTI_InitStruct->Line_64_95);
+      }
+
+      if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_EVENT) == LL_EXTI_MODE_C2_EVENT)
+      {
+        /* Enable event on provided Lines for Cortex-M4 */
+        LL_C2_EXTI_EnableEvent_64_95(EXTI_InitStruct->Line_64_95);
+      }
+      else
+      {
+        /* Disable event on provided Lines for Cortex-M4 */
+        LL_C2_EXTI_DisableEvent_64_95(EXTI_InitStruct->Line_64_95);
+      }
+#endif /* DUAL_CORE */
+
+      if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
+      {
+        switch (EXTI_InitStruct->Trigger)
+        {
+          case LL_EXTI_TRIGGER_RISING:
+            /* First Disable Falling Trigger on provided Lines */
+            LL_EXTI_DisableFallingTrig_64_95(EXTI_InitStruct->Line_64_95);
+            /* Then Enable IT on provided Lines */
+            LL_EXTI_EnableRisingTrig_64_95(EXTI_InitStruct->Line_64_95);
+            break;
+          case LL_EXTI_TRIGGER_FALLING:
+            /* First Disable Rising Trigger on provided Lines */
+            LL_EXTI_DisableRisingTrig_64_95(EXTI_InitStruct->Line_64_95);
+            /* Then Enable Falling Trigger on provided Lines */
+            LL_EXTI_EnableFallingTrig_64_95(EXTI_InitStruct->Line_64_95);
+            break;
+          case LL_EXTI_TRIGGER_RISING_FALLING:
+            LL_EXTI_EnableRisingTrig_64_95(EXTI_InitStruct->Line_64_95);
+            LL_EXTI_EnableFallingTrig_64_95(EXTI_InitStruct->Line_64_95);
+            break;
+          default:
+            status = ERROR;
+            break;
+        }
+      }
+    }
+  }
+  else /* DISABLE LineCommand */
+  {
+    /* Disable IT on provided Lines for Cortex-M7*/
+    LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
+    LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
+    LL_EXTI_DisableIT_64_95(EXTI_InitStruct->Line_64_95);
+
+    /* Disable event on provided Lines for Cortex-M7 */
+    LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
+    LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
+    LL_EXTI_DisableEvent_64_95(EXTI_InitStruct->Line_64_95);
+
+#if defined(DUAL_CORE)
+    /* Disable IT on provided Lines for Cortex-M4*/
+    LL_C2_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
+    LL_C2_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
+    LL_C2_EXTI_DisableIT_64_95(EXTI_InitStruct->Line_64_95);
+
+    /* Disable event on provided Lines for Cortex-M4 */
+    LL_C2_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
+    LL_C2_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
+    LL_C2_EXTI_DisableEvent_64_95(EXTI_InitStruct->Line_64_95);
+#endif /* DUAL_CORE */
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_EXTI_InitTypeDef field to default value.
+  * @param  EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure.
+  * @retval None
+  */
+void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct)
+{
+  EXTI_InitStruct->Line_0_31      = LL_EXTI_LINE_NONE;
+  EXTI_InitStruct->Line_32_63     = LL_EXTI_LINE_NONE;
+  EXTI_InitStruct->Line_64_95     = LL_EXTI_LINE_NONE;
+  EXTI_InitStruct->LineCommand    = DISABLE;
+  EXTI_InitStruct->Mode           = LL_EXTI_MODE_IT;
+  EXTI_InitStruct->Trigger        = LL_EXTI_TRIGGER_FALLING;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (EXTI) */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_gpio.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_gpio.c
new file mode 100644
index 00000000..176e27f8
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_gpio.c
@@ -0,0 +1,307 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_gpio.c
+  * @author  MCD Application Team
+  * @brief   GPIO LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+  
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_ll_gpio.h"
+#include "stm32h7xx_ll_bus.h"
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK)
+
+/** @addtogroup GPIO_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup GPIO_LL_Private_Macros
+  * @{
+  */
+#define IS_LL_GPIO_PIN(__VALUE__)          (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
+
+#define IS_LL_GPIO_MODE(__VALUE__)         (((__VALUE__) == LL_GPIO_MODE_INPUT)     ||\
+                                            ((__VALUE__) == LL_GPIO_MODE_OUTPUT)    ||\
+                                            ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\
+                                            ((__VALUE__) == LL_GPIO_MODE_ANALOG))
+
+#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__)  (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL)  ||\
+                                            ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))
+
+#define IS_LL_GPIO_SPEED(__VALUE__)        (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW)       ||\
+                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM)    ||\
+                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH)      ||\
+                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH))
+
+#define IS_LL_GPIO_PULL(__VALUE__)         (((__VALUE__) == LL_GPIO_PULL_NO)   ||\
+                                            ((__VALUE__) == LL_GPIO_PULL_UP)   ||\
+                                            ((__VALUE__) == LL_GPIO_PULL_DOWN))
+
+#define IS_LL_GPIO_ALTERNATE(__VALUE__)    (((__VALUE__) == LL_GPIO_AF_0  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_1  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_2  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_3  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_4  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_5  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_6  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_7  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_8  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_9  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_10 )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_11 )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_12 )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_13 )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_14 )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_15 ))
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup GPIO_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup GPIO_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize GPIO registers (Registers restored to their default values).
+  * @param  GPIOx GPIO Port
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: GPIO registers are de-initialized
+  *          - ERROR:   Wrong GPIO Port
+  */
+ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+
+  /* Force and Release reset on clock of GPIOx Port */
+  if (GPIOx == GPIOA)
+  {
+    LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOA);
+    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOA);
+  }
+  else if (GPIOx == GPIOB)
+  {
+    LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOB);
+    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOB);
+  }
+  else if (GPIOx == GPIOC)
+  {
+    LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOC);
+    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOC);
+  }
+#if defined(GPIOD)
+  else if (GPIOx == GPIOD)
+  {
+    LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOD);
+    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOD);
+  }
+#endif /* GPIOD */
+#if defined(GPIOE)
+  else if (GPIOx == GPIOE)
+  {
+    LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOE);
+    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOE);
+  }
+#endif /* GPIOE */
+#if defined(GPIOF)
+  else if (GPIOx == GPIOF)
+  {
+    LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOF);
+    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOF);
+  }
+#endif /* GPIOF */
+#if defined(GPIOG)
+  else if (GPIOx == GPIOG)
+  {
+    LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOG);
+    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOG);
+  }
+#endif /* GPIOG */
+#if defined(GPIOH)
+  else if (GPIOx == GPIOH)
+  {
+    LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOH);
+    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOH);
+  }
+#endif /* GPIOH */
+#if defined(GPIOI)
+  else if (GPIOx == GPIOI)
+  {
+    LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOI);
+    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOI);
+  }
+#endif /* GPIOI */
+#if defined(GPIOJ)
+  else if (GPIOx == GPIOJ)
+  {
+    LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOJ);
+    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOJ);
+  }
+#endif /* GPIOJ */
+#if defined(GPIOK)
+  else if (GPIOx == GPIOK)
+  {
+    LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOK);
+    LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOK);
+  }
+#endif /* GPIOK */
+  else
+  {
+    status = ERROR;
+  }
+
+  return (status);
+}
+
+/**
+  * @brief  Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
+  * @param  GPIOx GPIO Port
+  * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
+  *         that contains the configuration information for the specified GPIO peripheral.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
+  *          - ERROR:   Not applicable
+  */
+ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
+{
+  uint32_t pinpos, currentpin;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin));
+  assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode));
+  assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull));
+
+  /* ------------------------- Configure the port pins ---------------- */
+  /* Initialize  pinpos on first pin set */
+  pinpos = POSITION_VAL(GPIO_InitStruct->Pin);
+
+  /* Configure the port pins */
+  while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U)
+  {
+    /* Get current io position */
+    currentpin = (GPIO_InitStruct->Pin) & (0x00000001UL << pinpos);
+
+    if (currentpin != 0x00000000U)
+    {
+
+      if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
+      {
+        /* Check Speed mode parameters */
+        assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed));
+
+        /* Speed mode configuration */
+        LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
+
+        /* Check Output mode parameters */
+        assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
+
+        /* Output mode configuration*/
+        LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);
+
+      }
+
+      /* Pull-up Pull down resistor configuration*/
+      LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull);
+
+      if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)
+      {
+        /* Check Alternate parameter */
+        assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate));
+
+        /* Alternate function configuration */
+        if (currentpin < LL_GPIO_PIN_8)
+        {
+          LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate);
+        }
+        else
+        {
+          LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate);
+        }
+      }
+
+      /* Pin Mode configuration */
+      LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
+    }
+    pinpos++;
+  }
+
+  return (SUCCESS);
+}
+
+/**
+  * @brief Set each @ref LL_GPIO_InitTypeDef field to default value.
+  * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
+  *                          whose fields will be set to default values.
+  * @retval None
+  */
+
+void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct)
+{
+  /* Reset GPIO init structure parameters values */
+  GPIO_InitStruct->Pin        = LL_GPIO_PIN_ALL;
+  GPIO_InitStruct->Mode       = LL_GPIO_MODE_ANALOG;
+  GPIO_InitStruct->Speed      = LL_GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct->Pull       = LL_GPIO_PULL_NO;
+  GPIO_InitStruct->Alternate  = LL_GPIO_AF_0;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_rcc.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_rcc.c
new file mode 100644
index 00000000..699cd0ff
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_rcc.c
@@ -0,0 +1,1770 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_rcc.c
+  * @author  MCD Application Team
+  * @brief   RCC LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_ll_rcc.h"
+#include "stm32h7xx_ll_bus.h"
+#ifdef  USE_FULL_ASSERT
+  #include "stm32_assert.h"
+#else
+  #define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined(RCC)
+
+/** @addtogroup RCC_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+const uint8_t LL_RCC_PrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RCC_LL_Private_Macros
+  * @{
+  */
+#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_USART16_CLKSOURCE) \
+                                            || ((__VALUE__) == LL_RCC_USART234578_CLKSOURCE))
+
+
+#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_I2C123_CLKSOURCE) \
+                                            || ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE))
+
+#define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE)  \
+                                            || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE)  \
+                                            || ((__VALUE__) == LL_RCC_LPTIM345_CLKSOURCE))
+
+#if defined(LL_RCC_SAI4A_CLKSOURCE)
+#define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
+                                            || ((__VALUE__) == LL_RCC_SAI23_CLKSOURCE) \
+                                            || ((__VALUE__) == LL_RCC_SAI4A_CLKSOURCE) \
+                                            || ((__VALUE__) == LL_RCC_SAI4B_CLKSOURCE))
+#else
+#define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
+                                            || ((__VALUE__) == LL_RCC_SAI2A_CLKSOURCE) \
+                                            || ((__VALUE__) == LL_RCC_SAI2B_CLKSOURCE))
+#endif /* LL_RCC_SAI4A_CLKSOURCE */
+
+#define IS_LL_RCC_SPI_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_SPI123_CLKSOURCE) \
+                                            || ((__VALUE__) == LL_RCC_SPI45_CLKSOURCE) \
+                                            || ((__VALUE__) == LL_RCC_SPI6_CLKSOURCE))
+
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup RCC_LL_Private_Functions RCC Private functions
+  * @{
+  */
+uint32_t RCC_GetSystemClockFreq(void);
+uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
+uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
+uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
+uint32_t RCC_GetPCLK3ClockFreq(uint32_t HCLK_Frequency);
+uint32_t RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency);
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCC_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup RCC_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  Resets the RCC clock configuration to the default reset state.
+  * @note   The default reset state of the clock configuration is given below:
+  *            - HSI ON and used as system clock source
+  *            - HSE, PLL1, PLL2 and PLL3 OFF
+  *            - AHB, APB Bus pre-scaler set to 1.
+  *            - CSS, MCO1 and MCO2 OFF
+  *            - All interrupts disabled
+  * @note   This function doesn't modify the configuration of the
+  *            - Peripheral clocks
+  *            - LSI, LSE and RTC clocks
+  * @retval None
+  */
+void LL_RCC_DeInit(void)
+{
+  /* Set HSION bit */
+  SET_BIT(RCC->CR, RCC_CR_HSION);
+
+  /* Wait for HSI READY bit */
+  while(LL_RCC_HSI_IsReady() == 0U)
+  {}
+
+  /* Reset CFGR register */
+  CLEAR_REG(RCC->CFGR);
+
+  /* Reset CSION , CSIKERON, HSEON, HSI48ON, HSECSSON,HSIDIV, PLL1ON, PLL2ON, PLL3ON bits */
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSIKERON| RCC_CR_HSIDIV| RCC_CR_HSIDIVF| RCC_CR_CSION | RCC_CR_CSIKERON |  RCC_CR_HSI48ON  \
+  |RCC_CR_CSSHSEON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON);
+
+  /* Wait for PLL1 READY bit to be reset */
+  while(LL_RCC_PLL1_IsReady() != 0U)
+  {}
+
+  /* Wait for PLL2 READY bit to be reset */
+  while(LL_RCC_PLL2_IsReady() != 0U)
+  {}
+
+  /* Wait for PLL3 READY bit to be reset */
+  while(LL_RCC_PLL3_IsReady() != 0U)
+  {}
+
+#if defined(RCC_D1CFGR_HPRE)
+  /* Reset D1CFGR register */
+  CLEAR_REG(RCC->D1CFGR);
+
+  /* Reset D2CFGR register */
+  CLEAR_REG(RCC->D2CFGR);
+
+  /* Reset D3CFGR register */
+  CLEAR_REG(RCC->D3CFGR);
+#else
+  /* Reset CDCFGR1 register */
+  CLEAR_REG(RCC->CDCFGR1);
+
+  /* Reset CDCFGR2 register */
+  CLEAR_REG(RCC->CDCFGR2);
+
+  /* Reset SRDCFGR register */
+  CLEAR_REG(RCC->SRDCFGR);
+
+#endif /* RCC_D1CFGR_HPRE */
+
+  /* Reset PLLCKSELR register to default value */
+  RCC->PLLCKSELR= RCC_PLLCKSELR_DIVM1_5|RCC_PLLCKSELR_DIVM2_5|RCC_PLLCKSELR_DIVM3_5;
+
+  /* Reset PLLCFGR register to default value */
+  LL_RCC_WriteReg(PLLCFGR, 0x01FF0000U);
+
+  /* Reset PLL1DIVR register to default value */
+  LL_RCC_WriteReg(PLL1DIVR, 0x01010280U);
+
+  /* Reset PLL1FRACR register */
+  CLEAR_REG(RCC->PLL1FRACR);
+
+  /* Reset PLL2DIVR register to default value */
+  LL_RCC_WriteReg(PLL2DIVR, 0x01010280U);
+
+  /* Reset PLL2FRACR register */
+  CLEAR_REG(RCC->PLL2FRACR);
+
+  /* Reset PLL3DIVR register to default value */
+  LL_RCC_WriteReg(PLL3DIVR, 0x01010280U);
+
+  /* Reset PLL3FRACR register */
+  CLEAR_REG(RCC->PLL3FRACR);
+
+  /* Reset HSEBYP bit */
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
+
+  /* Disable all interrupts */
+  CLEAR_REG(RCC->CIER);
+
+  /* Clear all interrupts */
+  SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC | RCC_CICR_LSERDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC
+                   | RCC_CICR_CSIRDYC | RCC_CICR_HSI48RDYC | RCC_CICR_PLLRDYC | RCC_CICR_PLL2RDYC
+                   | RCC_CICR_PLL3RDYC | RCC_CICR_LSECSSC | RCC_CICR_HSECSSC);
+
+  /* Clear reset source flags */
+  SET_BIT(RCC->RSR, RCC_RSR_RMVF);
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup RCC_LL_EF_Get_Freq
+  * @brief  Return the frequencies of different on chip clocks;  System, AHB, APB1, APB2, APB3 and APB4 buses clocks.
+  *         and different peripheral clocks available on the device.
+  * @note   If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
+  * @note   If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
+  * @note   If SYSCLK source is CSI, function returns values based on CSI_VALUE(***)
+  * @note   If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
+  *         or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  * @note   (*) HSI_VALUE is a constant defined in header file (default value
+  *             64 MHz) divider by HSIDIV, but the real value may vary depending on
+  *             on the variations in voltage and temperature.
+  * @note   (**) HSE_VALUE is a constant defined in header file (default value
+  *              25 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  * @note   (***) CSI_VALUE is a constant defined in header file (default value
+  *               4 MHz) but the real value may vary depending on the variations
+  *               in voltage and temperature.
+  * @note   The result of this function could be incorrect when using fractional
+  *         value for HSE crystal.
+  * @note   This function can be used by the user application to compute the
+  *         baud-rate for the communication peripherals or configure other parameters.
+  * @{
+  */
+
+/**
+  * @brief  Return the frequencies of different on chip clocks;  System, AHB, APB1, APB2, APB3 and APB4 buses clocks.
+  * @note   Each time SYSCLK, HCLK, PCLK1, PCLK2, PCLK3 and/or PCLK4 clock changes, this function
+  *         must be called to update structure fields. Otherwise, any
+  *         configuration based on this function will be incorrect.
+  * @param  RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
+  * @retval None
+  */
+void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
+{
+  /* Get SYSCLK frequency */
+  RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
+
+  /* HCLK clock frequency */
+  RCC_Clocks->HCLK_Frequency   = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
+
+  /* PCLK1 clock frequency */
+  RCC_Clocks->PCLK1_Frequency  = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
+
+  /* PCLK2 clock frequency */
+  RCC_Clocks->PCLK2_Frequency  = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
+
+  /* PCLK3 clock frequency */
+  RCC_Clocks->PCLK3_Frequency  = RCC_GetPCLK3ClockFreq(RCC_Clocks->HCLK_Frequency);
+
+  /* PCLK4 clock frequency */
+  RCC_Clocks->PCLK4_Frequency  = RCC_GetPCLK4ClockFreq(RCC_Clocks->HCLK_Frequency);
+}
+
+/**
+  * @brief  Return PLL1 clocks frequencies
+  * @note   LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
+  * @retval None
+  */
+void LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks)
+{
+  uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO, pllsource;
+  uint32_t m, n, fracn = 0U;
+
+  /* PLL_VCO = (HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
+     SYSCLK = PLL_VCO / PLLP
+  */
+  pllsource = LL_RCC_PLL_GetSource();
+
+  switch (pllsource)
+  {
+    case LL_RCC_PLLSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
+      }
+      break;
+
+    case LL_RCC_PLLSOURCE_CSI:
+      if (LL_RCC_CSI_IsReady() != 0U)
+      {
+        pllinputfreq = CSI_VALUE;
+      }
+      break;
+
+    case LL_RCC_PLLSOURCE_HSE:
+      if (LL_RCC_HSE_IsReady() != 0U)
+      {
+        pllinputfreq = HSE_VALUE;
+      }
+      break;
+
+    case LL_RCC_PLLSOURCE_NONE:
+    default:
+      /* PLL clock disabled */
+      break;
+  }
+
+  PLL_Clocks->PLL_P_Frequency = 0U;
+  PLL_Clocks->PLL_Q_Frequency = 0U;
+  PLL_Clocks->PLL_R_Frequency = 0U;
+
+  m = LL_RCC_PLL1_GetM();
+  n = LL_RCC_PLL1_GetN();
+  if (LL_RCC_PLL1FRACN_IsEnabled() != 0U)
+  {
+    fracn = LL_RCC_PLL1_GetFRACN();
+  }
+
+  if (m != 0U)
+  {
+    if (LL_RCC_PLL1P_IsEnabled() != 0U)
+    {
+      PLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL1_GetP());
+    }
+
+    if (LL_RCC_PLL1Q_IsEnabled() != 0U)
+    {
+      PLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL1_GetQ());
+    }
+
+    if (LL_RCC_PLL1R_IsEnabled() != 0U)
+    {
+      PLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL1_GetR());
+    }
+  }
+}
+
+/**
+  * @brief  Return PLL2 clocks frequencies
+  * @note   LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
+  * @retval None
+  */
+void LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks)
+{
+  uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO, pllsource;
+  uint32_t m, n, fracn = 0U;
+
+  /* PLL_VCO = (HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
+     SYSCLK = PLL_VCO / PLLP
+  */
+  pllsource = LL_RCC_PLL_GetSource();
+
+  switch (pllsource)
+  {
+    case LL_RCC_PLLSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
+      }
+      break;
+
+    case LL_RCC_PLLSOURCE_CSI:
+      if (LL_RCC_CSI_IsReady() != 0U)
+      {
+        pllinputfreq = CSI_VALUE;
+      }
+      break;
+
+    case LL_RCC_PLLSOURCE_HSE:
+      if (LL_RCC_HSE_IsReady() != 0U)
+      {
+        pllinputfreq = HSE_VALUE;
+      }
+      break;
+
+    case LL_RCC_PLLSOURCE_NONE:
+    default:
+      /* PLL clock disabled */
+      break;
+  }
+
+  PLL_Clocks->PLL_P_Frequency = 0U;
+  PLL_Clocks->PLL_Q_Frequency = 0U;
+  PLL_Clocks->PLL_R_Frequency = 0U;
+
+  m = LL_RCC_PLL2_GetM();
+  n = LL_RCC_PLL2_GetN();
+  if (LL_RCC_PLL2FRACN_IsEnabled() != 0U)
+  {
+    fracn = LL_RCC_PLL2_GetFRACN();
+  }
+
+  if (m != 0U)
+  {
+    if (LL_RCC_PLL2P_IsEnabled() != 0U)
+    {
+      PLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL2_GetP());
+    }
+
+    if (LL_RCC_PLL2Q_IsEnabled() != 0U)
+    {
+      PLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL2_GetQ());
+    }
+
+    if (LL_RCC_PLL2R_IsEnabled() != 0U)
+    {
+      PLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL2_GetR());
+    }
+  }
+}
+
+/**
+  * @brief  Return PLL3 clocks frequencies
+  * @note   LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
+  * @retval None
+  */
+void LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks)
+{
+  uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO, pllsource;
+  uint32_t m, n, fracn = 0U;
+
+  /* PLL_VCO = (HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
+     SYSCLK = PLL_VCO / PLLP
+  */
+  pllsource = LL_RCC_PLL_GetSource();
+
+  switch (pllsource)
+  {
+    case LL_RCC_PLLSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
+      }
+      break;
+
+    case LL_RCC_PLLSOURCE_CSI:
+      if (LL_RCC_CSI_IsReady() != 0U)
+      {
+        pllinputfreq = CSI_VALUE;
+      }
+      break;
+
+    case LL_RCC_PLLSOURCE_HSE:
+      if (LL_RCC_HSE_IsReady() != 0U)
+      {
+        pllinputfreq = HSE_VALUE;
+      }
+      break;
+
+    case LL_RCC_PLLSOURCE_NONE:
+    default:
+      /* PLL clock disabled */
+      break;
+  }
+
+  PLL_Clocks->PLL_P_Frequency = 0U;
+  PLL_Clocks->PLL_Q_Frequency = 0U;
+  PLL_Clocks->PLL_R_Frequency = 0U;
+
+  m = LL_RCC_PLL3_GetM();
+  n = LL_RCC_PLL3_GetN();
+  if (LL_RCC_PLL3FRACN_IsEnabled() != 0U)
+  {
+    fracn = LL_RCC_PLL3_GetFRACN();
+  }
+
+  if ((m != 0U) && (pllinputfreq != 0U))
+  {
+    if (LL_RCC_PLL3P_IsEnabled() != 0U)
+    {
+      PLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL3_GetP());
+    }
+
+    if (LL_RCC_PLL3Q_IsEnabled() != 0U)
+    {
+      PLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL3_GetQ());
+    }
+
+    if (LL_RCC_PLL3R_IsEnabled() != 0U)
+    {
+      PLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL3_GetR());
+    }
+  }
+}
+
+/**
+  * @brief  Helper function to calculate the PLL frequency output
+  * @note ex: @ref LL_RCC_CalcPLLClockFreq (HSE_VALUE, @ref LL_RCC_PLL1_GetM (),
+  *             @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetFRACN (), @ref LL_RCC_PLL1_GetP ());
+  * @param  PLLInputFreq PLL Input frequency (based on HSE/(HSI/HSIDIV)/CSI)
+  * @param  M      Between 1 and 63
+  * @param  N      Between 4 and 512
+  * @param  FRACN  Between 0 and 0x1FFF
+  * @param  PQR    VCO output divider (P, Q or R)
+  *                Between 1 and 128, except for PLL1P Odd value not allowed
+  * @retval PLL1 clock frequency (in Hz)
+  */
+uint32_t LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t PQR)
+{
+  float_t freq;
+
+  freq = ((float_t)PLLInputFreq / (float_t)M) * ((float_t)N + ((float_t)FRACN/(float_t)0x2000));
+
+  freq = freq/(float_t)PQR;
+
+  return (uint32_t)freq;
+}
+
+/**
+  * @brief  Return USARTx clock frequency
+  * @param  USARTxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USART16_CLKSOURCE
+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE
+  * @retval USART clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
+{
+  uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  LL_PLL_ClocksTypeDef PLL_Clocks;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
+
+  switch (LL_RCC_GetUSARTClockSource(USARTxSource))
+  {
+    case LL_RCC_USART16_CLKSOURCE_PCLK2:
+      usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+      break;
+
+    case LL_RCC_USART234578_CLKSOURCE_PCLK1:
+      usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+      break;
+
+    case LL_RCC_USART16_CLKSOURCE_PLL2Q:
+    case LL_RCC_USART234578_CLKSOURCE_PLL2Q:
+      if (LL_RCC_PLL2_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
+        usart_frequency = PLL_Clocks.PLL_Q_Frequency;
+      }
+      break;
+
+    case LL_RCC_USART16_CLKSOURCE_PLL3Q:
+    case LL_RCC_USART234578_CLKSOURCE_PLL3Q:
+      if (LL_RCC_PLL3_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
+        usart_frequency = PLL_Clocks.PLL_Q_Frequency;
+      }
+      break;
+
+    case LL_RCC_USART16_CLKSOURCE_HSI:
+    case LL_RCC_USART234578_CLKSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        usart_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
+      }
+      break;
+
+    case LL_RCC_USART16_CLKSOURCE_CSI:
+    case LL_RCC_USART234578_CLKSOURCE_CSI:
+      if (LL_RCC_CSI_IsReady() != 0U)
+      {
+        usart_frequency = CSI_VALUE;
+      }
+      break;
+
+    case LL_RCC_USART16_CLKSOURCE_LSE:
+    case LL_RCC_USART234578_CLKSOURCE_LSE:
+      if (LL_RCC_LSE_IsReady() != 0U)
+      {
+        usart_frequency = LSE_VALUE;
+      }
+      break;
+
+    default:
+      /* Kernel clock disabled */
+      break;
+  }
+
+  return usart_frequency;
+}
+
+/**
+  * @brief  Return LPUART clock frequency
+  * @param  LPUARTxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE
+  * @retval LPUART clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)
+{
+  uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  LL_PLL_ClocksTypeDef PLL_Clocks;
+
+  switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))
+  {
+    case LL_RCC_LPUART1_CLKSOURCE_PCLK4:
+      lpuart_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+      break;
+
+    case LL_RCC_LPUART1_CLKSOURCE_PLL2Q:
+      if (LL_RCC_PLL2_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
+        lpuart_frequency = PLL_Clocks.PLL_Q_Frequency;
+      }
+      break;
+
+    case LL_RCC_LPUART1_CLKSOURCE_PLL3Q:
+      if (LL_RCC_PLL3_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
+        lpuart_frequency = PLL_Clocks.PLL_Q_Frequency;
+      }
+      break;
+
+    case LL_RCC_LPUART1_CLKSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        lpuart_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
+      }
+      break;
+
+    case LL_RCC_LPUART1_CLKSOURCE_CSI:
+      if (LL_RCC_CSI_IsReady() != 0U)
+      {
+        lpuart_frequency = CSI_VALUE;
+      }
+      break;
+
+    case LL_RCC_LPUART1_CLKSOURCE_LSE:
+      if (LL_RCC_LSE_IsReady() != 0U)
+      {
+        lpuart_frequency = LSE_VALUE;
+      }
+      break;
+
+    default:
+      /* Kernel clock disabled */
+      break;
+  }
+
+  return lpuart_frequency;
+}
+
+/**
+  * @brief  Return I2Cx clock frequency
+  * @param  I2CxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE
+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE
+  * @retval I2C clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
+{
+  uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  LL_PLL_ClocksTypeDef PLL_Clocks;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
+
+  switch (LL_RCC_GetI2CClockSource(I2CxSource))
+  {
+    case LL_RCC_I2C123_CLKSOURCE_PCLK1:
+      i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+      break;
+
+    case LL_RCC_I2C4_CLKSOURCE_PCLK4:
+      i2c_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+      break;
+
+    case LL_RCC_I2C123_CLKSOURCE_PLL3R:
+    case LL_RCC_I2C4_CLKSOURCE_PLL3R:
+      if (LL_RCC_PLL3_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
+        i2c_frequency = PLL_Clocks.PLL_R_Frequency;
+      }
+      break;
+
+    case LL_RCC_I2C123_CLKSOURCE_HSI:
+    case LL_RCC_I2C4_CLKSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        i2c_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
+      }
+      break;
+
+    case LL_RCC_I2C123_CLKSOURCE_CSI:
+    case LL_RCC_I2C4_CLKSOURCE_CSI:
+      if (LL_RCC_CSI_IsReady() != 0U)
+      {
+        i2c_frequency = CSI_VALUE;
+      }
+      break;
+
+    default:
+      /* Nothing to do */
+      break;
+  }
+
+  return i2c_frequency;
+}
+
+/**
+  * @brief  Return LPTIMx clock frequency
+  * @param  LPTIMxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE
+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE
+  * @retval LPTIM clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
+{
+  uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  LL_PLL_ClocksTypeDef PLL_Clocks;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
+
+  switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
+  {
+    case LL_RCC_LPTIM1_CLKSOURCE_PCLK1:
+      lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+      break;
+
+    case LL_RCC_LPTIM2_CLKSOURCE_PCLK4:
+    case LL_RCC_LPTIM345_CLKSOURCE_PCLK4:
+      lptim_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+      break;
+
+    case LL_RCC_LPTIM1_CLKSOURCE_PLL2P:
+    case LL_RCC_LPTIM2_CLKSOURCE_PLL2P:
+    case LL_RCC_LPTIM345_CLKSOURCE_PLL2P:
+      if (LL_RCC_PLL2_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
+        lptim_frequency = PLL_Clocks.PLL_P_Frequency;
+      }
+      break;
+
+    case LL_RCC_LPTIM1_CLKSOURCE_PLL3R:
+    case LL_RCC_LPTIM2_CLKSOURCE_PLL3R:
+    case LL_RCC_LPTIM345_CLKSOURCE_PLL3R:
+      if (LL_RCC_PLL3_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
+        lptim_frequency = PLL_Clocks.PLL_R_Frequency;
+      }
+      break;
+
+    case LL_RCC_LPTIM1_CLKSOURCE_LSE:
+    case LL_RCC_LPTIM2_CLKSOURCE_LSE:
+    case LL_RCC_LPTIM345_CLKSOURCE_LSE:
+      if (LL_RCC_LSE_IsReady() != 0U)
+      {
+        lptim_frequency = LSE_VALUE;
+      }
+      break;
+
+    case LL_RCC_LPTIM1_CLKSOURCE_LSI:
+    case LL_RCC_LPTIM2_CLKSOURCE_LSI:
+    case LL_RCC_LPTIM345_CLKSOURCE_LSI:
+      if (LL_RCC_LSI_IsReady() != 0U)
+      {
+        lptim_frequency = LSI_VALUE;
+      }
+      break;
+
+    case LL_RCC_LPTIM1_CLKSOURCE_CLKP:
+    case LL_RCC_LPTIM2_CLKSOURCE_CLKP:
+    case LL_RCC_LPTIM345_CLKSOURCE_CLKP:
+      lptim_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    default:
+      /* Kernel clock disabled */
+      break;
+  }
+
+  return lptim_frequency;
+}
+
+/**
+  * @brief  Return SAIx clock frequency
+  * @param  SAIxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE (*)
+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE (*)
+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE (*)
+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE (*)
+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE (*)
+  * @retval SAI clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  *
+  * (*) : Available on some STM32H7 lines only.
+  */
+uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
+{
+  uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  LL_PLL_ClocksTypeDef PLL_Clocks;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
+
+  switch (LL_RCC_GetSAIClockSource(SAIxSource))
+  {
+    case LL_RCC_SAI1_CLKSOURCE_PLL1Q:
+#if defined(SAI3)
+    case LL_RCC_SAI23_CLKSOURCE_PLL1Q:
+#endif /* SAI3 */
+#if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
+    case LL_RCC_SAI2A_CLKSOURCE_PLL1Q:
+    case LL_RCC_SAI2B_CLKSOURCE_PLL1Q:
+#endif /* (RCC_CDCCIP1R_SAI2ASEL) || (RCC_CDCCIP1R_SAI2BSEL) */
+#if defined(SAI4_Block_A) || defined(SAI4_Block_B)
+    case LL_RCC_SAI4A_CLKSOURCE_PLL1Q:
+    case LL_RCC_SAI4B_CLKSOURCE_PLL1Q:
+#endif /* (SAI4_Block_A) || (SAI4_Block_B) */
+      if (LL_RCC_PLL1_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
+        sai_frequency = PLL_Clocks.PLL_Q_Frequency;
+      }
+      break;
+
+    case LL_RCC_SAI1_CLKSOURCE_PLL2P:
+#if defined(SAI3)
+    case LL_RCC_SAI23_CLKSOURCE_PLL2P:
+#endif /* SAI3 */
+#if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
+    case LL_RCC_SAI2A_CLKSOURCE_PLL2P:
+    case LL_RCC_SAI2B_CLKSOURCE_PLL2P:
+#endif /* (RCC_CDCCIP1R_SAI2ASEL) || (RCC_CDCCIP1R_SAI2BSEL) */
+#if defined(SAI4_Block_A) || defined(SAI4_Block_B)
+    case LL_RCC_SAI4A_CLKSOURCE_PLL2P:
+    case LL_RCC_SAI4B_CLKSOURCE_PLL2P:
+#endif /* (SAI2_Block_A_BASE) || (SAI2_Block_B_BASE) */
+      if (LL_RCC_PLL2_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
+        sai_frequency = PLL_Clocks.PLL_P_Frequency;
+      }
+      break;
+
+    case LL_RCC_SAI1_CLKSOURCE_PLL3P:
+#if defined(SAI3)
+    case LL_RCC_SAI23_CLKSOURCE_PLL3P:
+#endif /* SAI3 */
+#if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
+    case LL_RCC_SAI2A_CLKSOURCE_PLL3P:
+    case LL_RCC_SAI2B_CLKSOURCE_PLL3P:
+#endif /* (RCC_CDCCIP1R_SAI2ASEL) || (RCC_CDCCIP1R_SAI2BSEL) */
+#if defined(SAI4_Block_A) || defined(SAI4_Block_B)
+    case LL_RCC_SAI4A_CLKSOURCE_PLL3P:
+    case LL_RCC_SAI4B_CLKSOURCE_PLL3P:
+#endif /* (SAI2_Block_A_BASE) || (SAI2_Block_B_BASE) */
+      if (LL_RCC_PLL3_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
+        sai_frequency = PLL_Clocks.PLL_P_Frequency;
+      }
+      break;
+
+    case LL_RCC_SAI1_CLKSOURCE_I2S_CKIN:
+#if defined(SAI3)
+    case LL_RCC_SAI23_CLKSOURCE_I2S_CKIN:
+#endif /* SAI3 */
+#if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
+    case LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN:
+    case LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN:
+#endif /* (RCC_CDCCIP1R_SAI2ASEL) || (RCC_CDCCIP1R_SAI2BSEL) */
+#if defined(SAI4_Block_A) || defined(SAI4_Block_B)
+    case LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN:
+    case LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN:
+#endif /* (SAI2_Block_A_BASE) || (SAI2_Block_B_BASE) */
+      sai_frequency = EXTERNAL_CLOCK_VALUE;
+      break;
+
+    case LL_RCC_SAI1_CLKSOURCE_CLKP:
+#if defined(SAI3)
+    case LL_RCC_SAI23_CLKSOURCE_CLKP:
+#endif /* SAI3 */
+#if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
+    case LL_RCC_SAI2A_CLKSOURCE_CLKP:
+    case LL_RCC_SAI2B_CLKSOURCE_CLKP:
+#endif /* (RCC_CDCCIP1R_SAI2ASEL) || (RCC_CDCCIP1R_SAI2BSEL) */
+#if defined(SAI4_Block_A) || defined(SAI4_Block_B)
+    case LL_RCC_SAI4A_CLKSOURCE_CLKP:
+    case LL_RCC_SAI4B_CLKSOURCE_CLKP:
+#endif /* (SAI2_Block_A_BASE) || (SAI2_Block_B_BASE) */
+      sai_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    default:
+      /* Kernel clock disabled */
+      break;
+  }
+
+  return sai_frequency;
+}
+
+/**
+  * @brief  Return ADC clock frequency
+  * @param  ADCxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_ADC_CLKSOURCE
+  * @retval ADC clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
+{
+  uint32_t adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  LL_PLL_ClocksTypeDef PLL_Clocks;
+
+  switch (LL_RCC_GetADCClockSource(ADCxSource))
+  {
+    case LL_RCC_ADC_CLKSOURCE_PLL2P:
+      if (LL_RCC_PLL2_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
+        adc_frequency = PLL_Clocks.PLL_P_Frequency;
+      }
+      break;
+
+    case LL_RCC_ADC_CLKSOURCE_PLL3R:
+      if (LL_RCC_PLL3_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
+        adc_frequency = PLL_Clocks.PLL_R_Frequency;
+      }
+      break;
+
+    case LL_RCC_ADC_CLKSOURCE_CLKP:
+      adc_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    default:
+      /* Kernel clock disabled */
+      break;
+  }
+
+  return adc_frequency;
+}
+
+/**
+  * @brief  Return SDMMC clock frequency
+  * @param  SDMMCxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SDMMC_CLKSOURCE
+  * @retval SDMMC clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)
+{
+  uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  LL_PLL_ClocksTypeDef PLL_Clocks;
+
+  switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))
+  {
+    case LL_RCC_SDMMC_CLKSOURCE_PLL1Q:
+      if (LL_RCC_PLL1_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
+        sdmmc_frequency = PLL_Clocks.PLL_Q_Frequency;
+      }
+      break;
+
+    case LL_RCC_SDMMC_CLKSOURCE_PLL2R:
+      if (LL_RCC_PLL2_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
+        sdmmc_frequency = PLL_Clocks.PLL_R_Frequency;
+      }
+      break;
+
+    default:
+      /* Nothing to do */
+      break;
+  }
+
+  return sdmmc_frequency;
+}
+
+/**
+  * @brief  Return RNG clock frequency
+  * @param  RNGxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE
+  * @retval RNG clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
+{
+  uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  LL_PLL_ClocksTypeDef PLL_Clocks;
+
+  switch (LL_RCC_GetRNGClockSource(RNGxSource))
+  {
+    case LL_RCC_RNG_CLKSOURCE_PLL1Q:
+      if (LL_RCC_PLL1_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
+        rng_frequency = PLL_Clocks.PLL_Q_Frequency;
+      }
+      break;
+
+    case LL_RCC_RNG_CLKSOURCE_HSI48:
+      if (LL_RCC_HSI48_IsReady() != 0U)
+      {
+        rng_frequency = 48000000U;
+      }
+      break;
+
+    case LL_RCC_RNG_CLKSOURCE_LSE:
+      if (LL_RCC_LSE_IsReady() != 0U)
+      {
+        rng_frequency = LSE_VALUE;
+      }
+      break;
+
+    case LL_RCC_RNG_CLKSOURCE_LSI:
+      if (LL_RCC_LSI_IsReady() != 0U)
+      {
+        rng_frequency = LSI_VALUE;
+      }
+      break;
+
+    default:
+      /* Nothing to do */
+      break;
+  }
+
+  return rng_frequency;
+}
+
+/**
+  * @brief  Return CEC clock frequency
+  * @param  CECxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE
+  * @retval CEC clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource)
+{
+  uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  switch (LL_RCC_GetCECClockSource(CECxSource))
+  {
+    case LL_RCC_CEC_CLKSOURCE_LSE:
+      if (LL_RCC_LSE_IsReady() != 0U)
+      {
+        cec_frequency = LSE_VALUE;
+      }
+      break;
+
+    case LL_RCC_CEC_CLKSOURCE_LSI:
+      if (LL_RCC_LSI_IsReady() != 0U)
+      {
+        cec_frequency = LSI_VALUE;
+      }
+      break;
+
+    case LL_RCC_CEC_CLKSOURCE_CSI_DIV122:
+      if (LL_RCC_CSI_IsReady() != 0U)
+      {
+        cec_frequency = CSI_VALUE / 122U;
+      }
+      break;
+
+    default:
+      /* Kernel clock disabled */
+      break;
+  }
+
+  return cec_frequency;
+}
+
+/**
+  * @brief  Return USB clock frequency
+  * @param  USBxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USB_CLKSOURCE
+  * @retval USB clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready or Disabled
+  */
+uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
+{
+  uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  LL_PLL_ClocksTypeDef PLL_Clocks;
+
+  switch (LL_RCC_GetUSBClockSource(USBxSource))
+  {
+    case LL_RCC_USB_CLKSOURCE_PLL1Q:
+      if (LL_RCC_PLL1_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
+        usb_frequency = PLL_Clocks.PLL_Q_Frequency;
+      }
+      break;
+
+    case LL_RCC_USB_CLKSOURCE_PLL3Q:
+      if (LL_RCC_PLL3_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
+        usb_frequency = PLL_Clocks.PLL_Q_Frequency;
+      }
+      break;
+
+    case LL_RCC_USB_CLKSOURCE_HSI48:
+      if (LL_RCC_HSI48_IsReady() != 0U)
+      {
+        usb_frequency = HSI48_VALUE;
+      }
+      break;
+
+    case LL_RCC_USB_CLKSOURCE_DISABLE:
+    default:
+      /* Nothing to do */
+      break;
+  }
+
+  return usb_frequency;
+}
+
+/**
+  * @brief  Return DFSDM clock frequency
+  * @param  DFSDMxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE
+  * @retval DFSDM clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)
+{
+  uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource))
+  {
+    case LL_RCC_DFSDM1_CLKSOURCE_SYSCLK:
+      dfsdm_frequency = RCC_GetSystemClockFreq();
+      break;
+
+    case LL_RCC_DFSDM1_CLKSOURCE_PCLK2:
+      dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+      break;
+
+    default:
+      /* Nothing to do */
+      break;
+  }
+
+  return dfsdm_frequency;
+}
+
+#if defined(DFSDM2_BASE)
+/**
+  * @brief  Return DFSDM clock frequency
+  * @param  DFSDMxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE
+  * @retval DFSDM clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetDFSDM2ClockFreq(uint32_t DFSDMxSource)
+{
+  uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+
+  switch (LL_RCC_GetDFSDM2ClockSource(DFSDMxSource))
+  {
+
+    case LL_RCC_DFSDM2_CLKSOURCE_SYSCLK:
+      dfsdm_frequency = RCC_GetSystemClockFreq();
+      break;
+
+    case LL_RCC_DFSDM2_CLKSOURCE_PCLK4:
+      dfsdm_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+      break;
+
+    default:
+      /* Nothing to do */
+      break;
+  }
+
+  return dfsdm_frequency;
+}
+#endif /* DFSDM2_BASE */
+
+#if defined(DSI)
+/**
+  * @brief  Return DSI clock frequency
+  * @param  DSIxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DSI_CLKSOURCE
+  * @retval DSI clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used
+  */
+uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource)
+{
+  uint32_t dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  LL_PLL_ClocksTypeDef PLL_Clocks;
+
+  switch (LL_RCC_GetDSIClockSource(DSIxSource))
+  {
+    case LL_RCC_DSI_CLKSOURCE_PLL2Q:
+      if (LL_RCC_PLL2_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
+        dsi_frequency = PLL_Clocks.PLL_Q_Frequency;
+      }
+      break;
+
+    case LL_RCC_DSI_CLKSOURCE_PHY:
+      dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
+      break;
+
+    default:
+      /* Nothing to do */
+      break;
+  }
+
+  return dsi_frequency;
+}
+#endif /* DSI */
+
+/**
+  * @brief  Return SPDIF clock frequency
+  * @param  SPDIFxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE
+  * @retval SPDIF clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetSPDIFClockFreq(uint32_t SPDIFxSource)
+{
+  uint32_t spdif_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  LL_PLL_ClocksTypeDef PLL_Clocks;
+
+  switch (LL_RCC_GetSPDIFClockSource(SPDIFxSource))
+  {
+    case LL_RCC_SPDIF_CLKSOURCE_PLL1Q:
+      if (LL_RCC_PLL1_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
+        spdif_frequency = PLL_Clocks.PLL_Q_Frequency;
+      }
+      break;
+
+    case LL_RCC_SPDIF_CLKSOURCE_PLL2R:
+      if (LL_RCC_PLL2_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
+        spdif_frequency = PLL_Clocks.PLL_R_Frequency;
+      }
+      break;
+
+    case LL_RCC_SPDIF_CLKSOURCE_PLL3R:
+      if (LL_RCC_PLL3_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
+        spdif_frequency = PLL_Clocks.PLL_R_Frequency;
+      }
+      break;
+
+    case LL_RCC_SPDIF_CLKSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        spdif_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
+      }
+      break;
+
+    default:
+      /* Nothing to do */
+      break;
+  }
+
+  return spdif_frequency;
+}
+
+/**
+  * @brief  Return SPIx clock frequency
+  * @param  SPIxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE
+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE
+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE
+  * @retval SPI clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource)
+{
+  uint32_t spi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  LL_PLL_ClocksTypeDef PLL_Clocks;
+
+  /* Check parameter */
+  assert_param(IS_LL_RCC_SPI_CLKSOURCE(SPIxSource));
+
+  switch (LL_RCC_GetSPIClockSource(SPIxSource))
+  {
+    case LL_RCC_SPI123_CLKSOURCE_PLL1Q:
+      if (LL_RCC_PLL1_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
+        spi_frequency = PLL_Clocks.PLL_Q_Frequency;
+      }
+      break;
+
+    case LL_RCC_SPI123_CLKSOURCE_PLL2P:
+      if (LL_RCC_PLL2_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
+        spi_frequency = PLL_Clocks.PLL_P_Frequency;
+      }
+      break;
+
+    case LL_RCC_SPI123_CLKSOURCE_PLL3P:
+      if (LL_RCC_PLL3_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
+        spi_frequency = PLL_Clocks.PLL_P_Frequency;
+      }
+      break;
+
+    case LL_RCC_SPI123_CLKSOURCE_I2S_CKIN:
+#if defined(LL_RCC_SPI6_CLKSOURCE_I2S_CKIN)
+    case LL_RCC_SPI6_CLKSOURCE_I2S_CKIN:
+#endif /* LL_RCC_SPI6_CLKSOURCE_I2S_CKIN */
+      spi_frequency = EXTERNAL_CLOCK_VALUE;
+      break;
+
+    case LL_RCC_SPI123_CLKSOURCE_CLKP:
+      spi_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    case LL_RCC_SPI45_CLKSOURCE_PCLK2:
+      spi_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+      break;
+
+    case LL_RCC_SPI6_CLKSOURCE_PCLK4:
+      spi_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+      break;
+
+    case LL_RCC_SPI45_CLKSOURCE_PLL2Q:
+    case LL_RCC_SPI6_CLKSOURCE_PLL2Q:
+      if (LL_RCC_PLL2_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
+        spi_frequency = PLL_Clocks.PLL_Q_Frequency;
+      }
+      break;
+
+    case LL_RCC_SPI45_CLKSOURCE_PLL3Q:
+    case LL_RCC_SPI6_CLKSOURCE_PLL3Q:
+      if (LL_RCC_PLL3_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
+        spi_frequency = PLL_Clocks.PLL_Q_Frequency;
+      }
+      break;
+
+    case LL_RCC_SPI45_CLKSOURCE_HSI:
+    case LL_RCC_SPI6_CLKSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        spi_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
+      }
+      break;
+
+    case LL_RCC_SPI45_CLKSOURCE_CSI:
+    case LL_RCC_SPI6_CLKSOURCE_CSI:
+      if (LL_RCC_CSI_IsReady() != 0U)
+      {
+        spi_frequency = CSI_VALUE;
+      }
+      break;
+
+    case LL_RCC_SPI45_CLKSOURCE_HSE:
+    case LL_RCC_SPI6_CLKSOURCE_HSE:
+      if (LL_RCC_HSE_IsReady() != 0U)
+      {
+        spi_frequency = HSE_VALUE;
+      }
+      break;
+
+    default:
+      /* Kernel clock disabled */
+      break;
+  }
+
+  return spi_frequency;
+}
+
+/**
+  * @brief  Return SWP clock frequency
+  * @param  SWPxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SWP_CLKSOURCE
+  * @retval SWP clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetSWPClockFreq(uint32_t SWPxSource)
+{
+  uint32_t swp_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  switch (LL_RCC_GetSWPClockSource(SWPxSource))
+  {
+    case LL_RCC_SWP_CLKSOURCE_PCLK1:
+      swp_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+      break;
+
+    case LL_RCC_SWP_CLKSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        swp_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
+      }
+      break;
+
+    default:
+      /* Nothing to do */
+      break;
+  }
+
+  return swp_frequency;
+}
+
+/**
+  * @brief  Return FDCAN clock frequency
+  * @param  FDCANxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE
+  * @retval FDCAN clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource)
+{
+  uint32_t fdcan_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  LL_PLL_ClocksTypeDef PLL_Clocks;
+
+  switch (LL_RCC_GetFDCANClockSource(FDCANxSource))
+  {
+    case LL_RCC_FDCAN_CLKSOURCE_HSE:
+      if (LL_RCC_HSE_IsReady() != 0U)
+      {
+        fdcan_frequency = HSE_VALUE;
+      }
+      break;
+
+    case LL_RCC_FDCAN_CLKSOURCE_PLL1Q:
+      if (LL_RCC_PLL1_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
+        fdcan_frequency = PLL_Clocks.PLL_Q_Frequency;
+      }
+      break;
+
+    case LL_RCC_FDCAN_CLKSOURCE_PLL2Q:
+      if (LL_RCC_PLL2_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
+        fdcan_frequency = PLL_Clocks.PLL_Q_Frequency;
+      }
+      break;
+
+    default:
+      /* Kernel clock disabled */
+      break;
+  }
+
+  return fdcan_frequency;
+}
+
+/**
+  * @brief  Return FMC clock frequency
+  * @param  FMCxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_FMC_CLKSOURCE
+  * @retval FMC clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetFMCClockFreq(uint32_t FMCxSource)
+{
+  uint32_t fmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  LL_PLL_ClocksTypeDef PLL_Clocks;
+
+  switch (LL_RCC_GetFMCClockSource(FMCxSource))
+  {
+    case LL_RCC_FMC_CLKSOURCE_HCLK:
+      fmc_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler()));
+      break;
+
+    case LL_RCC_FMC_CLKSOURCE_PLL1Q:
+      if (LL_RCC_PLL1_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
+        fmc_frequency = PLL_Clocks.PLL_Q_Frequency;
+      }
+      break;
+
+    case LL_RCC_FMC_CLKSOURCE_PLL2R:
+      if (LL_RCC_PLL2_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
+        fmc_frequency = PLL_Clocks.PLL_R_Frequency;
+      }
+      break;
+
+    case LL_RCC_FMC_CLKSOURCE_CLKP:
+      fmc_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    default:
+      /* Nothing to do */
+      break;
+  }
+
+  return fmc_frequency;
+}
+
+#if defined(QUADSPI)
+/**
+  * @brief  Return QSPI clock frequency
+  * @param  QSPIxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_QSPI_CLKSOURCE
+  * @retval QSPI clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetQSPIClockFreq(uint32_t QSPIxSource)
+{
+  uint32_t qspi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  LL_PLL_ClocksTypeDef PLL_Clocks;
+
+  switch (LL_RCC_GetQSPIClockSource(QSPIxSource))
+  {
+    case LL_RCC_QSPI_CLKSOURCE_HCLK:
+      qspi_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler()));
+      break;
+
+    case LL_RCC_QSPI_CLKSOURCE_PLL1Q:
+      if (LL_RCC_PLL1_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
+        qspi_frequency = PLL_Clocks.PLL_Q_Frequency;
+      }
+      break;
+
+    case LL_RCC_QSPI_CLKSOURCE_PLL2R:
+      if (LL_RCC_PLL2_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
+        qspi_frequency = PLL_Clocks.PLL_R_Frequency;
+      }
+      break;
+
+    case LL_RCC_QSPI_CLKSOURCE_CLKP:
+      qspi_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    default:
+      /* Nothing to do */
+      break;
+  }
+
+  return qspi_frequency;
+}
+#endif /* QUADSPI */
+
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+/**
+  * @brief  Return OSPI clock frequency
+  * @param  QSPIxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_OSPI_CLKSOURCE
+  * @retval OSPI clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+
+uint32_t LL_RCC_GetOSPIClockFreq(uint32_t OSPIxSource)
+{
+  uint32_t ospi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+  LL_PLL_ClocksTypeDef PLL_Clocks;
+
+  switch (LL_RCC_GetOSPIClockSource(OSPIxSource))
+  {
+    case LL_RCC_OSPI_CLKSOURCE_HCLK:
+      ospi_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler()));
+      break;
+
+    case LL_RCC_OSPI_CLKSOURCE_PLL1Q:
+      if (LL_RCC_PLL1_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
+        ospi_frequency = PLL_Clocks.PLL_Q_Frequency;
+      }
+      break;
+
+    case LL_RCC_OSPI_CLKSOURCE_PLL2R:
+      if (LL_RCC_PLL2_IsReady() != 0U)
+      {
+        LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
+        ospi_frequency = PLL_Clocks.PLL_R_Frequency;
+      }
+      break;
+
+    case LL_RCC_OSPI_CLKSOURCE_CLKP:
+      ospi_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
+      break;
+
+    default:
+      /* Nothing to do */
+      break;
+  }
+
+  return ospi_frequency;
+}
+#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
+
+/**
+  * @brief  Return CLKP clock frequency
+  * @param  CLKPxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE
+  * @retval CLKP clock frequency (in Hz)
+  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
+  */
+uint32_t LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource)
+{
+  uint32_t clkp_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  switch (LL_RCC_GetCLKPClockSource(CLKPxSource))
+  {
+    case LL_RCC_CLKP_CLKSOURCE_HSI:
+      if (LL_RCC_HSI_IsReady() != 0U)
+      {
+        clkp_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
+      }
+      break;
+
+    case LL_RCC_CLKP_CLKSOURCE_CSI:
+      if (LL_RCC_CSI_IsReady() != 0U)
+      {
+        clkp_frequency = CSI_VALUE;
+      }
+      break;
+
+    case LL_RCC_CLKP_CLKSOURCE_HSE:
+      if (LL_RCC_HSE_IsReady() != 0U)
+      {
+        clkp_frequency = HSE_VALUE;
+      }
+      break;
+
+    default:
+      /* CLKP clock disabled */
+      break;
+  }
+
+  return clkp_frequency;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup RCC_LL_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Return SYSTEM clock frequency
+  * @retval SYSTEM clock frequency (in Hz)
+  */
+uint32_t RCC_GetSystemClockFreq(void)
+{
+  uint32_t frequency = 0U;
+  LL_PLL_ClocksTypeDef PLL_Clocks;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (LL_RCC_GetSysClkSource())
+  {
+    /* No check on Ready: Won't be selected by hardware if not */
+    case LL_RCC_SYS_CLKSOURCE_STATUS_HSI:
+      frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
+      break;
+
+    case LL_RCC_SYS_CLKSOURCE_STATUS_CSI:
+      frequency = CSI_VALUE;
+      break;
+
+    case LL_RCC_SYS_CLKSOURCE_STATUS_HSE:
+      frequency = HSE_VALUE;
+      break;
+
+    case LL_RCC_SYS_CLKSOURCE_STATUS_PLL1:
+      LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
+      frequency = PLL_Clocks.PLL_P_Frequency;
+      break;
+
+    default:
+      /* Nothing to do */
+      break;
+  }
+
+  return frequency;
+}
+
+/**
+  * @brief  Return HCLK clock frequency
+  * @param  SYSCLK_Frequency SYSCLK clock frequency
+  * @retval HCLK clock frequency (in Hz)
+  */
+uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
+{
+  /* HCLK clock frequency */
+  return LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
+}
+
+/**
+  * @brief  Return PCLK1 clock frequency
+  * @param  HCLK_Frequency HCLK clock frequency
+  * @retval PCLK1 clock frequency (in Hz)
+  */
+uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
+{
+  /* PCLK1 clock frequency */
+  return LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
+}
+
+/**
+  * @brief  Return PCLK2 clock frequency
+  * @param  HCLK_Frequency HCLK clock frequency
+  * @retval PCLK2 clock frequency (in Hz)
+  */
+uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
+{
+  /* PCLK2 clock frequency */
+  return LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
+}
+
+/**
+  * @brief  Return PCLK3 clock frequency
+  * @param  HCLK_Frequency HCLK clock frequency
+  * @retval PCLK3 clock frequency (in Hz)
+  */
+uint32_t RCC_GetPCLK3ClockFreq(uint32_t HCLK_Frequency)
+{
+  /* PCLK3 clock frequency */
+  return LL_RCC_CALC_PCLK3_FREQ(HCLK_Frequency, LL_RCC_GetAPB3Prescaler());
+}
+
+/**
+  * @brief  Return PCLK4 clock frequency
+  * @param  HCLK_Frequency HCLK clock frequency
+  * @retval PCLK4 clock frequency (in Hz)
+  */
+uint32_t RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency)
+{
+  /* PCLK4 clock frequency */
+  return LL_RCC_CALC_PCLK4_FREQ(HCLK_Frequency, LL_RCC_GetAPB4Prescaler());
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(RCC) */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usart.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usart.c
new file mode 100644
index 00000000..9419620a
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usart.c
@@ -0,0 +1,496 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_usart.c
+  * @author  MCD Application Team
+  * @brief   USART LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_ll_usart.h"
+#include "stm32h7xx_ll_rcc.h"
+#include "stm32h7xx_ll_bus.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+#if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5) || defined (UART7) || defined (UART8) || defined (UART9) || defined (USART10)
+
+/** @addtogroup USART_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup USART_LL_Private_Macros
+  * @{
+  */
+
+#define IS_LL_USART_PRESCALER(__VALUE__)  (((__VALUE__) == LL_USART_PRESCALER_DIV1) \
+                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV2) \
+                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV4) \
+                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV6) \
+                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV8) \
+                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV10) \
+                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV12) \
+                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV16) \
+                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV32) \
+                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV64) \
+                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV128) \
+                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV256))
+
+/* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
+ *              divided by the smallest oversampling used on the USART (i.e. 8)    */
+#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 12500000U)
+
+/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
+#define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
+
+/* __VALUE__ BRR content must be lower than or equal to 0xFFFF. */
+#define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
+
+#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
+                                          || ((__VALUE__) == LL_USART_DIRECTION_RX) \
+                                          || ((__VALUE__) == LL_USART_DIRECTION_TX) \
+                                          || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
+
+#define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
+                                       || ((__VALUE__) == LL_USART_PARITY_EVEN) \
+                                       || ((__VALUE__) == LL_USART_PARITY_ODD))
+
+#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \
+                                          || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
+                                          || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
+
+#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
+                                             || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
+
+#define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
+                                                 || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
+
+#define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
+                                           || ((__VALUE__) == LL_USART_PHASE_2EDGE))
+
+#define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
+                                              || ((__VALUE__) == LL_USART_POLARITY_HIGH))
+
+#define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
+                                            || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
+
+#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
+                                         || ((__VALUE__) == LL_USART_STOPBITS_1) \
+                                         || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
+                                         || ((__VALUE__) == LL_USART_STOPBITS_2))
+
+#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
+                                          || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
+                                          || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
+                                          || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
+
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup USART_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup USART_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize USART registers (Registers restored to their default values).
+  * @param  USARTx USART Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: USART registers are de-initialized
+  *          - ERROR: USART registers are not de-initialized
+  */
+ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_UART_INSTANCE(USARTx));
+
+  if (USARTx == USART1)
+  {
+    /* Force reset of USART clock */
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
+
+    /* Release reset of USART clock */
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
+  }
+  else if (USARTx == USART2)
+  {
+    /* Force reset of USART clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
+
+    /* Release reset of USART clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
+  }
+  else if (USARTx == USART3)
+  {
+    /* Force reset of USART clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);
+
+    /* Release reset of USART clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
+  }
+  else if (USARTx == UART4)
+  {
+    /* Force reset of UART clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4);
+
+    /* Release reset of UART clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4);
+  }
+  else if (USARTx == UART5)
+  {
+    /* Force reset of UART clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5);
+
+    /* Release reset of UART clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5);
+  }
+  else if (USARTx == USART6)
+  {
+    /* Force reset of USART clock */
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART6);
+
+    /* Release reset of USART clock */
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART6);
+  }
+  else if (USARTx == UART7)
+  {
+    /* Force reset of UART clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART7);
+
+    /* Release reset of UART clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART7);
+  }
+  else if (USARTx == UART8)
+  {
+    /* Force reset of UART clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART8);
+
+    /* Release reset of UART clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART8);
+  }
+#if defined(UART9)
+  else if (USARTx == UART9)
+  {
+    /* Force reset of UART clock */
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_UART9);
+
+    /* Release reset of UART clock */
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_UART9);
+  }
+#endif /* UART9 */
+#if defined(USART10)
+  else if (USARTx == USART10)
+  {
+    /* Force reset of USART clock */
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART10);
+
+    /* Release reset of USART clock */
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART10);
+  }
+#endif /* USART10 */
+  else
+  {
+    status = ERROR;
+  }
+
+  return (status);
+}
+
+/**
+  * @brief  Initialize USART registers according to the specified
+  *         parameters in USART_InitStruct.
+  * @note   As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
+  *         USART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+  * @note   Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
+  * @param  USARTx USART Instance
+  * @param  USART_InitStruct pointer to a LL_USART_InitTypeDef structure
+  *         that contains the configuration information for the specified USART peripheral.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: USART registers are initialized according to USART_InitStruct content
+  *          - ERROR: Problem occurred during USART Registers initialization
+  */
+ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
+{
+  ErrorStatus status = ERROR;
+  uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
+
+  /* Check the parameters */
+  assert_param(IS_UART_INSTANCE(USARTx));
+  assert_param(IS_LL_USART_PRESCALER(USART_InitStruct->PrescalerValue));
+  assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
+  assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
+  assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
+  assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
+  assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
+  assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
+  assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
+
+  /* USART needs to be in disabled state, in order to be able to configure some bits in
+     CRx registers */
+  if (LL_USART_IsEnabled(USARTx) == 0U)
+  {
+    /*---------------------------- USART CR1 Configuration ---------------------
+     * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
+     * - DataWidth:          USART_CR1_M bits according to USART_InitStruct->DataWidth value
+     * - Parity:             USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
+     * - TransferDirection:  USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
+     * - Oversampling:       USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
+     */
+    MODIFY_REG(USARTx->CR1,
+               (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
+                USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
+               (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
+                USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
+
+    /*---------------------------- USART CR2 Configuration ---------------------
+     * Configure USARTx CR2 (Stop bits) with parameters:
+     * - Stop Bits:          USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
+     * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
+     */
+    LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
+
+    /*---------------------------- USART CR3 Configuration ---------------------
+     * Configure USARTx CR3 (Hardware Flow Control) with parameters:
+     * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value.
+     */
+    LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
+
+    /*---------------------------- USART BRR Configuration ---------------------
+     * Retrieve Clock frequency used for USART Peripheral
+     */
+    if (USARTx == USART1)
+    {
+      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART16_CLKSOURCE);
+    }
+    else if (USARTx == USART2)
+    {
+      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART234578_CLKSOURCE);
+    }
+    else if (USARTx == USART3)
+    {
+      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART234578_CLKSOURCE);
+    }
+    else if (USARTx == UART4)
+    {
+      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART234578_CLKSOURCE);
+    }
+    else if (USARTx == UART5)
+    {
+      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART234578_CLKSOURCE);
+    }
+    else if (USARTx == USART6)
+    {
+      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART16_CLKSOURCE);
+    }
+    else if (USARTx == UART7)
+    {
+      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART234578_CLKSOURCE);
+    }
+    else if (USARTx == UART8)
+    {
+      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART234578_CLKSOURCE);
+    }
+#if defined(UART9)
+    else if (USARTx == UART9)
+    {
+      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART16_CLKSOURCE);
+    }
+#endif /* UART9 */
+#if defined(USART10)
+    else if (USARTx == USART10)
+    {
+      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART16_CLKSOURCE);
+    }
+#endif /* USART10 */
+    else
+    {
+      /* Nothing to do, as error code is already assigned to ERROR value */
+    }
+
+    /* Configure the USART Baud Rate :
+       - prescaler value is required
+       - valid baud rate value (different from 0) is required
+       - Peripheral clock as returned by RCC service, should be valid (different from 0).
+    */
+    if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
+        && (USART_InitStruct->BaudRate != 0U))
+    {
+      status = SUCCESS;
+      LL_USART_SetBaudRate(USARTx,
+                           periphclk,
+                           USART_InitStruct->PrescalerValue,
+                           USART_InitStruct->OverSampling,
+                           USART_InitStruct->BaudRate);
+
+      /* Check BRR is greater than or equal to 16d */
+      assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
+
+      /* Check BRR is lower than or equal to 0xFFFF */
+      assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR));
+    }
+
+    /*---------------------------- USART PRESC Configuration -----------------------
+     * Configure USARTx PRESC (Prescaler) with parameters:
+     * - PrescalerValue: USART_PRESC_PRESCALER bits according to USART_InitStruct->PrescalerValue value.
+     */
+    LL_USART_SetPrescaler(USARTx, USART_InitStruct->PrescalerValue);
+  }
+  /* Endif (=> USART not in Disabled state => return ERROR) */
+
+  return (status);
+}
+
+/**
+  * @brief Set each @ref LL_USART_InitTypeDef field to default value.
+  * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure
+  *                         whose fields will be set to default values.
+  * @retval None
+  */
+
+void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
+{
+  /* Set USART_InitStruct fields to default values */
+  USART_InitStruct->PrescalerValue      = LL_USART_PRESCALER_DIV1;
+  USART_InitStruct->BaudRate            = 9600U;
+  USART_InitStruct->DataWidth           = LL_USART_DATAWIDTH_8B;
+  USART_InitStruct->StopBits            = LL_USART_STOPBITS_1;
+  USART_InitStruct->Parity              = LL_USART_PARITY_NONE ;
+  USART_InitStruct->TransferDirection   = LL_USART_DIRECTION_TX_RX;
+  USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
+  USART_InitStruct->OverSampling        = LL_USART_OVERSAMPLING_16;
+}
+
+/**
+  * @brief  Initialize USART Clock related settings according to the
+  *         specified parameters in the USART_ClockInitStruct.
+  * @note   As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
+  *         USART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+  * @param  USARTx USART Instance
+  * @param  USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
+  *         that contains the Clock configuration information for the specified USART peripheral.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
+  *          - ERROR: Problem occurred during USART Registers initialization
+  */
+ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check USART Instance and Clock signal output parameters */
+  assert_param(IS_UART_INSTANCE(USARTx));
+  assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
+
+  /* USART needs to be in disabled state, in order to be able to configure some bits in
+     CRx registers */
+  if (LL_USART_IsEnabled(USARTx) == 0U)
+  {
+    /*---------------------------- USART CR2 Configuration -----------------------*/
+    /* If Clock signal has to be output */
+    if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
+    {
+      /* Deactivate Clock signal delivery :
+       * - Disable Clock Output:        USART_CR2_CLKEN cleared
+       */
+      LL_USART_DisableSCLKOutput(USARTx);
+    }
+    else
+    {
+      /* Ensure USART instance is USART capable */
+      assert_param(IS_USART_INSTANCE(USARTx));
+
+      /* Check clock related parameters */
+      assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
+      assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
+      assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
+
+      /*---------------------------- USART CR2 Configuration -----------------------
+       * Configure USARTx CR2 (Clock signal related bits) with parameters:
+       * - Enable Clock Output:         USART_CR2_CLKEN set
+       * - Clock Polarity:              USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
+       * - Clock Phase:                 USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
+       * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
+       */
+      MODIFY_REG(USARTx->CR2,
+                 USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
+                 USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
+                 USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
+    }
+  }
+  /* Else (USART not in Disabled state => return ERROR */
+  else
+  {
+    status = ERROR;
+  }
+
+  return (status);
+}
+
+/**
+  * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
+  * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
+  *                              whose fields will be set to default values.
+  * @retval None
+  */
+void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
+{
+  /* Set LL_USART_ClockInitStruct fields with default values */
+  USART_ClockInitStruct->ClockOutput       = LL_USART_CLOCK_DISABLE;
+  USART_ClockInitStruct->ClockPolarity     = LL_USART_POLARITY_LOW;            /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
+  USART_ClockInitStruct->ClockPhase        = LL_USART_PHASE_1EDGE;             /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
+  USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT;  /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 || UART9 || USART10 */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c
new file mode 100644
index 00000000..1e4ae32f
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c
@@ -0,0 +1,1989 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_usb.c
+  * @author  MCD Application Team
+  * @brief   USB Low Layer HAL module driver.
+  *
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the USB Peripheral Controller:
+  *           + Initialization/de-initialization functions
+  *           + I/O operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State functions
+  *
+  @verbatim
+  ==============================================================================
+                    ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure.
+
+      (#) Call USB_CoreInit() API to initialize the USB Core peripheral.
+
+      (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_LL_USB_DRIVER
+  * @{
+  */
+
+#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED)
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx);
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup USB_LL_Exported_Functions USB Low Layer Exported Functions
+  * @{
+  */
+
+/** @defgroup USB_LL_Exported_Functions_Group1 Initialization/de-initialization functions
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### Initialization/de-initialization functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the USB Core
+  * @param  USBx USB Instance
+  * @param  cfg pointer to a USB_OTG_CfgTypeDef structure that contains
+  *         the configuration information for the specified USBx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
+{
+  HAL_StatusTypeDef ret;
+
+  if (cfg.phy_itface == USB_OTG_ULPI_PHY)
+  {
+    USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
+
+    /* Init The ULPI Interface */
+    USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
+
+    /* Select vbus source */
+    USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
+    if (cfg.use_external_vbus == 1U)
+    {
+      USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;
+    }
+    /* Reset after a PHY select  */
+    ret = USB_CoreReset(USBx);
+  }
+  else /* FS interface (embedded Phy) */
+  {
+    /* Select FS Embedded PHY */
+    USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
+
+    /* Reset after a PHY select and set Host mode */
+    ret = USB_CoreReset(USBx);
+
+    if (cfg.battery_charging_enable == 0U)
+    {
+      /* Activate the USB Transceiver */
+      USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
+    }
+    else
+    {
+      /* Deactivate the USB Transceiver */
+      USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
+    }
+  }
+
+  if (cfg.dma_enable == 1U)
+  {
+    USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2;
+    USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;
+  }
+
+  return ret;
+}
+
+
+/**
+  * @brief  Set the USB turnaround time
+  * @param  USBx USB Instance
+  * @param  hclk: AHB clock frequency
+  * @retval USB turnaround time In PHY Clocks number
+  */
+HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx,
+                                        uint32_t hclk, uint8_t speed)
+{
+  uint32_t UsbTrd;
+
+  /* The USBTRD is configured according to the tables below, depending on AHB frequency
+  used by application. In the low AHB frequency range it is used to stretch enough the USB response
+  time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access
+  latency to the Data FIFO */
+  if (speed == USBD_FS_SPEED)
+  {
+    if ((hclk >= 14200000U) && (hclk < 15000000U))
+    {
+      /* hclk Clock Range between 14.2-15 MHz */
+      UsbTrd = 0xFU;
+    }
+    else if ((hclk >= 15000000U) && (hclk < 16000000U))
+    {
+      /* hclk Clock Range between 15-16 MHz */
+      UsbTrd = 0xEU;
+    }
+    else if ((hclk >= 16000000U) && (hclk < 17200000U))
+    {
+      /* hclk Clock Range between 16-17.2 MHz */
+      UsbTrd = 0xDU;
+    }
+    else if ((hclk >= 17200000U) && (hclk < 18500000U))
+    {
+      /* hclk Clock Range between 17.2-18.5 MHz */
+      UsbTrd = 0xCU;
+    }
+    else if ((hclk >= 18500000U) && (hclk < 20000000U))
+    {
+      /* hclk Clock Range between 18.5-20 MHz */
+      UsbTrd = 0xBU;
+    }
+    else if ((hclk >= 20000000U) && (hclk < 21800000U))
+    {
+      /* hclk Clock Range between 20-21.8 MHz */
+      UsbTrd = 0xAU;
+    }
+    else if ((hclk >= 21800000U) && (hclk < 24000000U))
+    {
+      /* hclk Clock Range between 21.8-24 MHz */
+      UsbTrd = 0x9U;
+    }
+    else if ((hclk >= 24000000U) && (hclk < 27700000U))
+    {
+      /* hclk Clock Range between 24-27.7 MHz */
+      UsbTrd = 0x8U;
+    }
+    else if ((hclk >= 27700000U) && (hclk < 32000000U))
+    {
+      /* hclk Clock Range between 27.7-32 MHz */
+      UsbTrd = 0x7U;
+    }
+    else /* if(hclk >= 32000000) */
+    {
+      /* hclk Clock Range between 32-200 MHz */
+      UsbTrd = 0x6U;
+    }
+  }
+  else if (speed == USBD_HS_SPEED)
+  {
+    UsbTrd = USBD_HS_TRDT_VALUE;
+  }
+  else
+  {
+    UsbTrd = USBD_DEFAULT_TRDT_VALUE;
+  }
+
+  USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
+  USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_EnableGlobalInt
+  *         Enables the controller's Global Int in the AHB Config reg
+  * @param  USBx  Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
+{
+  USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_DisableGlobalInt
+  *         Disable the controller's Global Int in the AHB Config reg
+  * @param  USBx  Selected device
+  * @retval HAL status
+*/
+HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
+{
+  USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_SetCurrentMode : Set functional mode
+  * @param  USBx  Selected device
+  * @param  mode   current core mode
+  *          This parameter can be one of these values:
+  *            @arg USB_DEVICE_MODE: Peripheral mode
+  *            @arg USB_HOST_MODE: Host mode
+  *            @arg USB_DRD_MODE: Dual Role Device mode
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode)
+{
+  USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
+
+  if (mode == USB_HOST_MODE)
+  {
+    USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;
+  }
+  else if (mode == USB_DEVICE_MODE)
+  {
+    USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+  HAL_Delay(50U);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_DevInit : Initializes the USB_OTG controller registers
+  *         for device mode
+  * @param  USBx  Selected device
+  * @param  cfg   pointer to a USB_OTG_CfgTypeDef structure that contains
+  *         the configuration information for the specified USBx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
+{
+  HAL_StatusTypeDef ret = HAL_OK;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t i;
+
+  for (i = 0U; i < 15U; i++)
+  {
+    USBx->DIEPTXF[i] = 0U;
+  }
+
+  /* VBUS Sensing setup */
+  if (cfg.vbus_sensing_enable == 0U)
+  {
+    USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
+
+    /* Deactivate VBUS Sensing B */
+    USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
+
+    /* B-peripheral session valid override enable */
+    USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
+    USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
+  }
+  else
+  {
+    /* Enable HW VBUS sensing */
+    USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
+  }
+
+  /* Restart the Phy Clock */
+  USBx_PCGCCTL = 0U;
+
+  /* Device mode configuration */
+  USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80;
+
+  if (cfg.phy_itface == USB_OTG_ULPI_PHY)
+  {
+    if (cfg.speed == USBD_HS_SPEED)
+    {
+      /* Set Core speed to High speed mode */
+      (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH);
+    }
+    else
+    {
+      /* Set Core speed to Full speed mode */
+      (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL);
+    }
+  }
+  else
+  {
+    /* Set Core speed to Full speed mode */
+    (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL);
+  }
+
+  /* Flush the FIFOs */
+  if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */
+  {
+    ret = HAL_ERROR;
+  }
+
+  if (USB_FlushRxFifo(USBx) != HAL_OK)
+  {
+    ret = HAL_ERROR;
+  }
+
+  /* Clear all pending Device Interrupts */
+  USBx_DEVICE->DIEPMSK = 0U;
+  USBx_DEVICE->DOEPMSK = 0U;
+  USBx_DEVICE->DAINTMSK = 0U;
+
+  for (i = 0U; i < cfg.dev_endpoints; i++)
+  {
+    if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
+    {
+      if (i == 0U)
+      {
+        USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK;
+      }
+      else
+      {
+        USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK;
+      }
+    }
+    else
+    {
+      USBx_INEP(i)->DIEPCTL = 0U;
+    }
+
+    USBx_INEP(i)->DIEPTSIZ = 0U;
+    USBx_INEP(i)->DIEPINT  = 0xFB7FU;
+  }
+
+  for (i = 0U; i < cfg.dev_endpoints; i++)
+  {
+    if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
+    {
+      if (i == 0U)
+      {
+        USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK;
+      }
+      else
+      {
+        USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK;
+      }
+    }
+    else
+    {
+      USBx_OUTEP(i)->DOEPCTL = 0U;
+    }
+
+    USBx_OUTEP(i)->DOEPTSIZ = 0U;
+    USBx_OUTEP(i)->DOEPINT  = 0xFB7FU;
+  }
+
+  USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
+
+  /* Disable all interrupts. */
+  USBx->GINTMSK = 0U;
+
+  /* Clear any pending interrupts */
+  USBx->GINTSTS = 0xBFFFFFFFU;
+
+  /* Enable the common interrupts */
+  if (cfg.dma_enable == 0U)
+  {
+    USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
+  }
+
+  /* Enable interrupts matching to the Device mode ONLY */
+  USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |
+                   USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |
+                   USB_OTG_GINTMSK_OEPINT   | USB_OTG_GINTMSK_IISOIXFRM |
+                   USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM;
+
+  if (cfg.Sof_enable != 0U)
+  {
+    USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;
+  }
+
+  if (cfg.vbus_sensing_enable == 1U)
+  {
+    USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT);
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  USB_OTG_FlushTxFifo : Flush a Tx FIFO
+  * @param  USBx  Selected device
+  * @param  num  FIFO number
+  *         This parameter can be a value from 1 to 15
+            15 means Flush all Tx FIFOs
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
+{
+  uint32_t count = 0U;
+
+  USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6));
+
+  do
+  {
+    if (++count > 200000U)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_FlushRxFifo : Flush Rx FIFO
+  * @param  USBx  Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t count = 0;
+
+  USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
+
+  do
+  {
+    if (++count > 200000U)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_SetDevSpeed  Initializes the DevSpd field of DCFG register
+  *         depending the PHY type and the enumeration speed of the device.
+  * @param  USBx  Selected device
+  * @param  speed  device speed
+  *          This parameter can be one of these values:
+  *            @arg USB_OTG_SPEED_HIGH: High speed mode
+  *            @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode
+  *            @arg USB_OTG_SPEED_FULL: Full speed mode
+  * @retval  Hal status
+  */
+HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  USBx_DEVICE->DCFG |= speed;
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_GetDevSpeed  Return the Dev Speed
+  * @param  USBx  Selected device
+  * @retval speed  device speed
+  *          This parameter can be one of these values:
+  *            @arg PCD_SPEED_HIGH: High speed mode
+  *            @arg PCD_SPEED_FULL: Full speed mode
+  */
+uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint8_t speed;
+  uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD;
+
+  if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ)
+  {
+    speed = USBD_HS_SPEED;
+  }
+  else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) ||
+           (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ))
+  {
+    speed = USBD_FS_SPEED;
+  }
+  else
+  {
+    speed = 0xFU;
+  }
+
+  return speed;
+}
+
+/**
+  * @brief  Activate and configure an endpoint
+  * @param  USBx  Selected device
+  * @param  ep pointer to endpoint structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t epnum = (uint32_t)ep->num;
+
+  if (ep->is_in == 1U)
+  {
+    USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK));
+
+    if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U)
+    {
+      USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
+                                   ((uint32_t)ep->type << 18) | (epnum << 22) |
+                                   USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
+                                   USB_OTG_DIEPCTL_USBAEP;
+    }
+  }
+  else
+  {
+    USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16);
+
+    if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)
+    {
+      USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |
+                                    ((uint32_t)ep->type << 18) |
+                                    USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
+                                    USB_OTG_DOEPCTL_USBAEP;
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Activate and configure a dedicated endpoint
+  * @param  USBx  Selected device
+  * @param  ep pointer to endpoint structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t epnum = (uint32_t)ep->num;
+
+  /* Read DEPCTLn register */
+  if (ep->is_in == 1U)
+  {
+    if (((USBx_INEP(epnum)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U)
+    {
+      USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
+                                   ((uint32_t)ep->type << 18) | (epnum << 22) |
+                                   USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
+                                   USB_OTG_DIEPCTL_USBAEP;
+    }
+
+    USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK));
+  }
+  else
+  {
+    if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)
+    {
+      USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |
+                                    ((uint32_t)ep->type << 18) | (epnum << 22) |
+                                    USB_OTG_DOEPCTL_USBAEP;
+    }
+
+    USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  De-activate and de-initialize an endpoint
+  * @param  USBx  Selected device
+  * @param  ep pointer to endpoint structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t epnum = (uint32_t)ep->num;
+
+  /* Read DEPCTLn register */
+  if (ep->is_in == 1U)
+  {
+    USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
+    USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
+    USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP |
+                                   USB_OTG_DIEPCTL_MPSIZ |
+                                   USB_OTG_DIEPCTL_TXFNUM |
+                                   USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
+                                   USB_OTG_DIEPCTL_EPTYP);
+  }
+  else
+  {
+    USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
+    USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
+    USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP |
+                                    USB_OTG_DOEPCTL_MPSIZ |
+                                    USB_OTG_DOEPCTL_SD0PID_SEVNFRM |
+                                    USB_OTG_DOEPCTL_EPTYP);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  De-activate and de-initialize a dedicated endpoint
+  * @param  USBx  Selected device
+  * @param  ep pointer to endpoint structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t epnum = (uint32_t)ep->num;
+
+  /* Read DEPCTLn register */
+  if (ep->is_in == 1U)
+  {
+    USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
+    USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
+  }
+  else
+  {
+    USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
+    USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_EPStartXfer : setup and starts a transfer over an EP
+  * @param  USBx  Selected device
+  * @param  ep pointer to endpoint structure
+  * @param  dma USB dma enabled or disabled
+  *          This parameter can be one of these values:
+  *           0 : DMA feature not used
+  *           1 : DMA feature used
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t epnum = (uint32_t)ep->num;
+  uint16_t pktcnt;
+
+  /* IN endpoint */
+  if (ep->is_in == 1U)
+  {
+    /* Zero Length Packet? */
+    if (ep->xfer_len == 0U)
+    {
+      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
+      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
+      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
+    }
+    else
+    {
+      /* Program the transfer size and packet count
+      * as follows: xfersize = N * maxpacket +
+      * short_packet pktcnt = N + (short_packet
+      * exist ? 1 : 0)
+      */
+      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
+      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
+      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19));
+      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
+
+      if (ep->type == EP_TYPE_ISOC)
+      {
+        USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT);
+        USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29));
+      }
+    }
+
+    if (dma == 1U)
+    {
+      if ((uint32_t)ep->dma_addr != 0U)
+      {
+        USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr);
+      }
+
+      if (ep->type == EP_TYPE_ISOC)
+      {
+        if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
+        {
+          USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
+        }
+        else
+        {
+          USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
+        }
+      }
+
+      /* EP enable, IN data in FIFO */
+      USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
+    }
+    else
+    {
+      /* EP enable, IN data in FIFO */
+      USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
+
+      if (ep->type != EP_TYPE_ISOC)
+      {
+        /* Enable the Tx FIFO Empty Interrupt for this EP */
+        if (ep->xfer_len > 0U)
+        {
+          USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK);
+        }
+      }
+      else
+      {
+        if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
+        {
+          USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
+        }
+        else
+        {
+          USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
+        }
+
+        (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma);
+      }
+    }
+  }
+  else /* OUT endpoint */
+  {
+    /* Program the transfer size and packet count as follows:
+    * pktcnt = N
+    * xfersize = N * maxpacket
+    */
+    USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
+    USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
+
+    if (ep->xfer_len == 0U)
+    {
+      USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);
+      USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
+    }
+    else
+    {
+      pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket);
+      USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19);
+      USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt);
+    }
+
+    if (dma == 1U)
+    {
+      if ((uint32_t)ep->xfer_buff != 0U)
+      {
+        USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff);
+      }
+    }
+
+    if (ep->type == EP_TYPE_ISOC)
+    {
+      if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
+      {
+        USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;
+      }
+      else
+      {
+        USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
+      }
+    }
+    /* EP enable */
+    USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_EP0StartXfer : setup and starts a transfer over the EP  0
+  * @param  USBx  Selected device
+  * @param  ep pointer to endpoint structure
+  * @param  dma USB dma enabled or disabled
+  *          This parameter can be one of these values:
+  *           0 : DMA feature not used
+  *           1 : DMA feature used
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t epnum = (uint32_t)ep->num;
+
+  /* IN endpoint */
+  if (ep->is_in == 1U)
+  {
+    /* Zero Length Packet? */
+    if (ep->xfer_len == 0U)
+    {
+      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
+      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
+      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
+    }
+    else
+    {
+      /* Program the transfer size and packet count
+      * as follows: xfersize = N * maxpacket +
+      * short_packet pktcnt = N + (short_packet
+      * exist ? 1 : 0)
+      */
+      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
+      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
+
+      if (ep->xfer_len > ep->maxpacket)
+      {
+        ep->xfer_len = ep->maxpacket;
+      }
+      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
+      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
+    }
+
+    if (dma == 1U)
+    {
+      if ((uint32_t)ep->dma_addr != 0U)
+      {
+        USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr);
+      }
+
+      /* EP enable, IN data in FIFO */
+      USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
+    }
+    else
+    {
+      /* EP enable, IN data in FIFO */
+      USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
+
+      /* Enable the Tx FIFO Empty Interrupt for this EP */
+      if (ep->xfer_len > 0U)
+      {
+        USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK);
+      }
+    }
+  }
+  else /* OUT endpoint */
+  {
+    /* Program the transfer size and packet count as follows:
+    * pktcnt = N
+    * xfersize = N * maxpacket
+    */
+    USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
+    USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
+
+    if (ep->xfer_len > 0U)
+    {
+      ep->xfer_len = ep->maxpacket;
+    }
+
+    USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
+    USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket));
+
+    if (dma == 1U)
+    {
+      if ((uint32_t)ep->xfer_buff != 0U)
+      {
+        USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff);
+      }
+    }
+
+    /* EP enable */
+    USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_WritePacket : Writes a packet into the Tx FIFO associated
+  *         with the EP/channel
+  * @param  USBx  Selected device
+  * @param  src   pointer to source buffer
+  * @param  ch_ep_num  endpoint or host channel number
+  * @param  len  Number of bytes to write
+  * @param  dma USB dma enabled or disabled
+  *          This parameter can be one of these values:
+  *           0 : DMA feature not used
+  *           1 : DMA feature used
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t *pSrc = (uint32_t *)src;
+  uint32_t count32b, i;
+
+  if (dma == 0U)
+  {
+    count32b = ((uint32_t)len + 3U) / 4U;
+    for (i = 0U; i < count32b; i++)
+    {
+      USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc);
+      pSrc++;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_ReadPacket : read a packet from the RX FIFO
+  * @param  USBx  Selected device
+  * @param  dest  source pointer
+  * @param  len  Number of bytes to read
+  * @retval pointer to destination buffer
+  */
+void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t *pDest = (uint32_t *)dest;
+  uint32_t i;
+  uint32_t count32b = ((uint32_t)len + 3U) / 4U;
+
+  for (i = 0U; i < count32b; i++)
+  {
+    __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U));
+    pDest++;
+  }
+
+  return ((void *)pDest);
+}
+
+/**
+  * @brief  USB_EPSetStall : set a stall condition over an EP
+  * @param  USBx  Selected device
+  * @param  ep pointer to endpoint structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t epnum = (uint32_t)ep->num;
+
+  if (ep->is_in == 1U)
+  {
+    if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U))
+    {
+      USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS);
+    }
+    USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;
+  }
+  else
+  {
+    if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U))
+    {
+      USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS);
+    }
+    USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_EPClearStall : Clear a stall condition over an EP
+  * @param  USBx  Selected device
+  * @param  ep pointer to endpoint structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t epnum = (uint32_t)ep->num;
+
+  if (ep->is_in == 1U)
+  {
+    USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
+    if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))
+    {
+      USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */
+    }
+  }
+  else
+  {
+    USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
+    if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))
+    {
+      USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_StopDevice : Stop the usb device mode
+  * @param  USBx  Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)
+{
+  HAL_StatusTypeDef ret;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t i;
+
+  /* Clear Pending interrupt */
+  for (i = 0U; i < 15U; i++)
+  {
+    USBx_INEP(i)->DIEPINT = 0xFB7FU;
+    USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
+  }
+
+  /* Clear interrupt masks */
+  USBx_DEVICE->DIEPMSK  = 0U;
+  USBx_DEVICE->DOEPMSK  = 0U;
+  USBx_DEVICE->DAINTMSK = 0U;
+
+  /* Flush the FIFO */
+  ret = USB_FlushRxFifo(USBx);
+  if (ret != HAL_OK)
+  {
+    return ret;
+  }
+
+  ret = USB_FlushTxFifo(USBx,  0x10U);
+  if (ret != HAL_OK)
+  {
+    return ret;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  USB_SetDevAddress : Stop the usb device mode
+  * @param  USBx  Selected device
+  * @param  address  new device address to be assigned
+  *          This parameter can be a value from 0 to 255
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD);
+  USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down
+  * @param  USBx  Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  USB_DevConnect(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS;
+  HAL_Delay(3U);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down
+  * @param  USBx  Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
+  HAL_Delay(3U);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_ReadInterrupts: return the global USB interrupt status
+  * @param  USBx  Selected device
+  * @retval HAL status
+  */
+uint32_t  USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t tmpreg;
+
+  tmpreg = USBx->GINTSTS;
+  tmpreg &= USBx->GINTMSK;
+
+  return tmpreg;
+}
+
+/**
+  * @brief  USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status
+  * @param  USBx  Selected device
+  * @retval HAL status
+  */
+uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t tmpreg;
+
+  tmpreg  = USBx_DEVICE->DAINT;
+  tmpreg &= USBx_DEVICE->DAINTMSK;
+
+  return ((tmpreg & 0xffff0000U) >> 16);
+}
+
+/**
+  * @brief  USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status
+  * @param  USBx  Selected device
+  * @retval HAL status
+  */
+uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t tmpreg;
+
+  tmpreg  = USBx_DEVICE->DAINT;
+  tmpreg &= USBx_DEVICE->DAINTMSK;
+
+  return ((tmpreg & 0xFFFFU));
+}
+
+/**
+  * @brief  Returns Device OUT EP Interrupt register
+  * @param  USBx  Selected device
+  * @param  epnum  endpoint number
+  *          This parameter can be a value from 0 to 15
+  * @retval Device OUT EP Interrupt register
+  */
+uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t tmpreg;
+
+  tmpreg  = USBx_OUTEP((uint32_t)epnum)->DOEPINT;
+  tmpreg &= USBx_DEVICE->DOEPMSK;
+
+  return tmpreg;
+}
+
+/**
+  * @brief  Returns Device IN EP Interrupt register
+  * @param  USBx  Selected device
+  * @param  epnum  endpoint number
+  *          This parameter can be a value from 0 to 15
+  * @retval Device IN EP Interrupt register
+  */
+uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t tmpreg, msk, emp;
+
+  msk = USBx_DEVICE->DIEPMSK;
+  emp = USBx_DEVICE->DIEPEMPMSK;
+  msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7;
+  tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk;
+
+  return tmpreg;
+}
+
+/**
+  * @brief  USB_ClearInterrupts: clear a USB interrupt
+  * @param  USBx  Selected device
+  * @param  interrupt  interrupt flag
+  * @retval None
+  */
+void  USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)
+{
+  USBx->GINTSTS |= interrupt;
+}
+
+/**
+  * @brief  Returns USB core mode
+  * @param  USBx  Selected device
+  * @retval return core mode : Host or Device
+  *          This parameter can be one of these values:
+  *           0 : Host
+  *           1 : Device
+  */
+uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)
+{
+  return ((USBx->GINTSTS) & 0x1U);
+}
+
+/**
+  * @brief  Activate EP0 for Setup transactions
+  * @param  USBx  Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  /* Set the MPS of the IN EP0 to 64 bytes */
+  USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;
+
+  USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Prepare the EP0 to start the first control setup
+  * @param  USBx  Selected device
+  * @param  dma USB dma enabled or disabled
+  *          This parameter can be one of these values:
+  *           0 : DMA feature not used
+  *           1 : DMA feature used
+  * @param  psetup  pointer to setup packet
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
+
+  if (gSNPSiD > USB_OTG_CORE_ID_300A)
+  {
+    if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
+    {
+      return HAL_OK;
+    }
+  }
+
+  USBx_OUTEP(0U)->DOEPTSIZ = 0U;
+  USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
+  USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U);
+  USBx_OUTEP(0U)->DOEPTSIZ |=  USB_OTG_DOEPTSIZ_STUPCNT;
+
+  if (dma == 1U)
+  {
+    USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup;
+    /* EP enable */
+    USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Reset the USB Core (needed after USB clock settings change)
+  * @param  USBx  Selected device
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t count = 0U;
+
+  /* Wait for AHB master IDLE state. */
+  do
+  {
+    if (++count > 200000U)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
+
+  /* Core Soft Reset */
+  count = 0U;
+  USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
+
+  do
+  {
+    if (++count > 200000U)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_HostInit : Initializes the USB OTG controller registers
+  *         for Host mode
+  * @param  USBx  Selected device
+  * @param  cfg   pointer to a USB_OTG_CfgTypeDef structure that contains
+  *         the configuration information for the specified USBx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t i;
+
+  /* Restart the Phy Clock */
+  USBx_PCGCCTL = 0U;
+
+  /* Disable VBUS sensing */
+  USBx->GCCFG &= ~(USB_OTG_GCCFG_VBDEN);
+
+  /* Disable Battery chargin detector */
+  USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN);
+
+
+  if ((USBx->CID & (0x1U << 8)) != 0U)
+  {
+    if (cfg.speed == USB_OTG_SPEED_FULL)
+    {
+      /* Force Device Enumeration to FS/LS mode only */
+      USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS;
+    }
+    else
+    {
+      /* Set default Max speed support */
+      USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);
+    }
+  }
+  else
+  {
+    /* Set default Max speed support */
+    USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);
+  }
+
+  /* Make sure the FIFOs are flushed. */
+  (void)USB_FlushTxFifo(USBx, 0x10U); /* all Tx FIFOs */
+  (void)USB_FlushRxFifo(USBx);
+
+  /* Clear all pending HC Interrupts */
+  for (i = 0U; i < cfg.Host_channels; i++)
+  {
+    USBx_HC(i)->HCINT = 0xFFFFFFFFU;
+    USBx_HC(i)->HCINTMSK = 0U;
+  }
+
+  /* Enable VBUS driving */
+  (void)USB_DriveVbus(USBx, 1U);
+
+  HAL_Delay(200U);
+
+  /* Disable all interrupts. */
+  USBx->GINTMSK = 0U;
+
+  /* Clear any pending interrupts */
+  USBx->GINTSTS = 0xFFFFFFFFU;
+
+  if ((USBx->CID & (0x1U << 8)) != 0U)
+  {
+    /* set Rx FIFO size */
+    USBx->GRXFSIZ  = 0x200U;
+    USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x100U << 16) & USB_OTG_NPTXFD) | 0x200U);
+    USBx->HPTXFSIZ = (uint32_t)(((0xE0U << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U);
+  }
+  else
+  {
+    /* set Rx FIFO size */
+    USBx->GRXFSIZ  = 0x80U;
+    USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x60U << 16) & USB_OTG_NPTXFD) | 0x80U);
+    USBx->HPTXFSIZ = (uint32_t)(((0x40U << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U);
+  }
+
+  /* Enable the common interrupts */
+  if (cfg.dma_enable == 0U)
+  {
+    USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
+  }
+
+  /* Enable interrupts matching to the Host mode ONLY */
+  USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM            | USB_OTG_GINTMSK_HCIM | \
+                    USB_OTG_GINTMSK_SOFM             | USB_OTG_GINTSTS_DISCINT | \
+                    USB_OTG_GINTMSK_PXFRM_IISOOXFRM  | USB_OTG_GINTMSK_WUIM);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the
+  *         HCFG register on the PHY type and set the right frame interval
+  * @param  USBx  Selected device
+  * @param  freq  clock frequency
+  *          This parameter can be one of these values:
+  *           HCFG_48_MHZ : Full Speed 48 MHz Clock
+  *           HCFG_6_MHZ : Low Speed 6 MHz Clock
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS);
+  USBx_HOST->HCFG |= (uint32_t)freq & USB_OTG_HCFG_FSLSPCS;
+
+  if (freq == HCFG_48_MHZ)
+  {
+    USBx_HOST->HFIR = 48000U;
+  }
+  else if (freq == HCFG_6_MHZ)
+  {
+    USBx_HOST->HFIR = 6000U;
+  }
+  else
+  {
+    /* ... */
+  }
+
+  return HAL_OK;
+}
+
+/**
+* @brief  USB_OTG_ResetPort : Reset Host Port
+  * @param  USBx  Selected device
+  * @retval HAL status
+  * @note (1)The application must wait at least 10 ms
+  *   before clearing the reset bit.
+  */
+HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  __IO uint32_t hprt0 = 0U;
+
+  hprt0 = USBx_HPRT0;
+
+  hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |
+             USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
+
+  USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0);
+  HAL_Delay(100U);                                 /* See Note #1 */
+  USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0);
+  HAL_Delay(10U);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_DriveVbus : activate or de-activate vbus
+  * @param  state  VBUS state
+  *          This parameter can be one of these values:
+  *           0 : VBUS Active
+  *           1 : VBUS Inactive
+  * @retval HAL status
+*/
+HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  __IO uint32_t hprt0 = 0U;
+
+  hprt0 = USBx_HPRT0;
+
+  hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |
+             USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
+
+  if (((hprt0 & USB_OTG_HPRT_PPWR) == 0U) && (state == 1U))
+  {
+    USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0);
+  }
+  if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0U))
+  {
+    USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0);
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Return Host Core speed
+  * @param  USBx  Selected device
+  * @retval speed : Host speed
+  *          This parameter can be one of these values:
+  *            @arg HCD_SPEED_HIGH: High speed mode
+  *            @arg HCD_SPEED_FULL: Full speed mode
+  *            @arg HCD_SPEED_LOW: Low speed mode
+  */
+uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  __IO uint32_t hprt0 = 0U;
+
+  hprt0 = USBx_HPRT0;
+  return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17);
+}
+
+/**
+  * @brief  Return Host Current Frame number
+  * @param  USBx  Selected device
+  * @retval current frame number
+*/
+uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM);
+}
+
+/**
+  * @brief  Initialize a host channel
+  * @param  USBx  Selected device
+  * @param  ch_num  Channel number
+  *         This parameter can be a value from 1 to 15
+  * @param  epnum  Endpoint number
+  *          This parameter can be a value from 1 to 15
+  * @param  dev_address  Current device address
+  *          This parameter can be a value from 0 to 255
+  * @param  speed  Current device speed
+  *          This parameter can be one of these values:
+  *            @arg USB_OTG_SPEED_HIGH: High speed mode
+  *            @arg USB_OTG_SPEED_FULL: Full speed mode
+  *            @arg USB_OTG_SPEED_LOW: Low speed mode
+  * @param  ep_type  Endpoint Type
+  *          This parameter can be one of these values:
+  *            @arg EP_TYPE_CTRL: Control type
+  *            @arg EP_TYPE_ISOC: Isochronous type
+  *            @arg EP_TYPE_BULK: Bulk type
+  *            @arg EP_TYPE_INTR: Interrupt type
+  * @param  mps  Max Packet Size
+  *          This parameter can be a value from 0 to32K
+  * @retval HAL state
+  */
+HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
+                              uint8_t ch_num,
+                              uint8_t epnum,
+                              uint8_t dev_address,
+                              uint8_t speed,
+                              uint8_t ep_type,
+                              uint16_t mps)
+{
+  HAL_StatusTypeDef ret = HAL_OK;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t HCcharEpDir, HCcharLowSpeed;
+
+  /* Clear old interrupt conditions for this host channel. */
+  USBx_HC((uint32_t)ch_num)->HCINT = 0xFFFFFFFFU;
+
+  /* Enable channel interrupts required for this transfer. */
+  switch (ep_type)
+  {
+    case EP_TYPE_CTRL:
+    case EP_TYPE_BULK:
+      USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |
+                                            USB_OTG_HCINTMSK_STALLM |
+                                            USB_OTG_HCINTMSK_TXERRM |
+                                            USB_OTG_HCINTMSK_DTERRM |
+                                            USB_OTG_HCINTMSK_AHBERR |
+                                            USB_OTG_HCINTMSK_NAKM;
+
+      if ((epnum & 0x80U) == 0x80U)
+      {
+        USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
+      }
+      else
+      {
+        if ((USBx->CID & (0x1U << 8)) != 0U)
+        {
+          USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);
+        }
+      }
+      break;
+
+    case EP_TYPE_INTR:
+      USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |
+                                            USB_OTG_HCINTMSK_STALLM |
+                                            USB_OTG_HCINTMSK_TXERRM |
+                                            USB_OTG_HCINTMSK_DTERRM |
+                                            USB_OTG_HCINTMSK_NAKM   |
+                                            USB_OTG_HCINTMSK_AHBERR |
+                                            USB_OTG_HCINTMSK_FRMORM;
+
+      if ((epnum & 0x80U) == 0x80U)
+      {
+        USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
+      }
+
+      break;
+
+    case EP_TYPE_ISOC:
+      USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |
+                                            USB_OTG_HCINTMSK_ACKM   |
+                                            USB_OTG_HCINTMSK_AHBERR |
+                                            USB_OTG_HCINTMSK_FRMORM;
+
+      if ((epnum & 0x80U) == 0x80U)
+      {
+        USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM);
+      }
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+  }
+
+  /* Enable the top level host channel interrupt. */
+  USBx_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU);
+
+  /* Make sure host channel interrupts are enabled. */
+  USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM;
+
+  /* Program the HCCHAR register */
+  if ((epnum & 0x80U) == 0x80U)
+  {
+    HCcharEpDir = (0x1U << 15) & USB_OTG_HCCHAR_EPDIR;
+  }
+  else
+  {
+    HCcharEpDir = 0U;
+  }
+
+  if (speed == HPRT0_PRTSPD_LOW_SPEED)
+  {
+    HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV;
+  }
+  else
+  {
+    HCcharLowSpeed = 0U;
+  }
+
+  USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) |
+                                      ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) |
+                                      (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) |
+                                      ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | HCcharEpDir | HCcharLowSpeed;
+
+  if (ep_type == EP_TYPE_INTR)
+  {
+    USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ;
+  }
+
+  return ret;
+}
+
+/**
+  * @brief  Start a transfer over a host channel
+  * @param  USBx  Selected device
+  * @param  hc  pointer to host channel structure
+  * @param  dma USB dma enabled or disabled
+  *          This parameter can be one of these values:
+  *           0 : DMA feature not used
+  *           1 : DMA feature used
+  * @retval HAL state
+  */
+HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t ch_num = (uint32_t)hc->ch_num;
+  static __IO uint32_t tmpreg = 0U;
+  uint8_t  is_oddframe;
+  uint16_t len_words;
+  uint16_t num_packets;
+  uint16_t max_hc_pkt_count = 256U;
+
+  if (((USBx->CID & (0x1U << 8)) != 0U) && (hc->speed == USBH_HS_SPEED))
+  {
+    if ((dma == 0U) && (hc->do_ping == 1U))
+    {
+      (void)USB_DoPing(USBx, hc->ch_num);
+      return HAL_OK;
+    }
+    else if (dma == 1U)
+    {
+      USBx_HC(ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);
+      hc->do_ping = 0U;
+    }
+    else
+    {
+      /* ... */
+    }
+  }
+
+  /* Compute the expected number of packets associated to the transfer */
+  if (hc->xfer_len > 0U)
+  {
+    num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet);
+
+    if (num_packets > max_hc_pkt_count)
+    {
+      num_packets = max_hc_pkt_count;
+      hc->xfer_len = (uint32_t)num_packets * hc->max_packet;
+    }
+  }
+  else
+  {
+    num_packets = 1U;
+  }
+  if (hc->ep_is_in != 0U)
+  {
+    hc->xfer_len = (uint32_t)num_packets * hc->max_packet;
+  }
+
+  /* Initialize the HCTSIZn register */
+  USBx_HC(ch_num)->HCTSIZ = (hc->xfer_len & USB_OTG_HCTSIZ_XFRSIZ) |
+                            (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |
+                            (((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID);
+
+  if (dma != 0U)
+  {
+    /* xfer_buff MUST be 32-bits aligned */
+    USBx_HC(ch_num)->HCDMA = (uint32_t)hc->xfer_buff;
+  }
+
+  is_oddframe = (((uint32_t)USBx_HOST->HFNUM & 0x01U) != 0U) ? 0U : 1U;
+  USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM;
+  USBx_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29;
+
+  /* Set host channel enable */
+  tmpreg = USBx_HC(ch_num)->HCCHAR;
+  tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+
+  /* make sure to set the correct ep direction */
+  if (hc->ep_is_in != 0U)
+  {
+    tmpreg |= USB_OTG_HCCHAR_EPDIR;
+  }
+  else
+  {
+    tmpreg &= ~USB_OTG_HCCHAR_EPDIR;
+  }
+  tmpreg |= USB_OTG_HCCHAR_CHENA;
+  USBx_HC(ch_num)->HCCHAR = tmpreg;
+
+  if (dma == 0U) /* Slave mode */
+  {
+    if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U))
+    {
+      switch (hc->ep_type)
+      {
+        /* Non periodic transfer */
+        case EP_TYPE_CTRL:
+        case EP_TYPE_BULK:
+
+          len_words = (uint16_t)((hc->xfer_len + 3U) / 4U);
+
+          /* check if there is enough space in FIFO space */
+          if (len_words > (USBx->HNPTXSTS & 0xFFFFU))
+          {
+            /* need to process data in nptxfempty interrupt */
+            USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM;
+          }
+          break;
+
+        /* Periodic transfer */
+        case EP_TYPE_INTR:
+        case EP_TYPE_ISOC:
+          len_words = (uint16_t)((hc->xfer_len + 3U) / 4U);
+          /* check if there is enough space in FIFO space */
+          if (len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */
+          {
+            /* need to process data in ptxfempty interrupt */
+            USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM;
+          }
+          break;
+
+        default:
+          break;
+      }
+
+      /* Write packet into the Tx FIFO. */
+      (void)USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len, 0);
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Read all host channel interrupts status
+  * @param  USBx  Selected device
+  * @retval HAL state
+  */
+uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  return ((USBx_HOST->HAINT) & 0xFFFFU);
+}
+
+/**
+  * @brief  Halt a host channel
+  * @param  USBx  Selected device
+  * @param  hc_num  Host Channel number
+  *         This parameter can be a value from 1 to 15
+  * @retval HAL state
+  */
+HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t hcnum = (uint32_t)hc_num;
+  uint32_t count = 0U;
+  uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18;
+
+  /* Check for space in the request queue to issue the halt. */
+  if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK))
+  {
+    USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
+
+    if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U)
+    {
+      USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
+      USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+      USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
+      do
+      {
+        if (++count > 1000U)
+        {
+          break;
+        }
+      }
+      while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
+    }
+    else
+    {
+      USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+    }
+  }
+  else
+  {
+    USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
+
+    if ((USBx_HOST->HPTXSTS & (0xFFU << 16)) == 0U)
+    {
+      USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
+      USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+      USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
+      do
+      {
+        if (++count > 1000U)
+        {
+          break;
+        }
+      }
+      while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
+    }
+    else
+    {
+      USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initiate Do Ping protocol
+  * @param  USBx  Selected device
+  * @param  hc_num  Host Channel number
+  *         This parameter can be a value from 1 to 15
+  * @retval HAL state
+  */
+HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t chnum = (uint32_t)ch_num;
+  uint32_t num_packets = 1U;
+  uint32_t tmpreg;
+
+  USBx_HC(chnum)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |
+                           USB_OTG_HCTSIZ_DOPING;
+
+  /* Set host channel enable */
+  tmpreg = USBx_HC(chnum)->HCCHAR;
+  tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+  tmpreg |= USB_OTG_HCCHAR_CHENA;
+  USBx_HC(chnum)->HCCHAR = tmpreg;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop Host Core
+  * @param  USBx  Selected device
+  * @retval HAL state
+  */
+HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t count = 0U;
+  uint32_t value;
+  uint32_t i;
+
+  (void)USB_DisableGlobalInt(USBx);
+
+  /* Flush FIFO */
+  (void)USB_FlushTxFifo(USBx, 0x10U);
+  (void)USB_FlushRxFifo(USBx);
+
+  /* Flush out any leftover queued requests. */
+  for (i = 0U; i <= 15U; i++)
+  {
+    value = USBx_HC(i)->HCCHAR;
+    value |=  USB_OTG_HCCHAR_CHDIS;
+    value &= ~USB_OTG_HCCHAR_CHENA;
+    value &= ~USB_OTG_HCCHAR_EPDIR;
+    USBx_HC(i)->HCCHAR = value;
+  }
+
+  /* Halt all channels to put them into a known state. */
+  for (i = 0U; i <= 15U; i++)
+  {
+    value = USBx_HC(i)->HCCHAR;
+    value |= USB_OTG_HCCHAR_CHDIS;
+    value |= USB_OTG_HCCHAR_CHENA;
+    value &= ~USB_OTG_HCCHAR_EPDIR;
+    USBx_HC(i)->HCCHAR = value;
+
+    do
+    {
+      if (++count > 1000U)
+      {
+        break;
+      }
+    }
+    while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
+  }
+
+  /* Clear any pending Host interrupts */
+  USBx_HOST->HAINT = 0xFFFFFFFFU;
+  USBx->GINTSTS = 0xFFFFFFFFU;
+
+  (void)USB_EnableGlobalInt(USBx);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_ActivateRemoteWakeup active remote wakeup signalling
+  * @param  USBx Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
+  {
+    /* active Remote wakeup signalling */
+    USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_DeActivateRemoteWakeup de-active remote wakeup signalling
+  * @param  USBx Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  /* active Remote wakeup signalling */
+  USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);
+
+  return HAL_OK;
+}
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_utils.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_utils.c
new file mode 100644
index 00000000..cf19f617
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_utils.c
@@ -0,0 +1,975 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_ll_utils.c
+  * @author  MCD Application Team
+  * @brief   UTILS LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_ll_utils.h"
+#include "stm32h7xx_ll_rcc.h"
+#include "stm32h7xx_ll_pwr.h"
+
+#ifdef  USE_FULL_ASSERT
+  #include "stm32_assert.h"
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32H7xx_LL_Driver
+  * @{
+  */
+
+/** @addtogroup UTILS_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup UTILS_LL_Private_Constants
+  * @{
+  */
+#if (POWER_DOMAINS_NUMBER == 3U)
+#define UTILS_MAX_FREQUENCY_SCALE1  400000000U      /*!< Maximum frequency for system clock at power scale1, in Hz */
+#define UTILS_MAX_FREQUENCY_SCALE2  300000000U      /*!< Maximum frequency for system clock at power scale2, in Hz */
+#define UTILS_MAX_FREQUENCY_SCALE3  200000000U      /*!< Maximum frequency for system clock at power scale3, in Hz */
+#else
+#define UTILS_MAX_FREQUENCY_SCALE0  280000000U      /*!< Maximum frequency for system clock at power scale0, in Hz */
+#define UTILS_MAX_FREQUENCY_SCALE1  225000000U      /*!< Maximum frequency for system clock at power scale1, in Hz */
+#define UTILS_MAX_FREQUENCY_SCALE2  160000000U      /*!< Maximum frequency for system clock at power scale2, in Hz */
+#define UTILS_MAX_FREQUENCY_SCALE3   88000000U      /*!< Maximum frequency for system clock at power scale3, in Hz */
+#endif /*POWER_DOMAINS_NUMBER == 3U*/
+
+/* Defines used for PLL range */
+#define UTILS_PLLVCO_INPUT_MIN1       1000000U      /*!< Frequency min for the low range PLLVCO input, in Hz    */
+#define UTILS_PLLVCO_INPUT_MAX1       2000000U      /*!< Frequency max for the wide range PLLVCO input, in Hz   */
+#define UTILS_PLLVCO_INPUT_MIN2       2000000U      /*!< Frequency min for the low range PLLVCO input, in Hz    */
+#define UTILS_PLLVCO_INPUT_MAX2       4000000U      /*!< Frequency max for the wide range PLLVCO input, in Hz   */
+#define UTILS_PLLVCO_INPUT_MIN3       4000000U      /*!< Frequency min for the low range PLLVCO input, in Hz    */
+#define UTILS_PLLVCO_INPUT_MAX3       8000000U      /*!< Frequency max for the wide range PLLVCO input, in Hz   */
+#define UTILS_PLLVCO_INPUT_MIN4       8000000U      /*!< Frequency min for the low range PLLVCO input, in Hz    */
+#define UTILS_PLLVCO_INPUT_MAX4      16000000U      /*!< Frequency max for the wide range PLLVCO input, in Hz   */
+
+#if (POWER_DOMAINS_NUMBER == 3U)
+#define UTILS_PLLVCO_MEDIUM_OUTPUT_MIN    150000000U      /*!< Frequency min for the medium range PLLVCO output, in Hz   */
+#define UTILS_PLLVCO_WIDE_OUTPUT_MIN      192000000U      /*!< Frequency min for the wide range PLLVCO output, in Hz   */
+#define UTILS_PLLVCO_MEDIUM_OUTPUT_MAX    420000000U      /*!< Frequency max for the medium range PLLVCO output, in Hz  */
+#define UTILS_PLLVCO_WIDE_OUTPUT_MAX      836000000U      /*!< Frequency max for the wide range PLLVCO output, in Hz  */
+#else
+#define UTILS_PLLVCO_MEDIUM_OUTPUT_MIN    150000000U      /*!< Frequency min for the medium range PLLVCO output, in Hz   */
+#define UTILS_PLLVCO_WIDE_OUTPUT_MIN      128000000U      /*!< Frequency min for the wide range PLLVCO output, in Hz   */
+#define UTILS_PLLVCO_MEDIUM_OUTPUT_MAX    420000000U      /*!< Frequency max for the medium range PLLVCO output, in Hz  */
+#define UTILS_PLLVCO_WIDE_OUTPUT_MAX      560000000U      /*!< Frequency max for the wide range PLLVCO output, in Hz  */
+#endif /*POWER_DOMAINS_NUMBER == 3U*/
+
+/* Defines used for HSE range */
+#define UTILS_HSE_FREQUENCY_MIN      4000000U        /*!< Frequency min for HSE frequency, in Hz   */
+#define UTILS_HSE_FREQUENCY_MAX     48000000U        /*!< Frequency max for HSE frequency, in Hz   */
+
+/* Defines used for FLASH latency according to HCLK Frequency */
+#if (POWER_DOMAINS_NUMBER == 2U)
+#define UTILS_SCALE0_LATENCY0_FREQ   44000000U       /*!< HCLK frequency to set FLASH latency 0 in power scale 0  */
+#define UTILS_SCALE0_LATENCY1_FREQ   88000000U       /*!< HCLK frequency to set FLASH latency 1 in power scale 0  */
+#define UTILS_SCALE0_LATENCY2_FREQ  132000000U       /*!< HCLK frequency to set FLASH latency 2 in power scale 0  */
+#define UTILS_SCALE0_LATENCY3_FREQ  176000000U       /*!< HCLK frequency to set FLASH latency 3 in power scale 0  */
+#define UTILS_SCALE0_LATENCY4_FREQ  220000000U       /*!< HCLK frequency to set FLASH latency 4 in power scale 0  */
+#define UTILS_SCALE0_LATENCY5_FREQ  264000000U       /*!< HCLK frequency to set FLASH latency 5 in power scale 0  */
+#define UTILS_SCALE0_LATENCY6_FREQ  280000000U       /*!< HCLK frequency to set FLASH latency 6 in power scale 0  */
+
+#define UTILS_SCALE1_LATENCY0_FREQ   42000000U      /*!< HCLK frequency to set FLASH latency 0 in power scale 1  */
+#define UTILS_SCALE1_LATENCY1_FREQ   84000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 1  */
+#define UTILS_SCALE1_LATENCY2_FREQ  126000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 1  */
+#define UTILS_SCALE1_LATENCY3_FREQ  168000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 1  */
+#define UTILS_SCALE1_LATENCY4_FREQ  210000000U      /*!< HCLK frequency to set FLASH latency 4 in power scale 1  */
+#define UTILS_SCALE1_LATENCY5_FREQ  225000000U      /*!< HCLK frequency to set FLASH latency 5 in power scale 1  */
+
+#define UTILS_SCALE2_LATENCY0_FREQ   34000000U      /*!< HCLK frequency to set FLASH latency 0 in power scale 2  */
+#define UTILS_SCALE2_LATENCY1_FREQ   68000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 2  */
+#define UTILS_SCALE2_LATENCY2_FREQ  102000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 2  */
+#define UTILS_SCALE2_LATENCY3_FREQ  136000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 2  */
+#define UTILS_SCALE2_LATENCY4_FREQ  160000000U      /*!< HCLK frequency to set FLASH latency 4 in power scale 2  */
+
+#define UTILS_SCALE3_LATENCY0_FREQ   22000000U      /*!< HCLK frequency to set FLASH latency 0 in power scale 3  */
+#define UTILS_SCALE3_LATENCY1_FREQ   44000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 3  */
+#define UTILS_SCALE3_LATENCY2_FREQ   66000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 3  */
+#define UTILS_SCALE3_LATENCY3_FREQ   88000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 3  */
+
+#else
+
+#define UTILS_SCALE1_LATENCY0_FREQ   70000000U      /*!< HCLK frequency to set FLASH latency 0 in power scale 1  */
+#define UTILS_SCALE1_LATENCY1_FREQ  140000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 1  */
+#define UTILS_SCALE1_LATENCY2_FREQ  210000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 1  */
+
+#define UTILS_SCALE2_LATENCY0_FREQ   55000000U      /*!< HCLK frequency to set FLASH latency 0 in power scale 2  */
+#define UTILS_SCALE2_LATENCY1_FREQ  110000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 2  */
+#define UTILS_SCALE2_LATENCY2_FREQ  165000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 2  */
+#define UTILS_SCALE2_LATENCY3_FREQ  220000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 2  */
+
+#define UTILS_SCALE3_LATENCY0_FREQ   45000000U      /*!< HCLK frequency to set FLASH latency 0 in power scale 3  */
+#define UTILS_SCALE3_LATENCY1_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 3  */
+#define UTILS_SCALE3_LATENCY2_FREQ  135000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 3  */
+#define UTILS_SCALE3_LATENCY3_FREQ  180000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 3  */
+#define UTILS_SCALE3_LATENCY4_FREQ  225000000U      /*!< HCLK frequency to set FLASH latency 4 in power scale 3  */
+#endif /*POWER_DOMAINS_NUMBER == 2U*/
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup UTILS_LL_Private_Macros
+  * @{
+  */
+#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1)   \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2)   \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4)   \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8)   \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16)  \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64)  \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
+
+#define IS_LL_UTILS_AHB_DIV(__VALUE__)    (((__VALUE__) == LL_RCC_AHB_DIV_1)   \
+                                        || ((__VALUE__) == LL_RCC_AHB_DIV_2)   \
+                                        || ((__VALUE__) == LL_RCC_AHB_DIV_4)   \
+                                        || ((__VALUE__) == LL_RCC_AHB_DIV_8)   \
+                                        || ((__VALUE__) == LL_RCC_AHB_DIV_16)  \
+                                        || ((__VALUE__) == LL_RCC_AHB_DIV_64)  \
+                                        || ((__VALUE__) == LL_RCC_AHB_DIV_128) \
+                                        || ((__VALUE__) == LL_RCC_AHB_DIV_256) \
+                                        || ((__VALUE__) == LL_RCC_AHB_DIV_512))
+
+#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
+                                      || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
+                                      || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
+                                      || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
+                                      || ((__VALUE__) == LL_RCC_APB1_DIV_16))
+
+#define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
+                                      || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
+                                      || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
+                                      || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
+                                      || ((__VALUE__) == LL_RCC_APB2_DIV_16))
+
+#define IS_LL_UTILS_APB3_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB3_DIV_1) \
+                                      || ((__VALUE__) == LL_RCC_APB3_DIV_2) \
+                                      || ((__VALUE__) == LL_RCC_APB3_DIV_4) \
+                                      || ((__VALUE__) == LL_RCC_APB3_DIV_8) \
+                                      || ((__VALUE__) == LL_RCC_APB3_DIV_16))
+
+#define IS_LL_UTILS_APB4_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB4_DIV_1) \
+                                      || ((__VALUE__) == LL_RCC_APB4_DIV_2) \
+                                      || ((__VALUE__) == LL_RCC_APB4_DIV_4) \
+                                      || ((__VALUE__) == LL_RCC_APB4_DIV_8) \
+                                      || ((__VALUE__) == LL_RCC_APB4_DIV_16))
+
+#define IS_LL_UTILS_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 63U))
+
+#if (POWER_DOMAINS_NUMBER == 3U)
+#define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((4U <= (__VALUE__)) && ((__VALUE__) <= 512U))
+#else
+#define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 420U))
+#endif /*POWER_DOMAINS_NUMBER == 3U*/
+
+#define IS_LL_UTILS_PLLP_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 128U))
+
+#define IS_LL_UTILS_FRACN_VALUE(__VALUE__) ((__VALUE__) <= 0x1FFFU)
+
+#define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__, __RANGE__)  ( \
+(((__RANGE__) == LL_RCC_PLLINPUTRANGE_1_2) && (UTILS_PLLVCO_INPUT_MIN1 <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX1)) || \
+(((__RANGE__) == LL_RCC_PLLINPUTRANGE_2_4) && (UTILS_PLLVCO_INPUT_MIN2 <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX2)) || \
+(((__RANGE__) == LL_RCC_PLLINPUTRANGE_4_8) && (UTILS_PLLVCO_INPUT_MIN3 <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX3)) || \
+(((__RANGE__) == LL_RCC_PLLINPUTRANGE_8_16) && (UTILS_PLLVCO_INPUT_MIN4 <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX4)))
+
+#define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__, __RANGE__) ( \
+(((__RANGE__) == LL_RCC_PLLVCORANGE_MEDIUM) && (UTILS_PLLVCO_MEDIUM_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_MEDIUM_OUTPUT_MAX)) || \
+(((__RANGE__) == LL_RCC_PLLVCORANGE_WIDE) && (UTILS_PLLVCO_WIDE_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_WIDE_OUTPUT_MAX)))
+
+#define IS_LL_UTILS_CHECK_VCO_RANGES(__RANGEIN__, __RANGEOUT__) ( \
+(((__RANGEIN__) == LL_RCC_PLLINPUTRANGE_1_2) && ((__RANGEOUT__) == LL_RCC_PLLVCORANGE_MEDIUM)) || \
+(((__RANGEIN__) != LL_RCC_PLLINPUTRANGE_1_2) && ((__RANGEOUT__) == LL_RCC_PLLVCORANGE_WIDE)))
+
+#if (POWER_DOMAINS_NUMBER == 3U)
+#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
+                                              (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \
+                                              ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))
+#else
+#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE0) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE0) : \
+                                              (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
+                                              (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \
+                                              ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))
+#endif /*POWER_DOMAINS_NUMBER == 3U*/
+
+#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
+                                        || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
+
+#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
+/**
+  * @}
+  */
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Functions UTILS Private functions
+  * @{
+  */
+static uint32_t    UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
+static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+static ErrorStatus UTILS_IsPLLsReady(void);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UTILS_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup UTILS_LL_EF_DELAY
+  * @{
+  */
+#if defined (DUAL_CORE)
+/**
+  * @brief  This function configures the Cortex-M SysTick source to have 1ms time base.
+  * @note   When a RTOS is used, it is recommended to avoid changing the Systick
+  *         configuration by calling this function, for a delay use rather osDelay RTOS service.
+  * @param  CPU_Frequency Core frequency in Hz
+  * @note   CPU_Frequency can be calculated thanks to RCC helper macro or function
+  *         @ref LL_RCC_GetSystemClocksFreq
+  *         LL_RCC_GetSystemClocksFreq() is used to calculate the CM7 clock frequency
+  *         and __LL_RCC_CALC_HCLK_FREQ is used to caluclate the CM4 clock frequency.
+  * @retval None
+  */
+#else
+/**
+  * @brief  This function configures the Cortex-M SysTick source to have 1ms time base.
+  * @note   When a RTOS is used, it is recommended to avoid changing the Systick
+  *         configuration by calling this function, for a delay use rather osDelay RTOS service.
+  * @param  CPU_Frequency Core frequency in Hz
+  * @note   CPU_Frequency can be calculated thanks to RCC helper macro or function
+  *         @ref LL_RCC_GetSystemClocksFreq
+  * @retval None
+  */
+#endif /* DUAL_CORE */
+void LL_Init1msTick(uint32_t CPU_Frequency)
+{
+  /* Use frequency provided in argument */
+  LL_InitTick(CPU_Frequency, 1000U);
+}
+
+
+/**
+  * @brief  This function provides accurate delay (in milliseconds) based
+  *         on SysTick counter flag
+  * @note   When a RTOS is used, it is recommended to avoid using blocking delay
+  *         and use rather osDelay service.
+  * @note   To respect 1ms timebase, user should call @ref LL_Init1msTick function which
+  *         will configure Systick to 1ms
+  * @param  Delay specifies the delay time length, in milliseconds.
+  * @retval None
+  */
+void LL_mDelay(uint32_t Delay)
+{
+  uint32_t count = Delay;
+  __IO uint32_t  tmp = SysTick->CTRL;  /* Clear the COUNTFLAG first */
+  /* Add this code to indicate that local variable is not used */
+  ((void)tmp);
+
+  /* Add a period to guaranty minimum wait */
+  if(count < LL_MAX_DELAY)
+  {
+    count++;
+  }
+
+  while (count != 0U)
+  {
+    if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
+    {
+      count--;
+    }
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup UTILS_EF_SYSTEM
+  *  @brief    System Configuration functions
+  *
+  @verbatim
+ ===============================================================================
+           ##### System Configuration functions #####
+ ===============================================================================
+    [..]
+         System, AHB and APB buses clocks configuration
+
+#if (POWER_DOMAINS_NUMBER == 3U)
+         (+) The maximum frequency of the SYSCLK is 400 MHz and HCLK is 200 MHz.
+         (+) The maximum frequency of the PCLK1, PCLK2, PCLK3 and PCLK4 is 100 MHz.
+  @endverbatim
+  @internal
+             Depending on the device voltage range, the maximum frequency should be
+             adapted accordingly:
+             (++) +----------------------------------------------------------------------------+
+             (++) |  Wait states   |                           HCLK clock frequency (MHz)      |
+             (++) |                |-----------------------------------------------------------|
+             (++) |  (Latency)     |   voltage range 1 |   voltage range 2 |   voltage range 3 |
+             (++) |                |    1.15V - 1.26V  |    1.05V - 1.15V  |    0.95V - 1.05V  |
+             (++) |----------------|-------------------|-------------------|-------------------|
+             (++) |0WS(1CPU cycle) |   0 < HCLK <= 70  |   0 < HCLK <= 55  |   0 < HCLK <= 45  |
+             (++) |----------------|-------------------|-------------------|-------------------|
+             (++) |1WS(2CPU cycle) |  70 < HCLK <= 140 |  55 < HCLK <= 110 |  45 < HCLK <= 90  |
+             (++) |----------------|-------------------|-------------------|-------------------|
+             (++) |2WS(3CPU cycle) | 140 < HCLK <= 210 | 110 < HCLK <= 165 |  90 < HCLK <= 135 |
+             (++) |----------------|-------------------|-------------------|-------------------|
+             (++) |3WS(4CPU cycle) |        --         | 165 < HCLK <= 220 | 135 < HCLK <= 180 |
+             (++) |----------------|-------------------|-------------------|-------------------|
+             (++) |4WS(5CPU cycle) |        --         |        --         | 180 < HCLK <= 225 |
+             (++) +----------------------------------------------------------------------------+
+
+#else
+         (+) The maximum frequency of the SYSCLK is 280 MHz and HCLK is 280 MHz.
+         (+) The maximum frequency of the PCLK1, PCLK2, PCLK3 and PCLK4 is 140 MHz.
+  @endverbatim
+  @internal
+             Depending on the device voltage range, the maximum frequency should be
+             adapted accordingly:
+             (++) +------------------------------------------------------------------------------------------------+
+             (++) |  Wait states   |                          HCLK clock frequency (MHz)                           |
+             (++) |                |-------------------------------------------------------------------------------|
+             (++) |  (Latency)     |   voltage range 0 |   voltage range 1 |   voltage range 2 |   voltage range 3 |
+             (++) |                |    1.26V - 1.35V  |    1.15V - 1.26V  |    1.05V - 1.15V  |    0.95V - 1.05V  |
+             (++) |----------------|-------------------|-------------------|-------------------|-------------------|
+             (++) |0WS(1CPU cycle) |   0 < HCLK <= 44  |   0 < HCLK <= 42  |   0 < HCLK <= 34  |   0 < HCLK <= 22  |
+             (++) |----------------|-------------------|-------------------|-------------------|-------------------|
+             (++) |1WS(2CPU cycle) |  44 < HCLK <= 88  |  42 < HCLK <= 84  |  34 < HCLK <= 68  |  22 < HCLK <= 44  |
+             (++) |----------------|-------------------|-------------------|-------------------|-------------------|
+             (++) |2WS(3CPU cycle) |  88 < HCLK <= 132 |  84 < HCLK <= 126 |  68 < HCLK <= 102 |  44 < HCLK <= 66  |
+             (++) |----------------|-------------------|-------------------|-------------------|-------------------|
+             (++) |3WS(4CPU cycle) | 132 < HCLK <= 176 | 126 < HCLK <= 168 | 102 < HCLK <= 136 |  66 < HCLK <= 88  |
+             (++) |----------------|-------------------|-------------------|-------------------|-------------------|
+             (++) |4WS(5CPU cycle) | 176 < HCLK <= 220 | 168 < HCLK <= 210 | 136 < HCLK <= 160 |        --         |
+             (++) +------------------------------------------------------------------------------------------------+
+             (++) |5WS(6CPU cycle) | 220 < HCLK <= 264 | 210 < HCLK <= 225 |        --         |        --         |
+             (++) +------------------------------------------------------------------------------------------------+
+             (++) |6WS(7CPU cycle) | 264 < HCLK <= 280 |        --         |        --         |        --         |
+             (++) +------------------------------------------------------------------------------------------------+
+             (++) |7WS(8CPU cycle) |        --         |        --         |        --         |        --         |
+             (++) +------------------------------------------------------------------------------------------------+
+
+#endif
+  @endinternal
+  * @{
+  */
+#if defined (DUAL_CORE)
+/**
+  * @brief  This function sets directly SystemCoreClock CMSIS variable.
+  * @note   Variable can be calculated also through SystemCoreClockUpdate function.
+  * @param  CPU_Frequency Core frequency in Hz
+  * @note   CPU_Frequency can be calculated thanks to RCC helper macro or function
+  *         @ref LL_RCC_GetSystemClocksFreq
+  *         LL_RCC_GetSystemClocksFreq() is used to calculate the CM7 clock frequency
+  *         and __LL_RCC_CALC_HCLK_FREQ is used to caluclate the CM4 clock frequency.
+  * @retval None
+  */
+#else
+/**
+  * @brief  This function sets directly SystemCoreClock CMSIS variable.
+  * @note   Variable can be calculated also through SystemCoreClockUpdate function.
+  * @param  CPU_Frequency Core frequency in Hz
+  * @note   CPU_Frequency can be calculated thanks to RCC helper macro or function
+  *         @ref LL_RCC_GetSystemClocksFreq
+  * @retval None
+  */
+#endif /* DUAL_CORE */
+void LL_SetSystemCoreClock(uint32_t CPU_Frequency)
+{
+  /* HCLK clock frequency */
+  SystemCoreClock = CPU_Frequency;
+}
+
+/**
+  * @brief  This function configures system clock at maximum frequency with HSI as clock source of the PLL
+  * @note   The application need to ensure that PLL is disabled.
+  * @note   Function is based on the following formula:
+  *         - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP)
+  *         - PLLM: ensure that the VCO input frequency ranges from 1 to 16 MHz (PLLVCO_input = HSI frequency / PLLM)
+  *         - PLLN: ensure that the VCO output frequency is between 150 and 836 MHz or 128 to 560 MHz(*) (PLLVCO_output = PLLVCO_input * PLLN)
+  *         - PLLP: ensure that max frequency at 400000000 Hz or 280000000 Hz is reach (PLLVCO_output / PLLP)
+  * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+  *                             the configuration information for the PLL.
+  * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+  *                             the configuration information for the BUS prescalers.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: Max frequency configuration done
+  *          - ERROR: Max frequency configuration not done
+  *
+  * (*) : For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines.
+  *
+  */
+ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
+                                         LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
+{
+  ErrorStatus status;
+#ifdef  USE_FULL_ASSERT
+  uint32_t vcoinput_freq, vcooutput_freq;
+#endif
+  uint32_t pllfreq, hsi_clk;
+
+  /* Check the parameters */
+  assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
+  assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
+  assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
+  assert_param(IS_LL_UTILS_FRACN_VALUE(UTILS_PLLInitStruct->FRACN));
+
+  hsi_clk = (HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos));
+
+  /* Check VCO Input frequency */
+#ifdef  USE_FULL_ASSERT
+  vcoinput_freq = hsi_clk / UTILS_PLLInitStruct->PLLM;
+#endif
+  assert_param(IS_LL_UTILS_PLLVCO_INPUT(vcoinput_freq, UTILS_PLLInitStruct->VCO_Input));
+
+  /* Check VCO Output frequency */
+#ifdef  USE_FULL_ASSERT
+  vcooutput_freq = LL_RCC_CalcPLLClockFreq(hsi_clk, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->FRACN, 1UL);
+#endif
+  assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(vcooutput_freq, UTILS_PLLInitStruct->VCO_Output));
+
+  /* Check VCO Input ranges */
+  assert_param(IS_LL_UTILS_CHECK_VCO_RANGES(UTILS_PLLInitStruct->VCO_Input, UTILS_PLLInitStruct->VCO_Output));
+
+  /* Check if one of the PLL is enabled */
+  if(UTILS_IsPLLsReady() == SUCCESS)
+  {
+    /* Calculate the new PLL output frequency */
+    pllfreq = UTILS_GetPLLOutputFrequency(hsi_clk, UTILS_PLLInitStruct);
+
+    /* Enable HSI if not enabled */
+    if(LL_RCC_HSI_IsReady() != 1U)
+    {
+      LL_RCC_HSI_Enable();
+      while (LL_RCC_HSI_IsReady() != 1U)
+      {
+        /* Wait for HSI ready */
+      }
+    }
+
+    /* Configure PLL */
+    LL_RCC_PLL1P_Enable();
+    LL_RCC_PLL1FRACN_Enable();
+    LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_HSI);
+    LL_RCC_PLL1_SetVCOInputRange(UTILS_PLLInitStruct->VCO_Input);
+    LL_RCC_PLL1_SetVCOOutputRange(UTILS_PLLInitStruct->VCO_Output);
+    LL_RCC_PLL1_SetM(UTILS_PLLInitStruct->PLLM);
+    LL_RCC_PLL1_SetN(UTILS_PLLInitStruct->PLLN);
+    LL_RCC_PLL1_SetP(UTILS_PLLInitStruct->PLLP);
+    LL_RCC_PLL1_SetFRACN(UTILS_PLLInitStruct->FRACN);
+
+    /* Enable PLL and switch system clock to PLL */
+    status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
+  }
+  else
+  {
+    /* Current PLL configuration cannot be modified */
+    status = ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  This function configures system clock with HSE as clock source of the PLL
+  * @note   The application need to ensure that PLL is disabled.
+  * @note   Function is based on the following formula:
+  *         - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLP)
+  *         - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.10 MHz (PLLVCO_input = HSE frequency / PLLM)
+  *         - PLLN: ensure that the VCO output frequency is between 150 and 836 MHz or 128 to 560 MHz(*) (PLLVCO_output = PLLVCO_input * PLLN)
+  *         - PLLP: ensure that max frequency at 400000000 Hz or 280000000 Hz(*) is reached (PLLVCO_output / PLLP)
+  * @param  HSEFrequency Value between Min_Data = 4000000 and Max_Data = 48000000
+  * @param  HSEBypass This parameter can be one of the following values:
+  *         @arg @ref LL_UTILS_HSEBYPASS_ON
+  *         @arg @ref LL_UTILS_HSEBYPASS_OFF
+  * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+  *                             the configuration information for the PLL.
+  * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+  *                             the configuration information for the BUS prescalers.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: Max frequency configuration done
+  *          - ERROR: Max frequency configuration not done
+  *
+  * (*) : For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines.
+  *
+  */
+ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
+                                         LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
+{
+  ErrorStatus status;
+#ifdef  USE_FULL_ASSERT
+  uint32_t vcoinput_freq, vcooutput_freq;
+#endif
+  uint32_t pllfreq;
+
+  /* Check the parameters */
+  assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
+  assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
+  assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
+  assert_param(IS_LL_UTILS_FRACN_VALUE(UTILS_PLLInitStruct->FRACN));
+  assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
+  assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
+
+  /* Check VCO Input frequency */
+#ifdef  USE_FULL_ASSERT
+  vcoinput_freq = HSEFrequency / UTILS_PLLInitStruct->PLLM;
+#endif
+  assert_param(IS_LL_UTILS_PLLVCO_INPUT(vcoinput_freq, UTILS_PLLInitStruct->VCO_Input));
+
+  /* Check VCO output frequency */
+#ifdef  USE_FULL_ASSERT
+  vcooutput_freq = LL_RCC_CalcPLLClockFreq(HSEFrequency, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->FRACN, 1U);
+#endif
+  assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(vcooutput_freq, UTILS_PLLInitStruct->VCO_Output));
+
+  /* Check VCO Input/output ranges compatibility */
+  assert_param(IS_LL_UTILS_CHECK_VCO_RANGES(UTILS_PLLInitStruct->VCO_Input, UTILS_PLLInitStruct->VCO_Output));
+
+  /* Check if one of the PLL is enabled */
+  if(UTILS_IsPLLsReady() == SUCCESS)
+  {
+    /* Calculate the new PLL output frequency */
+    pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
+
+    /* Enable HSE if not enabled */
+    if(LL_RCC_HSE_IsReady() != 1U)
+    {
+      /* Check if need to enable HSE bypass feature or not */
+      if(HSEBypass == LL_UTILS_HSEBYPASS_ON)
+      {
+        LL_RCC_HSE_EnableBypass();
+      }
+      else
+      {
+        LL_RCC_HSE_DisableBypass();
+      }
+
+      /* Enable HSE */
+      LL_RCC_HSE_Enable();
+      while (LL_RCC_HSE_IsReady() != 1U)
+      {
+        /* Wait for HSE ready */
+      }
+    }
+
+    /* Configure PLL */
+    LL_RCC_PLL1P_Enable();
+    LL_RCC_PLL1FRACN_Enable();
+    LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_HSE);
+    LL_RCC_PLL1_SetVCOInputRange(UTILS_PLLInitStruct->VCO_Input);
+    LL_RCC_PLL1_SetVCOOutputRange(UTILS_PLLInitStruct->VCO_Output);
+    LL_RCC_PLL1_SetM(UTILS_PLLInitStruct->PLLM);
+    LL_RCC_PLL1_SetN(UTILS_PLLInitStruct->PLLN);
+    LL_RCC_PLL1_SetP(UTILS_PLLInitStruct->PLLP);
+    LL_RCC_PLL1_SetFRACN(UTILS_PLLInitStruct->FRACN);
+
+    /* Enable PLL and switch system clock to PLL */
+    status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
+  }
+  else
+  {
+    /* Current PLL configuration cannot be modified */
+    status = ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Update number of Flash wait states in line with new frequency and current
+            voltage range.
+  * @param  HCLK_Frequency  HCLK frequency
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: Latency has been modified
+  *          - ERROR: Latency cannot be modified
+  */
+ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency)
+{
+  ErrorStatus status = SUCCESS;
+  uint32_t timeout;
+  uint32_t getlatency;
+  uint32_t latency = LL_FLASH_LATENCY_0;  /* default value 0WS */
+
+
+
+  /* Frequency cannot be equal to 0 */
+  if (HCLK_Frequency == 0U)
+  {
+    status = ERROR;
+  }
+  else
+  {
+#if (POWER_DOMAINS_NUMBER == 2U)
+    if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE0)
+    {
+      if((HCLK_Frequency > UTILS_SCALE0_LATENCY5_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY6_FREQ))
+      {
+        /* 264 < HCLK <= 280 => 6WS (7 CPU cycles) */
+        latency = LL_FLASH_LATENCY_6;
+      }
+      else if((HCLK_Frequency > UTILS_SCALE0_LATENCY4_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY5_FREQ))
+      {
+        /* 220 < HCLK <= 264 => 5WS (6 CPU cycles) */
+        latency = LL_FLASH_LATENCY_5;
+      }
+      else if((HCLK_Frequency > UTILS_SCALE0_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY4_FREQ))
+      {
+        /* 176 < HCLK <= 220 => 4WS (5 CPU cycles) */
+        latency = LL_FLASH_LATENCY_4;
+      }
+      else if((HCLK_Frequency > UTILS_SCALE0_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY3_FREQ))
+      {
+        /* 132 < HCLK <= 176 => 3WS (4 CPU cycles) */
+        latency = LL_FLASH_LATENCY_3;
+      }
+      else if((HCLK_Frequency > UTILS_SCALE0_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY2_FREQ))
+      {
+        /* 88 < HCLK <= 132 => 2WS (3 CPU cycles) */
+        latency = LL_FLASH_LATENCY_2;
+      }
+      else if((HCLK_Frequency > UTILS_SCALE0_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY1_FREQ))
+      {
+        /* 44 < HCLK <= 88 => 1WS (2 CPU cycles) */
+        latency = LL_FLASH_LATENCY_1;
+      }
+      else if(HCLK_Frequency <= UTILS_SCALE0_LATENCY0_FREQ)
+      {
+        /* HCLK <= 44 => 0WS (1 CPU cycles) : Do nothing keep latency to default  LL_FLASH_LATENCY_0 */
+      }
+      else
+      {
+        status = ERROR;
+      }
+    }
+    else if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
+    {
+      if((HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY5_FREQ))
+      {
+        /* 210 < HCLK <= 225 => 5WS (6 CPU cycles) */
+        latency = LL_FLASH_LATENCY_5;
+      }
+      else if((HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY4_FREQ))
+      {
+        /* 168 < HCLK <= 210 => 4WS (5 CPU cycles) */
+        latency = LL_FLASH_LATENCY_4;
+      }
+      else if((HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY3_FREQ))
+      {
+        /* 126 < HCLK <= 168 => 3WS (4 CPU cycles) */
+        latency = LL_FLASH_LATENCY_3;
+      }
+      else if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY2_FREQ))
+#else
+    if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
+    {
+      if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY2_FREQ))
+#endif /*POWER_DOMAINS_NUMBER == 2U*/
+      {
+        /* 140 < HCLK <= 210 => 2WS (3 CPU cycles) */
+        latency = LL_FLASH_LATENCY_2;
+      }
+      else if((HCLK_Frequency > UTILS_SCALE1_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY1_FREQ))
+      {
+        /* 70 < HCLK <= 140 => 1WS (2 CPU cycles) */
+        latency = LL_FLASH_LATENCY_1;
+      }
+      else if(HCLK_Frequency <= UTILS_SCALE1_LATENCY0_FREQ)
+      {
+        /* HCLK <= 70 => 0WS (1 CPU cycles) : Do nothing keep latency to default  LL_FLASH_LATENCY_0 */
+      }
+      else
+      {
+        status = ERROR;
+      }
+    }
+    else if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2)
+    {
+#if (POWER_DOMAINS_NUMBER == 2U)
+      if((HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY4_FREQ))
+      {
+        /* 136 < HCLK <= 160 => 4WS (5 CPU cycles) */
+        latency = LL_FLASH_LATENCY_4;
+      }
+      else if((HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY3_FREQ))
+#else
+      if((HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY3_FREQ))
+#endif /*POWER_DOMAINS_NUMBER == 2U*/
+      {
+        /* 165 < HCLK <= 220 => 3WS (4 CPU cycles) */
+        latency = LL_FLASH_LATENCY_3;
+      }
+      else if((HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY2_FREQ))
+      {
+        /* 110 < HCLK <= 165 => 2WS (3 CPU cycles) */
+        latency = LL_FLASH_LATENCY_2;
+      }
+      else if((HCLK_Frequency > UTILS_SCALE2_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY1_FREQ))
+      {
+        /* 55 < HCLK <= 110 => 1WS (2 CPU cycles) */
+        latency = LL_FLASH_LATENCY_1;
+      }
+      else if(HCLK_Frequency <= UTILS_SCALE2_LATENCY0_FREQ)
+      {
+        /* HCLK <= 55 => 0WS (1 CPU cycles) : Do nothing keep latency to default  LL_FLASH_LATENCY_0 */
+      }
+      else
+      {
+        status = ERROR;
+      }
+    }
+    else /* Scale 3 */
+    {
+#if (POWER_DOMAINS_NUMBER == 3U)
+      if((HCLK_Frequency > UTILS_SCALE3_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY4_FREQ))
+      {
+        /* 180 < HCLK <= 225 => 4WS (5 CPU cycles) */
+        latency = LL_FLASH_LATENCY_4;
+      }
+      else if((HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY3_FREQ))
+#else
+      if((HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY3_FREQ))
+#endif /*POWER_DOMAINS_NUMBER == 3U*/
+      {
+        /* 135 < HCLK <= 180 => 3WS (4 CPU cycles) */
+        latency = LL_FLASH_LATENCY_3;
+      }
+      else if((HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY2_FREQ))
+      {
+        /* 90 < HCLK <= 135 => 2WS (3 CPU cycles) */
+        latency = LL_FLASH_LATENCY_2;
+      }
+      else if((HCLK_Frequency > UTILS_SCALE3_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY1_FREQ))
+      {
+        /* 45 < HCLK <= 90 => 1WS (2 CPU cycles) */
+        latency = LL_FLASH_LATENCY_1;
+      }
+      else if(HCLK_Frequency <= UTILS_SCALE3_LATENCY0_FREQ)
+      {
+        /* HCLK <= 45 => 0WS (1 CPU cycles) : Do nothing keep latency to default  LL_FLASH_LATENCY_0 */
+      }
+      else
+      {
+        status = ERROR;
+      }
+    }
+
+    if(status == SUCCESS)
+    {
+      LL_FLASH_SetLatency(latency);
+
+      /* Check that the new number of wait states is taken into account to access the Flash
+      memory by reading the FLASH_ACR register */
+      timeout = 2;
+      do
+      {
+        /* Wait for Flash latency to be updated */
+        getlatency = LL_FLASH_GetLatency();
+        timeout--;
+      } while ((getlatency != latency) && (timeout > 0U));
+
+      if(getlatency != latency)
+      {
+        status = ERROR;
+      }
+    }
+
+  }
+
+  return status;
+}
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup UTILS_LL_Private_Functions
+  * @{
+  */
+
+
+/**
+  * @brief  Function to check that PLL can be modified
+  * @param  PLL_InputFrequency  PLL input frequency (in Hz)
+  * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+  *                             the configuration information for the PLL.
+  * @retval PLL output frequency (in Hz)
+  */
+static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
+{
+  uint32_t pllfreq;
+
+  /* Check the parameters */
+  assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
+  assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
+  assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
+  assert_param(IS_LL_UTILS_FRACN_VALUE(UTILS_PLLInitStruct->FRACN));
+
+  pllfreq = LL_RCC_CalcPLLClockFreq(PLL_InputFrequency, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->FRACN, UTILS_PLLInitStruct->PLLP);
+
+  return pllfreq;
+}
+
+/**
+  * @brief  Check that all PLLs are ready therefore configuration can be done
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: All PLLs are ready so configuration can be done
+  *          - ERROR: One PLL at least is busy
+  */
+static ErrorStatus UTILS_IsPLLsReady(void)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check if one of the PLL1 is busy */
+  if(LL_RCC_PLL1_IsReady() != 0U)
+  {
+    /* PLL1 configuration cannot be done */
+    status = ERROR;
+  }
+
+  /* Check if one of the PLL2 is busy */
+  if(LL_RCC_PLL2_IsReady() != 0U)
+  {
+    /* PLL2 configuration cannot be done */
+    status = ERROR;
+  }
+
+  /* Check if one of the PLL3 is busy */
+  if(LL_RCC_PLL3_IsReady() != 0U)
+  {
+    /* PLL3 configuration cannot be done */
+    status = ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Function to enable PLL and switch system clock to PLL
+  * @param  SYSCLK_Frequency SYSCLK frequency
+  * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+  *                             the configuration information for the BUS prescalers.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: No problem to switch system to PLL
+  *          - ERROR: Problem to switch system to PLL
+  */
+static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
+{
+  ErrorStatus status = SUCCESS;
+  uint32_t new_hclk_frequency;
+
+  assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->SYSCLKDivider));
+  assert_param(IS_LL_UTILS_AHB_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
+  assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
+  assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
+  assert_param(IS_LL_UTILS_APB3_DIV(UTILS_ClkInitStruct->APB3CLKDivider));
+  assert_param(IS_LL_UTILS_APB4_DIV(UTILS_ClkInitStruct->APB4CLKDivider));
+
+  /* Calculate the new HCLK frequency */
+  new_hclk_frequency = LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
+
+  /* Increasing the number of wait states because of higher CPU frequency */
+  if (SystemD2Clock < new_hclk_frequency)
+  {
+    /* Set FLASH latency to highest latency */
+    status = LL_SetFlashLatency(new_hclk_frequency);
+  }
+
+  /* Update system clock configuration */
+  if(status == SUCCESS)
+  {
+    /* Enable PLL */
+    LL_RCC_PLL1_Enable();
+    while (LL_RCC_PLL1_IsReady() != 1U)
+    {
+      /* Wait for PLL ready */
+    }
+
+    /* Set All APBxPrescaler to the Highest Divider */
+    LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_16);
+    LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_16);
+    LL_RCC_SetAPB3Prescaler(LL_RCC_APB3_DIV_16);
+    LL_RCC_SetAPB4Prescaler(LL_RCC_APB4_DIV_16);
+
+    /* Set SYS prescaler*/
+    LL_RCC_SetSysPrescaler(UTILS_ClkInitStruct->SYSCLKDivider);
+
+    /* Set AHB prescaler*/
+    LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
+
+    /* Sysclk activation on the main PLL */
+    LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL1);
+    while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL1)
+    {
+      /* Wait for system clock switch to PLL */
+    }
+
+    /* Set APBn prescaler*/
+    LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
+    LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
+    LL_RCC_SetAPB3Prescaler(UTILS_ClkInitStruct->APB3CLKDivider);
+    LL_RCC_SetAPB4Prescaler(UTILS_ClkInitStruct->APB4CLKDivider);
+
+    /* Decreasing the number of wait states because of lower CPU frequency */
+    if (SystemD2Clock > new_hclk_frequency)
+    {
+      /* Set FLASH latency to lowest latency */
+      status = LL_SetFlashLatency(new_hclk_frequency);
+    }
+
+    /* Update the SystemD2Clock global variable */
+#if defined(RCC_D1CFGR_HPRE)
+    SystemD2Clock = (SYSCLK_Frequency >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+#else
+    SystemD2Clock = (SYSCLK_Frequency >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+#endif
+
+    /* Update SystemCoreClock variable */
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+    LL_SetSystemCoreClock(SystemD2Clock);
+#else
+    LL_SetSystemCoreClock(SYSCLK_Frequency);
+#endif /* DUAL_CORE && CORE_CM4 */
+
+  }
+
+
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32_USB_Device_Library/Core/Inc/usbd_core.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32_USB_Device_Library/Core/Inc/usbd_core.h
new file mode 100644
index 00000000..030927b3
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32_USB_Device_Library/Core/Inc/usbd_core.h
@@ -0,0 +1,161 @@
+/**
+  ******************************************************************************
+  * @file    usbd_core.h
+  * @author  MCD Application Team
+  * @brief   Header file for usbd_core.c file
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USBD_CORE_H
+#define __USBD_CORE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbd_conf.h"
+#include "usbd_def.h"
+#include "usbd_ioreq.h"
+#include "usbd_ctlreq.h"
+
+/** @addtogroup STM32_USB_DEVICE_LIBRARY
+  * @{
+  */
+
+/** @defgroup USBD_CORE
+  * @brief This file is the Header file for usbd_core.c file
+  * @{
+  */
+
+
+/** @defgroup USBD_CORE_Exported_Defines
+  * @{
+  */
+#ifndef USBD_DEBUG_LEVEL
+#define USBD_DEBUG_LEVEL           0U
+#endif /* USBD_DEBUG_LEVEL */
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_CORE_Exported_TypesDefinitions
+  * @{
+  */
+
+
+/**
+  * @}
+  */
+
+
+
+/** @defgroup USBD_CORE_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_CORE_Exported_Variables
+  * @{
+  */
+#define USBD_SOF          USBD_LL_SOF
+/**
+  * @}
+  */
+
+/** @defgroup USBD_CORE_Exported_FunctionsPrototype
+  * @{
+  */
+USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id);
+USBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev);
+USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev);
+USBD_StatusTypeDef USBD_Stop(USBD_HandleTypeDef *pdev);
+USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass);
+
+USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef  *pdev);
+USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef  *pdev, uint8_t cfgidx);
+USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef  *pdev, uint8_t cfgidx);
+
+USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup);
+USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata);
+USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata);
+
+USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef  *pdev);
+USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef  *pdev, USBD_SpeedTypeDef speed);
+USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef  *pdev);
+USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef  *pdev);
+
+USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef  *pdev);
+USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef  *pdev, uint8_t epnum);
+USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef  *pdev, uint8_t epnum);
+
+USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef  *pdev);
+USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef  *pdev);
+
+/* USBD Low Level Driver */
+USBD_StatusTypeDef  USBD_LL_Init(USBD_HandleTypeDef *pdev);
+USBD_StatusTypeDef  USBD_LL_DeInit(USBD_HandleTypeDef *pdev);
+USBD_StatusTypeDef  USBD_LL_Start(USBD_HandleTypeDef *pdev);
+USBD_StatusTypeDef  USBD_LL_Stop(USBD_HandleTypeDef *pdev);
+USBD_StatusTypeDef  USBD_LL_OpenEP(USBD_HandleTypeDef *pdev,
+                                   uint8_t  ep_addr,
+                                   uint8_t  ep_type,
+                                   uint16_t ep_mps);
+
+USBD_StatusTypeDef  USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
+USBD_StatusTypeDef  USBD_LL_FlushEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
+USBD_StatusTypeDef  USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
+USBD_StatusTypeDef  USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
+uint8_t             USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
+USBD_StatusTypeDef  USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr);
+USBD_StatusTypeDef  USBD_LL_Transmit(USBD_HandleTypeDef *pdev,
+                                     uint8_t  ep_addr,
+                                     uint8_t  *pbuf,
+                                     uint16_t  size);
+
+USBD_StatusTypeDef  USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev,
+                                           uint8_t  ep_addr,
+                                           uint8_t  *pbuf,
+                                           uint16_t  size);
+
+uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t  ep_addr);
+void  USBD_LL_Delay(uint32_t Delay);
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USBD_CORE_H */
+
+/**
+  * @}
+  */
+
+/**
+* @}
+*/
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
+
+
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h
new file mode 100644
index 00000000..25a47582
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h
@@ -0,0 +1,105 @@
+/**
+  ******************************************************************************
+  * @file    usbd_req.h
+  * @author  MCD Application Team
+  * @brief   Header file for the usbd_req.c file
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_REQUEST_H
+#define __USB_REQUEST_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include  "usbd_def.h"
+
+
+/** @addtogroup STM32_USB_DEVICE_LIBRARY
+  * @{
+  */
+
+/** @defgroup USBD_REQ
+  * @brief header file for the usbd_req.c file
+  * @{
+  */
+
+/** @defgroup USBD_REQ_Exported_Defines
+  * @{
+  */
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_REQ_Exported_Types
+  * @{
+  */
+/**
+  * @}
+  */
+
+
+
+/** @defgroup USBD_REQ_Exported_Macros
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup USBD_REQ_Exported_Variables
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup USBD_REQ_Exported_FunctionsPrototype
+  * @{
+  */
+
+USBD_StatusTypeDef  USBD_StdDevReq(USBD_HandleTypeDef  *pdev, USBD_SetupReqTypedef  *req);
+USBD_StatusTypeDef  USBD_StdItfReq(USBD_HandleTypeDef  *pdev, USBD_SetupReqTypedef  *req);
+USBD_StatusTypeDef  USBD_StdEPReq(USBD_HandleTypeDef  *pdev, USBD_SetupReqTypedef  *req);
+
+
+void USBD_CtlError(USBD_HandleTypeDef  *pdev, USBD_SetupReqTypedef *req);
+
+void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata);
+
+void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len);
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USB_REQUEST_H */
+
+/**
+  * @}
+  */
+
+/**
+* @}
+*/
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32_USB_Device_Library/Core/Inc/usbd_def.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32_USB_Device_Library/Core/Inc/usbd_def.h
new file mode 100644
index 00000000..8d7502f3
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32_USB_Device_Library/Core/Inc/usbd_def.h
@@ -0,0 +1,348 @@
+/**
+  ******************************************************************************
+  * @file    usbd_def.h
+  * @author  MCD Application Team
+  * @brief   General defines for the usb device library
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USBD_DEF_H
+#define __USBD_DEF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbd_conf.h"
+
+/** @addtogroup STM32_USBD_DEVICE_LIBRARY
+  * @{
+  */
+
+/** @defgroup USB_DEF
+  * @brief general defines for the usb device library file
+  * @{
+  */
+
+/** @defgroup USB_DEF_Exported_Defines
+  * @{
+  */
+
+#ifndef NULL
+#define NULL                                            0U
+#endif /* NULL */
+
+#ifndef USBD_MAX_NUM_INTERFACES
+#define USBD_MAX_NUM_INTERFACES                         1U
+#endif /* USBD_MAX_NUM_CONFIGURATION */
+
+#ifndef USBD_MAX_NUM_CONFIGURATION
+#define USBD_MAX_NUM_CONFIGURATION                      1U
+#endif /* USBD_MAX_NUM_CONFIGURATION */
+
+#ifndef USBD_LPM_ENABLED
+#define USBD_LPM_ENABLED                                0U
+#endif /* USBD_LPM_ENABLED */
+
+#ifndef USBD_SELF_POWERED
+#define USBD_SELF_POWERED                               1U
+#endif /*USBD_SELF_POWERED */
+
+#ifndef USBD_SUPPORT_USER_STRING_DESC
+#define USBD_SUPPORT_USER_STRING_DESC                   0U
+#endif /* USBD_SUPPORT_USER_STRING_DESC */
+
+#define  USB_LEN_DEV_QUALIFIER_DESC                     0x0AU
+#define  USB_LEN_DEV_DESC                               0x12U
+#define  USB_LEN_CFG_DESC                               0x09U
+#define  USB_LEN_IF_DESC                                0x09U
+#define  USB_LEN_EP_DESC                                0x07U
+#define  USB_LEN_OTG_DESC                               0x03U
+#define  USB_LEN_LANGID_STR_DESC                        0x04U
+#define  USB_LEN_OTHER_SPEED_DESC_SIZ                   0x09U
+
+#define  USBD_IDX_LANGID_STR                            0x00U
+#define  USBD_IDX_MFC_STR                               0x01U
+#define  USBD_IDX_PRODUCT_STR                           0x02U
+#define  USBD_IDX_SERIAL_STR                            0x03U
+#define  USBD_IDX_CONFIG_STR                            0x04U
+#define  USBD_IDX_INTERFACE_STR                         0x05U
+
+#define  USB_REQ_TYPE_STANDARD                          0x00U
+#define  USB_REQ_TYPE_CLASS                             0x20U
+#define  USB_REQ_TYPE_VENDOR                            0x40U
+#define  USB_REQ_TYPE_MASK                              0x60U
+
+#define  USB_REQ_RECIPIENT_DEVICE                       0x00U
+#define  USB_REQ_RECIPIENT_INTERFACE                    0x01U
+#define  USB_REQ_RECIPIENT_ENDPOINT                     0x02U
+#define  USB_REQ_RECIPIENT_MASK                         0x03U
+
+#define  USB_REQ_GET_STATUS                             0x00U
+#define  USB_REQ_CLEAR_FEATURE                          0x01U
+#define  USB_REQ_SET_FEATURE                            0x03U
+#define  USB_REQ_SET_ADDRESS                            0x05U
+#define  USB_REQ_GET_DESCRIPTOR                         0x06U
+#define  USB_REQ_SET_DESCRIPTOR                         0x07U
+#define  USB_REQ_GET_CONFIGURATION                      0x08U
+#define  USB_REQ_SET_CONFIGURATION                      0x09U
+#define  USB_REQ_GET_INTERFACE                          0x0AU
+#define  USB_REQ_SET_INTERFACE                          0x0BU
+#define  USB_REQ_SYNCH_FRAME                            0x0CU
+
+#define  USB_DESC_TYPE_DEVICE                           0x01U
+#define  USB_DESC_TYPE_CONFIGURATION                    0x02U
+#define  USB_DESC_TYPE_STRING                           0x03U
+#define  USB_DESC_TYPE_INTERFACE                        0x04U
+#define  USB_DESC_TYPE_ENDPOINT                         0x05U
+#define  USB_DESC_TYPE_DEVICE_QUALIFIER                 0x06U
+#define  USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION        0x07U
+#define  USB_DESC_TYPE_BOS                              0x0FU
+
+#define USB_CONFIG_REMOTE_WAKEUP                        0x02U
+#define USB_CONFIG_SELF_POWERED                         0x01U
+
+#define USB_FEATURE_EP_HALT                             0x00U
+#define USB_FEATURE_REMOTE_WAKEUP                       0x01U
+#define USB_FEATURE_TEST_MODE                           0x02U
+
+#define USB_DEVICE_CAPABITY_TYPE                        0x10U
+
+#define USB_HS_MAX_PACKET_SIZE                          512U
+#define USB_FS_MAX_PACKET_SIZE                          64U
+#define USB_MAX_EP0_SIZE                                64U
+
+/*  Device Status */
+#define USBD_STATE_DEFAULT                              0x01U
+#define USBD_STATE_ADDRESSED                            0x02U
+#define USBD_STATE_CONFIGURED                           0x03U
+#define USBD_STATE_SUSPENDED                            0x04U
+
+
+/*  EP0 State */
+#define USBD_EP0_IDLE                                   0x00U
+#define USBD_EP0_SETUP                                  0x01U
+#define USBD_EP0_DATA_IN                                0x02U
+#define USBD_EP0_DATA_OUT                               0x03U
+#define USBD_EP0_STATUS_IN                              0x04U
+#define USBD_EP0_STATUS_OUT                             0x05U
+#define USBD_EP0_STALL                                  0x06U
+
+#define USBD_EP_TYPE_CTRL                               0x00U
+#define USBD_EP_TYPE_ISOC                               0x01U
+#define USBD_EP_TYPE_BULK                               0x02U
+#define USBD_EP_TYPE_INTR                               0x03U
+
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_DEF_Exported_TypesDefinitions
+  * @{
+  */
+
+typedef  struct  usb_setup_req
+{
+  uint8_t   bmRequest;
+  uint8_t   bRequest;
+  uint16_t  wValue;
+  uint16_t  wIndex;
+  uint16_t  wLength;
+} USBD_SetupReqTypedef;
+
+struct _USBD_HandleTypeDef;
+
+typedef struct _Device_cb
+{
+  uint8_t (*Init)(struct _USBD_HandleTypeDef *pdev, uint8_t cfgidx);
+  uint8_t (*DeInit)(struct _USBD_HandleTypeDef *pdev, uint8_t cfgidx);
+  /* Control Endpoints*/
+  uint8_t (*Setup)(struct _USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef  *req);
+  uint8_t (*EP0_TxSent)(struct _USBD_HandleTypeDef *pdev);
+  uint8_t (*EP0_RxReady)(struct _USBD_HandleTypeDef *pdev);
+  /* Class Specific Endpoints*/
+  uint8_t (*DataIn)(struct _USBD_HandleTypeDef *pdev, uint8_t epnum);
+  uint8_t (*DataOut)(struct _USBD_HandleTypeDef *pdev, uint8_t epnum);
+  uint8_t (*SOF)(struct _USBD_HandleTypeDef *pdev);
+  uint8_t (*IsoINIncomplete)(struct _USBD_HandleTypeDef *pdev, uint8_t epnum);
+  uint8_t (*IsoOUTIncomplete)(struct _USBD_HandleTypeDef *pdev, uint8_t epnum);
+
+  uint8_t  *(*GetHSConfigDescriptor)(uint16_t *length);
+  uint8_t  *(*GetFSConfigDescriptor)(uint16_t *length);
+  uint8_t  *(*GetOtherSpeedConfigDescriptor)(uint16_t *length);
+  uint8_t  *(*GetDeviceQualifierDescriptor)(uint16_t *length);
+#if (USBD_SUPPORT_USER_STRING_DESC == 1U)
+  uint8_t  *(*GetUsrStrDescriptor)(struct _USBD_HandleTypeDef *pdev, uint8_t index,  uint16_t *length);
+#endif
+
+} USBD_ClassTypeDef;
+
+/* Following USB Device Speed */
+typedef enum
+{
+  USBD_SPEED_HIGH  = 0U,
+  USBD_SPEED_FULL  = 1U,
+  USBD_SPEED_LOW   = 2U,
+} USBD_SpeedTypeDef;
+
+/* Following USB Device status */
+typedef enum
+{
+  USBD_OK   = 0U,
+  USBD_BUSY,
+  USBD_FAIL,
+} USBD_StatusTypeDef;
+
+/* USB Device descriptors structure */
+typedef struct
+{
+  uint8_t  *(*GetDeviceDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
+  uint8_t  *(*GetLangIDStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
+  uint8_t  *(*GetManufacturerStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
+  uint8_t  *(*GetProductStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
+  uint8_t  *(*GetSerialStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
+  uint8_t  *(*GetConfigurationStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
+  uint8_t  *(*GetInterfaceStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
+#if (USBD_LPM_ENABLED == 1U)
+  uint8_t  *(*GetBOSDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
+#endif
+} USBD_DescriptorsTypeDef;
+
+/* USB Device handle structure */
+typedef struct
+{
+  uint32_t                status;
+  uint32_t                is_used;
+  uint32_t                total_length;
+  uint32_t                rem_length;
+  uint32_t                maxpacket;
+} USBD_EndpointTypeDef;
+
+/* USB Device handle structure */
+typedef struct _USBD_HandleTypeDef
+{
+  uint8_t                 id;
+  uint32_t                dev_config;
+  uint32_t                dev_default_config;
+  uint32_t                dev_config_status;
+  USBD_SpeedTypeDef       dev_speed;
+  USBD_EndpointTypeDef    ep_in[16];
+  USBD_EndpointTypeDef    ep_out[16];
+  uint32_t                ep0_state;
+  uint32_t                ep0_data_len;
+  uint8_t                 dev_state;
+  uint8_t                 dev_old_state;
+  uint8_t                 dev_address;
+  uint8_t                 dev_connection_status;
+  uint8_t                 dev_test_mode;
+  uint32_t                dev_remote_wakeup;
+
+  USBD_SetupReqTypedef    request;
+  USBD_DescriptorsTypeDef *pDesc;
+  USBD_ClassTypeDef       *pClass;
+  void                    *pClassData;
+  void                    *pUserData;
+  void                    *pData;
+} USBD_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+
+
+/** @defgroup USBD_DEF_Exported_Macros
+  * @{
+  */
+#define  SWAPBYTE(addr)        (((uint16_t)(*((uint8_t *)(addr)))) + \
+                               (((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U))
+
+#define LOBYTE(x)  ((uint8_t)((x) & 0x00FFU))
+#define HIBYTE(x)  ((uint8_t)(((x) & 0xFF00U) >> 8U))
+#define MIN(a, b)  (((a) < (b)) ? (a) : (b))
+#define MAX(a, b)  (((a) > (b)) ? (a) : (b))
+
+
+#if  defined ( __GNUC__ )
+#ifndef __weak
+#define __weak   __attribute__((weak))
+#endif /* __weak */
+#ifndef __packed
+#define __packed __attribute__((__packed__))
+#endif /* __packed */
+#endif /* __GNUC__ */
+
+
+/* In HS mode and when the DMA is used, all variables and data structures dealing
+   with the DMA during the transaction process should be 4-bytes aligned */
+
+#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
+#ifndef __ALIGN_END
+#define __ALIGN_END    __attribute__ ((aligned (4U)))
+#endif /* __ALIGN_END */
+#ifndef __ALIGN_BEGIN
+#define __ALIGN_BEGIN
+#endif /* __ALIGN_BEGIN */
+#else
+#ifndef __ALIGN_END
+#define __ALIGN_END
+#endif /* __ALIGN_END */
+#ifndef __ALIGN_BEGIN
+#if defined   (__CC_ARM)      /* ARM Compiler */
+#define __ALIGN_BEGIN    __align(4U)
+#elif defined (__ICCARM__)    /* IAR Compiler */
+#define __ALIGN_BEGIN
+#endif /* __CC_ARM */
+#endif /* __ALIGN_BEGIN */
+#endif /* __GNUC__ */
+
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DEF_Exported_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DEF_Exported_FunctionsPrototype
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USBD_DEF_H */
+
+/**
+  * @}
+  */
+
+/**
+* @}
+*/
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h
new file mode 100644
index 00000000..8a6dd5f7
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h
@@ -0,0 +1,119 @@
+/**
+  ******************************************************************************
+  * @file    usbd_ioreq.h
+  * @author  MCD Application Team
+  * @brief   Header file for the usbd_ioreq.c file
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USBD_IOREQ_H
+#define __USBD_IOREQ_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include  "usbd_def.h"
+#include  "usbd_core.h"
+
+/** @addtogroup STM32_USB_DEVICE_LIBRARY
+  * @{
+  */
+
+/** @defgroup USBD_IOREQ
+  * @brief header file for the usbd_ioreq.c file
+  * @{
+  */
+
+/** @defgroup USBD_IOREQ_Exported_Defines
+  * @{
+  */
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_IOREQ_Exported_Types
+  * @{
+  */
+
+
+/**
+  * @}
+  */
+
+
+
+/** @defgroup USBD_IOREQ_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_IOREQ_Exported_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_IOREQ_Exported_FunctionsPrototype
+  * @{
+  */
+
+USBD_StatusTypeDef  USBD_CtlSendData(USBD_HandleTypeDef *pdev,
+                                     uint8_t *pbuf,
+                                     uint16_t len);
+
+USBD_StatusTypeDef  USBD_CtlContinueSendData(USBD_HandleTypeDef  *pdev,
+                                             uint8_t *pbuf,
+                                             uint16_t len);
+
+USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef  *pdev,
+                                     uint8_t *pbuf,
+                                     uint16_t len);
+
+USBD_StatusTypeDef  USBD_CtlContinueRx(USBD_HandleTypeDef  *pdev,
+                                       uint8_t *pbuf,
+                                       uint16_t len);
+
+USBD_StatusTypeDef  USBD_CtlSendStatus(USBD_HandleTypeDef  *pdev);
+
+USBD_StatusTypeDef  USBD_CtlReceiveStatus(USBD_HandleTypeDef  *pdev);
+
+uint32_t  USBD_GetRxCount(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USBD_IOREQ_H */
+
+/**
+  * @}
+  */
+
+/**
+* @}
+*/
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32_USB_Device_Library/Core/Src/usbd_core.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32_USB_Device_Library/Core/Src/usbd_core.c
new file mode 100644
index 00000000..b1a60ae2
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32_USB_Device_Library/Core/Src/usbd_core.c
@@ -0,0 +1,611 @@
+/**
+  ******************************************************************************
+  * @file    usbd_core.c
+  * @author  MCD Application Team
+  * @brief   This file provides all the USBD core functions.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbd_core.h"
+
+/** @addtogroup STM32_USBD_DEVICE_LIBRARY
+* @{
+*/
+
+
+/** @defgroup USBD_CORE
+* @brief usbd core module
+* @{
+*/
+
+/** @defgroup USBD_CORE_Private_TypesDefinitions
+* @{
+*/
+
+/**
+* @}
+*/
+
+
+/** @defgroup USBD_CORE_Private_Defines
+* @{
+*/
+
+/**
+* @}
+*/
+
+
+/** @defgroup USBD_CORE_Private_Macros
+* @{
+*/
+
+/**
+* @}
+*/
+
+
+/** @defgroup USBD_CORE_Private_FunctionPrototypes
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup USBD_CORE_Private_Variables
+* @{
+*/
+
+/**
+* @}
+*/
+
+
+/** @defgroup USBD_CORE_Private_Functions
+* @{
+*/
+
+/**
+* @brief  USBD_Init
+*         Initializes the device stack and load the class driver
+* @param  pdev: device instance
+* @param  pdesc: Descriptor structure address
+* @param  id: Low level core index
+* @retval None
+*/
+USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev,
+                             USBD_DescriptorsTypeDef *pdesc, uint8_t id)
+{
+  /* Check whether the USB Host handle is valid */
+  if (pdev == NULL)
+  {
+#if (USBD_DEBUG_LEVEL > 1U)
+    USBD_ErrLog("Invalid Device handle");
+#endif
+    return USBD_FAIL;
+  }
+
+  /* Unlink previous class*/
+  if (pdev->pClass != NULL)
+  {
+    pdev->pClass = NULL;
+  }
+
+  /* Assign USBD Descriptors */
+  if (pdesc != NULL)
+  {
+    pdev->pDesc = pdesc;
+  }
+
+  /* Set Device initial State */
+  pdev->dev_state = USBD_STATE_DEFAULT;
+  pdev->id = id;
+  /* Initialize low level driver */
+  USBD_LL_Init(pdev);
+
+  return USBD_OK;
+}
+
+/**
+* @brief  USBD_DeInit
+*         Re-Initialize th device library
+* @param  pdev: device instance
+* @retval status: status
+*/
+USBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev)
+{
+  /* Set Default State */
+  pdev->dev_state = USBD_STATE_DEFAULT;
+
+  /* Free Class Resources */
+  pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config);
+
+  /* Stop the low level driver  */
+  USBD_LL_Stop(pdev);
+
+  /* Initialize low level driver */
+  USBD_LL_DeInit(pdev);
+
+  return USBD_OK;
+}
+
+/**
+  * @brief  USBD_RegisterClass
+  *         Link class driver to Device Core.
+  * @param  pDevice : Device Handle
+  * @param  pclass: Class handle
+  * @retval USBD Status
+  */
+USBD_StatusTypeDef  USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass)
+{
+  USBD_StatusTypeDef status = USBD_OK;
+  if (pclass != NULL)
+  {
+    /* link the class to the USB Device handle */
+    pdev->pClass = pclass;
+    status = USBD_OK;
+  }
+  else
+  {
+#if (USBD_DEBUG_LEVEL > 1U)
+    USBD_ErrLog("Invalid Class handle");
+#endif
+    status = USBD_FAIL;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  USBD_Start
+  *         Start the USB Device Core.
+  * @param  pdev: Device Handle
+  * @retval USBD Status
+  */
+USBD_StatusTypeDef  USBD_Start(USBD_HandleTypeDef *pdev)
+{
+  /* Start the low level driver  */
+  USBD_LL_Start(pdev);
+
+  return USBD_OK;
+}
+
+/**
+  * @brief  USBD_Stop
+  *         Stop the USB Device Core.
+  * @param  pdev: Device Handle
+  * @retval USBD Status
+  */
+USBD_StatusTypeDef  USBD_Stop(USBD_HandleTypeDef *pdev)
+{
+  /* Free Class Resources */
+  pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config);
+
+  /* Stop the low level driver */
+  USBD_LL_Stop(pdev);
+
+  return USBD_OK;
+}
+
+/**
+* @brief  USBD_RunTestMode
+*         Launch test mode process
+* @param  pdev: device instance
+* @retval status
+*/
+USBD_StatusTypeDef  USBD_RunTestMode(USBD_HandleTypeDef  *pdev)
+{
+  /* Prevent unused argument compilation warning */
+  UNUSED(pdev);
+
+  return USBD_OK;
+}
+
+/**
+* @brief  USBD_SetClassConfig
+*        Configure device and start the interface
+* @param  pdev: device instance
+* @param  cfgidx: configuration index
+* @retval status
+*/
+
+USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef  *pdev, uint8_t cfgidx)
+{
+  USBD_StatusTypeDef ret = USBD_FAIL;
+
+  if (pdev->pClass != NULL)
+  {
+    /* Set configuration  and Start the Class*/
+    if (pdev->pClass->Init(pdev, cfgidx) == 0U)
+    {
+      ret = USBD_OK;
+    }
+  }
+
+  return ret;
+}
+
+/**
+* @brief  USBD_ClrClassConfig
+*         Clear current configuration
+* @param  pdev: device instance
+* @param  cfgidx: configuration index
+* @retval status: USBD_StatusTypeDef
+*/
+USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef  *pdev, uint8_t cfgidx)
+{
+  /* Clear configuration  and De-initialize the Class process*/
+  pdev->pClass->DeInit(pdev, cfgidx);
+
+  return USBD_OK;
+}
+
+
+/**
+* @brief  USBD_SetupStage
+*         Handle the setup stage
+* @param  pdev: device instance
+* @retval status
+*/
+USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup)
+{
+  USBD_ParseSetupRequest(&pdev->request, psetup);
+
+  pdev->ep0_state = USBD_EP0_SETUP;
+
+  pdev->ep0_data_len = pdev->request.wLength;
+
+  switch (pdev->request.bmRequest & 0x1FU)
+  {
+    case USB_REQ_RECIPIENT_DEVICE:
+      USBD_StdDevReq(pdev, &pdev->request);
+      break;
+
+    case USB_REQ_RECIPIENT_INTERFACE:
+      USBD_StdItfReq(pdev, &pdev->request);
+      break;
+
+    case USB_REQ_RECIPIENT_ENDPOINT:
+      USBD_StdEPReq(pdev, &pdev->request);
+      break;
+
+    default:
+      USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U));
+      break;
+  }
+
+  return USBD_OK;
+}
+
+/**
+* @brief  USBD_DataOutStage
+*         Handle data OUT stage
+* @param  pdev: device instance
+* @param  epnum: endpoint index
+* @retval status
+*/
+USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev,
+                                        uint8_t epnum, uint8_t *pdata)
+{
+  USBD_EndpointTypeDef *pep;
+
+  if (epnum == 0U)
+  {
+    pep = &pdev->ep_out[0];
+
+    if (pdev->ep0_state == USBD_EP0_DATA_OUT)
+    {
+      if (pep->rem_length > pep->maxpacket)
+      {
+        pep->rem_length -= pep->maxpacket;
+
+        USBD_CtlContinueRx(pdev, pdata,
+                           (uint16_t)MIN(pep->rem_length, pep->maxpacket));
+      }
+      else
+      {
+        if ((pdev->pClass->EP0_RxReady != NULL) &&
+            (pdev->dev_state == USBD_STATE_CONFIGURED))
+        {
+          pdev->pClass->EP0_RxReady(pdev);
+        }
+        USBD_CtlSendStatus(pdev);
+      }
+    }
+    else
+    {
+      if (pdev->ep0_state == USBD_EP0_STATUS_OUT)
+      {
+        /*
+         * STATUS PHASE completed, update ep0_state to idle
+         */
+        pdev->ep0_state = USBD_EP0_IDLE;
+        USBD_LL_StallEP(pdev, 0U);
+      }
+    }
+  }
+  else if ((pdev->pClass->DataOut != NULL) &&
+           (pdev->dev_state == USBD_STATE_CONFIGURED))
+  {
+    pdev->pClass->DataOut(pdev, epnum);
+  }
+  else
+  {
+    /* should never be in this condition */
+    return USBD_FAIL;
+  }
+
+  return USBD_OK;
+}
+
+/**
+* @brief  USBD_DataInStage
+*         Handle data in stage
+* @param  pdev: device instance
+* @param  epnum: endpoint index
+* @retval status
+*/
+USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev,
+                                       uint8_t epnum, uint8_t *pdata)
+{
+  USBD_EndpointTypeDef *pep;
+
+  if (epnum == 0U)
+  {
+    pep = &pdev->ep_in[0];
+
+    if (pdev->ep0_state == USBD_EP0_DATA_IN)
+    {
+      if (pep->rem_length > pep->maxpacket)
+      {
+        pep->rem_length -= pep->maxpacket;
+
+        USBD_CtlContinueSendData(pdev, pdata, (uint16_t)pep->rem_length);
+
+        /* Prepare endpoint for premature end of transfer */
+        USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
+      }
+      else
+      {
+        /* last packet is MPS multiple, so send ZLP packet */
+        if ((pep->total_length % pep->maxpacket == 0U) &&
+            (pep->total_length >= pep->maxpacket) &&
+            (pep->total_length < pdev->ep0_data_len))
+        {
+          USBD_CtlContinueSendData(pdev, NULL, 0U);
+          pdev->ep0_data_len = 0U;
+
+          /* Prepare endpoint for premature end of transfer */
+          USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
+        }
+        else
+        {
+          if ((pdev->pClass->EP0_TxSent != NULL) &&
+              (pdev->dev_state == USBD_STATE_CONFIGURED))
+          {
+            pdev->pClass->EP0_TxSent(pdev);
+          }
+          USBD_LL_StallEP(pdev, 0x80U);
+          USBD_CtlReceiveStatus(pdev);
+        }
+      }
+    }
+    else
+    {
+      if ((pdev->ep0_state == USBD_EP0_STATUS_IN) ||
+          (pdev->ep0_state == USBD_EP0_IDLE))
+      {
+        USBD_LL_StallEP(pdev, 0x80U);
+      }
+    }
+
+    if (pdev->dev_test_mode == 1U)
+    {
+      USBD_RunTestMode(pdev);
+      pdev->dev_test_mode = 0U;
+    }
+  }
+  else if ((pdev->pClass->DataIn != NULL) &&
+           (pdev->dev_state == USBD_STATE_CONFIGURED))
+  {
+    pdev->pClass->DataIn(pdev, epnum);
+  }
+  else
+  {
+    /* should never be in this condition */
+    return USBD_FAIL;
+  }
+
+  return USBD_OK;
+}
+
+/**
+* @brief  USBD_LL_Reset
+*         Handle Reset event
+* @param  pdev: device instance
+* @retval status
+*/
+
+USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev)
+{
+  /* Open EP0 OUT */
+  USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
+  pdev->ep_out[0x00U & 0xFU].is_used = 1U;
+
+  pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE;
+
+  /* Open EP0 IN */
+  USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
+  pdev->ep_in[0x80U & 0xFU].is_used = 1U;
+
+  pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE;
+
+  /* Upon Reset call user call back */
+  pdev->dev_state = USBD_STATE_DEFAULT;
+  pdev->ep0_state = USBD_EP0_IDLE;
+  pdev->dev_config = 0U;
+  pdev->dev_remote_wakeup = 0U;
+
+  if (pdev->pClassData)
+  {
+    pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config);
+  }
+
+  return USBD_OK;
+}
+
+/**
+* @brief  USBD_LL_Reset
+*         Handle Reset event
+* @param  pdev: device instance
+* @retval status
+*/
+USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev,
+                                    USBD_SpeedTypeDef speed)
+{
+  pdev->dev_speed = speed;
+
+  return USBD_OK;
+}
+
+/**
+* @brief  USBD_Suspend
+*         Handle Suspend event
+* @param  pdev: device instance
+* @retval status
+*/
+
+USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev)
+{
+  pdev->dev_old_state =  pdev->dev_state;
+  pdev->dev_state  = USBD_STATE_SUSPENDED;
+
+  return USBD_OK;
+}
+
+/**
+* @brief  USBD_Resume
+*         Handle Resume event
+* @param  pdev: device instance
+* @retval status
+*/
+
+USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev)
+{
+  if (pdev->dev_state == USBD_STATE_SUSPENDED)
+  {
+    pdev->dev_state = pdev->dev_old_state;
+  }
+
+  return USBD_OK;
+}
+
+/**
+* @brief  USBD_SOF
+*         Handle SOF event
+* @param  pdev: device instance
+* @retval status
+*/
+
+USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev)
+{
+  if (pdev->dev_state == USBD_STATE_CONFIGURED)
+  {
+    if (pdev->pClass->SOF != NULL)
+    {
+      pdev->pClass->SOF(pdev);
+    }
+  }
+
+  return USBD_OK;
+}
+
+/**
+* @brief  USBD_IsoINIncomplete
+*         Handle iso in incomplete event
+* @param  pdev: device instance
+* @retval status
+*/
+USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev,
+                                           uint8_t epnum)
+{
+  /* Prevent unused arguments compilation warning */
+  UNUSED(pdev);
+  UNUSED(epnum);
+
+  return USBD_OK;
+}
+
+/**
+* @brief  USBD_IsoOUTIncomplete
+*         Handle iso out incomplete event
+* @param  pdev: device instance
+* @retval status
+*/
+USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev,
+                                            uint8_t epnum)
+{
+  /* Prevent unused arguments compilation warning */
+  UNUSED(pdev);
+  UNUSED(epnum);
+
+  return USBD_OK;
+}
+
+/**
+* @brief  USBD_DevConnected
+*         Handle device connection event
+* @param  pdev: device instance
+* @retval status
+*/
+USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev)
+{
+  /* Prevent unused argument compilation warning */
+  UNUSED(pdev);
+
+  return USBD_OK;
+}
+
+/**
+* @brief  USBD_DevDisconnected
+*         Handle device disconnection event
+* @param  pdev: device instance
+* @retval status
+*/
+USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev)
+{
+  /* Free Class Resources */
+  pdev->dev_state = USBD_STATE_DEFAULT;
+  pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config);
+
+  return USBD_OK;
+}
+/**
+* @}
+*/
+
+
+/**
+* @}
+*/
+
+
+/**
+* @}
+*/
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c
new file mode 100644
index 00000000..e57c1bcd
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c
@@ -0,0 +1,918 @@
+/**
+  ******************************************************************************
+  * @file    usbd_req.c
+  * @author  MCD Application Team
+  * @brief   This file provides the standard USB requests following chapter 9.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbd_ctlreq.h"
+#include "usbd_ioreq.h"
+
+
+/** @addtogroup STM32_USBD_STATE_DEVICE_LIBRARY
+  * @{
+  */
+
+
+/** @defgroup USBD_REQ
+  * @brief USB standard requests module
+  * @{
+  */
+
+/** @defgroup USBD_REQ_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_REQ_Private_Defines
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_REQ_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_REQ_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_REQ_Private_FunctionPrototypes
+  * @{
+  */
+static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev,
+                               USBD_SetupReqTypedef *req);
+
+static void USBD_SetAddress(USBD_HandleTypeDef *pdev,
+                            USBD_SetupReqTypedef *req);
+
+static void USBD_SetConfig(USBD_HandleTypeDef *pdev,
+                           USBD_SetupReqTypedef *req);
+
+static void USBD_GetConfig(USBD_HandleTypeDef *pdev,
+                           USBD_SetupReqTypedef *req);
+
+static void USBD_GetStatus(USBD_HandleTypeDef *pdev,
+                           USBD_SetupReqTypedef *req);
+
+static void USBD_SetFeature(USBD_HandleTypeDef *pdev,
+                            USBD_SetupReqTypedef *req);
+
+static void USBD_ClrFeature(USBD_HandleTypeDef *pdev,
+                            USBD_SetupReqTypedef *req);
+
+static uint8_t USBD_GetLen(uint8_t *buf);
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_REQ_Private_Functions
+  * @{
+  */
+
+
+/**
+* @brief  USBD_StdDevReq
+*         Handle standard usb device requests
+* @param  pdev: device instance
+* @param  req: usb request
+* @retval status
+*/
+USBD_StatusTypeDef  USBD_StdDevReq(USBD_HandleTypeDef *pdev,
+                                   USBD_SetupReqTypedef *req)
+{
+  USBD_StatusTypeDef ret = USBD_OK;
+
+  switch (req->bmRequest & USB_REQ_TYPE_MASK)
+  {
+    case USB_REQ_TYPE_CLASS:
+    case USB_REQ_TYPE_VENDOR:
+      pdev->pClass->Setup(pdev, req);
+      break;
+
+    case USB_REQ_TYPE_STANDARD:
+      switch (req->bRequest)
+      {
+        case USB_REQ_GET_DESCRIPTOR:
+          USBD_GetDescriptor(pdev, req);
+          break;
+
+        case USB_REQ_SET_ADDRESS:
+          USBD_SetAddress(pdev, req);
+          break;
+
+        case USB_REQ_SET_CONFIGURATION:
+          USBD_SetConfig(pdev, req);
+          break;
+
+        case USB_REQ_GET_CONFIGURATION:
+          USBD_GetConfig(pdev, req);
+          break;
+
+        case USB_REQ_GET_STATUS:
+          USBD_GetStatus(pdev, req);
+          break;
+
+        case USB_REQ_SET_FEATURE:
+          USBD_SetFeature(pdev, req);
+          break;
+
+        case USB_REQ_CLEAR_FEATURE:
+          USBD_ClrFeature(pdev, req);
+          break;
+
+        default:
+          USBD_CtlError(pdev, req);
+          break;
+      }
+      break;
+
+    default:
+      USBD_CtlError(pdev, req);
+      break;
+  }
+
+  return ret;
+}
+
+/**
+* @brief  USBD_StdItfReq
+*         Handle standard usb interface requests
+* @param  pdev: device instance
+* @param  req: usb request
+* @retval status
+*/
+USBD_StatusTypeDef  USBD_StdItfReq(USBD_HandleTypeDef *pdev,
+                                   USBD_SetupReqTypedef  *req)
+{
+  USBD_StatusTypeDef ret = USBD_OK;
+
+  switch (req->bmRequest & USB_REQ_TYPE_MASK)
+  {
+    case USB_REQ_TYPE_CLASS:
+    case USB_REQ_TYPE_VENDOR:
+    case USB_REQ_TYPE_STANDARD:
+      switch (pdev->dev_state)
+      {
+        case USBD_STATE_DEFAULT:
+        case USBD_STATE_ADDRESSED:
+        case USBD_STATE_CONFIGURED:
+
+          if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES)
+          {
+            ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req);
+
+            if ((req->wLength == 0U) && (ret == USBD_OK))
+            {
+              USBD_CtlSendStatus(pdev);
+            }
+          }
+          else
+          {
+            USBD_CtlError(pdev, req);
+          }
+          break;
+
+        default:
+          USBD_CtlError(pdev, req);
+          break;
+      }
+      break;
+
+    default:
+      USBD_CtlError(pdev, req);
+      break;
+  }
+
+  return USBD_OK;
+}
+
+/**
+* @brief  USBD_StdEPReq
+*         Handle standard usb endpoint requests
+* @param  pdev: device instance
+* @param  req: usb request
+* @retval status
+*/
+USBD_StatusTypeDef  USBD_StdEPReq(USBD_HandleTypeDef *pdev,
+                                  USBD_SetupReqTypedef  *req)
+{
+  USBD_EndpointTypeDef *pep;
+  uint8_t   ep_addr;
+  USBD_StatusTypeDef ret = USBD_OK;
+  ep_addr  = LOBYTE(req->wIndex);
+
+  switch (req->bmRequest & USB_REQ_TYPE_MASK)
+  {
+    case USB_REQ_TYPE_CLASS:
+    case USB_REQ_TYPE_VENDOR:
+      pdev->pClass->Setup(pdev, req);
+      break;
+
+    case USB_REQ_TYPE_STANDARD:
+      /* Check if it is a class request */
+      if ((req->bmRequest & 0x60U) == 0x20U)
+      {
+        ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req);
+
+        return ret;
+      }
+
+      switch (req->bRequest)
+      {
+        case USB_REQ_SET_FEATURE:
+          switch (pdev->dev_state)
+          {
+            case USBD_STATE_ADDRESSED:
+              if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
+              {
+                USBD_LL_StallEP(pdev, ep_addr);
+                USBD_LL_StallEP(pdev, 0x80U);
+              }
+              else
+              {
+                USBD_CtlError(pdev, req);
+              }
+              break;
+
+            case USBD_STATE_CONFIGURED:
+              if (req->wValue == USB_FEATURE_EP_HALT)
+              {
+                if ((ep_addr != 0x00U) &&
+                    (ep_addr != 0x80U) && (req->wLength == 0x00U))
+                {
+                  USBD_LL_StallEP(pdev, ep_addr);
+                }
+              }
+              USBD_CtlSendStatus(pdev);
+
+              break;
+
+            default:
+              USBD_CtlError(pdev, req);
+              break;
+          }
+          break;
+
+        case USB_REQ_CLEAR_FEATURE:
+
+          switch (pdev->dev_state)
+          {
+            case USBD_STATE_ADDRESSED:
+              if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
+              {
+                USBD_LL_StallEP(pdev, ep_addr);
+                USBD_LL_StallEP(pdev, 0x80U);
+              }
+              else
+              {
+                USBD_CtlError(pdev, req);
+              }
+              break;
+
+            case USBD_STATE_CONFIGURED:
+              if (req->wValue == USB_FEATURE_EP_HALT)
+              {
+                if ((ep_addr & 0x7FU) != 0x00U)
+                {
+                  USBD_LL_ClearStallEP(pdev, ep_addr);
+                }
+                USBD_CtlSendStatus(pdev);
+              }
+              break;
+
+            default:
+              USBD_CtlError(pdev, req);
+              break;
+          }
+          break;
+
+        case USB_REQ_GET_STATUS:
+          switch (pdev->dev_state)
+          {
+            case USBD_STATE_ADDRESSED:
+              if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
+              {
+                USBD_CtlError(pdev, req);
+                break;
+              }
+              pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
+                    &pdev->ep_out[ep_addr & 0x7FU];
+
+              pep->status = 0x0000U;
+
+              USBD_CtlSendData(pdev, (uint8_t *)(void *)&pep->status, 2U);
+              break;
+
+            case USBD_STATE_CONFIGURED:
+              if ((ep_addr & 0x80U) == 0x80U)
+              {
+                if (pdev->ep_in[ep_addr & 0xFU].is_used == 0U)
+                {
+                  USBD_CtlError(pdev, req);
+                  break;
+                }
+              }
+              else
+              {
+                if (pdev->ep_out[ep_addr & 0xFU].is_used == 0U)
+                {
+                  USBD_CtlError(pdev, req);
+                  break;
+                }
+              }
+
+              pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
+                    &pdev->ep_out[ep_addr & 0x7FU];
+
+              if ((ep_addr == 0x00U) || (ep_addr == 0x80U))
+              {
+                pep->status = 0x0000U;
+              }
+              else if (USBD_LL_IsStallEP(pdev, ep_addr))
+              {
+                pep->status = 0x0001U;
+              }
+              else
+              {
+                pep->status = 0x0000U;
+              }
+
+              USBD_CtlSendData(pdev, (uint8_t *)(void *)&pep->status, 2U);
+              break;
+
+            default:
+              USBD_CtlError(pdev, req);
+              break;
+          }
+          break;
+
+        default:
+          USBD_CtlError(pdev, req);
+          break;
+      }
+      break;
+
+    default:
+      USBD_CtlError(pdev, req);
+      break;
+  }
+
+  return ret;
+}
+
+
+/**
+* @brief  USBD_GetDescriptor
+*         Handle Get Descriptor requests
+* @param  pdev: device instance
+* @param  req: usb request
+* @retval status
+*/
+static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev,
+                               USBD_SetupReqTypedef *req)
+{
+  uint16_t len = 0U;
+  uint8_t *pbuf = NULL;
+  uint8_t err = 0U;
+
+  switch (req->wValue >> 8)
+  {
+#if (USBD_LPM_ENABLED == 1U)
+    case USB_DESC_TYPE_BOS:
+      if (pdev->pDesc->GetBOSDescriptor != NULL)
+      {
+        pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len);
+      }
+      else
+      {
+        USBD_CtlError(pdev, req);
+        err++;
+      }
+      break;
+#endif
+    case USB_DESC_TYPE_DEVICE:
+      pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len);
+      break;
+
+    case USB_DESC_TYPE_CONFIGURATION:
+      if (pdev->dev_speed == USBD_SPEED_HIGH)
+      {
+        pbuf = pdev->pClass->GetHSConfigDescriptor(&len);
+        pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
+      }
+      else
+      {
+        pbuf = pdev->pClass->GetFSConfigDescriptor(&len);
+        pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
+      }
+      break;
+
+    case USB_DESC_TYPE_STRING:
+      switch ((uint8_t)(req->wValue))
+      {
+        case USBD_IDX_LANGID_STR:
+          if (pdev->pDesc->GetLangIDStrDescriptor != NULL)
+          {
+            pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len);
+          }
+          else
+          {
+            USBD_CtlError(pdev, req);
+            err++;
+          }
+          break;
+
+        case USBD_IDX_MFC_STR:
+          if (pdev->pDesc->GetManufacturerStrDescriptor != NULL)
+          {
+            pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len);
+          }
+          else
+          {
+            USBD_CtlError(pdev, req);
+            err++;
+          }
+          break;
+
+        case USBD_IDX_PRODUCT_STR:
+          if (pdev->pDesc->GetProductStrDescriptor != NULL)
+          {
+            pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len);
+          }
+          else
+          {
+            USBD_CtlError(pdev, req);
+            err++;
+          }
+          break;
+
+        case USBD_IDX_SERIAL_STR:
+          if (pdev->pDesc->GetSerialStrDescriptor != NULL)
+          {
+            pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len);
+          }
+          else
+          {
+            USBD_CtlError(pdev, req);
+            err++;
+          }
+          break;
+
+        case USBD_IDX_CONFIG_STR:
+          if (pdev->pDesc->GetConfigurationStrDescriptor != NULL)
+          {
+            pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len);
+          }
+          else
+          {
+            USBD_CtlError(pdev, req);
+            err++;
+          }
+          break;
+
+        case USBD_IDX_INTERFACE_STR:
+          if (pdev->pDesc->GetInterfaceStrDescriptor != NULL)
+          {
+            pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len);
+          }
+          else
+          {
+            USBD_CtlError(pdev, req);
+            err++;
+          }
+          break;
+
+        default:
+#if (USBD_SUPPORT_USER_STRING_DESC == 1U)
+          if (pdev->pClass->GetUsrStrDescriptor != NULL)
+          {
+            pbuf = pdev->pClass->GetUsrStrDescriptor(pdev, (req->wValue), &len);
+          }
+          else
+          {
+            USBD_CtlError(pdev, req);
+            err++;
+          }
+          break;
+#else
+          USBD_CtlError(pdev, req);
+          err++;
+#endif
+      }
+      break;
+
+    case USB_DESC_TYPE_DEVICE_QUALIFIER:
+      if (pdev->dev_speed == USBD_SPEED_HIGH)
+      {
+        pbuf = pdev->pClass->GetDeviceQualifierDescriptor(&len);
+      }
+      else
+      {
+        USBD_CtlError(pdev, req);
+        err++;
+      }
+      break;
+
+    case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION:
+      if (pdev->dev_speed == USBD_SPEED_HIGH)
+      {
+        pbuf = pdev->pClass->GetOtherSpeedConfigDescriptor(&len);
+        pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION;
+      }
+      else
+      {
+        USBD_CtlError(pdev, req);
+        err++;
+      }
+      break;
+
+    default:
+      USBD_CtlError(pdev, req);
+      err++;
+      break;
+  }
+
+  if (err != 0U)
+  {
+    return;
+  }
+  else
+  {
+    if ((len != 0U) && (req->wLength != 0U))
+    {
+      len = MIN(len, req->wLength);
+      (void)USBD_CtlSendData(pdev, pbuf, len);
+    }
+
+    if (req->wLength == 0U)
+    {
+      (void)USBD_CtlSendStatus(pdev);
+    }
+  }
+}
+
+/**
+* @brief  USBD_SetAddress
+*         Set device address
+* @param  pdev: device instance
+* @param  req: usb request
+* @retval status
+*/
+static void USBD_SetAddress(USBD_HandleTypeDef *pdev,
+                            USBD_SetupReqTypedef *req)
+{
+  uint8_t  dev_addr;
+
+  if ((req->wIndex == 0U) && (req->wLength == 0U) && (req->wValue < 128U))
+  {
+    dev_addr = (uint8_t)(req->wValue) & 0x7FU;
+
+    if (pdev->dev_state == USBD_STATE_CONFIGURED)
+    {
+      USBD_CtlError(pdev, req);
+    }
+    else
+    {
+      pdev->dev_address = dev_addr;
+      USBD_LL_SetUSBAddress(pdev, dev_addr);
+      USBD_CtlSendStatus(pdev);
+
+      if (dev_addr != 0U)
+      {
+        pdev->dev_state = USBD_STATE_ADDRESSED;
+      }
+      else
+      {
+        pdev->dev_state = USBD_STATE_DEFAULT;
+      }
+    }
+  }
+  else
+  {
+    USBD_CtlError(pdev, req);
+  }
+}
+
+/**
+* @brief  USBD_SetConfig
+*         Handle Set device configuration request
+* @param  pdev: device instance
+* @param  req: usb request
+* @retval status
+*/
+static void USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
+{
+  static uint8_t cfgidx;
+
+  cfgidx = (uint8_t)(req->wValue);
+
+  if (cfgidx > USBD_MAX_NUM_CONFIGURATION)
+  {
+    USBD_CtlError(pdev, req);
+  }
+  else
+  {
+    switch (pdev->dev_state)
+    {
+      case USBD_STATE_ADDRESSED:
+        if (cfgidx)
+        {
+          pdev->dev_config = cfgidx;
+          pdev->dev_state = USBD_STATE_CONFIGURED;
+          if (USBD_SetClassConfig(pdev, cfgidx) == USBD_FAIL)
+          {
+            USBD_CtlError(pdev, req);
+            return;
+          }
+          USBD_CtlSendStatus(pdev);
+        }
+        else
+        {
+          USBD_CtlSendStatus(pdev);
+        }
+        break;
+
+      case USBD_STATE_CONFIGURED:
+        if (cfgidx == 0U)
+        {
+          pdev->dev_state = USBD_STATE_ADDRESSED;
+          pdev->dev_config = cfgidx;
+          USBD_ClrClassConfig(pdev, cfgidx);
+          USBD_CtlSendStatus(pdev);
+        }
+        else if (cfgidx != pdev->dev_config)
+        {
+          /* Clear old configuration */
+          USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config);
+
+          /* set new configuration */
+          pdev->dev_config = cfgidx;
+          if (USBD_SetClassConfig(pdev, cfgidx) == USBD_FAIL)
+          {
+            USBD_CtlError(pdev, req);
+            return;
+          }
+          USBD_CtlSendStatus(pdev);
+        }
+        else
+        {
+          USBD_CtlSendStatus(pdev);
+        }
+        break;
+
+      default:
+        USBD_CtlError(pdev, req);
+        USBD_ClrClassConfig(pdev, cfgidx);
+        break;
+    }
+  }
+}
+
+/**
+* @brief  USBD_GetConfig
+*         Handle Get device configuration request
+* @param  pdev: device instance
+* @param  req: usb request
+* @retval status
+*/
+static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
+{
+  if (req->wLength != 1U)
+  {
+    USBD_CtlError(pdev, req);
+  }
+  else
+  {
+    switch (pdev->dev_state)
+    {
+      case USBD_STATE_DEFAULT:
+      case USBD_STATE_ADDRESSED:
+        pdev->dev_default_config = 0U;
+        USBD_CtlSendData(pdev, (uint8_t *)(void *)&pdev->dev_default_config, 1U);
+        break;
+
+      case USBD_STATE_CONFIGURED:
+        USBD_CtlSendData(pdev, (uint8_t *)(void *)&pdev->dev_config, 1U);
+        break;
+
+      default:
+        USBD_CtlError(pdev, req);
+        break;
+    }
+  }
+}
+
+/**
+* @brief  USBD_GetStatus
+*         Handle Get Status request
+* @param  pdev: device instance
+* @param  req: usb request
+* @retval status
+*/
+static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
+{
+  switch (pdev->dev_state)
+  {
+    case USBD_STATE_DEFAULT:
+    case USBD_STATE_ADDRESSED:
+    case USBD_STATE_CONFIGURED:
+      if (req->wLength != 0x2U)
+      {
+        USBD_CtlError(pdev, req);
+        break;
+      }
+
+#if (USBD_SELF_POWERED == 1U)
+      pdev->dev_config_status = USB_CONFIG_SELF_POWERED;
+#else
+      pdev->dev_config_status = 0U;
+#endif
+
+      if (pdev->dev_remote_wakeup)
+      {
+        pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP;
+      }
+
+      USBD_CtlSendData(pdev, (uint8_t *)(void *)&pdev->dev_config_status, 2U);
+      break;
+
+    default:
+      USBD_CtlError(pdev, req);
+      break;
+  }
+}
+
+
+/**
+* @brief  USBD_SetFeature
+*         Handle Set device feature request
+* @param  pdev: device instance
+* @param  req: usb request
+* @retval status
+*/
+static void USBD_SetFeature(USBD_HandleTypeDef *pdev,
+                            USBD_SetupReqTypedef *req)
+{
+  if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
+  {
+    pdev->dev_remote_wakeup = 1U;
+    USBD_CtlSendStatus(pdev);
+  }
+}
+
+
+/**
+* @brief  USBD_ClrFeature
+*         Handle clear device feature request
+* @param  pdev: device instance
+* @param  req: usb request
+* @retval status
+*/
+static void USBD_ClrFeature(USBD_HandleTypeDef *pdev,
+                            USBD_SetupReqTypedef *req)
+{
+  switch (pdev->dev_state)
+  {
+    case USBD_STATE_DEFAULT:
+    case USBD_STATE_ADDRESSED:
+    case USBD_STATE_CONFIGURED:
+      if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
+      {
+        pdev->dev_remote_wakeup = 0U;
+        USBD_CtlSendStatus(pdev);
+      }
+      break;
+
+    default:
+      USBD_CtlError(pdev, req);
+      break;
+  }
+}
+
+/**
+* @brief  USBD_ParseSetupRequest
+*         Copy buffer into setup structure
+* @param  pdev: device instance
+* @param  req: usb request
+* @retval None
+*/
+
+void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata)
+{
+  req->bmRequest = *(uint8_t *)(pdata);
+  req->bRequest = *(uint8_t *)(pdata + 1U);
+  req->wValue = SWAPBYTE(pdata + 2U);
+  req->wIndex = SWAPBYTE(pdata + 4U);
+  req->wLength = SWAPBYTE(pdata + 6U);
+
+}
+
+/**
+* @brief  USBD_CtlError
+*         Handle USB low level Error
+* @param  pdev: device instance
+* @param  req: usb request
+* @retval None
+*/
+
+void USBD_CtlError(USBD_HandleTypeDef *pdev,
+                   USBD_SetupReqTypedef *req)
+{
+  USBD_LL_StallEP(pdev, 0x80U);
+  USBD_LL_StallEP(pdev, 0U);
+}
+
+
+/**
+  * @brief  USBD_GetString
+  *         Convert Ascii string into unicode one
+  * @param  desc : descriptor buffer
+  * @param  unicode : Formatted string buffer (unicode)
+  * @param  len : descriptor length
+  * @retval None
+  */
+void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len)
+{
+  uint8_t idx = 0U;
+
+  if (desc != NULL)
+  {
+    *len = (uint16_t)USBD_GetLen(desc) * 2U + 2U;
+    unicode[idx++] = *(uint8_t *)(void *)len;
+    unicode[idx++] = USB_DESC_TYPE_STRING;
+
+    while (*desc != '\0')
+    {
+      unicode[idx++] = *desc++;
+      unicode[idx++] =  0U;
+    }
+  }
+}
+
+/**
+  * @brief  USBD_GetLen
+  *         return the string length
+   * @param  buf : pointer to the ascii string buffer
+  * @retval string length
+  */
+static uint8_t USBD_GetLen(uint8_t *buf)
+{
+  uint8_t  len = 0U;
+
+  while (*buf != '\0')
+  {
+    len++;
+    buf++;
+  }
+
+  return len;
+}
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c
new file mode 100644
index 00000000..33519727
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c
@@ -0,0 +1,216 @@
+/**
+  ******************************************************************************
+  * @file    usbd_ioreq.c
+  * @author  MCD Application Team
+  * @brief   This file provides the IO requests APIs for control endpoints.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbd_ioreq.h"
+
+/** @addtogroup STM32_USB_DEVICE_LIBRARY
+  * @{
+  */
+
+
+/** @defgroup USBD_IOREQ
+  * @brief control I/O requests module
+  * @{
+  */
+
+/** @defgroup USBD_IOREQ_Private_TypesDefinitions
+  * @{
+  */
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_IOREQ_Private_Defines
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_IOREQ_Private_Macros
+  * @{
+  */
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_IOREQ_Private_Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_IOREQ_Private_FunctionPrototypes
+  * @{
+  */
+/**
+  * @}
+  */
+
+
+/** @defgroup USBD_IOREQ_Private_Functions
+  * @{
+  */
+
+/**
+* @brief  USBD_CtlSendData
+*         send data on the ctl pipe
+* @param  pdev: device instance
+* @param  buff: pointer to data buffer
+* @param  len: length of data to be sent
+* @retval status
+*/
+USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev,
+                                    uint8_t *pbuf, uint16_t len)
+{
+  /* Set EP0 State */
+  pdev->ep0_state = USBD_EP0_DATA_IN;
+  pdev->ep_in[0].total_length = len;
+  pdev->ep_in[0].rem_length   = len;
+
+  /* Start the transfer */
+  USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
+
+  return USBD_OK;
+}
+
+/**
+* @brief  USBD_CtlContinueSendData
+*         continue sending data on the ctl pipe
+* @param  pdev: device instance
+* @param  buff: pointer to data buffer
+* @param  len: length of data to be sent
+* @retval status
+*/
+USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev,
+                                            uint8_t *pbuf, uint16_t len)
+{
+  /* Start the next transfer */
+  USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
+
+  return USBD_OK;
+}
+
+/**
+* @brief  USBD_CtlPrepareRx
+*         receive data on the ctl pipe
+* @param  pdev: device instance
+* @param  buff: pointer to data buffer
+* @param  len: length of data to be received
+* @retval status
+*/
+USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef *pdev,
+                                     uint8_t *pbuf, uint16_t len)
+{
+  /* Set EP0 State */
+  pdev->ep0_state = USBD_EP0_DATA_OUT;
+  pdev->ep_out[0].total_length = len;
+  pdev->ep_out[0].rem_length   = len;
+
+  /* Start the transfer */
+  USBD_LL_PrepareReceive(pdev, 0U, pbuf, len);
+
+  return USBD_OK;
+}
+
+/**
+* @brief  USBD_CtlContinueRx
+*         continue receive data on the ctl pipe
+* @param  pdev: device instance
+* @param  buff: pointer to data buffer
+* @param  len: length of data to be received
+* @retval status
+*/
+USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev,
+                                      uint8_t *pbuf, uint16_t len)
+{
+  USBD_LL_PrepareReceive(pdev, 0U, pbuf, len);
+
+  return USBD_OK;
+}
+
+/**
+* @brief  USBD_CtlSendStatus
+*         send zero lzngth packet on the ctl pipe
+* @param  pdev: device instance
+* @retval status
+*/
+USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev)
+{
+  /* Set EP0 State */
+  pdev->ep0_state = USBD_EP0_STATUS_IN;
+
+  /* Start the transfer */
+  USBD_LL_Transmit(pdev, 0x00U, NULL, 0U);
+
+  return USBD_OK;
+}
+
+/**
+* @brief  USBD_CtlReceiveStatus
+*         receive zero lzngth packet on the ctl pipe
+* @param  pdev: device instance
+* @retval status
+*/
+USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev)
+{
+  /* Set EP0 State */
+  pdev->ep0_state = USBD_EP0_STATUS_OUT;
+
+  /* Start the transfer */
+  USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
+
+  return USBD_OK;
+}
+
+/**
+* @brief  USBD_GetRxCount
+*         returns the received data length
+* @param  pdev: device instance
+* @param  ep_addr: endpoint address
+* @retval Rx Data blength
+*/
+uint32_t USBD_GetRxCount(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+{
+  return USBD_LL_GetRxDataSize(pdev, ep_addr);
+}
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/stm32h7xx_hal_conf.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/stm32h7xx_hal_conf.h
new file mode 100644
index 00000000..50080dbc
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/stm32h7xx_hal_conf.h
@@ -0,0 +1,493 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32H7xx_HAL_CONF_H
+#define __STM32H7xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver 
+  */
+#define HAL_MODULE_ENABLED  
+
+  /* #define HAL_ADC_MODULE_ENABLED   */
+#define HAL_FDCAN_MODULE_ENABLED
+/* #define HAL_CEC_MODULE_ENABLED   */
+/* #define HAL_COMP_MODULE_ENABLED   */
+/* #define HAL_CRC_MODULE_ENABLED   */
+/* #define HAL_CRYP_MODULE_ENABLED   */
+/* #define HAL_DAC_MODULE_ENABLED   */
+/* #define HAL_DCMI_MODULE_ENABLED   */
+/* #define HAL_DMA2D_MODULE_ENABLED   */
+/* #define HAL_ETH_MODULE_ENABLED   */
+/* #define HAL_NAND_MODULE_ENABLED   */
+/* #define HAL_NOR_MODULE_ENABLED   */
+/* #define HAL_OTFDEC_MODULE_ENABLED   */
+/* #define HAL_SRAM_MODULE_ENABLED   */
+/* #define HAL_SDRAM_MODULE_ENABLED   */
+/* #define HAL_HASH_MODULE_ENABLED   */
+/* #define HAL_HRTIM_MODULE_ENABLED   */
+/* #define HAL_HSEM_MODULE_ENABLED   */
+/* #define HAL_GFXMMU_MODULE_ENABLED   */
+/* #define HAL_JPEG_MODULE_ENABLED   */
+/* #define HAL_OPAMP_MODULE_ENABLED   */
+/* #define HAL_OSPI_MODULE_ENABLED   */
+/* #define HAL_OSPI_MODULE_ENABLED   */
+/* #define HAL_I2S_MODULE_ENABLED   */
+/* #define HAL_SMBUS_MODULE_ENABLED   */
+/* #define HAL_IWDG_MODULE_ENABLED   */
+/* #define HAL_LPTIM_MODULE_ENABLED   */
+/* #define HAL_LTDC_MODULE_ENABLED   */
+/* #define HAL_QSPI_MODULE_ENABLED   */
+/* #define HAL_RNG_MODULE_ENABLED   */
+/* #define HAL_RTC_MODULE_ENABLED   */
+/* #define HAL_SAI_MODULE_ENABLED   */
+/* #define HAL_SD_MODULE_ENABLED   */
+/* #define HAL_MMC_MODULE_ENABLED   */
+/* #define HAL_SPDIFRX_MODULE_ENABLED   */
+/* #define HAL_SPI_MODULE_ENABLED   */
+/* #define HAL_SWPMI_MODULE_ENABLED   */
+/* #define HAL_TIM_MODULE_ENABLED   */
+/* #define HAL_UART_MODULE_ENABLED   */
+/* #define HAL_USART_MODULE_ENABLED   */
+/* #define HAL_IRDA_MODULE_ENABLED   */
+/* #define HAL_SMARTCARD_MODULE_ENABLED   */
+/* #define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_PCD_MODULE_ENABLED
+/* #define HAL_HCD_MODULE_ENABLED   */
+/* #define HAL_DFSDM_MODULE_ENABLED   */
+/* #define HAL_DSI_MODULE_ENABLED   */
+/* #define HAL_JPEG_MODULE_ENABLED   */
+/* #define HAL_MDIOS_MODULE_ENABLED   */
+/* #define HAL_PSSI_MODULE_ENABLED   */
+/* #define HAL_DTS_MODULE_ENABLED   */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_MDMA_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_HSEM_MODULE_ENABLED
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).  
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal  oscillator (CSI) default value.
+  *        This value is the default CSI value after Reset.
+  */
+#if !defined  (CSI_VALUE)
+  #define CSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* CSI_VALUE */
+   
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL). 
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for I2S peripheral
+  *        This value is used by the I2S HAL module to compute the I2S clock source 
+  *        frequency, this source is inserted directly through I2S_CKIN pad. 
+  */
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+  #define EXTERNAL_CLOCK_VALUE    12288000U /*!< Value of the External clock in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+#define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            ((uint32_t)0U) /*!< tick interrupt priority */
+#define  USE_RTOS                     0U
+#define  USE_SD_TRANSCEIVER           0U               /*!< use uSD Transceiver */
+
+#define  USE_HAL_ADC_REGISTER_CALLBACKS     0U /* ADC register callback disabled     */
+#define  USE_HAL_CEC_REGISTER_CALLBACKS     0U /* CEC register callback disabled     */
+#define  USE_HAL_COMP_REGISTER_CALLBACKS    0U /* COMP register callback disabled    */
+#define  USE_HAL_CRYP_REGISTER_CALLBACKS    0U /* CRYP register callback disabled    */
+#define  USE_HAL_DAC_REGISTER_CALLBACKS     0U /* DAC register callback disabled     */
+#define  USE_HAL_DCMI_REGISTER_CALLBACKS    0U /* DCMI register callback disabled    */
+#define  USE_HAL_DFSDM_REGISTER_CALLBACKS   0U /* DFSDM register callback disabled   */
+#define  USE_HAL_DMA2D_REGISTER_CALLBACKS   0U /* DMA2D register callback disabled   */
+#define  USE_HAL_DSI_REGISTER_CALLBACKS     0U /* DSI register callback disabled     */
+#define  USE_HAL_DTS_REGISTER_CALLBACKS     0U /* DTS register callback disabled     */
+#define  USE_HAL_ETH_REGISTER_CALLBACKS     0U /* ETH register callback disabled     */
+#define  USE_HAL_FDCAN_REGISTER_CALLBACKS   0U /* FDCAN register callback disabled   */
+#define  USE_HAL_NAND_REGISTER_CALLBACKS    0U /* NAND register callback disabled    */
+#define  USE_HAL_NOR_REGISTER_CALLBACKS     0U /* NOR register callback disabled     */
+#define  USE_HAL_SDRAM_REGISTER_CALLBACKS   0U /* SDRAM register callback disabled   */
+#define  USE_HAL_SRAM_REGISTER_CALLBACKS    0U /* SRAM register callback disabled    */
+#define  USE_HAL_HASH_REGISTER_CALLBACKS    0U /* HASH register callback disabled    */
+#define  USE_HAL_HCD_REGISTER_CALLBACKS     0U /* HCD register callback disabled     */
+#define  USE_HAL_GFXMMU_REGISTER_CALLBACKS  0U /* GFXMMU register callback disabled  */
+#define  USE_HAL_HRTIM_REGISTER_CALLBACKS   0U /* HRTIM register callback disabled   */
+#define  USE_HAL_I2C_REGISTER_CALLBACKS     0U /* I2C register callback disabled     */
+#define  USE_HAL_I2S_REGISTER_CALLBACKS     0U /* I2S register callback disabled     */
+#define  USE_HAL_IRDA_REGISTER_CALLBACKS    0U /* IRDA register callback disabled    */
+#define  USE_HAL_JPEG_REGISTER_CALLBACKS    0U /* JPEG register callback disabled    */
+#define  USE_HAL_LPTIM_REGISTER_CALLBACKS   0U /* LPTIM register callback disabled   */
+#define  USE_HAL_LTDC_REGISTER_CALLBACKS    0U /* LTDC register callback disabled    */
+#define  USE_HAL_MDIOS_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */
+#define  USE_HAL_MMC_REGISTER_CALLBACKS     0U /* MMC register callback disabled     */
+#define  USE_HAL_OPAMP_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */
+#define  USE_HAL_OSPI_REGISTER_CALLBACKS    0U /* OSPI register callback disabled    */
+#define  USE_HAL_OTFDEC_REGISTER_CALLBACKS  0U /* OTFDEC register callback disabled  */
+#define  USE_HAL_PCD_REGISTER_CALLBACKS     0U /* PCD register callback disabled     */
+#define  USE_HAL_QSPI_REGISTER_CALLBACKS    0U /* QSPI register callback disabled    */
+#define  USE_HAL_RNG_REGISTER_CALLBACKS     0U /* RNG register callback disabled     */
+#define  USE_HAL_RTC_REGISTER_CALLBACKS     0U /* RTC register callback disabled     */
+#define  USE_HAL_SAI_REGISTER_CALLBACKS     0U /* SAI register callback disabled     */
+#define  USE_HAL_SD_REGISTER_CALLBACKS      0U /* SD register callback disabled      */
+#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS  0U /* SMARTCARD register callback disabled */
+#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */
+#define  USE_HAL_SMBUS_REGISTER_CALLBACKS   0U /* SMBUS register callback disabled   */
+#define  USE_HAL_SPI_REGISTER_CALLBACKS     0U /* SPI register callback disabled     */
+#define  USE_HAL_SWPMI_REGISTER_CALLBACKS   0U /* SWPMI register callback disabled   */
+#define  USE_HAL_TIM_REGISTER_CALLBACKS     0U /* TIM register callback disabled     */
+#define  USE_HAL_UART_REGISTER_CALLBACKS    0U /* UART register callback disabled    */
+#define  USE_HAL_USART_REGISTER_CALLBACKS   0U /* USART register callback disabled   */
+#define  USE_HAL_WWDG_REGISTER_CALLBACKS    0U /* WWDG register callback disabled    */
+
+/* ########################### Ethernet Configuration ######################### */
+#define ETH_TX_DESC_CNT         4  /* number of Ethernet Tx DMA descriptors */
+#define ETH_RX_DESC_CNT         4  /* number of Ethernet Rx DMA descriptors */
+
+#define ETH_MAC_ADDR0    ((uint8_t)0x02)
+#define ETH_MAC_ADDR1    ((uint8_t)0x00)
+#define ETH_MAC_ADDR2    ((uint8_t)0x00)
+#define ETH_MAC_ADDR3    ((uint8_t)0x00)
+#define ETH_MAC_ADDR4    ((uint8_t)0x00)
+#define ETH_MAC_ADDR5    ((uint8_t)0x00)
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */ 
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file 
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32h7xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32h7xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32h7xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_MDMA_MODULE_ENABLED
+ #include "stm32h7xx_hal_mdma.h"
+#endif /* HAL_MDMA_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+  #include "stm32h7xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+  #include "stm32h7xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+  #include "stm32h7xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DSI_MODULE_ENABLED
+  #include "stm32h7xx_hal_dsi.h"
+#endif /* HAL_DSI_MODULE_ENABLED */
+
+#ifdef HAL_DFSDM_MODULE_ENABLED
+  #include "stm32h7xx_hal_dfsdm.h"
+#endif /* HAL_DFSDM_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+  #include "stm32h7xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32h7xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32h7xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32h7xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+  #include "stm32h7xx_hal_fdcan.h"
+#endif /* HAL_FDCAN_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+  #include "stm32h7xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32h7xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32h7xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32h7xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+  #include "stm32h7xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32h7xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GFXMMU_MODULE_ENABLED
+  #include "stm32h7xx_hal_gfxmmu.h"
+#endif /* HAL_GFXMMU_MODULE_ENABLED */
+
+#ifdef HAL_HRTIM_MODULE_ENABLED
+  #include "stm32h7xx_hal_hrtim.h"
+#endif /* HAL_HRTIM_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32h7xx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+  #include "stm32h7xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+  #include "stm32h7xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+  #include "stm32h7xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32h7xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32h7xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32h7xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_JPEG_MODULE_ENABLED
+ #include "stm32h7xx_hal_jpeg.h"
+#endif /* HAL_JPEG_MODULE_ENABLED */
+
+#ifdef HAL_MDIOS_MODULE_ENABLED
+ #include "stm32h7xx_hal_mdios.h"
+#endif /* HAL_MDIOS_MODULE_ENABLED */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+ #include "stm32h7xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+#include "stm32h7xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+#include "stm32h7xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_OPAMP_MODULE_ENABLED
+#include "stm32h7xx_hal_opamp.h"
+#endif /* HAL_OPAMP_MODULE_ENABLED */
+
+#ifdef HAL_OSPI_MODULE_ENABLED
+  #include "stm32h7xx_hal_ospi.h"
+#endif /* HAL_OSPI_MODULE_ENABLED */
+   
+#ifdef HAL_OTFDEC_MODULE_ENABLED
+#include "stm32h7xx_hal_otfdec.h"
+#endif /* HAL_OTFDEC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32h7xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32h7xx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RAMECC_MODULE_ENABLED
+ #include "stm32h7xx_hal_ramecc.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32h7xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32h7xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32h7xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32h7xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+ #include "stm32h7xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32h7xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_SPDIFRX_MODULE_ENABLED
+ #include "stm32h7xx_hal_spdifrx.h"
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */
+
+#ifdef HAL_SWPMI_MODULE_ENABLED
+ #include "stm32h7xx_hal_swpmi.h"
+#endif /* HAL_SWPMI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32h7xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32h7xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32h7xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32h7xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32h7xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32h7xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32h7xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32h7xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32h7xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_PSSI_MODULE_ENABLED
+  #include "stm32h7xx_hal_pssi.h"
+#endif /* HAL_PSSI_MODULE_ENABLED */
+
+#ifdef HAL_DTS_MODULE_ENABLED
+  #include "stm32h7xx_hal_dts.h"
+#endif /* HAL_DTS_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed. 
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32H7xx_HAL_CONF_H */
+ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/system_stm32h7xx.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/system_stm32h7xx.c
new file mode 100644
index 00000000..58da4c83
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/lib/system_stm32h7xx.c
@@ -0,0 +1,399 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32h7xx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-Mx Device Peripheral Access Layer System Source File.
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32h7xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock, it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32h7xx_system
+  * @{
+  */
+
+/** @addtogroup STM32H7xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32h7xx.h"
+#include <math.h>
+#if !defined  (HSE_VALUE)
+#define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (CSI_VALUE)
+  #define CSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* CSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Private_Defines
+  * @{
+  */
+
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to use initialized data in D2 domain SRAM (AHB SRAM) */
+/* #define DATA_IN_D2_SRAM */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00000000UL /*!< Vector Table base offset field.
+                                      This value must be a multiple of 0x200. */
+/******************************************************************************/
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Private_Variables
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock = 64000000;
+  uint32_t SystemD2Clock = 64000000;
+  const  uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the FPU setting and  vector table location
+  *         configuration.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+#if defined (DATA_IN_D2_SRAM)
+ __IO uint32_t tmpreg;
+#endif /* DATA_IN_D2_SRAM */
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2)));  /* set CP10 and CP11 Full Access */
+  #endif
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set HSION bit */
+  RCC->CR |= RCC_CR_HSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00000000;
+
+  /* Reset HSEON, CSSON , CSION,RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */
+  RCC->CR &= 0xEAF6ED7FU;
+
+#if defined(D3_SRAM_BASE)
+  /* Reset D1CFGR register */
+  RCC->D1CFGR = 0x00000000;
+
+  /* Reset D2CFGR register */
+  RCC->D2CFGR = 0x00000000;
+
+  /* Reset D3CFGR register */
+  RCC->D3CFGR = 0x00000000;
+#else
+  /* Reset CDCFGR1 register */
+  RCC->CDCFGR1 = 0x00000000;
+
+  /* Reset CDCFGR2 register */
+  RCC->CDCFGR2 = 0x00000000;
+
+  /* Reset SRDCFGR register */
+  RCC->SRDCFGR = 0x00000000;
+#endif
+  /* Reset PLLCKSELR register */
+  RCC->PLLCKSELR = 0x00000000;
+
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x00000000;
+  /* Reset PLL1DIVR register */
+  RCC->PLL1DIVR = 0x00000000;
+  /* Reset PLL1FRACR register */
+  RCC->PLL1FRACR = 0x00000000;
+
+  /* Reset PLL2DIVR register */
+  RCC->PLL2DIVR = 0x00000000;
+
+  /* Reset PLL2FRACR register */
+
+  RCC->PLL2FRACR = 0x00000000;
+  /* Reset PLL3DIVR register */
+  RCC->PLL3DIVR = 0x00000000;
+
+  /* Reset PLL3FRACR register */
+  RCC->PLL3FRACR = 0x00000000;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+
+#if (STM32H7_DEV_ID == 0x450UL)
+  /* dual core CM7 or single core line */
+  if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
+  {
+    /* if stm32h7 revY*/
+    /* Change  the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
+    *((__IO uint32_t*)0x51008108) = 0x000000001U;
+  }
+#endif
+
+#if defined (DATA_IN_D2_SRAM)
+  /* in case of initialized data in D2 SRAM (AHB SRAM) , enable the D2 SRAM clock (AHB SRAM clock) */
+#if defined(RCC_AHB2ENR_D2SRAM3EN)
+  RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);
+#elif defined(RCC_AHB2ENR_D2SRAM2EN)
+  RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN);
+#else
+  RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN);
+#endif /* RCC_AHB2ENR_D2SRAM3EN */
+
+  tmpreg = RCC->AHB2ENR;
+  (void) tmpreg;
+#endif /* DATA_IN_D2_SRAM */
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  /* Configure the Vector Table location add offset address for cortex-M4 ------------------*/
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = D2_AHBSRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+  SCB->VTOR = FLASH_BANK2_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif /* VECT_TAB_SRAM */
+
+#else
+
+  /* Configure the Vector Table location add offset address for cortex-M7 ------------------*/
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = D1_AXISRAM_BASE  | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal AXI-RAM */
+#else
+  SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+#endif /*DUAL_CORE && CORE_CM4*/
+
+}
+
+/**
+   * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock , it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*),
+  *             HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
+  *
+  *         (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *         (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+  *             64 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+  *              25 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
+  uint32_t common_system_clock;
+  float_t fracn1, pllvco;
+
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+  case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */
+    common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
+    break;
+
+  case RCC_CFGR_SWS_CSI:  /* CSI used as system clock  source */
+    common_system_clock = CSI_VALUE;
+    break;
+
+  case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
+    common_system_clock = HSE_VALUE;
+    break;
+
+  case RCC_CFGR_SWS_PLL1:  /* PLL1 used as system clock  source */
+
+    /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
+    SYSCLK = PLL_VCO / PLLR
+    */
+    pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+    pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4)  ;
+    pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
+    fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
+
+    if (pllm != 0U)
+    {
+      switch (pllsource)
+      {
+        case RCC_PLLCKSELR_PLLSRC_HSI:  /* HSI used as PLL clock source */
+
+        hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
+        pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+
+        break;
+
+        case RCC_PLLCKSELR_PLLSRC_CSI:  /* CSI used as PLL clock source */
+          pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+        break;
+
+        case RCC_PLLCKSELR_PLLSRC_HSE:  /* HSE used as PLL clock source */
+          pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+        break;
+
+      default:
+          pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+        break;
+      }
+      pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
+      common_system_clock =  (uint32_t)(float_t)(pllvco/(float_t)pllp);
+    }
+    else
+    {
+      common_system_clock = 0U;
+    }
+    break;
+
+  default:
+    common_system_clock = CSI_VALUE;
+    break;
+  }
+
+  /* Compute SystemClock frequency --------------------------------------------------*/
+#if defined (RCC_D1CFGR_D1CPRE)
+  tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];
+
+  /* common_system_clock frequency : CM7 CPU frequency  */
+  common_system_clock >>= tmp;
+
+  /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency  */
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+
+#else
+  tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos];
+
+  /* common_system_clock frequency : CM7 CPU frequency  */
+  common_system_clock >>= tmp;
+
+  /* SystemD2Clock frequency : AXI and AHBs Clock frequency  */
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+
+#endif
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  SystemCoreClock = SystemD2Clock;
+#else
+  SystemCoreClock = common_system_clock;
+#endif /* DUAL_CORE && CORE_CM4 */
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/main.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/main.c
new file mode 100644
index 00000000..21cbe246
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/main.c
@@ -0,0 +1,290 @@
+/************************************************************************************//**
+* \file         Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/main.c
+* \brief        Bootloader application source file.
+* \ingroup      Boot_ARMCM7_STM32H7_Nucleo_H743ZI_Keil
+* \internal
+*----------------------------------------------------------------------------------------
+*                          C O P Y R I G H T
+*----------------------------------------------------------------------------------------
+*   Copyright (c) 2020  by Feaser    http://www.feaser.com    All rights reserved
+*
+*----------------------------------------------------------------------------------------
+*                            L I C E N S E
+*----------------------------------------------------------------------------------------
+* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as published by the Free
+* Software Foundation, either version 3 of the License, or (at your option) any later
+* version.
+*
+* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+* PURPOSE. See the GNU General Public License for more details.
+*
+* You have received a copy of the GNU General Public License along with OpenBLT. It
+* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
+*
+* \endinternal
+****************************************************************************************/
+
+/****************************************************************************************
+* Include files
+****************************************************************************************/
+#include "boot.h"                                /* bootloader generic header          */
+#include "stm32h7xx.h"                           /* STM32 CPU and HAL header           */
+#include "stm32h7xx_ll_pwr.h"                    /* STM32 LL PWR header                */
+#include "stm32h7xx_ll_rcc.h"                    /* STM32 LL RCC header                */
+#include "stm32h7xx_ll_utils.h"                  /* STM32 LL UTILS header              */
+#include "stm32h7xx_ll_gpio.h"                   /* STM32 LL GPIO header               */
+
+
+/****************************************************************************************
+* Function prototypes
+****************************************************************************************/
+static void Init(void);
+static void SystemClock_Config(void);
+
+
+/************************************************************************************//**
+** \brief     This is the entry point for the bootloader application and is called
+**            by the reset interrupt vector after the C-startup routines executed.
+** \return    Program return code.
+**
+****************************************************************************************/
+int main(void)
+{
+  /* initialize the microcontroller */
+  Init();
+  /* initialize the bootloader */
+  BootInit();
+
+  /* start the infinite program loop */
+  while (1)
+  {
+    /* run the bootloader task */
+    BootTask();
+  }
+
+  /* program should never get here */
+  return 0;
+} /*** end of main ***/
+
+
+/************************************************************************************//**
+** \brief     Initializes the microcontroller.
+** \return    none.
+**
+****************************************************************************************/
+static void Init(void)
+{
+  /* HAL library initialization */
+  HAL_Init();
+  /* configure system clock */
+  SystemClock_Config();
+} /*** end of Init ***/
+
+
+/************************************************************************************//**
+** \brief     System Clock Configuration. This code was created by CubeMX and configures
+**            the system clock to match the configuration in the bootloader's
+**            configuration (blt_conf.h), specifically the macros:
+**            BOOT_CPU_SYSTEM_SPEED_KHZ and BOOT_CPU_XTAL_SPEED_KHZ.
+**            Note that the Lower Layer drivers were selected in CubeMX for the RCC
+**            subsystem.
+** \return    none.
+**
+****************************************************************************************/
+static void SystemClock_Config(void)
+{
+  /* Set flash latency. */
+  LL_FLASH_SetLatency(LL_FLASH_LATENCY_4);
+  if (LL_FLASH_GetLatency() != LL_FLASH_LATENCY_4)
+  {
+    /* Error setting flash latency. */
+    ASSERT_RT(BLT_FALSE);
+  }
+
+  /* Configure the main internal regulator output voltage. */
+  LL_PWR_ConfigSupply(LL_PWR_LDO_SUPPLY);
+  LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE0);
+
+  /* Enable the HSE clock. */
+  LL_RCC_HSE_EnableBypass();
+  LL_RCC_HSE_Enable();
+
+  /* Wait till HSE is ready. */
+  while (LL_RCC_HSE_IsReady() != 1)
+  {
+    ;
+  }
+
+  /* Configure and enable the PLL. */
+  LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_HSE);
+  LL_RCC_PLL1P_Enable();
+  LL_RCC_PLL1Q_Enable();
+  LL_RCC_PLL1_SetVCOInputRange(LL_RCC_PLLINPUTRANGE_2_4);
+  LL_RCC_PLL1_SetVCOOutputRange(LL_RCC_PLLVCORANGE_WIDE);
+  LL_RCC_PLL1_SetM(4);
+  LL_RCC_PLL1_SetN(480);
+  LL_RCC_PLL1_SetP(2);
+  LL_RCC_PLL1_SetQ(20);
+  LL_RCC_PLL1_SetR(2);
+  LL_RCC_PLL1_Enable();
+  /* Wait till PLL is ready. */
+  while (LL_RCC_PLL1_IsReady() != 1)
+  {
+    ;
+  }
+
+  /* Intermediate AHB prescaler 2 when target frequency clock is higher than 80 MHz */
+  LL_RCC_SetAHBPrescaler(LL_RCC_AHB_DIV_2);
+
+  LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL1);
+  LL_RCC_SetSysPrescaler(LL_RCC_SYSCLK_DIV_1);
+  LL_RCC_SetAHBPrescaler(LL_RCC_AHB_DIV_2);
+  LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_2);
+  LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_2);
+  LL_RCC_SetAPB3Prescaler(LL_RCC_APB3_DIV_2);
+  LL_RCC_SetAPB4Prescaler(LL_RCC_APB4_DIV_2);
+
+  /* Configure peripheral clock sources. */
+  LL_RCC_SetUSARTClockSource(LL_RCC_USART234578_CLKSOURCE_PCLK1);
+  LL_RCC_SetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE_HSE);
+  LL_RCC_SetUSBClockSource(LL_RCC_USB_CLKSOURCE_PLL1Q);
+
+  /* Update the system clock speed setting. */
+  LL_SetSystemCoreClock(BOOT_CPU_SYSTEM_SPEED_KHZ * 1000u);
+} /*** end of SystemClock_Config ***/
+
+
+/************************************************************************************//**
+** \brief     Initializes the Global MSP. This function is called from HAL_Init()
+**            function to perform system level initialization (GPIOs, clock, DMA,
+**            interrupt).
+** \return    none.
+**
+****************************************************************************************/
+void HAL_MspInit(void)
+{
+  LL_GPIO_InitTypeDef GPIO_InitStruct;
+
+  /* SYSCFG clock enable. */
+  LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_SYSCFG);
+
+  /* GPIO ports clock enable. */
+  LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOA);
+  LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOB);
+  LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOC);
+  LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOD);
+
+#if (BOOT_COM_RS232_ENABLE > 0)
+  /* UART clock enable. */
+  LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USART3);
+#endif
+
+#if (BOOT_COM_CAN_ENABLE > 0)
+  /* CAN clock enable. */
+  LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_FDCAN);
+#endif
+
+  /* Configure GPIO pin for the LED. */
+  GPIO_InitStruct.Pin = LL_GPIO_PIN_7;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  LL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+  /* Configure GPIO pin for (optional) backdoor entry input. */
+  GPIO_InitStruct.Pin = LL_GPIO_PIN_13;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  LL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+#if (BOOT_COM_RS232_ENABLE > 0)
+  /* UART TX and RX GPIO pin configuration. */
+  GPIO_InitStruct.Pin = LL_GPIO_PIN_8 | LL_GPIO_PIN_9;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  GPIO_InitStruct.Alternate = LL_GPIO_AF_7;
+  LL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+#endif
+
+#if (BOOT_COM_CAN_ENABLE > 0)
+  /* CAN TX and RX GPIO pin configuration. */
+  GPIO_InitStruct.Pin = LL_GPIO_PIN_8 | LL_GPIO_PIN_9;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  GPIO_InitStruct.Alternate = LL_GPIO_AF_9;
+  LL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+#endif
+
+#if (BOOT_COM_USB_ENABLE > 0)
+  /* USB pin configuration. */
+  GPIO_InitStruct.Pin = LL_GPIO_PIN_11 | LL_GPIO_PIN_12;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  GPIO_InitStruct.Alternate = LL_GPIO_AF_10;
+  LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+#endif
+
+#if (BOOT_COM_USB_ENABLE > 0)
+  /* USB clock enable. */
+  LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_USB2OTGHS);
+#endif
+} /*** end of HAL_MspInit ***/
+
+
+/************************************************************************************//**
+** \brief     DeInitializes the Global MSP. This function is called from HAL_DeInit()
+**            function to perform system level de-initialization (GPIOs, clock, DMA,
+**            interrupt).
+** \return    none.
+**
+****************************************************************************************/
+void HAL_MspDeInit(void)
+{
+  /* Reset the RCC clock configuration to the default reset state. */
+  LL_RCC_DeInit();
+  
+  /* Reset GPIO pin for the LED to turn it off. */
+  LL_GPIO_ResetOutputPin(GPIOB, LL_GPIO_PIN_7);
+
+  /* Deinit used GPIOs. */
+  LL_GPIO_DeInit(GPIOD);
+  LL_GPIO_DeInit(GPIOC);
+  LL_GPIO_DeInit(GPIOB);
+  LL_GPIO_DeInit(GPIOA);
+
+#if (BOOT_COM_USB_ENABLE > 0)
+  /* USB clock disable. */
+  LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_USB2OTGHS);
+#endif
+
+#if (BOOT_COM_CAN_ENABLE > 0)
+  /* CAN clock disable. */
+  LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_FDCAN);
+#endif
+
+#if (BOOT_COM_RS232_ENABLE > 0)
+  /* UART clock disable. */
+  LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_USART3);
+#endif
+
+  /* GPIO ports clock disable. */
+  LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_GPIOD);
+  LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_GPIOC);
+  LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_GPIOB);
+  LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_GPIOA);
+
+  /* SYSCFG clock disable. */
+  LL_APB4_GRP1_DisableClock(LL_APB4_GRP1_PERIPH_SYSCFG);
+} /*** end of HAL_MspDeInit ***/
+
+
+/*********************************** end of main.c *************************************/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/startup_stm32h743xx.s b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/startup_stm32h743xx.s
new file mode 100644
index 00000000..b298f2b8
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/startup_stm32h743xx.s
@@ -0,0 +1,608 @@
+;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;* File Name          : startup_stm32h743xx.s
+;* @author  MCD Application Team
+;* Description        : STM32H7xx devices vector table for MDK-ARM toolchain. 
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                IMPORT  SysTick_Handler	
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp                      ; Top of Stack
+                DCD     Reset_Handler                     ; Reset Handler
+                DCD     NMI_Handler                       ; NMI Handler
+                DCD     HardFault_Handler                 ; Hard Fault Handler
+                DCD     MemManage_Handler                 ; MPU Fault Handler
+                DCD     BusFault_Handler                  ; Bus Fault Handler
+                DCD     UsageFault_Handler                ; Usage Fault Handler
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     SVC_Handler                       ; SVCall Handler
+                DCD     DebugMon_Handler                  ; Debug Monitor Handler
+                DCD     0                                 ; Reserved
+                DCD     PendSV_Handler                    ; PendSV Handler
+                DCD     SysTick_Handler                   ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog interrupt ( wwdg1_it)                                         
+                DCD     PVD_AVD_IRQHandler                ; PVD/AVD through EXTI Line detection                        
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line            
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line                       
+                DCD     FLASH_IRQHandler                  ; FLASH                                           
+                DCD     RCC_IRQHandler                    ; RCC                                             
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0                                             
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1                                             
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2                                             
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3                                             
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4 
+                DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0
+                DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1                                   
+                DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2                                   
+                DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3                                   
+                DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4                                   
+                DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5                                   
+                DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6  
+                DCD     ADC_IRQHandler                    ; ADC1, ADC2                             
+                DCD     FDCAN1_IT0_IRQHandler             ; FDCAN1 interrupt line 0                        
+                DCD     FDCAN2_IT0_IRQHandler             ; FDCAN2 interrupt line 0                               
+                DCD     FDCAN1_IT1_IRQHandler             ; FDCAN1 interrupt line 1                        
+                DCD     FDCAN2_IT1_IRQHandler             ; FDCAN2 interrupt line 1                                               
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s                                    
+                DCD     TIM1_BRK_IRQHandler               ; TIM1 Break interrupt                   
+                DCD     TIM1_UP_IRQHandler                ; TIM1 Update Interrupt                 
+                DCD     TIM1_TRG_COM_IRQHandler           ; TIM1 Trigger and Commutation Interrupt 
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare                                   
+                DCD     TIM2_IRQHandler                   ; TIM2                                            
+                DCD     TIM3_IRQHandler                   ; TIM3                                            
+                DCD     TIM4_IRQHandler                   ; TIM4                                            
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event                                             
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error                                             
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event                                             
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error                                               
+                DCD     SPI1_IRQHandler                   ; SPI1                                            
+                DCD     SPI2_IRQHandler                   ; SPI2                                            
+                DCD     USART1_IRQHandler                 ; USART1                                          
+                DCD     USART2_IRQHandler                 ; USART2                                          
+                DCD     USART3_IRQHandler                 ; USART3                                          
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]  
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+                DCD     0                                 ; Reserved                                          
+                DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break Interrupt and TIM12 global interrupt                 
+                DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update Interrupt and TIM13 global interrupt
+                DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt
+                DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7                                           
+                DCD     FMC_IRQHandler                    ; FMC                             
+                DCD     SDMMC1_IRQHandler                 ; SDMMC1                            
+                DCD     TIM5_IRQHandler                   ; TIM5                            
+                DCD     SPI3_IRQHandler                   ; SPI3                            
+                DCD     UART4_IRQHandler                  ; UART4                           
+                DCD     UART5_IRQHandler                  ; UART5                           
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors           
+                DCD     TIM7_IRQHandler                   ; TIM7           
+                DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0                   
+                DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1                   
+                DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2                   
+                DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3                   
+                DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4                   
+                DCD     ETH_IRQHandler                    ; Ethernet                        
+                DCD     ETH_WKUP_IRQHandler               ; Ethernet Wakeup through EXTI line              
+                DCD     FDCAN_CAL_IRQHandler              ; FDCAN calibration unit interrupt                        
+                DCD     0                                 ; Reserved                              
+                DCD     0                                 ; Reserved 
+                DCD     0                                 ; Reserved 
+                DCD     0                                 ; Reserved                      
+                DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5                   
+                DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6                   
+                DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7                   
+                DCD     USART6_IRQHandler                 ; USART6                           
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event                             
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error                             
+                DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out                      
+                DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In                       
+                DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI                         
+                DCD     OTG_HS_IRQHandler                 ; USB OTG HS                    
+                DCD     DCMI_IRQHandler                   ; DCMI                            
+                DCD     0                                 ; Reserved                                     
+                DCD     RNG_IRQHandler                    ; Rng
+                DCD     FPU_IRQHandler                    ; FPU
+                DCD     UART7_IRQHandler                  ; UART7
+                DCD     UART8_IRQHandler                  ; UART8
+                DCD     SPI4_IRQHandler                   ; SPI4
+                DCD     SPI5_IRQHandler                   ; SPI5
+                DCD     SPI6_IRQHandler                   ; SPI6
+                DCD     SAI1_IRQHandler                   ; SAI1
+                DCD     LTDC_IRQHandler                   ; LTDC
+                DCD     LTDC_ER_IRQHandler                ; LTDC error
+                DCD     DMA2D_IRQHandler                  ; DMA2D
+                DCD     SAI2_IRQHandler                   ; SAI2
+                DCD     QUADSPI_IRQHandler                ; QUADSPI
+                DCD     LPTIM1_IRQHandler                 ; LPTIM1
+                DCD     CEC_IRQHandler                    ; HDMI_CEC
+                DCD     I2C4_EV_IRQHandler                ; I2C4 Event                             
+                DCD     I2C4_ER_IRQHandler                ; I2C4 Error 
+                DCD     SPDIF_RX_IRQHandler               ; SPDIF_RX
+                DCD     OTG_FS_EP1_OUT_IRQHandler         ; USB OTG FS End Point 1 Out                      
+                DCD     OTG_FS_EP1_IN_IRQHandler          ; USB OTG FS End Point 1 In                       
+                DCD     OTG_FS_WKUP_IRQHandler            ; USB OTG FS Wakeup through EXTI                         
+                DCD     OTG_FS_IRQHandler                 ; USB OTG FS                 
+                DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX1 Overrun interrupt  
+                DCD     HRTIM1_Master_IRQHandler          ; HRTIM Master Timer global Interrupts                              
+                DCD     HRTIM1_TIMA_IRQHandler            ; HRTIM Timer A global Interrupt                                    
+                DCD     HRTIM1_TIMB_IRQHandler            ; HRTIM Timer B global Interrupt                                    
+                DCD     HRTIM1_TIMC_IRQHandler            ; HRTIM Timer C global Interrupt                                    
+                DCD     HRTIM1_TIMD_IRQHandler            ; HRTIM Timer D global Interrupt                                    
+                DCD     HRTIM1_TIME_IRQHandler            ; HRTIM Timer E global Interrupt                                    
+                DCD     HRTIM1_FLT_IRQHandler             ; HRTIM Fault global Interrupt 
+                DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM Filter0 Interrupt   
+                DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM Filter1 Interrupt                                            
+                DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM Filter2 Interrupt                                            
+                DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM Filter3 Interrupt                                                                                    
+                DCD     SAI3_IRQHandler                   ; SAI3 global Interrupt                                             
+                DCD     SWPMI1_IRQHandler                 ; Serial Wire Interface 1 global interrupt                          
+                DCD     TIM15_IRQHandler                  ; TIM15 global Interrupt                                            
+                DCD     TIM16_IRQHandler                  ; TIM16 global Interrupt                                            
+                DCD     TIM17_IRQHandler                  ; TIM17 global Interrupt                                            
+                DCD     MDIOS_WKUP_IRQHandler             ; MDIOS Wakeup  Interrupt                                           
+                DCD     MDIOS_IRQHandler                  ; MDIOS global Interrupt                                            
+                DCD     JPEG_IRQHandler                   ; JPEG global Interrupt                                             
+                DCD     MDMA_IRQHandler                   ; MDMA global Interrupt                                             
+                DCD     0                                 ; Reserved                                               
+                DCD     SDMMC2_IRQHandler                 ; SDMMC2 global Interrupt                                           
+                DCD     HSEM1_IRQHandler                  ; HSEM1 global Interrupt                                             
+                DCD     0                                 ; Reserved                                              
+                DCD     ADC3_IRQHandler                   ; ADC3 global Interrupt                                              
+                DCD     DMAMUX2_OVR_IRQHandler            ; DMAMUX Overrun interrupt                                           
+                DCD     BDMA_Channel0_IRQHandler          ; BDMA Channel 0 global Interrupt                                    
+                DCD     BDMA_Channel1_IRQHandler          ; BDMA Channel 1 global Interrupt                                    
+                DCD     BDMA_Channel2_IRQHandler          ; BDMA Channel 2 global Interrupt                                    
+                DCD     BDMA_Channel3_IRQHandler          ; BDMA Channel 3 global Interrupt                                    
+                DCD     BDMA_Channel4_IRQHandler          ; BDMA Channel 4 global Interrupt                                    
+                DCD     BDMA_Channel5_IRQHandler          ; BDMA Channel 5 global Interrupt                                    
+                DCD     BDMA_Channel6_IRQHandler          ; BDMA Channel 6 global Interrupt                                    
+                DCD     BDMA_Channel7_IRQHandler          ; BDMA Channel 7 global Interrupt                                    
+                DCD     COMP1_IRQHandler                  ; COMP1 global Interrupt                                            
+                DCD     LPTIM2_IRQHandler                 ; LP TIM2 global interrupt                                          
+                DCD     LPTIM3_IRQHandler                 ; LP TIM3 global interrupt                                          
+                DCD     LPTIM4_IRQHandler                 ; LP TIM4 global interrupt                                          
+                DCD     LPTIM5_IRQHandler                 ; LP TIM5 global interrupt                                          
+                DCD     LPUART1_IRQHandler                ; LP UART1 interrupt                                                
+                DCD     0                                 ; Reserved                                                                              
+                DCD     CRS_IRQHandler                    ; Clock Recovery Global Interrupt                                   
+                DCD     ECC_IRQHandler                    ; ECC diagnostic Global Interrupt                                              
+                DCD     SAI4_IRQHandler                   ; SAI4 global interrupt                                                
+                DCD     0                                 ; Reserved                                 
+                DCD     0                                 ; Reserved                                    
+                DCD     WAKEUP_PIN_IRQHandler             ; Interrupt for all 6 wake-up pins 
+                
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                    [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                      [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler                [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler                [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler                 [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler               [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                      [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler                  [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                    [WEAK]
+                B       .
+                ENDP
+                                                          
+Default_Handler PROC                                      
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]                                       
+                EXPORT  PVD_AVD_IRQHandler                [WEAK]                         
+                EXPORT  TAMP_STAMP_IRQHandler             [WEAK]   
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]             
+                EXPORT  FLASH_IRQHandler                  [WEAK]                                        
+                EXPORT  RCC_IRQHandler                    [WEAK]                                          
+                EXPORT  EXTI0_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI1_IRQHandler                  [WEAK]                                           
+                EXPORT  EXTI2_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI3_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Stream0_IRQHandler           [WEAK] 
+                EXPORT  DMA1_Stream1_IRQHandler           [WEAK]                        
+                EXPORT  DMA1_Stream2_IRQHandler           [WEAK]                     
+                EXPORT  DMA1_Stream3_IRQHandler           [WEAK]                    
+                EXPORT  DMA1_Stream4_IRQHandler           [WEAK]                        
+                EXPORT  DMA1_Stream5_IRQHandler           [WEAK]                          
+                EXPORT  DMA1_Stream6_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream7_IRQHandler           [WEAK]
+                EXPORT  ADC_IRQHandler                    [WEAK]                          
+                EXPORT  FDCAN1_IT0_IRQHandler             [WEAK]                                            
+                EXPORT  FDCAN2_IT0_IRQHandler             [WEAK] 
+                EXPORT  FDCAN1_IT1_IRQHandler             [WEAK]                                            
+                EXPORT  FDCAN2_IT1_IRQHandler             [WEAK]   
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]                                    
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]                  
+                EXPORT  TIM1_UP_IRQHandler                [WEAK]                
+                EXPORT  TIM1_TRG_COM_IRQHandler           [WEAK] 
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]                                   
+                EXPORT  TIM2_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM3_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM4_IRQHandler                   [WEAK]                                            
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]                                             
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]                                             
+                EXPORT  I2C2_EV_IRQHandler                [WEAK]                                            
+                EXPORT  I2C2_ER_IRQHandler                [WEAK]                                               
+                EXPORT  SPI1_IRQHandler                   [WEAK]                                           
+                EXPORT  SPI2_IRQHandler                   [WEAK]                                            
+                EXPORT  USART1_IRQHandler                 [WEAK]                                          
+                EXPORT  USART2_IRQHandler                 [WEAK]                                          
+                EXPORT  USART3_IRQHandler                 [WEAK]                                         
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]                                  
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]                                       
+                EXPORT  TIM8_BRK_TIM12_IRQHandler         [WEAK]                 
+                EXPORT  TIM8_UP_TIM13_IRQHandler          [WEAK]                 
+                EXPORT  TIM8_TRG_COM_TIM14_IRQHandler     [WEAK] 
+                EXPORT  TIM8_CC_IRQHandler                [WEAK]                                   
+                EXPORT  DMA1_Stream7_IRQHandler           [WEAK]                                          
+                EXPORT  FMC_IRQHandler                    [WEAK]                                             
+                EXPORT  SDMMC1_IRQHandler                 [WEAK]                                             
+                EXPORT  TIM5_IRQHandler                   [WEAK]                                             
+                EXPORT  SPI3_IRQHandler                   [WEAK]                                             
+                EXPORT  UART4_IRQHandler                  [WEAK]                                            
+                EXPORT  UART5_IRQHandler                  [WEAK]                                            
+                EXPORT  TIM6_DAC_IRQHandler               [WEAK]                   
+                EXPORT  TIM7_IRQHandler                   [WEAK]                    
+                EXPORT  DMA2_Stream0_IRQHandler           [WEAK]                                  
+                EXPORT  DMA2_Stream1_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream2_IRQHandler           [WEAK]                                    
+                EXPORT  DMA2_Stream3_IRQHandler           [WEAK]                                    
+                EXPORT  DMA2_Stream4_IRQHandler           [WEAK]                                 
+                EXPORT  ETH_IRQHandler                    [WEAK]                                         
+                EXPORT  ETH_WKUP_IRQHandler               [WEAK]                     
+                EXPORT  FDCAN_CAL_IRQHandler              [WEAK]                                                                                                                                                                              
+                EXPORT  DMA2_Stream5_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream6_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream7_IRQHandler           [WEAK]                                   
+                EXPORT  USART6_IRQHandler                 [WEAK]                                           
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]                                              
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]                                              
+                EXPORT  OTG_HS_EP1_OUT_IRQHandler         [WEAK]                      
+                EXPORT  OTG_HS_EP1_IN_IRQHandler          [WEAK]                      
+                EXPORT  OTG_HS_WKUP_IRQHandler            [WEAK]                        
+                EXPORT  OTG_HS_IRQHandler                 [WEAK]                                      
+                EXPORT  DCMI_IRQHandler                   [WEAK]                                             
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  UART7_IRQHandler                  [WEAK]
+                EXPORT  UART8_IRQHandler                  [WEAK]
+                EXPORT  SPI4_IRQHandler                   [WEAK]
+                EXPORT  SPI5_IRQHandler                   [WEAK]
+                EXPORT  SPI6_IRQHandler                   [WEAK]
+                EXPORT  SAI1_IRQHandler                   [WEAK]
+                EXPORT  LTDC_IRQHandler                   [WEAK]
+                EXPORT  LTDC_ER_IRQHandler                [WEAK]
+                EXPORT  DMA2D_IRQHandler                  [WEAK]
+                EXPORT  SAI2_IRQHandler                   [WEAK]   
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  CEC_IRQHandler                    [WEAK]   
+                EXPORT  I2C4_EV_IRQHandler                [WEAK]
+                EXPORT  I2C4_ER_IRQHandler                [WEAK] 
+                EXPORT  SPDIF_RX_IRQHandler               [WEAK]
+                EXPORT  OTG_FS_EP1_OUT_IRQHandler         [WEAK]
+                EXPORT  OTG_FS_EP1_IN_IRQHandler          [WEAK]                      
+                EXPORT  OTG_FS_WKUP_IRQHandler            [WEAK]                      
+                EXPORT  OTG_FS_IRQHandler                 [WEAK]                        
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+                EXPORT  HRTIM1_Master_IRQHandler          [WEAK] 
+                EXPORT  HRTIM1_TIMA_IRQHandler            [WEAK]                                      
+                EXPORT  HRTIM1_TIMB_IRQHandler            [WEAK]                                      
+                EXPORT  HRTIM1_TIMC_IRQHandler            [WEAK]                                      
+                EXPORT  HRTIM1_TIMD_IRQHandler            [WEAK]                                      
+                EXPORT  HRTIM1_TIME_IRQHandler            [WEAK]                                      
+                EXPORT  HRTIM1_FLT_IRQHandler             [WEAK]
+                EXPORT  DFSDM1_FLT0_IRQHandler            [WEAK] 
+                EXPORT  DFSDM1_FLT1_IRQHandler            [WEAK]                                             
+                EXPORT  DFSDM1_FLT2_IRQHandler            [WEAK]                                             
+                EXPORT  DFSDM1_FLT3_IRQHandler            [WEAK]                                                                                        
+                EXPORT  SAI3_IRQHandler                   [WEAK]                                             
+                EXPORT  SWPMI1_IRQHandler                 [WEAK]                            
+                EXPORT  TIM15_IRQHandler                  [WEAK]                                             
+                EXPORT  TIM16_IRQHandler                  [WEAK]                                              
+                EXPORT  TIM17_IRQHandler                  [WEAK]                                            
+                EXPORT  MDIOS_WKUP_IRQHandler             [WEAK]                                             
+                EXPORT  MDIOS_IRQHandler                  [WEAK]                                              
+                EXPORT  JPEG_IRQHandler                   [WEAK]                                               
+                EXPORT  MDMA_IRQHandler                   [WEAK]                                                                                             
+                EXPORT  SDMMC2_IRQHandler                 [WEAK]                                             
+                EXPORT  HSEM1_IRQHandler                  [WEAK]                                                                                                             
+                EXPORT  ADC3_IRQHandler                   [WEAK]                                                
+                EXPORT  DMAMUX2_OVR_IRQHandler            [WEAK]                                            
+                EXPORT  BDMA_Channel0_IRQHandler          [WEAK]                                      
+                EXPORT  BDMA_Channel1_IRQHandler          [WEAK]                                      
+                EXPORT  BDMA_Channel2_IRQHandler          [WEAK]                                      
+                EXPORT  BDMA_Channel3_IRQHandler          [WEAK]                                      
+                EXPORT  BDMA_Channel4_IRQHandler          [WEAK]                                     
+                EXPORT  BDMA_Channel5_IRQHandler          [WEAK]                                      
+                EXPORT  BDMA_Channel6_IRQHandler          [WEAK]                                      
+                EXPORT  BDMA_Channel7_IRQHandler          [WEAK]                                     
+                EXPORT  COMP1_IRQHandler                  [WEAK]                                              
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]                                           
+                EXPORT  LPTIM3_IRQHandler                 [WEAK]                                            
+                EXPORT  LPTIM4_IRQHandler                 [WEAK]                                            
+                EXPORT  LPTIM5_IRQHandler                 [WEAK]                                            
+                EXPORT  LPUART1_IRQHandler                [WEAK]                                                  
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  ECC_IRQHandler                    [WEAK] 				
+                EXPORT  SAI4_IRQHandler                   [WEAK]                                                                                     
+                EXPORT  WAKEUP_PIN_IRQHandler             [WEAK] 
+
+
+WWDG_IRQHandler                                                          
+PVD_AVD_IRQHandler                                             
+TAMP_STAMP_IRQHandler                
+RTC_WKUP_IRQHandler                            
+FLASH_IRQHandler                                                          
+RCC_IRQHandler                                                              
+EXTI0_IRQHandler                                                              
+EXTI1_IRQHandler                                                             
+EXTI2_IRQHandler                                                              
+EXTI3_IRQHandler                                                              
+EXTI4_IRQHandler 
+DMA1_Stream0_IRQHandler
+DMA1_Stream1_IRQHandler                                  
+DMA1_Stream2_IRQHandler                               
+DMA1_Stream3_IRQHandler                              
+DMA1_Stream4_IRQHandler                                  
+DMA1_Stream5_IRQHandler                                    
+DMA1_Stream6_IRQHandler                   
+ADC_IRQHandler                                           
+FDCAN1_IT0_IRQHandler
+FDCAN2_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
+FDCAN2_IT1_IRQHandler
+EXTI9_5_IRQHandler                                                
+TIM1_BRK_IRQHandler                        
+TIM1_UP_IRQHandler                      
+TIM1_TRG_COM_IRQHandler  
+TIM1_CC_IRQHandler                                               
+TIM2_IRQHandler                                                           
+TIM3_IRQHandler                                                           
+TIM4_IRQHandler                                                           
+I2C1_EV_IRQHandler                                                         
+I2C1_ER_IRQHandler                                                         
+I2C2_EV_IRQHandler                                                        
+I2C2_ER_IRQHandler                                                           
+SPI1_IRQHandler                                                          
+SPI2_IRQHandler                                                           
+USART1_IRQHandler                                                       
+USART2_IRQHandler                                                       
+USART3_IRQHandler                                                      
+EXTI15_10_IRQHandler                                            
+RTC_Alarm_IRQHandler                                                           
+TIM8_BRK_TIM12_IRQHandler                      
+TIM8_UP_TIM13_IRQHandler                       
+TIM8_TRG_COM_TIM14_IRQHandler  
+TIM8_CC_IRQHandler                                               
+DMA1_Stream7_IRQHandler                                                 
+FMC_IRQHandler                                                            
+SDMMC1_IRQHandler                                                            
+TIM5_IRQHandler                                                            
+SPI3_IRQHandler                                                            
+UART4_IRQHandler                                                          
+UART5_IRQHandler                                                          
+TIM6_DAC_IRQHandler                            
+TIM7_IRQHandler                              
+DMA2_Stream0_IRQHandler                                         
+DMA2_Stream1_IRQHandler                                          
+DMA2_Stream2_IRQHandler                                           
+DMA2_Stream3_IRQHandler                                           
+DMA2_Stream4_IRQHandler                                        
+ETH_IRQHandler                                                         
+ETH_WKUP_IRQHandler                                
+FDCAN_CAL_IRQHandler                                                                                                                                                                                                                            
+DMA2_Stream5_IRQHandler                                          
+DMA2_Stream6_IRQHandler                                          
+DMA2_Stream7_IRQHandler                                          
+USART6_IRQHandler                                                        
+I2C3_EV_IRQHandler                                                          
+I2C3_ER_IRQHandler                                                          
+OTG_HS_EP1_OUT_IRQHandler 
+OTG_HS_EP1_IN_IRQHandler 
+OTG_HS_WKUP_IRQHandler   
+OTG_HS_IRQHandler        
+DCMI_IRQHandler                                                            
+RNG_IRQHandler
+FPU_IRQHandler  
+UART7_IRQHandler                  
+UART8_IRQHandler                  
+SPI4_IRQHandler                   
+SPI5_IRQHandler                   
+SPI6_IRQHandler                   
+SAI1_IRQHandler                   
+LTDC_IRQHandler                   
+LTDC_ER_IRQHandler                 
+DMA2D_IRQHandler   
+SAI2_IRQHandler        
+QUADSPI_IRQHandler
+LPTIM1_IRQHandler
+CEC_IRQHandler
+I2C4_EV_IRQHandler
+I2C4_ER_IRQHandler
+SPDIF_RX_IRQHandler
+OTG_FS_EP1_OUT_IRQHandler
+OTG_FS_EP1_IN_IRQHandler 
+OTG_FS_WKUP_IRQHandler   
+OTG_FS_IRQHandler        
+DMAMUX1_OVR_IRQHandler
+HRTIM1_Master_IRQHandler               
+HRTIM1_TIMA_IRQHandler                                                      
+HRTIM1_TIMB_IRQHandler                                                      
+HRTIM1_TIMC_IRQHandler                                                      
+HRTIM1_TIMD_IRQHandler                                                      
+HRTIM1_TIME_IRQHandler                                                      
+HRTIM1_FLT_IRQHandler 
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler                                                                
+DFSDM1_FLT2_IRQHandler                                                                
+DFSDM1_FLT3_IRQHandler                                                                                                                                
+SAI3_IRQHandler                                                                    
+SWPMI1_IRQHandler                                                 
+TIM15_IRQHandler                                                                   
+TIM16_IRQHandler                                                                    
+TIM17_IRQHandler                                                                  
+MDIOS_WKUP_IRQHandler                                                              
+MDIOS_IRQHandler                                                                    
+JPEG_IRQHandler                                                                      
+MDMA_IRQHandler                                                                                                                                            
+SDMMC2_IRQHandler                                                                  
+HSEM1_IRQHandler                                                                                                                                       
+ADC3_IRQHandler                                                                       
+DMAMUX2_OVR_IRQHandler                                                            
+BDMA_Channel0_IRQHandler                                                     
+BDMA_Channel1_IRQHandler                                                     
+BDMA_Channel2_IRQHandler                                                     
+BDMA_Channel3_IRQHandler                                                     
+BDMA_Channel4_IRQHandler                                                    
+BDMA_Channel5_IRQHandler                                                     
+BDMA_Channel6_IRQHandler                                                     
+BDMA_Channel7_IRQHandler                                                    
+COMP1_IRQHandler                                                                    
+LPTIM2_IRQHandler                                                                
+LPTIM3_IRQHandler                                                                 
+LPTIM4_IRQHandler                                                                 
+LPTIM5_IRQHandler                                                                 
+LPUART1_IRQHandler                                                                                                                         
+CRS_IRQHandler
+ECC_IRQHandler                                                            
+SAI4_IRQHandler      
+WAKEUP_PIN_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/stm32h743.sct b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/stm32h743.sct
new file mode 100644
index 00000000..f1304012
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/stm32h743.sct
@@ -0,0 +1,19 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00020000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00020000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+   .ANY (+XO)
+  }
+  RW_IRAM1 0x20000000 0x00020000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_IRAM2 0x24000000 0x00080000  {
+   .ANY (+RW +ZI)
+  }
+}
+
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/usbd_bulk.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/usbd_bulk.c
new file mode 100644
index 00000000..0a6a001c
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/usbd_bulk.c
@@ -0,0 +1,400 @@
+/**
+  ******************************************************************************
+  * @file    usbd_bulk.c
+  * @author  MCD Application Team
+  * @version V2.4.2
+  * @date    11-December-2015
+  * @brief   This file provides the high layer firmware functions to manage a
+  *          USB bulk device.
+  *                                  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbd_bulk.h"
+#include "usbd_desc.h"
+#include "usbd_ctlreq.h"
+
+
+/** @addtogroup STM32_USB_DEVICE_LIBRARY
+  * @{
+  */
+
+
+/** @defgroup USBD_Bulk
+  * @brief usbd core module
+  * @{
+  */ 
+
+/** @defgroup USBD_Bulk_Private_TypesDefinitions
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup USBD_Bulk_Private_Defines
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup USBD_Bulk_Private_Macros
+  * @{
+  */ 
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup USBD_Bulk_Private_FunctionPrototypes
+  * @{
+  */
+extern void UsbReceivePipeBulkOUT(uint8_t epnum);
+extern void UsbTransmitPipeBulkIN(void);
+
+
+static uint8_t  USBD_Bulk_Init (USBD_HandleTypeDef *pdev,
+                                uint8_t cfgidx);
+
+static uint8_t  USBD_Bulk_DeInit (USBD_HandleTypeDef *pdev,
+                                  uint8_t cfgidx);
+
+static uint8_t  USBD_Bulk_Setup (USBD_HandleTypeDef *pdev,
+                                 USBD_SetupReqTypedef *req);
+
+static uint8_t  USBD_Bulk_DataIn (USBD_HandleTypeDef *pdev,
+                                  uint8_t epnum);
+
+static uint8_t  USBD_Bulk_DataOut (USBD_HandleTypeDef *pdev,
+                                  uint8_t epnum);
+
+static uint8_t USBD_Bulk_SOF (USBD_HandleTypeDef *pdev);
+
+static uint8_t  *USBD_Bulk_GetFSCfgDesc (uint16_t *length);
+
+uint8_t  *USBD_Bulk_GetDeviceQualifierDescriptor (uint16_t *length);
+
+/* USB Standard Device Descriptor */
+__ALIGN_BEGIN static uint8_t USBD_Bulk_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END =
+{
+  USB_LEN_DEV_QUALIFIER_DESC,
+  USB_DESC_TYPE_DEVICE_QUALIFIER,
+  0x00,
+  0x02,
+  0x00,
+  0x00,
+  0x00,
+  0x40,
+  0x01,
+  0x00,
+};
+
+/**
+  * @}
+  */ 
+
+/** @defgroup USBD_Bulk_Private_Variables
+  * @{
+  */ 
+#if defined ( __ICCARM__ ) /* IAR Compiler */
+  #pragma data_alignment=4
+#endif /* defined ( __ICCARM__ ) */
+__ALIGN_BEGIN static volatile uint32_t  usbd_bulk_AltSet  __ALIGN_END = 0;
+__ALIGN_BEGIN uint8_t USB_Rx_Buffer[BULK_DATA_MAX_PACKET_SIZE] __ALIGN_END ;
+
+
+/* Bulk interface class callbacks structure */
+USBD_ClassTypeDef  USBD_Bulk =
+{
+  USBD_Bulk_Init,
+  USBD_Bulk_DeInit,
+  USBD_Bulk_Setup,
+  NULL,
+  NULL,
+  USBD_Bulk_DataIn,
+  USBD_Bulk_DataOut,
+  USBD_Bulk_SOF,
+  NULL,
+  NULL,     
+  NULL,
+  USBD_Bulk_GetFSCfgDesc,
+  NULL,
+  USBD_Bulk_GetDeviceQualifierDescriptor,
+};
+
+/* USB Bulk device Configuration Descriptor */
+__ALIGN_BEGIN uint8_t USBD_Bulk_CfgFSDesc[USB_BULK_CONFIG_DESC_SIZ] __ALIGN_END =
+{
+  /*Configuration Descriptor*/
+  0x09,   /* bLength: Configuration Descriptor size */
+  USB_DESC_TYPE_CONFIGURATION,      /* bDescriptorType: Configuration */
+  USB_BULK_CONFIG_DESC_SIZ,                /* wTotalLength:no of returned bytes */
+  0x00,
+  0x01,   /* bNumInterfaces: 1 interface */
+  0x01,   /* bConfigurationValue: Configuration value */
+  0x00,   /* iConfiguration: Index of string descriptor describing the configuration */
+  0xC0,   /* bmAttributes: self powered */
+  0x32,   /* MaxPower 100 mA */
+  
+  /*---------------------------------------------------------------------------*/
+  
+  /*Interface Descriptor */
+  0x09,   /* bLength: Interface Descriptor size */
+  USB_DESC_TYPE_INTERFACE,  /* bDescriptorType: Interface */
+  /* Interface descriptor type */
+  0x00,   /* bInterfaceNumber: Number of Interface */
+  0x00,   /* bAlternateSetting: Alternate setting */
+  0x02,   /* bNumEndpoints: One endpoints used */
+  0xFF,   /* bInterfaceClass: vendor specific */
+  0x00,   /* bInterfaceSubClass  */
+  0x00,   /* bInterfaceProtocol */
+  0x00,   /* iInterface: */
+
+  /*Endpoint IN Descriptor*/
+  0x07,   /* bLength: Endpoint Descriptor size */
+  USB_DESC_TYPE_ENDPOINT,      /* bDescriptorType: Endpoint */
+  BULK_IN_EP,                         /* bEndpointAddress */
+  0x02,                              /* bmAttributes: Bulk */
+  LOBYTE(BULK_DATA_MAX_PACKET_SIZE),  /* wMaxPacketSize: */
+  HIBYTE(BULK_DATA_MAX_PACKET_SIZE),
+  0xFF,                               /* bInterval: ignore for Bulk transfer */
+  
+  /*Endpoint OUT Descriptor*/
+  0x07,   /* bLength: Endpoint Descriptor size */
+  USB_DESC_TYPE_ENDPOINT,      /* bDescriptorType: Endpoint */
+  BULK_OUT_EP,                        /* bEndpointAddress */
+  0x02,                              /* bmAttributes: Bulk */
+  LOBYTE(BULK_DATA_MAX_PACKET_SIZE),  /* wMaxPacketSize: */
+  HIBYTE(BULK_DATA_MAX_PACKET_SIZE),
+  0xFF                              /* bInterval: ignore for Bulk transfer */
+} ;
+
+
+/**
+  * @}
+  */ 
+
+/** @defgroup USBD_Bulk_Private_Functions
+  * @{
+  */ 
+
+/**
+  * @brief  USBD_Bulk_Init
+  *         Initialize the Bulk interface
+  * @param  pdev: device instance
+  * @param  cfgidx: Configuration index
+  * @retval status
+  */
+static uint8_t  USBD_Bulk_Init (USBD_HandleTypeDef *pdev,
+                                uint8_t cfgidx)
+{
+  uint8_t ret = 0;
+  
+  /* Open EP IN */
+  USBD_LL_OpenEP(pdev,
+                 BULK_IN_EP,
+                 USBD_EP_TYPE_BULK,
+                 BULK_DATA_FS_IN_PACKET_SIZE);
+
+  /* Open EP OUT */
+  USBD_LL_OpenEP(pdev,
+                 BULK_OUT_EP,
+                 USBD_EP_TYPE_BULK,
+                 BULK_DATA_FS_OUT_PACKET_SIZE);
+
+  /* Prepare Out endpoint to receive next packet */
+  USBD_LL_PrepareReceive(pdev,
+                         BULK_OUT_EP,
+                         &USB_Rx_Buffer[0],
+                         BULK_DATA_FS_OUT_PACKET_SIZE);
+  
+  return ret;
+}
+
+/**
+  * @brief  USBD_Bulk_DeInit
+  *         DeInitialize the Bulk layer
+  * @param  pdev: device instance
+  * @param  cfgidx: Configuration index
+  * @retval status
+  */
+static uint8_t  USBD_Bulk_DeInit (USBD_HandleTypeDef *pdev,
+                                  uint8_t cfgidx)
+{
+  uint8_t ret = 0;
+  
+  /* Close EP IN */
+  USBD_LL_CloseEP(pdev, BULK_IN_EP);
+  
+  /* lose EP OUT */
+  USBD_LL_CloseEP(pdev, BULK_OUT_EP);
+  
+  return ret;
+}
+
+/**
+  * @brief  USBD_Bulk_Setup
+  *         Handle the bulk specific requests
+  * @param  pdev: instance
+  * @param  req: usb requests
+  * @retval status
+  */
+static uint8_t  USBD_Bulk_Setup (USBD_HandleTypeDef *pdev,
+                                 USBD_SetupReqTypedef *req)
+{
+  uint16_t len=USB_BULK_DESC_SIZ;
+  uint8_t  *pbuf=USBD_Bulk_CfgFSDesc + 9;
+
+  switch (req->bmRequest & USB_REQ_TYPE_MASK)
+  {
+  case USB_REQ_TYPE_STANDARD:
+    switch (req->bRequest)
+    {
+    case USB_REQ_GET_DESCRIPTOR :
+      if ( (req->wValue >> 8) == BULK_DESCRIPTOR_TYPE)
+      {
+        pbuf = USBD_Bulk_CfgFSDesc + 9 + (9 * USBD_MAX_NUM_INTERFACES);
+        len = MIN(USB_BULK_DESC_SIZ , req->wLength);
+        
+      }
+      USBD_CtlSendData (pdev, pbuf, len);
+      break;
+
+    case USB_REQ_GET_INTERFACE :
+      USBD_CtlSendData (pdev,
+                        (uint8_t *)&usbd_bulk_AltSet,
+                        1);
+      break;
+      
+    case USB_REQ_SET_INTERFACE :
+      if ((uint8_t)(req->wValue) < USBD_MAX_NUM_INTERFACES)
+      {
+        usbd_bulk_AltSet = (uint8_t)(req->wValue);
+      }
+      else
+      {
+        /* Call the error management function (command will be nacked */
+        USBD_CtlError (pdev, req);
+      }
+      break;
+    }
+ 
+  default: 
+    break;
+  }
+  return USBD_OK;
+}
+
+/**
+  * @brief  USBD_Bulk_DataIn
+  *         Data sent on non-control IN endpoint
+  * @param  pdev: device instance
+  * @param  epnum: endpoint number
+  * @retval status
+  */
+static uint8_t  USBD_Bulk_DataIn (USBD_HandleTypeDef *pdev, uint8_t epnum)
+{
+  /* endpoint finished the previous transmission so see if more data is left */
+  UsbTransmitPipeBulkIN();
+  return USBD_OK;
+}
+
+/**
+  * @brief  USBD_Bulk_DataOut
+  *         Data received on non-control Out endpoint
+  * @param  pdev: device instance
+  * @param  epnum: endpoint number
+  * @retval status
+  */
+static uint8_t  USBD_Bulk_DataOut (USBD_HandleTypeDef *pdev, uint8_t epnum)
+{
+  /* read the data from the bulk OUT pipe */
+  UsbReceivePipeBulkOUT(epnum);
+  return USBD_OK;
+}
+
+/**
+  * @brief  USBD_Bulk_SOF
+  *         Start Of Frame event management
+  * @param  pdev: device instance
+  * @retval status
+  */
+static uint8_t USBD_Bulk_SOF (USBD_HandleTypeDef *pdev)
+{
+  if (pdev->dev_state == USBD_STATE_CONFIGURED )
+  {
+    /* Check the data to be sent through IN pipe */
+    UsbTransmitPipeBulkIN();
+  }
+  return USBD_OK;
+
+}
+
+/**
+  * @brief  USBD_Bulk_GetFSCfgDesc
+  *         Return configuration descriptor
+  * @param  speed : current device speed
+  * @param  length : pointer data length
+  * @retval pointer to descriptor buffer
+  */
+static uint8_t  *USBD_Bulk_GetFSCfgDesc (uint16_t *length)
+{
+  *length = sizeof (USBD_Bulk_CfgFSDesc);
+  return USBD_Bulk_CfgFSDesc;
+}
+
+/**
+* @brief  DeviceQualifierDescriptor 
+*         return Device Qualifier descriptor
+* @param  length : pointer data length
+* @retval pointer to descriptor buffer
+*/
+uint8_t  *USBD_Bulk_GetDeviceQualifierDescriptor (uint16_t *length)
+{
+  *length = sizeof (USBD_Bulk_DeviceQualifierDesc);
+  return USBD_Bulk_DeviceQualifierDesc;
+}
+
+/**
+  * @brief  USBD_Bulk_GetRxBufferPtr
+  * @retval Pointer to reception buffer.
+  */
+uint8_t * USBD_Bulk_GetRxBufferPtr(void)
+{
+  return &USB_Rx_Buffer[0];
+}
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/usbd_bulk.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/usbd_bulk.h
new file mode 100644
index 00000000..ee1d83de
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/usbd_bulk.h
@@ -0,0 +1,113 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    usbd_cdc.h
+  * @author  MCD Application Team
+  * @brief   header file for the usbd_bulk.c file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      http://www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_BULK_H
+#define __USB_BULK_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include  "usbd_ioreq.h"
+
+/** @addtogroup STM32_USB_DEVICE_LIBRARY
+  * @{
+  */
+
+/** @defgroup usbd_cdc
+  * @brief This file is the Header file for usbd_cdc.c
+  * @{
+  */
+
+
+/** @defgroup usbd_cdc_Exported_Defines
+  * @{
+  */ 
+#define BULK_IN_EP                                  0x81  /* EP1 for data IN */
+#define BULK_OUT_EP                                 0x01  /* EP1 for data OUT */
+
+/* CDC Endpoints parameters: you can fine tune these values depending on the needed baudrates and performance. */
+#define BULK_DATA_MAX_PACKET_SIZE                   64  /* Endpoint IN & OUT Packet size */
+
+#define USB_BULK_CONFIG_DESC_SIZ                    32
+#define USB_BULK_DESC_SIZ                           (32-9)
+
+#define BULK_DESCRIPTOR_TYPE                        0x21
+
+
+#define BULK_DATA_FS_IN_PACKET_SIZE                 BULK_DATA_MAX_PACKET_SIZE
+#define BULK_DATA_FS_OUT_PACKET_SIZE                BULK_DATA_MAX_PACKET_SIZE
+
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup USBD_CORE_Exported_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup USBD_CORE_Exported_Macros
+  * @{
+  */ 
+  
+/**
+  * @}
+  */ 
+
+/** @defgroup USBD_CORE_Exported_Variables
+  * @{
+  */ 
+
+extern USBD_ClassTypeDef   USBD_Bulk;
+/**
+  * @}
+  */ 
+
+/** @defgroup USB_CORE_Exported_Functions
+  * @{
+  */
+uint8_t * USBD_Bulk_GetRxBufferPtr(void);
+/**
+  * @}
+  */ 
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* __USB_BULK_H */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/usbd_conf.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/usbd_conf.c
new file mode 100644
index 00000000..357bb1d2
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/usbd_conf.c
@@ -0,0 +1,591 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : usbd_conf.c
+  * @version        : v1.0_Cube
+  * @brief          : This file implements the board support package for the USB device library
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+#include "stm32h7xx_hal.h"
+#include "usbd_def.h"
+#include "usbd_core.h"
+#include "usbd_bulk.h"
+#include "boot.h"
+#include "usb.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE END PV */
+
+PCD_HandleTypeDef hpcd_USB_OTG_FS;
+
+/* External functions --------------------------------------------------------*/
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* USER CODE BEGIN PFP */
+/* Private function prototypes -----------------------------------------------*/
+USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status);
+
+/* USER CODE END PFP */
+
+/* Private functions ---------------------------------------------------------*/
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/**
+  * @brief  Setup stage callback
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
+#else
+void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup);
+}
+
+/**
+  * @brief  Data Out stage callback.
+  * @param  hpcd: PCD handle
+  * @param  epnum: Endpoint number
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#else
+void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff);
+}
+
+/**
+  * @brief  Data In stage callback.
+  * @param  hpcd: PCD handle
+  * @param  epnum: Endpoint number
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#else
+void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff);
+}
+
+/**
+  * @brief  SOF callback.
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
+#else
+void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData);
+}
+
+/**
+  * @brief  Reset callback.
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
+#else
+void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{ 
+  USBD_SpeedTypeDef speed = USBD_SPEED_FULL;
+
+  if ( hpcd->Init.speed == PCD_SPEED_HIGH)
+  {
+    speed = USBD_SPEED_HIGH;
+  }
+  else if ( hpcd->Init.speed == PCD_SPEED_FULL)
+  {
+    speed = USBD_SPEED_FULL;
+  }
+  else
+  {
+    ASSERT_RT(BLT_FALSE);
+  }
+    /* Set Speed. */
+  USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed);
+
+  /* Reset Device. */
+  USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData);
+}
+
+/**
+  * @brief  Suspend callback.
+  * When Low power mode is enabled the debug cannot be used (IAR, Keil doesn't support it)
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
+#else
+void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  /* Inform USB library that core enters in suspend Mode. */
+  USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData);
+  __HAL_PCD_GATE_PHYCLOCK(hpcd);
+  /* Enter in STOP mode. */
+  /* USER CODE BEGIN 2 */
+  if (hpcd->Init.low_power_enable)
+  {
+    /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */
+    SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
+  }
+  /* Inform application that the USB entered low power mode. */
+  UsbEnterLowPowerModeHook();
+  /* USER CODE END 2 */
+}
+
+/**
+  * @brief  Resume callback.
+  * When Low power mode is enabled the debug cannot be used (IAR, Keil doesn't support it)
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
+#else
+void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  /* USER CODE BEGIN 3 */
+  /* Inform application that the USB left low power mode. */
+  UsbLeaveLowPowerModeHook();
+  /* USER CODE END 3 */
+  USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData);
+}
+
+/**
+  * @brief  ISOOUTIncomplete callback.
+  * @param  hpcd: PCD handle
+  * @param  epnum: Endpoint number
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#else
+void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  USBD_LL_IsoOUTIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum);
+}
+
+/**
+  * @brief  ISOINIncomplete callback.
+  * @param  hpcd: PCD handle
+  * @param  epnum: Endpoint number
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#else
+void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  USBD_LL_IsoINIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum);
+}
+
+/**
+  * @brief  Connect callback.
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
+#else
+void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  /* Configure Low connection state. */
+  UsbConnectHook(BLT_TRUE);
+  /* Inform lower layer. */
+  USBD_LL_DevConnected((USBD_HandleTypeDef*)hpcd->pData);
+}
+
+/**
+  * @brief  Disconnect callback.
+  * @param  hpcd: PCD handle
+  * @retval None
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+static void PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
+#else
+void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+{
+  /* Configure High connection state. */
+  UsbConnectHook(BLT_FALSE);
+  /* Inform lower layer. */
+  USBD_LL_DevDisconnected((USBD_HandleTypeDef*)hpcd->pData);
+}
+
+/*******************************************************************************
+                       LL Driver Interface (USB Device Library --> PCD)
+*******************************************************************************/
+
+/**
+  * @brief  Initializes the low level portion of the device driver.
+  * @param  pdev: Device handle
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)
+{
+  /* Init USB Ip. */
+  if (pdev->id == DEVICE_FS) {
+  /* Link the driver to the stack. */
+  hpcd_USB_OTG_FS.pData = pdev;
+  pdev->pData = &hpcd_USB_OTG_FS;
+  
+  hpcd_USB_OTG_FS.Instance = USB_OTG_FS;
+  hpcd_USB_OTG_FS.Init.dev_endpoints = 9;
+  hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL;
+  hpcd_USB_OTG_FS.Init.dma_enable = DISABLE;
+  hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED;
+  hpcd_USB_OTG_FS.Init.Sof_enable = ENABLE;
+  hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE;
+  hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE;
+  hpcd_USB_OTG_FS.Init.battery_charging_enable = DISABLE;
+  hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE;
+  hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE;
+  if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK)
+  {
+    ASSERT_RT(BLT_FALSE);
+  }
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+  /* Register USB PCD CallBacks */
+  HAL_PCD_RegisterCallback(&hpcd_USB_OTG_FS, HAL_PCD_SOF_CB_ID, PCD_SOFCallback);
+  HAL_PCD_RegisterCallback(&hpcd_USB_OTG_FS, HAL_PCD_SETUPSTAGE_CB_ID, PCD_SetupStageCallback);
+  HAL_PCD_RegisterCallback(&hpcd_USB_OTG_FS, HAL_PCD_RESET_CB_ID, PCD_ResetCallback);
+  HAL_PCD_RegisterCallback(&hpcd_USB_OTG_FS, HAL_PCD_SUSPEND_CB_ID, PCD_SuspendCallback);
+  HAL_PCD_RegisterCallback(&hpcd_USB_OTG_FS, HAL_PCD_RESUME_CB_ID, PCD_ResumeCallback);
+  HAL_PCD_RegisterCallback(&hpcd_USB_OTG_FS, HAL_PCD_CONNECT_CB_ID, PCD_ConnectCallback);
+  HAL_PCD_RegisterCallback(&hpcd_USB_OTG_FS, HAL_PCD_DISCONNECT_CB_ID, PCD_DisconnectCallback);
+
+  HAL_PCD_RegisterDataOutStageCallback(&hpcd_USB_OTG_FS, PCD_DataOutStageCallback);
+  HAL_PCD_RegisterDataInStageCallback(&hpcd_USB_OTG_FS, PCD_DataInStageCallback);
+  HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOOUTIncompleteCallback);
+  HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOINIncompleteCallback);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+  HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_FS, 0x80);
+  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 0, 0x40);
+  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x80);
+  }
+  return USBD_OK;
+}
+
+/**
+  * @brief  De-Initializes the low level portion of the device driver.
+  * @param  pdev: Device handle
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_DeInit(USBD_HandleTypeDef *pdev)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+
+  hal_status = HAL_PCD_DeInit(pdev->pData);
+
+  usb_status =  USBD_Get_USB_Status(hal_status);
+  
+  return usb_status; 
+}
+
+/**
+  * @brief  Starts the low level portion of the device driver. 
+  * @param  pdev: Device handle
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+ 
+  hal_status = HAL_PCD_Start(pdev->pData);
+  
+  usb_status =  USBD_Get_USB_Status(hal_status);     
+  
+  return usb_status;
+}
+
+/**
+  * @brief  Stops the low level portion of the device driver.
+  * @param  pdev: Device handle
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_Stop(USBD_HandleTypeDef *pdev)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+
+  hal_status = HAL_PCD_Stop(pdev->pData);
+  
+  usb_status =  USBD_Get_USB_Status(hal_status);
+ 
+  return usb_status;
+}
+
+/**
+  * @brief  Opens an endpoint of the low level driver.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @param  ep_type: Endpoint type
+  * @param  ep_mps: Endpoint max packet size
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+
+  hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type);
+
+  usb_status =  USBD_Get_USB_Status(hal_status);
+  
+  return usb_status;
+}
+
+/**
+  * @brief  Closes an endpoint of the low level driver.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+  
+  hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr);
+  
+  usb_status =  USBD_Get_USB_Status(hal_status);    
+ 
+  return usb_status;  
+}
+
+/**
+  * @brief  Flushes an endpoint of the Low Level Driver.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_FlushEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+  
+  hal_status = HAL_PCD_EP_Flush(pdev->pData, ep_addr);
+  
+  usb_status =  USBD_Get_USB_Status(hal_status);   
+  
+  return usb_status;  
+}
+
+/**
+  * @brief  Sets a Stall condition on an endpoint of the Low Level Driver.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+  
+  hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr);
+
+  usb_status =  USBD_Get_USB_Status(hal_status);
+  
+  return usb_status;  
+}
+
+/**
+  * @brief  Clears a Stall condition on an endpoint of the Low Level Driver.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+  
+  hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr);
+    
+  usb_status =  USBD_Get_USB_Status(hal_status);  
+  
+  return usb_status; 
+}
+
+/**
+  * @brief  Returns Stall condition.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @retval Stall (1: Yes, 0: No)
+  */
+uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+{
+  PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData;
+  
+  if((ep_addr & 0x80) == 0x80)
+  {
+    return hpcd->IN_ep[ep_addr & 0x7F].is_stall; 
+  }
+  else
+  {
+    return hpcd->OUT_ep[ep_addr & 0x7F].is_stall; 
+  }
+}
+
+/**
+  * @brief  Assigns a USB address to the device.
+  * @param  pdev: Device handle
+  * @param  dev_addr: Device address
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+  
+  hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr);
+  
+  usb_status =  USBD_Get_USB_Status(hal_status);
+  
+  return usb_status;  
+}
+
+/**
+  * @brief  Transmits data over an endpoint.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @param  pbuf: Pointer to data to be sent
+  * @param  size: Data size    
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+
+  hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size);
+  
+  usb_status =  USBD_Get_USB_Status(hal_status); 
+  
+  return usb_status;    
+}
+
+/**
+  * @brief  Prepares an endpoint for reception.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @param  pbuf: Pointer to data to be received
+  * @param  size: Data size
+  * @retval USBD status
+  */
+USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+  USBD_StatusTypeDef usb_status = USBD_OK;
+
+  hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size);
+  
+  usb_status =  USBD_Get_USB_Status(hal_status);   
+  
+  return usb_status; 
+}
+
+/**
+  * @brief  Returns the last transfered packet size.
+  * @param  pdev: Device handle
+  * @param  ep_addr: Endpoint number
+  * @retval Recived Data Size
+  */
+uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+{
+  return HAL_PCD_EP_GetRxCount((PCD_HandleTypeDef*) pdev->pData, ep_addr);
+}
+
+/**
+  * @brief  Delays routine for the USB Device Library.
+  * @param  Delay: Delay in ms
+  * @retval None
+  */
+void USBD_LL_Delay(uint32_t Delay)
+{
+  HAL_Delay(Delay);
+}
+
+/**
+  * @brief  Retuns the USB status depending on the HAL status:
+  * @param  hal_status: HAL status
+  * @retval USB status
+  */
+USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status)
+{
+  USBD_StatusTypeDef usb_status = USBD_OK;
+
+  switch (hal_status)
+  {
+    case HAL_OK :
+      usb_status = USBD_OK;
+    break;
+    case HAL_ERROR :
+      usb_status = USBD_FAIL;
+    break;
+    case HAL_BUSY :
+      usb_status = USBD_BUSY;
+    break;
+    case HAL_TIMEOUT :
+      usb_status = USBD_FAIL;
+    break;
+    default :
+      usb_status = USBD_FAIL;
+    break;
+  }
+  return usb_status;
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/usbd_conf.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/usbd_conf.h
new file mode 100644
index 00000000..cee15fdc
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/usbd_conf.h
@@ -0,0 +1,175 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : usbd_conf.h
+  * @version        : v1.0_Cube
+  * @brief          : Header for usbd_conf.c file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USBD_CONF__H__
+#define __USBD_CONF__H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include "stm32h7xx.h"
+#include "stm32h7xx_hal.h"
+
+/* USER CODE BEGIN INCLUDE */
+
+/* USER CODE END INCLUDE */
+
+/** @addtogroup USBD_OTG_DRIVER
+  * @{
+  */
+
+/** @defgroup USBD_CONF USBD_CONF
+  * @brief Configuration file for Usb otg low level driver.
+  * @{
+  */
+
+/** @defgroup USBD_CONF_Exported_Variables USBD_CONF_Exported_Variables
+  * @brief Public variables.
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_CONF_Exported_Defines USBD_CONF_Exported_Defines
+  * @brief Defines for configuration of the Usb device.
+  * @{
+  */
+
+/*---------- -----------*/
+#define USBD_MAX_NUM_INTERFACES     1U
+/*---------- -----------*/
+#define USBD_MAX_NUM_CONFIGURATION     1U
+/*---------- -----------*/
+#define USBD_MAX_STR_DESC_SIZ     512U
+/*---------- -----------*/
+#define USBD_DEBUG_LEVEL     0U
+/*---------- -----------*/
+#define USBD_LPM_ENABLED     0U
+/*---------- -----------*/
+#define USBD_SELF_POWERED     1U
+
+/****************************************/
+/* #define for FS and HS identification */
+#define DEVICE_FS 		0
+#define DEVICE_HS 		1
+
+/* Inform USB core that a full speed device is used. */
+#define USE_USB_FS
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_CONF_Exported_Macros USBD_CONF_Exported_Macros
+  * @brief Aliases.
+  * @{
+  */
+
+/* Memory management macros */
+
+/** Alias for memory allocation. */
+#define USBD_malloc         malloc
+
+/** Alias for memory release. */
+#define USBD_free           free
+
+/** Alias for memory set. */
+#define USBD_memset         memset
+
+/** Alias for memory copy. */
+#define USBD_memcpy         memcpy
+
+/** Alias for delay. */
+#define USBD_Delay          HAL_Delay
+
+/* DEBUG macros */
+
+#if (USBD_DEBUG_LEVEL > 0)
+#define USBD_UsrLog(...)    printf(__VA_ARGS__);\
+                            printf("\n");
+#else
+#define USBD_UsrLog(...)
+#endif
+
+#if (USBD_DEBUG_LEVEL > 1)
+
+#define USBD_ErrLog(...)    printf("ERROR: ") ;\
+                            printf(__VA_ARGS__);\
+                            printf("\n");
+#else
+#define USBD_ErrLog(...)
+#endif
+
+#if (USBD_DEBUG_LEVEL > 2)
+#define USBD_DbgLog(...)    printf("DEBUG : ") ;\
+                            printf(__VA_ARGS__);\
+                            printf("\n");
+#else
+#define USBD_DbgLog(...)
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_CONF_Exported_Types USBD_CONF_Exported_Types
+  * @brief Types.
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_CONF_Exported_FunctionsPrototype USBD_CONF_Exported_FunctionsPrototype
+  * @brief Declaration of public functions for Usb device.
+  * @{
+  */
+
+/* Exported functions -------------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USBD_CONF__H__ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/usbd_desc.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/usbd_desc.c
new file mode 100644
index 00000000..464ac5cc
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/usbd_desc.c
@@ -0,0 +1,395 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : usbd_desc.c
+  * @version        : v1.0_Cube
+  * @brief          : This file implements the USB device descriptors.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbd_core.h"
+#include "usbd_desc.h"
+#include "usbd_conf.h"
+
+/* USER CODE BEGIN INCLUDE */
+
+/* USER CODE END INCLUDE */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE END PV */
+
+/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
+  * @{
+  */
+
+/** @addtogroup USBD_DESC
+  * @{
+  */
+
+/** @defgroup USBD_DESC_Private_TypesDefinitions USBD_DESC_Private_TypesDefinitions
+  * @brief Private types.
+  * @{
+  */
+
+/* USER CODE BEGIN PRIVATE_TYPES */
+
+/* USER CODE END PRIVATE_TYPES */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Private_Defines USBD_DESC_Private_Defines
+  * @brief Private defines.
+  * @{
+  */
+
+#define USBD_VID     0x1d50
+#define USBD_LANGID_STRING     1033
+#define USBD_MANUFACTURER_STRING     "OpenBLT User"
+#define USBD_PID_FS     0x60ac
+#define USBD_PRODUCT_STRING_FS     "WinUSB Bulk Device"
+#define USBD_CONFIGURATION_STRING_FS     "Default"
+#define USBD_INTERFACE_STRING_FS     "WinUSB Bulk Interface"
+
+/* USER CODE BEGIN PRIVATE_DEFINES */
+
+/* USER CODE END PRIVATE_DEFINES */
+
+/**
+  * @}
+  */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/** @defgroup USBD_DESC_Private_Macros USBD_DESC_Private_Macros
+  * @brief Private macros.
+  * @{
+  */
+
+/* USER CODE BEGIN PRIVATE_MACRO */
+
+/* USER CODE END PRIVATE_MACRO */
+
+/**
+  * @}
+  */
+  
+/** @defgroup USBD_DESC_Private_FunctionPrototypes USBD_DESC_Private_FunctionPrototypes
+  * @brief Private functions declaration.
+  * @{
+  */
+  
+static void Get_SerialNum(void);
+static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len);
+  
+/**
+  * @}
+  */  
+  
+
+/** @defgroup USBD_DESC_Private_FunctionPrototypes USBD_DESC_Private_FunctionPrototypes
+  * @brief Private functions declaration for FS.
+  * @{
+  */
+
+uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Private_Variables USBD_DESC_Private_Variables
+  * @brief Private variables.
+  * @{
+  */
+
+USBD_DescriptorsTypeDef FS_Desc =
+{
+  USBD_FS_DeviceDescriptor
+, USBD_FS_LangIDStrDescriptor
+, USBD_FS_ManufacturerStrDescriptor
+, USBD_FS_ProductStrDescriptor
+, USBD_FS_SerialStrDescriptor
+, USBD_FS_ConfigStrDescriptor
+, USBD_FS_InterfaceStrDescriptor
+};
+
+#if defined ( __ICCARM__ ) /* IAR Compiler */
+  #pragma data_alignment=4
+#endif /* defined ( __ICCARM__ ) */
+/** USB standard device descriptor. */
+__ALIGN_BEGIN uint8_t USBD_FS_DeviceDesc[USB_LEN_DEV_DESC] __ALIGN_END =
+{
+  0x12,                       /*bLength */
+  USB_DESC_TYPE_DEVICE,       /*bDescriptorType*/
+  0x00,                       /*bcdUSB */
+  0x02,
+  0x00,                       /*bDeviceClass*/
+  0x00,                       /*bDeviceSubClass*/
+  0x00,                       /*bDeviceProtocol*/
+  USB_MAX_EP0_SIZE,           /*bMaxPacketSize*/
+  LOBYTE(USBD_VID),           /*idVendor*/
+  HIBYTE(USBD_VID),           /*idVendor*/
+  LOBYTE(USBD_PID_FS),        /*idProduct*/
+  HIBYTE(USBD_PID_FS),        /*idProduct*/
+  0x00,                       /*bcdDevice rel. 2.00*/
+  0x02,
+  USBD_IDX_MFC_STR,           /*Index of manufacturer  string*/
+  USBD_IDX_PRODUCT_STR,       /*Index of product string*/
+  USBD_IDX_SERIAL_STR,        /*Index of serial number string*/
+  USBD_MAX_NUM_CONFIGURATION  /*bNumConfigurations*/
+};
+
+/* USB_DeviceDescriptor */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Private_Variables USBD_DESC_Private_Variables
+  * @brief Private variables.
+  * @{
+  */
+
+#if defined ( __ICCARM__ ) /* IAR Compiler */
+  #pragma data_alignment=4
+#endif /* defined ( __ICCARM__ ) */
+
+/** USB lang indentifier descriptor. */
+__ALIGN_BEGIN uint8_t USBD_LangIDDesc[USB_LEN_LANGID_STR_DESC] __ALIGN_END =
+{
+     USB_LEN_LANGID_STR_DESC,
+     USB_DESC_TYPE_STRING,
+     LOBYTE(USBD_LANGID_STRING),
+     HIBYTE(USBD_LANGID_STRING)
+};
+
+#if defined ( __ICCARM__ ) /* IAR Compiler */
+  #pragma data_alignment=4
+#endif /* defined ( __ICCARM__ ) */
+/* Internal string descriptor. */
+__ALIGN_BEGIN uint8_t USBD_StrDesc[USBD_MAX_STR_DESC_SIZ] __ALIGN_END;
+
+#if defined ( __ICCARM__ ) /*!< IAR Compiler */
+  #pragma data_alignment=4   
+#endif
+__ALIGN_BEGIN uint8_t USBD_StringSerial[USB_SIZ_STRING_SERIAL] __ALIGN_END = {
+  USB_SIZ_STRING_SERIAL,
+  USB_DESC_TYPE_STRING,
+};
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Private_Functions USBD_DESC_Private_Functions
+  * @brief Private functions.
+  * @{
+  */
+
+/**
+  * @brief  Return the device descriptor
+  * @param  speed : Current device speed
+  * @param  length : Pointer to data length variable
+  * @retval Pointer to descriptor buffer
+  */
+uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+{
+  UNUSED(speed);
+  *length = sizeof(USBD_FS_DeviceDesc);
+  return USBD_FS_DeviceDesc;
+}
+
+/**
+  * @brief  Return the LangID string descriptor
+  * @param  speed : Current device speed
+  * @param  length : Pointer to data length variable
+  * @retval Pointer to descriptor buffer
+  */
+uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+{
+  UNUSED(speed);
+  *length = sizeof(USBD_LangIDDesc);
+  return USBD_LangIDDesc;
+}
+
+/**
+  * @brief  Return the product string descriptor
+  * @param  speed : Current device speed
+  * @param  length : Pointer to data length variable
+  * @retval Pointer to descriptor buffer
+  */
+uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+{
+  if(speed == 0)
+  {
+    USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length);
+  }
+  else
+  {
+    USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length);
+  }
+  return USBD_StrDesc;
+}
+
+/**
+  * @brief  Return the manufacturer string descriptor
+  * @param  speed : Current device speed
+  * @param  length : Pointer to data length variable
+  * @retval Pointer to descriptor buffer
+  */
+uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+{
+  UNUSED(speed);
+  USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length);
+  return USBD_StrDesc;
+}
+
+/**
+  * @brief  Return the serial number string descriptor
+  * @param  speed : Current device speed
+  * @param  length : Pointer to data length variable
+  * @retval Pointer to descriptor buffer
+  */
+uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+{
+  UNUSED(speed);
+  *length = USB_SIZ_STRING_SERIAL;
+
+  /* Update the serial number string descriptor with the data from the unique
+   * ID */
+  Get_SerialNum();
+  /* USER CODE BEGIN USBD_FS_SerialStrDescriptor */
+  
+  /* USER CODE END USBD_FS_SerialStrDescriptor */
+  return (uint8_t *) USBD_StringSerial;
+}
+
+/**
+  * @brief  Return the configuration string descriptor
+  * @param  speed : Current device speed
+  * @param  length : Pointer to data length variable
+  * @retval Pointer to descriptor buffer
+  */
+uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+{
+  if(speed == USBD_SPEED_HIGH)
+  {
+    USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length);
+  }
+  else
+  {
+    USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length);
+  }
+  return USBD_StrDesc;
+}
+
+/**
+  * @brief  Return the interface string descriptor
+  * @param  speed : Current device speed
+  * @param  length : Pointer to data length variable
+  * @retval Pointer to descriptor buffer
+  */
+uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
+{
+  if(speed == 0)
+  {
+    USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length);
+  }
+  else
+  {
+    USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length);
+  }
+  return USBD_StrDesc;
+}
+
+/**
+  * @brief  Create the serial number string descriptor 
+  * @param  None 
+  * @retval None
+  */
+static void Get_SerialNum(void)
+{
+  uint32_t deviceserial0, deviceserial1, deviceserial2;
+
+  deviceserial0 = *(uint32_t *) DEVICE_ID1;
+  deviceserial1 = *(uint32_t *) DEVICE_ID2;
+  deviceserial2 = *(uint32_t *) DEVICE_ID3;
+
+  deviceserial0 += deviceserial2;
+
+  if (deviceserial0 != 0)
+  {
+    IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8);
+    IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4);
+  }
+}
+
+/**
+  * @brief  Convert Hex 32Bits value into char 
+  * @param  value: value to convert
+  * @param  pbuf: pointer to the buffer 
+  * @param  len: buffer length
+  * @retval None
+  */
+static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len)
+{
+  uint8_t idx = 0;
+
+  for (idx = 0; idx < len; idx++)
+  {
+    if (((value >> 28)) < 0xA)
+    {
+      pbuf[2 * idx] = (value >> 28) + '0';
+    }
+    else
+    {
+      pbuf[2 * idx] = (value >> 28) + 'A' - 10;
+    }
+
+    value = value << 4;
+
+    pbuf[2 * idx + 1] = 0;
+  }
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/usbd_desc.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/usbd_desc.h
new file mode 100644
index 00000000..0c6619fd
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Boot/usbd_desc.h
@@ -0,0 +1,145 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : usbd_desc.c
+  * @version        : v1.0_Cube
+  * @brief          : Header for usbd_conf.c file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */  
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USBD_DESC__C__
+#define __USBD_DESC__C__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbd_def.h"
+
+/* USER CODE BEGIN INCLUDE */
+
+/* USER CODE END INCLUDE */
+
+/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
+  * @{
+  */
+
+/** @defgroup USBD_DESC USBD_DESC
+  * @brief Usb device descriptors module.
+  * @{
+  */
+  
+/** @defgroup USBD_DESC_Exported_Constants USBD_DESC_Exported_Constants
+  * @brief Constants.
+  * @{
+  */
+#define         DEVICE_ID1          (UID_BASE)
+#define         DEVICE_ID2          (UID_BASE + 0x4)
+#define         DEVICE_ID3          (UID_BASE + 0x8)
+
+#define  USB_SIZ_STRING_SERIAL       0x1A
+
+/* USER CODE BEGIN EXPORTED_CONSTANTS */
+
+/* USER CODE END EXPORTED_CONSTANTS */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Exported_Defines USBD_DESC_Exported_Defines
+  * @brief Defines.
+  * @{
+  */
+
+/* USER CODE BEGIN EXPORTED_DEFINES */
+
+/* USER CODE END EXPORTED_DEFINES */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Exported_TypesDefinitions USBD_DESC_Exported_TypesDefinitions
+  * @brief Types.
+  * @{
+  */
+
+/* USER CODE BEGIN EXPORTED_TYPES */
+
+/* USER CODE END EXPORTED_TYPES */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Exported_Macros USBD_DESC_Exported_Macros
+  * @brief Aliases.
+  * @{
+  */
+
+/* USER CODE BEGIN EXPORTED_MACRO */
+
+/* USER CODE END EXPORTED_MACRO */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Exported_Variables USBD_DESC_Exported_Variables
+  * @brief Public variables.
+  * @{
+  */
+
+/** Descriptor for the Usb device. */
+extern USBD_DescriptorsTypeDef FS_Desc;
+
+/* USER CODE BEGIN EXPORTED_VARIABLES */
+
+/* USER CODE END EXPORTED_VARIABLES */
+
+/**
+  * @}
+  */
+
+/** @defgroup USBD_DESC_Exported_FunctionsPrototype USBD_DESC_Exported_FunctionsPrototype
+  * @brief Public functions declaration.
+  * @{
+  */
+
+/* USER CODE BEGIN EXPORTED_FUNCTIONS */
+
+/* USER CODE END EXPORTED_FUNCTIONS */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USBD_DESC__C__ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/bin/demoprog_stm32h743.axf b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/bin/demoprog_stm32h743.axf
new file mode 100644
index 00000000..079e9527
Binary files /dev/null and b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/bin/demoprog_stm32h743.axf differ
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/bin/demoprog_stm32h743.srec b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/bin/demoprog_stm32h743.srec
new file mode 100644
index 00000000..fd240729
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/bin/demoprog_stm32h743.srec
@@ -0,0 +1,1005 @@
+S31508020000F80700243D030208490302084B030208C5
+S315080200104D0302084F0302085103020800000000BC
+S315080200200000000000000000000000005303020860
+S315080200305503020800000000570302086D23020850
+S315080200405B0302085B0302085B0302085B03020800
+S315080200505B0302085B0302085B0302085B030208F0
+S315080200605B0302085B0302085B0302085B030208E0
+S315080200705B0302085B0302085B0302085B030208D0
+S315080200805B0302085B0302085B0302085B030208C0
+S315080200905B0302085B0302085B0302085B030208B0
+S315080200A05B0302085B0302085B0302085B030208A0
+S315080200B05B0302085B0302085B0302085B03020890
+S315080200C05B0302085B0302085B0302085B03020880
+S315080200D05B0302085B0302085B0302085B03020870
+S315080200E05B0302085B030208000000005B030208C8
+S315080200F05B0302085B0302085B0302085B03020850
+S315080201005B0302085B0302085B0302085B0302083F
+S315080201105B0302085B0302085B0302085B0302082F
+S315080201205B0302085B0302085B0302085B0302081F
+S315080201305B0302085B0302085B0302085B0302080F
+S31508020140000000000000000000000000000000009F
+S315080201505B0302085B0302085B0302085B030208EF
+S315080201605B0302085B0302085B0302085B030208DF
+S315080201705B0302085B0302085B0302080000000037
+S315080201805B0302085B0302085B0302085B030208BF
+S315080201905B0302085B0302085B0302085B030208AF
+S315080201A05B0302085B0302085B0302085B0302089F
+S315080201B05B0302085B0302085B0302085B0302088F
+S315080201C05B0302085B0302085B0302085B0302087F
+S315080201D05B0302085B0302085B0302085B0302086F
+S315080201E05B0302085B0302085B0302085B0302085F
+S315080201F05B0302085B0302085B0302085B0302084F
+S315080202005B0302085B0302085B0302085B0302083E
+S315080202105B0302085B0302085B0302085B0302082E
+S315080202205B0302085B0302085B0302080000000086
+S315080202305B0302085B030208000000005B03020876
+S315080202405B0302085B0302085B0302085B030208FE
+S315080202505B0302085B0302085B0302085B030208EE
+S315080202605B0302085B0302085B0302085B030208DE
+S315080202705B0302085B0302085B0302080000000036
+S315080202805B0302085B0302085B0302080000000026
+S31508020290000000005B030208EE11AA5500F002F8FE
+S315080202A000F03CF80AA090E8000C82448344AAF1C4
+S315080202B00107DA4501D100F031F8AFF2090EBAE8C2
+S315080202C00F0013F0010F18BFFB1A43F0010318477A
+S315080202D0AC3B0000CC3B0000103A24BF78C878C17A
+S315080202E0FAD8520724BF30C830C144BF04680C602C
+S315080202F0704700000023002400250026103A28BF74
+S3150802030078C1FBD8520728BF30C148BF0B60704777
+S315080203101FB503F066FD1FBD10B510BD00F005F947
+S315080203201146FFF7F5FF03F053FD00F023F903B476
+S31508020330FFF7F2FF03BC00F02BF900000A488546D6
+S315080203400A4880470A480047FEE7FEE7FEE7FEE757
+S31508020350FEE7FEE7FEE7FEE7FEE7FEE70548064993
+S31508020360064A074B70470000F8070024C52502080D
+S315080203709D020208F8010024F8070024F803002465
+S31508020380F803002453EA020C00F069802DE9F04BC9
+S315080203904FF00006002B1FBFB3FA83F503FA05F4E4
+S315080203A024FA05F65E4012BF1643B2FA82F502FA3D
+S315080203B005F4C5F120051EBF22FA05FC44EA0C0421
+S315080203C0203556EA044C4FEA144418BF641C4FF011
+S315080203D000084FF00009904271EB030C39D300294B
+S315080203E019BFB1FA81F701FA07F6B0FA80F700FAEF
+S315080203F007F6C7F120071EBF20FA07FC46EA0C06D5
+S315080204002037B6FBF4FCA7EB0507103F07F01F0BD6
+S31508020410CBF120060CFA0BFB2CFA06F644BFB346C0
+S315080204200026202FA4BF5E464FF0000B5BEA060C9F
+S3150802043008BF4FF0010B19EB0B09ABFB027C48EB2B
+S315080204400608C01B06FB02CC0BFB03CC71EB0C01A6
+S31508020450C1E70B46024641464846BDE8F08B13B54E
+S315080204604FF000004FF00001AFF30080BDE81C40DA
+S31508020470704710B5203AC0F00B80B1E81850203A00
+S31508020480A0E81850B1E81850A0E81850BFF4F5AF24
+S315080204905FEA027C24BFB1E81850A0E8185044BFAE
+S315080204A018C918C0BDE810405FEA827C24BF51F81B
+S315080204B0043B40F8043B08BF7047D20728BF31F80F
+S315080204C0023B48BF11F8012B28BF20F8023B48BF60
+S315080204D000F8012B70474FF0000200B51346944608
+S315080204E09646203922BFA0E80C50A0E80C50B1F17C
+S315080204F02001BFF4F7AF090728BFA0E80C5048BF90
+S315080205000CC05DF804EB890028BF40F8042B08BF2D
+S31508020510704748BF20F8022B11F0804F18BF00F829
+S31508020520012B7047704770477047754600F02CF8E4
+S31508020530AE4605006946534620F00700854618B0C0
+S3150802054020B5FFF70BFFBDE820404FF000064FF03D
+S3150802055000074FF000084FF0000B21F00701AC46E8
+S31508020560ACE8C009ACE8C009ACE8C009ACE8C00907
+S315080205708D46704710B50446AFF300802046BDE8A5
+S315080205801040FFF7D4BE00000048704794010024CB
+S3150802059001491820ABBEFEE726000200704700009C
+S315080205A0BFF34F8F05480168054A01F4E06111431C
+S315080205B00160BFF34F8F00BFFDE700000CED00E0BE
+S315080205C00400FA0570B58CB040F26766002401256E
+S315080205D01148402100F038FA30B10F48402102AAEA
+S315080205E06B4600F03FFA0546002D12D10298B0423A
+S315080205F002D1039800B90124012C0AD10598C0F347
+S3150802060007409DF80010FF2903D1022801D1FFF700
+S31508020610C7FF0CB070BD0000F400002470B58CB0A2
+S3150802062000240B940A94099440F2676609AB0AAA55
+S315080206300BA94FF4FA7000F0A1F820481E49016090
+S315080206408460C4600125057444748474BDF82C1052
+S31508020650416185619DF82810C1619DF824100162E7
+S3150802066045628562C562056344638563C46305643E
+S31508020670042141648464C164046541658465C46572
+S3150802068004664466816600F0ADFA01940294039505
+S31508020690049505960696079401A9084800F078F984
+S315080206A00222064801231146009500F0B5F90348CF
+S315080206B000F0CDFB0CB070BD00A00040F400002491
+S315080206C010B500F00BF8BDE81040FFF77BBF10B578
+S315080206D000F03EF8BDE81040FFF7A0BF70B51A4C0F
+S315080206E000251A4E607800280ED020783044401C27
+S315080206F001F02EFE012817D001F0B0FF61686431BF
+S31508020700884200D9657070BD104801F021FE0128A3
+S31508020710F9D13078401E3F28F5D801F09FFF606076
+S3150802072001206070257070BD2078401CC0B2207010
+S3150802073031788142F7D165707178FF29F3D10228A1
+S31508020740F1D1FFF72DFF0000000000242400002449
+S315080207500948084901604FF46141416000218160FE
+S31508020760C16001610C2242618161C16101628162DB
+S3150802077001F0FBBC00480040680000242DE9F04166
+S315080207804FF4FA560024154F4FF4007C07EB440841
+S3150802079017F8145098F8018045446D1C4543B6FB7A
+S315080207A0F5F805FB1868B8F1000F10D1B6FBF5F598
+S315080207B0ADB20D806D1E654509D217F8140010708A
+S315080207C007EB4400407818700120BDE8F081641CEC
+S315080207D0E4B2122CDAD30020F7E70000EC3D020857
+S315080207E030B5426B036853F8844F4FF6FC718C435D
+S315080207F044EA82041C60036853F8844F058F24F484
+S315080208007F0444EA05441C60836B1A44036853F860
+S31508020810884F8C4344EA82041C60036853F8884F65
+S31508020820858F24F4FE0444EA05441C60C36B02EB7C
+S315080208304302036853F8A04F8C4344EA82041C60BF
+S31508020840036853F8A04FB0F8405024F4FE0444EA73
+S3150802085005441C60D0E9103403FB0422036853F8EC
+S31508020860B04F8C4344EA82041C60036853F8B04FC5
+S31508020870B0F8485024F4FE0444EA05441C60D0E962
+S31508020880123403FB0422036853F8AC4F8C4344EA40
+S3150802089082041C60D0E9143403FB0422036853F86B
+S315080208A0F04F8C4344EA82041C60036853F8F04F05
+S315080208B0B0F8585024F47C1444EA05441C60836D4D
+S315080208C002EB4303026852F8C04F8C4344EA8301A1
+S315080208D01160016851F8C02FB0F85C3022F47C121E
+S315080208E042EA03420A60016851F8C02F90F8603064
+S315080208F022F07C5242EA03620A60416B224A02EB08
+S315080209008101C166826B01EB82020267C36B02EB4D
+S31508020910C3024267D0E91034634302EB830282675B
+S31508020920D0E91234634302EB8302C267D0E9143476
+S31508020930634302EB8302C0F88020836D02EBC30295
+S31508020940C0F88420C46D836E5C4302EB8402C0F84F
+S315080209508820046E5C4302EB8402C0F890200B4B9D
+S315080209609A4208D99830416841F020014160032132
+S315080209700170012030BD002200E004C1D0F8903099
+S315080209808B42FAD8002030BD00AC0040FCD30040B0
+S3150802099010B590F89820012A08D0022A06D050F8F5
+S315080209A09C1F41F002010160012010BDCA680B6854
+S315080209B08BB1072A0B6943EA42732BD00C7A4A6930
+S315080209C042EA84724968006F00EBC1000360426024
+S315080209D04FF0000010BD072A10D00C7A4FEAC26207
+S315080209E04B6943EA84730C8A42EA044243EA0203E5
+S315080209F04968C06E00EB81000360E9E70B8A4FF095
+S31508020A0060548A6942EA0343CA6944EA022243EA0B
+S31508020A100203EDE78A69D5E730B5039C90F898504A
+S31508020A20012D06D050F89C1F41F0040101600120F7
+S31508020A3030BD0068090141EA820141EA43012143C6
+S31508020A40C0F88010002030BD0068402904D0D0F8D4
+S31508020A50B40000F07F007047D0F8A40000F07F00D1
+S31508020A6070470000F0B5002690F89840022C06D090
+S31508020A7050F89C1F41F0080101600120F0BD402991
+S31508020A800BD041292BD0046D8C424AD850F89C1FB2
+S31508020A9041F0200101600120F0BD0468D4F8A0509D
+S31508020AA015F4FE0F0DD0D4F8A4506D0610D0D4F864
+S31508020AB0A440C4F30526446C456F744305EB8405CC
+S31508020AC034E050F89C1F41F0200101600120F0BD7E
+S31508020AD050F89C1F41F4807101600120F0BD046842
+S31508020AE0D4F8B05015F4FE0F0DD0D4F8B4506D06F4
+S31508020AF010D0D4F8B440C4F30526C46C856F744389
+S31508020B0005EB840512E050F89C1F41F020010160B4
+S31508020B100120F0BD50F89C1F41F48071016001204C
+S31508020B20F0BD446DC56F4C4305EB84052C6804F093
+S31508020B30804454602CB32C6824F0604414602C68FA
+S31508020B4004F0005494602C6804F000441461AC88E4
+S31508020B50A4B2D4616C6804F47024D4606C6804F49A
+S31508020B60801454616C6804F4001494616C68C4F3CC
+S31508020B70066414626C680835E40F54620024184F40
+S31508020B8009E02C68C4F38A441460D8E715F804C04F
+S31508020B9003F804C0641CD2F80CC007EB1C4C9CF882
+S31508020BA000C0A445F2D8402909D041290BD0012218
+S31508020BB020290CD200688A40C0F898200DE0006807
+S31508020BC0C0F8A86009E00068C0F8B86005E00068E7
+S31508020BD001F01F018A40C0F89C200020F0BD0000E9
+S31508020BE0203E02082DE9F04393B004464C2295496B
+S31508020BF06846FFF73EFC6CB1934F2068B84202D1B3
+S31508020C0000F5807060604FF4407994F898000026E9
+S31508020C1020B108E0012013B0BDE8F08384F899609A
+S31508020C20204600F013F92068816921F010018161DC
+S31508020C3000F020FA05464FF003080DE000F01AFA14
+S31508020C40401B0A2808D954F89C0F40F0010020607E
+S31508020C5004F8048C0120DEE7206880690007EDD4D9
+S31508020C602068816941F00101816100F003FA0546B5
+S31508020C700DE000F0FFF9401B0A2808D954F89C0F2A
+S31508020C8040F00100206004F8048C0120C3E72068C4
+S31508020C908069C007EDD02068816941F0020181614F
+S31508020CA0207C012839D02068816941F040018161A0
+S31508020CB0607C012837D02068816921F480418161EE
+S31508020CC0A07C012835D02068816941F48051816170
+S31508020CD020688169A26821F4407111438161206804
+S31508020CE0816921F0A40181612068016921F010015E
+S31508020CF00161E068012822D030B302282BD020688F
+S31508020D00816941F0800181612068016941F0100121
+S31508020D100161E068032818D022E02068816921F081
+S31508020D2040018161C4E72068816941F4804181619B
+S31508020D30C6E72068816921F480518161C8E7206885
+S31508020D40816941F0040181610AE02068816941F004
+S31508020D502001816104E02068816941F020018161F6
+S31508020D60207E401E4106E069401E41EA0020216AB3
+S31508020D70491E0843A18A491E40EA01402168C86102
+S31508020D80A06848450FD1E16AA06A491E401E40EA9A
+S31508020D900121206B401E41EA0011A08C401E41EA47
+S31508020DA000402168C860206E28B1206850F8C01F2C
+S31508020DB0626E11430160D4E91701C842694609D037
+S31508020DC0206850F8C82FA36E22F0070251F8233084
+S31508020DD01A430260206C48B1206850F8BC2F636C35
+S31508020DE022F0070251F823301A430260A06C50B170
+S31508020DF0206850F8BC2FE36C22F0700251F82330B9
+S31508020E0042EA03120260206D50B1206850F8BC2FE6
+S31508020E10636D22F4E06251F8231042EA012101606F
+S31508020E202068B84204D16068816821F003018160B4
+S31508020E3044F8946FA66001202071943C2046FFF77F
+S31508020E40CFFCE8E6303E020800A00040704790F862
+S31508020E509810012906D050F89C1F41F00401016040
+S31508020E6001207047022180F8981001688A6922F0E9
+S31508020E7001028A610021C0F89C1000207047000018
+S31508020E802DE9F84F0022684C4FF0B04B4FF003099A
+S31508020E904FF00F0AC1E0012696403340002B71D06D
+S31508020EA04D68012D05D0022D03D0112D01D0122D2A
+S31508020EB015D18768550009FA05FC27EA0C07D1F807
+S31508020EC00CC00CFA05FC4CEA070CC0F808C04568C9
+S31508020ED0B5430E79C6F3001696402E434660C5689A
+S31508020EE04FEA420C09FA0CF6B5438F6807FA0CF773
+S31508020EF02F43C7604D68022D01D0122D12D1D50895
+S31508020F0000EB8508D8F820705507ED0E0AFA05FE9B
+S31508020F1027EA0E07D1F810E00EFA05FE4EEA070E8A
+S31508020F20C8F820E00568B5430E7906F0030606FA06
+S31508020F300CF62E4306604D68ED006DD53B4D2E68C6
+S31508020F4046F002062E602D6805F00205009522F08D
+S31508020F50030606F1B046D6F808C495072F0F0AFA13
+S31508020F6007F52CEA050C324DA84201D100252EE0E0
+S31508020F70304DA84201D1012529E02F4DA84202D1C0
+S31508020F80022524E048E02D4DA84201D103251EE0A2
+S31508020F902B4DA84201D1042519E02A4DA84201D1B8
+S31508020FA0052514E0284DA84201D106250FE0274D54
+S31508020FB0A84201D107250AE0254DA84201D10825F4
+S31508020FC005E0244DA84201D1092500E00A25BD40C5
+S31508020FD045EA0C05C6F8085425689D434E68F6038B
+S31508020FE000D51D43256065689D434E68B60300D546
+S31508020FF01D436560DBF800509D434E68F60200D536
+S315080210001D43CBF80050DBF804509D434E68B602E8
+S3150802101000D51D43CBF80450521C0B6833FA02F56F
+S315080210207FF439AFBDE8F88F80000058F4440258BF
+S31508021030000002580004025800080258000C025820
+S31508021040001002580014025800180258001C0258D0
+S315080210500020025800240258002A01D081617047F4
+S31508021060090481617047000001480068000C704756
+S315080210700010005C014880687047000018000024D0
+S31508021080024881680278114481607047180000247A
+S3150802109010B5032000F0FEF800F090FC0F490A682C
+S315080210A0C2F303230E4AD35C03F01F03D840096830
+S315080210B001F00F01515C0B4A01F01F0120FA01F100
+S315080210C0116009490860002000F010F808B10120F3
+S315080210D010BD00F031F8002010BD00001844025877
+S315080210E0103E0208140000241000002470B50446BD
+S315080210F00F4D2A78002A0CD04FF47A700D49B0FBAE
+S31508021100F2F00968B1FBF0F001F017F818B1012006
+S3150802111070BD012070BD102C07D200222146501E38
+S3150802112000F098F86C60002070BD012070BD0000C8
+S315080211301800002410000024F0B587B04248016860
+S3150802114041F002010160006800F0020001903E4889
+S315080211501438016841F002010160016801F00201D8
+S315080211600191016841F004010160016801F004017E
+S315080211700191016841F008010160006800F0080069
+S31508021180019031480C38016841F4802101600068F9
+S3150802119000F4802001902C480838016841F48071D7
+S315080211A00160006800F480700190032000F072F874
+S315080211B000226FF00B00114600F04CF800226FF087
+S315080211C00A00114600F046F800226FF0090011469F
+S315080211D000F040F80022501F114600F03BF80022AA
+S315080211E0101F114600F036F80022901E114600F034
+S315080211F031F80022501E114600F02CF88020029089
+S315080212000120039000240494059402A90F4F38463E
+S31508021210FFF736FE4FF440750295022603960494AC
+S3150802122005940720069002A90948FFF729FE0295A8
+S315080212300396049405940920069002A93846FFF7F6
+S315080212401FFE07B0F0BD0000F4440258000402581D
+S31508021250000C0258F0B40D460D4B1B68C3F302236B
+S31508021260C3F10704042C00D90424191D072901D245
+S31508021270002300E0DB1E012606FA04F1491E294076
+S3150802128099409E40761E16403143F0BC02F090BD4E
+S315080212900CED00E000F00701054A10684FF6FF035F
+S315080212A0184040EA012003490843106070470000CD
+S315080212B00CED00E00000FA0570B514490A68D2433D
+S315080212C0520708D5096801F00701814201D00120B9
+S315080212D070BD002070BD0A6822F0070202430A6048
+S315080212E0FFF7C8FE0446094D4FF47A76083D06E034
+S315080212F0FFF7C0FE001BB04201D9012070BD286865
+S31508021300C0438004F4D4002070BD00000C48025883
+S3150802131010B500F00DFB05490968054AC1F302112B
+S31508021320515C01F01F01C84010BD0000204402585C
+S31508021330103E020810B569490A6802F003020968F4
+S31508021340C1F30531654B1B1D1B68C3F30013634CC0
+S3150802135014342468C4F3CC0414FB03F300EE103AE5
+S31508021360B8EE400A002971D09FED5D1A5B4BF7EE85
+S31508021370000A1033F2B39FED5B2A012A7FD0022AB4
+S315080213807CD001EE901A1968F8EE611AC2EE212A8B
+S31508021390C1F3080101EE901AF8EE611A40EE011A3D
+S315080213A031EEA00A22EE800A1968C1F3462101EE3F
+S315080213B0101AB8EE411A31EE201AC0EE011ABCEE26
+S315080213C0E11A80ED001A1968C1F3064101EE101AF6
+S315080213D0B8EE411A31EE201AC0EE011ABCEEE11A35
+S315080213E080ED011A1968C1F3066101EE101AB8EE0A
+S315080213F0411A00E008E071EE200A80EE201ABCEEDF
+S31508021400C10A80ED020A10BD344A283A1468A406B5
+S315080214101ED51268C2F3C104334AE24001EE902A8D
+S31508021420F8EE612A01EE901A1968F8EE611A82EE50
+S31508021430A12AC1F3080101EE901AF8EE611A40EEEC
+S31508021440011A31EEA00A22EE000AADE741E016E0E3
+S3150802145001EE901ADFED252A1968F8EE611A82EE76
+S31508021460A12AC1F3080101EE901AF8EE611A40EEBC
+S31508021470011A31EEA00A22EE000A95E713E001EE00
+S31508021480901A1968F8EE611AC2EE212AC1F3080108
+S3150802149001EE901AF8EE611A40EE011A31EEA00A30
+S315080214A022EE800A80E701EE901ADFED112A19680A
+S315080214B0F8EE611A82EEA12AC1F3080101EE901A2A
+S315080214C0F8EE611A40EE011A31EEA00A22EE000A7F
+S315080214D06AE7002101604160816010BD2844025814
+S315080214E0000000390024744A0090D0030024744C8A
+S315080214F00024F44A10B569490A6802F00302096829
+S31508021500C1F30551654B1B1D1B68C3F30023634CCE
+S315080215101C342468C4F3CC0414FB03F300EE103A1B
+S31508021520B8EE400A002971D09FED5D1A5B4BF7EEC3
+S31508021530000A1833F2B39FED5B2A012A7FD0022AEA
+S315080215407CD001EE901A1968F8EE611AC2EE212AC9
+S31508021550C1F3080101EE901AF8EE611A40EE011A7B
+S3150802156031EEA00A22EE800A1968C1F3462101EE7D
+S31508021570101AB8EE411A31EE201AC0EE011ABCEE64
+S31508021580E11A80ED001A1968C1F3064101EE101A34
+S31508021590B8EE411A31EE201AC0EE011ABCEEE11A73
+S315080215A080ED011A1968C1F3066101EE101AB8EE48
+S315080215B0411A00E008E071EE200A80EE201ABCEE1D
+S315080215C0C10A80ED020A10BD344A283A1468A406F4
+S315080215D01ED51268C2F3C104334AE24001EE902ACC
+S315080215E0F8EE612A01EE901A1968F8EE611A82EE8F
+S315080215F0A12AC1F3080101EE901AF8EE611A40EE2B
+S31508021600011A31EEA00A22EE000AADE741E016E021
+S3150802161001EE901ADFED252A1968F8EE611A82EEB4
+S31508021620A12AC1F3080101EE901AF8EE611A40EEFA
+S31508021630011A31EEA00A22EE000A95E713E001EE3E
+S31508021640901A1968F8EE611AC2EE212AC1F3080146
+S3150802165001EE901AF8EE611A40EE011A31EEA00A6E
+S3150802166022EE800A80E701EE901ADFED112A196848
+S31508021670F8EE611A82EEA12AC1F3080101EE901A68
+S31508021680F8EE611A40EE011A31EEA00A22EE000ABD
+S315080216906AE7002101604160816010BD2844025852
+S315080216A0000000390024744A0090D0030024744CC8
+S315080216B00024F44A2DE9F05F04460D46002C17D0A3
+S315080216C0DFF84C82D8F8000000F00F00A84211D2C9
+S315080216D0D8F8000020F00F002843C8F80000D8F810
+S315080216E0000000F00F00A84204D00120BDE8F09FD8
+S315080216F00120FBE72078874E40070AD52069316822
+S3150802170001F07001884204D9316821F07001014361
+S3150802171031602078804F00070AD56069396801F080
+S315080217207001884204D9396821F070010143396091
+S315080217302078C0060AD5A069396801F4E0618842B2
+S3150802174004D9396821F4E061014339602078DFF869
+S31508021750CC9180060DD5E069D9F8001001F0700128
+S31508021760884206D9D9F8001021F070010143C9F858
+S315080217700010207880070AD5E068316801F00F0169
+S31508021780884204D9316821F00F010143316020787B
+S31508021790C00743D03068A16820F4706008433060FF
+S315080217A05C4960681839022808D003280BD001283A
+S315080217B00ED00968490710D4012097E709688903FA
+S315080217C00BD4012092E70968890106D401208DE726
+S315080217D00968C90501D4012088E7DFF838A1AAF10A
+S315080217E0080ADAF8001021F007010143CAF80010C6
+S315080217F0FFF740FC834609E0FFF73CFCA0EB0B0130
+S3150802180041F28830814201D903206FE7DAF80000F5
+S31508021810616800F03800B0EBC10FEDD1207880077F
+S315080218200AD5E068316801F00F01884204D23168AE
+S3150802183021F00F0101433160D8F8000000F00F00D3
+S31508021840A8420ED9D8F8000020F00F002843C8F89D
+S315080218500000D8F8000000F00F00A84201D00120CD
+S3150802186044E7207840070AD52069316801F07001FB
+S31508021870884204D2316821F0700101433160207830
+S3150802188000070AD56069396801F07001884204D2F6
+S31508021890396821F07001014339602078C0060AD5FB
+S315080218A0A069396801F4E061884204D2396821F4F2
+S315080218B0E06101433960207880060DD5E069D9F8E0
+S315080218C0001001F07001884206D2D9F8001021F002
+S315080218D070010143C9F8001000F070F83168C1F3CD
+S315080218E003220F498A5C02F01F02D040326802F0D6
+S315080218F00F02895C0B4A01F01F0120FA01F11160FF
+S315080219000949086009480068BDE8F05FFFF7EEBBC1
+S3150802191000200052184402581C4402582044025817
+S31508021920103E020814000024100000241C000024A3
+S3150802193000B500F043F80B490A68C2F303230A4AC2
+S31508021940D35C03F01F03D840096801F00F01515C0C
+S31508021950064A01F01F0120FA01F11160044A1060DB
+S31508021960084600BD18440258103E02081400002416
+S315080219701000002400B5FFF7DBFF05490968054A90
+S31508021980C1F30211515C01F01F01C84000BD0000FD
+S315080219901C440258103E020800B5FFF7C9FF054964
+S315080219A00968054AC1F30221515C01F01F01C840CA
+S315080219B000BD00001C440258103E020830B56448B7
+S315080219C00068654C10F03801624808D002110829EF
+S315080219D00DD010290DD018290DD0104630BD21681A
+S315080219E08906FBD52168C1F3C101C84030BD10463E
+S315080219F030BD5A4830BD564918310A6802F003020A
+S31508021A000968C1F30511524B1C331B6803F0010325
+S31508021A104F4D24352D68C5F3CC0515FB03F300EEAF
+S31508021A20103AB8EE400A002977D0DFED4D0A484B46
+S31508021A30B7EE001A20333AB39FED4A2A012A58D044
+S31508021A40022A6CD001EE901A1868F8EE611AC2EEF4
+S31508021A50212AC0F3080001EE900AF8EE611A40EE58
+S31508021A60201A31EE810A22EE800A1868C0F346204F
+S31508021A70401C00EE900AF8EE600A80EE201ABCEED0
+S31508021A80C10A10EE100A30BD226892061BD52268DA
+S31508021A90C2F3C102D04001EE900A1868F8EE612A34
+S31508021AA001EE901AF8EE611A82EEA12AC0F3080036
+S31508021AB001EE900AF8EE611A40EE201A31EE810A1A
+S31508021AC022EE000AD1E701EE901ADFED272A1868FE
+S31508021AD0F8EE611A82EEA12AC0F3080001EE900A16
+S31508021AE0F8EE611A40EE201A31EE810A22EE000A59
+S31508021AF0BBE701EE901A1868F8EE611AC2EE212ABF
+S31508021B00C0F3080001EE900AF8EE611A40EE201AB8
+S31508021B1031EE810A22EE800AA7E716E0FFE701EE18
+S31508021B20901ADFED122A1868F8EE611A82EEA12AD7
+S31508021B30C0F3080001EE900AF8EE611A40EE201A88
+S31508021B4031EE810A22EE000A8FE7002030BD00003E
+S31508021B50104402580090D0030044025800127A003A
+S31508021B60000000390024744A0024744C0024F44A04
+S31508021B702DE9F05F0446002C10D02078DFF8E083C8
+S31508021B80F84EF94DC0075DD0D8F8000000F03800CD
+S31508021B90316810281FD0182803D006E00120BDE8B6
+S31508021BA0F09F01F00300022815D06068B0F5803F67
+S31508021BB018D0E0B1B0F5A02F22D0286820F48030E2
+S31508021BC02860286820F480202860606860B3FFF7E0
+S31508021BD051FA074624E02868800333D5606810BBAB
+S31508021BE00120DCE7286840F480302860EDE72868A1
+S31508021BF020F480302860286820F480202860E4E7F2
+S31508021C00286840F480202860286840F480302860DC
+S31508021C10DBE7FFF72FFAC01B642801D90320BEE7CA
+S31508021C2028688003F5D50DE0FFF724FA074606E093
+S31508021C30FFF720FAC01B642801D90320AFE72868FA
+S31508021C408003F5D4207841F2030AC84F800762D58B
+S31508021C50D8F8000000F03800316870B1182801D1B0
+S31508021C6088070AD0E068D0B3296821F01901014330
+S31508021C702960FFF7FFF9814622E02868400701D567
+S31508021C80E06858B1FFF7F0F9504509D83868216974
+S31508021C9020F47C3040EA013038603CE001207EE7DF
+S31508021CA03868217C20F0FE4040EA0160386032E064
+S31508021CB0FFF7E0F9A0EB0900022801D903206EE735
+S31508021CC028684007F4D5FFF7CFF9504508D8386891
+S31508021CD0216920F47C3040EA013038601BE007E0D5
+S31508021CE03868217C20F0FE4040EA0160386012E044
+S31508021CF0286820F001002860FFF7BCF9814607E052
+S31508021D00FFF7B8F9A0EB0900022801D9032046E734
+S31508021D1028684007F4D42078C00670D5D8F80000A1
+S31508021D2000F038003168DFF838B20828ABF1040B46
+S31508021D300FD0182803D101F00300012809D0E06961
+S31508021D4078B3286840F080002860FFF793F9814647
+S31508021D5028E02868C00504D5E069802801D001205A
+S31508021D601DE7FFF781F9504508D8386894F820101E
+S31508021D7020F0F84040EA8160386040E0DBF8000075
+S31508021D8094F8201020F07C5040EA0160CBF800005D
+S31508021D9035E0FFF76FF9A0EB0900022802D9032004
+S31508021DA0FDE61AE02868C005F3D5FFF75DF9504548
+S31508021DB008D8386894F8201020F0F84040EA816084
+S31508021DC038601CE0DBF8000094F8201020F07C5004
+S31508021DD040EA0160CBF8000011E0286820F0800094
+S31508021DE02860FFF747F9074606E0FFF743F9C01BE5
+S31508021DF0022801D90320D2E62868C005F5D420783E
+S31508021E00000730D5DFF85C91606909F14C09A8B181
+S31508021E10D9F8000040F00100C9F80000FFF72AF9D6
+S31508021E20074606E0FFF726F9C01B022801D9032058
+S31508021E30B5E6D9F800008007F4D514E0D9F8000011
+S31508021E4020F00100C9F80000FFF714F9074606E07A
+S31508021E50FFF710F9C01B022801D903209FE6D9F81B
+S31508021E6000008007F4D42078800626D5A06990B1B0
+S31508021E70286840F480502860FFF7FCF8074606E019
+S31508021E80FFF7F8F8C01B022801D9032087E628685D
+S31508021E908004F5D511E0286820F480502860FFF701
+S31508021EA0E9F8074606E0FFF7E5F8C01B022801D95C
+S31508021EB0032074E628688004F5D42078400768D59C
+S31508021EC02B4F386840F480703860FFF7D3F88146A4
+S31508021ED007E0FFF7CFF8A0EB0900642801D9032031
+S31508021EE05DE63868C005F4D51E4FA0684837012854
+S31508021EF012D0B0B105281DD0386820F0010038602C
+S31508021F00386820F004003860A06841F2883A30B395
+S31508021F10FFF7B0F881461EE0386840F001003860E5
+S31508021F20F2E7386820F001003860386820F00400CB
+S31508021F303860E9E7386840F004003860386840F0ED
+S31508021F4001003860E0E7FFF795F8A0EB0900504575
+S31508021F5001D9032023E638688007F4D519E009E099
+S31508021F6010440258284402580044025804440258AD
+S31508021F7000480258FFF77EF8814607E0FFF77AF82D
+S31508021F80A0EB0900504501D9032008E63868800706
+S31508021F90F4D4616AE9B3D8F80000DFF87C81C0F3AB
+S31508021FA0C200032876D0022907D0286820F080705C
+S31508021FB02860FFF75FF804467FE0286820F0807003
+S31508021FC02860FFF757F8074606E0FFF753F8C01BE5
+S31508021FD0022801D90320E2E528688001F5D4306891
+S31508021FE040F2F3318843E16A40EA0110A16A0843E4
+S31508021FF03060208E4FF6FF72616B401E491EC0F399
+S31508022000080002EA41210843218F4FF4FE02491EC5
+S3150802201000E07FE002EA0141084394F83C10491EB9
+S31508022020120202EA01610843C8F800003A48001F92
+S31508022030016821F0010101603749091D0A684FF656
+S31508022040F8739A43A36C42EAC3020A600168226CD7
+S3150802205021F00C01114301600168626C21F0020152
+S3150802206011430160016841F480310160016841F45D
+S3150802207000310160016841F480210160016841F084
+S3150802208001010160286840F080702860FEF7F2FFBF
+S31508022090044607E015E0FEF7EDFF001B022801D90A
+S315080220A003207CE528688001F5D533E0FEF7E2FFD8
+S315080220B0001B022801D9032071E528688001F5D49E
+S315080220C028E03268D8F80000012921D0A36A02F074
+S315080220D0030199421CD1E16AC2F30512914217D152
+S315080220E0216BC0F30802491E8A4211D1616BC0F303
+S315080220F04622491E91420BD1A16BC0F30642491EE4
+S31508022100914205D1E16BC0F30660491E814201D0B6
+S31508022110012044E5002042E53044025804284FF0E5
+S31508022120E02104D0086920F00400086170470869B4
+S3150802213040F0040008617047704710B5401EB0F1C0
+S31508022140807F01D3012010BD4FF0E02460610F218A
+S31508022150601701F02DFE0020A061072020610020F3
+S3150802216010BD10B5FFF7E8FF10BD10B50446002CE8
+S3150802217003D0D4F8800010B107E0012010BD00207A
+S3150802218084F87C00204600F028F82420C4F8800051
+S315080221902068016821F001010160204600F00CFB6D
+S315080221A0012818D0A06A10B1204600F071FA2068FA
+S315080221B0416821F4904141602068816821F02A0132
+S315080221C081602068016841F0010101602046BDE88E
+S315080221D0104000F0C1BA012010BD70472DE9F84F32
+S315080221E004460E4615469946D4F88400202802D09D
+S315080221F00220BDE8F88F06B3FDB194F87C000128E9
+S315080222001DD0012084F87C004FF00008C4F88880AD
+S315080222102220C4F88400FEF72DFF8246A4F85C50FB
+S31508022220A4F85E50FF21A0684FF4805398420DD15E
+S31508022230226932B1A4F860100FE00120D9E7022022
+S31508022240D7E740F2FF11A4F8601006E07F2268B1D2
+S31508022250B0F1805F12D0A4F86080B4F8607098423A
+S3150802226001D1206998B13546002628E0256915B1BD
+S31508022270A4F86020F1E7A4F86010EEE7216919B125
+S315080222803F21A4F86010E8E7A4F86020E5E70025F6
+S3150802229015E00022534620212046CDF8009001F091
+S315080222A02BFD08B10320A4E7A5B12068406A38408F
+S315080222B005F8010BB4F85E00401EA4F85E00B4F8F7
+S315080222C05E000028E5D12020C4F8840084F87C80CA
+S315080222D000208EE72068406A384026F8020BE9E7B4
+S315080222E010B501F05DFDFEF7D3FE00F047F800F0E9
+S315080222F0B7F9BDE8104000F001B800000022024814
+S315080223008021FEF7A9BE00000004025870B500F04D
+S31508022310A5F904460C4D6868201AB0F5FA7F0AD367
+S3150802232028780A4B40B100202870002218468021DE
+S31508022330FEF792FE6C6070BD0120287001221846D5
+S315080223408021FEF789FEF5E70800002400040258FA
+S3150802235010B50023014604480122FFF73FFF08B1E2
+S31508022360002010BD012010BD6800002410B5FEF73C
+S3150802237087FEBDE81040FFF7F4BE000010B59CB01A
+S315080223804C2109A8FEF7A7F8202101A8FEF7A3F811
+S315080223900220FEF791FF00241F48016841F44041DC
+S315080223A0016001681D490A6842F001020A6009686B
+S315080223B001F00101009101688904FCD50120099008
+S315080223C04FF4A0200A90022012901390042114912F
+S315080223D04FF4F072159216901791189019911A9453
+S315080223E01B9409A8FFF7C4FB00B1FEE73F20019042
+S315080223F0032002900394082004904020059006903A
+S31508022400010107910890042101A8FFF753F9002852
+S3150802241000D0FEE71CB010BD184802582C0400581C
+S3150802242030B55F4800685F4C10F038015E481BD033
+S31508022430021108291DD010291DD018291DD01046B1
+S31508022440574B08331968594AC1F30321515CC840EE
+S31508022450196801F00F01515C01F01F0120FA01F21F
+S3150802246053494A60086030BD2168C1F3C101C840BA
+S31508022470E6E71046E4E74F48E2E7494918310A68B1
+S3150802248002F003020968C1F30511454B1C331B68A8
+S3150802249003F00103424D24352D68C5F3CC0515FB1F
+S315080224A003F300EE103AB8EE400A71B3DFED420AC2
+S315080224B03B4BB7EE001A203342B3DFED401A012A2E
+S315080224C041D0022A53D002EE101A1868F8EE422AB0
+S315080224D081EEA22AC0F3080001EE900AF8EE611A0C
+S315080224E040EE201A31EE810A22EE000A1868C0F37D
+S315080224F04620401C00EE900AF8EE600A80EE201A8A
+S31508022500BCEEC10A10EE100A9AE746E0FFE7226817
+S31508022510C2F3C102D04001EE900A1868F8EE612AA9
+S3150802252001EE901AF8EE611A82EEA12AC0F30800AB
+S3150802253001EE900AF8EE611A40EE201A31EE810A8F
+S3150802254022EE000AD2E702EE101A1868F8EE422ABC
+S3150802255081EEA22AC0F3080001EE900AF8EE611A8B
+S3150802256040EE201A31EE810A22EE000ABEE701EE9B
+S31508022570901ADFED132A1868F8EE611A82EEA12A7C
+S31508022580C0F3080001EE900AF8EE611A40EE201A2E
+S3150802259031EE810A22EE000AA8E7002050E7000081
+S315080225A010440258004402580090D003103E020814
+S315080225B01000002400127A00000000390024744A30
+S315080225C00024F44A2048016841F4700101601F4959
+S315080225D0086840F0010008601C4A002010321060AA
+S315080225E00A681B4B1A400A60184A18321060121DF4
+S315080225F01060121D1060154A28321060121D1060F4
+S31508022600121D1060121D1060121D1060121D10603E
+S31508022610121D1060121D10600A6822F480220A60D8
+S315080226200A49603108600B4800686FF30F00B0F181
+S31508022630005F02D20849012008604FF00060024993
+S31508022640803908607047000088ED00E000440258AF
+S315080226507FEDF6EA0010005C08810051FEF70ABD1C
+S3150802266010B5FFF7DDFE09484FF47A710068B0FB32
+S31508022670F1F0FFF762FD0420FFF750FD0022BDE8E6
+S315080226801040501E1146FEF7E5BD0000100000245A
+S3150802269090F82810C90706D001684A68C36A22F466
+S315080226A000321A434A6090F82810890706D501684D
+S315080226B04A68036B22F480321A434A6090F828105B
+S315080226C0490706D501684A68436B22F480221A43F1
+S315080226D04A6090F82810090706D501684A68836B8C
+S315080226E022F400421A434A6090F82810C90606D511
+S315080226F001688A68C36B22F480521A438A6090F88A
+S315080227002810890606D501688A68036C22F40052E5
+S315080227101A438A6090F82810490611D501684A6852
+S31508022720436C22F480121A434A60416CB1F5801F49
+S3150802273006D101684A68836C22F4C0021A434A60C9
+S3150802274090F82810090606D501684A68C06C22F472
+S31508022750002202434A607047F8B504460026C4F8C8
+S315080227608860FEF787FC0746206800686FF07E459A
+S3150802277000070AD500223B464FF400112046009571
+S3150802278001F0BAFA08B10320F8BD206800684007CC
+S315080227900AD500223B464FF480012046009501F0F7
+S315080227A0ABFA08B10320F8BD20207C346060A06033
+S315080227B026700020F8BD00002DE9F04F87B00446C8
+S315080227C04FF0000800250020F74B21682669A26809
+S315080227D0E769324366693E433243666E16430A68C0
+S315080227E0F24F3A4032430A6021684A68E66822F4A0
+S315080227F0405232434A60A16922689A4201D0266A47
+S3150802280031439668EA4F3E400E4396602168CA6A8B
+S31508022810666A22F00F023243CA62E64E2168E64A27
+S31508022820B14224D1126802F03802182A16D005DC01
+S315080228305AB1082A0CD0102A04D10CE0202A10D04A
+S31508022840282A11D04FF0800B2AE14FF0010B27E11D
+S315080228504FF0040B24E14FF0080B21E14FF0100B67
+S315080228601EE14FF0200B1BE14FF0400B18E1D34E4F
+S31508022870B1421ED1126802F00702062A16D2DFE812
+S3150802288002F00306090C0F124FF0000B08E14FF095
+S31508022890040B05E14FF0080B02E14FF0100BFFE0C5
+S315080228A04FF0200BFCE04FF0400BF9E04FF0800BA5
+S315080228B0F6E0C34EB1421ED1126802F00702062A9A
+S315080228C016D2DFE802F00306090C0F124FF0000BCE
+S315080228D0E6E04FF0040BE3E04FF0080BE0E04FF0C0
+S315080228E0100BDDE04FF0200BDAE04FF0400BD7E09B
+S315080228F04FF0800BD4E0B34EB1421ED1126802F0FB
+S315080229000702062A16D2DFE802F00306090C0F129E
+S315080229104FF0000BC4E04FF0040BC1E04FF0080B78
+S31508022920BEE04FF0100BBBE04FF0200BB8E04FF0C3
+S31508022930400BB5E04FF0800BB2E0A34EB1421ED178
+S31508022940126802F00702062A16D2DFE802F0030628
+S31508022950090C0F124FF0000BA2E04FF0040B9FE098
+S315080229604FF0080B9CE04FF0100B99E04FF0200B4C
+S3150802297096E04FF0400B93E04FF0800B90E0934EB9
+S31508022980B14224D1126802F03802182A16D005DCA0
+S315080229905AB1082A0CD0102A04D10CE0202A10D0E9
+S315080229A0282A11D04FF0800B7AE04FF0010B77E01E
+S315080229B04FF0040B74E04FF0080B71E04FF0100B68
+S315080229C06EE04FF0200B6BE04FF0400B68E0804E54
+S315080229D0B1421ED1126802F00702062A16D2DFE8B1
+S315080229E002F00306090C0F124FF0000B58E04FF0E5
+S315080229F0040B55E04FF0080B52E04FF0100B4FE076
+S31508022A004FF0200B4CE04FF0400B49E04FF0800BA3
+S31508022A1046E0704EB1421ED1126802F00702062A3B
+S31508022A2016D2DFE802F00306090C0F124FF0000B6C
+S31508022A3036E04FF0040B33E04FF0080B30E04FF06E
+S31508022A40100B2DE04FF0200B2AE04FF0400B27E049
+S31508022A504FF0800B24E0994220D1574A121D126882
+S31508022A6002F00702062A16D2DFE802F00306090C6C
+S31508022A700F124FF0020B13E04FF0040B10E04FF069
+S31508022A80080B0DE04FF0100B0AE04FF0200B07E0A1
+S31508022A904FF0400B04E04FF0800B01E04FF0800B43
+S31508022AA0DFF834A1002799424FF4807977D1BBF138
+S31508022AB0100F75D009DCBBF1020F19D0BBF1040F58
+S31508022AC04DD0BBF1080F06D1A1E0BBF1200F68D0AB
+S31508022AD0BBF1400F66D00125002808D0666806EBD0
+S31508022AE04601814202D8B0EB063F77D90125EEE3CB
+S31508022AF0FEF70EFC0146606AC8B1012819D0022801
+S31508022B0019D0032819D0042819D0052819D006285F
+S31508022B1019D0072819D0082819D0092819D00A283F
+S31508022B2019D00B2819D00120B1FBF0F0D4E7012007
+S31508022B30FAE70220F8E70420F6E70620F4E7082079
+S31508022B40F2E70A20F0E70C20EEE71020ECE7202057
+S31508022B50EAE74020E8E78020E6E74846E4E704A8F3
+S31508022B60FEF7E8FB0599606AE8B1012839D0022820
+S31508022B7039D0032839D0042839D0052839D006286F
+S31508022B8039D0072839D0082839D0092839D00A284F
+S31508022B9039D00B2839D00120B1FBF0F09CE7AEE31F
+S31508022BA06DE0DDE011E11AE0000C0058F369FFCF91
+S31508022BB0FFF4FF110010014054440258004400403B
+S31508022BC000480040004C00400050004000140140FC
+S31508022BD000780040007C00400090D0032BE10120E1
+S31508022BE0DAE70220D8E70420D6E70620D4E7082049
+S31508022BF0D2E70A20D0E70C20CEE71020CCE7202027
+S31508022C00CAE74020C8E78020C6E74846C4E701A8C5
+S31508022C10FEF770FC0299606AC8B1012819D0022829
+S31508022C2019D0032819D0042819D0052819D006283E
+S31508022C3019D0072819D0082819D0092819D00A281E
+S31508022C4019D00B2819D00120B1FBF0F044E7012076
+S31508022C50FAE70220F8E70420F6E70620F4E7082058
+S31508022C60F2E70A20F0E70C20EEE71020ECE7202036
+S31508022C70EAE74020E8E78020E6E74846E4E7F7483F
+S31508022C800168890638D50068C0F3C1002AFA00F13E
+S31508022C90606AC8B1012819D0022819D0032819D0A8
+S31508022CA0042819D0052819D0062819D0072819D0BA
+S31508022CB0082819D0092819D00A2819D00B2819D09A
+S31508022CC00120B1FBF0F007E70120FAE70220F8E756
+S31508022CD00420F6E70620F4E70820F2E70A20F0E7E0
+S31508022CE00C20EEE71020ECE72020EAE74020E8E790
+S31508022CF08020E6E74846E4E7606AC8B1012819D0A9
+S31508022D00022819D0032819D0042819D0052819D061
+S31508022D10062819D0072819D0082819D0092819D041
+S31508022D200A2819D00B2819D00120BAFBF0F0D3E6ED
+S31508022D300120FAE70220F8E70420F6E70620F4E77E
+S31508022D400820F2E70A20F0E70C20EEE71020ECE76D
+S31508022D502020EAE74020E8E78020E6E74846E4E75D
+S31508022D60606AD0B101281AD002281AD003281AD0CC
+S31508022D7004281AD005281AD006281AD007281AD0E5
+S31508022D8008281AD009281AD00A281AD00B281AD0C5
+S31508022D900120B349B1FBF0F09EE60120F9E70220D3
+S31508022DA0F7E70420F5E70620F3E70820F1E70A200B
+S31508022DB0EFE70C20EDE71020EBE72020E9E74020BB
+S31508022DC0E7E78020E5E74846E3E7606AD8B10128E5
+S31508022DD01BD002281BD003281BD004281BD0052889
+S31508022DE01BD006281BD007281BD008281BD0092869
+S31508022DF01BD00A281BD00B281BD001204FF40041F8
+S31508022E00B1FBF0F068E60120F8E70220F6E70420B5
+S31508022E10F4E70620F2E70820F0E70A20EEE70C209E
+S31508022E20ECE71020EAE72020E8E74020E6E78020E2
+S31508022E30E4E74846E2E7BBF1100F7DD009DCBBF1B7
+S31508022E40020F16D0BBF1040F64D0BBF1080F06D1EE
+S31508022E50B8E0BBF1200F70D0BBF1400F6ED0012550
+S31508022E608049A8F54070884269D82068C0F80C8065
+S31508022E702DE2FEF74DFA0146606A50B301282BD0BF
+S31508022E8002282CD003282DD004282ED005282FD08E
+S31508022E90062830D0072831D0082832D0092833D05E
+S31508022EA00A2834D00B2801D04FF00109084600231E
+S31508022EB04A461946FDF766FA62680902030241EABA
+S31508022EC010615008181879410023FDF75BFA80460D
+S31508022ED0C6E74FF00109E9E74FF00209E6E74FF0C6
+S31508022EE00409E3E74FF00609E0E74FF00809DDE7D2
+S31508022EF04FF00A09DAE74FF00C09D7E74FF0100945
+S31508022F00D4E74FF02009D1E74FF04009CEE74FF05A
+S31508022F108009CBE704A8FEF70DFA0599606A78B32B
+S31508022F20012831D0022832D0032833D0042834D0DD
+S31508022F30052835D0062803E09CE040E18DE1DCE176
+S31508022F4031D0072832D0082833D0092834D00A28A5
+S31508022F5035D00B2801D04FF00109084600234A460E
+S31508022F601946FDF70FFA62680902030241EA10617F
+S31508022F705008181879410023FDF704FA80466FE7CE
+S31508022F80FFE74FF00109E8E74FF00209E5E74FF0DE
+S31508022F900409E2E74FF00609DFE74FF00809DCE724
+S31508022FA04FF00A09D9E74FF00C09D6E74FF0100996
+S31508022FB0D3E74FF02009D0E74FF04009CDE74FF0AD
+S31508022FC08009CAE701A8FEF795FA0299606A50B322
+S31508022FD001282BD002282CD003282DD004282ED045
+S31508022FE005282FD0062830D0072831D0082832D015
+S31508022FF0092839D00A283AD00B2801D04FF00109FE
+S31508023000084600234A461946FDF7BCF962680902D2
+S31508023010030241EA10615008181879410023FDF7A6
+S31508023020B1F980461CE74FF00109E9E74FF00209BA
+S31508023030E6E74FF00409E3E74FF00609E0E74FF049
+S315080230400809DDE74FF00A09DAE74FF00C09D7E776
+S315080230504FF01009D4E74FF02009D1E7004402588F
+S3150802306000093D00FFFC0F004FF04009C8E74FF08A
+S315080230708009C5E7F7480168890652D50068C0F392
+S31508023080C1002AFA00FA606A50B301282BD0022836
+S315080230902CD003282DD004282ED005282FD0062878
+S315080230A030D0072831D0082832D0092833D00A2848
+S315080230B034D00B2801D04FF00109504600234A4666
+S315080230C01946FDF75FF90902020241EA1061700822
+S315080230D01018324679410023FDF754F98046BFE6B7
+S315080230E04FF00109E9E74FF00209E6E74FF0040954
+S315080230F0E3E74FF00609E0E74FF00809DDE74FF08E
+S315080231000A09DAE74FF00C09D7E74FF01009D4E7B6
+S315080231104FF02009D1E74FF04009CEE74FF080097A
+S31508023120CBE7606A50B301282BD002282CD003289B
+S315080231302DD004282ED005282FD0062830D00728CF
+S3150802314031D0082832D0092833D00A2834D00B289F
+S3150802315001D04FF00109504600234A461946FDF7A9
+S3150802316011F90902020241EA106170081018324682
+S3150802317079410023FDF706F9804671E64FF0010909
+S31508023180E9E74FF00209E6E74FF00409E3E74FF0F3
+S315080231900609E0E74FF00809DDE74FF00A09DAE722
+S315080231A04FF00C09D7E74FF01009D4E74FF0200982
+S315080231B0D1E74FF04009CEE74FF08009CBE7606AC6
+S315080231C050B301282BD002282CD003282DD004284E
+S315080231D02ED005282FD0062830D0072831D0082827
+S315080231E032D0092833D00A2834D00B2801D04FF020
+S315080231F00109994800234A461946FDF7C3F8090208
+S31508023200020241EA10617008101832467941002319
+S31508023210FDF7B8F8804623E64FF00109E9E74FF0D3
+S315080232200209E6E74FF00409E3E74FF00609E0E78B
+S315080232304FF00809DDE74FF00A09DAE74FF00C0903
+S31508023240D7E74FF01009D4E74FF02009D1E74FF03E
+S315080232504009CEE74FF08009CBE7606A58B30128E8
+S315080232602CD002282DD003282ED0042830D00528A9
+S3150802327031D0062832D0072833D0082834D0092876
+S3150802328035D00A2836D00B2801D04FF00109002381
+S315080232904A464FF400401946FDF774F8090202023D
+S315080232A041EA106170081018324679410023FDF789
+S315080232B069F88046D4E54FF00109E8E74FF00209BC
+S315080232C0E5E74FF00409E2E74FF00609DFE797E280
+S315080232D04FF00809DBE74FF00A09D8E74FF00C0967
+S315080232E0D5E74FF01009D2E74FF02009CFE74FF0A4
+S315080232F04009CCE74FF08009C9E7012580E2E06979
+S315080233004FF400414FF6EF7688426ED1BBF1080FB3
+S315080233106CD009DCBBF1000F1ED0BBF1010F66D0E1
+S31508023320BBF1040F09D1B4E0BBF1100F7DD0BBF19C
+S31508023330200F7BD0BBF1400F79D00125A8F11000F0
+S31508023340B04275D84FF6F07108EA0100C8F3420197
+S3150802335008432168C86053E2FEF70CFB0146606A1F
+S3150802336010B3012823D0022824D0032825D0042804
+S3150802337026D0052827D0062828D0072829D00828A5
+S315080233802AD009282BD00A282CD00B2801D04FF096
+S315080233900109B1FBF9F04100606801EB5001B1FB8C
+S315080233A0F0F01FFA80F8C9E74FF00109F1E74FF08C
+S315080233B00209EEE74FF00409EBE74FF00609E8E7E2
+S315080233C04FF00809E5E74FF00A09E2E74FF00C0962
+S315080233D0DFE74FF01009DCE74FF02009D9E74FF095
+S315080233E04009D6E74FF08009D3E70AE29BE0FEF7E9
+S315080233F0D3FA0146606A38B3012828D002282DD0AC
+S3150802340003282ED004282FD0052830D0062831D0FC
+S31508023410072832D0082833D0092834D00A2835D0CC
+S315080234200B2801D04FF0010903E0C6E05AE1A0E1FA
+S31508023430E5E1B1FBF9F04100606801EB5001B1FB2F
+S31508023440F0F01FFA80F879E74FF00109ECE74FF040
+S315080234500209E9E70044025800093D004FF0040951
+S31508023460E2E74FF00609DFE74FF00809DCE74FF01D
+S315080234700A09D9E74FF00C09D6E74FF01009D3E746
+S315080234804FF02009D0E74FF04009CDE74FF0800909
+S31508023490CAE704A8FDF74EFF0599606A10B301282A
+S315080234A023D0022824D0032825D0042826D005288C
+S315080234B027D0062828D0072829D008282AD009285C
+S315080234C02BD00A282CD00B2801D04FF00109B1FBCA
+S315080234D0F9F04100606801EB5001B1FBF0F01FFA08
+S315080234E080F82BE74FF00109F1E74FF00209EEE702
+S315080234F04FF00409EBE74FF00609E8E74FF0080931
+S31508023500E5E74FF00A09E2E74FF00C09DFE74FF06B
+S315080235101009DCE74FF02009D9E74FF04009D6E752
+S315080235204FF08009D3E701A8FDF7E4FF0299606A24
+S3150802353010B3012823D0022824D0032825D0042832
+S3150802354026D0052827D0062828D0072829D00828D3
+S315080235502AD009282BD00A282CD00B2801D04FF0C4
+S315080235600109B1FBF9F04100606801EB5001B1FBBA
+S31508023570F0F01FFA80F8E1E64FF00109F1E74FF0A3
+S315080235800209EEE74FF00409EBE74FF00609E8E710
+S315080235904FF00809E5E74FF00A09E2E74FF00C0990
+S315080235A0DFE74FF01009DCE74FF02009D9E74FF0C3
+S315080235B04009D6E74FF08009D3E7FE480168890635
+S315080235C04AD50068C0F3C1002AFA00FA606A10B345
+S315080235D0012823D0022824D0032825D0042826D05F
+S315080235E0052827D0062828D0072829D008282AD02F
+S315080235F009282BD00A282CD00B2801D04FF0010914
+S31508023600BAFBF9F04100606801EB5001B1FBF0F03A
+S315080236101FFA80F892E64FF00109F1E74FF0020926
+S31508023620EEE74FF00409EBE74FF00609E8E74FF03B
+S315080236300809E5E74FF00A09E2E74FF00C09DFE768
+S315080236404FF01009DCE74FF02009D9E74FF040099F
+S31508023650D6E74FF08009D3E7606A10B3012823D072
+S31508023660022824D0032825D0042826D0052827D0C6
+S31508023670062828D0072829D008282AD009282BD096
+S315080236800A282CD00B2801D04FF00109BAFBF9F011
+S315080236904100606801EB5001B1FBF0F01FFA80F8B7
+S315080236A04CE64FF00109F1E74FF00209EEE74FF059
+S315080236B00409EBE74FF00609E8E74FF00809E5E7E2
+S315080236C04FF00A09E2E74FF00C09DFE74FF010095D
+S315080236D0DCE74FF02009D9E74FF04009D6E74FF06B
+S315080236E08009D3E7606A18B3012824D0022825D0B6
+S315080236F0032826D0042827D0052828D0062829D02A
+S3150802370007282AD008282BD009282CD00A282DD0F9
+S315080237100B2801D04FF00109A748B0FBF9F0410088
+S31508023720606801EB5001B1FBF0F01FFA80F805E67C
+S315080237304FF00109F0E74FF00209EDE74FF00409EF
+S31508023740EAE74FF00609E7E74FF00809E4E74FF022
+S315080237500A09E1E74FF00C09DEE74FF01009DBE74B
+S315080237604FF02009D8E74FF04009D5E74FF0800916
+S31508023770D2E7606A10B3012823D0022824D003288E
+S3150802378025D0042826D0052827D0062828D0072899
+S3150802379029D008282AD009282BD00A282CD00B2869
+S315080237A001D04FF00109B1FBF9F04100606801EB65
+S315080237B05001B1FBF0F01FFA80F8BFE54FF001099E
+S315080237C0F1E74FF00209EEE74FF00409EBE74FF095
+S315080237D00609E8E74FF00809E5E74FF00A09E2E7C4
+S315080237E04FF00C09DFE74FF01009DCE74FF020092C
+S315080237F0D9E74FF04009D6E74FF08009D3E701250C
+S315080238006CE2BBF1080F7DD009DCBBF1000F18D0C2
+S31508023810BBF1010F5DD0BBF1040F09D1A7E0BBF1E3
+S31508023820100F70D0BBF1200F6ED0BBF1400F6CD0D9
+S315080238300125A8F11000B04268D82068C0F80C80AB
+S315080238404CE2FEF797F80146606A08B3012822D0CF
+S31508023850022823D0032824D0042825D0052826D0D8
+S31508023860062827D0072828D0082829D009282AD0A8
+S315080238700A282BD00B2801D04FF001096068B1FB4A
+S31508023880F9F101EB5001B1FBF0F01FFA80F8D0E72D
+S315080238904FF00109F2E74FF00209EFE74FF004098A
+S315080238A0ECE74FF00609E9E74FF00809E6E74FF0BB
+S315080238B00A09E3E74FF00C09E0E74FF01009DDE7E4
+S315080238C04FF02009DAE74FF04009D7E74FF08009B1
+S315080238D0D4E7FEF761F80146606A38B3012828D0B2
+S315080238E0022829D003282AD004282BD005282CD030
+S315080238F006282DD007282ED008282FD0092830D000
+S315080239000A2804E082E0CAE05CE1A1E1E5E12BD005
+S315080239100B2801D04FF001096068B1FBF9F101EB00
+S315080239205001B1FBF0F01FFA80F882E74FF0010967
+S31508023930F2E74FF00209EFE74FF00409ECE74FF020
+S315080239400609E9E74FF00809E6E74FF00A09E3E74F
+S315080239504FF00C09E0E74FF01009DDE74FF02009B8
+S31508023960DAE74FF04009D7E74FF08009D4E704A811
+S31508023970FDF7E0FC0599606AD8B1012828D002282B
+S3150802398029D003282AD004282BD005282CD006288B
+S315080239902DD007282ED008282FD0092830D00A285B
+S315080239A031D00B2801D04FF001096068B1FBF9F15B
+S315080239B004E00AE00044025800093D0001EB500108
+S315080239C0B1FBF0F01FFA80F833E74FF00109ECE794
+S315080239D04FF00209E9E74FF00409E6E74FF0060956
+S315080239E0E3E74FF00809E0E74FF00A09DDE74FF091
+S315080239F00C09DAE74FF01009D7E74FF02009D4E7A8
+S31508023A004FF04009D1E74FF08009CEE701A8FDF74C
+S31508023A1071FD0299606A08B3012822D0022823D0D0
+S31508023A20032824D0042825D0052826D0062827D0FE
+S31508023A30072828D0082829D009282AD00A282BD0CE
+S31508023A400B2801D04FF001096068B1FBF9F101EBCF
+S31508023A505001B1FBF0F01FFA80F8EAE64FF00109CF
+S31508023A60F2E74FF00209EFE74FF00409ECE74FF0EF
+S31508023A700609E9E74FF00809E6E74FF00A09E3E71E
+S31508023A804FF00C09E0E74FF01009DDE74FF0200987
+S31508023A90DAE74FF04009D7E74FF08009D4E79448B0
+S31508023AA00168890649D50068C0F3C1002AFA00FAF6
+S31508023AB0606A08B3012822D0022823D0032824D01A
+S31508023AC0042825D0052826D0062827D0072828D056
+S31508023AD0082829D009282AD00A282BD00B2801D051
+S31508023AE04FF001096068BAFBF9F101EB5001B1FB2D
+S31508023AF0F0F01FFA80F89CE64FF00109F2E74FF062
+S31508023B000209EFE74FF00409ECE74FF00609E9E787
+S31508023B104FF00809E6E74FF00A09E3E74FF00C0908
+S31508023B20E0E74FF01009DDE74FF02009DAE74FF03A
+S31508023B304009D7E74FF08009D4E7606A08B301283D
+S31508023B4022D0022823D0032824D0042825D00528E9
+S31508023B5026D0062827D0072828D0082829D00928B9
+S31508023B602AD00A282BD00B2801D04FF00109606809
+S31508023B70BAFBF9F101EB5001B1FBF0F01FFA80F83C
+S31508023B8057E64FF00109F2E74FF00209EFE74FF067
+S31508023B900409ECE74FF00609E9E74FF00809E6E7FA
+S31508023BA04FF00A09E3E74FF00C09E0E74FF0100976
+S31508023BB0DDE74FF02009DAE74FF04009D7E74FF083
+S31508023BC08009D4E7606A10B3012823D0022824D0DA
+S31508023BD0032825D0042826D0052827D0062828D049
+S31508023BE0072829D008282AD009282BD00A282CD019
+S31508023BF00B2801D04FF001093E48B0FBF9F1606885
+S31508023C0001EB5001B1FBF0F01FFA80F811E64FF014
+S31508023C100109F1E74FF00209EEE74FF00409EBE775
+S31508023C204FF00609E8E74FF00809E5E74FF00A09F9
+S31508023C30E2E74FF00C09DFE74FF01009DCE74FF037
+S31508023C402009D9E74FF04009D6E74FF08009D3E7B4
+S31508023C50606A08B3012822D0022823D0032824D078
+S31508023C60042825D0052826D0062827D0072828D0B4
+S31508023C70082829D009282AD00A282BD00B2801D0AF
+S31508023C804FF001096068B1FBF9F101EB5001B1FB94
+S31508023C90F0F01FFA80F8CCE54FF00109F2E74FF091
+S31508023CA00209EFE74FF00409ECE74FF00609E9E7E6
+S31508023CB04FF00809E6E74FF00A09E3E74FF00C0967
+S31508023CC0E0E74FF01009DDE74FF02009DAE74FF099
+S31508023CD04009D7E74FF08009D4E701250120683467
+S31508023CE0608020806760A76007B02846BDE8F08F2D
+S31508023CF00044025800093D002DE9F04704460E46E5
+S31508023D0017469846089D4FF0000A4FF020093BE0F7
+S31508023D10681C39D0FDF7AEF9A0EB0800A84221D8F5
+S31508023D2005B32068016849072ED5C069C043000556
+S31508023D302AD421684FF4006008622068016821F4D9
+S31508023D40D07101602068816821F001018160C4F8A0
+S31508023D508090C4F88490C4F8889084F87CA00320E4
+S31508023D60BDE8F0872068016821F4D07101602068F7
+S31508023D70816821F001018160C4F88090C4F88490BA
+S31508023D8084F87CA00320EBE72068C06936EA0000C5
+S31508023D9004D00020B842BBD00020E1E70120F9E7B1
+S31508023DA002490148086070470000020808ED00E071
+S31508023DB00907090E002804DB00F1E02080F8001448
+S31508023DC0704700F00F0000F1E02080F8141D7047DC
+S31508023DD0FEF786FAFCF77BFCFEF798FAFCF770FC0E
+S31508023DE0FAE74FF04070E1EE100A70470502060244
+S31508023DF0060307030803090309040A040B040C044F
+S31508023E000C050D050E050F050F06100610071008FE
+S31508023E100000000001020304010203040607080960
+S31508023E200001020304050607080C10141820304086
+S31508023E300000000000000000000000000000000072
+S31508023E40000000000100000002000000030000005C
+S31508023E500400000000000000050000000000000049
+S31508023E60000000000000000006000000000000003C
+S31508023E700000000000000000070000009C3E020847
+S31508023E800000002424000000D8020208C03E0208EE
+S31508023E9024000024D4070000F402020800000000EF
+S31508023EA00000000000000000000000000090D0039F
+S31508023EB00090D0030100000010000000000000007E
+S7050802029D51
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/boot.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/boot.c
new file mode 100644
index 00000000..ac5258d4
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/boot.c
@@ -0,0 +1,498 @@
+/************************************************************************************//**
+* \file         Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/boot.c
+* \brief        Demo program bootloader interface source file.
+* \ingroup      Prog_ARMCM7_STM32H7_Nucleo_H743ZI_Keil
+* \internal
+*----------------------------------------------------------------------------------------
+*                          C O P Y R I G H T
+*----------------------------------------------------------------------------------------
+*   Copyright (c) 2020  by Feaser    http://www.feaser.com    All rights reserved
+*
+*----------------------------------------------------------------------------------------
+*                            L I C E N S E
+*----------------------------------------------------------------------------------------
+* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as published by the Free
+* Software Foundation, either version 3 of the License, or (at your option) any later
+* version.
+*
+* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+* PURPOSE. See the GNU General Public License for more details.
+*
+* You have received a copy of the GNU General Public License along with OpenBLT. It
+* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
+*
+* \endinternal
+****************************************************************************************/
+
+/****************************************************************************************
+* Include files
+****************************************************************************************/
+#include "header.h"                                    /* generic header               */
+
+
+/****************************************************************************************
+* Function prototypes
+****************************************************************************************/
+#if (BOOT_COM_RS232_ENABLE > 0)
+static void BootComRs232Init(void);
+static void BootComRs232CheckActivationRequest(void);
+#endif
+#if (BOOT_COM_CAN_ENABLE > 0)
+static void BootComCanInit(void);
+static void BootComCanCheckActivationRequest(void);
+#endif
+
+
+/************************************************************************************//**
+** \brief     Initializes the communication interface.
+** \return    none.
+**
+****************************************************************************************/
+void BootComInit(void)
+{
+#if (BOOT_COM_RS232_ENABLE > 0)
+  BootComRs232Init();
+#endif
+#if (BOOT_COM_CAN_ENABLE > 0)
+  BootComCanInit();
+#endif
+} /*** end of BootComInit ***/
+
+
+/************************************************************************************//**
+** \brief     Receives the CONNECT request from the host, which indicates that the
+**            bootloader should be activated and, if so, activates it.
+** \return    none.
+**
+****************************************************************************************/
+void BootComCheckActivationRequest(void)
+{
+#if (BOOT_COM_RS232_ENABLE > 0)
+  BootComRs232CheckActivationRequest();
+#endif
+#if (BOOT_COM_CAN_ENABLE > 0)
+  BootComCanCheckActivationRequest();
+#endif
+} /*** end of BootComCheckActivationRequest ***/
+
+
+/************************************************************************************//**
+** \brief     Bootloader activation function.
+** \return    none.
+**
+****************************************************************************************/
+void BootActivate(void)
+{
+  /* perform software reset to activate the bootoader again */
+  NVIC_SystemReset();
+} /*** end of BootActivate ***/
+
+
+#if (BOOT_COM_RS232_ENABLE > 0)
+/****************************************************************************************
+*     U N I V E R S A L   A S Y N C H R O N O U S   R X   T X   I N T E R F A C E
+****************************************************************************************/
+
+/****************************************************************************************
+* Macro definitions
+****************************************************************************************/
+/** \brief Timeout time for the reception of a CTO packet. The timer is started upon
+ *         reception of the first packet byte.
+ */
+#define RS232_CTO_RX_PACKET_TIMEOUT_MS (100u)
+
+
+/****************************************************************************************
+* Local data declarations
+****************************************************************************************/
+/** \brief UART handle to be used in API calls. */
+static UART_HandleTypeDef rs232Handle;
+
+
+/****************************************************************************************
+* Function prototypes
+****************************************************************************************/
+static unsigned char Rs232ReceiveByte(unsigned char *data);
+
+
+/************************************************************************************//**
+** \brief     Initializes the UART communication interface.
+** \return    none.
+**
+****************************************************************************************/
+static void BootComRs232Init(void)
+{
+  /* Configure UART peripheral. */
+  rs232Handle.Instance        = USART3;
+  rs232Handle.Init.BaudRate   = BOOT_COM_RS232_BAUDRATE;
+  rs232Handle.Init.WordLength = UART_WORDLENGTH_8B;
+  rs232Handle.Init.StopBits = UART_STOPBITS_1;
+  rs232Handle.Init.Parity = UART_PARITY_NONE;
+  rs232Handle.Init.Mode = UART_MODE_TX_RX;
+  rs232Handle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  rs232Handle.Init.OverSampling = UART_OVERSAMPLING_16;
+  rs232Handle.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+  rs232Handle.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  /* Initialize the UART peripheral. */
+  HAL_UART_Init(&rs232Handle);
+} /*** end of BootComRs232Init ***/
+
+
+/************************************************************************************//**
+** \brief     Receives the CONNECT request from the host, which indicates that the
+**            bootloader should be activated and, if so, activates it.
+** \return    none.
+**
+****************************************************************************************/
+static void BootComRs232CheckActivationRequest(void)
+{
+  static unsigned char xcpCtoReqPacket[BOOT_COM_RS232_RX_MAX_DATA+1];
+  static unsigned char xcpCtoRxLength;
+  static unsigned char xcpCtoRxInProgress = 0;
+  static unsigned long xcpCtoRxStartTime = 0;
+
+  /* start of cto packet received? */
+  if (xcpCtoRxInProgress == 0)
+  {
+    /* store the message length when received */
+    if (Rs232ReceiveByte(&xcpCtoReqPacket[0]) == 1)
+    {
+      /* check that the length has a valid value. it should not be 0 */
+      if ( (xcpCtoReqPacket[0] > 0) &&
+           (xcpCtoReqPacket[0] <= BOOT_COM_RS232_RX_MAX_DATA) )
+      {
+        /* store the start time */
+        xcpCtoRxStartTime = TimerGet();
+        /* indicate that a cto packet is being received */
+        xcpCtoRxInProgress = 1;
+        /* reset packet data count */
+        xcpCtoRxLength = 0;
+      }
+    }
+  }
+  else
+  {
+    /* store the next packet byte */
+    if (Rs232ReceiveByte(&xcpCtoReqPacket[xcpCtoRxLength+1]) == 1)
+    {
+      /* increment the packet data count */
+      xcpCtoRxLength++;
+
+      /* check to see if the entire packet was received */
+      if (xcpCtoRxLength == xcpCtoReqPacket[0])
+      {
+        /* done with cto packet reception */
+        xcpCtoRxInProgress = 0;
+
+        /* check if this was an XCP CONNECT command */
+        if ((xcpCtoReqPacket[1] == 0xff) && (xcpCtoRxLength == 2))
+        {
+          /* connection request received so start the bootloader */
+          BootActivate();
+        }
+      }
+    }
+    else
+    {
+      /* check packet reception timeout */
+      if (TimerGet() > (xcpCtoRxStartTime + RS232_CTO_RX_PACKET_TIMEOUT_MS))
+      {
+        /* cancel cto packet reception due to timeout. note that this automatically
+         * discards the already received packet bytes, allowing the host to retry.
+         */
+        xcpCtoRxInProgress = 0;
+      }
+    }
+  }
+} /*** end of BootComRs232CheckActivationRequest ***/
+
+
+/************************************************************************************//**
+** \brief     Receives a communication interface byte if one is present.
+** \param     data Pointer to byte where the data is to be stored.
+** \return    1 if a byte was received, 0 otherwise.
+**
+****************************************************************************************/
+static unsigned char Rs232ReceiveByte(unsigned char *data)
+{
+  HAL_StatusTypeDef result;
+
+  /* receive a byte in a non-blocking manner */
+  result = HAL_UART_Receive(&rs232Handle, data, 1, 0);
+  /* process the result */
+  if (result == HAL_OK)
+  {
+    /* success */
+    return 1;
+  }
+  /* error occurred */
+  return 0;
+} /*** end of Rs232ReceiveByte ***/
+#endif /* BOOT_COM_RS232_ENABLE > 0 */
+
+
+#if (BOOT_COM_CAN_ENABLE > 0)
+/****************************************************************************************
+*        C O N T R O L L E R   A R E A   N E T W O R K   I N T E R F A C E
+****************************************************************************************/
+
+/****************************************************************************************
+* Type definitions
+****************************************************************************************/
+/** \brief Structure type for grouping CAN bus timing related information. */
+typedef struct t_can_bus_timing
+{
+  unsigned char tseg1;                                /**< CAN time segment 1          */
+  unsigned char tseg2;                                /**< CAN time segment 2          */
+} tCanBusTiming;
+
+
+/****************************************************************************************
+* Local constant declarations
+****************************************************************************************/
+/** \brief CAN bittiming table for dynamically calculating the bittiming settings.
+ *  \details According to the CAN protocol 1 bit-time can be made up of between 8..25
+ *           time quanta (TQ). The total TQ in a bit is SYNC + TSEG1 + TSEG2 with SYNC
+ *           always being 1. The sample point is (SYNC + TSEG1) / (SYNC + TSEG1 + SEG2) *
+ *           100%. This array contains possible and valid time quanta configurations with
+ *           a sample point between 68..78%.
+ */
+static const tCanBusTiming canTiming[] =
+{                       /*  TQ | TSEG1 | TSEG2 | SP  */
+                        /* ------------------------- */
+    {  5, 2 },          /*   8 |   5   |   2   | 75% */
+    {  6, 2 },          /*   9 |   6   |   2   | 78% */
+    {  6, 3 },          /*  10 |   6   |   3   | 70% */
+    {  7, 3 },          /*  11 |   7   |   3   | 73% */
+    {  8, 3 },          /*  12 |   8   |   3   | 75% */
+    {  9, 3 },          /*  13 |   9   |   3   | 77% */
+    {  9, 4 },          /*  14 |   9   |   4   | 71% */
+    { 10, 4 },          /*  15 |  10   |   4   | 73% */
+    { 11, 4 },          /*  16 |  11   |   4   | 75% */
+    { 12, 4 },          /*  17 |  12   |   4   | 76% */
+    { 12, 5 },          /*  18 |  12   |   5   | 72% */
+    { 13, 5 },          /*  19 |  13   |   5   | 74% */
+    { 14, 5 },          /*  20 |  14   |   5   | 75% */
+    { 15, 5 },          /*  21 |  15   |   5   | 76% */
+    { 15, 6 },          /*  22 |  15   |   6   | 73% */
+    { 16, 6 },          /*  23 |  16   |   6   | 74% */
+    { 16, 7 },          /*  24 |  16   |   7   | 71% */
+    { 16, 8 }           /*  25 |  16   |   8   | 68% */
+};
+
+
+/****************************************************************************************
+* Local data declarations
+****************************************************************************************/
+/** \brief CAN handle to be used in API calls. */
+static FDCAN_HandleTypeDef canHandle;
+
+
+/************************************************************************************//**
+** \brief     Search algorithm to match the desired baudrate to a possible bus
+**            timing configuration.
+** \param     baud The desired baudrate in kbps. Valid values are 10..1000.
+** \param     prescaler Pointer to where the value for the prescaler will be stored.
+** \param     tseg1 Pointer to where the value for TSEG2 will be stored.
+** \param     tseg2 Pointer to where the value for TSEG2 will be stored.
+** \return    1 if the CAN bustiming register values were found, 0 otherwise.
+**
+****************************************************************************************/
+static unsigned char CanGetSpeedConfig(unsigned short baud, unsigned short *prescaler,
+                                       unsigned char *tseg1, unsigned char *tseg2)
+{
+  unsigned char cnt;
+  unsigned long canClockFreqkHz;
+
+  /* store CAN peripheral clock speed in kHz */
+  canClockFreqkHz = BOOT_CPU_XTAL_SPEED_KHZ;
+
+  /* loop through all possible time quanta configurations to find a match */
+  for (cnt=0; cnt < sizeof(canTiming)/sizeof(canTiming[0]); cnt++)
+  {
+    if ((canClockFreqkHz % (baud*(canTiming[cnt].tseg1+canTiming[cnt].tseg2+1))) == 0)
+    {
+      /* compute the prescaler that goes with this TQ configuration */
+      *prescaler = canClockFreqkHz/(baud*(canTiming[cnt].tseg1+canTiming[cnt].tseg2+1));
+
+      /* make sure the prescaler is valid */
+      if ( (*prescaler > 0) && (*prescaler <= 512) )
+      {
+        /* store the bustiming configuration */
+        *tseg1 = canTiming[cnt].tseg1;
+        *tseg2 = canTiming[cnt].tseg2;
+        /* found a good bus timing configuration */
+        return 1;
+      }
+    }
+  }
+  /* could not find a good bus timing configuration */
+  return 0;
+} /*** end of CanGetSpeedConfig ***/
+
+
+/************************************************************************************//**
+** \brief     Initializes the CAN communication interface.
+** \return    none.
+**
+****************************************************************************************/
+static void BootComCanInit(void)
+{
+  unsigned short prescaler = 0;
+  unsigned char tseg1 = 0, tseg2 = 0;
+  FDCAN_FilterTypeDef filterConfig;
+  unsigned long rxMsgId = BOOT_COM_CAN_RX_MSG_ID;
+
+  /* obtain bittiming configuration information. */
+  CanGetSpeedConfig(BOOT_COM_CAN_BAUDRATE/1000, &prescaler, &tseg1, &tseg2);
+
+  /* set the CAN controller configuration. */
+  canHandle.Instance = FDCAN1;
+  canHandle.Init.FrameFormat = FDCAN_FRAME_CLASSIC;
+  canHandle.Init.Mode = FDCAN_MODE_NORMAL;
+  canHandle.Init.AutoRetransmission = ENABLE;
+  canHandle.Init.TransmitPause = DISABLE;
+  canHandle.Init.ProtocolException = DISABLE;
+  canHandle.Init.NominalPrescaler = prescaler;
+  canHandle.Init.NominalSyncJumpWidth = 1;
+  canHandle.Init.NominalTimeSeg1 = tseg1;
+  canHandle.Init.NominalTimeSeg2 = tseg2;
+  /* FD mode is not used by this driver, so the .Init.DataXxx values are don't care. */
+  canHandle.Init.DataPrescaler = 1;
+  canHandle.Init.DataSyncJumpWidth = 1;
+  canHandle.Init.DataTimeSeg1 = 1;
+  canHandle.Init.DataTimeSeg2 = 1;
+  canHandle.Init.MessageRAMOffset = 0;
+  /* does the message to be received have a standard 11-bit CAN identifier? */
+  if ((rxMsgId & 0x80000000) == 0)
+  {
+    canHandle.Init.StdFiltersNbr = 1;
+    canHandle.Init.ExtFiltersNbr = 0;
+  }
+  else
+  {
+    canHandle.Init.StdFiltersNbr = 0;
+    canHandle.Init.ExtFiltersNbr = 1;
+  }
+  /* only reception FIFO 0 is used. */
+  canHandle.Init.RxFifo0ElmtsNbr = 1;
+  canHandle.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_8;
+  canHandle.Init.RxFifo1ElmtsNbr = 0;
+  canHandle.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_8;
+  canHandle.Init.RxBuffersNbr = 0;
+  canHandle.Init.RxBufferSize = FDCAN_DATA_BYTES_8;
+  /* no transmit buffer is needed. transmit FIFO is not used. */
+  canHandle.Init.TxEventsNbr = 0;
+  canHandle.Init.TxBuffersNbr = 0;
+  canHandle.Init.TxFifoQueueElmtsNbr = 0;
+  canHandle.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION;
+  canHandle.Init.TxElmtSize = FDCAN_DATA_BYTES_8;
+  /* initialize the CAN controller. this only fails if the CAN controller hardware is
+   * faulty. no need to evaluate the return value as there is nothing we can do about
+   * a faulty CAN controller.
+   */
+  (void)HAL_FDCAN_Init(&canHandle);
+
+  /* configure the reception filter. note that the implementation of this function
+   * always returns HAL_OK as long as the CAN controller is initialized, so no need to
+   * evaluate the return value.
+   */
+  if ((rxMsgId & 0x80000000) == 0)
+  {
+    filterConfig.IdType = FDCAN_STANDARD_ID;
+  }
+  else
+  {
+    filterConfig.IdType = FDCAN_EXTENDED_ID;
+    /* negate the ID-type bit */
+    rxMsgId &= ~0x80000000;
+  }
+  filterConfig.FilterIndex = 0;
+  filterConfig.FilterType = FDCAN_FILTER_DUAL;
+  filterConfig.FilterConfig = FDCAN_FILTER_TO_RXFIFO0;
+  filterConfig.FilterID1 = rxMsgId;
+  filterConfig.FilterID2 = rxMsgId;
+  filterConfig.RxBufferIndex = 0;
+  (void)HAL_FDCAN_ConfigFilter(&canHandle, &filterConfig);
+
+  /* configure global filter to reject all non-matching frames. */
+  HAL_FDCAN_ConfigGlobalFilter(&canHandle, FDCAN_REJECT, FDCAN_REJECT, 
+                               FDCAN_REJECT_REMOTE, FDCAN_REJECT_REMOTE);
+  
+  /* start the CAN peripheral. no need to evaluate the return value as there is nothing
+   * we can do about a faulty CAN controller. */
+  (void)HAL_FDCAN_Start(&canHandle);
+} /*** end of BootComCanInit ***/
+
+
+/************************************************************************************//**
+** \brief     Receives the CONNECT request from the host, which indicates that the
+**            bootloader should be activated and, if so, activates it.
+** \return    none.
+**
+****************************************************************************************/
+static void BootComCanCheckActivationRequest(void)
+{
+  unsigned long rxMsgId = BOOT_COM_CAN_RX_MSG_ID;
+  unsigned char packetIdMatches = 0;
+  FDCAN_RxHeaderTypeDef rxMsgHeader;
+  unsigned char rxMsgData[8];
+  unsigned char rxMsgLen;
+  HAL_StatusTypeDef rxStatus = HAL_ERROR;
+
+
+  /* poll for received CAN messages that await processing. */
+  if (HAL_FDCAN_GetRxFifoFillLevel(&canHandle, FDCAN_RX_FIFO0) > 0)
+  {
+    /* attempt to read the newly received CAN message from its buffer. */
+    rxStatus = HAL_FDCAN_GetRxMessage(&canHandle, FDCAN_RX_FIFO0, &rxMsgHeader,
+                                      rxMsgData);
+  }
+
+  /* only continue processing the CAN message if something was received. */
+  if (rxStatus == HAL_OK)
+  {
+    /* check if this message has the configured CAN packet identifier. */
+    if ((rxMsgId & 0x80000000) == 0)
+    {
+      /* was an 11-bit CAN message received that matches? */
+      if ( (rxMsgHeader.Identifier == rxMsgId) &&
+           (rxMsgHeader.IdType == FDCAN_STANDARD_ID) )
+      {
+        /* set flag that a packet with a matching CAN identifier was received. */
+        packetIdMatches = 1;
+      }
+    }
+    else
+    {
+      /* negate the ID-type bit */
+      rxMsgId &= ~0x80000000;
+      /* was an 29-bit CAN message received that matches? */
+      if ( (rxMsgHeader.Identifier == rxMsgId) &&
+           (rxMsgHeader.IdType == FDCAN_EXTENDED_ID) )
+      {
+        /* set flag that a packet with a matching CAN identifier was received. */
+        packetIdMatches = 1;
+      }
+    }
+
+    /* only continue if a packet with a matching CAN identifier was received. */
+    if (packetIdMatches == 1)
+    {
+      /* obtain the CAN message length. */
+      rxMsgLen = (unsigned char)(rxMsgHeader.DataLength >> 16U);
+      /* check if this was an XCP CONNECT command */
+      if ((rxMsgData[0] == 0xff) && (rxMsgLen == 2))
+      {
+        /* connection request received so start the bootloader */
+        BootActivate();
+      }
+    }
+  }
+} /*** end of BootComCanCheckActivationRequest ***/
+#endif /* BOOT_COM_CAN_ENABLE > 0 */
+
+
+/*********************************** end of boot.c *************************************/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/boot.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/boot.h
new file mode 100644
index 00000000..61f7cffa
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/boot.h
@@ -0,0 +1,40 @@
+/************************************************************************************//**
+* \file         Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/boot.h
+* \brief        Demo program bootloader interface header file.
+* \ingroup      Prog_ARMCM7_STM32H7_Nucleo_H743ZI_Keil
+* \internal
+*----------------------------------------------------------------------------------------
+*                          C O P Y R I G H T
+*----------------------------------------------------------------------------------------
+*   Copyright (c) 2020  by Feaser    http://www.feaser.com    All rights reserved
+*
+*----------------------------------------------------------------------------------------
+*                            L I C E N S E
+*----------------------------------------------------------------------------------------
+* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as published by the Free
+* Software Foundation, either version 3 of the License, or (at your option) any later
+* version.
+*
+* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+* PURPOSE. See the GNU General Public License for more details.
+*
+* You have received a copy of the GNU General Public License along with OpenBLT. It
+* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
+*
+* \endinternal
+****************************************************************************************/
+#ifndef BOOT_H
+#define BOOT_H
+
+/****************************************************************************************
+* Function prototypes
+****************************************************************************************/
+void BootComInit(void);
+void BootComCheckActivationRequest(void);
+void BootActivate(void);
+
+
+#endif /* BOOT_H */
+/*********************************** end of boot.h *************************************/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/header.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/header.h
new file mode 100644
index 00000000..c2344e93
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/header.h
@@ -0,0 +1,42 @@
+/************************************************************************************//**
+* \file         Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/header.h
+* \brief        Generic header file.
+* \ingroup      Prog_ARMCM7_STM32H7_Nucleo_H743ZI_Keil
+* \internal
+*----------------------------------------------------------------------------------------
+*                          C O P Y R I G H T
+*----------------------------------------------------------------------------------------
+*   Copyright (c) 2020  by Feaser    http://www.feaser.com    All rights reserved
+*
+*----------------------------------------------------------------------------------------
+*                            L I C E N S E
+*----------------------------------------------------------------------------------------
+* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as published by the Free
+* Software Foundation, either version 3 of the License, or (at your option) any later
+* version.
+*
+* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+* PURPOSE. See the GNU General Public License for more details.
+*
+* You have received a copy of the GNU General Public License along with OpenBLT. It
+* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
+*
+* \endinternal
+****************************************************************************************/
+#ifndef HEADER_H
+#define HEADER_H
+
+/****************************************************************************************
+* Include files
+****************************************************************************************/
+#include "../Boot/blt_conf.h"                          /* bootloader configuration     */
+#include "stm32h7xx.h"                                 /* STM32 CPU and HAL header     */
+#include "boot.h"                                      /* bootloader interface driver  */
+#include "led.h"                                       /* LED driver                   */
+#include "timer.h"                                     /* Timer driver                 */
+
+
+#endif /* HEADER_H */
+/*********************************** end of header.h ***********************************/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/ide/stm32h743.uvoptx b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/ide/stm32h743.uvoptx
new file mode 100644
index 00000000..b0ce965c
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/ide/stm32h743.uvoptx
@@ -0,0 +1,1160 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj; *.o</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>Target</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>16000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath></ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>18</CpuCode>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>1</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <bEvRecOn>1</bEvRecOn>
+        <bSchkAxf>0</bSchkAxf>
+        <bTchkAxf>0</bTchkAxf>
+        <nTsel>5</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>STLink\ST-LINKIII-KEIL_SWO.dll</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC8000 -FN1 -FF0STM32H7x_2048 -FS08000000 -FL0200000 -FP0($$Device:STM32H743ZITx$CMSIS\Flash\STM32H7x_2048.FLM))</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ST-LINKIII-KEIL_SWO</Key>
+          <Name>-U-O142 -O2254 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(5BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32H7x_2048.FLM -FS08000000 -FL0200000 -FP0($$Device:STM32H743ZITx$CMSIS\Flash\STM32H7x_2048.FLM)</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>1</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+      <bAutoGenD>0</bAutoGenD>
+      <LntExFlags>0</LntExFlags>
+      <pMisraName></pMisraName>
+      <pszMrule></pszMrule>
+      <pSingCmds></pSingCmds>
+      <pMultCmds></pMultCmds>
+      <pMisraNamep></pMisraNamep>
+      <pszMrulep></pszMrulep>
+      <pSingCmdsp></pSingCmdsp>
+      <pMultCmdsp></pMultCmdsp>
+      <DebugDescription>
+        <Enable>1</Enable>
+        <EnableFlashSeq>1</EnableFlashSeq>
+        <EnableLog>0</EnableLog>
+        <Protocol>2</Protocol>
+        <DbgClock>10000000</DbgClock>
+      </DebugDescription>
+    </TargetOption>
+  </Target>
+
+  <Group>
+    <GroupName>App</GroupName>
+    <tvExp>1</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>1</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\boot.c</PathWithFileName>
+      <FilenameWithoutPath>boot.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>2</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\boot.h</PathWithFileName>
+      <FilenameWithoutPath>boot.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>3</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\header.h</PathWithFileName>
+      <FilenameWithoutPath>header.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>4</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\led.c</PathWithFileName>
+      <FilenameWithoutPath>led.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>5</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\led.h</PathWithFileName>
+      <FilenameWithoutPath>led.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>6</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\main.c</PathWithFileName>
+      <FilenameWithoutPath>main.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>7</FileNumber>
+      <FileType>2</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\startup_stm32h743xx.s</PathWithFileName>
+      <FilenameWithoutPath>startup_stm32h743xx.s</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>8</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\timer.c</PathWithFileName>
+      <FilenameWithoutPath>timer.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>9</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\timer.h</PathWithFileName>
+      <FilenameWithoutPath>timer.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>Lib</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>10</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\stm32h7xx_hal_conf.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_conf.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>11</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\system_stm32h7xx.c</PathWithFileName>
+      <FilenameWithoutPath>system_stm32h7xx.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>12</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Device\ST\STM32H7xx\Include\stm32h7xx.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>13</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Device\ST\STM32H7xx\Include\stm32h743xx.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h743xx.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>14</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Device\ST\STM32H7xx\Include\system_stm32h7xx.h</PathWithFileName>
+      <FilenameWithoutPath>system_stm32h7xx.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>15</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Include\cmsis_armcc.h</PathWithFileName>
+      <FilenameWithoutPath>cmsis_armcc.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>16</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Include\cmsis_armclang.h</PathWithFileName>
+      <FilenameWithoutPath>cmsis_armclang.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>17</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Include\cmsis_compiler.h</PathWithFileName>
+      <FilenameWithoutPath>cmsis_compiler.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>18</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Include\cmsis_gcc.h</PathWithFileName>
+      <FilenameWithoutPath>cmsis_gcc.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>19</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Include\cmsis_iccarm.h</PathWithFileName>
+      <FilenameWithoutPath>cmsis_iccarm.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>20</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Include\cmsis_version.h</PathWithFileName>
+      <FilenameWithoutPath>cmsis_version.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>21</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Include\core_armv8mbl.h</PathWithFileName>
+      <FilenameWithoutPath>core_armv8mbl.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>22</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Include\core_armv8mml.h</PathWithFileName>
+      <FilenameWithoutPath>core_armv8mml.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>23</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Include\core_cm0.h</PathWithFileName>
+      <FilenameWithoutPath>core_cm0.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>24</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Include\core_cm0plus.h</PathWithFileName>
+      <FilenameWithoutPath>core_cm0plus.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>25</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Include\core_cm1.h</PathWithFileName>
+      <FilenameWithoutPath>core_cm1.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>26</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Include\core_cm3.h</PathWithFileName>
+      <FilenameWithoutPath>core_cm3.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>27</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Include\core_cm4.h</PathWithFileName>
+      <FilenameWithoutPath>core_cm4.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>28</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Include\core_cm7.h</PathWithFileName>
+      <FilenameWithoutPath>core_cm7.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>29</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Include\core_cm23.h</PathWithFileName>
+      <FilenameWithoutPath>core_cm23.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>30</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Include\core_cm33.h</PathWithFileName>
+      <FilenameWithoutPath>core_cm33.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>31</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Include\core_sc000.h</PathWithFileName>
+      <FilenameWithoutPath>core_sc000.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>32</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Include\core_sc300.h</PathWithFileName>
+      <FilenameWithoutPath>core_sc300.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>33</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Include\mpu_armv7.h</PathWithFileName>
+      <FilenameWithoutPath>mpu_armv7.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>34</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Include\mpu_armv8.h</PathWithFileName>
+      <FilenameWithoutPath>mpu_armv8.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>35</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\CMSIS\Include\tz_context.h</PathWithFileName>
+      <FilenameWithoutPath>tz_context.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>36</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>37</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_cortex.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_cortex.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>38</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_def.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_def.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>39</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dma.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_dma.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>40</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dma_ex.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_dma_ex.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>41</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_exti.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_exti.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>42</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_fdcan.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_fdcan.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>43</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_flash.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_flash.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>44</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_flash_ex.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_flash_ex.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>45</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_gpio.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_gpio.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>46</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_gpio_ex.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_gpio_ex.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>47</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_hsem.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_hsem.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>48</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_i2c.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_i2c.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>49</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_i2c_ex.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_i2c_ex.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>50</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_mdma.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_mdma.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>51</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pwr.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_pwr.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>52</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pwr_ex.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_pwr_ex.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>53</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_rcc.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_rcc.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>54</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_rcc_ex.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_rcc_ex.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>55</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_tim.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_tim.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>56</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_tim_ex.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_tim_ex.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>57</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_uart.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_uart.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>58</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_uart_ex.h</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_uart_ex.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>59</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h</PathWithFileName>
+      <FilenameWithoutPath>stm32_hal_legacy.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>60</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>61</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cortex.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_cortex.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>62</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_dma.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>63</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma_ex.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_dma_ex.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>64</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_exti.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_exti.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>65</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_fdcan.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_fdcan.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>66</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_flash.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>67</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash_ex.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_flash_ex.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>68</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_gpio.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_gpio.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>69</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hsem.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_hsem.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>70</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_i2c.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>71</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c_ex.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_i2c_ex.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>72</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mdma.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_mdma.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>73</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_pwr.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>74</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr_ex.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_pwr_ex.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>75</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_rcc.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>76</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc_ex.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_rcc_ex.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>77</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_tim.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>78</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim_ex.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_tim_ex.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>79</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_uart.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_uart.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>80</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_uart_ex.c</PathWithFileName>
+      <FilenameWithoutPath>stm32h7xx_hal_uart_ex.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+</ProjectOpt>
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/ide/stm32h743.uvprojx b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/ide/stm32h743.uvprojx
new file mode 100644
index 00000000..acafb21c
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/ide/stm32h743.uvprojx
@@ -0,0 +1,802 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>Target</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
+      <uAC6>0</uAC6>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>STM32H743ZITx</Device>
+          <Vendor>STMicroelectronics</Vendor>
+          <PackID>Keil.STM32H7xx_DFP.2.4.0</PackID>
+          <PackURL>https://www.keil.com/pack/</PackURL>
+          <Cpu>IRAM(0x20000000-0x2001FFFF) IRAM2(0x24000000-0x2407FFFF) IROM(0x8000000-0x81FFFFF) CLOCK(12000000) FPU3(DFPU) CPUTYPE("Cortex-M7") ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll></FlashDriverDll>
+          <DeviceId></DeviceId>
+          <RegisterFile></RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:STM32H743ZITx$CMSIS\SVD\STM32H743.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>..\bin\</OutputDirectory>
+          <OutputName>demoprog_stm32h743</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath></ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>1</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name>fromelf --m32 --output=..\bin\demoprog_stm32h743.srec ..\bin\demoprog_stm32h743.axf</UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>0</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>-REMAP -MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM7</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments>-MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM7</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4107</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>STLink\ST-LINKIII-KEIL_SWO.dll</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M7"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>3</RvdsVP>
+            <RvdsMve>0</RvdsMve>
+            <hadIRAM2>1</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>1</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x200000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x200000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x24000000</StartAddress>
+                <Size>0x80000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>2</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <uGnu>0</uGnu>
+            <useXO>0</useXO>
+            <v6Lang>1</v6Lang>
+            <v6LangP>1</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls>--diag_suppress=111</MiscControls>
+              <Define>USE_HAL_DRIVER,STM32H743xx</Define>
+              <Undefine></Undefine>
+              <IncludePath>..\..\Prog;..\lib;..\lib\CMSIS\Device\ST\STM32H7xx\Include;..\lib\CMSIS\Include;..\lib\STM32H7xx_HAL_Driver\Inc;..\lib\STM32H7xx_HAL_Driver\Inc\Legacy</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <uClangAs>0</uClangAs>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x08000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile>..\stm32h743.sct</ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>App</GroupName>
+          <Files>
+            <File>
+              <FileName>boot.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\boot.c</FilePath>
+            </File>
+            <File>
+              <FileName>boot.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\boot.h</FilePath>
+            </File>
+            <File>
+              <FileName>header.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\header.h</FilePath>
+            </File>
+            <File>
+              <FileName>led.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\led.c</FilePath>
+            </File>
+            <File>
+              <FileName>led.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\led.h</FilePath>
+            </File>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\main.c</FilePath>
+            </File>
+            <File>
+              <FileName>startup_stm32h743xx.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\startup_stm32h743xx.s</FilePath>
+            </File>
+            <File>
+              <FileName>timer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\timer.c</FilePath>
+            </File>
+            <File>
+              <FileName>timer.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\timer.h</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Lib</GroupName>
+          <Files>
+            <File>
+              <FileName>stm32h7xx_hal_conf.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\stm32h7xx_hal_conf.h</FilePath>
+            </File>
+            <File>
+              <FileName>system_stm32h7xx.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\system_stm32h7xx.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Device\ST\STM32H7xx\Include\stm32h7xx.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h743xx.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Device\ST\STM32H7xx\Include\stm32h743xx.h</FilePath>
+            </File>
+            <File>
+              <FileName>system_stm32h7xx.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Device\ST\STM32H7xx\Include\system_stm32h7xx.h</FilePath>
+            </File>
+            <File>
+              <FileName>cmsis_armcc.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Include\cmsis_armcc.h</FilePath>
+            </File>
+            <File>
+              <FileName>cmsis_armclang.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Include\cmsis_armclang.h</FilePath>
+            </File>
+            <File>
+              <FileName>cmsis_compiler.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Include\cmsis_compiler.h</FilePath>
+            </File>
+            <File>
+              <FileName>cmsis_gcc.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Include\cmsis_gcc.h</FilePath>
+            </File>
+            <File>
+              <FileName>cmsis_iccarm.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Include\cmsis_iccarm.h</FilePath>
+            </File>
+            <File>
+              <FileName>cmsis_version.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Include\cmsis_version.h</FilePath>
+            </File>
+            <File>
+              <FileName>core_armv8mbl.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Include\core_armv8mbl.h</FilePath>
+            </File>
+            <File>
+              <FileName>core_armv8mml.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Include\core_armv8mml.h</FilePath>
+            </File>
+            <File>
+              <FileName>core_cm0.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Include\core_cm0.h</FilePath>
+            </File>
+            <File>
+              <FileName>core_cm0plus.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Include\core_cm0plus.h</FilePath>
+            </File>
+            <File>
+              <FileName>core_cm1.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Include\core_cm1.h</FilePath>
+            </File>
+            <File>
+              <FileName>core_cm3.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Include\core_cm3.h</FilePath>
+            </File>
+            <File>
+              <FileName>core_cm4.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Include\core_cm4.h</FilePath>
+            </File>
+            <File>
+              <FileName>core_cm7.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Include\core_cm7.h</FilePath>
+            </File>
+            <File>
+              <FileName>core_cm23.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Include\core_cm23.h</FilePath>
+            </File>
+            <File>
+              <FileName>core_cm33.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Include\core_cm33.h</FilePath>
+            </File>
+            <File>
+              <FileName>core_sc000.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Include\core_sc000.h</FilePath>
+            </File>
+            <File>
+              <FileName>core_sc300.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Include\core_sc300.h</FilePath>
+            </File>
+            <File>
+              <FileName>mpu_armv7.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Include\mpu_armv7.h</FilePath>
+            </File>
+            <File>
+              <FileName>mpu_armv8.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Include\mpu_armv8.h</FilePath>
+            </File>
+            <File>
+              <FileName>tz_context.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\CMSIS\Include\tz_context.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_cortex.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_cortex.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_def.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_def.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_dma.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dma.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_dma_ex.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dma_ex.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_exti.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_exti.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_fdcan.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_fdcan.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_flash.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_flash.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_flash_ex.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_flash_ex.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_gpio.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_gpio.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_gpio_ex.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_gpio_ex.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_hsem.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_hsem.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_i2c.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_i2c.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_i2c_ex.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_i2c_ex.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_mdma.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_mdma.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_pwr.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pwr.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_pwr_ex.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pwr_ex.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_rcc.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_rcc.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_rcc_ex.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_rcc_ex.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_tim.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_tim.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_tim_ex.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_tim_ex.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_uart.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_uart.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_uart_ex.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_uart_ex.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32_hal_legacy.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_cortex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cortex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_dma.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_dma_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma_ex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_exti.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_exti.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_fdcan.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_fdcan.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_flash.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_flash_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash_ex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_gpio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_gpio.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_hsem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hsem.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_i2c.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_i2c_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c_ex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_mdma.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mdma.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_pwr.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_pwr_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr_ex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_rcc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_rcc_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc_ex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_tim.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_tim_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim_ex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_uart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_uart.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_uart_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\lib\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_uart_ex.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components/>
+    <files/>
+  </RTE>
+
+</Project>
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/led.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/led.c
new file mode 100644
index 00000000..040e5351
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/led.c
@@ -0,0 +1,94 @@
+/************************************************************************************//**
+* \file         Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/led.c
+* \brief        LED driver source file.
+* \ingroup      Prog_ARMCM7_STM32H7_Nucleo_H743ZI_Keil
+* \internal
+*----------------------------------------------------------------------------------------
+*                          C O P Y R I G H T
+*----------------------------------------------------------------------------------------
+*   Copyright (c) 2020  by Feaser    http://www.feaser.com    All rights reserved
+*
+*----------------------------------------------------------------------------------------
+*                            L I C E N S E
+*----------------------------------------------------------------------------------------
+* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as published by the Free
+* Software Foundation, either version 3 of the License, or (at your option) any later
+* version.
+*
+* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+* PURPOSE. See the GNU General Public License for more details.
+*
+* You have received a copy of the GNU General Public License along with OpenBLT. It
+* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
+*
+* \endinternal
+****************************************************************************************/
+
+/****************************************************************************************
+* Include files
+****************************************************************************************/
+#include "header.h"                                    /* generic header               */
+
+
+/****************************************************************************************
+* Macro definitions
+****************************************************************************************/
+/** \brief Toggle interval time in milliseconds. */
+#define LED_TOGGLE_MS  (500)
+
+
+/************************************************************************************//**
+** \brief     Initializes the LED. 
+** \return    none.
+**
+****************************************************************************************/
+void LedInit(void)
+{
+  /* Note that the initialization of the LED GPIO pin is done in HAL_MspInit(). All that
+   * is left to do here is to make sure the LED is turned off after initialization.
+   */
+  HAL_GPIO_WritePin(GPIOB, GPIO_PIN_7, GPIO_PIN_RESET);
+} /*** end of LedInit ***/
+
+
+/************************************************************************************//**
+** \brief     Toggles the LED at a fixed time interval.
+** \return    none.
+**
+****************************************************************************************/
+void LedToggle(void)
+{
+  static unsigned char led_toggle_state = 0;
+  static unsigned long timer_counter_last = 0;
+  unsigned long timer_counter_now;
+
+  /* check if toggle interval time passed */
+  timer_counter_now = TimerGet();
+  if ( (timer_counter_now - timer_counter_last) < LED_TOGGLE_MS)
+  {
+    /* not yet time to toggle */
+    return;
+  }
+
+  /* determine toggle action */
+  if (led_toggle_state == 0)
+  {
+    led_toggle_state = 1;
+    /* turn the LED on */
+    HAL_GPIO_WritePin(GPIOB, GPIO_PIN_7, GPIO_PIN_SET);
+  }
+  else
+  {
+    led_toggle_state = 0;
+    /* turn the LED off */
+    HAL_GPIO_WritePin(GPIOB, GPIO_PIN_7, GPIO_PIN_RESET);
+  }
+
+  /* store toggle time to determine next toggle interval */
+  timer_counter_last = timer_counter_now;
+} /*** end of LedToggle ***/
+
+
+/*********************************** end of led.c **************************************/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/led.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/led.h
new file mode 100644
index 00000000..75966ccb
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/led.h
@@ -0,0 +1,39 @@
+/************************************************************************************//**
+* \file         Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/led.h
+* \brief        LED driver header file.
+* \ingroup      Prog_ARMCM7_STM32H7_Nucleo_H743ZI_Keil
+* \internal
+*----------------------------------------------------------------------------------------
+*                          C O P Y R I G H T
+*----------------------------------------------------------------------------------------
+*   Copyright (c) 2020  by Feaser    http://www.feaser.com    All rights reserved
+*
+*----------------------------------------------------------------------------------------
+*                            L I C E N S E
+*----------------------------------------------------------------------------------------
+* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as published by the Free
+* Software Foundation, either version 3 of the License, or (at your option) any later
+* version.
+*
+* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+* PURPOSE. See the GNU General Public License for more details.
+*
+* You have received a copy of the GNU General Public License along with OpenBLT. It
+* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
+*
+* \endinternal
+****************************************************************************************/
+#ifndef LED_H
+#define LED_H
+
+/****************************************************************************************
+* Function prototypes
+****************************************************************************************/
+void LedInit(void);
+void LedToggle(void);
+
+
+#endif /* LED_H */
+/*********************************** end of led.h **************************************/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h
new file mode 100644
index 00000000..cdcde7d9
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h
@@ -0,0 +1,26288 @@
+/**
+  ******************************************************************************
+  * @file    stm32h743xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32H743xx Device Peripheral Access Layer Header File.
+  *
+  *          This file contains:
+  *           - Data structures and the address mapping for all peripherals
+  *           - Peripheral's registers declarations and bits definition
+  *           - Macros to access peripheral's registers hardware
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS_Device
+  * @{
+  */
+
+/** @addtogroup stm32h743xx
+  * @{
+  */
+
+#ifndef STM32H743xx_H
+#define STM32H743xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+  * @{
+  */
+
+/**
+ * @brief STM32H7XX Interrupt Number Definition, according to the selected device
+ *        in @ref Library_configuration_section
+ */
+typedef enum
+{
+/******  Cortex-M Processor Exceptions Numbers *****************************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
+  HardFault_IRQn              = -13,    /*!< 4 Cortex-M Memory Management Interrupt                            */
+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M Memory Management Interrupt                            */
+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M Bus Fault Interrupt                                    */
+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M Usage Fault Interrupt                                  */
+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M SV Call Interrupt                                     */
+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M Debug Monitor Interrupt                               */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M Pend SV Interrupt                                     */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M System Tick Interrupt                                 */
+/******  STM32 specific Interrupt Numbers **********************************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it)                   */
+  PVD_AVD_IRQn                = 1,      /*!< PVD/AVD through EXTI Line detection Interrupt                     */
+  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
+  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
+  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
+  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
+  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
+  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
+  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
+  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
+  ADC_IRQn                    = 18,     /*!< ADC1 and  ADC2 global Interrupts                                  */
+  FDCAN1_IT0_IRQn             = 19,     /*!< FDCAN1 Interrupt line 0                                           */
+  FDCAN2_IT0_IRQn             = 20,     /*!< FDCAN2 Interrupt line 0                                           */
+  FDCAN1_IT1_IRQn             = 21,     /*!< FDCAN1 Interrupt line 1                                           */
+  FDCAN2_IT1_IRQn             = 22,     /*!< FDCAN2 Interrupt line 1                                           */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
+  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                              */
+  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                             */
+  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt                            */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
+  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
+  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
+  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
+  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
+  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
+  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */
+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
+  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
+  DMA2_Stream0_IRQn           = 56,     /*!<   DMA2 Stream 0 global Interrupt                                  */
+  DMA2_Stream1_IRQn           = 57,     /*!<   DMA2 Stream 1 global Interrupt                                  */
+  DMA2_Stream2_IRQn           = 58,     /*!<   DMA2 Stream 2 global Interrupt                                  */
+  DMA2_Stream3_IRQn           = 59,     /*!<   DMA2 Stream 3 global Interrupt                                  */
+  DMA2_Stream4_IRQn           = 60,     /*!<   DMA2 Stream 4 global Interrupt                                  */
+  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
+  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
+  FDCAN_CAL_IRQn              = 63,     /*!< FDCAN Calibration unit Interrupt                                  */
+  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
+  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
+  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
+  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
+  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
+  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
+  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
+  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
+  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
+  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
+  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
+  RNG_IRQn                    = 80,     /*!< RNG global interrupt                                              */
+  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
+  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */
+  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */
+  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
+  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */
+  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */
+  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */
+  LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                             */
+  LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                       */
+  DMA2D_IRQn                  = 90,     /*!< DMA2D global Interrupt                                            */
+  SAI2_IRQn                   = 91,     /*!< SAI2 global Interrupt                                             */
+  QUADSPI_IRQn                = 92,     /*!< Quad SPI global interrupt                                         */
+  LPTIM1_IRQn                 = 93,     /*!< LP TIM1 interrupt                                                 */
+  CEC_IRQn                    = 94,     /*!< HDMI-CEC global Interrupt                                         */
+  I2C4_EV_IRQn                = 95,     /*!< I2C4 Event Interrupt                                              */
+  I2C4_ER_IRQn                = 96,     /*!< I2C4 Error Interrupt                                              */
+  SPDIF_RX_IRQn               = 97,     /*!< SPDIF-RX global Interrupt                                         */
+  OTG_FS_EP1_OUT_IRQn         = 98,     /*!< USB OTG HS2 global interrupt                                      */
+  OTG_FS_EP1_IN_IRQn          = 99,     /*!< USB OTG HS2 End Point 1 Out global interrupt                      */
+  OTG_FS_WKUP_IRQn            = 100,    /*!< USB OTG HS2 End Point 1 In global interrupt                       */
+  OTG_FS_IRQn                 = 101,    /*!< USB OTG HS2 Wakeup through EXTI interrupt                         */
+  DMAMUX1_OVR_IRQn            = 102,    /*!<DMAMUX1 Overrun interrupt                                          */
+  HRTIM1_Master_IRQn          = 103,    /*!< HRTIM Master Timer global Interrupts                              */
+  HRTIM1_TIMA_IRQn            = 104,    /*!< HRTIM Timer A global Interrupt                                    */
+  HRTIM1_TIMB_IRQn            = 105,    /*!< HRTIM Timer B global Interrupt                                    */
+  HRTIM1_TIMC_IRQn            = 106,    /*!< HRTIM Timer C global Interrupt                                    */
+  HRTIM1_TIMD_IRQn            = 107,    /*!< HRTIM Timer D global Interrupt                                    */
+  HRTIM1_TIME_IRQn            = 108,    /*!< HRTIM Timer E global Interrupt                                    */
+  HRTIM1_FLT_IRQn             = 109,    /*!< HRTIM Fault global Interrupt                                      */
+  DFSDM1_FLT0_IRQn            = 110,    /*!<DFSDM Filter1 Interrupt                                            */
+  DFSDM1_FLT1_IRQn            = 111,    /*!<DFSDM Filter2 Interrupt                                            */
+  DFSDM1_FLT2_IRQn            = 112,    /*!<DFSDM Filter3 Interrupt                                            */
+  DFSDM1_FLT3_IRQn            = 113,    /*!<DFSDM Filter4 Interrupt                                            */
+  SAI3_IRQn                   = 114,    /*!< SAI3 global Interrupt                                             */
+  SWPMI1_IRQn                 = 115,    /*!< Serial Wire Interface 1 global interrupt                          */
+  TIM15_IRQn                  = 116,    /*!< TIM15 global Interrupt                                            */
+  TIM16_IRQn                  = 117,    /*!< TIM16 global Interrupt                                            */
+  TIM17_IRQn                  = 118,    /*!< TIM17 global Interrupt                                            */
+  MDIOS_WKUP_IRQn             = 119,    /*!< MDIOS Wakeup  Interrupt                                           */
+  MDIOS_IRQn                  = 120,    /*!< MDIOS global Interrupt                                            */
+  JPEG_IRQn                   = 121,    /*!< JPEG global Interrupt                                             */
+  MDMA_IRQn                   = 122,    /*!< MDMA global Interrupt                                             */
+  SDMMC2_IRQn                 = 124,    /*!< SDMMC2 global Interrupt                                           */
+  HSEM1_IRQn                  = 125,    /*!< HSEM1 global Interrupt                                            */
+  ADC3_IRQn                   = 127,    /*!< ADC3 global Interrupt                                             */
+  DMAMUX2_OVR_IRQn            = 128,    /*!<DMAMUX2 Overrun interrupt                                          */
+  BDMA_Channel0_IRQn          = 129,    /*!< BDMA Channel 0 global Interrupt                                   */
+  BDMA_Channel1_IRQn          = 130,    /*!< BDMA Channel 1 global Interrupt                                   */
+  BDMA_Channel2_IRQn          = 131,    /*!< BDMA Channel 2 global Interrupt                                   */
+  BDMA_Channel3_IRQn          = 132,    /*!< BDMA Channel 3 global Interrupt                                   */
+  BDMA_Channel4_IRQn          = 133,    /*!< BDMA Channel 4 global Interrupt                                   */
+  BDMA_Channel5_IRQn          = 134,    /*!< BDMA Channel 5 global Interrupt                                   */
+  BDMA_Channel6_IRQn          = 135,    /*!< BDMA Channel 6 global Interrupt                                   */
+  BDMA_Channel7_IRQn          = 136,    /*!< BDMA Channel 7 global Interrupt                                   */
+  COMP_IRQn                   = 137 ,   /*!< COMP global Interrupt                                             */
+  LPTIM2_IRQn                 = 138,    /*!< LP TIM2 global interrupt                                          */
+  LPTIM3_IRQn                 = 139,    /*!< LP TIM3 global interrupt                                          */
+  LPTIM4_IRQn                 = 140,    /*!< LP TIM4 global interrupt                                          */
+  LPTIM5_IRQn                 = 141,    /*!< LP TIM5 global interrupt                                          */
+  LPUART1_IRQn                = 142,    /*!< LP UART1 interrupt                                                */
+  CRS_IRQn                    = 144,    /*!< Clock Recovery Global Interrupt                                   */
+  ECC_IRQn                    = 145,    /*!< ECC diagnostic Global Interrupt                                   */
+  SAI4_IRQn                   = 146,    /*!< SAI4 global interrupt                                             */
+  WAKEUP_PIN_IRQn             = 149,    /*!< Interrupt for all 6 wake-up pins                                  */
+} IRQn_Type;
+
+/**
+  * @}
+  */
+
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+
+
+
+
+/**
+  * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
+   */
+#define __CM7_REV               0x0100U   /*!< Cortex-M7 revision r1p0                       */
+#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */
+#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */
+#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1       /*!< FPU present                                   */
+#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */
+#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */
+#include "core_cm7.h"                     /*!< Cortex-M7 processor and core peripherals      */
+
+/**
+  * @}
+  */
+
+
+
+
+#include "system_stm32h7xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+  * @{
+  */
+
+/**
+  * @brief Analog to Digital Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t ISR;              /*!< ADC Interrupt and Status Register,                          Address offset: 0x00 */
+  __IO uint32_t IER;              /*!< ADC Interrupt Enable Register,                              Address offset: 0x04 */
+  __IO uint32_t CR;               /*!< ADC control register,                                       Address offset: 0x08 */
+  __IO uint32_t CFGR;             /*!< ADC Configuration register,                                 Address offset: 0x0C */
+  __IO uint32_t CFGR2;            /*!< ADC Configuration register 2,                               Address offset: 0x10 */
+  __IO uint32_t SMPR1;            /*!< ADC sample time register 1,                                 Address offset: 0x14 */
+  __IO uint32_t SMPR2;            /*!< ADC sample time register 2,                                 Address offset: 0x18 */
+  __IO uint32_t PCSEL;            /*!< ADC pre-channel selection,                                  Address offset: 0x1C */
+  __IO uint32_t LTR1;             /*!< ADC watchdog Lower threshold register 1,                    Address offset: 0x20 */
+  __IO uint32_t HTR1;             /*!< ADC watchdog higher threshold register 1,                   Address offset: 0x24 */
+  uint32_t      RESERVED1;        /*!< Reserved, 0x028                                                                  */
+  uint32_t      RESERVED2;        /*!< Reserved, 0x02C                                                                  */
+  __IO uint32_t SQR1;             /*!< ADC regular sequence register 1,                            Address offset: 0x30 */
+  __IO uint32_t SQR2;             /*!< ADC regular sequence register 2,                            Address offset: 0x34 */
+  __IO uint32_t SQR3;             /*!< ADC regular sequence register 3,                            Address offset: 0x38 */
+  __IO uint32_t SQR4;             /*!< ADC regular sequence register 4,                            Address offset: 0x3C */
+  __IO uint32_t DR;               /*!< ADC regular data register,                                  Address offset: 0x40 */
+  uint32_t      RESERVED3;        /*!< Reserved, 0x044                                                                  */
+  uint32_t      RESERVED4;        /*!< Reserved, 0x048                                                                  */
+  __IO uint32_t JSQR;             /*!< ADC injected sequence register,                             Address offset: 0x4C */
+  uint32_t      RESERVED5[4];     /*!< Reserved, 0x050 - 0x05C                                                          */
+  __IO uint32_t OFR1;             /*!< ADC offset register 1,                                      Address offset: 0x60 */
+  __IO uint32_t OFR2;             /*!< ADC offset register 2,                                      Address offset: 0x64 */
+  __IO uint32_t OFR3;             /*!< ADC offset register 3,                                      Address offset: 0x68 */
+  __IO uint32_t OFR4;             /*!< ADC offset register 4,                                      Address offset: 0x6C */
+  uint32_t      RESERVED6[4];     /*!< Reserved, 0x070 - 0x07C                                                          */
+  __IO uint32_t JDR1;             /*!< ADC injected data register 1,                               Address offset: 0x80 */
+  __IO uint32_t JDR2;             /*!< ADC injected data register 2,                               Address offset: 0x84 */
+  __IO uint32_t JDR3;             /*!< ADC injected data register 3,                               Address offset: 0x88 */
+  __IO uint32_t JDR4;             /*!< ADC injected data register 4,                               Address offset: 0x8C */
+  uint32_t      RESERVED7[4];     /*!< Reserved, 0x090 - 0x09C                                                          */
+  __IO uint32_t AWD2CR;           /*!< ADC  Analog Watchdog 2 Configuration Register,              Address offset: 0xA0 */
+  __IO uint32_t AWD3CR;           /*!< ADC  Analog Watchdog 3 Configuration Register,              Address offset: 0xA4 */
+  uint32_t      RESERVED8;        /*!< Reserved, 0x0A8                                                                  */
+  uint32_t      RESERVED9;        /*!< Reserved, 0x0AC                                                                  */
+  __IO uint32_t LTR2;             /*!< ADC watchdog Lower threshold register 2,                    Address offset: 0xB0 */
+  __IO uint32_t HTR2;             /*!< ADC watchdog Higher threshold register 2,                   Address offset: 0xB4 */
+  __IO uint32_t LTR3;             /*!< ADC watchdog Lower threshold register 3,                    Address offset: 0xB8 */
+  __IO uint32_t HTR3;             /*!< ADC watchdog Higher threshold register 3,                   Address offset: 0xBC */
+  __IO uint32_t DIFSEL;           /*!< ADC  Differential Mode Selection Register,                  Address offset: 0xC0 */
+  __IO uint32_t CALFACT;          /*!< ADC  Calibration Factors,                                   Address offset: 0xC4 */
+  __IO uint32_t CALFACT2;         /*!< ADC  Linearity Calibration Factors,                         Address offset: 0xC8 */
+} ADC_TypeDef;
+
+
+typedef struct
+{
+__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
+uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
+__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
+__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */
+__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */
+
+} ADC_Common_TypeDef;
+
+
+/**
+  * @brief VREFBUF
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */
+  __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */
+} VREFBUF_TypeDef;
+
+
+/**
+  * @brief FD Controller Area Network
+  */
+
+typedef struct
+{
+  __IO uint32_t CREL;         /*!< FDCAN Core Release register,                                     Address offset: 0x000 */
+  __IO uint32_t ENDN;         /*!< FDCAN Endian register,                                           Address offset: 0x004 */
+  __IO uint32_t RESERVED1;    /*!< Reserved,                                                                        0x008 */
+  __IO uint32_t DBTP;         /*!< FDCAN Data Bit Timing & Prescaler register,                      Address offset: 0x00C */
+  __IO uint32_t TEST;         /*!< FDCAN Test register,                                             Address offset: 0x010 */
+  __IO uint32_t RWD;          /*!< FDCAN RAM Watchdog register,                                     Address offset: 0x014 */
+  __IO uint32_t CCCR;         /*!< FDCAN CC Control register,                                       Address offset: 0x018 */
+  __IO uint32_t NBTP;         /*!< FDCAN Nominal Bit Timing & Prescaler register,                   Address offset: 0x01C */
+  __IO uint32_t TSCC;         /*!< FDCAN Timestamp Counter Configuration register,                  Address offset: 0x020 */
+  __IO uint32_t TSCV;         /*!< FDCAN Timestamp Counter Value register,                          Address offset: 0x024 */
+  __IO uint32_t TOCC;         /*!< FDCAN Timeout Counter Configuration register,                    Address offset: 0x028 */
+  __IO uint32_t TOCV;         /*!< FDCAN Timeout Counter Value register,                            Address offset: 0x02C */
+  __IO uint32_t RESERVED2[4]; /*!< Reserved,                                                                0x030 - 0x03C */
+  __IO uint32_t ECR;          /*!< FDCAN Error Counter register,                                    Address offset: 0x040 */
+  __IO uint32_t PSR;          /*!< FDCAN Protocol Status register,                                  Address offset: 0x044 */
+  __IO uint32_t TDCR;         /*!< FDCAN Transmitter Delay Compensation register,                   Address offset: 0x048 */
+  __IO uint32_t RESERVED3;    /*!< Reserved,                                                                        0x04C */
+  __IO uint32_t IR;           /*!< FDCAN Interrupt register,                                        Address offset: 0x050 */
+  __IO uint32_t IE;           /*!< FDCAN Interrupt Enable register,                                 Address offset: 0x054 */
+  __IO uint32_t ILS;          /*!< FDCAN Interrupt Line Select register,                            Address offset: 0x058 */
+  __IO uint32_t ILE;          /*!< FDCAN Interrupt Line Enable register,                            Address offset: 0x05C */
+  __IO uint32_t RESERVED4[8]; /*!< Reserved,                                                                0x060 - 0x07C */
+  __IO uint32_t GFC;          /*!< FDCAN Global Filter Configuration register,                      Address offset: 0x080 */
+  __IO uint32_t SIDFC;        /*!< FDCAN Standard ID Filter Configuration register,                 Address offset: 0x084 */
+  __IO uint32_t XIDFC;        /*!< FDCAN Extended ID Filter Configuration register,                 Address offset: 0x088 */
+  __IO uint32_t RESERVED5;    /*!< Reserved,                                                                        0x08C */
+  __IO uint32_t XIDAM;        /*!< FDCAN Extended ID AND Mask register,                             Address offset: 0x090 */
+  __IO uint32_t HPMS;         /*!< FDCAN High Priority Message Status register,                     Address offset: 0x094 */
+  __IO uint32_t NDAT1;        /*!< FDCAN New Data 1 register,                                       Address offset: 0x098 */
+  __IO uint32_t NDAT2;        /*!< FDCAN New Data 2 register,                                       Address offset: 0x09C */
+  __IO uint32_t RXF0C;        /*!< FDCAN Rx FIFO 0 Configuration register,                          Address offset: 0x0A0 */
+  __IO uint32_t RXF0S;        /*!< FDCAN Rx FIFO 0 Status register,                                 Address offset: 0x0A4 */
+  __IO uint32_t RXF0A;        /*!< FDCAN Rx FIFO 0 Acknowledge register,                            Address offset: 0x0A8 */
+  __IO uint32_t RXBC;         /*!< FDCAN Rx Buffer Configuration register,                          Address offset: 0x0AC */
+  __IO uint32_t RXF1C;        /*!< FDCAN Rx FIFO 1 Configuration register,                          Address offset: 0x0B0 */
+  __IO uint32_t RXF1S;        /*!< FDCAN Rx FIFO 1 Status register,                                 Address offset: 0x0B4 */
+  __IO uint32_t RXF1A;        /*!< FDCAN Rx FIFO 1 Acknowledge register,                            Address offset: 0x0B8 */
+  __IO uint32_t RXESC;        /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register,        Address offset: 0x0BC */
+  __IO uint32_t TXBC;         /*!< FDCAN Tx Buffer Configuration register,                          Address offset: 0x0C0 */
+  __IO uint32_t TXFQS;        /*!< FDCAN Tx FIFO/Queue Status register,                             Address offset: 0x0C4 */
+  __IO uint32_t TXESC;        /*!< FDCAN Tx Buffer Element Size Configuration register,             Address offset: 0x0C8 */
+  __IO uint32_t TXBRP;        /*!< FDCAN Tx Buffer Request Pending register,                        Address offset: 0x0CC */
+  __IO uint32_t TXBAR;        /*!< FDCAN Tx Buffer Add Request register,                            Address offset: 0x0D0 */
+  __IO uint32_t TXBCR;        /*!< FDCAN Tx Buffer Cancellation Request register,                   Address offset: 0x0D4 */
+  __IO uint32_t TXBTO;        /*!< FDCAN Tx Buffer Transmission Occurred register,                  Address offset: 0x0D8 */
+  __IO uint32_t TXBCF;        /*!< FDCAN Tx Buffer Cancellation Finished register,                  Address offset: 0x0DC */
+  __IO uint32_t TXBTIE;       /*!< FDCAN Tx Buffer Transmission Interrupt Enable register,          Address offset: 0x0E0 */
+  __IO uint32_t TXBCIE;       /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */
+  __IO uint32_t RESERVED6[2]; /*!< Reserved,                                                                0x0E8 - 0x0EC */
+  __IO uint32_t TXEFC;        /*!< FDCAN Tx Event FIFO Configuration register,                      Address offset: 0x0F0 */
+  __IO uint32_t TXEFS;        /*!< FDCAN Tx Event FIFO Status register,                             Address offset: 0x0F4 */
+  __IO uint32_t TXEFA;        /*!< FDCAN Tx Event FIFO Acknowledge register,                        Address offset: 0x0F8 */
+  __IO uint32_t RESERVED7;    /*!< Reserved,                                                                        0x0FC */
+} FDCAN_GlobalTypeDef;
+
+/**
+  * @brief TTFD Controller Area Network
+  */
+
+typedef struct
+{
+  __IO uint32_t TTTMC;          /*!< TT Trigger Memory Configuration register,    Address offset: 0x100 */
+  __IO uint32_t TTRMC;          /*!< TT Reference Message Configuration register, Address offset: 0x104 */
+  __IO uint32_t TTOCF;          /*!< TT Operation Configuration register,         Address offset: 0x108 */
+  __IO uint32_t TTMLM;          /*!< TT Matrix Limits register,                   Address offset: 0x10C */
+  __IO uint32_t TURCF;          /*!< TUR Configuration register,                  Address offset: 0x110 */
+  __IO uint32_t TTOCN;          /*!< TT Operation Control register,               Address offset: 0x114 */
+  __IO uint32_t TTGTP;          /*!< TT Global Time Preset register,              Address offset: 0x118 */
+  __IO uint32_t TTTMK;          /*!< TT Time Mark register,                       Address offset: 0x11C */
+  __IO uint32_t TTIR;           /*!< TT Interrupt register,                       Address offset: 0x120 */
+  __IO uint32_t TTIE;           /*!< TT Interrupt Enable register,                Address offset: 0x124 */
+  __IO uint32_t TTILS;          /*!< TT Interrupt Line Select register,           Address offset: 0x128 */
+  __IO uint32_t TTOST;          /*!< TT Operation Status register,                Address offset: 0x12C */
+  __IO uint32_t TURNA;          /*!< TT TUR Numerator Actual register,            Address offset: 0x130 */
+  __IO uint32_t TTLGT;          /*!< TT Local and Global Time register,           Address offset: 0x134 */
+  __IO uint32_t TTCTC;          /*!< TT Cycle Time and Count register,            Address offset: 0x138 */
+  __IO uint32_t TTCPT;          /*!< TT Capture Time register,                    Address offset: 0x13C */
+  __IO uint32_t TTCSM;          /*!< TT Cycle Sync Mark register,                 Address offset: 0x140 */
+  __IO uint32_t RESERVED1[111]; /*!< Reserved,                                            0x144 - 0x2FC */
+  __IO uint32_t TTTS;           /*!< TT Trigger Select register,                  Address offset: 0x300 */
+} TTCAN_TypeDef;
+
+/**
+  * @brief FD Controller Area Network
+  */
+
+typedef struct
+{
+  __IO uint32_t CREL;  /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */
+  __IO uint32_t CCFG;  /*!< Calibration Configuration register,           Address offset: 0x04 */
+  __IO uint32_t CSTAT; /*!< Calibration Status register,                  Address offset: 0x08 */
+  __IO uint32_t CWD;   /*!< Calibration Watchdog register,                Address offset: 0x0C */
+  __IO uint32_t IR;    /*!< CCU Interrupt register,                       Address offset: 0x10 */
+  __IO uint32_t IE;    /*!< CCU Interrupt Enable register,                Address offset: 0x14 */
+} FDCAN_ClockCalibrationUnit_TypeDef;
+
+
+/**
+  * @brief Consumer Electronics Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;           /*!< CEC control register,              Address offset:0x00 */
+  __IO uint32_t CFGR;         /*!< CEC configuration register,        Address offset:0x04 */
+  __IO uint32_t TXDR;         /*!< CEC Tx data register ,             Address offset:0x08 */
+  __IO uint32_t RXDR;         /*!< CEC Rx Data Register,              Address offset:0x0C */
+  __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register, Address offset:0x10 */
+  __IO uint32_t IER;          /*!< CEC interrupt enable register,     Address offset:0x14 */
+}CEC_TypeDef;
+
+/**
+  * @brief CRC calculation unit
+  */
+
+typedef struct
+{
+  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
+  __IO uint32_t IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
+  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
+  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */
+  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
+  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
+} CRC_TypeDef;
+
+
+/**
+  * @brief Clock Recovery System
+  */
+typedef struct
+{
+__IO uint32_t CR;            /*!< CRS ccontrol register,              Address offset: 0x00 */
+__IO uint32_t CFGR;          /*!< CRS configuration register,         Address offset: 0x04 */
+__IO uint32_t ISR;           /*!< CRS interrupt and status register,  Address offset: 0x08 */
+__IO uint32_t ICR;           /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
+} CRS_TypeDef;
+
+
+/**
+  * @brief Digital to Analog Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
+  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
+  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
+  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
+  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
+  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
+  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
+  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
+  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
+  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
+  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
+  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
+  __IO uint32_t CCR;      /*!< DAC calibration control register,                        Address offset: 0x38 */
+  __IO uint32_t MCR;      /*!< DAC mode control register,                               Address offset: 0x3C */
+  __IO uint32_t SHSR1;    /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */
+  __IO uint32_t SHSR2;    /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */
+  __IO uint32_t SHHR;     /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */
+  __IO uint32_t SHRR;     /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */
+} DAC_TypeDef;
+
+/**
+  * @brief DFSDM module registers
+  */
+typedef struct
+{
+  __IO uint32_t FLTCR1;          /*!< DFSDM control register1,                          Address offset: 0x100 */
+  __IO uint32_t FLTCR2;          /*!< DFSDM control register2,                          Address offset: 0x104 */
+  __IO uint32_t FLTISR;          /*!< DFSDM interrupt and status register,              Address offset: 0x108 */
+  __IO uint32_t FLTICR;          /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */
+  __IO uint32_t FLTJCHGR;        /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */
+  __IO uint32_t FLTFCR;          /*!< DFSDM filter control register,                    Address offset: 0x114 */
+  __IO uint32_t FLTJDATAR;       /*!< DFSDM data register for injected group,           Address offset: 0x118 */
+  __IO uint32_t FLTRDATAR;       /*!< DFSDM data register for regular group,            Address offset: 0x11C */
+  __IO uint32_t FLTAWHTR;        /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */
+  __IO uint32_t FLTAWLTR;        /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */
+  __IO uint32_t FLTAWSR;         /*!< DFSDM analog watchdog status register             Address offset: 0x128 */
+  __IO uint32_t FLTAWCFR;        /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */
+  __IO uint32_t FLTEXMAX;        /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */
+  __IO uint32_t FLTEXMIN;        /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */
+  __IO uint32_t FLTCNVTIMR;      /*!< DFSDM conversion timer,                           Address offset: 0x138 */
+} DFSDM_Filter_TypeDef;
+
+/**
+  * @brief DFSDM channel configuration registers
+  */
+typedef struct
+{
+  __IO uint32_t CHCFGR1;      /*!< DFSDM channel configuration register1,            Address offset: 0x00 */
+  __IO uint32_t CHCFGR2;      /*!< DFSDM channel configuration register2,            Address offset: 0x04 */
+  __IO uint32_t CHAWSCDR;     /*!< DFSDM channel analog watchdog and
+                                   short circuit detector register,                  Address offset: 0x08 */
+  __IO uint32_t CHWDATAR;     /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */
+  __IO uint32_t CHDATINR;     /*!< DFSDM channel data input register,                Address offset: 0x10 */
+} DFSDM_Channel_TypeDef;
+
+/**
+  * @brief Debug MCU
+  */
+typedef struct
+{
+  __IO uint32_t IDCODE;        /*!< MCU device ID code,                     Address offset: 0x00 */
+  __IO uint32_t CR;            /*!< Debug MCU configuration register,       Address offset: 0x04 */
+  uint32_t RESERVED4[11];      /*!< Reserved,                             Address offset: 0x08 */
+  __IO uint32_t APB3FZ1;     /*!< Debug MCU APB3FZ1 freeze register,    Address offset: 0x34 */
+  uint32_t RESERVED5;          /*!< Reserved,                             Address offset: 0x38 */
+  __IO uint32_t APB1LFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x3C */
+  uint32_t RESERVED6;          /*!< Reserved,                             Address offset: 0x40 */
+  __IO uint32_t APB1HFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x44 */
+  uint32_t RESERVED7;          /*!< Reserved,                             Address offset: 0x48 */
+  __IO uint32_t APB2FZ1;     /*!< Debug MCU APB2FZ1 freeze register,    Address offset: 0x4C */
+  uint32_t RESERVED8;          /*!< Reserved,                             Address offset: 0x50 */
+  __IO uint32_t APB4FZ1;     /*!< Debug MCU APB4FZ1 freeze register,    Address offset: 0x54 */
+}DBGMCU_TypeDef;
+/**
+  * @brief DCMI
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
+  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
+  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
+  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
+  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
+  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
+  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
+  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
+  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
+  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
+} DCMI_TypeDef;
+
+/**
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
+  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
+  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
+  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
+  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
+  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
+  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
+  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
+  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CCR;          /*!< DMA channel x configuration register          */
+  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register         */
+  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register     */
+  __IO uint32_t CM0AR;        /*!< DMA channel x memory 0 address register       */
+  __IO uint32_t CM1AR;        /*!< DMA channel x memory 1 address register       */
+} BDMA_Channel_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
+  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
+} BDMA_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t  CCR;        /*!< DMA Multiplexer Channel x Control Register   */
+}DMAMUX_Channel_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t  CSR;      /*!< DMA Channel Status Register     */
+  __IO uint32_t  CFR;      /*!< DMA Channel Clear Flag Register */
+}DMAMUX_ChannelStatus_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t  RGCR;        /*!< DMA Request Generator x Control Register   */
+}DMAMUX_RequestGen_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t  RGSR;        /*!< DMA Request Generator Status Register       */
+  __IO uint32_t  RGCFR;       /*!< DMA Request Generator Clear Flag Register   */
+}DMAMUX_RequestGenStatus_TypeDef;
+
+/**
+  * @brief MDMA Controller
+  */
+typedef struct
+{
+  __IO uint32_t  GISR0;   /*!< MDMA Global Interrupt/Status Register 0,          Address offset: 0x00 */
+}MDMA_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t  CISR;      /*!< MDMA channel x interrupt/status register,             Address offset: 0x40 */
+  __IO uint32_t  CIFCR;     /*!< MDMA channel x interrupt flag clear register,         Address offset: 0x44 */
+  __IO uint32_t  CESR;      /*!< MDMA Channel x error status register,                 Address offset: 0x48 */
+  __IO uint32_t  CCR;       /*!< MDMA channel x control register,                      Address offset: 0x4C */
+  __IO uint32_t  CTCR;      /*!< MDMA channel x Transfer Configuration register,       Address offset: 0x50 */
+  __IO uint32_t  CBNDTR;    /*!< MDMA Channel x block number of data register,         Address offset: 0x54 */
+  __IO uint32_t  CSAR;      /*!< MDMA channel x source address register,               Address offset: 0x58 */
+  __IO uint32_t  CDAR;      /*!< MDMA channel x destination address register,          Address offset: 0x5C */
+  __IO uint32_t  CBRUR;     /*!< MDMA channel x Block Repeat address Update register,  Address offset: 0x60 */
+  __IO uint32_t  CLAR;      /*!< MDMA channel x Link Address register,                 Address offset: 0x64 */
+  __IO uint32_t  CTBR;      /*!< MDMA channel x Trigger and Bus selection Register,    Address offset: 0x68 */
+  uint32_t       RESERVED0; /*!< Reserved, 0x68                                                             */
+  __IO uint32_t  CMAR;      /*!< MDMA channel x Mask address register,                 Address offset: 0x70 */
+  __IO uint32_t  CMDR;      /*!< MDMA channel x Mask Data register,                    Address offset: 0x74 */
+}MDMA_Channel_TypeDef;
+
+/**
+  * @brief DMA2D Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */
+  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */
+  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */
+  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */
+  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */
+  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */
+  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */
+  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */
+  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */
+  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */
+  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */
+  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */
+  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */
+  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */
+  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */
+  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */
+  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */
+  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */
+  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */
+  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */
+  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
+  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */
+  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */
+} DMA2D_TypeDef;
+
+
+/**
+  * @brief Ethernet MAC
+  */
+typedef struct
+{
+  __IO uint32_t MACCR;
+  __IO uint32_t MACECR;
+  __IO uint32_t MACPFR;
+  __IO uint32_t MACWTR;
+  __IO uint32_t MACHT0R;
+  __IO uint32_t MACHT1R;
+  uint32_t      RESERVED1[14];
+  __IO uint32_t MACVTR;
+  uint32_t      RESERVED2;
+  __IO uint32_t MACVHTR;
+  uint32_t      RESERVED3;
+  __IO uint32_t MACVIR;
+  __IO uint32_t MACIVIR;
+  uint32_t      RESERVED4[2];
+  __IO uint32_t MACTFCR;
+  uint32_t      RESERVED5[7];
+  __IO uint32_t MACRFCR;
+  uint32_t      RESERVED6[7];
+  __IO uint32_t MACISR;
+  __IO uint32_t MACIER;
+  __IO uint32_t MACRXTXSR;
+  uint32_t      RESERVED7;
+  __IO uint32_t MACPCSR;
+  __IO uint32_t MACRWKPFR;
+  uint32_t      RESERVED8[2];
+  __IO uint32_t MACLCSR;
+  __IO uint32_t MACLTCR;
+  __IO uint32_t MACLETR;
+  __IO uint32_t MAC1USTCR;
+  uint32_t      RESERVED9[12];
+  __IO uint32_t MACVR;
+  __IO uint32_t MACDR;
+  uint32_t      RESERVED10;
+  __IO uint32_t MACHWF0R;
+  __IO uint32_t MACHWF1R;
+  __IO uint32_t MACHWF2R;
+  uint32_t      RESERVED11[54];
+  __IO uint32_t MACMDIOAR;
+  __IO uint32_t MACMDIODR;
+  uint32_t      RESERVED12[2];
+  __IO uint32_t MACARPAR;
+  uint32_t      RESERVED13[59];
+  __IO uint32_t MACA0HR;
+  __IO uint32_t MACA0LR;
+  __IO uint32_t MACA1HR;
+  __IO uint32_t MACA1LR;
+  __IO uint32_t MACA2HR;
+  __IO uint32_t MACA2LR;
+  __IO uint32_t MACA3HR;
+  __IO uint32_t MACA3LR;
+  uint32_t      RESERVED14[248];
+  __IO uint32_t MMCCR;
+  __IO uint32_t MMCRIR;
+  __IO uint32_t MMCTIR;
+  __IO uint32_t MMCRIMR;
+  __IO uint32_t MMCTIMR;
+  uint32_t      RESERVED15[14];
+  __IO uint32_t MMCTSCGPR;
+  __IO uint32_t MMCTMCGPR;
+  uint32_t      RESERVED16[5];
+  __IO uint32_t MMCTPCGR;
+  uint32_t      RESERVED17[10];
+  __IO uint32_t MMCRCRCEPR;
+  __IO uint32_t MMCRAEPR;
+  uint32_t      RESERVED18[10];
+  __IO uint32_t MMCRUPGR;
+  uint32_t      RESERVED19[9];
+  __IO uint32_t MMCTLPIMSTR;
+  __IO uint32_t MMCTLPITCR;
+  __IO uint32_t MMCRLPIMSTR;
+  __IO uint32_t MMCRLPITCR;
+  uint32_t      RESERVED20[65];
+  __IO uint32_t MACL3L4C0R;
+  __IO uint32_t MACL4A0R;
+  uint32_t      RESERVED21[2];
+  __IO uint32_t MACL3A0R0R;
+  __IO uint32_t MACL3A1R0R;
+  __IO uint32_t MACL3A2R0R;
+  __IO uint32_t MACL3A3R0R;
+  uint32_t      RESERVED22[4];
+  __IO uint32_t MACL3L4C1R;
+  __IO uint32_t MACL4A1R;
+  uint32_t      RESERVED23[2];
+  __IO uint32_t MACL3A0R1R;
+  __IO uint32_t MACL3A1R1R;
+  __IO uint32_t MACL3A2R1R;
+  __IO uint32_t MACL3A3R1R;
+  uint32_t      RESERVED24[108];
+  __IO uint32_t MACTSCR;
+  __IO uint32_t MACSSIR;
+  __IO uint32_t MACSTSR;
+  __IO uint32_t MACSTNR;
+  __IO uint32_t MACSTSUR;
+  __IO uint32_t MACSTNUR;
+  __IO uint32_t MACTSAR;
+  uint32_t      RESERVED25;
+  __IO uint32_t MACTSSR;
+  uint32_t      RESERVED26[3];
+  __IO uint32_t MACTTSSNR;
+  __IO uint32_t MACTTSSSR;
+  uint32_t      RESERVED27[2];
+  __IO uint32_t MACACR;
+  uint32_t      RESERVED28;
+  __IO uint32_t MACATSNR;
+  __IO uint32_t MACATSSR;
+  __IO uint32_t MACTSIACR;
+  __IO uint32_t MACTSEACR;
+  __IO uint32_t MACTSICNR;
+  __IO uint32_t MACTSECNR;
+  uint32_t      RESERVED29[4];
+  __IO uint32_t MACPPSCR;
+  uint32_t      RESERVED30[3];
+  __IO uint32_t MACPPSTTSR;
+  __IO uint32_t MACPPSTTNR;
+  __IO uint32_t MACPPSIR;
+  __IO uint32_t MACPPSWR;
+  uint32_t      RESERVED31[12];
+  __IO uint32_t MACPOCR;
+  __IO uint32_t MACSPI0R;
+  __IO uint32_t MACSPI1R;
+  __IO uint32_t MACSPI2R;
+  __IO uint32_t MACLMIR;
+  uint32_t      RESERVED32[11];
+  __IO uint32_t MTLOMR;
+  uint32_t      RESERVED33[7];
+  __IO uint32_t MTLISR;
+  uint32_t      RESERVED34[55];
+  __IO uint32_t MTLTQOMR;
+  __IO uint32_t MTLTQUR;
+  __IO uint32_t MTLTQDR;
+  uint32_t      RESERVED35[8];
+  __IO uint32_t MTLQICSR;
+  __IO uint32_t MTLRQOMR;
+  __IO uint32_t MTLRQMPOCR;
+  __IO uint32_t MTLRQDR;
+  uint32_t      RESERVED36[177];
+  __IO uint32_t DMAMR;
+  __IO uint32_t DMASBMR;
+  __IO uint32_t DMAISR;
+  __IO uint32_t DMADSR;
+  uint32_t      RESERVED37[60];
+  __IO uint32_t DMACCR;
+  __IO uint32_t DMACTCR;
+  __IO uint32_t DMACRCR;
+  uint32_t      RESERVED38[2];
+  __IO uint32_t DMACTDLAR;
+  uint32_t      RESERVED39;
+  __IO uint32_t DMACRDLAR;
+  __IO uint32_t DMACTDTPR;
+  uint32_t      RESERVED40;
+  __IO uint32_t DMACRDTPR;
+  __IO uint32_t DMACTDRLR;
+  __IO uint32_t DMACRDRLR;
+  __IO uint32_t DMACIER;
+  __IO uint32_t DMACRIWTR;
+__IO uint32_t DMACSFCSR;
+  uint32_t      RESERVED41;
+  __IO uint32_t DMACCATDR;
+  uint32_t      RESERVED42;
+  __IO uint32_t DMACCARDR;
+  uint32_t      RESERVED43;
+  __IO uint32_t DMACCATBR;
+  uint32_t      RESERVED44;
+  __IO uint32_t DMACCARBR;
+  __IO uint32_t DMACSR;
+uint32_t      RESERVED45[2];
+__IO uint32_t DMACMFCR;
+}ETH_TypeDef;
+/**
+  * @brief External Interrupt/Event Controller
+  */
+
+typedef struct
+{
+__IO uint32_t RTSR1;               /*!< EXTI Rising trigger selection register,          Address offset: 0x00 */
+__IO uint32_t FTSR1;               /*!< EXTI Falling trigger selection register,         Address offset: 0x04 */
+__IO uint32_t SWIER1;              /*!< EXTI Software interrupt event register,          Address offset: 0x08 */
+__IO uint32_t D3PMR1;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */
+__IO uint32_t D3PCR1L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L)     Address offset: 0x10 */
+__IO uint32_t D3PCR1H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H)   Address offset: 0x14 */
+uint32_t      RESERVED1[2];        /*!< Reserved,                                        0x18 to 0x1C         */
+__IO uint32_t RTSR2;               /*!< EXTI Rising trigger selection register,          Address offset: 0x20 */
+__IO uint32_t FTSR2;               /*!< EXTI Falling trigger selection register,         Address offset: 0x24 */
+__IO uint32_t SWIER2;              /*!< EXTI Software interrupt event register,          Address offset: 0x28 */
+__IO uint32_t D3PMR2;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */
+__IO uint32_t D3PCR2L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L)  Address offset: 0x30 */
+__IO uint32_t D3PCR2H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */
+uint32_t      RESERVED2[2];        /*!< Reserved,                                        0x38 to 0x3C         */
+__IO uint32_t RTSR3;               /*!< EXTI Rising trigger selection register,          Address offset: 0x40 */
+__IO uint32_t FTSR3;               /*!< EXTI Falling trigger selection register,         Address offset: 0x44 */
+__IO uint32_t SWIER3;              /*!< EXTI Software interrupt event register,          Address offset: 0x48 */
+__IO uint32_t D3PMR3;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */
+__IO uint32_t D3PCR3L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */
+__IO uint32_t D3PCR3H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */
+uint32_t      RESERVED3[10];       /*!< Reserved,                                        0x58 to 0x7C         */
+__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                    Address offset: 0x80 */
+__IO uint32_t EMR1;                /*!< EXTI Event mask register,                        Address offset: 0x84 */
+__IO uint32_t PR1;                 /*!< EXTI Pending register,                           Address offset: 0x88 */
+uint32_t      RESERVED4;           /*!< Reserved,                                        0x8C                 */
+__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                    Address offset: 0x90 */
+__IO uint32_t EMR2;                /*!< EXTI Event mask register,                        Address offset: 0x94 */
+__IO uint32_t PR2;                 /*!< EXTI Pending register,                           Address offset: 0x98 */
+uint32_t      RESERVED5;           /*!< Reserved,                                        0x9C                 */
+__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                    Address offset: 0xA0 */
+__IO uint32_t EMR3;                /*!< EXTI Event mask register,                        Address offset: 0xA4 */
+__IO uint32_t PR3;                 /*!< EXTI Pending register,                           Address offset: 0xA8 */
+}EXTI_TypeDef;
+
+typedef struct
+{
+__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                Address offset: 0x00 */
+__IO uint32_t EMR1;                /*!< EXTI Event mask register,                    Address offset: 0x04 */
+__IO uint32_t PR1;                 /*!< EXTI Pending register,                       Address offset: 0x08 */
+uint32_t      RESERVED1;           /*!< Reserved, 0x0C                                                    */
+__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                Address offset: 0x10 */
+__IO uint32_t EMR2;                /*!< EXTI Event mask register,                    Address offset: 0x14 */
+__IO uint32_t PR2;                 /*!< EXTI Pending register,                       Address offset: 0x18 */
+uint32_t      RESERVED2;           /*!< Reserved, 0x1C                                                    */
+__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                Address offset: 0x20 */
+__IO uint32_t EMR3;                /*!< EXTI Event mask register,                    Address offset: 0x24 */
+__IO uint32_t PR3;                 /*!< EXTI Pending register,                       Address offset: 0x28 */
+}EXTI_Core_TypeDef;
+
+
+/**
+  * @brief FLASH Registers
+  */
+
+typedef struct
+{
+  __IO uint32_t ACR;             /*!< FLASH access control register,                            Address offset: 0x00  */
+  __IO uint32_t KEYR1;           /*!< Flash Key Register for bank1,                             Address offset: 0x04  */
+  __IO uint32_t OPTKEYR;         /*!< Flash Option Key Register,                                Address offset: 0x08  */
+  __IO uint32_t CR1;             /*!< Flash Control Register for bank1,                         Address offset: 0x0C  */
+  __IO uint32_t SR1;             /*!< Flash Status Register for bank1,                          Address offset: 0x10  */
+  __IO uint32_t CCR1;            /*!< Flash Control Register for bank1,                         Address offset: 0x14  */
+  __IO uint32_t OPTCR;           /*!< Flash Option Control Register,                            Address offset: 0x18  */
+  __IO uint32_t OPTSR_CUR;       /*!< Flash Option Status Current Register,                     Address offset: 0x1C  */
+  __IO uint32_t OPTSR_PRG;       /*!< Flash Option Status to Program Register,                  Address offset: 0x20  */
+  __IO uint32_t OPTCCR;          /*!< Flash Option Clear Control Register,                      Address offset: 0x24  */
+  __IO uint32_t PRAR_CUR1;       /*!< Flash Current Protection Address Register for bank1,      Address offset: 0x28  */
+  __IO uint32_t PRAR_PRG1;       /*!< Flash Protection Address to Program Register for bank1,   Address offset: 0x2C  */
+  __IO uint32_t SCAR_CUR1;       /*!< Flash Current Secure Address Register for bank1,          Address offset: 0x30  */
+  __IO uint32_t SCAR_PRG1;       /*!< Flash Secure Address to Program Register for bank1,       Address offset: 0x34  */
+  __IO uint32_t WPSN_CUR1;       /*!< Flash Current Write Protection Register on bank1,         Address offset: 0x38  */
+  __IO uint32_t WPSN_PRG1;       /*!< Flash Write Protection to Program Register on bank1,      Address offset: 0x3C  */
+  __IO uint32_t BOOT_CUR;        /*!< Flash Current Boot Address for Pelican Core Register,     Address offset: 0x40  */
+  __IO uint32_t BOOT_PRG;        /*!< Flash Boot Address to Program for Pelican Core Register,  Address offset: 0x44  */
+  uint32_t      RESERVED0[2];    /*!< Reserved, 0x48 to 0x4C                                                          */
+  __IO uint32_t CRCCR1;          /*!< Flash CRC Control register For Bank1 Register ,           Address offset: 0x50  */
+  __IO uint32_t CRCSADD1;        /*!< Flash CRC Start Address Register for Bank1 ,              Address offset: 0x54  */
+  __IO uint32_t CRCEADD1;        /*!< Flash CRC End Address Register for Bank1 ,                Address offset: 0x58  */
+  __IO uint32_t CRCDATA;         /*!< Flash CRC Data Register for Bank1 ,                       Address offset: 0x5C  */
+  __IO uint32_t ECC_FA1;         /*!< Flash ECC Fail Address For Bank1 Register ,               Address offset: 0x60  */
+  uint32_t      RESERVED1[40];   /*!< Reserved, 0x64 to 0x100                                                         */
+  __IO uint32_t KEYR2;           /*!< Flash Key Register for bank2,                             Address offset: 0x104 */
+  uint32_t      RESERVED2;       /*!< Reserved, 0x108                                                                 */
+  __IO uint32_t CR2;             /*!< Flash Control Register for bank2,                         Address offset: 0x10C */
+  __IO uint32_t SR2;             /*!< Flash Status Register for bank2,                          Address offset: 0x110 */
+  __IO uint32_t CCR2;            /*!< Flash Status Register for bank2,                          Address offset: 0x114 */
+  uint32_t      RESERVED3[4];    /*!< Reserved, 0x118 to 0x124                                                        */
+  __IO uint32_t PRAR_CUR2;       /*!< Flash Current Protection Address Register for bank2,      Address offset: 0x128 */
+  __IO uint32_t PRAR_PRG2;       /*!< Flash Protection Address to Program Register for bank2,   Address offset: 0x12C */
+  __IO uint32_t SCAR_CUR2;       /*!< Flash Current Secure Address Register for bank2,          Address offset: 0x130 */
+  __IO uint32_t SCAR_PRG2;       /*!< Flash Secure Address Register for bank2,                  Address offset: 0x134 */
+  __IO uint32_t WPSN_CUR2;       /*!< Flash Current Write Protection Register on bank2,         Address offset: 0x138 */
+  __IO uint32_t WPSN_PRG2;       /*!< Flash Write Protection to Program Register on bank2,      Address offset: 0x13C */
+  uint32_t      RESERVED4[4];    /*!< Reserved, 0x140 to 0x14C                                                        */
+  __IO uint32_t CRCCR2;          /*!< Flash CRC Control register For Bank2 Register ,           Address offset: 0x150 */
+  __IO uint32_t CRCSADD2;        /*!< Flash CRC Start Address Register for Bank2 ,              Address offset: 0x154 */
+  __IO uint32_t CRCEADD2;        /*!< Flash CRC End Address Register for Bank2 ,                Address offset: 0x158 */
+  __IO uint32_t CRCDATA2;        /*!< Flash CRC Data Register for Bank2 ,                       Address offset: 0x15C */
+  __IO uint32_t ECC_FA2;         /*!< Flash ECC Fail Address For Bank2 Register ,               Address offset: 0x160 */
+} FLASH_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FMC_Bank1_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank1E
+  */
+
+typedef struct
+{
+  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank2
+  */
+
+typedef struct
+{
+  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */
+  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */
+  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */
+  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
+  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */
+  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */
+} FMC_Bank2_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank3
+  */
+
+typedef struct
+{
+  __IO uint32_t PCR;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */
+  __IO uint32_t SR;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */
+  __IO uint32_t PMEM;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */
+  __IO uint32_t PATT;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
+  uint32_t      RESERVED;  /*!< Reserved, 0x90                                                            */
+  __IO uint32_t ECCR;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */
+} FMC_Bank3_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank5 and 6
+  */
+
+
+typedef struct
+{
+  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */
+  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */
+  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */
+  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */
+  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */
+} FMC_Bank5_6_TypeDef;
+
+/**
+  * @brief General Purpose I/O
+  */
+
+typedef struct
+{
+  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
+  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
+  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
+  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
+  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
+  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
+  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset,               Address offset: 0x18      */
+  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
+  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+  * @brief Operational Amplifier (OPAMP)
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;          /*!< OPAMP control/status register,                      Address offset: 0x00 */
+  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,     Address offset: 0x04 */
+  __IO uint32_t HSOTR;        /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */
+} OPAMP_TypeDef;
+
+/**
+  * @brief System configuration controller
+  */
+
+typedef struct
+{
+ uint32_t RESERVED1;           /*!< Reserved,                                           Address offset: 0x00        */
+ __IO uint32_t PMCR;           /*!< SYSCFG peripheral mode configuration register,      Address offset: 0x04        */
+ __IO uint32_t EXTICR[4];      /*!< SYSCFG external interrupt configuration registers,  Address offset: 0x08-0x14   */
+ __IO uint32_t CFGR;           /*!< SYSCFG configuration registers,                     Address offset: 0x18        */
+ uint32_t RESERVED2;           /*!< Reserved,                                           Address offset: 0x1C        */
+ __IO uint32_t CCCSR;          /*!< SYSCFG compensation cell control/status register,   Address offset: 0x20        */
+ __IO uint32_t CCVR;           /*!< SYSCFG compensation cell value register,            Address offset: 0x24        */
+ __IO uint32_t CCCR;           /*!< SYSCFG compensation cell code register,             Address offset: 0x28        */
+ __IO uint32_t PWRCR;          /*!< PWR control register,                               Address offset: 0x2C        */
+  uint32_t     RESERVED3[61];  /*!< Reserved, 0x30-0x120                                                            */
+  __IO uint32_t PKGR;          /*!< SYSCFG package register,                            Address offset: 0x124       */
+  uint32_t     RESERVED4[118]; /*!< Reserved, 0x128-0x2FC                                                           */
+ __IO uint32_t UR0;            /*!< SYSCFG user register 0,                             Address offset: 0x300       */
+ __IO uint32_t UR1;            /*!< SYSCFG user register 1,                             Address offset: 0x304       */
+ __IO uint32_t UR2;            /*!< SYSCFG user register 2,                             Address offset: 0x308       */
+ __IO uint32_t UR3;            /*!< SYSCFG user register 3,                             Address offset: 0x30C       */
+ __IO uint32_t UR4;            /*!< SYSCFG user register 4,                             Address offset: 0x310       */
+ __IO uint32_t UR5;            /*!< SYSCFG user register 5,                             Address offset: 0x314       */
+ __IO uint32_t UR6;            /*!< SYSCFG user register 6,                             Address offset: 0x318       */
+ __IO uint32_t UR7;            /*!< SYSCFG user register 7,                             Address offset: 0x31C       */
+ __IO uint32_t UR8;            /*!< SYSCFG user register 8,                             Address offset: 0x320       */
+ __IO uint32_t UR9;            /*!< SYSCFG user register 9,                             Address offset: 0x324       */
+ __IO uint32_t UR10;           /*!< SYSCFG user register 10,                            Address offset: 0x328       */
+ __IO uint32_t UR11;           /*!< SYSCFG user register 11,                            Address offset: 0x32C       */
+ __IO uint32_t UR12;           /*!< SYSCFG user register 12,                            Address offset: 0x330       */
+ __IO uint32_t UR13;           /*!< SYSCFG user register 13,                            Address offset: 0x334       */
+ __IO uint32_t UR14;           /*!< SYSCFG user register 14,                            Address offset: 0x338       */
+ __IO uint32_t UR15;           /*!< SYSCFG user register 15,                            Address offset: 0x33C       */
+ __IO uint32_t UR16;           /*!< SYSCFG user register 16,                            Address offset: 0x340       */
+ __IO uint32_t UR17;           /*!< SYSCFG user register 17,                            Address offset: 0x344       */
+
+} SYSCFG_TypeDef;
+
+/**
+  * @brief Inter-integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
+  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
+  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
+  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
+  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
+  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
+  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
+  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
+  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
+  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
+  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
+} I2C_TypeDef;
+
+/**
+  * @brief Independent WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
+  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
+} IWDG_TypeDef;
+
+
+/**
+  * @brief JPEG Codec
+  */
+typedef struct
+{
+  __IO uint32_t CONFR0;          /*!< JPEG Codec Control Register (JPEG_CONFR0),        Address offset: 00h       */
+  __IO uint32_t CONFR1;          /*!< JPEG Codec Control Register (JPEG_CONFR1),        Address offset: 04h       */
+  __IO uint32_t CONFR2;          /*!< JPEG Codec Control Register (JPEG_CONFR2),        Address offset: 08h       */
+  __IO uint32_t CONFR3;          /*!< JPEG Codec Control Register (JPEG_CONFR3),        Address offset: 0Ch       */
+  __IO uint32_t CONFR4;          /*!< JPEG Codec Control Register (JPEG_CONFR4),        Address offset: 10h       */
+  __IO uint32_t CONFR5;          /*!< JPEG Codec Control Register (JPEG_CONFR5),        Address offset: 14h       */
+  __IO uint32_t CONFR6;          /*!< JPEG Codec Control Register (JPEG_CONFR6),        Address offset: 18h       */
+  __IO uint32_t CONFR7;          /*!< JPEG Codec Control Register (JPEG_CONFR7),        Address offset: 1Ch       */
+  uint32_t  Reserved20[4];       /* Reserved                                            Address offset: 20h-2Ch   */
+  __IO uint32_t CR;              /*!< JPEG Control Register (JPEG_CR),                  Address offset: 30h       */
+  __IO uint32_t SR;              /*!< JPEG Status Register (JPEG_SR),                   Address offset: 34h       */
+  __IO uint32_t CFR;             /*!< JPEG Clear Flag Register (JPEG_CFR),              Address offset: 38h       */
+  uint32_t  Reserved3c;          /* Reserved                                            Address offset: 3Ch       */
+  __IO uint32_t DIR;             /*!< JPEG Data Input Register (JPEG_DIR),              Address offset: 40h       */
+  __IO uint32_t DOR;             /*!< JPEG Data Output Register (JPEG_DOR),             Address offset: 44h       */
+  uint32_t  Reserved48[2];       /* Reserved                                            Address offset: 48h-4Ch   */
+  __IO uint32_t QMEM0[16];       /*!< JPEG quantization tables 0,                       Address offset: 50h-8Ch   */
+  __IO uint32_t QMEM1[16];       /*!< JPEG quantization tables 1,                       Address offset: 90h-CCh   */
+  __IO uint32_t QMEM2[16];       /*!< JPEG quantization tables 2,                       Address offset: D0h-10Ch  */
+  __IO uint32_t QMEM3[16];       /*!< JPEG quantization tables 3,                       Address offset: 110h-14Ch */
+  __IO uint32_t HUFFMIN[16];     /*!< JPEG HuffMin tables,                              Address offset: 150h-18Ch */
+  __IO uint32_t HUFFBASE[32];    /*!< JPEG HuffSymb tables,                             Address offset: 190h-20Ch */
+  __IO uint32_t HUFFSYMB[84];    /*!< JPEG HUFFSYMB tables,                             Address offset: 210h-35Ch */
+  __IO uint32_t DHTMEM[103];     /*!< JPEG DHTMem tables,                               Address offset: 360h-4F8h */
+  uint32_t  Reserved4FC;         /* Reserved                                            Address offset: 4FCh      */
+  __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0,                 Address offset: 500h-65Ch */
+  __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1,                 Address offset: 660h-7BCh */
+  __IO uint32_t HUFFENC_DC0[8];  /*!< JPEG encodor, DC Huffman table 0,                 Address offset: 7C0h-7DCh */
+  __IO uint32_t HUFFENC_DC1[8];  /*!< JPEG encodor, DC Huffman table 1,                 Address offset: 7E0h-7FCh */
+
+} JPEG_TypeDef;
+
+/**
+  * @brief LCD-TFT Display Controller
+  */
+
+typedef struct
+{
+  uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04                                                       */
+  __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */
+  __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */
+  __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */
+  __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */
+  __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */
+  uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20                                                       */
+  __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */
+  uint32_t      RESERVED2[1];  /*!< Reserved, 0x28                                                            */
+  __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */
+  uint32_t      RESERVED3[1];  /*!< Reserved, 0x30                                                            */
+  __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */
+  __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */
+  __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */
+  __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
+  __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */
+  __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                 Address offset: 0x48 */
+} LTDC_TypeDef;
+
+/**
+  * @brief LCD-TFT Display layer x Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */
+  __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
+  __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */
+  __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */
+  __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */
+  __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */
+  __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */
+  __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */
+  uint32_t      RESERVED0[2];  /*!< Reserved */
+  __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */
+  __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */
+  __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */
+  uint32_t      RESERVED1[3];  /*!< Reserved */
+  __IO uint32_t CLUTWR;         /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */
+
+} LTDC_Layer_TypeDef;
+
+/**
+  * @brief Power Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;       /*!< PWR power control register 1,            Address offset: 0x00 */
+  __IO uint32_t CSR1;      /*!< PWR power control status register 1,     Address offset: 0x04 */
+  __IO uint32_t CR2;       /*!< PWR power control register 2,            Address offset: 0x08 */
+  __IO uint32_t CR3;       /*!< PWR power control register 3,            Address offset: 0x0C */
+  __IO uint32_t CPUCR;     /*!< PWR CPU control register,                Address offset: 0x10 */
+       uint32_t RESERVED0; /*!< Reserved,                                Address offset: 0x14 */
+  __IO uint32_t D3CR;      /*!< PWR D3 domain control register,          Address offset: 0x18 */
+       uint32_t RESERVED1; /*!< Reserved,                                Address offset: 0x1C */
+  __IO uint32_t WKUPCR;    /*!< PWR wakeup clear register,               Address offset: 0x20 */
+  __IO uint32_t WKUPFR;    /*!< PWR wakeup flag register,                Address offset: 0x24 */
+  __IO uint32_t WKUPEPR;   /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */
+} PWR_TypeDef;
+
+/**
+  * @brief Reset and Clock Control
+  */
+
+typedef struct
+{
+ __IO uint32_t CR;             /*!< RCC clock control register,                                              Address offset: 0x00  */
+ __IO uint32_t HSICFGR;        /*!< HSI Clock Calibration Register,                                          Address offset: 0x04  */
+ __IO uint32_t CRRCR;          /*!< Clock Recovery RC  Register,                                             Address offset: 0x08  */
+ __IO uint32_t CSICFGR;        /*!< CSI Clock Calibration Register,                                          Address offset: 0x0C  */
+ __IO uint32_t CFGR;           /*!< RCC clock configuration register,                                        Address offset: 0x10  */
+ uint32_t     RESERVED1;       /*!< Reserved,                                                                Address offset: 0x14  */
+ __IO uint32_t D1CFGR;         /*!< RCC Domain 1 configuration register,                                     Address offset: 0x18  */
+ __IO uint32_t D2CFGR;         /*!< RCC Domain 2 configuration register,                                     Address offset: 0x1C  */
+ __IO uint32_t D3CFGR;         /*!< RCC Domain 3 configuration register,                                     Address offset: 0x20  */
+ uint32_t     RESERVED2;       /*!< Reserved,                                                                Address offset: 0x24  */
+ __IO uint32_t PLLCKSELR;      /*!< RCC PLLs Clock Source Selection Register,                                Address offset: 0x28  */
+ __IO uint32_t PLLCFGR;        /*!< RCC PLLs  Configuration Register,                                        Address offset: 0x2C  */
+ __IO uint32_t PLL1DIVR;       /*!< RCC PLL1 Dividers Configuration Register,                                Address offset: 0x30  */
+ __IO uint32_t PLL1FRACR;      /*!< RCC PLL1 Fractional Divider Configuration Register,                      Address offset: 0x34  */
+ __IO uint32_t PLL2DIVR;       /*!< RCC PLL2 Dividers Configuration Register,                                Address offset: 0x38  */
+ __IO uint32_t PLL2FRACR;      /*!< RCC PLL2 Fractional Divider Configuration Register,                      Address offset: 0x3C  */
+ __IO uint32_t PLL3DIVR;       /*!< RCC PLL3 Dividers Configuration Register,                                Address offset: 0x40  */
+ __IO uint32_t PLL3FRACR;      /*!< RCC PLL3 Fractional Divider Configuration Register,                      Address offset: 0x44  */
+ uint32_t      RESERVED3;      /*!< Reserved,                                                                Address offset: 0x48  */
+ __IO uint32_t  D1CCIPR;       /*!< RCC Domain 1 Kernel Clock Configuration Register                         Address offset: 0x4C  */
+ __IO uint32_t  D2CCIP1R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x50  */
+ __IO uint32_t  D2CCIP2R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x54  */
+ __IO uint32_t  D3CCIPR;       /*!< RCC Domain 3 Kernel Clock Configuration Register                         Address offset: 0x58  */
+ uint32_t      RESERVED4;      /*!< Reserved,                                                                Address offset: 0x5C  */
+ __IO uint32_t  CIER;          /*!< RCC Clock Source Interrupt Enable Register                               Address offset: 0x60  */
+ __IO uint32_t  CIFR;          /*!< RCC Clock Source Interrupt Flag Register                                 Address offset: 0x64  */
+ __IO uint32_t  CICR;          /*!< RCC Clock Source Interrupt Clear Register                                Address offset: 0x68  */
+ uint32_t     RESERVED5;       /*!< Reserved,                                                                Address offset: 0x6C  */
+ __IO uint32_t  BDCR;          /*!< RCC Vswitch Backup Domain Control Register,                              Address offset: 0x70  */
+ __IO uint32_t  CSR;           /*!< RCC clock control & status register,                                     Address offset: 0x74  */
+ uint32_t     RESERVED6;       /*!< Reserved,                                                                Address offset: 0x78  */
+ __IO uint32_t AHB3RSTR;       /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x7C  */
+ __IO uint32_t AHB1RSTR;       /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x80  */
+ __IO uint32_t AHB2RSTR;       /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x84  */
+ __IO uint32_t AHB4RSTR;       /*!< RCC AHB4 peripheral reset register,                                      Address offset: 0x88  */
+ __IO uint32_t APB3RSTR;       /*!< RCC APB3 peripheral reset register,                                      Address offset: 0x8C  */
+ __IO uint32_t APB1LRSTR;      /*!< RCC APB1 peripheral reset Low Word register,                             Address offset: 0x90  */
+ __IO uint32_t APB1HRSTR;      /*!< RCC APB1 peripheral reset High Word register,                            Address offset: 0x94  */
+ __IO uint32_t APB2RSTR;       /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x98  */
+ __IO uint32_t APB4RSTR;       /*!< RCC APB4 peripheral reset register,                                      Address offset: 0x9C  */
+ __IO uint32_t GCR;            /*!< RCC RCC Global Control  Register,                                        Address offset: 0xA0  */
+ uint32_t     RESERVED8;       /*!< Reserved,                                                                Address offset: 0xA4  */
+ __IO uint32_t D3AMR;          /*!< RCC Domain 3 Autonomous Mode Register,                                   Address offset: 0xA8  */
+ uint32_t     RESERVED11[9];    /*!< Reserved, 0xAC-0xCC                                                      Address offset: 0xAC  */
+ __IO uint32_t RSR;            /*!< RCC Reset status register,                                               Address offset: 0xD0  */
+ __IO uint32_t AHB3ENR;        /*!< RCC AHB3 peripheral clock  register,                                     Address offset: 0xD4  */
+ __IO uint32_t AHB1ENR;        /*!< RCC AHB1 peripheral clock  register,                                     Address offset: 0xD8  */
+ __IO uint32_t AHB2ENR;        /*!< RCC AHB2 peripheral clock  register,                                     Address offset: 0xDC  */
+ __IO uint32_t AHB4ENR;        /*!< RCC AHB4 peripheral clock  register,                                     Address offset: 0xE0  */
+ __IO uint32_t APB3ENR;        /*!< RCC APB3 peripheral clock  register,                                     Address offset: 0xE4  */
+ __IO uint32_t APB1LENR;       /*!< RCC APB1 peripheral clock  Low Word register,                            Address offset: 0xE8  */
+ __IO uint32_t APB1HENR;       /*!< RCC APB1 peripheral clock  High Word register,                           Address offset: 0xEC  */
+ __IO uint32_t APB2ENR;        /*!< RCC APB2 peripheral clock  register,                                     Address offset: 0xF0  */
+ __IO uint32_t APB4ENR;        /*!< RCC APB4 peripheral clock  register,                                     Address offset: 0xF4  */
+ uint32_t      RESERVED12;      /*!< Reserved,                                                                Address offset: 0xF8  */
+ __IO uint32_t AHB3LPENR;      /*!< RCC AHB3 peripheral sleep clock  register,                               Address offset: 0xFC  */
+ __IO uint32_t AHB1LPENR;      /*!< RCC AHB1 peripheral sleep clock  register,                               Address offset: 0x100 */
+ __IO uint32_t AHB2LPENR;      /*!< RCC AHB2 peripheral sleep clock  register,                               Address offset: 0x104 */
+ __IO uint32_t AHB4LPENR;      /*!< RCC AHB4 peripheral sleep clock  register,                               Address offset: 0x108 */
+ __IO uint32_t APB3LPENR;      /*!< RCC APB3 peripheral sleep clock  register,                               Address offset: 0x10C */
+ __IO uint32_t APB1LLPENR;     /*!< RCC APB1 peripheral sleep clock  Low Word register,                      Address offset: 0x110 */
+ __IO uint32_t APB1HLPENR;     /*!< RCC APB1 peripheral sleep clock  High Word register,                     Address offset: 0x114 */
+ __IO uint32_t APB2LPENR;      /*!< RCC APB2 peripheral sleep clock  register,                               Address offset: 0x118 */
+ __IO uint32_t APB4LPENR;      /*!< RCC APB4 peripheral sleep clock  register,                               Address offset: 0x11C */
+ uint32_t     RESERVED13[4];   /*!< Reserved, 0x120-0x12C                                                    Address offset: 0x120 */
+
+} RCC_TypeDef;
+
+
+/**
+  * @brief Real-Time Clock
+  */
+typedef struct
+{
+  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
+  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
+  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
+  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
+  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
+  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
+       uint32_t RESERVED;   /*!< Reserved,                                                  Address offset: 0x18 */
+  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
+  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
+  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
+  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
+  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
+  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
+  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
+  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
+  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
+  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */
+  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
+  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
+  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset: 0x4C */
+  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
+  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
+  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
+  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
+  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
+  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */
+  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */
+  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */
+  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */
+  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
+  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */
+  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */
+  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */
+  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */
+  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */
+  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */
+  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */
+  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */
+  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */
+  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */
+  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */
+  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */
+  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */
+  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */
+  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */
+  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */
+  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */
+  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */
+  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */
+  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */
+  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */
+  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */
+} RTC_TypeDef;
+
+/**
+  * @brief Serial Audio Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t GCR;           /*!< SAI global configuration register, Address offset: 0x00 */
+  uint32_t      RESERVED0[16]; /*!< Reserved, 0x04 - 0x43                                   */
+  __IO uint32_t PDMCR;         /*!< SAI PDM control register,          Address offset: 0x44 */
+  __IO uint32_t PDMDLY;        /*!< SAI PDM delay register,            Address offset: 0x48 */
+} SAI_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */
+  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */
+  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */
+  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */
+  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
+  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */
+  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */
+  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+/**
+  * @brief SPDIF-RX Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t   CR;           /*!< Control register,                   Address offset: 0x00 */
+  __IO uint32_t   IMR;          /*!< Interrupt mask register,            Address offset: 0x04 */
+  __IO uint32_t   SR;           /*!< Status register,                    Address offset: 0x08 */
+  __IO uint32_t   IFCR;         /*!< Interrupt Flag Clear register,      Address offset: 0x0C */
+  __IO uint32_t   DR;           /*!< Data input register,                Address offset: 0x10 */
+  __IO uint32_t   CSR;          /*!< Channel Status register,            Address offset: 0x14 */
+  __IO uint32_t   DIR;          /*!< Debug Information register,         Address offset: 0x18 */
+  uint32_t        RESERVED2;    /*!< Reserved,  0x1A                                          */
+} SPDIFRX_TypeDef;
+
+
+/**
+  * @brief Secure digital input/output Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t POWER;          /*!< SDMMC power control register,             Address offset: 0x00  */
+  __IO uint32_t CLKCR;          /*!< SDMMC clock control register,             Address offset: 0x04  */
+  __IO uint32_t ARG;            /*!< SDMMC argument register,                  Address offset: 0x08  */
+  __IO uint32_t CMD;            /*!< SDMMC command register,                   Address offset: 0x0C  */
+  __I uint32_t  RESPCMD;        /*!< SDMMC command response register,          Address offset: 0x10  */
+  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,                Address offset: 0x14  */
+  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,                Address offset: 0x18  */
+  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,                Address offset: 0x1C  */
+  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,                Address offset: 0x20  */
+  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,                Address offset: 0x24  */
+  __IO uint32_t DLEN;           /*!< SDMMC data length register,               Address offset: 0x28  */
+  __IO uint32_t DCTRL;          /*!< SDMMC data control register,              Address offset: 0x2C  */
+  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,              Address offset: 0x30  */
+  __I uint32_t  STA;            /*!< SDMMC status register,                    Address offset: 0x34  */
+  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,           Address offset: 0x38  */
+  __IO uint32_t MASK;           /*!< SDMMC mask register,                      Address offset: 0x3C  */
+  __IO uint32_t ACKTIME;        /*!< SDMMC Acknowledgement timer register,     Address offset: 0x40  */
+  uint32_t      RESERVED0[3];   /*!< Reserved, 0x44 - 0x4C - 0x4C                                    */
+  __IO uint32_t IDMACTRL;       /*!< SDMMC DMA control register,               Address offset: 0x50  */
+  __IO uint32_t IDMABSIZE;      /*!< SDMMC DMA buffer size register,           Address offset: 0x54  */
+  __IO uint32_t IDMABASE0;      /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58  */
+  __IO uint32_t IDMABASE1;      /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C  */
+  uint32_t      RESERVED1[8];   /*!< Reserved, 0x60-0x7C                                             */
+  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,                 Address offset: 0x80  */
+  uint32_t      RESERVED2[222]; /*!< Reserved, 0x84-0x3F8                                            */
+  __IO uint32_t IPVR;           /*!< SDMMC data FIFO register,                 Address offset: 0x3FC */
+} SDMMC_TypeDef;
+
+
+/**
+  * @brief Delay Block DLYB
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< DELAY BLOCK control register,  Address offset: 0x00 */
+  __IO uint32_t CFGR;        /*!< DELAY BLOCK configuration register,  Address offset: 0x04 */
+} DLYB_TypeDef;
+
+/**
+  * @brief HW Semaphore HSEM
+  */
+
+typedef struct
+{
+  __IO uint32_t R[32];      /*!< 2-step write lock and read back registers,     Address offset: 00h-7Ch  */
+  __IO uint32_t RLR[32];    /*!< 1-step read lock registers,                    Address offset: 80h-FCh  */
+  __IO uint32_t C1IER;      /*!< HSEM Interrupt enable register ,             Address offset: 100h     */
+  __IO uint32_t C1ICR;      /*!< HSEM Interrupt clear register ,              Address offset: 104h     */
+  __IO uint32_t C1ISR;      /*!< HSEM Interrupt Status register ,             Address offset: 108h     */
+  __IO uint32_t C1MISR;     /*!< HSEM Interrupt Masked Status register ,      Address offset: 10Ch     */
+  uint32_t  Reserved[12];   /* Reserved                                       Address offset: 110h-13Ch  */
+  __IO uint32_t CR;         /*!< HSEM Semaphore clear register ,                Address offset: 140h      */
+  __IO uint32_t KEYR;       /*!< HSEM Semaphore clear key register ,            Address offset: 144h      */
+
+} HSEM_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t IER;        /*!< HSEM interrupt enable register ,                Address offset:   0h     */
+  __IO uint32_t ICR;        /*!< HSEM interrupt clear register ,                 Address offset:   4h     */
+  __IO uint32_t ISR;        /*!< HSEM interrupt status register ,                Address offset:   8h     */
+  __IO uint32_t MISR;       /*!< HSEM masked interrupt status register ,         Address offset:   Ch     */
+} HSEM_Common_TypeDef;
+
+/**
+  * @brief Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;           /*!< SPI/I2S Control register 1,                      Address offset: 0x00 */
+  __IO uint32_t CR2;           /*!< SPI Control register 2,                          Address offset: 0x04 */
+  __IO uint32_t CFG1;          /*!< SPI Configuration register 1,                    Address offset: 0x08 */
+  __IO uint32_t CFG2;          /*!< SPI Configuration register 2,                    Address offset: 0x0C */
+  __IO uint32_t IER;           /*!< SPI/I2S Interrupt Enable register,               Address offset: 0x10 */
+  __IO uint32_t SR;            /*!< SPI/I2S Status register,                         Address offset: 0x14 */
+  __IO uint32_t IFCR;          /*!< SPI/I2S Interrupt/Status flags clear register,   Address offset: 0x18 */
+  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                        */
+  __IO uint32_t TXDR;          /*!< SPI/I2S Transmit data register,                  Address offset: 0x20 */
+  uint32_t      RESERVED1[3];  /*!< Reserved, 0x24-0x2C                                                   */
+  __IO uint32_t RXDR;          /*!< SPI/I2S Receive data register,                   Address offset: 0x30 */
+  uint32_t      RESERVED2[3];  /*!< Reserved, 0x34-0x3C                                                   */
+  __IO uint32_t CRCPOLY;       /*!< SPI CRC Polynomial register,                     Address offset: 0x40 */
+  __IO uint32_t TXCRC;         /*!< SPI Transmitter CRC register,                    Address offset: 0x44 */
+  __IO uint32_t RXCRC;         /*!< SPI Receiver CRC register,                       Address offset: 0x48 */
+  __IO uint32_t UDRDR;         /*!< SPI Underrun data register,                      Address offset: 0x4C */
+  __IO uint32_t I2SCFGR;       /*!< I2S Configuration register,                      Address offset: 0x50 */
+
+} SPI_TypeDef;
+/**
+  * @brief QUAD Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< QUADSPI Control register,                           Address offset: 0x00 */
+  __IO uint32_t DCR;      /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */
+  __IO uint32_t SR;       /*!< QUADSPI Status register,                            Address offset: 0x08 */
+  __IO uint32_t FCR;      /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */
+  __IO uint32_t DLR;      /*!< QUADSPI Data Length register,                       Address offset: 0x10 */
+  __IO uint32_t CCR;      /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */
+  __IO uint32_t AR;       /*!< QUADSPI Address register,                           Address offset: 0x18 */
+  __IO uint32_t ABR;      /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */
+  __IO uint32_t DR;       /*!< QUADSPI Data register,                              Address offset: 0x20 */
+  __IO uint32_t PSMKR;    /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */
+  __IO uint32_t PSMAR;    /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */
+  __IO uint32_t PIR;      /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */
+  __IO uint32_t LPTR;     /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */
+} QUADSPI_TypeDef;
+
+/**
+  * @brief TIM
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */
+  __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */
+  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */
+  __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */
+  __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */
+  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */
+  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */
+  __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */
+  __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */
+  __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */
+  __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */
+  __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */
+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */
+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */
+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */
+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */
+  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */
+  __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */
+  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */
+  uint32_t      RESERVED1;   /*!< Reserved, 0x50                                                 */
+  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */
+  __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */
+  __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */
+  __IO uint32_t AF1;         /*!< TIM alternate function option register 1, Address offset: 0x60 */
+  __IO uint32_t AF2;         /*!< TIM alternate function option register 2, Address offset: 0x64 */
+  __IO uint32_t TISEL;       /*!< TIM Input Selection register,             Address offset: 0x68 */
+} TIM_TypeDef;
+
+/**
+  * @brief LPTIMIMER
+  */
+typedef struct
+{
+  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,         Address offset: 0x00 */
+  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,              Address offset: 0x04 */
+  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,             Address offset: 0x08 */
+  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                Address offset: 0x0C */
+  __IO uint32_t CR;       /*!< LPTIM Control register,                      Address offset: 0x10 */
+  __IO uint32_t CMP;      /*!< LPTIM Compare register,                      Address offset: 0x14 */
+  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                   Address offset: 0x18 */
+  __IO uint32_t CNT;      /*!< LPTIM Counter register,                      Address offset: 0x1C */
+  uint32_t  RESERVED1;    /*!< Reserved, 0x20                                                    */
+  __IO uint32_t CFGR2;    /*!< LPTIM Configuration register,                Address offset: 0x24 */
+} LPTIM_TypeDef;
+
+/**
+  * @brief Comparator
+  */
+typedef struct
+{
+  __IO uint32_t SR;        /*!< Comparator status register,                    Address offset: 0x00 */
+  __IO uint32_t ICFR;      /*!< Comparator interrupt clear flag register,       Address offset: 0x04 */
+  __IO uint32_t OR;        /*!< Comparator option register,                  Address offset: 0x08 */
+} COMPOPT_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CFGR;      /*!< Comparator configuration register  ,           Address offset: 0x00 */
+} COMP_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CFGR;       /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
+} COMP_Common_TypeDef;
+/**
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */
+  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */
+  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
+  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */
+  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
+  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */
+  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
+  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
+  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
+  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
+  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
+  __IO uint32_t PRESC;  /*!< USART clock Prescaler register,           Address offset: 0x2C */
+} USART_TypeDef;
+
+/**
+  * @brief Single Wire Protocol Master Interface SPWMI
+  */
+typedef struct
+{
+  __IO uint32_t CR;          /*!< SWPMI Configuration/Control register,     Address offset: 0x00 */
+  __IO uint32_t BRR;         /*!< SWPMI bitrate register,                   Address offset: 0x04 */
+    uint32_t  RESERVED1;     /*!< Reserved, 0x08                                                 */
+  __IO uint32_t ISR;         /*!< SWPMI Interrupt and Status register,      Address offset: 0x0C */
+  __IO uint32_t ICR;         /*!< SWPMI Interrupt Flag Clear register,      Address offset: 0x10 */
+  __IO uint32_t IER;         /*!< SWPMI Interrupt Enable register,          Address offset: 0x14 */
+  __IO uint32_t RFL;         /*!< SWPMI Receive Frame Length register,      Address offset: 0x18 */
+  __IO uint32_t TDR;         /*!< SWPMI Transmit data register,             Address offset: 0x1C */
+  __IO uint32_t RDR;         /*!< SWPMI Receive data register,              Address offset: 0x20 */
+  __IO uint32_t OR;          /*!< SWPMI Option register,                    Address offset: 0x24 */
+} SWPMI_TypeDef;
+
+/**
+  * @brief Window WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
+} WWDG_TypeDef;
+
+
+/**
+  * @brief RAM_ECC_Specific_Registers
+  */
+typedef struct
+{
+  __IO uint32_t CR;           /*!< RAMECC monitor configuration register          */
+  __IO uint32_t SR;           /*!< RAMECC monitor status register                 */
+  __IO uint32_t FAR;          /*!< RAMECC monitor failing address register        */
+  __IO uint32_t FDRL;         /*!< RAMECC monitor failing data low register       */
+  __IO uint32_t FDRH;         /*!< RAMECC monitor failing data high register      */
+  __IO uint32_t FECR;         /*!< RAMECC monitor failing ECC error code register */
+} RAMECC_MonitorTypeDef;
+
+typedef struct
+{
+  __IO uint32_t IER;          /*!< RAMECC interrupt enable register */
+} RAMECC_TypeDef;
+/**
+  * @}
+  */
+
+
+
+/**
+  * @brief High resolution Timer (HRTIM)
+  */
+/* HRTIM master registers definition */
+typedef struct
+{
+  __IO uint32_t MCR;            /*!< HRTIM Master Timer control register,                     Address offset: 0x00 */
+  __IO uint32_t MISR;           /*!< HRTIM Master Timer interrupt status register,            Address offset: 0x04 */
+  __IO uint32_t MICR;           /*!< HRTIM Master Timer interupt clear register,              Address offset: 0x08 */
+  __IO uint32_t MDIER;          /*!< HRTIM Master Timer DMA/interrupt enable register         Address offset: 0x0C */
+  __IO uint32_t MCNTR;          /*!< HRTIM Master Timer counter register,                     Address offset: 0x10 */
+  __IO uint32_t MPER;           /*!< HRTIM Master Timer period register,                      Address offset: 0x14 */
+  __IO uint32_t MREP;           /*!< HRTIM Master Timer repetition register,                  Address offset: 0x18 */
+  __IO uint32_t MCMP1R;         /*!< HRTIM Master Timer compare 1 register,                   Address offset: 0x1C */
+  uint32_t      RESERVED0;     /*!< Reserved,                                                                 0x20 */
+  __IO uint32_t MCMP2R;         /*!< HRTIM Master Timer compare 2 register,                   Address offset: 0x24 */
+  __IO uint32_t MCMP3R;         /*!< HRTIM Master Timer compare 3 register,                   Address offset: 0x28 */
+  __IO uint32_t MCMP4R;         /*!< HRTIM Master Timer compare 4 register,                   Address offset: 0x2C */
+  uint32_t      RESERVED1[20];  /*!< Reserved,                                                          0x30..0x7C */
+}HRTIM_Master_TypeDef;
+
+/* HRTIM Timer A to E registers definition */
+typedef struct
+{
+  __IO uint32_t TIMxCR;     /*!< HRTIM Timerx control register,                              Address offset: 0x00 */
+  __IO uint32_t TIMxISR;    /*!< HRTIM Timerx interrupt status register,                     Address offset: 0x04 */
+  __IO uint32_t TIMxICR;    /*!< HRTIM Timerx interrupt clear register,                      Address offset: 0x08 */
+  __IO uint32_t TIMxDIER;   /*!< HRTIM Timerx DMA/interrupt enable register,                 Address offset: 0x0C */
+  __IO uint32_t CNTxR;      /*!< HRTIM Timerx counter register,                              Address offset: 0x10 */
+  __IO uint32_t PERxR;      /*!< HRTIM Timerx period register,                               Address offset: 0x14 */
+  __IO uint32_t REPxR;      /*!< HRTIM Timerx repetition register,                           Address offset: 0x18 */
+  __IO uint32_t CMP1xR;     /*!< HRTIM Timerx compare 1 register,                            Address offset: 0x1C */
+  __IO uint32_t CMP1CxR;    /*!< HRTIM Timerx compare 1 compound register,                   Address offset: 0x20 */
+  __IO uint32_t CMP2xR;     /*!< HRTIM Timerx compare 2 register,                            Address offset: 0x24 */
+  __IO uint32_t CMP3xR;     /*!< HRTIM Timerx compare 3 register,                            Address offset: 0x28 */
+  __IO uint32_t CMP4xR;     /*!< HRTIM Timerx compare 4 register,                            Address offset: 0x2C */
+  __IO uint32_t CPT1xR;     /*!< HRTIM Timerx capture 1 register,                            Address offset: 0x30 */
+  __IO uint32_t CPT2xR;     /*!< HRTIM Timerx capture 2 register,                            Address offset: 0x34 */
+  __IO uint32_t DTxR;       /*!< HRTIM Timerx dead time register,                            Address offset: 0x38 */
+  __IO uint32_t SETx1R;     /*!< HRTIM Timerx output 1 set register,                         Address offset: 0x3C */
+  __IO uint32_t RSTx1R;     /*!< HRTIM Timerx output 1 reset register,                       Address offset: 0x40 */
+  __IO uint32_t SETx2R;     /*!< HRTIM Timerx output 2 set register,                         Address offset: 0x44 */
+  __IO uint32_t RSTx2R;     /*!< HRTIM Timerx output 2 reset register,                       Address offset: 0x48 */
+  __IO uint32_t EEFxR1;     /*!< HRTIM Timerx external event filtering 1 register,           Address offset: 0x4C */
+  __IO uint32_t EEFxR2;     /*!< HRTIM Timerx external event filtering 2 register,           Address offset: 0x50 */
+  __IO uint32_t RSTxR;      /*!< HRTIM Timerx Reset register,                                Address offset: 0x54 */
+  __IO uint32_t CHPxR;      /*!< HRTIM Timerx Chopper register,                              Address offset: 0x58 */
+  __IO uint32_t CPT1xCR;    /*!< HRTIM Timerx Capture 1 register,                            Address offset: 0x5C */
+  __IO uint32_t CPT2xCR;    /*!< HRTIM Timerx Capture 2 register,                            Address offset: 0x60 */
+  __IO uint32_t OUTxR;      /*!< HRTIM Timerx Output register,                               Address offset: 0x64 */
+  __IO uint32_t FLTxR;      /*!< HRTIM Timerx Fault register,                                Address offset: 0x68 */
+  uint32_t      RESERVED0[5];  /*!< Reserved,                                                          0x6C..0x7C */
+}HRTIM_Timerx_TypeDef;
+
+/* HRTIM common register definition */
+typedef struct
+{
+  __IO uint32_t CR1;        /*!< HRTIM control register1,                                    Address offset: 0x00 */
+  __IO uint32_t CR2;        /*!< HRTIM control register2,                                    Address offset: 0x04 */
+  __IO uint32_t ISR;        /*!< HRTIM interrupt status register,                            Address offset: 0x08 */
+  __IO uint32_t ICR;        /*!< HRTIM interrupt clear register,                             Address offset: 0x0C */
+  __IO uint32_t IER;        /*!< HRTIM interrupt enable register,                            Address offset: 0x10 */
+  __IO uint32_t OENR;       /*!< HRTIM Output enable register,                               Address offset: 0x14 */
+  __IO uint32_t ODISR;      /*!< HRTIM Output disable register,                              Address offset: 0x18 */
+  __IO uint32_t ODSR;       /*!< HRTIM Output disable status register,                       Address offset: 0x1C */
+  __IO uint32_t BMCR;       /*!< HRTIM Burst mode control register,                          Address offset: 0x20 */
+  __IO uint32_t BMTRGR;     /*!< HRTIM Busrt mode trigger register,                          Address offset: 0x24 */
+  __IO uint32_t BMCMPR;     /*!< HRTIM Burst mode compare register,                          Address offset: 0x28 */
+  __IO uint32_t BMPER;      /*!< HRTIM Burst mode period register,                           Address offset: 0x2C */
+  __IO uint32_t EECR1;      /*!< HRTIM Timer external event control register1,               Address offset: 0x30 */
+  __IO uint32_t EECR2;      /*!< HRTIM Timer external event control register2,               Address offset: 0x34 */
+  __IO uint32_t EECR3;      /*!< HRTIM Timer external event control register3,               Address offset: 0x38 */
+  __IO uint32_t ADC1R;      /*!< HRTIM ADC Trigger 1 register,                               Address offset: 0x3C */
+  __IO uint32_t ADC2R;      /*!< HRTIM ADC Trigger 2 register,                               Address offset: 0x40 */
+  __IO uint32_t ADC3R;      /*!< HRTIM ADC Trigger 3 register,                               Address offset: 0x44 */
+  __IO uint32_t ADC4R;      /*!< HRTIM ADC Trigger 4 register,                               Address offset: 0x48 */
+  __IO uint32_t RESERVED0;  /*!< Reserved,                                                   Address offset: 0x4C */
+  __IO uint32_t FLTINR1;    /*!< HRTIM Fault input register1,                                Address offset: 0x50 */
+  __IO uint32_t FLTINR2;    /*!< HRTIM Fault input register2,                                Address offset: 0x54 */
+  __IO uint32_t BDMUPR;     /*!< HRTIM Burst DMA Master Timer update register,               Address offset: 0x58 */
+  __IO uint32_t BDTAUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x5C */
+  __IO uint32_t BDTBUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x60 */
+  __IO uint32_t BDTCUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x64 */
+  __IO uint32_t BDTDUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x68 */
+  __IO uint32_t BDTEUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x6C */
+  __IO uint32_t BDMADR;     /*!< HRTIM Burst DMA Master Data register,                       Address offset: 0x70 */
+}HRTIM_Common_TypeDef;
+
+/* HRTIM  register definition */
+typedef struct {
+  HRTIM_Master_TypeDef sMasterRegs;
+  HRTIM_Timerx_TypeDef sTimerxRegs[5];
+  uint32_t             RESERVED0[32];
+  HRTIM_Common_TypeDef sCommonRegs;
+}HRTIM_TypeDef;
+/**
+  * @brief RNG
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
+} RNG_TypeDef;
+
+/**
+  * @brief MDIOS
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;
+  __IO uint32_t WRFR;
+  __IO uint32_t CWRFR;
+  __IO uint32_t RDFR;
+  __IO uint32_t CRDFR;
+  __IO uint32_t SR;
+  __IO uint32_t CLRFR;
+  uint32_t RESERVED[57];
+  __IO uint32_t DINR0;
+  __IO uint32_t DINR1;
+  __IO uint32_t DINR2;
+  __IO uint32_t DINR3;
+  __IO uint32_t DINR4;
+  __IO uint32_t DINR5;
+  __IO uint32_t DINR6;
+  __IO uint32_t DINR7;
+  __IO uint32_t DINR8;
+  __IO uint32_t DINR9;
+  __IO uint32_t DINR10;
+  __IO uint32_t DINR11;
+  __IO uint32_t DINR12;
+  __IO uint32_t DINR13;
+  __IO uint32_t DINR14;
+  __IO uint32_t DINR15;
+  __IO uint32_t DINR16;
+  __IO uint32_t DINR17;
+  __IO uint32_t DINR18;
+  __IO uint32_t DINR19;
+  __IO uint32_t DINR20;
+  __IO uint32_t DINR21;
+  __IO uint32_t DINR22;
+  __IO uint32_t DINR23;
+  __IO uint32_t DINR24;
+  __IO uint32_t DINR25;
+  __IO uint32_t DINR26;
+  __IO uint32_t DINR27;
+  __IO uint32_t DINR28;
+  __IO uint32_t DINR29;
+  __IO uint32_t DINR30;
+  __IO uint32_t DINR31;
+  __IO uint32_t DOUTR0;
+  __IO uint32_t DOUTR1;
+  __IO uint32_t DOUTR2;
+  __IO uint32_t DOUTR3;
+  __IO uint32_t DOUTR4;
+  __IO uint32_t DOUTR5;
+  __IO uint32_t DOUTR6;
+  __IO uint32_t DOUTR7;
+  __IO uint32_t DOUTR8;
+  __IO uint32_t DOUTR9;
+  __IO uint32_t DOUTR10;
+  __IO uint32_t DOUTR11;
+  __IO uint32_t DOUTR12;
+  __IO uint32_t DOUTR13;
+  __IO uint32_t DOUTR14;
+  __IO uint32_t DOUTR15;
+  __IO uint32_t DOUTR16;
+  __IO uint32_t DOUTR17;
+  __IO uint32_t DOUTR18;
+  __IO uint32_t DOUTR19;
+  __IO uint32_t DOUTR20;
+  __IO uint32_t DOUTR21;
+  __IO uint32_t DOUTR22;
+  __IO uint32_t DOUTR23;
+  __IO uint32_t DOUTR24;
+  __IO uint32_t DOUTR25;
+  __IO uint32_t DOUTR26;
+  __IO uint32_t DOUTR27;
+  __IO uint32_t DOUTR28;
+  __IO uint32_t DOUTR29;
+  __IO uint32_t DOUTR30;
+  __IO uint32_t DOUTR31;
+} MDIOS_TypeDef;
+
+
+/**
+  * @brief USB_OTG_Core_Registers
+  */
+typedef struct
+{
+ __IO uint32_t GOTGCTL;               /*!< USB_OTG Control and Status Register          000h */
+  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */
+  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */
+  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */
+  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */
+  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */
+  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */
+  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */
+  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */
+  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */
+  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */
+  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */
+  uint32_t Reserved30[2];             /*!< Reserved                                     030h */
+  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */
+  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */
+  __IO uint32_t GSNPSID;              /* USB_OTG core ID                                040h*/
+  __IO uint32_t GHWCFG1;              /* User HW config1                                044h*/
+  __IO uint32_t GHWCFG2;              /* User HW config2                                048h*/
+  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */
+  uint32_t  Reserved6;                /*!< Reserved                                     050h */
+  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */
+  __IO uint32_t GPWRDN;               /*!< Power Down Register                          058h */
+  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */
+   __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register       60Ch */
+    uint32_t  Reserved43[39];         /*!< Reserved                                058h-0FFh */
+  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */
+  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */
+} USB_OTG_GlobalTypeDef;
+
+
+/**
+  * @brief USB_OTG_device_Registers
+  */
+typedef struct
+{
+  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */
+  __IO uint32_t DCTL;            /*!< dev Control Register         804h */
+  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */
+  uint32_t Reserved0C;           /*!< Reserved                     80Ch */
+  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */
+  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */
+  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */
+  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */
+  uint32_t  Reserved20;          /*!< Reserved                     820h */
+  uint32_t Reserved9;            /*!< Reserved                     824h */
+  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */
+  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */
+  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */
+  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */
+  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */
+  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */
+  uint32_t Reserved40;           /*!< dedicated EP mask            840h */
+  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */
+  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */
+  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */
+} USB_OTG_DeviceTypeDef;
+
+
+/**
+  * @brief USB_OTG_IN_Endpoint-Specific_Register
+  */
+typedef struct
+{
+  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */
+  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */
+  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */
+  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */
+  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */
+  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */
+  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+
+/**
+  * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+  */
+typedef struct
+{
+  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */
+  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */
+  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */
+  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */
+  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */
+  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */
+  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
+} USB_OTG_OUTEndpointTypeDef;
+
+
+/**
+  * @brief USB_OTG_Host_Mode_Register_Structures
+  */
+typedef struct
+{
+  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */
+  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */
+  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */
+  uint32_t Reserved40C;           /*!< Reserved                             40Ch */
+  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */
+  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */
+  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */
+} USB_OTG_HostTypeDef;
+
+/**
+  * @brief USB_OTG_Host_Channel_Specific_Registers
+  */
+typedef struct
+{
+  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */
+  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */
+  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */
+  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */
+  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */
+  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */
+  uint32_t Reserved[2];           /*!< Reserved                                      */
+} USB_OTG_HostChannelTypeDef;
+/**
+  * @}
+  */
+
+
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+#define D1_ITCMRAM_BASE           (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM  */
+#define D1_ITCMICP_BASE           (0x00100000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM         */
+#define D1_DTCMRAM_BASE           (0x20000000UL) /*!< Base address of : 128KB system data RAM accessible over DTCM                            */
+#define D1_AXIFLASH_BASE          (0x08000000UL) /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI                */
+#define D1_AXIICP_BASE            (0x1FF00000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI          */
+#define D1_AXISRAM_BASE           (0x24000000UL) /*!< Base address of : (up to 512KB) system data RAM accessible over over AXI                */
+
+#define D2_AXISRAM_BASE           (0x10000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI                */
+#define D2_AHBSRAM_BASE           (0x30000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI->AHB Bridge    */
+
+#define D3_BKPSRAM_BASE           (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge                                */
+#define D3_SRAM_BASE              (0x38000000UL) /*!< Base address of : Backup SRAM(64 KB) over AXI->AHB Bridge                               */
+
+#define PERIPH_BASE               (0x40000000UL) /*!< Base address of : AHB/APB Peripherals                                                   */
+#define QSPI_BASE                 (0x90000000UL) /*!< Base address of : QSPI memories  accessible over AXI                                    */
+
+#define FLASH_BANK1_BASE          (0x08000000UL) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI                          */
+#define FLASH_BANK2_BASE          (0x08100000UL) /*!< Base address of : (up to 1 MB) Flash Bank2 accessible over AXI                          */
+#define FLASH_END                 (0x081FFFFFUL) /*!< FLASH end address                                                                       */
+
+/* Legacy define */
+#define FLASH_BASE                FLASH_BANK1_BASE
+
+/*!< Device electronic signature memory map */
+#define UID_BASE                  (0x1FF1E800UL)            /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE            (0x1FF1E880UL)            /*!< FLASH Size register base address */
+
+
+/*!< Peripheral memory map */
+#define D2_APB1PERIPH_BASE        PERIPH_BASE
+#define D2_APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
+#define D2_AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
+#define D2_AHB2PERIPH_BASE       (PERIPH_BASE + 0x08020000UL)
+
+#define D1_APB1PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)
+#define D1_AHB1PERIPH_BASE       (PERIPH_BASE + 0x12000000UL)
+
+#define D3_APB1PERIPH_BASE       (PERIPH_BASE + 0x18000000UL)
+#define D3_AHB1PERIPH_BASE       (PERIPH_BASE + 0x18020000UL)
+
+/*!< Legacy Peripheral memory map */
+#define APB1PERIPH_BASE        PERIPH_BASE
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000UL)
+
+
+/*!< D1_AHB1PERIPH peripherals */
+
+#define MDMA_BASE             (D1_AHB1PERIPH_BASE + 0x0000UL)
+#define DMA2D_BASE            (D1_AHB1PERIPH_BASE + 0x1000UL)
+#define JPGDEC_BASE           (D1_AHB1PERIPH_BASE + 0x3000UL)
+#define FLASH_R_BASE          (D1_AHB1PERIPH_BASE + 0x2000UL)
+#define FMC_R_BASE            (D1_AHB1PERIPH_BASE + 0x4000UL)
+#define QSPI_R_BASE           (D1_AHB1PERIPH_BASE + 0x5000UL)
+#define DLYB_QSPI_BASE        (D1_AHB1PERIPH_BASE + 0x6000UL)
+#define SDMMC1_BASE           (D1_AHB1PERIPH_BASE + 0x7000UL)
+#define DLYB_SDMMC1_BASE      (D1_AHB1PERIPH_BASE + 0x8000UL)
+#define RAMECC1_BASE          (D1_AHB1PERIPH_BASE + 0x9000UL)
+
+/*!< D2_AHB1PERIPH peripherals */
+
+#define DMA1_BASE               (D2_AHB1PERIPH_BASE + 0x0000UL)
+#define DMA2_BASE               (D2_AHB1PERIPH_BASE + 0x0400UL)
+#define DMAMUX1_BASE            (D2_AHB1PERIPH_BASE + 0x0800UL)
+#define ADC1_BASE               (D2_AHB1PERIPH_BASE + 0x2000UL)
+#define ADC2_BASE               (D2_AHB1PERIPH_BASE + 0x2100UL)
+#define ADC12_COMMON_BASE       (D2_AHB1PERIPH_BASE + 0x2300UL)
+#define ETH_BASE                (D2_AHB1PERIPH_BASE + 0x8000UL)
+#define ETH_MAC_BASE            (ETH_BASE)
+
+/*!< USB registers base address */
+#define USB1_OTG_HS_PERIPH_BASE              (0x40040000UL)
+#define USB2_OTG_FS_PERIPH_BASE              (0x40080000UL)
+#define USB_OTG_GLOBAL_BASE                  (0x000UL)
+#define USB_OTG_DEVICE_BASE                  (0x800UL)
+#define USB_OTG_IN_ENDPOINT_BASE             (0x900UL)
+#define USB_OTG_OUT_ENDPOINT_BASE            (0xB00UL)
+#define USB_OTG_EP_REG_SIZE                  (0x20UL)
+#define USB_OTG_HOST_BASE                    (0x400UL)
+#define USB_OTG_HOST_PORT_BASE               (0x440UL)
+#define USB_OTG_HOST_CHANNEL_BASE            (0x500UL)
+#define USB_OTG_HOST_CHANNEL_SIZE            (0x20UL)
+#define USB_OTG_PCGCCTL_BASE                 (0xE00UL)
+#define USB_OTG_FIFO_BASE                    (0x1000UL)
+#define USB_OTG_FIFO_SIZE                    (0x1000UL)
+
+/*!< D2_AHB2PERIPH peripherals */
+
+#define DCMI_BASE              (D2_AHB2PERIPH_BASE + 0x0000UL)
+#define RNG_BASE               (D2_AHB2PERIPH_BASE + 0x1800UL)
+#define SDMMC2_BASE            (D2_AHB2PERIPH_BASE + 0x2400UL)
+#define DLYB_SDMMC2_BASE       (D2_AHB2PERIPH_BASE + 0x2800UL)
+#define RAMECC2_BASE           (D2_AHB2PERIPH_BASE + 0x3000UL)
+
+/*!< D3_AHB1PERIPH peripherals */
+#define GPIOA_BASE            (D3_AHB1PERIPH_BASE + 0x0000UL)
+#define GPIOB_BASE            (D3_AHB1PERIPH_BASE + 0x0400UL)
+#define GPIOC_BASE            (D3_AHB1PERIPH_BASE + 0x0800UL)
+#define GPIOD_BASE            (D3_AHB1PERIPH_BASE + 0x0C00UL)
+#define GPIOE_BASE            (D3_AHB1PERIPH_BASE + 0x1000UL)
+#define GPIOF_BASE            (D3_AHB1PERIPH_BASE + 0x1400UL)
+#define GPIOG_BASE            (D3_AHB1PERIPH_BASE + 0x1800UL)
+#define GPIOH_BASE            (D3_AHB1PERIPH_BASE + 0x1C00UL)
+#define GPIOI_BASE            (D3_AHB1PERIPH_BASE + 0x2000UL)
+#define GPIOJ_BASE            (D3_AHB1PERIPH_BASE + 0x2400UL)
+#define GPIOK_BASE            (D3_AHB1PERIPH_BASE + 0x2800UL)
+#define RCC_BASE              (D3_AHB1PERIPH_BASE + 0x4400UL)
+#define PWR_BASE              (D3_AHB1PERIPH_BASE + 0x4800UL)
+#define CRC_BASE              (D3_AHB1PERIPH_BASE + 0x4C00UL)
+#define BDMA_BASE             (D3_AHB1PERIPH_BASE + 0x5400UL)
+#define DMAMUX2_BASE          (D3_AHB1PERIPH_BASE + 0x5800UL)
+#define ADC3_BASE             (D3_AHB1PERIPH_BASE + 0x6000UL)
+#define ADC3_COMMON_BASE      (D3_AHB1PERIPH_BASE + 0x6300UL)
+#define HSEM_BASE             (D3_AHB1PERIPH_BASE + 0x6400UL)
+#define RAMECC3_BASE          (D3_AHB1PERIPH_BASE + 0x7000UL)
+
+/*!< D1_APB1PERIPH peripherals */
+#define LTDC_BASE             (D1_APB1PERIPH_BASE + 0x1000UL)
+#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84UL)
+#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104UL)
+#define WWDG1_BASE            (D1_APB1PERIPH_BASE + 0x3000UL)
+
+/*!< D2_APB1PERIPH peripherals */
+#define TIM2_BASE             (D2_APB1PERIPH_BASE + 0x0000UL)
+#define TIM3_BASE             (D2_APB1PERIPH_BASE + 0x0400UL)
+#define TIM4_BASE             (D2_APB1PERIPH_BASE + 0x0800UL)
+#define TIM5_BASE             (D2_APB1PERIPH_BASE + 0x0C00UL)
+#define TIM6_BASE             (D2_APB1PERIPH_BASE + 0x1000UL)
+#define TIM7_BASE             (D2_APB1PERIPH_BASE + 0x1400UL)
+#define TIM12_BASE            (D2_APB1PERIPH_BASE + 0x1800UL)
+#define TIM13_BASE            (D2_APB1PERIPH_BASE + 0x1C00UL)
+#define TIM14_BASE            (D2_APB1PERIPH_BASE + 0x2000UL)
+#define LPTIM1_BASE           (D2_APB1PERIPH_BASE + 0x2400UL)
+
+
+#define SPI2_BASE             (D2_APB1PERIPH_BASE + 0x3800UL)
+#define SPI3_BASE             (D2_APB1PERIPH_BASE + 0x3C00UL)
+#define SPDIFRX_BASE          (D2_APB1PERIPH_BASE + 0x4000UL)
+#define USART2_BASE           (D2_APB1PERIPH_BASE + 0x4400UL)
+#define USART3_BASE           (D2_APB1PERIPH_BASE + 0x4800UL)
+#define UART4_BASE            (D2_APB1PERIPH_BASE + 0x4C00UL)
+#define UART5_BASE            (D2_APB1PERIPH_BASE + 0x5000UL)
+#define I2C1_BASE             (D2_APB1PERIPH_BASE + 0x5400UL)
+#define I2C2_BASE             (D2_APB1PERIPH_BASE + 0x5800UL)
+#define I2C3_BASE             (D2_APB1PERIPH_BASE + 0x5C00UL)
+#define CEC_BASE              (D2_APB1PERIPH_BASE + 0x6C00UL)
+#define DAC1_BASE             (D2_APB1PERIPH_BASE + 0x7400UL)
+#define UART7_BASE            (D2_APB1PERIPH_BASE + 0x7800UL)
+#define UART8_BASE            (D2_APB1PERIPH_BASE + 0x7C00UL)
+#define CRS_BASE              (D2_APB1PERIPH_BASE + 0x8400UL)
+#define SWPMI1_BASE           (D2_APB1PERIPH_BASE + 0x8800UL)
+#define OPAMP_BASE            (D2_APB1PERIPH_BASE + 0x9000UL)
+#define OPAMP1_BASE           (D2_APB1PERIPH_BASE + 0x9000UL)
+#define OPAMP2_BASE           (D2_APB1PERIPH_BASE + 0x9010UL)
+#define MDIOS_BASE            (D2_APB1PERIPH_BASE + 0x9400UL)
+#define FDCAN1_BASE           (D2_APB1PERIPH_BASE + 0xA000UL)
+#define FDCAN2_BASE           (D2_APB1PERIPH_BASE + 0xA400UL)
+#define FDCAN_CCU_BASE        (D2_APB1PERIPH_BASE + 0xA800UL)
+#define SRAMCAN_BASE          (D2_APB1PERIPH_BASE + 0xAC00UL)
+
+/*!< D2_APB2PERIPH peripherals */
+
+#define TIM1_BASE             (D2_APB2PERIPH_BASE + 0x0000UL)
+#define TIM8_BASE             (D2_APB2PERIPH_BASE + 0x0400UL)
+#define USART1_BASE           (D2_APB2PERIPH_BASE + 0x1000UL)
+#define USART6_BASE           (D2_APB2PERIPH_BASE + 0x1400UL)
+#define SPI1_BASE             (D2_APB2PERIPH_BASE + 0x3000UL)
+#define SPI4_BASE             (D2_APB2PERIPH_BASE + 0x3400UL)
+#define TIM15_BASE            (D2_APB2PERIPH_BASE + 0x4000UL)
+#define TIM16_BASE            (D2_APB2PERIPH_BASE + 0x4400UL)
+#define TIM17_BASE            (D2_APB2PERIPH_BASE + 0x4800UL)
+#define SPI5_BASE             (D2_APB2PERIPH_BASE + 0x5000UL)
+#define SAI1_BASE             (D2_APB2PERIPH_BASE + 0x5800UL)
+#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004UL)
+#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024UL)
+#define SAI2_BASE             (D2_APB2PERIPH_BASE + 0x5C00UL)
+#define SAI2_Block_A_BASE     (SAI2_BASE + 0x004UL)
+#define SAI2_Block_B_BASE     (SAI2_BASE + 0x024UL)
+#define SAI3_BASE             (D2_APB2PERIPH_BASE + 0x6000UL)
+#define SAI3_Block_A_BASE     (SAI3_BASE + 0x004UL)
+#define SAI3_Block_B_BASE     (SAI3_BASE + 0x024UL)
+#define DFSDM1_BASE           (D2_APB2PERIPH_BASE + 0x7000UL)
+#define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x00UL)
+#define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x20UL)
+#define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x40UL)
+#define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x60UL)
+#define DFSDM1_Channel4_BASE  (DFSDM1_BASE + 0x80UL)
+#define DFSDM1_Channel5_BASE  (DFSDM1_BASE + 0xA0UL)
+#define DFSDM1_Channel6_BASE  (DFSDM1_BASE + 0xC0UL)
+#define DFSDM1_Channel7_BASE  (DFSDM1_BASE + 0xE0UL)
+#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100UL)
+#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180UL)
+#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200UL)
+#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280UL)
+#define HRTIM1_BASE           (D2_APB2PERIPH_BASE + 0x7400UL)
+#define HRTIM1_TIMA_BASE      (HRTIM1_BASE + 0x00000080UL)
+#define HRTIM1_TIMB_BASE      (HRTIM1_BASE + 0x00000100UL)
+#define HRTIM1_TIMC_BASE      (HRTIM1_BASE + 0x00000180UL)
+#define HRTIM1_TIMD_BASE      (HRTIM1_BASE + 0x00000200UL)
+#define HRTIM1_TIME_BASE      (HRTIM1_BASE + 0x00000280UL)
+#define HRTIM1_COMMON_BASE    (HRTIM1_BASE + 0x00000380UL)
+
+
+/*!< D3_APB1PERIPH peripherals */
+#define EXTI_BASE             (D3_APB1PERIPH_BASE + 0x0000UL)
+#define EXTI_D1_BASE          (EXTI_BASE + 0x0080UL)
+#define EXTI_D2_BASE          (EXTI_BASE + 0x00C0UL)
+#define SYSCFG_BASE           (D3_APB1PERIPH_BASE + 0x0400UL)
+#define LPUART1_BASE          (D3_APB1PERIPH_BASE + 0x0C00UL)
+#define SPI6_BASE             (D3_APB1PERIPH_BASE + 0x1400UL)
+#define I2C4_BASE             (D3_APB1PERIPH_BASE + 0x1C00UL)
+#define LPTIM2_BASE           (D3_APB1PERIPH_BASE + 0x2400UL)
+#define LPTIM3_BASE           (D3_APB1PERIPH_BASE + 0x2800UL)
+#define LPTIM4_BASE           (D3_APB1PERIPH_BASE + 0x2C00UL)
+#define LPTIM5_BASE           (D3_APB1PERIPH_BASE + 0x3000UL)
+#define COMP12_BASE           (D3_APB1PERIPH_BASE + 0x3800UL)
+#define COMP1_BASE            (COMP12_BASE + 0x0CUL)
+#define COMP2_BASE            (COMP12_BASE + 0x10UL)
+#define VREFBUF_BASE          (D3_APB1PERIPH_BASE + 0x3C00UL)
+#define RTC_BASE              (D3_APB1PERIPH_BASE + 0x4000UL)
+#define IWDG1_BASE            (D3_APB1PERIPH_BASE + 0x4800UL)
+
+
+#define SAI4_BASE             (D3_APB1PERIPH_BASE + 0x5400UL)
+#define SAI4_Block_A_BASE     (SAI4_BASE + 0x004UL)
+#define SAI4_Block_B_BASE     (SAI4_BASE + 0x024UL)
+
+
+
+
+#define BDMA_Channel0_BASE    (BDMA_BASE + 0x0008UL)
+#define BDMA_Channel1_BASE    (BDMA_BASE + 0x001CUL)
+#define BDMA_Channel2_BASE    (BDMA_BASE + 0x0030UL)
+#define BDMA_Channel3_BASE    (BDMA_BASE + 0x0044UL)
+#define BDMA_Channel4_BASE    (BDMA_BASE + 0x0058UL)
+#define BDMA_Channel5_BASE    (BDMA_BASE + 0x006CUL)
+#define BDMA_Channel6_BASE    (BDMA_BASE + 0x0080UL)
+#define BDMA_Channel7_BASE    (BDMA_BASE + 0x0094UL)
+
+#define DMAMUX2_Channel0_BASE    (DMAMUX2_BASE)
+#define DMAMUX2_Channel1_BASE    (DMAMUX2_BASE + 0x0004UL)
+#define DMAMUX2_Channel2_BASE    (DMAMUX2_BASE + 0x0008UL)
+#define DMAMUX2_Channel3_BASE    (DMAMUX2_BASE + 0x000CUL)
+#define DMAMUX2_Channel4_BASE    (DMAMUX2_BASE + 0x0010UL)
+#define DMAMUX2_Channel5_BASE    (DMAMUX2_BASE + 0x0014UL)
+#define DMAMUX2_Channel6_BASE    (DMAMUX2_BASE + 0x0018UL)
+#define DMAMUX2_Channel7_BASE    (DMAMUX2_BASE + 0x001CUL)
+
+#define DMAMUX2_RequestGenerator0_BASE  (DMAMUX2_BASE + 0x0100UL)
+#define DMAMUX2_RequestGenerator1_BASE  (DMAMUX2_BASE + 0x0104UL)
+#define DMAMUX2_RequestGenerator2_BASE  (DMAMUX2_BASE + 0x0108UL)
+#define DMAMUX2_RequestGenerator3_BASE  (DMAMUX2_BASE + 0x010CUL)
+#define DMAMUX2_RequestGenerator4_BASE  (DMAMUX2_BASE + 0x0110UL)
+#define DMAMUX2_RequestGenerator5_BASE  (DMAMUX2_BASE + 0x0114UL)
+#define DMAMUX2_RequestGenerator6_BASE  (DMAMUX2_BASE + 0x0118UL)
+#define DMAMUX2_RequestGenerator7_BASE  (DMAMUX2_BASE + 0x011CUL)
+
+#define DMAMUX2_ChannelStatus_BASE      (DMAMUX2_BASE + 0x0080UL)
+#define DMAMUX2_RequestGenStatus_BASE   (DMAMUX2_BASE + 0x0140UL)
+
+#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)
+#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)
+#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)
+#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)
+#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)
+#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)
+#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)
+#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)
+
+#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)
+#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)
+#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)
+#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)
+#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)
+#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)
+#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)
+#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)
+
+#define DMAMUX1_Channel0_BASE    (DMAMUX1_BASE)
+#define DMAMUX1_Channel1_BASE    (DMAMUX1_BASE + 0x0004UL)
+#define DMAMUX1_Channel2_BASE    (DMAMUX1_BASE + 0x0008UL)
+#define DMAMUX1_Channel3_BASE    (DMAMUX1_BASE + 0x000CUL)
+#define DMAMUX1_Channel4_BASE    (DMAMUX1_BASE + 0x0010UL)
+#define DMAMUX1_Channel5_BASE    (DMAMUX1_BASE + 0x0014UL)
+#define DMAMUX1_Channel6_BASE    (DMAMUX1_BASE + 0x0018UL)
+#define DMAMUX1_Channel7_BASE    (DMAMUX1_BASE + 0x001CUL)
+#define DMAMUX1_Channel8_BASE    (DMAMUX1_BASE + 0x0020UL)
+#define DMAMUX1_Channel9_BASE    (DMAMUX1_BASE + 0x0024UL)
+#define DMAMUX1_Channel10_BASE   (DMAMUX1_BASE + 0x0028UL)
+#define DMAMUX1_Channel11_BASE   (DMAMUX1_BASE + 0x002CUL)
+#define DMAMUX1_Channel12_BASE   (DMAMUX1_BASE + 0x0030UL)
+#define DMAMUX1_Channel13_BASE   (DMAMUX1_BASE + 0x0034UL)
+#define DMAMUX1_Channel14_BASE   (DMAMUX1_BASE + 0x0038UL)
+#define DMAMUX1_Channel15_BASE   (DMAMUX1_BASE + 0x003CUL)
+
+#define DMAMUX1_RequestGenerator0_BASE  (DMAMUX1_BASE + 0x0100UL)
+#define DMAMUX1_RequestGenerator1_BASE  (DMAMUX1_BASE + 0x0104UL)
+#define DMAMUX1_RequestGenerator2_BASE  (DMAMUX1_BASE + 0x0108UL)
+#define DMAMUX1_RequestGenerator3_BASE  (DMAMUX1_BASE + 0x010CUL)
+#define DMAMUX1_RequestGenerator4_BASE  (DMAMUX1_BASE + 0x0110UL)
+#define DMAMUX1_RequestGenerator5_BASE  (DMAMUX1_BASE + 0x0114UL)
+#define DMAMUX1_RequestGenerator6_BASE  (DMAMUX1_BASE + 0x0118UL)
+#define DMAMUX1_RequestGenerator7_BASE  (DMAMUX1_BASE + 0x011CUL)
+
+#define DMAMUX1_ChannelStatus_BASE      (DMAMUX1_BASE + 0x0080UL)
+#define DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x0140UL)
+
+/*!< FMC Banks registers base  address */
+#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000UL)
+#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104UL)
+#define FMC_Bank2_R_BASE      (FMC_R_BASE + 0x0060UL)
+#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080UL)
+#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140UL)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE           (0x5C001000UL)
+
+#define MDMA_Channel0_BASE    (MDMA_BASE + 0x00000040UL)
+#define MDMA_Channel1_BASE    (MDMA_BASE + 0x00000080UL)
+#define MDMA_Channel2_BASE    (MDMA_BASE + 0x000000C0UL)
+#define MDMA_Channel3_BASE    (MDMA_BASE + 0x00000100UL)
+#define MDMA_Channel4_BASE    (MDMA_BASE + 0x00000140UL)
+#define MDMA_Channel5_BASE    (MDMA_BASE + 0x00000180UL)
+#define MDMA_Channel6_BASE    (MDMA_BASE + 0x000001C0UL)
+#define MDMA_Channel7_BASE    (MDMA_BASE + 0x00000200UL)
+#define MDMA_Channel8_BASE    (MDMA_BASE + 0x00000240UL)
+#define MDMA_Channel9_BASE    (MDMA_BASE + 0x00000280UL)
+#define MDMA_Channel10_BASE   (MDMA_BASE + 0x000002C0UL)
+#define MDMA_Channel11_BASE   (MDMA_BASE + 0x00000300UL)
+#define MDMA_Channel12_BASE   (MDMA_BASE + 0x00000340UL)
+#define MDMA_Channel13_BASE   (MDMA_BASE + 0x00000380UL)
+#define MDMA_Channel14_BASE   (MDMA_BASE + 0x000003C0UL)
+#define MDMA_Channel15_BASE   (MDMA_BASE + 0x00000400UL)
+
+#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL)
+#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL)
+#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL)
+#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL)
+#define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL)
+
+#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL)
+#define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL)
+#define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL)
+#define RAMECC2_Monitor4_BASE (RAMECC2_BASE + 0x80UL)
+#define RAMECC2_Monitor5_BASE (RAMECC2_BASE + 0xA0UL)
+
+#define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL)
+#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_declaration
+  * @{
+  */
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
+#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
+#define VREFBUF             ((VREFBUF_TypeDef *) VREFBUF_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG1               ((WWDG_TypeDef *) WWDG1_BASE)
+
+
+#define IWDG1               ((IWDG_TypeDef *) IWDG1_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
+#define SPI4                ((SPI_TypeDef *) SPI4_BASE)
+#define SPI5                ((SPI_TypeDef *) SPI5_BASE)
+#define SPI6                ((SPI_TypeDef *) SPI6_BASE)
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define USART3              ((USART_TypeDef *) USART3_BASE)
+#define USART6              ((USART_TypeDef *) USART6_BASE)
+#define UART7               ((USART_TypeDef *) UART7_BASE)
+#define UART8               ((USART_TypeDef *) UART8_BASE)
+#define CRS                 ((CRS_TypeDef *) CRS_BASE)
+#define UART4               ((USART_TypeDef *) UART4_BASE)
+#define UART5               ((USART_TypeDef *) UART5_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
+#define I2C4                ((I2C_TypeDef *) I2C4_BASE)
+#define FDCAN1              ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
+#define FDCAN2              ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
+#define FDCAN_CCU           ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)
+#define CEC                 ((CEC_TypeDef *) CEC_BASE)
+#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+#define DAC1                ((DAC_TypeDef *) DAC1_BASE)
+#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
+#define SWPMI1              ((SWPMI_TypeDef *) SWPMI1_BASE)
+#define LPTIM2              ((LPTIM_TypeDef *) LPTIM2_BASE)
+#define LPTIM3              ((LPTIM_TypeDef *) LPTIM3_BASE)
+#define LPTIM4              ((LPTIM_TypeDef *) LPTIM4_BASE)
+#define LPTIM5              ((LPTIM_TypeDef *) LPTIM5_BASE)
+
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define COMP12              ((COMPOPT_TypeDef *) COMP12_BASE)
+#define COMP1               ((COMP_TypeDef *) COMP1_BASE)
+#define COMP2               ((COMP_TypeDef *) COMP2_BASE)
+#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP2_BASE)
+#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
+#define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)
+#define OPAMP2              ((OPAMP_TypeDef *) OPAMP2_BASE)
+
+
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define EXTI_D1             ((EXTI_Core_TypeDef *) EXTI_D1_BASE)
+#define EXTI_D2             ((EXTI_Core_TypeDef *) EXTI_D2_BASE)
+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17               ((TIM_TypeDef *) TIM17_BASE)
+#define HRTIM1              ((HRTIM_TypeDef *) HRTIM1_BASE)
+#define HRTIM1_TIMA         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE)
+#define HRTIM1_TIMB         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE)
+#define HRTIM1_TIMC         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE)
+#define HRTIM1_TIMD         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE)
+#define HRTIM1_TIME         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE)
+#define HRTIM1_COMMON       ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)
+#define SAI1                ((SAI_TypeDef *) SAI1_BASE)
+#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
+#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+#define SAI2                ((SAI_TypeDef *) SAI2_BASE)
+#define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
+#define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
+#define SAI3                ((SAI_TypeDef *) SAI3_BASE)
+#define SAI3_Block_A        ((SAI_Block_TypeDef *)SAI3_Block_A_BASE)
+#define SAI3_Block_B        ((SAI_Block_TypeDef *)SAI3_Block_B_BASE)
+#define SAI4                ((SAI_TypeDef *) SAI4_BASE)
+#define SAI4_Block_A        ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)
+#define SAI4_Block_B        ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)
+
+#define SPDIFRX             ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
+#define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
+#define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
+#define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
+#define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
+#define DFSDM1_Channel4     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
+#define DFSDM1_Channel5     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
+#define DFSDM1_Channel6     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
+#define DFSDM1_Channel7     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
+#define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
+#define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
+#define DFSDM1_Filter2      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
+#define DFSDM1_Filter3      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
+#define DMA2D               ((DMA2D_TypeDef *) DMA2D_BASE)
+#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
+#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)
+#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)
+
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
+#define ADC3_COMMON         ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)
+#define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
+
+#define RNG                 ((RNG_TypeDef *) RNG_BASE)
+#define SDMMC2              ((SDMMC_TypeDef *) SDMMC2_BASE)
+#define DLYB_SDMMC2         ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)
+
+#define BDMA                ((BDMA_TypeDef *) BDMA_BASE)
+#define BDMA_Channel0       ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)
+#define BDMA_Channel1       ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)
+#define BDMA_Channel2       ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)
+#define BDMA_Channel3       ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)
+#define BDMA_Channel4       ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)
+#define BDMA_Channel5       ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)
+#define BDMA_Channel6       ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)
+#define BDMA_Channel7       ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)
+
+#define RAMECC1              ((RAMECC_TypeDef *)RAMECC1_BASE)
+#define RAMECC1_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)
+#define RAMECC1_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)
+#define RAMECC1_Monitor3     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)
+#define RAMECC1_Monitor4     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)
+#define RAMECC1_Monitor5     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)
+
+#define RAMECC2              ((RAMECC_TypeDef *)RAMECC2_BASE)
+#define RAMECC2_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)
+#define RAMECC2_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)
+#define RAMECC2_Monitor3     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)
+#define RAMECC2_Monitor4     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor4_BASE)
+#define RAMECC2_Monitor5     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor5_BASE)
+
+#define RAMECC3              ((RAMECC_TypeDef *)RAMECC3_BASE)
+#define RAMECC3_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)
+#define RAMECC3_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)
+
+#define DMAMUX2                ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)
+#define DMAMUX2_Channel0       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)
+#define DMAMUX2_Channel1       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)
+#define DMAMUX2_Channel2       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)
+#define DMAMUX2_Channel3       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)
+#define DMAMUX2_Channel4       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)
+#define DMAMUX2_Channel5       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)
+#define DMAMUX2_Channel6       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)
+#define DMAMUX2_Channel7       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)
+
+
+#define DMAMUX2_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)
+#define DMAMUX2_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)
+#define DMAMUX2_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)
+#define DMAMUX2_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)
+#define DMAMUX2_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)
+#define DMAMUX2_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)
+#define DMAMUX2_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)
+#define DMAMUX2_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)
+
+#define DMAMUX2_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)
+#define DMAMUX2_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)
+
+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+
+
+#define DMAMUX1              ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
+#define DMAMUX1_Channel0     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
+#define DMAMUX1_Channel1     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
+#define DMAMUX1_Channel2     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
+#define DMAMUX1_Channel3     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
+#define DMAMUX1_Channel4     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
+#define DMAMUX1_Channel5     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
+#define DMAMUX1_Channel6     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
+#define DMAMUX1_Channel7     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
+#define DMAMUX1_Channel8     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
+#define DMAMUX1_Channel9     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
+#define DMAMUX1_Channel10    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
+#define DMAMUX1_Channel11    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
+#define DMAMUX1_Channel12    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
+#define DMAMUX1_Channel13    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
+#define DMAMUX1_Channel14    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
+#define DMAMUX1_Channel15    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
+
+#define DMAMUX1_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
+#define DMAMUX1_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
+#define DMAMUX1_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
+#define DMAMUX1_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
+#define DMAMUX1_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)
+#define DMAMUX1_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)
+#define DMAMUX1_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)
+#define DMAMUX1_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)
+
+#define DMAMUX1_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *)    DMAMUX1_ChannelStatus_BASE)
+#define DMAMUX1_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
+
+
+#define FMC_Bank1_R           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
+#define FMC_Bank1E_R          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
+#define FMC_Bank2_R           ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)
+#define FMC_Bank3_R           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
+#define FMC_Bank5_6_R         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
+
+
+#define QUADSPI               ((QUADSPI_TypeDef *) QSPI_R_BASE)
+#define DLYB_QUADSPI          ((DLYB_TypeDef *) DLYB_QSPI_BASE)
+#define SDMMC1                ((SDMMC_TypeDef *) SDMMC1_BASE)
+#define DLYB_SDMMC1           ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)
+
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define JPEG                ((JPEG_TypeDef *) JPGDEC_BASE)
+#define HSEM                ((HSEM_TypeDef *) HSEM_BASE)
+#define HSEM_COMMON         ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))
+
+#define LTDC                ((LTDC_TypeDef *)LTDC_BASE)
+#define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
+#define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
+
+#define MDIOS               ((MDIOS_TypeDef *) MDIOS_BASE)
+
+#define ETH                 ((ETH_TypeDef *)ETH_BASE)
+#define MDMA                ((MDMA_TypeDef *)MDMA_BASE)
+#define MDMA_Channel0       ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)
+#define MDMA_Channel1       ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)
+#define MDMA_Channel2       ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)
+#define MDMA_Channel3       ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)
+#define MDMA_Channel4       ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)
+#define MDMA_Channel5       ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)
+#define MDMA_Channel6       ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)
+#define MDMA_Channel7       ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)
+#define MDMA_Channel8       ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)
+#define MDMA_Channel9       ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)
+#define MDMA_Channel10      ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)
+#define MDMA_Channel11      ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)
+#define MDMA_Channel12      ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)
+#define MDMA_Channel13      ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)
+#define MDMA_Channel14      ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)
+#define MDMA_Channel15      ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)
+
+
+#define USB1_OTG_HS         ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)
+#define USB2_OTG_FS         ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE)
+
+/* Legacy defines */
+#define USB_OTG_HS                   USB1_OTG_HS
+#define USB_OTG_HS_PERIPH_BASE       USB1_OTG_HS_PERIPH_BASE
+#define USB_OTG_FS                   USB2_OTG_FS
+#define USB_OTG_FS_PERIPH_BASE       USB2_OTG_FS_PERIPH_BASE
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+
+  /** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+
+/******************************************************************************/
+/*                         Peripheral Registers_Bits_Definition               */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Analog to Digital Converter                         */
+/*                                                                            */
+/******************************************************************************/
+/*******************************  ADC VERSION  ********************************/
+#define ADC_VER_V5_X
+/********************  Bit definition for ADC_ISR register  ********************/
+#define ADC_ISR_ADRDY_Pos                 (0U)
+#define ADC_ISR_ADRDY_Msk                 (0x1UL << ADC_ISR_ADRDY_Pos)         /*!< 0x00000001 */
+#define ADC_ISR_ADRDY                     ADC_ISR_ADRDY_Msk                    /*!< ADC Ready (ADRDY) flag  */
+#define ADC_ISR_EOSMP_Pos                 (1U)
+#define ADC_ISR_EOSMP_Msk                 (0x1UL << ADC_ISR_EOSMP_Pos)         /*!< 0x00000002 */
+#define ADC_ISR_EOSMP                     ADC_ISR_EOSMP_Msk                    /*!< ADC End of Sampling flag */
+#define ADC_ISR_EOC_Pos                   (2U)
+#define ADC_ISR_EOC_Msk                   (0x1UL << ADC_ISR_EOC_Pos)           /*!< 0x00000004 */
+#define ADC_ISR_EOC                       ADC_ISR_EOC_Msk                      /*!< ADC End of Regular Conversion flag */
+#define ADC_ISR_EOS_Pos                   (3U)
+#define ADC_ISR_EOS_Msk                   (0x1UL << ADC_ISR_EOS_Pos)           /*!< 0x00000008 */
+#define ADC_ISR_EOS                       ADC_ISR_EOS_Msk                      /*!< ADC End of Regular sequence of Conversions flag */
+#define ADC_ISR_OVR_Pos                   (4U)
+#define ADC_ISR_OVR_Msk                   (0x1UL << ADC_ISR_OVR_Pos)           /*!< 0x00000010 */
+#define ADC_ISR_OVR                       ADC_ISR_OVR_Msk                      /*!< ADC overrun flag */
+#define ADC_ISR_JEOC_Pos                  (5U)
+#define ADC_ISR_JEOC_Msk                  (0x1UL << ADC_ISR_JEOC_Pos)          /*!< 0x00000020 */
+#define ADC_ISR_JEOC                      ADC_ISR_JEOC_Msk                     /*!< ADC End of Injected Conversion flag */
+#define ADC_ISR_JEOS_Pos                  (6U)
+#define ADC_ISR_JEOS_Msk                  (0x1UL << ADC_ISR_JEOS_Pos)          /*!< 0x00000040 */
+#define ADC_ISR_JEOS                      ADC_ISR_JEOS_Msk                     /*!< ADC End of Injected sequence of Conversions flag */
+#define ADC_ISR_AWD1_Pos                  (7U)
+#define ADC_ISR_AWD1_Msk                  (0x1UL << ADC_ISR_AWD1_Pos)          /*!< 0x00000080 */
+#define ADC_ISR_AWD1                      ADC_ISR_AWD1_Msk                     /*!< ADC Analog watchdog 1 flag */
+#define ADC_ISR_AWD2_Pos                  (8U)
+#define ADC_ISR_AWD2_Msk                  (0x1UL << ADC_ISR_AWD2_Pos)          /*!< 0x00000100 */
+#define ADC_ISR_AWD2                      ADC_ISR_AWD2_Msk                     /*!< ADC Analog watchdog 2 flag */
+#define ADC_ISR_AWD3_Pos                  (9U)
+#define ADC_ISR_AWD3_Msk                  (0x1UL << ADC_ISR_AWD3_Pos)          /*!< 0x00000200 */
+#define ADC_ISR_AWD3                      ADC_ISR_AWD3_Msk                     /*!< ADC Analog watchdog 3 flag */
+#define ADC_ISR_JQOVF_Pos                 (10U)
+#define ADC_ISR_JQOVF_Msk                 (0x1UL << ADC_ISR_JQOVF_Pos)         /*!< 0x00000400 */
+#define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                    /*!< ADC Injected Context Queue Overflow flag */
+
+/********************  Bit definition for ADC_IER register  ********************/
+#define ADC_IER_ADRDYIE_Pos               (0U)
+#define ADC_IER_ADRDYIE_Msk               (0x1UL << ADC_IER_ADRDYIE_Pos)       /*!< 0x00000001 */
+#define ADC_IER_ADRDYIE                   ADC_IER_ADRDYIE_Msk                  /*!< ADC Ready (ADRDY) interrupt source */
+#define ADC_IER_EOSMPIE_Pos               (1U)
+#define ADC_IER_EOSMPIE_Msk               (0x1UL << ADC_IER_EOSMPIE_Pos)       /*!< 0x00000002 */
+#define ADC_IER_EOSMPIE                   ADC_IER_EOSMPIE_Msk                  /*!< ADC End of Sampling interrupt source */
+#define ADC_IER_EOCIE_Pos                 (2U)
+#define ADC_IER_EOCIE_Msk                 (0x1UL << ADC_IER_EOCIE_Pos)         /*!< 0x00000004 */
+#define ADC_IER_EOCIE                     ADC_IER_EOCIE_Msk                    /*!< ADC End of Regular Conversion interrupt source */
+#define ADC_IER_EOSIE_Pos                 (3U)
+#define ADC_IER_EOSIE_Msk                 (0x1UL << ADC_IER_EOSIE_Pos)         /*!< 0x00000008 */
+#define ADC_IER_EOSIE                     ADC_IER_EOSIE_Msk                    /*!< ADC End of Regular sequence of Conversions interrupt source */
+#define ADC_IER_OVRIE_Pos                 (4U)
+#define ADC_IER_OVRIE_Msk                 (0x1UL << ADC_IER_OVRIE_Pos)         /*!< 0x00000010 */
+#define ADC_IER_OVRIE                     ADC_IER_OVRIE_Msk                    /*!< ADC overrun interrupt source */
+#define ADC_IER_JEOCIE_Pos                (5U)
+#define ADC_IER_JEOCIE_Msk                (0x1UL << ADC_IER_JEOCIE_Pos)        /*!< 0x00000020 */
+#define ADC_IER_JEOCIE                    ADC_IER_JEOCIE_Msk                   /*!< ADC End of Injected Conversion interrupt source */
+#define ADC_IER_JEOSIE_Pos                (6U)
+#define ADC_IER_JEOSIE_Msk                (0x1UL << ADC_IER_JEOSIE_Pos)        /*!< 0x00000040 */
+#define ADC_IER_JEOSIE                    ADC_IER_JEOSIE_Msk                   /*!< ADC End of Injected sequence of Conversions interrupt source */
+#define ADC_IER_AWD1IE_Pos                (7U)
+#define ADC_IER_AWD1IE_Msk                (0x1UL << ADC_IER_AWD1IE_Pos)        /*!< 0x00000080 */
+#define ADC_IER_AWD1IE                    ADC_IER_AWD1IE_Msk                   /*!< ADC Analog watchdog 1 interrupt source */
+#define ADC_IER_AWD2IE_Pos                (8U)
+#define ADC_IER_AWD2IE_Msk                (0x1UL << ADC_IER_AWD2IE_Pos)        /*!< 0x00000100 */
+#define ADC_IER_AWD2IE                    ADC_IER_AWD2IE_Msk                   /*!< ADC Analog watchdog 2 interrupt source */
+#define ADC_IER_AWD3IE_Pos                (9U)
+#define ADC_IER_AWD3IE_Msk                (0x1UL << ADC_IER_AWD3IE_Pos)        /*!< 0x00000200 */
+#define ADC_IER_AWD3IE                    ADC_IER_AWD3IE_Msk                   /*!< ADC Analog watchdog 3 interrupt source */
+#define ADC_IER_JQOVFIE_Pos               (10U)
+#define ADC_IER_JQOVFIE_Msk               (0x1UL << ADC_IER_JQOVFIE_Pos)       /*!< 0x00000400 */
+#define ADC_IER_JQOVFIE                   ADC_IER_JQOVFIE_Msk                  /*!< ADC Injected Context Queue Overflow interrupt source */
+
+/********************  Bit definition for ADC_CR register  ********************/
+#define ADC_CR_ADEN_Pos                   (0U)
+#define ADC_CR_ADEN_Msk                   (0x1UL << ADC_CR_ADEN_Pos)           /*!< 0x00000001 */
+#define ADC_CR_ADEN                       ADC_CR_ADEN_Msk                      /*!< ADC Enable control */
+#define ADC_CR_ADDIS_Pos                  (1U)
+#define ADC_CR_ADDIS_Msk                  (0x1UL << ADC_CR_ADDIS_Pos)          /*!< 0x00000002 */
+#define ADC_CR_ADDIS                      ADC_CR_ADDIS_Msk                     /*!< ADC Disable command */
+#define ADC_CR_ADSTART_Pos                (2U)
+#define ADC_CR_ADSTART_Msk                (0x1UL << ADC_CR_ADSTART_Pos)        /*!< 0x00000004 */
+#define ADC_CR_ADSTART                    ADC_CR_ADSTART_Msk                   /*!< ADC Start of Regular conversion */
+#define ADC_CR_JADSTART_Pos               (3U)
+#define ADC_CR_JADSTART_Msk               (0x1UL << ADC_CR_JADSTART_Pos)       /*!< 0x00000008 */
+#define ADC_CR_JADSTART                   ADC_CR_JADSTART_Msk                  /*!< ADC Start of injected conversion */
+#define ADC_CR_ADSTP_Pos                  (4U)
+#define ADC_CR_ADSTP_Msk                  (0x1UL << ADC_CR_ADSTP_Pos)          /*!< 0x00000010 */
+#define ADC_CR_ADSTP                      ADC_CR_ADSTP_Msk                     /*!< ADC Stop of Regular conversion */
+#define ADC_CR_JADSTP_Pos                 (5U)
+#define ADC_CR_JADSTP_Msk                 (0x1UL << ADC_CR_JADSTP_Pos)         /*!< 0x00000020 */
+#define ADC_CR_JADSTP                     ADC_CR_JADSTP_Msk                    /*!< ADC Stop of injected conversion */
+#define ADC_CR_BOOST_Pos                  (8U)
+#define ADC_CR_BOOST_Msk                  (0x3UL << ADC_CR_BOOST_Pos)          /*!< 0x00000300 */
+#define ADC_CR_BOOST                      ADC_CR_BOOST_Msk                     /*!< ADC Boost Mode configuration */
+#define ADC_CR_BOOST_0                    (0x1UL << ADC_CR_BOOST_Pos)           /*!< 0x00000100 */
+#define ADC_CR_BOOST_1                    (0x2UL << ADC_CR_BOOST_Pos)           /*!< 0x00000200 */
+#define ADC_CR_ADCALLIN_Pos               (16U)
+#define ADC_CR_ADCALLIN_Msk               (0x1UL << ADC_CR_ADCALLIN_Pos)       /*!< 0x00010000 */
+#define ADC_CR_ADCALLIN                   ADC_CR_ADCALLIN_Msk                  /*!< ADC Linearity calibration */
+#define ADC_CR_LINCALRDYW1_Pos            (22U)
+#define ADC_CR_LINCALRDYW1_Msk            (0x1UL << ADC_CR_LINCALRDYW1_Pos)    /*!< 0x00400000 */
+#define ADC_CR_LINCALRDYW1                ADC_CR_LINCALRDYW1_Msk               /*!< ADC Linearity calibration ready Word 1 */
+#define ADC_CR_LINCALRDYW2_Pos            (23U)
+#define ADC_CR_LINCALRDYW2_Msk            (0x1UL << ADC_CR_LINCALRDYW2_Pos)    /*!< 0x00800000 */
+#define ADC_CR_LINCALRDYW2                ADC_CR_LINCALRDYW2_Msk               /*!< ADC Linearity calibration ready Word 2 */
+#define ADC_CR_LINCALRDYW3_Pos            (24U)
+#define ADC_CR_LINCALRDYW3_Msk            (0x1UL << ADC_CR_LINCALRDYW3_Pos)    /*!< 0x01000000 */
+#define ADC_CR_LINCALRDYW3                ADC_CR_LINCALRDYW3_Msk               /*!< ADC Linearity calibration ready Word 3 */
+#define ADC_CR_LINCALRDYW4_Pos            (25U)
+#define ADC_CR_LINCALRDYW4_Msk            (0x1UL << ADC_CR_LINCALRDYW4_Pos)    /*!< 0x02000000 */
+#define ADC_CR_LINCALRDYW4                ADC_CR_LINCALRDYW4_Msk               /*!< ADC Linearity calibration ready Word 4 */
+#define ADC_CR_LINCALRDYW5_Pos            (26U)
+#define ADC_CR_LINCALRDYW5_Msk            (0x1UL << ADC_CR_LINCALRDYW5_Pos)    /*!< 0x04000000 */
+#define ADC_CR_LINCALRDYW5                ADC_CR_LINCALRDYW5_Msk               /*!< ADC Linearity calibration ready Word 5 */
+#define ADC_CR_LINCALRDYW6_Pos            (27U)
+#define ADC_CR_LINCALRDYW6_Msk            (0x1UL << ADC_CR_LINCALRDYW6_Pos)    /*!< 0x08000000 */
+#define ADC_CR_LINCALRDYW6                ADC_CR_LINCALRDYW6_Msk               /*!< ADC Linearity calibration ready Word 6 */
+#define ADC_CR_ADVREGEN_Pos               (28U)
+#define ADC_CR_ADVREGEN_Msk               (0x1UL << ADC_CR_ADVREGEN_Pos)       /*!< 0x10000000 */
+#define ADC_CR_ADVREGEN                   ADC_CR_ADVREGEN_Msk                  /*!< ADC Voltage regulator Enable */
+#define ADC_CR_DEEPPWD_Pos                (29U)
+#define ADC_CR_DEEPPWD_Msk                (0x1UL << ADC_CR_DEEPPWD_Pos)        /*!< 0x20000000 */
+#define ADC_CR_DEEPPWD                    ADC_CR_DEEPPWD_Msk                   /*!< ADC Deep power down Enable */
+#define ADC_CR_ADCALDIF_Pos               (30U)
+#define ADC_CR_ADCALDIF_Msk               (0x1UL << ADC_CR_ADCALDIF_Pos)       /*!< 0x40000000 */
+#define ADC_CR_ADCALDIF                   ADC_CR_ADCALDIF_Msk                  /*!< ADC Differential Mode for calibration */
+#define ADC_CR_ADCAL_Pos                  (31U)
+#define ADC_CR_ADCAL_Msk                  (0x1UL << ADC_CR_ADCAL_Pos)          /*!< 0x80000000 */
+#define ADC_CR_ADCAL                      ADC_CR_ADCAL_Msk                     /*!< ADC Calibration */
+
+/********************  Bit definition for ADC_CFGR register  ********************/
+#define ADC_CFGR_DMNGT_Pos                (0U)
+#define ADC_CFGR_DMNGT_Msk                (0x3UL << ADC_CFGR_DMNGT_Pos)        /*!< 0x00000003 */
+#define ADC_CFGR_DMNGT                    ADC_CFGR_DMNGT_Msk                   /*!< ADC Data Management configuration */
+#define ADC_CFGR_DMNGT_0                  (0x1UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000001 */
+#define ADC_CFGR_DMNGT_1                  (0x2UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000002 */
+
+#define ADC_CFGR_RES_Pos                  (2U)
+#define ADC_CFGR_RES_Msk                  (0x7UL << ADC_CFGR_RES_Pos)          /*!< 0x0000001C */
+#define ADC_CFGR_RES                      ADC_CFGR_RES_Msk                     /*!< ADC Data resolution */
+#define ADC_CFGR_RES_0                    (0x1UL << ADC_CFGR_RES_Pos)           /*!< 0x00000004 */
+#define ADC_CFGR_RES_1                    (0x2UL << ADC_CFGR_RES_Pos)           /*!< 0x00000008 */
+#define ADC_CFGR_RES_2                    (0x4UL << ADC_CFGR_RES_Pos)           /*!< 0x00000010 */
+
+#define ADC_CFGR_EXTSEL_Pos               (5U)
+#define ADC_CFGR_EXTSEL_Msk               (0x1FUL << ADC_CFGR_EXTSEL_Pos)      /*!< 0x000003E0 */
+#define ADC_CFGR_EXTSEL                   ADC_CFGR_EXTSEL_Msk                  /*!< ADC External trigger selection for regular group */
+#define ADC_CFGR_EXTSEL_0                 (0x01UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000020 */
+#define ADC_CFGR_EXTSEL_1                 (0x02UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000040 */
+#define ADC_CFGR_EXTSEL_2                 (0x04UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000080 */
+#define ADC_CFGR_EXTSEL_3                 (0x08UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000100 */
+#define ADC_CFGR_EXTSEL_4                 (0x10UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000200 */
+
+#define ADC_CFGR_EXTEN_Pos                (10U)
+#define ADC_CFGR_EXTEN_Msk                (0x3UL << ADC_CFGR_EXTEN_Pos)        /*!< 0x00000C00 */
+#define ADC_CFGR_EXTEN                    ADC_CFGR_EXTEN_Msk                   /*!< ADC External trigger enable and polarity selection for regular channels */
+#define ADC_CFGR_EXTEN_0                  (0x1UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000400 */
+#define ADC_CFGR_EXTEN_1                  (0x2UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000800 */
+
+#define ADC_CFGR_OVRMOD_Pos               (12U)
+#define ADC_CFGR_OVRMOD_Msk               (0x1UL << ADC_CFGR_OVRMOD_Pos)       /*!< 0x00001000 */
+#define ADC_CFGR_OVRMOD                   ADC_CFGR_OVRMOD_Msk                  /*!< ADC overrun mode */
+#define ADC_CFGR_CONT_Pos                 (13U)
+#define ADC_CFGR_CONT_Msk                 (0x1UL << ADC_CFGR_CONT_Pos)         /*!< 0x00002000 */
+#define ADC_CFGR_CONT                     ADC_CFGR_CONT_Msk                    /*!< ADC Single/continuous conversion mode for regular conversion */
+#define ADC_CFGR_AUTDLY_Pos               (14U)
+#define ADC_CFGR_AUTDLY_Msk               (0x1UL << ADC_CFGR_AUTDLY_Pos)       /*!< 0x00004000 */
+#define ADC_CFGR_AUTDLY                   ADC_CFGR_AUTDLY_Msk                  /*!< ADC Delayed conversion mode */
+
+#define ADC_CFGR_DISCEN_Pos               (16U)
+#define ADC_CFGR_DISCEN_Msk               (0x1UL << ADC_CFGR_DISCEN_Pos)       /*!< 0x00010000 */
+#define ADC_CFGR_DISCEN                   ADC_CFGR_DISCEN_Msk                  /*!< ADC Discontinuous mode for regular channels */
+
+#define ADC_CFGR_DISCNUM_Pos              (17U)
+#define ADC_CFGR_DISCNUM_Msk              (0x7UL << ADC_CFGR_DISCNUM_Pos)      /*!< 0x000E0000 */
+#define ADC_CFGR_DISCNUM                  ADC_CFGR_DISCNUM_Msk                 /*!< ADC Discontinuous mode channel count */
+#define ADC_CFGR_DISCNUM_0                (0x1UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00020000 */
+#define ADC_CFGR_DISCNUM_1                (0x2UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00040000 */
+#define ADC_CFGR_DISCNUM_2                (0x4UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00080000 */
+
+#define ADC_CFGR_JDISCEN_Pos              (20U)
+#define ADC_CFGR_JDISCEN_Msk              (0x1UL << ADC_CFGR_JDISCEN_Pos)      /*!< 0x00100000 */
+#define ADC_CFGR_JDISCEN                  ADC_CFGR_JDISCEN_Msk                 /*!< ADC Discontinuous mode on injected channels */
+#define ADC_CFGR_JQM_Pos                  (21U)
+#define ADC_CFGR_JQM_Msk                  (0x1UL << ADC_CFGR_JQM_Pos)          /*!< 0x00200000 */
+#define ADC_CFGR_JQM                      ADC_CFGR_JQM_Msk                     /*!< ADC JSQR Queue mode */
+#define ADC_CFGR_AWD1SGL_Pos              (22U)
+#define ADC_CFGR_AWD1SGL_Msk              (0x1UL << ADC_CFGR_AWD1SGL_Pos)      /*!< 0x00400000 */
+#define ADC_CFGR_AWD1SGL                  ADC_CFGR_AWD1SGL_Msk                 /*!< Enable the watchdog 1 on a single channel or on all channels */
+#define ADC_CFGR_AWD1EN_Pos               (23U)
+#define ADC_CFGR_AWD1EN_Msk               (0x1UL << ADC_CFGR_AWD1EN_Pos)       /*!< 0x00800000 */
+#define ADC_CFGR_AWD1EN                   ADC_CFGR_AWD1EN_Msk                  /*!< ADC Analog watchdog 1 enable on regular Channels */
+#define ADC_CFGR_JAWD1EN_Pos              (24U)
+#define ADC_CFGR_JAWD1EN_Msk              (0x1UL << ADC_CFGR_JAWD1EN_Pos)      /*!< 0x01000000 */
+#define ADC_CFGR_JAWD1EN                  ADC_CFGR_JAWD1EN_Msk                 /*!< ADC Analog watchdog 1 enable on injected Channels */
+#define ADC_CFGR_JAUTO_Pos                (25U)
+#define ADC_CFGR_JAUTO_Msk                (0x1UL << ADC_CFGR_JAUTO_Pos)        /*!< 0x02000000 */
+#define ADC_CFGR_JAUTO                    ADC_CFGR_JAUTO_Msk                   /*!< ADC Automatic injected group conversion */
+
+#define ADC_CFGR_AWD1CH_Pos               (26U)
+#define ADC_CFGR_AWD1CH_Msk               (0x1FUL << ADC_CFGR_AWD1CH_Pos)      /*!< 0x7C000000 */
+#define ADC_CFGR_AWD1CH                   ADC_CFGR_AWD1CH_Msk                  /*!< ADC Analog watchdog 1 Channel selection */
+#define ADC_CFGR_AWD1CH_0                 (0x01UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x04000000 */
+#define ADC_CFGR_AWD1CH_1                 (0x02UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x08000000 */
+#define ADC_CFGR_AWD1CH_2                 (0x04UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x10000000 */
+#define ADC_CFGR_AWD1CH_3                 (0x08UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x20000000 */
+#define ADC_CFGR_AWD1CH_4                 (0x10UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x40000000 */
+
+#define ADC_CFGR_JQDIS_Pos                (31U)
+#define ADC_CFGR_JQDIS_Msk                (0x1UL << ADC_CFGR_JQDIS_Pos)        /*!< 0x80000000 */
+#define ADC_CFGR_JQDIS                    ADC_CFGR_JQDIS_Msk                   /*!< ADC Injected queue disable */
+
+/********************  Bit definition for ADC_CFGR2 register  ********************/
+#define ADC_CFGR2_ROVSE_Pos               (0U)
+#define ADC_CFGR2_ROVSE_Msk               (0x1UL << ADC_CFGR2_ROVSE_Pos)       /*!< 0x00000001 */
+#define ADC_CFGR2_ROVSE                   ADC_CFGR2_ROVSE_Msk                  /*!< ADC Regular group oversampler enable */
+#define ADC_CFGR2_JOVSE_Pos               (1U)
+#define ADC_CFGR2_JOVSE_Msk               (0x1UL << ADC_CFGR2_JOVSE_Pos)       /*!< 0x00000002 */
+#define ADC_CFGR2_JOVSE                   ADC_CFGR2_JOVSE_Msk                  /*!< ADC Injected group oversampler enable */
+
+#define ADC_CFGR2_OVSS_Pos                (5U)
+#define ADC_CFGR2_OVSS_Msk                (0xFUL << ADC_CFGR2_OVSS_Pos)        /*!< 0x000001E0 */
+#define ADC_CFGR2_OVSS                    ADC_CFGR2_OVSS_Msk                   /*!< ADC Regular Oversampling shift */
+#define ADC_CFGR2_OVSS_0                  (0x1UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000020 */
+#define ADC_CFGR2_OVSS_1                  (0x2UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000040 */
+#define ADC_CFGR2_OVSS_2                  (0x4UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000080 */
+#define ADC_CFGR2_OVSS_3                  (0x8UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000100 */
+
+#define ADC_CFGR2_TROVS_Pos               (9U)
+#define ADC_CFGR2_TROVS_Msk               (0x1UL << ADC_CFGR2_TROVS_Pos)       /*!< 0x00000200 */
+#define ADC_CFGR2_TROVS                   ADC_CFGR2_TROVS_Msk                  /*!< ADC Triggered regular Oversampling */
+#define ADC_CFGR2_ROVSM_Pos               (10U)
+#define ADC_CFGR2_ROVSM_Msk               (0x1UL << ADC_CFGR2_ROVSM_Pos)       /*!< 0x00000400 */
+#define ADC_CFGR2_ROVSM                   ADC_CFGR2_ROVSM_Msk                  /*!< ADC Regular oversampling mode */
+
+#define ADC_CFGR2_RSHIFT1_Pos             (11U)
+#define ADC_CFGR2_RSHIFT1_Msk             (0x1UL << ADC_CFGR2_RSHIFT1_Pos)     /*!< 0x00000800 */
+#define ADC_CFGR2_RSHIFT1                 ADC_CFGR2_RSHIFT1_Msk                /*!< ADC Right-shift data after Offset 1 correction */
+#define ADC_CFGR2_RSHIFT2_Pos             (12U)
+#define ADC_CFGR2_RSHIFT2_Msk             (0x1UL << ADC_CFGR2_RSHIFT2_Pos)     /*!< 0x00001000 */
+#define ADC_CFGR2_RSHIFT2                 ADC_CFGR2_RSHIFT2_Msk                /*!< ADC Right-shift data after Offset 2 correction */
+#define ADC_CFGR2_RSHIFT3_Pos             (13U)
+#define ADC_CFGR2_RSHIFT3_Msk             (0x1UL << ADC_CFGR2_RSHIFT3_Pos)     /*!< 0x00002000 */
+#define ADC_CFGR2_RSHIFT3                 ADC_CFGR2_RSHIFT3_Msk                /*!< ADC Right-shift data after Offset 3 correction */
+#define ADC_CFGR2_RSHIFT4_Pos             (14U)
+#define ADC_CFGR2_RSHIFT4_Msk             (0x1UL << ADC_CFGR2_RSHIFT4_Pos)     /*!< 0x00004000 */
+#define ADC_CFGR2_RSHIFT4                 ADC_CFGR2_RSHIFT4_Msk                /*!< ADC Right-shift data after Offset 4 correction */
+
+#define ADC_CFGR2_OVSR_Pos                (16U)
+#define ADC_CFGR2_OVSR_Msk                (0x3FFUL << ADC_CFGR2_OVSR_Pos)      /*!< 0x03FF0000 */
+#define ADC_CFGR2_OVSR                    ADC_CFGR2_OVSR_Msk                   /*!< ADC oversampling Ratio */
+#define ADC_CFGR2_OVSR_0                  (0x001UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00010000 */
+#define ADC_CFGR2_OVSR_1                  (0x002UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00020000 */
+#define ADC_CFGR2_OVSR_2                  (0x004UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00040000 */
+#define ADC_CFGR2_OVSR_3                  (0x008UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00080000 */
+#define ADC_CFGR2_OVSR_4                  (0x010UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00100000 */
+#define ADC_CFGR2_OVSR_5                  (0x020UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00200000 */
+#define ADC_CFGR2_OVSR_6                  (0x040UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00400000 */
+#define ADC_CFGR2_OVSR_7                  (0x080UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00800000 */
+#define ADC_CFGR2_OVSR_8                  (0x100UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x01000000 */
+#define ADC_CFGR2_OVSR_9                  (0x200UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x02000000 */
+
+#define ADC_CFGR2_LSHIFT_Pos              (28U)
+#define ADC_CFGR2_LSHIFT_Msk              (0xFUL << ADC_CFGR2_LSHIFT_Pos)      /*!< 0xF0000000 */
+#define ADC_CFGR2_LSHIFT                  ADC_CFGR2_LSHIFT_Msk                 /*!< ADC Left shift factor */
+#define ADC_CFGR2_LSHIFT_0                (0x1UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x10000000 */
+#define ADC_CFGR2_LSHIFT_1                (0x2UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x20000000 */
+#define ADC_CFGR2_LSHIFT_2                (0x4UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x40000000 */
+#define ADC_CFGR2_LSHIFT_3                (0x8UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_SMPR1 register  ********************/
+#define ADC_SMPR1_SMP0_Pos                (0U)
+#define ADC_SMPR1_SMP0_Msk                (0x7UL << ADC_SMPR1_SMP0_Pos)        /*!< 0x00000007 */
+#define ADC_SMPR1_SMP0                    ADC_SMPR1_SMP0_Msk                   /*!< ADC Channel 0 Sampling time selection  */
+#define ADC_SMPR1_SMP0_0                  (0x1UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000001 */
+#define ADC_SMPR1_SMP0_1                  (0x2UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000002 */
+#define ADC_SMPR1_SMP0_2                  (0x4UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000004 */
+
+#define ADC_SMPR1_SMP1_Pos                (3U)
+#define ADC_SMPR1_SMP1_Msk                (0x7UL << ADC_SMPR1_SMP1_Pos)        /*!< 0x00000038 */
+#define ADC_SMPR1_SMP1                    ADC_SMPR1_SMP1_Msk                   /*!< ADC Channel 1 Sampling time selection  */
+#define ADC_SMPR1_SMP1_0                  (0x1UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000008 */
+#define ADC_SMPR1_SMP1_1                  (0x2UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000010 */
+#define ADC_SMPR1_SMP1_2                  (0x4UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000020 */
+
+#define ADC_SMPR1_SMP2_Pos                (6U)
+#define ADC_SMPR1_SMP2_Msk                (0x7UL << ADC_SMPR1_SMP2_Pos)        /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP2                    ADC_SMPR1_SMP2_Msk                   /*!< ADC Channel 2 Sampling time selection  */
+#define ADC_SMPR1_SMP2_0                  (0x1UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000040 */
+#define ADC_SMPR1_SMP2_1                  (0x2UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000080 */
+#define ADC_SMPR1_SMP2_2                  (0x4UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000100 */
+
+#define ADC_SMPR1_SMP3_Pos                (9U)
+#define ADC_SMPR1_SMP3_Msk                (0x7UL << ADC_SMPR1_SMP3_Pos)        /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP3                    ADC_SMPR1_SMP3_Msk                   /*!< ADC Channel 3 Sampling time selection  */
+#define ADC_SMPR1_SMP3_0                  (0x1UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000200 */
+#define ADC_SMPR1_SMP3_1                  (0x2UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000400 */
+#define ADC_SMPR1_SMP3_2                  (0x4UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000800 */
+
+#define ADC_SMPR1_SMP4_Pos                (12U)
+#define ADC_SMPR1_SMP4_Msk                (0x7UL << ADC_SMPR1_SMP4_Pos)        /*!< 0x00007000 */
+#define ADC_SMPR1_SMP4                    ADC_SMPR1_SMP4_Msk                   /*!< ADC Channel 4 Sampling time selection  */
+#define ADC_SMPR1_SMP4_0                  (0x1UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00001000 */
+#define ADC_SMPR1_SMP4_1                  (0x2UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00002000 */
+#define ADC_SMPR1_SMP4_2                  (0x4UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00004000 */
+
+#define ADC_SMPR1_SMP5_Pos                (15U)
+#define ADC_SMPR1_SMP5_Msk                (0x7UL << ADC_SMPR1_SMP5_Pos)        /*!< 0x00038000 */
+#define ADC_SMPR1_SMP5                    ADC_SMPR1_SMP5_Msk                   /*!< ADC Channel 5 Sampling time selection  */
+#define ADC_SMPR1_SMP5_0                  (0x1UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00008000 */
+#define ADC_SMPR1_SMP5_1                  (0x2UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00010000 */
+#define ADC_SMPR1_SMP5_2                  (0x4UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00020000 */
+
+#define ADC_SMPR1_SMP6_Pos                (18U)
+#define ADC_SMPR1_SMP6_Msk                (0x7UL << ADC_SMPR1_SMP6_Pos)        /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP6                    ADC_SMPR1_SMP6_Msk                   /*!< ADC Channel 6 Sampling time selection  */
+#define ADC_SMPR1_SMP6_0                  (0x1UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00040000 */
+#define ADC_SMPR1_SMP6_1                  (0x2UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00080000 */
+#define ADC_SMPR1_SMP6_2                  (0x4UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00100000 */
+
+#define ADC_SMPR1_SMP7_Pos                (21U)
+#define ADC_SMPR1_SMP7_Msk                (0x7UL << ADC_SMPR1_SMP7_Pos)        /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP7                    ADC_SMPR1_SMP7_Msk                   /*!< ADC Channel 7 Sampling time selection  */
+#define ADC_SMPR1_SMP7_0                  (0x1UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00200000 */
+#define ADC_SMPR1_SMP7_1                  (0x2UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00400000 */
+#define ADC_SMPR1_SMP7_2                  (0x4UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00800000 */
+
+#define ADC_SMPR1_SMP8_Pos                (24U)
+#define ADC_SMPR1_SMP8_Msk                (0x7UL << ADC_SMPR1_SMP8_Pos)        /*!< 0x07000000 */
+#define ADC_SMPR1_SMP8                    ADC_SMPR1_SMP8_Msk                   /*!< ADC Channel 8 Sampling time selection  */
+#define ADC_SMPR1_SMP8_0                  (0x1UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x01000000 */
+#define ADC_SMPR1_SMP8_1                  (0x2UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x02000000 */
+#define ADC_SMPR1_SMP8_2                  (0x4UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x04000000 */
+
+#define ADC_SMPR1_SMP9_Pos                (27U)
+#define ADC_SMPR1_SMP9_Msk                (0x7UL << ADC_SMPR1_SMP9_Pos)        /*!< 0x38000000 */
+#define ADC_SMPR1_SMP9                    ADC_SMPR1_SMP9_Msk                   /*!< ADC Channel 9 Sampling time selection  */
+#define ADC_SMPR1_SMP9_0                  (0x1UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x08000000 */
+#define ADC_SMPR1_SMP9_1                  (0x2UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x10000000 */
+#define ADC_SMPR1_SMP9_2                  (0x4UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x20000000 */
+
+/********************  Bit definition for ADC_SMPR2 register  ********************/
+#define ADC_SMPR2_SMP10_Pos               (0U)
+#define ADC_SMPR2_SMP10_Msk               (0x7UL << ADC_SMPR2_SMP10_Pos)       /*!< 0x00000007 */
+#define ADC_SMPR2_SMP10                   ADC_SMPR2_SMP10_Msk                  /*!< ADC Channel 10 Sampling time selection  */
+#define ADC_SMPR2_SMP10_0                 (0x1UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000001 */
+#define ADC_SMPR2_SMP10_1                 (0x2UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000002 */
+#define ADC_SMPR2_SMP10_2                 (0x4UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000004 */
+
+#define ADC_SMPR2_SMP11_Pos               (3U)
+#define ADC_SMPR2_SMP11_Msk               (0x7UL << ADC_SMPR2_SMP11_Pos)       /*!< 0x00000038 */
+#define ADC_SMPR2_SMP11                   ADC_SMPR2_SMP11_Msk                  /*!< ADC Channel 11 Sampling time selection  */
+#define ADC_SMPR2_SMP11_0                 (0x1UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000008 */
+#define ADC_SMPR2_SMP11_1                 (0x2UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000010 */
+#define ADC_SMPR2_SMP11_2                 (0x4UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000020 */
+
+#define ADC_SMPR2_SMP12_Pos               (6U)
+#define ADC_SMPR2_SMP12_Msk               (0x7UL << ADC_SMPR2_SMP12_Pos)       /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP12                   ADC_SMPR2_SMP12_Msk                  /*!< ADC Channel 12 Sampling time selection  */
+#define ADC_SMPR2_SMP12_0                 (0x1UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000040 */
+#define ADC_SMPR2_SMP12_1                 (0x2UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000080 */
+#define ADC_SMPR2_SMP12_2                 (0x4UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000100 */
+
+#define ADC_SMPR2_SMP13_Pos               (9U)
+#define ADC_SMPR2_SMP13_Msk               (0x7UL << ADC_SMPR2_SMP13_Pos)       /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP13                   ADC_SMPR2_SMP13_Msk                  /*!< ADC Channel 13 Sampling time selection  */
+#define ADC_SMPR2_SMP13_0                 (0x1UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000200 */
+#define ADC_SMPR2_SMP13_1                 (0x2UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000400 */
+#define ADC_SMPR2_SMP13_2                 (0x4UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000800 */
+
+#define ADC_SMPR2_SMP14_Pos               (12U)
+#define ADC_SMPR2_SMP14_Msk               (0x7UL << ADC_SMPR2_SMP14_Pos)       /*!< 0x00007000 */
+#define ADC_SMPR2_SMP14                   ADC_SMPR2_SMP14_Msk                  /*!< ADC Channel 14 Sampling time selection  */
+#define ADC_SMPR2_SMP14_0                 (0x1UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00001000 */
+#define ADC_SMPR2_SMP14_1                 (0x2UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00002000 */
+#define ADC_SMPR2_SMP14_2                 (0x4UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00004000 */
+
+#define ADC_SMPR2_SMP15_Pos               (15U)
+#define ADC_SMPR2_SMP15_Msk               (0x7UL << ADC_SMPR2_SMP15_Pos)       /*!< 0x00038000 */
+#define ADC_SMPR2_SMP15                   ADC_SMPR2_SMP15_Msk                  /*!< ADC Channel 15 Sampling time selection  */
+#define ADC_SMPR2_SMP15_0                 (0x1UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00008000 */
+#define ADC_SMPR2_SMP15_1                 (0x2UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00010000 */
+#define ADC_SMPR2_SMP15_2                 (0x4UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00020000 */
+
+#define ADC_SMPR2_SMP16_Pos               (18U)
+#define ADC_SMPR2_SMP16_Msk               (0x7UL << ADC_SMPR2_SMP16_Pos)       /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP16                   ADC_SMPR2_SMP16_Msk                  /*!< ADC Channel 16 Sampling time selection  */
+#define ADC_SMPR2_SMP16_0                 (0x1UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00040000 */
+#define ADC_SMPR2_SMP16_1                 (0x2UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00080000 */
+#define ADC_SMPR2_SMP16_2                 (0x4UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00100000 */
+
+#define ADC_SMPR2_SMP17_Pos               (21U)
+#define ADC_SMPR2_SMP17_Msk               (0x7UL << ADC_SMPR2_SMP17_Pos)       /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP17                   ADC_SMPR2_SMP17_Msk                  /*!< ADC Channel 17 Sampling time selection  */
+#define ADC_SMPR2_SMP17_0                 (0x1UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00200000 */
+#define ADC_SMPR2_SMP17_1                 (0x2UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00400000 */
+#define ADC_SMPR2_SMP17_2                 (0x4UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00800000 */
+
+#define ADC_SMPR2_SMP18_Pos               (24U)
+#define ADC_SMPR2_SMP18_Msk               (0x7UL << ADC_SMPR2_SMP18_Pos)       /*!< 0x07000000 */
+#define ADC_SMPR2_SMP18                   ADC_SMPR2_SMP18_Msk                  /*!< ADC Channel 18 Sampling time selection  */
+#define ADC_SMPR2_SMP18_0                 (0x1UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x01000000 */
+#define ADC_SMPR2_SMP18_1                 (0x2UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x02000000 */
+#define ADC_SMPR2_SMP18_2                 (0x4UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x04000000 */
+
+#define ADC_SMPR2_SMP19_Pos               (27U)
+#define ADC_SMPR2_SMP19_Msk               (0x7UL << ADC_SMPR2_SMP19_Pos)       /*!< 0x38000000 */
+#define ADC_SMPR2_SMP19                   ADC_SMPR2_SMP19_Msk                  /*!< ADC Channel 19 Sampling time selection  */
+#define ADC_SMPR2_SMP19_0                 (0x1UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x08000000 */
+#define ADC_SMPR2_SMP19_1                 (0x2UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x10000000 */
+#define ADC_SMPR2_SMP19_2                 (0x4UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x20000000 */
+
+/********************  Bit definition for ADC_PCSEL register  ********************/
+#define ADC_PCSEL_PCSEL_Pos               (0U)
+#define ADC_PCSEL_PCSEL_Msk               (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos)   /*!< 0x000FFFFF */
+#define ADC_PCSEL_PCSEL                   ADC_PCSEL_PCSEL_Msk                  /*!< ADC pre channel selection */
+#define ADC_PCSEL_PCSEL_0                 (0x00001UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000001 */
+#define ADC_PCSEL_PCSEL_1                 (0x00002UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000002 */
+#define ADC_PCSEL_PCSEL_2                 (0x00004UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000004 */
+#define ADC_PCSEL_PCSEL_3                 (0x00008UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000008 */
+#define ADC_PCSEL_PCSEL_4                 (0x00010UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000010 */
+#define ADC_PCSEL_PCSEL_5                 (0x00020UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000020 */
+#define ADC_PCSEL_PCSEL_6                 (0x00040UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000040 */
+#define ADC_PCSEL_PCSEL_7                 (0x00080UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000080 */
+#define ADC_PCSEL_PCSEL_8                 (0x00100UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000100 */
+#define ADC_PCSEL_PCSEL_9                 (0x00200UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000200 */
+#define ADC_PCSEL_PCSEL_10                (0x00400UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000400 */
+#define ADC_PCSEL_PCSEL_11                (0x00800UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000800 */
+#define ADC_PCSEL_PCSEL_12                (0x01000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00001000 */
+#define ADC_PCSEL_PCSEL_13                (0x02000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00002000 */
+#define ADC_PCSEL_PCSEL_14                (0x04000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00004000 */
+#define ADC_PCSEL_PCSEL_15                (0x08000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00008000 */
+#define ADC_PCSEL_PCSEL_16                (0x10000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00010000 */
+#define ADC_PCSEL_PCSEL_17                (0x20000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00020000 */
+#define ADC_PCSEL_PCSEL_18                (0x40000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00040000 */
+#define ADC_PCSEL_PCSEL_19                (0x80000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00080000 */
+
+/*****************  Bit definition for ADC_LTR1, 2, 3 registers *****************/
+#define ADC_LTR_LT_Pos                    (0U)
+#define ADC_LTR_LT_Msk                    (0x3FFFFFFUL << ADC_LTR_LT_Pos)      /*!< 0x03FFFFFF */
+#define ADC_LTR_LT                        ADC_LTR_LT_Msk                       /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */
+
+/*****************  Bit definition for ADC_HTR1, 2, 3 registers  ****************/
+#define ADC_HTR_HT_Pos                    (0U)
+#define ADC_HTR_HT_Msk                    (0x3FFFFFFUL << ADC_HTR_HT_Pos)      /*!< 0x03FFFFFF */
+#define ADC_HTR_HT                        ADC_HTR_HT_Msk                       /*!< ADC Analog watchdog 1,2 and 3 higher threshold */
+
+
+/********************  Bit definition for ADC_SQR1 register  ********************/
+#define ADC_SQR1_L_Pos                    (0U)
+#define ADC_SQR1_L_Msk                    (0xFUL << ADC_SQR1_L_Pos)            /*!< 0x0000000F */
+#define ADC_SQR1_L                        ADC_SQR1_L_Msk                       /*!< ADC regular channel sequence lenght */
+#define ADC_SQR1_L_0                      (0x1UL << ADC_SQR1_L_Pos)             /*!< 0x00000001 */
+#define ADC_SQR1_L_1                      (0x2UL << ADC_SQR1_L_Pos)             /*!< 0x00000002 */
+#define ADC_SQR1_L_2                      (0x4UL << ADC_SQR1_L_Pos)             /*!< 0x00000004 */
+#define ADC_SQR1_L_3                      (0x8UL << ADC_SQR1_L_Pos)             /*!< 0x00000008 */
+
+#define ADC_SQR1_SQ1_Pos                  (6U)
+#define ADC_SQR1_SQ1_Msk                  (0x1FUL << ADC_SQR1_SQ1_Pos)         /*!< 0x000007C0 */
+#define ADC_SQR1_SQ1                      ADC_SQR1_SQ1_Msk                     /*!< ADC 1st conversion in regular sequence */
+#define ADC_SQR1_SQ1_0                    (0x01UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000040 */
+#define ADC_SQR1_SQ1_1                    (0x02UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000080 */
+#define ADC_SQR1_SQ1_2                    (0x04UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000100 */
+#define ADC_SQR1_SQ1_3                    (0x08UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000200 */
+#define ADC_SQR1_SQ1_4                    (0x10UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000400 */
+
+#define ADC_SQR1_SQ2_Pos                  (12U)
+#define ADC_SQR1_SQ2_Msk                  (0x1FUL << ADC_SQR1_SQ2_Pos)         /*!< 0x0001F000 */
+#define ADC_SQR1_SQ2                      ADC_SQR1_SQ2_Msk                     /*!< ADC 2nd conversion in regular sequence */
+#define ADC_SQR1_SQ2_0                    (0x01UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00001000 */
+#define ADC_SQR1_SQ2_1                    (0x02UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00002000 */
+#define ADC_SQR1_SQ2_2                    (0x04UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00004000 */
+#define ADC_SQR1_SQ2_3                    (0x08UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00008000 */
+#define ADC_SQR1_SQ2_4                    (0x10UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00010000 */
+
+#define ADC_SQR1_SQ3_Pos                  (18U)
+#define ADC_SQR1_SQ3_Msk                  (0x1FUL << ADC_SQR1_SQ3_Pos)         /*!< 0x007C0000 */
+#define ADC_SQR1_SQ3                      ADC_SQR1_SQ3_Msk                     /*!< ADC 3rd conversion in regular sequence */
+#define ADC_SQR1_SQ3_0                    (0x01UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00040000 */
+#define ADC_SQR1_SQ3_1                    (0x02UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00080000 */
+#define ADC_SQR1_SQ3_2                    (0x04UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00100000 */
+#define ADC_SQR1_SQ3_3                    (0x08UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00200000 */
+#define ADC_SQR1_SQ3_4                    (0x10UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00400000 */
+
+#define ADC_SQR1_SQ4_Pos                  (24U)
+#define ADC_SQR1_SQ4_Msk                  (0x1FUL << ADC_SQR1_SQ4_Pos)         /*!< 0x1F000000 */
+#define ADC_SQR1_SQ4                      ADC_SQR1_SQ4_Msk                     /*!< ADC 4th conversion in regular sequence */
+#define ADC_SQR1_SQ4_0                    (0x01UL << ADC_SQR1_SQ4_Pos)          /*!< 0x01000000 */
+#define ADC_SQR1_SQ4_1                    (0x02UL << ADC_SQR1_SQ4_Pos)          /*!< 0x02000000 */
+#define ADC_SQR1_SQ4_2                    (0x04UL << ADC_SQR1_SQ4_Pos)          /*!< 0x04000000 */
+#define ADC_SQR1_SQ4_3                    (0x08UL << ADC_SQR1_SQ4_Pos)          /*!< 0x08000000 */
+#define ADC_SQR1_SQ4_4                    (0x10UL << ADC_SQR1_SQ4_Pos)          /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR2 register  ********************/
+#define ADC_SQR2_SQ5_Pos                  (0U)
+#define ADC_SQR2_SQ5_Msk                  (0x1FUL << ADC_SQR2_SQ5_Pos)         /*!< 0x0000001F */
+#define ADC_SQR2_SQ5                      ADC_SQR2_SQ5_Msk                     /*!< ADC 5th conversion in regular sequence */
+#define ADC_SQR2_SQ5_0                    (0x01UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000001 */
+#define ADC_SQR2_SQ5_1                    (0x02UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000002 */
+#define ADC_SQR2_SQ5_2                    (0x04UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000004 */
+#define ADC_SQR2_SQ5_3                    (0x08UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000008 */
+#define ADC_SQR2_SQ5_4                    (0x10UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000010 */
+
+#define ADC_SQR2_SQ6_Pos                  (6U)
+#define ADC_SQR2_SQ6_Msk                  (0x1FUL << ADC_SQR2_SQ6_Pos)         /*!< 0x000007C0 */
+#define ADC_SQR2_SQ6                      ADC_SQR2_SQ6_Msk                     /*!< ADC 6th conversion in regular sequence */
+#define ADC_SQR2_SQ6_0                    (0x01UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000040 */
+#define ADC_SQR2_SQ6_1                    (0x02UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000080 */
+#define ADC_SQR2_SQ6_2                    (0x04UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000100 */
+#define ADC_SQR2_SQ6_3                    (0x08UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000200 */
+#define ADC_SQR2_SQ6_4                    (0x10UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000400 */
+
+#define ADC_SQR2_SQ7_Pos                  (12U)
+#define ADC_SQR2_SQ7_Msk                  (0x1FUL << ADC_SQR2_SQ7_Pos)         /*!< 0x0001F000 */
+#define ADC_SQR2_SQ7                      ADC_SQR2_SQ7_Msk                     /*!< ADC 7th conversion in regular sequence */
+#define ADC_SQR2_SQ7_0                    (0x01UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00001000 */
+#define ADC_SQR2_SQ7_1                    (0x02UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00002000 */
+#define ADC_SQR2_SQ7_2                    (0x04UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00004000 */
+#define ADC_SQR2_SQ7_3                    (0x08UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00008000 */
+#define ADC_SQR2_SQ7_4                    (0x10UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00010000 */
+
+#define ADC_SQR2_SQ8_Pos                  (18U)
+#define ADC_SQR2_SQ8_Msk                  (0x1FUL << ADC_SQR2_SQ8_Pos)         /*!< 0x007C0000 */
+#define ADC_SQR2_SQ8                      ADC_SQR2_SQ8_Msk                     /*!< ADC 8th conversion in regular sequence */
+#define ADC_SQR2_SQ8_0                    (0x01UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00040000 */
+#define ADC_SQR2_SQ8_1                    (0x02UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00080000 */
+#define ADC_SQR2_SQ8_2                    (0x04UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00100000 */
+#define ADC_SQR2_SQ8_3                    (0x08UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00200000 */
+#define ADC_SQR2_SQ8_4                    (0x10UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00400000 */
+
+#define ADC_SQR2_SQ9_Pos                  (24U)
+#define ADC_SQR2_SQ9_Msk                  (0x1FUL << ADC_SQR2_SQ9_Pos)         /*!< 0x1F000000 */
+#define ADC_SQR2_SQ9                      ADC_SQR2_SQ9_Msk                     /*!< ADC 9th conversion in regular sequence */
+#define ADC_SQR2_SQ9_0                    (0x01UL << ADC_SQR2_SQ9_Pos)          /*!< 0x01000000 */
+#define ADC_SQR2_SQ9_1                    (0x02UL << ADC_SQR2_SQ9_Pos)          /*!< 0x02000000 */
+#define ADC_SQR2_SQ9_2                    (0x04UL << ADC_SQR2_SQ9_Pos)          /*!< 0x04000000 */
+#define ADC_SQR2_SQ9_3                    (0x08UL << ADC_SQR2_SQ9_Pos)          /*!< 0x08000000 */
+#define ADC_SQR2_SQ9_4                    (0x10UL << ADC_SQR2_SQ9_Pos)          /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR3 register  ********************/
+#define ADC_SQR3_SQ10_Pos                 (0U)
+#define ADC_SQR3_SQ10_Msk                 (0x1FUL << ADC_SQR3_SQ10_Pos)        /*!< 0x0000001F */
+#define ADC_SQR3_SQ10                     ADC_SQR3_SQ10_Msk                    /*!< ADC 10th conversion in regular sequence */
+#define ADC_SQR3_SQ10_0                   (0x01UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000001 */
+#define ADC_SQR3_SQ10_1                   (0x02UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000002 */
+#define ADC_SQR3_SQ10_2                   (0x04UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000004 */
+#define ADC_SQR3_SQ10_3                   (0x08UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000008 */
+#define ADC_SQR3_SQ10_4                   (0x10UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000010 */
+
+#define ADC_SQR3_SQ11_Pos                 (6U)
+#define ADC_SQR3_SQ11_Msk                 (0x1FUL << ADC_SQR3_SQ11_Pos)        /*!< 0x000007C0 */
+#define ADC_SQR3_SQ11                     ADC_SQR3_SQ11_Msk                    /*!< ADC 11th conversion in regular sequence */
+#define ADC_SQR3_SQ11_0                   (0x01UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000040 */
+#define ADC_SQR3_SQ11_1                   (0x02UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000080 */
+#define ADC_SQR3_SQ11_2                   (0x04UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000100 */
+#define ADC_SQR3_SQ11_3                   (0x08UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000200 */
+#define ADC_SQR3_SQ11_4                   (0x10UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000400 */
+
+#define ADC_SQR3_SQ12_Pos                 (12U)
+#define ADC_SQR3_SQ12_Msk                 (0x1FUL << ADC_SQR3_SQ12_Pos)        /*!< 0x0001F000 */
+#define ADC_SQR3_SQ12                     ADC_SQR3_SQ12_Msk                    /*!< ADC 12th conversion in regular sequence */
+#define ADC_SQR3_SQ12_0                   (0x01UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00001000 */
+#define ADC_SQR3_SQ12_1                   (0x02UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00002000 */
+#define ADC_SQR3_SQ12_2                   (0x04UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00004000 */
+#define ADC_SQR3_SQ12_3                   (0x08UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00008000 */
+#define ADC_SQR3_SQ12_4                   (0x10UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00010000 */
+
+#define ADC_SQR3_SQ13_Pos                 (18U)
+#define ADC_SQR3_SQ13_Msk                 (0x1FUL << ADC_SQR3_SQ13_Pos)        /*!< 0x007C0000 */
+#define ADC_SQR3_SQ13                     ADC_SQR3_SQ13_Msk                    /*!< ADC 13th conversion in regular sequence */
+#define ADC_SQR3_SQ13_0                   (0x01UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00040000 */
+#define ADC_SQR3_SQ13_1                   (0x02UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00080000 */
+#define ADC_SQR3_SQ13_2                   (0x04UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00100000 */
+#define ADC_SQR3_SQ13_3                   (0x08UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00200000 */
+#define ADC_SQR3_SQ13_4                   (0x10UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00400000 */
+
+#define ADC_SQR3_SQ14_Pos                 (24U)
+#define ADC_SQR3_SQ14_Msk                 (0x1FUL << ADC_SQR3_SQ14_Pos)        /*!< 0x1F000000 */
+#define ADC_SQR3_SQ14                     ADC_SQR3_SQ14_Msk                    /*!< ADC 14th conversion in regular sequence */
+#define ADC_SQR3_SQ14_0                   (0x01UL << ADC_SQR3_SQ14_Pos)         /*!< 0x01000000 */
+#define ADC_SQR3_SQ14_1                   (0x02UL << ADC_SQR3_SQ14_Pos)         /*!< 0x02000000 */
+#define ADC_SQR3_SQ14_2                   (0x04UL << ADC_SQR3_SQ14_Pos)         /*!< 0x04000000 */
+#define ADC_SQR3_SQ14_3                   (0x08UL << ADC_SQR3_SQ14_Pos)         /*!< 0x08000000 */
+#define ADC_SQR3_SQ14_4                   (0x10UL << ADC_SQR3_SQ14_Pos)         /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR4 register  ********************/
+#define ADC_SQR4_SQ15_Pos                 (0U)
+#define ADC_SQR4_SQ15_Msk                 (0x1FUL << ADC_SQR4_SQ15_Pos)        /*!< 0x0000001F */
+#define ADC_SQR4_SQ15                     ADC_SQR4_SQ15_Msk                    /*!< ADC 15th conversion in regular sequence */
+#define ADC_SQR4_SQ15_0                   (0x01UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000001 */
+#define ADC_SQR4_SQ15_1                   (0x02UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000002 */
+#define ADC_SQR4_SQ15_2                   (0x04UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000004 */
+#define ADC_SQR4_SQ15_3                   (0x08UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000008 */
+#define ADC_SQR4_SQ15_4                   (0x10UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000010 */
+
+#define ADC_SQR4_SQ16_Pos                 (6U)
+#define ADC_SQR4_SQ16_Msk                 (0x1FUL << ADC_SQR4_SQ16_Pos)        /*!< 0x000007C0 */
+#define ADC_SQR4_SQ16                     ADC_SQR4_SQ16_Msk                    /*!< ADC 16th conversion in regular sequence */
+#define ADC_SQR4_SQ16_0                   (0x01UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000040 */
+#define ADC_SQR4_SQ16_1                   (0x02UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000080 */
+#define ADC_SQR4_SQ16_2                   (0x04UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000100 */
+#define ADC_SQR4_SQ16_3                   (0x08UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000200 */
+#define ADC_SQR4_SQ16_4                   (0x10UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000400 */
+/********************  Bit definition for ADC_DR register  ********************/
+#define ADC_DR_RDATA_Pos                  (0U)
+#define ADC_DR_RDATA_Msk                  (0xFFFFFFFFUL << ADC_DR_RDATA_Pos)   /*!< 0xFFFFFFFF */
+#define ADC_DR_RDATA                      ADC_DR_RDATA_Msk                     /*!< ADC regular Data converted */
+
+/********************  Bit definition for ADC_JSQR register  ********************/
+#define ADC_JSQR_JL_Pos                   (0U)
+#define ADC_JSQR_JL_Msk                   (0x3UL << ADC_JSQR_JL_Pos)           /*!< 0x00000003 */
+#define ADC_JSQR_JL                       ADC_JSQR_JL_Msk                      /*!< ADC injected channel sequence length */
+#define ADC_JSQR_JL_0                     (0x1UL << ADC_JSQR_JL_Pos)           /*!< 0x00000001 */
+#define ADC_JSQR_JL_1                     (0x2UL << ADC_JSQR_JL_Pos)           /*!< 0x00000002 */
+
+#define ADC_JSQR_JEXTSEL_Pos              (2U)
+#define ADC_JSQR_JEXTSEL_Msk              (0x1FUL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x0000007C */
+#define ADC_JSQR_JEXTSEL                  ADC_JSQR_JEXTSEL_Msk                 /*!< ADC external trigger selection for injected group */
+#define ADC_JSQR_JEXTSEL_0                (0x01UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000004 */
+#define ADC_JSQR_JEXTSEL_1                (0x02UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000008 */
+#define ADC_JSQR_JEXTSEL_2                (0x04UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000010 */
+#define ADC_JSQR_JEXTSEL_3                (0x08UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000020 */
+#define ADC_JSQR_JEXTSEL_4                (0x10UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000040 */
+
+#define ADC_JSQR_JEXTEN_Pos               (7U)
+#define ADC_JSQR_JEXTEN_Msk               (0x3UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000180 */
+#define ADC_JSQR_JEXTEN                   ADC_JSQR_JEXTEN_Msk                  /*!< ADC external trigger enable and polarity selection for injected channels */
+#define ADC_JSQR_JEXTEN_0                 (0x1UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000080 */
+#define ADC_JSQR_JEXTEN_1                 (0x2UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000100 */
+
+#define ADC_JSQR_JSQ1_Pos                 (9U)
+#define ADC_JSQR_JSQ1_Msk                 (0x1FUL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00003E00 */
+#define ADC_JSQR_JSQ1                     ADC_JSQR_JSQ1_Msk                    /*!< ADC 1st conversion in injected sequence */
+#define ADC_JSQR_JSQ1_0                   (0x01UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000200 */
+#define ADC_JSQR_JSQ1_1                   (0x02UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000400 */
+#define ADC_JSQR_JSQ1_2                   (0x04UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000800 */
+#define ADC_JSQR_JSQ1_3                   (0x08UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00001000 */
+#define ADC_JSQR_JSQ1_4                   (0x10UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00002000 */
+
+#define ADC_JSQR_JSQ2_Pos                 (15U)
+#define ADC_JSQR_JSQ2_Msk                 (0x1FUL << ADC_JSQR_JSQ2_Pos)        /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ2                     ADC_JSQR_JSQ2_Msk                    /*!< ADC 2nd conversion in injected sequence */
+#define ADC_JSQR_JSQ2_0                   (0x01UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00008000 */
+#define ADC_JSQR_JSQ2_1                   (0x02UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00010000 */
+#define ADC_JSQR_JSQ2_2                   (0x04UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00020000 */
+#define ADC_JSQR_JSQ2_3                   (0x08UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00040000 */
+#define ADC_JSQR_JSQ2_4                   (0x10UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00080000 */
+
+#define ADC_JSQR_JSQ3_Pos                 (21U)
+#define ADC_JSQR_JSQ3_Msk                 (0x1FUL << ADC_JSQR_JSQ3_Pos)        /*!< 0x03E00000 */
+#define ADC_JSQR_JSQ3                     ADC_JSQR_JSQ3_Msk                    /*!< ADC 3rd conversion in injected sequence */
+#define ADC_JSQR_JSQ3_0                   (0x01UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00200000 */
+#define ADC_JSQR_JSQ3_1                   (0x02UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00400000 */
+#define ADC_JSQR_JSQ3_2                   (0x04UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00800000 */
+#define ADC_JSQR_JSQ3_3                   (0x08UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x01000000 */
+#define ADC_JSQR_JSQ3_4                   (0x10UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x02000000 */
+
+#define ADC_JSQR_JSQ4_Pos                 (27U)
+#define ADC_JSQR_JSQ4_Msk                 (0x1FUL << ADC_JSQR_JSQ4_Pos)        /*!< 0xF8000000 */
+#define ADC_JSQR_JSQ4                     ADC_JSQR_JSQ4_Msk                    /*!< ADC 4th conversion in injected sequence */
+#define ADC_JSQR_JSQ4_0                   (0x01UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x08000000 */
+#define ADC_JSQR_JSQ4_1                   (0x02UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x10000000 */
+#define ADC_JSQR_JSQ4_2                   (0x04UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x20000000 */
+#define ADC_JSQR_JSQ4_3                   (0x08UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x40000000 */
+#define ADC_JSQR_JSQ4_4                   (0x10UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_OFR1 register  ********************/
+#define ADC_OFR1_OFFSET1_Pos              (0U)
+#define ADC_OFR1_OFFSET1_Msk              (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */
+#define ADC_OFR1_OFFSET1                  ADC_OFR1_OFFSET1_Msk                  /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
+#define ADC_OFR1_OFFSET1_0                (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
+#define ADC_OFR1_OFFSET1_1                (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
+#define ADC_OFR1_OFFSET1_2                (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
+#define ADC_OFR1_OFFSET1_3                (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
+#define ADC_OFR1_OFFSET1_4                (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
+#define ADC_OFR1_OFFSET1_5                (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
+#define ADC_OFR1_OFFSET1_6                (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
+#define ADC_OFR1_OFFSET1_7                (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
+#define ADC_OFR1_OFFSET1_8                (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
+#define ADC_OFR1_OFFSET1_9                (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
+#define ADC_OFR1_OFFSET1_10               (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
+#define ADC_OFR1_OFFSET1_11               (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
+#define ADC_OFR1_OFFSET1_12               (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */
+#define ADC_OFR1_OFFSET1_13               (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */
+#define ADC_OFR1_OFFSET1_14               (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */
+#define ADC_OFR1_OFFSET1_15               (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */
+#define ADC_OFR1_OFFSET1_16               (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */
+#define ADC_OFR1_OFFSET1_17               (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */
+#define ADC_OFR1_OFFSET1_18               (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */
+#define ADC_OFR1_OFFSET1_19               (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */
+#define ADC_OFR1_OFFSET1_20               (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */
+#define ADC_OFR1_OFFSET1_21               (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */
+#define ADC_OFR1_OFFSET1_22               (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */
+#define ADC_OFR1_OFFSET1_23               (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */
+#define ADC_OFR1_OFFSET1_24               (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */
+#define ADC_OFR1_OFFSET1_25               (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */
+
+#define ADC_OFR1_OFFSET1_CH_Pos           (26U)
+#define ADC_OFR1_OFFSET1_CH_Msk           (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x7C000000 */
+#define ADC_OFR1_OFFSET1_CH               ADC_OFR1_OFFSET1_CH_Msk               /*!< ADC Channel selection for the data offset 1 */
+#define ADC_OFR1_OFFSET1_CH_0             (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x04000000 */
+#define ADC_OFR1_OFFSET1_CH_1             (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x08000000 */
+#define ADC_OFR1_OFFSET1_CH_2             (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x10000000 */
+#define ADC_OFR1_OFFSET1_CH_3             (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x20000000 */
+#define ADC_OFR1_OFFSET1_CH_4             (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x40000000 */
+
+#define ADC_OFR1_SSATE_Pos                (31U)
+#define ADC_OFR1_SSATE_Msk                (0x1UL << ADC_OFR1_SSATE_Pos)         /*!< 0x80000000 */
+#define ADC_OFR1_SSATE                    ADC_OFR1_SSATE_Msk                    /*!< ADC Signed saturation Enable */
+
+
+/********************  Bit definition for ADC_OFR2 register  ********************/
+#define ADC_OFR2_OFFSET2_Pos              (0U)
+#define ADC_OFR2_OFFSET2_Msk              (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */
+#define ADC_OFR2_OFFSET2                  ADC_OFR2_OFFSET2_Msk                  /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
+#define ADC_OFR2_OFFSET2_0                (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
+#define ADC_OFR2_OFFSET2_1                (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
+#define ADC_OFR2_OFFSET2_2                (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
+#define ADC_OFR2_OFFSET2_3                (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
+#define ADC_OFR2_OFFSET2_4                (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
+#define ADC_OFR2_OFFSET2_5                (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
+#define ADC_OFR2_OFFSET2_6                (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
+#define ADC_OFR2_OFFSET2_7                (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
+#define ADC_OFR2_OFFSET2_8                (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
+#define ADC_OFR2_OFFSET2_9                (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
+#define ADC_OFR2_OFFSET2_10               (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
+#define ADC_OFR2_OFFSET2_11               (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
+#define ADC_OFR2_OFFSET2_12               (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */
+#define ADC_OFR2_OFFSET2_13               (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */
+#define ADC_OFR2_OFFSET2_14               (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */
+#define ADC_OFR2_OFFSET2_15               (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */
+#define ADC_OFR2_OFFSET2_16               (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */
+#define ADC_OFR2_OFFSET2_17               (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */
+#define ADC_OFR2_OFFSET2_18               (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */
+#define ADC_OFR2_OFFSET2_19               (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */
+#define ADC_OFR2_OFFSET2_20               (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */
+#define ADC_OFR2_OFFSET2_21               (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */
+#define ADC_OFR2_OFFSET2_22               (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */
+#define ADC_OFR2_OFFSET2_23               (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */
+#define ADC_OFR2_OFFSET2_24               (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */
+#define ADC_OFR2_OFFSET2_25               (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */
+
+#define ADC_OFR2_OFFSET2_CH_Pos           (26U)
+#define ADC_OFR2_OFFSET2_CH_Msk           (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x7C000000 */
+#define ADC_OFR2_OFFSET2_CH               ADC_OFR2_OFFSET2_CH_Msk               /*!< ADC Channel selection for the data offset 2 */
+#define ADC_OFR2_OFFSET2_CH_0             (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x04000000 */
+#define ADC_OFR2_OFFSET2_CH_1             (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x08000000 */
+#define ADC_OFR2_OFFSET2_CH_2             (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x10000000 */
+#define ADC_OFR2_OFFSET2_CH_3             (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x20000000 */
+#define ADC_OFR2_OFFSET2_CH_4             (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x40000000 */
+
+#define ADC_OFR2_SSATE_Pos                (31U)
+#define ADC_OFR2_SSATE_Msk                (0x1UL << ADC_OFR2_SSATE_Pos)         /*!< 0x80000000 */
+#define ADC_OFR2_SSATE                    ADC_OFR2_SSATE_Msk                    /*!< ADC Signed saturation Enable */
+
+
+/********************  Bit definition for ADC_OFR3 register  ********************/
+#define ADC_OFR3_OFFSET3_Pos              (0U)
+#define ADC_OFR3_OFFSET3_Msk              (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */
+#define ADC_OFR3_OFFSET3                  ADC_OFR3_OFFSET3_Msk                  /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
+#define ADC_OFR3_OFFSET3_0                (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
+#define ADC_OFR3_OFFSET3_1                (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
+#define ADC_OFR3_OFFSET3_2                (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
+#define ADC_OFR3_OFFSET3_3                (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
+#define ADC_OFR3_OFFSET3_4                (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
+#define ADC_OFR3_OFFSET3_5                (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
+#define ADC_OFR3_OFFSET3_6                (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
+#define ADC_OFR3_OFFSET3_7                (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
+#define ADC_OFR3_OFFSET3_8                (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
+#define ADC_OFR3_OFFSET3_9                (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
+#define ADC_OFR3_OFFSET3_10               (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
+#define ADC_OFR3_OFFSET3_11               (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
+#define ADC_OFR3_OFFSET3_12               (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */
+#define ADC_OFR3_OFFSET3_13               (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */
+#define ADC_OFR3_OFFSET3_14               (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */
+#define ADC_OFR3_OFFSET3_15               (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */
+#define ADC_OFR3_OFFSET3_16               (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */
+#define ADC_OFR3_OFFSET3_17               (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */
+#define ADC_OFR3_OFFSET3_18               (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */
+#define ADC_OFR3_OFFSET3_19               (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */
+#define ADC_OFR3_OFFSET3_20               (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */
+#define ADC_OFR3_OFFSET3_21               (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */
+#define ADC_OFR3_OFFSET3_22               (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */
+#define ADC_OFR3_OFFSET3_23               (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */
+#define ADC_OFR3_OFFSET3_24               (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */
+#define ADC_OFR3_OFFSET3_25               (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */
+
+#define ADC_OFR3_OFFSET3_CH_Pos           (26U)
+#define ADC_OFR3_OFFSET3_CH_Msk           (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x7C000000 */
+#define ADC_OFR3_OFFSET3_CH               ADC_OFR3_OFFSET3_CH_Msk               /*!< ADC Channel selection for the data offset 3 */
+#define ADC_OFR3_OFFSET3_CH_0             (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x04000000 */
+#define ADC_OFR3_OFFSET3_CH_1             (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x08000000 */
+#define ADC_OFR3_OFFSET3_CH_2             (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x10000000 */
+#define ADC_OFR3_OFFSET3_CH_3             (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x20000000 */
+#define ADC_OFR3_OFFSET3_CH_4             (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x40000000 */
+
+#define ADC_OFR3_SSATE_Pos                (31U)
+#define ADC_OFR3_SSATE_Msk                (0x1UL << ADC_OFR3_SSATE_Pos)         /*!< 0x80000000 */
+#define ADC_OFR3_SSATE                    ADC_OFR3_SSATE_Msk                    /*!< ADC Signed saturation Enable */
+
+
+/********************  Bit definition for ADC_OFR4 register  ********************/
+#define ADC_OFR4_OFFSET4_Pos              (0U)
+#define ADC_OFR4_OFFSET4_Msk              (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */
+#define ADC_OFR4_OFFSET4                  ADC_OFR4_OFFSET4_Msk                  /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
+#define ADC_OFR4_OFFSET4_0                (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
+#define ADC_OFR4_OFFSET4_1                (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
+#define ADC_OFR4_OFFSET4_2                (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
+#define ADC_OFR4_OFFSET4_3                (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
+#define ADC_OFR4_OFFSET4_4                (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
+#define ADC_OFR4_OFFSET4_5                (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
+#define ADC_OFR4_OFFSET4_6                (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
+#define ADC_OFR4_OFFSET4_7                (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
+#define ADC_OFR4_OFFSET4_8                (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
+#define ADC_OFR4_OFFSET4_9                (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
+#define ADC_OFR4_OFFSET4_10               (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
+#define ADC_OFR4_OFFSET4_11               (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
+#define ADC_OFR4_OFFSET4_12               (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */
+#define ADC_OFR4_OFFSET4_13               (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */
+#define ADC_OFR4_OFFSET4_14               (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */
+#define ADC_OFR4_OFFSET4_15               (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */
+#define ADC_OFR4_OFFSET4_16               (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */
+#define ADC_OFR4_OFFSET4_17               (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */
+#define ADC_OFR4_OFFSET4_18               (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */
+#define ADC_OFR4_OFFSET4_19               (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */
+#define ADC_OFR4_OFFSET4_20               (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */
+#define ADC_OFR4_OFFSET4_21               (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */
+#define ADC_OFR4_OFFSET4_22               (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */
+#define ADC_OFR4_OFFSET4_23               (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */
+#define ADC_OFR4_OFFSET4_24               (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */
+#define ADC_OFR4_OFFSET4_25               (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */
+
+#define ADC_OFR4_OFFSET4_CH_Pos           (26U)
+#define ADC_OFR4_OFFSET4_CH_Msk           (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x7C000000 */
+#define ADC_OFR4_OFFSET4_CH               ADC_OFR4_OFFSET4_CH_Msk               /*!< ADC Channel selection for the data offset 4 */
+#define ADC_OFR4_OFFSET4_CH_0             (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x04000000 */
+#define ADC_OFR4_OFFSET4_CH_1             (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x08000000 */
+#define ADC_OFR4_OFFSET4_CH_2             (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x10000000 */
+#define ADC_OFR4_OFFSET4_CH_3             (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x20000000 */
+#define ADC_OFR4_OFFSET4_CH_4             (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x40000000 */
+
+#define ADC_OFR4_SSATE_Pos                (31U)
+#define ADC_OFR4_SSATE_Msk                (0x1UL << ADC_OFR4_SSATE_Pos)         /*!< 0x80000000 */
+#define ADC_OFR4_SSATE                    ADC_OFR4_SSATE_Msk                    /*!< ADC Signed saturation Enable */
+
+
+/********************  Bit definition for ADC_JDR1 register  ********************/
+#define ADC_JDR1_JDATA_Pos                (0U)
+#define ADC_JDR1_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos)  /*!< 0xFFFFFFFF */
+#define ADC_JDR1_JDATA                    ADC_JDR1_JDATA_Msk                    /*!< ADC Injected DATA */
+#define ADC_JDR1_JDATA_0                  (0x00000001UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000001 */
+#define ADC_JDR1_JDATA_1                  (0x00000002UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000002 */
+#define ADC_JDR1_JDATA_2                  (0x00000004UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000004 */
+#define ADC_JDR1_JDATA_3                  (0x00000008UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000008 */
+#define ADC_JDR1_JDATA_4                  (0x00000010UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000010 */
+#define ADC_JDR1_JDATA_5                  (0x00000020UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000020 */
+#define ADC_JDR1_JDATA_6                  (0x00000040UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000040 */
+#define ADC_JDR1_JDATA_7                  (0x00000080UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000080 */
+#define ADC_JDR1_JDATA_8                  (0x00000100UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000100 */
+#define ADC_JDR1_JDATA_9                  (0x00000200UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000200 */
+#define ADC_JDR1_JDATA_10                 (0x00000400UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000400 */
+#define ADC_JDR1_JDATA_11                 (0x00000800UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000800 */
+#define ADC_JDR1_JDATA_12                 (0x00001000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00001000 */
+#define ADC_JDR1_JDATA_13                 (0x00002000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00002000 */
+#define ADC_JDR1_JDATA_14                 (0x00004000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00004000 */
+#define ADC_JDR1_JDATA_15                 (0x00008000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00008000 */
+#define ADC_JDR1_JDATA_16                 (0x00010000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00010000 */
+#define ADC_JDR1_JDATA_17                 (0x00020000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00020000 */
+#define ADC_JDR1_JDATA_18                 (0x00040000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00040000 */
+#define ADC_JDR1_JDATA_19                 (0x00080000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00080000 */
+#define ADC_JDR1_JDATA_20                 (0x00100000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00100000 */
+#define ADC_JDR1_JDATA_21                 (0x00200000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00200000 */
+#define ADC_JDR1_JDATA_22                 (0x00400000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00400000 */
+#define ADC_JDR1_JDATA_23                 (0x00800000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00800000 */
+#define ADC_JDR1_JDATA_24                 (0x01000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x01000000 */
+#define ADC_JDR1_JDATA_25                 (0x02000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x02000000 */
+#define ADC_JDR1_JDATA_26                 (0x04000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x04000000 */
+#define ADC_JDR1_JDATA_27                 (0x08000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x08000000 */
+#define ADC_JDR1_JDATA_28                 (0x10000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x10000000 */
+#define ADC_JDR1_JDATA_29                 (0x20000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x20000000 */
+#define ADC_JDR1_JDATA_30                 (0x40000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x40000000 */
+#define ADC_JDR1_JDATA_31                 (0x80000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_JDR2 register  ********************/
+#define ADC_JDR2_JDATA_Pos                (0U)
+#define ADC_JDR2_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos)  /*!< 0xFFFFFFFF */
+#define ADC_JDR2_JDATA                    ADC_JDR2_JDATA_Msk                    /*!< ADC Injected DATA */
+#define ADC_JDR2_JDATA_0                  (0x00000001UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000001 */
+#define ADC_JDR2_JDATA_1                  (0x00000002UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000002 */
+#define ADC_JDR2_JDATA_2                  (0x00000004UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000004 */
+#define ADC_JDR2_JDATA_3                  (0x00000008UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000008 */
+#define ADC_JDR2_JDATA_4                  (0x00000010UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000010 */
+#define ADC_JDR2_JDATA_5                  (0x00000020UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000020 */
+#define ADC_JDR2_JDATA_6                  (0x00000040UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000040 */
+#define ADC_JDR2_JDATA_7                  (0x00000080UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000080 */
+#define ADC_JDR2_JDATA_8                  (0x00000100UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000100 */
+#define ADC_JDR2_JDATA_9                  (0x00000200UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000200 */
+#define ADC_JDR2_JDATA_10                 (0x00000400UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000400 */
+#define ADC_JDR2_JDATA_11                 (0x00000800UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000800 */
+#define ADC_JDR2_JDATA_12                 (0x00001000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00001000 */
+#define ADC_JDR2_JDATA_13                 (0x00002000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00002000 */
+#define ADC_JDR2_JDATA_14                 (0x00004000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00004000 */
+#define ADC_JDR2_JDATA_15                 (0x00008000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00008000 */
+#define ADC_JDR2_JDATA_16                 (0x00010000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00010000 */
+#define ADC_JDR2_JDATA_17                 (0x00020000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00020000 */
+#define ADC_JDR2_JDATA_18                 (0x00040000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00040000 */
+#define ADC_JDR2_JDATA_19                 (0x00080000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00080000 */
+#define ADC_JDR2_JDATA_20                 (0x00100000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00100000 */
+#define ADC_JDR2_JDATA_21                 (0x00200000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00200000 */
+#define ADC_JDR2_JDATA_22                 (0x00400000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00400000 */
+#define ADC_JDR2_JDATA_23                 (0x00800000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00800000 */
+#define ADC_JDR2_JDATA_24                 (0x01000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x01000000 */
+#define ADC_JDR2_JDATA_25                 (0x02000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x02000000 */
+#define ADC_JDR2_JDATA_26                 (0x04000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x04000000 */
+#define ADC_JDR2_JDATA_27                 (0x08000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x08000000 */
+#define ADC_JDR2_JDATA_28                 (0x10000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x10000000 */
+#define ADC_JDR2_JDATA_29                 (0x20000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x20000000 */
+#define ADC_JDR2_JDATA_30                 (0x40000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x40000000 */
+#define ADC_JDR2_JDATA_31                 (0x80000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_JDR3 register  ********************/
+#define ADC_JDR3_JDATA_Pos                (0U)
+#define ADC_JDR3_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos)  /*!< 0xFFFFFFFF */
+#define ADC_JDR3_JDATA                    ADC_JDR3_JDATA_Msk                    /*!< ADC Injected DATA */
+#define ADC_JDR3_JDATA_0                  (0x00000001UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000001 */
+#define ADC_JDR3_JDATA_1                  (0x00000002UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000002 */
+#define ADC_JDR3_JDATA_2                  (0x00000004UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000004 */
+#define ADC_JDR3_JDATA_3                  (0x00000008UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000008 */
+#define ADC_JDR3_JDATA_4                  (0x00000010UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000010 */
+#define ADC_JDR3_JDATA_5                  (0x00000020UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000020 */
+#define ADC_JDR3_JDATA_6                  (0x00000040UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000040 */
+#define ADC_JDR3_JDATA_7                  (0x00000080UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000080 */
+#define ADC_JDR3_JDATA_8                  (0x00000100UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000100 */
+#define ADC_JDR3_JDATA_9                  (0x00000200UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000200 */
+#define ADC_JDR3_JDATA_10                 (0x00000400UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000400 */
+#define ADC_JDR3_JDATA_11                 (0x00000800UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000800 */
+#define ADC_JDR3_JDATA_12                 (0x00001000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00001000 */
+#define ADC_JDR3_JDATA_13                 (0x00002000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00002000 */
+#define ADC_JDR3_JDATA_14                 (0x00004000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00004000 */
+#define ADC_JDR3_JDATA_15                 (0x00008000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00008000 */
+#define ADC_JDR3_JDATA_16                 (0x00010000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00010000 */
+#define ADC_JDR3_JDATA_17                 (0x00020000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00020000 */
+#define ADC_JDR3_JDATA_18                 (0x00040000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00040000 */
+#define ADC_JDR3_JDATA_19                 (0x00080000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00080000 */
+#define ADC_JDR3_JDATA_20                 (0x00100000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00100000 */
+#define ADC_JDR3_JDATA_21                 (0x00200000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00200000 */
+#define ADC_JDR3_JDATA_22                 (0x00400000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00400000 */
+#define ADC_JDR3_JDATA_23                 (0x00800000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00800000 */
+#define ADC_JDR3_JDATA_24                 (0x01000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x01000000 */
+#define ADC_JDR3_JDATA_25                 (0x02000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x02000000 */
+#define ADC_JDR3_JDATA_26                 (0x04000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x04000000 */
+#define ADC_JDR3_JDATA_27                 (0x08000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x08000000 */
+#define ADC_JDR3_JDATA_28                 (0x10000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x10000000 */
+#define ADC_JDR3_JDATA_29                 (0x20000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x20000000 */
+#define ADC_JDR3_JDATA_30                 (0x40000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x40000000 */
+#define ADC_JDR3_JDATA_31                 (0x80000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_JDR4 register  ********************/
+#define ADC_JDR4_JDATA_Pos                (0U)
+#define ADC_JDR4_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos)  /*!< 0xFFFFFFFF */
+#define ADC_JDR4_JDATA                    ADC_JDR4_JDATA_Msk                    /*!< ADC Injected DATA */
+#define ADC_JDR4_JDATA_0                  (0x00000001UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000001 */
+#define ADC_JDR4_JDATA_1                  (0x00000002UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000002 */
+#define ADC_JDR4_JDATA_2                  (0x00000004UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000004 */
+#define ADC_JDR4_JDATA_3                  (0x00000008UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000008 */
+#define ADC_JDR4_JDATA_4                  (0x00000010UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000010 */
+#define ADC_JDR4_JDATA_5                  (0x00000020UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000020 */
+#define ADC_JDR4_JDATA_6                  (0x00000040UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000040 */
+#define ADC_JDR4_JDATA_7                  (0x00000080UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000080 */
+#define ADC_JDR4_JDATA_8                  (0x00000100UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000100 */
+#define ADC_JDR4_JDATA_9                  (0x00000200UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000200 */
+#define ADC_JDR4_JDATA_10                 (0x00000400UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000400 */
+#define ADC_JDR4_JDATA_11                 (0x00000800UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000800 */
+#define ADC_JDR4_JDATA_12                 (0x00001000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00001000 */
+#define ADC_JDR4_JDATA_13                 (0x00002000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00002000 */
+#define ADC_JDR4_JDATA_14                 (0x00004000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00004000 */
+#define ADC_JDR4_JDATA_15                 (0x00008000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00008000 */
+#define ADC_JDR4_JDATA_16                 (0x00010000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00010000 */
+#define ADC_JDR4_JDATA_17                 (0x00020000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00020000 */
+#define ADC_JDR4_JDATA_18                 (0x00040000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00040000 */
+#define ADC_JDR4_JDATA_19                 (0x00080000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00080000 */
+#define ADC_JDR4_JDATA_20                 (0x00100000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00100000 */
+#define ADC_JDR4_JDATA_21                 (0x00200000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00200000 */
+#define ADC_JDR4_JDATA_22                 (0x00400000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00400000 */
+#define ADC_JDR4_JDATA_23                 (0x00800000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00800000 */
+#define ADC_JDR4_JDATA_24                 (0x01000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x01000000 */
+#define ADC_JDR4_JDATA_25                 (0x02000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x02000000 */
+#define ADC_JDR4_JDATA_26                 (0x04000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x04000000 */
+#define ADC_JDR4_JDATA_27                 (0x08000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x08000000 */
+#define ADC_JDR4_JDATA_28                 (0x10000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x10000000 */
+#define ADC_JDR4_JDATA_29                 (0x20000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x20000000 */
+#define ADC_JDR4_JDATA_30                 (0x40000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x40000000 */
+#define ADC_JDR4_JDATA_31                 (0x80000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_AWD2CR register  ********************/
+#define ADC_AWD2CR_AWD2CH_Pos             (0U)
+#define ADC_AWD2CR_AWD2CH_Msk             (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x000FFFFF */
+#define ADC_AWD2CR_AWD2CH                 ADC_AWD2CR_AWD2CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */
+#define ADC_AWD2CR_AWD2CH_0               (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000001 */
+#define ADC_AWD2CR_AWD2CH_1               (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000002 */
+#define ADC_AWD2CR_AWD2CH_2               (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000004 */
+#define ADC_AWD2CR_AWD2CH_3               (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000008 */
+#define ADC_AWD2CR_AWD2CH_4               (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000010 */
+#define ADC_AWD2CR_AWD2CH_5               (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000020 */
+#define ADC_AWD2CR_AWD2CH_6               (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000040 */
+#define ADC_AWD2CR_AWD2CH_7               (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000080 */
+#define ADC_AWD2CR_AWD2CH_8               (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000100 */
+#define ADC_AWD2CR_AWD2CH_9               (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000200 */
+#define ADC_AWD2CR_AWD2CH_10              (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000400 */
+#define ADC_AWD2CR_AWD2CH_11              (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000800 */
+#define ADC_AWD2CR_AWD2CH_12              (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00001000 */
+#define ADC_AWD2CR_AWD2CH_13              (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00002000 */
+#define ADC_AWD2CR_AWD2CH_14              (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00004000 */
+#define ADC_AWD2CR_AWD2CH_15              (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00008000 */
+#define ADC_AWD2CR_AWD2CH_16              (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00010000 */
+#define ADC_AWD2CR_AWD2CH_17              (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00020000 */
+#define ADC_AWD2CR_AWD2CH_18              (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00040000 */
+#define ADC_AWD2CR_AWD2CH_19              (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00080000 */
+
+/********************  Bit definition for ADC_AWD3CR register  ********************/
+#define ADC_AWD3CR_AWD3CH_Pos             (0U)
+#define ADC_AWD3CR_AWD3CH_Msk             (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x000FFFFF */
+#define ADC_AWD3CR_AWD3CH                 ADC_AWD3CR_AWD3CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */
+#define ADC_AWD3CR_AWD3CH_0               (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000001 */
+#define ADC_AWD3CR_AWD3CH_1               (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000002 */
+#define ADC_AWD3CR_AWD3CH_2               (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000004 */
+#define ADC_AWD3CR_AWD3CH_3               (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000008 */
+#define ADC_AWD3CR_AWD3CH_4               (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000010 */
+#define ADC_AWD3CR_AWD3CH_5               (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000020 */
+#define ADC_AWD3CR_AWD3CH_6               (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000040 */
+#define ADC_AWD3CR_AWD3CH_7               (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000080 */
+#define ADC_AWD3CR_AWD3CH_8               (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000100 */
+#define ADC_AWD3CR_AWD3CH_9               (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000200 */
+#define ADC_AWD3CR_AWD3CH_10              (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000400 */
+#define ADC_AWD3CR_AWD3CH_11              (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000800 */
+#define ADC_AWD3CR_AWD3CH_12              (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00001000 */
+#define ADC_AWD3CR_AWD3CH_13              (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00002000 */
+#define ADC_AWD3CR_AWD3CH_14              (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00004000 */
+#define ADC_AWD3CR_AWD3CH_15              (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00008000 */
+#define ADC_AWD3CR_AWD3CH_16              (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00010000 */
+#define ADC_AWD3CR_AWD3CH_17              (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00020000 */
+#define ADC_AWD3CR_AWD3CH_18              (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00040000 */
+#define ADC_AWD3CR_AWD3CH_19              (0x80000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00080000 */
+
+/********************  Bit definition for ADC_DIFSEL register  ********************/
+#define ADC_DIFSEL_DIFSEL_Pos             (0U)
+#define ADC_DIFSEL_DIFSEL_Msk             (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x000FFFFF */
+#define ADC_DIFSEL_DIFSEL                 ADC_DIFSEL_DIFSEL_Msk                 /*!< ADC differential modes for channels 1 to 18 */
+#define ADC_DIFSEL_DIFSEL_0               (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000001 */
+#define ADC_DIFSEL_DIFSEL_1               (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000002 */
+#define ADC_DIFSEL_DIFSEL_2               (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000004 */
+#define ADC_DIFSEL_DIFSEL_3               (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000008 */
+#define ADC_DIFSEL_DIFSEL_4               (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000010 */
+#define ADC_DIFSEL_DIFSEL_5               (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000020 */
+#define ADC_DIFSEL_DIFSEL_6               (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000040 */
+#define ADC_DIFSEL_DIFSEL_7               (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000080 */
+#define ADC_DIFSEL_DIFSEL_8               (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000100 */
+#define ADC_DIFSEL_DIFSEL_9               (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000200 */
+#define ADC_DIFSEL_DIFSEL_10              (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000400 */
+#define ADC_DIFSEL_DIFSEL_11              (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000800 */
+#define ADC_DIFSEL_DIFSEL_12              (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00001000 */
+#define ADC_DIFSEL_DIFSEL_13              (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00002000 */
+#define ADC_DIFSEL_DIFSEL_14              (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00004000 */
+#define ADC_DIFSEL_DIFSEL_15              (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00008000 */
+#define ADC_DIFSEL_DIFSEL_16              (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00010000 */
+#define ADC_DIFSEL_DIFSEL_17              (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00020000 */
+#define ADC_DIFSEL_DIFSEL_18              (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00040000 */
+#define ADC_DIFSEL_DIFSEL_19              (0x80000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00080000 */
+
+/********************  Bit definition for ADC_CALFACT register  ********************/
+#define ADC_CALFACT_CALFACT_S_Pos         (0U)
+#define ADC_CALFACT_CALFACT_S_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */
+#define ADC_CALFACT_CALFACT_S             ADC_CALFACT_CALFACT_S_Msk              /*!< ADC calibration factors in single-ended mode */
+#define ADC_CALFACT_CALFACT_S_0           (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
+#define ADC_CALFACT_CALFACT_S_1           (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
+#define ADC_CALFACT_CALFACT_S_2           (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
+#define ADC_CALFACT_CALFACT_S_3           (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
+#define ADC_CALFACT_CALFACT_S_4           (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
+#define ADC_CALFACT_CALFACT_S_5           (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
+#define ADC_CALFACT_CALFACT_S_6           (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
+#define ADC_CALFACT_CALFACT_S_7           (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */
+#define ADC_CALFACT_CALFACT_S_8           (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */
+#define ADC_CALFACT_CALFACT_S_9           (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */
+#define ADC_CALFACT_CALFACT_S_10          (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */
+#define ADC_CALFACT_CALFACT_D_Pos         (16U)
+#define ADC_CALFACT_CALFACT_D_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */
+#define ADC_CALFACT_CALFACT_D             ADC_CALFACT_CALFACT_D_Msk              /*!< ADC calibration factors in differential mode */
+#define ADC_CALFACT_CALFACT_D_0           (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
+#define ADC_CALFACT_CALFACT_D_1           (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
+#define ADC_CALFACT_CALFACT_D_2           (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
+#define ADC_CALFACT_CALFACT_D_3           (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
+#define ADC_CALFACT_CALFACT_D_4           (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
+#define ADC_CALFACT_CALFACT_D_5           (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
+#define ADC_CALFACT_CALFACT_D_6           (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
+#define ADC_CALFACT_CALFACT_D_7           (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */
+#define ADC_CALFACT_CALFACT_D_8           (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */
+#define ADC_CALFACT_CALFACT_D_9           (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */
+#define ADC_CALFACT_CALFACT_D_10          (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */
+
+/********************  Bit definition for ADC_CALFACT2 register  ********************/
+#define ADC_CALFACT2_LINCALFACT_Pos       (0U)
+#define ADC_CALFACT2_LINCALFACT_Msk       (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */
+#define ADC_CALFACT2_LINCALFACT           ADC_CALFACT2_LINCALFACT_Msk                   /*!< ADC Linearity calibration factors */
+#define ADC_CALFACT2_LINCALFACT_0         (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */
+#define ADC_CALFACT2_LINCALFACT_1         (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */
+#define ADC_CALFACT2_LINCALFACT_2         (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */
+#define ADC_CALFACT2_LINCALFACT_3         (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */
+#define ADC_CALFACT2_LINCALFACT_4         (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */
+#define ADC_CALFACT2_LINCALFACT_5         (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */
+#define ADC_CALFACT2_LINCALFACT_6         (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */
+#define ADC_CALFACT2_LINCALFACT_7         (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */
+#define ADC_CALFACT2_LINCALFACT_8         (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */
+#define ADC_CALFACT2_LINCALFACT_9         (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */
+#define ADC_CALFACT2_LINCALFACT_10        (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */
+#define ADC_CALFACT2_LINCALFACT_11        (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */
+#define ADC_CALFACT2_LINCALFACT_12        (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */
+#define ADC_CALFACT2_LINCALFACT_13        (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */
+#define ADC_CALFACT2_LINCALFACT_14        (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */
+#define ADC_CALFACT2_LINCALFACT_15        (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */
+#define ADC_CALFACT2_LINCALFACT_16        (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */
+#define ADC_CALFACT2_LINCALFACT_17        (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */
+#define ADC_CALFACT2_LINCALFACT_18        (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */
+#define ADC_CALFACT2_LINCALFACT_19        (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */
+#define ADC_CALFACT2_LINCALFACT_20        (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */
+#define ADC_CALFACT2_LINCALFACT_21        (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */
+#define ADC_CALFACT2_LINCALFACT_22        (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */
+#define ADC_CALFACT2_LINCALFACT_23        (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */
+#define ADC_CALFACT2_LINCALFACT_24        (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */
+#define ADC_CALFACT2_LINCALFACT_25        (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */
+#define ADC_CALFACT2_LINCALFACT_26        (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */
+#define ADC_CALFACT2_LINCALFACT_27        (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */
+#define ADC_CALFACT2_LINCALFACT_28        (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */
+#define ADC_CALFACT2_LINCALFACT_29        (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */
+
+/*************************  ADC Common registers  *****************************/
+/********************  Bit definition for ADC_CSR register  ********************/
+#define ADC_CSR_ADRDY_MST_Pos             (0U)
+#define ADC_CSR_ADRDY_MST_Msk             (0x1UL << ADC_CSR_ADRDY_MST_Pos)     /*!< 0x00000001 */
+#define ADC_CSR_ADRDY_MST                 ADC_CSR_ADRDY_MST_Msk                /*!< Master ADC ready */
+#define ADC_CSR_EOSMP_MST_Pos             (1U)
+#define ADC_CSR_EOSMP_MST_Msk             (0x1UL << ADC_CSR_EOSMP_MST_Pos)     /*!< 0x00000002 */
+#define ADC_CSR_EOSMP_MST                 ADC_CSR_EOSMP_MST_Msk                /*!< End of sampling phase flag of the master ADC */
+#define ADC_CSR_EOC_MST_Pos               (2U)
+#define ADC_CSR_EOC_MST_Msk               (0x1UL << ADC_CSR_EOC_MST_Pos)       /*!< 0x00000004 */
+#define ADC_CSR_EOC_MST                   ADC_CSR_EOC_MST_Msk                  /*!< End of regular conversion of the master ADC */
+#define ADC_CSR_EOS_MST_Pos               (3U)
+#define ADC_CSR_EOS_MST_Msk               (0x1UL << ADC_CSR_EOS_MST_Pos)       /*!< 0x00000008 */
+#define ADC_CSR_EOS_MST                   ADC_CSR_EOS_MST_Msk                  /*!< End of regular sequence flag of the master ADC */
+#define ADC_CSR_OVR_MST_Pos               (4U)
+#define ADC_CSR_OVR_MST_Msk               (0x1UL << ADC_CSR_OVR_MST_Pos)       /*!< 0x00000010 */
+#define ADC_CSR_OVR_MST                   ADC_CSR_OVR_MST_Msk                  /*!< Overrun flag of the master ADC */
+#define ADC_CSR_JEOC_MST_Pos              (5U)
+#define ADC_CSR_JEOC_MST_Msk              (0x1UL << ADC_CSR_JEOC_MST_Pos)      /*!< 0x00000020 */
+#define ADC_CSR_JEOC_MST                  ADC_CSR_JEOC_MST_Msk                 /*!< End of injected conversion of the master ADC */
+#define ADC_CSR_JEOS_MST_Pos              (6U)
+#define ADC_CSR_JEOS_MST_Msk              (0x1UL << ADC_CSR_JEOS_MST_Pos)      /*!< 0x00000040 */
+#define ADC_CSR_JEOS_MST                  ADC_CSR_JEOS_MST_Msk                 /*!< End of injected sequence flag of the master ADC */
+#define ADC_CSR_AWD1_MST_Pos              (7U)
+#define ADC_CSR_AWD1_MST_Msk              (0x1UL << ADC_CSR_AWD1_MST_Pos)      /*!< 0x00000080 */
+#define ADC_CSR_AWD1_MST                  ADC_CSR_AWD1_MST_Msk                 /*!< Analog watchdog 1 flag of the master ADC */
+#define ADC_CSR_AWD2_MST_Pos              (8U)
+#define ADC_CSR_AWD2_MST_Msk              (0x1UL << ADC_CSR_AWD2_MST_Pos)      /*!< 0x00000100 */
+#define ADC_CSR_AWD2_MST                  ADC_CSR_AWD2_MST_Msk                 /*!< Analog watchdog 2 flag of the master ADC */
+#define ADC_CSR_AWD3_MST_Pos              (9U)
+#define ADC_CSR_AWD3_MST_Msk              (0x1UL << ADC_CSR_AWD3_MST_Pos)      /*!< 0x00000200 */
+#define ADC_CSR_AWD3_MST                  ADC_CSR_AWD3_MST_Msk                 /*!< Analog watchdog 3 flag of the master ADC */
+#define ADC_CSR_JQOVF_MST_Pos             (10U)
+#define ADC_CSR_JQOVF_MST_Msk             (0x1UL << ADC_CSR_JQOVF_MST_Pos)     /*!< 0x00000400 */
+#define ADC_CSR_JQOVF_MST                 ADC_CSR_JQOVF_MST_Msk                /*!< Injected context queue overflow flag of the master ADC */
+#define ADC_CSR_ADRDY_SLV_Pos             (16U)
+#define ADC_CSR_ADRDY_SLV_Msk             (0x1UL << ADC_CSR_ADRDY_SLV_Pos)     /*!< 0x00010000 */
+#define ADC_CSR_ADRDY_SLV                 ADC_CSR_ADRDY_SLV_Msk                /*!< Slave ADC ready */
+#define ADC_CSR_EOSMP_SLV_Pos             (17U)
+#define ADC_CSR_EOSMP_SLV_Msk             (0x1UL << ADC_CSR_EOSMP_SLV_Pos)     /*!< 0x00020000 */
+#define ADC_CSR_EOSMP_SLV                 ADC_CSR_EOSMP_SLV_Msk                /*!< End of sampling phase flag of the slave ADC */
+#define ADC_CSR_EOC_SLV_Pos               (18U)
+#define ADC_CSR_EOC_SLV_Msk               (0x1UL << ADC_CSR_EOC_SLV_Pos)       /*!< 0x00040000 */
+#define ADC_CSR_EOC_SLV                   ADC_CSR_EOC_SLV_Msk                  /*!< End of regular conversion of the slave ADC */
+#define ADC_CSR_EOS_SLV_Pos               (19U)
+#define ADC_CSR_EOS_SLV_Msk               (0x1UL << ADC_CSR_EOS_SLV_Pos)       /*!< 0x00080000 */
+#define ADC_CSR_EOS_SLV                   ADC_CSR_EOS_SLV_Msk                  /*!< End of regular sequence flag of the slave ADC */
+#define ADC_CSR_OVR_SLV_Pos               (20U)
+#define ADC_CSR_OVR_SLV_Msk               (0x1UL << ADC_CSR_OVR_SLV_Pos)       /*!< 0x00100000 */
+#define ADC_CSR_OVR_SLV                   ADC_CSR_OVR_SLV_Msk                  /*!< Overrun flag of the slave ADC */
+#define ADC_CSR_JEOC_SLV_Pos              (21U)
+#define ADC_CSR_JEOC_SLV_Msk              (0x1UL << ADC_CSR_JEOC_SLV_Pos)      /*!< 0x00200000 */
+#define ADC_CSR_JEOC_SLV                  ADC_CSR_JEOC_SLV_Msk                 /*!< End of injected conversion of the slave ADC */
+#define ADC_CSR_JEOS_SLV_Pos              (22U)
+#define ADC_CSR_JEOS_SLV_Msk              (0x1UL << ADC_CSR_JEOS_SLV_Pos)      /*!< 0x00400000 */
+#define ADC_CSR_JEOS_SLV                  ADC_CSR_JEOS_SLV_Msk                 /*!< End of injected sequence flag of the slave ADC */
+#define ADC_CSR_AWD1_SLV_Pos              (23U)
+#define ADC_CSR_AWD1_SLV_Msk              (0x1UL << ADC_CSR_AWD1_SLV_Pos)      /*!< 0x00800000 */
+#define ADC_CSR_AWD1_SLV                  ADC_CSR_AWD1_SLV_Msk                 /*!< Analog watchdog 1 flag of the slave ADC */
+#define ADC_CSR_AWD2_SLV_Pos              (24U)
+#define ADC_CSR_AWD2_SLV_Msk              (0x1UL << ADC_CSR_AWD2_SLV_Pos)      /*!< 0x01000000 */
+#define ADC_CSR_AWD2_SLV                  ADC_CSR_AWD2_SLV_Msk                 /*!< Analog watchdog 2 flag of the slave ADC */
+#define ADC_CSR_AWD3_SLV_Pos              (25U)
+#define ADC_CSR_AWD3_SLV_Msk              (0x1UL << ADC_CSR_AWD3_SLV_Pos)      /*!< 0x02000000 */
+#define ADC_CSR_AWD3_SLV                  ADC_CSR_AWD3_SLV_Msk                 /*!< Analog watchdog 3 flag of the slave ADC */
+#define ADC_CSR_JQOVF_SLV_Pos             (26U)
+#define ADC_CSR_JQOVF_SLV_Msk             (0x1UL << ADC_CSR_JQOVF_SLV_Pos)     /*!< 0x04000000 */
+#define ADC_CSR_JQOVF_SLV                 ADC_CSR_JQOVF_SLV_Msk                /*!< Injected context queue overflow flag of the slave ADC */
+
+/********************  Bit definition for ADC_CCR register  ********************/
+#define ADC_CCR_DUAL_Pos                  (0U)
+#define ADC_CCR_DUAL_Msk                  (0x1FUL << ADC_CCR_DUAL_Pos)          /*!< 0x0000001F */
+#define ADC_CCR_DUAL                      ADC_CCR_DUAL_Msk                      /*!< Dual ADC mode selection */
+#define ADC_CCR_DUAL_0                    (0x01UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000001 */
+#define ADC_CCR_DUAL_1                    (0x02UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000002 */
+#define ADC_CCR_DUAL_2                    (0x04UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000004 */
+#define ADC_CCR_DUAL_3                    (0x08UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000008 */
+#define ADC_CCR_DUAL_4                    (0x10UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000010 */
+
+#define ADC_CCR_DELAY_Pos                 (8U)
+#define ADC_CCR_DELAY_Msk                 (0xFUL << ADC_CCR_DELAY_Pos)          /*!< 0x00000F00 */
+#define ADC_CCR_DELAY                     ADC_CCR_DELAY_Msk                     /*!< Delay between 2 sampling phases */
+#define ADC_CCR_DELAY_0                   (0x1UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000100 */
+#define ADC_CCR_DELAY_1                   (0x2UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000200 */
+#define ADC_CCR_DELAY_2                   (0x4UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000400 */
+#define ADC_CCR_DELAY_3                   (0x8UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000800 */
+
+
+#define ADC_CCR_DAMDF_Pos                 (14U)
+#define ADC_CCR_DAMDF_Msk                 (0x3UL << ADC_CCR_DAMDF_Pos)          /*!< 0x0000C000 */
+#define ADC_CCR_DAMDF                     ADC_CCR_DAMDF_Msk                     /*!< Dual ADC mode Data format */
+#define ADC_CCR_DAMDF_0                   (0x1UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00004000 */
+#define ADC_CCR_DAMDF_1                   (0x2UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00008000 */
+
+#define ADC_CCR_CKMODE_Pos                (16U)
+#define ADC_CCR_CKMODE_Msk                (0x3UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00030000 */
+#define ADC_CCR_CKMODE                    ADC_CCR_CKMODE_Msk                    /*!< ADC clock mode */
+#define ADC_CCR_CKMODE_0                  (0x1UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00010000 */
+#define ADC_CCR_CKMODE_1                  (0x2UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00020000 */
+
+#define ADC_CCR_PRESC_Pos                 (18U)
+#define ADC_CCR_PRESC_Msk                 (0xFUL << ADC_CCR_PRESC_Pos)          /*!< 0x003C0000 */
+#define ADC_CCR_PRESC                     ADC_CCR_PRESC_Msk                     /*!< ADC prescaler */
+#define ADC_CCR_PRESC_0                   (0x1UL << ADC_CCR_PRESC_Pos)          /*!< 0x00040000 */
+#define ADC_CCR_PRESC_1                   (0x2UL << ADC_CCR_PRESC_Pos)          /*!< 0x00080000 */
+#define ADC_CCR_PRESC_2                   (0x4UL << ADC_CCR_PRESC_Pos)          /*!< 0x00100000 */
+#define ADC_CCR_PRESC_3                   (0x8UL << ADC_CCR_PRESC_Pos)          /*!< 0x00200000 */
+
+#define ADC_CCR_VREFEN_Pos                (22U)
+#define ADC_CCR_VREFEN_Msk                (0x1UL << ADC_CCR_VREFEN_Pos)         /*!< 0x00400000 */
+#define ADC_CCR_VREFEN                    ADC_CCR_VREFEN_Msk                    /*!< VREFINT enable */
+#define ADC_CCR_TSEN_Pos                  (23U)
+#define ADC_CCR_TSEN_Msk                  (0x1UL << ADC_CCR_TSEN_Pos)           /*!< 0x00800000 */
+#define ADC_CCR_TSEN                      ADC_CCR_TSEN_Msk                      /*!< Temperature sensor enable */
+#define ADC_CCR_VBATEN_Pos                (24U)
+#define ADC_CCR_VBATEN_Msk                (0x1UL << ADC_CCR_VBATEN_Pos)         /*!< 0x01000000 */
+#define ADC_CCR_VBATEN                    ADC_CCR_VBATEN_Msk                    /*!< VBAT enable */
+
+/********************  Bit definition for ADC_CDR register  *******************/
+#define ADC_CDR_RDATA_MST_Pos             (0U)
+#define ADC_CDR_RDATA_MST_Msk             (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)   /*!< 0x0000FFFF */
+#define ADC_CDR_RDATA_MST                 ADC_CDR_RDATA_MST_Msk                 /*!< ADC multimode master group regular conversion data */
+
+#define ADC_CDR_RDATA_SLV_Pos             (16U)
+#define ADC_CDR_RDATA_SLV_Msk             (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)   /*!< 0xFFFF0000 */
+#define ADC_CDR_RDATA_SLV                 ADC_CDR_RDATA_SLV_Msk                 /*!< ADC multimode slave group regular conversion data */
+
+/********************  Bit definition for ADC_CDR2 register  ******************/
+#define ADC_CDR2_RDATA_ALT_Pos            (0U)
+#define ADC_CDR2_RDATA_ALT_Msk            (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */
+#define ADC_CDR2_RDATA_ALT                ADC_CDR2_RDATA_ALT_Msk                   /*!< Regular data of the master/slave alternated ADCs */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                   VREFBUF                                  */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for VREFBUF_CSR register  ****************/
+#define VREFBUF_CSR_ENVR_Pos        (0U)
+#define VREFBUF_CSR_ENVR_Msk        (0x1UL << VREFBUF_CSR_ENVR_Pos)            /*!< 0x00000001 */
+#define VREFBUF_CSR_ENVR            VREFBUF_CSR_ENVR_Msk                       /*!<Voltage reference buffer enable */
+#define VREFBUF_CSR_HIZ_Pos         (1U)
+#define VREFBUF_CSR_HIZ_Msk         (0x1UL << VREFBUF_CSR_HIZ_Pos)             /*!< 0x00000002 */
+#define VREFBUF_CSR_HIZ             VREFBUF_CSR_HIZ_Msk                        /*!<High impedance mode             */
+#define VREFBUF_CSR_VRR_Pos         (3U)
+#define VREFBUF_CSR_VRR_Msk         (0x1UL << VREFBUF_CSR_VRR_Pos)             /*!< 0x00000008 */
+#define VREFBUF_CSR_VRR             VREFBUF_CSR_VRR_Msk                        /*!<Voltage reference buffer ready  */
+#define VREFBUF_CSR_VRS_Pos         (4U)
+#define VREFBUF_CSR_VRS_Msk         (0x7UL << VREFBUF_CSR_VRS_Pos)             /*!< 0x00000070 */
+#define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */
+
+#define VREFBUF_CSR_VRS_OUT1        ((uint32_t)0x00000000)                     /*!<Voltage reference VREF_OUT1     */
+#define VREFBUF_CSR_VRS_OUT2_Pos    (4U)
+#define VREFBUF_CSR_VRS_OUT2_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)        /*!< 0x00000010 */
+#define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */
+#define VREFBUF_CSR_VRS_OUT3_Pos    (5U)
+#define VREFBUF_CSR_VRS_OUT3_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT3_Pos)        /*!< 0x00000020 */
+#define VREFBUF_CSR_VRS_OUT3        VREFBUF_CSR_VRS_OUT3_Msk                   /*!<Voltage reference VREF_OUT3     */
+#define VREFBUF_CSR_VRS_OUT4_Pos    (4U)
+#define VREFBUF_CSR_VRS_OUT4_Msk    (0x3UL << VREFBUF_CSR_VRS_OUT4_Pos)        /*!< 0x00000030 */
+#define VREFBUF_CSR_VRS_OUT4        VREFBUF_CSR_VRS_OUT4_Msk                   /*!<Voltage reference VREF_OUT4     */
+
+/*******************  Bit definition for VREFBUF_CCR register  ****************/
+#define VREFBUF_CCR_TRIM_Pos        (0U)
+#define VREFBUF_CCR_TRIM_Msk        (0x3FUL << VREFBUF_CCR_TRIM_Pos)           /*!< 0x0000003F */
+#define VREFBUF_CCR_TRIM            VREFBUF_CCR_TRIM_Msk                       /*!<TRIM[5:0] bits (Trimming code)  */
+
+/******************************************************************************/
+/*                                                                            */
+/*                 Flexible Datarate Controller Area Network                  */
+/*                                                                            */
+/******************************************************************************/
+/*!<FDCAN control and status registers */
+/*****************  Bit definition for FDCAN_CREL register  *******************/
+#define FDCAN_CREL_DAY_Pos        (0U)
+#define FDCAN_CREL_DAY_Msk        (0xFFUL << FDCAN_CREL_DAY_Pos)               /*!< 0x000000FF */
+#define FDCAN_CREL_DAY            FDCAN_CREL_DAY_Msk                           /*!<Timestamp Day                           */
+#define FDCAN_CREL_MON_Pos        (8U)
+#define FDCAN_CREL_MON_Msk        (0xFFUL << FDCAN_CREL_MON_Pos)               /*!< 0x0000FF00 */
+#define FDCAN_CREL_MON            FDCAN_CREL_MON_Msk                           /*!<Timestamp Month                         */
+#define FDCAN_CREL_YEAR_Pos       (16U)
+#define FDCAN_CREL_YEAR_Msk       (0xFUL << FDCAN_CREL_YEAR_Pos)               /*!< 0x000F0000 */
+#define FDCAN_CREL_YEAR           FDCAN_CREL_YEAR_Msk                          /*!<Timestamp Year                          */
+#define FDCAN_CREL_SUBSTEP_Pos    (20U)
+#define FDCAN_CREL_SUBSTEP_Msk    (0xFUL << FDCAN_CREL_SUBSTEP_Pos)            /*!< 0x00F00000 */
+#define FDCAN_CREL_SUBSTEP        FDCAN_CREL_SUBSTEP_Msk                       /*!<Sub-step of Core release                */
+#define FDCAN_CREL_STEP_Pos       (24U)
+#define FDCAN_CREL_STEP_Msk       (0xFUL << FDCAN_CREL_STEP_Pos)               /*!< 0x0F000000 */
+#define FDCAN_CREL_STEP           FDCAN_CREL_STEP_Msk                          /*!<Step of Core release                    */
+#define FDCAN_CREL_REL_Pos        (28U)
+#define FDCAN_CREL_REL_Msk        (0xFUL << FDCAN_CREL_REL_Pos)                /*!< 0xF0000000 */
+#define FDCAN_CREL_REL            FDCAN_CREL_REL_Msk                           /*!<Core release                            */
+
+/*****************  Bit definition for FDCAN_ENDN register  *******************/
+#define FDCAN_ENDN_ETV_Pos        (0U)
+#define FDCAN_ENDN_ETV_Msk        (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)         /*!< 0xFFFFFFFF */
+#define FDCAN_ENDN_ETV            FDCAN_ENDN_ETV_Msk                           /*!<Endiannes Test Value                    */
+
+/*****************  Bit definition for FDCAN_DBTP register  *******************/
+#define FDCAN_DBTP_DSJW_Pos       (0U)
+#define FDCAN_DBTP_DSJW_Msk       (0xFUL << FDCAN_DBTP_DSJW_Pos)               /*!< 0x0000000F */
+#define FDCAN_DBTP_DSJW           FDCAN_DBTP_DSJW_Msk                          /*!<Synchronization Jump Width              */
+#define FDCAN_DBTP_DTSEG2_Pos     (4U)
+#define FDCAN_DBTP_DTSEG2_Msk     (0xFUL << FDCAN_DBTP_DTSEG2_Pos)             /*!< 0x000000F0 */
+#define FDCAN_DBTP_DTSEG2         FDCAN_DBTP_DTSEG2_Msk                        /*!<Data time segment after sample point    */
+#define FDCAN_DBTP_DTSEG1_Pos     (8U)
+#define FDCAN_DBTP_DTSEG1_Msk     (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)            /*!< 0x00001F00 */
+#define FDCAN_DBTP_DTSEG1         FDCAN_DBTP_DTSEG1_Msk                        /*!<Data time segment before sample point   */
+#define FDCAN_DBTP_DBRP_Pos       (16U)
+#define FDCAN_DBTP_DBRP_Msk       (0x1FUL << FDCAN_DBTP_DBRP_Pos)              /*!< 0x001F0000 */
+#define FDCAN_DBTP_DBRP           FDCAN_DBTP_DBRP_Msk                          /*!<Data BIt Rate Prescaler                 */
+#define FDCAN_DBTP_TDC_Pos        (23U)
+#define FDCAN_DBTP_TDC_Msk        (0x1UL << FDCAN_DBTP_TDC_Pos)                /*!< 0x00800000 */
+#define FDCAN_DBTP_TDC            FDCAN_DBTP_TDC_Msk                           /*!<Transceiver Delay Compensation          */
+
+/*****************  Bit definition for FDCAN_TEST register  *******************/
+#define FDCAN_TEST_LBCK_Pos       (4U)
+#define FDCAN_TEST_LBCK_Msk       (0x1UL << FDCAN_TEST_LBCK_Pos)               /*!< 0x00000010 */
+#define FDCAN_TEST_LBCK           FDCAN_TEST_LBCK_Msk                          /*!<Loop Back mode                           */
+#define FDCAN_TEST_TX_Pos         (5U)
+#define FDCAN_TEST_TX_Msk         (0x3UL << FDCAN_TEST_TX_Pos)                 /*!< 0x00000060 */
+#define FDCAN_TEST_TX             FDCAN_TEST_TX_Msk                            /*!<Control of Transmit Pin                  */
+#define FDCAN_TEST_RX_Pos         (7U)
+#define FDCAN_TEST_RX_Msk         (0x1UL << FDCAN_TEST_RX_Pos)                 /*!< 0x00000080 */
+#define FDCAN_TEST_RX             FDCAN_TEST_RX_Msk                            /*!<Receive Pin                              */
+
+/*****************  Bit definition for FDCAN_RWD register  ********************/
+#define FDCAN_RWD_WDC_Pos         (0U)
+#define FDCAN_RWD_WDC_Msk         (0xFFUL << FDCAN_RWD_WDC_Pos)                /*!< 0x000000FF */
+#define FDCAN_RWD_WDC             FDCAN_RWD_WDC_Msk                            /*!<Watchdog configuration                   */
+#define FDCAN_RWD_WDV_Pos         (8U)
+#define FDCAN_RWD_WDV_Msk         (0xFFUL << FDCAN_RWD_WDV_Pos)                /*!< 0x0000FF00 */
+#define FDCAN_RWD_WDV             FDCAN_RWD_WDV_Msk                            /*!<Watchdog value                           */
+
+/*****************  Bit definition for FDCAN_CCCR register  ********************/
+#define FDCAN_CCCR_INIT_Pos       (0U)
+#define FDCAN_CCCR_INIT_Msk       (0x1UL << FDCAN_CCCR_INIT_Pos)               /*!< 0x00000001 */
+#define FDCAN_CCCR_INIT           FDCAN_CCCR_INIT_Msk                          /*!<Initialization                           */
+#define FDCAN_CCCR_CCE_Pos        (1U)
+#define FDCAN_CCCR_CCE_Msk        (0x1UL << FDCAN_CCCR_CCE_Pos)                /*!< 0x00000002 */
+#define FDCAN_CCCR_CCE            FDCAN_CCCR_CCE_Msk                           /*!<Configuration Change Enable              */
+#define FDCAN_CCCR_ASM_Pos        (2U)
+#define FDCAN_CCCR_ASM_Msk        (0x1UL << FDCAN_CCCR_ASM_Pos)                /*!< 0x00000004 */
+#define FDCAN_CCCR_ASM            FDCAN_CCCR_ASM_Msk                           /*!<ASM Restricted Operation Mode            */
+#define FDCAN_CCCR_CSA_Pos        (3U)
+#define FDCAN_CCCR_CSA_Msk        (0x1UL << FDCAN_CCCR_CSA_Pos)                /*!< 0x00000008 */
+#define FDCAN_CCCR_CSA            FDCAN_CCCR_CSA_Msk                           /*!<Clock Stop Acknowledge                   */
+#define FDCAN_CCCR_CSR_Pos        (4U)
+#define FDCAN_CCCR_CSR_Msk        (0x1UL << FDCAN_CCCR_CSR_Pos)                /*!< 0x00000010 */
+#define FDCAN_CCCR_CSR            FDCAN_CCCR_CSR_Msk                           /*!<Clock Stop Request                       */
+#define FDCAN_CCCR_MON_Pos        (5U)
+#define FDCAN_CCCR_MON_Msk        (0x1UL << FDCAN_CCCR_MON_Pos)                /*!< 0x00000020 */
+#define FDCAN_CCCR_MON            FDCAN_CCCR_MON_Msk                           /*!<Bus Monitoring Mode                      */
+#define FDCAN_CCCR_DAR_Pos        (6U)
+#define FDCAN_CCCR_DAR_Msk        (0x1UL << FDCAN_CCCR_DAR_Pos)                /*!< 0x00000040 */
+#define FDCAN_CCCR_DAR            FDCAN_CCCR_DAR_Msk                           /*!<Disable Automatic Retransmission         */
+#define FDCAN_CCCR_TEST_Pos       (7U)
+#define FDCAN_CCCR_TEST_Msk       (0x1UL << FDCAN_CCCR_TEST_Pos)               /*!< 0x00000080 */
+#define FDCAN_CCCR_TEST           FDCAN_CCCR_TEST_Msk                          /*!<Test Mode Enable                         */
+#define FDCAN_CCCR_FDOE_Pos       (8U)
+#define FDCAN_CCCR_FDOE_Msk       (0x1UL << FDCAN_CCCR_FDOE_Pos)               /*!< 0x00000100 */
+#define FDCAN_CCCR_FDOE           FDCAN_CCCR_FDOE_Msk                          /*!<FD Operation Enable                      */
+#define FDCAN_CCCR_BRSE_Pos       (9U)
+#define FDCAN_CCCR_BRSE_Msk       (0x1UL << FDCAN_CCCR_BRSE_Pos)               /*!< 0x00000200 */
+#define FDCAN_CCCR_BRSE           FDCAN_CCCR_BRSE_Msk                          /*!<FDCAN Bit Rate Switching                 */
+#define FDCAN_CCCR_PXHD_Pos       (12U)
+#define FDCAN_CCCR_PXHD_Msk       (0x1UL << FDCAN_CCCR_PXHD_Pos)               /*!< 0x00001000 */
+#define FDCAN_CCCR_PXHD           FDCAN_CCCR_PXHD_Msk                          /*!<Protocol Exception Handling Disable      */
+#define FDCAN_CCCR_EFBI_Pos       (13U)
+#define FDCAN_CCCR_EFBI_Msk       (0x1UL << FDCAN_CCCR_EFBI_Pos)               /*!< 0x00002000 */
+#define FDCAN_CCCR_EFBI           FDCAN_CCCR_EFBI_Msk                          /*!<Edge Filtering during Bus Integration    */
+#define FDCAN_CCCR_TXP_Pos        (14U)
+#define FDCAN_CCCR_TXP_Msk        (0x1UL << FDCAN_CCCR_TXP_Pos)                /*!< 0x00004000 */
+#define FDCAN_CCCR_TXP            FDCAN_CCCR_TXP_Msk                           /*!<Two CAN bit times Pause                  */
+#define FDCAN_CCCR_NISO_Pos       (15U)
+#define FDCAN_CCCR_NISO_Msk       (0x1UL << FDCAN_CCCR_NISO_Pos)               /*!< 0x00008000 */
+#define FDCAN_CCCR_NISO           FDCAN_CCCR_NISO_Msk                          /*!<Non ISO Operation                        */
+
+/*****************  Bit definition for FDCAN_NBTP register  ********************/
+#define FDCAN_NBTP_NTSEG2_Pos     (0U)
+#define FDCAN_NBTP_NTSEG2_Msk     (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)            /*!< 0x0000007F */
+#define FDCAN_NBTP_NTSEG2         FDCAN_NBTP_NTSEG2_Msk                        /*!<Nominal Time segment after sample point  */
+#define FDCAN_NBTP_NTSEG1_Pos     (8U)
+#define FDCAN_NBTP_NTSEG1_Msk     (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)            /*!< 0x0000FF00 */
+#define FDCAN_NBTP_NTSEG1         FDCAN_NBTP_NTSEG1_Msk                        /*!<Nominal Time segment before sample point */
+#define FDCAN_NBTP_NBRP_Pos       (16U)
+#define FDCAN_NBTP_NBRP_Msk       (0x1FFUL << FDCAN_NBTP_NBRP_Pos)             /*!< 0x01FF0000 */
+#define FDCAN_NBTP_NBRP           FDCAN_NBTP_NBRP_Msk                          /*!<Bit Rate Prescaler                       */
+#define FDCAN_NBTP_NSJW_Pos       (25U)
+#define FDCAN_NBTP_NSJW_Msk       (0x7FUL << FDCAN_NBTP_NSJW_Pos)              /*!< 0xFE000000 */
+#define FDCAN_NBTP_NSJW           FDCAN_NBTP_NSJW_Msk                          /*!<Nominal (Re)Synchronization Jump Width   */
+
+/*****************  Bit definition for FDCAN_TSCC register  ********************/
+#define FDCAN_TSCC_TSS_Pos        (0U)
+#define FDCAN_TSCC_TSS_Msk        (0x3UL << FDCAN_TSCC_TSS_Pos)                /*!< 0x00000003 */
+#define FDCAN_TSCC_TSS            FDCAN_TSCC_TSS_Msk                           /*!<Timestamp Select                         */
+#define FDCAN_TSCC_TCP_Pos        (16U)
+#define FDCAN_TSCC_TCP_Msk        (0xFUL << FDCAN_TSCC_TCP_Pos)                /*!< 0x000F0000 */
+#define FDCAN_TSCC_TCP            FDCAN_TSCC_TCP_Msk                           /*!<Timestamp Counter Prescaler              */
+
+/*****************  Bit definition for FDCAN_TSCV register  ********************/
+#define FDCAN_TSCV_TSC_Pos        (0U)
+#define FDCAN_TSCV_TSC_Msk        (0xFFFFUL << FDCAN_TSCV_TSC_Pos)             /*!< 0x0000FFFF */
+#define FDCAN_TSCV_TSC            FDCAN_TSCV_TSC_Msk                           /*!<Timestamp Counter                        */
+
+/*****************  Bit definition for FDCAN_TOCC register  ********************/
+#define FDCAN_TOCC_ETOC_Pos       (0U)
+#define FDCAN_TOCC_ETOC_Msk       (0x1UL << FDCAN_TOCC_ETOC_Pos)               /*!< 0x00000001 */
+#define FDCAN_TOCC_ETOC           FDCAN_TOCC_ETOC_Msk                          /*!<Enable Timeout Counter                   */
+#define FDCAN_TOCC_TOS_Pos        (1U)
+#define FDCAN_TOCC_TOS_Msk        (0x3UL << FDCAN_TOCC_TOS_Pos)                /*!< 0x00000006 */
+#define FDCAN_TOCC_TOS            FDCAN_TOCC_TOS_Msk                           /*!<Timeout Select                           */
+#define FDCAN_TOCC_TOP_Pos        (16U)
+#define FDCAN_TOCC_TOP_Msk        (0xFFFFUL << FDCAN_TOCC_TOP_Pos)             /*!< 0xFFFF0000 */
+#define FDCAN_TOCC_TOP            FDCAN_TOCC_TOP_Msk                           /*!<Timeout Period                           */
+
+/*****************  Bit definition for FDCAN_TOCV register  ********************/
+#define FDCAN_TOCV_TOC_Pos        (0U)
+#define FDCAN_TOCV_TOC_Msk        (0xFFFFUL << FDCAN_TOCV_TOC_Pos)             /*!< 0x0000FFFF */
+#define FDCAN_TOCV_TOC            FDCAN_TOCV_TOC_Msk                           /*!<Timeout Counter                          */
+
+/*****************  Bit definition for FDCAN_ECR register  *********************/
+#define FDCAN_ECR_TEC_Pos         (0U)
+#define FDCAN_ECR_TEC_Msk         (0xFUL << FDCAN_ECR_TEC_Pos)                 /*!< 0x0000000F */
+#define FDCAN_ECR_TEC             FDCAN_ECR_TEC_Msk                            /*!<Transmit Error Counter                   */
+#define FDCAN_ECR_REC_Pos         (8U)
+#define FDCAN_ECR_REC_Msk         (0x7FUL << FDCAN_ECR_REC_Pos)                /*!< 0x00007F00 */
+#define FDCAN_ECR_REC             FDCAN_ECR_REC_Msk                            /*!<Receive Error Counter                    */
+#define FDCAN_ECR_RP_Pos          (15U)
+#define FDCAN_ECR_RP_Msk          (0x1UL << FDCAN_ECR_RP_Pos)                  /*!< 0x00008000 */
+#define FDCAN_ECR_RP              FDCAN_ECR_RP_Msk                             /*!<Receive Error Passive                    */
+#define FDCAN_ECR_CEL_Pos         (16U)
+#define FDCAN_ECR_CEL_Msk         (0xFFUL << FDCAN_ECR_CEL_Pos)                /*!< 0x00FF0000 */
+#define FDCAN_ECR_CEL             FDCAN_ECR_CEL_Msk                            /*!<CAN Error Logging                        */
+
+/*****************  Bit definition for FDCAN_PSR register  *********************/
+#define FDCAN_PSR_LEC_Pos         (0U)
+#define FDCAN_PSR_LEC_Msk         (0x7UL << FDCAN_PSR_LEC_Pos)                 /*!< 0x00000007 */
+#define FDCAN_PSR_LEC             FDCAN_PSR_LEC_Msk                            /*!<Last Error Code                          */
+#define FDCAN_PSR_ACT_Pos         (3U)
+#define FDCAN_PSR_ACT_Msk         (0x3UL << FDCAN_PSR_ACT_Pos)                 /*!< 0x00000018 */
+#define FDCAN_PSR_ACT             FDCAN_PSR_ACT_Msk                            /*!<Activity                                 */
+#define FDCAN_PSR_EP_Pos          (5U)
+#define FDCAN_PSR_EP_Msk          (0x1UL << FDCAN_PSR_EP_Pos)                  /*!< 0x00000020 */
+#define FDCAN_PSR_EP              FDCAN_PSR_EP_Msk                             /*!<Error Passive                            */
+#define FDCAN_PSR_EW_Pos          (6U)
+#define FDCAN_PSR_EW_Msk          (0x1UL << FDCAN_PSR_EW_Pos)                  /*!< 0x00000040 */
+#define FDCAN_PSR_EW              FDCAN_PSR_EW_Msk                             /*!<Warning Status                           */
+#define FDCAN_PSR_BO_Pos          (7U)
+#define FDCAN_PSR_BO_Msk          (0x1UL << FDCAN_PSR_BO_Pos)                  /*!< 0x00000080 */
+#define FDCAN_PSR_BO              FDCAN_PSR_BO_Msk                             /*!<Bus_Off Status                           */
+#define FDCAN_PSR_DLEC_Pos        (8U)
+#define FDCAN_PSR_DLEC_Msk        (0x7UL << FDCAN_PSR_DLEC_Pos)                /*!< 0x00000700 */
+#define FDCAN_PSR_DLEC            FDCAN_PSR_DLEC_Msk                           /*!<Data Last Error Code                     */
+#define FDCAN_PSR_RESI_Pos        (11U)
+#define FDCAN_PSR_RESI_Msk        (0x1UL << FDCAN_PSR_RESI_Pos)                /*!< 0x00000800 */
+#define FDCAN_PSR_RESI            FDCAN_PSR_RESI_Msk                           /*!<ESI flag of last received FDCAN Message  */
+#define FDCAN_PSR_RBRS_Pos        (12U)
+#define FDCAN_PSR_RBRS_Msk        (0x1UL << FDCAN_PSR_RBRS_Pos)                /*!< 0x00001000 */
+#define FDCAN_PSR_RBRS            FDCAN_PSR_RBRS_Msk                           /*!<BRS flag of last received FDCAN Message  */
+#define FDCAN_PSR_REDL_Pos        (13U)
+#define FDCAN_PSR_REDL_Msk        (0x1UL << FDCAN_PSR_REDL_Pos)                /*!< 0x00002000 */
+#define FDCAN_PSR_REDL            FDCAN_PSR_REDL_Msk                           /*!<Received FDCAN Message                   */
+#define FDCAN_PSR_PXE_Pos         (14U)
+#define FDCAN_PSR_PXE_Msk         (0x1UL << FDCAN_PSR_PXE_Pos)                 /*!< 0x00004000 */
+#define FDCAN_PSR_PXE             FDCAN_PSR_PXE_Msk                            /*!<Protocol Exception Event                 */
+#define FDCAN_PSR_TDCV_Pos        (16U)
+#define FDCAN_PSR_TDCV_Msk        (0x7FUL << FDCAN_PSR_TDCV_Pos)               /*!< 0x007F0000 */
+#define FDCAN_PSR_TDCV            FDCAN_PSR_TDCV_Msk                           /*!<Transmitter Delay Compensation Value     */
+
+/*****************  Bit definition for FDCAN_TDCR register  ********************/
+#define FDCAN_TDCR_TDCF_Pos       (0U)
+#define FDCAN_TDCR_TDCF_Msk       (0x7FUL << FDCAN_TDCR_TDCF_Pos)              /*!< 0x0000007F */
+#define FDCAN_TDCR_TDCF           FDCAN_TDCR_TDCF_Msk                          /*!<Transmitter Delay Compensation Filter    */
+#define FDCAN_TDCR_TDCO_Pos       (8U)
+#define FDCAN_TDCR_TDCO_Msk       (0x7FUL << FDCAN_TDCR_TDCO_Pos)              /*!< 0x00007F00 */
+#define FDCAN_TDCR_TDCO           FDCAN_TDCR_TDCO_Msk                          /*!<Transmitter Delay Compensation Offset    */
+
+/*****************  Bit definition for FDCAN_IR register  **********************/
+#define FDCAN_IR_RF0N_Pos         (0U)
+#define FDCAN_IR_RF0N_Msk         (0x1UL << FDCAN_IR_RF0N_Pos)                 /*!< 0x00000001 */
+#define FDCAN_IR_RF0N             FDCAN_IR_RF0N_Msk                            /*!<Rx FIFO 0 New Message                    */
+#define FDCAN_IR_RF0W_Pos         (1U)
+#define FDCAN_IR_RF0W_Msk         (0x1UL << FDCAN_IR_RF0W_Pos)                 /*!< 0x00000002 */
+#define FDCAN_IR_RF0W             FDCAN_IR_RF0W_Msk                            /*!<Rx FIFO 0 Watermark Reached              */
+#define FDCAN_IR_RF0F_Pos         (2U)
+#define FDCAN_IR_RF0F_Msk         (0x1UL << FDCAN_IR_RF0F_Pos)                 /*!< 0x00000004 */
+#define FDCAN_IR_RF0F             FDCAN_IR_RF0F_Msk                            /*!<Rx FIFO 0 Full                           */
+#define FDCAN_IR_RF0L_Pos         (3U)
+#define FDCAN_IR_RF0L_Msk         (0x1UL << FDCAN_IR_RF0L_Pos)                 /*!< 0x00000008 */
+#define FDCAN_IR_RF0L             FDCAN_IR_RF0L_Msk                            /*!<Rx FIFO 0 Message Lost                   */
+#define FDCAN_IR_RF1N_Pos         (4U)
+#define FDCAN_IR_RF1N_Msk         (0x1UL << FDCAN_IR_RF1N_Pos)                 /*!< 0x00000010 */
+#define FDCAN_IR_RF1N             FDCAN_IR_RF1N_Msk                            /*!<Rx FIFO 1 New Message                    */
+#define FDCAN_IR_RF1W_Pos         (5U)
+#define FDCAN_IR_RF1W_Msk         (0x1UL << FDCAN_IR_RF1W_Pos)                 /*!< 0x00000020 */
+#define FDCAN_IR_RF1W             FDCAN_IR_RF1W_Msk                            /*!<Rx FIFO 1 Watermark Reached              */
+#define FDCAN_IR_RF1F_Pos         (6U)
+#define FDCAN_IR_RF1F_Msk         (0x1UL << FDCAN_IR_RF1F_Pos)                 /*!< 0x00000040 */
+#define FDCAN_IR_RF1F             FDCAN_IR_RF1F_Msk                            /*!<Rx FIFO 1 Full                           */
+#define FDCAN_IR_RF1L_Pos         (7U)
+#define FDCAN_IR_RF1L_Msk         (0x1UL << FDCAN_IR_RF1L_Pos)                 /*!< 0x00000080 */
+#define FDCAN_IR_RF1L             FDCAN_IR_RF1L_Msk                            /*!<Rx FIFO 1 Message Lost                   */
+#define FDCAN_IR_HPM_Pos          (8U)
+#define FDCAN_IR_HPM_Msk          (0x1UL << FDCAN_IR_HPM_Pos)                  /*!< 0x00000100 */
+#define FDCAN_IR_HPM              FDCAN_IR_HPM_Msk                             /*!<High Priority Message                    */
+#define FDCAN_IR_TC_Pos           (9U)
+#define FDCAN_IR_TC_Msk           (0x1UL << FDCAN_IR_TC_Pos)                   /*!< 0x00000200 */
+#define FDCAN_IR_TC               FDCAN_IR_TC_Msk                              /*!<Transmission Completed                   */
+#define FDCAN_IR_TCF_Pos          (10U)
+#define FDCAN_IR_TCF_Msk          (0x1UL << FDCAN_IR_TCF_Pos)                  /*!< 0x00000400 */
+#define FDCAN_IR_TCF              FDCAN_IR_TCF_Msk                             /*!<Transmission Cancellation Finished       */
+#define FDCAN_IR_TFE_Pos          (11U)
+#define FDCAN_IR_TFE_Msk          (0x1UL << FDCAN_IR_TFE_Pos)                  /*!< 0x00000800 */
+#define FDCAN_IR_TFE              FDCAN_IR_TFE_Msk                             /*!<Tx FIFO Empty                            */
+#define FDCAN_IR_TEFN_Pos         (12U)
+#define FDCAN_IR_TEFN_Msk         (0x1UL << FDCAN_IR_TEFN_Pos)                 /*!< 0x00001000 */
+#define FDCAN_IR_TEFN             FDCAN_IR_TEFN_Msk                            /*!<Tx Event FIFO New Entry                  */
+#define FDCAN_IR_TEFW_Pos         (13U)
+#define FDCAN_IR_TEFW_Msk         (0x1UL << FDCAN_IR_TEFW_Pos)                 /*!< 0x00002000 */
+#define FDCAN_IR_TEFW             FDCAN_IR_TEFW_Msk                            /*!<Tx Event FIFO Watermark Reached          */
+#define FDCAN_IR_TEFF_Pos         (14U)
+#define FDCAN_IR_TEFF_Msk         (0x1UL << FDCAN_IR_TEFF_Pos)                 /*!< 0x00004000 */
+#define FDCAN_IR_TEFF             FDCAN_IR_TEFF_Msk                            /*!<Tx Event FIFO Full                       */
+#define FDCAN_IR_TEFL_Pos         (15U)
+#define FDCAN_IR_TEFL_Msk         (0x1UL << FDCAN_IR_TEFL_Pos)                 /*!< 0x00008000 */
+#define FDCAN_IR_TEFL             FDCAN_IR_TEFL_Msk                            /*!<Tx Event FIFO Element Lost               */
+#define FDCAN_IR_TSW_Pos          (16U)
+#define FDCAN_IR_TSW_Msk          (0x1UL << FDCAN_IR_TSW_Pos)                  /*!< 0x00010000 */
+#define FDCAN_IR_TSW              FDCAN_IR_TSW_Msk                             /*!<Timestamp Wraparound                     */
+#define FDCAN_IR_MRAF_Pos         (17U)
+#define FDCAN_IR_MRAF_Msk         (0x1UL << FDCAN_IR_MRAF_Pos)                 /*!< 0x00020000 */
+#define FDCAN_IR_MRAF             FDCAN_IR_MRAF_Msk                            /*!<Message RAM Access Failure               */
+#define FDCAN_IR_TOO_Pos          (18U)
+#define FDCAN_IR_TOO_Msk          (0x1UL << FDCAN_IR_TOO_Pos)                  /*!< 0x00040000 */
+#define FDCAN_IR_TOO              FDCAN_IR_TOO_Msk                             /*!<Timeout Occurred                         */
+#define FDCAN_IR_DRX_Pos          (19U)
+#define FDCAN_IR_DRX_Msk          (0x1UL << FDCAN_IR_DRX_Pos)                  /*!< 0x00080000 */
+#define FDCAN_IR_DRX              FDCAN_IR_DRX_Msk                             /*!<Message stored to Dedicated Rx Buffer    */
+#define FDCAN_IR_ELO_Pos          (22U)
+#define FDCAN_IR_ELO_Msk          (0x1UL << FDCAN_IR_ELO_Pos)                  /*!< 0x00400000 */
+#define FDCAN_IR_ELO              FDCAN_IR_ELO_Msk                             /*!<Error Logging Overflow                   */
+#define FDCAN_IR_EP_Pos           (23U)
+#define FDCAN_IR_EP_Msk           (0x1UL << FDCAN_IR_EP_Pos)                   /*!< 0x00800000 */
+#define FDCAN_IR_EP               FDCAN_IR_EP_Msk                              /*!<Error Passive                            */
+#define FDCAN_IR_EW_Pos           (24U)
+#define FDCAN_IR_EW_Msk           (0x1UL << FDCAN_IR_EW_Pos)                   /*!< 0x01000000 */
+#define FDCAN_IR_EW               FDCAN_IR_EW_Msk                              /*!<Warning Status                           */
+#define FDCAN_IR_BO_Pos           (25U)
+#define FDCAN_IR_BO_Msk           (0x1UL << FDCAN_IR_BO_Pos)                   /*!< 0x02000000 */
+#define FDCAN_IR_BO               FDCAN_IR_BO_Msk                              /*!<Bus_Off Status                           */
+#define FDCAN_IR_WDI_Pos          (26U)
+#define FDCAN_IR_WDI_Msk          (0x1UL << FDCAN_IR_WDI_Pos)                  /*!< 0x04000000 */
+#define FDCAN_IR_WDI              FDCAN_IR_WDI_Msk                             /*!<Watchdog Interrupt                       */
+#define FDCAN_IR_PEA_Pos          (27U)
+#define FDCAN_IR_PEA_Msk          (0x1UL << FDCAN_IR_PEA_Pos)                  /*!< 0x08000000 */
+#define FDCAN_IR_PEA              FDCAN_IR_PEA_Msk                             /*!<Protocol Error in Arbitration Phase      */
+#define FDCAN_IR_PED_Pos          (28U)
+#define FDCAN_IR_PED_Msk          (0x1UL << FDCAN_IR_PED_Pos)                  /*!< 0x10000000 */
+#define FDCAN_IR_PED              FDCAN_IR_PED_Msk                             /*!<Protocol Error in Data Phase             */
+#define FDCAN_IR_ARA_Pos          (29U)
+#define FDCAN_IR_ARA_Msk          (0x1UL << FDCAN_IR_ARA_Pos)                  /*!< 0x20000000 */
+#define FDCAN_IR_ARA              FDCAN_IR_ARA_Msk                             /*!<Access to Reserved Address               */
+
+/*****************  Bit definition for FDCAN_IE register  **********************/
+#define FDCAN_IE_RF0NE_Pos        (0U)
+#define FDCAN_IE_RF0NE_Msk        (0x1UL << FDCAN_IE_RF0NE_Pos)                /*!< 0x00000001 */
+#define FDCAN_IE_RF0NE            FDCAN_IE_RF0NE_Msk                           /*!<Rx FIFO 0 New Message Enable                 */
+#define FDCAN_IE_RF0WE_Pos        (1U)
+#define FDCAN_IE_RF0WE_Msk        (0x1UL << FDCAN_IE_RF0WE_Pos)                /*!< 0x00000002 */
+#define FDCAN_IE_RF0WE            FDCAN_IE_RF0WE_Msk                           /*!<Rx FIFO 0 Watermark Reached Enable           */
+#define FDCAN_IE_RF0FE_Pos        (2U)
+#define FDCAN_IE_RF0FE_Msk        (0x1UL << FDCAN_IE_RF0FE_Pos)                /*!< 0x00000004 */
+#define FDCAN_IE_RF0FE            FDCAN_IE_RF0FE_Msk                           /*!<Rx FIFO 0 Full Enable                        */
+#define FDCAN_IE_RF0LE_Pos        (3U)
+#define FDCAN_IE_RF0LE_Msk        (0x1UL << FDCAN_IE_RF0LE_Pos)                /*!< 0x00000008 */
+#define FDCAN_IE_RF0LE            FDCAN_IE_RF0LE_Msk                           /*!<Rx FIFO 0 Message Lost Enable                */
+#define FDCAN_IE_RF1NE_Pos        (4U)
+#define FDCAN_IE_RF1NE_Msk        (0x1UL << FDCAN_IE_RF1NE_Pos)                /*!< 0x00000010 */
+#define FDCAN_IE_RF1NE            FDCAN_IE_RF1NE_Msk                           /*!<Rx FIFO 1 New Message Enable                 */
+#define FDCAN_IE_RF1WE_Pos        (5U)
+#define FDCAN_IE_RF1WE_Msk        (0x1UL << FDCAN_IE_RF1WE_Pos)                /*!< 0x00000020 */
+#define FDCAN_IE_RF1WE            FDCAN_IE_RF1WE_Msk                           /*!<Rx FIFO 1 Watermark Reached Enable           */
+#define FDCAN_IE_RF1FE_Pos        (6U)
+#define FDCAN_IE_RF1FE_Msk        (0x1UL << FDCAN_IE_RF1FE_Pos)                /*!< 0x00000040 */
+#define FDCAN_IE_RF1FE            FDCAN_IE_RF1FE_Msk                           /*!<Rx FIFO 1 Full Enable                        */
+#define FDCAN_IE_RF1LE_Pos        (7U)
+#define FDCAN_IE_RF1LE_Msk        (0x1UL << FDCAN_IE_RF1LE_Pos)                /*!< 0x00000080 */
+#define FDCAN_IE_RF1LE            FDCAN_IE_RF1LE_Msk                           /*!<Rx FIFO 1 Message Lost Enable                */
+#define FDCAN_IE_HPME_Pos         (8U)
+#define FDCAN_IE_HPME_Msk         (0x1UL << FDCAN_IE_HPME_Pos)                 /*!< 0x00000100 */
+#define FDCAN_IE_HPME             FDCAN_IE_HPME_Msk                            /*!<High Priority Message Enable                 */
+#define FDCAN_IE_TCE_Pos          (9U)
+#define FDCAN_IE_TCE_Msk          (0x1UL << FDCAN_IE_TCE_Pos)                  /*!< 0x00000200 */
+#define FDCAN_IE_TCE              FDCAN_IE_TCE_Msk                             /*!<Transmission Completed Enable                */
+#define FDCAN_IE_TCFE_Pos         (10U)
+#define FDCAN_IE_TCFE_Msk         (0x1UL << FDCAN_IE_TCFE_Pos)                 /*!< 0x00000400 */
+#define FDCAN_IE_TCFE             FDCAN_IE_TCFE_Msk                            /*!<Transmission Cancellation Finished Enable    */
+#define FDCAN_IE_TFEE_Pos         (11U)
+#define FDCAN_IE_TFEE_Msk         (0x1UL << FDCAN_IE_TFEE_Pos)                 /*!< 0x00000800 */
+#define FDCAN_IE_TFEE             FDCAN_IE_TFEE_Msk                            /*!<Tx FIFO Empty Enable                         */
+#define FDCAN_IE_TEFNE_Pos        (12U)
+#define FDCAN_IE_TEFNE_Msk        (0x1UL << FDCAN_IE_TEFNE_Pos)                /*!< 0x00001000 */
+#define FDCAN_IE_TEFNE            FDCAN_IE_TEFNE_Msk                           /*!<Tx Event FIFO New Entry Enable               */
+#define FDCAN_IE_TEFWE_Pos        (13U)
+#define FDCAN_IE_TEFWE_Msk        (0x1UL << FDCAN_IE_TEFWE_Pos)                /*!< 0x00002000 */
+#define FDCAN_IE_TEFWE            FDCAN_IE_TEFWE_Msk                           /*!<Tx Event FIFO Watermark Reached Enable       */
+#define FDCAN_IE_TEFFE_Pos        (14U)
+#define FDCAN_IE_TEFFE_Msk        (0x1UL << FDCAN_IE_TEFFE_Pos)                /*!< 0x00004000 */
+#define FDCAN_IE_TEFFE            FDCAN_IE_TEFFE_Msk                           /*!<Tx Event FIFO Full Enable                    */
+#define FDCAN_IE_TEFLE_Pos        (15U)
+#define FDCAN_IE_TEFLE_Msk        (0x1UL << FDCAN_IE_TEFLE_Pos)                /*!< 0x00008000 */
+#define FDCAN_IE_TEFLE            FDCAN_IE_TEFLE_Msk                           /*!<Tx Event FIFO Element Lost Enable            */
+#define FDCAN_IE_TSWE_Pos         (16U)
+#define FDCAN_IE_TSWE_Msk         (0x1UL << FDCAN_IE_TSWE_Pos)                 /*!< 0x00010000 */
+#define FDCAN_IE_TSWE             FDCAN_IE_TSWE_Msk                            /*!<Timestamp Wraparound Enable                  */
+#define FDCAN_IE_MRAFE_Pos        (17U)
+#define FDCAN_IE_MRAFE_Msk        (0x1UL << FDCAN_IE_MRAFE_Pos)                /*!< 0x00020000 */
+#define FDCAN_IE_MRAFE            FDCAN_IE_MRAFE_Msk                           /*!<Message RAM Access Failure Enable            */
+#define FDCAN_IE_TOOE_Pos         (18U)
+#define FDCAN_IE_TOOE_Msk         (0x1UL << FDCAN_IE_TOOE_Pos)                 /*!< 0x00040000 */
+#define FDCAN_IE_TOOE             FDCAN_IE_TOOE_Msk                            /*!<Timeout Occurred Enable                      */
+#define FDCAN_IE_DRXE_Pos         (19U)
+#define FDCAN_IE_DRXE_Msk         (0x1UL << FDCAN_IE_DRXE_Pos)                 /*!< 0x00080000 */
+#define FDCAN_IE_DRXE             FDCAN_IE_DRXE_Msk                            /*!<Message stored to Dedicated Rx Buffer Enable */
+#define FDCAN_IE_BECE_Pos         (20U)
+#define FDCAN_IE_BECE_Msk         (0x1UL << FDCAN_IE_BECE_Pos)                 /*!< 0x00100000 */
+#define FDCAN_IE_BECE             FDCAN_IE_BECE_Msk                            /*!<Bit Error Corrected Interrupt Enable         */
+#define FDCAN_IE_BEUE_Pos         (21U)
+#define FDCAN_IE_BEUE_Msk         (0x1UL << FDCAN_IE_BEUE_Pos)                 /*!< 0x00200000 */
+#define FDCAN_IE_BEUE             FDCAN_IE_BEUE_Msk                            /*!<Bit Error Uncorrected Interrupt Enable       */
+#define FDCAN_IE_ELOE_Pos         (22U)
+#define FDCAN_IE_ELOE_Msk         (0x1UL << FDCAN_IE_ELOE_Pos)                 /*!< 0x00400000 */
+#define FDCAN_IE_ELOE             FDCAN_IE_ELOE_Msk                            /*!<Error Logging Overflow Enable                */
+#define FDCAN_IE_EPE_Pos          (23U)
+#define FDCAN_IE_EPE_Msk          (0x1UL << FDCAN_IE_EPE_Pos)                  /*!< 0x00800000 */
+#define FDCAN_IE_EPE              FDCAN_IE_EPE_Msk                             /*!<Error Passive Enable                         */
+#define FDCAN_IE_EWE_Pos          (24U)
+#define FDCAN_IE_EWE_Msk          (0x1UL << FDCAN_IE_EWE_Pos)                  /*!< 0x01000000 */
+#define FDCAN_IE_EWE              FDCAN_IE_EWE_Msk                             /*!<Warning Status Enable                        */
+#define FDCAN_IE_BOE_Pos          (25U)
+#define FDCAN_IE_BOE_Msk          (0x1UL << FDCAN_IE_BOE_Pos)                  /*!< 0x02000000 */
+#define FDCAN_IE_BOE              FDCAN_IE_BOE_Msk                             /*!<Bus_Off Status Enable                        */
+#define FDCAN_IE_WDIE_Pos         (26U)
+#define FDCAN_IE_WDIE_Msk         (0x1UL << FDCAN_IE_WDIE_Pos)                 /*!< 0x04000000 */
+#define FDCAN_IE_WDIE             FDCAN_IE_WDIE_Msk                            /*!<Watchdog Interrupt Enable                    */
+#define FDCAN_IE_PEAE_Pos         (27U)
+#define FDCAN_IE_PEAE_Msk         (0x1UL << FDCAN_IE_PEAE_Pos)                 /*!< 0x08000000 */
+#define FDCAN_IE_PEAE             FDCAN_IE_PEAE_Msk                            /*!<Protocol Error in Arbitration Phase Enable   */
+#define FDCAN_IE_PEDE_Pos         (28U)
+#define FDCAN_IE_PEDE_Msk         (0x1UL << FDCAN_IE_PEDE_Pos)                 /*!< 0x10000000 */
+#define FDCAN_IE_PEDE             FDCAN_IE_PEDE_Msk                            /*!<Protocol Error in Data Phase Enable          */
+#define FDCAN_IE_ARAE_Pos         (29U)
+#define FDCAN_IE_ARAE_Msk         (0x1UL << FDCAN_IE_ARAE_Pos)                 /*!< 0x20000000 */
+#define FDCAN_IE_ARAE             FDCAN_IE_ARAE_Msk                            /*!<Access to Reserved Address Enable            */
+
+/*****************  Bit definition for FDCAN_ILS register  **********************/
+#define FDCAN_ILS_RF0NL_Pos       (0U)
+#define FDCAN_ILS_RF0NL_Msk       (0x1UL << FDCAN_ILS_RF0NL_Pos)               /*!< 0x00000001 */
+#define FDCAN_ILS_RF0NL           FDCAN_ILS_RF0NL_Msk                          /*!<Rx FIFO 0 New Message Line                  */
+#define FDCAN_ILS_RF0WL_Pos       (1U)
+#define FDCAN_ILS_RF0WL_Msk       (0x1UL << FDCAN_ILS_RF0WL_Pos)               /*!< 0x00000002 */
+#define FDCAN_ILS_RF0WL           FDCAN_ILS_RF0WL_Msk                          /*!<Rx FIFO 0 Watermark Reached Line            */
+#define FDCAN_ILS_RF0FL_Pos       (2U)
+#define FDCAN_ILS_RF0FL_Msk       (0x1UL << FDCAN_ILS_RF0FL_Pos)               /*!< 0x00000004 */
+#define FDCAN_ILS_RF0FL           FDCAN_ILS_RF0FL_Msk                          /*!<Rx FIFO 0 Full Line                         */
+#define FDCAN_ILS_RF0LL_Pos       (3U)
+#define FDCAN_ILS_RF0LL_Msk       (0x1UL << FDCAN_ILS_RF0LL_Pos)               /*!< 0x00000008 */
+#define FDCAN_ILS_RF0LL           FDCAN_ILS_RF0LL_Msk                          /*!<Rx FIFO 0 Message Lost Line                 */
+#define FDCAN_ILS_RF1NL_Pos       (4U)
+#define FDCAN_ILS_RF1NL_Msk       (0x1UL << FDCAN_ILS_RF1NL_Pos)               /*!< 0x00000010 */
+#define FDCAN_ILS_RF1NL           FDCAN_ILS_RF1NL_Msk                          /*!<Rx FIFO 1 New Message Line                  */
+#define FDCAN_ILS_RF1WL_Pos       (5U)
+#define FDCAN_ILS_RF1WL_Msk       (0x1UL << FDCAN_ILS_RF1WL_Pos)               /*!< 0x00000020 */
+#define FDCAN_ILS_RF1WL           FDCAN_ILS_RF1WL_Msk                          /*!<Rx FIFO 1 Watermark Reached Line            */
+#define FDCAN_ILS_RF1FL_Pos       (6U)
+#define FDCAN_ILS_RF1FL_Msk       (0x1UL << FDCAN_ILS_RF1FL_Pos)               /*!< 0x00000040 */
+#define FDCAN_ILS_RF1FL           FDCAN_ILS_RF1FL_Msk                          /*!<Rx FIFO 1 Full Line                         */
+#define FDCAN_ILS_RF1LL_Pos       (7U)
+#define FDCAN_ILS_RF1LL_Msk       (0x1UL << FDCAN_ILS_RF1LL_Pos)               /*!< 0x00000080 */
+#define FDCAN_ILS_RF1LL           FDCAN_ILS_RF1LL_Msk                          /*!<Rx FIFO 1 Message Lost Line                 */
+#define FDCAN_ILS_HPML_Pos        (8U)
+#define FDCAN_ILS_HPML_Msk        (0x1UL << FDCAN_ILS_HPML_Pos)                /*!< 0x00000100 */
+#define FDCAN_ILS_HPML            FDCAN_ILS_HPML_Msk                           /*!<High Priority Message Line                  */
+#define FDCAN_ILS_TCL_Pos         (9U)
+#define FDCAN_ILS_TCL_Msk         (0x1UL << FDCAN_ILS_TCL_Pos)                 /*!< 0x00000200 */
+#define FDCAN_ILS_TCL             FDCAN_ILS_TCL_Msk                            /*!<Transmission Completed Line                 */
+#define FDCAN_ILS_TCFL_Pos        (10U)
+#define FDCAN_ILS_TCFL_Msk        (0x1UL << FDCAN_ILS_TCFL_Pos)                /*!< 0x00000400 */
+#define FDCAN_ILS_TCFL            FDCAN_ILS_TCFL_Msk                           /*!<Transmission Cancellation Finished Line     */
+#define FDCAN_ILS_TFEL_Pos        (11U)
+#define FDCAN_ILS_TFEL_Msk        (0x1UL << FDCAN_ILS_TFEL_Pos)                /*!< 0x00000800 */
+#define FDCAN_ILS_TFEL            FDCAN_ILS_TFEL_Msk                           /*!<Tx FIFO Empty Line                          */
+#define FDCAN_ILS_TEFNL_Pos       (12U)
+#define FDCAN_ILS_TEFNL_Msk       (0x1UL << FDCAN_ILS_TEFNL_Pos)               /*!< 0x00001000 */
+#define FDCAN_ILS_TEFNL           FDCAN_ILS_TEFNL_Msk                          /*!<Tx Event FIFO New Entry Line                */
+#define FDCAN_ILS_TEFWL_Pos       (13U)
+#define FDCAN_ILS_TEFWL_Msk       (0x1UL << FDCAN_ILS_TEFWL_Pos)               /*!< 0x00002000 */
+#define FDCAN_ILS_TEFWL           FDCAN_ILS_TEFWL_Msk                          /*!<Tx Event FIFO Watermark Reached Line        */
+#define FDCAN_ILS_TEFFL_Pos       (14U)
+#define FDCAN_ILS_TEFFL_Msk       (0x1UL << FDCAN_ILS_TEFFL_Pos)               /*!< 0x00004000 */
+#define FDCAN_ILS_TEFFL           FDCAN_ILS_TEFFL_Msk                          /*!<Tx Event FIFO Full Line                     */
+#define FDCAN_ILS_TEFLL_Pos       (15U)
+#define FDCAN_ILS_TEFLL_Msk       (0x1UL << FDCAN_ILS_TEFLL_Pos)               /*!< 0x00008000 */
+#define FDCAN_ILS_TEFLL           FDCAN_ILS_TEFLL_Msk                          /*!<Tx Event FIFO Element Lost Line             */
+#define FDCAN_ILS_TSWL_Pos        (16U)
+#define FDCAN_ILS_TSWL_Msk        (0x1UL << FDCAN_ILS_TSWL_Pos)                /*!< 0x00010000 */
+#define FDCAN_ILS_TSWL            FDCAN_ILS_TSWL_Msk                           /*!<Timestamp Wraparound Line                   */
+#define FDCAN_ILS_MRAFE_Pos       (17U)
+#define FDCAN_ILS_MRAFE_Msk       (0x1UL << FDCAN_ILS_MRAFE_Pos)               /*!< 0x00020000 */
+#define FDCAN_ILS_MRAFE           FDCAN_ILS_MRAFE_Msk                          /*!<Message RAM Access Failure Line             */
+#define FDCAN_ILS_TOOE_Pos        (18U)
+#define FDCAN_ILS_TOOE_Msk        (0x1UL << FDCAN_ILS_TOOE_Pos)                /*!< 0x00040000 */
+#define FDCAN_ILS_TOOE            FDCAN_ILS_TOOE_Msk                           /*!<Timeout Occurred Line                       */
+#define FDCAN_ILS_DRXE_Pos        (19U)
+#define FDCAN_ILS_DRXE_Msk        (0x1UL << FDCAN_ILS_DRXE_Pos)                /*!< 0x00080000 */
+#define FDCAN_ILS_DRXE            FDCAN_ILS_DRXE_Msk                           /*!<Message stored to Dedicated Rx Buffer Line  */
+#define FDCAN_ILS_BECE_Pos        (20U)
+#define FDCAN_ILS_BECE_Msk        (0x1UL << FDCAN_ILS_BECE_Pos)                /*!< 0x00100000 */
+#define FDCAN_ILS_BECE            FDCAN_ILS_BECE_Msk                           /*!<Bit Error Corrected Interrupt Line          */
+#define FDCAN_ILS_BEUE_Pos        (21U)
+#define FDCAN_ILS_BEUE_Msk        (0x1UL << FDCAN_ILS_BEUE_Pos)                /*!< 0x00200000 */
+#define FDCAN_ILS_BEUE            FDCAN_ILS_BEUE_Msk                           /*!<Bit Error Uncorrected Interrupt Line        */
+#define FDCAN_ILS_ELOE_Pos        (22U)
+#define FDCAN_ILS_ELOE_Msk        (0x1UL << FDCAN_ILS_ELOE_Pos)                /*!< 0x00400000 */
+#define FDCAN_ILS_ELOE            FDCAN_ILS_ELOE_Msk                           /*!<Error Logging Overflow Line                 */
+#define FDCAN_ILS_EPE_Pos         (23U)
+#define FDCAN_ILS_EPE_Msk         (0x1UL << FDCAN_ILS_EPE_Pos)                 /*!< 0x00800000 */
+#define FDCAN_ILS_EPE             FDCAN_ILS_EPE_Msk                            /*!<Error Passive Line                          */
+#define FDCAN_ILS_EWE_Pos         (24U)
+#define FDCAN_ILS_EWE_Msk         (0x1UL << FDCAN_ILS_EWE_Pos)                 /*!< 0x01000000 */
+#define FDCAN_ILS_EWE             FDCAN_ILS_EWE_Msk                            /*!<Warning Status Line                         */
+#define FDCAN_ILS_BOE_Pos         (25U)
+#define FDCAN_ILS_BOE_Msk         (0x1UL << FDCAN_ILS_BOE_Pos)                 /*!< 0x02000000 */
+#define FDCAN_ILS_BOE             FDCAN_ILS_BOE_Msk                            /*!<Bus_Off Status Line                         */
+#define FDCAN_ILS_WDIE_Pos        (26U)
+#define FDCAN_ILS_WDIE_Msk        (0x1UL << FDCAN_ILS_WDIE_Pos)                /*!< 0x04000000 */
+#define FDCAN_ILS_WDIE            FDCAN_ILS_WDIE_Msk                           /*!<Watchdog Interrupt Line                     */
+#define FDCAN_ILS_PEAE_Pos        (27U)
+#define FDCAN_ILS_PEAE_Msk        (0x1UL << FDCAN_ILS_PEAE_Pos)                /*!< 0x08000000 */
+#define FDCAN_ILS_PEAE            FDCAN_ILS_PEAE_Msk                           /*!<Protocol Error in Arbitration Phase Line    */
+#define FDCAN_ILS_PEDE_Pos        (28U)
+#define FDCAN_ILS_PEDE_Msk        (0x1UL << FDCAN_ILS_PEDE_Pos)                /*!< 0x10000000 */
+#define FDCAN_ILS_PEDE            FDCAN_ILS_PEDE_Msk                           /*!<Protocol Error in Data Phase Line           */
+#define FDCAN_ILS_ARAE_Pos        (29U)
+#define FDCAN_ILS_ARAE_Msk        (0x1UL << FDCAN_ILS_ARAE_Pos)                /*!< 0x20000000 */
+#define FDCAN_ILS_ARAE            FDCAN_ILS_ARAE_Msk                           /*!<Access to Reserved Address Line             */
+
+/*****************  Bit definition for FDCAN_ILE register  **********************/
+#define FDCAN_ILE_EINT0_Pos       (0U)
+#define FDCAN_ILE_EINT0_Msk       (0x1UL << FDCAN_ILE_EINT0_Pos)               /*!< 0x00000001 */
+#define FDCAN_ILE_EINT0           FDCAN_ILE_EINT0_Msk                          /*!<Enable Interrupt Line 0                   */
+#define FDCAN_ILE_EINT1_Pos       (1U)
+#define FDCAN_ILE_EINT1_Msk       (0x1UL << FDCAN_ILE_EINT1_Pos)               /*!< 0x00000002 */
+#define FDCAN_ILE_EINT1           FDCAN_ILE_EINT1_Msk                          /*!<Enable Interrupt Line 1                   */
+
+/*****************  Bit definition for FDCAN_GFC register  **********************/
+#define FDCAN_GFC_RRFE_Pos        (0U)
+#define FDCAN_GFC_RRFE_Msk        (0x1UL << FDCAN_GFC_RRFE_Pos)                /*!< 0x00000001 */
+#define FDCAN_GFC_RRFE            FDCAN_GFC_RRFE_Msk                           /*!<Reject Remote Frames Extended             */
+#define FDCAN_GFC_RRFS_Pos        (1U)
+#define FDCAN_GFC_RRFS_Msk        (0x1UL << FDCAN_GFC_RRFS_Pos)                /*!< 0x00000002 */
+#define FDCAN_GFC_RRFS            FDCAN_GFC_RRFS_Msk                           /*!<Reject Remote Frames Standard             */
+#define FDCAN_GFC_ANFE_Pos        (2U)
+#define FDCAN_GFC_ANFE_Msk        (0x3UL << FDCAN_GFC_ANFE_Pos)                /*!< 0x0000000C */
+#define FDCAN_GFC_ANFE            FDCAN_GFC_ANFE_Msk                           /*!<Accept Non-matching Frames Extended       */
+#define FDCAN_GFC_ANFS_Pos        (4U)
+#define FDCAN_GFC_ANFS_Msk        (0x3UL << FDCAN_GFC_ANFS_Pos)                /*!< 0x00000030 */
+#define FDCAN_GFC_ANFS            FDCAN_GFC_ANFS_Msk                           /*!<Accept Non-matching Frames Standard       */
+
+/*****************  Bit definition for FDCAN_SIDFC register  ********************/
+#define FDCAN_SIDFC_FLSSA_Pos     (2U)
+#define FDCAN_SIDFC_FLSSA_Msk     (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos)          /*!< 0x0000FFFC */
+#define FDCAN_SIDFC_FLSSA         FDCAN_SIDFC_FLSSA_Msk                        /*!<Filter List Standard Start Address        */
+#define FDCAN_SIDFC_LSS_Pos       (16U)
+#define FDCAN_SIDFC_LSS_Msk       (0xFFUL << FDCAN_SIDFC_LSS_Pos)              /*!< 0x00FF0000 */
+#define FDCAN_SIDFC_LSS           FDCAN_SIDFC_LSS_Msk                          /*!<List Size Standard                        */
+
+/*****************  Bit definition for FDCAN_XIDFC register  ********************/
+#define FDCAN_XIDFC_FLESA_Pos     (2U)
+#define FDCAN_XIDFC_FLESA_Msk     (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos)          /*!< 0x0000FFFC */
+#define FDCAN_XIDFC_FLESA         FDCAN_XIDFC_FLESA_Msk                        /*!<Filter List Standard Start Address        */
+#define FDCAN_XIDFC_LSE_Pos       (16U)
+#define FDCAN_XIDFC_LSE_Msk       (0x7FUL << FDCAN_XIDFC_LSE_Pos)              /*!< 0x007F0000 */
+#define FDCAN_XIDFC_LSE           FDCAN_XIDFC_LSE_Msk                          /*!<List Size Extended                        */
+
+/*****************  Bit definition for FDCAN_XIDAM register  ********************/
+#define FDCAN_XIDAM_EIDM_Pos      (0U)
+#define FDCAN_XIDAM_EIDM_Msk      (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)       /*!< 0x1FFFFFFF */
+#define FDCAN_XIDAM_EIDM          FDCAN_XIDAM_EIDM_Msk                         /*!<Extended ID Mask                          */
+
+/*****************  Bit definition for FDCAN_HPMS register  *********************/
+#define FDCAN_HPMS_BIDX_Pos       (0U)
+#define FDCAN_HPMS_BIDX_Msk       (0x3FUL << FDCAN_HPMS_BIDX_Pos)              /*!< 0x0000003F */
+#define FDCAN_HPMS_BIDX           FDCAN_HPMS_BIDX_Msk                          /*!<Buffer Index                              */
+#define FDCAN_HPMS_MSI_Pos        (6U)
+#define FDCAN_HPMS_MSI_Msk        (0x3UL << FDCAN_HPMS_MSI_Pos)                /*!< 0x000000C0 */
+#define FDCAN_HPMS_MSI            FDCAN_HPMS_MSI_Msk                           /*!<Message Storage Indicator                 */
+#define FDCAN_HPMS_FIDX_Pos       (8U)
+#define FDCAN_HPMS_FIDX_Msk       (0x7FUL << FDCAN_HPMS_FIDX_Pos)              /*!< 0x00007F00 */
+#define FDCAN_HPMS_FIDX           FDCAN_HPMS_FIDX_Msk                          /*!<Filter Index                              */
+#define FDCAN_HPMS_FLST_Pos       (15U)
+#define FDCAN_HPMS_FLST_Msk       (0x1UL << FDCAN_HPMS_FLST_Pos)               /*!< 0x00008000 */
+#define FDCAN_HPMS_FLST           FDCAN_HPMS_FLST_Msk                          /*!<Filter List                               */
+
+/*****************  Bit definition for FDCAN_NDAT1 register  ********************/
+#define FDCAN_NDAT1_ND0_Pos       (0U)
+#define FDCAN_NDAT1_ND0_Msk       (0x1UL << FDCAN_NDAT1_ND0_Pos)               /*!< 0x00000001 */
+#define FDCAN_NDAT1_ND0           FDCAN_NDAT1_ND0_Msk                          /*!<New Data flag of Rx Buffer 0              */
+#define FDCAN_NDAT1_ND1_Pos       (1U)
+#define FDCAN_NDAT1_ND1_Msk       (0x1UL << FDCAN_NDAT1_ND1_Pos)               /*!< 0x00000002 */
+#define FDCAN_NDAT1_ND1           FDCAN_NDAT1_ND1_Msk                          /*!<New Data flag of Rx Buffer 1              */
+#define FDCAN_NDAT1_ND2_Pos       (2U)
+#define FDCAN_NDAT1_ND2_Msk       (0x1UL << FDCAN_NDAT1_ND2_Pos)               /*!< 0x00000004 */
+#define FDCAN_NDAT1_ND2           FDCAN_NDAT1_ND2_Msk                          /*!<New Data flag of Rx Buffer 2              */
+#define FDCAN_NDAT1_ND3_Pos       (3U)
+#define FDCAN_NDAT1_ND3_Msk       (0x1UL << FDCAN_NDAT1_ND3_Pos)               /*!< 0x00000008 */
+#define FDCAN_NDAT1_ND3           FDCAN_NDAT1_ND3_Msk                          /*!<New Data flag of Rx Buffer 3              */
+#define FDCAN_NDAT1_ND4_Pos       (4U)
+#define FDCAN_NDAT1_ND4_Msk       (0x1UL << FDCAN_NDAT1_ND4_Pos)               /*!< 0x00000010 */
+#define FDCAN_NDAT1_ND4           FDCAN_NDAT1_ND4_Msk                          /*!<New Data flag of Rx Buffer 4              */
+#define FDCAN_NDAT1_ND5_Pos       (5U)
+#define FDCAN_NDAT1_ND5_Msk       (0x1UL << FDCAN_NDAT1_ND5_Pos)               /*!< 0x00000020 */
+#define FDCAN_NDAT1_ND5           FDCAN_NDAT1_ND5_Msk                          /*!<New Data flag of Rx Buffer 5              */
+#define FDCAN_NDAT1_ND6_Pos       (6U)
+#define FDCAN_NDAT1_ND6_Msk       (0x1UL << FDCAN_NDAT1_ND6_Pos)               /*!< 0x00000040 */
+#define FDCAN_NDAT1_ND6           FDCAN_NDAT1_ND6_Msk                          /*!<New Data flag of Rx Buffer 6              */
+#define FDCAN_NDAT1_ND7_Pos       (7U)
+#define FDCAN_NDAT1_ND7_Msk       (0x1UL << FDCAN_NDAT1_ND7_Pos)               /*!< 0x00000080 */
+#define FDCAN_NDAT1_ND7           FDCAN_NDAT1_ND7_Msk                          /*!<New Data flag of Rx Buffer 7              */
+#define FDCAN_NDAT1_ND8_Pos       (8U)
+#define FDCAN_NDAT1_ND8_Msk       (0x1UL << FDCAN_NDAT1_ND8_Pos)               /*!< 0x00000100 */
+#define FDCAN_NDAT1_ND8           FDCAN_NDAT1_ND8_Msk                          /*!<New Data flag of Rx Buffer 8              */
+#define FDCAN_NDAT1_ND9_Pos       (9U)
+#define FDCAN_NDAT1_ND9_Msk       (0x1UL << FDCAN_NDAT1_ND9_Pos)               /*!< 0x00000200 */
+#define FDCAN_NDAT1_ND9           FDCAN_NDAT1_ND9_Msk                          /*!<New Data flag of Rx Buffer 9              */
+#define FDCAN_NDAT1_ND10_Pos      (10U)
+#define FDCAN_NDAT1_ND10_Msk      (0x1UL << FDCAN_NDAT1_ND10_Pos)              /*!< 0x00000400 */
+#define FDCAN_NDAT1_ND10          FDCAN_NDAT1_ND10_Msk                         /*!<New Data flag of Rx Buffer 10             */
+#define FDCAN_NDAT1_ND11_Pos      (11U)
+#define FDCAN_NDAT1_ND11_Msk      (0x1UL << FDCAN_NDAT1_ND11_Pos)              /*!< 0x00000800 */
+#define FDCAN_NDAT1_ND11          FDCAN_NDAT1_ND11_Msk                         /*!<New Data flag of Rx Buffer 11             */
+#define FDCAN_NDAT1_ND12_Pos      (12U)
+#define FDCAN_NDAT1_ND12_Msk      (0x1UL << FDCAN_NDAT1_ND12_Pos)              /*!< 0x00001000 */
+#define FDCAN_NDAT1_ND12          FDCAN_NDAT1_ND12_Msk                         /*!<New Data flag of Rx Buffer 12             */
+#define FDCAN_NDAT1_ND13_Pos      (13U)
+#define FDCAN_NDAT1_ND13_Msk      (0x1UL << FDCAN_NDAT1_ND13_Pos)              /*!< 0x00002000 */
+#define FDCAN_NDAT1_ND13          FDCAN_NDAT1_ND13_Msk                         /*!<New Data flag of Rx Buffer 13             */
+#define FDCAN_NDAT1_ND14_Pos      (14U)
+#define FDCAN_NDAT1_ND14_Msk      (0x1UL << FDCAN_NDAT1_ND14_Pos)              /*!< 0x00004000 */
+#define FDCAN_NDAT1_ND14          FDCAN_NDAT1_ND14_Msk                         /*!<New Data flag of Rx Buffer 14             */
+#define FDCAN_NDAT1_ND15_Pos      (15U)
+#define FDCAN_NDAT1_ND15_Msk      (0x1UL << FDCAN_NDAT1_ND15_Pos)              /*!< 0x00008000 */
+#define FDCAN_NDAT1_ND15          FDCAN_NDAT1_ND15_Msk                         /*!<New Data flag of Rx Buffer 15             */
+#define FDCAN_NDAT1_ND16_Pos      (16U)
+#define FDCAN_NDAT1_ND16_Msk      (0x1UL << FDCAN_NDAT1_ND16_Pos)              /*!< 0x00010000 */
+#define FDCAN_NDAT1_ND16          FDCAN_NDAT1_ND16_Msk                         /*!<New Data flag of Rx Buffer 16             */
+#define FDCAN_NDAT1_ND17_Pos      (17U)
+#define FDCAN_NDAT1_ND17_Msk      (0x1UL << FDCAN_NDAT1_ND17_Pos)              /*!< 0x00020000 */
+#define FDCAN_NDAT1_ND17          FDCAN_NDAT1_ND17_Msk                         /*!<New Data flag of Rx Buffer 17             */
+#define FDCAN_NDAT1_ND18_Pos      (18U)
+#define FDCAN_NDAT1_ND18_Msk      (0x1UL << FDCAN_NDAT1_ND18_Pos)              /*!< 0x00040000 */
+#define FDCAN_NDAT1_ND18          FDCAN_NDAT1_ND18_Msk                         /*!<New Data flag of Rx Buffer 18             */
+#define FDCAN_NDAT1_ND19_Pos      (19U)
+#define FDCAN_NDAT1_ND19_Msk      (0x1UL << FDCAN_NDAT1_ND19_Pos)              /*!< 0x00080000 */
+#define FDCAN_NDAT1_ND19          FDCAN_NDAT1_ND19_Msk                         /*!<New Data flag of Rx Buffer 19             */
+#define FDCAN_NDAT1_ND20_Pos      (20U)
+#define FDCAN_NDAT1_ND20_Msk      (0x1UL << FDCAN_NDAT1_ND20_Pos)              /*!< 0x00100000 */
+#define FDCAN_NDAT1_ND20          FDCAN_NDAT1_ND20_Msk                         /*!<New Data flag of Rx Buffer 20             */
+#define FDCAN_NDAT1_ND21_Pos      (21U)
+#define FDCAN_NDAT1_ND21_Msk      (0x1UL << FDCAN_NDAT1_ND21_Pos)              /*!< 0x00200000 */
+#define FDCAN_NDAT1_ND21          FDCAN_NDAT1_ND21_Msk                         /*!<New Data flag of Rx Buffer 21             */
+#define FDCAN_NDAT1_ND22_Pos      (22U)
+#define FDCAN_NDAT1_ND22_Msk      (0x1UL << FDCAN_NDAT1_ND22_Pos)              /*!< 0x00400000 */
+#define FDCAN_NDAT1_ND22          FDCAN_NDAT1_ND22_Msk                         /*!<New Data flag of Rx Buffer 22             */
+#define FDCAN_NDAT1_ND23_Pos      (23U)
+#define FDCAN_NDAT1_ND23_Msk      (0x1UL << FDCAN_NDAT1_ND23_Pos)              /*!< 0x00800000 */
+#define FDCAN_NDAT1_ND23          FDCAN_NDAT1_ND23_Msk                         /*!<New Data flag of Rx Buffer 23             */
+#define FDCAN_NDAT1_ND24_Pos      (24U)
+#define FDCAN_NDAT1_ND24_Msk      (0x1UL << FDCAN_NDAT1_ND24_Pos)              /*!< 0x01000000 */
+#define FDCAN_NDAT1_ND24          FDCAN_NDAT1_ND24_Msk                         /*!<New Data flag of Rx Buffer 24             */
+#define FDCAN_NDAT1_ND25_Pos      (25U)
+#define FDCAN_NDAT1_ND25_Msk      (0x1UL << FDCAN_NDAT1_ND25_Pos)              /*!< 0x02000000 */
+#define FDCAN_NDAT1_ND25          FDCAN_NDAT1_ND25_Msk                         /*!<New Data flag of Rx Buffer 25             */
+#define FDCAN_NDAT1_ND26_Pos      (26U)
+#define FDCAN_NDAT1_ND26_Msk      (0x1UL << FDCAN_NDAT1_ND26_Pos)              /*!< 0x04000000 */
+#define FDCAN_NDAT1_ND26          FDCAN_NDAT1_ND26_Msk                         /*!<New Data flag of Rx Buffer 26             */
+#define FDCAN_NDAT1_ND27_Pos      (27U)
+#define FDCAN_NDAT1_ND27_Msk      (0x1UL << FDCAN_NDAT1_ND27_Pos)              /*!< 0x08000000 */
+#define FDCAN_NDAT1_ND27          FDCAN_NDAT1_ND27_Msk                         /*!<New Data flag of Rx Buffer 27             */
+#define FDCAN_NDAT1_ND28_Pos      (28U)
+#define FDCAN_NDAT1_ND28_Msk      (0x1UL << FDCAN_NDAT1_ND28_Pos)              /*!< 0x10000000 */
+#define FDCAN_NDAT1_ND28          FDCAN_NDAT1_ND28_Msk                         /*!<New Data flag of Rx Buffer 28             */
+#define FDCAN_NDAT1_ND29_Pos      (29U)
+#define FDCAN_NDAT1_ND29_Msk      (0x1UL << FDCAN_NDAT1_ND29_Pos)              /*!< 0x20000000 */
+#define FDCAN_NDAT1_ND29          FDCAN_NDAT1_ND29_Msk                         /*!<New Data flag of Rx Buffer 29             */
+#define FDCAN_NDAT1_ND30_Pos      (30U)
+#define FDCAN_NDAT1_ND30_Msk      (0x1UL << FDCAN_NDAT1_ND30_Pos)              /*!< 0x40000000 */
+#define FDCAN_NDAT1_ND30          FDCAN_NDAT1_ND30_Msk                         /*!<New Data flag of Rx Buffer 30             */
+#define FDCAN_NDAT1_ND31_Pos      (31U)
+#define FDCAN_NDAT1_ND31_Msk      (0x1UL << FDCAN_NDAT1_ND31_Pos)              /*!< 0x80000000 */
+#define FDCAN_NDAT1_ND31          FDCAN_NDAT1_ND31_Msk                         /*!<New Data flag of Rx Buffer 31             */
+
+/*****************  Bit definition for FDCAN_NDAT2 register  ********************/
+#define FDCAN_NDAT2_ND32_Pos      (0U)
+#define FDCAN_NDAT2_ND32_Msk      (0x1UL << FDCAN_NDAT2_ND32_Pos)              /*!< 0x00000001 */
+#define FDCAN_NDAT2_ND32          FDCAN_NDAT2_ND32_Msk                         /*!<New Data flag of Rx Buffer 32             */
+#define FDCAN_NDAT2_ND33_Pos      (1U)
+#define FDCAN_NDAT2_ND33_Msk      (0x1UL << FDCAN_NDAT2_ND33_Pos)              /*!< 0x00000002 */
+#define FDCAN_NDAT2_ND33          FDCAN_NDAT2_ND33_Msk                         /*!<New Data flag of Rx Buffer 33             */
+#define FDCAN_NDAT2_ND34_Pos      (2U)
+#define FDCAN_NDAT2_ND34_Msk      (0x1UL << FDCAN_NDAT2_ND34_Pos)              /*!< 0x00000004 */
+#define FDCAN_NDAT2_ND34          FDCAN_NDAT2_ND34_Msk                         /*!<New Data flag of Rx Buffer 34             */
+#define FDCAN_NDAT2_ND35_Pos      (3U)
+#define FDCAN_NDAT2_ND35_Msk      (0x1UL << FDCAN_NDAT2_ND35_Pos)              /*!< 0x00000008 */
+#define FDCAN_NDAT2_ND35          FDCAN_NDAT2_ND35_Msk                         /*!<New Data flag of Rx Buffer 35             */
+#define FDCAN_NDAT2_ND36_Pos      (4U)
+#define FDCAN_NDAT2_ND36_Msk      (0x1UL << FDCAN_NDAT2_ND36_Pos)              /*!< 0x00000010 */
+#define FDCAN_NDAT2_ND36          FDCAN_NDAT2_ND36_Msk                         /*!<New Data flag of Rx Buffer 36             */
+#define FDCAN_NDAT2_ND37_Pos      (5U)
+#define FDCAN_NDAT2_ND37_Msk      (0x1UL << FDCAN_NDAT2_ND37_Pos)              /*!< 0x00000020 */
+#define FDCAN_NDAT2_ND37          FDCAN_NDAT2_ND37_Msk                         /*!<New Data flag of Rx Buffer 37             */
+#define FDCAN_NDAT2_ND38_Pos      (6U)
+#define FDCAN_NDAT2_ND38_Msk      (0x1UL << FDCAN_NDAT2_ND38_Pos)              /*!< 0x00000040 */
+#define FDCAN_NDAT2_ND38          FDCAN_NDAT2_ND38_Msk                         /*!<New Data flag of Rx Buffer 38             */
+#define FDCAN_NDAT2_ND39_Pos      (7U)
+#define FDCAN_NDAT2_ND39_Msk      (0x1UL << FDCAN_NDAT2_ND39_Pos)              /*!< 0x00000080 */
+#define FDCAN_NDAT2_ND39          FDCAN_NDAT2_ND39_Msk                         /*!<New Data flag of Rx Buffer 39             */
+#define FDCAN_NDAT2_ND40_Pos      (8U)
+#define FDCAN_NDAT2_ND40_Msk      (0x1UL << FDCAN_NDAT2_ND40_Pos)              /*!< 0x00000100 */
+#define FDCAN_NDAT2_ND40          FDCAN_NDAT2_ND40_Msk                         /*!<New Data flag of Rx Buffer 40             */
+#define FDCAN_NDAT2_ND41_Pos      (9U)
+#define FDCAN_NDAT2_ND41_Msk      (0x1UL << FDCAN_NDAT2_ND41_Pos)              /*!< 0x00000200 */
+#define FDCAN_NDAT2_ND41          FDCAN_NDAT2_ND41_Msk                         /*!<New Data flag of Rx Buffer 41             */
+#define FDCAN_NDAT2_ND42_Pos      (10U)
+#define FDCAN_NDAT2_ND42_Msk      (0x1UL << FDCAN_NDAT2_ND42_Pos)              /*!< 0x00000400 */
+#define FDCAN_NDAT2_ND42          FDCAN_NDAT2_ND42_Msk                         /*!<New Data flag of Rx Buffer 42             */
+#define FDCAN_NDAT2_ND43_Pos      (11U)
+#define FDCAN_NDAT2_ND43_Msk      (0x1UL << FDCAN_NDAT2_ND43_Pos)              /*!< 0x00000800 */
+#define FDCAN_NDAT2_ND43          FDCAN_NDAT2_ND43_Msk                         /*!<New Data flag of Rx Buffer 43             */
+#define FDCAN_NDAT2_ND44_Pos      (12U)
+#define FDCAN_NDAT2_ND44_Msk      (0x1UL << FDCAN_NDAT2_ND44_Pos)              /*!< 0x00001000 */
+#define FDCAN_NDAT2_ND44          FDCAN_NDAT2_ND44_Msk                         /*!<New Data flag of Rx Buffer 44             */
+#define FDCAN_NDAT2_ND45_Pos      (13U)
+#define FDCAN_NDAT2_ND45_Msk      (0x1UL << FDCAN_NDAT2_ND45_Pos)              /*!< 0x00002000 */
+#define FDCAN_NDAT2_ND45          FDCAN_NDAT2_ND45_Msk                         /*!<New Data flag of Rx Buffer 45             */
+#define FDCAN_NDAT2_ND46_Pos      (14U)
+#define FDCAN_NDAT2_ND46_Msk      (0x1UL << FDCAN_NDAT2_ND46_Pos)              /*!< 0x00004000 */
+#define FDCAN_NDAT2_ND46          FDCAN_NDAT2_ND46_Msk                         /*!<New Data flag of Rx Buffer 46             */
+#define FDCAN_NDAT2_ND47_Pos      (15U)
+#define FDCAN_NDAT2_ND47_Msk      (0x1UL << FDCAN_NDAT2_ND47_Pos)              /*!< 0x00008000 */
+#define FDCAN_NDAT2_ND47          FDCAN_NDAT2_ND47_Msk                         /*!<New Data flag of Rx Buffer 47             */
+#define FDCAN_NDAT2_ND48_Pos      (16U)
+#define FDCAN_NDAT2_ND48_Msk      (0x1UL << FDCAN_NDAT2_ND48_Pos)              /*!< 0x00010000 */
+#define FDCAN_NDAT2_ND48          FDCAN_NDAT2_ND48_Msk                         /*!<New Data flag of Rx Buffer 48             */
+#define FDCAN_NDAT2_ND49_Pos      (17U)
+#define FDCAN_NDAT2_ND49_Msk      (0x1UL << FDCAN_NDAT2_ND49_Pos)              /*!< 0x00020000 */
+#define FDCAN_NDAT2_ND49          FDCAN_NDAT2_ND49_Msk                         /*!<New Data flag of Rx Buffer 49             */
+#define FDCAN_NDAT2_ND50_Pos      (18U)
+#define FDCAN_NDAT2_ND50_Msk      (0x1UL << FDCAN_NDAT2_ND50_Pos)              /*!< 0x00040000 */
+#define FDCAN_NDAT2_ND50          FDCAN_NDAT2_ND50_Msk                         /*!<New Data flag of Rx Buffer 50             */
+#define FDCAN_NDAT2_ND51_Pos      (19U)
+#define FDCAN_NDAT2_ND51_Msk      (0x1UL << FDCAN_NDAT2_ND51_Pos)              /*!< 0x00080000 */
+#define FDCAN_NDAT2_ND51          FDCAN_NDAT2_ND51_Msk                         /*!<New Data flag of Rx Buffer 51             */
+#define FDCAN_NDAT2_ND52_Pos      (20U)
+#define FDCAN_NDAT2_ND52_Msk      (0x1UL << FDCAN_NDAT2_ND52_Pos)              /*!< 0x00100000 */
+#define FDCAN_NDAT2_ND52          FDCAN_NDAT2_ND52_Msk                         /*!<New Data flag of Rx Buffer 52             */
+#define FDCAN_NDAT2_ND53_Pos      (21U)
+#define FDCAN_NDAT2_ND53_Msk      (0x1UL << FDCAN_NDAT2_ND53_Pos)              /*!< 0x00200000 */
+#define FDCAN_NDAT2_ND53          FDCAN_NDAT2_ND53_Msk                         /*!<New Data flag of Rx Buffer 53             */
+#define FDCAN_NDAT2_ND54_Pos      (22U)
+#define FDCAN_NDAT2_ND54_Msk      (0x1UL << FDCAN_NDAT2_ND54_Pos)              /*!< 0x00400000 */
+#define FDCAN_NDAT2_ND54          FDCAN_NDAT2_ND54_Msk                         /*!<New Data flag of Rx Buffer 54             */
+#define FDCAN_NDAT2_ND55_Pos      (23U)
+#define FDCAN_NDAT2_ND55_Msk      (0x1UL << FDCAN_NDAT2_ND55_Pos)              /*!< 0x00800000 */
+#define FDCAN_NDAT2_ND55          FDCAN_NDAT2_ND55_Msk                         /*!<New Data flag of Rx Buffer 55             */
+#define FDCAN_NDAT2_ND56_Pos      (24U)
+#define FDCAN_NDAT2_ND56_Msk      (0x1UL << FDCAN_NDAT2_ND56_Pos)              /*!< 0x01000000 */
+#define FDCAN_NDAT2_ND56          FDCAN_NDAT2_ND56_Msk                         /*!<New Data flag of Rx Buffer 56             */
+#define FDCAN_NDAT2_ND57_Pos      (25U)
+#define FDCAN_NDAT2_ND57_Msk      (0x1UL << FDCAN_NDAT2_ND57_Pos)              /*!< 0x02000000 */
+#define FDCAN_NDAT2_ND57          FDCAN_NDAT2_ND57_Msk                         /*!<New Data flag of Rx Buffer 57             */
+#define FDCAN_NDAT2_ND58_Pos      (26U)
+#define FDCAN_NDAT2_ND58_Msk      (0x1UL << FDCAN_NDAT2_ND58_Pos)              /*!< 0x04000000 */
+#define FDCAN_NDAT2_ND58          FDCAN_NDAT2_ND58_Msk                         /*!<New Data flag of Rx Buffer 58             */
+#define FDCAN_NDAT2_ND59_Pos      (27U)
+#define FDCAN_NDAT2_ND59_Msk      (0x1UL << FDCAN_NDAT2_ND59_Pos)              /*!< 0x08000000 */
+#define FDCAN_NDAT2_ND59          FDCAN_NDAT2_ND59_Msk                         /*!<New Data flag of Rx Buffer 59             */
+#define FDCAN_NDAT2_ND60_Pos      (28U)
+#define FDCAN_NDAT2_ND60_Msk      (0x1UL << FDCAN_NDAT2_ND60_Pos)              /*!< 0x10000000 */
+#define FDCAN_NDAT2_ND60          FDCAN_NDAT2_ND60_Msk                         /*!<New Data flag of Rx Buffer 60             */
+#define FDCAN_NDAT2_ND61_Pos      (29U)
+#define FDCAN_NDAT2_ND61_Msk      (0x1UL << FDCAN_NDAT2_ND61_Pos)              /*!< 0x20000000 */
+#define FDCAN_NDAT2_ND61          FDCAN_NDAT2_ND61_Msk                         /*!<New Data flag of Rx Buffer 61             */
+#define FDCAN_NDAT2_ND62_Pos      (30U)
+#define FDCAN_NDAT2_ND62_Msk      (0x1UL << FDCAN_NDAT2_ND62_Pos)              /*!< 0x40000000 */
+#define FDCAN_NDAT2_ND62          FDCAN_NDAT2_ND62_Msk                         /*!<New Data flag of Rx Buffer 62             */
+#define FDCAN_NDAT2_ND63_Pos      (31U)
+#define FDCAN_NDAT2_ND63_Msk      (0x1UL << FDCAN_NDAT2_ND63_Pos)              /*!< 0x80000000 */
+#define FDCAN_NDAT2_ND63          FDCAN_NDAT2_ND63_Msk                         /*!<New Data flag of Rx Buffer 63             */
+
+/*****************  Bit definition for FDCAN_RXF0C register  ********************/
+#define FDCAN_RXF0C_F0SA_Pos      (2U)
+#define FDCAN_RXF0C_F0SA_Msk      (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos)           /*!< 0x0000FFFC */
+#define FDCAN_RXF0C_F0SA          FDCAN_RXF0C_F0SA_Msk                         /*!<Rx FIFO 0 Start Address                   */
+#define FDCAN_RXF0C_F0S_Pos       (16U)
+#define FDCAN_RXF0C_F0S_Msk       (0x7FUL << FDCAN_RXF0C_F0S_Pos)              /*!< 0x007F0000 */
+#define FDCAN_RXF0C_F0S           FDCAN_RXF0C_F0S_Msk                          /*!<Number of Rx FIFO 0 elements              */
+#define FDCAN_RXF0C_F0WM_Pos      (24U)
+#define FDCAN_RXF0C_F0WM_Msk      (0x7FUL << FDCAN_RXF0C_F0WM_Pos)             /*!< 0x7F000000 */
+#define FDCAN_RXF0C_F0WM          FDCAN_RXF0C_F0WM_Msk                         /*!<FIFO 0 Watermark                          */
+#define FDCAN_RXF0C_F0OM_Pos      (31U)
+#define FDCAN_RXF0C_F0OM_Msk      (0x1UL << FDCAN_RXF0C_F0OM_Pos)              /*!< 0x80000000 */
+#define FDCAN_RXF0C_F0OM          FDCAN_RXF0C_F0OM_Msk                         /*!<FIFO 0 Operation Mode                     */
+
+/*****************  Bit definition for FDCAN_RXF0S register  ********************/
+#define FDCAN_RXF0S_F0FL_Pos      (0U)
+#define FDCAN_RXF0S_F0FL_Msk      (0x7FUL << FDCAN_RXF0S_F0FL_Pos)             /*!< 0x0000007F */
+#define FDCAN_RXF0S_F0FL          FDCAN_RXF0S_F0FL_Msk                         /*!<Rx FIFO 0 Fill Level                      */
+#define FDCAN_RXF0S_F0GI_Pos      (8U)
+#define FDCAN_RXF0S_F0GI_Msk      (0x3FUL << FDCAN_RXF0S_F0GI_Pos)             /*!< 0x00003F00 */
+#define FDCAN_RXF0S_F0GI          FDCAN_RXF0S_F0GI_Msk                         /*!<Rx FIFO 0 Get Index                       */
+#define FDCAN_RXF0S_F0PI_Pos      (16U)
+#define FDCAN_RXF0S_F0PI_Msk      (0x3FUL << FDCAN_RXF0S_F0PI_Pos)             /*!< 0x003F0000 */
+#define FDCAN_RXF0S_F0PI          FDCAN_RXF0S_F0PI_Msk                         /*!<Rx FIFO 0 Put Index                       */
+#define FDCAN_RXF0S_F0F_Pos       (24U)
+#define FDCAN_RXF0S_F0F_Msk       (0x1UL << FDCAN_RXF0S_F0F_Pos)               /*!< 0x01000000 */
+#define FDCAN_RXF0S_F0F           FDCAN_RXF0S_F0F_Msk                          /*!<Rx FIFO 0 Full                            */
+#define FDCAN_RXF0S_RF0L_Pos      (25U)
+#define FDCAN_RXF0S_RF0L_Msk      (0x1UL << FDCAN_RXF0S_RF0L_Pos)              /*!< 0x02000000 */
+#define FDCAN_RXF0S_RF0L          FDCAN_RXF0S_RF0L_Msk                         /*!<Rx FIFO 0 Message Lost                    */
+
+/*****************  Bit definition for FDCAN_RXF0A register  ********************/
+#define FDCAN_RXF0A_F0AI_Pos      (0U)
+#define FDCAN_RXF0A_F0AI_Msk      (0x3FUL << FDCAN_RXF0A_F0AI_Pos)             /*!< 0x0000003F */
+#define FDCAN_RXF0A_F0AI          FDCAN_RXF0A_F0AI_Msk                         /*!<Rx FIFO 0 Acknowledge Index               */
+
+/*****************  Bit definition for FDCAN_RXBC register  ********************/
+#define FDCAN_RXBC_RBSA_Pos       (2U)
+#define FDCAN_RXBC_RBSA_Msk       (0x3FFFUL << FDCAN_RXBC_RBSA_Pos)            /*!< 0x0000FFFC */
+#define FDCAN_RXBC_RBSA           FDCAN_RXBC_RBSA_Msk                          /*!<Rx Buffer Start Address                   */
+
+/*****************  Bit definition for FDCAN_RXF1C register  ********************/
+#define FDCAN_RXF1C_F1SA_Pos      (2U)
+#define FDCAN_RXF1C_F1SA_Msk      (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos)           /*!< 0x0000FFFC */
+#define FDCAN_RXF1C_F1SA          FDCAN_RXF1C_F1SA_Msk                         /*!<Rx FIFO 1 Start Address                   */
+#define FDCAN_RXF1C_F1S_Pos       (16U)
+#define FDCAN_RXF1C_F1S_Msk       (0x7FUL << FDCAN_RXF1C_F1S_Pos)              /*!< 0x007F0000 */
+#define FDCAN_RXF1C_F1S           FDCAN_RXF1C_F1S_Msk                          /*!<Number of Rx FIFO 1 elements              */
+#define FDCAN_RXF1C_F1WM_Pos      (24U)
+#define FDCAN_RXF1C_F1WM_Msk      (0x7FUL << FDCAN_RXF1C_F1WM_Pos)             /*!< 0x7F000000 */
+#define FDCAN_RXF1C_F1WM          FDCAN_RXF1C_F1WM_Msk                         /*!<Rx FIFO 1 Watermark                       */
+#define FDCAN_RXF1C_F1OM_Pos      (31U)
+#define FDCAN_RXF1C_F1OM_Msk      (0x1UL << FDCAN_RXF1C_F1OM_Pos)              /*!< 0x80000000 */
+#define FDCAN_RXF1C_F1OM          FDCAN_RXF1C_F1OM_Msk                         /*!<FIFO 1 Operation Mode                     */
+
+/*****************  Bit definition for FDCAN_RXF1S register  ********************/
+#define FDCAN_RXF1S_F1FL_Pos      (0U)
+#define FDCAN_RXF1S_F1FL_Msk      (0x7FUL << FDCAN_RXF1S_F1FL_Pos)             /*!< 0x0000007F */
+#define FDCAN_RXF1S_F1FL          FDCAN_RXF1S_F1FL_Msk                         /*!<Rx FIFO 1 Fill Level                      */
+#define FDCAN_RXF1S_F1GI_Pos      (8U)
+#define FDCAN_RXF1S_F1GI_Msk      (0x3FUL << FDCAN_RXF1S_F1GI_Pos)             /*!< 0x00003F00 */
+#define FDCAN_RXF1S_F1GI          FDCAN_RXF1S_F1GI_Msk                         /*!<Rx FIFO 1 Get Index                       */
+#define FDCAN_RXF1S_F1PI_Pos      (16U)
+#define FDCAN_RXF1S_F1PI_Msk      (0x3FUL << FDCAN_RXF1S_F1PI_Pos)             /*!< 0x003F0000 */
+#define FDCAN_RXF1S_F1PI          FDCAN_RXF1S_F1PI_Msk                         /*!<Rx FIFO 1 Put Index                       */
+#define FDCAN_RXF1S_F1F_Pos       (24U)
+#define FDCAN_RXF1S_F1F_Msk       (0x1UL << FDCAN_RXF1S_F1F_Pos)               /*!< 0x01000000 */
+#define FDCAN_RXF1S_F1F           FDCAN_RXF1S_F1F_Msk                          /*!<Rx FIFO 1 Full                            */
+#define FDCAN_RXF1S_RF1L_Pos      (25U)
+#define FDCAN_RXF1S_RF1L_Msk      (0x1UL << FDCAN_RXF1S_RF1L_Pos)              /*!< 0x02000000 */
+#define FDCAN_RXF1S_RF1L          FDCAN_RXF1S_RF1L_Msk                         /*!<Rx FIFO 1 Message Lost                    */
+
+/*****************  Bit definition for FDCAN_RXF1A register  ********************/
+#define FDCAN_RXF1A_F1AI_Pos      (0U)
+#define FDCAN_RXF1A_F1AI_Msk      (0x3FUL << FDCAN_RXF1A_F1AI_Pos)             /*!< 0x0000003F */
+#define FDCAN_RXF1A_F1AI          FDCAN_RXF1A_F1AI_Msk                         /*!<Rx FIFO 1 Acknowledge Index               */
+
+/*****************  Bit definition for FDCAN_RXESC register  ********************/
+#define FDCAN_RXESC_F0DS_Pos      (0U)
+#define FDCAN_RXESC_F0DS_Msk      (0x7UL << FDCAN_RXESC_F0DS_Pos)              /*!< 0x00000007 */
+#define FDCAN_RXESC_F0DS          FDCAN_RXESC_F0DS_Msk                         /*!<Rx FIFO 1 Data Field Size                 */
+#define FDCAN_RXESC_F1DS_Pos      (4U)
+#define FDCAN_RXESC_F1DS_Msk      (0x7UL << FDCAN_RXESC_F1DS_Pos)              /*!< 0x00000070 */
+#define FDCAN_RXESC_F1DS          FDCAN_RXESC_F1DS_Msk                         /*!<Rx FIFO 0 Data Field Size                 */
+#define FDCAN_RXESC_RBDS_Pos      (8U)
+#define FDCAN_RXESC_RBDS_Msk      (0x7UL << FDCAN_RXESC_RBDS_Pos)              /*!< 0x00000700 */
+#define FDCAN_RXESC_RBDS          FDCAN_RXESC_RBDS_Msk                         /*!<Rx Buffer Data Field Size                 */
+
+/*****************  Bit definition for FDCAN_TXBC register  *********************/
+#define FDCAN_TXBC_TBSA_Pos       (2U)
+#define FDCAN_TXBC_TBSA_Msk       (0x3FFFUL << FDCAN_TXBC_TBSA_Pos)            /*!< 0x0000FFFC */
+#define FDCAN_TXBC_TBSA           FDCAN_TXBC_TBSA_Msk                          /*!<Tx Buffers Start Address                  */
+#define FDCAN_TXBC_NDTB_Pos       (16U)
+#define FDCAN_TXBC_NDTB_Msk       (0x3FUL << FDCAN_TXBC_NDTB_Pos)              /*!< 0x003F0000 */
+#define FDCAN_TXBC_NDTB           FDCAN_TXBC_NDTB_Msk                          /*!<Number of Dedicated Transmit Buffers      */
+#define FDCAN_TXBC_TFQS_Pos       (24U)
+#define FDCAN_TXBC_TFQS_Msk       (0x3FUL << FDCAN_TXBC_TFQS_Pos)              /*!< 0x3F000000 */
+#define FDCAN_TXBC_TFQS           FDCAN_TXBC_TFQS_Msk                          /*!<Transmit FIFO/Queue Size                  */
+#define FDCAN_TXBC_TFQM_Pos       (30U)
+#define FDCAN_TXBC_TFQM_Msk       (0x1UL << FDCAN_TXBC_TFQM_Pos)               /*!< 0x40000000 */
+#define FDCAN_TXBC_TFQM           FDCAN_TXBC_TFQM_Msk                          /*!<Tx FIFO/Queue Mode                        */
+
+/*****************  Bit definition for FDCAN_TXFQS register  *********************/
+#define FDCAN_TXFQS_TFFL_Pos      (0U)
+#define FDCAN_TXFQS_TFFL_Msk      (0x3FUL << FDCAN_TXFQS_TFFL_Pos)             /*!< 0x0000003F */
+#define FDCAN_TXFQS_TFFL          FDCAN_TXFQS_TFFL_Msk                         /*!<Tx FIFO Free Level                        */
+#define FDCAN_TXFQS_TFGI_Pos      (8U)
+#define FDCAN_TXFQS_TFGI_Msk      (0x1FUL << FDCAN_TXFQS_TFGI_Pos)             /*!< 0x00001F00 */
+#define FDCAN_TXFQS_TFGI          FDCAN_TXFQS_TFGI_Msk                         /*!<Tx FIFO Get Index                         */
+#define FDCAN_TXFQS_TFQPI_Pos     (16U)
+#define FDCAN_TXFQS_TFQPI_Msk     (0x1FUL << FDCAN_TXFQS_TFQPI_Pos)            /*!< 0x001F0000 */
+#define FDCAN_TXFQS_TFQPI         FDCAN_TXFQS_TFQPI_Msk                        /*!<Tx FIFO/Queue Put Index                   */
+#define FDCAN_TXFQS_TFQF_Pos      (21U)
+#define FDCAN_TXFQS_TFQF_Msk      (0x1UL << FDCAN_TXFQS_TFQF_Pos)              /*!< 0x00200000 */
+#define FDCAN_TXFQS_TFQF          FDCAN_TXFQS_TFQF_Msk                         /*!<Tx FIFO/Queue Full                        */
+
+/*****************  Bit definition for FDCAN_TXESC register  *********************/
+#define FDCAN_TXESC_TBDS_Pos      (0U)
+#define FDCAN_TXESC_TBDS_Msk      (0x7UL << FDCAN_TXESC_TBDS_Pos)              /*!< 0x00000007 */
+#define FDCAN_TXESC_TBDS          FDCAN_TXESC_TBDS_Msk                         /*!<Tx Buffer Data Field Size                 */
+
+/*****************  Bit definition for FDCAN_TXBRP register  *********************/
+#define FDCAN_TXBRP_TRP_Pos       (0U)
+#define FDCAN_TXBRP_TRP_Msk       (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos)        /*!< 0xFFFFFFFF */
+#define FDCAN_TXBRP_TRP           FDCAN_TXBRP_TRP_Msk                          /*!<Transmission Request Pending              */
+
+/*****************  Bit definition for FDCAN_TXBAR register  *********************/
+#define FDCAN_TXBAR_AR_Pos        (0U)
+#define FDCAN_TXBAR_AR_Msk        (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos)         /*!< 0xFFFFFFFF */
+#define FDCAN_TXBAR_AR            FDCAN_TXBAR_AR_Msk                           /*!<Add Request                               */
+
+/*****************  Bit definition for FDCAN_TXBCR register  *********************/
+#define FDCAN_TXBCR_CR_Pos        (0U)
+#define FDCAN_TXBCR_CR_Msk        (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos)         /*!< 0xFFFFFFFF */
+#define FDCAN_TXBCR_CR            FDCAN_TXBCR_CR_Msk                           /*!<Cancellation Request                      */
+
+/*****************  Bit definition for FDCAN_TXBTO register  *********************/
+#define FDCAN_TXBTO_TO_Pos        (0U)
+#define FDCAN_TXBTO_TO_Msk        (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos)         /*!< 0xFFFFFFFF */
+#define FDCAN_TXBTO_TO            FDCAN_TXBTO_TO_Msk                           /*!<Transmission Occurred                     */
+
+/*****************  Bit definition for FDCAN_TXBCF register  *********************/
+#define FDCAN_TXBCF_CF_Pos        (0U)
+#define FDCAN_TXBCF_CF_Msk        (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos)         /*!< 0xFFFFFFFF */
+#define FDCAN_TXBCF_CF            FDCAN_TXBCF_CF_Msk                           /*!<Cancellation Finished                     */
+
+/*****************  Bit definition for FDCAN_TXBTIE register  ********************/
+#define FDCAN_TXBTIE_TIE_Pos      (0U)
+#define FDCAN_TXBTIE_TIE_Msk      (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos)       /*!< 0xFFFFFFFF */
+#define FDCAN_TXBTIE_TIE          FDCAN_TXBTIE_TIE_Msk                         /*!<Transmission Interrupt Enable             */
+
+/*****************  Bit definition for FDCAN_ TXBCIE register  *******************/
+#define FDCAN_TXBCIE_CFIE_Pos     (0U)
+#define FDCAN_TXBCIE_CFIE_Msk     (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos)      /*!< 0xFFFFFFFF */
+#define FDCAN_TXBCIE_CFIE         FDCAN_TXBCIE_CFIE_Msk                        /*!<Cancellation Finished Interrupt Enable    */
+
+/*****************  Bit definition for FDCAN_TXEFC register  *********************/
+#define FDCAN_TXEFC_EFSA_Pos      (2U)
+#define FDCAN_TXEFC_EFSA_Msk      (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos)           /*!< 0x0000FFFC */
+#define FDCAN_TXEFC_EFSA          FDCAN_TXEFC_EFSA_Msk                         /*!<Event FIFO Start Address                  */
+#define FDCAN_TXEFC_EFS_Pos       (16U)
+#define FDCAN_TXEFC_EFS_Msk       (0x3FUL << FDCAN_TXEFC_EFS_Pos)              /*!< 0x003F0000 */
+#define FDCAN_TXEFC_EFS           FDCAN_TXEFC_EFS_Msk                          /*!<Event FIFO Size                           */
+#define FDCAN_TXEFC_EFWM_Pos      (24U)
+#define FDCAN_TXEFC_EFWM_Msk      (0x3FUL << FDCAN_TXEFC_EFWM_Pos)             /*!< 0x3F000000 */
+#define FDCAN_TXEFC_EFWM          FDCAN_TXEFC_EFWM_Msk                         /*!<Event FIFO Watermark                      */
+
+/*****************  Bit definition for FDCAN_TXEFS register  *********************/
+#define FDCAN_TXEFS_EFFL_Pos      (0U)
+#define FDCAN_TXEFS_EFFL_Msk      (0x3FUL << FDCAN_TXEFS_EFFL_Pos)             /*!< 0x0000003F */
+#define FDCAN_TXEFS_EFFL          FDCAN_TXEFS_EFFL_Msk                         /*!<Event FIFO Fill Level                     */
+#define FDCAN_TXEFS_EFGI_Pos      (8U)
+#define FDCAN_TXEFS_EFGI_Msk      (0x1FUL << FDCAN_TXEFS_EFGI_Pos)             /*!< 0x00001F00 */
+#define FDCAN_TXEFS_EFGI          FDCAN_TXEFS_EFGI_Msk                         /*!<Event FIFO Get Index                      */
+#define FDCAN_TXEFS_EFPI_Pos      (16U)
+#define FDCAN_TXEFS_EFPI_Msk      (0x1FUL << FDCAN_TXEFS_EFPI_Pos)             /*!< 0x001F0000 */
+#define FDCAN_TXEFS_EFPI          FDCAN_TXEFS_EFPI_Msk                         /*!<Event FIFO Put Index                      */
+#define FDCAN_TXEFS_EFF_Pos       (24U)
+#define FDCAN_TXEFS_EFF_Msk       (0x1UL << FDCAN_TXEFS_EFF_Pos)               /*!< 0x01000000 */
+#define FDCAN_TXEFS_EFF           FDCAN_TXEFS_EFF_Msk                          /*!<Event FIFO Full                           */
+#define FDCAN_TXEFS_TEFL_Pos      (25U)
+#define FDCAN_TXEFS_TEFL_Msk      (0x1UL << FDCAN_TXEFS_TEFL_Pos)              /*!< 0x02000000 */
+#define FDCAN_TXEFS_TEFL          FDCAN_TXEFS_TEFL_Msk                         /*!<Tx Event FIFO Element Lost                */
+
+/*****************  Bit definition for FDCAN_TXEFA register  *********************/
+#define FDCAN_TXEFA_EFAI_Pos      (0U)
+#define FDCAN_TXEFA_EFAI_Msk      (0x1FUL << FDCAN_TXEFA_EFAI_Pos)             /*!< 0x0000001F */
+#define FDCAN_TXEFA_EFAI          FDCAN_TXEFA_EFAI_Msk                         /*!<Event FIFO Acknowledge Index              */
+
+/*****************  Bit definition for FDCAN_TTTMC register  *********************/
+#define FDCAN_TTTMC_TMSA_Pos      (2U)
+#define FDCAN_TTTMC_TMSA_Msk      (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos)           /*!< 0x0000FFFC */
+#define FDCAN_TTTMC_TMSA          FDCAN_TTTMC_TMSA_Msk                         /*!<Trigger Memory Start Address              */
+#define FDCAN_TTTMC_TME_Pos       (16U)
+#define FDCAN_TTTMC_TME_Msk       (0x7FUL << FDCAN_TTTMC_TME_Pos)              /*!< 0x007F0000 */
+#define FDCAN_TTTMC_TME           FDCAN_TTTMC_TME_Msk                          /*!<Trigger Memory Elements                   */
+
+/*****************  Bit definition for FDCAN_TTRMC register  *********************/
+#define FDCAN_TTRMC_RID_Pos       (0U)
+#define FDCAN_TTRMC_RID_Msk       (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos)        /*!< 0x1FFFFFFF */
+#define FDCAN_TTRMC_RID           FDCAN_TTRMC_RID_Msk                          /*!<Reference Identifier                      */
+#define FDCAN_TTRMC_XTD_Pos       (30U)
+#define FDCAN_TTRMC_XTD_Msk       (0x1UL << FDCAN_TTRMC_XTD_Pos)               /*!< 0x40000000 */
+#define FDCAN_TTRMC_XTD           FDCAN_TTRMC_XTD_Msk                          /*!< Extended Identifier                      */
+#define FDCAN_TTRMC_RMPS_Pos      (31U)
+#define FDCAN_TTRMC_RMPS_Msk      (0x1UL << FDCAN_TTRMC_RMPS_Pos)              /*!< 0x80000000 */
+#define FDCAN_TTRMC_RMPS          FDCAN_TTRMC_RMPS_Msk                         /*!<Reference Message Payload Select          */
+
+/*****************  Bit definition for FDCAN_TTOCF register  *********************/
+#define FDCAN_TTOCF_OM_Pos        (0U)
+#define FDCAN_TTOCF_OM_Msk        (0x3UL << FDCAN_TTOCF_OM_Pos)                /*!< 0x00000003 */
+#define FDCAN_TTOCF_OM            FDCAN_TTOCF_OM_Msk                           /*!<Operation Mode                            */
+#define FDCAN_TTOCF_GEN_Pos       (3U)
+#define FDCAN_TTOCF_GEN_Msk       (0x1UL << FDCAN_TTOCF_GEN_Pos)               /*!< 0x00000008 */
+#define FDCAN_TTOCF_GEN           FDCAN_TTOCF_GEN_Msk                          /*!<Gap Enable                                */
+#define FDCAN_TTOCF_TM_Pos        (4U)
+#define FDCAN_TTOCF_TM_Msk        (0x1UL << FDCAN_TTOCF_TM_Pos)                /*!< 0x00000010 */
+#define FDCAN_TTOCF_TM            FDCAN_TTOCF_TM_Msk                           /*!<Time Master                               */
+#define FDCAN_TTOCF_LDSDL_Pos     (5U)
+#define FDCAN_TTOCF_LDSDL_Msk     (0x7UL << FDCAN_TTOCF_LDSDL_Pos)             /*!< 0x000000E0 */
+#define FDCAN_TTOCF_LDSDL         FDCAN_TTOCF_LDSDL_Msk                        /*!<LD of Synchronization Deviation Limit     */
+#define FDCAN_TTOCF_IRTO_Pos      (8U)
+#define FDCAN_TTOCF_IRTO_Msk      (0x7FUL << FDCAN_TTOCF_IRTO_Pos)             /*!< 0x00007F00 */
+#define FDCAN_TTOCF_IRTO          FDCAN_TTOCF_IRTO_Msk                         /*!<Initial Reference Trigger Offset          */
+#define FDCAN_TTOCF_EECS_Pos      (15U)
+#define FDCAN_TTOCF_EECS_Msk      (0x1UL << FDCAN_TTOCF_EECS_Pos)              /*!< 0x00008000 */
+#define FDCAN_TTOCF_EECS          FDCAN_TTOCF_EECS_Msk                         /*!<Enable External Clock Synchronization     */
+#define FDCAN_TTOCF_AWL_Pos       (16U)
+#define FDCAN_TTOCF_AWL_Msk       (0xFFUL << FDCAN_TTOCF_AWL_Pos)              /*!< 0x00FF0000 */
+#define FDCAN_TTOCF_AWL           FDCAN_TTOCF_AWL_Msk                          /*!<Application Watchdog Limit                */
+#define FDCAN_TTOCF_EGTF_Pos      (24U)
+#define FDCAN_TTOCF_EGTF_Msk      (0x1UL << FDCAN_TTOCF_EGTF_Pos)              /*!< 0x01000000 */
+#define FDCAN_TTOCF_EGTF          FDCAN_TTOCF_EGTF_Msk                         /*!<Enable Global Time Filtering              */
+#define FDCAN_TTOCF_ECC_Pos       (25U)
+#define FDCAN_TTOCF_ECC_Msk       (0x1UL << FDCAN_TTOCF_ECC_Pos)               /*!< 0x02000000 */
+#define FDCAN_TTOCF_ECC           FDCAN_TTOCF_ECC_Msk                          /*!<Enable Clock Calibration                  */
+#define FDCAN_TTOCF_EVTP_Pos      (26U)
+#define FDCAN_TTOCF_EVTP_Msk      (0x1UL << FDCAN_TTOCF_EVTP_Pos)              /*!< 0x04000000 */
+#define FDCAN_TTOCF_EVTP          FDCAN_TTOCF_EVTP_Msk                         /*!<Event Trigger Polarity                    */
+
+/*****************  Bit definition for FDCAN_TTMLM register  *********************/
+#define FDCAN_TTMLM_CCM_Pos       (0U)
+#define FDCAN_TTMLM_CCM_Msk       (0x3FUL << FDCAN_TTMLM_CCM_Pos)              /*!< 0x0000003F */
+#define FDCAN_TTMLM_CCM           FDCAN_TTMLM_CCM_Msk                          /*!<Cycle Count Max                           */
+#define FDCAN_TTMLM_CSS_Pos       (6U)
+#define FDCAN_TTMLM_CSS_Msk       (0x3UL << FDCAN_TTMLM_CSS_Pos)               /*!< 0x000000C0 */
+#define FDCAN_TTMLM_CSS           FDCAN_TTMLM_CSS_Msk                          /*!<Cycle Start Synchronization               */
+#define FDCAN_TTMLM_TXEW_Pos      (8U)
+#define FDCAN_TTMLM_TXEW_Msk      (0xFUL << FDCAN_TTMLM_TXEW_Pos)              /*!< 0x00000F00 */
+#define FDCAN_TTMLM_TXEW          FDCAN_TTMLM_TXEW_Msk                         /*!<Tx Enable Window                          */
+#define FDCAN_TTMLM_ENTT_Pos      (16U)
+#define FDCAN_TTMLM_ENTT_Msk      (0xFFFUL << FDCAN_TTMLM_ENTT_Pos)            /*!< 0x0FFF0000 */
+#define FDCAN_TTMLM_ENTT          FDCAN_TTMLM_ENTT_Msk                         /*!<Expected Number of Tx Triggers            */
+
+/*****************  Bit definition for FDCAN_TURCF register  *********************/
+#define FDCAN_TURCF_NCL_Pos       (0U)
+#define FDCAN_TURCF_NCL_Msk       (0xFFFFUL << FDCAN_TURCF_NCL_Pos)            /*!< 0x0000FFFF */
+#define FDCAN_TURCF_NCL           FDCAN_TURCF_NCL_Msk                          /*!<Numerator Configuration Low               */
+#define FDCAN_TURCF_DC_Pos        (16U)
+#define FDCAN_TURCF_DC_Msk        (0x3FFFUL << FDCAN_TURCF_DC_Pos)             /*!< 0x3FFF0000 */
+#define FDCAN_TURCF_DC            FDCAN_TURCF_DC_Msk                           /*!<Denominator Configuration                 */
+#define FDCAN_TURCF_ELT_Pos       (31U)
+#define FDCAN_TURCF_ELT_Msk       (0x1UL << FDCAN_TURCF_ELT_Pos)               /*!< 0x80000000 */
+#define FDCAN_TURCF_ELT           FDCAN_TURCF_ELT_Msk                          /*!<Enable Local Time                         */
+
+/*****************  Bit definition for FDCAN_TTOCN register  ********************/
+#define FDCAN_TTOCN_SGT_Pos       (0U)
+#define FDCAN_TTOCN_SGT_Msk       (0x1UL << FDCAN_TTOCN_SGT_Pos)               /*!< 0x00000001 */
+#define FDCAN_TTOCN_SGT           FDCAN_TTOCN_SGT_Msk                          /*!<Set Global time                           */
+#define FDCAN_TTOCN_ECS_Pos       (1U)
+#define FDCAN_TTOCN_ECS_Msk       (0x1UL << FDCAN_TTOCN_ECS_Pos)               /*!< 0x00000002 */
+#define FDCAN_TTOCN_ECS           FDCAN_TTOCN_ECS_Msk                          /*!<External Clock Synchronization            */
+#define FDCAN_TTOCN_SWP_Pos       (2U)
+#define FDCAN_TTOCN_SWP_Msk       (0x1UL << FDCAN_TTOCN_SWP_Pos)               /*!< 0x00000004 */
+#define FDCAN_TTOCN_SWP           FDCAN_TTOCN_SWP_Msk                          /*!<Stop Watch Polarity                       */
+#define FDCAN_TTOCN_SWS_Pos       (3U)
+#define FDCAN_TTOCN_SWS_Msk       (0x3UL << FDCAN_TTOCN_SWS_Pos)               /*!< 0x00000018 */
+#define FDCAN_TTOCN_SWS           FDCAN_TTOCN_SWS_Msk                          /*!<Stop Watch Source                         */
+#define FDCAN_TTOCN_RTIE_Pos      (5U)
+#define FDCAN_TTOCN_RTIE_Msk      (0x1UL << FDCAN_TTOCN_RTIE_Pos)              /*!< 0x00000020 */
+#define FDCAN_TTOCN_RTIE          FDCAN_TTOCN_RTIE_Msk                         /*!<Register Time Mark Interrupt Pulse Enable */
+#define FDCAN_TTOCN_TMC_Pos       (6U)
+#define FDCAN_TTOCN_TMC_Msk       (0x3UL << FDCAN_TTOCN_TMC_Pos)               /*!< 0x000000C0 */
+#define FDCAN_TTOCN_TMC           FDCAN_TTOCN_TMC_Msk                          /*!<Register Time Mark Compare                */
+#define FDCAN_TTOCN_TTIE_Pos      (8U)
+#define FDCAN_TTOCN_TTIE_Msk      (0x1UL << FDCAN_TTOCN_TTIE_Pos)              /*!< 0x00000100 */
+#define FDCAN_TTOCN_TTIE          FDCAN_TTOCN_TTIE_Msk                         /*!<Trigger Time Mark Interrupt Pulse Enable  */
+#define FDCAN_TTOCN_GCS_Pos       (9U)
+#define FDCAN_TTOCN_GCS_Msk       (0x1UL << FDCAN_TTOCN_GCS_Pos)               /*!< 0x00000200 */
+#define FDCAN_TTOCN_GCS           FDCAN_TTOCN_GCS_Msk                          /*!<Gap Control Select                        */
+#define FDCAN_TTOCN_FGP_Pos       (10U)
+#define FDCAN_TTOCN_FGP_Msk       (0x1UL << FDCAN_TTOCN_FGP_Pos)               /*!< 0x00000400 */
+#define FDCAN_TTOCN_FGP           FDCAN_TTOCN_FGP_Msk                          /*!<Finish Gap                                */
+#define FDCAN_TTOCN_TMG_Pos       (11U)
+#define FDCAN_TTOCN_TMG_Msk       (0x1UL << FDCAN_TTOCN_TMG_Pos)               /*!< 0x00000800 */
+#define FDCAN_TTOCN_TMG           FDCAN_TTOCN_TMG_Msk                          /*!<Time Mark Gap                             */
+#define FDCAN_TTOCN_NIG_Pos       (12U)
+#define FDCAN_TTOCN_NIG_Msk       (0x1UL << FDCAN_TTOCN_NIG_Pos)               /*!< 0x00001000 */
+#define FDCAN_TTOCN_NIG           FDCAN_TTOCN_NIG_Msk                          /*!<Next is Gap                               */
+#define FDCAN_TTOCN_ESCN_Pos      (13U)
+#define FDCAN_TTOCN_ESCN_Msk      (0x1UL << FDCAN_TTOCN_ESCN_Pos)              /*!< 0x00002000 */
+#define FDCAN_TTOCN_ESCN          FDCAN_TTOCN_ESCN_Msk                         /*!<External Synchronization Control          */
+#define FDCAN_TTOCN_LCKC_Pos      (15U)
+#define FDCAN_TTOCN_LCKC_Msk      (0x1UL << FDCAN_TTOCN_LCKC_Pos)              /*!< 0x00008000 */
+#define FDCAN_TTOCN_LCKC          FDCAN_TTOCN_LCKC_Msk                         /*!<TT Operation Control Register Locked      */
+
+/*****************  Bit definition for FDCAN_TTGTP register  ********************/
+#define FDCAN_TTGTP_TP_Pos        (0U)
+#define FDCAN_TTGTP_TP_Msk        (0xFFFFUL << FDCAN_TTGTP_TP_Pos)             /*!< 0x0000FFFF */
+#define FDCAN_TTGTP_TP            FDCAN_TTGTP_TP_Msk                           /*!<Time Preset                               */
+#define FDCAN_TTGTP_CTP_Pos       (16U)
+#define FDCAN_TTGTP_CTP_Msk       (0xFFFFUL << FDCAN_TTGTP_CTP_Pos)            /*!< 0xFFFF0000 */
+#define FDCAN_TTGTP_CTP           FDCAN_TTGTP_CTP_Msk                          /*!<Cycle Time Target Phase                   */
+
+/*****************  Bit definition for FDCAN_TTTMK register  ********************/
+#define FDCAN_TTTMK_TM_Pos        (0U)
+#define FDCAN_TTTMK_TM_Msk        (0xFFFFUL << FDCAN_TTTMK_TM_Pos)             /*!< 0x0000FFFF */
+#define FDCAN_TTTMK_TM            FDCAN_TTTMK_TM_Msk                           /*!<Time Mark                                 */
+#define FDCAN_TTTMK_TICC_Pos      (16U)
+#define FDCAN_TTTMK_TICC_Msk      (0x7FUL << FDCAN_TTTMK_TICC_Pos)             /*!< 0x007F0000 */
+#define FDCAN_TTTMK_TICC          FDCAN_TTTMK_TICC_Msk                         /*!<Time Mark Cycle Code                      */
+#define FDCAN_TTTMK_LCKM_Pos      (31U)
+#define FDCAN_TTTMK_LCKM_Msk      (0x1UL << FDCAN_TTTMK_LCKM_Pos)              /*!< 0x80000000 */
+#define FDCAN_TTTMK_LCKM          FDCAN_TTTMK_LCKM_Msk                         /*!<TT Time Mark Register Locked              */
+
+/*****************  Bit definition for FDCAN_TTIR register  ********************/
+#define FDCAN_TTIR_SBC_Pos        (0U)
+#define FDCAN_TTIR_SBC_Msk        (0x1UL << FDCAN_TTIR_SBC_Pos)                /*!< 0x00000001 */
+#define FDCAN_TTIR_SBC            FDCAN_TTIR_SBC_Msk                           /*!<Start of Basic Cycle                      */
+#define FDCAN_TTIR_SMC_Pos        (1U)
+#define FDCAN_TTIR_SMC_Msk        (0x1UL << FDCAN_TTIR_SMC_Pos)                /*!< 0x00000002 */
+#define FDCAN_TTIR_SMC            FDCAN_TTIR_SMC_Msk                           /*!<Start of Matrix Cycle                     */
+#define FDCAN_TTIR_CSM_Pos        (2U)
+#define FDCAN_TTIR_CSM_Msk        (0x1UL << FDCAN_TTIR_CSM_Pos)                /*!< 0x00000004 */
+#define FDCAN_TTIR_CSM            FDCAN_TTIR_CSM_Msk                           /*!<Change of Synchronization Mode            */
+#define FDCAN_TTIR_SOG_Pos        (3U)
+#define FDCAN_TTIR_SOG_Msk        (0x1UL << FDCAN_TTIR_SOG_Pos)                /*!< 0x00000008 */
+#define FDCAN_TTIR_SOG            FDCAN_TTIR_SOG_Msk                           /*!<Start of Gap                              */
+#define FDCAN_TTIR_RTMI_Pos       (4U)
+#define FDCAN_TTIR_RTMI_Msk       (0x1UL << FDCAN_TTIR_RTMI_Pos)               /*!< 0x00000010 */
+#define FDCAN_TTIR_RTMI           FDCAN_TTIR_RTMI_Msk                          /*!<Register Time Mark Interrupt              */
+#define FDCAN_TTIR_TTMI_Pos       (5U)
+#define FDCAN_TTIR_TTMI_Msk       (0x1UL << FDCAN_TTIR_TTMI_Pos)               /*!< 0x00000020 */
+#define FDCAN_TTIR_TTMI           FDCAN_TTIR_TTMI_Msk                          /*!<Trigger Time Mark Event Internal          */
+#define FDCAN_TTIR_SWE_Pos        (6U)
+#define FDCAN_TTIR_SWE_Msk        (0x1UL << FDCAN_TTIR_SWE_Pos)                /*!< 0x00000040 */
+#define FDCAN_TTIR_SWE            FDCAN_TTIR_SWE_Msk                           /*!<Stop Watch Event                          */
+#define FDCAN_TTIR_GTW_Pos        (7U)
+#define FDCAN_TTIR_GTW_Msk        (0x1UL << FDCAN_TTIR_GTW_Pos)                /*!< 0x00000080 */
+#define FDCAN_TTIR_GTW            FDCAN_TTIR_GTW_Msk                           /*!<Global Time Wrap                          */
+#define FDCAN_TTIR_GTD_Pos        (8U)
+#define FDCAN_TTIR_GTD_Msk        (0x1UL << FDCAN_TTIR_GTD_Pos)                /*!< 0x00000100 */
+#define FDCAN_TTIR_GTD            FDCAN_TTIR_GTD_Msk                           /*!<Global Time Discontinuity                 */
+#define FDCAN_TTIR_GTE_Pos        (9U)
+#define FDCAN_TTIR_GTE_Msk        (0x1UL << FDCAN_TTIR_GTE_Pos)                /*!< 0x00000200 */
+#define FDCAN_TTIR_GTE            FDCAN_TTIR_GTE_Msk                           /*!<Global Time Error                         */
+#define FDCAN_TTIR_TXU_Pos        (10U)
+#define FDCAN_TTIR_TXU_Msk        (0x1UL << FDCAN_TTIR_TXU_Pos)                /*!< 0x00000400 */
+#define FDCAN_TTIR_TXU            FDCAN_TTIR_TXU_Msk                           /*!<Tx Count Underflow                        */
+#define FDCAN_TTIR_TXO_Pos        (11U)
+#define FDCAN_TTIR_TXO_Msk        (0x1UL << FDCAN_TTIR_TXO_Pos)                /*!< 0x00000800 */
+#define FDCAN_TTIR_TXO            FDCAN_TTIR_TXO_Msk                           /*!<Tx Count Overflow                         */
+#define FDCAN_TTIR_SE1_Pos        (12U)
+#define FDCAN_TTIR_SE1_Msk        (0x1UL << FDCAN_TTIR_SE1_Pos)                /*!< 0x00001000 */
+#define FDCAN_TTIR_SE1            FDCAN_TTIR_SE1_Msk                           /*!<Scheduling Error 1                        */
+#define FDCAN_TTIR_SE2_Pos        (13U)
+#define FDCAN_TTIR_SE2_Msk        (0x1UL << FDCAN_TTIR_SE2_Pos)                /*!< 0x00002000 */
+#define FDCAN_TTIR_SE2            FDCAN_TTIR_SE2_Msk                           /*!<Scheduling Error 2                        */
+#define FDCAN_TTIR_ELC_Pos        (14U)
+#define FDCAN_TTIR_ELC_Msk        (0x1UL << FDCAN_TTIR_ELC_Pos)                /*!< 0x00004000 */
+#define FDCAN_TTIR_ELC            FDCAN_TTIR_ELC_Msk                           /*!<Error Level Changed                       */
+#define FDCAN_TTIR_IWT_Pos        (15U)
+#define FDCAN_TTIR_IWT_Msk        (0x1UL << FDCAN_TTIR_IWT_Pos)                /*!< 0x00008000 */
+#define FDCAN_TTIR_IWT            FDCAN_TTIR_IWT_Msk                           /*!<Initialization Watch Trigger              */
+#define FDCAN_TTIR_WT_Pos         (16U)
+#define FDCAN_TTIR_WT_Msk         (0x1UL << FDCAN_TTIR_WT_Pos)                 /*!< 0x00010000 */
+#define FDCAN_TTIR_WT             FDCAN_TTIR_WT_Msk                            /*!<Watch Trigger                             */
+#define FDCAN_TTIR_AW_Pos         (17U)
+#define FDCAN_TTIR_AW_Msk         (0x1UL << FDCAN_TTIR_AW_Pos)                 /*!< 0x00020000 */
+#define FDCAN_TTIR_AW             FDCAN_TTIR_AW_Msk                            /*!<Application Watchdog                      */
+#define FDCAN_TTIR_CER_Pos        (18U)
+#define FDCAN_TTIR_CER_Msk        (0x1UL << FDCAN_TTIR_CER_Pos)                /*!< 0x00040000 */
+#define FDCAN_TTIR_CER            FDCAN_TTIR_CER_Msk                           /*!<Configuration Error                       */
+
+/*****************  Bit definition for FDCAN_TTIE register  ********************/
+#define FDCAN_TTIE_SBCE_Pos       (0U)
+#define FDCAN_TTIE_SBCE_Msk       (0x1UL << FDCAN_TTIE_SBCE_Pos)               /*!< 0x00000001 */
+#define FDCAN_TTIE_SBCE           FDCAN_TTIE_SBCE_Msk                          /*!<Start of Basic Cycle Interrupt Enable             */
+#define FDCAN_TTIE_SMCE_Pos       (1U)
+#define FDCAN_TTIE_SMCE_Msk       (0x1UL << FDCAN_TTIE_SMCE_Pos)               /*!< 0x00000002 */
+#define FDCAN_TTIE_SMCE           FDCAN_TTIE_SMCE_Msk                          /*!<Start of Matrix Cycle Interrupt Enable            */
+#define FDCAN_TTIE_CSME_Pos       (2U)
+#define FDCAN_TTIE_CSME_Msk       (0x1UL << FDCAN_TTIE_CSME_Pos)               /*!< 0x00000004 */
+#define FDCAN_TTIE_CSME           FDCAN_TTIE_CSME_Msk                          /*!<Change of Synchronization Mode Interrupt Enable   */
+#define FDCAN_TTIE_SOGE_Pos       (3U)
+#define FDCAN_TTIE_SOGE_Msk       (0x1UL << FDCAN_TTIE_SOGE_Pos)               /*!< 0x00000008 */
+#define FDCAN_TTIE_SOGE           FDCAN_TTIE_SOGE_Msk                          /*!<Start of Gap Interrupt Enable                     */
+#define FDCAN_TTIE_RTMIE_Pos      (4U)
+#define FDCAN_TTIE_RTMIE_Msk      (0x1UL << FDCAN_TTIE_RTMIE_Pos)              /*!< 0x00000010 */
+#define FDCAN_TTIE_RTMIE          FDCAN_TTIE_RTMIE_Msk                         /*!<Register Time Mark Interrupt Interrupt Enable     */
+#define FDCAN_TTIE_TTMIE_Pos      (5U)
+#define FDCAN_TTIE_TTMIE_Msk      (0x1UL << FDCAN_TTIE_TTMIE_Pos)              /*!< 0x00000020 */
+#define FDCAN_TTIE_TTMIE          FDCAN_TTIE_TTMIE_Msk                         /*!<Trigger Time Mark Event Internal Interrupt Enable */
+#define FDCAN_TTIE_SWEE_Pos       (6U)
+#define FDCAN_TTIE_SWEE_Msk       (0x1UL << FDCAN_TTIE_SWEE_Pos)               /*!< 0x00000040 */
+#define FDCAN_TTIE_SWEE           FDCAN_TTIE_SWEE_Msk                          /*!<Stop Watch Event Interrupt Enable                 */
+#define FDCAN_TTIE_GTWE_Pos       (7U)
+#define FDCAN_TTIE_GTWE_Msk       (0x1UL << FDCAN_TTIE_GTWE_Pos)               /*!< 0x00000080 */
+#define FDCAN_TTIE_GTWE           FDCAN_TTIE_GTWE_Msk                          /*!<Global Time Wrap Interrupt Enable                 */
+#define FDCAN_TTIE_GTDE_Pos       (8U)
+#define FDCAN_TTIE_GTDE_Msk       (0x1UL << FDCAN_TTIE_GTDE_Pos)               /*!< 0x00000100 */
+#define FDCAN_TTIE_GTDE           FDCAN_TTIE_GTDE_Msk                          /*!<Global Time Discontinuity Interrupt Enable        */
+#define FDCAN_TTIE_GTEE_Pos       (9U)
+#define FDCAN_TTIE_GTEE_Msk       (0x1UL << FDCAN_TTIE_GTEE_Pos)               /*!< 0x00000200 */
+#define FDCAN_TTIE_GTEE           FDCAN_TTIE_GTEE_Msk                          /*!<Global Time Error Interrupt Enable                */
+#define FDCAN_TTIE_TXUE_Pos       (10U)
+#define FDCAN_TTIE_TXUE_Msk       (0x1UL << FDCAN_TTIE_TXUE_Pos)               /*!< 0x00000400 */
+#define FDCAN_TTIE_TXUE           FDCAN_TTIE_TXUE_Msk                          /*!<Tx Count Underflow Interrupt Enable               */
+#define FDCAN_TTIE_TXOE_Pos       (11U)
+#define FDCAN_TTIE_TXOE_Msk       (0x1UL << FDCAN_TTIE_TXOE_Pos)               /*!< 0x00000800 */
+#define FDCAN_TTIE_TXOE           FDCAN_TTIE_TXOE_Msk                          /*!<Tx Count Overflow Interrupt Enable                */
+#define FDCAN_TTIE_SE1E_Pos       (12U)
+#define FDCAN_TTIE_SE1E_Msk       (0x1UL << FDCAN_TTIE_SE1E_Pos)               /*!< 0x00001000 */
+#define FDCAN_TTIE_SE1E           FDCAN_TTIE_SE1E_Msk                          /*!<Scheduling Error 1 Interrupt Enable               */
+#define FDCAN_TTIE_SE2E_Pos       (13U)
+#define FDCAN_TTIE_SE2E_Msk       (0x1UL << FDCAN_TTIE_SE2E_Pos)               /*!< 0x00002000 */
+#define FDCAN_TTIE_SE2E           FDCAN_TTIE_SE2E_Msk                          /*!<Scheduling Error 2 Interrupt Enable               */
+#define FDCAN_TTIE_ELCE_Pos       (14U)
+#define FDCAN_TTIE_ELCE_Msk       (0x1UL << FDCAN_TTIE_ELCE_Pos)               /*!< 0x00004000 */
+#define FDCAN_TTIE_ELCE           FDCAN_TTIE_ELCE_Msk                          /*!<Error Level Changed Interrupt Enable              */
+#define FDCAN_TTIE_IWTE_Pos       (15U)
+#define FDCAN_TTIE_IWTE_Msk       (0x1UL << FDCAN_TTIE_IWTE_Pos)               /*!< 0x00008000 */
+#define FDCAN_TTIE_IWTE           FDCAN_TTIE_IWTE_Msk                          /*!<Initialization Watch Trigger Interrupt Enable     */
+#define FDCAN_TTIE_WTE_Pos        (16U)
+#define FDCAN_TTIE_WTE_Msk        (0x1UL << FDCAN_TTIE_WTE_Pos)                /*!< 0x00010000 */
+#define FDCAN_TTIE_WTE            FDCAN_TTIE_WTE_Msk                           /*!<Watch Trigger Interrupt Enable                    */
+#define FDCAN_TTIE_AWE_Pos        (17U)
+#define FDCAN_TTIE_AWE_Msk        (0x1UL << FDCAN_TTIE_AWE_Pos)                /*!< 0x00020000 */
+#define FDCAN_TTIE_AWE            FDCAN_TTIE_AWE_Msk                           /*!<Application Watchdog Interrupt Enable             */
+#define FDCAN_TTIE_CERE_Pos       (18U)
+#define FDCAN_TTIE_CERE_Msk       (0x1UL << FDCAN_TTIE_CERE_Pos)               /*!< 0x00040000 */
+#define FDCAN_TTIE_CERE           FDCAN_TTIE_CERE_Msk                          /*!<Configuration Error Interrupt Enable              */
+
+/*****************  Bit definition for FDCAN_TTILS register  ********************/
+#define FDCAN_TTILS_SBCS_Pos      (0U)
+#define FDCAN_TTILS_SBCS_Msk      (0x1UL << FDCAN_TTILS_SBCS_Pos)              /*!< 0x00000001 */
+#define FDCAN_TTILS_SBCS          FDCAN_TTILS_SBCS_Msk                         /*!<Start of Basic Cycle Interrupt Line               */
+#define FDCAN_TTILS_SMCS_Pos      (1U)
+#define FDCAN_TTILS_SMCS_Msk      (0x1UL << FDCAN_TTILS_SMCS_Pos)              /*!< 0x00000002 */
+#define FDCAN_TTILS_SMCS          FDCAN_TTILS_SMCS_Msk                         /*!<Start of Matrix Cycle Interrupt Line              */
+#define FDCAN_TTILS_CSMS_Pos      (2U)
+#define FDCAN_TTILS_CSMS_Msk      (0x1UL << FDCAN_TTILS_CSMS_Pos)              /*!< 0x00000004 */
+#define FDCAN_TTILS_CSMS          FDCAN_TTILS_CSMS_Msk                         /*!<Change of Synchronization Mode Interrupt Line     */
+#define FDCAN_TTILS_SOGS_Pos      (3U)
+#define FDCAN_TTILS_SOGS_Msk      (0x1UL << FDCAN_TTILS_SOGS_Pos)              /*!< 0x00000008 */
+#define FDCAN_TTILS_SOGS          FDCAN_TTILS_SOGS_Msk                         /*!<Start of Gap Interrupt Line                       */
+#define FDCAN_TTILS_RTMIS_Pos     (4U)
+#define FDCAN_TTILS_RTMIS_Msk     (0x1UL << FDCAN_TTILS_RTMIS_Pos)             /*!< 0x00000010 */
+#define FDCAN_TTILS_RTMIS         FDCAN_TTILS_RTMIS_Msk                        /*!<Register Time Mark Interrupt Interrupt Line       */
+#define FDCAN_TTILS_TTMIS_Pos     (5U)
+#define FDCAN_TTILS_TTMIS_Msk     (0x1UL << FDCAN_TTILS_TTMIS_Pos)             /*!< 0x00000020 */
+#define FDCAN_TTILS_TTMIS         FDCAN_TTILS_TTMIS_Msk                        /*!<Trigger Time Mark Event Internal Interrupt Line   */
+#define FDCAN_TTILS_SWES_Pos      (6U)
+#define FDCAN_TTILS_SWES_Msk      (0x1UL << FDCAN_TTILS_SWES_Pos)              /*!< 0x00000040 */
+#define FDCAN_TTILS_SWES          FDCAN_TTILS_SWES_Msk                         /*!<Stop Watch Event Interrupt Line                   */
+#define FDCAN_TTILS_GTWS_Pos      (7U)
+#define FDCAN_TTILS_GTWS_Msk      (0x1UL << FDCAN_TTILS_GTWS_Pos)              /*!< 0x00000080 */
+#define FDCAN_TTILS_GTWS          FDCAN_TTILS_GTWS_Msk                         /*!<Global Time Wrap Interrupt Line                   */
+#define FDCAN_TTILS_GTDS_Pos      (8U)
+#define FDCAN_TTILS_GTDS_Msk      (0x1UL << FDCAN_TTILS_GTDS_Pos)              /*!< 0x00000100 */
+#define FDCAN_TTILS_GTDS          FDCAN_TTILS_GTDS_Msk                         /*!<Global Time Discontinuity Interrupt Line          */
+#define FDCAN_TTILS_GTES_Pos      (9U)
+#define FDCAN_TTILS_GTES_Msk      (0x1UL << FDCAN_TTILS_GTES_Pos)              /*!< 0x00000200 */
+#define FDCAN_TTILS_GTES          FDCAN_TTILS_GTES_Msk                         /*!<Global Time Error Interrupt Line                  */
+#define FDCAN_TTILS_TXUS_Pos      (10U)
+#define FDCAN_TTILS_TXUS_Msk      (0x1UL << FDCAN_TTILS_TXUS_Pos)              /*!< 0x00000400 */
+#define FDCAN_TTILS_TXUS          FDCAN_TTILS_TXUS_Msk                         /*!<Tx Count Underflow Interrupt Line                 */
+#define FDCAN_TTILS_TXOS_Pos      (11U)
+#define FDCAN_TTILS_TXOS_Msk      (0x1UL << FDCAN_TTILS_TXOS_Pos)              /*!< 0x00000800 */
+#define FDCAN_TTILS_TXOS          FDCAN_TTILS_TXOS_Msk                         /*!<Tx Count Overflow Interrupt Line                  */
+#define FDCAN_TTILS_SE1S_Pos      (12U)
+#define FDCAN_TTILS_SE1S_Msk      (0x1UL << FDCAN_TTILS_SE1S_Pos)              /*!< 0x00001000 */
+#define FDCAN_TTILS_SE1S          FDCAN_TTILS_SE1S_Msk                         /*!<Scheduling Error 1 Interrupt Line                 */
+#define FDCAN_TTILS_SE2S_Pos      (13U)
+#define FDCAN_TTILS_SE2S_Msk      (0x1UL << FDCAN_TTILS_SE2S_Pos)              /*!< 0x00002000 */
+#define FDCAN_TTILS_SE2S          FDCAN_TTILS_SE2S_Msk                         /*!<Scheduling Error 2 Interrupt Line                 */
+#define FDCAN_TTILS_ELCS_Pos      (14U)
+#define FDCAN_TTILS_ELCS_Msk      (0x1UL << FDCAN_TTILS_ELCS_Pos)              /*!< 0x00004000 */
+#define FDCAN_TTILS_ELCS          FDCAN_TTILS_ELCS_Msk                         /*!<Error Level Changed Interrupt Line                */
+#define FDCAN_TTILS_IWTS_Pos      (15U)
+#define FDCAN_TTILS_IWTS_Msk      (0x1UL << FDCAN_TTILS_IWTS_Pos)              /*!< 0x00008000 */
+#define FDCAN_TTILS_IWTS          FDCAN_TTILS_IWTS_Msk                         /*!<Initialization Watch Trigger Interrupt Line       */
+#define FDCAN_TTILS_WTS_Pos       (16U)
+#define FDCAN_TTILS_WTS_Msk       (0x1UL << FDCAN_TTILS_WTS_Pos)               /*!< 0x00010000 */
+#define FDCAN_TTILS_WTS           FDCAN_TTILS_WTS_Msk                          /*!<Watch Trigger Interrupt Line                      */
+#define FDCAN_TTILS_AWS_Pos       (17U)
+#define FDCAN_TTILS_AWS_Msk       (0x1UL << FDCAN_TTILS_AWS_Pos)               /*!< 0x00020000 */
+#define FDCAN_TTILS_AWS           FDCAN_TTILS_AWS_Msk                          /*!<Application Watchdog Interrupt Line               */
+#define FDCAN_TTILS_CERS_Pos      (18U)
+#define FDCAN_TTILS_CERS_Msk      (0x1UL << FDCAN_TTILS_CERS_Pos)              /*!< 0x00040000 */
+#define FDCAN_TTILS_CERS          FDCAN_TTILS_CERS_Msk                         /*!<Configuration Error Interrupt Line                */
+
+/*****************  Bit definition for FDCAN_TTOST register  ********************/
+#define FDCAN_TTOST_EL_Pos        (0U)
+#define FDCAN_TTOST_EL_Msk        (0x3UL << FDCAN_TTOST_EL_Pos)                /*!< 0x00000003 */
+#define FDCAN_TTOST_EL            FDCAN_TTOST_EL_Msk                           /*!<Error Level                              */
+#define FDCAN_TTOST_MS_Pos        (2U)
+#define FDCAN_TTOST_MS_Msk        (0x3UL << FDCAN_TTOST_MS_Pos)                /*!< 0x0000000C */
+#define FDCAN_TTOST_MS            FDCAN_TTOST_MS_Msk                           /*!<Master State                             */
+#define FDCAN_TTOST_SYS_Pos       (4U)
+#define FDCAN_TTOST_SYS_Msk       (0x3UL << FDCAN_TTOST_SYS_Pos)               /*!< 0x00000030 */
+#define FDCAN_TTOST_SYS           FDCAN_TTOST_SYS_Msk                          /*!<Synchronization State                    */
+#define FDCAN_TTOST_QGTP_Pos      (6U)
+#define FDCAN_TTOST_QGTP_Msk      (0x1UL << FDCAN_TTOST_QGTP_Pos)              /*!< 0x00000040 */
+#define FDCAN_TTOST_QGTP          FDCAN_TTOST_QGTP_Msk                         /*!<Quality of Global Time Phase             */
+#define FDCAN_TTOST_QCS_Pos       (7U)
+#define FDCAN_TTOST_QCS_Msk       (0x1UL << FDCAN_TTOST_QCS_Pos)               /*!< 0x00000080 */
+#define FDCAN_TTOST_QCS           FDCAN_TTOST_QCS_Msk                          /*!<Quality of Clock Speed                   */
+#define FDCAN_TTOST_RTO_Pos       (8U)
+#define FDCAN_TTOST_RTO_Msk       (0xFFUL << FDCAN_TTOST_RTO_Pos)              /*!< 0x0000FF00 */
+#define FDCAN_TTOST_RTO           FDCAN_TTOST_RTO_Msk                          /*!<Reference Trigger Offset                 */
+#define FDCAN_TTOST_WGTD_Pos      (22U)
+#define FDCAN_TTOST_WGTD_Msk      (0x1UL << FDCAN_TTOST_WGTD_Pos)              /*!< 0x00400000 */
+#define FDCAN_TTOST_WGTD          FDCAN_TTOST_WGTD_Msk                         /*!<Wait for Global Time Discontinuity       */
+#define FDCAN_TTOST_GFI_Pos       (23U)
+#define FDCAN_TTOST_GFI_Msk       (0x1UL << FDCAN_TTOST_GFI_Pos)               /*!< 0x00800000 */
+#define FDCAN_TTOST_GFI           FDCAN_TTOST_GFI_Msk                          /*!<Gap Finished Indicator                   */
+#define FDCAN_TTOST_TMP_Pos       (24U)
+#define FDCAN_TTOST_TMP_Msk       (0x7UL << FDCAN_TTOST_TMP_Pos)               /*!< 0x07000000 */
+#define FDCAN_TTOST_TMP           FDCAN_TTOST_TMP_Msk                          /*!<Time Master Priority                     */
+#define FDCAN_TTOST_GSI_Pos       (27U)
+#define FDCAN_TTOST_GSI_Msk       (0x1UL << FDCAN_TTOST_GSI_Pos)               /*!< 0x08000000 */
+#define FDCAN_TTOST_GSI           FDCAN_TTOST_GSI_Msk                          /*!<Gap Started Indicator                    */
+#define FDCAN_TTOST_WFE_Pos       (28U)
+#define FDCAN_TTOST_WFE_Msk       (0x1UL << FDCAN_TTOST_WFE_Pos)               /*!< 0x10000000 */
+#define FDCAN_TTOST_WFE           FDCAN_TTOST_WFE_Msk                          /*!<Wait for Event                           */
+#define FDCAN_TTOST_AWE_Pos       (29U)
+#define FDCAN_TTOST_AWE_Msk       (0x1UL << FDCAN_TTOST_AWE_Pos)               /*!< 0x20000000 */
+#define FDCAN_TTOST_AWE           FDCAN_TTOST_AWE_Msk                          /*!<Application Watchdog Event               */
+#define FDCAN_TTOST_WECS_Pos      (30U)
+#define FDCAN_TTOST_WECS_Msk      (0x1UL << FDCAN_TTOST_WECS_Pos)              /*!< 0x40000000 */
+#define FDCAN_TTOST_WECS          FDCAN_TTOST_WECS_Msk                         /*!<Wait for External Clock Synchronization  */
+#define FDCAN_TTOST_SPL_Pos       (31U)
+#define FDCAN_TTOST_SPL_Msk       (0x1UL << FDCAN_TTOST_SPL_Pos)               /*!< 0x80000000 */
+#define FDCAN_TTOST_SPL           FDCAN_TTOST_SPL_Msk                          /*!<Schedule Phase Lock                      */
+
+/*****************  Bit definition for FDCAN_TURNA register  ********************/
+#define FDCAN_TURNA_NAV_Pos       (0U)
+#define FDCAN_TURNA_NAV_Msk       (0x3FFFFUL << FDCAN_TURNA_NAV_Pos)           /*!< 0x0003FFFF */
+#define FDCAN_TURNA_NAV           FDCAN_TURNA_NAV_Msk                          /*!<Numerator Actual Value                   */
+
+/*****************  Bit definition for FDCAN_TTLGT register  ********************/
+#define FDCAN_TTLGT_LT_Pos        (0U)
+#define FDCAN_TTLGT_LT_Msk        (0xFFFFUL << FDCAN_TTLGT_LT_Pos)             /*!< 0x0000FFFF */
+#define FDCAN_TTLGT_LT            FDCAN_TTLGT_LT_Msk                           /*!<Local Time                               */
+#define FDCAN_TTLGT_GT_Pos        (16U)
+#define FDCAN_TTLGT_GT_Msk        (0xFFFFUL << FDCAN_TTLGT_GT_Pos)             /*!< 0xFFFF0000 */
+#define FDCAN_TTLGT_GT            FDCAN_TTLGT_GT_Msk                           /*!<Global Time                              */
+
+/*****************  Bit definition for FDCAN_TTCTC register  ********************/
+#define FDCAN_TTCTC_CT_Pos        (0U)
+#define FDCAN_TTCTC_CT_Msk        (0xFFFFUL << FDCAN_TTCTC_CT_Pos)             /*!< 0x0000FFFF */
+#define FDCAN_TTCTC_CT            FDCAN_TTCTC_CT_Msk                           /*!<Cycle Time                               */
+#define FDCAN_TTCTC_CC_Pos        (16U)
+#define FDCAN_TTCTC_CC_Msk        (0x3FUL << FDCAN_TTCTC_CC_Pos)               /*!< 0x003F0000 */
+#define FDCAN_TTCTC_CC            FDCAN_TTCTC_CC_Msk                           /*!<Cycle Count                              */
+
+/*****************  Bit definition for FDCAN_TTCPT register  ********************/
+#define FDCAN_TTCPT_CCV_Pos       (0U)
+#define FDCAN_TTCPT_CCV_Msk       (0x3FUL << FDCAN_TTCPT_CCV_Pos)              /*!< 0x0000003F */
+#define FDCAN_TTCPT_CCV           FDCAN_TTCPT_CCV_Msk                          /*!<Cycle Count Value                        */
+#define FDCAN_TTCPT_SWV_Pos       (16U)
+#define FDCAN_TTCPT_SWV_Msk       (0xFFFFUL << FDCAN_TTCPT_SWV_Pos)            /*!< 0xFFFF0000 */
+#define FDCAN_TTCPT_SWV           FDCAN_TTCPT_SWV_Msk                          /*!<Stop Watch Value                         */
+
+/*****************  Bit definition for FDCAN_TTCSM register  ********************/
+#define FDCAN_TTCSM_CSM_Pos       (0U)
+#define FDCAN_TTCSM_CSM_Msk       (0xFFFFUL << FDCAN_TTCSM_CSM_Pos)            /*!< 0x0000FFFF */
+#define FDCAN_TTCSM_CSM           FDCAN_TTCSM_CSM_Msk                          /*!<Cycle Sync Mark                          */
+
+/*****************  Bit definition for FDCAN_TTTS register  *********************/
+#define FDCAN_TTTS_SWTSEL_Pos     (0U)
+#define FDCAN_TTTS_SWTSEL_Msk     (0x3UL << FDCAN_TTTS_SWTSEL_Pos)             /*!< 0x00000003 */
+#define FDCAN_TTTS_SWTSEL         FDCAN_TTTS_SWTSEL_Msk                        /*!<Stop watch trigger input selection       */
+#define FDCAN_TTTS_EVTSEL_Pos     (4U)
+#define FDCAN_TTTS_EVTSEL_Msk     (0x3UL << FDCAN_TTTS_EVTSEL_Pos)             /*!< 0x00000030 */
+#define FDCAN_TTTS_EVTSEL         FDCAN_TTTS_EVTSEL_Msk                        /*!<Event trigger input selection            */
+
+/********************************************************************************/
+/*                                                                              */
+/*                      FDCANCCU (Clock Calibration unit)                       */
+/*                                                                              */
+/********************************************************************************/
+
+/*****************  Bit definition for FDCANCCU_CREL register  ******************/
+#define FDCANCCU_CREL_DAY_Pos        (0U)
+#define FDCANCCU_CREL_DAY_Msk        (0xFFUL << FDCANCCU_CREL_DAY_Pos)         /*!< 0x000000FF */
+#define FDCANCCU_CREL_DAY            FDCANCCU_CREL_DAY_Msk                     /*!<Timestamp Day                           */
+#define FDCANCCU_CREL_MON_Pos        (8U)
+#define FDCANCCU_CREL_MON_Msk        (0xFFUL << FDCANCCU_CREL_MON_Pos)         /*!< 0x0000FF00 */
+#define FDCANCCU_CREL_MON            FDCANCCU_CREL_MON_Msk                     /*!<Timestamp Month                         */
+#define FDCANCCU_CREL_YEAR_Pos       (16U)
+#define FDCANCCU_CREL_YEAR_Msk       (0xFUL << FDCANCCU_CREL_YEAR_Pos)         /*!< 0x000F0000 */
+#define FDCANCCU_CREL_YEAR           FDCANCCU_CREL_YEAR_Msk                    /*!<Timestamp Year                          */
+#define FDCANCCU_CREL_SUBSTEP_Pos    (20U)
+#define FDCANCCU_CREL_SUBSTEP_Msk    (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos)      /*!< 0x00F00000 */
+#define FDCANCCU_CREL_SUBSTEP        FDCANCCU_CREL_SUBSTEP_Msk                 /*!<Sub-step of Core release                */
+#define FDCANCCU_CREL_STEP_Pos       (24U)
+#define FDCANCCU_CREL_STEP_Msk       (0xFUL << FDCANCCU_CREL_STEP_Pos)         /*!< 0x0F000000 */
+#define FDCANCCU_CREL_STEP           FDCANCCU_CREL_STEP_Msk                    /*!<Step of Core release                    */
+#define FDCANCCU_CREL_REL_Pos        (28U)
+#define FDCANCCU_CREL_REL_Msk        (0xFUL << FDCANCCU_CREL_REL_Pos)          /*!< 0xF0000000 */
+#define FDCANCCU_CREL_REL            FDCANCCU_CREL_REL_Msk                     /*!<Core release                            */
+
+/*****************  Bit definition for FDCANCCU_CCFG register  ******************/
+#define FDCANCCU_CCFG_TQBT_Pos       (0U)
+#define FDCANCCU_CCFG_TQBT_Msk       (0x1FUL << FDCANCCU_CCFG_TQBT_Pos)        /*!< 0x0000001F */
+#define FDCANCCU_CCFG_TQBT           FDCANCCU_CCFG_TQBT_Msk                    /*!<Time Quanta per Bit Time                */
+#define FDCANCCU_CCFG_BCC_Pos        (6U)
+#define FDCANCCU_CCFG_BCC_Msk        (0x1UL << FDCANCCU_CCFG_BCC_Pos)          /*!< 0x00000040 */
+#define FDCANCCU_CCFG_BCC            FDCANCCU_CCFG_BCC_Msk                     /*!<Bypass Clock Calibration                */
+#define FDCANCCU_CCFG_CFL_Pos        (7U)
+#define FDCANCCU_CCFG_CFL_Msk        (0x1UL << FDCANCCU_CCFG_CFL_Pos)          /*!< 0x00000080 */
+#define FDCANCCU_CCFG_CFL            FDCANCCU_CCFG_CFL_Msk                     /*!<Calibration Field Length                */
+#define FDCANCCU_CCFG_OCPM_Pos       (8U)
+#define FDCANCCU_CCFG_OCPM_Msk       (0xFFUL << FDCANCCU_CCFG_OCPM_Pos)        /*!< 0x0000FF00 */
+#define FDCANCCU_CCFG_OCPM           FDCANCCU_CCFG_OCPM_Msk                    /*!<Oscillator Clock Periods Minimum        */
+#define FDCANCCU_CCFG_CDIV_Pos       (16U)
+#define FDCANCCU_CCFG_CDIV_Msk       (0xFUL << FDCANCCU_CCFG_CDIV_Pos)         /*!< 0x000F0000 */
+#define FDCANCCU_CCFG_CDIV           FDCANCCU_CCFG_CDIV_Msk                    /*!<Clock Divider                           */
+#define FDCANCCU_CCFG_SWR_Pos        (31U)
+#define FDCANCCU_CCFG_SWR_Msk        (0x1UL << FDCANCCU_CCFG_SWR_Pos)          /*!< 0x80000000 */
+#define FDCANCCU_CCFG_SWR            FDCANCCU_CCFG_SWR_Msk                     /*!<Software Reset                          */
+
+/*****************  Bit definition for FDCANCCU_CSTAT register  *****************/
+#define FDCANCCU_CSTAT_OCPC_Pos      (0U)
+#define FDCANCCU_CSTAT_OCPC_Msk      (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos)    /*!< 0x0003FFFF */
+#define FDCANCCU_CSTAT_OCPC          FDCANCCU_CSTAT_OCPC_Msk                   /*!<Oscillator Clock Period Counter        */
+#define FDCANCCU_CSTAT_TQC_Pos       (18U)
+#define FDCANCCU_CSTAT_TQC_Msk       (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos)       /*!< 0x1FFC0000 */
+#define FDCANCCU_CSTAT_TQC           FDCANCCU_CSTAT_TQC_Msk                    /*!<Time Quanta Counter                    */
+#define FDCANCCU_CSTAT_CALS_Pos      (30U)
+#define FDCANCCU_CSTAT_CALS_Msk      (0x3UL << FDCANCCU_CSTAT_CALS_Pos)        /*!< 0xC0000000 */
+#define FDCANCCU_CSTAT_CALS          FDCANCCU_CSTAT_CALS_Msk                   /*!<Calibration State                      */
+
+/******************  Bit definition for FDCANCCU_CWD register  ******************/
+#define FDCANCCU_CWD_WDC_Pos         (0U)
+#define FDCANCCU_CWD_WDC_Msk         (0xFFFFUL << FDCANCCU_CWD_WDC_Pos)        /*!< 0x0000FFFF */
+#define FDCANCCU_CWD_WDC             FDCANCCU_CWD_WDC_Msk                      /*!<Watchdog Configuration                 */
+#define FDCANCCU_CWD_WDV_Pos         (16U)
+#define FDCANCCU_CWD_WDV_Msk         (0xFFFFUL << FDCANCCU_CWD_WDV_Pos)        /*!< 0xFFFF0000 */
+#define FDCANCCU_CWD_WDV             FDCANCCU_CWD_WDV_Msk                      /*!<Watchdog Value                         */
+
+/******************  Bit definition for FDCANCCU_IR register  *******************/
+#define FDCANCCU_IR_CWE_Pos          (0U)
+#define FDCANCCU_IR_CWE_Msk          (0x1UL << FDCANCCU_IR_CWE_Pos)            /*!< 0x00000001 */
+#define FDCANCCU_IR_CWE              FDCANCCU_IR_CWE_Msk                       /*!<Calibration Watchdog Event             */
+#define FDCANCCU_IR_CSC_Pos          (1U)
+#define FDCANCCU_IR_CSC_Msk          (0x1UL << FDCANCCU_IR_CSC_Pos)            /*!< 0x00000002 */
+#define FDCANCCU_IR_CSC              FDCANCCU_IR_CSC_Msk                       /*!<Calibration State Changed              */
+
+/******************  Bit definition for FDCANCCU_IE register  *******************/
+#define FDCANCCU_IE_CWEE_Pos         (0U)
+#define FDCANCCU_IE_CWEE_Msk         (0x1UL << FDCANCCU_IE_CWEE_Pos)           /*!< 0x00000001 */
+#define FDCANCCU_IE_CWEE             FDCANCCU_IE_CWEE_Msk                      /*!<Calibration Watchdog Event Enable      */
+#define FDCANCCU_IE_CSCE_Pos         (1U)
+#define FDCANCCU_IE_CSCE_Msk         (0x1UL << FDCANCCU_IE_CSCE_Pos)           /*!< 0x00000002 */
+#define FDCANCCU_IE_CSCE             FDCANCCU_IE_CSCE_Msk                      /*!<Calibration State Changed Enable       */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          HDMI-CEC (CEC)                                    */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for CEC_CR register  *********************/
+#define CEC_CR_CECEN_Pos         (0U)
+#define CEC_CR_CECEN_Msk         (0x1UL << CEC_CR_CECEN_Pos)                   /*!< 0x00000001 */
+#define CEC_CR_CECEN             CEC_CR_CECEN_Msk                              /*!< CEC Enable                                */
+#define CEC_CR_TXSOM_Pos         (1U)
+#define CEC_CR_TXSOM_Msk         (0x1UL << CEC_CR_TXSOM_Pos)                   /*!< 0x00000002 */
+#define CEC_CR_TXSOM             CEC_CR_TXSOM_Msk                              /*!< CEC Tx Start Of Message                   */
+#define CEC_CR_TXEOM_Pos         (2U)
+#define CEC_CR_TXEOM_Msk         (0x1UL << CEC_CR_TXEOM_Pos)                   /*!< 0x00000004 */
+#define CEC_CR_TXEOM             CEC_CR_TXEOM_Msk                              /*!< CEC Tx End Of Message                     */
+
+/*******************  Bit definition for CEC_CFGR register  *******************/
+#define CEC_CFGR_SFT_Pos         (0U)
+#define CEC_CFGR_SFT_Msk         (0x7UL << CEC_CFGR_SFT_Pos)                   /*!< 0x00000007 */
+#define CEC_CFGR_SFT             CEC_CFGR_SFT_Msk                              /*!< CEC Signal Free Time                      */
+#define CEC_CFGR_RXTOL_Pos       (3U)
+#define CEC_CFGR_RXTOL_Msk       (0x1UL << CEC_CFGR_RXTOL_Pos)                 /*!< 0x00000008 */
+#define CEC_CFGR_RXTOL           CEC_CFGR_RXTOL_Msk                            /*!< CEC Tolerance                             */
+#define CEC_CFGR_BRESTP_Pos      (4U)
+#define CEC_CFGR_BRESTP_Msk      (0x1UL << CEC_CFGR_BRESTP_Pos)                /*!< 0x00000010 */
+#define CEC_CFGR_BRESTP          CEC_CFGR_BRESTP_Msk                           /*!< CEC Rx Stop                               */
+#define CEC_CFGR_BREGEN_Pos      (5U)
+#define CEC_CFGR_BREGEN_Msk      (0x1UL << CEC_CFGR_BREGEN_Pos)                /*!< 0x00000020 */
+#define CEC_CFGR_BREGEN          CEC_CFGR_BREGEN_Msk                           /*!< CEC Bit Rising Error generation           */
+#define CEC_CFGR_LBPEGEN_Pos     (6U)
+#define CEC_CFGR_LBPEGEN_Msk     (0x1UL << CEC_CFGR_LBPEGEN_Pos)               /*!< 0x00000040 */
+#define CEC_CFGR_LBPEGEN         CEC_CFGR_LBPEGEN_Msk                          /*!< CEC Long Bit Period Error generation      */
+#define CEC_CFGR_SFTOPT_Pos      (8U)
+#define CEC_CFGR_SFTOPT_Msk      (0x1UL << CEC_CFGR_SFTOPT_Pos)                /*!< 0x00000100 */
+#define CEC_CFGR_SFTOPT          CEC_CFGR_SFTOPT_Msk                           /*!< CEC Signal Free Time optional             */
+#define CEC_CFGR_BRDNOGEN_Pos    (7U)
+#define CEC_CFGR_BRDNOGEN_Msk    (0x1UL << CEC_CFGR_BRDNOGEN_Pos)              /*!< 0x00000080 */
+#define CEC_CFGR_BRDNOGEN        CEC_CFGR_BRDNOGEN_Msk                         /*!< CEC Broadcast No error generation         */
+#define CEC_CFGR_OAR_Pos         (16U)
+#define CEC_CFGR_OAR_Msk         (0x7FFFUL << CEC_CFGR_OAR_Pos)                /*!< 0x7FFF0000 */
+#define CEC_CFGR_OAR             CEC_CFGR_OAR_Msk                              /*!< CEC Own Address                           */
+#define CEC_CFGR_LSTN_Pos        (31U)
+#define CEC_CFGR_LSTN_Msk        (0x1UL << CEC_CFGR_LSTN_Pos)                  /*!< 0x80000000 */
+#define CEC_CFGR_LSTN            CEC_CFGR_LSTN_Msk                             /*!< CEC Listen mode                           */
+
+/*******************  Bit definition for CEC_TXDR register  *******************/
+#define CEC_TXDR_TXD_Pos         (0U)
+#define CEC_TXDR_TXD_Msk         (0xFFUL << CEC_TXDR_TXD_Pos)                  /*!< 0x000000FF */
+#define CEC_TXDR_TXD             CEC_TXDR_TXD_Msk                              /*!< CEC Tx Data                               */
+
+/*******************  Bit definition for CEC_RXDR register  *******************/
+#define CEC_RXDR_RXD_Pos         (0U)
+#define CEC_RXDR_RXD_Msk         (0xFFUL << CEC_RXDR_RXD_Pos)                  /*!< 0x000000FF */
+#define CEC_RXDR_RXD             CEC_RXDR_RXD_Msk                              /*!< CEC Rx Data                               */
+
+/*******************  Bit definition for CEC_ISR register  ********************/
+#define CEC_ISR_RXBR_Pos         (0U)
+#define CEC_ISR_RXBR_Msk         (0x1UL << CEC_ISR_RXBR_Pos)                   /*!< 0x00000001 */
+#define CEC_ISR_RXBR             CEC_ISR_RXBR_Msk                              /*!< CEC Rx-Byte Received                      */
+#define CEC_ISR_RXEND_Pos        (1U)
+#define CEC_ISR_RXEND_Msk        (0x1UL << CEC_ISR_RXEND_Pos)                  /*!< 0x00000002 */
+#define CEC_ISR_RXEND            CEC_ISR_RXEND_Msk                             /*!< CEC End Of Reception                      */
+#define CEC_ISR_RXOVR_Pos        (2U)
+#define CEC_ISR_RXOVR_Msk        (0x1UL << CEC_ISR_RXOVR_Pos)                  /*!< 0x00000004 */
+#define CEC_ISR_RXOVR            CEC_ISR_RXOVR_Msk                             /*!< CEC Rx-Overrun                            */
+#define CEC_ISR_BRE_Pos          (3U)
+#define CEC_ISR_BRE_Msk          (0x1UL << CEC_ISR_BRE_Pos)                    /*!< 0x00000008 */
+#define CEC_ISR_BRE              CEC_ISR_BRE_Msk                               /*!< CEC Rx Bit Rising Error                   */
+#define CEC_ISR_SBPE_Pos         (4U)
+#define CEC_ISR_SBPE_Msk         (0x1UL << CEC_ISR_SBPE_Pos)                   /*!< 0x00000010 */
+#define CEC_ISR_SBPE             CEC_ISR_SBPE_Msk                              /*!< CEC Rx Short Bit period Error             */
+#define CEC_ISR_LBPE_Pos         (5U)
+#define CEC_ISR_LBPE_Msk         (0x1UL << CEC_ISR_LBPE_Pos)                   /*!< 0x00000020 */
+#define CEC_ISR_LBPE             CEC_ISR_LBPE_Msk                              /*!< CEC Rx Long Bit period Error              */
+#define CEC_ISR_RXACKE_Pos       (6U)
+#define CEC_ISR_RXACKE_Msk       (0x1UL << CEC_ISR_RXACKE_Pos)                 /*!< 0x00000040 */
+#define CEC_ISR_RXACKE           CEC_ISR_RXACKE_Msk                            /*!< CEC Rx Missing Acknowledge                */
+#define CEC_ISR_ARBLST_Pos       (7U)
+#define CEC_ISR_ARBLST_Msk       (0x1UL << CEC_ISR_ARBLST_Pos)                 /*!< 0x00000080 */
+#define CEC_ISR_ARBLST           CEC_ISR_ARBLST_Msk                            /*!< CEC Arbitration Lost                      */
+#define CEC_ISR_TXBR_Pos         (8U)
+#define CEC_ISR_TXBR_Msk         (0x1UL << CEC_ISR_TXBR_Pos)                   /*!< 0x00000100 */
+#define CEC_ISR_TXBR             CEC_ISR_TXBR_Msk                              /*!< CEC Tx Byte Request                       */
+#define CEC_ISR_TXEND_Pos        (9U)
+#define CEC_ISR_TXEND_Msk        (0x1UL << CEC_ISR_TXEND_Pos)                  /*!< 0x00000200 */
+#define CEC_ISR_TXEND            CEC_ISR_TXEND_Msk                             /*!< CEC End of Transmission                   */
+#define CEC_ISR_TXUDR_Pos        (10U)
+#define CEC_ISR_TXUDR_Msk        (0x1UL << CEC_ISR_TXUDR_Pos)                  /*!< 0x00000400 */
+#define CEC_ISR_TXUDR            CEC_ISR_TXUDR_Msk                             /*!< CEC Tx-Buffer Underrun                    */
+#define CEC_ISR_TXERR_Pos        (11U)
+#define CEC_ISR_TXERR_Msk        (0x1UL << CEC_ISR_TXERR_Pos)                  /*!< 0x00000800 */
+#define CEC_ISR_TXERR            CEC_ISR_TXERR_Msk                             /*!< CEC Tx-Error                              */
+#define CEC_ISR_TXACKE_Pos       (12U)
+#define CEC_ISR_TXACKE_Msk       (0x1UL << CEC_ISR_TXACKE_Pos)                 /*!< 0x00001000 */
+#define CEC_ISR_TXACKE           CEC_ISR_TXACKE_Msk                            /*!< CEC Tx Missing Acknowledge                */
+
+/*******************  Bit definition for CEC_IER register  ********************/
+#define CEC_IER_RXBRIE_Pos       (0U)
+#define CEC_IER_RXBRIE_Msk       (0x1UL << CEC_IER_RXBRIE_Pos)                 /*!< 0x00000001 */
+#define CEC_IER_RXBRIE           CEC_IER_RXBRIE_Msk                            /*!< CEC Rx-Byte Received IT Enable            */
+#define CEC_IER_RXENDIE_Pos      (1U)
+#define CEC_IER_RXENDIE_Msk      (0x1UL << CEC_IER_RXENDIE_Pos)                /*!< 0x00000002 */
+#define CEC_IER_RXENDIE          CEC_IER_RXENDIE_Msk                           /*!< CEC End Of Reception IT Enable            */
+#define CEC_IER_RXOVRIE_Pos      (2U)
+#define CEC_IER_RXOVRIE_Msk      (0x1UL << CEC_IER_RXOVRIE_Pos)                /*!< 0x00000004 */
+#define CEC_IER_RXOVRIE          CEC_IER_RXOVRIE_Msk                           /*!< CEC Rx-Overrun IT Enable                  */
+#define CEC_IER_BREIE_Pos        (3U)
+#define CEC_IER_BREIE_Msk        (0x1UL << CEC_IER_BREIE_Pos)                  /*!< 0x00000008 */
+#define CEC_IER_BREIE            CEC_IER_BREIE_Msk                             /*!< CEC Rx Bit Rising Error IT Enable         */
+#define CEC_IER_SBPEIE_Pos       (4U)
+#define CEC_IER_SBPEIE_Msk       (0x1UL << CEC_IER_SBPEIE_Pos)                 /*!< 0x00000010 */
+#define CEC_IER_SBPEIE           CEC_IER_SBPEIE_Msk                            /*!< CEC Rx Short Bit period Error IT Enable   */
+#define CEC_IER_LBPEIE_Pos       (5U)
+#define CEC_IER_LBPEIE_Msk       (0x1UL << CEC_IER_LBPEIE_Pos)                 /*!< 0x00000020 */
+#define CEC_IER_LBPEIE           CEC_IER_LBPEIE_Msk                            /*!< CEC Rx Long Bit period Error IT Enable    */
+#define CEC_IER_RXACKEIE_Pos     (6U)
+#define CEC_IER_RXACKEIE_Msk     (0x1UL << CEC_IER_RXACKEIE_Pos)               /*!< 0x00000040 */
+#define CEC_IER_RXACKEIE         CEC_IER_RXACKEIE_Msk                          /*!< CEC Rx Missing Acknowledge IT Enable      */
+#define CEC_IER_ARBLSTIE_Pos     (7U)
+#define CEC_IER_ARBLSTIE_Msk     (0x1UL << CEC_IER_ARBLSTIE_Pos)               /*!< 0x00000080 */
+#define CEC_IER_ARBLSTIE         CEC_IER_ARBLSTIE_Msk                          /*!< CEC Arbitration Lost IT Enable            */
+#define CEC_IER_TXBRIE_Pos       (8U)
+#define CEC_IER_TXBRIE_Msk       (0x1UL << CEC_IER_TXBRIE_Pos)                 /*!< 0x00000100 */
+#define CEC_IER_TXBRIE           CEC_IER_TXBRIE_Msk                            /*!< CEC Tx Byte Request  IT Enable            */
+#define CEC_IER_TXENDIE_Pos      (9U)
+#define CEC_IER_TXENDIE_Msk      (0x1UL << CEC_IER_TXENDIE_Pos)                /*!< 0x00000200 */
+#define CEC_IER_TXENDIE          CEC_IER_TXENDIE_Msk                           /*!< CEC End of Transmission IT Enable         */
+#define CEC_IER_TXUDRIE_Pos      (10U)
+#define CEC_IER_TXUDRIE_Msk      (0x1UL << CEC_IER_TXUDRIE_Pos)                /*!< 0x00000400 */
+#define CEC_IER_TXUDRIE          CEC_IER_TXUDRIE_Msk                           /*!< CEC Tx-Buffer Underrun IT Enable          */
+#define CEC_IER_TXERRIE_Pos      (11U)
+#define CEC_IER_TXERRIE_Msk      (0x1UL << CEC_IER_TXERRIE_Pos)                /*!< 0x00000800 */
+#define CEC_IER_TXERRIE          CEC_IER_TXERRIE_Msk                           /*!< CEC Tx-Error IT Enable                    */
+#define CEC_IER_TXACKEIE_Pos     (12U)
+#define CEC_IER_TXACKEIE_Msk     (0x1UL << CEC_IER_TXACKEIE_Pos)               /*!< 0x00001000 */
+#define CEC_IER_TXACKEIE         CEC_IER_TXACKEIE_Msk                          /*!< CEC Tx Missing Acknowledge IT Enable      */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRC calculation unit                              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CRC_DR register  *********************/
+#define CRC_DR_DR_Pos            (0U)
+#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)               /*!< 0xFFFFFFFF */
+#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define CRC_IDR_IDR_Pos          (0U)
+#define CRC_IDR_IDR_Msk          (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)             /*!< 0xFFFFFFFF */
+#define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 32-bit data register bits */
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define CRC_CR_RESET_Pos         (0U)
+#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                   /*!< 0x00000001 */
+#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE_Pos      (3U)
+#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000018 */
+#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
+#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
+#define CRC_CR_REV_IN_Pos        (5U)
+#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000060 */
+#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
+#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
+#define CRC_CR_REV_OUT_Pos       (7U)
+#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                 /*!< 0x00000080 */
+#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
+
+/*******************  Bit definition for CRC_INIT register  *******************/
+#define CRC_INIT_INIT_Pos        (0U)
+#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)           /*!< 0xFFFFFFFF */
+#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
+
+/*******************  Bit definition for CRC_POL register  ********************/
+#define CRC_POL_POL_Pos          (0U)
+#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)             /*!< 0xFFFFFFFF */
+#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRS Clock Recovery System                         */
+/******************************************************************************/
+
+/*******************  Bit definition for CRS_CR register  *********************/
+#define CRS_CR_SYNCOKIE_Pos       (0U)
+#define CRS_CR_SYNCOKIE_Msk       (0x1UL << CRS_CR_SYNCOKIE_Pos)               /*!< 0x00000001 */
+#define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /*!< SYNC event OK interrupt enable */
+#define CRS_CR_SYNCWARNIE_Pos     (1U)
+#define CRS_CR_SYNCWARNIE_Msk     (0x1UL << CRS_CR_SYNCWARNIE_Pos)             /*!< 0x00000002 */
+#define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /*!< SYNC warning interrupt enable */
+#define CRS_CR_ERRIE_Pos          (2U)
+#define CRS_CR_ERRIE_Msk          (0x1UL << CRS_CR_ERRIE_Pos)                  /*!< 0x00000004 */
+#define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /*!< SYNC error or trimming error interrupt enable */
+#define CRS_CR_ESYNCIE_Pos        (3U)
+#define CRS_CR_ESYNCIE_Msk        (0x1UL << CRS_CR_ESYNCIE_Pos)                /*!< 0x00000008 */
+#define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /*!< Expected SYNC interrupt enable */
+#define CRS_CR_CEN_Pos            (5U)
+#define CRS_CR_CEN_Msk            (0x1UL << CRS_CR_CEN_Pos)                    /*!< 0x00000020 */
+#define CRS_CR_CEN                CRS_CR_CEN_Msk                               /*!< Frequency error counter enable */
+#define CRS_CR_AUTOTRIMEN_Pos     (6U)
+#define CRS_CR_AUTOTRIMEN_Msk     (0x1UL << CRS_CR_AUTOTRIMEN_Pos)             /*!< 0x00000040 */
+#define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /*!< Automatic trimming enable */
+#define CRS_CR_SWSYNC_Pos         (7U)
+#define CRS_CR_SWSYNC_Msk         (0x1UL << CRS_CR_SWSYNC_Pos)                 /*!< 0x00000080 */
+#define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /*!< Generate software SYNC event */
+#define CRS_CR_TRIM_Pos           (8U)
+#define CRS_CR_TRIM_Msk           (0x3FUL << CRS_CR_TRIM_Pos)                  /*!< 0x00003F00 */
+#define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /*!< HSI48 oscillator smooth trimming */
+
+/*******************  Bit definition for CRS_CFGR register  *********************/
+#define CRS_CFGR_RELOAD_Pos       (0U)
+#define CRS_CFGR_RELOAD_Msk       (0xFFFFUL << CRS_CFGR_RELOAD_Pos)            /*!< 0x0000FFFF */
+#define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /*!< Counter reload value */
+#define CRS_CFGR_FELIM_Pos        (16U)
+#define CRS_CFGR_FELIM_Msk        (0xFFUL << CRS_CFGR_FELIM_Pos)               /*!< 0x00FF0000 */
+#define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /*!< Frequency error limit */
+
+#define CRS_CFGR_SYNCDIV_Pos      (24U)
+#define CRS_CFGR_SYNCDIV_Msk      (0x7UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x07000000 */
+#define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /*!< SYNC divider */
+#define CRS_CFGR_SYNCDIV_0        (0x1UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */
+#define CRS_CFGR_SYNCDIV_1        (0x2UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */
+#define CRS_CFGR_SYNCDIV_2        (0x4UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */
+
+#define CRS_CFGR_SYNCSRC_Pos      (28U)
+#define CRS_CFGR_SYNCSRC_Msk      (0x3UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x30000000 */
+#define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /*!< SYNC signal source selection */
+#define CRS_CFGR_SYNCSRC_0        (0x1UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */
+#define CRS_CFGR_SYNCSRC_1        (0x2UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */
+
+#define CRS_CFGR_SYNCPOL_Pos      (31U)
+#define CRS_CFGR_SYNCPOL_Msk      (0x1UL << CRS_CFGR_SYNCPOL_Pos)              /*!< 0x80000000 */
+#define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /*!< SYNC polarity selection */
+
+/*******************  Bit definition for CRS_ISR register  *********************/
+#define CRS_ISR_SYNCOKF_Pos       (0U)
+#define CRS_ISR_SYNCOKF_Msk       (0x1UL << CRS_ISR_SYNCOKF_Pos)               /*!< 0x00000001 */
+#define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /*!< SYNC event OK flag */
+#define CRS_ISR_SYNCWARNF_Pos     (1U)
+#define CRS_ISR_SYNCWARNF_Msk     (0x1UL << CRS_ISR_SYNCWARNF_Pos)             /*!< 0x00000002 */
+#define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /*!< SYNC warning flag */
+#define CRS_ISR_ERRF_Pos          (2U)
+#define CRS_ISR_ERRF_Msk          (0x1UL << CRS_ISR_ERRF_Pos)                  /*!< 0x00000004 */
+#define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /*!< Error flag */
+#define CRS_ISR_ESYNCF_Pos        (3U)
+#define CRS_ISR_ESYNCF_Msk        (0x1UL << CRS_ISR_ESYNCF_Pos)                /*!< 0x00000008 */
+#define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /*!< Expected SYNC flag */
+#define CRS_ISR_SYNCERR_Pos       (8U)
+#define CRS_ISR_SYNCERR_Msk       (0x1UL << CRS_ISR_SYNCERR_Pos)               /*!< 0x00000100 */
+#define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /*!< SYNC error */
+#define CRS_ISR_SYNCMISS_Pos      (9U)
+#define CRS_ISR_SYNCMISS_Msk      (0x1UL << CRS_ISR_SYNCMISS_Pos)              /*!< 0x00000200 */
+#define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /*!< SYNC missed */
+#define CRS_ISR_TRIMOVF_Pos       (10U)
+#define CRS_ISR_TRIMOVF_Msk       (0x1UL << CRS_ISR_TRIMOVF_Pos)               /*!< 0x00000400 */
+#define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /*!< Trimming overflow or underflow */
+#define CRS_ISR_FEDIR_Pos         (15U)
+#define CRS_ISR_FEDIR_Msk         (0x1UL << CRS_ISR_FEDIR_Pos)                 /*!< 0x00008000 */
+#define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /*!< Frequency error direction */
+#define CRS_ISR_FECAP_Pos         (16U)
+#define CRS_ISR_FECAP_Msk         (0xFFFFUL << CRS_ISR_FECAP_Pos)              /*!< 0xFFFF0000 */
+#define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /*!< Frequency error capture */
+
+/*******************  Bit definition for CRS_ICR register  *********************/
+#define CRS_ICR_SYNCOKC_Pos       (0U)
+#define CRS_ICR_SYNCOKC_Msk       (0x1UL << CRS_ICR_SYNCOKC_Pos)               /*!< 0x00000001 */
+#define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /*!< SYNC event OK clear flag */
+#define CRS_ICR_SYNCWARNC_Pos     (1U)
+#define CRS_ICR_SYNCWARNC_Msk     (0x1UL << CRS_ICR_SYNCWARNC_Pos)             /*!< 0x00000002 */
+#define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /*!< SYNC warning clear flag */
+#define CRS_ICR_ERRC_Pos          (2U)
+#define CRS_ICR_ERRC_Msk          (0x1UL << CRS_ICR_ERRC_Pos)                  /*!< 0x00000004 */
+#define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /*!< Error clear flag */
+#define CRS_ICR_ESYNCC_Pos        (3U)
+#define CRS_ICR_ESYNCC_Msk        (0x1UL << CRS_ICR_ESYNCC_Pos)                /*!< 0x00000008 */
+#define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /*!< Expected SYNC clear flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Digital to Analog Converter                           */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DAC_CR register  ********************/
+#define DAC_CR_EN1_Pos              (0U)
+#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                  /*!< 0x00000001 */
+#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */
+#define DAC_CR_TEN1_Pos             (1U)
+#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                 /*!< 0x00000002 */
+#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos            (2U)
+#define DAC_CR_TSEL1_Msk            (0xFUL << DAC_CR_TSEL1_Pos)                /*!< 0x0000003C */
+#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000004 */
+#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
+#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
+#define DAC_CR_TSEL1_3              (0x8UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
+
+
+#define DAC_CR_WAVE1_Pos            (6U)
+#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                /*!< 0x000000C0 */
+#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos            (8U)
+#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                /*!< 0x00000F00 */
+#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos           (12U)
+#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)               /*!< 0x00001000 */
+#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1_Pos        (13U)
+#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)            /*!< 0x00002000 */
+#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/
+#define DAC_CR_CEN1_Pos             (14U)
+#define DAC_CR_CEN1_Msk             (0x1UL << DAC_CR_CEN1_Pos)                 /*!< 0x00004000 */
+#define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/
+
+#define DAC_CR_EN2_Pos              (16U)
+#define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                  /*!< 0x00010000 */
+#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */
+#define DAC_CR_TEN2_Pos             (17U)
+#define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                 /*!< 0x00020000 */
+#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2_Pos            (18U)
+#define DAC_CR_TSEL2_Msk            (0xFUL << DAC_CR_TSEL2_Pos)                /*!< 0x003C0000 */
+#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00040000 */
+#define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */
+#define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */
+#define DAC_CR_TSEL2_3              (0x8UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */
+
+
+#define DAC_CR_WAVE2_Pos            (22U)
+#define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                /*!< 0x00C00000 */
+#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */
+#define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */
+
+#define DAC_CR_MAMP2_Pos            (24U)
+#define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                /*!< 0x0F000000 */
+#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */
+#define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */
+#define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */
+#define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */
+
+#define DAC_CR_DMAEN2_Pos           (28U)
+#define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)               /*!< 0x10000000 */
+#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2_Pos        (29U)
+#define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)            /*!< 0x20000000 */
+#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/
+#define DAC_CR_CEN2_Pos             (30U)
+#define DAC_CR_CEN2_Msk             (0x1UL << DAC_CR_CEN2_Pos)                 /*!< 0x40000000 */
+#define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/
+
+/*****************  Bit definition for DAC_SWTRIGR register  ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)
+#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)         /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)
+#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)         /*!< 0x00000002 */
+#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */
+
+/*****************  Bit definition for DAC_DHR12R1 register  ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos    (0U)
+#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)      /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L1 register  ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos    (4U)
+#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)      /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R1 register  ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos     (0U)
+#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)        /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12R2 register  ******************/
+#define DAC_DHR12R2_DACC2DHR_Pos    (0U)
+#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)      /*!< 0x00000FFF */
+#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L2 register  ******************/
+#define DAC_DHR12L2_DACC2DHR_Pos    (4U)
+#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)      /*!< 0x0000FFF0 */
+#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R2 register  ******************/
+#define DAC_DHR8R2_DACC2DHR_Pos     (0U)
+#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)        /*!< 0x000000FF */
+#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12RD register  ******************/
+#define DAC_DHR12RD_DACC1DHR_Pos    (0U)
+#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)      /*!< 0x00000FFF */
+#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR_Pos    (16U)
+#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)      /*!< 0x0FFF0000 */
+#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12LD register  ******************/
+#define DAC_DHR12LD_DACC1DHR_Pos    (4U)
+#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)      /*!< 0x0000FFF0 */
+#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR_Pos    (20U)
+#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)      /*!< 0xFFF00000 */
+#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8RD register  ******************/
+#define DAC_DHR8RD_DACC1DHR_Pos     (0U)
+#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)        /*!< 0x000000FF */
+#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR_Pos     (8U)
+#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)        /*!< 0x0000FF00 */
+#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
+
+/*******************  Bit definition for DAC_DOR1 register  *******************/
+#define DAC_DOR1_DACC1DOR_Pos       (0U)
+#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)         /*!< 0x00000FFF */
+#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */
+
+/*******************  Bit definition for DAC_DOR2 register  *******************/
+#define DAC_DOR2_DACC2DOR_Pos       (0U)
+#define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)         /*!< 0x00000FFF */
+#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */
+
+/********************  Bit definition for DAC_SR register  ********************/
+#define DAC_SR_DMAUDR1_Pos          (13U)
+#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)              /*!< 0x00002000 */
+#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_CAL_FLAG1_Pos        (14U)
+#define DAC_SR_CAL_FLAG1_Msk        (0x1UL << DAC_SR_CAL_FLAG1_Pos)            /*!< 0x00004000 */
+#define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */
+#define DAC_SR_BWST1_Pos            (15U)
+#define DAC_SR_BWST1_Msk            (0x4001UL << DAC_SR_BWST1_Pos)             /*!< 0x20008000 */
+#define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */
+
+#define DAC_SR_DMAUDR2_Pos          (29U)
+#define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)              /*!< 0x20000000 */
+#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */
+#define DAC_SR_CAL_FLAG2_Pos        (30U)
+#define DAC_SR_CAL_FLAG2_Msk        (0x1UL << DAC_SR_CAL_FLAG2_Pos)            /*!< 0x40000000 */
+#define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */
+#define DAC_SR_BWST2_Pos            (31U)
+#define DAC_SR_BWST2_Msk            (0x1UL << DAC_SR_BWST2_Pos)                /*!< 0x80000000 */
+#define DAC_SR_BWST2                DAC_SR_BWST2_Msk                           /*!<DAC channel2 busy writing sample time flag */
+
+/*******************  Bit definition for DAC_CCR register  ********************/
+#define DAC_CCR_OTRIM1_Pos          (0U)
+#define DAC_CCR_OTRIM1_Msk          (0x1FUL << DAC_CCR_OTRIM1_Pos)             /*!< 0x0000001F */
+#define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */
+#define DAC_CCR_OTRIM2_Pos          (16U)
+#define DAC_CCR_OTRIM2_Msk          (0x1FUL << DAC_CCR_OTRIM2_Pos)             /*!< 0x001F0000 */
+#define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */
+
+/*******************  Bit definition for DAC_MCR register  *******************/
+#define DAC_MCR_MODE1_Pos           (0U)
+#define DAC_MCR_MODE1_Msk           (0x7UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000007 */
+#define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */
+#define DAC_MCR_MODE1_0             (0x1UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000001 */
+#define DAC_MCR_MODE1_1             (0x2UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000002 */
+#define DAC_MCR_MODE1_2             (0x4UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000004 */
+
+#define DAC_MCR_MODE2_Pos           (16U)
+#define DAC_MCR_MODE2_Msk           (0x7UL << DAC_MCR_MODE2_Pos)               /*!< 0x00070000 */
+#define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */
+#define DAC_MCR_MODE2_0             (0x1UL << DAC_MCR_MODE2_Pos)                /*!< 0x00010000 */
+#define DAC_MCR_MODE2_1             (0x2UL << DAC_MCR_MODE2_Pos)                /*!< 0x00020000 */
+#define DAC_MCR_MODE2_2             (0x4UL << DAC_MCR_MODE2_Pos)                /*!< 0x00040000 */
+
+/******************  Bit definition for DAC_SHSR1 register  ******************/
+#define DAC_SHSR1_TSAMPLE1_Pos      (0U)
+#define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)        /*!< 0x000003FF */
+#define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */
+
+/******************  Bit definition for DAC_SHSR2 register  ******************/
+#define DAC_SHSR2_TSAMPLE2_Pos      (0U)
+#define DAC_SHSR2_TSAMPLE2_Msk      (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)        /*!< 0x000003FF */
+#define DAC_SHSR2_TSAMPLE2          DAC_SHSR2_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */
+
+/******************  Bit definition for DAC_SHHR register  ******************/
+#define DAC_SHHR_THOLD1_Pos         (0U)
+#define DAC_SHHR_THOLD1_Msk         (0x3FFUL << DAC_SHHR_THOLD1_Pos)           /*!< 0x000003FF */
+#define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */
+#define DAC_SHHR_THOLD2_Pos         (16U)
+#define DAC_SHHR_THOLD2_Msk         (0x3FFUL << DAC_SHHR_THOLD2_Pos)           /*!< 0x03FF0000 */
+#define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */
+
+/******************  Bit definition for DAC_SHRR register  ******************/
+#define DAC_SHRR_TREFRESH1_Pos      (0U)
+#define DAC_SHRR_TREFRESH1_Msk      (0xFFUL << DAC_SHRR_TREFRESH1_Pos)         /*!< 0x000000FF */
+#define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */
+#define DAC_SHRR_TREFRESH2_Pos      (16U)
+#define DAC_SHRR_TREFRESH2_Msk      (0xFFUL << DAC_SHRR_TREFRESH2_Pos)         /*!< 0x00FF0000 */
+#define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    DCMI                                    */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for DCMI_CR register  ******************/
+#define DCMI_CR_CAPTURE_Pos        (0U)
+#define DCMI_CR_CAPTURE_Msk        (0x1UL << DCMI_CR_CAPTURE_Pos)              /*!< 0x00000001 */
+#define DCMI_CR_CAPTURE            DCMI_CR_CAPTURE_Msk
+#define DCMI_CR_CM_Pos             (1U)
+#define DCMI_CR_CM_Msk             (0x1UL << DCMI_CR_CM_Pos)                   /*!< 0x00000002 */
+#define DCMI_CR_CM                 DCMI_CR_CM_Msk
+#define DCMI_CR_CROP_Pos           (2U)
+#define DCMI_CR_CROP_Msk           (0x1UL << DCMI_CR_CROP_Pos)                 /*!< 0x00000004 */
+#define DCMI_CR_CROP               DCMI_CR_CROP_Msk
+#define DCMI_CR_JPEG_Pos           (3U)
+#define DCMI_CR_JPEG_Msk           (0x1UL << DCMI_CR_JPEG_Pos)                 /*!< 0x00000008 */
+#define DCMI_CR_JPEG               DCMI_CR_JPEG_Msk
+#define DCMI_CR_ESS_Pos            (4U)
+#define DCMI_CR_ESS_Msk            (0x1UL << DCMI_CR_ESS_Pos)                  /*!< 0x00000010 */
+#define DCMI_CR_ESS                DCMI_CR_ESS_Msk
+#define DCMI_CR_PCKPOL_Pos         (5U)
+#define DCMI_CR_PCKPOL_Msk         (0x1UL << DCMI_CR_PCKPOL_Pos)               /*!< 0x00000020 */
+#define DCMI_CR_PCKPOL             DCMI_CR_PCKPOL_Msk
+#define DCMI_CR_HSPOL_Pos          (6U)
+#define DCMI_CR_HSPOL_Msk          (0x1UL << DCMI_CR_HSPOL_Pos)                /*!< 0x00000040 */
+#define DCMI_CR_HSPOL              DCMI_CR_HSPOL_Msk
+#define DCMI_CR_VSPOL_Pos          (7U)
+#define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                /*!< 0x00000080 */
+#define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk
+#define DCMI_CR_FCRC_0             ((uint32_t)0x00000100U)
+#define DCMI_CR_FCRC_1             ((uint32_t)0x00000200U)
+#define DCMI_CR_EDM_0              ((uint32_t)0x00000400U)
+#define DCMI_CR_EDM_1              ((uint32_t)0x00000800U)
+#define DCMI_CR_CRE_Pos            (12U)
+#define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                  /*!< 0x00001000 */
+#define DCMI_CR_CRE                DCMI_CR_CRE_Msk
+#define DCMI_CR_ENABLE_Pos         (14U)
+#define DCMI_CR_ENABLE_Msk         (0x1UL << DCMI_CR_ENABLE_Pos)               /*!< 0x00004000 */
+#define DCMI_CR_ENABLE             DCMI_CR_ENABLE_Msk
+#define DCMI_CR_BSM_Pos            (16U)
+#define DCMI_CR_BSM_Msk            (0x3UL << DCMI_CR_BSM_Pos)                  /*!< 0x00030000 */
+#define DCMI_CR_BSM                DCMI_CR_BSM_Msk
+#define DCMI_CR_BSM_0              (0x1UL << DCMI_CR_BSM_Pos)                   /*!< 0x00010000 */
+#define DCMI_CR_BSM_1              (0x2UL << DCMI_CR_BSM_Pos)                   /*!< 0x00020000 */
+#define DCMI_CR_OEBS_Pos           (18U)
+#define DCMI_CR_OEBS_Msk           (0x1UL << DCMI_CR_OEBS_Pos)                 /*!< 0x00040000 */
+#define DCMI_CR_OEBS               DCMI_CR_OEBS_Msk
+#define DCMI_CR_LSM_Pos            (19U)
+#define DCMI_CR_LSM_Msk            (0x1UL << DCMI_CR_LSM_Pos)                  /*!< 0x00080000 */
+#define DCMI_CR_LSM                DCMI_CR_LSM_Msk
+#define DCMI_CR_OELS_Pos           (20U)
+#define DCMI_CR_OELS_Msk           (0x1UL << DCMI_CR_OELS_Pos)                 /*!< 0x00100000 */
+#define DCMI_CR_OELS               DCMI_CR_OELS_Msk
+
+/********************  Bits definition for DCMI_SR register  ******************/
+#define DCMI_SR_HSYNC_Pos          (0U)
+#define DCMI_SR_HSYNC_Msk          (0x1UL << DCMI_SR_HSYNC_Pos)                /*!< 0x00000001 */
+#define DCMI_SR_HSYNC              DCMI_SR_HSYNC_Msk
+#define DCMI_SR_VSYNC_Pos          (1U)
+#define DCMI_SR_VSYNC_Msk          (0x1UL << DCMI_SR_VSYNC_Pos)                /*!< 0x00000002 */
+#define DCMI_SR_VSYNC              DCMI_SR_VSYNC_Msk
+#define DCMI_SR_FNE_Pos            (2U)
+#define DCMI_SR_FNE_Msk            (0x1UL << DCMI_SR_FNE_Pos)                  /*!< 0x00000004 */
+#define DCMI_SR_FNE                DCMI_SR_FNE_Msk
+
+/********************  Bits definition for DCMI_RIS register   ****************/
+#define DCMI_RIS_FRAME_RIS_Pos     (0U)
+#define DCMI_RIS_FRAME_RIS_Msk     (0x1UL << DCMI_RIS_FRAME_RIS_Pos)           /*!< 0x00000001 */
+#define DCMI_RIS_FRAME_RIS         DCMI_RIS_FRAME_RIS_Msk
+#define DCMI_RIS_OVR_RIS_Pos       (1U)
+#define DCMI_RIS_OVR_RIS_Msk       (0x1UL << DCMI_RIS_OVR_RIS_Pos)             /*!< 0x00000002 */
+#define DCMI_RIS_OVR_RIS           DCMI_RIS_OVR_RIS_Msk
+#define DCMI_RIS_ERR_RIS_Pos       (2U)
+#define DCMI_RIS_ERR_RIS_Msk       (0x1UL << DCMI_RIS_ERR_RIS_Pos)             /*!< 0x00000004 */
+#define DCMI_RIS_ERR_RIS           DCMI_RIS_ERR_RIS_Msk
+#define DCMI_RIS_VSYNC_RIS_Pos     (3U)
+#define DCMI_RIS_VSYNC_RIS_Msk     (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)           /*!< 0x00000008 */
+#define DCMI_RIS_VSYNC_RIS         DCMI_RIS_VSYNC_RIS_Msk
+#define DCMI_RIS_LINE_RIS_Pos      (4U)
+#define DCMI_RIS_LINE_RIS_Msk      (0x1UL << DCMI_RIS_LINE_RIS_Pos)            /*!< 0x00000010 */
+#define DCMI_RIS_LINE_RIS          DCMI_RIS_LINE_RIS_Msk
+
+/********************  Bits definition for DCMI_IER register  *****************/
+#define DCMI_IER_FRAME_IE_Pos      (0U)
+#define DCMI_IER_FRAME_IE_Msk      (0x1UL << DCMI_IER_FRAME_IE_Pos)            /*!< 0x00000001 */
+#define DCMI_IER_FRAME_IE          DCMI_IER_FRAME_IE_Msk
+#define DCMI_IER_OVR_IE_Pos        (1U)
+#define DCMI_IER_OVR_IE_Msk        (0x1UL << DCMI_IER_OVR_IE_Pos)              /*!< 0x00000002 */
+#define DCMI_IER_OVR_IE            DCMI_IER_OVR_IE_Msk
+#define DCMI_IER_ERR_IE_Pos        (2U)
+#define DCMI_IER_ERR_IE_Msk        (0x1UL << DCMI_IER_ERR_IE_Pos)              /*!< 0x00000004 */
+#define DCMI_IER_ERR_IE            DCMI_IER_ERR_IE_Msk
+#define DCMI_IER_VSYNC_IE_Pos      (3U)
+#define DCMI_IER_VSYNC_IE_Msk      (0x1UL << DCMI_IER_VSYNC_IE_Pos)            /*!< 0x00000008 */
+#define DCMI_IER_VSYNC_IE          DCMI_IER_VSYNC_IE_Msk
+#define DCMI_IER_LINE_IE_Pos       (4U)
+#define DCMI_IER_LINE_IE_Msk       (0x1UL << DCMI_IER_LINE_IE_Pos)             /*!< 0x00000010 */
+#define DCMI_IER_LINE_IE           DCMI_IER_LINE_IE_Msk
+
+
+/********************  Bits definition for DCMI_MIS register  *****************/
+#define DCMI_MIS_FRAME_MIS_Pos     (0U)
+#define DCMI_MIS_FRAME_MIS_Msk     (0x1UL << DCMI_MIS_FRAME_MIS_Pos)           /*!< 0x00000001 */
+#define DCMI_MIS_FRAME_MIS         DCMI_MIS_FRAME_MIS_Msk
+#define DCMI_MIS_OVR_MIS_Pos       (1U)
+#define DCMI_MIS_OVR_MIS_Msk       (0x1UL << DCMI_MIS_OVR_MIS_Pos)             /*!< 0x00000002 */
+#define DCMI_MIS_OVR_MIS           DCMI_MIS_OVR_MIS_Msk
+#define DCMI_MIS_ERR_MIS_Pos       (2U)
+#define DCMI_MIS_ERR_MIS_Msk       (0x1UL << DCMI_MIS_ERR_MIS_Pos)             /*!< 0x00000004 */
+#define DCMI_MIS_ERR_MIS           DCMI_MIS_ERR_MIS_Msk
+#define DCMI_MIS_VSYNC_MIS_Pos     (3U)
+#define DCMI_MIS_VSYNC_MIS_Msk     (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)           /*!< 0x00000008 */
+#define DCMI_MIS_VSYNC_MIS         DCMI_MIS_VSYNC_MIS_Msk
+#define DCMI_MIS_LINE_MIS_Pos      (4U)
+#define DCMI_MIS_LINE_MIS_Msk      (0x1UL << DCMI_MIS_LINE_MIS_Pos)            /*!< 0x00000010 */
+#define DCMI_MIS_LINE_MIS          DCMI_MIS_LINE_MIS_Msk
+
+
+/********************  Bits definition for DCMI_ICR register  *****************/
+#define DCMI_ICR_FRAME_ISC_Pos     (0U)
+#define DCMI_ICR_FRAME_ISC_Msk     (0x1UL << DCMI_ICR_FRAME_ISC_Pos)           /*!< 0x00000001 */
+#define DCMI_ICR_FRAME_ISC         DCMI_ICR_FRAME_ISC_Msk
+#define DCMI_ICR_OVR_ISC_Pos       (1U)
+#define DCMI_ICR_OVR_ISC_Msk       (0x1UL << DCMI_ICR_OVR_ISC_Pos)             /*!< 0x00000002 */
+#define DCMI_ICR_OVR_ISC           DCMI_ICR_OVR_ISC_Msk
+#define DCMI_ICR_ERR_ISC_Pos       (2U)
+#define DCMI_ICR_ERR_ISC_Msk       (0x1UL << DCMI_ICR_ERR_ISC_Pos)             /*!< 0x00000004 */
+#define DCMI_ICR_ERR_ISC           DCMI_ICR_ERR_ISC_Msk
+#define DCMI_ICR_VSYNC_ISC_Pos     (3U)
+#define DCMI_ICR_VSYNC_ISC_Msk     (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)           /*!< 0x00000008 */
+#define DCMI_ICR_VSYNC_ISC         DCMI_ICR_VSYNC_ISC_Msk
+#define DCMI_ICR_LINE_ISC_Pos      (4U)
+#define DCMI_ICR_LINE_ISC_Msk      (0x1UL << DCMI_ICR_LINE_ISC_Pos)            /*!< 0x00000010 */
+#define DCMI_ICR_LINE_ISC          DCMI_ICR_LINE_ISC_Msk
+
+
+/********************  Bits definition for DCMI_ESCR register  ******************/
+#define DCMI_ESCR_FSC_Pos          (0U)
+#define DCMI_ESCR_FSC_Msk          (0xFFUL << DCMI_ESCR_FSC_Pos)               /*!< 0x000000FF */
+#define DCMI_ESCR_FSC              DCMI_ESCR_FSC_Msk
+#define DCMI_ESCR_LSC_Pos          (8U)
+#define DCMI_ESCR_LSC_Msk          (0xFFUL << DCMI_ESCR_LSC_Pos)               /*!< 0x0000FF00 */
+#define DCMI_ESCR_LSC              DCMI_ESCR_LSC_Msk
+#define DCMI_ESCR_LEC_Pos          (16U)
+#define DCMI_ESCR_LEC_Msk          (0xFFUL << DCMI_ESCR_LEC_Pos)               /*!< 0x00FF0000 */
+#define DCMI_ESCR_LEC              DCMI_ESCR_LEC_Msk
+#define DCMI_ESCR_FEC_Pos          (24U)
+#define DCMI_ESCR_FEC_Msk          (0xFFUL << DCMI_ESCR_FEC_Pos)               /*!< 0xFF000000 */
+#define DCMI_ESCR_FEC              DCMI_ESCR_FEC_Msk
+
+/********************  Bits definition for DCMI_ESUR register  ******************/
+#define DCMI_ESUR_FSU_Pos          (0U)
+#define DCMI_ESUR_FSU_Msk          (0xFFUL << DCMI_ESUR_FSU_Pos)               /*!< 0x000000FF */
+#define DCMI_ESUR_FSU              DCMI_ESUR_FSU_Msk
+#define DCMI_ESUR_LSU_Pos          (8U)
+#define DCMI_ESUR_LSU_Msk          (0xFFUL << DCMI_ESUR_LSU_Pos)               /*!< 0x0000FF00 */
+#define DCMI_ESUR_LSU              DCMI_ESUR_LSU_Msk
+#define DCMI_ESUR_LEU_Pos          (16U)
+#define DCMI_ESUR_LEU_Msk          (0xFFUL << DCMI_ESUR_LEU_Pos)               /*!< 0x00FF0000 */
+#define DCMI_ESUR_LEU              DCMI_ESUR_LEU_Msk
+#define DCMI_ESUR_FEU_Pos          (24U)
+#define DCMI_ESUR_FEU_Msk          (0xFFUL << DCMI_ESUR_FEU_Pos)               /*!< 0xFF000000 */
+#define DCMI_ESUR_FEU              DCMI_ESUR_FEU_Msk
+
+/********************  Bits definition for DCMI_CWSTRT register  ******************/
+#define DCMI_CWSTRT_HOFFCNT_Pos    (0U)
+#define DCMI_CWSTRT_HOFFCNT_Msk    (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)       /*!< 0x00003FFF */
+#define DCMI_CWSTRT_HOFFCNT        DCMI_CWSTRT_HOFFCNT_Msk
+#define DCMI_CWSTRT_VST_Pos        (16U)
+#define DCMI_CWSTRT_VST_Msk        (0x1FFFUL << DCMI_CWSTRT_VST_Pos)           /*!< 0x1FFF0000 */
+#define DCMI_CWSTRT_VST            DCMI_CWSTRT_VST_Msk
+
+/********************  Bits definition for DCMI_CWSIZE register  ******************/
+#define DCMI_CWSIZE_CAPCNT_Pos     (0U)
+#define DCMI_CWSIZE_CAPCNT_Msk     (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)        /*!< 0x00003FFF */
+#define DCMI_CWSIZE_CAPCNT         DCMI_CWSIZE_CAPCNT_Msk
+#define DCMI_CWSIZE_VLINE_Pos      (16U)
+#define DCMI_CWSIZE_VLINE_Msk      (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)         /*!< 0x3FFF0000 */
+#define DCMI_CWSIZE_VLINE          DCMI_CWSIZE_VLINE_Msk
+
+/********************  Bits definition for DCMI_DR register  ******************/
+#define DCMI_DR_BYTE0_Pos          (0U)
+#define DCMI_DR_BYTE0_Msk          (0xFFUL << DCMI_DR_BYTE0_Pos)               /*!< 0x000000FF */
+#define DCMI_DR_BYTE0              DCMI_DR_BYTE0_Msk
+#define DCMI_DR_BYTE1_Pos          (8U)
+#define DCMI_DR_BYTE1_Msk          (0xFFUL << DCMI_DR_BYTE1_Pos)               /*!< 0x0000FF00 */
+#define DCMI_DR_BYTE1              DCMI_DR_BYTE1_Msk
+#define DCMI_DR_BYTE2_Pos          (16U)
+#define DCMI_DR_BYTE2_Msk          (0xFFUL << DCMI_DR_BYTE2_Pos)               /*!< 0x00FF0000 */
+#define DCMI_DR_BYTE2              DCMI_DR_BYTE2_Msk
+#define DCMI_DR_BYTE3_Pos          (24U)
+#define DCMI_DR_BYTE3_Msk          (0xFFUL << DCMI_DR_BYTE3_Pos)               /*!< 0xFF000000 */
+#define DCMI_DR_BYTE3              DCMI_DR_BYTE3_Msk
+
+/******************************************************************************/
+/*                                                                            */
+/*                 Digital Filter for Sigma Delta Modulators                  */
+/*                                                                            */
+/******************************************************************************/
+
+/****************   DFSDM channel configuration registers  ********************/
+
+/***************  Bit definition for DFSDM_CHCFGR1 register  ******************/
+#define DFSDM_CHCFGR1_DFSDMEN_Pos       (31U)
+#define DFSDM_CHCFGR1_DFSDMEN_Msk       (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos)   /*!< 0x80000000 */
+#define DFSDM_CHCFGR1_DFSDMEN           DFSDM_CHCFGR1_DFSDMEN_Msk              /*!< Global enable for DFSDM interface */
+#define DFSDM_CHCFGR1_CKOUTSRC_Pos      (30U)
+#define DFSDM_CHCFGR1_CKOUTSRC_Msk      (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos)  /*!< 0x40000000 */
+#define DFSDM_CHCFGR1_CKOUTSRC          DFSDM_CHCFGR1_CKOUTSRC_Msk             /*!< Output serial clock source selection */
+#define DFSDM_CHCFGR1_CKOUTDIV_Pos      (16U)
+#define DFSDM_CHCFGR1_CKOUTDIV_Msk      (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */
+#define DFSDM_CHCFGR1_CKOUTDIV          DFSDM_CHCFGR1_CKOUTDIV_Msk             /*!< CKOUTDIV[7:0] output serial clock divider */
+#define DFSDM_CHCFGR1_DATPACK_Pos       (14U)
+#define DFSDM_CHCFGR1_DATPACK_Msk       (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos)   /*!< 0x0000C000 */
+#define DFSDM_CHCFGR1_DATPACK           DFSDM_CHCFGR1_DATPACK_Msk              /*!< DATPACK[1:0] Data packing mode */
+#define DFSDM_CHCFGR1_DATPACK_1         (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00008000 */
+#define DFSDM_CHCFGR1_DATPACK_0         (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00004000 */
+#define DFSDM_CHCFGR1_DATMPX_Pos        (12U)
+#define DFSDM_CHCFGR1_DATMPX_Msk        (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos)    /*!< 0x00003000 */
+#define DFSDM_CHCFGR1_DATMPX            DFSDM_CHCFGR1_DATMPX_Msk               /*!< DATMPX[1:0] Input data multiplexer for channel y */
+#define DFSDM_CHCFGR1_DATMPX_1          (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00002000 */
+#define DFSDM_CHCFGR1_DATMPX_0          (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00001000 */
+#define DFSDM_CHCFGR1_CHINSEL_Pos       (8U)
+#define DFSDM_CHCFGR1_CHINSEL_Msk       (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos)   /*!< 0x00000100 */
+#define DFSDM_CHCFGR1_CHINSEL           DFSDM_CHCFGR1_CHINSEL_Msk              /*!< Serial inputs selection for channel y */
+#define DFSDM_CHCFGR1_CHEN_Pos          (7U)
+#define DFSDM_CHCFGR1_CHEN_Msk          (0x1UL << DFSDM_CHCFGR1_CHEN_Pos)      /*!< 0x00000080 */
+#define DFSDM_CHCFGR1_CHEN              DFSDM_CHCFGR1_CHEN_Msk                 /*!< Channel y enable */
+#define DFSDM_CHCFGR1_CKABEN_Pos        (6U)
+#define DFSDM_CHCFGR1_CKABEN_Msk        (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos)    /*!< 0x00000040 */
+#define DFSDM_CHCFGR1_CKABEN            DFSDM_CHCFGR1_CKABEN_Msk               /*!< Clock absence detector enable on channel y */
+#define DFSDM_CHCFGR1_SCDEN_Pos         (5U)
+#define DFSDM_CHCFGR1_SCDEN_Msk         (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos)     /*!< 0x00000020 */
+#define DFSDM_CHCFGR1_SCDEN             DFSDM_CHCFGR1_SCDEN_Msk                /*!< Short circuit detector enable on channel y */
+#define DFSDM_CHCFGR1_SPICKSEL_Pos      (2U)
+#define DFSDM_CHCFGR1_SPICKSEL_Msk      (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos)  /*!< 0x0000000C */
+#define DFSDM_CHCFGR1_SPICKSEL          DFSDM_CHCFGR1_SPICKSEL_Msk             /*!< SPICKSEL[1:0] SPI clock select for channel y */
+#define DFSDM_CHCFGR1_SPICKSEL_1        (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000008 */
+#define DFSDM_CHCFGR1_SPICKSEL_0        (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000004 */
+#define DFSDM_CHCFGR1_SITP_Pos          (0U)
+#define DFSDM_CHCFGR1_SITP_Msk          (0x3UL << DFSDM_CHCFGR1_SITP_Pos)      /*!< 0x00000003 */
+#define DFSDM_CHCFGR1_SITP              DFSDM_CHCFGR1_SITP_Msk                 /*!< SITP[1:0] Serial interface type for channel y */
+#define DFSDM_CHCFGR1_SITP_1            (0x2UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000002 */
+#define DFSDM_CHCFGR1_SITP_0            (0x1UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000001 */
+
+/***************  Bit definition for DFSDM_CHCFGR2 register  ******************/
+#define DFSDM_CHCFGR2_OFFSET_Pos        (8U)
+#define DFSDM_CHCFGR2_OFFSET_Msk        (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_CHCFGR2_OFFSET            DFSDM_CHCFGR2_OFFSET_Msk               /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
+#define DFSDM_CHCFGR2_DTRBS_Pos         (3U)
+#define DFSDM_CHCFGR2_DTRBS_Msk         (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos)    /*!< 0x000000F8 */
+#define DFSDM_CHCFGR2_DTRBS             DFSDM_CHCFGR2_DTRBS_Msk                /*!< DTRBS[4:0] Data right bit-shift for channel y */
+
+/******************  Bit definition for DFSDM_CHAWSCDR register *****************/
+#define DFSDM_CHAWSCDR_AWFORD_Pos       (22U)
+#define DFSDM_CHAWSCDR_AWFORD_Msk       (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos)   /*!< 0x00C00000 */
+#define DFSDM_CHAWSCDR_AWFORD           DFSDM_CHAWSCDR_AWFORD_Msk              /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
+#define DFSDM_CHAWSCDR_AWFORD_1         (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00800000 */
+#define DFSDM_CHAWSCDR_AWFORD_0         (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00400000 */
+#define DFSDM_CHAWSCDR_AWFOSR_Pos       (16U)
+#define DFSDM_CHAWSCDR_AWFOSR_Msk       (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos)  /*!< 0x001F0000 */
+#define DFSDM_CHAWSCDR_AWFOSR           DFSDM_CHAWSCDR_AWFOSR_Msk              /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
+#define DFSDM_CHAWSCDR_BKSCD_Pos        (12U)
+#define DFSDM_CHAWSCDR_BKSCD_Msk        (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos)    /*!< 0x0000F000 */
+#define DFSDM_CHAWSCDR_BKSCD            DFSDM_CHAWSCDR_BKSCD_Msk               /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
+#define DFSDM_CHAWSCDR_SCDT_Pos         (0U)
+#define DFSDM_CHAWSCDR_SCDT_Msk         (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos)    /*!< 0x000000FF */
+#define DFSDM_CHAWSCDR_SCDT             DFSDM_CHAWSCDR_SCDT_Msk                /*!< SCDT[7:0] Short circuit detector threshold for channel y */
+
+/****************  Bit definition for DFSDM_CHWDATR register *******************/
+#define DFSDM_CHWDATR_WDATA_Pos         (0U)
+#define DFSDM_CHWDATR_WDATA_Msk         (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos)  /*!< 0x0000FFFF */
+#define DFSDM_CHWDATR_WDATA             DFSDM_CHWDATR_WDATA_Msk                /*!< WDATA[15:0] Input channel y watchdog data */
+
+/****************  Bit definition for DFSDM_CHDATINR register *****************/
+#define DFSDM_CHDATINR_INDAT0_Pos       (0U)
+#define DFSDM_CHDATINR_INDAT0_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */
+#define DFSDM_CHDATINR_INDAT0           DFSDM_CHDATINR_INDAT0_Msk              /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
+#define DFSDM_CHDATINR_INDAT1_Pos       (16U)
+#define DFSDM_CHDATINR_INDAT1_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */
+#define DFSDM_CHDATINR_INDAT1           DFSDM_CHDATINR_INDAT1_Msk              /*!< INDAT0[15:0] Input data for channel y */
+
+/************************   DFSDM module registers  ****************************/
+
+/********************  Bit definition for DFSDM_FLTCR1 register *******************/
+#define DFSDM_FLTCR1_AWFSEL_Pos         (30U)
+#define DFSDM_FLTCR1_AWFSEL_Msk         (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos)     /*!< 0x40000000 */
+#define DFSDM_FLTCR1_AWFSEL             DFSDM_FLTCR1_AWFSEL_Msk                /*!< Analog watchdog fast mode select */
+#define DFSDM_FLTCR1_FAST_Pos           (29U)
+#define DFSDM_FLTCR1_FAST_Msk           (0x1UL << DFSDM_FLTCR1_FAST_Pos)       /*!< 0x20000000 */
+#define DFSDM_FLTCR1_FAST               DFSDM_FLTCR1_FAST_Msk                  /*!< Fast conversion mode selection */
+#define DFSDM_FLTCR1_RCH_Pos            (24U)
+#define DFSDM_FLTCR1_RCH_Msk            (0x7UL << DFSDM_FLTCR1_RCH_Pos)        /*!< 0x07000000 */
+#define DFSDM_FLTCR1_RCH                DFSDM_FLTCR1_RCH_Msk                   /*!< RCH[2:0] Regular channel selection */
+#define DFSDM_FLTCR1_RDMAEN_Pos         (21U)
+#define DFSDM_FLTCR1_RDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos)     /*!< 0x00200000 */
+#define DFSDM_FLTCR1_RDMAEN             DFSDM_FLTCR1_RDMAEN_Msk                /*!< DMA channel enabled to read data for the regular conversion */
+#define DFSDM_FLTCR1_RSYNC_Pos          (19U)
+#define DFSDM_FLTCR1_RSYNC_Msk          (0x1UL << DFSDM_FLTCR1_RSYNC_Pos)      /*!< 0x00080000 */
+#define DFSDM_FLTCR1_RSYNC              DFSDM_FLTCR1_RSYNC_Msk                 /*!< Launch regular conversion synchronously with DFSDMx */
+#define DFSDM_FLTCR1_RCONT_Pos          (18U)
+#define DFSDM_FLTCR1_RCONT_Msk          (0x1UL << DFSDM_FLTCR1_RCONT_Pos)      /*!< 0x00040000 */
+#define DFSDM_FLTCR1_RCONT              DFSDM_FLTCR1_RCONT_Msk                 /*!< Continuous mode selection for regular conversions */
+#define DFSDM_FLTCR1_RSWSTART_Pos       (17U)
+#define DFSDM_FLTCR1_RSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos)   /*!< 0x00020000 */
+#define DFSDM_FLTCR1_RSWSTART           DFSDM_FLTCR1_RSWSTART_Msk              /*!< Software start of a conversion on the regular channel */
+#define DFSDM_FLTCR1_JEXTEN_Pos         (13U)
+#define DFSDM_FLTCR1_JEXTEN_Msk         (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos)     /*!< 0x00006000 */
+#define DFSDM_FLTCR1_JEXTEN             DFSDM_FLTCR1_JEXTEN_Msk                /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
+#define DFSDM_FLTCR1_JEXTEN_1           (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00004000 */
+#define DFSDM_FLTCR1_JEXTEN_0           (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00002000 */
+#define DFSDM_FLTCR1_JEXTSEL_Pos        (8U)
+#define DFSDM_FLTCR1_JEXTSEL_Msk        (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos)   /*!< 0x00001F00 */
+#define DFSDM_FLTCR1_JEXTSEL            DFSDM_FLTCR1_JEXTSEL_Msk               /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */
+#define DFSDM_FLTCR1_JEXTSEL_0          (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000100 */
+#define DFSDM_FLTCR1_JEXTSEL_1          (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000200 */
+#define DFSDM_FLTCR1_JEXTSEL_2          (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000400 */
+#define DFSDM_FLTCR1_JEXTSEL_3          (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000800 */
+#define DFSDM_FLTCR1_JEXTSEL_4          (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00001000 */
+
+#define DFSDM_FLTCR1_JDMAEN_Pos         (5U)
+#define DFSDM_FLTCR1_JDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos)     /*!< 0x00000020 */
+#define DFSDM_FLTCR1_JDMAEN             DFSDM_FLTCR1_JDMAEN_Msk                /*!< DMA channel enabled to read data for the injected channel group */
+#define DFSDM_FLTCR1_JSCAN_Pos          (4U)
+#define DFSDM_FLTCR1_JSCAN_Msk          (0x1UL << DFSDM_FLTCR1_JSCAN_Pos)      /*!< 0x00000010 */
+#define DFSDM_FLTCR1_JSCAN              DFSDM_FLTCR1_JSCAN_Msk                 /*!< Scanning conversion in continuous mode selection for injected conversions */
+#define DFSDM_FLTCR1_JSYNC_Pos          (3U)
+#define DFSDM_FLTCR1_JSYNC_Msk          (0x1UL << DFSDM_FLTCR1_JSYNC_Pos)      /*!< 0x00000008 */
+#define DFSDM_FLTCR1_JSYNC              DFSDM_FLTCR1_JSYNC_Msk                 /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */
+#define DFSDM_FLTCR1_JSWSTART_Pos       (1U)
+#define DFSDM_FLTCR1_JSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos)   /*!< 0x00000002 */
+#define DFSDM_FLTCR1_JSWSTART           DFSDM_FLTCR1_JSWSTART_Msk              /*!< Start the conversion of the injected group of channels */
+#define DFSDM_FLTCR1_DFEN_Pos           (0U)
+#define DFSDM_FLTCR1_DFEN_Msk           (0x1UL << DFSDM_FLTCR1_DFEN_Pos)       /*!< 0x00000001 */
+#define DFSDM_FLTCR1_DFEN               DFSDM_FLTCR1_DFEN_Msk                  /*!< DFSDM enable */
+
+/********************  Bit definition for DFSDM_FLTCR2 register *******************/
+#define DFSDM_FLTCR2_AWDCH_Pos          (16U)
+#define DFSDM_FLTCR2_AWDCH_Msk          (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos)     /*!< 0x00FF0000 */
+#define DFSDM_FLTCR2_AWDCH              DFSDM_FLTCR2_AWDCH_Msk                 /*!< AWDCH[7:0] Analog watchdog channel selection */
+#define DFSDM_FLTCR2_EXCH_Pos           (8U)
+#define DFSDM_FLTCR2_EXCH_Msk           (0xFFUL << DFSDM_FLTCR2_EXCH_Pos)      /*!< 0x0000FF00 */
+#define DFSDM_FLTCR2_EXCH               DFSDM_FLTCR2_EXCH_Msk                  /*!< EXCH[7:0] Extreme detector channel selection */
+#define DFSDM_FLTCR2_CKABIE_Pos         (6U)
+#define DFSDM_FLTCR2_CKABIE_Msk         (0x1UL << DFSDM_FLTCR2_CKABIE_Pos)     /*!< 0x00000040 */
+#define DFSDM_FLTCR2_CKABIE             DFSDM_FLTCR2_CKABIE_Msk                /*!< Clock absence interrupt enable */
+#define DFSDM_FLTCR2_SCDIE_Pos          (5U)
+#define DFSDM_FLTCR2_SCDIE_Msk          (0x1UL << DFSDM_FLTCR2_SCDIE_Pos)      /*!< 0x00000020 */
+#define DFSDM_FLTCR2_SCDIE              DFSDM_FLTCR2_SCDIE_Msk                 /*!< Short circuit detector interrupt enable */
+#define DFSDM_FLTCR2_AWDIE_Pos          (4U)
+#define DFSDM_FLTCR2_AWDIE_Msk          (0x1UL << DFSDM_FLTCR2_AWDIE_Pos)      /*!< 0x00000010 */
+#define DFSDM_FLTCR2_AWDIE              DFSDM_FLTCR2_AWDIE_Msk                 /*!< Analog watchdog interrupt enable */
+#define DFSDM_FLTCR2_ROVRIE_Pos         (3U)
+#define DFSDM_FLTCR2_ROVRIE_Msk         (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos)     /*!< 0x00000008 */
+#define DFSDM_FLTCR2_ROVRIE             DFSDM_FLTCR2_ROVRIE_Msk                /*!< Regular data overrun interrupt enable */
+#define DFSDM_FLTCR2_JOVRIE_Pos         (2U)
+#define DFSDM_FLTCR2_JOVRIE_Msk         (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos)     /*!< 0x00000004 */
+#define DFSDM_FLTCR2_JOVRIE             DFSDM_FLTCR2_JOVRIE_Msk                /*!< Injected data overrun interrupt enable */
+#define DFSDM_FLTCR2_REOCIE_Pos         (1U)
+#define DFSDM_FLTCR2_REOCIE_Msk         (0x1UL << DFSDM_FLTCR2_REOCIE_Pos)     /*!< 0x00000002 */
+#define DFSDM_FLTCR2_REOCIE             DFSDM_FLTCR2_REOCIE_Msk                /*!< Regular end of conversion interrupt enable */
+#define DFSDM_FLTCR2_JEOCIE_Pos         (0U)
+#define DFSDM_FLTCR2_JEOCIE_Msk         (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos)     /*!< 0x00000001 */
+#define DFSDM_FLTCR2_JEOCIE             DFSDM_FLTCR2_JEOCIE_Msk                /*!< Injected end of conversion interrupt enable */
+
+/********************  Bit definition for DFSDM_FLTISR register *******************/
+#define DFSDM_FLTISR_SCDF_Pos           (24U)
+#define DFSDM_FLTISR_SCDF_Msk           (0xFFUL << DFSDM_FLTISR_SCDF_Pos)      /*!< 0xFF000000 */
+#define DFSDM_FLTISR_SCDF               DFSDM_FLTISR_SCDF_Msk                  /*!< SCDF[7:0] Short circuit detector flag */
+#define DFSDM_FLTISR_CKABF_Pos          (16U)
+#define DFSDM_FLTISR_CKABF_Msk          (0xFFUL << DFSDM_FLTISR_CKABF_Pos)     /*!< 0x00FF0000 */
+#define DFSDM_FLTISR_CKABF              DFSDM_FLTISR_CKABF_Msk                 /*!< CKABF[7:0] Clock absence flag */
+#define DFSDM_FLTISR_RCIP_Pos           (14U)
+#define DFSDM_FLTISR_RCIP_Msk           (0x1UL << DFSDM_FLTISR_RCIP_Pos)       /*!< 0x00004000 */
+#define DFSDM_FLTISR_RCIP               DFSDM_FLTISR_RCIP_Msk                  /*!< Regular conversion in progress status */
+#define DFSDM_FLTISR_JCIP_Pos           (13U)
+#define DFSDM_FLTISR_JCIP_Msk           (0x1UL << DFSDM_FLTISR_JCIP_Pos)       /*!< 0x00002000 */
+#define DFSDM_FLTISR_JCIP               DFSDM_FLTISR_JCIP_Msk                  /*!< Injected conversion in progress status */
+#define DFSDM_FLTISR_AWDF_Pos           (4U)
+#define DFSDM_FLTISR_AWDF_Msk           (0x1UL << DFSDM_FLTISR_AWDF_Pos)       /*!< 0x00000010 */
+#define DFSDM_FLTISR_AWDF               DFSDM_FLTISR_AWDF_Msk                  /*!< Analog watchdog */
+#define DFSDM_FLTISR_ROVRF_Pos          (3U)
+#define DFSDM_FLTISR_ROVRF_Msk          (0x1UL << DFSDM_FLTISR_ROVRF_Pos)      /*!< 0x00000008 */
+#define DFSDM_FLTISR_ROVRF              DFSDM_FLTISR_ROVRF_Msk                 /*!< Regular conversion overrun flag */
+#define DFSDM_FLTISR_JOVRF_Pos          (2U)
+#define DFSDM_FLTISR_JOVRF_Msk          (0x1UL << DFSDM_FLTISR_JOVRF_Pos)      /*!< 0x00000004 */
+#define DFSDM_FLTISR_JOVRF              DFSDM_FLTISR_JOVRF_Msk                 /*!< Injected conversion overrun flag */
+#define DFSDM_FLTISR_REOCF_Pos          (1U)
+#define DFSDM_FLTISR_REOCF_Msk          (0x1UL << DFSDM_FLTISR_REOCF_Pos)      /*!< 0x00000002 */
+#define DFSDM_FLTISR_REOCF              DFSDM_FLTISR_REOCF_Msk                 /*!< End of regular conversion flag */
+#define DFSDM_FLTISR_JEOCF_Pos          (0U)
+#define DFSDM_FLTISR_JEOCF_Msk          (0x1UL << DFSDM_FLTISR_JEOCF_Pos)      /*!< 0x00000001 */
+#define DFSDM_FLTISR_JEOCF              DFSDM_FLTISR_JEOCF_Msk                 /*!< End of injected conversion flag */
+
+/********************  Bit definition for DFSDM_FLTICR register *******************/
+#define DFSDM_FLTICR_CLRSCDF_Pos        (24U)
+#define DFSDM_FLTICR_CLRSCDF_Msk        (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos)   /*!< 0xFF000000 */
+#define DFSDM_FLTICR_CLRSCDF            DFSDM_FLTICR_CLRSCDF_Msk               /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
+#define DFSDM_FLTICR_CLRCKABF_Pos       (16U)
+#define DFSDM_FLTICR_CLRCKABF_Msk       (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos)  /*!< 0x00FF0000 */
+#define DFSDM_FLTICR_CLRCKABF           DFSDM_FLTICR_CLRCKABF_Msk              /*!< CLRCKABF[7:0] Clear the clock absence flag */
+#define DFSDM_FLTICR_CLRROVRF_Pos       (3U)
+#define DFSDM_FLTICR_CLRROVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos)   /*!< 0x00000008 */
+#define DFSDM_FLTICR_CLRROVRF           DFSDM_FLTICR_CLRROVRF_Msk              /*!< Clear the regular conversion overrun flag */
+#define DFSDM_FLTICR_CLRJOVRF_Pos       (2U)
+#define DFSDM_FLTICR_CLRJOVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos)   /*!< 0x00000004 */
+#define DFSDM_FLTICR_CLRJOVRF           DFSDM_FLTICR_CLRJOVRF_Msk              /*!< Clear the injected conversion overrun flag */
+
+/*******************  Bit definition for DFSDM_FLTJCHGR register ******************/
+#define DFSDM_FLTJCHGR_JCHG_Pos         (0U)
+#define DFSDM_FLTJCHGR_JCHG_Msk         (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos)    /*!< 0x000000FF */
+#define DFSDM_FLTJCHGR_JCHG             DFSDM_FLTJCHGR_JCHG_Msk                /*!< JCHG[7:0] Injected channel group selection */
+
+/********************  Bit definition for DFSDM_FLTFCR register *******************/
+#define DFSDM_FLTFCR_FORD_Pos           (29U)
+#define DFSDM_FLTFCR_FORD_Msk           (0x7UL << DFSDM_FLTFCR_FORD_Pos)       /*!< 0xE0000000 */
+#define DFSDM_FLTFCR_FORD               DFSDM_FLTFCR_FORD_Msk                  /*!< FORD[2:0] Sinc filter order */
+#define DFSDM_FLTFCR_FORD_2             (0x4UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x80000000 */
+#define DFSDM_FLTFCR_FORD_1             (0x2UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x40000000 */
+#define DFSDM_FLTFCR_FORD_0             (0x1UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x20000000 */
+#define DFSDM_FLTFCR_FOSR_Pos           (16U)
+#define DFSDM_FLTFCR_FOSR_Msk           (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos)     /*!< 0x03FF0000 */
+#define DFSDM_FLTFCR_FOSR               DFSDM_FLTFCR_FOSR_Msk                  /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
+#define DFSDM_FLTFCR_IOSR_Pos           (0U)
+#define DFSDM_FLTFCR_IOSR_Msk           (0xFFUL << DFSDM_FLTFCR_IOSR_Pos)      /*!< 0x000000FF */
+#define DFSDM_FLTFCR_IOSR               DFSDM_FLTFCR_IOSR_Msk                  /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
+
+/******************  Bit definition for DFSDM_FLTJDATAR register *****************/
+#define DFSDM_FLTJDATAR_JDATA_Pos       (8U)
+#define DFSDM_FLTJDATAR_JDATA_Msk       (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTJDATAR_JDATA           DFSDM_FLTJDATAR_JDATA_Msk              /*!< JDATA[23:0] Injected group conversion data */
+#define DFSDM_FLTJDATAR_JDATACH_Pos     (0U)
+#define DFSDM_FLTJDATAR_JDATACH_Msk     (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */
+#define DFSDM_FLTJDATAR_JDATACH         DFSDM_FLTJDATAR_JDATACH_Msk            /*!< JDATACH[2:0] Injected channel most recently converted */
+
+/******************  Bit definition for DFSDM_FLTRDATAR register *****************/
+#define DFSDM_FLTRDATAR_RDATA_Pos       (8U)
+#define DFSDM_FLTRDATAR_RDATA_Msk       (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTRDATAR_RDATA           DFSDM_FLTRDATAR_RDATA_Msk              /*!< RDATA[23:0] Regular channel conversion data */
+#define DFSDM_FLTRDATAR_RPEND_Pos       (4U)
+#define DFSDM_FLTRDATAR_RPEND_Msk       (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos)   /*!< 0x00000010 */
+#define DFSDM_FLTRDATAR_RPEND           DFSDM_FLTRDATAR_RPEND_Msk              /*!< RPEND Regular channel pending data */
+#define DFSDM_FLTRDATAR_RDATACH_Pos     (0U)
+#define DFSDM_FLTRDATAR_RDATACH_Msk     (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */
+#define DFSDM_FLTRDATAR_RDATACH         DFSDM_FLTRDATAR_RDATACH_Msk            /*!< RDATACH[2:0] Regular channel most recently converted */
+
+/******************  Bit definition for DFSDM_FLTAWHTR register ******************/
+#define DFSDM_FLTAWHTR_AWHT_Pos         (8U)
+#define DFSDM_FLTAWHTR_AWHT_Msk         (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTAWHTR_AWHT             DFSDM_FLTAWHTR_AWHT_Msk                /*!< AWHT[23:0] Analog watchdog high threshold */
+#define DFSDM_FLTAWHTR_BKAWH_Pos        (0U)
+#define DFSDM_FLTAWHTR_BKAWH_Msk        (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)    /*!< 0x0000000F */
+#define DFSDM_FLTAWHTR_BKAWH            DFSDM_FLTAWHTR_BKAWH_Msk               /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
+
+/******************  Bit definition for DFSDM_FLTAWLTR register ******************/
+#define DFSDM_FLTAWLTR_AWLT_Pos         (8U)
+#define DFSDM_FLTAWLTR_AWLT_Msk         (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTAWLTR_AWLT             DFSDM_FLTAWLTR_AWLT_Msk                /*!< AWHT[23:0] Analog watchdog low threshold */
+#define DFSDM_FLTAWLTR_BKAWL_Pos        (0U)
+#define DFSDM_FLTAWLTR_BKAWL_Msk        (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos)    /*!< 0x0000000F */
+#define DFSDM_FLTAWLTR_BKAWL            DFSDM_FLTAWLTR_BKAWL_Msk               /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
+
+/******************  Bit definition for DFSDM_FLTAWSR register ******************/
+#define DFSDM_FLTAWSR_AWHTF_Pos         (8U)
+#define DFSDM_FLTAWSR_AWHTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos)    /*!< 0x0000FF00 */
+#define DFSDM_FLTAWSR_AWHTF             DFSDM_FLTAWSR_AWHTF_Msk                /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
+#define DFSDM_FLTAWSR_AWLTF_Pos         (0U)
+#define DFSDM_FLTAWSR_AWLTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos)    /*!< 0x000000FF */
+#define DFSDM_FLTAWSR_AWLTF             DFSDM_FLTAWSR_AWLTF_Msk                /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
+
+/******************  Bit definition for DFSDM_FLTAWCFR) register *****************/
+#define DFSDM_FLTAWCFR_CLRAWHTF_Pos     (8U)
+#define DFSDM_FLTAWCFR_CLRAWHTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */
+#define DFSDM_FLTAWCFR_CLRAWHTF         DFSDM_FLTAWCFR_CLRAWHTF_Msk            /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
+#define DFSDM_FLTAWCFR_CLRAWLTF_Pos     (0U)
+#define DFSDM_FLTAWCFR_CLRAWLTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */
+#define DFSDM_FLTAWCFR_CLRAWLTF         DFSDM_FLTAWCFR_CLRAWLTF_Msk            /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
+
+/******************  Bit definition for DFSDM_FLTEXMAX register ******************/
+#define DFSDM_FLTEXMAX_EXMAX_Pos        (8U)
+#define DFSDM_FLTEXMAX_EXMAX_Msk        (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTEXMAX_EXMAX            DFSDM_FLTEXMAX_EXMAX_Msk               /*!< EXMAX[23:0] Extreme detector maximum value */
+#define DFSDM_FLTEXMAX_EXMAXCH_Pos      (0U)
+#define DFSDM_FLTEXMAX_EXMAXCH_Msk      (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos)  /*!< 0x00000007 */
+#define DFSDM_FLTEXMAX_EXMAXCH          DFSDM_FLTEXMAX_EXMAXCH_Msk             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
+
+/******************  Bit definition for DFSDM_FLTEXMIN register ******************/
+#define DFSDM_FLTEXMIN_EXMIN_Pos        (8U)
+#define DFSDM_FLTEXMIN_EXMIN_Msk        (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTEXMIN_EXMIN            DFSDM_FLTEXMIN_EXMIN_Msk               /*!< EXMIN[23:0] Extreme detector minimum value */
+#define DFSDM_FLTEXMIN_EXMINCH_Pos      (0U)
+#define DFSDM_FLTEXMIN_EXMINCH_Msk      (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos)  /*!< 0x00000007 */
+#define DFSDM_FLTEXMIN_EXMINCH          DFSDM_FLTEXMIN_EXMINCH_Msk             /*!< EXMINCH[2:0] Extreme detector minimum data channel */
+
+/******************  Bit definition for DFSDM_FLTCNVTIMR register ******************/
+#define DFSDM_FLTCNVTIMR_CNVCNT_Pos     (4U)
+#define DFSDM_FLTCNVTIMR_CNVCNT_Msk     (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */
+#define DFSDM_FLTCNVTIMR_CNVCNT         DFSDM_FLTCNVTIMR_CNVCNT_Msk            /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           BDMA Controller                                  */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for BDMA_ISR register  ********************/
+#define BDMA_ISR_GIF0_Pos       (0U)
+#define BDMA_ISR_GIF0_Msk       (0x1UL << BDMA_ISR_GIF0_Pos)                   /*!< 0x00000001 */
+#define BDMA_ISR_GIF0           BDMA_ISR_GIF0_Msk                              /*!< Channel 0 Global interrupt flag */
+#define BDMA_ISR_TCIF0_Pos      (1U)
+#define BDMA_ISR_TCIF0_Msk      (0x1UL << BDMA_ISR_TCIF0_Pos)                  /*!< 0x00000002 */
+#define BDMA_ISR_TCIF0          BDMA_ISR_TCIF0_Msk                             /*!< Channel 0 Transfer Complete flag */
+#define BDMA_ISR_HTIF0_Pos      (2U)
+#define BDMA_ISR_HTIF0_Msk      (0x1UL << BDMA_ISR_HTIF0_Pos)                  /*!< 0x00000004 */
+#define BDMA_ISR_HTIF0          BDMA_ISR_HTIF0_Msk                             /*!< Channel 0 Half Transfer flag */
+#define BDMA_ISR_TEIF0_Pos      (3U)
+#define BDMA_ISR_TEIF0_Msk      (0x1UL << BDMA_ISR_TEIF0_Pos)                  /*!< 0x00000008 */
+#define BDMA_ISR_TEIF0          BDMA_ISR_TEIF0_Msk                             /*!< Channel 0 Transfer Error flag */
+#define BDMA_ISR_GIF1_Pos       (4U)
+#define BDMA_ISR_GIF1_Msk       (0x1UL << BDMA_ISR_GIF1_Pos)                   /*!< 0x00000010 */
+#define BDMA_ISR_GIF1           BDMA_ISR_GIF1_Msk                              /*!< Channel 1 Global interrupt flag */
+#define BDMA_ISR_TCIF1_Pos      (5U)
+#define BDMA_ISR_TCIF1_Msk      (0x1UL << BDMA_ISR_TCIF1_Pos)                  /*!< 0x00000020 */
+#define BDMA_ISR_TCIF1          BDMA_ISR_TCIF1_Msk                             /*!< Channel 1 Transfer Complete flag */
+#define BDMA_ISR_HTIF1_Pos      (6U)
+#define BDMA_ISR_HTIF1_Msk      (0x1UL << BDMA_ISR_HTIF1_Pos)                  /*!< 0x00000040 */
+#define BDMA_ISR_HTIF1          BDMA_ISR_HTIF1_Msk                             /*!< Channel 1 Half Transfer flag */
+#define BDMA_ISR_TEIF1_Pos      (7U)
+#define BDMA_ISR_TEIF1_Msk      (0x1UL << BDMA_ISR_TEIF1_Pos)                  /*!< 0x00000080 */
+#define BDMA_ISR_TEIF1          BDMA_ISR_TEIF1_Msk                             /*!< Channel 1 Transfer Error flag */
+#define BDMA_ISR_GIF2_Pos       (8U)
+#define BDMA_ISR_GIF2_Msk       (0x1UL << BDMA_ISR_GIF2_Pos)                   /*!< 0x00000100 */
+#define BDMA_ISR_GIF2           BDMA_ISR_GIF2_Msk                              /*!< Channel 2 Global interrupt flag */
+#define BDMA_ISR_TCIF2_Pos      (9U)
+#define BDMA_ISR_TCIF2_Msk      (0x1UL << BDMA_ISR_TCIF2_Pos)                  /*!< 0x00000200 */
+#define BDMA_ISR_TCIF2          BDMA_ISR_TCIF2_Msk                             /*!< Channel 2 Transfer Complete flag */
+#define BDMA_ISR_HTIF2_Pos      (10U)
+#define BDMA_ISR_HTIF2_Msk      (0x1UL << BDMA_ISR_HTIF2_Pos)                  /*!< 0x00000400 */
+#define BDMA_ISR_HTIF2          BDMA_ISR_HTIF2_Msk                             /*!< Channel 2 Half Transfer flag */
+#define BDMA_ISR_TEIF2_Pos      (11U)
+#define BDMA_ISR_TEIF2_Msk      (0x1UL << BDMA_ISR_TEIF2_Pos)                  /*!< 0x00000800 */
+#define BDMA_ISR_TEIF2          BDMA_ISR_TEIF2_Msk                             /*!< Channel 2 Transfer Error flag */
+#define BDMA_ISR_GIF3_Pos       (12U)
+#define BDMA_ISR_GIF3_Msk       (0x1UL << BDMA_ISR_GIF3_Pos)                   /*!< 0x00001000 */
+#define BDMA_ISR_GIF3           BDMA_ISR_GIF3_Msk                              /*!< Channel 3 Global interrupt flag */
+#define BDMA_ISR_TCIF3_Pos      (13U)
+#define BDMA_ISR_TCIF3_Msk      (0x1UL << BDMA_ISR_TCIF3_Pos)                  /*!< 0x00002000 */
+#define BDMA_ISR_TCIF3          BDMA_ISR_TCIF3_Msk                             /*!< Channel 3 Transfer Complete flag */
+#define BDMA_ISR_HTIF3_Pos      (14U)
+#define BDMA_ISR_HTIF3_Msk      (0x1UL << BDMA_ISR_HTIF3_Pos)                  /*!< 0x00004000 */
+#define BDMA_ISR_HTIF3          BDMA_ISR_HTIF3_Msk                             /*!< Channel 3 Half Transfer flag */
+#define BDMA_ISR_TEIF3_Pos      (15U)
+#define BDMA_ISR_TEIF3_Msk      (0x1UL << BDMA_ISR_TEIF3_Pos)                  /*!< 0x00008000 */
+#define BDMA_ISR_TEIF3          BDMA_ISR_TEIF3_Msk                             /*!< Channel 3 Transfer Error flag */
+#define BDMA_ISR_GIF4_Pos       (16U)
+#define BDMA_ISR_GIF4_Msk       (0x1UL << BDMA_ISR_GIF4_Pos)                   /*!< 0x00010000 */
+#define BDMA_ISR_GIF4           BDMA_ISR_GIF4_Msk                              /*!< Channel 4 Global interrupt flag */
+#define BDMA_ISR_TCIF4_Pos      (17U)
+#define BDMA_ISR_TCIF4_Msk      (0x1UL << BDMA_ISR_TCIF4_Pos)                  /*!< 0x00020000 */
+#define BDMA_ISR_TCIF4          BDMA_ISR_TCIF4_Msk                             /*!< Channel 4 Transfer Complete flag */
+#define BDMA_ISR_HTIF4_Pos      (18U)
+#define BDMA_ISR_HTIF4_Msk      (0x1UL << BDMA_ISR_HTIF4_Pos)                  /*!< 0x00040000 */
+#define BDMA_ISR_HTIF4          BDMA_ISR_HTIF4_Msk                             /*!< Channel 4 Half Transfer flag */
+#define BDMA_ISR_TEIF4_Pos      (19U)
+#define BDMA_ISR_TEIF4_Msk      (0x1UL << BDMA_ISR_TEIF4_Pos)                  /*!< 0x00080000 */
+#define BDMA_ISR_TEIF4          BDMA_ISR_TEIF4_Msk                             /*!< Channel 4 Transfer Error flag */
+#define BDMA_ISR_GIF5_Pos       (20U)
+#define BDMA_ISR_GIF5_Msk       (0x1UL << BDMA_ISR_GIF5_Pos)                   /*!< 0x00100000 */
+#define BDMA_ISR_GIF5           BDMA_ISR_GIF5_Msk                              /*!< Channel 5 Global interrupt flag */
+#define BDMA_ISR_TCIF5_Pos      (21U)
+#define BDMA_ISR_TCIF5_Msk      (0x1UL << BDMA_ISR_TCIF5_Pos)                  /*!< 0x00200000 */
+#define BDMA_ISR_TCIF5          BDMA_ISR_TCIF5_Msk                             /*!< Channel 5 Transfer Complete flag */
+#define BDMA_ISR_HTIF5_Pos      (22U)
+#define BDMA_ISR_HTIF5_Msk      (0x1UL << BDMA_ISR_HTIF5_Pos)                  /*!< 0x00400000 */
+#define BDMA_ISR_HTIF5          BDMA_ISR_HTIF5_Msk                             /*!< Channel 5 Half Transfer flag */
+#define BDMA_ISR_TEIF5_Pos      (23U)
+#define BDMA_ISR_TEIF5_Msk      (0x1UL << BDMA_ISR_TEIF5_Pos)                  /*!< 0x00800000 */
+#define BDMA_ISR_TEIF5          BDMA_ISR_TEIF5_Msk                             /*!< Channel 5 Transfer Error flag */
+#define BDMA_ISR_GIF6_Pos       (24U)
+#define BDMA_ISR_GIF6_Msk       (0x1UL << BDMA_ISR_GIF6_Pos)                   /*!< 0x01000000 */
+#define BDMA_ISR_GIF6           BDMA_ISR_GIF6_Msk                              /*!< Channel 6 Global interrupt flag */
+#define BDMA_ISR_TCIF6_Pos      (25U)
+#define BDMA_ISR_TCIF6_Msk      (0x1UL << BDMA_ISR_TCIF6_Pos)                  /*!< 0x02000000 */
+#define BDMA_ISR_TCIF6          BDMA_ISR_TCIF6_Msk                             /*!< Channel 6 Transfer Complete flag */
+#define BDMA_ISR_HTIF6_Pos      (26U)
+#define BDMA_ISR_HTIF6_Msk      (0x1UL << BDMA_ISR_HTIF6_Pos)                  /*!< 0x04000000 */
+#define BDMA_ISR_HTIF6          BDMA_ISR_HTIF6_Msk                             /*!< Channel 6 Half Transfer flag */
+#define BDMA_ISR_TEIF6_Pos      (27U)
+#define BDMA_ISR_TEIF6_Msk      (0x1UL << BDMA_ISR_TEIF6_Pos)                  /*!< 0x08000000 */
+#define BDMA_ISR_TEIF6          BDMA_ISR_TEIF6_Msk                             /*!< Channel 6 Transfer Error flag */
+#define BDMA_ISR_GIF7_Pos       (28U)
+#define BDMA_ISR_GIF7_Msk       (0x1UL << BDMA_ISR_GIF7_Pos)                   /*!< 0x10000000 */
+#define BDMA_ISR_GIF7           BDMA_ISR_GIF7_Msk                              /*!< Channel 7 Global interrupt flag */
+#define BDMA_ISR_TCIF7_Pos      (29U)
+#define BDMA_ISR_TCIF7_Msk      (0x1UL << BDMA_ISR_TCIF7_Pos)                  /*!< 0x20000000 */
+#define BDMA_ISR_TCIF7          BDMA_ISR_TCIF7_Msk                             /*!< Channel 7 Transfer Complete flag */
+#define BDMA_ISR_HTIF7_Pos      (30U)
+#define BDMA_ISR_HTIF7_Msk      (0x1UL << BDMA_ISR_HTIF7_Pos)                  /*!< 0x40000000 */
+#define BDMA_ISR_HTIF7          BDMA_ISR_HTIF7_Msk                             /*!< Channel 7 Half Transfer flag */
+#define BDMA_ISR_TEIF7_Pos      (31U)
+#define BDMA_ISR_TEIF7_Msk      (0x1UL << BDMA_ISR_TEIF7_Pos)                  /*!< 0x80000000 */
+#define BDMA_ISR_TEIF7          BDMA_ISR_TEIF7_Msk                             /*!< Channel 7 Transfer Error flag */
+
+/*******************  Bit definition for BDMA_IFCR register  *******************/
+#define BDMA_IFCR_CGIF0_Pos     (0U)
+#define BDMA_IFCR_CGIF0_Msk     (0x1UL << BDMA_IFCR_CGIF0_Pos)                 /*!< 0x00000001 */
+#define BDMA_IFCR_CGIF0         BDMA_IFCR_CGIF0_Msk                            /*!< Channel 0 Global interrupt clearr */
+#define BDMA_IFCR_CTCIF0_Pos    (1U)
+#define BDMA_IFCR_CTCIF0_Msk    (0x1UL << BDMA_IFCR_CTCIF0_Pos)                /*!< 0x00000002 */
+#define BDMA_IFCR_CTCIF0        BDMA_IFCR_CTCIF0_Msk                           /*!< Channel 0 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF0_Pos    (2U)
+#define BDMA_IFCR_CHTIF0_Msk    (0x1UL << BDMA_IFCR_CHTIF0_Pos)                /*!< 0x00000004 */
+#define BDMA_IFCR_CHTIF0        BDMA_IFCR_CHTIF0_Msk                           /*!< Channel 0 Half Transfer clear */
+#define BDMA_IFCR_CTEIF0_Pos    (3U)
+#define BDMA_IFCR_CTEIF0_Msk    (0x1UL << BDMA_IFCR_CTEIF0_Pos)                /*!< 0x00000008 */
+#define BDMA_IFCR_CTEIF0        BDMA_IFCR_CTEIF0_Msk                           /*!< Channel 0 Transfer Error clear */
+#define BDMA_IFCR_CGIF1_Pos     (4U)
+#define BDMA_IFCR_CGIF1_Msk     (0x1UL << BDMA_IFCR_CGIF1_Pos)                 /*!< 0x00000010 */
+#define BDMA_IFCR_CGIF1         BDMA_IFCR_CGIF1_Msk                            /*!< Channel 1 Global interrupt clear */
+#define BDMA_IFCR_CTCIF1_Pos    (5U)
+#define BDMA_IFCR_CTCIF1_Msk    (0x1UL << BDMA_IFCR_CTCIF1_Pos)                /*!< 0x00000020 */
+#define BDMA_IFCR_CTCIF1        BDMA_IFCR_CTCIF1_Msk                           /*!< Channel 1 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF1_Pos    (6U)
+#define BDMA_IFCR_CHTIF1_Msk    (0x1UL << BDMA_IFCR_CHTIF1_Pos)                /*!< 0x00000040 */
+#define BDMA_IFCR_CHTIF1        BDMA_IFCR_CHTIF1_Msk                           /*!< Channel 1 Half Transfer clear */
+#define BDMA_IFCR_CTEIF1_Pos    (7U)
+#define BDMA_IFCR_CTEIF1_Msk    (0x1UL << BDMA_IFCR_CTEIF1_Pos)                /*!< 0x00000080 */
+#define BDMA_IFCR_CTEIF1        BDMA_IFCR_CTEIF1_Msk                           /*!< Channel 1 Transfer Error clear */
+#define BDMA_IFCR_CGIF2_Pos     (8U)
+#define BDMA_IFCR_CGIF2_Msk     (0x1UL << BDMA_IFCR_CGIF2_Pos)                 /*!< 0x00000100 */
+#define BDMA_IFCR_CGIF2         BDMA_IFCR_CGIF2_Msk                            /*!< Channel 2 Global interrupt clear */
+#define BDMA_IFCR_CTCIF2_Pos    (9U)
+#define BDMA_IFCR_CTCIF2_Msk    (0x1UL << BDMA_IFCR_CTCIF2_Pos)                /*!< 0x00000200 */
+#define BDMA_IFCR_CTCIF2        BDMA_IFCR_CTCIF2_Msk                           /*!< Channel 2 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF2_Pos    (10U)
+#define BDMA_IFCR_CHTIF2_Msk    (0x1UL << BDMA_IFCR_CHTIF2_Pos)                /*!< 0x00000400 */
+#define BDMA_IFCR_CHTIF2        BDMA_IFCR_CHTIF2_Msk                           /*!< Channel 2 Half Transfer clear */
+#define BDMA_IFCR_CTEIF2_Pos    (11U)
+#define BDMA_IFCR_CTEIF2_Msk    (0x1UL << BDMA_IFCR_CTEIF2_Pos)                /*!< 0x00000800 */
+#define BDMA_IFCR_CTEIF2        BDMA_IFCR_CTEIF2_Msk                           /*!< Channel 2 Transfer Error clear */
+#define BDMA_IFCR_CGIF3_Pos     (12U)
+#define BDMA_IFCR_CGIF3_Msk     (0x1UL << BDMA_IFCR_CGIF3_Pos)                 /*!< 0x00001000 */
+#define BDMA_IFCR_CGIF3         BDMA_IFCR_CGIF3_Msk                            /*!< Channel 3 Global interrupt clear */
+#define BDMA_IFCR_CTCIF3_Pos    (13U)
+#define BDMA_IFCR_CTCIF3_Msk    (0x1UL << BDMA_IFCR_CTCIF3_Pos)                /*!< 0x00002000 */
+#define BDMA_IFCR_CTCIF3        BDMA_IFCR_CTCIF3_Msk                           /*!< Channel 3 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF3_Pos    (14U)
+#define BDMA_IFCR_CHTIF3_Msk    (0x1UL << BDMA_IFCR_CHTIF3_Pos)                /*!< 0x00004000 */
+#define BDMA_IFCR_CHTIF3        BDMA_IFCR_CHTIF3_Msk                           /*!< Channel 3 Half Transfer clear */
+#define BDMA_IFCR_CTEIF3_Pos    (15U)
+#define BDMA_IFCR_CTEIF3_Msk    (0x1UL << BDMA_IFCR_CTEIF3_Pos)                /*!< 0x00008000 */
+#define BDMA_IFCR_CTEIF3        BDMA_IFCR_CTEIF3_Msk                           /*!< Channel 3 Transfer Error clear */
+#define BDMA_IFCR_CGIF4_Pos     (16U)
+#define BDMA_IFCR_CGIF4_Msk     (0x1UL << BDMA_IFCR_CGIF4_Pos)                 /*!< 0x00010000 */
+#define BDMA_IFCR_CGIF4         BDMA_IFCR_CGIF4_Msk                            /*!< Channel 4 Global interrupt clear */
+#define BDMA_IFCR_CTCIF4_Pos    (17U)
+#define BDMA_IFCR_CTCIF4_Msk    (0x1UL << BDMA_IFCR_CTCIF4_Pos)                /*!< 0x00020000 */
+#define BDMA_IFCR_CTCIF4        BDMA_IFCR_CTCIF4_Msk                           /*!< Channel 4 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF4_Pos    (18U)
+#define BDMA_IFCR_CHTIF4_Msk    (0x1UL << BDMA_IFCR_CHTIF4_Pos)                /*!< 0x00040000 */
+#define BDMA_IFCR_CHTIF4        BDMA_IFCR_CHTIF4_Msk                           /*!< Channel 4 Half Transfer clear */
+#define BDMA_IFCR_CTEIF4_Pos    (19U)
+#define BDMA_IFCR_CTEIF4_Msk    (0x1UL << BDMA_IFCR_CTEIF4_Pos)                /*!< 0x00080000 */
+#define BDMA_IFCR_CTEIF4        BDMA_IFCR_CTEIF4_Msk                           /*!< Channel 4 Transfer Error clear */
+#define BDMA_IFCR_CGIF5_Pos     (20U)
+#define BDMA_IFCR_CGIF5_Msk     (0x1UL << BDMA_IFCR_CGIF5_Pos)                 /*!< 0x00100000 */
+#define BDMA_IFCR_CGIF5         BDMA_IFCR_CGIF5_Msk                            /*!< Channel 5 Global interrupt clear */
+#define BDMA_IFCR_CTCIF5_Pos    (21U)
+#define BDMA_IFCR_CTCIF5_Msk    (0x1UL << BDMA_IFCR_CTCIF5_Pos)                /*!< 0x00200000 */
+#define BDMA_IFCR_CTCIF5        BDMA_IFCR_CTCIF5_Msk                           /*!< Channel 5 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF5_Pos    (22U)
+#define BDMA_IFCR_CHTIF5_Msk    (0x1UL << BDMA_IFCR_CHTIF5_Pos)                /*!< 0x00400000 */
+#define BDMA_IFCR_CHTIF5        BDMA_IFCR_CHTIF5_Msk                           /*!< Channel 5 Half Transfer clear */
+#define BDMA_IFCR_CTEIF5_Pos    (23U)
+#define BDMA_IFCR_CTEIF5_Msk    (0x1UL << BDMA_IFCR_CTEIF5_Pos)                /*!< 0x00800000 */
+#define BDMA_IFCR_CTEIF5        BDMA_IFCR_CTEIF5_Msk                           /*!< Channel 5 Transfer Error clear */
+#define BDMA_IFCR_CGIF6_Pos     (24U)
+#define BDMA_IFCR_CGIF6_Msk     (0x1UL << BDMA_IFCR_CGIF6_Pos)                 /*!< 0x01000000 */
+#define BDMA_IFCR_CGIF6         BDMA_IFCR_CGIF6_Msk                            /*!< Channel 6 Global interrupt clear */
+#define BDMA_IFCR_CTCIF6_Pos    (25U)
+#define BDMA_IFCR_CTCIF6_Msk    (0x1UL << BDMA_IFCR_CTCIF6_Pos)                /*!< 0x02000000 */
+#define BDMA_IFCR_CTCIF6        BDMA_IFCR_CTCIF6_Msk                           /*!< Channel 6 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF6_Pos    (26U)
+#define BDMA_IFCR_CHTIF6_Msk    (0x1UL << BDMA_IFCR_CHTIF6_Pos)                /*!< 0x04000000 */
+#define BDMA_IFCR_CHTIF6        BDMA_IFCR_CHTIF6_Msk                           /*!< Channel 6 Half Transfer clear */
+#define BDMA_IFCR_CTEIF6_Pos    (27U)
+#define BDMA_IFCR_CTEIF6_Msk    (0x1UL << BDMA_IFCR_CTEIF6_Pos)                /*!< 0x08000000 */
+#define BDMA_IFCR_CTEIF6        BDMA_IFCR_CTEIF6_Msk                           /*!< Channel 6 Transfer Error clear */
+#define BDMA_IFCR_CGIF7_Pos     (28U)
+#define BDMA_IFCR_CGIF7_Msk     (0x1UL << BDMA_IFCR_CGIF7_Pos)                 /*!< 0x10000000 */
+#define BDMA_IFCR_CGIF7         BDMA_IFCR_CGIF7_Msk                            /*!< Channel 7 Global interrupt clear */
+#define BDMA_IFCR_CTCIF7_Pos    (29U)
+#define BDMA_IFCR_CTCIF7_Msk    (0x1UL << BDMA_IFCR_CTCIF7_Pos)                /*!< 0x20000000 */
+#define BDMA_IFCR_CTCIF7        BDMA_IFCR_CTCIF7_Msk                           /*!< Channel 7 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF7_Pos    (30U)
+#define BDMA_IFCR_CHTIF7_Msk    (0x1UL << BDMA_IFCR_CHTIF7_Pos)                /*!< 0x40000000 */
+#define BDMA_IFCR_CHTIF7        BDMA_IFCR_CHTIF7_Msk                           /*!< Channel 7 Half Transfer clear */
+#define BDMA_IFCR_CTEIF7_Pos    (31U)
+#define BDMA_IFCR_CTEIF7_Msk    (0x1UL << BDMA_IFCR_CTEIF7_Pos)                /*!< 0x80000000 */
+#define BDMA_IFCR_CTEIF7        BDMA_IFCR_CTEIF7_Msk                           /*!< Channel 7 Transfer Error clear */
+
+/*******************  Bit definition for BDMA_CCR register  ********************/
+#define BDMA_CCR_EN_Pos         (0U)
+#define BDMA_CCR_EN_Msk         (0x1UL << BDMA_CCR_EN_Pos)                     /*!< 0x00000001 */
+#define BDMA_CCR_EN             BDMA_CCR_EN_Msk                                /*!< Channel enable                      */
+#define BDMA_CCR_TCIE_Pos       (1U)
+#define BDMA_CCR_TCIE_Msk       (0x1UL << BDMA_CCR_TCIE_Pos)                   /*!< 0x00000002 */
+#define BDMA_CCR_TCIE           BDMA_CCR_TCIE_Msk                              /*!< Transfer complete interrupt enable  */
+#define BDMA_CCR_HTIE_Pos       (2U)
+#define BDMA_CCR_HTIE_Msk       (0x1UL << BDMA_CCR_HTIE_Pos)                   /*!< 0x00000004 */
+#define BDMA_CCR_HTIE           BDMA_CCR_HTIE_Msk                              /*!< Half Transfer interrupt enable      */
+#define BDMA_CCR_TEIE_Pos       (3U)
+#define BDMA_CCR_TEIE_Msk       (0x1UL << BDMA_CCR_TEIE_Pos)                   /*!< 0x00000008 */
+#define BDMA_CCR_TEIE           BDMA_CCR_TEIE_Msk                              /*!< Transfer error interrupt enable     */
+#define BDMA_CCR_DIR_Pos        (4U)
+#define BDMA_CCR_DIR_Msk        (0x1UL << BDMA_CCR_DIR_Pos)                    /*!< 0x00000010 */
+#define BDMA_CCR_DIR            BDMA_CCR_DIR_Msk                               /*!< Data transfer direction             */
+#define BDMA_CCR_CIRC_Pos       (5U)
+#define BDMA_CCR_CIRC_Msk       (0x1UL << BDMA_CCR_CIRC_Pos)                   /*!< 0x00000020 */
+#define BDMA_CCR_CIRC           BDMA_CCR_CIRC_Msk                              /*!< Circular mode                       */
+#define BDMA_CCR_PINC_Pos       (6U)
+#define BDMA_CCR_PINC_Msk       (0x1UL << BDMA_CCR_PINC_Pos)                   /*!< 0x00000040 */
+#define BDMA_CCR_PINC           BDMA_CCR_PINC_Msk                              /*!< Peripheral increment mode           */
+#define BDMA_CCR_MINC_Pos       (7U)
+#define BDMA_CCR_MINC_Msk       (0x1UL << BDMA_CCR_MINC_Pos)                   /*!< 0x00000080 */
+#define BDMA_CCR_MINC           BDMA_CCR_MINC_Msk                              /*!< Memory increment mode               */
+
+#define BDMA_CCR_PSIZE_Pos      (8U)
+#define BDMA_CCR_PSIZE_Msk      (0x3UL << BDMA_CCR_PSIZE_Pos)                  /*!< 0x00000300 */
+#define BDMA_CCR_PSIZE          BDMA_CCR_PSIZE_Msk                             /*!< PSIZE[1:0] bits (Peripheral size)   */
+#define BDMA_CCR_PSIZE_0        (0x1UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000100 */
+#define BDMA_CCR_PSIZE_1        (0x2UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000200 */
+
+#define BDMA_CCR_MSIZE_Pos      (10U)
+#define BDMA_CCR_MSIZE_Msk      (0x3UL << BDMA_CCR_MSIZE_Pos)                  /*!< 0x00000C00 */
+#define BDMA_CCR_MSIZE          BDMA_CCR_MSIZE_Msk                             /*!< MSIZE[1:0] bits (Memory size)       */
+#define BDMA_CCR_MSIZE_0        (0x1UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000400 */
+#define BDMA_CCR_MSIZE_1        (0x2UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000800 */
+
+#define BDMA_CCR_PL_Pos         (12U)
+#define BDMA_CCR_PL_Msk         (0x3UL << BDMA_CCR_PL_Pos)                     /*!< 0x00003000 */
+#define BDMA_CCR_PL             BDMA_CCR_PL_Msk                                /*!< PL[1:0] bits(Channel Priority level)*/
+#define BDMA_CCR_PL_0           (0x1UL << BDMA_CCR_PL_Pos)                      /*!< 0x00001000 */
+#define BDMA_CCR_PL_1           (0x2UL << BDMA_CCR_PL_Pos)                      /*!< 0x00002000 */
+
+#define BDMA_CCR_MEM2MEM_Pos    (14U)
+#define BDMA_CCR_MEM2MEM_Msk    (0x1UL << BDMA_CCR_MEM2MEM_Pos)                /*!< 0x00004000 */
+#define BDMA_CCR_MEM2MEM        BDMA_CCR_MEM2MEM_Msk                           /*!< Memory to memory mode               */
+#define BDMA_CCR_DBM_Pos        (15U)
+#define BDMA_CCR_DBM_Msk        (0x1UL << BDMA_CCR_DBM_Pos)                    /*!< 0x0000A000 */
+#define BDMA_CCR_DBM            BDMA_CCR_DBM_Msk                               /*!< Memory to memory mode               */
+#define BDMA_CCR_CT_Pos         (16U)
+#define BDMA_CCR_CT_Msk         (0x1UL << BDMA_CCR_CT_Pos)                     /*!< 0x00010000 */
+#define BDMA_CCR_CT             BDMA_CCR_CT_Msk                                /*!< Memory to memory mode               */
+
+/******************  Bit definition for BDMA_CNDTR register  *******************/
+#define BDMA_CNDTR_NDT_Pos      (0U)
+#define BDMA_CNDTR_NDT_Msk      (0xFFFFUL << BDMA_CNDTR_NDT_Pos)               /*!< 0x0000FFFF */
+#define BDMA_CNDTR_NDT          BDMA_CNDTR_NDT_Msk                             /*!< Number of data to Transfer          */
+
+/******************  Bit definition for BDMA_CPAR register  ********************/
+#define BDMA_CPAR_PA_Pos        (0U)
+#define BDMA_CPAR_PA_Msk        (0xFFFFFFFFUL << BDMA_CPAR_PA_Pos)             /*!< 0xFFFFFFFF */
+#define BDMA_CPAR_PA            BDMA_CPAR_PA_Msk                               /*!< Peripheral Address                  */
+
+/******************  Bit definition for BDMA_CM0AR register  ********************/
+#define BDMA_CM0AR_MA_Pos        (0U)
+#define BDMA_CM0AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM0AR_MA_Pos)             /*!< 0xFFFFFFFF */
+#define BDMA_CM0AR_MA            BDMA_CM0AR_MA_Msk                               /*!< Memory Address                      */
+
+/******************  Bit definition for BDMA_CM1AR register  ********************/
+#define BDMA_CM1AR_MA_Pos        (0U)
+#define BDMA_CM1AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM1AR_MA_Pos)             /*!< 0xFFFFFFFF */
+#define BDMA_CM1AR_MA            BDMA_CM1AR_MA_Msk                               /*!< Memory Address                      */
+
+/******************************************************************************/
+/*                                                                            */
+/*                Ethernet MAC Registers bits definitions                     */
+/*                                                                            */
+/******************************************************************************/
+/* Bit definition for Ethernet MAC Configuration Register register */
+#define ETH_MACCR_ARP_Pos                             (31U)
+#define ETH_MACCR_ARP_Msk                             (0x1UL << ETH_MACCR_ARP_Pos) /*!< 0x80000000 */
+#define ETH_MACCR_ARP                                 ETH_MACCR_ARP_Msk        /* ARP Offload Enable */
+#define ETH_MACCR_SARC_Pos                            (28U)
+#define ETH_MACCR_SARC_Msk                            (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
+#define ETH_MACCR_SARC                                ETH_MACCR_SARC_Msk       /* Source Address Insertion or Replacement Control */
+#define ETH_MACCR_SARC_MTIATI                         ((uint32_t)0x00000000)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
+#define ETH_MACCR_SARC_INSADDR0_Pos                   (29U)
+#define ETH_MACCR_SARC_INSADDR0_Msk                   (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
+#define ETH_MACCR_SARC_INSADDR0                       ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
+#define ETH_MACCR_SARC_INSADDR1_Pos                   (29U)
+#define ETH_MACCR_SARC_INSADDR1_Msk                   (0x3UL << ETH_MACCR_SARC_INSADDR1_Pos) /*!< 0x60000000 */
+#define ETH_MACCR_SARC_INSADDR1                       ETH_MACCR_SARC_INSADDR1_Msk /* Insert MAC Address1 in the SA field of all transmitted packets. */
+#define ETH_MACCR_SARC_REPADDR0_Pos                   (28U)
+#define ETH_MACCR_SARC_REPADDR0_Msk                   (0x3UL << ETH_MACCR_SARC_REPADDR0_Pos) /*!< 0x30000000 */
+#define ETH_MACCR_SARC_REPADDR0                       ETH_MACCR_SARC_REPADDR0_Msk /* Replace MAC Address0 in the SA field of all transmitted packets. */
+#define ETH_MACCR_SARC_REPADDR1_Pos                   (28U)
+#define ETH_MACCR_SARC_REPADDR1_Msk                   (0x7UL << ETH_MACCR_SARC_REPADDR1_Pos) /*!< 0x70000000 */
+#define ETH_MACCR_SARC_REPADDR1                       ETH_MACCR_SARC_REPADDR1_Msk /* Replace MAC Address1 in the SA field of all transmitted packets. */
+#define ETH_MACCR_IPC_Pos                             (27U)
+#define ETH_MACCR_IPC_Msk                             (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */
+#define ETH_MACCR_IPC                                 ETH_MACCR_IPC_Msk        /* Checksum Offload */
+#define ETH_MACCR_IPG_Pos                             (24U)
+#define ETH_MACCR_IPG_Msk                             (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
+#define ETH_MACCR_IPG                                 ETH_MACCR_IPG_Msk        /* Inter-Packet Gap */
+#define ETH_MACCR_IPG_96BIT                           ((uint32_t)0x00000000)   /* Minimum IFG between Packets during transmission is 96Bit */
+#define ETH_MACCR_IPG_88BIT                           ((uint32_t)0x01000000)   /* Minimum IFG between Packets during transmission is 88Bit */
+#define ETH_MACCR_IPG_80BIT                           ((uint32_t)0x02000000)   /* Minimum IFG between Packets during transmission is 80Bit */
+#define ETH_MACCR_IPG_72BIT                           ((uint32_t)0x03000000)   /* Minimum IFG between Packets during transmission is 72Bit */
+#define ETH_MACCR_IPG_64BIT                           ((uint32_t)0x04000000)   /* Minimum IFG between Packets during transmission is 64Bit */
+#define ETH_MACCR_IPG_56BIT                           ((uint32_t)0x05000000)   /* Minimum IFG between Packets during transmission is 56Bit */
+#define ETH_MACCR_IPG_48BIT                           ((uint32_t)0x06000000)   /* Minimum IFG between Packets during transmission is 48Bit */
+#define ETH_MACCR_IPG_40BIT                           ((uint32_t)0x07000000)   /* Minimum IFG between Packets during transmission is 40Bit */
+#define ETH_MACCR_GPSLCE_Pos                          (23U)
+#define ETH_MACCR_GPSLCE_Msk                          (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
+#define ETH_MACCR_GPSLCE                              ETH_MACCR_GPSLCE_Msk     /* Giant Packet Size Limit Control Enable */
+#define ETH_MACCR_S2KP_Pos                            (22U)
+#define ETH_MACCR_S2KP_Msk                            (0x1UL << ETH_MACCR_S2KP_Pos) /*!< 0x00400000 */
+#define ETH_MACCR_S2KP                                ETH_MACCR_S2KP_Msk       /* IEEE 802.3as Support for 2K Packets */
+#define ETH_MACCR_CST_Pos                             (21U)
+#define ETH_MACCR_CST_Msk                             (0x1UL << ETH_MACCR_CST_Pos) /*!< 0x00200000 */
+#define ETH_MACCR_CST                                 ETH_MACCR_CST_Msk        /* CRC stripping for Type packets */
+#define ETH_MACCR_ACS_Pos                             (20U)
+#define ETH_MACCR_ACS_Msk                             (0x1UL << ETH_MACCR_ACS_Pos) /*!< 0x00100000 */
+#define ETH_MACCR_ACS                                 ETH_MACCR_ACS_Msk        /* Automatic Pad or CRC Stripping */
+#define ETH_MACCR_WD_Pos                              (19U)
+#define ETH_MACCR_WD_Msk                              (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00080000 */
+#define ETH_MACCR_WD                                  ETH_MACCR_WD_Msk         /* Watchdog disable */
+#define ETH_MACCR_JD_Pos                              (17U)
+#define ETH_MACCR_JD_Msk                              (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00020000 */
+#define ETH_MACCR_JD                                  ETH_MACCR_JD_Msk         /* Jabber disable */
+#define ETH_MACCR_JE_Pos                              (16U)
+#define ETH_MACCR_JE_Msk                              (0x1UL << ETH_MACCR_JE_Pos) /*!< 0x00010000 */
+#define ETH_MACCR_JE                                  ETH_MACCR_JE_Msk         /* Jumbo Packet Enable */
+#define ETH_MACCR_FES_Pos                             (14U)
+#define ETH_MACCR_FES_Msk                             (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
+#define ETH_MACCR_FES                                 ETH_MACCR_FES_Msk        /* Fast ethernet speed */
+#define ETH_MACCR_DM_Pos                              (13U)
+#define ETH_MACCR_DM_Msk                              (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00002000 */
+#define ETH_MACCR_DM                                  ETH_MACCR_DM_Msk         /* Duplex mode */
+#define ETH_MACCR_LM_Pos                              (12U)
+#define ETH_MACCR_LM_Msk                              (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
+#define ETH_MACCR_LM                                  ETH_MACCR_LM_Msk         /* loopback mode */
+#define ETH_MACCR_ECRSFD_Pos                          (11U)
+#define ETH_MACCR_ECRSFD_Msk                          (0x1UL << ETH_MACCR_ECRSFD_Pos) /*!< 0x00000800 */
+#define ETH_MACCR_ECRSFD                              ETH_MACCR_ECRSFD_Msk     /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */
+#define ETH_MACCR_DO_Pos                              (10U)
+#define ETH_MACCR_DO_Msk                              (0x1UL << ETH_MACCR_DO_Pos) /*!< 0x00000400 */
+#define ETH_MACCR_DO                                  ETH_MACCR_DO_Msk         /* Disable Receive own  */
+#define ETH_MACCR_DCRS_Pos                            (9U)
+#define ETH_MACCR_DCRS_Msk                            (0x1UL << ETH_MACCR_DCRS_Pos) /*!< 0x00000200 */
+#define ETH_MACCR_DCRS                                ETH_MACCR_DCRS_Msk       /* Disable Carrier Sense During Transmission */
+#define ETH_MACCR_DR_Pos                              (8U)
+#define ETH_MACCR_DR_Msk                              (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */
+#define ETH_MACCR_DR                                  ETH_MACCR_DR_Msk         /* Disable Retry */
+#define ETH_MACCR_BL_Pos                              (5U)
+#define ETH_MACCR_BL_Msk                              (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
+#define ETH_MACCR_BL                                  ETH_MACCR_BL_Msk         /* Back-off limit mask */
+#define ETH_MACCR_BL_10                               (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */
+#define ETH_MACCR_BL_8                                (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */
+#define ETH_MACCR_BL_4                                (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */
+#define ETH_MACCR_BL_1                                (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
+#define ETH_MACCR_DC_Pos                              (4U)
+#define ETH_MACCR_DC_Msk                              (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
+#define ETH_MACCR_DC                                  ETH_MACCR_DC_Msk         /* Defferal check */
+#define ETH_MACCR_PRELEN_Pos                          (2U)
+#define ETH_MACCR_PRELEN_Msk                          (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */
+#define ETH_MACCR_PRELEN                              ETH_MACCR_PRELEN_Msk     /* Preamble Length for Transmit packets */
+#define ETH_MACCR_PRELEN_7                            (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */
+#define ETH_MACCR_PRELEN_5                            (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */
+#define ETH_MACCR_PRELEN_3                            (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */
+#define ETH_MACCR_TE_Pos                              (1U)
+#define ETH_MACCR_TE_Msk                              (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000002 */
+#define ETH_MACCR_TE                                  ETH_MACCR_TE_Msk         /* Transmitter enable */
+#define ETH_MACCR_RE_Pos                              (0U)
+#define ETH_MACCR_RE_Msk                              (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000001 */
+#define ETH_MACCR_RE                                  ETH_MACCR_RE_Msk         /* Receiver enable */
+
+/* Bit definition for Ethernet MAC Extended Configuration Register register */
+#define ETH_MACECR_EIPG_Pos                           (25U)
+#define ETH_MACECR_EIPG_Msk                           (0x1FUL << ETH_MACECR_EIPG_Pos) /*!< 0x3E000000 */
+#define ETH_MACECR_EIPG                               ETH_MACECR_EIPG_Msk      /* Extended Inter-Packet Gap */
+#define ETH_MACECR_EIPGEN_Pos                         (24U)
+#define ETH_MACECR_EIPGEN_Msk                         (0x1UL << ETH_MACECR_EIPGEN_Pos) /*!< 0x01000000 */
+#define ETH_MACECR_EIPGEN                             ETH_MACECR_EIPGEN_Msk    /* Extended Inter-Packet Gap Enable */
+#define ETH_MACECR_USP_Pos                            (18U)
+#define ETH_MACECR_USP_Msk                            (0x1UL << ETH_MACECR_USP_Pos) /*!< 0x00040000 */
+#define ETH_MACECR_USP                                ETH_MACECR_USP_Msk       /* Unicast Slow Protocol Packet Detect */
+#define ETH_MACECR_SPEN_Pos                           (17U)
+#define ETH_MACECR_SPEN_Msk                           (0x1UL << ETH_MACECR_SPEN_Pos) /*!< 0x00020000 */
+#define ETH_MACECR_SPEN                               ETH_MACECR_SPEN_Msk      /* Slow Protocol Detection Enable */
+#define ETH_MACECR_DCRCC_Pos                          (16U)
+#define ETH_MACECR_DCRCC_Msk                          (0x1UL << ETH_MACECR_DCRCC_Pos) /*!< 0x00010000 */
+#define ETH_MACECR_DCRCC                              ETH_MACECR_DCRCC_Msk     /* Disable CRC Checking for Received Packets */
+#define ETH_MACECR_GPSL_Pos                           (0U)
+#define ETH_MACECR_GPSL_Msk                           (0x3FFFUL << ETH_MACECR_GPSL_Pos) /*!< 0x00003FFF */
+#define ETH_MACECR_GPSL                               ETH_MACECR_GPSL_Msk      /* Giant Packet Size Limit */
+
+/* Bit definition for Ethernet MAC Packet Filter Register */
+#define ETH_MACPFR_RA_Pos                             (31U)
+#define ETH_MACPFR_RA_Msk                             (0x1UL << ETH_MACPFR_RA_Pos) /*!< 0x80000000 */
+#define ETH_MACPFR_RA                                 ETH_MACPFR_RA_Msk        /* Receive all */
+#define ETH_MACPFR_DNTU_Pos                           (21U)
+#define ETH_MACPFR_DNTU_Msk                           (0x1UL << ETH_MACPFR_DNTU_Pos) /*!< 0x00200000 */
+#define ETH_MACPFR_DNTU                               ETH_MACPFR_DNTU_Msk      /* Drop Non-TCP/UDP over IP Packets */
+#define ETH_MACPFR_IPFE_Pos                           (20U)
+#define ETH_MACPFR_IPFE_Msk                           (0x1UL << ETH_MACPFR_IPFE_Pos) /*!< 0x00100000 */
+#define ETH_MACPFR_IPFE                               ETH_MACPFR_IPFE_Msk      /* Layer 3 and Layer 4 Filter Enable */
+#define ETH_MACPFR_VTFE_Pos                           (16U)
+#define ETH_MACPFR_VTFE_Msk                           (0x1UL << ETH_MACPFR_VTFE_Pos) /*!< 0x00010000 */
+#define ETH_MACPFR_VTFE                               ETH_MACPFR_VTFE_Msk      /* VLAN Tag Filter Enable */
+#define ETH_MACPFR_HPF_Pos                            (10U)
+#define ETH_MACPFR_HPF_Msk                            (0x1UL << ETH_MACPFR_HPF_Pos) /*!< 0x00000400 */
+#define ETH_MACPFR_HPF                                ETH_MACPFR_HPF_Msk       /* Hash or perfect filter */
+#define ETH_MACPFR_SAF_Pos                            (9U)
+#define ETH_MACPFR_SAF_Msk                            (0x1UL << ETH_MACPFR_SAF_Pos) /*!< 0x00000200 */
+#define ETH_MACPFR_SAF                                ETH_MACPFR_SAF_Msk       /* Source address filter enable */
+#define ETH_MACPFR_SAIF_Pos                           (8U)
+#define ETH_MACPFR_SAIF_Msk                           (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */
+#define ETH_MACPFR_SAIF                               ETH_MACPFR_SAIF_Msk      /* SA inverse filtering */
+#define ETH_MACPFR_PCF_Pos                            (6U)
+#define ETH_MACPFR_PCF_Msk                            (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
+#define ETH_MACPFR_PCF                                ETH_MACPFR_PCF_Msk       /* Pass control frames: 4 cases */
+#define ETH_MACPFR_PCF_BLOCKALL                       ((uint32_t)0x00000000)   /* MAC filters all control frames from reaching the application */
+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos         (6U)
+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk         (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA             ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
+#define ETH_MACPFR_PCF_FORWARDALL_Pos                 (7U)
+#define ETH_MACPFR_PCF_FORWARDALL_Msk                 (0x1UL << ETH_MACPFR_PCF_FORWARDALL_Pos) /*!< 0x00000080 */
+#define ETH_MACPFR_PCF_FORWARDALL                     ETH_MACPFR_PCF_FORWARDALL_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos    (6U)
+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk    (0x3UL << ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos) /*!< 0x000000C0 */
+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER        ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk /* MAC forwards control frames that pass the Address Filter. */
+#define ETH_MACPFR_DBF_Pos                            (5U)
+#define ETH_MACPFR_DBF_Msk                            (0x1UL << ETH_MACPFR_DBF_Pos) /*!< 0x00000020 */
+#define ETH_MACPFR_DBF                                ETH_MACPFR_DBF_Msk       /* Disable Broadcast Packets */
+#define ETH_MACPFR_PM_Pos                             (4U)
+#define ETH_MACPFR_PM_Msk                             (0x1UL << ETH_MACPFR_PM_Pos) /*!< 0x00000010 */
+#define ETH_MACPFR_PM                                 ETH_MACPFR_PM_Msk        /* Pass all mutlicast */
+#define ETH_MACPFR_DAIF_Pos                           (3U)
+#define ETH_MACPFR_DAIF_Msk                           (0x1UL << ETH_MACPFR_DAIF_Pos) /*!< 0x00000008 */
+#define ETH_MACPFR_DAIF                               ETH_MACPFR_DAIF_Msk      /* DA Inverse filtering */
+#define ETH_MACPFR_HMC_Pos                            (2U)
+#define ETH_MACPFR_HMC_Msk                            (0x1UL << ETH_MACPFR_HMC_Pos) /*!< 0x00000004 */
+#define ETH_MACPFR_HMC                                ETH_MACPFR_HMC_Msk       /* Hash multicast */
+#define ETH_MACPFR_HUC_Pos                            (1U)
+#define ETH_MACPFR_HUC_Msk                            (0x1UL << ETH_MACPFR_HUC_Pos) /*!< 0x00000002 */
+#define ETH_MACPFR_HUC                                ETH_MACPFR_HUC_Msk       /* Hash unicast */
+#define ETH_MACPFR_PR_Pos                             (0U)
+#define ETH_MACPFR_PR_Msk                             (0x1UL << ETH_MACPFR_PR_Pos) /*!< 0x00000001 */
+#define ETH_MACPFR_PR                                 ETH_MACPFR_PR_Msk        /* Promiscuous mode */
+
+/* Bit definition for Ethernet MAC Watchdog Timeout Register */
+#define ETH_MACWTR_PWE_Pos                            (8U)
+#define ETH_MACWTR_PWE_Msk                            (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */
+#define ETH_MACWTR_PWE                                ETH_MACWTR_PWE_Msk       /* Programmable Watchdog Enable */
+#define ETH_MACWTR_WTO_Pos                            (0U)
+#define ETH_MACWTR_WTO_Msk                            (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
+#define ETH_MACWTR_WTO                                ETH_MACWTR_WTO_Msk       /* Watchdog Timeout */
+#define ETH_MACWTR_WTO_2KB                            ((uint32_t)0x00000000)   /* Maximum received packet length 2KB*/
+#define ETH_MACWTR_WTO_3KB                            ((uint32_t)0x00000001)   /* Maximum received packet length 3KB */
+#define ETH_MACWTR_WTO_4KB                            ((uint32_t)0x00000002)   /* Maximum received packet length 4KB */
+#define ETH_MACWTR_WTO_5KB                            ((uint32_t)0x00000003)   /* Maximum received packet length 5KB */
+#define ETH_MACWTR_WTO_6KB                            ((uint32_t)0x00000004)   /* Maximum received packet length 6KB */
+#define ETH_MACWTR_WTO_7KB                            ((uint32_t)0x00000005)   /* Maximum received packet length 7KB */
+#define ETH_MACWTR_WTO_8KB                            ((uint32_t)0x00000006)   /* Maximum received packet length 8KB */
+#define ETH_MACWTR_WTO_9KB                            ((uint32_t)0x00000007)   /* Maximum received packet length 9KB */
+#define ETH_MACWTR_WTO_10KB                           ((uint32_t)0x00000008)   /* Maximum received packet length 10KB */
+#define ETH_MACWTR_WTO_11KB                           ((uint32_t)0x00000009)   /* Maximum received packet length 11KB */
+#define ETH_MACWTR_WTO_12KB                           ((uint32_t)0x0000000A)   /* Maximum received packet length 12KB */
+#define ETH_MACWTR_WTO_13KB                           ((uint32_t)0x0000000B)   /* Maximum received packet length 13KB */
+#define ETH_MACWTR_WTO_14KB                           ((uint32_t)0x0000000C)   /* Maximum received packet length 14KB */
+#define ETH_MACWTR_WTO_15KB                           ((uint32_t)0x0000000D)   /* Maximum received packet length 15KB */
+#define ETH_MACWTR_WTO_16KB                           ((uint32_t)0x0000000E)   /* Maximum received packet length 16KB */
+
+/* Bit definition for Ethernet MAC Hash Table High Register */
+#define ETH_MACHTHR_HTH_Pos                           (0U)
+#define ETH_MACHTHR_HTH_Msk                           (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACHTHR_HTH                               ETH_MACHTHR_HTH_Msk      /* Hash table high */
+
+/* Bit definition for Ethernet MAC Hash Table Low Register */
+#define ETH_MACHTLR_HTL_Pos                           (0U)
+#define ETH_MACHTLR_HTL_Msk                           (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACHTLR_HTL                               ETH_MACHTLR_HTL_Msk      /* Hash table low */
+
+/* Bit definition for Ethernet MAC VLAN Tag Register */
+#define ETH_MACVTR_EIVLRXS_Pos                        (31U)
+#define ETH_MACVTR_EIVLRXS_Msk                        (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */
+#define ETH_MACVTR_EIVLRXS                            ETH_MACVTR_EIVLRXS_Msk   /* Enable Inner VLAN Tag in Rx Status */
+#define ETH_MACVTR_EIVLS_Pos                          (28U)
+#define ETH_MACVTR_EIVLS_Msk                          (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
+#define ETH_MACVTR_EIVLS                              ETH_MACVTR_EIVLS_Msk     /* Enable Inner VLAN Tag Stripping on Receive */
+#define ETH_MACVTR_EIVLS_DONOTSTRIP                   ((uint32_t)0x00000000)   /* Do not strip */
+#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos              (28U)
+#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk              (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
+#define ETH_MACVTR_EIVLS_STRIPIFPASS                  ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
+#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos             (29U)
+#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk             (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */
+#define ETH_MACVTR_EIVLS_STRIPIFFAILS                 ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
+#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos              (28U)
+#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk              (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */
+#define ETH_MACVTR_EIVLS_ALWAYSSTRIP                  ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */
+#define ETH_MACVTR_ERIVLT_Pos                         (27U)
+#define ETH_MACVTR_ERIVLT_Msk                         (0x1UL << ETH_MACVTR_ERIVLT_Pos) /*!< 0x08000000 */
+#define ETH_MACVTR_ERIVLT                             ETH_MACVTR_ERIVLT_Msk    /* Enable Inner VLAN Tag */
+#define ETH_MACVTR_EDVLP_Pos                          (26U)
+#define ETH_MACVTR_EDVLP_Msk                          (0x1UL << ETH_MACVTR_EDVLP_Pos) /*!< 0x04000000 */
+#define ETH_MACVTR_EDVLP                              ETH_MACVTR_EDVLP_Msk     /* Enable Double VLAN Processing */
+#define ETH_MACVTR_VTHM_Pos                           (25U)
+#define ETH_MACVTR_VTHM_Msk                           (0x1UL << ETH_MACVTR_VTHM_Pos) /*!< 0x02000000 */
+#define ETH_MACVTR_VTHM                               ETH_MACVTR_VTHM_Msk      /* VLAN Tag Hash Table Match Enable */
+#define ETH_MACVTR_EVLRXS_Pos                         (24U)
+#define ETH_MACVTR_EVLRXS_Msk                         (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */
+#define ETH_MACVTR_EVLRXS                             ETH_MACVTR_EVLRXS_Msk    /* Enable VLAN Tag in Rx status */
+#define ETH_MACVTR_EVLS_Pos                           (21U)
+#define ETH_MACVTR_EVLS_Msk                           (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
+#define ETH_MACVTR_EVLS                               ETH_MACVTR_EVLS_Msk      /* Enable VLAN Tag Stripping on Receive */
+#define ETH_MACVTR_EVLS_DONOTSTRIP                    ((uint32_t)0x00000000)   /* Do not strip */
+#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos               (21U)
+#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk               (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
+#define ETH_MACVTR_EVLS_STRIPIFPASS                   ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
+#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos              (22U)
+#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk              (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */
+#define ETH_MACVTR_EVLS_STRIPIFFAILS                  ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
+#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos               (21U)
+#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk               (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */
+#define ETH_MACVTR_EVLS_ALWAYSSTRIP                   ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */
+#define ETH_MACVTR_DOVLTC_Pos                         (20U)
+#define ETH_MACVTR_DOVLTC_Msk                         (0x1UL << ETH_MACVTR_DOVLTC_Pos) /*!< 0x00100000 */
+#define ETH_MACVTR_DOVLTC                             ETH_MACVTR_DOVLTC_Msk    /* Disable VLAN Type Check */
+#define ETH_MACVTR_ERSVLM_Pos                         (19U)
+#define ETH_MACVTR_ERSVLM_Msk                         (0x1UL << ETH_MACVTR_ERSVLM_Pos) /*!< 0x00080000 */
+#define ETH_MACVTR_ERSVLM                             ETH_MACVTR_ERSVLM_Msk    /* Enable Receive S-VLAN Match */
+#define ETH_MACVTR_ESVL_Pos                           (18U)
+#define ETH_MACVTR_ESVL_Msk                           (0x1UL << ETH_MACVTR_ESVL_Pos) /*!< 0x00040000 */
+#define ETH_MACVTR_ESVL                               ETH_MACVTR_ESVL_Msk      /* Enable S-VLAN */
+#define ETH_MACVTR_VTIM_Pos                           (17U)
+#define ETH_MACVTR_VTIM_Msk                           (0x1UL << ETH_MACVTR_VTIM_Pos) /*!< 0x00020000 */
+#define ETH_MACVTR_VTIM                               ETH_MACVTR_VTIM_Msk      /* VLAN Tag Inverse Match Enable */
+#define ETH_MACVTR_ETV_Pos                            (16U)
+#define ETH_MACVTR_ETV_Msk                            (0x1UL << ETH_MACVTR_ETV_Pos) /*!< 0x00010000 */
+#define ETH_MACVTR_ETV                                ETH_MACVTR_ETV_Msk       /* Enable 12-Bit VLAN Tag Comparison */
+#define ETH_MACVTR_VL_Pos                             (0U)
+#define ETH_MACVTR_VL_Msk                             (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */
+#define ETH_MACVTR_VL                                 ETH_MACVTR_VL_Msk        /* VLAN Tag Identifier for Receive Packets */
+#define ETH_MACVTR_VL_UP_Pos                          (13U)
+#define ETH_MACVTR_VL_UP_Msk                          (0x7UL << ETH_MACVTR_VL_UP_Pos) /*!< 0x0000E000 */
+#define ETH_MACVTR_VL_UP                              ETH_MACVTR_VL_UP_Msk     /* User Priority */
+#define ETH_MACVTR_VL_CFIDEI_Pos                      (12U)
+#define ETH_MACVTR_VL_CFIDEI_Msk                      (0x1UL << ETH_MACVTR_VL_CFIDEI_Pos) /*!< 0x00001000 */
+#define ETH_MACVTR_VL_CFIDEI                          ETH_MACVTR_VL_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
+#define ETH_MACVTR_VL_VID_Pos                         (0U)
+#define ETH_MACVTR_VL_VID_Msk                         (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */
+#define ETH_MACVTR_VL_VID                             ETH_MACVTR_VL_VID_Msk    /* VLAN Identifier field of VLAN tag */
+
+/* Bit definition for Ethernet MAC VLAN Hash Table Register */
+#define ETH_MACVHTR_VLHT_Pos                          (0U)
+#define ETH_MACVHTR_VLHT_Msk                          (0xFFFFUL << ETH_MACVHTR_VLHT_Pos) /*!< 0x0000FFFF */
+#define ETH_MACVHTR_VLHT                              ETH_MACVHTR_VLHT_Msk     /* VLAN Hash Table */
+
+/* Bit definition for Ethernet MAC VLAN Incl Register */
+#define ETH_MACVIR_VLTI_Pos                           (20U)
+#define ETH_MACVIR_VLTI_Msk                           (0x1UL << ETH_MACVIR_VLTI_Pos) /*!< 0x00100000 */
+#define ETH_MACVIR_VLTI                               ETH_MACVIR_VLTI_Msk      /* VLAN Tag Input */
+#define ETH_MACVIR_CSVL_Pos                           (19U)
+#define ETH_MACVIR_CSVL_Msk                           (0x1UL << ETH_MACVIR_CSVL_Pos) /*!< 0x00080000 */
+#define ETH_MACVIR_CSVL                               ETH_MACVIR_CSVL_Msk      /* C-VLAN or S-VLAN */
+#define ETH_MACVIR_VLP_Pos                            (18U)
+#define ETH_MACVIR_VLP_Msk                            (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */
+#define ETH_MACVIR_VLP                                ETH_MACVIR_VLP_Msk       /* VLAN Priority Control */
+#define ETH_MACVIR_VLC_Pos                            (16U)
+#define ETH_MACVIR_VLC_Msk                            (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
+#define ETH_MACVIR_VLC                                ETH_MACVIR_VLC_Msk       /* VLAN Tag Control in Transmit Packets */
+#define ETH_MACVIR_VLC_NOVLANTAG                      ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos              (16U)
+#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
+#define ETH_MACVIR_VLC_VLANTAGDELETE                  ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
+#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos              (17U)
+#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */
+#define ETH_MACVIR_VLC_VLANTAGINSERT                  ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
+#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos             (16U)
+#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk             (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */
+#define ETH_MACVIR_VLC_VLANTAGREPLACE                 ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
+#define ETH_MACVIR_VLT_Pos                            (0U)
+#define ETH_MACVIR_VLT_Msk                            (0xFFFFUL << ETH_MACVIR_VLT_Pos) /*!< 0x0000FFFF */
+#define ETH_MACVIR_VLT                                ETH_MACVIR_VLT_Msk       /* VLAN Tag for Transmit Packets */
+#define ETH_MACVIR_VLT_UP_Pos                         (13U)
+#define ETH_MACVIR_VLT_UP_Msk                         (0x7UL << ETH_MACVIR_VLT_UP_Pos) /*!< 0x0000E000 */
+#define ETH_MACVIR_VLT_UP                             ETH_MACVIR_VLT_UP_Msk    /* User Priority */
+#define ETH_MACVIR_VLT_CFIDEI_Pos                     (12U)
+#define ETH_MACVIR_VLT_CFIDEI_Msk                     (0x1UL << ETH_MACVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */
+#define ETH_MACVIR_VLT_CFIDEI                         ETH_MACVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
+#define ETH_MACVIR_VLT_VID_Pos                        (0U)
+#define ETH_MACVIR_VLT_VID_Msk                        (0xFFFUL << ETH_MACVIR_VLT_VID_Pos) /*!< 0x00000FFF */
+#define ETH_MACVIR_VLT_VID                            ETH_MACVIR_VLT_VID_Msk   /* VLAN Identifier field of VLAN tag */
+
+/* Bit definition for Ethernet MAC Inner_VLAN Incl Register */
+#define ETH_MACIVIR_VLTI_Pos                          (20U)
+#define ETH_MACIVIR_VLTI_Msk                          (0x1UL << ETH_MACIVIR_VLTI_Pos) /*!< 0x00100000 */
+#define ETH_MACIVIR_VLTI                              ETH_MACIVIR_VLTI_Msk     /* VLAN Tag Input */
+#define ETH_MACIVIR_CSVL_Pos                          (19U)
+#define ETH_MACIVIR_CSVL_Msk                          (0x1UL << ETH_MACIVIR_CSVL_Pos) /*!< 0x00080000 */
+#define ETH_MACIVIR_CSVL                              ETH_MACIVIR_CSVL_Msk     /* C-VLAN or S-VLAN */
+#define ETH_MACIVIR_VLP_Pos                           (18U)
+#define ETH_MACIVIR_VLP_Msk                           (0x1UL << ETH_MACIVIR_VLP_Pos) /*!< 0x00040000 */
+#define ETH_MACIVIR_VLP                               ETH_MACIVIR_VLP_Msk      /* VLAN Priority Control */
+#define ETH_MACIVIR_VLC_Pos                           (16U)
+#define ETH_MACIVIR_VLC_Msk                           (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
+#define ETH_MACIVIR_VLC                               ETH_MACIVIR_VLC_Msk      /* VLAN Tag Control in Transmit Packets */
+#define ETH_MACIVIR_VLC_NOVLANTAG                     ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos             (16U)
+#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
+#define ETH_MACIVIR_VLC_VLANTAGDELETE                 ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
+#define ETH_MACIVIR_VLC_VLANTAGINSERT_Pos             (17U)
+#define ETH_MACIVIR_VLC_VLANTAGINSERT_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */
+#define ETH_MACIVIR_VLC_VLANTAGINSERT                 ETH_MACIVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
+#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos            (16U)
+#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk            (0x3UL << ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */
+#define ETH_MACIVIR_VLC_VLANTAGREPLACE                ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
+#define ETH_MACIVIR_VLT_Pos                           (0U)
+#define ETH_MACIVIR_VLT_Msk                           (0xFFFFUL << ETH_MACIVIR_VLT_Pos) /*!< 0x0000FFFF */
+#define ETH_MACIVIR_VLT                               ETH_MACIVIR_VLT_Msk      /* VLAN Tag for Transmit Packets */
+#define ETH_MACIVIR_VLT_UP_Pos                        (13U)
+#define ETH_MACIVIR_VLT_UP_Msk                        (0x7UL << ETH_MACIVIR_VLT_UP_Pos) /*!< 0x0000E000 */
+#define ETH_MACIVIR_VLT_UP                            ETH_MACIVIR_VLT_UP_Msk   /* User Priority */
+#define ETH_MACIVIR_VLT_CFIDEI_Pos                    (12U)
+#define ETH_MACIVIR_VLT_CFIDEI_Msk                    (0x1UL << ETH_MACIVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */
+#define ETH_MACIVIR_VLT_CFIDEI                        ETH_MACIVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
+#define ETH_MACIVIR_VLT_VID_Pos                       (0U)
+#define ETH_MACIVIR_VLT_VID_Msk                       (0xFFFUL << ETH_MACIVIR_VLT_VID_Pos) /*!< 0x00000FFF */
+#define ETH_MACIVIR_VLT_VID                           ETH_MACIVIR_VLT_VID_Msk  /* VLAN Identifier field of VLAN tag */
+
+/* Bit definition for Ethernet MAC Tx Flow Ctrl Register */
+#define ETH_MACTFCR_PT_Pos                            (16U)
+#define ETH_MACTFCR_PT_Msk                            (0xFFFFUL << ETH_MACTFCR_PT_Pos) /*!< 0xFFFF0000 */
+#define ETH_MACTFCR_PT                                ETH_MACTFCR_PT_Msk       /* Pause Time */
+#define ETH_MACTFCR_DZPQ_Pos                          (7U)
+#define ETH_MACTFCR_DZPQ_Msk                          (0x1UL << ETH_MACTFCR_DZPQ_Pos) /*!< 0x00000080 */
+#define ETH_MACTFCR_DZPQ                              ETH_MACTFCR_DZPQ_Msk     /* Disable Zero-Quanta Pause */
+#define ETH_MACTFCR_PLT_Pos                           (4U)
+#define ETH_MACTFCR_PLT_Msk                           (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */
+#define ETH_MACTFCR_PLT                               ETH_MACTFCR_PLT_Msk      /* Pause Low Threshold */
+#define ETH_MACTFCR_PLT_MINUS4                        ((uint32_t)0x00000000)   /* Pause time minus 4 slot times */
+#define ETH_MACTFCR_PLT_MINUS28_Pos                   (4U)
+#define ETH_MACTFCR_PLT_MINUS28_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
+#define ETH_MACTFCR_PLT_MINUS28                       ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
+#define ETH_MACTFCR_PLT_MINUS36_Pos                   (5U)
+#define ETH_MACTFCR_PLT_MINUS36_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS36_Pos) /*!< 0x00000020 */
+#define ETH_MACTFCR_PLT_MINUS36                       ETH_MACTFCR_PLT_MINUS36_Msk /* Pause time minus 36 slot times */
+#define ETH_MACTFCR_PLT_MINUS144_Pos                  (4U)
+#define ETH_MACTFCR_PLT_MINUS144_Msk                  (0x3UL << ETH_MACTFCR_PLT_MINUS144_Pos) /*!< 0x00000030 */
+#define ETH_MACTFCR_PLT_MINUS144                      ETH_MACTFCR_PLT_MINUS144_Msk /* Pause time minus 144 slot times */
+#define ETH_MACTFCR_PLT_MINUS256_Pos                  (6U)
+#define ETH_MACTFCR_PLT_MINUS256_Msk                  (0x1UL << ETH_MACTFCR_PLT_MINUS256_Pos) /*!< 0x00000040 */
+#define ETH_MACTFCR_PLT_MINUS256                      ETH_MACTFCR_PLT_MINUS256_Msk /* Pause time minus 256 slot times */
+#define ETH_MACTFCR_PLT_MINUS512_Pos                  (4U)
+#define ETH_MACTFCR_PLT_MINUS512_Msk                  (0x5UL << ETH_MACTFCR_PLT_MINUS512_Pos) /*!< 0x00000050 */
+#define ETH_MACTFCR_PLT_MINUS512                      ETH_MACTFCR_PLT_MINUS512_Msk /* Pause time minus 512 slot times */
+#define ETH_MACTFCR_TFE_Pos                           (1U)
+#define ETH_MACTFCR_TFE_Msk                           (0x1UL << ETH_MACTFCR_TFE_Pos) /*!< 0x00000002 */
+#define ETH_MACTFCR_TFE                               ETH_MACTFCR_TFE_Msk      /* Transmit Flow Control Enable */
+#define ETH_MACTFCR_FCB_Pos                           (0U)
+#define ETH_MACTFCR_FCB_Msk                           (0x1UL << ETH_MACTFCR_FCB_Pos) /*!< 0x00000001 */
+#define ETH_MACTFCR_FCB                               ETH_MACTFCR_FCB_Msk      /* Flow Control Busy or Backpressure Activate */
+
+/* Bit definition for Ethernet MAC Rx Flow Ctrl Register */
+#define ETH_MACRFCR_UP_Pos                            (1U)
+#define ETH_MACRFCR_UP_Msk                            (0x1UL << ETH_MACRFCR_UP_Pos) /*!< 0x00000002 */
+#define ETH_MACRFCR_UP                                ETH_MACRFCR_UP_Msk       /* Unicast Pause Packet Detect */
+#define ETH_MACRFCR_RFE_Pos                           (0U)
+#define ETH_MACRFCR_RFE_Msk                           (0x1UL << ETH_MACRFCR_RFE_Pos) /*!< 0x00000001 */
+#define ETH_MACRFCR_RFE                               ETH_MACRFCR_RFE_Msk      /* Receive Flow Control Enable */
+
+/* Bit definition for Ethernet MAC Interrupt Status Register */
+#define ETH_MACISR_RXSTSIS_Pos                        (14U)
+#define ETH_MACISR_RXSTSIS_Msk                        (0x1UL << ETH_MACISR_RXSTSIS_Pos) /*!< 0x00004000 */
+#define ETH_MACISR_RXSTSIS                            ETH_MACISR_RXSTSIS_Msk   /* Receive Status Interrupt */
+#define ETH_MACISR_TXSTSIS_Pos                        (13U)
+#define ETH_MACISR_TXSTSIS_Msk                        (0x1UL << ETH_MACISR_TXSTSIS_Pos) /*!< 0x00002000 */
+#define ETH_MACISR_TXSTSIS                            ETH_MACISR_TXSTSIS_Msk   /* Transmit Status Interrupt */
+#define ETH_MACISR_TSIS_Pos                           (12U)
+#define ETH_MACISR_TSIS_Msk                           (0x1UL << ETH_MACISR_TSIS_Pos) /*!< 0x00001000 */
+#define ETH_MACISR_TSIS                               ETH_MACISR_TSIS_Msk      /* Timestamp Interrupt Status */
+#define ETH_MACISR_MMCTXIS_Pos                        (10U)
+#define ETH_MACISR_MMCTXIS_Msk                        (0x1UL << ETH_MACISR_MMCTXIS_Pos) /*!< 0x00000400 */
+#define ETH_MACISR_MMCTXIS                            ETH_MACISR_MMCTXIS_Msk   /* MMC Transmit Interrupt Status */
+#define ETH_MACISR_MMCRXIS_Pos                        (9U)
+#define ETH_MACISR_MMCRXIS_Msk                        (0x1UL << ETH_MACISR_MMCRXIS_Pos) /*!< 0x00000200 */
+#define ETH_MACISR_MMCRXIS                            ETH_MACISR_MMCRXIS_Msk   /* MMC Receive Interrupt Status */
+#define ETH_MACISR_MMCIS_Pos                          (8U)
+#define ETH_MACISR_MMCIS_Msk                          (0x1UL << ETH_MACISR_MMCIS_Pos) /*!< 0x00000100 */
+#define ETH_MACISR_MMCIS                              ETH_MACISR_MMCIS_Msk     /* MMC Interrupt Status */
+#define ETH_MACISR_LPIIS_Pos                          (5U)
+#define ETH_MACISR_LPIIS_Msk                          (0x1UL << ETH_MACISR_LPIIS_Pos) /*!< 0x00000020 */
+#define ETH_MACISR_LPIIS                              ETH_MACISR_LPIIS_Msk     /* LPI Interrupt Status */
+#define ETH_MACISR_PMTIS_Pos                          (4U)
+#define ETH_MACISR_PMTIS_Msk                          (0x1UL << ETH_MACISR_PMTIS_Pos) /*!< 0x00000010 */
+#define ETH_MACISR_PMTIS                              ETH_MACISR_PMTIS_Msk     /* PMT Interrupt Status */
+#define ETH_MACISR_PHYIS_Pos                          (3U)
+#define ETH_MACISR_PHYIS_Msk                          (0x1UL << ETH_MACISR_PHYIS_Pos) /*!< 0x00000008 */
+#define ETH_MACISR_PHYIS                              ETH_MACISR_PHYIS_Msk     /* PHY Interrupt */
+
+/* Bit definition for Ethernet MAC Interrupt Enable Register */
+#define ETH_MACIER_RXSTSIE_Pos                        (14U)
+#define ETH_MACIER_RXSTSIE_Msk                        (0x1UL << ETH_MACIER_RXSTSIE_Pos) /*!< 0x00004000 */
+#define ETH_MACIER_RXSTSIE                            ETH_MACIER_RXSTSIE_Msk   /* Receive Status Interrupt Enable */
+#define ETH_MACIER_TXSTSIE_Pos                        (13U)
+#define ETH_MACIER_TXSTSIE_Msk                        (0x1UL << ETH_MACIER_TXSTSIE_Pos) /*!< 0x00002000 */
+#define ETH_MACIER_TXSTSIE                            ETH_MACIER_TXSTSIE_Msk   /* Transmit Status Interrupt Enable */
+#define ETH_MACIER_TSIE_Pos                           (12U)
+#define ETH_MACIER_TSIE_Msk                           (0x1UL << ETH_MACIER_TSIE_Pos) /*!< 0x00001000 */
+#define ETH_MACIER_TSIE                               ETH_MACIER_TSIE_Msk      /* Timestamp Interrupt Enable */
+#define ETH_MACIER_LPIIE_Pos                          (5U)
+#define ETH_MACIER_LPIIE_Msk                          (0x1UL << ETH_MACIER_LPIIE_Pos) /*!< 0x00000020 */
+#define ETH_MACIER_LPIIE                              ETH_MACIER_LPIIE_Msk     /* LPI Interrupt Enable */
+#define ETH_MACIER_PMTIE_Pos                          (4U)
+#define ETH_MACIER_PMTIE_Msk                          (0x1UL << ETH_MACIER_PMTIE_Pos) /*!< 0x00000010 */
+#define ETH_MACIER_PMTIE                              ETH_MACIER_PMTIE_Msk     /* PMT Interrupt Enable */
+#define ETH_MACIER_PHYIE_Pos                          (3U)
+#define ETH_MACIER_PHYIE_Msk                          (0x1UL << ETH_MACIER_PHYIE_Pos) /*!< 0x00000008 */
+#define ETH_MACIER_PHYIE                              ETH_MACIER_PHYIE_Msk     /* PHY Interrupt Enable */
+
+/* Bit definition for Ethernet MAC Rx Tx Status Register */
+#define ETH_MACRXTXSR_RWT_Pos                         (8U)
+#define ETH_MACRXTXSR_RWT_Msk                         (0x1UL << ETH_MACRXTXSR_RWT_Pos) /*!< 0x00000100 */
+#define ETH_MACRXTXSR_RWT                             ETH_MACRXTXSR_RWT_Msk    /* Receive Watchdog Timeout */
+#define ETH_MACRXTXSR_EXCOL_Pos                       (5U)
+#define ETH_MACRXTXSR_EXCOL_Msk                       (0x1UL << ETH_MACRXTXSR_EXCOL_Pos) /*!< 0x00000020 */
+#define ETH_MACRXTXSR_EXCOL                           ETH_MACRXTXSR_EXCOL_Msk  /* Excessive Collisions */
+#define ETH_MACRXTXSR_LCOL_Pos                        (4U)
+#define ETH_MACRXTXSR_LCOL_Msk                        (0x1UL << ETH_MACRXTXSR_LCOL_Pos) /*!< 0x00000010 */
+#define ETH_MACRXTXSR_LCOL                            ETH_MACRXTXSR_LCOL_Msk   /* Late Collision */
+#define ETH_MACRXTXSR_EXDEF_Pos                       (3U)
+#define ETH_MACRXTXSR_EXDEF_Msk                       (0x1UL << ETH_MACRXTXSR_EXDEF_Pos) /*!< 0x00000008 */
+#define ETH_MACRXTXSR_EXDEF                           ETH_MACRXTXSR_EXDEF_Msk  /* Excessive Deferral */
+#define ETH_MACRXTXSR_LCARR_Pos                       (2U)
+#define ETH_MACRXTXSR_LCARR_Msk                       (0x1UL << ETH_MACRXTXSR_LCARR_Pos) /*!< 0x00000004 */
+#define ETH_MACRXTXSR_LCARR                           ETH_MACRXTXSR_LCARR_Msk  /* Loss of Carrier */
+#define ETH_MACRXTXSR_NCARR_Pos                       (1U)
+#define ETH_MACRXTXSR_NCARR_Msk                       (0x1UL << ETH_MACRXTXSR_NCARR_Pos) /*!< 0x00000002 */
+#define ETH_MACRXTXSR_NCARR                           ETH_MACRXTXSR_NCARR_Msk  /* No Carrier */
+#define ETH_MACRXTXSR_TJT_Pos                         (0U)
+#define ETH_MACRXTXSR_TJT_Msk                         (0x1UL << ETH_MACRXTXSR_TJT_Pos) /*!< 0x00000001 */
+#define ETH_MACRXTXSR_TJT                             ETH_MACRXTXSR_TJT_Msk    /* Transmit Jabber Timeout */
+
+/* Bit definition for Ethernet MAC PMT Control Status Register */
+#define ETH_MACPCSR_RWKFILTRST_Pos                    (31U)
+#define ETH_MACPCSR_RWKFILTRST_Msk                    (0x1UL << ETH_MACPCSR_RWKFILTRST_Pos) /*!< 0x80000000 */
+#define ETH_MACPCSR_RWKFILTRST                        ETH_MACPCSR_RWKFILTRST_Msk /* Remote Wake-Up Packet Filter Register Pointer Reset */
+#define ETH_MACPCSR_RWKPTR_Pos                        (24U)
+#define ETH_MACPCSR_RWKPTR_Msk                        (0x1FUL << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x1F000000 */
+#define ETH_MACPCSR_RWKPTR                            ETH_MACPCSR_RWKPTR_Msk   /* Remote Wake-up FIFO Pointer */
+#define ETH_MACPCSR_RWKPFE_Pos                        (10U)
+#define ETH_MACPCSR_RWKPFE_Msk                        (0x1UL << ETH_MACPCSR_RWKPFE_Pos) /*!< 0x00000400 */
+#define ETH_MACPCSR_RWKPFE                            ETH_MACPCSR_RWKPFE_Msk   /* Remote Wake-up Packet Forwarding Enable */
+#define ETH_MACPCSR_GLBLUCAST_Pos                     (9U)
+#define ETH_MACPCSR_GLBLUCAST_Msk                     (0x1UL << ETH_MACPCSR_GLBLUCAST_Pos) /*!< 0x00000200 */
+#define ETH_MACPCSR_GLBLUCAST                         ETH_MACPCSR_GLBLUCAST_Msk /* Global Unicast */
+#define ETH_MACPCSR_RWKPRCVD_Pos                      (6U)
+#define ETH_MACPCSR_RWKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_RWKPRCVD_Pos) /*!< 0x00000040 */
+#define ETH_MACPCSR_RWKPRCVD                          ETH_MACPCSR_RWKPRCVD_Msk /* Remote Wake-Up Packet Received */
+#define ETH_MACPCSR_MGKPRCVD_Pos                      (5U)
+#define ETH_MACPCSR_MGKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_MGKPRCVD_Pos) /*!< 0x00000020 */
+#define ETH_MACPCSR_MGKPRCVD                          ETH_MACPCSR_MGKPRCVD_Msk /* Magic Packet Received */
+#define ETH_MACPCSR_RWKPKTEN_Pos                      (2U)
+#define ETH_MACPCSR_RWKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_RWKPKTEN_Pos) /*!< 0x00000004 */
+#define ETH_MACPCSR_RWKPKTEN                          ETH_MACPCSR_RWKPKTEN_Msk /* Remote Wake-Up Packet Enable */
+#define ETH_MACPCSR_MGKPKTEN_Pos                      (1U)
+#define ETH_MACPCSR_MGKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_MGKPKTEN_Pos) /*!< 0x00000002 */
+#define ETH_MACPCSR_MGKPKTEN                          ETH_MACPCSR_MGKPKTEN_Msk /* Magic Packet Enable */
+#define ETH_MACPCSR_PWRDWN_Pos                        (0U)
+#define ETH_MACPCSR_PWRDWN_Msk                        (0x1UL << ETH_MACPCSR_PWRDWN_Pos) /*!< 0x00000001 */
+#define ETH_MACPCSR_PWRDWN                            ETH_MACPCSR_PWRDWN_Msk   /* Power Down */
+
+/* Bit definition for Ethernet MAC Remote Wake-Up Packet Filter Register */
+#define ETH_MACRWUPFR_D_Pos                           (0U)
+#define ETH_MACRWUPFR_D_Msk                           (0xFFFFFFFFUL << ETH_MACRWUPFR_D_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACRWUPFR_D                               ETH_MACRWUPFR_D_Msk      /* Wake-up Packet filter register data */
+
+/* Bit definition for Ethernet MAC LPI Control Status Register */
+#define ETH_MACLCSR_LPITCSE_Pos                       (21U)
+#define ETH_MACLCSR_LPITCSE_Msk                       (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */
+#define ETH_MACLCSR_LPITCSE                           ETH_MACLCSR_LPITCSE_Msk  /* LPI Tx Clock Stop Enable */
+#define ETH_MACLCSR_LPITE_Pos                         (20U)
+#define ETH_MACLCSR_LPITE_Msk                         (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */
+#define ETH_MACLCSR_LPITE                             ETH_MACLCSR_LPITE_Msk    /* LPI Timer Enable */
+#define ETH_MACLCSR_LPITXA_Pos                        (19U)
+#define ETH_MACLCSR_LPITXA_Msk                        (0x1UL << ETH_MACLCSR_LPITXA_Pos) /*!< 0x00080000 */
+#define ETH_MACLCSR_LPITXA                            ETH_MACLCSR_LPITXA_Msk   /* LPI Tx Automate */
+#define ETH_MACLCSR_PLS_Pos                           (17U)
+#define ETH_MACLCSR_PLS_Msk                           (0x1UL << ETH_MACLCSR_PLS_Pos) /*!< 0x00020000 */
+#define ETH_MACLCSR_PLS                               ETH_MACLCSR_PLS_Msk      /* PHY Link Status */
+#define ETH_MACLCSR_LPIEN_Pos                         (16U)
+#define ETH_MACLCSR_LPIEN_Msk                         (0x1UL << ETH_MACLCSR_LPIEN_Pos) /*!< 0x00010000 */
+#define ETH_MACLCSR_LPIEN                             ETH_MACLCSR_LPIEN_Msk    /* LPI Enable */
+#define ETH_MACLCSR_RLPIST_Pos                        (9U)
+#define ETH_MACLCSR_RLPIST_Msk                        (0x1UL << ETH_MACLCSR_RLPIST_Pos) /*!< 0x00000200 */
+#define ETH_MACLCSR_RLPIST                            ETH_MACLCSR_RLPIST_Msk   /* Receive LPI State */
+#define ETH_MACLCSR_TLPIST_Pos                        (8U)
+#define ETH_MACLCSR_TLPIST_Msk                        (0x1UL << ETH_MACLCSR_TLPIST_Pos) /*!< 0x00000100 */
+#define ETH_MACLCSR_TLPIST                            ETH_MACLCSR_TLPIST_Msk   /* Transmit LPI State */
+#define ETH_MACLCSR_RLPIEX_Pos                        (3U)
+#define ETH_MACLCSR_RLPIEX_Msk                        (0x1UL << ETH_MACLCSR_RLPIEX_Pos) /*!< 0x00000008 */
+#define ETH_MACLCSR_RLPIEX                            ETH_MACLCSR_RLPIEX_Msk   /* Receive LPI Exit */
+#define ETH_MACLCSR_RLPIEN_Pos                        (2U)
+#define ETH_MACLCSR_RLPIEN_Msk                        (0x1UL << ETH_MACLCSR_RLPIEN_Pos) /*!< 0x00000004 */
+#define ETH_MACLCSR_RLPIEN                            ETH_MACLCSR_RLPIEN_Msk   /* Receive LPI Entry */
+#define ETH_MACLCSR_TLPIEX_Pos                        (1U)
+#define ETH_MACLCSR_TLPIEX_Msk                        (0x1UL << ETH_MACLCSR_TLPIEX_Pos) /*!< 0x00000002 */
+#define ETH_MACLCSR_TLPIEX                            ETH_MACLCSR_TLPIEX_Msk   /* Transmit LPI Exit */
+#define ETH_MACLCSR_TLPIEN_Pos                        (0U)
+#define ETH_MACLCSR_TLPIEN_Msk                        (0x1UL << ETH_MACLCSR_TLPIEN_Pos) /*!< 0x00000001 */
+#define ETH_MACLCSR_TLPIEN                            ETH_MACLCSR_TLPIEN_Msk   /* Transmit LPI Entry */
+
+/* Bit definition for Ethernet MAC LPI Timers Control Register */
+#define ETH_MACLTCR_LST_Pos                           (16U)
+#define ETH_MACLTCR_LST_Msk                           (0x3FFUL << ETH_MACLTCR_LST_Pos) /*!< 0x03FF0000 */
+#define ETH_MACLTCR_LST                               ETH_MACLTCR_LST_Msk      /* LPI LS TIMER */
+#define ETH_MACLTCR_TWT_Pos                           (0U)
+#define ETH_MACLTCR_TWT_Msk                           (0xFFFFUL << ETH_MACLTCR_TWT_Pos) /*!< 0x0000FFFF */
+#define ETH_MACLTCR_TWT                               ETH_MACLTCR_TWT_Msk      /* LPI TW TIMER */
+
+/* Bit definition for Ethernet MAC LPI Entry Timer Register */
+#define ETH_MACLETR_LPIET_Pos                         (0U)
+#define ETH_MACLETR_LPIET_Msk                         (0xFFFFFUL << ETH_MACLETR_LPIET_Pos) /*!< 0x000FFFFF */
+#define ETH_MACLETR_LPIET                             ETH_MACLETR_LPIET_Msk    /* LPI Entry Timer */
+
+/* Bit definition for Ethernet MAC 1US Tic Counter Register */
+#define ETH_MAC1USTCR_TIC1USCNTR_Pos                  (0U)
+#define ETH_MAC1USTCR_TIC1USCNTR_Msk                  (0xFFFUL << ETH_MAC1USTCR_TIC1USCNTR_Pos) /*!< 0x00000FFF */
+#define ETH_MAC1USTCR_TIC1USCNTR                      ETH_MAC1USTCR_TIC1USCNTR_Msk /* 1US TIC Counter */
+
+/* Bit definition for Ethernet MAC Version Register */
+#define ETH_MACVR_USERVER_Pos                         (8U)
+#define ETH_MACVR_USERVER_Msk                         (0xFFUL << ETH_MACVR_USERVER_Pos) /*!< 0x0000FF00 */
+#define ETH_MACVR_USERVER                             ETH_MACVR_USERVER_Msk    /* User-defined Version */
+#define ETH_MACVR_SNPSVER_Pos                         (0U)
+#define ETH_MACVR_SNPSVER_Msk                         (0xFFUL << ETH_MACVR_SNPSVER_Pos) /*!< 0x000000FF */
+#define ETH_MACVR_SNPSVER                             ETH_MACVR_SNPSVER_Msk    /* Synopsys-defined Version */
+
+/* Bit definition for Ethernet MAC Debug Register */
+#define ETH_MACDR_TFCSTS_Pos                          (17U)
+#define ETH_MACDR_TFCSTS_Msk                          (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
+#define ETH_MACDR_TFCSTS                              ETH_MACDR_TFCSTS_Msk     /* MAC Transmit Packet Controller Status */
+#define ETH_MACDR_TFCSTS_IDLE                         ((uint32_t)0x00000000)   /* Idle state */
+#define ETH_MACDR_TFCSTS_WAIT_Pos                     (17U)
+#define ETH_MACDR_TFCSTS_WAIT_Msk                     (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
+#define ETH_MACDR_TFCSTS_WAIT                         ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
+#define ETH_MACDR_TFCSTS_GENERATEPCP_Pos              (18U)
+#define ETH_MACDR_TFCSTS_GENERATEPCP_Msk              (0x1UL << ETH_MACDR_TFCSTS_GENERATEPCP_Pos) /*!< 0x00040000 */
+#define ETH_MACDR_TFCSTS_GENERATEPCP                  ETH_MACDR_TFCSTS_GENERATEPCP_Msk /* Generating and transmitting a Pause control packet */
+#define ETH_MACDR_TFCSTS_TRASFERIP_Pos                (17U)
+#define ETH_MACDR_TFCSTS_TRASFERIP_Msk                (0x3UL << ETH_MACDR_TFCSTS_TRASFERIP_Pos) /*!< 0x00060000 */
+#define ETH_MACDR_TFCSTS_TRASFERIP                    ETH_MACDR_TFCSTS_TRASFERIP_Msk /* Transferring input packet for transmission */
+#define ETH_MACDR_TPESTS_Pos                          (16U)
+#define ETH_MACDR_TPESTS_Msk                          (0x1UL << ETH_MACDR_TPESTS_Pos) /*!< 0x00010000 */
+#define ETH_MACDR_TPESTS                              ETH_MACDR_TPESTS_Msk     /* MAC Receive Packet Controller FIFO Status */
+#define ETH_MACDR_RFCFCSTS_Pos                        (1U)
+#define ETH_MACDR_RFCFCSTS_Msk                        (0x3UL << ETH_MACDR_RFCFCSTS_Pos) /*!< 0x00000006 */
+#define ETH_MACDR_RFCFCSTS                            ETH_MACDR_RFCFCSTS_Msk   /* MAC MII Transmit Protocol Engine Status */
+#define ETH_MACDR_RPESTS_Pos                          (0U)
+#define ETH_MACDR_RPESTS_Msk                          (0x1UL << ETH_MACDR_RPESTS_Pos) /*!< 0x00000001 */
+#define ETH_MACDR_RPESTS                              ETH_MACDR_RPESTS_Msk     /* MAC MII Receive Protocol Engine Status */
+
+/* Bit definition for Ethernet MAC HW Feature0 Register */
+#define ETH_MACHWF0R_ACTPHYSEL_Pos                    (28U)
+#define ETH_MACHWF0R_ACTPHYSEL_Msk                    (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
+#define ETH_MACHWF0R_ACTPHYSEL                        ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
+#define ETH_MACHWF0R_ACTPHYSEL_MII                    ((uint32_t)0x00000000)   /* MII */
+#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos               (30U)
+#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk               (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
+#define ETH_MACHWF0R_ACTPHYSEL_RMII                   ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
+#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos             (28U)
+#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk             (0x7UL << ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos) /*!< 0x70000000 */
+#define ETH_MACHWF0R_ACTPHYSEL_REVMII                 ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk /* RevMII */
+#define ETH_MACHWF0R_SAVLANINS_Pos                    (27U)
+#define ETH_MACHWF0R_SAVLANINS_Msk                    (0x1UL << ETH_MACHWF0R_SAVLANINS_Pos) /*!< 0x08000000 */
+#define ETH_MACHWF0R_SAVLANINS                        ETH_MACHWF0R_SAVLANINS_Msk /* Source Address or VLAN Insertion Enable */
+#define ETH_MACHWF0R_TSSTSSEL_Pos                     (25U)
+#define ETH_MACHWF0R_TSSTSSEL_Msk                     (0x3UL << ETH_MACHWF0R_TSSTSSEL_Pos) /*!< 0x06000000 */
+#define ETH_MACHWF0R_TSSTSSEL                         ETH_MACHWF0R_TSSTSSEL_Msk /* Timestamp System Time Source */
+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos            (25U)
+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos) /*!< 0x02000000 */
+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL                ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk /* Timestamp System Time Source: Internal */
+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos            (26U)
+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos) /*!< 0x04000000 */
+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL                ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk /* Timestamp System Time Source: External */
+#define ETH_MACHWF0R_TSSTSSEL_BOTH_Pos                (25U)
+#define ETH_MACHWF0R_TSSTSSEL_BOTH_Msk                (0x3UL << ETH_MACHWF0R_TSSTSSEL_BOTH_Pos) /*!< 0x06000000 */
+#define ETH_MACHWF0R_TSSTSSEL_BOTH                    ETH_MACHWF0R_TSSTSSEL_BOTH_Msk /* Timestamp System Time Source: Internal & External */
+#define ETH_MACHWF0R_MACADR64SEL_Pos                  (24U)
+#define ETH_MACHWF0R_MACADR64SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR64SEL_Pos) /*!< 0x01000000 */
+#define ETH_MACHWF0R_MACADR64SEL                      ETH_MACHWF0R_MACADR64SEL_Msk /* MAC Addresses 64-127 Selected */
+#define ETH_MACHWF0R_MACADR32SEL_Pos                  (23U)
+#define ETH_MACHWF0R_MACADR32SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR32SEL_Pos) /*!< 0x00800000 */
+#define ETH_MACHWF0R_MACADR32SEL                      ETH_MACHWF0R_MACADR32SEL_Msk /* MAC Addresses 32-63 Selected */
+#define ETH_MACHWF0R_ADDMACADRSEL_Pos                 (18U)
+#define ETH_MACHWF0R_ADDMACADRSEL_Msk                 (0x1FUL << ETH_MACHWF0R_ADDMACADRSEL_Pos) /*!< 0x007C0000 */
+#define ETH_MACHWF0R_ADDMACADRSEL                     ETH_MACHWF0R_ADDMACADRSEL_Msk /* MAC Addresses 1- 31 Selected */
+#define ETH_MACHWF0R_RXCOESEL_Pos                     (16U)
+#define ETH_MACHWF0R_RXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_RXCOESEL_Pos) /*!< 0x00010000 */
+#define ETH_MACHWF0R_RXCOESEL                         ETH_MACHWF0R_RXCOESEL_Msk /* Receive Checksum Offload Enabled */
+#define ETH_MACHWF0R_TXCOESEL_Pos                     (14U)
+#define ETH_MACHWF0R_TXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_TXCOESEL_Pos) /*!< 0x00004000 */
+#define ETH_MACHWF0R_TXCOESEL                         ETH_MACHWF0R_TXCOESEL_Msk /* Transmit Checksum Offload Enabled */
+#define ETH_MACHWF0R_EEESEL_Pos                       (13U)
+#define ETH_MACHWF0R_EEESEL_Msk                       (0x1UL << ETH_MACHWF0R_EEESEL_Pos) /*!< 0x00002000 */
+#define ETH_MACHWF0R_EEESEL                           ETH_MACHWF0R_EEESEL_Msk  /* Energy Efficient Ethernet Enabled */
+#define ETH_MACHWF0R_TSSEL_Pos                        (12U)
+#define ETH_MACHWF0R_TSSEL_Msk                        (0x1UL << ETH_MACHWF0R_TSSEL_Pos) /*!< 0x00001000 */
+#define ETH_MACHWF0R_TSSEL                            ETH_MACHWF0R_TSSEL_Msk   /* IEEE 1588-2008 Timestamp Enabled */
+#define ETH_MACHWF0R_ARPOFFSEL_Pos                    (9U)
+#define ETH_MACHWF0R_ARPOFFSEL_Msk                    (0x1UL << ETH_MACHWF0R_ARPOFFSEL_Pos) /*!< 0x00000200 */
+#define ETH_MACHWF0R_ARPOFFSEL                        ETH_MACHWF0R_ARPOFFSEL_Msk /* ARP Offload Enabled */
+#define ETH_MACHWF0R_MMCSEL_Pos                       (8U)
+#define ETH_MACHWF0R_MMCSEL_Msk                       (0x1UL << ETH_MACHWF0R_MMCSEL_Pos) /*!< 0x00000100 */
+#define ETH_MACHWF0R_MMCSEL                           ETH_MACHWF0R_MMCSEL_Msk  /* RMON Module Enable */
+#define ETH_MACHWF0R_MGKSEL_Pos                       (7U)
+#define ETH_MACHWF0R_MGKSEL_Msk                       (0x1UL << ETH_MACHWF0R_MGKSEL_Pos) /*!< 0x00000080 */
+#define ETH_MACHWF0R_MGKSEL                           ETH_MACHWF0R_MGKSEL_Msk  /* PMT Magic Packet Enable */
+#define ETH_MACHWF0R_RWKSEL_Pos                       (6U)
+#define ETH_MACHWF0R_RWKSEL_Msk                       (0x1UL << ETH_MACHWF0R_RWKSEL_Pos) /*!< 0x00000040 */
+#define ETH_MACHWF0R_RWKSEL                           ETH_MACHWF0R_RWKSEL_Msk  /* PMT Remote Wake-up Packet Enable */
+#define ETH_MACHWF0R_SMASEL_Pos                       (5U)
+#define ETH_MACHWF0R_SMASEL_Msk                       (0x1UL << ETH_MACHWF0R_SMASEL_Pos) /*!< 0x00000020 */
+#define ETH_MACHWF0R_SMASEL                           ETH_MACHWF0R_SMASEL_Msk  /* SMA (MDIO) Interface */
+#define ETH_MACHWF0R_VLHASH_Pos                       (4U)
+#define ETH_MACHWF0R_VLHASH_Msk                       (0x1UL << ETH_MACHWF0R_VLHASH_Pos) /*!< 0x00000010 */
+#define ETH_MACHWF0R_VLHASH                           ETH_MACHWF0R_VLHASH_Msk  /* VLAN Hash Filter Selected */
+#define ETH_MACHWF0R_PCSSEL_Pos                       (3U)
+#define ETH_MACHWF0R_PCSSEL_Msk                       (0x1UL << ETH_MACHWF0R_PCSSEL_Pos) /*!< 0x00000008 */
+#define ETH_MACHWF0R_PCSSEL                           ETH_MACHWF0R_PCSSEL_Msk  /* PCS Registers (TBI, SGMII, or RTBI PHY interface) */
+#define ETH_MACHWF0R_HDSEL_Pos                        (2U)
+#define ETH_MACHWF0R_HDSEL_Msk                        (0x1UL << ETH_MACHWF0R_HDSEL_Pos) /*!< 0x00000004 */
+#define ETH_MACHWF0R_HDSEL                            ETH_MACHWF0R_HDSEL_Msk   /* Half-duplex Support */
+#define ETH_MACHWF0R_GMIISEL_Pos                      (1U)
+#define ETH_MACHWF0R_GMIISEL_Msk                      (0x1UL << ETH_MACHWF0R_GMIISEL_Pos) /*!< 0x00000002 */
+#define ETH_MACHWF0R_GMIISEL                          ETH_MACHWF0R_GMIISEL_Msk /* 1000 Mbps Support */
+#define ETH_MACHWF0R_MIISEL_Pos                       (0U)
+#define ETH_MACHWF0R_MIISEL_Msk                       (0x1UL << ETH_MACHWF0R_MIISEL_Pos) /*!< 0x00000001 */
+#define ETH_MACHWF0R_MIISEL                           ETH_MACHWF0R_MIISEL_Msk  /* 10 or 100 Mbps Support */
+
+/* Bit definition for Ethernet MAC HW Feature1 Register */
+#define ETH_MACHWF1R_L3L4FNUM_Pos                     (27U)
+#define ETH_MACHWF1R_L3L4FNUM_Msk                     (0xFUL << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x78000000 */
+#define ETH_MACHWF1R_L3L4FNUM                         ETH_MACHWF1R_L3L4FNUM_Msk /* Total number of L3 or L4 Filters */
+#define ETH_MACHWF1R_HASHTBLSZ_Pos                    (24U)
+#define ETH_MACHWF1R_HASHTBLSZ_Msk                    (0x3UL << ETH_MACHWF1R_HASHTBLSZ_Pos) /*!< 0x03000000 */
+#define ETH_MACHWF1R_HASHTBLSZ                        ETH_MACHWF1R_HASHTBLSZ_Msk /* Hash Table Size */
+#define ETH_MACHWF1R_AVSEL_Pos                        (20U)
+#define ETH_MACHWF1R_AVSEL_Msk                        (0x1UL << ETH_MACHWF1R_AVSEL_Pos) /*!< 0x00100000 */
+#define ETH_MACHWF1R_AVSEL                            ETH_MACHWF1R_AVSEL_Msk   /* AV Feature Enabled */
+#define ETH_MACHWF1R_DBGMEMA_Pos                      (19U)
+#define ETH_MACHWF1R_DBGMEMA_Msk                      (0x1UL << ETH_MACHWF1R_DBGMEMA_Pos) /*!< 0x00080000 */
+#define ETH_MACHWF1R_DBGMEMA                          ETH_MACHWF1R_DBGMEMA_Msk /* Debug Memory Interface Enabled */
+#define ETH_MACHWF1R_TSOEN_Pos                        (18U)
+#define ETH_MACHWF1R_TSOEN_Msk                        (0x1UL << ETH_MACHWF1R_TSOEN_Pos) /*!< 0x00040000 */
+#define ETH_MACHWF1R_TSOEN                            ETH_MACHWF1R_TSOEN_Msk   /* TCP Segmentation Offload Enable */
+#define ETH_MACHWF1R_SPHEN_Pos                        (17U)
+#define ETH_MACHWF1R_SPHEN_Msk                        (0x1UL << ETH_MACHWF1R_SPHEN_Pos) /*!< 0x00020000 */
+#define ETH_MACHWF1R_SPHEN                            ETH_MACHWF1R_SPHEN_Msk   /* Split Header Feature Enable */
+#define ETH_MACHWF1R_DCBEN_Pos                        (16U)
+#define ETH_MACHWF1R_DCBEN_Msk                        (0x1UL << ETH_MACHWF1R_DCBEN_Pos) /*!< 0x00010000 */
+#define ETH_MACHWF1R_DCBEN                            ETH_MACHWF1R_DCBEN_Msk   /* DCB Feature Enable */
+#define ETH_MACHWF1R_ADDR64_Pos                       (14U)
+#define ETH_MACHWF1R_ADDR64_Msk                       (0x3UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x0000C000 */
+#define ETH_MACHWF1R_ADDR64                           ETH_MACHWF1R_ADDR64_Msk  /* Address Width */
+#define ETH_MACHWF1R_ADDR64_32                        (0x0UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00000000 */
+#define ETH_MACHWF1R_ADDR64_40                        (0x1UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00004000 */
+#define ETH_MACHWF1R_ADDR64_48                        (0x2UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00008000 */
+#define ETH_MACHWF1R_ADVTHWORD_Pos                    (13U)
+#define ETH_MACHWF1R_ADVTHWORD_Msk                    (0x1UL << ETH_MACHWF1R_ADVTHWORD_Pos) /*!< 0x00002000 */
+#define ETH_MACHWF1R_ADVTHWORD                        ETH_MACHWF1R_ADVTHWORD_Msk /* IEEE 1588 High Word Register Enable */
+#define ETH_MACHWF1R_PTOEN_Pos                        (12U)
+#define ETH_MACHWF1R_PTOEN_Msk                        (0x1UL << ETH_MACHWF1R_PTOEN_Pos) /*!< 0x00001000 */
+#define ETH_MACHWF1R_PTOEN                            ETH_MACHWF1R_PTOEN_Msk   /* PTP Offload Enable */
+#define ETH_MACHWF1R_OSTEN_Pos                        (11U)
+#define ETH_MACHWF1R_OSTEN_Msk                        (0x1UL << ETH_MACHWF1R_OSTEN_Pos) /*!< 0x00000800 */
+#define ETH_MACHWF1R_OSTEN                            ETH_MACHWF1R_OSTEN_Msk   /* One-Step Timestamping Enable */
+#define ETH_MACHWF1R_TXFIFOSIZE_Pos                   (6U)
+#define ETH_MACHWF1R_TXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x000007C0 */
+#define ETH_MACHWF1R_TXFIFOSIZE                       ETH_MACHWF1R_TXFIFOSIZE_Msk /* MTL Transmit FIFO Size */
+#define ETH_MACHWF1R_RXFIFOSIZE_Pos                   (0U)
+#define ETH_MACHWF1R_RXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x0000001F */
+#define ETH_MACHWF1R_RXFIFOSIZE                       ETH_MACHWF1R_RXFIFOSIZE_Msk /* MTL Receive FIFO Size */
+
+/* Bit definition for Ethernet MAC HW Feature2 Register */
+#define ETH_MACHWF2R_AUXSNAPNUM_Pos                   (28U)
+#define ETH_MACHWF2R_AUXSNAPNUM_Msk                   (0x7UL << ETH_MACHWF2R_AUXSNAPNUM_Pos) /*!< 0x70000000 */
+#define ETH_MACHWF2R_AUXSNAPNUM                       ETH_MACHWF2R_AUXSNAPNUM_Msk /* Number of Auxiliary Snapshot Inputs */
+#define ETH_MACHWF2R_PPSOUTNUM_Pos                    (24U)
+#define ETH_MACHWF2R_PPSOUTNUM_Msk                    (0x7UL << ETH_MACHWF2R_PPSOUTNUM_Pos) /*!< 0x07000000 */
+#define ETH_MACHWF2R_PPSOUTNUM                        ETH_MACHWF2R_PPSOUTNUM_Msk /*  Number of PPS Outputs */
+#define ETH_MACHWF2R_TXCHCNT_Pos                      (18U)
+#define ETH_MACHWF2R_TXCHCNT_Msk                      (0xFUL << ETH_MACHWF2R_TXCHCNT_Pos) /*!< 0x003C0000 */
+#define ETH_MACHWF2R_TXCHCNT                          ETH_MACHWF2R_TXCHCNT_Msk /* Number of DMA Transmit Channels */
+#define ETH_MACHWF2R_RXCHCNT_Pos                      (13U)
+#define ETH_MACHWF2R_RXCHCNT_Msk                      (0x7UL << ETH_MACHWF2R_RXCHCNT_Pos) /*!< 0x0000E000 */
+#define ETH_MACHWF2R_RXCHCNT                          ETH_MACHWF2R_RXCHCNT_Msk /* Number of DMA Receive Channels */
+#define ETH_MACHWF2R_TXQCNT_Pos                       (6U)
+#define ETH_MACHWF2R_TXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_TXQCNT_Pos) /*!< 0x000003C0 */
+#define ETH_MACHWF2R_TXQCNT                           ETH_MACHWF2R_TXQCNT_Msk  /* Number of MTL Transmit Queues */
+#define ETH_MACHWF2R_RXQCNT_Pos                       (0U)
+#define ETH_MACHWF2R_RXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_RXQCNT_Pos) /*!< 0x0000000F */
+#define ETH_MACHWF2R_RXQCNT                           ETH_MACHWF2R_RXQCNT_Msk  /* Number of MTL Receive Queues */
+
+/* Bit definition for Ethernet MAC MDIO Address Register */
+#define ETH_MACMDIOAR_PSE_Pos                         (27U)
+#define ETH_MACMDIOAR_PSE_Msk                         (0x1UL << ETH_MACMDIOAR_PSE_Pos) /*!< 0x08000000 */
+#define ETH_MACMDIOAR_PSE                             ETH_MACMDIOAR_PSE_Msk    /* Preamble Suppression Enable */
+#define ETH_MACMDIOAR_BTB_Pos                         (26U)
+#define ETH_MACMDIOAR_BTB_Msk                         (0x1UL << ETH_MACMDIOAR_BTB_Pos) /*!< 0x04000000 */
+#define ETH_MACMDIOAR_BTB                             ETH_MACMDIOAR_BTB_Msk    /* Back to Back transactions */
+#define ETH_MACMDIOAR_PA_Pos                          (21U)
+#define ETH_MACMDIOAR_PA_Msk                          (0x1FUL << ETH_MACMDIOAR_PA_Pos) /*!< 0x03E00000 */
+#define ETH_MACMDIOAR_PA                              ETH_MACMDIOAR_PA_Msk     /* Physical Layer Address */
+#define ETH_MACMDIOAR_RDA_Pos                         (16U)
+#define ETH_MACMDIOAR_RDA_Msk                         (0x1FUL << ETH_MACMDIOAR_RDA_Pos) /*!< 0x001F0000 */
+#define ETH_MACMDIOAR_RDA                             ETH_MACMDIOAR_RDA_Msk    /* Register/Device Address */
+#define ETH_MACMDIOAR_NTC_Pos                         (12U)
+#define ETH_MACMDIOAR_NTC_Msk                         (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */
+#define ETH_MACMDIOAR_NTC                             ETH_MACMDIOAR_NTC_Msk    /* Number of Trailing Clocks */
+#define ETH_MACMDIOAR_CR_Pos                          (8U)
+#define ETH_MACMDIOAR_CR_Msk                          (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
+#define ETH_MACMDIOAR_CR                              ETH_MACMDIOAR_CR_Msk     /* CSR Clock Range */
+#define ETH_MACMDIOAR_CR_DIV42                        ((uint32_t)0x00000000)   /* CSR clock/42 */
+#define ETH_MACMDIOAR_CR_DIV62_Pos                    (8U)
+#define ETH_MACMDIOAR_CR_DIV62_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
+#define ETH_MACMDIOAR_CR_DIV62                        ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
+#define ETH_MACMDIOAR_CR_DIV16_Pos                    (9U)
+#define ETH_MACMDIOAR_CR_DIV16_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV16_Pos) /*!< 0x00000200 */
+#define ETH_MACMDIOAR_CR_DIV16                        ETH_MACMDIOAR_CR_DIV16_Msk /* CSR clock/16 */
+#define ETH_MACMDIOAR_CR_DIV26_Pos                    (8U)
+#define ETH_MACMDIOAR_CR_DIV26_Msk                    (0x3UL << ETH_MACMDIOAR_CR_DIV26_Pos) /*!< 0x00000300 */
+#define ETH_MACMDIOAR_CR_DIV26                        ETH_MACMDIOAR_CR_DIV26_Msk /* CSR clock/26 */
+#define ETH_MACMDIOAR_CR_DIV102_Pos                   (10U)
+#define ETH_MACMDIOAR_CR_DIV102_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV102_Pos) /*!< 0x00000400 */
+#define ETH_MACMDIOAR_CR_DIV102                       ETH_MACMDIOAR_CR_DIV102_Msk /* CSR clock/102 */
+#define ETH_MACMDIOAR_CR_DIV124_Pos                   (8U)
+#define ETH_MACMDIOAR_CR_DIV124_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV124_Pos) /*!< 0x00000500 */
+#define ETH_MACMDIOAR_CR_DIV124                       ETH_MACMDIOAR_CR_DIV124_Msk /* CSR clock/124 */
+#define ETH_MACMDIOAR_CR_DIV4AR_Pos                   (11U)
+#define ETH_MACMDIOAR_CR_DIV4AR_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV4AR_Pos) /*!< 0x00000800 */
+#define ETH_MACMDIOAR_CR_DIV4AR                       ETH_MACMDIOAR_CR_DIV4AR_Msk /* CSR clock/4: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV6AR_Pos                   (8U)
+#define ETH_MACMDIOAR_CR_DIV6AR_Msk                   (0x9UL << ETH_MACMDIOAR_CR_DIV6AR_Pos) /*!< 0x00000900 */
+#define ETH_MACMDIOAR_CR_DIV6AR                       ETH_MACMDIOAR_CR_DIV6AR_Msk /* CSR clock/6: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV8AR_Pos                   (9U)
+#define ETH_MACMDIOAR_CR_DIV8AR_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV8AR_Pos) /*!< 0x00000A00 */
+#define ETH_MACMDIOAR_CR_DIV8AR                       ETH_MACMDIOAR_CR_DIV8AR_Msk /* CSR clock/8: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV10AR_Pos                  (8U)
+#define ETH_MACMDIOAR_CR_DIV10AR_Msk                  (0xBUL << ETH_MACMDIOAR_CR_DIV10AR_Pos) /*!< 0x00000B00 */
+#define ETH_MACMDIOAR_CR_DIV10AR                      ETH_MACMDIOAR_CR_DIV10AR_Msk /* CSR clock/10: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV12AR_Pos                  (10U)
+#define ETH_MACMDIOAR_CR_DIV12AR_Msk                  (0x3UL << ETH_MACMDIOAR_CR_DIV12AR_Pos) /*!< 0x00000C00 */
+#define ETH_MACMDIOAR_CR_DIV12AR                      ETH_MACMDIOAR_CR_DIV12AR_Msk /* CSR clock/12: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV14AR_Pos                  (8U)
+#define ETH_MACMDIOAR_CR_DIV14AR_Msk                  (0xDUL << ETH_MACMDIOAR_CR_DIV14AR_Pos) /*!< 0x00000D00 */
+#define ETH_MACMDIOAR_CR_DIV14AR                      ETH_MACMDIOAR_CR_DIV14AR_Msk /* CSR clock/14: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV16AR_Pos                  (9U)
+#define ETH_MACMDIOAR_CR_DIV16AR_Msk                  (0x7UL << ETH_MACMDIOAR_CR_DIV16AR_Pos) /*!< 0x00000E00 */
+#define ETH_MACMDIOAR_CR_DIV16AR                      ETH_MACMDIOAR_CR_DIV16AR_Msk /* CSR clock/16: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV18AR_Pos                  (8U)
+#define ETH_MACMDIOAR_CR_DIV18AR_Msk                  (0xFUL << ETH_MACMDIOAR_CR_DIV18AR_Pos) /*!< 0x00000F00 */
+#define ETH_MACMDIOAR_CR_DIV18AR                      ETH_MACMDIOAR_CR_DIV18AR_Msk /* CSR clock/18: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_SKAP_Pos                        (4U)
+#define ETH_MACMDIOAR_SKAP_Msk                        (0x1UL << ETH_MACMDIOAR_SKAP_Pos) /*!< 0x00000010 */
+#define ETH_MACMDIOAR_SKAP                            ETH_MACMDIOAR_SKAP_Msk   /* Skip Address Packet */
+#define ETH_MACMDIOAR_MOC_Pos                         (2U)
+#define ETH_MACMDIOAR_MOC_Msk                         (0x3UL << ETH_MACMDIOAR_MOC_Pos) /*!< 0x0000000C */
+#define ETH_MACMDIOAR_MOC                             ETH_MACMDIOAR_MOC_Msk    /* MII Operation Command */
+#define ETH_MACMDIOAR_MOC_WR_Pos                      (2U)
+#define ETH_MACMDIOAR_MOC_WR_Msk                      (0x1UL << ETH_MACMDIOAR_MOC_WR_Pos) /*!< 0x00000004 */
+#define ETH_MACMDIOAR_MOC_WR                          ETH_MACMDIOAR_MOC_WR_Msk /* Write */
+#define ETH_MACMDIOAR_MOC_PRDIA_Pos                   (3U)
+#define ETH_MACMDIOAR_MOC_PRDIA_Msk                   (0x1UL << ETH_MACMDIOAR_MOC_PRDIA_Pos) /*!< 0x00000008 */
+#define ETH_MACMDIOAR_MOC_PRDIA                       ETH_MACMDIOAR_MOC_PRDIA_Msk /* Post Read Increment Address for Clause 45 PHY */
+#define ETH_MACMDIOAR_MOC_RD_Pos                      (2U)
+#define ETH_MACMDIOAR_MOC_RD_Msk                      (0x3UL << ETH_MACMDIOAR_MOC_RD_Pos) /*!< 0x0000000C */
+#define ETH_MACMDIOAR_MOC_RD                          ETH_MACMDIOAR_MOC_RD_Msk /* Read */
+#define ETH_MACMDIOAR_C45E_Pos                        (1U)
+#define ETH_MACMDIOAR_C45E_Msk                        (0x1UL << ETH_MACMDIOAR_C45E_Pos) /*!< 0x00000002 */
+#define ETH_MACMDIOAR_C45E                            ETH_MACMDIOAR_C45E_Msk   /* Clause 45 PHY Enable */
+#define ETH_MACMDIOAR_MB_Pos                          (0U)
+#define ETH_MACMDIOAR_MB_Msk                          (0x1UL << ETH_MACMDIOAR_MB_Pos) /*!< 0x00000001 */
+#define ETH_MACMDIOAR_MB                              ETH_MACMDIOAR_MB_Msk     /* MII Busy */
+
+/* Bit definition for Ethernet MAC MDIO Data Register */
+#define ETH_MACMDIODR_RA_Pos                          (16U)
+#define ETH_MACMDIODR_RA_Msk                          (0xFFFFUL << ETH_MACMDIODR_RA_Pos) /*!< 0xFFFF0000 */
+#define ETH_MACMDIODR_RA                              ETH_MACMDIODR_RA_Msk     /* Register Address */
+#define ETH_MACMDIODR_MD_Pos                          (0U)
+#define ETH_MACMDIODR_MD_Msk                          (0xFFFFUL << ETH_MACMDIODR_MD_Pos) /*!< 0x0000FFFF */
+#define ETH_MACMDIODR_MD                              ETH_MACMDIODR_MD_Msk     /* MII Data */
+
+/* Bit definition for Ethernet ARP Address Register */
+#define ETH_MACARPAR_ARPPA_Pos                         (0U)
+#define ETH_MACARPAR_ARPPA_Msk                         (0xFFFFFFFFUL << ETH_MACARPAR_ARPPA_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACARPAR_ARPPA                             ETH_MACARPAR_ARPPA_Msk     /* ARP Protocol Address */
+
+/* Bit definition for Ethernet MAC Address 0 High Register */
+#define ETH_MACA0HR_AE_Pos                            (31U)
+#define ETH_MACA0HR_AE_Msk                            (0x1UL << ETH_MACA0HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA0HR_AE                                ETH_MACA0HR_AE_Msk /* Address Enable*/
+#define ETH_MACA0HR_ADDRHI_Pos                        (0U)
+#define ETH_MACA0HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA0HR_ADDRHI                            ETH_MACA0HR_ADDRHI_Msk   /* MAC Address 0*/
+
+/* Bit definition for Ethernet MAC Address 0 Low Register */
+#define ETH_MACA0LR_ADDRLO_Pos                        (0U)
+#define ETH_MACA0LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA0LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA0LR_ADDRLO                            ETH_MACA0LR_ADDRLO_Msk   /* MAC Address 0*/
+
+/* Bit definition for Ethernet MAC Address 1 High Register */
+#define ETH_MACA1HR_AE_Pos                            (31U)
+#define ETH_MACA1HR_AE_Msk                            (0x1UL << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA1HR_AE                                ETH_MACA1HR_AE_Msk /* Address Enable*/
+#define ETH_MACA1HR_SA_Pos                            (30U)
+#define ETH_MACA1HR_SA_Msk                            (0x1UL << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA1HR_SA                                ETH_MACA1HR_SA_Msk /* Source Address */
+#define ETH_MACA1HR_MBC_Pos                           (24U)
+#define ETH_MACA1HR_MBC_Msk                           (0x3FUL << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA1HR_MBC                               ETH_MACA1HR_MBC_Msk /* Mask Byte Control */
+#define ETH_MACA1HR_ADDRHI_Pos                        (0U)
+#define ETH_MACA1HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA1HR_ADDRHI                            ETH_MACA1HR_ADDRHI_Msk   /* MAC Address 1*/
+
+/* Bit definition for Ethernet MAC Address 1 Low Register */
+#define ETH_MACA1LR_ADDRLO_Pos                        (0U)
+#define ETH_MACA1LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA1LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA1LR_ADDRLO                            ETH_MACA1LR_ADDRLO_Msk   /* MAC Address 1*/
+
+/* Bit definition for Ethernet MAC Address 2 High Register */
+#define ETH_MACA2HR_AE_Pos                            (31U)
+#define ETH_MACA2HR_AE_Msk                            (0x1UL << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA2HR_AE                                ETH_MACA2HR_AE_Msk /* Address Enable*/
+#define ETH_MACA2HR_SA_Pos                            (30U)
+#define ETH_MACA2HR_SA_Msk                            (0x1UL << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA2HR_SA                                ETH_MACA2HR_SA_Msk /* Source Address */
+#define ETH_MACA2HR_MBC_Pos                           (24U)
+#define ETH_MACA2HR_MBC_Msk                           (0x3FUL << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA2HR_MBC                               ETH_MACA2HR_MBC_Msk /* Mask Byte Control */
+#define ETH_MACA2HR_ADDRHI_Pos                        (0U)
+#define ETH_MACA2HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA2HR_ADDRHI                            ETH_MACA2HR_ADDRHI_Msk   /* MAC Address 1*/
+
+/* Bit definition for Ethernet MAC Address 2 Low Register */
+#define ETH_MACA2LR_ADDRLO_Pos                        (0U)
+#define ETH_MACA2LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA2LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA2LR_ADDRLO                            ETH_MACA2LR_ADDRLO_Msk   /* MAC Address 2*/
+
+/* Bit definition for Ethernet MAC Address 3 High Register */
+#define ETH_MACA3HR_AE_Pos                            (31U)
+#define ETH_MACA3HR_AE_Msk                            (0x1UL << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA3HR_AE                                ETH_MACA3HR_AE_Msk /* Address Enable*/
+#define ETH_MACA3HR_SA_Pos                            (30U)
+#define ETH_MACA3HR_SA_Msk                            (0x1UL << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA3HR_SA                                ETH_MACA3HR_SA_Msk /* Source Address */
+#define ETH_MACA3HR_MBC_Pos                           (24U)
+#define ETH_MACA3HR_MBC_Msk                           (0x3FUL << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA3HR_MBC                               ETH_MACA3HR_MBC_Msk /* Mask Byte Control */
+#define ETH_MACA3HR_ADDRHI_Pos                        (0U)
+#define ETH_MACA3HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA3HR_ADDRHI                            ETH_MACA3HR_ADDRHI_Msk   /* MAC Address 1*/
+
+/* Bit definition for Ethernet MAC Address 3 Low Register */
+#define ETH_MACA3LR_ADDRLO_Pos                        (0U)
+#define ETH_MACA3LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA3LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA3LR_ADDRLO                            ETH_MACA3LR_ADDRLO_Msk   /* MAC Address 3*/
+
+/* Bit definition for Ethernet MAC Address High Register */
+#define ETH_MACAHR_AE_Pos                             (31U)
+#define ETH_MACAHR_AE_Msk                             (0x1UL << ETH_MACAHR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACAHR_AE                                 ETH_MACAHR_AE_Msk        /* Address enable */
+#define ETH_MACAHR_SA_Pos                             (30U)
+#define ETH_MACAHR_SA_Msk                             (0x1UL << ETH_MACAHR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACAHR_SA                                 ETH_MACAHR_SA_Msk        /* Source address */
+#define ETH_MACAHR_MBC_Pos                            (24U)
+#define ETH_MACAHR_MBC_Msk                            (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACAHR_MBC                                ETH_MACAHR_MBC_Msk       /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+#define ETH_MACAHR_MBC_HBITS15_8                      ((uint32_t)0x20000000)   /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACAHR_MBC_HBITS7_0                       ((uint32_t)0x10000000)   /* Mask MAC Address high reg bits [7:0] */
+#define ETH_MACAHR_MBC_LBITS31_24                     ((uint32_t)0x08000000)   /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACAHR_MBC_LBITS23_16                     ((uint32_t)0x04000000)   /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACAHR_MBC_LBITS15_8                      ((uint32_t)0x02000000)   /* Mask MAC Address low reg bits [15:8] */
+#define ETH_MACAHR_MBC_LBITS7_0                       ((uint32_t)0x01000000)   /* Mask MAC Address low reg bits [7:0] */
+#define ETH_MACAHR_MACAH_Pos                          (0U)
+#define ETH_MACAHR_MACAH_Msk                          (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */
+#define ETH_MACAHR_MACAH                              ETH_MACAHR_MACAH_Msk     /* MAC address high */
+
+/* Bit definition for Ethernet MAC Address Low Register */
+#define ETH_MACALR_MACAL_Pos                          (0U)
+#define ETH_MACALR_MACAL_Msk                          (0xFFFFFFFFUL << ETH_MACALR_MACAL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACALR_MACAL                              ETH_MACALR_MACAL_Msk     /* MAC address low */
+
+/* Bit definition for Ethernet MMC Control Register */
+#define ETH_MMCCR_UCDBC_Pos                           (8U)
+#define ETH_MMCCR_UCDBC_Msk                           (0x1UL << ETH_MMCCR_UCDBC_Pos) /*!< 0x00000100 */
+#define ETH_MMCCR_UCDBC                               ETH_MMCCR_UCDBC_Msk  /* Update MMC Counters for Dropped Broadcast Packets */
+#define ETH_MMCCR_CNTPRSTLVL_Pos                      (5U)
+#define ETH_MMCCR_CNTPRSTLVL_Msk                      (0x1UL << ETH_MMCCR_CNTPRSTLVL_Pos) /*!< 0x00000020 */
+#define ETH_MMCCR_CNTPRSTLVL                          ETH_MMCCR_CNTPRSTLVL_Msk  /* Full-Half Preset */
+#define ETH_MMCCR_CNTPRST_Pos                         (4U)
+#define ETH_MMCCR_CNTPRST_Msk                         (0x1UL << ETH_MMCCR_CNTPRST_Pos) /*!< 0x00000010 */
+#define ETH_MMCCR_CNTPRST                             ETH_MMCCR_CNTPRST_Msk  /* Counters Reset */
+#define ETH_MMCCR_CNTFREEZ_Pos                        (3U)
+#define ETH_MMCCR_CNTFREEZ_Msk                        (0x1UL << ETH_MMCCR_CNTFREEZ_Pos) /*!< 0x00000008 */
+#define ETH_MMCCR_CNTFREEZ                            ETH_MMCCR_CNTFREEZ_Msk  /* MMC Counter Freeze */
+#define ETH_MMCCR_RSTONRD_Pos                         (2U)
+#define ETH_MMCCR_RSTONRD_Msk                         (0x1UL << ETH_MMCCR_RSTONRD_Pos) /*!< 0x00000004 */
+#define ETH_MMCCR_RSTONRD                             ETH_MMCCR_RSTONRD_Msk  /* Reset On Read */
+#define ETH_MMCCR_CNTSTOPRO_Pos                       (1U)
+#define ETH_MMCCR_CNTSTOPRO_Msk                       (0x1UL << ETH_MMCCR_CNTSTOPRO_Pos) /*!< 0x00000002 */
+#define ETH_MMCCR_CNTSTOPRO                           ETH_MMCCR_CNTSTOPRO_Msk  /* Counter Stop Rollover */
+#define ETH_MMCCR_CNTRST_Pos                          (0U)
+#define ETH_MMCCR_CNTRST_Msk                          (0x1UL << ETH_MMCCR_CNTRST_Pos) /*!< 0x00000001 */
+#define ETH_MMCCR_CNTRST                              ETH_MMCCR_CNTRST_Msk  /* Counters Reset */
+
+/* Bit definition for Ethernet MMC Rx Interrupt Register */
+#define ETH_MMCRIR_RXLPITRCIS_Pos                     (27U)
+#define ETH_MMCRIR_RXLPITRCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPITRCIS_Pos) /*!< 0x08000000 */
+#define ETH_MMCRIR_RXLPITRCIS                         ETH_MMCRIR_RXLPITRCIS_Msk  /* MMC Receive LPI transition counter interrupt status */
+#define ETH_MMCRIR_RXLPIUSCIS_Pos                     (26U)
+#define ETH_MMCRIR_RXLPIUSCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPIUSCIS_Pos) /*!< 0x04000000 */
+#define ETH_MMCRIR_RXLPIUSCIS                         ETH_MMCRIR_RXLPIUSCIS_Msk  /* MMC Receive LPI microsecond counter interrupt status */
+#define ETH_MMCRIR_RXUCGPIS_Pos                       (17U)
+#define ETH_MMCRIR_RXUCGPIS_Msk                       (0x1UL << ETH_MMCRIR_RXUCGPIS_Pos) /*!< 0x00020000 */
+#define ETH_MMCRIR_RXUCGPIS                           ETH_MMCRIR_RXUCGPIS_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Status */
+#define ETH_MMCRIR_RXALGNERPIS_Pos                    (6U)
+#define ETH_MMCRIR_RXALGNERPIS_Msk                    (0x1UL << ETH_MMCRIR_RXALGNERPIS_Pos) /*!< 0x00000040 */
+#define ETH_MMCRIR_RXALGNERPIS                        ETH_MMCRIR_RXALGNERPIS_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Status */
+#define ETH_MMCRIR_RXCRCERPIS_Pos                     (5U)
+#define ETH_MMCRIR_RXCRCERPIS_Msk                     (0x1UL << ETH_MMCRIR_RXCRCERPIS_Pos) /*!< 0x00000020 */
+#define ETH_MMCRIR_RXCRCERPIS                         ETH_MMCRIR_RXCRCERPIS_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Status */
+
+/* Bit definition for Ethernet MMC Tx Interrupt Register */
+#define ETH_MMCTIR_TXLPITRCIS_Pos                     (27U)
+#define ETH_MMCTIR_TXLPITRCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPITRCIS_Pos) /*!< 0x08000000 */
+#define ETH_MMCTIR_TXLPITRCIS                         ETH_MMCTIR_TXLPITRCIS_Msk  /* MMC Transmit LPI transition counter interrupt status */
+#define ETH_MMCTIR_TXLPIUSCIS_Pos                     (26U)
+#define ETH_MMCTIR_TXLPIUSCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPIUSCIS_Pos) /*!< 0x04000000 */
+#define ETH_MMCTIR_TXLPIUSCIS                         ETH_MMCTIR_TXLPIUSCIS_Msk  /* MMC Transmit LPI microsecond counter interrupt status */
+#define ETH_MMCTIR_TXGPKTIS_Pos                       (21U)
+#define ETH_MMCTIR_TXGPKTIS_Msk                       (0x1UL << ETH_MMCTIR_TXGPKTIS_Pos) /*!< 0x00200000 */
+#define ETH_MMCTIR_TXGPKTIS                           ETH_MMCTIR_TXGPKTIS_Msk  /* MMC Transmit Good Packet Counter Interrupt Status */
+#define ETH_MMCTIR_TXMCOLGPIS_Pos                     (15U)
+#define ETH_MMCTIR_TXMCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXMCOLGPIS_Pos) /*!< 0x00008000 */
+#define ETH_MMCTIR_TXMCOLGPIS                         ETH_MMCTIR_TXMCOLGPIS_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Status */
+#define ETH_MMCTIR_TXSCOLGPIS_Pos                     (14U)
+#define ETH_MMCTIR_TXSCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXSCOLGPIS_Pos) /*!< 0x00004000 */
+#define ETH_MMCTIR_TXSCOLGPIS                         ETH_MMCTIR_TXSCOLGPIS_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Status */
+
+/* Bit definition for Ethernet MMC Rx interrupt Mask register */
+#define ETH_MMCRIMR_RXLPITRCIM_Pos                    (27U)
+#define ETH_MMCRIMR_RXLPITRCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPITRCIM_Pos) /*!< 0x08000000 */
+#define ETH_MMCRIMR_RXLPITRCIM                        ETH_MMCRIMR_RXLPITRCIM_Msk  /* MMC Receive LPI transition counter interrupt Mask */
+#define ETH_MMCRIMR_RXLPIUSCIM_Pos                    (26U)
+#define ETH_MMCRIMR_RXLPIUSCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPIUSCIM_Pos) /*!< 0x04000000 */
+#define ETH_MMCRIMR_RXLPIUSCIM                        ETH_MMCRIMR_RXLPIUSCIM_Msk  /* MMC Receive LPI microsecond counter interrupt Mask */
+#define ETH_MMCRIMR_RXUCGPIM_Pos                      (17U)
+#define ETH_MMCRIMR_RXUCGPIM_Msk                      (0x1UL << ETH_MMCRIMR_RXUCGPIM_Pos) /*!< 0x00020000 */
+#define ETH_MMCRIMR_RXUCGPIM                          ETH_MMCRIMR_RXUCGPIM_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Mask */
+#define ETH_MMCRIMR_RXALGNERPIM_Pos                   (6U)
+#define ETH_MMCRIMR_RXALGNERPIM_Msk                   (0x1UL << ETH_MMCRIMR_RXALGNERPIM_Pos) /*!< 0x00000040 */
+#define ETH_MMCRIMR_RXALGNERPIM                       ETH_MMCRIMR_RXALGNERPIM_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Mask */
+#define ETH_MMCRIMR_RXCRCERPIM_Pos                    (5U)
+#define ETH_MMCRIMR_RXCRCERPIM_Msk                    (0x1UL << ETH_MMCRIMR_RXCRCERPIM_Pos) /*!< 0x00000020 */
+#define ETH_MMCRIMR_RXCRCERPIM                        ETH_MMCRIMR_RXCRCERPIM_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Mask */
+
+/* Bit definition for Ethernet MMC Tx Interrupt Mask Register */
+#define ETH_MMCTIMR_TXLPITRCIM_Pos                    (27U)
+#define ETH_MMCTIMR_TXLPITRCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */
+#define ETH_MMCTIMR_TXLPITRCIM                        ETH_MMCTIMR_TXLPITRCIM_Msk  /* MMC Transmit LPI transition counter interrupt Mask*/
+#define ETH_MMCTIMR_TXLPIUSCIM_Pos                    (26U)
+#define ETH_MMCTIMR_TXLPIUSCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPIUSCIM_Pos) /*!< 0x04000000 */
+#define ETH_MMCTIMR_TXLPIUSCIM                        ETH_MMCTIMR_TXLPIUSCIM_Msk  /* MMC Transmit LPI microsecond counter interrupt Mask*/
+#define ETH_MMCTIMR_TXGPKTIM_Pos                      (21U)
+#define ETH_MMCTIMR_TXGPKTIM_Msk                      (0x1UL << ETH_MMCTIMR_TXGPKTIM_Pos) /*!< 0x00200000 */
+#define ETH_MMCTIMR_TXGPKTIM                          ETH_MMCTIMR_TXGPKTIM_Msk  /* MMC Transmit Good Packet Counter Interrupt Mask*/
+#define ETH_MMCTIMR_TXMCOLGPIM_Pos                    (15U)
+#define ETH_MMCTIMR_TXMCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXMCOLGPIM_Pos) /*!< 0x00008000 */
+#define ETH_MMCTIMR_TXMCOLGPIM                        ETH_MMCTIMR_TXMCOLGPIM_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask */
+#define ETH_MMCTIMR_TXSCOLGPIM_Pos                    (14U)
+#define ETH_MMCTIMR_TXSCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXSCOLGPIM_Pos) /*!< 0x00004000 */
+#define ETH_MMCTIMR_TXSCOLGPIM                        ETH_MMCTIMR_TXSCOLGPIM_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Mask */
+
+/* Bit definition for Ethernet MMC Tx Single Collision Good Packets Register */
+#define ETH_MMCTSCGPR_TXSNGLCOLG_Pos                  (0U)
+#define ETH_MMCTSCGPR_TXSNGLCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTSCGPR_TXSNGLCOLG_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTSCGPR_TXSNGLCOLG                      ETH_MMCTSCGPR_TXSNGLCOLG_msk /* Tx Single Collision Good Packets */
+
+/* Bit definition for Ethernet MMC Tx Multiple Collision Good Packets Register */
+#define ETH_MMCTMCGPR_TXMULTCOLG_Pos                  (0U)
+#define ETH_MMCTMCGPR_TXMULTCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTMCGPR_TXMULTCOLG_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTMCGPR_TXMULTCOLG                      ETH_MMCTMCGPR_TXMULTCOLG_msk /* Tx Multiple Collision Good Packets */
+
+/* Bit definition for Ethernet MMC Tx Packet Count Good Register */
+#define ETH_MMCTPCGR_TXPKTG_Pos                       (0U)
+#define ETH_MMCTPCGR_TXPKTG_msk                       (0xFFFFFFFFUL <<  ETH_MMCTPCGR_TXPKTG_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTPCGR_TXPKTG                           ETH_MMCTPCGR_TXPKTG_msk /* Tx Packet Count Good */
+
+/* Bit definition for Ethernet MMC Rx CRC Error Packets Register */
+#define ETH_MMCRCRCEPR_RXCRCERR_Pos                   (0U)
+#define ETH_MMCRCRCEPR_RXCRCERR_msk                   (0xFFFFFFFFUL <<  ETH_MMCRCRCEPR_RXCRCERR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRCRCEPR_RXCRCERR                       ETH_MMCRCRCEPR_RXCRCERR_msk /* Rx CRC Error Packets */
+
+/* Bit definition for Ethernet MMC Rx alignment error packets register */
+#define ETH_MMCRAEPR_RXALGNERR_Pos                    (0U)
+#define ETH_MMCRAEPR_RXALGNERR_msk                    (0xFFFFFFFFUL <<  ETH_MMCRAEPR_RXALGNERR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRAEPR_RXALGNERR                        ETH_MMCRAEPR_RXALGNERR_msk /* Rx Alignment Error Packets */
+
+/* Bit definition for Ethernet MMC Rx Unicast Packets Good Register */
+#define ETH_MMCRUPGR_RXUCASTG_Pos                     (0U)
+#define ETH_MMCRUPGR_RXUCASTG_msk                     (0xFFFFFFFFUL <<  ETH_MMCRUPGR_RXUCASTG_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRUPGR_RXUCASTG                         ETH_MMCRUPGR_RXUCASTG_msk /* Rx Unicast Packets Good */
+
+/* Bit definition for Ethernet MMC Tx LPI Microsecond Timer Register */
+#define ETH_MMCTLPIMSTR_TXLPIUSC_Pos                  (0U)
+#define ETH_MMCTLPIMSTR_TXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCTLPIMSTR_TXLPIUSC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTLPIMSTR_TXLPIUSC                      ETH_MMCTLPIMSTR_TXLPIUSC_msk /* Tx LPI Microseconds Counter */
+
+/* Bit definition for Ethernet MMC Tx LPI Transition Counter Register */
+#define ETH_MMCTLPITCR_TXLPITRC_Pos                   (0U)
+#define ETH_MMCTLPITCR_TXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCTLPITCR_TXLPITRC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTLPITCR_TXLPITRC                       ETH_MMCTLPITCR_TXLPITRC_msk /* Tx LPI Transition counter */
+
+/* Bit definition for Ethernet MMC Rx LPI Microsecond Counter Register */
+#define ETH_MMCRLPIMSTR_RXLPIUSC_Pos                  (0U)
+#define ETH_MMCRLPIMSTR_RXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCRLPIMSTR_RXLPIUSC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRLPIMSTR_RXLPIUSC                      ETH_MMCRLPIMSTR_RXLPIUSC_msk /* Rx LPI Microseconds Counter */
+
+/* Bit definition for Ethernet MMC Rx LPI Transition Counter Register */
+#define ETH_MMCRLPITCR_RXLPITRC_Pos                   (0U)
+#define ETH_MMCRLPITCR_RXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCRLPITCR_RXLPITRC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRLPITCR_RXLPITRC                       ETH_MMCRLPITCR_RXLPITRC_msk /* Rx LPI Transition counter */
+
+/* Bit definition for Ethernet MAC L3 L4 Control Register */
+#define ETH_MACL3L4CR_L4DPIM_Pos                      (21U)
+#define ETH_MACL3L4CR_L4DPIM_Msk                      (0x1UL << ETH_MACL3L4CR_L4DPIM_Pos) /*!< 0x00200000 */
+#define ETH_MACL3L4CR_L4DPIM                          ETH_MACL3L4CR_L4DPIM_Msk /* Layer 4 Destination Port Inverse Match Enable */
+#define ETH_MACL3L4CR_L4DPM_Pos                       (20U)
+#define ETH_MACL3L4CR_L4DPM_Msk                       (0x1UL << ETH_MACL3L4CR_L4DPM_Pos) /*!< 0x00100000 */
+#define ETH_MACL3L4CR_L4DPM                           ETH_MACL3L4CR_L4DPM_Msk  /* Layer 4 Destination Port Match Enable */
+#define ETH_MACL3L4CR_L4SPIM_Pos                      (19U)
+#define ETH_MACL3L4CR_L4SPIM_Msk                      (0x1UL << ETH_MACL3L4CR_L4SPIM_Pos) /*!< 0x00080000 */
+#define ETH_MACL3L4CR_L4SPIM                          ETH_MACL3L4CR_L4SPIM_Msk /* Layer 4 Source Port Inverse Match Enable */
+#define ETH_MACL3L4CR_L4SPM_Pos                       (18U)
+#define ETH_MACL3L4CR_L4SPM_Msk                       (0x1UL << ETH_MACL3L4CR_L4SPM_Pos) /*!< 0x00040000 */
+#define ETH_MACL3L4CR_L4SPM                           ETH_MACL3L4CR_L4SPM_Msk  /* Layer 4 Source Port Match Enable */
+#define ETH_MACL3L4CR_L4PEN_Pos                       (16U)
+#define ETH_MACL3L4CR_L4PEN_Msk                       (0x1UL << ETH_MACL3L4CR_L4PEN_Pos) /*!< 0x00010000 */
+#define ETH_MACL3L4CR_L4PEN                           ETH_MACL3L4CR_L4PEN_Msk  /* Layer 4 Protocol Enable */
+#define ETH_MACL3L4CR_L3HDBM_Pos                      (11U)
+#define ETH_MACL3L4CR_L3HDBM_Msk                      (0x1FUL << ETH_MACL3L4CR_L3HDBM_Pos) /*!< 0x0000F800 */
+#define ETH_MACL3L4CR_L3HDBM                          ETH_MACL3L4CR_L3HDBM_Msk /* Layer 3 IP DA Higher Bits Match */
+#define ETH_MACL3L4CR_L3HSBM_Pos                      (6U)
+#define ETH_MACL3L4CR_L3HSBM_Msk                      (0x1FUL << ETH_MACL3L4CR_L3HSBM_Pos) /*!< 0x000007C0 */
+#define ETH_MACL3L4CR_L3HSBM                          ETH_MACL3L4CR_L3HSBM_Msk /* Layer 3 IP SA Higher Bits Match */
+#define ETH_MACL3L4CR_L3DAIM_Pos                      (5U)
+#define ETH_MACL3L4CR_L3DAIM_Msk                      (0x1UL << ETH_MACL3L4CR_L3DAIM_Pos) /*!< 0x00000020 */
+#define ETH_MACL3L4CR_L3DAIM                          ETH_MACL3L4CR_L3DAIM_Msk /* Layer 3 IP DA Inverse Match Enable */
+#define ETH_MACL3L4CR_L3DAM_Pos                       (4U)
+#define ETH_MACL3L4CR_L3DAM_Msk                       (0x1UL << ETH_MACL3L4CR_L3DAM_Pos) /*!< 0x00000010 */
+#define ETH_MACL3L4CR_L3DAM                           ETH_MACL3L4CR_L3DAM_Msk  /* Layer 3 IP DA Match Enable */
+#define ETH_MACL3L4CR_L3SAIM_Pos                      (3U)
+#define ETH_MACL3L4CR_L3SAIM_Msk                      (0x1UL << ETH_MACL3L4CR_L3SAIM_Pos) /*!< 0x00000008 */
+#define ETH_MACL3L4CR_L3SAIM                          ETH_MACL3L4CR_L3SAIM_Msk /* Layer 3 IP SA Inverse Match Enable */
+#define ETH_MACL3L4CR_L3SAM_Pos                       (2U)
+#define ETH_MACL3L4CR_L3SAM_Msk                       (0x1UL << ETH_MACL3L4CR_L3SAM_Pos) /*!< 0x00000004 */
+#define ETH_MACL3L4CR_L3SAM                           ETH_MACL3L4CR_L3SAM_Msk  /* Layer 3 IP SA Match Enable*/
+#define ETH_MACL3L4CR_L3PEN_Pos                       (0U)
+#define ETH_MACL3L4CR_L3PEN_Msk                       (0x1UL << ETH_MACL3L4CR_L3PEN_Pos) /*!< 0x00000001 */
+#define ETH_MACL3L4CR_L3PEN                           ETH_MACL3L4CR_L3PEN_Msk  /* Layer 3 Protocol Enable */
+
+/* Bit definition for Ethernet MAC L4 Address Register */
+#define ETH_MACL4AR_L4DP_Pos                          (16U)
+#define ETH_MACL4AR_L4DP_Msk                          (0xFFFFUL << ETH_MACL4AR_L4DP_Pos) /*!< 0xFFFF0000 */
+#define ETH_MACL4AR_L4DP                              ETH_MACL4AR_L4DP_Msk     /* Layer 4 Destination Port Number Field */
+#define ETH_MACL4AR_L4SP_Pos                          (0U)
+#define ETH_MACL4AR_L4SP_Msk                          (0xFFFFUL << ETH_MACL4AR_L4SP_Pos) /*!< 0x0000FFFF */
+#define ETH_MACL4AR_L4SP                              ETH_MACL4AR_L4SP_Msk     /* Layer 4 Source Port Number Field */
+
+/* Bit definition for Ethernet MAC L3 Address0 Register */
+#define ETH_MACL3A0R_L3A0_Pos                         (0U)
+#define ETH_MACL3A0R_L3A0_Msk                         (0xFFFFFFFFUL << ETH_MACL3A0R_L3A0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A0R_L3A0                             ETH_MACL3A0R_L3A0_Msk    /* Layer 3 Address 0 Field */
+
+/* Bit definition for Ethernet MAC L4 Address1 Register */
+#define ETH_MACL3A1R_L3A1_Pos                         (0U)
+#define ETH_MACL3A1R_L3A1_Msk                         (0xFFFFFFFFUL << ETH_MACL3A1R_L3A1_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A1R_L3A1                             ETH_MACL3A1R_L3A1_Msk    /* Layer 3 Address 1 Field */
+
+/* Bit definition for Ethernet MAC L4 Address2 Register */
+#define ETH_MACL3A2R_L3A2_Pos                         (0U)
+#define ETH_MACL3A2R_L3A2_Msk                         (0xFFFFFFFFUL << ETH_MACL3A2R_L3A2_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A2R_L3A2                             ETH_MACL3A2R_L3A2_Msk    /* Layer 3 Address 2 Field */
+
+/* Bit definition for Ethernet MAC L4 Address3 Register */
+#define ETH_MACL3A3R_L3A3_Pos                         (0U)
+#define ETH_MACL3A3R_L3A3_Msk                         (0xFFFFFFFFUL << ETH_MACL3A3R_L3A3_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A3R_L3A3                             ETH_MACL3A3R_L3A3_Msk    /* Layer 3 Address 3 Field */
+
+/* Bit definition for Ethernet MAC Timestamp Control Register */
+#define ETH_MACTSCR_TXTSSTSM_Pos                      (24U)
+#define ETH_MACTSCR_TXTSSTSM_Msk                      (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */
+#define ETH_MACTSCR_TXTSSTSM                          ETH_MACTSCR_TXTSSTSM_Msk  /* Transmit Timestamp Status Mode */
+#define ETH_MACTSCR_CSC_Pos                           (19U)
+#define ETH_MACTSCR_CSC_Msk                           (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */
+#define ETH_MACTSCR_CSC                               ETH_MACTSCR_CSC_Msk  /* Enable checksum correction during OST for PTP over UDP/IPv4 packets */
+#define ETH_MACTSCR_TSENMACADDR_Pos                   (18U)
+#define ETH_MACTSCR_TSENMACADDR_Msk                   (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */
+#define ETH_MACTSCR_TSENMACADDR                       ETH_MACTSCR_TSENMACADDR_Msk  /* Enable MAC Address for PTP Packet Filtering */
+#define ETH_MACTSCR_SNAPTYPSEL_Pos                    (16U)
+#define ETH_MACTSCR_SNAPTYPSEL_Msk                    (0x3UL << ETH_MACTSCR_SNAPTYPSEL_Pos) /*!< 0x00030000 */
+#define ETH_MACTSCR_SNAPTYPSEL                        ETH_MACTSCR_SNAPTYPSEL_Msk  /* Select PTP packets for Taking Snapshots */
+#define ETH_MACTSCR_TSMSTRENA_Pos                     (15U)
+#define ETH_MACTSCR_TSMSTRENA_Msk                     (0x1UL << ETH_MACTSCR_TSMSTRENA_Pos) /*!< 0x00008000 */
+#define ETH_MACTSCR_TSMSTRENA                         ETH_MACTSCR_TSMSTRENA_Msk  /* Enable Snapshot for Messages Relevant to Master */
+#define ETH_MACTSCR_TSEVNTENA_Pos                     (14U)
+#define ETH_MACTSCR_TSEVNTENA_Msk                     (0x1UL << ETH_MACTSCR_TSEVNTENA_Pos) /*!< 0x00004000 */
+#define ETH_MACTSCR_TSEVNTENA                         ETH_MACTSCR_TSEVNTENA_Msk  /* Enable Timestamp Snapshot for Event Messages */
+#define ETH_MACTSCR_TSIPV4ENA_Pos                     (13U)
+#define ETH_MACTSCR_TSIPV4ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV4ENA_Pos) /*!< 0x00002000 */
+#define ETH_MACTSCR_TSIPV4ENA                         ETH_MACTSCR_TSIPV4ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv4-UDP */
+#define ETH_MACTSCR_TSIPV6ENA_Pos                     (12U)
+#define ETH_MACTSCR_TSIPV6ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV6ENA_Pos) /*!< 0x00001000 */
+#define ETH_MACTSCR_TSIPV6ENA                         ETH_MACTSCR_TSIPV6ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv6-UDP */
+#define ETH_MACTSCR_TSIPENA_Pos                       (11U)
+#define ETH_MACTSCR_TSIPENA_Msk                       (0x1UL << ETH_MACTSCR_TSIPENA_Pos) /*!< 0x00000800 */
+#define ETH_MACTSCR_TSIPENA                           ETH_MACTSCR_TSIPENA_Msk  /* Enable Processing of PTP over Ethernet Packets */
+#define ETH_MACTSCR_TSVER2ENA_Pos                     (10U)
+#define ETH_MACTSCR_TSVER2ENA_Msk                     (0x1UL << ETH_MACTSCR_TSVER2ENA_Pos) /*!< 0x00000400 */
+#define ETH_MACTSCR_TSVER2ENA                         ETH_MACTSCR_TSVER2ENA_Msk  /* Enable PTP Packet Processing for Version 2 Format */
+#define ETH_MACTSCR_TSCTRLSSR_Pos                     (9U)
+#define ETH_MACTSCR_TSCTRLSSR_Msk                     (0x1UL << ETH_MACTSCR_TSCTRLSSR_Pos) /*!< 0x00000200 */
+#define ETH_MACTSCR_TSCTRLSSR                         ETH_MACTSCR_TSCTRLSSR_Msk  /* Timestamp Digital or Binary Rollover Control */
+#define ETH_MACTSCR_TSENALL_Pos                       (8U)
+#define ETH_MACTSCR_TSENALL_Msk                       (0x1UL << ETH_MACTSCR_TSENALL_Pos) /*!< 0x00000100 */
+#define ETH_MACTSCR_TSENALL                           ETH_MACTSCR_TSENALL_Msk  /* Enable Timestamp for All Packets */
+#define ETH_MACTSCR_TSADDREG_Pos                      (5U)
+#define ETH_MACTSCR_TSADDREG_Msk                      (0x1UL << ETH_MACTSCR_TSADDREG_Pos) /*!< 0x00000020 */
+#define ETH_MACTSCR_TSADDREG                          ETH_MACTSCR_TSADDREG_Msk  /* Update Addend Register */
+#define ETH_MACTSCR_TSUPDT_Pos                        (3U)
+#define ETH_MACTSCR_TSUPDT_Msk                        (0x1UL << ETH_MACTSCR_TSUPDT_Pos) /*!< 0x00000008 */
+#define ETH_MACTSCR_TSUPDT                            ETH_MACTSCR_TSUPDT_Msk  /* Update Timestamp */
+#define ETH_MACTSCR_TSINIT_Pos                        (2U)
+#define ETH_MACTSCR_TSINIT_Msk                        (0x1UL << ETH_MACTSCR_TSINIT_Pos) /*!< 0x00000004 */
+#define ETH_MACTSCR_TSINIT                             ETH_MACTSCR_TSINIT_Msk  /* Initialize Timestamp */
+#define ETH_MACTSCR_TSCFUPDT_Pos                      (1U)
+#define ETH_MACTSCR_TSCFUPDT_Msk                      (0x1UL << ETH_MACTSCR_TSCFUPDT_Pos) /*!< 0x00000002 */
+#define ETH_MACTSCR_TSCFUPDT                          ETH_MACTSCR_TSCFUPDT_Msk  /* Fine or Coarse Timestamp Update*/
+#define ETH_MACTSCR_TSENA_Pos                         (0U)
+#define ETH_MACTSCR_TSENA_Msk                         (0x1UL << ETH_MACTSCR_TSENA_Pos) /*!< 0x00000001 */
+#define ETH_MACTSCR_TSENA                             ETH_MACTSCR_TSENA_Msk  /* Enable Timestamp */
+
+/* Bit definition for Ethernet MAC Sub-second Increment Register */
+#define ETH_MACMACSSIR_SSINC_Pos                      (16U)
+#define ETH_MACMACSSIR_SSINC_Msk                      (0xFFUL << ETH_MACMACSSIR_SSINC_Pos) /*!< 0x0000FF00 */
+#define ETH_MACMACSSIR_SSINC                          ETH_MACMACSSIR_SSINC_Msk  /* Sub-second Increment Value */
+#define ETH_MACMACSSIR_SNSINC_Pos                     (8U)
+#define ETH_MACMACSSIR_SNSINC_Msk                     (0xFFUL << ETH_MACMACSSIR_SNSINC_Pos) /*!< 0x000000FF */
+#define ETH_MACMACSSIR_SNSINC                         ETH_MACMACSSIR_SNSINC_Msk  /* Sub-nanosecond Increment Value */
+
+/* Bit definition for Ethernet MAC System Time Seconds Register */
+#define ETH_MACSTSR_TSS_Pos                           (0U)
+#define ETH_MACSTSR_TSS_Msk                           (0xFFFFFFFFUL << ETH_MACSTSR_TSS_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACSTSR_TSS                               ETH_MACSTSR_TSS_Msk  /* Timestamp Second */
+
+/* Bit definition for Ethernet MAC System Time Nanoseconds Register */
+#define ETH_MACSTNR_TSSS_Pos                          (0U)
+#define ETH_MACSTNR_TSSS_Msk                          (0x7FFFFFFFUL << ETH_MACSTNR_TSSS_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACSTNR_TSSS                              ETH_MACSTNR_TSSS_Msk  /* Timestamp Sub-seconds */
+
+/* Bit definition for Ethernet MAC System Time Seconds Update Register */
+#define ETH_MACSTSUR_TSS_Pos                          (0U)
+#define ETH_MACSTSUR_TSS_Msk                          (0xFFFFFFFFUL << ETH_MACSTSUR_TSS_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACSTSUR_TSS                              ETH_MACSTSUR_TSS_Msk  /* Timestamp Seconds */
+
+/* Bit definition for Ethernet MAC System Time Nanoseconds Update Register */
+#define ETH_MACSTNUR_ADDSUB_Pos                       (31U)
+#define ETH_MACSTNUR_ADDSUB_Msk                       (0x1UL << ETH_MACSTNUR_ADDSUB_Pos) /*!< 0x80000000 */
+#define ETH_MACSTNUR_ADDSUB                           ETH_MACSTNUR_ADDSUB_Msk  /* Add or Subtract Time */
+#define ETH_MACSTNUR_TSSS_Pos                         (0U)
+#define ETH_MACSTNUR_TSSS_Msk                         (0x7FFFFFFFUL << ETH_MACSTNUR_TSSS_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACSTNUR_TSSS                             ETH_MACSTNUR_TSSS_Msk  /* Timestamp Sub-seconds */
+
+/* Bit definition for Ethernet MAC Timestamp Addend Register */
+#define ETH_MACTSAR_TSAR_Pos                          (0U)
+#define ETH_MACTSAR_TSAR_Msk                          (0xFFFFFFFFUL << ETH_MACTSAR_TSAR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSAR_TSAR                              ETH_MACTSAR_TSAR_Msk  /* Timestamp Addend Register */
+
+/* Bit definition for Ethernet MAC Timestamp Status Register */
+#define ETH_MACTSSR_ATSNS_Pos                         (25U)
+#define ETH_MACTSSR_ATSNS_Msk                         (0x1FUL << ETH_MACTSSR_ATSNS_Pos) /*!< 0x3E000000 */
+#define ETH_MACTSSR_ATSNS                             ETH_MACTSSR_ATSNS_Msk  /* Number of Auxiliary Timestamp Snapshots */
+#define ETH_MACTSSR_ATSSTM_Pos                        (24U)
+#define ETH_MACTSSR_ATSSTM_Msk                        (0x1UL << ETH_MACTSSR_ATSSTM_Pos) /*!< 0x01000000 */
+#define ETH_MACTSSR_ATSSTM                            ETH_MACTSSR_ATSSTM_Msk  /* Auxiliary Timestamp Snapshot Trigger Missed */
+#define ETH_MACTSSR_ATSSTN_Pos                        (16U)
+#define ETH_MACTSSR_ATSSTN_Msk                        (0xFUL << ETH_MACTSSR_ATSSTN_Pos) /*!< 0x000F0000 */
+#define ETH_MACTSSR_ATSSTN                            ETH_MACTSSR_ATSSTN_Msk  /* Auxiliary Timestamp Snapshot Trigger Identifier */
+#define ETH_MACTSSR_TXTSSIS_Pos                       (15U)
+#define ETH_MACTSSR_TXTSSIS_Msk                       (0x1UL << ETH_MACTSSR_TXTSSIS_Pos) /*!< 0x00008000 */
+#define ETH_MACTSSR_TXTSSIS                           ETH_MACTSSR_TXTSSIS_Msk  /* Tx Timestamp Status Interrupt Status */
+#define ETH_MACTSSR_TSTRGTERR0_Pos                    (3U)
+#define ETH_MACTSSR_TSTRGTERR0_Msk                    (0x1UL << ETH_MACTSSR_TSTRGTERR0_Pos) /*!< 0x00000008 */
+#define ETH_MACTSSR_TSTRGTERR0                        ETH_MACTSSR_TSTRGTERR0_Msk  /* Timestamp Target Time Error */
+#define ETH_MACTSSR_AUXTSTRIG_Pos                     (2U)
+#define ETH_MACTSSR_AUXTSTRIG_Msk                     (0x1UL << ETH_MACTSSR_AUXTSTRIG_Pos) /*!< 0x00000004 */
+#define ETH_MACTSSR_AUXTSTRIG                         ETH_MACTSSR_AUXTSTRIG_Msk  /* Auxiliary Timestamp Trigger Snapshot*/
+#define ETH_MACTSSR_TSTARGT0_Pos                      (1U)
+#define ETH_MACTSSR_TSTARGT0_Msk                      (0x1UL << ETH_MACTSSR_TSTARGT0_Pos) /*!< 0x00000002 */
+#define ETH_MACTSSR_TSTARGT0                          ETH_MACTSSR_TSTARGT0_Msk  /* Timestamp Target Time Reached */
+#define ETH_MACTSSR_TSSOVF_Pos                        (0U)
+#define ETH_MACTSSR_TSSOVF_Msk                        (0x1UL << ETH_MACTSSR_TSSOVF_Pos) /*!< 0x00000001 */
+#define ETH_MACTSSR_TSSOVF                            ETH_MACTSSR_TSSOVF_Msk  /* Timestamp Seconds Overflow */
+
+/* Bit definition for Ethernet MAC Tx Timestamp Status Nanoseconds Register */
+#define ETH_MACTTSSNR_TXTSSMIS_Pos                    (31U)
+#define ETH_MACTTSSNR_TXTSSMIS_Msk                    (0x1UL << ETH_MACTTSSNR_TXTSSMIS_Pos) /*!< 0x80000000 */
+#define ETH_MACTTSSNR_TXTSSMIS                        ETH_MACTTSSNR_TXTSSMIS_Msk  /* Transmit Timestamp Status Missed */
+#define ETH_MACTTSSNR_TXTSSLO_Pos                     (0U)
+#define ETH_MACTTSSNR_TXTSSLO_Msk                     (0x7FFFFFFFUL << ETH_MACTTSSNR_TXTSSLO_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACTTSSNR_TXTSSLO                         ETH_MACTTSSNR_TXTSSLO_Msk  /* Transmit Timestamp Status Low */
+
+/* Bit definition for Ethernet MAC Tx Timestamp Status Seconds Register */
+#define ETH_MACTTSSSR_TXTSSHI_Pos                     (0U)
+#define ETH_MACTTSSSR_TXTSSHI_Msk                     (0xFFFFFFFFUL << ETH_MACTTSSSR_TXTSSHI_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTTSSSR_TXTSSHI                         ETH_MACTTSSSR_TXTSSHI_Msk  /* Transmit Timestamp Status High */
+
+/* Bit definition for Ethernet MAC Auxiliary Control Register*/
+#define ETH_MACACR_ATSEN3_Pos                         (7U)
+#define ETH_MACACR_ATSEN3_Msk                         (0x1UL << ETH_MACACR_ATSEN3_Pos) /*!< 0x00000080 */
+#define ETH_MACACR_ATSEN3                             ETH_MACACR_ATSEN3_Msk  /* Auxiliary Snapshot 3 Enable */
+#define ETH_MACACR_ATSEN2_Pos                         (6U)
+#define ETH_MACACR_ATSEN2_Msk                         (0x1UL << ETH_MACACR_ATSEN2_Pos) /*!< 0x00000040 */
+#define ETH_MACACR_ATSEN2                             ETH_MACACR_ATSEN2_Msk  /* Auxiliary Snapshot 2 Enable */
+#define ETH_MACACR_ATSEN1_Pos                         (5U)
+#define ETH_MACACR_ATSEN1_Msk                         (0x1UL << ETH_MACACR_ATSEN1_Pos) /*!< 0x00000020 */
+#define ETH_MACACR_ATSEN1                             ETH_MACACR_ATSEN1_Msk  /* Auxiliary Snapshot 1 Enable */
+#define ETH_MACACR_ATSEN0_Pos                         (4U)
+#define ETH_MACACR_ATSEN0_Msk                         (0x1UL << ETH_MACACR_ATSEN0_Pos) /*!< 0x00000010 */
+#define ETH_MACACR_ATSEN0                             ETH_MACACR_ATSEN0_Msk  /* Auxiliary Snapshot 0 Enable */
+#define ETH_MACACR_ATSFC_Pos                          (0U)
+#define ETH_MACACR_ATSFC_Msk                          (0x1UL << ETH_MACACR_ATSFC_Pos) /*!< 0x00000001 */
+#define ETH_MACACR_ATSFC                              ETH_MACACR_ATSFC_Msk  /* Auxiliary Snapshot FIFO Clear */
+
+/* Bit definition for Ethernet MAC Auxiliary Timestamp Nanoseconds Register */
+#define ETH_MACATSNR_AUXTSLO_Pos                      (0U)
+#define ETH_MACATSNR_AUXTSLO_Msk                      (0x7FFFFFFFUL << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACATSNR_AUXTSLO                          ETH_MACATSNR_AUXTSLO_Msk  /* Auxiliary Timestamp */
+
+/* Bit definition for Ethernet MAC Auxiliary Timestamp Seconds Register */
+#define ETH_MACATSSR_AUXTSHI_Pos                      (0U)
+#define ETH_MACATSSR_AUXTSHI_Msk                      (0xFFFFFFFFUL << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACATSSR_AUXTSHI                          ETH_MACATSSR_AUXTSHI_Msk  /* Auxiliary Timestamp */
+
+/* Bit definition for Ethernet MAC Timestamp Ingress Asymmetric Correction Register */
+#define ETH_MACTSIACR_OSTIAC_Pos                      (0U)
+#define ETH_MACTSIACR_OSTIAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSIACR_OSTIAC                          ETH_MACTSIACR_OSTIAC_Msk  /* One-Step Timestamp Ingress Asymmetry Correction */
+
+/* Bit definition for Ethernet MAC Timestamp Egress Asymmetric Correction Register */
+#define ETH_MACTSEACR_OSTEAC_Pos                      (0U)
+#define ETH_MACTSEACR_OSTEAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSEACR_OSTEAC                          ETH_MACTSEACR_OSTEAC_Msk  /* One-Step Timestamp Egress Asymmetry Correction */
+
+/* Bit definition for Ethernet MAC Timestamp Ingress Correction Nanosecond Register */
+#define ETH_MACTSICNR_TSIC_Pos                        (0U)
+#define ETH_MACTSICNR_TSIC_Msk                        (0xFFFFFFFFUL << ETH_MACTSICNR_TSIC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSICNR_TSIC                            ETH_MACTSICNR_TSIC_Msk  /* Timestamp Ingress Correction */
+
+/* Bit definition for Ethernet MAC Timestamp Egress correction Nanosecond Register */
+#define ETH_MACTSECNR_TSEC_Pos                        (0U)
+#define ETH_MACTSECNR_TSEC_Msk                        (0xFFFFFFFFUL << ETH_MACTSECNR_TSEC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSECNR_TSEC                            ETH_MACTSECNR_TSEC_Msk  /* Timestamp Egress Correction */
+
+/* Bit definition for Ethernet MAC PPS Control Register */
+#define ETH_MACPPSCR_TRGTMODSEL0_Pos                  (5U)
+#define ETH_MACPPSCR_TRGTMODSEL0_Msk                  (0x3UL << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000060 */
+#define ETH_MACPPSCR_TRGTMODSEL0                      ETH_MACPPSCR_TRGTMODSEL0_Msk  /* Target Time Register Mode for PPS Output */
+#define ETH_MACPPSCR_PPSEN0_Pos                       (4U)
+#define ETH_MACPPSCR_PPSEN0_Msk                       (0x1UL << ETH_MACPPSCR_PPSEN0_Pos) /*!< 0x00000010 */
+#define ETH_MACPPSCR_PPSEN0                           ETH_MACPPSCR_PPSEN0_Msk  /* Flexible PPS Output Mode Enable */
+#define ETH_MACPPSCR_PPSCTRL_Pos                      (0U)
+#define ETH_MACPPSCR_PPSCTRL_Msk                      (0xFUL << ETH_MACPPSCR_PPSCTRL_Pos) /*!< 0x0000000F */
+#define ETH_MACPPSCR_PPSCTRL                          ETH_MACPPSCR_PPSCTRL_Msk  /* PPS Output Frequency Control */
+
+/* Bit definition for Ethernet MAC PPS Target Time Seconds Register */
+#define ETH_MACPPSTTSR_TSTRH0_Pos                     (0U)
+#define ETH_MACPPSTTSR_TSTRH0_Msk                     (0xFFFFFFFFUL << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACPPSTTSR_TSTRH0                         ETH_MACPPSTTSR_TSTRH0_Msk  /* PPS Target Time Seconds Register */
+
+/* Bit definition for Ethernet MAC PPS Target Time Nanoseconds Register */
+#define ETH_MACPPSTTNR_TRGTBUSY0_Pos                  (31U)
+#define ETH_MACPPSTTNR_TRGTBUSY0_Msk                  (0x1UL << ETH_MACPPSTTNR_TRGTBUSY0_Pos) /*!< 0x80000000 */
+#define ETH_MACPPSTTNR_TRGTBUSY0                      ETH_MACPPSTTNR_TRGTBUSY0_Msk  /* PPS Target Time Register Busy */
+#define ETH_MACPPSTTNR_TTSL0_Pos                      (0U)
+#define ETH_MACPPSTTNR_TTSL0_Msk                      (0x7FFFFFFFUL << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACPPSTTNR_TTSL0                          ETH_MACPPSTTNR_TTSL0_Msk  /* Target Time Low for PPS Register */
+
+/* Bit definition for Ethernet MAC PPS Interval Register */
+#define ETH_MACPPSIR_PPSINT0_Pos                      (0U)
+#define ETH_MACPPSIR_PPSINT0_Msk                      (0xFFFFFFFFUL << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACPPSIR_PPSINT0                          ETH_MACPPSIR_PPSINT0_Msk  /* PPS Output Signal Interval */
+
+/* Bit definition for Ethernet MAC PPS Width Register */
+#define ETH_MACPPSWR_PPSWIDTH0_Pos                    (0U)
+#define ETH_MACPPSWR_PPSWIDTH0_Msk                    (0xFFFFFFFFUL << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACPPSWR_PPSWIDTH0                        ETH_MACPPSWR_PPSWIDTH0_Msk  /* PPS Output Signal Width */
+
+/* Bit definition for Ethernet MAC PTP Offload Control Register */
+#define ETH_MACPOCR_DN_Pos                            (8U)
+#define ETH_MACPOCR_DN_Msk                            (0xFFUL << ETH_MACPOCR_DN_Pos) /*!< 0x0000FF00 */
+#define ETH_MACPOCR_DN                                ETH_MACPOCR_DN_Msk  /* Domain Number */
+#define ETH_MACPOCR_DRRDIS_Pos                        (6U)
+#define ETH_MACPOCR_DRRDIS_Msk                        (0x1UL << ETH_MACPOCR_DRRDIS_Pos) /*!< 0x00000040 */
+#define ETH_MACPOCR_DRRDIS                            ETH_MACPOCR_DRRDIS_Msk  /* Disable PTO Delay Request/Response response generation */
+#define ETH_MACPOCR_APDREQTRIG_Pos                    (5U)
+#define ETH_MACPOCR_APDREQTRIG_Msk                    (0x1UL << ETH_MACPOCR_APDREQTRIG_Pos) /*!< 0x00000020 */
+#define ETH_MACPOCR_APDREQTRIG                        ETH_MACPOCR_APDREQTRIG_Msk  /* Automatic PTP Pdelay_Req message Trigger */
+#define ETH_MACPOCR_ASYNCTRIG_Pos                     (4U)
+#define ETH_MACPOCR_ASYNCTRIG_Msk                     (0x1UL << ETH_MACPOCR_ASYNCTRIG_Pos) /*!< 0x00000010 */
+#define ETH_MACPOCR_ASYNCTRIG                         ETH_MACPOCR_ASYNCTRIG_Msk  /* Automatic PTP SYNC message Trigger */
+#define ETH_MACPOCR_APDREQEN_Pos                      (2U)
+#define ETH_MACPOCR_APDREQEN_Msk                      (0x1UL << ETH_MACPOCR_APDREQEN_Pos) /*!< 0x00000004 */
+#define ETH_MACPOCR_APDREQEN                          ETH_MACPOCR_APDREQEN_Msk  /* Automatic PTP Pdelay_Req message Enable */
+#define ETH_MACPOCR_ASYNCEN_Pos                       (1U)
+#define ETH_MACPOCR_ASYNCEN_Msk                       (0x1UL << ETH_MACPOCR_ASYNCEN_Pos) /*!< 0x00000002 */
+#define ETH_MACPOCR_ASYNCEN                           ETH_MACPOCR_ASYNCEN_Msk  /* Automatic PTP SYNC message Enable */
+#define ETH_MACPOCR_PTOEN_Pos                         (0U)
+#define ETH_MACPOCR_PTOEN_Msk                         (0x1UL << ETH_MACPOCR_PTOEN_Pos) /*!< 0x00000001 */
+#define ETH_MACPOCR_PTOEN                             ETH_MACPOCR_PTOEN_Msk  /* PTP Offload Enable */
+
+/* Bit definition for Ethernet MAC PTP Source Port Identity 0 Register */
+#define ETH_MACSPI0R_SPI0_Pos                         (0U)
+#define ETH_MACSPI0R_SPI0_Msk                         (0xFFFFFFFFUL << ETH_MACSPI0R_SPI0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACSPI0R_SPI0                             ETH_MACSPI0R_SPI0_Msk  /* Source Port Identity 0 */
+
+/* Bit definition for Ethernet MAC PTP Source Port Identity 1 Register */
+#define ETH_MACSPI1R_SPI1_Pos                         (0U)
+#define ETH_MACSPI1R_SPI1_Msk                         (0xFFFFFFFFUL << ETH_MACSPI1R_SPI1_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACSPI1R_SPI1                             ETH_MACSPI1R_SPI1_Msk  /* Source Port Identity 1 */
+
+/* Bit definition for Ethernet MAC PTP Source Port Identity 2 Register */
+#define ETH_MACSPI2R_SPI2_Pos                         (0U)
+#define ETH_MACSPI2R_SPI2_Msk                         (0xFFFFUL << ETH_MACSPI2R_SPI2_Pos) /*!< 0x0000FFFF */
+#define ETH_MACSPI2R_SPI2                             ETH_MACSPI2R_SPI2_Msk  /* Source Port Identity 2 */
+
+/* Bit definition for Ethernet MAC Log Message Interval Register */
+#define ETH_MACLMIR_LMPDRI_Pos                        (24U)
+#define ETH_MACLMIR_LMPDRI_Msk                        (0xFFUL << ETH_MACLMIR_LMPDRI_Pos) /*!< 0xFF000000 */
+#define ETH_MACLMIR_LMPDRI                             ETH_MACLMIR_LMPDRI_Msk  /* Log Min Pdelay_Req Interval */
+#define ETH_MACLMIR_DRSYNCR_Pos                       (8U)
+#define ETH_MACLMIR_DRSYNCR_Msk                       (0x7UL << ETH_MACLMIR_DRSYNCR_Pos) /*!< 0x00000700 */
+#define ETH_MACLMIR_DRSYNCR                           ETH_MACLMIR_DRSYNCR_Msk  /* Delay_Req to SYNC Ratio */
+#define ETH_MACLMIR_LSI_Pos                           (0U)
+#define ETH_MACLMIR_LSI_Msk                           (0xFFUL << ETH_MACLMIR_LSI_Pos) /*!< 0x000000FF */
+#define ETH_MACLMIR_LSI                               ETH_MACLMIR_LSI_Msk  /* Log Sync Interval */
+
+/* Bit definition for Ethernet MTL Operation Mode Register */
+#define ETH_MTLOMR_CNTCLR_Pos                         (9U)
+#define ETH_MTLOMR_CNTCLR_Msk                         (0x1UL << ETH_MTLOMR_CNTCLR_Pos) /*!< 0x00000200 */
+#define ETH_MTLOMR_CNTCLR                             ETH_MTLOMR_CNTCLR_Msk    /* Counters Reset */
+#define ETH_MTLOMR_CNTPRST_Pos                        (8U)
+#define ETH_MTLOMR_CNTPRST_Msk                        (0x1UL << ETH_MTLOMR_CNTPRST_Pos) /*!< 0x00000100 */
+#define ETH_MTLOMR_CNTPRST                            ETH_MTLOMR_CNTPRST_Msk   /* Counters Preset */
+#define ETH_MTLOMR_DTXSTS_Pos                         (1U)
+#define ETH_MTLOMR_DTXSTS_Msk                         (0x1UL << ETH_MTLOMR_DTXSTS_Pos) /*!< 0x00000002 */
+#define ETH_MTLOMR_DTXSTS                             ETH_MTLOMR_DTXSTS_Msk  /* Drop Transmit Status */
+
+/* Bit definition for Ethernet MTL Interrupt Status Register */
+#define ETH_MTLISR_MACIS_Pos                          (16U)
+#define ETH_MTLISR_MACIS_Msk                          (0x1UL << ETH_MTLISR_MACIS_Pos) /*!< 0x00010000 */
+#define ETH_MTLISR_MACIS                              ETH_MTLISR_MACIS_Msk     /* MAC Interrupt Status */
+#define ETH_MTLISR_QIS_Pos                            (0U)
+#define ETH_MTLISR_QIS_Msk                            (0x1UL << ETH_MTLISR_QIS_Pos) /*!< 0x00000001 */
+#define ETH_MTLISR_QIS                                ETH_MTLISR_QIS_Msk       /* Queue Interrupt status */
+
+/* Bit definition for Ethernet MTL Tx Queue Operation Mode Register */
+#define ETH_MTLTQOMR_TTC_Pos                          (4U)
+#define ETH_MTLTQOMR_TTC_Msk                          (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */
+#define ETH_MTLTQOMR_TTC                              ETH_MTLTQOMR_TTC_Msk     /* Transmit Threshold Control */
+#define ETH_MTLTQOMR_TTC_32BITS                       ((uint32_t)0x00000000)   /* 32 bits Threshold */
+#define ETH_MTLTQOMR_TTC_64BITS                       ((uint32_t)0x00000010)   /* 64  bits Threshold */
+#define ETH_MTLTQOMR_TTC_96BITS                       ((uint32_t)0x00000020)   /* 96 bits Threshold */
+#define ETH_MTLTQOMR_TTC_128BITS                      ((uint32_t)0x00000030)   /* 128 bits Threshold */
+#define ETH_MTLTQOMR_TTC_192BITS                      ((uint32_t)0x00000040)   /* 192 bits Threshold */
+#define ETH_MTLTQOMR_TTC_256BITS                      ((uint32_t)0x00000050)   /* 256 bits Threshold */
+#define ETH_MTLTQOMR_TTC_384BITS                      ((uint32_t)0x00000060)   /* 384 bits Threshold */
+#define ETH_MTLTQOMR_TTC_512BITS                      ((uint32_t)0x00000070)   /* 512 bits Threshold */
+#define ETH_MTLTQOMR_TSF_Pos                          (1U)
+#define ETH_MTLTQOMR_TSF_Msk                          (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */
+#define ETH_MTLTQOMR_TSF                              ETH_MTLTQOMR_TSF_Msk     /* Transmit Store and Forward */
+#define ETH_MTLTQOMR_FTQ_Pos                          (0U)
+#define ETH_MTLTQOMR_FTQ_Msk                          (0x1UL << ETH_MTLTQOMR_FTQ_Pos) /*!< 0x00000001 */
+#define ETH_MTLTQOMR_FTQ                              ETH_MTLTQOMR_FTQ_Msk     /* Flush Transmit Queue */
+
+/* Bit definition for Ethernet MTL Tx Queue Underflow Register */
+#define ETH_MTLTQUR_UFCNTOVF_Pos                      (11U)
+#define ETH_MTLTQUR_UFCNTOVF_Msk                      (0x1UL << ETH_MTLTQUR_UFCNTOVF_Pos) /*!< 0x00000800 */
+#define ETH_MTLTQUR_UFCNTOVF                          ETH_MTLTQUR_UFCNTOVF_Msk /* Overflow Bit for Underflow Packet Counter */
+#define ETH_MTLTQUR_UFPKTCNT_Pos                      (0U)
+#define ETH_MTLTQUR_UFPKTCNT_Msk                      (0x7FFUL << ETH_MTLTQUR_UFPKTCNT_Pos) /*!< 0x000007FF */
+#define ETH_MTLTQUR_UFPKTCNT                          ETH_MTLTQUR_UFPKTCNT_Msk /* Underflow Packet Counter */
+
+/* Bit definition for Ethernet MTL Tx Queue Debug Register */
+#define ETH_MTLTQDR_STXSTSF_Pos                       (20U)
+#define ETH_MTLTQDR_STXSTSF_Msk                       (0x7UL << ETH_MTLTQDR_STXSTSF_Pos) /*!< 0x00700000 */
+#define ETH_MTLTQDR_STXSTSF                           ETH_MTLTQDR_STXSTSF_Msk  /* Number of Status Words in the Tx Status FIFO of Queue */
+#define ETH_MTLTQDR_PTXQ_Pos                          (16U)
+#define ETH_MTLTQDR_PTXQ_Msk                          (0x7UL << ETH_MTLTQDR_PTXQ_Pos) /*!< 0x00070000 */
+#define ETH_MTLTQDR_PTXQ                              ETH_MTLTQDR_PTXQ_Msk     /* Number of Packets in the Transmit Queue */
+#define ETH_MTLTQDR_TXSTSFSTS_Pos                     (5U)
+#define ETH_MTLTQDR_TXSTSFSTS_Msk                     (0x1UL << ETH_MTLTQDR_TXSTSFSTS_Pos) /*!< 0x00000020 */
+#define ETH_MTLTQDR_TXSTSFSTS                         ETH_MTLTQDR_TXSTSFSTS_Msk /* MTL Tx Status FIFO Full Status */
+#define ETH_MTLTQDR_TXQSTS_Pos                        (4U)
+#define ETH_MTLTQDR_TXQSTS_Msk                        (0x1UL << ETH_MTLTQDR_TXQSTS_Pos) /*!< 0x00000010 */
+#define ETH_MTLTQDR_TXQSTS                            ETH_MTLTQDR_TXQSTS_Msk   /* MTL Tx Queue Not Empty Status */
+#define ETH_MTLTQDR_TWCSTS_Pos                        (3U)
+#define ETH_MTLTQDR_TWCSTS_Msk                        (0x1UL << ETH_MTLTQDR_TWCSTS_Pos) /*!< 0x00000008 */
+#define ETH_MTLTQDR_TWCSTS                            ETH_MTLTQDR_TWCSTS_Msk   /* MTL Tx Queue Write Controller Status */
+#define ETH_MTLTQDR_TRCSTS_Pos                        (1U)
+#define ETH_MTLTQDR_TRCSTS_Msk                        (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */
+#define ETH_MTLTQDR_TRCSTS                            ETH_MTLTQDR_TRCSTS_Msk  /* MTL Tx Queue Read Controller Status */
+#define ETH_MTLTQDR_TRCSTS_IDLE                       ((uint32_t)0x00000000)  /* Idle state */
+#define ETH_MTLTQDR_TRCSTS_READ                       ((uint32_t)0x00000002)  /* Read state (transferring data to the MAC transmitter) */
+#define ETH_MTLTQDR_TRCSTS_WAITING                    ((uint32_t)0x00000004)  /* Waiting for pending Tx Status from the MAC transmitter */
+#define ETH_MTLTQDR_TRCSTS_FLUSHING                   ((uint32_t)0x00000006)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */
+#define ETH_MTLTQDR_TXQPAUSED_Pos                     (0U)
+#define ETH_MTLTQDR_TXQPAUSED_Msk                     (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */
+#define ETH_MTLTQDR_TXQPAUSED                         ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
+
+/* Bit definition for Ethernet MTL Queue Interrupt Control Status Register */
+#define ETH_MTLQICSR_RXOIE_Pos                        (24U)
+#define ETH_MTLQICSR_RXOIE_Msk                        (0x1UL << ETH_MTLQICSR_RXOIE_Pos) /*!< 0x01000000 */
+#define ETH_MTLQICSR_RXOIE                            ETH_MTLQICSR_RXOIE_Msk   /* Receive Queue Overflow Interrupt Enable */
+#define ETH_MTLQICSR_RXOVFIS_Pos                      (16U)
+#define ETH_MTLQICSR_RXOVFIS_Msk                      (0x1UL << ETH_MTLQICSR_RXOVFIS_Pos) /*!< 0x00010000 */
+#define ETH_MTLQICSR_RXOVFIS                          ETH_MTLQICSR_RXOVFIS_Msk /* Receive Queue Overflow Interrupt Status */
+#define ETH_MTLQICSR_TXUIE_Pos                        (8U)
+#define ETH_MTLQICSR_TXUIE_Msk                        (0x1UL << ETH_MTLQICSR_TXUIE_Pos) /*!< 0x00000100 */
+#define ETH_MTLQICSR_TXUIE                            ETH_MTLQICSR_TXUIE_Msk   /* Transmit Queue Underflow Interrupt Enable */
+#define ETH_MTLQICSR_TXUNFIS_Pos                      (0U)
+#define ETH_MTLQICSR_TXUNFIS_Msk                      (0x1UL << ETH_MTLQICSR_TXUNFIS_Pos) /*!< 0x00000001 */
+#define ETH_MTLQICSR_TXUNFIS                          ETH_MTLQICSR_TXUNFIS_Msk /* Transmit Queue Underflow Interrupt Status */
+
+/* Bit definition for Ethernet MTL Rx Queue Operation Mode Register */
+#define ETH_MTLRQOMR_RQS_Pos                          (20U)
+#define ETH_MTLRQOMR_RQS_Msk                          (0x7UL << ETH_MTLRQOMR_RQS_Pos) /*!< 0x00700000 */
+#define ETH_MTLRQOMR_RQS                              ETH_MTLRQOMR_RQS_Msk /* Receive Queue Size */
+#define ETH_MTLRQOMR_RFD_Pos                          (14U)
+#define ETH_MTLRQOMR_RFD_Msk                          (0x7UL << ETH_MTLRQOMR_RFD_Pos) /*!< 0x0001C000 */
+#define ETH_MTLRQOMR_RFD                              ETH_MTLRQOMR_RFD_Msk /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */
+#define ETH_MTLRQOMR_RFA_Pos                          (8U)
+#define ETH_MTLRQOMR_RFA_Msk                          (0x7UL << ETH_MTLRQOMR_RFA_Pos) /*!< 0x00000700 */
+#define ETH_MTLRQOMR_RFA                              ETH_MTLRQOMR_RFA_Msk /* Threshold for Activating Flow Control (in half-duplex and full-duplex */
+#define ETH_MTLRQOMR_EHFC_Pos                         (7U)
+#define ETH_MTLRQOMR_EHFC_Msk                         (0x1UL << ETH_MTLRQOMR_EHFC_Pos) /*!< 0x00000080 */
+#define ETH_MTLRQOMR_EHFC                             ETH_MTLRQOMR_EHFC_Msk /* DEnable Hardware Flow Control */
+#define ETH_MTLRQOMR_DISTCPEF_Pos                     (6U)
+#define ETH_MTLRQOMR_DISTCPEF_Msk                     (0x1UL << ETH_MTLRQOMR_DISTCPEF_Pos) /*!< 0x00000040 */
+#define ETH_MTLRQOMR_DISTCPEF                         ETH_MTLRQOMR_DISTCPEF_Msk /* Disable Dropping of TCP/IP Checksum Error Packets */
+#define ETH_MTLRQOMR_RSF_Pos                          (5U)
+#define ETH_MTLRQOMR_RSF_Msk                          (0x1UL << ETH_MTLRQOMR_RSF_Pos) /*!< 0x00000020 */
+#define ETH_MTLRQOMR_RSF                              ETH_MTLRQOMR_RSF_Msk     /* Receive Queue Store and Forward */
+#define ETH_MTLRQOMR_FEP_Pos                          (4U)
+#define ETH_MTLRQOMR_FEP_Msk                          (0x1UL << ETH_MTLRQOMR_FEP_Pos) /*!< 0x00000010 */
+#define ETH_MTLRQOMR_FEP                              ETH_MTLRQOMR_FEP_Msk     /* Forward Error Packets */
+#define ETH_MTLRQOMR_FUP_Pos                          (3U)
+#define ETH_MTLRQOMR_FUP_Msk                          (0x1UL << ETH_MTLRQOMR_FUP_Pos) /*!< 0x00000008 */
+#define ETH_MTLRQOMR_FUP                              ETH_MTLRQOMR_FUP_Msk     /* Forward Undersized Good Packets */
+#define ETH_MTLRQOMR_RTC_Pos                          (0U)
+#define ETH_MTLRQOMR_RTC_Msk                          (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */
+#define ETH_MTLRQOMR_RTC                              ETH_MTLRQOMR_RTC_Msk     /* Receive Queue Threshold Control */
+#define ETH_MTLRQOMR_RTC_64BITS                       ((uint32_t)0x00000000)   /* 64 bits Threshold */
+#define ETH_MTLRQOMR_RTC_32BITS                       ((uint32_t)0x00000001)   /* 32 bits Threshold */
+#define ETH_MTLRQOMR_RTC_96BITS                       ((uint32_t)0x00000002)   /* 96 bits Threshold */
+#define ETH_MTLRQOMR_RTC_128BITS                      ((uint32_t)0x00000003)   /* 128 bits Threshold */
+
+/* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
+#define ETH_MTLRQMPOCR_MISCNTOVF_Pos                  (27U)
+#define ETH_MTLRQMPOCR_MISCNTOVF_Msk                  (0x1UL << ETH_MTLRQMPOCR_MISCNTOVF_Pos) /*!< 0x08000000 */
+#define ETH_MTLRQMPOCR_MISCNTOVF                      ETH_MTLRQMPOCR_MISCNTOVF_Msk /* Missed Packet Counter Overflow Bit */
+#define ETH_MTLRQMPOCR_MISPKTCNT_Pos                  (16U)
+#define ETH_MTLRQMPOCR_MISPKTCNT_Msk                  (0x7FFUL << ETH_MTLRQMPOCR_MISPKTCNT_Pos) /*!< 0x07FF0000 */
+#define ETH_MTLRQMPOCR_MISPKTCNT                      ETH_MTLRQMPOCR_MISPKTCNT_Msk /* Missed Packet Counter */
+#define ETH_MTLRQMPOCR_OVFCNTOVF_Pos                  (11U)
+#define ETH_MTLRQMPOCR_OVFCNTOVF_Msk                  (0x1UL << ETH_MTLRQMPOCR_OVFCNTOVF_Pos) /*!< 0x00000800 */
+#define ETH_MTLRQMPOCR_OVFCNTOVF                      ETH_MTLRQMPOCR_OVFCNTOVF_Msk /* Overflow Counter Overflow Bit */
+#define ETH_MTLRQMPOCR_OVFPKTCNT_Pos                  (0U)
+#define ETH_MTLRQMPOCR_OVFPKTCNT_Msk                  (0x7FFUL << ETH_MTLRQMPOCR_OVFPKTCNT_Pos) /*!< 0x000007FF */
+#define ETH_MTLRQMPOCR_OVFPKTCNT                      ETH_MTLRQMPOCR_OVFPKTCNT_Msk /* Overflow Packet Counter */
+
+/* Bit definition for Ethernet MTL Rx Queue Debug Register */
+#define ETH_MTLRQDR_PRXQ_Pos                          (16U)
+#define ETH_MTLRQDR_PRXQ_Msk                          (0x3FFFUL << ETH_MTLRQDR_PRXQ_Pos) /*!< 0x3FFF0000 */
+#define ETH_MTLRQDR_PRXQ                              ETH_MTLRQDR_PRXQ_Msk     /* Number of Packets in Receive Queue */
+#define ETH_MTLRQDR_RXQSTS_Pos                        (4U)
+#define ETH_MTLRQDR_RXQSTS_Msk                        (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */
+#define ETH_MTLRQDR_RXQSTS                            ETH_MTLRQDR_RXQSTS_Msk   /* MTL Rx Queue Fill-Level Status */
+#define ETH_MTLRQDR_RXQSTS_EMPTY                      ((uint32_t)0x00000000)   /* Rx Queue empty */
+#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos         (4U)
+#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
+#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD             ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
+#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos         (5U)
+#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos) /*!< 0x00000020 */
+#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD             ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk /* Rx Queue fill-level above flow-control activate threshold */
+#define ETH_MTLRQDR_RXQSTS_FULL_Pos                   (4U)
+#define ETH_MTLRQDR_RXQSTS_FULL_Msk                   (0x3UL << ETH_MTLRQDR_RXQSTS_FULL_Pos) /*!< 0x00000030 */
+#define ETH_MTLRQDR_RXQSTS_FULL                       ETH_MTLRQDR_RXQSTS_FULL_Msk /* Rx Queue full */
+#define ETH_MTLRQDR_RRCSTS_Pos                        (1U)
+#define ETH_MTLRQDR_RRCSTS_Msk                        (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */
+#define ETH_MTLRQDR_RRCSTS                            ETH_MTLRQDR_RRCSTS_Msk   /* MTL Rx Queue Read Controller State */
+#define ETH_MTLRQDR_RRCSTS_IDLE                       ((uint32_t)0x00000000)   /* Idle state */
+#define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos            (1U)
+#define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk            (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
+#define ETH_MTLRQDR_RRCSTS_READINGDATA                ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
+#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos          (2U)
+#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk          (0x1UL << ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos) /*!< 0x00000004 */
+#define ETH_MTLRQDR_RRCSTS_READINGSTATUS              ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk /* Reading packet status (or timestamp) */
+#define ETH_MTLRQDR_RRCSTS_FLUSHING_Pos               (1U)
+#define ETH_MTLRQDR_RRCSTS_FLUSHING_Msk               (0x3UL << ETH_MTLRQDR_RRCSTS_FLUSHING_Pos) /*!< 0x00000006 */
+#define ETH_MTLRQDR_RRCSTS_FLUSHING                   ETH_MTLRQDR_RRCSTS_FLUSHING_Msk /* Flushing the packet data and status */
+#define ETH_MTLRQDR_RWCSTS_Pos                        (0U)
+#define ETH_MTLRQDR_RWCSTS_Msk                        (0x1UL << ETH_MTLRQDR_RWCSTS_Pos) /*!< 0x00000001 */
+#define ETH_MTLRQDR_RWCSTS                            ETH_MTLRQDR_RWCSTS_Msk   /* MTL Rx Queue Write Controller Active Status */
+
+/* Bit definition for Ethernet MTL Rx Queue Control Register */
+#define ETH_MTLRQCR_RQPA_Pos                          (3U)
+#define ETH_MTLRQCR_RQPA_Msk                          (0x1UL << ETH_MTLRQCR_RQPA_Pos) /*!< 0x00000008 */
+#define ETH_MTLRQCR_RQPA                              ETH_MTLRQCR_RQPA_Msk     /* Receive Queue Packet Arbitration */
+#define ETH_MTLRQCR_RQW_Pos                           (0U)
+#define ETH_MTLRQCR_RQW_Msk                           (0x7UL << ETH_MTLRQCR_RQW_Pos) /*!< 0x00000007 */
+#define ETH_MTLRQCR_RQW                               ETH_MTLRQCR_RQW_Msk      /* Receive Queue Weight */
+
+/* Bit definition for Ethernet DMA Mode Register */
+#define ETH_DMAMR_INTM_Pos                            (16U)
+#define ETH_DMAMR_INTM_Msk                            (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */
+#define ETH_DMAMR_INTM                                ETH_DMAMR_INTM_Msk       /* This field defines the interrupt mode */
+#define ETH_DMAMR_INTM_0                              (0x0UL << ETH_DMAMR_INTM_Pos) /*!< 0x00000000 */
+#define ETH_DMAMR_INTM_1                              (0x1UL << ETH_DMAMR_INTM_Pos) /*!< 0x00010000 */
+#define ETH_DMAMR_INTM_2                              (0x2UL << ETH_DMAMR_INTM_Pos) /*!< 0x00020000 */
+#define ETH_DMAMR_PR_Pos                              (12U)
+#define ETH_DMAMR_PR_Msk                              (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
+#define ETH_DMAMR_PR                                  ETH_DMAMR_PR_Msk         /* Priority Ratio */
+#define ETH_DMAMR_PR_1_1                              ((uint32_t)0x00000000)   /* The priority ratio is 1:1 */
+#define ETH_DMAMR_PR_2_1                              ((uint32_t)0x00001000)   /* The priority ratio is 2:1 */
+#define ETH_DMAMR_PR_3_1                              ((uint32_t)0x00002000)   /* The priority ratio is 3:1 */
+#define ETH_DMAMR_PR_4_1                              ((uint32_t)0x00003000)   /* The priority ratio is 4:1 */
+#define ETH_DMAMR_PR_5_1                              ((uint32_t)0x00004000)   /* The priority ratio is 5:1 */
+#define ETH_DMAMR_PR_6_1                              ((uint32_t)0x00005000)   /* The priority ratio is 6:1 */
+#define ETH_DMAMR_PR_7_1                              ((uint32_t)0x00006000)   /* The priority ratio is 7:1 */
+#define ETH_DMAMR_PR_8_1                              ((uint32_t)0x00007000)   /* The priority ratio is 8:1 */
+#define ETH_DMAMR_TXPR_Pos                            (11U)
+#define ETH_DMAMR_TXPR_Msk                            (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
+#define ETH_DMAMR_TXPR                                ETH_DMAMR_TXPR_Msk       /* Transmit Priority */
+#define ETH_DMAMR_DA_Pos                              (1U)
+#define ETH_DMAMR_DA_Msk                              (0x1UL << ETH_DMAMR_DA_Pos) /*!< 0x00000002 */
+#define ETH_DMAMR_DA                                  ETH_DMAMR_DA_Msk         /* DMA Tx or Rx Arbitration Scheme */
+#define ETH_DMAMR_SWR_Pos                             (0U)
+#define ETH_DMAMR_SWR_Msk                             (0x1UL << ETH_DMAMR_SWR_Pos) /*!< 0x00000001 */
+#define ETH_DMAMR_SWR                                 ETH_DMAMR_SWR_Msk        /* Software Reset */
+
+/* Bit definition for Ethernet DMA SysBus Mode Register */
+#define ETH_DMASBMR_RB_Pos                            (15U)
+#define ETH_DMASBMR_RB_Msk                            (0x1UL << ETH_DMASBMR_RB_Pos) /*!< 0x00008000 */
+#define ETH_DMASBMR_RB                                ETH_DMASBMR_RB_Msk       /* Rebuild INCRx Burst */
+#define ETH_DMASBMR_MB_Pos                            (14U)
+#define ETH_DMASBMR_MB_Msk                            (0x1UL << ETH_DMASBMR_MB_Pos) /*!< 0x00004000 */
+#define ETH_DMASBMR_MB                                ETH_DMASBMR_MB_Msk       /* Mixed Burst */
+#define ETH_DMASBMR_AAL_Pos                           (12U)
+#define ETH_DMASBMR_AAL_Msk                           (0x1UL << ETH_DMASBMR_AAL_Pos) /*!< 0x00001000 */
+#define ETH_DMASBMR_AAL                               ETH_DMASBMR_AAL_Msk      /* Address-Aligned Beats */
+#define ETH_DMASBMR_FB_Pos                            (0U)
+#define ETH_DMASBMR_FB_Msk                            (0x1UL << ETH_DMASBMR_FB_Pos) /*!< 0x00000001 */
+#define ETH_DMASBMR_FB                                ETH_DMASBMR_FB_Msk       /* Fixed Burst Length */
+
+/* Bit definition for Ethernet DMA Interrupt Status Register */
+#define ETH_DMAISR_MACIS_Pos                          (17U)
+#define ETH_DMAISR_MACIS_Msk                          (0x1UL << ETH_DMAISR_MACIS_Pos) /*!< 0x00020000 */
+#define ETH_DMAISR_MACIS                              ETH_DMAISR_MACIS_Msk     /* MAC Interrupt Status */
+#define ETH_DMAISR_MTLIS_Pos                          (16U)
+#define ETH_DMAISR_MTLIS_Msk                          (0x1UL << ETH_DMAISR_MTLIS_Pos) /*!< 0x00010000 */
+#define ETH_DMAISR_MTLIS                              ETH_DMAISR_MTLIS_Msk     /* MAC Interrupt Status */
+#define ETH_DMAISR_DMACIS_Pos                         (0U)
+#define ETH_DMAISR_DMACIS_Msk                         (0x1UL << ETH_DMAISR_DMACIS_Pos) /*!< 0x00000001 */
+#define ETH_DMAISR_DMACIS                             ETH_DMAISR_DMACIS_Msk    /* DMA Channel Interrupt Status */
+
+/* Bit definition for Ethernet DMA Debug Status Register */
+#define ETH_DMADSR_TPS_Pos                            (12U)
+#define ETH_DMADSR_TPS_Msk                            (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */
+#define ETH_DMADSR_TPS                                ETH_DMADSR_TPS_Msk       /* DMA Channel Transmit Process State */
+#define ETH_DMADSR_TPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Transmit Command issued) */
+#define ETH_DMADSR_TPS_FETCHING_Pos                   (12U)
+#define ETH_DMADSR_TPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */
+#define ETH_DMADSR_TPS_FETCHING                       ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
+#define ETH_DMADSR_TPS_WAITING_Pos                    (13U)
+#define ETH_DMADSR_TPS_WAITING_Msk                    (0x1UL << ETH_DMADSR_TPS_WAITING_Pos) /*!< 0x00002000 */
+#define ETH_DMADSR_TPS_WAITING                        ETH_DMADSR_TPS_WAITING_Msk /* Running (Waiting for status) */
+#define ETH_DMADSR_TPS_READING_Pos                    (12U)
+#define ETH_DMADSR_TPS_READING_Msk                    (0x3UL << ETH_DMADSR_TPS_READING_Pos) /*!< 0x00003000 */
+#define ETH_DMADSR_TPS_READING                        ETH_DMADSR_TPS_READING_Msk /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */
+#define ETH_DMADSR_TPS_TIMESTAMP_WR_Pos               (14U)
+#define ETH_DMADSR_TPS_TIMESTAMP_WR_Msk               (0x1UL << ETH_DMADSR_TPS_TIMESTAMP_WR_Pos) /*!< 0x00004000 */
+#define ETH_DMADSR_TPS_TIMESTAMP_WR                   ETH_DMADSR_TPS_TIMESTAMP_WR_Msk /* Timestamp write state */
+#define ETH_DMADSR_TPS_SUSPENDED_Pos                  (13U)
+#define ETH_DMADSR_TPS_SUSPENDED_Msk                  (0x3UL << ETH_DMADSR_TPS_SUSPENDED_Pos) /*!< 0x00006000 */
+#define ETH_DMADSR_TPS_SUSPENDED                      ETH_DMADSR_TPS_SUSPENDED_Msk /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */
+#define ETH_DMADSR_TPS_CLOSING_Pos                    (12U)
+#define ETH_DMADSR_TPS_CLOSING_Msk                    (0x7UL << ETH_DMADSR_TPS_CLOSING_Pos) /*!< 0x00007000 */
+#define ETH_DMADSR_TPS_CLOSING                        ETH_DMADSR_TPS_CLOSING_Msk /* Running (Closing Tx Descriptor) */
+#define ETH_DMADSR_RPS_Pos                            (8U)
+#define ETH_DMADSR_RPS_Msk                            (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */
+#define ETH_DMADSR_RPS                                ETH_DMADSR_RPS_Msk       /* DMA Channel Receive Process State */
+#define ETH_DMADSR_RPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Receive Command issued) */
+#define ETH_DMADSR_RPS_FETCHING_Pos                   (12U)
+#define ETH_DMADSR_RPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */
+#define ETH_DMADSR_RPS_FETCHING                       ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
+#define ETH_DMADSR_RPS_WAITING_Pos                    (12U)
+#define ETH_DMADSR_RPS_WAITING_Msk                    (0x3UL << ETH_DMADSR_RPS_WAITING_Pos) /*!< 0x00003000 */
+#define ETH_DMADSR_RPS_WAITING                        ETH_DMADSR_RPS_WAITING_Msk /* Running (Waiting for status) */
+#define ETH_DMADSR_RPS_SUSPENDED_Pos                  (14U)
+#define ETH_DMADSR_RPS_SUSPENDED_Msk                  (0x1UL << ETH_DMADSR_RPS_SUSPENDED_Pos) /*!< 0x00004000 */
+#define ETH_DMADSR_RPS_SUSPENDED                      ETH_DMADSR_RPS_SUSPENDED_Msk /* Suspended (Rx Descriptor Unavailable) */
+#define ETH_DMADSR_RPS_CLOSING_Pos                    (12U)
+#define ETH_DMADSR_RPS_CLOSING_Msk                    (0x5UL << ETH_DMADSR_RPS_CLOSING_Pos) /*!< 0x00005000 */
+#define ETH_DMADSR_RPS_CLOSING                        ETH_DMADSR_RPS_CLOSING_Msk /* Running (Closing the Rx Descriptor) */
+#define ETH_DMADSR_RPS_TIMESTAMP_WR_Pos               (13U)
+#define ETH_DMADSR_RPS_TIMESTAMP_WR_Msk               (0x3UL << ETH_DMADSR_RPS_TIMESTAMP_WR_Pos) /*!< 0x00006000 */
+#define ETH_DMADSR_RPS_TIMESTAMP_WR                   ETH_DMADSR_RPS_TIMESTAMP_WR_Msk /* Timestamp write state */
+#define ETH_DMADSR_RPS_TRANSFERRING_Pos               (12U)
+#define ETH_DMADSR_RPS_TRANSFERRING_Msk               (0x7UL << ETH_DMADSR_RPS_TRANSFERRING_Pos) /*!< 0x00007000 */
+#define ETH_DMADSR_RPS_TRANSFERRING                   ETH_DMADSR_RPS_TRANSFERRING_Msk /* Running (Transferring the received packet data from the Rx buffer to the system memory) */
+
+/* Bit definition for Ethernet DMA Channel Control Register */
+#define ETH_DMACCR_DSL_Pos                            (18U)
+#define ETH_DMACCR_DSL_Msk                            (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */
+#define ETH_DMACCR_DSL                                ETH_DMACCR_DSL_Msk       /* Descriptor Skip Length */
+#define ETH_DMACCR_DSL_0BIT                           ((uint32_t)0x00000000)
+#define ETH_DMACCR_DSL_32BIT                          ((uint32_t)0x00040000)
+#define ETH_DMACCR_DSL_64BIT                          ((uint32_t)0x00080000)
+#define ETH_DMACCR_DSL_128BIT                         ((uint32_t)0x00100000)
+#define ETH_DMACCR_8PBL                               ((uint32_t)0x00010000)   /* 8xPBL mode */
+#define ETH_DMACCR_MSS_Pos                            (0U)
+#define ETH_DMACCR_MSS_Msk                            (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */
+#define ETH_DMACCR_MSS                                ETH_DMACCR_MSS_Msk       /* Maximum Segment Size */
+
+/* Bit definition for Ethernet DMA Channel Tx Control Register */
+#define ETH_DMACTCR_TPBL_Pos                          (16U)
+#define ETH_DMACTCR_TPBL_Msk                          (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */
+#define ETH_DMACTCR_TPBL                              ETH_DMACTCR_TPBL_Msk     /* Transmit Programmable Burst Length */
+#define ETH_DMACTCR_TPBL_1PBL                         ((uint32_t)0x00010000)   /* Transmit Programmable Burst Length 1 */
+#define ETH_DMACTCR_TPBL_2PBL                         ((uint32_t)0x00020000)   /* Transmit Programmable Burst Length 2 */
+#define ETH_DMACTCR_TPBL_4PBL                         ((uint32_t)0x00040000)   /* Transmit Programmable Burst Length 4 */
+#define ETH_DMACTCR_TPBL_8PBL                         ((uint32_t)0x00080000)   /* Transmit Programmable Burst Length 8 */
+#define ETH_DMACTCR_TPBL_16PBL                        ((uint32_t)0x00100000)   /* Transmit Programmable Burst Length 16 */
+#define ETH_DMACTCR_TPBL_32PBL                        ((uint32_t)0x00200000)   /* Transmit Programmable Burst Length 32 */
+#define ETH_DMACTCR_TSE_Pos                           (12U)
+#define ETH_DMACTCR_TSE_Msk                           (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */
+#define ETH_DMACTCR_TSE                               ETH_DMACTCR_TSE_Msk      /* TCP Segmentation Enabled */
+#define ETH_DMACTCR_OSP_Pos                           (4U)
+#define ETH_DMACTCR_OSP_Msk                           (0x1UL << ETH_DMACTCR_OSP_Pos) /*!< 0x00000010 */
+#define ETH_DMACTCR_OSP                               ETH_DMACTCR_OSP_Msk      /* Operate on Second Packet */
+#define ETH_DMACTCR_ST_Pos                            (0U)
+#define ETH_DMACTCR_ST_Msk                            (0x1UL << ETH_DMACTCR_ST_Pos) /*!< 0x00000001 */
+#define ETH_DMACTCR_ST                                ETH_DMACTCR_ST_Msk       /* Start or Stop Transmission Command */
+
+/* Bit definition for Ethernet DMA Channel Rx Control Register */
+#define ETH_DMACRCR_RPF_Pos                           (31U)
+#define ETH_DMACRCR_RPF_Msk                           (0x1UL << ETH_DMACRCR_RPF_Pos) /*!< 0x80000000 */
+#define ETH_DMACRCR_RPF                               ETH_DMACRCR_RPF_Msk      /* Rx Packet Flush */
+#define ETH_DMACRCR_RPBL_Pos                          (16U)
+#define ETH_DMACRCR_RPBL_Msk                          (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */
+#define ETH_DMACRCR_RPBL                              ETH_DMACRCR_RPBL_Msk     /* Receive Programmable Burst Length */
+#define ETH_DMACRCR_RPBL_1PBL                         ((uint32_t)0x00010000)   /* Receive Programmable Burst Length 1 */
+#define ETH_DMACRCR_RPBL_2PBL                         ((uint32_t)0x00020000)   /* Receive Programmable Burst Length 2 */
+#define ETH_DMACRCR_RPBL_4PBL                         ((uint32_t)0x00040000)   /* Receive Programmable Burst Length 4 */
+#define ETH_DMACRCR_RPBL_8PBL                         ((uint32_t)0x00080000)   /* Receive Programmable Burst Length 8 */
+#define ETH_DMACRCR_RPBL_16PBL                        ((uint32_t)0x00100000)   /* Receive Programmable Burst Length 16 */
+#define ETH_DMACRCR_RPBL_32PBL                        ((uint32_t)0x00200000)   /* Receive Programmable Burst Length 32 */
+#define ETH_DMACRCR_RBSZ_Pos                          (1U)
+#define ETH_DMACRCR_RBSZ_Msk                          (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */
+#define ETH_DMACRCR_RBSZ                              ETH_DMACRCR_RBSZ_Msk     /* Receive Buffer size */
+#define ETH_DMACRCR_SR_Pos                            (0U)
+#define ETH_DMACRCR_SR_Msk                            (0x1UL << ETH_DMACRCR_SR_Pos) /*!< 0x00000001 */
+#define ETH_DMACRCR_SR                                ETH_DMACRCR_SR_Msk       /* Start or Stop Receive */
+
+/* Bit definition for Ethernet DMA CH Tx Desc List Address Register */
+#define ETH_DMACTDLAR_TDESLA_Pos                      (2U)
+#define ETH_DMACTDLAR_TDESLA_Msk                      (0x3FFFFFFFUL << ETH_DMACTDLAR_TDESLA_Pos) /*!< 0xFFFFFFFC */
+#define ETH_DMACTDLAR_TDESLA                          ETH_DMACTDLAR_TDESLA_Msk /* Start of Transmit List */
+
+/* Bit definition for Ethernet DMA CH Rx Desc List Address Register */
+#define ETH_DMACRDLAR_RDESLA_Pos                      (2U)
+#define ETH_DMACRDLAR_RDESLA_Msk                      (0x3FFFFFFFUL << ETH_DMACRDLAR_RDESLA_Pos) /*!< 0xFFFFFFFC */
+#define ETH_DMACRDLAR_RDESLA                          ETH_DMACRDLAR_RDESLA_Msk /* Start of Receive List */
+
+/* Bit definition for Ethernet DMA CH Tx Desc Tail Pointer Register */
+#define ETH_DMACTDTPR_TDT_Pos                         (2U)
+#define ETH_DMACTDTPR_TDT_Msk                         (0x3FFFFFFFUL << ETH_DMACTDTPR_TDT_Pos) /*!< 0xFFFFFFFC */
+#define ETH_DMACTDTPR_TDT                             ETH_DMACTDTPR_TDT_Msk    /* Transmit Descriptor Tail Pointer */
+
+/* Bit definition for Ethernet DMA CH Rx Desc Tail Pointer Register */
+#define ETH_DMACRDTPR_RDT_Pos                         (2U)
+#define ETH_DMACRDTPR_RDT_Msk                         (0x3FFFFFFFUL << ETH_DMACRDTPR_RDT_Pos) /*!< 0xFFFFFFFC */
+#define ETH_DMACRDTPR_RDT                             ETH_DMACRDTPR_RDT_Msk    /* Receive Descriptor Tail Pointer */
+
+/* Bit definition for Ethernet DMA CH Tx Desc Ring Length Register */
+#define ETH_DMACTDRLR_TDRL_Pos                        (0U)
+#define ETH_DMACTDRLR_TDRL_Msk                        (0x3FFUL << ETH_DMACTDRLR_TDRL_Pos) /*!< 0x000003FF */
+#define ETH_DMACTDRLR_TDRL                            ETH_DMACTDRLR_TDRL_Msk   /* Transmit Descriptor Ring Length */
+
+/* Bit definition for Ethernet DMA CH Rx Desc Ring Length Register */
+#define ETH_DMACRDRLR_RDRL_Pos                        (0U)
+#define ETH_DMACRDRLR_RDRL_Msk                        (0x3FFUL << ETH_DMACRDRLR_RDRL_Pos) /*!< 0x000003FF */
+#define ETH_DMACRDRLR_RDRL                            ETH_DMACRDRLR_RDRL_Msk   /* Receive Descriptor Ring Length */
+
+/* Bit definition for Ethernet DMA Channel Interrupt Enable Register */
+#define ETH_DMACIER_NIE_Pos                           (15U)
+#define ETH_DMACIER_NIE_Msk                           (0x1UL << ETH_DMACIER_NIE_Pos) /*!< 0x00008000 */
+#define ETH_DMACIER_NIE                               ETH_DMACIER_NIE_Msk      /* Normal Interrupt Summary Enable */
+#define ETH_DMACIER_AIE_Pos                           (14U)
+#define ETH_DMACIER_AIE_Msk                           (0x1UL << ETH_DMACIER_AIE_Pos) /*!< 0x00004000 */
+#define ETH_DMACIER_AIE                               ETH_DMACIER_AIE_Msk      /* Abnormal Interrupt Summary Enable */
+#define ETH_DMACIER_CDEE_Pos                          (13U)
+#define ETH_DMACIER_CDEE_Msk                          (0x1UL << ETH_DMACIER_CDEE_Pos) /*!< 0x00002000 */
+#define ETH_DMACIER_CDEE                              ETH_DMACIER_CDEE_Msk     /* Context Descriptor Error Enable */
+#define ETH_DMACIER_FBEE_Pos                          (12U)
+#define ETH_DMACIER_FBEE_Msk                          (0x1UL << ETH_DMACIER_FBEE_Pos) /*!< 0x00001000 */
+#define ETH_DMACIER_FBEE                              ETH_DMACIER_FBEE_Msk     /* Fatal Bus Error Enable */
+#define ETH_DMACIER_ERIE_Pos                          (11U)
+#define ETH_DMACIER_ERIE_Msk                          (0x1UL << ETH_DMACIER_ERIE_Pos) /*!< 0x00000800 */
+#define ETH_DMACIER_ERIE                              ETH_DMACIER_ERIE_Msk     /* Early Receive Interrupt Enable */
+#define ETH_DMACIER_ETIE_Pos                          (10U)
+#define ETH_DMACIER_ETIE_Msk                          (0x1UL << ETH_DMACIER_ETIE_Pos) /*!< 0x00000400 */
+#define ETH_DMACIER_ETIE                              ETH_DMACIER_ETIE_Msk     /* Early Transmit Interrupt Enable */
+#define ETH_DMACIER_RWTE_Pos                          (9U)
+#define ETH_DMACIER_RWTE_Msk                          (0x1UL << ETH_DMACIER_RWTE_Pos) /*!< 0x00000200 */
+#define ETH_DMACIER_RWTE                              ETH_DMACIER_RWTE_Msk     /* Receive Watchdog Timeout Enable */
+#define ETH_DMACIER_RSE_Pos                           (8U)
+#define ETH_DMACIER_RSE_Msk                           (0x1UL << ETH_DMACIER_RSE_Pos) /*!< 0x00000100 */
+#define ETH_DMACIER_RSE                               ETH_DMACIER_RSE_Msk      /* Receive Stopped Enable */
+#define ETH_DMACIER_RBUE_Pos                          (7U)
+#define ETH_DMACIER_RBUE_Msk                          (0x1UL << ETH_DMACIER_RBUE_Pos) /*!< 0x00000080 */
+#define ETH_DMACIER_RBUE                              ETH_DMACIER_RBUE_Msk     /* Receive Buffer Unavailable Enable */
+#define ETH_DMACIER_RIE_Pos                           (6U)
+#define ETH_DMACIER_RIE_Msk                           (0x1UL << ETH_DMACIER_RIE_Pos) /*!< 0x00000040 */
+#define ETH_DMACIER_RIE                               ETH_DMACIER_RIE_Msk      /* Receive Interrupt Enable */
+#define ETH_DMACIER_TBUE_Pos                          (2U)
+#define ETH_DMACIER_TBUE_Msk                          (0x1UL << ETH_DMACIER_TBUE_Pos) /*!< 0x00000004 */
+#define ETH_DMACIER_TBUE                              ETH_DMACIER_TBUE_Msk     /* Transmit Buffer Unavailable Enable */
+#define ETH_DMACIER_TXSE_Pos                          (1U)
+#define ETH_DMACIER_TXSE_Msk                          (0x1UL << ETH_DMACIER_TXSE_Pos) /*!< 0x00000002 */
+#define ETH_DMACIER_TXSE                              ETH_DMACIER_TXSE_Msk     /* Transmit Stopped Enable */
+#define ETH_DMACIER_TIE_Pos                           (0U)
+#define ETH_DMACIER_TIE_Msk                           (0x1UL << ETH_DMACIER_TIE_Pos) /*!< 0x00000001 */
+#define ETH_DMACIER_TIE                               ETH_DMACIER_TIE_Msk      /* Transmit Interrupt Enable */
+
+/* Bit definition for Ethernet DMA Channel Rx Interrupt Watchdog Timer Register */
+#define ETH_DMACRIWTR_RWT_Pos                         (0U)
+#define ETH_DMACRIWTR_RWT_Msk                         (0xFFUL << ETH_DMACRIWTR_RWT_Pos) /*!< 0x000000FF */
+#define ETH_DMACRIWTR_RWT                             ETH_DMACRIWTR_RWT_Msk    /* Receive Interrupt Watchdog Timer Count */
+
+/* Bit definition for Ethernet DMA Channel Current App Tx Desc Register */
+#define ETH_DMACCATDR_CURTDESAPTR_Pos                 (0U)
+#define ETH_DMACCATDR_CURTDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCATDR_CURTDESAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACCATDR_CURTDESAPTR                     ETH_DMACCATDR_CURTDESAPTR_Msk /* Application Transmit Descriptor Address Pointer */
+
+/* Bit definition for Ethernet DMA Channel Current App Rx Desc Register */
+#define ETH_DMACCARDR_CURRDESAPTR_Pos                 (0U)
+#define ETH_DMACCARDR_CURRDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCARDR_CURRDESAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACCARDR_CURRDESAPTR                     ETH_DMACCARDR_CURRDESAPTR_Msk /* Application Receive Descriptor Address Pointer */
+
+/* Bit definition for Ethernet DMA Channel Current App Tx Buffer Register */
+#define ETH_DMACCATBR_CURTBUFAPTR_Pos                 (0U)
+#define ETH_DMACCATBR_CURTBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCATBR_CURTBUFAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACCATBR_CURTBUFAPTR                     ETH_DMACCATBR_CURTBUFAPTR_Msk /* Application Transmit Buffer Address Pointer */
+
+/* Bit definition for Ethernet DMA Channel Current App Rx Buffer Register */
+#define ETH_DMACCARBR_CURRBUFAPTR_Pos                 (0U)
+#define ETH_DMACCARBR_CURRBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCARBR_CURRBUFAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACCARBR_CURRBUFAPTR                     ETH_DMACCARBR_CURRBUFAPTR_Msk /* Application Receive Buffer Address Pointer */
+
+/* Bit definition for Ethernet DMA Channel Status Register */
+#define ETH_DMACSR_REB_Pos                            (19U)
+#define ETH_DMACSR_REB_Msk                            (0x7UL << ETH_DMACSR_REB_Pos) /*!< 0x00380000 */
+#define ETH_DMACSR_REB                                ETH_DMACSR_REB_Msk       /* Rx DMA Error Bits */
+#define ETH_DMACSR_TEB_Pos                            (16U)
+#define ETH_DMACSR_TEB_Msk                            (0x7UL << ETH_DMACSR_TEB_Pos) /*!< 0x00070000 */
+#define ETH_DMACSR_TEB                                ETH_DMACSR_TEB_Msk       /* Tx DMA Error Bits */
+#define ETH_DMACSR_NIS_Pos                            (15U)
+#define ETH_DMACSR_NIS_Msk                            (0x1UL << ETH_DMACSR_NIS_Pos) /*!< 0x00008000 */
+#define ETH_DMACSR_NIS                                ETH_DMACSR_NIS_Msk       /* Normal Interrupt Summary */
+#define ETH_DMACSR_AIS_Pos                            (14U)
+#define ETH_DMACSR_AIS_Msk                            (0x1UL << ETH_DMACSR_AIS_Pos) /*!< 0x00004000 */
+#define ETH_DMACSR_AIS                                ETH_DMACSR_AIS_Msk       /* Abnormal Interrupt Summary */
+#define ETH_DMACSR_CDE_Pos                            (13U)
+#define ETH_DMACSR_CDE_Msk                            (0x1UL << ETH_DMACSR_CDE_Pos) /*!< 0x00002000 */
+#define ETH_DMACSR_CDE                                ETH_DMACSR_CDE_Msk       /* Context Descriptor Error */
+#define ETH_DMACSR_FBE_Pos                            (12U)
+#define ETH_DMACSR_FBE_Msk                            (0x1UL << ETH_DMACSR_FBE_Pos) /*!< 0x00001000 */
+#define ETH_DMACSR_FBE                                ETH_DMACSR_FBE_Msk       /* Fatal Bus Error */
+#define ETH_DMACSR_ERI_Pos                            (11U)
+#define ETH_DMACSR_ERI_Msk                            (0x1UL << ETH_DMACSR_ERI_Pos) /*!< 0x00000800 */
+#define ETH_DMACSR_ERI                                ETH_DMACSR_ERI_Msk       /* Early Receive Interrupt */
+#define ETH_DMACSR_ETI_Pos                            (10U)
+#define ETH_DMACSR_ETI_Msk                            (0x1UL << ETH_DMACSR_ETI_Pos) /*!< 0x00000400 */
+#define ETH_DMACSR_ETI                                ETH_DMACSR_ETI_Msk       /* Early Transmit Interrupt */
+#define ETH_DMACSR_RWT_Pos                            (9U)
+#define ETH_DMACSR_RWT_Msk                            (0x1UL << ETH_DMACSR_RWT_Pos) /*!< 0x00000200 */
+#define ETH_DMACSR_RWT                                ETH_DMACSR_RWT_Msk       /* Receive Watchdog Timeout */
+#define ETH_DMACSR_RPS_Pos                            (8U)
+#define ETH_DMACSR_RPS_Msk                            (0x1UL << ETH_DMACSR_RPS_Pos) /*!< 0x00000100 */
+#define ETH_DMACSR_RPS                                ETH_DMACSR_RPS_Msk       /* Receive Process Stopped */
+#define ETH_DMACSR_RBU_Pos                            (7U)
+#define ETH_DMACSR_RBU_Msk                            (0x1UL << ETH_DMACSR_RBU_Pos) /*!< 0x00000080 */
+#define ETH_DMACSR_RBU                                ETH_DMACSR_RBU_Msk       /* Receive Buffer Unavailable */
+#define ETH_DMACSR_RI_Pos                             (6U)
+#define ETH_DMACSR_RI_Msk                             (0x1UL << ETH_DMACSR_RI_Pos) /*!< 0x00000040 */
+#define ETH_DMACSR_RI                                 ETH_DMACSR_RI_Msk        /* Receive Interrupt */
+#define ETH_DMACSR_TBU_Pos                            (2U)
+#define ETH_DMACSR_TBU_Msk                            (0x1UL << ETH_DMACSR_TBU_Pos) /*!< 0x00000004 */
+#define ETH_DMACSR_TBU                                ETH_DMACSR_TBU_Msk       /* Transmit Buffer Unavailable */
+#define ETH_DMACSR_TPS_Pos                            (1U)
+#define ETH_DMACSR_TPS_Msk                            (0x1UL << ETH_DMACSR_TPS_Pos) /*!< 0x00000002 */
+#define ETH_DMACSR_TPS                                ETH_DMACSR_TPS_Msk       /* Transmit Process Stopped */
+#define ETH_DMACSR_TI_Pos                             (0U)
+#define ETH_DMACSR_TI_Msk                             (0x1UL << ETH_DMACSR_TI_Pos) /*!< 0x00000001 */
+#define ETH_DMACSR_TI                                 ETH_DMACSR_TI_Msk        /* Transmit Interrupt */
+
+/* Bit definition for Ethernet DMA Channel missed frame count register */
+#define ETH_DMACMFCR_MFCO_Pos                         (15U)
+#define ETH_DMACMFCR_MFCO_Msk                         (0x1UL << ETH_DMACMFCR_MFCO_Pos) /*!< 0x00008000 */
+#define ETH_DMACMFCR_MFCO                             ETH_DMACMFCR_MFCO_Msk    /* Overflow status of the MFC Counter */
+#define ETH_DMACMFCR_MFC_Pos                          (0U)
+#define ETH_DMACMFCR_MFC_Msk                          (0x7FFUL << ETH_DMACMFCR_MFC_Pos) /*!< 0x000007FF */
+#define ETH_DMACMFCR_MFC                              ETH_DMACMFCR_MFC_Msk     /* The number of packet counters dropped by the DMA */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             DMA Controller                                 */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for DMA_SxCR register  *****************/
+#define DMA_SxCR_MBURST_Pos      (23U)
+#define DMA_SxCR_MBURST_Msk      (0x3UL << DMA_SxCR_MBURST_Pos)                /*!< 0x01800000 */
+#define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk                           /*!< Memory burst transfer configuration */
+#define DMA_SxCR_MBURST_0        (0x1UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */
+#define DMA_SxCR_MBURST_1        (0x2UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */
+#define DMA_SxCR_PBURST_Pos      (21U)
+#define DMA_SxCR_PBURST_Msk      (0x3UL << DMA_SxCR_PBURST_Pos)                /*!< 0x00600000 */
+#define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk                           /*!< Peripheral burst transfer configuration */
+#define DMA_SxCR_PBURST_0        (0x1UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */
+#define DMA_SxCR_PBURST_1        (0x2UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */
+#define DMA_SxCR_TRBUFF_Pos      (20U)
+#define DMA_SxCR_TRBUFF_Msk      (0x1UL << DMA_SxCR_TRBUFF_Pos)                 /*!< 0x00100000 */
+#define DMA_SxCR_TRBUFF          DMA_SxCR_TRBUFF_Msk                            /*!< bufferable transfers enabled/disable */
+#define DMA_SxCR_CT_Pos          (19U)
+#define DMA_SxCR_CT_Msk          (0x1UL << DMA_SxCR_CT_Pos)                    /*!< 0x00080000 */
+#define DMA_SxCR_CT              DMA_SxCR_CT_Msk                               /*!< Current target (only in double buffer mode) */
+#define DMA_SxCR_DBM_Pos         (18U)
+#define DMA_SxCR_DBM_Msk         (0x1UL << DMA_SxCR_DBM_Pos)                   /*!< 0x00040000 */
+#define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk                              /*!< Double buffer mode */
+#define DMA_SxCR_PL_Pos          (16U)
+#define DMA_SxCR_PL_Msk          (0x3UL << DMA_SxCR_PL_Pos)                    /*!< 0x00030000 */
+#define DMA_SxCR_PL              DMA_SxCR_PL_Msk                               /*!< Priority level */
+#define DMA_SxCR_PL_0            (0x1UL << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */
+#define DMA_SxCR_PL_1            (0x2UL << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */
+#define DMA_SxCR_PINCOS_Pos      (15U)
+#define DMA_SxCR_PINCOS_Msk      (0x1UL << DMA_SxCR_PINCOS_Pos)                /*!< 0x00008000 */
+#define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk                           /*!< Peripheral increment offset size */
+#define DMA_SxCR_MSIZE_Pos       (13U)
+#define DMA_SxCR_MSIZE_Msk       (0x3UL << DMA_SxCR_MSIZE_Pos)                 /*!< 0x00006000 */
+#define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk                            /*!< Memory data size */
+#define DMA_SxCR_MSIZE_0         (0x1UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */
+#define DMA_SxCR_MSIZE_1         (0x2UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */
+#define DMA_SxCR_PSIZE_Pos       (11U)
+#define DMA_SxCR_PSIZE_Msk       (0x3UL << DMA_SxCR_PSIZE_Pos)                 /*!< 0x00001800 */
+#define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk                            /*< Peripheral data size */
+#define DMA_SxCR_PSIZE_0         (0x1UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */
+#define DMA_SxCR_PSIZE_1         (0x2UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */
+#define DMA_SxCR_MINC_Pos        (10U)
+#define DMA_SxCR_MINC_Msk        (0x1UL << DMA_SxCR_MINC_Pos)                  /*!< 0x00000400 */
+#define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk                             /*!< Memory increment mode */
+#define DMA_SxCR_PINC_Pos        (9U)
+#define DMA_SxCR_PINC_Msk        (0x1UL << DMA_SxCR_PINC_Pos)                  /*!< 0x00000200 */
+#define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk                             /*!< Peripheral increment mode */
+#define DMA_SxCR_CIRC_Pos        (8U)
+#define DMA_SxCR_CIRC_Msk        (0x1UL << DMA_SxCR_CIRC_Pos)                  /*!< 0x00000100 */
+#define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk                             /*!< Circular mode */
+#define DMA_SxCR_DIR_Pos         (6U)
+#define DMA_SxCR_DIR_Msk         (0x3UL << DMA_SxCR_DIR_Pos)                   /*!< 0x000000C0 */
+#define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk                              /*!< Data transfer direction */
+#define DMA_SxCR_DIR_0           (0x1UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */
+#define DMA_SxCR_DIR_1           (0x2UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */
+#define DMA_SxCR_PFCTRL_Pos      (5U)
+#define DMA_SxCR_PFCTRL_Msk      (0x1UL << DMA_SxCR_PFCTRL_Pos)                /*!< 0x00000020 */
+#define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk                           /*!< Peripheral flow controller */
+#define DMA_SxCR_TCIE_Pos        (4U)
+#define DMA_SxCR_TCIE_Msk        (0x1UL << DMA_SxCR_TCIE_Pos)                  /*!< 0x00000010 */
+#define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk                             /*!< Transfer complete interrupt enable */
+#define DMA_SxCR_HTIE_Pos        (3U)
+#define DMA_SxCR_HTIE_Msk        (0x1UL << DMA_SxCR_HTIE_Pos)                  /*!< 0x00000008 */
+#define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk                             /*!< Half transfer interrupt enable */
+#define DMA_SxCR_TEIE_Pos        (2U)
+#define DMA_SxCR_TEIE_Msk        (0x1UL << DMA_SxCR_TEIE_Pos)                  /*!< 0x00000004 */
+#define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk                             /*!< Transfer error interrupt enable */
+#define DMA_SxCR_DMEIE_Pos       (1U)
+#define DMA_SxCR_DMEIE_Msk       (0x1UL << DMA_SxCR_DMEIE_Pos)                 /*!< 0x00000002 */
+#define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk                            /*!< Direct mode error interrupt enable */
+#define DMA_SxCR_EN_Pos          (0U)
+#define DMA_SxCR_EN_Msk          (0x1UL << DMA_SxCR_EN_Pos)                    /*!< 0x00000001 */
+#define DMA_SxCR_EN              DMA_SxCR_EN_Msk                               /*!< Stream enable / flag stream ready when read low */
+
+/********************  Bits definition for DMA_SxCNDTR register  **************/
+#define DMA_SxNDT_Pos            (0U)
+#define DMA_SxNDT_Msk            (0xFFFFUL << DMA_SxNDT_Pos)                   /*!< 0x0000FFFF */
+#define DMA_SxNDT                DMA_SxNDT_Msk                                 /*!< Number of data items to transfer */
+#define DMA_SxNDT_0              (0x0001UL << DMA_SxNDT_Pos)                    /*!< 0x00000001 */
+#define DMA_SxNDT_1              (0x0002UL << DMA_SxNDT_Pos)                    /*!< 0x00000002 */
+#define DMA_SxNDT_2              (0x0004UL << DMA_SxNDT_Pos)                    /*!< 0x00000004 */
+#define DMA_SxNDT_3              (0x0008UL << DMA_SxNDT_Pos)                    /*!< 0x00000008 */
+#define DMA_SxNDT_4              (0x0010UL << DMA_SxNDT_Pos)                    /*!< 0x00000010 */
+#define DMA_SxNDT_5              (0x0020UL << DMA_SxNDT_Pos)                    /*!< 0x00000020 */
+#define DMA_SxNDT_6              (0x0040UL << DMA_SxNDT_Pos)                    /*!< 0x00000040 */
+#define DMA_SxNDT_7              (0x0080UL << DMA_SxNDT_Pos)                    /*!< 0x00000080 */
+#define DMA_SxNDT_8              (0x0100UL << DMA_SxNDT_Pos)                    /*!< 0x00000100 */
+#define DMA_SxNDT_9              (0x0200UL << DMA_SxNDT_Pos)                    /*!< 0x00000200 */
+#define DMA_SxNDT_10             (0x0400UL << DMA_SxNDT_Pos)                    /*!< 0x00000400 */
+#define DMA_SxNDT_11             (0x0800UL << DMA_SxNDT_Pos)                    /*!< 0x00000800 */
+#define DMA_SxNDT_12             (0x1000UL << DMA_SxNDT_Pos)                    /*!< 0x00001000 */
+#define DMA_SxNDT_13             (0x2000UL << DMA_SxNDT_Pos)                    /*!< 0x00002000 */
+#define DMA_SxNDT_14             (0x4000UL << DMA_SxNDT_Pos)                    /*!< 0x00004000 */
+#define DMA_SxNDT_15             (0x8000UL << DMA_SxNDT_Pos)                    /*!< 0x00008000 */
+
+/********************  Bits definition for DMA_SxFCR register  ****************/
+#define DMA_SxFCR_FEIE_Pos       (7U)
+#define DMA_SxFCR_FEIE_Msk       (0x1UL << DMA_SxFCR_FEIE_Pos)                 /*!< 0x00000080 */
+#define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk                            /*!< FIFO error interrupt enable */
+#define DMA_SxFCR_FS_Pos         (3U)
+#define DMA_SxFCR_FS_Msk         (0x7UL << DMA_SxFCR_FS_Pos)                   /*!< 0x00000038 */
+#define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk                              /*!< FIFO status */
+#define DMA_SxFCR_FS_0           (0x1UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */
+#define DMA_SxFCR_FS_1           (0x2UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */
+#define DMA_SxFCR_FS_2           (0x4UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */
+#define DMA_SxFCR_DMDIS_Pos      (2U)
+#define DMA_SxFCR_DMDIS_Msk      (0x1UL << DMA_SxFCR_DMDIS_Pos)                /*!< 0x00000004 */
+#define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk                           /*!< Direct mode disable */
+#define DMA_SxFCR_FTH_Pos        (0U)
+#define DMA_SxFCR_FTH_Msk        (0x3UL << DMA_SxFCR_FTH_Pos)                  /*!< 0x00000003 */
+#define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk                             /*!< FIFO threshold selection */
+#define DMA_SxFCR_FTH_0          (0x1UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */
+#define DMA_SxFCR_FTH_1          (0x2UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */
+
+/********************  Bits definition for DMA_LISR register  *****************/
+#define DMA_LISR_TCIF3_Pos       (27U)
+#define DMA_LISR_TCIF3_Msk       (0x1UL << DMA_LISR_TCIF3_Pos)                 /*!< 0x08000000 */
+#define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk                            /*!<  Stream 3 transfer complete interrupt flag */
+#define DMA_LISR_HTIF3_Pos       (26U)
+#define DMA_LISR_HTIF3_Msk       (0x1UL << DMA_LISR_HTIF3_Pos)                 /*!< 0x04000000 */
+#define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk                            /*!<  Stream 3 half transfer interrupt flag */
+#define DMA_LISR_TEIF3_Pos       (25U)
+#define DMA_LISR_TEIF3_Msk       (0x1UL << DMA_LISR_TEIF3_Pos)                 /*!< 0x02000000 */
+#define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk                            /*!<  Stream 3 transfer error interrupt flag */
+#define DMA_LISR_DMEIF3_Pos      (24U)
+#define DMA_LISR_DMEIF3_Msk      (0x1UL << DMA_LISR_DMEIF3_Pos)                /*!< 0x01000000 */
+#define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk                           /*!<  Stream 3 direct mode error interrupt flag */
+#define DMA_LISR_FEIF3_Pos       (22U)
+#define DMA_LISR_FEIF3_Msk       (0x1UL << DMA_LISR_FEIF3_Pos)                 /*!< 0x00400000 */
+#define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk                            /*!<  Stream 3 FIFO error interrupt flag */
+#define DMA_LISR_TCIF2_Pos       (21U)
+#define DMA_LISR_TCIF2_Msk       (0x1UL << DMA_LISR_TCIF2_Pos)                 /*!< 0x00200000 */
+#define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk                            /*!<  Stream 2 transfer complete interrupt flag */
+#define DMA_LISR_HTIF2_Pos       (20U)
+#define DMA_LISR_HTIF2_Msk       (0x1UL << DMA_LISR_HTIF2_Pos)                 /*!< 0x00100000 */
+#define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk                            /*!<  Stream 2 half transfer interrupt flag */
+#define DMA_LISR_TEIF2_Pos       (19U)
+#define DMA_LISR_TEIF2_Msk       (0x1UL << DMA_LISR_TEIF2_Pos)                 /*!< 0x00080000 */
+#define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk                            /*!<  Stream 2 transfer error interrupt flag */
+#define DMA_LISR_DMEIF2_Pos      (18U)
+#define DMA_LISR_DMEIF2_Msk      (0x1UL << DMA_LISR_DMEIF2_Pos)                /*!< 0x00040000 */
+#define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk                           /*!<  Stream 2 direct mode error interrupt flag */
+#define DMA_LISR_FEIF2_Pos       (16U)
+#define DMA_LISR_FEIF2_Msk       (0x1UL << DMA_LISR_FEIF2_Pos)                 /*!< 0x00010000 */
+#define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk                            /*!<  Stream 2 FIFO error interrupt flag */
+#define DMA_LISR_TCIF1_Pos       (11U)
+#define DMA_LISR_TCIF1_Msk       (0x1UL << DMA_LISR_TCIF1_Pos)                 /*!< 0x00000800 */
+#define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk                            /*!<  Stream 1 transfer complete interrupt flag */
+#define DMA_LISR_HTIF1_Pos       (10U)
+#define DMA_LISR_HTIF1_Msk       (0x1UL << DMA_LISR_HTIF1_Pos)                 /*!< 0x00000400 */
+#define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk                            /*!<  Stream 1 half transfer interrupt flag */
+#define DMA_LISR_TEIF1_Pos       (9U)
+#define DMA_LISR_TEIF1_Msk       (0x1UL << DMA_LISR_TEIF1_Pos)                 /*!< 0x00000200 */
+#define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk                            /*!<  Stream 1 transfer error interrupt flag */
+#define DMA_LISR_DMEIF1_Pos      (8U)
+#define DMA_LISR_DMEIF1_Msk      (0x1UL << DMA_LISR_DMEIF1_Pos)                /*!< 0x00000100 */
+#define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk                           /*!<  Stream 1 direct mode error interrupt flag */
+#define DMA_LISR_FEIF1_Pos       (6U)
+#define DMA_LISR_FEIF1_Msk       (0x1UL << DMA_LISR_FEIF1_Pos)                 /*!< 0x00000040 */
+#define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk                            /*!<  Stream 1 FIFO error interrupt flag */
+#define DMA_LISR_TCIF0_Pos       (5U)
+#define DMA_LISR_TCIF0_Msk       (0x1UL << DMA_LISR_TCIF0_Pos)                 /*!< 0x00000020 */
+#define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk                            /*!<  Stream 0 transfer complete interrupt flag */
+#define DMA_LISR_HTIF0_Pos       (4U)
+#define DMA_LISR_HTIF0_Msk       (0x1UL << DMA_LISR_HTIF0_Pos)                 /*!< 0x00000010 */
+#define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk                            /*!<  Stream 0 half transfer interrupt flag */
+#define DMA_LISR_TEIF0_Pos       (3U)
+#define DMA_LISR_TEIF0_Msk       (0x1UL << DMA_LISR_TEIF0_Pos)                 /*!< 0x00000008 */
+#define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk                            /*!<  Stream 0 transfer error interrupt flag */
+#define DMA_LISR_DMEIF0_Pos      (2U)
+#define DMA_LISR_DMEIF0_Msk      (0x1UL << DMA_LISR_DMEIF0_Pos)                /*!< 0x00000004 */
+#define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk                           /*!<  Stream 0 direct mode error interrupt flag */
+#define DMA_LISR_FEIF0_Pos       (0U)
+#define DMA_LISR_FEIF0_Msk       (0x1UL << DMA_LISR_FEIF0_Pos)                 /*!< 0x00000001 */
+#define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk                            /*!<  Stream 0 FIFO error interrupt flag */
+
+/********************  Bits definition for DMA_HISR register  *****************/
+#define DMA_HISR_TCIF7_Pos       (27U)
+#define DMA_HISR_TCIF7_Msk       (0x1UL << DMA_HISR_TCIF7_Pos)                 /*!< 0x08000000 */
+#define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk                            /*!<  Stream 7 transfer complete interrupt flag */
+#define DMA_HISR_HTIF7_Pos       (26U)
+#define DMA_HISR_HTIF7_Msk       (0x1UL << DMA_HISR_HTIF7_Pos)                 /*!< 0x04000000 */
+#define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk                            /*!<  Stream 7 half transfer interrupt flag */
+#define DMA_HISR_TEIF7_Pos       (25U)
+#define DMA_HISR_TEIF7_Msk       (0x1UL << DMA_HISR_TEIF7_Pos)                 /*!< 0x02000000 */
+#define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk                            /*!<  Stream 7 transfer error interrupt flag */
+#define DMA_HISR_DMEIF7_Pos      (24U)
+#define DMA_HISR_DMEIF7_Msk      (0x1UL << DMA_HISR_DMEIF7_Pos)                /*!< 0x01000000 */
+#define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk                           /*!<  Stream 7 direct mode error interrupt flag */
+#define DMA_HISR_FEIF7_Pos       (22U)
+#define DMA_HISR_FEIF7_Msk       (0x1UL << DMA_HISR_FEIF7_Pos)                 /*!< 0x00400000 */
+#define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk                            /*!<  Stream 7 FIFO error interrupt flag */
+#define DMA_HISR_TCIF6_Pos       (21U)
+#define DMA_HISR_TCIF6_Msk       (0x1UL << DMA_HISR_TCIF6_Pos)                 /*!< 0x00200000 */
+#define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk                            /*!<  Stream 6 transfer complete interrupt flag */
+#define DMA_HISR_HTIF6_Pos       (20U)
+#define DMA_HISR_HTIF6_Msk       (0x1UL << DMA_HISR_HTIF6_Pos)                 /*!< 0x00100000 */
+#define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk                            /*!<  Stream 6 half transfer interrupt flag */
+#define DMA_HISR_TEIF6_Pos       (19U)
+#define DMA_HISR_TEIF6_Msk       (0x1UL << DMA_HISR_TEIF6_Pos)                 /*!< 0x00080000 */
+#define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk                            /*!<  Stream 6 transfer error interrupt flag */
+#define DMA_HISR_DMEIF6_Pos      (18U)
+#define DMA_HISR_DMEIF6_Msk      (0x1UL << DMA_HISR_DMEIF6_Pos)                /*!< 0x00040000 */
+#define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk                           /*!<  Stream 6 direct mode error interrupt flag */
+#define DMA_HISR_FEIF6_Pos       (16U)
+#define DMA_HISR_FEIF6_Msk       (0x1UL << DMA_HISR_FEIF6_Pos)                 /*!< 0x00010000 */
+#define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk                            /*!<  Stream 6 FIFO error interrupt flag */
+#define DMA_HISR_TCIF5_Pos       (11U)
+#define DMA_HISR_TCIF5_Msk       (0x1UL << DMA_HISR_TCIF5_Pos)                 /*!< 0x00000800 */
+#define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk                            /*!<  Stream 5 transfer complete interrupt flag */
+#define DMA_HISR_HTIF5_Pos       (10U)
+#define DMA_HISR_HTIF5_Msk       (0x1UL << DMA_HISR_HTIF5_Pos)                 /*!< 0x00000400 */
+#define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk                            /*!<  Stream 5 half transfer interrupt flag */
+#define DMA_HISR_TEIF5_Pos       (9U)
+#define DMA_HISR_TEIF5_Msk       (0x1UL << DMA_HISR_TEIF5_Pos)                 /*!< 0x00000200 */
+#define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk                            /*!<  Stream 5 transfer error interrupt flag */
+#define DMA_HISR_DMEIF5_Pos      (8U)
+#define DMA_HISR_DMEIF5_Msk      (0x1UL << DMA_HISR_DMEIF5_Pos)                /*!< 0x00000100 */
+#define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk                           /*!<  Stream 5 direct mode error interrupt flag */
+#define DMA_HISR_FEIF5_Pos       (6U)
+#define DMA_HISR_FEIF5_Msk       (0x1UL << DMA_HISR_FEIF5_Pos)                 /*!< 0x00000040 */
+#define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk                            /*!<  Stream 5 FIFO error interrupt flag */
+#define DMA_HISR_TCIF4_Pos       (5U)
+#define DMA_HISR_TCIF4_Msk       (0x1UL << DMA_HISR_TCIF4_Pos)                 /*!< 0x00000020 */
+#define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk                            /*!<  Stream 4 transfer complete interrupt flag */
+#define DMA_HISR_HTIF4_Pos       (4U)
+#define DMA_HISR_HTIF4_Msk       (0x1UL << DMA_HISR_HTIF4_Pos)                 /*!< 0x00000010 */
+#define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk                            /*!<  Stream 4 half transfer interrupt flag */
+#define DMA_HISR_TEIF4_Pos       (3U)
+#define DMA_HISR_TEIF4_Msk       (0x1UL << DMA_HISR_TEIF4_Pos)                 /*!< 0x00000008 */
+#define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk                            /*!<  Stream 4 transfer error interrupt flag */
+#define DMA_HISR_DMEIF4_Pos      (2U)
+#define DMA_HISR_DMEIF4_Msk      (0x1UL << DMA_HISR_DMEIF4_Pos)                /*!< 0x00000004 */
+#define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk                           /*!<  Stream 4 direct mode error interrupt flag */
+#define DMA_HISR_FEIF4_Pos       (0U)
+#define DMA_HISR_FEIF4_Msk       (0x1UL << DMA_HISR_FEIF4_Pos)                 /*!< 0x00000001 */
+#define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk                            /*!<  Stream 4 FIFO error interrupt flag */
+
+/********************  Bits definition for DMA_LIFCR register  ****************/
+#define DMA_LIFCR_CTCIF3_Pos     (27U)
+#define DMA_LIFCR_CTCIF3_Msk     (0x1UL << DMA_LIFCR_CTCIF3_Pos)               /*!< 0x08000000 */
+#define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk                          /*!<  Stream 3 clear transfer complete interrupt flag */
+#define DMA_LIFCR_CHTIF3_Pos     (26U)
+#define DMA_LIFCR_CHTIF3_Msk     (0x1UL << DMA_LIFCR_CHTIF3_Pos)               /*!< 0x04000000 */
+#define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk                          /*!<  Stream 3 clear half transfer interrupt flag */
+#define DMA_LIFCR_CTEIF3_Pos     (25U)
+#define DMA_LIFCR_CTEIF3_Msk     (0x1UL << DMA_LIFCR_CTEIF3_Pos)               /*!< 0x02000000 */
+#define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk                          /*!<  Stream 3 clear transfer error interrupt flag */
+#define DMA_LIFCR_CDMEIF3_Pos    (24U)
+#define DMA_LIFCR_CDMEIF3_Msk    (0x1UL << DMA_LIFCR_CDMEIF3_Pos)              /*!< 0x01000000 */
+#define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk                         /*!<  Stream 3 clear direct mode error interrupt flag */
+#define DMA_LIFCR_CFEIF3_Pos     (22U)
+#define DMA_LIFCR_CFEIF3_Msk     (0x1UL << DMA_LIFCR_CFEIF3_Pos)               /*!< 0x00400000 */
+#define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk                          /*!<  Stream 3 clear FIFO error interrupt flag */
+#define DMA_LIFCR_CTCIF2_Pos     (21U)
+#define DMA_LIFCR_CTCIF2_Msk     (0x1UL << DMA_LIFCR_CTCIF2_Pos)               /*!< 0x00200000 */
+#define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk                          /*!<  Stream 2 clear transfer complete interrupt flag */
+#define DMA_LIFCR_CHTIF2_Pos     (20U)
+#define DMA_LIFCR_CHTIF2_Msk     (0x1UL << DMA_LIFCR_CHTIF2_Pos)               /*!< 0x00100000 */
+#define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk                          /*!<  Stream 2 clear half transfer interrupt flag */
+#define DMA_LIFCR_CTEIF2_Pos     (19U)
+#define DMA_LIFCR_CTEIF2_Msk     (0x1UL << DMA_LIFCR_CTEIF2_Pos)               /*!< 0x00080000 */
+#define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk                          /*!<  Stream 2 clear transfer error interrupt flag */
+#define DMA_LIFCR_CDMEIF2_Pos    (18U)
+#define DMA_LIFCR_CDMEIF2_Msk    (0x1UL << DMA_LIFCR_CDMEIF2_Pos)              /*!< 0x00040000 */
+#define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk                         /*!<  Stream 2 clear direct mode error interrupt flag */
+#define DMA_LIFCR_CFEIF2_Pos     (16U)
+#define DMA_LIFCR_CFEIF2_Msk     (0x1UL << DMA_LIFCR_CFEIF2_Pos)               /*!< 0x00010000 */
+#define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk                          /*!<  Stream 2 clear FIFO error interrupt flag */
+#define DMA_LIFCR_CTCIF1_Pos     (11U)
+#define DMA_LIFCR_CTCIF1_Msk     (0x1UL << DMA_LIFCR_CTCIF1_Pos)               /*!< 0x00000800 */
+#define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk                          /*!<  Stream 1 clear transfer complete interrupt flag */
+#define DMA_LIFCR_CHTIF1_Pos     (10U)
+#define DMA_LIFCR_CHTIF1_Msk     (0x1UL << DMA_LIFCR_CHTIF1_Pos)               /*!< 0x00000400 */
+#define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk                          /*!<  Stream 1 clear half transfer interrupt flag */
+#define DMA_LIFCR_CTEIF1_Pos     (9U)
+#define DMA_LIFCR_CTEIF1_Msk     (0x1UL << DMA_LIFCR_CTEIF1_Pos)               /*!< 0x00000200 */
+#define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk                          /*!<  Stream 1 clear transfer error interrupt flag */
+#define DMA_LIFCR_CDMEIF1_Pos    (8U)
+#define DMA_LIFCR_CDMEIF1_Msk    (0x1UL << DMA_LIFCR_CDMEIF1_Pos)              /*!< 0x00000100 */
+#define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk                         /*!<  Stream 1 clear direct mode error interrupt flag */
+#define DMA_LIFCR_CFEIF1_Pos     (6U)
+#define DMA_LIFCR_CFEIF1_Msk     (0x1UL << DMA_LIFCR_CFEIF1_Pos)               /*!< 0x00000040 */
+#define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk                          /*!<  Stream 1 clear FIFO error interrupt flag */
+#define DMA_LIFCR_CTCIF0_Pos     (5U)
+#define DMA_LIFCR_CTCIF0_Msk     (0x1UL << DMA_LIFCR_CTCIF0_Pos)               /*!< 0x00000020 */
+#define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk                          /*!<  Stream 0 clear transfer complete interrupt flag */
+#define DMA_LIFCR_CHTIF0_Pos     (4U)
+#define DMA_LIFCR_CHTIF0_Msk     (0x1UL << DMA_LIFCR_CHTIF0_Pos)               /*!< 0x00000010 */
+#define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk                          /*!<  Stream 0 clear half transfer interrupt flag */
+#define DMA_LIFCR_CTEIF0_Pos     (3U)
+#define DMA_LIFCR_CTEIF0_Msk     (0x1UL << DMA_LIFCR_CTEIF0_Pos)               /*!< 0x00000008 */
+#define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk                          /*!<  Stream 0 clear transfer error interrupt flag */
+#define DMA_LIFCR_CDMEIF0_Pos    (2U)
+#define DMA_LIFCR_CDMEIF0_Msk    (0x1UL << DMA_LIFCR_CDMEIF0_Pos)              /*!< 0x00000004 */
+#define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk                         /*!<  Stream 0 clear direct mode error interrupt flag */
+#define DMA_LIFCR_CFEIF0_Pos     (0U)
+#define DMA_LIFCR_CFEIF0_Msk     (0x1UL << DMA_LIFCR_CFEIF0_Pos)               /*!< 0x00000001 */
+#define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk                          /*!<  Stream 0 clear FIFO error interrupt flag */
+
+/********************  Bits definition for DMA_HIFCR  register  ****************/
+#define DMA_HIFCR_CTCIF7_Pos     (27U)
+#define DMA_HIFCR_CTCIF7_Msk     (0x1UL << DMA_HIFCR_CTCIF7_Pos)               /*!< 0x08000000 */
+#define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk                          /*!<  Stream 7 clear transfer complete interrupt flag */
+#define DMA_HIFCR_CHTIF7_Pos     (26U)
+#define DMA_HIFCR_CHTIF7_Msk     (0x1UL << DMA_HIFCR_CHTIF7_Pos)               /*!< 0x04000000 */
+#define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk                          /*!<  Stream 7 clear half transfer interrupt flag */
+#define DMA_HIFCR_CTEIF7_Pos     (25U)
+#define DMA_HIFCR_CTEIF7_Msk     (0x1UL << DMA_HIFCR_CTEIF7_Pos)               /*!< 0x02000000 */
+#define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk                          /*!<  Stream 7 clear transfer error interrupt flag */
+#define DMA_HIFCR_CDMEIF7_Pos    (24U)
+#define DMA_HIFCR_CDMEIF7_Msk    (0x1UL << DMA_HIFCR_CDMEIF7_Pos)              /*!< 0x01000000 */
+#define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk                         /*!<  Stream 7 clear direct mode error interrupt flag */
+#define DMA_HIFCR_CFEIF7_Pos     (22U)
+#define DMA_HIFCR_CFEIF7_Msk     (0x1UL << DMA_HIFCR_CFEIF7_Pos)               /*!< 0x00400000 */
+#define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk                          /*!<  Stream 7 clear FIFO error interrupt flag */
+#define DMA_HIFCR_CTCIF6_Pos     (21U)
+#define DMA_HIFCR_CTCIF6_Msk     (0x1UL << DMA_HIFCR_CTCIF6_Pos)               /*!< 0x00200000 */
+#define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk                          /*!<  Stream 6 clear transfer complete interrupt flag */
+#define DMA_HIFCR_CHTIF6_Pos     (20U)
+#define DMA_HIFCR_CHTIF6_Msk     (0x1UL << DMA_HIFCR_CHTIF6_Pos)               /*!< 0x00100000 */
+#define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk                          /*!<  Stream 6 clear half transfer interrupt flag */
+#define DMA_HIFCR_CTEIF6_Pos     (19U)
+#define DMA_HIFCR_CTEIF6_Msk     (0x1UL << DMA_HIFCR_CTEIF6_Pos)               /*!< 0x00080000 */
+#define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk                          /*!<  Stream 6 clear transfer error interrupt flag */
+#define DMA_HIFCR_CDMEIF6_Pos    (18U)
+#define DMA_HIFCR_CDMEIF6_Msk    (0x1UL << DMA_HIFCR_CDMEIF6_Pos)              /*!< 0x00040000 */
+#define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk                         /*!<  Stream 6 clear direct mode error interrupt flag */
+#define DMA_HIFCR_CFEIF6_Pos     (16U)
+#define DMA_HIFCR_CFEIF6_Msk     (0x1UL << DMA_HIFCR_CFEIF6_Pos)               /*!< 0x00010000 */
+#define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk                          /*!<  Stream 6 clear FIFO error interrupt flag */
+#define DMA_HIFCR_CTCIF5_Pos     (11U)
+#define DMA_HIFCR_CTCIF5_Msk     (0x1UL << DMA_HIFCR_CTCIF5_Pos)               /*!< 0x00000800 */
+#define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk                          /*!<  Stream 5 clear transfer complete interrupt flag */
+#define DMA_HIFCR_CHTIF5_Pos     (10U)
+#define DMA_HIFCR_CHTIF5_Msk     (0x1UL << DMA_HIFCR_CHTIF5_Pos)               /*!< 0x00000400 */
+#define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk                          /*!<  Stream 5 clear half transfer interrupt flag */
+#define DMA_HIFCR_CTEIF5_Pos     (9U)
+#define DMA_HIFCR_CTEIF5_Msk     (0x1UL << DMA_HIFCR_CTEIF5_Pos)               /*!< 0x00000200 */
+#define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk                          /*!<  Stream 5 clear transfer error interrupt flag */
+#define DMA_HIFCR_CDMEIF5_Pos    (8U)
+#define DMA_HIFCR_CDMEIF5_Msk    (0x1UL << DMA_HIFCR_CDMEIF5_Pos)              /*!< 0x00000100 */
+#define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk                         /*!<  Stream 5 clear direct mode error interrupt flag */
+#define DMA_HIFCR_CFEIF5_Pos     (6U)
+#define DMA_HIFCR_CFEIF5_Msk     (0x1UL << DMA_HIFCR_CFEIF5_Pos)               /*!< 0x00000040 */
+#define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk                          /*!<  Stream 5 clear FIFO error interrupt flag */
+#define DMA_HIFCR_CTCIF4_Pos     (5U)
+#define DMA_HIFCR_CTCIF4_Msk     (0x1UL << DMA_HIFCR_CTCIF4_Pos)               /*!< 0x00000020 */
+#define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk                          /*!<  Stream 4 clear transfer complete interrupt flag */
+#define DMA_HIFCR_CHTIF4_Pos     (4U)
+#define DMA_HIFCR_CHTIF4_Msk     (0x1UL << DMA_HIFCR_CHTIF4_Pos)               /*!< 0x00000010 */
+#define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk                          /*!<  Stream 4 clear half transfer interrupt flag */
+#define DMA_HIFCR_CTEIF4_Pos     (3U)
+#define DMA_HIFCR_CTEIF4_Msk     (0x1UL << DMA_HIFCR_CTEIF4_Pos)               /*!< 0x00000008 */
+#define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk                          /*!<  Stream 4 clear transfer error interrupt flag */
+#define DMA_HIFCR_CDMEIF4_Pos    (2U)
+#define DMA_HIFCR_CDMEIF4_Msk    (0x1UL << DMA_HIFCR_CDMEIF4_Pos)              /*!< 0x00000004 */
+#define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk                         /*!<  Stream 4 clear direct mode error interrupt flag */
+#define DMA_HIFCR_CFEIF4_Pos     (0U)
+#define DMA_HIFCR_CFEIF4_Msk     (0x1UL << DMA_HIFCR_CFEIF4_Pos)               /*!< 0x00000001 */
+#define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk                          /*!<  Stream 4 clear FIFO error interrupt flag */
+
+/******************  Bit definition for DMA_SxPAR register  ********************/
+#define DMA_SxPAR_PA_Pos         (0U)
+#define DMA_SxPAR_PA_Msk         (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)            /*!< 0xFFFFFFFF */
+#define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_SxM0AR register  ********************/
+#define DMA_SxM0AR_M0A_Pos       (0U)
+#define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)          /*!< 0xFFFFFFFF */
+#define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory 0 Address */
+
+/******************  Bit definition for DMA_SxM1AR register  ********************/
+#define DMA_SxM1AR_M1A_Pos       (0U)
+#define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)          /*!< 0xFFFFFFFF */
+#define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory 1 Address */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             DMAMUX Controller                              */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for DMAMUX_CxCR register  **************/
+#define DMAMUX_CxCR_DMAREQ_ID_Pos      (0U)
+#define DMAMUX_CxCR_DMAREQ_ID_Msk      (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)   /*!< 0x000000FF */
+#define DMAMUX_CxCR_DMAREQ_ID          DMAMUX_CxCR_DMAREQ_ID_Msk               /*!<  DMA request identification */
+#define DMAMUX_CxCR_DMAREQ_ID_0        (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000001 */
+#define DMAMUX_CxCR_DMAREQ_ID_1        (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000002 */
+#define DMAMUX_CxCR_DMAREQ_ID_2        (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000004 */
+#define DMAMUX_CxCR_DMAREQ_ID_3        (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000008 */
+#define DMAMUX_CxCR_DMAREQ_ID_4        (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000010 */
+#define DMAMUX_CxCR_DMAREQ_ID_5        (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000020 */
+#define DMAMUX_CxCR_DMAREQ_ID_6        (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000040 */
+#define DMAMUX_CxCR_DMAREQ_ID_7        (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000080 */
+#define DMAMUX_CxCR_SOIE_Pos           (8U)
+#define DMAMUX_CxCR_SOIE_Msk           (0x1UL << DMAMUX_CxCR_SOIE_Pos)         /*!< 0x00000100 */
+#define DMAMUX_CxCR_SOIE               DMAMUX_CxCR_SOIE_Msk                    /*!<  Synchronization overrun interrupt enable */
+#define DMAMUX_CxCR_EGE_Pos            (9U)
+#define DMAMUX_CxCR_EGE_Msk            (0x1UL << DMAMUX_CxCR_EGE_Pos)          /*!< 0x00000200 */
+#define DMAMUX_CxCR_EGE                DMAMUX_CxCR_EGE_Msk                     /*!<  Event generation enable */
+#define DMAMUX_CxCR_SE_Pos             (16U)
+#define DMAMUX_CxCR_SE_Msk             (0x1UL << DMAMUX_CxCR_SE_Pos)           /*!< 0x00010000 */
+#define DMAMUX_CxCR_SE                 DMAMUX_CxCR_SE_Msk                      /*!<  Synchronization enable */
+#define DMAMUX_CxCR_SPOL_Pos           (17U)
+#define DMAMUX_CxCR_SPOL_Msk           (0x3UL << DMAMUX_CxCR_SPOL_Pos)         /*!< 0x00060000 */
+#define DMAMUX_CxCR_SPOL               DMAMUX_CxCR_SPOL_Msk                    /*!<  Synchronization polarity */
+#define DMAMUX_CxCR_SPOL_0             (0x1UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00020000 */
+#define DMAMUX_CxCR_SPOL_1             (0x2UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00040000 */
+#define DMAMUX_CxCR_NBREQ_Pos          (19U)
+#define DMAMUX_CxCR_NBREQ_Msk          (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)       /*!< 0x00F80000 */
+#define DMAMUX_CxCR_NBREQ              DMAMUX_CxCR_NBREQ_Msk                   /*!<  Number of DMA requests minus 1 to forward */
+#define DMAMUX_CxCR_NBREQ_0            (0x01UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00080000 */
+#define DMAMUX_CxCR_NBREQ_1            (0x02UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00100000 */
+#define DMAMUX_CxCR_NBREQ_2            (0x04UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00200000 */
+#define DMAMUX_CxCR_NBREQ_3            (0x08UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00400000 */
+#define DMAMUX_CxCR_NBREQ_4            (0x10UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00800000 */
+#define DMAMUX_CxCR_SYNC_ID_Pos        (24U)
+#define DMAMUX_CxCR_SYNC_ID_Msk        (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)     /*!< 0x1F000000 */
+#define DMAMUX_CxCR_SYNC_ID            DMAMUX_CxCR_SYNC_ID_Msk                 /*!<  Synchronization identification */
+#define DMAMUX_CxCR_SYNC_ID_0          (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x01000000 */
+#define DMAMUX_CxCR_SYNC_ID_1          (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x02000000 */
+#define DMAMUX_CxCR_SYNC_ID_2          (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x04000000 */
+#define DMAMUX_CxCR_SYNC_ID_3          (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x08000000 */
+#define DMAMUX_CxCR_SYNC_ID_4          (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x10000000 */
+
+/********************  Bits definition for DMAMUX_CSR register  **************/
+#define DMAMUX_CSR_SOF0_Pos            (0U)
+#define DMAMUX_CSR_SOF0_Msk            (0x1UL << DMAMUX_CSR_SOF0_Pos)          /*!< 0x00000001 */
+#define DMAMUX_CSR_SOF0                DMAMUX_CSR_SOF0_Msk                     /*!< Channel 0 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF1_Pos            (1U)
+#define DMAMUX_CSR_SOF1_Msk            (0x1UL << DMAMUX_CSR_SOF1_Pos)          /*!< 0x00000002 */
+#define DMAMUX_CSR_SOF1                DMAMUX_CSR_SOF1_Msk                     /*!< Channel 1 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF2_Pos            (2U)
+#define DMAMUX_CSR_SOF2_Msk            (0x1UL << DMAMUX_CSR_SOF2_Pos)          /*!< 0x00000004 */
+#define DMAMUX_CSR_SOF2                DMAMUX_CSR_SOF2_Msk                     /*!< Channel 2 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF3_Pos            (3U)
+#define DMAMUX_CSR_SOF3_Msk            (0x1UL << DMAMUX_CSR_SOF3_Pos)          /*!< 0x00000008 */
+#define DMAMUX_CSR_SOF3                DMAMUX_CSR_SOF3_Msk                     /*!< Channel 3 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF4_Pos            (4U)
+#define DMAMUX_CSR_SOF4_Msk            (0x1UL << DMAMUX_CSR_SOF4_Pos)          /*!< 0x00000010 */
+#define DMAMUX_CSR_SOF4                DMAMUX_CSR_SOF4_Msk                     /*!< Channel 4 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF5_Pos            (5U)
+#define DMAMUX_CSR_SOF5_Msk            (0x1UL << DMAMUX_CSR_SOF5_Pos)          /*!< 0x00000020 */
+#define DMAMUX_CSR_SOF5                DMAMUX_CSR_SOF5_Msk                     /*!< Channel 5 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF6_Pos            (6U)
+#define DMAMUX_CSR_SOF6_Msk            (0x1UL << DMAMUX_CSR_SOF6_Pos)          /*!< 0x00000040 */
+#define DMAMUX_CSR_SOF6                DMAMUX_CSR_SOF6_Msk                     /*!< Channel 6 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF7_Pos            (7U)
+#define DMAMUX_CSR_SOF7_Msk            (0x1UL << DMAMUX_CSR_SOF7_Pos)          /*!< 0x00000080 */
+#define DMAMUX_CSR_SOF7                DMAMUX_CSR_SOF7_Msk                     /*!< Channel 7 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF8_Pos            (8U)
+#define DMAMUX_CSR_SOF8_Msk            (0x1UL << DMAMUX_CSR_SOF8_Pos)          /*!< 0x00000100 */
+#define DMAMUX_CSR_SOF8                DMAMUX_CSR_SOF8_Msk                     /*!< Channel 8 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF9_Pos            (9U)
+#define DMAMUX_CSR_SOF9_Msk            (0x1UL << DMAMUX_CSR_SOF9_Pos)          /*!< 0x00000200 */
+#define DMAMUX_CSR_SOF9                DMAMUX_CSR_SOF9_Msk                     /*!< Channel 9 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF10_Pos           (10U)
+#define DMAMUX_CSR_SOF10_Msk           (0x1UL << DMAMUX_CSR_SOF10_Pos)         /*!< 0x00000400 */
+#define DMAMUX_CSR_SOF10               DMAMUX_CSR_SOF10_Msk                    /*!< Channel 10 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF11_Pos           (11U)
+#define DMAMUX_CSR_SOF11_Msk           (0x1UL << DMAMUX_CSR_SOF11_Pos)         /*!< 0x00000800 */
+#define DMAMUX_CSR_SOF11               DMAMUX_CSR_SOF11_Msk                    /*!< Channel 11 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF12_Pos           (12U)
+#define DMAMUX_CSR_SOF12_Msk           (0x1UL << DMAMUX_CSR_SOF12_Pos)         /*!< 0x00001000 */
+#define DMAMUX_CSR_SOF12               DMAMUX_CSR_SOF12_Msk                    /*!< Channel 12 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF13_Pos           (13U)
+#define DMAMUX_CSR_SOF13_Msk           (0x1UL << DMAMUX_CSR_SOF13_Pos)         /*!< 0x00002000 */
+#define DMAMUX_CSR_SOF13               DMAMUX_CSR_SOF13_Msk                    /*!< Channel 13 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF14_Pos           (14U)
+#define DMAMUX_CSR_SOF14_Msk           (0x1UL << DMAMUX_CSR_SOF14_Pos)         /*!< 0x00004000 */
+#define DMAMUX_CSR_SOF14               DMAMUX_CSR_SOF14_Msk                    /*!< Channel 14 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF15_Pos           (15U)
+#define DMAMUX_CSR_SOF15_Msk           (0x1UL << DMAMUX_CSR_SOF15_Pos)         /*!< 0x00008000 */
+#define DMAMUX_CSR_SOF15               DMAMUX_CSR_SOF15_Msk                    /*!< Channel 15 Synchronization overrun event flag */
+
+/********************  Bits definition for DMAMUX_CFR register  **************/
+#define DMAMUX_CFR_CSOF0_Pos           (0U)
+#define DMAMUX_CFR_CSOF0_Msk           (0x1UL << DMAMUX_CFR_CSOF0_Pos)         /*!< 0x00000001 */
+#define DMAMUX_CFR_CSOF0               DMAMUX_CFR_CSOF0_Msk                    /*!< Channel 0 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF1_Pos           (1U)
+#define DMAMUX_CFR_CSOF1_Msk           (0x1UL << DMAMUX_CFR_CSOF1_Pos)         /*!< 0x00000002 */
+#define DMAMUX_CFR_CSOF1               DMAMUX_CFR_CSOF1_Msk                    /*!< Channel 1 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF2_Pos           (2U)
+#define DMAMUX_CFR_CSOF2_Msk           (0x1UL << DMAMUX_CFR_CSOF2_Pos)         /*!< 0x00000004 */
+#define DMAMUX_CFR_CSOF2               DMAMUX_CFR_CSOF2_Msk                    /*!< Channel 2 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF3_Pos           (3U)
+#define DMAMUX_CFR_CSOF3_Msk           (0x1UL << DMAMUX_CFR_CSOF3_Pos)         /*!< 0x00000008 */
+#define DMAMUX_CFR_CSOF3               DMAMUX_CFR_CSOF3_Msk                    /*!< Channel 3 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF4_Pos           (4U)
+#define DMAMUX_CFR_CSOF4_Msk           (0x1UL << DMAMUX_CFR_CSOF4_Pos)         /*!< 0x00000010 */
+#define DMAMUX_CFR_CSOF4               DMAMUX_CFR_CSOF4_Msk                    /*!< Channel 4 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF5_Pos           (5U)
+#define DMAMUX_CFR_CSOF5_Msk           (0x1UL << DMAMUX_CFR_CSOF5_Pos)         /*!< 0x00000020 */
+#define DMAMUX_CFR_CSOF5               DMAMUX_CFR_CSOF5_Msk                    /*!< Channel 5 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF6_Pos           (6U)
+#define DMAMUX_CFR_CSOF6_Msk           (0x1UL << DMAMUX_CFR_CSOF6_Pos)         /*!< 0x00000040 */
+#define DMAMUX_CFR_CSOF6               DMAMUX_CFR_CSOF6_Msk                    /*!< Channel 6 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF7_Pos           (7U)
+#define DMAMUX_CFR_CSOF7_Msk           (0x1UL << DMAMUX_CFR_CSOF7_Pos)         /*!< 0x00000080 */
+#define DMAMUX_CFR_CSOF7               DMAMUX_CFR_CSOF7_Msk                    /*!< Channel 7 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF8_Pos           (8U)
+#define DMAMUX_CFR_CSOF8_Msk           (0x1UL << DMAMUX_CFR_CSOF8_Pos)         /*!< 0x00000100 */
+#define DMAMUX_CFR_CSOF8               DMAMUX_CFR_CSOF8_Msk                    /*!< Channel 8 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF9_Pos           (9U)
+#define DMAMUX_CFR_CSOF9_Msk           (0x1UL << DMAMUX_CFR_CSOF9_Pos)         /*!< 0x00000200 */
+#define DMAMUX_CFR_CSOF9               DMAMUX_CFR_CSOF9_Msk                    /*!< Channel 9 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF10_Pos          (10U)
+#define DMAMUX_CFR_CSOF10_Msk          (0x1UL << DMAMUX_CFR_CSOF10_Pos)        /*!< 0x00000400 */
+#define DMAMUX_CFR_CSOF10              DMAMUX_CFR_CSOF10_Msk                   /*!< Channel 10 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF11_Pos          (11U)
+#define DMAMUX_CFR_CSOF11_Msk          (0x1UL << DMAMUX_CFR_CSOF11_Pos)        /*!< 0x00000800 */
+#define DMAMUX_CFR_CSOF11              DMAMUX_CFR_CSOF11_Msk                   /*!< Channel 11 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF12_Pos          (12U)
+#define DMAMUX_CFR_CSOF12_Msk          (0x1UL << DMAMUX_CFR_CSOF12_Pos)        /*!< 0x00001000 */
+#define DMAMUX_CFR_CSOF12              DMAMUX_CFR_CSOF12_Msk                   /*!< Channel 12 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF13_Pos          (13U)
+#define DMAMUX_CFR_CSOF13_Msk          (0x1UL << DMAMUX_CFR_CSOF13_Pos)        /*!< 0x00002000 */
+#define DMAMUX_CFR_CSOF13              DMAMUX_CFR_CSOF13_Msk                   /*!< Channel 13 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF14_Pos          (14U)
+#define DMAMUX_CFR_CSOF14_Msk          (0x1UL << DMAMUX_CFR_CSOF14_Pos)        /*!< 0x00004000 */
+#define DMAMUX_CFR_CSOF14              DMAMUX_CFR_CSOF14_Msk                   /*!< Channel 14 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF15_Pos          (15U)
+#define DMAMUX_CFR_CSOF15_Msk          (0x1UL << DMAMUX_CFR_CSOF15_Pos)        /*!< 0x00008000 */
+#define DMAMUX_CFR_CSOF15              DMAMUX_CFR_CSOF15_Msk                   /*!< Channel 15 Clear synchronization overrun event flag */
+
+/********************  Bits definition for DMAMUX_RGxCR register  ************/
+#define DMAMUX_RGxCR_SIG_ID_Pos        (0U)
+#define DMAMUX_RGxCR_SIG_ID_Msk        (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)     /*!< 0x0000001F */
+#define DMAMUX_RGxCR_SIG_ID            DMAMUX_RGxCR_SIG_ID_Msk                 /*!< Signal identification */
+#define DMAMUX_RGxCR_SIG_ID_0          (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000001 */
+#define DMAMUX_RGxCR_SIG_ID_1          (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000002 */
+#define DMAMUX_RGxCR_SIG_ID_2          (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000004 */
+#define DMAMUX_RGxCR_SIG_ID_3          (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000008 */
+#define DMAMUX_RGxCR_SIG_ID_4          (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000010 */
+#define DMAMUX_RGxCR_OIE_Pos           (8U)
+#define DMAMUX_RGxCR_OIE_Msk           (0x1UL << DMAMUX_RGxCR_OIE_Pos)         /*!< 0x00000100 */
+#define DMAMUX_RGxCR_OIE               DMAMUX_RGxCR_OIE_Msk                    /*!< Trigger overrun interrupt enable */
+#define DMAMUX_RGxCR_GE_Pos            (16U)
+#define DMAMUX_RGxCR_GE_Msk            (0x1UL << DMAMUX_RGxCR_GE_Pos)          /*!< 0x00010000 */
+#define DMAMUX_RGxCR_GE                DMAMUX_RGxCR_GE_Msk                     /*!< DMA request generator enable */
+#define DMAMUX_RGxCR_GPOL_Pos          (17U)
+#define DMAMUX_RGxCR_GPOL_Msk          (0x3UL << DMAMUX_RGxCR_GPOL_Pos)        /*!< 0x00060000 */
+#define DMAMUX_RGxCR_GPOL              DMAMUX_RGxCR_GPOL_Msk                   /*!< DMA request generator trigger polarity */
+#define DMAMUX_RGxCR_GPOL_0            (0x1UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00020000 */
+#define DMAMUX_RGxCR_GPOL_1            (0x2UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00040000 */
+#define DMAMUX_RGxCR_GNBREQ_Pos        (19U)
+#define DMAMUX_RGxCR_GNBREQ_Msk        (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)     /*!< 0x00F80000 */
+#define DMAMUX_RGxCR_GNBREQ            DMAMUX_RGxCR_GNBREQ_Msk                 /*!< Number of DMA requests to be generated */
+#define DMAMUX_RGxCR_GNBREQ_0          (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00080000 */
+#define DMAMUX_RGxCR_GNBREQ_1          (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00100000 */
+#define DMAMUX_RGxCR_GNBREQ_2          (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00200000 */
+#define DMAMUX_RGxCR_GNBREQ_3          (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00400000 */
+#define DMAMUX_RGxCR_GNBREQ_4          (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00800000 */
+
+/********************  Bits definition for DMAMUX_RGSR register  **************/
+#define DMAMUX_RGSR_OF0_Pos            (0U)
+#define DMAMUX_RGSR_OF0_Msk            (0x1UL << DMAMUX_RGSR_OF0_Pos)          /*!< 0x00000001 */
+#define DMAMUX_RGSR_OF0                DMAMUX_RGSR_OF0_Msk                     /*!< Request generator channel 0 Trigger overrun event flag */
+#define DMAMUX_RGSR_OF1_Pos            (1U)
+#define DMAMUX_RGSR_OF1_Msk            (0x1UL << DMAMUX_RGSR_OF1_Pos)          /*!< 0x00000002 */
+#define DMAMUX_RGSR_OF1                DMAMUX_RGSR_OF1_Msk                     /*!< Request generator channel 1 Trigger overrun event flag */
+#define DMAMUX_RGSR_OF2_Pos            (2U)
+#define DMAMUX_RGSR_OF2_Msk            (0x1UL << DMAMUX_RGSR_OF2_Pos)          /*!< 0x00000004 */
+#define DMAMUX_RGSR_OF2                DMAMUX_RGSR_OF2_Msk                     /*!< Request generator channel 2 Trigger overrun event flag */
+#define DMAMUX_RGSR_OF3_Pos            (3U)
+#define DMAMUX_RGSR_OF3_Msk            (0x1UL << DMAMUX_RGSR_OF3_Pos)          /*!< 0x00000008 */
+#define DMAMUX_RGSR_OF3                DMAMUX_RGSR_OF3_Msk                     /*!< Request generator channel 3 Trigger overrun event flag */
+#define DMAMUX_RGSR_OF4_Pos            (4U)
+#define DMAMUX_RGSR_OF4_Msk            (0x1UL << DMAMUX_RGSR_OF4_Pos)          /*!< 0x00000010 */
+#define DMAMUX_RGSR_OF4                DMAMUX_RGSR_OF4_Msk                     /*!< Request generator channel 4 Trigger overrun event flag */
+#define DMAMUX_RGSR_OF5_Pos            (5U)
+#define DMAMUX_RGSR_OF5_Msk            (0x1UL << DMAMUX_RGSR_OF5_Pos)          /*!< 0x00000020 */
+#define DMAMUX_RGSR_OF5                DMAMUX_RGSR_OF5_Msk                     /*!< Request generator channel 5 Trigger overrun event flag */
+#define DMAMUX_RGSR_OF6_Pos            (6U)
+#define DMAMUX_RGSR_OF6_Msk            (0x1UL << DMAMUX_RGSR_OF6_Pos)          /*!< 0x00000040 */
+#define DMAMUX_RGSR_OF6                DMAMUX_RGSR_OF6_Msk                     /*!< Request generator channel 6 Trigger overrun event flag */
+#define DMAMUX_RGSR_OF7_Pos            (7U)
+#define DMAMUX_RGSR_OF7_Msk            (0x1UL << DMAMUX_RGSR_OF7_Pos)          /*!< 0x00000080 */
+#define DMAMUX_RGSR_OF7                DMAMUX_RGSR_OF7_Msk                     /*!< Request generator channel 7 Trigger overrun event flag */
+
+/********************  Bits definition for DMAMUX_RGCFR register  **************/
+#define DMAMUX_RGCFR_COF0_Pos          (0U)
+#define DMAMUX_RGCFR_COF0_Msk          (0x1UL << DMAMUX_RGCFR_COF0_Pos)        /*!< 0x00000001 */
+#define DMAMUX_RGCFR_COF0              DMAMUX_RGCFR_COF0_Msk                   /*!< Request generator channel 0 Clear trigger overrun event flag */
+#define DMAMUX_RGCFR_COF1_Pos          (1U)
+#define DMAMUX_RGCFR_COF1_Msk          (0x1UL << DMAMUX_RGCFR_COF1_Pos)        /*!< 0x00000002 */
+#define DMAMUX_RGCFR_COF1              DMAMUX_RGCFR_COF1_Msk                   /*!< Request generator channel 1 Clear trigger overrun event flag */
+#define DMAMUX_RGCFR_COF2_Pos          (2U)
+#define DMAMUX_RGCFR_COF2_Msk          (0x1UL << DMAMUX_RGCFR_COF2_Pos)        /*!< 0x00000004 */
+#define DMAMUX_RGCFR_COF2              DMAMUX_RGCFR_COF2_Msk                   /*!< Request generator channel 2 Clear trigger overrun event flag */
+#define DMAMUX_RGCFR_COF3_Pos          (3U)
+#define DMAMUX_RGCFR_COF3_Msk          (0x1UL << DMAMUX_RGCFR_COF3_Pos)        /*!< 0x00000008 */
+#define DMAMUX_RGCFR_COF3              DMAMUX_RGCFR_COF3_Msk                   /*!< Request generator channel 3 Clear trigger overrun event flag */
+#define DMAMUX_RGCFR_COF4_Pos          (4U)
+#define DMAMUX_RGCFR_COF4_Msk          (0x1UL << DMAMUX_RGCFR_COF4_Pos)        /*!< 0x00000010 */
+#define DMAMUX_RGCFR_COF4              DMAMUX_RGCFR_COF4_Msk                   /*!< Request generator channel 4 Clear trigger overrun event flag */
+#define DMAMUX_RGCFR_COF5_Pos          (5U)
+#define DMAMUX_RGCFR_COF5_Msk          (0x1UL << DMAMUX_RGCFR_COF5_Pos)        /*!< 0x00000020 */
+#define DMAMUX_RGCFR_COF5              DMAMUX_RGCFR_COF5_Msk                   /*!< Request generator channel 5 Clear trigger overrun event flag */
+#define DMAMUX_RGCFR_COF6_Pos          (6U)
+#define DMAMUX_RGCFR_COF6_Msk          (0x1UL << DMAMUX_RGCFR_COF6_Pos)        /*!< 0x00000040 */
+#define DMAMUX_RGCFR_COF6              DMAMUX_RGCFR_COF6_Msk                   /*!< Request generator channel 6 Clear trigger overrun event flag */
+#define DMAMUX_RGCFR_COF7_Pos          (7U)
+#define DMAMUX_RGCFR_COF7_Msk          (0x1UL << DMAMUX_RGCFR_COF7_Pos)        /*!< 0x00000080 */
+#define DMAMUX_RGCFR_COF7              DMAMUX_RGCFR_COF7_Msk                   /*!< Request generator channel 7 Clear trigger overrun event flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         AHB Master DMA2D Controller (DMA2D)                */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for DMA2D_CR register  ******************/
+
+#define DMA2D_CR_START_Pos         (0U)
+#define DMA2D_CR_START_Msk         (0x1UL << DMA2D_CR_START_Pos)               /*!< 0x00000001 */
+#define DMA2D_CR_START             DMA2D_CR_START_Msk                          /*!< Start transfer                          */
+#define DMA2D_CR_SUSP_Pos          (1U)
+#define DMA2D_CR_SUSP_Msk          (0x1UL << DMA2D_CR_SUSP_Pos)                /*!< 0x00000002 */
+#define DMA2D_CR_SUSP              DMA2D_CR_SUSP_Msk                           /*!< Suspend transfer                        */
+#define DMA2D_CR_ABORT_Pos         (2U)
+#define DMA2D_CR_ABORT_Msk         (0x1UL << DMA2D_CR_ABORT_Pos)               /*!< 0x00000004 */
+#define DMA2D_CR_ABORT             DMA2D_CR_ABORT_Msk                          /*!< Abort transfer                          */
+#define DMA2D_CR_LOM_Pos           (6U)
+#define DMA2D_CR_LOM_Msk           (0x1UL << DMA2D_CR_LOM_Pos)                 /*!< 0x00000040 */
+#define DMA2D_CR_LOM               DMA2D_CR_LOM_Msk                            /*!< Line Offset Mode                         */
+#define DMA2D_CR_TEIE_Pos          (8U)
+#define DMA2D_CR_TEIE_Msk          (0x1UL << DMA2D_CR_TEIE_Pos)                /*!< 0x00000100 */
+#define DMA2D_CR_TEIE              DMA2D_CR_TEIE_Msk                           /*!< Transfer Error Interrupt Enable         */
+#define DMA2D_CR_TCIE_Pos          (9U)
+#define DMA2D_CR_TCIE_Msk          (0x1UL << DMA2D_CR_TCIE_Pos)                /*!< 0x00000200 */
+#define DMA2D_CR_TCIE              DMA2D_CR_TCIE_Msk                           /*!< Transfer Complete Interrupt Enable      */
+#define DMA2D_CR_TWIE_Pos          (10U)
+#define DMA2D_CR_TWIE_Msk          (0x1UL << DMA2D_CR_TWIE_Pos)                /*!< 0x00000400 */
+#define DMA2D_CR_TWIE              DMA2D_CR_TWIE_Msk                           /*!< Transfer Watermark Interrupt Enable     */
+#define DMA2D_CR_CAEIE_Pos         (11U)
+#define DMA2D_CR_CAEIE_Msk         (0x1UL << DMA2D_CR_CAEIE_Pos)               /*!< 0x00000800 */
+#define DMA2D_CR_CAEIE             DMA2D_CR_CAEIE_Msk                          /*!< CLUT Access Error Interrupt Enable      */
+#define DMA2D_CR_CTCIE_Pos         (12U)
+#define DMA2D_CR_CTCIE_Msk         (0x1UL << DMA2D_CR_CTCIE_Pos)               /*!< 0x00001000 */
+#define DMA2D_CR_CTCIE             DMA2D_CR_CTCIE_Msk                          /*!< CLUT Transfer Complete Interrupt Enable */
+#define DMA2D_CR_CEIE_Pos          (13U)
+#define DMA2D_CR_CEIE_Msk          (0x1UL << DMA2D_CR_CEIE_Pos)                /*!< 0x00002000 */
+#define DMA2D_CR_CEIE              DMA2D_CR_CEIE_Msk                           /*!< Configuration Error Interrupt Enable    */
+#define DMA2D_CR_MODE_Pos          (16U)
+#define DMA2D_CR_MODE_Msk          (0x7UL << DMA2D_CR_MODE_Pos)                /*!< 0x00070000 */
+#define DMA2D_CR_MODE              DMA2D_CR_MODE_Msk                           /*!< DMA2D Mode[2:0]                         */
+#define DMA2D_CR_MODE_0            (0x1UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00010000 */
+#define DMA2D_CR_MODE_1            (0x2UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00020000 */
+#define DMA2D_CR_MODE_2            (0x4UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00040000 */
+
+/********************  Bit definition for DMA2D_ISR register  *****************/
+
+#define DMA2D_ISR_TEIF_Pos         (0U)
+#define DMA2D_ISR_TEIF_Msk         (0x1UL << DMA2D_ISR_TEIF_Pos)               /*!< 0x00000001 */
+#define DMA2D_ISR_TEIF             DMA2D_ISR_TEIF_Msk                          /*!< Transfer Error Interrupt Flag         */
+#define DMA2D_ISR_TCIF_Pos         (1U)
+#define DMA2D_ISR_TCIF_Msk         (0x1UL << DMA2D_ISR_TCIF_Pos)               /*!< 0x00000002 */
+#define DMA2D_ISR_TCIF             DMA2D_ISR_TCIF_Msk                          /*!< Transfer Complete Interrupt Flag      */
+#define DMA2D_ISR_TWIF_Pos         (2U)
+#define DMA2D_ISR_TWIF_Msk         (0x1UL << DMA2D_ISR_TWIF_Pos)               /*!< 0x00000004 */
+#define DMA2D_ISR_TWIF             DMA2D_ISR_TWIF_Msk                          /*!< Transfer Watermark Interrupt Flag     */
+#define DMA2D_ISR_CAEIF_Pos        (3U)
+#define DMA2D_ISR_CAEIF_Msk        (0x1UL << DMA2D_ISR_CAEIF_Pos)              /*!< 0x00000008 */
+#define DMA2D_ISR_CAEIF            DMA2D_ISR_CAEIF_Msk                         /*!< CLUT Access Error Interrupt Flag      */
+#define DMA2D_ISR_CTCIF_Pos        (4U)
+#define DMA2D_ISR_CTCIF_Msk        (0x1UL << DMA2D_ISR_CTCIF_Pos)              /*!< 0x00000010 */
+#define DMA2D_ISR_CTCIF            DMA2D_ISR_CTCIF_Msk                         /*!< CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_CEIF_Pos         (5U)
+#define DMA2D_ISR_CEIF_Msk         (0x1UL << DMA2D_ISR_CEIF_Pos)               /*!< 0x00000020 */
+#define DMA2D_ISR_CEIF             DMA2D_ISR_CEIF_Msk                          /*!< Configuration Error Interrupt Flag    */
+
+/********************  Bit definition for DMA2D_IFCR register  ****************/
+
+#define DMA2D_IFCR_CTEIF_Pos       (0U)
+#define DMA2D_IFCR_CTEIF_Msk       (0x1UL << DMA2D_IFCR_CTEIF_Pos)             /*!< 0x00000001 */
+#define DMA2D_IFCR_CTEIF           DMA2D_IFCR_CTEIF_Msk                        /*!< Clears Transfer Error Interrupt Flag         */
+#define DMA2D_IFCR_CTCIF_Pos       (1U)
+#define DMA2D_IFCR_CTCIF_Msk       (0x1UL << DMA2D_IFCR_CTCIF_Pos)             /*!< 0x00000002 */
+#define DMA2D_IFCR_CTCIF           DMA2D_IFCR_CTCIF_Msk                        /*!< Clears Transfer Complete Interrupt Flag      */
+#define DMA2D_IFCR_CTWIF_Pos       (2U)
+#define DMA2D_IFCR_CTWIF_Msk       (0x1UL << DMA2D_IFCR_CTWIF_Pos)             /*!< 0x00000004 */
+#define DMA2D_IFCR_CTWIF           DMA2D_IFCR_CTWIF_Msk                        /*!< Clears Transfer Watermark Interrupt Flag     */
+#define DMA2D_IFCR_CAECIF_Pos      (3U)
+#define DMA2D_IFCR_CAECIF_Msk      (0x1UL << DMA2D_IFCR_CAECIF_Pos)            /*!< 0x00000008 */
+#define DMA2D_IFCR_CAECIF          DMA2D_IFCR_CAECIF_Msk                       /*!< Clears CLUT Access Error Interrupt Flag      */
+#define DMA2D_IFCR_CCTCIF_Pos      (4U)
+#define DMA2D_IFCR_CCTCIF_Msk      (0x1UL << DMA2D_IFCR_CCTCIF_Pos)            /*!< 0x00000010 */
+#define DMA2D_IFCR_CCTCIF          DMA2D_IFCR_CCTCIF_Msk                       /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CCEIF_Pos       (5U)
+#define DMA2D_IFCR_CCEIF_Msk       (0x1UL << DMA2D_IFCR_CCEIF_Pos)             /*!< 0x00000020 */
+#define DMA2D_IFCR_CCEIF           DMA2D_IFCR_CCEIF_Msk                        /*!< Clears Configuration Error Interrupt Flag    */
+
+/********************  Bit definition for DMA2D_FGMAR register  ***************/
+
+#define DMA2D_FGMAR_MA_Pos         (0U)
+#define DMA2D_FGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)        /*!< 0xFFFFFFFF */
+#define DMA2D_FGMAR_MA             DMA2D_FGMAR_MA_Msk                          /*!< Foreground Memory Address */
+
+/********************  Bit definition for DMA2D_FGOR register  ****************/
+
+#define DMA2D_FGOR_LO_Pos          (0U)
+#define DMA2D_FGOR_LO_Msk          (0xFFFFUL << DMA2D_FGOR_LO_Pos)             /*!< 0x0000FFFF */
+#define DMA2D_FGOR_LO              DMA2D_FGOR_LO_Msk                           /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_BGMAR register  ***************/
+
+#define DMA2D_BGMAR_MA_Pos         (0U)
+#define DMA2D_BGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)        /*!< 0xFFFFFFFF */
+#define DMA2D_BGMAR_MA             DMA2D_BGMAR_MA_Msk                          /*!< Background Memory Address */
+
+/********************  Bit definition for DMA2D_BGOR register  ****************/
+
+#define DMA2D_BGOR_LO_Pos          (0U)
+#define DMA2D_BGOR_LO_Msk          (0xFFFFUL << DMA2D_BGOR_LO_Pos)             /*!< 0x0000FFFF */
+#define DMA2D_BGOR_LO              DMA2D_BGOR_LO_Msk                           /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_FGPFCCR register  *************/
+
+#define DMA2D_FGPFCCR_CM_Pos       (0U)
+#define DMA2D_FGPFCCR_CM_Msk       (0xFUL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x0000000F */
+#define DMA2D_FGPFCCR_CM           DMA2D_FGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */
+#define DMA2D_FGPFCCR_CM_0         (0x1UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000001 */
+#define DMA2D_FGPFCCR_CM_1         (0x2UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000002 */
+#define DMA2D_FGPFCCR_CM_2         (0x4UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000004 */
+#define DMA2D_FGPFCCR_CM_3         (0x8UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000008 */
+#define DMA2D_FGPFCCR_CCM_Pos      (4U)
+#define DMA2D_FGPFCCR_CCM_Msk      (0x1UL << DMA2D_FGPFCCR_CCM_Pos)            /*!< 0x00000010 */
+#define DMA2D_FGPFCCR_CCM          DMA2D_FGPFCCR_CCM_Msk                       /*!< CLUT Color mode */
+#define DMA2D_FGPFCCR_START_Pos    (5U)
+#define DMA2D_FGPFCCR_START_Msk    (0x1UL << DMA2D_FGPFCCR_START_Pos)          /*!< 0x00000020 */
+#define DMA2D_FGPFCCR_START        DMA2D_FGPFCCR_START_Msk                     /*!< Start */
+#define DMA2D_FGPFCCR_CS_Pos       (8U)
+#define DMA2D_FGPFCCR_CS_Msk       (0xFFUL << DMA2D_FGPFCCR_CS_Pos)            /*!< 0x0000FF00 */
+#define DMA2D_FGPFCCR_CS           DMA2D_FGPFCCR_CS_Msk                        /*!< CLUT size */
+#define DMA2D_FGPFCCR_AM_Pos       (16U)
+#define DMA2D_FGPFCCR_AM_Msk       (0x3UL << DMA2D_FGPFCCR_AM_Pos)             /*!< 0x00030000 */
+#define DMA2D_FGPFCCR_AM           DMA2D_FGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */
+#define DMA2D_FGPFCCR_AM_0         (0x1UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00010000 */
+#define DMA2D_FGPFCCR_AM_1         (0x2UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00020000 */
+#define DMA2D_FGPFCCR_CSS_Pos      (18U)
+#define DMA2D_FGPFCCR_CSS_Msk      (0x3UL << DMA2D_FGPFCCR_CSS_Pos)            /*!< 0x000C0000 */
+#define DMA2D_FGPFCCR_CSS          DMA2D_FGPFCCR_CSS_Msk                       /* !< Chroma Sub-Sampling */
+#define DMA2D_FGPFCCR_CSS_0        (0x1UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00040000 */
+#define DMA2D_FGPFCCR_CSS_1        (0x2UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00080000 */
+#define DMA2D_FGPFCCR_AI_Pos       (20U)
+#define DMA2D_FGPFCCR_AI_Msk       (0x1UL << DMA2D_FGPFCCR_AI_Pos)             /*!< 0x00100000 */
+#define DMA2D_FGPFCCR_AI           DMA2D_FGPFCCR_AI_Msk                        /*!< Foreground Input Alpha Inverted */
+#define DMA2D_FGPFCCR_RBS_Pos      (21U)
+#define DMA2D_FGPFCCR_RBS_Msk      (0x1UL << DMA2D_FGPFCCR_RBS_Pos)            /*!< 0x00200000 */
+#define DMA2D_FGPFCCR_RBS          DMA2D_FGPFCCR_RBS_Msk                       /*!< Foreground Input Red Blue Swap */
+#define DMA2D_FGPFCCR_ALPHA_Pos    (24U)
+#define DMA2D_FGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */
+#define DMA2D_FGPFCCR_ALPHA        DMA2D_FGPFCCR_ALPHA_Msk                     /*!< Alpha value */
+
+/********************  Bit definition for DMA2D_FGCOLR register  **************/
+
+#define DMA2D_FGCOLR_BLUE_Pos      (0U)
+#define DMA2D_FGCOLR_BLUE_Msk      (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)           /*!< 0x000000FF */
+#define DMA2D_FGCOLR_BLUE          DMA2D_FGCOLR_BLUE_Msk                       /*!< Foreground Blue Value */
+#define DMA2D_FGCOLR_GREEN_Pos     (8U)
+#define DMA2D_FGCOLR_GREEN_Msk     (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */
+#define DMA2D_FGCOLR_GREEN         DMA2D_FGCOLR_GREEN_Msk                      /*!< Foreground Green Value */
+#define DMA2D_FGCOLR_RED_Pos       (16U)
+#define DMA2D_FGCOLR_RED_Msk       (0xFFUL << DMA2D_FGCOLR_RED_Pos)            /*!< 0x00FF0000 */
+#define DMA2D_FGCOLR_RED           DMA2D_FGCOLR_RED_Msk                        /*!< Foreground Red Value */
+
+/********************  Bit definition for DMA2D_BGPFCCR register  *************/
+
+#define DMA2D_BGPFCCR_CM_Pos       (0U)
+#define DMA2D_BGPFCCR_CM_Msk       (0xFUL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x0000000F */
+#define DMA2D_BGPFCCR_CM           DMA2D_BGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */
+#define DMA2D_BGPFCCR_CM_0         (0x1UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000001 */
+#define DMA2D_BGPFCCR_CM_1         (0x2UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000002 */
+#define DMA2D_BGPFCCR_CM_2         (0x4UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000004 */
+#define DMA2D_BGPFCCR_CM_3         (0x8UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000008 */
+#define DMA2D_BGPFCCR_CCM_Pos      (4U)
+#define DMA2D_BGPFCCR_CCM_Msk      (0x1UL << DMA2D_BGPFCCR_CCM_Pos)            /*!< 0x00000010 */
+#define DMA2D_BGPFCCR_CCM          DMA2D_BGPFCCR_CCM_Msk                       /*!< CLUT Color mode */
+#define DMA2D_BGPFCCR_START_Pos    (5U)
+#define DMA2D_BGPFCCR_START_Msk    (0x1UL << DMA2D_BGPFCCR_START_Pos)          /*!< 0x00000020 */
+#define DMA2D_BGPFCCR_START        DMA2D_BGPFCCR_START_Msk                     /*!< Start */
+#define DMA2D_BGPFCCR_CS_Pos       (8U)
+#define DMA2D_BGPFCCR_CS_Msk       (0xFFUL << DMA2D_BGPFCCR_CS_Pos)            /*!< 0x0000FF00 */
+#define DMA2D_BGPFCCR_CS           DMA2D_BGPFCCR_CS_Msk                        /*!< CLUT size */
+#define DMA2D_BGPFCCR_AM_Pos       (16U)
+#define DMA2D_BGPFCCR_AM_Msk       (0x3UL << DMA2D_BGPFCCR_AM_Pos)             /*!< 0x00030000 */
+#define DMA2D_BGPFCCR_AM           DMA2D_BGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */
+#define DMA2D_BGPFCCR_AM_0         (0x1UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00010000 */
+#define DMA2D_BGPFCCR_AM_1         (0x2UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00020000 */
+#define DMA2D_BGPFCCR_AI_Pos       (20U)
+#define DMA2D_BGPFCCR_AI_Msk       (0x1UL << DMA2D_BGPFCCR_AI_Pos)             /*!< 0x00100000 */
+#define DMA2D_BGPFCCR_AI           DMA2D_BGPFCCR_AI_Msk                        /*!< background Input Alpha Inverted */
+#define DMA2D_BGPFCCR_RBS_Pos      (21U)
+#define DMA2D_BGPFCCR_RBS_Msk      (0x1UL << DMA2D_BGPFCCR_RBS_Pos)            /*!< 0x00200000 */
+#define DMA2D_BGPFCCR_RBS          DMA2D_BGPFCCR_RBS_Msk                       /*!< Background Input Red Blue Swap */
+#define DMA2D_BGPFCCR_ALPHA_Pos    (24U)
+#define DMA2D_BGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */
+#define DMA2D_BGPFCCR_ALPHA        DMA2D_BGPFCCR_ALPHA_Msk                     /*!< background Input Alpha value */
+
+/********************  Bit definition for DMA2D_BGCOLR register  **************/
+
+#define DMA2D_BGCOLR_BLUE_Pos      (0U)
+#define DMA2D_BGCOLR_BLUE_Msk      (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)           /*!< 0x000000FF */
+#define DMA2D_BGCOLR_BLUE          DMA2D_BGCOLR_BLUE_Msk                       /*!< Background Blue Value */
+#define DMA2D_BGCOLR_GREEN_Pos     (8U)
+#define DMA2D_BGCOLR_GREEN_Msk     (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */
+#define DMA2D_BGCOLR_GREEN         DMA2D_BGCOLR_GREEN_Msk                      /*!< Background Green Value */
+#define DMA2D_BGCOLR_RED_Pos       (16U)
+#define DMA2D_BGCOLR_RED_Msk       (0xFFUL << DMA2D_BGCOLR_RED_Pos)            /*!< 0x00FF0000 */
+#define DMA2D_BGCOLR_RED           DMA2D_BGCOLR_RED_Msk                        /*!< Background Red Value */
+
+/********************  Bit definition for DMA2D_FGCMAR register  **************/
+
+#define DMA2D_FGCMAR_MA_Pos        (0U)
+#define DMA2D_FGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */
+#define DMA2D_FGCMAR_MA            DMA2D_FGCMAR_MA_Msk                         /*!< Foreground CLUT Memory Address */
+
+/********************  Bit definition for DMA2D_BGCMAR register  **************/
+
+#define DMA2D_BGCMAR_MA_Pos        (0U)
+#define DMA2D_BGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */
+#define DMA2D_BGCMAR_MA            DMA2D_BGCMAR_MA_Msk                         /*!< Background CLUT Memory Address */
+
+/********************  Bit definition for DMA2D_OPFCCR register  **************/
+
+#define DMA2D_OPFCCR_CM_Pos        (0U)
+#define DMA2D_OPFCCR_CM_Msk        (0x7UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000007 */
+#define DMA2D_OPFCCR_CM            DMA2D_OPFCCR_CM_Msk                         /*!< Output Color mode CM[2:0] */
+#define DMA2D_OPFCCR_CM_0          (0x1UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000001 */
+#define DMA2D_OPFCCR_CM_1          (0x2UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000002 */
+#define DMA2D_OPFCCR_CM_2          (0x4UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000004 */
+#define DMA2D_OPFCCR_SB_Pos        (8U)
+#define DMA2D_OPFCCR_SB_Msk        (0x1UL << DMA2D_OPFCCR_SB_Pos)              /*!< 0x00000100 */
+#define DMA2D_OPFCCR_SB            DMA2D_OPFCCR_SB_Msk                         /*!< Swap Bytes */
+#define DMA2D_OPFCCR_AI_Pos        (20U)
+#define DMA2D_OPFCCR_AI_Msk        (0x1UL << DMA2D_OPFCCR_AI_Pos)              /*!< 0x00100000 */
+#define DMA2D_OPFCCR_AI            DMA2D_OPFCCR_AI_Msk                         /*!< Output Alpha Inverted */
+#define DMA2D_OPFCCR_RBS_Pos       (21U)
+#define DMA2D_OPFCCR_RBS_Msk       (0x1UL << DMA2D_OPFCCR_RBS_Pos)             /*!< 0x00200000 */
+#define DMA2D_OPFCCR_RBS           DMA2D_OPFCCR_RBS_Msk                        /*!< Output Red Blue Swap */
+
+/********************  Bit definition for DMA2D_OCOLR register  ***************/
+
+/*!<Mode_ARGB8888/RGB888 */
+
+#define DMA2D_OCOLR_BLUE_1_Pos     (0U)
+#define DMA2D_OCOLR_BLUE_1_Msk     (0xFFUL <<DMA2D_OCOLR_BLUE_1_Pos)            /*0x000000FFU*/
+#define DMA2D_OCOLR_BLUE_1         DMA2D_OCOLR_BLUE_1_Msk                      /*!< Output BLUE Value */
+#define DMA2D_OCOLR_GREEN_1_Pos    (8U)
+#define DMA2D_OCOLR_GREEN_1_Msk    (0xFFUL<<DMA2D_OCOLR_GREEN_1_Pos)            /*0x0000FF00U)*/
+#define DMA2D_OCOLR_GREEN_1        DMA2D_OCOLR_GREEN_1_Msk                     /*!< Output GREEN Value  */
+#define DMA2D_OCOLR_RED_1_Pos      (16U)
+#define DMA2D_OCOLR_RED_1_Msk      (0xFFUL << DMA2D_OCOLR_RED_1_Pos)            /*0x00FF0000U */
+#define DMA2D_OCOLR_RED_1          DMA2D_OCOLR_RED_1_Msk                       /*!< Output Red Value */
+#define DMA2D_OCOLR_ALPHA_1_Pos    (24U)
+#define DMA2D_OCOLR_ALPHA_1_Msk    (0xFFUL << DMA2D_OCOLR_ALPHA_1_Pos)          /*0xFF000000U*/
+#define DMA2D_OCOLR_ALPHA_1        DMA2D_OCOLR_ALPHA_1_Msk                     /*!< Output Alpha Channel Value */
+
+/*!<Mode_RGB565 */
+#define DMA2D_OCOLR_BLUE_2_Pos     (0U)
+#define DMA2D_OCOLR_BLUE_2_Msk     (0x1FUL <<DMA2D_OCOLR_BLUE_2_Pos)            /*0x0000001FU*/
+#define DMA2D_OCOLR_BLUE_2         DMA2D_OCOLR_BLUE_2_Msk                      /*!< Output BLUE Value */
+#define DMA2D_OCOLR_GREEN_2_Pos    (5U)
+#define DMA2D_OCOLR_GREEN_2_Msk    (0x7EUL << DMA2D_OCOLR_GREEN_2_Pos)          /* 0x000007E0U */
+#define DMA2D_OCOLR_GREEN_2        DMA2D_OCOLR_GREEN_2_Msk                     /*!< Output GREEN Value  */
+#define DMA2D_OCOLR_RED_2_Pos      (11U)
+#define DMA2D_OCOLR_RED_2_Msk      (0xF8UL<<DMA2D_OCOLR_RED_2_Pos)              /*0x0000F800U*/
+#define DMA2D_OCOLR_RED_2          DMA2D_OCOLR_RED_2_Msk                       /*!< Output Red Value */
+
+/*!<Mode_ARGB1555 */
+#define DMA2D_OCOLR_BLUE_3_Pos     (0U)
+#define DMA2D_OCOLR_BLUE_3_Msk     (0x1FUL << DMA2D_OCOLR_BLUE_3_Pos)           /*0x0000001FU*/
+#define DMA2D_OCOLR_BLUE_3         DMA2D_OCOLR_BLUE_3_Msk                      /*!< Output BLUE Value */
+#define DMA2D_OCOLR_GREEN_3_Pos    (5U)
+#define DMA2D_OCOLR_GREEN_3_Msk    (0x3EUL << DMA2D_OCOLR_GREEN_3_Pos)          /*0x000003E0U*/
+#define DMA2D_OCOLR_GREEN_3        DMA2D_OCOLR_GREEN_3_Msk                     /*!< Output GREEN Value  */
+#define DMA2D_OCOLR_RED_3_Pos      (10U)
+#define DMA2D_OCOLR_RED_3_Msk      (0x7CUL << DMA2D_OCOLR_RED_3_Pos)            /* 0x00007C00U*/
+#define DMA2D_OCOLR_RED_3          DMA2D_OCOLR_RED_3_Msk                       /*!< Output Red Value */
+#define DMA2D_OCOLR_ALPHA_3_Pos    (15U)
+#define DMA2D_OCOLR_ALPHA_3_Msk    (0x1UL << DMA2D_OCOLR_ALPHA_3_Pos)           /*0x00008000U*/
+#define DMA2D_OCOLR_ALPHA_3        DMA2D_OCOLR_ALPHA_3_Msk                     /*!< Output Alpha Channel Value */
+
+/*!<Mode_ARGB4444 */
+#define DMA2D_OCOLR_BLUE_4_Pos     (0U)
+#define DMA2D_OCOLR_BLUE_4_Msk     (0xFUL << DMA2D_OCOLR_BLUE_4_Pos)            /*0x0000000FU*/
+#define DMA2D_OCOLR_BLUE_4         DMA2D_OCOLR_BLUE_4_Msk                      /*!< Output BLUE Value */
+#define DMA2D_OCOLR_GREEN_4_Pos    (4U)
+#define DMA2D_OCOLR_GREEN_4_Msk    (0xFUL << DMA2D_OCOLR_GREEN_4_Pos)           /*0x000000F0U*/
+#define DMA2D_OCOLR_GREEN_4        DMA2D_OCOLR_GREEN_4_Msk                     /*!< Output GREEN Value  */
+#define DMA2D_OCOLR_RED_4_Pos      (8U)
+#define DMA2D_OCOLR_RED_4_Msk      (0xFUL << DMA2D_OCOLR_RED_4_Pos)             /*0x00000F00U*/
+#define DMA2D_OCOLR_RED_4          DMA2D_OCOLR_RED_4_Msk                       /*!< Output Red Value */
+#define DMA2D_OCOLR_ALPHA_4_Pos    (12U)
+#define DMA2D_OCOLR_ALPHA_4_Msk    (0xFUL << DMA2D_OCOLR_ALPHA_4_Pos)            /*0x0000F000U*/
+#define DMA2D_OCOLR_ALPHA_4        DMA2D_OCOLR_ALPHA_4_Msk                     /*!< Output Alpha Channel Value */
+
+/********************  Bit definition for DMA2D_OMAR register  ****************/
+
+#define DMA2D_OMAR_MA_Pos          (0U)
+#define DMA2D_OMAR_MA_Msk          (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)         /*!< 0xFFFFFFFF */
+#define DMA2D_OMAR_MA              DMA2D_OMAR_MA_Msk                           /*!< Output Memory Address */
+
+/********************  Bit definition for DMA2D_OOR register  *****************/
+
+#define DMA2D_OOR_LO_Pos           (0U)
+#define DMA2D_OOR_LO_Msk           (0xFFFFUL << DMA2D_OOR_LO_Pos)              /*!< 0x0000FFFF */
+#define DMA2D_OOR_LO               DMA2D_OOR_LO_Msk                            /*!< Output Line Offset */
+
+/********************  Bit definition for DMA2D_NLR register  *****************/
+
+#define DMA2D_NLR_NL_Pos           (0U)
+#define DMA2D_NLR_NL_Msk           (0xFFFFUL << DMA2D_NLR_NL_Pos)              /*!< 0x0000FFFF */
+#define DMA2D_NLR_NL               DMA2D_NLR_NL_Msk                            /*!< Number of Lines */
+#define DMA2D_NLR_PL_Pos           (16U)
+#define DMA2D_NLR_PL_Msk           (0x3FFFUL << DMA2D_NLR_PL_Pos)              /*!< 0x3FFF0000 */
+#define DMA2D_NLR_PL               DMA2D_NLR_PL_Msk                            /*!< Pixel per Lines */
+
+/********************  Bit definition for DMA2D_LWR register  *****************/
+
+#define DMA2D_LWR_LW_Pos           (0U)
+#define DMA2D_LWR_LW_Msk           (0xFFFFUL << DMA2D_LWR_LW_Pos)              /*!< 0x0000FFFF */
+#define DMA2D_LWR_LW               DMA2D_LWR_LW_Msk                            /*!< Line Watermark */
+
+/********************  Bit definition for DMA2D_AMTCR register  ***************/
+
+#define DMA2D_AMTCR_EN_Pos         (0U)
+#define DMA2D_AMTCR_EN_Msk         (0x1UL << DMA2D_AMTCR_EN_Pos)               /*!< 0x00000001 */
+#define DMA2D_AMTCR_EN             DMA2D_AMTCR_EN_Msk                          /*!< Enable */
+#define DMA2D_AMTCR_DT_Pos         (8U)
+#define DMA2D_AMTCR_DT_Msk         (0xFFUL << DMA2D_AMTCR_DT_Pos)              /*!< 0x0000FF00 */
+#define DMA2D_AMTCR_DT             DMA2D_AMTCR_DT_Msk                          /*!< Dead Time */
+
+
+/********************  Bit definition for DMA2D_FGCLUT register  **************/
+
+/********************  Bit definition for DMA2D_BGCLUT register  **************/
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                    External Interrupt/Event Controller                     */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for EXTI_RTSR1 register  *******************/
+#define EXTI_RTSR1_TR_Pos          (0U)
+#define EXTI_RTSR1_TR_Msk          (0x3FFFFFUL << EXTI_RTSR1_TR_Pos)           /*!< 0x003FFFFF */
+#define EXTI_RTSR1_TR              EXTI_RTSR1_TR_Msk                           /*!< Rising trigger event configuration bit */
+#define EXTI_RTSR1_TR0_Pos         (0U)
+#define EXTI_RTSR1_TR0_Msk         (0x1UL << EXTI_RTSR1_TR0_Pos)               /*!< 0x00000001 */
+#define EXTI_RTSR1_TR0             EXTI_RTSR1_TR0_Msk                          /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR1_TR1_Pos         (1U)
+#define EXTI_RTSR1_TR1_Msk         (0x1UL << EXTI_RTSR1_TR1_Pos)               /*!< 0x00000002 */
+#define EXTI_RTSR1_TR1             EXTI_RTSR1_TR1_Msk                          /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR1_TR2_Pos         (2U)
+#define EXTI_RTSR1_TR2_Msk         (0x1UL << EXTI_RTSR1_TR2_Pos)               /*!< 0x00000004 */
+#define EXTI_RTSR1_TR2             EXTI_RTSR1_TR2_Msk                          /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR1_TR3_Pos         (3U)
+#define EXTI_RTSR1_TR3_Msk         (0x1UL << EXTI_RTSR1_TR3_Pos)               /*!< 0x00000008 */
+#define EXTI_RTSR1_TR3             EXTI_RTSR1_TR3_Msk                          /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR1_TR4_Pos         (4U)
+#define EXTI_RTSR1_TR4_Msk         (0x1UL << EXTI_RTSR1_TR4_Pos)               /*!< 0x00000010 */
+#define EXTI_RTSR1_TR4             EXTI_RTSR1_TR4_Msk                          /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR1_TR5_Pos         (5U)
+#define EXTI_RTSR1_TR5_Msk         (0x1UL << EXTI_RTSR1_TR5_Pos)               /*!< 0x00000020 */
+#define EXTI_RTSR1_TR5             EXTI_RTSR1_TR5_Msk                          /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR1_TR6_Pos         (6U)
+#define EXTI_RTSR1_TR6_Msk         (0x1UL << EXTI_RTSR1_TR6_Pos)               /*!< 0x00000040 */
+#define EXTI_RTSR1_TR6             EXTI_RTSR1_TR6_Msk                          /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR1_TR7_Pos         (7U)
+#define EXTI_RTSR1_TR7_Msk         (0x1UL << EXTI_RTSR1_TR7_Pos)               /*!< 0x00000080 */
+#define EXTI_RTSR1_TR7             EXTI_RTSR1_TR7_Msk                          /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR1_TR8_Pos         (8U)
+#define EXTI_RTSR1_TR8_Msk         (0x1UL << EXTI_RTSR1_TR8_Pos)               /*!< 0x00000100 */
+#define EXTI_RTSR1_TR8             EXTI_RTSR1_TR8_Msk                          /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR1_TR9_Pos         (9U)
+#define EXTI_RTSR1_TR9_Msk         (0x1UL << EXTI_RTSR1_TR9_Pos)               /*!< 0x00000200 */
+#define EXTI_RTSR1_TR9             EXTI_RTSR1_TR9_Msk                          /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR1_TR10_Pos        (10U)
+#define EXTI_RTSR1_TR10_Msk        (0x1UL << EXTI_RTSR1_TR10_Pos)              /*!< 0x00000400 */
+#define EXTI_RTSR1_TR10            EXTI_RTSR1_TR10_Msk                         /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR1_TR11_Pos        (11U)
+#define EXTI_RTSR1_TR11_Msk        (0x1UL << EXTI_RTSR1_TR11_Pos)              /*!< 0x00000800 */
+#define EXTI_RTSR1_TR11            EXTI_RTSR1_TR11_Msk                         /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR1_TR12_Pos        (12U)
+#define EXTI_RTSR1_TR12_Msk        (0x1UL << EXTI_RTSR1_TR12_Pos)              /*!< 0x00001000 */
+#define EXTI_RTSR1_TR12            EXTI_RTSR1_TR12_Msk                         /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR1_TR13_Pos        (13U)
+#define EXTI_RTSR1_TR13_Msk        (0x1UL << EXTI_RTSR1_TR13_Pos)              /*!< 0x00002000 */
+#define EXTI_RTSR1_TR13            EXTI_RTSR1_TR13_Msk                         /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR1_TR14_Pos        (14U)
+#define EXTI_RTSR1_TR14_Msk        (0x1UL << EXTI_RTSR1_TR14_Pos)              /*!< 0x00004000 */
+#define EXTI_RTSR1_TR14            EXTI_RTSR1_TR14_Msk                         /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR1_TR15_Pos        (15U)
+#define EXTI_RTSR1_TR15_Msk        (0x1UL << EXTI_RTSR1_TR15_Pos)              /*!< 0x00008000 */
+#define EXTI_RTSR1_TR15            EXTI_RTSR1_TR15_Msk                         /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR1_TR16_Pos        (16U)
+#define EXTI_RTSR1_TR16_Msk        (0x1UL << EXTI_RTSR1_TR16_Pos)              /*!< 0x00010000 */
+#define EXTI_RTSR1_TR16            EXTI_RTSR1_TR16_Msk                         /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR1_TR17_Pos        (17U)
+#define EXTI_RTSR1_TR17_Msk        (0x1UL << EXTI_RTSR1_TR17_Pos)              /*!< 0x00020000 */
+#define EXTI_RTSR1_TR17            EXTI_RTSR1_TR17_Msk                         /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR1_TR18_Pos        (18U)
+#define EXTI_RTSR1_TR18_Msk        (0x1UL << EXTI_RTSR1_TR18_Pos)              /*!< 0x00040000 */
+#define EXTI_RTSR1_TR18            EXTI_RTSR1_TR18_Msk                         /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR1_TR19_Pos        (19U)
+#define EXTI_RTSR1_TR19_Msk        (0x1UL << EXTI_RTSR1_TR19_Pos)              /*!< 0x00080000 */
+#define EXTI_RTSR1_TR19            EXTI_RTSR1_TR19_Msk                         /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR1_TR20_Pos        (20U)
+#define EXTI_RTSR1_TR20_Msk        (0x1UL << EXTI_RTSR1_TR20_Pos)              /*!< 0x00100000 */
+#define EXTI_RTSR1_TR20            EXTI_RTSR1_TR20_Msk                         /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR1_TR21_Pos        (21U)
+#define EXTI_RTSR1_TR21_Msk        (0x1UL << EXTI_RTSR1_TR21_Pos)              /*!< 0x00200000 */
+#define EXTI_RTSR1_TR21            EXTI_RTSR1_TR21_Msk                         /*!< Rising trigger event configuration bit of line 21 */
+
+/******************  Bit definition for EXTI_FTSR1 register  *******************/
+#define EXTI_FTSR1_TR_Pos          (0U)
+#define EXTI_FTSR1_TR_Msk          (0x3FFFFFUL << EXTI_FTSR1_TR_Pos)           /*!< 0x003FFFFF */
+#define EXTI_FTSR1_TR              EXTI_FTSR1_TR_Msk                           /*!< Falling trigger event configuration bit */
+#define EXTI_FTSR1_TR0_Pos         (0U)
+#define EXTI_FTSR1_TR0_Msk         (0x1UL << EXTI_FTSR1_TR0_Pos)               /*!< 0x00000001 */
+#define EXTI_FTSR1_TR0             EXTI_FTSR1_TR0_Msk                          /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR1_TR1_Pos         (1U)
+#define EXTI_FTSR1_TR1_Msk         (0x1UL << EXTI_FTSR1_TR1_Pos)               /*!< 0x00000002 */
+#define EXTI_FTSR1_TR1             EXTI_FTSR1_TR1_Msk                          /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR1_TR2_Pos         (2U)
+#define EXTI_FTSR1_TR2_Msk         (0x1UL << EXTI_FTSR1_TR2_Pos)               /*!< 0x00000004 */
+#define EXTI_FTSR1_TR2             EXTI_FTSR1_TR2_Msk                          /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR1_TR3_Pos         (3U)
+#define EXTI_FTSR1_TR3_Msk         (0x1UL << EXTI_FTSR1_TR3_Pos)               /*!< 0x00000008 */
+#define EXTI_FTSR1_TR3             EXTI_FTSR1_TR3_Msk                          /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR1_TR4_Pos         (4U)
+#define EXTI_FTSR1_TR4_Msk         (0x1UL << EXTI_FTSR1_TR4_Pos)               /*!< 0x00000010 */
+#define EXTI_FTSR1_TR4             EXTI_FTSR1_TR4_Msk                          /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR1_TR5_Pos         (5U)
+#define EXTI_FTSR1_TR5_Msk         (0x1UL << EXTI_FTSR1_TR5_Pos)               /*!< 0x00000020 */
+#define EXTI_FTSR1_TR5             EXTI_FTSR1_TR5_Msk                          /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR1_TR6_Pos         (6U)
+#define EXTI_FTSR1_TR6_Msk         (0x1UL << EXTI_FTSR1_TR6_Pos)               /*!< 0x00000040 */
+#define EXTI_FTSR1_TR6             EXTI_FTSR1_TR6_Msk                          /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR1_TR7_Pos         (7U)
+#define EXTI_FTSR1_TR7_Msk         (0x1UL << EXTI_FTSR1_TR7_Pos)               /*!< 0x00000080 */
+#define EXTI_FTSR1_TR7             EXTI_FTSR1_TR7_Msk                          /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR1_TR8_Pos         (8U)
+#define EXTI_FTSR1_TR8_Msk         (0x1UL << EXTI_FTSR1_TR8_Pos)               /*!< 0x00000100 */
+#define EXTI_FTSR1_TR8             EXTI_FTSR1_TR8_Msk                          /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR1_TR9_Pos         (9U)
+#define EXTI_FTSR1_TR9_Msk         (0x1UL << EXTI_FTSR1_TR9_Pos)               /*!< 0x00000200 */
+#define EXTI_FTSR1_TR9             EXTI_FTSR1_TR9_Msk                          /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR1_TR10_Pos        (10U)
+#define EXTI_FTSR1_TR10_Msk        (0x1UL << EXTI_FTSR1_TR10_Pos)              /*!< 0x00000400 */
+#define EXTI_FTSR1_TR10            EXTI_FTSR1_TR10_Msk                         /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR1_TR11_Pos        (11U)
+#define EXTI_FTSR1_TR11_Msk        (0x1UL << EXTI_FTSR1_TR11_Pos)              /*!< 0x00000800 */
+#define EXTI_FTSR1_TR11            EXTI_FTSR1_TR11_Msk                         /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR1_TR12_Pos        (12U)
+#define EXTI_FTSR1_TR12_Msk        (0x1UL << EXTI_FTSR1_TR12_Pos)              /*!< 0x00001000 */
+#define EXTI_FTSR1_TR12            EXTI_FTSR1_TR12_Msk                         /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR1_TR13_Pos        (13U)
+#define EXTI_FTSR1_TR13_Msk        (0x1UL << EXTI_FTSR1_TR13_Pos)              /*!< 0x00002000 */
+#define EXTI_FTSR1_TR13            EXTI_FTSR1_TR13_Msk                         /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR1_TR14_Pos        (14U)
+#define EXTI_FTSR1_TR14_Msk        (0x1UL << EXTI_FTSR1_TR14_Pos)              /*!< 0x00004000 */
+#define EXTI_FTSR1_TR14            EXTI_FTSR1_TR14_Msk                         /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR1_TR15_Pos        (15U)
+#define EXTI_FTSR1_TR15_Msk        (0x1UL << EXTI_FTSR1_TR15_Pos)              /*!< 0x00008000 */
+#define EXTI_FTSR1_TR15            EXTI_FTSR1_TR15_Msk                         /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR1_TR16_Pos        (16U)
+#define EXTI_FTSR1_TR16_Msk        (0x1UL << EXTI_FTSR1_TR16_Pos)              /*!< 0x00010000 */
+#define EXTI_FTSR1_TR16            EXTI_FTSR1_TR16_Msk                         /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR1_TR17_Pos        (17U)
+#define EXTI_FTSR1_TR17_Msk        (0x1UL << EXTI_FTSR1_TR17_Pos)              /*!< 0x00020000 */
+#define EXTI_FTSR1_TR17            EXTI_FTSR1_TR17_Msk                         /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR1_TR18_Pos        (18U)
+#define EXTI_FTSR1_TR18_Msk        (0x1UL << EXTI_FTSR1_TR18_Pos)              /*!< 0x00040000 */
+#define EXTI_FTSR1_TR18            EXTI_FTSR1_TR18_Msk                         /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR1_TR19_Pos        (19U)
+#define EXTI_FTSR1_TR19_Msk        (0x1UL << EXTI_FTSR1_TR19_Pos)              /*!< 0x00080000 */
+#define EXTI_FTSR1_TR19            EXTI_FTSR1_TR19_Msk                         /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR1_TR20_Pos        (20U)
+#define EXTI_FTSR1_TR20_Msk        (0x1UL << EXTI_FTSR1_TR20_Pos)              /*!< 0x00100000 */
+#define EXTI_FTSR1_TR20            EXTI_FTSR1_TR20_Msk                         /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR1_TR21_Pos        (21U)
+#define EXTI_FTSR1_TR21_Msk        (0x1UL << EXTI_FTSR1_TR21_Pos)              /*!< 0x00200000 */
+#define EXTI_FTSR1_TR21            EXTI_FTSR1_TR21_Msk                         /*!< Falling trigger event configuration bit of line 21 */
+
+/******************  Bit definition for EXTI_SWIER1 register  ******************/
+#define EXTI_SWIER1_SWIER0_Pos     (0U)
+#define EXTI_SWIER1_SWIER0_Msk     (0x1UL << EXTI_SWIER1_SWIER0_Pos)           /*!< 0x00000001 */
+#define EXTI_SWIER1_SWIER0         EXTI_SWIER1_SWIER0_Msk                      /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER1_SWIER1_Pos     (1U)
+#define EXTI_SWIER1_SWIER1_Msk     (0x1UL << EXTI_SWIER1_SWIER1_Pos)           /*!< 0x00000002 */
+#define EXTI_SWIER1_SWIER1         EXTI_SWIER1_SWIER1_Msk                      /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER1_SWIER2_Pos     (2U)
+#define EXTI_SWIER1_SWIER2_Msk     (0x1UL << EXTI_SWIER1_SWIER2_Pos)           /*!< 0x00000004 */
+#define EXTI_SWIER1_SWIER2         EXTI_SWIER1_SWIER2_Msk                      /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER1_SWIER3_Pos     (3U)
+#define EXTI_SWIER1_SWIER3_Msk     (0x1UL << EXTI_SWIER1_SWIER3_Pos)           /*!< 0x00000008 */
+#define EXTI_SWIER1_SWIER3         EXTI_SWIER1_SWIER3_Msk                      /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER1_SWIER4_Pos     (4U)
+#define EXTI_SWIER1_SWIER4_Msk     (0x1UL << EXTI_SWIER1_SWIER4_Pos)           /*!< 0x00000010 */
+#define EXTI_SWIER1_SWIER4         EXTI_SWIER1_SWIER4_Msk                      /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER1_SWIER5_Pos     (5U)
+#define EXTI_SWIER1_SWIER5_Msk     (0x1UL << EXTI_SWIER1_SWIER5_Pos)           /*!< 0x00000020 */
+#define EXTI_SWIER1_SWIER5         EXTI_SWIER1_SWIER5_Msk                      /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER1_SWIER6_Pos     (6U)
+#define EXTI_SWIER1_SWIER6_Msk     (0x1UL << EXTI_SWIER1_SWIER6_Pos)           /*!< 0x00000040 */
+#define EXTI_SWIER1_SWIER6         EXTI_SWIER1_SWIER6_Msk                      /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER1_SWIER7_Pos     (7U)
+#define EXTI_SWIER1_SWIER7_Msk     (0x1UL << EXTI_SWIER1_SWIER7_Pos)           /*!< 0x00000080 */
+#define EXTI_SWIER1_SWIER7         EXTI_SWIER1_SWIER7_Msk                      /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER1_SWIER8_Pos     (8U)
+#define EXTI_SWIER1_SWIER8_Msk     (0x1UL << EXTI_SWIER1_SWIER8_Pos)           /*!< 0x00000100 */
+#define EXTI_SWIER1_SWIER8         EXTI_SWIER1_SWIER8_Msk                      /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER1_SWIER9_Pos     (9U)
+#define EXTI_SWIER1_SWIER9_Msk     (0x1UL << EXTI_SWIER1_SWIER9_Pos)           /*!< 0x00000200 */
+#define EXTI_SWIER1_SWIER9         EXTI_SWIER1_SWIER9_Msk                      /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER1_SWIER10_Pos    (10U)
+#define EXTI_SWIER1_SWIER10_Msk    (0x1UL << EXTI_SWIER1_SWIER10_Pos)          /*!< 0x00000400 */
+#define EXTI_SWIER1_SWIER10        EXTI_SWIER1_SWIER10_Msk                     /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER1_SWIER11_Pos    (11U)
+#define EXTI_SWIER1_SWIER11_Msk    (0x1UL << EXTI_SWIER1_SWIER11_Pos)          /*!< 0x00000800 */
+#define EXTI_SWIER1_SWIER11        EXTI_SWIER1_SWIER11_Msk                     /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER1_SWIER12_Pos    (12U)
+#define EXTI_SWIER1_SWIER12_Msk    (0x1UL << EXTI_SWIER1_SWIER12_Pos)          /*!< 0x00001000 */
+#define EXTI_SWIER1_SWIER12        EXTI_SWIER1_SWIER12_Msk                     /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER1_SWIER13_Pos    (13U)
+#define EXTI_SWIER1_SWIER13_Msk    (0x1UL << EXTI_SWIER1_SWIER13_Pos)          /*!< 0x00002000 */
+#define EXTI_SWIER1_SWIER13        EXTI_SWIER1_SWIER13_Msk                     /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER1_SWIER14_Pos    (14U)
+#define EXTI_SWIER1_SWIER14_Msk    (0x1UL << EXTI_SWIER1_SWIER14_Pos)          /*!< 0x00004000 */
+#define EXTI_SWIER1_SWIER14        EXTI_SWIER1_SWIER14_Msk                     /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER1_SWIER15_Pos    (15U)
+#define EXTI_SWIER1_SWIER15_Msk    (0x1UL << EXTI_SWIER1_SWIER15_Pos)          /*!< 0x00008000 */
+#define EXTI_SWIER1_SWIER15        EXTI_SWIER1_SWIER15_Msk                     /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER1_SWIER16_Pos    (16U)
+#define EXTI_SWIER1_SWIER16_Msk    (0x1UL << EXTI_SWIER1_SWIER16_Pos)          /*!< 0x00010000 */
+#define EXTI_SWIER1_SWIER16        EXTI_SWIER1_SWIER16_Msk                     /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER1_SWIER17_Pos    (17U)
+#define EXTI_SWIER1_SWIER17_Msk    (0x1UL << EXTI_SWIER1_SWIER17_Pos)          /*!< 0x00020000 */
+#define EXTI_SWIER1_SWIER17        EXTI_SWIER1_SWIER17_Msk                     /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER1_SWIER18_Pos    (18U)
+#define EXTI_SWIER1_SWIER18_Msk    (0x1UL << EXTI_SWIER1_SWIER18_Pos)          /*!< 0x00040000 */
+#define EXTI_SWIER1_SWIER18        EXTI_SWIER1_SWIER18_Msk                     /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER1_SWIER19_Pos    (19U)
+#define EXTI_SWIER1_SWIER19_Msk    (0x1UL << EXTI_SWIER1_SWIER19_Pos)          /*!< 0x00080000 */
+#define EXTI_SWIER1_SWIER19        EXTI_SWIER1_SWIER19_Msk                     /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER1_SWIER20_Pos    (20U)
+#define EXTI_SWIER1_SWIER20_Msk    (0x1UL << EXTI_SWIER1_SWIER20_Pos)          /*!< 0x00100000 */
+#define EXTI_SWIER1_SWIER20        EXTI_SWIER1_SWIER20_Msk                     /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER1_SWIER21_Pos    (21U)
+#define EXTI_SWIER1_SWIER21_Msk    (0x1UL << EXTI_SWIER1_SWIER21_Pos)          /*!< 0x00200000 */
+#define EXTI_SWIER1_SWIER21        EXTI_SWIER1_SWIER21_Msk                     /*!< Software Interrupt on line 21 */
+
+/******************  Bit definition for EXTI_D3PMR1 register  ******************/
+#define EXTI_D3PMR1_MR0_Pos        (0U)
+#define EXTI_D3PMR1_MR0_Msk        (0x1UL << EXTI_D3PMR1_MR0_Pos)              /*!< 0x00000001 */
+#define EXTI_D3PMR1_MR0            EXTI_D3PMR1_MR0_Msk                         /*!< Pending Mask Event for line 0  */
+#define EXTI_D3PMR1_MR1_Pos        (1U)
+#define EXTI_D3PMR1_MR1_Msk        (0x1UL << EXTI_D3PMR1_MR1_Pos)              /*!< 0x00000002 */
+#define EXTI_D3PMR1_MR1            EXTI_D3PMR1_MR1_Msk                         /*!< Pending Mask Event for line 1  */
+#define EXTI_D3PMR1_MR2_Pos        (2U)
+#define EXTI_D3PMR1_MR2_Msk        (0x1UL << EXTI_D3PMR1_MR2_Pos)              /*!< 0x00000004 */
+#define EXTI_D3PMR1_MR2            EXTI_D3PMR1_MR2_Msk                         /*!< Pending Mask Event for line 2  */
+#define EXTI_D3PMR1_MR3_Pos        (3U)
+#define EXTI_D3PMR1_MR3_Msk        (0x1UL << EXTI_D3PMR1_MR3_Pos)              /*!< 0x00000008 */
+#define EXTI_D3PMR1_MR3            EXTI_D3PMR1_MR3_Msk                         /*!< Pending Mask Event for line 3  */
+#define EXTI_D3PMR1_MR4_Pos        (4U)
+#define EXTI_D3PMR1_MR4_Msk        (0x1UL << EXTI_D3PMR1_MR4_Pos)              /*!< 0x00000010 */
+#define EXTI_D3PMR1_MR4            EXTI_D3PMR1_MR4_Msk                         /*!< Pending Mask Event for line 4  */
+#define EXTI_D3PMR1_MR5_Pos        (5U)
+#define EXTI_D3PMR1_MR5_Msk        (0x1UL << EXTI_D3PMR1_MR5_Pos)              /*!< 0x00000020 */
+#define EXTI_D3PMR1_MR5            EXTI_D3PMR1_MR5_Msk                         /*!< Pending Mask Event for line 5  */
+#define EXTI_D3PMR1_MR6_Pos        (6U)
+#define EXTI_D3PMR1_MR6_Msk        (0x1UL << EXTI_D3PMR1_MR6_Pos)              /*!< 0x00000040 */
+#define EXTI_D3PMR1_MR6            EXTI_D3PMR1_MR6_Msk                         /*!< Pending Mask Event for line 6  */
+#define EXTI_D3PMR1_MR7_Pos        (7U)
+#define EXTI_D3PMR1_MR7_Msk        (0x1UL << EXTI_D3PMR1_MR7_Pos)              /*!< 0x00000080 */
+#define EXTI_D3PMR1_MR7            EXTI_D3PMR1_MR7_Msk                         /*!< Pending Mask Event for line 7  */
+#define EXTI_D3PMR1_MR8_Pos        (8U)
+#define EXTI_D3PMR1_MR8_Msk        (0x1UL << EXTI_D3PMR1_MR8_Pos)              /*!< 0x00000100 */
+#define EXTI_D3PMR1_MR8            EXTI_D3PMR1_MR8_Msk                         /*!< Pending Mask Event for line 8  */
+#define EXTI_D3PMR1_MR9_Pos        (9U)
+#define EXTI_D3PMR1_MR9_Msk        (0x1UL << EXTI_D3PMR1_MR9_Pos)              /*!< 0x00000200 */
+#define EXTI_D3PMR1_MR9            EXTI_D3PMR1_MR9_Msk                         /*!< Pending Mask Event for line 9  */
+#define EXTI_D3PMR1_MR10_Pos       (10U)
+#define EXTI_D3PMR1_MR10_Msk       (0x1UL << EXTI_D3PMR1_MR10_Pos)             /*!< 0x00000400 */
+#define EXTI_D3PMR1_MR10           EXTI_D3PMR1_MR10_Msk                        /*!< Pending Mask Event for line 10 */
+#define EXTI_D3PMR1_MR11_Pos       (11U)
+#define EXTI_D3PMR1_MR11_Msk       (0x1UL << EXTI_D3PMR1_MR11_Pos)             /*!< 0x00000800 */
+#define EXTI_D3PMR1_MR11           EXTI_D3PMR1_MR11_Msk                        /*!< Pending Mask Event for line 11 */
+#define EXTI_D3PMR1_MR12_Pos       (12U)
+#define EXTI_D3PMR1_MR12_Msk       (0x1UL << EXTI_D3PMR1_MR12_Pos)             /*!< 0x00001000 */
+#define EXTI_D3PMR1_MR12           EXTI_D3PMR1_MR12_Msk                        /*!< Pending Mask Event for line 12 */
+#define EXTI_D3PMR1_MR13_Pos       (13U)
+#define EXTI_D3PMR1_MR13_Msk       (0x1UL << EXTI_D3PMR1_MR13_Pos)             /*!< 0x00002000 */
+#define EXTI_D3PMR1_MR13           EXTI_D3PMR1_MR13_Msk                        /*!< Pending Mask Event for line 13 */
+#define EXTI_D3PMR1_MR14_Pos       (14U)
+#define EXTI_D3PMR1_MR14_Msk       (0x1UL << EXTI_D3PMR1_MR14_Pos)             /*!< 0x00004000 */
+#define EXTI_D3PMR1_MR14           EXTI_D3PMR1_MR14_Msk                        /*!< Pending Mask Event for line 14 */
+#define EXTI_D3PMR1_MR15_Pos       (15U)
+#define EXTI_D3PMR1_MR15_Msk       (0x1UL << EXTI_D3PMR1_MR15_Pos)             /*!< 0x00008000 */
+#define EXTI_D3PMR1_MR15           EXTI_D3PMR1_MR15_Msk                        /*!< Pending Mask Event for line 15 */
+#define EXTI_D3PMR1_MR19_Pos       (19U)
+#define EXTI_D3PMR1_MR19_Msk       (0x1UL << EXTI_D3PMR1_MR19_Pos)             /*!< 0x00080000 */
+#define EXTI_D3PMR1_MR19           EXTI_D3PMR1_MR19_Msk                        /*!< Pending Mask Event for line 19 */
+#define EXTI_D3PMR1_MR20_Pos       (20U)
+#define EXTI_D3PMR1_MR20_Msk       (0x1UL << EXTI_D3PMR1_MR20_Pos)             /*!< 0x00100000 */
+#define EXTI_D3PMR1_MR20           EXTI_D3PMR1_MR20_Msk                        /*!< Pending Mask Event for line 20 */
+#define EXTI_D3PMR1_MR21_Pos       (21U)
+#define EXTI_D3PMR1_MR21_Msk       (0x1UL << EXTI_D3PMR1_MR21_Pos)             /*!< 0x00200000 */
+#define EXTI_D3PMR1_MR21           EXTI_D3PMR1_MR21_Msk                        /*!< Pending Mask Event for line 21 */
+#define EXTI_D3PMR1_MR25_Pos       (24U)
+#define EXTI_D3PMR1_MR25_Msk       (0x1UL << EXTI_D3PMR1_MR25_Pos)             /*!< 0x01000000 */
+#define EXTI_D3PMR1_MR25           EXTI_D3PMR1_MR25_Msk                        /*!< Pending Mask Event for line 25 */
+
+/*******************  Bit definition for EXTI_D3PCR1L register  ****************/
+#define EXTI_D3PCR1L_PCS0_Pos       (0U)
+#define EXTI_D3PCR1L_PCS0_Msk       (0x3UL << EXTI_D3PCR1L_PCS0_Pos)           /*!< 0x00000003 */
+#define EXTI_D3PCR1L_PCS0           EXTI_D3PCR1L_PCS0_Msk                      /*!< D3 Pending request clear input signal selection on line 0 */
+#define EXTI_D3PCR1L_PCS1_Pos       (2U)
+#define EXTI_D3PCR1L_PCS1_Msk       (0x3UL << EXTI_D3PCR1L_PCS1_Pos)           /*!< 0x000000C0 */
+#define EXTI_D3PCR1L_PCS1           EXTI_D3PCR1L_PCS1_Msk                      /*!< D3 Pending request clear input signal selection on line 1 */
+#define EXTI_D3PCR1L_PCS2_Pos       (4U)
+#define EXTI_D3PCR1L_PCS2_Msk       (0x3UL << EXTI_D3PCR1L_PCS2_Pos)           /*!< 0x00000030 */
+#define EXTI_D3PCR1L_PCS2           EXTI_D3PCR1L_PCS2_Msk                      /*!< D3 Pending request clear input signal selection on line 2 */
+#define EXTI_D3PCR1L_PCS3_Pos       (6U)
+#define EXTI_D3PCR1L_PCS3_Msk       (0x3UL << EXTI_D3PCR1L_PCS3_Pos)           /*!< 0x000000C0 */
+#define EXTI_D3PCR1L_PCS3           EXTI_D3PCR1L_PCS3_Msk                      /*!< D3 Pending request clear input signal selection on line 3 */
+#define EXTI_D3PCR1L_PCS4_Pos       (8U)
+#define EXTI_D3PCR1L_PCS4_Msk       (0x3UL << EXTI_D3PCR1L_PCS4_Pos)           /*!< 0x00000300 */
+#define EXTI_D3PCR1L_PCS4           EXTI_D3PCR1L_PCS4_Msk                      /*!< D3 Pending request clear input signal selection on line 4 */
+#define EXTI_D3PCR1L_PCS5_Pos       (10U)
+#define EXTI_D3PCR1L_PCS5_Msk       (0x3UL << EXTI_D3PCR1L_PCS5_Pos)           /*!< 0x00000C00 */
+#define EXTI_D3PCR1L_PCS5           EXTI_D3PCR1L_PCS5_Msk                      /*!< D3 Pending request clear input signal selection on line 5 */
+#define EXTI_D3PCR1L_PCS6_Pos       (12U)
+#define EXTI_D3PCR1L_PCS6_Msk       (0x3UL << EXTI_D3PCR1L_PCS6_Pos)           /*!< 0x00003000 */
+#define EXTI_D3PCR1L_PCS6           EXTI_D3PCR1L_PCS6_Msk                      /*!< D3 Pending request clear input signal selection on line 6 */
+#define EXTI_D3PCR1L_PCS7_Pos       (14U)
+#define EXTI_D3PCR1L_PCS7_Msk       (0x3UL << EXTI_D3PCR1L_PCS7_Pos)           /*!< 0x0000C000 */
+#define EXTI_D3PCR1L_PCS7           EXTI_D3PCR1L_PCS7_Msk                      /*!< D3 Pending request clear input signal selection on line 7 */
+#define EXTI_D3PCR1L_PCS8_Pos       (16U)
+#define EXTI_D3PCR1L_PCS8_Msk       (0x3UL << EXTI_D3PCR1L_PCS8_Pos)           /*!< 0x00030000 */
+#define EXTI_D3PCR1L_PCS8           EXTI_D3PCR1L_PCS8_Msk                      /*!< D3 Pending request clear input signal selection on line 8 */
+#define EXTI_D3PCR1L_PCS9_Pos       (18U)
+#define EXTI_D3PCR1L_PCS9_Msk       (0x3UL << EXTI_D3PCR1L_PCS9_Pos)           /*!< 0x000C0000 */
+#define EXTI_D3PCR1L_PCS9           EXTI_D3PCR1L_PCS9_Msk                      /*!< D3 Pending request clear input signal selection on line 9 */
+#define EXTI_D3PCR1L_PCS10_Pos      (20U)
+#define EXTI_D3PCR1L_PCS10_Msk      (0x3UL << EXTI_D3PCR1L_PCS10_Pos)          /*!< 0x00300000 */
+#define EXTI_D3PCR1L_PCS10          EXTI_D3PCR1L_PCS10_Msk                     /*!< D3 Pending request clear input signal selection on line 10*/
+#define EXTI_D3PCR1L_PCS11_Pos      (22U)
+#define EXTI_D3PCR1L_PCS11_Msk      (0x3UL << EXTI_D3PCR1L_PCS11_Pos)          /*!< 0x00C00000 */
+#define EXTI_D3PCR1L_PCS11          EXTI_D3PCR1L_PCS11_Msk                     /*!< D3 Pending request clear input signal selection on line 11*/
+#define EXTI_D3PCR1L_PCS12_Pos      (24U)
+#define EXTI_D3PCR1L_PCS12_Msk      (0x3UL << EXTI_D3PCR1L_PCS12_Pos)          /*!< 0x03000000 */
+#define EXTI_D3PCR1L_PCS12          EXTI_D3PCR1L_PCS12_Msk                     /*!< D3 Pending request clear input signal selection on line 12*/
+#define EXTI_D3PCR1L_PCS13_Pos      (26U)
+#define EXTI_D3PCR1L_PCS13_Msk      (0x3UL << EXTI_D3PCR1L_PCS13_Pos)          /*!< 0x0C000000 */
+#define EXTI_D3PCR1L_PCS13          EXTI_D3PCR1L_PCS13_Msk                     /*!< D3 Pending request clear input signal selection on line 13*/
+#define EXTI_D3PCR1L_PCS14_Pos      (28U)
+#define EXTI_D3PCR1L_PCS14_Msk      (0x3UL << EXTI_D3PCR1L_PCS14_Pos)          /*!< 0x30000000 */
+#define EXTI_D3PCR1L_PCS14          EXTI_D3PCR1L_PCS14_Msk                     /*!< D3 Pending request clear input signal selection on line 14*/
+#define EXTI_D3PCR1L_PCS15_Pos      (30U)
+#define EXTI_D3PCR1L_PCS15_Msk      (0x3UL << EXTI_D3PCR1L_PCS15_Pos)          /*!< 0xC0000000 */
+#define EXTI_D3PCR1L_PCS15          EXTI_D3PCR1L_PCS15_Msk                     /*!< D3 Pending request clear input signal selection on line 15*/
+
+/*******************  Bit definition for EXTI_D3PCR1H register  ****************/
+#define EXTI_D3PCR1H_PCS19_Pos       (6U)
+#define EXTI_D3PCR1H_PCS19_Msk       (0x3UL << EXTI_D3PCR1H_PCS19_Pos)         /*!< 0x000000C0 */
+#define EXTI_D3PCR1H_PCS19           EXTI_D3PCR1H_PCS19_Msk                    /*!< D3 Pending request clear input signal selection on line 19 */
+#define EXTI_D3PCR1H_PCS20_Pos       (8U)
+#define EXTI_D3PCR1H_PCS20_Msk       (0x3UL << EXTI_D3PCR1H_PCS20_Pos)         /*!< 0x00000300 */
+#define EXTI_D3PCR1H_PCS20           EXTI_D3PCR1H_PCS20_Msk                    /*!< D3 Pending request clear input signal selection on line 20 */
+#define EXTI_D3PCR1H_PCS21_Pos       (10U)
+#define EXTI_D3PCR1H_PCS21_Msk       (0x3UL << EXTI_D3PCR1H_PCS21_Pos)         /*!< 0x00000C00 */
+#define EXTI_D3PCR1H_PCS21           EXTI_D3PCR1H_PCS21_Msk                    /*!< D3 Pending request clear input signal selection on line 21 */
+#define EXTI_D3PCR1H_PCS25_Pos       (18U)
+#define EXTI_D3PCR1H_PCS25_Msk       (0x3UL << EXTI_D3PCR1H_PCS25_Pos)         /*!< 0x000C0000 */
+#define EXTI_D3PCR1H_PCS25           EXTI_D3PCR1H_PCS25_Msk                    /*!< D3 Pending request clear input signal selection on line 25 */
+
+/******************  Bit definition for EXTI_RTSR2 register  *******************/
+#define EXTI_RTSR2_TR_Pos          (17U)
+#define EXTI_RTSR2_TR_Msk          (0x5UL << EXTI_RTSR2_TR_Pos)                /*!< 0x000A0000 */
+#define EXTI_RTSR2_TR              EXTI_RTSR2_TR_Msk                           /*!< Rising trigger event configuration bit */
+#define EXTI_RTSR2_TR49_Pos        (17U)
+#define EXTI_RTSR2_TR49_Msk        (0x1UL << EXTI_RTSR2_TR49_Pos)              /*!< 0x00020000 */
+#define EXTI_RTSR2_TR49            EXTI_RTSR2_TR49_Msk                         /*!< Rising trigger event configuration bit of line 49 */
+#define EXTI_RTSR2_TR51_Pos        (19U)
+#define EXTI_RTSR2_TR51_Msk        (0x1UL << EXTI_RTSR2_TR51_Pos)              /*!< 0x00080000 */
+#define EXTI_RTSR2_TR51            EXTI_RTSR2_TR51_Msk                         /*!< Rising trigger event configuration bit of line 51 */
+
+/******************  Bit definition for EXTI_FTSR2 register  *******************/
+#define EXTI_FTSR2_TR_Pos          (17U)
+#define EXTI_FTSR2_TR_Msk          (0x5UL << EXTI_FTSR2_TR_Pos)                /*!< 0x000A0000 */
+#define EXTI_FTSR2_TR              EXTI_FTSR2_TR_Msk                           /*!< Falling trigger event configuration bit */
+#define EXTI_FTSR2_TR49_Pos        (17U)
+#define EXTI_FTSR2_TR49_Msk        (0x1UL << EXTI_FTSR2_TR49_Pos)              /*!< 0x00020000 */
+#define EXTI_FTSR2_TR49            EXTI_FTSR2_TR49_Msk                         /*!< Falling trigger event configuration bit of line 49 */
+#define EXTI_FTSR2_TR51_Pos        (19U)
+#define EXTI_FTSR2_TR51_Msk        (0x1UL << EXTI_FTSR2_TR51_Pos)              /*!< 0x00080000 */
+#define EXTI_FTSR2_TR51            EXTI_FTSR2_TR51_Msk                         /*!< Falling trigger event configuration bit of line 51 */
+
+/******************  Bit definition for EXTI_SWIER2 register  ******************/
+#define EXTI_SWIER2_SWIER49_Pos    (17U)
+#define EXTI_SWIER2_SWIER49_Msk    (0x1UL << EXTI_SWIER2_SWIER49_Pos)          /*!< 0x00020000 */
+#define EXTI_SWIER2_SWIER49        EXTI_SWIER2_SWIER49_Msk                     /*!< Software Interrupt on line 49 */
+#define EXTI_SWIER2_SWIER51_Pos    (19U)
+#define EXTI_SWIER2_SWIER51_Msk    (0x1UL << EXTI_SWIER2_SWIER51_Pos)          /*!< 0x00080000 */
+#define EXTI_SWIER2_SWIER51        EXTI_SWIER2_SWIER51_Msk                     /*!< Software Interrupt on line 51 */
+
+/******************  Bit definition for EXTI_D3PMR2 register  ******************/
+#define EXTI_D3PMR2_MR34_Pos       (2U)
+#define EXTI_D3PMR2_MR34_Msk       (0x1UL << EXTI_D3PMR2_MR34_Pos)             /*!< 0x00000004 */
+#define EXTI_D3PMR2_MR34           EXTI_D3PMR2_MR34_Msk                        /*!< Pending Mask Event for line 34  */
+#define EXTI_D3PMR2_MR35_Pos       (3U)
+#define EXTI_D3PMR2_MR35_Msk       (0x1UL << EXTI_D3PMR2_MR35_Pos)             /*!< 0x00000008 */
+#define EXTI_D3PMR2_MR35           EXTI_D3PMR2_MR35_Msk                        /*!< Pending Mask Event for line 35  */
+#define EXTI_D3PMR2_MR41_Pos       (9U)
+#define EXTI_D3PMR2_MR41_Msk       (0x1UL << EXTI_D3PMR2_MR41_Pos)             /*!< 0x00000200 */
+#define EXTI_D3PMR2_MR41           EXTI_D3PMR2_MR41_Msk                        /*!< Pending Mask Event for line 41  */
+#define EXTI_D3PMR2_MR48_Pos       (16U)
+#define EXTI_D3PMR2_MR48_Msk       (0x1UL << EXTI_D3PMR2_MR48_Pos)             /*!< 0x00010000 */
+#define EXTI_D3PMR2_MR48           EXTI_D3PMR2_MR48_Msk                        /*!< Pending Mask Event for line 48  */
+#define EXTI_D3PMR2_MR49_Pos       (17U)
+#define EXTI_D3PMR2_MR49_Msk       (0x1UL << EXTI_D3PMR2_MR49_Pos)             /*!< 0x00020000 */
+#define EXTI_D3PMR2_MR49           EXTI_D3PMR2_MR49_Msk                        /*!< Pending Mask Event for line 49  */
+#define EXTI_D3PMR2_MR50_Pos       (18U)
+#define EXTI_D3PMR2_MR50_Msk       (0x1UL << EXTI_D3PMR2_MR50_Pos)             /*!< 0x00040000 */
+#define EXTI_D3PMR2_MR50           EXTI_D3PMR2_MR50_Msk                        /*!< Pending Mask Event for line 50  */
+#define EXTI_D3PMR2_MR51_Pos       (19U)
+#define EXTI_D3PMR2_MR51_Msk       (0x1UL << EXTI_D3PMR2_MR51_Pos)             /*!< 0x00080000 */
+#define EXTI_D3PMR2_MR51           EXTI_D3PMR2_MR51_Msk                        /*!< Pending Mask Event for line 51  */
+#define EXTI_D3PMR2_MR52_Pos       (20U)
+#define EXTI_D3PMR2_MR52_Msk       (0x1UL << EXTI_D3PMR2_MR52_Pos)             /*!< 0x00100000 */
+#define EXTI_D3PMR2_MR52           EXTI_D3PMR2_MR52_Msk                        /*!< Pending Mask Event for line 52  */
+#define EXTI_D3PMR2_MR53_Pos       (21U)
+#define EXTI_D3PMR2_MR53_Msk       (0x1UL << EXTI_D3PMR2_MR53_Pos)             /*!< 0x00200000 */
+#define EXTI_D3PMR2_MR53           EXTI_D3PMR2_MR53_Msk                        /*!< Pending Mask Event for line 53  */
+/*******************  Bit definition for EXTI_D3PCR2L register  ****************/
+#define EXTI_D3PCR2L_PCS34_Pos       (4U)
+#define EXTI_D3PCR2L_PCS34_Msk       (0x3UL << EXTI_D3PCR2L_PCS34_Pos)         /*!< 0x00000030 */
+#define EXTI_D3PCR2L_PCS34           EXTI_D3PCR2L_PCS34_Msk                    /*!< D3 Pending request clear input signal selection on line 34 */
+#define EXTI_D3PCR2L_PCS35_Pos       (6U)
+#define EXTI_D3PCR2L_PCS35_Msk       (0x3UL << EXTI_D3PCR2L_PCS35_Pos)         /*!< 0x000000C0 */
+#define EXTI_D3PCR2L_PCS35           EXTI_D3PCR2L_PCS35_Msk                    /*!< D3 Pending request clear input signal selection on line 35 */
+#define EXTI_D3PCR2L_PCS41_Pos       (18U)
+#define EXTI_D3PCR2L_PCS41_Msk       (0x3UL << EXTI_D3PCR2L_PCS41_Pos)         /*!< 0x000C0000 */
+#define EXTI_D3PCR2L_PCS41           EXTI_D3PCR2L_PCS41_Msk                    /*!< D3 Pending request clear input signal selection on line 41 */
+
+
+/*******************  Bit definition for EXTI_D3PCR2H register  ****************/
+#define EXTI_D3PCR2H_PCS48_Pos       (0U)
+#define EXTI_D3PCR2H_PCS48_Msk       (0x3UL << EXTI_D3PCR2H_PCS48_Pos)         /*!< 0x00000003 */
+#define EXTI_D3PCR2H_PCS48           EXTI_D3PCR2H_PCS48_Msk                    /*!< D3 Pending request clear input signal selection on line 48 */
+#define EXTI_D3PCR2H_PCS49_Pos       (2U)
+#define EXTI_D3PCR2H_PCS49_Msk       (0x3UL << EXTI_D3PCR2H_PCS49_Pos)         /*!< 0x0000000C */
+#define EXTI_D3PCR2H_PCS49           EXTI_D3PCR2H_PCS49_Msk                    /*!< D3 Pending request clear input signal selection on line 49 */
+#define EXTI_D3PCR2H_PCS50_Pos       (4U)
+#define EXTI_D3PCR2H_PCS50_Msk       (0x3UL << EXTI_D3PCR2H_PCS50_Pos)         /*!< 0x00000030 */
+#define EXTI_D3PCR2H_PCS50           EXTI_D3PCR2H_PCS50_Msk                    /*!< D3 Pending request clear input signal selection on line 50 */
+#define EXTI_D3PCR2H_PCS51_Pos       (6U)
+#define EXTI_D3PCR2H_PCS51_Msk       (0x3UL << EXTI_D3PCR2H_PCS51_Pos)         /*!< 0x000000C0 */
+#define EXTI_D3PCR2H_PCS51           EXTI_D3PCR2H_PCS51_Msk                    /*!< D3 Pending request clear input signal selection on line 51 */
+#define EXTI_D3PCR2H_PCS52_Pos       (8U)
+#define EXTI_D3PCR2H_PCS52_Msk       (0x3UL << EXTI_D3PCR2H_PCS52_Pos)         /*!< 0x00000300 */
+#define EXTI_D3PCR2H_PCS52           EXTI_D3PCR2H_PCS52_Msk                    /*!< D3 Pending request clear input signal selection on line 52 */
+#define EXTI_D3PCR2H_PCS53_Pos       (10U)
+#define EXTI_D3PCR2H_PCS53_Msk       (0x3UL << EXTI_D3PCR2H_PCS53_Pos)         /*!< 0x00000C00 */
+#define EXTI_D3PCR2H_PCS53           EXTI_D3PCR2H_PCS53_Msk                    /*!< D3 Pending request clear input signal selection on line 53 */
+/******************  Bit definition for EXTI_RTSR3 register  *******************/
+#define EXTI_RTSR3_TR_Pos          (18U)
+#define EXTI_RTSR3_TR_Msk          (0x1DUL << EXTI_RTSR3_TR_Pos)               /*!< 0x00740000 */
+#define EXTI_RTSR3_TR              EXTI_RTSR3_TR_Msk                           /*!< Rising trigger event configuration bit */
+#define EXTI_RTSR3_TR82_Pos        (18U)
+#define EXTI_RTSR3_TR82_Msk        (0x1UL << EXTI_RTSR3_TR82_Pos)              /*!< 0x00040000 */
+#define EXTI_RTSR3_TR82            EXTI_RTSR3_TR82_Msk                         /*!< Rising trigger event configuration bit of line 82 */
+#define EXTI_RTSR3_TR84_Pos        (20U)
+#define EXTI_RTSR3_TR84_Msk        (0x1UL << EXTI_RTSR3_TR84_Pos)              /*!< 0x00100000 */
+#define EXTI_RTSR3_TR84            EXTI_RTSR3_TR84_Msk                         /*!< Rising trigger event configuration bit of line 84 */
+#define EXTI_RTSR3_TR85_Pos        (21U)
+#define EXTI_RTSR3_TR85_Msk        (0x1UL << EXTI_RTSR3_TR85_Pos)              /*!< 0x00200000 */
+#define EXTI_RTSR3_TR85            EXTI_RTSR3_TR85_Msk                         /*!< Rising trigger event configuration bit of line 85 */
+#define EXTI_RTSR3_TR86_Pos        (22U)
+#define EXTI_RTSR3_TR86_Msk        (0x1UL << EXTI_RTSR3_TR86_Pos)              /*!< 0x00400000 */
+#define EXTI_RTSR3_TR86            EXTI_RTSR3_TR86_Msk                         /*!< Rising trigger event configuration bit of line 86 */
+
+/******************  Bit definition for EXTI_FTSR3 register  *******************/
+#define EXTI_FTSR3_TR_Pos          (18U)
+#define EXTI_FTSR3_TR_Msk          (0x1DUL << EXTI_FTSR3_TR_Pos)               /*!< 0x00740000 */
+#define EXTI_FTSR3_TR              EXTI_FTSR3_TR_Msk                           /*!< Falling trigger event configuration bit */
+#define EXTI_FTSR3_TR82_Pos        (18U)
+#define EXTI_FTSR3_TR82_Msk        (0x1UL << EXTI_FTSR3_TR82_Pos)              /*!< 0x00040000 */
+#define EXTI_FTSR3_TR82            EXTI_FTSR3_TR82_Msk                         /*!< Falling trigger event configuration bit of line 82 */
+#define EXTI_FTSR3_TR84_Pos        (20U)
+#define EXTI_FTSR3_TR84_Msk        (0x1UL << EXTI_FTSR3_TR84_Pos)              /*!< 0x00100000 */
+#define EXTI_FTSR3_TR84            EXTI_FTSR3_TR84_Msk                         /*!< Falling trigger event configuration bit of line 84 */
+#define EXTI_FTSR3_TR85_Pos        (21U)
+#define EXTI_FTSR3_TR85_Msk        (0x1UL << EXTI_FTSR3_TR85_Pos)              /*!< 0x00200000 */
+#define EXTI_FTSR3_TR85            EXTI_FTSR3_TR85_Msk                         /*!< Falling trigger event configuration bit of line 85 */
+#define EXTI_FTSR3_TR86_Pos        (22U)
+#define EXTI_FTSR3_TR86_Msk        (0x1UL << EXTI_FTSR3_TR86_Pos)              /*!< 0x00400000 */
+#define EXTI_FTSR3_TR86            EXTI_FTSR3_TR86_Msk                         /*!< Falling trigger event configuration bit of line 86 */
+
+/******************  Bit definition for EXTI_SWIER3 register  ******************/
+#define EXTI_SWIER3_SWI_Pos        (18U)
+#define EXTI_SWIER3_SWI_Msk        (0x1DUL << EXTI_SWIER3_SWI_Pos)             /*!< 0x00740000 */
+#define EXTI_SWIER3_SWI            EXTI_SWIER3_SWI_Msk                         /*!< Software Interrupt event bit */
+#define EXTI_SWIER3_SWIER82_Pos    (18U)
+#define EXTI_SWIER3_SWIER82_Msk    (0x1UL << EXTI_SWIER3_SWIER82_Pos)          /*!< 0x00040000 */
+#define EXTI_SWIER3_SWIER82        EXTI_SWIER3_SWIER82_Msk                     /*!< Software Interrupt on line 82 */
+#define EXTI_SWIER3_SWIER84_Pos    (20U)
+#define EXTI_SWIER3_SWIER84_Msk    (0x1UL << EXTI_SWIER3_SWIER84_Pos)          /*!< 0x00100000 */
+#define EXTI_SWIER3_SWIER84        EXTI_SWIER3_SWIER84_Msk                     /*!< Software Interrupt on line 84 */
+#define EXTI_SWIER3_SWIER85_Pos    (21U)
+#define EXTI_SWIER3_SWIER85_Msk    (0x1UL << EXTI_SWIER3_SWIER85_Pos)          /*!< 0x00200000 */
+#define EXTI_SWIER3_SWIER85        EXTI_SWIER3_SWIER85_Msk                     /*!< Software Interrupt on line 85 */
+#define EXTI_SWIER3_SWIER86_Pos    (22U)
+#define EXTI_SWIER3_SWIER86_Msk    (0x1UL << EXTI_SWIER3_SWIER86_Pos)          /*!< 0x00400000 */
+#define EXTI_SWIER3_SWIER86        EXTI_SWIER3_SWIER86_Msk                     /*!< Software Interrupt on line 86 */
+
+/*******************  Bit definition for EXTI_IMR1 register  *******************/
+#define EXTI_IMR1_IM_Pos           (0U)
+#define EXTI_IMR1_IM_Msk           (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos)          /*!< 0xFFFFFFFF */
+#define EXTI_IMR1_IM               EXTI_IMR1_IM_Msk                            /*!< Interrupt Mask */
+#define EXTI_IMR1_IM0_Pos          (0U)
+#define EXTI_IMR1_IM0_Msk          (0x1UL << EXTI_IMR1_IM0_Pos)                /*!< 0x00000001 */
+#define EXTI_IMR1_IM0              EXTI_IMR1_IM0_Msk                           /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR1_IM1_Pos          (1U)
+#define EXTI_IMR1_IM1_Msk          (0x1UL << EXTI_IMR1_IM1_Pos)                /*!< 0x00000002 */
+#define EXTI_IMR1_IM1              EXTI_IMR1_IM1_Msk                           /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR1_IM2_Pos          (2U)
+#define EXTI_IMR1_IM2_Msk          (0x1UL << EXTI_IMR1_IM2_Pos)                /*!< 0x00000004 */
+#define EXTI_IMR1_IM2              EXTI_IMR1_IM2_Msk                           /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR1_IM3_Pos          (3U)
+#define EXTI_IMR1_IM3_Msk          (0x1UL << EXTI_IMR1_IM3_Pos)                /*!< 0x00000008 */
+#define EXTI_IMR1_IM3              EXTI_IMR1_IM3_Msk                           /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR1_IM4_Pos          (4U)
+#define EXTI_IMR1_IM4_Msk          (0x1UL << EXTI_IMR1_IM4_Pos)                /*!< 0x00000010 */
+#define EXTI_IMR1_IM4              EXTI_IMR1_IM4_Msk                           /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR1_IM5_Pos          (5U)
+#define EXTI_IMR1_IM5_Msk          (0x1UL << EXTI_IMR1_IM5_Pos)                /*!< 0x00000020 */
+#define EXTI_IMR1_IM5              EXTI_IMR1_IM5_Msk                           /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR1_IM6_Pos          (6U)
+#define EXTI_IMR1_IM6_Msk          (0x1UL << EXTI_IMR1_IM6_Pos)                /*!< 0x00000040 */
+#define EXTI_IMR1_IM6              EXTI_IMR1_IM6_Msk                           /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR1_IM7_Pos          (7U)
+#define EXTI_IMR1_IM7_Msk          (0x1UL << EXTI_IMR1_IM7_Pos)                /*!< 0x00000080 */
+#define EXTI_IMR1_IM7              EXTI_IMR1_IM7_Msk                           /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR1_IM8_Pos          (8U)
+#define EXTI_IMR1_IM8_Msk          (0x1UL << EXTI_IMR1_IM8_Pos)                /*!< 0x00000100 */
+#define EXTI_IMR1_IM8              EXTI_IMR1_IM8_Msk                           /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR1_IM9_Pos          (9U)
+#define EXTI_IMR1_IM9_Msk          (0x1UL << EXTI_IMR1_IM9_Pos)                /*!< 0x00000200 */
+#define EXTI_IMR1_IM9              EXTI_IMR1_IM9_Msk                           /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR1_IM10_Pos         (10U)
+#define EXTI_IMR1_IM10_Msk         (0x1UL << EXTI_IMR1_IM10_Pos)               /*!< 0x00000400 */
+#define EXTI_IMR1_IM10             EXTI_IMR1_IM10_Msk                          /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR1_IM11_Pos         (11U)
+#define EXTI_IMR1_IM11_Msk         (0x1UL << EXTI_IMR1_IM11_Pos)               /*!< 0x00000800 */
+#define EXTI_IMR1_IM11             EXTI_IMR1_IM11_Msk                          /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR1_IM12_Pos         (12U)
+#define EXTI_IMR1_IM12_Msk         (0x1UL << EXTI_IMR1_IM12_Pos)               /*!< 0x00001000 */
+#define EXTI_IMR1_IM12             EXTI_IMR1_IM12_Msk                          /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR1_IM13_Pos         (13U)
+#define EXTI_IMR1_IM13_Msk         (0x1UL << EXTI_IMR1_IM13_Pos)               /*!< 0x00002000 */
+#define EXTI_IMR1_IM13             EXTI_IMR1_IM13_Msk                          /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR1_IM14_Pos         (14U)
+#define EXTI_IMR1_IM14_Msk         (0x1UL << EXTI_IMR1_IM14_Pos)               /*!< 0x00004000 */
+#define EXTI_IMR1_IM14             EXTI_IMR1_IM14_Msk                          /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR1_IM15_Pos         (15U)
+#define EXTI_IMR1_IM15_Msk         (0x1UL << EXTI_IMR1_IM15_Pos)               /*!< 0x00008000 */
+#define EXTI_IMR1_IM15             EXTI_IMR1_IM15_Msk                          /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR1_IM16_Pos         (16U)
+#define EXTI_IMR1_IM16_Msk         (0x1UL << EXTI_IMR1_IM16_Pos)               /*!< 0x00010000 */
+#define EXTI_IMR1_IM16             EXTI_IMR1_IM16_Msk                          /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR1_IM17_Pos         (17U)
+#define EXTI_IMR1_IM17_Msk         (0x1UL << EXTI_IMR1_IM17_Pos)               /*!< 0x00020000 */
+#define EXTI_IMR1_IM17             EXTI_IMR1_IM17_Msk                          /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR1_IM18_Pos         (18U)
+#define EXTI_IMR1_IM18_Msk         (0x1UL << EXTI_IMR1_IM18_Pos)               /*!< 0x00040000 */
+#define EXTI_IMR1_IM18             EXTI_IMR1_IM18_Msk                          /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR1_IM19_Pos         (19U)
+#define EXTI_IMR1_IM19_Msk         (0x1UL << EXTI_IMR1_IM19_Pos)               /*!< 0x00080000 */
+#define EXTI_IMR1_IM19             EXTI_IMR1_IM19_Msk                          /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR1_IM20_Pos         (20U)
+#define EXTI_IMR1_IM20_Msk         (0x1UL << EXTI_IMR1_IM20_Pos)               /*!< 0x00100000 */
+#define EXTI_IMR1_IM20             EXTI_IMR1_IM20_Msk                          /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR1_IM21_Pos         (21U)
+#define EXTI_IMR1_IM21_Msk         (0x1UL << EXTI_IMR1_IM21_Pos)               /*!< 0x00200000 */
+#define EXTI_IMR1_IM21             EXTI_IMR1_IM21_Msk                          /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR1_IM22_Pos         (22U)
+#define EXTI_IMR1_IM22_Msk         (0x1UL << EXTI_IMR1_IM22_Pos)               /*!< 0x00400000 */
+#define EXTI_IMR1_IM22             EXTI_IMR1_IM22_Msk                          /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR1_IM23_Pos         (23U)
+#define EXTI_IMR1_IM23_Msk         (0x1UL << EXTI_IMR1_IM23_Pos)               /*!< 0x00800000 */
+#define EXTI_IMR1_IM23             EXTI_IMR1_IM23_Msk                          /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR1_IM24_Pos         (24U)
+#define EXTI_IMR1_IM24_Msk         (0x1UL << EXTI_IMR1_IM24_Pos)               /*!< 0x01000000 */
+#define EXTI_IMR1_IM24             EXTI_IMR1_IM24_Msk                          /*!< Interrupt Mask on line 24 */
+#define EXTI_IMR1_IM25_Pos         (25U)
+#define EXTI_IMR1_IM25_Msk         (0x1UL << EXTI_IMR1_IM25_Pos)               /*!< 0x02000000 */
+#define EXTI_IMR1_IM25             EXTI_IMR1_IM25_Msk                          /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR1_IM26_Pos         (26U)
+#define EXTI_IMR1_IM26_Msk         (0x1UL << EXTI_IMR1_IM26_Pos)               /*!< 0x04000000 */
+#define EXTI_IMR1_IM26             EXTI_IMR1_IM26_Msk                          /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR1_IM27_Pos         (27U)
+#define EXTI_IMR1_IM27_Msk         (0x1UL << EXTI_IMR1_IM27_Pos)               /*!< 0x08000000 */
+#define EXTI_IMR1_IM27             EXTI_IMR1_IM27_Msk                          /*!< Interrupt Mask on line 27 */
+#define EXTI_IMR1_IM28_Pos         (28U)
+#define EXTI_IMR1_IM28_Msk         (0x1UL << EXTI_IMR1_IM28_Pos)               /*!< 0x10000000 */
+#define EXTI_IMR1_IM28             EXTI_IMR1_IM28_Msk                          /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR1_IM29_Pos         (29U)
+#define EXTI_IMR1_IM29_Msk         (0x1UL << EXTI_IMR1_IM29_Pos)               /*!< 0x20000000 */
+#define EXTI_IMR1_IM29             EXTI_IMR1_IM29_Msk                          /*!< Interrupt Mask on line 29 */
+#define EXTI_IMR1_IM30_Pos         (30U)
+#define EXTI_IMR1_IM30_Msk         (0x1UL << EXTI_IMR1_IM30_Pos)               /*!< 0x40000000 */
+#define EXTI_IMR1_IM30             EXTI_IMR1_IM30_Msk                          /*!< Interrupt Mask on line 30 */
+#define EXTI_IMR1_IM31_Pos         (31U)
+#define EXTI_IMR1_IM31_Msk         (0x1UL << EXTI_IMR1_IM31_Pos)               /*!< 0x80000000 */
+#define EXTI_IMR1_IM31             EXTI_IMR1_IM31_Msk                          /*!< Interrupt Mask on line 31 */
+
+/*******************  Bit definition for EXTI_EMR1 register  *******************/
+#define EXTI_EMR1_EM_Pos           (0U)
+#define EXTI_EMR1_EM_Msk           (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos)          /*!< 0xFFFFFFFF */
+#define EXTI_EMR1_EM               EXTI_EMR1_EM_Msk                            /*!< Event Mask */
+#define EXTI_EMR1_EM0_Pos          (0U)
+#define EXTI_EMR1_EM0_Msk          (0x1UL << EXTI_EMR1_EM0_Pos)                /*!< 0x00000001 */
+#define EXTI_EMR1_EM0              EXTI_EMR1_EM0_Msk                           /*!< Event Mask on line 0 */
+#define EXTI_EMR1_EM1_Pos          (1U)
+#define EXTI_EMR1_EM1_Msk          (0x1UL << EXTI_EMR1_EM1_Pos)                /*!< 0x00000002 */
+#define EXTI_EMR1_EM1              EXTI_EMR1_EM1_Msk                           /*!< Event Mask on line 1 */
+#define EXTI_EMR1_EM2_Pos          (2U)
+#define EXTI_EMR1_EM2_Msk          (0x1UL << EXTI_EMR1_EM2_Pos)                /*!< 0x00000004 */
+#define EXTI_EMR1_EM2              EXTI_EMR1_EM2_Msk                           /*!< Event Mask on line 2 */
+#define EXTI_EMR1_EM3_Pos          (3U)
+#define EXTI_EMR1_EM3_Msk          (0x1UL << EXTI_EMR1_EM3_Pos)                /*!< 0x00000008 */
+#define EXTI_EMR1_EM3              EXTI_EMR1_EM3_Msk                           /*!< Event Mask on line 3 */
+#define EXTI_EMR1_EM4_Pos          (4U)
+#define EXTI_EMR1_EM4_Msk          (0x1UL << EXTI_EMR1_EM4_Pos)                /*!< 0x00000010 */
+#define EXTI_EMR1_EM4              EXTI_EMR1_EM4_Msk                           /*!< Event Mask on line 4 */
+#define EXTI_EMR1_EM5_Pos          (5U)
+#define EXTI_EMR1_EM5_Msk          (0x1UL << EXTI_EMR1_EM5_Pos)                /*!< 0x00000020 */
+#define EXTI_EMR1_EM5              EXTI_EMR1_EM5_Msk                           /*!< Event Mask on line 5 */
+#define EXTI_EMR1_EM6_Pos          (6U)
+#define EXTI_EMR1_EM6_Msk          (0x1UL << EXTI_EMR1_EM6_Pos)                /*!< 0x00000040 */
+#define EXTI_EMR1_EM6              EXTI_EMR1_EM6_Msk                           /*!< Event Mask on line 6 */
+#define EXTI_EMR1_EM7_Pos          (7U)
+#define EXTI_EMR1_EM7_Msk          (0x1UL << EXTI_EMR1_EM7_Pos)                /*!< 0x00000080 */
+#define EXTI_EMR1_EM7              EXTI_EMR1_EM7_Msk                           /*!< Event Mask on line 7 */
+#define EXTI_EMR1_EM8_Pos          (8U)
+#define EXTI_EMR1_EM8_Msk          (0x1UL << EXTI_EMR1_EM8_Pos)                /*!< 0x00000100 */
+#define EXTI_EMR1_EM8              EXTI_EMR1_EM8_Msk                           /*!< Event Mask on line 8 */
+#define EXTI_EMR1_EM9_Pos          (9U)
+#define EXTI_EMR1_EM9_Msk          (0x1UL << EXTI_EMR1_EM9_Pos)                /*!< 0x00000200 */
+#define EXTI_EMR1_EM9              EXTI_EMR1_EM9_Msk                           /*!< Event Mask on line 9 */
+#define EXTI_EMR1_EM10_Pos         (10U)
+#define EXTI_EMR1_EM10_Msk         (0x1UL << EXTI_EMR1_EM10_Pos)               /*!< 0x00000400 */
+#define EXTI_EMR1_EM10             EXTI_EMR1_EM10_Msk                          /*!< Event Mask on line 10 */
+#define EXTI_EMR1_EM11_Pos         (11U)
+#define EXTI_EMR1_EM11_Msk         (0x1UL << EXTI_EMR1_EM11_Pos)               /*!< 0x00000800 */
+#define EXTI_EMR1_EM11             EXTI_EMR1_EM11_Msk                          /*!< Event Mask on line 11 */
+#define EXTI_EMR1_EM12_Pos         (12U)
+#define EXTI_EMR1_EM12_Msk         (0x1UL << EXTI_EMR1_EM12_Pos)               /*!< 0x00001000 */
+#define EXTI_EMR1_EM12             EXTI_EMR1_EM12_Msk                          /*!< Event Mask on line 12 */
+#define EXTI_EMR1_EM13_Pos         (13U)
+#define EXTI_EMR1_EM13_Msk         (0x1UL << EXTI_EMR1_EM13_Pos)               /*!< 0x00002000 */
+#define EXTI_EMR1_EM13             EXTI_EMR1_EM13_Msk                          /*!< Event Mask on line 13 */
+#define EXTI_EMR1_EM14_Pos         (14U)
+#define EXTI_EMR1_EM14_Msk         (0x1UL << EXTI_EMR1_EM14_Pos)               /*!< 0x00004000 */
+#define EXTI_EMR1_EM14             EXTI_EMR1_EM14_Msk                          /*!< Event Mask on line 14 */
+#define EXTI_EMR1_EM15_Pos         (15U)
+#define EXTI_EMR1_EM15_Msk         (0x1UL << EXTI_EMR1_EM15_Pos)               /*!< 0x00008000 */
+#define EXTI_EMR1_EM15             EXTI_EMR1_EM15_Msk                          /*!< Event Mask on line 15 */
+#define EXTI_EMR1_EM16_Pos         (16U)
+#define EXTI_EMR1_EM16_Msk         (0x1UL << EXTI_EMR1_EM16_Pos)               /*!< 0x00010000 */
+#define EXTI_EMR1_EM16             EXTI_EMR1_EM16_Msk                          /*!< Event Mask on line 16 */
+#define EXTI_EMR1_EM17_Pos         (17U)
+#define EXTI_EMR1_EM17_Msk         (0x1UL << EXTI_EMR1_EM17_Pos)               /*!< 0x00020000 */
+#define EXTI_EMR1_EM17             EXTI_EMR1_EM17_Msk                          /*!< Event Mask on line 17 */
+#define EXTI_EMR1_EM18_Pos         (18U)
+#define EXTI_EMR1_EM18_Msk         (0x1UL << EXTI_EMR1_EM18_Pos)               /*!< 0x00040000 */
+#define EXTI_EMR1_EM18             EXTI_EMR1_EM18_Msk                          /*!< Event Mask on line 18 */
+#define EXTI_EMR1_EM20_Pos         (20U)
+#define EXTI_EMR1_EM20_Msk         (0x1UL << EXTI_EMR1_EM20_Pos)               /*!< 0x00100000 */
+#define EXTI_EMR1_EM20             EXTI_EMR1_EM20_Msk                          /*!< Event Mask on line 20 */
+#define EXTI_EMR1_EM21_Pos         (21U)
+#define EXTI_EMR1_EM21_Msk         (0x1UL << EXTI_EMR1_EM21_Pos)               /*!< 0x00200000 */
+#define EXTI_EMR1_EM21             EXTI_EMR1_EM21_Msk                          /*!< Event Mask on line 21 */
+#define EXTI_EMR1_EM22_Pos         (22U)
+#define EXTI_EMR1_EM22_Msk         (0x1UL << EXTI_EMR1_EM22_Pos)               /*!< 0x00400000 */
+#define EXTI_EMR1_EM22             EXTI_EMR1_EM22_Msk                          /*!< Event Mask on line 22 */
+#define EXTI_EMR1_EM23_Pos         (23U)
+#define EXTI_EMR1_EM23_Msk         (0x1UL << EXTI_EMR1_EM23_Pos)               /*!< 0x00800000 */
+#define EXTI_EMR1_EM23             EXTI_EMR1_EM23_Msk                          /*!< Event Mask on line 23 */
+#define EXTI_EMR1_EM24_Pos         (24U)
+#define EXTI_EMR1_EM24_Msk         (0x1UL << EXTI_EMR1_EM24_Pos)               /*!< 0x01000000 */
+#define EXTI_EMR1_EM24             EXTI_EMR1_EM24_Msk                          /*!< Event Mask on line 24 */
+#define EXTI_EMR1_EM25_Pos         (25U)
+#define EXTI_EMR1_EM25_Msk         (0x1UL << EXTI_EMR1_EM25_Pos)               /*!< 0x02000000 */
+#define EXTI_EMR1_EM25             EXTI_EMR1_EM25_Msk                          /*!< Event Mask on line 25 */
+#define EXTI_EMR1_EM26_Pos         (26U)
+#define EXTI_EMR1_EM26_Msk         (0x1UL << EXTI_EMR1_EM26_Pos)               /*!< 0x04000000 */
+#define EXTI_EMR1_EM26             EXTI_EMR1_EM26_Msk                          /*!< Event Mask on line 26 */
+#define EXTI_EMR1_EM27_Pos         (27U)
+#define EXTI_EMR1_EM27_Msk         (0x1UL << EXTI_EMR1_EM27_Pos)               /*!< 0x08000000 */
+#define EXTI_EMR1_EM27             EXTI_EMR1_EM27_Msk                          /*!< Event Mask on line 27 */
+#define EXTI_EMR1_EM28_Pos         (28U)
+#define EXTI_EMR1_EM28_Msk         (0x1UL << EXTI_EMR1_EM28_Pos)               /*!< 0x10000000 */
+#define EXTI_EMR1_EM28             EXTI_EMR1_EM28_Msk                          /*!< Event Mask on line 28 */
+#define EXTI_EMR1_EM29_Pos         (29U)
+#define EXTI_EMR1_EM29_Msk         (0x1UL << EXTI_EMR1_EM29_Pos)               /*!< 0x20000000 */
+#define EXTI_EMR1_EM29             EXTI_EMR1_EM29_Msk                          /*!< Event Mask on line 29 */
+#define EXTI_EMR1_EM30_Pos         (30U)
+#define EXTI_EMR1_EM30_Msk         (0x1UL << EXTI_EMR1_EM30_Pos)               /*!< 0x40000000 */
+#define EXTI_EMR1_EM30             EXTI_EMR1_EM30_Msk                          /*!< Event Mask on line 30 */
+#define EXTI_EMR1_EM31_Pos         (31U)
+#define EXTI_EMR1_EM31_Msk         (0x1UL << EXTI_EMR1_EM31_Pos)               /*!< 0x80000000 */
+#define EXTI_EMR1_EM31             EXTI_EMR1_EM31_Msk                          /*!< Event Mask on line 31 */
+
+/*******************  Bit definition for EXTI_PR1 register  ********************/
+#define EXTI_PR1_PR_Pos            (0U)
+#define EXTI_PR1_PR_Msk            (0x3FFFFFUL << EXTI_PR1_PR_Pos)             /*!< 0x003FFFFF */
+#define EXTI_PR1_PR                EXTI_PR1_PR_Msk                             /*!< Pending bit */
+#define EXTI_PR1_PR0_Pos           (0U)
+#define EXTI_PR1_PR0_Msk           (0x1UL << EXTI_PR1_PR0_Pos)                 /*!< 0x00000001 */
+#define EXTI_PR1_PR0               EXTI_PR1_PR0_Msk                            /*!< Pending bit for line 0 */
+#define EXTI_PR1_PR1_Pos           (1U)
+#define EXTI_PR1_PR1_Msk           (0x1UL << EXTI_PR1_PR1_Pos)                 /*!< 0x00000002 */
+#define EXTI_PR1_PR1               EXTI_PR1_PR1_Msk                            /*!< Pending bit for line 1 */
+#define EXTI_PR1_PR2_Pos           (2U)
+#define EXTI_PR1_PR2_Msk           (0x1UL << EXTI_PR1_PR2_Pos)                 /*!< 0x00000004 */
+#define EXTI_PR1_PR2               EXTI_PR1_PR2_Msk                            /*!< Pending bit for line 2 */
+#define EXTI_PR1_PR3_Pos           (3U)
+#define EXTI_PR1_PR3_Msk           (0x1UL << EXTI_PR1_PR3_Pos)                 /*!< 0x00000008 */
+#define EXTI_PR1_PR3               EXTI_PR1_PR3_Msk                            /*!< Pending bit for line 3 */
+#define EXTI_PR1_PR4_Pos           (4U)
+#define EXTI_PR1_PR4_Msk           (0x1UL << EXTI_PR1_PR4_Pos)                 /*!< 0x00000010 */
+#define EXTI_PR1_PR4               EXTI_PR1_PR4_Msk                            /*!< Pending bit for line 4 */
+#define EXTI_PR1_PR5_Pos           (5U)
+#define EXTI_PR1_PR5_Msk           (0x1UL << EXTI_PR1_PR5_Pos)                 /*!< 0x00000020 */
+#define EXTI_PR1_PR5               EXTI_PR1_PR5_Msk                            /*!< Pending bit for line 5 */
+#define EXTI_PR1_PR6_Pos           (6U)
+#define EXTI_PR1_PR6_Msk           (0x1UL << EXTI_PR1_PR6_Pos)                 /*!< 0x00000040 */
+#define EXTI_PR1_PR6               EXTI_PR1_PR6_Msk                            /*!< Pending bit for line 6 */
+#define EXTI_PR1_PR7_Pos           (7U)
+#define EXTI_PR1_PR7_Msk           (0x1UL << EXTI_PR1_PR7_Pos)                 /*!< 0x00000080 */
+#define EXTI_PR1_PR7               EXTI_PR1_PR7_Msk                            /*!< Pending bit for line 7 */
+#define EXTI_PR1_PR8_Pos           (8U)
+#define EXTI_PR1_PR8_Msk           (0x1UL << EXTI_PR1_PR8_Pos)                 /*!< 0x00000100 */
+#define EXTI_PR1_PR8               EXTI_PR1_PR8_Msk                            /*!< Pending bit for line 8 */
+#define EXTI_PR1_PR9_Pos           (9U)
+#define EXTI_PR1_PR9_Msk           (0x1UL << EXTI_PR1_PR9_Pos)                 /*!< 0x00000200 */
+#define EXTI_PR1_PR9               EXTI_PR1_PR9_Msk                            /*!< Pending bit for line 9 */
+#define EXTI_PR1_PR10_Pos          (10U)
+#define EXTI_PR1_PR10_Msk          (0x1UL << EXTI_PR1_PR10_Pos)                /*!< 0x00000400 */
+#define EXTI_PR1_PR10              EXTI_PR1_PR10_Msk                           /*!< Pending bit for line 10 */
+#define EXTI_PR1_PR11_Pos          (11U)
+#define EXTI_PR1_PR11_Msk          (0x1UL << EXTI_PR1_PR11_Pos)                /*!< 0x00000800 */
+#define EXTI_PR1_PR11              EXTI_PR1_PR11_Msk                           /*!< Pending bit for line 11 */
+#define EXTI_PR1_PR12_Pos          (12U)
+#define EXTI_PR1_PR12_Msk          (0x1UL << EXTI_PR1_PR12_Pos)                /*!< 0x00001000 */
+#define EXTI_PR1_PR12              EXTI_PR1_PR12_Msk                           /*!< Pending bit for line 12 */
+#define EXTI_PR1_PR13_Pos          (13U)
+#define EXTI_PR1_PR13_Msk          (0x1UL << EXTI_PR1_PR13_Pos)                /*!< 0x00002000 */
+#define EXTI_PR1_PR13              EXTI_PR1_PR13_Msk                           /*!< Pending bit for line 13 */
+#define EXTI_PR1_PR14_Pos          (14U)
+#define EXTI_PR1_PR14_Msk          (0x1UL << EXTI_PR1_PR14_Pos)                /*!< 0x00004000 */
+#define EXTI_PR1_PR14              EXTI_PR1_PR14_Msk                           /*!< Pending bit for line 14 */
+#define EXTI_PR1_PR15_Pos          (15U)
+#define EXTI_PR1_PR15_Msk          (0x1UL << EXTI_PR1_PR15_Pos)                /*!< 0x00008000 */
+#define EXTI_PR1_PR15              EXTI_PR1_PR15_Msk                           /*!< Pending bit for line 15 */
+#define EXTI_PR1_PR16_Pos          (16U)
+#define EXTI_PR1_PR16_Msk          (0x1UL << EXTI_PR1_PR16_Pos)                /*!< 0x00010000 */
+#define EXTI_PR1_PR16              EXTI_PR1_PR16_Msk                           /*!< Pending bit for line 16 */
+#define EXTI_PR1_PR17_Pos          (17U)
+#define EXTI_PR1_PR17_Msk          (0x1UL << EXTI_PR1_PR17_Pos)                /*!< 0x00020000 */
+#define EXTI_PR1_PR17              EXTI_PR1_PR17_Msk                           /*!< Pending bit for line 17 */
+#define EXTI_PR1_PR18_Pos          (18U)
+#define EXTI_PR1_PR18_Msk          (0x1UL << EXTI_PR1_PR18_Pos)                /*!< 0x00040000 */
+#define EXTI_PR1_PR18              EXTI_PR1_PR18_Msk                           /*!< Pending bit for line 18 */
+#define EXTI_PR1_PR19_Pos          (19U)
+#define EXTI_PR1_PR19_Msk          (0x1UL << EXTI_PR1_PR19_Pos)                /*!< 0x00080000 */
+#define EXTI_PR1_PR19              EXTI_PR1_PR19_Msk                           /*!< Pending bit for line 19 */
+#define EXTI_PR1_PR20_Pos          (20U)
+#define EXTI_PR1_PR20_Msk          (0x1UL << EXTI_PR1_PR20_Pos)                /*!< 0x00100000 */
+#define EXTI_PR1_PR20              EXTI_PR1_PR20_Msk                           /*!< Pending bit for line 20 */
+#define EXTI_PR1_PR21_Pos          (21U)
+#define EXTI_PR1_PR21_Msk          (0x1UL << EXTI_PR1_PR21_Pos)                /*!< 0x00200000 */
+#define EXTI_PR1_PR21              EXTI_PR1_PR21_Msk                           /*!< Pending bit for line 21 */
+
+/*******************  Bit definition for EXTI_IMR2 register  *******************/
+#define EXTI_IMR2_IM_Pos           (0U)
+#define EXTI_IMR2_IM_Msk           (0xFFFFDFFFUL << EXTI_IMR2_IM_Pos)          /*!< 0xFFFFDFFF */
+#define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            /*!< Interrupt Mask */
+#define EXTI_IMR2_IM32_Pos         (0U)
+#define EXTI_IMR2_IM32_Msk         (0x1UL << EXTI_IMR2_IM32_Pos)               /*!< 0x00000001 */
+#define EXTI_IMR2_IM32             EXTI_IMR2_IM32_Msk                          /*!< Interrupt Mask on line 32 */
+#define EXTI_IMR2_IM33_Pos         (1U)
+#define EXTI_IMR2_IM33_Msk         (0x1UL << EXTI_IMR2_IM33_Pos)               /*!< 0x00000002 */
+#define EXTI_IMR2_IM33             EXTI_IMR2_IM33_Msk                          /*!< Interrupt Mask on line 33 */
+#define EXTI_IMR2_IM34_Pos         (2U)
+#define EXTI_IMR2_IM34_Msk         (0x1UL << EXTI_IMR2_IM34_Pos)               /*!< 0x00000004 */
+#define EXTI_IMR2_IM34             EXTI_IMR2_IM34_Msk                          /*!< Interrupt Mask on line 34 */
+#define EXTI_IMR2_IM35_Pos         (3U)
+#define EXTI_IMR2_IM35_Msk         (0x1UL << EXTI_IMR2_IM35_Pos)               /*!< 0x00000008 */
+#define EXTI_IMR2_IM35             EXTI_IMR2_IM35_Msk                          /*!< Interrupt Mask on line 35 */
+#define EXTI_IMR2_IM36_Pos         (4U)
+#define EXTI_IMR2_IM36_Msk         (0x1UL << EXTI_IMR2_IM36_Pos)               /*!< 0x00000010 */
+#define EXTI_IMR2_IM36             EXTI_IMR2_IM36_Msk                          /*!< Interrupt Mask on line 36 */
+#define EXTI_IMR2_IM37_Pos         (5U)
+#define EXTI_IMR2_IM37_Msk         (0x1UL << EXTI_IMR2_IM37_Pos)               /*!< 0x00000020 */
+#define EXTI_IMR2_IM37             EXTI_IMR2_IM37_Msk                          /*!< Interrupt Mask on line 37 */
+#define EXTI_IMR2_IM38_Pos         (6U)
+#define EXTI_IMR2_IM38_Msk         (0x1UL << EXTI_IMR2_IM38_Pos)               /*!< 0x00000040 */
+#define EXTI_IMR2_IM38             EXTI_IMR2_IM38_Msk                          /*!< Interrupt Mask on line 38 */
+#define EXTI_IMR2_IM39_Pos         (7U)
+#define EXTI_IMR2_IM39_Msk         (0x1UL << EXTI_IMR2_IM39_Pos)               /*!< 0x00000080 */
+#define EXTI_IMR2_IM39             EXTI_IMR2_IM39_Msk                          /*!< Interrupt Mask on line 39 */
+#define EXTI_IMR2_IM40_Pos         (8U)
+#define EXTI_IMR2_IM40_Msk         (0x1UL << EXTI_IMR2_IM40_Pos)               /*!< 0x00000100 */
+#define EXTI_IMR2_IM40             EXTI_IMR2_IM40_Msk                          /*!< Interrupt Mask on line 40 */
+#define EXTI_IMR2_IM41_Pos         (9U)
+#define EXTI_IMR2_IM41_Msk         (0x1UL << EXTI_IMR2_IM41_Pos)               /*!< 0x00000200 */
+#define EXTI_IMR2_IM41             EXTI_IMR2_IM41_Msk                          /*!< Interrupt Mask on line 41 */
+#define EXTI_IMR2_IM42_Pos         (10U)
+#define EXTI_IMR2_IM42_Msk         (0x1UL << EXTI_IMR2_IM42_Pos)               /*!< 0x00000400 */
+#define EXTI_IMR2_IM42             EXTI_IMR2_IM42_Msk                          /*!< Interrupt Mask on line 42 */
+#define EXTI_IMR2_IM43_Pos         (11U)
+#define EXTI_IMR2_IM43_Msk         (0x1UL << EXTI_IMR2_IM43_Pos)               /*!< 0x00000800 */
+#define EXTI_IMR2_IM43             EXTI_IMR2_IM43_Msk                          /*!< Interrupt Mask on line 43 */
+#define EXTI_IMR2_IM44_Pos         (12U)
+#define EXTI_IMR2_IM44_Msk         (0x1UL << EXTI_IMR2_IM44_Pos)               /*!< 0x00001000 */
+#define EXTI_IMR2_IM44             EXTI_IMR2_IM44_Msk                          /*!< Interrupt Mask on line 44 */
+#define EXTI_IMR2_IM46_Pos         (14U)
+#define EXTI_IMR2_IM46_Msk         (0x1UL << EXTI_IMR2_IM46_Pos)               /*!< 0x00004000 */
+#define EXTI_IMR2_IM46             EXTI_IMR2_IM46_Msk                          /*!< Interrupt Mask on line 46 */
+#define EXTI_IMR2_IM47_Pos         (15U)
+#define EXTI_IMR2_IM47_Msk         (0x1UL << EXTI_IMR2_IM47_Pos)               /*!< 0x00008000 */
+#define EXTI_IMR2_IM47             EXTI_IMR2_IM47_Msk                          /*!< Interrupt Mask on line 47 */
+#define EXTI_IMR2_IM48_Pos         (16U)
+#define EXTI_IMR2_IM48_Msk         (0x1UL << EXTI_IMR2_IM48_Pos)               /*!< 0x00010000 */
+#define EXTI_IMR2_IM48             EXTI_IMR2_IM48_Msk                          /*!< Interrupt Mask on line 48 */
+#define EXTI_IMR2_IM49_Pos         (17U)
+#define EXTI_IMR2_IM49_Msk         (0x1UL << EXTI_IMR2_IM49_Pos)               /*!< 0x00020000 */
+#define EXTI_IMR2_IM49             EXTI_IMR2_IM49_Msk                          /*!< Interrupt Mask on line 49 */
+#define EXTI_IMR2_IM50_Pos         (18U)
+#define EXTI_IMR2_IM50_Msk         (0x1UL << EXTI_IMR2_IM50_Pos)               /*!< 0x00040000 */
+#define EXTI_IMR2_IM50             EXTI_IMR2_IM50_Msk                          /*!< Interrupt Mask on line 50 */
+#define EXTI_IMR2_IM51_Pos         (19U)
+#define EXTI_IMR2_IM51_Msk         (0x1UL << EXTI_IMR2_IM51_Pos)               /*!< 0x00080000 */
+#define EXTI_IMR2_IM51             EXTI_IMR2_IM51_Msk                          /*!< Interrupt Mask on line 51 */
+#define EXTI_IMR2_IM52_Pos         (20U)
+#define EXTI_IMR2_IM52_Msk         (0x1UL << EXTI_IMR2_IM52_Pos)               /*!< 0x00100000 */
+#define EXTI_IMR2_IM52             EXTI_IMR2_IM52_Msk                          /*!< Interrupt Mask on line 52 */
+#define EXTI_IMR2_IM53_Pos         (21U)
+#define EXTI_IMR2_IM53_Msk         (0x1UL << EXTI_IMR2_IM53_Pos)               /*!< 0x00200000 */
+#define EXTI_IMR2_IM53             EXTI_IMR2_IM53_Msk                          /*!< Interrupt Mask on line 53 */
+#define EXTI_IMR2_IM54_Pos         (22U)
+#define EXTI_IMR2_IM54_Msk         (0x1UL << EXTI_IMR2_IM54_Pos)               /*!< 0x00400000 */
+#define EXTI_IMR2_IM54             EXTI_IMR2_IM54_Msk                          /*!< Interrupt Mask on line 54 */
+#define EXTI_IMR2_IM55_Pos         (23U)
+#define EXTI_IMR2_IM55_Msk         (0x1UL << EXTI_IMR2_IM55_Pos)               /*!< 0x00800000 */
+#define EXTI_IMR2_IM55             EXTI_IMR2_IM55_Msk                          /*!< Interrupt Mask on line 55 */
+#define EXTI_IMR2_IM56_Pos         (24U)
+#define EXTI_IMR2_IM56_Msk         (0x1UL << EXTI_IMR2_IM56_Pos)               /*!< 0x01000000 */
+#define EXTI_IMR2_IM56             EXTI_IMR2_IM56_Msk                          /*!< Interrupt Mask on line 56 */
+#define EXTI_IMR2_IM57_Pos         (25U)
+#define EXTI_IMR2_IM57_Msk         (0x1UL << EXTI_IMR2_IM57_Pos)               /*!< 0x02000000 */
+#define EXTI_IMR2_IM57             EXTI_IMR2_IM57_Msk                          /*!< Interrupt Mask on line 57 */
+#define EXTI_IMR2_IM58_Pos         (26U)
+#define EXTI_IMR2_IM58_Msk         (0x1UL << EXTI_IMR2_IM58_Pos)               /*!< 0x04000000 */
+#define EXTI_IMR2_IM58             EXTI_IMR2_IM58_Msk                          /*!< Interrupt Mask on line 58 */
+#define EXTI_IMR2_IM59_Pos         (27U)
+#define EXTI_IMR2_IM59_Msk         (0x1UL << EXTI_IMR2_IM59_Pos)               /*!< 0x08000000 */
+#define EXTI_IMR2_IM59             EXTI_IMR2_IM59_Msk                          /*!< Interrupt Mask on line 59 */
+#define EXTI_IMR2_IM60_Pos         (28U)
+#define EXTI_IMR2_IM60_Msk         (0x1UL << EXTI_IMR2_IM60_Pos)               /*!< 0x10000000 */
+#define EXTI_IMR2_IM60             EXTI_IMR2_IM60_Msk                          /*!< Interrupt Mask on line 60 */
+#define EXTI_IMR2_IM61_Pos         (29U)
+#define EXTI_IMR2_IM61_Msk         (0x1UL << EXTI_IMR2_IM61_Pos)               /*!< 0x20000000 */
+#define EXTI_IMR2_IM61             EXTI_IMR2_IM61_Msk                          /*!< Interrupt Mask on line 61 */
+#define EXTI_IMR2_IM62_Pos         (30U)
+#define EXTI_IMR2_IM62_Msk         (0x1UL << EXTI_IMR2_IM62_Pos)               /*!< 0x40000000 */
+#define EXTI_IMR2_IM62             EXTI_IMR2_IM62_Msk                          /*!< Interrupt Mask on line 62 */
+#define EXTI_IMR2_IM63_Pos         (31U)
+#define EXTI_IMR2_IM63_Msk         (0x1UL << EXTI_IMR2_IM63_Pos)               /*!< 0x80000000 */
+#define EXTI_IMR2_IM63             EXTI_IMR2_IM63_Msk                          /*!< Interrupt Mask on line 63 */
+
+/*******************  Bit definition for EXTI_EMR2 register  *******************/
+#define EXTI_EMR2_EM_Pos           (0U)
+#define EXTI_EMR2_EM_Msk           (0xFFFFDFFFUL << EXTI_EMR2_EM_Pos)          /*!< 0xFFFFDFFF */
+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            /*!< Event Mask */
+#define EXTI_EMR2_EM32_Pos         (0U)
+#define EXTI_EMR2_EM32_Msk         (0x1UL << EXTI_EMR2_EM32_Pos)               /*!< 0x00000001 */
+#define EXTI_EMR2_EM32             EXTI_EMR2_EM32_Msk                          /*!< Event Mask on line 32*/
+#define EXTI_EMR2_EM33_Pos         (1U)
+#define EXTI_EMR2_EM33_Msk         (0x1UL << EXTI_EMR2_EM33_Pos)               /*!< 0x00000002 */
+#define EXTI_EMR2_EM33             EXTI_EMR2_EM33_Msk                          /*!< Event Mask on line 33*/
+#define EXTI_EMR2_EM34_Pos         (2U)
+#define EXTI_EMR2_EM34_Msk         (0x1UL << EXTI_EMR2_EM34_Pos)               /*!< 0x00000004 */
+#define EXTI_EMR2_EM34             EXTI_EMR2_EM34_Msk                          /*!< Event Mask on line 34*/
+#define EXTI_EMR2_EM35_Pos         (3U)
+#define EXTI_EMR2_EM35_Msk         (0x1UL << EXTI_EMR2_EM35_Pos)               /*!< 0x00000008 */
+#define EXTI_EMR2_EM35             EXTI_EMR2_EM35_Msk                          /*!< Event Mask on line 35*/
+#define EXTI_EMR2_EM36_Pos         (4U)
+#define EXTI_EMR2_EM36_Msk         (0x1UL << EXTI_EMR2_EM36_Pos)               /*!< 0x00000010 */
+#define EXTI_EMR2_EM36             EXTI_EMR2_EM36_Msk                          /*!< Event Mask on line 36*/
+#define EXTI_EMR2_EM37_Pos         (5U)
+#define EXTI_EMR2_EM37_Msk         (0x1UL << EXTI_EMR2_EM37_Pos)               /*!< 0x00000020 */
+#define EXTI_EMR2_EM37             EXTI_EMR2_EM37_Msk                          /*!< Event Mask on line 37*/
+#define EXTI_EMR2_EM38_Pos         (6U)
+#define EXTI_EMR2_EM38_Msk         (0x1UL << EXTI_EMR2_EM38_Pos)               /*!< 0x00000040 */
+#define EXTI_EMR2_EM38             EXTI_EMR2_EM38_Msk                          /*!< Event Mask on line 38*/
+#define EXTI_EMR2_EM39_Pos         (7U)
+#define EXTI_EMR2_EM39_Msk         (0x1UL << EXTI_EMR2_EM39_Pos)               /*!< 0x00000080 */
+#define EXTI_EMR2_EM39             EXTI_EMR2_EM39_Msk                          /*!< Event Mask on line 39*/
+#define EXTI_EMR2_EM40_Pos         (8U)
+#define EXTI_EMR2_EM40_Msk         (0x1UL << EXTI_EMR2_EM40_Pos)               /*!< 0x00000100 */
+#define EXTI_EMR2_EM40             EXTI_EMR2_EM40_Msk                          /*!< Event Mask on line 40*/
+#define EXTI_EMR2_EM41_Pos         (9U)
+#define EXTI_EMR2_EM41_Msk         (0x1UL << EXTI_EMR2_EM41_Pos)               /*!< 0x00000200 */
+#define EXTI_EMR2_EM41             EXTI_EMR2_EM41_Msk                          /*!< Event Mask on line 41*/
+#define EXTI_EMR2_EM42_Pos         (10U)
+#define EXTI_EMR2_EM42_Msk         (0x1UL << EXTI_EMR2_EM42_Pos)               /*!< 0x00000400 */
+#define EXTI_EMR2_EM42             EXTI_EMR2_EM42_Msk                          /*!< Event Mask on line 42 */
+#define EXTI_EMR2_EM43_Pos         (11U)
+#define EXTI_EMR2_EM43_Msk         (0x1UL << EXTI_EMR2_EM43_Pos)               /*!< 0x00000800 */
+#define EXTI_EMR2_EM43             EXTI_EMR2_EM43_Msk                          /*!< Event Mask on line 43 */
+#define EXTI_EMR2_EM44_Pos         (12U)
+#define EXTI_EMR2_EM44_Msk         (0x1UL << EXTI_EMR2_EM44_Pos)               /*!< 0x00001000 */
+#define EXTI_EMR2_EM44             EXTI_EMR2_EM44_Msk                          /*!< Event Mask on line 44 */
+#define EXTI_EMR2_EM46_Pos         (14U)
+#define EXTI_EMR2_EM46_Msk         (0x1UL << EXTI_EMR2_EM46_Pos)               /*!< 0x00004000 */
+#define EXTI_EMR2_EM46             EXTI_EMR2_EM46_Msk                          /*!< Event Mask on line 46 */
+#define EXTI_EMR2_EM47_Pos         (15U)
+#define EXTI_EMR2_EM47_Msk         (0x1UL << EXTI_EMR2_EM47_Pos)               /*!< 0x00008000 */
+#define EXTI_EMR2_EM47             EXTI_EMR2_EM47_Msk                          /*!< Event Mask on line 47 */
+#define EXTI_EMR2_EM48_Pos         (16U)
+#define EXTI_EMR2_EM48_Msk         (0x1UL << EXTI_EMR2_EM48_Pos)               /*!< 0x00010000 */
+#define EXTI_EMR2_EM48             EXTI_EMR2_EM48_Msk                          /*!< Event Mask on line 48 */
+#define EXTI_EMR2_EM49_Pos         (17U)
+#define EXTI_EMR2_EM49_Msk         (0x1UL << EXTI_EMR2_EM49_Pos)               /*!< 0x00020000 */
+#define EXTI_EMR2_EM49             EXTI_EMR2_EM49_Msk                          /*!< Event Mask on line 49 */
+#define EXTI_EMR2_EM50_Pos         (18U)
+#define EXTI_EMR2_EM50_Msk         (0x1UL << EXTI_EMR2_EM50_Pos)               /*!< 0x00040000 */
+#define EXTI_EMR2_EM50             EXTI_EMR2_EM50_Msk                          /*!< Event Mask on line 50 */
+#define EXTI_EMR2_EM51_Pos         (19U)
+#define EXTI_EMR2_EM51_Msk         (0x1UL << EXTI_EMR2_EM51_Pos)               /*!< 0x00080000 */
+#define EXTI_EMR2_EM51             EXTI_EMR2_EM51_Msk                          /*!< Event Mask on line 51 */
+#define EXTI_EMR2_EM52_Pos         (20U)
+#define EXTI_EMR2_EM52_Msk         (0x1UL << EXTI_EMR2_EM52_Pos)               /*!< 0x00100000 */
+#define EXTI_EMR2_EM52             EXTI_EMR2_EM52_Msk                          /*!< Event Mask on line 52 */
+#define EXTI_EMR2_EM53_Pos         (21U)
+#define EXTI_EMR2_EM53_Msk         (0x1UL << EXTI_EMR2_EM53_Pos)               /*!< 0x00200000 */
+#define EXTI_EMR2_EM53             EXTI_EMR2_EM53_Msk                          /*!< Event Mask on line 53 */
+#define EXTI_EMR2_EM54_Pos         (22U)
+#define EXTI_EMR2_EM54_Msk         (0x1UL << EXTI_EMR2_EM54_Pos)               /*!< 0x00400000 */
+#define EXTI_EMR2_EM54             EXTI_EMR2_EM54_Msk                          /*!< Event Mask on line 54 */
+#define EXTI_EMR2_EM55_Pos         (23U)
+#define EXTI_EMR2_EM55_Msk         (0x1UL << EXTI_EMR2_EM55_Pos)               /*!< 0x00800000 */
+#define EXTI_EMR2_EM55             EXTI_EMR2_EM55_Msk                          /*!< Event Mask on line 55 */
+#define EXTI_EMR2_EM56_Pos         (24U)
+#define EXTI_EMR2_EM56_Msk         (0x1UL << EXTI_EMR2_EM56_Pos)               /*!< 0x01000000 */
+#define EXTI_EMR2_EM56             EXTI_EMR2_EM56_Msk                          /*!< Event Mask on line 56 */
+#define EXTI_EMR2_EM57_Pos         (25U)
+#define EXTI_EMR2_EM57_Msk         (0x1UL << EXTI_EMR2_EM57_Pos)               /*!< 0x02000000 */
+#define EXTI_EMR2_EM57             EXTI_EMR2_EM57_Msk                          /*!< Event Mask on line 57 */
+#define EXTI_EMR2_EM58_Pos         (26U)
+#define EXTI_EMR2_EM58_Msk         (0x1UL << EXTI_EMR2_EM58_Pos)               /*!< 0x04000000 */
+#define EXTI_EMR2_EM58             EXTI_EMR2_EM58_Msk                          /*!< Event Mask on line 58 */
+#define EXTI_EMR2_EM59_Pos         (27U)
+#define EXTI_EMR2_EM59_Msk         (0x1UL << EXTI_EMR2_EM59_Pos)               /*!< 0x08000000 */
+#define EXTI_EMR2_EM59             EXTI_EMR2_EM59_Msk                          /*!< Event Mask on line 59 */
+#define EXTI_EMR2_EM60_Pos         (28U)
+#define EXTI_EMR2_EM60_Msk         (0x1UL << EXTI_EMR2_EM60_Pos)               /*!< 0x10000000 */
+#define EXTI_EMR2_EM60             EXTI_EMR2_EM60_Msk                          /*!< Event Mask on line 60 */
+#define EXTI_EMR2_EM61_Pos         (29U)
+#define EXTI_EMR2_EM61_Msk         (0x1UL << EXTI_EMR2_EM61_Pos)               /*!< 0x20000000 */
+#define EXTI_EMR2_EM61             EXTI_EMR2_EM61_Msk                          /*!< Event Mask on line 61 */
+#define EXTI_EMR2_EM62_Pos         (30U)
+#define EXTI_EMR2_EM62_Msk         (0x1UL << EXTI_EMR2_EM62_Pos)               /*!< 0x40000000 */
+#define EXTI_EMR2_EM62             EXTI_EMR2_EM62_Msk                          /*!< Event Mask on line 62 */
+#define EXTI_EMR2_EM63_Pos         (31U)
+#define EXTI_EMR2_EM63_Msk         (0x1UL << EXTI_EMR2_EM63_Pos)               /*!< 0x80000000 */
+#define EXTI_EMR2_EM63             EXTI_EMR2_EM63_Msk                          /*!< Event Mask on line 63 */
+
+/*******************  Bit definition for EXTI_PR2 register  ********************/
+#define EXTI_PR2_PR_Pos            (17U)
+#define EXTI_PR2_PR_Msk            (0x5UL << EXTI_PR2_PR_Pos)                  /*!< 0x000A0000 */
+#define EXTI_PR2_PR                EXTI_PR2_PR_Msk                             /*!< Pending bit */
+#define EXTI_PR2_PR49_Pos          (17U)
+#define EXTI_PR2_PR49_Msk          (0x1UL << EXTI_PR2_PR49_Pos)                /*!< 0x00020000 */
+#define EXTI_PR2_PR49              EXTI_PR2_PR49_Msk                           /*!< Pending bit for line 49 */
+#define EXTI_PR2_PR51_Pos          (19U)
+#define EXTI_PR2_PR51_Msk          (0x1UL << EXTI_PR2_PR51_Pos)                /*!< 0x00080000 */
+#define EXTI_PR2_PR51              EXTI_PR2_PR51_Msk                           /*!< Pending bit for line 51 */
+
+/*******************  Bit definition for EXTI_IMR3 register  *******************/
+#define EXTI_IMR3_IM_Pos           (0U)
+#define EXTI_IMR3_IM_Msk           (0x00F5FFFFUL << EXTI_IMR3_IM_Pos)          /*!< 0x00F5FFFF */
+#define EXTI_IMR3_IM               EXTI_IMR3_IM_Msk                            /*!< Interrupt Mask */
+#define EXTI_IMR3_IM64_Pos         (0U)
+#define EXTI_IMR3_IM64_Msk         (0x1UL << EXTI_IMR3_IM64_Pos)               /*!< 0x00000001 */
+#define EXTI_IMR3_IM64             EXTI_IMR3_IM64_Msk                          /*!< Interrupt Mask on line 64 */
+#define EXTI_IMR3_IM65_Pos         (1U)
+#define EXTI_IMR3_IM65_Msk         (0x1UL << EXTI_IMR3_IM65_Pos)               /*!< 0x00000002 */
+#define EXTI_IMR3_IM65             EXTI_IMR3_IM65_Msk                          /*!< Interrupt Mask on line 65 */
+#define EXTI_IMR3_IM66_Pos         (2U)
+#define EXTI_IMR3_IM66_Msk         (0x1UL << EXTI_IMR3_IM66_Pos)               /*!< 0x00000004 */
+#define EXTI_IMR3_IM66             EXTI_IMR3_IM66_Msk                          /*!< Interrupt Mask on line 66 */
+#define EXTI_IMR3_IM67_Pos         (3U)
+#define EXTI_IMR3_IM67_Msk         (0x1UL << EXTI_IMR3_IM67_Pos)               /*!< 0x00000008 */
+#define EXTI_IMR3_IM67             EXTI_IMR3_IM67_Msk                          /*!< Interrupt Mask on line 67 */
+#define EXTI_IMR3_IM68_Pos         (4U)
+#define EXTI_IMR3_IM68_Msk         (0x1UL << EXTI_IMR3_IM68_Pos)               /*!< 0x00000010 */
+#define EXTI_IMR3_IM68             EXTI_IMR3_IM68_Msk                          /*!< Interrupt Mask on line 68 */
+#define EXTI_IMR3_IM69_Pos         (5U)
+#define EXTI_IMR3_IM69_Msk         (0x1UL << EXTI_IMR3_IM69_Pos)               /*!< 0x00000020 */
+#define EXTI_IMR3_IM69             EXTI_IMR3_IM69_Msk                          /*!< Interrupt Mask on line 69 */
+#define EXTI_IMR3_IM70_Pos         (6U)
+#define EXTI_IMR3_IM70_Msk         (0x1UL << EXTI_IMR3_IM70_Pos)               /*!< 0x00000040 */
+#define EXTI_IMR3_IM70             EXTI_IMR3_IM70_Msk                          /*!< Interrupt Mask on line 70 */
+#define EXTI_IMR3_IM71_Pos         (7U)
+#define EXTI_IMR3_IM71_Msk         (0x1UL << EXTI_IMR3_IM71_Pos)               /*!< 0x00000080 */
+#define EXTI_IMR3_IM71             EXTI_IMR3_IM71_Msk                          /*!< Interrupt Mask on line 71 */
+#define EXTI_IMR3_IM72_Pos         (8U)
+#define EXTI_IMR3_IM72_Msk         (0x1UL << EXTI_IMR3_IM72_Pos)               /*!< 0x00000100 */
+#define EXTI_IMR3_IM72             EXTI_IMR3_IM72_Msk                          /*!< Interrupt Mask on line 72 */
+#define EXTI_IMR3_IM73_Pos         (9U)
+#define EXTI_IMR3_IM73_Msk         (0x1UL << EXTI_IMR3_IM73_Pos)               /*!< 0x00000200 */
+#define EXTI_IMR3_IM73             EXTI_IMR3_IM73_Msk                          /*!< Interrupt Mask on line 73 */
+#define EXTI_IMR3_IM74_Pos         (10U)
+#define EXTI_IMR3_IM74_Msk         (0x1UL << EXTI_IMR3_IM74_Pos)               /*!< 0x00000400 */
+#define EXTI_IMR3_IM74             EXTI_IMR3_IM74_Msk                          /*!< Interrupt Mask on line 74 */
+#define EXTI_IMR3_IM75_Pos         (11U)
+#define EXTI_IMR3_IM75_Msk         (0x1UL << EXTI_IMR3_IM75_Pos)               /*!< 0x00000800 */
+#define EXTI_IMR3_IM75             EXTI_IMR3_IM75_Msk                          /*!< Interrupt Mask on line 75 */
+#define EXTI_IMR3_IM76_Pos         (12U)
+#define EXTI_IMR3_IM76_Msk         (0x1UL << EXTI_IMR3_IM76_Pos)               /*!< 0x00001000 */
+#define EXTI_IMR3_IM76             EXTI_IMR3_IM76_Msk                          /*!< Interrupt Mask on line 76 */
+#define EXTI_IMR3_IM77_Pos         (13U)
+#define EXTI_IMR3_IM77_Msk         (0x1UL << EXTI_IMR3_IM77_Pos)               /*!< 0x00002000 */
+#define EXTI_IMR3_IM77             EXTI_IMR3_IM77_Msk                          /*!< Interrupt Mask on line 77 */
+#define EXTI_IMR3_IM78_Pos         (14U)
+#define EXTI_IMR3_IM78_Msk         (0x1UL << EXTI_IMR3_IM78_Pos)               /*!< 0x00004000 */
+#define EXTI_IMR3_IM78             EXTI_IMR3_IM78_Msk                          /*!< Interrupt Mask on line 78 */
+#define EXTI_IMR3_IM79_Pos         (15U)
+#define EXTI_IMR3_IM79_Msk         (0x1UL << EXTI_IMR3_IM79_Pos)               /*!< 0x00008000 */
+#define EXTI_IMR3_IM79             EXTI_IMR3_IM79_Msk                          /*!< Interrupt Mask on line 79 */
+#define EXTI_IMR3_IM80_Pos         (16U)
+#define EXTI_IMR3_IM80_Msk         (0x1UL << EXTI_IMR3_IM80_Pos)               /*!< 0x00010000 */
+#define EXTI_IMR3_IM80             EXTI_IMR3_IM80_Msk                          /*!< Interrupt Mask on line 80 */
+#define EXTI_IMR3_IM82_Pos         (18U)
+#define EXTI_IMR3_IM82_Msk         (0x1UL << EXTI_IMR3_IM82_Pos)               /*!< 0x00040000 */
+#define EXTI_IMR3_IM82             EXTI_IMR3_IM82_Msk                          /*!< Interrupt Mask on line 82 */
+#define EXTI_IMR3_IM84_Pos         (20U)
+#define EXTI_IMR3_IM84_Msk         (0x1UL << EXTI_IMR3_IM84_Pos)               /*!< 0x00100000 */
+#define EXTI_IMR3_IM84             EXTI_IMR3_IM84_Msk                          /*!< Interrupt Mask on line 84 */
+#define EXTI_IMR3_IM85_Pos         (21U)
+#define EXTI_IMR3_IM85_Msk         (0x1UL << EXTI_IMR3_IM85_Pos)               /*!< 0x00200000 */
+#define EXTI_IMR3_IM85             EXTI_IMR3_IM85_Msk                          /*!< Interrupt Mask on line 85 */
+#define EXTI_IMR3_IM86_Pos         (22U)
+#define EXTI_IMR3_IM86_Msk         (0x1UL << EXTI_IMR3_IM86_Pos)               /*!< 0x00400000 */
+#define EXTI_IMR3_IM86             EXTI_IMR3_IM86_Msk                          /*!< Interrupt Mask on line 86 */
+#define EXTI_IMR3_IM87_Pos         (23U)
+#define EXTI_IMR3_IM87_Msk         (0x1UL << EXTI_IMR3_IM87_Pos)               /*!< 0x00800000 */
+#define EXTI_IMR3_IM87             EXTI_IMR3_IM87_Msk                          /*!< Interrupt Mask on line 87 */
+
+
+/*******************  Bit definition for EXTI_EMR3 register  *******************/
+#define EXTI_EMR3_EM_Pos           (0U)
+#define EXTI_EMR3_EM_Msk           (0x00F5FFFFUL << EXTI_EMR3_EM_Pos)          /*!< 0x00F5FFFF */
+#define EXTI_EMR3_EM               EXTI_EMR3_EM_Msk                            /*!< Event Mask           */
+#define EXTI_EMR3_EM64_Pos         (0U)
+#define EXTI_EMR3_EM64_Msk         (0x1UL << EXTI_EMR3_EM64_Pos)               /*!< 0x00000001 */
+#define EXTI_EMR3_EM64             EXTI_EMR3_EM64_Msk                          /*!< Event Mask on line 64*/
+#define EXTI_EMR3_EM65_Pos         (1U)
+#define EXTI_EMR3_EM65_Msk         (0x1UL << EXTI_EMR3_EM65_Pos)               /*!< 0x00000002 */
+#define EXTI_EMR3_EM65             EXTI_EMR3_EM65_Msk                          /*!< Event Mask on line 65*/
+#define EXTI_EMR3_EM66_Pos         (2U)
+#define EXTI_EMR3_EM66_Msk         (0x1UL << EXTI_EMR3_EM66_Pos)               /*!< 0x00000004 */
+#define EXTI_EMR3_EM66             EXTI_EMR3_EM66_Msk                          /*!< Event Mask on line 66*/
+#define EXTI_EMR3_EM67_Pos         (3U)
+#define EXTI_EMR3_EM67_Msk         (0x1UL << EXTI_EMR3_EM67_Pos)               /*!< 0x00000008 */
+#define EXTI_EMR3_EM67             EXTI_EMR3_EM67_Msk                          /*!< Event Mask on line 67*/
+#define EXTI_EMR3_EM68_Pos         (4U)
+#define EXTI_EMR3_EM68_Msk         (0x1UL << EXTI_EMR3_EM68_Pos)               /*!< 0x00000010 */
+#define EXTI_EMR3_EM68             EXTI_EMR3_EM68_Msk                          /*!< Event Mask on line 68*/
+#define EXTI_EMR3_EM69_Pos         (5U)
+#define EXTI_EMR3_EM69_Msk         (0x1UL << EXTI_EMR3_EM69_Pos)               /*!< 0x00000020 */
+#define EXTI_EMR3_EM69             EXTI_EMR3_EM69_Msk                          /*!< Event Mask on line 69*/
+#define EXTI_EMR3_EM70_Pos         (6U)
+#define EXTI_EMR3_EM70_Msk         (0x1UL << EXTI_EMR3_EM70_Pos)               /*!< 0x00000040 */
+#define EXTI_EMR3_EM70             EXTI_EMR3_EM70_Msk                          /*!< Event Mask on line 70*/
+#define EXTI_EMR3_EM71_Pos         (7U)
+#define EXTI_EMR3_EM71_Msk         (0x1UL << EXTI_EMR3_EM71_Pos)               /*!< 0x00000080 */
+#define EXTI_EMR3_EM71             EXTI_EMR3_EM71_Msk                          /*!< Event Mask on line 71*/
+#define EXTI_EMR3_EM72_Pos         (8U)
+#define EXTI_EMR3_EM72_Msk         (0x1UL << EXTI_EMR3_EM72_Pos)               /*!< 0x00000100 */
+#define EXTI_EMR3_EM72             EXTI_EMR3_EM72_Msk                          /*!< Event Mask on line 72*/
+#define EXTI_EMR3_EM73_Pos         (9U)
+#define EXTI_EMR3_EM73_Msk         (0x1UL << EXTI_EMR3_EM73_Pos)               /*!< 0x00000200 */
+#define EXTI_EMR3_EM73             EXTI_EMR3_EM73_Msk                          /*!< Event Mask on line 73*/
+#define EXTI_EMR3_EM74_Pos         (10U)
+#define EXTI_EMR3_EM74_Msk         (0x1UL << EXTI_EMR3_EM74_Pos)               /*!< 0x00000400 */
+#define EXTI_EMR3_EM74             EXTI_EMR3_EM74_Msk                          /*!< Event Mask on line 74 */
+#define EXTI_EMR3_EM75_Pos         (11U)
+#define EXTI_EMR3_EM75_Msk         (0x1UL << EXTI_EMR3_EM75_Pos)               /*!< 0x00000800 */
+#define EXTI_EMR3_EM75             EXTI_EMR3_EM75_Msk                          /*!< Event Mask on line 75 */
+#define EXTI_EMR3_EM76_Pos         (12U)
+#define EXTI_EMR3_EM76_Msk         (0x1UL << EXTI_EMR3_EM76_Pos)               /*!< 0x00001000 */
+#define EXTI_EMR3_EM76             EXTI_EMR3_EM76_Msk                          /*!< Event Mask on line 76 */
+#define EXTI_EMR3_EM77_Pos         (13U)
+#define EXTI_EMR3_EM77_Msk         (0x1UL << EXTI_EMR3_EM77_Pos)               /*!< 0x00002000 */
+#define EXTI_EMR3_EM77             EXTI_EMR3_EM77_Msk                          /*!< Event Mask on line 77 */
+#define EXTI_EMR3_EM78_Pos         (14U)
+#define EXTI_EMR3_EM78_Msk         (0x1UL << EXTI_EMR3_EM78_Pos)               /*!< 0x00004000 */
+#define EXTI_EMR3_EM78             EXTI_EMR3_EM78_Msk                          /*!< Event Mask on line 78 */
+#define EXTI_EMR3_EM79_Pos         (15U)
+#define EXTI_EMR3_EM79_Msk         (0x1UL << EXTI_EMR3_EM79_Pos)               /*!< 0x00008000 */
+#define EXTI_EMR3_EM79             EXTI_EMR3_EM79_Msk                          /*!< Event Mask on line 79 */
+#define EXTI_EMR3_EM80_Pos         (16U)
+#define EXTI_EMR3_EM80_Msk         (0x1UL << EXTI_EMR3_EM80_Pos)               /*!< 0x00010000 */
+#define EXTI_EMR3_EM80             EXTI_EMR3_EM80_Msk                          /*!< Event Mask on line 80 */
+#define EXTI_EMR3_EM81_Pos         (17U)
+#define EXTI_EMR3_EM81_Msk         (0x1UL << EXTI_EMR3_EM81_Pos)               /*!< 0x00020000 */
+#define EXTI_EMR3_EM81             EXTI_EMR3_EM81_Msk                          /*!< Event Mask on line 81 */
+#define EXTI_EMR3_EM82_Pos         (18U)
+#define EXTI_EMR3_EM82_Msk         (0x1UL << EXTI_EMR3_EM82_Pos)               /*!< 0x00040000 */
+#define EXTI_EMR3_EM82             EXTI_EMR3_EM82_Msk                          /*!< Event Mask on line 82 */
+#define EXTI_EMR3_EM84_Pos         (20U)
+#define EXTI_EMR3_EM84_Msk         (0x1UL << EXTI_EMR3_EM84_Pos)               /*!< 0x00100000 */
+#define EXTI_EMR3_EM84             EXTI_EMR3_EM84_Msk                          /*!< Event Mask on line 84 */
+#define EXTI_EMR3_EM85_Pos         (21U)
+#define EXTI_EMR3_EM85_Msk         (0x1UL << EXTI_EMR3_EM85_Pos)               /*!< 0x00200000 */
+#define EXTI_EMR3_EM85             EXTI_EMR3_EM85_Msk                          /*!< Event Mask on line 85 */
+#define EXTI_EMR3_EM86_Pos         (22U)
+#define EXTI_EMR3_EM86_Msk         (0x1UL << EXTI_EMR3_EM86_Pos)               /*!< 0x00400000 */
+#define EXTI_EMR3_EM86             EXTI_EMR3_EM86_Msk                          /*!< Event Mask on line 86 */
+#define EXTI_EMR3_EM87_Pos         (23U)
+#define EXTI_EMR3_EM87_Msk         (0x1UL << EXTI_EMR3_EM87_Pos)               /*!< 0x00800000 */
+#define EXTI_EMR3_EM87             EXTI_EMR3_EM87_Msk                          /*!< Event Mask on line 87 */
+
+/*******************  Bit definition for EXTI_PR3 register  ********************/
+#define EXTI_PR3_PR_Pos            (18U)
+#define EXTI_PR3_PR_Msk            (0x1DUL << EXTI_PR3_PR_Pos)                 /*!< 0x00740000 */
+#define EXTI_PR3_PR                EXTI_PR3_PR_Msk                             /*!< Pending bit */
+#define EXTI_PR3_PR82_Pos          (18U)
+#define EXTI_PR3_PR82_Msk          (0x1UL << EXTI_PR3_PR82_Pos)                /*!< 0x00040000 */
+#define EXTI_PR3_PR82              EXTI_PR3_PR82_Msk                           /*!< Pending bit for line 82 */
+#define EXTI_PR3_PR84_Pos          (20U)
+#define EXTI_PR3_PR84_Msk          (0x1UL << EXTI_PR3_PR84_Pos)                /*!< 0x00100000 */
+#define EXTI_PR3_PR84              EXTI_PR3_PR84_Msk                           /*!< Pending bit for line 84 */
+#define EXTI_PR3_PR85_Pos          (21U)
+#define EXTI_PR3_PR85_Msk          (0x1UL << EXTI_PR3_PR85_Pos)                /*!< 0x00200000 */
+#define EXTI_PR3_PR85              EXTI_PR3_PR85_Msk                           /*!< Pending bit for line 85 */
+#define EXTI_PR3_PR86_Pos          (22U)
+#define EXTI_PR3_PR86_Msk          (0x1UL << EXTI_PR3_PR86_Pos)                /*!< 0x00400000 */
+#define EXTI_PR3_PR86              EXTI_PR3_PR86_Msk                           /*!< Pending bit for line 86 */
+/******************************************************************************/
+/*                                                                            */
+/*                                    FLASH                                   */
+/*                                                                            */
+/******************************************************************************/
+/*
+* @brief FLASH Global Defines
+*/
+#define FLASH_SECTOR_TOTAL                   8U                    /* 8 sectors */
+#define FLASH_SIZE                           0x200000UL            /* 2 MB   */
+#define FLASH_BANK_SIZE                      (FLASH_SIZE >> 1)     /* 1 MB   */
+#define FLASH_SECTOR_SIZE                    0x00020000UL          /* 128 KB */
+#define FLASH_LATENCY_DEFAULT                FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */
+#define FLASH_NB_32BITWORD_IN_FLASHWORD      8U                    /* 256 bits */
+#define DUAL_BANK                                                  /* Dual-bank Flash */
+
+/*******************  Bits definition for FLASH_ACR register  **********************/
+#define FLASH_ACR_LATENCY_Pos                (0U)
+#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Read Latency */
+#define FLASH_ACR_LATENCY_0WS                (0x00000000UL)
+#define FLASH_ACR_LATENCY_1WS                (0x00000001UL)
+#define FLASH_ACR_LATENCY_2WS                (0x00000002UL)
+#define FLASH_ACR_LATENCY_3WS                (0x00000003UL)
+#define FLASH_ACR_LATENCY_4WS                (0x00000004UL)
+#define FLASH_ACR_LATENCY_5WS                (0x00000005UL)
+#define FLASH_ACR_LATENCY_6WS                (0x00000006UL)
+#define FLASH_ACR_LATENCY_7WS                (0x00000007UL)
+#define FLASH_ACR_LATENCY_8WS                (0x00000008UL)
+#define FLASH_ACR_LATENCY_9WS                (0x00000009UL)
+#define FLASH_ACR_LATENCY_10WS               (0x0000000AUL)
+#define FLASH_ACR_LATENCY_11WS               (0x0000000BUL)
+#define FLASH_ACR_LATENCY_12WS               (0x0000000CUL)
+#define FLASH_ACR_LATENCY_13WS               (0x0000000DUL)
+#define FLASH_ACR_LATENCY_14WS               (0x0000000EUL)
+#define FLASH_ACR_LATENCY_15WS               (0x0000000FUL)
+#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
+#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
+#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
+#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
+#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
+
+/*******************  Bits definition for FLASH_CR register  ***********************/
+#define FLASH_CR_LOCK_Pos                    (0U)
+#define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)      /*!< 0x00000001 */
+#define FLASH_CR_LOCK                        FLASH_CR_LOCK_Msk                 /*!< Configuration lock bit */
+#define FLASH_CR_PG_Pos                      (1U)
+#define FLASH_CR_PG_Msk                      (0x1UL << FLASH_CR_PG_Pos)        /*!< 0x00000002 */
+#define FLASH_CR_PG                          FLASH_CR_PG_Msk                   /*!< Internal buffer control bit */
+#define FLASH_CR_SER_Pos                     (2U)
+#define FLASH_CR_SER_Msk                     (0x1UL << FLASH_CR_SER_Pos)       /*!< 0x00000004 */
+#define FLASH_CR_SER                         FLASH_CR_SER_Msk                  /*!< Sector erase request */
+#define FLASH_CR_BER_Pos                     (3U)
+#define FLASH_CR_BER_Msk                     (0x1UL << FLASH_CR_BER_Pos)       /*!< 0x00000008 */
+#define FLASH_CR_BER                         FLASH_CR_BER_Msk                  /*!< Bank erase request */
+#define FLASH_CR_PSIZE_Pos                   (4U)
+#define FLASH_CR_PSIZE_Msk                   (0x3UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000030 */
+#define FLASH_CR_PSIZE                       FLASH_CR_PSIZE_Msk                /*!< Program size */
+#define FLASH_CR_PSIZE_0                     (0x1UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000010 */
+#define FLASH_CR_PSIZE_1                     (0x2UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000020 */
+#define FLASH_CR_FW_Pos                      (6U)
+#define FLASH_CR_FW_Msk                      (0x1UL << FLASH_CR_FW_Pos)        /*!< 0x00000040 */
+#define FLASH_CR_FW                          FLASH_CR_FW_Msk                   /*!< Write forcing control bit */
+#define FLASH_CR_START_Pos                   (7U)
+#define FLASH_CR_START_Msk                   (0x1UL << FLASH_CR_START_Pos)     /*!< 0x00000080 */
+#define FLASH_CR_START                       FLASH_CR_START_Msk                /*!< Erase start control bit */
+#define FLASH_CR_SNB_Pos                     (8U)
+#define FLASH_CR_SNB_Msk                     (0x7UL << FLASH_CR_SNB_Pos)       /*!< 0x00000700 */
+#define FLASH_CR_SNB                         FLASH_CR_SNB_Msk                  /*!< Sector erase selection number */
+#define FLASH_CR_SNB_0                       (0x1UL << FLASH_CR_SNB_Pos)       /*!< 0x00000100 */
+#define FLASH_CR_SNB_1                       (0x2UL << FLASH_CR_SNB_Pos)       /*!< 0x00000200 */
+#define FLASH_CR_SNB_2                       (0x4UL << FLASH_CR_SNB_Pos)       /*!< 0x00000400 */
+#define FLASH_CR_CRC_EN_Pos                  (15U)
+#define FLASH_CR_CRC_EN_Msk                  (0x1UL << FLASH_CR_CRC_EN_Pos)    /*!< 0x00008000 */
+#define FLASH_CR_CRC_EN                      FLASH_CR_CRC_EN_Msk               /*!< CRC control bit */
+#define FLASH_CR_EOPIE_Pos                   (16U)
+#define FLASH_CR_EOPIE_Msk                   (0x1UL << FLASH_CR_EOPIE_Pos)     /*!< 0x00010000 */
+#define FLASH_CR_EOPIE                       FLASH_CR_EOPIE_Msk                /*!< End-of-program interrupt control bit */
+#define FLASH_CR_WRPERRIE_Pos                (17U)
+#define FLASH_CR_WRPERRIE_Msk                (0x1UL << FLASH_CR_WRPERRIE_Pos)  /*!< 0x00020000 */
+#define FLASH_CR_WRPERRIE                    FLASH_CR_WRPERRIE_Msk             /*!< Write protection error interrupt enable bit */
+#define FLASH_CR_PGSERRIE_Pos                (18U)
+#define FLASH_CR_PGSERRIE_Msk                (0x1UL << FLASH_CR_PGSERRIE_Pos)  /*!< 0x00040000 */
+#define FLASH_CR_PGSERRIE                    FLASH_CR_PGSERRIE_Msk             /*!< Programming sequence error interrupt enable bit */
+#define FLASH_CR_STRBERRIE_Pos               (19U)
+#define FLASH_CR_STRBERRIE_Msk               (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */
+#define FLASH_CR_STRBERRIE                   FLASH_CR_STRBERRIE_Msk            /*!< Strobe error interrupt enable bit */
+#define FLASH_CR_INCERRIE_Pos                (21U)
+#define FLASH_CR_INCERRIE_Msk                (0x1UL << FLASH_CR_INCERRIE_Pos)  /*!< 0x00200000 */
+#define FLASH_CR_INCERRIE                    FLASH_CR_INCERRIE_Msk             /*!< Inconsistency error interrupt enable bit */
+#define FLASH_CR_OPERRIE_Pos                 (22U)
+#define FLASH_CR_OPERRIE_Msk                 (0x1UL << FLASH_CR_OPERRIE_Pos)   /*!< 0x00400000 */
+#define FLASH_CR_OPERRIE                     FLASH_CR_OPERRIE_Msk              /*!< Write/erase error interrupt enable bit */
+#define FLASH_CR_RDPERRIE_Pos                (23U)
+#define FLASH_CR_RDPERRIE_Msk                (0x1UL << FLASH_CR_RDPERRIE_Pos)  /*!< 0x00800000 */
+#define FLASH_CR_RDPERRIE                    FLASH_CR_RDPERRIE_Msk             /*!< Read protection error interrupt enable bit */
+#define FLASH_CR_RDSERRIE_Pos                (24U)
+#define FLASH_CR_RDSERRIE_Msk                (0x1UL << FLASH_CR_RDSERRIE_Pos)  /*!< 0x01000000 */
+#define FLASH_CR_RDSERRIE                    FLASH_CR_RDSERRIE_Msk             /*!< Secure error interrupt enable bit */
+#define FLASH_CR_SNECCERRIE_Pos              (25U)
+#define FLASH_CR_SNECCERRIE_Msk              (0x1UL << FLASH_CR_SNECCERRIE_Pos) /*!< 0x02000000 */
+#define FLASH_CR_SNECCERRIE                  FLASH_CR_SNECCERRIE_Msk            /*!< ECC single correction error interrupt enable bit */
+#define FLASH_CR_DBECCERRIE_Pos              (26U)
+#define FLASH_CR_DBECCERRIE_Msk              (0x1UL << FLASH_CR_DBECCERRIE_Pos) /*!< 0x04000000 */
+#define FLASH_CR_DBECCERRIE                  FLASH_CR_DBECCERRIE_Msk            /*!< ECC double detection error interrupt enable bit */
+#define FLASH_CR_CRCENDIE_Pos                (27U)
+#define FLASH_CR_CRCENDIE_Msk                (0x1UL << FLASH_CR_CRCENDIE_Pos)  /*!< 0x08000000 */
+#define FLASH_CR_CRCENDIE                    FLASH_CR_CRCENDIE_Msk             /*!< CRC end of calculation interrupt enable bit */
+#define FLASH_CR_CRCRDERRIE_Pos              (28U)
+#define FLASH_CR_CRCRDERRIE_Msk              (0x1UL << FLASH_CR_CRCRDERRIE_Pos) /*!< 0x10000000 */
+#define FLASH_CR_CRCRDERRIE                  FLASH_CR_CRCRDERRIE_Msk            /*!< CRC read error interrupt enable bit */
+
+/*******************  Bits definition for FLASH_SR register  ***********************/
+#define FLASH_SR_BSY_Pos                     (0U)
+#define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)       /*!< 0x00000001 */
+#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy flag */
+#define FLASH_SR_WBNE_Pos                    (1U)
+#define FLASH_SR_WBNE_Msk                    (0x1UL << FLASH_SR_WBNE_Pos)      /*!< 0x00000002 */
+#define FLASH_SR_WBNE                        FLASH_SR_WBNE_Msk                 /*!< Write buffer not empty flag */
+#define FLASH_SR_QW_Pos                      (2U)
+#define FLASH_SR_QW_Msk                      (0x1UL << FLASH_SR_QW_Pos)        /*!< 0x00000004 */
+#define FLASH_SR_QW                          FLASH_SR_QW_Msk                   /*!< Wait queue flag */
+#define FLASH_SR_CRC_BUSY_Pos                (3U)
+#define FLASH_SR_CRC_BUSY_Msk                (0x1UL << FLASH_SR_CRC_BUSY_Pos)  /*!< 0x00000008 */
+#define FLASH_SR_CRC_BUSY                    FLASH_SR_CRC_BUSY_Msk             /*!< CRC busy flag */
+#define FLASH_SR_EOP_Pos                     (16U)
+#define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)       /*!< 0x00010000 */
+#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End-of-program flag */
+#define FLASH_SR_WRPERR_Pos                  (17U)
+#define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)    /*!< 0x00020000 */
+#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protection error flag */
+#define FLASH_SR_PGSERR_Pos                  (18U)
+#define FLASH_SR_PGSERR_Msk                  (0x1UL << FLASH_SR_PGSERR_Pos)    /*!< 0x00040000 */
+#define FLASH_SR_PGSERR                      FLASH_SR_PGSERR_Msk               /*!< Programming sequence error flag */
+#define FLASH_SR_STRBERR_Pos                 (19U)
+#define FLASH_SR_STRBERR_Msk                 (0x1UL << FLASH_SR_STRBERR_Pos)   /*!< 0x00080000 */
+#define FLASH_SR_STRBERR                     FLASH_SR_STRBERR_Msk              /*!< Strobe error flag */
+#define FLASH_SR_INCERR_Pos                  (21U)
+#define FLASH_SR_INCERR_Msk                  (0x1UL << FLASH_SR_INCERR_Pos)    /*!< 0x00200000 */
+#define FLASH_SR_INCERR                      FLASH_SR_INCERR_Msk               /*!< Inconsistency error flag */
+#define FLASH_SR_OPERR_Pos                   (22U)
+#define FLASH_SR_OPERR_Msk                   (0x1UL << FLASH_SR_OPERR_Pos)     /*!< 0x00400000 */
+#define FLASH_SR_OPERR                       FLASH_SR_OPERR_Msk                /*!< Write/erase error flag */
+#define FLASH_SR_RDPERR_Pos                  (23U)
+#define FLASH_SR_RDPERR_Msk                  (0x1UL << FLASH_SR_RDPERR_Pos)    /*!< 0x00800000 */
+#define FLASH_SR_RDPERR                      FLASH_SR_RDPERR_Msk               /*!< Read protection error flag */
+#define FLASH_SR_RDSERR_Pos                  (24U)
+#define FLASH_SR_RDSERR_Msk                  (0x1UL << FLASH_SR_RDSERR_Pos)    /*!< 0x01000000 */
+#define FLASH_SR_RDSERR                      FLASH_SR_RDSERR_Msk               /*!< Secure error flag */
+#define FLASH_SR_SNECCERR_Pos                (25U)
+#define FLASH_SR_SNECCERR_Msk                (0x1UL << FLASH_SR_SNECCERR_Pos)  /*!< 0x02000000 */
+#define FLASH_SR_SNECCERR                    FLASH_SR_SNECCERR_Msk             /*!< Single correction error flag */
+#define FLASH_SR_DBECCERR_Pos                (26U)
+#define FLASH_SR_DBECCERR_Msk                (0x1UL << FLASH_SR_DBECCERR_Pos)  /*!< 0x04000000 */
+#define FLASH_SR_DBECCERR                    FLASH_SR_DBECCERR_Msk             /*!< ECC double detection error flag */
+#define FLASH_SR_CRCEND_Pos                  (27U)
+#define FLASH_SR_CRCEND_Msk                  (0x1UL << FLASH_SR_CRCEND_Pos)    /*!< 0x08000000 */
+#define FLASH_SR_CRCEND                      FLASH_SR_CRCEND_Msk               /*!< CRC end of calculation flag */
+#define FLASH_SR_CRCRDERR_Pos                (28U)
+#define FLASH_SR_CRCRDERR_Msk                (0x1UL << FLASH_SR_CRCRDERR_Pos)  /*!< 0x10000000 */
+#define FLASH_SR_CRCRDERR                    FLASH_SR_CRCRDERR_Msk             /*!< CRC read error flag */
+
+/*******************  Bits definition for FLASH_CCR register  *******************/
+#define FLASH_CCR_CLR_EOP_Pos                (16U)
+#define FLASH_CCR_CLR_EOP_Msk                (0x1UL << FLASH_CCR_CLR_EOP_Pos)  /*!< 0x00010000 */
+#define FLASH_CCR_CLR_EOP                    FLASH_CCR_CLR_EOP_Msk             /*!< EOP flag clear bit */
+#define FLASH_CCR_CLR_WRPERR_Pos             (17U)
+#define FLASH_CCR_CLR_WRPERR_Msk             (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */
+#define FLASH_CCR_CLR_WRPERR                 FLASH_CCR_CLR_WRPERR_Msk            /*!< WRPERR flag clear bit */
+#define FLASH_CCR_CLR_PGSERR_Pos             (18U)
+#define FLASH_CCR_CLR_PGSERR_Msk             (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */
+#define FLASH_CCR_CLR_PGSERR                 FLASH_CCR_CLR_PGSERR_Msk            /*!< PGSERR flag clear bit */
+#define FLASH_CCR_CLR_STRBERR_Pos            (19U)
+#define FLASH_CCR_CLR_STRBERR_Msk            (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */
+#define FLASH_CCR_CLR_STRBERR                FLASH_CCR_CLR_STRBERR_Msk            /*!< STRBERR flag clear bit */
+#define FLASH_CCR_CLR_INCERR_Pos             (21U)
+#define FLASH_CCR_CLR_INCERR_Msk             (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00200000 */
+#define FLASH_CCR_CLR_INCERR                 FLASH_CCR_CLR_INCERR_Msk            /*!< INCERR flag clear bit */
+#define FLASH_CCR_CLR_OPERR_Pos              (22U)
+#define FLASH_CCR_CLR_OPERR_Msk              (0x1UL << FLASH_CCR_CLR_OPERR_Pos) /*!< 0x00400000 */
+#define FLASH_CCR_CLR_OPERR                  FLASH_CCR_CLR_OPERR_Msk            /*!< OPERR flag clear bit */
+#define FLASH_CCR_CLR_RDPERR_Pos             (23U)
+#define FLASH_CCR_CLR_RDPERR_Msk             (0x1UL << FLASH_CCR_CLR_RDPERR_Pos) /*!< 0x00800000 */
+#define FLASH_CCR_CLR_RDPERR                 FLASH_CCR_CLR_RDPERR_Msk            /*!< RDPERR flag clear bit */
+#define FLASH_CCR_CLR_RDSERR_Pos             (24U)
+#define FLASH_CCR_CLR_RDSERR_Msk             (0x1UL << FLASH_CCR_CLR_RDSERR_Pos) /*!< 0x01000000 */
+#define FLASH_CCR_CLR_RDSERR                 FLASH_CCR_CLR_RDSERR_Msk            /*!< RDSERR flag clear bit */
+#define FLASH_CCR_CLR_SNECCERR_Pos           (25U)
+#define FLASH_CCR_CLR_SNECCERR_Msk           (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos) /*!< 0x02000000 */
+#define FLASH_CCR_CLR_SNECCERR               FLASH_CCR_CLR_SNECCERR_Msk            /*!< SNECCERR flag clear bit */
+#define FLASH_CCR_CLR_DBECCERR_Pos           (26U)
+#define FLASH_CCR_CLR_DBECCERR_Msk           (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos) /*!< 0x04000000 */
+#define FLASH_CCR_CLR_DBECCERR               FLASH_CCR_CLR_DBECCERR_Msk            /*!< DBECCERR flag clear bit */
+#define FLASH_CCR_CLR_CRCEND_Pos             (27U)
+#define FLASH_CCR_CLR_CRCEND_Msk             (0x1UL << FLASH_CCR_CLR_CRCEND_Pos) /*!< 0x08000000 */
+#define FLASH_CCR_CLR_CRCEND                 FLASH_CCR_CLR_CRCEND_Msk            /*!< CRCEND flag clear bit */
+#define FLASH_CCR_CLR_CRCRDERR_Pos           (28U)
+#define FLASH_CCR_CLR_CRCRDERR_Msk           (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos) /*!< 0x10000000 */
+#define FLASH_CCR_CLR_CRCRDERR               FLASH_CCR_CLR_CRCRDERR_Msk            /*!< CRCRDERR flag clear bit */
+
+/*******************  Bits definition for FLASH_OPTCR register  *******************/
+#define FLASH_OPTCR_OPTLOCK_Pos              (0U)
+#define FLASH_OPTCR_OPTLOCK_Msk              (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)  /*!< 0x00000001 */
+#define FLASH_OPTCR_OPTLOCK                  FLASH_OPTCR_OPTLOCK_Msk             /*!< FLASH_OPTCR lock option configuration bit */
+#define FLASH_OPTCR_OPTSTART_Pos             (1U)
+#define FLASH_OPTCR_OPTSTART_Msk             (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */
+#define FLASH_OPTCR_OPTSTART                 FLASH_OPTCR_OPTSTART_Msk            /*!< Option byte start change option configuration bit */
+#define FLASH_OPTCR_MER_Pos                  (4U)
+#define FLASH_OPTCR_MER_Msk                  (0x1UL << FLASH_OPTCR_MER_Pos)      /*!< 0x00000010 */
+#define FLASH_OPTCR_MER                      FLASH_OPTCR_MER_Msk                 /*!< Mass erase request */
+#define FLASH_OPTCR_OPTCHANGEERRIE_Pos       (30U)
+#define FLASH_OPTCR_OPTCHANGEERRIE_Msk       (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) /*!< 0x40000000 */
+#define FLASH_OPTCR_OPTCHANGEERRIE           FLASH_OPTCR_OPTCHANGEERRIE_Msk            /*!< Option byte change error interrupt enable bit */
+#define FLASH_OPTCR_SWAP_BANK_Pos            (31U)
+#define FLASH_OPTCR_SWAP_BANK_Msk            (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */
+#define FLASH_OPTCR_SWAP_BANK                FLASH_OPTCR_SWAP_BANK_Msk            /*!< Bank swapping option configuration bit */
+
+/*******************  Bits definition for FLASH_OPTSR register  ***************/
+#define FLASH_OPTSR_OPT_BUSY_Pos             (0U)
+#define FLASH_OPTSR_OPT_BUSY_Msk             (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos) /*!< 0x00000001 */
+#define FLASH_OPTSR_OPT_BUSY                 FLASH_OPTSR_OPT_BUSY_Msk            /*!< Option byte change ongoing flag */
+#define FLASH_OPTSR_BOR_LEV_Pos              (2U)
+#define FLASH_OPTSR_BOR_LEV_Msk              (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x0000000C */
+#define FLASH_OPTSR_BOR_LEV                  FLASH_OPTSR_BOR_LEV_Msk            /*!< Brownout level option status bit */
+#define FLASH_OPTSR_BOR_LEV_0                (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000004 */
+#define FLASH_OPTSR_BOR_LEV_1                (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000008 */
+#define FLASH_OPTSR_IWDG1_SW_Pos             (4U)
+#define FLASH_OPTSR_IWDG1_SW_Msk             (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos) /*!< 0x00000010 */
+#define FLASH_OPTSR_IWDG1_SW                 FLASH_OPTSR_IWDG1_SW_Msk            /*!< IWDG1 control mode option status bit */
+#define FLASH_OPTSR_NRST_STOP_D1_Pos         (6U)
+#define FLASH_OPTSR_NRST_STOP_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos) /*!< 0x00000040 */
+#define FLASH_OPTSR_NRST_STOP_D1             FLASH_OPTSR_NRST_STOP_D1_Msk            /*!< D1 domain DStop entry reset option status bit */
+#define FLASH_OPTSR_NRST_STBY_D1_Pos         (7U)
+#define FLASH_OPTSR_NRST_STBY_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos) /*!< 0x00000080 */
+#define FLASH_OPTSR_NRST_STBY_D1             FLASH_OPTSR_NRST_STBY_D1_Msk            /*!< D1 domain DStandby entry reset option status bit */
+#define FLASH_OPTSR_RDP_Pos                  (8U)
+#define FLASH_OPTSR_RDP_Msk                  (0xFFUL << FLASH_OPTSR_RDP_Pos)   /*!< 0x0000FF00 */
+#define FLASH_OPTSR_RDP                      FLASH_OPTSR_RDP_Msk               /*!< Readout protection level option status byte */
+#define FLASH_OPTSR_FZ_IWDG_STOP_Pos         (17U)
+#define FLASH_OPTSR_FZ_IWDG_STOP_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos) /*!< 0x00020000 */
+#define FLASH_OPTSR_FZ_IWDG_STOP             FLASH_OPTSR_FZ_IWDG_STOP_Msk            /*!< IWDG Stop mode freeze option status bit */
+#define FLASH_OPTSR_FZ_IWDG_SDBY_Pos         (18U)
+#define FLASH_OPTSR_FZ_IWDG_SDBY_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos) /*!< 0x00040000 */
+#define FLASH_OPTSR_FZ_IWDG_SDBY             FLASH_OPTSR_FZ_IWDG_SDBY_Msk            /*!< IWDG Standby mode freeze option status bit */
+#define FLASH_OPTSR_ST_RAM_SIZE_Pos          (19U)
+#define FLASH_OPTSR_ST_RAM_SIZE_Msk          (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00180000 */
+#define FLASH_OPTSR_ST_RAM_SIZE              FLASH_OPTSR_ST_RAM_SIZE_Msk            /*!< ST RAM size option status */
+#define FLASH_OPTSR_ST_RAM_SIZE_0            (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00080000 */
+#define FLASH_OPTSR_ST_RAM_SIZE_1            (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00100000 */
+#define FLASH_OPTSR_SECURITY_Pos             (21U)
+#define FLASH_OPTSR_SECURITY_Msk             (0x1UL << FLASH_OPTSR_SECURITY_Pos) /*!< 0x00200000 */
+#define FLASH_OPTSR_SECURITY                 FLASH_OPTSR_SECURITY_Msk            /*!< Security enable option status bit */
+#define FLASH_OPTSR_IO_HSLV_Pos              (29U)
+#define FLASH_OPTSR_IO_HSLV_Msk              (0x1UL << FLASH_OPTSR_IO_HSLV_Pos) /*!< 0x20000000 */
+#define FLASH_OPTSR_IO_HSLV                  FLASH_OPTSR_IO_HSLV_Msk            /*!< I/O high-speed at low-voltage status bit */
+#define FLASH_OPTSR_OPTCHANGEERR_Pos         (30U)
+#define FLASH_OPTSR_OPTCHANGEERR_Msk         (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) /*!< 0x40000000 */
+#define FLASH_OPTSR_OPTCHANGEERR             FLASH_OPTSR_OPTCHANGEERR_Msk            /*!< Option byte change error flag */
+#define FLASH_OPTSR_SWAP_BANK_OPT_Pos        (31U)
+#define FLASH_OPTSR_SWAP_BANK_OPT_Msk        (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos) /*!< 0x80000000 */
+#define FLASH_OPTSR_SWAP_BANK_OPT            FLASH_OPTSR_SWAP_BANK_OPT_Msk            /*!< Bank swapping option status bit */
+
+/*******************  Bits definition for FLASH_OPTCCR register  *******************/
+#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos    (30U)
+#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk    (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos) /*!< 0x40000000 */
+#define FLASH_OPTCCR_CLR_OPTCHANGEERR        FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk            /*!< OPTCHANGEERR reset bit */
+
+/*******************  Bits definition for FLASH_PRAR register  *********************/
+#define FLASH_PRAR_PROT_AREA_START_Pos       (0U)
+#define FLASH_PRAR_PROT_AREA_START_Msk       (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos) /*!< 0x00000FFF */
+#define FLASH_PRAR_PROT_AREA_START           FLASH_PRAR_PROT_AREA_START_Msk              /*!< PCROP area start status bits */
+#define FLASH_PRAR_PROT_AREA_END_Pos         (16U)
+#define FLASH_PRAR_PROT_AREA_END_Msk         (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos) /*!< 0x0FFF0000 */
+#define FLASH_PRAR_PROT_AREA_END             FLASH_PRAR_PROT_AREA_END_Msk              /*!< PCROP area end status bits */
+#define FLASH_PRAR_DMEP_Pos                  (31U)
+#define FLASH_PRAR_DMEP_Msk                  (0x1UL << FLASH_PRAR_DMEP_Pos)    /*!< 0x80000000 */
+#define FLASH_PRAR_DMEP                      FLASH_PRAR_DMEP_Msk               /*!< PCROP protected erase enable option status bit */
+
+/*******************  Bits definition for FLASH_SCAR register  *********************/
+#define FLASH_SCAR_SEC_AREA_START_Pos        (0U)
+#define FLASH_SCAR_SEC_AREA_START_Msk        (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos) /*!< 0x00000FFF */
+#define FLASH_SCAR_SEC_AREA_START            FLASH_SCAR_SEC_AREA_START_Msk              /*!< Secure-only area start status bits */
+#define FLASH_SCAR_SEC_AREA_END_Pos          (16U)
+#define FLASH_SCAR_SEC_AREA_END_Msk          (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos) /*!< 0x0FFF0000 */
+#define FLASH_SCAR_SEC_AREA_END              FLASH_SCAR_SEC_AREA_END_Msk              /*!< Secure-only area end status bits */
+#define FLASH_SCAR_DMES_Pos                  (31U)
+#define FLASH_SCAR_DMES_Msk                  (0x1UL << FLASH_SCAR_DMES_Pos)    /*!< 0x80000000 */
+#define FLASH_SCAR_DMES                      FLASH_SCAR_DMES_Msk               /*!< Secure access protected erase enable option status bit */
+
+/*******************  Bits definition for FLASH_WPSN register  *********************/
+#define FLASH_WPSN_WRPSN_Pos                 (0U)
+#define FLASH_WPSN_WRPSN_Msk                 (0xFFUL << FLASH_WPSN_WRPSN_Pos)  /*!< 0x000000FF */
+#define FLASH_WPSN_WRPSN                     FLASH_WPSN_WRPSN_Msk              /*!< Sector write protection option status byte */
+
+/*******************  Bits definition for FLASH_BOOT_CUR register  ****************/
+#define FLASH_BOOT_ADD0_Pos                  (0U)
+#define FLASH_BOOT_ADD0_Msk                  (0xFFFFUL << FLASH_BOOT_ADD0_Pos) /*!< 0x0000FFFF */
+#define FLASH_BOOT_ADD0                      FLASH_BOOT_ADD0_Msk               /*!< Arm Cortex-M7 boot address 0 */
+#define FLASH_BOOT_ADD1_Pos                  (16U)
+#define FLASH_BOOT_ADD1_Msk                  (0xFFFFUL << FLASH_BOOT_ADD1_Pos) /*!< 0xFFFF0000 */
+#define FLASH_BOOT_ADD1                      FLASH_BOOT_ADD1_Msk               /*!< Arm Cortex-M7 boot address 1 */
+
+
+/*******************  Bits definition for FLASH_CRCCR register  ********************/
+#define FLASH_CRCCR_CRC_SECT_Pos             (0U)
+#define FLASH_CRCCR_CRC_SECT_Msk             (0x7UL << FLASH_CRCCR_CRC_SECT_Pos) /*!< 0x00000007 */
+#define FLASH_CRCCR_CRC_SECT                 FLASH_CRCCR_CRC_SECT_Msk            /*!< CRC sector number */
+#define FLASH_CRCCR_CRC_BY_SECT_Pos          (8U)
+#define FLASH_CRCCR_CRC_BY_SECT_Msk          (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos) /*!< 0x00000100 */
+#define FLASH_CRCCR_CRC_BY_SECT              FLASH_CRCCR_CRC_BY_SECT_Msk            /*!< CRC sector mode select bit */
+#define FLASH_CRCCR_ADD_SECT_Pos             (9U)
+#define FLASH_CRCCR_ADD_SECT_Msk             (0x1UL << FLASH_CRCCR_ADD_SECT_Pos) /*!< 0x00000200 */
+#define FLASH_CRCCR_ADD_SECT                 FLASH_CRCCR_ADD_SECT_Msk            /*!< CRC sector select bit */
+#define FLASH_CRCCR_CLEAN_SECT_Pos           (10U)
+#define FLASH_CRCCR_CLEAN_SECT_Msk           (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos) /*!< 0x00000400 */
+#define FLASH_CRCCR_CLEAN_SECT               FLASH_CRCCR_CLEAN_SECT_Msk            /*!< CRC sector list clear bit */
+#define FLASH_CRCCR_START_CRC_Pos            (16U)
+#define FLASH_CRCCR_START_CRC_Msk            (0x1UL << FLASH_CRCCR_START_CRC_Pos) /*!< 0x00010000 */
+#define FLASH_CRCCR_START_CRC                FLASH_CRCCR_START_CRC_Msk            /*!< CRC start bit */
+#define FLASH_CRCCR_CLEAN_CRC_Pos            (17U)
+#define FLASH_CRCCR_CLEAN_CRC_Msk            (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos) /*!< 0x00020000 */
+#define FLASH_CRCCR_CLEAN_CRC                FLASH_CRCCR_CLEAN_CRC_Msk            /*!< CRC clear bit */
+#define FLASH_CRCCR_CRC_BURST_Pos            (20U)
+#define FLASH_CRCCR_CRC_BURST_Msk            (0x3UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00300000 */
+#define FLASH_CRCCR_CRC_BURST                FLASH_CRCCR_CRC_BURST_Msk            /*!< CRC burst size */
+#define FLASH_CRCCR_CRC_BURST_0              (0x1UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00100000 */
+#define FLASH_CRCCR_CRC_BURST_1              (0x2UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00200000 */
+#define FLASH_CRCCR_ALL_BANK_Pos             (22U)
+#define FLASH_CRCCR_ALL_BANK_Msk             (0x1UL << FLASH_CRCCR_ALL_BANK_Pos) /*!< 0x00400000 */
+#define FLASH_CRCCR_ALL_BANK                 FLASH_CRCCR_ALL_BANK_Msk            /*!< CRC select bit */
+
+/*******************  Bits definition for FLASH_CRCSADD register  ****************/
+#define FLASH_CRCSADD_CRC_START_ADDR_Pos     (0U)
+#define FLASH_CRCSADD_CRC_START_ADDR_Msk     (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_CRCSADD_CRC_START_ADDR         FLASH_CRCSADD_CRC_START_ADDR_Msk                   /*!< CRC start address */
+
+/*******************  Bits definition for FLASH_CRCEADD register  ****************/
+#define FLASH_CRCEADD_CRC_END_ADDR_Pos       (0U)
+#define FLASH_CRCEADD_CRC_END_ADDR_Msk       (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_CRCEADD_CRC_END_ADDR           FLASH_CRCEADD_CRC_END_ADDR_Msk                   /*!< CRC end address */
+
+/*******************  Bits definition for FLASH_CRCDATA register  ***************/
+#define FLASH_CRCDATA_CRC_DATA_Pos           (0U)
+#define FLASH_CRCDATA_CRC_DATA_Msk           (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_CRCDATA_CRC_DATA               FLASH_CRCDATA_CRC_DATA_Msk                   /*!< CRC result */
+
+/*******************  Bits definition for FLASH_ECC_FA register  *******************/
+#define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos       (0U)
+#define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk       (0x7FFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos) /*!< 0x00007FFF */
+#define FLASH_ECC_FA_FAIL_ECC_ADDR           FLASH_ECC_FA_FAIL_ECC_ADDR_Msk               /*!< ECC error address */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Flexible Memory Controller                        */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for FMC_BCR1 register  *******************/
+#define FMC_BCR1_CCLKEN_Pos        (20U)
+#define FMC_BCR1_CCLKEN_Msk        (0x1UL << FMC_BCR1_CCLKEN_Pos)              /*!< 0x00100000 */
+#define FMC_BCR1_CCLKEN            FMC_BCR1_CCLKEN_Msk                         /*!<Continous clock enable     */
+#define FMC_BCR1_WFDIS_Pos         (21U)
+#define FMC_BCR1_WFDIS_Msk         (0x1UL << FMC_BCR1_WFDIS_Pos)               /*!< 0x00200000 */
+#define FMC_BCR1_WFDIS             FMC_BCR1_WFDIS_Msk                          /*!<Write FIFO Disable         */
+
+#define FMC_BCR1_BMAP_Pos          (24U)
+#define FMC_BCR1_BMAP_Msk          (0x3UL << FMC_BCR1_BMAP_Pos)                /*!< 0x03000000 */
+#define FMC_BCR1_BMAP              FMC_BCR1_BMAP_Msk                           /*!<BMAP[1:0] FMC bank mapping */
+#define FMC_BCR1_BMAP_0            (0x1UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x01000000 */
+#define FMC_BCR1_BMAP_1            (0x2UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x02000000 */
+
+#define FMC_BCR1_FMCEN_Pos         (31U)
+#define FMC_BCR1_FMCEN_Msk         (0x1UL << FMC_BCR1_FMCEN_Pos)               /*!< 0x80000000 */
+#define FMC_BCR1_FMCEN             FMC_BCR1_FMCEN_Msk                          /*!<FMC controller Enable */
+/******************  Bit definition for FMC_BCRx registers (x=1..4)  *********/
+#define FMC_BCRx_MBKEN_Pos         (0U)
+#define FMC_BCRx_MBKEN_Msk         (0x1UL << FMC_BCRx_MBKEN_Pos)               /*!< 0x00000001 */
+#define FMC_BCRx_MBKEN             FMC_BCRx_MBKEN_Msk                          /*!<Memory bank enable bit                 */
+#define FMC_BCRx_MUXEN_Pos         (1U)
+#define FMC_BCRx_MUXEN_Msk         (0x1UL << FMC_BCRx_MUXEN_Pos)               /*!< 0x00000002 */
+#define FMC_BCRx_MUXEN             FMC_BCRx_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */
+
+#define FMC_BCRx_MTYP_Pos          (2U)
+#define FMC_BCRx_MTYP_Msk          (0x3UL << FMC_BCRx_MTYP_Pos)                /*!< 0x0000000C */
+#define FMC_BCRx_MTYP              FMC_BCRx_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */
+#define FMC_BCRx_MTYP_0            (0x1UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000004 */
+#define FMC_BCRx_MTYP_1            (0x2UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000008 */
+
+#define FMC_BCRx_MWID_Pos          (4U)
+#define FMC_BCRx_MWID_Msk          (0x3UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000030 */
+#define FMC_BCRx_MWID              FMC_BCRx_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCRx_MWID_0            (0x1UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000010 */
+#define FMC_BCRx_MWID_1            (0x2UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000020 */
+
+#define FMC_BCRx_FACCEN_Pos        (6U)
+#define FMC_BCRx_FACCEN_Msk        (0x1UL << FMC_BCRx_FACCEN_Pos)              /*!< 0x00000040 */
+#define FMC_BCRx_FACCEN            FMC_BCRx_FACCEN_Msk                         /*!<Flash access enable        */
+#define FMC_BCRx_BURSTEN_Pos       (8U)
+#define FMC_BCRx_BURSTEN_Msk       (0x1UL << FMC_BCRx_BURSTEN_Pos)             /*!< 0x00000100 */
+#define FMC_BCRx_BURSTEN           FMC_BCRx_BURSTEN_Msk                        /*!<Burst enable bit           */
+#define FMC_BCRx_WAITPOL_Pos       (9U)
+#define FMC_BCRx_WAITPOL_Msk       (0x1UL << FMC_BCRx_WAITPOL_Pos)             /*!< 0x00000200 */
+#define FMC_BCRx_WAITPOL           FMC_BCRx_WAITPOL_Msk                        /*!<Wait signal polarity bit   */
+#define FMC_BCRx_WAITCFG_Pos       (11U)
+#define FMC_BCRx_WAITCFG_Msk       (0x1UL << FMC_BCRx_WAITCFG_Pos)             /*!< 0x00000800 */
+#define FMC_BCRx_WAITCFG           FMC_BCRx_WAITCFG_Msk                        /*!<Wait timing configuration  */
+#define FMC_BCRx_WREN_Pos          (12U)
+#define FMC_BCRx_WREN_Msk          (0x1UL << FMC_BCRx_WREN_Pos)                /*!< 0x00001000 */
+#define FMC_BCRx_WREN              FMC_BCRx_WREN_Msk                           /*!<Write enable bit           */
+#define FMC_BCRx_WAITEN_Pos        (13U)
+#define FMC_BCRx_WAITEN_Msk        (0x1UL << FMC_BCRx_WAITEN_Pos)              /*!< 0x00002000 */
+#define FMC_BCRx_WAITEN            FMC_BCRx_WAITEN_Msk                         /*!<Wait enable bit            */
+#define FMC_BCRx_EXTMOD_Pos        (14U)
+#define FMC_BCRx_EXTMOD_Msk        (0x1UL << FMC_BCRx_EXTMOD_Pos)              /*!< 0x00004000 */
+#define FMC_BCRx_EXTMOD            FMC_BCRx_EXTMOD_Msk                         /*!<Extended mode enable       */
+#define FMC_BCRx_ASYNCWAIT_Pos     (15U)
+#define FMC_BCRx_ASYNCWAIT_Msk     (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)           /*!< 0x00008000 */
+#define FMC_BCRx_ASYNCWAIT         FMC_BCRx_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */
+
+#define FMC_BCRx_CPSIZE_Pos        (16U)
+#define FMC_BCRx_CPSIZE_Msk        (0x7UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00070000 */
+#define FMC_BCRx_CPSIZE            FMC_BCRx_CPSIZE_Msk                         /*!<PSIZE[2:0] bits CRAM Page Size */
+#define FMC_BCRx_CPSIZE_0          (0x1UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00010000 */
+#define FMC_BCRx_CPSIZE_1          (0x2UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00020000 */
+#define FMC_BCRx_CPSIZE_2          (0x4UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00040000 */
+
+#define FMC_BCRx_CBURSTRW_Pos      (19U)
+#define FMC_BCRx_CBURSTRW_Msk      (0x1UL << FMC_BCRx_CBURSTRW_Pos)            /*!< 0x00080000 */
+#define FMC_BCRx_CBURSTRW          FMC_BCRx_CBURSTRW_Msk                       /*!<Write burst enable         */
+
+/******************  Bit definition for FMC_BTRx registers (x=1..4)  *********/
+#define FMC_BTRx_ADDSET_Pos        (0U)
+#define FMC_BTRx_ADDSET_Msk        (0xFUL << FMC_BTRx_ADDSET_Pos)              /*!< 0x0000000F */
+#define FMC_BTRx_ADDSET            FMC_BTRx_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTRx_ADDSET_0          (0x1UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000001 */
+#define FMC_BTRx_ADDSET_1          (0x2UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000002 */
+#define FMC_BTRx_ADDSET_2          (0x4UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000004 */
+#define FMC_BTRx_ADDSET_3          (0x8UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000008 */
+
+#define FMC_BTRx_ADDHLD_Pos        (4U)
+#define FMC_BTRx_ADDHLD_Msk        (0xFUL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x000000F0 */
+#define FMC_BTRx_ADDHLD            FMC_BTRx_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
+#define FMC_BTRx_ADDHLD_0          (0x1UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000010 */
+#define FMC_BTRx_ADDHLD_1          (0x2UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000020 */
+#define FMC_BTRx_ADDHLD_2          (0x4UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000040 */
+#define FMC_BTRx_ADDHLD_3          (0x8UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000080 */
+
+#define FMC_BTRx_DATAST_Pos        (8U)
+#define FMC_BTRx_DATAST_Msk        (0xFFUL << FMC_BTRx_DATAST_Pos)             /*!< 0x0000FF00 */
+#define FMC_BTRx_DATAST            FMC_BTRx_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTRx_DATAST_0          (0x01UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000100 */
+#define FMC_BTRx_DATAST_1          (0x02UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000200 */
+#define FMC_BTRx_DATAST_2          (0x04UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000400 */
+#define FMC_BTRx_DATAST_3          (0x08UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000800 */
+#define FMC_BTRx_DATAST_4          (0x10UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00001000 */
+#define FMC_BTRx_DATAST_5          (0x20UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00002000 */
+#define FMC_BTRx_DATAST_6          (0x40UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00004000 */
+#define FMC_BTRx_DATAST_7          (0x80UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00008000 */
+
+#define FMC_BTRx_BUSTURN_Pos       (16U)
+#define FMC_BTRx_BUSTURN_Msk       (0xFUL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x000F0000 */
+#define FMC_BTRx_BUSTURN           FMC_BTRx_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTRx_BUSTURN_0         (0x1UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00010000 */
+#define FMC_BTRx_BUSTURN_1         (0x2UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00020000 */
+#define FMC_BTRx_BUSTURN_2         (0x4UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00040000 */
+#define FMC_BTRx_BUSTURN_3         (0x8UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00080000 */
+
+#define FMC_BTRx_CLKDIV_Pos        (20U)
+#define FMC_BTRx_CLKDIV_Msk        (0xFUL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00F00000 */
+#define FMC_BTRx_CLKDIV            FMC_BTRx_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTRx_CLKDIV_0          (0x1UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00100000 */
+#define FMC_BTRx_CLKDIV_1          (0x2UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00200000 */
+#define FMC_BTRx_CLKDIV_2          (0x4UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00400000 */
+#define FMC_BTRx_CLKDIV_3          (0x8UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00800000 */
+
+#define FMC_BTRx_DATLAT_Pos        (24U)
+#define FMC_BTRx_DATLAT_Msk        (0xFUL << FMC_BTRx_DATLAT_Pos)              /*!< 0x0F000000 */
+#define FMC_BTRx_DATLAT            FMC_BTRx_DATLAT_Msk                         /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTRx_DATLAT_0          (0x1UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x01000000 */
+#define FMC_BTRx_DATLAT_1          (0x2UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x02000000 */
+#define FMC_BTRx_DATLAT_2          (0x4UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x04000000 */
+#define FMC_BTRx_DATLAT_3          (0x8UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x08000000 */
+
+#define FMC_BTRx_ACCMOD_Pos        (28U)
+#define FMC_BTRx_ACCMOD_Msk        (0x3UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x30000000 */
+#define FMC_BTRx_ACCMOD            FMC_BTRx_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTRx_ACCMOD_0          (0x1UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x10000000 */
+#define FMC_BTRx_ACCMOD_1          (0x2UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x20000000 */
+
+/******************  Bit definition for FMC_BWTRx registers (x=1..4)  *********/
+#define FMC_BWTRx_ADDSET_Pos       (0U)
+#define FMC_BWTRx_ADDSET_Msk       (0xFUL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x0000000F */
+#define FMC_BWTRx_ADDSET           FMC_BWTRx_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTRx_ADDSET_0         (0x1UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000001 */
+#define FMC_BWTRx_ADDSET_1         (0x2UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000002 */
+#define FMC_BWTRx_ADDSET_2         (0x4UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000004 */
+#define FMC_BWTRx_ADDSET_3         (0x8UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000008 */
+
+#define FMC_BWTRx_ADDHLD_Pos       (4U)
+#define FMC_BWTRx_ADDHLD_Msk       (0xFUL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x000000F0 */
+#define FMC_BWTRx_ADDHLD           FMC_BWTRx_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTRx_ADDHLD_0         (0x1UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000010 */
+#define FMC_BWTRx_ADDHLD_1         (0x2UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000020 */
+#define FMC_BWTRx_ADDHLD_2         (0x4UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000040 */
+#define FMC_BWTRx_ADDHLD_3         (0x8UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000080 */
+
+#define FMC_BWTRx_DATAST_Pos       (8U)
+#define FMC_BWTRx_DATAST_Msk       (0xFFUL << FMC_BWTRx_DATAST_Pos)            /*!< 0x0000FF00 */
+#define FMC_BWTRx_DATAST           FMC_BWTRx_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTRx_DATAST_0         (0x01UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000100 */
+#define FMC_BWTRx_DATAST_1         (0x02UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000200 */
+#define FMC_BWTRx_DATAST_2         (0x04UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000400 */
+#define FMC_BWTRx_DATAST_3         (0x08UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000800 */
+#define FMC_BWTRx_DATAST_4         (0x10UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00001000 */
+#define FMC_BWTRx_DATAST_5         (0x20UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00002000 */
+#define FMC_BWTRx_DATAST_6         (0x40UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00004000 */
+#define FMC_BWTRx_DATAST_7         (0x80UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00008000 */
+
+#define FMC_BWTRx_BUSTURN_Pos      (16U)
+#define FMC_BWTRx_BUSTURN_Msk      (0xFUL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x000F0000 */
+#define FMC_BWTRx_BUSTURN          FMC_BWTRx_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BWTRx_BUSTURN_0        (0x1UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00010000 */
+#define FMC_BWTRx_BUSTURN_1        (0x2UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00020000 */
+#define FMC_BWTRx_BUSTURN_2        (0x4UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00040000 */
+#define FMC_BWTRx_BUSTURN_3        (0x8UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00080000 */
+
+#define FMC_BWTRx_ACCMOD_Pos       (28U)
+#define FMC_BWTRx_ACCMOD_Msk       (0x3UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x30000000 */
+#define FMC_BWTRx_ACCMOD           FMC_BWTRx_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTRx_ACCMOD_0         (0x1UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x10000000 */
+#define FMC_BWTRx_ACCMOD_1         (0x2UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x20000000 */
+
+/******************  Bit definition for FMC_PCR register  *******************/
+#define FMC_PCR_PWAITEN_Pos        (1U)
+#define FMC_PCR_PWAITEN_Msk        (0x1UL << FMC_PCR_PWAITEN_Pos)              /*!< 0x00000002 */
+#define FMC_PCR_PWAITEN            FMC_PCR_PWAITEN_Msk                         /*!<Wait feature enable bit                   */
+#define FMC_PCR_PBKEN_Pos          (2U)
+#define FMC_PCR_PBKEN_Msk          (0x1UL << FMC_PCR_PBKEN_Pos)                /*!< 0x00000004 */
+#define FMC_PCR_PBKEN              FMC_PCR_PBKEN_Msk                           /*!<NAND Flash memory bank enable bit */
+
+#define FMC_PCR_PWID_Pos           (4U)
+#define FMC_PCR_PWID_Msk           (0x3UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000030 */
+#define FMC_PCR_PWID               FMC_PCR_PWID_Msk                            /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR_PWID_0             (0x1UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000010 */
+#define FMC_PCR_PWID_1             (0x2UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000020 */
+
+#define FMC_PCR_ECCEN_Pos          (6U)
+#define FMC_PCR_ECCEN_Msk          (0x1UL << FMC_PCR_ECCEN_Pos)                /*!< 0x00000040 */
+#define FMC_PCR_ECCEN              FMC_PCR_ECCEN_Msk                           /*!<ECC computation logic enable bit          */
+
+#define FMC_PCR_TCLR_Pos           (9U)
+#define FMC_PCR_TCLR_Msk           (0xFUL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001E00 */
+#define FMC_PCR_TCLR               FMC_PCR_TCLR_Msk                            /*!<TCLR[3:0] bits (CLE to RE delay)          */
+#define FMC_PCR_TCLR_0             (0x1UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000200 */
+#define FMC_PCR_TCLR_1             (0x2UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000400 */
+#define FMC_PCR_TCLR_2             (0x4UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000800 */
+#define FMC_PCR_TCLR_3             (0x8UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00001000 */
+
+#define FMC_PCR_TAR_Pos            (13U)
+#define FMC_PCR_TAR_Msk            (0xFUL << FMC_PCR_TAR_Pos)                  /*!< 0x0001E000 */
+#define FMC_PCR_TAR                FMC_PCR_TAR_Msk                             /*!<TAR[3:0] bits (ALE to RE delay)           */
+#define FMC_PCR_TAR_0              (0x1UL << FMC_PCR_TAR_Pos)                   /*!< 0x00002000 */
+#define FMC_PCR_TAR_1              (0x2UL << FMC_PCR_TAR_Pos)                   /*!< 0x00004000 */
+#define FMC_PCR_TAR_2              (0x4UL << FMC_PCR_TAR_Pos)                   /*!< 0x00008000 */
+#define FMC_PCR_TAR_3              (0x8UL << FMC_PCR_TAR_Pos)                   /*!< 0x00010000 */
+
+#define FMC_PCR_ECCPS_Pos          (17U)
+#define FMC_PCR_ECCPS_Msk          (0x7UL << FMC_PCR_ECCPS_Pos)                /*!< 0x000E0000 */
+#define FMC_PCR_ECCPS              FMC_PCR_ECCPS_Msk                           /*!<ECCPS[1:0] bits (ECC page size)           */
+#define FMC_PCR_ECCPS_0            (0x1UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00020000 */
+#define FMC_PCR_ECCPS_1            (0x2UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00040000 */
+#define FMC_PCR_ECCPS_2            (0x4UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00080000 */
+
+/*******************  Bit definition for FMC_SR register  *******************/
+#define FMC_SR_IRS_Pos             (0U)
+#define FMC_SR_IRS_Msk             (0x1UL << FMC_SR_IRS_Pos)                   /*!< 0x00000001 */
+#define FMC_SR_IRS                 FMC_SR_IRS_Msk                              /*!<Interrupt Rising Edge status                */
+#define FMC_SR_ILS_Pos             (1U)
+#define FMC_SR_ILS_Msk             (0x1UL << FMC_SR_ILS_Pos)                   /*!< 0x00000002 */
+#define FMC_SR_ILS                 FMC_SR_ILS_Msk                              /*!<Interrupt Level status                      */
+#define FMC_SR_IFS_Pos             (2U)
+#define FMC_SR_IFS_Msk             (0x1UL << FMC_SR_IFS_Pos)                   /*!< 0x00000004 */
+#define FMC_SR_IFS                 FMC_SR_IFS_Msk                              /*!<Interrupt Falling Edge status               */
+#define FMC_SR_IREN_Pos            (3U)
+#define FMC_SR_IREN_Msk            (0x1UL << FMC_SR_IREN_Pos)                  /*!< 0x00000008 */
+#define FMC_SR_IREN                FMC_SR_IREN_Msk                             /*!<Interrupt Rising Edge detection Enable bit  */
+#define FMC_SR_ILEN_Pos            (4U)
+#define FMC_SR_ILEN_Msk            (0x1UL << FMC_SR_ILEN_Pos)                  /*!< 0x00000010 */
+#define FMC_SR_ILEN                FMC_SR_ILEN_Msk                             /*!<Interrupt Level detection Enable bit        */
+#define FMC_SR_IFEN_Pos            (5U)
+#define FMC_SR_IFEN_Msk            (0x1UL << FMC_SR_IFEN_Pos)                  /*!< 0x00000020 */
+#define FMC_SR_IFEN                FMC_SR_IFEN_Msk                             /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR_FEMPT_Pos           (6U)
+#define FMC_SR_FEMPT_Msk           (0x1UL << FMC_SR_FEMPT_Pos)                 /*!< 0x00000040 */
+#define FMC_SR_FEMPT               FMC_SR_FEMPT_Msk                            /*!<FIFO empty                                  */
+
+/******************  Bit definition for FMC_PMEM register  ******************/
+#define FMC_PMEM_MEMSET_Pos       (0U)
+#define FMC_PMEM_MEMSET_Msk       (0xFFUL << FMC_PMEM_MEMSET_Pos)            /*!< 0x000000FF */
+#define FMC_PMEM_MEMSET           FMC_PMEM_MEMSET_Msk                        /*!<MEMSET[7:0] bits (Common memory setup time) */
+#define FMC_PMEM_MEMSET_0         (0x01UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000001 */
+#define FMC_PMEM_MEMSET_1         (0x02UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000002 */
+#define FMC_PMEM_MEMSET_2         (0x04UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000004 */
+#define FMC_PMEM_MEMSET_3         (0x08UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000008 */
+#define FMC_PMEM_MEMSET_4         (0x10UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000010 */
+#define FMC_PMEM_MEMSET_5         (0x20UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000020 */
+#define FMC_PMEM_MEMSET_6         (0x40UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000040 */
+#define FMC_PMEM_MEMSET_7         (0x80UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000080 */
+
+#define FMC_PMEM_MEMWAIT_Pos      (8U)
+#define FMC_PMEM_MEMWAIT_Msk      (0xFFUL << FMC_PMEM_MEMWAIT_Pos)           /*!< 0x0000FF00 */
+#define FMC_PMEM_MEMWAIT          FMC_PMEM_MEMWAIT_Msk                       /*!<MEMWAIT[7:0] bits (Common memory wait time) */
+#define FMC_PMEM_MEMWAIT_0        (0x01UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000100 */
+#define FMC_PMEM_MEMWAIT_1        (0x02UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000200 */
+#define FMC_PMEM_MEMWAIT_2        (0x04UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000400 */
+#define FMC_PMEM_MEMWAIT_3        (0x08UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000800 */
+#define FMC_PMEM_MEMWAIT_4        (0x10UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00001000 */
+#define FMC_PMEM_MEMWAIT_5        (0x20UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00002000 */
+#define FMC_PMEM_MEMWAIT_6        (0x40UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00004000 */
+#define FMC_PMEM_MEMWAIT_7        (0x80UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00008000 */
+
+#define FMC_PMEM_MEMHOLD_Pos      (16U)
+#define FMC_PMEM_MEMHOLD_Msk      (0xFFUL << FMC_PMEM_MEMHOLD_Pos)           /*!< 0x00FF0000 */
+#define FMC_PMEM_MEMHOLD          FMC_PMEM_MEMHOLD_Msk                       /*!<MEMHOLD[7:0] bits (Common memory hold time) */
+#define FMC_PMEM_MEMHOLD_0        (0x01UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00010000 */
+#define FMC_PMEM_MEMHOLD_1        (0x02UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00020000 */
+#define FMC_PMEM_MEMHOLD_2        (0x04UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00040000 */
+#define FMC_PMEM_MEMHOLD_3        (0x08UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00080000 */
+#define FMC_PMEM_MEMHOLD_4        (0x10UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00100000 */
+#define FMC_PMEM_MEMHOLD_5        (0x20UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00200000 */
+#define FMC_PMEM_MEMHOLD_6        (0x40UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00400000 */
+#define FMC_PMEM_MEMHOLD_7        (0x80UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00800000 */
+
+#define FMC_PMEM_MEMHIZ_Pos       (24U)
+#define FMC_PMEM_MEMHIZ_Msk       (0xFFUL << FMC_PMEM_MEMHIZ_Pos)            /*!< 0xFF000000 */
+#define FMC_PMEM_MEMHIZ           FMC_PMEM_MEMHIZ_Msk                        /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */
+#define FMC_PMEM_MEMHIZ_0         (0x01UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x01000000 */
+#define FMC_PMEM_MEMHIZ_1         (0x02UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x02000000 */
+#define FMC_PMEM_MEMHIZ_2         (0x04UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x04000000 */
+#define FMC_PMEM_MEMHIZ_3         (0x08UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x08000000 */
+#define FMC_PMEM_MEMHIZ_4         (0x10UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x10000000 */
+#define FMC_PMEM_MEMHIZ_5         (0x20UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x20000000 */
+#define FMC_PMEM_MEMHIZ_6         (0x40UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x40000000 */
+#define FMC_PMEM_MEMHIZ_7         (0x80UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_PATT register  ******************/
+#define FMC_PATT_ATTSET_Pos       (0U)
+#define FMC_PATT_ATTSET_Msk       (0xFFUL << FMC_PATT_ATTSET_Pos)            /*!< 0x000000FF */
+#define FMC_PATT_ATTSET           FMC_PATT_ATTSET_Msk                        /*!<ATTSET[7:0] bits (Attribute memory setup time) */
+#define FMC_PATT_ATTSET_0         (0x01UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000001 */
+#define FMC_PATT_ATTSET_1         (0x02UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000002 */
+#define FMC_PATT_ATTSET_2         (0x04UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000004 */
+#define FMC_PATT_ATTSET_3         (0x08UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000008 */
+#define FMC_PATT_ATTSET_4         (0x10UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000010 */
+#define FMC_PATT_ATTSET_5         (0x20UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000020 */
+#define FMC_PATT_ATTSET_6         (0x40UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000040 */
+#define FMC_PATT_ATTSET_7         (0x80UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000080 */
+
+#define FMC_PATT_ATTWAIT_Pos      (8U)
+#define FMC_PATT_ATTWAIT_Msk      (0xFFUL << FMC_PATT_ATTWAIT_Pos)           /*!< 0x0000FF00 */
+#define FMC_PATT_ATTWAIT          FMC_PATT_ATTWAIT_Msk                       /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */
+#define FMC_PATT_ATTWAIT_0        (0x01UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000100 */
+#define FMC_PATT_ATTWAIT_1        (0x02UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000200 */
+#define FMC_PATT_ATTWAIT_2        (0x04UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000400 */
+#define FMC_PATT_ATTWAIT_3        (0x08UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000800 */
+#define FMC_PATT_ATTWAIT_4        (0x10UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00001000 */
+#define FMC_PATT_ATTWAIT_5        (0x20UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00002000 */
+#define FMC_PATT_ATTWAIT_6        (0x40UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00004000 */
+#define FMC_PATT_ATTWAIT_7        (0x80UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00008000 */
+
+#define FMC_PATT_ATTHOLD_Pos      (16U)
+#define FMC_PATT_ATTHOLD_Msk      (0xFFUL << FMC_PATT_ATTHOLD_Pos)           /*!< 0x00FF0000 */
+#define FMC_PATT_ATTHOLD          FMC_PATT_ATTHOLD_Msk                       /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */
+#define FMC_PATT_ATTHOLD_0        (0x01UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00010000 */
+#define FMC_PATT_ATTHOLD_1        (0x02UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00020000 */
+#define FMC_PATT_ATTHOLD_2        (0x04UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00040000 */
+#define FMC_PATT_ATTHOLD_3        (0x08UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00080000 */
+#define FMC_PATT_ATTHOLD_4        (0x10UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00100000 */
+#define FMC_PATT_ATTHOLD_5        (0x20UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00200000 */
+#define FMC_PATT_ATTHOLD_6        (0x40UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00400000 */
+#define FMC_PATT_ATTHOLD_7        (0x80UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00800000 */
+
+#define FMC_PATT_ATTHIZ_Pos       (24U)
+#define FMC_PATT_ATTHIZ_Msk       (0xFFUL << FMC_PATT_ATTHIZ_Pos)            /*!< 0xFF000000 */
+#define FMC_PATT_ATTHIZ           FMC_PATT_ATTHIZ_Msk                        /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */
+#define FMC_PATT_ATTHIZ_0         (0x01UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x01000000 */
+#define FMC_PATT_ATTHIZ_1         (0x02UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x02000000 */
+#define FMC_PATT_ATTHIZ_2         (0x04UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x04000000 */
+#define FMC_PATT_ATTHIZ_3         (0x08UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x08000000 */
+#define FMC_PATT_ATTHIZ_4         (0x10UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x10000000 */
+#define FMC_PATT_ATTHIZ_5         (0x20UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x20000000 */
+#define FMC_PATT_ATTHIZ_6         (0x40UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x40000000 */
+#define FMC_PATT_ATTHIZ_7         (0x80UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_ECCR3 register  ******************/
+#define FMC_ECCR3_ECC3_Pos         (0U)
+#define FMC_ECCR3_ECC3_Msk         (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos)        /*!< 0xFFFFFFFF */
+#define FMC_ECCR3_ECC3             FMC_ECCR3_ECC3_Msk                          /*!<ECC result */
+
+/******************  Bit definition for FMC_SDCRx registers (x=1..4)  *********/
+#define FMC_SDCRx_NC_Pos           (0U)
+#define FMC_SDCRx_NC_Msk           (0x3UL << FMC_SDCRx_NC_Pos)                 /*!< 0x00000003 */
+#define FMC_SDCRx_NC               FMC_SDCRx_NC_Msk                            /*!<NC[1:0] bits (Number of column bits) */
+#define FMC_SDCRx_NC_0             (0x1UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000001 */
+#define FMC_SDCRx_NC_1             (0x2UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000002 */
+
+#define FMC_SDCRx_NR_Pos           (2U)
+#define FMC_SDCRx_NR_Msk           (0x3UL << FMC_SDCRx_NR_Pos)                 /*!< 0x0000000C */
+#define FMC_SDCRx_NR               FMC_SDCRx_NR_Msk                            /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCRx_NR_0             (0x1UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000004 */
+#define FMC_SDCRx_NR_1             (0x2UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000008 */
+
+#define FMC_SDCRx_MWID_Pos         (4U)
+#define FMC_SDCRx_MWID_Msk         (0x3UL << FMC_SDCRx_MWID_Pos)               /*!< 0x00000030 */
+#define FMC_SDCRx_MWID             FMC_SDCRx_MWID_Msk                          /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCRx_MWID_0           (0x1UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000010 */
+#define FMC_SDCRx_MWID_1           (0x2UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000020 */
+
+#define FMC_SDCRx_NB_Pos           (6U)
+#define FMC_SDCRx_NB_Msk           (0x1UL << FMC_SDCRx_NB_Pos)                 /*!< 0x00000040 */
+#define FMC_SDCRx_NB               FMC_SDCRx_NB_Msk                            /*!<Number of internal bank */
+
+#define FMC_SDCRx_CAS_Pos          (7U)
+#define FMC_SDCRx_CAS_Msk          (0x3UL << FMC_SDCRx_CAS_Pos)                /*!< 0x00000180 */
+#define FMC_SDCRx_CAS              FMC_SDCRx_CAS_Msk                           /*!<CAS[1:0] bits (CAS latency) */
+#define FMC_SDCRx_CAS_0            (0x1UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000080 */
+#define FMC_SDCRx_CAS_1            (0x2UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000100 */
+
+#define FMC_SDCRx_WP_Pos           (9U)
+#define FMC_SDCRx_WP_Msk           (0x1UL << FMC_SDCRx_WP_Pos)                 /*!< 0x00000200 */
+#define FMC_SDCRx_WP               FMC_SDCRx_WP_Msk                            /*!<Write protection */
+
+#define FMC_SDCRx_SDCLK_Pos        (10U)
+#define FMC_SDCRx_SDCLK_Msk        (0x3UL << FMC_SDCRx_SDCLK_Pos)              /*!< 0x00000C00 */
+#define FMC_SDCRx_SDCLK            FMC_SDCRx_SDCLK_Msk                         /*!<SDRAM clock configuration */
+#define FMC_SDCRx_SDCLK_0          (0x1UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000400 */
+#define FMC_SDCRx_SDCLK_1          (0x2UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000800 */
+
+#define FMC_SDCRx_RBURST_Pos       (12U)
+#define FMC_SDCRx_RBURST_Msk       (0x1UL << FMC_SDCRx_RBURST_Pos)             /*!< 0x00001000 */
+#define FMC_SDCRx_RBURST           FMC_SDCRx_RBURST_Msk                        /*!<Read burst */
+
+#define FMC_SDCRx_RPIPE_Pos        (13U)
+#define FMC_SDCRx_RPIPE_Msk        (0x3UL << FMC_SDCRx_RPIPE_Pos)              /*!< 0x00006000 */
+#define FMC_SDCRx_RPIPE            FMC_SDCRx_RPIPE_Msk                         /*!<Write protection */
+#define FMC_SDCRx_RPIPE_0          (0x1UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00002000 */
+#define FMC_SDCRx_RPIPE_1          (0x2UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00004000 */
+
+/******************  Bit definition for FMC_SDTRx(1,2) register  ******************/
+#define FMC_SDTRx_TMRD_Pos         (0U)
+#define FMC_SDTRx_TMRD_Msk         (0xFUL << FMC_SDTRx_TMRD_Pos)               /*!< 0x0000000F */
+#define FMC_SDTRx_TMRD             FMC_SDTRx_TMRD_Msk                          /*!<TMRD[3:0] bits (Load mode register to active) */
+#define FMC_SDTRx_TMRD_0           (0x1UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000001 */
+#define FMC_SDTRx_TMRD_1           (0x2UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000002 */
+#define FMC_SDTRx_TMRD_2           (0x4UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000004 */
+#define FMC_SDTRx_TMRD_3           (0x8UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000008 */
+
+#define FMC_SDTRx_TXSR_Pos         (4U)
+#define FMC_SDTRx_TXSR_Msk         (0xFUL << FMC_SDTRx_TXSR_Pos)               /*!< 0x000000F0 */
+#define FMC_SDTRx_TXSR             FMC_SDTRx_TXSR_Msk                          /*!<TXSR[3:0] bits (Exit self refresh) */
+#define FMC_SDTRx_TXSR_0           (0x1UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000010 */
+#define FMC_SDTRx_TXSR_1           (0x2UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000020 */
+#define FMC_SDTRx_TXSR_2           (0x4UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000040 */
+#define FMC_SDTRx_TXSR_3           (0x8UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000080 */
+
+#define FMC_SDTRx_TRAS_Pos         (8U)
+#define FMC_SDTRx_TRAS_Msk         (0xFUL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000F00 */
+#define FMC_SDTRx_TRAS             FMC_SDTRx_TRAS_Msk                          /*!<TRAS[3:0] bits (Self refresh time) */
+#define FMC_SDTRx_TRAS_0           (0x1UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000100 */
+#define FMC_SDTRx_TRAS_1           (0x2UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000200 */
+#define FMC_SDTRx_TRAS_2           (0x4UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000400 */
+#define FMC_SDTRx_TRAS_3           (0x8UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000800 */
+
+#define FMC_SDTRx_TRC_Pos          (12U)
+#define FMC_SDTRx_TRC_Msk          (0xFUL << FMC_SDTRx_TRC_Pos)                /*!< 0x0000F000 */
+#define FMC_SDTRx_TRC              FMC_SDTRx_TRC_Msk                           /*!<TRC[2:0] bits (Row cycle delay) */
+#define FMC_SDTRx_TRC_0            (0x1UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00001000 */
+#define FMC_SDTRx_TRC_1            (0x2UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00002000 */
+#define FMC_SDTRx_TRC_2            (0x4UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00004000 */
+
+#define FMC_SDTRx_TWR_Pos          (16U)
+#define FMC_SDTRx_TWR_Msk          (0xFUL << FMC_SDTRx_TWR_Pos)                /*!< 0x000F0000 */
+#define FMC_SDTRx_TWR              FMC_SDTRx_TWR_Msk                           /*!<TRC[2:0] bits (Write recovery delay) */
+#define FMC_SDTRx_TWR_0            (0x1UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00010000 */
+#define FMC_SDTRx_TWR_1            (0x2UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00020000 */
+#define FMC_SDTRx_TWR_2            (0x4UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00040000 */
+
+#define FMC_SDTRx_TRP_Pos          (20U)
+#define FMC_SDTRx_TRP_Msk          (0xFUL << FMC_SDTRx_TRP_Pos)                /*!< 0x00F00000 */
+#define FMC_SDTRx_TRP              FMC_SDTRx_TRP_Msk                           /*!<TRP[2:0] bits (Row precharge delay) */
+#define FMC_SDTRx_TRP_0            (0x1UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00100000 */
+#define FMC_SDTRx_TRP_1            (0x2UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00200000 */
+#define FMC_SDTRx_TRP_2            (0x4UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00400000 */
+
+#define FMC_SDTRx_TRCD_Pos         (24U)
+#define FMC_SDTRx_TRCD_Msk         (0xFUL << FMC_SDTRx_TRCD_Pos)               /*!< 0x0F000000 */
+#define FMC_SDTRx_TRCD             FMC_SDTRx_TRCD_Msk                          /*!<TRP[2:0] bits (Row to column delay) */
+#define FMC_SDTRx_TRCD_0           (0x1UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x01000000 */
+#define FMC_SDTRx_TRCD_1           (0x2UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x02000000 */
+#define FMC_SDTRx_TRCD_2           (0x4UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x04000000 */
+
+/******************  Bit definition for FMC_SDCMR register  ******************/
+#define FMC_SDCMR_MODE_Pos         (0U)
+#define FMC_SDCMR_MODE_Msk         (0x7UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000007 */
+#define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */
+#define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */
+#define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */
+#define FMC_SDCMR_MODE_2           (0x3UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000003 */
+
+#define FMC_SDCMR_CTB2_Pos         (3U)
+#define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */
+#define FMC_SDCMR_CTB2             FMC_SDCMR_CTB2_Msk                          /*!<Command target 2 */
+
+#define FMC_SDCMR_CTB1_Pos         (4U)
+#define FMC_SDCMR_CTB1_Msk         (0x1UL << FMC_SDCMR_CTB1_Pos)               /*!< 0x00000010 */
+#define FMC_SDCMR_CTB1             FMC_SDCMR_CTB1_Msk                          /*!<Command target 1 */
+
+#define FMC_SDCMR_NRFS_Pos         (5U)
+#define FMC_SDCMR_NRFS_Msk         (0xFUL << FMC_SDCMR_NRFS_Pos)               /*!< 0x000001E0 */
+#define FMC_SDCMR_NRFS             FMC_SDCMR_NRFS_Msk                          /*!<NRFS[3:0] bits (Number of auto-refresh) */
+#define FMC_SDCMR_NRFS_0           (0x1UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000020 */
+#define FMC_SDCMR_NRFS_1           (0x2UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000040 */
+#define FMC_SDCMR_NRFS_2           (0x4UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000080 */
+#define FMC_SDCMR_NRFS_3           (0x8UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000100 */
+
+#define FMC_SDCMR_MRD_Pos          (9U)
+#define FMC_SDCMR_MRD_Msk          (0x1FFFUL << FMC_SDCMR_MRD_Pos)             /*!< 0x003FFE00 */
+#define FMC_SDCMR_MRD              FMC_SDCMR_MRD_Msk                           /*!<MRD[12:0] bits (Mode register definition) */
+
+/******************  Bit definition for FMC_SDRTR register  ******************/
+#define FMC_SDRTR_CRE_Pos          (0U)
+#define FMC_SDRTR_CRE_Msk          (0x1UL << FMC_SDRTR_CRE_Pos)                /*!< 0x00000001 */
+#define FMC_SDRTR_CRE              FMC_SDRTR_CRE_Msk                           /*!<Clear refresh error flag */
+
+#define FMC_SDRTR_COUNT_Pos        (1U)
+#define FMC_SDRTR_COUNT_Msk        (0x1FFFUL << FMC_SDRTR_COUNT_Pos)           /*!< 0x00003FFE */
+#define FMC_SDRTR_COUNT            FMC_SDRTR_COUNT_Msk                         /*!<COUNT[12:0] bits (Refresh timer count) */
+
+#define FMC_SDRTR_REIE_Pos         (14U)
+#define FMC_SDRTR_REIE_Msk         (0x1UL << FMC_SDRTR_REIE_Pos)               /*!< 0x00004000 */
+#define FMC_SDRTR_REIE             FMC_SDRTR_REIE_Msk                          /*!<RES interupt enable */
+
+/******************  Bit definition for FMC_SDSR register  ******************/
+#define FMC_SDSR_RE_Pos            (0U)
+#define FMC_SDSR_RE_Msk            (0x1UL << FMC_SDSR_RE_Pos)                  /*!< 0x00000001 */
+#define FMC_SDSR_RE                FMC_SDSR_RE_Msk                             /*!<Refresh error flag */
+
+#define FMC_SDSR_MODES1_Pos        (1U)
+#define FMC_SDSR_MODES1_Msk        (0x3UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000006 */
+#define FMC_SDSR_MODES1            FMC_SDSR_MODES1_Msk                         /*!<MODES1[1:0]bits (Status mode for bank 1) */
+#define FMC_SDSR_MODES1_0          (0x1UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000002 */
+#define FMC_SDSR_MODES1_1          (0x2UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000004 */
+
+#define FMC_SDSR_MODES2_Pos        (3U)
+#define FMC_SDSR_MODES2_Msk        (0x3UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000018 */
+#define FMC_SDSR_MODES2            FMC_SDSR_MODES2_Msk                         /*!<MODES2[1:0]bits (Status mode for bank 2) */
+#define FMC_SDSR_MODES2_0          (0x1UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000008 */
+#define FMC_SDSR_MODES2_1          (0x2UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000010 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            General Purpose I/O                             */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bits definition for GPIO_MODER register  *****************/
+#define GPIO_MODER_MODE0_Pos           (0U)
+#define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
+#define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000002 */
+
+#define GPIO_MODER_MODE1_Pos           (2U)
+#define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
+#define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000008 */
+
+#define GPIO_MODER_MODE2_Pos           (4U)
+#define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
+#define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000020 */
+
+#define GPIO_MODER_MODE3_Pos           (6U)
+#define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000080 */
+
+#define GPIO_MODER_MODE4_Pos           (8U)
+#define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
+#define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000200 */
+
+#define GPIO_MODER_MODE5_Pos           (10U)
+#define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000800 */
+
+#define GPIO_MODER_MODE6_Pos           (12U)
+#define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
+#define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00002000 */
+
+#define GPIO_MODER_MODE7_Pos           (14U)
+#define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00008000 */
+
+#define GPIO_MODER_MODE8_Pos           (16U)
+#define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
+#define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00020000 */
+
+#define GPIO_MODER_MODE9_Pos           (18U)
+#define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00080000 */
+
+#define GPIO_MODER_MODE10_Pos          (20U)
+#define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
+#define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00200000 */
+
+#define GPIO_MODER_MODE11_Pos          (22U)
+#define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00800000 */
+
+#define GPIO_MODER_MODE12_Pos          (24U)
+#define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
+#define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)         /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)         /*!< 0x02000000 */
+
+#define GPIO_MODER_MODE13_Pos          (26U)
+#define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)         /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)         /*!< 0x08000000 */
+
+#define GPIO_MODER_MODE14_Pos          (28U)
+#define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
+#define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)         /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)         /*!< 0x20000000 */
+
+#define GPIO_MODER_MODE15_Pos          (30U)
+#define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)         /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)         /*!< 0x80000000 */
+
+/******************  Bits definition for GPIO_OTYPER register  ****************/
+#define GPIO_OTYPER_OT0_Pos            (0U)
+#define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */
+#define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk
+#define GPIO_OTYPER_OT1_Pos            (1U)
+#define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */
+#define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk
+#define GPIO_OTYPER_OT2_Pos            (2U)
+#define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */
+#define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk
+#define GPIO_OTYPER_OT3_Pos            (3U)
+#define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */
+#define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk
+#define GPIO_OTYPER_OT4_Pos            (4U)
+#define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */
+#define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk
+#define GPIO_OTYPER_OT5_Pos            (5U)
+#define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */
+#define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk
+#define GPIO_OTYPER_OT6_Pos            (6U)
+#define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */
+#define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk
+#define GPIO_OTYPER_OT7_Pos            (7U)
+#define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */
+#define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk
+#define GPIO_OTYPER_OT8_Pos            (8U)
+#define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */
+#define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk
+#define GPIO_OTYPER_OT9_Pos            (9U)
+#define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */
+#define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk
+#define GPIO_OTYPER_OT10_Pos           (10U)
+#define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */
+#define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk
+#define GPIO_OTYPER_OT11_Pos           (11U)
+#define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */
+#define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk
+#define GPIO_OTYPER_OT12_Pos           (12U)
+#define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */
+#define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk
+#define GPIO_OTYPER_OT13_Pos           (13U)
+#define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */
+#define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk
+#define GPIO_OTYPER_OT14_Pos           (14U)
+#define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */
+#define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk
+#define GPIO_OTYPER_OT15_Pos           (15U)
+#define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */
+#define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk
+
+/******************  Bits definition for GPIO_OSPEEDR register  ***************/
+#define GPIO_OSPEEDR_OSPEED0_Pos       (0U)
+#define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */
+#define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk
+#define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000001 */
+#define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000002 */
+
+#define GPIO_OSPEEDR_OSPEED1_Pos       (2U)
+#define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */
+#define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk
+#define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000004 */
+#define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000008 */
+
+#define GPIO_OSPEEDR_OSPEED2_Pos       (4U)
+#define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */
+#define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk
+#define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000010 */
+#define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000020 */
+
+#define GPIO_OSPEEDR_OSPEED3_Pos       (6U)
+#define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */
+#define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk
+#define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000040 */
+#define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000080 */
+
+#define GPIO_OSPEEDR_OSPEED4_Pos       (8U)
+#define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */
+#define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk
+#define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000100 */
+#define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000200 */
+
+#define GPIO_OSPEEDR_OSPEED5_Pos       (10U)
+#define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */
+#define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk
+#define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000400 */
+#define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000800 */
+
+#define GPIO_OSPEEDR_OSPEED6_Pos       (12U)
+#define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */
+#define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk
+#define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00001000 */
+#define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00002000 */
+
+#define GPIO_OSPEEDR_OSPEED7_Pos       (14U)
+#define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */
+#define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk
+#define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00004000 */
+#define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00008000 */
+
+#define GPIO_OSPEEDR_OSPEED8_Pos       (16U)
+#define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */
+#define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk
+#define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00010000 */
+#define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00020000 */
+
+#define GPIO_OSPEEDR_OSPEED9_Pos       (18U)
+#define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */
+#define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk
+#define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00040000 */
+#define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00080000 */
+
+#define GPIO_OSPEEDR_OSPEED10_Pos      (20U)
+#define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */
+#define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk
+#define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00100000 */
+#define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00200000 */
+
+#define GPIO_OSPEEDR_OSPEED11_Pos      (22U)
+#define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */
+#define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk
+#define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00400000 */
+#define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00800000 */
+
+#define GPIO_OSPEEDR_OSPEED12_Pos      (24U)
+#define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */
+#define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk
+#define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x01000000 */
+#define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x02000000 */
+
+#define GPIO_OSPEEDR_OSPEED13_Pos      (26U)
+#define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */
+#define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk
+#define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x04000000 */
+#define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x08000000 */
+
+#define GPIO_OSPEEDR_OSPEED14_Pos      (28U)
+#define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */
+#define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk
+#define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x10000000 */
+#define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x20000000 */
+
+#define GPIO_OSPEEDR_OSPEED15_Pos      (30U)
+#define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */
+#define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk
+#define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x40000000 */
+#define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x80000000 */
+
+/******************  Bits definition for GPIO_PUPDR register  *****************/
+#define GPIO_PUPDR_PUPD0_Pos           (0U)
+#define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000002 */
+
+#define GPIO_PUPDR_PUPD1_Pos           (2U)
+#define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000008 */
+
+#define GPIO_PUPDR_PUPD2_Pos           (4U)
+#define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000020 */
+
+#define GPIO_PUPDR_PUPD3_Pos           (6U)
+#define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000080 */
+
+#define GPIO_PUPDR_PUPD4_Pos           (8U)
+#define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000200 */
+
+#define GPIO_PUPDR_PUPD5_Pos           (10U)
+#define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000800 */
+
+#define GPIO_PUPDR_PUPD6_Pos           (12U)
+#define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00002000 */
+
+#define GPIO_PUPDR_PUPD7_Pos           (14U)
+#define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00008000 */
+
+#define GPIO_PUPDR_PUPD8_Pos           (16U)
+#define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00020000 */
+
+#define GPIO_PUPDR_PUPD9_Pos           (18U)
+#define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00080000 */
+
+#define GPIO_PUPDR_PUPD10_Pos          (20U)
+#define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00200000 */
+
+#define GPIO_PUPDR_PUPD11_Pos          (22U)
+#define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00800000 */
+
+#define GPIO_PUPDR_PUPD12_Pos          (24U)
+#define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x02000000 */
+
+#define GPIO_PUPDR_PUPD13_Pos          (26U)
+#define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x08000000 */
+
+#define GPIO_PUPDR_PUPD14_Pos          (28U)
+#define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x20000000 */
+
+#define GPIO_PUPDR_PUPD15_Pos          (30U)
+#define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x80000000 */
+
+/******************  Bits definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_ID0_Pos               (0U)
+#define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
+#define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos               (1U)
+#define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
+#define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos               (2U)
+#define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
+#define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos               (3U)
+#define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
+#define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos               (4U)
+#define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
+#define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos               (5U)
+#define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
+#define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos               (6U)
+#define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
+#define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos               (7U)
+#define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
+#define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos               (8U)
+#define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
+#define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos               (9U)
+#define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
+#define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos              (10U)
+#define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
+#define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos              (11U)
+#define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
+#define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos              (12U)
+#define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
+#define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos              (13U)
+#define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
+#define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos              (14U)
+#define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
+#define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos              (15U)
+#define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
+#define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk
+
+/******************  Bits definition for GPIO_ODR register  *******************/
+#define GPIO_ODR_OD0_Pos               (0U)
+#define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
+#define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos               (1U)
+#define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
+#define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos               (2U)
+#define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
+#define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos               (3U)
+#define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
+#define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos               (4U)
+#define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
+#define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos               (5U)
+#define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
+#define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos               (6U)
+#define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
+#define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos               (7U)
+#define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
+#define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos               (8U)
+#define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
+#define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos               (9U)
+#define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
+#define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos              (10U)
+#define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
+#define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos              (11U)
+#define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
+#define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos              (12U)
+#define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
+#define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos              (13U)
+#define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
+#define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos              (14U)
+#define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
+#define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos              (15U)
+#define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
+#define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk
+
+/******************  Bits definition for GPIO_BSRR register  ******************/
+#define GPIO_BSRR_BS0_Pos              (0U)
+#define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */
+#define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk
+#define GPIO_BSRR_BS1_Pos              (1U)
+#define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */
+#define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk
+#define GPIO_BSRR_BS2_Pos              (2U)
+#define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */
+#define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk
+#define GPIO_BSRR_BS3_Pos              (3U)
+#define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */
+#define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk
+#define GPIO_BSRR_BS4_Pos              (4U)
+#define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */
+#define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk
+#define GPIO_BSRR_BS5_Pos              (5U)
+#define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */
+#define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk
+#define GPIO_BSRR_BS6_Pos              (6U)
+#define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */
+#define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk
+#define GPIO_BSRR_BS7_Pos              (7U)
+#define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */
+#define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk
+#define GPIO_BSRR_BS8_Pos              (8U)
+#define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */
+#define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk
+#define GPIO_BSRR_BS9_Pos              (9U)
+#define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */
+#define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk
+#define GPIO_BSRR_BS10_Pos             (10U)
+#define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */
+#define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk
+#define GPIO_BSRR_BS11_Pos             (11U)
+#define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */
+#define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk
+#define GPIO_BSRR_BS12_Pos             (12U)
+#define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */
+#define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk
+#define GPIO_BSRR_BS13_Pos             (13U)
+#define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */
+#define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk
+#define GPIO_BSRR_BS14_Pos             (14U)
+#define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */
+#define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk
+#define GPIO_BSRR_BS15_Pos             (15U)
+#define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */
+#define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk
+#define GPIO_BSRR_BR0_Pos              (16U)
+#define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */
+#define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk
+#define GPIO_BSRR_BR1_Pos              (17U)
+#define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */
+#define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk
+#define GPIO_BSRR_BR2_Pos              (18U)
+#define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */
+#define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk
+#define GPIO_BSRR_BR3_Pos              (19U)
+#define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */
+#define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk
+#define GPIO_BSRR_BR4_Pos              (20U)
+#define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */
+#define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk
+#define GPIO_BSRR_BR5_Pos              (21U)
+#define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */
+#define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk
+#define GPIO_BSRR_BR6_Pos              (22U)
+#define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */
+#define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk
+#define GPIO_BSRR_BR7_Pos              (23U)
+#define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */
+#define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk
+#define GPIO_BSRR_BR8_Pos              (24U)
+#define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */
+#define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk
+#define GPIO_BSRR_BR9_Pos              (25U)
+#define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */
+#define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk
+#define GPIO_BSRR_BR10_Pos             (26U)
+#define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */
+#define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk
+#define GPIO_BSRR_BR11_Pos             (27U)
+#define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */
+#define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk
+#define GPIO_BSRR_BR12_Pos             (28U)
+#define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */
+#define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk
+#define GPIO_BSRR_BR13_Pos             (29U)
+#define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */
+#define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk
+#define GPIO_BSRR_BR14_Pos             (30U)
+#define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */
+#define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk
+#define GPIO_BSRR_BR15_Pos             (31U)
+#define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */
+#define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0_Pos             (0U)
+#define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos             (1U)
+#define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos             (2U)
+#define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos             (3U)
+#define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos             (4U)
+#define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos             (5U)
+#define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos             (6U)
+#define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos             (7U)
+#define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos             (8U)
+#define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos             (9U)
+#define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos            (10U)
+#define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos            (11U)
+#define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos            (12U)
+#define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos            (13U)
+#define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos            (14U)
+#define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos            (15U)
+#define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos             (16U)
+#define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk
+
+/****************** Bit definition for GPIO_AFRL register  ********************/
+#define GPIO_AFRL_AFSEL0_Pos           (0U)
+#define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000001 */
+#define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000002 */
+#define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000004 */
+#define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000008 */
+#define GPIO_AFRL_AFSEL1_Pos           (4U)
+#define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000010 */
+#define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000020 */
+#define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000040 */
+#define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000080 */
+#define GPIO_AFRL_AFSEL2_Pos           (8U)
+#define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000100 */
+#define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000200 */
+#define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000400 */
+#define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000800 */
+#define GPIO_AFRL_AFSEL3_Pos           (12U)
+#define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00001000 */
+#define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00002000 */
+#define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00004000 */
+#define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00008000 */
+#define GPIO_AFRL_AFSEL4_Pos           (16U)
+#define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00010000 */
+#define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00020000 */
+#define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00040000 */
+#define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00080000 */
+#define GPIO_AFRL_AFSEL5_Pos           (20U)
+#define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00100000 */
+#define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00200000 */
+#define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00400000 */
+#define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00800000 */
+#define GPIO_AFRL_AFSEL6_Pos           (24U)
+#define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x01000000 */
+#define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x02000000 */
+#define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x04000000 */
+#define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x08000000 */
+#define GPIO_AFRL_AFSEL7_Pos           (28U)
+#define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk
+#define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x10000000 */
+#define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x20000000 */
+#define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x40000000 */
+#define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0
+#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1
+#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2
+#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3
+#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4
+#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5
+#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6
+#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7
+
+/****************** Bit definition for GPIO_AFRH register  ********************/
+#define GPIO_AFRH_AFSEL8_Pos           (0U)
+#define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000001 */
+#define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000002 */
+#define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000004 */
+#define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000008 */
+#define GPIO_AFRH_AFSEL9_Pos           (4U)
+#define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000010 */
+#define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000020 */
+#define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000040 */
+#define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000080 */
+#define GPIO_AFRH_AFSEL10_Pos          (8U)
+#define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000100 */
+#define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000200 */
+#define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000400 */
+#define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000800 */
+#define GPIO_AFRH_AFSEL11_Pos          (12U)
+#define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00001000 */
+#define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00002000 */
+#define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00004000 */
+#define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00008000 */
+#define GPIO_AFRH_AFSEL12_Pos          (16U)
+#define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00010000 */
+#define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00020000 */
+#define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00040000 */
+#define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00080000 */
+#define GPIO_AFRH_AFSEL13_Pos          (20U)
+#define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00100000 */
+#define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00200000 */
+#define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00400000 */
+#define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00800000 */
+#define GPIO_AFRH_AFSEL14_Pos          (24U)
+#define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x01000000 */
+#define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x02000000 */
+#define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x04000000 */
+#define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x08000000 */
+#define GPIO_AFRH_AFSEL15_Pos          (28U)
+#define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk
+#define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x10000000 */
+#define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x20000000 */
+#define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x40000000 */
+#define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8
+#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9
+#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10
+#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11
+#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12
+#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13
+#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14
+#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15
+
+/******************************************************************************/
+/*                                                                            */
+/*                        HSEM HW Semaphore                                   */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for HSEM_R register  ********************/
+#define HSEM_R_PROCID_Pos         (0U)
+#define HSEM_R_PROCID_Msk         (0xFFUL << HSEM_R_PROCID_Pos)                /*!< 0x000000FF */
+#define HSEM_R_PROCID             HSEM_R_PROCID_Msk                            /*!<Semaphore ProcessID */
+#define HSEM_R_COREID_Pos         (8U)
+#define HSEM_R_COREID_Msk         (0xFFUL << HSEM_R_COREID_Pos)                /*!< 0x0000FF00 */
+#define HSEM_R_COREID             HSEM_R_COREID_Msk                            /*!<Semaphore CoreID.   */
+#define HSEM_R_LOCK_Pos           (31U)
+#define HSEM_R_LOCK_Msk           (0x1UL << HSEM_R_LOCK_Pos)                   /*!< 0x80000000 */
+#define HSEM_R_LOCK               HSEM_R_LOCK_Msk                              /*!<Lock indication.    */
+
+/********************  Bit definition for HSEM_RLR register  ******************/
+#define HSEM_RLR_PROCID_Pos       (0U)
+#define HSEM_RLR_PROCID_Msk       (0xFFUL << HSEM_RLR_PROCID_Pos)              /*!< 0x000000FF */
+#define HSEM_RLR_PROCID           HSEM_RLR_PROCID_Msk                          /*!<Semaphore ProcessID */
+#define HSEM_RLR_COREID_Pos       (8U)
+#define HSEM_RLR_COREID_Msk       (0xFFUL << HSEM_RLR_COREID_Pos)              /*!< 0x0000FF00 */
+#define HSEM_RLR_COREID           HSEM_RLR_COREID_Msk                          /*!<Semaphore CoreID.   */
+#define HSEM_RLR_LOCK_Pos         (31U)
+#define HSEM_RLR_LOCK_Msk         (0x1UL << HSEM_RLR_LOCK_Pos)                 /*!< 0x80000000 */
+#define HSEM_RLR_LOCK             HSEM_RLR_LOCK_Msk                            /*!<Lock indication.    */
+
+/********************  Bit definition for HSEM_C1IER register  *****************/
+#define HSEM_C1IER_ISE0_Pos       (0U)
+#define HSEM_C1IER_ISE0_Msk       (0x1UL << HSEM_C1IER_ISE0_Pos)               /*!< 0x00000001 */
+#define HSEM_C1IER_ISE0           HSEM_C1IER_ISE0_Msk                          /*!<semaphore 0 , interrupt 0 enable bit.  */
+#define HSEM_C1IER_ISE1_Pos       (1U)
+#define HSEM_C1IER_ISE1_Msk       (0x1UL << HSEM_C1IER_ISE1_Pos)               /*!< 0x00000002 */
+#define HSEM_C1IER_ISE1           HSEM_C1IER_ISE1_Msk                          /*!<semaphore 1 , interrupt 0 enable bit.  */
+#define HSEM_C1IER_ISE2_Pos       (2U)
+#define HSEM_C1IER_ISE2_Msk       (0x1UL << HSEM_C1IER_ISE2_Pos)               /*!< 0x00000004 */
+#define HSEM_C1IER_ISE2           HSEM_C1IER_ISE2_Msk                          /*!<semaphore 2 , interrupt 0 enable bit.  */
+#define HSEM_C1IER_ISE3_Pos       (3U)
+#define HSEM_C1IER_ISE3_Msk       (0x1UL << HSEM_C1IER_ISE3_Pos)               /*!< 0x00000008 */
+#define HSEM_C1IER_ISE3           HSEM_C1IER_ISE3_Msk                          /*!<semaphore 3 , interrupt 0 enable bit.  */
+#define HSEM_C1IER_ISE4_Pos       (4U)
+#define HSEM_C1IER_ISE4_Msk       (0x1UL << HSEM_C1IER_ISE4_Pos)               /*!< 0x00000010 */
+#define HSEM_C1IER_ISE4           HSEM_C1IER_ISE4_Msk                          /*!<semaphore 4 , interrupt 0 enable bit.  */
+#define HSEM_C1IER_ISE5_Pos       (5U)
+#define HSEM_C1IER_ISE5_Msk       (0x1UL << HSEM_C1IER_ISE5_Pos)               /*!< 0x00000020 */
+#define HSEM_C1IER_ISE5           HSEM_C1IER_ISE5_Msk                          /*!<semaphore 5 interrupt 0 enable bit.    */
+#define HSEM_C1IER_ISE6_Pos       (6U)
+#define HSEM_C1IER_ISE6_Msk       (0x1UL << HSEM_C1IER_ISE6_Pos)               /*!< 0x00000040 */
+#define HSEM_C1IER_ISE6           HSEM_C1IER_ISE6_Msk                          /*!<semaphore 6 interrupt 0 enable bit.    */
+#define HSEM_C1IER_ISE7_Pos       (7U)
+#define HSEM_C1IER_ISE7_Msk       (0x1UL << HSEM_C1IER_ISE7_Pos)               /*!< 0x00000080 */
+#define HSEM_C1IER_ISE7           HSEM_C1IER_ISE7_Msk                          /*!<semaphore 7 interrupt 0 enable bit.    */
+#define HSEM_C1IER_ISE8_Pos       (8U)
+#define HSEM_C1IER_ISE8_Msk       (0x1UL << HSEM_C1IER_ISE8_Pos)               /*!< 0x00000100 */
+#define HSEM_C1IER_ISE8           HSEM_C1IER_ISE8_Msk                          /*!<semaphore 8 interrupt 0 enable bit.    */
+#define HSEM_C1IER_ISE9_Pos       (9U)
+#define HSEM_C1IER_ISE9_Msk       (0x1UL << HSEM_C1IER_ISE9_Pos)               /*!< 0x00000200 */
+#define HSEM_C1IER_ISE9           HSEM_C1IER_ISE9_Msk                          /*!<semaphore 9 interrupt 0 enable bit.    */
+#define HSEM_C1IER_ISE10_Pos      (10U)
+#define HSEM_C1IER_ISE10_Msk      (0x1UL << HSEM_C1IER_ISE10_Pos)              /*!< 0x00000400 */
+#define HSEM_C1IER_ISE10          HSEM_C1IER_ISE10_Msk                         /*!<semaphore 10 interrupt 0 enable bit.   */
+#define HSEM_C1IER_ISE11_Pos      (11U)
+#define HSEM_C1IER_ISE11_Msk      (0x1UL << HSEM_C1IER_ISE11_Pos)              /*!< 0x00000800 */
+#define HSEM_C1IER_ISE11          HSEM_C1IER_ISE11_Msk                         /*!<semaphore 11 interrupt 0 enable bit.   */
+#define HSEM_C1IER_ISE12_Pos      (12U)
+#define HSEM_C1IER_ISE12_Msk      (0x1UL << HSEM_C1IER_ISE12_Pos)              /*!< 0x00001000 */
+#define HSEM_C1IER_ISE12          HSEM_C1IER_ISE12_Msk                         /*!<semaphore 12 interrupt 0 enable bit.   */
+#define HSEM_C1IER_ISE13_Pos      (13U)
+#define HSEM_C1IER_ISE13_Msk      (0x1UL << HSEM_C1IER_ISE13_Pos)              /*!< 0x00002000 */
+#define HSEM_C1IER_ISE13          HSEM_C1IER_ISE13_Msk                         /*!<semaphore 13 interrupt 0 enable bit.   */
+#define HSEM_C1IER_ISE14_Pos      (14U)
+#define HSEM_C1IER_ISE14_Msk      (0x1UL << HSEM_C1IER_ISE14_Pos)              /*!< 0x00004000 */
+#define HSEM_C1IER_ISE14          HSEM_C1IER_ISE14_Msk                         /*!<semaphore 14 interrupt 0 enable bit.   */
+#define HSEM_C1IER_ISE15_Pos      (15U)
+#define HSEM_C1IER_ISE15_Msk      (0x1UL << HSEM_C1IER_ISE15_Pos)              /*!< 0x00008000 */
+#define HSEM_C1IER_ISE15          HSEM_C1IER_ISE15_Msk                         /*!<semaphore 15 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE16_Pos      (16U)
+#define HSEM_C1IER_ISE16_Msk      (0x1UL << HSEM_C1IER_ISE16_Pos)              /*!< 0x00010000 */
+#define HSEM_C1IER_ISE16          HSEM_C1IER_ISE16_Msk                         /*!<semaphore 16 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE17_Pos      (17U)
+#define HSEM_C1IER_ISE17_Msk      (0x1UL << HSEM_C1IER_ISE17_Pos)              /*!< 0x00020000 */
+#define HSEM_C1IER_ISE17          HSEM_C1IER_ISE17_Msk                         /*!<semaphore 17 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE18_Pos      (18U)
+#define HSEM_C1IER_ISE18_Msk      (0x1UL << HSEM_C1IER_ISE18_Pos)              /*!< 0x00040000 */
+#define HSEM_C1IER_ISE18          HSEM_C1IER_ISE18_Msk                         /*!<semaphore 18 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE19_Pos      (19U)
+#define HSEM_C1IER_ISE19_Msk      (0x1UL << HSEM_C1IER_ISE19_Pos)              /*!< 0x00080000 */
+#define HSEM_C1IER_ISE19          HSEM_C1IER_ISE19_Msk                         /*!<semaphore 19 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE20_Pos      (20U)
+#define HSEM_C1IER_ISE20_Msk      (0x1UL << HSEM_C1IER_ISE20_Pos)              /*!< 0x00100000 */
+#define HSEM_C1IER_ISE20          HSEM_C1IER_ISE20_Msk                         /*!<semaphore 20 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE21_Pos      (21U)
+#define HSEM_C1IER_ISE21_Msk      (0x1UL << HSEM_C1IER_ISE21_Pos)              /*!< 0x00200000 */
+#define HSEM_C1IER_ISE21          HSEM_C1IER_ISE21_Msk                         /*!<semaphore 21 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE22_Pos      (22U)
+#define HSEM_C1IER_ISE22_Msk      (0x1UL << HSEM_C1IER_ISE22_Pos)              /*!< 0x00400000 */
+#define HSEM_C1IER_ISE22          HSEM_C1IER_ISE22_Msk                         /*!<semaphore 22 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE23_Pos      (23U)
+#define HSEM_C1IER_ISE23_Msk      (0x1UL << HSEM_C1IER_ISE23_Pos)              /*!< 0x00800000 */
+#define HSEM_C1IER_ISE23          HSEM_C1IER_ISE23_Msk                         /*!<semaphore 23 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE24_Pos      (24U)
+#define HSEM_C1IER_ISE24_Msk      (0x1UL << HSEM_C1IER_ISE24_Pos)              /*!< 0x01000000 */
+#define HSEM_C1IER_ISE24          HSEM_C1IER_ISE24_Msk                         /*!<semaphore 24 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE25_Pos      (25U)
+#define HSEM_C1IER_ISE25_Msk      (0x1UL << HSEM_C1IER_ISE25_Pos)              /*!< 0x02000000 */
+#define HSEM_C1IER_ISE25          HSEM_C1IER_ISE25_Msk                         /*!<semaphore 25 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE26_Pos      (26U)
+#define HSEM_C1IER_ISE26_Msk      (0x1UL << HSEM_C1IER_ISE26_Pos)              /*!< 0x04000000 */
+#define HSEM_C1IER_ISE26          HSEM_C1IER_ISE26_Msk                         /*!<semaphore 26 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE27_Pos      (27U)
+#define HSEM_C1IER_ISE27_Msk      (0x1UL << HSEM_C1IER_ISE27_Pos)              /*!< 0x08000000 */
+#define HSEM_C1IER_ISE27          HSEM_C1IER_ISE27_Msk                         /*!<semaphore 27 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE28_Pos      (28U)
+#define HSEM_C1IER_ISE28_Msk      (0x1UL << HSEM_C1IER_ISE28_Pos)              /*!< 0x10000000 */
+#define HSEM_C1IER_ISE28          HSEM_C1IER_ISE28_Msk                         /*!<semaphore 28 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE29_Pos      (29U)
+#define HSEM_C1IER_ISE29_Msk      (0x1UL << HSEM_C1IER_ISE29_Pos)              /*!< 0x20000000 */
+#define HSEM_C1IER_ISE29          HSEM_C1IER_ISE29_Msk                         /*!<semaphore 29 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE30_Pos      (30U)
+#define HSEM_C1IER_ISE30_Msk      (0x1UL << HSEM_C1IER_ISE30_Pos)              /*!< 0x40000000 */
+#define HSEM_C1IER_ISE30          HSEM_C1IER_ISE30_Msk                         /*!<semaphore 30 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE31_Pos      (31U)
+#define HSEM_C1IER_ISE31_Msk      (0x1UL << HSEM_C1IER_ISE31_Pos)              /*!< 0x80000000 */
+#define HSEM_C1IER_ISE31          HSEM_C1IER_ISE31_Msk                         /*!<semaphore 31 interrupt 0 enable bit. */
+
+/********************  Bit definition for HSEM_C1ICR register  *****************/
+#define HSEM_C1ICR_ISC0_Pos       (0U)
+#define HSEM_C1ICR_ISC0_Msk       (0x1UL << HSEM_C1ICR_ISC0_Pos)               /*!< 0x00000001 */
+#define HSEM_C1ICR_ISC0           HSEM_C1ICR_ISC0_Msk                          /*!<semaphore 0 , interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC1_Pos       (1U)
+#define HSEM_C1ICR_ISC1_Msk       (0x1UL << HSEM_C1ICR_ISC1_Pos)               /*!< 0x00000002 */
+#define HSEM_C1ICR_ISC1           HSEM_C1ICR_ISC1_Msk                          /*!<semaphore 1 , interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC2_Pos       (2U)
+#define HSEM_C1ICR_ISC2_Msk       (0x1UL << HSEM_C1ICR_ISC2_Pos)               /*!< 0x00000004 */
+#define HSEM_C1ICR_ISC2           HSEM_C1ICR_ISC2_Msk                          /*!<semaphore 2 , interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC3_Pos       (3U)
+#define HSEM_C1ICR_ISC3_Msk       (0x1UL << HSEM_C1ICR_ISC3_Pos)               /*!< 0x00000008 */
+#define HSEM_C1ICR_ISC3           HSEM_C1ICR_ISC3_Msk                          /*!<semaphore 3 , interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC4_Pos       (4U)
+#define HSEM_C1ICR_ISC4_Msk       (0x1UL << HSEM_C1ICR_ISC4_Pos)               /*!< 0x00000010 */
+#define HSEM_C1ICR_ISC4           HSEM_C1ICR_ISC4_Msk                          /*!<semaphore 4 , interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC5_Pos       (5U)
+#define HSEM_C1ICR_ISC5_Msk       (0x1UL << HSEM_C1ICR_ISC5_Pos)               /*!< 0x00000020 */
+#define HSEM_C1ICR_ISC5           HSEM_C1ICR_ISC5_Msk                          /*!<semaphore 5 interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC6_Pos       (6U)
+#define HSEM_C1ICR_ISC6_Msk       (0x1UL << HSEM_C1ICR_ISC6_Pos)               /*!< 0x00000040 */
+#define HSEM_C1ICR_ISC6           HSEM_C1ICR_ISC6_Msk                          /*!<semaphore 6 interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC7_Pos       (7U)
+#define HSEM_C1ICR_ISC7_Msk       (0x1UL << HSEM_C1ICR_ISC7_Pos)               /*!< 0x00000080 */
+#define HSEM_C1ICR_ISC7           HSEM_C1ICR_ISC7_Msk                          /*!<semaphore 7 interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC8_Pos       (8U)
+#define HSEM_C1ICR_ISC8_Msk       (0x1UL << HSEM_C1ICR_ISC8_Pos)               /*!< 0x00000100 */
+#define HSEM_C1ICR_ISC8           HSEM_C1ICR_ISC8_Msk                          /*!<semaphore 8 interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC9_Pos       (9U)
+#define HSEM_C1ICR_ISC9_Msk       (0x1UL << HSEM_C1ICR_ISC9_Pos)               /*!< 0x00000200 */
+#define HSEM_C1ICR_ISC9           HSEM_C1ICR_ISC9_Msk                          /*!<semaphore 9 interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC10_Pos      (10U)
+#define HSEM_C1ICR_ISC10_Msk      (0x1UL << HSEM_C1ICR_ISC10_Pos)              /*!< 0x00000400 */
+#define HSEM_C1ICR_ISC10          HSEM_C1ICR_ISC10_Msk                         /*!<semaphore 10 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC11_Pos      (11U)
+#define HSEM_C1ICR_ISC11_Msk      (0x1UL << HSEM_C1ICR_ISC11_Pos)              /*!< 0x00000800 */
+#define HSEM_C1ICR_ISC11          HSEM_C1ICR_ISC11_Msk                         /*!<semaphore 11 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC12_Pos      (12U)
+#define HSEM_C1ICR_ISC12_Msk      (0x1UL << HSEM_C1ICR_ISC12_Pos)              /*!< 0x00001000 */
+#define HSEM_C1ICR_ISC12          HSEM_C1ICR_ISC12_Msk                         /*!<semaphore 12 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC13_Pos      (13U)
+#define HSEM_C1ICR_ISC13_Msk      (0x1UL << HSEM_C1ICR_ISC13_Pos)              /*!< 0x00002000 */
+#define HSEM_C1ICR_ISC13          HSEM_C1ICR_ISC13_Msk                         /*!<semaphore 13 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC14_Pos      (14U)
+#define HSEM_C1ICR_ISC14_Msk      (0x1UL << HSEM_C1ICR_ISC14_Pos)              /*!< 0x00004000 */
+#define HSEM_C1ICR_ISC14          HSEM_C1ICR_ISC14_Msk                         /*!<semaphore 14 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC15_Pos      (15U)
+#define HSEM_C1ICR_ISC15_Msk      (0x1UL << HSEM_C1ICR_ISC15_Pos)              /*!< 0x00008000 */
+#define HSEM_C1ICR_ISC15          HSEM_C1ICR_ISC15_Msk                         /*!<semaphore 15 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC16_Pos      (16U)
+#define HSEM_C1ICR_ISC16_Msk      (0x1UL << HSEM_C1ICR_ISC16_Pos)              /*!< 0x00010000 */
+#define HSEM_C1ICR_ISC16          HSEM_C1ICR_ISC16_Msk                         /*!<semaphore 16 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC17_Pos      (17U)
+#define HSEM_C1ICR_ISC17_Msk      (0x1UL << HSEM_C1ICR_ISC17_Pos)              /*!< 0x00020000 */
+#define HSEM_C1ICR_ISC17          HSEM_C1ICR_ISC17_Msk                         /*!<semaphore 17 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC18_Pos      (18U)
+#define HSEM_C1ICR_ISC18_Msk      (0x1UL << HSEM_C1ICR_ISC18_Pos)              /*!< 0x00040000 */
+#define HSEM_C1ICR_ISC18          HSEM_C1ICR_ISC18_Msk                         /*!<semaphore 18 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC19_Pos      (19U)
+#define HSEM_C1ICR_ISC19_Msk      (0x1UL << HSEM_C1ICR_ISC19_Pos)              /*!< 0x00080000 */
+#define HSEM_C1ICR_ISC19          HSEM_C1ICR_ISC19_Msk                         /*!<semaphore 19 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC20_Pos      (20U)
+#define HSEM_C1ICR_ISC20_Msk      (0x1UL << HSEM_C1ICR_ISC20_Pos)              /*!< 0x00100000 */
+#define HSEM_C1ICR_ISC20          HSEM_C1ICR_ISC20_Msk                         /*!<semaphore 20 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC21_Pos      (21U)
+#define HSEM_C1ICR_ISC21_Msk      (0x1UL << HSEM_C1ICR_ISC21_Pos)              /*!< 0x00200000 */
+#define HSEM_C1ICR_ISC21          HSEM_C1ICR_ISC21_Msk                         /*!<semaphore 21 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC22_Pos      (22U)
+#define HSEM_C1ICR_ISC22_Msk      (0x1UL << HSEM_C1ICR_ISC22_Pos)              /*!< 0x00400000 */
+#define HSEM_C1ICR_ISC22          HSEM_C1ICR_ISC22_Msk                         /*!<semaphore 22 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC23_Pos      (23U)
+#define HSEM_C1ICR_ISC23_Msk      (0x1UL << HSEM_C1ICR_ISC23_Pos)              /*!< 0x00800000 */
+#define HSEM_C1ICR_ISC23          HSEM_C1ICR_ISC23_Msk                         /*!<semaphore 23 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC24_Pos      (24U)
+#define HSEM_C1ICR_ISC24_Msk      (0x1UL << HSEM_C1ICR_ISC24_Pos)              /*!< 0x01000000 */
+#define HSEM_C1ICR_ISC24          HSEM_C1ICR_ISC24_Msk                         /*!<semaphore 24 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC25_Pos      (25U)
+#define HSEM_C1ICR_ISC25_Msk      (0x1UL << HSEM_C1ICR_ISC25_Pos)              /*!< 0x02000000 */
+#define HSEM_C1ICR_ISC25          HSEM_C1ICR_ISC25_Msk                         /*!<semaphore 25 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC26_Pos      (26U)
+#define HSEM_C1ICR_ISC26_Msk      (0x1UL << HSEM_C1ICR_ISC26_Pos)              /*!< 0x04000000 */
+#define HSEM_C1ICR_ISC26          HSEM_C1ICR_ISC26_Msk                         /*!<semaphore 26 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC27_Pos      (27U)
+#define HSEM_C1ICR_ISC27_Msk      (0x1UL << HSEM_C1ICR_ISC27_Pos)              /*!< 0x08000000 */
+#define HSEM_C1ICR_ISC27          HSEM_C1ICR_ISC27_Msk                         /*!<semaphore 27 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC28_Pos      (28U)
+#define HSEM_C1ICR_ISC28_Msk      (0x1UL << HSEM_C1ICR_ISC28_Pos)              /*!< 0x10000000 */
+#define HSEM_C1ICR_ISC28          HSEM_C1ICR_ISC28_Msk                         /*!<semaphore 28 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC29_Pos      (29U)
+#define HSEM_C1ICR_ISC29_Msk      (0x1UL << HSEM_C1ICR_ISC29_Pos)              /*!< 0x20000000 */
+#define HSEM_C1ICR_ISC29          HSEM_C1ICR_ISC29_Msk                         /*!<semaphore 29 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC30_Pos      (30U)
+#define HSEM_C1ICR_ISC30_Msk      (0x1UL << HSEM_C1ICR_ISC30_Pos)              /*!< 0x40000000 */
+#define HSEM_C1ICR_ISC30          HSEM_C1ICR_ISC30_Msk                         /*!<semaphore 30 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC31_Pos      (31U)
+#define HSEM_C1ICR_ISC31_Msk      (0x1UL << HSEM_C1ICR_ISC31_Pos)              /*!< 0x80000000 */
+#define HSEM_C1ICR_ISC31          HSEM_C1ICR_ISC31_Msk                         /*!<semaphore 31 interrupt 0 clear bit. */
+
+/********************  Bit definition for HSEM_C1ISR register  *****************/
+#define HSEM_C1ISR_ISF0_Pos       (0U)
+#define HSEM_C1ISR_ISF0_Msk       (0x1UL << HSEM_C1ISR_ISF0_Pos)               /*!< 0x00000001 */
+#define HSEM_C1ISR_ISF0           HSEM_C1ISR_ISF0_Msk                          /*!<semaphore 0 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF1_Pos       (1U)
+#define HSEM_C1ISR_ISF1_Msk       (0x1UL << HSEM_C1ISR_ISF1_Pos)               /*!< 0x00000002 */
+#define HSEM_C1ISR_ISF1           HSEM_C1ISR_ISF1_Msk                          /*!<semaphore 1 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF2_Pos       (2U)
+#define HSEM_C1ISR_ISF2_Msk       (0x1UL << HSEM_C1ISR_ISF2_Pos)               /*!< 0x00000004 */
+#define HSEM_C1ISR_ISF2           HSEM_C1ISR_ISF2_Msk                          /*!<semaphore 2 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF3_Pos       (3U)
+#define HSEM_C1ISR_ISF3_Msk       (0x1UL << HSEM_C1ISR_ISF3_Pos)               /*!< 0x00000008 */
+#define HSEM_C1ISR_ISF3           HSEM_C1ISR_ISF3_Msk                          /*!<semaphore 3 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF4_Pos       (4U)
+#define HSEM_C1ISR_ISF4_Msk       (0x1UL << HSEM_C1ISR_ISF4_Pos)               /*!< 0x00000010 */
+#define HSEM_C1ISR_ISF4           HSEM_C1ISR_ISF4_Msk                          /*!<semaphore 4 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF5_Pos       (5U)
+#define HSEM_C1ISR_ISF5_Msk       (0x1UL << HSEM_C1ISR_ISF5_Pos)               /*!< 0x00000020 */
+#define HSEM_C1ISR_ISF5           HSEM_C1ISR_ISF5_Msk                          /*!<semaphore 5 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF6_Pos       (6U)
+#define HSEM_C1ISR_ISF6_Msk       (0x1UL << HSEM_C1ISR_ISF6_Pos)               /*!< 0x00000040 */
+#define HSEM_C1ISR_ISF6           HSEM_C1ISR_ISF6_Msk                          /*!<semaphore 6 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF7_Pos       (7U)
+#define HSEM_C1ISR_ISF7_Msk       (0x1UL << HSEM_C1ISR_ISF7_Pos)               /*!< 0x00000080 */
+#define HSEM_C1ISR_ISF7           HSEM_C1ISR_ISF7_Msk                          /*!<semaphore 7 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF8_Pos       (8U)
+#define HSEM_C1ISR_ISF8_Msk       (0x1UL << HSEM_C1ISR_ISF8_Pos)               /*!< 0x00000100 */
+#define HSEM_C1ISR_ISF8           HSEM_C1ISR_ISF8_Msk                          /*!<semaphore 8 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF9_Pos       (9U)
+#define HSEM_C1ISR_ISF9_Msk       (0x1UL << HSEM_C1ISR_ISF9_Pos)               /*!< 0x00000200 */
+#define HSEM_C1ISR_ISF9           HSEM_C1ISR_ISF9_Msk                          /*!<semaphore 9 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF10_Pos      (10U)
+#define HSEM_C1ISR_ISF10_Msk      (0x1UL << HSEM_C1ISR_ISF10_Pos)              /*!< 0x00000400 */
+#define HSEM_C1ISR_ISF10          HSEM_C1ISR_ISF10_Msk                         /*!<semaphore 10 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF11_Pos      (11U)
+#define HSEM_C1ISR_ISF11_Msk      (0x1UL << HSEM_C1ISR_ISF11_Pos)              /*!< 0x00000800 */
+#define HSEM_C1ISR_ISF11          HSEM_C1ISR_ISF11_Msk                         /*!<semaphore 11 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF12_Pos      (12U)
+#define HSEM_C1ISR_ISF12_Msk      (0x1UL << HSEM_C1ISR_ISF12_Pos)              /*!< 0x00001000 */
+#define HSEM_C1ISR_ISF12          HSEM_C1ISR_ISF12_Msk                         /*!<semaphore 12 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF13_Pos      (13U)
+#define HSEM_C1ISR_ISF13_Msk      (0x1UL << HSEM_C1ISR_ISF13_Pos)              /*!< 0x00002000 */
+#define HSEM_C1ISR_ISF13          HSEM_C1ISR_ISF13_Msk                         /*!<semaphore 13 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF14_Pos      (14U)
+#define HSEM_C1ISR_ISF14_Msk      (0x1UL << HSEM_C1ISR_ISF14_Pos)              /*!< 0x00004000 */
+#define HSEM_C1ISR_ISF14          HSEM_C1ISR_ISF14_Msk                         /*!<semaphore 14 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF15_Pos      (15U)
+#define HSEM_C1ISR_ISF15_Msk      (0x1UL << HSEM_C1ISR_ISF15_Pos)              /*!< 0x00008000 */
+#define HSEM_C1ISR_ISF15          HSEM_C1ISR_ISF15_Msk                         /*!<semaphore 15 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF16_Pos      (16U)
+#define HSEM_C1ISR_ISF16_Msk      (0x1UL << HSEM_C1ISR_ISF16_Pos)              /*!< 0x00010000 */
+#define HSEM_C1ISR_ISF16          HSEM_C1ISR_ISF16_Msk                         /*!<semaphore 16 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF17_Pos      (17U)
+#define HSEM_C1ISR_ISF17_Msk      (0x1UL << HSEM_C1ISR_ISF17_Pos)              /*!< 0x00020000 */
+#define HSEM_C1ISR_ISF17          HSEM_C1ISR_ISF17_Msk                         /*!<semaphore 17 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF18_Pos      (18U)
+#define HSEM_C1ISR_ISF18_Msk      (0x1UL << HSEM_C1ISR_ISF18_Pos)              /*!< 0x00040000 */
+#define HSEM_C1ISR_ISF18          HSEM_C1ISR_ISF18_Msk                         /*!<semaphore 18 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF19_Pos      (19U)
+#define HSEM_C1ISR_ISF19_Msk      (0x1UL << HSEM_C1ISR_ISF19_Pos)              /*!< 0x00080000 */
+#define HSEM_C1ISR_ISF19          HSEM_C1ISR_ISF19_Msk                         /*!<semaphore 19 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF20_Pos      (20U)
+#define HSEM_C1ISR_ISF20_Msk      (0x1UL << HSEM_C1ISR_ISF20_Pos)              /*!< 0x00100000 */
+#define HSEM_C1ISR_ISF20          HSEM_C1ISR_ISF20_Msk                         /*!<semaphore 20 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF21_Pos      (21U)
+#define HSEM_C1ISR_ISF21_Msk      (0x1UL << HSEM_C1ISR_ISF21_Pos)              /*!< 0x00200000 */
+#define HSEM_C1ISR_ISF21          HSEM_C1ISR_ISF21_Msk                         /*!<semaphore 21 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF22_Pos      (22U)
+#define HSEM_C1ISR_ISF22_Msk      (0x1UL << HSEM_C1ISR_ISF22_Pos)              /*!< 0x00400000 */
+#define HSEM_C1ISR_ISF22          HSEM_C1ISR_ISF22_Msk                         /*!<semaphore 22 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF23_Pos      (23U)
+#define HSEM_C1ISR_ISF23_Msk      (0x1UL << HSEM_C1ISR_ISF23_Pos)              /*!< 0x00800000 */
+#define HSEM_C1ISR_ISF23          HSEM_C1ISR_ISF23_Msk                         /*!<semaphore 23 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF24_Pos      (24U)
+#define HSEM_C1ISR_ISF24_Msk      (0x1UL << HSEM_C1ISR_ISF24_Pos)              /*!< 0x01000000 */
+#define HSEM_C1ISR_ISF24          HSEM_C1ISR_ISF24_Msk                         /*!<semaphore 24 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF25_Pos      (25U)
+#define HSEM_C1ISR_ISF25_Msk      (0x1UL << HSEM_C1ISR_ISF25_Pos)              /*!< 0x02000000 */
+#define HSEM_C1ISR_ISF25          HSEM_C1ISR_ISF25_Msk                         /*!<semaphore 25 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF26_Pos      (26U)
+#define HSEM_C1ISR_ISF26_Msk      (0x1UL << HSEM_C1ISR_ISF26_Pos)              /*!< 0x04000000 */
+#define HSEM_C1ISR_ISF26          HSEM_C1ISR_ISF26_Msk                         /*!<semaphore 26 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF27_Pos      (27U)
+#define HSEM_C1ISR_ISF27_Msk      (0x1UL << HSEM_C1ISR_ISF27_Pos)              /*!< 0x08000000 */
+#define HSEM_C1ISR_ISF27          HSEM_C1ISR_ISF27_Msk                         /*!<semaphore 27 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF28_Pos      (28U)
+#define HSEM_C1ISR_ISF28_Msk      (0x1UL << HSEM_C1ISR_ISF28_Pos)              /*!< 0x10000000 */
+#define HSEM_C1ISR_ISF28          HSEM_C1ISR_ISF28_Msk                         /*!<semaphore 28 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF29_Pos      (29U)
+#define HSEM_C1ISR_ISF29_Msk      (0x1UL << HSEM_C1ISR_ISF29_Pos)              /*!< 0x20000000 */
+#define HSEM_C1ISR_ISF29          HSEM_C1ISR_ISF29_Msk                         /*!<semaphore 29 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF30_Pos      (30U)
+#define HSEM_C1ISR_ISF30_Msk      (0x1UL << HSEM_C1ISR_ISF30_Pos)              /*!< 0x40000000 */
+#define HSEM_C1ISR_ISF30          HSEM_C1ISR_ISF30_Msk                         /*!<semaphore 30 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF31_Pos      (31U)
+#define HSEM_C1ISR_ISF31_Msk      (0x1UL << HSEM_C1ISR_ISF31_Pos)              /*!< 0x80000000 */
+#define HSEM_C1ISR_ISF31          HSEM_C1ISR_ISF31_Msk                         /*!<semaphore 31 interrupt 0 status bit. */
+
+/********************  Bit definition for HSEM_C1MISR register  *****************/
+#define HSEM_C1MISR_MISF0_Pos     (0U)
+#define HSEM_C1MISR_MISF0_Msk     (0x1UL << HSEM_C1MISR_MISF0_Pos)             /*!< 0x00000001 */
+#define HSEM_C1MISR_MISF0         HSEM_C1MISR_MISF0_Msk                        /*!<semaphore 0 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF1_Pos     (1U)
+#define HSEM_C1MISR_MISF1_Msk     (0x1UL << HSEM_C1MISR_MISF1_Pos)             /*!< 0x00000002 */
+#define HSEM_C1MISR_MISF1         HSEM_C1MISR_MISF1_Msk                        /*!<semaphore 1 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF2_Pos     (2U)
+#define HSEM_C1MISR_MISF2_Msk     (0x1UL << HSEM_C1MISR_MISF2_Pos)             /*!< 0x00000004 */
+#define HSEM_C1MISR_MISF2         HSEM_C1MISR_MISF2_Msk                        /*!<semaphore 2 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF3_Pos     (3U)
+#define HSEM_C1MISR_MISF3_Msk     (0x1UL << HSEM_C1MISR_MISF3_Pos)             /*!< 0x00000008 */
+#define HSEM_C1MISR_MISF3         HSEM_C1MISR_MISF3_Msk                        /*!<semaphore 3 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF4_Pos     (4U)
+#define HSEM_C1MISR_MISF4_Msk     (0x1UL << HSEM_C1MISR_MISF4_Pos)             /*!< 0x00000010 */
+#define HSEM_C1MISR_MISF4         HSEM_C1MISR_MISF4_Msk                        /*!<semaphore 4 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF5_Pos     (5U)
+#define HSEM_C1MISR_MISF5_Msk     (0x1UL << HSEM_C1MISR_MISF5_Pos)             /*!< 0x00000020 */
+#define HSEM_C1MISR_MISF5         HSEM_C1MISR_MISF5_Msk                        /*!<semaphore 5 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF6_Pos     (6U)
+#define HSEM_C1MISR_MISF6_Msk     (0x1UL << HSEM_C1MISR_MISF6_Pos)             /*!< 0x00000040 */
+#define HSEM_C1MISR_MISF6         HSEM_C1MISR_MISF6_Msk                        /*!<semaphore 6 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF7_Pos     (7U)
+#define HSEM_C1MISR_MISF7_Msk     (0x1UL << HSEM_C1MISR_MISF7_Pos)             /*!< 0x00000080 */
+#define HSEM_C1MISR_MISF7         HSEM_C1MISR_MISF7_Msk                        /*!<semaphore 7 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF8_Pos     (8U)
+#define HSEM_C1MISR_MISF8_Msk     (0x1UL << HSEM_C1MISR_MISF8_Pos)             /*!< 0x00000100 */
+#define HSEM_C1MISR_MISF8         HSEM_C1MISR_MISF8_Msk                        /*!<semaphore 8 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF9_Pos     (9U)
+#define HSEM_C1MISR_MISF9_Msk     (0x1UL << HSEM_C1MISR_MISF9_Pos)             /*!< 0x00000200 */
+#define HSEM_C1MISR_MISF9         HSEM_C1MISR_MISF9_Msk                        /*!<semaphore 9 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF10_Pos    (10U)
+#define HSEM_C1MISR_MISF10_Msk    (0x1UL << HSEM_C1MISR_MISF10_Pos)            /*!< 0x00000400 */
+#define HSEM_C1MISR_MISF10        HSEM_C1MISR_MISF10_Msk                       /*!<semaphore 10 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF11_Pos    (11U)
+#define HSEM_C1MISR_MISF11_Msk    (0x1UL << HSEM_C1MISR_MISF11_Pos)            /*!< 0x00000800 */
+#define HSEM_C1MISR_MISF11        HSEM_C1MISR_MISF11_Msk                       /*!<semaphore 11 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF12_Pos    (12U)
+#define HSEM_C1MISR_MISF12_Msk    (0x1UL << HSEM_C1MISR_MISF12_Pos)            /*!< 0x00001000 */
+#define HSEM_C1MISR_MISF12        HSEM_C1MISR_MISF12_Msk                       /*!<semaphore 12 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF13_Pos    (13U)
+#define HSEM_C1MISR_MISF13_Msk    (0x1UL << HSEM_C1MISR_MISF13_Pos)            /*!< 0x00002000 */
+#define HSEM_C1MISR_MISF13        HSEM_C1MISR_MISF13_Msk                       /*!<semaphore 13 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF14_Pos    (14U)
+#define HSEM_C1MISR_MISF14_Msk    (0x1UL << HSEM_C1MISR_MISF14_Pos)            /*!< 0x00004000 */
+#define HSEM_C1MISR_MISF14        HSEM_C1MISR_MISF14_Msk                       /*!<semaphore 14 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF15_Pos    (15U)
+#define HSEM_C1MISR_MISF15_Msk    (0x1UL << HSEM_C1MISR_MISF15_Pos)            /*!< 0x00008000 */
+#define HSEM_C1MISR_MISF15        HSEM_C1MISR_MISF15_Msk                       /*!<semaphore 15 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF16_Pos    (16U)
+#define HSEM_C1MISR_MISF16_Msk    (0x1UL << HSEM_C1MISR_MISF16_Pos)            /*!< 0x00010000 */
+#define HSEM_C1MISR_MISF16        HSEM_C1MISR_MISF16_Msk                       /*!<semaphore 16 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF17_Pos    (17U)
+#define HSEM_C1MISR_MISF17_Msk    (0x1UL << HSEM_C1MISR_MISF17_Pos)            /*!< 0x00020000 */
+#define HSEM_C1MISR_MISF17        HSEM_C1MISR_MISF17_Msk                       /*!<semaphore 17 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF18_Pos    (18U)
+#define HSEM_C1MISR_MISF18_Msk    (0x1UL << HSEM_C1MISR_MISF18_Pos)            /*!< 0x00040000 */
+#define HSEM_C1MISR_MISF18        HSEM_C1MISR_MISF18_Msk                       /*!<semaphore 18 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF19_Pos    (19U)
+#define HSEM_C1MISR_MISF19_Msk    (0x1UL << HSEM_C1MISR_MISF19_Pos)            /*!< 0x00080000 */
+#define HSEM_C1MISR_MISF19        HSEM_C1MISR_MISF19_Msk                       /*!<semaphore 19 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF20_Pos    (20U)
+#define HSEM_C1MISR_MISF20_Msk    (0x1UL << HSEM_C1MISR_MISF20_Pos)            /*!< 0x00100000 */
+#define HSEM_C1MISR_MISF20        HSEM_C1MISR_MISF20_Msk                       /*!<semaphore 20 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF21_Pos    (21U)
+#define HSEM_C1MISR_MISF21_Msk    (0x1UL << HSEM_C1MISR_MISF21_Pos)            /*!< 0x00200000 */
+#define HSEM_C1MISR_MISF21        HSEM_C1MISR_MISF21_Msk                       /*!<semaphore 21 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF22_Pos    (22U)
+#define HSEM_C1MISR_MISF22_Msk    (0x1UL << HSEM_C1MISR_MISF22_Pos)            /*!< 0x00400000 */
+#define HSEM_C1MISR_MISF22        HSEM_C1MISR_MISF22_Msk                       /*!<semaphore 22 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF23_Pos    (23U)
+#define HSEM_C1MISR_MISF23_Msk    (0x1UL << HSEM_C1MISR_MISF23_Pos)            /*!< 0x00800000 */
+#define HSEM_C1MISR_MISF23        HSEM_C1MISR_MISF23_Msk                       /*!<semaphore 23 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF24_Pos    (24U)
+#define HSEM_C1MISR_MISF24_Msk    (0x1UL << HSEM_C1MISR_MISF24_Pos)            /*!< 0x01000000 */
+#define HSEM_C1MISR_MISF24        HSEM_C1MISR_MISF24_Msk                       /*!<semaphore 24 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF25_Pos    (25U)
+#define HSEM_C1MISR_MISF25_Msk    (0x1UL << HSEM_C1MISR_MISF25_Pos)            /*!< 0x02000000 */
+#define HSEM_C1MISR_MISF25        HSEM_C1MISR_MISF25_Msk                       /*!<semaphore 25 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF26_Pos    (26U)
+#define HSEM_C1MISR_MISF26_Msk    (0x1UL << HSEM_C1MISR_MISF26_Pos)            /*!< 0x04000000 */
+#define HSEM_C1MISR_MISF26        HSEM_C1MISR_MISF26_Msk                       /*!<semaphore 26 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF27_Pos    (27U)
+#define HSEM_C1MISR_MISF27_Msk    (0x1UL << HSEM_C1MISR_MISF27_Pos)            /*!< 0x08000000 */
+#define HSEM_C1MISR_MISF27        HSEM_C1MISR_MISF27_Msk                       /*!<semaphore 27 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF28_Pos    (28U)
+#define HSEM_C1MISR_MISF28_Msk    (0x1UL << HSEM_C1MISR_MISF28_Pos)            /*!< 0x10000000 */
+#define HSEM_C1MISR_MISF28        HSEM_C1MISR_MISF28_Msk                       /*!<semaphore 28 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF29_Pos    (29U)
+#define HSEM_C1MISR_MISF29_Msk    (0x1UL << HSEM_C1MISR_MISF29_Pos)            /*!< 0x20000000 */
+#define HSEM_C1MISR_MISF29        HSEM_C1MISR_MISF29_Msk                       /*!<semaphore 29 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF30_Pos    (30U)
+#define HSEM_C1MISR_MISF30_Msk    (0x1UL << HSEM_C1MISR_MISF30_Pos)            /*!< 0x40000000 */
+#define HSEM_C1MISR_MISF30        HSEM_C1MISR_MISF30_Msk                       /*!<semaphore 30 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF31_Pos    (31U)
+#define HSEM_C1MISR_MISF31_Msk    (0x1UL << HSEM_C1MISR_MISF31_Pos)            /*!< 0x80000000 */
+#define HSEM_C1MISR_MISF31        HSEM_C1MISR_MISF31_Msk                       /*!<semaphore 31 interrupt 0 masked status bit. */
+
+/********************  Bit definition for HSEM_CR register  *****************/
+#define HSEM_CR_COREID_Pos        (8U)
+#define HSEM_CR_COREID_Msk        (0xFFUL << HSEM_CR_COREID_Pos)               /*!< 0x0000FF00 */
+#define HSEM_CR_COREID            HSEM_CR_COREID_Msk                           /*!<CoreID of semaphores to be cleared. */
+#define HSEM_CR_KEY_Pos           (16U)
+#define HSEM_CR_KEY_Msk           (0xFFFFUL << HSEM_CR_KEY_Pos)                /*!< 0xFFFF0000 */
+#define HSEM_CR_KEY               HSEM_CR_KEY_Msk                              /*!<semaphores clear key. */
+
+/********************  Bit definition for HSEM_KEYR register  *****************/
+#define HSEM_KEYR_KEY_Pos         (16U)
+#define HSEM_KEYR_KEY_Msk         (0xFFFFUL << HSEM_KEYR_KEY_Pos)              /*!< 0xFFFF0000 */
+#define HSEM_KEYR_KEY             HSEM_KEYR_KEY_Msk                            /*!<semaphores clear key. */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Inter-integrated Circuit Interface (I2C)              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for I2C_CR1 register  *******************/
+#define I2C_CR1_PE_Pos               (0U)
+#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                 /*!< 0x00000001 */
+#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */
+#define I2C_CR1_TXIE_Pos             (1U)
+#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)               /*!< 0x00000002 */
+#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */
+#define I2C_CR1_RXIE_Pos             (2U)
+#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)               /*!< 0x00000004 */
+#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE_Pos           (3U)
+#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)             /*!< 0x00000008 */
+#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE_Pos           (4U)
+#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)             /*!< 0x00000010 */
+#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE_Pos           (5U)
+#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)             /*!< 0x00000020 */
+#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE_Pos             (6U)
+#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)               /*!< 0x00000040 */
+#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE_Pos            (7U)
+#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)              /*!< 0x00000080 */
+#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */
+#define I2C_CR1_DNF_Pos              (8U)
+#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                /*!< 0x00000F00 */
+#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF_Pos           (12U)
+#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)             /*!< 0x00001000 */
+#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */
+#define I2C_CR1_TXDMAEN_Pos          (14U)
+#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)            /*!< 0x00004000 */
+#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN_Pos          (15U)
+#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)            /*!< 0x00008000 */
+#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */
+#define I2C_CR1_SBC_Pos              (16U)
+#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                /*!< 0x00010000 */
+#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH_Pos        (17U)
+#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)          /*!< 0x00020000 */
+#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN_Pos            (18U)
+#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)              /*!< 0x00040000 */
+#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN_Pos             (19U)
+#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)               /*!< 0x00080000 */
+#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */
+#define I2C_CR1_SMBHEN_Pos           (20U)
+#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)             /*!< 0x00100000 */
+#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN_Pos           (21U)
+#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)             /*!< 0x00200000 */
+#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN_Pos          (22U)
+#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)            /*!< 0x00400000 */
+#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */
+#define I2C_CR1_PECEN_Pos            (23U)
+#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)              /*!< 0x00800000 */
+#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */
+
+/******************  Bit definition for I2C_CR2 register  ********************/
+#define I2C_CR2_SADD_Pos             (0U)
+#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)             /*!< 0x000003FF */
+#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN_Pos           (10U)
+#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)             /*!< 0x00000400 */
+#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10_Pos            (11U)
+#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)              /*!< 0x00000800 */
+#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R_Pos          (12U)
+#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)            /*!< 0x00001000 */
+#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START_Pos            (13U)
+#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)              /*!< 0x00002000 */
+#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */
+#define I2C_CR2_STOP_Pos             (14U)
+#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)               /*!< 0x00004000 */
+#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK_Pos             (15U)
+#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)               /*!< 0x00008000 */
+#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES_Pos           (16U)
+#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)            /*!< 0x00FF0000 */
+#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */
+#define I2C_CR2_RELOAD_Pos           (24U)
+#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)             /*!< 0x01000000 */
+#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND_Pos          (25U)
+#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)            /*!< 0x02000000 */
+#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE_Pos          (26U)
+#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)            /*!< 0x04000000 */
+#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */
+
+/*******************  Bit definition for I2C_OAR1 register  ******************/
+#define I2C_OAR1_OA1_Pos             (0U)
+#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)             /*!< 0x000003FF */
+#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE_Pos         (10U)
+#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)           /*!< 0x00000400 */
+#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN_Pos           (15U)
+#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)             /*!< 0x00008000 */
+#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */
+
+/*******************  Bit definition for I2C_OAR2 register  ******************/
+#define I2C_OAR2_OA2_Pos             (1U)
+#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)              /*!< 0x000000FE */
+#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK_Pos          (8U)
+#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)            /*!< 0x00000700 */
+#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK           0x00000000UL                              /*!< No mask */
+#define I2C_OAR2_OA2MASK01_Pos       (8U)
+#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)         /*!< 0x00000100 */
+#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02_Pos       (9U)
+#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)         /*!< 0x00000200 */
+#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03_Pos       (8U)
+#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)         /*!< 0x00000300 */
+#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04_Pos       (10U)
+#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)         /*!< 0x00000400 */
+#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05_Pos       (8U)
+#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)         /*!< 0x00000500 */
+#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06_Pos       (9U)
+#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)         /*!< 0x00000600 */
+#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07_Pos       (8U)
+#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)         /*!< 0x00000700 */
+#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN_Pos           (15U)
+#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)             /*!< 0x00008000 */
+#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable */
+
+/*******************  Bit definition for I2C_TIMINGR register *******************/
+#define I2C_TIMINGR_SCLL_Pos         (0U)
+#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)          /*!< 0x000000FF */
+#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH_Pos         (8U)
+#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)          /*!< 0x0000FF00 */
+#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL_Pos       (16U)
+#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)         /*!< 0x000F0000 */
+#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL_Pos       (20U)
+#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)         /*!< 0x00F00000 */
+#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */
+#define I2C_TIMINGR_PRESC_Pos        (28U)
+#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)          /*!< 0xF0000000 */
+#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)
+#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)    /*!< 0x00000FFF */
+#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE_Pos       (12U)
+#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)         /*!< 0x00001000 */
+#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)
+#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)      /*!< 0x00008000 */
+#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)
+#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)    /*!< 0x0FFF0000 */
+#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)
+#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)        /*!< 0x80000000 */
+#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
+
+/******************  Bit definition for I2C_ISR register  *********************/
+#define I2C_ISR_TXE_Pos              (0U)
+#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                /*!< 0x00000001 */
+#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */
+#define I2C_ISR_TXIS_Pos             (1U)
+#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)               /*!< 0x00000002 */
+#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE_Pos             (2U)
+#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)               /*!< 0x00000004 */
+#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
+#define I2C_ISR_ADDR_Pos             (3U)
+#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)               /*!< 0x00000008 */
+#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF_Pos            (4U)
+#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)              /*!< 0x00000010 */
+#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */
+#define I2C_ISR_STOPF_Pos            (5U)
+#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)              /*!< 0x00000020 */
+#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */
+#define I2C_ISR_TC_Pos               (6U)
+#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                 /*!< 0x00000040 */
+#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR_Pos              (7U)
+#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                /*!< 0x00000080 */
+#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */
+#define I2C_ISR_BERR_Pos             (8U)
+#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)               /*!< 0x00000100 */
+#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */
+#define I2C_ISR_ARLO_Pos             (9U)
+#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)               /*!< 0x00000200 */
+#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */
+#define I2C_ISR_OVR_Pos              (10U)
+#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                /*!< 0x00000400 */
+#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR_Pos           (11U)
+#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)             /*!< 0x00000800 */
+#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT_Pos          (12U)
+#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)            /*!< 0x00001000 */
+#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT_Pos            (13U)
+#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)              /*!< 0x00002000 */
+#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */
+#define I2C_ISR_BUSY_Pos             (15U)
+#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)               /*!< 0x00008000 */
+#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */
+#define I2C_ISR_DIR_Pos              (16U)
+#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                /*!< 0x00010000 */
+#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE_Pos          (17U)
+#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)           /*!< 0x00FE0000 */
+#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
+
+/******************  Bit definition for I2C_ICR register  *********************/
+#define I2C_ICR_ADDRCF_Pos           (3U)
+#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)             /*!< 0x00000008 */
+#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF_Pos           (4U)
+#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)             /*!< 0x00000010 */
+#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */
+#define I2C_ICR_STOPCF_Pos           (5U)
+#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)             /*!< 0x00000020 */
+#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF_Pos           (8U)
+#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)             /*!< 0x00000100 */
+#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF_Pos           (9U)
+#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)             /*!< 0x00000200 */
+#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF_Pos            (10U)
+#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)              /*!< 0x00000400 */
+#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF_Pos            (11U)
+#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)              /*!< 0x00000800 */
+#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF_Pos         (12U)
+#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)           /*!< 0x00001000 */
+#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF_Pos          (13U)
+#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)            /*!< 0x00002000 */
+#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */
+
+/******************  Bit definition for I2C_PECR register  *********************/
+#define I2C_PECR_PEC_Pos             (0U)
+#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)              /*!< 0x000000FF */
+#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
+
+/******************  Bit definition for I2C_RXDR register  *********************/
+#define I2C_RXDR_RXDATA_Pos          (0U)
+#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)           /*!< 0x000000FF */
+#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
+
+/******************  Bit definition for I2C_TXDR register  *********************/
+#define I2C_TXDR_TXDATA_Pos          (0U)
+#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)           /*!< 0x000000FF */
+#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Independent WATCHDOG                             */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define IWDG_KR_KEY_Pos      (0U)
+#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                     /*!< 0x0000FFFF */
+#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define IWDG_PR_PR_Pos       (0U)
+#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                         /*!< 0x00000007 */
+#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */
+#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */
+#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */
+#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define IWDG_RLR_RL_Pos      (0U)
+#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                      /*!< 0x00000FFF */
+#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define IWDG_SR_PVU_Pos      (0U)
+#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                        /*!< 0x00000001 */
+#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos      (1U)
+#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                        /*!< 0x00000002 */
+#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU_Pos      (2U)
+#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                        /*!< 0x00000004 */
+#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
+
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define IWDG_WINR_WIN_Pos    (0U)
+#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                    /*!< 0x00000FFF */
+#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        JPEG Encoder/Decoder                                */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for CONFR0 register  ********************/
+#define JPEG_CONFR0_START_Pos           (0U)
+#define JPEG_CONFR0_START_Msk           (0x1UL << JPEG_CONFR0_START_Pos)       /*!< 0x00000001 */
+#define JPEG_CONFR0_START               JPEG_CONFR0_START_Msk                  /*!<Start/Stop bit */
+
+/********************  Bit definition for CONFR1 register  ********************/
+#define JPEG_CONFR1_NF_Pos              (0U)
+#define JPEG_CONFR1_NF_Msk              (0x3UL << JPEG_CONFR1_NF_Pos)          /*!< 0x00000003 */
+#define JPEG_CONFR1_NF                  JPEG_CONFR1_NF_Msk                     /*!<Number of color components */
+#define JPEG_CONFR1_NF_0                (0x1UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000001 */
+#define JPEG_CONFR1_NF_1                (0x2UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000002 */
+#define JPEG_CONFR1_DE_Pos              (3U)
+#define JPEG_CONFR1_DE_Msk              (0x1UL << JPEG_CONFR1_DE_Pos)          /*!< 0x00000008 */
+#define JPEG_CONFR1_DE                  JPEG_CONFR1_DE_Msk                     /*!<Decoding Enable */
+#define JPEG_CONFR1_COLORSPACE_Pos      (4U)
+#define JPEG_CONFR1_COLORSPACE_Msk      (0x3UL << JPEG_CONFR1_COLORSPACE_Pos)  /*!< 0x00000030 */
+#define JPEG_CONFR1_COLORSPACE          JPEG_CONFR1_COLORSPACE_Msk             /*!<Color Space */
+#define JPEG_CONFR1_COLORSPACE_0        (0x1UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000010 */
+#define JPEG_CONFR1_COLORSPACE_1        (0x2UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000020 */
+#define JPEG_CONFR1_NS_Pos              (6U)
+#define JPEG_CONFR1_NS_Msk              (0x3UL << JPEG_CONFR1_NS_Pos)          /*!< 0x000000C0 */
+#define JPEG_CONFR1_NS                  JPEG_CONFR1_NS_Msk                     /*!<Number of components for Scan */
+#define JPEG_CONFR1_NS_0                (0x1UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000040 */
+#define JPEG_CONFR1_NS_1                (0x2UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000080 */
+#define JPEG_CONFR1_HDR_Pos             (8U)
+#define JPEG_CONFR1_HDR_Msk             (0x1UL << JPEG_CONFR1_HDR_Pos)         /*!< 0x00000100 */
+#define JPEG_CONFR1_HDR                 JPEG_CONFR1_HDR_Msk                    /*!<Header Processing On/Off */
+#define JPEG_CONFR1_YSIZE_Pos           (16U)
+#define JPEG_CONFR1_YSIZE_Msk           (0xFFFFUL << JPEG_CONFR1_YSIZE_Pos)    /*!< 0xFFFF0000 */
+#define JPEG_CONFR1_YSIZE               JPEG_CONFR1_YSIZE_Msk                  /*!<Number of lines in source image */
+
+/********************  Bit definition for CONFR2 register  ********************/
+#define JPEG_CONFR2_NMCU_Pos            (0U)
+#define JPEG_CONFR2_NMCU_Msk            (0x3FFFFFFUL << JPEG_CONFR2_NMCU_Pos)  /*!< 0x03FFFFFF */
+#define JPEG_CONFR2_NMCU                JPEG_CONFR2_NMCU_Msk                   /*!<Number of MCU units minus 1 to encode */
+
+/********************  Bit definition for CONFR3 register  ********************/
+#define JPEG_CONFR3_XSIZE_Pos           (16U)
+#define JPEG_CONFR3_XSIZE_Msk           (0xFFFFUL << JPEG_CONFR3_XSIZE_Pos)    /*!< 0xFFFF0000 */
+#define JPEG_CONFR3_XSIZE               JPEG_CONFR3_XSIZE_Msk                  /*!<Number of pixels per line */
+
+/********************  Bit definition for CONFR4 register  ********************/
+#define JPEG_CONFR4_HD_Pos              (0U)
+#define JPEG_CONFR4_HD_Msk              (0x1UL << JPEG_CONFR4_HD_Pos)          /*!< 0x00000001 */
+#define JPEG_CONFR4_HD                  JPEG_CONFR4_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */
+#define JPEG_CONFR4_HA_Pos              (1U)
+#define JPEG_CONFR4_HA_Msk              (0x1UL << JPEG_CONFR4_HA_Pos)          /*!< 0x00000002 */
+#define JPEG_CONFR4_HA                  JPEG_CONFR4_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */
+#define JPEG_CONFR4_QT_Pos              (2U)
+#define JPEG_CONFR4_QT_Msk              (0x3UL << JPEG_CONFR4_QT_Pos)          /*!< 0x0000000C */
+#define JPEG_CONFR4_QT                  JPEG_CONFR4_QT_Msk                     /*!<Selects quantization table associated with a color component */
+#define JPEG_CONFR4_QT_0                (0x1UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000004 */
+#define JPEG_CONFR4_QT_1                (0x2UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000008 */
+#define JPEG_CONFR4_NB_Pos              (4U)
+#define JPEG_CONFR4_NB_Msk              (0xFUL << JPEG_CONFR4_NB_Pos)          /*!< 0x000000F0 */
+#define JPEG_CONFR4_NB                  JPEG_CONFR4_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */
+#define JPEG_CONFR4_NB_0                (0x1UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000010 */
+#define JPEG_CONFR4_NB_1                (0x2UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000020 */
+#define JPEG_CONFR4_NB_2                (0x4UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000040 */
+#define JPEG_CONFR4_NB_3                (0x8UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000080 */
+#define JPEG_CONFR4_VSF_Pos             (8U)
+#define JPEG_CONFR4_VSF_Msk             (0xFUL << JPEG_CONFR4_VSF_Pos)         /*!< 0x00000F00 */
+#define JPEG_CONFR4_VSF                 JPEG_CONFR4_VSF_Msk                    /*!<Vertical sampling factor for component 1 */
+#define JPEG_CONFR4_VSF_0               (0x1UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000100 */
+#define JPEG_CONFR4_VSF_1               (0x2UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000200 */
+#define JPEG_CONFR4_VSF_2               (0x4UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000400 */
+#define JPEG_CONFR4_VSF_3               (0x8UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000800 */
+#define JPEG_CONFR4_HSF_Pos             (12U)
+#define JPEG_CONFR4_HSF_Msk             (0xFUL << JPEG_CONFR4_HSF_Pos)         /*!< 0x0000F000 */
+#define JPEG_CONFR4_HSF                 JPEG_CONFR4_HSF_Msk                    /*!<Horizontal sampling factor for component 1 */
+#define JPEG_CONFR4_HSF_0               (0x1UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00001000 */
+#define JPEG_CONFR4_HSF_1               (0x2UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00002000 */
+#define JPEG_CONFR4_HSF_2               (0x4UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00004000 */
+#define JPEG_CONFR4_HSF_3               (0x8UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00008000 */
+
+/********************  Bit definition for CONFR5 register  ********************/
+#define JPEG_CONFR5_HD_Pos              (0U)
+#define JPEG_CONFR5_HD_Msk              (0x1UL << JPEG_CONFR5_HD_Pos)          /*!< 0x00000001 */
+#define JPEG_CONFR5_HD                  JPEG_CONFR5_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */
+#define JPEG_CONFR5_HA_Pos              (1U)
+#define JPEG_CONFR5_HA_Msk              (0x1UL << JPEG_CONFR5_HA_Pos)          /*!< 0x00000002 */
+#define JPEG_CONFR5_HA                  JPEG_CONFR5_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */
+#define JPEG_CONFR5_QT_Pos              (2U)
+#define JPEG_CONFR5_QT_Msk              (0x3UL << JPEG_CONFR5_QT_Pos)          /*!< 0x0000000C */
+#define JPEG_CONFR5_QT                  JPEG_CONFR5_QT_Msk                     /*!<Selects quantization table associated with a color component */
+#define JPEG_CONFR5_QT_0                (0x1UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000004 */
+#define JPEG_CONFR5_QT_1                (0x2UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000008 */
+#define JPEG_CONFR5_NB_Pos              (4U)
+#define JPEG_CONFR5_NB_Msk              (0xFUL << JPEG_CONFR5_NB_Pos)          /*!< 0x000000F0 */
+#define JPEG_CONFR5_NB                  JPEG_CONFR5_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */
+#define JPEG_CONFR5_NB_0                (0x1UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000010 */
+#define JPEG_CONFR5_NB_1                (0x2UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000020 */
+#define JPEG_CONFR5_NB_2                (0x4UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000040 */
+#define JPEG_CONFR5_NB_3                (0x8UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000080 */
+#define JPEG_CONFR5_VSF_Pos             (8U)
+#define JPEG_CONFR5_VSF_Msk             (0xFUL << JPEG_CONFR5_VSF_Pos)         /*!< 0x00000F00 */
+#define JPEG_CONFR5_VSF                 JPEG_CONFR5_VSF_Msk                    /*!<Vertical sampling factor for component 2 */
+#define JPEG_CONFR5_VSF_0               (0x1UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000100 */
+#define JPEG_CONFR5_VSF_1               (0x2UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000200 */
+#define JPEG_CONFR5_VSF_2               (0x4UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000400 */
+#define JPEG_CONFR5_VSF_3               (0x8UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000800 */
+#define JPEG_CONFR5_HSF_Pos             (12U)
+#define JPEG_CONFR5_HSF_Msk             (0xFUL << JPEG_CONFR5_HSF_Pos)         /*!< 0x0000F000 */
+#define JPEG_CONFR5_HSF                 JPEG_CONFR5_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */
+#define JPEG_CONFR5_HSF_0               (0x1UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00001000 */
+#define JPEG_CONFR5_HSF_1               (0x2UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00002000 */
+#define JPEG_CONFR5_HSF_2               (0x4UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00004000 */
+#define JPEG_CONFR5_HSF_3               (0x8UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00008000 */
+
+/********************  Bit definition for CONFR6 register  ********************/
+#define JPEG_CONFR6_HD_Pos              (0U)
+#define JPEG_CONFR6_HD_Msk              (0x1UL << JPEG_CONFR6_HD_Pos)          /*!< 0x00000001 */
+#define JPEG_CONFR6_HD                  JPEG_CONFR6_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */
+#define JPEG_CONFR6_HA_Pos              (1U)
+#define JPEG_CONFR6_HA_Msk              (0x1UL << JPEG_CONFR6_HA_Pos)          /*!< 0x00000002 */
+#define JPEG_CONFR6_HA                  JPEG_CONFR6_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */
+#define JPEG_CONFR6_QT_Pos              (2U)
+#define JPEG_CONFR6_QT_Msk              (0x3UL << JPEG_CONFR6_QT_Pos)          /*!< 0x0000000C */
+#define JPEG_CONFR6_QT                  JPEG_CONFR6_QT_Msk                     /*!<Selects quantization table associated with a color component */
+#define JPEG_CONFR6_QT_0                (0x1UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000004 */
+#define JPEG_CONFR6_QT_1                (0x2UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000008 */
+#define JPEG_CONFR6_NB_Pos              (4U)
+#define JPEG_CONFR6_NB_Msk              (0xFUL << JPEG_CONFR6_NB_Pos)          /*!< 0x000000F0 */
+#define JPEG_CONFR6_NB                  JPEG_CONFR6_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */
+#define JPEG_CONFR6_NB_0                (0x1UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000010 */
+#define JPEG_CONFR6_NB_1                (0x2UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000020 */
+#define JPEG_CONFR6_NB_2                (0x4UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000040 */
+#define JPEG_CONFR6_NB_3                (0x8UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000080 */
+#define JPEG_CONFR6_VSF_Pos             (8U)
+#define JPEG_CONFR6_VSF_Msk             (0xFUL << JPEG_CONFR6_VSF_Pos)         /*!< 0x00000F00 */
+#define JPEG_CONFR6_VSF                 JPEG_CONFR6_VSF_Msk                    /*!<Vertical sampling factor for component 2 */
+#define JPEG_CONFR6_VSF_0               (0x1UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000100 */
+#define JPEG_CONFR6_VSF_1               (0x2UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000200 */
+#define JPEG_CONFR6_VSF_2               (0x4UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000400 */
+#define JPEG_CONFR6_VSF_3               (0x8UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000800 */
+#define JPEG_CONFR6_HSF_Pos             (12U)
+#define JPEG_CONFR6_HSF_Msk             (0xFUL << JPEG_CONFR6_HSF_Pos)         /*!< 0x0000F000 */
+#define JPEG_CONFR6_HSF                 JPEG_CONFR6_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */
+#define JPEG_CONFR6_HSF_0               (0x1UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00001000 */
+#define JPEG_CONFR6_HSF_1               (0x2UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00002000 */
+#define JPEG_CONFR6_HSF_2               (0x4UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00004000 */
+#define JPEG_CONFR6_HSF_3               (0x8UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00008000 */
+
+/********************  Bit definition for CONFR7 register  ********************/
+#define JPEG_CONFR7_HD_Pos              (0U)
+#define JPEG_CONFR7_HD_Msk              (0x1UL << JPEG_CONFR7_HD_Pos)          /*!< 0x00000001 */
+#define JPEG_CONFR7_HD                  JPEG_CONFR7_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */
+#define JPEG_CONFR7_HA_Pos              (1U)
+#define JPEG_CONFR7_HA_Msk              (0x1UL << JPEG_CONFR7_HA_Pos)          /*!< 0x00000002 */
+#define JPEG_CONFR7_HA                  JPEG_CONFR7_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */
+#define JPEG_CONFR7_QT_Pos              (2U)
+#define JPEG_CONFR7_QT_Msk              (0x3UL << JPEG_CONFR7_QT_Pos)          /*!< 0x0000000C */
+#define JPEG_CONFR7_QT                  JPEG_CONFR7_QT_Msk                     /*!<Selects quantization table associated with a color component */
+#define JPEG_CONFR7_QT_0                (0x1UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000004 */
+#define JPEG_CONFR7_QT_1                (0x2UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000008 */
+#define JPEG_CONFR7_NB_Pos              (4U)
+#define JPEG_CONFR7_NB_Msk              (0xFUL << JPEG_CONFR7_NB_Pos)          /*!< 0x000000F0 */
+#define JPEG_CONFR7_NB                  JPEG_CONFR7_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */
+#define JPEG_CONFR7_NB_0                (0x1UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000010 */
+#define JPEG_CONFR7_NB_1                (0x2UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000020 */
+#define JPEG_CONFR7_NB_2                (0x4UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000040 */
+#define JPEG_CONFR7_NB_3                (0x8UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000080 */
+#define JPEG_CONFR7_VSF_Pos             (8U)
+#define JPEG_CONFR7_VSF_Msk             (0xFUL << JPEG_CONFR7_VSF_Pos)         /*!< 0x00000F00 */
+#define JPEG_CONFR7_VSF                 JPEG_CONFR7_VSF_Msk                    /*!<Vertical sampling factor for component 2 */
+#define JPEG_CONFR7_VSF_0               (0x1UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000100 */
+#define JPEG_CONFR7_VSF_1               (0x2UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000200 */
+#define JPEG_CONFR7_VSF_2               (0x4UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000400 */
+#define JPEG_CONFR7_VSF_3               (0x8UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000800 */
+#define JPEG_CONFR7_HSF_Pos             (12U)
+#define JPEG_CONFR7_HSF_Msk             (0xFUL << JPEG_CONFR7_HSF_Pos)         /*!< 0x0000F000 */
+#define JPEG_CONFR7_HSF                 JPEG_CONFR7_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */
+#define JPEG_CONFR7_HSF_0               (0x1UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00001000 */
+#define JPEG_CONFR7_HSF_1               (0x2UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00002000 */
+#define JPEG_CONFR7_HSF_2               (0x4UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00004000 */
+#define JPEG_CONFR7_HSF_3               (0x8UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00008000 */
+
+/********************  Bit definition for CR register  ********************/
+#define JPEG_CR_JCEN_Pos                (0U)
+#define JPEG_CR_JCEN_Msk                (0x1UL << JPEG_CR_JCEN_Pos)            /*!< 0x00000001 */
+#define JPEG_CR_JCEN                    JPEG_CR_JCEN_Msk                       /*!<Enable the JPEG Codec Core */
+#define JPEG_CR_IFTIE_Pos               (1U)
+#define JPEG_CR_IFTIE_Msk               (0x1UL << JPEG_CR_IFTIE_Pos)           /*!< 0x00000002 */
+#define JPEG_CR_IFTIE                   JPEG_CR_IFTIE_Msk                      /*!<Input FIFO Threshold Interrupt Enable */
+#define JPEG_CR_IFNFIE_Pos              (2U)
+#define JPEG_CR_IFNFIE_Msk              (0x1UL << JPEG_CR_IFNFIE_Pos)          /*!< 0x00000004 */
+#define JPEG_CR_IFNFIE                  JPEG_CR_IFNFIE_Msk                     /*!<Input FIFO Not Full Interrupt Enable */
+#define JPEG_CR_OFTIE_Pos               (3U)
+#define JPEG_CR_OFTIE_Msk               (0x1UL << JPEG_CR_OFTIE_Pos)           /*!< 0x00000008 */
+#define JPEG_CR_OFTIE                   JPEG_CR_OFTIE_Msk                      /*!<Output FIFO Threshold Interrupt Enable */
+#define JPEG_CR_OFNEIE_Pos              (4U)
+#define JPEG_CR_OFNEIE_Msk              (0x1UL << JPEG_CR_OFNEIE_Pos)          /*!< 0x00000010 */
+#define JPEG_CR_OFNEIE                  JPEG_CR_OFNEIE_Msk                     /*!<Output FIFO Not Empty Interrupt Enable */
+#define JPEG_CR_EOCIE_Pos               (5U)
+#define JPEG_CR_EOCIE_Msk               (0x1UL << JPEG_CR_EOCIE_Pos)           /*!< 0x00000020 */
+#define JPEG_CR_EOCIE                   JPEG_CR_EOCIE_Msk                      /*!<End of Conversion Interrupt Enable */
+#define JPEG_CR_HPDIE_Pos               (6U)
+#define JPEG_CR_HPDIE_Msk               (0x1UL << JPEG_CR_HPDIE_Pos)           /*!< 0x00000040 */
+#define JPEG_CR_HPDIE                   JPEG_CR_HPDIE_Msk                      /*!<Header Parsing Done Interrupt Enable */
+#define JPEG_CR_IFF_Pos                 (13U)
+#define JPEG_CR_IFF_Msk                 (0x1UL << JPEG_CR_IFF_Pos)             /*!< 0x00002000 */
+#define JPEG_CR_IFF                     JPEG_CR_IFF_Msk                        /*!<Flush the input FIFO */
+#define JPEG_CR_OFF_Pos                 (14U)
+#define JPEG_CR_OFF_Msk                 (0x1UL << JPEG_CR_OFF_Pos)             /*!< 0x00004000 */
+#define JPEG_CR_OFF                     JPEG_CR_OFF_Msk                        /*!<Flush the output FIFO */
+
+/********************  Bit definition for SR register  ********************/
+#define JPEG_SR_IFTF_Pos                (1U)
+#define JPEG_SR_IFTF_Msk                (0x1UL << JPEG_SR_IFTF_Pos)            /*!< 0x00000002 */
+#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is bellow its threshold flag */
+#define JPEG_SR_IFNFF_Pos               (2U)
+#define JPEG_SR_IFNFF_Msk               (0x1UL << JPEG_SR_IFNFF_Pos)           /*!< 0x00000004 */
+#define JPEG_SR_IFNFF                   JPEG_SR_IFNFF_Msk                      /*!<Input FIFO Not Full Flag, a data can be written */
+#define JPEG_SR_OFTF_Pos                (3U)
+#define JPEG_SR_OFTF_Msk                (0x1UL << JPEG_SR_OFTF_Pos)            /*!< 0x00000008 */
+#define JPEG_SR_OFTF                    JPEG_SR_OFTF_Msk                       /*!<Output FIFO is not empty and has reach its threshold */
+#define JPEG_SR_OFNEF_Pos               (4U)
+#define JPEG_SR_OFNEF_Msk               (0x1UL << JPEG_SR_OFNEF_Pos)           /*!< 0x00000010 */
+#define JPEG_SR_OFNEF                   JPEG_SR_OFNEF_Msk                      /*!<Output FIFO is not empty, a data is available */
+#define JPEG_SR_EOCF_Pos                (5U)
+#define JPEG_SR_EOCF_Msk                (0x1UL << JPEG_SR_EOCF_Pos)            /*!< 0x00000020 */
+#define JPEG_SR_EOCF                    JPEG_SR_EOCF_Msk                       /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */
+#define JPEG_SR_HPDF_Pos                (6U)
+#define JPEG_SR_HPDF_Msk                (0x1UL << JPEG_SR_HPDF_Pos)            /*!< 0x00000040 */
+#define JPEG_SR_HPDF                    JPEG_SR_HPDF_Msk                       /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */
+#define JPEG_SR_COF_Pos                 (7U)
+#define JPEG_SR_COF_Msk                 (0x1UL << JPEG_SR_COF_Pos)             /*!< 0x00000080 */
+#define JPEG_SR_COF                     JPEG_SR_COF_Msk                        /*!<JPEG Codec operation on going flag */
+
+/********************  Bit definition for CFR register  ********************/
+#define JPEG_CFR_CEOCF_Pos              (4U)
+#define JPEG_CFR_CEOCF_Msk              (0x1UL << JPEG_CFR_CEOCF_Pos)          /*!< 0x00000010 */
+#define JPEG_CFR_CEOCF                  JPEG_CFR_CEOCF_Msk                     /*!<Clear End of Conversion Flag */
+#define JPEG_CFR_CHPDF_Pos              (5U)
+#define JPEG_CFR_CHPDF_Msk              (0x1UL << JPEG_CFR_CHPDF_Pos)          /*!< 0x00000020 */
+#define JPEG_CFR_CHPDF                  JPEG_CFR_CHPDF_Msk                     /*!<Clear Header Parsing Done Flag */
+
+/********************  Bit definition for DIR register  ********************/
+#define JPEG_DIR_DATAIN_Pos             (0U)
+#define JPEG_DIR_DATAIN_Msk             (0xFFFFFFFFUL << JPEG_DIR_DATAIN_Pos)  /*!< 0xFFFFFFFF */
+#define JPEG_DIR_DATAIN                 JPEG_DIR_DATAIN_Msk                    /*!<Data Input FIFO */
+
+/********************  Bit definition for DOR register  ********************/
+#define JPEG_DOR_DATAOUT_Pos            (0U)
+#define JPEG_DOR_DATAOUT_Msk            (0xFFFFFFFFUL << JPEG_DOR_DATAOUT_Pos) /*!< 0xFFFFFFFF */
+#define JPEG_DOR_DATAOUT                JPEG_DOR_DATAOUT_Msk                   /*!<Data Output FIFO */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      LCD-TFT Display Controller (LTDC)                     */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for LTDC_SSCR register  *****************/
+
+#define LTDC_SSCR_VSH_Pos            (0U)
+#define LTDC_SSCR_VSH_Msk            (0x7FFUL << LTDC_SSCR_VSH_Pos)            /*!< 0x000007FF */
+#define LTDC_SSCR_VSH                LTDC_SSCR_VSH_Msk                         /*!< Vertical Synchronization Height  */
+#define LTDC_SSCR_HSW_Pos            (16U)
+#define LTDC_SSCR_HSW_Msk            (0xFFFUL << LTDC_SSCR_HSW_Pos)            /*!< 0x0FFF0000 */
+#define LTDC_SSCR_HSW                LTDC_SSCR_HSW_Msk                         /*!< Horizontal Synchronization Width */
+
+/********************  Bit definition for LTDC_BPCR register  *****************/
+
+#define LTDC_BPCR_AVBP_Pos           (0U)
+#define LTDC_BPCR_AVBP_Msk           (0x7FFUL << LTDC_BPCR_AVBP_Pos)           /*!< 0x000007FF */
+#define LTDC_BPCR_AVBP               LTDC_BPCR_AVBP_Msk                        /*!< Accumulated Vertical Back Porch   */
+#define LTDC_BPCR_AHBP_Pos           (16U)
+#define LTDC_BPCR_AHBP_Msk           (0xFFFUL << LTDC_BPCR_AHBP_Pos)           /*!< 0x0FFF0000 */
+#define LTDC_BPCR_AHBP               LTDC_BPCR_AHBP_Msk                        /*!< Accumulated Horizontal Back Porch */
+
+/********************  Bit definition for LTDC_AWCR register  *****************/
+
+#define LTDC_AWCR_AAH_Pos            (0U)
+#define LTDC_AWCR_AAH_Msk            (0x7FFUL << LTDC_AWCR_AAH_Pos)            /*!< 0x000007FF */
+#define LTDC_AWCR_AAH                LTDC_AWCR_AAH_Msk                         /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAW_Pos            (16U)
+#define LTDC_AWCR_AAW_Msk            (0xFFFUL << LTDC_AWCR_AAW_Pos)            /*!< 0x0FFF0000 */
+#define LTDC_AWCR_AAW                LTDC_AWCR_AAW_Msk                         /*!< Accumulated Active Width */
+
+/********************  Bit definition for LTDC_TWCR register  *****************/
+
+#define LTDC_TWCR_TOTALH_Pos         (0U)
+#define LTDC_TWCR_TOTALH_Msk         (0x7FFUL << LTDC_TWCR_TOTALH_Pos)         /*!< 0x000007FF */
+#define LTDC_TWCR_TOTALH             LTDC_TWCR_TOTALH_Msk                      /*!< Total Heigh */
+#define LTDC_TWCR_TOTALW_Pos         (16U)
+#define LTDC_TWCR_TOTALW_Msk         (0xFFFUL << LTDC_TWCR_TOTALW_Pos)         /*!< 0x0FFF0000 */
+#define LTDC_TWCR_TOTALW             LTDC_TWCR_TOTALW_Msk                      /*!< Total Width */
+
+/********************  Bit definition for LTDC_GCR register  ******************/
+
+#define LTDC_GCR_LTDCEN_Pos          (0U)
+#define LTDC_GCR_LTDCEN_Msk          (0x1UL << LTDC_GCR_LTDCEN_Pos)            /*!< 0x00000001 */
+#define LTDC_GCR_LTDCEN              LTDC_GCR_LTDCEN_Msk                       /*!< LCD-TFT controller enable bit       */
+#define LTDC_GCR_DBW_Pos             (4U)
+#define LTDC_GCR_DBW_Msk             (0x7UL << LTDC_GCR_DBW_Pos)               /*!< 0x00000070 */
+#define LTDC_GCR_DBW                 LTDC_GCR_DBW_Msk                          /*!< Dither Blue Width                   */
+#define LTDC_GCR_DGW_Pos             (8U)
+#define LTDC_GCR_DGW_Msk             (0x7UL << LTDC_GCR_DGW_Pos)               /*!< 0x00000700 */
+#define LTDC_GCR_DGW                 LTDC_GCR_DGW_Msk                          /*!< Dither Green Width                  */
+#define LTDC_GCR_DRW_Pos             (12U)
+#define LTDC_GCR_DRW_Msk             (0x7UL << LTDC_GCR_DRW_Pos)               /*!< 0x00007000 */
+#define LTDC_GCR_DRW                 LTDC_GCR_DRW_Msk                          /*!< Dither Red Width                    */
+#define LTDC_GCR_DEN_Pos             (16U)
+#define LTDC_GCR_DEN_Msk             (0x1UL << LTDC_GCR_DEN_Pos)               /*!< 0x00010000 */
+#define LTDC_GCR_DEN                 LTDC_GCR_DEN_Msk                          /*!< Dither Enable                       */
+#define LTDC_GCR_PCPOL_Pos           (28U)
+#define LTDC_GCR_PCPOL_Msk           (0x1UL << LTDC_GCR_PCPOL_Pos)             /*!< 0x10000000 */
+#define LTDC_GCR_PCPOL               LTDC_GCR_PCPOL_Msk                        /*!< Pixel Clock Polarity                */
+#define LTDC_GCR_DEPOL_Pos           (29U)
+#define LTDC_GCR_DEPOL_Msk           (0x1UL << LTDC_GCR_DEPOL_Pos)             /*!< 0x20000000 */
+#define LTDC_GCR_DEPOL               LTDC_GCR_DEPOL_Msk                        /*!< Data Enable Polarity                */
+#define LTDC_GCR_VSPOL_Pos           (30U)
+#define LTDC_GCR_VSPOL_Msk           (0x1UL << LTDC_GCR_VSPOL_Pos)             /*!< 0x40000000 */
+#define LTDC_GCR_VSPOL               LTDC_GCR_VSPOL_Msk                        /*!< Vertical Synchronization Polarity   */
+#define LTDC_GCR_HSPOL_Pos           (31U)
+#define LTDC_GCR_HSPOL_Msk           (0x1UL << LTDC_GCR_HSPOL_Pos)             /*!< 0x80000000 */
+#define LTDC_GCR_HSPOL               LTDC_GCR_HSPOL_Msk                        /*!< Horizontal Synchronization Polarity */
+
+
+/********************  Bit definition for LTDC_SRCR register  *****************/
+
+#define LTDC_SRCR_IMR_Pos            (0U)
+#define LTDC_SRCR_IMR_Msk            (0x1UL << LTDC_SRCR_IMR_Pos)              /*!< 0x00000001 */
+#define LTDC_SRCR_IMR                LTDC_SRCR_IMR_Msk                         /*!< Immediate Reload         */
+#define LTDC_SRCR_VBR_Pos            (1U)
+#define LTDC_SRCR_VBR_Msk            (0x1UL << LTDC_SRCR_VBR_Pos)              /*!< 0x00000002 */
+#define LTDC_SRCR_VBR                LTDC_SRCR_VBR_Msk                         /*!< Vertical Blanking Reload */
+
+/********************  Bit definition for LTDC_BCCR register  *****************/
+
+#define LTDC_BCCR_BCBLUE_Pos         (0U)
+#define LTDC_BCCR_BCBLUE_Msk         (0xFFUL << LTDC_BCCR_BCBLUE_Pos)          /*!< 0x000000FF */
+#define LTDC_BCCR_BCBLUE             LTDC_BCCR_BCBLUE_Msk                      /*!< Background Blue value  */
+#define LTDC_BCCR_BCGREEN_Pos        (8U)
+#define LTDC_BCCR_BCGREEN_Msk        (0xFFUL << LTDC_BCCR_BCGREEN_Pos)         /*!< 0x0000FF00 */
+#define LTDC_BCCR_BCGREEN            LTDC_BCCR_BCGREEN_Msk                     /*!< Background Green value */
+#define LTDC_BCCR_BCRED_Pos          (16U)
+#define LTDC_BCCR_BCRED_Msk          (0xFFUL << LTDC_BCCR_BCRED_Pos)           /*!< 0x00FF0000 */
+#define LTDC_BCCR_BCRED              LTDC_BCCR_BCRED_Msk                       /*!< Background Red value   */
+
+/********************  Bit definition for LTDC_IER register  ******************/
+
+#define LTDC_IER_LIE_Pos             (0U)
+#define LTDC_IER_LIE_Msk             (0x1UL << LTDC_IER_LIE_Pos)               /*!< 0x00000001 */
+#define LTDC_IER_LIE                 LTDC_IER_LIE_Msk                          /*!< Line Interrupt Enable            */
+#define LTDC_IER_FUIE_Pos            (1U)
+#define LTDC_IER_FUIE_Msk            (0x1UL << LTDC_IER_FUIE_Pos)              /*!< 0x00000002 */
+#define LTDC_IER_FUIE                LTDC_IER_FUIE_Msk                         /*!< FIFO Underrun Interrupt Enable   */
+#define LTDC_IER_TERRIE_Pos          (2U)
+#define LTDC_IER_TERRIE_Msk          (0x1UL << LTDC_IER_TERRIE_Pos)            /*!< 0x00000004 */
+#define LTDC_IER_TERRIE              LTDC_IER_TERRIE_Msk                       /*!< Transfer Error Interrupt Enable  */
+#define LTDC_IER_RRIE_Pos            (3U)
+#define LTDC_IER_RRIE_Msk            (0x1UL << LTDC_IER_RRIE_Pos)              /*!< 0x00000008 */
+#define LTDC_IER_RRIE                LTDC_IER_RRIE_Msk                         /*!< Register Reload interrupt enable */
+
+/********************  Bit definition for LTDC_ISR register  ******************/
+
+#define LTDC_ISR_LIF_Pos             (0U)
+#define LTDC_ISR_LIF_Msk             (0x1UL << LTDC_ISR_LIF_Pos)               /*!< 0x00000001 */
+#define LTDC_ISR_LIF                 LTDC_ISR_LIF_Msk                          /*!< Line Interrupt Flag */
+#define LTDC_ISR_FUIF_Pos            (1U)
+#define LTDC_ISR_FUIF_Msk            (0x1UL << LTDC_ISR_FUIF_Pos)              /*!< 0x00000002 */
+#define LTDC_ISR_FUIF                LTDC_ISR_FUIF_Msk                         /*!< FIFO Underrun Interrupt Flag */
+#define LTDC_ISR_TERRIF_Pos          (2U)
+#define LTDC_ISR_TERRIF_Msk          (0x1UL << LTDC_ISR_TERRIF_Pos)            /*!< 0x00000004 */
+#define LTDC_ISR_TERRIF              LTDC_ISR_TERRIF_Msk                       /*!< Transfer Error Interrupt Flag */
+#define LTDC_ISR_RRIF_Pos            (3U)
+#define LTDC_ISR_RRIF_Msk            (0x1UL << LTDC_ISR_RRIF_Pos)              /*!< 0x00000008 */
+#define LTDC_ISR_RRIF                LTDC_ISR_RRIF_Msk                         /*!< Register Reload interrupt Flag */
+
+/********************  Bit definition for LTDC_ICR register  ******************/
+
+#define LTDC_ICR_CLIF_Pos            (0U)
+#define LTDC_ICR_CLIF_Msk            (0x1UL << LTDC_ICR_CLIF_Pos)              /*!< 0x00000001 */
+#define LTDC_ICR_CLIF                LTDC_ICR_CLIF_Msk                         /*!< Clears the Line Interrupt Flag */
+#define LTDC_ICR_CFUIF_Pos           (1U)
+#define LTDC_ICR_CFUIF_Msk           (0x1UL << LTDC_ICR_CFUIF_Pos)             /*!< 0x00000002 */
+#define LTDC_ICR_CFUIF               LTDC_ICR_CFUIF_Msk                        /*!< Clears the FIFO Underrun Interrupt Flag */
+#define LTDC_ICR_CTERRIF_Pos         (2U)
+#define LTDC_ICR_CTERRIF_Msk         (0x1UL << LTDC_ICR_CTERRIF_Pos)           /*!< 0x00000004 */
+#define LTDC_ICR_CTERRIF             LTDC_ICR_CTERRIF_Msk                      /*!< Clears the Transfer Error Interrupt Flag */
+#define LTDC_ICR_CRRIF_Pos           (3U)
+#define LTDC_ICR_CRRIF_Msk           (0x1UL << LTDC_ICR_CRRIF_Pos)             /*!< 0x00000008 */
+#define LTDC_ICR_CRRIF               LTDC_ICR_CRRIF_Msk                        /*!< Clears Register Reload interrupt Flag */
+
+/********************  Bit definition for LTDC_LIPCR register  ****************/
+
+#define LTDC_LIPCR_LIPOS_Pos         (0U)
+#define LTDC_LIPCR_LIPOS_Msk         (0x7FFUL << LTDC_LIPCR_LIPOS_Pos)         /*!< 0x000007FF */
+#define LTDC_LIPCR_LIPOS             LTDC_LIPCR_LIPOS_Msk                      /*!< Line Interrupt Position */
+
+/********************  Bit definition for LTDC_CPSR register  *****************/
+
+#define LTDC_CPSR_CYPOS_Pos          (0U)
+#define LTDC_CPSR_CYPOS_Msk          (0xFFFFUL << LTDC_CPSR_CYPOS_Pos)         /*!< 0x0000FFFF */
+#define LTDC_CPSR_CYPOS              LTDC_CPSR_CYPOS_Msk                       /*!< Current Y Position */
+#define LTDC_CPSR_CXPOS_Pos          (16U)
+#define LTDC_CPSR_CXPOS_Msk          (0xFFFFUL << LTDC_CPSR_CXPOS_Pos)         /*!< 0xFFFF0000 */
+#define LTDC_CPSR_CXPOS              LTDC_CPSR_CXPOS_Msk                       /*!< Current X Position */
+
+/********************  Bit definition for LTDC_CDSR register  *****************/
+
+#define LTDC_CDSR_VDES_Pos           (0U)
+#define LTDC_CDSR_VDES_Msk           (0x1UL << LTDC_CDSR_VDES_Pos)             /*!< 0x00000001 */
+#define LTDC_CDSR_VDES               LTDC_CDSR_VDES_Msk                        /*!< Vertical Data Enable Status       */
+#define LTDC_CDSR_HDES_Pos           (1U)
+#define LTDC_CDSR_HDES_Msk           (0x1UL << LTDC_CDSR_HDES_Pos)             /*!< 0x00000002 */
+#define LTDC_CDSR_HDES               LTDC_CDSR_HDES_Msk                        /*!< Horizontal Data Enable Status     */
+#define LTDC_CDSR_VSYNCS_Pos         (2U)
+#define LTDC_CDSR_VSYNCS_Msk         (0x1UL << LTDC_CDSR_VSYNCS_Pos)           /*!< 0x00000004 */
+#define LTDC_CDSR_VSYNCS             LTDC_CDSR_VSYNCS_Msk                      /*!< Vertical Synchronization Status   */
+#define LTDC_CDSR_HSYNCS_Pos         (3U)
+#define LTDC_CDSR_HSYNCS_Msk         (0x1UL << LTDC_CDSR_HSYNCS_Pos)           /*!< 0x00000008 */
+#define LTDC_CDSR_HSYNCS             LTDC_CDSR_HSYNCS_Msk                      /*!< Horizontal Synchronization Status */
+
+/********************  Bit definition for LTDC_LxCR register  *****************/
+
+#define LTDC_LxCR_LEN_Pos            (0U)
+#define LTDC_LxCR_LEN_Msk            (0x1UL << LTDC_LxCR_LEN_Pos)              /*!< 0x00000001 */
+#define LTDC_LxCR_LEN                LTDC_LxCR_LEN_Msk                         /*!< Layer Enable              */
+#define LTDC_LxCR_COLKEN_Pos         (1U)
+#define LTDC_LxCR_COLKEN_Msk         (0x1UL << LTDC_LxCR_COLKEN_Pos)           /*!< 0x00000002 */
+#define LTDC_LxCR_COLKEN             LTDC_LxCR_COLKEN_Msk                      /*!< Color Keying Enable       */
+#define LTDC_LxCR_CLUTEN_Pos         (4U)
+#define LTDC_LxCR_CLUTEN_Msk         (0x1UL << LTDC_LxCR_CLUTEN_Pos)           /*!< 0x00000010 */
+#define LTDC_LxCR_CLUTEN             LTDC_LxCR_CLUTEN_Msk                      /*!< Color Lockup Table Enable */
+
+/********************  Bit definition for LTDC_LxWHPCR register  **************/
+
+#define LTDC_LxWHPCR_WHSTPOS_Pos     (0U)
+#define LTDC_LxWHPCR_WHSTPOS_Msk     (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos)     /*!< 0x00000FFF */
+#define LTDC_LxWHPCR_WHSTPOS         LTDC_LxWHPCR_WHSTPOS_Msk                  /*!< Window Horizontal Start Position */
+#define LTDC_LxWHPCR_WHSPPOS_Pos     (16U)
+#define LTDC_LxWHPCR_WHSPPOS_Msk     (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos)    /*!< 0xFFFF0000 */
+#define LTDC_LxWHPCR_WHSPPOS         LTDC_LxWHPCR_WHSPPOS_Msk                  /*!< Window Horizontal Stop Position  */
+
+/********************  Bit definition for LTDC_LxWVPCR register  **************/
+
+#define LTDC_LxWVPCR_WVSTPOS_Pos     (0U)
+#define LTDC_LxWVPCR_WVSTPOS_Msk     (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos)     /*!< 0x00000FFF */
+#define LTDC_LxWVPCR_WVSTPOS         LTDC_LxWVPCR_WVSTPOS_Msk                  /*!< Window Vertical Start Position */
+#define LTDC_LxWVPCR_WVSPPOS_Pos     (16U)
+#define LTDC_LxWVPCR_WVSPPOS_Msk     (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos)    /*!< 0xFFFF0000 */
+#define LTDC_LxWVPCR_WVSPPOS         LTDC_LxWVPCR_WVSPPOS_Msk                  /*!< Window Vertical Stop Position  */
+
+/********************  Bit definition for LTDC_LxCKCR register  ***************/
+
+#define LTDC_LxCKCR_CKBLUE_Pos       (0U)
+#define LTDC_LxCKCR_CKBLUE_Msk       (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos)        /*!< 0x000000FF */
+#define LTDC_LxCKCR_CKBLUE           LTDC_LxCKCR_CKBLUE_Msk                    /*!< Color Key Blue value  */
+#define LTDC_LxCKCR_CKGREEN_Pos      (8U)
+#define LTDC_LxCKCR_CKGREEN_Msk      (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos)       /*!< 0x0000FF00 */
+#define LTDC_LxCKCR_CKGREEN          LTDC_LxCKCR_CKGREEN_Msk                   /*!< Color Key Green value */
+#define LTDC_LxCKCR_CKRED_Pos        (16U)
+#define LTDC_LxCKCR_CKRED_Msk        (0xFFUL << LTDC_LxCKCR_CKRED_Pos)         /*!< 0x00FF0000 */
+#define LTDC_LxCKCR_CKRED            LTDC_LxCKCR_CKRED_Msk                     /*!< Color Key Red value   */
+
+/********************  Bit definition for LTDC_LxPFCR register  ***************/
+
+#define LTDC_LxPFCR_PF_Pos           (0U)
+#define LTDC_LxPFCR_PF_Msk           (0x7UL << LTDC_LxPFCR_PF_Pos)             /*!< 0x00000007 */
+#define LTDC_LxPFCR_PF               LTDC_LxPFCR_PF_Msk                        /*!< Pixel Format */
+
+/********************  Bit definition for LTDC_LxCACR register  ***************/
+
+#define LTDC_LxCACR_CONSTA_Pos       (0U)
+#define LTDC_LxCACR_CONSTA_Msk       (0xFFUL << LTDC_LxCACR_CONSTA_Pos)        /*!< 0x000000FF */
+#define LTDC_LxCACR_CONSTA           LTDC_LxCACR_CONSTA_Msk                    /*!< Constant Alpha */
+
+/********************  Bit definition for LTDC_LxDCCR register  ***************/
+
+#define LTDC_LxDCCR_DCBLUE_Pos       (0U)
+#define LTDC_LxDCCR_DCBLUE_Msk       (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos)        /*!< 0x000000FF */
+#define LTDC_LxDCCR_DCBLUE           LTDC_LxDCCR_DCBLUE_Msk                    /*!< Default Color Blue  */
+#define LTDC_LxDCCR_DCGREEN_Pos      (8U)
+#define LTDC_LxDCCR_DCGREEN_Msk      (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos)       /*!< 0x0000FF00 */
+#define LTDC_LxDCCR_DCGREEN          LTDC_LxDCCR_DCGREEN_Msk                   /*!< Default Color Green */
+#define LTDC_LxDCCR_DCRED_Pos        (16U)
+#define LTDC_LxDCCR_DCRED_Msk        (0xFFUL << LTDC_LxDCCR_DCRED_Pos)         /*!< 0x00FF0000 */
+#define LTDC_LxDCCR_DCRED            LTDC_LxDCCR_DCRED_Msk                     /*!< Default Color Red   */
+#define LTDC_LxDCCR_DCALPHA_Pos      (24U)
+#define LTDC_LxDCCR_DCALPHA_Msk      (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos)       /*!< 0xFF000000 */
+#define LTDC_LxDCCR_DCALPHA          LTDC_LxDCCR_DCALPHA_Msk                   /*!< Default Color Alpha */
+
+/********************  Bit definition for LTDC_LxBFCR register  ***************/
+
+#define LTDC_LxBFCR_BF2_Pos          (0U)
+#define LTDC_LxBFCR_BF2_Msk          (0x7UL << LTDC_LxBFCR_BF2_Pos)            /*!< 0x00000007 */
+#define LTDC_LxBFCR_BF2              LTDC_LxBFCR_BF2_Msk                       /*!< Blending Factor 2 */
+#define LTDC_LxBFCR_BF1_Pos          (8U)
+#define LTDC_LxBFCR_BF1_Msk          (0x7UL << LTDC_LxBFCR_BF1_Pos)            /*!< 0x00000700 */
+#define LTDC_LxBFCR_BF1              LTDC_LxBFCR_BF1_Msk                       /*!< Blending Factor 1 */
+
+/********************  Bit definition for LTDC_LxCFBAR register  **************/
+
+#define LTDC_LxCFBAR_CFBADD_Pos      (0U)
+#define LTDC_LxCFBAR_CFBADD_Msk      (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */
+#define LTDC_LxCFBAR_CFBADD          LTDC_LxCFBAR_CFBADD_Msk                   /*!< Color Frame Buffer Start Address */
+
+/********************  Bit definition for LTDC_LxCFBLR register  **************/
+
+#define LTDC_LxCFBLR_CFBLL_Pos       (0U)
+#define LTDC_LxCFBLR_CFBLL_Msk       (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos)      /*!< 0x00001FFF */
+#define LTDC_LxCFBLR_CFBLL           LTDC_LxCFBLR_CFBLL_Msk                    /*!< Color Frame Buffer Line Length    */
+#define LTDC_LxCFBLR_CFBP_Pos        (16U)
+#define LTDC_LxCFBLR_CFBP_Msk        (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos)       /*!< 0x1FFF0000 */
+#define LTDC_LxCFBLR_CFBP            LTDC_LxCFBLR_CFBP_Msk                     /*!< Color Frame Buffer Pitch in bytes */
+
+/********************  Bit definition for LTDC_LxCFBLNR register  *************/
+
+#define LTDC_LxCFBLNR_CFBLNBR_Pos    (0U)
+#define LTDC_LxCFBLNR_CFBLNBR_Msk    (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos)    /*!< 0x000007FF */
+#define LTDC_LxCFBLNR_CFBLNBR        LTDC_LxCFBLNR_CFBLNBR_Msk                 /*!< Frame Buffer Line Number */
+
+/********************  Bit definition for LTDC_LxCLUTWR register  *************/
+
+#define LTDC_LxCLUTWR_BLUE_Pos       (0U)
+#define LTDC_LxCLUTWR_BLUE_Msk       (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos)        /*!< 0x000000FF */
+#define LTDC_LxCLUTWR_BLUE           LTDC_LxCLUTWR_BLUE_Msk                    /*!< Blue value   */
+#define LTDC_LxCLUTWR_GREEN_Pos      (8U)
+#define LTDC_LxCLUTWR_GREEN_Msk      (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos)       /*!< 0x0000FF00 */
+#define LTDC_LxCLUTWR_GREEN          LTDC_LxCLUTWR_GREEN_Msk                   /*!< Green value  */
+#define LTDC_LxCLUTWR_RED_Pos        (16U)
+#define LTDC_LxCLUTWR_RED_Msk        (0xFFUL << LTDC_LxCLUTWR_RED_Pos)         /*!< 0x00FF0000 */
+#define LTDC_LxCLUTWR_RED            LTDC_LxCLUTWR_RED_Msk                     /*!< Red value    */
+#define LTDC_LxCLUTWR_CLUTADD_Pos    (24U)
+#define LTDC_LxCLUTWR_CLUTADD_Msk    (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos)     /*!< 0xFF000000 */
+#define LTDC_LxCLUTWR_CLUTADD        LTDC_LxCLUTWR_CLUTADD_Msk                 /*!< CLUT address */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                     MDMA                                   */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for MDMA_GISR0 register  ****************/
+#define MDMA_GISR0_GIF0_Pos       (0U)
+#define MDMA_GISR0_GIF0_Msk       (0x1UL << MDMA_GISR0_GIF0_Pos)               /*!< 0x00000001 */
+#define MDMA_GISR0_GIF0           MDMA_GISR0_GIF0_Msk                          /*!< Channel 0 global interrupt flag */
+#define MDMA_GISR0_GIF1_Pos       (1U)
+#define MDMA_GISR0_GIF1_Msk       (0x1UL << MDMA_GISR0_GIF1_Pos)               /*!< 0x00000002 */
+#define MDMA_GISR0_GIF1           MDMA_GISR0_GIF1_Msk                          /*!< Channel 1 global interrupt flag */
+#define MDMA_GISR0_GIF2_Pos       (2U)
+#define MDMA_GISR0_GIF2_Msk       (0x1UL << MDMA_GISR0_GIF2_Pos)               /*!< 0x00000004 */
+#define MDMA_GISR0_GIF2           MDMA_GISR0_GIF2_Msk                          /*!< Channel 2 global interrupt flag */
+#define MDMA_GISR0_GIF3_Pos       (3U)
+#define MDMA_GISR0_GIF3_Msk       (0x1UL << MDMA_GISR0_GIF3_Pos)               /*!< 0x00000008 */
+#define MDMA_GISR0_GIF3           MDMA_GISR0_GIF3_Msk                          /*!< Channel 3 global interrupt flag */
+#define MDMA_GISR0_GIF4_Pos       (4U)
+#define MDMA_GISR0_GIF4_Msk       (0x1UL << MDMA_GISR0_GIF4_Pos)               /*!< 0x00000010 */
+#define MDMA_GISR0_GIF4           MDMA_GISR0_GIF4_Msk                          /*!< Channel 4 global interrupt flag */
+#define MDMA_GISR0_GIF5_Pos       (5U)
+#define MDMA_GISR0_GIF5_Msk       (0x1UL << MDMA_GISR0_GIF5_Pos)               /*!< 0x00000020 */
+#define MDMA_GISR0_GIF5           MDMA_GISR0_GIF5_Msk                          /*!< Channel 5 global interrupt flag */
+#define MDMA_GISR0_GIF6_Pos       (6U)
+#define MDMA_GISR0_GIF6_Msk       (0x1UL << MDMA_GISR0_GIF6_Pos)               /*!< 0x00000040 */
+#define MDMA_GISR0_GIF6           MDMA_GISR0_GIF6_Msk                          /*!< Channel 6 global interrupt flag */
+#define MDMA_GISR0_GIF7_Pos       (7U)
+#define MDMA_GISR0_GIF7_Msk       (0x1UL << MDMA_GISR0_GIF7_Pos)               /*!< 0x00000080 */
+#define MDMA_GISR0_GIF7           MDMA_GISR0_GIF7_Msk                          /*!< Channel 7 global interrupt flag */
+#define MDMA_GISR0_GIF8_Pos       (8U)
+#define MDMA_GISR0_GIF8_Msk       (0x1UL << MDMA_GISR0_GIF8_Pos)               /*!< 0x00000100 */
+#define MDMA_GISR0_GIF8           MDMA_GISR0_GIF8_Msk                          /*!< Channel 8 global interrupt flag */
+#define MDMA_GISR0_GIF9_Pos       (9U)
+#define MDMA_GISR0_GIF9_Msk       (0x1UL << MDMA_GISR0_GIF9_Pos)               /*!< 0x00000200 */
+#define MDMA_GISR0_GIF9           MDMA_GISR0_GIF9_Msk                          /*!< Channel 9 global interrupt flag */
+#define MDMA_GISR0_GIF10_Pos      (10U)
+#define MDMA_GISR0_GIF10_Msk      (0x1UL << MDMA_GISR0_GIF10_Pos)              /*!< 0x00000400 */
+#define MDMA_GISR0_GIF10          MDMA_GISR0_GIF10_Msk                         /*!< Channel 10 global interrupt flag */
+#define MDMA_GISR0_GIF11_Pos      (11U)
+#define MDMA_GISR0_GIF11_Msk      (0x1UL << MDMA_GISR0_GIF11_Pos)              /*!< 0x00000800 */
+#define MDMA_GISR0_GIF11          MDMA_GISR0_GIF11_Msk                         /*!< Channel 11 global interrupt flag */
+#define MDMA_GISR0_GIF12_Pos      (12U)
+#define MDMA_GISR0_GIF12_Msk      (0x1UL << MDMA_GISR0_GIF12_Pos)              /*!< 0x00001000 */
+#define MDMA_GISR0_GIF12          MDMA_GISR0_GIF12_Msk                         /*!< Channel 12 global interrupt flag */
+#define MDMA_GISR0_GIF13_Pos      (13U)
+#define MDMA_GISR0_GIF13_Msk      (0x1UL << MDMA_GISR0_GIF13_Pos)              /*!< 0x00002000 */
+#define MDMA_GISR0_GIF13          MDMA_GISR0_GIF13_Msk                         /*!< Channel 13 global interrupt flag */
+#define MDMA_GISR0_GIF14_Pos      (14U)
+#define MDMA_GISR0_GIF14_Msk      (0x1UL << MDMA_GISR0_GIF14_Pos)              /*!< 0x00004000 */
+#define MDMA_GISR0_GIF14          MDMA_GISR0_GIF14_Msk                         /*!< Channel 14 global interrupt flag */
+#define MDMA_GISR0_GIF15_Pos      (15U)
+#define MDMA_GISR0_GIF15_Msk      (0x1UL << MDMA_GISR0_GIF15_Pos)              /*!< 0x00008000 */
+#define MDMA_GISR0_GIF15          MDMA_GISR0_GIF15_Msk                         /*!< Channel 15 global interrupt flag */
+
+/********************  Bit definition for MDMA_CxISR register  ****************/
+#define MDMA_CISR_TEIF_Pos        (0U)
+#define MDMA_CISR_TEIF_Msk        (0x1UL << MDMA_CISR_TEIF_Pos)                /*!< 0x00000001 */
+#define MDMA_CISR_TEIF            MDMA_CISR_TEIF_Msk                           /*!< Channel x transfer error interrupt flag */
+#define MDMA_CISR_CTCIF_Pos       (1U)
+#define MDMA_CISR_CTCIF_Msk       (0x1UL << MDMA_CISR_CTCIF_Pos)               /*!< 0x00000002 */
+#define MDMA_CISR_CTCIF           MDMA_CISR_CTCIF_Msk                          /*!< Channel x Channel Transfer Complete interrupt flag */
+#define MDMA_CISR_BRTIF_Pos       (2U)
+#define MDMA_CISR_BRTIF_Msk       (0x1UL << MDMA_CISR_BRTIF_Pos)               /*!< 0x00000004 */
+#define MDMA_CISR_BRTIF           MDMA_CISR_BRTIF_Msk                          /*!< Channel x block repeat transfer complete interrupt flag */
+#define MDMA_CISR_BTIF_Pos        (3U)
+#define MDMA_CISR_BTIF_Msk        (0x1UL << MDMA_CISR_BTIF_Pos)                /*!< 0x00000008 */
+#define MDMA_CISR_BTIF            MDMA_CISR_BTIF_Msk                           /*!< Channel x block transfer complete interrupt flag */
+#define MDMA_CISR_TCIF_Pos        (4U)
+#define MDMA_CISR_TCIF_Msk        (0x1UL << MDMA_CISR_TCIF_Pos)                /*!< 0x00000010 */
+#define MDMA_CISR_TCIF            MDMA_CISR_TCIF_Msk                           /*!< Channel x buffer transfer complete interrupt flag */
+#define MDMA_CISR_CRQA_Pos        (16U)
+#define MDMA_CISR_CRQA_Msk        (0x1UL << MDMA_CISR_CRQA_Pos)                /*!< 0x00010000 */
+#define MDMA_CISR_CRQA            MDMA_CISR_CRQA_Msk                           /*!< Channel x ReQest Active flag */
+
+/********************  Bit definition for MDMA_CxIFCR register  ****************/
+#define MDMA_CIFCR_CTEIF_Pos      (0U)
+#define MDMA_CIFCR_CTEIF_Msk      (0x1UL << MDMA_CIFCR_CTEIF_Pos)              /*!< 0x00000001 */
+#define MDMA_CIFCR_CTEIF          MDMA_CIFCR_CTEIF_Msk                         /*!< Channel x clear transfer error interrupt flag */
+#define MDMA_CIFCR_CCTCIF_Pos     (1U)
+#define MDMA_CIFCR_CCTCIF_Msk     (0x1UL << MDMA_CIFCR_CCTCIF_Pos)             /*!< 0x00000002 */
+#define MDMA_CIFCR_CCTCIF         MDMA_CIFCR_CCTCIF_Msk                        /*!< Clear Channel transfer complete interrupt flag for channel x */
+#define MDMA_CIFCR_CBRTIF_Pos     (2U)
+#define MDMA_CIFCR_CBRTIF_Msk     (0x1UL << MDMA_CIFCR_CBRTIF_Pos)             /*!< 0x00000004 */
+#define MDMA_CIFCR_CBRTIF         MDMA_CIFCR_CBRTIF_Msk                        /*!< Channel x clear block repeat transfer complete interrupt flag */
+#define MDMA_CIFCR_CBTIF_Pos      (3U)
+#define MDMA_CIFCR_CBTIF_Msk      (0x1UL << MDMA_CIFCR_CBTIF_Pos)              /*!< 0x00000008 */
+#define MDMA_CIFCR_CBTIF          MDMA_CIFCR_CBTIF_Msk                         /*!< Channel x Clear block transfer complete interrupt flag */
+#define MDMA_CIFCR_CLTCIF_Pos     (4U)
+#define MDMA_CIFCR_CLTCIF_Msk     (0x1UL << MDMA_CIFCR_CLTCIF_Pos)             /*!< 0x00000010 */
+#define MDMA_CIFCR_CLTCIF         MDMA_CIFCR_CLTCIF_Msk                        /*!< CLear Transfer buffer Complete Interrupt Flag for channel */
+
+/********************  Bit definition for MDMA_CxESR register  ****************/
+#define MDMA_CESR_TEA_Pos         (0U)
+#define MDMA_CESR_TEA_Msk         (0x7FUL << MDMA_CESR_TEA_Pos)                /*!< 0x0000007F */
+#define MDMA_CESR_TEA             MDMA_CESR_TEA_Msk                            /*!< Transfer Error Address */
+#define MDMA_CESR_TED_Pos         (7U)
+#define MDMA_CESR_TED_Msk         (0x1UL << MDMA_CESR_TED_Pos)                 /*!< 0x00000080 */
+#define MDMA_CESR_TED             MDMA_CESR_TED_Msk                            /*!< Transfer Error Direction */
+#define MDMA_CESR_TELD_Pos        (8U)
+#define MDMA_CESR_TELD_Msk        (0x1UL << MDMA_CESR_TELD_Pos)                /*!< 0x00000100 */
+#define MDMA_CESR_TELD            MDMA_CESR_TELD_Msk                           /*!< Transfer Error Link Data */
+#define MDMA_CESR_TEMD_Pos        (9U)
+#define MDMA_CESR_TEMD_Msk        (0x1UL << MDMA_CESR_TEMD_Pos)                /*!< 0x00000200 */
+#define MDMA_CESR_TEMD            MDMA_CESR_TEMD_Msk                           /*!< Transfer Error Mask Data */
+#define MDMA_CESR_ASE_Pos         (10U)
+#define MDMA_CESR_ASE_Msk         (0x1UL << MDMA_CESR_ASE_Pos)                 /*!< 0x00000400 */
+#define MDMA_CESR_ASE             MDMA_CESR_ASE_Msk                            /*!< Address/Size Error       */
+#define MDMA_CESR_BSE_Pos         (11U)
+#define MDMA_CESR_BSE_Msk         (0x1UL << MDMA_CESR_BSE_Pos)                 /*!< 0x00000800 */
+#define MDMA_CESR_BSE             MDMA_CESR_BSE_Msk                            /*!< Block Size Error         */
+
+/********************  Bit definition for MDMA_CxCR register  ****************/
+#define MDMA_CCR_EN_Pos           (0U)
+#define MDMA_CCR_EN_Msk           (0x1UL << MDMA_CCR_EN_Pos)                   /*!< 0x00000001 */
+#define MDMA_CCR_EN               MDMA_CCR_EN_Msk                              /*!< Channel enable / flag channel ready when read low */
+#define MDMA_CCR_TEIE_Pos         (1U)
+#define MDMA_CCR_TEIE_Msk         (0x1UL << MDMA_CCR_TEIE_Pos)                 /*!< 0x00000002 */
+#define MDMA_CCR_TEIE             MDMA_CCR_TEIE_Msk                            /*!< Transfer error interrupt enable */
+#define MDMA_CCR_CTCIE_Pos        (2U)
+#define MDMA_CCR_CTCIE_Msk        (0x1UL << MDMA_CCR_CTCIE_Pos)                /*!< 0x00000004 */
+#define MDMA_CCR_CTCIE            MDMA_CCR_CTCIE_Msk                           /*!< Channel Transfer Complete interrupt enable */
+#define MDMA_CCR_BRTIE_Pos        (3U)
+#define MDMA_CCR_BRTIE_Msk        (0x1UL << MDMA_CCR_BRTIE_Pos)                /*!< 0x00000008 */
+#define MDMA_CCR_BRTIE            MDMA_CCR_BRTIE_Msk                           /*!< Block Repeat transfer interrupt enable */
+#define MDMA_CCR_BTIE_Pos         (4U)
+#define MDMA_CCR_BTIE_Msk         (0x1UL << MDMA_CCR_BTIE_Pos)                 /*!< 0x00000010 */
+#define MDMA_CCR_BTIE             MDMA_CCR_BTIE_Msk                            /*!< Block Transfer interrupt enable */
+#define MDMA_CCR_TCIE_Pos         (5U)
+#define MDMA_CCR_TCIE_Msk         (0x1UL << MDMA_CCR_TCIE_Pos)                 /*!< 0x00000020 */
+#define MDMA_CCR_TCIE             MDMA_CCR_TCIE_Msk                            /*!< buffer Transfer Complete interrupt enable */
+#define MDMA_CCR_PL_Pos           (6U)
+#define MDMA_CCR_PL_Msk           (0x3UL << MDMA_CCR_PL_Pos)                   /*!< 0x000000C0 */
+#define MDMA_CCR_PL               MDMA_CCR_PL_Msk                              /*!< Priority level */
+#define MDMA_CCR_PL_0             (0x1UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000040 */
+#define MDMA_CCR_PL_1             (0x2UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000080 */
+#define MDMA_CCR_BEX_Pos          (12U)
+#define MDMA_CCR_BEX_Msk          (0x1UL << MDMA_CCR_BEX_Pos)                  /*!< 0x00001000 */
+#define MDMA_CCR_BEX              MDMA_CCR_BEX_Msk                             /*!< Byte Endianess eXchange */
+#define MDMA_CCR_HEX_Pos          (13U)
+#define MDMA_CCR_HEX_Msk          (0x1UL << MDMA_CCR_HEX_Pos)                  /*!< 0x00002000 */
+#define MDMA_CCR_HEX              MDMA_CCR_HEX_Msk                             /*!< Half word Endianess eXchange */
+#define MDMA_CCR_WEX_Pos          (14U)
+#define MDMA_CCR_WEX_Msk          (0x1UL << MDMA_CCR_WEX_Pos)                  /*!< 0x00004000 */
+#define MDMA_CCR_WEX              MDMA_CCR_WEX_Msk                             /*!< Word Endianess eXchange */
+#define MDMA_CCR_SWRQ_Pos         (16U)
+#define MDMA_CCR_SWRQ_Msk         (0x1UL << MDMA_CCR_SWRQ_Pos)                 /*!< 0x00010000 */
+#define MDMA_CCR_SWRQ             MDMA_CCR_SWRQ_Msk                            /*!< SW ReQuest */
+
+/********************  Bit definition for MDMA_CxTCR register  ****************/
+#define MDMA_CTCR_SINC_Pos        (0U)
+#define MDMA_CTCR_SINC_Msk        (0x3UL << MDMA_CTCR_SINC_Pos)                /*!< 0x00000003 */
+#define MDMA_CTCR_SINC            MDMA_CTCR_SINC_Msk                           /*!< Source increment mode */
+#define MDMA_CTCR_SINC_0          (0x1UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000001 */
+#define MDMA_CTCR_SINC_1          (0x2UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000002 */
+#define MDMA_CTCR_DINC_Pos        (2U)
+#define MDMA_CTCR_DINC_Msk        (0x3UL << MDMA_CTCR_DINC_Pos)                /*!< 0x0000000C */
+#define MDMA_CTCR_DINC            MDMA_CTCR_DINC_Msk                           /*!< Source increment mode */
+#define MDMA_CTCR_DINC_0          (0x1UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000004 */
+#define MDMA_CTCR_DINC_1          (0x2UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000008 */
+#define MDMA_CTCR_SSIZE_Pos       (4U)
+#define MDMA_CTCR_SSIZE_Msk       (0x3UL << MDMA_CTCR_SSIZE_Pos)               /*!< 0x00000030 */
+#define MDMA_CTCR_SSIZE           MDMA_CTCR_SSIZE_Msk                          /*!< Source data size */
+#define MDMA_CTCR_SSIZE_0         (0x1UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000010 */
+#define MDMA_CTCR_SSIZE_1         (0x2UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000020 */
+#define MDMA_CTCR_DSIZE_Pos       (6U)
+#define MDMA_CTCR_DSIZE_Msk       (0x3UL << MDMA_CTCR_DSIZE_Pos)               /*!< 0x000000C0 */
+#define MDMA_CTCR_DSIZE           MDMA_CTCR_DSIZE_Msk                          /*!< Destination data size */
+#define MDMA_CTCR_DSIZE_0         (0x1UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000040 */
+#define MDMA_CTCR_DSIZE_1         (0x2UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000080 */
+#define MDMA_CTCR_SINCOS_Pos      (8U)
+#define MDMA_CTCR_SINCOS_Msk      (0x3UL << MDMA_CTCR_SINCOS_Pos)              /*!< 0x00000300 */
+#define MDMA_CTCR_SINCOS          MDMA_CTCR_SINCOS_Msk                         /*!< Source increment offset size */
+#define MDMA_CTCR_SINCOS_0        (0x1UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000100 */
+#define MDMA_CTCR_SINCOS_1        (0x2UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000200 */
+#define MDMA_CTCR_DINCOS_Pos      (10U)
+#define MDMA_CTCR_DINCOS_Msk      (0x3UL << MDMA_CTCR_DINCOS_Pos)              /*!< 0x00000C00 */
+#define MDMA_CTCR_DINCOS          MDMA_CTCR_DINCOS_Msk                         /*!< Destination increment offset size */
+#define MDMA_CTCR_DINCOS_0        (0x1UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000400 */
+#define MDMA_CTCR_DINCOS_1        (0x2UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000800 */
+#define MDMA_CTCR_SBURST_Pos      (12U)
+#define MDMA_CTCR_SBURST_Msk      (0x7UL << MDMA_CTCR_SBURST_Pos)              /*!< 0x00007000 */
+#define MDMA_CTCR_SBURST          MDMA_CTCR_SBURST_Msk                         /*!< Source burst transfer configuration */
+#define MDMA_CTCR_SBURST_0        (0x1UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00001000 */
+#define MDMA_CTCR_SBURST_1        (0x2UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00002000 */
+#define MDMA_CTCR_SBURST_2        (0x4UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00004000 */
+#define MDMA_CTCR_DBURST_Pos      (15U)
+#define MDMA_CTCR_DBURST_Msk      (0x7UL << MDMA_CTCR_DBURST_Pos)              /*!< 0x00038000 */
+#define MDMA_CTCR_DBURST          MDMA_CTCR_DBURST_Msk                         /*!< Destination burst transfer configuration */
+#define MDMA_CTCR_DBURST_0        (0x1UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00008000 */
+#define MDMA_CTCR_DBURST_1        (0x2UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00010000 */
+#define MDMA_CTCR_DBURST_2        (0x4UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00020000 */
+#define MDMA_CTCR_TLEN_Pos        (18U)
+#define MDMA_CTCR_TLEN_Msk        (0x7FUL << MDMA_CTCR_TLEN_Pos)               /*!< 0x01FC0000 */
+#define MDMA_CTCR_TLEN            MDMA_CTCR_TLEN_Msk                           /*!< buffer Transfer Length (number of bytes - 1) */
+#define MDMA_CTCR_PKE_Pos         (25U)
+#define MDMA_CTCR_PKE_Msk         (0x1UL << MDMA_CTCR_PKE_Pos)                 /*!< 0x02000000 */
+#define MDMA_CTCR_PKE             MDMA_CTCR_PKE_Msk                            /*!< PacK Enable */
+#define MDMA_CTCR_PAM_Pos         (26U)
+#define MDMA_CTCR_PAM_Msk         (0x3UL << MDMA_CTCR_PAM_Pos)                 /*!< 0x0C000000 */
+#define MDMA_CTCR_PAM             MDMA_CTCR_PAM_Msk                            /*!< Padding/Alignement Mode */
+#define MDMA_CTCR_PAM_0           (0x1UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x4000000 */
+#define MDMA_CTCR_PAM_1           (0x2UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x8000000 */
+#define MDMA_CTCR_TRGM_Pos        (28U)
+#define MDMA_CTCR_TRGM_Msk        (0x3UL << MDMA_CTCR_TRGM_Pos)                /*!< 0x30000000 */
+#define MDMA_CTCR_TRGM            MDMA_CTCR_TRGM_Msk                           /*!< Trigger Mode */
+#define MDMA_CTCR_TRGM_0          (0x1UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x10000000 */
+#define MDMA_CTCR_TRGM_1          (0x2UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x20000000 */
+#define MDMA_CTCR_SWRM_Pos        (30U)
+#define MDMA_CTCR_SWRM_Msk        (0x1UL << MDMA_CTCR_SWRM_Pos)                /*!< 0x40000000 */
+#define MDMA_CTCR_SWRM            MDMA_CTCR_SWRM_Msk                           /*!< SW Request Mode */
+#define MDMA_CTCR_BWM_Pos         (31U)
+#define MDMA_CTCR_BWM_Msk         (0x1UL << MDMA_CTCR_BWM_Pos)                 /*!< 0x80000000 */
+#define MDMA_CTCR_BWM             MDMA_CTCR_BWM_Msk                            /*!< Bufferable Write Mode */
+
+/********************  Bit definition for MDMA_CxBNDTR register  ****************/
+#define MDMA_CBNDTR_BNDT_Pos      (0U)
+#define MDMA_CBNDTR_BNDT_Msk      (0x1FFFFUL << MDMA_CBNDTR_BNDT_Pos)          /*!< 0x0001FFFF */
+#define MDMA_CBNDTR_BNDT          MDMA_CBNDTR_BNDT_Msk                         /*!< Block Number of data bytes to transfer */
+#define MDMA_CBNDTR_BRSUM_Pos     (18U)
+#define MDMA_CBNDTR_BRSUM_Msk     (0x1UL << MDMA_CBNDTR_BRSUM_Pos)             /*!< 0x00040000 */
+#define MDMA_CBNDTR_BRSUM         MDMA_CBNDTR_BRSUM_Msk                        /*!< Block Repeat Source address Update Mode */
+#define MDMA_CBNDTR_BRDUM_Pos     (19U)
+#define MDMA_CBNDTR_BRDUM_Msk     (0x1UL << MDMA_CBNDTR_BRDUM_Pos)             /*!< 0x00080000 */
+#define MDMA_CBNDTR_BRDUM         MDMA_CBNDTR_BRDUM_Msk                        /*!< Block Repeat Destination address Update Mode */
+#define MDMA_CBNDTR_BRC_Pos       (20U)
+#define MDMA_CBNDTR_BRC_Msk       (0xFFFUL << MDMA_CBNDTR_BRC_Pos)             /*!< 0xFFF00000 */
+#define MDMA_CBNDTR_BRC           MDMA_CBNDTR_BRC_Msk                          /*!< Block Repeat Count */
+
+/********************  Bit definition for MDMA_CxSAR register  ****************/
+#define MDMA_CSAR_SAR_Pos         (0U)
+#define MDMA_CSAR_SAR_Msk         (0xFFFFFFFFUL << MDMA_CSAR_SAR_Pos)          /*!< 0xFFFFFFFF */
+#define MDMA_CSAR_SAR             MDMA_CSAR_SAR_Msk                            /*!< Source address */
+
+/********************  Bit definition for MDMA_CxDAR register  ****************/
+#define MDMA_CDAR_DAR_Pos         (0U)
+#define MDMA_CDAR_DAR_Msk         (0xFFFFFFFFUL << MDMA_CDAR_DAR_Pos)          /*!< 0xFFFFFFFF */
+#define MDMA_CDAR_DAR             MDMA_CDAR_DAR_Msk                            /*!< Destination address */
+
+/********************  Bit definition for MDMA_CxBRUR  ************************/
+#define MDMA_CBRUR_SUV_Pos        (0U)
+#define MDMA_CBRUR_SUV_Msk        (0xFFFFUL << MDMA_CBRUR_SUV_Pos)             /*!< 0x0000FFFF */
+#define MDMA_CBRUR_SUV            MDMA_CBRUR_SUV_Msk                           /*!< Source address Update Value */
+#define MDMA_CBRUR_DUV_Pos        (16U)
+#define MDMA_CBRUR_DUV_Msk        (0xFFFFUL << MDMA_CBRUR_DUV_Pos)             /*!< 0xFFFF0000 */
+#define MDMA_CBRUR_DUV            MDMA_CBRUR_DUV_Msk                           /*!< Destination address Update Value */
+
+/********************  Bit definition for MDMA_CxLAR  *************************/
+#define MDMA_CLAR_LAR_Pos         (0U)
+#define MDMA_CLAR_LAR_Msk         (0xFFFFFFFFUL << MDMA_CLAR_LAR_Pos)          /*!< 0xFFFFFFFF */
+#define MDMA_CLAR_LAR             MDMA_CLAR_LAR_Msk                            /*!< Link Address Register */
+
+/********************  Bit definition for MDMA_CxTBR)  ************************/
+#define MDMA_CTBR_TSEL_Pos        (0U)
+#define MDMA_CTBR_TSEL_Msk        (0xFFUL << MDMA_CTBR_TSEL_Pos)               /*!< 0x000000FF */
+#define MDMA_CTBR_TSEL            MDMA_CTBR_TSEL_Msk                           /*!< Trigger SELection */
+#define MDMA_CTBR_SBUS_Pos        (16U)
+#define MDMA_CTBR_SBUS_Msk        (0x1UL << MDMA_CTBR_SBUS_Pos)                /*!< 0x00010000 */
+#define MDMA_CTBR_SBUS            MDMA_CTBR_SBUS_Msk                           /*!< Source BUS select */
+#define MDMA_CTBR_DBUS_Pos        (17U)
+#define MDMA_CTBR_DBUS_Msk        (0x1UL << MDMA_CTBR_DBUS_Pos)                /*!< 0x00020000 */
+#define MDMA_CTBR_DBUS            MDMA_CTBR_DBUS_Msk                           /*!< Destination BUS select */
+
+/********************  Bit definition for MDMA_CxMAR)  ************************/
+#define MDMA_CMAR_MAR_Pos         (0U)
+#define MDMA_CMAR_MAR_Msk         (0xFFFFFFFFUL << MDMA_CMAR_MAR_Pos)          /*!< 0xFFFFFFFF */
+#define MDMA_CMAR_MAR             MDMA_CMAR_MAR_Msk                            /*!< Mask address */
+
+/********************  Bit definition for MDMA_CxMDR)  ************************/
+#define MDMA_CMDR_MDR_Pos         (0U)
+#define MDMA_CMDR_MDR_Msk         (0xFFFFFFFFUL << MDMA_CMDR_MDR_Pos)          /*!< 0xFFFFFFFF */
+#define MDMA_CMDR_MDR             MDMA_CMDR_MDR_Msk                            /*!< Mask Data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Operational Amplifier (OPAMP)                      */
+/*                                                                            */
+/******************************************************************************/
+/*********************  Bit definition for OPAMPx_CSR register  ***************/
+#define OPAMP_CSR_OPAMPxEN_Pos           (0U)
+#define OPAMP_CSR_OPAMPxEN_Msk           (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)     /*!< 0x00000001 */
+#define OPAMP_CSR_OPAMPxEN               OPAMP_CSR_OPAMPxEN_Msk                /*!< OPAMP enable */
+#define OPAMP_CSR_FORCEVP_Pos            (1U)
+#define OPAMP_CSR_FORCEVP_Msk            (0x1UL << OPAMP_CSR_FORCEVP_Pos)      /*!< 0x00000002 */
+#define OPAMP_CSR_FORCEVP                OPAMP_CSR_FORCEVP_Msk                 /*!< Force internal reference on VP */
+
+#define OPAMP_CSR_VPSEL_Pos              (2U)
+#define OPAMP_CSR_VPSEL_Msk              (0x3UL << OPAMP_CSR_VPSEL_Pos)        /*!< 0x0000000C */
+#define OPAMP_CSR_VPSEL                  OPAMP_CSR_VPSEL_Msk                   /*!< Non inverted input selection */
+#define OPAMP_CSR_VPSEL_0                (0x1UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000004 */
+#define OPAMP_CSR_VPSEL_1                (0x2UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000008 */
+
+#define OPAMP_CSR_VMSEL_Pos              (5U)
+#define OPAMP_CSR_VMSEL_Msk              (0x3UL << OPAMP_CSR_VMSEL_Pos)        /*!< 0x00000060 */
+#define OPAMP_CSR_VMSEL                  OPAMP_CSR_VMSEL_Msk                   /*!< Inverting input selection */
+#define OPAMP_CSR_VMSEL_0                (0x1UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000020 */
+#define OPAMP_CSR_VMSEL_1                (0x2UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000040 */
+
+#define OPAMP_CSR_OPAHSM_Pos             (8U)
+#define OPAMP_CSR_OPAHSM_Msk             (0x1UL << OPAMP_CSR_OPAHSM_Pos)       /*!< 0x00000100 */
+#define OPAMP_CSR_OPAHSM                 OPAMP_CSR_OPAHSM_Msk                  /*!< Operational amplifier high speed mode */
+#define OPAMP_CSR_CALON_Pos              (11U)
+#define OPAMP_CSR_CALON_Msk              (0x1UL << OPAMP_CSR_CALON_Pos)        /*!< 0x00000800 */
+#define OPAMP_CSR_CALON                  OPAMP_CSR_CALON_Msk                   /*!< Calibration mode enable */
+
+#define OPAMP_CSR_CALSEL_Pos             (12U)
+#define OPAMP_CSR_CALSEL_Msk             (0x3UL << OPAMP_CSR_CALSEL_Pos)       /*!< 0x00003000 */
+#define OPAMP_CSR_CALSEL                 OPAMP_CSR_CALSEL_Msk                  /*!< Calibration selection */
+#define OPAMP_CSR_CALSEL_0               (0x1UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00001000 */
+#define OPAMP_CSR_CALSEL_1               (0x2UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00002000 */
+
+#define OPAMP_CSR_PGGAIN_Pos             (14U)
+#define OPAMP_CSR_PGGAIN_Msk             (0xFUL << OPAMP_CSR_PGGAIN_Pos)       /*!< 0x0003C000 */
+#define OPAMP_CSR_PGGAIN                 OPAMP_CSR_PGGAIN_Msk                  /*!< Operational amplifier Programmable amplifier gain value */
+#define OPAMP_CSR_PGGAIN_0               (0x1UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00004000 */
+#define OPAMP_CSR_PGGAIN_1               (0x2UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00008000 */
+#define OPAMP_CSR_PGGAIN_2               (0x4UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00010000 */
+#define OPAMP_CSR_PGGAIN_3               (0x8UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00020000 */
+
+#define OPAMP_CSR_USERTRIM_Pos           (18U)
+#define OPAMP_CSR_USERTRIM_Msk           (0x1UL << OPAMP_CSR_USERTRIM_Pos)     /*!< 0x00040000 */
+#define OPAMP_CSR_USERTRIM               OPAMP_CSR_USERTRIM_Msk                /*!< User trimming enable */
+#define OPAMP_CSR_TSTREF_Pos             (29U)
+#define OPAMP_CSR_TSTREF_Msk             (0x1UL << OPAMP_CSR_TSTREF_Pos)       /*!< 0x20000000 */
+#define OPAMP_CSR_TSTREF                 OPAMP_CSR_TSTREF_Msk                  /*!< OpAmp calibration reference voltage output control */
+#define OPAMP_CSR_CALOUT_Pos             (30U)
+#define OPAMP_CSR_CALOUT_Msk             (0x1UL << OPAMP_CSR_CALOUT_Pos)       /*!< 0x40000000 */
+#define OPAMP_CSR_CALOUT                 OPAMP_CSR_CALOUT_Msk                  /*!< Operational amplifier calibration output */
+
+/*********************  Bit definition for OPAMP1_CSR register  ***************/
+#define OPAMP1_CSR_OPAEN_Pos              (0U)
+#define OPAMP1_CSR_OPAEN_Msk              (0x1UL << OPAMP1_CSR_OPAEN_Pos)      /*!< 0x00000001 */
+#define OPAMP1_CSR_OPAEN                  OPAMP1_CSR_OPAEN_Msk                 /*!< Operational amplifier1 Enable */
+#define OPAMP1_CSR_FORCEVP_Pos            (1U)
+#define OPAMP1_CSR_FORCEVP_Msk            (0x1UL << OPAMP1_CSR_FORCEVP_Pos)    /*!< 0x00000002 */
+#define OPAMP1_CSR_FORCEVP                OPAMP1_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */
+
+#define OPAMP1_CSR_VPSEL_Pos              (2U)
+#define OPAMP1_CSR_VPSEL_Msk              (0x3UL << OPAMP1_CSR_VPSEL_Pos)      /*!< 0x0000000C */
+#define OPAMP1_CSR_VPSEL                  OPAMP1_CSR_VPSEL_Msk                 /*!< Non inverted input selection */
+#define OPAMP1_CSR_VPSEL_0                (0x1UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000004 */
+#define OPAMP1_CSR_VPSEL_1                (0x2UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000008 */
+
+#define OPAMP1_CSR_VMSEL_Pos              (5U)
+#define OPAMP1_CSR_VMSEL_Msk              (0x3UL << OPAMP1_CSR_VMSEL_Pos)      /*!< 0x00000060 */
+#define OPAMP1_CSR_VMSEL                  OPAMP1_CSR_VMSEL_Msk                 /*!< Inverting input selection */
+#define OPAMP1_CSR_VMSEL_0                (0x1UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000020 */
+#define OPAMP1_CSR_VMSEL_1                (0x2UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000040 */
+
+#define OPAMP1_CSR_OPAHSM_Pos             (8U)
+#define OPAMP1_CSR_OPAHSM_Msk             (0x1UL << OPAMP1_CSR_OPAHSM_Pos)     /*!< 0x00000100 */
+#define OPAMP1_CSR_OPAHSM                 OPAMP1_CSR_OPAHSM_Msk                /*!< Operational amplifier1 high speed mode */
+#define OPAMP1_CSR_CALON_Pos              (11U)
+#define OPAMP1_CSR_CALON_Msk              (0x1UL << OPAMP1_CSR_CALON_Pos)      /*!< 0x00000800 */
+#define OPAMP1_CSR_CALON                  OPAMP1_CSR_CALON_Msk                 /*!< Calibration mode enable */
+
+#define OPAMP1_CSR_CALSEL_Pos             (12U)
+#define OPAMP1_CSR_CALSEL_Msk             (0x3UL << OPAMP1_CSR_CALSEL_Pos)     /*!< 0x00003000 */
+#define OPAMP1_CSR_CALSEL                 OPAMP1_CSR_CALSEL_Msk                /*!< Calibration selection */
+#define OPAMP1_CSR_CALSEL_0               (0x1UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00001000 */
+#define OPAMP1_CSR_CALSEL_1               (0x2UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00002000 */
+
+#define OPAMP1_CSR_PGGAIN_Pos             (14U)
+#define OPAMP1_CSR_PGGAIN_Msk             (0xFUL << OPAMP1_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */
+#define OPAMP1_CSR_PGGAIN                 OPAMP1_CSR_PGGAIN_Msk                /*!< Operational amplifier1 Programmable amplifier gain value */
+#define OPAMP1_CSR_PGGAIN_0               (0x1UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00004000 */
+#define OPAMP1_CSR_PGGAIN_1               (0x2UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00008000 */
+#define OPAMP1_CSR_PGGAIN_2               (0x4UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00010000 */
+#define OPAMP1_CSR_PGGAIN_3               (0x8UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00020000 */
+
+#define OPAMP1_CSR_USERTRIM_Pos           (18U)
+#define OPAMP1_CSR_USERTRIM_Msk           (0x1UL << OPAMP1_CSR_USERTRIM_Pos)   /*!< 0x00040000 */
+#define OPAMP1_CSR_USERTRIM               OPAMP1_CSR_USERTRIM_Msk              /*!< User trimming enable */
+#define OPAMP1_CSR_TSTREF_Pos             (29U)
+#define OPAMP1_CSR_TSTREF_Msk             (0x1UL << OPAMP1_CSR_TSTREF_Pos)     /*!< 0x20000000 */
+#define OPAMP1_CSR_TSTREF                 OPAMP1_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */
+#define OPAMP1_CSR_CALOUT_Pos             (30U)
+#define OPAMP1_CSR_CALOUT_Msk             (0x1UL << OPAMP1_CSR_CALOUT_Pos)     /*!< 0x40000000 */
+#define OPAMP1_CSR_CALOUT                 OPAMP1_CSR_CALOUT_Msk                /*!< Operational amplifier1 calibration output */
+
+/*********************  Bit definition for OPAMP2_CSR register  ***************/
+#define OPAMP2_CSR_OPAEN_Pos              (0U)
+#define OPAMP2_CSR_OPAEN_Msk              (0x1UL << OPAMP2_CSR_OPAEN_Pos)      /*!< 0x00000001 */
+#define OPAMP2_CSR_OPAEN                  OPAMP2_CSR_OPAEN_Msk                 /*!< Operational amplifier2 Enable */
+#define OPAMP2_CSR_FORCEVP_Pos            (1U)
+#define OPAMP2_CSR_FORCEVP_Msk            (0x1UL << OPAMP2_CSR_FORCEVP_Pos)    /*!< 0x00000002 */
+#define OPAMP2_CSR_FORCEVP                OPAMP2_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */
+
+#define OPAMP2_CSR_VPSEL_Pos              (2U)
+#define OPAMP2_CSR_VPSEL_Msk              (0x3UL << OPAMP2_CSR_VPSEL_Pos)      /*!< 0x0000000C */
+#define OPAMP2_CSR_VPSEL                  OPAMP2_CSR_VPSEL_Msk                 /*!< Non inverted input selection */
+#define OPAMP2_CSR_VPSEL_0                (0x1UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000004 */
+#define OPAMP2_CSR_VPSEL_1                (0x2UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000008 */
+
+#define OPAMP2_CSR_VMSEL_Pos              (5U)
+#define OPAMP2_CSR_VMSEL_Msk              (0x3UL << OPAMP2_CSR_VMSEL_Pos)      /*!< 0x00000060 */
+#define OPAMP2_CSR_VMSEL                  OPAMP2_CSR_VMSEL_Msk                 /*!< Inverting input selection */
+#define OPAMP2_CSR_VMSEL_0                (0x1UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000020 */
+#define OPAMP2_CSR_VMSEL_1                (0x2UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000040 */
+
+#define OPAMP2_CSR_OPAHSM_Pos             (8U)
+#define OPAMP2_CSR_OPAHSM_Msk             (0x1UL << OPAMP2_CSR_OPAHSM_Pos)     /*!< 0x00000100 */
+#define OPAMP2_CSR_OPAHSM                 OPAMP2_CSR_OPAHSM_Msk                /*!< Operational amplifier2 high speed mode */
+#define OPAMP2_CSR_CALON_Pos              (11U)
+#define OPAMP2_CSR_CALON_Msk              (0x1UL << OPAMP2_CSR_CALON_Pos)      /*!< 0x00000800 */
+#define OPAMP2_CSR_CALON                  OPAMP2_CSR_CALON_Msk                 /*!< Calibration mode enable */
+
+#define OPAMP2_CSR_CALSEL_Pos             (12U)
+#define OPAMP2_CSR_CALSEL_Msk             (0x3UL << OPAMP2_CSR_CALSEL_Pos)     /*!< 0x00003000 */
+#define OPAMP2_CSR_CALSEL                 OPAMP2_CSR_CALSEL_Msk                /*!< Calibration selection */
+#define OPAMP2_CSR_CALSEL_0               (0x1UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00001000 */
+#define OPAMP2_CSR_CALSEL_1               (0x2UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00002000 */
+
+#define OPAMP2_CSR_PGGAIN_Pos             (14U)
+#define OPAMP2_CSR_PGGAIN_Msk             (0xFUL << OPAMP2_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */
+#define OPAMP2_CSR_PGGAIN                 OPAMP2_CSR_PGGAIN_Msk                /*!< Operational amplifier2 Programmable amplifier gain value */
+#define OPAMP2_CSR_PGGAIN_0               (0x1UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00004000 */
+#define OPAMP2_CSR_PGGAIN_1               (0x2UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00008000 */
+#define OPAMP2_CSR_PGGAIN_2               (0x4UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00010000 */
+#define OPAMP2_CSR_PGGAIN_3               (0x8UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00020000 */
+
+#define OPAMP2_CSR_USERTRIM_Pos           (18U)
+#define OPAMP2_CSR_USERTRIM_Msk           (0x1UL << OPAMP2_CSR_USERTRIM_Pos)   /*!< 0x00040000 */
+#define OPAMP2_CSR_USERTRIM               OPAMP2_CSR_USERTRIM_Msk              /*!< User trimming enable */
+#define OPAMP2_CSR_TSTREF_Pos             (29U)
+#define OPAMP2_CSR_TSTREF_Msk             (0x1UL << OPAMP2_CSR_TSTREF_Pos)     /*!< 0x20000000 */
+#define OPAMP2_CSR_TSTREF                 OPAMP2_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */
+#define OPAMP2_CSR_CALOUT_Pos             (30U)
+#define OPAMP2_CSR_CALOUT_Msk             (0x1UL << OPAMP2_CSR_CALOUT_Pos)     /*!< 0x40000000 */
+#define OPAMP2_CSR_CALOUT                 OPAMP2_CSR_CALOUT_Msk                /*!< Operational amplifier2 calibration output */
+
+/*******************  Bit definition for OPAMP_OTR register  ******************/
+#define OPAMP_OTR_TRIMOFFSETN_Pos        (0U)
+#define OPAMP_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP_OTR_TRIMOFFSETN            OPAMP_OTR_TRIMOFFSETN_Msk             /*!< Trim for NMOS differential pairs */
+#define OPAMP_OTR_TRIMOFFSETP_Pos        (8U)
+#define OPAMP_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP_OTR_TRIMOFFSETP            OPAMP_OTR_TRIMOFFSETP_Msk             /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP1_OTR register  ******************/
+#define OPAMP1_OTR_TRIMOFFSETN_Pos        (0U)
+#define OPAMP1_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP1_OTR_TRIMOFFSETN            OPAMP1_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */
+#define OPAMP1_OTR_TRIMOFFSETP_Pos        (8U)
+#define OPAMP1_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP1_OTR_TRIMOFFSETP            OPAMP1_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP2_OTR register  ******************/
+#define OPAMP2_OTR_TRIMOFFSETN_Pos        (0U)
+#define OPAMP2_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP2_OTR_TRIMOFFSETN            OPAMP2_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */
+#define OPAMP2_OTR_TRIMOFFSETP_Pos        (8U)
+#define OPAMP2_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP2_OTR_TRIMOFFSETP            OPAMP2_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP_HSOTR register  ****************/
+#define OPAMP_HSOTR_TRIMHSOFFSETN_Pos    (0U)
+#define OPAMP_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP_HSOTR_TRIMHSOFFSETN        OPAMP_HSOTR_TRIMHSOFFSETN_Msk         /*!< Trim for NMOS differential pairs */
+#define OPAMP_HSOTR_TRIMHSOFFSETP_Pos    (8U)
+#define OPAMP_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP_HSOTR_TRIMHSOFFSETP        OPAMP_HSOTR_TRIMHSOFFSETP_Msk         /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP1_HSOTR register  ****************/
+#define OPAMP1_HSOTR_TRIMHSOFFSETN_Pos    (0U)
+#define OPAMP1_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP1_HSOTR_TRIMHSOFFSETN        OPAMP1_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */
+#define OPAMP1_HSOTR_TRIMHSOFFSETP_Pos    (8U)
+#define OPAMP1_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP1_HSOTR_TRIMHSOFFSETP        OPAMP1_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP2_HSOTR register  ****************/
+#define OPAMP2_HSOTR_TRIMHSOFFSETN_Pos    (0U)
+#define OPAMP2_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP2_HSOTR_TRIMHSOFFSETN        OPAMP2_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */
+#define OPAMP2_HSOTR_TRIMHSOFFSETP_Pos    (8U)
+#define OPAMP2_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP2_HSOTR_TRIMHSOFFSETP        OPAMP2_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             Power Control                                  */
+/*                                                                            */
+/******************************************************************************/
+/*************************  NUMBER OF POWER DOMAINS  **************************/
+#define POWER_DOMAINS_NUMBER           3U                                      /*!< 3 Domains */
+
+/********************  Bit definition for PWR_CR1 register  *******************/
+#define PWR_CR1_ALS_Pos                (17U)
+#define PWR_CR1_ALS_Msk                (0x3UL << PWR_CR1_ALS_Pos)              /*!< 0x00060000 */
+#define PWR_CR1_ALS                    PWR_CR1_ALS_Msk                         /*!< Analog Voltage Detector level selection */
+#define PWR_CR1_ALS_0                  (0x1UL << PWR_CR1_ALS_Pos)              /*!< 0x00020000 */
+#define PWR_CR1_ALS_1                  (0x2UL << PWR_CR1_ALS_Pos)              /*!< 0x00040000 */
+#define PWR_CR1_AVDEN_Pos              (16U)
+#define PWR_CR1_AVDEN_Msk              (0x1UL << PWR_CR1_AVDEN_Pos)            /*!< 0x00010000 */
+#define PWR_CR1_AVDEN                  PWR_CR1_AVDEN_Msk                       /*!< Analog Voltage Detector Enable */
+#define PWR_CR1_SVOS_Pos               (14U)
+#define PWR_CR1_SVOS_Msk               (0x3UL << PWR_CR1_SVOS_Pos)             /*!< 0x0000C000 */
+#define PWR_CR1_SVOS                   PWR_CR1_SVOS_Msk                        /*!< System STOP mode Voltage Scaling selection */
+#define PWR_CR1_SVOS_0                 (0x1UL << PWR_CR1_SVOS_Pos)             /*!< 0x00004000 */
+#define PWR_CR1_SVOS_1                 (0x2UL << PWR_CR1_SVOS_Pos)             /*!< 0x00008000 */
+#define PWR_CR1_FLPS_Pos               (9U)
+#define PWR_CR1_FLPS_Msk               (0x1UL << PWR_CR1_FLPS_Pos)             /*!< 0x00000200 */
+#define PWR_CR1_FLPS                   PWR_CR1_FLPS_Msk                        /*!< Flash low power mode in DSTOP */
+#define PWR_CR1_DBP_Pos                (8U)
+#define PWR_CR1_DBP_Msk                (0x1UL << PWR_CR1_DBP_Pos)              /*!< 0x00000100 */
+#define PWR_CR1_DBP                    PWR_CR1_DBP_Msk                         /*!< Disable Back-up domain Protection */
+#define PWR_CR1_PLS_Pos                (5U)
+#define PWR_CR1_PLS_Msk                (0x7UL << PWR_CR1_PLS_Pos)              /*!< 0x000000E0 */
+#define PWR_CR1_PLS                    PWR_CR1_PLS_Msk                         /*!< Programmable Voltage Detector level selection */
+#define PWR_CR1_PLS_0                  (0x1UL << PWR_CR1_PLS_Pos)              /*!< 0x00000020 */
+#define PWR_CR1_PLS_1                  (0x2UL << PWR_CR1_PLS_Pos)              /*!< 0x00000040 */
+#define PWR_CR1_PLS_2                  (0x4UL << PWR_CR1_PLS_Pos)              /*!< 0x00000080 */
+#define PWR_CR1_PVDEN_Pos              (4U)
+#define PWR_CR1_PVDEN_Msk              (0x1UL << PWR_CR1_PVDEN_Pos)            /*!< 0x00000010 */
+#define PWR_CR1_PVDEN                  PWR_CR1_PVDEN_Msk                       /*!< Programmable Voltage detector enable */
+#define PWR_CR1_LPDS_Pos               (0U)
+#define PWR_CR1_LPDS_Msk               (0x1UL << PWR_CR1_LPDS_Pos)             /*!< 0x00000001 */
+#define PWR_CR1_LPDS                   PWR_CR1_LPDS_Msk                        /*!< Low Power Deepsleep with SVOS3 */
+
+/*!< PVD level configuration */
+#define PWR_CR1_PLS_LEV0               (0UL)                                   /*!< PVD level 0 */
+#define PWR_CR1_PLS_LEV1_Pos           (5U)
+#define PWR_CR1_PLS_LEV1_Msk           (0x1UL << PWR_CR1_PLS_LEV1_Pos)         /*!< 0x00000020 */
+#define PWR_CR1_PLS_LEV1               PWR_CR1_PLS_LEV1_Msk                    /*!< PVD level 1 */
+#define PWR_CR1_PLS_LEV2_Pos           (6U)
+#define PWR_CR1_PLS_LEV2_Msk           (0x1UL << PWR_CR1_PLS_LEV2_Pos)         /*!< 0x00000040 */
+#define PWR_CR1_PLS_LEV2               PWR_CR1_PLS_LEV2_Msk                    /*!< PVD level 2 */
+#define PWR_CR1_PLS_LEV3_Pos           (5U)
+#define PWR_CR1_PLS_LEV3_Msk           (0x3UL << PWR_CR1_PLS_LEV3_Pos)         /*!< 0x00000060 */
+#define PWR_CR1_PLS_LEV3               PWR_CR1_PLS_LEV3_Msk                    /*!< PVD level 3 */
+#define PWR_CR1_PLS_LEV4_Pos           (7U)
+#define PWR_CR1_PLS_LEV4_Msk           (0x1UL << PWR_CR1_PLS_LEV4_Pos)         /*!< 0x00000080 */
+#define PWR_CR1_PLS_LEV4               PWR_CR1_PLS_LEV4_Msk                    /*!< PVD level 4 */
+#define PWR_CR1_PLS_LEV5_Pos           (5U)
+#define PWR_CR1_PLS_LEV5_Msk           (0x5UL << PWR_CR1_PLS_LEV5_Pos)         /*!< 0x000000A0 */
+#define PWR_CR1_PLS_LEV5               PWR_CR1_PLS_LEV5_Msk                    /*!< PVD level 5 */
+#define PWR_CR1_PLS_LEV6_Pos           (6U)
+#define PWR_CR1_PLS_LEV6_Msk           (0x3UL << PWR_CR1_PLS_LEV6_Pos)         /*!< 0x000000C0 */
+#define PWR_CR1_PLS_LEV6               PWR_CR1_PLS_LEV6_Msk                    /*!< PVD level 6 */
+#define PWR_CR1_PLS_LEV7_Pos           (5U)
+#define PWR_CR1_PLS_LEV7_Msk           (0x7UL << PWR_CR1_PLS_LEV7_Pos)         /*!< 0x000000E0 */
+#define PWR_CR1_PLS_LEV7               PWR_CR1_PLS_LEV7_Msk                    /*!< PVD level 7 */
+
+/*!< AVD level configuration */
+#define PWR_CR1_ALS_LEV0               (0UL)                                   /*!< AVD level 0 */
+#define PWR_CR1_ALS_LEV1_Pos           (17U)
+#define PWR_CR1_ALS_LEV1_Msk           (0x1UL << PWR_CR1_ALS_LEV1_Pos)         /*!< 0x00020000 */
+#define PWR_CR1_ALS_LEV1               PWR_CR1_ALS_LEV1_Msk                    /*!< AVD level 1 */
+#define PWR_CR1_ALS_LEV2_Pos           (18U)
+#define PWR_CR1_ALS_LEV2_Msk           (0x1UL << PWR_CR1_ALS_LEV2_Pos)         /*!< 0x00040000 */
+#define PWR_CR1_ALS_LEV2               PWR_CR1_ALS_LEV2_Msk                    /*!< AVD level 2 */
+#define PWR_CR1_ALS_LEV3_Pos           (17U)
+#define PWR_CR1_ALS_LEV3_Msk           (0x3UL << PWR_CR1_ALS_LEV3_Pos)         /*!< 0x00060000 */
+#define PWR_CR1_ALS_LEV3               PWR_CR1_ALS_LEV3_Msk                    /*!< AVD level 3 */
+
+/********************  Bit definition for PWR_CSR1 register  ******************/
+#define PWR_CSR1_AVDO_Pos              (16U)
+#define PWR_CSR1_AVDO_Msk              (0x1UL << PWR_CSR1_AVDO_Pos)            /*!< 0x00010000 */
+#define PWR_CSR1_AVDO                  PWR_CSR1_AVDO_Msk                       /*!< Analog Voltage Detect Output */
+#define PWR_CSR1_ACTVOS_Pos            (14U)
+#define PWR_CSR1_ACTVOS_Msk            (0x3UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x0000C000 */
+#define PWR_CSR1_ACTVOS                PWR_CSR1_ACTVOS_Msk                     /*!< Current actual used VOS for VDD11 Voltage Scaling */
+#define PWR_CSR1_ACTVOS_0              (0x1UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00004000 */
+#define PWR_CSR1_ACTVOS_1              (0x2UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00008000 */
+#define PWR_CSR1_ACTVOSRDY_Pos         (13U)
+#define PWR_CSR1_ACTVOSRDY_Msk         (0x1UL << PWR_CSR1_ACTVOSRDY_Pos)       /*!< 0x00002000 */
+#define PWR_CSR1_ACTVOSRDY             PWR_CSR1_ACTVOSRDY_Msk                  /*!< Ready bit for current actual used VOS for VDD11 Voltage Scaling  */
+#define PWR_CSR1_PVDO_Pos              (4U)
+#define PWR_CSR1_PVDO_Msk              (0x1UL << PWR_CSR1_PVDO_Pos)            /*!< 0x00000010 */
+#define PWR_CSR1_PVDO                  PWR_CSR1_PVDO_Msk                       /*!< Programmable Voltage Detect Output */
+
+/********************  Bit definition for PWR_CR2 register  *******************/
+#define PWR_CR2_TEMPH_Pos              (23U)
+#define PWR_CR2_TEMPH_Msk              (0x1UL << PWR_CR2_TEMPH_Pos)            /*!< 0x00800000 */
+#define PWR_CR2_TEMPH                  PWR_CR2_TEMPH_Msk                       /*!< Monitored temperature level above high threshold */
+#define PWR_CR2_TEMPL_Pos              (22U)
+#define PWR_CR2_TEMPL_Msk              (0x1UL << PWR_CR2_TEMPL_Pos)            /*!< 0x00400000 */
+#define PWR_CR2_TEMPL                  PWR_CR2_TEMPL_Msk                       /*!< Monitored temperature level above low threshold */
+#define PWR_CR2_VBATH_Pos              (21U)
+#define PWR_CR2_VBATH_Msk              (0x1UL << PWR_CR2_VBATH_Pos)            /*!< 0x00200000 */
+#define PWR_CR2_VBATH                  PWR_CR2_VBATH_Msk                       /*!< Monitored VBAT level above high threshold */
+#define PWR_CR2_VBATL_Pos              (20U)
+#define PWR_CR2_VBATL_Msk              (0x1UL << PWR_CR2_VBATL_Pos)            /*!< 0x00100000 */
+#define PWR_CR2_VBATL                  PWR_CR2_VBATL_Msk                       /*!< Monitored VBAT level above low threshold */
+#define PWR_CR2_BRRDY_Pos              (16U)
+#define PWR_CR2_BRRDY_Msk              (0x1UL << PWR_CR2_BRRDY_Pos)            /*!< 0x00010000 */
+#define PWR_CR2_BRRDY                  PWR_CR2_BRRDY_Msk                       /*!< Backup regulator ready */
+#define PWR_CR2_MONEN_Pos              (4U)
+#define PWR_CR2_MONEN_Msk              (0x1UL << PWR_CR2_MONEN_Pos)            /*!< 0x00000010 */
+#define PWR_CR2_MONEN                  PWR_CR2_MONEN_Msk                       /*!< VBAT and temperature monitoring enable */
+#define PWR_CR2_BREN_Pos               (0U)
+#define PWR_CR2_BREN_Msk               (0x1UL << PWR_CR2_BREN_Pos)             /*!< 0x00000001 */
+#define PWR_CR2_BREN                   PWR_CR2_BREN_Msk                        /*!< Backup regulator enable */
+
+/********************  Bit definition for PWR_CR3 register  *******************/
+#define PWR_CR3_USB33RDY_Pos           (26U)
+#define PWR_CR3_USB33RDY_Msk           (0x1UL << PWR_CR3_USB33RDY_Pos)         /*!< 0x04000000 */
+#define PWR_CR3_USB33RDY               PWR_CR3_USB33RDY_Msk                    /*!< USB supply ready */
+#define PWR_CR3_USBREGEN_Pos           (25U)
+#define PWR_CR3_USBREGEN_Msk           (0x1UL << PWR_CR3_USBREGEN_Pos)         /*!< 0x02000000 */
+#define PWR_CR3_USBREGEN               PWR_CR3_USBREGEN_Msk                    /*!< USB regulator enable */
+#define PWR_CR3_USB33DEN_Pos           (24U)
+#define PWR_CR3_USB33DEN_Msk           (0x1UL << PWR_CR3_USB33DEN_Pos)         /*!< 0x01000000 */
+#define PWR_CR3_USB33DEN               PWR_CR3_USB33DEN_Msk                    /*!< VDD33_USB voltage level detector enable */
+#define PWR_CR3_VBRS_Pos               (9U)
+#define PWR_CR3_VBRS_Msk               (0x1UL << PWR_CR3_VBRS_Pos)             /*!< 0x00000200 */
+#define PWR_CR3_VBRS                   PWR_CR3_VBRS_Msk                        /*!< VBAT charging resistor selection */
+#define PWR_CR3_VBE_Pos                (8U)
+#define PWR_CR3_VBE_Msk                (0x1UL << PWR_CR3_VBE_Pos)              /*!< 0x00000100 */
+#define PWR_CR3_VBE                    PWR_CR3_VBE_Msk                         /*!< VBAT charging enable */
+#define PWR_CR3_SCUEN_Pos              (2U)
+#define PWR_CR3_SCUEN_Msk              (0x1UL << PWR_CR3_SCUEN_Pos)            /*!< 0x00000004 */
+#define PWR_CR3_SCUEN                  PWR_CR3_SCUEN_Msk                       /*!< Supply configuration update enable */
+#define PWR_CR3_LDOEN_Pos              (1U)
+#define PWR_CR3_LDOEN_Msk              (0x1UL << PWR_CR3_LDOEN_Pos)            /*!< 0x00000002 */
+#define PWR_CR3_LDOEN                  PWR_CR3_LDOEN_Msk                       /*!< Low Drop Output regulator enable */
+#define PWR_CR3_BYPASS_Pos             (0U)
+#define PWR_CR3_BYPASS_Msk             (0x1UL << PWR_CR3_BYPASS_Pos)           /*!< 0x00000001 */
+#define PWR_CR3_BYPASS                 PWR_CR3_BYPASS_Msk                      /*!< Power Management Unit bypass */
+
+/********************  Bit definition for PWR_CPUCR register  *****************/
+#define PWR_CPUCR_RUN_D3_Pos           (11U)
+#define PWR_CPUCR_RUN_D3_Msk           (0x1UL << PWR_CPUCR_RUN_D3_Pos)         /*!< 0x00000800 */
+#define PWR_CPUCR_RUN_D3               PWR_CPUCR_RUN_D3_Msk                    /*!< Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes */
+#define PWR_CPUCR_CSSF_Pos             (9U)
+#define PWR_CPUCR_CSSF_Msk             (0x1UL << PWR_CPUCR_CSSF_Pos)           /*!< 0x00000200 */
+#define PWR_CPUCR_CSSF                 PWR_CPUCR_CSSF_Msk                      /*!< Clear D1 domain CPU1 STANDBY, STOP and HOLD flags */
+#define PWR_CPUCR_SBF_D2_Pos           (8U)
+#define PWR_CPUCR_SBF_D2_Msk           (0x1UL << PWR_CPUCR_SBF_D2_Pos)         /*!< 0x00000100 */
+#define PWR_CPUCR_SBF_D2               PWR_CPUCR_SBF_D2_Msk                    /*!< D2 domain DSTANDBY Flag */
+#define PWR_CPUCR_SBF_D1_Pos           (7U)
+#define PWR_CPUCR_SBF_D1_Msk           (0x1UL << PWR_CPUCR_SBF_D1_Pos)         /*!< 0x00000080 */
+#define PWR_CPUCR_SBF_D1               PWR_CPUCR_SBF_D1_Msk                    /*!< D1 domain DSTANDBY Flag */
+#define PWR_CPUCR_SBF_Pos              (6U)
+#define PWR_CPUCR_SBF_Msk              (0x1UL << PWR_CPUCR_SBF_Pos)            /*!< 0x00000040 */
+#define PWR_CPUCR_SBF                  PWR_CPUCR_SBF_Msk                       /*!< System STANDBY Flag */
+#define PWR_CPUCR_STOPF_Pos            (5U)
+#define PWR_CPUCR_STOPF_Msk            (0x1UL << PWR_CPUCR_STOPF_Pos)          /*!< 0x00000020 */
+#define PWR_CPUCR_STOPF                PWR_CPUCR_STOPF_Msk                     /*!< STOP Flag */
+#define PWR_CPUCR_PDDS_D3_Pos          (2U)
+#define PWR_CPUCR_PDDS_D3_Msk          (0x1UL << PWR_CPUCR_PDDS_D3_Pos)        /*!< 0x00000004 */
+#define PWR_CPUCR_PDDS_D3              PWR_CPUCR_PDDS_D3_Msk                   /*!< System D3 domain Power Down Deepsleep */
+#define PWR_CPUCR_PDDS_D2_Pos          (1U)
+#define PWR_CPUCR_PDDS_D2_Msk          (0x1UL << PWR_CPUCR_PDDS_D2_Pos)        /*!< 0x00000002 */
+#define PWR_CPUCR_PDDS_D2              PWR_CPUCR_PDDS_D2_Msk                   /*!< D2 domain Power Down Deepsleep */
+#define PWR_CPUCR_PDDS_D1_Pos          (0U)
+#define PWR_CPUCR_PDDS_D1_Msk          (0x1UL << PWR_CPUCR_PDDS_D1_Pos)        /*!< 0x00000001 */
+#define PWR_CPUCR_PDDS_D1              PWR_CPUCR_PDDS_D1_Msk                   /*!< D1 domain Power Down Deepsleep selection */
+
+
+/********************  Bit definition for PWR_D3CR register  ******************/
+#define PWR_D3CR_VOS_Pos               (14U)
+#define PWR_D3CR_VOS_Msk               (0x3UL << PWR_D3CR_VOS_Pos)             /*!< 0x0000C000 */
+#define PWR_D3CR_VOS                   PWR_D3CR_VOS_Msk                        /*!< Voltage Scaling selection according performance */
+#define PWR_D3CR_VOS_0                 (0x1UL << PWR_D3CR_VOS_Pos)             /*!< 0x00004000 */
+#define PWR_D3CR_VOS_1                 (0x2UL << PWR_D3CR_VOS_Pos)             /*!< 0x00008000 */
+#define PWR_D3CR_VOSRDY_Pos            (13U)
+#define PWR_D3CR_VOSRDY_Msk            (0x1UL << PWR_D3CR_VOSRDY_Pos)          /*!< 0x00002000 */
+#define PWR_D3CR_VOSRDY                PWR_D3CR_VOSRDY_Msk                     /*!< VOS Ready bit for VDD11 Voltage Scaling output selection */
+
+/******************  Bit definition for PWR_WKUPCR register  ******************/
+#define PWR_WKUPCR_WKUPC6_Pos          (5U)
+#define PWR_WKUPCR_WKUPC6_Msk          (0x1UL << PWR_WKUPCR_WKUPC6_Pos)        /*!< 0x00000020 */
+#define PWR_WKUPCR_WKUPC6              PWR_WKUPCR_WKUPC6_Msk                   /*!< Clear Wakeup Pin Flag 6 */
+#define PWR_WKUPCR_WKUPC5_Pos          (4U)
+#define PWR_WKUPCR_WKUPC5_Msk          (0x1UL << PWR_WKUPCR_WKUPC5_Pos)        /*!< 0x00000010 */
+#define PWR_WKUPCR_WKUPC5              PWR_WKUPCR_WKUPC5_Msk                   /*!< Clear Wakeup Pin Flag 5 */
+#define PWR_WKUPCR_WKUPC4_Pos          (3U)
+#define PWR_WKUPCR_WKUPC4_Msk          (0x1UL << PWR_WKUPCR_WKUPC4_Pos)        /*!< 0x00000008 */
+#define PWR_WKUPCR_WKUPC4              PWR_WKUPCR_WKUPC4_Msk                   /*!< Clear Wakeup Pin Flag 4 */
+#define PWR_WKUPCR_WKUPC3_Pos          (2U)
+#define PWR_WKUPCR_WKUPC3_Msk          (0x1UL << PWR_WKUPCR_WKUPC3_Pos)        /*!< 0x00000004 */
+#define PWR_WKUPCR_WKUPC3              PWR_WKUPCR_WKUPC3_Msk                   /*!< Clear Wakeup Pin Flag 3 */
+#define PWR_WKUPCR_WKUPC2_Pos          (1U)
+#define PWR_WKUPCR_WKUPC2_Msk          (0x1UL << PWR_WKUPCR_WKUPC2_Pos)        /*!< 0x00000002 */
+#define PWR_WKUPCR_WKUPC2              PWR_WKUPCR_WKUPC2_Msk                   /*!< Clear Wakeup Pin Flag 2 */
+#define PWR_WKUPCR_WKUPC1_Pos          (0U)
+#define PWR_WKUPCR_WKUPC1_Msk          (0x1UL << PWR_WKUPCR_WKUPC1_Pos)        /*!< 0x00000001 */
+#define PWR_WKUPCR_WKUPC1              PWR_WKUPCR_WKUPC1_Msk                   /*!< Clear Wakeup Pin Flag 1 */
+
+/********************  Bit definition for PWR_WKUPFR register  ****************/
+#define PWR_WKUPFR_WKUPF6_Pos          (5U)
+#define PWR_WKUPFR_WKUPF6_Msk          (0x1UL << PWR_WKUPFR_WKUPF6_Pos)        /*!< 0x00000020 */
+#define PWR_WKUPFR_WKUPF6              PWR_WKUPFR_WKUPF6_Msk                   /*!< Wakeup Pin Flag 6 */
+#define PWR_WKUPFR_WKUPF5_Pos          (4U)
+#define PWR_WKUPFR_WKUPF5_Msk          (0x1UL << PWR_WKUPFR_WKUPF5_Pos)        /*!< 0x00000010 */
+#define PWR_WKUPFR_WKUPF5              PWR_WKUPFR_WKUPF5_Msk                   /*!< Wakeup Pin Flag 5 */
+#define PWR_WKUPFR_WKUPF4_Pos          (3U)
+#define PWR_WKUPFR_WKUPF4_Msk          (0x1UL << PWR_WKUPFR_WKUPF4_Pos)        /*!< 0x00000008 */
+#define PWR_WKUPFR_WKUPF4              PWR_WKUPFR_WKUPF4_Msk                   /*!< Wakeup Pin Flag 4 */
+#define PWR_WKUPFR_WKUPF3_Pos          (2U)
+#define PWR_WKUPFR_WKUPF3_Msk          (0x1UL << PWR_WKUPFR_WKUPF3_Pos)        /*!< 0x00000004 */
+#define PWR_WKUPFR_WKUPF3              PWR_WKUPFR_WKUPF3_Msk                   /*!< Wakeup Pin Flag 3 */
+#define PWR_WKUPFR_WKUPF2_Pos          (1U)
+#define PWR_WKUPFR_WKUPF2_Msk          (0x1UL << PWR_WKUPFR_WKUPF2_Pos)        /*!< 0x00000002 */
+#define PWR_WKUPFR_WKUPF2              PWR_WKUPFR_WKUPF2_Msk                   /*!< Wakeup Pin Flag 2 */
+#define PWR_WKUPFR_WKUPF1_Pos          (0U)
+#define PWR_WKUPFR_WKUPF1_Msk          (0x1UL << PWR_WKUPFR_WKUPF1_Pos)        /*!< 0x00000001 */
+#define PWR_WKUPFR_WKUPF1              PWR_WKUPFR_WKUPF1_Msk                   /*!< Wakeup Pin Flag 1 */
+
+/******************  Bit definition for PWR_WKUPEPR register  *****************/
+#define PWR_WKUPEPR_WKUPPUPD6_Pos      (26U)
+#define PWR_WKUPEPR_WKUPPUPD6_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x0C000000 */
+#define PWR_WKUPEPR_WKUPPUPD6          PWR_WKUPEPR_WKUPPUPD6_Msk               /*!< Wakeup Pin pull configuration for WKUP6 */
+#define PWR_WKUPEPR_WKUPPUPD6_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x04000000 */
+#define PWR_WKUPEPR_WKUPPUPD6_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x08000000 */
+#define PWR_WKUPEPR_WKUPPUPD5_Pos      (24U)
+#define PWR_WKUPEPR_WKUPPUPD5_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x03000000 */
+#define PWR_WKUPEPR_WKUPPUPD5          PWR_WKUPEPR_WKUPPUPD5_Msk               /*!< Wakeup Pin pull configuration for WKUP5 */
+#define PWR_WKUPEPR_WKUPPUPD5_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x01000000 */
+#define PWR_WKUPEPR_WKUPPUPD5_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x02000000 */
+#define PWR_WKUPEPR_WKUPPUPD4_Pos      (22U)
+#define PWR_WKUPEPR_WKUPPUPD4_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00C00000 */
+#define PWR_WKUPEPR_WKUPPUPD4          PWR_WKUPEPR_WKUPPUPD4_Msk               /*!< Wakeup Pin pull configuration for WKUP4 */
+#define PWR_WKUPEPR_WKUPPUPD4_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00400000 */
+#define PWR_WKUPEPR_WKUPPUPD4_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00800000 */
+#define PWR_WKUPEPR_WKUPPUPD3_Pos      (20U)
+#define PWR_WKUPEPR_WKUPPUPD3_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00300000 */
+#define PWR_WKUPEPR_WKUPPUPD3          PWR_WKUPEPR_WKUPPUPD3_Msk               /*!< Wakeup Pin pull configuration for WKUP3 */
+#define PWR_WKUPEPR_WKUPPUPD3_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00100000 */
+#define PWR_WKUPEPR_WKUPPUPD3_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00200000 */
+#define PWR_WKUPEPR_WKUPPUPD2_Pos      (18U)
+#define PWR_WKUPEPR_WKUPPUPD2_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x000C0000 */
+#define PWR_WKUPEPR_WKUPPUPD2          PWR_WKUPEPR_WKUPPUPD2_Msk               /*!< Wakeup Pin pull configuration for WKUP2 */
+#define PWR_WKUPEPR_WKUPPUPD2_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00040000 */
+#define PWR_WKUPEPR_WKUPPUPD2_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00080000 */
+#define PWR_WKUPEPR_WKUPPUPD1_Pos      (16U)
+#define PWR_WKUPEPR_WKUPPUPD1_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00030000 */
+#define PWR_WKUPEPR_WKUPPUPD1          PWR_WKUPEPR_WKUPPUPD1_Msk               /*!< Wakeup Pin pull configuration for WKUP1 */
+#define PWR_WKUPEPR_WKUPPUPD1_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00010000 */
+#define PWR_WKUPEPR_WKUPPUPD1_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00020000 */
+#define PWR_WKUPEPR_WKUPP6_Pos         (13U)
+#define PWR_WKUPEPR_WKUPP6_Msk         (0x1UL << PWR_WKUPEPR_WKUPP6_Pos)       /*!< 0x00002000 */
+#define PWR_WKUPEPR_WKUPP6             PWR_WKUPEPR_WKUPP6_Msk                  /*!< Wakeup Pin Polarity for WKUP6 */
+#define PWR_WKUPEPR_WKUPP5_Pos         (12U)
+#define PWR_WKUPEPR_WKUPP5_Msk         (0x1UL << PWR_WKUPEPR_WKUPP5_Pos)       /*!< 0x00001000 */
+#define PWR_WKUPEPR_WKUPP5             PWR_WKUPEPR_WKUPP5_Msk                  /*!< Wakeup Pin Polarity for WKUP5 */
+#define PWR_WKUPEPR_WKUPP4_Pos         (11U)
+#define PWR_WKUPEPR_WKUPP4_Msk         (0x1UL << PWR_WKUPEPR_WKUPP4_Pos)       /*!< 0x00000800 */
+#define PWR_WKUPEPR_WKUPP4             PWR_WKUPEPR_WKUPP4_Msk                  /*!< Wakeup Pin Polarity for WKUP4 */
+#define PWR_WKUPEPR_WKUPP3_Pos         (10U)
+#define PWR_WKUPEPR_WKUPP3_Msk         (0x1UL << PWR_WKUPEPR_WKUPP3_Pos)       /*!< 0x00000400 */
+#define PWR_WKUPEPR_WKUPP3             PWR_WKUPEPR_WKUPP3_Msk                  /*!< Wakeup Pin Polarity for WKUP3 */
+#define PWR_WKUPEPR_WKUPP2_Pos         (9U)
+#define PWR_WKUPEPR_WKUPP2_Msk         (0x1UL << PWR_WKUPEPR_WKUPP2_Pos)       /*!< 0x00000200 */
+#define PWR_WKUPEPR_WKUPP2             PWR_WKUPEPR_WKUPP2_Msk                  /*!< Wakeup Pin Polarity for WKUP2 */
+#define PWR_WKUPEPR_WKUPP1_Pos         (8U)
+#define PWR_WKUPEPR_WKUPP1_Msk         (0x1UL << PWR_WKUPEPR_WKUPP1_Pos)       /*!< 0x00000100 */
+#define PWR_WKUPEPR_WKUPP1             PWR_WKUPEPR_WKUPP1_Msk                  /*!< Wakeup Pin Polarity for WKUP1 */
+#define PWR_WKUPEPR_WKUPEN6_Pos        (5U)
+#define PWR_WKUPEPR_WKUPEN6_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN6_Pos)      /*!< 0x00000020 */
+#define PWR_WKUPEPR_WKUPEN6            PWR_WKUPEPR_WKUPEN6_Msk                 /*!< Enable Wakeup Pin WKUP6 */
+#define PWR_WKUPEPR_WKUPEN5_Pos        (4U)
+#define PWR_WKUPEPR_WKUPEN5_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN5_Pos)      /*!< 0x00000010 */
+#define PWR_WKUPEPR_WKUPEN5            PWR_WKUPEPR_WKUPEN5_Msk                 /*!< Enable Wakeup Pin WKUP5 */
+#define PWR_WKUPEPR_WKUPEN4_Pos        (3U)
+#define PWR_WKUPEPR_WKUPEN4_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos)      /*!< 0x00000008 */
+#define PWR_WKUPEPR_WKUPEN4            PWR_WKUPEPR_WKUPEN4_Msk                 /*!< Enable Wakeup Pin WKUP4 */
+#define PWR_WKUPEPR_WKUPEN3_Pos        (2U)
+#define PWR_WKUPEPR_WKUPEN3_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos)      /*!< 0x00000004 */
+#define PWR_WKUPEPR_WKUPEN3            PWR_WKUPEPR_WKUPEN3_Msk                 /*!< Enable Wakeup Pin WKUP3 */
+#define PWR_WKUPEPR_WKUPEN2_Pos        (1U)
+#define PWR_WKUPEPR_WKUPEN2_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos)      /*!< 0x00000002 */
+#define PWR_WKUPEPR_WKUPEN2            PWR_WKUPEPR_WKUPEN2_Msk                 /*!< Enable Wakeup Pin WKUP2 */
+#define PWR_WKUPEPR_WKUPEN1_Pos        (0U)
+#define PWR_WKUPEPR_WKUPEN1_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos)      /*!< 0x00000001 */
+#define PWR_WKUPEPR_WKUPEN1            PWR_WKUPEPR_WKUPEN1_Msk                 /*!< Enable Wakeup Pin WKUP1 */
+#define PWR_WKUPEPR_WKUPEN_Pos         (0U)
+#define PWR_WKUPEPR_WKUPEN_Msk         (0x3FUL << PWR_WKUPEPR_WKUPEN_Pos)      /*!< 0x0000003F */
+#define PWR_WKUPEPR_WKUPEN             PWR_WKUPEPR_WKUPEN_Msk                  /*!< Enable all Wakeup Pin */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Reset and Clock Control                            */
+/*                                                                            */
+/******************************************************************************/
+/*******************************  RCC VERSION  ********************************/
+#define RCC_VER_X
+
+/********************  Bit definition for RCC_CR register  ********************/
+#define RCC_CR_HSION_Pos                       (0U)
+#define RCC_CR_HSION_Msk                       (0x1UL << RCC_CR_HSION_Pos)     /*!< 0x00000001 */
+#define RCC_CR_HSION                           RCC_CR_HSION_Msk                /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIKERON_Pos                    (1U)
+#define RCC_CR_HSIKERON_Msk                    (0x1UL << RCC_CR_HSIKERON_Pos)  /*!< 0x00000002 */
+#define RCC_CR_HSIKERON                        RCC_CR_HSIKERON_Msk             /*!< Internal High Speed clock enable for some IPs Kernel */
+#define RCC_CR_HSIRDY_Pos                      (2U)
+#define RCC_CR_HSIRDY_Msk                      (0x1UL << RCC_CR_HSIRDY_Pos)    /*!< 0x00000004 */
+#define RCC_CR_HSIRDY                          RCC_CR_HSIRDY_Msk               /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSIDIV_Pos                      (3U)
+#define RCC_CR_HSIDIV_Msk                      (0x3UL << RCC_CR_HSIDIV_Pos)    /*!< 0x00000018 */
+#define RCC_CR_HSIDIV                          RCC_CR_HSIDIV_Msk               /*!< Internal High Speed clock divider selection */
+#define RCC_CR_HSIDIV_1                        (0x0UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000000 */
+#define RCC_CR_HSIDIV_2                        (0x1UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000008 */
+#define RCC_CR_HSIDIV_4                        (0x2UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000010 */
+#define RCC_CR_HSIDIV_8                        (0x3UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000018 */
+
+#define RCC_CR_HSIDIVF_Pos                     (5U)
+#define RCC_CR_HSIDIVF_Msk                     (0x1UL << RCC_CR_HSIDIVF_Pos)   /*!< 0x00000020 */
+#define RCC_CR_HSIDIVF                         RCC_CR_HSIDIVF_Msk              /*!< HSI Divider flag */
+#define RCC_CR_CSION_Pos                       (7U)
+#define RCC_CR_CSION_Msk                       (0x1UL << RCC_CR_CSION_Pos)     /*!< 0x00000080 */
+#define RCC_CR_CSION                           RCC_CR_CSION_Msk                /*!< The Internal RC 4MHz oscillator clock enable */
+#define RCC_CR_CSIRDY_Pos                      (8U)
+#define RCC_CR_CSIRDY_Msk                      (0x1UL << RCC_CR_CSIRDY_Pos)    /*!< 0x00000100 */
+#define RCC_CR_CSIRDY                          RCC_CR_CSIRDY_Msk               /*!< The Internal RC 4MHz oscillator clock ready */
+#define RCC_CR_CSIKERON_Pos                    (9U)
+#define RCC_CR_CSIKERON_Msk                    (0x1UL << RCC_CR_CSIKERON_Pos)  /*!< 0x00000200 */
+#define RCC_CR_CSIKERON                        RCC_CR_CSIKERON_Msk             /*!< Internal RC 4MHz oscillator clock enable for some IPs Kernel */
+#define RCC_CR_HSI48ON_Pos                     (12U)
+#define RCC_CR_HSI48ON_Msk                     (0x1UL << RCC_CR_HSI48ON_Pos)   /*!< 0x00001000 */
+#define RCC_CR_HSI48ON                         RCC_CR_HSI48ON_Msk              /*!< HSI48 clock enable clock enable  */
+#define RCC_CR_HSI48RDY_Pos                    (13U)
+#define RCC_CR_HSI48RDY_Msk                    (0x1UL << RCC_CR_HSI48RDY_Pos)  /*!< 0x00002000 */
+#define RCC_CR_HSI48RDY                        RCC_CR_HSI48RDY_Msk             /*!< HSI48 clock ready */
+
+#define RCC_CR_D1CKRDY_Pos                     (14U)
+#define RCC_CR_D1CKRDY_Msk                     (0x1UL << RCC_CR_D1CKRDY_Pos)   /*!< 0x00004000 */
+#define RCC_CR_D1CKRDY                         RCC_CR_D1CKRDY_Msk              /*!< D1 domain clocks ready flag  */
+#define RCC_CR_D2CKRDY_Pos                     (15U)
+#define RCC_CR_D2CKRDY_Msk                     (0x1UL << RCC_CR_D2CKRDY_Pos)   /*!< 0x00008000 */
+#define RCC_CR_D2CKRDY                         RCC_CR_D2CKRDY_Msk              /*!< D2 domain clocks ready flag */
+
+#define RCC_CR_HSEON_Pos                       (16U)
+#define RCC_CR_HSEON_Msk                       (0x1UL << RCC_CR_HSEON_Pos)     /*!< 0x00010000 */
+#define RCC_CR_HSEON                           RCC_CR_HSEON_Msk                /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY_Pos                      (17U)
+#define RCC_CR_HSERDY_Msk                      (0x1UL << RCC_CR_HSERDY_Pos)    /*!< 0x00020000 */
+#define RCC_CR_HSERDY                          RCC_CR_HSERDY_Msk               /*!< External High Speed clock ready */
+#define RCC_CR_HSEBYP_Pos                      (18U)
+#define RCC_CR_HSEBYP_Msk                      (0x1UL << RCC_CR_HSEBYP_Pos)    /*!< 0x00040000 */
+#define RCC_CR_HSEBYP                          RCC_CR_HSEBYP_Msk               /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSHSEON_Pos                    (19U)
+#define RCC_CR_CSSHSEON_Msk                    (0x1UL << RCC_CR_CSSHSEON_Pos)  /*!< 0x00080000 */
+#define RCC_CR_CSSHSEON                        RCC_CR_CSSHSEON_Msk             /*!< HSE Clock security System enable */
+
+
+#define RCC_CR_PLL1ON_Pos                      (24U)
+#define RCC_CR_PLL1ON_Msk                      (0x1UL << RCC_CR_PLL1ON_Pos)    /*!< 0x01000000 */
+#define RCC_CR_PLL1ON                          RCC_CR_PLL1ON_Msk               /*!< System PLL1 clock enable */
+#define RCC_CR_PLL1RDY_Pos                     (25U)
+#define RCC_CR_PLL1RDY_Msk                     (0x1UL << RCC_CR_PLL1RDY_Pos)   /*!< 0x02000000 */
+#define RCC_CR_PLL1RDY                         RCC_CR_PLL1RDY_Msk              /*!< System PLL1 clock ready */
+#define RCC_CR_PLL2ON_Pos                      (26U)
+#define RCC_CR_PLL2ON_Msk                      (0x1UL << RCC_CR_PLL2ON_Pos)    /*!< 0x04000000 */
+#define RCC_CR_PLL2ON                          RCC_CR_PLL2ON_Msk               /*!< System PLL2 clock enable */
+#define RCC_CR_PLL2RDY_Pos                     (27U)
+#define RCC_CR_PLL2RDY_Msk                     (0x1UL << RCC_CR_PLL2RDY_Pos)   /*!< 0x08000000 */
+#define RCC_CR_PLL2RDY                         RCC_CR_PLL2RDY_Msk              /*!< System PLL2 clock ready */
+#define RCC_CR_PLL3ON_Pos                      (28U)
+#define RCC_CR_PLL3ON_Msk                      (0x1UL << RCC_CR_PLL3ON_Pos)    /*!< 0x10000000 */
+#define RCC_CR_PLL3ON                          RCC_CR_PLL3ON_Msk               /*!< System PLL3 clock enable */
+#define RCC_CR_PLL3RDY_Pos                     (29U)
+#define RCC_CR_PLL3RDY_Msk                     (0x1UL << RCC_CR_PLL3RDY_Pos)   /*!< 0x20000000 */
+#define RCC_CR_PLL3RDY                         RCC_CR_PLL3RDY_Msk              /*!< System PLL3 clock ready */
+
+/*Legacy */
+#define RCC_CR_PLLON_Pos                       (24U)
+#define RCC_CR_PLLON_Msk                       (0x1UL << RCC_CR_PLLON_Pos)     /*!< 0x01000000 */
+#define RCC_CR_PLLON                           RCC_CR_PLLON_Msk                /*!< System PLL clock enable */
+#define RCC_CR_PLLRDY_Pos                      (25U)
+#define RCC_CR_PLLRDY_Msk                      (0x1UL << RCC_CR_PLLRDY_Pos)    /*!< 0x02000000 */
+#define RCC_CR_PLLRDY                          RCC_CR_PLLRDY_Msk               /*!< System PLL clock ready */
+
+/********************  Bit definition for RCC_HSICFGR register  ***************/
+/*!< HSICAL configuration */
+#define RCC_HSICFGR_HSICAL_Pos                 (0U)
+#define RCC_HSICFGR_HSICAL_Msk                 (0xFFFUL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000FFF */
+#define RCC_HSICFGR_HSICAL                     RCC_HSICFGR_HSICAL_Msk          /*!< HSICAL[11:0] bits */
+#define RCC_HSICFGR_HSICAL_0                   (0x001UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000001 */
+#define RCC_HSICFGR_HSICAL_1                   (0x002UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000002 */
+#define RCC_HSICFGR_HSICAL_2                   (0x004UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000004 */
+#define RCC_HSICFGR_HSICAL_3                   (0x008UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000008 */
+#define RCC_HSICFGR_HSICAL_4                   (0x010UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000010 */
+#define RCC_HSICFGR_HSICAL_5                   (0x020UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000020 */
+#define RCC_HSICFGR_HSICAL_6                   (0x040UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000040 */
+#define RCC_HSICFGR_HSICAL_7                   (0x080UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000080 */
+#define RCC_HSICFGR_HSICAL_8                   (0x100UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000100 */
+#define RCC_HSICFGR_HSICAL_9                   (0x200UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000200 */
+#define RCC_HSICFGR_HSICAL_10                  (0x400UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000400 */
+#define RCC_HSICFGR_HSICAL_11                  (0x800UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000800 */
+
+/*!< HSITRIM configuration */
+#define RCC_HSICFGR_HSITRIM_Pos                (24U)
+#define RCC_HSICFGR_HSITRIM_Msk                (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x7F000000 */
+#define RCC_HSICFGR_HSITRIM                    RCC_HSICFGR_HSITRIM_Msk         /*!< HSITRIM[6:0] bits */
+#define RCC_HSICFGR_HSITRIM_0                  (0x01UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x01000000 */
+#define RCC_HSICFGR_HSITRIM_1                  (0x02UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x02000000 */
+#define RCC_HSICFGR_HSITRIM_2                  (0x04UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x04000000 */
+#define RCC_HSICFGR_HSITRIM_3                  (0x08UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x08000000 */
+#define RCC_HSICFGR_HSITRIM_4                  (0x10UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x10000000 */
+#define RCC_HSICFGR_HSITRIM_5                  (0x20UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x20000000 */
+#define RCC_HSICFGR_HSITRIM_6                  (0x40UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x40000000 */
+
+
+/********************  Bit definition for RCC_CRRCR register  *****************/
+
+/*!< HSI48CAL configuration */
+#define RCC_CRRCR_HSI48CAL_Pos                 (0U)
+#define RCC_CRRCR_HSI48CAL_Msk                 (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x000003FF */
+#define RCC_CRRCR_HSI48CAL                     RCC_CRRCR_HSI48CAL_Msk          /*!< HSI48CAL[9:0] bits */
+#define RCC_CRRCR_HSI48CAL_0                   (0x001UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000001 */
+#define RCC_CRRCR_HSI48CAL_1                   (0x002UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000002 */
+#define RCC_CRRCR_HSI48CAL_2                   (0x004UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000004 */
+#define RCC_CRRCR_HSI48CAL_3                   (0x008UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000008 */
+#define RCC_CRRCR_HSI48CAL_4                   (0x010UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000010 */
+#define RCC_CRRCR_HSI48CAL_5                   (0x020UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000020 */
+#define RCC_CRRCR_HSI48CAL_6                   (0x040UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000040 */
+#define RCC_CRRCR_HSI48CAL_7                   (0x080UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */
+#define RCC_CRRCR_HSI48CAL_8                   (0x100UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */
+#define RCC_CRRCR_HSI48CAL_9                   (0x200UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */
+
+
+/********************  Bit definition for RCC_CSICFGR register  *****************/
+/*!< CSICAL configuration */
+#define RCC_CSICFGR_CSICAL_Pos                 (0U)
+#define RCC_CSICFGR_CSICAL_Msk                 (0xFFUL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x000000FF */
+#define RCC_CSICFGR_CSICAL                     RCC_CSICFGR_CSICAL_Msk          /*!< CSICAL[7:0] bits */
+#define RCC_CSICFGR_CSICAL_0                   (0x01UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000001 */
+#define RCC_CSICFGR_CSICAL_1                   (0x02UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000002 */
+#define RCC_CSICFGR_CSICAL_2                   (0x04UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000004 */
+#define RCC_CSICFGR_CSICAL_3                   (0x08UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000008 */
+#define RCC_CSICFGR_CSICAL_4                   (0x10UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000010 */
+#define RCC_CSICFGR_CSICAL_5                   (0x20UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000020 */
+#define RCC_CSICFGR_CSICAL_6                   (0x40UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000040 */
+#define RCC_CSICFGR_CSICAL_7                   (0x80UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000080 */
+
+/*!< CSITRIM configuration */
+#define RCC_CSICFGR_CSITRIM_Pos                (24U)
+#define RCC_CSICFGR_CSITRIM_Msk                (0x3FUL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x3F000000 */
+#define RCC_CSICFGR_CSITRIM                    RCC_CSICFGR_CSITRIM_Msk         /*!< CSITRIM[5:0] bits */
+#define RCC_CSICFGR_CSITRIM_0                  (0x01UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x01000000 */
+#define RCC_CSICFGR_CSITRIM_1                  (0x02UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x02000000 */
+#define RCC_CSICFGR_CSITRIM_2                  (0x04UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x04000000 */
+#define RCC_CSICFGR_CSITRIM_3                  (0x08UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x08000000 */
+#define RCC_CSICFGR_CSITRIM_4                  (0x10UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x10000000 */
+#define RCC_CSICFGR_CSITRIM_5                  (0x20UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x20000000 */
+
+/********************  Bit definition for RCC_CFGR register  ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos                        (0U)
+#define RCC_CFGR_SW_Msk                        (0x7UL << RCC_CFGR_SW_Pos)           /*!< 0x00000007 */
+#define RCC_CFGR_SW                            RCC_CFGR_SW_Msk                     /*!< SW[2:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0                          (0x1UL << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */
+#define RCC_CFGR_SW_1                          (0x2UL << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */
+#define RCC_CFGR_SW_2                          (0x4UL << RCC_CFGR_SW_Pos)           /*!< 0x00000004 */
+
+#define RCC_CFGR_SW_HSI                        (0x00000000UL)                       /*!< HSI selection as system clock */
+#define RCC_CFGR_SW_CSI                        (0x00000001UL)                       /*!< CSI selection as system clock */
+#define RCC_CFGR_SW_HSE                        (0x00000002UL)                       /*!< HSE selection as system clock */
+#define RCC_CFGR_SW_PLL1                       (0x00000003UL)                       /*!< PLL1 selection as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos                       (3U)
+#define RCC_CFGR_SWS_Msk                       (0x7UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000038 */
+#define RCC_CFGR_SWS                           RCC_CFGR_SWS_Msk                    /*!< SWS[2:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0                         (0x1UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */
+#define RCC_CFGR_SWS_1                         (0x2UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000010 */
+#define RCC_CFGR_SWS_2                         (0x4UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000020 */
+
+#define RCC_CFGR_SWS_HSI                       (0x00000000UL)                       /*!< HSI used as system clock */
+#define RCC_CFGR_SWS_CSI                       (0x00000008UL)                       /*!< CSI used as system clock */
+#define RCC_CFGR_SWS_HSE                       (0x00000010UL)                       /*!< HSE used as system clock */
+#define RCC_CFGR_SWS_PLL1                      (0x00000018UL)                       /*!< PLL1 used as system clock */
+
+#define RCC_CFGR_STOPWUCK_Pos                  (6U)
+#define RCC_CFGR_STOPWUCK_Msk                  (0x1UL << RCC_CFGR_STOPWUCK_Pos)     /*!< 0x00000040 */
+#define RCC_CFGR_STOPWUCK                      RCC_CFGR_STOPWUCK_Msk                /*!< Wake Up from stop and CSS backup clock selection */
+
+#define RCC_CFGR_STOPKERWUCK_Pos               (7U)
+#define RCC_CFGR_STOPKERWUCK_Msk               (0x1UL << RCC_CFGR_STOPKERWUCK_Pos)  /*!< 0x00000080 */
+#define RCC_CFGR_STOPKERWUCK                   RCC_CFGR_STOPKERWUCK_Msk             /*!< Kernel Clock Selection after a Wake Up from STOP */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE_Pos                    (8U)
+#define RCC_CFGR_RTCPRE_Msk                    (0x3FUL << RCC_CFGR_RTCPRE_Pos)
+#define RCC_CFGR_RTCPRE                        RCC_CFGR_RTCPRE_Msk                  /*!< 0x00003F00 */
+#define RCC_CFGR_RTCPRE_0                      (0x1UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000100 */
+#define RCC_CFGR_RTCPRE_1                      (0x2UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000200 */
+#define RCC_CFGR_RTCPRE_2                      (0x4UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000400 */
+#define RCC_CFGR_RTCPRE_3                      (0x8UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000800 */
+#define RCC_CFGR_RTCPRE_4                      (0x10UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00001000 */
+#define RCC_CFGR_RTCPRE_5                      (0x20UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00002000 */
+
+/*!< HRTIMSEL configuration */
+#define RCC_CFGR_HRTIMSEL_Pos                  (14U)
+#define RCC_CFGR_HRTIMSEL_Msk                  (0x1UL << RCC_CFGR_HRTIMSEL_Pos)
+#define RCC_CFGR_HRTIMSEL                      RCC_CFGR_HRTIMSEL_Msk                /*!< 0x00004000 */
+
+/*!< TIMPRE configuration */
+#define RCC_CFGR_TIMPRE_Pos                    (15U)
+#define RCC_CFGR_TIMPRE_Msk                    (0x1UL << RCC_CFGR_TIMPRE_Pos)
+#define RCC_CFGR_TIMPRE                        RCC_CFGR_TIMPRE_Msk                  /*!< 0x00008000 */
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1_Pos                      (22U)
+#define RCC_CFGR_MCO1_Msk                      (0x7UL << RCC_CFGR_MCO1_Pos)
+#define RCC_CFGR_MCO1                          RCC_CFGR_MCO1_Msk                       /*!< 0x01C00000 */
+#define RCC_CFGR_MCO1_0                        (0x1UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00400000 */
+#define RCC_CFGR_MCO1_1                        (0x2UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00800000 */
+#define RCC_CFGR_MCO1_2                        (0x4UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x01000000 */
+
+#define RCC_CFGR_MCO1PRE_Pos                   (18U)
+#define RCC_CFGR_MCO1PRE_Msk                   (0xFUL << RCC_CFGR_MCO1PRE_Pos)
+#define RCC_CFGR_MCO1PRE                       RCC_CFGR_MCO1PRE_Msk                    /*!< 0x003C0000 */
+#define RCC_CFGR_MCO1PRE_0                     (0x1UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00040000 */
+#define RCC_CFGR_MCO1PRE_1                     (0x2UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00080000 */
+#define RCC_CFGR_MCO1PRE_2                     (0x4UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00100000 */
+#define RCC_CFGR_MCO1PRE_3                     (0x8UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00200000 */
+
+#define RCC_CFGR_MCO2PRE_Pos                   (25U)
+#define RCC_CFGR_MCO2PRE_Msk                   (0xFUL << RCC_CFGR_MCO2PRE_Pos)
+#define RCC_CFGR_MCO2PRE                       RCC_CFGR_MCO2PRE_Msk                    /*!< 0x1E000000 */
+#define RCC_CFGR_MCO2PRE_0                     (0x1UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x02000000 */
+#define RCC_CFGR_MCO2PRE_1                     (0x2UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x04000000 */
+#define RCC_CFGR_MCO2PRE_2                     (0x4UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x08000000 */
+#define RCC_CFGR_MCO2PRE_3                     (0x8UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x10000000 */
+
+#define RCC_CFGR_MCO2_Pos                      (29U)
+#define RCC_CFGR_MCO2_Msk                      (0x7UL << RCC_CFGR_MCO2_Pos)
+#define RCC_CFGR_MCO2                          RCC_CFGR_MCO2_Msk                       /*!< 0xE0000000 */
+#define RCC_CFGR_MCO2_0                        (0x1UL << RCC_CFGR_MCO2_Pos)             /*!< 0x20000000 */
+#define RCC_CFGR_MCO2_1                        (0x2UL << RCC_CFGR_MCO2_Pos)             /*!< 0x40000000 */
+#define RCC_CFGR_MCO2_2                        (0x4UL << RCC_CFGR_MCO2_Pos)             /*!< 0x80000000 */
+
+/********************  Bit definition for RCC_D1CFGR register  ******************/
+/*!< D1HPRE configuration */
+#define RCC_D1CFGR_HPRE_Pos                    (0U)
+#define RCC_D1CFGR_HPRE_Msk                    (0xFUL << RCC_D1CFGR_HPRE_Pos)  /*!< 0x0000000F */
+#define RCC_D1CFGR_HPRE                        RCC_D1CFGR_HPRE_Msk             /*!< HPRE[3:0] bits (AHB3 prescaler) */
+#define RCC_D1CFGR_HPRE_0                      (0x1UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000001 */
+#define RCC_D1CFGR_HPRE_1                      (0x2UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000002 */
+#define RCC_D1CFGR_HPRE_2                      (0x4UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000004 */
+#define RCC_D1CFGR_HPRE_3                      (0x8UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000008 */
+
+
+#define RCC_D1CFGR_HPRE_DIV1                   ((uint32_t)0x00000000)          /*!< AHB3 Clock not divided */
+#define RCC_D1CFGR_HPRE_DIV2_Pos               (3U)
+#define RCC_D1CFGR_HPRE_DIV2_Msk               (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */
+#define RCC_D1CFGR_HPRE_DIV2                   RCC_D1CFGR_HPRE_DIV2_Msk        /*!< AHB3 Clock divided by 2 */
+#define RCC_D1CFGR_HPRE_DIV4_Pos               (0U)
+#define RCC_D1CFGR_HPRE_DIV4_Msk               (0x9UL << RCC_D1CFGR_HPRE_DIV4_Pos) /*!< 0x00000009 */
+#define RCC_D1CFGR_HPRE_DIV4                   RCC_D1CFGR_HPRE_DIV4_Msk        /*!< AHB3 Clock divided by 4 */
+#define RCC_D1CFGR_HPRE_DIV8_Pos               (1U)
+#define RCC_D1CFGR_HPRE_DIV8_Msk               (0x5UL << RCC_D1CFGR_HPRE_DIV8_Pos) /*!< 0x0000000A */
+#define RCC_D1CFGR_HPRE_DIV8                   RCC_D1CFGR_HPRE_DIV8_Msk        /*!< AHB3 Clock divided by 8 */
+#define RCC_D1CFGR_HPRE_DIV16_Pos              (0U)
+#define RCC_D1CFGR_HPRE_DIV16_Msk              (0xBUL << RCC_D1CFGR_HPRE_DIV16_Pos) /*!< 0x0000000B */
+#define RCC_D1CFGR_HPRE_DIV16                  RCC_D1CFGR_HPRE_DIV16_Msk       /*!< AHB3 Clock divided by 16 */
+#define RCC_D1CFGR_HPRE_DIV64_Pos              (2U)
+#define RCC_D1CFGR_HPRE_DIV64_Msk              (0x3UL << RCC_D1CFGR_HPRE_DIV64_Pos) /*!< 0x0000000C */
+#define RCC_D1CFGR_HPRE_DIV64                  RCC_D1CFGR_HPRE_DIV64_Msk       /*!< AHB3 Clock divided by 64 */
+#define RCC_D1CFGR_HPRE_DIV128_Pos             (0U)
+#define RCC_D1CFGR_HPRE_DIV128_Msk             (0xDUL << RCC_D1CFGR_HPRE_DIV128_Pos) /*!< 0x0000000D */
+#define RCC_D1CFGR_HPRE_DIV128                 RCC_D1CFGR_HPRE_DIV128_Msk      /*!< AHB3 Clock divided by 128 */
+#define RCC_D1CFGR_HPRE_DIV256_Pos             (1U)
+#define RCC_D1CFGR_HPRE_DIV256_Msk             (0x7UL << RCC_D1CFGR_HPRE_DIV256_Pos) /*!< 0x0000000E */
+#define RCC_D1CFGR_HPRE_DIV256                 RCC_D1CFGR_HPRE_DIV256_Msk      /*!< AHB3 Clock divided by 256 */
+#define RCC_D1CFGR_HPRE_DIV512_Pos             (0U)
+#define RCC_D1CFGR_HPRE_DIV512_Msk             (0xFUL << RCC_D1CFGR_HPRE_DIV512_Pos) /*!< 0x0000000F */
+#define RCC_D1CFGR_HPRE_DIV512                 RCC_D1CFGR_HPRE_DIV512_Msk      /*!< AHB3 Clock divided by 512 */
+
+/*!< D1PPRE configuration */
+#define RCC_D1CFGR_D1PPRE_Pos                  (4U)
+#define RCC_D1CFGR_D1PPRE_Msk                  (0x7UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000070 */
+#define RCC_D1CFGR_D1PPRE                      RCC_D1CFGR_D1PPRE_Msk           /*!< D1PRE[2:0] bits (APB3 prescaler) */
+#define RCC_D1CFGR_D1PPRE_0                    (0x1UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000010 */
+#define RCC_D1CFGR_D1PPRE_1                    (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */
+#define RCC_D1CFGR_D1PPRE_2                    (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */
+
+#define RCC_D1CFGR_D1PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB3 clock not divided */
+#define RCC_D1CFGR_D1PPRE_DIV2_Pos             (6U)
+#define RCC_D1CFGR_D1PPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */
+#define RCC_D1CFGR_D1PPRE_DIV2                 RCC_D1CFGR_D1PPRE_DIV2_Msk      /*!< APB3 clock divided by 2 */
+#define RCC_D1CFGR_D1PPRE_DIV4_Pos             (4U)
+#define RCC_D1CFGR_D1PPRE_DIV4_Msk             (0x5UL << RCC_D1CFGR_D1PPRE_DIV4_Pos) /*!< 0x00000050 */
+#define RCC_D1CFGR_D1PPRE_DIV4                 RCC_D1CFGR_D1PPRE_DIV4_Msk      /*!< APB3 clock divided by 4 */
+#define RCC_D1CFGR_D1PPRE_DIV8_Pos             (5U)
+#define RCC_D1CFGR_D1PPRE_DIV8_Msk             (0x3UL << RCC_D1CFGR_D1PPRE_DIV8_Pos) /*!< 0x00000060 */
+#define RCC_D1CFGR_D1PPRE_DIV8                 RCC_D1CFGR_D1PPRE_DIV8_Msk      /*!< APB3 clock divided by 8 */
+#define RCC_D1CFGR_D1PPRE_DIV16_Pos            (4U)
+#define RCC_D1CFGR_D1PPRE_DIV16_Msk            (0x7UL << RCC_D1CFGR_D1PPRE_DIV16_Pos) /*!< 0x00000070 */
+#define RCC_D1CFGR_D1PPRE_DIV16                RCC_D1CFGR_D1PPRE_DIV16_Msk     /*!< APB3 clock divided by 16 */
+
+#define RCC_D1CFGR_D1CPRE_Pos                  (8U)
+#define RCC_D1CFGR_D1CPRE_Msk                  (0xFUL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000F00 */
+#define RCC_D1CFGR_D1CPRE                      RCC_D1CFGR_D1CPRE_Msk           /*!< D1CPRE[2:0] bits (Domain 1 Core prescaler) */
+#define RCC_D1CFGR_D1CPRE_0                    (0x1UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000100 */
+#define RCC_D1CFGR_D1CPRE_1                    (0x2UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000200 */
+#define RCC_D1CFGR_D1CPRE_2                    (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */
+#define RCC_D1CFGR_D1CPRE_3                    (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */
+
+#define RCC_D1CFGR_D1CPRE_DIV1                 ((uint32_t)0x00000000)          /*!< Domain 1 Core clock not divided */
+#define RCC_D1CFGR_D1CPRE_DIV2_Pos             (11U)
+#define RCC_D1CFGR_D1CPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */
+#define RCC_D1CFGR_D1CPRE_DIV2                 RCC_D1CFGR_D1CPRE_DIV2_Msk      /*!< Domain 1 Core clock divided by 2 */
+#define RCC_D1CFGR_D1CPRE_DIV4_Pos             (8U)
+#define RCC_D1CFGR_D1CPRE_DIV4_Msk             (0x9UL << RCC_D1CFGR_D1CPRE_DIV4_Pos) /*!< 0x00000900 */
+#define RCC_D1CFGR_D1CPRE_DIV4                 RCC_D1CFGR_D1CPRE_DIV4_Msk      /*!< Domain 1 Core clock divided by 4 */
+#define RCC_D1CFGR_D1CPRE_DIV8_Pos             (9U)
+#define RCC_D1CFGR_D1CPRE_DIV8_Msk             (0x5UL << RCC_D1CFGR_D1CPRE_DIV8_Pos) /*!< 0x00000A00 */
+#define RCC_D1CFGR_D1CPRE_DIV8                 RCC_D1CFGR_D1CPRE_DIV8_Msk      /*!< Domain 1 Core clock divided by 8 */
+#define RCC_D1CFGR_D1CPRE_DIV16_Pos            (8U)
+#define RCC_D1CFGR_D1CPRE_DIV16_Msk            (0xBUL << RCC_D1CFGR_D1CPRE_DIV16_Pos) /*!< 0x00000B00 */
+#define RCC_D1CFGR_D1CPRE_DIV16                RCC_D1CFGR_D1CPRE_DIV16_Msk     /*!< Domain 1 Core clock divided by 16 */
+#define RCC_D1CFGR_D1CPRE_DIV64_Pos            (10U)
+#define RCC_D1CFGR_D1CPRE_DIV64_Msk            (0x3UL << RCC_D1CFGR_D1CPRE_DIV64_Pos) /*!< 0x00000C00 */
+#define RCC_D1CFGR_D1CPRE_DIV64                RCC_D1CFGR_D1CPRE_DIV64_Msk     /*!< Domain 1 Core clock divided by 64 */
+#define RCC_D1CFGR_D1CPRE_DIV128_Pos           (8U)
+#define RCC_D1CFGR_D1CPRE_DIV128_Msk           (0xDUL << RCC_D1CFGR_D1CPRE_DIV128_Pos) /*!< 0x00000D00 */
+#define RCC_D1CFGR_D1CPRE_DIV128               RCC_D1CFGR_D1CPRE_DIV128_Msk    /*!< Domain 1 Core clock divided by 128 */
+#define RCC_D1CFGR_D1CPRE_DIV256_Pos           (9U)
+#define RCC_D1CFGR_D1CPRE_DIV256_Msk           (0x7UL << RCC_D1CFGR_D1CPRE_DIV256_Pos) /*!< 0x00000E00 */
+#define RCC_D1CFGR_D1CPRE_DIV256               RCC_D1CFGR_D1CPRE_DIV256_Msk    /*!< Domain 1 Core clock divided by 256 */
+#define RCC_D1CFGR_D1CPRE_DIV512_Pos           (8U)
+#define RCC_D1CFGR_D1CPRE_DIV512_Msk           (0xFUL << RCC_D1CFGR_D1CPRE_DIV512_Pos) /*!< 0x00000F00 */
+#define RCC_D1CFGR_D1CPRE_DIV512               RCC_D1CFGR_D1CPRE_DIV512_Msk    /*!< Domain 1 Core clock divided by 512 */
+
+/********************  Bit definition for RCC_D2CFGR register  ******************/
+/*!< D2PPRE1 configuration */
+#define RCC_D2CFGR_D2PPRE1_Pos                 (4U)
+#define RCC_D2CFGR_D2PPRE1_Msk                 (0x7UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000070 */
+#define RCC_D2CFGR_D2PPRE1                     RCC_D2CFGR_D2PPRE1_Msk          /*!< D1PPRE1[2:0] bits (APB1 prescaler) */
+#define RCC_D2CFGR_D2PPRE1_0                   (0x1UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000010 */
+#define RCC_D2CFGR_D2PPRE1_1                   (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */
+#define RCC_D2CFGR_D2PPRE1_2                   (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */
+
+#define RCC_D2CFGR_D2PPRE1_DIV1                ((uint32_t)0x00000000)          /*!< APB1 clock not divided */
+#define RCC_D2CFGR_D2PPRE1_DIV2_Pos            (6U)
+#define RCC_D2CFGR_D2PPRE1_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */
+#define RCC_D2CFGR_D2PPRE1_DIV2                RCC_D2CFGR_D2PPRE1_DIV2_Msk     /*!< APB1 clock divided by 2 */
+#define RCC_D2CFGR_D2PPRE1_DIV4_Pos            (4U)
+#define RCC_D2CFGR_D2PPRE1_DIV4_Msk            (0x5UL << RCC_D2CFGR_D2PPRE1_DIV4_Pos) /*!< 0x00000050 */
+#define RCC_D2CFGR_D2PPRE1_DIV4                RCC_D2CFGR_D2PPRE1_DIV4_Msk     /*!< APB1 clock divided by 4 */
+#define RCC_D2CFGR_D2PPRE1_DIV8_Pos            (5U)
+#define RCC_D2CFGR_D2PPRE1_DIV8_Msk            (0x3UL << RCC_D2CFGR_D2PPRE1_DIV8_Pos) /*!< 0x00000060 */
+#define RCC_D2CFGR_D2PPRE1_DIV8                RCC_D2CFGR_D2PPRE1_DIV8_Msk     /*!< APB1 clock divided by 8 */
+#define RCC_D2CFGR_D2PPRE1_DIV16_Pos           (4U)
+#define RCC_D2CFGR_D2PPRE1_DIV16_Msk           (0x7UL << RCC_D2CFGR_D2PPRE1_DIV16_Pos) /*!< 0x00000070 */
+#define RCC_D2CFGR_D2PPRE1_DIV16               RCC_D2CFGR_D2PPRE1_DIV16_Msk    /*!< APB1 clock divided by 16 */
+
+/*!< D2PPRE2 configuration */
+#define RCC_D2CFGR_D2PPRE2_Pos                 (8U)
+#define RCC_D2CFGR_D2PPRE2_Msk                 (0x7UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000700 */
+#define RCC_D2CFGR_D2PPRE2                     RCC_D2CFGR_D2PPRE2_Msk          /*!< D2PPRE2[2:0] bits (APB2 prescaler) */
+#define RCC_D2CFGR_D2PPRE2_0                   (0x1UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000100 */
+#define RCC_D2CFGR_D2PPRE2_1                   (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */
+#define RCC_D2CFGR_D2PPRE2_2                   (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */
+
+#define RCC_D2CFGR_D2PPRE2_DIV1                ((uint32_t)0x00000000)          /*!< APB2 clock not divided */
+#define RCC_D2CFGR_D2PPRE2_DIV2_Pos            (10U)
+#define RCC_D2CFGR_D2PPRE2_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */
+#define RCC_D2CFGR_D2PPRE2_DIV2                RCC_D2CFGR_D2PPRE2_DIV2_Msk     /*!< APB2 clock divided by 2 */
+#define RCC_D2CFGR_D2PPRE2_DIV4_Pos            (8U)
+#define RCC_D2CFGR_D2PPRE2_DIV4_Msk            (0x5UL << RCC_D2CFGR_D2PPRE2_DIV4_Pos) /*!< 0x00000500 */
+#define RCC_D2CFGR_D2PPRE2_DIV4                RCC_D2CFGR_D2PPRE2_DIV4_Msk     /*!< APB2 clock divided by 4 */
+#define RCC_D2CFGR_D2PPRE2_DIV8_Pos            (9U)
+#define RCC_D2CFGR_D2PPRE2_DIV8_Msk            (0x3UL << RCC_D2CFGR_D2PPRE2_DIV8_Pos) /*!< 0x00000600 */
+#define RCC_D2CFGR_D2PPRE2_DIV8                RCC_D2CFGR_D2PPRE2_DIV8_Msk     /*!< APB2 clock divided by 8 */
+#define RCC_D2CFGR_D2PPRE2_DIV16_Pos           (8U)
+#define RCC_D2CFGR_D2PPRE2_DIV16_Msk           (0x7UL << RCC_D2CFGR_D2PPRE2_DIV16_Pos) /*!< 0x00000700 */
+#define RCC_D2CFGR_D2PPRE2_DIV16               RCC_D2CFGR_D2PPRE2_DIV16_Msk    /*!< APB2 clock divided by 16 */
+
+/********************  Bit definition for RCC_D3CFGR register  ******************/
+/*!< D3PPRE configuration */
+#define RCC_D3CFGR_D3PPRE_Pos                  (4U)
+#define RCC_D3CFGR_D3PPRE_Msk                  (0x7UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000070 */
+#define RCC_D3CFGR_D3PPRE                      RCC_D3CFGR_D3PPRE_Msk           /*!< D3PPRE1[2:0] bits (APB4 prescaler) */
+#define RCC_D3CFGR_D3PPRE_0                    (0x1UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000010 */
+#define RCC_D3CFGR_D3PPRE_1                    (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */
+#define RCC_D3CFGR_D3PPRE_2                    (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */
+
+#define RCC_D3CFGR_D3PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB4 clock not divided */
+#define RCC_D3CFGR_D3PPRE_DIV2_Pos             (6U)
+#define RCC_D3CFGR_D3PPRE_DIV2_Msk             (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */
+#define RCC_D3CFGR_D3PPRE_DIV2                 RCC_D3CFGR_D3PPRE_DIV2_Msk      /*!< APB4 clock divided by 2 */
+#define RCC_D3CFGR_D3PPRE_DIV4_Pos             (4U)
+#define RCC_D3CFGR_D3PPRE_DIV4_Msk             (0x5UL << RCC_D3CFGR_D3PPRE_DIV4_Pos) /*!< 0x00000050 */
+#define RCC_D3CFGR_D3PPRE_DIV4                 RCC_D3CFGR_D3PPRE_DIV4_Msk      /*!< APB4 clock divided by 4 */
+#define RCC_D3CFGR_D3PPRE_DIV8_Pos             (5U)
+#define RCC_D3CFGR_D3PPRE_DIV8_Msk             (0x3UL << RCC_D3CFGR_D3PPRE_DIV8_Pos) /*!< 0x00000060 */
+#define RCC_D3CFGR_D3PPRE_DIV8                 RCC_D3CFGR_D3PPRE_DIV8_Msk      /*!< APB4 clock divided by 8 */
+#define RCC_D3CFGR_D3PPRE_DIV16_Pos            (4U)
+#define RCC_D3CFGR_D3PPRE_DIV16_Msk            (0x7UL << RCC_D3CFGR_D3PPRE_DIV16_Pos) /*!< 0x00000070 */
+#define RCC_D3CFGR_D3PPRE_DIV16                RCC_D3CFGR_D3PPRE_DIV16_Msk     /*!< APB4 clock divided by 16 */
+
+/********************  Bit definition for RCC_PLLCKSELR register  *************/
+
+#define RCC_PLLCKSELR_PLLSRC_Pos               (0U)
+#define RCC_PLLCKSELR_PLLSRC_Msk               (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
+#define RCC_PLLCKSELR_PLLSRC                   RCC_PLLCKSELR_PLLSRC_Msk
+
+#define RCC_PLLCKSELR_PLLSRC_HSI               ((uint32_t)0x00000000)          /*!< HSI source clock selected */
+#define RCC_PLLCKSELR_PLLSRC_CSI_Pos           (0U)
+#define RCC_PLLCKSELR_PLLSRC_CSI_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
+#define RCC_PLLCKSELR_PLLSRC_CSI               RCC_PLLCKSELR_PLLSRC_CSI_Msk    /*!< CSI source clock selected */
+#define RCC_PLLCKSELR_PLLSRC_HSE_Pos           (1U)
+#define RCC_PLLCKSELR_PLLSRC_HSE_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_HSE_Pos) /*!< 0x00000002 */
+#define RCC_PLLCKSELR_PLLSRC_HSE               RCC_PLLCKSELR_PLLSRC_HSE_Msk    /*!< HSE source clock selected */
+#define RCC_PLLCKSELR_PLLSRC_NONE_Pos          (0U)
+#define RCC_PLLCKSELR_PLLSRC_NONE_Msk          (0x3UL << RCC_PLLCKSELR_PLLSRC_NONE_Pos) /*!< 0x00000003 */
+#define RCC_PLLCKSELR_PLLSRC_NONE              RCC_PLLCKSELR_PLLSRC_NONE_Msk   /*!< No source clock selected  */
+
+#define RCC_PLLCKSELR_DIVM1_Pos                (4U)
+#define RCC_PLLCKSELR_DIVM1_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x000003F0 */
+#define RCC_PLLCKSELR_DIVM1                    RCC_PLLCKSELR_DIVM1_Msk
+#define RCC_PLLCKSELR_DIVM1_0                  (0x01UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000010 */
+#define RCC_PLLCKSELR_DIVM1_1                  (0x02UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000020 */
+#define RCC_PLLCKSELR_DIVM1_2                  (0x04UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000040 */
+#define RCC_PLLCKSELR_DIVM1_3                  (0x08UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000080 */
+#define RCC_PLLCKSELR_DIVM1_4                  (0x10UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000100 */
+#define RCC_PLLCKSELR_DIVM1_5                  (0x20UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000200 */
+
+#define RCC_PLLCKSELR_DIVM2_Pos                (12U)
+#define RCC_PLLCKSELR_DIVM2_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x0003F000 */
+#define RCC_PLLCKSELR_DIVM2                    RCC_PLLCKSELR_DIVM2_Msk
+#define RCC_PLLCKSELR_DIVM2_0                  (0x01UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00001000 */
+#define RCC_PLLCKSELR_DIVM2_1                  (0x02UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00002000 */
+#define RCC_PLLCKSELR_DIVM2_2                  (0x04UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00004000 */
+#define RCC_PLLCKSELR_DIVM2_3                  (0x08UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00008000 */
+#define RCC_PLLCKSELR_DIVM2_4                  (0x10UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00010000 */
+#define RCC_PLLCKSELR_DIVM2_5                  (0x20UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00020000 */
+
+#define RCC_PLLCKSELR_DIVM3_Pos                (20U)
+#define RCC_PLLCKSELR_DIVM3_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x03F00000 */
+#define RCC_PLLCKSELR_DIVM3                    RCC_PLLCKSELR_DIVM3_Msk
+#define RCC_PLLCKSELR_DIVM3_0                  (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00100000 */
+#define RCC_PLLCKSELR_DIVM3_1                  (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00200000 */
+#define RCC_PLLCKSELR_DIVM3_2                  (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00400000 */
+#define RCC_PLLCKSELR_DIVM3_3                  (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00800000 */
+#define RCC_PLLCKSELR_DIVM3_4                  (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x01000000 */
+#define RCC_PLLCKSELR_DIVM3_5                  (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 */
+
+/********************  Bit definition for RCC_PLLCFGR register  ***************/
+
+#define RCC_PLLCFGR_PLL1FRACEN_Pos             (0U)
+#define RCC_PLLCFGR_PLL1FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos) /*!< 0x00000001 */
+#define RCC_PLLCFGR_PLL1FRACEN                 RCC_PLLCFGR_PLL1FRACEN_Msk
+#define RCC_PLLCFGR_PLL1VCOSEL_Pos             (1U)
+#define RCC_PLLCFGR_PLL1VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos) /*!< 0x00000002 */
+#define RCC_PLLCFGR_PLL1VCOSEL                 RCC_PLLCFGR_PLL1VCOSEL_Msk
+#define RCC_PLLCFGR_PLL1RGE_Pos                (2U)
+#define RCC_PLLCFGR_PLL1RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
+#define RCC_PLLCFGR_PLL1RGE                    RCC_PLLCFGR_PLL1RGE_Msk
+#define RCC_PLLCFGR_PLL1RGE_0                  (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */
+#define RCC_PLLCFGR_PLL1RGE_1                  (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */
+#define RCC_PLLCFGR_PLL1RGE_2                  (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */
+#define RCC_PLLCFGR_PLL1RGE_3                  (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
+
+#define RCC_PLLCFGR_PLL2FRACEN_Pos             (4U)
+#define RCC_PLLCFGR_PLL2FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos) /*!< 0x00000010 */
+#define RCC_PLLCFGR_PLL2FRACEN                 RCC_PLLCFGR_PLL2FRACEN_Msk
+#define RCC_PLLCFGR_PLL2VCOSEL_Pos             (5U)
+#define RCC_PLLCFGR_PLL2VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos) /*!< 0x00000020 */
+#define RCC_PLLCFGR_PLL2VCOSEL                 RCC_PLLCFGR_PLL2VCOSEL_Msk
+#define RCC_PLLCFGR_PLL2RGE_Pos                (6U)
+#define RCC_PLLCFGR_PLL2RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */
+#define RCC_PLLCFGR_PLL2RGE                    RCC_PLLCFGR_PLL2RGE_Msk
+#define RCC_PLLCFGR_PLL2RGE_0                  (0x0UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000000 */
+#define RCC_PLLCFGR_PLL2RGE_1                  (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000040 */
+#define RCC_PLLCFGR_PLL2RGE_2                  (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000080 */
+#define RCC_PLLCFGR_PLL2RGE_3                  (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */
+
+#define RCC_PLLCFGR_PLL3FRACEN_Pos             (8U)
+#define RCC_PLLCFGR_PLL3FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos) /*!< 0x00000100 */
+#define RCC_PLLCFGR_PLL3FRACEN                 RCC_PLLCFGR_PLL3FRACEN_Msk
+#define RCC_PLLCFGR_PLL3VCOSEL_Pos             (9U)
+#define RCC_PLLCFGR_PLL3VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos) /*!< 0x00000200 */
+#define RCC_PLLCFGR_PLL3VCOSEL                 RCC_PLLCFGR_PLL3VCOSEL_Msk
+#define RCC_PLLCFGR_PLL3RGE_Pos                (10U)
+#define RCC_PLLCFGR_PLL3RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */
+#define RCC_PLLCFGR_PLL3RGE                    RCC_PLLCFGR_PLL3RGE_Msk
+#define RCC_PLLCFGR_PLL3RGE_0                  (0x0UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000000 */
+#define RCC_PLLCFGR_PLL3RGE_1                  (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000400 */
+#define RCC_PLLCFGR_PLL3RGE_2                  (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000800 */
+#define RCC_PLLCFGR_PLL3RGE_3                  (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */
+
+#define RCC_PLLCFGR_DIVP1EN_Pos                (16U)
+#define RCC_PLLCFGR_DIVP1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP1EN_Pos) /*!< 0x00010000 */
+#define RCC_PLLCFGR_DIVP1EN                    RCC_PLLCFGR_DIVP1EN_Msk
+#define RCC_PLLCFGR_DIVQ1EN_Pos                (17U)
+#define RCC_PLLCFGR_DIVQ1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ1EN_Pos) /*!< 0x00020000 */
+#define RCC_PLLCFGR_DIVQ1EN                    RCC_PLLCFGR_DIVQ1EN_Msk
+#define RCC_PLLCFGR_DIVR1EN_Pos                (18U)
+#define RCC_PLLCFGR_DIVR1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR1EN_Pos) /*!< 0x00040000 */
+#define RCC_PLLCFGR_DIVR1EN                    RCC_PLLCFGR_DIVR1EN_Msk
+
+#define RCC_PLLCFGR_DIVP2EN_Pos                (19U)
+#define RCC_PLLCFGR_DIVP2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP2EN_Pos) /*!< 0x00080000 */
+#define RCC_PLLCFGR_DIVP2EN                    RCC_PLLCFGR_DIVP2EN_Msk
+#define RCC_PLLCFGR_DIVQ2EN_Pos                (20U)
+#define RCC_PLLCFGR_DIVQ2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ2EN_Pos) /*!< 0x00100000 */
+#define RCC_PLLCFGR_DIVQ2EN                    RCC_PLLCFGR_DIVQ2EN_Msk
+#define RCC_PLLCFGR_DIVR2EN_Pos                (21U)
+#define RCC_PLLCFGR_DIVR2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR2EN_Pos) /*!< 0x00200000 */
+#define RCC_PLLCFGR_DIVR2EN                    RCC_PLLCFGR_DIVR2EN_Msk
+
+#define RCC_PLLCFGR_DIVP3EN_Pos                (22U)
+#define RCC_PLLCFGR_DIVP3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP3EN_Pos) /*!< 0x00400000 */
+#define RCC_PLLCFGR_DIVP3EN                    RCC_PLLCFGR_DIVP3EN_Msk
+#define RCC_PLLCFGR_DIVQ3EN_Pos                (23U)
+#define RCC_PLLCFGR_DIVQ3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ3EN_Pos) /*!< 0x00800000 */
+#define RCC_PLLCFGR_DIVQ3EN                    RCC_PLLCFGR_DIVQ3EN_Msk
+#define RCC_PLLCFGR_DIVR3EN_Pos                (24U)
+#define RCC_PLLCFGR_DIVR3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR3EN_Pos) /*!< 0x01000000 */
+#define RCC_PLLCFGR_DIVR3EN                    RCC_PLLCFGR_DIVR3EN_Msk
+
+
+/********************  Bit definition for RCC_PLL1DIVR register  ***************/
+#define RCC_PLL1DIVR_N1_Pos                    (0U)
+#define RCC_PLL1DIVR_N1_Msk                    (0x1FFUL << RCC_PLL1DIVR_N1_Pos) /*!< 0x000001FF */
+#define RCC_PLL1DIVR_N1                        RCC_PLL1DIVR_N1_Msk
+#define RCC_PLL1DIVR_P1_Pos                    (9U)
+#define RCC_PLL1DIVR_P1_Msk                    (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */
+#define RCC_PLL1DIVR_P1                        RCC_PLL1DIVR_P1_Msk
+#define RCC_PLL1DIVR_Q1_Pos                    (16U)
+#define RCC_PLL1DIVR_Q1_Msk                    (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */
+#define RCC_PLL1DIVR_Q1                        RCC_PLL1DIVR_Q1_Msk
+#define RCC_PLL1DIVR_R1_Pos                    (24U)
+#define RCC_PLL1DIVR_R1_Msk                    (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
+#define RCC_PLL1DIVR_R1                        RCC_PLL1DIVR_R1_Msk
+
+/********************  Bit definition for RCC_PLL1FRACR register  ***************/
+#define RCC_PLL1FRACR_FRACN1_Pos               (3U)
+#define RCC_PLL1FRACR_FRACN1_Msk               (0x1FFFUL << RCC_PLL1FRACR_FRACN1_Pos) /*!< 0x0000FFF8 */
+#define RCC_PLL1FRACR_FRACN1                   RCC_PLL1FRACR_FRACN1_Msk
+
+/********************  Bit definition for RCC_PLL2DIVR register  ***************/
+#define RCC_PLL2DIVR_N2_Pos                    (0U)
+#define RCC_PLL2DIVR_N2_Msk                    (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */
+#define RCC_PLL2DIVR_N2                        RCC_PLL2DIVR_N2_Msk
+#define RCC_PLL2DIVR_P2_Pos                    (9U)
+#define RCC_PLL2DIVR_P2_Msk                    (0x7FUL << RCC_PLL2DIVR_P2_Pos) /*!< 0x0000FE00 */
+#define RCC_PLL2DIVR_P2                        RCC_PLL2DIVR_P2_Msk
+#define RCC_PLL2DIVR_Q2_Pos                    (16U)
+#define RCC_PLL2DIVR_Q2_Msk                    (0x7FUL << RCC_PLL2DIVR_Q2_Pos) /*!< 0x007F0000 */
+#define RCC_PLL2DIVR_Q2                        RCC_PLL2DIVR_Q2_Msk
+#define RCC_PLL2DIVR_R2_Pos                    (24U)
+#define RCC_PLL2DIVR_R2_Msk                    (0x7FUL << RCC_PLL2DIVR_R2_Pos) /*!< 0x7F000000 */
+#define RCC_PLL2DIVR_R2                        RCC_PLL2DIVR_R2_Msk
+
+/********************  Bit definition for RCC_PLL2FRACR register  ***************/
+#define RCC_PLL2FRACR_FRACN2_Pos               (3U)
+#define RCC_PLL2FRACR_FRACN2_Msk               (0x1FFFUL << RCC_PLL2FRACR_FRACN2_Pos) /*!< 0x0000FFF8 */
+#define RCC_PLL2FRACR_FRACN2                   RCC_PLL2FRACR_FRACN2_Msk
+
+/********************  Bit definition for RCC_PLL3DIVR register  ***************/
+#define RCC_PLL3DIVR_N3_Pos                    (0U)
+#define RCC_PLL3DIVR_N3_Msk                    (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */
+#define RCC_PLL3DIVR_N3                        RCC_PLL3DIVR_N3_Msk
+#define RCC_PLL3DIVR_P3_Pos                    (9U)
+#define RCC_PLL3DIVR_P3_Msk                    (0x7FUL << RCC_PLL3DIVR_P3_Pos) /*!< 0x0000FE00 */
+#define RCC_PLL3DIVR_P3                        RCC_PLL3DIVR_P3_Msk
+#define RCC_PLL3DIVR_Q3_Pos                    (16U)
+#define RCC_PLL3DIVR_Q3_Msk                    (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */
+#define RCC_PLL3DIVR_Q3                        RCC_PLL3DIVR_Q3_Msk
+#define RCC_PLL3DIVR_R3_Pos                    (24U)
+#define RCC_PLL3DIVR_R3_Msk                    (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */
+#define RCC_PLL3DIVR_R3                        RCC_PLL3DIVR_R3_Msk
+
+/********************  Bit definition for RCC_PLL3FRACR register  ***************/
+#define RCC_PLL3FRACR_FRACN3_Pos               (3U)
+#define RCC_PLL3FRACR_FRACN3_Msk               (0x1FFFUL << RCC_PLL3FRACR_FRACN3_Pos) /*!< 0x0000FFF8 */
+#define RCC_PLL3FRACR_FRACN3                   RCC_PLL3FRACR_FRACN3_Msk
+
+/********************  Bit definition for RCC_D1CCIPR register  ***************/
+#define RCC_D1CCIPR_FMCSEL_Pos                 (0U)
+#define RCC_D1CCIPR_FMCSEL_Msk                 (0x3UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000003 */
+#define RCC_D1CCIPR_FMCSEL                     RCC_D1CCIPR_FMCSEL_Msk
+#define RCC_D1CCIPR_FMCSEL_0                   (0x1UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000001 */
+#define RCC_D1CCIPR_FMCSEL_1                   (0x2UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000002 */
+#define RCC_D1CCIPR_QSPISEL_Pos                (4U)
+#define RCC_D1CCIPR_QSPISEL_Msk                (0x3UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000030 */
+#define RCC_D1CCIPR_QSPISEL                    RCC_D1CCIPR_QSPISEL_Msk
+#define RCC_D1CCIPR_QSPISEL_0                  (0x1UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000010 */
+#define RCC_D1CCIPR_QSPISEL_1                  (0x2UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000020 */
+#define RCC_D1CCIPR_SDMMCSEL_Pos               (16U)
+#define RCC_D1CCIPR_SDMMCSEL_Msk               (0x1UL << RCC_D1CCIPR_SDMMCSEL_Pos) /*!< 0x00010000 */
+#define RCC_D1CCIPR_SDMMCSEL                   RCC_D1CCIPR_SDMMCSEL_Msk
+#define RCC_D1CCIPR_CKPERSEL_Pos               (28U)
+#define RCC_D1CCIPR_CKPERSEL_Msk               (0x3UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x30000000 */
+#define RCC_D1CCIPR_CKPERSEL                   RCC_D1CCIPR_CKPERSEL_Msk
+#define RCC_D1CCIPR_CKPERSEL_0                 (0x1UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x10000000 */
+#define RCC_D1CCIPR_CKPERSEL_1                 (0x2UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x20000000 */
+
+/********************  Bit definition for RCC_D2CCIP1R register  ***************/
+#define RCC_D2CCIP1R_SAI1SEL_Pos               (0U)
+#define RCC_D2CCIP1R_SAI1SEL_Msk               (0x7UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000007 */
+#define RCC_D2CCIP1R_SAI1SEL                   RCC_D2CCIP1R_SAI1SEL_Msk
+#define RCC_D2CCIP1R_SAI1SEL_0                 (0x1UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000001 */
+#define RCC_D2CCIP1R_SAI1SEL_1                 (0x2UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000002 */
+#define RCC_D2CCIP1R_SAI1SEL_2                 (0x4UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000004 */
+
+#define RCC_D2CCIP1R_SAI23SEL_Pos              (6U)
+#define RCC_D2CCIP1R_SAI23SEL_Msk              (0x7UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x000001C0 */
+#define RCC_D2CCIP1R_SAI23SEL                  RCC_D2CCIP1R_SAI23SEL_Msk
+#define RCC_D2CCIP1R_SAI23SEL_0                (0x1UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000040 */
+#define RCC_D2CCIP1R_SAI23SEL_1                (0x2UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000080 */
+#define RCC_D2CCIP1R_SAI23SEL_2                (0x4UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000100 */
+
+#define RCC_D2CCIP1R_SPI123SEL_Pos             (12U)
+#define RCC_D2CCIP1R_SPI123SEL_Msk             (0x7UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00007000 */
+#define RCC_D2CCIP1R_SPI123SEL                 RCC_D2CCIP1R_SPI123SEL_Msk
+#define RCC_D2CCIP1R_SPI123SEL_0               (0x1UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00001000 */
+#define RCC_D2CCIP1R_SPI123SEL_1               (0x2UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00002000 */
+#define RCC_D2CCIP1R_SPI123SEL_2               (0x4UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00004000 */
+
+#define RCC_D2CCIP1R_SPI45SEL_Pos              (16U)
+#define RCC_D2CCIP1R_SPI45SEL_Msk              (0x7UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00070000 */
+#define RCC_D2CCIP1R_SPI45SEL                  RCC_D2CCIP1R_SPI45SEL_Msk
+#define RCC_D2CCIP1R_SPI45SEL_0                (0x1UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00010000 */
+#define RCC_D2CCIP1R_SPI45SEL_1                (0x2UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00020000 */
+#define RCC_D2CCIP1R_SPI45SEL_2                (0x4UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00040000 */
+
+#define RCC_D2CCIP1R_SPDIFSEL_Pos              (20U)
+#define RCC_D2CCIP1R_SPDIFSEL_Msk              (0x3UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00300000 */
+#define RCC_D2CCIP1R_SPDIFSEL                  RCC_D2CCIP1R_SPDIFSEL_Msk
+#define RCC_D2CCIP1R_SPDIFSEL_0                (0x1UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00100000 */
+#define RCC_D2CCIP1R_SPDIFSEL_1                (0x2UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00200000 */
+
+#define RCC_D2CCIP1R_DFSDM1SEL_Pos             (24U)
+#define RCC_D2CCIP1R_DFSDM1SEL_Msk             (0x1UL << RCC_D2CCIP1R_DFSDM1SEL_Pos) /*!< 0x01000000 */
+#define RCC_D2CCIP1R_DFSDM1SEL                 RCC_D2CCIP1R_DFSDM1SEL_Msk
+
+#define RCC_D2CCIP1R_FDCANSEL_Pos              (28U)
+#define RCC_D2CCIP1R_FDCANSEL_Msk              (0x3UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x30000000 */
+#define RCC_D2CCIP1R_FDCANSEL                  RCC_D2CCIP1R_FDCANSEL_Msk
+#define RCC_D2CCIP1R_FDCANSEL_0                (0x1UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x10000000 */
+#define RCC_D2CCIP1R_FDCANSEL_1                (0x2UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x20000000 */
+
+#define RCC_D2CCIP1R_SWPSEL_Pos                (31U)
+#define RCC_D2CCIP1R_SWPSEL_Msk                (0x1UL << RCC_D2CCIP1R_SWPSEL_Pos) /*!< 0x80000000 */
+#define RCC_D2CCIP1R_SWPSEL                    RCC_D2CCIP1R_SWPSEL_Msk
+
+/********************  Bit definition for RCC_D2CCIP2R register  ***************/
+#define RCC_D2CCIP2R_USART16SEL_Pos            (3U)
+#define RCC_D2CCIP2R_USART16SEL_Msk            (0x7UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000038 */
+#define RCC_D2CCIP2R_USART16SEL                RCC_D2CCIP2R_USART16SEL_Msk
+#define RCC_D2CCIP2R_USART16SEL_0              (0x1UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000008 */
+#define RCC_D2CCIP2R_USART16SEL_1              (0x2UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000010 */
+#define RCC_D2CCIP2R_USART16SEL_2              (0x4UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000020 */
+
+#define RCC_D2CCIP2R_USART28SEL_Pos            (0U)
+#define RCC_D2CCIP2R_USART28SEL_Msk            (0x7UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000007 */
+#define RCC_D2CCIP2R_USART28SEL                RCC_D2CCIP2R_USART28SEL_Msk
+#define RCC_D2CCIP2R_USART28SEL_0              (0x1UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000001 */
+#define RCC_D2CCIP2R_USART28SEL_1              (0x2UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000002 */
+#define RCC_D2CCIP2R_USART28SEL_2              (0x4UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000004 */
+
+#define RCC_D2CCIP2R_RNGSEL_Pos                (8U)
+#define RCC_D2CCIP2R_RNGSEL_Msk                (0x3UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000300 */
+#define RCC_D2CCIP2R_RNGSEL                    RCC_D2CCIP2R_RNGSEL_Msk
+#define RCC_D2CCIP2R_RNGSEL_0                  (0x1UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000100 */
+#define RCC_D2CCIP2R_RNGSEL_1                  (0x2UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000200 */
+
+#define RCC_D2CCIP2R_I2C123SEL_Pos             (12U)
+#define RCC_D2CCIP2R_I2C123SEL_Msk             (0x3UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00003000 */
+#define RCC_D2CCIP2R_I2C123SEL                 RCC_D2CCIP2R_I2C123SEL_Msk
+#define RCC_D2CCIP2R_I2C123SEL_0               (0x1UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00001000 */
+#define RCC_D2CCIP2R_I2C123SEL_1               (0x2UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00002000 */
+
+#define RCC_D2CCIP2R_USBSEL_Pos                (20U)
+#define RCC_D2CCIP2R_USBSEL_Msk                (0x3UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00300000 */
+#define RCC_D2CCIP2R_USBSEL                    RCC_D2CCIP2R_USBSEL_Msk
+#define RCC_D2CCIP2R_USBSEL_0                  (0x1UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00100000 */
+#define RCC_D2CCIP2R_USBSEL_1                  (0x2UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00200000 */
+
+#define RCC_D2CCIP2R_CECSEL_Pos                (22U)
+#define RCC_D2CCIP2R_CECSEL_Msk                (0x3UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00C00000 */
+#define RCC_D2CCIP2R_CECSEL                    RCC_D2CCIP2R_CECSEL_Msk
+#define RCC_D2CCIP2R_CECSEL_0                  (0x1UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00400000 */
+#define RCC_D2CCIP2R_CECSEL_1                  (0x2UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00800000 */
+
+#define RCC_D2CCIP2R_LPTIM1SEL_Pos             (28U)
+#define RCC_D2CCIP2R_LPTIM1SEL_Msk             (0x7UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x70000000 */
+#define RCC_D2CCIP2R_LPTIM1SEL                 RCC_D2CCIP2R_LPTIM1SEL_Msk
+#define RCC_D2CCIP2R_LPTIM1SEL_0               (0x1UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x10000000 */
+#define RCC_D2CCIP2R_LPTIM1SEL_1               (0x2UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x20000000 */
+#define RCC_D2CCIP2R_LPTIM1SEL_2               (0x4UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for RCC_D3CCIPR register  ***************/
+#define RCC_D3CCIPR_LPUART1SEL_Pos             (0U)
+#define RCC_D3CCIPR_LPUART1SEL_Msk             (0x7UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000007 */
+#define RCC_D3CCIPR_LPUART1SEL                 RCC_D3CCIPR_LPUART1SEL_Msk
+#define RCC_D3CCIPR_LPUART1SEL_0               (0x1UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000001 */
+#define RCC_D3CCIPR_LPUART1SEL_1               (0x2UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000002 */
+#define RCC_D3CCIPR_LPUART1SEL_2               (0x4UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000004 */
+
+#define RCC_D3CCIPR_I2C4SEL_Pos                (8U)
+#define RCC_D3CCIPR_I2C4SEL_Msk                (0x3UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000300 */
+#define RCC_D3CCIPR_I2C4SEL                    RCC_D3CCIPR_I2C4SEL_Msk
+#define RCC_D3CCIPR_I2C4SEL_0                  (0x1UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000100 */
+#define RCC_D3CCIPR_I2C4SEL_1                  (0x2UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000200 */
+
+#define RCC_D3CCIPR_LPTIM2SEL_Pos              (10U)
+#define RCC_D3CCIPR_LPTIM2SEL_Msk              (0x7UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001C00 */
+#define RCC_D3CCIPR_LPTIM2SEL                  RCC_D3CCIPR_LPTIM2SEL_Msk
+#define RCC_D3CCIPR_LPTIM2SEL_0                (0x1UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000400 */
+#define RCC_D3CCIPR_LPTIM2SEL_1                (0x2UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000800 */
+#define RCC_D3CCIPR_LPTIM2SEL_2                (0x4UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001000 */
+
+#define RCC_D3CCIPR_LPTIM345SEL_Pos            (13U)
+#define RCC_D3CCIPR_LPTIM345SEL_Msk            (0x7UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x0000E000 */
+#define RCC_D3CCIPR_LPTIM345SEL                RCC_D3CCIPR_LPTIM345SEL_Msk
+#define RCC_D3CCIPR_LPTIM345SEL_0              (0x1UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00002000 */
+#define RCC_D3CCIPR_LPTIM345SEL_1              (0x2UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00004000 */
+#define RCC_D3CCIPR_LPTIM345SEL_2              (0x4UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00008000 */
+
+#define RCC_D3CCIPR_SAI4ASEL_Pos               (21U)
+#define RCC_D3CCIPR_SAI4ASEL_Msk               (0x7UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00E00000 */
+#define RCC_D3CCIPR_SAI4ASEL                   RCC_D3CCIPR_SAI4ASEL_Msk
+#define RCC_D3CCIPR_SAI4ASEL_0                 (0x1UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00200000 */
+#define RCC_D3CCIPR_SAI4ASEL_1                 (0x2UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00400000 */
+#define RCC_D3CCIPR_SAI4ASEL_2                 (0x4UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00800000 */
+
+#define RCC_D3CCIPR_SAI4BSEL_Pos               (24U)
+#define RCC_D3CCIPR_SAI4BSEL_Msk               (0x7UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x07000000 */
+#define RCC_D3CCIPR_SAI4BSEL                   RCC_D3CCIPR_SAI4BSEL_Msk
+#define RCC_D3CCIPR_SAI4BSEL_0                 (0x1UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x01000000 */
+#define RCC_D3CCIPR_SAI4BSEL_1                 (0x2UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x02000000 */
+#define RCC_D3CCIPR_SAI4BSEL_2                 (0x4UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x04000000 */
+
+#define RCC_D3CCIPR_ADCSEL_Pos                 (16U)
+#define RCC_D3CCIPR_ADCSEL_Msk                 (0x3UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00030000 */
+#define RCC_D3CCIPR_ADCSEL                     RCC_D3CCIPR_ADCSEL_Msk
+#define RCC_D3CCIPR_ADCSEL_0                   (0x1UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00010000 */
+#define RCC_D3CCIPR_ADCSEL_1                   (0x2UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00020000 */
+
+#define RCC_D3CCIPR_SPI6SEL_Pos                (28U)
+#define RCC_D3CCIPR_SPI6SEL_Msk                (0x7UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x70000000 */
+#define RCC_D3CCIPR_SPI6SEL                    RCC_D3CCIPR_SPI6SEL_Msk
+#define RCC_D3CCIPR_SPI6SEL_0                  (0x1UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x10000000 */
+#define RCC_D3CCIPR_SPI6SEL_1                  (0x2UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x20000000 */
+#define RCC_D3CCIPR_SPI6SEL_2                  (0x4UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x40000000 */
+/********************  Bit definition for RCC_CIER register  ******************/
+#define RCC_CIER_LSIRDYIE_Pos                  (0U)
+#define RCC_CIER_LSIRDYIE_Msk                  (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
+#define RCC_CIER_LSIRDYIE                      RCC_CIER_LSIRDYIE_Msk
+#define RCC_CIER_LSERDYIE_Pos                  (1U)
+#define RCC_CIER_LSERDYIE_Msk                  (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
+#define RCC_CIER_LSERDYIE                      RCC_CIER_LSERDYIE_Msk
+#define RCC_CIER_HSIRDYIE_Pos                  (2U)
+#define RCC_CIER_HSIRDYIE_Msk                  (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
+#define RCC_CIER_HSIRDYIE                      RCC_CIER_HSIRDYIE_Msk
+#define RCC_CIER_HSERDYIE_Pos                  (3U)
+#define RCC_CIER_HSERDYIE_Msk                  (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
+#define RCC_CIER_HSERDYIE                      RCC_CIER_HSERDYIE_Msk
+#define RCC_CIER_CSIRDYIE_Pos                  (4U)
+#define RCC_CIER_CSIRDYIE_Msk                  (0x1UL << RCC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */
+#define RCC_CIER_CSIRDYIE                      RCC_CIER_CSIRDYIE_Msk
+#define RCC_CIER_HSI48RDYIE_Pos                (5U)
+#define RCC_CIER_HSI48RDYIE_Msk                (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000020 */
+#define RCC_CIER_HSI48RDYIE                    RCC_CIER_HSI48RDYIE_Msk
+#define RCC_CIER_PLL1RDYIE_Pos                 (6U)
+#define RCC_CIER_PLL1RDYIE_Msk                 (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000040 */
+#define RCC_CIER_PLL1RDYIE                     RCC_CIER_PLL1RDYIE_Msk
+#define RCC_CIER_PLL2RDYIE_Pos                 (7U)
+#define RCC_CIER_PLL2RDYIE_Msk                 (0x1UL << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000080 */
+#define RCC_CIER_PLL2RDYIE                     RCC_CIER_PLL2RDYIE_Msk
+#define RCC_CIER_PLL3RDYIE_Pos                 (8U)
+#define RCC_CIER_PLL3RDYIE_Msk                 (0x1UL << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000100 */
+#define RCC_CIER_PLL3RDYIE                     RCC_CIER_PLL3RDYIE_Msk
+#define RCC_CIER_LSECSSIE_Pos                  (9U)
+#define RCC_CIER_LSECSSIE_Msk                  (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */
+#define RCC_CIER_LSECSSIE                      RCC_CIER_LSECSSIE_Msk
+
+/********************  Bit definition for RCC_CIFR register  ******************/
+#define RCC_CIFR_LSIRDYF_Pos                   (0U)
+#define RCC_CIFR_LSIRDYF_Msk                   (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIFR_LSIRDYF                       RCC_CIFR_LSIRDYF_Msk
+#define RCC_CIFR_LSERDYF_Pos                   (1U)
+#define RCC_CIFR_LSERDYF_Msk                   (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIFR_LSERDYF                       RCC_CIFR_LSERDYF_Msk
+#define RCC_CIFR_HSIRDYF_Pos                   (2U)
+#define RCC_CIFR_HSIRDYF_Msk                   (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIFR_HSIRDYF                       RCC_CIFR_HSIRDYF_Msk
+#define RCC_CIFR_HSERDYF_Pos                   (3U)
+#define RCC_CIFR_HSERDYF_Msk                   (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIFR_HSERDYF                       RCC_CIFR_HSERDYF_Msk
+#define RCC_CIFR_CSIRDYF_Pos                   (4U)
+#define RCC_CIFR_CSIRDYF_Msk                   (0x1UL << RCC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIFR_CSIRDYF                       RCC_CIFR_CSIRDYF_Msk
+#define RCC_CIFR_HSI48RDYF_Pos                 (5U)
+#define RCC_CIFR_HSI48RDYF_Msk                 (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000020 */
+#define RCC_CIFR_HSI48RDYF                     RCC_CIFR_HSI48RDYF_Msk
+#define RCC_CIFR_PLLRDYF_Pos                   (6U)
+#define RCC_CIFR_PLLRDYF_Msk                   (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000040 */
+#define RCC_CIFR_PLLRDYF                       RCC_CIFR_PLLRDYF_Msk
+#define RCC_CIFR_PLL2RDYF_Pos                  (7U)
+#define RCC_CIFR_PLL2RDYF_Msk                  (0x1UL << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000080 */
+#define RCC_CIFR_PLL2RDYF                      RCC_CIFR_PLL2RDYF_Msk
+#define RCC_CIFR_PLL3RDYF_Pos                  (8U)
+#define RCC_CIFR_PLL3RDYF_Msk                  (0x1UL << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000100 */
+#define RCC_CIFR_PLL3RDYF                      RCC_CIFR_PLL3RDYF_Msk
+#define RCC_CIFR_LSECSSF_Pos                   (9U)
+#define RCC_CIFR_LSECSSF_Msk                   (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */
+#define RCC_CIFR_LSECSSF                       RCC_CIFR_LSECSSF_Msk
+#define RCC_CIFR_HSECSSF_Pos                   (10U)
+#define RCC_CIFR_HSECSSF_Msk                   (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */
+#define RCC_CIFR_HSECSSF                       RCC_CIFR_HSECSSF_Msk
+
+/********************  Bit definition for RCC_CICR register  ******************/
+#define RCC_CICR_LSIRDYC_Pos                   (0U)
+#define RCC_CICR_LSIRDYC_Msk                   (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
+#define RCC_CICR_LSIRDYC                       RCC_CICR_LSIRDYC_Msk
+#define RCC_CICR_LSERDYC_Pos                   (1U)
+#define RCC_CICR_LSERDYC_Msk                   (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
+#define RCC_CICR_LSERDYC                       RCC_CICR_LSERDYC_Msk
+#define RCC_CICR_HSIRDYC_Pos                   (2U)
+#define RCC_CICR_HSIRDYC_Msk                   (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */
+#define RCC_CICR_HSIRDYC                       RCC_CICR_HSIRDYC_Msk
+#define RCC_CICR_HSERDYC_Pos                   (3U)
+#define RCC_CICR_HSERDYC_Msk                   (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */
+#define RCC_CICR_HSERDYC                       RCC_CICR_HSERDYC_Msk
+#define RCC_CICR_CSIRDYC_Pos                   (4U)
+#define RCC_CICR_CSIRDYC_Msk                   (0x1UL << RCC_CICR_CSIRDYC_Pos) /*!< 0x00000010 */
+#define RCC_CICR_CSIRDYC                       RCC_CICR_CSIRDYC_Msk
+#define RCC_CICR_HSI48RDYC_Pos                 (5U)
+#define RCC_CICR_HSI48RDYC_Msk                 (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000020 */
+#define RCC_CICR_HSI48RDYC                     RCC_CICR_HSI48RDYC_Msk
+#define RCC_CICR_PLLRDYC_Pos                   (6U)
+#define RCC_CICR_PLLRDYC_Msk                   (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000040 */
+#define RCC_CICR_PLLRDYC                       RCC_CICR_PLLRDYC_Msk
+#define RCC_CICR_PLL2RDYC_Pos                  (7U)
+#define RCC_CICR_PLL2RDYC_Msk                  (0x1UL << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000080 */
+#define RCC_CICR_PLL2RDYC                      RCC_CICR_PLL2RDYC_Msk
+#define RCC_CICR_PLL3RDYC_Pos                  (8U)
+#define RCC_CICR_PLL3RDYC_Msk                  (0x1UL << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000100 */
+#define RCC_CICR_PLL3RDYC                      RCC_CICR_PLL3RDYC_Msk
+#define RCC_CICR_LSECSSC_Pos                   (9U)
+#define RCC_CICR_LSECSSC_Msk                   (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */
+#define RCC_CICR_LSECSSC                       RCC_CICR_LSECSSC_Msk
+#define RCC_CICR_HSECSSC_Pos                   (10U)
+#define RCC_CICR_HSECSSC_Msk                   (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */
+#define RCC_CICR_HSECSSC                       RCC_CICR_HSECSSC_Msk
+
+/********************  Bit definition for RCC_BDCR register  ******************/
+#define RCC_BDCR_LSEON_Pos                     (0U)
+#define RCC_BDCR_LSEON_Msk                     (0x1UL << RCC_BDCR_LSEON_Pos)   /*!< 0x00000001 */
+#define RCC_BDCR_LSEON                         RCC_BDCR_LSEON_Msk
+#define RCC_BDCR_LSERDY_Pos                    (1U)
+#define RCC_BDCR_LSERDY_Msk                    (0x1UL << RCC_BDCR_LSERDY_Pos)  /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY                        RCC_BDCR_LSERDY_Msk
+#define RCC_BDCR_LSEBYP_Pos                    (2U)
+#define RCC_BDCR_LSEBYP_Msk                    (0x1UL << RCC_BDCR_LSEBYP_Pos)  /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP                        RCC_BDCR_LSEBYP_Msk
+
+#define RCC_BDCR_LSEDRV_Pos                    (3U)
+#define RCC_BDCR_LSEDRV_Msk                    (0x3UL << RCC_BDCR_LSEDRV_Pos)  /*!< 0x00000018 */
+#define RCC_BDCR_LSEDRV                        RCC_BDCR_LSEDRV_Msk
+#define RCC_BDCR_LSEDRV_0                      (0x1UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000008 */
+#define RCC_BDCR_LSEDRV_1                      (0x2UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000010 */
+
+#define RCC_BDCR_LSECSSON_Pos                  (5U)
+#define RCC_BDCR_LSECSSON_Msk                  (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */
+#define RCC_BDCR_LSECSSON                      RCC_BDCR_LSECSSON_Msk
+#define RCC_BDCR_LSECSSD_Pos                   (6U)
+#define RCC_BDCR_LSECSSD_Msk                   (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */
+#define RCC_BDCR_LSECSSD                       RCC_BDCR_LSECSSD_Msk
+
+#define RCC_BDCR_RTCSEL_Pos                    (8U)
+#define RCC_BDCR_RTCSEL_Msk                    (0x3UL << RCC_BDCR_RTCSEL_Pos)  /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL                        RCC_BDCR_RTCSEL_Msk
+#define RCC_BDCR_RTCSEL_0                      (0x1UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1                      (0x2UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000200 */
+
+#define RCC_BDCR_RTCEN_Pos                     (15U)
+#define RCC_BDCR_RTCEN_Msk                     (0x1UL << RCC_BDCR_RTCEN_Pos)   /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN                         RCC_BDCR_RTCEN_Msk
+#define RCC_BDCR_BDRST_Pos                     (16U)
+#define RCC_BDCR_BDRST_Msk                     (0x1UL << RCC_BDCR_BDRST_Pos)   /*!< 0x00010000 */
+#define RCC_BDCR_BDRST                         RCC_BDCR_BDRST_Msk
+/********************  Bit definition for RCC_CSR register  *******************/
+#define RCC_CSR_LSION_Pos                      (0U)
+#define RCC_CSR_LSION_Msk                      (0x1UL << RCC_CSR_LSION_Pos)    /*!< 0x00000001 */
+#define RCC_CSR_LSION                          RCC_CSR_LSION_Msk
+#define RCC_CSR_LSIRDY_Pos                     (1U)
+#define RCC_CSR_LSIRDY_Msk                     (0x1UL << RCC_CSR_LSIRDY_Pos)   /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY                         RCC_CSR_LSIRDY_Msk
+
+
+/********************  Bit definition for RCC_AHB3ENR register  **************/
+#define RCC_AHB3ENR_MDMAEN_Pos                 (0U)
+#define RCC_AHB3ENR_MDMAEN_Msk                 (0x1UL << RCC_AHB3ENR_MDMAEN_Pos)       /*!< 0x00000001 */
+#define RCC_AHB3ENR_MDMAEN                     RCC_AHB3ENR_MDMAEN_Msk
+#define RCC_AHB3ENR_DMA2DEN_Pos                (4U)
+#define RCC_AHB3ENR_DMA2DEN_Msk                (0x1UL << RCC_AHB3ENR_DMA2DEN_Pos)      /*!< 0x00000010 */
+#define RCC_AHB3ENR_DMA2DEN                    RCC_AHB3ENR_DMA2DEN_Msk
+#define RCC_AHB3ENR_JPGDECEN_Pos               (5U)
+#define RCC_AHB3ENR_JPGDECEN_Msk               (0x1UL << RCC_AHB3ENR_JPGDECEN_Pos)     /*!< 0x00000020 */
+#define RCC_AHB3ENR_JPGDECEN                   RCC_AHB3ENR_JPGDECEN_Msk
+#define RCC_AHB3ENR_FMCEN_Pos                  (12U)
+#define RCC_AHB3ENR_FMCEN_Msk                  (0x1UL << RCC_AHB3ENR_FMCEN_Pos)        /*!< 0x00001000 */
+#define RCC_AHB3ENR_FMCEN                      RCC_AHB3ENR_FMCEN_Msk
+#define RCC_AHB3ENR_QSPIEN_Pos                 (14U)
+#define RCC_AHB3ENR_QSPIEN_Msk                 (0x1UL << RCC_AHB3ENR_QSPIEN_Pos)       /*!< 0x00004000 */
+#define RCC_AHB3ENR_QSPIEN                     RCC_AHB3ENR_QSPIEN_Msk
+#define RCC_AHB3ENR_SDMMC1EN_Pos               (16U)
+#define RCC_AHB3ENR_SDMMC1EN_Msk               (0x1UL << RCC_AHB3ENR_SDMMC1EN_Pos)     /*!< 0x00010000 */
+#define RCC_AHB3ENR_SDMMC1EN                   RCC_AHB3ENR_SDMMC1EN_Msk
+
+/********************  Bit definition for RCC_AHB1ENR register  ***************/
+#define RCC_AHB1ENR_DMA1EN_Pos                 (0U)
+#define RCC_AHB1ENR_DMA1EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)          /*!< 0x00000001 */
+#define RCC_AHB1ENR_DMA1EN                     RCC_AHB1ENR_DMA1EN_Msk
+#define RCC_AHB1ENR_DMA2EN_Pos                 (1U)
+#define RCC_AHB1ENR_DMA2EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)          /*!< 0x00000002 */
+#define RCC_AHB1ENR_DMA2EN                     RCC_AHB1ENR_DMA2EN_Msk
+#define RCC_AHB1ENR_ADC12EN_Pos                (5U)
+#define RCC_AHB1ENR_ADC12EN_Msk                (0x1UL << RCC_AHB1ENR_ADC12EN_Pos)         /*!< 0x00000020 */
+#define RCC_AHB1ENR_ADC12EN                    RCC_AHB1ENR_ADC12EN_Msk
+#define RCC_AHB1ENR_ETH1MACEN_Pos              (15U)
+#define RCC_AHB1ENR_ETH1MACEN_Msk              (0x1UL << RCC_AHB1ENR_ETH1MACEN_Pos)       /*!< 0x00008000 */
+#define RCC_AHB1ENR_ETH1MACEN                  RCC_AHB1ENR_ETH1MACEN_Msk
+#define RCC_AHB1ENR_ETH1TXEN_Pos               (16U)
+#define RCC_AHB1ENR_ETH1TXEN_Msk               (0x1UL << RCC_AHB1ENR_ETH1TXEN_Pos)        /*!< 0x00010000 */
+#define RCC_AHB1ENR_ETH1TXEN                   RCC_AHB1ENR_ETH1TXEN_Msk
+#define RCC_AHB1ENR_ETH1RXEN_Pos               (17U)
+#define RCC_AHB1ENR_ETH1RXEN_Msk               (0x1UL << RCC_AHB1ENR_ETH1RXEN_Pos)        /*!< 0x00020000 */
+#define RCC_AHB1ENR_ETH1RXEN                   RCC_AHB1ENR_ETH1RXEN_Msk
+#define RCC_AHB1ENR_USB1OTGHSEN_Pos            (25U)
+#define RCC_AHB1ENR_USB1OTGHSEN_Msk            (0x1UL << RCC_AHB1ENR_USB1OTGHSEN_Pos)     /*!< 0x02000000 */
+#define RCC_AHB1ENR_USB1OTGHSEN                RCC_AHB1ENR_USB1OTGHSEN_Msk
+#define RCC_AHB1ENR_USB1OTGHSULPIEN_Pos        (26U)
+#define RCC_AHB1ENR_USB1OTGHSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_USB1OTGHSULPIEN_Pos) /*!< 0x04000000 */
+#define RCC_AHB1ENR_USB1OTGHSULPIEN            RCC_AHB1ENR_USB1OTGHSULPIEN_Msk
+#define RCC_AHB1ENR_USB2OTGFSEN_Pos            (27U)
+#define RCC_AHB1ENR_USB2OTGFSEN_Msk            (0x1UL << RCC_AHB1ENR_USB2OTGFSEN_Pos)     /*!< 0x08000000 */
+#define RCC_AHB1ENR_USB2OTGFSEN                RCC_AHB1ENR_USB2OTGFSEN_Msk
+#define RCC_AHB1ENR_USB2OTGFSULPIEN_Pos        (28U)
+#define RCC_AHB1ENR_USB2OTGFSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_USB2OTGFSULPIEN_Pos) /*!< 0x10000000 */
+#define RCC_AHB1ENR_USB2OTGFSULPIEN            RCC_AHB1ENR_USB2OTGFSULPIEN_Msk
+
+/* Legacy define */
+#define RCC_AHB1ENR_USB2OTGHSEN_Pos            RCC_AHB1ENR_USB2OTGFSEN_Pos
+#define RCC_AHB1ENR_USB2OTGHSEN_Msk            RCC_AHB1ENR_USB2OTGFSEN_Msk
+#define RCC_AHB1ENR_USB2OTGHSEN                RCC_AHB1ENR_USB2OTGFSEN
+#define RCC_AHB1ENR_USB2OTGHSULPIEN_Pos        RCC_AHB1ENR_USB2OTGFSULPIEN_Pos
+#define RCC_AHB1ENR_USB2OTGHSULPIEN_Msk        RCC_AHB1ENR_USB2OTGFSULPIEN_Msk
+#define RCC_AHB1ENR_USB2OTGHSULPIEN            RCC_AHB1ENR_USB2OTGFSULPIEN
+
+
+/********************  Bit definition for RCC_AHB2ENR register  ***************/
+#define RCC_AHB2ENR_DCMIEN_Pos                 (0U)
+#define RCC_AHB2ENR_DCMIEN_Msk                 (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)          /*!< 0x00000001 */
+#define RCC_AHB2ENR_DCMIEN                     RCC_AHB2ENR_DCMIEN_Msk
+#define RCC_AHB2ENR_RNGEN_Pos                  (6U)
+#define RCC_AHB2ENR_RNGEN_Msk                  (0x1UL << RCC_AHB2ENR_RNGEN_Pos)           /*!< 0x00000040 */
+#define RCC_AHB2ENR_RNGEN                      RCC_AHB2ENR_RNGEN_Msk
+#define RCC_AHB2ENR_SDMMC2EN_Pos               (9U)
+#define RCC_AHB2ENR_SDMMC2EN_Msk               (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos)        /*!< 0x00000200 */
+#define RCC_AHB2ENR_SDMMC2EN                   RCC_AHB2ENR_SDMMC2EN_Msk
+#define RCC_AHB2ENR_SRAM1EN_Pos                (29U)
+#define RCC_AHB2ENR_SRAM1EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM1EN_Pos)       /*!< 0x20000000 */
+#define RCC_AHB2ENR_SRAM1EN                    RCC_AHB2ENR_SRAM1EN_Msk
+#define RCC_AHB2ENR_SRAM2EN_Pos                (30U)
+#define RCC_AHB2ENR_SRAM2EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos)       /*!< 0x40000000 */
+#define RCC_AHB2ENR_SRAM2EN                    RCC_AHB2ENR_SRAM2EN_Msk
+#define RCC_AHB2ENR_SRAM3EN_Pos                (31U)
+#define RCC_AHB2ENR_SRAM3EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM3EN_Pos)       /*!< 0x80000000 */
+#define RCC_AHB2ENR_SRAM3EN                    RCC_AHB2ENR_SRAM3EN_Msk
+
+/* Legacy define */
+#define RCC_AHB2ENR_D2SRAM1EN_Pos              RCC_AHB2ENR_SRAM1EN_Pos
+#define RCC_AHB2ENR_D2SRAM1EN_Msk              RCC_AHB2ENR_SRAM1EN_Msk
+#define RCC_AHB2ENR_D2SRAM1EN                  RCC_AHB2ENR_SRAM1EN
+#define RCC_AHB2ENR_D2SRAM2EN_Pos              RCC_AHB2ENR_SRAM2EN_Pos
+#define RCC_AHB2ENR_D2SRAM2EN_Msk              RCC_AHB2ENR_SRAM2EN_Msk
+#define RCC_AHB2ENR_D2SRAM2EN                  RCC_AHB2ENR_SRAM2EN
+#define RCC_AHB2ENR_D2SRAM3EN_Pos              RCC_AHB2ENR_SRAM3EN_Pos
+#define RCC_AHB2ENR_D2SRAM3EN_Msk              RCC_AHB2ENR_SRAM3EN_Msk
+#define RCC_AHB2ENR_D2SRAM3EN                  RCC_AHB2ENR_SRAM3EN
+
+/********************  Bit definition for RCC_AHB4ENR register  ******************/
+#define RCC_AHB4ENR_GPIOAEN_Pos                (0U)
+#define RCC_AHB4ENR_GPIOAEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos)         /*!< 0x00000001 */
+#define RCC_AHB4ENR_GPIOAEN                    RCC_AHB4ENR_GPIOAEN_Msk
+#define RCC_AHB4ENR_GPIOBEN_Pos                (1U)
+#define RCC_AHB4ENR_GPIOBEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos)         /*!< 0x00000002 */
+#define RCC_AHB4ENR_GPIOBEN                    RCC_AHB4ENR_GPIOBEN_Msk
+#define RCC_AHB4ENR_GPIOCEN_Pos                (2U)
+#define RCC_AHB4ENR_GPIOCEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos)         /*!< 0x00000004 */
+#define RCC_AHB4ENR_GPIOCEN                    RCC_AHB4ENR_GPIOCEN_Msk
+#define RCC_AHB4ENR_GPIODEN_Pos                (3U)
+#define RCC_AHB4ENR_GPIODEN_Msk                (0x1UL << RCC_AHB4ENR_GPIODEN_Pos)         /*!< 0x00000008 */
+#define RCC_AHB4ENR_GPIODEN                    RCC_AHB4ENR_GPIODEN_Msk
+#define RCC_AHB4ENR_GPIOEEN_Pos                (4U)
+#define RCC_AHB4ENR_GPIOEEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos)         /*!< 0x00000010 */
+#define RCC_AHB4ENR_GPIOEEN                    RCC_AHB4ENR_GPIOEEN_Msk
+#define RCC_AHB4ENR_GPIOFEN_Pos                (5U)
+#define RCC_AHB4ENR_GPIOFEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos)         /*!< 0x00000020 */
+#define RCC_AHB4ENR_GPIOFEN                    RCC_AHB4ENR_GPIOFEN_Msk
+#define RCC_AHB4ENR_GPIOGEN_Pos                (6U)
+#define RCC_AHB4ENR_GPIOGEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos)         /*!< 0x00000040 */
+#define RCC_AHB4ENR_GPIOGEN                    RCC_AHB4ENR_GPIOGEN_Msk
+#define RCC_AHB4ENR_GPIOHEN_Pos                (7U)
+#define RCC_AHB4ENR_GPIOHEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos)         /*!< 0x00000080 */
+#define RCC_AHB4ENR_GPIOHEN                    RCC_AHB4ENR_GPIOHEN_Msk
+#define RCC_AHB4ENR_GPIOIEN_Pos                (8U)
+#define RCC_AHB4ENR_GPIOIEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOIEN_Pos)         /*!< 0x00000100 */
+#define RCC_AHB4ENR_GPIOIEN                    RCC_AHB4ENR_GPIOIEN_Msk
+#define RCC_AHB4ENR_GPIOJEN_Pos                (9U)
+#define RCC_AHB4ENR_GPIOJEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOJEN_Pos)         /*!< 0x00000200 */
+#define RCC_AHB4ENR_GPIOJEN                    RCC_AHB4ENR_GPIOJEN_Msk
+#define RCC_AHB4ENR_GPIOKEN_Pos                (10U)
+#define RCC_AHB4ENR_GPIOKEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOKEN_Pos)         /*!< 0x00000400 */
+#define RCC_AHB4ENR_GPIOKEN                    RCC_AHB4ENR_GPIOKEN_Msk
+#define RCC_AHB4ENR_CRCEN_Pos                  (19U)
+#define RCC_AHB4ENR_CRCEN_Msk                  (0x1UL << RCC_AHB4ENR_CRCEN_Pos)           /*!< 0x00080000 */
+#define RCC_AHB4ENR_CRCEN                      RCC_AHB4ENR_CRCEN_Msk
+#define RCC_AHB4ENR_BDMAEN_Pos                 (21U)
+#define RCC_AHB4ENR_BDMAEN_Msk                 (0x1UL << RCC_AHB4ENR_BDMAEN_Pos)          /*!< 0x00200000 */
+#define RCC_AHB4ENR_BDMAEN                     RCC_AHB4ENR_BDMAEN_Msk
+#define RCC_AHB4ENR_ADC3EN_Pos                 (24U)
+#define RCC_AHB4ENR_ADC3EN_Msk                 (0x1UL << RCC_AHB4ENR_ADC3EN_Pos)          /*!< 0x01000000 */
+#define RCC_AHB4ENR_ADC3EN                     RCC_AHB4ENR_ADC3EN_Msk
+#define RCC_AHB4ENR_HSEMEN_Pos                 (25U)
+#define RCC_AHB4ENR_HSEMEN_Msk                 (0x1UL << RCC_AHB4ENR_HSEMEN_Pos)          /*!< 0x02000000 */
+#define RCC_AHB4ENR_HSEMEN                     RCC_AHB4ENR_HSEMEN_Msk
+#define RCC_AHB4ENR_BKPRAMEN_Pos               (28U)
+#define RCC_AHB4ENR_BKPRAMEN_Msk               (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos)        /*!< 0x10000000 */
+#define RCC_AHB4ENR_BKPRAMEN                   RCC_AHB4ENR_BKPRAMEN_Msk
+
+/********************  Bit definition for RCC_APB3ENR register  ******************/
+#define RCC_APB3ENR_LTDCEN_Pos                 (3U)
+#define RCC_APB3ENR_LTDCEN_Msk                 (0x1UL << RCC_APB3ENR_LTDCEN_Pos) /*!< 0x00000008 */
+#define RCC_APB3ENR_LTDCEN                     RCC_APB3ENR_LTDCEN_Msk
+#define RCC_APB3ENR_WWDG1EN_Pos                (6U)
+#define RCC_APB3ENR_WWDG1EN_Msk                (0x1UL << RCC_APB3ENR_WWDG1EN_Pos) /*!< 0x00000040 */
+#define RCC_APB3ENR_WWDG1EN                    RCC_APB3ENR_WWDG1EN_Msk
+
+/********************  Bit definition for RCC_APB1LENR register  ******************/
+
+#define RCC_APB1LENR_TIM2EN_Pos                (0U)
+#define RCC_APB1LENR_TIM2EN_Msk                (0x1UL << RCC_APB1LENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1LENR_TIM2EN                    RCC_APB1LENR_TIM2EN_Msk
+#define RCC_APB1LENR_TIM3EN_Pos                (1U)
+#define RCC_APB1LENR_TIM3EN_Msk                (0x1UL << RCC_APB1LENR_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1LENR_TIM3EN                    RCC_APB1LENR_TIM3EN_Msk
+#define RCC_APB1LENR_TIM4EN_Pos                (2U)
+#define RCC_APB1LENR_TIM4EN_Msk                (0x1UL << RCC_APB1LENR_TIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1LENR_TIM4EN                    RCC_APB1LENR_TIM4EN_Msk
+#define RCC_APB1LENR_TIM5EN_Pos                (3U)
+#define RCC_APB1LENR_TIM5EN_Msk                (0x1UL << RCC_APB1LENR_TIM5EN_Pos) /*!< 0x00000008 */
+#define RCC_APB1LENR_TIM5EN                    RCC_APB1LENR_TIM5EN_Msk
+#define RCC_APB1LENR_TIM6EN_Pos                (4U)
+#define RCC_APB1LENR_TIM6EN_Msk                (0x1UL << RCC_APB1LENR_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_APB1LENR_TIM6EN                    RCC_APB1LENR_TIM6EN_Msk
+#define RCC_APB1LENR_TIM7EN_Pos                (5U)
+#define RCC_APB1LENR_TIM7EN_Msk                (0x1UL << RCC_APB1LENR_TIM7EN_Pos) /*!< 0x00000020 */
+#define RCC_APB1LENR_TIM7EN                    RCC_APB1LENR_TIM7EN_Msk
+#define RCC_APB1LENR_TIM12EN_Pos               (6U)
+#define RCC_APB1LENR_TIM12EN_Msk               (0x1UL << RCC_APB1LENR_TIM12EN_Pos) /*!< 0x00000040 */
+#define RCC_APB1LENR_TIM12EN                   RCC_APB1LENR_TIM12EN_Msk
+#define RCC_APB1LENR_TIM13EN_Pos               (7U)
+#define RCC_APB1LENR_TIM13EN_Msk               (0x1UL << RCC_APB1LENR_TIM13EN_Pos) /*!< 0x00000080 */
+#define RCC_APB1LENR_TIM13EN                   RCC_APB1LENR_TIM13EN_Msk
+#define RCC_APB1LENR_TIM14EN_Pos               (8U)
+#define RCC_APB1LENR_TIM14EN_Msk               (0x1UL << RCC_APB1LENR_TIM14EN_Pos) /*!< 0x00000100 */
+#define RCC_APB1LENR_TIM14EN                   RCC_APB1LENR_TIM14EN_Msk
+#define RCC_APB1LENR_LPTIM1EN_Pos              (9U)
+#define RCC_APB1LENR_LPTIM1EN_Msk              (0x1UL << RCC_APB1LENR_LPTIM1EN_Pos) /*!< 0x00000200 */
+#define RCC_APB1LENR_LPTIM1EN                  RCC_APB1LENR_LPTIM1EN_Msk
+
+
+#define RCC_APB1LENR_SPI2EN_Pos                (14U)
+#define RCC_APB1LENR_SPI2EN_Msk                (0x1UL << RCC_APB1LENR_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1LENR_SPI2EN                    RCC_APB1LENR_SPI2EN_Msk
+#define RCC_APB1LENR_SPI3EN_Pos                (15U)
+#define RCC_APB1LENR_SPI3EN_Msk                (0x1UL << RCC_APB1LENR_SPI3EN_Pos) /*!< 0x00008000 */
+#define RCC_APB1LENR_SPI3EN                    RCC_APB1LENR_SPI3EN_Msk
+#define RCC_APB1LENR_SPDIFRXEN_Pos             (16U)
+#define RCC_APB1LENR_SPDIFRXEN_Msk             (0x1UL << RCC_APB1LENR_SPDIFRXEN_Pos) /*!< 0x00010000 */
+#define RCC_APB1LENR_SPDIFRXEN                 RCC_APB1LENR_SPDIFRXEN_Msk
+#define RCC_APB1LENR_USART2EN_Pos              (17U)
+#define RCC_APB1LENR_USART2EN_Msk              (0x1UL << RCC_APB1LENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1LENR_USART2EN                  RCC_APB1LENR_USART2EN_Msk
+#define RCC_APB1LENR_USART3EN_Pos              (18U)
+#define RCC_APB1LENR_USART3EN_Msk              (0x1UL << RCC_APB1LENR_USART3EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1LENR_USART3EN                  RCC_APB1LENR_USART3EN_Msk
+#define RCC_APB1LENR_UART4EN_Pos               (19U)
+#define RCC_APB1LENR_UART4EN_Msk               (0x1UL << RCC_APB1LENR_UART4EN_Pos) /*!< 0x00080000 */
+#define RCC_APB1LENR_UART4EN                   RCC_APB1LENR_UART4EN_Msk
+#define RCC_APB1LENR_UART5EN_Pos               (20U)
+#define RCC_APB1LENR_UART5EN_Msk               (0x1UL << RCC_APB1LENR_UART5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB1LENR_UART5EN                   RCC_APB1LENR_UART5EN_Msk
+#define RCC_APB1LENR_I2C1EN_Pos                (21U)
+#define RCC_APB1LENR_I2C1EN_Msk                (0x1UL << RCC_APB1LENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1LENR_I2C1EN                    RCC_APB1LENR_I2C1EN_Msk
+#define RCC_APB1LENR_I2C2EN_Pos                (22U)
+#define RCC_APB1LENR_I2C2EN_Msk                (0x1UL << RCC_APB1LENR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1LENR_I2C2EN                    RCC_APB1LENR_I2C2EN_Msk
+#define RCC_APB1LENR_I2C3EN_Pos                (23U)
+#define RCC_APB1LENR_I2C3EN_Msk                (0x1UL << RCC_APB1LENR_I2C3EN_Pos) /*!< 0x00800000 */
+#define RCC_APB1LENR_I2C3EN                    RCC_APB1LENR_I2C3EN_Msk
+#define RCC_APB1LENR_CECEN_Pos                 (27U)
+#define RCC_APB1LENR_CECEN_Msk                 (0x1UL << RCC_APB1LENR_CECEN_Pos) /*!< 0x08000000 */
+#define RCC_APB1LENR_CECEN                     RCC_APB1LENR_CECEN_Msk
+#define RCC_APB1LENR_DAC12EN_Pos               (29U)
+#define RCC_APB1LENR_DAC12EN_Msk               (0x1UL << RCC_APB1LENR_DAC12EN_Pos) /*!< 0x20000000 */
+#define RCC_APB1LENR_DAC12EN                   RCC_APB1LENR_DAC12EN_Msk
+#define RCC_APB1LENR_UART7EN_Pos               (30U)
+#define RCC_APB1LENR_UART7EN_Msk               (0x1UL << RCC_APB1LENR_UART7EN_Pos) /*!< 0x40000000 */
+#define RCC_APB1LENR_UART7EN                   RCC_APB1LENR_UART7EN_Msk
+#define RCC_APB1LENR_UART8EN_Pos               (31U)
+#define RCC_APB1LENR_UART8EN_Msk               (0x1UL << RCC_APB1LENR_UART8EN_Pos) /*!< 0x80000000 */
+#define RCC_APB1LENR_UART8EN                   RCC_APB1LENR_UART8EN_Msk
+
+/* Legacy define */
+#define RCC_APB1LENR_HDMICECEN_Pos             RCC_APB1LENR_CECEN_Pos
+#define RCC_APB1LENR_HDMICECEN_Msk             RCC_APB1LENR_CECEN_Msk
+#define RCC_APB1LENR_HDMICECEN                 RCC_APB1LENR_CECEN
+/********************  Bit definition for RCC_APB1HENR register  ******************/
+#define RCC_APB1HENR_CRSEN_Pos                 (1U)
+#define RCC_APB1HENR_CRSEN_Msk                 (0x1UL << RCC_APB1HENR_CRSEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1HENR_CRSEN                     RCC_APB1HENR_CRSEN_Msk
+#define RCC_APB1HENR_SWPMIEN_Pos               (2U)
+#define RCC_APB1HENR_SWPMIEN_Msk               (0x1UL << RCC_APB1HENR_SWPMIEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1HENR_SWPMIEN                   RCC_APB1HENR_SWPMIEN_Msk
+#define RCC_APB1HENR_OPAMPEN_Pos               (4U)
+#define RCC_APB1HENR_OPAMPEN_Msk               (0x1UL << RCC_APB1HENR_OPAMPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1HENR_OPAMPEN                   RCC_APB1HENR_OPAMPEN_Msk
+#define RCC_APB1HENR_MDIOSEN_Pos               (5U)
+#define RCC_APB1HENR_MDIOSEN_Msk               (0x1UL << RCC_APB1HENR_MDIOSEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1HENR_MDIOSEN                   RCC_APB1HENR_MDIOSEN_Msk
+#define RCC_APB1HENR_FDCANEN_Pos               (8U)
+#define RCC_APB1HENR_FDCANEN_Msk               (0x1UL << RCC_APB1HENR_FDCANEN_Pos) /*!< 0x00000100 */
+#define RCC_APB1HENR_FDCANEN                   RCC_APB1HENR_FDCANEN_Msk
+
+/********************  Bit definition for RCC_APB2ENR register  ******************/
+#define RCC_APB2ENR_TIM1EN_Pos                 (0U)
+#define RCC_APB2ENR_TIM1EN_Msk                 (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_TIM1EN                     RCC_APB2ENR_TIM1EN_Msk
+#define RCC_APB2ENR_TIM8EN_Pos                 (1U)
+#define RCC_APB2ENR_TIM8EN_Msk                 (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
+#define RCC_APB2ENR_TIM8EN                     RCC_APB2ENR_TIM8EN_Msk
+#define RCC_APB2ENR_USART1EN_Pos               (4U)
+#define RCC_APB2ENR_USART1EN_Msk               (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
+#define RCC_APB2ENR_USART1EN                   RCC_APB2ENR_USART1EN_Msk
+#define RCC_APB2ENR_USART6EN_Pos               (5U)
+#define RCC_APB2ENR_USART6EN_Msk               (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_USART6EN                   RCC_APB2ENR_USART6EN_Msk
+#define RCC_APB2ENR_SPI1EN_Pos                 (12U)
+#define RCC_APB2ENR_SPI1EN_Msk                 (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN                     RCC_APB2ENR_SPI1EN_Msk
+#define RCC_APB2ENR_SPI4EN_Pos                 (13U)
+#define RCC_APB2ENR_SPI4EN_Msk                 (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
+#define RCC_APB2ENR_SPI4EN                     RCC_APB2ENR_SPI4EN_Msk
+#define RCC_APB2ENR_TIM15EN_Pos                (16U)
+#define RCC_APB2ENR_TIM15EN_Msk                (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
+#define RCC_APB2ENR_TIM15EN                    RCC_APB2ENR_TIM15EN_Msk
+#define RCC_APB2ENR_TIM16EN_Pos                (17U)
+#define RCC_APB2ENR_TIM16EN_Msk                (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
+#define RCC_APB2ENR_TIM16EN                    RCC_APB2ENR_TIM16EN_Msk
+#define RCC_APB2ENR_TIM17EN_Pos                (18U)
+#define RCC_APB2ENR_TIM17EN_Msk                (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
+#define RCC_APB2ENR_TIM17EN                    RCC_APB2ENR_TIM17EN_Msk
+#define RCC_APB2ENR_SPI5EN_Pos                 (20U)
+#define RCC_APB2ENR_SPI5EN_Msk                 (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB2ENR_SPI5EN                     RCC_APB2ENR_SPI5EN_Msk
+#define RCC_APB2ENR_SAI1EN_Pos                 (22U)
+#define RCC_APB2ENR_SAI1EN_Msk                 (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */
+#define RCC_APB2ENR_SAI1EN                     RCC_APB2ENR_SAI1EN_Msk
+#define RCC_APB2ENR_SAI2EN_Pos                 (23U)
+#define RCC_APB2ENR_SAI2EN_Msk                 (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */
+#define RCC_APB2ENR_SAI2EN                     RCC_APB2ENR_SAI2EN_Msk
+#define RCC_APB2ENR_SAI3EN_Pos                 (24U)
+#define RCC_APB2ENR_SAI3EN_Msk                 (0x1UL << RCC_APB2ENR_SAI3EN_Pos) /*!< 0x01000000 */
+#define RCC_APB2ENR_SAI3EN                     RCC_APB2ENR_SAI3EN_Msk
+#define RCC_APB2ENR_DFSDM1EN_Pos               (28U)
+#define RCC_APB2ENR_DFSDM1EN_Msk               (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x10000000 */
+#define RCC_APB2ENR_DFSDM1EN                   RCC_APB2ENR_DFSDM1EN_Msk
+#define RCC_APB2ENR_HRTIMEN_Pos                (29U)
+#define RCC_APB2ENR_HRTIMEN_Msk                (0x1UL << RCC_APB2ENR_HRTIMEN_Pos) /*!< 0x20000000 */
+#define RCC_APB2ENR_HRTIMEN                    RCC_APB2ENR_HRTIMEN_Msk
+
+/********************  Bit definition for RCC_APB4ENR register  ******************/
+#define RCC_APB4ENR_SYSCFGEN_Pos               (1U)
+#define RCC_APB4ENR_SYSCFGEN_Msk               (0x1UL << RCC_APB4ENR_SYSCFGEN_Pos) /*!< 0x00000002 */
+#define RCC_APB4ENR_SYSCFGEN                   RCC_APB4ENR_SYSCFGEN_Msk
+#define RCC_APB4ENR_LPUART1EN_Pos              (3U)
+#define RCC_APB4ENR_LPUART1EN_Msk              (0x1UL << RCC_APB4ENR_LPUART1EN_Pos) /*!< 0x00000008 */
+#define RCC_APB4ENR_LPUART1EN                  RCC_APB4ENR_LPUART1EN_Msk
+#define RCC_APB4ENR_SPI6EN_Pos                 (5U)
+#define RCC_APB4ENR_SPI6EN_Msk                 (0x1UL << RCC_APB4ENR_SPI6EN_Pos) /*!< 0x00000020 */
+#define RCC_APB4ENR_SPI6EN                     RCC_APB4ENR_SPI6EN_Msk
+#define RCC_APB4ENR_I2C4EN_Pos                 (7U)
+#define RCC_APB4ENR_I2C4EN_Msk                 (0x1UL << RCC_APB4ENR_I2C4EN_Pos) /*!< 0x00000080 */
+#define RCC_APB4ENR_I2C4EN                     RCC_APB4ENR_I2C4EN_Msk
+#define RCC_APB4ENR_LPTIM2EN_Pos               (9U)
+#define RCC_APB4ENR_LPTIM2EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos) /*!< 0x00000200 */
+#define RCC_APB4ENR_LPTIM2EN                   RCC_APB4ENR_LPTIM2EN_Msk
+#define RCC_APB4ENR_LPTIM3EN_Pos               (10U)
+#define RCC_APB4ENR_LPTIM3EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos) /*!< 0x00000400 */
+#define RCC_APB4ENR_LPTIM3EN                   RCC_APB4ENR_LPTIM3EN_Msk
+#define RCC_APB4ENR_LPTIM4EN_Pos               (11U)
+#define RCC_APB4ENR_LPTIM4EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM4EN_Pos) /*!< 0x00000800 */
+#define RCC_APB4ENR_LPTIM4EN                   RCC_APB4ENR_LPTIM4EN_Msk
+#define RCC_APB4ENR_LPTIM5EN_Pos               (12U)
+#define RCC_APB4ENR_LPTIM5EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM5EN_Pos) /*!< 0x00001000 */
+#define RCC_APB4ENR_LPTIM5EN                   RCC_APB4ENR_LPTIM5EN_Msk
+#define RCC_APB4ENR_COMP12EN_Pos               (14U)
+#define RCC_APB4ENR_COMP12EN_Msk               (0x1UL << RCC_APB4ENR_COMP12EN_Pos) /*!< 0x00004000 */
+#define RCC_APB4ENR_COMP12EN                   RCC_APB4ENR_COMP12EN_Msk
+#define RCC_APB4ENR_VREFEN_Pos                 (15U)
+#define RCC_APB4ENR_VREFEN_Msk                 (0x1UL << RCC_APB4ENR_VREFEN_Pos) /*!< 0x00008000 */
+#define RCC_APB4ENR_VREFEN                     RCC_APB4ENR_VREFEN_Msk
+#define RCC_APB4ENR_RTCAPBEN_Pos               (16U)
+#define RCC_APB4ENR_RTCAPBEN_Msk               (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos) /*!< 0x00010000 */
+#define RCC_APB4ENR_RTCAPBEN                   RCC_APB4ENR_RTCAPBEN_Msk
+#define RCC_APB4ENR_SAI4EN_Pos                 (21U)
+#define RCC_APB4ENR_SAI4EN_Msk                 (0x1UL << RCC_APB4ENR_SAI4EN_Pos) /*!< 0x00200000 */
+#define RCC_APB4ENR_SAI4EN                     RCC_APB4ENR_SAI4EN_Msk
+
+
+/********************  Bit definition for RCC_AHB3RSTR register  ***************/
+#define RCC_AHB3RSTR_MDMARST_Pos               (0U)
+#define RCC_AHB3RSTR_MDMARST_Msk               (0x1UL << RCC_AHB3RSTR_MDMARST_Pos)      /*!< 0x00000001 */
+#define RCC_AHB3RSTR_MDMARST                   RCC_AHB3RSTR_MDMARST_Msk
+#define RCC_AHB3RSTR_DMA2DRST_Pos              (4U)
+#define RCC_AHB3RSTR_DMA2DRST_Msk              (0x1UL << RCC_AHB3RSTR_DMA2DRST_Pos)     /*!< 0x00000010 */
+#define RCC_AHB3RSTR_DMA2DRST                  RCC_AHB3RSTR_DMA2DRST_Msk
+#define RCC_AHB3RSTR_JPGDECRST_Pos             (5U)
+#define RCC_AHB3RSTR_JPGDECRST_Msk             (0x1UL << RCC_AHB3RSTR_JPGDECRST_Pos)    /*!< 0x00000020 */
+#define RCC_AHB3RSTR_JPGDECRST                 RCC_AHB3RSTR_JPGDECRST_Msk
+#define RCC_AHB3RSTR_FMCRST_Pos                (12U)
+#define RCC_AHB3RSTR_FMCRST_Msk                (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)      /*!< 0x00001000 */
+#define RCC_AHB3RSTR_FMCRST                    RCC_AHB3RSTR_FMCRST_Msk
+#define RCC_AHB3RSTR_QSPIRST_Pos               (14U)
+#define RCC_AHB3RSTR_QSPIRST_Msk               (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)     /*!< 0x00004000 */
+#define RCC_AHB3RSTR_QSPIRST                   RCC_AHB3RSTR_QSPIRST_Msk
+#define RCC_AHB3RSTR_SDMMC1RST_Pos             (16U)
+#define RCC_AHB3RSTR_SDMMC1RST_Msk             (0x1UL << RCC_AHB3RSTR_SDMMC1RST_Pos)   /*!< 0x00010000 */
+#define RCC_AHB3RSTR_SDMMC1RST                 RCC_AHB3RSTR_SDMMC1RST_Msk
+
+
+/********************  Bit definition for RCC_AHB1RSTR register  ***************/
+#define RCC_AHB1RSTR_DMA1RST_Pos               (0U)
+#define RCC_AHB1RSTR_DMA1RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)      /*!< 0x00000001 */
+#define RCC_AHB1RSTR_DMA1RST                   RCC_AHB1RSTR_DMA1RST_Msk
+#define RCC_AHB1RSTR_DMA2RST_Pos               (1U)
+#define RCC_AHB1RSTR_DMA2RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)      /*!< 0x00000002 */
+#define RCC_AHB1RSTR_DMA2RST                   RCC_AHB1RSTR_DMA2RST_Msk
+#define RCC_AHB1RSTR_ADC12RST_Pos              (5U)
+#define RCC_AHB1RSTR_ADC12RST_Msk              (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos)     /*!< 0x00000020 */
+#define RCC_AHB1RSTR_ADC12RST                  RCC_AHB1RSTR_ADC12RST_Msk
+#define RCC_AHB1RSTR_ETH1MACRST_Pos            (15U)
+#define RCC_AHB1RSTR_ETH1MACRST_Msk            (0x1UL << RCC_AHB1RSTR_ETH1MACRST_Pos)   /*!< 0x00008000 */
+#define RCC_AHB1RSTR_ETH1MACRST                RCC_AHB1RSTR_ETH1MACRST_Msk
+#define RCC_AHB1RSTR_USB1OTGHSRST_Pos          (25U)
+#define RCC_AHB1RSTR_USB1OTGHSRST_Msk          (0x1UL << RCC_AHB1RSTR_USB1OTGHSRST_Pos) /*!< 0x02000000 */
+#define RCC_AHB1RSTR_USB1OTGHSRST              RCC_AHB1RSTR_USB1OTGHSRST_Msk
+#define RCC_AHB1RSTR_USB2OTGFSRST_Pos          (27U)
+#define RCC_AHB1RSTR_USB2OTGFSRST_Msk          (0x1UL << RCC_AHB1RSTR_USB2OTGFSRST_Pos) /*!< 0x08000000 */
+#define RCC_AHB1RSTR_USB2OTGFSRST              RCC_AHB1RSTR_USB2OTGFSRST_Msk
+
+/* Legacy define */
+#define RCC_AHB1RSTR_USB2OTGHSRST_Pos          RCC_AHB1RSTR_USB2OTGFSRST_Pos
+#define RCC_AHB1RSTR_USB2OTGHSRST_Msk          RCC_AHB1RSTR_USB2OTGFSRST_Msk
+#define RCC_AHB1RSTR_USB2OTGHSRST              RCC_AHB1RSTR_USB2OTGFSRST
+
+/********************  Bit definition for RCC_AHB2RSTR register  ***************/
+#define RCC_AHB2RSTR_DCMIRST_Pos               (0U)
+#define RCC_AHB2RSTR_DCMIRST_Msk               (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)       /*!< 0x00000001 */
+#define RCC_AHB2RSTR_DCMIRST                   RCC_AHB2RSTR_DCMIRST_Msk
+#define RCC_AHB2RSTR_RNGRST_Pos                (6U)
+#define RCC_AHB2RSTR_RNGRST_Msk                (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)        /*!< 0x00000040 */
+#define RCC_AHB2RSTR_RNGRST                    RCC_AHB2RSTR_RNGRST_Msk
+#define RCC_AHB2RSTR_SDMMC2RST_Pos             (9U)
+#define RCC_AHB2RSTR_SDMMC2RST_Msk             (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos)     /*!< 0x00000200 */
+#define RCC_AHB2RSTR_SDMMC2RST                 RCC_AHB2RSTR_SDMMC2RST_Msk
+
+/********************  Bit definition for RCC_AHB4RSTR register  ******************/
+#define RCC_AHB4RSTR_GPIOARST_Pos              (0U)
+#define RCC_AHB4RSTR_GPIOARST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos)      /*!< 0x00000001 */
+#define RCC_AHB4RSTR_GPIOARST                  RCC_AHB4RSTR_GPIOARST_Msk
+#define RCC_AHB4RSTR_GPIOBRST_Pos              (1U)
+#define RCC_AHB4RSTR_GPIOBRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos)      /*!< 0x00000002 */
+#define RCC_AHB4RSTR_GPIOBRST                  RCC_AHB4RSTR_GPIOBRST_Msk
+#define RCC_AHB4RSTR_GPIOCRST_Pos              (2U)
+#define RCC_AHB4RSTR_GPIOCRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos)      /*!< 0x00000004 */
+#define RCC_AHB4RSTR_GPIOCRST                  RCC_AHB4RSTR_GPIOCRST_Msk
+#define RCC_AHB4RSTR_GPIODRST_Pos              (3U)
+#define RCC_AHB4RSTR_GPIODRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos)      /*!< 0x00000008 */
+#define RCC_AHB4RSTR_GPIODRST                  RCC_AHB4RSTR_GPIODRST_Msk
+#define RCC_AHB4RSTR_GPIOERST_Pos              (4U)
+#define RCC_AHB4RSTR_GPIOERST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos)      /*!< 0x00000010 */
+#define RCC_AHB4RSTR_GPIOERST                  RCC_AHB4RSTR_GPIOERST_Msk
+#define RCC_AHB4RSTR_GPIOFRST_Pos              (5U)
+#define RCC_AHB4RSTR_GPIOFRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos)       /*!< 0x00000020 */
+#define RCC_AHB4RSTR_GPIOFRST                  RCC_AHB4RSTR_GPIOFRST_Msk
+#define RCC_AHB4RSTR_GPIOGRST_Pos              (6U)
+#define RCC_AHB4RSTR_GPIOGRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos)       /*!< 0x00000040 */
+#define RCC_AHB4RSTR_GPIOGRST                  RCC_AHB4RSTR_GPIOGRST_Msk
+#define RCC_AHB4RSTR_GPIOHRST_Pos              (7U)
+#define RCC_AHB4RSTR_GPIOHRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos)       /*!< 0x00000080 */
+#define RCC_AHB4RSTR_GPIOHRST                  RCC_AHB4RSTR_GPIOHRST_Msk
+#define RCC_AHB4RSTR_GPIOIRST_Pos              (8U)
+#define RCC_AHB4RSTR_GPIOIRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOIRST_Pos)       /*!< 0x00000100 */
+#define RCC_AHB4RSTR_GPIOIRST                  RCC_AHB4RSTR_GPIOIRST_Msk
+#define RCC_AHB4RSTR_GPIOJRST_Pos              (9U)
+#define RCC_AHB4RSTR_GPIOJRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOJRST_Pos)       /*!< 0x00000200 */
+#define RCC_AHB4RSTR_GPIOJRST                  RCC_AHB4RSTR_GPIOJRST_Msk
+#define RCC_AHB4RSTR_GPIOKRST_Pos              (10U)
+#define RCC_AHB4RSTR_GPIOKRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOKRST_Pos)       /*!< 0x00000400 */
+#define RCC_AHB4RSTR_GPIOKRST                  RCC_AHB4RSTR_GPIOKRST_Msk
+#define RCC_AHB4RSTR_CRCRST_Pos                (19U)
+#define RCC_AHB4RSTR_CRCRST_Msk                (0x1UL << RCC_AHB4RSTR_CRCRST_Pos)         /*!< 0x00080000 */
+#define RCC_AHB4RSTR_CRCRST                    RCC_AHB4RSTR_CRCRST_Msk
+#define RCC_AHB4RSTR_BDMARST_Pos               (21U)
+#define RCC_AHB4RSTR_BDMARST_Msk               (0x1UL << RCC_AHB4RSTR_BDMARST_Pos)        /*!< 0x00200000 */
+#define RCC_AHB4RSTR_BDMARST                   RCC_AHB4RSTR_BDMARST_Msk
+#define RCC_AHB4RSTR_ADC3RST_Pos               (24U)
+#define RCC_AHB4RSTR_ADC3RST_Msk               (0x1UL << RCC_AHB4RSTR_ADC3RST_Pos)        /*!< 0x01000000 */
+#define RCC_AHB4RSTR_ADC3RST                   RCC_AHB4RSTR_ADC3RST_Msk
+#define RCC_AHB4RSTR_HSEMRST_Pos               (25U)
+#define RCC_AHB4RSTR_HSEMRST_Msk               (0x1UL << RCC_AHB4RSTR_HSEMRST_Pos)        /*!< 0x02000000 */
+#define RCC_AHB4RSTR_HSEMRST                   RCC_AHB4RSTR_HSEMRST_Msk
+
+
+/********************  Bit definition for RCC_APB3RSTR register  ******************/
+#define RCC_APB3RSTR_LTDCRST_Pos               (3U)
+#define RCC_APB3RSTR_LTDCRST_Msk               (0x1UL << RCC_APB3RSTR_LTDCRST_Pos) /*!< 0x00000008 */
+#define RCC_APB3RSTR_LTDCRST                   RCC_APB3RSTR_LTDCRST_Msk
+
+/********************  Bit definition for RCC_APB1LRSTR register  ******************/
+
+#define RCC_APB1LRSTR_TIM2RST_Pos              (0U)
+#define RCC_APB1LRSTR_TIM2RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1LRSTR_TIM2RST                  RCC_APB1LRSTR_TIM2RST_Msk
+#define RCC_APB1LRSTR_TIM3RST_Pos              (1U)
+#define RCC_APB1LRSTR_TIM3RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1LRSTR_TIM3RST                  RCC_APB1LRSTR_TIM3RST_Msk
+#define RCC_APB1LRSTR_TIM4RST_Pos              (2U)
+#define RCC_APB1LRSTR_TIM4RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1LRSTR_TIM4RST                  RCC_APB1LRSTR_TIM4RST_Msk
+#define RCC_APB1LRSTR_TIM5RST_Pos              (3U)
+#define RCC_APB1LRSTR_TIM5RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos) /*!< 0x00000008 */
+#define RCC_APB1LRSTR_TIM5RST                  RCC_APB1LRSTR_TIM5RST_Msk
+#define RCC_APB1LRSTR_TIM6RST_Pos              (4U)
+#define RCC_APB1LRSTR_TIM6RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1LRSTR_TIM6RST                  RCC_APB1LRSTR_TIM6RST_Msk
+#define RCC_APB1LRSTR_TIM7RST_Pos              (5U)
+#define RCC_APB1LRSTR_TIM7RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1LRSTR_TIM7RST                  RCC_APB1LRSTR_TIM7RST_Msk
+#define RCC_APB1LRSTR_TIM12RST_Pos             (6U)
+#define RCC_APB1LRSTR_TIM12RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos) /*!< 0x00000040 */
+#define RCC_APB1LRSTR_TIM12RST                 RCC_APB1LRSTR_TIM12RST_Msk
+#define RCC_APB1LRSTR_TIM13RST_Pos             (7U)
+#define RCC_APB1LRSTR_TIM13RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM13RST_Pos) /*!< 0x00000080 */
+#define RCC_APB1LRSTR_TIM13RST                 RCC_APB1LRSTR_TIM13RST_Msk
+#define RCC_APB1LRSTR_TIM14RST_Pos             (8U)
+#define RCC_APB1LRSTR_TIM14RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM14RST_Pos) /*!< 0x00000100 */
+#define RCC_APB1LRSTR_TIM14RST                 RCC_APB1LRSTR_TIM14RST_Msk
+#define RCC_APB1LRSTR_LPTIM1RST_Pos            (9U)
+#define RCC_APB1LRSTR_LPTIM1RST_Msk            (0x1UL << RCC_APB1LRSTR_LPTIM1RST_Pos) /*!< 0x00000200 */
+#define RCC_APB1LRSTR_LPTIM1RST                RCC_APB1LRSTR_LPTIM1RST_Msk
+#define RCC_APB1LRSTR_SPI2RST_Pos              (14U)
+#define RCC_APB1LRSTR_SPI2RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1LRSTR_SPI2RST                  RCC_APB1LRSTR_SPI2RST_Msk
+#define RCC_APB1LRSTR_SPI3RST_Pos              (15U)
+#define RCC_APB1LRSTR_SPI3RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos) /*!< 0x00008000 */
+#define RCC_APB1LRSTR_SPI3RST                  RCC_APB1LRSTR_SPI3RST_Msk
+#define RCC_APB1LRSTR_SPDIFRXRST_Pos           (16U)
+#define RCC_APB1LRSTR_SPDIFRXRST_Msk           (0x1UL << RCC_APB1LRSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */
+#define RCC_APB1LRSTR_SPDIFRXRST               RCC_APB1LRSTR_SPDIFRXRST_Msk
+#define RCC_APB1LRSTR_USART2RST_Pos            (17U)
+#define RCC_APB1LRSTR_USART2RST_Msk            (0x1UL << RCC_APB1LRSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1LRSTR_USART2RST                RCC_APB1LRSTR_USART2RST_Msk
+#define RCC_APB1LRSTR_USART3RST_Pos            (18U)
+#define RCC_APB1LRSTR_USART3RST_Msk            (0x1UL << RCC_APB1LRSTR_USART3RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1LRSTR_USART3RST                RCC_APB1LRSTR_USART3RST_Msk
+#define RCC_APB1LRSTR_UART4RST_Pos             (19U)
+#define RCC_APB1LRSTR_UART4RST_Msk             (0x1UL << RCC_APB1LRSTR_UART4RST_Pos) /*!< 0x00080000 */
+#define RCC_APB1LRSTR_UART4RST                 RCC_APB1LRSTR_UART4RST_Msk
+#define RCC_APB1LRSTR_UART5RST_Pos             (20U)
+#define RCC_APB1LRSTR_UART5RST_Msk             (0x1UL << RCC_APB1LRSTR_UART5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB1LRSTR_UART5RST                 RCC_APB1LRSTR_UART5RST_Msk
+#define RCC_APB1LRSTR_I2C1RST_Pos              (21U)
+#define RCC_APB1LRSTR_I2C1RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1LRSTR_I2C1RST                  RCC_APB1LRSTR_I2C1RST_Msk
+#define RCC_APB1LRSTR_I2C2RST_Pos              (22U)
+#define RCC_APB1LRSTR_I2C2RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1LRSTR_I2C2RST                  RCC_APB1LRSTR_I2C2RST_Msk
+#define RCC_APB1LRSTR_I2C3RST_Pos              (23U)
+#define RCC_APB1LRSTR_I2C3RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C3RST_Pos) /*!< 0x00800000 */
+#define RCC_APB1LRSTR_I2C3RST                  RCC_APB1LRSTR_I2C3RST_Msk
+#define RCC_APB1LRSTR_CECRST_Pos               (27U)
+#define RCC_APB1LRSTR_CECRST_Msk               (0x1UL << RCC_APB1LRSTR_CECRST_Pos) /*!< 0x08000000 */
+#define RCC_APB1LRSTR_CECRST                   RCC_APB1LRSTR_CECRST_Msk
+#define RCC_APB1LRSTR_DAC12RST_Pos             (29U)
+#define RCC_APB1LRSTR_DAC12RST_Msk             (0x1UL << RCC_APB1LRSTR_DAC12RST_Pos) /*!< 0x20000000 */
+#define RCC_APB1LRSTR_DAC12RST                 RCC_APB1LRSTR_DAC12RST_Msk
+#define RCC_APB1LRSTR_UART7RST_Pos             (30U)
+#define RCC_APB1LRSTR_UART7RST_Msk             (0x1UL << RCC_APB1LRSTR_UART7RST_Pos) /*!< 0x40000000 */
+#define RCC_APB1LRSTR_UART7RST                 RCC_APB1LRSTR_UART7RST_Msk
+#define RCC_APB1LRSTR_UART8RST_Pos             (31U)
+#define RCC_APB1LRSTR_UART8RST_Msk             (0x1UL << RCC_APB1LRSTR_UART8RST_Pos) /*!< 0x80000000 */
+#define RCC_APB1LRSTR_UART8RST                 RCC_APB1LRSTR_UART8RST_Msk
+
+/* Legacy define */
+#define RCC_APB1LRSTR_HDMICECRST_Pos           RCC_APB1LRSTR_CECRST_Pos
+#define RCC_APB1LRSTR_HDMICECRST_Msk           RCC_APB1LRSTR_CECRST_Msk
+#define RCC_APB1LRSTR_HDMICECRST               RCC_APB1LRSTR_CECRST
+/********************  Bit definition for RCC_APB1HRSTR register  ******************/
+#define RCC_APB1HRSTR_CRSRST_Pos               (1U)
+#define RCC_APB1HRSTR_CRSRST_Msk               (0x1UL << RCC_APB1HRSTR_CRSRST_Pos) /*!< 0x00000002 */
+#define RCC_APB1HRSTR_CRSRST                   RCC_APB1HRSTR_CRSRST_Msk
+#define RCC_APB1HRSTR_SWPMIRST_Pos             (2U)
+#define RCC_APB1HRSTR_SWPMIRST_Msk             (0x1UL << RCC_APB1HRSTR_SWPMIRST_Pos) /*!< 0x00000004 */
+#define RCC_APB1HRSTR_SWPMIRST                 RCC_APB1HRSTR_SWPMIRST_Msk
+#define RCC_APB1HRSTR_OPAMPRST_Pos             (4U)
+#define RCC_APB1HRSTR_OPAMPRST_Msk             (0x1UL << RCC_APB1HRSTR_OPAMPRST_Pos) /*!< 0x00000010 */
+#define RCC_APB1HRSTR_OPAMPRST                 RCC_APB1HRSTR_OPAMPRST_Msk
+#define RCC_APB1HRSTR_MDIOSRST_Pos             (5U)
+#define RCC_APB1HRSTR_MDIOSRST_Msk             (0x1UL << RCC_APB1HRSTR_MDIOSRST_Pos) /*!< 0x00000020 */
+#define RCC_APB1HRSTR_MDIOSRST                 RCC_APB1HRSTR_MDIOSRST_Msk
+#define RCC_APB1HRSTR_FDCANRST_Pos             (8U)
+#define RCC_APB1HRSTR_FDCANRST_Msk             (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos) /*!< 0x00000100 */
+#define RCC_APB1HRSTR_FDCANRST                 RCC_APB1HRSTR_FDCANRST_Msk
+
+/********************  Bit definition for RCC_APB2RSTR register  ******************/
+#define RCC_APB2RSTR_TIM1RST_Pos               (0U)
+#define RCC_APB2RSTR_TIM1RST_Msk               (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_TIM1RST                   RCC_APB2RSTR_TIM1RST_Msk
+#define RCC_APB2RSTR_TIM8RST_Pos               (1U)
+#define RCC_APB2RSTR_TIM8RST_Msk               (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
+#define RCC_APB2RSTR_TIM8RST                   RCC_APB2RSTR_TIM8RST_Msk
+#define RCC_APB2RSTR_USART1RST_Pos             (4U)
+#define RCC_APB2RSTR_USART1RST_Msk             (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTR_USART1RST                 RCC_APB2RSTR_USART1RST_Msk
+#define RCC_APB2RSTR_USART6RST_Pos             (5U)
+#define RCC_APB2RSTR_USART6RST_Msk             (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_USART6RST                 RCC_APB2RSTR_USART6RST_Msk
+#define RCC_APB2RSTR_SPI1RST_Pos               (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk               (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST                   RCC_APB2RSTR_SPI1RST_Msk
+#define RCC_APB2RSTR_SPI4RST_Pos               (13U)
+#define RCC_APB2RSTR_SPI4RST_Msk               (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
+#define RCC_APB2RSTR_SPI4RST                   RCC_APB2RSTR_SPI4RST_Msk
+#define RCC_APB2RSTR_TIM15RST_Pos              (16U)
+#define RCC_APB2RSTR_TIM15RST_Msk              (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
+#define RCC_APB2RSTR_TIM15RST                  RCC_APB2RSTR_TIM15RST_Msk
+#define RCC_APB2RSTR_TIM16RST_Pos              (17U)
+#define RCC_APB2RSTR_TIM16RST_Msk              (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
+#define RCC_APB2RSTR_TIM16RST                  RCC_APB2RSTR_TIM16RST_Msk
+#define RCC_APB2RSTR_TIM17RST_Pos              (18U)
+#define RCC_APB2RSTR_TIM17RST_Msk              (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
+#define RCC_APB2RSTR_TIM17RST                  RCC_APB2RSTR_TIM17RST_Msk
+#define RCC_APB2RSTR_SPI5RST_Pos               (20U)
+#define RCC_APB2RSTR_SPI5RST_Msk               (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB2RSTR_SPI5RST                   RCC_APB2RSTR_SPI5RST_Msk
+#define RCC_APB2RSTR_SAI1RST_Pos               (22U)
+#define RCC_APB2RSTR_SAI1RST_Msk               (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */
+#define RCC_APB2RSTR_SAI1RST                   RCC_APB2RSTR_SAI1RST_Msk
+#define RCC_APB2RSTR_SAI2RST_Pos               (23U)
+#define RCC_APB2RSTR_SAI2RST_Msk               (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */
+#define RCC_APB2RSTR_SAI2RST                   RCC_APB2RSTR_SAI2RST_Msk
+#define RCC_APB2RSTR_SAI3RST_Pos               (24U)
+#define RCC_APB2RSTR_SAI3RST_Msk               (0x1UL << RCC_APB2RSTR_SAI3RST_Pos) /*!< 0x01000000 */
+#define RCC_APB2RSTR_SAI3RST                   RCC_APB2RSTR_SAI3RST_Msk
+#define RCC_APB2RSTR_DFSDM1RST_Pos             (28U)
+#define RCC_APB2RSTR_DFSDM1RST_Msk             (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x10000000 */
+#define RCC_APB2RSTR_DFSDM1RST                 RCC_APB2RSTR_DFSDM1RST_Msk
+#define RCC_APB2RSTR_HRTIMRST_Pos              (29U)
+#define RCC_APB2RSTR_HRTIMRST_Msk              (0x1UL << RCC_APB2RSTR_HRTIMRST_Pos) /*!< 0x20000000 */
+#define RCC_APB2RSTR_HRTIMRST                  RCC_APB2RSTR_HRTIMRST_Msk
+
+/********************  Bit definition for RCC_APB4RSTR register  ******************/
+#define RCC_APB4RSTR_SYSCFGRST_Pos             (1U)
+#define RCC_APB4RSTR_SYSCFGRST_Msk             (0x1UL << RCC_APB4RSTR_SYSCFGRST_Pos) /*!< 0x00000002 */
+#define RCC_APB4RSTR_SYSCFGRST                 RCC_APB4RSTR_SYSCFGRST_Msk
+#define RCC_APB4RSTR_LPUART1RST_Pos            (3U)
+#define RCC_APB4RSTR_LPUART1RST_Msk            (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos) /*!< 0x00000008 */
+#define RCC_APB4RSTR_LPUART1RST                RCC_APB4RSTR_LPUART1RST_Msk
+#define RCC_APB4RSTR_SPI6RST_Pos               (5U)
+#define RCC_APB4RSTR_SPI6RST_Msk               (0x1UL << RCC_APB4RSTR_SPI6RST_Pos) /*!< 0x00000020 */
+#define RCC_APB4RSTR_SPI6RST                   RCC_APB4RSTR_SPI6RST_Msk
+#define RCC_APB4RSTR_I2C4RST_Pos               (7U)
+#define RCC_APB4RSTR_I2C4RST_Msk               (0x1UL << RCC_APB4RSTR_I2C4RST_Pos) /*!< 0x00000080 */
+#define RCC_APB4RSTR_I2C4RST                   RCC_APB4RSTR_I2C4RST_Msk
+#define RCC_APB4RSTR_LPTIM2RST_Pos             (9U)
+#define RCC_APB4RSTR_LPTIM2RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos) /*!< 0x00000200 */
+#define RCC_APB4RSTR_LPTIM2RST                 RCC_APB4RSTR_LPTIM2RST_Msk
+#define RCC_APB4RSTR_LPTIM3RST_Pos             (10U)
+#define RCC_APB4RSTR_LPTIM3RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos) /*!< 0x00000400 */
+#define RCC_APB4RSTR_LPTIM3RST                 RCC_APB4RSTR_LPTIM3RST_Msk
+#define RCC_APB4RSTR_LPTIM4RST_Pos             (11U)
+#define RCC_APB4RSTR_LPTIM4RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM4RST_Pos) /*!< 0x00000800 */
+#define RCC_APB4RSTR_LPTIM4RST                 RCC_APB4RSTR_LPTIM4RST_Msk
+#define RCC_APB4RSTR_LPTIM5RST_Pos             (12U)
+#define RCC_APB4RSTR_LPTIM5RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM5RST_Pos) /*!< 0x00001000 */
+#define RCC_APB4RSTR_LPTIM5RST                 RCC_APB4RSTR_LPTIM5RST_Msk
+#define RCC_APB4RSTR_COMP12RST_Pos             (14U)
+#define RCC_APB4RSTR_COMP12RST_Msk             (0x1UL << RCC_APB4RSTR_COMP12RST_Pos) /*!< 0x00004000 */
+#define RCC_APB4RSTR_COMP12RST                 RCC_APB4RSTR_COMP12RST_Msk
+#define RCC_APB4RSTR_VREFRST_Pos               (15U)
+#define RCC_APB4RSTR_VREFRST_Msk               (0x1UL << RCC_APB4RSTR_VREFRST_Pos) /*!< 0x00008000 */
+#define RCC_APB4RSTR_VREFRST                   RCC_APB4RSTR_VREFRST_Msk
+#define RCC_APB4RSTR_SAI4RST_Pos               (21U)
+#define RCC_APB4RSTR_SAI4RST_Msk               (0x1UL << RCC_APB4RSTR_SAI4RST_Pos) /*!< 0x00200000 */
+#define RCC_APB4RSTR_SAI4RST                   RCC_APB4RSTR_SAI4RST_Msk
+
+
+/********************  Bit definition for RCC_GCR register  ********************/
+#define RCC_GCR_WW1RSC_Pos                     (0U)
+#define RCC_GCR_WW1RSC_Msk                     (0x1UL << RCC_GCR_WW1RSC_Pos)   /*!< 0x00000001 */
+#define RCC_GCR_WW1RSC                         RCC_GCR_WW1RSC_Msk
+
+/********************  Bit definition for RCC_D3AMR register  ********************/
+#define RCC_D3AMR_BDMAAMEN_Pos                 (0U)
+#define RCC_D3AMR_BDMAAMEN_Msk                 (0x1UL << RCC_D3AMR_BDMAAMEN_Pos) /*!< 0x00000001 */
+#define RCC_D3AMR_BDMAAMEN                     RCC_D3AMR_BDMAAMEN_Msk
+#define RCC_D3AMR_LPUART1AMEN_Pos              (3U)
+#define RCC_D3AMR_LPUART1AMEN_Msk              (0x1UL << RCC_D3AMR_LPUART1AMEN_Pos) /*!< 0x00000008 */
+#define RCC_D3AMR_LPUART1AMEN                  RCC_D3AMR_LPUART1AMEN_Msk
+#define RCC_D3AMR_SPI6AMEN_Pos                 (5U)
+#define RCC_D3AMR_SPI6AMEN_Msk                 (0x1UL << RCC_D3AMR_SPI6AMEN_Pos) /*!< 0x00000020 */
+#define RCC_D3AMR_SPI6AMEN                     RCC_D3AMR_SPI6AMEN_Msk
+#define RCC_D3AMR_I2C4AMEN_Pos                 (7U)
+#define RCC_D3AMR_I2C4AMEN_Msk                 (0x1UL << RCC_D3AMR_I2C4AMEN_Pos) /*!< 0x00000080 */
+#define RCC_D3AMR_I2C4AMEN                     RCC_D3AMR_I2C4AMEN_Msk
+#define RCC_D3AMR_LPTIM2AMEN_Pos               (9U)
+#define RCC_D3AMR_LPTIM2AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM2AMEN_Pos) /*!< 0x00000200 */
+#define RCC_D3AMR_LPTIM2AMEN                   RCC_D3AMR_LPTIM2AMEN_Msk
+#define RCC_D3AMR_LPTIM3AMEN_Pos               (10U)
+#define RCC_D3AMR_LPTIM3AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM3AMEN_Pos) /*!< 0x00000400 */
+#define RCC_D3AMR_LPTIM3AMEN                   RCC_D3AMR_LPTIM3AMEN_Msk
+#define RCC_D3AMR_LPTIM4AMEN_Pos               (11U)
+#define RCC_D3AMR_LPTIM4AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM4AMEN_Pos) /*!< 0x00000800 */
+#define RCC_D3AMR_LPTIM4AMEN                   RCC_D3AMR_LPTIM4AMEN_Msk
+#define RCC_D3AMR_LPTIM5AMEN_Pos               (12U)
+#define RCC_D3AMR_LPTIM5AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM5AMEN_Pos) /*!< 0x00001000 */
+#define RCC_D3AMR_LPTIM5AMEN                   RCC_D3AMR_LPTIM5AMEN_Msk
+#define RCC_D3AMR_COMP12AMEN_Pos               (14U)
+#define RCC_D3AMR_COMP12AMEN_Msk               (0x1UL << RCC_D3AMR_COMP12AMEN_Pos) /*!< 0x00004000 */
+#define RCC_D3AMR_COMP12AMEN                   RCC_D3AMR_COMP12AMEN_Msk
+#define RCC_D3AMR_VREFAMEN_Pos                 (15U)
+#define RCC_D3AMR_VREFAMEN_Msk                 (0x1UL << RCC_D3AMR_VREFAMEN_Pos) /*!< 0x00008000 */
+#define RCC_D3AMR_VREFAMEN                     RCC_D3AMR_VREFAMEN_Msk
+#define RCC_D3AMR_RTCAMEN_Pos                  (16U)
+#define RCC_D3AMR_RTCAMEN_Msk                  (0x1UL << RCC_D3AMR_RTCAMEN_Pos) /*!< 0x00010000 */
+#define RCC_D3AMR_RTCAMEN                      RCC_D3AMR_RTCAMEN_Msk
+#define RCC_D3AMR_CRCAMEN_Pos                  (19U)
+#define RCC_D3AMR_CRCAMEN_Msk                  (0x1UL << RCC_D3AMR_CRCAMEN_Pos) /*!< 0x00080000 */
+#define RCC_D3AMR_CRCAMEN                      RCC_D3AMR_CRCAMEN_Msk
+#define RCC_D3AMR_SAI4AMEN_Pos                 (21U)
+#define RCC_D3AMR_SAI4AMEN_Msk                 (0x1UL << RCC_D3AMR_SAI4AMEN_Pos) /*!< 0x00200000 */
+#define RCC_D3AMR_SAI4AMEN                     RCC_D3AMR_SAI4AMEN_Msk
+#define RCC_D3AMR_ADC3AMEN_Pos                 (24U)
+#define RCC_D3AMR_ADC3AMEN_Msk                 (0x1UL << RCC_D3AMR_ADC3AMEN_Pos) /*!< 0x01000000 */
+#define RCC_D3AMR_ADC3AMEN                     RCC_D3AMR_ADC3AMEN_Msk
+
+
+#define RCC_D3AMR_BKPRAMAMEN_Pos               (28U)
+#define RCC_D3AMR_BKPRAMAMEN_Msk               (0x1UL << RCC_D3AMR_BKPRAMAMEN_Pos) /*!< 0x10000000 */
+#define RCC_D3AMR_BKPRAMAMEN                   RCC_D3AMR_BKPRAMAMEN_Msk
+#define RCC_D3AMR_SRAM4AMEN_Pos                (29U)
+#define RCC_D3AMR_SRAM4AMEN_Msk                (0x1UL << RCC_D3AMR_SRAM4AMEN_Pos) /*!< 0x20000000 */
+#define RCC_D3AMR_SRAM4AMEN                    RCC_D3AMR_SRAM4AMEN_Msk
+/********************  Bit definition for RCC_AHB3LPENR register  **************/
+#define RCC_AHB3LPENR_MDMALPEN_Pos             (0U)
+#define RCC_AHB3LPENR_MDMALPEN_Msk             (0x1UL << RCC_AHB3LPENR_MDMALPEN_Pos)         /*!< 0x00000001 */
+#define RCC_AHB3LPENR_MDMALPEN                 RCC_AHB3LPENR_MDMALPEN_Msk
+#define RCC_AHB3LPENR_DMA2DLPEN_Pos            (4U)
+#define RCC_AHB3LPENR_DMA2DLPEN_Msk            (0x1UL << RCC_AHB3LPENR_DMA2DLPEN_Pos)        /*!< 0x00000010 */
+#define RCC_AHB3LPENR_DMA2DLPEN                RCC_AHB3LPENR_DMA2DLPEN_Msk
+#define RCC_AHB3LPENR_JPGDECLPEN_Pos           (5U)
+#define RCC_AHB3LPENR_JPGDECLPEN_Msk           (0x1UL << RCC_AHB3LPENR_JPGDECLPEN_Pos)       /*!< 0x00000020 */
+#define RCC_AHB3LPENR_JPGDECLPEN               RCC_AHB3LPENR_JPGDECLPEN_Msk
+#define RCC_AHB3LPENR_FLASHLPEN_Pos            (8U)
+#define RCC_AHB3LPENR_FLASHLPEN_Msk            (0x1UL << RCC_AHB3LPENR_FLASHLPEN_Pos)        /*!< 0x00000100 */
+#define RCC_AHB3LPENR_FLASHLPEN                RCC_AHB3LPENR_FLASHLPEN_Msk
+#define RCC_AHB3LPENR_FMCLPEN_Pos              (12U)
+#define RCC_AHB3LPENR_FMCLPEN_Msk              (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos)          /*!< 0x00001000 */
+#define RCC_AHB3LPENR_FMCLPEN                  RCC_AHB3LPENR_FMCLPEN_Msk
+#define RCC_AHB3LPENR_QSPILPEN_Pos             (14U)
+#define RCC_AHB3LPENR_QSPILPEN_Msk             (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos)         /*!< 0x00004000 */
+#define RCC_AHB3LPENR_QSPILPEN                 RCC_AHB3LPENR_QSPILPEN_Msk
+#define RCC_AHB3LPENR_SDMMC1LPEN_Pos           (16U)
+#define RCC_AHB3LPENR_SDMMC1LPEN_Msk           (0x1UL << RCC_AHB3LPENR_SDMMC1LPEN_Pos)       /*!< 0x00010000 */
+#define RCC_AHB3LPENR_SDMMC1LPEN               RCC_AHB3LPENR_SDMMC1LPEN_Msk
+#define RCC_AHB3LPENR_DTCM1LPEN_Pos            (28U)
+#define RCC_AHB3LPENR_DTCM1LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM1LPEN_Pos)        /*!< 0x10000000 */
+#define RCC_AHB3LPENR_DTCM1LPEN                RCC_AHB3LPENR_DTCM1LPEN_Msk
+#define RCC_AHB3LPENR_DTCM2LPEN_Pos            (29U)
+#define RCC_AHB3LPENR_DTCM2LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM2LPEN_Pos)        /*!< 0x20000000 */
+#define RCC_AHB3LPENR_DTCM2LPEN                RCC_AHB3LPENR_DTCM2LPEN_Msk
+#define RCC_AHB3LPENR_ITCMLPEN_Pos             (30U)
+#define RCC_AHB3LPENR_ITCMLPEN_Msk             (0x1UL << RCC_AHB3LPENR_ITCMLPEN_Pos)         /*!< 0x40000000 */
+#define RCC_AHB3LPENR_ITCMLPEN                 RCC_AHB3LPENR_ITCMLPEN_Msk
+#define RCC_AHB3LPENR_AXISRAMLPEN_Pos          (31U)
+#define RCC_AHB3LPENR_AXISRAMLPEN_Msk          (0x1UL << RCC_AHB3LPENR_AXISRAMLPEN_Pos)      /*!< 0x80000000 */
+#define RCC_AHB3LPENR_AXISRAMLPEN              RCC_AHB3LPENR_AXISRAMLPEN_Msk
+
+
+/********************  Bit definition for RCC_AHB1LPENR register  ***************/
+#define RCC_AHB1LPENR_DMA1LPEN_Pos             (0U)
+#define RCC_AHB1LPENR_DMA1LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1LPENR_DMA1LPEN                 RCC_AHB1LPENR_DMA1LPEN_Msk
+#define RCC_AHB1LPENR_DMA2LPEN_Pos             (1U)
+#define RCC_AHB1LPENR_DMA2LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1LPENR_DMA2LPEN                 RCC_AHB1LPENR_DMA2LPEN_Msk
+#define RCC_AHB1LPENR_ADC12LPEN_Pos            (5U)
+#define RCC_AHB1LPENR_ADC12LPEN_Msk            (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB1LPENR_ADC12LPEN                RCC_AHB1LPENR_ADC12LPEN_Msk
+#define RCC_AHB1LPENR_ETH1MACLPEN_Pos          (15U)
+#define RCC_AHB1LPENR_ETH1MACLPEN_Msk          (0x1UL << RCC_AHB1LPENR_ETH1MACLPEN_Pos) /*!< 0x00008000 */
+#define RCC_AHB1LPENR_ETH1MACLPEN              RCC_AHB1LPENR_ETH1MACLPEN_Msk
+#define RCC_AHB1LPENR_ETH1TXLPEN_Pos           (16U)
+#define RCC_AHB1LPENR_ETH1TXLPEN_Msk           (0x1UL << RCC_AHB1LPENR_ETH1TXLPEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB1LPENR_ETH1TXLPEN               RCC_AHB1LPENR_ETH1TXLPEN_Msk
+#define RCC_AHB1LPENR_ETH1RXLPEN_Pos           (17U)
+#define RCC_AHB1LPENR_ETH1RXLPEN_Msk           (0x1UL << RCC_AHB1LPENR_ETH1RXLPEN_Pos) /*!< 0x00020000 */
+#define RCC_AHB1LPENR_ETH1RXLPEN               RCC_AHB1LPENR_ETH1RXLPEN_Msk
+#define RCC_AHB1LPENR_USB1OTGHSLPEN_Pos        (25U)
+#define RCC_AHB1LPENR_USB1OTGHSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_USB1OTGHSLPEN_Pos) /*!< 0x02000000 */
+#define RCC_AHB1LPENR_USB1OTGHSLPEN            RCC_AHB1LPENR_USB1OTGHSLPEN_Msk
+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos    (26U)
+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos) /*!< 0x04000000 */
+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN        RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk
+#define RCC_AHB1LPENR_USB2OTGFSLPEN_Pos        (27U)
+#define RCC_AHB1LPENR_USB2OTGFSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_USB2OTGFSLPEN_Pos) /*!< 0x08000000 */
+#define RCC_AHB1LPENR_USB2OTGFSLPEN            RCC_AHB1LPENR_USB2OTGFSLPEN_Msk
+#define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos    (28U)
+#define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos) /*!< 0x10000000 */
+#define RCC_AHB1LPENR_USB2OTGFSULPILPEN        RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk
+
+/* Legacy define */
+#define RCC_AHB1LPENR_USB2OTGHSLPEN_Pos        RCC_AHB1LPENR_USB2OTGFSLPEN_Pos
+#define RCC_AHB1LPENR_USB2OTGHSLPEN_Msk        RCC_AHB1LPENR_USB2OTGFSLPEN_Msk
+#define RCC_AHB1LPENR_USB2OTGHSLPEN            RCC_AHB1LPENR_USB2OTGFSLPEN
+#define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Pos    RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos
+#define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Msk    RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk
+#define RCC_AHB1LPENR_USB2OTGHSULPILPEN        RCC_AHB1LPENR_USB2OTGFSULPILPEN
+
+/********************  Bit definition for RCC_AHB2LPENR register  ***************/
+#define RCC_AHB2LPENR_DCMILPEN_Pos             (0U)
+#define RCC_AHB2LPENR_DCMILPEN_Msk             (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB2LPENR_DCMILPEN                 RCC_AHB2LPENR_DCMILPEN_Msk
+#define RCC_AHB2LPENR_RNGLPEN_Pos              (6U)
+#define RCC_AHB2LPENR_RNGLPEN_Msk              (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB2LPENR_RNGLPEN                  RCC_AHB2LPENR_RNGLPEN_Msk
+#define RCC_AHB2LPENR_SDMMC2LPEN_Pos           (9U)
+#define RCC_AHB2LPENR_SDMMC2LPEN_Msk           (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000200 */
+#define RCC_AHB2LPENR_SDMMC2LPEN               RCC_AHB2LPENR_SDMMC2LPEN_Msk
+#define RCC_AHB2LPENR_SRAM1LPEN_Pos          (29U)
+#define RCC_AHB2LPENR_SRAM1LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM1LPEN_Pos) /*!< 0x20000000 */
+#define RCC_AHB2LPENR_SRAM1LPEN              RCC_AHB2LPENR_SRAM1LPEN_Msk
+#define RCC_AHB2LPENR_SRAM2LPEN_Pos          (30U)
+#define RCC_AHB2LPENR_SRAM2LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM2LPEN_Pos) /*!< 0x40000000 */
+#define RCC_AHB2LPENR_SRAM2LPEN              RCC_AHB2LPENR_SRAM2LPEN_Msk
+#define RCC_AHB2LPENR_SRAM3LPEN_Pos          (31U)
+#define RCC_AHB2LPENR_SRAM3LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM3LPEN_Pos) /*!< 0x80000000 */
+#define RCC_AHB2LPENR_SRAM3LPEN              RCC_AHB2LPENR_SRAM3LPEN_Msk
+
+/* Legacy define */
+#define RCC_AHB2LPENR_D2SRAM1LPEN_Pos          RCC_AHB2LPENR_SRAM1LPEN_Pos
+#define RCC_AHB2LPENR_D2SRAM1LPEN_Msk          RCC_AHB2LPENR_SRAM1LPEN_Msk
+#define RCC_AHB2LPENR_D2SRAM1LPEN              RCC_AHB2LPENR_SRAM1LPEN
+#define RCC_AHB2LPENR_D2SRAM2LPEN_Pos          RCC_AHB2LPENR_SRAM2LPEN_Pos
+#define RCC_AHB2LPENR_D2SRAM2LPEN_Msk          RCC_AHB2LPENR_SRAM2LPEN_Msk
+#define RCC_AHB2LPENR_D2SRAM2LPEN              RCC_AHB2LPENR_SRAM2LPEN
+#define RCC_AHB2LPENR_D2SRAM3LPEN_Pos          RCC_AHB2LPENR_SRAM3LPEN_Pos
+#define RCC_AHB2LPENR_D2SRAM3LPEN_Msk          RCC_AHB2LPENR_SRAM3LPEN_Msk
+#define RCC_AHB2LPENR_D2SRAM3LPEN              RCC_AHB2LPENR_SRAM3LPEN
+
+/********************  Bit definition for RCC_AHB4LPENR register  ******************/
+#define RCC_AHB4LPENR_GPIOALPEN_Pos            (0U)
+#define RCC_AHB4LPENR_GPIOALPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB4LPENR_GPIOALPEN                RCC_AHB4LPENR_GPIOALPEN_Msk
+#define RCC_AHB4LPENR_GPIOBLPEN_Pos            (1U)
+#define RCC_AHB4LPENR_GPIOBLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB4LPENR_GPIOBLPEN                RCC_AHB4LPENR_GPIOBLPEN_Msk
+#define RCC_AHB4LPENR_GPIOCLPEN_Pos            (2U)
+#define RCC_AHB4LPENR_GPIOCLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB4LPENR_GPIOCLPEN                RCC_AHB4LPENR_GPIOCLPEN_Msk
+#define RCC_AHB4LPENR_GPIODLPEN_Pos            (3U)
+#define RCC_AHB4LPENR_GPIODLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB4LPENR_GPIODLPEN                RCC_AHB4LPENR_GPIODLPEN_Msk
+#define RCC_AHB4LPENR_GPIOELPEN_Pos            (4U)
+#define RCC_AHB4LPENR_GPIOELPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB4LPENR_GPIOELPEN                RCC_AHB4LPENR_GPIOELPEN_Msk
+#define RCC_AHB4LPENR_GPIOFLPEN_Pos            (5U)
+#define RCC_AHB4LPENR_GPIOFLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB4LPENR_GPIOFLPEN                RCC_AHB4LPENR_GPIOFLPEN_Msk
+#define RCC_AHB4LPENR_GPIOGLPEN_Pos            (6U)
+#define RCC_AHB4LPENR_GPIOGLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB4LPENR_GPIOGLPEN                RCC_AHB4LPENR_GPIOGLPEN_Msk
+#define RCC_AHB4LPENR_GPIOHLPEN_Pos            (7U)
+#define RCC_AHB4LPENR_GPIOHLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB4LPENR_GPIOHLPEN                RCC_AHB4LPENR_GPIOHLPEN_Msk
+#define RCC_AHB4LPENR_GPIOILPEN_Pos            (8U)
+#define RCC_AHB4LPENR_GPIOILPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB4LPENR_GPIOILPEN                RCC_AHB4LPENR_GPIOILPEN_Msk
+#define RCC_AHB4LPENR_GPIOJLPEN_Pos            (9U)
+#define RCC_AHB4LPENR_GPIOJLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */
+#define RCC_AHB4LPENR_GPIOJLPEN                RCC_AHB4LPENR_GPIOJLPEN_Msk
+#define RCC_AHB4LPENR_GPIOKLPEN_Pos            (10U)
+#define RCC_AHB4LPENR_GPIOKLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */
+#define RCC_AHB4LPENR_GPIOKLPEN                RCC_AHB4LPENR_GPIOKLPEN_Msk
+#define RCC_AHB4LPENR_CRCLPEN_Pos              (19U)
+#define RCC_AHB4LPENR_CRCLPEN_Msk              (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos) /*!< 0x00080000 */
+#define RCC_AHB4LPENR_CRCLPEN                  RCC_AHB4LPENR_CRCLPEN_Msk
+#define RCC_AHB4LPENR_BDMALPEN_Pos             (21U)
+#define RCC_AHB4LPENR_BDMALPEN_Msk             (0x1UL << RCC_AHB4LPENR_BDMALPEN_Pos) /*!< 0x00200000 */
+#define RCC_AHB4LPENR_BDMALPEN                 RCC_AHB4LPENR_BDMALPEN_Msk
+#define RCC_AHB4LPENR_ADC3LPEN_Pos             (24U)
+#define RCC_AHB4LPENR_ADC3LPEN_Msk             (0x1UL << RCC_AHB4LPENR_ADC3LPEN_Pos) /*!< 0x01000000 */
+#define RCC_AHB4LPENR_ADC3LPEN                 RCC_AHB4LPENR_ADC3LPEN_Msk
+#define RCC_AHB4LPENR_BKPRAMLPEN_Pos           (28U)
+#define RCC_AHB4LPENR_BKPRAMLPEN_Msk           (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos) /*!< 0x10000000 */
+#define RCC_AHB4LPENR_BKPRAMLPEN               RCC_AHB4LPENR_BKPRAMLPEN_Msk
+#define RCC_AHB4LPENR_SRAM4LPEN_Pos            (29U)
+#define RCC_AHB4LPENR_SRAM4LPEN_Msk            (0x1UL << RCC_AHB4LPENR_SRAM4LPEN_Pos) /*!< 0x20000000 */
+#define RCC_AHB4LPENR_SRAM4LPEN                RCC_AHB4LPENR_SRAM4LPEN_Msk
+
+/* Legacy define */
+#define RCC_AHB4LPENR_D3SRAM1LPEN_Pos          RCC_AHB4LPENR_SRAM4LPEN_Pos
+#define RCC_AHB4LPENR_D3SRAM1LPEN_Msk          RCC_AHB4LPENR_SRAM4LPEN_Msk
+#define RCC_AHB4LPENR_D3SRAM1LPEN              RCC_AHB4LPENR_SRAM4LPEN
+/********************  Bit definition for RCC_APB3LPENR register  ******************/
+#define RCC_APB3LPENR_LTDCLPEN_Pos             (3U)
+#define RCC_APB3LPENR_LTDCLPEN_Msk             (0x1UL << RCC_APB3LPENR_LTDCLPEN_Pos) /*!< 0x00000008 */
+#define RCC_APB3LPENR_LTDCLPEN                 RCC_APB3LPENR_LTDCLPEN_Msk
+#define RCC_APB3LPENR_WWDG1LPEN_Pos            (6U)
+#define RCC_APB3LPENR_WWDG1LPEN_Msk            (0x1UL << RCC_APB3LPENR_WWDG1LPEN_Pos) /*!< 0x00000040 */
+#define RCC_APB3LPENR_WWDG1LPEN                RCC_APB3LPENR_WWDG1LPEN_Msk
+
+/********************  Bit definition for RCC_APB1LLPENR register  ******************/
+
+#define RCC_APB1LLPENR_TIM2LPEN_Pos            (0U)
+#define RCC_APB1LLPENR_TIM2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1LLPENR_TIM2LPEN                RCC_APB1LLPENR_TIM2LPEN_Msk
+#define RCC_APB1LLPENR_TIM3LPEN_Pos            (1U)
+#define RCC_APB1LLPENR_TIM3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1LLPENR_TIM3LPEN                RCC_APB1LLPENR_TIM3LPEN_Msk
+#define RCC_APB1LLPENR_TIM4LPEN_Pos            (2U)
+#define RCC_APB1LLPENR_TIM4LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1LLPENR_TIM4LPEN                RCC_APB1LLPENR_TIM4LPEN_Msk
+#define RCC_APB1LLPENR_TIM5LPEN_Pos            (3U)
+#define RCC_APB1LLPENR_TIM5LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
+#define RCC_APB1LLPENR_TIM5LPEN                RCC_APB1LLPENR_TIM5LPEN_Msk
+#define RCC_APB1LLPENR_TIM6LPEN_Pos            (4U)
+#define RCC_APB1LLPENR_TIM6LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1LLPENR_TIM6LPEN                RCC_APB1LLPENR_TIM6LPEN_Msk
+#define RCC_APB1LLPENR_TIM7LPEN_Pos            (5U)
+#define RCC_APB1LLPENR_TIM7LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1LLPENR_TIM7LPEN                RCC_APB1LLPENR_TIM7LPEN_Msk
+#define RCC_APB1LLPENR_TIM12LPEN_Pos           (6U)
+#define RCC_APB1LLPENR_TIM12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
+#define RCC_APB1LLPENR_TIM12LPEN               RCC_APB1LLPENR_TIM12LPEN_Msk
+#define RCC_APB1LLPENR_TIM13LPEN_Pos           (7U)
+#define RCC_APB1LLPENR_TIM13LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
+#define RCC_APB1LLPENR_TIM13LPEN               RCC_APB1LLPENR_TIM13LPEN_Msk
+#define RCC_APB1LLPENR_TIM14LPEN_Pos           (8U)
+#define RCC_APB1LLPENR_TIM14LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB1LLPENR_TIM14LPEN               RCC_APB1LLPENR_TIM14LPEN_Msk
+#define RCC_APB1LLPENR_LPTIM1LPEN_Pos          (9U)
+#define RCC_APB1LLPENR_LPTIM1LPEN_Msk          (0x1UL << RCC_APB1LLPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */
+#define RCC_APB1LLPENR_LPTIM1LPEN              RCC_APB1LLPENR_LPTIM1LPEN_Msk
+
+
+#define RCC_APB1LLPENR_SPI2LPEN_Pos            (14U)
+#define RCC_APB1LLPENR_SPI2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB1LLPENR_SPI2LPEN                RCC_APB1LLPENR_SPI2LPEN_Msk
+#define RCC_APB1LLPENR_SPI3LPEN_Pos            (15U)
+#define RCC_APB1LLPENR_SPI3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
+#define RCC_APB1LLPENR_SPI3LPEN                RCC_APB1LLPENR_SPI3LPEN_Msk
+#define RCC_APB1LLPENR_SPDIFRXLPEN_Pos         (16U)
+#define RCC_APB1LLPENR_SPDIFRXLPEN_Msk         (0x1UL << RCC_APB1LLPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */
+#define RCC_APB1LLPENR_SPDIFRXLPEN             RCC_APB1LLPENR_SPDIFRXLPEN_Msk
+#define RCC_APB1LLPENR_USART2LPEN_Pos          (17U)
+#define RCC_APB1LLPENR_USART2LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1LLPENR_USART2LPEN              RCC_APB1LLPENR_USART2LPEN_Msk
+#define RCC_APB1LLPENR_USART3LPEN_Pos          (18U)
+#define RCC_APB1LLPENR_USART3LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1LLPENR_USART3LPEN              RCC_APB1LLPENR_USART3LPEN_Msk
+#define RCC_APB1LLPENR_UART4LPEN_Pos           (19U)
+#define RCC_APB1LLPENR_UART4LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos) /*!< 0x00080000 */
+#define RCC_APB1LLPENR_UART4LPEN               RCC_APB1LLPENR_UART4LPEN_Msk
+#define RCC_APB1LLPENR_UART5LPEN_Pos           (20U)
+#define RCC_APB1LLPENR_UART5LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos) /*!< 0x00100000 */
+#define RCC_APB1LLPENR_UART5LPEN               RCC_APB1LLPENR_UART5LPEN_Msk
+#define RCC_APB1LLPENR_I2C1LPEN_Pos            (21U)
+#define RCC_APB1LLPENR_I2C1LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1LLPENR_I2C1LPEN                RCC_APB1LLPENR_I2C1LPEN_Msk
+#define RCC_APB1LLPENR_I2C2LPEN_Pos            (22U)
+#define RCC_APB1LLPENR_I2C2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_APB1LLPENR_I2C2LPEN                RCC_APB1LLPENR_I2C2LPEN_Msk
+#define RCC_APB1LLPENR_I2C3LPEN_Pos            (23U)
+#define RCC_APB1LLPENR_I2C3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1LLPENR_I2C3LPEN                RCC_APB1LLPENR_I2C3LPEN_Msk
+#define RCC_APB1LLPENR_CECLPEN_Pos             (27U)
+#define RCC_APB1LLPENR_CECLPEN_Msk             (0x1UL << RCC_APB1LLPENR_CECLPEN_Pos) /*!< 0x08000000 */
+#define RCC_APB1LLPENR_CECLPEN                 RCC_APB1LLPENR_CECLPEN_Msk
+#define RCC_APB1LLPENR_DAC12LPEN_Pos           (29U)
+#define RCC_APB1LLPENR_DAC12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_DAC12LPEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1LLPENR_DAC12LPEN               RCC_APB1LLPENR_DAC12LPEN_Msk
+#define RCC_APB1LLPENR_UART7LPEN_Pos           (30U)
+#define RCC_APB1LLPENR_UART7LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART7LPEN_Pos) /*!< 0x40000000 */
+#define RCC_APB1LLPENR_UART7LPEN               RCC_APB1LLPENR_UART7LPEN_Msk
+#define RCC_APB1LLPENR_UART8LPEN_Pos           (31U)
+#define RCC_APB1LLPENR_UART8LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART8LPEN_Pos) /*!< 0x80000000 */
+#define RCC_APB1LLPENR_UART8LPEN               RCC_APB1LLPENR_UART8LPEN_Msk
+
+/* Legacy define */
+#define RCC_APB1LLPENR_HDMICECEN_Pos           RCC_APB1LLPENR_CECLPEN_Pos
+#define RCC_APB1LLPENR_HDMICECEN_Msk           RCC_APB1LLPENR_CECLPEN_Msk
+#define RCC_APB1LLPENR_HDMICECEN               RCC_APB1LLPENR_CECLPEN
+/********************  Bit definition for RCC_APB1HLPENR register  ******************/
+#define RCC_APB1HLPENR_CRSLPEN_Pos             (1U)
+#define RCC_APB1HLPENR_CRSLPEN_Msk             (0x1UL << RCC_APB1HLPENR_CRSLPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1HLPENR_CRSLPEN                 RCC_APB1HLPENR_CRSLPEN_Msk
+#define RCC_APB1HLPENR_SWPMILPEN_Pos           (2U)
+#define RCC_APB1HLPENR_SWPMILPEN_Msk           (0x1UL << RCC_APB1HLPENR_SWPMILPEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1HLPENR_SWPMILPEN               RCC_APB1HLPENR_SWPMILPEN_Msk
+#define RCC_APB1HLPENR_OPAMPLPEN_Pos           (4U)
+#define RCC_APB1HLPENR_OPAMPLPEN_Msk           (0x1UL << RCC_APB1HLPENR_OPAMPLPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1HLPENR_OPAMPLPEN               RCC_APB1HLPENR_OPAMPLPEN_Msk
+#define RCC_APB1HLPENR_MDIOSLPEN_Pos           (5U)
+#define RCC_APB1HLPENR_MDIOSLPEN_Msk           (0x1UL << RCC_APB1HLPENR_MDIOSLPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1HLPENR_MDIOSLPEN               RCC_APB1HLPENR_MDIOSLPEN_Msk
+#define RCC_APB1HLPENR_FDCANLPEN_Pos           (8U)
+#define RCC_APB1HLPENR_FDCANLPEN_Msk           (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB1HLPENR_FDCANLPEN               RCC_APB1HLPENR_FDCANLPEN_Msk
+
+/********************  Bit definition for RCC_APB2LPENR register  ******************/
+#define RCC_APB2LPENR_TIM1LPEN_Pos             (0U)
+#define RCC_APB2LPENR_TIM1LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2LPENR_TIM1LPEN                 RCC_APB2LPENR_TIM1LPEN_Msk
+#define RCC_APB2LPENR_TIM8LPEN_Pos             (1U)
+#define RCC_APB2LPENR_TIM8LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB2LPENR_TIM8LPEN                 RCC_APB2LPENR_TIM8LPEN_Msk
+#define RCC_APB2LPENR_USART1LPEN_Pos           (4U)
+#define RCC_APB2LPENR_USART1LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB2LPENR_USART1LPEN               RCC_APB2LPENR_USART1LPEN_Msk
+#define RCC_APB2LPENR_USART6LPEN_Pos           (5U)
+#define RCC_APB2LPENR_USART6LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2LPENR_USART6LPEN               RCC_APB2LPENR_USART6LPEN_Msk
+#define RCC_APB2LPENR_SPI1LPEN_Pos             (12U)
+#define RCC_APB2LPENR_SPI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2LPENR_SPI1LPEN                 RCC_APB2LPENR_SPI1LPEN_Msk
+#define RCC_APB2LPENR_SPI4LPEN_Pos             (13U)
+#define RCC_APB2LPENR_SPI4LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
+#define RCC_APB2LPENR_SPI4LPEN                 RCC_APB2LPENR_SPI4LPEN_Msk
+#define RCC_APB2LPENR_TIM15LPEN_Pos            (16U)
+#define RCC_APB2LPENR_TIM15LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */
+#define RCC_APB2LPENR_TIM15LPEN                RCC_APB2LPENR_TIM15LPEN_Msk
+#define RCC_APB2LPENR_TIM16LPEN_Pos            (17U)
+#define RCC_APB2LPENR_TIM16LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB2LPENR_TIM16LPEN                RCC_APB2LPENR_TIM16LPEN_Msk
+#define RCC_APB2LPENR_TIM17LPEN_Pos            (18U)
+#define RCC_APB2LPENR_TIM17LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB2LPENR_TIM17LPEN                RCC_APB2LPENR_TIM17LPEN_Msk
+#define RCC_APB2LPENR_SPI5LPEN_Pos             (20U)
+#define RCC_APB2LPENR_SPI5LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
+#define RCC_APB2LPENR_SPI5LPEN                 RCC_APB2LPENR_SPI5LPEN_Msk
+#define RCC_APB2LPENR_SAI1LPEN_Pos             (22U)
+#define RCC_APB2LPENR_SAI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2LPENR_SAI1LPEN                 RCC_APB2LPENR_SAI1LPEN_Msk
+#define RCC_APB2LPENR_SAI2LPEN_Pos             (23U)
+#define RCC_APB2LPENR_SAI2LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */
+#define RCC_APB2LPENR_SAI2LPEN                 RCC_APB2LPENR_SAI2LPEN_Msk
+#define RCC_APB2LPENR_SAI3LPEN_Pos             (24U)
+#define RCC_APB2LPENR_SAI3LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI3LPEN_Pos) /*!< 0x01000000 */
+#define RCC_APB2LPENR_SAI3LPEN                 RCC_APB2LPENR_SAI3LPEN_Msk
+#define RCC_APB2LPENR_DFSDM1LPEN_Pos           (28U)
+#define RCC_APB2LPENR_DFSDM1LPEN_Msk           (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x10000000 */
+#define RCC_APB2LPENR_DFSDM1LPEN               RCC_APB2LPENR_DFSDM1LPEN_Msk
+#define RCC_APB2LPENR_HRTIMLPEN_Pos            (29U)
+#define RCC_APB2LPENR_HRTIMLPEN_Msk            (0x1UL << RCC_APB2LPENR_HRTIMLPEN_Pos) /*!< 0x20000000 */
+#define RCC_APB2LPENR_HRTIMLPEN                RCC_APB2LPENR_HRTIMLPEN_Msk
+
+/********************  Bit definition for RCC_APB4LPENR register  ******************/
+#define RCC_APB4LPENR_SYSCFGLPEN_Pos           (1U)
+#define RCC_APB4LPENR_SYSCFGLPEN_Msk           (0x1UL << RCC_APB4LPENR_SYSCFGLPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB4LPENR_SYSCFGLPEN               RCC_APB4LPENR_SYSCFGLPEN_Msk
+#define RCC_APB4LPENR_LPUART1LPEN_Pos          (3U)
+#define RCC_APB4LPENR_LPUART1LPEN_Msk          (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos) /*!< 0x00000008 */
+#define RCC_APB4LPENR_LPUART1LPEN              RCC_APB4LPENR_LPUART1LPEN_Msk
+#define RCC_APB4LPENR_SPI6LPEN_Pos             (5U)
+#define RCC_APB4LPENR_SPI6LPEN_Msk             (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB4LPENR_SPI6LPEN                 RCC_APB4LPENR_SPI6LPEN_Msk
+#define RCC_APB4LPENR_I2C4LPEN_Pos             (7U)
+#define RCC_APB4LPENR_I2C4LPEN_Msk             (0x1UL << RCC_APB4LPENR_I2C4LPEN_Pos) /*!< 0x00000080 */
+#define RCC_APB4LPENR_I2C4LPEN                 RCC_APB4LPENR_I2C4LPEN_Msk
+#define RCC_APB4LPENR_LPTIM2LPEN_Pos           (9U)
+#define RCC_APB4LPENR_LPTIM2LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos) /*!< 0x00000200 */
+#define RCC_APB4LPENR_LPTIM2LPEN               RCC_APB4LPENR_LPTIM2LPEN_Msk
+#define RCC_APB4LPENR_LPTIM3LPEN_Pos           (10U)
+#define RCC_APB4LPENR_LPTIM3LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos) /*!< 0x00000400 */
+#define RCC_APB4LPENR_LPTIM3LPEN               RCC_APB4LPENR_LPTIM3LPEN_Msk
+#define RCC_APB4LPENR_LPTIM4LPEN_Pos           (11U)
+#define RCC_APB4LPENR_LPTIM4LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM4LPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB4LPENR_LPTIM4LPEN               RCC_APB4LPENR_LPTIM4LPEN_Msk
+#define RCC_APB4LPENR_LPTIM5LPEN_Pos           (12U)
+#define RCC_APB4LPENR_LPTIM5LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM5LPEN_Pos) /*!< 0x00001000 */
+#define RCC_APB4LPENR_LPTIM5LPEN               RCC_APB4LPENR_LPTIM5LPEN_Msk
+#define RCC_APB4LPENR_COMP12LPEN_Pos           (14U)
+#define RCC_APB4LPENR_COMP12LPEN_Msk           (0x1UL << RCC_APB4LPENR_COMP12LPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB4LPENR_COMP12LPEN               RCC_APB4LPENR_COMP12LPEN_Msk
+#define RCC_APB4LPENR_VREFLPEN_Pos             (15U)
+#define RCC_APB4LPENR_VREFLPEN_Msk             (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos) /*!< 0x00008000 */
+#define RCC_APB4LPENR_VREFLPEN                 RCC_APB4LPENR_VREFLPEN_Msk
+#define RCC_APB4LPENR_RTCAPBLPEN_Pos           (16U)
+#define RCC_APB4LPENR_RTCAPBLPEN_Msk           (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos) /*!< 0x00010000 */
+#define RCC_APB4LPENR_RTCAPBLPEN               RCC_APB4LPENR_RTCAPBLPEN_Msk
+#define RCC_APB4LPENR_SAI4LPEN_Pos             (21U)
+#define RCC_APB4LPENR_SAI4LPEN_Msk             (0x1UL << RCC_APB4LPENR_SAI4LPEN_Pos) /*!< 0x00200000 */
+#define RCC_APB4LPENR_SAI4LPEN                 RCC_APB4LPENR_SAI4LPEN_Msk
+
+
+/********************  Bit definition for RCC_RSR register  *******************/
+#define RCC_RSR_RMVF_Pos                       (16U)
+#define RCC_RSR_RMVF_Msk                       (0x1UL << RCC_RSR_RMVF_Pos)     /*!< 0x00010000 */
+#define RCC_RSR_RMVF                           RCC_RSR_RMVF_Msk
+#define RCC_RSR_CPURSTF_Pos                    (17U)
+#define RCC_RSR_CPURSTF_Msk                    (0x1UL << RCC_RSR_CPURSTF_Pos)  /*!< 0x00020000 */
+#define RCC_RSR_CPURSTF                        RCC_RSR_CPURSTF_Msk
+#define RCC_RSR_D1RSTF_Pos                     (19U)
+#define RCC_RSR_D1RSTF_Msk                     (0x1UL << RCC_RSR_D1RSTF_Pos)   /*!< 0x00080000 */
+#define RCC_RSR_D1RSTF                         RCC_RSR_D1RSTF_Msk
+#define RCC_RSR_D2RSTF_Pos                     (20U)
+#define RCC_RSR_D2RSTF_Msk                     (0x1UL << RCC_RSR_D2RSTF_Pos)   /*!< 0x00100000 */
+#define RCC_RSR_D2RSTF                         RCC_RSR_D2RSTF_Msk
+#define RCC_RSR_BORRSTF_Pos                    (21U)
+#define RCC_RSR_BORRSTF_Msk                    (0x1UL << RCC_RSR_BORRSTF_Pos)  /*!< 0x00200000 */
+#define RCC_RSR_BORRSTF                        RCC_RSR_BORRSTF_Msk
+#define RCC_RSR_PINRSTF_Pos                    (22U)
+#define RCC_RSR_PINRSTF_Msk                    (0x1UL << RCC_RSR_PINRSTF_Pos)  /*!< 0x00400000 */
+#define RCC_RSR_PINRSTF                        RCC_RSR_PINRSTF_Msk
+#define RCC_RSR_PORRSTF_Pos                    (23U)
+#define RCC_RSR_PORRSTF_Msk                    (0x1UL << RCC_RSR_PORRSTF_Pos)  /*!< 0x00800000 */
+#define RCC_RSR_PORRSTF                        RCC_RSR_PORRSTF_Msk
+#define RCC_RSR_SFTRSTF_Pos                    (24U)
+#define RCC_RSR_SFTRSTF_Msk                    (0x1UL << RCC_RSR_SFTRSTF_Pos)  /*!< 0x01000000 */
+#define RCC_RSR_SFTRSTF                        RCC_RSR_SFTRSTF_Msk
+#define RCC_RSR_IWDG1RSTF_Pos                  (26U)
+#define RCC_RSR_IWDG1RSTF_Msk                  (0x1UL << RCC_RSR_IWDG1RSTF_Pos) /*!< 0x04000000 */
+#define RCC_RSR_IWDG1RSTF                      RCC_RSR_IWDG1RSTF_Msk
+#define RCC_RSR_WWDG1RSTF_Pos                  (28U)
+#define RCC_RSR_WWDG1RSTF_Msk                  (0x1UL << RCC_RSR_WWDG1RSTF_Pos) /*!< 0x10000000 */
+#define RCC_RSR_WWDG1RSTF                      RCC_RSR_WWDG1RSTF_Msk
+
+#define RCC_RSR_LPWRRSTF_Pos                   (30U)
+#define RCC_RSR_LPWRRSTF_Msk                   (0x1UL << RCC_RSR_LPWRRSTF_Pos) /*!< 0x40000000 */
+#define RCC_RSR_LPWRRSTF                       RCC_RSR_LPWRRSTF_Msk
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    RNG                                     */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RNG_CR register  *******************/
+#define RNG_CR_RNGEN_Pos    (2U)
+#define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                        /*!< 0x00000004 */
+#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk
+#define RNG_CR_IE_Pos       (3U)
+#define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                           /*!< 0x00000008 */
+#define RNG_CR_IE           RNG_CR_IE_Msk
+#define RNG_CR_CED_Pos      (5U)
+#define RNG_CR_CED_Msk      (0x1UL << RNG_CR_CED_Pos)                          /*!< 0x00000020 */
+#define RNG_CR_CED          RNG_CR_CED_Msk
+
+/********************  Bits definition for RNG_SR register  *******************/
+#define RNG_SR_DRDY_Pos     (0U)
+#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                         /*!< 0x00000001 */
+#define RNG_SR_DRDY         RNG_SR_DRDY_Msk
+#define RNG_SR_CECS_Pos     (1U)
+#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                         /*!< 0x00000002 */
+#define RNG_SR_CECS         RNG_SR_CECS_Msk
+#define RNG_SR_SECS_Pos     (2U)
+#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                         /*!< 0x00000004 */
+#define RNG_SR_SECS         RNG_SR_SECS_Msk
+#define RNG_SR_CEIS_Pos     (5U)
+#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                         /*!< 0x00000020 */
+#define RNG_SR_CEIS         RNG_SR_CEIS_Msk
+#define RNG_SR_SEIS_Pos     (6U)
+#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                         /*!< 0x00000040 */
+#define RNG_SR_SEIS         RNG_SR_SEIS_Msk
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RTC_TR register  *******************/
+#define RTC_TR_PM_Pos                  (22U)
+#define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                /*!< 0x00400000 */
+#define RTC_TR_PM                      RTC_TR_PM_Msk
+#define RTC_TR_HT_Pos                  (20U)
+#define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                /*!< 0x00300000 */
+#define RTC_TR_HT                      RTC_TR_HT_Msk
+#define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                 /*!< 0x00100000 */
+#define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                 /*!< 0x00200000 */
+#define RTC_TR_HU_Pos                  (16U)
+#define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                /*!< 0x000F0000 */
+#define RTC_TR_HU                      RTC_TR_HU_Msk
+#define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                 /*!< 0x00010000 */
+#define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                 /*!< 0x00020000 */
+#define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                 /*!< 0x00040000 */
+#define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                 /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos                 (12U)
+#define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)               /*!< 0x00007000 */
+#define RTC_TR_MNT                     RTC_TR_MNT_Msk
+#define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)                /*!< 0x00001000 */
+#define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)                /*!< 0x00002000 */
+#define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)                /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos                 (8U)
+#define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)               /*!< 0x00000F00 */
+#define RTC_TR_MNU                     RTC_TR_MNU_Msk
+#define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)                /*!< 0x00000100 */
+#define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)                /*!< 0x00000200 */
+#define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)                /*!< 0x00000400 */
+#define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)                /*!< 0x00000800 */
+#define RTC_TR_ST_Pos                  (4U)
+#define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                /*!< 0x00000070 */
+#define RTC_TR_ST                      RTC_TR_ST_Msk
+#define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                 /*!< 0x00000010 */
+#define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                 /*!< 0x00000020 */
+#define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                 /*!< 0x00000040 */
+#define RTC_TR_SU_Pos                  (0U)
+#define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                /*!< 0x0000000F */
+#define RTC_TR_SU                      RTC_TR_SU_Msk
+#define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                 /*!< 0x00000001 */
+#define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                 /*!< 0x00000002 */
+#define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                 /*!< 0x00000004 */
+#define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                 /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_DR register  *******************/
+#define RTC_DR_YT_Pos                  (20U)
+#define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                /*!< 0x00F00000 */
+#define RTC_DR_YT                      RTC_DR_YT_Msk
+#define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                 /*!< 0x00100000 */
+#define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                 /*!< 0x00200000 */
+#define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                 /*!< 0x00400000 */
+#define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                 /*!< 0x00800000 */
+#define RTC_DR_YU_Pos                  (16U)
+#define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                /*!< 0x000F0000 */
+#define RTC_DR_YU                      RTC_DR_YU_Msk
+#define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                 /*!< 0x00010000 */
+#define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                 /*!< 0x00020000 */
+#define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                 /*!< 0x00040000 */
+#define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                 /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos                 (13U)
+#define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)               /*!< 0x0000E000 */
+#define RTC_DR_WDU                     RTC_DR_WDU_Msk
+#define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)                /*!< 0x00002000 */
+#define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)                /*!< 0x00004000 */
+#define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)                /*!< 0x00008000 */
+#define RTC_DR_MT_Pos                  (12U)
+#define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                /*!< 0x00001000 */
+#define RTC_DR_MT                      RTC_DR_MT_Msk
+#define RTC_DR_MU_Pos                  (8U)
+#define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                /*!< 0x00000F00 */
+#define RTC_DR_MU                      RTC_DR_MU_Msk
+#define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                 /*!< 0x00000100 */
+#define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                 /*!< 0x00000200 */
+#define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                 /*!< 0x00000400 */
+#define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                 /*!< 0x00000800 */
+#define RTC_DR_DT_Pos                  (4U)
+#define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                /*!< 0x00000030 */
+#define RTC_DR_DT                      RTC_DR_DT_Msk
+#define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                 /*!< 0x00000010 */
+#define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                 /*!< 0x00000020 */
+#define RTC_DR_DU_Pos                  (0U)
+#define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                /*!< 0x0000000F */
+#define RTC_DR_DU                      RTC_DR_DU_Msk
+#define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                 /*!< 0x00000001 */
+#define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                 /*!< 0x00000002 */
+#define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                 /*!< 0x00000004 */
+#define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                 /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_CR register  *******************/
+#define RTC_CR_ITSE_Pos                (24U)
+#define RTC_CR_ITSE_Msk                (0x1UL << RTC_CR_ITSE_Pos)              /*!< 0x01000000 */
+#define RTC_CR_ITSE                    RTC_CR_ITSE_Msk
+#define RTC_CR_COE_Pos                 (23U)
+#define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)               /*!< 0x00800000 */
+#define RTC_CR_COE                     RTC_CR_COE_Msk
+#define RTC_CR_OSEL_Pos                (21U)
+#define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)              /*!< 0x00600000 */
+#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk
+#define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */
+#define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */
+#define RTC_CR_POL_Pos                 (20U)
+#define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)               /*!< 0x00100000 */
+#define RTC_CR_POL                     RTC_CR_POL_Msk
+#define RTC_CR_COSEL_Pos               (19U)
+#define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)             /*!< 0x00080000 */
+#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk
+#define RTC_CR_BKP_Pos                 (18U)
+#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)               /*!< 0x00040000 */
+#define RTC_CR_BKP                     RTC_CR_BKP_Msk
+#define RTC_CR_SUB1H_Pos               (17U)
+#define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)             /*!< 0x00020000 */
+#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk
+#define RTC_CR_ADD1H_Pos               (16U)
+#define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)             /*!< 0x00010000 */
+#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk
+#define RTC_CR_TSIE_Pos                (15U)
+#define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)              /*!< 0x00008000 */
+#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk
+#define RTC_CR_WUTIE_Pos               (14U)
+#define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)             /*!< 0x00004000 */
+#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk
+#define RTC_CR_ALRBIE_Pos              (13U)
+#define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)            /*!< 0x00002000 */
+#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk
+#define RTC_CR_ALRAIE_Pos              (12U)
+#define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)            /*!< 0x00001000 */
+#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk
+#define RTC_CR_TSE_Pos                 (11U)
+#define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)               /*!< 0x00000800 */
+#define RTC_CR_TSE                     RTC_CR_TSE_Msk
+#define RTC_CR_WUTE_Pos                (10U)
+#define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)              /*!< 0x00000400 */
+#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk
+#define RTC_CR_ALRBE_Pos               (9U)
+#define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)             /*!< 0x00000200 */
+#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk
+#define RTC_CR_ALRAE_Pos               (8U)
+#define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)             /*!< 0x00000100 */
+#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk
+#define RTC_CR_FMT_Pos                 (6U)
+#define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)               /*!< 0x00000040 */
+#define RTC_CR_FMT                     RTC_CR_FMT_Msk
+#define RTC_CR_BYPSHAD_Pos             (5U)
+#define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)           /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk
+#define RTC_CR_REFCKON_Pos             (4U)
+#define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)           /*!< 0x00000010 */
+#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk
+#define RTC_CR_TSEDGE_Pos              (3U)
+#define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)            /*!< 0x00000008 */
+#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk
+#define RTC_CR_WUCKSEL_Pos             (0U)
+#define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk
+#define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */
+
+/********************  Bits definition for RTC_ISR register  ******************/
+#define RTC_ISR_ITSF_Pos               (17U)
+#define RTC_ISR_ITSF_Msk               (0x1UL << RTC_ISR_ITSF_Pos)             /*!< 0x00020000 */
+#define RTC_ISR_ITSF                   RTC_ISR_ITSF_Msk
+#define RTC_ISR_RECALPF_Pos            (16U)
+#define RTC_ISR_RECALPF_Msk            (0x1UL << RTC_ISR_RECALPF_Pos)          /*!< 0x00010000 */
+#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk
+#define RTC_ISR_TAMP3F_Pos             (15U)
+#define RTC_ISR_TAMP3F_Msk             (0x1UL << RTC_ISR_TAMP3F_Pos)           /*!< 0x00008000 */
+#define RTC_ISR_TAMP3F                 RTC_ISR_TAMP3F_Msk
+#define RTC_ISR_TAMP2F_Pos             (14U)
+#define RTC_ISR_TAMP2F_Msk             (0x1UL << RTC_ISR_TAMP2F_Pos)           /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk
+#define RTC_ISR_TAMP1F_Pos             (13U)
+#define RTC_ISR_TAMP1F_Msk             (0x1UL << RTC_ISR_TAMP1F_Pos)           /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk
+#define RTC_ISR_TSOVF_Pos              (12U)
+#define RTC_ISR_TSOVF_Msk              (0x1UL << RTC_ISR_TSOVF_Pos)            /*!< 0x00001000 */
+#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk
+#define RTC_ISR_TSF_Pos                (11U)
+#define RTC_ISR_TSF_Msk                (0x1UL << RTC_ISR_TSF_Pos)              /*!< 0x00000800 */
+#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk
+#define RTC_ISR_WUTF_Pos               (10U)
+#define RTC_ISR_WUTF_Msk               (0x1UL << RTC_ISR_WUTF_Pos)             /*!< 0x00000400 */
+#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk
+#define RTC_ISR_ALRBF_Pos              (9U)
+#define RTC_ISR_ALRBF_Msk              (0x1UL << RTC_ISR_ALRBF_Pos)            /*!< 0x00000200 */
+#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk
+#define RTC_ISR_ALRAF_Pos              (8U)
+#define RTC_ISR_ALRAF_Msk              (0x1UL << RTC_ISR_ALRAF_Pos)            /*!< 0x00000100 */
+#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk
+#define RTC_ISR_INIT_Pos               (7U)
+#define RTC_ISR_INIT_Msk               (0x1UL << RTC_ISR_INIT_Pos)             /*!< 0x00000080 */
+#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk
+#define RTC_ISR_INITF_Pos              (6U)
+#define RTC_ISR_INITF_Msk              (0x1UL << RTC_ISR_INITF_Pos)            /*!< 0x00000040 */
+#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk
+#define RTC_ISR_RSF_Pos                (5U)
+#define RTC_ISR_RSF_Msk                (0x1UL << RTC_ISR_RSF_Pos)              /*!< 0x00000020 */
+#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk
+#define RTC_ISR_INITS_Pos              (4U)
+#define RTC_ISR_INITS_Msk              (0x1UL << RTC_ISR_INITS_Pos)            /*!< 0x00000010 */
+#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk
+#define RTC_ISR_SHPF_Pos               (3U)
+#define RTC_ISR_SHPF_Msk               (0x1UL << RTC_ISR_SHPF_Pos)             /*!< 0x00000008 */
+#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk
+#define RTC_ISR_WUTWF_Pos              (2U)
+#define RTC_ISR_WUTWF_Msk              (0x1UL << RTC_ISR_WUTWF_Pos)            /*!< 0x00000004 */
+#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk
+#define RTC_ISR_ALRBWF_Pos             (1U)
+#define RTC_ISR_ALRBWF_Msk             (0x1UL << RTC_ISR_ALRBWF_Pos)           /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk
+#define RTC_ISR_ALRAWF_Pos             (0U)
+#define RTC_ISR_ALRAWF_Msk             (0x1UL << RTC_ISR_ALRAWF_Pos)           /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk
+
+/********************  Bits definition for RTC_PRER register  *****************/
+#define RTC_PRER_PREDIV_A_Pos          (16U)
+#define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)       /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk
+#define RTC_PRER_PREDIV_S_Pos          (0U)
+#define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)     /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk
+
+/********************  Bits definition for RTC_WUTR register  *****************/
+#define RTC_WUTR_WUT_Pos               (0U)
+#define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)          /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk
+
+/********************  Bits definition for RTC_ALRMAR register  ***************/
+#define RTC_ALRMAR_MSK4_Pos            (31U)
+#define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)          /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk
+#define RTC_ALRMAR_WDSEL_Pos           (30U)
+#define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)         /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk
+#define RTC_ALRMAR_DT_Pos              (28U)
+#define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)            /*!< 0x30000000 */
+#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk
+#define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos              (24U)
+#define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)            /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk
+#define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos            (23U)
+#define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)          /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk
+#define RTC_ALRMAR_PM_Pos              (22U)
+#define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)            /*!< 0x00400000 */
+#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk
+#define RTC_ALRMAR_HT_Pos              (20U)
+#define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00300000 */
+#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk
+#define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos              (16U)
+#define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)            /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk
+#define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos            (15U)
+#define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)          /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk
+#define RTC_ALRMAR_MNT_Pos             (12U)
+#define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk
+#define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos             (8U)
+#define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk
+#define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos            (7U)
+#define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)          /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk
+#define RTC_ALRMAR_ST_Pos              (4U)
+#define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000070 */
+#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk
+#define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos              (0U)
+#define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)            /*!< 0x0000000F */
+#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk
+#define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_ALRMBR register  ***************/
+#define RTC_ALRMBR_MSK4_Pos            (31U)
+#define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)          /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk
+#define RTC_ALRMBR_WDSEL_Pos           (30U)
+#define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)         /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk
+#define RTC_ALRMBR_DT_Pos              (28U)
+#define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)            /*!< 0x30000000 */
+#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk
+#define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos              (24U)
+#define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)            /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk
+#define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos            (23U)
+#define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)          /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk
+#define RTC_ALRMBR_PM_Pos              (22U)
+#define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)            /*!< 0x00400000 */
+#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk
+#define RTC_ALRMBR_HT_Pos              (20U)
+#define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00300000 */
+#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk
+#define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos              (16U)
+#define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)            /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk
+#define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos            (15U)
+#define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)          /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk
+#define RTC_ALRMBR_MNT_Pos             (12U)
+#define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk
+#define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos             (8U)
+#define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk
+#define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos            (7U)
+#define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)          /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk
+#define RTC_ALRMBR_ST_Pos              (4U)
+#define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000070 */
+#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk
+#define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos              (0U)
+#define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)            /*!< 0x0000000F */
+#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk
+#define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_WPR register  ******************/
+#define RTC_WPR_KEY_Pos                (0U)
+#define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)             /*!< 0x000000FF */
+#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk
+
+/********************  Bits definition for RTC_SSR register  ******************/
+#define RTC_SSR_SS_Pos                 (0U)
+#define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)            /*!< 0x0000FFFF */
+#define RTC_SSR_SS                     RTC_SSR_SS_Msk
+
+/********************  Bits definition for RTC_SHIFTR register  ***************/
+#define RTC_SHIFTR_SUBFS_Pos           (0U)
+#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)      /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk
+#define RTC_SHIFTR_ADD1S_Pos           (31U)
+#define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)         /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk
+
+/********************  Bits definition for RTC_TSTR register  *****************/
+#define RTC_TSTR_PM_Pos                (22U)
+#define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)              /*!< 0x00400000 */
+#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk
+#define RTC_TSTR_HT_Pos                (20U)
+#define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)              /*!< 0x00300000 */
+#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk
+#define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */
+#define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos                (16U)
+#define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)              /*!< 0x000F0000 */
+#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk
+#define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */
+#define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */
+#define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */
+#define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos               (12U)
+#define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)             /*!< 0x00007000 */
+#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk
+#define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos               (8U)
+#define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)             /*!< 0x00000F00 */
+#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk
+#define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos                (4U)
+#define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)              /*!< 0x00000070 */
+#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk
+#define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */
+#define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */
+#define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos                (0U)
+#define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)              /*!< 0x0000000F */
+#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk
+#define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */
+#define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */
+#define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */
+#define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_TSDR register  *****************/
+#define RTC_TSDR_WDU_Pos               (13U)
+#define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)             /*!< 0x0000E000 */
+#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk
+#define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos                (12U)
+#define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)              /*!< 0x00001000 */
+#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk
+#define RTC_TSDR_MU_Pos                (8U)
+#define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)              /*!< 0x00000F00 */
+#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk
+#define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */
+#define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */
+#define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */
+#define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos                (4U)
+#define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)              /*!< 0x00000030 */
+#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk
+#define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */
+#define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos                (0U)
+#define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)              /*!< 0x0000000F */
+#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk
+#define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */
+#define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */
+#define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */
+#define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_TSSSR register  ****************/
+#define RTC_TSSSR_SS_Pos               (0U)
+#define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)          /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk
+
+/********************  Bits definition for RTC_CALR register  *****************/
+#define RTC_CALR_CALP_Pos              (15U)
+#define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)            /*!< 0x00008000 */
+#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk
+#define RTC_CALR_CALW8_Pos             (14U)
+#define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)           /*!< 0x00004000 */
+#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk
+#define RTC_CALR_CALW16_Pos            (13U)
+#define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)          /*!< 0x00002000 */
+#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk
+#define RTC_CALR_CALM_Pos              (0U)
+#define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)          /*!< 0x000001FF */
+#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk
+#define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */
+#define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */
+#define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */
+#define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */
+#define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */
+#define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */
+#define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */
+#define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */
+#define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */
+
+/********************  Bits definition for RTC_TAMPCR register  ***************/
+#define RTC_TAMPCR_TAMP3MF_Pos         (24U)
+#define RTC_TAMPCR_TAMP3MF_Msk         (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)       /*!< 0x01000000 */
+#define RTC_TAMPCR_TAMP3MF             RTC_TAMPCR_TAMP3MF_Msk
+#define RTC_TAMPCR_TAMP3NOERASE_Pos    (23U)
+#define RTC_TAMPCR_TAMP3NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)  /*!< 0x00800000 */
+#define RTC_TAMPCR_TAMP3NOERASE        RTC_TAMPCR_TAMP3NOERASE_Msk
+#define RTC_TAMPCR_TAMP3IE_Pos         (22U)
+#define RTC_TAMPCR_TAMP3IE_Msk         (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)       /*!< 0x00400000 */
+#define RTC_TAMPCR_TAMP3IE             RTC_TAMPCR_TAMP3IE_Msk
+#define RTC_TAMPCR_TAMP2MF_Pos         (21U)
+#define RTC_TAMPCR_TAMP2MF_Msk         (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)       /*!< 0x00200000 */
+#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk
+#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)
+#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)  /*!< 0x00100000 */
+#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk
+#define RTC_TAMPCR_TAMP2IE_Pos         (19U)
+#define RTC_TAMPCR_TAMP2IE_Msk         (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)       /*!< 0x00080000 */
+#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk
+#define RTC_TAMPCR_TAMP1MF_Pos         (18U)
+#define RTC_TAMPCR_TAMP1MF_Msk         (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)       /*!< 0x00040000 */
+#define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk
+#define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)
+#define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)  /*!< 0x00020000 */
+#define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk
+#define RTC_TAMPCR_TAMP1IE_Pos         (16U)
+#define RTC_TAMPCR_TAMP1IE_Msk         (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)       /*!< 0x00010000 */
+#define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk
+#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)
+#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)     /*!< 0x00008000 */
+#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk
+#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)
+#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)      /*!< 0x00006000 */
+#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk
+#define RTC_TAMPCR_TAMPPRCH_0          (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */
+#define RTC_TAMPCR_TAMPPRCH_1          (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */
+#define RTC_TAMPCR_TAMPFLT_Pos         (11U)
+#define RTC_TAMPCR_TAMPFLT_Msk         (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)       /*!< 0x00001800 */
+#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk
+#define RTC_TAMPCR_TAMPFLT_0           (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */
+#define RTC_TAMPCR_TAMPFLT_1           (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */
+#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)
+#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)      /*!< 0x00000700 */
+#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk
+#define RTC_TAMPCR_TAMPFREQ_0          (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */
+#define RTC_TAMPCR_TAMPFREQ_1          (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */
+#define RTC_TAMPCR_TAMPFREQ_2          (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */
+#define RTC_TAMPCR_TAMPTS_Pos          (7U)
+#define RTC_TAMPCR_TAMPTS_Msk          (0x1UL << RTC_TAMPCR_TAMPTS_Pos)        /*!< 0x00000080 */
+#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk
+#define RTC_TAMPCR_TAMP3TRG_Pos        (6U)
+#define RTC_TAMPCR_TAMP3TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)      /*!< 0x00000040 */
+#define RTC_TAMPCR_TAMP3TRG            RTC_TAMPCR_TAMP3TRG_Msk
+#define RTC_TAMPCR_TAMP3E_Pos          (5U)
+#define RTC_TAMPCR_TAMP3E_Msk          (0x1UL << RTC_TAMPCR_TAMP3E_Pos)        /*!< 0x00000020 */
+#define RTC_TAMPCR_TAMP3E              RTC_TAMPCR_TAMP3E_Msk
+#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)
+#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)      /*!< 0x00000010 */
+#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk
+#define RTC_TAMPCR_TAMP2E_Pos          (3U)
+#define RTC_TAMPCR_TAMP2E_Msk          (0x1UL << RTC_TAMPCR_TAMP2E_Pos)        /*!< 0x00000008 */
+#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk
+#define RTC_TAMPCR_TAMPIE_Pos          (2U)
+#define RTC_TAMPCR_TAMPIE_Msk          (0x1UL << RTC_TAMPCR_TAMPIE_Pos)        /*!< 0x00000004 */
+#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk
+#define RTC_TAMPCR_TAMP1TRG_Pos        (1U)
+#define RTC_TAMPCR_TAMP1TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)      /*!< 0x00000002 */
+#define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk
+#define RTC_TAMPCR_TAMP1E_Pos          (0U)
+#define RTC_TAMPCR_TAMP1E_Msk          (0x1UL << RTC_TAMPCR_TAMP1E_Pos)        /*!< 0x00000001 */
+#define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk
+
+/********************  Bits definition for RTC_ALRMASSR register  *************/
+#define RTC_ALRMASSR_MASKSS_Pos        (24U)
+#define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos            (0U)
+#define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)       /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk
+
+/********************  Bits definition for RTC_ALRMBSSR register  *************/
+#define RTC_ALRMBSSR_MASKSS_Pos        (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos            (0U)
+#define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)       /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk
+
+/********************  Bits definition for RTC_OR register  *******************/
+#define RTC_OR_OUT_RMP_Pos             (1U)
+#define RTC_OR_OUT_RMP_Msk             (0x1UL << RTC_OR_OUT_RMP_Pos)           /*!< 0x00000002 */
+#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk
+#define RTC_OR_ALARMOUTTYPE_Pos        (0U)
+#define RTC_OR_ALARMOUTTYPE_Msk        (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)      /*!< 0x00000001 */
+#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk
+
+/********************  Bits definition for RTC_BKP0R register  ****************/
+#define RTC_BKP0R_Pos                  (0U)
+#define RTC_BKP0R_Msk                  (0xFFFFFFFFUL << RTC_BKP0R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP0R                      RTC_BKP0R_Msk
+
+/********************  Bits definition for RTC_BKP1R register  ****************/
+#define RTC_BKP1R_Pos                  (0U)
+#define RTC_BKP1R_Msk                  (0xFFFFFFFFUL << RTC_BKP1R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP1R                      RTC_BKP1R_Msk
+
+/********************  Bits definition for RTC_BKP2R register  ****************/
+#define RTC_BKP2R_Pos                  (0U)
+#define RTC_BKP2R_Msk                  (0xFFFFFFFFUL << RTC_BKP2R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP2R                      RTC_BKP2R_Msk
+
+/********************  Bits definition for RTC_BKP3R register  ****************/
+#define RTC_BKP3R_Pos                  (0U)
+#define RTC_BKP3R_Msk                  (0xFFFFFFFFUL << RTC_BKP3R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP3R                      RTC_BKP3R_Msk
+
+/********************  Bits definition for RTC_BKP4R register  ****************/
+#define RTC_BKP4R_Pos                  (0U)
+#define RTC_BKP4R_Msk                  (0xFFFFFFFFUL << RTC_BKP4R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP4R                      RTC_BKP4R_Msk
+
+/********************  Bits definition for RTC_BKP5R register  ****************/
+#define RTC_BKP5R_Pos                  (0U)
+#define RTC_BKP5R_Msk                  (0xFFFFFFFFUL << RTC_BKP5R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP5R                      RTC_BKP5R_Msk
+
+/********************  Bits definition for RTC_BKP6R register  ****************/
+#define RTC_BKP6R_Pos                  (0U)
+#define RTC_BKP6R_Msk                  (0xFFFFFFFFUL << RTC_BKP6R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP6R                      RTC_BKP6R_Msk
+
+/********************  Bits definition for RTC_BKP7R register  ****************/
+#define RTC_BKP7R_Pos                  (0U)
+#define RTC_BKP7R_Msk                  (0xFFFFFFFFUL << RTC_BKP7R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP7R                      RTC_BKP7R_Msk
+
+/********************  Bits definition for RTC_BKP8R register  ****************/
+#define RTC_BKP8R_Pos                  (0U)
+#define RTC_BKP8R_Msk                  (0xFFFFFFFFUL << RTC_BKP8R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP8R                      RTC_BKP8R_Msk
+
+/********************  Bits definition for RTC_BKP9R register  ****************/
+#define RTC_BKP9R_Pos                  (0U)
+#define RTC_BKP9R_Msk                  (0xFFFFFFFFUL << RTC_BKP9R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP9R                      RTC_BKP9R_Msk
+
+/********************  Bits definition for RTC_BKP10R register  ***************/
+#define RTC_BKP10R_Pos                 (0U)
+#define RTC_BKP10R_Msk                 (0xFFFFFFFFUL << RTC_BKP10R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP10R                     RTC_BKP10R_Msk
+
+/********************  Bits definition for RTC_BKP11R register  ***************/
+#define RTC_BKP11R_Pos                 (0U)
+#define RTC_BKP11R_Msk                 (0xFFFFFFFFUL << RTC_BKP11R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP11R                     RTC_BKP11R_Msk
+
+/********************  Bits definition for RTC_BKP12R register  ***************/
+#define RTC_BKP12R_Pos                 (0U)
+#define RTC_BKP12R_Msk                 (0xFFFFFFFFUL << RTC_BKP12R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP12R                     RTC_BKP12R_Msk
+
+/********************  Bits definition for RTC_BKP13R register  ***************/
+#define RTC_BKP13R_Pos                 (0U)
+#define RTC_BKP13R_Msk                 (0xFFFFFFFFUL << RTC_BKP13R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP13R                     RTC_BKP13R_Msk
+
+/********************  Bits definition for RTC_BKP14R register  ***************/
+#define RTC_BKP14R_Pos                 (0U)
+#define RTC_BKP14R_Msk                 (0xFFFFFFFFUL << RTC_BKP14R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP14R                     RTC_BKP14R_Msk
+
+/********************  Bits definition for RTC_BKP15R register  ***************/
+#define RTC_BKP15R_Pos                 (0U)
+#define RTC_BKP15R_Msk                 (0xFFFFFFFFUL << RTC_BKP15R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP15R                     RTC_BKP15R_Msk
+
+/********************  Bits definition for RTC_BKP16R register  ***************/
+#define RTC_BKP16R_Pos                 (0U)
+#define RTC_BKP16R_Msk                 (0xFFFFFFFFUL << RTC_BKP16R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP16R                     RTC_BKP16R_Msk
+
+/********************  Bits definition for RTC_BKP17R register  ***************/
+#define RTC_BKP17R_Pos                 (0U)
+#define RTC_BKP17R_Msk                 (0xFFFFFFFFUL << RTC_BKP17R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP17R                     RTC_BKP17R_Msk
+
+/********************  Bits definition for RTC_BKP18R register  ***************/
+#define RTC_BKP18R_Pos                 (0U)
+#define RTC_BKP18R_Msk                 (0xFFFFFFFFUL << RTC_BKP18R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP18R                     RTC_BKP18R_Msk
+
+/********************  Bits definition for RTC_BKP19R register  ***************/
+#define RTC_BKP19R_Pos                 (0U)
+#define RTC_BKP19R_Msk                 (0xFFFFFFFFUL << RTC_BKP19R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP19R                     RTC_BKP19R_Msk
+
+/********************  Bits definition for RTC_BKP20R register  ***************/
+#define RTC_BKP20R_Pos                 (0U)
+#define RTC_BKP20R_Msk                 (0xFFFFFFFFUL << RTC_BKP20R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP20R                     RTC_BKP20R_Msk
+
+/********************  Bits definition for RTC_BKP21R register  ***************/
+#define RTC_BKP21R_Pos                 (0U)
+#define RTC_BKP21R_Msk                 (0xFFFFFFFFUL << RTC_BKP21R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP21R                     RTC_BKP21R_Msk
+
+/********************  Bits definition for RTC_BKP22R register  ***************/
+#define RTC_BKP22R_Pos                 (0U)
+#define RTC_BKP22R_Msk                 (0xFFFFFFFFUL << RTC_BKP22R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP22R                     RTC_BKP22R_Msk
+
+/********************  Bits definition for RTC_BKP23R register  ***************/
+#define RTC_BKP23R_Pos                 (0U)
+#define RTC_BKP23R_Msk                 (0xFFFFFFFFUL << RTC_BKP23R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP23R                     RTC_BKP23R_Msk
+
+/********************  Bits definition for RTC_BKP24R register  ***************/
+#define RTC_BKP24R_Pos                 (0U)
+#define RTC_BKP24R_Msk                 (0xFFFFFFFFUL << RTC_BKP24R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP24R                     RTC_BKP24R_Msk
+
+/********************  Bits definition for RTC_BKP25R register  ***************/
+#define RTC_BKP25R_Pos                 (0U)
+#define RTC_BKP25R_Msk                 (0xFFFFFFFFUL << RTC_BKP25R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP25R                     RTC_BKP25R_Msk
+
+/********************  Bits definition for RTC_BKP26R register  ***************/
+#define RTC_BKP26R_Pos                 (0U)
+#define RTC_BKP26R_Msk                 (0xFFFFFFFFUL << RTC_BKP26R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP26R                     RTC_BKP26R_Msk
+
+/********************  Bits definition for RTC_BKP27R register  ***************/
+#define RTC_BKP27R_Pos                 (0U)
+#define RTC_BKP27R_Msk                 (0xFFFFFFFFUL << RTC_BKP27R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP27R                     RTC_BKP27R_Msk
+
+/********************  Bits definition for RTC_BKP28R register  ***************/
+#define RTC_BKP28R_Pos                 (0U)
+#define RTC_BKP28R_Msk                 (0xFFFFFFFFUL << RTC_BKP28R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP28R                     RTC_BKP28R_Msk
+
+/********************  Bits definition for RTC_BKP29R register  ***************/
+#define RTC_BKP29R_Pos                 (0U)
+#define RTC_BKP29R_Msk                 (0xFFFFFFFFUL << RTC_BKP29R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP29R                     RTC_BKP29R_Msk
+
+/********************  Bits definition for RTC_BKP30R register  ***************/
+#define RTC_BKP30R_Pos                 (0U)
+#define RTC_BKP30R_Msk                 (0xFFFFFFFFUL << RTC_BKP30R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP30R                     RTC_BKP30R_Msk
+
+/********************  Bits definition for RTC_BKP31R register  ***************/
+#define RTC_BKP31R_Pos                 (0U)
+#define RTC_BKP31R_Msk                 (0xFFFFFFFFUL << RTC_BKP31R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP31R                     RTC_BKP31R_Msk
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER_Pos             (5U)
+#define RTC_BKP_NUMBER_Msk             (0x1UL << RTC_BKP_NUMBER_Pos)           /*!< 0x00000020 */
+#define RTC_BKP_NUMBER                 RTC_BKP_NUMBER_Msk
+
+/******************************************************************************/
+/*                                                                            */
+/*                              SPDIF-RX Interface                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for SPDIF_CR register  ******************/
+#define SPDIFRX_CR_SPDIFEN_Pos      (0U)
+#define SPDIFRX_CR_SPDIFEN_Msk      (0x3UL << SPDIFRX_CR_SPDIFEN_Pos)          /*!< 0x00000003 */
+#define SPDIFRX_CR_SPDIFEN          SPDIFRX_CR_SPDIFEN_Msk                     /*!<Peripheral Block Enable                      */
+#define SPDIFRX_CR_RXDMAEN_Pos      (2U)
+#define SPDIFRX_CR_RXDMAEN_Msk      (0x1UL << SPDIFRX_CR_RXDMAEN_Pos)          /*!< 0x00000004 */
+#define SPDIFRX_CR_RXDMAEN          SPDIFRX_CR_RXDMAEN_Msk                     /*!<Receiver DMA Enable for data flow            */
+#define SPDIFRX_CR_RXSTEO_Pos       (3U)
+#define SPDIFRX_CR_RXSTEO_Msk       (0x1UL << SPDIFRX_CR_RXSTEO_Pos)           /*!< 0x00000008 */
+#define SPDIFRX_CR_RXSTEO           SPDIFRX_CR_RXSTEO_Msk                      /*!<Stereo Mode                                  */
+#define SPDIFRX_CR_DRFMT_Pos        (4U)
+#define SPDIFRX_CR_DRFMT_Msk        (0x3UL << SPDIFRX_CR_DRFMT_Pos)            /*!< 0x00000030 */
+#define SPDIFRX_CR_DRFMT            SPDIFRX_CR_DRFMT_Msk                       /*!<RX Data format                               */
+#define SPDIFRX_CR_PMSK_Pos         (6U)
+#define SPDIFRX_CR_PMSK_Msk         (0x1UL << SPDIFRX_CR_PMSK_Pos)             /*!< 0x00000040 */
+#define SPDIFRX_CR_PMSK             SPDIFRX_CR_PMSK_Msk                        /*!<Mask Parity error bit                        */
+#define SPDIFRX_CR_VMSK_Pos         (7U)
+#define SPDIFRX_CR_VMSK_Msk         (0x1UL << SPDIFRX_CR_VMSK_Pos)             /*!< 0x00000080 */
+#define SPDIFRX_CR_VMSK             SPDIFRX_CR_VMSK_Msk                        /*!<Mask of Validity bit                         */
+#define SPDIFRX_CR_CUMSK_Pos        (8U)
+#define SPDIFRX_CR_CUMSK_Msk        (0x1UL << SPDIFRX_CR_CUMSK_Pos)            /*!< 0x00000100 */
+#define SPDIFRX_CR_CUMSK            SPDIFRX_CR_CUMSK_Msk                       /*!<Mask of channel status and user bits         */
+#define SPDIFRX_CR_PTMSK_Pos        (9U)
+#define SPDIFRX_CR_PTMSK_Msk        (0x1UL << SPDIFRX_CR_PTMSK_Pos)            /*!< 0x00000200 */
+#define SPDIFRX_CR_PTMSK            SPDIFRX_CR_PTMSK_Msk                       /*!<Mask of Preamble Type bits                   */
+#define SPDIFRX_CR_CBDMAEN_Pos      (10U)
+#define SPDIFRX_CR_CBDMAEN_Msk      (0x1UL << SPDIFRX_CR_CBDMAEN_Pos)          /*!< 0x00000400 */
+#define SPDIFRX_CR_CBDMAEN          SPDIFRX_CR_CBDMAEN_Msk                     /*!<Control Buffer DMA ENable for control flow   */
+#define SPDIFRX_CR_CHSEL_Pos        (11U)
+#define SPDIFRX_CR_CHSEL_Msk        (0x1UL << SPDIFRX_CR_CHSEL_Pos)            /*!< 0x00000800 */
+#define SPDIFRX_CR_CHSEL            SPDIFRX_CR_CHSEL_Msk                       /*!<Channel Selection                            */
+#define SPDIFRX_CR_NBTR_Pos         (12U)
+#define SPDIFRX_CR_NBTR_Msk         (0x3UL << SPDIFRX_CR_NBTR_Pos)             /*!< 0x00003000 */
+#define SPDIFRX_CR_NBTR             SPDIFRX_CR_NBTR_Msk                        /*!<Maximum allowed re-tries during synchronization phase */
+#define SPDIFRX_CR_WFA_Pos          (14U)
+#define SPDIFRX_CR_WFA_Msk          (0x1UL << SPDIFRX_CR_WFA_Pos)              /*!< 0x00004000 */
+#define SPDIFRX_CR_WFA              SPDIFRX_CR_WFA_Msk                         /*!<Wait For Activity     */
+#define SPDIFRX_CR_INSEL_Pos        (16U)
+#define SPDIFRX_CR_INSEL_Msk        (0x7UL << SPDIFRX_CR_INSEL_Pos)            /*!< 0x00070000 */
+#define SPDIFRX_CR_INSEL            SPDIFRX_CR_INSEL_Msk                       /*!<SPDIF input selection */
+#define SPDIFRX_CR_CKSEN_Pos        (20U)
+#define SPDIFRX_CR_CKSEN_Msk        (0x1UL << SPDIFRX_CR_CKSEN_Pos)            /*!< 0x00100000 */
+#define SPDIFRX_CR_CKSEN            SPDIFRX_CR_CKSEN_Msk                       /*!<Symbol Clock Enable */
+#define SPDIFRX_CR_CKSBKPEN_Pos     (21U)
+#define SPDIFRX_CR_CKSBKPEN_Msk     (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos)         /*!< 0x00200000 */
+#define SPDIFRX_CR_CKSBKPEN         SPDIFRX_CR_CKSBKPEN_Msk                    /*!<Backup Symbol Clock Enable */
+
+/*******************  Bit definition for SPDIFRX_IMR register  *******************/
+#define SPDIFRX_IMR_RXNEIE_Pos      (0U)
+#define SPDIFRX_IMR_RXNEIE_Msk      (0x1UL << SPDIFRX_IMR_RXNEIE_Pos)          /*!< 0x00000001 */
+#define SPDIFRX_IMR_RXNEIE          SPDIFRX_IMR_RXNEIE_Msk                     /*!<RXNE interrupt enable                              */
+#define SPDIFRX_IMR_CSRNEIE_Pos     (1U)
+#define SPDIFRX_IMR_CSRNEIE_Msk     (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos)         /*!< 0x00000002 */
+#define SPDIFRX_IMR_CSRNEIE         SPDIFRX_IMR_CSRNEIE_Msk                    /*!<Control Buffer Ready Interrupt Enable              */
+#define SPDIFRX_IMR_PERRIE_Pos      (2U)
+#define SPDIFRX_IMR_PERRIE_Msk      (0x1UL << SPDIFRX_IMR_PERRIE_Pos)          /*!< 0x00000004 */
+#define SPDIFRX_IMR_PERRIE          SPDIFRX_IMR_PERRIE_Msk                     /*!<Parity error interrupt enable                      */
+#define SPDIFRX_IMR_OVRIE_Pos       (3U)
+#define SPDIFRX_IMR_OVRIE_Msk       (0x1UL << SPDIFRX_IMR_OVRIE_Pos)           /*!< 0x00000008 */
+#define SPDIFRX_IMR_OVRIE           SPDIFRX_IMR_OVRIE_Msk                      /*!<Overrun error Interrupt Enable                     */
+#define SPDIFRX_IMR_SBLKIE_Pos      (4U)
+#define SPDIFRX_IMR_SBLKIE_Msk      (0x1UL << SPDIFRX_IMR_SBLKIE_Pos)          /*!< 0x00000010 */
+#define SPDIFRX_IMR_SBLKIE          SPDIFRX_IMR_SBLKIE_Msk                     /*!<Synchronization Block Detected Interrupt Enable    */
+#define SPDIFRX_IMR_SYNCDIE_Pos     (5U)
+#define SPDIFRX_IMR_SYNCDIE_Msk     (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos)         /*!< 0x00000020 */
+#define SPDIFRX_IMR_SYNCDIE         SPDIFRX_IMR_SYNCDIE_Msk                    /*!<Synchronization Done                               */
+#define SPDIFRX_IMR_IFEIE_Pos       (6U)
+#define SPDIFRX_IMR_IFEIE_Msk       (0x1UL << SPDIFRX_IMR_IFEIE_Pos)           /*!< 0x00000040 */
+#define SPDIFRX_IMR_IFEIE           SPDIFRX_IMR_IFEIE_Msk                      /*!<Serial Interface Error Interrupt Enable            */
+
+/*******************  Bit definition for SPDIFRX_SR register  *******************/
+#define SPDIFRX_SR_RXNE_Pos         (0U)
+#define SPDIFRX_SR_RXNE_Msk         (0x1UL << SPDIFRX_SR_RXNE_Pos)             /*!< 0x00000001 */
+#define SPDIFRX_SR_RXNE             SPDIFRX_SR_RXNE_Msk                        /*!<Read data register not empty                          */
+#define SPDIFRX_SR_CSRNE_Pos        (1U)
+#define SPDIFRX_SR_CSRNE_Msk        (0x1UL << SPDIFRX_SR_CSRNE_Pos)            /*!< 0x00000002 */
+#define SPDIFRX_SR_CSRNE            SPDIFRX_SR_CSRNE_Msk                       /*!<The Control Buffer register is not empty              */
+#define SPDIFRX_SR_PERR_Pos         (2U)
+#define SPDIFRX_SR_PERR_Msk         (0x1UL << SPDIFRX_SR_PERR_Pos)             /*!< 0x00000004 */
+#define SPDIFRX_SR_PERR             SPDIFRX_SR_PERR_Msk                        /*!<Parity error                                          */
+#define SPDIFRX_SR_OVR_Pos          (3U)
+#define SPDIFRX_SR_OVR_Msk          (0x1UL << SPDIFRX_SR_OVR_Pos)              /*!< 0x00000008 */
+#define SPDIFRX_SR_OVR              SPDIFRX_SR_OVR_Msk                         /*!<Overrun error                                         */
+#define SPDIFRX_SR_SBD_Pos          (4U)
+#define SPDIFRX_SR_SBD_Msk          (0x1UL << SPDIFRX_SR_SBD_Pos)              /*!< 0x00000010 */
+#define SPDIFRX_SR_SBD              SPDIFRX_SR_SBD_Msk                         /*!<Synchronization Block Detected                        */
+#define SPDIFRX_SR_SYNCD_Pos        (5U)
+#define SPDIFRX_SR_SYNCD_Msk        (0x1UL << SPDIFRX_SR_SYNCD_Pos)            /*!< 0x00000020 */
+#define SPDIFRX_SR_SYNCD            SPDIFRX_SR_SYNCD_Msk                       /*!<Synchronization Done                                  */
+#define SPDIFRX_SR_FERR_Pos         (6U)
+#define SPDIFRX_SR_FERR_Msk         (0x1UL << SPDIFRX_SR_FERR_Pos)             /*!< 0x00000040 */
+#define SPDIFRX_SR_FERR             SPDIFRX_SR_FERR_Msk                        /*!<Framing error                                         */
+#define SPDIFRX_SR_SERR_Pos         (7U)
+#define SPDIFRX_SR_SERR_Msk         (0x1UL << SPDIFRX_SR_SERR_Pos)             /*!< 0x00000080 */
+#define SPDIFRX_SR_SERR             SPDIFRX_SR_SERR_Msk                        /*!<Synchronization error                                 */
+#define SPDIFRX_SR_TERR_Pos         (8U)
+#define SPDIFRX_SR_TERR_Msk         (0x1UL << SPDIFRX_SR_TERR_Pos)             /*!< 0x00000100 */
+#define SPDIFRX_SR_TERR             SPDIFRX_SR_TERR_Msk                        /*!<Time-out error                                        */
+#define SPDIFRX_SR_WIDTH5_Pos       (16U)
+#define SPDIFRX_SR_WIDTH5_Msk       (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos)        /*!< 0x7FFF0000 */
+#define SPDIFRX_SR_WIDTH5           SPDIFRX_SR_WIDTH5_Msk                      /*!<Duration of 5 symbols counted with spdif_clk          */
+
+/*******************  Bit definition for SPDIFRX_IFCR register  *******************/
+#define SPDIFRX_IFCR_PERRCF_Pos     (2U)
+#define SPDIFRX_IFCR_PERRCF_Msk     (0x1UL << SPDIFRX_IFCR_PERRCF_Pos)         /*!< 0x00000004 */
+#define SPDIFRX_IFCR_PERRCF         SPDIFRX_IFCR_PERRCF_Msk                    /*!<Clears the Parity error flag                         */
+#define SPDIFRX_IFCR_OVRCF_Pos      (3U)
+#define SPDIFRX_IFCR_OVRCF_Msk      (0x1UL << SPDIFRX_IFCR_OVRCF_Pos)          /*!< 0x00000008 */
+#define SPDIFRX_IFCR_OVRCF          SPDIFRX_IFCR_OVRCF_Msk                     /*!<Clears the Overrun error flag                        */
+#define SPDIFRX_IFCR_SBDCF_Pos      (4U)
+#define SPDIFRX_IFCR_SBDCF_Msk      (0x1UL << SPDIFRX_IFCR_SBDCF_Pos)          /*!< 0x00000010 */
+#define SPDIFRX_IFCR_SBDCF          SPDIFRX_IFCR_SBDCF_Msk                     /*!<Clears the Synchronization Block Detected flag       */
+#define SPDIFRX_IFCR_SYNCDCF_Pos    (5U)
+#define SPDIFRX_IFCR_SYNCDCF_Msk    (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos)        /*!< 0x00000020 */
+#define SPDIFRX_IFCR_SYNCDCF        SPDIFRX_IFCR_SYNCDCF_Msk                   /*!<Clears the Synchronization Done flag                 */
+
+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b00 case) *******************/
+#define SPDIFRX_DR0_DR_Pos          (0U)
+#define SPDIFRX_DR0_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos)         /*!< 0x00FFFFFF */
+#define SPDIFRX_DR0_DR              SPDIFRX_DR0_DR_Msk                         /*!<Data value            */
+#define SPDIFRX_DR0_PE_Pos          (24U)
+#define SPDIFRX_DR0_PE_Msk          (0x1UL << SPDIFRX_DR0_PE_Pos)              /*!< 0x01000000 */
+#define SPDIFRX_DR0_PE              SPDIFRX_DR0_PE_Msk                         /*!<Parity Error bit      */
+#define SPDIFRX_DR0_V_Pos           (25U)
+#define SPDIFRX_DR0_V_Msk           (0x1UL << SPDIFRX_DR0_V_Pos)               /*!< 0x02000000 */
+#define SPDIFRX_DR0_V               SPDIFRX_DR0_V_Msk                          /*!<Validity bit          */
+#define SPDIFRX_DR0_U_Pos           (26U)
+#define SPDIFRX_DR0_U_Msk           (0x1UL << SPDIFRX_DR0_U_Pos)               /*!< 0x04000000 */
+#define SPDIFRX_DR0_U               SPDIFRX_DR0_U_Msk                          /*!<User bit              */
+#define SPDIFRX_DR0_C_Pos           (27U)
+#define SPDIFRX_DR0_C_Msk           (0x1UL << SPDIFRX_DR0_C_Pos)               /*!< 0x08000000 */
+#define SPDIFRX_DR0_C               SPDIFRX_DR0_C_Msk                          /*!<Channel Status bit    */
+#define SPDIFRX_DR0_PT_Pos          (28U)
+#define SPDIFRX_DR0_PT_Msk          (0x3UL << SPDIFRX_DR0_PT_Pos)              /*!< 0x30000000 */
+#define SPDIFRX_DR0_PT              SPDIFRX_DR0_PT_Msk                         /*!<Preamble Type         */
+
+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b01 case) *******************/
+#define SPDIFRX_DR1_DR_Pos          (8U)
+#define SPDIFRX_DR1_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos)         /*!< 0xFFFFFF00 */
+#define SPDIFRX_DR1_DR              SPDIFRX_DR1_DR_Msk                         /*!<Data value            */
+#define SPDIFRX_DR1_PT_Pos          (4U)
+#define SPDIFRX_DR1_PT_Msk          (0x3UL << SPDIFRX_DR1_PT_Pos)              /*!< 0x00000030 */
+#define SPDIFRX_DR1_PT              SPDIFRX_DR1_PT_Msk                         /*!<Preamble Type         */
+#define SPDIFRX_DR1_C_Pos           (3U)
+#define SPDIFRX_DR1_C_Msk           (0x1UL << SPDIFRX_DR1_C_Pos)               /*!< 0x00000008 */
+#define SPDIFRX_DR1_C               SPDIFRX_DR1_C_Msk                          /*!<Channel Status bit    */
+#define SPDIFRX_DR1_U_Pos           (2U)
+#define SPDIFRX_DR1_U_Msk           (0x1UL << SPDIFRX_DR1_U_Pos)               /*!< 0x00000004 */
+#define SPDIFRX_DR1_U               SPDIFRX_DR1_U_Msk                          /*!<User bit              */
+#define SPDIFRX_DR1_V_Pos           (1U)
+#define SPDIFRX_DR1_V_Msk           (0x1UL << SPDIFRX_DR1_V_Pos)               /*!< 0x00000002 */
+#define SPDIFRX_DR1_V               SPDIFRX_DR1_V_Msk                          /*!<Validity bit          */
+#define SPDIFRX_DR1_PE_Pos          (0U)
+#define SPDIFRX_DR1_PE_Msk          (0x1UL << SPDIFRX_DR1_PE_Pos)              /*!< 0x00000001 */
+#define SPDIFRX_DR1_PE              SPDIFRX_DR1_PE_Msk                         /*!<Parity Error bit      */
+
+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b10 case) *******************/
+#define SPDIFRX_DR1_DRNL1_Pos       (16U)
+#define SPDIFRX_DR1_DRNL1_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos)        /*!< 0xFFFF0000 */
+#define SPDIFRX_DR1_DRNL1           SPDIFRX_DR1_DRNL1_Msk                      /*!<Data value Channel B      */
+#define SPDIFRX_DR1_DRNL2_Pos       (0U)
+#define SPDIFRX_DR1_DRNL2_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos)        /*!< 0x0000FFFF */
+#define SPDIFRX_DR1_DRNL2           SPDIFRX_DR1_DRNL2_Msk                      /*!<Data value Channel A      */
+
+/*******************  Bit definition for SPDIFRX_CSR register   *******************/
+#define SPDIFRX_CSR_USR_Pos         (0U)
+#define SPDIFRX_CSR_USR_Msk         (0xFFFFUL << SPDIFRX_CSR_USR_Pos)          /*!< 0x0000FFFF */
+#define SPDIFRX_CSR_USR             SPDIFRX_CSR_USR_Msk                        /*!<User data information           */
+#define SPDIFRX_CSR_CS_Pos          (16U)
+#define SPDIFRX_CSR_CS_Msk          (0xFFUL << SPDIFRX_CSR_CS_Pos)             /*!< 0x00FF0000 */
+#define SPDIFRX_CSR_CS              SPDIFRX_CSR_CS_Msk                         /*!<Channel A status information    */
+#define SPDIFRX_CSR_SOB_Pos         (24U)
+#define SPDIFRX_CSR_SOB_Msk         (0x1UL << SPDIFRX_CSR_SOB_Pos)             /*!< 0x01000000 */
+#define SPDIFRX_CSR_SOB             SPDIFRX_CSR_SOB_Msk                        /*!<Start Of Block                  */
+
+/*******************  Bit definition for SPDIFRX_DIR register    *******************/
+#define SPDIFRX_DIR_THI_Pos         (0U)
+#define SPDIFRX_DIR_THI_Msk         (0x1FFFUL << SPDIFRX_DIR_THI_Pos)          /*!< 0x00001FFF */
+#define SPDIFRX_DIR_THI             SPDIFRX_DIR_THI_Msk                        /*!<Threshold LOW      */
+#define SPDIFRX_DIR_TLO_Pos         (16U)
+#define SPDIFRX_DIR_TLO_Msk         (0x1FFFUL << SPDIFRX_DIR_TLO_Pos)          /*!< 0x1FFF0000 */
+#define SPDIFRX_DIR_TLO             SPDIFRX_DIR_TLO_Msk                        /*!<Threshold HIGH     */
+
+/*******************  Bit definition for SPDIFRX_VERR register    *******************/
+#define SPDIFRX_VERR_MINREV_Pos     (0U)
+#define SPDIFRX_VERR_MINREV_Msk     (0xFUL << SPDIFRX_VERR_MINREV_Pos)         /*!< 0x0000000F */
+#define SPDIFRX_VERR_MINREV         SPDIFRX_VERR_MINREV_Msk                    /*!<SPDIFRX Minor revision     */
+#define SPDIFRX_VERR_MAJREV_Pos     (4U)
+#define SPDIFRX_VERR_MAJREV_Msk     (0xFUL << SPDIFRX_VERR_MAJREV_Pos)         /*!< 0x000000F0 */
+#define SPDIFRX_VERR_MAJREV         SPDIFRX_VERR_MAJREV_Msk                    /*!<SPDIFRX Major revision     */
+
+/*******************  Bit definition for SPDIFRX_IDR register    *******************/
+#define SPDIFRX_IDR_ID_Pos          (0U)
+#define SPDIFRX_IDR_ID_Msk          (0xFFFFFFFFUL << SPDIFRX_IDR_ID_Pos)       /*!< 0xFFFFFFFF */
+#define SPDIFRX_IDR_ID              SPDIFRX_IDR_ID_Msk                         /*!<SPDIFRX identifier     */
+
+/*******************  Bit definition for SPDIFRX_SIDR register    *******************/
+#define SPDIFRX_SIDR_SID_Pos        (0U)
+#define SPDIFRX_SIDR_SID_Msk        (0xFFFFFFFFUL << SPDIFRX_SIDR_SID_Pos)     /*!< 0xFFFFFFFF */
+#define SPDIFRX_SIDR_SID            SPDIFRX_SIDR_SID_Msk                       /*!<Size of the memory region allocated to SPDIFRX registers */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Serial Audio Interface                            */
+/*                                                                            */
+/******************************************************************************/
+/*******************************  SAI VERSION  ********************************/
+#define SAI_VER_V2_X
+
+/********************  Bit definition for SAI_GCR register  *******************/
+#define SAI_GCR_SYNCIN_Pos         (0U)
+#define SAI_GCR_SYNCIN_Msk         (0x3UL << SAI_GCR_SYNCIN_Pos)               /*!< 0x00000003 */
+#define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
+#define SAI_GCR_SYNCIN_0           (0x1UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */
+#define SAI_GCR_SYNCIN_1           (0x2UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */
+
+#define SAI_GCR_SYNCOUT_Pos        (4U)
+#define SAI_GCR_SYNCOUT_Msk        (0x3UL << SAI_GCR_SYNCOUT_Pos)              /*!< 0x00000030 */
+#define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define SAI_GCR_SYNCOUT_0          (0x1UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */
+#define SAI_GCR_SYNCOUT_1          (0x2UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */
+
+/*******************  Bit definition for SAI_xCR1 register  *******************/
+#define SAI_xCR1_MODE_Pos          (0U)
+#define SAI_xCR1_MODE_Msk          (0x3UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000003 */
+#define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */
+#define SAI_xCR1_MODE_0            (0x1UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */
+#define SAI_xCR1_MODE_1            (0x2UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */
+
+#define SAI_xCR1_PRTCFG_Pos        (2U)
+#define SAI_xCR1_PRTCFG_Msk        (0x3UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x0000000C */
+#define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
+#define SAI_xCR1_PRTCFG_0          (0x1UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */
+#define SAI_xCR1_PRTCFG_1          (0x2UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */
+
+#define SAI_xCR1_DS_Pos            (5U)
+#define SAI_xCR1_DS_Msk            (0x7UL << SAI_xCR1_DS_Pos)                  /*!< 0x000000E0 */
+#define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */
+#define SAI_xCR1_DS_0              (0x1UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */
+#define SAI_xCR1_DS_1              (0x2UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */
+#define SAI_xCR1_DS_2              (0x4UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */
+
+#define SAI_xCR1_LSBFIRST_Pos      (8U)
+#define SAI_xCR1_LSBFIRST_Msk      (0x1UL << SAI_xCR1_LSBFIRST_Pos)            /*!< 0x00000100 */
+#define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */
+#define SAI_xCR1_CKSTR_Pos         (9U)
+#define SAI_xCR1_CKSTR_Msk         (0x1UL << SAI_xCR1_CKSTR_Pos)               /*!< 0x00000200 */
+#define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */
+
+#define SAI_xCR1_SYNCEN_Pos        (10U)
+#define SAI_xCR1_SYNCEN_Msk        (0x3UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000C00 */
+#define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define SAI_xCR1_SYNCEN_0          (0x1UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */
+#define SAI_xCR1_SYNCEN_1          (0x2UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */
+
+#define SAI_xCR1_MONO_Pos          (12U)
+#define SAI_xCR1_MONO_Msk          (0x1UL << SAI_xCR1_MONO_Pos)                /*!< 0x00001000 */
+#define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */
+#define SAI_xCR1_OUTDRIV_Pos       (13U)
+#define SAI_xCR1_OUTDRIV_Msk       (0x1UL << SAI_xCR1_OUTDRIV_Pos)             /*!< 0x00002000 */
+#define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */
+#define SAI_xCR1_SAIEN_Pos         (16U)
+#define SAI_xCR1_SAIEN_Msk         (0x1UL << SAI_xCR1_SAIEN_Pos)               /*!< 0x00010000 */
+#define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */
+#define SAI_xCR1_DMAEN_Pos         (17U)
+#define SAI_xCR1_DMAEN_Msk         (0x1UL << SAI_xCR1_DMAEN_Pos)               /*!< 0x00020000 */
+#define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */
+#define SAI_xCR1_NODIV_Pos         (19U)
+#define SAI_xCR1_NODIV_Msk         (0x1UL << SAI_xCR1_NODIV_Pos)               /*!< 0x00080000 */
+#define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */
+
+#define SAI_xCR1_MCKDIV_Pos        (20U)
+#define SAI_xCR1_MCKDIV_Msk        (0x3FUL << SAI_xCR1_MCKDIV_Pos)             /*!< 0x03F00000 */
+#define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[5:0] (Master ClocK Divider)  */
+#define SAI_xCR1_MCKDIV_0          (0x01UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00100000 */
+#define SAI_xCR1_MCKDIV_1          (0x02UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00200000 */
+#define SAI_xCR1_MCKDIV_2          (0x04UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00400000 */
+#define SAI_xCR1_MCKDIV_3          (0x08UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00800000 */
+#define SAI_xCR1_MCKDIV_4          (0x10UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x01000000 */
+#define SAI_xCR1_MCKDIV_5          (0x20UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x02000000 */
+
+#define SAI_xCR1_MCKEN_Pos         (27U)
+#define SAI_xCR1_MCKEN_Msk         (0x1UL << SAI_xCR1_MCKEN_Pos)               /*!< 0x08000000 */
+#define SAI_xCR1_MCKEN             SAI_xCR1_MCKEN_Msk                          /*!<Master ClocK enable */
+
+#define SAI_xCR1_OSR_Pos           (26U)
+#define SAI_xCR1_OSR_Msk           (0x1UL << SAI_xCR1_OSR_Pos)                 /*!< 0x04000000 */
+#define SAI_xCR1_OSR               SAI_xCR1_OSR_Msk                            /*!<OverSampling Ratio for master clock  */
+
+/* Legacy define */
+#define  SAI_xCR1_NOMCK               SAI_xCR1_NODIV
+
+/*******************  Bit definition for SAI_xCR2 register  *******************/
+#define SAI_xCR2_FTH_Pos           (0U)
+#define SAI_xCR2_FTH_Msk           (0x7UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000007 */
+#define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */
+#define SAI_xCR2_FTH_0             (0x1UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */
+#define SAI_xCR2_FTH_1             (0x2UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */
+#define SAI_xCR2_FTH_2             (0x4UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */
+
+#define SAI_xCR2_FFLUSH_Pos        (3U)
+#define SAI_xCR2_FFLUSH_Msk        (0x1UL << SAI_xCR2_FFLUSH_Pos)              /*!< 0x00000008 */
+#define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */
+#define SAI_xCR2_TRIS_Pos          (4U)
+#define SAI_xCR2_TRIS_Msk          (0x1UL << SAI_xCR2_TRIS_Pos)                /*!< 0x00000010 */
+#define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */
+#define SAI_xCR2_MUTE_Pos          (5U)
+#define SAI_xCR2_MUTE_Msk          (0x1UL << SAI_xCR2_MUTE_Pos)                /*!< 0x00000020 */
+#define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */
+#define SAI_xCR2_MUTEVAL_Pos       (6U)
+#define SAI_xCR2_MUTEVAL_Msk       (0x1UL << SAI_xCR2_MUTEVAL_Pos)             /*!< 0x00000040 */
+#define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */
+
+#define SAI_xCR2_MUTECNT_Pos       (7U)
+#define SAI_xCR2_MUTECNT_Msk       (0x3FUL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00001F80 */
+#define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */
+#define SAI_xCR2_MUTECNT_0         (0x01UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */
+#define SAI_xCR2_MUTECNT_1         (0x02UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */
+#define SAI_xCR2_MUTECNT_2         (0x04UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */
+#define SAI_xCR2_MUTECNT_3         (0x08UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */
+#define SAI_xCR2_MUTECNT_4         (0x10UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */
+#define SAI_xCR2_MUTECNT_5         (0x20UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */
+
+#define SAI_xCR2_CPL_Pos           (13U)
+#define SAI_xCR2_CPL_Msk           (0x1UL << SAI_xCR2_CPL_Pos)                 /*!< 0x00002000 */
+#define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!< Complement Bit             */
+
+#define SAI_xCR2_COMP_Pos          (14U)
+#define SAI_xCR2_COMP_Msk          (0x3UL << SAI_xCR2_COMP_Pos)                /*!< 0x0000C000 */
+#define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */
+#define SAI_xCR2_COMP_0            (0x1UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */
+#define SAI_xCR2_COMP_1            (0x2UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */
+
+/******************  Bit definition for SAI_xFRCR register  *******************/
+#define SAI_xFRCR_FRL_Pos          (0U)
+#define SAI_xFRCR_FRL_Msk          (0xFFUL << SAI_xFRCR_FRL_Pos)               /*!< 0x000000FF */
+#define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](FRame Length)  */
+#define SAI_xFRCR_FRL_0            (0x01UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */
+#define SAI_xFRCR_FRL_1            (0x02UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */
+#define SAI_xFRCR_FRL_2            (0x04UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */
+#define SAI_xFRCR_FRL_3            (0x08UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */
+#define SAI_xFRCR_FRL_4            (0x10UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */
+#define SAI_xFRCR_FRL_5            (0x20UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */
+#define SAI_xFRCR_FRL_6            (0x40UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */
+#define SAI_xFRCR_FRL_7            (0x80UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */
+
+#define SAI_xFRCR_FSALL_Pos        (8U)
+#define SAI_xFRCR_FSALL_Msk        (0x7FUL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00007F00 */
+#define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FSALL[6:0] (Frame Synchronization Active Level Length)  */
+#define SAI_xFRCR_FSALL_0          (0x01UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */
+#define SAI_xFRCR_FSALL_1          (0x02UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */
+#define SAI_xFRCR_FSALL_2          (0x04UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */
+#define SAI_xFRCR_FSALL_3          (0x08UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */
+#define SAI_xFRCR_FSALL_4          (0x10UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */
+#define SAI_xFRCR_FSALL_5          (0x20UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */
+#define SAI_xFRCR_FSALL_6          (0x40UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */
+
+#define SAI_xFRCR_FSDEF_Pos        (16U)
+#define SAI_xFRCR_FSDEF_Msk        (0x1UL << SAI_xFRCR_FSDEF_Pos)              /*!< 0x00010000 */
+#define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!<Frame Synchronization Definition  */
+#define SAI_xFRCR_FSPOL_Pos        (17U)
+#define SAI_xFRCR_FSPOL_Msk        (0x1UL << SAI_xFRCR_FSPOL_Pos)              /*!< 0x00020000 */
+#define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */
+#define SAI_xFRCR_FSOFF_Pos        (18U)
+#define SAI_xFRCR_FSOFF_Msk        (0x1UL << SAI_xFRCR_FSOFF_Pos)              /*!< 0x00040000 */
+#define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */
+
+/* Legacy define */
+#define  SAI_xFRCR_FSPO                      SAI_xFRCR_FSPOL
+
+/******************  Bit definition for SAI_xSLOTR register  *******************/
+#define SAI_xSLOTR_FBOFF_Pos       (0U)
+#define SAI_xSLOTR_FBOFF_Msk       (0x1FUL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x0000001F */
+#define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FBOFF[4:0](First Bit Offset)  */
+#define SAI_xSLOTR_FBOFF_0         (0x01UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */
+#define SAI_xSLOTR_FBOFF_1         (0x02UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */
+#define SAI_xSLOTR_FBOFF_2         (0x04UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */
+#define SAI_xSLOTR_FBOFF_3         (0x08UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */
+#define SAI_xSLOTR_FBOFF_4         (0x10UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */
+
+#define SAI_xSLOTR_SLOTSZ_Pos      (6U)
+#define SAI_xSLOTR_SLOTSZ_Msk      (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x000000C0 */
+#define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */
+#define SAI_xSLOTR_SLOTSZ_0        (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */
+#define SAI_xSLOTR_SLOTSZ_1        (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */
+
+#define SAI_xSLOTR_NBSLOT_Pos      (8U)
+#define SAI_xSLOTR_NBSLOT_Msk      (0xFUL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000F00 */
+#define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
+#define SAI_xSLOTR_NBSLOT_0        (0x1UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */
+#define SAI_xSLOTR_NBSLOT_1        (0x2UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */
+#define SAI_xSLOTR_NBSLOT_2        (0x4UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */
+#define SAI_xSLOTR_NBSLOT_3        (0x8UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */
+
+#define SAI_xSLOTR_SLOTEN_Pos      (16U)
+#define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)         /*!< 0xFFFF0000 */
+#define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */
+
+/*******************  Bit definition for SAI_xIMR register  *******************/
+#define SAI_xIMR_OVRUDRIE_Pos      (0U)
+#define SAI_xIMR_OVRUDRIE_Msk      (0x1UL << SAI_xIMR_OVRUDRIE_Pos)            /*!< 0x00000001 */
+#define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */
+#define SAI_xIMR_MUTEDETIE_Pos     (1U)
+#define SAI_xIMR_MUTEDETIE_Msk     (0x1UL << SAI_xIMR_MUTEDETIE_Pos)           /*!< 0x00000002 */
+#define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */
+#define SAI_xIMR_WCKCFGIE_Pos      (2U)
+#define SAI_xIMR_WCKCFGIE_Msk      (0x1UL << SAI_xIMR_WCKCFGIE_Pos)            /*!< 0x00000004 */
+#define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */
+#define SAI_xIMR_FREQIE_Pos        (3U)
+#define SAI_xIMR_FREQIE_Msk        (0x1UL << SAI_xIMR_FREQIE_Pos)              /*!< 0x00000008 */
+#define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */
+#define SAI_xIMR_CNRDYIE_Pos       (4U)
+#define SAI_xIMR_CNRDYIE_Msk       (0x1UL << SAI_xIMR_CNRDYIE_Pos)             /*!< 0x00000010 */
+#define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */
+#define SAI_xIMR_AFSDETIE_Pos      (5U)
+#define SAI_xIMR_AFSDETIE_Msk      (0x1UL << SAI_xIMR_AFSDETIE_Pos)            /*!< 0x00000020 */
+#define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */
+#define SAI_xIMR_LFSDETIE_Pos      (6U)
+#define SAI_xIMR_LFSDETIE_Msk      (0x1UL << SAI_xIMR_LFSDETIE_Pos)            /*!< 0x00000040 */
+#define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */
+
+/********************  Bit definition for SAI_xSR register  *******************/
+#define SAI_xSR_OVRUDR_Pos         (0U)
+#define SAI_xSR_OVRUDR_Msk         (0x1UL << SAI_xSR_OVRUDR_Pos)               /*!< 0x00000001 */
+#define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */
+#define SAI_xSR_MUTEDET_Pos        (1U)
+#define SAI_xSR_MUTEDET_Msk        (0x1UL << SAI_xSR_MUTEDET_Pos)              /*!< 0x00000002 */
+#define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */
+#define SAI_xSR_WCKCFG_Pos         (2U)
+#define SAI_xSR_WCKCFG_Msk         (0x1UL << SAI_xSR_WCKCFG_Pos)               /*!< 0x00000004 */
+#define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */
+#define SAI_xSR_FREQ_Pos           (3U)
+#define SAI_xSR_FREQ_Msk           (0x1UL << SAI_xSR_FREQ_Pos)                 /*!< 0x00000008 */
+#define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */
+#define SAI_xSR_CNRDY_Pos          (4U)
+#define SAI_xSR_CNRDY_Msk          (0x1UL << SAI_xSR_CNRDY_Pos)                /*!< 0x00000010 */
+#define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */
+#define SAI_xSR_AFSDET_Pos         (5U)
+#define SAI_xSR_AFSDET_Msk         (0x1UL << SAI_xSR_AFSDET_Pos)               /*!< 0x00000020 */
+#define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */
+#define SAI_xSR_LFSDET_Pos         (6U)
+#define SAI_xSR_LFSDET_Msk         (0x1UL << SAI_xSR_LFSDET_Pos)               /*!< 0x00000040 */
+#define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */
+
+#define SAI_xSR_FLVL_Pos           (16U)
+#define SAI_xSR_FLVL_Msk           (0x7UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00070000 */
+#define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */
+#define SAI_xSR_FLVL_0             (0x1UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */
+#define SAI_xSR_FLVL_1             (0x2UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */
+#define SAI_xSR_FLVL_2             (0x4UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */
+
+/******************  Bit definition for SAI_xCLRFR register  ******************/
+#define SAI_xCLRFR_COVRUDR_Pos     (0U)
+#define SAI_xCLRFR_COVRUDR_Msk     (0x1UL << SAI_xCLRFR_COVRUDR_Pos)           /*!< 0x00000001 */
+#define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */
+#define SAI_xCLRFR_CMUTEDET_Pos    (1U)
+#define SAI_xCLRFR_CMUTEDET_Msk    (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)          /*!< 0x00000002 */
+#define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */
+#define SAI_xCLRFR_CWCKCFG_Pos     (2U)
+#define SAI_xCLRFR_CWCKCFG_Msk     (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)           /*!< 0x00000004 */
+#define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */
+#define SAI_xCLRFR_CFREQ_Pos       (3U)
+#define SAI_xCLRFR_CFREQ_Msk       (0x1UL << SAI_xCLRFR_CFREQ_Pos)             /*!< 0x00000008 */
+#define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */
+#define SAI_xCLRFR_CCNRDY_Pos      (4U)
+#define SAI_xCLRFR_CCNRDY_Msk      (0x1UL << SAI_xCLRFR_CCNRDY_Pos)            /*!< 0x00000010 */
+#define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */
+#define SAI_xCLRFR_CAFSDET_Pos     (5U)
+#define SAI_xCLRFR_CAFSDET_Msk     (0x1UL << SAI_xCLRFR_CAFSDET_Pos)           /*!< 0x00000020 */
+#define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */
+#define SAI_xCLRFR_CLFSDET_Pos     (6U)
+#define SAI_xCLRFR_CLFSDET_Msk     (0x1UL << SAI_xCLRFR_CLFSDET_Pos)           /*!< 0x00000040 */
+#define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */
+
+/******************  Bit definition for SAI_xDR register  *********************/
+#define SAI_xDR_DATA_Pos           (0U)
+#define SAI_xDR_DATA_Msk           (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)          /*!< 0xFFFFFFFF */
+#define SAI_xDR_DATA               SAI_xDR_DATA_Msk
+
+/*******************  Bit definition for SAI_PDMCR register  ******************/
+#define SAI_PDMCR_PDMEN_Pos        (0U)
+#define SAI_PDMCR_PDMEN_Msk        (0x1UL << SAI_PDMCR_PDMEN_Pos)              /*!< 0x00000001 */
+#define SAI_PDMCR_PDMEN            SAI_PDMCR_PDMEN_Msk                         /*!<PDM Enable                                          */
+
+#define SAI_PDMCR_MICNBR_Pos       (4U)
+#define SAI_PDMCR_MICNBR_Msk       (0x3UL << SAI_PDMCR_MICNBR_Pos)             /*!< 0x00000030 */
+#define SAI_PDMCR_MICNBR           SAI_PDMCR_MICNBR_Msk                        /*!<Number of microphones                               */
+#define SAI_PDMCR_MICNBR_0         (0x1UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000010 */
+#define SAI_PDMCR_MICNBR_1         (0x2UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000020 */
+
+#define SAI_PDMCR_CKEN1_Pos        (8U)
+#define SAI_PDMCR_CKEN1_Msk        (0x1UL << SAI_PDMCR_CKEN1_Pos)              /*!< 0x00000100 */
+#define SAI_PDMCR_CKEN1            SAI_PDMCR_CKEN1_Msk                         /*!<Clock enable of bitstream clock number 1            */
+#define SAI_PDMCR_CKEN2_Pos        (9U)
+#define SAI_PDMCR_CKEN2_Msk        (0x1UL << SAI_PDMCR_CKEN2_Pos)              /*!< 0x00000200 */
+#define SAI_PDMCR_CKEN2            SAI_PDMCR_CKEN2_Msk                         /*!<Clock enable of bitstream clock number 2            */
+#define SAI_PDMCR_CKEN3_Pos        (10U)
+#define SAI_PDMCR_CKEN3_Msk        (0x1UL << SAI_PDMCR_CKEN3_Pos)              /*!< 0x00000400 */
+#define SAI_PDMCR_CKEN3            SAI_PDMCR_CKEN3_Msk                         /*!<Clock enable of bitstream clock number 3            */
+#define SAI_PDMCR_CKEN4_Pos        (11U)
+#define SAI_PDMCR_CKEN4_Msk        (0x1UL << SAI_PDMCR_CKEN4_Pos)              /*!< 0x00000800 */
+#define SAI_PDMCR_CKEN4            SAI_PDMCR_CKEN4_Msk                         /*!<Clock enable of bitstream clock number 4            */
+
+/******************  Bit definition for SAI_PDMDLY register  ******************/
+#define SAI_PDMDLY_DLYM1L_Pos      (0U)
+#define SAI_PDMDLY_DLYM1L_Msk      (0x7UL << SAI_PDMDLY_DLYM1L_Pos)            /*!< 0x00000007 */
+#define SAI_PDMDLY_DLYM1L          SAI_PDMDLY_DLYM1L_Msk                       /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */
+#define SAI_PDMDLY_DLYM1L_0        (0x1UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000001 */
+#define SAI_PDMDLY_DLYM1L_1        (0x2UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000002 */
+#define SAI_PDMDLY_DLYM1L_2        (0x4UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000004 */
+
+#define SAI_PDMDLY_DLYM1R_Pos      (4U)
+#define SAI_PDMDLY_DLYM1R_Msk      (0x7UL << SAI_PDMDLY_DLYM1R_Pos)            /*!< 0x00000070 */
+#define SAI_PDMDLY_DLYM1R          SAI_PDMDLY_DLYM1R_Msk                       /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */
+#define SAI_PDMDLY_DLYM1R_0        (0x1UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000010 */
+#define SAI_PDMDLY_DLYM1R_1        (0x2UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000020 */
+#define SAI_PDMDLY_DLYM1R_2        (0x4UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000040 */
+
+#define SAI_PDMDLY_DLYM2L_Pos      (8U)
+#define SAI_PDMDLY_DLYM2L_Msk      (0x7UL << SAI_PDMDLY_DLYM2L_Pos)            /*!< 0x00000700 */
+#define SAI_PDMDLY_DLYM2L          SAI_PDMDLY_DLYM2L_Msk                       /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */
+#define SAI_PDMDLY_DLYM2L_0        (0x1UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000100 */
+#define SAI_PDMDLY_DLYM2L_1        (0x2UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000200 */
+#define SAI_PDMDLY_DLYM2L_2        (0x4UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000400 */
+
+#define SAI_PDMDLY_DLYM2R_Pos      (12U)
+#define SAI_PDMDLY_DLYM2R_Msk      (0x7UL << SAI_PDMDLY_DLYM2R_Pos)            /*!< 0x00007000 */
+#define SAI_PDMDLY_DLYM2R          SAI_PDMDLY_DLYM2R_Msk                       /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2)*/
+#define SAI_PDMDLY_DLYM2R_0        (0x1UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00001000 */
+#define SAI_PDMDLY_DLYM2R_1        (0x2UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00002000 */
+#define SAI_PDMDLY_DLYM2R_2        (0x4UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00004000 */
+
+#define SAI_PDMDLY_DLYM3L_Pos      (16U)
+#define SAI_PDMDLY_DLYM3L_Msk      (0x7UL << SAI_PDMDLY_DLYM3L_Pos)            /*!< 0x00070000 */
+#define SAI_PDMDLY_DLYM3L          SAI_PDMDLY_DLYM3L_Msk                       /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3)*/
+#define SAI_PDMDLY_DLYM3L_0        (0x1UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00010000 */
+#define SAI_PDMDLY_DLYM3L_1        (0x2UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00020000 */
+#define SAI_PDMDLY_DLYM3L_2        (0x4UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00040000 */
+
+#define SAI_PDMDLY_DLYM3R_Pos      (20U)
+#define SAI_PDMDLY_DLYM3R_Msk      (0x7UL << SAI_PDMDLY_DLYM3R_Pos)            /*!< 0x00700000 */
+#define SAI_PDMDLY_DLYM3R          SAI_PDMDLY_DLYM3R_Msk                       /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3)*/
+#define SAI_PDMDLY_DLYM3R_0        (0x1UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00100000 */
+#define SAI_PDMDLY_DLYM3R_1        (0x2UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00200000 */
+#define SAI_PDMDLY_DLYM3R_2        (0x4UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00400000 */
+
+#define SAI_PDMDLY_DLYM4L_Pos      (24U)
+#define SAI_PDMDLY_DLYM4L_Msk      (0x7UL << SAI_PDMDLY_DLYM4L_Pos)            /*!< 0x07000000 */
+#define SAI_PDMDLY_DLYM4L          SAI_PDMDLY_DLYM4L_Msk                       /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4)*/
+#define SAI_PDMDLY_DLYM4L_0        (0x1UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x01000000 */
+#define SAI_PDMDLY_DLYM4L_1        (0x2UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x02000000 */
+#define SAI_PDMDLY_DLYM4L_2        (0x4UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x04000000 */
+
+#define SAI_PDMDLY_DLYM4R_Pos      (28U)
+#define SAI_PDMDLY_DLYM4R_Msk      (0x7UL << SAI_PDMDLY_DLYM4R_Pos)            /*!< 0x70000000 */
+#define SAI_PDMDLY_DLYM4R          SAI_PDMDLY_DLYM4R_Msk                       /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4)*/
+#define SAI_PDMDLY_DLYM4R_0        (0x1UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x10000000 */
+#define SAI_PDMDLY_DLYM4R_1        (0x2UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x20000000 */
+#define SAI_PDMDLY_DLYM4R_2        (0x4UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x40000000 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           SDMMC Interface                                  */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SDMMC_POWER register  ******************/
+#define SDMMC_POWER_PWRCTRL_Pos          (0U)
+#define SDMMC_POWER_PWRCTRL_Msk          (0x3UL << SDMMC_POWER_PWRCTRL_Pos)    /*!< 0x00000003 */
+#define SDMMC_POWER_PWRCTRL              SDMMC_POWER_PWRCTRL_Msk               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDMMC_POWER_PWRCTRL_0            (0x1UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000001 */
+#define SDMMC_POWER_PWRCTRL_1            (0x2UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000002 */
+#define SDMMC_POWER_VSWITCH_Pos          (2U)
+#define SDMMC_POWER_VSWITCH_Msk          (0x1UL << SDMMC_POWER_VSWITCH_Pos)    /*!< 0x00000004 */
+#define SDMMC_POWER_VSWITCH              SDMMC_POWER_VSWITCH_Msk               /*!<Voltage switch sequence start */
+#define SDMMC_POWER_VSWITCHEN_Pos        (3U)
+#define SDMMC_POWER_VSWITCHEN_Msk        (0x1UL << SDMMC_POWER_VSWITCHEN_Pos)  /*!< 0x00000008 */
+#define SDMMC_POWER_VSWITCHEN            SDMMC_POWER_VSWITCHEN_Msk             /*!<Voltage switch procedure enable */
+#define SDMMC_POWER_DIRPOL_Pos           (4U)
+#define SDMMC_POWER_DIRPOL_Msk           (0x1UL << SDMMC_POWER_DIRPOL_Pos)     /*!< 0x00000010 */
+#define SDMMC_POWER_DIRPOL               SDMMC_POWER_DIRPOL_Msk                /*!<Data and Command direction signals polarity selection */
+
+/******************  Bit definition for SDMMC_CLKCR register  ******************/
+#define SDMMC_CLKCR_CLKDIV_Pos           (0U)
+#define SDMMC_CLKCR_CLKDIV_Msk           (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos)   /*!< 0x000003FF */
+#define SDMMC_CLKCR_CLKDIV               SDMMC_CLKCR_CLKDIV_Msk                /*!<Clock divide factor             */
+#define SDMMC_CLKCR_PWRSAV_Pos           (12U)
+#define SDMMC_CLKCR_PWRSAV_Msk           (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)     /*!< 0x00001000 */
+#define SDMMC_CLKCR_PWRSAV               SDMMC_CLKCR_PWRSAV_Msk                /*!<Power saving configuration bit  */
+
+#define SDMMC_CLKCR_WIDBUS_Pos           (14U)
+#define SDMMC_CLKCR_WIDBUS_Msk           (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)     /*!< 0x0000C000 */
+#define SDMMC_CLKCR_WIDBUS               SDMMC_CLKCR_WIDBUS_Msk                /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDMMC_CLKCR_WIDBUS_0             (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00004000 */
+#define SDMMC_CLKCR_WIDBUS_1             (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00008000 */
+
+#define SDMMC_CLKCR_NEGEDGE_Pos          (16U)
+#define SDMMC_CLKCR_NEGEDGE_Msk          (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)    /*!< 0x00010000 */
+#define SDMMC_CLKCR_NEGEDGE              SDMMC_CLKCR_NEGEDGE_Msk               /*!<SDMMC_CK dephasing selection bit */
+#define SDMMC_CLKCR_HWFC_EN_Pos          (17U)
+#define SDMMC_CLKCR_HWFC_EN_Msk          (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)    /*!< 0x00020000 */
+#define SDMMC_CLKCR_HWFC_EN              SDMMC_CLKCR_HWFC_EN_Msk               /*!<HW Flow Control enable           */
+#define SDMMC_CLKCR_DDR_Pos              (18U)
+#define SDMMC_CLKCR_DDR_Msk              (0x1UL << SDMMC_CLKCR_DDR_Pos)        /*!< 0x00040000 */
+#define SDMMC_CLKCR_DDR                  SDMMC_CLKCR_DDR_Msk                   /*!<Data rate signaling selection    */
+#define SDMMC_CLKCR_BUSSPEED_Pos         (19U)
+#define SDMMC_CLKCR_BUSSPEED_Msk         (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos)   /*!< 0x00080000 */
+#define SDMMC_CLKCR_BUSSPEED             SDMMC_CLKCR_BUSSPEED_Msk              /*!<Bus speed mode selection         */
+#define SDMMC_CLKCR_SELCLKRX_Pos         (20U)
+#define SDMMC_CLKCR_SELCLKRX_Msk         (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos)   /*!< 0x00300000 */
+#define SDMMC_CLKCR_SELCLKRX             SDMMC_CLKCR_SELCLKRX_Msk              /*!<SELCLKRX[1:0] bits (Receive clock selection) */
+#define SDMMC_CLKCR_SELCLKRX_0           (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00100000 */
+#define SDMMC_CLKCR_SELCLKRX_1           (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00200000 */
+
+/*******************  Bit definition for SDMMC_ARG register  *******************/
+#define SDMMC_ARG_CMDARG_Pos             (0U)
+#define SDMMC_ARG_CMDARG_Msk             (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_ARG_CMDARG                 SDMMC_ARG_CMDARG_Msk                  /*!<Command argument */
+
+/*******************  Bit definition for SDMMC_CMD register  *******************/
+#define SDMMC_CMD_CMDINDEX_Pos           (0U)
+#define SDMMC_CMD_CMDINDEX_Msk           (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)    /*!< 0x0000003F */
+#define SDMMC_CMD_CMDINDEX               SDMMC_CMD_CMDINDEX_Msk                /*!<Command Index                               */
+#define SDMMC_CMD_CMDTRANS_Pos           (6U)
+#define SDMMC_CMD_CMDTRANS_Msk           (0x1UL << SDMMC_CMD_CMDTRANS_Pos)     /*!< 0x00000040 */
+#define SDMMC_CMD_CMDTRANS               SDMMC_CMD_CMDTRANS_Msk                /*!<CPSM Treats command as a Data Transfer      */
+#define SDMMC_CMD_CMDSTOP_Pos            (7U)
+#define SDMMC_CMD_CMDSTOP_Msk            (0x1UL << SDMMC_CMD_CMDSTOP_Pos)      /*!< 0x00000080 */
+#define SDMMC_CMD_CMDSTOP                SDMMC_CMD_CMDSTOP_Msk                 /*!<CPSM Treats command as a Stop               */
+
+#define SDMMC_CMD_WAITRESP_Pos           (8U)
+#define SDMMC_CMD_WAITRESP_Msk           (0x3UL << SDMMC_CMD_WAITRESP_Pos)     /*!< 0x00000300 */
+#define SDMMC_CMD_WAITRESP               SDMMC_CMD_WAITRESP_Msk                /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDMMC_CMD_WAITRESP_0             (0x1UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000100 */
+#define SDMMC_CMD_WAITRESP_1             (0x2UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000200 */
+
+#define SDMMC_CMD_WAITINT_Pos            (10U)
+#define SDMMC_CMD_WAITINT_Msk            (0x1UL << SDMMC_CMD_WAITINT_Pos)      /*!< 0x00000400 */
+#define SDMMC_CMD_WAITINT                SDMMC_CMD_WAITINT_Msk                 /*!<CPSM Waits for Interrupt Request                               */
+#define SDMMC_CMD_WAITPEND_Pos           (11U)
+#define SDMMC_CMD_WAITPEND_Msk           (0x1UL << SDMMC_CMD_WAITPEND_Pos)     /*!< 0x00000800 */
+#define SDMMC_CMD_WAITPEND               SDMMC_CMD_WAITPEND_Msk                /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDMMC_CMD_CPSMEN_Pos             (12U)
+#define SDMMC_CMD_CPSMEN_Msk             (0x1UL << SDMMC_CMD_CPSMEN_Pos)       /*!< 0x00001000 */
+#define SDMMC_CMD_CPSMEN                 SDMMC_CMD_CPSMEN_Msk                  /*!<Command path state machine (CPSM) Enable bit                   */
+#define SDMMC_CMD_DTHOLD_Pos             (13U)
+#define SDMMC_CMD_DTHOLD_Msk             (0x1UL << SDMMC_CMD_DTHOLD_Pos)       /*!< 0x00002000 */
+#define SDMMC_CMD_DTHOLD                 SDMMC_CMD_DTHOLD_Msk                  /*!<Hold new data block transmission and reception in the DPSM     */
+#define SDMMC_CMD_BOOTMODE_Pos           (14U)
+#define SDMMC_CMD_BOOTMODE_Msk           (0x1UL << SDMMC_CMD_BOOTMODE_Pos)     /*!< 0x00004000 */
+#define SDMMC_CMD_BOOTMODE               SDMMC_CMD_BOOTMODE_Msk                /*!<Boot mode                                                      */
+#define SDMMC_CMD_BOOTEN_Pos             (15U)
+#define SDMMC_CMD_BOOTEN_Msk             (0x1UL << SDMMC_CMD_BOOTEN_Pos)       /*!< 0x00008000 */
+#define SDMMC_CMD_BOOTEN                 SDMMC_CMD_BOOTEN_Msk                  /*!<Enable Boot mode procedure                                     */
+#define SDMMC_CMD_CMDSUSPEND_Pos         (16U)
+#define SDMMC_CMD_CMDSUSPEND_Msk         (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos)   /*!< 0x00010000 */
+#define SDMMC_CMD_CMDSUSPEND             SDMMC_CMD_CMDSUSPEND_Msk              /*!<CPSM Treats command as a Suspend or Resume command             */
+
+/*****************  Bit definition for SDMMC_RESPCMD register  *****************/
+#define SDMMC_RESPCMD_RESPCMD_Pos        (0U)
+#define SDMMC_RESPCMD_RESPCMD_Msk        (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
+#define SDMMC_RESPCMD_RESPCMD            SDMMC_RESPCMD_RESPCMD_Msk             /*!<Response command index */
+
+/******************  Bit definition for SDMMC_RESP0 register  ******************/
+#define SDMMC_RESP0_CARDSTATUS0_Pos      (0U)
+#define SDMMC_RESP0_CARDSTATUS0_Msk      (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP0_CARDSTATUS0          SDMMC_RESP0_CARDSTATUS0_Msk           /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP1 register  ******************/
+#define SDMMC_RESP1_CARDSTATUS1_Pos      (0U)
+#define SDMMC_RESP1_CARDSTATUS1_Msk      (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP1_CARDSTATUS1          SDMMC_RESP1_CARDSTATUS1_Msk           /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP2 register  ******************/
+#define SDMMC_RESP2_CARDSTATUS2_Pos      (0U)
+#define SDMMC_RESP2_CARDSTATUS2_Msk      (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP2_CARDSTATUS2          SDMMC_RESP2_CARDSTATUS2_Msk           /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP3 register  ******************/
+#define SDMMC_RESP3_CARDSTATUS3_Pos      (0U)
+#define SDMMC_RESP3_CARDSTATUS3_Msk      (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP3_CARDSTATUS3          SDMMC_RESP3_CARDSTATUS3_Msk           /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP4 register  ******************/
+#define SDMMC_RESP4_CARDSTATUS4_Pos      (0U)
+#define SDMMC_RESP4_CARDSTATUS4_Msk      (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP4_CARDSTATUS4          SDMMC_RESP4_CARDSTATUS4_Msk           /*!<Card Status */
+
+/******************  Bit definition for SDMMC_DTIMER register  *****************/
+#define SDMMC_DTIMER_DATATIME_Pos        (0U)
+#define SDMMC_DTIMER_DATATIME_Msk        (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_DTIMER_DATATIME            SDMMC_DTIMER_DATATIME_Msk             /*!<Data timeout period. */
+
+/******************  Bit definition for SDMMC_DLEN register  *******************/
+#define SDMMC_DLEN_DATALENGTH_Pos        (0U)
+#define SDMMC_DLEN_DATALENGTH_Msk        (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_DLEN_DATALENGTH            SDMMC_DLEN_DATALENGTH_Msk             /*!<Data length value    */
+
+/******************  Bit definition for SDMMC_DCTRL register  ******************/
+#define SDMMC_DCTRL_DTEN_Pos             (0U)
+#define SDMMC_DCTRL_DTEN_Msk             (0x1UL << SDMMC_DCTRL_DTEN_Pos)       /*!< 0x00000001 */
+#define SDMMC_DCTRL_DTEN                 SDMMC_DCTRL_DTEN_Msk                  /*!<Data transfer enabled bit                */
+#define SDMMC_DCTRL_DTDIR_Pos            (1U)
+#define SDMMC_DCTRL_DTDIR_Msk            (0x1UL << SDMMC_DCTRL_DTDIR_Pos)      /*!< 0x00000002 */
+#define SDMMC_DCTRL_DTDIR                SDMMC_DCTRL_DTDIR_Msk                 /*!<Data transfer direction selection        */
+#define SDMMC_DCTRL_DTMODE_Pos           (2U)
+#define SDMMC_DCTRL_DTMODE_Msk           (0x3UL << SDMMC_DCTRL_DTMODE_Pos)     /*!< 0x0000000C */
+#define SDMMC_DCTRL_DTMODE               SDMMC_DCTRL_DTMODE_Msk                /*!<DTMODE[1:0] Data transfer mode selection */
+#define SDMMC_DCTRL_DTMODE_0             (0x1UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000004 */
+#define SDMMC_DCTRL_DTMODE_1             (0x2UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000008 */
+
+#define SDMMC_DCTRL_DBLOCKSIZE_Pos       (4U)
+#define SDMMC_DCTRL_DBLOCKSIZE_Msk       (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
+#define SDMMC_DCTRL_DBLOCKSIZE           SDMMC_DCTRL_DBLOCKSIZE_Msk            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDMMC_DCTRL_DBLOCKSIZE_0         (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000010 */
+#define SDMMC_DCTRL_DBLOCKSIZE_1         (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000020 */
+#define SDMMC_DCTRL_DBLOCKSIZE_2         (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000040 */
+#define SDMMC_DCTRL_DBLOCKSIZE_3         (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000080 */
+
+#define SDMMC_DCTRL_RWSTART_Pos          (8U)
+#define SDMMC_DCTRL_RWSTART_Msk          (0x1UL << SDMMC_DCTRL_RWSTART_Pos)    /*!< 0x00000100 */
+#define SDMMC_DCTRL_RWSTART              SDMMC_DCTRL_RWSTART_Msk               /*!<Read wait start                                 */
+#define SDMMC_DCTRL_RWSTOP_Pos           (9U)
+#define SDMMC_DCTRL_RWSTOP_Msk           (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)     /*!< 0x00000200 */
+#define SDMMC_DCTRL_RWSTOP               SDMMC_DCTRL_RWSTOP_Msk                /*!<Read wait stop                                  */
+#define SDMMC_DCTRL_RWMOD_Pos            (10U)
+#define SDMMC_DCTRL_RWMOD_Msk            (0x1UL << SDMMC_DCTRL_RWMOD_Pos)      /*!< 0x00000400 */
+#define SDMMC_DCTRL_RWMOD                SDMMC_DCTRL_RWMOD_Msk                 /*!<Read wait mode                                  */
+#define SDMMC_DCTRL_SDIOEN_Pos           (11U)
+#define SDMMC_DCTRL_SDIOEN_Msk           (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)     /*!< 0x00000800 */
+#define SDMMC_DCTRL_SDIOEN               SDMMC_DCTRL_SDIOEN_Msk                /*!<SD I/O enable functions                         */
+#define SDMMC_DCTRL_BOOTACKEN_Pos        (12U)
+#define SDMMC_DCTRL_BOOTACKEN_Msk        (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos)  /*!< 0x00001000 */
+#define SDMMC_DCTRL_BOOTACKEN            SDMMC_DCTRL_BOOTACKEN_Msk             /*!<Enable the reception of the Boot Acknowledgment */
+#define SDMMC_DCTRL_FIFORST_Pos          (13U)
+#define SDMMC_DCTRL_FIFORST_Msk          (0x1UL << SDMMC_DCTRL_FIFORST_Pos)    /*!< 0x00002000 */
+#define SDMMC_DCTRL_FIFORST              SDMMC_DCTRL_FIFORST_Msk               /*!<FIFO reset                                      */
+
+/******************  Bit definition for SDMMC_DCOUNT register  *****************/
+#define SDMMC_DCOUNT_DATACOUNT_Pos       (0U)
+#define SDMMC_DCOUNT_DATACOUNT_Msk       (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_DCOUNT_DATACOUNT           SDMMC_DCOUNT_DATACOUNT_Msk            /*!<Data count value */
+
+/******************  Bit definition for SDMMC_STA register  ********************/
+#define SDMMC_STA_CCRCFAIL_Pos           (0U)
+#define SDMMC_STA_CCRCFAIL_Msk           (0x1UL << SDMMC_STA_CCRCFAIL_Pos)     /*!< 0x00000001 */
+#define SDMMC_STA_CCRCFAIL               SDMMC_STA_CCRCFAIL_Msk                /*!<Command response received (CRC check failed)  */
+#define SDMMC_STA_DCRCFAIL_Pos           (1U)
+#define SDMMC_STA_DCRCFAIL_Msk           (0x1UL << SDMMC_STA_DCRCFAIL_Pos)     /*!< 0x00000002 */
+#define SDMMC_STA_DCRCFAIL               SDMMC_STA_DCRCFAIL_Msk                /*!<Data block sent/received (CRC check failed)   */
+#define SDMMC_STA_CTIMEOUT_Pos           (2U)
+#define SDMMC_STA_CTIMEOUT_Msk           (0x1UL << SDMMC_STA_CTIMEOUT_Pos)     /*!< 0x00000004 */
+#define SDMMC_STA_CTIMEOUT               SDMMC_STA_CTIMEOUT_Msk                /*!<Command response timeout                      */
+#define SDMMC_STA_DTIMEOUT_Pos           (3U)
+#define SDMMC_STA_DTIMEOUT_Msk           (0x1UL << SDMMC_STA_DTIMEOUT_Pos)     /*!< 0x00000008 */
+#define SDMMC_STA_DTIMEOUT               SDMMC_STA_DTIMEOUT_Msk                /*!<Data timeout                                  */
+#define SDMMC_STA_TXUNDERR_Pos           (4U)
+#define SDMMC_STA_TXUNDERR_Msk           (0x1UL << SDMMC_STA_TXUNDERR_Pos)     /*!< 0x00000010 */
+#define SDMMC_STA_TXUNDERR               SDMMC_STA_TXUNDERR_Msk                /*!<Transmit FIFO underrun error                  */
+#define SDMMC_STA_RXOVERR_Pos            (5U)
+#define SDMMC_STA_RXOVERR_Msk            (0x1UL << SDMMC_STA_RXOVERR_Pos)      /*!< 0x00000020 */
+#define SDMMC_STA_RXOVERR                SDMMC_STA_RXOVERR_Msk                 /*!<Received FIFO overrun error                   */
+#define SDMMC_STA_CMDREND_Pos            (6U)
+#define SDMMC_STA_CMDREND_Msk            (0x1UL << SDMMC_STA_CMDREND_Pos)      /*!< 0x00000040 */
+#define SDMMC_STA_CMDREND                SDMMC_STA_CMDREND_Msk                 /*!<Command response received (CRC check passed)  */
+#define SDMMC_STA_CMDSENT_Pos            (7U)
+#define SDMMC_STA_CMDSENT_Msk            (0x1UL << SDMMC_STA_CMDSENT_Pos)      /*!< 0x00000080 */
+#define SDMMC_STA_CMDSENT                SDMMC_STA_CMDSENT_Msk                 /*!<Command sent (no response required)           */
+#define SDMMC_STA_DATAEND_Pos            (8U)
+#define SDMMC_STA_DATAEND_Msk            (0x1UL << SDMMC_STA_DATAEND_Pos)      /*!< 0x00000100 */
+#define SDMMC_STA_DATAEND                SDMMC_STA_DATAEND_Msk                 /*!<Data end (data counter, SDIDCOUNT, is zero)   */
+#define SDMMC_STA_DHOLD_Pos              (9U)
+#define SDMMC_STA_DHOLD_Msk              (0x1UL << SDMMC_STA_DHOLD_Pos)        /*!< 0x00000200 */
+#define SDMMC_STA_DHOLD                  SDMMC_STA_DHOLD_Msk                   /*!<Data transfer Hold                                                      */
+#define SDMMC_STA_DBCKEND_Pos            (10U)
+#define SDMMC_STA_DBCKEND_Msk            (0x1UL << SDMMC_STA_DBCKEND_Pos)      /*!< 0x00000400 */
+#define SDMMC_STA_DBCKEND                SDMMC_STA_DBCKEND_Msk                 /*!<Data block sent/received (CRC check passed)   */
+#define SDMMC_STA_DABORT_Pos             (11U)
+#define SDMMC_STA_DABORT_Msk             (0x1UL << SDMMC_STA_DABORT_Pos)       /*!< 0x00000800 */
+#define SDMMC_STA_DABORT                 SDMMC_STA_DABORT_Msk                  /*!<Data transfer aborted by CMD12                                          */
+#define SDMMC_STA_DPSMACT_Pos            (12U)
+#define SDMMC_STA_DPSMACT_Msk            (0x1UL << SDMMC_STA_DPSMACT_Pos)      /*!< 0x00001000 */
+#define SDMMC_STA_DPSMACT                SDMMC_STA_DPSMACT_Msk                 /*!<Data path state machine active                                       */
+#define SDMMC_STA_CPSMACT_Pos            (13U)
+#define SDMMC_STA_CPSMACT_Msk            (0x1UL << SDMMC_STA_CPSMACT_Pos)      /*!< 0x00002000 */
+#define SDMMC_STA_CPSMACT                SDMMC_STA_CPSMACT_Msk                 /*!<Command path state machine active                                          */
+#define SDMMC_STA_TXFIFOHE_Pos           (14U)
+#define SDMMC_STA_TXFIFOHE_Msk           (0x1UL << SDMMC_STA_TXFIFOHE_Pos)     /*!< 0x00004000 */
+#define SDMMC_STA_TXFIFOHE               SDMMC_STA_TXFIFOHE_Msk                /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDMMC_STA_RXFIFOHF_Pos           (15U)
+#define SDMMC_STA_RXFIFOHF_Msk           (0x1UL << SDMMC_STA_RXFIFOHF_Pos)     /*!< 0x00008000 */
+#define SDMMC_STA_RXFIFOHF               SDMMC_STA_RXFIFOHF_Msk                /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDMMC_STA_TXFIFOF_Pos            (16U)
+#define SDMMC_STA_TXFIFOF_Msk            (0x1UL << SDMMC_STA_TXFIFOF_Pos)      /*!< 0x00010000 */
+#define SDMMC_STA_TXFIFOF                SDMMC_STA_TXFIFOF_Msk                 /*!<Transmit FIFO full                            */
+#define SDMMC_STA_RXFIFOF_Pos            (17U)
+#define SDMMC_STA_RXFIFOF_Msk            (0x1UL << SDMMC_STA_RXFIFOF_Pos)      /*!< 0x00020000 */
+#define SDMMC_STA_RXFIFOF                SDMMC_STA_RXFIFOF_Msk                 /*!<Receive FIFO full                             */
+#define SDMMC_STA_TXFIFOE_Pos            (18U)
+#define SDMMC_STA_TXFIFOE_Msk            (0x1UL << SDMMC_STA_TXFIFOE_Pos)      /*!< 0x00040000 */
+#define SDMMC_STA_TXFIFOE                SDMMC_STA_TXFIFOE_Msk                 /*!<Transmit FIFO empty                           */
+#define SDMMC_STA_RXFIFOE_Pos            (19U)
+#define SDMMC_STA_RXFIFOE_Msk            (0x1UL << SDMMC_STA_RXFIFOE_Pos)      /*!< 0x00080000 */
+#define SDMMC_STA_RXFIFOE                SDMMC_STA_RXFIFOE_Msk                 /*!<Receive FIFO empty                            */
+#define SDMMC_STA_BUSYD0_Pos             (20U)
+#define SDMMC_STA_BUSYD0_Msk             (0x1UL << SDMMC_STA_BUSYD0_Pos)       /*!< 0x00100000 */
+#define SDMMC_STA_BUSYD0                 SDMMC_STA_BUSYD0_Msk                  /*!<Inverted value of SDMMC_D0 line (Busy)                                  */
+#define SDMMC_STA_BUSYD0END_Pos          (21U)
+#define SDMMC_STA_BUSYD0END_Msk          (0x1UL << SDMMC_STA_BUSYD0END_Pos)    /*!< 0x00200000 */
+#define SDMMC_STA_BUSYD0END              SDMMC_STA_BUSYD0END_Msk               /*!<End of SDMMC_D0 Busy following a CMD response detected                  */
+#define SDMMC_STA_SDIOIT_Pos             (22U)
+#define SDMMC_STA_SDIOIT_Msk             (0x1UL << SDMMC_STA_SDIOIT_Pos)       /*!< 0x00400000 */
+#define SDMMC_STA_SDIOIT                 SDMMC_STA_SDIOIT_Msk                  /*!<SDIO interrupt received                                                 */
+#define SDMMC_STA_ACKFAIL_Pos            (23U)
+#define SDMMC_STA_ACKFAIL_Msk            (0x1UL << SDMMC_STA_ACKFAIL_Pos)      /*!< 0x00800000 */
+#define SDMMC_STA_ACKFAIL                SDMMC_STA_ACKFAIL_Msk                 /*!<Boot Acknowledgment received (BootAck check fail)                       */
+#define SDMMC_STA_ACKTIMEOUT_Pos         (24U)
+#define SDMMC_STA_ACKTIMEOUT_Msk         (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos)   /*!< 0x01000000 */
+#define SDMMC_STA_ACKTIMEOUT             SDMMC_STA_ACKTIMEOUT_Msk              /*!<Boot Acknowledgment timeout                                             */
+#define SDMMC_STA_VSWEND_Pos             (25U)
+#define SDMMC_STA_VSWEND_Msk             (0x1UL << SDMMC_STA_VSWEND_Pos)       /*!< 0x02000000 */
+#define SDMMC_STA_VSWEND                 SDMMC_STA_VSWEND_Msk                  /*!<Voltage switch critical timing section completion                       */
+#define SDMMC_STA_CKSTOP_Pos             (26U)
+#define SDMMC_STA_CKSTOP_Msk             (0x1UL << SDMMC_STA_CKSTOP_Pos)       /*!< 0x04000000 */
+#define SDMMC_STA_CKSTOP                 SDMMC_STA_CKSTOP_Msk                  /*!<SDMMC_CK stopped in Voltage switch procedure                            */
+#define SDMMC_STA_IDMATE_Pos             (27U)
+#define SDMMC_STA_IDMATE_Msk             (0x1UL << SDMMC_STA_IDMATE_Pos)       /*!< 0x08000000 */
+#define SDMMC_STA_IDMATE                 SDMMC_STA_IDMATE_Msk                  /*!<IDMA transfer error                                                     */
+#define SDMMC_STA_IDMABTC_Pos            (28U)
+#define SDMMC_STA_IDMABTC_Msk            (0x1UL << SDMMC_STA_IDMABTC_Pos)      /*!< 0x10000000 */
+#define SDMMC_STA_IDMABTC                SDMMC_STA_IDMABTC_Msk                 /*!<IDMA buffer transfer complete                                           */
+
+/*******************  Bit definition for SDMMC_ICR register  *******************/
+#define SDMMC_ICR_CCRCFAILC_Pos          (0U)
+#define SDMMC_ICR_CCRCFAILC_Msk          (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)    /*!< 0x00000001 */
+#define SDMMC_ICR_CCRCFAILC              SDMMC_ICR_CCRCFAILC_Msk               /*!<CCRCFAIL flag clear bit */
+#define SDMMC_ICR_DCRCFAILC_Pos          (1U)
+#define SDMMC_ICR_DCRCFAILC_Msk          (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)    /*!< 0x00000002 */
+#define SDMMC_ICR_DCRCFAILC              SDMMC_ICR_DCRCFAILC_Msk               /*!<DCRCFAIL flag clear bit */
+#define SDMMC_ICR_CTIMEOUTC_Pos          (2U)
+#define SDMMC_ICR_CTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)    /*!< 0x00000004 */
+#define SDMMC_ICR_CTIMEOUTC              SDMMC_ICR_CTIMEOUTC_Msk               /*!<CTIMEOUT flag clear bit */
+#define SDMMC_ICR_DTIMEOUTC_Pos          (3U)
+#define SDMMC_ICR_DTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)    /*!< 0x00000008 */
+#define SDMMC_ICR_DTIMEOUTC              SDMMC_ICR_DTIMEOUTC_Msk               /*!<DTIMEOUT flag clear bit */
+#define SDMMC_ICR_TXUNDERRC_Pos          (4U)
+#define SDMMC_ICR_TXUNDERRC_Msk          (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)    /*!< 0x00000010 */
+#define SDMMC_ICR_TXUNDERRC              SDMMC_ICR_TXUNDERRC_Msk               /*!<TXUNDERR flag clear bit */
+#define SDMMC_ICR_RXOVERRC_Pos           (5U)
+#define SDMMC_ICR_RXOVERRC_Msk           (0x1UL << SDMMC_ICR_RXOVERRC_Pos)     /*!< 0x00000020 */
+#define SDMMC_ICR_RXOVERRC               SDMMC_ICR_RXOVERRC_Msk                /*!<RXOVERR flag clear bit  */
+#define SDMMC_ICR_CMDRENDC_Pos           (6U)
+#define SDMMC_ICR_CMDRENDC_Msk           (0x1UL << SDMMC_ICR_CMDRENDC_Pos)     /*!< 0x00000040 */
+#define SDMMC_ICR_CMDRENDC               SDMMC_ICR_CMDRENDC_Msk                /*!<CMDREND flag clear bit  */
+#define SDMMC_ICR_CMDSENTC_Pos           (7U)
+#define SDMMC_ICR_CMDSENTC_Msk           (0x1UL << SDMMC_ICR_CMDSENTC_Pos)     /*!< 0x00000080 */
+#define SDMMC_ICR_CMDSENTC               SDMMC_ICR_CMDSENTC_Msk                /*!<CMDSENT flag clear bit  */
+#define SDMMC_ICR_DATAENDC_Pos           (8U)
+#define SDMMC_ICR_DATAENDC_Msk           (0x1UL << SDMMC_ICR_DATAENDC_Pos)     /*!< 0x00000100 */
+#define SDMMC_ICR_DATAENDC               SDMMC_ICR_DATAENDC_Msk                /*!<DATAEND flag clear bit  */
+#define SDMMC_ICR_DHOLDC_Pos             (9U)
+#define SDMMC_ICR_DHOLDC_Msk             (0x1UL << SDMMC_ICR_DHOLDC_Pos)       /*!< 0x00000200 */
+#define SDMMC_ICR_DHOLDC                 SDMMC_ICR_DHOLDC_Msk                  /*!<DHOLD flag clear bit       */
+#define SDMMC_ICR_DBCKENDC_Pos           (10U)
+#define SDMMC_ICR_DBCKENDC_Msk           (0x1UL << SDMMC_ICR_DBCKENDC_Pos)     /*!< 0x00000400 */
+#define SDMMC_ICR_DBCKENDC               SDMMC_ICR_DBCKENDC_Msk                /*!<DBCKEND flag clear bit  */
+#define SDMMC_ICR_DABORTC_Pos            (11U)
+#define SDMMC_ICR_DABORTC_Msk            (0x1UL << SDMMC_ICR_DABORTC_Pos)      /*!< 0x00000800 */
+#define SDMMC_ICR_DABORTC                SDMMC_ICR_DABORTC_Msk                 /*!<DABORTC flag clear bit     */
+#define SDMMC_ICR_BUSYD0ENDC_Pos         (21U)
+#define SDMMC_ICR_BUSYD0ENDC_Msk         (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos)   /*!< 0x00200000 */
+#define SDMMC_ICR_BUSYD0ENDC             SDMMC_ICR_BUSYD0ENDC_Msk              /*!<BUSYD0ENDC flag clear bit  */
+#define SDMMC_ICR_SDIOITC_Pos            (22U)
+#define SDMMC_ICR_SDIOITC_Msk            (0x1UL << SDMMC_ICR_SDIOITC_Pos)      /*!< 0x00400000 */
+#define SDMMC_ICR_SDIOITC                SDMMC_ICR_SDIOITC_Msk                 /*!<SDIOIT flag clear bit      */
+#define SDMMC_ICR_ACKFAILC_Pos           (23U)
+#define SDMMC_ICR_ACKFAILC_Msk           (0x1UL << SDMMC_ICR_ACKFAILC_Pos)     /*!< 0x00800000 */
+#define SDMMC_ICR_ACKFAILC               SDMMC_ICR_ACKFAILC_Msk                /*!<ACKFAILC flag clear bit    */
+#define SDMMC_ICR_ACKTIMEOUTC_Pos        (24U)
+#define SDMMC_ICR_ACKTIMEOUTC_Msk        (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos)  /*!< 0x01000000 */
+#define SDMMC_ICR_ACKTIMEOUTC            SDMMC_ICR_ACKTIMEOUTC_Msk             /*!<ACKTIMEOUTC flag clear bit */
+#define SDMMC_ICR_VSWENDC_Pos            (25U)
+#define SDMMC_ICR_VSWENDC_Msk            (0x1UL << SDMMC_ICR_VSWENDC_Pos)      /*!< 0x02000000 */
+#define SDMMC_ICR_VSWENDC                SDMMC_ICR_VSWENDC_Msk                 /*!<VSWENDC flag clear bit     */
+#define SDMMC_ICR_CKSTOPC_Pos            (26U)
+#define SDMMC_ICR_CKSTOPC_Msk            (0x1UL << SDMMC_ICR_CKSTOPC_Pos)      /*!< 0x04000000 */
+#define SDMMC_ICR_CKSTOPC                SDMMC_ICR_CKSTOPC_Msk                 /*!<CKSTOPC flag clear bit     */
+#define SDMMC_ICR_IDMATEC_Pos            (27U)
+#define SDMMC_ICR_IDMATEC_Msk            (0x1UL << SDMMC_ICR_IDMATEC_Pos)      /*!< 0x08000000 */
+#define SDMMC_ICR_IDMATEC                SDMMC_ICR_IDMATEC_Msk                 /*!<IDMATEC flag clear bit     */
+#define SDMMC_ICR_IDMABTCC_Pos           (28U)
+#define SDMMC_ICR_IDMABTCC_Msk           (0x1UL << SDMMC_ICR_IDMABTCC_Pos)     /*!< 0x10000000 */
+#define SDMMC_ICR_IDMABTCC               SDMMC_ICR_IDMABTCC_Msk                /*!<IDMABTCC flag clear bit    */
+
+/******************  Bit definition for SDMMC_MASK register  *******************/
+#define SDMMC_MASK_CCRCFAILIE_Pos        (0U)
+#define SDMMC_MASK_CCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)  /*!< 0x00000001 */
+#define SDMMC_MASK_CCRCFAILIE            SDMMC_MASK_CCRCFAILIE_Msk             /*!<Command CRC Fail Interrupt Enable          */
+#define SDMMC_MASK_DCRCFAILIE_Pos        (1U)
+#define SDMMC_MASK_DCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)  /*!< 0x00000002 */
+#define SDMMC_MASK_DCRCFAILIE            SDMMC_MASK_DCRCFAILIE_Msk             /*!<Data CRC Fail Interrupt Enable             */
+#define SDMMC_MASK_CTIMEOUTIE_Pos        (2U)
+#define SDMMC_MASK_CTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)  /*!< 0x00000004 */
+#define SDMMC_MASK_CTIMEOUTIE            SDMMC_MASK_CTIMEOUTIE_Msk             /*!<Command TimeOut Interrupt Enable           */
+#define SDMMC_MASK_DTIMEOUTIE_Pos        (3U)
+#define SDMMC_MASK_DTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)  /*!< 0x00000008 */
+#define SDMMC_MASK_DTIMEOUTIE            SDMMC_MASK_DTIMEOUTIE_Msk             /*!<Data TimeOut Interrupt Enable              */
+#define SDMMC_MASK_TXUNDERRIE_Pos        (4U)
+#define SDMMC_MASK_TXUNDERRIE_Msk        (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)  /*!< 0x00000010 */
+#define SDMMC_MASK_TXUNDERRIE            SDMMC_MASK_TXUNDERRIE_Msk             /*!<Tx FIFO UnderRun Error Interrupt Enable    */
+#define SDMMC_MASK_RXOVERRIE_Pos         (5U)
+#define SDMMC_MASK_RXOVERRIE_Msk         (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)   /*!< 0x00000020 */
+#define SDMMC_MASK_RXOVERRIE             SDMMC_MASK_RXOVERRIE_Msk              /*!<Rx FIFO OverRun Error Interrupt Enable     */
+#define SDMMC_MASK_CMDRENDIE_Pos         (6U)
+#define SDMMC_MASK_CMDRENDIE_Msk         (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)   /*!< 0x00000040 */
+#define SDMMC_MASK_CMDRENDIE             SDMMC_MASK_CMDRENDIE_Msk              /*!<Command Response Received Interrupt Enable */
+#define SDMMC_MASK_CMDSENTIE_Pos         (7U)
+#define SDMMC_MASK_CMDSENTIE_Msk         (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)   /*!< 0x00000080 */
+#define SDMMC_MASK_CMDSENTIE             SDMMC_MASK_CMDSENTIE_Msk              /*!<Command Sent Interrupt Enable              */
+#define SDMMC_MASK_DATAENDIE_Pos         (8U)
+#define SDMMC_MASK_DATAENDIE_Msk         (0x1UL << SDMMC_MASK_DATAENDIE_Pos)   /*!< 0x00000100 */
+#define SDMMC_MASK_DATAENDIE             SDMMC_MASK_DATAENDIE_Msk              /*!<Data End Interrupt Enable                  */
+#define SDMMC_MASK_DHOLDIE_Pos           (9U)
+#define SDMMC_MASK_DHOLDIE_Msk           (0x1UL << SDMMC_MASK_DHOLDIE_Pos)     /*!< 0x00000200 */
+#define SDMMC_MASK_DHOLDIE               SDMMC_MASK_DHOLDIE_Msk                /*!<Data Hold Interrupt Enable                 */
+#define SDMMC_MASK_DBCKENDIE_Pos         (10U)
+#define SDMMC_MASK_DBCKENDIE_Msk         (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)   /*!< 0x00000400 */
+#define SDMMC_MASK_DBCKENDIE             SDMMC_MASK_DBCKENDIE_Msk              /*!<Data Block End Interrupt Enable            */
+#define SDMMC_MASK_DABORTIE_Pos          (11U)
+#define SDMMC_MASK_DABORTIE_Msk          (0x1UL << SDMMC_MASK_DABORTIE_Pos)    /*!< 0x00000800 */
+#define SDMMC_MASK_DABORTIE              SDMMC_MASK_DABORTIE_Msk               /*!<Data transfer aborted interrupt enable     */
+
+#define SDMMC_MASK_TXFIFOHEIE_Pos        (14U)
+#define SDMMC_MASK_TXFIFOHEIE_Msk        (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)  /*!< 0x00004000 */
+#define SDMMC_MASK_TXFIFOHEIE            SDMMC_MASK_TXFIFOHEIE_Msk             /*!<Tx FIFO Half Empty interrupt Enable        */
+#define SDMMC_MASK_RXFIFOHFIE_Pos        (15U)
+#define SDMMC_MASK_RXFIFOHFIE_Msk        (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)  /*!< 0x00008000 */
+#define SDMMC_MASK_RXFIFOHFIE            SDMMC_MASK_RXFIFOHFIE_Msk             /*!<Rx FIFO Half Full interrupt Enable         */
+
+#define SDMMC_MASK_RXFIFOFIE_Pos         (17U)
+#define SDMMC_MASK_RXFIFOFIE_Msk         (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)   /*!< 0x00020000 */
+#define SDMMC_MASK_RXFIFOFIE             SDMMC_MASK_RXFIFOFIE_Msk              /*!<Rx FIFO Full interrupt Enable              */
+#define SDMMC_MASK_TXFIFOEIE_Pos         (18U)
+#define SDMMC_MASK_TXFIFOEIE_Msk         (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)   /*!< 0x00040000 */
+#define SDMMC_MASK_TXFIFOEIE             SDMMC_MASK_TXFIFOEIE_Msk              /*!<Tx FIFO Empty interrupt Enable             */
+
+#define SDMMC_MASK_BUSYD0ENDIE_Pos       (21U)
+#define SDMMC_MASK_BUSYD0ENDIE_Msk       (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */
+#define SDMMC_MASK_BUSYD0ENDIE           SDMMC_MASK_BUSYD0ENDIE_Msk            /*!<BUSYD0ENDIE interrupt Enable */
+#define SDMMC_MASK_SDIOITIE_Pos           (22U)
+#define SDMMC_MASK_SDIOITIE_Msk           (0x1UL << SDMMC_MASK_SDIOITIE_Pos)     /*!< 0x00400000 */
+#define SDMMC_MASK_SDIOITIE               SDMMC_MASK_SDIOITIE_Msk                /*!<SDMMC Mode Interrupt Received interrupt Enable */
+#define SDMMC_MASK_ACKFAILIE_Pos         (23U)
+#define SDMMC_MASK_ACKFAILIE_Msk         (0x1UL << SDMMC_MASK_ACKFAILIE_Pos)   /*!< 0x00800000 */
+#define SDMMC_MASK_ACKFAILIE             SDMMC_MASK_ACKFAILIE_Msk              /*!<Acknowledgment Fail Interrupt Enable */
+#define SDMMC_MASK_ACKTIMEOUTIE_Pos      (24U)
+#define SDMMC_MASK_ACKTIMEOUTIE_Msk      (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */
+#define SDMMC_MASK_ACKTIMEOUTIE          SDMMC_MASK_ACKTIMEOUTIE_Msk           /*!<Acknowledgment timeout Interrupt Enable */
+#define SDMMC_MASK_VSWENDIE_Pos          (25U)
+#define SDMMC_MASK_VSWENDIE_Msk          (0x1UL << SDMMC_MASK_VSWENDIE_Pos)    /*!< 0x02000000 */
+#define SDMMC_MASK_VSWENDIE              SDMMC_MASK_VSWENDIE_Msk               /*!<Voltage switch critical timing section completion Interrupt Enable */
+#define SDMMC_MASK_CKSTOPIE_Pos          (26U)
+#define SDMMC_MASK_CKSTOPIE_Msk          (0x1UL << SDMMC_MASK_CKSTOPIE_Pos)    /*!< 0x04000000 */
+#define SDMMC_MASK_CKSTOPIE              SDMMC_MASK_CKSTOPIE_Msk               /*!<Voltage Switch clock stopped Interrupt Enable */
+#define SDMMC_MASK_IDMABTCIE_Pos         (28U)
+#define SDMMC_MASK_IDMABTCIE_Msk         (0x1UL << SDMMC_MASK_IDMABTCIE_Pos)   /*!< 0x10000000 */
+#define SDMMC_MASK_IDMABTCIE             SDMMC_MASK_IDMABTCIE_Msk              /*!<IDMA buffer transfer complete Interrupt Enable */
+
+/*****************  Bit definition for SDMMC_ACKTIME register  *****************/
+#define SDMMC_ACKTIME_ACKTIME_Pos        (0U)
+#define SDMMC_ACKTIME_ACKTIME_Msk        (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_ACKTIME_ACKTIME            SDMMC_ACKTIME_ACKTIME_Msk             /*!<Boot acknowledgment timeout period */
+
+/******************  Bit definition for SDMMC_FIFO register  *******************/
+#define SDMMC_FIFO_FIFODATA_Pos          (0U)
+#define SDMMC_FIFO_FIFODATA_Msk          (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_FIFO_FIFODATA              SDMMC_FIFO_FIFODATA_Msk               /*!<Receive and transmit FIFO data */
+
+/******************  Bit definition for SDMMC_IDMACTRL register ****************/
+#define SDMMC_IDMA_IDMAEN_Pos            (0U)
+#define SDMMC_IDMA_IDMAEN_Msk            (0x1UL << SDMMC_IDMA_IDMAEN_Pos)      /*!< 0x00000001 */
+#define SDMMC_IDMA_IDMAEN                SDMMC_IDMA_IDMAEN_Msk                 /*!< Enable the internal DMA of the SDMMC peripheral */
+#define SDMMC_IDMA_IDMABMODE_Pos         (1U)
+#define SDMMC_IDMA_IDMABMODE_Msk         (0x1UL << SDMMC_IDMA_IDMABMODE_Pos)   /*!< 0x00000002 */
+#define SDMMC_IDMA_IDMABMODE             SDMMC_IDMA_IDMABMODE_Msk              /*!< Enable double buffer mode for IDMA */
+#define SDMMC_IDMA_IDMABACT_Pos          (2U)
+#define SDMMC_IDMA_IDMABACT_Msk          (0x1UL << SDMMC_IDMA_IDMABACT_Pos)    /*!< 0x00000004 */
+#define SDMMC_IDMA_IDMABACT              SDMMC_IDMA_IDMABACT_Msk               /*!< Uses buffer 1 when double buffer mode is selected */
+
+/*****************  Bit definition for SDMMC_IDMABSIZE register  ***************/
+#define SDMMC_IDMABSIZE_IDMABNDT_Pos     (5U)
+#define SDMMC_IDMABSIZE_IDMABNDT_Msk     (0xFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos) /*!< 0x00001FE0 */
+#define SDMMC_IDMABSIZE_IDMABNDT         SDMMC_IDMABSIZE_IDMABNDT_Msk          /*!< Number of transfers per buffer */
+
+/*****************  Bit definition for SDMMC_IDMABASE0 register  ***************/
+#define SDMMC_IDMABASE0_IDMABASE0        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 0 memory base address */
+
+/*****************  Bit definition for SDMMC_IDMABASE1 register  ***************/
+#define SDMMC_IDMABASE1_IDMABASE1        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 1 memory base address */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Delay Block Interface (DLYB)                        */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for DLYB_CR register  ********************/
+#define DLYB_CR_DEN_Pos         (0U)
+#define DLYB_CR_DEN_Msk         (0x1UL << DLYB_CR_DEN_Pos)                     /*!< 0x00000001 */
+#define DLYB_CR_DEN             DLYB_CR_DEN_Msk                                /*!<Delay Block enable */
+#define DLYB_CR_SEN_Pos         (1U)
+#define DLYB_CR_SEN_Msk         (0x1UL << DLYB_CR_SEN_Pos)                     /*!< 0x00000002 */
+#define DLYB_CR_SEN             DLYB_CR_SEN_Msk                                /*!<Sampler length enable */
+
+
+/*******************  Bit definition for DLYB_CFGR register  ********************/
+#define DLYB_CFGR_SEL_Pos       (0U)
+#define DLYB_CFGR_SEL_Msk       (0xFUL << DLYB_CFGR_SEL_Pos)                   /*!< 0x0000000F */
+#define DLYB_CFGR_SEL           DLYB_CFGR_SEL_Msk                              /*!<Select the phase for the Output clock[3:0] */
+#define DLYB_CFGR_SEL_0         (0x1UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000001 */
+#define DLYB_CFGR_SEL_1         (0x2UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000002 */
+#define DLYB_CFGR_SEL_2         (0x3UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000003 */
+#define DLYB_CFGR_SEL_3         (0x8UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000008 */
+
+#define DLYB_CFGR_UNIT_Pos      (8U)
+#define DLYB_CFGR_UNIT_Msk      (0x7FUL << DLYB_CFGR_UNIT_Pos)                 /*!< 0x00007F00 */
+#define DLYB_CFGR_UNIT          DLYB_CFGR_UNIT_Msk                             /*!<Delay Defines the delay of a Unit delay cell[6:0] */
+#define DLYB_CFGR_UNIT_0        (0x01UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000100 */
+#define DLYB_CFGR_UNIT_1        (0x02UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000200 */
+#define DLYB_CFGR_UNIT_2        (0x04UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000400 */
+#define DLYB_CFGR_UNIT_3        (0x08UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000800 */
+#define DLYB_CFGR_UNIT_4        (0x10UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00001000 */
+#define DLYB_CFGR_UNIT_5        (0x20UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00002000 */
+#define DLYB_CFGR_UNIT_6        (0x40UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00004000 */
+
+#define DLYB_CFGR_LNG_Pos       (16U)
+#define DLYB_CFGR_LNG_Msk       (0xFFFUL << DLYB_CFGR_LNG_Pos)                 /*!< 0x0FFF0000 */
+#define DLYB_CFGR_LNG           DLYB_CFGR_LNG_Msk                              /*!<Delay line length value[11:0] */
+#define DLYB_CFGR_LNG_0         (0x001UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00010000 */
+#define DLYB_CFGR_LNG_1         (0x002UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00020000 */
+#define DLYB_CFGR_LNG_2         (0x004UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00040000 */
+#define DLYB_CFGR_LNG_3         (0x008UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00080000 */
+#define DLYB_CFGR_LNG_4         (0x010UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00100000 */
+#define DLYB_CFGR_LNG_5         (0x020UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00200000 */
+#define DLYB_CFGR_LNG_6         (0x040UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00400000 */
+#define DLYB_CFGR_LNG_7         (0x080UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00800000 */
+#define DLYB_CFGR_LNG_8         (0x100UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x01000000 */
+#define DLYB_CFGR_LNG_9         (0x200UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x02000000 */
+#define DLYB_CFGR_LNG_10        (0x400UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x04000000 */
+#define DLYB_CFGR_LNG_11        (0x800UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x08000000 */
+
+#define DLYB_CFGR_LNGF_Pos      (31U)
+#define DLYB_CFGR_LNGF_Msk      (0x1UL << DLYB_CFGR_LNGF_Pos)                  /*!< 0x80000000 */
+#define DLYB_CFGR_LNGF          DLYB_CFGR_LNGF_Msk                             /*!<Length valid flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                   Serial Peripheral Interface (SPI/I2S)                    */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define SPI_CR1_SPE_Pos             (0U)
+#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000001 */
+#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<Serial Peripheral Enable                         */
+#define SPI_CR1_MASRX_Pos           (8U)
+#define SPI_CR1_MASRX_Msk           (0x1UL << SPI_CR1_MASRX_Pos)               /*!< 0x00000100 */
+#define SPI_CR1_MASRX               SPI_CR1_MASRX_Msk                          /*!<Master automatic SUSP in Receive mode            */
+#define SPI_CR1_CSTART_Pos          (9U)
+#define SPI_CR1_CSTART_Msk          (0x1UL << SPI_CR1_CSTART_Pos)              /*!< 0x00000200 */
+#define SPI_CR1_CSTART              SPI_CR1_CSTART_Msk                         /*!<Master transfer start                            */
+#define SPI_CR1_CSUSP_Pos           (10U)
+#define SPI_CR1_CSUSP_Msk           (0x1UL << SPI_CR1_CSUSP_Pos)               /*!< 0x00000400 */
+#define SPI_CR1_CSUSP               SPI_CR1_CSUSP_Msk                          /*!<Master SUSPend request                           */
+#define SPI_CR1_HDDIR_Pos           (11U)
+#define SPI_CR1_HDDIR_Msk           (0x1UL << SPI_CR1_HDDIR_Pos)               /*!< 0x00000800 */
+#define SPI_CR1_HDDIR               SPI_CR1_HDDIR_Msk                          /*!<Rx/Tx direction at Half-duplex mode              */
+#define SPI_CR1_SSI_Pos             (12U)
+#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                 /*!< 0x00001000 */
+#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal SS signal input level                   */
+#define SPI_CR1_CRC33_17_Pos        (13U)
+#define SPI_CR1_CRC33_17_Msk        (0x1UL << SPI_CR1_CRC33_17_Pos)            /*!< 0x00002000 */
+#define SPI_CR1_CRC33_17             SPI_CR1_CRC33_17_Msk                      /*!<32-bit CRC polynomial configuration              */
+#define SPI_CR1_RCRCINI_Pos         (14U)
+#define SPI_CR1_RCRCINI_Msk         (0x1UL << SPI_CR1_RCRCINI_Pos)             /*!< 0x00004000 */
+#define SPI_CR1_RCRCINI             SPI_CR1_RCRCINI_Msk                        /*!<CRC init pattern control for receiver            */
+#define SPI_CR1_TCRCINI_Pos         (15U)
+#define SPI_CR1_TCRCINI_Msk         (0x1UL << SPI_CR1_TCRCINI_Pos)             /*!< 0x00008000 */
+#define SPI_CR1_TCRCINI             SPI_CR1_TCRCINI_Msk                        /*!<CRC init pattern control for transmitter         */
+#define SPI_CR1_IOLOCK_Pos          (16U)
+#define SPI_CR1_IOLOCK_Msk          (0x1UL << SPI_CR1_IOLOCK_Pos)              /*!< 0x00010000 */
+#define SPI_CR1_IOLOCK              SPI_CR1_IOLOCK_Msk                         /*!<Locking the AF configuration of associated IOs   */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define SPI_CR2_TSER_Pos            (16U)
+#define SPI_CR2_TSER_Msk            (0xFFFFUL << SPI_CR2_TSER_Pos)             /*!< 0xFFFF0000 */
+#define SPI_CR2_TSER                SPI_CR2_TSER_Msk                           /*!<Number of data transfer extension                */
+#define SPI_CR2_TSIZE_Pos           (0U)
+#define SPI_CR2_TSIZE_Msk           (0xFFFFUL << SPI_CR2_TSIZE_Pos)            /*!< 0x0000FFFF */
+#define SPI_CR2_TSIZE               SPI_CR2_TSIZE_Msk                          /*!<Number of data at current transfer               */
+
+/*******************  Bit definition for SPI_CFG1 register  ********************/
+#define SPI_CFG1_DSIZE_Pos          (0U)
+#define SPI_CFG1_DSIZE_Msk          (0x1FUL << SPI_CFG1_DSIZE_Pos)             /*!< 0x0000001F */
+#define SPI_CFG1_DSIZE              SPI_CFG1_DSIZE_Msk                         /*!<DSIZE[4:0]: Bits number in single SPI data frame */
+#define SPI_CFG1_DSIZE_0            (0x01UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000001 */
+#define SPI_CFG1_DSIZE_1            (0x02UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000002 */
+#define SPI_CFG1_DSIZE_2            (0x04UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000004 */
+#define SPI_CFG1_DSIZE_3            (0x08UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000008 */
+#define SPI_CFG1_DSIZE_4            (0x10UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000010 */
+
+#define SPI_CFG1_FTHLV_Pos          (5U)
+#define SPI_CFG1_FTHLV_Msk          (0xFUL << SPI_CFG1_FTHLV_Pos)              /*!< 0x000001E0 */
+#define SPI_CFG1_FTHLV              SPI_CFG1_FTHLV_Msk                         /*!<FTHVL [3:0]: FIFO threshold level*/
+#define SPI_CFG1_FTHLV_0            (0x1UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000020 */
+#define SPI_CFG1_FTHLV_1            (0x2UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000040 */
+#define SPI_CFG1_FTHLV_2            (0x4UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000080 */
+#define SPI_CFG1_FTHLV_3            (0x8UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000100 */
+
+#define SPI_CFG1_UDRCFG_Pos         (9U)
+#define SPI_CFG1_UDRCFG_Msk         (0x3UL << SPI_CFG1_UDRCFG_Pos)             /*!< 0x00000600 */
+#define SPI_CFG1_UDRCFG             SPI_CFG1_UDRCFG_Msk                        /*!<UDRCFG[1:0]: Behavior of transmitter at underrun */
+#define SPI_CFG1_UDRCFG_0           (0x1UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000200 */
+#define SPI_CFG1_UDRCFG_1           (0x2UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000400 */
+
+
+#define SPI_CFG1_UDRDET_Pos         (11U)
+#define SPI_CFG1_UDRDET_Msk         (0x3UL << SPI_CFG1_UDRDET_Pos)             /*!< 0x00001800 */
+#define SPI_CFG1_UDRDET             SPI_CFG1_UDRDET_Msk                        /*!<UDRDET[1:0]: Detection of underrun condition     */
+#define SPI_CFG1_UDRDET_0           (0x1UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00000800 */
+#define SPI_CFG1_UDRDET_1           (0x2UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00001000 */
+
+#define SPI_CFG1_RXDMAEN_Pos        (14U)
+#define SPI_CFG1_RXDMAEN_Msk        (0x1UL << SPI_CFG1_RXDMAEN_Pos)            /*!< 0x00004000 */
+#define SPI_CFG1_RXDMAEN            SPI_CFG1_RXDMAEN_Msk                       /*!<Rx DMA stream enable                */
+#define SPI_CFG1_TXDMAEN_Pos        (15U)
+#define SPI_CFG1_TXDMAEN_Msk        (0x1UL << SPI_CFG1_TXDMAEN_Pos)            /*!< 0x00008000 */
+#define SPI_CFG1_TXDMAEN            SPI_CFG1_TXDMAEN_Msk                       /*!<Tx DMA stream enable                */
+
+#define SPI_CFG1_CRCSIZE_Pos        (16U)
+#define SPI_CFG1_CRCSIZE_Msk        (0x1FUL << SPI_CFG1_CRCSIZE_Pos)           /*!< 0x001F0000 */
+#define SPI_CFG1_CRCSIZE            SPI_CFG1_CRCSIZE_Msk                       /*!<CRCSIZE [4:0]: Length of CRC frame*/
+#define SPI_CFG1_CRCSIZE_0          (0x01UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00010000 */
+#define SPI_CFG1_CRCSIZE_1          (0x02UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00020000 */
+#define SPI_CFG1_CRCSIZE_2          (0x04UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00040000 */
+#define SPI_CFG1_CRCSIZE_3          (0x08UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00080000 */
+#define SPI_CFG1_CRCSIZE_4          (0x10UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00100000 */
+
+#define SPI_CFG1_CRCEN_Pos          (22U)
+#define SPI_CFG1_CRCEN_Msk          (0x1UL << SPI_CFG1_CRCEN_Pos)              /*!< 0x00400000 */
+#define SPI_CFG1_CRCEN              SPI_CFG1_CRCEN_Msk                         /*!<Hardware CRC computation enable */
+
+#define SPI_CFG1_MBR_Pos            (28U)
+#define SPI_CFG1_MBR_Msk            (0x7UL << SPI_CFG1_MBR_Pos)                /*!< 0x70000000 */
+#define SPI_CFG1_MBR                SPI_CFG1_MBR_Msk                           /*!<Master baud rate                */
+#define SPI_CFG1_MBR_0              (0x1UL << SPI_CFG1_MBR_Pos)                 /*!< 0x10000000 */
+#define SPI_CFG1_MBR_1              (0x2UL << SPI_CFG1_MBR_Pos)                 /*!< 0x20000000 */
+#define SPI_CFG1_MBR_2              (0x4UL << SPI_CFG1_MBR_Pos)                 /*!< 0x40000000 */
+
+/*******************  Bit definition for SPI_CFG2 register  ********************/
+#define SPI_CFG2_MSSI_Pos           (0U)
+#define SPI_CFG2_MSSI_Msk           (0xFUL << SPI_CFG2_MSSI_Pos)               /*!< 0x0000000F */
+#define SPI_CFG2_MSSI               SPI_CFG2_MSSI_Msk                          /*!<Master SS Idleness */
+#define SPI_CFG2_MSSI_0             (0x1UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000001 */
+#define SPI_CFG2_MSSI_1             (0x2UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000002 */
+#define SPI_CFG2_MSSI_2             (0x4UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000004 */
+#define SPI_CFG2_MSSI_3             (0x8UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000008 */
+
+#define SPI_CFG2_MIDI_Pos           (4U)
+#define SPI_CFG2_MIDI_Msk           (0xFUL << SPI_CFG2_MIDI_Pos)               /*!< 0x000000F0 */
+#define SPI_CFG2_MIDI               SPI_CFG2_MIDI_Msk                          /*!<Master Inter-Data Idleness */
+#define SPI_CFG2_MIDI_0             (0x1UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000010 */
+#define SPI_CFG2_MIDI_1             (0x2UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000020 */
+#define SPI_CFG2_MIDI_2             (0x4UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000040 */
+#define SPI_CFG2_MIDI_3             (0x8UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000080 */
+
+#define SPI_CFG2_IOSWP_Pos          (15U)
+#define SPI_CFG2_IOSWP_Msk          (0x1UL << SPI_CFG2_IOSWP_Pos)              /*!< 0x00008000 */
+#define SPI_CFG2_IOSWP              SPI_CFG2_IOSWP_Msk                         /*!<Swap functionality of MISO and MOSI pins */
+
+#define SPI_CFG2_COMM_Pos           (17U)
+#define SPI_CFG2_COMM_Msk           (0x3UL << SPI_CFG2_COMM_Pos)               /*!< 0x00060000 */
+#define SPI_CFG2_COMM               SPI_CFG2_COMM_Msk                          /*!<COMM [1:0]: SPI Communication Mode*/
+#define SPI_CFG2_COMM_0             (0x1UL << SPI_CFG2_COMM_Pos)                /*!< 0x00020000 */
+#define SPI_CFG2_COMM_1             (0x2UL << SPI_CFG2_COMM_Pos)                /*!< 0x00040000 */
+
+#define SPI_CFG2_SP_Pos             (19U)
+#define SPI_CFG2_SP_Msk             (0x7UL << SPI_CFG2_SP_Pos)                 /*!< 0x00380000 */
+#define SPI_CFG2_SP                 SPI_CFG2_SP_Msk                            /*!<SP[2:0]: Serial Protocol */
+#define SPI_CFG2_SP_0               (0x1UL << SPI_CFG2_SP_Pos)                  /*!< 0x00080000 */
+#define SPI_CFG2_SP_1               (0x2UL << SPI_CFG2_SP_Pos)                  /*!< 0x00100000 */
+#define SPI_CFG2_SP_2               (0x4UL << SPI_CFG2_SP_Pos)                  /*!< 0x00200000 */
+
+#define SPI_CFG2_MASTER_Pos         (22U)
+#define SPI_CFG2_MASTER_Msk         (0x1UL << SPI_CFG2_MASTER_Pos)             /*!< 0x00400000 */
+#define SPI_CFG2_MASTER             SPI_CFG2_MASTER_Msk                        /*!<SPI Master           */
+#define SPI_CFG2_LSBFRST_Pos        (23U)
+#define SPI_CFG2_LSBFRST_Msk        (0x1UL << SPI_CFG2_LSBFRST_Pos)            /*!< 0x00800000 */
+#define SPI_CFG2_LSBFRST            SPI_CFG2_LSBFRST_Msk                       /*!<Data frame format               */
+#define SPI_CFG2_CPHA_Pos           (24U)
+#define SPI_CFG2_CPHA_Msk           (0x1UL << SPI_CFG2_CPHA_Pos)               /*!< 0x01000000 */
+#define SPI_CFG2_CPHA               SPI_CFG2_CPHA_Msk                          /*!<Clock Phase      */
+#define SPI_CFG2_CPOL_Pos           (25U)
+#define SPI_CFG2_CPOL_Msk           (0x1UL << SPI_CFG2_CPOL_Pos)               /*!< 0x02000000 */
+#define SPI_CFG2_CPOL               SPI_CFG2_CPOL_Msk                          /*!<Clock Polarity   */
+#define SPI_CFG2_SSM_Pos            (26U)
+#define SPI_CFG2_SSM_Msk            (0x1UL << SPI_CFG2_SSM_Pos)                /*!< 0x04000000 */
+#define SPI_CFG2_SSM                SPI_CFG2_SSM_Msk                           /*!<Software slave management */
+
+#define SPI_CFG2_SSIOP_Pos          (28U)
+#define SPI_CFG2_SSIOP_Msk          (0x1UL << SPI_CFG2_SSIOP_Pos)              /*!< 0x10000000 */
+#define SPI_CFG2_SSIOP              SPI_CFG2_SSIOP_Msk                         /*!<SS input/output polarity */
+#define SPI_CFG2_SSOE_Pos           (29U)
+#define SPI_CFG2_SSOE_Msk           (0x1UL << SPI_CFG2_SSOE_Pos)               /*!< 0x20000000 */
+#define SPI_CFG2_SSOE               SPI_CFG2_SSOE_Msk                          /*!<SS output enable */
+#define SPI_CFG2_SSOM_Pos           (30U)
+#define SPI_CFG2_SSOM_Msk           (0x1UL << SPI_CFG2_SSOM_Pos)               /*!< 0x40000000 */
+#define SPI_CFG2_SSOM               SPI_CFG2_SSOM_Msk                          /*!<SS output management in master mode */
+
+#define SPI_CFG2_AFCNTR_Pos         (31U)
+#define SPI_CFG2_AFCNTR_Msk         (0x1UL << SPI_CFG2_AFCNTR_Pos)             /*!< 0x80000000 */
+#define SPI_CFG2_AFCNTR             SPI_CFG2_AFCNTR_Msk                        /*!<Alternate function GPIOs control */
+
+/*******************  Bit definition for SPI_IER register  ********************/
+#define SPI_IER_RXPIE_Pos           (0U)
+#define SPI_IER_RXPIE_Msk           (0x1UL << SPI_IER_RXPIE_Pos)               /*!< 0x00000001 */
+#define SPI_IER_RXPIE               SPI_IER_RXPIE_Msk                          /*!<RXP Interrupt Enable            */
+#define SPI_IER_TXPIE_Pos           (1U)
+#define SPI_IER_TXPIE_Msk           (0x1UL << SPI_IER_TXPIE_Pos)               /*!< 0x00000002 */
+#define SPI_IER_TXPIE               SPI_IER_TXPIE_Msk                          /*!<TXP interrupt enable            */
+#define SPI_IER_DXPIE_Pos           (2U)
+#define SPI_IER_DXPIE_Msk           (0x1UL << SPI_IER_DXPIE_Pos)               /*!< 0x00000004 */
+#define SPI_IER_DXPIE               SPI_IER_DXPIE_Msk                          /*!<DXP interrupt enable            */
+#define SPI_IER_EOTIE_Pos           (3U)
+#define SPI_IER_EOTIE_Msk           (0x1UL << SPI_IER_EOTIE_Pos)               /*!< 0x00000008 */
+#define SPI_IER_EOTIE               SPI_IER_EOTIE_Msk                          /*!<EOT/SUSP/TXC interrupt enable   */
+#define SPI_IER_TXTFIE_Pos          (4U)
+#define SPI_IER_TXTFIE_Msk          (0x1UL << SPI_IER_TXTFIE_Pos)              /*!< 0x00000010 */
+#define SPI_IER_TXTFIE              SPI_IER_TXTFIE_Msk                         /*!<TXTF interrupt enable           */
+#define SPI_IER_UDRIE_Pos           (5U)
+#define SPI_IER_UDRIE_Msk           (0x1UL << SPI_IER_UDRIE_Pos)               /*!< 0x00000020 */
+#define SPI_IER_UDRIE               SPI_IER_UDRIE_Msk                          /*!<UDR interrupt enable            */
+#define SPI_IER_OVRIE_Pos           (6U)
+#define SPI_IER_OVRIE_Msk           (0x1UL << SPI_IER_OVRIE_Pos)               /*!< 0x00000040 */
+#define SPI_IER_OVRIE               SPI_IER_OVRIE_Msk                          /*!<OVR interrupt enable            */
+#define SPI_IER_CRCEIE_Pos          (7U)
+#define SPI_IER_CRCEIE_Msk          (0x1UL << SPI_IER_CRCEIE_Pos)               /*!< 0x00000080 */
+#define SPI_IER_CRCEIE              SPI_IER_CRCEIE_Msk                          /*!<CRCE interrupt enable           */
+#define SPI_IER_TIFREIE_Pos         (8U)
+#define SPI_IER_TIFREIE_Msk         (0x1UL << SPI_IER_TIFREIE_Pos)             /*!< 0x00000100 */
+#define SPI_IER_TIFREIE             SPI_IER_TIFREIE_Msk                        /*!<TI Frame Error interrupt enable */
+#define SPI_IER_MODFIE_Pos          (9U)
+#define SPI_IER_MODFIE_Msk          (0x1UL << SPI_IER_MODFIE_Pos)              /*!< 0x00000200 */
+#define SPI_IER_MODFIE              SPI_IER_MODFIE_Msk                         /*!<MODF interrupt enable           */
+#define SPI_IER_TSERFIE_Pos         (10U)
+#define SPI_IER_TSERFIE_Msk         (0x1UL << SPI_IER_TSERFIE_Pos)              /*!< 0x00000400 */
+#define SPI_IER_TSERFIE             SPI_IER_TSERFIE_Msk                        /*!<TSERF interrupt enable          */
+
+/*******************  Bit definition for SPI_SR register  ********************/
+#define SPI_SR_RXP_Pos              (0U)
+#define SPI_SR_RXP_Msk              (0x1UL << SPI_SR_RXP_Pos)                  /*!< 0x00000001 */
+#define SPI_SR_RXP                  SPI_SR_RXP_Msk                             /*!<Rx-Packet available             */
+#define SPI_SR_TXP_Pos              (1U)
+#define SPI_SR_TXP_Msk              (0x1UL << SPI_SR_TXP_Pos)                  /*!< 0x00000002 */
+#define SPI_SR_TXP                  SPI_SR_TXP_Msk                             /*!<Tx-Packet space available       */
+#define SPI_SR_DXP_Pos              (2U)
+#define SPI_SR_DXP_Msk              (0x1UL << SPI_SR_DXP_Pos)                  /*!< 0x00000004 */
+#define SPI_SR_DXP                  SPI_SR_DXP_Msk                             /*!<Duplex Packet available         */
+#define SPI_SR_EOT_Pos              (3U)
+#define SPI_SR_EOT_Msk              (0x1UL << SPI_SR_EOT_Pos)                  /*!< 0x00000008 */
+#define SPI_SR_EOT                  SPI_SR_EOT_Msk                             /*!<Duplex Packet available         */
+#define SPI_SR_TXTF_Pos             (4U)
+#define SPI_SR_TXTF_Msk             (0x1UL << SPI_SR_TXTF_Pos)                 /*!< 0x00000010 */
+#define SPI_SR_TXTF                 SPI_SR_TXTF_Msk                            /*!<Transmission Transfer Filled    */
+#define SPI_SR_UDR_Pos              (5U)
+#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                  /*!< 0x00000020 */
+#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<UDR at Slave transmission       */
+#define SPI_SR_OVR_Pos              (6U)
+#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                  /*!< 0x00000040 */
+#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Rx-Packet available             */
+#define SPI_SR_CRCE_Pos             (7U)
+#define SPI_SR_CRCE_Msk             (0x1UL << SPI_SR_CRCE_Pos)                 /*!< 0x00000080 */
+#define SPI_SR_CRCE                 SPI_SR_CRCE_Msk                            /*!<CRC Error Detected              */
+#define SPI_SR_TIFRE_Pos            (8U)
+#define SPI_SR_TIFRE_Msk            (0x1UL << SPI_SR_TIFRE_Pos)                /*!< 0x00000100 */
+#define SPI_SR_TIFRE                SPI_SR_TIFRE_Msk                           /*!<TI frame format error Detected  */
+#define SPI_SR_MODF_Pos             (9U)
+#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                 /*!< 0x00000200 */
+#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode Fault Detected             */
+#define SPI_SR_TSERF_Pos            (10U)
+#define SPI_SR_TSERF_Msk            (0x1UL << SPI_SR_TSERF_Pos)                /*!< 0x00000400 */
+#define SPI_SR_TSERF                SPI_SR_TSERF_Msk                           /*!<Number of SPI data to be transacted reloaded     */
+#define SPI_SR_SUSP_Pos             (11U)
+#define SPI_SR_SUSP_Msk             (0x1UL << SPI_SR_SUSP_Pos)                 /*!< 0x00000800 */
+#define SPI_SR_SUSP                 SPI_SR_SUSP_Msk                            /*!<SUSP is set by hardware  */
+#define SPI_SR_TXC_Pos              (12U)
+#define SPI_SR_TXC_Msk              (0x1UL << SPI_SR_TXC_Pos)                  /*!< 0x00001000 */
+#define SPI_SR_TXC                  SPI_SR_TXC_Msk                             /*!<TxFIFO transmission complete */
+#define SPI_SR_RXPLVL_Pos           (13U)
+#define SPI_SR_RXPLVL_Msk           (0x3UL << SPI_SR_RXPLVL_Pos)               /*!< 0x00006000 */
+#define SPI_SR_RXPLVL               SPI_SR_RXPLVL_Msk                          /*!<RxFIFO Packing Level                             */
+#define SPI_SR_RXPLVL_0             (0x1UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00002000 */
+#define SPI_SR_RXPLVL_1             (0x2UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00004000 */
+#define SPI_SR_RXWNE_Pos            (15U)
+#define SPI_SR_RXWNE_Msk            (0x1UL << SPI_SR_RXWNE_Pos)                /*!< 0x00008000 */
+#define SPI_SR_RXWNE                SPI_SR_RXWNE_Msk                           /*!<Rx FIFO Word Not Empty                           */
+#define SPI_SR_CTSIZE_Pos           (16U)
+#define SPI_SR_CTSIZE_Msk           (0xFFFFUL << SPI_SR_CTSIZE_Pos)            /*!< 0xFFFF0000 */
+#define SPI_SR_CTSIZE               SPI_SR_CTSIZE_Msk                          /*!<Number of data frames remaining in TSIZE         */
+
+/*******************  Bit definition for SPI_IFCR register  ********************/
+#define SPI_IFCR_EOTC_Pos           (3U)
+#define SPI_IFCR_EOTC_Msk           (0x1UL << SPI_IFCR_EOTC_Pos)               /*!< 0x00000008 */
+#define SPI_IFCR_EOTC               SPI_IFCR_EOTC_Msk                          /*!<End Of Transfer flag clear              */
+#define SPI_IFCR_TXTFC_Pos          (4U)
+#define SPI_IFCR_TXTFC_Msk          (0x1UL << SPI_IFCR_TXTFC_Pos)              /*!< 0x00000010 */
+#define SPI_IFCR_TXTFC              SPI_IFCR_TXTFC_Msk                         /*!<Transmission Transfer Filled flag clear */
+#define SPI_IFCR_UDRC_Pos           (5U)
+#define SPI_IFCR_UDRC_Msk           (0x1UL << SPI_IFCR_UDRC_Pos)               /*!< 0x00000020 */
+#define SPI_IFCR_UDRC               SPI_IFCR_UDRC_Msk                          /*!<Underrun flag clear                     */
+#define SPI_IFCR_OVRC_Pos           (6U)
+#define SPI_IFCR_OVRC_Msk           (0x1UL << SPI_IFCR_OVRC_Pos)               /*!< 0x00000040 */
+#define SPI_IFCR_OVRC               SPI_IFCR_OVRC_Msk                          /*!<Overrun flag clear                      */
+#define SPI_IFCR_CRCEC_Pos          (7U)
+#define SPI_IFCR_CRCEC_Msk          (0x1UL << SPI_IFCR_CRCEC_Pos)              /*!< 0x00000080 */
+#define SPI_IFCR_CRCEC              SPI_IFCR_CRCEC_Msk                         /*!<CRC Error flag clear                    */
+#define SPI_IFCR_TIFREC_Pos         (8U)
+#define SPI_IFCR_TIFREC_Msk         (0x1UL << SPI_IFCR_TIFREC_Pos)             /*!< 0x00000100 */
+#define SPI_IFCR_TIFREC             SPI_IFCR_TIFREC_Msk                        /*!<TI frame format error flag clear        */
+#define SPI_IFCR_MODFC_Pos          (9U)
+#define SPI_IFCR_MODFC_Msk          (0x1UL << SPI_IFCR_MODFC_Pos)              /*!< 0x00000200 */
+#define SPI_IFCR_MODFC              SPI_IFCR_MODFC_Msk                         /*!<Mode Fault flag clear                   */
+#define SPI_IFCR_TSERFC_Pos         (10U)
+#define SPI_IFCR_TSERFC_Msk         (0x1UL << SPI_IFCR_TSERFC_Pos)             /*!< 0x00000400 */
+#define SPI_IFCR_TSERFC             SPI_IFCR_TSERFC_Msk                        /*!<TSERFC flag clear                       */
+#define SPI_IFCR_SUSPC_Pos          (11U)
+#define SPI_IFCR_SUSPC_Msk          (0x1UL << SPI_IFCR_SUSPC_Pos)              /*!< 0x00000800 */
+#define SPI_IFCR_SUSPC              SPI_IFCR_SUSPC_Msk                         /*!<SUSPend flag clear                      */
+
+/*******************  Bit definition for SPI_TXDR register  ********************/
+#define SPI_TXDR_TXDR_Pos           (0U)
+#define SPI_TXDR_TXDR_Msk           (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos)        /*!< 0xFFFFFFFF */
+#define SPI_TXDR_TXDR               SPI_TXDR_TXDR_Msk                          /* Transmit Data Register */
+
+/*******************  Bit definition for SPI_RXDR register  ********************/
+#define SPI_RXDR_RXDR_Pos           (0U)
+#define SPI_RXDR_RXDR_Msk           (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos)        /*!< 0xFFFFFFFF */
+#define SPI_RXDR_RXDR               SPI_RXDR_RXDR_Msk                          /* Receive Data Register  */
+
+/*******************  Bit definition for SPI_CRCPOLY register  ********************/
+#define SPI_CRCPOLY_CRCPOLY_Pos     (0U)
+#define SPI_CRCPOLY_CRCPOLY_Msk     (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos)  /*!< 0xFFFFFFFF */
+#define SPI_CRCPOLY_CRCPOLY         SPI_CRCPOLY_CRCPOLY_Msk                    /* CRC Polynomial register  */
+
+/*******************  Bit definition for SPI_TXCRC register  ********************/
+#define SPI_TXCRC_TXCRC_Pos         (0U)
+#define SPI_TXCRC_TXCRC_Msk         (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos)      /*!< 0xFFFFFFFF */
+#define SPI_TXCRC_TXCRC             SPI_TXCRC_TXCRC_Msk                        /* CRCRegister for transmitter */
+
+/*******************  Bit definition for SPI_RXCRC register  ********************/
+#define SPI_RXCRC_RXCRC_Pos         (0U)
+#define SPI_RXCRC_RXCRC_Msk         (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos)      /*!< 0xFFFFFFFF */
+#define SPI_RXCRC_RXCRC             SPI_RXCRC_RXCRC_Msk                        /* CRCRegister for receiver */
+
+/*******************  Bit definition for SPI_UDRDR register  ********************/
+#define SPI_UDRDR_UDRDR_Pos         (0U)
+#define SPI_UDRDR_UDRDR_Msk         (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos)      /*!< 0xFFFFFFFF */
+#define SPI_UDRDR_UDRDR             SPI_UDRDR_UDRDR_Msk                        /* Data at slave underrun condition */
+
+/******************  Bit definition for SPI_I2SCFGR register  *****************/
+#define SPI_I2SCFGR_I2SMOD_Pos      (0U)
+#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)          /*!< 0x00000001 */
+#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
+#define SPI_I2SCFGR_I2SCFG_Pos      (1U)
+#define SPI_I2SCFGR_I2SCFG_Msk      (0x7UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x0000000E */
+#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[2:0] I2S configuration mode                */
+#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000002 */
+#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000004 */
+#define SPI_I2SCFGR_I2SCFG_2        (0x4UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000008 */
+#define SPI_I2SCFGR_I2SSTD_Pos      (4U)
+#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] I2S standard selection                */
+#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */
+#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)
+#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)         /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                         */
+#define SPI_I2SCFGR_DATLEN_Pos      (8U)
+#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000300 */
+#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] Data length to be transferred         */
+#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000100 */
+#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000200 */
+#define SPI_I2SCFGR_CHLEN_Pos       (10U)
+#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)           /*!< 0x00000400 */
+#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
+#define SPI_I2SCFGR_CKPOL_Pos       (11U)
+#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)           /*!< 0x00000800 */
+#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<Steady state clock polarity                       */
+#define SPI_I2SCFGR_FIXCH_Pos       (12U)
+#define SPI_I2SCFGR_FIXCH_Msk       (0x1UL << SPI_I2SCFGR_FIXCH_Pos)           /*!< 0x00001000 */
+#define SPI_I2SCFGR_FIXCH           SPI_I2SCFGR_FIXCH_Msk                      /*!<Fixed channel length in SLAVE                     */
+#define SPI_I2SCFGR_WSINV_Pos       (13U)
+#define SPI_I2SCFGR_WSINV_Msk       (0x1UL << SPI_I2SCFGR_WSINV_Pos)           /*!< 0x00002000 */
+#define SPI_I2SCFGR_WSINV           SPI_I2SCFGR_WSINV_Msk                      /*!<Word select inversion                             */
+#define SPI_I2SCFGR_DATFMT_Pos      (14U)
+#define SPI_I2SCFGR_DATFMT_Msk      (0x1UL << SPI_I2SCFGR_DATFMT_Pos)          /*!< 0x00004000 */
+#define SPI_I2SCFGR_DATFMT          SPI_I2SCFGR_DATFMT_Msk                     /*!<Data format                                       */
+#define SPI_I2SCFGR_I2SDIV_Pos      (16U)
+#define SPI_I2SCFGR_I2SDIV_Msk      (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos)         /*!< 0x00FF0000 */
+#define SPI_I2SCFGR_I2SDIV          SPI_I2SCFGR_I2SDIV_Msk                     /*!<I2S Linear prescaler */
+#define SPI_I2SCFGR_ODD_Pos         (24U)
+#define SPI_I2SCFGR_ODD_Msk         (0x1UL << SPI_I2SCFGR_ODD_Pos)             /*!< 0x01000000 */
+#define SPI_I2SCFGR_ODD             SPI_I2SCFGR_ODD_Msk                        /*!<Odd factor for the prescaler */
+#define SPI_I2SCFGR_MCKOE_Pos       (25U)
+#define SPI_I2SCFGR_MCKOE_Msk       (0x1UL << SPI_I2SCFGR_MCKOE_Pos)           /*!< 0x02000000 */
+#define SPI_I2SCFGR_MCKOE           SPI_I2SCFGR_MCKOE_Msk                      /*!<Master Clock Output Enable */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    QUADSPI                                 */
+/*                                                                            */
+/******************************************************************************/
+/*****************  Bit definition for QUADSPI_CR register  *******************/
+#define QUADSPI_CR_EN_Pos                (0U)
+#define QUADSPI_CR_EN_Msk                (0x1UL << QUADSPI_CR_EN_Pos)          /*!< 0x00000001 */
+#define QUADSPI_CR_EN                    QUADSPI_CR_EN_Msk                     /*!< Enable */
+#define QUADSPI_CR_ABORT_Pos             (1U)
+#define QUADSPI_CR_ABORT_Msk             (0x1UL << QUADSPI_CR_ABORT_Pos)       /*!< 0x00000002 */
+#define QUADSPI_CR_ABORT                 QUADSPI_CR_ABORT_Msk                  /*!< Abort request */
+#define QUADSPI_CR_DMAEN_Pos             (2U)
+#define QUADSPI_CR_DMAEN_Msk             (0x1UL << QUADSPI_CR_DMAEN_Pos)       /*!< 0x00000004 */
+#define QUADSPI_CR_DMAEN                 QUADSPI_CR_DMAEN_Msk                  /*!< DMA Enable */
+#define QUADSPI_CR_TCEN_Pos              (3U)
+#define QUADSPI_CR_TCEN_Msk              (0x1UL << QUADSPI_CR_TCEN_Pos)        /*!< 0x00000008 */
+#define QUADSPI_CR_TCEN                  QUADSPI_CR_TCEN_Msk                   /*!< Timeout Counter Enable */
+#define QUADSPI_CR_SSHIFT_Pos            (4U)
+#define QUADSPI_CR_SSHIFT_Msk            (0x1UL << QUADSPI_CR_SSHIFT_Pos)      /*!< 0x00000010 */
+#define QUADSPI_CR_SSHIFT                QUADSPI_CR_SSHIFT_Msk                 /*!< SSHIFT Sample Shift */
+#define QUADSPI_CR_DFM_Pos               (6U)
+#define QUADSPI_CR_DFM_Msk               (0x1UL << QUADSPI_CR_DFM_Pos)         /*!< 0x00000040 */
+#define QUADSPI_CR_DFM                   QUADSPI_CR_DFM_Msk                    /*!< Dual Flash Mode */
+#define QUADSPI_CR_FSEL_Pos              (7U)
+#define QUADSPI_CR_FSEL_Msk              (0x1UL << QUADSPI_CR_FSEL_Pos)        /*!< 0x00000080 */
+#define QUADSPI_CR_FSEL                  QUADSPI_CR_FSEL_Msk                   /*!< Flash Select */
+#define QUADSPI_CR_FTHRES_Pos            (8U)
+#define QUADSPI_CR_FTHRES_Msk            (0xFUL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000F00 */
+#define QUADSPI_CR_FTHRES                QUADSPI_CR_FTHRES_Msk                 /*!< FTHRES[3:0] FIFO Level */
+#define QUADSPI_CR_FTHRES_0              (0x1UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000100 */
+#define QUADSPI_CR_FTHRES_1              (0x2UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000200 */
+#define QUADSPI_CR_FTHRES_2              (0x4UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000400 */
+#define QUADSPI_CR_FTHRES_3              (0x8UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000800 */
+#define QUADSPI_CR_TEIE_Pos              (16U)
+#define QUADSPI_CR_TEIE_Msk              (0x1UL << QUADSPI_CR_TEIE_Pos)        /*!< 0x00010000 */
+#define QUADSPI_CR_TEIE                  QUADSPI_CR_TEIE_Msk                   /*!< Transfer Error Interrupt Enable */
+#define QUADSPI_CR_TCIE_Pos              (17U)
+#define QUADSPI_CR_TCIE_Msk              (0x1UL << QUADSPI_CR_TCIE_Pos)        /*!< 0x00020000 */
+#define QUADSPI_CR_TCIE                  QUADSPI_CR_TCIE_Msk                   /*!< Transfer Complete Interrupt Enable */
+#define QUADSPI_CR_FTIE_Pos              (18U)
+#define QUADSPI_CR_FTIE_Msk              (0x1UL << QUADSPI_CR_FTIE_Pos)        /*!< 0x00040000 */
+#define QUADSPI_CR_FTIE                  QUADSPI_CR_FTIE_Msk                   /*!< FIFO Threshold Interrupt Enable */
+#define QUADSPI_CR_SMIE_Pos              (19U)
+#define QUADSPI_CR_SMIE_Msk              (0x1UL << QUADSPI_CR_SMIE_Pos)        /*!< 0x00080000 */
+#define QUADSPI_CR_SMIE                  QUADSPI_CR_SMIE_Msk                   /*!< Status Match Interrupt Enable */
+#define QUADSPI_CR_TOIE_Pos              (20U)
+#define QUADSPI_CR_TOIE_Msk              (0x1UL << QUADSPI_CR_TOIE_Pos)        /*!< 0x00100000 */
+#define QUADSPI_CR_TOIE                  QUADSPI_CR_TOIE_Msk                   /*!< TimeOut Interrupt Enable */
+#define QUADSPI_CR_APMS_Pos              (22U)
+#define QUADSPI_CR_APMS_Msk              (0x1UL << QUADSPI_CR_APMS_Pos)        /*!< 0x00400000 */
+#define QUADSPI_CR_APMS                  QUADSPI_CR_APMS_Msk                   /*!< Bit 1 */
+#define QUADSPI_CR_PMM_Pos               (23U)
+#define QUADSPI_CR_PMM_Msk               (0x1UL << QUADSPI_CR_PMM_Pos)         /*!< 0x00800000 */
+#define QUADSPI_CR_PMM                   QUADSPI_CR_PMM_Msk                    /*!< Polling Match Mode */
+#define QUADSPI_CR_PRESCALER_Pos         (24U)
+#define QUADSPI_CR_PRESCALER_Msk         (0xFFUL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0xFF000000 */
+#define QUADSPI_CR_PRESCALER             QUADSPI_CR_PRESCALER_Msk              /*!< PRESCALER[7:0] Clock prescaler */
+#define QUADSPI_CR_PRESCALER_0           (0x01UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x01000000 */
+#define QUADSPI_CR_PRESCALER_1           (0x02UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x02000000 */
+#define QUADSPI_CR_PRESCALER_2           (0x04UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x04000000 */
+#define QUADSPI_CR_PRESCALER_3           (0x08UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x08000000 */
+#define QUADSPI_CR_PRESCALER_4           (0x10UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x10000000 */
+#define QUADSPI_CR_PRESCALER_5           (0x20UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x20000000 */
+#define QUADSPI_CR_PRESCALER_6           (0x40UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x40000000 */
+#define QUADSPI_CR_PRESCALER_7           (0x80UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x80000000 */
+
+/*****************  Bit definition for QUADSPI_DCR register  ******************/
+#define QUADSPI_DCR_CKMODE_Pos           (0U)
+#define QUADSPI_DCR_CKMODE_Msk           (0x1UL << QUADSPI_DCR_CKMODE_Pos)     /*!< 0x00000001 */
+#define QUADSPI_DCR_CKMODE               QUADSPI_DCR_CKMODE_Msk                /*!< Mode 0 / Mode 3 */
+#define QUADSPI_DCR_CSHT_Pos             (8U)
+#define QUADSPI_DCR_CSHT_Msk             (0x7UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000700 */
+#define QUADSPI_DCR_CSHT                 QUADSPI_DCR_CSHT_Msk                  /*!< CSHT[2:0]: ChipSelect High Time */
+#define QUADSPI_DCR_CSHT_0               (0x1UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000100 */
+#define QUADSPI_DCR_CSHT_1               (0x2UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000200 */
+#define QUADSPI_DCR_CSHT_2               (0x4UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000400 */
+#define QUADSPI_DCR_FSIZE_Pos            (16U)
+#define QUADSPI_DCR_FSIZE_Msk            (0x1FUL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x001F0000 */
+#define QUADSPI_DCR_FSIZE                QUADSPI_DCR_FSIZE_Msk                 /*!< FSIZE[4:0]: Flash Size */
+#define QUADSPI_DCR_FSIZE_0              (0x01UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00010000 */
+#define QUADSPI_DCR_FSIZE_1              (0x02UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00020000 */
+#define QUADSPI_DCR_FSIZE_2              (0x04UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00040000 */
+#define QUADSPI_DCR_FSIZE_3              (0x08UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00080000 */
+#define QUADSPI_DCR_FSIZE_4              (0x10UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00100000 */
+
+/******************  Bit definition for QUADSPI_SR register  *******************/
+#define QUADSPI_SR_TEF_Pos               (0U)
+#define QUADSPI_SR_TEF_Msk               (0x1UL << QUADSPI_SR_TEF_Pos)         /*!< 0x00000001 */
+#define QUADSPI_SR_TEF                   QUADSPI_SR_TEF_Msk                    /*!< Transfer Error Flag */
+#define QUADSPI_SR_TCF_Pos               (1U)
+#define QUADSPI_SR_TCF_Msk               (0x1UL << QUADSPI_SR_TCF_Pos)         /*!< 0x00000002 */
+#define QUADSPI_SR_TCF                   QUADSPI_SR_TCF_Msk                    /*!< Transfer Complete Flag */
+#define QUADSPI_SR_FTF_Pos               (2U)
+#define QUADSPI_SR_FTF_Msk               (0x1UL << QUADSPI_SR_FTF_Pos)         /*!< 0x00000004 */
+#define QUADSPI_SR_FTF                   QUADSPI_SR_FTF_Msk                    /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_SMF_Pos               (3U)
+#define QUADSPI_SR_SMF_Msk               (0x1UL << QUADSPI_SR_SMF_Pos)         /*!< 0x00000008 */
+#define QUADSPI_SR_SMF                   QUADSPI_SR_SMF_Msk                    /*!< Status Match Flag */
+#define QUADSPI_SR_TOF_Pos               (4U)
+#define QUADSPI_SR_TOF_Msk               (0x1UL << QUADSPI_SR_TOF_Pos)         /*!< 0x00000010 */
+#define QUADSPI_SR_TOF                   QUADSPI_SR_TOF_Msk                    /*!< Timeout Flag */
+#define QUADSPI_SR_BUSY_Pos              (5U)
+#define QUADSPI_SR_BUSY_Msk              (0x1UL << QUADSPI_SR_BUSY_Pos)        /*!< 0x00000020 */
+#define QUADSPI_SR_BUSY                  QUADSPI_SR_BUSY_Msk                   /*!< Busy */
+#define QUADSPI_SR_FLEVEL_Pos            (8U)
+#define QUADSPI_SR_FLEVEL_Msk            (0x3FUL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00003F00 */
+#define QUADSPI_SR_FLEVEL                QUADSPI_SR_FLEVEL_Msk                 /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_FLEVEL_0              (0x01UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000100 */
+#define QUADSPI_SR_FLEVEL_1              (0x02UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000200 */
+#define QUADSPI_SR_FLEVEL_2              (0x04UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000400 */
+#define QUADSPI_SR_FLEVEL_3              (0x08UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000800 */
+#define QUADSPI_SR_FLEVEL_4              (0x10UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00001000 */
+#define QUADSPI_SR_FLEVEL_5              (0x20UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00002000 */
+
+/******************  Bit definition for QUADSPI_FCR register  ******************/
+#define QUADSPI_FCR_CTEF_Pos             (0U)
+#define QUADSPI_FCR_CTEF_Msk             (0x1UL << QUADSPI_FCR_CTEF_Pos)       /*!< 0x00000001 */
+#define QUADSPI_FCR_CTEF                 QUADSPI_FCR_CTEF_Msk                  /*!< Clear Transfer Error Flag */
+#define QUADSPI_FCR_CTCF_Pos             (1U)
+#define QUADSPI_FCR_CTCF_Msk             (0x1UL << QUADSPI_FCR_CTCF_Pos)       /*!< 0x00000002 */
+#define QUADSPI_FCR_CTCF                 QUADSPI_FCR_CTCF_Msk                  /*!< Clear Transfer Complete Flag */
+#define QUADSPI_FCR_CSMF_Pos             (3U)
+#define QUADSPI_FCR_CSMF_Msk             (0x1UL << QUADSPI_FCR_CSMF_Pos)       /*!< 0x00000008 */
+#define QUADSPI_FCR_CSMF                 QUADSPI_FCR_CSMF_Msk                  /*!< Clear Status Match Flag */
+#define QUADSPI_FCR_CTOF_Pos             (4U)
+#define QUADSPI_FCR_CTOF_Msk             (0x1UL << QUADSPI_FCR_CTOF_Pos)       /*!< 0x00000010 */
+#define QUADSPI_FCR_CTOF                 QUADSPI_FCR_CTOF_Msk                  /*!< Clear Timeout Flag */
+
+/******************  Bit definition for QUADSPI_DLR register  ******************/
+#define QUADSPI_DLR_DL_Pos               (0U)
+#define QUADSPI_DLR_DL_Msk               (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)  /*!< 0xFFFFFFFF */
+#define QUADSPI_DLR_DL                   QUADSPI_DLR_DL_Msk                    /*!< DL[31:0]: Data Length */
+
+/******************  Bit definition for QUADSPI_CCR register  ******************/
+#define QUADSPI_CCR_INSTRUCTION_Pos      (0U)
+#define QUADSPI_CCR_INSTRUCTION_Msk      (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
+#define QUADSPI_CCR_INSTRUCTION          QUADSPI_CCR_INSTRUCTION_Msk             /*!< INSTRUCTION[7:0]: Instruction */
+#define QUADSPI_CCR_INSTRUCTION_0        (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */
+#define QUADSPI_CCR_INSTRUCTION_1        (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */
+#define QUADSPI_CCR_INSTRUCTION_2        (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */
+#define QUADSPI_CCR_INSTRUCTION_3        (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */
+#define QUADSPI_CCR_INSTRUCTION_4        (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */
+#define QUADSPI_CCR_INSTRUCTION_5        (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */
+#define QUADSPI_CCR_INSTRUCTION_6        (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */
+#define QUADSPI_CCR_INSTRUCTION_7        (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */
+#define QUADSPI_CCR_IMODE_Pos            (8U)
+#define QUADSPI_CCR_IMODE_Msk            (0x3UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000300 */
+#define QUADSPI_CCR_IMODE                QUADSPI_CCR_IMODE_Msk                   /*!< IMODE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_IMODE_0              (0x1UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000100 */
+#define QUADSPI_CCR_IMODE_1              (0x2UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000200 */
+#define QUADSPI_CCR_ADMODE_Pos           (10U)
+#define QUADSPI_CCR_ADMODE_Msk           (0x3UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000C00 */
+#define QUADSPI_CCR_ADMODE               QUADSPI_CCR_ADMODE_Msk                  /*!< ADMODE[1:0]: Address Mode */
+#define QUADSPI_CCR_ADMODE_0             (0x1UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000400 */
+#define QUADSPI_CCR_ADMODE_1             (0x2UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000800 */
+#define QUADSPI_CCR_ADSIZE_Pos           (12U)
+#define QUADSPI_CCR_ADSIZE_Msk           (0x3UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00003000 */
+#define QUADSPI_CCR_ADSIZE               QUADSPI_CCR_ADSIZE_Msk                  /*!< ADSIZE[1:0]: Address Size */
+#define QUADSPI_CCR_ADSIZE_0             (0x1UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00001000 */
+#define QUADSPI_CCR_ADSIZE_1             (0x2UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00002000 */
+#define QUADSPI_CCR_ABMODE_Pos           (14U)
+#define QUADSPI_CCR_ABMODE_Msk           (0x3UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x0000C000 */
+#define QUADSPI_CCR_ABMODE               QUADSPI_CCR_ABMODE_Msk                  /*!< ABMODE[1:0]: Alternate Bytes Mode */
+#define QUADSPI_CCR_ABMODE_0             (0x1UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00004000 */
+#define QUADSPI_CCR_ABMODE_1             (0x2UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00008000 */
+#define QUADSPI_CCR_ABSIZE_Pos           (16U)
+#define QUADSPI_CCR_ABSIZE_Msk           (0x3UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00030000 */
+#define QUADSPI_CCR_ABSIZE               QUADSPI_CCR_ABSIZE_Msk                  /*!< ABSIZE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_ABSIZE_0             (0x1UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00010000 */
+#define QUADSPI_CCR_ABSIZE_1             (0x2UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00020000 */
+#define QUADSPI_CCR_DCYC_Pos             (18U)
+#define QUADSPI_CCR_DCYC_Msk             (0x1FUL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x007C0000 */
+#define QUADSPI_CCR_DCYC                 QUADSPI_CCR_DCYC_Msk                    /*!< DCYC[4:0]: Dummy Cycles */
+#define QUADSPI_CCR_DCYC_0               (0x01UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00040000 */
+#define QUADSPI_CCR_DCYC_1               (0x02UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00080000 */
+#define QUADSPI_CCR_DCYC_2               (0x04UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00100000 */
+#define QUADSPI_CCR_DCYC_3               (0x08UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00200000 */
+#define QUADSPI_CCR_DCYC_4               (0x10UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00400000 */
+#define QUADSPI_CCR_DMODE_Pos            (24U)
+#define QUADSPI_CCR_DMODE_Msk            (0x3UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x03000000 */
+#define QUADSPI_CCR_DMODE                QUADSPI_CCR_DMODE_Msk                   /*!< DMODE[1:0]: Data Mode */
+#define QUADSPI_CCR_DMODE_0              (0x1UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x01000000 */
+#define QUADSPI_CCR_DMODE_1              (0x2UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x02000000 */
+#define QUADSPI_CCR_FMODE_Pos            (26U)
+#define QUADSPI_CCR_FMODE_Msk            (0x3UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x0C000000 */
+#define QUADSPI_CCR_FMODE                QUADSPI_CCR_FMODE_Msk                   /*!< FMODE[1:0]: Functional Mode */
+#define QUADSPI_CCR_FMODE_0              (0x1UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x04000000 */
+#define QUADSPI_CCR_FMODE_1              (0x2UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x08000000 */
+#define QUADSPI_CCR_SIOO_Pos             (28U)
+#define QUADSPI_CCR_SIOO_Msk             (0x1UL << QUADSPI_CCR_SIOO_Pos)         /*!< 0x10000000 */
+#define QUADSPI_CCR_SIOO                 QUADSPI_CCR_SIOO_Msk                    /*!< SIOO: Send Instruction Only Once Mode */
+#define QUADSPI_CCR_DHHC_Pos             (30U)
+#define QUADSPI_CCR_DHHC_Msk             (0x1UL << QUADSPI_CCR_DHHC_Pos)         /*!< 0x40000000 */
+#define QUADSPI_CCR_DHHC                 QUADSPI_CCR_DHHC_Msk                    /*!< DHHC: DDR hold half cycle */
+#define QUADSPI_CCR_DDRM_Pos             (31U)
+#define QUADSPI_CCR_DDRM_Msk             (0x1UL << QUADSPI_CCR_DDRM_Pos)         /*!< 0x80000000 */
+#define QUADSPI_CCR_DDRM                 QUADSPI_CCR_DDRM_Msk                    /*!< DDRM: Double Data Rate Mode */
+
+/******************  Bit definition for QUADSPI_AR register  *******************/
+#define QUADSPI_AR_ADDRESS_Pos           (0U)
+#define QUADSPI_AR_ADDRESS_Msk           (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_AR_ADDRESS               QUADSPI_AR_ADDRESS_Msk                /*!< ADDRESS[31:0]: Address */
+
+/******************  Bit definition for QUADSPI_ABR register  ******************/
+#define QUADSPI_ABR_ALTERNATE_Pos        (0U)
+#define QUADSPI_ABR_ALTERNATE_Msk        (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_ABR_ALTERNATE            QUADSPI_ABR_ALTERNATE_Msk             /*!< ALTERNATE[31:0]: Alternate Bytes */
+
+/******************  Bit definition for QUADSPI_DR register  *******************/
+#define QUADSPI_DR_DATA_Pos              (0U)
+#define QUADSPI_DR_DATA_Msk              (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_DR_DATA                  QUADSPI_DR_DATA_Msk                   /*!< DATA[31:0]: Data */
+
+/******************  Bit definition for QUADSPI_PSMKR register  ****************/
+#define QUADSPI_PSMKR_MASK_Pos           (0U)
+#define QUADSPI_PSMKR_MASK_Msk           (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_PSMKR_MASK               QUADSPI_PSMKR_MASK_Msk                /*!< MASK[31:0]: Status Mask */
+
+/******************  Bit definition for QUADSPI_PSMAR register  ****************/
+#define QUADSPI_PSMAR_MATCH_Pos          (0U)
+#define QUADSPI_PSMAR_MATCH_Msk          (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_PSMAR_MATCH              QUADSPI_PSMAR_MATCH_Msk               /*!< MATCH[31:0]: Status Match */
+
+/******************  Bit definition for QUADSPI_PIR register  *****************/
+#define QUADSPI_PIR_INTERVAL_Pos         (0U)
+#define QUADSPI_PIR_INTERVAL_Msk         (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
+#define QUADSPI_PIR_INTERVAL             QUADSPI_PIR_INTERVAL_Msk              /*!< INTERVAL[15:0]: Polling Interval */
+
+/******************  Bit definition for QUADSPI_LPTR register  *****************/
+#define QUADSPI_LPTR_TIMEOUT_Pos         (0U)
+#define QUADSPI_LPTR_TIMEOUT_Msk         (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
+#define QUADSPI_LPTR_TIMEOUT             QUADSPI_LPTR_TIMEOUT_Msk              /*!< TIMEOUT[15:0]: Timeout period */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 SYSCFG                                     */
+/*                                                                            */
+/******************************************************************************/
+
+/******************  Bit definition for SYSCFG_PMCR register  ******************/
+#define SYSCFG_PMCR_I2C1_FMP_Pos        (0U)
+#define SYSCFG_PMCR_I2C1_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C1_FMP_Pos)    /*!< 0x00000001 */
+#define SYSCFG_PMCR_I2C1_FMP            SYSCFG_PMCR_I2C1_FMP_Msk               /*!< I2C1 Fast mode plus */
+#define SYSCFG_PMCR_I2C2_FMP_Pos        (1U)
+#define SYSCFG_PMCR_I2C2_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C2_FMP_Pos)    /*!< 0x00000002 */
+#define SYSCFG_PMCR_I2C2_FMP            SYSCFG_PMCR_I2C2_FMP_Msk               /*!< I2C2 Fast mode plus */
+#define SYSCFG_PMCR_I2C3_FMP_Pos        (2U)
+#define SYSCFG_PMCR_I2C3_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C3_FMP_Pos)    /*!< 0x00000004 */
+#define SYSCFG_PMCR_I2C3_FMP            SYSCFG_PMCR_I2C3_FMP_Msk               /*!< I2C3 Fast mode plus */
+#define SYSCFG_PMCR_I2C4_FMP_Pos        (3U)
+#define SYSCFG_PMCR_I2C4_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C4_FMP_Pos)    /*!< 0x00000008 */
+#define SYSCFG_PMCR_I2C4_FMP            SYSCFG_PMCR_I2C4_FMP_Msk               /*!< I2C4 Fast mode plus */
+#define SYSCFG_PMCR_I2C_PB6_FMP_Pos     (4U)
+#define SYSCFG_PMCR_I2C_PB6_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB6_FMP_Pos) /*!< 0x00000010 */
+#define SYSCFG_PMCR_I2C_PB6_FMP         SYSCFG_PMCR_I2C_PB6_FMP_Msk            /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_PMCR_I2C_PB7_FMP_Pos     (5U)
+#define SYSCFG_PMCR_I2C_PB7_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB7_FMP_Pos) /*!< 0x00000020 */
+#define SYSCFG_PMCR_I2C_PB7_FMP         SYSCFG_PMCR_I2C_PB7_FMP_Msk            /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_PMCR_I2C_PB8_FMP_Pos     (6U)
+#define SYSCFG_PMCR_I2C_PB8_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB8_FMP_Pos) /*!< 0x00000040 */
+#define SYSCFG_PMCR_I2C_PB8_FMP         SYSCFG_PMCR_I2C_PB8_FMP_Msk            /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_PMCR_I2C_PB9_FMP_Pos     (7U)
+#define SYSCFG_PMCR_I2C_PB9_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB9_FMP_Pos) /*!< 0x00000080 */
+#define SYSCFG_PMCR_I2C_PB9_FMP         SYSCFG_PMCR_I2C_PB9_FMP_Msk            /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_PMCR_BOOSTEN_Pos         (8U)
+#define SYSCFG_PMCR_BOOSTEN_Msk         (0x1UL << SYSCFG_PMCR_BOOSTEN_Pos)     /*!< 0x00000100 */
+#define SYSCFG_PMCR_BOOSTEN             SYSCFG_PMCR_BOOSTEN_Msk                /*!< I/O analog switch voltage booster enable */
+
+#define SYSCFG_PMCR_BOOSTVDDSEL_Pos     (9U)
+#define SYSCFG_PMCR_BOOSTVDDSEL_Msk     (0x1UL << SYSCFG_PMCR_BOOSTVDDSEL_Pos) /*!< 0x00000200 */
+#define SYSCFG_PMCR_BOOSTVDDSEL         SYSCFG_PMCR_BOOSTVDDSEL_Msk            /*!< Analog switch supply source selection : VDD/VDDA */
+
+#define SYSCFG_PMCR_EPIS_SEL_Pos        (21U)
+#define SYSCFG_PMCR_EPIS_SEL_Msk        (0x7UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00E00000 */
+#define SYSCFG_PMCR_EPIS_SEL            SYSCFG_PMCR_EPIS_SEL_Msk               /*!< Ethernet PHY Interface Selection */
+#define SYSCFG_PMCR_EPIS_SEL_0          (0x1UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00200000 */
+#define SYSCFG_PMCR_EPIS_SEL_1          (0x2UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00400000 */
+#define SYSCFG_PMCR_EPIS_SEL_2          (0x4UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00800000 */
+#define SYSCFG_PMCR_PA0SO_Pos           (24U)
+#define SYSCFG_PMCR_PA0SO_Msk           (0x1UL << SYSCFG_PMCR_PA0SO_Pos)       /*!< 0x01000000 */
+#define SYSCFG_PMCR_PA0SO               SYSCFG_PMCR_PA0SO_Msk                  /*!< PA0 Switch Open */
+#define SYSCFG_PMCR_PA1SO_Pos           (25U)
+#define SYSCFG_PMCR_PA1SO_Msk           (0x1UL << SYSCFG_PMCR_PA1SO_Pos)       /*!< 0x02000000 */
+#define SYSCFG_PMCR_PA1SO               SYSCFG_PMCR_PA1SO_Msk                  /*!< PA1 Switch Open */
+#define SYSCFG_PMCR_PC2SO_Pos           (26U)
+#define SYSCFG_PMCR_PC2SO_Msk           (0x1UL << SYSCFG_PMCR_PC2SO_Pos)       /*!< 0x04000000 */
+#define SYSCFG_PMCR_PC2SO               SYSCFG_PMCR_PC2SO_Msk                  /*!< PC2 Switch Open */
+#define SYSCFG_PMCR_PC3SO_Pos           (27U)
+#define SYSCFG_PMCR_PC3SO_Msk           (0x1UL << SYSCFG_PMCR_PC3SO_Pos)       /*!< 0x08000000 */
+#define SYSCFG_PMCR_PC3SO               SYSCFG_PMCR_PC3SO_Msk                  /*!< PC3 Switch Open */
+
+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)
+#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)    /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)
+#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)    /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)
+#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)    /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)
+#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)    /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */
+/**
+  * @brief   EXTI0 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000)                 /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001)                 /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002)                 /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003)                 /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004)                 /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x00000005)                 /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x00000006)                 /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000007)                 /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI         ((uint32_t)0x00000008)                 /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x00000009)                 /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x0000000A)                 /*!<PK[0] pin */
+
+/**
+  * @brief   EXTI1 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000)                 /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010)                 /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020)                 /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030)                 /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040)                 /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x00000050)                 /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x00000060)                 /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000070)                 /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI         ((uint32_t)0x00000080)                 /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x00000090)                 /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x000000A0)                 /*!<PK[1] pin */
+/**
+  * @brief   EXTI2 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000)                 /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100)                 /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200)                 /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300)                 /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400)                 /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x00000500)                 /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x00000600)                 /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x00000700)                 /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI         ((uint32_t)0x00000800)                 /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x00000900)                 /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x00000A00)                 /*!<PK[2] pin */
+
+/**
+  * @brief   EXTI3 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000)                 /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000)                 /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000)                 /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000)                 /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000)                 /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x00005000)                 /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x00006000)                 /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x00007000)                 /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI         ((uint32_t)0x00008000)                 /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x00009000)                 /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0x0000A000)                 /*!<PK[3] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
+#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)
+#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)    /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)
+#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)    /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)
+#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)    /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)
+#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)    /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */
+/**
+  * @brief   EXTI4 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000)                 /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001)                 /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002)                 /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003)                 /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004)                 /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x00000005)                 /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x00000006)                 /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x00000007)                 /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI         ((uint32_t)0x00000008)                 /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x00000009)                 /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x0000000A)                 /*!<PK[4] pin */
+/**
+  * @brief   EXTI5 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000)                 /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010)                 /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020)                 /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030)                 /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040)                 /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x00000050)                 /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x00000060)                 /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x00000070)                 /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI         ((uint32_t)0x00000080)                 /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x00000090)                 /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x000000A0)                 /*!<PK[5] pin */
+/**
+  * @brief   EXTI6 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000)                 /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100)                 /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200)                 /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300)                 /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400)                 /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x00000500)                 /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x00000600)                 /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x00000700)                 /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI         ((uint32_t)0x00000800)                 /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x00000900)                 /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x00000A00)                 /*!<PK[6] pin */
+
+/**
+  * @brief   EXTI7 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000)                 /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000)                 /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000)                 /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000)                 /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000)                 /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x00005000)                 /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x00006000)                 /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x00007000)                 /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI         ((uint32_t)0x00008000)                 /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x00009000)                 /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0x0000A000)                 /*!<PK[7] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
+#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)
+#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)    /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)
+#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)    /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)
+#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)   /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)
+#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)   /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */
+
+/**
+  * @brief   EXTI8 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000)                 /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001)                 /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002)                 /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003)                 /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004)                 /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x00000005)                 /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x00000006)                 /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x00000007)                 /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI         ((uint32_t)0x00000008)                 /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x00000009)                 /*!<PJ[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PK         ((uint32_t)0x0000000A)                 /*!<PK[8] pin */
+
+/**
+  * @brief   EXTI9 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000)                 /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010)                 /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020)                 /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030)                 /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040)                 /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x00000050)                 /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x00000060)                 /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x00000070)                 /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI         ((uint32_t)0x00000080)                 /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x00000090)                 /*!<PJ[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PK         ((uint32_t)0x000000A0)                 /*!<PK[9] pin */
+
+/**
+  * @brief   EXTI10 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000)                 /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100)                 /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200)                 /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300)                 /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400)                 /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x00000500)                 /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x00000600)                 /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x00000700)                 /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI        ((uint32_t)0x00000800)                 /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x00000900)                 /*!<PJ[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PK        ((uint32_t)0x00000A00)                 /*!<PK[10] pin */
+
+/**
+  * @brief   EXTI11 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000)                 /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000)                 /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000)                 /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000)                 /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000)                 /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x00005000)                 /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x00006000)                 /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x00007000)                 /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI        ((uint32_t)0x00008000)                 /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x00009000)                 /*!<PJ[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PK        ((uint32_t)0x0000A000)                 /*!<PK[11] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
+#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)
+#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)   /*!< 0x0000000F */
+#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)
+#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)   /*!< 0x000000F0 */
+#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)
+#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)   /*!< 0x00000F00 */
+#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)
+#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)   /*!< 0x0000F000 */
+#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */
+/**
+  * @brief   EXTI12 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000)                 /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001)                 /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002)                 /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003)                 /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004)                 /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x00000005)                 /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x00000006)                 /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x00000007)                 /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI        ((uint32_t)0x00000008)                 /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x00000009)                 /*!<PJ[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PK        ((uint32_t)0x0000000A)                 /*!<PK[12] pin */
+/**
+  * @brief   EXTI13 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000)                 /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010)                 /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020)                 /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030)                 /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040)                 /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x00000050)                 /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x00000060)                 /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x00000070)                 /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI        ((uint32_t)0x00000080)                 /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x00000090)                 /*!<PJ[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PK        ((uint32_t)0x000000A0)                 /*!<PK[13] pin */
+/**
+  * @brief   EXTI14 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000)                 /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100)                 /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200)                 /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300)                 /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400)                 /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x00000500)                 /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x00000600)                 /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x00000700)                 /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI        ((uint32_t)0x00000800)                 /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x00000900)                 /*!<PJ[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PK        ((uint32_t)0x00000A00)                 /*!<PK[14] pin */
+/**
+  * @brief   EXTI15 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000)                 /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000)                 /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000)                 /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000)                 /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000)                 /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x00005000)                 /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x00006000)                 /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x00007000)                 /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI        ((uint32_t)0x00008000)                 /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x00009000)                 /*!<PJ[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PK        ((uint32_t)0x0000A000)                 /*!<PK[15] pin */
+
+/******************  Bit definition for SYSCFG_CFGR register  ******************/
+#define SYSCFG_CFGR_PVDL_Pos            (2U)
+#define SYSCFG_CFGR_PVDL_Msk            (0x1UL << SYSCFG_CFGR_PVDL_Pos)        /*!< 0x00000004 */
+#define SYSCFG_CFGR_PVDL                SYSCFG_CFGR_PVDL_Msk                   /*!<PVD lock enable bit */
+#define SYSCFG_CFGR_FLASHL_Pos          (3U)
+#define SYSCFG_CFGR_FLASHL_Msk          (0x1UL << SYSCFG_CFGR_FLASHL_Pos)      /*!< 0x00000008 */
+#define SYSCFG_CFGR_FLASHL              SYSCFG_CFGR_FLASHL_Msk                 /*!<FLASH double ECC error lock bit */
+#define SYSCFG_CFGR_CM7L_Pos            (6U)
+#define SYSCFG_CFGR_CM7L_Msk            (0x1UL << SYSCFG_CFGR_CM7L_Pos)        /*!< 0x00000040 */
+#define SYSCFG_CFGR_CM7L                SYSCFG_CFGR_CM7L_Msk                   /*!<Cortex-M7 LOCKUP (Hardfault) output enable bit */
+#define SYSCFG_CFGR_BKRAML_Pos          (7U)
+#define SYSCFG_CFGR_BKRAML_Msk          (0x1UL << SYSCFG_CFGR_BKRAML_Pos)      /*!< 0x00000080 */
+#define SYSCFG_CFGR_BKRAML              SYSCFG_CFGR_BKRAML_Msk                 /*!<Backup SRAM double ECC error lock bit */
+#define SYSCFG_CFGR_SRAM4L_Pos          (9U)
+#define SYSCFG_CFGR_SRAM4L_Msk          (0x1UL << SYSCFG_CFGR_SRAM4L_Pos)      /*!< 0x00000200 */
+#define SYSCFG_CFGR_SRAM4L              SYSCFG_CFGR_SRAM4L_Msk                 /*!<SRAM4 double ECC error lock bit */
+#define SYSCFG_CFGR_SRAM3L_Pos          (10U)
+#define SYSCFG_CFGR_SRAM3L_Msk          (0x1UL << SYSCFG_CFGR_SRAM3L_Pos)      /*!< 0x00000400 */
+#define SYSCFG_CFGR_SRAM3L              SYSCFG_CFGR_SRAM3L_Msk                 /*!<SRAM3 double ECC error lock bit */
+#define SYSCFG_CFGR_SRAM2L_Pos          (11U)
+#define SYSCFG_CFGR_SRAM2L_Msk          (0x1UL << SYSCFG_CFGR_SRAM2L_Pos)      /*!< 0x00000800 */
+#define SYSCFG_CFGR_SRAM2L              SYSCFG_CFGR_SRAM2L_Msk                 /*!<SRAM2 double ECC error lock bit */
+#define SYSCFG_CFGR_SRAM1L_Pos          (12U)
+#define SYSCFG_CFGR_SRAM1L_Msk          (0x1UL << SYSCFG_CFGR_SRAM1L_Pos)      /*!< 0x00001000 */
+#define SYSCFG_CFGR_SRAM1L              SYSCFG_CFGR_SRAM1L_Msk                 /*!<SRAM1 double ECC error lock bit */
+#define SYSCFG_CFGR_DTCML_Pos           (13U)
+#define SYSCFG_CFGR_DTCML_Msk           (0x1UL << SYSCFG_CFGR_DTCML_Pos)       /*!< 0x00002000 */
+#define SYSCFG_CFGR_DTCML               SYSCFG_CFGR_DTCML_Msk                  /*!<DTCM double ECC error lock bit */
+#define SYSCFG_CFGR_ITCML_Pos           (14U)
+#define SYSCFG_CFGR_ITCML_Msk           (0x1UL << SYSCFG_CFGR_ITCML_Pos)       /*!< 0x00004000 */
+#define SYSCFG_CFGR_ITCML               SYSCFG_CFGR_ITCML_Msk                  /*!<ITCM double ECC error lock bit */
+#define SYSCFG_CFGR_AXISRAML_Pos        (15U)
+#define SYSCFG_CFGR_AXISRAML_Msk        (0x1UL << SYSCFG_CFGR_AXISRAML_Pos)    /*!< 0x00008000 */
+#define SYSCFG_CFGR_AXISRAML            SYSCFG_CFGR_AXISRAML_Msk               /*!<AXISRAM double ECC error lock bit */
+
+/******************  Bit definition for SYSCFG_CCCSR register  ******************/
+#define SYSCFG_CCCSR_EN_Pos             (0U)
+#define SYSCFG_CCCSR_EN_Msk             (0x1UL << SYSCFG_CCCSR_EN_Pos)         /*!< 0x00000001 */
+#define SYSCFG_CCCSR_EN                 SYSCFG_CCCSR_EN_Msk                    /*!< I/O compensation cell enable */
+#define SYSCFG_CCCSR_CS_Pos             (1U)
+#define SYSCFG_CCCSR_CS_Msk             (0x1UL << SYSCFG_CCCSR_CS_Pos)         /*!< 0x00000002 */
+#define SYSCFG_CCCSR_CS                 SYSCFG_CCCSR_CS_Msk                    /*!< I/O compensation cell code selection */
+#define SYSCFG_CCCSR_READY_Pos          (8U)
+#define SYSCFG_CCCSR_READY_Msk          (0x1UL << SYSCFG_CCCSR_READY_Pos)      /*!< 0x00000100 */
+#define SYSCFG_CCCSR_READY              SYSCFG_CCCSR_READY_Msk                 /*!< I/O compensation cell ready flag */
+#define SYSCFG_CCCSR_HSLV_Pos           (16U)
+#define SYSCFG_CCCSR_HSLV_Msk           (0x1UL << SYSCFG_CCCSR_HSLV_Pos)       /*!< 0x00010000 */
+#define SYSCFG_CCCSR_HSLV               SYSCFG_CCCSR_HSLV_Msk                  /*!< High-speed at low-voltage */
+
+/******************  Bit definition for SYSCFG_CCVR register  *******************/
+#define SYSCFG_CCVR_NCV_Pos             (0U)
+#define SYSCFG_CCVR_NCV_Msk             (0xFUL << SYSCFG_CCVR_NCV_Pos)         /*!< 0x0000000F */
+#define SYSCFG_CCVR_NCV                 SYSCFG_CCVR_NCV_Msk                    /*!< NMOS compensation value */
+#define SYSCFG_CCVR_PCV_Pos             (4U)
+#define SYSCFG_CCVR_PCV_Msk             (0xFUL << SYSCFG_CCVR_PCV_Pos)         /*!< 0x000000F0 */
+#define SYSCFG_CCVR_PCV                 SYSCFG_CCVR_PCV_Msk                    /*!< PMOS compensation value */
+
+/******************  Bit definition for SYSCFG_CCCR register  *******************/
+#define SYSCFG_CCCR_NCC_Pos             (0U)
+#define SYSCFG_CCCR_NCC_Msk             (0xFUL << SYSCFG_CCCR_NCC_Pos)         /*!< 0x0000000F */
+#define SYSCFG_CCCR_NCC                 SYSCFG_CCCR_NCC_Msk                    /*!< NMOS compensation code */
+#define SYSCFG_CCCR_PCC_Pos             (4U)
+#define SYSCFG_CCCR_PCC_Msk             (0xFUL << SYSCFG_CCCR_PCC_Pos)         /*!< 0x000000F0 */
+#define SYSCFG_CCCR_PCC                 SYSCFG_CCCR_PCC_Msk                    /*!< PMOS compensation code */
+/******************  Bit definition for SYSCFG_PWRCR register  *******************/
+#define SYSCFG_PWRCR_ODEN_Pos           (0U)
+#define SYSCFG_PWRCR_ODEN_Msk           (0x1UL << SYSCFG_PWRCR_ODEN_Pos)         /*!< 0x00000001 */
+#define SYSCFG_PWRCR_ODEN               SYSCFG_PWRCR_ODEN_Msk                    /*!< PWR overdrive enable */
+
+/******************  Bit definition for SYSCFG_PKGR register  *******************/
+#define SYSCFG_PKGR_PKG_Pos             (0U)
+#define SYSCFG_PKGR_PKG_Msk             (0xFUL << SYSCFG_PKGR_PKG_Pos)         /*!< 0x0000000F */
+#define SYSCFG_PKGR_PKG                 SYSCFG_PKGR_PKG_Msk                    /*!< Package type */
+
+/******************  Bit definition for SYSCFG_UR0 register  *******************/
+#define SYSCFG_UR0_BKS_Pos              (0U)
+#define SYSCFG_UR0_BKS_Msk              (0x1UL << SYSCFG_UR0_BKS_Pos)          /*!< 0x00000001 */
+#define SYSCFG_UR0_BKS                  SYSCFG_UR0_BKS_Msk                     /*!< Bank Swap */
+#define SYSCFG_UR0_RDP_Pos              (16U)
+#define SYSCFG_UR0_RDP_Msk              (0xFFUL << SYSCFG_UR0_RDP_Pos)         /*!< 0x00FF0000 */
+#define SYSCFG_UR0_RDP                  SYSCFG_UR0_RDP_Msk                     /*!< Readout protection */
+
+/******************  Bit definition for SYSCFG_UR2 register  *******************/
+#define SYSCFG_UR2_BORH_Pos             (0U)
+#define SYSCFG_UR2_BORH_Msk             (0x3UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000003 */
+#define SYSCFG_UR2_BORH                 SYSCFG_UR2_BORH_Msk                    /*!< Brown Out Reset High level */
+#define SYSCFG_UR2_BORH_0               (0x1UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000001 */
+#define SYSCFG_UR2_BORH_1               (0x2UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000002 */
+#define SYSCFG_UR2_BOOT_ADD0_Pos        (16U)
+#define SYSCFG_UR2_BOOT_ADD0_Msk        (0xFFFFUL << SYSCFG_UR2_BOOT_ADD0_Pos) /*!< 0xFFFF0000 */
+#define SYSCFG_UR2_BOOT_ADD0            SYSCFG_UR2_BOOT_ADD0_Msk               /*!< Core Boot Address 0 */
+/******************  Bit definition for SYSCFG_UR3 register  *******************/
+#define SYSCFG_UR3_BOOT_ADD1_Pos        (0U)
+#define SYSCFG_UR3_BOOT_ADD1_Msk        (0xFFFFUL << SYSCFG_UR3_BOOT_ADD1_Pos) /*!< 0x0000FFFF */
+#define SYSCFG_UR3_BOOT_ADD1            SYSCFG_UR3_BOOT_ADD1_Msk               /*!< Core Boot Address 1 */
+
+  /******************  Bit definition for SYSCFG_UR4 register  *******************/
+
+#define SYSCFG_UR4_MEPAD_BANK1_Pos      (16U)
+#define SYSCFG_UR4_MEPAD_BANK1_Msk      (0x1UL << SYSCFG_UR4_MEPAD_BANK1_Pos)  /*!< 0x00010000 */
+#define SYSCFG_UR4_MEPAD_BANK1          SYSCFG_UR4_MEPAD_BANK1_Msk             /*!< Mass Erase Protected Area Disabled for bank 1 */
+
+/******************  Bit definition for SYSCFG_UR5 register  *******************/
+#define SYSCFG_UR5_MESAD_BANK1_Pos      (0U)
+#define SYSCFG_UR5_MESAD_BANK1_Msk      (0x1UL << SYSCFG_UR5_MESAD_BANK1_Pos)  /*!< 0x00000001 */
+#define SYSCFG_UR5_MESAD_BANK1          SYSCFG_UR5_MESAD_BANK1_Msk             /*!< Mass erase secured area disabled for bank 1 */
+#define SYSCFG_UR5_WRPN_BANK1_Pos       (16U)
+#define SYSCFG_UR5_WRPN_BANK1_Msk       (0xFFUL << SYSCFG_UR5_WRPN_BANK1_Pos)  /*!< 0x00FF0000 */
+#define SYSCFG_UR5_WRPN_BANK1           SYSCFG_UR5_WRPN_BANK1_Msk              /*!< Write protection for flash bank 1 */
+
+/******************  Bit definition for SYSCFG_UR6 register  *******************/
+#define SYSCFG_UR6_PABEG_BANK1_Pos      (0U)
+#define SYSCFG_UR6_PABEG_BANK1_Msk      (0xFFFUL << SYSCFG_UR6_PABEG_BANK1_Pos) /*!< 0x00000FFF */
+#define SYSCFG_UR6_PABEG_BANK1          SYSCFG_UR6_PABEG_BANK1_Msk             /*!< Protected area start address for bank 1 */
+#define SYSCFG_UR6_PAEND_BANK1_Pos      (16U)
+#define SYSCFG_UR6_PAEND_BANK1_Msk      (0xFFFUL << SYSCFG_UR6_PAEND_BANK1_Pos) /*!< 0x0FFF0000 */
+#define SYSCFG_UR6_PAEND_BANK1          SYSCFG_UR6_PAEND_BANK1_Msk             /*!< Protected area end address for bank 1 */
+
+/******************  Bit definition for SYSCFG_UR7 register  *******************/
+#define SYSCFG_UR7_SABEG_BANK1_Pos      (0U)
+#define SYSCFG_UR7_SABEG_BANK1_Msk      (0xFFFUL << SYSCFG_UR7_SABEG_BANK1_Pos) /*!< 0x00000FFF */
+#define SYSCFG_UR7_SABEG_BANK1          SYSCFG_UR7_SABEG_BANK1_Msk             /*!< Secured area start address for bank 1 */
+#define SYSCFG_UR7_SAEND_BANK1_Pos      (16U)
+#define SYSCFG_UR7_SAEND_BANK1_Msk      (0xFFFUL << SYSCFG_UR7_SAEND_BANK1_Pos) /*!< 0x0FFF0000 */
+#define SYSCFG_UR7_SAEND_BANK1          SYSCFG_UR7_SAEND_BANK1_Msk             /*!< Secured area end address for bank 1 */
+
+/******************  Bit definition for SYSCFG_UR8 register  *******************/
+#define SYSCFG_UR8_MEPAD_BANK2_Pos      (0U)
+#define SYSCFG_UR8_MEPAD_BANK2_Msk      (0x1UL << SYSCFG_UR8_MEPAD_BANK2_Pos)  /*!< 0x00000001 */
+#define SYSCFG_UR8_MEPAD_BANK2          SYSCFG_UR8_MEPAD_BANK2_Msk             /*!< Mass erase Protected area disabled for bank 2 */
+#define SYSCFG_UR8_MESAD_BANK2_Pos      (16U)
+#define SYSCFG_UR8_MESAD_BANK2_Msk      (0x1UL << SYSCFG_UR8_MESAD_BANK2_Pos)  /*!< 0x00010000 */
+#define SYSCFG_UR8_MESAD_BANK2          SYSCFG_UR8_MESAD_BANK2_Msk             /*!< Mass Erase Secured Area Disabled for bank 2 */
+
+/******************  Bit definition for SYSCFG_UR9 register  *******************/
+#define SYSCFG_UR9_WRPN_BANK2_Pos       (0U)
+#define SYSCFG_UR9_WRPN_BANK2_Msk       (0xFFUL << SYSCFG_UR9_WRPN_BANK2_Pos)  /*!< 0x000000FF */
+#define SYSCFG_UR9_WRPN_BANK2           SYSCFG_UR9_WRPN_BANK2_Msk              /*!< Write protection for flash bank 2 */
+#define SYSCFG_UR9_PABEG_BANK2_Pos      (16U)
+#define SYSCFG_UR9_PABEG_BANK2_Msk      (0xFFFUL << SYSCFG_UR9_PABEG_BANK2_Pos) /*!< 0x0FFF0000 */
+#define SYSCFG_UR9_PABEG_BANK2          SYSCFG_UR9_PABEG_BANK2_Msk             /*!< Protected area start address for bank 2 */
+
+/******************  Bit definition for SYSCFG_UR10 register  *******************/
+#define SYSCFG_UR10_PAEND_BANK2_Pos     (0U)
+#define SYSCFG_UR10_PAEND_BANK2_Msk     (0xFFFUL << SYSCFG_UR10_PAEND_BANK2_Pos) /*!< 0x00000FFF */
+#define SYSCFG_UR10_PAEND_BANK2         SYSCFG_UR10_PAEND_BANK2_Msk            /*!< Protected area end address for bank 2 */
+#define SYSCFG_UR10_SABEG_BANK2_Pos     (16U)
+#define SYSCFG_UR10_SABEG_BANK2_Msk     (0xFFFUL << SYSCFG_UR10_SABEG_BANK2_Pos) /*!< 0x0FFF0000 */
+#define SYSCFG_UR10_SABEG_BANK2         SYSCFG_UR10_SABEG_BANK2_Msk            /*!< Secured area start address for bank 2 */
+
+/******************  Bit definition for SYSCFG_UR11 register  *******************/
+#define SYSCFG_UR11_SAEND_BANK2_Pos     (0U)
+#define SYSCFG_UR11_SAEND_BANK2_Msk     (0xFFFUL << SYSCFG_UR11_SAEND_BANK2_Pos) /*!< 0x00000FFF */
+#define SYSCFG_UR11_SAEND_BANK2         SYSCFG_UR11_SAEND_BANK2_Msk            /*!< Secured area end address for bank 2 */
+#define SYSCFG_UR11_IWDG1M_Pos          (16U)
+#define SYSCFG_UR11_IWDG1M_Msk          (0x1UL << SYSCFG_UR11_IWDG1M_Pos)      /*!< 0x00010000 */
+#define SYSCFG_UR11_IWDG1M              SYSCFG_UR11_IWDG1M_Msk                 /*!< Independent Watchdog 1 mode (SW or HW) */
+
+/******************  Bit definition for SYSCFG_UR12 register  *******************/
+
+#define SYSCFG_UR12_SECURE_Pos          (16U)
+#define SYSCFG_UR12_SECURE_Msk          (0x1UL << SYSCFG_UR12_SECURE_Pos)      /*!< 0x00010000 */
+#define SYSCFG_UR12_SECURE              SYSCFG_UR12_SECURE_Msk                 /*!< Secure mode status */
+
+/******************  Bit definition for SYSCFG_UR13 register  *******************/
+#define SYSCFG_UR13_SDRS_Pos            (0U)
+#define SYSCFG_UR13_SDRS_Msk            (0x3UL << SYSCFG_UR13_SDRS_Pos)        /*!< 0x00000003 */
+#define SYSCFG_UR13_SDRS                SYSCFG_UR13_SDRS_Msk                   /*!< Secured DTCM RAM Size */
+#define SYSCFG_UR13_D1SBRST_Pos         (16U)
+#define SYSCFG_UR13_D1SBRST_Msk         (0x1UL << SYSCFG_UR13_D1SBRST_Pos)     /*!< 0x00010000 */
+#define SYSCFG_UR13_D1SBRST             SYSCFG_UR13_D1SBRST_Msk                /*!< D1 Standby reset */
+
+/******************  Bit definition for SYSCFG_UR14 register  *******************/
+#define SYSCFG_UR14_D1STPRST_Pos        (0U)
+#define SYSCFG_UR14_D1STPRST_Msk        (0x1UL << SYSCFG_UR14_D1STPRST_Pos)    /*!< 0x00000001 */
+#define SYSCFG_UR14_D1STPRST            SYSCFG_UR14_D1STPRST_Msk               /*!< D1 Stop Reset */
+
+/******************  Bit definition for SYSCFG_UR15 register  *******************/
+#define SYSCFG_UR15_FZIWDGSTB_Pos       (16U)
+#define SYSCFG_UR15_FZIWDGSTB_Msk       (0x1UL << SYSCFG_UR15_FZIWDGSTB_Pos)   /*!< 0x00010000 */
+#define SYSCFG_UR15_FZIWDGSTB           SYSCFG_UR15_FZIWDGSTB_Msk              /*!< Freeze independent watchdogs in Standby mode */
+
+/******************  Bit definition for SYSCFG_UR16 register  *******************/
+#define SYSCFG_UR16_FZIWDGSTP_Pos       (0U)
+#define SYSCFG_UR16_FZIWDGSTP_Msk       (0x1UL << SYSCFG_UR16_FZIWDGSTP_Pos)   /*!< 0x00000001 */
+#define SYSCFG_UR16_FZIWDGSTP           SYSCFG_UR16_FZIWDGSTP_Msk              /*!< Freeze independent watchdogs in Stop mode */
+#define SYSCFG_UR16_PKP_Pos             (16U)
+#define SYSCFG_UR16_PKP_Msk             (0x1UL << SYSCFG_UR16_PKP_Pos)         /*!< 0x00010000 */
+#define SYSCFG_UR16_PKP                 SYSCFG_UR16_PKP_Msk                    /*!< Private key programmed */
+
+/******************  Bit definition for SYSCFG_UR17 register  *******************/
+#define SYSCFG_UR17_IOHSLV_Pos          (0U)
+#define SYSCFG_UR17_IOHSLV_Msk          (0x1UL << SYSCFG_UR17_IOHSLV_Pos)      /*!< 0x00000001 */
+#define SYSCFG_UR17_IOHSLV              SYSCFG_UR17_IOHSLV_Msk                 /*!< I/O high speed / low voltage */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    TIM                                     */
+/*                                                                            */
+/******************************************************************************/
+#define TIM_BREAK_INPUT_SUPPORT             /*!<TIM Break input feature */
+
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define TIM_CR1_CEN_Pos           (0U)
+#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */
+#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos          (1U)
+#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */
+#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
+#define TIM_CR1_URS_Pos           (2U)
+#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */
+#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
+#define TIM_CR1_OPM_Pos           (3U)
+#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */
+#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos           (4U)
+#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */
+#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
+
+#define TIM_CR1_CMS_Pos           (5U)
+#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */
+#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
+#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos          (7U)
+#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */
+#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos           (8U)
+#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */
+#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
+#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
+
+#define TIM_CR1_UIFREMAP_Pos      (11U)
+#define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */
+#define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define TIM_CR2_CCPC_Pos          (0U)
+#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */
+#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos          (2U)
+#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */
+#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos          (3U)
+#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */
+#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos           (4U)
+#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000070 */
+#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
+#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
+#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos          (7U)
+#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */
+#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos          (8U)
+#define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */
+#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos         (9U)
+#define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */
+#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos          (10U)
+#define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */
+#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos         (11U)
+#define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */
+#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos          (12U)
+#define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */
+#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos         (13U)
+#define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */
+#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos          (14U)
+#define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */
+#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
+#define TIM_CR2_OIS5_Pos          (16U)
+#define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
+#define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */
+#define TIM_CR2_OIS6_Pos          (17U)
+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00020000 */
+#define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */
+
+#define TIM_CR2_MMS2_Pos          (20U)
+#define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */
+#define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00100000 */
+#define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00200000 */
+#define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00400000 */
+#define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00800000 */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define TIM_SMCR_SMS_Pos          (0U)
+#define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */
+#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000004 */
+#define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)               /*!< 0x00010000 */
+
+#define TIM_SMCR_TS_Pos           (4U)
+#define TIM_SMCR_TS_Msk           (0x30007UL << TIM_SMCR_TS_Pos)               /*!< 0x00300070 */
+#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[4:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0             (0x00001UL << TIM_SMCR_TS_Pos)                /*!< 0x00000010 */
+#define TIM_SMCR_TS_1             (0x00002UL << TIM_SMCR_TS_Pos)                /*!< 0x00000020 */
+#define TIM_SMCR_TS_2             (0x00004UL << TIM_SMCR_TS_Pos)                /*!< 0x00000040 */
+#define TIM_SMCR_TS_3             (0x10000UL << TIM_SMCR_TS_Pos)                /*!< 0x00100000 */
+#define TIM_SMCR_TS_4             (0x20000UL << TIM_SMCR_TS_Pos)                /*!< 0x00200000 */
+
+#define TIM_SMCR_MSM_Pos          (7U)
+#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */
+#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos          (8U)
+#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */
+#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos         (12U)
+#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */
+#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos          (14U)
+#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */
+#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos          (15U)
+#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */
+#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define TIM_DIER_UIE_Pos          (0U)
+#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */
+#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos        (1U)
+#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */
+#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos        (2U)
+#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */
+#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos        (3U)
+#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */
+#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos        (4U)
+#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */
+#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos        (5U)
+#define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */
+#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos          (6U)
+#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */
+#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos          (7U)
+#define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */
+#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos          (8U)
+#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */
+#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos        (9U)
+#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */
+#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos        (10U)
+#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */
+#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos        (11U)
+#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */
+#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos        (12U)
+#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */
+#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos        (13U)
+#define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */
+#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos          (14U)
+#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */
+#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define TIM_SR_UIF_Pos            (0U)
+#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */
+#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos          (1U)
+#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */
+#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos          (2U)
+#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */
+#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos          (3U)
+#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */
+#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos          (4U)
+#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */
+#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos          (5U)
+#define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */
+#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos            (6U)
+#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */
+#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos            (7U)
+#define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */
+#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
+#define TIM_SR_B2IF_Pos           (8U)
+#define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */
+#define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break2 interrupt Flag */
+#define TIM_SR_CC1OF_Pos          (9U)
+#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */
+#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos          (10U)
+#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */
+#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos          (11U)
+#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */
+#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos          (12U)
+#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */
+#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
+#define TIM_SR_CC5IF_Pos          (16U)
+#define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */
+#define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */
+#define TIM_SR_CC6IF_Pos          (17U)
+#define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */
+#define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */
+#define TIM_SR_SBIF_Pos           (13U)
+#define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */
+#define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!< System Break Flag */
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define TIM_EGR_UG_Pos            (0U)
+#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */
+#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos          (1U)
+#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */
+#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos          (2U)
+#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */
+#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos          (3U)
+#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */
+#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos          (4U)
+#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */
+#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos          (5U)
+#define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */
+#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos            (6U)
+#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */
+#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos            (7U)
+#define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */
+#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */
+#define TIM_EGR_B2G_Pos           (8U)
+#define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */
+#define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break Generation */
+
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define TIM_CCMR1_CC1S_Pos        (0U)
+#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos       (2U)
+#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos       (3U)
+#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos        (4U)
+#define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */
+#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000040 */
+#define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010000 */
+
+#define TIM_CCMR1_OC1CE_Pos       (7U)
+#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos        (8U)
+#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos       (10U)
+#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos       (11U)
+#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos        (12U)
+#define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */
+#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00004000 */
+#define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x01000000 */
+
+#define TIM_CCMR1_OC2CE_Pos       (15U)
+#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos      (2U)
+#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos        (4U)
+#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos      (10U)
+#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos        (12U)
+#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define TIM_CCMR2_CC3S_Pos        (0U)
+#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos       (2U)
+#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos       (3U)
+#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos        (4U)
+#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
+#define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010000 */
+
+#define TIM_CCMR2_OC3CE_Pos       (7U)
+#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos        (8U)
+#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos       (10U)
+#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos       (11U)
+#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos        (12U)
+#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
+#define TIM_CCMR2_OC4M_3          (0x100UL << TIM_CCMR2_OC4M_Pos)               /*!< 0x00100000 */
+
+#define TIM_CCMR2_OC4CE_Pos       (15U)
+#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos      (2U)
+#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos        (4U)
+#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos      (10U)
+#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos        (12U)
+#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define TIM_CCER_CC1E_Pos         (0U)
+#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */
+#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos         (1U)
+#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */
+#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos        (2U)
+#define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */
+#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos        (3U)
+#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */
+#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos         (4U)
+#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */
+#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos         (5U)
+#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */
+#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos        (6U)
+#define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */
+#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos        (7U)
+#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */
+#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos         (8U)
+#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */
+#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos         (9U)
+#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */
+#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos        (10U)
+#define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */
+#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos        (11U)
+#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */
+#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos         (12U)
+#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */
+#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos         (13U)
+#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */
+#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos        (15U)
+#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */
+#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
+#define TIM_CCER_CC5E_Pos         (16U)
+#define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */
+#define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */
+#define TIM_CCER_CC5P_Pos         (17U)
+#define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */
+#define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */
+#define TIM_CCER_CC6E_Pos         (20U)
+#define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */
+#define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */
+#define TIM_CCER_CC6P_Pos         (21U)
+#define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */
+#define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define TIM_CNT_CNT_Pos           (0U)
+#define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
+#define TIM_CNT_UIFCPY_Pos        (31U)
+#define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */
+#define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy */
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define TIM_PSC_PSC_Pos           (0U)
+#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */
+#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define TIM_ARR_ARR_Pos           (0U)
+#define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RCR register  ********************/
+#define TIM_RCR_REP_Pos           (0U)
+#define TIM_RCR_REP_Msk           (0xFFUL << TIM_RCR_REP_Pos)                  /*!< 0x000000FF */
+#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define TIM_CCR1_CCR1_Pos         (0U)
+#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)              /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define TIM_CCR2_CCR2_Pos         (0U)
+#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)              /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define TIM_CCR3_CCR3_Pos         (0U)
+#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)              /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define TIM_CCR4_CCR4_Pos         (0U)
+#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)              /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_CCR5 register  *******************/
+#define TIM_CCR5_CCR5_Pos         (0U)
+#define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)          /*!< 0xFFFFFFFF */
+#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */
+#define TIM_CCR5_GC5C1_Pos        (29U)
+#define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */
+#define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */
+#define TIM_CCR5_GC5C2_Pos        (30U)
+#define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */
+#define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */
+#define TIM_CCR5_GC5C3_Pos        (31U)
+#define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */
+#define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */
+
+/*******************  Bit definition for TIM_CCR6 register  *******************/
+#define TIM_CCR6_CCR6_Pos         (0U)
+#define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */
+#define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define TIM_BDTR_DTG_Pos          (0U)
+#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */
+#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000001 */
+#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000002 */
+#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000004 */
+#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000008 */
+#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000010 */
+#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000020 */
+#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000040 */
+#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000080 */
+
+#define TIM_BDTR_LOCK_Pos         (8U)
+#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */
+#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000100 */
+#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000200 */
+
+#define TIM_BDTR_OSSI_Pos         (10U)
+#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */
+#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos         (11U)
+#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */
+#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos          (12U)
+#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */
+#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break1 */
+#define TIM_BDTR_BKP_Pos          (13U)
+#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */
+#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break1 */
+#define TIM_BDTR_AOE_Pos          (14U)
+#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */
+#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos          (15U)
+#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */
+#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
+
+#define TIM_BDTR_BKF_Pos          (16U)
+#define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */
+#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break1 */
+#define TIM_BDTR_BK2F_Pos         (20U)
+#define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */
+#define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break2 */
+
+#define TIM_BDTR_BK2E_Pos         (24U)
+#define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */
+#define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break2 */
+#define TIM_BDTR_BK2P_Pos         (25U)
+#define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */
+#define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break2 */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define TIM_DCR_DBA_Pos           (0U)
+#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */
+#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
+#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
+#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
+#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
+#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos           (8U)
+#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */
+#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
+#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
+#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
+#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
+#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define TIM_DMAR_DMAB_Pos         (0U)
+#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)              /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
+
+/******************  Bit definition for TIM_CCMR3 register  *******************/
+#define TIM_CCMR3_OC5FE_Pos       (2U)
+#define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */
+#define TIM_CCMR3_OC5PE_Pos       (3U)
+#define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */
+#define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
+
+#define TIM_CCMR3_OC5M_Pos        (4U)
+#define TIM_CCMR3_OC5M_Msk        (0x7UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00000070 */
+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_0          (0x1UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000010 */
+#define TIM_CCMR3_OC5M_1          (0x2UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000020 */
+#define TIM_CCMR3_OC5M_2          (0x4UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000040 */
+#define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010000 */
+
+#define TIM_CCMR3_OC5CE_Pos       (7U)
+#define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */
+#define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */
+
+#define TIM_CCMR3_OC6FE_Pos       (10U)
+#define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR3_OC6PE_Pos       (11U)
+#define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */
+#define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR3_OC6M_Pos        (12U)
+#define TIM_CCMR3_OC6M_Msk        (0x7UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x00007000 */
+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR3_OC6M_0          (0x1UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00001000 */
+#define TIM_CCMR3_OC6M_1          (0x2UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00002000 */
+#define TIM_CCMR3_OC6M_2          (0x4UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00004000 */
+#define TIM_CCMR3_OC6M_3          (0x100UL << TIM_CCMR3_OC6M_Pos)               /*!< 0x00100000 */
+
+#define TIM_CCMR3_OC6CE_Pos       (15U)
+#define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
+#define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 4 Clear Enable */
+/*******************  Bit definition for TIM1_AF1 register  *********************/
+#define TIM1_AF1_BKINE_Pos        (0U)
+#define TIM1_AF1_BKINE_Msk        (0x1UL << TIM1_AF1_BKINE_Pos)                /*!< 0x00000001 */
+#define TIM1_AF1_BKINE            TIM1_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */
+#define TIM1_AF1_BKCMP1E_Pos      (1U)
+#define TIM1_AF1_BKCMP1E_Msk      (0x1UL << TIM1_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */
+#define TIM1_AF1_BKCMP1E          TIM1_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */
+#define TIM1_AF1_BKCMP2E_Pos      (2U)
+#define TIM1_AF1_BKCMP2E_Msk      (0x1UL << TIM1_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */
+#define TIM1_AF1_BKCMP2E          TIM1_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit */
+#define TIM1_AF1_BKDF1BK0E_Pos    (8U)
+#define TIM1_AF1_BKDF1BK0E_Msk    (0x1UL << TIM1_AF1_BKDF1BK0E_Pos)            /*!< 0x00000100 */
+#define TIM1_AF1_BKDF1BK0E        TIM1_AF1_BKDF1BK0E_Msk                       /*!<BKDF1BK0E Break input DFSDM Break 0 */
+#define TIM1_AF1_BKINP_Pos        (9U)
+#define TIM1_AF1_BKINP_Msk        (0x1UL << TIM1_AF1_BKINP_Pos)                /*!< 0x00000200 */
+#define TIM1_AF1_BKINP            TIM1_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */
+#define TIM1_AF1_BKCMP1P_Pos      (10U)
+#define TIM1_AF1_BKCMP1P_Msk      (0x1UL << TIM1_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */
+#define TIM1_AF1_BKCMP1P          TIM1_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */
+#define TIM1_AF1_BKCMP2P_Pos      (11U)
+#define TIM1_AF1_BKCMP2P_Msk      (0x1UL << TIM1_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */
+#define TIM1_AF1_BKCMP2P          TIM1_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */
+
+#define TIM1_AF1_ETRSEL_Pos       (14U)
+#define TIM1_AF1_ETRSEL_Msk       (0xFUL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */
+#define TIM1_AF1_ETRSEL           TIM1_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM1 ETRSEL) */
+#define TIM1_AF1_ETRSEL_0         (0x1UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00004000 */
+#define TIM1_AF1_ETRSEL_1         (0x2UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00008000 */
+#define TIM1_AF1_ETRSEL_2         (0x4UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00010000 */
+#define TIM1_AF1_ETRSEL_3         (0x8UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00020000 */
+
+/*******************  Bit definition for TIM1_AF2 register  *********************/
+#define TIM1_AF2_BK2INE_Pos       (0U)
+#define TIM1_AF2_BK2INE_Msk       (0x1UL << TIM1_AF2_BK2INE_Pos)               /*!< 0x00000001 */
+#define TIM1_AF2_BK2INE           TIM1_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */
+#define TIM1_AF2_BK2CMP1E_Pos     (1U)
+#define TIM1_AF2_BK2CMP1E_Msk     (0x1UL << TIM1_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */
+#define TIM1_AF2_BK2CMP1E         TIM1_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */
+#define TIM1_AF2_BK2CMP2E_Pos     (2U)
+#define TIM1_AF2_BK2CMP2E_Msk     (0x1UL << TIM1_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */
+#define TIM1_AF2_BK2CMP2E         TIM1_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */
+#define TIM1_AF2_BK2DFBK1E_Pos    (8U)
+#define TIM1_AF2_BK2DFBK1E_Msk    (0x1UL << TIM1_AF2_BK2DFBK1E_Pos)            /*!< 0x00000100 */
+#define TIM1_AF2_BK2DFBK1E        TIM1_AF2_BK2DFBK1E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 1 */
+#define TIM1_AF2_BK2INP_Pos       (9U)
+#define TIM1_AF2_BK2INP_Msk       (0x1UL << TIM1_AF2_BK2INP_Pos)               /*!< 0x00000200 */
+#define TIM1_AF2_BK2INP           TIM1_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */
+#define TIM1_AF2_BK2CMP1P_Pos     (10U)
+#define TIM1_AF2_BK2CMP1P_Msk     (0x1UL << TIM1_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */
+#define TIM1_AF2_BK2CMP1P         TIM1_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */
+#define TIM1_AF2_BK2CMP2P_Pos     (11U)
+#define TIM1_AF2_BK2CMP2P_Msk     (0x1UL << TIM1_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */
+#define TIM1_AF2_BK2CMP2P         TIM1_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */
+
+/*******************  Bit definition for TIM_TISEL register  *********************/
+#define TIM_TISEL_TI1SEL_Pos      (0U)
+#define TIM_TISEL_TI1SEL_Msk      (0xFUL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x0000000F */
+#define TIM_TISEL_TI1SEL          TIM_TISEL_TI1SEL_Msk                         /*!<TI1SEL[3:0] bits (TIM TI1 SEL)*/
+#define TIM_TISEL_TI1SEL_0        (0x1UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000001 */
+#define TIM_TISEL_TI1SEL_1        (0x2UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000002 */
+#define TIM_TISEL_TI1SEL_2        (0x4UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000004 */
+#define TIM_TISEL_TI1SEL_3        (0x8UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000008 */
+
+#define TIM_TISEL_TI2SEL_Pos      (8U)
+#define TIM_TISEL_TI2SEL_Msk      (0xFUL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000F00 */
+#define TIM_TISEL_TI2SEL          TIM_TISEL_TI2SEL_Msk                         /*!<TI2SEL[3:0] bits (TIM TI2 SEL)*/
+#define TIM_TISEL_TI2SEL_0        (0x1UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000100 */
+#define TIM_TISEL_TI2SEL_1        (0x2UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000200 */
+#define TIM_TISEL_TI2SEL_2        (0x4UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000400 */
+#define TIM_TISEL_TI2SEL_3        (0x8UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000800 */
+
+#define TIM_TISEL_TI3SEL_Pos      (16U)
+#define TIM_TISEL_TI3SEL_Msk      (0xFUL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x000F0000 */
+#define TIM_TISEL_TI3SEL          TIM_TISEL_TI3SEL_Msk                         /*!<TI3SEL[3:0] bits (TIM TI3 SEL)*/
+#define TIM_TISEL_TI3SEL_0        (0x1UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00010000 */
+#define TIM_TISEL_TI3SEL_1        (0x2UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00020000 */
+#define TIM_TISEL_TI3SEL_2        (0x4UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00040000 */
+#define TIM_TISEL_TI3SEL_3        (0x8UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00080000 */
+
+#define TIM_TISEL_TI4SEL_Pos      (24U)
+#define TIM_TISEL_TI4SEL_Msk      (0xFUL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x0F000000 */
+#define TIM_TISEL_TI4SEL          TIM_TISEL_TI4SEL_Msk                         /*!<TI4SEL[3:0] bits (TIM TI4 SEL)*/
+#define TIM_TISEL_TI4SEL_0        (0x1UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x01000000 */
+#define TIM_TISEL_TI4SEL_1        (0x2UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x02000000 */
+#define TIM_TISEL_TI4SEL_2        (0x4UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x04000000 */
+#define TIM_TISEL_TI4SEL_3        (0x8UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x08000000 */
+
+/*******************  Bit definition for TIM8_AF1 register  *********************/
+#define TIM8_AF1_BKINE_Pos        (0U)
+#define TIM8_AF1_BKINE_Msk        (0x1UL << TIM8_AF1_BKINE_Pos)                /*!< 0x00000001 */
+#define TIM8_AF1_BKINE            TIM8_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */
+#define TIM8_AF1_BKCMP1E_Pos      (1U)
+#define TIM8_AF1_BKCMP1E_Msk      (0x1UL << TIM8_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */
+#define TIM8_AF1_BKCMP1E          TIM8_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */
+#define TIM8_AF1_BKCMP2E_Pos      (2U)
+#define TIM8_AF1_BKCMP2E_Msk      (0x1UL << TIM8_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */
+#define TIM8_AF1_BKCMP2E          TIM8_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit  */
+#define TIM8_AF1_BKDFBK2E_Pos     (8U)
+#define TIM8_AF1_BKDFBK2E_Msk     (0x1UL << TIM8_AF1_BKDFBK2E_Pos)             /*!< 0x00000100 */
+#define TIM8_AF1_BKDFBK2E         TIM8_AF1_BKDFBK2E_Msk                        /*!<BKDFBK2E Break input DFSDM Break 2 */
+#define TIM8_AF1_BKINP_Pos        (9U)
+#define TIM8_AF1_BKINP_Msk        (0x1UL << TIM8_AF1_BKINP_Pos)                /*!< 0x00000200 */
+#define TIM8_AF1_BKINP            TIM8_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */
+#define TIM8_AF1_BKCMP1P_Pos      (10U)
+#define TIM8_AF1_BKCMP1P_Msk      (0x1UL << TIM8_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */
+#define TIM8_AF1_BKCMP1P          TIM8_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */
+#define TIM8_AF1_BKCMP2P_Pos      (11U)
+#define TIM8_AF1_BKCMP2P_Msk      (0x1UL << TIM8_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */
+#define TIM8_AF1_BKCMP2P          TIM8_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */
+
+#define TIM8_AF1_ETRSEL_Pos       (14U)
+#define TIM8_AF1_ETRSEL_Msk       (0xFUL << TIM8_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */
+#define TIM8_AF1_ETRSEL           TIM8_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM8 ETRSEL) */
+#define TIM8_AF1_ETRSEL_0         (0x1UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00004000 */
+#define TIM8_AF1_ETRSEL_1         (0x2UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00008000 */
+#define TIM8_AF1_ETRSEL_2         (0x4UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00010000 */
+#define TIM8_AF1_ETRSEL_3         (0x8UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00020000 */
+/*******************  Bit definition for TIM8_AF2 register  *********************/
+#define TIM8_AF2_BK2INE_Pos       (0U)
+#define TIM8_AF2_BK2INE_Msk       (0x1UL << TIM8_AF2_BK2INE_Pos)               /*!< 0x00000001 */
+#define TIM8_AF2_BK2INE           TIM8_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */
+#define TIM8_AF2_BK2CMP1E_Pos     (1U)
+#define TIM8_AF2_BK2CMP1E_Msk     (0x1UL << TIM8_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */
+#define TIM8_AF2_BK2CMP1E         TIM8_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */
+#define TIM8_AF2_BK2CMP2E_Pos     (2U)
+#define TIM8_AF2_BK2CMP2E_Msk     (0x1UL << TIM8_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */
+#define TIM8_AF2_BK2CMP2E         TIM8_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */
+#define TIM8_AF2_BK2DFBK3E_Pos    (8U)
+#define TIM8_AF2_BK2DFBK3E_Msk    (0x1UL << TIM8_AF2_BK2DFBK3E_Pos)            /*!< 0x00000100 */
+#define TIM8_AF2_BK2DFBK3E        TIM8_AF2_BK2DFBK3E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 3 */
+#define TIM8_AF2_BK2INP_Pos       (9U)
+#define TIM8_AF2_BK2INP_Msk       (0x1UL << TIM8_AF2_BK2INP_Pos)               /*!< 0x00000200 */
+#define TIM8_AF2_BK2INP           TIM8_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */
+#define TIM8_AF2_BK2CMP1P_Pos     (10U)
+#define TIM8_AF2_BK2CMP1P_Msk     (0x1UL << TIM8_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */
+#define TIM8_AF2_BK2CMP1P         TIM8_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */
+#define TIM8_AF2_BK2CMP2P_Pos     (11U)
+#define TIM8_AF2_BK2CMP2P_Msk     (0x1UL << TIM8_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */
+#define TIM8_AF2_BK2CMP2P         TIM8_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */
+
+/*******************  Bit definition for TIM2_AF1 register  *********************/
+#define TIM2_AF1_ETRSEL_Pos      (14U)
+#define TIM2_AF1_ETRSEL_Msk      (0xFUL << TIM2_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */
+#define TIM2_AF1_ETRSEL          TIM2_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM2 ETRSEL) */
+#define TIM2_AF1_ETRSEL_0        (0x1UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */
+#define TIM2_AF1_ETRSEL_1        (0x2UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */
+#define TIM2_AF1_ETRSEL_2        (0x4UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */
+#define TIM2_AF1_ETRSEL_3        (0x8UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */
+
+/*******************  Bit definition for TIM3_AF1 register  *********************/
+#define TIM3_AF1_ETRSEL_Pos      (14U)
+#define TIM3_AF1_ETRSEL_Msk      (0xFUL << TIM3_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */
+#define TIM3_AF1_ETRSEL          TIM3_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM3 ETRSEL) */
+#define TIM3_AF1_ETRSEL_0        (0x1UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */
+#define TIM3_AF1_ETRSEL_1        (0x2UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */
+#define TIM3_AF1_ETRSEL_2        (0x4UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */
+#define TIM3_AF1_ETRSEL_3        (0x8UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */
+
+/*******************  Bit definition for TIM5_AF1 register  *********************/
+#define TIM5_AF1_ETRSEL_Pos      (14U)
+#define TIM5_AF1_ETRSEL_Msk      (0xFUL << TIM5_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */
+#define TIM5_AF1_ETRSEL          TIM5_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM5 ETRSEL) */
+#define TIM5_AF1_ETRSEL_0        (0x1UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */
+#define TIM5_AF1_ETRSEL_1        (0x2UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */
+#define TIM5_AF1_ETRSEL_2        (0x4UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */
+#define TIM5_AF1_ETRSEL_3        (0x8UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */
+
+/*******************  Bit definition for TIM15_AF1 register  *********************/
+#define TIM15_AF1_BKINE_Pos        (0U)
+#define TIM15_AF1_BKINE_Msk        (0x1UL << TIM15_AF1_BKINE_Pos)              /*!< 0x00000001 */
+#define TIM15_AF1_BKINE            TIM15_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */
+#define TIM15_AF1_BKCMP1E_Pos      (1U)
+#define TIM15_AF1_BKCMP1E_Msk      (0x1UL << TIM15_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */
+#define TIM15_AF1_BKCMP1E          TIM15_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */
+#define TIM15_AF1_BKCMP2E_Pos      (2U)
+#define TIM15_AF1_BKCMP2E_Msk      (0x1UL << TIM15_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */
+#define TIM15_AF1_BKCMP2E          TIM15_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */
+#define TIM15_AF1_BKDF1BK2E_Pos    (8U)
+#define TIM15_AF1_BKDF1BK2E_Msk    (0x1UL << TIM15_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */
+#define TIM15_AF1_BKDF1BK2E        TIM15_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[0] enable */
+#define TIM15_AF1_BKINP_Pos        (9U)
+#define TIM15_AF1_BKINP_Msk        (0x1UL << TIM15_AF1_BKINP_Pos)              /*!< 0x00000200 */
+#define TIM15_AF1_BKINP            TIM15_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */
+#define TIM15_AF1_BKCMP1P_Pos      (10U)
+#define TIM15_AF1_BKCMP1P_Msk      (0x1UL << TIM15_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */
+#define TIM15_AF1_BKCMP1P          TIM15_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */
+#define TIM15_AF1_BKCMP2P_Pos      (11U)
+#define TIM15_AF1_BKCMP2P_Msk      (0x1UL << TIM15_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */
+#define TIM15_AF1_BKCMP2P          TIM15_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */
+
+/*******************  Bit definition for TIM16_ register  *********************/
+#define TIM16_AF1_BKINE_Pos        (0U)
+#define TIM16_AF1_BKINE_Msk        (0x1UL << TIM16_AF1_BKINE_Pos)              /*!< 0x00000001 */
+#define TIM16_AF1_BKINE            TIM16_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */
+#define TIM16_AF1_BKCMP1E_Pos      (1U)
+#define TIM16_AF1_BKCMP1E_Msk      (0x1UL << TIM16_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */
+#define TIM16_AF1_BKCMP1E          TIM16_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */
+#define TIM16_AF1_BKCMP2E_Pos      (2U)
+#define TIM16_AF1_BKCMP2E_Msk      (0x1UL << TIM16_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */
+#define TIM16_AF1_BKCMP2E          TIM16_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */
+#define TIM16_AF1_BKDF1BK2E_Pos    (8U)
+#define TIM16_AF1_BKDF1BK2E_Msk    (0x1UL << TIM16_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */
+#define TIM16_AF1_BKDF1BK2E        TIM16_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[1] enable */
+#define TIM16_AF1_BKINP_Pos        (9U)
+#define TIM16_AF1_BKINP_Msk        (0x1UL << TIM16_AF1_BKINP_Pos)              /*!< 0x00000200 */
+#define TIM16_AF1_BKINP            TIM16_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */
+#define TIM16_AF1_BKCMP1P_Pos      (10U)
+#define TIM16_AF1_BKCMP1P_Msk      (0x1UL << TIM16_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */
+#define TIM16_AF1_BKCMP1P          TIM16_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */
+#define TIM16_AF1_BKCMP2P_Pos      (11U)
+#define TIM16_AF1_BKCMP2P_Msk      (0x1UL << TIM16_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */
+#define TIM16_AF1_BKCMP2P          TIM16_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */
+
+/*******************  Bit definition for TIM17_AF1 register  *********************/
+#define TIM17_AF1_BKINE_Pos        (0U)
+#define TIM17_AF1_BKINE_Msk        (0x1UL << TIM17_AF1_BKINE_Pos)              /*!< 0x00000001 */
+#define TIM17_AF1_BKINE            TIM17_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */
+#define TIM17_AF1_BKCMP1E_Pos      (1U)
+#define TIM17_AF1_BKCMP1E_Msk      (0x1UL << TIM17_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */
+#define TIM17_AF1_BKCMP1E          TIM17_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */
+#define TIM17_AF1_BKCMP2E_Pos      (2U)
+#define TIM17_AF1_BKCMP2E_Msk      (0x1UL << TIM17_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */
+#define TIM17_AF1_BKCMP2E          TIM17_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */
+#define TIM17_AF1_BKDF1BK2E_Pos    (8U)
+#define TIM17_AF1_BKDF1BK2E_Msk    (0x1UL << TIM17_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */
+#define TIM17_AF1_BKDF1BK2E        TIM17_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[2] enable */
+#define TIM17_AF1_BKINP_Pos        (9U)
+#define TIM17_AF1_BKINP_Msk        (0x1UL << TIM17_AF1_BKINP_Pos)              /*!< 0x00000200 */
+#define TIM17_AF1_BKINP            TIM17_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */
+#define TIM17_AF1_BKCMP1P_Pos      (10U)
+#define TIM17_AF1_BKCMP1P_Msk      (0x1UL << TIM17_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */
+#define TIM17_AF1_BKCMP1P          TIM17_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */
+#define TIM17_AF1_BKCMP2P_Pos      (11U)
+#define TIM17_AF1_BKCMP2P_Msk      (0x1UL << TIM17_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */
+#define TIM17_AF1_BKCMP2P          TIM17_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Low Power Timer (LPTTIM)                           */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for LPTIM_ISR register  *******************/
+#define LPTIM_ISR_CMPM_Pos          (0U)
+#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)              /*!< 0x00000001 */
+#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
+#define LPTIM_ISR_ARRM_Pos          (1U)
+#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */
+#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG_Pos       (2U)
+#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */
+#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK_Pos         (3U)
+#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)             /*!< 0x00000008 */
+#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK_Pos         (4U)
+#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */
+#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP_Pos            (5U)
+#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */
+#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN_Pos          (6U)
+#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */
+#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
+
+/******************  Bit definition for LPTIM_ICR register  *******************/
+#define LPTIM_ICR_CMPMCF_Pos        (0U)
+#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)            /*!< 0x00000001 */
+#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF_Pos        (1U)
+#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */
+#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)
+#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */
+#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF_Pos       (3U)
+#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)           /*!< 0x00000008 */
+#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF_Pos       (4U)
+#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */
+#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF_Pos          (5U)
+#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */
+#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF_Pos        (6U)
+#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */
+#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
+
+/******************  Bit definition for LPTIM_IER register ********************/
+#define LPTIM_IER_CMPMIE_Pos        (0U)
+#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)            /*!< 0x00000001 */
+#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE_Pos        (1U)
+#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)            /*!< 0x00000002 */
+#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE_Pos     (2U)
+#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)         /*!< 0x00000004 */
+#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE_Pos       (3U)
+#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)           /*!< 0x00000008 */
+#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE_Pos       (4U)
+#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)           /*!< 0x00000010 */
+#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE_Pos          (5U)
+#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)              /*!< 0x00000020 */
+#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE_Pos        (6U)
+#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)            /*!< 0x00000040 */
+#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
+
+/******************  Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL_Pos        (0U)
+#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */
+#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL_Pos        (1U)
+#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */
+#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */
+#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */
+
+#define LPTIM_CFGR_CKFLT_Pos        (3U)
+#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */
+#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */
+#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */
+
+#define LPTIM_CFGR_TRGFLT_Pos       (6U)
+#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */
+#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */
+#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */
+
+#define LPTIM_CFGR_PRESC_Pos        (9U)
+#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */
+#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */
+#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */
+#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */
+
+#define LPTIM_CFGR_TRIGSEL_Pos      (13U)
+#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x0000E000 */
+#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */
+#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */
+#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */
+
+#define LPTIM_CFGR_TRIGEN_Pos       (17U)
+#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */
+#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */
+#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */
+
+#define LPTIM_CFGR_TIMOUT_Pos       (19U)
+#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */
+#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
+#define LPTIM_CFGR_WAVE_Pos         (20U)
+#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */
+#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL_Pos       (21U)
+#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */
+#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD_Pos      (22U)
+#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */
+#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE_Pos    (23U)
+#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */
+#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC_Pos          (24U)
+#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */
+#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
+
+/******************  Bit definition for LPTIM_CR register  ********************/
+#define LPTIM_CR_ENABLE_Pos         (0U)
+#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */
+#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT_Pos        (1U)
+#define LPTIM_CR_SNGSTRT_Msk        (0x40001UL << LPTIM_CR_SNGSTRT_Pos)        /*!< 0x00080002 */
+#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT_Pos        (2U)
+#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */
+#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
+#define LPTIM_CR_COUNTRST_Pos       (3U)
+#define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */
+#define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Timer Counter reset in synchronous mode*/
+#define LPTIM_CR_RSTARE_Pos         (4U)
+#define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */
+#define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Timer Counter reset after read enable (asynchronously)*/
+
+
+/******************  Bit definition for LPTIM_CMP register  *******************/
+#define LPTIM_CMP_CMP_Pos           (0U)
+#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)            /*!< 0x0000FFFF */
+#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
+
+/******************  Bit definition for LPTIM_ARR register  *******************/
+#define LPTIM_ARR_ARR_Pos           (0U)
+#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */
+#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
+
+/******************  Bit definition for LPTIM_CNT register  *******************/
+#define LPTIM_CNT_CNT_Pos           (0U)
+#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */
+#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
+
+/******************  Bit definition for LPTIM_CFGR2 register  *****************/
+#define LPTIM_CFGR2_IN1SEL_Pos      (0U)
+#define LPTIM_CFGR2_IN1SEL_Msk      (0x3UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000003 */
+#define LPTIM_CFGR2_IN1SEL          LPTIM_CFGR2_IN1SEL_Msk                     /*!< IN1SEL[1:0] bits (Remap selection) */
+#define LPTIM_CFGR2_IN1SEL_0        (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000001 */
+#define LPTIM_CFGR2_IN1SEL_1        (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000002 */
+#define LPTIM_CFGR2_IN2SEL_Pos      (4U)
+#define LPTIM_CFGR2_IN2SEL_Msk      (0x3UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000030 */
+#define LPTIM_CFGR2_IN2SEL          LPTIM_CFGR2_IN2SEL_Msk                     /*!< IN2SEL[5:4] bits (Remap selection) */
+#define LPTIM_CFGR2_IN2SEL_0        (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000010 */
+#define LPTIM_CFGR2_IN2SEL_1        (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000020 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Analog Comparators (COMP)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for COMP_SR register  ********************/
+#define COMP_SR_C1VAL_Pos            (0U)
+#define COMP_SR_C1VAL_Msk            (0x1UL << COMP_SR_C1VAL_Pos)              /*!< 0x00000001 */
+#define COMP_SR_C1VAL                COMP_SR_C1VAL_Msk
+#define COMP_SR_C2VAL_Pos            (1U)
+#define COMP_SR_C2VAL_Msk            (0x1UL << COMP_SR_C2VAL_Pos)              /*!< 0x00000002 */
+#define COMP_SR_C2VAL                COMP_SR_C2VAL_Msk
+#define COMP_SR_C1IF_Pos             (16U)
+#define COMP_SR_C1IF_Msk             (0x1UL << COMP_SR_C1IF_Pos)               /*!< 0x00010000 */
+#define COMP_SR_C1IF                 COMP_SR_C1IF_Msk
+#define COMP_SR_C2IF_Pos             (17U)
+#define COMP_SR_C2IF_Msk             (0x1UL << COMP_SR_C2IF_Pos)               /*!< 0x00020000 */
+#define COMP_SR_C2IF                 COMP_SR_C2IF_Msk
+/*******************  Bit definition for COMP_ICFR register  ********************/
+#define COMP_ICFR_C1IF_Pos           (16U)
+#define COMP_ICFR_C1IF_Msk           (0x1UL << COMP_ICFR_C1IF_Pos)             /*!< 0x00010000 */
+#define COMP_ICFR_C1IF               COMP_ICFR_C1IF_Msk
+#define COMP_ICFR_C2IF_Pos           (17U)
+#define COMP_ICFR_C2IF_Msk           (0x1UL << COMP_ICFR_C2IF_Pos)             /*!< 0x00020000 */
+#define COMP_ICFR_C2IF               COMP_ICFR_C2IF_Msk
+/*******************  Bit definition for COMP_OR register  ********************/
+#define COMP_OR_AFOPA6_Pos           (0U)
+#define COMP_OR_AFOPA6_Msk           (0x1UL << COMP_OR_AFOPA6_Pos)             /*!< 0x00000001 */
+#define COMP_OR_AFOPA6               COMP_OR_AFOPA6_Msk
+#define COMP_OR_AFOPA8_Pos           (1U)
+#define COMP_OR_AFOPA8_Msk           (0x1UL << COMP_OR_AFOPA8_Pos)             /*!< 0x00000002 */
+#define COMP_OR_AFOPA8               COMP_OR_AFOPA8_Msk
+#define COMP_OR_AFOPB12_Pos          (2U)
+#define COMP_OR_AFOPB12_Msk          (0x1UL << COMP_OR_AFOPB12_Pos)            /*!< 0x00000004 */
+#define COMP_OR_AFOPB12              COMP_OR_AFOPB12_Msk
+#define COMP_OR_AFOPE6_Pos           (3U)
+#define COMP_OR_AFOPE6_Msk           (0x1UL << COMP_OR_AFOPE6_Pos)             /*!< 0x00000008 */
+#define COMP_OR_AFOPE6               COMP_OR_AFOPE6_Msk
+#define COMP_OR_AFOPE15_Pos          (4U)
+#define COMP_OR_AFOPE15_Msk          (0x1UL << COMP_OR_AFOPE15_Pos)            /*!< 0x00000010 */
+#define COMP_OR_AFOPE15              COMP_OR_AFOPE15_Msk
+#define COMP_OR_AFOPG2_Pos           (5U)
+#define COMP_OR_AFOPG2_Msk           (0x1UL << COMP_OR_AFOPG2_Pos)             /*!< 0x00000020 */
+#define COMP_OR_AFOPG2               COMP_OR_AFOPG2_Msk
+#define COMP_OR_AFOPG3_Pos           (6U)
+#define COMP_OR_AFOPG3_Msk           (0x1UL << COMP_OR_AFOPG3_Pos)             /*!< 0x00000040 */
+#define COMP_OR_AFOPG3               COMP_OR_AFOPG3_Msk
+#define COMP_OR_AFOPG4_Pos           (7U)
+#define COMP_OR_AFOPG4_Msk           (0x1UL << COMP_OR_AFOPG4_Pos)             /*!< 0x00000080 */
+#define COMP_OR_AFOPG4               COMP_OR_AFOPG4_Msk
+#define COMP_OR_AFOPI1_Pos           (8U)
+#define COMP_OR_AFOPI1_Msk           (0x1UL << COMP_OR_AFOPI1_Pos)             /*!< 0x00000100 */
+#define COMP_OR_AFOPI1               COMP_OR_AFOPI1_Msk
+#define COMP_OR_AFOPI4_Pos           (9U)
+#define COMP_OR_AFOPI4_Msk           (0x1UL << COMP_OR_AFOPI4_Pos)             /*!< 0x00000200 */
+#define COMP_OR_AFOPI4               COMP_OR_AFOPI4_Msk
+#define COMP_OR_AFOPK2_Pos           (10U)
+#define COMP_OR_AFOPK2_Msk           (0x1UL << COMP_OR_AFOPK2_Pos)             /*!< 0x00000400 */
+#define COMP_OR_AFOPK2               COMP_OR_AFOPK2_Msk
+
+/*!< ******************  Bit definition for COMP_CFGRx register  ********************/
+#define COMP_CFGRx_EN_Pos            (0U)
+#define COMP_CFGRx_EN_Msk            (0x1UL << COMP_CFGRx_EN_Pos)              /*!< 0x00000001 */
+#define COMP_CFGRx_EN                COMP_CFGRx_EN_Msk                         /*!< COMPx enable bit                     */
+#define COMP_CFGRx_BRGEN_Pos         (1U)
+#define COMP_CFGRx_BRGEN_Msk         (0x1UL << COMP_CFGRx_BRGEN_Pos)           /*!< 0x00000002 */
+#define COMP_CFGRx_BRGEN             COMP_CFGRx_BRGEN_Msk                      /*!< COMPx Scaler bridge enable           */
+#define COMP_CFGRx_SCALEN_Pos        (2U)
+#define COMP_CFGRx_SCALEN_Msk        (0x1UL << COMP_CFGRx_SCALEN_Pos)          /*!< 0x00000004 */
+#define COMP_CFGRx_SCALEN            COMP_CFGRx_SCALEN_Msk                     /*!< COMPx Voltage scaler enable bit      */
+#define COMP_CFGRx_POLARITY_Pos      (3U)
+#define COMP_CFGRx_POLARITY_Msk      (0x1UL << COMP_CFGRx_POLARITY_Pos)        /*!< 0x00000008 */
+#define COMP_CFGRx_POLARITY          COMP_CFGRx_POLARITY_Msk                   /*!< COMPx  polarity selection bit        */
+#define COMP_CFGRx_WINMODE_Pos       (4U)
+#define COMP_CFGRx_WINMODE_Msk       (0x1UL << COMP_CFGRx_WINMODE_Pos)         /*!< 0x00000010 */
+#define COMP_CFGRx_WINMODE           COMP_CFGRx_WINMODE_Msk                    /*!< COMPx Windows mode selection bit     */
+#define COMP_CFGRx_ITEN_Pos          (6U)
+#define COMP_CFGRx_ITEN_Msk          (0x1UL << COMP_CFGRx_ITEN_Pos)            /*!< 0x00000040 */
+#define COMP_CFGRx_ITEN              COMP_CFGRx_ITEN_Msk                       /*!< COMPx  interrupt enable              */
+#define COMP_CFGRx_HYST_Pos          (8U)
+#define COMP_CFGRx_HYST_Msk          (0x3UL << COMP_CFGRx_HYST_Pos)            /*!< 0x00000300 */
+#define COMP_CFGRx_HYST              COMP_CFGRx_HYST_Msk                       /*!< COMPx  hysteresis selection bits     */
+#define COMP_CFGRx_HYST_0            (0x1UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000100 */
+#define COMP_CFGRx_HYST_1            (0x2UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000200 */
+#define COMP_CFGRx_PWRMODE_Pos       (12U)
+#define COMP_CFGRx_PWRMODE_Msk       (0x3UL << COMP_CFGRx_PWRMODE_Pos)         /*!< 0x00003000 */
+#define COMP_CFGRx_PWRMODE           COMP_CFGRx_PWRMODE_Msk                    /*!< COMPx Power Mode of the comparator   */
+#define COMP_CFGRx_PWRMODE_0         (0x1UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00001000 */
+#define COMP_CFGRx_PWRMODE_1         (0x2UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00002000 */
+#define COMP_CFGRx_INMSEL_Pos        (16U)
+#define COMP_CFGRx_INMSEL_Msk        (0x7UL << COMP_CFGRx_INMSEL_Pos)          /*!< 0x00070000 */
+#define COMP_CFGRx_INMSEL            COMP_CFGRx_INMSEL_Msk                     /*!< COMPx  input minus selection bit  */
+#define COMP_CFGRx_INMSEL_0          (0x1UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00010000 */
+#define COMP_CFGRx_INMSEL_1          (0x2UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00020000 */
+#define COMP_CFGRx_INMSEL_2          (0x4UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00040000 */
+#define COMP_CFGRx_INPSEL_Pos        (20U)
+#define COMP_CFGRx_INPSEL_Msk        (0x1UL << COMP_CFGRx_INPSEL_Pos)          /*!< 0x00100000 */
+#define COMP_CFGRx_INPSEL            COMP_CFGRx_INPSEL_Msk                     /*!< COMPx  input plus selection bit       */
+#define COMP_CFGRx_BLANKING_Pos      (24U)
+#define COMP_CFGRx_BLANKING_Msk      (0xFUL << COMP_CFGRx_BLANKING_Pos)        /*!< 0x0F000000 */
+#define COMP_CFGRx_BLANKING          COMP_CFGRx_BLANKING_Msk                   /*!< COMPx  blanking source selection bits */
+#define COMP_CFGRx_BLANKING_0        (0x1UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x01000000 */
+#define COMP_CFGRx_BLANKING_1        (0x2UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x02000000 */
+#define COMP_CFGRx_BLANKING_2        (0x4UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x04000000 */
+#define COMP_CFGRx_LOCK_Pos          (31U)
+#define COMP_CFGRx_LOCK_Msk          (0x1UL << COMP_CFGRx_LOCK_Pos)            /*!< 0x80000000 */
+#define COMP_CFGRx_LOCK              COMP_CFGRx_LOCK_Msk                       /*!< COMPx Lock Bit                        */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for USART_CR1 register  *******************/
+#define USART_CR1_UE_Pos                (0U)
+#define USART_CR1_UE_Msk                (0x1UL << USART_CR1_UE_Pos)            /*!< 0x00000001 */
+#define USART_CR1_UE                    USART_CR1_UE_Msk                       /*!< USART Enable */
+#define USART_CR1_UESM_Pos              (1U)
+#define USART_CR1_UESM_Msk              (0x1UL << USART_CR1_UESM_Pos)          /*!< 0x00000002 */
+#define USART_CR1_UESM                  USART_CR1_UESM_Msk                     /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE_Pos                (2U)
+#define USART_CR1_RE_Msk                (0x1UL << USART_CR1_RE_Pos)            /*!< 0x00000004 */
+#define USART_CR1_RE                    USART_CR1_RE_Msk                       /*!< Receiver Enable */
+#define USART_CR1_TE_Pos                (3U)
+#define USART_CR1_TE_Msk                (0x1UL << USART_CR1_TE_Pos)            /*!< 0x00000008 */
+#define USART_CR1_TE                    USART_CR1_TE_Msk                       /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos            (4U)
+#define USART_CR1_IDLEIE_Msk            (0x1UL << USART_CR1_IDLEIE_Pos)        /*!< 0x00000010 */
+#define USART_CR1_IDLEIE                USART_CR1_IDLEIE_Msk                   /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_RXFNEIE_Pos    (5U)
+#define USART_CR1_RXNEIE_RXFNEIE_Msk    (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE_RXFNEIE        USART_CR1_RXNEIE_RXFNEIE_Msk           /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
+#define USART_CR1_TCIE_Pos              (6U)
+#define USART_CR1_TCIE_Msk              (0x1UL << USART_CR1_TCIE_Pos)          /*!< 0x00000040 */
+#define USART_CR1_TCIE                  USART_CR1_TCIE_Msk                     /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_TXFNFIE_Pos     (7U)
+#define USART_CR1_TXEIE_TXFNFIE_Msk     (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE_TXFNFIE         USART_CR1_TXEIE_TXFNFIE_Msk            /*!< TXE and TX FIFO Not Full Interrupt Enable */
+#define USART_CR1_PEIE_Pos              (8U)
+#define USART_CR1_PEIE_Msk              (0x1UL << USART_CR1_PEIE_Pos)          /*!< 0x00000100 */
+#define USART_CR1_PEIE                  USART_CR1_PEIE_Msk                     /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos                (9U)
+#define USART_CR1_PS_Msk                (0x1UL << USART_CR1_PS_Pos)            /*!< 0x00000200 */
+#define USART_CR1_PS                    USART_CR1_PS_Msk                       /*!< Parity Selection */
+#define USART_CR1_PCE_Pos               (10U)
+#define USART_CR1_PCE_Msk               (0x1UL << USART_CR1_PCE_Pos)           /*!< 0x00000400 */
+#define USART_CR1_PCE                   USART_CR1_PCE_Msk                      /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos              (11U)
+#define USART_CR1_WAKE_Msk              (0x1UL << USART_CR1_WAKE_Pos)          /*!< 0x00000800 */
+#define USART_CR1_WAKE                  USART_CR1_WAKE_Msk                     /*!< Receiver Wakeup method */
+#define USART_CR1_M_Pos                 (12U)
+#define USART_CR1_M_Msk                 (0x10001UL << USART_CR1_M_Pos)         /*!< 0x10001000 */
+#define USART_CR1_M                     USART_CR1_M_Msk                        /*!< Word length */
+#define USART_CR1_M0_Pos                (12U)
+#define USART_CR1_M0_Msk                (0x1UL << USART_CR1_M0_Pos)            /*!< 0x00001000 */
+#define USART_CR1_M0                    USART_CR1_M0_Msk                       /*!< Word length - Bit 0 */
+#define USART_CR1_MME_Pos               (13U)
+#define USART_CR1_MME_Msk               (0x1UL << USART_CR1_MME_Pos)           /*!< 0x00002000 */
+#define USART_CR1_MME                   USART_CR1_MME_Msk                      /*!< Mute Mode Enable */
+#define USART_CR1_CMIE_Pos              (14U)
+#define USART_CR1_CMIE_Msk              (0x1UL << USART_CR1_CMIE_Pos)          /*!< 0x00004000 */
+#define USART_CR1_CMIE                  USART_CR1_CMIE_Msk                     /*!< Character match interrupt enable */
+#define USART_CR1_OVER8_Pos             (15U)
+#define USART_CR1_OVER8_Msk             (0x1UL << USART_CR1_OVER8_Pos)         /*!< 0x00008000 */
+#define USART_CR1_OVER8                 USART_CR1_OVER8_Msk                    /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT_Pos              (16U)
+#define USART_CR1_DEDT_Msk              (0x1FUL << USART_CR1_DEDT_Pos)         /*!< 0x001F0000 */
+#define USART_CR1_DEDT                  USART_CR1_DEDT_Msk                     /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0                (0x01UL << USART_CR1_DEDT_Pos)          /*!< 0x00010000 */
+#define USART_CR1_DEDT_1                (0x02UL << USART_CR1_DEDT_Pos)          /*!< 0x00020000 */
+#define USART_CR1_DEDT_2                (0x04UL << USART_CR1_DEDT_Pos)          /*!< 0x00040000 */
+#define USART_CR1_DEDT_3                (0x08UL << USART_CR1_DEDT_Pos)          /*!< 0x00080000 */
+#define USART_CR1_DEDT_4                (0x10UL << USART_CR1_DEDT_Pos)          /*!< 0x00100000 */
+#define USART_CR1_DEAT_Pos              (21U)
+#define USART_CR1_DEAT_Msk              (0x1FUL << USART_CR1_DEAT_Pos)         /*!< 0x03E00000 */
+#define USART_CR1_DEAT                  USART_CR1_DEAT_Msk                     /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0                (0x01UL << USART_CR1_DEAT_Pos)          /*!< 0x00200000 */
+#define USART_CR1_DEAT_1                (0x02UL << USART_CR1_DEAT_Pos)          /*!< 0x00400000 */
+#define USART_CR1_DEAT_2                (0x04UL << USART_CR1_DEAT_Pos)          /*!< 0x00800000 */
+#define USART_CR1_DEAT_3                (0x08UL << USART_CR1_DEAT_Pos)          /*!< 0x01000000 */
+#define USART_CR1_DEAT_4                (0x10UL << USART_CR1_DEAT_Pos)          /*!< 0x02000000 */
+#define USART_CR1_RTOIE_Pos             (26U)
+#define USART_CR1_RTOIE_Msk             (0x1UL << USART_CR1_RTOIE_Pos)         /*!< 0x04000000 */
+#define USART_CR1_RTOIE                 USART_CR1_RTOIE_Msk                    /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE_Pos             (27U)
+#define USART_CR1_EOBIE_Msk             (0x1UL << USART_CR1_EOBIE_Pos)         /*!< 0x08000000 */
+#define USART_CR1_EOBIE                 USART_CR1_EOBIE_Msk                    /*!< End of Block interrupt enable */
+#define USART_CR1_M1_Pos                (28U)
+#define USART_CR1_M1_Msk                (0x1UL << USART_CR1_M1_Pos)            /*!< 0x10000000 */
+#define USART_CR1_M1                    USART_CR1_M1_Msk                       /*!< Word length - Bit 1 */
+#define USART_CR1_FIFOEN_Pos            (29U)
+#define USART_CR1_FIFOEN_Msk            (0x1UL << USART_CR1_FIFOEN_Pos)        /*!< 0x20000000 */
+#define USART_CR1_FIFOEN                USART_CR1_FIFOEN_Msk                   /*!< FIFO mode enable */
+#define USART_CR1_TXFEIE_Pos            (30U)
+#define USART_CR1_TXFEIE_Msk            (0x1UL << USART_CR1_TXFEIE_Pos)        /*!< 0x40000000 */
+#define USART_CR1_TXFEIE                USART_CR1_TXFEIE_Msk                   /*!< TXFIFO empty interrupt enable */
+#define USART_CR1_RXFFIE_Pos            (31U)
+#define USART_CR1_RXFFIE_Msk            (0x1UL << USART_CR1_RXFFIE_Pos)        /*!< 0x80000000 */
+#define USART_CR1_RXFFIE                USART_CR1_RXFFIE_Msk                   /*!< RXFIFO Full interrupt enable */
+
+/* Legacy define */
+#define  USART_CR1_RXNEIE  USART_CR1_RXNEIE_RXFNEIE
+#define  USART_CR1_TXEIE   USART_CR1_TXEIE_TXFNFIE
+
+/******************  Bit definition for USART_CR2 register  *******************/
+#define USART_CR2_SLVEN_Pos             (0U)
+#define USART_CR2_SLVEN_Msk             (0x1UL << USART_CR2_SLVEN_Pos)         /*!< 0x00000001 */
+#define USART_CR2_SLVEN                 USART_CR2_SLVEN_Msk                    /*!< Synchronous Slave mode Enable */
+#define USART_CR2_DIS_NSS_Pos           (3U)
+#define USART_CR2_DIS_NSS_Msk           (0x1UL << USART_CR2_DIS_NSS_Pos)       /*!< 0x00000008 */
+#define USART_CR2_DIS_NSS               USART_CR2_DIS_NSS_Msk                  /*!< Negative Slave Select (NSS) pin management */
+#define USART_CR2_ADDM7_Pos             (4U)
+#define USART_CR2_ADDM7_Msk             (0x1UL << USART_CR2_ADDM7_Pos)         /*!< 0x00000010 */
+#define USART_CR2_ADDM7                 USART_CR2_ADDM7_Msk                    /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL_Pos              (5U)
+#define USART_CR2_LBDL_Msk              (0x1UL << USART_CR2_LBDL_Pos)          /*!< 0x00000020 */
+#define USART_CR2_LBDL                  USART_CR2_LBDL_Msk                     /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos             (6U)
+#define USART_CR2_LBDIE_Msk             (0x1UL << USART_CR2_LBDIE_Pos)         /*!< 0x00000040 */
+#define USART_CR2_LBDIE                 USART_CR2_LBDIE_Msk                    /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos              (8U)
+#define USART_CR2_LBCL_Msk              (0x1UL << USART_CR2_LBCL_Pos)          /*!< 0x00000100 */
+#define USART_CR2_LBCL                  USART_CR2_LBCL_Msk                     /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos              (9U)
+#define USART_CR2_CPHA_Msk              (0x1UL << USART_CR2_CPHA_Pos)          /*!< 0x00000200 */
+#define USART_CR2_CPHA                  USART_CR2_CPHA_Msk                     /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos              (10U)
+#define USART_CR2_CPOL_Msk              (0x1UL << USART_CR2_CPOL_Pos)          /*!< 0x00000400 */
+#define USART_CR2_CPOL                  USART_CR2_CPOL_Msk                     /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos             (11U)
+#define USART_CR2_CLKEN_Msk             (0x1UL << USART_CR2_CLKEN_Pos)         /*!< 0x00000800 */
+#define USART_CR2_CLKEN                 USART_CR2_CLKEN_Msk                    /*!< Clock Enable */
+#define USART_CR2_STOP_Pos              (12U)
+#define USART_CR2_STOP_Msk              (0x3UL << USART_CR2_STOP_Pos)          /*!< 0x00003000 */
+#define USART_CR2_STOP                  USART_CR2_STOP_Msk                     /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0                (0x1UL << USART_CR2_STOP_Pos)           /*!< 0x00001000 */
+#define USART_CR2_STOP_1                (0x2UL << USART_CR2_STOP_Pos)           /*!< 0x00002000 */
+#define USART_CR2_LINEN_Pos             (14U)
+#define USART_CR2_LINEN_Msk             (0x1UL << USART_CR2_LINEN_Pos)         /*!< 0x00004000 */
+#define USART_CR2_LINEN                 USART_CR2_LINEN_Msk                    /*!< LIN mode enable */
+#define USART_CR2_SWAP_Pos              (15U)
+#define USART_CR2_SWAP_Msk              (0x1UL << USART_CR2_SWAP_Pos)          /*!< 0x00008000 */
+#define USART_CR2_SWAP                  USART_CR2_SWAP_Msk                     /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV_Pos             (16U)
+#define USART_CR2_RXINV_Msk             (0x1UL << USART_CR2_RXINV_Pos)         /*!< 0x00010000 */
+#define USART_CR2_RXINV                 USART_CR2_RXINV_Msk                    /*!< RX pin active level inversion */
+#define USART_CR2_TXINV_Pos             (17U)
+#define USART_CR2_TXINV_Msk             (0x1UL << USART_CR2_TXINV_Pos)         /*!< 0x00020000 */
+#define USART_CR2_TXINV                 USART_CR2_TXINV_Msk                    /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV_Pos           (18U)
+#define USART_CR2_DATAINV_Msk           (0x1UL << USART_CR2_DATAINV_Pos)       /*!< 0x00040000 */
+#define USART_CR2_DATAINV               USART_CR2_DATAINV_Msk                  /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST_Pos          (19U)
+#define USART_CR2_MSBFIRST_Msk          (0x1UL << USART_CR2_MSBFIRST_Pos)      /*!< 0x00080000 */
+#define USART_CR2_MSBFIRST              USART_CR2_MSBFIRST_Msk                 /*!< Most Significant Bit First */
+#define USART_CR2_ABREN_Pos             (20U)
+#define USART_CR2_ABREN_Msk             (0x1UL << USART_CR2_ABREN_Pos)         /*!< 0x00100000 */
+#define USART_CR2_ABREN                 USART_CR2_ABREN_Msk                    /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE_Pos           (21U)
+#define USART_CR2_ABRMODE_Msk           (0x3UL << USART_CR2_ABRMODE_Pos)       /*!< 0x00600000 */
+#define USART_CR2_ABRMODE               USART_CR2_ABRMODE_Msk                  /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0             (0x1UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00200000 */
+#define USART_CR2_ABRMODE_1             (0x2UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00400000 */
+#define USART_CR2_RTOEN_Pos             (23U)
+#define USART_CR2_RTOEN_Msk             (0x1UL << USART_CR2_RTOEN_Pos)         /*!< 0x00800000 */
+#define USART_CR2_RTOEN                 USART_CR2_RTOEN_Msk                    /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD_Pos               (24U)
+#define USART_CR2_ADD_Msk               (0xFFUL << USART_CR2_ADD_Pos)          /*!< 0xFF000000 */
+#define USART_CR2_ADD                   USART_CR2_ADD_Msk                      /*!< Address of the USART node */
+
+/******************  Bit definition for USART_CR3 register  *******************/
+#define USART_CR3_EIE_Pos               (0U)
+#define USART_CR3_EIE_Msk               (0x1UL << USART_CR3_EIE_Pos)           /*!< 0x00000001 */
+#define USART_CR3_EIE                   USART_CR3_EIE_Msk                      /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos              (1U)
+#define USART_CR3_IREN_Msk              (0x1UL << USART_CR3_IREN_Pos)          /*!< 0x00000002 */
+#define USART_CR3_IREN                  USART_CR3_IREN_Msk                     /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos              (2U)
+#define USART_CR3_IRLP_Msk              (0x1UL << USART_CR3_IRLP_Pos)          /*!< 0x00000004 */
+#define USART_CR3_IRLP                  USART_CR3_IRLP_Msk                     /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos             (3U)
+#define USART_CR3_HDSEL_Msk             (0x1UL << USART_CR3_HDSEL_Pos)         /*!< 0x00000008 */
+#define USART_CR3_HDSEL                 USART_CR3_HDSEL_Msk                    /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos              (4U)
+#define USART_CR3_NACK_Msk              (0x1UL << USART_CR3_NACK_Pos)          /*!< 0x00000010 */
+#define USART_CR3_NACK                  USART_CR3_NACK_Msk                     /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN_Pos              (5U)
+#define USART_CR3_SCEN_Msk              (0x1UL << USART_CR3_SCEN_Pos)          /*!< 0x00000020 */
+#define USART_CR3_SCEN                  USART_CR3_SCEN_Msk                     /*!< SmartCard mode enable */
+#define USART_CR3_DMAR_Pos              (6U)
+#define USART_CR3_DMAR_Msk              (0x1UL << USART_CR3_DMAR_Pos)          /*!< 0x00000040 */
+#define USART_CR3_DMAR                  USART_CR3_DMAR_Msk                     /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos              (7U)
+#define USART_CR3_DMAT_Msk              (0x1UL << USART_CR3_DMAT_Pos)          /*!< 0x00000080 */
+#define USART_CR3_DMAT                  USART_CR3_DMAT_Msk                     /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos              (8U)
+#define USART_CR3_RTSE_Msk              (0x1UL << USART_CR3_RTSE_Pos)          /*!< 0x00000100 */
+#define USART_CR3_RTSE                  USART_CR3_RTSE_Msk                     /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos              (9U)
+#define USART_CR3_CTSE_Msk              (0x1UL << USART_CR3_CTSE_Pos)          /*!< 0x00000200 */
+#define USART_CR3_CTSE                  USART_CR3_CTSE_Msk                     /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos             (10U)
+#define USART_CR3_CTSIE_Msk             (0x1UL << USART_CR3_CTSIE_Pos)         /*!< 0x00000400 */
+#define USART_CR3_CTSIE                 USART_CR3_CTSIE_Msk                    /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos            (11U)
+#define USART_CR3_ONEBIT_Msk            (0x1UL << USART_CR3_ONEBIT_Pos)        /*!< 0x00000800 */
+#define USART_CR3_ONEBIT                USART_CR3_ONEBIT_Msk                   /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS_Pos            (12U)
+#define USART_CR3_OVRDIS_Msk            (0x1UL << USART_CR3_OVRDIS_Pos)        /*!< 0x00001000 */
+#define USART_CR3_OVRDIS                USART_CR3_OVRDIS_Msk                   /*!< Overrun Disable */
+#define USART_CR3_DDRE_Pos              (13U)
+#define USART_CR3_DDRE_Msk              (0x1UL << USART_CR3_DDRE_Pos)          /*!< 0x00002000 */
+#define USART_CR3_DDRE                  USART_CR3_DDRE_Msk                     /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM_Pos               (14U)
+#define USART_CR3_DEM_Msk               (0x1UL << USART_CR3_DEM_Pos)           /*!< 0x00004000 */
+#define USART_CR3_DEM                   USART_CR3_DEM_Msk                      /*!< Driver Enable Mode */
+#define USART_CR3_DEP_Pos               (15U)
+#define USART_CR3_DEP_Msk               (0x1UL << USART_CR3_DEP_Pos)           /*!< 0x00008000 */
+#define USART_CR3_DEP                   USART_CR3_DEP_Msk                      /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT_Pos           (17U)
+#define USART_CR3_SCARCNT_Msk           (0x7UL << USART_CR3_SCARCNT_Pos)       /*!< 0x000E0000 */
+#define USART_CR3_SCARCNT               USART_CR3_SCARCNT_Msk                  /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0             (0x1UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00020000 */
+#define USART_CR3_SCARCNT_1             (0x2UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00040000 */
+#define USART_CR3_SCARCNT_2             (0x4UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00080000 */
+#define USART_CR3_WUS_Pos               (20U)
+#define USART_CR3_WUS_Msk               (0x3UL << USART_CR3_WUS_Pos)           /*!< 0x00300000 */
+#define USART_CR3_WUS                   USART_CR3_WUS_Msk                      /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0                 (0x1UL << USART_CR3_WUS_Pos)            /*!< 0x00100000 */
+#define USART_CR3_WUS_1                 (0x2UL << USART_CR3_WUS_Pos)            /*!< 0x00200000 */
+#define USART_CR3_WUFIE_Pos             (22U)
+#define USART_CR3_WUFIE_Msk             (0x1UL << USART_CR3_WUFIE_Pos)         /*!< 0x00400000 */
+#define USART_CR3_WUFIE                 USART_CR3_WUFIE_Msk                    /*!< Wake Up Interrupt Enable */
+#define USART_CR3_TXFTIE_Pos            (23U)
+#define USART_CR3_TXFTIE_Msk            (0x1UL << USART_CR3_TXFTIE_Pos)        /*!< 0x00800000 */
+#define USART_CR3_TXFTIE                USART_CR3_TXFTIE_Msk                   /*!< TXFIFO threshold interrupt enable */
+#define USART_CR3_TCBGTIE_Pos           (24U)
+#define USART_CR3_TCBGTIE_Msk           (0x1UL << USART_CR3_TCBGTIE_Pos)       /*!< 0x01000000 */
+#define USART_CR3_TCBGTIE               USART_CR3_TCBGTIE_Msk                  /*!< Transmission Complete before guard time, interrupt enable */
+#define USART_CR3_RXFTCFG_Pos           (25U)
+#define USART_CR3_RXFTCFG_Msk           (0x7UL << USART_CR3_RXFTCFG_Pos)       /*!< 0x0E000000 */
+#define USART_CR3_RXFTCFG               USART_CR3_RXFTCFG_Msk                  /*!< RXFTCFG [2:0]Receive FIFO threshold configuration */
+#define USART_CR3_RXFTCFG_0             (0x1UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x02000000 */
+#define USART_CR3_RXFTCFG_1             (0x2UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x04000000 */
+#define USART_CR3_RXFTCFG_2             (0x4UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x08000000 */
+#define USART_CR3_RXFTIE_Pos            (28U)
+#define USART_CR3_RXFTIE_Msk            (0x1UL << USART_CR3_RXFTIE_Pos)        /*!< 0x10000000 */
+#define USART_CR3_RXFTIE                USART_CR3_RXFTIE_Msk                   /*!< RXFIFO threshold interrupt enable */
+#define USART_CR3_TXFTCFG_Pos           (29U)
+#define USART_CR3_TXFTCFG_Msk           (0x7UL << USART_CR3_TXFTCFG_Pos)       /*!< 0xE0000000 */
+#define USART_CR3_TXFTCFG               USART_CR3_TXFTCFG_Msk                  /*!< TXFIFO [2:0] threshold configuration */
+#define USART_CR3_TXFTCFG_0             (0x1UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x20000000 */
+#define USART_CR3_TXFTCFG_1             (0x2UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x40000000 */
+#define USART_CR3_TXFTCFG_2             (0x4UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x80000000 */
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define USART_BRR_DIV_FRACTION_Pos      (0U)
+#define USART_BRR_DIV_FRACTION_Msk      (0xFUL << USART_BRR_DIV_FRACTION_Pos)  /*!< 0x0000000F */
+#define USART_BRR_DIV_FRACTION          USART_BRR_DIV_FRACTION_Msk             /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA_Pos      (4U)
+#define USART_BRR_DIV_MANTISSA_Msk      (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_MANTISSA          USART_BRR_DIV_MANTISSA_Msk             /*!< Mantissa of USARTDIV */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define USART_GTPR_PSC_Pos              (0U)
+#define USART_GTPR_PSC_Msk              (0xFFUL << USART_GTPR_PSC_Pos)         /*!< 0x000000FF */
+#define USART_GTPR_PSC                  USART_GTPR_PSC_Msk                     /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT_Pos               (8U)
+#define USART_GTPR_GT_Msk               (0xFFUL << USART_GTPR_GT_Pos)          /*!< 0x0000FF00 */
+#define USART_GTPR_GT                   USART_GTPR_GT_Msk                      /*!< GT[7:0] bits (Guard time value) */
+
+/*******************  Bit definition for USART_RTOR register  *****************/
+#define USART_RTOR_RTO_Pos              (0U)
+#define USART_RTOR_RTO_Msk              (0xFFFFFFUL << USART_RTOR_RTO_Pos)     /*!< 0x00FFFFFF */
+#define USART_RTOR_RTO                  USART_RTOR_RTO_Msk                     /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN_Pos             (24U)
+#define USART_RTOR_BLEN_Msk             (0xFFUL << USART_RTOR_BLEN_Pos)        /*!< 0xFF000000 */
+#define USART_RTOR_BLEN                 USART_RTOR_BLEN_Msk                    /*!< Block Length */
+
+/*******************  Bit definition for USART_RQR register  ******************/
+#define USART_RQR_ABRRQ_Pos             (0U)
+#define USART_RQR_ABRRQ_Msk             (0x1UL << USART_RQR_ABRRQ_Pos)         /*!< 0x00000001 */
+#define USART_RQR_ABRRQ                 USART_RQR_ABRRQ_Msk                    /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ_Pos             (1U)
+#define USART_RQR_SBKRQ_Msk             (0x1UL << USART_RQR_SBKRQ_Pos)         /*!< 0x00000002 */
+#define USART_RQR_SBKRQ                 USART_RQR_SBKRQ_Msk                    /*!< Send Break Request */
+#define USART_RQR_MMRQ_Pos              (2U)
+#define USART_RQR_MMRQ_Msk              (0x1UL << USART_RQR_MMRQ_Pos)          /*!< 0x00000004 */
+#define USART_RQR_MMRQ                  USART_RQR_MMRQ_Msk                     /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ_Pos             (3U)
+#define USART_RQR_RXFRQ_Msk             (0x1UL << USART_RQR_RXFRQ_Pos)         /*!< 0x00000008 */
+#define USART_RQR_RXFRQ                 USART_RQR_RXFRQ_Msk                    /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ_Pos             (4U)
+#define USART_RQR_TXFRQ_Msk             (0x1UL << USART_RQR_TXFRQ_Pos)         /*!< 0x00000010 */
+#define USART_RQR_TXFRQ                 USART_RQR_TXFRQ_Msk                    /*!< Transmit data flush Request */
+
+/*******************  Bit definition for USART_ISR register  ******************/
+#define USART_ISR_PE_Pos                (0U)
+#define USART_ISR_PE_Msk                (0x1UL << USART_ISR_PE_Pos)            /*!< 0x00000001 */
+#define USART_ISR_PE                    USART_ISR_PE_Msk                       /*!< Parity Error */
+#define USART_ISR_FE_Pos                (1U)
+#define USART_ISR_FE_Msk                (0x1UL << USART_ISR_FE_Pos)            /*!< 0x00000002 */
+#define USART_ISR_FE                    USART_ISR_FE_Msk                       /*!< Framing Error */
+#define USART_ISR_NE_Pos                (2U)
+#define USART_ISR_NE_Msk                (0x1UL << USART_ISR_NE_Pos)            /*!< 0x00000004 */
+#define USART_ISR_NE                    USART_ISR_NE_Msk                       /*!< Noise detected Flag */
+#define USART_ISR_ORE_Pos               (3U)
+#define USART_ISR_ORE_Msk               (0x1UL << USART_ISR_ORE_Pos)           /*!< 0x00000008 */
+#define USART_ISR_ORE                   USART_ISR_ORE_Msk                      /*!< OverRun Error */
+#define USART_ISR_IDLE_Pos              (4U)
+#define USART_ISR_IDLE_Msk              (0x1UL << USART_ISR_IDLE_Pos)          /*!< 0x00000010 */
+#define USART_ISR_IDLE                  USART_ISR_IDLE_Msk                     /*!< IDLE line detected */
+#define USART_ISR_RXNE_RXFNE_Pos        (5U)
+#define USART_ISR_RXNE_RXFNE_Msk        (0x1UL << USART_ISR_RXNE_RXFNE_Pos)    /*!< 0x00000020 */
+#define USART_ISR_RXNE_RXFNE            USART_ISR_RXNE_RXFNE_Msk               /*!< Read Data Register or RX FIFO Not Empty */
+#define USART_ISR_TC_Pos                (6U)
+#define USART_ISR_TC_Msk                (0x1UL << USART_ISR_TC_Pos)            /*!< 0x00000040 */
+#define USART_ISR_TC                    USART_ISR_TC_Msk                       /*!< Transmission Complete */
+#define USART_ISR_TXE_TXFNF_Pos         (7U)
+#define USART_ISR_TXE_TXFNF_Msk         (0x1UL << USART_ISR_TXE_TXFNF_Pos)     /*!< 0x00000080 */
+#define USART_ISR_TXE_TXFNF             USART_ISR_TXE_TXFNF_Msk                /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
+#define USART_ISR_LBDF_Pos              (8U)
+#define USART_ISR_LBDF_Msk              (0x1UL << USART_ISR_LBDF_Pos)          /*!< 0x00000100 */
+#define USART_ISR_LBDF                  USART_ISR_LBDF_Msk                     /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF_Pos             (9U)
+#define USART_ISR_CTSIF_Msk             (0x1UL << USART_ISR_CTSIF_Pos)         /*!< 0x00000200 */
+#define USART_ISR_CTSIF                 USART_ISR_CTSIF_Msk                    /*!< CTS interrupt flag */
+#define USART_ISR_CTS_Pos               (10U)
+#define USART_ISR_CTS_Msk               (0x1UL << USART_ISR_CTS_Pos)           /*!< 0x00000400 */
+#define USART_ISR_CTS                   USART_ISR_CTS_Msk                      /*!< CTS flag */
+#define USART_ISR_RTOF_Pos              (11U)
+#define USART_ISR_RTOF_Msk              (0x1UL << USART_ISR_RTOF_Pos)          /*!< 0x00000800 */
+#define USART_ISR_RTOF                  USART_ISR_RTOF_Msk                     /*!< Receiver Time Out */
+#define USART_ISR_EOBF_Pos              (12U)
+#define USART_ISR_EOBF_Msk              (0x1UL << USART_ISR_EOBF_Pos)          /*!< 0x00001000 */
+#define USART_ISR_EOBF                  USART_ISR_EOBF_Msk                     /*!< End Of Block Flag */
+#define USART_ISR_UDR_Pos               (13U)
+#define USART_ISR_UDR_Msk               (0x1UL << USART_ISR_UDR_Pos)           /*!< 0x00002000 */
+#define USART_ISR_UDR                   USART_ISR_UDR_Msk                      /*!< SPI slave underrun error flag */
+#define USART_ISR_ABRE_Pos              (14U)
+#define USART_ISR_ABRE_Msk              (0x1UL << USART_ISR_ABRE_Pos)          /*!< 0x00004000 */
+#define USART_ISR_ABRE                  USART_ISR_ABRE_Msk                     /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF_Pos              (15U)
+#define USART_ISR_ABRF_Msk              (0x1UL << USART_ISR_ABRF_Pos)          /*!< 0x00008000 */
+#define USART_ISR_ABRF                  USART_ISR_ABRF_Msk                     /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY_Pos              (16U)
+#define USART_ISR_BUSY_Msk              (0x1UL << USART_ISR_BUSY_Pos)          /*!< 0x00010000 */
+#define USART_ISR_BUSY                  USART_ISR_BUSY_Msk                     /*!< Busy Flag */
+#define USART_ISR_CMF_Pos               (17U)
+#define USART_ISR_CMF_Msk               (0x1UL << USART_ISR_CMF_Pos)           /*!< 0x00020000 */
+#define USART_ISR_CMF                   USART_ISR_CMF_Msk                      /*!< Character Match Flag */
+#define USART_ISR_SBKF_Pos              (18U)
+#define USART_ISR_SBKF_Msk              (0x1UL << USART_ISR_SBKF_Pos)          /*!< 0x00040000 */
+#define USART_ISR_SBKF                  USART_ISR_SBKF_Msk                     /*!< Send Break Flag */
+#define USART_ISR_RWU_Pos               (19U)
+#define USART_ISR_RWU_Msk               (0x1UL << USART_ISR_RWU_Pos)           /*!< 0x00080000 */
+#define USART_ISR_RWU                   USART_ISR_RWU_Msk                      /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF_Pos               (20U)
+#define USART_ISR_WUF_Msk               (0x1UL << USART_ISR_WUF_Pos)           /*!< 0x00100000 */
+#define USART_ISR_WUF                   USART_ISR_WUF_Msk                      /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK_Pos             (21U)
+#define USART_ISR_TEACK_Msk             (0x1UL << USART_ISR_TEACK_Pos)         /*!< 0x00200000 */
+#define USART_ISR_TEACK                 USART_ISR_TEACK_Msk                    /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK_Pos             (22U)
+#define USART_ISR_REACK_Msk             (0x1UL << USART_ISR_REACK_Pos)         /*!< 0x00400000 */
+#define USART_ISR_REACK                 USART_ISR_REACK_Msk                    /*!< Receive Enable Acknowledge Flag */
+#define USART_ISR_TXFE_Pos              (23U)
+#define USART_ISR_TXFE_Msk              (0x1UL << USART_ISR_TXFE_Pos)          /*!< 0x00800000 */
+#define USART_ISR_TXFE                  USART_ISR_TXFE_Msk                     /*!< TXFIFO Empty */
+#define USART_ISR_RXFF_Pos              (24U)
+#define USART_ISR_RXFF_Msk              (0x1UL << USART_ISR_RXFF_Pos)          /*!< 0x01000000 */
+#define USART_ISR_RXFF                  USART_ISR_RXFF_Msk                     /*!< RXFIFO Full Flag */
+#define USART_ISR_TCBGT_Pos             (25U)
+#define USART_ISR_TCBGT_Msk             (0x1UL << USART_ISR_TCBGT_Pos)         /*!< 0x02000000 */
+#define USART_ISR_TCBGT                 USART_ISR_TCBGT_Msk                    /*!< Transmission complete before guard time Flag */
+#define USART_ISR_RXFT_Pos              (26U)
+#define USART_ISR_RXFT_Msk              (0x1UL << USART_ISR_RXFT_Pos)          /*!< 0x04000000 */
+#define USART_ISR_RXFT                  USART_ISR_RXFT_Msk                     /*!< RXFIFO threshold Flag */
+#define USART_ISR_TXFT_Pos              (27U)
+#define USART_ISR_TXFT_Msk              (0x1UL << USART_ISR_TXFT_Pos)          /*!< 0x08000000 */
+#define USART_ISR_TXFT                  USART_ISR_TXFT_Msk                     /*!< TXFIFO threshold Flag */
+
+/*******************  Bit definition for USART_ICR register  ******************/
+#define USART_ICR_PECF_Pos              (0U)
+#define USART_ICR_PECF_Msk              (0x1UL << USART_ICR_PECF_Pos)          /*!< 0x00000001 */
+#define USART_ICR_PECF                  USART_ICR_PECF_Msk                     /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF_Pos              (1U)
+#define USART_ICR_FECF_Msk              (0x1UL << USART_ICR_FECF_Pos)          /*!< 0x00000002 */
+#define USART_ICR_FECF                  USART_ICR_FECF_Msk                     /*!< Framing Error Clear Flag */
+#define USART_ICR_NECF_Pos              (2U)
+#define USART_ICR_NECF_Msk              (0x1UL << USART_ICR_NECF_Pos)          /*!< 0x00000004 */
+#define USART_ICR_NECF                  USART_ICR_NECF_Msk                     /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF_Pos             (3U)
+#define USART_ICR_ORECF_Msk             (0x1UL << USART_ICR_ORECF_Pos)         /*!< 0x00000008 */
+#define USART_ICR_ORECF                 USART_ICR_ORECF_Msk                    /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF_Pos            (4U)
+#define USART_ICR_IDLECF_Msk            (0x1UL << USART_ICR_IDLECF_Pos)        /*!< 0x00000010 */
+#define USART_ICR_IDLECF                USART_ICR_IDLECF_Msk                   /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TXFECF_Pos            (5U)
+#define USART_ICR_TXFECF_Msk            (0x1UL << USART_ICR_TXFECF_Pos)        /*!< 0x00000020 */
+#define USART_ICR_TXFECF                USART_ICR_TXFECF_Msk                   /*!< TXFIFO empty clear flag */
+#define USART_ICR_TCCF_Pos              (6U)
+#define USART_ICR_TCCF_Msk              (0x1UL << USART_ICR_TCCF_Pos)          /*!< 0x00000040 */
+#define USART_ICR_TCCF                  USART_ICR_TCCF_Msk                     /*!< Transmission Complete Clear Flag */
+#define USART_ICR_TCBGTCF_Pos           (7U)
+#define USART_ICR_TCBGTCF_Msk           (0x1UL << USART_ICR_TCBGTCF_Pos)       /*!< 0x00000080 */
+#define USART_ICR_TCBGTCF               USART_ICR_TCBGTCF_Msk                  /*!< Transmission complete before guard time Clear Flag */
+#define USART_ICR_LBDCF_Pos             (8U)
+#define USART_ICR_LBDCF_Msk             (0x1UL << USART_ICR_LBDCF_Pos)         /*!< 0x00000100 */
+#define USART_ICR_LBDCF                 USART_ICR_LBDCF_Msk                    /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF_Pos             (9U)
+#define USART_ICR_CTSCF_Msk             (0x1UL << USART_ICR_CTSCF_Pos)         /*!< 0x00000200 */
+#define USART_ICR_CTSCF                 USART_ICR_CTSCF_Msk                    /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF_Pos             (11U)
+#define USART_ICR_RTOCF_Msk             (0x1UL << USART_ICR_RTOCF_Pos)         /*!< 0x00000800 */
+#define USART_ICR_RTOCF                 USART_ICR_RTOCF_Msk                    /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF_Pos             (12U)
+#define USART_ICR_EOBCF_Msk             (0x1UL << USART_ICR_EOBCF_Pos)         /*!< 0x00001000 */
+#define USART_ICR_EOBCF                 USART_ICR_EOBCF_Msk                    /*!< End Of Block Clear Flag */
+#define USART_ICR_UDRCF_Pos             (13U)
+#define USART_ICR_UDRCF_Msk             (0x1UL << USART_ICR_UDRCF_Pos)         /*!< 0x00002000 */
+#define USART_ICR_UDRCF                 USART_ICR_UDRCF_Msk                    /*!< SPI slave underrun clear flag */
+#define USART_ICR_CMCF_Pos              (17U)
+#define USART_ICR_CMCF_Msk              (0x1UL << USART_ICR_CMCF_Pos)          /*!< 0x00020000 */
+#define USART_ICR_CMCF                  USART_ICR_CMCF_Msk                     /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF_Pos              (20U)
+#define USART_ICR_WUCF_Msk              (0x1UL << USART_ICR_WUCF_Pos)          /*!< 0x00100000 */
+#define USART_ICR_WUCF                  USART_ICR_WUCF_Msk                     /*!< Wake Up from stop mode Clear Flag */
+
+/*******************  Bit definition for USART_RDR register  ******************/
+#define USART_RDR_RDR_Pos               (0U)
+#define USART_RDR_RDR_Msk               (0x1FFUL << USART_RDR_RDR_Pos)         /*!< 0x000001FF */
+#define USART_RDR_RDR                   USART_RDR_RDR_Msk                      /*!< RDR[8:0] bits (Receive Data value) */
+
+/*******************  Bit definition for USART_TDR register  ******************/
+#define USART_TDR_TDR_Pos               (0U)
+#define USART_TDR_TDR_Msk               (0x1FFUL << USART_TDR_TDR_Pos)         /*!< 0x000001FF */
+#define USART_TDR_TDR                   USART_TDR_TDR_Msk                      /*!< TDR[8:0] bits (Transmit Data value) */
+
+/*******************  Bit definition for USART_PRESC register  ******************/
+#define USART_PRESC_PRESCALER_Pos       (0U)
+#define USART_PRESC_PRESCALER_Msk       (0xFUL << USART_PRESC_PRESCALER_Pos)   /*!< 0x0000000F */
+#define USART_PRESC_PRESCALER           USART_PRESC_PRESCALER_Msk              /*!< PRESCALER[3:0] bits (Clock prescaler) */
+#define USART_PRESC_PRESCALER_0         (0x1UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000001 */
+#define USART_PRESC_PRESCALER_1         (0x2UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000002 */
+#define USART_PRESC_PRESCALER_2         (0x4UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000004 */
+#define USART_PRESC_PRESCALER_3         (0x8UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000008 */
+
+/******************************************************************************/
+/*                                                                            */
+/*           Single Wire Protocol Master Interface (SWPMI)                    */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for SWPMI_CR register   ********************/
+#define SWPMI_CR_RXDMA_Pos       (0U)
+#define SWPMI_CR_RXDMA_Msk       (0x1UL << SWPMI_CR_RXDMA_Pos)                 /*!< 0x00000001 */
+#define SWPMI_CR_RXDMA           SWPMI_CR_RXDMA_Msk                            /*!<Reception DMA enable                                 */
+#define SWPMI_CR_TXDMA_Pos       (1U)
+#define SWPMI_CR_TXDMA_Msk       (0x1UL << SWPMI_CR_TXDMA_Pos)                 /*!< 0x00000002 */
+#define SWPMI_CR_TXDMA           SWPMI_CR_TXDMA_Msk                            /*!<Transmission DMA enable                              */
+#define SWPMI_CR_RXMODE_Pos      (2U)
+#define SWPMI_CR_RXMODE_Msk      (0x1UL << SWPMI_CR_RXMODE_Pos)                /*!< 0x00000004 */
+#define SWPMI_CR_RXMODE          SWPMI_CR_RXMODE_Msk                           /*!<Reception buffering mode                             */
+#define SWPMI_CR_TXMODE_Pos      (3U)
+#define SWPMI_CR_TXMODE_Msk      (0x1UL << SWPMI_CR_TXMODE_Pos)                /*!< 0x00000008 */
+#define SWPMI_CR_TXMODE          SWPMI_CR_TXMODE_Msk                           /*!<Transmission buffering mode                          */
+#define SWPMI_CR_LPBK_Pos        (4U)
+#define SWPMI_CR_LPBK_Msk        (0x1UL << SWPMI_CR_LPBK_Pos)                  /*!< 0x00000010 */
+#define SWPMI_CR_LPBK            SWPMI_CR_LPBK_Msk                             /*!<Loopback mode enable                                 */
+#define SWPMI_CR_SWPACT_Pos      (5U)
+#define SWPMI_CR_SWPACT_Msk      (0x1UL << SWPMI_CR_SWPACT_Pos)                /*!< 0x00000020 */
+#define SWPMI_CR_SWPACT          SWPMI_CR_SWPACT_Msk                           /*!<Single wire protocol master interface activate       */
+#define SWPMI_CR_DEACT_Pos       (10U)
+#define SWPMI_CR_DEACT_Msk       (0x1UL << SWPMI_CR_DEACT_Pos)                 /*!< 0x00000400 */
+#define SWPMI_CR_DEACT           SWPMI_CR_DEACT_Msk                            /*!<Single wire protocol master interface deactivate     */
+#define SWPMI_CR_SWPEN_Pos       (11U)
+#define SWPMI_CR_SWPEN_Msk       (0x1UL << SWPMI_CR_SWPEN_Pos)                 /*!< 0x00000800 */
+#define SWPMI_CR_SWPEN           SWPMI_CR_SWPEN_Msk                            /*!<Single wire protocol master transceiver enable       */
+
+/*******************  Bit definition for SWPMI_BRR register  ********************/
+#define SWPMI_BRR_BR_Pos         (0U)
+#define SWPMI_BRR_BR_Msk         (0xFFUL << SWPMI_BRR_BR_Pos)                  /*!< 0x000000FF */
+#define SWPMI_BRR_BR             SWPMI_BRR_BR_Msk                              /*!<BR[7:0] bits (Bitrate prescaler) */
+
+/*******************  Bit definition for SWPMI_ISR register  ********************/
+#define SWPMI_ISR_RXBFF_Pos      (0U)
+#define SWPMI_ISR_RXBFF_Msk      (0x1UL << SWPMI_ISR_RXBFF_Pos)                /*!< 0x00000001 */
+#define SWPMI_ISR_RXBFF          SWPMI_ISR_RXBFF_Msk                           /*!<Receive buffer full flag        */
+#define SWPMI_ISR_TXBEF_Pos      (1U)
+#define SWPMI_ISR_TXBEF_Msk      (0x1UL << SWPMI_ISR_TXBEF_Pos)                /*!< 0x00000002 */
+#define SWPMI_ISR_TXBEF          SWPMI_ISR_TXBEF_Msk                           /*!<Transmit buffer empty flag      */
+#define SWPMI_ISR_RXBERF_Pos     (2U)
+#define SWPMI_ISR_RXBERF_Msk     (0x1UL << SWPMI_ISR_RXBERF_Pos)               /*!< 0x00000004 */
+#define SWPMI_ISR_RXBERF         SWPMI_ISR_RXBERF_Msk                          /*!<Receive CRC error flag          */
+#define SWPMI_ISR_RXOVRF_Pos     (3U)
+#define SWPMI_ISR_RXOVRF_Msk     (0x1UL << SWPMI_ISR_RXOVRF_Pos)               /*!< 0x00000008 */
+#define SWPMI_ISR_RXOVRF         SWPMI_ISR_RXOVRF_Msk                          /*!<Receive overrun error flag      */
+#define SWPMI_ISR_TXUNRF_Pos     (4U)
+#define SWPMI_ISR_TXUNRF_Msk     (0x1UL << SWPMI_ISR_TXUNRF_Pos)               /*!< 0x00000010 */
+#define SWPMI_ISR_TXUNRF         SWPMI_ISR_TXUNRF_Msk                          /*!<Transmit underrun error flag    */
+#define SWPMI_ISR_RXNE_Pos       (5U)
+#define SWPMI_ISR_RXNE_Msk       (0x1UL << SWPMI_ISR_RXNE_Pos)                 /*!< 0x00000020 */
+#define SWPMI_ISR_RXNE           SWPMI_ISR_RXNE_Msk                            /*!<Receive data register not empty */
+#define SWPMI_ISR_TXE_Pos        (6U)
+#define SWPMI_ISR_TXE_Msk        (0x1UL << SWPMI_ISR_TXE_Pos)                  /*!< 0x00000040 */
+#define SWPMI_ISR_TXE            SWPMI_ISR_TXE_Msk                             /*!<Transmit data register empty    */
+#define SWPMI_ISR_TCF_Pos        (7U)
+#define SWPMI_ISR_TCF_Msk        (0x1UL << SWPMI_ISR_TCF_Pos)                  /*!< 0x00000080 */
+#define SWPMI_ISR_TCF            SWPMI_ISR_TCF_Msk                             /*!<Transfer complete flag          */
+#define SWPMI_ISR_SRF_Pos        (8U)
+#define SWPMI_ISR_SRF_Msk        (0x1UL << SWPMI_ISR_SRF_Pos)                  /*!< 0x00000100 */
+#define SWPMI_ISR_SRF            SWPMI_ISR_SRF_Msk                             /*!<Slave resume flag               */
+#define SWPMI_ISR_SUSP_Pos       (9U)
+#define SWPMI_ISR_SUSP_Msk       (0x1UL << SWPMI_ISR_SUSP_Pos)                 /*!< 0x00000200 */
+#define SWPMI_ISR_SUSP           SWPMI_ISR_SUSP_Msk                            /*!<SUSPEND flag                    */
+#define SWPMI_ISR_DEACTF_Pos     (10U)
+#define SWPMI_ISR_DEACTF_Msk     (0x1UL << SWPMI_ISR_DEACTF_Pos)               /*!< 0x00000400 */
+#define SWPMI_ISR_DEACTF         SWPMI_ISR_DEACTF_Msk                          /*!<DEACTIVATED flag                */
+#define SWPMI_ISR_RDYF_Pos       (11U)
+#define SWPMI_ISR_RDYF_Msk       (0x1UL << SWPMI_ISR_RDYF_Pos)                 /*!< 0x00000800 */
+#define SWPMI_ISR_RDYF           SWPMI_ISR_RDYF_Msk                            /*!<Transceiver ready flag          */
+
+/*******************  Bit definition for SWPMI_ICR register  ********************/
+#define SWPMI_ICR_CRXBFF_Pos     (0U)
+#define SWPMI_ICR_CRXBFF_Msk     (0x1UL << SWPMI_ICR_CRXBFF_Pos)               /*!< 0x00000001 */
+#define SWPMI_ICR_CRXBFF         SWPMI_ICR_CRXBFF_Msk                          /*!<Clear receive buffer full flag       */
+#define SWPMI_ICR_CTXBEF_Pos     (1U)
+#define SWPMI_ICR_CTXBEF_Msk     (0x1UL << SWPMI_ICR_CTXBEF_Pos)               /*!< 0x00000002 */
+#define SWPMI_ICR_CTXBEF         SWPMI_ICR_CTXBEF_Msk                          /*!<Clear transmit buffer empty flag     */
+#define SWPMI_ICR_CRXBERF_Pos    (2U)
+#define SWPMI_ICR_CRXBERF_Msk    (0x1UL << SWPMI_ICR_CRXBERF_Pos)              /*!< 0x00000004 */
+#define SWPMI_ICR_CRXBERF        SWPMI_ICR_CRXBERF_Msk                         /*!<Clear receive CRC error flag         */
+#define SWPMI_ICR_CRXOVRF_Pos    (3U)
+#define SWPMI_ICR_CRXOVRF_Msk    (0x1UL << SWPMI_ICR_CRXOVRF_Pos)              /*!< 0x00000008 */
+#define SWPMI_ICR_CRXOVRF        SWPMI_ICR_CRXOVRF_Msk                         /*!<Clear receive overrun error flag     */
+#define SWPMI_ICR_CTXUNRF_Pos    (4U)
+#define SWPMI_ICR_CTXUNRF_Msk    (0x1UL << SWPMI_ICR_CTXUNRF_Pos)              /*!< 0x00000010 */
+#define SWPMI_ICR_CTXUNRF        SWPMI_ICR_CTXUNRF_Msk                         /*!<Clear transmit underrun error flag   */
+#define SWPMI_ICR_CTCF_Pos       (7U)
+#define SWPMI_ICR_CTCF_Msk       (0x1UL << SWPMI_ICR_CTCF_Pos)                 /*!< 0x00000080 */
+#define SWPMI_ICR_CTCF           SWPMI_ICR_CTCF_Msk                            /*!<Clear transfer complete flag         */
+#define SWPMI_ICR_CSRF_Pos       (8U)
+#define SWPMI_ICR_CSRF_Msk       (0x1UL << SWPMI_ICR_CSRF_Pos)                 /*!< 0x00000100 */
+#define SWPMI_ICR_CSRF           SWPMI_ICR_CSRF_Msk                            /*!<Clear slave resume flag              */
+#define SWPMI_ICR_CRDYF_Pos      (11U)
+#define SWPMI_ICR_CRDYF_Msk      (0x1UL << SWPMI_ICR_CRDYF_Pos)                /*!< 0x00000800 */
+#define SWPMI_ICR_CRDYF          SWPMI_ICR_CRDYF_Msk                           /*!<Clear transceiver ready flag         */
+
+/*******************  Bit definition for SWPMI_IER register  ********************/
+#define SWPMI_IER_RXBFIE_Pos     (0U)
+#define SWPMI_IER_RXBFIE_Msk     (0x1UL << SWPMI_IER_RXBFIE_Pos)               /*!< 0x00000001 */
+#define SWPMI_IER_RXBFIE         SWPMI_IER_RXBFIE_Msk                          /*!<Receive buffer full interrupt enable        */
+#define SWPMI_IER_TXBEIE_Pos     (1U)
+#define SWPMI_IER_TXBEIE_Msk     (0x1UL << SWPMI_IER_TXBEIE_Pos)               /*!< 0x00000002 */
+#define SWPMI_IER_TXBEIE         SWPMI_IER_TXBEIE_Msk                          /*!<Transmit buffer empty interrupt enable      */
+#define SWPMI_IER_RXBERIE_Pos    (2U)
+#define SWPMI_IER_RXBERIE_Msk    (0x1UL << SWPMI_IER_RXBERIE_Pos)              /*!< 0x00000004 */
+#define SWPMI_IER_RXBERIE        SWPMI_IER_RXBERIE_Msk                         /*!<Receive CRC error interrupt enable          */
+#define SWPMI_IER_RXOVRIE_Pos    (3U)
+#define SWPMI_IER_RXOVRIE_Msk    (0x1UL << SWPMI_IER_RXOVRIE_Pos)              /*!< 0x00000008 */
+#define SWPMI_IER_RXOVRIE        SWPMI_IER_RXOVRIE_Msk                         /*!<Receive overrun error interrupt enable      */
+#define SWPMI_IER_TXUNRIE_Pos    (4U)
+#define SWPMI_IER_TXUNRIE_Msk    (0x1UL << SWPMI_IER_TXUNRIE_Pos)              /*!< 0x00000010 */
+#define SWPMI_IER_TXUNRIE        SWPMI_IER_TXUNRIE_Msk                         /*!<Transmit underrun error interrupt enable    */
+#define SWPMI_IER_RIE_Pos        (5U)
+#define SWPMI_IER_RIE_Msk        (0x1UL << SWPMI_IER_RIE_Pos)                  /*!< 0x00000020 */
+#define SWPMI_IER_RIE            SWPMI_IER_RIE_Msk                             /*!<Receive interrupt enable                    */
+#define SWPMI_IER_TIE_Pos        (6U)
+#define SWPMI_IER_TIE_Msk        (0x1UL << SWPMI_IER_TIE_Pos)                  /*!< 0x00000040 */
+#define SWPMI_IER_TIE            SWPMI_IER_TIE_Msk                             /*!<Transmit interrupt enable                   */
+#define SWPMI_IER_TCIE_Pos       (7U)
+#define SWPMI_IER_TCIE_Msk       (0x1UL << SWPMI_IER_TCIE_Pos)                 /*!< 0x00000080 */
+#define SWPMI_IER_TCIE           SWPMI_IER_TCIE_Msk                            /*!<Transmit complete interrupt enable          */
+#define SWPMI_IER_SRIE_Pos       (8U)
+#define SWPMI_IER_SRIE_Msk       (0x1UL << SWPMI_IER_SRIE_Pos)                 /*!< 0x00000100 */
+#define SWPMI_IER_SRIE           SWPMI_IER_SRIE_Msk                            /*!<Slave resume interrupt enable               */
+#define SWPMI_IER_RDYIE_Pos      (11U)
+#define SWPMI_IER_RDYIE_Msk      (0x1UL << SWPMI_IER_RDYIE_Pos)                /*!< 0x00000800 */
+#define SWPMI_IER_RDYIE          SWPMI_IER_RDYIE_Msk                           /*!<Transceiver ready interrupt enable          */
+
+/*******************  Bit definition for SWPMI_RFL register  ********************/
+#define SWPMI_RFL_RFL_Pos        (0U)
+#define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */
+#define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */
+#define SWPMI_RFL_RFL_0_1        ((uint32_t)0x00000003)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
+
+/*******************  Bit definition for SWPMI_TDR register  ********************/
+#define SWPMI_TDR_TD_Pos         (0U)
+#define SWPMI_TDR_TD_Msk         (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos)            /*!< 0xFFFFFFFF */
+#define SWPMI_TDR_TD             SWPMI_TDR_TD_Msk                              /*!<Transmit Data Register         */
+
+/*******************  Bit definition for SWPMI_RDR register  ********************/
+#define SWPMI_RDR_RD_Pos         (0U)
+#define SWPMI_RDR_RD_Msk         (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos)            /*!< 0xFFFFFFFF */
+#define SWPMI_RDR_RD             SWPMI_RDR_RD_Msk                              /*!<Recive Data Register           */
+
+
+/*******************  Bit definition for SWPMI_OR register  ********************/
+#define SWPMI_OR_TBYP_Pos        (0U)
+#define SWPMI_OR_TBYP_Msk        (0x1UL << SWPMI_OR_TBYP_Pos)                  /*!< 0x00000001 */
+#define SWPMI_OR_TBYP            SWPMI_OR_TBYP_Msk                             /*!<SWP Transceiver Bypass */
+#define SWPMI_OR_CLASS_Pos       (1U)
+#define SWPMI_OR_CLASS_Msk       (0x1UL << SWPMI_OR_CLASS_Pos)                 /*!< 0x00000002 */
+#define SWPMI_OR_CLASS           SWPMI_OR_CLASS_Msk                            /*!<SWP CLASS selection */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Window WATCHDOG                                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define WWDG_CR_T_Pos           (0U)
+#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                      /*!< 0x0000007F */
+#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
+#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
+#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
+#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
+#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
+#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
+#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
+
+#define WWDG_CR_WDGA_Pos        (7U)
+#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                    /*!< 0x00000080 */
+#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define WWDG_CFR_W_Pos          (0U)
+#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                     /*!< 0x0000007F */
+#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
+#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
+#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
+#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
+#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
+#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
+#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
+
+#define WWDG_CFR_EWI_Pos        (9U)
+#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                    /*!< 0x00000200 */
+#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
+
+#define WWDG_CFR_WDGTB_Pos      (11U)
+#define WWDG_CFR_WDGTB_Msk      (0x7UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00003800 */
+#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[2:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000800 */
+#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00001000 */
+#define WWDG_CFR_WDGTB_2        (0x4UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00002000 */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define WWDG_SR_EWIF_Pos        (0U)
+#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                    /*!< 0x00000001 */
+#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                DBG                                         */
+/*                                                                            */
+/******************************************************************************/
+/*********************************  DEVICE ID  ********************************/
+#define STM32H7_DEV_ID           0x450UL
+
+/********************  Bit definition for DBGMCU_IDCODE register  *************/
+#define DBGMCU_IDCODE_DEV_ID_Pos          (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk          (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID              DBGMCU_IDCODE_DEV_ID_Msk
+#define DBGMCU_IDCODE_REV_ID_Pos          (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk          (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID              DBGMCU_IDCODE_REV_ID_Msk
+
+/********************  Bit definition for DBGMCU_CR register  *****************/
+#define DBGMCU_CR_DBG_SLEEPD1_Pos         (0U)
+#define DBGMCU_CR_DBG_SLEEPD1_Msk         (0x1UL << DBGMCU_CR_DBG_SLEEPD1_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEPD1             DBGMCU_CR_DBG_SLEEPD1_Msk
+#define DBGMCU_CR_DBG_STOPD1_Pos          (1U)
+#define DBGMCU_CR_DBG_STOPD1_Msk          (0x1UL << DBGMCU_CR_DBG_STOPD1_Pos)  /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOPD1              DBGMCU_CR_DBG_STOPD1_Msk
+#define DBGMCU_CR_DBG_STANDBYD1_Pos       (2U)
+#define DBGMCU_CR_DBG_STANDBYD1_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYD1_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBYD1           DBGMCU_CR_DBG_STANDBYD1_Msk
+#define DBGMCU_CR_DBG_STOPD3_Pos          (7U)
+#define DBGMCU_CR_DBG_STOPD3_Msk          (0x1UL << DBGMCU_CR_DBG_STOPD3_Pos)  /*!< 0x00000080 */
+#define DBGMCU_CR_DBG_STOPD3              DBGMCU_CR_DBG_STOPD3_Msk
+#define DBGMCU_CR_DBG_STANDBYD3_Pos       (8U)
+#define DBGMCU_CR_DBG_STANDBYD3_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYD3_Pos) /*!< 0x00000100 */
+#define DBGMCU_CR_DBG_STANDBYD3           DBGMCU_CR_DBG_STANDBYD3_Msk
+#define DBGMCU_CR_DBG_TRACECKEN_Pos       (20U)
+#define DBGMCU_CR_DBG_TRACECKEN_Msk       (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos) /*!< 0x00100000 */
+#define DBGMCU_CR_DBG_TRACECKEN           DBGMCU_CR_DBG_TRACECKEN_Msk
+#define DBGMCU_CR_DBG_CKD1EN_Pos          (21U)
+#define DBGMCU_CR_DBG_CKD1EN_Msk          (0x1UL << DBGMCU_CR_DBG_CKD1EN_Pos)  /*!< 0x00200000 */
+#define DBGMCU_CR_DBG_CKD1EN              DBGMCU_CR_DBG_CKD1EN_Msk
+#define DBGMCU_CR_DBG_CKD3EN_Pos          (22U)
+#define DBGMCU_CR_DBG_CKD3EN_Msk          (0x1UL << DBGMCU_CR_DBG_CKD3EN_Pos)  /*!< 0x00400000 */
+#define DBGMCU_CR_DBG_CKD3EN              DBGMCU_CR_DBG_CKD3EN_Msk
+#define DBGMCU_CR_DBG_TRGOEN_Pos          (28U)
+#define DBGMCU_CR_DBG_TRGOEN_Msk          (0x1UL << DBGMCU_CR_DBG_TRGOEN_Pos)  /*!< 0x10000000 */
+#define DBGMCU_CR_DBG_TRGOEN              DBGMCU_CR_DBG_TRGOEN_Msk
+
+/********************  Bit definition for APB3FZ1 register  ************/
+#define DBGMCU_APB3FZ1_DBG_WWDG1_Pos      (6U)
+#define DBGMCU_APB3FZ1_DBG_WWDG1_Msk      (0x1UL << DBGMCU_APB3FZ1_DBG_WWDG1_Pos) /*!< 0x00000040 */
+#define DBGMCU_APB3FZ1_DBG_WWDG1          DBGMCU_APB3FZ1_DBG_WWDG1_Msk
+/********************  Bit definition for APB1LFZ1 register  ************/
+#define DBGMCU_APB1LFZ1_DBG_TIM2_Pos      (0U)
+#define DBGMCU_APB1LFZ1_DBG_TIM2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1LFZ1_DBG_TIM2          DBGMCU_APB1LFZ1_DBG_TIM2_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM3_Pos      (1U)
+#define DBGMCU_APB1LFZ1_DBG_TIM3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB1LFZ1_DBG_TIM3          DBGMCU_APB1LFZ1_DBG_TIM3_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM4_Pos      (2U)
+#define DBGMCU_APB1LFZ1_DBG_TIM4_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB1LFZ1_DBG_TIM4          DBGMCU_APB1LFZ1_DBG_TIM4_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM5_Pos      (3U)
+#define DBGMCU_APB1LFZ1_DBG_TIM5_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_Pos) /*!< 0x00000008 */
+#define DBGMCU_APB1LFZ1_DBG_TIM5          DBGMCU_APB1LFZ1_DBG_TIM5_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM6_Pos      (4U)
+#define DBGMCU_APB1LFZ1_DBG_TIM6_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB1LFZ1_DBG_TIM6          DBGMCU_APB1LFZ1_DBG_TIM6_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM7_Pos      (5U)
+#define DBGMCU_APB1LFZ1_DBG_TIM7_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB1LFZ1_DBG_TIM7          DBGMCU_APB1LFZ1_DBG_TIM7_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM12_Pos     (6U)
+#define DBGMCU_APB1LFZ1_DBG_TIM12_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_Pos) /*!< 0x00000040 */
+#define DBGMCU_APB1LFZ1_DBG_TIM12         DBGMCU_APB1LFZ1_DBG_TIM12_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM13_Pos     (7U)
+#define DBGMCU_APB1LFZ1_DBG_TIM13_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_Pos) /*!< 0x00000080 */
+#define DBGMCU_APB1LFZ1_DBG_TIM13         DBGMCU_APB1LFZ1_DBG_TIM13_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM14_Pos     (8U)
+#define DBGMCU_APB1LFZ1_DBG_TIM14_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_Pos) /*!< 0x00000100 */
+#define DBGMCU_APB1LFZ1_DBG_TIM14         DBGMCU_APB1LFZ1_DBG_TIM14_Msk
+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos    (9U)
+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos) /*!< 0x00000200 */
+#define DBGMCU_APB1LFZ1_DBG_LPTIM1        DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk
+#define DBGMCU_APB1LFZ1_DBG_I2C1_Pos      (21U)
+#define DBGMCU_APB1LFZ1_DBG_I2C1_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1LFZ1_DBG_I2C1          DBGMCU_APB1LFZ1_DBG_I2C1_Msk
+#define DBGMCU_APB1LFZ1_DBG_I2C2_Pos      (22U)
+#define DBGMCU_APB1LFZ1_DBG_I2C2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1LFZ1_DBG_I2C2          DBGMCU_APB1LFZ1_DBG_I2C2_Msk
+#define DBGMCU_APB1LFZ1_DBG_I2C3_Pos      (23U)
+#define DBGMCU_APB1LFZ1_DBG_I2C3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_Pos) /*!< 0x00800000 */
+#define DBGMCU_APB1LFZ1_DBG_I2C3          DBGMCU_APB1LFZ1_DBG_I2C3_Msk
+
+/********************  Bit definition for APB1HFZ1 register  ************/
+#define DBGMCU_APB1HFZ1_DBG_FDCAN_Pos     (8U)
+#define DBGMCU_APB1HFZ1_DBG_FDCAN_Msk     (0x1UL << DBGMCU_APB1HFZ1_DBG_FDCAN_Pos) /*!< 0x00000100 */
+#define DBGMCU_APB1HFZ1_DBG_FDCAN         DBGMCU_APB1HFZ1_DBG_FDCAN_Msk
+/********************  Bit definition for APB2FZ1 register  ************/
+#define DBGMCU_APB2FZ1_DBG_TIM1_Pos       (0U)
+#define DBGMCU_APB2FZ1_DBG_TIM1_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB2FZ1_DBG_TIM1           DBGMCU_APB2FZ1_DBG_TIM1_Msk
+#define DBGMCU_APB2FZ1_DBG_TIM8_Pos       (1U)
+#define DBGMCU_APB2FZ1_DBG_TIM8_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB2FZ1_DBG_TIM8           DBGMCU_APB2FZ1_DBG_TIM8_Msk
+#define DBGMCU_APB2FZ1_DBG_TIM15_Pos      (16U)
+#define DBGMCU_APB2FZ1_DBG_TIM15_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_Pos) /*!< 0x00010000 */
+#define DBGMCU_APB2FZ1_DBG_TIM15          DBGMCU_APB2FZ1_DBG_TIM15_Msk
+#define DBGMCU_APB2FZ1_DBG_TIM16_Pos      (17U)
+#define DBGMCU_APB2FZ1_DBG_TIM16_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_Pos) /*!< 0x00020000 */
+#define DBGMCU_APB2FZ1_DBG_TIM16          DBGMCU_APB2FZ1_DBG_TIM16_Msk
+#define DBGMCU_APB2FZ1_DBG_TIM17_Pos      (18U)
+#define DBGMCU_APB2FZ1_DBG_TIM17_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_Pos) /*!< 0x00040000 */
+#define DBGMCU_APB2FZ1_DBG_TIM17          DBGMCU_APB2FZ1_DBG_TIM17_Msk
+#define DBGMCU_APB2FZ1_DBG_HRTIM_Pos      (29U)
+#define DBGMCU_APB2FZ1_DBG_HRTIM_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_HRTIM_Pos) /*!< 0x20000000 */
+#define DBGMCU_APB2FZ1_DBG_HRTIM          DBGMCU_APB2FZ1_DBG_HRTIM_Msk
+
+/********************  Bit definition for APB4FZ1 register  ************/
+#define DBGMCU_APB4FZ1_DBG_I2C4_Pos       (7U)
+#define DBGMCU_APB4FZ1_DBG_I2C4_Msk       (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_Pos) /*!< 0x00000080 */
+#define DBGMCU_APB4FZ1_DBG_I2C4           DBGMCU_APB4FZ1_DBG_I2C4_Msk
+#define DBGMCU_APB4FZ1_DBG_LPTIM2_Pos     (9U)
+#define DBGMCU_APB4FZ1_DBG_LPTIM2_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_Pos) /*!< 0x00000200 */
+#define DBGMCU_APB4FZ1_DBG_LPTIM2         DBGMCU_APB4FZ1_DBG_LPTIM2_Msk
+#define DBGMCU_APB4FZ1_DBG_LPTIM3_Pos     (10U)
+#define DBGMCU_APB4FZ1_DBG_LPTIM3_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB4FZ1_DBG_LPTIM3         DBGMCU_APB4FZ1_DBG_LPTIM3_Msk
+#define DBGMCU_APB4FZ1_DBG_LPTIM4_Pos     (11U)
+#define DBGMCU_APB4FZ1_DBG_LPTIM4_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM4_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB4FZ1_DBG_LPTIM4         DBGMCU_APB4FZ1_DBG_LPTIM4_Msk
+#define DBGMCU_APB4FZ1_DBG_LPTIM5_Pos     (12U)
+#define DBGMCU_APB4FZ1_DBG_LPTIM5_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM5_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB4FZ1_DBG_LPTIM5         DBGMCU_APB4FZ1_DBG_LPTIM5_Msk
+#define DBGMCU_APB4FZ1_DBG_RTC_Pos        (16U)
+#define DBGMCU_APB4FZ1_DBG_RTC_Msk        (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_Pos) /*!< 0x00010000 */
+#define DBGMCU_APB4FZ1_DBG_RTC            DBGMCU_APB4FZ1_DBG_RTC_Msk
+#define DBGMCU_APB4FZ1_DBG_IWDG1_Pos      (18U)
+#define DBGMCU_APB4FZ1_DBG_IWDG1_Msk      (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG1_Pos) /*!< 0x00040000 */
+#define DBGMCU_APB4FZ1_DBG_IWDG1          DBGMCU_APB4FZ1_DBG_IWDG1_Msk
+/******************************************************************************/
+/*                                                                            */
+/*                        High Resolution Timer (HRTIM)                       */
+/*                                                                            */
+/******************************************************************************/
+/******************** Master Timer control register ***************************/
+#define HRTIM_MCR_CK_PSC_Pos          (0U)
+#define HRTIM_MCR_CK_PSC_Msk          (0x7UL << HRTIM_MCR_CK_PSC_Pos)          /*!< 0x00000007 */
+#define HRTIM_MCR_CK_PSC              HRTIM_MCR_CK_PSC_Msk                     /*!< Prescaler mask */
+#define HRTIM_MCR_CK_PSC_0            (0x1UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000001 */
+#define HRTIM_MCR_CK_PSC_1            (0x2UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000002 */
+#define HRTIM_MCR_CK_PSC_2            (0x4UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000004 */
+
+#define HRTIM_MCR_CONT_Pos            (3U)
+#define HRTIM_MCR_CONT_Msk            (0x1UL << HRTIM_MCR_CONT_Pos)            /*!< 0x00000008 */
+#define HRTIM_MCR_CONT                HRTIM_MCR_CONT_Msk                       /*!< Continuous mode */
+#define HRTIM_MCR_RETRIG_Pos          (4U)
+#define HRTIM_MCR_RETRIG_Msk          (0x1UL << HRTIM_MCR_RETRIG_Pos)          /*!< 0x00000010 */
+#define HRTIM_MCR_RETRIG              HRTIM_MCR_RETRIG_Msk                     /*!< Rettrigreable mode */
+#define HRTIM_MCR_HALF_Pos            (5U)
+#define HRTIM_MCR_HALF_Msk            (0x1UL << HRTIM_MCR_HALF_Pos)            /*!< 0x00000020 */
+#define HRTIM_MCR_HALF                HRTIM_MCR_HALF_Msk                       /*!< Half mode */
+
+#define HRTIM_MCR_SYNC_IN_Pos         (8U)
+#define HRTIM_MCR_SYNC_IN_Msk         (0x3UL << HRTIM_MCR_SYNC_IN_Pos)         /*!< 0x00000300 */
+#define HRTIM_MCR_SYNC_IN             HRTIM_MCR_SYNC_IN_Msk                    /*!< Synchronization input master */
+#define HRTIM_MCR_SYNC_IN_0           (0x1UL << HRTIM_MCR_SYNC_IN_Pos)          /*!< 0x00000100 */
+#define HRTIM_MCR_SYNC_IN_1           (0x2UL << HRTIM_MCR_SYNC_IN_Pos)          /*!< 0x00000200 */
+#define HRTIM_MCR_SYNCRSTM_Pos        (10U)
+#define HRTIM_MCR_SYNCRSTM_Msk        (0x1UL << HRTIM_MCR_SYNCRSTM_Pos)        /*!< 0x00000400 */
+#define HRTIM_MCR_SYNCRSTM            HRTIM_MCR_SYNCRSTM_Msk                   /*!< Synchronization reset master */
+#define HRTIM_MCR_SYNCSTRTM_Pos       (11U)
+#define HRTIM_MCR_SYNCSTRTM_Msk       (0x1UL << HRTIM_MCR_SYNCSTRTM_Pos)       /*!< 0x00000800 */
+#define HRTIM_MCR_SYNCSTRTM           HRTIM_MCR_SYNCSTRTM_Msk                  /*!< Synchronization start master */
+#define HRTIM_MCR_SYNC_OUT_Pos        (12U)
+#define HRTIM_MCR_SYNC_OUT_Msk        (0x3UL << HRTIM_MCR_SYNC_OUT_Pos)        /*!< 0x00003000 */
+#define HRTIM_MCR_SYNC_OUT            HRTIM_MCR_SYNC_OUT_Msk                   /*!< Synchronization output master */
+#define HRTIM_MCR_SYNC_OUT_0          (0x1UL << HRTIM_MCR_SYNC_OUT_Pos)         /*!< 0x00001000 */
+#define HRTIM_MCR_SYNC_OUT_1          (0x2UL << HRTIM_MCR_SYNC_OUT_Pos)         /*!< 0x00002000 */
+#define HRTIM_MCR_SYNC_SRC_Pos        (14U)
+#define HRTIM_MCR_SYNC_SRC_Msk        (0x3UL << HRTIM_MCR_SYNC_SRC_Pos)        /*!< 0x0000C000 */
+#define HRTIM_MCR_SYNC_SRC            HRTIM_MCR_SYNC_SRC_Msk                   /*!< Synchronization source */
+#define HRTIM_MCR_SYNC_SRC_0          (0x1UL << HRTIM_MCR_SYNC_SRC_Pos)         /*!< 0x00004000 */
+#define HRTIM_MCR_SYNC_SRC_1          (0x2UL << HRTIM_MCR_SYNC_SRC_Pos)         /*!< 0x00008000 */
+
+#define HRTIM_MCR_MCEN_Pos            (16U)
+#define HRTIM_MCR_MCEN_Msk            (0x1UL << HRTIM_MCR_MCEN_Pos)            /*!< 0x00010000 */
+#define HRTIM_MCR_MCEN                HRTIM_MCR_MCEN_Msk                       /*!< Master counter enable */
+#define HRTIM_MCR_TACEN_Pos           (17U)
+#define HRTIM_MCR_TACEN_Msk           (0x1UL << HRTIM_MCR_TACEN_Pos)           /*!< 0x00020000 */
+#define HRTIM_MCR_TACEN               HRTIM_MCR_TACEN_Msk                      /*!< Timer A counter enable */
+#define HRTIM_MCR_TBCEN_Pos           (18U)
+#define HRTIM_MCR_TBCEN_Msk           (0x1UL << HRTIM_MCR_TBCEN_Pos)           /*!< 0x00040000 */
+#define HRTIM_MCR_TBCEN               HRTIM_MCR_TBCEN_Msk                      /*!< Timer B counter enable */
+#define HRTIM_MCR_TCCEN_Pos           (19U)
+#define HRTIM_MCR_TCCEN_Msk           (0x1UL << HRTIM_MCR_TCCEN_Pos)           /*!< 0x00080000 */
+#define HRTIM_MCR_TCCEN               HRTIM_MCR_TCCEN_Msk                      /*!< Timer C counter enable */
+#define HRTIM_MCR_TDCEN_Pos           (20U)
+#define HRTIM_MCR_TDCEN_Msk           (0x1UL << HRTIM_MCR_TDCEN_Pos)           /*!< 0x00100000 */
+#define HRTIM_MCR_TDCEN               HRTIM_MCR_TDCEN_Msk                      /*!< Timer D counter enable */
+#define HRTIM_MCR_TECEN_Pos           (21U)
+#define HRTIM_MCR_TECEN_Msk           (0x1UL << HRTIM_MCR_TECEN_Pos)           /*!< 0x00200000 */
+#define HRTIM_MCR_TECEN               HRTIM_MCR_TECEN_Msk                      /*!< Timer E counter enable */
+
+#define HRTIM_MCR_DACSYNC_Pos         (25U)
+#define HRTIM_MCR_DACSYNC_Msk         (0x3UL << HRTIM_MCR_DACSYNC_Pos)         /*!< 0x06000000 */
+#define HRTIM_MCR_DACSYNC             HRTIM_MCR_DACSYNC_Msk                    /*!< DAC sychronization mask */
+#define HRTIM_MCR_DACSYNC_0           (0x1UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x02000000 */
+#define HRTIM_MCR_DACSYNC_1           (0x2UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x04000000 */
+
+#define HRTIM_MCR_PREEN_Pos           (27U)
+#define HRTIM_MCR_PREEN_Msk           (0x1UL << HRTIM_MCR_PREEN_Pos)           /*!< 0x08000000 */
+#define HRTIM_MCR_PREEN               HRTIM_MCR_PREEN_Msk                      /*!< Master preload enable */
+#define HRTIM_MCR_MREPU_Pos           (29U)
+#define HRTIM_MCR_MREPU_Msk           (0x1UL << HRTIM_MCR_MREPU_Pos)           /*!< 0x20000000 */
+#define HRTIM_MCR_MREPU               HRTIM_MCR_MREPU_Msk                      /*!< Master repetition update */
+
+#define HRTIM_MCR_BRSTDMA_Pos         (30U)
+#define HRTIM_MCR_BRSTDMA_Msk         (0x3UL << HRTIM_MCR_BRSTDMA_Pos)         /*!< 0xC0000000 */
+#define HRTIM_MCR_BRSTDMA             HRTIM_MCR_BRSTDMA_Msk                    /*!< Burst DMA update */
+#define HRTIM_MCR_BRSTDMA_0           (0x1UL << HRTIM_MCR_BRSTDMA_Pos)          /*!< 0x40000000 */
+#define HRTIM_MCR_BRSTDMA_1           (0x2UL << HRTIM_MCR_BRSTDMA_Pos)          /*!< 0x80000000 */
+
+/******************** Master Timer Interrupt status register ******************/
+#define HRTIM_MISR_MCMP1_Pos          (0U)
+#define HRTIM_MISR_MCMP1_Msk          (0x1UL << HRTIM_MISR_MCMP1_Pos)          /*!< 0x00000001 */
+#define HRTIM_MISR_MCMP1              HRTIM_MISR_MCMP1_Msk                     /*!< Master compare 1 interrupt flag */
+#define HRTIM_MISR_MCMP2_Pos          (1U)
+#define HRTIM_MISR_MCMP2_Msk          (0x1UL << HRTIM_MISR_MCMP2_Pos)          /*!< 0x00000002 */
+#define HRTIM_MISR_MCMP2              HRTIM_MISR_MCMP2_Msk                     /*!< Master compare 2 interrupt flag */
+#define HRTIM_MISR_MCMP3_Pos          (2U)
+#define HRTIM_MISR_MCMP3_Msk          (0x1UL << HRTIM_MISR_MCMP3_Pos)          /*!< 0x00000004 */
+#define HRTIM_MISR_MCMP3              HRTIM_MISR_MCMP3_Msk                     /*!< Master compare 3 interrupt flag */
+#define HRTIM_MISR_MCMP4_Pos          (3U)
+#define HRTIM_MISR_MCMP4_Msk          (0x1UL << HRTIM_MISR_MCMP4_Pos)          /*!< 0x00000008 */
+#define HRTIM_MISR_MCMP4              HRTIM_MISR_MCMP4_Msk                     /*!< Master compare 4 interrupt flag */
+#define HRTIM_MISR_MREP_Pos           (4U)
+#define HRTIM_MISR_MREP_Msk           (0x1UL << HRTIM_MISR_MREP_Pos)           /*!< 0x00000010 */
+#define HRTIM_MISR_MREP               HRTIM_MISR_MREP_Msk                      /*!< Master Repetition interrupt flag */
+#define HRTIM_MISR_SYNC_Pos           (5U)
+#define HRTIM_MISR_SYNC_Msk           (0x1UL << HRTIM_MISR_SYNC_Pos)           /*!< 0x00000020 */
+#define HRTIM_MISR_SYNC               HRTIM_MISR_SYNC_Msk                      /*!< Synchronization input interrupt flag */
+#define HRTIM_MISR_MUPD_Pos           (6U)
+#define HRTIM_MISR_MUPD_Msk           (0x1UL << HRTIM_MISR_MUPD_Pos)           /*!< 0x00000040 */
+#define HRTIM_MISR_MUPD               HRTIM_MISR_MUPD_Msk                      /*!< Master update interrupt flag */
+
+/******************** Master Timer Interrupt clear register *******************/
+#define HRTIM_MICR_MCMP1_Pos          (0U)
+#define HRTIM_MICR_MCMP1_Msk          (0x1UL << HRTIM_MICR_MCMP1_Pos)          /*!< 0x00000001 */
+#define HRTIM_MICR_MCMP1              HRTIM_MICR_MCMP1_Msk                     /*!< Master compare 1 interrupt flag clear */
+#define HRTIM_MICR_MCMP2_Pos          (1U)
+#define HRTIM_MICR_MCMP2_Msk          (0x1UL << HRTIM_MICR_MCMP2_Pos)          /*!< 0x00000002 */
+#define HRTIM_MICR_MCMP2              HRTIM_MICR_MCMP2_Msk                     /*!< Master compare 2 interrupt flag clear */
+#define HRTIM_MICR_MCMP3_Pos          (2U)
+#define HRTIM_MICR_MCMP3_Msk          (0x1UL << HRTIM_MICR_MCMP3_Pos)          /*!< 0x00000004 */
+#define HRTIM_MICR_MCMP3              HRTIM_MICR_MCMP3_Msk                     /*!< Master compare 3 interrupt flag clear */
+#define HRTIM_MICR_MCMP4_Pos          (3U)
+#define HRTIM_MICR_MCMP4_Msk          (0x1UL << HRTIM_MICR_MCMP4_Pos)          /*!< 0x00000008 */
+#define HRTIM_MICR_MCMP4              HRTIM_MICR_MCMP4_Msk                     /*!< Master compare 4 interrupt flag clear */
+#define HRTIM_MICR_MREP_Pos           (4U)
+#define HRTIM_MICR_MREP_Msk           (0x1UL << HRTIM_MICR_MREP_Pos)           /*!< 0x00000010 */
+#define HRTIM_MICR_MREP               HRTIM_MICR_MREP_Msk                      /*!< Master Repetition interrupt flag clear */
+#define HRTIM_MICR_SYNC_Pos           (5U)
+#define HRTIM_MICR_SYNC_Msk           (0x1UL << HRTIM_MICR_SYNC_Pos)           /*!< 0x00000020 */
+#define HRTIM_MICR_SYNC               HRTIM_MICR_SYNC_Msk                      /*!< Synchronization input interrupt flag clear */
+#define HRTIM_MICR_MUPD_Pos           (6U)
+#define HRTIM_MICR_MUPD_Msk           (0x1UL << HRTIM_MICR_MUPD_Pos)           /*!< 0x00000040 */
+#define HRTIM_MICR_MUPD               HRTIM_MICR_MUPD_Msk                      /*!< Master update interrupt flag clear */
+
+/******************** Master Timer DMA/Interrupt enable register **************/
+#define HRTIM_MDIER_MCMP1IE_Pos       (0U)
+#define HRTIM_MDIER_MCMP1IE_Msk       (0x1UL << HRTIM_MDIER_MCMP1IE_Pos)       /*!< 0x00000001 */
+#define HRTIM_MDIER_MCMP1IE           HRTIM_MDIER_MCMP1IE_Msk                  /*!< Master compare 1 interrupt enable */
+#define HRTIM_MDIER_MCMP2IE_Pos       (1U)
+#define HRTIM_MDIER_MCMP2IE_Msk       (0x1UL << HRTIM_MDIER_MCMP2IE_Pos)       /*!< 0x00000002 */
+#define HRTIM_MDIER_MCMP2IE           HRTIM_MDIER_MCMP2IE_Msk                  /*!< Master compare 2 interrupt enable */
+#define HRTIM_MDIER_MCMP3IE_Pos       (2U)
+#define HRTIM_MDIER_MCMP3IE_Msk       (0x1UL << HRTIM_MDIER_MCMP3IE_Pos)       /*!< 0x00000004 */
+#define HRTIM_MDIER_MCMP3IE           HRTIM_MDIER_MCMP3IE_Msk                  /*!< Master compare 3 interrupt enable */
+#define HRTIM_MDIER_MCMP4IE_Pos       (3U)
+#define HRTIM_MDIER_MCMP4IE_Msk       (0x1UL << HRTIM_MDIER_MCMP4IE_Pos)       /*!< 0x00000008 */
+#define HRTIM_MDIER_MCMP4IE           HRTIM_MDIER_MCMP4IE_Msk                  /*!< Master compare 4 interrupt enable */
+#define HRTIM_MDIER_MREPIE_Pos        (4U)
+#define HRTIM_MDIER_MREPIE_Msk        (0x1UL << HRTIM_MDIER_MREPIE_Pos)        /*!< 0x00000010 */
+#define HRTIM_MDIER_MREPIE            HRTIM_MDIER_MREPIE_Msk                   /*!< Master Repetition interrupt enable */
+#define HRTIM_MDIER_SYNCIE_Pos        (5U)
+#define HRTIM_MDIER_SYNCIE_Msk        (0x1UL << HRTIM_MDIER_SYNCIE_Pos)        /*!< 0x00000020 */
+#define HRTIM_MDIER_SYNCIE            HRTIM_MDIER_SYNCIE_Msk                   /*!< Synchronization input interrupt enable */
+#define HRTIM_MDIER_MUPDIE_Pos        (6U)
+#define HRTIM_MDIER_MUPDIE_Msk        (0x1UL << HRTIM_MDIER_MUPDIE_Pos)        /*!< 0x00000040 */
+#define HRTIM_MDIER_MUPDIE            HRTIM_MDIER_MUPDIE_Msk                   /*!< Master update interrupt enable */
+
+#define HRTIM_MDIER_MCMP1DE_Pos       (16U)
+#define HRTIM_MDIER_MCMP1DE_Msk       (0x1UL << HRTIM_MDIER_MCMP1DE_Pos)       /*!< 0x00010000 */
+#define HRTIM_MDIER_MCMP1DE           HRTIM_MDIER_MCMP1DE_Msk                  /*!< Master compare 1 DMA enable */
+#define HRTIM_MDIER_MCMP2DE_Pos       (17U)
+#define HRTIM_MDIER_MCMP2DE_Msk       (0x1UL << HRTIM_MDIER_MCMP2DE_Pos)       /*!< 0x00020000 */
+#define HRTIM_MDIER_MCMP2DE           HRTIM_MDIER_MCMP2DE_Msk                  /*!< Master compare 2 DMA enable */
+#define HRTIM_MDIER_MCMP3DE_Pos       (18U)
+#define HRTIM_MDIER_MCMP3DE_Msk       (0x1UL << HRTIM_MDIER_MCMP3DE_Pos)       /*!< 0x00040000 */
+#define HRTIM_MDIER_MCMP3DE           HRTIM_MDIER_MCMP3DE_Msk                  /*!< Master compare 3 DMA enable */
+#define HRTIM_MDIER_MCMP4DE_Pos       (19U)
+#define HRTIM_MDIER_MCMP4DE_Msk       (0x1UL << HRTIM_MDIER_MCMP4DE_Pos)       /*!< 0x00080000 */
+#define HRTIM_MDIER_MCMP4DE           HRTIM_MDIER_MCMP4DE_Msk                  /*!< Master compare 4 DMA enable */
+#define HRTIM_MDIER_MREPDE_Pos        (20U)
+#define HRTIM_MDIER_MREPDE_Msk        (0x1UL << HRTIM_MDIER_MREPDE_Pos)        /*!< 0x00100000 */
+#define HRTIM_MDIER_MREPDE            HRTIM_MDIER_MREPDE_Msk                   /*!< Master Repetition DMA enable */
+#define HRTIM_MDIER_SYNCDE_Pos        (21U)
+#define HRTIM_MDIER_SYNCDE_Msk        (0x1UL << HRTIM_MDIER_SYNCDE_Pos)        /*!< 0x00200000 */
+#define HRTIM_MDIER_SYNCDE            HRTIM_MDIER_SYNCDE_Msk                   /*!< Synchronization input DMA enable */
+#define HRTIM_MDIER_MUPDDE_Pos        (22U)
+#define HRTIM_MDIER_MUPDDE_Msk        (0x1UL << HRTIM_MDIER_MUPDDE_Pos)        /*!< 0x00400000 */
+#define HRTIM_MDIER_MUPDDE            HRTIM_MDIER_MUPDDE_Msk                   /*!< Master update DMA enable */
+
+/*******************  Bit definition for HRTIM_MCNTR register  ****************/
+#define HRTIM_MCNTR_MCNTR_Pos         (0U)
+#define HRTIM_MCNTR_MCNTR_Msk         (0xFFFFUL << HRTIM_MCNTR_MCNTR_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_MCNTR_MCNTR             HRTIM_MCNTR_MCNTR_Msk                    /*!<Counter Value */
+
+/*******************  Bit definition for HRTIM_MPER register  *****************/
+#define HRTIM_MPER_MPER_Pos           (0U)
+#define HRTIM_MPER_MPER_Msk           (0xFFFFUL << HRTIM_MPER_MPER_Pos)        /*!< 0x0000FFFF */
+#define HRTIM_MPER_MPER               HRTIM_MPER_MPER_Msk                      /*!< Period Value */
+
+/*******************  Bit definition for HRTIM_MREP register  *****************/
+#define HRTIM_MREP_MREP_Pos           (0U)
+#define HRTIM_MREP_MREP_Msk           (0xFFUL << HRTIM_MREP_MREP_Pos)          /*!< 0x000000FF */
+#define HRTIM_MREP_MREP               HRTIM_MREP_MREP_Msk                      /*!<Repetition Value */
+
+/*******************  Bit definition for HRTIM_MCMP1R register  *****************/
+#define HRTIM_MCMP1R_MCMP1R_Pos       (0U)
+#define HRTIM_MCMP1R_MCMP1R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP1R_Pos)    /*!< 0x0000FFFF */
+#define HRTIM_MCMP1R_MCMP1R           HRTIM_MCMP1R_MCMP1R_Msk                  /*!<Compare Value */
+
+/*******************  Bit definition for HRTIM_MCMP2R register  *****************/
+#define HRTIM_MCMP1R_MCMP2R_Pos       (0U)
+#define HRTIM_MCMP1R_MCMP2R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP2R_Pos)    /*!< 0x0000FFFF */
+#define HRTIM_MCMP1R_MCMP2R           HRTIM_MCMP1R_MCMP2R_Msk                  /*!<Compare Value */
+
+/*******************  Bit definition for HRTIM_MCMP3R register  *****************/
+#define HRTIM_MCMP1R_MCMP3R_Pos       (0U)
+#define HRTIM_MCMP1R_MCMP3R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP3R_Pos)    /*!< 0x0000FFFF */
+#define HRTIM_MCMP1R_MCMP3R           HRTIM_MCMP1R_MCMP3R_Msk                  /*!<Compare Value */
+
+/*******************  Bit definition for HRTIM_MCMP4R register  *****************/
+#define HRTIM_MCMP1R_MCMP4R_Pos       (0U)
+#define HRTIM_MCMP1R_MCMP4R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP4R_Pos)    /*!< 0x0000FFFF */
+#define HRTIM_MCMP1R_MCMP4R           HRTIM_MCMP1R_MCMP4R_Msk                  /*!<Compare Value */
+
+/******************** Slave control register **********************************/
+#define HRTIM_TIMCR_CK_PSC_Pos        (0U)
+#define HRTIM_TIMCR_CK_PSC_Msk        (0x7UL << HRTIM_TIMCR_CK_PSC_Pos)        /*!< 0x00000007 */
+#define HRTIM_TIMCR_CK_PSC            HRTIM_TIMCR_CK_PSC_Msk                   /*!< Slave prescaler mask*/
+#define HRTIM_TIMCR_CK_PSC_0          (0x1UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000001 */
+#define HRTIM_TIMCR_CK_PSC_1          (0x2UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000002 */
+#define HRTIM_TIMCR_CK_PSC_2          (0x4UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000004 */
+
+#define HRTIM_TIMCR_CONT_Pos          (3U)
+#define HRTIM_TIMCR_CONT_Msk          (0x1UL << HRTIM_TIMCR_CONT_Pos)          /*!< 0x00000008 */
+#define HRTIM_TIMCR_CONT              HRTIM_TIMCR_CONT_Msk                     /*!< Slave continuous mode */
+#define HRTIM_TIMCR_RETRIG_Pos        (4U)
+#define HRTIM_TIMCR_RETRIG_Msk        (0x1UL << HRTIM_TIMCR_RETRIG_Pos)        /*!< 0x00000010 */
+#define HRTIM_TIMCR_RETRIG            HRTIM_TIMCR_RETRIG_Msk                   /*!< Slave Retrigreable mode */
+#define HRTIM_TIMCR_HALF_Pos          (5U)
+#define HRTIM_TIMCR_HALF_Msk          (0x1UL << HRTIM_TIMCR_HALF_Pos)          /*!< 0x00000020 */
+#define HRTIM_TIMCR_HALF              HRTIM_TIMCR_HALF_Msk                     /*!< Slave Half mode */
+#define HRTIM_TIMCR_PSHPLL_Pos        (6U)
+#define HRTIM_TIMCR_PSHPLL_Msk        (0x1UL << HRTIM_TIMCR_PSHPLL_Pos)        /*!< 0x00000040 */
+#define HRTIM_TIMCR_PSHPLL            HRTIM_TIMCR_PSHPLL_Msk                   /*!< Slave push-pull mode */
+
+#define HRTIM_TIMCR_SYNCRST_Pos       (10U)
+#define HRTIM_TIMCR_SYNCRST_Msk       (0x1UL << HRTIM_TIMCR_SYNCRST_Pos)       /*!< 0x00000400 */
+#define HRTIM_TIMCR_SYNCRST           HRTIM_TIMCR_SYNCRST_Msk                  /*!< Slave synchronization resets */
+#define HRTIM_TIMCR_SYNCSTRT_Pos      (11U)
+#define HRTIM_TIMCR_SYNCSTRT_Msk      (0x1UL << HRTIM_TIMCR_SYNCSTRT_Pos)      /*!< 0x00000800 */
+#define HRTIM_TIMCR_SYNCSTRT          HRTIM_TIMCR_SYNCSTRT_Msk                 /*!< Slave synchronization starts */
+
+#define HRTIM_TIMCR_DELCMP2_Pos       (12U)
+#define HRTIM_TIMCR_DELCMP2_Msk       (0x3UL << HRTIM_TIMCR_DELCMP2_Pos)       /*!< 0x00003000 */
+#define HRTIM_TIMCR_DELCMP2           HRTIM_TIMCR_DELCMP2_Msk                  /*!< Slave delayed compartor 2 mode mask */
+#define HRTIM_TIMCR_DELCMP2_0         (0x1UL << HRTIM_TIMCR_DELCMP2_Pos)        /*!< 0x00001000 */
+#define HRTIM_TIMCR_DELCMP2_1         (0x2UL << HRTIM_TIMCR_DELCMP2_Pos)        /*!< 0x00002000 */
+#define HRTIM_TIMCR_DELCMP4_Pos       (14U)
+#define HRTIM_TIMCR_DELCMP4_Msk       (0x3UL << HRTIM_TIMCR_DELCMP4_Pos)       /*!< 0x0000C000 */
+#define HRTIM_TIMCR_DELCMP4           HRTIM_TIMCR_DELCMP4_Msk                  /*!< Slave delayed compartor 4 mode mask */
+#define HRTIM_TIMCR_DELCMP4_0         (0x1UL << HRTIM_TIMCR_DELCMP4_Pos)        /*!< 0x00004000 */
+#define HRTIM_TIMCR_DELCMP4_1         (0x2UL << HRTIM_TIMCR_DELCMP4_Pos)        /*!< 0x00008000 */
+
+#define HRTIM_TIMCR_TREPU_Pos         (17U)
+#define HRTIM_TIMCR_TREPU_Msk         (0x1UL << HRTIM_TIMCR_TREPU_Pos)         /*!< 0x00020000 */
+#define HRTIM_TIMCR_TREPU             HRTIM_TIMCR_TREPU_Msk                    /*!< Slave repetition update */
+#define HRTIM_TIMCR_TRSTU_Pos         (18U)
+#define HRTIM_TIMCR_TRSTU_Msk         (0x1UL << HRTIM_TIMCR_TRSTU_Pos)         /*!< 0x00040000 */
+#define HRTIM_TIMCR_TRSTU             HRTIM_TIMCR_TRSTU_Msk                    /*!< Slave reset update */
+#define HRTIM_TIMCR_TAU_Pos           (19U)
+#define HRTIM_TIMCR_TAU_Msk           (0x1UL << HRTIM_TIMCR_TAU_Pos)           /*!< 0x00080000 */
+#define HRTIM_TIMCR_TAU               HRTIM_TIMCR_TAU_Msk                      /*!< Slave Timer A update reserved for TIM A */
+#define HRTIM_TIMCR_TBU_Pos           (20U)
+#define HRTIM_TIMCR_TBU_Msk           (0x1UL << HRTIM_TIMCR_TBU_Pos)           /*!< 0x00100000 */
+#define HRTIM_TIMCR_TBU               HRTIM_TIMCR_TBU_Msk                      /*!< Slave Timer B update reserved for TIM B */
+#define HRTIM_TIMCR_TCU_Pos           (21U)
+#define HRTIM_TIMCR_TCU_Msk           (0x1UL << HRTIM_TIMCR_TCU_Pos)           /*!< 0x00200000 */
+#define HRTIM_TIMCR_TCU               HRTIM_TIMCR_TCU_Msk                      /*!< Slave Timer C update reserved for TIM C */
+#define HRTIM_TIMCR_TDU_Pos           (22U)
+#define HRTIM_TIMCR_TDU_Msk           (0x1UL << HRTIM_TIMCR_TDU_Pos)           /*!< 0x00400000 */
+#define HRTIM_TIMCR_TDU               HRTIM_TIMCR_TDU_Msk                      /*!< Slave Timer D update reserved for TIM D */
+#define HRTIM_TIMCR_TEU_Pos           (23U)
+#define HRTIM_TIMCR_TEU_Msk           (0x1UL << HRTIM_TIMCR_TEU_Pos)           /*!< 0x00800000 */
+#define HRTIM_TIMCR_TEU               HRTIM_TIMCR_TEU_Msk                      /*!< Slave Timer E update reserved for TIM E */
+#define HRTIM_TIMCR_MSTU_Pos          (24U)
+#define HRTIM_TIMCR_MSTU_Msk          (0x1UL << HRTIM_TIMCR_MSTU_Pos)          /*!< 0x01000000 */
+#define HRTIM_TIMCR_MSTU              HRTIM_TIMCR_MSTU_Msk                     /*!< Master Update */
+
+#define HRTIM_TIMCR_DACSYNC_Pos       (25U)
+#define HRTIM_TIMCR_DACSYNC_Msk       (0x3UL << HRTIM_TIMCR_DACSYNC_Pos)       /*!< 0x06000000 */
+#define HRTIM_TIMCR_DACSYNC           HRTIM_TIMCR_DACSYNC_Msk                  /*!< DAC sychronization mask */
+#define HRTIM_TIMCR_DACSYNC_0         (0x1UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x02000000 */
+#define HRTIM_TIMCR_DACSYNC_1         (0x2UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x04000000 */
+#define HRTIM_TIMCR_PREEN_Pos         (27U)
+#define HRTIM_TIMCR_PREEN_Msk         (0x1UL << HRTIM_TIMCR_PREEN_Pos)         /*!< 0x08000000 */
+#define HRTIM_TIMCR_PREEN             HRTIM_TIMCR_PREEN_Msk                    /*!< Slave preload enable */
+
+#define HRTIM_TIMCR_UPDGAT_Pos        (28U)
+#define HRTIM_TIMCR_UPDGAT_Msk        (0xFUL << HRTIM_TIMCR_UPDGAT_Pos)        /*!< 0xF0000000 */
+#define HRTIM_TIMCR_UPDGAT            HRTIM_TIMCR_UPDGAT_Msk                   /*!< Slave update gating mask */
+#define HRTIM_TIMCR_UPDGAT_0          (0x1UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x10000000 */
+#define HRTIM_TIMCR_UPDGAT_1          (0x2UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x20000000 */
+#define HRTIM_TIMCR_UPDGAT_2          (0x4UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x40000000 */
+#define HRTIM_TIMCR_UPDGAT_3          (0x8UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x80000000 */
+
+/******************** Slave Interrupt status register **************************/
+#define HRTIM_TIMISR_CMP1_Pos         (0U)
+#define HRTIM_TIMISR_CMP1_Msk         (0x1UL << HRTIM_TIMISR_CMP1_Pos)         /*!< 0x00000001 */
+#define HRTIM_TIMISR_CMP1             HRTIM_TIMISR_CMP1_Msk                    /*!< Slave compare 1 interrupt flag */
+#define HRTIM_TIMISR_CMP2_Pos         (1U)
+#define HRTIM_TIMISR_CMP2_Msk         (0x1UL << HRTIM_TIMISR_CMP2_Pos)         /*!< 0x00000002 */
+#define HRTIM_TIMISR_CMP2             HRTIM_TIMISR_CMP2_Msk                    /*!< Slave compare 2 interrupt flag */
+#define HRTIM_TIMISR_CMP3_Pos         (2U)
+#define HRTIM_TIMISR_CMP3_Msk         (0x1UL << HRTIM_TIMISR_CMP3_Pos)         /*!< 0x00000004 */
+#define HRTIM_TIMISR_CMP3             HRTIM_TIMISR_CMP3_Msk                    /*!< Slave compare 3 interrupt flag */
+#define HRTIM_TIMISR_CMP4_Pos         (3U)
+#define HRTIM_TIMISR_CMP4_Msk         (0x1UL << HRTIM_TIMISR_CMP4_Pos)         /*!< 0x00000008 */
+#define HRTIM_TIMISR_CMP4             HRTIM_TIMISR_CMP4_Msk                    /*!< Slave compare 4 interrupt flag */
+#define HRTIM_TIMISR_REP_Pos          (4U)
+#define HRTIM_TIMISR_REP_Msk          (0x1UL << HRTIM_TIMISR_REP_Pos)          /*!< 0x00000010 */
+#define HRTIM_TIMISR_REP              HRTIM_TIMISR_REP_Msk                     /*!< Slave repetition interrupt flag */
+#define HRTIM_TIMISR_UPD_Pos          (6U)
+#define HRTIM_TIMISR_UPD_Msk          (0x1UL << HRTIM_TIMISR_UPD_Pos)          /*!< 0x00000040 */
+#define HRTIM_TIMISR_UPD              HRTIM_TIMISR_UPD_Msk                     /*!< Slave update interrupt flag */
+#define HRTIM_TIMISR_CPT1_Pos         (7U)
+#define HRTIM_TIMISR_CPT1_Msk         (0x1UL << HRTIM_TIMISR_CPT1_Pos)         /*!< 0x00000080 */
+#define HRTIM_TIMISR_CPT1             HRTIM_TIMISR_CPT1_Msk                    /*!< Slave capture 1 interrupt flag */
+#define HRTIM_TIMISR_CPT2_Pos         (8U)
+#define HRTIM_TIMISR_CPT2_Msk         (0x1UL << HRTIM_TIMISR_CPT2_Pos)         /*!< 0x00000100 */
+#define HRTIM_TIMISR_CPT2             HRTIM_TIMISR_CPT2_Msk                    /*!< Slave capture 2 interrupt flag */
+#define HRTIM_TIMISR_SET1_Pos         (9U)
+#define HRTIM_TIMISR_SET1_Msk         (0x1UL << HRTIM_TIMISR_SET1_Pos)         /*!< 0x00000200 */
+#define HRTIM_TIMISR_SET1             HRTIM_TIMISR_SET1_Msk                    /*!< Slave output 1 set interrupt flag */
+#define HRTIM_TIMISR_RST1_Pos         (10U)
+#define HRTIM_TIMISR_RST1_Msk         (0x1UL << HRTIM_TIMISR_RST1_Pos)         /*!< 0x00000400 */
+#define HRTIM_TIMISR_RST1             HRTIM_TIMISR_RST1_Msk                    /*!< Slave output 1 reset interrupt flag */
+#define HRTIM_TIMISR_SET2_Pos         (11U)
+#define HRTIM_TIMISR_SET2_Msk         (0x1UL << HRTIM_TIMISR_SET2_Pos)         /*!< 0x00000800 */
+#define HRTIM_TIMISR_SET2             HRTIM_TIMISR_SET2_Msk                    /*!< Slave output 2 set interrupt flag */
+#define HRTIM_TIMISR_RST2_Pos         (12U)
+#define HRTIM_TIMISR_RST2_Msk         (0x1UL << HRTIM_TIMISR_RST2_Pos)         /*!< 0x00001000 */
+#define HRTIM_TIMISR_RST2             HRTIM_TIMISR_RST2_Msk                    /*!< Slave output 2 reset interrupt flag */
+#define HRTIM_TIMISR_RST_Pos          (13U)
+#define HRTIM_TIMISR_RST_Msk          (0x1UL << HRTIM_TIMISR_RST_Pos)          /*!< 0x00002000 */
+#define HRTIM_TIMISR_RST              HRTIM_TIMISR_RST_Msk                     /*!< Slave reset interrupt flag */
+#define HRTIM_TIMISR_DLYPRT_Pos       (14U)
+#define HRTIM_TIMISR_DLYPRT_Msk       (0x1UL << HRTIM_TIMISR_DLYPRT_Pos)       /*!< 0x00004000 */
+#define HRTIM_TIMISR_DLYPRT           HRTIM_TIMISR_DLYPRT_Msk                  /*!< Slave output 1 delay protection interrupt flag */
+#define HRTIM_TIMISR_CPPSTAT_Pos      (16U)
+#define HRTIM_TIMISR_CPPSTAT_Msk      (0x1UL << HRTIM_TIMISR_CPPSTAT_Pos)      /*!< 0x00010000 */
+#define HRTIM_TIMISR_CPPSTAT          HRTIM_TIMISR_CPPSTAT_Msk                 /*!< Slave current push-pull flag */
+#define HRTIM_TIMISR_IPPSTAT_Pos      (17U)
+#define HRTIM_TIMISR_IPPSTAT_Msk      (0x1UL << HRTIM_TIMISR_IPPSTAT_Pos)      /*!< 0x00020000 */
+#define HRTIM_TIMISR_IPPSTAT          HRTIM_TIMISR_IPPSTAT_Msk                 /*!< Slave idle push-pull flag */
+#define HRTIM_TIMISR_O1STAT_Pos       (18U)
+#define HRTIM_TIMISR_O1STAT_Msk       (0x1UL << HRTIM_TIMISR_O1STAT_Pos)       /*!< 0x00040000 */
+#define HRTIM_TIMISR_O1STAT           HRTIM_TIMISR_O1STAT_Msk                  /*!< Slave output 1 state flag */
+#define HRTIM_TIMISR_O2STAT_Pos       (19U)
+#define HRTIM_TIMISR_O2STAT_Msk       (0x1UL << HRTIM_TIMISR_O2STAT_Pos)       /*!< 0x00080000 */
+#define HRTIM_TIMISR_O2STAT           HRTIM_TIMISR_O2STAT_Msk                  /*!< Slave output 2 state flag */
+#define HRTIM_TIMISR_O1CPY_Pos        (20U)
+#define HRTIM_TIMISR_O1CPY_Msk        (0x1UL << HRTIM_TIMISR_O1CPY_Pos)        /*!< 0x00100000 */
+#define HRTIM_TIMISR_O1CPY            HRTIM_TIMISR_O1CPY_Msk                   /*!< Slave output 1 copy flag */
+#define HRTIM_TIMISR_O2CPY_Pos        (21U)
+#define HRTIM_TIMISR_O2CPY_Msk        (0x1UL << HRTIM_TIMISR_O2CPY_Pos)        /*!< 0x00200000 */
+#define HRTIM_TIMISR_O2CPY            HRTIM_TIMISR_O2CPY_Msk                   /*!< Slave output 2 copy flag */
+
+/******************** Slave Interrupt clear register **************************/
+#define HRTIM_TIMICR_CMP1C_Pos        (0U)
+#define HRTIM_TIMICR_CMP1C_Msk        (0x1UL << HRTIM_TIMICR_CMP1C_Pos)        /*!< 0x00000001 */
+#define HRTIM_TIMICR_CMP1C            HRTIM_TIMICR_CMP1C_Msk                   /*!< Slave compare 1 clear flag */
+#define HRTIM_TIMICR_CMP2C_Pos        (1U)
+#define HRTIM_TIMICR_CMP2C_Msk        (0x1UL << HRTIM_TIMICR_CMP2C_Pos)        /*!< 0x00000002 */
+#define HRTIM_TIMICR_CMP2C            HRTIM_TIMICR_CMP2C_Msk                   /*!< Slave compare 2 clear flag */
+#define HRTIM_TIMICR_CMP3C_Pos        (2U)
+#define HRTIM_TIMICR_CMP3C_Msk        (0x1UL << HRTIM_TIMICR_CMP3C_Pos)        /*!< 0x00000004 */
+#define HRTIM_TIMICR_CMP3C            HRTIM_TIMICR_CMP3C_Msk                   /*!< Slave compare 3 clear flag */
+#define HRTIM_TIMICR_CMP4C_Pos        (3U)
+#define HRTIM_TIMICR_CMP4C_Msk        (0x1UL << HRTIM_TIMICR_CMP4C_Pos)        /*!< 0x00000008 */
+#define HRTIM_TIMICR_CMP4C            HRTIM_TIMICR_CMP4C_Msk                   /*!< Slave compare 4 clear flag */
+#define HRTIM_TIMICR_REPC_Pos         (4U)
+#define HRTIM_TIMICR_REPC_Msk         (0x1UL << HRTIM_TIMICR_REPC_Pos)         /*!< 0x00000010 */
+#define HRTIM_TIMICR_REPC             HRTIM_TIMICR_REPC_Msk                    /*!< Slave repetition clear flag */
+#define HRTIM_TIMICR_UPDC_Pos         (6U)
+#define HRTIM_TIMICR_UPDC_Msk         (0x1UL << HRTIM_TIMICR_UPDC_Pos)         /*!< 0x00000040 */
+#define HRTIM_TIMICR_UPDC             HRTIM_TIMICR_UPDC_Msk                    /*!< Slave update clear flag */
+#define HRTIM_TIMICR_CPT1C_Pos        (7U)
+#define HRTIM_TIMICR_CPT1C_Msk        (0x1UL << HRTIM_TIMICR_CPT1C_Pos)        /*!< 0x00000080 */
+#define HRTIM_TIMICR_CPT1C            HRTIM_TIMICR_CPT1C_Msk                   /*!< Slave capture 1 clear flag */
+#define HRTIM_TIMICR_CPT2C_Pos        (8U)
+#define HRTIM_TIMICR_CPT2C_Msk        (0x1UL << HRTIM_TIMICR_CPT2C_Pos)        /*!< 0x00000100 */
+#define HRTIM_TIMICR_CPT2C            HRTIM_TIMICR_CPT2C_Msk                   /*!< Slave capture 2 clear flag */
+#define HRTIM_TIMICR_SET1C_Pos        (9U)
+#define HRTIM_TIMICR_SET1C_Msk        (0x1UL << HRTIM_TIMICR_SET1C_Pos)        /*!< 0x00000200 */
+#define HRTIM_TIMICR_SET1C            HRTIM_TIMICR_SET1C_Msk                   /*!< Slave output 1 set clear flag */
+#define HRTIM_TIMICR_RST1C_Pos        (10U)
+#define HRTIM_TIMICR_RST1C_Msk        (0x1UL << HRTIM_TIMICR_RST1C_Pos)        /*!< 0x00000400 */
+#define HRTIM_TIMICR_RST1C            HRTIM_TIMICR_RST1C_Msk                   /*!< Slave output 1 reset clear flag */
+#define HRTIM_TIMICR_SET2C_Pos        (11U)
+#define HRTIM_TIMICR_SET2C_Msk        (0x1UL << HRTIM_TIMICR_SET2C_Pos)        /*!< 0x00000800 */
+#define HRTIM_TIMICR_SET2C            HRTIM_TIMICR_SET2C_Msk                   /*!< Slave output 2 set clear flag */
+#define HRTIM_TIMICR_RST2C_Pos        (12U)
+#define HRTIM_TIMICR_RST2C_Msk        (0x1UL << HRTIM_TIMICR_RST2C_Pos)        /*!< 0x00001000 */
+#define HRTIM_TIMICR_RST2C            HRTIM_TIMICR_RST2C_Msk                   /*!< Slave output 2 reset clear flag */
+#define HRTIM_TIMICR_RSTC_Pos         (13U)
+#define HRTIM_TIMICR_RSTC_Msk         (0x1UL << HRTIM_TIMICR_RSTC_Pos)         /*!< 0x00002000 */
+#define HRTIM_TIMICR_RSTC             HRTIM_TIMICR_RSTC_Msk                    /*!< Slave reset clear flag */
+#define HRTIM_TIMICR_DLYPRTC_Pos      (14U)
+#define HRTIM_TIMICR_DLYPRTC_Msk      (0x1UL << HRTIM_TIMICR_DLYPRTC_Pos)      /*!< 0x00004000 */
+#define HRTIM_TIMICR_DLYPRTC          HRTIM_TIMICR_DLYPRTC_Msk                 /*!< Slave output 1 delay protection clear flag */
+
+/******************** Slave DMA/Interrupt enable register *********************/
+#define HRTIM_TIMDIER_CMP1IE_Pos      (0U)
+#define HRTIM_TIMDIER_CMP1IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP1IE_Pos)      /*!< 0x00000001 */
+#define HRTIM_TIMDIER_CMP1IE          HRTIM_TIMDIER_CMP1IE_Msk                 /*!< Slave compare 1 interrupt enable */
+#define HRTIM_TIMDIER_CMP2IE_Pos      (1U)
+#define HRTIM_TIMDIER_CMP2IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP2IE_Pos)      /*!< 0x00000002 */
+#define HRTIM_TIMDIER_CMP2IE          HRTIM_TIMDIER_CMP2IE_Msk                 /*!< Slave compare 2 interrupt enable */
+#define HRTIM_TIMDIER_CMP3IE_Pos      (2U)
+#define HRTIM_TIMDIER_CMP3IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP3IE_Pos)      /*!< 0x00000004 */
+#define HRTIM_TIMDIER_CMP3IE          HRTIM_TIMDIER_CMP3IE_Msk                 /*!< Slave compare 3 interrupt enable */
+#define HRTIM_TIMDIER_CMP4IE_Pos      (3U)
+#define HRTIM_TIMDIER_CMP4IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP4IE_Pos)      /*!< 0x00000008 */
+#define HRTIM_TIMDIER_CMP4IE          HRTIM_TIMDIER_CMP4IE_Msk                 /*!< Slave compare 4 interrupt enable */
+#define HRTIM_TIMDIER_REPIE_Pos       (4U)
+#define HRTIM_TIMDIER_REPIE_Msk       (0x1UL << HRTIM_TIMDIER_REPIE_Pos)       /*!< 0x00000010 */
+#define HRTIM_TIMDIER_REPIE           HRTIM_TIMDIER_REPIE_Msk                  /*!< Slave repetition interrupt enable */
+#define HRTIM_TIMDIER_UPDIE_Pos       (6U)
+#define HRTIM_TIMDIER_UPDIE_Msk       (0x1UL << HRTIM_TIMDIER_UPDIE_Pos)       /*!< 0x00000040 */
+#define HRTIM_TIMDIER_UPDIE           HRTIM_TIMDIER_UPDIE_Msk                  /*!< Slave update interrupt enable */
+#define HRTIM_TIMDIER_CPT1IE_Pos      (7U)
+#define HRTIM_TIMDIER_CPT1IE_Msk      (0x1UL << HRTIM_TIMDIER_CPT1IE_Pos)      /*!< 0x00000080 */
+#define HRTIM_TIMDIER_CPT1IE          HRTIM_TIMDIER_CPT1IE_Msk                 /*!< Slave capture 1 interrupt enable */
+#define HRTIM_TIMDIER_CPT2IE_Pos      (8U)
+#define HRTIM_TIMDIER_CPT2IE_Msk      (0x1UL << HRTIM_TIMDIER_CPT2IE_Pos)      /*!< 0x00000100 */
+#define HRTIM_TIMDIER_CPT2IE          HRTIM_TIMDIER_CPT2IE_Msk                 /*!< Slave capture 2 interrupt enable */
+#define HRTIM_TIMDIER_SET1IE_Pos      (9U)
+#define HRTIM_TIMDIER_SET1IE_Msk      (0x1UL << HRTIM_TIMDIER_SET1IE_Pos)      /*!< 0x00000200 */
+#define HRTIM_TIMDIER_SET1IE          HRTIM_TIMDIER_SET1IE_Msk                 /*!< Slave output 1 set interrupt enable */
+#define HRTIM_TIMDIER_RST1IE_Pos      (10U)
+#define HRTIM_TIMDIER_RST1IE_Msk      (0x1UL << HRTIM_TIMDIER_RST1IE_Pos)      /*!< 0x00000400 */
+#define HRTIM_TIMDIER_RST1IE          HRTIM_TIMDIER_RST1IE_Msk                 /*!< Slave output 1 reset interrupt enable */
+#define HRTIM_TIMDIER_SET2IE_Pos      (11U)
+#define HRTIM_TIMDIER_SET2IE_Msk      (0x1UL << HRTIM_TIMDIER_SET2IE_Pos)      /*!< 0x00000800 */
+#define HRTIM_TIMDIER_SET2IE          HRTIM_TIMDIER_SET2IE_Msk                 /*!< Slave output 2 set interrupt enable */
+#define HRTIM_TIMDIER_RST2IE_Pos      (12U)
+#define HRTIM_TIMDIER_RST2IE_Msk      (0x1UL << HRTIM_TIMDIER_RST2IE_Pos)      /*!< 0x00001000 */
+#define HRTIM_TIMDIER_RST2IE          HRTIM_TIMDIER_RST2IE_Msk                 /*!< Slave output 2 reset interrupt enable */
+#define HRTIM_TIMDIER_RSTIE_Pos       (13U)
+#define HRTIM_TIMDIER_RSTIE_Msk       (0x1UL << HRTIM_TIMDIER_RSTIE_Pos)       /*!< 0x00002000 */
+#define HRTIM_TIMDIER_RSTIE           HRTIM_TIMDIER_RSTIE_Msk                  /*!< Slave reset interrupt enable */
+#define HRTIM_TIMDIER_DLYPRTIE_Pos    (14U)
+#define HRTIM_TIMDIER_DLYPRTIE_Msk    (0x1UL << HRTIM_TIMDIER_DLYPRTIE_Pos)    /*!< 0x00004000 */
+#define HRTIM_TIMDIER_DLYPRTIE        HRTIM_TIMDIER_DLYPRTIE_Msk               /*!< Slave delay protection interrupt enable */
+
+#define HRTIM_TIMDIER_CMP1DE_Pos      (16U)
+#define HRTIM_TIMDIER_CMP1DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP1DE_Pos)      /*!< 0x00010000 */
+#define HRTIM_TIMDIER_CMP1DE          HRTIM_TIMDIER_CMP1DE_Msk                 /*!< Slave compare 1 request enable */
+#define HRTIM_TIMDIER_CMP2DE_Pos      (17U)
+#define HRTIM_TIMDIER_CMP2DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP2DE_Pos)      /*!< 0x00020000 */
+#define HRTIM_TIMDIER_CMP2DE          HRTIM_TIMDIER_CMP2DE_Msk                 /*!< Slave compare 2 request enable */
+#define HRTIM_TIMDIER_CMP3DE_Pos      (18U)
+#define HRTIM_TIMDIER_CMP3DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP3DE_Pos)      /*!< 0x00040000 */
+#define HRTIM_TIMDIER_CMP3DE          HRTIM_TIMDIER_CMP3DE_Msk                 /*!< Slave compare 3 request enable */
+#define HRTIM_TIMDIER_CMP4DE_Pos      (19U)
+#define HRTIM_TIMDIER_CMP4DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP4DE_Pos)      /*!< 0x00080000 */
+#define HRTIM_TIMDIER_CMP4DE          HRTIM_TIMDIER_CMP4DE_Msk                 /*!< Slave compare 4 request enable */
+#define HRTIM_TIMDIER_REPDE_Pos       (20U)
+#define HRTIM_TIMDIER_REPDE_Msk       (0x1UL << HRTIM_TIMDIER_REPDE_Pos)       /*!< 0x00100000 */
+#define HRTIM_TIMDIER_REPDE           HRTIM_TIMDIER_REPDE_Msk                  /*!< Slave repetition request enable */
+#define HRTIM_TIMDIER_UPDDE_Pos       (22U)
+#define HRTIM_TIMDIER_UPDDE_Msk       (0x1UL << HRTIM_TIMDIER_UPDDE_Pos)       /*!< 0x00400000 */
+#define HRTIM_TIMDIER_UPDDE           HRTIM_TIMDIER_UPDDE_Msk                  /*!< Slave update request enable */
+#define HRTIM_TIMDIER_CPT1DE_Pos      (23U)
+#define HRTIM_TIMDIER_CPT1DE_Msk      (0x1UL << HRTIM_TIMDIER_CPT1DE_Pos)      /*!< 0x00800000 */
+#define HRTIM_TIMDIER_CPT1DE          HRTIM_TIMDIER_CPT1DE_Msk                 /*!< Slave capture 1 request enable */
+#define HRTIM_TIMDIER_CPT2DE_Pos      (24U)
+#define HRTIM_TIMDIER_CPT2DE_Msk      (0x1UL << HRTIM_TIMDIER_CPT2DE_Pos)      /*!< 0x01000000 */
+#define HRTIM_TIMDIER_CPT2DE          HRTIM_TIMDIER_CPT2DE_Msk                 /*!< Slave capture 2 request enable */
+#define HRTIM_TIMDIER_SET1DE_Pos      (25U)
+#define HRTIM_TIMDIER_SET1DE_Msk      (0x1UL << HRTIM_TIMDIER_SET1DE_Pos)      /*!< 0x02000000 */
+#define HRTIM_TIMDIER_SET1DE          HRTIM_TIMDIER_SET1DE_Msk                 /*!< Slave output 1 set request enable */
+#define HRTIM_TIMDIER_RST1DE_Pos      (26U)
+#define HRTIM_TIMDIER_RST1DE_Msk      (0x1UL << HRTIM_TIMDIER_RST1DE_Pos)      /*!< 0x04000000 */
+#define HRTIM_TIMDIER_RST1DE          HRTIM_TIMDIER_RST1DE_Msk                 /*!< Slave output 1 reset request enable */
+#define HRTIM_TIMDIER_SET2DE_Pos      (27U)
+#define HRTIM_TIMDIER_SET2DE_Msk      (0x1UL << HRTIM_TIMDIER_SET2DE_Pos)      /*!< 0x08000000 */
+#define HRTIM_TIMDIER_SET2DE          HRTIM_TIMDIER_SET2DE_Msk                 /*!< Slave output 2 set request enable */
+#define HRTIM_TIMDIER_RST2DE_Pos      (28U)
+#define HRTIM_TIMDIER_RST2DE_Msk      (0x1UL << HRTIM_TIMDIER_RST2DE_Pos)      /*!< 0x10000000 */
+#define HRTIM_TIMDIER_RST2DE          HRTIM_TIMDIER_RST2DE_Msk                 /*!< Slave output 2 reset request enable */
+#define HRTIM_TIMDIER_RSTDE_Pos       (29U)
+#define HRTIM_TIMDIER_RSTDE_Msk       (0x1UL << HRTIM_TIMDIER_RSTDE_Pos)       /*!< 0x20000000 */
+#define HRTIM_TIMDIER_RSTDE           HRTIM_TIMDIER_RSTDE_Msk                  /*!< Slave reset request enable */
+#define HRTIM_TIMDIER_DLYPRTDE_Pos    (30U)
+#define HRTIM_TIMDIER_DLYPRTDE_Msk    (0x1UL << HRTIM_TIMDIER_DLYPRTDE_Pos)    /*!< 0x40000000 */
+#define HRTIM_TIMDIER_DLYPRTDE        HRTIM_TIMDIER_DLYPRTDE_Msk               /*!< Slavedelay protection request enable */
+
+/******************  Bit definition for HRTIM_CNTR register  ****************/
+#define HRTIM_CNTR_CNTR_Pos           (0U)
+#define HRTIM_CNTR_CNTR_Msk           (0xFFFFUL << HRTIM_CNTR_CNTR_Pos)        /*!< 0x0000FFFF */
+#define HRTIM_CNTR_CNTR               HRTIM_CNTR_CNTR_Msk                      /*!< Counter Value */
+
+/*******************  Bit definition for HRTIM_PER register  *****************/
+#define HRTIM_PER_PER_Pos             (0U)
+#define HRTIM_PER_PER_Msk             (0xFFFFUL << HRTIM_PER_PER_Pos)          /*!< 0x0000FFFF */
+#define HRTIM_PER_PER                 HRTIM_PER_PER_Msk                        /*!< Period Value */
+
+/*******************  Bit definition for HRTIM_REP register  *****************/
+#define HRTIM_REP_REP_Pos             (0U)
+#define HRTIM_REP_REP_Msk             (0xFFUL << HRTIM_REP_REP_Pos)            /*!< 0x000000FF */
+#define HRTIM_REP_REP                 HRTIM_REP_REP_Msk                        /*!< Repetition Value */
+
+/*******************  Bit definition for HRTIM_CMP1R register  *****************/
+#define HRTIM_CMP1R_CMP1R_Pos         (0U)
+#define HRTIM_CMP1R_CMP1R_Msk         (0xFFFFUL << HRTIM_CMP1R_CMP1R_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_CMP1R_CMP1R             HRTIM_CMP1R_CMP1R_Msk                    /*!< Compare Value */
+
+/*******************  Bit definition for HRTIM_CMP1CR register  *****************/
+#define HRTIM_CMP1CR_CMP1CR_Pos       (0U)
+#define HRTIM_CMP1CR_CMP1CR_Msk       (0xFFFFFFFFUL << HRTIM_CMP1CR_CMP1CR_Pos) /*!< 0xFFFFFFFF */
+#define HRTIM_CMP1CR_CMP1CR           HRTIM_CMP1CR_CMP1CR_Msk                  /*!< Compare Value */
+
+/*******************  Bit definition for HRTIM_CMP2R register  *****************/
+#define HRTIM_CMP2R_CMP2R_Pos         (0U)
+#define HRTIM_CMP2R_CMP2R_Msk         (0xFFFFUL << HRTIM_CMP2R_CMP2R_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_CMP2R_CMP2R             HRTIM_CMP2R_CMP2R_Msk                    /*!< Compare Value */
+
+/*******************  Bit definition for HRTIM_CMP3R register  *****************/
+#define HRTIM_CMP3R_CMP3R_Pos         (0U)
+#define HRTIM_CMP3R_CMP3R_Msk         (0xFFFFUL << HRTIM_CMP3R_CMP3R_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_CMP3R_CMP3R             HRTIM_CMP3R_CMP3R_Msk                    /*!< Compare Value */
+
+/*******************  Bit definition for HRTIM_CMP4R register  *****************/
+#define HRTIM_CMP4R_CMP4R_Pos         (0U)
+#define HRTIM_CMP4R_CMP4R_Msk         (0xFFFFUL << HRTIM_CMP4R_CMP4R_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_CMP4R_CMP4R             HRTIM_CMP4R_CMP4R_Msk                    /*!< Compare Value */
+
+/*******************  Bit definition for HRTIM_CPT1R register  ****************/
+#define HRTIM_CPT1R_CPT1R_Pos         (0U)
+#define HRTIM_CPT1R_CPT1R_Msk         (0xFFFFUL << HRTIM_CPT1R_CPT1R_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_CPT1R_CPT1R             HRTIM_CPT1R_CPT1R_Msk                    /*!< Capture Value */
+
+/*******************  Bit definition for HRTIM_CPT2R register  ****************/
+#define HRTIM_CPT2R_CPT2R_Pos         (0U)
+#define HRTIM_CPT2R_CPT2R_Msk         (0xFFFFUL << HRTIM_CPT2R_CPT2R_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_CPT2R_CPT2R             HRTIM_CPT2R_CPT2R_Msk                    /*!< Capture Value */
+
+/******************** Bit definition for Slave Deadtime register **************/
+#define HRTIM_DTR_DTR_Pos             (0U)
+#define HRTIM_DTR_DTR_Msk             (0x1FFUL << HRTIM_DTR_DTR_Pos)           /*!< 0x000001FF */
+#define HRTIM_DTR_DTR                 HRTIM_DTR_DTR_Msk                        /*!< Dead time rising value */
+#define HRTIM_DTR_DTR_0               (0x001UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000001 */
+#define HRTIM_DTR_DTR_1               (0x002UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000002 */
+#define HRTIM_DTR_DTR_2               (0x004UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000004 */
+#define HRTIM_DTR_DTR_3               (0x008UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000008 */
+#define HRTIM_DTR_DTR_4               (0x010UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000010 */
+#define HRTIM_DTR_DTR_5               (0x020UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000020 */
+#define HRTIM_DTR_DTR_6               (0x040UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000040 */
+#define HRTIM_DTR_DTR_7               (0x080UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000080 */
+#define HRTIM_DTR_DTR_8               (0x100UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000100 */
+#define HRTIM_DTR_SDTR_Pos            (9U)
+#define HRTIM_DTR_SDTR_Msk            (0x1UL << HRTIM_DTR_SDTR_Pos)            /*!< 0x00000200 */
+#define HRTIM_DTR_SDTR                HRTIM_DTR_SDTR_Msk                       /*!< Sign dead time rising value */
+#define HRTIM_DTR_DTPRSC_Pos          (10U)
+#define HRTIM_DTR_DTPRSC_Msk          (0x7UL << HRTIM_DTR_DTPRSC_Pos)          /*!< 0x00001C00 */
+#define HRTIM_DTR_DTPRSC              HRTIM_DTR_DTPRSC_Msk                     /*!< Dead time prescaler */
+#define HRTIM_DTR_DTPRSC_0            (0x1UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00000400 */
+#define HRTIM_DTR_DTPRSC_1            (0x2UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00000800 */
+#define HRTIM_DTR_DTPRSC_2            (0x4UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00001000 */
+#define HRTIM_DTR_DTRSLK_Pos          (14U)
+#define HRTIM_DTR_DTRSLK_Msk          (0x1UL << HRTIM_DTR_DTRSLK_Pos)          /*!< 0x00004000 */
+#define HRTIM_DTR_DTRSLK              HRTIM_DTR_DTRSLK_Msk                     /*!< Dead time rising sign lock */
+#define HRTIM_DTR_DTRLK_Pos           (15U)
+#define HRTIM_DTR_DTRLK_Msk           (0x1UL << HRTIM_DTR_DTRLK_Pos)           /*!< 0x00008000 */
+#define HRTIM_DTR_DTRLK               HRTIM_DTR_DTRLK_Msk                      /*!< Dead time rising lock */
+#define HRTIM_DTR_DTF_Pos             (16U)
+#define HRTIM_DTR_DTF_Msk             (0x1FFUL << HRTIM_DTR_DTF_Pos)           /*!< 0x01FF0000 */
+#define HRTIM_DTR_DTF                 HRTIM_DTR_DTF_Msk                        /*!< Dead time falling value */
+#define HRTIM_DTR_DTF_0               (0x001UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00010000 */
+#define HRTIM_DTR_DTF_1               (0x002UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00020000 */
+#define HRTIM_DTR_DTF_2               (0x004UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00040000 */
+#define HRTIM_DTR_DTF_3               (0x008UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00080000 */
+#define HRTIM_DTR_DTF_4               (0x010UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00100000 */
+#define HRTIM_DTR_DTF_5               (0x020UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00200000 */
+#define HRTIM_DTR_DTF_6               (0x040UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00400000 */
+#define HRTIM_DTR_DTF_7               (0x080UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00800000 */
+#define HRTIM_DTR_DTF_8               (0x100UL << HRTIM_DTR_DTF_Pos)            /*!< 0x01000000 */
+#define HRTIM_DTR_SDTF_Pos            (25U)
+#define HRTIM_DTR_SDTF_Msk            (0x1UL << HRTIM_DTR_SDTF_Pos)            /*!< 0x02000000 */
+#define HRTIM_DTR_SDTF                HRTIM_DTR_SDTF_Msk                       /*!< Sign dead time falling value */
+#define HRTIM_DTR_DTFSLK_Pos          (30U)
+#define HRTIM_DTR_DTFSLK_Msk          (0x1UL << HRTIM_DTR_DTFSLK_Pos)          /*!< 0x40000000 */
+#define HRTIM_DTR_DTFSLK              HRTIM_DTR_DTFSLK_Msk                     /*!< Dead time falling sign lock */
+#define HRTIM_DTR_DTFLK_Pos           (31U)
+#define HRTIM_DTR_DTFLK_Msk           (0x1UL << HRTIM_DTR_DTFLK_Pos)           /*!< 0x80000000 */
+#define HRTIM_DTR_DTFLK               HRTIM_DTR_DTFLK_Msk                      /*!< Dead time falling lock */
+
+/**** Bit definition for Slave Output 1 set register **************************/
+#define HRTIM_SET1R_SST_Pos           (0U)
+#define HRTIM_SET1R_SST_Msk           (0x1UL << HRTIM_SET1R_SST_Pos)           /*!< 0x00000001 */
+#define HRTIM_SET1R_SST               HRTIM_SET1R_SST_Msk                      /*!< software set trigger */
+#define HRTIM_SET1R_RESYNC_Pos        (1U)
+#define HRTIM_SET1R_RESYNC_Msk        (0x1UL << HRTIM_SET1R_RESYNC_Pos)        /*!< 0x00000002 */
+#define HRTIM_SET1R_RESYNC            HRTIM_SET1R_RESYNC_Msk                   /*!< Timer A resynchronization */
+#define HRTIM_SET1R_PER_Pos           (2U)
+#define HRTIM_SET1R_PER_Msk           (0x1UL << HRTIM_SET1R_PER_Pos)           /*!< 0x00000004 */
+#define HRTIM_SET1R_PER               HRTIM_SET1R_PER_Msk                      /*!< Timer A period */
+#define HRTIM_SET1R_CMP1_Pos          (3U)
+#define HRTIM_SET1R_CMP1_Msk          (0x1UL << HRTIM_SET1R_CMP1_Pos)          /*!< 0x00000008 */
+#define HRTIM_SET1R_CMP1              HRTIM_SET1R_CMP1_Msk                     /*!< Timer A compare 1 */
+#define HRTIM_SET1R_CMP2_Pos          (4U)
+#define HRTIM_SET1R_CMP2_Msk          (0x1UL << HRTIM_SET1R_CMP2_Pos)          /*!< 0x00000010 */
+#define HRTIM_SET1R_CMP2              HRTIM_SET1R_CMP2_Msk                     /*!< Timer A compare 2 */
+#define HRTIM_SET1R_CMP3_Pos          (5U)
+#define HRTIM_SET1R_CMP3_Msk          (0x1UL << HRTIM_SET1R_CMP3_Pos)          /*!< 0x00000020 */
+#define HRTIM_SET1R_CMP3              HRTIM_SET1R_CMP3_Msk                     /*!< Timer A compare 3 */
+#define HRTIM_SET1R_CMP4_Pos          (6U)
+#define HRTIM_SET1R_CMP4_Msk          (0x1UL << HRTIM_SET1R_CMP4_Pos)          /*!< 0x00000040 */
+#define HRTIM_SET1R_CMP4              HRTIM_SET1R_CMP4_Msk                     /*!< Timer A compare 4 */
+
+#define HRTIM_SET1R_MSTPER_Pos        (7U)
+#define HRTIM_SET1R_MSTPER_Msk        (0x1UL << HRTIM_SET1R_MSTPER_Pos)        /*!< 0x00000080 */
+#define HRTIM_SET1R_MSTPER            HRTIM_SET1R_MSTPER_Msk                   /*!< Master period */
+#define HRTIM_SET1R_MSTCMP1_Pos       (8U)
+#define HRTIM_SET1R_MSTCMP1_Msk       (0x1UL << HRTIM_SET1R_MSTCMP1_Pos)       /*!< 0x00000100 */
+#define HRTIM_SET1R_MSTCMP1           HRTIM_SET1R_MSTCMP1_Msk                  /*!< Master compare 1 */
+#define HRTIM_SET1R_MSTCMP2_Pos       (9U)
+#define HRTIM_SET1R_MSTCMP2_Msk       (0x1UL << HRTIM_SET1R_MSTCMP2_Pos)       /*!< 0x00000200 */
+#define HRTIM_SET1R_MSTCMP2           HRTIM_SET1R_MSTCMP2_Msk                  /*!< Master compare 2 */
+#define HRTIM_SET1R_MSTCMP3_Pos       (10U)
+#define HRTIM_SET1R_MSTCMP3_Msk       (0x1UL << HRTIM_SET1R_MSTCMP3_Pos)       /*!< 0x00000400 */
+#define HRTIM_SET1R_MSTCMP3           HRTIM_SET1R_MSTCMP3_Msk                  /*!< Master compare 3 */
+#define HRTIM_SET1R_MSTCMP4_Pos       (11U)
+#define HRTIM_SET1R_MSTCMP4_Msk       (0x1UL << HRTIM_SET1R_MSTCMP4_Pos)       /*!< 0x00000800 */
+#define HRTIM_SET1R_MSTCMP4           HRTIM_SET1R_MSTCMP4_Msk                  /*!< Master compare 4 */
+
+#define HRTIM_SET1R_TIMEVNT1_Pos      (12U)
+#define HRTIM_SET1R_TIMEVNT1_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT1_Pos)      /*!< 0x00001000 */
+#define HRTIM_SET1R_TIMEVNT1          HRTIM_SET1R_TIMEVNT1_Msk                 /*!< Timer event 1 */
+#define HRTIM_SET1R_TIMEVNT2_Pos      (13U)
+#define HRTIM_SET1R_TIMEVNT2_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT2_Pos)      /*!< 0x00002000 */
+#define HRTIM_SET1R_TIMEVNT2          HRTIM_SET1R_TIMEVNT2_Msk                 /*!< Timer event 2 */
+#define HRTIM_SET1R_TIMEVNT3_Pos      (14U)
+#define HRTIM_SET1R_TIMEVNT3_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT3_Pos)      /*!< 0x00004000 */
+#define HRTIM_SET1R_TIMEVNT3          HRTIM_SET1R_TIMEVNT3_Msk                 /*!< Timer event 3 */
+#define HRTIM_SET1R_TIMEVNT4_Pos      (15U)
+#define HRTIM_SET1R_TIMEVNT4_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT4_Pos)      /*!< 0x00008000 */
+#define HRTIM_SET1R_TIMEVNT4          HRTIM_SET1R_TIMEVNT4_Msk                 /*!< Timer event 4 */
+#define HRTIM_SET1R_TIMEVNT5_Pos      (16U)
+#define HRTIM_SET1R_TIMEVNT5_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT5_Pos)      /*!< 0x00010000 */
+#define HRTIM_SET1R_TIMEVNT5          HRTIM_SET1R_TIMEVNT5_Msk                 /*!< Timer event 5 */
+#define HRTIM_SET1R_TIMEVNT6_Pos      (17U)
+#define HRTIM_SET1R_TIMEVNT6_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT6_Pos)      /*!< 0x00020000 */
+#define HRTIM_SET1R_TIMEVNT6          HRTIM_SET1R_TIMEVNT6_Msk                 /*!< Timer event 6 */
+#define HRTIM_SET1R_TIMEVNT7_Pos      (18U)
+#define HRTIM_SET1R_TIMEVNT7_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT7_Pos)      /*!< 0x00040000 */
+#define HRTIM_SET1R_TIMEVNT7          HRTIM_SET1R_TIMEVNT7_Msk                 /*!< Timer event 7 */
+#define HRTIM_SET1R_TIMEVNT8_Pos      (19U)
+#define HRTIM_SET1R_TIMEVNT8_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT8_Pos)      /*!< 0x00080000 */
+#define HRTIM_SET1R_TIMEVNT8          HRTIM_SET1R_TIMEVNT8_Msk                 /*!< Timer event 8 */
+#define HRTIM_SET1R_TIMEVNT9_Pos      (20U)
+#define HRTIM_SET1R_TIMEVNT9_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT9_Pos)      /*!< 0x00100000 */
+#define HRTIM_SET1R_TIMEVNT9          HRTIM_SET1R_TIMEVNT9_Msk                 /*!< Timer event 9 */
+
+#define HRTIM_SET1R_EXTVNT1_Pos       (21U)
+#define HRTIM_SET1R_EXTVNT1_Msk       (0x1UL << HRTIM_SET1R_EXTVNT1_Pos)       /*!< 0x00200000 */
+#define HRTIM_SET1R_EXTVNT1           HRTIM_SET1R_EXTVNT1_Msk                  /*!< External event 1 */
+#define HRTIM_SET1R_EXTVNT2_Pos       (22U)
+#define HRTIM_SET1R_EXTVNT2_Msk       (0x1UL << HRTIM_SET1R_EXTVNT2_Pos)       /*!< 0x00400000 */
+#define HRTIM_SET1R_EXTVNT2           HRTIM_SET1R_EXTVNT2_Msk                  /*!< External event 2 */
+#define HRTIM_SET1R_EXTVNT3_Pos       (23U)
+#define HRTIM_SET1R_EXTVNT3_Msk       (0x1UL << HRTIM_SET1R_EXTVNT3_Pos)       /*!< 0x00800000 */
+#define HRTIM_SET1R_EXTVNT3           HRTIM_SET1R_EXTVNT3_Msk                  /*!< External event 3 */
+#define HRTIM_SET1R_EXTVNT4_Pos       (24U)
+#define HRTIM_SET1R_EXTVNT4_Msk       (0x1UL << HRTIM_SET1R_EXTVNT4_Pos)       /*!< 0x01000000 */
+#define HRTIM_SET1R_EXTVNT4           HRTIM_SET1R_EXTVNT4_Msk                  /*!< External event 4 */
+#define HRTIM_SET1R_EXTVNT5_Pos       (25U)
+#define HRTIM_SET1R_EXTVNT5_Msk       (0x1UL << HRTIM_SET1R_EXTVNT5_Pos)       /*!< 0x02000000 */
+#define HRTIM_SET1R_EXTVNT5           HRTIM_SET1R_EXTVNT5_Msk                  /*!< External event 5 */
+#define HRTIM_SET1R_EXTVNT6_Pos       (26U)
+#define HRTIM_SET1R_EXTVNT6_Msk       (0x1UL << HRTIM_SET1R_EXTVNT6_Pos)       /*!< 0x04000000 */
+#define HRTIM_SET1R_EXTVNT6           HRTIM_SET1R_EXTVNT6_Msk                  /*!< External event 6 */
+#define HRTIM_SET1R_EXTVNT7_Pos       (27U)
+#define HRTIM_SET1R_EXTVNT7_Msk       (0x1UL << HRTIM_SET1R_EXTVNT7_Pos)       /*!< 0x08000000 */
+#define HRTIM_SET1R_EXTVNT7           HRTIM_SET1R_EXTVNT7_Msk                  /*!< External event 7 */
+#define HRTIM_SET1R_EXTVNT8_Pos       (28U)
+#define HRTIM_SET1R_EXTVNT8_Msk       (0x1UL << HRTIM_SET1R_EXTVNT8_Pos)       /*!< 0x10000000 */
+#define HRTIM_SET1R_EXTVNT8           HRTIM_SET1R_EXTVNT8_Msk                  /*!< External event 8 */
+#define HRTIM_SET1R_EXTVNT9_Pos       (29U)
+#define HRTIM_SET1R_EXTVNT9_Msk       (0x1UL << HRTIM_SET1R_EXTVNT9_Pos)       /*!< 0x20000000 */
+#define HRTIM_SET1R_EXTVNT9           HRTIM_SET1R_EXTVNT9_Msk                  /*!< External event 9 */
+#define HRTIM_SET1R_EXTVNT10_Pos      (30U)
+#define HRTIM_SET1R_EXTVNT10_Msk      (0x1UL << HRTIM_SET1R_EXTVNT10_Pos)      /*!< 0x40000000 */
+#define HRTIM_SET1R_EXTVNT10          HRTIM_SET1R_EXTVNT10_Msk                 /*!< External event 10 */
+
+#define HRTIM_SET1R_UPDATE_Pos        (31U)
+#define HRTIM_SET1R_UPDATE_Msk        (0x1UL << HRTIM_SET1R_UPDATE_Pos)        /*!< 0x80000000 */
+#define HRTIM_SET1R_UPDATE            HRTIM_SET1R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */
+
+/**** Bit definition for Slave Output 1 reset register ************************/
+#define HRTIM_RST1R_SRT_Pos           (0U)
+#define HRTIM_RST1R_SRT_Msk           (0x1UL << HRTIM_RST1R_SRT_Pos)           /*!< 0x00000001 */
+#define HRTIM_RST1R_SRT               HRTIM_RST1R_SRT_Msk                      /*!< software reset trigger */
+#define HRTIM_RST1R_RESYNC_Pos        (1U)
+#define HRTIM_RST1R_RESYNC_Msk        (0x1UL << HRTIM_RST1R_RESYNC_Pos)        /*!< 0x00000002 */
+#define HRTIM_RST1R_RESYNC            HRTIM_RST1R_RESYNC_Msk                   /*!< Timer A resynchronization */
+#define HRTIM_RST1R_PER_Pos           (2U)
+#define HRTIM_RST1R_PER_Msk           (0x1UL << HRTIM_RST1R_PER_Pos)           /*!< 0x00000004 */
+#define HRTIM_RST1R_PER               HRTIM_RST1R_PER_Msk                      /*!< Timer A period */
+#define HRTIM_RST1R_CMP1_Pos          (3U)
+#define HRTIM_RST1R_CMP1_Msk          (0x1UL << HRTIM_RST1R_CMP1_Pos)          /*!< 0x00000008 */
+#define HRTIM_RST1R_CMP1              HRTIM_RST1R_CMP1_Msk                     /*!< Timer A compare 1 */
+#define HRTIM_RST1R_CMP2_Pos          (4U)
+#define HRTIM_RST1R_CMP2_Msk          (0x1UL << HRTIM_RST1R_CMP2_Pos)          /*!< 0x00000010 */
+#define HRTIM_RST1R_CMP2              HRTIM_RST1R_CMP2_Msk                     /*!< Timer A compare 2 */
+#define HRTIM_RST1R_CMP3_Pos          (5U)
+#define HRTIM_RST1R_CMP3_Msk          (0x1UL << HRTIM_RST1R_CMP3_Pos)          /*!< 0x00000020 */
+#define HRTIM_RST1R_CMP3              HRTIM_RST1R_CMP3_Msk                     /*!< Timer A compare 3 */
+#define HRTIM_RST1R_CMP4_Pos          (6U)
+#define HRTIM_RST1R_CMP4_Msk          (0x1UL << HRTIM_RST1R_CMP4_Pos)          /*!< 0x00000040 */
+#define HRTIM_RST1R_CMP4              HRTIM_RST1R_CMP4_Msk                     /*!< Timer A compare 4 */
+
+#define HRTIM_RST1R_MSTPER_Pos        (7U)
+#define HRTIM_RST1R_MSTPER_Msk        (0x1UL << HRTIM_RST1R_MSTPER_Pos)        /*!< 0x00000080 */
+#define HRTIM_RST1R_MSTPER            HRTIM_RST1R_MSTPER_Msk                   /*!< Master period */
+#define HRTIM_RST1R_MSTCMP1_Pos       (8U)
+#define HRTIM_RST1R_MSTCMP1_Msk       (0x1UL << HRTIM_RST1R_MSTCMP1_Pos)       /*!< 0x00000100 */
+#define HRTIM_RST1R_MSTCMP1           HRTIM_RST1R_MSTCMP1_Msk                  /*!< Master compare 1 */
+#define HRTIM_RST1R_MSTCMP2_Pos       (9U)
+#define HRTIM_RST1R_MSTCMP2_Msk       (0x1UL << HRTIM_RST1R_MSTCMP2_Pos)       /*!< 0x00000200 */
+#define HRTIM_RST1R_MSTCMP2           HRTIM_RST1R_MSTCMP2_Msk                  /*!< Master compare 2 */
+#define HRTIM_RST1R_MSTCMP3_Pos       (10U)
+#define HRTIM_RST1R_MSTCMP3_Msk       (0x1UL << HRTIM_RST1R_MSTCMP3_Pos)       /*!< 0x00000400 */
+#define HRTIM_RST1R_MSTCMP3           HRTIM_RST1R_MSTCMP3_Msk                  /*!< Master compare 3 */
+#define HRTIM_RST1R_MSTCMP4_Pos       (11U)
+#define HRTIM_RST1R_MSTCMP4_Msk       (0x1UL << HRTIM_RST1R_MSTCMP4_Pos)       /*!< 0x00000800 */
+#define HRTIM_RST1R_MSTCMP4           HRTIM_RST1R_MSTCMP4_Msk                  /*!< Master compare 4 */
+
+#define HRTIM_RST1R_TIMEVNT1_Pos      (12U)
+#define HRTIM_RST1R_TIMEVNT1_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT1_Pos)      /*!< 0x00001000 */
+#define HRTIM_RST1R_TIMEVNT1          HRTIM_RST1R_TIMEVNT1_Msk                 /*!< Timer event 1 */
+#define HRTIM_RST1R_TIMEVNT2_Pos      (13U)
+#define HRTIM_RST1R_TIMEVNT2_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT2_Pos)      /*!< 0x00002000 */
+#define HRTIM_RST1R_TIMEVNT2          HRTIM_RST1R_TIMEVNT2_Msk                 /*!< Timer event 2 */
+#define HRTIM_RST1R_TIMEVNT3_Pos      (14U)
+#define HRTIM_RST1R_TIMEVNT3_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT3_Pos)      /*!< 0x00004000 */
+#define HRTIM_RST1R_TIMEVNT3          HRTIM_RST1R_TIMEVNT3_Msk                 /*!< Timer event 3 */
+#define HRTIM_RST1R_TIMEVNT4_Pos      (15U)
+#define HRTIM_RST1R_TIMEVNT4_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT4_Pos)      /*!< 0x00008000 */
+#define HRTIM_RST1R_TIMEVNT4          HRTIM_RST1R_TIMEVNT4_Msk                 /*!< Timer event 4 */
+#define HRTIM_RST1R_TIMEVNT5_Pos      (16U)
+#define HRTIM_RST1R_TIMEVNT5_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT5_Pos)      /*!< 0x00010000 */
+#define HRTIM_RST1R_TIMEVNT5          HRTIM_RST1R_TIMEVNT5_Msk                 /*!< Timer event 5 */
+#define HRTIM_RST1R_TIMEVNT6_Pos      (17U)
+#define HRTIM_RST1R_TIMEVNT6_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT6_Pos)      /*!< 0x00020000 */
+#define HRTIM_RST1R_TIMEVNT6          HRTIM_RST1R_TIMEVNT6_Msk                 /*!< Timer event 6 */
+#define HRTIM_RST1R_TIMEVNT7_Pos      (18U)
+#define HRTIM_RST1R_TIMEVNT7_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT7_Pos)      /*!< 0x00040000 */
+#define HRTIM_RST1R_TIMEVNT7          HRTIM_RST1R_TIMEVNT7_Msk                 /*!< Timer event 7 */
+#define HRTIM_RST1R_TIMEVNT8_Pos      (19U)
+#define HRTIM_RST1R_TIMEVNT8_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT8_Pos)      /*!< 0x00080000 */
+#define HRTIM_RST1R_TIMEVNT8          HRTIM_RST1R_TIMEVNT8_Msk                 /*!< Timer event 8 */
+#define HRTIM_RST1R_TIMEVNT9_Pos      (20U)
+#define HRTIM_RST1R_TIMEVNT9_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT9_Pos)      /*!< 0x00100000 */
+#define HRTIM_RST1R_TIMEVNT9          HRTIM_RST1R_TIMEVNT9_Msk                 /*!< Timer event 9 */
+
+#define HRTIM_RST1R_EXTVNT1_Pos       (21U)
+#define HRTIM_RST1R_EXTVNT1_Msk       (0x1UL << HRTIM_RST1R_EXTVNT1_Pos)       /*!< 0x00200000 */
+#define HRTIM_RST1R_EXTVNT1           HRTIM_RST1R_EXTVNT1_Msk                  /*!< External event 1 */
+#define HRTIM_RST1R_EXTVNT2_Pos       (22U)
+#define HRTIM_RST1R_EXTVNT2_Msk       (0x1UL << HRTIM_RST1R_EXTVNT2_Pos)       /*!< 0x00400000 */
+#define HRTIM_RST1R_EXTVNT2           HRTIM_RST1R_EXTVNT2_Msk                  /*!< External event 2 */
+#define HRTIM_RST1R_EXTVNT3_Pos       (23U)
+#define HRTIM_RST1R_EXTVNT3_Msk       (0x1UL << HRTIM_RST1R_EXTVNT3_Pos)       /*!< 0x00800000 */
+#define HRTIM_RST1R_EXTVNT3           HRTIM_RST1R_EXTVNT3_Msk                  /*!< External event 3 */
+#define HRTIM_RST1R_EXTVNT4_Pos       (24U)
+#define HRTIM_RST1R_EXTVNT4_Msk       (0x1UL << HRTIM_RST1R_EXTVNT4_Pos)       /*!< 0x01000000 */
+#define HRTIM_RST1R_EXTVNT4           HRTIM_RST1R_EXTVNT4_Msk                  /*!< External event 4 */
+#define HRTIM_RST1R_EXTVNT5_Pos       (25U)
+#define HRTIM_RST1R_EXTVNT5_Msk       (0x1UL << HRTIM_RST1R_EXTVNT5_Pos)       /*!< 0x02000000 */
+#define HRTIM_RST1R_EXTVNT5           HRTIM_RST1R_EXTVNT5_Msk                  /*!< External event 5 */
+#define HRTIM_RST1R_EXTVNT6_Pos       (26U)
+#define HRTIM_RST1R_EXTVNT6_Msk       (0x1UL << HRTIM_RST1R_EXTVNT6_Pos)       /*!< 0x04000000 */
+#define HRTIM_RST1R_EXTVNT6           HRTIM_RST1R_EXTVNT6_Msk                  /*!< External event 6 */
+#define HRTIM_RST1R_EXTVNT7_Pos       (27U)
+#define HRTIM_RST1R_EXTVNT7_Msk       (0x1UL << HRTIM_RST1R_EXTVNT7_Pos)       /*!< 0x08000000 */
+#define HRTIM_RST1R_EXTVNT7           HRTIM_RST1R_EXTVNT7_Msk                  /*!< External event 7 */
+#define HRTIM_RST1R_EXTVNT8_Pos       (28U)
+#define HRTIM_RST1R_EXTVNT8_Msk       (0x1UL << HRTIM_RST1R_EXTVNT8_Pos)       /*!< 0x10000000 */
+#define HRTIM_RST1R_EXTVNT8           HRTIM_RST1R_EXTVNT8_Msk                  /*!< External event 8 */
+#define HRTIM_RST1R_EXTVNT9_Pos       (29U)
+#define HRTIM_RST1R_EXTVNT9_Msk       (0x1UL << HRTIM_RST1R_EXTVNT9_Pos)       /*!< 0x20000000 */
+#define HRTIM_RST1R_EXTVNT9           HRTIM_RST1R_EXTVNT9_Msk                  /*!< External event 9 */
+#define HRTIM_RST1R_EXTVNT10_Pos      (30U)
+#define HRTIM_RST1R_EXTVNT10_Msk      (0x1UL << HRTIM_RST1R_EXTVNT10_Pos)      /*!< 0x40000000 */
+#define HRTIM_RST1R_EXTVNT10          HRTIM_RST1R_EXTVNT10_Msk                 /*!< External event 10 */
+
+#define HRTIM_RST1R_UPDATE_Pos        (31U)
+#define HRTIM_RST1R_UPDATE_Msk        (0x1UL << HRTIM_RST1R_UPDATE_Pos)        /*!< 0x80000000 */
+#define HRTIM_RST1R_UPDATE            HRTIM_RST1R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */
+
+
+/**** Bit definition for Slave Output 2 set register **************************/
+#define HRTIM_SET2R_SST_Pos           (0U)
+#define HRTIM_SET2R_SST_Msk           (0x1UL << HRTIM_SET2R_SST_Pos)           /*!< 0x00000001 */
+#define HRTIM_SET2R_SST               HRTIM_SET2R_SST_Msk                      /*!< software set trigger */
+#define HRTIM_SET2R_RESYNC_Pos        (1U)
+#define HRTIM_SET2R_RESYNC_Msk        (0x1UL << HRTIM_SET2R_RESYNC_Pos)        /*!< 0x00000002 */
+#define HRTIM_SET2R_RESYNC            HRTIM_SET2R_RESYNC_Msk                   /*!< Timer A resynchronization */
+#define HRTIM_SET2R_PER_Pos           (2U)
+#define HRTIM_SET2R_PER_Msk           (0x1UL << HRTIM_SET2R_PER_Pos)           /*!< 0x00000004 */
+#define HRTIM_SET2R_PER               HRTIM_SET2R_PER_Msk                      /*!< Timer A period */
+#define HRTIM_SET2R_CMP1_Pos          (3U)
+#define HRTIM_SET2R_CMP1_Msk          (0x1UL << HRTIM_SET2R_CMP1_Pos)          /*!< 0x00000008 */
+#define HRTIM_SET2R_CMP1              HRTIM_SET2R_CMP1_Msk                     /*!< Timer A compare 1 */
+#define HRTIM_SET2R_CMP2_Pos          (4U)
+#define HRTIM_SET2R_CMP2_Msk          (0x1UL << HRTIM_SET2R_CMP2_Pos)          /*!< 0x00000010 */
+#define HRTIM_SET2R_CMP2              HRTIM_SET2R_CMP2_Msk                     /*!< Timer A compare 2 */
+#define HRTIM_SET2R_CMP3_Pos          (5U)
+#define HRTIM_SET2R_CMP3_Msk          (0x1UL << HRTIM_SET2R_CMP3_Pos)          /*!< 0x00000020 */
+#define HRTIM_SET2R_CMP3              HRTIM_SET2R_CMP3_Msk                     /*!< Timer A compare 3 */
+#define HRTIM_SET2R_CMP4_Pos          (6U)
+#define HRTIM_SET2R_CMP4_Msk          (0x1UL << HRTIM_SET2R_CMP4_Pos)          /*!< 0x00000040 */
+#define HRTIM_SET2R_CMP4              HRTIM_SET2R_CMP4_Msk                     /*!< Timer A compare 4 */
+
+#define HRTIM_SET2R_MSTPER_Pos        (7U)
+#define HRTIM_SET2R_MSTPER_Msk        (0x1UL << HRTIM_SET2R_MSTPER_Pos)        /*!< 0x00000080 */
+#define HRTIM_SET2R_MSTPER            HRTIM_SET2R_MSTPER_Msk                   /*!< Master period */
+#define HRTIM_SET2R_MSTCMP1_Pos       (8U)
+#define HRTIM_SET2R_MSTCMP1_Msk       (0x1UL << HRTIM_SET2R_MSTCMP1_Pos)       /*!< 0x00000100 */
+#define HRTIM_SET2R_MSTCMP1           HRTIM_SET2R_MSTCMP1_Msk                  /*!< Master compare 1 */
+#define HRTIM_SET2R_MSTCMP2_Pos       (9U)
+#define HRTIM_SET2R_MSTCMP2_Msk       (0x1UL << HRTIM_SET2R_MSTCMP2_Pos)       /*!< 0x00000200 */
+#define HRTIM_SET2R_MSTCMP2           HRTIM_SET2R_MSTCMP2_Msk                  /*!< Master compare 2 */
+#define HRTIM_SET2R_MSTCMP3_Pos       (10U)
+#define HRTIM_SET2R_MSTCMP3_Msk       (0x1UL << HRTIM_SET2R_MSTCMP3_Pos)       /*!< 0x00000400 */
+#define HRTIM_SET2R_MSTCMP3           HRTIM_SET2R_MSTCMP3_Msk                  /*!< Master compare 3 */
+#define HRTIM_SET2R_MSTCMP4_Pos       (11U)
+#define HRTIM_SET2R_MSTCMP4_Msk       (0x1UL << HRTIM_SET2R_MSTCMP4_Pos)       /*!< 0x00000800 */
+#define HRTIM_SET2R_MSTCMP4           HRTIM_SET2R_MSTCMP4_Msk                  /*!< Master compare 4 */
+
+#define HRTIM_SET2R_TIMEVNT1_Pos      (12U)
+#define HRTIM_SET2R_TIMEVNT1_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT1_Pos)      /*!< 0x00001000 */
+#define HRTIM_SET2R_TIMEVNT1          HRTIM_SET2R_TIMEVNT1_Msk                 /*!< Timer event 1 */
+#define HRTIM_SET2R_TIMEVNT2_Pos      (13U)
+#define HRTIM_SET2R_TIMEVNT2_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT2_Pos)      /*!< 0x00002000 */
+#define HRTIM_SET2R_TIMEVNT2          HRTIM_SET2R_TIMEVNT2_Msk                 /*!< Timer event 2 */
+#define HRTIM_SET2R_TIMEVNT3_Pos      (14U)
+#define HRTIM_SET2R_TIMEVNT3_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT3_Pos)      /*!< 0x00004000 */
+#define HRTIM_SET2R_TIMEVNT3          HRTIM_SET2R_TIMEVNT3_Msk                 /*!< Timer event 3 */
+#define HRTIM_SET2R_TIMEVNT4_Pos      (15U)
+#define HRTIM_SET2R_TIMEVNT4_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT4_Pos)      /*!< 0x00008000 */
+#define HRTIM_SET2R_TIMEVNT4          HRTIM_SET2R_TIMEVNT4_Msk                 /*!< Timer event 4 */
+#define HRTIM_SET2R_TIMEVNT5_Pos      (16U)
+#define HRTIM_SET2R_TIMEVNT5_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT5_Pos)      /*!< 0x00010000 */
+#define HRTIM_SET2R_TIMEVNT5          HRTIM_SET2R_TIMEVNT5_Msk                 /*!< Timer event 5 */
+#define HRTIM_SET2R_TIMEVNT6_Pos      (17U)
+#define HRTIM_SET2R_TIMEVNT6_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT6_Pos)      /*!< 0x00020000 */
+#define HRTIM_SET2R_TIMEVNT6          HRTIM_SET2R_TIMEVNT6_Msk                 /*!< Timer event 6 */
+#define HRTIM_SET2R_TIMEVNT7_Pos      (18U)
+#define HRTIM_SET2R_TIMEVNT7_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT7_Pos)      /*!< 0x00040000 */
+#define HRTIM_SET2R_TIMEVNT7          HRTIM_SET2R_TIMEVNT7_Msk                 /*!< Timer event 7 */
+#define HRTIM_SET2R_TIMEVNT8_Pos      (19U)
+#define HRTIM_SET2R_TIMEVNT8_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT8_Pos)      /*!< 0x00080000 */
+#define HRTIM_SET2R_TIMEVNT8          HRTIM_SET2R_TIMEVNT8_Msk                 /*!< Timer event 8 */
+#define HRTIM_SET2R_TIMEVNT9_Pos      (20U)
+#define HRTIM_SET2R_TIMEVNT9_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT9_Pos)      /*!< 0x00100000 */
+#define HRTIM_SET2R_TIMEVNT9          HRTIM_SET2R_TIMEVNT9_Msk                 /*!< Timer event 9 */
+
+#define HRTIM_SET2R_EXTVNT1_Pos       (21U)
+#define HRTIM_SET2R_EXTVNT1_Msk       (0x1UL << HRTIM_SET2R_EXTVNT1_Pos)       /*!< 0x00200000 */
+#define HRTIM_SET2R_EXTVNT1           HRTIM_SET2R_EXTVNT1_Msk                  /*!< External event 1 */
+#define HRTIM_SET2R_EXTVNT2_Pos       (22U)
+#define HRTIM_SET2R_EXTVNT2_Msk       (0x1UL << HRTIM_SET2R_EXTVNT2_Pos)       /*!< 0x00400000 */
+#define HRTIM_SET2R_EXTVNT2           HRTIM_SET2R_EXTVNT2_Msk                  /*!< External event 2 */
+#define HRTIM_SET2R_EXTVNT3_Pos       (23U)
+#define HRTIM_SET2R_EXTVNT3_Msk       (0x1UL << HRTIM_SET2R_EXTVNT3_Pos)       /*!< 0x00800000 */
+#define HRTIM_SET2R_EXTVNT3           HRTIM_SET2R_EXTVNT3_Msk                  /*!< External event 3 */
+#define HRTIM_SET2R_EXTVNT4_Pos       (24U)
+#define HRTIM_SET2R_EXTVNT4_Msk       (0x1UL << HRTIM_SET2R_EXTVNT4_Pos)       /*!< 0x01000000 */
+#define HRTIM_SET2R_EXTVNT4           HRTIM_SET2R_EXTVNT4_Msk                  /*!< External event 4 */
+#define HRTIM_SET2R_EXTVNT5_Pos       (25U)
+#define HRTIM_SET2R_EXTVNT5_Msk       (0x1UL << HRTIM_SET2R_EXTVNT5_Pos)       /*!< 0x02000000 */
+#define HRTIM_SET2R_EXTVNT5           HRTIM_SET2R_EXTVNT5_Msk                  /*!< External event 5 */
+#define HRTIM_SET2R_EXTVNT6_Pos       (26U)
+#define HRTIM_SET2R_EXTVNT6_Msk       (0x1UL << HRTIM_SET2R_EXTVNT6_Pos)       /*!< 0x04000000 */
+#define HRTIM_SET2R_EXTVNT6           HRTIM_SET2R_EXTVNT6_Msk                  /*!< External event 6 */
+#define HRTIM_SET2R_EXTVNT7_Pos       (27U)
+#define HRTIM_SET2R_EXTVNT7_Msk       (0x1UL << HRTIM_SET2R_EXTVNT7_Pos)       /*!< 0x08000000 */
+#define HRTIM_SET2R_EXTVNT7           HRTIM_SET2R_EXTVNT7_Msk                  /*!< External event 7 */
+#define HRTIM_SET2R_EXTVNT8_Pos       (28U)
+#define HRTIM_SET2R_EXTVNT8_Msk       (0x1UL << HRTIM_SET2R_EXTVNT8_Pos)       /*!< 0x10000000 */
+#define HRTIM_SET2R_EXTVNT8           HRTIM_SET2R_EXTVNT8_Msk                  /*!< External event 8 */
+#define HRTIM_SET2R_EXTVNT9_Pos       (29U)
+#define HRTIM_SET2R_EXTVNT9_Msk       (0x1UL << HRTIM_SET2R_EXTVNT9_Pos)       /*!< 0x20000000 */
+#define HRTIM_SET2R_EXTVNT9           HRTIM_SET2R_EXTVNT9_Msk                  /*!< External event 9 */
+#define HRTIM_SET2R_EXTVNT10_Pos      (30U)
+#define HRTIM_SET2R_EXTVNT10_Msk      (0x1UL << HRTIM_SET2R_EXTVNT10_Pos)      /*!< 0x40000000 */
+#define HRTIM_SET2R_EXTVNT10          HRTIM_SET2R_EXTVNT10_Msk                 /*!< External event 10 */
+
+#define HRTIM_SET2R_UPDATE_Pos        (31U)
+#define HRTIM_SET2R_UPDATE_Msk        (0x1UL << HRTIM_SET2R_UPDATE_Pos)        /*!< 0x80000000 */
+#define HRTIM_SET2R_UPDATE            HRTIM_SET2R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */
+
+/**** Bit definition for Slave Output 2 reset register ************************/
+#define HRTIM_RST2R_SRT_Pos           (0U)
+#define HRTIM_RST2R_SRT_Msk           (0x1UL << HRTIM_RST2R_SRT_Pos)           /*!< 0x00000001 */
+#define HRTIM_RST2R_SRT               HRTIM_RST2R_SRT_Msk                      /*!< software reset trigger */
+#define HRTIM_RST2R_RESYNC_Pos        (1U)
+#define HRTIM_RST2R_RESYNC_Msk        (0x1UL << HRTIM_RST2R_RESYNC_Pos)        /*!< 0x00000002 */
+#define HRTIM_RST2R_RESYNC            HRTIM_RST2R_RESYNC_Msk                   /*!< Timer A resynchronization */
+#define HRTIM_RST2R_PER_Pos           (2U)
+#define HRTIM_RST2R_PER_Msk           (0x1UL << HRTIM_RST2R_PER_Pos)           /*!< 0x00000004 */
+#define HRTIM_RST2R_PER               HRTIM_RST2R_PER_Msk                      /*!< Timer A period */
+#define HRTIM_RST2R_CMP1_Pos          (3U)
+#define HRTIM_RST2R_CMP1_Msk          (0x1UL << HRTIM_RST2R_CMP1_Pos)          /*!< 0x00000008 */
+#define HRTIM_RST2R_CMP1              HRTIM_RST2R_CMP1_Msk                     /*!< Timer A compare 1 */
+#define HRTIM_RST2R_CMP2_Pos          (4U)
+#define HRTIM_RST2R_CMP2_Msk          (0x1UL << HRTIM_RST2R_CMP2_Pos)          /*!< 0x00000010 */
+#define HRTIM_RST2R_CMP2              HRTIM_RST2R_CMP2_Msk                     /*!< Timer A compare 2 */
+#define HRTIM_RST2R_CMP3_Pos          (5U)
+#define HRTIM_RST2R_CMP3_Msk          (0x1UL << HRTIM_RST2R_CMP3_Pos)          /*!< 0x00000020 */
+#define HRTIM_RST2R_CMP3              HRTIM_RST2R_CMP3_Msk                     /*!< Timer A compare 3 */
+#define HRTIM_RST2R_CMP4_Pos          (6U)
+#define HRTIM_RST2R_CMP4_Msk          (0x1UL << HRTIM_RST2R_CMP4_Pos)          /*!< 0x00000040 */
+#define HRTIM_RST2R_CMP4              HRTIM_RST2R_CMP4_Msk                     /*!< Timer A compare 4 */
+
+#define HRTIM_RST2R_MSTPER_Pos        (7U)
+#define HRTIM_RST2R_MSTPER_Msk        (0x1UL << HRTIM_RST2R_MSTPER_Pos)        /*!< 0x00000080 */
+#define HRTIM_RST2R_MSTPER            HRTIM_RST2R_MSTPER_Msk                   /*!< Master period */
+#define HRTIM_RST2R_MSTCMP1_Pos       (8U)
+#define HRTIM_RST2R_MSTCMP1_Msk       (0x1UL << HRTIM_RST2R_MSTCMP1_Pos)       /*!< 0x00000100 */
+#define HRTIM_RST2R_MSTCMP1           HRTIM_RST2R_MSTCMP1_Msk                  /*!< Master compare 1 */
+#define HRTIM_RST2R_MSTCMP2_Pos       (9U)
+#define HRTIM_RST2R_MSTCMP2_Msk       (0x1UL << HRTIM_RST2R_MSTCMP2_Pos)       /*!< 0x00000200 */
+#define HRTIM_RST2R_MSTCMP2           HRTIM_RST2R_MSTCMP2_Msk                  /*!< Master compare 2 */
+#define HRTIM_RST2R_MSTCMP3_Pos       (10U)
+#define HRTIM_RST2R_MSTCMP3_Msk       (0x1UL << HRTIM_RST2R_MSTCMP3_Pos)       /*!< 0x00000400 */
+#define HRTIM_RST2R_MSTCMP3           HRTIM_RST2R_MSTCMP3_Msk                  /*!< Master compare 3 */
+#define HRTIM_RST2R_MSTCMP4_Pos       (11U)
+#define HRTIM_RST2R_MSTCMP4_Msk       (0x1UL << HRTIM_RST2R_MSTCMP4_Pos)       /*!< 0x00000800 */
+#define HRTIM_RST2R_MSTCMP4           HRTIM_RST2R_MSTCMP4_Msk                  /*!< Master compare 4 */
+
+#define HRTIM_RST2R_TIMEVNT1_Pos      (12U)
+#define HRTIM_RST2R_TIMEVNT1_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT1_Pos)      /*!< 0x00001000 */
+#define HRTIM_RST2R_TIMEVNT1          HRTIM_RST2R_TIMEVNT1_Msk                 /*!< Timer event 1 */
+#define HRTIM_RST2R_TIMEVNT2_Pos      (13U)
+#define HRTIM_RST2R_TIMEVNT2_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT2_Pos)      /*!< 0x00002000 */
+#define HRTIM_RST2R_TIMEVNT2          HRTIM_RST2R_TIMEVNT2_Msk                 /*!< Timer event 2 */
+#define HRTIM_RST2R_TIMEVNT3_Pos      (14U)
+#define HRTIM_RST2R_TIMEVNT3_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT3_Pos)      /*!< 0x00004000 */
+#define HRTIM_RST2R_TIMEVNT3          HRTIM_RST2R_TIMEVNT3_Msk                 /*!< Timer event 3 */
+#define HRTIM_RST2R_TIMEVNT4_Pos      (15U)
+#define HRTIM_RST2R_TIMEVNT4_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT4_Pos)      /*!< 0x00008000 */
+#define HRTIM_RST2R_TIMEVNT4          HRTIM_RST2R_TIMEVNT4_Msk                 /*!< Timer event 4 */
+#define HRTIM_RST2R_TIMEVNT5_Pos      (16U)
+#define HRTIM_RST2R_TIMEVNT5_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT5_Pos)      /*!< 0x00010000 */
+#define HRTIM_RST2R_TIMEVNT5          HRTIM_RST2R_TIMEVNT5_Msk                 /*!< Timer event 5 */
+#define HRTIM_RST2R_TIMEVNT6_Pos      (17U)
+#define HRTIM_RST2R_TIMEVNT6_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT6_Pos)      /*!< 0x00020000 */
+#define HRTIM_RST2R_TIMEVNT6          HRTIM_RST2R_TIMEVNT6_Msk                 /*!< Timer event 6 */
+#define HRTIM_RST2R_TIMEVNT7_Pos      (18U)
+#define HRTIM_RST2R_TIMEVNT7_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT7_Pos)      /*!< 0x00040000 */
+#define HRTIM_RST2R_TIMEVNT7          HRTIM_RST2R_TIMEVNT7_Msk                 /*!< Timer event 7 */
+#define HRTIM_RST2R_TIMEVNT8_Pos      (19U)
+#define HRTIM_RST2R_TIMEVNT8_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT8_Pos)      /*!< 0x00080000 */
+#define HRTIM_RST2R_TIMEVNT8          HRTIM_RST2R_TIMEVNT8_Msk                 /*!< Timer event 8 */
+#define HRTIM_RST2R_TIMEVNT9_Pos      (20U)
+#define HRTIM_RST2R_TIMEVNT9_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT9_Pos)      /*!< 0x00100000 */
+#define HRTIM_RST2R_TIMEVNT9          HRTIM_RST2R_TIMEVNT9_Msk                 /*!< Timer event 9 */
+
+#define HRTIM_RST2R_EXTVNT1_Pos       (21U)
+#define HRTIM_RST2R_EXTVNT1_Msk       (0x1UL << HRTIM_RST2R_EXTVNT1_Pos)       /*!< 0x00200000 */
+#define HRTIM_RST2R_EXTVNT1           HRTIM_RST2R_EXTVNT1_Msk                  /*!< External event 1 */
+#define HRTIM_RST2R_EXTVNT2_Pos       (22U)
+#define HRTIM_RST2R_EXTVNT2_Msk       (0x1UL << HRTIM_RST2R_EXTVNT2_Pos)       /*!< 0x00400000 */
+#define HRTIM_RST2R_EXTVNT2           HRTIM_RST2R_EXTVNT2_Msk                  /*!< External event 2 */
+#define HRTIM_RST2R_EXTVNT3_Pos       (23U)
+#define HRTIM_RST2R_EXTVNT3_Msk       (0x1UL << HRTIM_RST2R_EXTVNT3_Pos)       /*!< 0x00800000 */
+#define HRTIM_RST2R_EXTVNT3           HRTIM_RST2R_EXTVNT3_Msk                  /*!< External event 3 */
+#define HRTIM_RST2R_EXTVNT4_Pos       (24U)
+#define HRTIM_RST2R_EXTVNT4_Msk       (0x1UL << HRTIM_RST2R_EXTVNT4_Pos)       /*!< 0x01000000 */
+#define HRTIM_RST2R_EXTVNT4           HRTIM_RST2R_EXTVNT4_Msk                  /*!< External event 4 */
+#define HRTIM_RST2R_EXTVNT5_Pos       (25U)
+#define HRTIM_RST2R_EXTVNT5_Msk       (0x1UL << HRTIM_RST2R_EXTVNT5_Pos)       /*!< 0x02000000 */
+#define HRTIM_RST2R_EXTVNT5           HRTIM_RST2R_EXTVNT5_Msk                  /*!< External event 5 */
+#define HRTIM_RST2R_EXTVNT6_Pos       (26U)
+#define HRTIM_RST2R_EXTVNT6_Msk       (0x1UL << HRTIM_RST2R_EXTVNT6_Pos)       /*!< 0x04000000 */
+#define HRTIM_RST2R_EXTVNT6           HRTIM_RST2R_EXTVNT6_Msk                  /*!< External event 6 */
+#define HRTIM_RST2R_EXTVNT7_Pos       (27U)
+#define HRTIM_RST2R_EXTVNT7_Msk       (0x1UL << HRTIM_RST2R_EXTVNT7_Pos)       /*!< 0x08000000 */
+#define HRTIM_RST2R_EXTVNT7           HRTIM_RST2R_EXTVNT7_Msk                  /*!< External event 7 */
+#define HRTIM_RST2R_EXTVNT8_Pos       (28U)
+#define HRTIM_RST2R_EXTVNT8_Msk       (0x1UL << HRTIM_RST2R_EXTVNT8_Pos)       /*!< 0x10000000 */
+#define HRTIM_RST2R_EXTVNT8           HRTIM_RST2R_EXTVNT8_Msk                  /*!< External event 8 */
+#define HRTIM_RST2R_EXTVNT9_Pos       (29U)
+#define HRTIM_RST2R_EXTVNT9_Msk       (0x1UL << HRTIM_RST2R_EXTVNT9_Pos)       /*!< 0x20000000 */
+#define HRTIM_RST2R_EXTVNT9           HRTIM_RST2R_EXTVNT9_Msk                  /*!< External event 9 */
+#define HRTIM_RST2R_EXTVNT10_Pos      (30U)
+#define HRTIM_RST2R_EXTVNT10_Msk      (0x1UL << HRTIM_RST2R_EXTVNT10_Pos)      /*!< 0x40000000 */
+#define HRTIM_RST2R_EXTVNT10          HRTIM_RST2R_EXTVNT10_Msk                 /*!< External event 10 */
+
+#define HRTIM_RST2R_UPDATE_Pos        (31U)
+#define HRTIM_RST2R_UPDATE_Msk        (0x1UL << HRTIM_RST2R_UPDATE_Pos)        /*!< 0x80000000 */
+#define HRTIM_RST2R_UPDATE            HRTIM_RST2R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */
+
+/**** Bit definition for Slave external event filtering  register 1 ***********/
+#define HRTIM_EEFR1_EE1LTCH_Pos       (0U)
+#define HRTIM_EEFR1_EE1LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE1LTCH_Pos)       /*!< 0x00000001 */
+#define HRTIM_EEFR1_EE1LTCH           HRTIM_EEFR1_EE1LTCH_Msk                  /*!< External Event 1 latch */
+#define HRTIM_EEFR1_EE1FLTR_Pos       (1U)
+#define HRTIM_EEFR1_EE1FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE1FLTR_Pos)       /*!< 0x0000001E */
+#define HRTIM_EEFR1_EE1FLTR           HRTIM_EEFR1_EE1FLTR_Msk                  /*!< External Event 1 filter mask */
+#define HRTIM_EEFR1_EE1FLTR_0         (0x1UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000002 */
+#define HRTIM_EEFR1_EE1FLTR_1         (0x2UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000004 */
+#define HRTIM_EEFR1_EE1FLTR_2         (0x4UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000008 */
+#define HRTIM_EEFR1_EE1FLTR_3         (0x8UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000010 */
+
+#define HRTIM_EEFR1_EE2LTCH_Pos       (6U)
+#define HRTIM_EEFR1_EE2LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE2LTCH_Pos)       /*!< 0x00000040 */
+#define HRTIM_EEFR1_EE2LTCH           HRTIM_EEFR1_EE2LTCH_Msk                  /*!< External Event 2 latch */
+#define HRTIM_EEFR1_EE2FLTR_Pos       (7U)
+#define HRTIM_EEFR1_EE2FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE2FLTR_Pos)       /*!< 0x00000780 */
+#define HRTIM_EEFR1_EE2FLTR           HRTIM_EEFR1_EE2FLTR_Msk                  /*!< External Event 2 filter mask */
+#define HRTIM_EEFR1_EE2FLTR_0         (0x1UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000080 */
+#define HRTIM_EEFR1_EE2FLTR_1         (0x2UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000100 */
+#define HRTIM_EEFR1_EE2FLTR_2         (0x4UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000200 */
+#define HRTIM_EEFR1_EE2FLTR_3         (0x8UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000400 */
+
+#define HRTIM_EEFR1_EE3LTCH_Pos       (12U)
+#define HRTIM_EEFR1_EE3LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE3LTCH_Pos)       /*!< 0x00001000 */
+#define HRTIM_EEFR1_EE3LTCH           HRTIM_EEFR1_EE3LTCH_Msk                  /*!< External Event 3 latch */
+#define HRTIM_EEFR1_EE3FLTR_Pos       (13U)
+#define HRTIM_EEFR1_EE3FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE3FLTR_Pos)       /*!< 0x0001E000 */
+#define HRTIM_EEFR1_EE3FLTR           HRTIM_EEFR1_EE3FLTR_Msk                  /*!< External Event 3 filter mask */
+#define HRTIM_EEFR1_EE3FLTR_0         (0x1UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00002000 */
+#define HRTIM_EEFR1_EE3FLTR_1         (0x2UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00004000 */
+#define HRTIM_EEFR1_EE3FLTR_2         (0x4UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00008000 */
+#define HRTIM_EEFR1_EE3FLTR_3         (0x8UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00010000 */
+
+#define HRTIM_EEFR1_EE4LTCH_Pos       (18U)
+#define HRTIM_EEFR1_EE4LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE4LTCH_Pos)       /*!< 0x00040000 */
+#define HRTIM_EEFR1_EE4LTCH           HRTIM_EEFR1_EE4LTCH_Msk                  /*!< External Event 4 latch */
+#define HRTIM_EEFR1_EE4FLTR_Pos       (19U)
+#define HRTIM_EEFR1_EE4FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE4FLTR_Pos)       /*!< 0x00780000 */
+#define HRTIM_EEFR1_EE4FLTR           HRTIM_EEFR1_EE4FLTR_Msk                  /*!< External Event 4 filter mask */
+#define HRTIM_EEFR1_EE4FLTR_0         (0x1UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00080000 */
+#define HRTIM_EEFR1_EE4FLTR_1         (0x2UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00100000 */
+#define HRTIM_EEFR1_EE4FLTR_2         (0x4UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00200000 */
+#define HRTIM_EEFR1_EE4FLTR_3         (0x8UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00400000 */
+
+#define HRTIM_EEFR1_EE5LTCH_Pos       (24U)
+#define HRTIM_EEFR1_EE5LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE5LTCH_Pos)       /*!< 0x01000000 */
+#define HRTIM_EEFR1_EE5LTCH           HRTIM_EEFR1_EE5LTCH_Msk                  /*!< External Event 5 latch */
+#define HRTIM_EEFR1_EE5FLTR_Pos       (25U)
+#define HRTIM_EEFR1_EE5FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE5FLTR_Pos)       /*!< 0x1E000000 */
+#define HRTIM_EEFR1_EE5FLTR           HRTIM_EEFR1_EE5FLTR_Msk                  /*!< External Event 5 filter mask */
+#define HRTIM_EEFR1_EE5FLTR_0         (0x1UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x02000000 */
+#define HRTIM_EEFR1_EE5FLTR_1         (0x2UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x04000000 */
+#define HRTIM_EEFR1_EE5FLTR_2         (0x4UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x08000000 */
+#define HRTIM_EEFR1_EE5FLTR_3         (0x8UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x10000000 */
+
+/**** Bit definition for Slave external event filtering  register 2 ***********/
+#define HRTIM_EEFR2_EE6LTCH_Pos       (0U)
+#define HRTIM_EEFR2_EE6LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE6LTCH_Pos)       /*!< 0x00000001 */
+#define HRTIM_EEFR2_EE6LTCH           HRTIM_EEFR2_EE6LTCH_Msk                  /*!< External Event 6 latch */
+#define HRTIM_EEFR2_EE6FLTR_Pos       (1U)
+#define HRTIM_EEFR2_EE6FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE6FLTR_Pos)       /*!< 0x0000001E */
+#define HRTIM_EEFR2_EE6FLTR           HRTIM_EEFR2_EE6FLTR_Msk                  /*!< External Event 6 filter mask */
+#define HRTIM_EEFR2_EE6FLTR_0         (0x1UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000002 */
+#define HRTIM_EEFR2_EE6FLTR_1         (0x2UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000004 */
+#define HRTIM_EEFR2_EE6FLTR_2         (0x4UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000008 */
+#define HRTIM_EEFR2_EE6FLTR_3         (0x8UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000010 */
+
+#define HRTIM_EEFR2_EE7LTCH_Pos       (6U)
+#define HRTIM_EEFR2_EE7LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE7LTCH_Pos)       /*!< 0x00000040 */
+#define HRTIM_EEFR2_EE7LTCH           HRTIM_EEFR2_EE7LTCH_Msk                  /*!< External Event 7 latch */
+#define HRTIM_EEFR2_EE7FLTR_Pos       (7U)
+#define HRTIM_EEFR2_EE7FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE7FLTR_Pos)       /*!< 0x00000780 */
+#define HRTIM_EEFR2_EE7FLTR           HRTIM_EEFR2_EE7FLTR_Msk                  /*!< External Event 7 filter mask */
+#define HRTIM_EEFR2_EE7FLTR_0         (0x1UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000080 */
+#define HRTIM_EEFR2_EE7FLTR_1         (0x2UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000100 */
+#define HRTIM_EEFR2_EE7FLTR_2         (0x4UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000200 */
+#define HRTIM_EEFR2_EE7FLTR_3         (0x8UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000400 */
+
+#define HRTIM_EEFR2_EE8LTCH_Pos       (12U)
+#define HRTIM_EEFR2_EE8LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE8LTCH_Pos)       /*!< 0x00001000 */
+#define HRTIM_EEFR2_EE8LTCH           HRTIM_EEFR2_EE8LTCH_Msk                  /*!< External Event 8 latch */
+#define HRTIM_EEFR2_EE8FLTR_Pos       (13U)
+#define HRTIM_EEFR2_EE8FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE8FLTR_Pos)       /*!< 0x0001E000 */
+#define HRTIM_EEFR2_EE8FLTR           HRTIM_EEFR2_EE8FLTR_Msk                  /*!< External Event 8 filter mask */
+#define HRTIM_EEFR2_EE8FLTR_0         (0x1UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00002000 */
+#define HRTIM_EEFR2_EE8FLTR_1         (0x2UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00004000 */
+#define HRTIM_EEFR2_EE8FLTR_2         (0x4UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00008000 */
+#define HRTIM_EEFR2_EE8FLTR_3         (0x8UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00010000 */
+
+#define HRTIM_EEFR2_EE9LTCH_Pos       (18U)
+#define HRTIM_EEFR2_EE9LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE9LTCH_Pos)       /*!< 0x00040000 */
+#define HRTIM_EEFR2_EE9LTCH           HRTIM_EEFR2_EE9LTCH_Msk                  /*!< External Event 9 latch */
+#define HRTIM_EEFR2_EE9FLTR_Pos       (19U)
+#define HRTIM_EEFR2_EE9FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE9FLTR_Pos)       /*!< 0x00780000 */
+#define HRTIM_EEFR2_EE9FLTR           HRTIM_EEFR2_EE9FLTR_Msk                  /*!< External Event 9 filter mask */
+#define HRTIM_EEFR2_EE9FLTR_0         (0x1UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00080000 */
+#define HRTIM_EEFR2_EE9FLTR_1         (0x2UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00100000 */
+#define HRTIM_EEFR2_EE9FLTR_2         (0x4UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00200000 */
+#define HRTIM_EEFR2_EE9FLTR_3         (0x8UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00400000 */
+
+#define HRTIM_EEFR2_EE10LTCH_Pos      (24U)
+#define HRTIM_EEFR2_EE10LTCH_Msk      (0x1UL << HRTIM_EEFR2_EE10LTCH_Pos)      /*!< 0x01000000 */
+#define HRTIM_EEFR2_EE10LTCH          HRTIM_EEFR2_EE10LTCH_Msk                 /*!< External Event 10 latch */
+#define HRTIM_EEFR2_EE10FLTR_Pos      (25U)
+#define HRTIM_EEFR2_EE10FLTR_Msk      (0xFUL << HRTIM_EEFR2_EE10FLTR_Pos)      /*!< 0x1E000000 */
+#define HRTIM_EEFR2_EE10FLTR          HRTIM_EEFR2_EE10FLTR_Msk                 /*!< External Event 10 filter mask */
+#define HRTIM_EEFR2_EE10FLTR_0        (0x1UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x02000000 */
+#define HRTIM_EEFR2_EE10FLTR_1        (0x2UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x04000000 */
+#define HRTIM_EEFR2_EE10FLTR_2        (0x4UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x08000000 */
+#define HRTIM_EEFR2_EE10FLTR_3        (0x8UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x10000000 */
+
+/**** Bit definition for Slave Timer reset register ***************************/
+#define HRTIM_RSTR_UPDATE_Pos         (1U)
+#define HRTIM_RSTR_UPDATE_Msk         (0x1UL << HRTIM_RSTR_UPDATE_Pos)         /*!< 0x00000002 */
+#define HRTIM_RSTR_UPDATE             HRTIM_RSTR_UPDATE_Msk                    /*!< Timer update */
+#define HRTIM_RSTR_CMP2_Pos           (2U)
+#define HRTIM_RSTR_CMP2_Msk           (0x1UL << HRTIM_RSTR_CMP2_Pos)           /*!< 0x00000004 */
+#define HRTIM_RSTR_CMP2               HRTIM_RSTR_CMP2_Msk                      /*!< Timer compare2 */
+#define HRTIM_RSTR_CMP4_Pos           (3U)
+#define HRTIM_RSTR_CMP4_Msk           (0x1UL << HRTIM_RSTR_CMP4_Pos)           /*!< 0x00000008 */
+#define HRTIM_RSTR_CMP4               HRTIM_RSTR_CMP4_Msk                      /*!< Timer compare4 */
+
+#define HRTIM_RSTR_MSTPER_Pos         (4U)
+#define HRTIM_RSTR_MSTPER_Msk         (0x1UL << HRTIM_RSTR_MSTPER_Pos)         /*!< 0x00000010 */
+#define HRTIM_RSTR_MSTPER             HRTIM_RSTR_MSTPER_Msk                    /*!< Master period */
+#define HRTIM_RSTR_MSTCMP1_Pos        (5U)
+#define HRTIM_RSTR_MSTCMP1_Msk        (0x1UL << HRTIM_RSTR_MSTCMP1_Pos)        /*!< 0x00000020 */
+#define HRTIM_RSTR_MSTCMP1            HRTIM_RSTR_MSTCMP1_Msk                   /*!< Master compare1 */
+#define HRTIM_RSTR_MSTCMP2_Pos        (6U)
+#define HRTIM_RSTR_MSTCMP2_Msk        (0x1UL << HRTIM_RSTR_MSTCMP2_Pos)        /*!< 0x00000040 */
+#define HRTIM_RSTR_MSTCMP2            HRTIM_RSTR_MSTCMP2_Msk                   /*!< Master compare2 */
+#define HRTIM_RSTR_MSTCMP3_Pos        (7U)
+#define HRTIM_RSTR_MSTCMP3_Msk        (0x1UL << HRTIM_RSTR_MSTCMP3_Pos)        /*!< 0x00000080 */
+#define HRTIM_RSTR_MSTCMP3            HRTIM_RSTR_MSTCMP3_Msk                   /*!< Master compare3 */
+#define HRTIM_RSTR_MSTCMP4_Pos        (8U)
+#define HRTIM_RSTR_MSTCMP4_Msk        (0x1UL << HRTIM_RSTR_MSTCMP4_Pos)        /*!< 0x00000100 */
+#define HRTIM_RSTR_MSTCMP4            HRTIM_RSTR_MSTCMP4_Msk                   /*!< Master compare4 */
+
+#define HRTIM_RSTR_EXTEVNT1_Pos       (9U)
+#define HRTIM_RSTR_EXTEVNT1_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT1_Pos)       /*!< 0x00000200 */
+#define HRTIM_RSTR_EXTEVNT1           HRTIM_RSTR_EXTEVNT1_Msk                  /*!< External event 1 */
+#define HRTIM_RSTR_EXTEVNT2_Pos       (10U)
+#define HRTIM_RSTR_EXTEVNT2_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT2_Pos)       /*!< 0x00000400 */
+#define HRTIM_RSTR_EXTEVNT2           HRTIM_RSTR_EXTEVNT2_Msk                  /*!< External event 2 */
+#define HRTIM_RSTR_EXTEVNT3_Pos       (11U)
+#define HRTIM_RSTR_EXTEVNT3_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT3_Pos)       /*!< 0x00000800 */
+#define HRTIM_RSTR_EXTEVNT3           HRTIM_RSTR_EXTEVNT3_Msk                  /*!< External event 3 */
+#define HRTIM_RSTR_EXTEVNT4_Pos       (12U)
+#define HRTIM_RSTR_EXTEVNT4_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT4_Pos)       /*!< 0x00001000 */
+#define HRTIM_RSTR_EXTEVNT4           HRTIM_RSTR_EXTEVNT4_Msk                  /*!< External event 4 */
+#define HRTIM_RSTR_EXTEVNT5_Pos       (13U)
+#define HRTIM_RSTR_EXTEVNT5_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT5_Pos)       /*!< 0x00002000 */
+#define HRTIM_RSTR_EXTEVNT5           HRTIM_RSTR_EXTEVNT5_Msk                  /*!< External event 5 */
+#define HRTIM_RSTR_EXTEVNT6_Pos       (14U)
+#define HRTIM_RSTR_EXTEVNT6_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT6_Pos)       /*!< 0x00004000 */
+#define HRTIM_RSTR_EXTEVNT6           HRTIM_RSTR_EXTEVNT6_Msk                  /*!< External event 6 */
+#define HRTIM_RSTR_EXTEVNT7_Pos       (15U)
+#define HRTIM_RSTR_EXTEVNT7_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT7_Pos)       /*!< 0x00008000 */
+#define HRTIM_RSTR_EXTEVNT7           HRTIM_RSTR_EXTEVNT7_Msk                  /*!< External event 7 */
+#define HRTIM_RSTR_EXTEVNT8_Pos       (16U)
+#define HRTIM_RSTR_EXTEVNT8_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT8_Pos)       /*!< 0x00010000 */
+#define HRTIM_RSTR_EXTEVNT8           HRTIM_RSTR_EXTEVNT8_Msk                  /*!< External event 8 */
+#define HRTIM_RSTR_EXTEVNT9_Pos       (17U)
+#define HRTIM_RSTR_EXTEVNT9_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT9_Pos)       /*!< 0x00020000 */
+#define HRTIM_RSTR_EXTEVNT9           HRTIM_RSTR_EXTEVNT9_Msk                  /*!< External event 9 */
+#define HRTIM_RSTR_EXTEVNT10_Pos      (18U)
+#define HRTIM_RSTR_EXTEVNT10_Msk      (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos)      /*!< 0x00040000 */
+#define HRTIM_RSTR_EXTEVNT10          HRTIM_RSTR_EXTEVNT10_Msk                 /*!< External event 10 */
+
+#define HRTIM_RSTR_TIMBCMP1_Pos       (19U)
+#define HRTIM_RSTR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos)       /*!< 0x00080000 */
+#define HRTIM_RSTR_TIMBCMP1           HRTIM_RSTR_TIMBCMP1_Msk                  /*!< Timer B compare 1 */
+#define HRTIM_RSTR_TIMBCMP2_Pos       (20U)
+#define HRTIM_RSTR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP2_Pos)       /*!< 0x00100000 */
+#define HRTIM_RSTR_TIMBCMP2           HRTIM_RSTR_TIMBCMP2_Msk                  /*!< Timer B compare 2 */
+#define HRTIM_RSTR_TIMBCMP4_Pos       (21U)
+#define HRTIM_RSTR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP4_Pos)       /*!< 0x00200000 */
+#define HRTIM_RSTR_TIMBCMP4           HRTIM_RSTR_TIMBCMP4_Msk                  /*!< Timer B compare 4 */
+
+#define HRTIM_RSTR_TIMCCMP1_Pos       (22U)
+#define HRTIM_RSTR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP1_Pos)       /*!< 0x00400000 */
+#define HRTIM_RSTR_TIMCCMP1           HRTIM_RSTR_TIMCCMP1_Msk                  /*!< Timer C compare 1 */
+#define HRTIM_RSTR_TIMCCMP2_Pos       (23U)
+#define HRTIM_RSTR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP2_Pos)       /*!< 0x00800000 */
+#define HRTIM_RSTR_TIMCCMP2           HRTIM_RSTR_TIMCCMP2_Msk                  /*!< Timer C compare 2 */
+#define HRTIM_RSTR_TIMCCMP4_Pos       (24U)
+#define HRTIM_RSTR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP4_Pos)       /*!< 0x01000000 */
+#define HRTIM_RSTR_TIMCCMP4           HRTIM_RSTR_TIMCCMP4_Msk                  /*!< Timer C compare 4 */
+
+#define HRTIM_RSTR_TIMDCMP1_Pos       (25U)
+#define HRTIM_RSTR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP1_Pos)       /*!< 0x02000000 */
+#define HRTIM_RSTR_TIMDCMP1           HRTIM_RSTR_TIMDCMP1_Msk                  /*!< Timer D compare 1 */
+#define HRTIM_RSTR_TIMDCMP2_Pos       (26U)
+#define HRTIM_RSTR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP2_Pos)       /*!< 0x04000000 */
+#define HRTIM_RSTR_TIMDCMP2           HRTIM_RSTR_TIMDCMP2_Msk                  /*!< Timer D compare 2 */
+#define HRTIM_RSTR_TIMDCMP4_Pos       (27U)
+#define HRTIM_RSTR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP4_Pos)       /*!< 0x08000000 */
+#define HRTIM_RSTR_TIMDCMP4           HRTIM_RSTR_TIMDCMP4_Msk                  /*!< Timer D compare 4 */
+
+#define HRTIM_RSTR_TIMECMP1_Pos       (28U)
+#define HRTIM_RSTR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTR_TIMECMP1_Pos)       /*!< 0x10000000 */
+#define HRTIM_RSTR_TIMECMP1           HRTIM_RSTR_TIMECMP1_Msk                  /*!< Timer E compare 1 */
+#define HRTIM_RSTR_TIMECMP2_Pos       (29U)
+#define HRTIM_RSTR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTR_TIMECMP2_Pos)       /*!< 0x20000000 */
+#define HRTIM_RSTR_TIMECMP2           HRTIM_RSTR_TIMECMP2_Msk                  /*!< Timer E compare 2 */
+#define HRTIM_RSTR_TIMECMP4_Pos       (30U)
+#define HRTIM_RSTR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTR_TIMECMP4_Pos)       /*!< 0x40000000 */
+#define HRTIM_RSTR_TIMECMP4           HRTIM_RSTR_TIMECMP4_Msk                  /*!< Timer E compare 4 */
+
+/**** Bit definition for Slave Timer Chopper register *************************/
+#define HRTIM_CHPR_CARFRQ_Pos         (0U)
+#define HRTIM_CHPR_CARFRQ_Msk         (0xFUL << HRTIM_CHPR_CARFRQ_Pos)         /*!< 0x0000000F */
+#define HRTIM_CHPR_CARFRQ             HRTIM_CHPR_CARFRQ_Msk                    /*!< Timer carrier frequency value */
+#define HRTIM_CHPR_CARFRQ_0           (0x1UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000001 */
+#define HRTIM_CHPR_CARFRQ_1           (0x2UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000002 */
+#define HRTIM_CHPR_CARFRQ_2           (0x4UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000004 */
+#define HRTIM_CHPR_CARFRQ_3           (0x8UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000008 */
+
+#define HRTIM_CHPR_CARDTY_Pos         (4U)
+#define HRTIM_CHPR_CARDTY_Msk         (0x7UL << HRTIM_CHPR_CARDTY_Pos)         /*!< 0x00000070 */
+#define HRTIM_CHPR_CARDTY             HRTIM_CHPR_CARDTY_Msk                    /*!< Timer chopper duty cycle value */
+#define HRTIM_CHPR_CARDTY_0           (0x1UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000010 */
+#define HRTIM_CHPR_CARDTY_1           (0x2UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000020 */
+#define HRTIM_CHPR_CARDTY_2           (0x4UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000040 */
+
+#define HRTIM_CHPR_STRPW_Pos          (7U)
+#define HRTIM_CHPR_STRPW_Msk          (0xFUL << HRTIM_CHPR_STRPW_Pos)          /*!< 0x00000780 */
+#define HRTIM_CHPR_STRPW              HRTIM_CHPR_STRPW_Msk                     /*!< Timer start pulse width value */
+#define HRTIM_CHPR_STRPW_0            (0x1UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000080 */
+#define HRTIM_CHPR_STRPW_1            (0x2UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000100 */
+#define HRTIM_CHPR_STRPW_2            (0x4UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000200 */
+#define HRTIM_CHPR_STRPW_3            (0x8UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000400 */
+
+/**** Bit definition for Slave Timer Capture 1 control register ***************/
+#define HRTIM_CPT1CR_SWCPT_Pos        (0U)
+#define HRTIM_CPT1CR_SWCPT_Msk        (0x1UL << HRTIM_CPT1CR_SWCPT_Pos)        /*!< 0x00000001 */
+#define HRTIM_CPT1CR_SWCPT            HRTIM_CPT1CR_SWCPT_Msk                   /*!< Software capture */
+#define HRTIM_CPT1CR_UPDCPT_Pos       (1U)
+#define HRTIM_CPT1CR_UPDCPT_Msk       (0x1UL << HRTIM_CPT1CR_UPDCPT_Pos)       /*!< 0x00000002 */
+#define HRTIM_CPT1CR_UPDCPT           HRTIM_CPT1CR_UPDCPT_Msk                  /*!< Update capture */
+#define HRTIM_CPT1CR_EXEV1CPT_Pos     (2U)
+#define HRTIM_CPT1CR_EXEV1CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV1CPT_Pos)     /*!< 0x00000004 */
+#define HRTIM_CPT1CR_EXEV1CPT         HRTIM_CPT1CR_EXEV1CPT_Msk                /*!< External event 1 capture */
+#define HRTIM_CPT1CR_EXEV2CPT_Pos     (3U)
+#define HRTIM_CPT1CR_EXEV2CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV2CPT_Pos)     /*!< 0x00000008 */
+#define HRTIM_CPT1CR_EXEV2CPT         HRTIM_CPT1CR_EXEV2CPT_Msk                /*!< External event 2 capture */
+#define HRTIM_CPT1CR_EXEV3CPT_Pos     (4U)
+#define HRTIM_CPT1CR_EXEV3CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV3CPT_Pos)     /*!< 0x00000010 */
+#define HRTIM_CPT1CR_EXEV3CPT         HRTIM_CPT1CR_EXEV3CPT_Msk                /*!< External event 3 capture */
+#define HRTIM_CPT1CR_EXEV4CPT_Pos     (5U)
+#define HRTIM_CPT1CR_EXEV4CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV4CPT_Pos)     /*!< 0x00000020 */
+#define HRTIM_CPT1CR_EXEV4CPT         HRTIM_CPT1CR_EXEV4CPT_Msk                /*!< External event 4 capture */
+#define HRTIM_CPT1CR_EXEV5CPT_Pos     (6U)
+#define HRTIM_CPT1CR_EXEV5CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV5CPT_Pos)     /*!< 0x00000040 */
+#define HRTIM_CPT1CR_EXEV5CPT         HRTIM_CPT1CR_EXEV5CPT_Msk                /*!< External event 5 capture */
+#define HRTIM_CPT1CR_EXEV6CPT_Pos     (7U)
+#define HRTIM_CPT1CR_EXEV6CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV6CPT_Pos)     /*!< 0x00000080 */
+#define HRTIM_CPT1CR_EXEV6CPT         HRTIM_CPT1CR_EXEV6CPT_Msk                /*!< External event 6 capture */
+#define HRTIM_CPT1CR_EXEV7CPT_Pos     (8U)
+#define HRTIM_CPT1CR_EXEV7CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV7CPT_Pos)     /*!< 0x00000100 */
+#define HRTIM_CPT1CR_EXEV7CPT         HRTIM_CPT1CR_EXEV7CPT_Msk                /*!< External event 7 capture */
+#define HRTIM_CPT1CR_EXEV8CPT_Pos     (9U)
+#define HRTIM_CPT1CR_EXEV8CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV8CPT_Pos)     /*!< 0x00000200 */
+#define HRTIM_CPT1CR_EXEV8CPT         HRTIM_CPT1CR_EXEV8CPT_Msk                /*!< External event 8 capture */
+#define HRTIM_CPT1CR_EXEV9CPT_Pos     (10U)
+#define HRTIM_CPT1CR_EXEV9CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV9CPT_Pos)     /*!< 0x00000400 */
+#define HRTIM_CPT1CR_EXEV9CPT         HRTIM_CPT1CR_EXEV9CPT_Msk                /*!< External event 9 capture */
+#define HRTIM_CPT1CR_EXEV10CPT_Pos    (11U)
+#define HRTIM_CPT1CR_EXEV10CPT_Msk    (0x1UL << HRTIM_CPT1CR_EXEV10CPT_Pos)    /*!< 0x00000800 */
+#define HRTIM_CPT1CR_EXEV10CPT        HRTIM_CPT1CR_EXEV10CPT_Msk               /*!< External event 10 capture */
+
+#define HRTIM_CPT1CR_TA1SET_Pos       (12U)
+#define HRTIM_CPT1CR_TA1SET_Msk       (0x1UL << HRTIM_CPT1CR_TA1SET_Pos)       /*!< 0x00001000 */
+#define HRTIM_CPT1CR_TA1SET           HRTIM_CPT1CR_TA1SET_Msk                  /*!< Timer A output 1 set */
+#define HRTIM_CPT1CR_TA1RST_Pos       (13U)
+#define HRTIM_CPT1CR_TA1RST_Msk       (0x1UL << HRTIM_CPT1CR_TA1RST_Pos)       /*!< 0x00002000 */
+#define HRTIM_CPT1CR_TA1RST           HRTIM_CPT1CR_TA1RST_Msk                  /*!< Timer A output 1 reset */
+#define HRTIM_CPT1CR_TIMACMP1_Pos     (14U)
+#define HRTIM_CPT1CR_TIMACMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMACMP1_Pos)     /*!< 0x00004000 */
+#define HRTIM_CPT1CR_TIMACMP1         HRTIM_CPT1CR_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_CPT1CR_TIMACMP2_Pos     (15U)
+#define HRTIM_CPT1CR_TIMACMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMACMP2_Pos)     /*!< 0x00008000 */
+#define HRTIM_CPT1CR_TIMACMP2         HRTIM_CPT1CR_TIMACMP2_Msk                /*!< Timer A compare 2 */
+
+#define HRTIM_CPT1CR_TB1SET_Pos       (16U)
+#define HRTIM_CPT1CR_TB1SET_Msk       (0x1UL << HRTIM_CPT1CR_TB1SET_Pos)       /*!< 0x00010000 */
+#define HRTIM_CPT1CR_TB1SET           HRTIM_CPT1CR_TB1SET_Msk                  /*!< Timer B output 1 set */
+#define HRTIM_CPT1CR_TB1RST_Pos       (17U)
+#define HRTIM_CPT1CR_TB1RST_Msk       (0x1UL << HRTIM_CPT1CR_TB1RST_Pos)       /*!< 0x00020000 */
+#define HRTIM_CPT1CR_TB1RST           HRTIM_CPT1CR_TB1RST_Msk                  /*!< Timer B output 1 reset */
+#define HRTIM_CPT1CR_TIMBCMP1_Pos     (18U)
+#define HRTIM_CPT1CR_TIMBCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMBCMP1_Pos)     /*!< 0x00040000 */
+#define HRTIM_CPT1CR_TIMBCMP1         HRTIM_CPT1CR_TIMBCMP1_Msk                /*!< Timer B compare 1 */
+#define HRTIM_CPT1CR_TIMBCMP2_Pos     (19U)
+#define HRTIM_CPT1CR_TIMBCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMBCMP2_Pos)     /*!< 0x00080000 */
+#define HRTIM_CPT1CR_TIMBCMP2         HRTIM_CPT1CR_TIMBCMP2_Msk                /*!< Timer B compare 2 */
+
+#define HRTIM_CPT1CR_TC1SET_Pos       (20U)
+#define HRTIM_CPT1CR_TC1SET_Msk       (0x1UL << HRTIM_CPT1CR_TC1SET_Pos)       /*!< 0x00100000 */
+#define HRTIM_CPT1CR_TC1SET           HRTIM_CPT1CR_TC1SET_Msk                  /*!< Timer C output 1 set */
+#define HRTIM_CPT1CR_TC1RST_Pos       (21U)
+#define HRTIM_CPT1CR_TC1RST_Msk       (0x1UL << HRTIM_CPT1CR_TC1RST_Pos)       /*!< 0x00200000 */
+#define HRTIM_CPT1CR_TC1RST           HRTIM_CPT1CR_TC1RST_Msk                  /*!< Timer C output 1 reset */
+#define HRTIM_CPT1CR_TIMCCMP1_Pos     (22U)
+#define HRTIM_CPT1CR_TIMCCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMCCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_CPT1CR_TIMCCMP1         HRTIM_CPT1CR_TIMCCMP1_Msk                /*!< Timer C compare 1 */
+#define HRTIM_CPT1CR_TIMCCMP2_Pos     (23U)
+#define HRTIM_CPT1CR_TIMCCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMCCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_CPT1CR_TIMCCMP2         HRTIM_CPT1CR_TIMCCMP2_Msk                /*!< Timer C compare 2 */
+
+#define HRTIM_CPT1CR_TD1SET_Pos       (24U)
+#define HRTIM_CPT1CR_TD1SET_Msk       (0x1UL << HRTIM_CPT1CR_TD1SET_Pos)       /*!< 0x01000000 */
+#define HRTIM_CPT1CR_TD1SET           HRTIM_CPT1CR_TD1SET_Msk                  /*!< Timer D output 1 set */
+#define HRTIM_CPT1CR_TD1RST_Pos       (25U)
+#define HRTIM_CPT1CR_TD1RST_Msk       (0x1UL << HRTIM_CPT1CR_TD1RST_Pos)       /*!< 0x02000000 */
+#define HRTIM_CPT1CR_TD1RST           HRTIM_CPT1CR_TD1RST_Msk                  /*!< Timer D output 1 reset */
+#define HRTIM_CPT1CR_TIMDCMP1_Pos     (26U)
+#define HRTIM_CPT1CR_TIMDCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMDCMP1_Pos)     /*!< 0x04000000 */
+#define HRTIM_CPT1CR_TIMDCMP1         HRTIM_CPT1CR_TIMDCMP1_Msk                /*!< Timer D compare 1 */
+#define HRTIM_CPT1CR_TIMDCMP2_Pos     (27U)
+#define HRTIM_CPT1CR_TIMDCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMDCMP2_Pos)     /*!< 0x08000000 */
+#define HRTIM_CPT1CR_TIMDCMP2         HRTIM_CPT1CR_TIMDCMP2_Msk                /*!< Timer D compare 2 */
+
+#define HRTIM_CPT1CR_TE1SET_Pos       (28U)
+#define HRTIM_CPT1CR_TE1SET_Msk       (0x1UL << HRTIM_CPT1CR_TE1SET_Pos)       /*!< 0x10000000 */
+#define HRTIM_CPT1CR_TE1SET           HRTIM_CPT1CR_TE1SET_Msk                  /*!< Timer E output 1 set */
+#define HRTIM_CPT1CR_TE1RST_Pos       (29U)
+#define HRTIM_CPT1CR_TE1RST_Msk       (0x1UL << HRTIM_CPT1CR_TE1RST_Pos)       /*!< 0x20000000 */
+#define HRTIM_CPT1CR_TE1RST           HRTIM_CPT1CR_TE1RST_Msk                  /*!< Timer E output 1 reset */
+#define HRTIM_CPT1CR_TIMECMP1_Pos     (30U)
+#define HRTIM_CPT1CR_TIMECMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMECMP1_Pos)     /*!< 0x40000000 */
+#define HRTIM_CPT1CR_TIMECMP1         HRTIM_CPT1CR_TIMECMP1_Msk                /*!< Timer E compare 1 */
+#define HRTIM_CPT1CR_TIMECMP2_Pos     (31U)
+#define HRTIM_CPT1CR_TIMECMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMECMP2_Pos)     /*!< 0x80000000 */
+#define HRTIM_CPT1CR_TIMECMP2         HRTIM_CPT1CR_TIMECMP2_Msk                /*!< Timer E compare 2 */
+
+/**** Bit definition for Slave Timer Capture 2 control register ***************/
+#define HRTIM_CPT2CR_SWCPT_Pos        (0U)
+#define HRTIM_CPT2CR_SWCPT_Msk        (0x1UL << HRTIM_CPT2CR_SWCPT_Pos)        /*!< 0x00000001 */
+#define HRTIM_CPT2CR_SWCPT            HRTIM_CPT2CR_SWCPT_Msk                   /*!< Software capture */
+#define HRTIM_CPT2CR_UPDCPT_Pos       (1U)
+#define HRTIM_CPT2CR_UPDCPT_Msk       (0x1UL << HRTIM_CPT2CR_UPDCPT_Pos)       /*!< 0x00000002 */
+#define HRTIM_CPT2CR_UPDCPT           HRTIM_CPT2CR_UPDCPT_Msk                  /*!< Update capture */
+#define HRTIM_CPT2CR_EXEV1CPT_Pos     (2U)
+#define HRTIM_CPT2CR_EXEV1CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV1CPT_Pos)     /*!< 0x00000004 */
+#define HRTIM_CPT2CR_EXEV1CPT         HRTIM_CPT2CR_EXEV1CPT_Msk                /*!< External event 1 capture */
+#define HRTIM_CPT2CR_EXEV2CPT_Pos     (3U)
+#define HRTIM_CPT2CR_EXEV2CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV2CPT_Pos)     /*!< 0x00000008 */
+#define HRTIM_CPT2CR_EXEV2CPT         HRTIM_CPT2CR_EXEV2CPT_Msk                /*!< External event 2 capture */
+#define HRTIM_CPT2CR_EXEV3CPT_Pos     (4U)
+#define HRTIM_CPT2CR_EXEV3CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV3CPT_Pos)     /*!< 0x00000010 */
+#define HRTIM_CPT2CR_EXEV3CPT         HRTIM_CPT2CR_EXEV3CPT_Msk                /*!< External event 3 capture */
+#define HRTIM_CPT2CR_EXEV4CPT_Pos     (5U)
+#define HRTIM_CPT2CR_EXEV4CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV4CPT_Pos)     /*!< 0x00000020 */
+#define HRTIM_CPT2CR_EXEV4CPT         HRTIM_CPT2CR_EXEV4CPT_Msk                /*!< External event 4 capture */
+#define HRTIM_CPT2CR_EXEV5CPT_Pos     (6U)
+#define HRTIM_CPT2CR_EXEV5CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV5CPT_Pos)     /*!< 0x00000040 */
+#define HRTIM_CPT2CR_EXEV5CPT         HRTIM_CPT2CR_EXEV5CPT_Msk                /*!< External event 5 capture */
+#define HRTIM_CPT2CR_EXEV6CPT_Pos     (7U)
+#define HRTIM_CPT2CR_EXEV6CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV6CPT_Pos)     /*!< 0x00000080 */
+#define HRTIM_CPT2CR_EXEV6CPT         HRTIM_CPT2CR_EXEV6CPT_Msk                /*!< External event 6 capture */
+#define HRTIM_CPT2CR_EXEV7CPT_Pos     (8U)
+#define HRTIM_CPT2CR_EXEV7CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV7CPT_Pos)     /*!< 0x00000100 */
+#define HRTIM_CPT2CR_EXEV7CPT         HRTIM_CPT2CR_EXEV7CPT_Msk                /*!< External event 7 capture */
+#define HRTIM_CPT2CR_EXEV8CPT_Pos     (9U)
+#define HRTIM_CPT2CR_EXEV8CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV8CPT_Pos)     /*!< 0x00000200 */
+#define HRTIM_CPT2CR_EXEV8CPT         HRTIM_CPT2CR_EXEV8CPT_Msk                /*!< External event 8 capture */
+#define HRTIM_CPT2CR_EXEV9CPT_Pos     (10U)
+#define HRTIM_CPT2CR_EXEV9CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV9CPT_Pos)     /*!< 0x00000400 */
+#define HRTIM_CPT2CR_EXEV9CPT         HRTIM_CPT2CR_EXEV9CPT_Msk                /*!< External event 9 capture */
+#define HRTIM_CPT2CR_EXEV10CPT_Pos    (11U)
+#define HRTIM_CPT2CR_EXEV10CPT_Msk    (0x1UL << HRTIM_CPT2CR_EXEV10CPT_Pos)    /*!< 0x00000800 */
+#define HRTIM_CPT2CR_EXEV10CPT        HRTIM_CPT2CR_EXEV10CPT_Msk               /*!< External event 10 capture */
+
+#define HRTIM_CPT2CR_TA1SET_Pos       (12U)
+#define HRTIM_CPT2CR_TA1SET_Msk       (0x1UL << HRTIM_CPT2CR_TA1SET_Pos)       /*!< 0x00001000 */
+#define HRTIM_CPT2CR_TA1SET           HRTIM_CPT2CR_TA1SET_Msk                  /*!< Timer A output 1 set */
+#define HRTIM_CPT2CR_TA1RST_Pos       (13U)
+#define HRTIM_CPT2CR_TA1RST_Msk       (0x1UL << HRTIM_CPT2CR_TA1RST_Pos)       /*!< 0x00002000 */
+#define HRTIM_CPT2CR_TA1RST           HRTIM_CPT2CR_TA1RST_Msk                  /*!< Timer A output 1 reset */
+#define HRTIM_CPT2CR_TIMACMP1_Pos     (14U)
+#define HRTIM_CPT2CR_TIMACMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMACMP1_Pos)     /*!< 0x00004000 */
+#define HRTIM_CPT2CR_TIMACMP1         HRTIM_CPT2CR_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_CPT2CR_TIMACMP2_Pos     (15U)
+#define HRTIM_CPT2CR_TIMACMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMACMP2_Pos)     /*!< 0x00008000 */
+#define HRTIM_CPT2CR_TIMACMP2         HRTIM_CPT2CR_TIMACMP2_Msk                /*!< Timer A compare 2 */
+
+#define HRTIM_CPT2CR_TB1SET_Pos       (16U)
+#define HRTIM_CPT2CR_TB1SET_Msk       (0x1UL << HRTIM_CPT2CR_TB1SET_Pos)       /*!< 0x00010000 */
+#define HRTIM_CPT2CR_TB1SET           HRTIM_CPT2CR_TB1SET_Msk                  /*!< Timer B output 1 set */
+#define HRTIM_CPT2CR_TB1RST_Pos       (17U)
+#define HRTIM_CPT2CR_TB1RST_Msk       (0x1UL << HRTIM_CPT2CR_TB1RST_Pos)       /*!< 0x00020000 */
+#define HRTIM_CPT2CR_TB1RST           HRTIM_CPT2CR_TB1RST_Msk                  /*!< Timer B output 1 reset */
+#define HRTIM_CPT2CR_TIMBCMP1_Pos     (18U)
+#define HRTIM_CPT2CR_TIMBCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMBCMP1_Pos)     /*!< 0x00040000 */
+#define HRTIM_CPT2CR_TIMBCMP1         HRTIM_CPT2CR_TIMBCMP1_Msk                /*!< Timer B compare 1 */
+#define HRTIM_CPT2CR_TIMBCMP2_Pos     (19U)
+#define HRTIM_CPT2CR_TIMBCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMBCMP2_Pos)     /*!< 0x00080000 */
+#define HRTIM_CPT2CR_TIMBCMP2         HRTIM_CPT2CR_TIMBCMP2_Msk                /*!< Timer B compare 2 */
+
+#define HRTIM_CPT2CR_TC1SET_Pos       (20U)
+#define HRTIM_CPT2CR_TC1SET_Msk       (0x1UL << HRTIM_CPT2CR_TC1SET_Pos)       /*!< 0x00100000 */
+#define HRTIM_CPT2CR_TC1SET           HRTIM_CPT2CR_TC1SET_Msk                  /*!< Timer C output 1 set */
+#define HRTIM_CPT2CR_TC1RST_Pos       (21U)
+#define HRTIM_CPT2CR_TC1RST_Msk       (0x1UL << HRTIM_CPT2CR_TC1RST_Pos)       /*!< 0x00200000 */
+#define HRTIM_CPT2CR_TC1RST           HRTIM_CPT2CR_TC1RST_Msk                  /*!< Timer C output 1 reset */
+#define HRTIM_CPT2CR_TIMCCMP1_Pos     (22U)
+#define HRTIM_CPT2CR_TIMCCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMCCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_CPT2CR_TIMCCMP1         HRTIM_CPT2CR_TIMCCMP1_Msk                /*!< Timer C compare 1 */
+#define HRTIM_CPT2CR_TIMCCMP2_Pos     (23U)
+#define HRTIM_CPT2CR_TIMCCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMCCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_CPT2CR_TIMCCMP2         HRTIM_CPT2CR_TIMCCMP2_Msk                /*!< Timer C compare 2 */
+
+#define HRTIM_CPT2CR_TD1SET_Pos       (24U)
+#define HRTIM_CPT2CR_TD1SET_Msk       (0x1UL << HRTIM_CPT2CR_TD1SET_Pos)       /*!< 0x01000000 */
+#define HRTIM_CPT2CR_TD1SET           HRTIM_CPT2CR_TD1SET_Msk                  /*!< Timer D output 1 set */
+#define HRTIM_CPT2CR_TD1RST_Pos       (25U)
+#define HRTIM_CPT2CR_TD1RST_Msk       (0x1UL << HRTIM_CPT2CR_TD1RST_Pos)       /*!< 0x02000000 */
+#define HRTIM_CPT2CR_TD1RST           HRTIM_CPT2CR_TD1RST_Msk                  /*!< Timer D output 1 reset */
+#define HRTIM_CPT2CR_TIMDCMP1_Pos     (26U)
+#define HRTIM_CPT2CR_TIMDCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMDCMP1_Pos)     /*!< 0x04000000 */
+#define HRTIM_CPT2CR_TIMDCMP1         HRTIM_CPT2CR_TIMDCMP1_Msk                /*!< Timer D compare 1 */
+#define HRTIM_CPT2CR_TIMDCMP2_Pos     (27U)
+#define HRTIM_CPT2CR_TIMDCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMDCMP2_Pos)     /*!< 0x08000000 */
+#define HRTIM_CPT2CR_TIMDCMP2         HRTIM_CPT2CR_TIMDCMP2_Msk                /*!< Timer D compare 2 */
+
+#define HRTIM_CPT2CR_TE1SET_Pos       (28U)
+#define HRTIM_CPT2CR_TE1SET_Msk       (0x1UL << HRTIM_CPT2CR_TE1SET_Pos)       /*!< 0x10000000 */
+#define HRTIM_CPT2CR_TE1SET           HRTIM_CPT2CR_TE1SET_Msk                  /*!< Timer E output 1 set */
+#define HRTIM_CPT2CR_TE1RST_Pos       (29U)
+#define HRTIM_CPT2CR_TE1RST_Msk       (0x1UL << HRTIM_CPT2CR_TE1RST_Pos)       /*!< 0x20000000 */
+#define HRTIM_CPT2CR_TE1RST           HRTIM_CPT2CR_TE1RST_Msk                  /*!< Timer E output 1 reset */
+#define HRTIM_CPT2CR_TIMECMP1_Pos     (30U)
+#define HRTIM_CPT2CR_TIMECMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMECMP1_Pos)     /*!< 0x40000000 */
+#define HRTIM_CPT2CR_TIMECMP1         HRTIM_CPT2CR_TIMECMP1_Msk                /*!< Timer E compare 1 */
+#define HRTIM_CPT2CR_TIMECMP2_Pos     (31U)
+#define HRTIM_CPT2CR_TIMECMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMECMP2_Pos)     /*!< 0x80000000 */
+#define HRTIM_CPT2CR_TIMECMP2         HRTIM_CPT2CR_TIMECMP2_Msk                /*!< Timer E compare 2 */
+
+/**** Bit definition for Slave Timer Output register **************************/
+#define HRTIM_OUTR_POL1_Pos           (1U)
+#define HRTIM_OUTR_POL1_Msk           (0x1UL << HRTIM_OUTR_POL1_Pos)           /*!< 0x00000002 */
+#define HRTIM_OUTR_POL1               HRTIM_OUTR_POL1_Msk                      /*!< Slave output 1 polarity */
+#define HRTIM_OUTR_IDLM1_Pos          (2U)
+#define HRTIM_OUTR_IDLM1_Msk          (0x1UL << HRTIM_OUTR_IDLM1_Pos)          /*!< 0x00000004 */
+#define HRTIM_OUTR_IDLM1              HRTIM_OUTR_IDLM1_Msk                     /*!< Slave output 1 idle mode */
+#define HRTIM_OUTR_IDLES1_Pos         (3U)
+#define HRTIM_OUTR_IDLES1_Msk         (0x1UL << HRTIM_OUTR_IDLES1_Pos)         /*!< 0x00000008 */
+#define HRTIM_OUTR_IDLES1             HRTIM_OUTR_IDLES1_Msk                    /*!< Slave output 1 idle state */
+#define HRTIM_OUTR_FAULT1_Pos         (4U)
+#define HRTIM_OUTR_FAULT1_Msk         (0x3UL << HRTIM_OUTR_FAULT1_Pos)         /*!< 0x00000030 */
+#define HRTIM_OUTR_FAULT1             HRTIM_OUTR_FAULT1_Msk                    /*!< Slave output 1 fault state */
+#define HRTIM_OUTR_FAULT1_0           (0x1UL << HRTIM_OUTR_FAULT1_Pos)          /*!< 0x00000010 */
+#define HRTIM_OUTR_FAULT1_1           (0x2UL << HRTIM_OUTR_FAULT1_Pos)          /*!< 0x00000020 */
+#define HRTIM_OUTR_CHP1_Pos           (6U)
+#define HRTIM_OUTR_CHP1_Msk           (0x1UL << HRTIM_OUTR_CHP1_Pos)           /*!< 0x00000040 */
+#define HRTIM_OUTR_CHP1               HRTIM_OUTR_CHP1_Msk                      /*!< Slave output 1 chopper enable */
+#define HRTIM_OUTR_DIDL1_Pos          (7U)
+#define HRTIM_OUTR_DIDL1_Msk          (0x1UL << HRTIM_OUTR_DIDL1_Pos)          /*!< 0x00000080 */
+#define HRTIM_OUTR_DIDL1              HRTIM_OUTR_DIDL1_Msk                     /*!< Slave output 1 dead time idle */
+
+#define HRTIM_OUTR_DTEN_Pos           (8U)
+#define HRTIM_OUTR_DTEN_Msk           (0x1UL << HRTIM_OUTR_DTEN_Pos)           /*!< 0x00000100 */
+#define HRTIM_OUTR_DTEN               HRTIM_OUTR_DTEN_Msk                      /*!< Slave output deadtime enable */
+#define HRTIM_OUTR_DLYPRTEN_Pos       (9U)
+#define HRTIM_OUTR_DLYPRTEN_Msk       (0x1UL << HRTIM_OUTR_DLYPRTEN_Pos)       /*!< 0x00000200 */
+#define HRTIM_OUTR_DLYPRTEN           HRTIM_OUTR_DLYPRTEN_Msk                  /*!< Slave output delay protection enable */
+#define HRTIM_OUTR_DLYPRT_Pos         (10U)
+#define HRTIM_OUTR_DLYPRT_Msk         (0x7UL << HRTIM_OUTR_DLYPRT_Pos)         /*!< 0x00001C00 */
+#define HRTIM_OUTR_DLYPRT             HRTIM_OUTR_DLYPRT_Msk                    /*!< Slave output delay protection */
+#define HRTIM_OUTR_DLYPRT_0           (0x1UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00000400 */
+#define HRTIM_OUTR_DLYPRT_1           (0x2UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00000800 */
+#define HRTIM_OUTR_DLYPRT_2           (0x4UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00001000 */
+
+#define HRTIM_OUTR_POL2_Pos           (17U)
+#define HRTIM_OUTR_POL2_Msk           (0x1UL << HRTIM_OUTR_POL2_Pos)           /*!< 0x00020000 */
+#define HRTIM_OUTR_POL2               HRTIM_OUTR_POL2_Msk                      /*!< Slave output 2 polarity */
+#define HRTIM_OUTR_IDLM2_Pos          (18U)
+#define HRTIM_OUTR_IDLM2_Msk          (0x1UL << HRTIM_OUTR_IDLM2_Pos)          /*!< 0x00040000 */
+#define HRTIM_OUTR_IDLM2              HRTIM_OUTR_IDLM2_Msk                     /*!< Slave output 2 idle mode */
+#define HRTIM_OUTR_IDLES2_Pos         (19U)
+#define HRTIM_OUTR_IDLES2_Msk         (0x1UL << HRTIM_OUTR_IDLES2_Pos)         /*!< 0x00080000 */
+#define HRTIM_OUTR_IDLES2             HRTIM_OUTR_IDLES2_Msk                    /*!< Slave output 2 idle state */
+#define HRTIM_OUTR_FAULT2_Pos         (20U)
+#define HRTIM_OUTR_FAULT2_Msk         (0x3UL << HRTIM_OUTR_FAULT2_Pos)         /*!< 0x00300000 */
+#define HRTIM_OUTR_FAULT2             HRTIM_OUTR_FAULT2_Msk                    /*!< Slave output 2 fault state */
+#define HRTIM_OUTR_FAULT2_0           (0x1UL << HRTIM_OUTR_FAULT2_Pos)          /*!< 0x00100000 */
+#define HRTIM_OUTR_FAULT2_1           (0x2UL << HRTIM_OUTR_FAULT2_Pos)          /*!< 0x00200000 */
+#define HRTIM_OUTR_CHP2_Pos           (22U)
+#define HRTIM_OUTR_CHP2_Msk           (0x1UL << HRTIM_OUTR_CHP2_Pos)           /*!< 0x00400000 */
+#define HRTIM_OUTR_CHP2               HRTIM_OUTR_CHP2_Msk                      /*!< Slave output 2 chopper enable */
+#define HRTIM_OUTR_DIDL2_Pos          (23U)
+#define HRTIM_OUTR_DIDL2_Msk          (0x1UL << HRTIM_OUTR_DIDL2_Pos)          /*!< 0x00800000 */
+#define HRTIM_OUTR_DIDL2              HRTIM_OUTR_DIDL2_Msk                     /*!< Slave output 2 dead time idle */
+
+/**** Bit definition for Slave Timer Fault register ***************************/
+#define HRTIM_FLTR_FLT1EN_Pos         (0U)
+#define HRTIM_FLTR_FLT1EN_Msk         (0x1UL << HRTIM_FLTR_FLT1EN_Pos)         /*!< 0x00000001 */
+#define HRTIM_FLTR_FLT1EN             HRTIM_FLTR_FLT1EN_Msk                    /*!< Fault 1 enable */
+#define HRTIM_FLTR_FLT2EN_Pos         (1U)
+#define HRTIM_FLTR_FLT2EN_Msk         (0x1UL << HRTIM_FLTR_FLT2EN_Pos)         /*!< 0x00000002 */
+#define HRTIM_FLTR_FLT2EN             HRTIM_FLTR_FLT2EN_Msk                    /*!< Fault 2 enable */
+#define HRTIM_FLTR_FLT3EN_Pos         (2U)
+#define HRTIM_FLTR_FLT3EN_Msk         (0x1UL << HRTIM_FLTR_FLT3EN_Pos)         /*!< 0x00000004 */
+#define HRTIM_FLTR_FLT3EN             HRTIM_FLTR_FLT3EN_Msk                    /*!< Fault 3 enable */
+#define HRTIM_FLTR_FLT4EN_Pos         (3U)
+#define HRTIM_FLTR_FLT4EN_Msk         (0x1UL << HRTIM_FLTR_FLT4EN_Pos)         /*!< 0x00000008 */
+#define HRTIM_FLTR_FLT4EN             HRTIM_FLTR_FLT4EN_Msk                    /*!< Fault 4 enable */
+#define HRTIM_FLTR_FLT5EN_Pos         (4U)
+#define HRTIM_FLTR_FLT5EN_Msk         (0x1UL << HRTIM_FLTR_FLT5EN_Pos)         /*!< 0x00000010 */
+#define HRTIM_FLTR_FLT5EN             HRTIM_FLTR_FLT5EN_Msk                    /*!< Fault 5 enable */
+#define HRTIM_FLTR_FLTLCK_Pos         (31U)
+#define HRTIM_FLTR_FLTLCK_Msk         (0x1UL << HRTIM_FLTR_FLTLCK_Pos)         /*!< 0x80000000 */
+#define HRTIM_FLTR_FLTLCK             HRTIM_FLTR_FLTLCK_Msk                    /*!< Fault sources lock */
+
+/**** Bit definition for Common HRTIM Timer control register 1 ****************/
+#define HRTIM_CR1_MUDIS_Pos           (0U)
+#define HRTIM_CR1_MUDIS_Msk           (0x1UL << HRTIM_CR1_MUDIS_Pos)           /*!< 0x00000001 */
+#define HRTIM_CR1_MUDIS               HRTIM_CR1_MUDIS_Msk                      /*!< Master update disable*/
+#define HRTIM_CR1_TAUDIS_Pos          (1U)
+#define HRTIM_CR1_TAUDIS_Msk          (0x1UL << HRTIM_CR1_TAUDIS_Pos)          /*!< 0x00000002 */
+#define HRTIM_CR1_TAUDIS              HRTIM_CR1_TAUDIS_Msk                     /*!< Timer A update disable*/
+#define HRTIM_CR1_TBUDIS_Pos          (2U)
+#define HRTIM_CR1_TBUDIS_Msk          (0x1UL << HRTIM_CR1_TBUDIS_Pos)          /*!< 0x00000004 */
+#define HRTIM_CR1_TBUDIS              HRTIM_CR1_TBUDIS_Msk                     /*!< Timer B update disable*/
+#define HRTIM_CR1_TCUDIS_Pos          (3U)
+#define HRTIM_CR1_TCUDIS_Msk          (0x1UL << HRTIM_CR1_TCUDIS_Pos)          /*!< 0x00000008 */
+#define HRTIM_CR1_TCUDIS              HRTIM_CR1_TCUDIS_Msk                     /*!< Timer C update disable*/
+#define HRTIM_CR1_TDUDIS_Pos          (4U)
+#define HRTIM_CR1_TDUDIS_Msk          (0x1UL << HRTIM_CR1_TDUDIS_Pos)          /*!< 0x00000010 */
+#define HRTIM_CR1_TDUDIS              HRTIM_CR1_TDUDIS_Msk                     /*!< Timer D update disable*/
+#define HRTIM_CR1_TEUDIS_Pos          (5U)
+#define HRTIM_CR1_TEUDIS_Msk          (0x1UL << HRTIM_CR1_TEUDIS_Pos)          /*!< 0x00000020 */
+#define HRTIM_CR1_TEUDIS              HRTIM_CR1_TEUDIS_Msk                     /*!< Timer E update disable*/
+#define HRTIM_CR1_ADC1USRC_Pos        (16U)
+#define HRTIM_CR1_ADC1USRC_Msk        (0x7UL << HRTIM_CR1_ADC1USRC_Pos)        /*!< 0x00070000 */
+#define HRTIM_CR1_ADC1USRC            HRTIM_CR1_ADC1USRC_Msk                   /*!< ADC Trigger 1 update source */
+#define HRTIM_CR1_ADC1USRC_0          (0x1UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00010000 */
+#define HRTIM_CR1_ADC1USRC_1          (0x2UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00020000 */
+#define HRTIM_CR1_ADC1USRC_2          (0x4UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00040000 */
+#define HRTIM_CR1_ADC2USRC_Pos        (19U)
+#define HRTIM_CR1_ADC2USRC_Msk        (0x7UL << HRTIM_CR1_ADC2USRC_Pos)        /*!< 0x00380000 */
+#define HRTIM_CR1_ADC2USRC            HRTIM_CR1_ADC2USRC_Msk                   /*!< ADC Trigger 2 update source */
+#define HRTIM_CR1_ADC2USRC_0          (0x1UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00080000 */
+#define HRTIM_CR1_ADC2USRC_1          (0x2UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00100000 */
+#define HRTIM_CR1_ADC2USRC_2          (0x4UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00200000 */
+#define HRTIM_CR1_ADC3USRC_Pos        (22U)
+#define HRTIM_CR1_ADC3USRC_Msk        (0x7UL << HRTIM_CR1_ADC3USRC_Pos)        /*!< 0x01C00000 */
+#define HRTIM_CR1_ADC3USRC            HRTIM_CR1_ADC3USRC_Msk                   /*!< ADC Trigger 3 update source */
+#define HRTIM_CR1_ADC3USRC_0          (0x1UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x00400000 */
+#define HRTIM_CR1_ADC3USRC_1          (0x2UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x00800000 */
+#define HRTIM_CR1_ADC3USRC_2          (0x4UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x01000000 */
+#define HRTIM_CR1_ADC4USRC_Pos        (25U)
+#define HRTIM_CR1_ADC4USRC_Msk        (0x7UL << HRTIM_CR1_ADC4USRC_Pos)        /*!< 0x0E000000 */
+#define HRTIM_CR1_ADC4USRC            HRTIM_CR1_ADC4USRC_Msk                   /*!< ADC Trigger 4 update source */
+#define HRTIM_CR1_ADC4USRC_0          (0x1UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x02000000 */
+#define HRTIM_CR1_ADC4USRC_1          (0x2UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x04000000 */
+#define HRTIM_CR1_ADC4USRC_2          (0x0UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x0800000 */
+
+/**** Bit definition for Common HRTIM Timer control register 2 ****************/
+#define HRTIM_CR2_MSWU_Pos            (0U)
+#define HRTIM_CR2_MSWU_Msk            (0x1UL << HRTIM_CR2_MSWU_Pos)            /*!< 0x00000001 */
+#define HRTIM_CR2_MSWU                HRTIM_CR2_MSWU_Msk                       /*!< Master software update */
+#define HRTIM_CR2_TASWU_Pos           (1U)
+#define HRTIM_CR2_TASWU_Msk           (0x1UL << HRTIM_CR2_TASWU_Pos)           /*!< 0x00000002 */
+#define HRTIM_CR2_TASWU               HRTIM_CR2_TASWU_Msk                      /*!< Timer A software update */
+#define HRTIM_CR2_TBSWU_Pos           (2U)
+#define HRTIM_CR2_TBSWU_Msk           (0x1UL << HRTIM_CR2_TBSWU_Pos)           /*!< 0x00000004 */
+#define HRTIM_CR2_TBSWU               HRTIM_CR2_TBSWU_Msk                      /*!< Timer B software update */
+#define HRTIM_CR2_TCSWU_Pos           (3U)
+#define HRTIM_CR2_TCSWU_Msk           (0x1UL << HRTIM_CR2_TCSWU_Pos)           /*!< 0x00000008 */
+#define HRTIM_CR2_TCSWU               HRTIM_CR2_TCSWU_Msk                      /*!< Timer C software update */
+#define HRTIM_CR2_TDSWU_Pos           (4U)
+#define HRTIM_CR2_TDSWU_Msk           (0x1UL << HRTIM_CR2_TDSWU_Pos)           /*!< 0x00000010 */
+#define HRTIM_CR2_TDSWU               HRTIM_CR2_TDSWU_Msk                      /*!< Timer D software update */
+#define HRTIM_CR2_TESWU_Pos           (5U)
+#define HRTIM_CR2_TESWU_Msk           (0x1UL << HRTIM_CR2_TESWU_Pos)           /*!< 0x00000020 */
+#define HRTIM_CR2_TESWU               HRTIM_CR2_TESWU_Msk                      /*!< Timer E software update */
+#define HRTIM_CR2_MRST_Pos            (8U)
+#define HRTIM_CR2_MRST_Msk            (0x1UL << HRTIM_CR2_MRST_Pos)            /*!< 0x00000100 */
+#define HRTIM_CR2_MRST                HRTIM_CR2_MRST_Msk                       /*!< Master count software reset */
+#define HRTIM_CR2_TARST_Pos           (9U)
+#define HRTIM_CR2_TARST_Msk           (0x1UL << HRTIM_CR2_TARST_Pos)           /*!< 0x00000200 */
+#define HRTIM_CR2_TARST               HRTIM_CR2_TARST_Msk                      /*!< Timer A count software reset */
+#define HRTIM_CR2_TBRST_Pos           (10U)
+#define HRTIM_CR2_TBRST_Msk           (0x1UL << HRTIM_CR2_TBRST_Pos)           /*!< 0x00000400 */
+#define HRTIM_CR2_TBRST               HRTIM_CR2_TBRST_Msk                      /*!< Timer B count software reset */
+#define HRTIM_CR2_TCRST_Pos           (11U)
+#define HRTIM_CR2_TCRST_Msk           (0x1UL << HRTIM_CR2_TCRST_Pos)           /*!< 0x00000800 */
+#define HRTIM_CR2_TCRST               HRTIM_CR2_TCRST_Msk                      /*!< Timer C count software reset */
+#define HRTIM_CR2_TDRST_Pos           (12U)
+#define HRTIM_CR2_TDRST_Msk           (0x1UL << HRTIM_CR2_TDRST_Pos)           /*!< 0x00001000 */
+#define HRTIM_CR2_TDRST               HRTIM_CR2_TDRST_Msk                      /*!< Timer D count software reset */
+#define HRTIM_CR2_TERST_Pos           (13U)
+#define HRTIM_CR2_TERST_Msk           (0x1UL << HRTIM_CR2_TERST_Pos)           /*!< 0x00002000 */
+#define HRTIM_CR2_TERST               HRTIM_CR2_TERST_Msk                      /*!< Timer E count software reset */
+
+/**** Bit definition for Common HRTIM Timer interrupt status register *********/
+#define HRTIM_ISR_FLT1_Pos            (0U)
+#define HRTIM_ISR_FLT1_Msk            (0x1UL << HRTIM_ISR_FLT1_Pos)            /*!< 0x00000001 */
+#define HRTIM_ISR_FLT1                HRTIM_ISR_FLT1_Msk                       /*!< Fault 1 interrupt flag */
+#define HRTIM_ISR_FLT2_Pos            (1U)
+#define HRTIM_ISR_FLT2_Msk            (0x1UL << HRTIM_ISR_FLT2_Pos)            /*!< 0x00000002 */
+#define HRTIM_ISR_FLT2                HRTIM_ISR_FLT2_Msk                       /*!< Fault 2 interrupt flag */
+#define HRTIM_ISR_FLT3_Pos            (2U)
+#define HRTIM_ISR_FLT3_Msk            (0x1UL << HRTIM_ISR_FLT3_Pos)            /*!< 0x00000004 */
+#define HRTIM_ISR_FLT3                HRTIM_ISR_FLT3_Msk                       /*!< Fault 3 interrupt flag */
+#define HRTIM_ISR_FLT4_Pos            (3U)
+#define HRTIM_ISR_FLT4_Msk            (0x1UL << HRTIM_ISR_FLT4_Pos)            /*!< 0x00000008 */
+#define HRTIM_ISR_FLT4                HRTIM_ISR_FLT4_Msk                       /*!< Fault 4 interrupt flag */
+#define HRTIM_ISR_FLT5_Pos            (4U)
+#define HRTIM_ISR_FLT5_Msk            (0x1UL << HRTIM_ISR_FLT5_Pos)            /*!< 0x00000010 */
+#define HRTIM_ISR_FLT5                HRTIM_ISR_FLT5_Msk                       /*!< Fault 5 interrupt flag */
+#define HRTIM_ISR_SYSFLT_Pos          (5U)
+#define HRTIM_ISR_SYSFLT_Msk          (0x1UL << HRTIM_ISR_SYSFLT_Pos)          /*!< 0x00000020 */
+#define HRTIM_ISR_SYSFLT              HRTIM_ISR_SYSFLT_Msk                     /*!< System Fault interrupt flag */
+#define HRTIM_ISR_BMPER_Pos           (17U)
+#define HRTIM_ISR_BMPER_Msk           (0x1UL << HRTIM_ISR_BMPER_Pos)           /*!< 0x00020000 */
+#define HRTIM_ISR_BMPER               HRTIM_ISR_BMPER_Msk                      /*!<  Burst mode period interrupt flag */
+
+/**** Bit definition for Common HRTIM Timer interrupt clear register **********/
+#define HRTIM_ICR_FLT1C_Pos           (0U)
+#define HRTIM_ICR_FLT1C_Msk           (0x1UL << HRTIM_ICR_FLT1C_Pos)           /*!< 0x00000001 */
+#define HRTIM_ICR_FLT1C               HRTIM_ICR_FLT1C_Msk                      /*!< Fault 1 interrupt flag clear */
+#define HRTIM_ICR_FLT2C_Pos           (1U)
+#define HRTIM_ICR_FLT2C_Msk           (0x1UL << HRTIM_ICR_FLT2C_Pos)           /*!< 0x00000002 */
+#define HRTIM_ICR_FLT2C               HRTIM_ICR_FLT2C_Msk                      /*!< Fault 2 interrupt flag clear */
+#define HRTIM_ICR_FLT3C_Pos           (2U)
+#define HRTIM_ICR_FLT3C_Msk           (0x1UL << HRTIM_ICR_FLT3C_Pos)           /*!< 0x00000004 */
+#define HRTIM_ICR_FLT3C               HRTIM_ICR_FLT3C_Msk                      /*!< Fault 3 interrupt flag clear */
+#define HRTIM_ICR_FLT4C_Pos           (3U)
+#define HRTIM_ICR_FLT4C_Msk           (0x1UL << HRTIM_ICR_FLT4C_Pos)           /*!< 0x00000008 */
+#define HRTIM_ICR_FLT4C               HRTIM_ICR_FLT4C_Msk                      /*!< Fault 4 interrupt flag clear */
+#define HRTIM_ICR_FLT5C_Pos           (4U)
+#define HRTIM_ICR_FLT5C_Msk           (0x1UL << HRTIM_ICR_FLT5C_Pos)           /*!< 0x00000010 */
+#define HRTIM_ICR_FLT5C               HRTIM_ICR_FLT5C_Msk                      /*!< Fault 5 interrupt flag clear */
+#define HRTIM_ICR_SYSFLTC_Pos         (5U)
+#define HRTIM_ICR_SYSFLTC_Msk         (0x1UL << HRTIM_ICR_SYSFLTC_Pos)         /*!< 0x00000020 */
+#define HRTIM_ICR_SYSFLTC             HRTIM_ICR_SYSFLTC_Msk                    /*!< System Fault interrupt flag clear */
+#define HRTIM_ICR_BMPERC_Pos          (17U)
+#define HRTIM_ICR_BMPERC_Msk          (0x1UL << HRTIM_ICR_BMPERC_Pos)          /*!< 0x00020000 */
+#define HRTIM_ICR_BMPERC              HRTIM_ICR_BMPERC_Msk                     /*!<  Burst mode period interrupt flag clear */
+
+/**** Bit definition for Common HRTIM Timer interrupt enable register *********/
+#define HRTIM_IER_FLT1_Pos            (0U)
+#define HRTIM_IER_FLT1_Msk            (0x1UL << HRTIM_IER_FLT1_Pos)            /*!< 0x00000001 */
+#define HRTIM_IER_FLT1                HRTIM_IER_FLT1_Msk                       /*!< Fault 1 interrupt enable */
+#define HRTIM_IER_FLT2_Pos            (1U)
+#define HRTIM_IER_FLT2_Msk            (0x1UL << HRTIM_IER_FLT2_Pos)            /*!< 0x00000002 */
+#define HRTIM_IER_FLT2                HRTIM_IER_FLT2_Msk                       /*!< Fault 2 interrupt enable */
+#define HRTIM_IER_FLT3_Pos            (2U)
+#define HRTIM_IER_FLT3_Msk            (0x1UL << HRTIM_IER_FLT3_Pos)            /*!< 0x00000004 */
+#define HRTIM_IER_FLT3                HRTIM_IER_FLT3_Msk                       /*!< Fault 3 interrupt enable */
+#define HRTIM_IER_FLT4_Pos            (3U)
+#define HRTIM_IER_FLT4_Msk            (0x1UL << HRTIM_IER_FLT4_Pos)            /*!< 0x00000008 */
+#define HRTIM_IER_FLT4                HRTIM_IER_FLT4_Msk                       /*!< Fault 4 interrupt enable */
+#define HRTIM_IER_FLT5_Pos            (4U)
+#define HRTIM_IER_FLT5_Msk            (0x1UL << HRTIM_IER_FLT5_Pos)            /*!< 0x00000010 */
+#define HRTIM_IER_FLT5                HRTIM_IER_FLT5_Msk                       /*!< Fault 5 interrupt enable */
+#define HRTIM_IER_SYSFLT_Pos          (5U)
+#define HRTIM_IER_SYSFLT_Msk          (0x1UL << HRTIM_IER_SYSFLT_Pos)          /*!< 0x00000020 */
+#define HRTIM_IER_SYSFLT              HRTIM_IER_SYSFLT_Msk                     /*!< System Fault interrupt enable */
+#define HRTIM_IER_BMPER_Pos           (17U)
+#define HRTIM_IER_BMPER_Msk           (0x1UL << HRTIM_IER_BMPER_Pos)           /*!< 0x00020000 */
+#define HRTIM_IER_BMPER               HRTIM_IER_BMPER_Msk                      /*!<  Burst mode period interrupt enable */
+
+/**** Bit definition for Common HRTIM Timer output enable register ************/
+#define HRTIM_OENR_TA1OEN_Pos         (0U)
+#define HRTIM_OENR_TA1OEN_Msk         (0x1UL << HRTIM_OENR_TA1OEN_Pos)         /*!< 0x00000001 */
+#define HRTIM_OENR_TA1OEN             HRTIM_OENR_TA1OEN_Msk                    /*!< Timer A Output 1 enable */
+#define HRTIM_OENR_TA2OEN_Pos         (1U)
+#define HRTIM_OENR_TA2OEN_Msk         (0x1UL << HRTIM_OENR_TA2OEN_Pos)         /*!< 0x00000002 */
+#define HRTIM_OENR_TA2OEN             HRTIM_OENR_TA2OEN_Msk                    /*!< Timer A Output 2 enable */
+#define HRTIM_OENR_TB1OEN_Pos         (2U)
+#define HRTIM_OENR_TB1OEN_Msk         (0x1UL << HRTIM_OENR_TB1OEN_Pos)         /*!< 0x00000004 */
+#define HRTIM_OENR_TB1OEN             HRTIM_OENR_TB1OEN_Msk                    /*!< Timer B Output 1 enable */
+#define HRTIM_OENR_TB2OEN_Pos         (3U)
+#define HRTIM_OENR_TB2OEN_Msk         (0x1UL << HRTIM_OENR_TB2OEN_Pos)         /*!< 0x00000008 */
+#define HRTIM_OENR_TB2OEN             HRTIM_OENR_TB2OEN_Msk                    /*!< Timer B Output 2 enable */
+#define HRTIM_OENR_TC1OEN_Pos         (4U)
+#define HRTIM_OENR_TC1OEN_Msk         (0x1UL << HRTIM_OENR_TC1OEN_Pos)         /*!< 0x00000010 */
+#define HRTIM_OENR_TC1OEN             HRTIM_OENR_TC1OEN_Msk                    /*!< Timer C Output 1 enable */
+#define HRTIM_OENR_TC2OEN_Pos         (5U)
+#define HRTIM_OENR_TC2OEN_Msk         (0x1UL << HRTIM_OENR_TC2OEN_Pos)         /*!< 0x00000020 */
+#define HRTIM_OENR_TC2OEN             HRTIM_OENR_TC2OEN_Msk                    /*!< Timer C Output 2 enable */
+#define HRTIM_OENR_TD1OEN_Pos         (6U)
+#define HRTIM_OENR_TD1OEN_Msk         (0x1UL << HRTIM_OENR_TD1OEN_Pos)         /*!< 0x00000040 */
+#define HRTIM_OENR_TD1OEN             HRTIM_OENR_TD1OEN_Msk                    /*!< Timer D Output 1 enable */
+#define HRTIM_OENR_TD2OEN_Pos         (7U)
+#define HRTIM_OENR_TD2OEN_Msk         (0x1UL << HRTIM_OENR_TD2OEN_Pos)         /*!< 0x00000080 */
+#define HRTIM_OENR_TD2OEN             HRTIM_OENR_TD2OEN_Msk                    /*!< Timer D Output 2 enable */
+#define HRTIM_OENR_TE1OEN_Pos         (8U)
+#define HRTIM_OENR_TE1OEN_Msk         (0x1UL << HRTIM_OENR_TE1OEN_Pos)         /*!< 0x00000100 */
+#define HRTIM_OENR_TE1OEN             HRTIM_OENR_TE1OEN_Msk                    /*!< Timer E Output 1 enable */
+#define HRTIM_OENR_TE2OEN_Pos         (9U)
+#define HRTIM_OENR_TE2OEN_Msk         (0x1UL << HRTIM_OENR_TE2OEN_Pos)         /*!< 0x00000200 */
+#define HRTIM_OENR_TE2OEN             HRTIM_OENR_TE2OEN_Msk                    /*!< Timer E Output 2 enable */
+
+/**** Bit definition for Common HRTIM Timer output disable register ***********/
+#define HRTIM_ODISR_TA1ODIS_Pos       (0U)
+#define HRTIM_ODISR_TA1ODIS_Msk       (0x1UL << HRTIM_ODISR_TA1ODIS_Pos)       /*!< 0x00000001 */
+#define HRTIM_ODISR_TA1ODIS           HRTIM_ODISR_TA1ODIS_Msk                  /*!< Timer A Output 1 disable */
+#define HRTIM_ODISR_TA2ODIS_Pos       (1U)
+#define HRTIM_ODISR_TA2ODIS_Msk       (0x1UL << HRTIM_ODISR_TA2ODIS_Pos)       /*!< 0x00000002 */
+#define HRTIM_ODISR_TA2ODIS           HRTIM_ODISR_TA2ODIS_Msk                  /*!< Timer A Output 2 disable */
+#define HRTIM_ODISR_TB1ODIS_Pos       (2U)
+#define HRTIM_ODISR_TB1ODIS_Msk       (0x1UL << HRTIM_ODISR_TB1ODIS_Pos)       /*!< 0x00000004 */
+#define HRTIM_ODISR_TB1ODIS           HRTIM_ODISR_TB1ODIS_Msk                  /*!< Timer B Output 1 disable */
+#define HRTIM_ODISR_TB2ODIS_Pos       (3U)
+#define HRTIM_ODISR_TB2ODIS_Msk       (0x1UL << HRTIM_ODISR_TB2ODIS_Pos)       /*!< 0x00000008 */
+#define HRTIM_ODISR_TB2ODIS           HRTIM_ODISR_TB2ODIS_Msk                  /*!< Timer B Output 2 disable */
+#define HRTIM_ODISR_TC1ODIS_Pos       (4U)
+#define HRTIM_ODISR_TC1ODIS_Msk       (0x1UL << HRTIM_ODISR_TC1ODIS_Pos)       /*!< 0x00000010 */
+#define HRTIM_ODISR_TC1ODIS           HRTIM_ODISR_TC1ODIS_Msk                  /*!< Timer C Output 1 disable */
+#define HRTIM_ODISR_TC2ODIS_Pos       (5U)
+#define HRTIM_ODISR_TC2ODIS_Msk       (0x1UL << HRTIM_ODISR_TC2ODIS_Pos)       /*!< 0x00000020 */
+#define HRTIM_ODISR_TC2ODIS           HRTIM_ODISR_TC2ODIS_Msk                  /*!< Timer C Output 2 disable */
+#define HRTIM_ODISR_TD1ODIS_Pos       (6U)
+#define HRTIM_ODISR_TD1ODIS_Msk       (0x1UL << HRTIM_ODISR_TD1ODIS_Pos)       /*!< 0x00000040 */
+#define HRTIM_ODISR_TD1ODIS           HRTIM_ODISR_TD1ODIS_Msk                  /*!< Timer D Output 1 disable */
+#define HRTIM_ODISR_TD2ODIS_Pos       (7U)
+#define HRTIM_ODISR_TD2ODIS_Msk       (0x1UL << HRTIM_ODISR_TD2ODIS_Pos)       /*!< 0x00000080 */
+#define HRTIM_ODISR_TD2ODIS           HRTIM_ODISR_TD2ODIS_Msk                  /*!< Timer D Output 2 disable */
+#define HRTIM_ODISR_TE1ODIS_Pos       (8U)
+#define HRTIM_ODISR_TE1ODIS_Msk       (0x1UL << HRTIM_ODISR_TE1ODIS_Pos)       /*!< 0x00000100 */
+#define HRTIM_ODISR_TE1ODIS           HRTIM_ODISR_TE1ODIS_Msk                  /*!< Timer E Output 1 disable */
+#define HRTIM_ODISR_TE2ODIS_Pos       (9U)
+#define HRTIM_ODISR_TE2ODIS_Msk       (0x1UL << HRTIM_ODISR_TE2ODIS_Pos)       /*!< 0x00000200 */
+#define HRTIM_ODISR_TE2ODIS           HRTIM_ODISR_TE2ODIS_Msk                  /*!< Timer E Output 2 disable */
+
+/**** Bit definition for Common HRTIM Timer output disable status register *****/
+#define HRTIM_ODSR_TA1ODS_Pos         (0U)
+#define HRTIM_ODSR_TA1ODS_Msk         (0x1UL << HRTIM_ODSR_TA1ODS_Pos)         /*!< 0x00000001 */
+#define HRTIM_ODSR_TA1ODS             HRTIM_ODSR_TA1ODS_Msk                    /*!< Timer A Output 1 disable status */
+#define HRTIM_ODSR_TA2ODS_Pos         (1U)
+#define HRTIM_ODSR_TA2ODS_Msk         (0x1UL << HRTIM_ODSR_TA2ODS_Pos)         /*!< 0x00000002 */
+#define HRTIM_ODSR_TA2ODS             HRTIM_ODSR_TA2ODS_Msk                    /*!< Timer A Output 2 disable status */
+#define HRTIM_ODSR_TB1ODS_Pos         (2U)
+#define HRTIM_ODSR_TB1ODS_Msk         (0x1UL << HRTIM_ODSR_TB1ODS_Pos)         /*!< 0x00000004 */
+#define HRTIM_ODSR_TB1ODS             HRTIM_ODSR_TB1ODS_Msk                    /*!< Timer B Output 1 disable status */
+#define HRTIM_ODSR_TB2ODS_Pos         (3U)
+#define HRTIM_ODSR_TB2ODS_Msk         (0x1UL << HRTIM_ODSR_TB2ODS_Pos)         /*!< 0x00000008 */
+#define HRTIM_ODSR_TB2ODS             HRTIM_ODSR_TB2ODS_Msk                    /*!< Timer B Output 2 disable status */
+#define HRTIM_ODSR_TC1ODS_Pos         (4U)
+#define HRTIM_ODSR_TC1ODS_Msk         (0x1UL << HRTIM_ODSR_TC1ODS_Pos)         /*!< 0x00000010 */
+#define HRTIM_ODSR_TC1ODS             HRTIM_ODSR_TC1ODS_Msk                    /*!< Timer C Output 1 disable status */
+#define HRTIM_ODSR_TC2ODS_Pos         (5U)
+#define HRTIM_ODSR_TC2ODS_Msk         (0x1UL << HRTIM_ODSR_TC2ODS_Pos)         /*!< 0x00000020 */
+#define HRTIM_ODSR_TC2ODS             HRTIM_ODSR_TC2ODS_Msk                    /*!< Timer C Output 2 disable status */
+#define HRTIM_ODSR_TD1ODS_Pos         (6U)
+#define HRTIM_ODSR_TD1ODS_Msk         (0x1UL << HRTIM_ODSR_TD1ODS_Pos)         /*!< 0x00000040 */
+#define HRTIM_ODSR_TD1ODS             HRTIM_ODSR_TD1ODS_Msk                    /*!< Timer D Output 1 disable status */
+#define HRTIM_ODSR_TD2ODS_Pos         (7U)
+#define HRTIM_ODSR_TD2ODS_Msk         (0x1UL << HRTIM_ODSR_TD2ODS_Pos)         /*!< 0x00000080 */
+#define HRTIM_ODSR_TD2ODS             HRTIM_ODSR_TD2ODS_Msk                    /*!< Timer D Output 2 disable status */
+#define HRTIM_ODSR_TE1ODS_Pos         (8U)
+#define HRTIM_ODSR_TE1ODS_Msk         (0x1UL << HRTIM_ODSR_TE1ODS_Pos)         /*!< 0x00000100 */
+#define HRTIM_ODSR_TE1ODS             HRTIM_ODSR_TE1ODS_Msk                    /*!< Timer E Output 1 disable status */
+#define HRTIM_ODSR_TE2ODS_Pos         (9U)
+#define HRTIM_ODSR_TE2ODS_Msk         (0x1UL << HRTIM_ODSR_TE2ODS_Pos)         /*!< 0x00000200 */
+#define HRTIM_ODSR_TE2ODS             HRTIM_ODSR_TE2ODS_Msk                    /*!< Timer E Output 2 disable status */
+
+/**** Bit definition for Common HRTIM Timer Burst mode control register ********/
+#define HRTIM_BMCR_BME_Pos            (0U)
+#define HRTIM_BMCR_BME_Msk            (0x1UL << HRTIM_BMCR_BME_Pos)            /*!< 0x00000001 */
+#define HRTIM_BMCR_BME                HRTIM_BMCR_BME_Msk                       /*!< Burst mode enbale */
+#define HRTIM_BMCR_BMOM_Pos           (1U)
+#define HRTIM_BMCR_BMOM_Msk           (0x1UL << HRTIM_BMCR_BMOM_Pos)           /*!< 0x00000002 */
+#define HRTIM_BMCR_BMOM               HRTIM_BMCR_BMOM_Msk                      /*!< Burst mode operating mode */
+#define HRTIM_BMCR_BMCLK_Pos          (2U)
+#define HRTIM_BMCR_BMCLK_Msk          (0xFUL << HRTIM_BMCR_BMCLK_Pos)          /*!< 0x0000003C */
+#define HRTIM_BMCR_BMCLK              HRTIM_BMCR_BMCLK_Msk                     /*!< Burst mode clock source */
+#define HRTIM_BMCR_BMCLK_0            (0x1UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000004 */
+#define HRTIM_BMCR_BMCLK_1            (0x2UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000008 */
+#define HRTIM_BMCR_BMCLK_2            (0x4UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000010 */
+#define HRTIM_BMCR_BMCLK_3            (0x8UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000020 */
+#define HRTIM_BMCR_BMPRSC_Pos         (6U)
+#define HRTIM_BMCR_BMPRSC_Msk         (0xFUL << HRTIM_BMCR_BMPRSC_Pos)         /*!< 0x000003C0 */
+#define HRTIM_BMCR_BMPRSC             HRTIM_BMCR_BMPRSC_Msk                    /*!< Burst mode prescaler */
+#define HRTIM_BMCR_BMPRSC_0           (0x1UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000040 */
+#define HRTIM_BMCR_BMPRSC_1           (0x2UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000080 */
+#define HRTIM_BMCR_BMPRSC_2           (0x4UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000100 */
+#define HRTIM_BMCR_BMPRSC_3           (0x8UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000200 */
+#define HRTIM_BMCR_BMPREN_Pos         (10U)
+#define HRTIM_BMCR_BMPREN_Msk         (0x1UL << HRTIM_BMCR_BMPREN_Pos)         /*!< 0x00000400 */
+#define HRTIM_BMCR_BMPREN             HRTIM_BMCR_BMPREN_Msk                    /*!< Burst mode Preload bit */
+#define HRTIM_BMCR_MTBM_Pos           (16U)
+#define HRTIM_BMCR_MTBM_Msk           (0x1UL << HRTIM_BMCR_MTBM_Pos)           /*!< 0x00010000 */
+#define HRTIM_BMCR_MTBM               HRTIM_BMCR_MTBM_Msk                      /*!< Master Timer Burst mode */
+#define HRTIM_BMCR_TABM_Pos           (17U)
+#define HRTIM_BMCR_TABM_Msk           (0x1UL << HRTIM_BMCR_TABM_Pos)           /*!< 0x00020000 */
+#define HRTIM_BMCR_TABM               HRTIM_BMCR_TABM_Msk                      /*!< Timer A Burst mode */
+#define HRTIM_BMCR_TBBM_Pos           (18U)
+#define HRTIM_BMCR_TBBM_Msk           (0x1UL << HRTIM_BMCR_TBBM_Pos)           /*!< 0x00040000 */
+#define HRTIM_BMCR_TBBM               HRTIM_BMCR_TBBM_Msk                      /*!< Timer B Burst mode */
+#define HRTIM_BMCR_TCBM_Pos           (19U)
+#define HRTIM_BMCR_TCBM_Msk           (0x1UL << HRTIM_BMCR_TCBM_Pos)           /*!< 0x00080000 */
+#define HRTIM_BMCR_TCBM               HRTIM_BMCR_TCBM_Msk                      /*!< Timer C Burst mode */
+#define HRTIM_BMCR_TDBM_Pos           (20U)
+#define HRTIM_BMCR_TDBM_Msk           (0x1UL << HRTIM_BMCR_TDBM_Pos)           /*!< 0x00100000 */
+#define HRTIM_BMCR_TDBM               HRTIM_BMCR_TDBM_Msk                      /*!< Timer D Burst mode */
+#define HRTIM_BMCR_TEBM_Pos           (21U)
+#define HRTIM_BMCR_TEBM_Msk           (0x1UL << HRTIM_BMCR_TEBM_Pos)           /*!< 0x00200000 */
+#define HRTIM_BMCR_TEBM               HRTIM_BMCR_TEBM_Msk                      /*!< Timer E Burst mode */
+#define HRTIM_BMCR_BMSTAT_Pos         (31U)
+#define HRTIM_BMCR_BMSTAT_Msk         (0x1UL << HRTIM_BMCR_BMSTAT_Pos)         /*!< 0x80000000 */
+#define HRTIM_BMCR_BMSTAT             HRTIM_BMCR_BMSTAT_Msk                    /*!< Burst mode status */
+
+/**** Bit definition for Common HRTIM Timer Burst mode Trigger register *******/
+#define HRTIM_BMTRGR_SW_Pos           (0U)
+#define HRTIM_BMTRGR_SW_Msk           (0x1UL << HRTIM_BMTRGR_SW_Pos)           /*!< 0x00000001 */
+#define HRTIM_BMTRGR_SW               HRTIM_BMTRGR_SW_Msk                      /*!< Software start */
+#define HRTIM_BMTRGR_MSTRST_Pos       (1U)
+#define HRTIM_BMTRGR_MSTRST_Msk       (0x1UL << HRTIM_BMTRGR_MSTRST_Pos)       /*!< 0x00000002 */
+#define HRTIM_BMTRGR_MSTRST           HRTIM_BMTRGR_MSTRST_Msk                  /*!<  Master reset */
+#define HRTIM_BMTRGR_MSTREP_Pos       (2U)
+#define HRTIM_BMTRGR_MSTREP_Msk       (0x1UL << HRTIM_BMTRGR_MSTREP_Pos)       /*!< 0x00000004 */
+#define HRTIM_BMTRGR_MSTREP           HRTIM_BMTRGR_MSTREP_Msk                  /*!<  Master repetition */
+#define HRTIM_BMTRGR_MSTCMP1_Pos      (3U)
+#define HRTIM_BMTRGR_MSTCMP1_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP1_Pos)      /*!< 0x00000008 */
+#define HRTIM_BMTRGR_MSTCMP1          HRTIM_BMTRGR_MSTCMP1_Msk                 /*!<  Master compare 1 */
+#define HRTIM_BMTRGR_MSTCMP2_Pos      (4U)
+#define HRTIM_BMTRGR_MSTCMP2_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP2_Pos)      /*!< 0x00000010 */
+#define HRTIM_BMTRGR_MSTCMP2          HRTIM_BMTRGR_MSTCMP2_Msk                 /*!< Master compare 2  */
+#define HRTIM_BMTRGR_MSTCMP3_Pos      (5U)
+#define HRTIM_BMTRGR_MSTCMP3_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP3_Pos)      /*!< 0x00000020 */
+#define HRTIM_BMTRGR_MSTCMP3          HRTIM_BMTRGR_MSTCMP3_Msk                 /*!< Master compare 3 */
+#define HRTIM_BMTRGR_MSTCMP4_Pos      (6U)
+#define HRTIM_BMTRGR_MSTCMP4_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP4_Pos)      /*!< 0x00000040 */
+#define HRTIM_BMTRGR_MSTCMP4          HRTIM_BMTRGR_MSTCMP4_Msk                 /*!< Master compare 4 */
+#define HRTIM_BMTRGR_TARST_Pos        (7U)
+#define HRTIM_BMTRGR_TARST_Msk        (0x1UL << HRTIM_BMTRGR_TARST_Pos)        /*!< 0x00000080 */
+#define HRTIM_BMTRGR_TARST            HRTIM_BMTRGR_TARST_Msk                   /*!< Timer A reset  */
+#define HRTIM_BMTRGR_TAREP_Pos        (8U)
+#define HRTIM_BMTRGR_TAREP_Msk        (0x1UL << HRTIM_BMTRGR_TAREP_Pos)        /*!< 0x00000100 */
+#define HRTIM_BMTRGR_TAREP            HRTIM_BMTRGR_TAREP_Msk                   /*!< Timer A repetition  */
+#define HRTIM_BMTRGR_TACMP1_Pos       (9U)
+#define HRTIM_BMTRGR_TACMP1_Msk       (0x1UL << HRTIM_BMTRGR_TACMP1_Pos)       /*!< 0x00000200 */
+#define HRTIM_BMTRGR_TACMP1           HRTIM_BMTRGR_TACMP1_Msk                  /*!< Timer A compare 1  */
+#define HRTIM_BMTRGR_TACMP2_Pos       (10U)
+#define HRTIM_BMTRGR_TACMP2_Msk       (0x1UL << HRTIM_BMTRGR_TACMP2_Pos)       /*!< 0x00000400 */
+#define HRTIM_BMTRGR_TACMP2           HRTIM_BMTRGR_TACMP2_Msk                  /*!< Timer A compare 2  */
+#define HRTIM_BMTRGR_TBRST_Pos        (11U)
+#define HRTIM_BMTRGR_TBRST_Msk        (0x1UL << HRTIM_BMTRGR_TBRST_Pos)        /*!< 0x00000800 */
+#define HRTIM_BMTRGR_TBRST            HRTIM_BMTRGR_TBRST_Msk                   /*!< Timer B reset  */
+#define HRTIM_BMTRGR_TBREP_Pos        (12U)
+#define HRTIM_BMTRGR_TBREP_Msk        (0x1UL << HRTIM_BMTRGR_TBREP_Pos)        /*!< 0x00001000 */
+#define HRTIM_BMTRGR_TBREP            HRTIM_BMTRGR_TBREP_Msk                   /*!< Timer B repetition  */
+#define HRTIM_BMTRGR_TBCMP1_Pos       (13U)
+#define HRTIM_BMTRGR_TBCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TBCMP1_Pos)       /*!< 0x00002000 */
+#define HRTIM_BMTRGR_TBCMP1           HRTIM_BMTRGR_TBCMP1_Msk                  /*!< Timer B compare 1 */
+#define HRTIM_BMTRGR_TBCMP2_Pos       (14U)
+#define HRTIM_BMTRGR_TBCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TBCMP2_Pos)       /*!< 0x00004000 */
+#define HRTIM_BMTRGR_TBCMP2           HRTIM_BMTRGR_TBCMP2_Msk                  /*!< Timer B compare 2 */
+#define HRTIM_BMTRGR_TCRST_Pos        (15U)
+#define HRTIM_BMTRGR_TCRST_Msk        (0x1UL << HRTIM_BMTRGR_TCRST_Pos)        /*!< 0x00008000 */
+#define HRTIM_BMTRGR_TCRST            HRTIM_BMTRGR_TCRST_Msk                   /*!< Timer C reset  */
+#define HRTIM_BMTRGR_TCREP_Pos        (16U)
+#define HRTIM_BMTRGR_TCREP_Msk        (0x1UL << HRTIM_BMTRGR_TCREP_Pos)        /*!< 0x00010000 */
+#define HRTIM_BMTRGR_TCREP            HRTIM_BMTRGR_TCREP_Msk                   /*!< Timer C repetition */
+#define HRTIM_BMTRGR_TCCMP1_Pos       (17U)
+#define HRTIM_BMTRGR_TCCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TCCMP1_Pos)       /*!< 0x00020000 */
+#define HRTIM_BMTRGR_TCCMP1           HRTIM_BMTRGR_TCCMP1_Msk                  /*!< Timer C compare 1 */
+#define HRTIM_BMTRGR_TCCMP2_Pos       (18U)
+#define HRTIM_BMTRGR_TCCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TCCMP2_Pos)       /*!< 0x00040000 */
+#define HRTIM_BMTRGR_TCCMP2           HRTIM_BMTRGR_TCCMP2_Msk                  /*!< Timer C compare 2 */
+#define HRTIM_BMTRGR_TDRST_Pos        (19U)
+#define HRTIM_BMTRGR_TDRST_Msk        (0x1UL << HRTIM_BMTRGR_TDRST_Pos)        /*!< 0x00080000 */
+#define HRTIM_BMTRGR_TDRST            HRTIM_BMTRGR_TDRST_Msk                   /*!< Timer D reset  */
+#define HRTIM_BMTRGR_TDREP_Pos        (20U)
+#define HRTIM_BMTRGR_TDREP_Msk        (0x1UL << HRTIM_BMTRGR_TDREP_Pos)        /*!< 0x00100000 */
+#define HRTIM_BMTRGR_TDREP            HRTIM_BMTRGR_TDREP_Msk                   /*!< Timer D repetition  */
+#define HRTIM_BMTRGR_TDCMP1_Pos       (21U)
+#define HRTIM_BMTRGR_TDCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TDCMP1_Pos)       /*!< 0x00200000 */
+#define HRTIM_BMTRGR_TDCMP1           HRTIM_BMTRGR_TDCMP1_Msk                  /*!< Timer D compare 1 */
+#define HRTIM_BMTRGR_TDCMP2_Pos       (22U)
+#define HRTIM_BMTRGR_TDCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TDCMP2_Pos)       /*!< 0x00400000 */
+#define HRTIM_BMTRGR_TDCMP2           HRTIM_BMTRGR_TDCMP2_Msk                  /*!< Timer D compare 2 */
+#define HRTIM_BMTRGR_TERST_Pos        (23U)
+#define HRTIM_BMTRGR_TERST_Msk        (0x1UL << HRTIM_BMTRGR_TERST_Pos)        /*!< 0x00800000 */
+#define HRTIM_BMTRGR_TERST            HRTIM_BMTRGR_TERST_Msk                   /*!< Timer E reset  */
+#define HRTIM_BMTRGR_TEREP_Pos        (24U)
+#define HRTIM_BMTRGR_TEREP_Msk        (0x1UL << HRTIM_BMTRGR_TEREP_Pos)        /*!< 0x01000000 */
+#define HRTIM_BMTRGR_TEREP            HRTIM_BMTRGR_TEREP_Msk                   /*!< Timer E repetition  */
+#define HRTIM_BMTRGR_TECMP1_Pos       (25U)
+#define HRTIM_BMTRGR_TECMP1_Msk       (0x1UL << HRTIM_BMTRGR_TECMP1_Pos)       /*!< 0x02000000 */
+#define HRTIM_BMTRGR_TECMP1           HRTIM_BMTRGR_TECMP1_Msk                  /*!< Timer E compare 1 */
+#define HRTIM_BMTRGR_TECMP2_Pos       (26U)
+#define HRTIM_BMTRGR_TECMP2_Msk       (0x1UL << HRTIM_BMTRGR_TECMP2_Pos)       /*!< 0x04000000 */
+#define HRTIM_BMTRGR_TECMP2           HRTIM_BMTRGR_TECMP2_Msk                  /*!< Timer E compare 2 */
+#define HRTIM_BMTRGR_TAEEV7_Pos       (27U)
+#define HRTIM_BMTRGR_TAEEV7_Msk       (0x1UL << HRTIM_BMTRGR_TAEEV7_Pos)       /*!< 0x08000000 */
+#define HRTIM_BMTRGR_TAEEV7           HRTIM_BMTRGR_TAEEV7_Msk                  /*!< Timer A period following External Event7  */
+#define HRTIM_BMTRGR_TDEEV8_Pos       (28U)
+#define HRTIM_BMTRGR_TDEEV8_Msk       (0x1UL << HRTIM_BMTRGR_TDEEV8_Pos)       /*!< 0x10000000 */
+#define HRTIM_BMTRGR_TDEEV8           HRTIM_BMTRGR_TDEEV8_Msk                  /*!< Timer D period following External Event8  */
+#define HRTIM_BMTRGR_EEV7_Pos         (29U)
+#define HRTIM_BMTRGR_EEV7_Msk         (0x1UL << HRTIM_BMTRGR_EEV7_Pos)         /*!< 0x20000000 */
+#define HRTIM_BMTRGR_EEV7             HRTIM_BMTRGR_EEV7_Msk                    /*!< External Event 7 */
+#define HRTIM_BMTRGR_EEV8_Pos         (30U)
+#define HRTIM_BMTRGR_EEV8_Msk         (0x1UL << HRTIM_BMTRGR_EEV8_Pos)         /*!< 0x40000000 */
+#define HRTIM_BMTRGR_EEV8             HRTIM_BMTRGR_EEV8_Msk                    /*!< External Event 8 */
+#define HRTIM_BMTRGR_OCHPEV_Pos       (31U)
+#define HRTIM_BMTRGR_OCHPEV_Msk       (0x1UL << HRTIM_BMTRGR_OCHPEV_Pos)       /*!< 0x80000000 */
+#define HRTIM_BMTRGR_OCHPEV           HRTIM_BMTRGR_OCHPEV_Msk                  /*!< on-chip Event */
+
+/*******************  Bit definition for HRTIM_BMCMPR register  ***************/
+#define HRTIM_BMCMPR_BMCMPR_Pos       (0U)
+#define HRTIM_BMCMPR_BMCMPR_Msk       (0xFFFFUL << HRTIM_BMCMPR_BMCMPR_Pos)    /*!< 0x0000FFFF */
+#define HRTIM_BMCMPR_BMCMPR           HRTIM_BMCMPR_BMCMPR_Msk                  /*!<!<Burst Compare Value */
+
+/*******************  Bit definition for HRTIM_BMPER register  ****************/
+#define HRTIM_BMPER_BMPER_Pos         (0U)
+#define HRTIM_BMPER_BMPER_Msk         (0xFFFFUL << HRTIM_BMPER_BMPER_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_BMPER_BMPER             HRTIM_BMPER_BMPER_Msk                    /*!<!<Burst period Value */
+
+/*******************  Bit definition for HRTIM_EECR1 register  ****************/
+#define HRTIM_EECR1_EE1SRC_Pos        (0U)
+#define HRTIM_EECR1_EE1SRC_Msk        (0x3UL << HRTIM_EECR1_EE1SRC_Pos)        /*!< 0x00000003 */
+#define HRTIM_EECR1_EE1SRC            HRTIM_EECR1_EE1SRC_Msk                   /*!< External event 1 source */
+#define HRTIM_EECR1_EE1SRC_0          (0x1UL << HRTIM_EECR1_EE1SRC_Pos)         /*!< 0x00000001 */
+#define HRTIM_EECR1_EE1SRC_1          (0x2UL << HRTIM_EECR1_EE1SRC_Pos)         /*!< 0x00000002 */
+#define HRTIM_EECR1_EE1POL_Pos        (2U)
+#define HRTIM_EECR1_EE1POL_Msk        (0x1UL << HRTIM_EECR1_EE1POL_Pos)        /*!< 0x00000004 */
+#define HRTIM_EECR1_EE1POL            HRTIM_EECR1_EE1POL_Msk                   /*!< External event 1 Polarity */
+#define HRTIM_EECR1_EE1SNS_Pos        (3U)
+#define HRTIM_EECR1_EE1SNS_Msk        (0x3UL << HRTIM_EECR1_EE1SNS_Pos)        /*!< 0x00000018 */
+#define HRTIM_EECR1_EE1SNS            HRTIM_EECR1_EE1SNS_Msk                   /*!< External event 1 sensitivity */
+#define HRTIM_EECR1_EE1SNS_0          (0x1UL << HRTIM_EECR1_EE1SNS_Pos)         /*!< 0x00000008 */
+#define HRTIM_EECR1_EE1SNS_1          (0x2UL << HRTIM_EECR1_EE1SNS_Pos)         /*!< 0x00000010 */
+#define HRTIM_EECR1_EE1FAST_Pos       (5U)
+#define HRTIM_EECR1_EE1FAST_Msk       (0x1UL << HRTIM_EECR1_EE1FAST_Pos)       /*!< 0x00000020 */
+#define HRTIM_EECR1_EE1FAST           HRTIM_EECR1_EE1FAST_Msk                  /*!< External event 1 Fast mode */
+
+#define HRTIM_EECR1_EE2SRC_Pos        (6U)
+#define HRTIM_EECR1_EE2SRC_Msk        (0x3UL << HRTIM_EECR1_EE2SRC_Pos)        /*!< 0x000000C0 */
+#define HRTIM_EECR1_EE2SRC            HRTIM_EECR1_EE2SRC_Msk                   /*!< External event 2 source */
+#define HRTIM_EECR1_EE2SRC_0          (0x1UL << HRTIM_EECR1_EE2SRC_Pos)         /*!< 0x00000040 */
+#define HRTIM_EECR1_EE2SRC_1          (0x2UL << HRTIM_EECR1_EE2SRC_Pos)         /*!< 0x00000080 */
+#define HRTIM_EECR1_EE2POL_Pos        (8U)
+#define HRTIM_EECR1_EE2POL_Msk        (0x1UL << HRTIM_EECR1_EE2POL_Pos)        /*!< 0x00000100 */
+#define HRTIM_EECR1_EE2POL            HRTIM_EECR1_EE2POL_Msk                   /*!< External event 2 Polarity */
+#define HRTIM_EECR1_EE2SNS_Pos        (9U)
+#define HRTIM_EECR1_EE2SNS_Msk        (0x3UL << HRTIM_EECR1_EE2SNS_Pos)        /*!< 0x00000600 */
+#define HRTIM_EECR1_EE2SNS            HRTIM_EECR1_EE2SNS_Msk                   /*!< External event 2 sensitivity */
+#define HRTIM_EECR1_EE2SNS_0          (0x1UL << HRTIM_EECR1_EE2SNS_Pos)         /*!< 0x00000200 */
+#define HRTIM_EECR1_EE2SNS_1          (0x2UL << HRTIM_EECR1_EE2SNS_Pos)         /*!< 0x00000400 */
+#define HRTIM_EECR1_EE2FAST_Pos       (11U)
+#define HRTIM_EECR1_EE2FAST_Msk       (0x1UL << HRTIM_EECR1_EE2FAST_Pos)       /*!< 0x00000800 */
+#define HRTIM_EECR1_EE2FAST           HRTIM_EECR1_EE2FAST_Msk                  /*!< External event 2 Fast mode */
+
+#define HRTIM_EECR1_EE3SRC_Pos        (12U)
+#define HRTIM_EECR1_EE3SRC_Msk        (0x3UL << HRTIM_EECR1_EE3SRC_Pos)        /*!< 0x00003000 */
+#define HRTIM_EECR1_EE3SRC            HRTIM_EECR1_EE3SRC_Msk                   /*!< External event 3 source */
+#define HRTIM_EECR1_EE3SRC_0          (0x1UL << HRTIM_EECR1_EE3SRC_Pos)         /*!< 0x00001000 */
+#define HRTIM_EECR1_EE3SRC_1          (0x2UL << HRTIM_EECR1_EE3SRC_Pos)         /*!< 0x00002000 */
+#define HRTIM_EECR1_EE3POL_Pos        (14U)
+#define HRTIM_EECR1_EE3POL_Msk        (0x1UL << HRTIM_EECR1_EE3POL_Pos)        /*!< 0x00004000 */
+#define HRTIM_EECR1_EE3POL            HRTIM_EECR1_EE3POL_Msk                   /*!< External event 3 Polarity */
+#define HRTIM_EECR1_EE3SNS_Pos        (15U)
+#define HRTIM_EECR1_EE3SNS_Msk        (0x3UL << HRTIM_EECR1_EE3SNS_Pos)        /*!< 0x00018000 */
+#define HRTIM_EECR1_EE3SNS            HRTIM_EECR1_EE3SNS_Msk                   /*!< External event 3 sensitivity */
+#define HRTIM_EECR1_EE3SNS_0          (0x1UL << HRTIM_EECR1_EE3SNS_Pos)         /*!< 0x00008000 */
+#define HRTIM_EECR1_EE3SNS_1          (0x2UL << HRTIM_EECR1_EE3SNS_Pos)         /*!< 0x00010000 */
+#define HRTIM_EECR1_EE3FAST_Pos       (17U)
+#define HRTIM_EECR1_EE3FAST_Msk       (0x1UL << HRTIM_EECR1_EE3FAST_Pos)       /*!< 0x00020000 */
+#define HRTIM_EECR1_EE3FAST           HRTIM_EECR1_EE3FAST_Msk                  /*!< External event 3 Fast mode */
+
+#define HRTIM_EECR1_EE4SRC_Pos        (18U)
+#define HRTIM_EECR1_EE4SRC_Msk        (0x3UL << HRTIM_EECR1_EE4SRC_Pos)        /*!< 0x000C0000 */
+#define HRTIM_EECR1_EE4SRC            HRTIM_EECR1_EE4SRC_Msk                   /*!< External event 4 source */
+#define HRTIM_EECR1_EE4SRC_0          (0x1UL << HRTIM_EECR1_EE4SRC_Pos)         /*!< 0x00040000 */
+#define HRTIM_EECR1_EE4SRC_1          (0x2UL << HRTIM_EECR1_EE4SRC_Pos)         /*!< 0x00080000 */
+#define HRTIM_EECR1_EE4POL_Pos        (20U)
+#define HRTIM_EECR1_EE4POL_Msk        (0x1UL << HRTIM_EECR1_EE4POL_Pos)        /*!< 0x00100000 */
+#define HRTIM_EECR1_EE4POL            HRTIM_EECR1_EE4POL_Msk                   /*!< External event 4 Polarity */
+#define HRTIM_EECR1_EE4SNS_Pos        (21U)
+#define HRTIM_EECR1_EE4SNS_Msk        (0x3UL << HRTIM_EECR1_EE4SNS_Pos)        /*!< 0x00600000 */
+#define HRTIM_EECR1_EE4SNS            HRTIM_EECR1_EE4SNS_Msk                   /*!< External event 4 sensitivity */
+#define HRTIM_EECR1_EE4SNS_0          (0x1UL << HRTIM_EECR1_EE4SNS_Pos)         /*!< 0x00200000 */
+#define HRTIM_EECR1_EE4SNS_1          (0x2UL << HRTIM_EECR1_EE4SNS_Pos)         /*!< 0x00400000 */
+#define HRTIM_EECR1_EE4FAST_Pos       (23U)
+#define HRTIM_EECR1_EE4FAST_Msk       (0x1UL << HRTIM_EECR1_EE4FAST_Pos)       /*!< 0x00800000 */
+#define HRTIM_EECR1_EE4FAST           HRTIM_EECR1_EE4FAST_Msk                  /*!< External event 4 Fast mode */
+
+#define HRTIM_EECR1_EE5SRC_Pos        (24U)
+#define HRTIM_EECR1_EE5SRC_Msk        (0x3UL << HRTIM_EECR1_EE5SRC_Pos)        /*!< 0x03000000 */
+#define HRTIM_EECR1_EE5SRC            HRTIM_EECR1_EE5SRC_Msk                   /*!< External event 5 source */
+#define HRTIM_EECR1_EE5SRC_0          (0x1UL << HRTIM_EECR1_EE5SRC_Pos)         /*!< 0x01000000 */
+#define HRTIM_EECR1_EE5SRC_1          (0x2UL << HRTIM_EECR1_EE5SRC_Pos)         /*!< 0x02000000 */
+#define HRTIM_EECR1_EE5POL_Pos        (26U)
+#define HRTIM_EECR1_EE5POL_Msk        (0x1UL << HRTIM_EECR1_EE5POL_Pos)        /*!< 0x04000000 */
+#define HRTIM_EECR1_EE5POL            HRTIM_EECR1_EE5POL_Msk                   /*!< External event 5 Polarity */
+#define HRTIM_EECR1_EE5SNS_Pos        (27U)
+#define HRTIM_EECR1_EE5SNS_Msk        (0x3UL << HRTIM_EECR1_EE5SNS_Pos)        /*!< 0x18000000 */
+#define HRTIM_EECR1_EE5SNS            HRTIM_EECR1_EE5SNS_Msk                   /*!< External event 5 sensitivity */
+#define HRTIM_EECR1_EE5SNS_0          (0x1UL << HRTIM_EECR1_EE5SNS_Pos)         /*!< 0x08000000 */
+#define HRTIM_EECR1_EE5SNS_1          (0x2UL << HRTIM_EECR1_EE5SNS_Pos)         /*!< 0x10000000 */
+#define HRTIM_EECR1_EE5FAST_Pos       (29U)
+#define HRTIM_EECR1_EE5FAST_Msk       (0x1UL << HRTIM_EECR1_EE5FAST_Pos)       /*!< 0x20000000 */
+#define HRTIM_EECR1_EE5FAST           HRTIM_EECR1_EE5FAST_Msk                  /*!< External event 5 Fast mode */
+
+/*******************  Bit definition for HRTIM_EECR2 register  ****************/
+#define HRTIM_EECR2_EE6SRC_Pos        (0U)
+#define HRTIM_EECR2_EE6SRC_Msk        (0x3UL << HRTIM_EECR2_EE6SRC_Pos)        /*!< 0x00000003 */
+#define HRTIM_EECR2_EE6SRC            HRTIM_EECR2_EE6SRC_Msk                   /*!< External event 6 source */
+#define HRTIM_EECR2_EE6SRC_0          (0x1UL << HRTIM_EECR2_EE6SRC_Pos)         /*!< 0x00000001 */
+#define HRTIM_EECR2_EE6SRC_1          (0x2UL << HRTIM_EECR2_EE6SRC_Pos)         /*!< 0x00000002 */
+#define HRTIM_EECR2_EE6POL_Pos        (2U)
+#define HRTIM_EECR2_EE6POL_Msk        (0x1UL << HRTIM_EECR2_EE6POL_Pos)        /*!< 0x00000004 */
+#define HRTIM_EECR2_EE6POL            HRTIM_EECR2_EE6POL_Msk                   /*!< External event 6 Polarity */
+#define HRTIM_EECR2_EE6SNS_Pos        (3U)
+#define HRTIM_EECR2_EE6SNS_Msk        (0x3UL << HRTIM_EECR2_EE6SNS_Pos)        /*!< 0x00000018 */
+#define HRTIM_EECR2_EE6SNS            HRTIM_EECR2_EE6SNS_Msk                   /*!< External event 6 sensitivity */
+#define HRTIM_EECR2_EE6SNS_0          (0x1UL << HRTIM_EECR2_EE6SNS_Pos)         /*!< 0x00000008 */
+#define HRTIM_EECR2_EE6SNS_1          (0x2UL << HRTIM_EECR2_EE6SNS_Pos)         /*!< 0x00000010 */
+
+#define HRTIM_EECR2_EE7SRC_Pos        (6U)
+#define HRTIM_EECR2_EE7SRC_Msk        (0x3UL << HRTIM_EECR2_EE7SRC_Pos)        /*!< 0x000000C0 */
+#define HRTIM_EECR2_EE7SRC            HRTIM_EECR2_EE7SRC_Msk                   /*!< External event 7 source */
+#define HRTIM_EECR2_EE7SRC_0          (0x1UL << HRTIM_EECR2_EE7SRC_Pos)         /*!< 0x00000040 */
+#define HRTIM_EECR2_EE7SRC_1          (0x2UL << HRTIM_EECR2_EE7SRC_Pos)         /*!< 0x00000080 */
+#define HRTIM_EECR2_EE7POL_Pos        (8U)
+#define HRTIM_EECR2_EE7POL_Msk        (0x1UL << HRTIM_EECR2_EE7POL_Pos)        /*!< 0x00000100 */
+#define HRTIM_EECR2_EE7POL            HRTIM_EECR2_EE7POL_Msk                   /*!< External event 7 Polarity */
+#define HRTIM_EECR2_EE7SNS_Pos        (9U)
+#define HRTIM_EECR2_EE7SNS_Msk        (0x3UL << HRTIM_EECR2_EE7SNS_Pos)        /*!< 0x00000600 */
+#define HRTIM_EECR2_EE7SNS            HRTIM_EECR2_EE7SNS_Msk                   /*!< External event 7 sensitivity */
+#define HRTIM_EECR2_EE7SNS_0          (0x1UL << HRTIM_EECR2_EE7SNS_Pos)         /*!< 0x00000200 */
+#define HRTIM_EECR2_EE7SNS_1          (0x2UL << HRTIM_EECR2_EE7SNS_Pos)         /*!< 0x00000400 */
+
+#define HRTIM_EECR2_EE8SRC_Pos        (12U)
+#define HRTIM_EECR2_EE8SRC_Msk        (0x3UL << HRTIM_EECR2_EE8SRC_Pos)        /*!< 0x00003000 */
+#define HRTIM_EECR2_EE8SRC            HRTIM_EECR2_EE8SRC_Msk                   /*!< External event 8 source */
+#define HRTIM_EECR2_EE8SRC_0          (0x1UL << HRTIM_EECR2_EE8SRC_Pos)         /*!< 0x00001000 */
+#define HRTIM_EECR2_EE8SRC_1          (0x2UL << HRTIM_EECR2_EE8SRC_Pos)         /*!< 0x00002000 */
+#define HRTIM_EECR2_EE8POL_Pos        (14U)
+#define HRTIM_EECR2_EE8POL_Msk        (0x1UL << HRTIM_EECR2_EE8POL_Pos)        /*!< 0x00004000 */
+#define HRTIM_EECR2_EE8POL            HRTIM_EECR2_EE8POL_Msk                   /*!< External event 8 Polarity */
+#define HRTIM_EECR2_EE8SNS_Pos        (15U)
+#define HRTIM_EECR2_EE8SNS_Msk        (0x3UL << HRTIM_EECR2_EE8SNS_Pos)        /*!< 0x00018000 */
+#define HRTIM_EECR2_EE8SNS            HRTIM_EECR2_EE8SNS_Msk                   /*!< External event 8 sensitivity */
+#define HRTIM_EECR2_EE8SNS_0          (0x1UL << HRTIM_EECR2_EE8SNS_Pos)         /*!< 0x00008000 */
+#define HRTIM_EECR2_EE8SNS_1          (0x2UL << HRTIM_EECR2_EE8SNS_Pos)         /*!< 0x00010000 */
+
+#define HRTIM_EECR2_EE9SRC_Pos        (18U)
+#define HRTIM_EECR2_EE9SRC_Msk        (0x3UL << HRTIM_EECR2_EE9SRC_Pos)        /*!< 0x000C0000 */
+#define HRTIM_EECR2_EE9SRC            HRTIM_EECR2_EE9SRC_Msk                   /*!< External event 9 source */
+#define HRTIM_EECR2_EE9SRC_0          (0x1UL << HRTIM_EECR2_EE9SRC_Pos)         /*!< 0x00040000 */
+#define HRTIM_EECR2_EE9SRC_1          (0x2UL << HRTIM_EECR2_EE9SRC_Pos)         /*!< 0x00080000 */
+#define HRTIM_EECR2_EE9POL_Pos        (20U)
+#define HRTIM_EECR2_EE9POL_Msk        (0x1UL << HRTIM_EECR2_EE9POL_Pos)        /*!< 0x00100000 */
+#define HRTIM_EECR2_EE9POL            HRTIM_EECR2_EE9POL_Msk                   /*!< External event 9 Polarity */
+#define HRTIM_EECR2_EE9SNS_Pos        (21U)
+#define HRTIM_EECR2_EE9SNS_Msk        (0x3UL << HRTIM_EECR2_EE9SNS_Pos)        /*!< 0x00600000 */
+#define HRTIM_EECR2_EE9SNS            HRTIM_EECR2_EE9SNS_Msk                   /*!< External event 9 sensitivity */
+#define HRTIM_EECR2_EE9SNS_0          (0x1UL << HRTIM_EECR2_EE9SNS_Pos)         /*!< 0x00200000 */
+#define HRTIM_EECR2_EE9SNS_1          (0x2UL << HRTIM_EECR2_EE9SNS_Pos)         /*!< 0x00400000 */
+
+#define HRTIM_EECR2_EE10SRC_Pos       (24U)
+#define HRTIM_EECR2_EE10SRC_Msk       (0x3UL << HRTIM_EECR2_EE10SRC_Pos)       /*!< 0x03000000 */
+#define HRTIM_EECR2_EE10SRC           HRTIM_EECR2_EE10SRC_Msk                  /*!< External event 10 source */
+#define HRTIM_EECR2_EE10SRC_0         (0x1UL << HRTIM_EECR2_EE10SRC_Pos)        /*!< 0x01000000 */
+#define HRTIM_EECR2_EE10SRC_1         (0x2UL << HRTIM_EECR2_EE10SRC_Pos)        /*!< 0x02000000 */
+#define HRTIM_EECR2_EE10POL_Pos       (26U)
+#define HRTIM_EECR2_EE10POL_Msk       (0x1UL << HRTIM_EECR2_EE10POL_Pos)       /*!< 0x04000000 */
+#define HRTIM_EECR2_EE10POL           HRTIM_EECR2_EE10POL_Msk                  /*!< External event 10 Polarity */
+#define HRTIM_EECR2_EE10SNS_Pos       (27U)
+#define HRTIM_EECR2_EE10SNS_Msk       (0x3UL << HRTIM_EECR2_EE10SNS_Pos)       /*!< 0x18000000 */
+#define HRTIM_EECR2_EE10SNS           HRTIM_EECR2_EE10SNS_Msk                  /*!< External event 10 sensitivity */
+#define HRTIM_EECR2_EE10SNS_0         (0x1UL << HRTIM_EECR2_EE10SNS_Pos)        /*!< 0x08000000 */
+#define HRTIM_EECR2_EE10SNS_1         (0x2UL << HRTIM_EECR2_EE10SNS_Pos)        /*!< 0x10000000 */
+
+/*******************  Bit definition for HRTIM_EECR3 register  ****************/
+#define HRTIM_EECR3_EE6F_Pos          (0U)
+#define HRTIM_EECR3_EE6F_Msk          (0xFUL << HRTIM_EECR3_EE6F_Pos)          /*!< 0x0000000F */
+#define HRTIM_EECR3_EE6F              HRTIM_EECR3_EE6F_Msk                     /*!< External event 6 filter */
+#define HRTIM_EECR3_EE6F_0            (0x1UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000001 */
+#define HRTIM_EECR3_EE6F_1            (0x2UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000002 */
+#define HRTIM_EECR3_EE6F_2            (0x4UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000004 */
+#define HRTIM_EECR3_EE6F_3            (0x8UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000008 */
+#define HRTIM_EECR3_EE7F_Pos          (6U)
+#define HRTIM_EECR3_EE7F_Msk          (0xFUL << HRTIM_EECR3_EE7F_Pos)          /*!< 0x000003C0 */
+#define HRTIM_EECR3_EE7F              HRTIM_EECR3_EE7F_Msk                     /*!< External event 7 filter */
+#define HRTIM_EECR3_EE7F_0            (0x1UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000040 */
+#define HRTIM_EECR3_EE7F_1            (0x2UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000080 */
+#define HRTIM_EECR3_EE7F_2            (0x4UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000100 */
+#define HRTIM_EECR3_EE7F_3            (0x8UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000200 */
+#define HRTIM_EECR3_EE8F_Pos          (12U)
+#define HRTIM_EECR3_EE8F_Msk          (0xFUL << HRTIM_EECR3_EE8F_Pos)          /*!< 0x0000F000 */
+#define HRTIM_EECR3_EE8F              HRTIM_EECR3_EE8F_Msk                     /*!< External event 8 filter */
+#define HRTIM_EECR3_EE8F_0            (0x1UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00001000 */
+#define HRTIM_EECR3_EE8F_1            (0x2UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00002000 */
+#define HRTIM_EECR3_EE8F_2            (0x4UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00004000 */
+#define HRTIM_EECR3_EE8F_3            (0x8UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00008000 */
+#define HRTIM_EECR3_EE9F_Pos          (18U)
+#define HRTIM_EECR3_EE9F_Msk          (0xFUL << HRTIM_EECR3_EE9F_Pos)          /*!< 0x003C0000 */
+#define HRTIM_EECR3_EE9F              HRTIM_EECR3_EE9F_Msk                     /*!< External event 9 filter */
+#define HRTIM_EECR3_EE9F_0            (0x1UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00040000 */
+#define HRTIM_EECR3_EE9F_1            (0x2UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00080000 */
+#define HRTIM_EECR3_EE9F_2            (0x4UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00100000 */
+#define HRTIM_EECR3_EE9F_3            (0x8UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00200000 */
+#define HRTIM_EECR3_EE10F_Pos         (24U)
+#define HRTIM_EECR3_EE10F_Msk         (0xFUL << HRTIM_EECR3_EE10F_Pos)         /*!< 0x0F000000 */
+#define HRTIM_EECR3_EE10F             HRTIM_EECR3_EE10F_Msk                    /*!< External event 10 filter */
+#define HRTIM_EECR3_EE10F_0           (0x1UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x01000000 */
+#define HRTIM_EECR3_EE10F_1           (0x2UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x02000000 */
+#define HRTIM_EECR3_EE10F_2           (0x4UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x04000000 */
+#define HRTIM_EECR3_EE10F_3           (0x8UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x08000000 */
+#define HRTIM_EECR3_EEVSD_Pos         (30U)
+#define HRTIM_EECR3_EEVSD_Msk         (0x3UL << HRTIM_EECR3_EEVSD_Pos)         /*!< 0xC0000000 */
+#define HRTIM_EECR3_EEVSD             HRTIM_EECR3_EEVSD_Msk                    /*!< External event sampling clock division */
+#define HRTIM_EECR3_EEVSD_0           (0x1UL << HRTIM_EECR3_EEVSD_Pos)          /*!< 0x40000000 */
+#define HRTIM_EECR3_EEVSD_1           (0x2UL << HRTIM_EECR3_EEVSD_Pos)          /*!< 0x80000000 */
+
+/*******************  Bit definition for HRTIM_ADC1R register  ****************/
+#define HRTIM_ADC1R_AD1MC1_Pos        (0U)
+#define HRTIM_ADC1R_AD1MC1_Msk        (0x1UL << HRTIM_ADC1R_AD1MC1_Pos)        /*!< 0x00000001 */
+#define HRTIM_ADC1R_AD1MC1            HRTIM_ADC1R_AD1MC1_Msk                   /*!< ADC Trigger 1 on master compare 1 */
+#define HRTIM_ADC1R_AD1MC2_Pos        (1U)
+#define HRTIM_ADC1R_AD1MC2_Msk        (0x1UL << HRTIM_ADC1R_AD1MC2_Pos)        /*!< 0x00000002 */
+#define HRTIM_ADC1R_AD1MC2            HRTIM_ADC1R_AD1MC2_Msk                   /*!< ADC Trigger 1 on master compare 2 */
+#define HRTIM_ADC1R_AD1MC3_Pos        (2U)
+#define HRTIM_ADC1R_AD1MC3_Msk        (0x1UL << HRTIM_ADC1R_AD1MC3_Pos)        /*!< 0x00000004 */
+#define HRTIM_ADC1R_AD1MC3            HRTIM_ADC1R_AD1MC3_Msk                   /*!< ADC Trigger 1 on master compare 3 */
+#define HRTIM_ADC1R_AD1MC4_Pos        (3U)
+#define HRTIM_ADC1R_AD1MC4_Msk        (0x1UL << HRTIM_ADC1R_AD1MC4_Pos)        /*!< 0x00000008 */
+#define HRTIM_ADC1R_AD1MC4            HRTIM_ADC1R_AD1MC4_Msk                   /*!< ADC Trigger 1 on master compare 4 */
+#define HRTIM_ADC1R_AD1MPER_Pos       (4U)
+#define HRTIM_ADC1R_AD1MPER_Msk       (0x1UL << HRTIM_ADC1R_AD1MPER_Pos)       /*!< 0x00000010 */
+#define HRTIM_ADC1R_AD1MPER           HRTIM_ADC1R_AD1MPER_Msk                  /*!< ADC Trigger 1 on master period */
+#define HRTIM_ADC1R_AD1EEV1_Pos       (5U)
+#define HRTIM_ADC1R_AD1EEV1_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV1_Pos)       /*!< 0x00000020 */
+#define HRTIM_ADC1R_AD1EEV1           HRTIM_ADC1R_AD1EEV1_Msk                  /*!< ADC Trigger 1 on external event 1 */
+#define HRTIM_ADC1R_AD1EEV2_Pos       (6U)
+#define HRTIM_ADC1R_AD1EEV2_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV2_Pos)       /*!< 0x00000040 */
+#define HRTIM_ADC1R_AD1EEV2           HRTIM_ADC1R_AD1EEV2_Msk                  /*!< ADC Trigger 1 on external event 2 */
+#define HRTIM_ADC1R_AD1EEV3_Pos       (7U)
+#define HRTIM_ADC1R_AD1EEV3_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV3_Pos)       /*!< 0x00000080 */
+#define HRTIM_ADC1R_AD1EEV3           HRTIM_ADC1R_AD1EEV3_Msk                  /*!< ADC Trigger 1 on external event 3 */
+#define HRTIM_ADC1R_AD1EEV4_Pos       (8U)
+#define HRTIM_ADC1R_AD1EEV4_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV4_Pos)       /*!< 0x00000100 */
+#define HRTIM_ADC1R_AD1EEV4           HRTIM_ADC1R_AD1EEV4_Msk                  /*!< ADC Trigger 1 on external event 4 */
+#define HRTIM_ADC1R_AD1EEV5_Pos       (9U)
+#define HRTIM_ADC1R_AD1EEV5_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV5_Pos)       /*!< 0x00000200 */
+#define HRTIM_ADC1R_AD1EEV5           HRTIM_ADC1R_AD1EEV5_Msk                  /*!< ADC Trigger 1 on external event 5 */
+#define HRTIM_ADC1R_AD1TAC2_Pos       (10U)
+#define HRTIM_ADC1R_AD1TAC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC2_Pos)       /*!< 0x00000400 */
+#define HRTIM_ADC1R_AD1TAC2           HRTIM_ADC1R_AD1TAC2_Msk                  /*!< ADC Trigger 1 on Timer A compare 2 */
+#define HRTIM_ADC1R_AD1TAC3_Pos       (11U)
+#define HRTIM_ADC1R_AD1TAC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC3_Pos)       /*!< 0x00000800 */
+#define HRTIM_ADC1R_AD1TAC3           HRTIM_ADC1R_AD1TAC3_Msk                  /*!< ADC Trigger 1 on Timer A compare 3 */
+#define HRTIM_ADC1R_AD1TAC4_Pos       (12U)
+#define HRTIM_ADC1R_AD1TAC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC4_Pos)       /*!< 0x00001000 */
+#define HRTIM_ADC1R_AD1TAC4           HRTIM_ADC1R_AD1TAC4_Msk                  /*!< ADC Trigger 1 on Timer A compare 4 */
+#define HRTIM_ADC1R_AD1TAPER_Pos      (13U)
+#define HRTIM_ADC1R_AD1TAPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TAPER_Pos)      /*!< 0x00002000 */
+#define HRTIM_ADC1R_AD1TAPER          HRTIM_ADC1R_AD1TAPER_Msk                 /*!< ADC Trigger 1 on Timer A period */
+#define HRTIM_ADC1R_AD1TARST_Pos      (14U)
+#define HRTIM_ADC1R_AD1TARST_Msk      (0x1UL << HRTIM_ADC1R_AD1TARST_Pos)      /*!< 0x00004000 */
+#define HRTIM_ADC1R_AD1TARST          HRTIM_ADC1R_AD1TARST_Msk                 /*!< ADC Trigger 1 on Timer A reset */
+#define HRTIM_ADC1R_AD1TBC2_Pos       (15U)
+#define HRTIM_ADC1R_AD1TBC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC2_Pos)       /*!< 0x00008000 */
+#define HRTIM_ADC1R_AD1TBC2           HRTIM_ADC1R_AD1TBC2_Msk                  /*!< ADC Trigger 1 on Timer B compare 2 */
+#define HRTIM_ADC1R_AD1TBC3_Pos       (16U)
+#define HRTIM_ADC1R_AD1TBC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC3_Pos)       /*!< 0x00010000 */
+#define HRTIM_ADC1R_AD1TBC3           HRTIM_ADC1R_AD1TBC3_Msk                  /*!< ADC Trigger 1 on Timer B compare 3 */
+#define HRTIM_ADC1R_AD1TBC4_Pos       (17U)
+#define HRTIM_ADC1R_AD1TBC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC4_Pos)       /*!< 0x00020000 */
+#define HRTIM_ADC1R_AD1TBC4           HRTIM_ADC1R_AD1TBC4_Msk                  /*!< ADC Trigger 1 on Timer B compare 4 */
+#define HRTIM_ADC1R_AD1TBPER_Pos      (18U)
+#define HRTIM_ADC1R_AD1TBPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TBPER_Pos)      /*!< 0x00040000 */
+#define HRTIM_ADC1R_AD1TBPER          HRTIM_ADC1R_AD1TBPER_Msk                 /*!< ADC Trigger 1 on Timer B period */
+#define HRTIM_ADC1R_AD1TBRST_Pos      (19U)
+#define HRTIM_ADC1R_AD1TBRST_Msk      (0x1UL << HRTIM_ADC1R_AD1TBRST_Pos)      /*!< 0x00080000 */
+#define HRTIM_ADC1R_AD1TBRST          HRTIM_ADC1R_AD1TBRST_Msk                 /*!< ADC Trigger 1 on Timer B reset */
+#define HRTIM_ADC1R_AD1TCC2_Pos       (20U)
+#define HRTIM_ADC1R_AD1TCC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC2_Pos)       /*!< 0x00100000 */
+#define HRTIM_ADC1R_AD1TCC2           HRTIM_ADC1R_AD1TCC2_Msk                  /*!< ADC Trigger 1 on Timer C compare 2 */
+#define HRTIM_ADC1R_AD1TCC3_Pos       (21U)
+#define HRTIM_ADC1R_AD1TCC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC3_Pos)       /*!< 0x00200000 */
+#define HRTIM_ADC1R_AD1TCC3           HRTIM_ADC1R_AD1TCC3_Msk                  /*!< ADC Trigger 1 on Timer C compare 3 */
+#define HRTIM_ADC1R_AD1TCC4_Pos       (22U)
+#define HRTIM_ADC1R_AD1TCC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC4_Pos)       /*!< 0x00400000 */
+#define HRTIM_ADC1R_AD1TCC4           HRTIM_ADC1R_AD1TCC4_Msk                  /*!< ADC Trigger 1 on Timer C compare 4 */
+#define HRTIM_ADC1R_AD1TCPER_Pos      (23U)
+#define HRTIM_ADC1R_AD1TCPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TCPER_Pos)      /*!< 0x00800000 */
+#define HRTIM_ADC1R_AD1TCPER          HRTIM_ADC1R_AD1TCPER_Msk                 /*!< ADC Trigger 1 on Timer C period */
+#define HRTIM_ADC1R_AD1TDC2_Pos       (24U)
+#define HRTIM_ADC1R_AD1TDC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC2_Pos)       /*!< 0x01000000 */
+#define HRTIM_ADC1R_AD1TDC2           HRTIM_ADC1R_AD1TDC2_Msk                  /*!< ADC Trigger 1 on Timer D compare 2 */
+#define HRTIM_ADC1R_AD1TDC3_Pos       (25U)
+#define HRTIM_ADC1R_AD1TDC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC3_Pos)       /*!< 0x02000000 */
+#define HRTIM_ADC1R_AD1TDC3           HRTIM_ADC1R_AD1TDC3_Msk                  /*!< ADC Trigger 1 on Timer D compare 3 */
+#define HRTIM_ADC1R_AD1TDC4_Pos       (26U)
+#define HRTIM_ADC1R_AD1TDC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC4_Pos)       /*!< 0x04000000 */
+#define HRTIM_ADC1R_AD1TDC4           HRTIM_ADC1R_AD1TDC4_Msk                  /*!< ADC Trigger 1 on Timer D compare 4 */
+#define HRTIM_ADC1R_AD1TDPER_Pos      (27U)
+#define HRTIM_ADC1R_AD1TDPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TDPER_Pos)      /*!< 0x08000000 */
+#define HRTIM_ADC1R_AD1TDPER          HRTIM_ADC1R_AD1TDPER_Msk                 /*!< ADC Trigger 1 on Timer D period */
+#define HRTIM_ADC1R_AD1TEC2_Pos       (28U)
+#define HRTIM_ADC1R_AD1TEC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC2_Pos)       /*!< 0x10000000 */
+#define HRTIM_ADC1R_AD1TEC2           HRTIM_ADC1R_AD1TEC2_Msk                  /*!< ADC Trigger 1 on Timer E compare 2 */
+#define HRTIM_ADC1R_AD1TEC3_Pos       (29U)
+#define HRTIM_ADC1R_AD1TEC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC3_Pos)       /*!< 0x20000000 */
+#define HRTIM_ADC1R_AD1TEC3           HRTIM_ADC1R_AD1TEC3_Msk                  /*!< ADC Trigger 1 on Timer E compare 3 */
+#define HRTIM_ADC1R_AD1TEC4_Pos       (30U)
+#define HRTIM_ADC1R_AD1TEC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC4_Pos)       /*!< 0x40000000 */
+#define HRTIM_ADC1R_AD1TEC4           HRTIM_ADC1R_AD1TEC4_Msk                  /*!< ADC Trigger 1 on Timer E compare 4 */
+#define HRTIM_ADC1R_AD1TEPER_Pos      (31U)
+#define HRTIM_ADC1R_AD1TEPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TEPER_Pos)      /*!< 0x80000000 */
+#define HRTIM_ADC1R_AD1TEPER          HRTIM_ADC1R_AD1TEPER_Msk                 /*!< ADC Trigger 1 on Timer E period */
+
+/*******************  Bit definition for HRTIM_ADC2R register  ****************/
+#define HRTIM_ADC2R_AD2MC1_Pos        (0U)
+#define HRTIM_ADC2R_AD2MC1_Msk        (0x1UL << HRTIM_ADC2R_AD2MC1_Pos)        /*!< 0x00000001 */
+#define HRTIM_ADC2R_AD2MC1            HRTIM_ADC2R_AD2MC1_Msk                   /*!< ADC Trigger 2 on master compare 1 */
+#define HRTIM_ADC2R_AD2MC2_Pos        (1U)
+#define HRTIM_ADC2R_AD2MC2_Msk        (0x1UL << HRTIM_ADC2R_AD2MC2_Pos)        /*!< 0x00000002 */
+#define HRTIM_ADC2R_AD2MC2            HRTIM_ADC2R_AD2MC2_Msk                   /*!< ADC Trigger 2 on master compare 2 */
+#define HRTIM_ADC2R_AD2MC3_Pos        (2U)
+#define HRTIM_ADC2R_AD2MC3_Msk        (0x1UL << HRTIM_ADC2R_AD2MC3_Pos)        /*!< 0x00000004 */
+#define HRTIM_ADC2R_AD2MC3            HRTIM_ADC2R_AD2MC3_Msk                   /*!< ADC Trigger 2 on master compare 3 */
+#define HRTIM_ADC2R_AD2MC4_Pos        (3U)
+#define HRTIM_ADC2R_AD2MC4_Msk        (0x1UL << HRTIM_ADC2R_AD2MC4_Pos)        /*!< 0x00000008 */
+#define HRTIM_ADC2R_AD2MC4            HRTIM_ADC2R_AD2MC4_Msk                   /*!< ADC Trigger 2 on master compare 4 */
+#define HRTIM_ADC2R_AD2MPER_Pos       (4U)
+#define HRTIM_ADC2R_AD2MPER_Msk       (0x1UL << HRTIM_ADC2R_AD2MPER_Pos)       /*!< 0x00000010 */
+#define HRTIM_ADC2R_AD2MPER           HRTIM_ADC2R_AD2MPER_Msk                  /*!< ADC Trigger 2 on master period */
+#define HRTIM_ADC2R_AD2EEV6_Pos       (5U)
+#define HRTIM_ADC2R_AD2EEV6_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV6_Pos)       /*!< 0x00000020 */
+#define HRTIM_ADC2R_AD2EEV6           HRTIM_ADC2R_AD2EEV6_Msk                  /*!< ADC Trigger 2 on external event 6 */
+#define HRTIM_ADC2R_AD2EEV7_Pos       (6U)
+#define HRTIM_ADC2R_AD2EEV7_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV7_Pos)       /*!< 0x00000040 */
+#define HRTIM_ADC2R_AD2EEV7           HRTIM_ADC2R_AD2EEV7_Msk                  /*!< ADC Trigger 2 on external event 7 */
+#define HRTIM_ADC2R_AD2EEV8_Pos       (7U)
+#define HRTIM_ADC2R_AD2EEV8_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV8_Pos)       /*!< 0x00000080 */
+#define HRTIM_ADC2R_AD2EEV8           HRTIM_ADC2R_AD2EEV8_Msk                  /*!< ADC Trigger 2 on external event 8 */
+#define HRTIM_ADC2R_AD2EEV9_Pos       (8U)
+#define HRTIM_ADC2R_AD2EEV9_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV9_Pos)       /*!< 0x00000100 */
+#define HRTIM_ADC2R_AD2EEV9           HRTIM_ADC2R_AD2EEV9_Msk                  /*!< ADC Trigger 2 on external event 9 */
+#define HRTIM_ADC2R_AD2EEV10_Pos      (9U)
+#define HRTIM_ADC2R_AD2EEV10_Msk      (0x1UL << HRTIM_ADC2R_AD2EEV10_Pos)      /*!< 0x00000200 */
+#define HRTIM_ADC2R_AD2EEV10          HRTIM_ADC2R_AD2EEV10_Msk                 /*!< ADC Trigger 2 on external event 10 */
+#define HRTIM_ADC2R_AD2TAC2_Pos       (10U)
+#define HRTIM_ADC2R_AD2TAC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC2_Pos)       /*!< 0x00000400 */
+#define HRTIM_ADC2R_AD2TAC2           HRTIM_ADC2R_AD2TAC2_Msk                  /*!< ADC Trigger 2 on Timer A compare 2 */
+#define HRTIM_ADC2R_AD2TAC3_Pos       (11U)
+#define HRTIM_ADC2R_AD2TAC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC3_Pos)       /*!< 0x00000800 */
+#define HRTIM_ADC2R_AD2TAC3           HRTIM_ADC2R_AD2TAC3_Msk                  /*!< ADC Trigger 2 on Timer A compare 3 */
+#define HRTIM_ADC2R_AD2TAC4_Pos       (12U)
+#define HRTIM_ADC2R_AD2TAC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC4_Pos)       /*!< 0x00001000 */
+#define HRTIM_ADC2R_AD2TAC4           HRTIM_ADC2R_AD2TAC4_Msk                  /*!< ADC Trigger 2 on Timer A compare 4*/
+#define HRTIM_ADC2R_AD2TAPER_Pos      (13U)
+#define HRTIM_ADC2R_AD2TAPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TAPER_Pos)      /*!< 0x00002000 */
+#define HRTIM_ADC2R_AD2TAPER          HRTIM_ADC2R_AD2TAPER_Msk                 /*!< ADC Trigger 2 on Timer A period */
+#define HRTIM_ADC2R_AD2TBC2_Pos       (14U)
+#define HRTIM_ADC2R_AD2TBC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC2_Pos)       /*!< 0x00004000 */
+#define HRTIM_ADC2R_AD2TBC2           HRTIM_ADC2R_AD2TBC2_Msk                  /*!< ADC Trigger 2 on Timer B compare 2 */
+#define HRTIM_ADC2R_AD2TBC3_Pos       (15U)
+#define HRTIM_ADC2R_AD2TBC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC3_Pos)       /*!< 0x00008000 */
+#define HRTIM_ADC2R_AD2TBC3           HRTIM_ADC2R_AD2TBC3_Msk                  /*!< ADC Trigger 2 on Timer B compare 3 */
+#define HRTIM_ADC2R_AD2TBC4_Pos       (16U)
+#define HRTIM_ADC2R_AD2TBC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC4_Pos)       /*!< 0x00010000 */
+#define HRTIM_ADC2R_AD2TBC4           HRTIM_ADC2R_AD2TBC4_Msk                  /*!< ADC Trigger 2 on Timer B compare 4 */
+#define HRTIM_ADC2R_AD2TBPER_Pos      (17U)
+#define HRTIM_ADC2R_AD2TBPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TBPER_Pos)      /*!< 0x00020000 */
+#define HRTIM_ADC2R_AD2TBPER          HRTIM_ADC2R_AD2TBPER_Msk                 /*!< ADC Trigger 2 on Timer B period */
+#define HRTIM_ADC2R_AD2TCC2_Pos       (18U)
+#define HRTIM_ADC2R_AD2TCC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC2_Pos)       /*!< 0x00040000 */
+#define HRTIM_ADC2R_AD2TCC2           HRTIM_ADC2R_AD2TCC2_Msk                  /*!< ADC Trigger 2 on Timer C compare 2 */
+#define HRTIM_ADC2R_AD2TCC3_Pos       (19U)
+#define HRTIM_ADC2R_AD2TCC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC3_Pos)       /*!< 0x00080000 */
+#define HRTIM_ADC2R_AD2TCC3           HRTIM_ADC2R_AD2TCC3_Msk                  /*!< ADC Trigger 2 on Timer C compare 3 */
+#define HRTIM_ADC2R_AD2TCC4_Pos       (20U)
+#define HRTIM_ADC2R_AD2TCC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC4_Pos)       /*!< 0x00100000 */
+#define HRTIM_ADC2R_AD2TCC4           HRTIM_ADC2R_AD2TCC4_Msk                  /*!< ADC Trigger 2 on Timer C compare 4 */
+#define HRTIM_ADC2R_AD2TCPER_Pos      (21U)
+#define HRTIM_ADC2R_AD2TCPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TCPER_Pos)      /*!< 0x00200000 */
+#define HRTIM_ADC2R_AD2TCPER          HRTIM_ADC2R_AD2TCPER_Msk                 /*!< ADC Trigger 2 on Timer C period */
+#define HRTIM_ADC2R_AD2TCRST_Pos      (22U)
+#define HRTIM_ADC2R_AD2TCRST_Msk      (0x1UL << HRTIM_ADC2R_AD2TCRST_Pos)      /*!< 0x00400000 */
+#define HRTIM_ADC2R_AD2TCRST          HRTIM_ADC2R_AD2TCRST_Msk                 /*!< ADC Trigger 2 on Timer C reset */
+#define HRTIM_ADC2R_AD2TDC2_Pos       (23U)
+#define HRTIM_ADC2R_AD2TDC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC2_Pos)       /*!< 0x00800000 */
+#define HRTIM_ADC2R_AD2TDC2           HRTIM_ADC2R_AD2TDC2_Msk                  /*!< ADC Trigger 2 on Timer D compare 2 */
+#define HRTIM_ADC2R_AD2TDC3_Pos       (24U)
+#define HRTIM_ADC2R_AD2TDC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC3_Pos)       /*!< 0x01000000 */
+#define HRTIM_ADC2R_AD2TDC3           HRTIM_ADC2R_AD2TDC3_Msk                  /*!< ADC Trigger 2 on Timer D compare 3 */
+#define HRTIM_ADC2R_AD2TDC4_Pos       (25U)
+#define HRTIM_ADC2R_AD2TDC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC4_Pos)       /*!< 0x02000000 */
+#define HRTIM_ADC2R_AD2TDC4           HRTIM_ADC2R_AD2TDC4_Msk                  /*!< ADC Trigger 2 on Timer D compare 4*/
+#define HRTIM_ADC2R_AD2TDPER_Pos      (26U)
+#define HRTIM_ADC2R_AD2TDPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TDPER_Pos)      /*!< 0x04000000 */
+#define HRTIM_ADC2R_AD2TDPER          HRTIM_ADC2R_AD2TDPER_Msk                 /*!< ADC Trigger 2 on Timer D period */
+#define HRTIM_ADC2R_AD2TDRST_Pos      (27U)
+#define HRTIM_ADC2R_AD2TDRST_Msk      (0x1UL << HRTIM_ADC2R_AD2TDRST_Pos)      /*!< 0x08000000 */
+#define HRTIM_ADC2R_AD2TDRST          HRTIM_ADC2R_AD2TDRST_Msk                 /*!< ADC Trigger 2 on Timer D reset */
+#define HRTIM_ADC2R_AD2TEC2_Pos       (28U)
+#define HRTIM_ADC2R_AD2TEC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC2_Pos)       /*!< 0x10000000 */
+#define HRTIM_ADC2R_AD2TEC2           HRTIM_ADC2R_AD2TEC2_Msk                  /*!< ADC Trigger 2 on Timer E compare 2 */
+#define HRTIM_ADC2R_AD2TEC3_Pos       (29U)
+#define HRTIM_ADC2R_AD2TEC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC3_Pos)       /*!< 0x20000000 */
+#define HRTIM_ADC2R_AD2TEC3           HRTIM_ADC2R_AD2TEC3_Msk                  /*!< ADC Trigger 2 on Timer E compare 3 */
+#define HRTIM_ADC2R_AD2TEC4_Pos       (30U)
+#define HRTIM_ADC2R_AD2TEC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC4_Pos)       /*!< 0x40000000 */
+#define HRTIM_ADC2R_AD2TEC4           HRTIM_ADC2R_AD2TEC4_Msk                  /*!< ADC Trigger 2 on Timer E compare 4 */
+#define HRTIM_ADC2R_AD2TERST_Pos      (31U)
+#define HRTIM_ADC2R_AD2TERST_Msk      (0x1UL << HRTIM_ADC2R_AD2TERST_Pos)      /*!< 0x80000000 */
+#define HRTIM_ADC2R_AD2TERST          HRTIM_ADC2R_AD2TERST_Msk                 /*!< ADC Trigger 2 on Timer E reset */
+
+/*******************  Bit definition for HRTIM_ADC3R register  ****************/
+#define HRTIM_ADC3R_AD3MC1_Pos        (0U)
+#define HRTIM_ADC3R_AD3MC1_Msk        (0x1UL << HRTIM_ADC3R_AD3MC1_Pos)        /*!< 0x00000001 */
+#define HRTIM_ADC3R_AD3MC1            HRTIM_ADC3R_AD3MC1_Msk                   /*!< ADC Trigger 3 on master compare 1 */
+#define HRTIM_ADC3R_AD3MC2_Pos        (1U)
+#define HRTIM_ADC3R_AD3MC2_Msk        (0x1UL << HRTIM_ADC3R_AD3MC2_Pos)        /*!< 0x00000002 */
+#define HRTIM_ADC3R_AD3MC2            HRTIM_ADC3R_AD3MC2_Msk                   /*!< ADC Trigger 3 on master compare 2 */
+#define HRTIM_ADC3R_AD3MC3_Pos        (2U)
+#define HRTIM_ADC3R_AD3MC3_Msk        (0x1UL << HRTIM_ADC3R_AD3MC3_Pos)        /*!< 0x00000004 */
+#define HRTIM_ADC3R_AD3MC3            HRTIM_ADC3R_AD3MC3_Msk                   /*!< ADC Trigger 3 on master compare 3 */
+#define HRTIM_ADC3R_AD3MC4_Pos        (3U)
+#define HRTIM_ADC3R_AD3MC4_Msk        (0x1UL << HRTIM_ADC3R_AD3MC4_Pos)        /*!< 0x00000008 */
+#define HRTIM_ADC3R_AD3MC4            HRTIM_ADC3R_AD3MC4_Msk                   /*!< ADC Trigger 3 on master compare 4 */
+#define HRTIM_ADC3R_AD3MPER_Pos       (4U)
+#define HRTIM_ADC3R_AD3MPER_Msk       (0x1UL << HRTIM_ADC3R_AD3MPER_Pos)       /*!< 0x00000010 */
+#define HRTIM_ADC3R_AD3MPER           HRTIM_ADC3R_AD3MPER_Msk                  /*!< ADC Trigger 3 on master period */
+#define HRTIM_ADC3R_AD3EEV1_Pos       (5U)
+#define HRTIM_ADC3R_AD3EEV1_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV1_Pos)       /*!< 0x00000020 */
+#define HRTIM_ADC3R_AD3EEV1           HRTIM_ADC3R_AD3EEV1_Msk                  /*!< ADC Trigger 3 on external event 1 */
+#define HRTIM_ADC3R_AD3EEV2_Pos       (6U)
+#define HRTIM_ADC3R_AD3EEV2_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV2_Pos)       /*!< 0x00000040 */
+#define HRTIM_ADC3R_AD3EEV2           HRTIM_ADC3R_AD3EEV2_Msk                  /*!< ADC Trigger 3 on external event 2 */
+#define HRTIM_ADC3R_AD3EEV3_Pos       (7U)
+#define HRTIM_ADC3R_AD3EEV3_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV3_Pos)       /*!< 0x00000080 */
+#define HRTIM_ADC3R_AD3EEV3           HRTIM_ADC3R_AD3EEV3_Msk                  /*!< ADC Trigger 3 on external event 3 */
+#define HRTIM_ADC3R_AD3EEV4_Pos       (8U)
+#define HRTIM_ADC3R_AD3EEV4_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV4_Pos)       /*!< 0x00000100 */
+#define HRTIM_ADC3R_AD3EEV4           HRTIM_ADC3R_AD3EEV4_Msk                  /*!< ADC Trigger 3 on external event 4 */
+#define HRTIM_ADC3R_AD3EEV5_Pos       (9U)
+#define HRTIM_ADC3R_AD3EEV5_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV5_Pos)       /*!< 0x00000200 */
+#define HRTIM_ADC3R_AD3EEV5           HRTIM_ADC3R_AD3EEV5_Msk                  /*!< ADC Trigger 3 on external event 5 */
+#define HRTIM_ADC3R_AD3TAC2_Pos       (10U)
+#define HRTIM_ADC3R_AD3TAC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC2_Pos)       /*!< 0x00000400 */
+#define HRTIM_ADC3R_AD3TAC2           HRTIM_ADC3R_AD3TAC2_Msk                  /*!< ADC Trigger 3 on Timer A compare 2 */
+#define HRTIM_ADC3R_AD3TAC3_Pos       (11U)
+#define HRTIM_ADC3R_AD3TAC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC3_Pos)       /*!< 0x00000800 */
+#define HRTIM_ADC3R_AD3TAC3           HRTIM_ADC3R_AD3TAC3_Msk                  /*!< ADC Trigger 3 on Timer A compare 3 */
+#define HRTIM_ADC3R_AD3TAC4_Pos       (12U)
+#define HRTIM_ADC3R_AD3TAC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC4_Pos)       /*!< 0x00001000 */
+#define HRTIM_ADC3R_AD3TAC4           HRTIM_ADC3R_AD3TAC4_Msk                  /*!< ADC Trigger 3 on Timer A compare 4 */
+#define HRTIM_ADC3R_AD3TAPER_Pos      (13U)
+#define HRTIM_ADC3R_AD3TAPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TAPER_Pos)      /*!< 0x00002000 */
+#define HRTIM_ADC3R_AD3TAPER          HRTIM_ADC3R_AD3TAPER_Msk                 /*!< ADC Trigger 3 on Timer A period */
+#define HRTIM_ADC3R_AD3TARST_Pos      (14U)
+#define HRTIM_ADC3R_AD3TARST_Msk      (0x1UL << HRTIM_ADC3R_AD3TARST_Pos)      /*!< 0x00004000 */
+#define HRTIM_ADC3R_AD3TARST          HRTIM_ADC3R_AD3TARST_Msk                 /*!< ADC Trigger 3 on Timer A reset */
+#define HRTIM_ADC3R_AD3TBC2_Pos       (15U)
+#define HRTIM_ADC3R_AD3TBC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC2_Pos)       /*!< 0x00008000 */
+#define HRTIM_ADC3R_AD3TBC2           HRTIM_ADC3R_AD3TBC2_Msk                  /*!< ADC Trigger 3 on Timer B compare 2 */
+#define HRTIM_ADC3R_AD3TBC3_Pos       (16U)
+#define HRTIM_ADC3R_AD3TBC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC3_Pos)       /*!< 0x00010000 */
+#define HRTIM_ADC3R_AD3TBC3           HRTIM_ADC3R_AD3TBC3_Msk                  /*!< ADC Trigger 3 on Timer B compare 3 */
+#define HRTIM_ADC3R_AD3TBC4_Pos       (17U)
+#define HRTIM_ADC3R_AD3TBC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC4_Pos)       /*!< 0x00020000 */
+#define HRTIM_ADC3R_AD3TBC4           HRTIM_ADC3R_AD3TBC4_Msk                  /*!< ADC Trigger 3 on Timer B compare 4 */
+#define HRTIM_ADC3R_AD3TBPER_Pos      (18U)
+#define HRTIM_ADC3R_AD3TBPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TBPER_Pos)      /*!< 0x00040000 */
+#define HRTIM_ADC3R_AD3TBPER          HRTIM_ADC3R_AD3TBPER_Msk                 /*!< ADC Trigger 3 on Timer B period */
+#define HRTIM_ADC3R_AD3TBRST_Pos      (19U)
+#define HRTIM_ADC3R_AD3TBRST_Msk      (0x1UL << HRTIM_ADC3R_AD3TBRST_Pos)      /*!< 0x00080000 */
+#define HRTIM_ADC3R_AD3TBRST          HRTIM_ADC3R_AD3TBRST_Msk                 /*!< ADC Trigger 3 on Timer B reset */
+#define HRTIM_ADC3R_AD3TCC2_Pos       (20U)
+#define HRTIM_ADC3R_AD3TCC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC2_Pos)       /*!< 0x00100000 */
+#define HRTIM_ADC3R_AD3TCC2           HRTIM_ADC3R_AD3TCC2_Msk                  /*!< ADC Trigger 3 on Timer C compare 2 */
+#define HRTIM_ADC3R_AD3TCC3_Pos       (21U)
+#define HRTIM_ADC3R_AD3TCC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC3_Pos)       /*!< 0x00200000 */
+#define HRTIM_ADC3R_AD3TCC3           HRTIM_ADC3R_AD3TCC3_Msk                  /*!< ADC Trigger 3 on Timer C compare 3 */
+#define HRTIM_ADC3R_AD3TCC4_Pos       (22U)
+#define HRTIM_ADC3R_AD3TCC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC4_Pos)       /*!< 0x00400000 */
+#define HRTIM_ADC3R_AD3TCC4           HRTIM_ADC3R_AD3TCC4_Msk                  /*!< ADC Trigger 3 on Timer C compare 4 */
+#define HRTIM_ADC3R_AD3TCPER_Pos      (23U)
+#define HRTIM_ADC3R_AD3TCPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TCPER_Pos)      /*!< 0x00800000 */
+#define HRTIM_ADC3R_AD3TCPER          HRTIM_ADC3R_AD3TCPER_Msk                 /*!< ADC Trigger 3 on Timer C period */
+#define HRTIM_ADC3R_AD3TDC2_Pos       (24U)
+#define HRTIM_ADC3R_AD3TDC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC2_Pos)       /*!< 0x01000000 */
+#define HRTIM_ADC3R_AD3TDC2           HRTIM_ADC3R_AD3TDC2_Msk                  /*!< ADC Trigger 3 on Timer D compare 2 */
+#define HRTIM_ADC3R_AD3TDC3_Pos       (25U)
+#define HRTIM_ADC3R_AD3TDC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC3_Pos)       /*!< 0x02000000 */
+#define HRTIM_ADC3R_AD3TDC3           HRTIM_ADC3R_AD3TDC3_Msk                  /*!< ADC Trigger 3 on Timer D compare 3 */
+#define HRTIM_ADC3R_AD3TDC4_Pos       (26U)
+#define HRTIM_ADC3R_AD3TDC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC4_Pos)       /*!< 0x04000000 */
+#define HRTIM_ADC3R_AD3TDC4           HRTIM_ADC3R_AD3TDC4_Msk                  /*!< ADC Trigger 3 on Timer D compare 4 */
+#define HRTIM_ADC3R_AD3TDPER_Pos      (27U)
+#define HRTIM_ADC3R_AD3TDPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TDPER_Pos)      /*!< 0x08000000 */
+#define HRTIM_ADC3R_AD3TDPER          HRTIM_ADC3R_AD3TDPER_Msk                 /*!< ADC Trigger 3 on Timer D period */
+#define HRTIM_ADC3R_AD3TEC2_Pos       (28U)
+#define HRTIM_ADC3R_AD3TEC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC2_Pos)       /*!< 0x10000000 */
+#define HRTIM_ADC3R_AD3TEC2           HRTIM_ADC3R_AD3TEC2_Msk                  /*!< ADC Trigger 3 on Timer E compare 2 */
+#define HRTIM_ADC3R_AD3TEC3_Pos       (29U)
+#define HRTIM_ADC3R_AD3TEC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC3_Pos)       /*!< 0x20000000 */
+#define HRTIM_ADC3R_AD3TEC3           HRTIM_ADC3R_AD3TEC3_Msk                  /*!< ADC Trigger 3 on Timer E compare 3 */
+#define HRTIM_ADC3R_AD3TEC4_Pos       (30U)
+#define HRTIM_ADC3R_AD3TEC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC4_Pos)       /*!< 0x40000000 */
+#define HRTIM_ADC3R_AD3TEC4           HRTIM_ADC3R_AD3TEC4_Msk                  /*!< ADC Trigger 3 on Timer E compare 4 */
+#define HRTIM_ADC3R_AD3TEPER_Pos      (31U)
+#define HRTIM_ADC3R_AD3TEPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TEPER_Pos)      /*!< 0x80000000 */
+#define HRTIM_ADC3R_AD3TEPER          HRTIM_ADC3R_AD3TEPER_Msk                 /*!< ADC Trigger 3 on Timer E period */
+
+/*******************  Bit definition for HRTIM_ADC4R register  ****************/
+#define HRTIM_ADC4R_AD4MC1_Pos        (0U)
+#define HRTIM_ADC4R_AD4MC1_Msk        (0x1UL << HRTIM_ADC4R_AD4MC1_Pos)        /*!< 0x00000001 */
+#define HRTIM_ADC4R_AD4MC1            HRTIM_ADC4R_AD4MC1_Msk                   /*!< ADC Trigger 4 on master compare 1 */
+#define HRTIM_ADC4R_AD4MC2_Pos        (1U)
+#define HRTIM_ADC4R_AD4MC2_Msk        (0x1UL << HRTIM_ADC4R_AD4MC2_Pos)        /*!< 0x00000002 */
+#define HRTIM_ADC4R_AD4MC2            HRTIM_ADC4R_AD4MC2_Msk                   /*!< ADC Trigger 4 on master compare 2 */
+#define HRTIM_ADC4R_AD4MC3_Pos        (2U)
+#define HRTIM_ADC4R_AD4MC3_Msk        (0x1UL << HRTIM_ADC4R_AD4MC3_Pos)        /*!< 0x00000004 */
+#define HRTIM_ADC4R_AD4MC3            HRTIM_ADC4R_AD4MC3_Msk                   /*!< ADC Trigger 4 on master compare 3 */
+#define HRTIM_ADC4R_AD4MC4_Pos        (3U)
+#define HRTIM_ADC4R_AD4MC4_Msk        (0x1UL << HRTIM_ADC4R_AD4MC4_Pos)        /*!< 0x00000008 */
+#define HRTIM_ADC4R_AD4MC4            HRTIM_ADC4R_AD4MC4_Msk                   /*!< ADC Trigger 4 on master compare 4 */
+#define HRTIM_ADC4R_AD4MPER_Pos       (4U)
+#define HRTIM_ADC4R_AD4MPER_Msk       (0x1UL << HRTIM_ADC4R_AD4MPER_Pos)       /*!< 0x00000010 */
+#define HRTIM_ADC4R_AD4MPER           HRTIM_ADC4R_AD4MPER_Msk                  /*!< ADC Trigger 4 on master period */
+#define HRTIM_ADC4R_AD4EEV6_Pos       (5U)
+#define HRTIM_ADC4R_AD4EEV6_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV6_Pos)       /*!< 0x00000020 */
+#define HRTIM_ADC4R_AD4EEV6           HRTIM_ADC4R_AD4EEV6_Msk                  /*!< ADC Trigger 4 on external event 6 */
+#define HRTIM_ADC4R_AD4EEV7_Pos       (6U)
+#define HRTIM_ADC4R_AD4EEV7_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV7_Pos)       /*!< 0x00000040 */
+#define HRTIM_ADC4R_AD4EEV7           HRTIM_ADC4R_AD4EEV7_Msk                  /*!< ADC Trigger 4 on external event 7 */
+#define HRTIM_ADC4R_AD4EEV8_Pos       (7U)
+#define HRTIM_ADC4R_AD4EEV8_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV8_Pos)       /*!< 0x00000080 */
+#define HRTIM_ADC4R_AD4EEV8           HRTIM_ADC4R_AD4EEV8_Msk                  /*!< ADC Trigger 4 on external event 8 */
+#define HRTIM_ADC4R_AD4EEV9_Pos       (8U)
+#define HRTIM_ADC4R_AD4EEV9_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV9_Pos)       /*!< 0x00000100 */
+#define HRTIM_ADC4R_AD4EEV9           HRTIM_ADC4R_AD4EEV9_Msk                  /*!< ADC Trigger 4 on external event 9 */
+#define HRTIM_ADC4R_AD4EEV10_Pos      (9U)
+#define HRTIM_ADC4R_AD4EEV10_Msk      (0x1UL << HRTIM_ADC4R_AD4EEV10_Pos)      /*!< 0x00000200 */
+#define HRTIM_ADC4R_AD4EEV10          HRTIM_ADC4R_AD4EEV10_Msk                 /*!< ADC Trigger 4 on external event 10 */
+#define HRTIM_ADC4R_AD4TAC2_Pos       (10U)
+#define HRTIM_ADC4R_AD4TAC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC2_Pos)       /*!< 0x00000400 */
+#define HRTIM_ADC4R_AD4TAC2           HRTIM_ADC4R_AD4TAC2_Msk                  /*!< ADC Trigger 4 on Timer A compare 2 */
+#define HRTIM_ADC4R_AD4TAC3_Pos       (11U)
+#define HRTIM_ADC4R_AD4TAC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC3_Pos)       /*!< 0x00000800 */
+#define HRTIM_ADC4R_AD4TAC3           HRTIM_ADC4R_AD4TAC3_Msk                  /*!< ADC Trigger 4 on Timer A compare 3 */
+#define HRTIM_ADC4R_AD4TAC4_Pos       (12U)
+#define HRTIM_ADC4R_AD4TAC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC4_Pos)       /*!< 0x00001000 */
+#define HRTIM_ADC4R_AD4TAC4           HRTIM_ADC4R_AD4TAC4_Msk                  /*!< ADC Trigger 4 on Timer A compare 4*/
+#define HRTIM_ADC4R_AD4TAPER_Pos      (13U)
+#define HRTIM_ADC4R_AD4TAPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TAPER_Pos)      /*!< 0x00002000 */
+#define HRTIM_ADC4R_AD4TAPER          HRTIM_ADC4R_AD4TAPER_Msk                 /*!< ADC Trigger 4 on Timer A period */
+#define HRTIM_ADC4R_AD4TBC2_Pos       (14U)
+#define HRTIM_ADC4R_AD4TBC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC2_Pos)       /*!< 0x00004000 */
+#define HRTIM_ADC4R_AD4TBC2           HRTIM_ADC4R_AD4TBC2_Msk                  /*!< ADC Trigger 4 on Timer B compare 2 */
+#define HRTIM_ADC4R_AD4TBC3_Pos       (15U)
+#define HRTIM_ADC4R_AD4TBC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC3_Pos)       /*!< 0x00008000 */
+#define HRTIM_ADC4R_AD4TBC3           HRTIM_ADC4R_AD4TBC3_Msk                  /*!< ADC Trigger 4 on Timer B compare 3 */
+#define HRTIM_ADC4R_AD4TBC4_Pos       (16U)
+#define HRTIM_ADC4R_AD4TBC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC4_Pos)       /*!< 0x00010000 */
+#define HRTIM_ADC4R_AD4TBC4           HRTIM_ADC4R_AD4TBC4_Msk                  /*!< ADC Trigger 4 on Timer B compare 4 */
+#define HRTIM_ADC4R_AD4TBPER_Pos      (17U)
+#define HRTIM_ADC4R_AD4TBPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TBPER_Pos)      /*!< 0x00020000 */
+#define HRTIM_ADC4R_AD4TBPER          HRTIM_ADC4R_AD4TBPER_Msk                 /*!< ADC Trigger 4 on Timer B period */
+#define HRTIM_ADC4R_AD4TCC2_Pos       (18U)
+#define HRTIM_ADC4R_AD4TCC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC2_Pos)       /*!< 0x00040000 */
+#define HRTIM_ADC4R_AD4TCC2           HRTIM_ADC4R_AD4TCC2_Msk                  /*!< ADC Trigger 4 on Timer C compare 2 */
+#define HRTIM_ADC4R_AD4TCC3_Pos       (19U)
+#define HRTIM_ADC4R_AD4TCC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC3_Pos)       /*!< 0x00080000 */
+#define HRTIM_ADC4R_AD4TCC3           HRTIM_ADC4R_AD4TCC3_Msk                  /*!< ADC Trigger 4 on Timer C compare 3 */
+#define HRTIM_ADC4R_AD4TCC4_Pos       (20U)
+#define HRTIM_ADC4R_AD4TCC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC4_Pos)       /*!< 0x00100000 */
+#define HRTIM_ADC4R_AD4TCC4           HRTIM_ADC4R_AD4TCC4_Msk                  /*!< ADC Trigger 4 on Timer C compare 4 */
+#define HRTIM_ADC4R_AD4TCPER_Pos      (21U)
+#define HRTIM_ADC4R_AD4TCPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TCPER_Pos)      /*!< 0x00200000 */
+#define HRTIM_ADC4R_AD4TCPER          HRTIM_ADC4R_AD4TCPER_Msk                 /*!< ADC Trigger 4 on Timer C period */
+#define HRTIM_ADC4R_AD4TCRST_Pos      (22U)
+#define HRTIM_ADC4R_AD4TCRST_Msk      (0x1UL << HRTIM_ADC4R_AD4TCRST_Pos)      /*!< 0x00400000 */
+#define HRTIM_ADC4R_AD4TCRST          HRTIM_ADC4R_AD4TCRST_Msk                 /*!< ADC Trigger 4 on Timer C reset */
+#define HRTIM_ADC4R_AD4TDC2_Pos       (23U)
+#define HRTIM_ADC4R_AD4TDC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC2_Pos)       /*!< 0x00800000 */
+#define HRTIM_ADC4R_AD4TDC2           HRTIM_ADC4R_AD4TDC2_Msk                  /*!< ADC Trigger 4 on Timer D compare 2 */
+#define HRTIM_ADC4R_AD4TDC3_Pos       (24U)
+#define HRTIM_ADC4R_AD4TDC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC3_Pos)       /*!< 0x01000000 */
+#define HRTIM_ADC4R_AD4TDC3           HRTIM_ADC4R_AD4TDC3_Msk                  /*!< ADC Trigger 4 on Timer D compare 3 */
+#define HRTIM_ADC4R_AD4TDC4_Pos       (25U)
+#define HRTIM_ADC4R_AD4TDC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC4_Pos)       /*!< 0x02000000 */
+#define HRTIM_ADC4R_AD4TDC4           HRTIM_ADC4R_AD4TDC4_Msk                  /*!< ADC Trigger 4 on Timer D compare 4*/
+#define HRTIM_ADC4R_AD4TDPER_Pos      (26U)
+#define HRTIM_ADC4R_AD4TDPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TDPER_Pos)      /*!< 0x04000000 */
+#define HRTIM_ADC4R_AD4TDPER          HRTIM_ADC4R_AD4TDPER_Msk                 /*!< ADC Trigger 4 on Timer D period */
+#define HRTIM_ADC4R_AD4TDRST_Pos      (27U)
+#define HRTIM_ADC4R_AD4TDRST_Msk      (0x1UL << HRTIM_ADC4R_AD4TDRST_Pos)      /*!< 0x08000000 */
+#define HRTIM_ADC4R_AD4TDRST          HRTIM_ADC4R_AD4TDRST_Msk                 /*!< ADC Trigger 4 on Timer D reset */
+#define HRTIM_ADC4R_AD4TEC2_Pos       (28U)
+#define HRTIM_ADC4R_AD4TEC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC2_Pos)       /*!< 0x10000000 */
+#define HRTIM_ADC4R_AD4TEC2           HRTIM_ADC4R_AD4TEC2_Msk                  /*!< ADC Trigger 4 on Timer E compare 2 */
+#define HRTIM_ADC4R_AD4TEC3_Pos       (29U)
+#define HRTIM_ADC4R_AD4TEC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC3_Pos)       /*!< 0x20000000 */
+#define HRTIM_ADC4R_AD4TEC3           HRTIM_ADC4R_AD4TEC3_Msk                  /*!< ADC Trigger 4 on Timer E compare 3 */
+#define HRTIM_ADC4R_AD4TEC4_Pos       (30U)
+#define HRTIM_ADC4R_AD4TEC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC4_Pos)       /*!< 0x40000000 */
+#define HRTIM_ADC4R_AD4TEC4           HRTIM_ADC4R_AD4TEC4_Msk                  /*!< ADC Trigger 4 on Timer E compare 4 */
+#define HRTIM_ADC4R_AD4TERST_Pos      (31U)
+#define HRTIM_ADC4R_AD4TERST_Msk      (0x1UL << HRTIM_ADC4R_AD4TERST_Pos)      /*!< 0x80000000 */
+#define HRTIM_ADC4R_AD4TERST          HRTIM_ADC4R_AD4TERST_Msk                 /*!< ADC Trigger 4 on Timer E reset */
+
+/*******************  Bit definition for HRTIM_FLTINR1 register  ***************/
+#define HRTIM_FLTINR1_FLT1E_Pos       (0U)
+#define HRTIM_FLTINR1_FLT1E_Msk       (0x1UL << HRTIM_FLTINR1_FLT1E_Pos)       /*!< 0x00000001 */
+#define HRTIM_FLTINR1_FLT1E           HRTIM_FLTINR1_FLT1E_Msk                  /*!< Fault 1 enable */
+#define HRTIM_FLTINR1_FLT1P_Pos       (1U)
+#define HRTIM_FLTINR1_FLT1P_Msk       (0x1UL << HRTIM_FLTINR1_FLT1P_Pos)       /*!< 0x00000002 */
+#define HRTIM_FLTINR1_FLT1P           HRTIM_FLTINR1_FLT1P_Msk                  /*!< Fault 1 polarity */
+#define HRTIM_FLTINR1_FLT1SRC_Pos     (2U)
+#define HRTIM_FLTINR1_FLT1SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT1SRC_Pos)     /*!< 0x00000004 */
+#define HRTIM_FLTINR1_FLT1SRC         HRTIM_FLTINR1_FLT1SRC_Msk                /*!< Fault 1 source */
+#define HRTIM_FLTINR1_FLT1F_Pos       (3U)
+#define HRTIM_FLTINR1_FLT1F_Msk       (0xFUL << HRTIM_FLTINR1_FLT1F_Pos)       /*!< 0x00000078 */
+#define HRTIM_FLTINR1_FLT1F           HRTIM_FLTINR1_FLT1F_Msk                  /*!< Fault 1 filter */
+#define HRTIM_FLTINR1_FLT1F_0         (0x1UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000008 */
+#define HRTIM_FLTINR1_FLT1F_1         (0x2UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000010 */
+#define HRTIM_FLTINR1_FLT1F_2         (0x4UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000020 */
+#define HRTIM_FLTINR1_FLT1F_3         (0x8UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000040 */
+#define HRTIM_FLTINR1_FLT1LCK_Pos     (7U)
+#define HRTIM_FLTINR1_FLT1LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT1LCK_Pos)     /*!< 0x00000080 */
+#define HRTIM_FLTINR1_FLT1LCK         HRTIM_FLTINR1_FLT1LCK_Msk                /*!< Fault 1 lock */
+
+#define HRTIM_FLTINR1_FLT2E_Pos       (8U)
+#define HRTIM_FLTINR1_FLT2E_Msk       (0x1UL << HRTIM_FLTINR1_FLT2E_Pos)       /*!< 0x00000100 */
+#define HRTIM_FLTINR1_FLT2E           HRTIM_FLTINR1_FLT2E_Msk                  /*!< Fault 2 enable */
+#define HRTIM_FLTINR1_FLT2P_Pos       (9U)
+#define HRTIM_FLTINR1_FLT2P_Msk       (0x1UL << HRTIM_FLTINR1_FLT2P_Pos)       /*!< 0x00000200 */
+#define HRTIM_FLTINR1_FLT2P           HRTIM_FLTINR1_FLT2P_Msk                  /*!< Fault 2 polarity */
+#define HRTIM_FLTINR1_FLT2SRC_Pos     (10U)
+#define HRTIM_FLTINR1_FLT2SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT2SRC_Pos)     /*!< 0x00000400 */
+#define HRTIM_FLTINR1_FLT2SRC         HRTIM_FLTINR1_FLT2SRC_Msk                /*!< Fault 2 source */
+#define HRTIM_FLTINR1_FLT2F_Pos       (11U)
+#define HRTIM_FLTINR1_FLT2F_Msk       (0xFUL << HRTIM_FLTINR1_FLT2F_Pos)       /*!< 0x00007800 */
+#define HRTIM_FLTINR1_FLT2F           HRTIM_FLTINR1_FLT2F_Msk                  /*!< Fault 2 filter */
+#define HRTIM_FLTINR1_FLT2F_0         (0x1UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00000800 */
+#define HRTIM_FLTINR1_FLT2F_1         (0x2UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00001000 */
+#define HRTIM_FLTINR1_FLT2F_2         (0x4UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00002000 */
+#define HRTIM_FLTINR1_FLT2F_3         (0x8UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00004000 */
+#define HRTIM_FLTINR1_FLT2LCK_Pos     (15U)
+#define HRTIM_FLTINR1_FLT2LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT2LCK_Pos)     /*!< 0x00008000 */
+#define HRTIM_FLTINR1_FLT2LCK         HRTIM_FLTINR1_FLT2LCK_Msk                /*!< Fault 2 lock */
+
+#define HRTIM_FLTINR1_FLT3E_Pos       (16U)
+#define HRTIM_FLTINR1_FLT3E_Msk       (0x1UL << HRTIM_FLTINR1_FLT3E_Pos)       /*!< 0x00010000 */
+#define HRTIM_FLTINR1_FLT3E           HRTIM_FLTINR1_FLT3E_Msk                  /*!< Fault 3 enable */
+#define HRTIM_FLTINR1_FLT3P_Pos       (17U)
+#define HRTIM_FLTINR1_FLT3P_Msk       (0x1UL << HRTIM_FLTINR1_FLT3P_Pos)       /*!< 0x00020000 */
+#define HRTIM_FLTINR1_FLT3P           HRTIM_FLTINR1_FLT3P_Msk                  /*!< Fault 3 polarity */
+#define HRTIM_FLTINR1_FLT3SRC_Pos     (18U)
+#define HRTIM_FLTINR1_FLT3SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT3SRC_Pos)     /*!< 0x00040000 */
+#define HRTIM_FLTINR1_FLT3SRC         HRTIM_FLTINR1_FLT3SRC_Msk                /*!< Fault 3 source */
+#define HRTIM_FLTINR1_FLT3F_Pos       (19U)
+#define HRTIM_FLTINR1_FLT3F_Msk       (0xFUL << HRTIM_FLTINR1_FLT3F_Pos)       /*!< 0x00780000 */
+#define HRTIM_FLTINR1_FLT3F           HRTIM_FLTINR1_FLT3F_Msk                  /*!< Fault 3 filter */
+#define HRTIM_FLTINR1_FLT3F_0         (0x1UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00080000 */
+#define HRTIM_FLTINR1_FLT3F_1         (0x2UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00100000 */
+#define HRTIM_FLTINR1_FLT3F_2         (0x4UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00200000 */
+#define HRTIM_FLTINR1_FLT3F_3         (0x8UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00400000 */
+#define HRTIM_FLTINR1_FLT3LCK_Pos     (23U)
+#define HRTIM_FLTINR1_FLT3LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT3LCK_Pos)     /*!< 0x00800000 */
+#define HRTIM_FLTINR1_FLT3LCK         HRTIM_FLTINR1_FLT3LCK_Msk                /*!< Fault 3 lock */
+
+#define HRTIM_FLTINR1_FLT4E_Pos       (24U)
+#define HRTIM_FLTINR1_FLT4E_Msk       (0x1UL << HRTIM_FLTINR1_FLT4E_Pos)       /*!< 0x01000000 */
+#define HRTIM_FLTINR1_FLT4E           HRTIM_FLTINR1_FLT4E_Msk                  /*!< Fault 4 enable */
+#define HRTIM_FLTINR1_FLT4P_Pos       (25U)
+#define HRTIM_FLTINR1_FLT4P_Msk       (0x1UL << HRTIM_FLTINR1_FLT4P_Pos)       /*!< 0x02000000 */
+#define HRTIM_FLTINR1_FLT4P           HRTIM_FLTINR1_FLT4P_Msk                  /*!< Fault 4 polarity */
+#define HRTIM_FLTINR1_FLT4SRC_Pos     (26U)
+#define HRTIM_FLTINR1_FLT4SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT4SRC_Pos)     /*!< 0x04000000 */
+#define HRTIM_FLTINR1_FLT4SRC         HRTIM_FLTINR1_FLT4SRC_Msk                /*!< Fault 4 source */
+#define HRTIM_FLTINR1_FLT4F_Pos       (27U)
+#define HRTIM_FLTINR1_FLT4F_Msk       (0xFUL << HRTIM_FLTINR1_FLT4F_Pos)       /*!< 0x78000000 */
+#define HRTIM_FLTINR1_FLT4F           HRTIM_FLTINR1_FLT4F_Msk                  /*!< Fault 4 filter */
+#define HRTIM_FLTINR1_FLT4F_0         (0x1UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x08000000 */
+#define HRTIM_FLTINR1_FLT4F_1         (0x2UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x10000000 */
+#define HRTIM_FLTINR1_FLT4F_2         (0x4UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x20000000 */
+#define HRTIM_FLTINR1_FLT4F_3         (0x8UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x40000000 */
+#define HRTIM_FLTINR1_FLT4LCK_Pos     (31U)
+#define HRTIM_FLTINR1_FLT4LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT4LCK_Pos)     /*!< 0x80000000 */
+#define HRTIM_FLTINR1_FLT4LCK         HRTIM_FLTINR1_FLT4LCK_Msk                /*!< Fault 4 lock */
+
+/*******************  Bit definition for HRTIM_FLTINR2 register  ***************/
+#define HRTIM_FLTINR2_FLT5E_Pos       (0U)
+#define HRTIM_FLTINR2_FLT5E_Msk       (0x1UL << HRTIM_FLTINR2_FLT5E_Pos)       /*!< 0x00000001 */
+#define HRTIM_FLTINR2_FLT5E           HRTIM_FLTINR2_FLT5E_Msk                  /*!< Fault 5 enable */
+#define HRTIM_FLTINR2_FLT5P_Pos       (1U)
+#define HRTIM_FLTINR2_FLT5P_Msk       (0x1UL << HRTIM_FLTINR2_FLT5P_Pos)       /*!< 0x00000002 */
+#define HRTIM_FLTINR2_FLT5P           HRTIM_FLTINR2_FLT5P_Msk                  /*!< Fault 5 polarity */
+#define HRTIM_FLTINR2_FLT5SRC_Pos     (2U)
+#define HRTIM_FLTINR2_FLT5SRC_Msk     (0x1UL << HRTIM_FLTINR2_FLT5SRC_Pos)     /*!< 0x00000004 */
+#define HRTIM_FLTINR2_FLT5SRC         HRTIM_FLTINR2_FLT5SRC_Msk                /*!< Fault 5 source */
+#define HRTIM_FLTINR2_FLT5F_Pos       (3U)
+#define HRTIM_FLTINR2_FLT5F_Msk       (0xFUL << HRTIM_FLTINR2_FLT5F_Pos)       /*!< 0x00000078 */
+#define HRTIM_FLTINR2_FLT5F           HRTIM_FLTINR2_FLT5F_Msk                  /*!< Fault 5 filter */
+#define HRTIM_FLTINR2_FLT5F_0         (0x1UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000008 */
+#define HRTIM_FLTINR2_FLT5F_1         (0x2UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000010 */
+#define HRTIM_FLTINR2_FLT5F_2         (0x4UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000020 */
+#define HRTIM_FLTINR2_FLT5F_3         (0x8UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000040 */
+#define HRTIM_FLTINR2_FLT5LCK_Pos     (7U)
+#define HRTIM_FLTINR2_FLT5LCK_Msk     (0x1UL << HRTIM_FLTINR2_FLT5LCK_Pos)     /*!< 0x00000080 */
+#define HRTIM_FLTINR2_FLT5LCK         HRTIM_FLTINR2_FLT5LCK_Msk                /*!< Fault 5 lock */
+#define HRTIM_FLTINR2_FLTSD_Pos       (24U)
+#define HRTIM_FLTINR2_FLTSD_Msk       (0x3UL << HRTIM_FLTINR2_FLTSD_Pos)       /*!< 0x03000000 */
+#define HRTIM_FLTINR2_FLTSD           HRTIM_FLTINR2_FLTSD_Msk                  /*!< Fault sampling clock division */
+#define HRTIM_FLTINR2_FLTSD_0         (0x1UL << HRTIM_FLTINR2_FLTSD_Pos)        /*!< 0x01000000 */
+#define HRTIM_FLTINR2_FLTSD_1         (0x2UL << HRTIM_FLTINR2_FLTSD_Pos)        /*!< 0x02000000 */
+
+/*******************  Bit definition for HRTIM_BDMUPR register  ***************/
+#define HRTIM_BDMUPR_MCR_Pos          (0U)
+#define HRTIM_BDMUPR_MCR_Msk          (0x1UL << HRTIM_BDMUPR_MCR_Pos)          /*!< 0x00000001 */
+#define HRTIM_BDMUPR_MCR              HRTIM_BDMUPR_MCR_Msk                     /*!< MCR register update enable */
+#define HRTIM_BDMUPR_MICR_Pos         (1U)
+#define HRTIM_BDMUPR_MICR_Msk         (0x1UL << HRTIM_BDMUPR_MICR_Pos)         /*!< 0x00000002 */
+#define HRTIM_BDMUPR_MICR             HRTIM_BDMUPR_MICR_Msk                    /*!< MICR register update enable */
+#define HRTIM_BDMUPR_MDIER_Pos        (2U)
+#define HRTIM_BDMUPR_MDIER_Msk        (0x1UL << HRTIM_BDMUPR_MDIER_Pos)        /*!< 0x00000004 */
+#define HRTIM_BDMUPR_MDIER            HRTIM_BDMUPR_MDIER_Msk                   /*!< MDIER register update enable */
+#define HRTIM_BDMUPR_MCNT_Pos         (3U)
+#define HRTIM_BDMUPR_MCNT_Msk         (0x1UL << HRTIM_BDMUPR_MCNT_Pos)         /*!< 0x00000008 */
+#define HRTIM_BDMUPR_MCNT             HRTIM_BDMUPR_MCNT_Msk                    /*!< MCNT register update enable */
+#define HRTIM_BDMUPR_MPER_Pos         (4U)
+#define HRTIM_BDMUPR_MPER_Msk         (0x1UL << HRTIM_BDMUPR_MPER_Pos)         /*!< 0x00000010 */
+#define HRTIM_BDMUPR_MPER             HRTIM_BDMUPR_MPER_Msk                    /*!< MPER register update enable */
+#define HRTIM_BDMUPR_MREP_Pos         (5U)
+#define HRTIM_BDMUPR_MREP_Msk         (0x1UL << HRTIM_BDMUPR_MREP_Pos)         /*!< 0x00000020 */
+#define HRTIM_BDMUPR_MREP             HRTIM_BDMUPR_MREP_Msk                    /*!< MREP register update enable */
+#define HRTIM_BDMUPR_MCMP1_Pos        (6U)
+#define HRTIM_BDMUPR_MCMP1_Msk        (0x1UL << HRTIM_BDMUPR_MCMP1_Pos)        /*!< 0x00000040 */
+#define HRTIM_BDMUPR_MCMP1            HRTIM_BDMUPR_MCMP1_Msk                   /*!< MCMP1 register update enable */
+#define HRTIM_BDMUPR_MCMP2_Pos        (7U)
+#define HRTIM_BDMUPR_MCMP2_Msk        (0x1UL << HRTIM_BDMUPR_MCMP2_Pos)        /*!< 0x00000080 */
+#define HRTIM_BDMUPR_MCMP2            HRTIM_BDMUPR_MCMP2_Msk                   /*!< MCMP2 register update enable */
+#define HRTIM_BDMUPR_MCMP3_Pos        (8U)
+#define HRTIM_BDMUPR_MCMP3_Msk        (0x1UL << HRTIM_BDMUPR_MCMP3_Pos)        /*!< 0x00000100 */
+#define HRTIM_BDMUPR_MCMP3            HRTIM_BDMUPR_MCMP3_Msk                   /*!< MCMP3 register update enable */
+#define HRTIM_BDMUPR_MCMP4_Pos        (9U)
+#define HRTIM_BDMUPR_MCMP4_Msk        (0x1UL << HRTIM_BDMUPR_MCMP4_Pos)        /*!< 0x00000200 */
+#define HRTIM_BDMUPR_MCMP4            HRTIM_BDMUPR_MCMP4_Msk                   /*!< MPCMP4 register update enable */
+
+/*******************  Bit definition for HRTIM_BDTUPR register  ***************/
+#define HRTIM_BDTUPR_TIMCR_Pos        (0U)
+#define HRTIM_BDTUPR_TIMCR_Msk        (0x1UL << HRTIM_BDTUPR_TIMCR_Pos)        /*!< 0x00000001 */
+#define HRTIM_BDTUPR_TIMCR            HRTIM_BDTUPR_TIMCR_Msk                   /*!<  TIMCR register update enable */
+#define HRTIM_BDTUPR_TIMICR_Pos       (1U)
+#define HRTIM_BDTUPR_TIMICR_Msk       (0x1UL << HRTIM_BDTUPR_TIMICR_Pos)       /*!< 0x00000002 */
+#define HRTIM_BDTUPR_TIMICR           HRTIM_BDTUPR_TIMICR_Msk                  /*!<  TIMICR register update enable */
+#define HRTIM_BDTUPR_TIMDIER_Pos      (2U)
+#define HRTIM_BDTUPR_TIMDIER_Msk      (0x1UL << HRTIM_BDTUPR_TIMDIER_Pos)      /*!< 0x00000004 */
+#define HRTIM_BDTUPR_TIMDIER          HRTIM_BDTUPR_TIMDIER_Msk                 /*!<  TIMDIER register update enable */
+#define HRTIM_BDTUPR_TIMCNT_Pos       (3U)
+#define HRTIM_BDTUPR_TIMCNT_Msk       (0x1UL << HRTIM_BDTUPR_TIMCNT_Pos)       /*!< 0x00000008 */
+#define HRTIM_BDTUPR_TIMCNT           HRTIM_BDTUPR_TIMCNT_Msk                  /*!<  TIMCNT register update enable */
+#define HRTIM_BDTUPR_TIMPER_Pos       (4U)
+#define HRTIM_BDTUPR_TIMPER_Msk       (0x1UL << HRTIM_BDTUPR_TIMPER_Pos)       /*!< 0x00000010 */
+#define HRTIM_BDTUPR_TIMPER           HRTIM_BDTUPR_TIMPER_Msk                  /*!<  TIMPER register update enable */
+#define HRTIM_BDTUPR_TIMREP_Pos       (5U)
+#define HRTIM_BDTUPR_TIMREP_Msk       (0x1UL << HRTIM_BDTUPR_TIMREP_Pos)       /*!< 0x00000020 */
+#define HRTIM_BDTUPR_TIMREP           HRTIM_BDTUPR_TIMREP_Msk                  /*!<  TIMREP register update enable */
+#define HRTIM_BDTUPR_TIMCMP1_Pos      (6U)
+#define HRTIM_BDTUPR_TIMCMP1_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP1_Pos)      /*!< 0x00000040 */
+#define HRTIM_BDTUPR_TIMCMP1          HRTIM_BDTUPR_TIMCMP1_Msk                 /*!<  TIMCMP1 register update enable */
+#define HRTIM_BDTUPR_TIMCMP2_Pos      (7U)
+#define HRTIM_BDTUPR_TIMCMP2_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP2_Pos)      /*!< 0x00000080 */
+#define HRTIM_BDTUPR_TIMCMP2          HRTIM_BDTUPR_TIMCMP2_Msk                 /*!<  TIMCMP2 register update enable */
+#define HRTIM_BDTUPR_TIMCMP3_Pos      (8U)
+#define HRTIM_BDTUPR_TIMCMP3_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP3_Pos)      /*!< 0x00000100 */
+#define HRTIM_BDTUPR_TIMCMP3          HRTIM_BDTUPR_TIMCMP3_Msk                 /*!<  TIMCMP3 register update enable */
+#define HRTIM_BDTUPR_TIMCMP4_Pos      (9U)
+#define HRTIM_BDTUPR_TIMCMP4_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP4_Pos)      /*!< 0x00000200 */
+#define HRTIM_BDTUPR_TIMCMP4          HRTIM_BDTUPR_TIMCMP4_Msk                 /*!<  TIMCMP4 register update enable */
+#define HRTIM_BDTUPR_TIMDTR_Pos       (10U)
+#define HRTIM_BDTUPR_TIMDTR_Msk       (0x1UL << HRTIM_BDTUPR_TIMDTR_Pos)       /*!< 0x00000400 */
+#define HRTIM_BDTUPR_TIMDTR           HRTIM_BDTUPR_TIMDTR_Msk                  /*!<  TIMDTR register update enable */
+#define HRTIM_BDTUPR_TIMSET1R_Pos     (11U)
+#define HRTIM_BDTUPR_TIMSET1R_Msk     (0x1UL << HRTIM_BDTUPR_TIMSET1R_Pos)     /*!< 0x00000800 */
+#define HRTIM_BDTUPR_TIMSET1R         HRTIM_BDTUPR_TIMSET1R_Msk                /*!<  TIMSET1R register update enable */
+#define HRTIM_BDTUPR_TIMRST1R_Pos     (12U)
+#define HRTIM_BDTUPR_TIMRST1R_Msk     (0x1UL << HRTIM_BDTUPR_TIMRST1R_Pos)     /*!< 0x00001000 */
+#define HRTIM_BDTUPR_TIMRST1R         HRTIM_BDTUPR_TIMRST1R_Msk                /*!<  TIMRST1R register update enable */
+#define HRTIM_BDTUPR_TIMSET2R_Pos     (13U)
+#define HRTIM_BDTUPR_TIMSET2R_Msk     (0x1UL << HRTIM_BDTUPR_TIMSET2R_Pos)     /*!< 0x00002000 */
+#define HRTIM_BDTUPR_TIMSET2R         HRTIM_BDTUPR_TIMSET2R_Msk                /*!<  TIMSET2R register update enable */
+#define HRTIM_BDTUPR_TIMRST2R_Pos     (14U)
+#define HRTIM_BDTUPR_TIMRST2R_Msk     (0x1UL << HRTIM_BDTUPR_TIMRST2R_Pos)     /*!< 0x00004000 */
+#define HRTIM_BDTUPR_TIMRST2R         HRTIM_BDTUPR_TIMRST2R_Msk                /*!<  TIMRST2R register update enable */
+#define HRTIM_BDTUPR_TIMEEFR1_Pos     (15U)
+#define HRTIM_BDTUPR_TIMEEFR1_Msk     (0x1UL << HRTIM_BDTUPR_TIMEEFR1_Pos)     /*!< 0x00008000 */
+#define HRTIM_BDTUPR_TIMEEFR1         HRTIM_BDTUPR_TIMEEFR1_Msk                /*!<  TIMEEFR1 register update enable */
+#define HRTIM_BDTUPR_TIMEEFR2_Pos     (16U)
+#define HRTIM_BDTUPR_TIMEEFR2_Msk     (0x1UL << HRTIM_BDTUPR_TIMEEFR2_Pos)     /*!< 0x00010000 */
+#define HRTIM_BDTUPR_TIMEEFR2         HRTIM_BDTUPR_TIMEEFR2_Msk                /*!<  TIMEEFR2 register update enable */
+#define HRTIM_BDTUPR_TIMRSTR_Pos      (17U)
+#define HRTIM_BDTUPR_TIMRSTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMRSTR_Pos)      /*!< 0x00020000 */
+#define HRTIM_BDTUPR_TIMRSTR          HRTIM_BDTUPR_TIMRSTR_Msk                 /*!<  TIMRSTR register update enable */
+#define HRTIM_BDTUPR_TIMCHPR_Pos      (18U)
+#define HRTIM_BDTUPR_TIMCHPR_Msk      (0x1UL << HRTIM_BDTUPR_TIMCHPR_Pos)      /*!< 0x00040000 */
+#define HRTIM_BDTUPR_TIMCHPR          HRTIM_BDTUPR_TIMCHPR_Msk                 /*!<  TIMCHPR register update enable */
+#define HRTIM_BDTUPR_TIMOUTR_Pos      (19U)
+#define HRTIM_BDTUPR_TIMOUTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMOUTR_Pos)      /*!< 0x00080000 */
+#define HRTIM_BDTUPR_TIMOUTR          HRTIM_BDTUPR_TIMOUTR_Msk                 /*!<  TIMOUTR register update enable */
+#define HRTIM_BDTUPR_TIMFLTR_Pos      (20U)
+#define HRTIM_BDTUPR_TIMFLTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMFLTR_Pos)      /*!< 0x00100000 */
+#define HRTIM_BDTUPR_TIMFLTR          HRTIM_BDTUPR_TIMFLTR_Msk                 /*!<  TIMFLTR register update enable */
+
+/*******************  Bit definition for HRTIM_BDMADR register  ***************/
+#define HRTIM_BDMADR_BDMADR_Pos       (0U)
+#define HRTIM_BDMADR_BDMADR_Msk       (0xFFFFFFFFUL << HRTIM_BDMADR_BDMADR_Pos) /*!< 0xFFFFFFFF */
+#define HRTIM_BDMADR_BDMADR           HRTIM_BDMADR_BDMADR_Msk                  /*!<  Burst DMA Data register */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             RAM ECC monitoring                             */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for RAMECC_IER register  ******************/
+#define RAMECC_IER_GECCDEBWIE_Pos         (3U)
+#define RAMECC_IER_GECCDEBWIE_Msk         (0x1UL << RAMECC_IER_GECCDEBWIE_Pos)  /*!< 0x00000008 */
+#define RAMECC_IER_GECCDEBWIE             RAMECC_IER_GECCDEBWIE_Msk             /*!< Global ECC double error on byte write (BW) interrupt enable */
+#define RAMECC_IER_GECCDEIE_Pos           (2U)
+#define RAMECC_IER_GECCDEIE_Msk           (0x1UL << RAMECC_IER_GECCDEIE_Pos)    /*!< 0x00000004 */
+#define RAMECC_IER_GECCDEIE               RAMECC_IER_GECCDEIE_Msk               /*!< Global ECC double error interrupt enable */
+#define RAMECC_IER_GECCSEIE_Pos           (1U)
+#define RAMECC_IER_GECCSEIE_Msk           (0x1UL << RAMECC_IER_GECCSEIE_Pos)    /*!< 0x00000002 */
+#define RAMECC_IER_GECCSEIE               RAMECC_IER_GECCSEIE_Msk               /*!< Global ECC single error interrupt enable */
+#define RAMECC_IER_GIE_Pos                (0U)
+#define RAMECC_IER_GIE_Msk                (0x1UL << RAMECC_IER_GIE_Pos)         /*!< 0x00000001 */
+#define RAMECC_IER_GIE                    RAMECC_IER_GIE_Msk                    /*!< Global interrupt enable */
+
+/*******************  Bit definition for RAMECC_CR register  ******************/
+#define RAMECC_CR_ECCELEN_Pos             (5U)
+#define RAMECC_CR_ECCELEN_Msk             (0x1UL << RAMECC_CR_ECCELEN_Pos)      /*!< 0x00000020 */
+#define RAMECC_CR_ECCELEN                 RAMECC_CR_ECCELEN_Msk                 /*!< ECC error latching enable */
+#define RAMECC_CR_ECCDEBWIE_Pos           (4U)
+#define RAMECC_CR_ECCDEBWIE_Msk           (0x1UL << RAMECC_CR_ECCDEBWIE_Pos)    /*!< 0x00000010 */
+#define RAMECC_CR_ECCDEBWIE               RAMECC_CR_ECCDEBWIE_Msk               /*!< ECC double error on byte write (BW) interrupt enable */
+#define RAMECC_CR_ECCDEIE_Pos             (3U)
+#define RAMECC_CR_ECCDEIE_Msk             (0x1UL << RAMECC_CR_ECCDEIE_Pos)      /*!< 0x00000008 */
+#define RAMECC_CR_ECCDEIE                 RAMECC_CR_ECCDEIE_Msk                 /*!< ECC double error interrupt enable */
+#define RAMECC_CR_ECCSEIE_Pos             (2U)
+#define RAMECC_CR_ECCSEIE_Msk             (0x1UL << RAMECC_CR_ECCSEIE_Pos)      /*!< 0x00000004 */
+#define RAMECC_CR_ECCSEIE                 RAMECC_CR_ECCSEIE_Msk                 /*!< ECC single error interrupt enable */
+
+/*******************  Bit definition for RAMECC_SR register  ******************/
+#define RAMECC_SR_DEBWDF_Pos             (2U)
+#define RAMECC_SR_DEBWDF_Msk             (0x1UL << RAMECC_SR_DEBWDF_Pos)        /*!< 0x00000004 */
+#define RAMECC_SR_DEBWDF                 RAMECC_SR_DEBWDF_Msk                   /*!< ECC double error on byte write (BW) detected flag */
+#define RAMECC_SR_DEDF_Pos               (1U)
+#define RAMECC_SR_DEDF_Msk               (0x1UL << RAMECC_SR_DEDF_Pos)          /*!< 0x00000002 */
+#define RAMECC_SR_DEDF                   RAMECC_SR_DEDF_Msk                     /*!< ECC double error detected flag */
+#define RAMECC_SR_SEDCF_Pos              (0U)
+#define RAMECC_SR_SEDCF_Msk              (0x1UL << RAMECC_SR_SEDCF_Pos)         /*!< 0x00000001 */
+#define RAMECC_SR_SEDCF                  RAMECC_SR_SEDCF_Msk                    /*!< ECC single error detected and corrected flag */
+
+/******************  Bit definition for RAMECC_FAR register  ******************/
+#define RAMECC_FAR_FADD_Pos              (0U)
+#define RAMECC_FAR_FADD_Msk              (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos)  /*!< 0xFFFFFFFF */
+#define RAMECC_FAR_FADD                  RAMECC_FAR_FADD_Msk                    /*!< ECC error failing address */
+
+/******************  Bit definition for RAMECC_FDRL register  *****************/
+#define RAMECC_FAR_FDATAL_Pos            (0U)
+#define RAMECC_FAR_FDATAL_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAL_Pos)/*!< 0xFFFFFFFF */
+#define RAMECC_FAR_FDATAL                RAMECC_FAR_FDATAL_Msk                  /*!< ECC error failing address */
+
+/******************  Bit definition for RAMECC_FDRH register  *****************/
+#define RAMECC_FAR_FDATAH_Pos            (0U)
+#define RAMECC_FAR_FDATAH_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAH_Pos)/*!< 0xFFFFFFFF */
+#define RAMECC_FAR_FDATAH                RAMECC_FAR_FDATAH_Msk                  /* Failing data high (64-bit memory) */
+
+/*****************  Bit definition for RAMECC_FECR register  ******************/
+#define RAMECC_FECR_FEC_Pos              (0U)
+#define RAMECC_FECR_FEC_Msk              (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos)  /*!< 0xFFFFFFFF */
+#define RAMECC_FECR_FEC                  RAMECC_FECR_FEC_Msk                    /*!< Failing error code */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                MDIOS                                        */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for MDIOS_CR register  *******************/
+#define MDIOS_CR_EN_Pos                (0U)
+#define MDIOS_CR_EN_Msk                (0x1UL << MDIOS_CR_EN_Pos)              /*!< 0x00000001 */
+#define MDIOS_CR_EN                    MDIOS_CR_EN_Msk                         /*!<  MDIOS slave peripheral enable */
+#define MDIOS_CR_WRIE_Pos              (1U)
+#define MDIOS_CR_WRIE_Msk              (0x1UL << MDIOS_CR_WRIE_Pos)            /*!< 0x00000002 */
+#define MDIOS_CR_WRIE                  MDIOS_CR_WRIE_Msk                       /*!<  MDIOS slave register write interrupt enable. */
+#define MDIOS_CR_RDIE_Pos              (2U)
+#define MDIOS_CR_RDIE_Msk              (0x1UL << MDIOS_CR_RDIE_Pos)            /*!< 0x00000004 */
+#define MDIOS_CR_RDIE                  MDIOS_CR_RDIE_Msk                       /*!<  MDIOS slave register read interrupt enable. */
+#define MDIOS_CR_EIE_Pos               (3U)
+#define MDIOS_CR_EIE_Msk               (0x1UL << MDIOS_CR_EIE_Pos)             /*!< 0x00000008 */
+#define MDIOS_CR_EIE                   MDIOS_CR_EIE_Msk                        /*!<  MDIOS slave register error interrupt enable. */
+#define MDIOS_CR_DPC_Pos               (7U)
+#define MDIOS_CR_DPC_Msk               (0x1UL << MDIOS_CR_DPC_Pos)             /*!< 0x00000080 */
+#define MDIOS_CR_DPC                   MDIOS_CR_DPC_Msk                        /*!<  MDIOS slave disable preamble check. */
+#define MDIOS_CR_PORT_ADDRESS_Pos      (8U)
+#define MDIOS_CR_PORT_ADDRESS_Msk      (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos)   /*!< 0x00001F00 */
+#define MDIOS_CR_PORT_ADDRESS          MDIOS_CR_PORT_ADDRESS_Msk               /*!<  MDIOS slave port address mask. */
+#define MDIOS_CR_PORT_ADDRESS_0        (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000100 */
+#define MDIOS_CR_PORT_ADDRESS_1        (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000200 */
+#define MDIOS_CR_PORT_ADDRESS_2        (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000400 */
+#define MDIOS_CR_PORT_ADDRESS_3        (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000800 */
+#define MDIOS_CR_PORT_ADDRESS_4        (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00001000 */
+
+/********************  Bit definition for MDIOS_SR register  *******************/
+#define MDIOS_SR_PERF_Pos              (0U)
+#define MDIOS_SR_PERF_Msk              (0x1UL << MDIOS_SR_PERF_Pos)            /*!< 0x00000001 */
+#define MDIOS_SR_PERF                  MDIOS_SR_PERF_Msk                       /*!<  MDIOS slave turnaround error flag*/
+#define MDIOS_SR_SERF_Pos              (1U)
+#define MDIOS_SR_SERF_Msk              (0x1UL << MDIOS_SR_SERF_Pos)            /*!< 0x00000002 */
+#define MDIOS_SR_SERF                  MDIOS_SR_SERF_Msk                       /*!<  MDIOS slave start error flag */
+#define MDIOS_SR_TERF_Pos              (2U)
+#define MDIOS_SR_TERF_Msk              (0x1UL << MDIOS_SR_TERF_Pos)            /*!< 0x00000004 */
+#define MDIOS_SR_TERF                  MDIOS_SR_TERF_Msk                       /*!<  MDIOS slave preamble error flag */
+
+/********************  Bit definition for MDIOS_CLRFR register  *******************/
+#define MDIOS_SR_CPERF_Pos             (0U)
+#define MDIOS_SR_CPERF_Msk             (0x1UL << MDIOS_SR_CPERF_Pos)           /*!< 0x00000001 */
+#define MDIOS_SR_CPERF                 MDIOS_SR_CPERF_Msk                      /*!<  MDIOS slave Clear the turnaround error flag */
+#define MDIOS_SR_CSERF_Pos             (1U)
+#define MDIOS_SR_CSERF_Msk             (0x1UL << MDIOS_SR_CSERF_Pos)           /*!< 0x00000002 */
+#define MDIOS_SR_CSERF                 MDIOS_SR_CSERF_Msk                      /*!<  MDIOS slave Clear the start error flag */
+#define MDIOS_SR_CTERF_Pos             (2U)
+#define MDIOS_SR_CTERF_Msk             (0x1UL << MDIOS_SR_CTERF_Pos)           /*!< 0x00000004 */
+#define MDIOS_SR_CTERF                 MDIOS_SR_CTERF_Msk                      /*!<  MDIOS slave Clear the preamble error flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                       USB_OTG                              */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/
+#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)
+#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)
+#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
+#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */
+#define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)
+#define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */
+#define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)
+#define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
+#define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
+#define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)
+#define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)
+#define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
+#define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)
+#define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)
+#define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */
+#define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)
+#define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)
+#define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)
+#define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)
+#define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
+#define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_EHEN_Pos                 (12U)
+#define USB_OTG_GOTGCTL_EHEN_Msk                 (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
+#define USB_OTG_GOTGCTL_EHEN                     USB_OTG_GOTGCTL_EHEN_Msk      /*!< Embedded host enable */
+#define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)
+#define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
+#define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)
+#define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)
+#define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */
+#define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)
+#define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!< B-session valid */
+#define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)
+#define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
+#define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */
+
+/********************  Bit definition forUSB_OTG_HCFG register  ********************/
+
+#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)
+#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
+#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */
+#define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCFG_FSLSS_Pos                   (2U)
+#define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */
+
+/********************  Bit definition forUSB_OTG_DCFG register  ********************/
+
+#define USB_OTG_DCFG_DSPD_Pos                    (0U)
+#define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
+#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)
+#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD_Pos                     (4U)
+#define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */
+#define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
+
+#define USB_OTG_DCFG_PFIVL_Pos                   (11U)
+#define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
+
+#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)
+#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
+#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
+
+/********************  Bit definition forUSB_OTG_PCGCR register  ********************/
+#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)
+#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)
+#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)
+#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */
+
+/********************  Bit definition forUSB_OTG_GOTGINT register  ********************/
+#define USB_OTG_GOTGINT_SEDET_Pos                (2U)
+#define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */
+#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)
+#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */
+#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)
+#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)
+#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */
+#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)
+#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */
+#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)
+#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */
+
+/********************  Bit definition forUSB_OTG_DCTL register  ********************/
+#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)
+#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS_Pos                    (1U)
+#define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */
+#define USB_OTG_DCTL_GINSTS_Pos                  (2U)
+#define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */
+#define USB_OTG_DCTL_GONSTS_Pos                  (3U)
+#define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
+#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */
+
+#define USB_OTG_DCTL_TCTL_Pos                    (4U)
+#define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
+#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCTL_SGINAK_Pos                  (7U)
+#define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */
+#define USB_OTG_DCTL_CGINAK_Pos                  (8U)
+#define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */
+#define USB_OTG_DCTL_SGONAK_Pos                  (9U)
+#define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */
+#define USB_OTG_DCTL_CGONAK_Pos                  (10U)
+#define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */
+#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)
+#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
+
+/********************  Bit definition forUSB_OTG_HFIR register  ********************/
+#define USB_OTG_HFIR_FRIVL_Pos                   (0U)
+#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */
+
+/********************  Bit definition forUSB_OTG_HFNUM register  ********************/
+#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)
+#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */
+#define USB_OTG_HFNUM_FTREM_Pos                  (16U)
+#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */
+
+/********************  Bit definition forUSB_OTG_DSTS register  ********************/
+#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)
+#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */
+
+#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)
+#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
+#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
+#define USB_OTG_DSTS_EERR_Pos                    (3U)
+#define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
+#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */
+#define USB_OTG_DSTS_FNSOF_Pos                   (8U)
+#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
+#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */
+
+/********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/
+#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)
+#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
+#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */
+
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)
+#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
+#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
+#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
+#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
+#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
+#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)
+#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)
+#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)
+#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
+#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */
+
+/********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)
+#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
+#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
+#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
+#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
+#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)
+#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
+#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)
+#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
+#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)
+#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
+#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */
+
+#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)
+#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
+#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
+#define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
+#define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
+#define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)
+#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)
+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
+#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */
+#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)
+#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
+#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */
+#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)
+#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
+#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */
+#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)
+#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
+#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)
+#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
+#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */
+#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)
+#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
+#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)
+#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
+#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */
+#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)
+#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
+#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */
+#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)
+#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
+#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */
+#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)
+#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */
+
+/********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
+#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)
+#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
+#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */
+#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)
+#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
+#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */
+#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)
+#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
+#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)
+#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
+#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)
+#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
+#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */
+
+#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)
+#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
+#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
+#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
+#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)
+#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
+#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)
+#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
+#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */
+
+/********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/
+#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)
+#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */
+#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)
+#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */
+#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)
+#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
+#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)
+#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */
+#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)
+#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */
+#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)
+#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */
+#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)
+#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */
+
+/********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)
+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */
+
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)
+#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)
+#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
+
+/********************  Bit definition forUSB_OTG_HAINT register  ********************/
+#define USB_OTG_HAINT_HAINT_Pos                  (0U)
+#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */
+
+/********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/
+#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)
+#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)
+#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */
+#define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)
+#define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
+#define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk      /*!< OUT transaction AHB Error interrupt mask               */
+#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)
+#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */
+#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)
+#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)
+#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)
+#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */
+#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)
+#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */
+#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)
+#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */
+#define USB_OTG_DOEPMSK_BERRM_Pos                (12U)
+#define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask               */
+#define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)
+#define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask               */
+#define USB_OTG_DOEPMSK_NYETM_Pos                (14U)
+#define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk      /*!< NYET interrupt mask                */
+
+/********************  Bit definition forUSB_OTG_GINTSTS register  ********************/
+#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)
+#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
+#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */
+#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)
+#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */
+#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)
+#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */
+#define USB_OTG_GINTSTS_SOF_Pos                  (3U)
+#define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */
+#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)
+#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */
+#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)
+#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */
+#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)
+#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */
+#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)
+#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */
+#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)
+#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */
+#define USB_OTG_GINTSTS_USBRST_Pos               (12U)
+#define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */
+#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)
+#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */
+#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)
+#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */
+#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)
+#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */
+#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)
+#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */
+#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)
+#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */
+#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)
+#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)
+#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */
+#define USB_OTG_GINTSTS_RSTDET_Pos               (23U)
+#define USB_OTG_GINTSTS_RSTDET_Msk               (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
+#define USB_OTG_GINTSTS_RSTDET                   USB_OTG_GINTSTS_RSTDET_Msk    /*!< Reset detected interrupt                       */
+#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)
+#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */
+#define USB_OTG_GINTSTS_HCINT_Pos                (25U)
+#define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */
+#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)
+#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */
+#define USB_OTG_GINTSTS_LPMINT_Pos               (27U)
+#define USB_OTG_GINTSTS_LPMINT_Msk               (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt                                  */
+#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)
+#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */
+#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)
+#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */
+#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)
+#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)
+#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */
+
+/********************  Bit definition forUSB_OTG_GINTMSK register  ********************/
+#define USB_OTG_GINTMSK_MMISM_Pos                (1U)
+#define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */
+#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)
+#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */
+#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)
+#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */
+#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)
+#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */
+#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)
+#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)
+#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)
+#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */
+#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)
+#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */
+#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)
+#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */
+#define USB_OTG_GINTMSK_USBRST_Pos               (12U)
+#define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)
+#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */
+#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)
+#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */
+#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)
+#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */
+#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)
+#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
+#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */
+#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)
+#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */
+#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)
+#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)
+#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */
+#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)
+#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */
+#define USB_OTG_GINTMSK_RSTDEM_Pos               (23U)
+#define USB_OTG_GINTMSK_RSTDEM_Msk               (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */
+#define USB_OTG_GINTMSK_RSTDEM                   USB_OTG_GINTMSK_RSTDEM_Msk    /*!< Reset detected interrupt mask                      */
+#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)
+#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */
+#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)
+#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */
+#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)
+#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */
+#define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)
+#define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask                                  */
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)
+#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */
+#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)
+#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */
+#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)
+#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)
+#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */
+
+/********************  Bit definition forUSB_OTG_DAINT register  ********************/
+#define USB_OTG_DAINT_IEPINT_Pos                 (0U)
+#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */
+#define USB_OTG_DAINT_OEPINT_Pos                 (16U)
+#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */
+
+/********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/
+#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)
+#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */
+
+/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
+#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)
+#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */
+#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)
+#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)
+#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)
+#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/
+#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)
+#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)
+#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition for OTG register  ********************/
+
+#define USB_OTG_CHNUM_Pos                        (0U)
+#define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)  /*!< 0x0000000F */
+#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */
+#define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos                         (4U)
+#define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */
+
+#define USB_OTG_DPID_Pos                         (15U)
+#define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)   /*!< 0x00018000 */
+#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */
+#define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */
+#define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */
+
+#define USB_OTG_PKTSTS_Pos                       (17U)
+#define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */
+
+#define USB_OTG_EPNUM_Pos                        (0U)
+#define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)  /*!< 0x0000000F */
+#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */
+
+#define USB_OTG_FRMNUM_Pos                       (21U)
+#define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */
+
+/********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/
+#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)
+#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */
+
+/********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)
+#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */
+
+/********************  Bit definition for OTG register  ********************/
+#define USB_OTG_NPTXFSA_Pos                      (0U)
+#define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD_Pos                       (16U)
+#define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */
+#define USB_OTG_TX0FSA_Pos                       (0U)
+#define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */
+#define USB_OTG_TX0FD_Pos                        (16U)
+#define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */
+
+/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)
+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
+#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
+
+/********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
+#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
+#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)
+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
+#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)
+#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
+#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)
+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
+#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)
+#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
+#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */
+
+/********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/********************  Bit definition forUSB_OTG_DEACHINT register  ********************/
+#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)
+#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */
+#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)
+#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */
+
+/********************  Bit definition forUSB_OTG_GCCFG register  ********************/
+#define USB_OTG_GCCFG_DCDET_Pos                  (0U)
+#define USB_OTG_GCCFG_DCDET_Msk                  (0x1UL << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */
+#define USB_OTG_GCCFG_DCDET                      USB_OTG_GCCFG_DCDET_Msk       /*!< Data contact detection (DCD) status */
+#define USB_OTG_GCCFG_PDET_Pos                   (1U)
+#define USB_OTG_GCCFG_PDET_Msk                   (0x1UL << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_GCCFG_PDET                       USB_OTG_GCCFG_PDET_Msk        /*!< Primary detection (PD) status */
+#define USB_OTG_GCCFG_SDET_Pos                   (2U)
+#define USB_OTG_GCCFG_SDET_Msk                   (0x1UL << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GCCFG_SDET                       USB_OTG_GCCFG_SDET_Msk        /*!< Secondary detection (SD) status */
+#define USB_OTG_GCCFG_PS2DET_Pos                 (3U)
+#define USB_OTG_GCCFG_PS2DET_Msk                 (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */
+#define USB_OTG_GCCFG_PS2DET                     USB_OTG_GCCFG_PS2DET_Msk      /*!< DM pull-up detection status */
+#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)
+#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
+#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */
+#define USB_OTG_GCCFG_BCDEN_Pos                  (17U)
+#define USB_OTG_GCCFG_BCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_GCCFG_BCDEN                      USB_OTG_GCCFG_BCDEN_Msk       /*!< Battery charging detector (BCD) enable */
+#define USB_OTG_GCCFG_DCDEN_Pos                  (18U)
+#define USB_OTG_GCCFG_DCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_GCCFG_DCDEN                      USB_OTG_GCCFG_DCDEN_Msk       /*!< Data contact detection (DCD) mode enable*/
+#define USB_OTG_GCCFG_PDEN_Pos                   (19U)
+#define USB_OTG_GCCFG_PDEN_Msk                   (0x1UL << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_GCCFG_PDEN                       USB_OTG_GCCFG_PDEN_Msk        /*!< Primary detection (PD) mode enable*/
+#define USB_OTG_GCCFG_SDEN_Pos                   (20U)
+#define USB_OTG_GCCFG_SDEN_Msk                   (0x1UL << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_GCCFG_SDEN                       USB_OTG_GCCFG_SDEN_Msk        /*!< Secondary detection (SD) mode enable */
+#define USB_OTG_GCCFG_VBDEN_Pos                  (21U)
+#define USB_OTG_GCCFG_VBDEN_Msk                  (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk       /*!< Secondary detection (SD) mode enable */
+
+/********************  Bit definition forUSB_OTG_GPWRDN) register  ********************/
+#define USB_OTG_GPWRDN_ADPMEN_Pos                (0U)
+#define USB_OTG_GPWRDN_ADPMEN_Msk                (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */
+#define USB_OTG_GPWRDN_ADPMEN                    USB_OTG_GPWRDN_ADPMEN_Msk     /*!< ADP module enable */
+#define USB_OTG_GPWRDN_ADPIF_Pos                 (23U)
+#define USB_OTG_GPWRDN_ADPIF_Msk                 (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */
+#define USB_OTG_GPWRDN_ADPIF                     USB_OTG_GPWRDN_ADPIF_Msk      /*!< ADP Interrupt flag */
+
+/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
+
+/********************  Bit definition forUSB_OTG_CID register  ********************/
+#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)
+#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */
+
+/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/
+#define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)
+#define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
+#define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /*!< LPM support enable                                     */
+#define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)
+#define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
+#define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /*!< LPM Token acknowledge enable                           */
+#define USB_OTG_GLPMCFG_BESL_Pos                 (2U)
+#define USB_OTG_GLPMCFG_BESL_Msk                 (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
+#define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /*!< BESL value received with last ACKed LPM Token          */
+#define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)
+#define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
+#define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /*!< bRemoteWake value received with last ACKed LPM Token   */
+#define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)
+#define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /*!< L1 shallow sleep enable                                */
+#define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)
+#define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
+#define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /*!< BESL threshold                                         */
+#define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)
+#define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
+#define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /*!< L1 deep sleep enable                                   */
+#define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)
+#define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
+#define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /*!< LPM response                                           */
+#define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)
+#define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /*!< Port sleep status                                      */
+#define USB_OTG_GLPMCFG_L1RSMOK_Pos              (16U)
+#define USB_OTG_GLPMCFG_L1RSMOK_Msk              (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
+#define USB_OTG_GLPMCFG_L1RSMOK                  USB_OTG_GLPMCFG_L1RSMOK_Msk   /*!< Sleep State Resume OK                                  */
+#define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)
+#define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /*!< LPM Channel Index                                      */
+#define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)
+#define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
+#define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /*!< LPM retry count                                        */
+#define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)
+#define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /*!< Send LPM transaction                                   */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status                                 */
+#define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)
+#define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
+#define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /*!< Enable best effort service latency                     */
+
+/********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)
+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)
+#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)
+#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)
+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+
+/********************  Bit definition forUSB_OTG_HPRT register  ********************/
+#define USB_OTG_HPRT_PCSTS_Pos                   (0U)
+#define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */
+#define USB_OTG_HPRT_PCDET_Pos                   (1U)
+#define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */
+#define USB_OTG_HPRT_PENA_Pos                    (2U)
+#define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
+#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */
+#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)
+#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
+#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA_Pos                    (4U)
+#define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
+#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */
+#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)
+#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
+#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */
+#define USB_OTG_HPRT_PRES_Pos                    (6U)
+#define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
+#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume   */
+#define USB_OTG_HPRT_PSUSP_Pos                   (7U)
+#define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
+#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend  */
+#define USB_OTG_HPRT_PRST_Pos                    (8U)
+#define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
+#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset    */
+
+#define USB_OTG_HPRT_PLSTS_Pos                   (10U)
+#define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
+#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
+#define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_HPRT_PPWR_Pos                    (12U)
+#define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL_Pos                   (13U)
+#define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
+#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
+#define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
+#define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
+#define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_HPRT_PSPD_Pos                    (17U)
+#define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
+#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
+
+/********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)
+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)
+#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)
+#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)
+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)
+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)
+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
+
+/********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)
+#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)
+#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth */
+
+/********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/
+#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)
+#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)
+#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)
+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)
+#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)
+#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DIEPCTL_STALL_Pos                (21U)
+#define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)
+#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
+#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
+#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
+#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)
+#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)
+#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)
+#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)
+#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)
+#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable */
+
+/********************  Bit definition forUSB_OTG_HCCHAR register  ********************/
+#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)
+#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)
+#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
+#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
+#define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)
+#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)
+#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)
+#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
+
+#define USB_OTG_HCCHAR_MC_Pos                    (20U)
+#define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
+#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
+#define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
+
+#define USB_OTG_HCCHAR_DAD_Pos                   (22U)
+#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
+#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
+#define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
+#define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
+#define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
+#define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
+#define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
+#define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
+#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)
+#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)
+#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)
+#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */
+
+/********************  Bit definition forUSB_OTG_HCSPLT register  ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)
+#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
+#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
+
+#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)
+#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
+#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
+
+#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)
+#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
+#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)
+#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
+#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)
+#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */
+
+/********************  Bit definition forUSB_OTG_HCINT register  ********************/
+#define USB_OTG_HCINT_XFRC_Pos                   (0U)
+#define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH_Pos                    (1U)
+#define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR_Pos                 (2U)
+#define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */
+#define USB_OTG_HCINT_STALL_Pos                  (3U)
+#define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK_Pos                    (4U)
+#define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK_Pos                    (5U)
+#define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET_Pos                   (6U)
+#define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR_Pos                  (7U)
+#define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR_Pos                  (8U)
+#define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR_Pos                  (9U)
+#define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR_Pos                  (10U)
+#define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */
+
+/********************  Bit definition forUSB_OTG_DIEPINT register  ********************/
+#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)
+#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)
+#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_AHBERR_Pos               (2U)
+#define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */
+#define USB_OTG_DIEPINT_TOC_Pos                  (3U)
+#define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)
+#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNM_Pos               (5U)
+#define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */
+#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)
+#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)
+#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
+#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA_Pos                  (9U)
+#define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)
+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR_Pos                 (12U)
+#define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK_Pos                  (13U)
+#define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */
+
+/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/
+#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)
+#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)
+#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)
+#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)
+#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)
+#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)
+#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET_Pos                (6U)
+#define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)
+#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)
+#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)
+#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)
+#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */
+
+/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)
+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)
+#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */
+/********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)
+#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)
+#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)
+#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)
+#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
+#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/
+#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)
+#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */
+
+/********************  Bit definition forUSB_OTG_HCDMA register  ********************/
+#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)
+#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */
+
+/********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)
+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
+
+/********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)
+#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)
+#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */
+
+/********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)
+#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)
+#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)
+#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)
+#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)
+#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)
+#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
+#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL_Pos                (21U)
+#define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)
+#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)
+#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)
+#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)
+#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */
+
+/********************  Bit definition forUSB_OTG_DOEPINT register  ********************/
+#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)
+#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)
+#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_AHBERR_Pos               (2U)
+#define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */
+#define USB_OTG_DOEPINT_STUP_Pos                 (3U)
+#define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)
+#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)
+#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< OUT Status Phase Received interrupt */
+#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)
+#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)
+#define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */
+#define USB_OTG_DOEPINT_BERR_Pos                 (12U)
+#define USB_OTG_DOEPINT_BERR_Msk                 (0x1UL << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPINT_BERR                      USB_OTG_DOEPINT_BERR_Msk   /*!< Babble error interrupt */
+#define USB_OTG_DOEPINT_NAK_Pos                  (13U)
+#define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */
+#define USB_OTG_DOEPINT_NYET_Pos                 (14U)
+#define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */
+#define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)
+#define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */
+
+/********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)
+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for PCGCCTL register  ********************/
+#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)
+#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)
+#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)
+#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+                                       ((INSTANCE) == ADC2) || \
+                                       ((INSTANCE) == ADC3))
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON) ||\
+                                          ((INSTANCE) == ADC3_COMMON))
+
+/******************************** COMP Instances ******************************/
+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
+                                       ((INSTANCE) == COMP2))
+
+#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
+/******************** COMP Instances with window mode capability **************/
+#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
+
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
+/******************************* DCMI Instances *******************************/
+#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
+
+/******************************* DELAYBLOCK Instances *******************************/
+#define IS_DLYB_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DLYB_SDMMC1) || \
+                                         ((INSTANCE) == DLYB_SDMMC2) || \
+                                         ((INSTANCE) == DLYB_QUADSPI))
+/****************************** DFSDM Instances *******************************/
+#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
+                                               ((INSTANCE) == DFSDM1_Filter1) || \
+                                               ((INSTANCE) == DFSDM1_Filter2) || \
+                                               ((INSTANCE) == DFSDM1_Filter3))
+
+#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
+                                                 ((INSTANCE) == DFSDM1_Channel1) || \
+                                                 ((INSTANCE) == DFSDM1_Channel2) || \
+                                                 ((INSTANCE) == DFSDM1_Channel3) || \
+                                                 ((INSTANCE) == DFSDM1_Channel4) || \
+                                                 ((INSTANCE) == DFSDM1_Channel5) || \
+                                                 ((INSTANCE) == DFSDM1_Channel6) || \
+                                                 ((INSTANCE) == DFSDM1_Channel7))
+/****************************** RAMECC Instances ******************************/
+#define IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMECC1_Monitor1)   || \
+                                                  ((INSTANCE) == RAMECC1_Monitor2)   || \
+                                                  ((INSTANCE) == RAMECC1_Monitor3)   || \
+                                                  ((INSTANCE) == RAMECC1_Monitor4)   || \
+                                                  ((INSTANCE) == RAMECC1_Monitor5)   || \
+                                                  ((INSTANCE) == RAMECC2_Monitor1)   || \
+                                                  ((INSTANCE) == RAMECC2_Monitor2)   || \
+                                                  ((INSTANCE) == RAMECC2_Monitor3)   || \
+                                                  ((INSTANCE) == RAMECC2_Monitor4)   || \
+                                                  ((INSTANCE) == RAMECC2_Monitor5)   || \
+                                                  ((INSTANCE) == RAMECC3_Monitor1)   || \
+                                                  ((INSTANCE) == RAMECC3_Monitor2))
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \
+                                       ((INSTANCE) == DMA1_Stream1)   || \
+                                       ((INSTANCE) == DMA1_Stream2)   || \
+                                       ((INSTANCE) == DMA1_Stream3)   || \
+                                       ((INSTANCE) == DMA1_Stream4)   || \
+                                       ((INSTANCE) == DMA1_Stream5)   || \
+                                       ((INSTANCE) == DMA1_Stream6)   || \
+                                       ((INSTANCE) == DMA1_Stream7)   || \
+                                       ((INSTANCE) == DMA2_Stream0)   || \
+                                       ((INSTANCE) == DMA2_Stream1)   || \
+                                       ((INSTANCE) == DMA2_Stream2)   || \
+                                       ((INSTANCE) == DMA2_Stream3)   || \
+                                       ((INSTANCE) == DMA2_Stream4)   || \
+                                       ((INSTANCE) == DMA2_Stream5)   || \
+                                       ((INSTANCE) == DMA2_Stream6)   || \
+                                       ((INSTANCE) == DMA2_Stream7)   || \
+                                       ((INSTANCE) == BDMA_Channel0) || \
+                                       ((INSTANCE) == BDMA_Channel1) || \
+                                       ((INSTANCE) == BDMA_Channel2) || \
+                                       ((INSTANCE) == BDMA_Channel3) || \
+                                       ((INSTANCE) == BDMA_Channel4) || \
+                                       ((INSTANCE) == BDMA_Channel5) || \
+                                       ((INSTANCE) == BDMA_Channel6) || \
+                                       ((INSTANCE) == BDMA_Channel7))
+
+/****************************** BDMA CHANNEL Instances ***************************/
+#define IS_BDMA_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == BDMA_Channel0) || \
+                                            ((INSTANCE) == BDMA_Channel1) || \
+                                            ((INSTANCE) == BDMA_Channel2) || \
+                                            ((INSTANCE) == BDMA_Channel3) || \
+                                            ((INSTANCE) == BDMA_Channel4) || \
+                                            ((INSTANCE) == BDMA_Channel5) || \
+                                            ((INSTANCE) == BDMA_Channel6) || \
+                                            ((INSTANCE) == BDMA_Channel7))
+
+/****************************** DMA DMAMUX ALL Instances ***************************/
+#define IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)    || \
+                                               ((INSTANCE) == DMA1_Stream1)    || \
+                                               ((INSTANCE) == DMA1_Stream2)    || \
+                                               ((INSTANCE) == DMA1_Stream3)    || \
+                                               ((INSTANCE) == DMA1_Stream4)    || \
+                                               ((INSTANCE) == DMA1_Stream5)    || \
+                                               ((INSTANCE) == DMA1_Stream6)    || \
+                                               ((INSTANCE) == DMA1_Stream7)    || \
+                                               ((INSTANCE) == DMA2_Stream0)    || \
+                                               ((INSTANCE) == DMA2_Stream1)    || \
+                                               ((INSTANCE) == DMA2_Stream2)    || \
+                                               ((INSTANCE) == DMA2_Stream3)    || \
+                                               ((INSTANCE) == DMA2_Stream4)    || \
+                                               ((INSTANCE) == DMA2_Stream5)    || \
+                                               ((INSTANCE) == DMA2_Stream6)    || \
+                                               ((INSTANCE) == DMA2_Stream7)    || \
+                                               ((INSTANCE) == BDMA_Channel0)   || \
+                                               ((INSTANCE) == BDMA_Channel1)   || \
+                                               ((INSTANCE) == BDMA_Channel2)   || \
+                                               ((INSTANCE) == BDMA_Channel3)   || \
+                                               ((INSTANCE) == BDMA_Channel4)   || \
+                                               ((INSTANCE) == BDMA_Channel5)   || \
+                                               ((INSTANCE) == BDMA_Channel6)   || \
+                                               ((INSTANCE) == BDMA_Channel7))
+
+/****************************** BDMA DMAMUX Instances ***************************/
+#define IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == BDMA_Channel0) || \
+                                                    ((INSTANCE) == BDMA_Channel1) || \
+                                                    ((INSTANCE) == BDMA_Channel2) || \
+                                                    ((INSTANCE) == BDMA_Channel3) || \
+                                                    ((INSTANCE) == BDMA_Channel4) || \
+                                                    ((INSTANCE) == BDMA_Channel5) || \
+                                                    ((INSTANCE) == BDMA_Channel6) || \
+                                                    ((INSTANCE) == BDMA_Channel7))
+
+/****************************** DMA STREAM Instances ***************************/
+#define IS_DMA_STREAM_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \
+                                          ((INSTANCE) == DMA1_Stream1)   || \
+                                          ((INSTANCE) == DMA1_Stream2)   || \
+                                          ((INSTANCE) == DMA1_Stream3)   || \
+                                          ((INSTANCE) == DMA1_Stream4)   || \
+                                          ((INSTANCE) == DMA1_Stream5)   || \
+                                          ((INSTANCE) == DMA1_Stream6)   || \
+                                          ((INSTANCE) == DMA1_Stream7)   || \
+                                          ((INSTANCE) == DMA2_Stream0)   || \
+                                          ((INSTANCE) == DMA2_Stream1)   || \
+                                          ((INSTANCE) == DMA2_Stream2)   || \
+                                          ((INSTANCE) == DMA2_Stream3)   || \
+                                          ((INSTANCE) == DMA2_Stream4)   || \
+                                          ((INSTANCE) == DMA2_Stream5)   || \
+                                          ((INSTANCE) == DMA2_Stream6)   || \
+                                          ((INSTANCE) == DMA2_Stream7))
+
+/****************************** DMA DMAMUX Instances ***************************/
+#define IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)   || \
+                                                  ((INSTANCE) == DMA1_Stream1)   || \
+                                                  ((INSTANCE) == DMA1_Stream2)   || \
+                                                  ((INSTANCE) == DMA1_Stream3)   || \
+                                                  ((INSTANCE) == DMA1_Stream4)   || \
+                                                  ((INSTANCE) == DMA1_Stream5)   || \
+                                                  ((INSTANCE) == DMA1_Stream6)   || \
+                                                  ((INSTANCE) == DMA1_Stream7)   || \
+                                                  ((INSTANCE) == DMA2_Stream0)   || \
+                                                  ((INSTANCE) == DMA2_Stream1)   || \
+                                                  ((INSTANCE) == DMA2_Stream2)   || \
+                                                  ((INSTANCE) == DMA2_Stream3)   || \
+                                                  ((INSTANCE) == DMA2_Stream4)   || \
+                                                  ((INSTANCE) == DMA2_Stream5)   || \
+                                                  ((INSTANCE) == DMA2_Stream6)   || \
+                                                  ((INSTANCE) == DMA2_Stream7))
+
+/******************************** DMA Request Generator Instances **************/
+#define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator1) || \
+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator2) || \
+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator3) || \
+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator4) || \
+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator5) || \
+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator6) || \
+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator7) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator0) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator1) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator2) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator3) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator4) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator5) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator6) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator7))
+
+/******************************* DMA2D Instances *******************************/
+#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
+
+/******************************** MDMA Request Generator Instances **************/
+#define IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDMA_Channel0)  || \
+                                               ((INSTANCE) == MDMA_Channel1)  || \
+                                               ((INSTANCE) == MDMA_Channel2)  || \
+                                               ((INSTANCE) == MDMA_Channel3)  || \
+                                               ((INSTANCE) == MDMA_Channel4)  || \
+                                               ((INSTANCE) == MDMA_Channel5)  || \
+                                               ((INSTANCE) == MDMA_Channel6)  || \
+                                               ((INSTANCE) == MDMA_Channel7)  || \
+                                               ((INSTANCE) == MDMA_Channel8)  || \
+                                               ((INSTANCE) == MDMA_Channel9)  || \
+                                               ((INSTANCE) == MDMA_Channel10) || \
+                                               ((INSTANCE) == MDMA_Channel11) || \
+                                               ((INSTANCE) == MDMA_Channel12) || \
+                                               ((INSTANCE) == MDMA_Channel13) || \
+                                               ((INSTANCE) == MDMA_Channel14) || \
+                                               ((INSTANCE) == MDMA_Channel15))
+
+/******************************* QUADSPI Instances *******************************/
+#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
+
+/******************************* FDCAN Instances ******************************/
+#define IS_FDCAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == FDCAN1) || \
+                                             ((__INSTANCE__) == FDCAN2))
+
+#define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1)
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+                                        ((INSTANCE) == GPIOB) || \
+                                        ((INSTANCE) == GPIOC) || \
+                                        ((INSTANCE) == GPIOD) || \
+                                        ((INSTANCE) == GPIOE) || \
+                                        ((INSTANCE) == GPIOF) || \
+                                        ((INSTANCE) == GPIOG) || \
+                                        ((INSTANCE) == GPIOH) || \
+                                        ((INSTANCE) == GPIOI) || \
+                                        ((INSTANCE) == GPIOJ) || \
+                                        ((INSTANCE) == GPIOK))
+
+/******************************* GPIO AF Instances ****************************/
+#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/**************************** GPIO Lock Instances *****************************/
+/* On H7, all GPIO Bank support the Lock mechanism */
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/******************************** HSEM Instances *******************************/
+#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)
+#define HSEM_CPU1_COREID         (0x00000003U) /* Semaphore Core CM7 ID */
+#define HSEM_CR_COREID_CPU1      (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
+#define HSEM_CR_COREID_CURRENT   (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
+
+#define HSEM_SEMID_MIN     (0U)       /* HSEM ID Min*/
+#define HSEM_SEMID_MAX     (31U)      /* HSEM ID Max */
+
+#define HSEM_PROCESSID_MIN (0U)       /* HSEM Process ID Min */
+#define HSEM_PROCESSID_MAX (255U)     /* HSEM Process ID Max */
+
+#define HSEM_CLEAR_KEY_MIN (0U)       /* HSEM clear Key Min value */
+#define HSEM_CLEAR_KEY_MAX (0xFFFFU)  /* HSEM clear Key Max value */
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+                                       ((INSTANCE) == I2C2) || \
+                                       ((INSTANCE) == I2C3) || \
+                                       ((INSTANCE) == I2C4))
+/************** I2C Instances : wakeup capability from stop modes *************/
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
+
+/****************************** SMBUS Instances *******************************/
+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+                                         ((INSTANCE) == I2C2) || \
+                                         ((INSTANCE) == I2C3) || \
+                                         ((INSTANCE) == I2C4))
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE)   (((INSTANCE) == SPI1) || \
+                                         ((INSTANCE) == SPI2) || \
+                                         ((INSTANCE) == SPI3))
+
+/****************************** LTDC Instances ********************************/
+#define IS_LTDC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == LTDC)
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
+
+/****************************** SDMMC Instances *********************************/
+#define IS_SDMMC_ALL_INSTANCE(_INSTANCE_) (((_INSTANCE_) == SDMMC1) || \
+                                           ((_INSTANCE_) == SDMMC2))
+
+/******************************** SMBUS Instances *****************************/
+#define IS_SMBUS_INSTANCE(INSTANCE)  ((INSTANCE) == I2C1)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+                                       ((INSTANCE) == SPI2) || \
+                                       ((INSTANCE) == SPI3) || \
+                                       ((INSTANCE) == SPI4) || \
+                                       ((INSTANCE) == SPI5) || \
+                                       ((INSTANCE) == SPI6))
+
+#define IS_SPI_HIGHEND_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+                                           ((INSTANCE) == SPI2) || \
+                                           ((INSTANCE) == SPI3))
+
+/******************************** SWPMI Instances *****************************/
+#define IS_SWPMI_INSTANCE(INSTANCE)  ((INSTANCE) == SWPMI1)
+
+/****************** LPTIM Instances : All supported instances *****************/
+#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \
+                                         ((INSTANCE) == LPTIM2) || \
+                                         ((INSTANCE) == LPTIM3) || \
+                                         ((INSTANCE) == LPTIM4) || \
+                                         ((INSTANCE) == LPTIM5))
+
+/****************** LPTIM Instances : supporting encoder interface **************/
+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \
+                                                           ((INSTANCE) == LPTIM2))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM6)   || \
+                                         ((INSTANCE) == TIM7)   || \
+                                         ((INSTANCE) == TIM8)   || \
+                                         ((INSTANCE) == TIM12)  || \
+                                         ((INSTANCE) == TIM13)  || \
+                                         ((INSTANCE) == TIM14)  || \
+                                         ((INSTANCE) == TIM15)  || \
+                                         ((INSTANCE) == TIM16)  || \
+                                         ((INSTANCE) == TIM17))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8)   || \
+                                         ((INSTANCE) == TIM12)  || \
+                                         ((INSTANCE) == TIM13)  || \
+                                         ((INSTANCE) == TIM14)  || \
+                                         ((INSTANCE) == TIM15)  || \
+                                         ((INSTANCE) == TIM16)  || \
+                                         ((INSTANCE) == TIM17))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8)   || \
+                                         ((INSTANCE) == TIM12)  || \
+                                         ((INSTANCE) == TIM15))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 5 capture/compare channels *************/
+#define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM8))
+/************ TIM Instances : at least 6 capture/compare channels *************/
+#define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
+                                                ((__INSTANCE__) == TIM8))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8)   || \
+                                         ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \
+                                           ((INSTANCE) == TIM2)   || \
+                                           ((INSTANCE) == TIM3)   || \
+                                           ((INSTANCE) == TIM4)   || \
+                                           ((INSTANCE) == TIM5)   || \
+                                           ((INSTANCE) == TIM6)   || \
+                                           ((INSTANCE) == TIM7)   || \
+                                           ((INSTANCE) == TIM8)   || \
+                                           ((INSTANCE) == TIM15)  || \
+                                           ((INSTANCE) == TIM16)  || \
+                                           ((INSTANCE) == TIM17))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM5)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15)  || \
+                                            ((INSTANCE) == TIM16)  || \
+                                            ((INSTANCE) == TIM17))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM5)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM5)   || \
+                                            ((INSTANCE) == TIM8))
+
+/*************** TIM Instances : external trigger reamp input available *******/
+#define IS_TIM_ETR_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \
+                                           ((INSTANCE) == TIM2)   || \
+                                           ((INSTANCE) == TIM3)   || \
+                                           ((INSTANCE) == TIM4)   || \
+                                           ((INSTANCE) == TIM5)   || \
+                                           ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
+                                          ((INSTANCE) == TIM2)  || \
+                                          ((INSTANCE) == TIM3)  || \
+                                          ((INSTANCE) == TIM5)  || \
+                                          ((INSTANCE) == TIM8)  || \
+                                          ((INSTANCE) == TIM16) || \
+                                          ((INSTANCE) == TIM17))
+
+/*************** TIM Instances : external trigger reamp input available *******/
+#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \
+                                              ((INSTANCE) == TIM2)   || \
+                                              ((INSTANCE) == TIM3)   || \
+                                              ((INSTANCE) == TIM5)   || \
+                                              ((INSTANCE) == TIM8))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM5)   || \
+                                            ((INSTANCE) == TIM6)   || \
+                                            ((INSTANCE) == TIM7)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15))
+
+/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                           ((INSTANCE) == TIM2)   || \
+                                           ((INSTANCE) == TIM3)   || \
+                                           ((INSTANCE) == TIM4)   || \
+                                           ((INSTANCE) == TIM5)   || \
+                                           ((INSTANCE) == TIM8)   || \
+                                           ((INSTANCE) == TIM12))
+
+/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
+#define IS_TIM_TRGO2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                           ((INSTANCE) == TIM8))
+
+/****** TIM Instances : TISEL available (TIMx_TISEL available )*********/
+#define IS_TIM_TISEL_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)   || \
+                                          ((INSTANCE) == TIM2)   || \
+                                          ((INSTANCE) == TIM3)   || \
+                                          ((INSTANCE) == TIM4)   || \
+                                          ((INSTANCE) == TIM5)   || \
+                                          ((INSTANCE) == TIM8)   || \
+                                          ((INSTANCE) == TIM15)  || \
+                                          ((INSTANCE) == TIM16)  || \
+                                          ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting commutation event *************/
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)    || \
+                                                     ((INSTANCE) == TIM8)    || \
+                                                     ((INSTANCE) == TIM15)   || \
+                                                     ((INSTANCE) == TIM16)   || \
+                                                     ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1)  || \
+                                                      ((__INSTANCE__) == TIM2)      || \
+                                                      ((__INSTANCE__) == TIM3)      || \
+                                                      ((__INSTANCE__) == TIM4)      || \
+                                                      ((__INSTANCE__) == TIM5)      || \
+                                                      ((__INSTANCE__) == TIM8))
+
+/****** TIM Instances : TIM_CCR5_GC5C available (TIMx_CCR5.GC5C available )*********/
+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                                       ((INSTANCE) == TIM8))
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+    ((((INSTANCE) == TIM1) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4) ||          \
+      ((CHANNEL) == TIM_CHANNEL_5) ||          \
+      ((CHANNEL) == TIM_CHANNEL_6)))           \
+     ||                                        \
+     (((INSTANCE) == TIM2) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+  ||                                           \
+      (((INSTANCE) == TIM3) &&                 \
+      (((CHANNEL) == TIM_CHANNEL_1)||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+  ||                                           \
+      (((INSTANCE) == TIM4) &&                 \
+      (((CHANNEL) == TIM_CHANNEL_1) ||         \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+  ||                                           \
+      (((INSTANCE) == TIM5) &&                 \
+      (((CHANNEL) == TIM_CHANNEL_1) ||         \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+  ||                                           \
+      (((INSTANCE) == TIM8) &&                 \
+      (((CHANNEL) == TIM_CHANNEL_1) ||         \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4) ||          \
+      ((CHANNEL) == TIM_CHANNEL_5) ||          \
+      ((CHANNEL) == TIM_CHANNEL_6)))           \
+  ||                                           \
+     (((INSTANCE) == TIM12) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2)))           \
+  ||                                           \
+     (((INSTANCE) == TIM13) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+  ||                                           \
+     (((INSTANCE) == TIM14) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+  ||                                           \
+     (((INSTANCE) == TIM15) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+     ((CHANNEL) == TIM_CHANNEL_2)))            \
+  ||                                           \
+     (((INSTANCE) == TIM16) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+  ||                                           \
+     (((INSTANCE) == TIM17) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1))))
+
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
+      (((INSTANCE) == TIM1)    || \
+      ((INSTANCE) == TIM8)     || \
+       ((INSTANCE) == TIM15)   || \
+       ((INSTANCE) == TIM16)   || \
+       ((INSTANCE) == TIM17))
+
+/************** TIM Instances : supporting Break source selection *************/
+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                               ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting complementary output(s) ********/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+   ((((INSTANCE) == TIM1) &&                    \
+     (((CHANNEL) == TIM_CHANNEL_1) ||           \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3)))            \
+ ||                                             \
+      (((INSTANCE) == TIM8) &&                  \
+      (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3)))            \
+    ||                                          \
+    (((INSTANCE) == TIM15) &&                   \
+      ((CHANNEL) == TIM_CHANNEL_1))             \
+    ||                                          \
+    (((INSTANCE) == TIM16) &&                   \
+     ((CHANNEL) == TIM_CHANNEL_1))              \
+    ||                                          \
+    (((INSTANCE) == TIM17) &&                   \
+     ((CHANNEL) == TIM_CHANNEL_1)))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM5)    || \
+   ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM15)   || \
+   ((INSTANCE) == TIM16)   || \
+   ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting synchronization ****************/
+#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
+    (((__INSTANCE__) == TIM1)    || \
+     ((__INSTANCE__) == TIM2)    || \
+     ((__INSTANCE__) == TIM3)    || \
+     ((__INSTANCE__) == TIM4)    || \
+     ((__INSTANCE__) == TIM5)    || \
+     ((__INSTANCE__) == TIM6)    || \
+     ((__INSTANCE__) == TIM8)    || \
+     ((__INSTANCE__) == TIM12)   || \
+     ((__INSTANCE__) == TIM15))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM5)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM15)   || \
+   ((INSTANCE) == TIM16)   || \
+   ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting external clock mode 1 for ETRF input */
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM5)    || \
+   ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting external clock mode 2 **********/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1)     || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM5)    || \
+   ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM5)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM5)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3))
+
+/****************** TIM Instances : TIM_32B_COUNTER ***************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : TIM_BKIN2 ***************************/
+#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting Hall sensor interface **********/
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1)  || \
+                                                             ((__INSTANCE__) == TIM2)  || \
+                                                             ((__INSTANCE__) == TIM3)  || \
+                                                             ((__INSTANCE__) == TIM4)  || \
+                                                             ((__INSTANCE__) == TIM5)  || \
+                                                             ((__INSTANCE__) == TIM15) || \
+                                                             ((__INSTANCE__) == TIM8))
+
+/****************************** HRTIM Instances *******************************/
+#define IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                     ((INSTANCE) == USART2) || \
+                                     ((INSTANCE) == USART3) || \
+                                     ((INSTANCE) == USART6))
+
+/******************** USART Instances : SPI slave mode ************************/
+#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                              ((INSTANCE) == USART2) || \
+                                              ((INSTANCE) == USART3) || \
+                                              ((INSTANCE) == USART6))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                    ((INSTANCE) == USART2) || \
+                                    ((INSTANCE) == USART3) || \
+                                    ((INSTANCE) == UART4)  || \
+                                    ((INSTANCE) == UART5)  || \
+                                    ((INSTANCE) == USART6) || \
+                                    ((INSTANCE) == UART7)  || \
+                                    ((INSTANCE) == UART8))
+
+/******************** UART Instances : FIFO mode.******************************/
+#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                         ((INSTANCE) == USART2) || \
+                                         ((INSTANCE) == USART3) || \
+                                         ((INSTANCE) == UART4)  || \
+                                         ((INSTANCE) == UART5)  || \
+                                         ((INSTANCE) == USART6) || \
+                                         ((INSTANCE) == UART7)  || \
+                                         ((INSTANCE) == UART8))
+
+/****************** UART Instances : Auto Baud Rate detection *****************/
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                                            ((INSTANCE) == USART2) || \
+                                                            ((INSTANCE) == USART3) || \
+                                                            ((INSTANCE) == UART4)  || \
+                                                            ((INSTANCE) == UART5)  || \
+                                                            ((INSTANCE) == USART6) || \
+                                                            ((INSTANCE) == UART7)  || \
+                                                            ((INSTANCE) == UART8))
+
+/*********************** UART Instances : Driver Enable ***********************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                                  ((INSTANCE) == USART2) || \
+                                                  ((INSTANCE) == USART3) || \
+                                                  ((INSTANCE) == UART4)  || \
+                                                  ((INSTANCE) == UART5)  || \
+                                                  ((INSTANCE) == USART6) || \
+                                                  ((INSTANCE) == UART7)  || \
+                                                  ((INSTANCE) == UART8)  || \
+                                                  ((INSTANCE) == LPUART1))
+
+/********************* UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                               ((INSTANCE) == USART2) || \
+                                               ((INSTANCE) == USART3) || \
+                                               ((INSTANCE) == UART4)  || \
+                                               ((INSTANCE) == UART5)  || \
+                                               ((INSTANCE) == USART6) || \
+                                               ((INSTANCE) == UART7)  || \
+                                               ((INSTANCE) == UART8)  || \
+                                               ((INSTANCE) == LPUART1))
+
+/******************* UART Instances : Hardware Flow control *******************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                           ((INSTANCE) == USART2) || \
+                                           ((INSTANCE) == USART3) || \
+                                           ((INSTANCE) == UART4)  || \
+                                           ((INSTANCE) == UART5)  || \
+                                           ((INSTANCE) == USART6) || \
+                                           ((INSTANCE) == UART7)  || \
+                                           ((INSTANCE) == UART8)  || \
+                                           ((INSTANCE) == LPUART1))
+
+/************************* UART Instances : LIN mode **************************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                        ((INSTANCE) == USART2) || \
+                                        ((INSTANCE) == USART3) || \
+                                        ((INSTANCE) == UART4)  || \
+                                        ((INSTANCE) == UART5)  || \
+                                        ((INSTANCE) == USART6) || \
+                                        ((INSTANCE) == UART7)  || \
+                                        ((INSTANCE) == UART8))
+
+/****************** UART Instances : Wake-up from Stop mode *******************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                                    ((INSTANCE) == USART2) || \
+                                                    ((INSTANCE) == USART3) || \
+                                                    ((INSTANCE) == UART4)  || \
+                                                    ((INSTANCE) == UART5)  || \
+                                                    ((INSTANCE) == USART6) || \
+                                                    ((INSTANCE) == UART7)  || \
+                                                    ((INSTANCE) == UART8)  || \
+                                                    ((INSTANCE) == LPUART1))
+
+/************************* UART Instances : IRDA mode *************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                    ((INSTANCE) == USART2) || \
+                                    ((INSTANCE) == USART3) || \
+                                    ((INSTANCE) == UART4)  || \
+                                    ((INSTANCE) == UART5)  || \
+                                    ((INSTANCE) == USART6) || \
+                                    ((INSTANCE) == UART7)  || \
+                                    ((INSTANCE) == UART8))
+
+/********************* USART Instances : Smard card mode **********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                         ((INSTANCE) == USART2) || \
+                                         ((INSTANCE) == USART3) || \
+                                         ((INSTANCE) == USART6))
+
+/****************************** LPUART Instance *******************************/
+#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG1)
+/****************************** USB Instances ********************************/
+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG1)
+/****************************** MDIOS Instances ********************************/
+#define IS_MDIOS_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == MDIOS)
+
+/****************************** CEC Instances *********************************/
+#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
+
+/****************************** SAI Instances ********************************/
+#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
+                    ((INSTANCE) == SAI1_Block_B) || \
+                     ((INSTANCE) == SAI2_Block_A) || \
+                     ((INSTANCE) == SAI2_Block_B) || \
+                     ((INSTANCE) == SAI3_Block_A) || \
+                     ((INSTANCE) == SAI3_Block_B) || \
+                     ((INSTANCE) == SAI4_Block_A) || \
+                     ((INSTANCE) == SAI4_Block_B))
+
+/****************************** SPDIFRX Instances ********************************/
+#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)
+
+/****************************** OPAMP Instances *******************************/
+#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
+                                         ((INSTANCE) == OPAMP2))
+
+#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
+
+/*********************** USB OTG PCD Instances ********************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+                                        ((INSTANCE) == USB_OTG_HS))
+
+/*********************** USB OTG HCD Instances ********************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+                                       ((INSTANCE) == USB_OTG_HS))
+
+/******************************************************************************/
+/*  For a painless codes migration between the STM32H7xx device product       */
+/*  lines, or with STM32F7xx devices the aliases defined below are put        */
+/*   in place to overcome the differences in the interrupt handlers and IRQn  */
+/*   definitions. No need to update developed interrupt code when moving      */
+/*  across product lines within the same STM32H7 Family                       */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define  HASH_RNG_IRQn                  RNG_IRQn
+#define  TIM1_BRK_TIM9_IRQn             TIM1_BRK_IRQn
+#define  TIM1_UP_TIM10_IRQn             TIM1_UP_IRQn
+#define  TIM1_TRG_COM_TIM11_IRQn        TIM1_TRG_COM_IRQn
+#define  PVD_IRQn                       PVD_AVD_IRQn
+
+
+
+/* Aliases for __IRQHandler */
+#define  HASH_RNG_IRQHandler           RNG_IRQHandler
+#define TIM1_BRK_TIM9_IRQHandler       TIM1_BRK_IRQHandler
+#define TIM1_UP_TIM9_IRQHandler        TIM1_UP_IRQHandler
+#define TIM1_TRG_COM_TIM11_IRQHandler  TIM1_TRG_COM_IRQHandler
+#define PVD_IRQHandler                 PVD_AVD_IRQHandler
+
+/* Aliases for COMP __IRQHandler */
+#define COMP_IRQHandler                COMP1_IRQHandler
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* STM32H743xx_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h
new file mode 100644
index 00000000..f6296181
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h
@@ -0,0 +1,224 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32H7xx Device Peripheral Access Layer Header File.
+  *
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The STM32H7xx device used in the target application
+  *              - To use or not the peripheral�s drivers in application code(i.e.
+  *                code will be based on direct access to peripheral�s registers
+  *                rather than drivers API), this option is controlled by
+  *                "#define USE_HAL_DRIVER"
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32h7xx
+  * @{
+  */
+
+#ifndef STM32H7xx_H
+#define STM32H7xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+
+/**
+  * @brief STM32 Family
+  */
+#if !defined  (STM32H7)
+#define STM32H7
+#endif /* STM32H7 */
+
+
+/* Uncomment the line below according to the target STM32H7 device used in your
+   application
+  */
+
+#if !defined (STM32H743xx) && !defined (STM32H753xx)  && !defined (STM32H750xx) && !defined (STM32H742xx) && \
+    !defined (STM32H745xx) && !defined (STM32H755xx)  && !defined (STM32H747xx) && !defined (STM32H757xx) && \
+    !defined (STM32H7A3xx) && !defined (STM32H7A3xxQ) && !defined (STM32H7B3xx) && !defined (STM32H7B3xxQ) && !defined (STM32H7B0xx)  && !defined (STM32H7B0xxQ)
+  /* #define STM32H742xx */   /*!< STM32H742VI, STM32H742ZI, STM32H742AI, STM32H742II, STM32H742BI, STM32H742XI Devices */
+  /* #define STM32H743xx */   /*!< STM32H743VI, STM32H743ZI, STM32H743AI, STM32H743II, STM32H743BI, STM32H743XI Devices */
+  /* #define STM32H753xx */   /*!< STM32H753VI, STM32H753ZI, STM32H753AI, STM32H753II, STM32H753BI, STM32H753XI Devices */
+  /* #define STM32H750xx */   /*!< STM32H750V, STM32H750I, STM32H750X Devices */
+  /* #define STM32H747xx */   /*!< STM32H747ZI, STM32H747AI, STM32H747II, STM32H747BI, STM32H747XI Devices */
+  /* #define STM32H757xx */   /*!< STM32H757ZI, STM32H757AI, STM32H757II, STM32H757BI, STM32H757XI Devices */
+  /* #define STM32H745xx */   /*!< STM32H745ZI, STM32H745II, STM32H745BI, STM32H745XI Devices  */
+  /* #define STM32H755xx */   /*!< STM32H755ZI, STM32H755II, STM32H755BI, STM32H755XI Devices  */
+  /* #define STM32H7B0xx */   /*!< STM32H7B0ABIxQ, STM32H7B0IBTx, STM32H7B0RBTx, STM32H7B0VBTx, STM32H7B0ZBTx, STM32H7B0IBKxQ */
+  /* #define STM32H7A3xx */   /*!< STM32H7A3IIK6, STM32H7A3IIT6, STM32H7A3NIH6, STM32H7A3RIT6, STM32H7A3VIH6, STM32H7A3VIT6, STM32H7A3ZIT6 */
+  /* #define STM32H7A3xxQ */  /*!< STM32H7A3QIY6Q, STM32H7A3IIK6Q, STM32H7A3IIT6Q, STM32H7A3LIH6Q, STM32H7A3VIH6Q, STM32H7A3VIT6Q, STM32H7A3AII6Q, STM32H7A3ZIT6Q */
+  /* #define STM32H7B3xx */   /*!< STM32H7B3IIK6, STM32H7B3IIT6, STM32H7B3NIH6, STM32H7B3RIT6, STM32H7B3VIH6, STM32H7B3VIT6, STM32H7B3ZIT6 */
+  /* #define STM32H7B3xxQ */  /*!< STM32H7B3QIY6Q, STM32H7B3IIK6Q, STM32H7B3IIT6Q, STM32H7B3LIH6Q, STM32H7B3VIH6Q, STM32H7B3VIT6Q, STM32H7B3AII6Q, STM32H7B3ZIT6Q */
+#endif
+
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+
+#if defined(DUAL_CORE) && !defined(CORE_CM4) && !defined(CORE_CM7)
+ #error "Dual core device, please select CORE_CM4 or CORE_CM7"
+#endif
+
+#if !defined  (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will
+   be based on direct access to peripherals registers
+   */
+  /*#define USE_HAL_DRIVER */
+#endif /* USE_HAL_DRIVER */
+
+/**
+  * @brief CMSIS Device version number V1.8.0
+  */
+#define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN   (0x01) /*!< [31:24] main version */
+#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1   (0x08) /*!< [23:16] sub1 version */
+#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __STM32H7xx_CMSIS_DEVICE_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
+#define __STM32H7xx_CMSIS_DEVICE_VERSION        ((__CMSIS_DEVICE_VERSION_MAIN     << 24)\
+                                      |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
+                                      |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
+                                      |(__CMSIS_DEVICE_HAL_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Device_Included
+  * @{
+  */
+
+#if defined(STM32H743xx)
+  #include "stm32h743xx.h"
+#elif defined(STM32H753xx)
+  #include "stm32h753xx.h"
+#elif defined(STM32H750xx)
+  #include "stm32h750xx.h"
+#elif defined(STM32H742xx)
+  #include "stm32h742xx.h"
+#elif defined(STM32H745xx)
+  #include "stm32h745xx.h"
+#elif defined(STM32H755xx)
+  #include "stm32h755xx.h"
+#elif defined(STM32H747xx)
+  #include "stm32h747xx.h"
+#elif defined(STM32H757xx)
+  #include "stm32h757xx.h"
+#elif defined(STM32H7B0xx)
+  #include "stm32h7b0xx.h"
+#elif defined(STM32H7B0xxQ)
+  #include "stm32h7b0xxq.h"
+#elif defined(STM32H7A3xx)
+  #include "stm32h7a3xx.h"
+#elif defined(STM32H7B3xx)
+  #include "stm32h7b3xx.h"
+#elif defined(STM32H7A3xxQ)
+  #include "stm32h7a3xxq.h"
+#elif defined(STM32H7B3xxQ)
+  #include "stm32h7b3xxq.h"
+#else
+ #error "Please select first the target STM32H7xx device used in your application (in stm32h7xx.h file)"
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_types
+  * @{
+  */
+typedef enum
+{
+  RESET = 0,
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+  DISABLE = 0,
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+  SUCCESS = 0,
+  ERROR = !SUCCESS
+} ErrorStatus;
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL)))
+
+
+/**
+  * @}
+  */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32h7xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* STM32H7xx_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h
new file mode 100644
index 00000000..dd75af67
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h
@@ -0,0 +1,105 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32h7xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-Mx Device System Source File for STM32H7xx devices.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32h7xx_system
+  * @{
+  */
+
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef SYSTEM_STM32H7XX_H
+#define SYSTEM_STM32H7XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32H7xx_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32H7xx_System_Exported_types
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+extern uint32_t SystemCoreClock;             /*!< System Domain1 Clock Frequency  */
+extern uint32_t SystemD2Clock;               /*!< System Domain2 Clock Frequency  */
+extern const  uint8_t D1CorePrescTable[16] ; /*!< D1CorePrescTable prescalers table values */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Exported_Functions
+  * @{
+  */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_STM32H7XX_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/cmsis_armcc.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/cmsis_armcc.h
new file mode 100644
index 00000000..7d751fb3
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/cmsis_armcc.h
@@ -0,0 +1,865 @@
+/**************************************************************************//**
+ * @file     cmsis_armcc.h
+ * @brief    CMSIS compiler ARMCC (Arm Compiler 5) header file
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+  #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \
+     (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )
+  #define __ARM_ARCH_6M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))
+  #define __ARM_ARCH_7M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+  #define __ARM_ARCH_7EM__          1
+#endif
+
+  /* __ARM_ARCH_8M_BASE__  not applicable */
+  /* __ARM_ARCH_8M_MAIN__  not applicable */
+
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE                 
+  #define __STATIC_FORCEINLINE                   static __forceinline
+#endif           
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __declspec(noreturn)
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        __packed struct
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         __packed union
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #define __UNALIGNED_UINT32(x)                  (*((__packed uint32_t *)(x)))
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();     */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();    */
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  register uint32_t __regBasePriMax      __ASM("basepri_max");
+  __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#else
+  (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB() do {\
+                   __schedule_barrier();\
+                   __isb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+                   __schedule_barrier();\
+                   __dsb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+                   __schedule_barrier();\
+                   __dmb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+                  
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+  #define __RBIT                          __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value != 0U; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+  return result;
+}
+#endif
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
+#else
+  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
+#else
+  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
+#else
+  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXB(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX                           __clrex
+
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#else  /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/cmsis_armclang.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/cmsis_armclang.h
new file mode 100644
index 00000000..d8031b03
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/cmsis_armclang.h
@@ -0,0 +1,1869 @@
+/**************************************************************************//**
+ * @file     cmsis_armclang.h
+ * @brief    CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header   /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include <arm_compat.h>    /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE                 
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline
+#endif                                           
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+  
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+  
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+  return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#define __get_FPSCR      (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR()      ((uint32_t)0U)
+#endif
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#define __set_FPSCR      __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x)      ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP          __builtin_arm_nop
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI          __builtin_arm_wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE          __builtin_arm_wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV          __builtin_arm_sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB()        __builtin_arm_isb(0xF);
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()        __builtin_arm_dsb(0xF);
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB()        __builtin_arm_dmb(0xF);
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV(value)   __builtin_bswap32(value)
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U)
+  {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)     __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __RBIT            __builtin_arm_rbit
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ             (uint8_t)__builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB        (uint8_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH        (uint16_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW        (uint32_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXB        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXH        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXW        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX             __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT             __builtin_arm_ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT             __builtin_arm_usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXB                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXH                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEX                  (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+  int32_t result;
+
+  __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/cmsis_compiler.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/cmsis_compiler.h
new file mode 100644
index 00000000..79a2cac3
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/cmsis_compiler.h
@@ -0,0 +1,266 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/cmsis_gcc.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/cmsis_gcc.h
new file mode 100644
index 00000000..1bd41a49
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/cmsis_gcc.h
@@ -0,0 +1,2085 @@
+/**************************************************************************//**
+ * @file     cmsis_gcc.h
+ * @brief    CMSIS compiler GCC header file
+ * @version  V5.0.4
+ * @date     09. April 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+  #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static inline
+#endif
+#ifndef   __STATIC_FORCEINLINE                 
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
+#endif                                           
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+  
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+  
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+  return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_get_fpscr) 
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+  return __builtin_arm_get_fpscr();
+#else
+  uint32_t result;
+
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  return(result);
+#endif
+#else
+  return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_set_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+  __builtin_arm_set_fpscr(fpscr);
+#else
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#endif
+#else
+  (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP()                             __ASM volatile ("nop")
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI()                             __ASM volatile ("wfi")
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE()                             __ASM volatile ("wfe")
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV()                             __ASM volatile ("sev")
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE void __ISB(void)
+{
+  __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+  __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+  __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (int16_t)__builtin_bswap16(value);
+#else
+  int16_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U)
+  {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value != 0U; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+#endif
+  return result;
+}
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ             (uint8_t)__builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  ARG1  Value to be saturated
+  \param [in]  ARG2  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+__extension__ \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  ARG1  Value to be saturated
+  \param [in]  ARG2  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+ __extension__ \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/cmsis_iccarm.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/cmsis_iccarm.h
new file mode 100644
index 00000000..3c90a2cd
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/cmsis_iccarm.h
@@ -0,0 +1,935 @@
+/**************************************************************************//**
+ * @file     cmsis_iccarm.h
+ * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version  V5.0.7
+ * @date     19. June 2018
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2018 IAR Systems
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+  #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+  #define __ICCARM_V8 1
+#else
+  #define __ICCARM_V8 0
+#endif
+
+#ifndef __ALIGNED
+  #if __ICCARM_V8
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #elif (__VER__ >= 7080000)
+    /* Needs IAR language extensions */
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #else
+    #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
+/* Macros already defined */
+#else
+  #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
+    #if __ARM_ARCH == 6
+      #define __ARM_ARCH_6M__ 1
+    #elif __ARM_ARCH == 7
+      #if __ARM_FEATURE_DSP
+        #define __ARM_ARCH_7EM__ 1
+      #else
+        #define __ARM_ARCH_7M__ 1
+      #endif
+    #endif /* __ARM_ARCH */
+  #endif /* __ARM_ARCH_PROFILE == 'M' */
+#endif
+
+/* Alternativ core deduction for older ICCARM's */
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
+    !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
+  #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
+    #define __ARM_ARCH_6M__ 1
+  #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
+    #define __ARM_ARCH_7M__ 1
+  #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
+    #define __ARM_ARCH_7EM__  1
+  #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #else
+    #error "Unknown target."
+  #endif
+#endif
+
+
+
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
+  #define __IAR_M0_FAMILY  1
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
+  #define __IAR_M0_FAMILY  1
+#else
+  #define __IAR_M0_FAMILY  0
+#endif
+
+
+#ifndef __ASM
+  #define __ASM __asm
+#endif
+
+#ifndef __INLINE
+  #define __INLINE inline
+#endif
+
+#ifndef   __NO_RETURN
+  #if __ICCARM_V8
+    #define __NO_RETURN __attribute__((__noreturn__))
+  #else
+    #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+  #endif
+#endif
+
+#ifndef   __PACKED
+  #if __ICCARM_V8
+    #define __PACKED __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED __packed
+  #endif
+#endif
+
+#ifndef   __PACKED_STRUCT
+  #if __ICCARM_V8
+    #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_STRUCT __packed struct
+  #endif
+#endif
+
+#ifndef   __PACKED_UNION
+  #if __ICCARM_V8
+    #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_UNION __packed union
+  #endif
+#endif
+
+#ifndef   __RESTRICT
+  #define __RESTRICT            __restrict
+#endif
+
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE       static inline
+#endif
+
+#ifndef   __FORCEINLINE
+  #define __FORCEINLINE         _Pragma("inline=forced")
+#endif
+
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE  __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+{
+  return *(__packed uint16_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+{
+  *(__packed uint16_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+{
+  return *(__packed uint32_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+{
+  *(__packed uint32_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32   /* deprecated */
+#pragma language=save
+#pragma language=extended
+__packed struct  __iar_u32 { uint32_t v; };
+#pragma language=restore
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+
+#ifndef   __USED
+  #if __ICCARM_V8
+    #define __USED __attribute__((used))
+  #else
+    #define __USED _Pragma("__root")
+  #endif
+#endif
+
+#ifndef   __WEAK
+  #if __ICCARM_V8
+    #define __WEAK __attribute__((weak))
+  #else
+    #define __WEAK _Pragma("__weak")
+  #endif
+#endif
+
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+  #define __ICCARM_INTRINSICS_VERSION__  0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+  #if defined(__CLZ)
+    #undef __CLZ
+  #endif
+  #if defined(__REVSH)
+    #undef __REVSH
+  #endif
+  #if defined(__RBIT)
+    #undef __RBIT
+  #endif
+  #if defined(__SSAT)
+    #undef __SSAT
+  #endif
+  #if defined(__USAT)
+    #undef __USAT
+  #endif
+
+  #include "iccarm_builtin.h"
+
+  #define __disable_fault_irq __iar_builtin_disable_fiq
+  #define __disable_irq       __iar_builtin_disable_interrupt
+  #define __enable_fault_irq  __iar_builtin_enable_fiq
+  #define __enable_irq        __iar_builtin_enable_interrupt
+  #define __arm_rsr           __iar_builtin_rsr
+  #define __arm_wsr           __iar_builtin_wsr
+
+
+  #define __get_APSR()                (__arm_rsr("APSR"))
+  #define __get_BASEPRI()             (__arm_rsr("BASEPRI"))
+  #define __get_CONTROL()             (__arm_rsr("CONTROL"))
+  #define __get_FAULTMASK()           (__arm_rsr("FAULTMASK"))
+
+  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+    #define __get_FPSCR()             (__arm_rsr("FPSCR"))
+    #define __set_FPSCR(VALUE)        (__arm_wsr("FPSCR", (VALUE)))
+  #else
+    #define __get_FPSCR()             ( 0 )
+    #define __set_FPSCR(VALUE)        ((void)VALUE)
+  #endif
+
+  #define __get_IPSR()                (__arm_rsr("IPSR"))
+  #define __get_MSP()                 (__arm_rsr("MSP"))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __get_MSPLIM()            (0U)
+  #else
+    #define __get_MSPLIM()            (__arm_rsr("MSPLIM"))
+  #endif
+  #define __get_PRIMASK()             (__arm_rsr("PRIMASK"))
+  #define __get_PSP()                 (__arm_rsr("PSP"))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __get_PSPLIM()            (0U)
+  #else
+    #define __get_PSPLIM()            (__arm_rsr("PSPLIM"))
+  #endif
+
+  #define __get_xPSR()                (__arm_rsr("xPSR"))
+
+  #define __set_BASEPRI(VALUE)        (__arm_wsr("BASEPRI", (VALUE)))
+  #define __set_BASEPRI_MAX(VALUE)    (__arm_wsr("BASEPRI_MAX", (VALUE)))
+  #define __set_CONTROL(VALUE)        (__arm_wsr("CONTROL", (VALUE)))
+  #define __set_FAULTMASK(VALUE)      (__arm_wsr("FAULTMASK", (VALUE)))
+  #define __set_MSP(VALUE)            (__arm_wsr("MSP", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __set_MSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_MSPLIM(VALUE)       (__arm_wsr("MSPLIM", (VALUE)))
+  #endif
+  #define __set_PRIMASK(VALUE)        (__arm_wsr("PRIMASK", (VALUE)))
+  #define __set_PSP(VALUE)            (__arm_wsr("PSP", (VALUE)))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __set_PSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_PSPLIM(VALUE)       (__arm_wsr("PSPLIM", (VALUE)))
+  #endif
+
+  #define __TZ_get_CONTROL_NS()       (__arm_rsr("CONTROL_NS"))
+  #define __TZ_set_CONTROL_NS(VALUE)  (__arm_wsr("CONTROL_NS", (VALUE)))
+  #define __TZ_get_PSP_NS()           (__arm_rsr("PSP_NS"))
+  #define __TZ_set_PSP_NS(VALUE)      (__arm_wsr("PSP_NS", (VALUE)))
+  #define __TZ_get_MSP_NS()           (__arm_rsr("MSP_NS"))
+  #define __TZ_set_MSP_NS(VALUE)      (__arm_wsr("MSP_NS", (VALUE)))
+  #define __TZ_get_SP_NS()            (__arm_rsr("SP_NS"))
+  #define __TZ_set_SP_NS(VALUE)       (__arm_wsr("SP_NS", (VALUE)))
+  #define __TZ_get_PRIMASK_NS()       (__arm_rsr("PRIMASK_NS"))
+  #define __TZ_set_PRIMASK_NS(VALUE)  (__arm_wsr("PRIMASK_NS", (VALUE)))
+  #define __TZ_get_BASEPRI_NS()       (__arm_rsr("BASEPRI_NS"))
+  #define __TZ_set_BASEPRI_NS(VALUE)  (__arm_wsr("BASEPRI_NS", (VALUE)))
+  #define __TZ_get_FAULTMASK_NS()     (__arm_rsr("FAULTMASK_NS"))
+  #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __TZ_get_PSPLIM_NS()      (0U)
+    #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+  #else
+    #define __TZ_get_PSPLIM_NS()      (__arm_rsr("PSPLIM_NS"))
+    #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+  #endif
+
+  #define __TZ_get_MSPLIM_NS()        (__arm_rsr("MSPLIM_NS"))
+  #define __TZ_set_MSPLIM_NS(VALUE)   (__arm_wsr("MSPLIM_NS", (VALUE)))
+
+  #define __NOP     __iar_builtin_no_operation
+
+  #define __CLZ     __iar_builtin_CLZ
+  #define __CLREX   __iar_builtin_CLREX
+
+  #define __DMB     __iar_builtin_DMB
+  #define __DSB     __iar_builtin_DSB
+  #define __ISB     __iar_builtin_ISB
+
+  #define __LDREXB  __iar_builtin_LDREXB
+  #define __LDREXH  __iar_builtin_LDREXH
+  #define __LDREXW  __iar_builtin_LDREX
+
+  #define __RBIT    __iar_builtin_RBIT
+  #define __REV     __iar_builtin_REV
+  #define __REV16   __iar_builtin_REV16
+
+  __IAR_FT int16_t __REVSH(int16_t val)
+  {
+    return (int16_t) __iar_builtin_REVSH(val);
+  }
+
+  #define __ROR     __iar_builtin_ROR
+  #define __RRX     __iar_builtin_RRX
+
+  #define __SEV     __iar_builtin_SEV
+
+  #if !__IAR_M0_FAMILY
+    #define __SSAT    __iar_builtin_SSAT
+  #endif
+
+  #define __STREXB  __iar_builtin_STREXB
+  #define __STREXH  __iar_builtin_STREXH
+  #define __STREXW  __iar_builtin_STREX
+
+  #if !__IAR_M0_FAMILY
+    #define __USAT    __iar_builtin_USAT
+  #endif
+
+  #define __WFE     __iar_builtin_WFE
+  #define __WFI     __iar_builtin_WFI
+
+  #if __ARM_MEDIA__
+    #define __SADD8   __iar_builtin_SADD8
+    #define __QADD8   __iar_builtin_QADD8
+    #define __SHADD8  __iar_builtin_SHADD8
+    #define __UADD8   __iar_builtin_UADD8
+    #define __UQADD8  __iar_builtin_UQADD8
+    #define __UHADD8  __iar_builtin_UHADD8
+    #define __SSUB8   __iar_builtin_SSUB8
+    #define __QSUB8   __iar_builtin_QSUB8
+    #define __SHSUB8  __iar_builtin_SHSUB8
+    #define __USUB8   __iar_builtin_USUB8
+    #define __UQSUB8  __iar_builtin_UQSUB8
+    #define __UHSUB8  __iar_builtin_UHSUB8
+    #define __SADD16  __iar_builtin_SADD16
+    #define __QADD16  __iar_builtin_QADD16
+    #define __SHADD16 __iar_builtin_SHADD16
+    #define __UADD16  __iar_builtin_UADD16
+    #define __UQADD16 __iar_builtin_UQADD16
+    #define __UHADD16 __iar_builtin_UHADD16
+    #define __SSUB16  __iar_builtin_SSUB16
+    #define __QSUB16  __iar_builtin_QSUB16
+    #define __SHSUB16 __iar_builtin_SHSUB16
+    #define __USUB16  __iar_builtin_USUB16
+    #define __UQSUB16 __iar_builtin_UQSUB16
+    #define __UHSUB16 __iar_builtin_UHSUB16
+    #define __SASX    __iar_builtin_SASX
+    #define __QASX    __iar_builtin_QASX
+    #define __SHASX   __iar_builtin_SHASX
+    #define __UASX    __iar_builtin_UASX
+    #define __UQASX   __iar_builtin_UQASX
+    #define __UHASX   __iar_builtin_UHASX
+    #define __SSAX    __iar_builtin_SSAX
+    #define __QSAX    __iar_builtin_QSAX
+    #define __SHSAX   __iar_builtin_SHSAX
+    #define __USAX    __iar_builtin_USAX
+    #define __UQSAX   __iar_builtin_UQSAX
+    #define __UHSAX   __iar_builtin_UHSAX
+    #define __USAD8   __iar_builtin_USAD8
+    #define __USADA8  __iar_builtin_USADA8
+    #define __SSAT16  __iar_builtin_SSAT16
+    #define __USAT16  __iar_builtin_USAT16
+    #define __UXTB16  __iar_builtin_UXTB16
+    #define __UXTAB16 __iar_builtin_UXTAB16
+    #define __SXTB16  __iar_builtin_SXTB16
+    #define __SXTAB16 __iar_builtin_SXTAB16
+    #define __SMUAD   __iar_builtin_SMUAD
+    #define __SMUADX  __iar_builtin_SMUADX
+    #define __SMMLA   __iar_builtin_SMMLA
+    #define __SMLAD   __iar_builtin_SMLAD
+    #define __SMLADX  __iar_builtin_SMLADX
+    #define __SMLALD  __iar_builtin_SMLALD
+    #define __SMLALDX __iar_builtin_SMLALDX
+    #define __SMUSD   __iar_builtin_SMUSD
+    #define __SMUSDX  __iar_builtin_SMUSDX
+    #define __SMLSD   __iar_builtin_SMLSD
+    #define __SMLSDX  __iar_builtin_SMLSDX
+    #define __SMLSLD  __iar_builtin_SMLSLD
+    #define __SMLSLDX __iar_builtin_SMLSLDX
+    #define __SEL     __iar_builtin_SEL
+    #define __QADD    __iar_builtin_QADD
+    #define __QSUB    __iar_builtin_QSUB
+    #define __PKHBT   __iar_builtin_PKHBT
+    #define __PKHTB   __iar_builtin_PKHTB
+  #endif
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #define __CLZ  __cmsis_iar_clz_not_active
+    #define __SSAT __cmsis_iar_ssat_not_active
+    #define __USAT __cmsis_iar_usat_not_active
+    #define __RBIT __cmsis_iar_rbit_not_active
+    #define __get_APSR  __cmsis_iar_get_APSR_not_active
+  #endif
+
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+    #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
+  #endif
+
+  #ifdef __INTRINSICS_INCLUDED
+  #error intrinsics.h is already included previously!
+  #endif
+
+  #include <intrinsics.h>
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #undef __CLZ
+    #undef __SSAT
+    #undef __USAT
+    #undef __RBIT
+    #undef __get_APSR
+
+    __STATIC_INLINE uint8_t __CLZ(uint32_t data)
+    {
+      if (data == 0U) { return 32U; }
+
+      uint32_t count = 0U;
+      uint32_t mask = 0x80000000U;
+
+      while ((data & mask) == 0U)
+      {
+        count += 1U;
+        mask = mask >> 1U;
+      }
+      return count;
+    }
+
+    __STATIC_INLINE uint32_t __RBIT(uint32_t v)
+    {
+      uint8_t sc = 31U;
+      uint32_t r = v;
+      for (v >>= 1U; v; v >>= 1U)
+      {
+        r <<= 1U;
+        r |= v & 1U;
+        sc--;
+      }
+      return (r << sc);
+    }
+
+    __STATIC_INLINE  uint32_t __get_APSR(void)
+    {
+      uint32_t res;
+      __asm("MRS      %0,APSR" : "=r" (res));
+      return res;
+    }
+
+  #endif
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #undef __get_FPSCR
+    #undef __set_FPSCR
+    #define __get_FPSCR()       (0)
+    #define __set_FPSCR(VALUE)  ((void)VALUE)
+  #endif
+
+  #pragma diag_suppress=Pe940
+  #pragma diag_suppress=Pe177
+
+  #define __enable_irq    __enable_interrupt
+  #define __disable_irq   __disable_interrupt
+  #define __NOP           __no_operation
+
+  #define __get_xPSR      __get_PSR
+
+  #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
+
+    __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+    {
+      return __LDREX((unsigned long *)ptr);
+    }
+
+    __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+    {
+      return __STREX(value, (unsigned long *)ptr);
+    }
+  #endif
+
+
+  /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+  #if (__CORTEX_M >= 0x03)
+
+    __IAR_FT uint32_t __RRX(uint32_t value)
+    {
+      uint32_t result;
+      __ASM("RRX      %0, %1" : "=r"(result) : "r" (value) : "cc");
+      return(result);
+    }
+
+    __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_MAX,%0"::"r" (value));
+    }
+
+
+    #define __enable_fault_irq  __enable_fiq
+    #define __disable_fault_irq __disable_fiq
+
+
+  #endif /* (__CORTEX_M >= 0x03) */
+
+  __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+  {
+    return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+  }
+
+  #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+       (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+   __IAR_FT uint32_t __get_MSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,MSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_MSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      MSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __get_PSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,PSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_PSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      PSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,CONTROL_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_CONTROL_NS(uint32_t value)
+    {
+      __asm volatile("MSR      CONTROL_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_SP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,SP_NS" : "=r" (res));
+      return res;
+    }
+    __IAR_FT void   __TZ_set_SP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      SP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PRIMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PRIMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PRIMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PRIMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_BASEPRI_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,BASEPRI_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_BASEPRI_NS(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_FAULTMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,FAULTMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_FAULTMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      FAULTMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSPLIM_NS(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,PSPLIM_NS" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PSPLIM_NS(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      PSPLIM_NS,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSPLIM_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSPLIM_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSPLIM_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSPLIM_NS,%0" :: "r" (value));
+    }
+
+  #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#endif   /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value)    __asm volatile ("BKPT     %0" : : "i"(value))
+
+#if __IAR_M0_FAMILY
+  __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+  {
+    if ((sat >= 1U) && (sat <= 32U))
+    {
+      const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+      const int32_t min = -1 - max ;
+      if (val > max)
+      {
+        return max;
+      }
+      else if (val < min)
+      {
+        return min;
+      }
+    }
+    return val;
+  }
+
+  __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+  {
+    if (sat <= 31U)
+    {
+      const uint32_t max = ((1U << sat) - 1U);
+      if (val > (int32_t)max)
+      {
+        return max;
+      }
+      else if (val < 0)
+      {
+        return 0U;
+      }
+    }
+    return (uint32_t)val;
+  }
+#endif
+
+#if (__CORTEX_M >= 0x03)   /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+  __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
+  {
+    __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
+  {
+    __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
+  {
+    __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+  }
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+
+  __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
+  {
+    __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
+  {
+    __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
+  {
+    __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#undef __IAR_FT
+#undef __IAR_M0_FAMILY
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#endif /* __CMSIS_ICCARM_H__ */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/cmsis_version.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/cmsis_version.h
new file mode 100644
index 00000000..ae3f2e33
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/cmsis_version.h
@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 1U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/core_armv8mbl.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/core_armv8mbl.h
new file mode 100644
index 00000000..ec76ab21
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/core_armv8mbl.h
@@ -0,0 +1,1918 @@
+/**************************************************************************//**
+ * @file     core_armv8mbl.h
+ * @brief    CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File
+ * @version  V5.0.7
+ * @date     22. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MBL_H_GENERIC
+#define __CORE_ARMV8MBL_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_ARMv8MBL
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS definitions */
+#define __ARMv8MBL_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __ARMv8MBL_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __ARMv8MBL_CMSIS_VERSION       ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
+                                         __ARMv8MBL_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                     ( 2U)                                            /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MBL_H_DEPENDANT
+#define __CORE_ARMV8MBL_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __ARMv8MBL_REV
+    #define __ARMv8MBL_REV               0x0000U
+    #warning "__ARMv8MBL_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ETM_PRESENT
+    #define __ETM_PRESENT             0U
+    #warning "__ETM_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MTB_PRESENT
+    #define __MTB_PRESENT             0U
+    #warning "__MTB_PRESENT not defined in device header file; using default!"
+  #endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MBL */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+        uint32_t RESERVED0[6U];
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Sizes Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Sizes Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
+        uint32_t RESERVED3[809U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  Software Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  Software Lock Status Register */
+        uint32_t RESERVED4[4U];
+  __IM  uint32_t TYPE;                   /*!< Offset: 0xFC8 (R/ )  Device Identifier Register */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos              0U                                         /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk             (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)    /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos                0U                                         /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk               (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)        /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos                     1U                                         /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk                    (0x1UL << TPI_LSR_nTT_Pos)                  /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos                     1U                                         /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk                    (0x1UL << TPI_LSR_SLK_Pos)                  /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos                     0U                                         /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk                    (0x1UL /*<< TPI_LSR_SLI_Pos*/)              /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+        uint32_t RESERVED0[7U];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
+#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
+#else
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
+#endif
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/core_armv8mml.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/core_armv8mml.h
new file mode 100644
index 00000000..2d0f1067
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/core_armv8mml.h
@@ -0,0 +1,2927 @@
+/**************************************************************************//**
+ * @file     core_armv8mml.h
+ * @brief    CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File
+ * @version  V5.0.7
+ * @date     06. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MML_H_GENERIC
+#define __CORE_ARMV8MML_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_ARMv8MML
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS Armv8MML definitions */
+#define __ARMv8MML_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __ARMv8MML_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __ARMv8MML_CMSIS_VERSION       ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
+                                         __ARMv8MML_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                     (81U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MML_H_DEPENDANT
+#define __CORE_ARMV8MML_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __ARMv8MML_REV
+    #define __ARMv8MML_REV               0x0000U
+    #warning "__ARMv8MML_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DSP_PRESENT
+    #define __DSP_PRESENT             0U
+    #warning "__DSP_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MML */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */
+    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */
+    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED6[580U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
+        uint32_t RESERVED3[92U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+        uint32_t RESERVED7[6U];
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
+        uint32_t RESERVED6[4U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+        uint32_t RESERVED32[934U];
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+        uint32_t RESERVED33[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Sizes Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Sizes Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
+        uint32_t RESERVED3[809U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  Software Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  Software Lock Status Register */
+        uint32_t RESERVED4[4U];
+  __IM  uint32_t TYPE;                   /*!< Offset: 0xFC8 (R/ )  Device Identifier Register */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos              0U                                         /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk             (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)    /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos                0U                                         /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk               (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)        /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos                     1U                                         /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk                    (0x1UL << TPI_LSR_nTT_Pos)                  /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos                     1U                                         /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk                    (0x1UL << TPI_LSR_SLK_Pos)                  /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos                     0U                                         /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk                    (0x1UL /*<< TPI_LSR_SLI_Pos*/)              /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
+  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
+  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
+  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
+        uint32_t RESERVED0[1];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#else
+        uint32_t RESERVED0[3];
+#endif
+  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
+  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
+  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
+  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
+#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
+#else
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
+#endif
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Priority Grouping (non-secure)
+  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB_NS->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB_NS->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping (non-secure)
+  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/core_cm0.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/core_cm0.h
new file mode 100644
index 00000000..6f82227c
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/core_cm0.h
@@ -0,0 +1,949 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V5.0.5
+ * @date     28. May 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M0
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM0_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (0U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000U
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+        uint32_t RESERVED0;
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           Address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/core_cm0plus.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/core_cm0plus.h
new file mode 100644
index 00000000..b9377e8c
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/core_cm0plus.h
@@ -0,0 +1,1083 @@
+/**************************************************************************//**
+ * @file     core_cm0plus.h
+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version  V5.0.6
+ * @date     28. May 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex-M0+
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM0+ definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB  (__CM_CMSIS_VERSION_SUB)                   /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
+                                       __CM0PLUS_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                   (0U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0PLUS_REV
+    #define __CM0PLUS_REV             0x0000U
+    #warning "__CM0PLUS_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 8U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0+ header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0+ */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+    uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/core_cm1.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/core_cm1.h
new file mode 100644
index 00000000..fd1c4077
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/core_cm1.h
@@ -0,0 +1,976 @@
+/**************************************************************************//**
+ * @file     core_cm1.h
+ * @brief    CMSIS Cortex-M1 Core Peripheral Access Layer Header File
+ * @version  V1.0.0
+ * @date     23. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM1_H_GENERIC
+#define __CORE_CM1_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M1
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM1 definitions */
+#define __CM1_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM1_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM1_CMSIS_VERSION       ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM1_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (1U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM1_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM1_H_DEPENDANT
+#define __CORE_CM1_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM1_REV
+    #define __CM1_REV               0x0100U
+    #warning "__CM1_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M1 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+        uint32_t RESERVED0;
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_ITCMUAEN_Pos            4U                                        /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMUAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos)         /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
+
+#define SCnSCB_ACTLR_ITCMLAEN_Pos            3U                                        /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMLAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos)         /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M1 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M1 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           Address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM1_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/core_cm23.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/core_cm23.h
new file mode 100644
index 00000000..8202a8dd
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/core_cm23.h
@@ -0,0 +1,1993 @@
+/**************************************************************************//**
+ * @file     core_cm23.h
+ * @brief    CMSIS Cortex-M23 Core Peripheral Access Layer Header File
+ * @version  V5.0.7
+ * @date     22. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM23_H_GENERIC
+#define __CORE_CM23_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M23
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS definitions */
+#define __CM23_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM23_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM23_CMSIS_VERSION       ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
+                                     __CM23_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                 (23U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM23_H_DEPENDANT
+#define __CORE_CM23_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM23_REV
+    #define __CM23_REV                0x0000U
+    #warning "__CM23_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ETM_PRESENT
+    #define __ETM_PRESENT             0U
+    #warning "__ETM_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MTB_PRESENT
+    #define __MTB_PRESENT             0U
+    #warning "__MTB_PRESENT not defined in device header file; using default!"
+  #endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M23 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+        uint32_t RESERVED0[6U];
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t ITFTTD0;                /*!< Offset: 0xEEC (R/ )  Integration Test FIFO Test Data 0 Register */
+  __IOM uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/W)  Integration Test ATB Control Register 2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  Integration Test ATB Control Register 0 */
+  __IM  uint32_t ITFTTD1;                /*!< Offset: 0xEFC (R/ )  Integration Test FIFO Test Data 1 Register */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  Device Configuration Register */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos      16U                                         /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos       8U                                         /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos       0U                                          /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk      (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)      /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)      /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos      16U                                         /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos       8U                                         /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos       0U                                          /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk      (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)      /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)      /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+        uint32_t RESERVED0[7U];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M23 */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M23 */
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */ 
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
+#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
+#else 
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
+#endif
+
+	
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/core_cm3.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/core_cm3.h
new file mode 100644
index 00000000..b0dfbd3d
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/core_cm3.h
@@ -0,0 +1,1941 @@
+/**************************************************************************//**
+ * @file     core_cm3.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version  V5.0.8
+ * @date     04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M3
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM3_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (3U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM3_REV
+    #define __CM3_REV               0x0200U
+    #warning "__CM3_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if defined (__CM3_REV) && (__CM3_REV < 0x0201U)                   /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+#else
+        uint32_t RESERVED1[1U];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) );               /* Insert write key and priority group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/core_cm33.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/core_cm33.h
new file mode 100644
index 00000000..02f82e29
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/core_cm33.h
@@ -0,0 +1,3002 @@
+/**************************************************************************//**
+ * @file     core_cm33.h
+ * @brief    CMSIS Cortex-M33 Core Peripheral Access Layer Header File
+ * @version  V5.0.9
+ * @date     06. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM33_H_GENERIC
+#define __CORE_CM33_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M33
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS CM33 definitions */
+#define __CM33_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM33_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM33_CMSIS_VERSION       ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
+                                     __CM33_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                 (33U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined (__TARGET_FPU_VFP)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined (__ARM_PCS_VFP)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined (__ARMVFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined (__TI_VFP_SUPPORT__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined (__FPU_VFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM33_H_DEPENDANT
+#define __CORE_CM33_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM33_REV
+    #define __CM33_REV                0x0000U
+    #warning "__CM33_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DSP_PRESENT
+    #define __DSP_PRESENT             0U
+    #warning "__DSP_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M33 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */
+    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */
+    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED6[580U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
+        uint32_t RESERVED3[92U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+        uint32_t RESERVED7[6U];
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
+        uint32_t RESERVED6[4U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+        uint32_t RESERVED32[934U];
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+        uint32_t RESERVED33[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t ITFTTD0;                /*!< Offset: 0xEEC (R/ )  Integration Test FIFO Test Data 0 Register */
+  __IOM uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/W)  Integration Test ATB Control Register 2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  Integration Test ATB Control Register 0 */
+  __IM  uint32_t ITFTTD1;                /*!< Offset: 0xEFC (R/ )  Integration Test FIFO Test Data 1 Register */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  Device Configuration Register */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos      16U                                         /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos       8U                                         /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos       0U                                          /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk      (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)      /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)      /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos      16U                                         /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos       8U                                         /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos       0U                                          /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk      (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)      /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)      /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
+  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
+  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
+  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
+        uint32_t RESERVED0[1];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#else
+        uint32_t RESERVED0[3];
+#endif
+  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
+  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
+  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
+  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */ 
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
+#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
+#else 
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
+#endif
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priority group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Priority Grouping (non-secure)
+  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB_NS->AIRCR;                                                /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
+  SCB_NS->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping (non-secure)
+  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/core_cm4.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/core_cm4.h
new file mode 100644
index 00000000..308b8681
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/core_cm4.h
@@ -0,0 +1,2129 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V5.0.8
+ * @date     04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M4
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM4_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (4U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000U
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
+#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+#define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after return, restore floating-point state  */
+#define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after return, restore floating-point state  */
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/core_cm7.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/core_cm7.h
new file mode 100644
index 00000000..ada6c2a5
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/core_cm7.h
@@ -0,0 +1,2671 @@
+/**************************************************************************//**
+ * @file     core_cm7.h
+ * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File
+ * @version  V5.0.8
+ * @date     04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM7_H_GENERIC
+#define __CORE_CM7_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M7
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM7 definitions */
+#define __CM7_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM7_CMSIS_VERSION_SUB   ( __CM_CMSIS_VERSION_SUB)                  /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM7_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (7U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM7_H_DEPENDANT
+#define __CORE_CM7_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM7_REV
+    #define __CM7_REV               0x0000U
+    #warning "__CM7_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ICACHE_PRESENT
+    #define __ICACHE_PRESENT          0U
+    #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DCACHE_PRESENT
+    #define __DCACHE_PRESENT          0U
+    #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DTCM_PRESENT
+    #define __DTCM_PRESENT            0U
+    #warning "__DTCM_PRESENT        not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M7 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MFR[4U];             /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[5U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+        uint32_t RESERVED3[93U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+        uint32_t RESERVED7[6U];
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                      18U                                           /*!< SCB CCR: Branch prediction enable bit Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: Branch prediction enable bit Mask */
+
+#define SCB_CCR_IC_Pos                      17U                                           /*!< SCB CCR: Instruction cache enable bit Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: Instruction cache enable bit Mask */
+
+#define SCB_CCR_DC_Pos                      16U                                           /*!< SCB CCR: Cache enable bit Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: Cache enable bit Mask */
+
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12U                                         /*!< ACTLR: DISITMATBFLUSH Position */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define SCnSCB_ACTLR_DISRAMODE_Pos         11U                                         /*!< ACTLR: DISRAMODE Position */
+#define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: DISRAMODE Mask */
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos         10U                                         /*!< ACTLR: FPEXCODIS Position */
+#define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: FPEXCODIS Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED3[981U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 (  W)  Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
+#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+#define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after return, restore floating-point state  */
+#define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after return, restore floating-point state  */
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)IRQn)]                = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]                >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = SCB->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################  Cache functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_CacheFunctions Cache Functions
+  \brief    Functions that configure Instruction and Data cache.
+  @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )
+
+
+/**
+  \brief   Enable I-Cache
+  \details Turns on I-Cache
+  */
+__STATIC_INLINE void SCB_EnableICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+    __DSB();
+    __ISB();
+    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Disable I-Cache
+  \details Turns off I-Cache
+  */
+__STATIC_INLINE void SCB_DisableICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  /* disable I-Cache */
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Invalidate I-Cache
+  \details Invalidates I-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Enable D-Cache
+  \details Turns on D-Cache
+  */
+__STATIC_INLINE void SCB_EnableDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+    __DSB();
+
+    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Disable D-Cache
+  \details Turns off D-Cache
+  */
+__STATIC_INLINE void SCB_DisableDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  /* disable D-Cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean & invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Invalidate D-Cache
+  \details Invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Clean D-Cache
+  \details Cleans D-Cache
+  */
+__STATIC_INLINE void SCB_CleanDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+     SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+   __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
+                      ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Clean & Invalidate D-Cache
+  \details Cleans and Invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean & invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Invalidate by address
+  \details Invalidates D-Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+     int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t)addr;
+     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCIMVAC = op_addr;
+      op_addr += (uint32_t)linesize;
+      op_size -=           linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Clean by address
+  \details Cleans D-Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+     int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t) addr;
+     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCCMVAC = op_addr;
+      op_addr += (uint32_t)linesize;
+      op_size -=           linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Clean and Invalidate by address
+  \details Cleans and invalidates D_Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+     int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t) addr;
+     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCCIMVAC = op_addr;
+      op_addr += (uint32_t)linesize;
+      op_size -=           linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/core_sc000.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/core_sc000.h
new file mode 100644
index 00000000..9086c642
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/core_sc000.h
@@ -0,0 +1,1022 @@
+/**************************************************************************//**
+ * @file     core_sc000.h
+ * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version  V5.0.5
+ * @date     28. May 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup SC000
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                 /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
+                                      __SC000_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_SC                 (000U)                                   /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC000_REV
+    #define __SC000_REV             0x0000U
+    #warning "__SC000_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+        uint32_t RESERVED1[154U];
+  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the SC000 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for SC000 */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for SC000 */
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for SC000 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/core_sc300.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/core_sc300.h
new file mode 100644
index 00000000..665822da
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/core_sc300.h
@@ -0,0 +1,1915 @@
+/**************************************************************************//**
+ * @file     core_sc300.h
+ * @brief    CMSIS SC300 Core Peripheral Access Layer Header File
+ * @version  V5.0.6
+ * @date     04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup SC3000
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                 /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
+                                      __SC300_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_SC                 (300U)                                   /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC300_H_DEPENDANT
+#define __CORE_SC300_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC300_REV
+    #define __SC300_REV               0x0000U
+    #warning "__SC300_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+        uint32_t RESERVED1[129U];
+  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+        uint32_t RESERVED1[1U];
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/mpu_armv7.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/mpu_armv7.h
new file mode 100644
index 00000000..7d4b600c
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/mpu_armv7.h
@@ -0,0 +1,270 @@
+/******************************************************************************
+ * @file     mpu_armv7.h
+ * @brief    CMSIS MPU API for Armv7-M MPU
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+ 
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
+#define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
+#define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
+#define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
+#define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
+#define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
+#define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
+#define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
+#define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
+#define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
+#define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
+#define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
+#define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
+#define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
+#define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
+#define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
+#define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
+#define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
+#define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
+#define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
+#define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
+#define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
+#define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
+#define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
+#define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
+#define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
+#define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
+#define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
+
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
+#define ARM_MPU_AP_URO  2U ///!< MPU Access Permission unprivileged access read-only
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
+#define ARM_MPU_AP_PRO  5U ///!< MPU Access Permission privileged access read-only
+#define ARM_MPU_AP_RO   6U ///!< MPU Access Permission read-only access
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+  (((BaseAddress) & MPU_RBAR_ADDR_Msk) |  \
+   ((Region) & MPU_RBAR_REGION_Msk)    |  \
+   (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Memory Access Attributes
+* 
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+*/  
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)   \
+  ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk)                 | \
+   (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk)                      | \
+   (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk)                      | \
+   (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param AccessAttributes  Memory access attribution, see \ref ARM_MPU_ACCESS_.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)      \
+  ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk)                                          | \
+   (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)                                      | \
+   (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
+  
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/                         
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+  ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
+
+/**
+* MPU Memory Access Attribute for strongly ordered memory.
+*  - TEX: 000b
+*  - Shareable
+*  - Non-cacheable
+*  - Non-bufferable
+*/ 
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
+
+/**
+* MPU Memory Access Attribute for device memory.
+*  - TEX: 000b (if non-shareable) or 010b (if shareable)
+*  - Shareable or non-shareable
+*  - Non-cacheable
+*  - Bufferable (if shareable) or non-bufferable (if non-shareable)
+*
+* \param IsShareable Configures the device memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
+
+/**
+* MPU Memory Access Attribute for normal memory.
+*  - TEX: 1BBb (reflecting outer cacheability rules)
+*  - Shareable or non-shareable
+*  - Cacheable or non-cacheable (reflecting inner cacheability rules)
+*  - Bufferable or non-bufferable (reflecting inner cacheability rules)
+*
+* \param OuterCp Configures the outer cache policy.
+* \param InnerCp Configures the inner cache policy.
+* \param IsShareable Configures the memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
+
+/**
+* MPU Memory Access Attribute non-cacheable policy.
+*/
+#define ARM_MPU_CACHEP_NOCACHE 0U
+
+/**
+* MPU Memory Access Attribute write-back, write and read allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_WRA 1U
+
+/**
+* MPU Memory Access Attribute write-through, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WT_NWA 2U
+
+/**
+* MPU Memory Access Attribute write-back, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_NWA 3U
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR; //!< The region base address register value (RBAR)
+  uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  MPU->RNR = rnr;
+  MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+  MPU->RNR = rnr;
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  while (cnt > MPU_TYPE_RALIASES) {
+    orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+    table += MPU_TYPE_RALIASES;
+    cnt -= MPU_TYPE_RALIASES;
+  }
+  orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/mpu_armv8.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/mpu_armv8.h
new file mode 100644
index 00000000..99ee9f99
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/mpu_armv8.h
@@ -0,0 +1,333 @@
+/******************************************************************************
+ * @file     mpu_armv8.h
+ * @brief    CMSIS MPU API for Armv8-M MPU
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV8_H
+#define ARM_MPU_ARMV8_H
+
+/** \brief Attribute for device memory (outer only) */
+#define ARM_MPU_ATTR_DEVICE                           ( 0U )
+
+/** \brief Attribute for non-cacheable, normal memory */
+#define ARM_MPU_ATTR_NON_CACHEABLE                    ( 4U )
+
+/** \brief Attribute for normal memory (outer and inner)
+* \param NT Non-Transient: Set to 1 for non-transient data.
+* \param WB Write-Back: Set to 1 to use write-back update policy.
+* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
+* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
+*/
+#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
+  (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
+
+/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
+
+/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRE  (1U)
+
+/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGRE   (2U)
+
+/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_GRE    (3U)
+
+/** \brief Memory Attribute
+* \param O Outer memory attributes
+* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
+*/
+#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
+
+/** \brief Normal memory non-shareable  */
+#define ARM_MPU_SH_NON   (0U)
+
+/** \brief Normal memory outer shareable  */
+#define ARM_MPU_SH_OUTER (2U)
+
+/** \brief Normal memory inner shareable  */
+#define ARM_MPU_SH_INNER (3U)
+
+/** \brief Memory access permissions
+* \param RO Read-Only: Set to 1 for read-only memory.
+* \param NP Non-Privileged: Set to 1 for non-privileged memory.
+*/
+#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
+
+/** \brief Region Base Address Register value
+* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
+* \param SH Defines the Shareability domain for this memory region.
+* \param RO Read-Only: Set to 1 for a read-only memory region.
+* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
+* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
+*/
+#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
+  ((BASE & MPU_RBAR_BASE_Msk) | \
+  ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
+  ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
+  ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
+
+/** \brief Region Limit Address Register value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR(LIMIT, IDX) \
+  ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
+  ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+  (MPU_RLAR_EN_Msk))
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR;                   /*!< Region Base Address Register value */
+  uint32_t RLAR;                   /*!< Region Limit Address Register value */
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+#ifdef MPU_NS
+/** Enable the Non-secure MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the Non-secure MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable_NS(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU_NS->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+#endif
+
+/** Set the memory attribute encoding to the given MPU.
+* \param mpu Pointer to the MPU to be configured.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
+{
+  const uint8_t reg = idx / 4U;
+  const uint32_t pos = ((idx % 4U) * 8U);
+  const uint32_t mask = 0xFFU << pos;
+  
+  if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
+    return; // invalid index
+  }
+  
+  mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
+}
+
+/** Set the memory attribute encoding.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU, idx, attr);
+}
+
+#ifdef MPU_NS
+/** Set the memory attribute encoding to the Non-secure MPU.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
+}
+#endif
+
+/** Clear and disable the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
+{
+  mpu->RNR = rnr;
+  mpu->RLAR = 0U;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  ARM_MPU_ClrRegionEx(MPU, rnr);
+}
+
+#ifdef MPU_NS
+/** Clear and disable the given Non-secure MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
+{  
+  ARM_MPU_ClrRegionEx(MPU_NS, rnr);
+}
+#endif
+
+/** Configure the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  mpu->RNR = rnr;
+  mpu->RBAR = rbar;
+  mpu->RLAR = rlar;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
+}
+
+#ifdef MPU_NS
+/** Configure the given Non-secure MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);  
+}
+#endif
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table to the given MPU.
+* \param mpu Pointer to the MPU registers to be used.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  if (cnt == 1U) {
+    mpu->RNR = rnr;
+    orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
+  } else {
+    uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);
+    uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
+    
+    mpu->RNR = rnrBase;
+    while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
+      uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
+      orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
+      table += c;
+      cnt -= c;
+      rnrOffset = 0U;
+      rnrBase += MPU_TYPE_RALIASES;
+      mpu->RNR = rnrBase;
+    }
+    
+    orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU, rnr, table, cnt);
+}
+
+#ifdef MPU_NS
+/** Load the given number of MPU regions from a table to the Non-secure MPU.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
+}
+#endif
+
+#endif
+
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/tz_context.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/tz_context.h
new file mode 100644
index 00000000..d4c1474f
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/CMSIS/Include/tz_context.h
@@ -0,0 +1,70 @@
+/******************************************************************************
+ * @file     tz_context.h
+ * @brief    Context Management for Armv8-M TrustZone
+ * @version  V1.0.1
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef TZ_CONTEXT_H
+#define TZ_CONTEXT_H
+ 
+#include <stdint.h>
+ 
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+ 
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+  
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+ 
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in]  module   identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0    no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+ 
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+ 
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+ 
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+ 
+#endif  // TZ_CONTEXT_H
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
new file mode 100644
index 00000000..7b859e37
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
@@ -0,0 +1,3775 @@
+/**
+  ******************************************************************************
+  * @file    stm32_hal_legacy.h
+  * @author  MCD Application Team
+  * @brief   This file contains aliases definition for the STM32Cube HAL constants
+  *          macros and functions maintained for legacy purpose.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32_HAL_LEGACY
+#define STM32_HAL_LEGACY
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define AES_FLAG_RDERR                  CRYP_FLAG_RDERR
+#define AES_FLAG_WRERR                  CRYP_FLAG_WRERR
+#define AES_CLEARFLAG_CCF               CRYP_CLEARFLAG_CCF
+#define AES_CLEARFLAG_RDERR             CRYP_CLEARFLAG_RDERR
+#define AES_CLEARFLAG_WRERR             CRYP_CLEARFLAG_WRERR
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define ADC_RESOLUTION12b               ADC_RESOLUTION_12B
+#define ADC_RESOLUTION10b               ADC_RESOLUTION_10B
+#define ADC_RESOLUTION8b                ADC_RESOLUTION_8B
+#define ADC_RESOLUTION6b                ADC_RESOLUTION_6B
+#define OVR_DATA_OVERWRITTEN            ADC_OVR_DATA_OVERWRITTEN
+#define OVR_DATA_PRESERVED              ADC_OVR_DATA_PRESERVED
+#define EOC_SINGLE_CONV                 ADC_EOC_SINGLE_CONV
+#define EOC_SEQ_CONV                    ADC_EOC_SEQ_CONV
+#define EOC_SINGLE_SEQ_CONV             ADC_EOC_SINGLE_SEQ_CONV
+#define REGULAR_GROUP                   ADC_REGULAR_GROUP
+#define INJECTED_GROUP                  ADC_INJECTED_GROUP
+#define REGULAR_INJECTED_GROUP          ADC_REGULAR_INJECTED_GROUP
+#define AWD_EVENT                       ADC_AWD_EVENT
+#define AWD1_EVENT                      ADC_AWD1_EVENT
+#define AWD2_EVENT                      ADC_AWD2_EVENT
+#define AWD3_EVENT                      ADC_AWD3_EVENT
+#define OVR_EVENT                       ADC_OVR_EVENT
+#define JQOVF_EVENT                     ADC_JQOVF_EVENT
+#define ALL_CHANNELS                    ADC_ALL_CHANNELS
+#define REGULAR_CHANNELS                ADC_REGULAR_CHANNELS
+#define INJECTED_CHANNELS               ADC_INJECTED_CHANNELS
+#define SYSCFG_FLAG_SENSOR_ADC          ADC_FLAG_SENSOR
+#define SYSCFG_FLAG_VREF_ADC            ADC_FLAG_VREFINT
+#define ADC_CLOCKPRESCALER_PCLK_DIV1    ADC_CLOCK_SYNC_PCLK_DIV1
+#define ADC_CLOCKPRESCALER_PCLK_DIV2    ADC_CLOCK_SYNC_PCLK_DIV2
+#define ADC_CLOCKPRESCALER_PCLK_DIV4    ADC_CLOCK_SYNC_PCLK_DIV4
+#define ADC_CLOCKPRESCALER_PCLK_DIV6    ADC_CLOCK_SYNC_PCLK_DIV6
+#define ADC_CLOCKPRESCALER_PCLK_DIV8    ADC_CLOCK_SYNC_PCLK_DIV8
+#define ADC_EXTERNALTRIG0_T6_TRGO       ADC_EXTERNALTRIGCONV_T6_TRGO
+#define ADC_EXTERNALTRIG1_T21_CC2       ADC_EXTERNALTRIGCONV_T21_CC2
+#define ADC_EXTERNALTRIG2_T2_TRGO       ADC_EXTERNALTRIGCONV_T2_TRGO
+#define ADC_EXTERNALTRIG3_T2_CC4        ADC_EXTERNALTRIGCONV_T2_CC4
+#define ADC_EXTERNALTRIG4_T22_TRGO      ADC_EXTERNALTRIGCONV_T22_TRGO
+#define ADC_EXTERNALTRIG7_EXT_IT11      ADC_EXTERNALTRIGCONV_EXT_IT11
+#define ADC_CLOCK_ASYNC                 ADC_CLOCK_ASYNC_DIV1
+#define ADC_EXTERNALTRIG_EDGE_NONE      ADC_EXTERNALTRIGCONVEDGE_NONE
+#define ADC_EXTERNALTRIG_EDGE_RISING    ADC_EXTERNALTRIGCONVEDGE_RISING
+#define ADC_EXTERNALTRIG_EDGE_FALLING   ADC_EXTERNALTRIGCONVEDGE_FALLING
+#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
+#define ADC_SAMPLETIME_2CYCLE_5         ADC_SAMPLETIME_2CYCLES_5
+
+#define HAL_ADC_STATE_BUSY_REG          HAL_ADC_STATE_REG_BUSY
+#define HAL_ADC_STATE_BUSY_INJ          HAL_ADC_STATE_INJ_BUSY
+#define HAL_ADC_STATE_EOC_REG           HAL_ADC_STATE_REG_EOC
+#define HAL_ADC_STATE_EOC_INJ           HAL_ADC_STATE_INJ_EOC
+#define HAL_ADC_STATE_ERROR             HAL_ADC_STATE_ERROR_INTERNAL
+#define HAL_ADC_STATE_BUSY              HAL_ADC_STATE_BUSY_INTERNAL
+#define HAL_ADC_STATE_AWD               HAL_ADC_STATE_AWD1
+
+#if defined(STM32H7)
+#define ADC_CHANNEL_VBAT_DIV4           ADC_CHANNEL_VBAT
+#endif /* STM32H7 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define COMP_WINDOWMODE_DISABLED       COMP_WINDOWMODE_DISABLE
+#define COMP_WINDOWMODE_ENABLED        COMP_WINDOWMODE_ENABLE
+#define COMP_EXTI_LINE_COMP1_EVENT     COMP_EXTI_LINE_COMP1
+#define COMP_EXTI_LINE_COMP2_EVENT     COMP_EXTI_LINE_COMP2
+#define COMP_EXTI_LINE_COMP3_EVENT     COMP_EXTI_LINE_COMP3
+#define COMP_EXTI_LINE_COMP4_EVENT     COMP_EXTI_LINE_COMP4
+#define COMP_EXTI_LINE_COMP5_EVENT     COMP_EXTI_LINE_COMP5
+#define COMP_EXTI_LINE_COMP6_EVENT     COMP_EXTI_LINE_COMP6
+#define COMP_EXTI_LINE_COMP7_EVENT     COMP_EXTI_LINE_COMP7
+#if defined(STM32L0)
+#define COMP_LPTIMCONNECTION_ENABLED   ((uint32_t)0x00000003U)    /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
+#endif
+#define COMP_OUTPUT_COMP6TIM2OCREFCLR  COMP_OUTPUT_COMP6_TIM2OCREFCLR
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define COMP_OUTPUT_TIM3IC1            COMP_OUTPUT_COMP1_TIM3IC1
+#define COMP_OUTPUT_TIM3OCREFCLR       COMP_OUTPUT_COMP1_TIM3OCREFCLR
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32L0) || defined(STM32L4)
+#define COMP_WINDOWMODE_ENABLE         COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
+
+#define COMP_NONINVERTINGINPUT_IO1      COMP_INPUT_PLUS_IO1
+#define COMP_NONINVERTINGINPUT_IO2      COMP_INPUT_PLUS_IO2
+#define COMP_NONINVERTINGINPUT_IO3      COMP_INPUT_PLUS_IO3
+#define COMP_NONINVERTINGINPUT_IO4      COMP_INPUT_PLUS_IO4
+#define COMP_NONINVERTINGINPUT_IO5      COMP_INPUT_PLUS_IO5
+#define COMP_NONINVERTINGINPUT_IO6      COMP_INPUT_PLUS_IO6
+
+#define COMP_INVERTINGINPUT_1_4VREFINT  COMP_INPUT_MINUS_1_4VREFINT
+#define COMP_INVERTINGINPUT_1_2VREFINT  COMP_INPUT_MINUS_1_2VREFINT
+#define COMP_INVERTINGINPUT_3_4VREFINT  COMP_INPUT_MINUS_3_4VREFINT
+#define COMP_INVERTINGINPUT_VREFINT     COMP_INPUT_MINUS_VREFINT
+#define COMP_INVERTINGINPUT_DAC1_CH1    COMP_INPUT_MINUS_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC1_CH2    COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_DAC1        COMP_INPUT_MINUS_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC2        COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_IO1         COMP_INPUT_MINUS_IO1
+#if defined(STM32L0)
+/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2),     */
+/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding   */
+/* to the second dedicated IO (only for COMP2).                               */
+#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO2
+#else
+#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_IO2
+#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO3
+#endif
+#define COMP_INVERTINGINPUT_IO4         COMP_INPUT_MINUS_IO4
+#define COMP_INVERTINGINPUT_IO5         COMP_INPUT_MINUS_IO5
+
+#define COMP_OUTPUTLEVEL_LOW            COMP_OUTPUT_LEVEL_LOW
+#define COMP_OUTPUTLEVEL_HIGH           COMP_OUTPUT_LEVEL_HIGH
+
+/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose.                    */
+/*       To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()".        */
+#if defined(COMP_CSR_LOCK)
+#define COMP_FLAG_LOCK                 COMP_CSR_LOCK
+#elif defined(COMP_CSR_COMP1LOCK)
+#define COMP_FLAG_LOCK                 COMP_CSR_COMP1LOCK
+#elif defined(COMP_CSR_COMPxLOCK)
+#define COMP_FLAG_LOCK                 COMP_CSR_COMPxLOCK
+#endif
+
+#if defined(STM32L4)
+#define COMP_BLANKINGSRCE_TIM1OC5        COMP_BLANKINGSRC_TIM1_OC5_COMP1
+#define COMP_BLANKINGSRCE_TIM2OC3        COMP_BLANKINGSRC_TIM2_OC3_COMP1
+#define COMP_BLANKINGSRCE_TIM3OC3        COMP_BLANKINGSRC_TIM3_OC3_COMP1
+#define COMP_BLANKINGSRCE_TIM3OC4        COMP_BLANKINGSRC_TIM3_OC4_COMP2
+#define COMP_BLANKINGSRCE_TIM8OC5        COMP_BLANKINGSRC_TIM8_OC5_COMP2
+#define COMP_BLANKINGSRCE_TIM15OC1       COMP_BLANKINGSRC_TIM15_OC1_COMP2
+#define COMP_BLANKINGSRCE_NONE           COMP_BLANKINGSRC_NONE
+#endif
+
+#if defined(STM32L0)
+#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_MEDIUMSPEED
+#define COMP_MODE_LOWSPEED               COMP_POWERMODE_ULTRALOWPOWER
+#else
+#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_HIGHSPEED
+#define COMP_MODE_MEDIUMSPEED            COMP_POWERMODE_MEDIUMSPEED
+#define COMP_MODE_LOWPOWER               COMP_POWERMODE_LOWPOWER
+#define COMP_MODE_ULTRALOWPOWER          COMP_POWERMODE_ULTRALOWPOWER
+#endif
+
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
+/**
+  * @}
+  */
+
+/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define CRC_OUTPUTDATA_INVERSION_DISABLED    CRC_OUTPUTDATA_INVERSION_DISABLE
+#define CRC_OUTPUTDATA_INVERSION_ENABLED     CRC_OUTPUTDATA_INVERSION_ENABLE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define DAC1_CHANNEL_1                                  DAC_CHANNEL_1
+#define DAC1_CHANNEL_2                                  DAC_CHANNEL_2
+#define DAC2_CHANNEL_1                                  DAC_CHANNEL_1
+#define DAC_WAVE_NONE                                   0x00000000U
+#define DAC_WAVE_NOISE                                  DAC_CR_WAVE1_0
+#define DAC_WAVE_TRIANGLE                               DAC_CR_WAVE1_1
+#define DAC_WAVEGENERATION_NONE                         DAC_WAVE_NONE
+#define DAC_WAVEGENERATION_NOISE                        DAC_WAVE_NOISE
+#define DAC_WAVEGENERATION_TRIANGLE                     DAC_WAVE_TRIANGLE
+
+#if defined(STM32G4) || defined(STM32H7)
+#define DAC_CHIPCONNECT_DISABLE       DAC_CHIPCONNECT_EXTERNAL
+#define DAC_CHIPCONNECT_ENABLE        DAC_CHIPCONNECT_INTERNAL
+#endif
+
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
+#define HAL_DAC_MSP_INIT_CB_ID       HAL_DAC_MSPINIT_CB_ID
+#define HAL_DAC_MSP_DEINIT_CB_ID     HAL_DAC_MSPDEINIT_CB_ID
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define HAL_REMAPDMA_ADC_DMA_CH2                DMA_REMAP_ADC_DMA_CH2
+#define HAL_REMAPDMA_USART1_TX_DMA_CH4          DMA_REMAP_USART1_TX_DMA_CH4
+#define HAL_REMAPDMA_USART1_RX_DMA_CH5          DMA_REMAP_USART1_RX_DMA_CH5
+#define HAL_REMAPDMA_TIM16_DMA_CH4              DMA_REMAP_TIM16_DMA_CH4
+#define HAL_REMAPDMA_TIM17_DMA_CH2              DMA_REMAP_TIM17_DMA_CH2
+#define HAL_REMAPDMA_USART3_DMA_CH32            DMA_REMAP_USART3_DMA_CH32
+#define HAL_REMAPDMA_TIM16_DMA_CH6              DMA_REMAP_TIM16_DMA_CH6
+#define HAL_REMAPDMA_TIM17_DMA_CH7              DMA_REMAP_TIM17_DMA_CH7
+#define HAL_REMAPDMA_SPI2_DMA_CH67              DMA_REMAP_SPI2_DMA_CH67
+#define HAL_REMAPDMA_USART2_DMA_CH67            DMA_REMAP_USART2_DMA_CH67
+#define HAL_REMAPDMA_I2C1_DMA_CH76              DMA_REMAP_I2C1_DMA_CH76
+#define HAL_REMAPDMA_TIM1_DMA_CH6               DMA_REMAP_TIM1_DMA_CH6
+#define HAL_REMAPDMA_TIM2_DMA_CH7               DMA_REMAP_TIM2_DMA_CH7
+#define HAL_REMAPDMA_TIM3_DMA_CH6               DMA_REMAP_TIM3_DMA_CH6
+
+#define IS_HAL_REMAPDMA                          IS_DMA_REMAP
+#define __HAL_REMAPDMA_CHANNEL_ENABLE            __HAL_DMA_REMAP_CHANNEL_ENABLE
+#define __HAL_REMAPDMA_CHANNEL_DISABLE           __HAL_DMA_REMAP_CHANNEL_DISABLE
+
+#if defined(STM32L4)
+
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI0            HAL_DMAMUX1_REQ_GEN_EXTI0
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI1            HAL_DMAMUX1_REQ_GEN_EXTI1
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI2            HAL_DMAMUX1_REQ_GEN_EXTI2
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI3            HAL_DMAMUX1_REQ_GEN_EXTI3
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI4            HAL_DMAMUX1_REQ_GEN_EXTI4
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI5            HAL_DMAMUX1_REQ_GEN_EXTI5
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI6            HAL_DMAMUX1_REQ_GEN_EXTI6
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI7            HAL_DMAMUX1_REQ_GEN_EXTI7
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI8            HAL_DMAMUX1_REQ_GEN_EXTI8
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI9            HAL_DMAMUX1_REQ_GEN_EXTI9
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI10           HAL_DMAMUX1_REQ_GEN_EXTI10
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI11           HAL_DMAMUX1_REQ_GEN_EXTI11
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI12           HAL_DMAMUX1_REQ_GEN_EXTI12
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI13           HAL_DMAMUX1_REQ_GEN_EXTI13
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI14           HAL_DMAMUX1_REQ_GEN_EXTI14
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI15           HAL_DMAMUX1_REQ_GEN_EXTI15
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT       HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT       HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE           HAL_DMAMUX1_REQ_GEN_DSI_TE
+#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT          HAL_DMAMUX1_REQ_GEN_DSI_EOT
+#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT        HAL_DMAMUX1_REQ_GEN_DMA2D_EOT
+#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT          HAL_DMAMUX1_REQ_GEN_LTDC_IT
+
+#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT          HAL_DMAMUX_REQ_GEN_NO_EVENT
+#define HAL_DMAMUX_REQUEST_GEN_RISING            HAL_DMAMUX_REQ_GEN_RISING
+#define HAL_DMAMUX_REQUEST_GEN_FALLING           HAL_DMAMUX_REQ_GEN_FALLING
+#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING    HAL_DMAMUX_REQ_GEN_RISING_FALLING
+
+#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+#define DMA_REQUEST_DCMI_PSSI                    DMA_REQUEST_DCMI
+#endif
+
+#endif /* STM32L4 */
+
+#if defined(STM32G0)
+#define DMA_REQUEST_DAC1_CHANNEL1                DMA_REQUEST_DAC1_CH1
+#define DMA_REQUEST_DAC1_CHANNEL2                DMA_REQUEST_DAC1_CH2
+#endif
+
+#if defined(STM32H7)
+
+#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
+#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
+
+#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
+#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
+
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI0              HAL_DMAMUX1_REQ_GEN_EXTI0
+#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO         HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
+
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP          HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP          HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT          HAL_DMAMUX2_REQ_GEN_COMP1_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT          HAL_DMAMUX2_REQ_GEN_COMP2_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP           HAL_DMAMUX2_REQ_GEN_RTC_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_EXTI0              HAL_DMAMUX2_REQ_GEN_EXTI0
+#define HAL_DMAMUX2_REQUEST_GEN_EXTI2              HAL_DMAMUX2_REQ_GEN_EXTI2
+#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT        HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT            HAL_DMAMUX2_REQ_GEN_SPI6_IT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
+#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT            HAL_DMAMUX2_REQ_GEN_ADC3_IT
+#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT      HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
+#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
+
+#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT            HAL_DMAMUX_REQ_GEN_NO_EVENT
+#define HAL_DMAMUX_REQUEST_GEN_RISING              HAL_DMAMUX_REQ_GEN_RISING
+#define HAL_DMAMUX_REQUEST_GEN_FALLING             HAL_DMAMUX_REQ_GEN_FALLING
+#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING      HAL_DMAMUX_REQ_GEN_RISING_FALLING
+
+#define DFSDM_FILTER_EXT_TRIG_LPTIM1               DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT
+#define DFSDM_FILTER_EXT_TRIG_LPTIM2               DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
+#define DFSDM_FILTER_EXT_TRIG_LPTIM3               DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
+
+#define DAC_TRIGGER_LP1_OUT                        DAC_TRIGGER_LPTIM1_OUT
+#define DAC_TRIGGER_LP2_OUT                        DAC_TRIGGER_LPTIM2_OUT
+
+#endif /* STM32H7 */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define TYPEPROGRAM_BYTE              FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_HALFWORD          FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_WORD              FLASH_TYPEPROGRAM_WORD
+#define TYPEPROGRAM_DOUBLEWORD        FLASH_TYPEPROGRAM_DOUBLEWORD
+#define TYPEERASE_SECTORS             FLASH_TYPEERASE_SECTORS
+#define TYPEERASE_PAGES               FLASH_TYPEERASE_PAGES
+#define TYPEERASE_PAGEERASE           FLASH_TYPEERASE_PAGES
+#define TYPEERASE_MASSERASE           FLASH_TYPEERASE_MASSERASE
+#define WRPSTATE_DISABLE              OB_WRPSTATE_DISABLE
+#define WRPSTATE_ENABLE               OB_WRPSTATE_ENABLE
+#define HAL_FLASH_TIMEOUT_VALUE       FLASH_TIMEOUT_VALUE
+#define OBEX_PCROP                    OPTIONBYTE_PCROP
+#define OBEX_BOOTCONFIG               OPTIONBYTE_BOOTCONFIG
+#define PCROPSTATE_DISABLE            OB_PCROP_STATE_DISABLE
+#define PCROPSTATE_ENABLE             OB_PCROP_STATE_ENABLE
+#define TYPEERASEDATA_BYTE            FLASH_TYPEERASEDATA_BYTE
+#define TYPEERASEDATA_HALFWORD        FLASH_TYPEERASEDATA_HALFWORD
+#define TYPEERASEDATA_WORD            FLASH_TYPEERASEDATA_WORD
+#define TYPEPROGRAMDATA_BYTE          FLASH_TYPEPROGRAMDATA_BYTE
+#define TYPEPROGRAMDATA_HALFWORD      FLASH_TYPEPROGRAMDATA_HALFWORD
+#define TYPEPROGRAMDATA_WORD          FLASH_TYPEPROGRAMDATA_WORD
+#define TYPEPROGRAMDATA_FASTBYTE      FLASH_TYPEPROGRAMDATA_FASTBYTE
+#define TYPEPROGRAMDATA_FASTHALFWORD  FLASH_TYPEPROGRAMDATA_FASTHALFWORD
+#define TYPEPROGRAMDATA_FASTWORD      FLASH_TYPEPROGRAMDATA_FASTWORD
+#define PAGESIZE                      FLASH_PAGE_SIZE
+#define TYPEPROGRAM_FASTBYTE          FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_FASTHALFWORD      FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_FASTWORD          FLASH_TYPEPROGRAM_WORD
+#define VOLTAGE_RANGE_1               FLASH_VOLTAGE_RANGE_1
+#define VOLTAGE_RANGE_2               FLASH_VOLTAGE_RANGE_2
+#define VOLTAGE_RANGE_3               FLASH_VOLTAGE_RANGE_3
+#define VOLTAGE_RANGE_4               FLASH_VOLTAGE_RANGE_4
+#define TYPEPROGRAM_FAST              FLASH_TYPEPROGRAM_FAST
+#define TYPEPROGRAM_FAST_AND_LAST     FLASH_TYPEPROGRAM_FAST_AND_LAST
+#define WRPAREA_BANK1_AREAA           OB_WRPAREA_BANK1_AREAA
+#define WRPAREA_BANK1_AREAB           OB_WRPAREA_BANK1_AREAB
+#define WRPAREA_BANK2_AREAA           OB_WRPAREA_BANK2_AREAA
+#define WRPAREA_BANK2_AREAB           OB_WRPAREA_BANK2_AREAB
+#define IWDG_STDBY_FREEZE             OB_IWDG_STDBY_FREEZE
+#define IWDG_STDBY_ACTIVE             OB_IWDG_STDBY_RUN
+#define IWDG_STOP_FREEZE              OB_IWDG_STOP_FREEZE
+#define IWDG_STOP_ACTIVE              OB_IWDG_STOP_RUN
+#define FLASH_ERROR_NONE              HAL_FLASH_ERROR_NONE
+#define FLASH_ERROR_RD                HAL_FLASH_ERROR_RD
+#define FLASH_ERROR_PG                HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_PGP               HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_WRP               HAL_FLASH_ERROR_WRP
+#define FLASH_ERROR_OPTV              HAL_FLASH_ERROR_OPTV
+#define FLASH_ERROR_OPTVUSR           HAL_FLASH_ERROR_OPTVUSR
+#define FLASH_ERROR_PROG              HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_OP                HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_PGA               HAL_FLASH_ERROR_PGA
+#define FLASH_ERROR_SIZE              HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_SIZ               HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_PGS               HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_MIS               HAL_FLASH_ERROR_MIS
+#define FLASH_ERROR_FAST              HAL_FLASH_ERROR_FAST
+#define FLASH_ERROR_FWWERR            HAL_FLASH_ERROR_FWWERR
+#define FLASH_ERROR_NOTZERO           HAL_FLASH_ERROR_NOTZERO
+#define FLASH_ERROR_OPERATION         HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_ERS               HAL_FLASH_ERROR_ERS
+#define OB_WDG_SW                     OB_IWDG_SW
+#define OB_WDG_HW                     OB_IWDG_HW
+#define OB_SDADC12_VDD_MONITOR_SET    OB_SDACD_VDD_MONITOR_SET
+#define OB_SDADC12_VDD_MONITOR_RESET  OB_SDACD_VDD_MONITOR_RESET
+#define OB_RAM_PARITY_CHECK_SET       OB_SRAM_PARITY_SET
+#define OB_RAM_PARITY_CHECK_RESET     OB_SRAM_PARITY_RESET
+#define IS_OB_SDADC12_VDD_MONITOR     IS_OB_SDACD_VDD_MONITOR
+#define OB_RDP_LEVEL0                 OB_RDP_LEVEL_0
+#define OB_RDP_LEVEL1                 OB_RDP_LEVEL_1
+#define OB_RDP_LEVEL2                 OB_RDP_LEVEL_2
+#if defined(STM32G0)
+#define OB_BOOT_LOCK_DISABLE          OB_BOOT_ENTRY_FORCED_NONE
+#define OB_BOOT_LOCK_ENABLE           OB_BOOT_ENTRY_FORCED_FLASH
+#else
+#define OB_BOOT_ENTRY_FORCED_NONE     OB_BOOT_LOCK_DISABLE
+#define OB_BOOT_ENTRY_FORCED_FLASH    OB_BOOT_LOCK_ENABLE
+#endif
+#if defined(STM32H7)
+#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1
+#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1
+#define FLASH_FLAG_STRBER_BANK1R  FLASH_FLAG_STRBERR_BANK1
+#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
+#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
+#define FLASH_FLAG_STRBER_BANK2R  FLASH_FLAG_STRBERR_BANK2
+#define FLASH_FLAG_WDW            FLASH_FLAG_WBNE
+#define OB_WRP_SECTOR_All         OB_WRP_SECTOR_ALL
+#endif /* STM32H7 */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#if defined(STM32H7)
+#define __HAL_RCC_JPEG_CLK_ENABLE               __HAL_RCC_JPGDECEN_CLK_ENABLE
+#define __HAL_RCC_JPEG_CLK_DISABLE              __HAL_RCC_JPGDECEN_CLK_DISABLE
+#define __HAL_RCC_JPEG_FORCE_RESET              __HAL_RCC_JPGDECRST_FORCE_RESET
+#define __HAL_RCC_JPEG_RELEASE_RESET            __HAL_RCC_JPGDECRST_RELEASE_RESET
+#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE         __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
+#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE        __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
+#endif /* STM32H7 */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9    I2C_FASTMODEPLUS_PA9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10   I2C_FASTMODEPLUS_PA10
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6    I2C_FASTMODEPLUS_PB6
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7    I2C_FASTMODEPLUS_PB7
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8    I2C_FASTMODEPLUS_PB8
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9    I2C_FASTMODEPLUS_PB9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C1       I2C_FASTMODEPLUS_I2C1
+#define HAL_SYSCFG_FASTMODEPLUS_I2C2       I2C_FASTMODEPLUS_I2C2
+#define HAL_SYSCFG_FASTMODEPLUS_I2C3       I2C_FASTMODEPLUS_I2C3
+#if defined(STM32G4)
+
+#define HAL_SYSCFG_EnableIOAnalogSwitchBooster    HAL_SYSCFG_EnableIOSwitchBooster
+#define HAL_SYSCFG_DisableIOAnalogSwitchBooster   HAL_SYSCFG_DisableIOSwitchBooster
+#define HAL_SYSCFG_EnableIOAnalogSwitchVDD        HAL_SYSCFG_EnableIOSwitchVDD
+#define HAL_SYSCFG_DisableIOAnalogSwitchVDD       HAL_SYSCFG_DisableIOSwitchVDD
+#endif /* STM32G4 */
+/**
+  * @}
+  */
+
+
+/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
+  * @{
+  */
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
+#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE       FMC_NAND_WAIT_FEATURE_DISABLE
+#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE        FMC_NAND_WAIT_FEATURE_ENABLE
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_8            FMC_NAND_MEM_BUS_WIDTH_8
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_16           FMC_NAND_MEM_BUS_WIDTH_16
+#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4)
+#define FMC_NAND_WAIT_FEATURE_DISABLE           FMC_NAND_PCC_WAIT_FEATURE_DISABLE
+#define FMC_NAND_WAIT_FEATURE_ENABLE            FMC_NAND_PCC_WAIT_FEATURE_ENABLE
+#define FMC_NAND_MEM_BUS_WIDTH_8                FMC_NAND_PCC_MEM_BUS_WIDTH_8
+#define FMC_NAND_MEM_BUS_WIDTH_16               FMC_NAND_PCC_MEM_BUS_WIDTH_16
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define FSMC_NORSRAM_TYPEDEF                      FSMC_NORSRAM_TypeDef
+#define FSMC_NORSRAM_EXTENDED_TYPEDEF             FSMC_NORSRAM_EXTENDED_TypeDef
+/**
+  * @}
+  */
+
+/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define GET_GPIO_SOURCE                           GPIO_GET_INDEX
+#define GET_GPIO_INDEX                            GPIO_GET_INDEX
+
+#if defined(STM32F4)
+#define GPIO_AF12_SDMMC                           GPIO_AF12_SDIO
+#define GPIO_AF12_SDMMC1                          GPIO_AF12_SDIO
+#endif
+
+#if defined(STM32F7)
+#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1
+#endif
+
+#if defined(STM32L4)
+#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1
+#endif
+
+#if defined(STM32H7)
+#define GPIO_AF7_SDIO1                            GPIO_AF7_SDMMC1
+#define GPIO_AF8_SDIO1                            GPIO_AF8_SDMMC1
+#define GPIO_AF12_SDIO1                           GPIO_AF12_SDMMC1
+#define GPIO_AF9_SDIO2                            GPIO_AF9_SDMMC2
+#define GPIO_AF10_SDIO2                           GPIO_AF10_SDMMC2
+#define GPIO_AF11_SDIO2                           GPIO_AF11_SDMMC2
+
+#if defined (STM32H743xx) || defined (STM32H753xx)  || defined (STM32H750xx) || defined (STM32H742xx) || \
+    defined (STM32H745xx) || defined (STM32H755xx)  || defined (STM32H747xx) || defined (STM32H757xx)
+#define GPIO_AF10_OTG2_HS  GPIO_AF10_OTG2_FS
+#define GPIO_AF10_OTG1_FS  GPIO_AF10_OTG1_HS
+#define GPIO_AF12_OTG2_FS  GPIO_AF12_OTG1_FS
+#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
+#endif /* STM32H7 */
+
+#define GPIO_AF0_LPTIM                            GPIO_AF0_LPTIM1
+#define GPIO_AF1_LPTIM                            GPIO_AF1_LPTIM1
+#define GPIO_AF2_LPTIM                            GPIO_AF2_LPTIM1
+
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7)
+#define  GPIO_SPEED_LOW                           GPIO_SPEED_FREQ_LOW
+#define  GPIO_SPEED_MEDIUM                        GPIO_SPEED_FREQ_MEDIUM
+#define  GPIO_SPEED_FAST                          GPIO_SPEED_FREQ_HIGH
+#define  GPIO_SPEED_HIGH                          GPIO_SPEED_FREQ_VERY_HIGH
+#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/
+
+#if defined(STM32L1)
+ #define  GPIO_SPEED_VERY_LOW    GPIO_SPEED_FREQ_LOW
+ #define  GPIO_SPEED_LOW         GPIO_SPEED_FREQ_MEDIUM
+ #define  GPIO_SPEED_MEDIUM      GPIO_SPEED_FREQ_HIGH
+ #define  GPIO_SPEED_HIGH        GPIO_SPEED_FREQ_VERY_HIGH
+#endif /* STM32L1 */
+
+#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
+ #define  GPIO_SPEED_LOW    GPIO_SPEED_FREQ_LOW
+ #define  GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
+ #define  GPIO_SPEED_HIGH   GPIO_SPEED_FREQ_HIGH
+#endif /* STM32F0 || STM32F3 || STM32F1 */
+
+#define GPIO_AF6_DFSDM                            GPIO_AF6_DFSDM1
+/**
+  * @}
+  */
+
+/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define HRTIM_TIMDELAYEDPROTECTION_DISABLED           HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
+
+#define __HAL_HRTIM_SetCounter        __HAL_HRTIM_SETCOUNTER
+#define __HAL_HRTIM_GetCounter        __HAL_HRTIM_GETCOUNTER
+#define __HAL_HRTIM_SetPeriod         __HAL_HRTIM_SETPERIOD
+#define __HAL_HRTIM_GetPeriod         __HAL_HRTIM_GETPERIOD
+#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
+#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
+#define __HAL_HRTIM_SetCompare        __HAL_HRTIM_SETCOMPARE
+#define __HAL_HRTIM_GetCompare        __HAL_HRTIM_GETCOMPARE
+
+#if defined(STM32G4)
+#define HAL_HRTIM_ExternalEventCounterConfig    HAL_HRTIM_ExtEventCounterConfig
+#define HAL_HRTIM_ExternalEventCounterEnable    HAL_HRTIM_ExtEventCounterEnable
+#define HAL_HRTIM_ExternalEventCounterDisable   HAL_HRTIM_ExtEventCounterDisable
+#define HAL_HRTIM_ExternalEventCounterReset     HAL_HRTIM_ExtEventCounterReset
+#endif /* STM32G4 */
+
+#if defined(STM32H7)
+#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
+
+#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
+#endif /* STM32H7 */
+
+#if defined(STM32F3)
+/** @brief Constants defining available sources associated to external events.
+  */
+#define HRTIM_EVENTSRC_1              (0x00000000U)
+#define HRTIM_EVENTSRC_2              (HRTIM_EECR1_EE1SRC_0)
+#define HRTIM_EVENTSRC_3              (HRTIM_EECR1_EE1SRC_1)
+#define HRTIM_EVENTSRC_4              (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
+
+/** @brief Constants defining the events that can be selected to configure the
+  *        set/reset crossbar of a timer output
+  */
+#define HRTIM_OUTPUTSET_TIMEV_1       (HRTIM_SET1R_TIMEVNT1)
+#define HRTIM_OUTPUTSET_TIMEV_2       (HRTIM_SET1R_TIMEVNT2)
+#define HRTIM_OUTPUTSET_TIMEV_3       (HRTIM_SET1R_TIMEVNT3)
+#define HRTIM_OUTPUTSET_TIMEV_4       (HRTIM_SET1R_TIMEVNT4)
+#define HRTIM_OUTPUTSET_TIMEV_5       (HRTIM_SET1R_TIMEVNT5)
+#define HRTIM_OUTPUTSET_TIMEV_6       (HRTIM_SET1R_TIMEVNT6)
+#define HRTIM_OUTPUTSET_TIMEV_7       (HRTIM_SET1R_TIMEVNT7)
+#define HRTIM_OUTPUTSET_TIMEV_8       (HRTIM_SET1R_TIMEVNT8)
+#define HRTIM_OUTPUTSET_TIMEV_9       (HRTIM_SET1R_TIMEVNT9)
+
+#define HRTIM_OUTPUTRESET_TIMEV_1     (HRTIM_RST1R_TIMEVNT1)
+#define HRTIM_OUTPUTRESET_TIMEV_2     (HRTIM_RST1R_TIMEVNT2)
+#define HRTIM_OUTPUTRESET_TIMEV_3     (HRTIM_RST1R_TIMEVNT3)
+#define HRTIM_OUTPUTRESET_TIMEV_4     (HRTIM_RST1R_TIMEVNT4)
+#define HRTIM_OUTPUTRESET_TIMEV_5     (HRTIM_RST1R_TIMEVNT5)
+#define HRTIM_OUTPUTRESET_TIMEV_6     (HRTIM_RST1R_TIMEVNT6)
+#define HRTIM_OUTPUTRESET_TIMEV_7     (HRTIM_RST1R_TIMEVNT7)
+#define HRTIM_OUTPUTRESET_TIMEV_8     (HRTIM_RST1R_TIMEVNT8)
+#define HRTIM_OUTPUTRESET_TIMEV_9     (HRTIM_RST1R_TIMEVNT9)
+
+/** @brief Constants defining the event filtering applied to external events
+  *        by a timer
+  */
+#define HRTIM_TIMEVENTFILTER_NONE             (0x00000000U)
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1     (HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2     (HRTIM_EEFR1_EE1FLTR_1)
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3     (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4     (HRTIM_EEFR1_EE1FLTR_2)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4    (HRTIM_EEFR1_EE1FLTR_3)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)
+#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
+#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM     (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
+
+/** @brief Constants defining the DLL calibration periods (in micro seconds)
+  */
+#define HRTIM_CALIBRATIONRATE_7300             0x00000000U
+#define HRTIM_CALIBRATIONRATE_910              (HRTIM_DLLCR_CALRTE_0)
+#define HRTIM_CALIBRATIONRATE_114              (HRTIM_DLLCR_CALRTE_1)
+#define HRTIM_CALIBRATIONRATE_14               (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
+
+#endif /* STM32F3 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define I2C_DUALADDRESS_DISABLED                I2C_DUALADDRESS_DISABLE
+#define I2C_DUALADDRESS_ENABLED                 I2C_DUALADDRESS_ENABLE
+#define I2C_GENERALCALL_DISABLED                I2C_GENERALCALL_DISABLE
+#define I2C_GENERALCALL_ENABLED                 I2C_GENERALCALL_ENABLE
+#define I2C_NOSTRETCH_DISABLED                  I2C_NOSTRETCH_DISABLE
+#define I2C_NOSTRETCH_ENABLED                   I2C_NOSTRETCH_ENABLE
+#define I2C_ANALOGFILTER_ENABLED                I2C_ANALOGFILTER_ENABLE
+#define I2C_ANALOGFILTER_DISABLED               I2C_ANALOGFILTER_DISABLE
+#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
+#define HAL_I2C_STATE_MEM_BUSY_TX               HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_MEM_BUSY_RX               HAL_I2C_STATE_BUSY_RX
+#define HAL_I2C_STATE_MASTER_BUSY_TX            HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_MASTER_BUSY_RX            HAL_I2C_STATE_BUSY_RX
+#define HAL_I2C_STATE_SLAVE_BUSY_TX             HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_SLAVE_BUSY_RX             HAL_I2C_STATE_BUSY_RX
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define IRDA_ONE_BIT_SAMPLE_DISABLED            IRDA_ONE_BIT_SAMPLE_DISABLE
+#define IRDA_ONE_BIT_SAMPLE_ENABLED             IRDA_ONE_BIT_SAMPLE_ENABLE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define KR_KEY_RELOAD                   IWDG_KEY_RELOAD
+#define KR_KEY_ENABLE                   IWDG_KEY_ENABLE
+#define KR_KEY_EWA                      IWDG_KEY_WRITE_ACCESS_ENABLE
+#define KR_KEY_DWA                      IWDG_KEY_WRITE_ACCESS_DISABLE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
+
+#define LPTIM_CLOCKPOLARITY_RISINGEDGE          LPTIM_CLOCKPOLARITY_RISING
+#define LPTIM_CLOCKPOLARITY_FALLINGEDGE         LPTIM_CLOCKPOLARITY_FALLING
+#define LPTIM_CLOCKPOLARITY_BOTHEDGES           LPTIM_CLOCKPOLARITY_RISING_FALLING
+
+#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION  LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS      LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS      LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS      LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+/* The following 3 definition have also been present in a temporary version of lptim.h */
+/* They need to be renamed also to the right name, just in case */
+#define LPTIM_TRIGSAMPLETIME_2TRANSITION        LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSITION        LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSITION        LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define HAL_NAND_Read_Page              HAL_NAND_Read_Page_8b
+#define HAL_NAND_Write_Page             HAL_NAND_Write_Page_8b
+#define HAL_NAND_Read_SpareArea         HAL_NAND_Read_SpareArea_8b
+#define HAL_NAND_Write_SpareArea        HAL_NAND_Write_SpareArea_8b
+
+#define NAND_AddressTypedef             NAND_AddressTypeDef
+
+#define __ARRAY_ADDRESS                 ARRAY_ADDRESS
+#define __ADDR_1st_CYCLE                ADDR_1ST_CYCLE
+#define __ADDR_2nd_CYCLE                ADDR_2ND_CYCLE
+#define __ADDR_3rd_CYCLE                ADDR_3RD_CYCLE
+#define __ADDR_4th_CYCLE                ADDR_4TH_CYCLE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define NOR_StatusTypedef              HAL_NOR_StatusTypeDef
+#define NOR_SUCCESS                    HAL_NOR_STATUS_SUCCESS
+#define NOR_ONGOING                    HAL_NOR_STATUS_ONGOING
+#define NOR_ERROR                      HAL_NOR_STATUS_ERROR
+#define NOR_TIMEOUT                    HAL_NOR_STATUS_TIMEOUT
+
+#define __NOR_WRITE                    NOR_WRITE
+#define __NOR_ADDR_SHIFT               NOR_ADDR_SHIFT
+/**
+  * @}
+  */
+
+/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define OPAMP_NONINVERTINGINPUT_VP0           OPAMP_NONINVERTINGINPUT_IO0
+#define OPAMP_NONINVERTINGINPUT_VP1           OPAMP_NONINVERTINGINPUT_IO1
+#define OPAMP_NONINVERTINGINPUT_VP2           OPAMP_NONINVERTINGINPUT_IO2
+#define OPAMP_NONINVERTINGINPUT_VP3           OPAMP_NONINVERTINGINPUT_IO3
+
+#define OPAMP_SEC_NONINVERTINGINPUT_VP0       OPAMP_SEC_NONINVERTINGINPUT_IO0
+#define OPAMP_SEC_NONINVERTINGINPUT_VP1       OPAMP_SEC_NONINVERTINGINPUT_IO1
+#define OPAMP_SEC_NONINVERTINGINPUT_VP2       OPAMP_SEC_NONINVERTINGINPUT_IO2
+#define OPAMP_SEC_NONINVERTINGINPUT_VP3       OPAMP_SEC_NONINVERTINGINPUT_IO3
+
+#define OPAMP_INVERTINGINPUT_VM0              OPAMP_INVERTINGINPUT_IO0
+#define OPAMP_INVERTINGINPUT_VM1              OPAMP_INVERTINGINPUT_IO1
+
+#define IOPAMP_INVERTINGINPUT_VM0             OPAMP_INVERTINGINPUT_IO0
+#define IOPAMP_INVERTINGINPUT_VM1             OPAMP_INVERTINGINPUT_IO1
+
+#define OPAMP_SEC_INVERTINGINPUT_VM0          OPAMP_SEC_INVERTINGINPUT_IO0
+#define OPAMP_SEC_INVERTINGINPUT_VM1          OPAMP_SEC_INVERTINGINPUT_IO1
+
+#define OPAMP_INVERTINGINPUT_VINM             OPAMP_SEC_INVERTINGINPUT_IO1
+
+#define OPAMP_PGACONNECT_NO                   OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
+#define OPAMP_PGACONNECT_VM0                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
+#define OPAMP_PGACONNECT_VM1                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
+
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
+#define HAL_OPAMP_MSP_INIT_CB_ID       HAL_OPAMP_MSPINIT_CB_ID
+#define HAL_OPAMP_MSP_DEINIT_CB_ID     HAL_OPAMP_MSPDEINIT_CB_ID
+#endif
+
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define I2S_STANDARD_PHILLIPS      I2S_STANDARD_PHILIPS
+
+#if defined(STM32H7)
+  #define I2S_IT_TXE               I2S_IT_TXP
+  #define I2S_IT_RXNE              I2S_IT_RXP
+
+  #define I2S_FLAG_TXE             I2S_FLAG_TXP
+  #define I2S_FLAG_RXNE            I2S_FLAG_RXP
+#endif
+
+#if defined(STM32F7)
+  #define I2S_CLOCK_SYSCLK           I2S_CLOCK_PLL
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+/* Compact Flash-ATA registers description */
+#define CF_DATA                       ATA_DATA
+#define CF_SECTOR_COUNT               ATA_SECTOR_COUNT
+#define CF_SECTOR_NUMBER              ATA_SECTOR_NUMBER
+#define CF_CYLINDER_LOW               ATA_CYLINDER_LOW
+#define CF_CYLINDER_HIGH              ATA_CYLINDER_HIGH
+#define CF_CARD_HEAD                  ATA_CARD_HEAD
+#define CF_STATUS_CMD                 ATA_STATUS_CMD
+#define CF_STATUS_CMD_ALTERNATE       ATA_STATUS_CMD_ALTERNATE
+#define CF_COMMON_DATA_AREA           ATA_COMMON_DATA_AREA
+
+/* Compact Flash-ATA commands */
+#define CF_READ_SECTOR_CMD            ATA_READ_SECTOR_CMD
+#define CF_WRITE_SECTOR_CMD           ATA_WRITE_SECTOR_CMD
+#define CF_ERASE_SECTOR_CMD           ATA_ERASE_SECTOR_CMD
+#define CF_IDENTIFY_CMD               ATA_IDENTIFY_CMD
+
+#define PCCARD_StatusTypedef          HAL_PCCARD_StatusTypeDef
+#define PCCARD_SUCCESS                HAL_PCCARD_STATUS_SUCCESS
+#define PCCARD_ONGOING                HAL_PCCARD_STATUS_ONGOING
+#define PCCARD_ERROR                  HAL_PCCARD_STATUS_ERROR
+#define PCCARD_TIMEOUT                HAL_PCCARD_STATUS_TIMEOUT
+/**
+  * @}
+  */
+  
+/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define FORMAT_BIN                  RTC_FORMAT_BIN
+#define FORMAT_BCD                  RTC_FORMAT_BCD
+
+#define RTC_ALARMSUBSECONDMASK_None     RTC_ALARMSUBSECONDMASK_NONE
+#define RTC_TAMPERERASEBACKUP_DISABLED  RTC_TAMPER_ERASE_BACKUP_DISABLE
+#define RTC_TAMPERMASK_FLAG_DISABLED    RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_TAMPERMASK_FLAG_ENABLED     RTC_TAMPERMASK_FLAG_ENABLE
+
+#define RTC_MASKTAMPERFLAG_DISABLED     RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE
+#define RTC_TAMPERERASEBACKUP_ENABLED   RTC_TAMPER_ERASE_BACKUP_ENABLE
+#define RTC_TAMPER1_2_INTERRUPT         RTC_ALL_TAMPER_INTERRUPT
+#define RTC_TAMPER1_2_3_INTERRUPT       RTC_ALL_TAMPER_INTERRUPT
+
+#define RTC_TIMESTAMPPIN_PC13  RTC_TIMESTAMPPIN_DEFAULT
+#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PC1   RTC_TIMESTAMPPIN_POS2
+
+#define RTC_OUTPUT_REMAP_PC13  RTC_OUTPUT_REMAP_NONE
+#define RTC_OUTPUT_REMAP_PB14  RTC_OUTPUT_REMAP_POS1
+#define RTC_OUTPUT_REMAP_PB2   RTC_OUTPUT_REMAP_POS1
+
+#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
+#define RTC_TAMPERPIN_PA0  RTC_TAMPERPIN_POS1
+#define RTC_TAMPERPIN_PI8  RTC_TAMPERPIN_POS1
+
+#if defined(STM32H7)
+#define RTC_TAMPCR_TAMPXE          RTC_TAMPER_X
+#define RTC_TAMPCR_TAMPXIE         RTC_TAMPER_X_INTERRUPT
+
+#define RTC_TAMPER1_INTERRUPT      RTC_IT_TAMP1
+#define RTC_TAMPER2_INTERRUPT      RTC_IT_TAMP2
+#define RTC_TAMPER3_INTERRUPT      RTC_IT_TAMP3
+#define RTC_ALL_TAMPER_INTERRUPT   RTC_IT_TAMPALL
+#endif /* STM32H7 */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define SMARTCARD_NACK_ENABLED                  SMARTCARD_NACK_ENABLE
+#define SMARTCARD_NACK_DISABLED                 SMARTCARD_NACK_DISABLE
+
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLED      SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLED       SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLE       SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLE        SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+
+#define SMARTCARD_TIMEOUT_DISABLED              SMARTCARD_TIMEOUT_DISABLE
+#define SMARTCARD_TIMEOUT_ENABLED               SMARTCARD_TIMEOUT_ENABLE
+
+#define SMARTCARD_LASTBIT_DISABLED              SMARTCARD_LASTBIT_DISABLE
+#define SMARTCARD_LASTBIT_ENABLED               SMARTCARD_LASTBIT_ENABLE
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define SMBUS_DUALADDRESS_DISABLED      SMBUS_DUALADDRESS_DISABLE
+#define SMBUS_DUALADDRESS_ENABLED       SMBUS_DUALADDRESS_ENABLE
+#define SMBUS_GENERALCALL_DISABLED      SMBUS_GENERALCALL_DISABLE
+#define SMBUS_GENERALCALL_ENABLED       SMBUS_GENERALCALL_ENABLE
+#define SMBUS_NOSTRETCH_DISABLED        SMBUS_NOSTRETCH_DISABLE
+#define SMBUS_NOSTRETCH_ENABLED         SMBUS_NOSTRETCH_ENABLE
+#define SMBUS_ANALOGFILTER_ENABLED      SMBUS_ANALOGFILTER_ENABLE
+#define SMBUS_ANALOGFILTER_DISABLED     SMBUS_ANALOGFILTER_DISABLE
+#define SMBUS_PEC_DISABLED              SMBUS_PEC_DISABLE
+#define SMBUS_PEC_ENABLED               SMBUS_PEC_ENABLE
+#define HAL_SMBUS_STATE_SLAVE_LISTEN    HAL_SMBUS_STATE_LISTEN
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define SPI_TIMODE_DISABLED             SPI_TIMODE_DISABLE
+#define SPI_TIMODE_ENABLED              SPI_TIMODE_ENABLE
+
+#define SPI_CRCCALCULATION_DISABLED     SPI_CRCCALCULATION_DISABLE
+#define SPI_CRCCALCULATION_ENABLED      SPI_CRCCALCULATION_ENABLE
+
+#define SPI_NSS_PULSE_DISABLED          SPI_NSS_PULSE_DISABLE
+#define SPI_NSS_PULSE_ENABLED           SPI_NSS_PULSE_ENABLE
+
+#if defined(STM32H7)
+
+ #define SPI_FLAG_TXE                    SPI_FLAG_TXP
+ #define SPI_FLAG_RXNE                   SPI_FLAG_RXP
+
+ #define SPI_IT_TXE                      SPI_IT_TXP
+ #define SPI_IT_RXNE                     SPI_IT_RXP
+
+ #define SPI_FRLVL_EMPTY                 SPI_RX_FIFO_0PACKET
+ #define SPI_FRLVL_QUARTER_FULL          SPI_RX_FIFO_1PACKET
+ #define SPI_FRLVL_HALF_FULL             SPI_RX_FIFO_2PACKET
+ #define SPI_FRLVL_FULL                  SPI_RX_FIFO_3PACKET
+
+#endif /* STM32H7 */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define CCER_CCxE_MASK                   TIM_CCER_CCxE_MASK
+#define CCER_CCxNE_MASK                  TIM_CCER_CCxNE_MASK
+
+#define TIM_DMABase_CR1                  TIM_DMABASE_CR1
+#define TIM_DMABase_CR2                  TIM_DMABASE_CR2
+#define TIM_DMABase_SMCR                 TIM_DMABASE_SMCR
+#define TIM_DMABase_DIER                 TIM_DMABASE_DIER
+#define TIM_DMABase_SR                   TIM_DMABASE_SR
+#define TIM_DMABase_EGR                  TIM_DMABASE_EGR
+#define TIM_DMABase_CCMR1                TIM_DMABASE_CCMR1
+#define TIM_DMABase_CCMR2                TIM_DMABASE_CCMR2
+#define TIM_DMABase_CCER                 TIM_DMABASE_CCER
+#define TIM_DMABase_CNT                  TIM_DMABASE_CNT
+#define TIM_DMABase_PSC                  TIM_DMABASE_PSC
+#define TIM_DMABase_ARR                  TIM_DMABASE_ARR
+#define TIM_DMABase_RCR                  TIM_DMABASE_RCR
+#define TIM_DMABase_CCR1                 TIM_DMABASE_CCR1
+#define TIM_DMABase_CCR2                 TIM_DMABASE_CCR2
+#define TIM_DMABase_CCR3                 TIM_DMABASE_CCR3
+#define TIM_DMABase_CCR4                 TIM_DMABASE_CCR4
+#define TIM_DMABase_BDTR                 TIM_DMABASE_BDTR
+#define TIM_DMABase_DCR                  TIM_DMABASE_DCR
+#define TIM_DMABase_DMAR                 TIM_DMABASE_DMAR
+#define TIM_DMABase_OR1                  TIM_DMABASE_OR1
+#define TIM_DMABase_CCMR3                TIM_DMABASE_CCMR3
+#define TIM_DMABase_CCR5                 TIM_DMABASE_CCR5
+#define TIM_DMABase_CCR6                 TIM_DMABASE_CCR6
+#define TIM_DMABase_OR2                  TIM_DMABASE_OR2
+#define TIM_DMABase_OR3                  TIM_DMABASE_OR3
+#define TIM_DMABase_OR                   TIM_DMABASE_OR
+
+#define TIM_EventSource_Update           TIM_EVENTSOURCE_UPDATE
+#define TIM_EventSource_CC1              TIM_EVENTSOURCE_CC1
+#define TIM_EventSource_CC2              TIM_EVENTSOURCE_CC2
+#define TIM_EventSource_CC3              TIM_EVENTSOURCE_CC3
+#define TIM_EventSource_CC4              TIM_EVENTSOURCE_CC4
+#define TIM_EventSource_COM              TIM_EVENTSOURCE_COM
+#define TIM_EventSource_Trigger          TIM_EVENTSOURCE_TRIGGER
+#define TIM_EventSource_Break            TIM_EVENTSOURCE_BREAK
+#define TIM_EventSource_Break2           TIM_EVENTSOURCE_BREAK2
+
+#define TIM_DMABurstLength_1Transfer     TIM_DMABURSTLENGTH_1TRANSFER
+#define TIM_DMABurstLength_2Transfers    TIM_DMABURSTLENGTH_2TRANSFERS
+#define TIM_DMABurstLength_3Transfers    TIM_DMABURSTLENGTH_3TRANSFERS
+#define TIM_DMABurstLength_4Transfers    TIM_DMABURSTLENGTH_4TRANSFERS
+#define TIM_DMABurstLength_5Transfers    TIM_DMABURSTLENGTH_5TRANSFERS
+#define TIM_DMABurstLength_6Transfers    TIM_DMABURSTLENGTH_6TRANSFERS
+#define TIM_DMABurstLength_7Transfers    TIM_DMABURSTLENGTH_7TRANSFERS
+#define TIM_DMABurstLength_8Transfers    TIM_DMABURSTLENGTH_8TRANSFERS
+#define TIM_DMABurstLength_9Transfers    TIM_DMABURSTLENGTH_9TRANSFERS
+#define TIM_DMABurstLength_10Transfers   TIM_DMABURSTLENGTH_10TRANSFERS
+#define TIM_DMABurstLength_11Transfers   TIM_DMABURSTLENGTH_11TRANSFERS
+#define TIM_DMABurstLength_12Transfers   TIM_DMABURSTLENGTH_12TRANSFERS
+#define TIM_DMABurstLength_13Transfers   TIM_DMABURSTLENGTH_13TRANSFERS
+#define TIM_DMABurstLength_14Transfers   TIM_DMABURSTLENGTH_14TRANSFERS
+#define TIM_DMABurstLength_15Transfers   TIM_DMABURSTLENGTH_15TRANSFERS
+#define TIM_DMABurstLength_16Transfers   TIM_DMABURSTLENGTH_16TRANSFERS
+#define TIM_DMABurstLength_17Transfers   TIM_DMABURSTLENGTH_17TRANSFERS
+#define TIM_DMABurstLength_18Transfers   TIM_DMABURSTLENGTH_18TRANSFERS
+
+#if defined(STM32L0)
+#define TIM22_TI1_GPIO1   TIM22_TI1_GPIO
+#define TIM22_TI1_GPIO2   TIM22_TI1_GPIO
+#endif
+
+#if defined(STM32F3)
+#define IS_TIM_HALL_INTERFACE_INSTANCE   IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
+#endif
+
+#if defined(STM32H7)
+#define TIM_TIM1_ETR_COMP1_OUT        TIM_TIM1_ETR_COMP1
+#define TIM_TIM1_ETR_COMP2_OUT        TIM_TIM1_ETR_COMP2
+#define TIM_TIM8_ETR_COMP1_OUT        TIM_TIM8_ETR_COMP1
+#define TIM_TIM8_ETR_COMP2_OUT        TIM_TIM8_ETR_COMP2
+#define TIM_TIM2_ETR_COMP1_OUT        TIM_TIM2_ETR_COMP1
+#define TIM_TIM2_ETR_COMP2_OUT        TIM_TIM2_ETR_COMP2
+#define TIM_TIM3_ETR_COMP1_OUT        TIM_TIM3_ETR_COMP1
+#define TIM_TIM1_TI1_COMP1_OUT        TIM_TIM1_TI1_COMP1
+#define TIM_TIM8_TI1_COMP2_OUT        TIM_TIM8_TI1_COMP2
+#define TIM_TIM2_TI4_COMP1_OUT        TIM_TIM2_TI4_COMP1
+#define TIM_TIM2_TI4_COMP2_OUT        TIM_TIM2_TI4_COMP2
+#define TIM_TIM2_TI4_COMP1COMP2_OUT   TIM_TIM2_TI4_COMP1_COMP2
+#define TIM_TIM3_TI1_COMP1_OUT        TIM_TIM3_TI1_COMP1
+#define TIM_TIM3_TI1_COMP2_OUT        TIM_TIM3_TI1_COMP2
+#define TIM_TIM3_TI1_COMP1COMP2_OUT   TIM_TIM3_TI1_COMP1_COMP2
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define TSC_SYNC_POL_FALL        TSC_SYNC_POLARITY_FALLING
+#define TSC_SYNC_POL_RISE_HIGH   TSC_SYNC_POLARITY_RISING
+/**
+  * @}
+  */
+
+/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define UART_ONEBIT_SAMPLING_DISABLED   UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONEBIT_SAMPLING_ENABLED    UART_ONE_BIT_SAMPLE_ENABLE
+#define UART_ONE_BIT_SAMPLE_DISABLED    UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONE_BIT_SAMPLE_ENABLED     UART_ONE_BIT_SAMPLE_ENABLE
+
+#define __HAL_UART_ONEBIT_ENABLE        __HAL_UART_ONE_BIT_SAMPLE_ENABLE
+#define __HAL_UART_ONEBIT_DISABLE       __HAL_UART_ONE_BIT_SAMPLE_DISABLE
+
+#define __DIV_SAMPLING16                UART_DIV_SAMPLING16
+#define __DIVMANT_SAMPLING16            UART_DIVMANT_SAMPLING16
+#define __DIVFRAQ_SAMPLING16            UART_DIVFRAQ_SAMPLING16
+#define __UART_BRR_SAMPLING16           UART_BRR_SAMPLING16
+
+#define __DIV_SAMPLING8                 UART_DIV_SAMPLING8
+#define __DIVMANT_SAMPLING8             UART_DIVMANT_SAMPLING8
+#define __DIVFRAQ_SAMPLING8             UART_DIVFRAQ_SAMPLING8
+#define __UART_BRR_SAMPLING8            UART_BRR_SAMPLING8
+
+#define __DIV_LPUART                    UART_DIV_LPUART
+
+#define UART_WAKEUPMETHODE_IDLELINE     UART_WAKEUPMETHOD_IDLELINE
+#define UART_WAKEUPMETHODE_ADDRESSMARK  UART_WAKEUPMETHOD_ADDRESSMARK
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define USART_CLOCK_DISABLED            USART_CLOCK_DISABLE
+#define USART_CLOCK_ENABLED             USART_CLOCK_ENABLE
+
+#define USARTNACK_ENABLED               USART_NACK_ENABLE
+#define USARTNACK_DISABLED              USART_NACK_DISABLE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define CFR_BASE                    WWDG_CFR_BASE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define CAN_FilterFIFO0             CAN_FILTER_FIFO0
+#define CAN_FilterFIFO1             CAN_FILTER_FIFO1
+#define CAN_IT_RQCP0                CAN_IT_TME
+#define CAN_IT_RQCP1                CAN_IT_TME
+#define CAN_IT_RQCP2                CAN_IT_TME
+#define INAK_TIMEOUT                CAN_TIMEOUT_VALUE
+#define SLAK_TIMEOUT                CAN_TIMEOUT_VALUE
+#define CAN_TXSTATUS_FAILED         ((uint8_t)0x00U)
+#define CAN_TXSTATUS_OK             ((uint8_t)0x01U)
+#define CAN_TXSTATUS_PENDING        ((uint8_t)0x02U)
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define VLAN_TAG                ETH_VLAN_TAG
+#define MIN_ETH_PAYLOAD         ETH_MIN_ETH_PAYLOAD
+#define MAX_ETH_PAYLOAD         ETH_MAX_ETH_PAYLOAD
+#define JUMBO_FRAME_PAYLOAD     ETH_JUMBO_FRAME_PAYLOAD
+#define MACMIIAR_CR_MASK        ETH_MACMIIAR_CR_MASK
+#define MACCR_CLEAR_MASK        ETH_MACCR_CLEAR_MASK
+#define MACFCR_CLEAR_MASK       ETH_MACFCR_CLEAR_MASK
+#define DMAOMR_CLEAR_MASK       ETH_DMAOMR_CLEAR_MASK
+
+#define ETH_MMCCR              0x00000100U
+#define ETH_MMCRIR             0x00000104U
+#define ETH_MMCTIR             0x00000108U
+#define ETH_MMCRIMR            0x0000010CU
+#define ETH_MMCTIMR            0x00000110U
+#define ETH_MMCTGFSCCR         0x0000014CU
+#define ETH_MMCTGFMSCCR        0x00000150U
+#define ETH_MMCTGFCR           0x00000168U
+#define ETH_MMCRFCECR          0x00000194U
+#define ETH_MMCRFAECR          0x00000198U
+#define ETH_MMCRGUFCR          0x000001C4U
+
+#define ETH_MAC_TXFIFO_FULL                             0x02000000U  /* Tx FIFO full */
+#define ETH_MAC_TXFIFONOT_EMPTY                         0x01000000U  /* Tx FIFO not empty */
+#define ETH_MAC_TXFIFO_WRITE_ACTIVE                     0x00400000U  /* Tx FIFO write active */
+#define ETH_MAC_TXFIFO_IDLE                             0x00000000U  /* Tx FIFO read status: Idle */
+#define ETH_MAC_TXFIFO_READ                             0x00100000U  /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
+#define ETH_MAC_TXFIFO_WAITING                          0x00200000U  /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
+#define ETH_MAC_TXFIFO_WRITING                          0x00300000U  /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
+#define ETH_MAC_TRANSMISSION_PAUSE                      0x00080000U  /* MAC transmitter in pause */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE            0x00000000U  /* MAC transmit frame controller: Idle */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING         0x00020000U  /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF   0x00040000U  /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING    0x00060000U  /* MAC transmit frame controller: Transferring input frame for transmission */
+#define ETH_MAC_MII_TRANSMIT_ACTIVE           0x00010000U  /* MAC MII transmit engine active */
+#define ETH_MAC_RXFIFO_EMPTY                  0x00000000U  /* Rx FIFO fill level: empty */
+#define ETH_MAC_RXFIFO_BELOW_THRESHOLD        0x00000100U  /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
+#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD        0x00000200U  /* Rx FIFO fill level: fill-level above flow-control activate threshold */
+#define ETH_MAC_RXFIFO_FULL                   0x00000300U  /* Rx FIFO fill level: full */
+#if defined(STM32F1)
+#else
+#define ETH_MAC_READCONTROLLER_IDLE           0x00000000U  /* Rx FIFO read controller IDLE state */
+#define ETH_MAC_READCONTROLLER_READING_DATA   0x00000020U  /* Rx FIFO read controller Reading frame data */
+#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U  /* Rx FIFO read controller Reading frame status (or time-stamp) */
+#endif
+#define ETH_MAC_READCONTROLLER_FLUSHING       0x00000060U  /* Rx FIFO read controller Flushing the frame data and status */
+#define ETH_MAC_RXFIFO_WRITE_ACTIVE           0x00000010U  /* Rx FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_NOTACTIVE          0x00000000U  /* MAC small FIFO read / write controllers not active */
+#define ETH_MAC_SMALL_FIFO_READ_ACTIVE        0x00000002U  /* MAC small FIFO read controller active */
+#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE       0x00000004U  /* MAC small FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_RW_ACTIVE          0x00000006U  /* MAC small FIFO read / write controllers active */
+#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE   0x00000001U  /* MAC MII receive protocol engine active */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define HAL_DCMI_ERROR_OVF      HAL_DCMI_ERROR_OVR
+#define DCMI_IT_OVF             DCMI_IT_OVR
+#define DCMI_FLAG_OVFRI         DCMI_FLAG_OVRRI
+#define DCMI_FLAG_OVFMI         DCMI_FLAG_OVRMI
+
+#define HAL_DCMI_ConfigCROP     HAL_DCMI_ConfigCrop
+#define HAL_DCMI_EnableCROP     HAL_DCMI_EnableCrop
+#define HAL_DCMI_DisableCROP    HAL_DCMI_DisableCrop
+
+/**
+  * @}
+  */
+
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
+  || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
+  || defined(STM32H7)
+/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define DMA2D_ARGB8888          DMA2D_OUTPUT_ARGB8888
+#define DMA2D_RGB888            DMA2D_OUTPUT_RGB888
+#define DMA2D_RGB565            DMA2D_OUTPUT_RGB565
+#define DMA2D_ARGB1555          DMA2D_OUTPUT_ARGB1555
+#define DMA2D_ARGB4444          DMA2D_OUTPUT_ARGB4444
+
+#define CM_ARGB8888             DMA2D_INPUT_ARGB8888
+#define CM_RGB888               DMA2D_INPUT_RGB888
+#define CM_RGB565               DMA2D_INPUT_RGB565
+#define CM_ARGB1555             DMA2D_INPUT_ARGB1555
+#define CM_ARGB4444             DMA2D_INPUT_ARGB4444
+#define CM_L8                   DMA2D_INPUT_L8
+#define CM_AL44                 DMA2D_INPUT_AL44
+#define CM_AL88                 DMA2D_INPUT_AL88
+#define CM_L4                   DMA2D_INPUT_L4
+#define CM_A8                   DMA2D_INPUT_A8
+#define CM_A4                   DMA2D_INPUT_A4
+/**
+  * @}
+  */
+#endif  /* STM32L4 ||  STM32F7 ||  STM32F4 ||  STM32H7 */
+
+/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_CRYP_ComputationCpltCallback     HAL_CRYPEx_ComputationCpltCallback
+/**
+  * @}
+  */
+
+/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_HASH_STATETypeDef        HAL_HASH_StateTypeDef
+#define HAL_HASHPhaseTypeDef         HAL_HASH_PhaseTypeDef
+#define HAL_HMAC_MD5_Finish          HAL_HASH_MD5_Finish
+#define HAL_HMAC_SHA1_Finish         HAL_HASH_SHA1_Finish
+#define HAL_HMAC_SHA224_Finish       HAL_HASH_SHA224_Finish
+#define HAL_HMAC_SHA256_Finish       HAL_HASH_SHA256_Finish
+
+/*HASH Algorithm Selection*/
+
+#define HASH_AlgoSelection_SHA1      HASH_ALGOSELECTION_SHA1
+#define HASH_AlgoSelection_SHA224    HASH_ALGOSELECTION_SHA224
+#define HASH_AlgoSelection_SHA256    HASH_ALGOSELECTION_SHA256
+#define HASH_AlgoSelection_MD5       HASH_ALGOSELECTION_MD5
+
+#define HASH_AlgoMode_HASH         HASH_ALGOMODE_HASH
+#define HASH_AlgoMode_HMAC         HASH_ALGOMODE_HMAC
+
+#define HASH_HMACKeyType_ShortKey  HASH_HMAC_KEYTYPE_SHORTKEY
+#define HASH_HMACKeyType_LongKey   HASH_HMAC_KEYTYPE_LONGKEY
+
+#if defined(STM32L4) || defined(STM32L5) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
+
+#define HAL_HASH_MD5_Accumulate                HAL_HASH_MD5_Accmlt
+#define HAL_HASH_MD5_Accumulate_End            HAL_HASH_MD5_Accmlt_End
+#define HAL_HASH_MD5_Accumulate_IT             HAL_HASH_MD5_Accmlt_IT
+#define HAL_HASH_MD5_Accumulate_End_IT         HAL_HASH_MD5_Accmlt_End_IT
+
+#define HAL_HASH_SHA1_Accumulate               HAL_HASH_SHA1_Accmlt
+#define HAL_HASH_SHA1_Accumulate_End           HAL_HASH_SHA1_Accmlt_End
+#define HAL_HASH_SHA1_Accumulate_IT            HAL_HASH_SHA1_Accmlt_IT
+#define HAL_HASH_SHA1_Accumulate_End_IT        HAL_HASH_SHA1_Accmlt_End_IT
+
+#define HAL_HASHEx_SHA224_Accumulate           HAL_HASHEx_SHA224_Accmlt
+#define HAL_HASHEx_SHA224_Accumulate_End       HAL_HASHEx_SHA224_Accmlt_End
+#define HAL_HASHEx_SHA224_Accumulate_IT        HAL_HASHEx_SHA224_Accmlt_IT
+#define HAL_HASHEx_SHA224_Accumulate_End_IT    HAL_HASHEx_SHA224_Accmlt_End_IT
+
+#define HAL_HASHEx_SHA256_Accumulate           HAL_HASHEx_SHA256_Accmlt
+#define HAL_HASHEx_SHA256_Accumulate_End       HAL_HASHEx_SHA256_Accmlt_End
+#define HAL_HASHEx_SHA256_Accumulate_IT        HAL_HASHEx_SHA256_Accmlt_IT
+#define HAL_HASHEx_SHA256_Accumulate_End_IT    HAL_HASHEx_SHA256_Accmlt_End_IT
+
+#endif  /* STM32L4 || STM32L5 || STM32F4 || STM32F7 || STM32H7 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
+#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
+#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
+#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
+#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
+#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
+#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
+#define HAL_VREFINT_OutputSelect  HAL_SYSCFG_VREFINT_OutputSelect
+#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
+#if defined(STM32L0)
+#else
+#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
+#endif
+#define HAL_ADC_EnableBuffer_Cmd(cmd)  (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
+#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ?  HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
+#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
+#define HAL_EnableSRDomainDBGStopMode      HAL_EnableDomain3DBGStopMode
+#define HAL_DisableSRDomainDBGStopMode     HAL_DisableDomain3DBGStopMode
+#define HAL_EnableSRDomainDBGStandbyMode   HAL_EnableDomain3DBGStandbyMode
+#define HAL_DisableSRDomainDBGStandbyMode  HAL_DisableDomain3DBGStandbyMode
+#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ  || STM32H7B0xxQ */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define FLASH_HalfPageProgram      HAL_FLASHEx_HalfPageProgram
+#define FLASH_EnableRunPowerDown   HAL_FLASHEx_EnableRunPowerDown
+#define FLASH_DisableRunPowerDown  HAL_FLASHEx_DisableRunPowerDown
+#define HAL_DATA_EEPROMEx_Unlock   HAL_FLASHEx_DATAEEPROM_Unlock
+#define HAL_DATA_EEPROMEx_Lock     HAL_FLASHEx_DATAEEPROM_Lock
+#define HAL_DATA_EEPROMEx_Erase    HAL_FLASHEx_DATAEEPROM_Erase
+#define HAL_DATA_EEPROMEx_Program  HAL_FLASHEx_DATAEEPROM_Program
+
+ /**
+  * @}
+  */
+
+/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_I2CEx_AnalogFilter_Config         HAL_I2CEx_ConfigAnalogFilter
+#define HAL_I2CEx_DigitalFilter_Config        HAL_I2CEx_ConfigDigitalFilter
+#define HAL_FMPI2CEx_AnalogFilter_Config      HAL_FMPI2CEx_ConfigAnalogFilter
+#define HAL_FMPI2CEx_DigitalFilter_Config     HAL_FMPI2CEx_ConfigDigitalFilter
+
+#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
+
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)
+#define HAL_I2C_Master_Sequential_Transmit_IT  HAL_I2C_Master_Seq_Transmit_IT
+#define HAL_I2C_Master_Sequential_Receive_IT   HAL_I2C_Master_Seq_Receive_IT
+#define HAL_I2C_Slave_Sequential_Transmit_IT   HAL_I2C_Slave_Seq_Transmit_IT
+#define HAL_I2C_Slave_Sequential_Receive_IT    HAL_I2C_Slave_Seq_Receive_IT
+#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)
+#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
+#define HAL_I2C_Master_Sequential_Receive_DMA  HAL_I2C_Master_Seq_Receive_DMA
+#define HAL_I2C_Slave_Sequential_Transmit_DMA  HAL_I2C_Slave_Seq_Transmit_DMA
+#define HAL_I2C_Slave_Sequential_Receive_DMA   HAL_I2C_Slave_Seq_Receive_DMA
+#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */
+
+#if defined(STM32F4)
+#define HAL_FMPI2C_Master_Sequential_Transmit_IT  HAL_FMPI2C_Master_Seq_Transmit_IT
+#define HAL_FMPI2C_Master_Sequential_Receive_IT   HAL_FMPI2C_Master_Seq_Receive_IT
+#define HAL_FMPI2C_Slave_Sequential_Transmit_IT   HAL_FMPI2C_Slave_Seq_Transmit_IT
+#define HAL_FMPI2C_Slave_Sequential_Receive_IT    HAL_FMPI2C_Slave_Seq_Receive_IT
+#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA
+#define HAL_FMPI2C_Master_Sequential_Receive_DMA  HAL_FMPI2C_Master_Seq_Receive_DMA
+#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA  HAL_FMPI2C_Slave_Seq_Transmit_DMA
+#define HAL_FMPI2C_Slave_Sequential_Receive_DMA   HAL_FMPI2C_Slave_Seq_Receive_DMA
+#endif /* STM32F4 */
+ /**
+  * @}
+  */
+
+/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
+  * @{
+  */
+
+#if defined(STM32G0)
+#define HAL_PWR_ConfigPVD                             HAL_PWREx_ConfigPVD
+#define HAL_PWR_EnablePVD                             HAL_PWREx_EnablePVD
+#define HAL_PWR_DisablePVD                            HAL_PWREx_DisablePVD
+#define HAL_PWR_PVD_IRQHandler                        HAL_PWREx_PVD_IRQHandler
+#endif
+#define HAL_PWR_PVDConfig                             HAL_PWR_ConfigPVD
+#define HAL_PWR_DisableBkUpReg                        HAL_PWREx_DisableBkUpReg
+#define HAL_PWR_DisableFlashPowerDown                 HAL_PWREx_DisableFlashPowerDown
+#define HAL_PWR_DisableVddio2Monitor                  HAL_PWREx_DisableVddio2Monitor
+#define HAL_PWR_EnableBkUpReg                         HAL_PWREx_EnableBkUpReg
+#define HAL_PWR_EnableFlashPowerDown                  HAL_PWREx_EnableFlashPowerDown
+#define HAL_PWR_EnableVddio2Monitor                   HAL_PWREx_EnableVddio2Monitor
+#define HAL_PWR_PVD_PVM_IRQHandler                    HAL_PWREx_PVD_PVM_IRQHandler
+#define HAL_PWR_PVDLevelConfig                        HAL_PWR_ConfigPVD
+#define HAL_PWR_Vddio2Monitor_IRQHandler              HAL_PWREx_Vddio2Monitor_IRQHandler
+#define HAL_PWR_Vddio2MonitorCallback                 HAL_PWREx_Vddio2MonitorCallback
+#define HAL_PWREx_ActivateOverDrive                   HAL_PWREx_EnableOverDrive
+#define HAL_PWREx_DeactivateOverDrive                 HAL_PWREx_DisableOverDrive
+#define HAL_PWREx_DisableSDADCAnalog                  HAL_PWREx_DisableSDADC
+#define HAL_PWREx_EnableSDADCAnalog                   HAL_PWREx_EnableSDADC
+#define HAL_PWREx_PVMConfig                           HAL_PWREx_ConfigPVM
+
+#define PWR_MODE_NORMAL                               PWR_PVD_MODE_NORMAL
+#define PWR_MODE_IT_RISING                            PWR_PVD_MODE_IT_RISING
+#define PWR_MODE_IT_FALLING                           PWR_PVD_MODE_IT_FALLING
+#define PWR_MODE_IT_RISING_FALLING                    PWR_PVD_MODE_IT_RISING_FALLING
+#define PWR_MODE_EVENT_RISING                         PWR_PVD_MODE_EVENT_RISING
+#define PWR_MODE_EVENT_FALLING                        PWR_PVD_MODE_EVENT_FALLING
+#define PWR_MODE_EVENT_RISING_FALLING                 PWR_PVD_MODE_EVENT_RISING_FALLING
+
+#define CR_OFFSET_BB                                  PWR_CR_OFFSET_BB
+#define CSR_OFFSET_BB                                 PWR_CSR_OFFSET_BB
+#define PMODE_BIT_NUMBER                              VOS_BIT_NUMBER
+#define CR_PMODE_BB                                   CR_VOS_BB
+
+#define DBP_BitNumber                                 DBP_BIT_NUMBER
+#define PVDE_BitNumber                                PVDE_BIT_NUMBER
+#define PMODE_BitNumber                               PMODE_BIT_NUMBER
+#define EWUP_BitNumber                                EWUP_BIT_NUMBER
+#define FPDS_BitNumber                                FPDS_BIT_NUMBER
+#define ODEN_BitNumber                                ODEN_BIT_NUMBER
+#define ODSWEN_BitNumber                              ODSWEN_BIT_NUMBER
+#define MRLVDS_BitNumber                              MRLVDS_BIT_NUMBER
+#define LPLVDS_BitNumber                              LPLVDS_BIT_NUMBER
+#define BRE_BitNumber                                 BRE_BIT_NUMBER
+
+#define PWR_MODE_EVT                                  PWR_PVD_MODE_NORMAL
+
+ /**
+  * @}
+  */
+
+/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_SMBUS_Slave_Listen_IT          HAL_SMBUS_EnableListen_IT
+#define HAL_SMBUS_SlaveAddrCallback        HAL_SMBUS_AddrCallback
+#define HAL_SMBUS_SlaveListenCpltCallback  HAL_SMBUS_ListenCpltCallback
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_SPI_FlushRxFifo                HAL_SPIEx_FlushRxFifo
+/**
+  * @}
+  */
+
+/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_TIM_DMADelayPulseCplt                       TIM_DMADelayPulseCplt
+#define HAL_TIM_DMAError                                TIM_DMAError
+#define HAL_TIM_DMACaptureCplt                          TIM_DMACaptureCplt
+#define HAL_TIMEx_DMACommutationCplt                    TIMEx_DMACommutationCplt
+#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
+#define HAL_TIM_SlaveConfigSynchronization              HAL_TIM_SlaveConfigSynchro
+#define HAL_TIM_SlaveConfigSynchronization_IT           HAL_TIM_SlaveConfigSynchro_IT
+#define HAL_TIMEx_CommutationCallback                   HAL_TIMEx_CommutCallback
+#define HAL_TIMEx_ConfigCommutationEvent                HAL_TIMEx_ConfigCommutEvent
+#define HAL_TIMEx_ConfigCommutationEvent_IT             HAL_TIMEx_ConfigCommutEvent_IT
+#define HAL_TIMEx_ConfigCommutationEvent_DMA            HAL_TIMEx_ConfigCommutEvent_DMA
+#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
+/**
+  * @}
+  */
+
+/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
+#define HAL_LTDC_Relaod           HAL_LTDC_Reload
+#define HAL_LTDC_StructInitFromVideoConfig  HAL_LTDCEx_StructInitFromVideoConfig
+#define HAL_LTDC_StructInitFromAdaptedCommandConfig  HAL_LTDCEx_StructInitFromAdaptedCommandConfig
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros ------------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define AES_IT_CC                      CRYP_IT_CC
+#define AES_IT_ERR                     CRYP_IT_ERR
+#define AES_FLAG_CCF                   CRYP_FLAG_CCF
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_GET_BOOT_MODE                   __HAL_SYSCFG_GET_BOOT_MODE
+#define __HAL_REMAPMEMORY_FLASH               __HAL_SYSCFG_REMAPMEMORY_FLASH
+#define __HAL_REMAPMEMORY_SYSTEMFLASH         __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
+#define __HAL_REMAPMEMORY_SRAM                __HAL_SYSCFG_REMAPMEMORY_SRAM
+#define __HAL_REMAPMEMORY_FMC                 __HAL_SYSCFG_REMAPMEMORY_FMC
+#define __HAL_REMAPMEMORY_FMC_SDRAM           __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
+#define __HAL_REMAPMEMORY_FSMC                __HAL_SYSCFG_REMAPMEMORY_FSMC
+#define __HAL_REMAPMEMORY_QUADSPI             __HAL_SYSCFG_REMAPMEMORY_QUADSPI
+#define __HAL_FMC_BANK                        __HAL_SYSCFG_FMC_BANK
+#define __HAL_GET_FLAG                        __HAL_SYSCFG_GET_FLAG
+#define __HAL_CLEAR_FLAG                      __HAL_SYSCFG_CLEAR_FLAG
+#define __HAL_VREFINT_OUT_ENABLE              __HAL_SYSCFG_VREFINT_OUT_ENABLE
+#define __HAL_VREFINT_OUT_DISABLE             __HAL_SYSCFG_VREFINT_OUT_DISABLE
+#define __HAL_SYSCFG_SRAM2_WRP_ENABLE         __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
+
+#define SYSCFG_FLAG_VREF_READY                SYSCFG_FLAG_VREFINT_READY
+#define SYSCFG_FLAG_RC48                      RCC_FLAG_HSI48
+#define IS_SYSCFG_FASTMODEPLUS_CONFIG         IS_I2C_FASTMODEPLUS
+#define UFB_MODE_BitNumber                    UFB_MODE_BIT_NUMBER
+#define CMP_PD_BitNumber                      CMP_PD_BIT_NUMBER
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __ADC_ENABLE                                     __HAL_ADC_ENABLE
+#define __ADC_DISABLE                                    __HAL_ADC_DISABLE
+#define __HAL_ADC_ENABLING_CONDITIONS                    ADC_ENABLING_CONDITIONS
+#define __HAL_ADC_DISABLING_CONDITIONS                   ADC_DISABLING_CONDITIONS
+#define __HAL_ADC_IS_ENABLED                             ADC_IS_ENABLE
+#define __ADC_IS_ENABLED                                 ADC_IS_ENABLE
+#define __HAL_ADC_IS_SOFTWARE_START_REGULAR              ADC_IS_SOFTWARE_START_REGULAR
+#define __HAL_ADC_IS_SOFTWARE_START_INJECTED             ADC_IS_SOFTWARE_START_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR          ADC_IS_CONVERSION_ONGOING_REGULAR
+#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED         ADC_IS_CONVERSION_ONGOING_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING                  ADC_IS_CONVERSION_ONGOING
+#define __HAL_ADC_CLEAR_ERRORCODE                        ADC_CLEAR_ERRORCODE
+
+#define __HAL_ADC_GET_RESOLUTION                         ADC_GET_RESOLUTION
+#define __HAL_ADC_JSQR_RK                                ADC_JSQR_RK
+#define __HAL_ADC_CFGR_AWD1CH                            ADC_CFGR_AWD1CH_SHIFT
+#define __HAL_ADC_CFGR_AWD23CR                           ADC_CFGR_AWD23CR
+#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION            ADC_CFGR_INJECT_AUTO_CONVERSION
+#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE              ADC_CFGR_INJECT_CONTEXT_QUEUE
+#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS             ADC_CFGR_INJECT_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS                ADC_CFGR_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM                 ADC_CFGR_DISCONTINUOUS_NUM
+#define __HAL_ADC_CFGR_AUTOWAIT                          ADC_CFGR_AUTOWAIT
+#define __HAL_ADC_CFGR_CONTINUOUS                        ADC_CFGR_CONTINUOUS
+#define __HAL_ADC_CFGR_OVERRUN                           ADC_CFGR_OVERRUN
+#define __HAL_ADC_CFGR_DMACONTREQ                        ADC_CFGR_DMACONTREQ
+#define __HAL_ADC_CFGR_EXTSEL                            ADC_CFGR_EXTSEL_SET
+#define __HAL_ADC_JSQR_JEXTSEL                           ADC_JSQR_JEXTSEL_SET
+#define __HAL_ADC_OFR_CHANNEL                            ADC_OFR_CHANNEL
+#define __HAL_ADC_DIFSEL_CHANNEL                         ADC_DIFSEL_CHANNEL
+#define __HAL_ADC_CALFACT_DIFF_SET                       ADC_CALFACT_DIFF_SET
+#define __HAL_ADC_CALFACT_DIFF_GET                       ADC_CALFACT_DIFF_GET
+#define __HAL_ADC_TRX_HIGHTHRESHOLD                      ADC_TRX_HIGHTHRESHOLD
+
+#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION                ADC_OFFSET_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION         ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION        ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_COMMON_REGISTER                        ADC_COMMON_REGISTER
+#define __HAL_ADC_COMMON_CCR_MULTI                       ADC_COMMON_CCR_MULTI
+#define __HAL_ADC_MULTIMODE_IS_ENABLED                   ADC_MULTIMODE_IS_ENABLE
+#define __ADC_MULTIMODE_IS_ENABLED                       ADC_MULTIMODE_IS_ENABLE
+#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER        ADC_NONMULTIMODE_OR_MULTIMODEMASTER
+#define __HAL_ADC_COMMON_ADC_OTHER                       ADC_COMMON_ADC_OTHER
+#define __HAL_ADC_MULTI_SLAVE                            ADC_MULTI_SLAVE
+
+#define __HAL_ADC_SQR1_L                                 ADC_SQR1_L_SHIFT
+#define __HAL_ADC_JSQR_JL                                ADC_JSQR_JL_SHIFT
+#define __HAL_ADC_JSQR_RK_JL                             ADC_JSQR_RK_JL
+#define __HAL_ADC_CR1_DISCONTINUOUS_NUM                  ADC_CR1_DISCONTINUOUS_NUM
+#define __HAL_ADC_CR1_SCAN                               ADC_CR1_SCAN_SET
+#define __HAL_ADC_CONVCYCLES_MAX_RANGE                   ADC_CONVCYCLES_MAX_RANGE
+#define __HAL_ADC_CLOCK_PRESCALER_RANGE                  ADC_CLOCK_PRESCALER_RANGE
+#define __HAL_ADC_GET_CLOCK_PRESCALER                    ADC_GET_CLOCK_PRESCALER
+
+#define __HAL_ADC_SQR1                                   ADC_SQR1
+#define __HAL_ADC_SMPR1                                  ADC_SMPR1
+#define __HAL_ADC_SMPR2                                  ADC_SMPR2
+#define __HAL_ADC_SQR3_RK                                ADC_SQR3_RK
+#define __HAL_ADC_SQR2_RK                                ADC_SQR2_RK
+#define __HAL_ADC_SQR1_RK                                ADC_SQR1_RK
+#define __HAL_ADC_CR2_CONTINUOUS                         ADC_CR2_CONTINUOUS
+#define __HAL_ADC_CR1_DISCONTINUOUS                      ADC_CR1_DISCONTINUOUS
+#define __HAL_ADC_CR1_SCANCONV                           ADC_CR1_SCANCONV
+#define __HAL_ADC_CR2_EOCSelection                       ADC_CR2_EOCSelection
+#define __HAL_ADC_CR2_DMAContReq                         ADC_CR2_DMAContReq
+#define __HAL_ADC_JSQR                                   ADC_JSQR
+
+#define __HAL_ADC_CHSELR_CHANNEL                         ADC_CHSELR_CHANNEL
+#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS               ADC_CFGR1_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR1_AUTOOFF                          ADC_CFGR1_AUTOOFF
+#define __HAL_ADC_CFGR1_AUTOWAIT                         ADC_CFGR1_AUTOWAIT
+#define __HAL_ADC_CFGR1_CONTINUOUS                       ADC_CFGR1_CONTINUOUS
+#define __HAL_ADC_CFGR1_OVERRUN                          ADC_CFGR1_OVERRUN
+#define __HAL_ADC_CFGR1_SCANDIR                          ADC_CFGR1_SCANDIR
+#define __HAL_ADC_CFGR1_DMACONTREQ                       ADC_CFGR1_DMACONTREQ
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_DHR12R1_ALIGNEMENT                        DAC_DHR12R1_ALIGNMENT
+#define __HAL_DHR12R2_ALIGNEMENT                        DAC_DHR12R2_ALIGNMENT
+#define __HAL_DHR12RD_ALIGNEMENT                        DAC_DHR12RD_ALIGNMENT
+#define IS_DAC_GENERATE_WAVE                            IS_DAC_WAVE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
+#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
+#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
+#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
+#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
+#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
+#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
+#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
+#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
+#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
+#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
+#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
+#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
+#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
+#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
+#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
+
+#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
+#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
+#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
+#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
+#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
+#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
+#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
+#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
+#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
+#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
+#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
+#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
+#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
+#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
+
+
+#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
+#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
+#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
+#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
+#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
+#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
+#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
+#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
+#if defined(STM32H7)
+  #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
+  #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
+  #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
+  #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
+#else
+  #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
+  #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
+  #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
+  #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
+#endif /* STM32H7 */
+#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
+#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
+#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
+#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
+#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
+#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
+#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
+#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
+#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
+#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
+#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
+#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#if defined(STM32F3)
+#define COMP_START                                       __HAL_COMP_ENABLE
+#define COMP_STOP                                        __HAL_COMP_DISABLE
+#define COMP_LOCK                                        __HAL_COMP_LOCK
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F302xE) || defined(STM32F302xC)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP7_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP7_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP7_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F373xC) ||defined(STM32F378xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+# endif
+#else
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+#endif
+
+#define __HAL_COMP_GET_EXTI_LINE  COMP_GET_EXTI_LINE
+
+#if defined(STM32L0) || defined(STM32L4)
+/* Note: On these STM32 families, the only argument of this macro             */
+/*       is COMP_FLAG_LOCK.                                                   */
+/*       This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle  */
+/*       argument.                                                            */
+#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__)  (__HAL_COMP_IS_LOCKED(__HANDLE__))
+#endif
+/**
+  * @}
+  */
+
+#if defined(STM32L0) || defined(STM32L4)
+/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_COMP_Start_IT       HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
+#define HAL_COMP_Stop_IT        HAL_COMP_Stop  /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
+/**
+  * @}
+  */
+#endif
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
+                          ((WAVE) == DAC_WAVE_NOISE)|| \
+                          ((WAVE) == DAC_WAVE_TRIANGLE))
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define IS_WRPAREA          IS_OB_WRPAREA
+#define IS_TYPEPROGRAM      IS_FLASH_TYPEPROGRAM
+#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
+#define IS_TYPEERASE        IS_FLASH_TYPEERASE
+#define IS_NBSECTORS        IS_FLASH_NBSECTORS
+#define IS_OB_WDG_SOURCE    IS_OB_IWDG_SOURCE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_I2C_RESET_CR2             I2C_RESET_CR2
+#define __HAL_I2C_GENERATE_START        I2C_GENERATE_START
+#if defined(STM32F1)
+#define __HAL_I2C_FREQ_RANGE            I2C_FREQRANGE
+#else
+#define __HAL_I2C_FREQ_RANGE            I2C_FREQ_RANGE
+#endif /* STM32F1 */
+#define __HAL_I2C_RISE_TIME             I2C_RISE_TIME
+#define __HAL_I2C_SPEED_STANDARD        I2C_SPEED_STANDARD
+#define __HAL_I2C_SPEED_FAST            I2C_SPEED_FAST
+#define __HAL_I2C_SPEED                 I2C_SPEED
+#define __HAL_I2C_7BIT_ADD_WRITE        I2C_7BIT_ADD_WRITE
+#define __HAL_I2C_7BIT_ADD_READ         I2C_7BIT_ADD_READ
+#define __HAL_I2C_10BIT_ADDRESS         I2C_10BIT_ADDRESS
+#define __HAL_I2C_10BIT_HEADER_WRITE    I2C_10BIT_HEADER_WRITE
+#define __HAL_I2C_10BIT_HEADER_READ     I2C_10BIT_HEADER_READ
+#define __HAL_I2C_MEM_ADD_MSB           I2C_MEM_ADD_MSB
+#define __HAL_I2C_MEM_ADD_LSB           I2C_MEM_ADD_LSB
+#define __HAL_I2C_FREQRANGE             I2C_FREQRANGE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define IS_I2S_INSTANCE                 IS_I2S_ALL_INSTANCE
+#define IS_I2S_INSTANCE_EXT             IS_I2S_ALL_INSTANCE_EXT
+
+#if defined(STM32H7)
+  #define __HAL_I2S_CLEAR_FREFLAG       __HAL_I2S_CLEAR_TIFREFLAG
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __IRDA_DISABLE                  __HAL_IRDA_DISABLE
+#define __IRDA_ENABLE                   __HAL_IRDA_ENABLE
+
+#define __HAL_IRDA_GETCLOCKSOURCE       IRDA_GETCLOCKSOURCE
+#define __HAL_IRDA_MASK_COMPUTATION     IRDA_MASK_COMPUTATION
+#define __IRDA_GETCLOCKSOURCE           IRDA_GETCLOCKSOURCE
+#define __IRDA_MASK_COMPUTATION         IRDA_MASK_COMPUTATION
+
+#define IS_IRDA_ONEBIT_SAMPLE           IS_IRDA_ONE_BIT_SAMPLE
+
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_IWDG_ENABLE_WRITE_ACCESS  IWDG_ENABLE_WRITE_ACCESS
+#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_LPTIM_ENABLE_INTERRUPT    __HAL_LPTIM_ENABLE_IT
+#define __HAL_LPTIM_DISABLE_INTERRUPT   __HAL_LPTIM_DISABLE_IT
+#define __HAL_LPTIM_GET_ITSTATUS        __HAL_LPTIM_GET_IT_SOURCE
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __OPAMP_CSR_OPAXPD                OPAMP_CSR_OPAXPD
+#define __OPAMP_CSR_S3SELX                OPAMP_CSR_S3SELX
+#define __OPAMP_CSR_S4SELX                OPAMP_CSR_S4SELX
+#define __OPAMP_CSR_S5SELX                OPAMP_CSR_S5SELX
+#define __OPAMP_CSR_S6SELX                OPAMP_CSR_S6SELX
+#define __OPAMP_CSR_OPAXCAL_L             OPAMP_CSR_OPAXCAL_L
+#define __OPAMP_CSR_OPAXCAL_H             OPAMP_CSR_OPAXCAL_H
+#define __OPAMP_CSR_OPAXLPM               OPAMP_CSR_OPAXLPM
+#define __OPAMP_CSR_ALL_SWITCHES          OPAMP_CSR_ALL_SWITCHES
+#define __OPAMP_CSR_ANAWSELX              OPAMP_CSR_ANAWSELX
+#define __OPAMP_CSR_OPAXCALOUT            OPAMP_CSR_OPAXCALOUT
+#define __OPAMP_OFFSET_TRIM_BITSPOSITION  OPAMP_OFFSET_TRIM_BITSPOSITION
+#define __OPAMP_OFFSET_TRIM_SET           OPAMP_OFFSET_TRIM_SET
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_PVD_EVENT_DISABLE                                  __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PVD_EVENT_ENABLE                                   __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PVM_EVENT_DISABLE                                  __HAL_PWR_PVM_EVENT_DISABLE
+#define __HAL_PVM_EVENT_ENABLE                                   __HAL_PWR_PVM_EVENT_ENABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
+#define __HAL_PWR_INTERNALWAKEUP_DISABLE                         HAL_PWREx_DisableInternalWakeUpLine
+#define __HAL_PWR_INTERNALWAKEUP_ENABLE                          HAL_PWREx_EnableInternalWakeUpLine
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE                    HAL_PWREx_DisablePullUpPullDownConfig
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE                     HAL_PWREx_EnablePullUpPullDownConfig
+#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER()                  do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
+#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE                         __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE                          __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE                __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE                 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE                 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE                  __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER              __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER               __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVM_DISABLE()                                  do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
+#define __HAL_PWR_PVM_ENABLE()                                   do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE                  HAL_PWREx_DisableSRAM2ContentRetention
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE                   HAL_PWREx_EnableSRAM2ContentRetention
+#define __HAL_PWR_VDDIO2_DISABLE                                 HAL_PWREx_DisableVddIO2
+#define __HAL_PWR_VDDIO2_ENABLE                                  HAL_PWREx_EnableVddIO2
+#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER                 __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER           __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_VDDUSB_DISABLE                                 HAL_PWREx_DisableVddUSB
+#define __HAL_PWR_VDDUSB_ENABLE                                  HAL_PWREx_EnableVddUSB
+
+#if defined (STM32F4)
+#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD)         __HAL_PWR_PVD_EXTI_ENABLE_IT()
+#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_DISABLE_IT()
+#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD)          __HAL_PWR_PVD_EXTI_GET_FLAG()
+#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
+#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD)     __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
+#else
+#define __HAL_PVD_EXTI_CLEAR_FLAG                                __HAL_PWR_PVD_EXTI_CLEAR_FLAG
+#define __HAL_PVD_EXTI_DISABLE_IT                                __HAL_PWR_PVD_EXTI_DISABLE_IT
+#define __HAL_PVD_EXTI_ENABLE_IT                                 __HAL_PWR_PVD_EXTI_ENABLE_IT
+#define __HAL_PVD_EXTI_GENERATE_SWIT                             __HAL_PWR_PVD_EXTI_GENERATE_SWIT
+#define __HAL_PVD_EXTI_GET_FLAG                                  __HAL_PWR_PVD_EXTI_GET_FLAG
+#endif /* STM32F4 */
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
+  * @{
+  */
+
+#define RCC_StopWakeUpClock_MSI     RCC_STOP_WAKEUPCLOCK_MSI
+#define RCC_StopWakeUpClock_HSI     RCC_STOP_WAKEUPCLOCK_HSI
+
+#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
+#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
+
+#define __ADC_CLK_DISABLE          __HAL_RCC_ADC_CLK_DISABLE
+#define __ADC_CLK_ENABLE           __HAL_RCC_ADC_CLK_ENABLE
+#define __ADC_CLK_SLEEP_DISABLE    __HAL_RCC_ADC_CLK_SLEEP_DISABLE
+#define __ADC_CLK_SLEEP_ENABLE     __HAL_RCC_ADC_CLK_SLEEP_ENABLE
+#define __ADC_FORCE_RESET          __HAL_RCC_ADC_FORCE_RESET
+#define __ADC_RELEASE_RESET        __HAL_RCC_ADC_RELEASE_RESET
+#define __ADC1_CLK_DISABLE         __HAL_RCC_ADC1_CLK_DISABLE
+#define __ADC1_CLK_ENABLE          __HAL_RCC_ADC1_CLK_ENABLE
+#define __ADC1_FORCE_RESET         __HAL_RCC_ADC1_FORCE_RESET
+#define __ADC1_RELEASE_RESET       __HAL_RCC_ADC1_RELEASE_RESET
+#define __ADC1_CLK_SLEEP_ENABLE    __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
+#define __ADC1_CLK_SLEEP_DISABLE   __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_DISABLE         __HAL_RCC_ADC2_CLK_DISABLE
+#define __ADC2_CLK_ENABLE          __HAL_RCC_ADC2_CLK_ENABLE
+#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
+#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
+#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
+#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
+#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
+#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
+#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
+#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
+#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
+#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
+#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
+#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
+#define __CRYP_CLK_SLEEP_ENABLE      __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
+#define __CRYP_CLK_SLEEP_DISABLE  __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
+#define __CRYP_CLK_ENABLE  __HAL_RCC_CRYP_CLK_ENABLE
+#define __CRYP_CLK_DISABLE  __HAL_RCC_CRYP_CLK_DISABLE
+#define __CRYP_FORCE_RESET       __HAL_RCC_CRYP_FORCE_RESET
+#define __CRYP_RELEASE_RESET  __HAL_RCC_CRYP_RELEASE_RESET
+#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
+#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
+#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
+#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
+#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
+#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
+#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
+#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
+#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
+#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
+#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
+#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
+#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
+#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
+#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
+#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
+#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
+#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
+#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
+#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
+#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
+#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
+#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN_CLK_DISABLE         __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN_CLK_ENABLE          __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN_FORCE_RESET         __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN_RELEASE_RESET       __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
+#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
+#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
+#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
+#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
+#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
+#define __COMP_CLK_DISABLE        __HAL_RCC_COMP_CLK_DISABLE
+#define __COMP_CLK_ENABLE         __HAL_RCC_COMP_CLK_ENABLE
+#define __COMP_FORCE_RESET        __HAL_RCC_COMP_FORCE_RESET
+#define __COMP_RELEASE_RESET      __HAL_RCC_COMP_RELEASE_RESET
+#define __COMP_CLK_SLEEP_ENABLE   __HAL_RCC_COMP_CLK_SLEEP_ENABLE
+#define __COMP_CLK_SLEEP_DISABLE  __HAL_RCC_COMP_CLK_SLEEP_DISABLE
+#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
+#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
+#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
+#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
+#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
+#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
+#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
+#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
+#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
+#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
+#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
+#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
+#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
+#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
+#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
+#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
+#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
+#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
+#define __DBGMCU_CLK_ENABLE     __HAL_RCC_DBGMCU_CLK_ENABLE
+#define __DBGMCU_CLK_DISABLE     __HAL_RCC_DBGMCU_CLK_DISABLE
+#define __DBGMCU_FORCE_RESET    __HAL_RCC_DBGMCU_FORCE_RESET
+#define __DBGMCU_RELEASE_RESET  __HAL_RCC_DBGMCU_RELEASE_RESET
+#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
+#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
+#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
+#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
+#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
+#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
+#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
+#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
+#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
+#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
+#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
+#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
+#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
+#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
+#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
+#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
+#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
+#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
+#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
+#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
+#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
+#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
+#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
+#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
+#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
+#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
+#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
+#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
+#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
+#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
+#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
+#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
+#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
+#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
+#define __FLITF_CLK_DISABLE       __HAL_RCC_FLITF_CLK_DISABLE
+#define __FLITF_CLK_ENABLE        __HAL_RCC_FLITF_CLK_ENABLE
+#define __FLITF_FORCE_RESET       __HAL_RCC_FLITF_FORCE_RESET
+#define __FLITF_RELEASE_RESET     __HAL_RCC_FLITF_RELEASE_RESET
+#define __FLITF_CLK_SLEEP_ENABLE  __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
+#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
+#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
+#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
+#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
+#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
+#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
+#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
+#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
+#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
+#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
+#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
+#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
+#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
+#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
+#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
+#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
+#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
+#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
+#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
+#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
+#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
+#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
+#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
+#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
+#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
+#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
+#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
+#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
+#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
+#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
+#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
+#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
+#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
+#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
+#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
+#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
+#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
+#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
+#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
+#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
+#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
+#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
+#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
+#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
+#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
+#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
+#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
+#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
+#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
+#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
+#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
+#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
+#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
+#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
+#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
+#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
+#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
+#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
+#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
+#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
+#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
+#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
+#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
+#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
+#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
+#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
+#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
+#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
+#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
+#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
+#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
+#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
+#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
+#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
+#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
+#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
+#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
+#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
+#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
+#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
+#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
+#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
+#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
+#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
+#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
+#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
+#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
+#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
+#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
+#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
+#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
+#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
+#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
+#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
+#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
+#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
+#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
+#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
+#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
+#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
+#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
+#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
+#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
+#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
+#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
+#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
+#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
+#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
+#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
+#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
+#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
+#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
+#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
+#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
+#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
+#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
+#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
+#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
+#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
+#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
+#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
+#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
+#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
+
+#if defined(STM32WB)
+#define __HAL_RCC_QSPI_CLK_DISABLE            __HAL_RCC_QUADSPI_CLK_DISABLE
+#define __HAL_RCC_QSPI_CLK_ENABLE             __HAL_RCC_QUADSPI_CLK_ENABLE
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE      __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE       __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_QSPI_FORCE_RESET            __HAL_RCC_QUADSPI_FORCE_RESET
+#define __HAL_RCC_QSPI_RELEASE_RESET          __HAL_RCC_QUADSPI_RELEASE_RESET
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED         __HAL_RCC_QUADSPI_IS_CLK_ENABLED
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED        __HAL_RCC_QUADSPI_IS_CLK_DISABLED
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED   __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED  __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED
+#define QSPI_IRQHandler QUADSPI_IRQHandler
+#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */
+
+#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
+#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
+#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
+#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
+#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
+#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
+#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
+#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
+#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
+#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
+#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
+#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
+#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
+#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
+#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
+#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
+#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
+#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
+#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
+#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
+#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
+#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
+#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
+#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
+#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
+#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
+#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
+#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
+#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
+#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
+#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
+#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
+#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
+#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
+#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
+#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
+#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
+#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
+#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
+#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
+#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
+#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
+#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
+#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
+#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
+#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
+#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
+#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
+#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
+#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
+#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
+#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
+#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
+#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
+#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
+#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
+#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
+#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
+#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
+#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
+#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
+#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
+#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
+#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
+#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
+#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
+#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
+#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
+#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
+#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
+#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
+#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
+#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
+#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
+#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
+#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
+#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
+#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
+#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
+#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
+#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
+#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
+#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
+#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
+#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
+#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
+#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
+#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
+#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
+#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
+#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
+#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
+#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
+#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
+#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
+#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
+#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
+#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
+#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
+#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
+#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
+#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
+#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
+#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
+#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
+#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
+#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
+#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
+#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
+#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
+#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
+#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
+#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
+#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
+#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
+#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
+#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
+#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
+#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
+#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
+#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
+#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
+#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
+#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
+#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
+#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
+#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
+#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
+#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
+#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
+#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
+#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
+#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
+#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
+#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
+#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
+#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
+#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
+#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
+#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
+#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
+#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
+#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
+#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
+#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
+#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
+#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
+#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
+#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
+#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
+#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
+#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
+#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
+#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
+#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
+#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
+#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
+#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
+#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
+#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
+#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
+#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
+#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
+#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
+#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
+#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
+#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
+#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
+#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
+#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
+#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
+#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
+#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
+#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
+#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
+#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
+#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
+#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
+#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
+#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
+#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
+#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
+#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
+#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
+#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
+#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
+#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
+#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
+#define __USART4_CLK_DISABLE        __HAL_RCC_UART4_CLK_DISABLE
+#define __USART4_CLK_ENABLE         __HAL_RCC_UART4_CLK_ENABLE
+#define __USART4_CLK_SLEEP_ENABLE   __HAL_RCC_UART4_CLK_SLEEP_ENABLE
+#define __USART4_CLK_SLEEP_DISABLE  __HAL_RCC_UART4_CLK_SLEEP_DISABLE
+#define __USART4_FORCE_RESET        __HAL_RCC_UART4_FORCE_RESET
+#define __USART4_RELEASE_RESET      __HAL_RCC_UART4_RELEASE_RESET
+#define __USART5_CLK_DISABLE        __HAL_RCC_UART5_CLK_DISABLE
+#define __USART5_CLK_ENABLE         __HAL_RCC_UART5_CLK_ENABLE
+#define __USART5_CLK_SLEEP_ENABLE   __HAL_RCC_UART5_CLK_SLEEP_ENABLE
+#define __USART5_CLK_SLEEP_DISABLE  __HAL_RCC_UART5_CLK_SLEEP_DISABLE
+#define __USART5_FORCE_RESET        __HAL_RCC_UART5_FORCE_RESET
+#define __USART5_RELEASE_RESET      __HAL_RCC_UART5_RELEASE_RESET
+#define __USART7_CLK_DISABLE        __HAL_RCC_UART7_CLK_DISABLE
+#define __USART7_CLK_ENABLE         __HAL_RCC_UART7_CLK_ENABLE
+#define __USART7_FORCE_RESET        __HAL_RCC_UART7_FORCE_RESET
+#define __USART7_RELEASE_RESET      __HAL_RCC_UART7_RELEASE_RESET
+#define __USART8_CLK_DISABLE        __HAL_RCC_UART8_CLK_DISABLE
+#define __USART8_CLK_ENABLE         __HAL_RCC_UART8_CLK_ENABLE
+#define __USART8_FORCE_RESET        __HAL_RCC_UART8_FORCE_RESET
+#define __USART8_RELEASE_RESET      __HAL_RCC_UART8_RELEASE_RESET
+#define __USB_CLK_DISABLE         __HAL_RCC_USB_CLK_DISABLE
+#define __USB_CLK_ENABLE          __HAL_RCC_USB_CLK_ENABLE
+#define __USB_FORCE_RESET         __HAL_RCC_USB_FORCE_RESET
+#define __USB_CLK_SLEEP_ENABLE    __HAL_RCC_USB_CLK_SLEEP_ENABLE
+#define __USB_CLK_SLEEP_DISABLE   __HAL_RCC_USB_CLK_SLEEP_DISABLE
+#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
+#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
+#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
+
+#if defined(STM32H7)
+#define __HAL_RCC_WWDG_CLK_DISABLE   __HAL_RCC_WWDG1_CLK_DISABLE
+#define __HAL_RCC_WWDG_CLK_ENABLE   __HAL_RCC_WWDG1_CLK_ENABLE
+#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE  __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE  __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE
+
+#define __HAL_RCC_WWDG_FORCE_RESET    ((void)0U)  /* Not available on the STM32H7*/
+#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/
+
+
+#define  __HAL_RCC_WWDG_IS_CLK_ENABLED    __HAL_RCC_WWDG1_IS_CLK_ENABLED
+#define  __HAL_RCC_WWDG_IS_CLK_DISABLED  __HAL_RCC_WWDG1_IS_CLK_DISABLED
+#endif
+
+#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
+#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
+#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
+#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
+#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
+#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
+
+#define __TIM21_CLK_ENABLE   __HAL_RCC_TIM21_CLK_ENABLE
+#define __TIM21_CLK_DISABLE   __HAL_RCC_TIM21_CLK_DISABLE
+#define __TIM21_FORCE_RESET   __HAL_RCC_TIM21_FORCE_RESET
+#define __TIM21_RELEASE_RESET  __HAL_RCC_TIM21_RELEASE_RESET
+#define __TIM21_CLK_SLEEP_ENABLE   __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
+#define __TIM21_CLK_SLEEP_DISABLE   __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
+#define __TIM22_CLK_ENABLE   __HAL_RCC_TIM22_CLK_ENABLE
+#define __TIM22_CLK_DISABLE   __HAL_RCC_TIM22_CLK_DISABLE
+#define __TIM22_FORCE_RESET   __HAL_RCC_TIM22_FORCE_RESET
+#define __TIM22_RELEASE_RESET  __HAL_RCC_TIM22_RELEASE_RESET
+#define __TIM22_CLK_SLEEP_ENABLE   __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
+#define __TIM22_CLK_SLEEP_DISABLE   __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
+#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
+#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
+#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
+#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
+#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
+#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
+#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
+#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
+
+#define __USB_OTG_FS_FORCE_RESET  __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __USB_OTG_FS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+#define __USB_OTG_FS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
+#define __USB_OTG_FS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
+#define __USB_OTG_HS_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_DISABLE
+#define __USB_OTG_HS_CLK_ENABLE          __HAL_RCC_USB_OTG_HS_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
+#define __TIM9_CLK_SLEEP_ENABLE          __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
+#define __TIM9_CLK_SLEEP_DISABLE  __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
+#define __TIM10_CLK_SLEEP_ENABLE  __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
+#define __TIM10_CLK_SLEEP_DISABLE  __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
+#define __TIM11_CLK_SLEEP_ENABLE  __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
+#define __TIM11_CLK_SLEEP_DISABLE  __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
+#define __ETHMACPTP_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
+#define __ETHMACPTP_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
+#define __ETHMACPTP_CLK_ENABLE          __HAL_RCC_ETHMACPTP_CLK_ENABLE
+#define __ETHMACPTP_CLK_DISABLE          __HAL_RCC_ETHMACPTP_CLK_DISABLE
+#define __HASH_CLK_ENABLE          __HAL_RCC_HASH_CLK_ENABLE
+#define __HASH_FORCE_RESET          __HAL_RCC_HASH_FORCE_RESET
+#define __HASH_RELEASE_RESET          __HAL_RCC_HASH_RELEASE_RESET
+#define __HASH_CLK_SLEEP_ENABLE          __HAL_RCC_HASH_CLK_SLEEP_ENABLE
+#define __HASH_CLK_SLEEP_DISABLE  __HAL_RCC_HASH_CLK_SLEEP_DISABLE
+#define __HASH_CLK_DISABLE            __HAL_RCC_HASH_CLK_DISABLE
+#define __SPI5_CLK_ENABLE          __HAL_RCC_SPI5_CLK_ENABLE
+#define __SPI5_CLK_DISABLE              __HAL_RCC_SPI5_CLK_DISABLE
+#define __SPI5_FORCE_RESET          __HAL_RCC_SPI5_FORCE_RESET
+#define __SPI5_RELEASE_RESET          __HAL_RCC_SPI5_RELEASE_RESET
+#define __SPI5_CLK_SLEEP_ENABLE          __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
+#define __SPI5_CLK_SLEEP_DISABLE  __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
+#define __SPI6_CLK_ENABLE          __HAL_RCC_SPI6_CLK_ENABLE
+#define __SPI6_CLK_DISABLE          __HAL_RCC_SPI6_CLK_DISABLE
+#define __SPI6_FORCE_RESET          __HAL_RCC_SPI6_FORCE_RESET
+#define __SPI6_RELEASE_RESET         __HAL_RCC_SPI6_RELEASE_RESET
+#define __SPI6_CLK_SLEEP_ENABLE          __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
+#define __SPI6_CLK_SLEEP_DISABLE  __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
+#define __LTDC_CLK_ENABLE          __HAL_RCC_LTDC_CLK_ENABLE
+#define __LTDC_CLK_DISABLE          __HAL_RCC_LTDC_CLK_DISABLE
+#define __LTDC_FORCE_RESET          __HAL_RCC_LTDC_FORCE_RESET
+#define __LTDC_RELEASE_RESET          __HAL_RCC_LTDC_RELEASE_RESET
+#define __LTDC_CLK_SLEEP_ENABLE          __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
+#define __ETHMAC_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
+#define __ETHMAC_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
+#define __ETHMACTX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
+#define __ETHMACTX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
+#define __ETHMACRX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
+#define __ETHMACRX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
+#define __TIM12_CLK_SLEEP_ENABLE  __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
+#define __TIM12_CLK_SLEEP_DISABLE  __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
+#define __TIM13_CLK_SLEEP_ENABLE  __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
+#define __TIM13_CLK_SLEEP_DISABLE  __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
+#define __TIM14_CLK_SLEEP_ENABLE  __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
+#define __TIM14_CLK_SLEEP_DISABLE  __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
+#define __BKPSRAM_CLK_ENABLE          __HAL_RCC_BKPSRAM_CLK_ENABLE
+#define __BKPSRAM_CLK_DISABLE          __HAL_RCC_BKPSRAM_CLK_DISABLE
+#define __BKPSRAM_CLK_SLEEP_ENABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
+#define __BKPSRAM_CLK_SLEEP_DISABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
+#define __CCMDATARAMEN_CLK_ENABLE  __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
+#define __CCMDATARAMEN_CLK_DISABLE  __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
+#define __USART6_CLK_ENABLE          __HAL_RCC_USART6_CLK_ENABLE
+#define __USART6_CLK_DISABLE          __HAL_RCC_USART6_CLK_DISABLE
+#define __USART6_FORCE_RESET        __HAL_RCC_USART6_FORCE_RESET
+#define __USART6_RELEASE_RESET        __HAL_RCC_USART6_RELEASE_RESET
+#define __USART6_CLK_SLEEP_ENABLE  __HAL_RCC_USART6_CLK_SLEEP_ENABLE
+#define __USART6_CLK_SLEEP_DISABLE  __HAL_RCC_USART6_CLK_SLEEP_DISABLE
+#define __SPI4_CLK_ENABLE          __HAL_RCC_SPI4_CLK_ENABLE
+#define __SPI4_CLK_DISABLE          __HAL_RCC_SPI4_CLK_DISABLE
+#define __SPI4_FORCE_RESET          __HAL_RCC_SPI4_FORCE_RESET
+#define __SPI4_RELEASE_RESET        __HAL_RCC_SPI4_RELEASE_RESET
+#define __SPI4_CLK_SLEEP_ENABLE   __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
+#define __SPI4_CLK_SLEEP_DISABLE  __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
+#define __GPIOI_CLK_ENABLE          __HAL_RCC_GPIOI_CLK_ENABLE
+#define __GPIOI_CLK_DISABLE          __HAL_RCC_GPIOI_CLK_DISABLE
+#define __GPIOI_FORCE_RESET          __HAL_RCC_GPIOI_FORCE_RESET
+#define __GPIOI_RELEASE_RESET          __HAL_RCC_GPIOI_RELEASE_RESET
+#define __GPIOI_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
+#define __GPIOI_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
+#define __GPIOJ_CLK_ENABLE          __HAL_RCC_GPIOJ_CLK_ENABLE
+#define __GPIOJ_CLK_DISABLE          __HAL_RCC_GPIOJ_CLK_DISABLE
+#define __GPIOJ_FORCE_RESET         __HAL_RCC_GPIOJ_FORCE_RESET
+#define __GPIOJ_RELEASE_RESET          __HAL_RCC_GPIOJ_RELEASE_RESET
+#define __GPIOJ_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
+#define __GPIOJ_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
+#define __GPIOK_CLK_ENABLE          __HAL_RCC_GPIOK_CLK_ENABLE
+#define __GPIOK_CLK_DISABLE          __HAL_RCC_GPIOK_CLK_DISABLE
+#define __GPIOK_RELEASE_RESET          __HAL_RCC_GPIOK_RELEASE_RESET
+#define __GPIOK_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
+#define __GPIOK_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
+#define __ETH_CLK_ENABLE          __HAL_RCC_ETH_CLK_ENABLE
+#define __ETH_CLK_DISABLE          __HAL_RCC_ETH_CLK_DISABLE
+#define __DCMI_CLK_ENABLE          __HAL_RCC_DCMI_CLK_ENABLE
+#define __DCMI_CLK_DISABLE          __HAL_RCC_DCMI_CLK_DISABLE
+#define __DCMI_FORCE_RESET          __HAL_RCC_DCMI_FORCE_RESET
+#define __DCMI_RELEASE_RESET          __HAL_RCC_DCMI_RELEASE_RESET
+#define __DCMI_CLK_SLEEP_ENABLE   __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
+#define __DCMI_CLK_SLEEP_DISABLE  __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
+#define __UART7_CLK_ENABLE          __HAL_RCC_UART7_CLK_ENABLE
+#define __UART7_CLK_DISABLE          __HAL_RCC_UART7_CLK_DISABLE
+#define __UART7_RELEASE_RESET       __HAL_RCC_UART7_RELEASE_RESET
+#define __UART7_FORCE_RESET       __HAL_RCC_UART7_FORCE_RESET
+#define __UART7_CLK_SLEEP_ENABLE  __HAL_RCC_UART7_CLK_SLEEP_ENABLE
+#define __UART7_CLK_SLEEP_DISABLE  __HAL_RCC_UART7_CLK_SLEEP_DISABLE
+#define __UART8_CLK_ENABLE          __HAL_RCC_UART8_CLK_ENABLE
+#define __UART8_CLK_DISABLE          __HAL_RCC_UART8_CLK_DISABLE
+#define __UART8_FORCE_RESET          __HAL_RCC_UART8_FORCE_RESET
+#define __UART8_RELEASE_RESET          __HAL_RCC_UART8_RELEASE_RESET
+#define __UART8_CLK_SLEEP_ENABLE  __HAL_RCC_UART8_CLK_SLEEP_ENABLE
+#define __UART8_CLK_SLEEP_DISABLE  __HAL_RCC_UART8_CLK_SLEEP_DISABLE
+#define __OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __OTGHSULPI_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __OTGHSULPI_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
+#define __HAL_RCC_OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __HAL_RCC_OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE      __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE     __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED  __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
+#define __SRAM3_CLK_SLEEP_ENABLE       __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_ENABLE        __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_DISABLE       __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
+#define __DAC_CLK_SLEEP_ENABLE         __HAL_RCC_DAC_CLK_SLEEP_ENABLE
+#define __DAC_CLK_SLEEP_DISABLE        __HAL_RCC_DAC_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_SLEEP_ENABLE        __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
+#define __ADC2_CLK_SLEEP_DISABLE       __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
+#define __ADC3_CLK_SLEEP_ENABLE        __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
+#define __ADC3_CLK_SLEEP_DISABLE       __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
+#define __FSMC_FORCE_RESET             __HAL_RCC_FSMC_FORCE_RESET
+#define __FSMC_RELEASE_RESET           __HAL_RCC_FSMC_RELEASE_RESET
+#define __FSMC_CLK_SLEEP_ENABLE        __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
+#define __FSMC_CLK_SLEEP_DISABLE       __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
+#define __SDIO_FORCE_RESET             __HAL_RCC_SDIO_FORCE_RESET
+#define __SDIO_RELEASE_RESET           __HAL_RCC_SDIO_RELEASE_RESET
+#define __SDIO_CLK_SLEEP_DISABLE       __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __SDIO_CLK_SLEEP_ENABLE        __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_ENABLE             __HAL_RCC_DMA2D_CLK_ENABLE
+#define __DMA2D_CLK_DISABLE            __HAL_RCC_DMA2D_CLK_DISABLE
+#define __DMA2D_FORCE_RESET            __HAL_RCC_DMA2D_FORCE_RESET
+#define __DMA2D_RELEASE_RESET          __HAL_RCC_DMA2D_RELEASE_RESET
+#define __DMA2D_CLK_SLEEP_ENABLE       __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_SLEEP_DISABLE      __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
+
+/* alias define maintained for legacy */
+#define __HAL_RCC_OTGFS_FORCE_RESET    __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __HAL_RCC_OTGFS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+
+#define __ADC12_CLK_ENABLE          __HAL_RCC_ADC12_CLK_ENABLE
+#define __ADC12_CLK_DISABLE         __HAL_RCC_ADC12_CLK_DISABLE
+#define __ADC34_CLK_ENABLE          __HAL_RCC_ADC34_CLK_ENABLE
+#define __ADC34_CLK_DISABLE         __HAL_RCC_ADC34_CLK_DISABLE
+#define __DAC2_CLK_ENABLE           __HAL_RCC_DAC2_CLK_ENABLE
+#define __DAC2_CLK_DISABLE          __HAL_RCC_DAC2_CLK_DISABLE
+#define __TIM18_CLK_ENABLE          __HAL_RCC_TIM18_CLK_ENABLE
+#define __TIM18_CLK_DISABLE         __HAL_RCC_TIM18_CLK_DISABLE
+#define __TIM19_CLK_ENABLE          __HAL_RCC_TIM19_CLK_ENABLE
+#define __TIM19_CLK_DISABLE         __HAL_RCC_TIM19_CLK_DISABLE
+#define __TIM20_CLK_ENABLE          __HAL_RCC_TIM20_CLK_ENABLE
+#define __TIM20_CLK_DISABLE         __HAL_RCC_TIM20_CLK_DISABLE
+#define __HRTIM1_CLK_ENABLE         __HAL_RCC_HRTIM1_CLK_ENABLE
+#define __HRTIM1_CLK_DISABLE        __HAL_RCC_HRTIM1_CLK_DISABLE
+#define __SDADC1_CLK_ENABLE         __HAL_RCC_SDADC1_CLK_ENABLE
+#define __SDADC2_CLK_ENABLE         __HAL_RCC_SDADC2_CLK_ENABLE
+#define __SDADC3_CLK_ENABLE         __HAL_RCC_SDADC3_CLK_ENABLE
+#define __SDADC1_CLK_DISABLE        __HAL_RCC_SDADC1_CLK_DISABLE
+#define __SDADC2_CLK_DISABLE        __HAL_RCC_SDADC2_CLK_DISABLE
+#define __SDADC3_CLK_DISABLE        __HAL_RCC_SDADC3_CLK_DISABLE
+
+#define __ADC12_FORCE_RESET         __HAL_RCC_ADC12_FORCE_RESET
+#define __ADC12_RELEASE_RESET       __HAL_RCC_ADC12_RELEASE_RESET
+#define __ADC34_FORCE_RESET         __HAL_RCC_ADC34_FORCE_RESET
+#define __ADC34_RELEASE_RESET       __HAL_RCC_ADC34_RELEASE_RESET
+#define __DAC2_FORCE_RESET          __HAL_RCC_DAC2_FORCE_RESET
+#define __DAC2_RELEASE_RESET        __HAL_RCC_DAC2_RELEASE_RESET
+#define __TIM18_FORCE_RESET         __HAL_RCC_TIM18_FORCE_RESET
+#define __TIM18_RELEASE_RESET       __HAL_RCC_TIM18_RELEASE_RESET
+#define __TIM19_FORCE_RESET         __HAL_RCC_TIM19_FORCE_RESET
+#define __TIM19_RELEASE_RESET       __HAL_RCC_TIM19_RELEASE_RESET
+#define __TIM20_FORCE_RESET         __HAL_RCC_TIM20_FORCE_RESET
+#define __TIM20_RELEASE_RESET       __HAL_RCC_TIM20_RELEASE_RESET
+#define __HRTIM1_FORCE_RESET        __HAL_RCC_HRTIM1_FORCE_RESET
+#define __HRTIM1_RELEASE_RESET      __HAL_RCC_HRTIM1_RELEASE_RESET
+#define __SDADC1_FORCE_RESET        __HAL_RCC_SDADC1_FORCE_RESET
+#define __SDADC2_FORCE_RESET        __HAL_RCC_SDADC2_FORCE_RESET
+#define __SDADC3_FORCE_RESET        __HAL_RCC_SDADC3_FORCE_RESET
+#define __SDADC1_RELEASE_RESET      __HAL_RCC_SDADC1_RELEASE_RESET
+#define __SDADC2_RELEASE_RESET      __HAL_RCC_SDADC2_RELEASE_RESET
+#define __SDADC3_RELEASE_RESET      __HAL_RCC_SDADC3_RELEASE_RESET
+
+#define __ADC1_IS_CLK_ENABLED       __HAL_RCC_ADC1_IS_CLK_ENABLED
+#define __ADC1_IS_CLK_DISABLED      __HAL_RCC_ADC1_IS_CLK_DISABLED
+#define __ADC12_IS_CLK_ENABLED      __HAL_RCC_ADC12_IS_CLK_ENABLED
+#define __ADC12_IS_CLK_DISABLED     __HAL_RCC_ADC12_IS_CLK_DISABLED
+#define __ADC34_IS_CLK_ENABLED      __HAL_RCC_ADC34_IS_CLK_ENABLED
+#define __ADC34_IS_CLK_DISABLED     __HAL_RCC_ADC34_IS_CLK_DISABLED
+#define __CEC_IS_CLK_ENABLED        __HAL_RCC_CEC_IS_CLK_ENABLED
+#define __CEC_IS_CLK_DISABLED       __HAL_RCC_CEC_IS_CLK_DISABLED
+#define __CRC_IS_CLK_ENABLED        __HAL_RCC_CRC_IS_CLK_ENABLED
+#define __CRC_IS_CLK_DISABLED       __HAL_RCC_CRC_IS_CLK_DISABLED
+#define __DAC1_IS_CLK_ENABLED       __HAL_RCC_DAC1_IS_CLK_ENABLED
+#define __DAC1_IS_CLK_DISABLED      __HAL_RCC_DAC1_IS_CLK_DISABLED
+#define __DAC2_IS_CLK_ENABLED       __HAL_RCC_DAC2_IS_CLK_ENABLED
+#define __DAC2_IS_CLK_DISABLED      __HAL_RCC_DAC2_IS_CLK_DISABLED
+#define __DMA1_IS_CLK_ENABLED       __HAL_RCC_DMA1_IS_CLK_ENABLED
+#define __DMA1_IS_CLK_DISABLED      __HAL_RCC_DMA1_IS_CLK_DISABLED
+#define __DMA2_IS_CLK_ENABLED       __HAL_RCC_DMA2_IS_CLK_ENABLED
+#define __DMA2_IS_CLK_DISABLED      __HAL_RCC_DMA2_IS_CLK_DISABLED
+#define __FLITF_IS_CLK_ENABLED      __HAL_RCC_FLITF_IS_CLK_ENABLED
+#define __FLITF_IS_CLK_DISABLED     __HAL_RCC_FLITF_IS_CLK_DISABLED
+#define __FMC_IS_CLK_ENABLED        __HAL_RCC_FMC_IS_CLK_ENABLED
+#define __FMC_IS_CLK_DISABLED       __HAL_RCC_FMC_IS_CLK_DISABLED
+#define __GPIOA_IS_CLK_ENABLED      __HAL_RCC_GPIOA_IS_CLK_ENABLED
+#define __GPIOA_IS_CLK_DISABLED     __HAL_RCC_GPIOA_IS_CLK_DISABLED
+#define __GPIOB_IS_CLK_ENABLED      __HAL_RCC_GPIOB_IS_CLK_ENABLED
+#define __GPIOB_IS_CLK_DISABLED     __HAL_RCC_GPIOB_IS_CLK_DISABLED
+#define __GPIOC_IS_CLK_ENABLED      __HAL_RCC_GPIOC_IS_CLK_ENABLED
+#define __GPIOC_IS_CLK_DISABLED     __HAL_RCC_GPIOC_IS_CLK_DISABLED
+#define __GPIOD_IS_CLK_ENABLED      __HAL_RCC_GPIOD_IS_CLK_ENABLED
+#define __GPIOD_IS_CLK_DISABLED     __HAL_RCC_GPIOD_IS_CLK_DISABLED
+#define __GPIOE_IS_CLK_ENABLED      __HAL_RCC_GPIOE_IS_CLK_ENABLED
+#define __GPIOE_IS_CLK_DISABLED     __HAL_RCC_GPIOE_IS_CLK_DISABLED
+#define __GPIOF_IS_CLK_ENABLED      __HAL_RCC_GPIOF_IS_CLK_ENABLED
+#define __GPIOF_IS_CLK_DISABLED     __HAL_RCC_GPIOF_IS_CLK_DISABLED
+#define __GPIOG_IS_CLK_ENABLED      __HAL_RCC_GPIOG_IS_CLK_ENABLED
+#define __GPIOG_IS_CLK_DISABLED     __HAL_RCC_GPIOG_IS_CLK_DISABLED
+#define __GPIOH_IS_CLK_ENABLED      __HAL_RCC_GPIOH_IS_CLK_ENABLED
+#define __GPIOH_IS_CLK_DISABLED     __HAL_RCC_GPIOH_IS_CLK_DISABLED
+#define __HRTIM1_IS_CLK_ENABLED     __HAL_RCC_HRTIM1_IS_CLK_ENABLED
+#define __HRTIM1_IS_CLK_DISABLED    __HAL_RCC_HRTIM1_IS_CLK_DISABLED
+#define __I2C1_IS_CLK_ENABLED       __HAL_RCC_I2C1_IS_CLK_ENABLED
+#define __I2C1_IS_CLK_DISABLED      __HAL_RCC_I2C1_IS_CLK_DISABLED
+#define __I2C2_IS_CLK_ENABLED       __HAL_RCC_I2C2_IS_CLK_ENABLED
+#define __I2C2_IS_CLK_DISABLED      __HAL_RCC_I2C2_IS_CLK_DISABLED
+#define __I2C3_IS_CLK_ENABLED       __HAL_RCC_I2C3_IS_CLK_ENABLED
+#define __I2C3_IS_CLK_DISABLED      __HAL_RCC_I2C3_IS_CLK_DISABLED
+#define __PWR_IS_CLK_ENABLED        __HAL_RCC_PWR_IS_CLK_ENABLED
+#define __PWR_IS_CLK_DISABLED       __HAL_RCC_PWR_IS_CLK_DISABLED
+#define __SYSCFG_IS_CLK_ENABLED     __HAL_RCC_SYSCFG_IS_CLK_ENABLED
+#define __SYSCFG_IS_CLK_DISABLED    __HAL_RCC_SYSCFG_IS_CLK_DISABLED
+#define __SPI1_IS_CLK_ENABLED       __HAL_RCC_SPI1_IS_CLK_ENABLED
+#define __SPI1_IS_CLK_DISABLED      __HAL_RCC_SPI1_IS_CLK_DISABLED
+#define __SPI2_IS_CLK_ENABLED       __HAL_RCC_SPI2_IS_CLK_ENABLED
+#define __SPI2_IS_CLK_DISABLED      __HAL_RCC_SPI2_IS_CLK_DISABLED
+#define __SPI3_IS_CLK_ENABLED       __HAL_RCC_SPI3_IS_CLK_ENABLED
+#define __SPI3_IS_CLK_DISABLED      __HAL_RCC_SPI3_IS_CLK_DISABLED
+#define __SPI4_IS_CLK_ENABLED       __HAL_RCC_SPI4_IS_CLK_ENABLED
+#define __SPI4_IS_CLK_DISABLED      __HAL_RCC_SPI4_IS_CLK_DISABLED
+#define __SDADC1_IS_CLK_ENABLED     __HAL_RCC_SDADC1_IS_CLK_ENABLED
+#define __SDADC1_IS_CLK_DISABLED    __HAL_RCC_SDADC1_IS_CLK_DISABLED
+#define __SDADC2_IS_CLK_ENABLED     __HAL_RCC_SDADC2_IS_CLK_ENABLED
+#define __SDADC2_IS_CLK_DISABLED    __HAL_RCC_SDADC2_IS_CLK_DISABLED
+#define __SDADC3_IS_CLK_ENABLED     __HAL_RCC_SDADC3_IS_CLK_ENABLED
+#define __SDADC3_IS_CLK_DISABLED    __HAL_RCC_SDADC3_IS_CLK_DISABLED
+#define __SRAM_IS_CLK_ENABLED       __HAL_RCC_SRAM_IS_CLK_ENABLED
+#define __SRAM_IS_CLK_DISABLED      __HAL_RCC_SRAM_IS_CLK_DISABLED
+#define __TIM1_IS_CLK_ENABLED       __HAL_RCC_TIM1_IS_CLK_ENABLED
+#define __TIM1_IS_CLK_DISABLED      __HAL_RCC_TIM1_IS_CLK_DISABLED
+#define __TIM2_IS_CLK_ENABLED       __HAL_RCC_TIM2_IS_CLK_ENABLED
+#define __TIM2_IS_CLK_DISABLED      __HAL_RCC_TIM2_IS_CLK_DISABLED
+#define __TIM3_IS_CLK_ENABLED       __HAL_RCC_TIM3_IS_CLK_ENABLED
+#define __TIM3_IS_CLK_DISABLED      __HAL_RCC_TIM3_IS_CLK_DISABLED
+#define __TIM4_IS_CLK_ENABLED       __HAL_RCC_TIM4_IS_CLK_ENABLED
+#define __TIM4_IS_CLK_DISABLED      __HAL_RCC_TIM4_IS_CLK_DISABLED
+#define __TIM5_IS_CLK_ENABLED       __HAL_RCC_TIM5_IS_CLK_ENABLED
+#define __TIM5_IS_CLK_DISABLED      __HAL_RCC_TIM5_IS_CLK_DISABLED
+#define __TIM6_IS_CLK_ENABLED       __HAL_RCC_TIM6_IS_CLK_ENABLED
+#define __TIM6_IS_CLK_DISABLED      __HAL_RCC_TIM6_IS_CLK_DISABLED
+#define __TIM7_IS_CLK_ENABLED       __HAL_RCC_TIM7_IS_CLK_ENABLED
+#define __TIM7_IS_CLK_DISABLED      __HAL_RCC_TIM7_IS_CLK_DISABLED
+#define __TIM8_IS_CLK_ENABLED       __HAL_RCC_TIM8_IS_CLK_ENABLED
+#define __TIM8_IS_CLK_DISABLED      __HAL_RCC_TIM8_IS_CLK_DISABLED
+#define __TIM12_IS_CLK_ENABLED      __HAL_RCC_TIM12_IS_CLK_ENABLED
+#define __TIM12_IS_CLK_DISABLED     __HAL_RCC_TIM12_IS_CLK_DISABLED
+#define __TIM13_IS_CLK_ENABLED      __HAL_RCC_TIM13_IS_CLK_ENABLED
+#define __TIM13_IS_CLK_DISABLED     __HAL_RCC_TIM13_IS_CLK_DISABLED
+#define __TIM14_IS_CLK_ENABLED      __HAL_RCC_TIM14_IS_CLK_ENABLED
+#define __TIM14_IS_CLK_DISABLED     __HAL_RCC_TIM14_IS_CLK_DISABLED
+#define __TIM15_IS_CLK_ENABLED      __HAL_RCC_TIM15_IS_CLK_ENABLED
+#define __TIM15_IS_CLK_DISABLED     __HAL_RCC_TIM15_IS_CLK_DISABLED
+#define __TIM16_IS_CLK_ENABLED      __HAL_RCC_TIM16_IS_CLK_ENABLED
+#define __TIM16_IS_CLK_DISABLED     __HAL_RCC_TIM16_IS_CLK_DISABLED
+#define __TIM17_IS_CLK_ENABLED      __HAL_RCC_TIM17_IS_CLK_ENABLED
+#define __TIM17_IS_CLK_DISABLED     __HAL_RCC_TIM17_IS_CLK_DISABLED
+#define __TIM18_IS_CLK_ENABLED      __HAL_RCC_TIM18_IS_CLK_ENABLED
+#define __TIM18_IS_CLK_DISABLED     __HAL_RCC_TIM18_IS_CLK_DISABLED
+#define __TIM19_IS_CLK_ENABLED      __HAL_RCC_TIM19_IS_CLK_ENABLED
+#define __TIM19_IS_CLK_DISABLED     __HAL_RCC_TIM19_IS_CLK_DISABLED
+#define __TIM20_IS_CLK_ENABLED      __HAL_RCC_TIM20_IS_CLK_ENABLED
+#define __TIM20_IS_CLK_DISABLED     __HAL_RCC_TIM20_IS_CLK_DISABLED
+#define __TSC_IS_CLK_ENABLED        __HAL_RCC_TSC_IS_CLK_ENABLED
+#define __TSC_IS_CLK_DISABLED       __HAL_RCC_TSC_IS_CLK_DISABLED
+#define __UART4_IS_CLK_ENABLED      __HAL_RCC_UART4_IS_CLK_ENABLED
+#define __UART4_IS_CLK_DISABLED     __HAL_RCC_UART4_IS_CLK_DISABLED
+#define __UART5_IS_CLK_ENABLED      __HAL_RCC_UART5_IS_CLK_ENABLED
+#define __UART5_IS_CLK_DISABLED     __HAL_RCC_UART5_IS_CLK_DISABLED
+#define __USART1_IS_CLK_ENABLED     __HAL_RCC_USART1_IS_CLK_ENABLED
+#define __USART1_IS_CLK_DISABLED    __HAL_RCC_USART1_IS_CLK_DISABLED
+#define __USART2_IS_CLK_ENABLED     __HAL_RCC_USART2_IS_CLK_ENABLED
+#define __USART2_IS_CLK_DISABLED    __HAL_RCC_USART2_IS_CLK_DISABLED
+#define __USART3_IS_CLK_ENABLED     __HAL_RCC_USART3_IS_CLK_ENABLED
+#define __USART3_IS_CLK_DISABLED    __HAL_RCC_USART3_IS_CLK_DISABLED
+#define __USB_IS_CLK_ENABLED        __HAL_RCC_USB_IS_CLK_ENABLED
+#define __USB_IS_CLK_DISABLED       __HAL_RCC_USB_IS_CLK_DISABLED
+#define __WWDG_IS_CLK_ENABLED       __HAL_RCC_WWDG_IS_CLK_ENABLED
+#define __WWDG_IS_CLK_DISABLED      __HAL_RCC_WWDG_IS_CLK_DISABLED
+
+#if defined(STM32L1)
+#define __HAL_RCC_CRYP_CLK_DISABLE         __HAL_RCC_AES_CLK_DISABLE
+#define __HAL_RCC_CRYP_CLK_ENABLE          __HAL_RCC_AES_CLK_ENABLE
+#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE   __HAL_RCC_AES_CLK_SLEEP_DISABLE
+#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE    __HAL_RCC_AES_CLK_SLEEP_ENABLE
+#define __HAL_RCC_CRYP_FORCE_RESET         __HAL_RCC_AES_FORCE_RESET
+#define __HAL_RCC_CRYP_RELEASE_RESET       __HAL_RCC_AES_RELEASE_RESET
+#endif /* STM32L1 */
+
+#if defined(STM32F4)
+#define __HAL_RCC_SDMMC1_FORCE_RESET       __HAL_RCC_SDIO_FORCE_RESET
+#define __HAL_RCC_SDMMC1_RELEASE_RESET     __HAL_RCC_SDIO_RELEASE_RESET
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE  __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDMMC1_CLK_ENABLE        __HAL_RCC_SDIO_CLK_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_DISABLE       __HAL_RCC_SDIO_CLK_DISABLE
+#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED    __HAL_RCC_SDIO_IS_CLK_ENABLED
+#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED   __HAL_RCC_SDIO_IS_CLK_DISABLED
+#define Sdmmc1ClockSelection               SdioClockSelection
+#define RCC_PERIPHCLK_SDMMC1               RCC_PERIPHCLK_SDIO
+#define RCC_SDMMC1CLKSOURCE_CLK48          RCC_SDIOCLKSOURCE_CK48
+#define RCC_SDMMC1CLKSOURCE_SYSCLK         RCC_SDIOCLKSOURCE_SYSCLK
+#define __HAL_RCC_SDMMC1_CONFIG            __HAL_RCC_SDIO_CONFIG
+#define __HAL_RCC_GET_SDMMC1_SOURCE        __HAL_RCC_GET_SDIO_SOURCE
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define __HAL_RCC_SDIO_FORCE_RESET         __HAL_RCC_SDMMC1_FORCE_RESET
+#define __HAL_RCC_SDIO_RELEASE_RESET       __HAL_RCC_SDMMC1_RELEASE_RESET
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE    __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE   __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDIO_CLK_ENABLE          __HAL_RCC_SDMMC1_CLK_ENABLE
+#define __HAL_RCC_SDIO_CLK_DISABLE         __HAL_RCC_SDMMC1_CLK_DISABLE
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED      __HAL_RCC_SDMMC1_IS_CLK_ENABLED
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED     __HAL_RCC_SDMMC1_IS_CLK_DISABLED
+#define SdioClockSelection                 Sdmmc1ClockSelection
+#define RCC_PERIPHCLK_SDIO                 RCC_PERIPHCLK_SDMMC1
+#define __HAL_RCC_SDIO_CONFIG              __HAL_RCC_SDMMC1_CONFIG
+#define __HAL_RCC_GET_SDIO_SOURCE          __HAL_RCC_GET_SDMMC1_SOURCE
+#endif
+
+#if defined(STM32F7)
+#define RCC_SDIOCLKSOURCE_CLK48             RCC_SDMMC1CLKSOURCE_CLK48
+#define RCC_SDIOCLKSOURCE_SYSCLK           RCC_SDMMC1CLKSOURCE_SYSCLK
+#endif
+
+#if defined(STM32H7)
+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()              __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()         __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()             __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE()        __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET()             __HAL_RCC_USB1_OTG_HS_FORCE_RESET()
+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()           __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()        __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()   __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()       __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE()  __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
+
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()             __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE()        __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE()            __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE()       __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()            __HAL_RCC_USB2_OTG_FS_FORCE_RESET()
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET()          __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()       __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE()  __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE()      __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()
+#endif
+
+#define __HAL_RCC_I2SCLK            __HAL_RCC_I2S_CONFIG
+#define __HAL_RCC_I2SCLK_CONFIG     __HAL_RCC_I2S_CONFIG
+
+#define __RCC_PLLSRC                RCC_GET_PLL_OSCSOURCE
+
+#define IS_RCC_MSIRANGE             IS_RCC_MSI_CLOCK_RANGE
+#define IS_RCC_RTCCLK_SOURCE        IS_RCC_RTCCLKSOURCE
+#define IS_RCC_SYSCLK_DIV           IS_RCC_HCLK
+#define IS_RCC_HCLK_DIV             IS_RCC_PCLK
+#define IS_RCC_PERIPHCLK            IS_RCC_PERIPHCLOCK
+
+#define RCC_IT_HSI14                RCC_IT_HSI14RDY
+
+#define RCC_IT_CSSLSE               RCC_IT_LSECSS
+#define RCC_IT_CSSHSE               RCC_IT_CSS
+
+#define RCC_PLLMUL_3                RCC_PLL_MUL3
+#define RCC_PLLMUL_4                RCC_PLL_MUL4
+#define RCC_PLLMUL_6                RCC_PLL_MUL6
+#define RCC_PLLMUL_8                RCC_PLL_MUL8
+#define RCC_PLLMUL_12               RCC_PLL_MUL12
+#define RCC_PLLMUL_16               RCC_PLL_MUL16
+#define RCC_PLLMUL_24               RCC_PLL_MUL24
+#define RCC_PLLMUL_32               RCC_PLL_MUL32
+#define RCC_PLLMUL_48               RCC_PLL_MUL48
+
+#define RCC_PLLDIV_2                RCC_PLL_DIV2
+#define RCC_PLLDIV_3                RCC_PLL_DIV3
+#define RCC_PLLDIV_4                RCC_PLL_DIV4
+
+#define IS_RCC_MCOSOURCE            IS_RCC_MCO1SOURCE
+#define __HAL_RCC_MCO_CONFIG        __HAL_RCC_MCO1_CONFIG
+#define RCC_MCO_NODIV               RCC_MCODIV_1
+#define RCC_MCO_DIV1                RCC_MCODIV_1
+#define RCC_MCO_DIV2                RCC_MCODIV_2
+#define RCC_MCO_DIV4                RCC_MCODIV_4
+#define RCC_MCO_DIV8                RCC_MCODIV_8
+#define RCC_MCO_DIV16               RCC_MCODIV_16
+#define RCC_MCO_DIV32               RCC_MCODIV_32
+#define RCC_MCO_DIV64               RCC_MCODIV_64
+#define RCC_MCO_DIV128              RCC_MCODIV_128
+#define RCC_MCOSOURCE_NONE          RCC_MCO1SOURCE_NOCLOCK
+#define RCC_MCOSOURCE_LSI           RCC_MCO1SOURCE_LSI
+#define RCC_MCOSOURCE_LSE           RCC_MCO1SOURCE_LSE
+#define RCC_MCOSOURCE_SYSCLK        RCC_MCO1SOURCE_SYSCLK
+#define RCC_MCOSOURCE_HSI           RCC_MCO1SOURCE_HSI
+#define RCC_MCOSOURCE_HSI14         RCC_MCO1SOURCE_HSI14
+#define RCC_MCOSOURCE_HSI48         RCC_MCO1SOURCE_HSI48
+#define RCC_MCOSOURCE_HSE           RCC_MCO1SOURCE_HSE
+#define RCC_MCOSOURCE_PLLCLK_DIV1   RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_NODIV  RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_DIV2   RCC_MCO1SOURCE_PLLCLK_DIV2
+
+#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
+#define RCC_RTCCLKSOURCE_NO_CLK     RCC_RTCCLKSOURCE_NONE
+#else
+#define RCC_RTCCLKSOURCE_NONE       RCC_RTCCLKSOURCE_NO_CLK
+#endif
+
+#define RCC_USBCLK_PLLSAI1          RCC_USBCLKSOURCE_PLLSAI1
+#define RCC_USBCLK_PLL              RCC_USBCLKSOURCE_PLL
+#define RCC_USBCLK_MSI              RCC_USBCLKSOURCE_MSI
+#define RCC_USBCLKSOURCE_PLLCLK     RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1          RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1_5        RCC_USBCLKSOURCE_PLL_DIV1_5
+#define RCC_USBPLLCLK_DIV2          RCC_USBCLKSOURCE_PLL_DIV2
+#define RCC_USBPLLCLK_DIV3          RCC_USBCLKSOURCE_PLL_DIV3
+
+#define HSION_BitNumber        RCC_HSION_BIT_NUMBER
+#define HSION_BITNUMBER        RCC_HSION_BIT_NUMBER
+#define HSEON_BitNumber        RCC_HSEON_BIT_NUMBER
+#define HSEON_BITNUMBER        RCC_HSEON_BIT_NUMBER
+#define MSION_BITNUMBER        RCC_MSION_BIT_NUMBER
+#define CSSON_BitNumber        RCC_CSSON_BIT_NUMBER
+#define CSSON_BITNUMBER        RCC_CSSON_BIT_NUMBER
+#define PLLON_BitNumber        RCC_PLLON_BIT_NUMBER
+#define PLLON_BITNUMBER        RCC_PLLON_BIT_NUMBER
+#define PLLI2SON_BitNumber     RCC_PLLI2SON_BIT_NUMBER
+#define I2SSRC_BitNumber       RCC_I2SSRC_BIT_NUMBER
+#define RTCEN_BitNumber        RCC_RTCEN_BIT_NUMBER
+#define RTCEN_BITNUMBER        RCC_RTCEN_BIT_NUMBER
+#define BDRST_BitNumber        RCC_BDRST_BIT_NUMBER
+#define BDRST_BITNUMBER        RCC_BDRST_BIT_NUMBER
+#define RTCRST_BITNUMBER       RCC_RTCRST_BIT_NUMBER
+#define LSION_BitNumber        RCC_LSION_BIT_NUMBER
+#define LSION_BITNUMBER        RCC_LSION_BIT_NUMBER
+#define LSEON_BitNumber        RCC_LSEON_BIT_NUMBER
+#define LSEON_BITNUMBER        RCC_LSEON_BIT_NUMBER
+#define LSEBYP_BITNUMBER       RCC_LSEBYP_BIT_NUMBER
+#define PLLSAION_BitNumber     RCC_PLLSAION_BIT_NUMBER
+#define TIMPRE_BitNumber       RCC_TIMPRE_BIT_NUMBER
+#define RMVF_BitNumber         RCC_RMVF_BIT_NUMBER
+#define RMVF_BITNUMBER         RCC_RMVF_BIT_NUMBER
+#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
+#define CR_BYTE2_ADDRESS       RCC_CR_BYTE2_ADDRESS
+#define CIR_BYTE1_ADDRESS      RCC_CIR_BYTE1_ADDRESS
+#define CIR_BYTE2_ADDRESS      RCC_CIR_BYTE2_ADDRESS
+#define BDCR_BYTE0_ADDRESS     RCC_BDCR_BYTE0_ADDRESS
+#define DBP_TIMEOUT_VALUE      RCC_DBP_TIMEOUT_VALUE
+#define LSE_TIMEOUT_VALUE      RCC_LSE_TIMEOUT_VALUE
+
+#define CR_HSION_BB            RCC_CR_HSION_BB
+#define CR_CSSON_BB            RCC_CR_CSSON_BB
+#define CR_PLLON_BB            RCC_CR_PLLON_BB
+#define CR_PLLI2SON_BB         RCC_CR_PLLI2SON_BB
+#define CR_MSION_BB            RCC_CR_MSION_BB
+#define CSR_LSION_BB           RCC_CSR_LSION_BB
+#define CSR_LSEON_BB           RCC_CSR_LSEON_BB
+#define CSR_LSEBYP_BB          RCC_CSR_LSEBYP_BB
+#define CSR_RTCEN_BB           RCC_CSR_RTCEN_BB
+#define CSR_RTCRST_BB          RCC_CSR_RTCRST_BB
+#define CFGR_I2SSRC_BB         RCC_CFGR_I2SSRC_BB
+#define BDCR_RTCEN_BB          RCC_BDCR_RTCEN_BB
+#define BDCR_BDRST_BB          RCC_BDCR_BDRST_BB
+#define CR_HSEON_BB            RCC_CR_HSEON_BB
+#define CSR_RMVF_BB            RCC_CSR_RMVF_BB
+#define CR_PLLSAION_BB         RCC_CR_PLLSAION_BB
+#define DCKCFGR_TIMPRE_BB      RCC_DCKCFGR_TIMPRE_BB
+
+#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER     __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
+#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER    __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
+#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB        __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
+#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB       __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
+#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE         __HAL_RCC_CRS_RELOADVALUE_CALCULATE
+
+#define __HAL_RCC_GET_IT_SOURCE                     __HAL_RCC_GET_IT
+
+#define RCC_CRS_SYNCWARM       RCC_CRS_SYNCWARN
+#define RCC_CRS_TRIMOV         RCC_CRS_TRIMOVF
+
+#define RCC_PERIPHCLK_CK48               RCC_PERIPHCLK_CLK48
+#define RCC_CK48CLKSOURCE_PLLQ           RCC_CLK48CLKSOURCE_PLLQ
+#define RCC_CK48CLKSOURCE_PLLSAIP        RCC_CLK48CLKSOURCE_PLLSAIP
+#define RCC_CK48CLKSOURCE_PLLI2SQ        RCC_CLK48CLKSOURCE_PLLI2SQ
+#define IS_RCC_CK48CLKSOURCE             IS_RCC_CLK48CLKSOURCE
+#define RCC_SDIOCLKSOURCE_CK48           RCC_SDIOCLKSOURCE_CLK48
+
+#define __HAL_RCC_DFSDM_CLK_ENABLE             __HAL_RCC_DFSDM1_CLK_ENABLE
+#define __HAL_RCC_DFSDM_CLK_DISABLE            __HAL_RCC_DFSDM1_CLK_DISABLE
+#define __HAL_RCC_DFSDM_IS_CLK_ENABLED         __HAL_RCC_DFSDM1_IS_CLK_ENABLED
+#define __HAL_RCC_DFSDM_IS_CLK_DISABLED        __HAL_RCC_DFSDM1_IS_CLK_DISABLED
+#define __HAL_RCC_DFSDM_FORCE_RESET            __HAL_RCC_DFSDM1_FORCE_RESET
+#define __HAL_RCC_DFSDM_RELEASE_RESET          __HAL_RCC_DFSDM1_RELEASE_RESET
+#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE       __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
+#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE      __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED   __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED  __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
+#define DfsdmClockSelection         Dfsdm1ClockSelection
+#define RCC_PERIPHCLK_DFSDM         RCC_PERIPHCLK_DFSDM1
+#define RCC_DFSDMCLKSOURCE_PCLK     RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_DFSDMCLKSOURCE_SYSCLK   RCC_DFSDM1CLKSOURCE_SYSCLK
+#define __HAL_RCC_DFSDM_CONFIG      __HAL_RCC_DFSDM1_CONFIG
+#define __HAL_RCC_GET_DFSDM_SOURCE  __HAL_RCC_GET_DFSDM1_SOURCE
+#define RCC_DFSDM1CLKSOURCE_PCLK    RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_SWPMI1CLKSOURCE_PCLK    RCC_SWPMI1CLKSOURCE_PCLK1
+#define RCC_LPTIM1CLKSOURCE_PCLK    RCC_LPTIM1CLKSOURCE_PCLK1
+#define RCC_LPTIM2CLKSOURCE_PCLK    RCC_LPTIM2CLKSOURCE_PCLK1
+
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM1AUDIOCLKSOURCE_I2S1
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM1AUDIOCLKSOURCE_I2S2
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM2AUDIOCLKSOURCE_I2S1
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM2AUDIOCLKSOURCE_I2S2
+#define RCC_DFSDM1CLKSOURCE_APB2            RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_DFSDM2CLKSOURCE_APB2            RCC_DFSDM2CLKSOURCE_PCLK2
+#define RCC_FMPI2C1CLKSOURCE_APB            RCC_FMPI2C1CLKSOURCE_PCLK1
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define  HAL_RNG_ReadyCallback(__HANDLE__)  HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4)
+#else
+#define __HAL_RTC_CLEAR_FLAG                      __HAL_RTC_EXTI_CLEAR_FLAG
+#endif
+#define __HAL_RTC_DISABLE_IT                      __HAL_RTC_EXTI_DISABLE_IT
+#define __HAL_RTC_ENABLE_IT                       __HAL_RTC_EXTI_ENABLE_IT
+
+#if defined (STM32F1)
+#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
+
+#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_ENABLE_IT()
+
+#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_DISABLE_IT()
+
+#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT)    __HAL_RTC_ALARM_EXTI_GET_FLAG()
+
+#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
+#else
+#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
+                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
+                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
+#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__)   (((__EXTI_LINE__)  == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
+                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
+                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
+#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
+                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
+                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
+#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__)    (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
+                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
+                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
+#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__)   (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
+                                                      (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() :  \
+                                                          __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
+#endif   /* STM32F1 */
+
+#define IS_ALARM                                  IS_RTC_ALARM
+#define IS_ALARM_MASK                             IS_RTC_ALARM_MASK
+#define IS_TAMPER                                 IS_RTC_TAMPER
+#define IS_TAMPER_ERASE_MODE                      IS_RTC_TAMPER_ERASE_MODE
+#define IS_TAMPER_FILTER                          IS_RTC_TAMPER_FILTER
+#define IS_TAMPER_INTERRUPT                       IS_RTC_TAMPER_INTERRUPT
+#define IS_TAMPER_MASKFLAG_STATE                  IS_RTC_TAMPER_MASKFLAG_STATE
+#define IS_TAMPER_PRECHARGE_DURATION              IS_RTC_TAMPER_PRECHARGE_DURATION
+#define IS_TAMPER_PULLUP_STATE                    IS_RTC_TAMPER_PULLUP_STATE
+#define IS_TAMPER_SAMPLING_FREQ                   IS_RTC_TAMPER_SAMPLING_FREQ
+#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION     IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
+#define IS_TAMPER_TRIGGER                         IS_RTC_TAMPER_TRIGGER
+#define IS_WAKEUP_CLOCK                           IS_RTC_WAKEUP_CLOCK
+#define IS_WAKEUP_COUNTER                         IS_RTC_WAKEUP_COUNTER
+
+#define __RTC_WRITEPROTECTION_ENABLE  __HAL_RTC_WRITEPROTECTION_ENABLE
+#define __RTC_WRITEPROTECTION_DISABLE  __HAL_RTC_WRITEPROTECTION_DISABLE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define SD_OCR_CID_CSD_OVERWRIETE   SD_OCR_CID_CSD_OVERWRITE
+#define SD_CMD_SD_APP_STAUS         SD_CMD_SD_APP_STATUS
+
+#if defined(STM32F4) || defined(STM32F2)
+#define  SD_SDMMC_DISABLED          SD_SDIO_DISABLED
+#define  SD_SDMMC_FUNCTION_BUSY     SD_SDIO_FUNCTION_BUSY
+#define  SD_SDMMC_FUNCTION_FAILED   SD_SDIO_FUNCTION_FAILED
+#define  SD_SDMMC_UNKNOWN_FUNCTION  SD_SDIO_UNKNOWN_FUNCTION
+#define  SD_CMD_SDMMC_SEN_OP_COND   SD_CMD_SDIO_SEN_OP_COND
+#define  SD_CMD_SDMMC_RW_DIRECT     SD_CMD_SDIO_RW_DIRECT
+#define  SD_CMD_SDMMC_RW_EXTENDED   SD_CMD_SDIO_RW_EXTENDED
+#define  __HAL_SD_SDMMC_ENABLE      __HAL_SD_SDIO_ENABLE
+#define  __HAL_SD_SDMMC_DISABLE     __HAL_SD_SDIO_DISABLE
+#define  __HAL_SD_SDMMC_DMA_ENABLE  __HAL_SD_SDIO_DMA_ENABLE
+#define  __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
+#define  __HAL_SD_SDMMC_ENABLE_IT   __HAL_SD_SDIO_ENABLE_IT
+#define  __HAL_SD_SDMMC_DISABLE_IT  __HAL_SD_SDIO_DISABLE_IT
+#define  __HAL_SD_SDMMC_GET_FLAG    __HAL_SD_SDIO_GET_FLAG
+#define  __HAL_SD_SDMMC_CLEAR_FLAG  __HAL_SD_SDIO_CLEAR_FLAG
+#define  __HAL_SD_SDMMC_GET_IT      __HAL_SD_SDIO_GET_IT
+#define  __HAL_SD_SDMMC_CLEAR_IT    __HAL_SD_SDIO_CLEAR_IT
+#define  SDMMC_STATIC_FLAGS         SDIO_STATIC_FLAGS
+#define  SDMMC_CMD0TIMEOUT          SDIO_CMD0TIMEOUT
+#define  SD_SDMMC_SEND_IF_COND      SD_SDIO_SEND_IF_COND
+/* alias CMSIS */
+#define  SDMMC1_IRQn                SDIO_IRQn
+#define  SDMMC1_IRQHandler          SDIO_IRQHandler
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define  SD_SDIO_DISABLED           SD_SDMMC_DISABLED
+#define  SD_SDIO_FUNCTION_BUSY      SD_SDMMC_FUNCTION_BUSY
+#define  SD_SDIO_FUNCTION_FAILED    SD_SDMMC_FUNCTION_FAILED
+#define  SD_SDIO_UNKNOWN_FUNCTION   SD_SDMMC_UNKNOWN_FUNCTION
+#define  SD_CMD_SDIO_SEN_OP_COND    SD_CMD_SDMMC_SEN_OP_COND
+#define  SD_CMD_SDIO_RW_DIRECT      SD_CMD_SDMMC_RW_DIRECT
+#define  SD_CMD_SDIO_RW_EXTENDED    SD_CMD_SDMMC_RW_EXTENDED
+#define  __HAL_SD_SDIO_ENABLE       __HAL_SD_SDMMC_ENABLE
+#define  __HAL_SD_SDIO_DISABLE      __HAL_SD_SDMMC_DISABLE
+#define  __HAL_SD_SDIO_DMA_ENABLE   __HAL_SD_SDMMC_DMA_ENABLE
+#define  __HAL_SD_SDIO_DMA_DISABL   __HAL_SD_SDMMC_DMA_DISABLE
+#define  __HAL_SD_SDIO_ENABLE_IT    __HAL_SD_SDMMC_ENABLE_IT
+#define  __HAL_SD_SDIO_DISABLE_IT   __HAL_SD_SDMMC_DISABLE_IT
+#define  __HAL_SD_SDIO_GET_FLAG     __HAL_SD_SDMMC_GET_FLAG
+#define  __HAL_SD_SDIO_CLEAR_FLAG   __HAL_SD_SDMMC_CLEAR_FLAG
+#define  __HAL_SD_SDIO_GET_IT       __HAL_SD_SDMMC_GET_IT
+#define  __HAL_SD_SDIO_CLEAR_IT     __HAL_SD_SDMMC_CLEAR_IT
+#define  SDIO_STATIC_FLAGS          SDMMC_STATIC_FLAGS
+#define  SDIO_CMD0TIMEOUT           SDMMC_CMD0TIMEOUT
+#define  SD_SDIO_SEND_IF_COND       SD_SDMMC_SEND_IF_COND
+/* alias CMSIS for compatibilities */
+#define  SDIO_IRQn                  SDMMC1_IRQn
+#define  SDIO_IRQHandler            SDMMC1_IRQHandler
+#endif
+
+#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7)
+#define  HAL_SD_CardCIDTypedef       HAL_SD_CardCIDTypeDef
+#define  HAL_SD_CardCSDTypedef       HAL_SD_CardCSDTypeDef
+#define  HAL_SD_CardStatusTypedef    HAL_SD_CardStatusTypeDef
+#define  HAL_SD_CardStateTypedef     HAL_SD_CardStateTypeDef
+#endif
+
+#if defined(STM32H7) || defined(STM32L5)
+#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback   HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
+#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback   HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
+#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback  HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
+#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback  HAL_MMCEx_Write_DMADoubleBuf1CpltCallback
+#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback    HAL_SDEx_Read_DMADoubleBuf0CpltCallback
+#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback    HAL_SDEx_Read_DMADoubleBuf1CpltCallback
+#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback   HAL_SDEx_Write_DMADoubleBuf0CpltCallback
+#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback   HAL_SDEx_Write_DMADoubleBuf1CpltCallback
+#define HAL_SD_DriveTransciver_1_8V_Callback          HAL_SD_DriveTransceiver_1_8V_Callback
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __SMARTCARD_ENABLE_IT           __HAL_SMARTCARD_ENABLE_IT
+#define __SMARTCARD_DISABLE_IT          __HAL_SMARTCARD_DISABLE_IT
+#define __SMARTCARD_ENABLE              __HAL_SMARTCARD_ENABLE
+#define __SMARTCARD_DISABLE             __HAL_SMARTCARD_DISABLE
+#define __SMARTCARD_DMA_REQUEST_ENABLE  __HAL_SMARTCARD_DMA_REQUEST_ENABLE
+#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
+
+#define __HAL_SMARTCARD_GETCLOCKSOURCE  SMARTCARD_GETCLOCKSOURCE
+#define __SMARTCARD_GETCLOCKSOURCE      SMARTCARD_GETCLOCKSOURCE
+
+#define IS_SMARTCARD_ONEBIT_SAMPLING    IS_SMARTCARD_ONE_BIT_SAMPLE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_SMBUS_RESET_CR1           SMBUS_RESET_CR1
+#define __HAL_SMBUS_RESET_CR2           SMBUS_RESET_CR2
+#define __HAL_SMBUS_GENERATE_START      SMBUS_GENERATE_START
+#define __HAL_SMBUS_GET_ADDR_MATCH      SMBUS_GET_ADDR_MATCH
+#define __HAL_SMBUS_GET_DIR             SMBUS_GET_DIR
+#define __HAL_SMBUS_GET_STOP_MODE       SMBUS_GET_STOP_MODE
+#define __HAL_SMBUS_GET_PEC_MODE        SMBUS_GET_PEC_MODE
+#define __HAL_SMBUS_GET_ALERT_ENABLED   SMBUS_GET_ALERT_ENABLED
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_SPI_1LINE_TX              SPI_1LINE_TX
+#define __HAL_SPI_1LINE_RX              SPI_1LINE_RX
+#define __HAL_SPI_RESET_CRC             SPI_RESET_CRC
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_UART_GETCLOCKSOURCE       UART_GETCLOCKSOURCE
+#define __HAL_UART_MASK_COMPUTATION     UART_MASK_COMPUTATION
+#define __UART_GETCLOCKSOURCE           UART_GETCLOCKSOURCE
+#define __UART_MASK_COMPUTATION         UART_MASK_COMPUTATION
+
+#define IS_UART_WAKEUPMETHODE           IS_UART_WAKEUPMETHOD
+
+#define IS_UART_ONEBIT_SAMPLE           IS_UART_ONE_BIT_SAMPLE
+#define IS_UART_ONEBIT_SAMPLING         IS_UART_ONE_BIT_SAMPLE
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __USART_ENABLE_IT               __HAL_USART_ENABLE_IT
+#define __USART_DISABLE_IT              __HAL_USART_DISABLE_IT
+#define __USART_ENABLE                  __HAL_USART_ENABLE
+#define __USART_DISABLE                 __HAL_USART_DISABLE
+
+#define __HAL_USART_GETCLOCKSOURCE      USART_GETCLOCKSOURCE
+#define __USART_GETCLOCKSOURCE          USART_GETCLOCKSOURCE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define USB_EXTI_LINE_WAKEUP                               USB_WAKEUP_EXTI_LINE
+
+#define USB_FS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
+#define USB_FS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_FS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_FS_EXTI_LINE_WAKEUP                            USB_OTG_FS_WAKEUP_EXTI_LINE
+
+#define USB_HS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
+#define USB_HS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_HS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_HS_EXTI_LINE_WAKEUP                            USB_OTG_HS_WAKEUP_EXTI_LINE
+
+#define __HAL_USB_EXTI_ENABLE_IT                           __HAL_USB_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_EXTI_DISABLE_IT                          __HAL_USB_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_EXTI_GET_FLAG                            __HAL_USB_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_EXTI_CLEAR_FLAG                          __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER             __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER            __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER           __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+
+#define __HAL_USB_FS_EXTI_ENABLE_IT                        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_FS_EXTI_DISABLE_IT                       __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_FS_EXTI_GET_FLAG                         __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_FS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define __HAL_USB_HS_EXTI_ENABLE_IT                        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_HS_EXTI_DISABLE_IT                       __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_HS_EXTI_GET_FLAG                         __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_HS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define HAL_PCD_ActiveRemoteWakeup                         HAL_PCD_ActivateRemoteWakeup
+#define HAL_PCD_DeActiveRemoteWakeup                       HAL_PCD_DeActivateRemoteWakeup
+
+#define HAL_PCD_SetTxFiFo                                  HAL_PCDEx_SetTxFiFo
+#define HAL_PCD_SetRxFiFo                                  HAL_PCDEx_SetRxFiFo
+/**
+  * @}
+  */
+
+/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_TIM_SetICPrescalerValue   TIM_SET_ICPRESCALERVALUE
+#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
+
+#define TIM_GET_ITSTATUS                __HAL_TIM_GET_IT_SOURCE
+#define TIM_GET_CLEAR_IT                __HAL_TIM_CLEAR_IT
+
+#define __HAL_TIM_GET_ITSTATUS          __HAL_TIM_GET_IT_SOURCE
+
+#define __HAL_TIM_DIRECTION_STATUS      __HAL_TIM_IS_TIM_COUNTING_DOWN
+#define __HAL_TIM_PRESCALER             __HAL_TIM_SET_PRESCALER
+#define __HAL_TIM_SetCounter            __HAL_TIM_SET_COUNTER
+#define __HAL_TIM_GetCounter            __HAL_TIM_GET_COUNTER
+#define __HAL_TIM_SetAutoreload         __HAL_TIM_SET_AUTORELOAD
+#define __HAL_TIM_GetAutoreload         __HAL_TIM_GET_AUTORELOAD
+#define __HAL_TIM_SetClockDivision      __HAL_TIM_SET_CLOCKDIVISION
+#define __HAL_TIM_GetClockDivision      __HAL_TIM_GET_CLOCKDIVISION
+#define __HAL_TIM_SetICPrescaler        __HAL_TIM_SET_ICPRESCALER
+#define __HAL_TIM_GetICPrescaler        __HAL_TIM_GET_ICPRESCALER
+#define __HAL_TIM_SetCompare            __HAL_TIM_SET_COMPARE
+#define __HAL_TIM_GetCompare            __HAL_TIM_GET_COMPARE
+
+#define TIM_BREAKINPUTSOURCE_DFSDM  TIM_BREAKINPUTSOURCE_DFSDM1
+/**
+  * @}
+  */
+
+/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_ETH_EXTI_ENABLE_IT                   __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_ETH_EXTI_DISABLE_IT                  __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_ETH_EXTI_GET_FLAG                    __HAL_ETH_WAKEUP_EXTI_GET_FLAG
+#define __HAL_ETH_EXTI_CLEAR_FLAG                  __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER     __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER    __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER   __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
+
+#define ETH_PROMISCIOUSMODE_ENABLE   ETH_PROMISCUOUS_MODE_ENABLE
+#define ETH_PROMISCIOUSMODE_DISABLE  ETH_PROMISCUOUS_MODE_DISABLE
+#define IS_ETH_PROMISCIOUS_MODE      IS_ETH_PROMISCUOUS_MODE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_LTDC_LAYER LTDC_LAYER
+#define __HAL_LTDC_RELOAD_CONFIG  __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define SAI_OUTPUTDRIVE_DISABLED          SAI_OUTPUTDRIVE_DISABLE
+#define SAI_OUTPUTDRIVE_ENABLED           SAI_OUTPUTDRIVE_ENABLE
+#define SAI_MASTERDIVIDER_ENABLED         SAI_MASTERDIVIDER_ENABLE
+#define SAI_MASTERDIVIDER_DISABLED        SAI_MASTERDIVIDER_DISABLE
+#define SAI_STREOMODE                     SAI_STEREOMODE
+#define SAI_FIFOStatus_Empty              SAI_FIFOSTATUS_EMPTY
+#define SAI_FIFOStatus_Less1QuarterFull   SAI_FIFOSTATUS_LESS1QUARTERFULL
+#define SAI_FIFOStatus_1QuarterFull       SAI_FIFOSTATUS_1QUARTERFULL
+#define SAI_FIFOStatus_HalfFull           SAI_FIFOSTATUS_HALFFULL
+#define SAI_FIFOStatus_3QuartersFull      SAI_FIFOSTATUS_3QUARTERFULL
+#define SAI_FIFOStatus_Full               SAI_FIFOSTATUS_FULL
+#define IS_SAI_BLOCK_MONO_STREO_MODE      IS_SAI_BLOCK_MONO_STEREO_MODE
+#define SAI_SYNCHRONOUS_EXT               SAI_SYNCHRONOUS_EXT_SAI1
+#define SAI_SYNCEXT_IN_ENABLE             SAI_SYNCEXT_OUTBLOCKA_ENABLE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#if defined(STM32H7)
+#define HAL_SPDIFRX_ReceiveControlFlow      HAL_SPDIFRX_ReceiveCtrlFlow
+#define HAL_SPDIFRX_ReceiveControlFlow_IT   HAL_SPDIFRX_ReceiveCtrlFlow_IT
+#define HAL_SPDIFRX_ReceiveControlFlow_DMA  HAL_SPDIFRX_ReceiveCtrlFlow_DMA
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
+#define HAL_HRTIM_WaveformCounterStart_IT      HAL_HRTIM_WaveformCountStart_IT
+#define HAL_HRTIM_WaveformCounterStart_DMA     HAL_HRTIM_WaveformCountStart_DMA
+#define HAL_HRTIM_WaveformCounterStart         HAL_HRTIM_WaveformCountStart
+#define HAL_HRTIM_WaveformCounterStop_IT       HAL_HRTIM_WaveformCountStop_IT
+#define HAL_HRTIM_WaveformCounterStop_DMA      HAL_HRTIM_WaveformCountStop_DMA
+#define HAL_HRTIM_WaveformCounterStop          HAL_HRTIM_WaveformCountStop
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)
+#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
+#endif /* STM32L4 || STM32F4 || STM32F7 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32_HAL_LEGACY */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h
new file mode 100644
index 00000000..2ee957c3
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h
@@ -0,0 +1,1078 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal.h
+  * @author  MCD Application Team
+  * @brief   This file contains all the functions prototypes for the HAL
+  *          module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_H
+#define STM32H7xx_HAL_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_conf.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup HAL
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup HAL_TICK_FREQ Tick Frequency
+  * @{
+  */
+typedef enum
+{
+  HAL_TICK_FREQ_10HZ         = 100U,
+  HAL_TICK_FREQ_100HZ        = 10U,
+  HAL_TICK_FREQ_1KHZ         = 1U,
+  HAL_TICK_FREQ_DEFAULT      = HAL_TICK_FREQ_1KHZ
+} HAL_TickFreqTypeDef;
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup REV_ID device revision ID
+  * @{
+  */
+#define REV_ID_Y ((uint32_t)0x1003)  /*!< STM32H7 rev.Y */
+#define REV_ID_B ((uint32_t)0x2000)  /*!< STM32H7 rev.B */
+#define REV_ID_X ((uint32_t)0x2001)  /*!< STM32H7 rev.X */
+#define REV_ID_V ((uint32_t)0x2003)  /*!< STM32H7 rev.V */
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
+  * @{
+  */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE0   VREFBUF_CSR_VRS_OUT2   /*!< Voltage reference scale 0 (VREF_OUT2) */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE1   VREFBUF_CSR_VRS_OUT1   /*!< Voltage reference scale 1 (VREF_OUT1) */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE2   VREFBUF_CSR_VRS_OUT4   /*!< Voltage reference scale 2 (VREF_OUT4) */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE3   VREFBUF_CSR_VRS_OUT3   /*!< Voltage reference scale 3 (VREF_OUT3) */
+
+
+#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__)  (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
+                                                     ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1) || \
+                                                     ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE2) || \
+                                                     ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE3))
+
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance
+  * @{
+  */
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE  ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to Voltage reference buffer output */
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE   VREFBUF_CSR_HIZ        /*!< VREF_plus pin is high impedance */
+
+#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__)  (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
+                                                      ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
+
+#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__)  (((__VALUE__) > 0UL) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
+
+/**
+  * @}
+  */
+
+#if !defined(SYSCFG_PMCR_BOOSTEN)
+/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
+  * @{
+  */
+
+/** @brief  Fast-mode Plus driving capability on a specific GPIO
+  */
+#define SYSCFG_FASTMODEPLUS_PB6        SYSCFG_PMCR_I2C_PB6_FMP  /*!< Enable Fast-mode Plus on PB6 */
+#define SYSCFG_FASTMODEPLUS_PB7        SYSCFG_PMCR_I2C_PB7_FMP  /*!< Enable Fast-mode Plus on PB7 */
+#define SYSCFG_FASTMODEPLUS_PB8        SYSCFG_PMCR_I2C_PB8_FMP  /*!< Enable Fast-mode Plus on PB8 */
+#define SYSCFG_FASTMODEPLUS_PB9        SYSCFG_PMCR_I2C_PB9_FMP  /*!< Enable Fast-mode Plus on PB9 */
+
+#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
+
+#endif /* ! SYSCFG_PMCR_BOOSTEN */
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_Ethernet_Config  Ethernet Config
+  * @{
+  */
+#define SYSCFG_ETH_MII                      ((uint32_t)0x00000000)  /*!< Select the Media Independent Interface */
+#define SYSCFG_ETH_RMII                     SYSCFG_PMCR_EPIS_SEL_2  /*!< Select the Reduced Media Independent Interface */
+
+#define IS_SYSCFG_ETHERNET_CONFIG(CONFIG) (((CONFIG) == SYSCFG_ETH_MII)        || \
+                                          ((CONFIG) == SYSCFG_ETH_RMII))
+
+/**
+  * @}
+  */
+
+
+/** @defgroup SYSCFG_Analog_Switch_Config  Analog Switch Config
+  * @{
+  */
+#define SYSCFG_SWITCH_PA0                       SYSCFG_PMCR_PA0SO  /*!< Select PA0 analog switch */
+#define SYSCFG_SWITCH_PA1                       SYSCFG_PMCR_PA1SO  /*!< Select PA1 analog switch */
+#define SYSCFG_SWITCH_PC2                       SYSCFG_PMCR_PC2SO  /*!< Select PC2 analog switch */
+#define SYSCFG_SWITCH_PC3                       SYSCFG_PMCR_PC3SO  /*!< Select PC3 analog switch */
+
+
+#define IS_SYSCFG_ANALOG_SWITCH(SWITCH)    ((((SWITCH) & SYSCFG_SWITCH_PA0) == SYSCFG_SWITCH_PA0)|| \
+                                           (((SWITCH) & SYSCFG_SWITCH_PA1) == SYSCFG_SWITCH_PA1) || \
+                                           (((SWITCH) & SYSCFG_SWITCH_PC2) == SYSCFG_SWITCH_PC2) || \
+                                           (((SWITCH) & SYSCFG_SWITCH_PC3) == SYSCFG_SWITCH_PC3))
+
+
+#define SYSCFG_SWITCH_PA0_OPEN                       SYSCFG_PMCR_PA0SO       /*!< PA0 analog switch opened */
+#define SYSCFG_SWITCH_PA0_CLOSE                      ((uint32_t)0x00000000)  /*!< PA0 analog switch closed */
+#define SYSCFG_SWITCH_PA1_OPEN                       SYSCFG_PMCR_PA1SO       /*!< PA1 analog switch opened */
+#define SYSCFG_SWITCH_PA1_CLOSE                      ((uint32_t)0x00000000)  /*!< PA1 analog switch closed*/
+#define SYSCFG_SWITCH_PC2_OPEN                       SYSCFG_PMCR_PC2SO       /*!< PC2 analog switch opened */
+#define SYSCFG_SWITCH_PC2_CLOSE                      ((uint32_t)0x00000000)  /*!< PC2 analog switch closed */
+#define SYSCFG_SWITCH_PC3_OPEN                       SYSCFG_PMCR_PC3SO       /*!< PC3 analog switch opened */
+#define SYSCFG_SWITCH_PC3_CLOSE                      ((uint32_t)0x00000000)  /*!< PC3 analog switch closed */
+
+#define IS_SYSCFG_SWITCH_STATE(STATE)      ((((STATE) & SYSCFG_SWITCH_PA0_OPEN) == SYSCFG_SWITCH_PA0_OPEN)    || \
+                                           (((STATE) & SYSCFG_SWITCH_PA0_CLOSE) == SYSCFG_SWITCH_PA0_CLOSE)   || \
+                                           (((STATE) & SYSCFG_SWITCH_PA1_OPEN) == SYSCFG_SWITCH_PA1_OPEN)     || \
+                                           (((STATE) & SYSCFG_SWITCH_PA1_CLOSE) == SYSCFG_SWITCH_PA1_CLOSE)   || \
+                                           (((STATE) & SYSCFG_SWITCH_PC2_OPEN) == SYSCFG_SWITCH_PC2_OPEN)     || \
+                                           (((STATE) & SYSCFG_SWITCH_PC2_CLOSE) == SYSCFG_SWITCH_PC2_CLOSE)   || \
+                                           (((STATE) & SYSCFG_SWITCH_PC3_OPEN) == SYSCFG_SWITCH_PC3_OPEN)     || \
+                                           (((STATE) & SYSCFG_SWITCH_PC3_CLOSE) == SYSCFG_SWITCH_PC3_CLOSE))
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_Boot_Config  Boot Config
+  * @{
+  */
+#define SYSCFG_BOOT_ADDR0                    ((uint32_t)0x00000000)  /*!< Select Boot address0 */
+#define SYSCFG_BOOT_ADDR1                    ((uint32_t)0x00000001)  /*!< Select Boot address1 */
+
+#define IS_SYSCFG_BOOT_REGISTER(REGISTER) (((REGISTER) == SYSCFG_BOOT_ADDR0)|| \
+                                          ((REGISTER) == SYSCFG_BOOT_ADDR1))
+
+#define IS_SYSCFG_BOOT_ADDRESS(ADDRESS) ((ADDRESS) < PERIPH_BASE)
+
+/**
+  * @}
+  */
+
+
+/** @defgroup SYSCFG_IOCompenstionCell_Config  IOCompenstionCell Config
+  * @{
+  */
+#define SYSCFG_CELL_CODE                    ((uint32_t)0x00000000)  /*!< Select Code from the cell */
+#define SYSCFG_REGISTER_CODE                 SYSCFG_CCCSR_CS        /*!< Code from the SYSCFG compensation cell code register */
+
+#define IS_SYSCFG_CODE_SELECT(SELECT) (((SELECT) == SYSCFG_CELL_CODE)|| \
+                                        ((SELECT) == SYSCFG_REGISTER_CODE))
+
+#define IS_SYSCFG_CODE_CONFIG(CONFIG) ((CONFIG) < (0x10UL))
+
+/**
+  * @}
+  */
+
+
+
+
+/** @defgroup EXTI_Event_Input_Config  Event Input Config
+  * @{
+  */
+
+#define EXTI_MODE_IT          ((uint32_t)0x00010000)
+#define EXTI_MODE_EVT         ((uint32_t)0x00020000)
+#define EXTI_RISING_EDGE      ((uint32_t)0x00100000)
+#define EXTI_FALLING_EDGE     ((uint32_t)0x00200000)
+
+#define IS_EXTI_EDGE_LINE(EDGE) (((EDGE) == EXTI_RISING_EDGE) || ((EDGE) == EXTI_FALLING_EDGE))
+#define IS_EXTI_MODE_LINE(MODE) (((MODE) == EXTI_MODE_IT) || ((MODE) == EXTI_MODE_EVT))
+
+#define EXTI_LINE0       ((uint32_t)0x00)  /*!< External interrupt LINE 0  */
+#define EXTI_LINE1       ((uint32_t)0x01)  /*!< External interrupt LINE 1  */
+#define EXTI_LINE2       ((uint32_t)0x02)  /*!< External interrupt LINE 2  */
+#define EXTI_LINE3       ((uint32_t)0x03)  /*!< External interrupt LINE 3  */
+#define EXTI_LINE4       ((uint32_t)0x04)  /*!< External interrupt LINE 4  */
+#define EXTI_LINE5       ((uint32_t)0x05)  /*!< External interrupt LINE 5  */
+#define EXTI_LINE6       ((uint32_t)0x06)  /*!< External interrupt LINE 6  */
+#define EXTI_LINE7       ((uint32_t)0x07)  /*!< External interrupt LINE 7  */
+#define EXTI_LINE8       ((uint32_t)0x08)  /*!< External interrupt LINE 8  */
+#define EXTI_LINE9       ((uint32_t)0x09)  /*!< External interrupt LINE 9  */
+#define EXTI_LINE10      ((uint32_t)0x0A)  /*!< External interrupt LINE 10 */
+#define EXTI_LINE11      ((uint32_t)0x0B)  /*!< External interrupt LINE 11 */
+#define EXTI_LINE12      ((uint32_t)0x0C)  /*!< External interrupt LINE 12 */
+#define EXTI_LINE13      ((uint32_t)0x0D)  /*!< External interrupt LINE 13 */
+#define EXTI_LINE14      ((uint32_t)0x0E)  /*!< External interrupt LINE 14 */
+#define EXTI_LINE15      ((uint32_t)0x0F)  /*!< External interrupt LINE 15 */
+#define EXTI_LINE16      ((uint32_t)0x10)
+#define EXTI_LINE17      ((uint32_t)0x11)
+#define EXTI_LINE18      ((uint32_t)0x12)
+#define EXTI_LINE19      ((uint32_t)0x13)
+#define EXTI_LINE20      ((uint32_t)0x14)
+#define EXTI_LINE21      ((uint32_t)0x15)
+#define EXTI_LINE22      ((uint32_t)0x16)
+#define EXTI_LINE23      ((uint32_t)0x17)
+#define EXTI_LINE24      ((uint32_t)0x18)
+#define EXTI_LINE25      ((uint32_t)0x19)
+#define EXTI_LINE26      ((uint32_t)0x1A)
+#define EXTI_LINE27      ((uint32_t)0x1B)
+#define EXTI_LINE28      ((uint32_t)0x1C)
+#define EXTI_LINE29      ((uint32_t)0x1D)
+#define EXTI_LINE30      ((uint32_t)0x1E)
+#define EXTI_LINE31      ((uint32_t)0x1F)
+#define EXTI_LINE32      ((uint32_t)0x20)
+#define EXTI_LINE33      ((uint32_t)0x21)
+#define EXTI_LINE34      ((uint32_t)0x22)
+#define EXTI_LINE35      ((uint32_t)0x23)
+#define EXTI_LINE36      ((uint32_t)0x24)
+#define EXTI_LINE37      ((uint32_t)0x25)
+#define EXTI_LINE38      ((uint32_t)0x26)
+#define EXTI_LINE39      ((uint32_t)0x27)
+
+#define EXTI_LINE40      ((uint32_t)0x28)
+#define EXTI_LINE41      ((uint32_t)0x29)
+#define EXTI_LINE42      ((uint32_t)0x2A)
+#define EXTI_LINE43      ((uint32_t)0x2B)
+#define EXTI_LINE44      ((uint32_t)0x2C)  /* Not available in all family lines */
+/* EXTI_LINE45 Reserved */
+#if defined(DUAL_CORE)
+#define EXTI_LINE46      ((uint32_t)0x2E)
+#else
+/* EXTI_LINE46 Reserved */
+#endif /* DUAL_CORE */
+#define EXTI_LINE47      ((uint32_t)0x2F)
+#define EXTI_LINE48      ((uint32_t)0x30)
+#define EXTI_LINE49      ((uint32_t)0x31)
+#define EXTI_LINE50      ((uint32_t)0x32)
+#define EXTI_LINE51      ((uint32_t)0x33)
+#define EXTI_LINE52      ((uint32_t)0x34)
+#define EXTI_LINE53      ((uint32_t)0x35)
+#define EXTI_LINE54      ((uint32_t)0x36)
+#define EXTI_LINE55      ((uint32_t)0x37)
+#define EXTI_LINE56      ((uint32_t)0x38)
+#define EXTI_LINE57      ((uint32_t)0x39)
+#define EXTI_LINE58      ((uint32_t)0x3A)
+#define EXTI_LINE59      ((uint32_t)0x3B)
+#define EXTI_LINE60      ((uint32_t)0x3C)
+#define EXTI_LINE61      ((uint32_t)0x3D)
+#define EXTI_LINE62      ((uint32_t)0x3E)
+#define EXTI_LINE63      ((uint32_t)0x3F)
+#define EXTI_LINE64      ((uint32_t)0x40)
+#define EXTI_LINE65      ((uint32_t)0x41)
+#define EXTI_LINE66      ((uint32_t)0x42)
+#define EXTI_LINE67      ((uint32_t)0x43)
+#define EXTI_LINE68      ((uint32_t)0x44)
+#define EXTI_LINE69      ((uint32_t)0x45)
+#define EXTI_LINE70      ((uint32_t)0x46)
+#define EXTI_LINE71      ((uint32_t)0x47)
+#define EXTI_LINE72      ((uint32_t)0x48)
+#define EXTI_LINE73      ((uint32_t)0x49)
+#define EXTI_LINE74      ((uint32_t)0x4A)
+#define EXTI_LINE75      ((uint32_t)0x4B)  /* Not available in all family lines */
+#define EXTI_LINE76      ((uint32_t)0x4C)  /* Not available in all family lines */
+#if defined(DUAL_CORE)
+#define EXTI_LINE77      ((uint32_t)0x4D)
+#define EXTI_LINE78      ((uint32_t)0x4E)
+#define EXTI_LINE79      ((uint32_t)0x4F)
+#define EXTI_LINE80      ((uint32_t)0x50)
+#else
+/* EXTI_LINE77 Reserved */
+/* EXTI_LINE78 Reserved */
+/* EXTI_LINE79 Reserved */
+/* EXTI_LINE80 Reserved */
+#endif /* DUAL_CORE */
+/* EXTI_LINE81   Reserved */
+#if defined(DUAL_CORE)
+#define EXTI_LINE82      ((uint32_t)0x52)
+#else
+/* EXTI_LINE82 Reserved */
+#endif /* DUAL_CORE */
+/* EXTI_LINE83   Reserved */
+#if defined(DUAL_CORE)
+#define EXTI_LINE84      ((uint32_t)0x54)
+#else
+/* EXTI_LINE84 Reserved */
+#endif /* DUAL_CORE */
+#define EXTI_LINE85      ((uint32_t)0x55)
+#define EXTI_LINE86      ((uint32_t)0x56)  /* Not available in all family lines */
+#define EXTI_LINE87      ((uint32_t)0x57)
+#define EXTI_LINE88      ((uint32_t)0x58)  /* Not available in all family lines */
+
+#if defined(DUAL_CORE)
+#define IS_HAL_EXTI_CONFIG_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \
+                                ((LINE) == EXTI_LINE2)  || ((LINE) == EXTI_LINE3)   || \
+                                ((LINE) == EXTI_LINE4)  || ((LINE) == EXTI_LINE5)   || \
+                                ((LINE) == EXTI_LINE6)  || ((LINE) == EXTI_LINE7)   || \
+                                ((LINE) == EXTI_LINE8)  || ((LINE) == EXTI_LINE9)   || \
+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11)  || \
+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13)  || \
+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15)  || \
+                                ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17)  || \
+                                ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19)  || \
+                                ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21)  || \
+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE51)  || \
+                                ((LINE) == EXTI_LINE82) || ((LINE) == EXTI_LINE84)  || \
+                                ((LINE) == EXTI_LINE85) || ((LINE) == EXTI_LINE86))
+#else
+#define IS_HAL_EXTI_CONFIG_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1)|| \
+                                ((LINE) == EXTI_LINE2)  || ((LINE) == EXTI_LINE3)   || \
+                                ((LINE) == EXTI_LINE4)  || ((LINE) == EXTI_LINE5)   || \
+                                ((LINE) == EXTI_LINE6)  || ((LINE) == EXTI_LINE7)   || \
+                                ((LINE) == EXTI_LINE8)  || ((LINE) == EXTI_LINE9)   || \
+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
+                                ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
+                                ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
+                                ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE51) || \
+                                ((LINE) == EXTI_LINE85) || ((LINE) == EXTI_LINE86))
+#endif /* DUAL_CORE */
+
+#if defined(DUAL_CORE)
+#define IS_EXTI_ALL_LINE(LINE) (((LINE) == EXTI_LINE0)  || ((LINE) == EXTI_LINE1)  || \
+                                ((LINE) == EXTI_LINE2)  || ((LINE) == EXTI_LINE3)  || \
+                                ((LINE) == EXTI_LINE4)  || ((LINE) == EXTI_LINE5)  || \
+                                ((LINE) == EXTI_LINE6)  || ((LINE) == EXTI_LINE7)  || \
+                                ((LINE) == EXTI_LINE8)  || ((LINE) == EXTI_LINE9)  || \
+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
+                                ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
+                                ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
+                                ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
+                                ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \
+                                ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \
+                                ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \
+                                ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \
+                                ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \
+                                ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \
+                                ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
+                                ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \
+                                ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \
+                                ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \
+                                ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \
+                                ((LINE) == EXTI_LINE44) || ((LINE) == EXTI_LINE46) || \
+                                ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \
+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
+                                ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
+                                ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \
+                                ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \
+                                ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \
+                                ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \
+                                ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \
+                                ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \
+                                ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \
+                                ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \
+                                ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \
+                                ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \
+                                ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \
+                                ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
+                                ((LINE) == EXTI_LINE77) || ((LINE) == EXTI_LINE79) || \
+                                ((LINE) == EXTI_LINE84) || ((LINE) == EXTI_LINE85) || \
+                                ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87) || \
+                                ((LINE) == EXTI_LINE78) || \
+                                ((LINE) == EXTI_LINE80) || ((LINE) == EXTI_LINE82))
+#else
+#define IS_EXTI_ALL_LINE(LINE) (((LINE) == EXTI_LINE0)  || ((LINE) == EXTI_LINE1)  || \
+                                ((LINE) == EXTI_LINE2)  || ((LINE) == EXTI_LINE3)  || \
+                                ((LINE) == EXTI_LINE4)  || ((LINE) == EXTI_LINE5)  || \
+                                ((LINE) == EXTI_LINE6)  || ((LINE) == EXTI_LINE7)  || \
+                                ((LINE) == EXTI_LINE8)  || ((LINE) == EXTI_LINE9)  || \
+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
+                                ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
+                                ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
+                                ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
+                                ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \
+                                ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \
+                                ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \
+                                ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \
+                                ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \
+                                ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \
+                                ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
+                                ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \
+                                ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \
+                                ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \
+                                ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \
+                                ((LINE) == EXTI_LINE44) || \
+                                ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \
+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
+                                ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
+                                ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \
+                                ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \
+                                ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \
+                                ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \
+                                ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \
+                                ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \
+                                ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \
+                                ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \
+                                ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \
+                                ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \
+                                ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \
+                                ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
+                                ((LINE) == EXTI_LINE85) || \
+                                ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87) || \
+                                ((LINE) == EXTI_LINE88))
+#endif /*DUAL_CORE*/
+
+#if defined(DUAL_CORE)
+#define IS_EXTI_D1_LINE(LINE) (((LINE) == EXTI_LINE0)  || ((LINE) == EXTI_LINE1)  || \
+                                ((LINE) == EXTI_LINE2)  || ((LINE) == EXTI_LINE3)  || \
+                                ((LINE) == EXTI_LINE4)  || ((LINE) == EXTI_LINE5)  || \
+                                ((LINE) == EXTI_LINE6)  || ((LINE) == EXTI_LINE7)  || \
+                                ((LINE) == EXTI_LINE8)  || ((LINE) == EXTI_LINE9)  || \
+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
+                                ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
+                                ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
+                                ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
+                                ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \
+                                ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \
+                                ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \
+                                ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \
+                                ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \
+                                ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \
+                                ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
+                                ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \
+                                ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \
+                                ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \
+                                ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \
+                                ((LINE) == EXTI_LINE44) || ((LINE) == EXTI_LINE46) || \
+                                ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \
+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
+                                ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
+                                ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \
+                                ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \
+                                ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \
+                                ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \
+                                ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \
+                                ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \
+                                ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \
+                                ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \
+                                ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \
+                                ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \
+                                ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \
+                                ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
+                                ((LINE) == EXTI_LINE77) || ((LINE) == EXTI_LINE79) || \
+                                ((LINE) == EXTI_LINE84) || ((LINE) == EXTI_LINE85) || \
+                                ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87))
+#else
+#define IS_EXTI_D1_LINE(LINE) (((LINE) == EXTI_LINE0)  || ((LINE) == EXTI_LINE1)  || \
+                                ((LINE) == EXTI_LINE2)  || ((LINE) == EXTI_LINE3)  || \
+                                ((LINE) == EXTI_LINE4)  || ((LINE) == EXTI_LINE5)  || \
+                                ((LINE) == EXTI_LINE6)  || ((LINE) == EXTI_LINE7)  || \
+                                ((LINE) == EXTI_LINE8)  || ((LINE) == EXTI_LINE9)  || \
+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
+                                ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
+                                ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
+                                ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
+                                ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \
+                                ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \
+                                ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \
+                                ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \
+                                ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \
+                                ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \
+                                ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
+                                ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \
+                                ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \
+                                ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \
+                                ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \
+                                ((LINE) == EXTI_LINE44) || \
+                                ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \
+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
+                                ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
+                                ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \
+                                ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \
+                                ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \
+                                ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \
+                                ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \
+                                ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \
+                                ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \
+                                ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \
+                                ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \
+                                ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \
+                                ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \
+                                ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
+                                ((LINE) == EXTI_LINE85) || \
+                                ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87) || \
+                                ((LINE) == EXTI_LINE88))
+#endif /*DUAL_CORE*/
+
+#if defined(DUAL_CORE)
+#define IS_EXTI_D2_LINE(LINE) (((LINE) == EXTI_LINE0)  || ((LINE) == EXTI_LINE1)    || \
+                                ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3)   || \
+                                ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5)   || \
+                                ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7)   || \
+                                ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9)   || \
+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
+                                ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
+                                ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
+                                ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
+                                ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \
+                                ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \
+                                ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \
+                                ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \
+                                ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \
+                                ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \
+                                ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
+                                ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \
+                                ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \
+                                ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \
+                                ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \
+                                ((LINE) == EXTI_LINE44) || ((LINE) == EXTI_LINE46) || \
+                                ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \
+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
+                                ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
+                                ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \
+                                ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \
+                                ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \
+                                ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \
+                                ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \
+                                ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \
+                                ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \
+                                ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \
+                                ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \
+                                ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \
+                                ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \
+                                ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
+                                ((LINE) == EXTI_LINE78) || ((LINE) == EXTI_LINE80) || \
+                                ((LINE) == EXTI_LINE82) || ((LINE) == EXTI_LINE85) || \
+                                ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87))
+#endif /*DUAL_CORE*/
+
+#if defined(DUAL_CORE)
+#define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1)    || \
+                                ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3)   || \
+                                ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5)   || \
+                                ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7)   || \
+                                ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9)   || \
+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
+                                ((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || \
+                                ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE25) || \
+                                ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
+                                ((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || \
+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
+                                ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
+                                ((LINE) == EXTI_LINE53))
+#elif (POWER_DOMAINS_NUMBER == 3U)
+#define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1)    || \
+                                ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3)   || \
+                                ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5)   || \
+                                ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7)   || \
+                                ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9)   || \
+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
+                                ((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || \
+                                ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE25) || \
+                                ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
+                                ((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || \
+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
+                                ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
+                                ((LINE) == EXTI_LINE53))
+#else
+#define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1)    || \
+                                ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3)   || \
+                                ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5)   || \
+                                ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7)   || \
+                                ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9)   || \
+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
+                                ((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || \
+                                ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE25) || \
+                                ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
+                                ((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || \
+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
+                                ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE88))
+#endif /*DUAL_CORE*/
+
+
+#define  BDMA_CH6_CLEAR           ((uint32_t)0x00000000)   /*!< BDMA ch6 event selected as D3 domain pendclear source*/
+#define  BDMA_CH7_CLEAR           ((uint32_t)0x00000001)   /*!< BDMA ch7 event selected as D3 domain pendclear source*/
+#if defined (LPTIM4)
+#define  LPTIM4_OUT_CLEAR         ((uint32_t)0x00000002)   /*!< LPTIM4 out selected as D3 domain pendclear source*/
+#else
+#define  LPTIM2_OUT_CLEAR         ((uint32_t)0x00000002)   /*!< LPTIM2 out selected as D3 domain pendclear source*/
+#endif /* LPTIM4 */
+#if defined (LPTIM5)
+#define  LPTIM5_OUT_CLEAR         ((uint32_t)0x00000003)   /*!< LPTIM5 out selected as D3 domain pendclear source*/
+#else
+#define  LPTIM3_OUT_CLEAR         ((uint32_t)0x00000003)   /*!< LPTIM3 out selected as D3 domain pendclear source*/
+#endif /* LPTIM5 */
+#if defined (LPTIM4) && defined (LPTIM5)
+#define IS_EXTI_D3_CLEAR(SOURCE) (((SOURCE) == BDMA_CH6_CLEAR) || ((SOURCE) == BDMA_CH7_CLEAR)    || \
+                                 ((SOURCE) == LPTIM4_OUT_CLEAR) || ((SOURCE) == LPTIM5_OUT_CLEAR))
+#else
+#define IS_EXTI_D3_CLEAR(SOURCE) (((SOURCE) == BDMA_CH6_CLEAR) || ((SOURCE) == BDMA_CH7_CLEAR)    || \
+                                 ((SOURCE) == LPTIM2_OUT_CLEAR) || ((SOURCE) == LPTIM3_OUT_CLEAR))
+#endif /* LPTIM4 LPTIM5 */
+/**
+  * @}
+  */
+
+
+/** @defgroup FMC_SwapBankMapping_Config  SwapBankMapping Config
+  * @{
+  */
+#define FMC_SWAPBMAP_DISABLE             (0x00000000U)
+#define FMC_SWAPBMAP_SDRAM_SRAM          FMC_BCR1_BMAP_0
+#define FMC_SWAPBMAP_SDRAMB2             FMC_BCR1_BMAP_1
+
+#define IS_FMC_SWAPBMAP_MODE(__MODE__) (((__MODE__) == FMC_SWAPBMAP_DISABLE)    || \
+                                        ((__MODE__) == FMC_SWAPBMAP_SDRAM_SRAM) || \
+                                        ((__MODE__) == FMC_SWAPBMAP_SDRAMB2))
+/**
+  * @}
+  */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup ART_Exported_Macros ART Exported Macros
+  * @{
+  */
+#if defined(DUAL_CORE)
+
+/** @brief  ART Enable Macro.
+  *         Enable the Cortex-M4 ART cache.
+  */
+#define __HAL_ART_ENABLE()   SET_BIT(ART->CTR, ART_CTR_EN)
+
+/** @brief  ART Disable Macro.
+  *         Disable the Cortex-M4 ART cache.
+  */
+#define __HAL_ART_DISABLE()   CLEAR_BIT(ART->CTR, ART_CTR_EN)
+
+/** @brief  ART Cache BaseAddress Config.
+  *         Configure the Cortex-M4 ART cache Base Address.
+  */
+#define __HAL_ART_CONFIG_BASE_ADDRESS(__BASE_ADDRESS__)   MODIFY_REG(ART->CTR, ART_CTR_PCACHEADDR, (((__BASE_ADDRESS__) >> 12U) & 0x000FFF00UL))
+
+#endif /* DUAL_CORE */
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
+  * @{
+  */
+
+/** @brief  SYSCFG Break AXIRAM double ECC lock.
+  *         Enable and lock the connection of AXIRAM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_AXISRAM_DBL_ECC_LOCK()     SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML)
+
+/** @brief  SYSCFG Break ITCM double ECC lock.
+  *         Enable and lock the connection of ITCM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_ITCM_DBL_ECC_LOCK()        SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_ITCML)
+
+/** @brief  SYSCFG Break DTCM double ECC lock.
+  *         Enable and lock the connection of DTCM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_DTCM_DBL_ECC_LOCK()        SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_DTCML)
+
+/** @brief  SYSCFG Break SRAM1 double ECC lock.
+  *         Enable and lock the connection of SRAM1 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_SRAM1_DBL_ECC_LOCK()       SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM1L)
+
+/** @brief  SYSCFG Break SRAM2 double ECC lock.
+  *         Enable and lock the connection of SRAM2 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_SRAM2_DBL_ECC_LOCK()       SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM2L)
+
+/** @brief  SYSCFG Break SRAM3 double ECC lock.
+  *         Enable and lock the connection of SRAM3 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_SRAM3_DBL_ECC_LOCK()       SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM3L)
+
+/** @brief  SYSCFG Break SRAM4 double ECC lock.
+  *         Enable and lock the connection of SRAM4 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_SRAM4_DBL_ECC_LOCK()       SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM4L)
+
+/** @brief  SYSCFG Break Backup SRAM double ECC lock.
+  *         Enable and lock the connection of Backup SRAM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_BKRAM_DBL_ECC_LOCK()       SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_BKRAML)
+
+/** @brief  SYSCFG Break Cortex-M7 Lockup lock.
+  *         Enable and lock the connection of Cortex-M7 LOCKUP output to TIM1/8/15/16/17 and HRTIMER Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_CM7_LOCKUP_LOCK()          SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_CM7L)
+
+/** @brief  SYSCFG Break FLASH double ECC lock.
+  *         Enable and lock the connection of Flash double ECC error connection to TIM1/8/15/16/17 and HRTIMER Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_FLASH_DBL_ECC_LOCK()       SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_FLASHL)
+
+/** @brief  SYSCFG Break PVD lock.
+  *         Enable and lock the PVD connection to Timer1/8/15/16/17 and HRTIMER Break input, as well as the PVDE and PLS[2:0] in the PWR_CR1 register.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_PVD_LOCK()                 SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_PVDL)
+
+#if defined(DUAL_CORE)
+/** @brief  SYSCFG Break Cortex-M4 Lockup lock.
+  *         Enable and lock the connection of Cortex-M4 LOCKUP output to TIM1/8/15/16/17 and HRTIMER Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+            This feature is available on STM32H7 rev.B and above.
+  */
+#define __HAL_SYSCFG_BREAK_CM4_LOCKUP_LOCK()          SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_CM4L)
+#endif /* DUAL_CORE */
+
+#if !defined(SYSCFG_PMCR_BOOSTEN)
+/** @brief  Fast-mode Plus driving capability enable/disable macros
+  * @param __FASTMODEPLUS__  This parameter can be a value of :
+  *     @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6
+  *     @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7
+  *     @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8
+  *     @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9
+  */
+#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)  do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
+                                                                SET_BIT(SYSCFG->PMCR, (__FASTMODEPLUS__));\
+                                                               }while(0)
+
+#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
+                                                                CLEAR_BIT(SYSCFG->PMCR, (__FASTMODEPLUS__));\
+                                                               }while(0)
+
+#endif /* !SYSCFG_PMCR_BOOSTEN */
+/**
+  * @}
+  */
+
+/** @brief  Freeze/Unfreeze Peripherals in Debug mode
+  */
+#define __HAL_DBGMCU_FREEZE_WWDG1()          (DBGMCU->APB3FZ1 |= (DBGMCU_APB3FZ1_DBG_WWDG1))
+
+#define __HAL_DBGMCU_FREEZE_TIM2()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM2))
+#define __HAL_DBGMCU_FREEZE_TIM3()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM3))
+#define __HAL_DBGMCU_FREEZE_TIM4()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM4))
+#define __HAL_DBGMCU_FREEZE_TIM5()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM5))
+#define __HAL_DBGMCU_FREEZE_TIM6()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM6))
+#define __HAL_DBGMCU_FREEZE_TIM7()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM7))
+#define __HAL_DBGMCU_FREEZE_TIM12()          (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM12))
+#define __HAL_DBGMCU_FREEZE_TIM13()          (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM13))
+#define __HAL_DBGMCU_FREEZE_TIM14()          (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM14))
+#define __HAL_DBGMCU_FREEZE_LPTIM1()         (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_LPTIM1))
+#define __HAL_DBGMCU_FREEZE_I2C1()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C1))
+#define __HAL_DBGMCU_FREEZE_I2C2()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C2))
+#define __HAL_DBGMCU_FREEZE_I2C3()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C3))
+#define __HAL_DBGMCU_FREEZE_FDCAN()          (DBGMCU->APB1HFZ1 |= (DBGMCU_APB1HFZ1_DBG_FDCAN))
+
+
+#define __HAL_DBGMCU_FREEZE_TIM1()           (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM1))
+#define __HAL_DBGMCU_FREEZE_TIM8()           (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM8))
+#define __HAL_DBGMCU_FREEZE_TIM15()          (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM15))
+#define __HAL_DBGMCU_FREEZE_TIM16()          (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM16))
+#define __HAL_DBGMCU_FREEZE_TIM17()          (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM17))
+#define __HAL_DBGMCU_FREEZE_HRTIM()          (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_HRTIM))
+
+#define __HAL_DBGMCU_FREEZE_I2C4()           (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_I2C4))
+#define __HAL_DBGMCU_FREEZE_LPTIM2()         (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM2))
+#define __HAL_DBGMCU_FREEZE_LPTIM3()         (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM3))
+#define __HAL_DBGMCU_FREEZE_LPTIM4()         (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM4))
+#define __HAL_DBGMCU_FREEZE_LPTIM5()         (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM5))
+#define __HAL_DBGMCU_FREEZE_RTC()            (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_RTC))
+#define __HAL_DBGMCU_FREEZE_IWDG1()          (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_IWDG1))
+
+
+#define __HAL_DBGMCU_UnFreeze_WWDG1()          (DBGMCU->APB3FZ1  &= ~ (DBGMCU_APB3FZ1_DBG_WWDG1))
+
+#define __HAL_DBGMCU_UnFreeze_TIM2()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM2))
+#define __HAL_DBGMCU_UnFreeze_TIM3()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM3))
+#define __HAL_DBGMCU_UnFreeze_TIM4()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM4))
+#define __HAL_DBGMCU_UnFreeze_TIM5()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM5))
+#define __HAL_DBGMCU_UnFreeze_TIM6()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM6))
+#define __HAL_DBGMCU_UnFreeze_TIM7()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM7))
+#define __HAL_DBGMCU_UnFreeze_TIM12()          (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM12))
+#define __HAL_DBGMCU_UnFreeze_TIM13()          (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM13))
+#define __HAL_DBGMCU_UnFreeze_TIM14()          (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM14))
+#define __HAL_DBGMCU_UnFreeze_LPTIM1()         (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_LPTIM1))
+#define __HAL_DBGMCU_UnFreeze_I2C1()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_I2C1))
+#define __HAL_DBGMCU_UnFreeze_I2C2()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_I2C2))
+#define __HAL_DBGMCU_UnFreeze_I2C3()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_I2C3))
+#define __HAL_DBGMCU_UnFreeze_FDCAN()          (DBGMCU->APB1HFZ1  &= ~ (DBGMCU_APB1HFZ1_DBG_FDCAN))
+
+
+#define __HAL_DBGMCU_UnFreeze_TIM1()           (DBGMCU->APB2FZ1  &= ~ (DBGMCU_APB2FZ1_DBG_TIM1))
+#define __HAL_DBGMCU_UnFreeze_TIM8()           (DBGMCU->APB2FZ1  &= ~ (DBGMCU_APB2FZ1_DBG_TIM8))
+#define __HAL_DBGMCU_UnFreeze_TIM15()          (DBGMCU->APB2FZ1  &= ~ (DBGMCU_APB2FZ1_DBG_TIM15))
+#define __HAL_DBGMCU_UnFreeze_TIM16()          (DBGMCU->APB2FZ1  &= ~ (DBGMCU_APB2FZ1_DBG_TIM16))
+#define __HAL_DBGMCU_UnFreeze_TIM17()          (DBGMCU->APB2FZ1  &= ~ (DBGMCU_APB2FZ1_DBG_TIM17))
+#define __HAL_DBGMCU_UnFreeze_HRTIM()          (DBGMCU->APB2FZ1  &= ~ (DBGMCU_APB2FZ1_DBG_HRTIM))
+
+#define __HAL_DBGMCU_UnFreeze_I2C4()           (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_I2C4))
+#define __HAL_DBGMCU_UnFreeze_LPTIM2()         (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM2))
+#define __HAL_DBGMCU_UnFreeze_LPTIM3()         (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM3))
+#define __HAL_DBGMCU_UnFreeze_LPTIM4()         (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM4))
+#define __HAL_DBGMCU_UnFreeze_LPTIM5()         (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM5))
+#define __HAL_DBGMCU_UnFreeze_RTC()            (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_RTC))
+#define __HAL_DBGMCU_UnFreeze_IWDG1()          (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_IWDG1))
+
+
+#if defined(DUAL_CORE)
+#define __HAL_DBGMCU_FREEZE2_IWDG2()          (DBGMCU->APB4FZ2  |= (DBGMCU_APB4FZ2_DBG_IWDG2))
+#define __HAL_DBGMCU_FREEZE2_WWDG2()          (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_WWDG2))
+
+#define __HAL_DBGMCU_UnFreeze2_IWDG2()        (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_IWDG2))
+#define __HAL_DBGMCU_UnFreeze2_WWDG2()        (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_WWDG2))
+
+
+#define __HAL_DBGMCU_FREEZE2_WWDG1()          (DBGMCU->APB3FZ2 |= (DBGMCU_APB3FZ2_DBG_WWDG1))
+
+#define __HAL_DBGMCU_FREEZE2_TIM2()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM2))
+#define __HAL_DBGMCU_FREEZE2_TIM3()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM3))
+#define __HAL_DBGMCU_FREEZE2_TIM4()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM4))
+#define __HAL_DBGMCU_FREEZE2_TIM5()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM5))
+#define __HAL_DBGMCU_FREEZE2_TIM6()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM6))
+#define __HAL_DBGMCU_FREEZE2_TIM7()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM7))
+#define __HAL_DBGMCU_FREEZE2_TIM12()          (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM12))
+#define __HAL_DBGMCU_FREEZE2_TIM13()          (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM13))
+#define __HAL_DBGMCU_FREEZE2_TIM14()          (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM14))
+#define __HAL_DBGMCU_FREEZE2_LPTIM1()         (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_LPTIM1))
+#define __HAL_DBGMCU_FREEZE2_I2C1()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_I2C1))
+#define __HAL_DBGMCU_FREEZE2_I2C2()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_I2C2))
+#define __HAL_DBGMCU_FREEZE2_I2C3()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_I2C3))
+#define __HAL_DBGMCU_FREEZE2_FDCAN()          (DBGMCU->APB1HFZ2 |= (DBGMCU_APB1HFZ2_DBG_FDCAN))
+
+
+#define __HAL_DBGMCU_FREEZE2_TIM1()           (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM1))
+#define __HAL_DBGMCU_FREEZE2_TIM8()           (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM8))
+#define __HAL_DBGMCU_FREEZE2_TIM15()          (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM15))
+#define __HAL_DBGMCU_FREEZE2_TIM16()          (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM16))
+#define __HAL_DBGMCU_FREEZE2_TIM17()          (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM17))
+#define __HAL_DBGMCU_FREEZE2_HRTIM()          (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_HRTIM))
+
+#define __HAL_DBGMCU_FREEZE2_I2C4()           (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_I2C4))
+#define __HAL_DBGMCU_FREEZE2_LPTIM2()         (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM2))
+#define __HAL_DBGMCU_FREEZE2_LPTIM3()         (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM3))
+#define __HAL_DBGMCU_FREEZE2_LPTIM4()         (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM4))
+#define __HAL_DBGMCU_FREEZE2_LPTIM5()         (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM5))
+#define __HAL_DBGMCU_FREEZE2_RTC()            (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_RTC))
+#define __HAL_DBGMCU_FREEZE2_IWDG1()          (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_IWDG1))
+
+#define __HAL_DBGMCU_UnFreeze2_WWDG1()          (DBGMCU->APB3FZ2  &= ~ (DBGMCU_APB3FZ2_DBG_WWDG1))
+
+#define __HAL_DBGMCU_UnFreeze2_TIM2()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM2))
+#define __HAL_DBGMCU_UnFreeze2_TIM3()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM3))
+#define __HAL_DBGMCU_UnFreeze2_TIM4()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM4))
+#define __HAL_DBGMCU_UnFreeze2_TIM5()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM5))
+#define __HAL_DBGMCU_UnFreeze2_TIM6()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM6))
+#define __HAL_DBGMCU_UnFreeze2_TIM7()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM7))
+#define __HAL_DBGMCU_UnFreeze2_TIM12()          (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM12))
+#define __HAL_DBGMCU_UnFreeze2_TIM13()          (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM13))
+#define __HAL_DBGMCU_UnFreeze2_TIM14()          (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM14))
+#define __HAL_DBGMCU_UnFreeze2_LPTIM1()         (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_LPTIM1))
+#define __HAL_DBGMCU_UnFreeze2_I2C1()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_I2C1))
+#define __HAL_DBGMCU_UnFreeze2_I2C2()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_I2C2))
+#define __HAL_DBGMCU_UnFreeze2_I2C3()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_I2C3))
+#define __HAL_DBGMCU_UnFreeze2_FDCAN()          (DBGMCU->APB1HFZ2  &= ~ (DBGMCU_APB1HFZ2_DBG_FDCAN))
+
+
+#define __HAL_DBGMCU_UnFreeze2_TIM1()           (DBGMCU->APB2FZ2  &= ~ (DBGMCU_APB2FZ2_DBG_TIM1))
+#define __HAL_DBGMCU_UnFreeze2_TIM8()           (DBGMCU->APB2FZ2  &= ~ (DBGMCU_APB2FZ2_DBG_TIM8))
+#define __HAL_DBGMCU_UnFreeze2_TIM15()          (DBGMCU->APB2FZ2  &= ~ (DBGMCU_APB2FZ2_DBG_TIM15))
+#define __HAL_DBGMCU_UnFreeze2_TIM16()          (DBGMCU->APB2FZ2  &= ~ (DBGMCU_APB2FZ2_DBG_TIM16))
+#define __HAL_DBGMCU_UnFreeze2_TIM17()          (DBGMCU->APB2FZ2  &= ~ (DBGMCU_APB2FZ2_DBG_TIM17))
+#define __HAL_DBGMCU_UnFreeze2_HRTIM()          (DBGMCU->APB2FZ2  &= ~ (DBGMCU_APB2FZ2_DBG_HRTIM))
+
+#define __HAL_DBGMCU_UnFreeze2_I2C4()           (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_I2C4))
+#define __HAL_DBGMCU_UnFreeze2_LPTIM2()         (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM2))
+#define __HAL_DBGMCU_UnFreeze2_LPTIM3()         (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM3))
+#define __HAL_DBGMCU_UnFreeze2_LPTIM4()         (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM4))
+#define __HAL_DBGMCU_UnFreeze2_LPTIM5()         (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM5))
+#define __HAL_DBGMCU_UnFreeze2_RTC()            (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_RTC))
+#define __HAL_DBGMCU_UnFreeze2_IWDG1()          (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_IWDG1))
+
+#endif /*DUAL_CORE*/
+
+/** @defgroup HAL_Private_Macros HAL Private Macros
+  * @{
+  */
+#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ)  || \
+                           ((FREQ) == HAL_TICK_FREQ_100HZ) || \
+                           ((FREQ) == HAL_TICK_FREQ_1KHZ))
+/**
+  * @}
+  */
+
+/* Exported variables --------------------------------------------------------*/
+
+/** @addtogroup HAL_Exported_Variables
+  * @{
+  */
+extern __IO uint32_t uwTick;
+extern uint32_t uwTickPrio;
+extern HAL_TickFreqTypeDef uwTickFreq;
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization and de-initialization functions  ******************************/
+HAL_StatusTypeDef HAL_Init(void);
+HAL_StatusTypeDef HAL_DeInit(void);
+void HAL_MspInit(void);
+void HAL_MspDeInit(void);
+HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
+
+/* Peripheral Control functions  ************************************************/
+void HAL_IncTick(void);
+void HAL_Delay(uint32_t Delay);
+uint32_t HAL_GetTick(void);
+uint32_t HAL_GetTickPrio(void);
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
+HAL_TickFreqTypeDef HAL_GetTickFreq(void);
+void HAL_SuspendTick(void);
+void HAL_ResumeTick(void);
+uint32_t HAL_GetHalVersion(void);
+uint32_t HAL_GetREVID(void);
+uint32_t HAL_GetDEVID(void);
+uint32_t HAL_GetUIDw0(void);
+uint32_t HAL_GetUIDw1(void);
+uint32_t HAL_GetUIDw2(void);
+#if defined(SYSCFG_PMCR_EPIS_SEL)
+void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface);
+#endif /* SYSCFG_PMCR_EPIS_SEL */
+void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState );
+#if defined(SYSCFG_PMCR_BOOSTEN)
+void HAL_SYSCFG_EnableBOOST(void);
+void HAL_SYSCFG_DisableBOOST(void);
+#endif /* SYSCFG_PMCR_BOOSTEN */
+
+#if defined (SYSCFG_UR2_BOOT_ADD0) ||  defined (SYSCFG_UR2_BCM7_ADD0)
+void HAL_SYSCFG_CM7BootAddConfig(uint32_t BootRegister, uint32_t BootAddress);
+#endif /* SYSCFG_UR2_BOOT_ADD0 || SYSCFG_UR2_BCM7_ADD0*/
+
+#if defined(DUAL_CORE)
+void HAL_SYSCFG_CM4BootAddConfig(uint32_t BootRegister, uint32_t BootAddress);
+void HAL_SYSCFG_EnableCM7BOOT(void);
+void HAL_SYSCFG_DisableCM7BOOT(void);
+void HAL_SYSCFG_EnableCM4BOOT(void);
+void HAL_SYSCFG_DisableCM4BOOT(void);
+#endif /*DUAL_CORE*/
+void HAL_EnableCompensationCell(void);
+void HAL_DisableCompensationCell(void);
+void HAL_SYSCFG_EnableIOSpeedOptimize(void);
+void HAL_SYSCFG_DisableIOSpeedOptimize(void);
+void HAL_SYSCFG_CompensationCodeSelect(uint32_t SYSCFG_CompCode);
+void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode);
+#if defined(SYSCFG_CCCR_NCC_MMC)
+void HAL_SYSCFG_VDDMMC_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode);
+#endif /* SYSCFG_CCCR_NCC_MMC */
+void HAL_EnableDBGSleepMode(void);
+void HAL_DisableDBGSleepMode(void);
+void HAL_EnableDBGStopMode(void);
+void HAL_DisableDBGStopMode(void);
+void HAL_EnableDBGStandbyMode(void);
+void HAL_DisableDBGStandbyMode(void);
+#if defined(DUAL_CORE)
+void HAL_EnableDomain2DBGSleepMode(void);
+void HAL_DisableDomain2DBGSleepMode(void);
+void HAL_EnableDomain2DBGStopMode(void);
+void HAL_DisableDomain2DBGStopMode(void);
+void HAL_EnableDomain2DBGStandbyMode(void);
+void HAL_DisableDomain2DBGStandbyMode(void);
+#endif /*DUAL_CORE*/
+void HAL_EnableDomain3DBGStopMode(void);
+void HAL_DisableDomain3DBGStopMode(void);
+void HAL_EnableDomain3DBGStandbyMode(void);
+void HAL_DisableDomain3DBGStandbyMode(void);
+void HAL_EXTI_EdgeConfig(uint32_t EXTI_Line , uint32_t EXTI_Edge );
+void HAL_EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
+#if defined(DUAL_CORE)
+void HAL_EXTI_D2_ClearFlag(uint32_t EXTI_Line);
+#endif /*DUAL_CORE*/
+void HAL_EXTI_D1_ClearFlag(uint32_t EXTI_Line);
+void HAL_EXTI_D1_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode,  uint32_t EXTI_LineCmd);
+#if defined(DUAL_CORE)
+void HAL_EXTI_D2_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode,  uint32_t EXTI_LineCmd);
+#endif /*DUAL_CORE*/
+void HAL_EXTI_D3_EventInputConfig(uint32_t EXTI_Line, uint32_t EXTI_LineCmd , uint32_t EXTI_ClearSrc);
+void HAL_SetFMCMemorySwappingConfig(uint32_t BankMapConfig);
+uint32_t HAL_GetFMCMemorySwappingConfig(void);
+void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
+void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
+void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
+HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
+void HAL_SYSCFG_DisableVREFBUF(void);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h
new file mode 100644
index 00000000..4eca4390
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h
@@ -0,0 +1,461 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_cortex.h
+  * @author  MCD Application Team
+  * @brief   Header file of CORTEX HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_CORTEX_H
+#define STM32H7xx_HAL_CORTEX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup CORTEX
+  * @{
+  */
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Types Cortex Exported Types
+  * @{
+  */
+
+#if (__MPU_PRESENT == 1)
+/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
+  * @brief  MPU Region initialization structure
+  * @{
+  */
+typedef struct
+{
+  uint8_t                Enable;                /*!< Specifies the status of the region.
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */
+  uint8_t                Number;                /*!< Specifies the number of the region to protect.
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */
+  uint32_t               BaseAddress;           /*!< Specifies the base address of the region to protect.                           */
+  uint8_t                Size;                  /*!< Specifies the size of the region to protect.
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Size                   */
+  uint8_t                SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable.
+                                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */
+  uint8_t                TypeExtField;          /*!< Specifies the TEX field level.
+                                                     This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                    */
+  uint8_t                AccessPermission;      /*!< Specifies the region access permission type.
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */
+  uint8_t                DisableExec;           /*!< Specifies the instruction access status.
+                                                     This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */
+  uint8_t                IsShareable;           /*!< Specifies the shareability status of the protected region.
+                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */
+  uint8_t                IsCacheable;           /*!< Specifies the cacheable status of the region protected.
+                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable              */
+  uint8_t                IsBufferable;          /*!< Specifies the bufferable status of the protected region.
+                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable             */
+}MPU_Region_InitTypeDef;
+/**
+  * @}
+  */
+#endif /* __MPU_PRESENT */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
+  * @{
+  */
+
+/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
+  * @{
+  */
+#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority
+                                                                 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority
+                                                                 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority
+                                                                 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority
+                                                                 1 bits for subpriority */
+#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority
+                                                                 0 bits for subpriority */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
+  * @{
+  */
+#define SYSTICK_CLKSOURCE_HCLK_DIV8    ((uint32_t)0x00000000)
+#define SYSTICK_CLKSOURCE_HCLK         ((uint32_t)0x00000004)
+
+/**
+  * @}
+  */
+
+#if (__MPU_PRESENT == 1)
+/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
+  * @{
+  */
+#define  MPU_HFNMI_PRIVDEF_NONE      ((uint32_t)0x00000000)
+#define  MPU_HARDFAULT_NMI           ((uint32_t)0x00000002)
+#define  MPU_PRIVILEGED_DEFAULT      ((uint32_t)0x00000004)
+#define  MPU_HFNMI_PRIVDEF           ((uint32_t)0x00000006)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
+  * @{
+  */
+#define  MPU_REGION_ENABLE     ((uint8_t)0x01)
+#define  MPU_REGION_DISABLE    ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
+  * @{
+  */
+#define  MPU_INSTRUCTION_ACCESS_ENABLE      ((uint8_t)0x00)
+#define  MPU_INSTRUCTION_ACCESS_DISABLE     ((uint8_t)0x01)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
+  * @{
+  */
+#define  MPU_ACCESS_SHAREABLE        ((uint8_t)0x01)
+#define  MPU_ACCESS_NOT_SHAREABLE    ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
+  * @{
+  */
+#define  MPU_ACCESS_CACHEABLE         ((uint8_t)0x01)
+#define  MPU_ACCESS_NOT_CACHEABLE     ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
+  * @{
+  */
+#define  MPU_ACCESS_BUFFERABLE         ((uint8_t)0x01)
+#define  MPU_ACCESS_NOT_BUFFERABLE     ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
+  * @{
+  */
+#define  MPU_TEX_LEVEL0    ((uint8_t)0x00)
+#define  MPU_TEX_LEVEL1    ((uint8_t)0x01)
+#define  MPU_TEX_LEVEL2    ((uint8_t)0x02)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
+  * @{
+  */
+#define   MPU_REGION_SIZE_32B      ((uint8_t)0x04)
+#define   MPU_REGION_SIZE_64B      ((uint8_t)0x05)
+#define   MPU_REGION_SIZE_128B     ((uint8_t)0x06)
+#define   MPU_REGION_SIZE_256B     ((uint8_t)0x07)
+#define   MPU_REGION_SIZE_512B     ((uint8_t)0x08)
+#define   MPU_REGION_SIZE_1KB      ((uint8_t)0x09)
+#define   MPU_REGION_SIZE_2KB      ((uint8_t)0x0A)
+#define   MPU_REGION_SIZE_4KB      ((uint8_t)0x0B)
+#define   MPU_REGION_SIZE_8KB      ((uint8_t)0x0C)
+#define   MPU_REGION_SIZE_16KB     ((uint8_t)0x0D)
+#define   MPU_REGION_SIZE_32KB     ((uint8_t)0x0E)
+#define   MPU_REGION_SIZE_64KB     ((uint8_t)0x0F)
+#define   MPU_REGION_SIZE_128KB    ((uint8_t)0x10)
+#define   MPU_REGION_SIZE_256KB    ((uint8_t)0x11)
+#define   MPU_REGION_SIZE_512KB    ((uint8_t)0x12)
+#define   MPU_REGION_SIZE_1MB      ((uint8_t)0x13)
+#define   MPU_REGION_SIZE_2MB      ((uint8_t)0x14)
+#define   MPU_REGION_SIZE_4MB      ((uint8_t)0x15)
+#define   MPU_REGION_SIZE_8MB      ((uint8_t)0x16)
+#define   MPU_REGION_SIZE_16MB     ((uint8_t)0x17)
+#define   MPU_REGION_SIZE_32MB     ((uint8_t)0x18)
+#define   MPU_REGION_SIZE_64MB     ((uint8_t)0x19)
+#define   MPU_REGION_SIZE_128MB    ((uint8_t)0x1A)
+#define   MPU_REGION_SIZE_256MB    ((uint8_t)0x1B)
+#define   MPU_REGION_SIZE_512MB    ((uint8_t)0x1C)
+#define   MPU_REGION_SIZE_1GB      ((uint8_t)0x1D)
+#define   MPU_REGION_SIZE_2GB      ((uint8_t)0x1E)
+#define   MPU_REGION_SIZE_4GB      ((uint8_t)0x1F)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
+  * @{
+  */
+#define  MPU_REGION_NO_ACCESS      ((uint8_t)0x00)
+#define  MPU_REGION_PRIV_RW        ((uint8_t)0x01)
+#define  MPU_REGION_PRIV_RW_URO    ((uint8_t)0x02)
+#define  MPU_REGION_FULL_ACCESS    ((uint8_t)0x03)
+#define  MPU_REGION_PRIV_RO        ((uint8_t)0x05)
+#define  MPU_REGION_PRIV_RO_URO    ((uint8_t)0x06)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
+  * @{
+  */
+#define  MPU_REGION_NUMBER0    ((uint8_t)0x00)
+#define  MPU_REGION_NUMBER1    ((uint8_t)0x01)
+#define  MPU_REGION_NUMBER2    ((uint8_t)0x02)
+#define  MPU_REGION_NUMBER3    ((uint8_t)0x03)
+#define  MPU_REGION_NUMBER4    ((uint8_t)0x04)
+#define  MPU_REGION_NUMBER5    ((uint8_t)0x05)
+#define  MPU_REGION_NUMBER6    ((uint8_t)0x06)
+#define  MPU_REGION_NUMBER7    ((uint8_t)0x07)
+#if !defined(CORE_CM4)
+#define  MPU_REGION_NUMBER8    ((uint8_t)0x08)
+#define  MPU_REGION_NUMBER9    ((uint8_t)0x09)
+#define  MPU_REGION_NUMBER10   ((uint8_t)0x0A)
+#define  MPU_REGION_NUMBER11   ((uint8_t)0x0B)
+#define  MPU_REGION_NUMBER12   ((uint8_t)0x0C)
+#define  MPU_REGION_NUMBER13   ((uint8_t)0x0D)
+#define  MPU_REGION_NUMBER14   ((uint8_t)0x0E)
+#define  MPU_REGION_NUMBER15   ((uint8_t)0x0F)
+#endif /* !defined(CORE_CM4) */
+
+/**
+  * @}
+  */
+#endif /* __MPU_PRESENT */
+
+/**
+  * @}
+  */
+
+
+/* Exported Macros -----------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+
+/** @defgroup CORTEX_CPU_Identifier CORTEX_CPU_Identifier
+  * @{
+  */
+#define CM7_CPUID        ((uint32_t)0x00000003)
+
+#if defined(DUAL_CORE)
+#define CM4_CPUID        ((uint32_t)0x00000001)
+#endif /*DUAL_CORE*/
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CORTEX_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup CORTEX_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SystemReset(void);
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
+/**
+  * @}
+  */
+
+/** @addtogroup CORTEX_Exported_Functions_Group2
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+#if (__MPU_PRESENT == 1)
+void HAL_MPU_Enable(uint32_t MPU_Control);
+void HAL_MPU_Disable(void);
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
+#endif /* __MPU_PRESENT */
+uint32_t HAL_NVIC_GetPriorityGrouping(void);
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
+void HAL_SYSTICK_IRQHandler(void);
+void HAL_SYSTICK_Callback(void);
+uint32_t HAL_GetCurrentCPUID(void);
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
+  * @{
+  */
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_1) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_2) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_3) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10UL)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY)         ((PRIORITY) < 0x10UL)
+
+#define IS_NVIC_DEVICE_IRQ(IRQ)                (((int32_t)IRQ) >= 0x00)
+
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
+                                       ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
+
+#if (__MPU_PRESENT == 1)
+#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
+                                     ((STATE) == MPU_REGION_DISABLE))
+
+#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
+                                          ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
+
+#define IS_MPU_ACCESS_SHAREABLE(STATE)   (((STATE) == MPU_ACCESS_SHAREABLE) || \
+                                          ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
+
+#define IS_MPU_ACCESS_CACHEABLE(STATE)   (((STATE) == MPU_ACCESS_CACHEABLE) || \
+                                          ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
+
+#define IS_MPU_ACCESS_BUFFERABLE(STATE)   (((STATE) == MPU_ACCESS_BUFFERABLE) || \
+                                          ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
+
+#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0)  || \
+                                ((TYPE) == MPU_TEX_LEVEL1)  || \
+                                ((TYPE) == MPU_TEX_LEVEL2))
+
+#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS)   || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RW)     || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
+                                                  ((TYPE) == MPU_REGION_FULL_ACCESS) || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RO)     || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RO_URO))
+
+#if !defined(CORE_CM4)
+#define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER1)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER2)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER3)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER4)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER5)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER6)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER7)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER8)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER9)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER10) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER11) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER12) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER13) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER14) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER15))
+#else
+#define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER1)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER2)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER3)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER4)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER5)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER6)  || \
+                                         ((NUMBER) == MPU_REGION_NUMBER7))
+#endif /* !defined(CORE_CM4) */
+
+#define IS_MPU_REGION_SIZE(SIZE)    (((SIZE) == MPU_REGION_SIZE_32B)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_64B)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_128B)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_256B)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_512B)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_1KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_2KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_4KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_8KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_16KB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_32KB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_64KB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_128KB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_256KB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_512KB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_1MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_2MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_4MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_8MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_16MB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_32MB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_64MB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_128MB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_256MB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_512MB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_1GB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_2GB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_4GB))
+
+#define IS_MPU_SUB_REGION_DISABLE(SUBREGION)  ((SUBREGION) < (uint16_t)0x00FF)
+#endif /* __MPU_PRESENT */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_CORTEX_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h
new file mode 100644
index 00000000..fce605de
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h
@@ -0,0 +1,188 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_def.h
+  * @author  MCD Application Team
+  * @brief   This file contains HAL common defines, enumeration, macros and
+  *          structures definitions.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_DEF
+#define STM32H7xx_HAL_DEF
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx.h"
+#include "Legacy/stm32_hal_legacy.h"
+#include <stddef.h>
+#include <math.h>
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+  * @brief  HAL Status structures definition
+  */
+typedef enum
+{
+  HAL_OK       = 0x00,
+  HAL_ERROR    = 0x01,
+  HAL_BUSY     = 0x02,
+  HAL_TIMEOUT  = 0x03
+} HAL_StatusTypeDef;
+
+/**
+  * @brief  HAL Lock structures definition
+  */
+typedef enum
+{
+  HAL_UNLOCKED = 0x00,
+  HAL_LOCKED   = 0x01
+} HAL_LockTypeDef;
+
+/* Exported macro ------------------------------------------------------------*/
+
+#define HAL_MAX_DELAY      0xFFFFFFFFU
+
+#define HAL_IS_BIT_SET(REG, BIT)         (((REG) & (BIT)) == (BIT))
+#define HAL_IS_BIT_CLR(REG, BIT)         (((REG) & (BIT)) == 0U)
+
+#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__)               \
+                        do{                                                      \
+                              (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
+                              (__DMA_HANDLE__).Parent = (__HANDLE__);             \
+                          } while(0)
+
+#define UNUSED(x) ((void)(x))
+
+/** @brief Reset the Handle's State field.
+  * @param __HANDLE__: specifies the Peripheral Handle.
+  * @note  This macro can be used for the following purpose: 
+  *          - When the Handle is declared as local variable; before passing it as parameter
+  *            to HAL_PPP_Init() for the first time, it is mandatory to use this macro 
+  *            to set to 0 the Handle's "State" field.
+  *            Otherwise, "State" field may have any random value and the first time the function 
+  *            HAL_PPP_Init() is called, the low level hardware initialization will be missed
+  *            (i.e. HAL_PPP_MspInit() will not be executed).
+  *          - When there is a need to reconfigure the low level hardware: instead of calling
+  *            HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
+  *            In this later function, when the Handle's "State" field is set to 0, it will execute the function
+  *            HAL_PPP_MspInit() which will reconfigure the low level hardware.
+  * @retval None
+  */
+#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
+
+#if (USE_RTOS == 1)
+  #error " USE_RTOS should be 0 in the current HAL release "
+#else
+  #define __HAL_LOCK(__HANDLE__)                                           \
+                                do{                                        \
+                                    if((__HANDLE__)->Lock == HAL_LOCKED)   \
+                                    {                                      \
+                                       return HAL_BUSY;                    \
+                                    }                                      \
+                                    else                                   \
+                                    {                                      \
+                                       (__HANDLE__)->Lock = HAL_LOCKED;    \
+                                    }                                      \
+                                  }while (0)
+
+  #define __HAL_UNLOCK(__HANDLE__)                                          \
+                                  do{                                       \
+                                      (__HANDLE__)->Lock = HAL_UNLOCKED;    \
+                                    }while (0)
+#endif /* USE_RTOS */
+
+#if  defined ( __GNUC__ )
+  #ifndef __weak
+    #define __weak   __attribute__((weak))
+  #endif /* __weak */
+  #ifndef __packed
+    #define __packed __attribute__((__packed__))
+  #endif /* __packed */
+#endif /* __GNUC__ */
+
+
+/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
+#if defined   (__GNUC__)        /* GNU Compiler */
+  #ifndef __ALIGN_END
+    #define __ALIGN_END    __attribute__ ((aligned (4)))
+  #endif /* __ALIGN_END */
+  #ifndef __ALIGN_BEGIN
+    #define __ALIGN_BEGIN
+  #endif /* __ALIGN_BEGIN */
+#else
+  #ifndef __ALIGN_END
+    #define __ALIGN_END
+  #endif /* __ALIGN_END */
+  #ifndef __ALIGN_BEGIN
+    #if defined   (__CC_ARM)      /* ARM Compiler */
+      #define __ALIGN_BEGIN    __align(4)
+    #elif defined (__ICCARM__)    /* IAR Compiler */
+      #define __ALIGN_BEGIN
+    #endif /* __CC_ARM */
+  #endif /* __ALIGN_BEGIN */
+#endif /* __GNUC__ */
+
+/* Macro to get variable aligned on 32-bytes,needed for cache maintenance purpose */
+#if defined   (__GNUC__)        /* GNU Compiler */
+  #define ALIGN_32BYTES(buf)  buf __attribute__ ((aligned (32)))                                    
+#elif defined (__ICCARM__)    /* IAR Compiler */
+  #define ALIGN_32BYTES(buf) _Pragma("data_alignment=32") buf  
+#elif defined   (__CC_ARM)      /* ARM Compiler */
+  #define ALIGN_32BYTES(buf) __align(32) buf  
+#endif
+
+/**
+  * @brief  __RAM_FUNC definition
+  */
+#if defined ( __CC_ARM   )
+/* ARM Compiler
+   ------------
+   RAM functions are defined using the toolchain options.
+   Functions that are executed in RAM should reside in a separate source module.
+   Using the 'Options for File' dialog you can simply change the 'Code / Const'
+   area of a module to a memory space in physical RAM.
+   Available memory areas are declared in the 'Target' tab of the 'Options for Target'
+   dialog.
+*/
+#define __RAM_FUNC
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+   ---------------
+   RAM functions are defined using a specific toolchain keyword "__ramfunc".
+*/
+#define __RAM_FUNC __ramfunc
+
+#elif defined   (  __GNUC__  )
+/* GNU Compiler
+   ------------
+  RAM functions are defined using a specific toolchain attribute
+   "__attribute__((section(".RamFunc")))".
+*/
+#define __RAM_FUNC __attribute__((section(".RamFunc")))
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_DEF */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h
new file mode 100644
index 00000000..36d553b0
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h
@@ -0,0 +1,1290 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_dma.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMA HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_DMA_H
+#define STM32H7xx_HAL_DMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DMA
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Types DMA Exported Types
+  * @brief    DMA Exported Types
+  * @{
+  */
+
+/**
+  * @brief  DMA Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t Request;               /*!< Specifies the request selected for the specified stream.
+                                           This parameter can be a value of @ref DMA_Request_selection              */
+
+  uint32_t Direction;            /*!< Specifies if the data will be transferred from memory to peripheral,
+                                      from memory to memory or from peripheral to memory.
+                                      This parameter can be a value of @ref DMA_Data_transfer_direction              */
+
+  uint32_t PeriphInc;            /*!< Specifies whether the Peripheral address register should be incremented or not.
+                                      This parameter can be a value of @ref DMA_Peripheral_incremented_mode          */
+
+  uint32_t MemInc;               /*!< Specifies whether the memory address register should be incremented or not.
+                                      This parameter can be a value of @ref DMA_Memory_incremented_mode              */
+
+  uint32_t PeriphDataAlignment;  /*!< Specifies the Peripheral data width.
+                                      This parameter can be a value of @ref DMA_Peripheral_data_size                 */
+
+  uint32_t MemDataAlignment;     /*!< Specifies the Memory data width.
+                                      This parameter can be a value of @ref DMA_Memory_data_size                     */
+
+  uint32_t Mode;                 /*!< Specifies the operation mode of the DMAy Streamx.
+                                      This parameter can be a value of @ref DMA_mode
+                                      @note The circular buffer mode cannot be used if the memory-to-memory
+                                            data transfer is configured on the selected Stream                        */
+
+  uint32_t Priority;             /*!< Specifies the software priority for the DMAy Streamx.
+                                      This parameter can be a value of @ref DMA_Priority_level                        */
+
+  uint32_t FIFOMode;             /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
+                                      This parameter can be a value of @ref DMA_FIFO_direct_mode
+                                      @note The Direct mode (FIFO mode disabled) cannot be used if the
+                                            memory-to-memory data transfer is configured on the selected stream       */
+
+  uint32_t FIFOThreshold;        /*!< Specifies the FIFO threshold level.
+                                      This parameter can be a value of @ref DMA_FIFO_threshold_level                  */
+
+  uint32_t MemBurst;             /*!< Specifies the Burst transfer configuration for the memory transfers.
+                                      It specifies the amount of data to be transferred in a single non interruptible
+                                      transaction.
+                                      This parameter can be a value of @ref DMA_Memory_burst
+                                      @note The burst mode is possible only if the address Increment mode is enabled. */
+
+  uint32_t PeriphBurst;          /*!< Specifies the Burst transfer configuration for the peripheral transfers.
+                                      It specifies the amount of data to be transferred in a single non interruptible
+                                      transaction.
+                                      This parameter can be a value of @ref DMA_Peripheral_burst
+                                      @note The burst mode is possible only if the address Increment mode is enabled. */
+}DMA_InitTypeDef;
+
+/**
+  * @brief  HAL DMA State structures definition
+  */
+typedef enum
+{
+  HAL_DMA_STATE_RESET             = 0x00U,  /*!< DMA not yet initialized or disabled */
+  HAL_DMA_STATE_READY             = 0x01U,  /*!< DMA initialized and ready for use   */
+  HAL_DMA_STATE_BUSY              = 0x02U,  /*!< DMA process is ongoing              */
+  HAL_DMA_STATE_ERROR             = 0x03U,  /*!< DMA error state                     */
+  HAL_DMA_STATE_ABORT             = 0x04U,  /*!< DMA Abort state                     */
+}HAL_DMA_StateTypeDef;
+
+/**
+  * @brief  HAL DMA Transfer complete level structure definition
+  */
+typedef enum
+{
+  HAL_DMA_FULL_TRANSFER      = 0x00U,    /*!< Full transfer     */
+  HAL_DMA_HALF_TRANSFER      = 0x01U,    /*!< Half Transfer     */
+}HAL_DMA_LevelCompleteTypeDef;
+
+/**
+  * @brief  HAL DMA Callbacks IDs structure definition
+  */
+typedef enum
+{
+  HAL_DMA_XFER_CPLT_CB_ID          = 0x00U,    /*!< Full transfer     */
+  HAL_DMA_XFER_HALFCPLT_CB_ID      = 0x01U,    /*!< Half Transfer     */
+  HAL_DMA_XFER_M1CPLT_CB_ID        = 0x02U,    /*!< M1 Full Transfer  */
+  HAL_DMA_XFER_M1HALFCPLT_CB_ID    = 0x03U,    /*!< M1 Half Transfer  */
+  HAL_DMA_XFER_ERROR_CB_ID         = 0x04U,    /*!< Error             */
+  HAL_DMA_XFER_ABORT_CB_ID         = 0x05U,    /*!< Abort             */
+  HAL_DMA_XFER_ALL_CB_ID           = 0x06U     /*!< All               */
+}HAL_DMA_CallbackIDTypeDef;
+
+/**
+  * @brief  DMA handle Structure definition
+  */
+typedef struct __DMA_HandleTypeDef
+{
+  void                            *Instance;                                                        /*!< Register base address                         */
+
+  DMA_InitTypeDef                 Init;                                                             /*!< DMA communication parameters                  */
+
+  HAL_LockTypeDef                 Lock;                                                             /*!< DMA locking object                            */
+
+  __IO HAL_DMA_StateTypeDef       State;                                                            /*!< DMA transfer state                            */
+
+  void                            *Parent;                                                          /*!< Parent object state                           */
+
+  void                            (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);         /*!< DMA transfer complete callback                */
+
+  void                            (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);     /*!< DMA Half transfer complete callback           */
+
+  void                            (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma);       /*!< DMA transfer complete Memory1 callback        */
+
+  void                            (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);   /*!< DMA transfer Half complete Memory1 callback   */
+
+  void                            (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);        /*!< DMA transfer error callback                   */
+
+  void                            (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma);        /*!< DMA transfer Abort callback                   */
+
+ __IO uint32_t                    ErrorCode;                                                        /*!< DMA Error code                                */
+
+ uint32_t                         StreamBaseAddress;                                                /*!< DMA Stream Base Address                       */
+
+ uint32_t                         StreamIndex;                                                      /*!< DMA Stream Index                              */
+
+ DMAMUX_Channel_TypeDef           *DMAmuxChannel;                                                   /*!< DMAMUX Channel Base Address                   */
+
+ DMAMUX_ChannelStatus_TypeDef     *DMAmuxChannelStatus;                                             /*!< DMAMUX Channels Status Base Address           */
+
+ uint32_t                         DMAmuxChannelStatusMask;                                          /*!< DMAMUX Channel Status Mask                    */
+
+
+ DMAMUX_RequestGen_TypeDef        *DMAmuxRequestGen;                                                /*!< DMAMUX request generator Base Address         */
+
+ DMAMUX_RequestGenStatus_TypeDef  *DMAmuxRequestGenStatus;                                          /*!< DMAMUX request generator Status Address       */
+
+ uint32_t                         DMAmuxRequestGenStatusMask;                                       /*!< DMAMUX request generator Status mask          */
+
+}DMA_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Constants DMA Exported Constants
+  * @brief    DMA Exported constants
+  * @{
+  */
+
+/** @defgroup DMA_Error_Code DMA Error Code
+  * @brief    DMA Error Code
+  * @{
+  */
+#define HAL_DMA_ERROR_NONE            (0x00000000U)    /*!< No error                                */
+#define HAL_DMA_ERROR_TE              (0x00000001U)    /*!< Transfer error                          */
+#define HAL_DMA_ERROR_FE              (0x00000002U)    /*!< FIFO error                              */
+#define HAL_DMA_ERROR_DME             (0x00000004U)    /*!< Direct Mode error                       */
+#define HAL_DMA_ERROR_TIMEOUT         (0x00000020U)    /*!< Timeout error                           */
+#define HAL_DMA_ERROR_PARAM           (0x00000040U)    /*!< Parameter error                         */
+#define HAL_DMA_ERROR_NO_XFER         (0x00000080U)    /*!< Abort requested with no Xfer ongoing    */
+#define HAL_DMA_ERROR_NOT_SUPPORTED   (0x00000100U)    /*!< Not supported mode                      */
+#define HAL_DMA_ERROR_SYNC            (0x00000200U)    /*!< DMAMUX sync overrun  error              */
+#define HAL_DMA_ERROR_REQGEN          (0x00000400U)    /*!< DMAMUX request generator overrun  error */
+#define HAL_DMA_ERROR_BUSY            (0x00000800U)    /*!< DMA Busy                          error */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Request_selection DMA Request selection
+  * @brief    DMA Request selection
+  * @{
+  */
+/* DMAMUX1 requests */
+#define DMA_REQUEST_MEM2MEM          0U  /*!< memory to memory transfer   */
+
+#define DMA_REQUEST_GENERATOR0       1U  /*!< DMAMUX1 request generator 0 */
+#define DMA_REQUEST_GENERATOR1       2U  /*!< DMAMUX1 request generator 1 */
+#define DMA_REQUEST_GENERATOR2       3U  /*!< DMAMUX1 request generator 2 */
+#define DMA_REQUEST_GENERATOR3       4U  /*!< DMAMUX1 request generator 3 */
+#define DMA_REQUEST_GENERATOR4       5U  /*!< DMAMUX1 request generator 4 */
+#define DMA_REQUEST_GENERATOR5       6U  /*!< DMAMUX1 request generator 5 */
+#define DMA_REQUEST_GENERATOR6       7U  /*!< DMAMUX1 request generator 6 */
+#define DMA_REQUEST_GENERATOR7       8U  /*!< DMAMUX1 request generator 7 */
+
+#define DMA_REQUEST_ADC1             9U  /*!< DMAMUX1 ADC1 request */
+#define DMA_REQUEST_ADC2             10U /*!< DMAMUX1 ADC2 request */
+
+#define DMA_REQUEST_TIM1_CH1         11U  /*!< DMAMUX1 TIM1 CH1 request  */
+#define DMA_REQUEST_TIM1_CH2         12U  /*!< DMAMUX1 TIM1 CH2 request  */
+#define DMA_REQUEST_TIM1_CH3         13U  /*!< DMAMUX1 TIM1 CH3 request  */
+#define DMA_REQUEST_TIM1_CH4         14U  /*!< DMAMUX1 TIM1 CH4 request  */
+#define DMA_REQUEST_TIM1_UP          15U  /*!< DMAMUX1 TIM1 UP request   */
+#define DMA_REQUEST_TIM1_TRIG        16U  /*!< DMAMUX1 TIM1 TRIG request */
+#define DMA_REQUEST_TIM1_COM         17U  /*!< DMAMUX1 TIM1 COM request  */
+
+#define DMA_REQUEST_TIM2_CH1         18U  /*!< DMAMUX1 TIM2 CH1 request  */
+#define DMA_REQUEST_TIM2_CH2         19U  /*!< DMAMUX1 TIM2 CH2 request  */
+#define DMA_REQUEST_TIM2_CH3         20U  /*!< DMAMUX1 TIM2 CH3 request  */
+#define DMA_REQUEST_TIM2_CH4         21U  /*!< DMAMUX1 TIM2 CH4 request  */
+#define DMA_REQUEST_TIM2_UP          22U  /*!< DMAMUX1 TIM2 UP request   */
+
+#define DMA_REQUEST_TIM3_CH1         23U  /*!< DMAMUX1 TIM3 CH1 request  */
+#define DMA_REQUEST_TIM3_CH2         24U  /*!< DMAMUX1 TIM3 CH2 request  */
+#define DMA_REQUEST_TIM3_CH3         25U  /*!< DMAMUX1 TIM3 CH3 request  */
+#define DMA_REQUEST_TIM3_CH4         26U  /*!< DMAMUX1 TIM3 CH4 request  */
+#define DMA_REQUEST_TIM3_UP          27U  /*!< DMAMUX1 TIM3 UP request   */
+#define DMA_REQUEST_TIM3_TRIG        28U  /*!< DMAMUX1 TIM3 TRIG request */
+
+#define DMA_REQUEST_TIM4_CH1         29U  /*!< DMAMUX1 TIM4 CH1 request  */
+#define DMA_REQUEST_TIM4_CH2         30U  /*!< DMAMUX1 TIM4 CH2 request  */
+#define DMA_REQUEST_TIM4_CH3         31U  /*!< DMAMUX1 TIM4 CH3 request  */
+#define DMA_REQUEST_TIM4_UP          32U  /*!< DMAMUX1 TIM4 UP request   */
+
+#define DMA_REQUEST_I2C1_RX          33U  /*!< DMAMUX1 I2C1 RX request   */
+#define DMA_REQUEST_I2C1_TX          34U  /*!< DMAMUX1 I2C1 TX request   */
+#define DMA_REQUEST_I2C2_RX          35U  /*!< DMAMUX1 I2C2 RX request   */
+#define DMA_REQUEST_I2C2_TX          36U  /*!< DMAMUX1 I2C2 TX request   */
+
+#define DMA_REQUEST_SPI1_RX          37U  /*!< DMAMUX1 SPI1 RX request   */
+#define DMA_REQUEST_SPI1_TX          38U  /*!< DMAMUX1 SPI1 TX request   */
+#define DMA_REQUEST_SPI2_RX          39U  /*!< DMAMUX1 SPI2 RX request   */
+#define DMA_REQUEST_SPI2_TX          40U  /*!< DMAMUX1 SPI2 TX request   */
+
+#define DMA_REQUEST_USART1_RX        41U  /*!< DMAMUX1 USART1 RX request */
+#define DMA_REQUEST_USART1_TX        42U  /*!< DMAMUX1 USART1 TX request */
+#define DMA_REQUEST_USART2_RX        43U  /*!< DMAMUX1 USART2 RX request */
+#define DMA_REQUEST_USART2_TX        44U  /*!< DMAMUX1 USART2 TX request */
+#define DMA_REQUEST_USART3_RX        45U  /*!< DMAMUX1 USART3 RX request */
+#define DMA_REQUEST_USART3_TX        46U  /*!< DMAMUX1 USART3 TX request */
+
+#define DMA_REQUEST_TIM8_CH1         47U  /*!< DMAMUX1 TIM8 CH1 request  */
+#define DMA_REQUEST_TIM8_CH2         48U  /*!< DMAMUX1 TIM8 CH2 request  */
+#define DMA_REQUEST_TIM8_CH3         49U  /*!< DMAMUX1 TIM8 CH3 request  */
+#define DMA_REQUEST_TIM8_CH4         50U  /*!< DMAMUX1 TIM8 CH4 request  */
+#define DMA_REQUEST_TIM8_UP          51U  /*!< DMAMUX1 TIM8 UP request   */
+#define DMA_REQUEST_TIM8_TRIG        52U  /*!< DMAMUX1 TIM8 TRIG request */
+#define DMA_REQUEST_TIM8_COM         53U  /*!< DMAMUX1 TIM8 COM request  */
+
+#define DMA_REQUEST_TIM5_CH1         55U  /*!< DMAMUX1 TIM5 CH1 request  */
+#define DMA_REQUEST_TIM5_CH2         56U  /*!< DMAMUX1 TIM5 CH2 request  */
+#define DMA_REQUEST_TIM5_CH3         57U  /*!< DMAMUX1 TIM5 CH3 request  */
+#define DMA_REQUEST_TIM5_CH4         58U  /*!< DMAMUX1 TIM5 CH4 request  */
+#define DMA_REQUEST_TIM5_UP          59U  /*!< DMAMUX1 TIM5 UP request   */
+#define DMA_REQUEST_TIM5_TRIG        60U  /*!< DMAMUX1 TIM5 TRIG request */
+
+#define DMA_REQUEST_SPI3_RX          61U  /*!< DMAMUX1 SPI3 RX request   */
+#define DMA_REQUEST_SPI3_TX          62U  /*!< DMAMUX1 SPI3 TX request   */
+
+#define DMA_REQUEST_UART4_RX         63U  /*!< DMAMUX1 UART4 RX request */
+#define DMA_REQUEST_UART4_TX         64U  /*!< DMAMUX1 UART4 TX request */
+#define DMA_REQUEST_UART5_RX         65U  /*!< DMAMUX1 UART5 RX request */
+#define DMA_REQUEST_UART5_TX         66U  /*!< DMAMUX1 UART5 TX request */
+
+#define DMA_REQUEST_DAC1_CH1         67U  /*!< DMAMUX1 DAC1 Channel 1 request */
+#define DMA_REQUEST_DAC1_CH2         68U  /*!< DMAMUX1 DAC1 Channel 2 request */
+
+#define DMA_REQUEST_TIM6_UP          69U  /*!< DMAMUX1 TIM6 UP request   */
+#define DMA_REQUEST_TIM7_UP          70U  /*!< DMAMUX1 TIM7 UP request   */
+
+#define DMA_REQUEST_USART6_RX        71U  /*!< DMAMUX1 USART6 RX request */
+#define DMA_REQUEST_USART6_TX        72U  /*!< DMAMUX1 USART6 TX request */
+
+#define DMA_REQUEST_I2C3_RX          73U  /*!< DMAMUX1 I2C3 RX request   */
+#define DMA_REQUEST_I2C3_TX          74U  /*!< DMAMUX1 I2C3 TX request   */
+
+#if defined (PSSI)
+#define DMA_REQUEST_DCMI_PSSI        75U  /*!< DMAMUX1 DCMI/PSSI request    */
+#define DMA_REQUEST_DCMI             DMA_REQUEST_DCMI_PSSI /* Legacy define */
+#else
+#define DMA_REQUEST_DCMI             75U  /*!< DMAMUX1 DCMI request         */
+#endif /* PSSI */
+
+#define DMA_REQUEST_CRYP_IN          76U  /*!< DMAMUX1 CRYP IN request   */
+#define DMA_REQUEST_CRYP_OUT         77U  /*!< DMAMUX1 CRYP OUT request  */
+
+#define DMA_REQUEST_HASH_IN          78U  /*!< DMAMUX1 HASH IN request   */
+
+#define DMA_REQUEST_UART7_RX         79U  /*!< DMAMUX1 UART7 RX request  */
+#define DMA_REQUEST_UART7_TX         80U  /*!< DMAMUX1 UART7 TX request  */
+#define DMA_REQUEST_UART8_RX         81U  /*!< DMAMUX1 UART8 RX request  */
+#define DMA_REQUEST_UART8_TX         82U  /*!< DMAMUX1 UART8 TX request  */
+
+#define DMA_REQUEST_SPI4_RX          83U  /*!< DMAMUX1 SPI4 RX request   */
+#define DMA_REQUEST_SPI4_TX          84U  /*!< DMAMUX1 SPI4 TX request   */
+#define DMA_REQUEST_SPI5_RX          85U  /*!< DMAMUX1 SPI5 RX request   */
+#define DMA_REQUEST_SPI5_TX          86U  /*!< DMAMUX1 SPI5 TX request   */
+
+#define DMA_REQUEST_SAI1_A           87U  /*!< DMAMUX1 SAI1 A request    */
+#define DMA_REQUEST_SAI1_B           88U  /*!< DMAMUX1 SAI1 B request    */
+#define DMA_REQUEST_SAI2_A           89U  /*!< DMAMUX1 SAI2 A request    */
+#define DMA_REQUEST_SAI2_B           90U  /*!< DMAMUX1 SAI2 B request    */
+
+#define DMA_REQUEST_SWPMI_RX         91U  /*!< DMAMUX1 SWPMI RX request  */
+#define DMA_REQUEST_SWPMI_TX         92U  /*!< DMAMUX1 SWPMI TX request  */
+
+#define DMA_REQUEST_SPDIF_RX_DT      93U  /*!< DMAMUX1 SPDIF RXDT request*/
+#define DMA_REQUEST_SPDIF_RX_CS      94U  /*!< DMAMUX1 SPDIF RXCS request*/
+
+#if defined(HRTIM1)
+#define DMA_REQUEST_HRTIM_MASTER     95U  /*!< DMAMUX1 HRTIM1 Master request 1 */
+#define DMA_REQUEST_HRTIM_TIMER_A    96U  /*!< DMAMUX1 HRTIM1 TimerA request 2 */
+#define DMA_REQUEST_HRTIM_TIMER_B    97U  /*!< DMAMUX1 HRTIM1 TimerB request 3 */
+#define DMA_REQUEST_HRTIM_TIMER_C    98U  /*!< DMAMUX1 HRTIM1 TimerC request 4 */
+#define DMA_REQUEST_HRTIM_TIMER_D    99U  /*!< DMAMUX1 HRTIM1 TimerD request 5 */
+#define DMA_REQUEST_HRTIM_TIMER_E   100U  /*!< DMAMUX1 HRTIM1 TimerE request 6 */
+#endif /* HRTIM1 */
+
+#define DMA_REQUEST_DFSDM1_FLT0     101U  /*!< DMAMUX1 DFSDM Filter0 request */
+#define DMA_REQUEST_DFSDM1_FLT1     102U  /*!< DMAMUX1 DFSDM Filter1 request */
+#define DMA_REQUEST_DFSDM1_FLT2     103U  /*!< DMAMUX1 DFSDM Filter2 request */
+#define DMA_REQUEST_DFSDM1_FLT3     104U  /*!< DMAMUX1 DFSDM Filter3 request */
+
+#define DMA_REQUEST_TIM15_CH1       105U  /*!< DMAMUX1 TIM15 CH1 request  */
+#define DMA_REQUEST_TIM15_UP        106U  /*!< DMAMUX1 TIM15 UP request   */
+#define DMA_REQUEST_TIM15_TRIG      107U  /*!< DMAMUX1 TIM15 TRIG request */
+#define DMA_REQUEST_TIM15_COM       108U  /*!< DMAMUX1 TIM15 COM request  */
+
+#define DMA_REQUEST_TIM16_CH1       109U  /*!< DMAMUX1 TIM16 CH1 request  */
+#define DMA_REQUEST_TIM16_UP        110U  /*!< DMAMUX1 TIM16 UP request   */
+
+#define DMA_REQUEST_TIM17_CH1       111U  /*!< DMAMUX1 TIM17 CH1 request  */
+#define DMA_REQUEST_TIM17_UP        112U  /*!< DMAMUX1 TIM17 UP request   */
+
+#if defined(SAI3)
+#define DMA_REQUEST_SAI3_A          113U  /*!< DMAMUX1 SAI3 A request  */
+#define DMA_REQUEST_SAI3_B          114U  /*!< DMAMUX1 SAI3 B request  */
+#endif /* SAI3 */
+
+#if defined(ADC3)
+#define DMA_REQUEST_ADC3            115U  /*!< DMAMUX1 ADC3 request  */
+#endif /* ADC3 */
+
+#if defined(UART9)
+#define DMA_REQUEST_UART9_RX        116U  /*!< DMAMUX1 UART9 request  */
+#define DMA_REQUEST_UART9_TX        117U  /*!< DMAMUX1 UART9 request  */
+#endif /* UART9 */
+
+#if defined(USART10)
+#define DMA_REQUEST_USART10_RX      118U  /*!< DMAMUX1 USART10 request  */
+#define DMA_REQUEST_USART10_TX      119U  /*!< DMAMUX1 USART10 request  */
+#endif /* USART10 */
+
+
+/* DMAMUX2 requests */
+#define BDMA_REQUEST_MEM2MEM          0U  /*!< memory to memory transfer   */
+#define BDMA_REQUEST_GENERATOR0       1U  /*!< DMAMUX2 request generator 0 */
+#define BDMA_REQUEST_GENERATOR1       2U  /*!< DMAMUX2 request generator 1 */
+#define BDMA_REQUEST_GENERATOR2       3U  /*!< DMAMUX2 request generator 2 */
+#define BDMA_REQUEST_GENERATOR3       4U  /*!< DMAMUX2 request generator 3 */
+#define BDMA_REQUEST_GENERATOR4       5U  /*!< DMAMUX2 request generator 4 */
+#define BDMA_REQUEST_GENERATOR5       6U  /*!< DMAMUX2 request generator 5 */
+#define BDMA_REQUEST_GENERATOR6       7U  /*!< DMAMUX2 request generator 6 */
+#define BDMA_REQUEST_GENERATOR7       8U  /*!< DMAMUX2 request generator 7 */
+#define BDMA_REQUEST_LPUART1_RX       9U  /*!< DMAMUX2 LP_UART1_RX request */
+#define BDMA_REQUEST_LPUART1_TX      10U  /*!< DMAMUX2 LP_UART1_TX request */
+#define BDMA_REQUEST_SPI6_RX         11U  /*!< DMAMUX2 SPI6 RX request     */
+#define BDMA_REQUEST_SPI6_TX         12U  /*!< DMAMUX2 SPI6 TX request     */
+#define BDMA_REQUEST_I2C4_RX         13U  /*!< DMAMUX2 I2C4 RX request     */
+#define BDMA_REQUEST_I2C4_TX         14U  /*!< DMAMUX2 I2C4 TX request     */
+#if defined(SAI4)
+#define BDMA_REQUEST_SAI4_A          15U  /*!< DMAMUX2 SAI4 A request      */
+#define BDMA_REQUEST_SAI4_B          16U  /*!< DMAMUX2 SAI4 B request      */
+#endif /* SAI4 */
+#if defined(ADC3)
+#define BDMA_REQUEST_ADC3            17U  /*!< DMAMUX2 ADC3 request        */
+#endif /* ADC3 */
+#if defined(DAC2)
+#define BDMA_REQUEST_DAC2_CH1        17U  /*!< DMAMUX2 DAC2 CH1 request    */
+#endif /* DAC2 */
+#if defined(DFSDM2_Channel0)
+#define BDMA_REQUEST_DFSDM2_FLT0     18U  /*!< DMAMUX2 DFSDM2 request      */
+#endif /* DFSDM1_Channel0 */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
+  * @brief    DMA data transfer direction
+  * @{
+  */
+#define DMA_PERIPH_TO_MEMORY         ((uint32_t)0x00000000U)      /*!< Peripheral to memory direction */
+#define DMA_MEMORY_TO_PERIPH         ((uint32_t)DMA_SxCR_DIR_0)  /*!< Memory to peripheral direction */
+#define DMA_MEMORY_TO_MEMORY         ((uint32_t)DMA_SxCR_DIR_1)  /*!< Memory to memory direction     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
+  * @brief    DMA peripheral incremented mode
+  * @{
+  */
+#define DMA_PINC_ENABLE        ((uint32_t)DMA_SxCR_PINC)  /*!< Peripheral increment mode enable  */
+#define DMA_PINC_DISABLE       ((uint32_t)0x00000000U)     /*!< Peripheral increment mode disable */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
+  * @brief    DMA memory incremented mode
+  * @{
+  */
+#define DMA_MINC_ENABLE         ((uint32_t)DMA_SxCR_MINC)  /*!< Memory increment mode enable  */
+#define DMA_MINC_DISABLE        ((uint32_t)0x00000000U)     /*!< Memory increment mode disable */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
+  * @brief    DMA peripheral data size
+  * @{
+  */
+#define DMA_PDATAALIGN_BYTE          ((uint32_t)0x00000000U)       /*!< Peripheral data alignment: Byte      */
+#define DMA_PDATAALIGN_HALFWORD      ((uint32_t)DMA_SxCR_PSIZE_0)  /*!< Peripheral data alignment: HalfWord  */
+#define DMA_PDATAALIGN_WORD          ((uint32_t)DMA_SxCR_PSIZE_1)  /*!< Peripheral data alignment: Word      */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Memory_data_size DMA Memory data size
+  * @brief    DMA memory data size
+  * @{
+  */
+#define DMA_MDATAALIGN_BYTE          ((uint32_t)0x00000000U)       /*!< Memory data alignment: Byte     */
+#define DMA_MDATAALIGN_HALFWORD      ((uint32_t)DMA_SxCR_MSIZE_0)  /*!< Memory data alignment: HalfWord */
+#define DMA_MDATAALIGN_WORD          ((uint32_t)DMA_SxCR_MSIZE_1)  /*!< Memory data alignment: Word     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_mode DMA mode
+  * @brief    DMA mode
+  * @{
+  */
+#define DMA_NORMAL              ((uint32_t)0x00000000U)                  /*!< Normal mode                                    */
+#define DMA_CIRCULAR            ((uint32_t)DMA_SxCR_CIRC)                /*!< Circular mode                                  */
+#define DMA_PFCTRL              ((uint32_t)DMA_SxCR_PFCTRL)              /*!< Peripheral flow control mode                   */
+#define DMA_DOUBLE_BUFFER_M0    ((uint32_t)DMA_SxCR_DBM)                 /*!< Double buffer mode with first target memory M0 */
+#define DMA_DOUBLE_BUFFER_M1    ((uint32_t)(DMA_SxCR_DBM | DMA_SxCR_CT)) /*!< Double buffer mode with first target memory M1 */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Priority_level DMA Priority level
+  * @brief    DMA priority levels
+  * @{
+  */
+#define DMA_PRIORITY_LOW             ((uint32_t)0x00000000U)    /*!< Priority level: Low       */
+#define DMA_PRIORITY_MEDIUM          ((uint32_t)DMA_SxCR_PL_0)  /*!< Priority level: Medium    */
+#define DMA_PRIORITY_HIGH            ((uint32_t)DMA_SxCR_PL_1)  /*!< Priority level: High      */
+#define DMA_PRIORITY_VERY_HIGH       ((uint32_t)DMA_SxCR_PL)    /*!< Priority level: Very High */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
+  * @brief    DMA FIFO direct mode
+  * @{
+  */
+#define DMA_FIFOMODE_DISABLE        ((uint32_t)0x00000000U)       /*!< FIFO mode disable */
+#define DMA_FIFOMODE_ENABLE         ((uint32_t)DMA_SxFCR_DMDIS)  /*!< FIFO mode enable  */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
+  * @brief    DMA FIFO level
+  * @{
+  */
+#define DMA_FIFO_THRESHOLD_1QUARTERFULL       ((uint32_t)0x00000000U)       /*!< FIFO threshold 1 quart full configuration  */
+#define DMA_FIFO_THRESHOLD_HALFFULL           ((uint32_t)DMA_SxFCR_FTH_0)  /*!< FIFO threshold half full configuration     */
+#define DMA_FIFO_THRESHOLD_3QUARTERSFULL      ((uint32_t)DMA_SxFCR_FTH_1)  /*!< FIFO threshold 3 quarts full configuration */
+#define DMA_FIFO_THRESHOLD_FULL               ((uint32_t)DMA_SxFCR_FTH)    /*!< FIFO threshold full configuration          */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Memory_burst DMA Memory burst
+  * @brief    DMA memory burst
+  * @{
+  */
+#define DMA_MBURST_SINGLE       ((uint32_t)0x00000000U)
+#define DMA_MBURST_INC4         ((uint32_t)DMA_SxCR_MBURST_0)
+#define DMA_MBURST_INC8         ((uint32_t)DMA_SxCR_MBURST_1)
+#define DMA_MBURST_INC16        ((uint32_t)DMA_SxCR_MBURST)
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Peripheral_burst DMA Peripheral burst
+  * @brief    DMA peripheral burst
+  * @{
+  */
+#define DMA_PBURST_SINGLE       ((uint32_t)0x00000000U)
+#define DMA_PBURST_INC4         ((uint32_t)DMA_SxCR_PBURST_0)
+#define DMA_PBURST_INC8         ((uint32_t)DMA_SxCR_PBURST_1)
+#define DMA_PBURST_INC16        ((uint32_t)DMA_SxCR_PBURST)
+/**
+  * @}
+  */
+
+/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
+  * @brief    DMA interrupts definition
+  * @{
+  */
+#define DMA_IT_TC                         ((uint32_t)DMA_SxCR_TCIE)
+#define DMA_IT_HT                         ((uint32_t)DMA_SxCR_HTIE)
+#define DMA_IT_TE                         ((uint32_t)DMA_SxCR_TEIE)
+#define DMA_IT_DME                        ((uint32_t)DMA_SxCR_DMEIE)
+#define DMA_IT_FE                         ((uint32_t)0x00000080U)
+/**
+  * @}
+  */
+
+/** @defgroup DMA_flag_definitions DMA flag definitions
+  * @brief    DMA flag definitions
+  * @{
+  */
+#define DMA_FLAG_FEIF0_4                    ((uint32_t)0x00000001U)
+#define DMA_FLAG_DMEIF0_4                   ((uint32_t)0x00000004U)
+#define DMA_FLAG_TEIF0_4                    ((uint32_t)0x00000008U)
+#define DMA_FLAG_HTIF0_4                    ((uint32_t)0x00000010U)
+#define DMA_FLAG_TCIF0_4                    ((uint32_t)0x00000020U)
+#define DMA_FLAG_FEIF1_5                    ((uint32_t)0x00000040U)
+#define DMA_FLAG_DMEIF1_5                   ((uint32_t)0x00000100U)
+#define DMA_FLAG_TEIF1_5                    ((uint32_t)0x00000200U)
+#define DMA_FLAG_HTIF1_5                    ((uint32_t)0x00000400U)
+#define DMA_FLAG_TCIF1_5                    ((uint32_t)0x00000800U)
+#define DMA_FLAG_FEIF2_6                    ((uint32_t)0x00010000U)
+#define DMA_FLAG_DMEIF2_6                   ((uint32_t)0x00040000U)
+#define DMA_FLAG_TEIF2_6                    ((uint32_t)0x00080000U)
+#define DMA_FLAG_HTIF2_6                    ((uint32_t)0x00100000U)
+#define DMA_FLAG_TCIF2_6                    ((uint32_t)0x00200000U)
+#define DMA_FLAG_FEIF3_7                    ((uint32_t)0x00400000U)
+#define DMA_FLAG_DMEIF3_7                   ((uint32_t)0x01000000U)
+#define DMA_FLAG_TEIF3_7                    ((uint32_t)0x02000000U)
+#define DMA_FLAG_HTIF3_7                    ((uint32_t)0x04000000U)
+#define DMA_FLAG_TCIF3_7                    ((uint32_t)0x08000000U)
+/**
+  * @}
+  */
+
+/** @defgroup BDMA_flag_definitions BDMA flag definitions
+  * @brief    BDMA flag definitions
+  * @{
+  */
+#define BDMA_FLAG_GL0                      ((uint32_t)0x00000001)
+#define BDMA_FLAG_TC0                      ((uint32_t)0x00000002)
+#define BDMA_FLAG_HT0                      ((uint32_t)0x00000004)
+#define BDMA_FLAG_TE0                      ((uint32_t)0x00000008)
+#define BDMA_FLAG_GL1                      ((uint32_t)0x00000010)
+#define BDMA_FLAG_TC1                      ((uint32_t)0x00000020)
+#define BDMA_FLAG_HT1                      ((uint32_t)0x00000040)
+#define BDMA_FLAG_TE1                      ((uint32_t)0x00000080)
+#define BDMA_FLAG_GL2                      ((uint32_t)0x00000100)
+#define BDMA_FLAG_TC2                      ((uint32_t)0x00000200)
+#define BDMA_FLAG_HT2                      ((uint32_t)0x00000400)
+#define BDMA_FLAG_TE2                      ((uint32_t)0x00000800)
+#define BDMA_FLAG_GL3                      ((uint32_t)0x00001000)
+#define BDMA_FLAG_TC3                      ((uint32_t)0x00002000)
+#define BDMA_FLAG_HT3                      ((uint32_t)0x00004000)
+#define BDMA_FLAG_TE3                      ((uint32_t)0x00008000)
+#define BDMA_FLAG_GL4                      ((uint32_t)0x00010000)
+#define BDMA_FLAG_TC4                      ((uint32_t)0x00020000)
+#define BDMA_FLAG_HT4                      ((uint32_t)0x00040000)
+#define BDMA_FLAG_TE4                      ((uint32_t)0x00080000)
+#define BDMA_FLAG_GL5                      ((uint32_t)0x00100000)
+#define BDMA_FLAG_TC5                      ((uint32_t)0x00200000)
+#define BDMA_FLAG_HT5                      ((uint32_t)0x00400000)
+#define BDMA_FLAG_TE5                      ((uint32_t)0x00800000)
+#define BDMA_FLAG_GL6                      ((uint32_t)0x01000000)
+#define BDMA_FLAG_TC6                      ((uint32_t)0x02000000)
+#define BDMA_FLAG_HT6                      ((uint32_t)0x04000000)
+#define BDMA_FLAG_TE6                      ((uint32_t)0x08000000)
+#define BDMA_FLAG_GL7                      ((uint32_t)0x10000000)
+#define BDMA_FLAG_TC7                      ((uint32_t)0x20000000)
+#define BDMA_FLAG_HT7                      ((uint32_t)0x40000000)
+#define BDMA_FLAG_TE7                      ((uint32_t)0x80000000)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DMA_Exported_Macros DMA Exported Macros
+  * @{
+  */
+
+/** @brief Reset DMA handle state
+  * @param  __HANDLE__: specifies the DMA handle.
+  * @retval None
+  */
+#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
+
+/**
+  * @brief  Return the current DMA Stream FIFO filled level.
+  * @param  __HANDLE__: DMA handle
+  * @retval The FIFO filling state.
+  *           - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
+  *                                              and not empty.
+  *           - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
+  *           - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
+  *           - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
+  *           - DMA_FIFOStatus_Empty: when FIFO is empty
+  *           - DMA_FIFOStatus_Full: when FIFO is full
+  */
+#define __HAL_DMA_GET_FS(__HANDLE__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (DMA_SxFCR_FS)) : 0)
+
+/**
+  * @brief  Enable the specified DMA Stream.
+  * @param  __HANDLE__: DMA handle
+  * @retval None
+  */
+#define __HAL_DMA_ENABLE(__HANDLE__) \
+((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |=  DMA_SxCR_EN) : \
+(((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |=  BDMA_CCR_EN))
+
+/**
+  * @brief  Disable the specified DMA Stream.
+  * @param  __HANDLE__: DMA handle
+  * @retval None
+  */
+#define __HAL_DMA_DISABLE(__HANDLE__) \
+((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &=  ~DMA_SxCR_EN) : \
+(((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &=  ~BDMA_CCR_EN))
+
+/* Interrupt & Flag management */
+
+/**
+  * @brief  Return the current DMA Stream transfer complete flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified transfer complete flag index.
+  */
+#if defined(BDMA1)
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TCIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TCIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TCIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TCIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_TC0  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_TC0  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_TC1  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_TC1  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_TC2  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_TC2  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_TC3  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_TC3  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_TC4  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_TC4  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_TC5  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_TC5  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_TC6  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_TC6  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_TC7  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_TC7  :\
+ (uint32_t)0x00000000)
+#else
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TCIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TCIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TCIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TCIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_TC0   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_TC1   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_TC2   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_TC3   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_TC4   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_TC5   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TC6   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TC7   :\
+ (uint32_t)0x00000000)
+#endif /* BDMA1 */
+
+/**
+  * @brief  Return the current DMA Stream half transfer complete flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified half transfer complete flag index.
+  */
+#if defined(BDMA1)
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_HTIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_HTIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_HTIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_HTIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_HT0  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_HT0  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_HT1  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_HT1  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_HT2  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_HT2  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_HT3  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_HT3  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_HT4  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_HT4  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_HT5  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_HT5  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_HT6  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_HT6  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_HT7  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_HT7  :\
+ (uint32_t)0x00000000)
+#else
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_HTIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_HTIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_HTIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_HTIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_HT0   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_HT1   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_HT2   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_HT3   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_HT4   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_HT5   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_HT6   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_HT7   :\
+ (uint32_t)0x00000000)
+#endif /* BDMA1 */
+
+/**
+  * @brief  Return the current DMA Stream transfer error flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified transfer error flag index.
+  */
+#if defined(BDMA1)
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_TE0  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_TE0  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_TE1  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_TE1  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_TE2  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_TE2  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_TE3  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_TE3  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_TE4  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_TE4  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_TE5  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_TE5  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_TE6  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_TE6  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_TE7  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_TE7  :\
+ (uint32_t)0x00000000)
+#else
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_TE0   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_TE1   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_TE2   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_TE3   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_TE4   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_TE5   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TE6   :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TE7   :\
+ (uint32_t)0x00000000)
+#endif /* BDMA1 */
+
+/**
+  * @brief  Return the current DMA Stream FIFO error flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified FIFO error flag index.
+  */
+#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_FEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_FEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_FEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_FEIF3_7 :\
+  (uint32_t)0x00000000)
+
+/**
+  * @brief  Return the current DMA Stream direct mode error flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified direct mode error flag index.
+  */
+#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_DMEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_DMEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_DMEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_DMEIF3_7 :\
+  (uint32_t)0x00000000)
+
+/**
+  * @brief  Returns the current BDMA Channel Global interrupt flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified transfer error flag index.
+  */
+#if defined(BDMA1)
+#define __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_ISR_GIF0 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_ISR_GIF0 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_ISR_GIF1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_ISR_GIF1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_ISR_GIF2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_ISR_GIF2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_ISR_GIF3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_ISR_GIF3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_ISR_GIF4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_ISR_GIF4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_ISR_GIF5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_ISR_GIF5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_ISR_GIF6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_ISR_GIF6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_ISR_GIF7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_ISR_GIF7 :\
+ (uint32_t)0x00000000)
+#else
+#define __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_ISR_GIF0 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_ISR_GIF1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_ISR_GIF2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_ISR_GIF3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_ISR_GIF4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_ISR_GIF5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_ISR_GIF6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_ISR_GIF7 :\
+  (uint32_t)0x00000000)
+#endif /* BDMA1 */
+
+/**
+  * @brief  Get the DMA Stream pending flags.
+  * @param  __HANDLE__: DMA handle
+  * @param  __FLAG__: Get the specified flag.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
+  *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
+  *            @arg DMA_FLAG_TEIFx: Transfer error flag.
+  *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.
+  *            @arg DMA_FLAG_FEIFx: FIFO error flag.
+  *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
+  * @retval The state of FLAG (SET or RESET).
+  */
+#if defined(BDMA1)
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)BDMA1_Channel7)?  (BDMA2->ISR & (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7  )?  (BDMA1->ISR & (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3  )?  (DMA2->HISR & (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7  )?  (DMA2->LISR & (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3  )?  (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
+#else
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->ISR & (__FLAG__))  :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
+#endif /* BDMA1 */
+
+/**
+  * @brief  Clear the DMA Stream pending flags.
+  * @param  __HANDLE__: DMA handle
+  * @param  __FLAG__: specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
+  *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
+  *            @arg DMA_FLAG_TEIFx: Transfer error flag.
+  *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.
+  *            @arg DMA_FLAG_FEIFx: FIFO error flag.
+  *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
+  * @retval None
+  */
+#if defined(BDMA1)
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)BDMA1_Channel7)? (BDMA2->IFCR = (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)?  (BDMA1->IFCR = (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)?  (DMA2->HIFCR = (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)?  (DMA2->LIFCR = (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)?  (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
+#else
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->IFCR = (__FLAG__))  :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
+#endif /* BDMA1 */
+
+#define DMA_TO_BDMA_IT(__DMA_IT__) \
+((((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE |BDMA_CCR_TEIE) :\
+ (((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT)) == (DMA_IT_TC | DMA_IT_HT)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE) :\
+ (((__DMA_IT__) & (DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_HTIE |BDMA_CCR_TEIE)  :\
+ (((__DMA_IT__) & (DMA_IT_TC | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_TE)) ? (BDMA_CCR_TCIE |BDMA_CCR_TEIE)  :\
+ ((__DMA_IT__) == DMA_IT_TC) ? BDMA_CCR_TCIE :\
+ ((__DMA_IT__) == DMA_IT_HT) ? BDMA_CCR_HTIE :\
+ ((__DMA_IT__) == DMA_IT_TE) ? BDMA_CCR_TEIE :\
+ (uint32_t)0x00000000)
+
+
+#define __HAL_BDMA_CHANNEL_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
+(((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |= (DMA_TO_BDMA_IT(__INTERRUPT__)))
+
+#define __HAL_DMA_STREAM_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((__INTERRUPT__) != DMA_IT_FE)? \
+(((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |= (__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR |= (__INTERRUPT__)))
+
+/**
+  * @brief  Enable the specified DMA Stream interrupts.
+  * @param  __HANDLE__: DMA handle
+  * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+  *        This parameter can be one of the following values:
+  *           @arg DMA_IT_TC: Transfer complete interrupt mask.
+  *           @arg DMA_IT_HT: Half transfer complete interrupt mask.
+  *           @arg DMA_IT_TE: Transfer error interrupt mask.
+  *           @arg DMA_IT_FE: FIFO error interrupt mask.
+  *           @arg DMA_IT_DME: Direct mode error interrupt.
+  * @retval None
+  */
+#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))?\
+                                                        (__HAL_DMA_STREAM_ENABLE_IT((__HANDLE__), (__INTERRUPT__))) :\
+                                                        (__HAL_BDMA_CHANNEL_ENABLE_IT((__HANDLE__), (__INTERRUPT__))))
+
+
+#define __HAL_BDMA_CHANNEL_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &= ~(DMA_TO_BDMA_IT(__INTERRUPT__)))
+
+#define __HAL_DMA_STREAM_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \
+(((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &= ~(__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR &= ~(__INTERRUPT__)))
+
+/**
+  * @brief  Disable the specified DMA Stream interrupts.
+  * @param  __HANDLE__: DMA handle
+  * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+  *         This parameter can be one of the following values:
+  *            @arg DMA_IT_TC: Transfer complete interrupt mask.
+  *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
+  *            @arg DMA_IT_TE: Transfer error interrupt mask.
+  *            @arg DMA_IT_FE: FIFO error interrupt mask.
+  *            @arg DMA_IT_DME: Direct mode error interrupt.
+  * @retval None
+  */
+#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))?\
+                                                         (__HAL_DMA_STREAM_DISABLE_IT((__HANDLE__), (__INTERRUPT__))) :\
+                                                         (__HAL_BDMA_CHANNEL_DISABLE_IT((__HANDLE__), (__INTERRUPT__))))
+
+
+#define __HAL_BDMA_CHANNEL_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  ((((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR & (DMA_TO_BDMA_IT(__INTERRUPT__))))
+
+#define __HAL_DMA_STREAM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \
+                                                        (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR & (__INTERRUPT__)) : \
+                                                        (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (__INTERRUPT__)))
+
+/**
+  * @brief  Check whether the specified DMA Stream interrupt is enabled or not.
+  * @param  __HANDLE__: DMA handle
+  * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
+  *         This parameter can be one of the following values:
+  *            @arg DMA_IT_TC: Transfer complete interrupt mask.
+  *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
+  *            @arg DMA_IT_TE: Transfer error interrupt mask.
+  *            @arg DMA_IT_FE: FIFO error interrupt mask.
+  *            @arg DMA_IT_DME: Direct mode error interrupt.
+  * @retval The state of DMA_IT.
+  */
+#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \
+                                                            (__HAL_DMA_STREAM_GET_IT_SOURCE((__HANDLE__), (__INTERRUPT__))) :\
+                                                            (__HAL_BDMA_CHANNEL_GET_IT_SOURCE((__HANDLE__), (__INTERRUPT__))))
+
+/**
+  * @brief  Writes the number of data units to be transferred on the DMA Stream.
+  * @param  __HANDLE__: DMA handle
+  * @param  __COUNTER__: Number of data units to be transferred (from 0 to 65535)
+  *          Number of data items depends only on the Peripheral data format.
+  *
+  * @note   If Peripheral data format is Bytes: number of data units is equal
+  *         to total number of bytes to be transferred.
+  *
+  * @note   If Peripheral data format is Half-Word: number of data units is
+  *         equal to total number of bytes to be transferred / 2.
+  *
+  * @note   If Peripheral data format is Word: number of data units is equal
+  *         to total  number of bytes to be transferred / 4.
+  *
+  * @retval The number of remaining data units in the current DMAy Streamx transfer.
+  */
+#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \
+                                                        (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR = (uint16_t)(__COUNTER__)) :\
+                                                        (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CNDTR = (uint16_t)(__COUNTER__)))
+
+/**
+  * @brief  Returns the number of remaining data units in the current DMAy Streamx transfer.
+  * @param  __HANDLE__: DMA handle
+  *
+  * @retval The number of remaining data units in the current DMA Stream transfer.
+  */
+#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \
+                                           (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR) :\
+                                           (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CNDTR))
+
+/**
+  * @}
+  */
+
+/* Include DMA HAL Extension module */
+#include "stm32h7xx_hal_dma_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Functions DMA Exported Functions
+  * @brief    DMA Exported functions
+  * @{
+  */
+
+/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief   Initialization and de-initialization functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
+  * @brief   I/O operation functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
+void              HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
+  * @brief    Peripheral State functions
+  * @{
+  */
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
+uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+/* Private Constants -------------------------------------------------------------*/
+/** @defgroup DMA_Private_Constants DMA Private Constants
+  * @brief    DMA private defines and constants
+  * @{
+  */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DMA_Private_Macros DMA Private Macros
+  * @brief    DMA private macros
+  * @{
+  */
+
+#if defined(ADC3)
+#define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_ADC3))
+#else
+#define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_USART10_TX))
+#endif /* ADC3 */
+
+#if defined(ADC3)
+#define IS_BDMA_REQUEST(REQUEST) (((REQUEST) <= BDMA_REQUEST_ADC3))
+#else
+#define IS_BDMA_REQUEST(REQUEST) (((REQUEST) <= BDMA_REQUEST_DFSDM2_FLT0))
+#endif /* ADC3 */
+
+#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
+                                     ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
+                                     ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
+
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
+
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
+                                            ((STATE) == DMA_PINC_DISABLE))
+
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
+                                        ((STATE) == DMA_MINC_DISABLE))
+
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
+                                           ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
+                                           ((SIZE) == DMA_PDATAALIGN_WORD))
+
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
+                                       ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
+                                       ((SIZE) == DMA_MDATAALIGN_WORD ))
+
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )           || \
+                           ((MODE) == DMA_CIRCULAR)          || \
+                           ((MODE) == DMA_PFCTRL)            || \
+                           ((MODE) == DMA_DOUBLE_BUFFER_M0)  || \
+                           ((MODE) == DMA_DOUBLE_BUFFER_M1))
+
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
+                                   ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
+                                   ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
+                                   ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
+
+#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
+                                       ((STATE) == DMA_FIFOMODE_ENABLE))
+
+#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
+                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL)      || \
+                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
+                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
+
+#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
+                                    ((BURST) == DMA_MBURST_INC4)   || \
+                                    ((BURST) == DMA_MBURST_INC8)   || \
+                                    ((BURST) == DMA_MBURST_INC16))
+
+#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
+                                        ((BURST) == DMA_PBURST_INC4)   || \
+                                        ((BURST) == DMA_PBURST_INC8)   || \
+                                        ((BURST) == DMA_PBURST_INC16))
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DMA_Private_Functions DMA Private Functions
+  * @brief    DMA private  functions
+  * @{
+  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h
new file mode 100644
index 00000000..4125ae7e
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h
@@ -0,0 +1,312 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_dma_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMA HAL extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_DMA_EX_H
+#define STM32H7xx_HAL_DMA_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DMAEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DMAEx_Exported_Types DMAEx Exported Types
+  * @brief DMAEx Exported types
+  * @{
+  */
+
+/**
+  * @brief  HAL DMA Memory definition
+  */
+typedef enum
+{
+  MEMORY0      = 0x00U,    /*!< Memory 0     */
+  MEMORY1      = 0x01U,    /*!< Memory 1     */
+
+}HAL_DMA_MemoryTypeDef;
+
+/**
+  * @brief  HAL DMAMUX Synchronization configuration structure definition
+  */
+typedef struct
+{
+  uint32_t SyncSignalID;  /*!< Specifies the synchronization signal gating the DMA request in periodic mode.
+                              This parameter can be a value of @ref DMAEx_MUX_SyncSignalID_selection */
+
+  uint32_t SyncPolarity;  /*!< Specifies the polarity of the signal on which the DMA request is synchronized.
+                              This parameter can be a value of @ref DMAEx_MUX_SyncPolarity_selection */
+
+  FunctionalState SyncEnable;  /*!< Specifies if the synchronization shall be enabled or disabled
+                                    This parameter can take the value ENABLE or DISABLE*/
+
+
+  FunctionalState EventEnable;    /*!< Specifies if an event shall be generated once the RequestNumber is reached.
+                                       This parameter can take the value ENABLE or DISABLE */
+
+  uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be authorized after a sync event.
+                               This parameters can be in the range 1 to 32 */
+
+}HAL_DMA_MuxSyncConfigTypeDef;
+
+
+/**
+  * @brief  HAL DMAMUX request generator parameters structure definition
+  */
+typedef struct
+{
+ uint32_t SignalID;      /*!< Specifies the ID of the signal used for DMAMUX request generator
+                              This parameter can be a value of @ref DMAEx_MUX_SignalGeneratorID_selection */
+
+  uint32_t Polarity;       /*!< Specifies the polarity of the signal on which the request is generated.
+                             This parameter can be a value of @ref DMAEx_MUX_RequestGeneneratorPolarity_selection */
+
+  uint32_t RequestNumber;  /*!< Specifies the number of DMA request that will be generated after a signal event.
+                                This parameters can be in the range 1 to 32 */
+
+}HAL_DMA_MuxRequestGeneratorConfigTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMAEx_Exported_Constants DMA Exported Constants
+  * @brief    DMAEx Exported constants
+  * @{
+  */
+
+/** @defgroup DMAEx_MUX_SyncSignalID_selection DMAEx MUX SyncSignalID selection
+  * @brief    DMAEx MUX SyncSignalID selection
+  * @{
+  */
+#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT   0U   /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel0 Event */
+#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT   1U   /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel1 Event */
+#define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT   2U   /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel2 Event */
+#define HAL_DMAMUX1_SYNC_LPTIM1_OUT        3U   /*!< DMAMUX1 synchronization Signal is LPTIM1 OUT             */
+#define HAL_DMAMUX1_SYNC_LPTIM2_OUT        4U   /*!< DMAMUX1 synchronization Signal is LPTIM2 OUT             */
+#define HAL_DMAMUX1_SYNC_LPTIM3_OUT        5U   /*!< DMAMUX1 synchronization Signal is LPTIM3 OUT             */
+#define HAL_DMAMUX1_SYNC_EXTI0             6U   /*!< DMAMUX1 synchronization Signal is EXTI0 IT               */
+#define HAL_DMAMUX1_SYNC_TIM12_TRGO        7U   /*!< DMAMUX1 synchronization Signal is TIM12 TRGO             */
+
+#define HAL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT   0U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel0 Event */
+#define HAL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT   1U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel1 Event */
+#define HAL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT   2U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel2 Event */
+#define HAL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT   3U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel3 Event */
+#define HAL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT   4U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel4 Event */
+#define HAL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT   5U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel5 Event */
+#define HAL_DMAMUX2_SYNC_LPUART1_RX_WKUP   6U   /*!< DMAMUX2 synchronization Signal is LPUART1 RX Wakeup      */
+#define HAL_DMAMUX2_SYNC_LPUART1_TX_WKUP   7U   /*!< DMAMUX2 synchronization Signal is LPUART1 TX Wakeup      */
+#define HAL_DMAMUX2_SYNC_LPTIM2_OUT        8U   /*!< DMAMUX2 synchronization Signal is LPTIM2 output          */
+#define HAL_DMAMUX2_SYNC_LPTIM3_OUT        9U   /*!< DMAMUX2 synchronization Signal is LPTIM3 output          */
+#define HAL_DMAMUX2_SYNC_I2C4_WKUP        10U   /*!< DMAMUX2 synchronization Signal is I2C4 Wakeup            */
+#define HAL_DMAMUX2_SYNC_SPI6_WKUP        11U   /*!< DMAMUX2 synchronization Signal is SPI6 Wakeup            */
+#define HAL_DMAMUX2_SYNC_COMP1_OUT        12U   /*!< DMAMUX2 synchronization Signal is Comparator 1 output    */
+#define HAL_DMAMUX2_SYNC_RTC_WKUP         13U   /*!< DMAMUX2 synchronization Signal is RTC Wakeup             */
+#define HAL_DMAMUX2_SYNC_EXTI0            14U   /*!< DMAMUX2 synchronization Signal is EXTI0 IT               */
+#define HAL_DMAMUX2_SYNC_EXTI2            15U   /*!< DMAMUX2 synchronization Signal is EXTI2 IT               */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMAEx_MUX_SyncPolarity_selection DMAEx MUX SyncPolarity selection
+  * @brief    DMAEx MUX SyncPolarity selection
+  * @{
+  */
+#define HAL_DMAMUX_SYNC_NO_EVENT        0x00000000U             /*!< block synchronization events                    */
+#define HAL_DMAMUX_SYNC_RISING          DMAMUX_CxCR_SPOL_0      /*!< synchronize with rising edge events             */
+#define HAL_DMAMUX_SYNC_FALLING         DMAMUX_CxCR_SPOL_1      /*!< synchronize with falling edge events            */
+#define HAL_DMAMUX_SYNC_RISING_FALLING  DMAMUX_CxCR_SPOL        /*!< synchronize with rising and falling edge events */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup DMAEx_MUX_SignalGeneratorID_selection DMAEx MUX SignalGeneratorID selection
+  * @brief    DMAEx MUX SignalGeneratorID selection
+  * @{
+  */
+#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT   0U   /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel0 Event */
+#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT   1U   /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel1 Event */
+#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT   2U   /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel2 Event */
+#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT        3U   /*!< DMAMUX1 Request generator Signal is LPTIM1 OUT             */
+#define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT        4U   /*!< DMAMUX1 Request generator Signal is LPTIM2 OUT             */
+#define HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT        5U   /*!< DMAMUX1 Request generator Signal is LPTIM3 OUT             */
+#define HAL_DMAMUX1_REQ_GEN_EXTI0             6U   /*!< DMAMUX1 Request generator Signal is EXTI0 IT               */
+#define HAL_DMAMUX1_REQ_GEN_TIM12_TRGO        7U   /*!< DMAMUX1 Request generator Signal is TIM12 TRGO             */
+
+#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT   0U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel0 Event */
+#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT   1U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel1 Event */
+#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT   2U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel2 Event */
+#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT   3U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel3 Event */
+#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT   4U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel4 Event */
+#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT   5U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel5 Event */
+#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT   6U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel6 Event */
+#define HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP   7U   /*!< DMAMUX2 Request generator Signal is LPUART1 RX Wakeup      */
+#define HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP   8U   /*!< DMAMUX2 Request generator Signal is LPUART1 TX Wakeup      */
+#define HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP       9U   /*!< DMAMUX2 Request generator Signal is LPTIM2 Wakeup          */
+#define HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT       10U   /*!< DMAMUX2 Request generator Signal is LPTIM2 OUT             */
+#define HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP      11U   /*!< DMAMUX2 Request generator Signal is LPTIM3 Wakeup          */
+#define HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT       12U   /*!< DMAMUX2 Request generator Signal is LPTIM3 OUT             */
+#if defined(LPTIM4)
+#define HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP      13U   /*!< DMAMUX2 Request generator Signal is LPTIM4 Wakeup          */
+#endif /* LPTIM4 */
+#if defined(LPTIM5)
+#define HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP      14U   /*!< DMAMUX2 Request generator Signal is LPTIM5 Wakeup          */
+#endif /* LPTIM5 */
+#define HAL_DMAMUX2_REQ_GEN_I2C4_WKUP        15U   /*!< DMAMUX2 Request generator Signal is I2C4 Wakeup            */
+#define HAL_DMAMUX2_REQ_GEN_SPI6_WKUP        16U   /*!< DMAMUX2 Request generator Signal is SPI6 Wakeup            */
+#define HAL_DMAMUX2_REQ_GEN_COMP1_OUT        17U   /*!< DMAMUX2 Request generator Signal is Comparator 1 output    */
+#define HAL_DMAMUX2_REQ_GEN_COMP2_OUT        18U   /*!< DMAMUX2 Request generator Signal is Comparator 2 output    */
+#define HAL_DMAMUX2_REQ_GEN_RTC_WKUP         19U   /*!< DMAMUX2 Request generator Signal is RTC Wakeup             */
+#define HAL_DMAMUX2_REQ_GEN_EXTI0            20U   /*!< DMAMUX2 Request generator Signal is EXTI0                  */
+#define HAL_DMAMUX2_REQ_GEN_EXTI2            21U   /*!< DMAMUX2 Request generator Signal is EXTI2                  */
+#define HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT      22U   /*!< DMAMUX2 Request generator Signal is I2C4 IT Event          */
+#define HAL_DMAMUX2_REQ_GEN_SPI6_IT          23U   /*!< DMAMUX2 Request generator Signal is SPI6 IT                */
+#define HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT    24U   /*!< DMAMUX2 Request generator Signal is LPUART1 Tx IT          */
+#define HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT    25U   /*!< DMAMUX2 Request generator Signal is LPUART1 Rx IT          */
+#if defined(ADC3)
+#define HAL_DMAMUX2_REQ_GEN_ADC3_IT          26U   /*!< DMAMUX2 Request generator Signal is ADC3 IT                */
+#define HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT    27U   /*!< DMAMUX2 Request generator Signal is ADC3 Analog Watchdog 1 output */
+#endif /* ADC3 */
+#define HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT      28U   /*!< DMAMUX2 Request generator Signal is BDMA Channel 0 IT      */
+#define HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT      29U   /*!< DMAMUX2 Request generator Signal is BDMA Channel 1 IT      */
+
+
+/**
+  * @}
+  */
+
+/** @defgroup DMAEx_MUX_RequestGeneneratorPolarity_selection DMAEx MUX RequestGeneneratorPolarity selection
+  * @brief    DMAEx MUX RequestGeneneratorPolarity selection
+  * @{
+  */
+#define HAL_DMAMUX_REQ_GEN_NO_EVENT        0x00000000U           /*!< block request generator events                     */
+#define HAL_DMAMUX_REQ_GEN_RISING          DMAMUX_RGxCR_GPOL_0  /*!< generate request on rising edge events             */
+#define HAL_DMAMUX_REQ_GEN_FALLING         DMAMUX_RGxCR_GPOL_1  /*!< generate request on falling edge events            */
+#define HAL_DMAMUX_REQ_GEN_RISING_FALLING  DMAMUX_RGxCR_GPOL    /*!< generate request on rising and falling edge events */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
+  * @brief   DMAEx Exported functions
+  * @{
+  */
+
+/** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions
+  * @brief   Extended features functions
+  * @{
+  */
+
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory);
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig);
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig);
+HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma);
+
+void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DMAEx_Private_Macros DMA Private Macros
+  * @brief    DMAEx private macros
+  * @{
+  */
+
+#define IS_DMA_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_TIM12_TRGO)
+#define IS_BDMA_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX2_SYNC_EXTI2)
+
+#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
+
+#define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT)    || \
+                                           ((POLARITY) == HAL_DMAMUX_SYNC_RISING)   || \
+                                           ((POLARITY) == HAL_DMAMUX_SYNC_FALLING)  || \
+                                           ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING))
+
+#define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE)   || ((SYNC) == ENABLE))
+
+#define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE)   || \
+                                     ((EVENT) == ENABLE))
+
+#define IS_DMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_TIM12_TRGO)
+#define IS_BDMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT)
+
+#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
+
+#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT) || \
+                                                  ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING)   || \
+                                                  ((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING)   || \
+                                                  ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING))
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DMAEx_Private_Functions DMAEx Private Functions
+  * @brief DMAEx Private functions
+  * @{
+  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h
new file mode 100644
index 00000000..6273f3c3
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h
@@ -0,0 +1,507 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_exti.h
+  * @author  MCD Application Team
+  * @brief   Header file of EXTI HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_EXTI_H
+#define STM32H7xx_HAL_EXTI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup EXTI EXTI
+  * @brief EXTI HAL module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup EXTI_Exported_Types EXTI Exported Types
+  * @{
+  */
+typedef enum
+{
+  HAL_EXTI_COMMON_CB_ID          = 0x00U,
+} EXTI_CallbackIDTypeDef;
+
+
+/**
+  * @brief  EXTI Handle structure definition
+  */
+typedef struct
+{
+  uint32_t Line;                    /*!<  Exti line number */
+  void (* PendingCallback)(void);   /*!<  Exti pending callback */
+} EXTI_HandleTypeDef;
+
+/**
+  * @brief  EXTI Configuration structure definition
+  */
+typedef struct
+{
+  uint32_t Line;           /*!< The Exti line to be configured. This parameter
+                                can be a value of @ref EXTI_Line */
+  uint32_t Mode;           /*!< The Exit Mode to be configured for a core.
+                                This parameter can be a combination of @ref EXTI_Mode */
+  uint32_t Trigger;        /*!< The Exti Trigger to be configured. This parameter
+                                can be a value of @ref EXTI_Trigger */
+  uint32_t GPIOSel;        /*!< The Exti GPIO multiplexer selection to be configured.
+                                This parameter is only possible for line 0 to 15. It
+                                can be a value of @ref EXTI_GPIOSel */
+
+  uint32_t PendClearSource; /*!< Specifies the event pending clear source for D3/SRD
+                                 domain. This parameter can be a value of @ref
+                                 EXTI_PendClear_Source */
+
+} EXTI_ConfigTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
+  * @{
+  */
+
+/** @defgroup EXTI_Line  EXTI Line
+  * @{
+  */
+#define EXTI_LINE_0                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x00U)
+#define EXTI_LINE_1                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x01U)
+#define EXTI_LINE_2                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x02U)
+#define EXTI_LINE_3                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x03U)
+#define EXTI_LINE_4                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x04U)
+#define EXTI_LINE_5                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x05U)
+#define EXTI_LINE_6                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x06U)
+#define EXTI_LINE_7                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x07U)
+#define EXTI_LINE_8                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x08U)
+#define EXTI_LINE_9                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x09U)
+#define EXTI_LINE_10                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x0AU)
+#define EXTI_LINE_11                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x0BU)
+#define EXTI_LINE_12                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x0CU)
+#define EXTI_LINE_13                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x0DU)
+#define EXTI_LINE_14                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x0EU)
+#define EXTI_LINE_15                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x0FU)
+#define EXTI_LINE_16                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x10U)
+#define EXTI_LINE_17                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x11U)
+#define EXTI_LINE_18                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x12U)
+#define EXTI_LINE_19                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x13U)
+#define EXTI_LINE_20                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x14U)
+#define EXTI_LINE_21                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x15U)
+#define EXTI_LINE_22                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x16U)
+#define EXTI_LINE_23                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x17U)
+#define EXTI_LINE_24                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x18U)
+#define EXTI_LINE_25                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x19U)
+#define EXTI_LINE_26                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1AU)
+#define EXTI_LINE_27                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1BU)
+#define EXTI_LINE_28                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1CU)
+#define EXTI_LINE_29                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1DU)
+#define EXTI_LINE_30                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1EU)
+#define EXTI_LINE_31                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1FU)
+#define EXTI_LINE_32                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x00U)
+#define EXTI_LINE_33                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x01U)
+#define EXTI_LINE_34                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x02U)
+#define EXTI_LINE_35                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x03U)
+#define EXTI_LINE_36                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x04U)
+#define EXTI_LINE_37                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x05U)
+#define EXTI_LINE_38                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x06U)
+#define EXTI_LINE_39                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x07U)
+#define EXTI_LINE_40                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x08U)
+#define EXTI_LINE_41                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x09U)
+#define EXTI_LINE_42                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0AU)
+#define EXTI_LINE_43                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0BU)
+#if !defined(USB2_OTG_FS)
+#define EXTI_LINE_44                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE    | 0x0CU)
+#else
+#define EXTI_LINE_44                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0CU)
+#endif /* USB2_OTG_FS */
+#define EXTI_LINE_45                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE    | 0x0DU)
+#if defined(DSI)
+#define EXTI_LINE_46                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0EU)
+#else
+#define EXTI_LINE_46                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE    | 0x0EU)
+#endif /* DSI */
+#define EXTI_LINE_47                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0FU)
+#define EXTI_LINE_48                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x10U)
+#define EXTI_LINE_49                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x11U)
+#define EXTI_LINE_50                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x12U)
+#define EXTI_LINE_51                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x13U)
+#if !defined(UART9)
+#define EXTI_LINE_52                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x14U)
+#else
+#define EXTI_LINE_52                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x14U)
+#endif /* UART9 */
+#if !defined(USART10)
+#define EXTI_LINE_53                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x15U)
+#else
+#define EXTI_LINE_53                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x15U)
+#endif /* USART10 */
+#define EXTI_LINE_54                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x16U)
+#define EXTI_LINE_55                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x17U)
+#define EXTI_LINE_56                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x18U)
+#define EXTI_LINE_57                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x19U)
+#define EXTI_LINE_58                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1AU)
+#define EXTI_LINE_59                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1BU)
+#define EXTI_LINE_60                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1CU)
+#define EXTI_LINE_61                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1DU)
+#define EXTI_LINE_62                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1EU)
+#define EXTI_LINE_63                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1FU)
+#define EXTI_LINE_64                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x00U)
+#define EXTI_LINE_65                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x01U)
+#define EXTI_LINE_66                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x02U)
+#define EXTI_LINE_67                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x03U)
+#define EXTI_LINE_68                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x04U)
+#define EXTI_LINE_69                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x05U)
+#define EXTI_LINE_70                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x06U)
+#define EXTI_LINE_71                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x07U)
+#define EXTI_LINE_72                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x08U)
+#define EXTI_LINE_73                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x09U)
+#define EXTI_LINE_74                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0AU)
+#if defined(ADC3)
+#define EXTI_LINE_75                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0BU)
+#else
+#define EXTI_LINE_75                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 |  EXTI_TARGET_MSK_NONE   | 0x0BU)
+#endif /* ADC3 */
+#if defined(SAI4)
+#define EXTI_LINE_76                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0CU)
+#else
+#define EXTI_LINE_76                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 |  EXTI_TARGET_MSK_NONE   | 0x0CU)
+#endif /* SAI4 */
+#if defined (DUAL_CORE)
+#define EXTI_LINE_77                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x0DU)
+#define EXTI_LINE_78                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU2| 0x0EU)
+#define EXTI_LINE_79                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x0FU)
+#define EXTI_LINE_80                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU2| 0x10U)
+#else
+#define EXTI_LINE_77                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0DU)
+#define EXTI_LINE_78                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0EU)
+#define EXTI_LINE_79                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0FU)
+#define EXTI_LINE_80                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x10U)
+#endif /* DUAL_CORE */
+
+#define EXTI_LINE_81                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x11U)
+
+#if defined (DUAL_CORE)
+#define EXTI_LINE_82                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU2| 0x12U)
+#else
+#define EXTI_LINE_82                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x12U)
+#endif /* DUAL_CORE */
+
+#define EXTI_LINE_83                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x13U)
+#if defined (DUAL_CORE)
+#define EXTI_LINE_84                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x14U)
+#else
+#define EXTI_LINE_84                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x14U)
+#endif /* DUAL_CORE */
+#define EXTI_LINE_85                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x15U)
+#if defined(ETH)
+#define EXTI_LINE_86                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x16U)
+#else
+#define EXTI_LINE_86                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x16U)
+#endif /* ETH */
+#define EXTI_LINE_87                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x17U)
+#if defined(DTS)
+#define EXTI_LINE_88                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL | 0x18U)
+#endif /* DTS */
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Mode  EXTI Mode
+  * @{
+  */
+#define EXTI_MODE_NONE                      0x00000000U
+#define EXTI_MODE_INTERRUPT                 0x00000001U
+#define EXTI_MODE_EVENT                     0x00000002U
+#if defined(DUAL_CORE)
+#define EXTI_MODE_CORE1_INTERRUPT           EXTI_MODE_INTERRUPT
+#define EXTI_MODE_CORE1_EVENT               EXTI_MODE_EVENT
+#define EXTI_MODE_CORE2_INTERRUPT           0x00000010U
+#define EXTI_MODE_CORE2_EVENT               0x00000020U
+#endif /* DUAL_CORE */
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Trigger  EXTI Trigger
+  * @{
+  */
+#define EXTI_TRIGGER_NONE                   0x00000000U
+#define EXTI_TRIGGER_RISING                 0x00000001U
+#define EXTI_TRIGGER_FALLING                0x00000002U
+#define EXTI_TRIGGER_RISING_FALLING         (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_GPIOSel  EXTI GPIOSel
+  * @brief
+  * @{
+  */
+#define EXTI_GPIOA                          0x00000000U
+#define EXTI_GPIOB                          0x00000001U
+#define EXTI_GPIOC                          0x00000002U
+#define EXTI_GPIOD                          0x00000003U
+#define EXTI_GPIOE                          0x00000004U
+#define EXTI_GPIOF                          0x00000005U
+#define EXTI_GPIOG                          0x00000006U
+#define EXTI_GPIOH                          0x00000007U
+#define EXTI_GPIOI                          0x00000008U
+#define EXTI_GPIOJ                          0x00000009U
+#define EXTI_GPIOK                          0x0000000AU
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_PendClear_Source  EXTI PendClear Source
+  * @brief
+  * @{
+  */
+#define EXTI_D3_PENDCLR_SRC_NONE       0x00000000U /*!< No D3 domain pendclear source , PMRx register to be set to zero  */
+#define EXTI_D3_PENDCLR_SRC_DMACH6     0x00000001U /*!< DMA ch6 event selected as D3 domain pendclear source, PMRx register to be set to 1 */
+#define EXTI_D3_PENDCLR_SRC_DMACH7     0x00000002U /*!< DMA ch7 event selected as D3 domain pendclear source, PMRx register to be set to 1*/
+#if defined (LPTIM4)
+#define EXTI_D3_PENDCLR_SRC_LPTIM4     0x00000003U /*!< LPTIM4 out selected as D3 domain pendclear source, PMRx register to be set to 1    */
+#else
+#define EXTI_D3_PENDCLR_SRC_LPTIM2     0x00000003U /*!< LPTIM2 out selected as D3 domain pendclear source, PMRx register to be set to 1    */
+#endif
+#if defined (LPTIM5)
+#define EXTI_D3_PENDCLR_SRC_LPTIM5     0x00000004U /*!< LPTIM5 out selected as D3 domain pendclear source, PMRx register to be set to 1    */
+#else
+#define EXTI_D3_PENDCLR_SRC_LPTIM3     0x00000004U /*!< LPTIM3 out selected as D3 domain pendclear source, PMRx register to be set to 1    */
+#endif
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants --------------------------------------------------------*/
+/** @defgroup EXTI_Private_Constants EXTI Private Constants
+  * @{
+  */
+/**
+  * @brief  EXTI Line property definition
+  */
+#define EXTI_PROPERTY_SHIFT                 24U
+#define EXTI_DIRECT                         (0x01UL << EXTI_PROPERTY_SHIFT)
+#define EXTI_CONFIG                         (0x02UL << EXTI_PROPERTY_SHIFT)
+#define EXTI_GPIO                           ((0x04UL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
+#define EXTI_RESERVED                       (0x08UL << EXTI_PROPERTY_SHIFT)
+#define EXTI_PROPERTY_MASK                  (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
+
+/**
+  * @brief  EXTI Event presence definition
+  */
+#define EXTI_EVENT_PRESENCE_SHIFT           28U
+#define EXTI_EVENT                          (0x01UL << EXTI_EVENT_PRESENCE_SHIFT)
+#define EXTI_EVENT_PRESENCE_MASK            (EXTI_EVENT)
+
+/**
+  * @brief  EXTI Register and bit usage
+  */
+#define EXTI_REG_SHIFT                      16U
+#define EXTI_REG1                           (0x00UL << EXTI_REG_SHIFT)
+#define EXTI_REG2                           (0x01UL << EXTI_REG_SHIFT)
+#define EXTI_REG3                           (0x02UL << EXTI_REG_SHIFT)
+#define EXTI_REG_MASK                       (EXTI_REG1 | EXTI_REG2 | EXTI_REG3)
+#define EXTI_PIN_MASK                       0x0000001FUL
+
+/**
+  * @brief  EXTI Target and bit usage
+  */
+#define EXTI_TARGET_SHIFT                   20U
+#define EXTI_TARGET_MSK_NONE                (0x00UL << EXTI_TARGET_SHIFT)
+#define EXTI_TARGET_MSK_D3SRD               (0x01UL << EXTI_TARGET_SHIFT)
+#define EXTI_TARGET_MSK_CPU1                (0x02UL << EXTI_TARGET_SHIFT)
+#if defined (DUAL_CORE)
+#define EXTI_TARGET_MSK_CPU2                (0x04UL << EXTI_TARGET_SHIFT)
+#define EXTI_TARGET_MASK                    (EXTI_TARGET_MSK_D3SRD | EXTI_TARGET_MSK_CPU1 | EXTI_TARGET_MSK_CPU2)
+#define EXTI_TARGET_MSK_ALL_CPU             (EXTI_TARGET_MSK_CPU1 | EXTI_TARGET_MSK_CPU2)
+#else
+#define EXTI_TARGET_MASK                    (EXTI_TARGET_MSK_D3SRD | EXTI_TARGET_MSK_CPU1)
+#define EXTI_TARGET_MSK_ALL_CPU              EXTI_TARGET_MSK_CPU1
+#endif /* DUAL_CORE */
+#define EXTI_TARGET_MSK_ALL                  EXTI_TARGET_MASK
+
+/**
+  * @brief  EXTI Mask for interrupt & event mode
+  */
+#if defined (DUAL_CORE)
+#define EXTI_MODE_MASK                      (EXTI_MODE_CORE1_EVENT | EXTI_MODE_CORE1_INTERRUPT | EXTI_MODE_CORE2_INTERRUPT | EXTI_MODE_CORE2_EVENT)
+#else
+#define EXTI_MODE_MASK                      (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
+#endif /* DUAL_CORE */
+
+/**
+  * @brief  EXTI Mask for trigger possibilities
+  */
+#define EXTI_TRIGGER_MASK                   (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
+
+/**
+  * @brief  EXTI Line number
+  */
+#if defined (EXTI_LINE_88)
+#define EXTI_LINE_NB                        89UL
+#else
+#define EXTI_LINE_NB                        88UL
+#endif /* EXTI_LINE_88 */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup EXTI_Private_Macros EXTI Private Macros
+  * @{
+  */
+#define IS_EXTI_PROPERTY(__LINE__)      ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
+                                         (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG)          || \
+                                         (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO))
+#if defined (DUAL_CORE)
+#define IS_EXTI_TARGET(__LINE__)        ((((__LINE__) & EXTI_TARGET_MASK)   == EXTI_TARGET_MSK_CPU1)      || \
+                                         (((__LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_CPU2)    || \
+                                         (((__LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL_CPU) || \
+                                         (((__LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL))
+#else
+#define IS_EXTI_TARGET(__LINE__)        ((((__LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_CPU1)   || \
+                                         (((__LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL))
+#endif
+
+#define IS_EXTI_LINE(__LINE__)          ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_EVENT_PRESENCE_MASK | EXTI_REG_MASK | EXTI_PIN_MASK | EXTI_TARGET_MASK)) == 0x00UL) && \
+                                         IS_EXTI_PROPERTY(__LINE__) && IS_EXTI_TARGET(__LINE__) && \
+                                         (((__LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK))      < \
+                                         (((EXTI_LINE_NB / 32UL) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32UL))))
+
+#define IS_EXTI_MODE(__MODE__)          (((__MODE__) & ~EXTI_MODE_MASK) == 0x00UL)
+
+#define IS_EXTI_TRIGGER(__LINE__)       (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00UL)
+
+#define IS_EXTI_PENDING_EDGE(__LINE__)  (((__LINE__) == EXTI_TRIGGER_RISING) || \
+                                         ((__LINE__) == EXTI_TRIGGER_FALLING)|| \
+                                         ((__LINE__) == EXTI_TRIGGER_RISING_FALLING))
+
+#define IS_EXTI_CONFIG_LINE(__LINE__)   (((__LINE__) & EXTI_CONFIG) != 0x00UL)
+
+#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \
+                                         ((__PORT__) == EXTI_GPIOB) || \
+                                         ((__PORT__) == EXTI_GPIOC) || \
+                                         ((__PORT__) == EXTI_GPIOD) || \
+                                         ((__PORT__) == EXTI_GPIOE) || \
+                                         ((__PORT__) == EXTI_GPIOF) || \
+                                         ((__PORT__) == EXTI_GPIOG) || \
+                                         ((__PORT__) == EXTI_GPIOH) || \
+                                         ((__PORT__) == EXTI_GPIOI) || \
+                                         ((__PORT__) == EXTI_GPIOJ) || \
+                                         ((__PORT__) == EXTI_GPIOK))
+
+#define IS_EXTI_GPIO_PIN(__PIN__)       ((__PIN__) < 16UL)
+#if defined (LPTIM4) && defined (LPTIM5)
+#define IS_EXTI_D3_PENDCLR_SRC(__SRC__) (((__SRC__) == EXTI_D3_PENDCLR_SRC_NONE) || \
+                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH6) || \
+                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH7) || \
+                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM4) || \
+                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM5))
+#else
+#define IS_EXTI_D3_PENDCLR_SRC(__SRC__) (((__SRC__) == EXTI_D3_PENDCLR_SRC_NONE) || \
+                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH6) || \
+                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH7) || \
+                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM2) || \
+                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM3))
+#endif /* LPTIM4 && LPTIM5 */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
+  * @brief    EXTI Exported Functions
+  * @{
+  */
+
+/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
+  * @brief    Configuration functions
+  * @{
+  */
+/* Configuration functions ****************************************************/
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
+HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
+HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
+HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
+HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
+  * @brief    IO operation functions
+  * @{
+  */
+/* IO operation functions *****************************************************/
+void              HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
+uint32_t          HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
+void              HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
+void              HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_EXTI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h
new file mode 100644
index 00000000..cfe58cf7
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h
@@ -0,0 +1,2414 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_fdcan.h
+  * @author  MCD Application Team
+  * @brief   Header file of FDCAN HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_FDCAN_H
+#define STM32H7xx_HAL_FDCAN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FDCAN
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FDCAN_Exported_Types FDCAN Exported Types
+  * @{
+  */
+
+/**
+  * @brief HAL State structures definition
+  */
+typedef enum
+{
+  HAL_FDCAN_STATE_RESET      = 0x00U, /*!< FDCAN not yet initialized or disabled */
+  HAL_FDCAN_STATE_READY      = 0x01U, /*!< FDCAN initialized and ready for use   */
+  HAL_FDCAN_STATE_BUSY       = 0x02U, /*!< FDCAN process is ongoing              */
+  HAL_FDCAN_STATE_ERROR      = 0x03U  /*!< FDCAN error state                     */
+} HAL_FDCAN_StateTypeDef;
+
+/**
+  * @brief FDCAN Init structure definition
+  */
+typedef struct
+{
+  uint32_t FrameFormat;                  /*!< Specifies the FDCAN frame format.
+                                              This parameter can be a value of @ref FDCAN_frame_format     */
+
+  uint32_t Mode;                         /*!< Specifies the FDCAN mode.
+                                              This parameter can be a value of @ref FDCAN_operating_mode   */
+
+  FunctionalState AutoRetransmission;    /*!< Enable or disable the automatic retransmission mode.
+                                              This parameter can be set to ENABLE or DISABLE               */
+
+  FunctionalState TransmitPause;         /*!< Enable or disable the Transmit Pause feature.
+                                              This parameter can be set to ENABLE or DISABLE               */
+
+  FunctionalState ProtocolException;      /*!< Enable or disable the Protocol Exception Handling.
+                                              This parameter can be set to ENABLE or DISABLE               */
+
+  uint32_t NominalPrescaler;             /*!< Specifies the value by which the oscillator frequency is
+                                              divided for generating the nominal bit time quanta.
+                                              This parameter must be a number between 1 and 512            */
+
+  uint32_t NominalSyncJumpWidth;         /*!< Specifies the maximum number of time quanta the FDCAN
+                                              hardware is allowed to lengthen or shorten a bit to perform
+                                              resynchronization.
+                                              This parameter must be a number between 1 and 128            */
+
+  uint32_t NominalTimeSeg1;              /*!< Specifies the number of time quanta in Bit Segment 1.
+                                              This parameter must be a number between 2 and 256            */
+
+  uint32_t NominalTimeSeg2;              /*!< Specifies the number of time quanta in Bit Segment 2.
+                                              This parameter must be a number between 2 and 128            */
+
+  uint32_t DataPrescaler;                /*!< Specifies the value by which the oscillator frequency is
+                                              divided for generating the data bit time quanta.
+                                              This parameter must be a number between 1 and 32             */
+
+  uint32_t DataSyncJumpWidth;            /*!< Specifies the maximum number of time quanta the FDCAN
+                                              hardware is allowed to lengthen or shorten a data bit to
+                                              perform resynchronization.
+                                              This parameter must be a number between 1 and 16             */
+
+  uint32_t DataTimeSeg1;                 /*!< Specifies the number of time quanta in Data Bit Segment 1.
+                                              This parameter must be a number between 1 and 32             */
+
+  uint32_t DataTimeSeg2;                 /*!< Specifies the number of time quanta in Data Bit Segment 2.
+                                              This parameter must be a number between 1 and 16             */
+
+  uint32_t MessageRAMOffset;             /*!< Specifies the message RAM start address.
+                                              This parameter must be a number between 0 and 2560           */
+
+  uint32_t StdFiltersNbr;                /*!< Specifies the number of standard Message ID filters.
+                                              This parameter must be a number between 0 and 128            */
+
+  uint32_t ExtFiltersNbr;                /*!< Specifies the number of extended Message ID filters.
+                                              This parameter must be a number between 0 and 64             */
+
+  uint32_t RxFifo0ElmtsNbr;              /*!< Specifies the number of Rx FIFO0 Elements.
+                                              This parameter must be a number between 0 and 64             */
+
+  uint32_t RxFifo0ElmtSize;              /*!< Specifies the Data Field Size in an Rx FIFO 0 element.
+                                              This parameter can be a value of @ref FDCAN_data_field_size  */
+
+  uint32_t RxFifo1ElmtsNbr;              /*!< Specifies the number of Rx FIFO 1 Elements.
+                                              This parameter must be a number between 0 and 64             */
+
+  uint32_t RxFifo1ElmtSize;              /*!< Specifies the Data Field Size in an Rx FIFO 1 element.
+                                              This parameter can be a value of @ref FDCAN_data_field_size  */
+
+  uint32_t RxBuffersNbr;                 /*!< Specifies the number of Dedicated Rx Buffer elements.
+                                              This parameter must be a number between 0 and 64             */
+
+  uint32_t RxBufferSize;                 /*!< Specifies the Data Field Size in an Rx Buffer element.
+                                              This parameter can be a value of @ref FDCAN_data_field_size  */
+
+  uint32_t TxEventsNbr;                  /*!< Specifies the number of Tx Event FIFO elements.
+                                              This parameter must be a number between 0 and 32             */
+
+  uint32_t TxBuffersNbr;                 /*!< Specifies the number of Dedicated Tx Buffers.
+                                              This parameter must be a number between 0 and 32             */
+
+  uint32_t TxFifoQueueElmtsNbr;          /*!< Specifies the number of Tx Buffers used for Tx FIFO/Queue.
+                                              This parameter must be a number between 0 and 32             */
+
+  uint32_t TxFifoQueueMode;              /*!< Tx FIFO/Queue Mode selection.
+                                              This parameter can be a value of @ref FDCAN_txFifoQueue_Mode */
+
+  uint32_t TxElmtSize;                   /*!< Specifies the Data Field Size in a Tx Element.
+                                              This parameter can be a value of @ref FDCAN_data_field_size  */
+
+} FDCAN_InitTypeDef;
+
+/**
+  * @brief  FDCAN clock calibration unit structure definition
+  */
+typedef struct
+{
+  uint32_t ClockCalibration;     /*!< Enable or disable the clock calibration.
+                                      This parameter can be a value of @ref FDCAN_clock_calibration.       */
+
+  uint32_t ClockDivider;         /*!< Specifies the FDCAN kernel clock divider when the clock calibration
+                                      is bypassed.
+                                      This parameter can be a value of @ref FDCAN_clock_divider            */
+
+  uint32_t MinOscClkPeriods;     /*!< Configures the minimum number of periods in two CAN bit times. The
+                                      actual configured number of periods is MinOscClkPeriods x 32.
+                                      This parameter must be a number between 0x00 and 0xFF                */
+
+  uint32_t CalFieldLength;       /*!< Specifies the calibration field length.
+                                      This parameter can be a value of @ref FDCAN_calibration_field_length */
+
+  uint32_t TimeQuantaPerBitTime; /*!< Configures the number of time quanta per bit time.
+                                      This parameter must be a number between 4 and 25                     */
+
+  uint32_t WatchdogStartValue;   /*!< Start value of the Calibration Watchdog Counter.
+                                      If set to zero the counter is disabled.
+                                      This parameter must be a number between 0x0000 and 0xFFFF            */
+
+} FDCAN_ClkCalUnitTypeDef;
+
+/**
+  * @brief  FDCAN filter structure definition
+  */
+typedef struct
+{
+  uint32_t IdType;           /*!< Specifies the identifier type.
+                                  This parameter can be a value of @ref FDCAN_id_type       */
+
+  uint32_t FilterIndex;      /*!< Specifies the filter which will be initialized.
+                                  This parameter must be a number between:
+                                   - 0 and 127, if IdType is FDCAN_STANDARD_ID
+                                   - 0 and 63, if IdType is FDCAN_EXTENDED_ID               */
+
+  uint32_t FilterType;       /*!< Specifies the filter type.
+                                  This parameter can be a value of @ref FDCAN_filter_type.
+                                  The value FDCAN_EXT_FILTER_RANGE_NO_EIDM is permitted
+                                  only when IdType is FDCAN_EXTENDED_ID.
+                                  This parameter is ignored if FilterConfig is set to
+                                  FDCAN_FILTER_TO_RXBUFFER                                  */
+
+  uint32_t FilterConfig;     /*!< Specifies the filter configuration.
+                                  This parameter can be a value of @ref FDCAN_filter_config */
+
+  uint32_t FilterID1;        /*!< Specifies the filter identification 1.
+                                  This parameter must be a number between:
+                                   - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+                                   - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID       */
+
+  uint32_t FilterID2;        /*!< Specifies the filter identification 2.
+                                  This parameter is ignored if FilterConfig is set to
+                                  FDCAN_FILTER_TO_RXBUFFER.
+                                  This parameter must be a number between:
+                                   - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+                                   - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID       */
+
+  uint32_t RxBufferIndex;    /*!< Contains the index of the Rx buffer in which the
+                                  matching message will be stored.
+                                  This parameter must be a number between 0 and 63.
+                                  This parameter is ignored if FilterConfig is different
+                                  from FDCAN_FILTER_TO_RXBUFFER                             */
+
+  uint32_t IsCalibrationMsg; /*!< Specifies whether the filter is configured for
+                                  calibration messages.
+                                  This parameter is ignored if FilterConfig is different
+                                  from FDCAN_FILTER_TO_RXBUFFER.
+                                  This parameter can be:
+                                   - 0 : ordinary message
+                                   - 1 : calibration message                                */
+
+} FDCAN_FilterTypeDef;
+
+/**
+  * @brief  FDCAN Tx header structure definition
+  */
+typedef struct
+{
+  uint32_t Identifier;          /*!< Specifies the identifier.
+                                     This parameter must be a number between:
+                                      - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+                                      - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID               */
+
+  uint32_t IdType;              /*!< Specifies the identifier type for the message that will be
+                                     transmitted.
+                                     This parameter can be a value of @ref FDCAN_id_type               */
+
+  uint32_t TxFrameType;         /*!< Specifies the frame type of the message that will be transmitted.
+                                     This parameter can be a value of @ref FDCAN_frame_type            */
+
+  uint32_t DataLength;          /*!< Specifies the length of the frame that will be transmitted.
+                                      This parameter can be a value of @ref FDCAN_data_length_code     */
+
+  uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
+                                     This parameter can be a value of @ref FDCAN_error_state_indicator */
+
+  uint32_t BitRateSwitch;       /*!< Specifies whether the Tx frame will be transmitted with or without
+                                     bit rate switching.
+                                     This parameter can be a value of @ref FDCAN_bit_rate_switching    */
+
+  uint32_t FDFormat;            /*!< Specifies whether the Tx frame will be transmitted in classic or
+                                     FD format.
+                                     This parameter can be a value of @ref FDCAN_format                */
+
+  uint32_t TxEventFifoControl;  /*!< Specifies the event FIFO control.
+                                     This parameter can be a value of @ref FDCAN_EFC                   */
+
+  uint32_t MessageMarker;       /*!< Specifies the message marker to be copied into Tx Event FIFO
+                                     element for identification of Tx message status.
+                                     This parameter must be a number between 0 and 0xFF                */
+
+} FDCAN_TxHeaderTypeDef;
+
+/**
+  * @brief  FDCAN Rx header structure definition
+  */
+typedef struct
+{
+  uint32_t Identifier;            /*!< Specifies the identifier.
+                                       This parameter must be a number between:
+                                        - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+                                        - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID               */
+
+  uint32_t IdType;                /*!< Specifies the identifier type of the received message.
+                                       This parameter can be a value of @ref FDCAN_id_type               */
+
+  uint32_t RxFrameType;           /*!< Specifies the the received message frame type.
+                                       This parameter can be a value of @ref FDCAN_frame_type            */
+
+  uint32_t DataLength;            /*!< Specifies the received frame length.
+                                        This parameter can be a value of @ref FDCAN_data_length_code     */
+
+  uint32_t ErrorStateIndicator;   /*!< Specifies the error state indicator.
+                                       This parameter can be a value of @ref FDCAN_error_state_indicator */
+
+  uint32_t BitRateSwitch;         /*!< Specifies whether the Rx frame is received with or without bit
+                                       rate switching.
+                                       This parameter can be a value of @ref FDCAN_bit_rate_switching    */
+
+  uint32_t FDFormat;              /*!< Specifies whether the Rx frame is received in classic or FD
+                                       format.
+                                       This parameter can be a value of @ref FDCAN_format                */
+
+  uint32_t RxTimestamp;           /*!< Specifies the timestamp counter value captured on start of frame
+                                       reception.
+                                       This parameter must be a number between 0 and 0xFFFF              */
+
+  uint32_t FilterIndex;           /*!< Specifies the index of matching Rx acceptance filter element.
+                                       This parameter must be a number between:
+                                        - 0 and 127, if IdType is FDCAN_STANDARD_ID
+                                        - 0 and 63, if IdType is FDCAN_EXTENDED_ID                       */
+
+  uint32_t IsFilterMatchingFrame; /*!< Specifies whether the accepted frame did not match any Rx filter.
+                                         Acceptance of non-matching frames may be enabled via
+                                         HAL_FDCAN_ConfigGlobalFilter().
+                                         This parameter can be 0 or 1                                    */
+
+} FDCAN_RxHeaderTypeDef;
+
+/**
+  * @brief  FDCAN Tx event FIFO structure definition
+  */
+typedef struct
+{
+  uint32_t Identifier;          /*!< Specifies the identifier.
+                                     This parameter must be a number between:
+                                      - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+                                      - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID               */
+
+  uint32_t IdType;              /*!< Specifies the identifier type for the transmitted message.
+                                     This parameter can be a value of @ref FDCAN_id_type               */
+
+  uint32_t TxFrameType;         /*!< Specifies the frame type of the transmitted message.
+                                     This parameter can be a value of @ref FDCAN_frame_type            */
+
+  uint32_t DataLength;          /*!< Specifies the length of the transmitted frame.
+                                     This parameter can be a value of @ref FDCAN_data_length_code      */
+
+  uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
+                                     This parameter can be a value of @ref FDCAN_error_state_indicator */
+
+  uint32_t BitRateSwitch;       /*!< Specifies whether the Tx frame is transmitted with or without bit
+                                     rate switching.
+                                     This parameter can be a value of @ref FDCAN_bit_rate_switching    */
+
+  uint32_t FDFormat;            /*!< Specifies whether the Tx frame is transmitted in classic or FD
+                                     format.
+                                     This parameter can be a value of @ref FDCAN_format                */
+
+  uint32_t TxTimestamp;         /*!< Specifies the timestamp counter value captured on start of frame
+                                     transmission.
+                                     This parameter must be a number between 0 and 0xFFFF              */
+
+  uint32_t MessageMarker;       /*!< Specifies the message marker copied into Tx Event FIFO element
+                                     for identification of Tx message status.
+                                     This parameter must be a number between 0 and 0xFF                */
+
+  uint32_t EventType;           /*!< Specifies the event type.
+                                     This parameter can be a value of @ref FDCAN_event_type            */
+
+} FDCAN_TxEventFifoTypeDef;
+
+/**
+  * @brief  FDCAN High Priority Message Status structure definition
+  */
+typedef struct
+{
+  uint32_t FilterList;     /*!< Specifies the filter list of the matching filter element.
+                                This parameter can be:
+                                 - 0 : Standard Filter List
+                                 - 1 : Extended Filter List                                */
+
+  uint32_t FilterIndex;    /*!< Specifies the index of matching filter element.
+                                This parameter can be a number between:
+                                - 0 and 127, if FilterList is 0 (Standard)
+                                - 0 and 63, if FilterList is 1 (Extended)                  */
+
+  uint32_t MessageStorage; /*!< Specifies the HP Message Storage.
+                                This parameter can be a value of @ref FDCAN_hp_msg_storage */
+
+  uint32_t MessageIndex;   /*!< Specifies the Index of Rx FIFO element to which the
+                                message was stored.
+                                This parameter is valid only when MessageStorage is:
+                                  FDCAN_HP_STORAGE_RXFIFO0
+                                 or
+                                  FDCAN_HP_STORAGE_RXFIFO1                                 */
+
+} FDCAN_HpMsgStatusTypeDef;
+
+/**
+  * @brief FDCAN Protocol Status structure definition
+  */
+typedef struct
+{
+  uint32_t LastErrorCode;     /*!< Specifies the type of the last error that occurred on the FDCAN bus.
+                                   This parameter can be a value of @ref FDCAN_protocol_error_code                           */
+
+  uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase of a CAN FD format
+                                   frame with its BRS flag set.
+                                   This parameter can be a value of @ref FDCAN_protocol_error_code                           */
+
+  uint32_t Activity;          /*!< Specifies the FDCAN module communication state.
+                                   This parameter can be a value of @ref FDCAN_communication_state                           */
+
+  uint32_t ErrorPassive;      /*!< Specifies the FDCAN module error status.
+                                   This parameter can be:
+                                    - 0 : The FDCAN is in Error_Active state
+                                    - 1 : The FDCAN is in Error_Passive state                                                */
+
+  uint32_t Warning;           /*!< Specifies the FDCAN module warning status.
+                                   This parameter can be:
+                                    - 0 : error counters (RxErrorCnt and TxErrorCnt) are below the Error_Warning limit of 96
+                                    - 1 : at least one of error counters has reached the Error_Warning limit of 96           */
+
+  uint32_t BusOff;            /*!< Specifies the FDCAN module Bus_Off status.
+                                   This parameter can be:
+                                    - 0 : The FDCAN is not in Bus_Off state
+                                    - 1 : The FDCAN is in Bus_Off state                                                      */
+
+  uint32_t RxESIflag;         /*!< Specifies ESI flag of last received CAN FD message.
+                                   This parameter can be:
+                                    - 0 : Last received CAN FD message did not have its ESI flag set
+                                    - 1 : Last received CAN FD message had its ESI flag set                                  */
+
+  uint32_t RxBRSflag;         /*!< Specifies BRS flag of last received CAN FD message.
+                                   This parameter can be:
+                                    - 0 : Last received CAN FD message did not have its BRS flag set
+                                    - 1 : Last received CAN FD message had its BRS flag set                                  */
+
+  uint32_t RxFDFflag;         /*!< Specifies if CAN FD message (FDF flag set) has been received since last protocol status.
+                                   This parameter can be:
+                                    - 0 : no CAN FD message received
+                                    - 1 : CAN FD message received                                                            */
+
+  uint32_t ProtocolException; /*!< Specifies the FDCAN module Protocol Exception status.
+                                   This parameter can be:
+                                    - 0 : No protocol exception event occurred since last read access
+                                    - 1 : Protocol exception event occurred                                                  */
+
+  uint32_t TDCvalue;          /*!< Specifies the Transmitter Delay Compensation Value.
+                                   This parameter can be a number between 0 and 127                                          */
+
+} FDCAN_ProtocolStatusTypeDef;
+
+/**
+  * @brief FDCAN Error Counters structure definition
+  */
+typedef struct
+{
+  uint32_t TxErrorCnt;     /*!< Specifies the Transmit Error Counter Value.
+                                This parameter can be a number between 0 and 255                                         */
+
+  uint32_t RxErrorCnt;     /*!< Specifies the Receive Error Counter Value.
+                                This parameter can be a number between 0 and 127                                         */
+
+  uint32_t RxErrorPassive; /*!< Specifies the Receive Error Passive status.
+                                This parameter can be:
+                                 - 0 : The Receive Error Counter (RxErrorCnt) is below the error passive level of 128
+                                 - 1 : The Receive Error Counter (RxErrorCnt) has reached the error passive level of 128 */
+
+  uint32_t ErrorLogging;   /*!< Specifies the Transmit/Receive error logging counter value.
+                                This parameter can be a number between 0 and 255.
+                                This counter is incremented each time when a FDCAN protocol error causes the TxErrorCnt
+                                or the RxErrorCnt to be incremented. The counter stops at 255; the next increment of
+                                TxErrorCnt or RxErrorCnt sets interrupt flag FDCAN_FLAG_ERROR_LOGGING_OVERFLOW           */
+
+} FDCAN_ErrorCountersTypeDef;
+
+/**
+  * @brief FDCAN TT Init structure definition
+  */
+typedef struct
+{
+  uint32_t OperationMode;     /*!< Specifies the FDCAN Operation Mode.
+                                   This parameter can be a value of @ref FDCAN_operation_mode               */
+
+  uint32_t GapEnable;         /*!< Specifies the FDCAN TT Operation.
+                                   This parameter can be a value of @ref FDCAN_TT_operation.
+                                   This parameter is ignored if OperationMode is set to
+                                   FDCAN_TT_COMMUNICATION_LEVEL0                                            */
+
+  uint32_t TimeMaster;        /*!< Specifies whether the instance is a slave or a potential master.
+                                   This parameter can be a value of @ref FDCAN_TT_time_master               */
+
+  uint32_t SyncDevLimit;      /*!< Specifies the Synchronization Deviation Limit SDL of the TUR
+                                   numerator : TUR = (Numerator � SDL) / Denominator.
+                                   With : SDL = 2^(SyncDevLimit+5).
+                                   This parameter must be a number between 0 and 7                          */
+
+  uint32_t InitRefTrigOffset; /*!< Specifies the Initial Reference Trigger Offset.
+                                   This parameter must be a number between 0 and 127                        */
+
+  uint32_t ExternalClkSync;   /*!< Enable or disable External Clock Synchronization.
+                                   This parameter can be a value of @ref FDCAN_TT_external_clk_sync.
+                                   This parameter is ignored if OperationMode is set to
+                                   FDCAN_TT_COMMUNICATION_LEVEL1                                            */
+
+  uint32_t AppWdgLimit;       /*!< Specifies the Application Watchdog Limit : maximum time after
+                                   which the application has to serve the application watchdog.
+                                   The application watchdog is incremented once each 256 NTUs.
+                                   The application watchdog can be disabled by setting AppWdgLimit to 0.
+                                   This parameter must be a number between 0 and 255.
+                                   This parameter is ignored if OperationMode is set to
+                                   FDCAN_TT_COMMUNICATION_LEVEL0                                            */
+
+  uint32_t GlobalTimeFilter;  /*!< Enable or disable Global Time Filtering.
+                                   This parameter can be a value of @ref FDCAN_TT_global_time_filtering.
+                                   This parameter is ignored if OperationMode is set to
+                                   FDCAN_TT_COMMUNICATION_LEVEL1                                            */
+
+  uint32_t ClockCalibration;  /*!< Enable or disable Automatic Clock Calibration.
+                                   This parameter can be a value of @ref FDCAN_TT_auto_clk_calibration.
+                                   This parameter is ignored if OperationMode is set to
+                                   FDCAN_TT_COMMUNICATION_LEVEL1                                            */
+
+  uint32_t EvtTrigPolarity;   /*!< Specifies the Event Trigger Polarity.
+                                   This parameter can be a value of @ref FDCAN_TT_event_trig_polarity.
+                                   This parameter is ignored if OperationMode is set to
+                                   FDCAN_TT_COMMUNICATION_LEVEL0                                            */
+
+  uint32_t BasicCyclesNbr;    /*!< Specifies the nubmer of basic cycles in the system matrix.
+                                   This parameter can be a value of @ref FDCAN_TT_basic_cycle_number        */
+
+  uint32_t CycleStartSync;    /*!< Enable or disable synchronization pulse output at pin fdcan1_soc.
+                                   This parameter can be a value of @ref FDCAN_TT_cycle_start_sync          */
+
+  uint32_t TxEnableWindow;    /*!< Specifies the length of Tx enable window in NTUs.
+                                   This parameter must be a number between 1 and 16                         */
+
+  uint32_t ExpTxTrigNbr;      /*!< Specifies the number of expected Tx_Triggers in the system matrix.
+                                   This is the sum of Tx_Triggers for exclusive, single arbitrating and
+                                   merged arbitrating windows.
+                                   This parameter must be a number between 0 and 4095                       */
+
+  uint32_t TURNumerator;      /*!< Specifies the TUR (Time Unit Ratio) numerator.
+                                   It is adviced to set this parameter to the largest applicable value.
+                                   This parameter must be a number between 0x10000 and 0x1FFFF              */
+
+  uint32_t TURDenominator;    /*!< Specifies the TUR (Time Unit Ratio) denominator.
+                                   This parameter must be a number between 0x0001 and 0x3FFF                */
+
+  uint32_t TriggerMemoryNbr;  /*!< Specifies the number of trigger memory elements.
+                                   This parameter must be a number between 0 and 64                         */
+
+  uint32_t StopWatchTrigSel;  /*!< Specifies the input to be used as stop watch trigger.
+                                   This parameter can be a value of @ref FDCAN_TT_stop_watch_trig_selection */
+
+  uint32_t EventTrigSel;      /*!< Specifies the input to be used as event trigger.
+                                   This parameter can be a value of @ref FDCAN_TT_event_trig_selection      */
+
+} FDCAN_TT_ConfigTypeDef;
+
+/**
+  * @brief  FDCAN Trigger structure definition
+  */
+typedef struct
+{
+  uint32_t TriggerIndex;  /*!< Specifies the trigger which will be configured.
+                               This parameter must be a number between 0 and 63                                 */
+
+  uint32_t TimeMark;      /*!< Specifies the cycle time for which the trigger becomes active.
+                               This parameter must be a number between 0 and 0xFFFF                             */
+
+  uint32_t RepeatFactor;  /*!< Specifies the trigger repeat factor.
+                               This parameter can be a value of @ref FDCAN_TT_Repeat_Factor                     */
+
+  uint32_t StartCycle;    /*!< Specifies the index of the first cycle in which the trigger becomes active.
+                               This parameter is ignored if RepeatFactor is set to FDCAN_TT_REPEAT_EVERY_CYCLE.
+                               This parameter must be a number between 0 and RepeatFactor                       */
+
+  uint32_t TmEventInt;    /*!< Enable or disable the internal time mark event.
+                               If enabled, FDCAN_TT_FLAG_TRIG_TIME_MARK flag is set when trigger memory element
+                               becomes active.
+                               This parameter can be a value of @ref FDCAN_TT_Time_Mark_Event_Internal          */
+
+  uint32_t TmEventExt;    /*!< Enable or disable the external time mark event.
+                               If enabled, and if TTOCN.TTIE is set, a pulse is generated at fdcan1_tmp when
+                               trigger memory element becomes active.
+                               This parameter can be a value of @ref FDCAN_TT_Time_Mark_Event_External          */
+
+  uint32_t TriggerType;   /*!< Specifies the trigger type.
+                               This parameter can be a value of @ref FDCAN_TT_Trigger_Type                      */
+
+  uint32_t FilterType;    /*!< Specifies the filter identifier type.
+                               This parameter can be a value of @ref FDCAN_id_type                              */
+
+  uint32_t TxBufferIndex; /*!< Specifies the index of the Tx buffer for which the trigger is valid.
+                               This parameter can be a value of @ref FDCAN_Tx_location.
+                               This parameter is taken in consideration only if the trigger is configured for
+                               transmission.                                                                    */
+
+  uint32_t FilterIndex;   /*!< Specifies the filter for which the trigger is valid.
+                               This parameter is taken in consideration only if the trigger is configured for
+                               reception.
+                               This parameter must be a number between:
+                                - 0 and 127, if FilterType is FDCAN_STANDARD_ID
+                                - 0 and 63, if FilterType is FDCAN_EXTENDED_ID                                  */
+
+} FDCAN_TriggerTypeDef;
+
+/**
+  * @brief  FDCAN TT Operation Status structure definition
+  */
+typedef struct
+{
+  uint32_t ErrorLevel;       /*!< Specifies the type of the TT operation error level.
+                                  This parameter can be a value of @ref FDCAN_TT_error_level                    */
+
+  uint32_t MasterState;      /*!< Specifies the type of the TT master state.
+                                  This parameter can be a value of @ref FDCAN_TT_master_state                   */
+
+  uint32_t SyncState;        /*!< Specifies the type of the TT synchronization state.
+                                  This parameter can be a value of @ref FDCAN_TT_sync_state                     */
+
+  uint32_t GTimeQuality;     /*!< Specifies the Quality of Global Time Phase.
+                                  This parameter is only relevant in Level 0 and Level 2, otherwise fixed to 0.
+                                  This parameter can be:
+                                   - 0 : Global time not valid
+                                   - 1 : Global time in phase with Time Master                                  */
+
+  uint32_t ClockQuality;     /*!< Specifies the Quality of Clock Speed.
+                                  This parameter is only relevant in Level 0 and Level 2, otherwise fixed to 1.
+                                  This parameter can be:
+                                   - 0 : Local clock speed not synchronized to Time Master clock speed
+                                   - 1 : Synchronization Deviation = SDL                                        */
+
+  uint32_t RefTrigOffset;    /*!< Specifies the Actual Reference Trigger Offset Value.
+                                  This parameter can be a number between 0 and 0xFF                             */
+
+  uint32_t GTimeDiscPending; /*!< Specifies the Global Time Discontinuity State.
+                                  This parameter can be:
+                                   - 0 : No global time preset pending
+                                   - 1 : Node waits for the global time preset to take effect                   */
+
+  uint32_t GapFinished;      /*!< Specifies whether a Gap is finished.
+                                  This parameter can be:
+                                   - 0 : Reset at the end of each reference message
+                                   - 1 : Gap finished                                                           */
+
+  uint32_t MasterPriority;   /*!< Specifies the Priority of actual Time Master.
+                                  This parameter can be a number between 0 and 0x7                              */
+
+  uint32_t GapStarted;       /*!< Specifies whether a Gap is started.
+                                  This parameter can be:
+                                   - 0 : No Gap in schedule
+                                   - 1 : Gap time after Basic Cycle has started                                 */
+
+  uint32_t WaitForEvt;       /*!< Specifies whether a Gap is annouced.
+                                  This parameter can be:
+                                   - 0 : No Gap announced, reset by a reference message with Next_is_Gap = 0
+                                   - 1 : Reference message with Next_is_Gap = 1 received                        */
+
+  uint32_t AppWdgEvt;        /*!< Specifies the Application Watchdog State.
+                                  This parameter can be:
+                                   - 0 : Application Watchdog served in time
+                                   - 1 : Failed to serve Application Watchdog in time                           */
+
+  uint32_t ECSPending;       /*!< Specifies the External Clock Synchronization State.
+                                  This parameter can be:
+                                   - 0 : No external clock synchronization pending
+                                   - 1 : Node waits for external clock synchronization to take effect           */
+
+  uint32_t PhaseLock;        /*!< Specifies the Phase Lock State.
+                                  This parameter can be:
+                                   - 0 : Phase outside range
+                                   - 1 : Phase inside range                                                     */
+
+} FDCAN_TTOperationStatusTypeDef;
+
+/**
+  * @brief  FDCAN Message RAM blocks
+  */
+typedef struct
+{
+  uint32_t StandardFilterSA; /*!< Specifies the Standard Filter List Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t ExtendedFilterSA; /*!< Specifies the Extended Filter List Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t RxFIFO0SA;        /*!< Specifies the Rx FIFO 0 Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t RxFIFO1SA;        /*!< Specifies the Rx FIFO 1 Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t RxBufferSA;       /*!< Specifies the Rx Buffer Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t TxEventFIFOSA;    /*!< Specifies the Tx Event FIFO Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t TxBufferSA;       /*!< Specifies the Tx Buffers Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t TxFIFOQSA;        /*!< Specifies the Tx FIFO/Queue Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t TTMemorySA;       /*!< Specifies the Trigger Memory Start Address.
+                                  This parameter must be a 32-bit word address      */
+
+  uint32_t EndAddress;       /*!< Specifies the End Address of the allocated RAM.
+                                  This parameter must be a 32-bit word address      */
+
+} FDCAN_MsgRamAddressTypeDef;
+
+/**
+  * @brief  FDCAN handle structure definition
+  */
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+typedef struct __FDCAN_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+{
+  FDCAN_GlobalTypeDef         *Instance;        /*!< Register base address     */
+
+  TTCAN_TypeDef               *ttcan;           /*!< TT register base address  */
+
+  FDCAN_InitTypeDef           Init;             /*!< FDCAN required parameters */
+
+  FDCAN_MsgRamAddressTypeDef  msgRam;           /*!< FDCAN Message RAM blocks  */
+
+  uint32_t                    LatestTxFifoQRequest; /*!< FDCAN Tx buffer index
+                                               of latest Tx FIFO/Queue request */
+
+  __IO HAL_FDCAN_StateTypeDef State;            /*!< FDCAN communication state */
+
+  HAL_LockTypeDef             Lock;             /*!< FDCAN locking object      */
+
+  __IO uint32_t               ErrorCode;        /*!< FDCAN Error code          */
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+  void (* ClockCalibrationCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs);         /*!< FDCAN Clock Calibration callback          */
+  void (* TxEventFifoCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs);                 /*!< FDCAN Tx Event Fifo callback              */
+  void (* RxFifo0Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs);                         /*!< FDCAN Rx Fifo 0 callback                  */
+  void (* RxFifo1Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs);                         /*!< FDCAN Rx Fifo 1 callback                  */
+  void (* TxFifoEmptyCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                          /*!< FDCAN Tx Fifo Empty callback              */
+  void (* TxBufferCompleteCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);             /*!< FDCAN Tx Buffer complete callback         */
+  void (* TxBufferAbortCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);                /*!< FDCAN Tx Buffer abort callback            */
+  void (* RxBufferNewMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                   /*!< FDCAN Rx Buffer New Message callback      */
+  void (* HighPriorityMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                  /*!< FDCAN High priority message callback      */
+  void (* TimestampWraparoundCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                  /*!< FDCAN Timestamp wraparound callback       */
+  void (* TimeoutOccurredCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                      /*!< FDCAN Timeout occurred callback           */
+  void (* ErrorCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                                /*!< FDCAN Error callback                      */
+  void (* ErrorStatusCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs);                 /*!< FDCAN Error status callback               */
+  void (* TT_ScheduleSyncCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs);             /*!< FDCAN T Schedule Synchronization callback */
+  void (* TT_TimeMarkCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs);                  /*!< FDCAN TT Time Mark callback               */
+  void (* TT_StopWatchCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount); /*!< FDCAN TT Stop Watch callback              */
+  void (* TT_GlobalTimeCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs);                /*!< FDCAN TT Global Time callback             */
+
+  void (* MspInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                              /*!< FDCAN Msp Init callback                   */
+  void (* MspDeInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                            /*!< FDCAN Msp DeInit callback                 */
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+} FDCAN_HandleTypeDef;
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+/**
+  * @brief  HAL FDCAN common Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_FDCAN_TX_FIFO_EMPTY_CB_ID        = 0x00U, /*!< FDCAN Tx Fifo Empty callback ID         */
+  HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID    = 0x01U, /*!< FDCAN Rx buffer new message callback ID */
+  HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID    = 0x02U, /*!< FDCAN High priority message callback ID */
+  HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID = 0x03U, /*!< FDCAN Timestamp wraparound callback ID  */
+  HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID     = 0x04U, /*!< FDCAN Timeout occurred callback ID      */
+  HAL_FDCAN_ERROR_CALLBACK_CB_ID       = 0x05U, /*!< FDCAN Error callback ID                 */
+
+  HAL_FDCAN_MSPINIT_CB_ID              = 0x06U, /*!< FDCAN MspInit callback ID               */
+  HAL_FDCAN_MSPDEINIT_CB_ID            = 0x07U, /*!< FDCAN MspDeInit callback ID             */
+
+} HAL_FDCAN_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL FDCAN Callback pointer definition
+  */
+typedef  void (*pFDCAN_CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan);                                                     /*!< pointer to a common FDCAN callback function                    */
+typedef  void (*pFDCAN_ClockCalibrationCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs);         /*!< pointer to Clock Calibration FDCAN callback function           */
+typedef  void (*pFDCAN_TxEventFifoCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs);                 /*!< pointer to Tx event Fifo FDCAN callback function               */
+typedef  void (*pFDCAN_RxFifo0CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs);                         /*!< pointer to Rx Fifo 0 FDCAN callback function                   */
+typedef  void (*pFDCAN_RxFifo1CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs);                         /*!< pointer to Rx Fifo 1 FDCAN callback function                   */
+typedef  void (*pFDCAN_TxBufferCompleteCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);             /*!< pointer to Tx Buffer complete FDCAN callback function          */
+typedef  void (*pFDCAN_TxBufferAbortCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);                /*!< pointer to Tx Buffer abort FDCAN callback function             */
+typedef  void (*pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs);                 /*!< pointer to Error Status callback function                      */
+typedef  void (*pFDCAN_TT_ScheduleSyncCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs);             /*!< pointer to TT Schedule Synchronization FDCAN callback function */
+typedef  void (*pFDCAN_TT_TimeMarkCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs);                  /*!< pointer to TT Time Mark FDCAN callback function                */
+typedef  void (*pFDCAN_TT_StopWatchCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount); /*!< pointer to TT Stop Watch FDCAN callback function               */
+typedef  void (*pFDCAN_TT_GlobalTimeCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs);                /*!< pointer to TT Global Time FDCAN callback function              */
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FDCAN_Exported_Constants FDCAN Exported Constants
+  * @{
+  */
+
+/** @defgroup HAL_FDCAN_Error_Code HAL FDCAN Error Code
+  * @{
+  */
+#define HAL_FDCAN_ERROR_NONE            ((uint32_t)0x00000000U) /*!< No error                                                               */
+#define HAL_FDCAN_ERROR_TIMEOUT         ((uint32_t)0x00000001U) /*!< Timeout error                                                          */
+#define HAL_FDCAN_ERROR_NOT_INITIALIZED ((uint32_t)0x00000002U) /*!< Peripheral not initialized                                             */
+#define HAL_FDCAN_ERROR_NOT_READY       ((uint32_t)0x00000004U) /*!< Peripheral not ready                                                   */
+#define HAL_FDCAN_ERROR_NOT_STARTED     ((uint32_t)0x00000008U) /*!< Peripheral not started                                                 */
+#define HAL_FDCAN_ERROR_NOT_SUPPORTED   ((uint32_t)0x00000010U) /*!< Mode not supported                                                     */
+#define HAL_FDCAN_ERROR_PARAM           ((uint32_t)0x00000020U) /*!< Parameter error                                                        */
+#define HAL_FDCAN_ERROR_PENDING         ((uint32_t)0x00000040U) /*!< Pending operation                                                      */
+#define HAL_FDCAN_ERROR_RAM_ACCESS      ((uint32_t)0x00000080U) /*!< Message RAM Access Failure                                             */
+#define HAL_FDCAN_ERROR_FIFO_EMPTY      ((uint32_t)0x00000100U) /*!< Put element in full FIFO                                               */
+#define HAL_FDCAN_ERROR_FIFO_FULL       ((uint32_t)0x00000200U) /*!< Get element from empty FIFO                                            */
+#define HAL_FDCAN_ERROR_LOG_OVERFLOW    FDCAN_IR_ELO            /*!< Overflow of CAN Error Logging Counter                                  */
+#define HAL_FDCAN_ERROR_RAM_WDG         FDCAN_IR_WDI            /*!< Message RAM Watchdog event occurred                                    */
+#define HAL_FDCAN_ERROR_PROTOCOL_ARBT   FDCAN_IR_PEA            /*!< Protocol Error in Arbitration Phase (Nominal Bit Time is used)         */
+#define HAL_FDCAN_ERROR_PROTOCOL_DATA   FDCAN_IR_PED            /*!< Protocol Error in Data Phase (Data Bit Time is used)                   */
+#define HAL_FDCAN_ERROR_RESERVED_AREA   FDCAN_IR_ARA            /*!< Access to Reserved Address                                             */
+#define HAL_FDCAN_ERROR_TT_GLOBAL_TIME  FDCAN_TTIR_GTE          /*!< Global Time Error : Synchronization deviation exceeded limit           */
+#define HAL_FDCAN_ERROR_TT_TX_UNDERFLOW FDCAN_TTIR_TXU          /*!< Tx Count Underflow : Less Tx trigger than expected in one matrix cycle */
+#define HAL_FDCAN_ERROR_TT_TX_OVERFLOW  FDCAN_TTIR_TXO          /*!< Tx Count Overflow : More Tx trigger than expected in one matrix cycle  */
+#define HAL_FDCAN_ERROR_TT_SCHEDULE1    FDCAN_TTIR_SE1          /*!< Scheduling error 1                                                     */
+#define HAL_FDCAN_ERROR_TT_SCHEDULE2    FDCAN_TTIR_SE2          /*!< Scheduling error 2                                                     */
+#define HAL_FDCAN_ERROR_TT_NO_INIT_REF  FDCAN_TTIR_IWT          /*!< No system startup due to missing reference message                     */
+#define HAL_FDCAN_ERROR_TT_NO_REF       FDCAN_TTIR_WT           /*!< Missing reference message                                              */
+#define HAL_FDCAN_ERROR_TT_APPL_WDG     FDCAN_TTIR_AW           /*!< Application watchdog not served in time                                */
+#define HAL_FDCAN_ERROR_TT_CONFIG       FDCAN_TTIR_CER          /*!< Error found in trigger list                                            */
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+#define HAL_FDCAN_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100U) /*!< Invalid Callback error                                                */
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_frame_format FDCAN Frame Format
+  * @{
+  */
+#define FDCAN_FRAME_CLASSIC   ((uint32_t)0x00000000U)                         /*!< Classic mode                      */
+#define FDCAN_FRAME_FD_NO_BRS ((uint32_t)FDCAN_CCCR_FDOE)                     /*!< FD mode without BitRate Switching */
+#define FDCAN_FRAME_FD_BRS    ((uint32_t)(FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE)) /*!< FD mode with BitRate Switching    */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_operating_mode FDCAN Operating Mode
+  * @{
+  */
+#define FDCAN_MODE_NORMAL               ((uint32_t)0x00000000U) /*!< Normal mode               */
+#define FDCAN_MODE_RESTRICTED_OPERATION ((uint32_t)0x00000001U) /*!< Restricted Operation mode */
+#define FDCAN_MODE_BUS_MONITORING       ((uint32_t)0x00000002U) /*!< Bus Monitoring mode       */
+#define FDCAN_MODE_INTERNAL_LOOPBACK    ((uint32_t)0x00000003U) /*!< Internal LoopBack mode    */
+#define FDCAN_MODE_EXTERNAL_LOOPBACK    ((uint32_t)0x00000004U) /*!< External LoopBack mode    */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_clock_calibration FDCAN Clock Calibration
+  * @{
+  */
+#define FDCAN_CLOCK_CALIBRATION_DISABLE ((uint32_t)0x00000000U) /*!< Disable Clock Calibration */
+#define FDCAN_CLOCK_CALIBRATION_ENABLE  ((uint32_t)0x00000001U) /*!< Enable Clock Calibration  */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_clock_divider FDCAN Clock Divider
+  * @{
+  */
+#define FDCAN_CLOCK_DIV1  ((uint32_t)0x00000000U) /*!< Divide kernel clock by 1  */
+#define FDCAN_CLOCK_DIV2  ((uint32_t)0x00010000U) /*!< Divide kernel clock by 2  */
+#define FDCAN_CLOCK_DIV4  ((uint32_t)0x00020000U) /*!< Divide kernel clock by 4  */
+#define FDCAN_CLOCK_DIV6  ((uint32_t)0x00030000U) /*!< Divide kernel clock by 6  */
+#define FDCAN_CLOCK_DIV8  ((uint32_t)0x00040000U) /*!< Divide kernel clock by 8  */
+#define FDCAN_CLOCK_DIV10 ((uint32_t)0x00050000U) /*!< Divide kernel clock by 10 */
+#define FDCAN_CLOCK_DIV12 ((uint32_t)0x00060000U) /*!< Divide kernel clock by 12 */
+#define FDCAN_CLOCK_DIV14 ((uint32_t)0x00070000U) /*!< Divide kernel clock by 14 */
+#define FDCAN_CLOCK_DIV16 ((uint32_t)0x00080000U) /*!< Divide kernel clock by 16 */
+#define FDCAN_CLOCK_DIV18 ((uint32_t)0x00090000U) /*!< Divide kernel clock by 18 */
+#define FDCAN_CLOCK_DIV20 ((uint32_t)0x000A0000U) /*!< Divide kernel clock by 20 */
+#define FDCAN_CLOCK_DIV22 ((uint32_t)0x000B0000U) /*!< Divide kernel clock by 22 */
+#define FDCAN_CLOCK_DIV24 ((uint32_t)0x000C0000U) /*!< Divide kernel clock by 24 */
+#define FDCAN_CLOCK_DIV26 ((uint32_t)0x000D0000U) /*!< Divide kernel clock by 26 */
+#define FDCAN_CLOCK_DIV28 ((uint32_t)0x000E0000U) /*!< Divide kernel clock by 28 */
+#define FDCAN_CLOCK_DIV30 ((uint32_t)0x000F0000U) /*!< Divide kernel clock by 30 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_calibration_field_length FDCAN Calibration Field Length
+  * @{
+  */
+#define FDCAN_CALIB_FIELD_LENGTH_32 ((uint32_t)0x00000000U)       /*!< Calibration field length is 32 bits */
+#define FDCAN_CALIB_FIELD_LENGTH_64 ((uint32_t)FDCANCCU_CCFG_CFL) /*!< Calibration field length is 64 bits */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_calibration_state FDCAN Calibration State
+  * @{
+  */
+#define FDCAN_CLOCK_NOT_CALIBRATED       ((uint32_t)0x00000000U) /*!< Clock not calibrated       */
+#define FDCAN_CLOCK_BASIC_CALIBRATED     ((uint32_t)0x40000000U) /*!< Clock basic calibrated     */
+#define FDCAN_CLOCK_PRECISION_CALIBRATED ((uint32_t)0x80000000U) /*!< Clock precision calibrated */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_calibration_counter FDCAN Calibration Counter
+  * @{
+  */
+#define FDCAN_CALIB_TIME_QUANTA_COUNTER  ((uint32_t)0x00000000U) /*!< Time Quanta Counter             */
+#define FDCAN_CALIB_CLOCK_PERIOD_COUNTER ((uint32_t)0x00000001U) /*!< Oscillator Clock Period Counter */
+#define FDCAN_CALIB_WATCHDOG_COUNTER     ((uint32_t)0x00000002U) /*!< Calibration Watchdog Counter    */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_data_field_size FDCAN Data Field Size
+  * @{
+  */
+#define FDCAN_DATA_BYTES_8  ((uint32_t)0x00000004U) /*!< 8 bytes data field  */
+#define FDCAN_DATA_BYTES_12 ((uint32_t)0x00000005U) /*!< 12 bytes data field */
+#define FDCAN_DATA_BYTES_16 ((uint32_t)0x00000006U) /*!< 16 bytes data field */
+#define FDCAN_DATA_BYTES_20 ((uint32_t)0x00000007U) /*!< 20 bytes data field */
+#define FDCAN_DATA_BYTES_24 ((uint32_t)0x00000008U) /*!< 24 bytes data field */
+#define FDCAN_DATA_BYTES_32 ((uint32_t)0x0000000AU) /*!< 32 bytes data field */
+#define FDCAN_DATA_BYTES_48 ((uint32_t)0x0000000EU) /*!< 48 bytes data field */
+#define FDCAN_DATA_BYTES_64 ((uint32_t)0x00000012U) /*!< 64 bytes data field */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_txFifoQueue_Mode FDCAN Tx FIFO/Queue Mode
+  * @{
+  */
+#define FDCAN_TX_FIFO_OPERATION  ((uint32_t)0x00000000U)     /*!< FIFO mode  */
+#define FDCAN_TX_QUEUE_OPERATION ((uint32_t)FDCAN_TXBC_TFQM) /*!< Queue mode */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_id_type FDCAN ID Type
+  * @{
+  */
+#define FDCAN_STANDARD_ID ((uint32_t)0x00000000U) /*!< Standard ID element */
+#define FDCAN_EXTENDED_ID ((uint32_t)0x40000000U) /*!< Extended ID element */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_frame_type FDCAN Frame Type
+  * @{
+  */
+#define FDCAN_DATA_FRAME   ((uint32_t)0x00000000U)  /*!< Data frame   */
+#define FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U)  /*!< Remote frame */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_data_length_code FDCAN Data Length Code
+  * @{
+  */
+#define FDCAN_DLC_BYTES_0  ((uint32_t)0x00000000U) /*!< 0 bytes data field  */
+#define FDCAN_DLC_BYTES_1  ((uint32_t)0x00010000U) /*!< 1 bytes data field  */
+#define FDCAN_DLC_BYTES_2  ((uint32_t)0x00020000U) /*!< 2 bytes data field  */
+#define FDCAN_DLC_BYTES_3  ((uint32_t)0x00030000U) /*!< 3 bytes data field  */
+#define FDCAN_DLC_BYTES_4  ((uint32_t)0x00040000U) /*!< 4 bytes data field  */
+#define FDCAN_DLC_BYTES_5  ((uint32_t)0x00050000U) /*!< 5 bytes data field  */
+#define FDCAN_DLC_BYTES_6  ((uint32_t)0x00060000U) /*!< 6 bytes data field  */
+#define FDCAN_DLC_BYTES_7  ((uint32_t)0x00070000U) /*!< 7 bytes data field  */
+#define FDCAN_DLC_BYTES_8  ((uint32_t)0x00080000U) /*!< 8 bytes data field  */
+#define FDCAN_DLC_BYTES_12 ((uint32_t)0x00090000U) /*!< 12 bytes data field */
+#define FDCAN_DLC_BYTES_16 ((uint32_t)0x000A0000U) /*!< 16 bytes data field */
+#define FDCAN_DLC_BYTES_20 ((uint32_t)0x000B0000U) /*!< 20 bytes data field */
+#define FDCAN_DLC_BYTES_24 ((uint32_t)0x000C0000U) /*!< 24 bytes data field */
+#define FDCAN_DLC_BYTES_32 ((uint32_t)0x000D0000U) /*!< 32 bytes data field */
+#define FDCAN_DLC_BYTES_48 ((uint32_t)0x000E0000U) /*!< 48 bytes data field */
+#define FDCAN_DLC_BYTES_64 ((uint32_t)0x000F0000U) /*!< 64 bytes data field */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_error_state_indicator FDCAN Error State Indicator
+  * @{
+  */
+#define FDCAN_ESI_ACTIVE  ((uint32_t)0x00000000U) /*!< Transmitting node is error active  */
+#define FDCAN_ESI_PASSIVE ((uint32_t)0x80000000U) /*!< Transmitting node is error passive */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_bit_rate_switching FDCAN Bit Rate Switching
+  * @{
+  */
+#define FDCAN_BRS_OFF ((uint32_t)0x00000000U) /*!< FDCAN frames transmitted/received without bit rate switching */
+#define FDCAN_BRS_ON  ((uint32_t)0x00100000U) /*!< FDCAN frames transmitted/received with bit rate switching    */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_format FDCAN format
+  * @{
+  */
+#define FDCAN_CLASSIC_CAN ((uint32_t)0x00000000U) /*!< Frame transmitted/received in Classic CAN format */
+#define FDCAN_FD_CAN      ((uint32_t)0x00200000U) /*!< Frame transmitted/received in FDCAN format       */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_EFC FDCAN Event FIFO control
+  * @{
+  */
+#define FDCAN_NO_TX_EVENTS    ((uint32_t)0x00000000U) /*!< Do not store Tx events */
+#define FDCAN_STORE_TX_EVENTS ((uint32_t)0x00800000U) /*!< Store Tx events        */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_filter_type FDCAN Filter Type
+  * @{
+  */
+#define FDCAN_FILTER_RANGE         ((uint32_t)0x00000000U) /*!< Range filter from FilterID1 to FilterID2                        */
+#define FDCAN_FILTER_DUAL          ((uint32_t)0x00000001U) /*!< Dual ID filter for FilterID1 or FilterID2                       */
+#define FDCAN_FILTER_MASK          ((uint32_t)0x00000002U) /*!< Classic filter: FilterID1 = filter, FilterID2 = mask            */
+#define FDCAN_FILTER_RANGE_NO_EIDM ((uint32_t)0x00000003U) /*!< Range filter from FilterID1 to FilterID2, EIDM mask not applied */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_filter_config FDCAN Filter Configuration
+  * @{
+  */
+#define FDCAN_FILTER_DISABLE       ((uint32_t)0x00000000U) /*!< Disable filter element                                    */
+#define FDCAN_FILTER_TO_RXFIFO0    ((uint32_t)0x00000001U) /*!< Store in Rx FIFO 0 if filter matches                      */
+#define FDCAN_FILTER_TO_RXFIFO1    ((uint32_t)0x00000002U) /*!< Store in Rx FIFO 1 if filter matches                      */
+#define FDCAN_FILTER_REJECT        ((uint32_t)0x00000003U) /*!< Reject ID if filter matches                               */
+#define FDCAN_FILTER_HP            ((uint32_t)0x00000004U) /*!< Set high priority if filter matches                       */
+#define FDCAN_FILTER_TO_RXFIFO0_HP ((uint32_t)0x00000005U) /*!< Set high priority and store in FIFO 0 if filter matches   */
+#define FDCAN_FILTER_TO_RXFIFO1_HP ((uint32_t)0x00000006U) /*!< Set high priority and store in FIFO 1 if filter matches   */
+#define FDCAN_FILTER_TO_RXBUFFER   ((uint32_t)0x00000007U) /*!< Store into Rx Buffer, configuration of FilterType ignored */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Tx_location FDCAN Tx Location
+  * @{
+  */
+#define FDCAN_TX_BUFFER0  ((uint32_t)0x00000001U) /*!< Add message to Tx Buffer 0  */
+#define FDCAN_TX_BUFFER1  ((uint32_t)0x00000002U) /*!< Add message to Tx Buffer 1  */
+#define FDCAN_TX_BUFFER2  ((uint32_t)0x00000004U) /*!< Add message to Tx Buffer 2  */
+#define FDCAN_TX_BUFFER3  ((uint32_t)0x00000008U) /*!< Add message to Tx Buffer 3  */
+#define FDCAN_TX_BUFFER4  ((uint32_t)0x00000010U) /*!< Add message to Tx Buffer 4  */
+#define FDCAN_TX_BUFFER5  ((uint32_t)0x00000020U) /*!< Add message to Tx Buffer 5  */
+#define FDCAN_TX_BUFFER6  ((uint32_t)0x00000040U) /*!< Add message to Tx Buffer 6  */
+#define FDCAN_TX_BUFFER7  ((uint32_t)0x00000080U) /*!< Add message to Tx Buffer 7  */
+#define FDCAN_TX_BUFFER8  ((uint32_t)0x00000100U) /*!< Add message to Tx Buffer 8  */
+#define FDCAN_TX_BUFFER9  ((uint32_t)0x00000200U) /*!< Add message to Tx Buffer 9  */
+#define FDCAN_TX_BUFFER10 ((uint32_t)0x00000400U) /*!< Add message to Tx Buffer 10 */
+#define FDCAN_TX_BUFFER11 ((uint32_t)0x00000800U) /*!< Add message to Tx Buffer 11 */
+#define FDCAN_TX_BUFFER12 ((uint32_t)0x00001000U) /*!< Add message to Tx Buffer 12 */
+#define FDCAN_TX_BUFFER13 ((uint32_t)0x00002000U) /*!< Add message to Tx Buffer 13 */
+#define FDCAN_TX_BUFFER14 ((uint32_t)0x00004000U) /*!< Add message to Tx Buffer 14 */
+#define FDCAN_TX_BUFFER15 ((uint32_t)0x00008000U) /*!< Add message to Tx Buffer 15 */
+#define FDCAN_TX_BUFFER16 ((uint32_t)0x00010000U) /*!< Add message to Tx Buffer 16 */
+#define FDCAN_TX_BUFFER17 ((uint32_t)0x00020000U) /*!< Add message to Tx Buffer 17 */
+#define FDCAN_TX_BUFFER18 ((uint32_t)0x00040000U) /*!< Add message to Tx Buffer 18 */
+#define FDCAN_TX_BUFFER19 ((uint32_t)0x00080000U) /*!< Add message to Tx Buffer 19 */
+#define FDCAN_TX_BUFFER20 ((uint32_t)0x00100000U) /*!< Add message to Tx Buffer 20 */
+#define FDCAN_TX_BUFFER21 ((uint32_t)0x00200000U) /*!< Add message to Tx Buffer 21 */
+#define FDCAN_TX_BUFFER22 ((uint32_t)0x00400000U) /*!< Add message to Tx Buffer 22 */
+#define FDCAN_TX_BUFFER23 ((uint32_t)0x00800000U) /*!< Add message to Tx Buffer 23 */
+#define FDCAN_TX_BUFFER24 ((uint32_t)0x01000000U) /*!< Add message to Tx Buffer 24 */
+#define FDCAN_TX_BUFFER25 ((uint32_t)0x02000000U) /*!< Add message to Tx Buffer 25 */
+#define FDCAN_TX_BUFFER26 ((uint32_t)0x04000000U) /*!< Add message to Tx Buffer 26 */
+#define FDCAN_TX_BUFFER27 ((uint32_t)0x08000000U) /*!< Add message to Tx Buffer 27 */
+#define FDCAN_TX_BUFFER28 ((uint32_t)0x10000000U) /*!< Add message to Tx Buffer 28 */
+#define FDCAN_TX_BUFFER29 ((uint32_t)0x20000000U) /*!< Add message to Tx Buffer 29 */
+#define FDCAN_TX_BUFFER30 ((uint32_t)0x40000000U) /*!< Add message to Tx Buffer 30 */
+#define FDCAN_TX_BUFFER31 ((uint32_t)0x80000000U) /*!< Add message to Tx Buffer 31 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Rx_location FDCAN Rx Location
+  * @{
+  */
+#define FDCAN_RX_FIFO0    ((uint32_t)0x00000040U) /*!< Get received message from Rx FIFO 0    */
+#define FDCAN_RX_FIFO1    ((uint32_t)0x00000041U) /*!< Get received message from Rx FIFO 1    */
+#define FDCAN_RX_BUFFER0  ((uint32_t)0x00000000U) /*!< Get received message from Rx Buffer 0  */
+#define FDCAN_RX_BUFFER1  ((uint32_t)0x00000001U) /*!< Get received message from Rx Buffer 1  */
+#define FDCAN_RX_BUFFER2  ((uint32_t)0x00000002U) /*!< Get received message from Rx Buffer 2  */
+#define FDCAN_RX_BUFFER3  ((uint32_t)0x00000003U) /*!< Get received message from Rx Buffer 3  */
+#define FDCAN_RX_BUFFER4  ((uint32_t)0x00000004U) /*!< Get received message from Rx Buffer 4  */
+#define FDCAN_RX_BUFFER5  ((uint32_t)0x00000005U) /*!< Get received message from Rx Buffer 5  */
+#define FDCAN_RX_BUFFER6  ((uint32_t)0x00000006U) /*!< Get received message from Rx Buffer 6  */
+#define FDCAN_RX_BUFFER7  ((uint32_t)0x00000007U) /*!< Get received message from Rx Buffer 7  */
+#define FDCAN_RX_BUFFER8  ((uint32_t)0x00000008U) /*!< Get received message from Rx Buffer 8  */
+#define FDCAN_RX_BUFFER9  ((uint32_t)0x00000009U) /*!< Get received message from Rx Buffer 9  */
+#define FDCAN_RX_BUFFER10 ((uint32_t)0x0000000AU) /*!< Get received message from Rx Buffer 10 */
+#define FDCAN_RX_BUFFER11 ((uint32_t)0x0000000BU) /*!< Get received message from Rx Buffer 11 */
+#define FDCAN_RX_BUFFER12 ((uint32_t)0x0000000CU) /*!< Get received message from Rx Buffer 12 */
+#define FDCAN_RX_BUFFER13 ((uint32_t)0x0000000DU) /*!< Get received message from Rx Buffer 13 */
+#define FDCAN_RX_BUFFER14 ((uint32_t)0x0000000EU) /*!< Get received message from Rx Buffer 14 */
+#define FDCAN_RX_BUFFER15 ((uint32_t)0x0000000FU) /*!< Get received message from Rx Buffer 15 */
+#define FDCAN_RX_BUFFER16 ((uint32_t)0x00000010U) /*!< Get received message from Rx Buffer 16 */
+#define FDCAN_RX_BUFFER17 ((uint32_t)0x00000011U) /*!< Get received message from Rx Buffer 17 */
+#define FDCAN_RX_BUFFER18 ((uint32_t)0x00000012U) /*!< Get received message from Rx Buffer 18 */
+#define FDCAN_RX_BUFFER19 ((uint32_t)0x00000013U) /*!< Get received message from Rx Buffer 19 */
+#define FDCAN_RX_BUFFER20 ((uint32_t)0x00000014U) /*!< Get received message from Rx Buffer 20 */
+#define FDCAN_RX_BUFFER21 ((uint32_t)0x00000015U) /*!< Get received message from Rx Buffer 21 */
+#define FDCAN_RX_BUFFER22 ((uint32_t)0x00000016U) /*!< Get received message from Rx Buffer 22 */
+#define FDCAN_RX_BUFFER23 ((uint32_t)0x00000017U) /*!< Get received message from Rx Buffer 23 */
+#define FDCAN_RX_BUFFER24 ((uint32_t)0x00000018U) /*!< Get received message from Rx Buffer 24 */
+#define FDCAN_RX_BUFFER25 ((uint32_t)0x00000019U) /*!< Get received message from Rx Buffer 25 */
+#define FDCAN_RX_BUFFER26 ((uint32_t)0x0000001AU) /*!< Get received message from Rx Buffer 26 */
+#define FDCAN_RX_BUFFER27 ((uint32_t)0x0000001BU) /*!< Get received message from Rx Buffer 27 */
+#define FDCAN_RX_BUFFER28 ((uint32_t)0x0000001CU) /*!< Get received message from Rx Buffer 28 */
+#define FDCAN_RX_BUFFER29 ((uint32_t)0x0000001DU) /*!< Get received message from Rx Buffer 29 */
+#define FDCAN_RX_BUFFER30 ((uint32_t)0x0000001EU) /*!< Get received message from Rx Buffer 30 */
+#define FDCAN_RX_BUFFER31 ((uint32_t)0x0000001FU) /*!< Get received message from Rx Buffer 31 */
+#define FDCAN_RX_BUFFER32 ((uint32_t)0x00000020U) /*!< Get received message from Rx Buffer 32 */
+#define FDCAN_RX_BUFFER33 ((uint32_t)0x00000021U) /*!< Get received message from Rx Buffer 33 */
+#define FDCAN_RX_BUFFER34 ((uint32_t)0x00000022U) /*!< Get received message from Rx Buffer 34 */
+#define FDCAN_RX_BUFFER35 ((uint32_t)0x00000023U) /*!< Get received message from Rx Buffer 35 */
+#define FDCAN_RX_BUFFER36 ((uint32_t)0x00000024U) /*!< Get received message from Rx Buffer 36 */
+#define FDCAN_RX_BUFFER37 ((uint32_t)0x00000025U) /*!< Get received message from Rx Buffer 37 */
+#define FDCAN_RX_BUFFER38 ((uint32_t)0x00000026U) /*!< Get received message from Rx Buffer 38 */
+#define FDCAN_RX_BUFFER39 ((uint32_t)0x00000027U) /*!< Get received message from Rx Buffer 39 */
+#define FDCAN_RX_BUFFER40 ((uint32_t)0x00000028U) /*!< Get received message from Rx Buffer 40 */
+#define FDCAN_RX_BUFFER41 ((uint32_t)0x00000029U) /*!< Get received message from Rx Buffer 41 */
+#define FDCAN_RX_BUFFER42 ((uint32_t)0x0000002AU) /*!< Get received message from Rx Buffer 42 */
+#define FDCAN_RX_BUFFER43 ((uint32_t)0x0000002BU) /*!< Get received message from Rx Buffer 43 */
+#define FDCAN_RX_BUFFER44 ((uint32_t)0x0000002CU) /*!< Get received message from Rx Buffer 44 */
+#define FDCAN_RX_BUFFER45 ((uint32_t)0x0000002DU) /*!< Get received message from Rx Buffer 45 */
+#define FDCAN_RX_BUFFER46 ((uint32_t)0x0000002EU) /*!< Get received message from Rx Buffer 46 */
+#define FDCAN_RX_BUFFER47 ((uint32_t)0x0000002FU) /*!< Get received message from Rx Buffer 47 */
+#define FDCAN_RX_BUFFER48 ((uint32_t)0x00000030U) /*!< Get received message from Rx Buffer 48 */
+#define FDCAN_RX_BUFFER49 ((uint32_t)0x00000031U) /*!< Get received message from Rx Buffer 49 */
+#define FDCAN_RX_BUFFER50 ((uint32_t)0x00000032U) /*!< Get received message from Rx Buffer 50 */
+#define FDCAN_RX_BUFFER51 ((uint32_t)0x00000033U) /*!< Get received message from Rx Buffer 51 */
+#define FDCAN_RX_BUFFER52 ((uint32_t)0x00000034U) /*!< Get received message from Rx Buffer 52 */
+#define FDCAN_RX_BUFFER53 ((uint32_t)0x00000035U) /*!< Get received message from Rx Buffer 53 */
+#define FDCAN_RX_BUFFER54 ((uint32_t)0x00000036U) /*!< Get received message from Rx Buffer 54 */
+#define FDCAN_RX_BUFFER55 ((uint32_t)0x00000037U) /*!< Get received message from Rx Buffer 55 */
+#define FDCAN_RX_BUFFER56 ((uint32_t)0x00000038U) /*!< Get received message from Rx Buffer 56 */
+#define FDCAN_RX_BUFFER57 ((uint32_t)0x00000039U) /*!< Get received message from Rx Buffer 57 */
+#define FDCAN_RX_BUFFER58 ((uint32_t)0x0000003AU) /*!< Get received message from Rx Buffer 58 */
+#define FDCAN_RX_BUFFER59 ((uint32_t)0x0000003BU) /*!< Get received message from Rx Buffer 59 */
+#define FDCAN_RX_BUFFER60 ((uint32_t)0x0000003CU) /*!< Get received message from Rx Buffer 60 */
+#define FDCAN_RX_BUFFER61 ((uint32_t)0x0000003DU) /*!< Get received message from Rx Buffer 61 */
+#define FDCAN_RX_BUFFER62 ((uint32_t)0x0000003EU) /*!< Get received message from Rx Buffer 62 */
+#define FDCAN_RX_BUFFER63 ((uint32_t)0x0000003FU) /*!< Get received message from Rx Buffer 63 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_event_type FDCAN Event Type
+  * @{
+  */
+#define FDCAN_TX_EVENT             ((uint32_t)0x00400000U) /*!< Tx event                              */
+#define FDCAN_TX_IN_SPITE_OF_ABORT ((uint32_t)0x00800000U) /*!< Transmission in spite of cancellation */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_hp_msg_storage FDCAN High Priority Message Storage
+  * @{
+  */
+#define FDCAN_HP_STORAGE_NO_FIFO  ((uint32_t)0x00000000U) /*!< No FIFO selected         */
+#define FDCAN_HP_STORAGE_MSG_LOST ((uint32_t)0x00000040U) /*!< FIFO message lost        */
+#define FDCAN_HP_STORAGE_RXFIFO0  ((uint32_t)0x00000080U) /*!< Message stored in FIFO 0 */
+#define FDCAN_HP_STORAGE_RXFIFO1  ((uint32_t)0x000000C0U) /*!< Message stored in FIFO 1 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_protocol_error_code FDCAN protocol error code
+  * @{
+  */
+#define FDCAN_PROTOCOL_ERROR_NONE      ((uint32_t)0x00000000U) /*!< No error occurred         */
+#define FDCAN_PROTOCOL_ERROR_STUFF     ((uint32_t)0x00000001U) /*!< Stuff error               */
+#define FDCAN_PROTOCOL_ERROR_FORM      ((uint32_t)0x00000002U) /*!< Form error                */
+#define FDCAN_PROTOCOL_ERROR_ACK       ((uint32_t)0x00000003U) /*!< Acknowledge error         */
+#define FDCAN_PROTOCOL_ERROR_BIT1      ((uint32_t)0x00000004U) /*!< Bit 1 (recessive) error   */
+#define FDCAN_PROTOCOL_ERROR_BIT0      ((uint32_t)0x00000005U) /*!< Bit 0 (dominant) error    */
+#define FDCAN_PROTOCOL_ERROR_CRC       ((uint32_t)0x00000006U) /*!< CRC check sum error       */
+#define FDCAN_PROTOCOL_ERROR_NO_CHANGE ((uint32_t)0x00000007U) /*!< No change since last read */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_communication_state FDCAN communication state
+  * @{
+  */
+#define FDCAN_COM_STATE_SYNC ((uint32_t)0x00000000U) /*!< Node is synchronizing on CAN communication */
+#define FDCAN_COM_STATE_IDLE ((uint32_t)0x00000008U) /*!< Node is neither receiver nor transmitter   */
+#define FDCAN_COM_STATE_RX   ((uint32_t)0x00000010U) /*!< Node is operating as receiver              */
+#define FDCAN_COM_STATE_TX   ((uint32_t)0x00000018U) /*!< Node is operating as transmitter           */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_FIFO_watermark FDCAN FIFO watermark
+  * @{
+  */
+#define FDCAN_CFG_TX_EVENT_FIFO ((uint32_t)0x00000000U) /*!< Tx event FIFO */
+#define FDCAN_CFG_RX_FIFO0      ((uint32_t)0x00000001U) /*!< Rx FIFO0      */
+#define FDCAN_CFG_RX_FIFO1      ((uint32_t)0x00000002U) /*!< Rx FIFO1      */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Rx_FIFO_operation_mode FDCAN FIFO operation mode
+  * @{
+  */
+#define FDCAN_RX_FIFO_BLOCKING  ((uint32_t)0x00000000U) /*!< Rx FIFO blocking mode  */
+#define FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x80000000U) /*!< Rx FIFO overwrite mode */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Non_Matching_Frames FDCAN non-matching frames
+  * @{
+  */
+#define FDCAN_ACCEPT_IN_RX_FIFO0 ((uint32_t)0x00000000U) /*!< Accept in Rx FIFO 0 */
+#define FDCAN_ACCEPT_IN_RX_FIFO1 ((uint32_t)0x00000001U) /*!< Accept in Rx FIFO 1 */
+#define FDCAN_REJECT             ((uint32_t)0x00000002U) /*!< Reject              */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Reject_Remote_Frames FDCAN reject remote frames
+  * @{
+  */
+#define FDCAN_FILTER_REMOTE ((uint32_t)0x00000000U) /*!< Filter remote frames */
+#define FDCAN_REJECT_REMOTE ((uint32_t)0x00000001U) /*!< Reject all remote frames */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Interrupt_Line FDCAN interrupt line
+  * @{
+  */
+#define FDCAN_INTERRUPT_LINE0 ((uint32_t)0x00000001U) /*!< Interrupt Line 0 */
+#define FDCAN_INTERRUPT_LINE1 ((uint32_t)0x00000002U) /*!< Interrupt Line 1 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Timestamp FDCAN timestamp
+  * @{
+  */
+#define FDCAN_TIMESTAMP_INTERNAL ((uint32_t)0x00000001U) /*!< Timestamp counter value incremented according to TCP */
+#define FDCAN_TIMESTAMP_EXTERNAL ((uint32_t)0x00000002U) /*!< External timestamp counter value used                */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Timestamp_Prescaler FDCAN timestamp prescaler
+  * @{
+  */
+#define FDCAN_TIMESTAMP_PRESC_1  ((uint32_t)0x00000000U) /*!< Timestamp counter time unit in equal to CAN bit time                 */
+#define FDCAN_TIMESTAMP_PRESC_2  ((uint32_t)0x00010000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 2  */
+#define FDCAN_TIMESTAMP_PRESC_3  ((uint32_t)0x00020000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 3  */
+#define FDCAN_TIMESTAMP_PRESC_4  ((uint32_t)0x00030000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 4  */
+#define FDCAN_TIMESTAMP_PRESC_5  ((uint32_t)0x00040000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 5  */
+#define FDCAN_TIMESTAMP_PRESC_6  ((uint32_t)0x00050000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 6  */
+#define FDCAN_TIMESTAMP_PRESC_7  ((uint32_t)0x00060000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 7  */
+#define FDCAN_TIMESTAMP_PRESC_8  ((uint32_t)0x00070000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 8  */
+#define FDCAN_TIMESTAMP_PRESC_9  ((uint32_t)0x00080000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 9  */
+#define FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 10 */
+#define FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 11 */
+#define FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 12 */
+#define FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 13 */
+#define FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 14 */
+#define FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 15 */
+#define FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 16 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Timeout_Operation FDCAN timeout operation
+  * @{
+  */
+#define FDCAN_TIMEOUT_CONTINUOUS    ((uint32_t)0x00000000U) /*!< Timeout continuous operation        */
+#define FDCAN_TIMEOUT_TX_EVENT_FIFO ((uint32_t)0x00000002U) /*!< Timeout controlled by Tx Event FIFO */
+#define FDCAN_TIMEOUT_RX_FIFO0      ((uint32_t)0x00000004U) /*!< Timeout controlled by Rx FIFO 0     */
+#define FDCAN_TIMEOUT_RX_FIFO1      ((uint32_t)0x00000006U) /*!< Timeout controlled by Rx FIFO 1     */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_Reference_Message_Payload FDCAN TT reference message payload
+  * @{
+  */
+#define FDCAN_TT_REF_MESSAGE_NO_PAYLOAD  ((uint32_t)0x00000000U)      /*!< Reference message has no additional payload  */
+#define FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD ((uint32_t)FDCAN_TTRMC_RMPS) /*!< Additional payload is taken from Tx Buffer 0 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_Repeat_Factor FDCAN TT repeat factor
+  * @{
+  */
+#define FDCAN_TT_REPEAT_EVERY_CYCLE      ((uint32_t)0x00000000U) /*!< Trigger valid for all cycles   */
+#define FDCAN_TT_REPEAT_EVERY_2ND_CYCLE  ((uint32_t)0x00000002U) /*!< Trigger valid every 2dn cycle  */
+#define FDCAN_TT_REPEAT_EVERY_4TH_CYCLE  ((uint32_t)0x00000004U) /*!< Trigger valid every 4th cycle  */
+#define FDCAN_TT_REPEAT_EVERY_8TH_CYCLE  ((uint32_t)0x00000008U) /*!< Trigger valid every 8th cycle  */
+#define FDCAN_TT_REPEAT_EVERY_16TH_CYCLE ((uint32_t)0x00000010U) /*!< Trigger valid every 16th cycle */
+#define FDCAN_TT_REPEAT_EVERY_32ND_CYCLE ((uint32_t)0x00000020U) /*!< Trigger valid every 32nd cycle */
+#define FDCAN_TT_REPEAT_EVERY_64TH_CYCLE ((uint32_t)0x00000040U) /*!< Trigger valid every 64th cycle */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_Trigger_Type FDCAN TT trigger type
+  * @{
+  */
+#define FDCAN_TT_TX_REF_TRIGGER         ((uint32_t)0x00000000U) /*!< Transmit reference message in strictly time-triggered operation                                                     */
+#define FDCAN_TT_TX_REF_TRIGGER_GAP     ((uint32_t)0x00000001U) /*!< Transmit reference message in external event-synchronized time-triggered operation                                  */
+#define FDCAN_TT_TX_TRIGGER_SINGLE      ((uint32_t)0x00000002U) /*!< Start a single transmission in an exclusive time window                                                             */
+#define FDCAN_TT_TX_TRIGGER_CONTINUOUS  ((uint32_t)0x00000003U) /*!< Start a continuous transmission in an exclusive time window                                                         */
+#define FDCAN_TT_TX_TRIGGER_ARBITRATION ((uint32_t)0x00000004U) /*!< Start a transmission in an arbitration time window                                                                  */
+#define FDCAN_TT_TX_TRIGGER_MERGED      ((uint32_t)0x00000005U) /*!< Start a merged arbitration window                                                                                   */
+#define FDCAN_TT_WATCH_TRIGGER          ((uint32_t)0x00000006U) /*!< Check for missing reference messages in strictly time-triggered operation                                           */
+#define FDCAN_TT_WATCH_TRIGGER_GAP      ((uint32_t)0x00000007U) /*!< Check for missing reference messages in external event-synchronized time-triggered operation                        */
+#define FDCAN_TT_RX_TRIGGER             ((uint32_t)0x00000008U) /*!< Check for the reception of periodic messages in exclusive time windows                                              */
+#define FDCAN_TT_TIME_BASE_TRIGGER      ((uint32_t)0x00000009U) /*!< Generate internal/external events depending on TmEventInt/TmEventExt configuration                                  */
+#define FDCAN_TT_END_OF_LIST            ((uint32_t)0x0000000AU) /*!< Illegal trigger, to be assigned to the unused triggers after a FDCAN_TT_WATCH_TRIGGER or FDCAN_TT_WATCH_TRIGGER_GAP */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_Time_Mark_Event_Internal FDCAN TT time mark event internal
+  * @{
+  */
+#define FDCAN_TT_TM_NO_INTERNAL_EVENT  ((uint32_t)0x00000000U) /*!< No action                                               */
+#define FDCAN_TT_TM_GEN_INTERNAL_EVENT ((uint32_t)0x00000020U) /*!< Internal event is generated when trigger becomes active */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_Time_Mark_Event_External FDCAN TT time mark event external
+  * @{
+  */
+#define FDCAN_TT_TM_NO_EXTERNAL_EVENT  ((uint32_t)0x00000000U) /*!< No action                                                       */
+#define FDCAN_TT_TM_GEN_EXTERNAL_EVENT ((uint32_t)0x00000010U) /*!< External event (pulse) is generated when trigger becomes active */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_operation_mode FDCAN Operation Mode
+  * @{
+  */
+#define FDCAN_TT_COMMUNICATION_LEVEL1    ((uint32_t)0x00000001U) /*!< Time triggered communication, level 1 */
+#define FDCAN_TT_COMMUNICATION_LEVEL2    ((uint32_t)0x00000002U) /*!< Time triggered communication, level 2 */
+#define FDCAN_TT_COMMUNICATION_LEVEL0    ((uint32_t)0x00000003U) /*!< Time triggered communication, level 0 */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_operation FDCAN TT Operation
+  * @{
+  */
+#define FDCAN_STRICTLY_TT_OPERATION     ((uint32_t)0x00000000U)     /*!< Strictly time-triggered operation                    */
+#define FDCAN_EXT_EVT_SYNC_TT_OPERATION ((uint32_t)FDCAN_TTOCF_GEN) /*!< External event-synchronized time-triggered operation */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_time_master FDCAN TT Time Master
+  * @{
+  */
+#define FDCAN_TT_SLAVE            ((uint32_t)0x00000000U)    /*!< Time slave            */
+#define FDCAN_TT_POTENTIAL_MASTER ((uint32_t)FDCAN_TTOCF_TM) /*!< Potential time master */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_external_clk_sync FDCAN TT External Clock Synchronization
+  * @{
+  */
+#define FDCAN_TT_EXT_CLK_SYNC_DISABLE ((uint32_t)0x00000000U)      /*!< External clock synchronization in Level 0,2 disabled */
+#define FDCAN_TT_EXT_CLK_SYNC_ENABLE  ((uint32_t)FDCAN_TTOCF_EECS) /*!< External clock synchronization in Level 0,2 enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_global_time_filtering FDCAN TT Global Time Filtering
+  * @{
+  */
+#define FDCAN_TT_GLOB_TIME_FILT_DISABLE ((uint32_t)0x00000000U)      /*!< Global time filtering in Level 0,2 disabled */
+#define FDCAN_TT_GLOB_TIME_FILT_ENABLE  ((uint32_t)FDCAN_TTOCF_EGTF) /*!< Global time filtering in Level 0,2 enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_auto_clk_calibration FDCAN TT Automatic Clock Calibration
+  * @{
+  */
+#define FDCAN_TT_AUTO_CLK_CALIB_DISABLE ((uint32_t)0x00000000U)     /*!< Automatic clock calibration in Level 0,2 disabled */
+#define FDCAN_TT_AUTO_CLK_CALIB_ENABLE  ((uint32_t)FDCAN_TTOCF_ECC) /*!< Automatic clock calibration in Level 0,2 enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_event_trig_polarity FDCAN TT Event Trigger Polarity
+  * @{
+  */
+#define FDCAN_TT_EVT_TRIG_POL_RISING  ((uint32_t)0x00000000U)      /*!< Rising edge trigger  */
+#define FDCAN_TT_EVT_TRIG_POL_FALLING ((uint32_t)FDCAN_TTOCF_EVTP) /*!< Falling edge trigger */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_basic_cycle_number FDCAN TT Basic Cycle Number
+  * @{
+  */
+#define FDCAN_TT_CYCLES_PER_MATRIX_1  ((uint32_t)0x00000000U) /*!< 1 Basic Cycle per Matrix   */
+#define FDCAN_TT_CYCLES_PER_MATRIX_2  ((uint32_t)0x00000001U) /*!< 2 Basic Cycles per Matrix  */
+#define FDCAN_TT_CYCLES_PER_MATRIX_4  ((uint32_t)0x00000003U) /*!< 4 Basic Cycles per Matrix  */
+#define FDCAN_TT_CYCLES_PER_MATRIX_8  ((uint32_t)0x00000007U) /*!< 8 Basic Cycles per Matrix  */
+#define FDCAN_TT_CYCLES_PER_MATRIX_16 ((uint32_t)0x0000000FU) /*!< 16 Basic Cycles per Matrix */
+#define FDCAN_TT_CYCLES_PER_MATRIX_32 ((uint32_t)0x0000001FU) /*!< 32 Basic Cycles per Matrix */
+#define FDCAN_TT_CYCLES_PER_MATRIX_64 ((uint32_t)0x0000003FU) /*!< 64 Basic Cycles per Matrix */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_cycle_start_sync FDCAN TT Cycle Start Sync
+  * @{
+  */
+#define FDCAN_TT_NO_SYNC_PULSE          ((uint32_t)0x00000000U) /*!< No sync pulse                      */
+#define FDCAN_TT_SYNC_BASIC_CYCLE_START ((uint32_t)0x00000040U) /*!< Sync pulse at start of basic cycle */
+#define FDCAN_TT_SYNC_MATRIX_START      ((uint32_t)0x00000080U) /*!< Sync pulse at start of matrix      */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_stop_watch_trig_selection FDCAN TT Stop Watch Trigger Selection
+  * @{
+  */
+#define FDCAN_TT_STOP_WATCH_TRIGGER_0 ((uint32_t)0x00000000U) /*!< TIM2 selected as stop watch trigger  */
+#define FDCAN_TT_STOP_WATCH_TRIGGER_1 ((uint32_t)0x00000001U) /*!< TIM3 selected as stop watch trigger  */
+#define FDCAN_TT_STOP_WATCH_TRIGGER_2 ((uint32_t)0x00000002U) /*!< ETH selected as stop watch trigger   */
+#define FDCAN_TT_STOP_WATCH_TRIGGER_3 ((uint32_t)0x00000003U) /*!< HRTIM selected as stop watch trigger */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_event_trig_selection FDCAN TT Event Trigger Selection
+  * @{
+  */
+#define FDCAN_TT_EVENT_TRIGGER_0 ((uint32_t)0x00000000U) /*!< TIM2 selected as event trigger  */
+#define FDCAN_TT_EVENT_TRIGGER_1 ((uint32_t)0x00000010U) /*!< TIM3 selected as event trigger  */
+#define FDCAN_TT_EVENT_TRIGGER_2 ((uint32_t)0x00000020U) /*!< ETH selected as event trigger   */
+#define FDCAN_TT_EVENT_TRIGGER_3 ((uint32_t)0x00000030U) /*!< HRTIM selected as event trigger */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_stop_watch_source FDCAN TT Stop Watch Source
+  * @{
+  */
+#define FDCAN_TT_STOP_WATCH_DISABLED    ((uint32_t)0x00000000U) /*!< Stop Watch disabled                                                        */
+#define FDCAN_TT_STOP_WATCH_CYCLE_TIME  ((uint32_t)0x00000008U) /*!< Actual value of cycle time is copied to Capture Time register (TTCPT.SWV)  */
+#define FDCAN_TT_STOP_WATCH_LOCAL_TIME  ((uint32_t)0x00000010U) /*!< Actual value of local time is copied to Capture Time register (TTCPT.SWV)  */
+#define FDCAN_TT_STOP_WATCH_GLOBAL_TIME ((uint32_t)0x00000018U) /*!< Actual value of global time is copied to Capture Time register (TTCPT.SWV) */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_stop_watch_polarity FDCAN TT Stop Watch Polarity
+  * @{
+  */
+#define FDCAN_TT_STOP_WATCH_RISING  ((uint32_t)0x00000000U) /*!< Selected stop watch source is captured at rising edge of fdcan1_swt  */
+#define FDCAN_TT_STOP_WATCH_FALLING ((uint32_t)0x00000004U) /*!< Selected stop watch source is captured at falling edge of fdcan1_swt */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_time_mark_source FDCAN TT Time Mark Source
+  * @{
+  */
+#define FDCAN_TT_REG_TIMEMARK_DIABLED  ((uint32_t)0x00000000U) /*!< No Register Time Mark Interrupt generated               */
+#define FDCAN_TT_REG_TIMEMARK_CYC_TIME ((uint32_t)0x00000040U) /*!< Register Time Mark Interrupt if Time Mark = cycle time  */
+#define FDCAN_TT_REG_TIMEMARK_LOC_TIME ((uint32_t)0x00000080U) /*!< Register Time Mark Interrupt if Time Mark = local time  */
+#define FDCAN_TT_REG_TIMEMARK_GLO_TIME ((uint32_t)0x000000C0U) /*!< Register Time Mark Interrupt if Time Mark = global time */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_error_level FDCAN TT Error Level
+  * @{
+  */
+#define FDCAN_TT_NO_ERROR     ((uint32_t)0x00000000U) /*!< Severity 0 - No Error     */
+#define FDCAN_TT_WARNING      ((uint32_t)0x00000001U) /*!< Severity 1 - Warning      */
+#define FDCAN_TT_ERROR        ((uint32_t)0x00000002U) /*!< Severity 2 - Error        */
+#define FDCAN_TT_SEVERE_ERROR ((uint32_t)0x00000003U) /*!< Severity 3 - Severe Error */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_master_state FDCAN TT Master State
+  * @{
+  */
+#define FDCAN_TT_MASTER_OFF          ((uint32_t)0x00000000U) /*!< Master_Off, no master properties relevant */
+#define FDCAN_TT_TIME_SLAVE          ((uint32_t)0x00000004U) /*!< Operating as Time Slave                   */
+#define FDCAN_TT_BACKUP_TIME_MASTER  ((uint32_t)0x00000008U) /*!< Operating as Backup Time Master           */
+#define FDCAN_TT_CURRENT_TIME_MASTER ((uint32_t)0x0000000CU) /*!< Operating as current Time Master          */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TT_sync_state FDCAN TT Synchronization State
+  * @{
+  */
+#define FDCAN_TT_OUT_OF_SYNC   ((uint32_t)0x00000000U) /*!< Out of Synchronization         */
+#define FDCAN_TT_SYNCHRONIZING ((uint32_t)0x00000010U) /*!< Synchronizing to communication */
+#define FDCAN_TT_IN_GAP        ((uint32_t)0x00000020U) /*!< Schedule suspended by Gap      */
+#define FDCAN_TT_IN_SCHEDULE   ((uint32_t)0x00000030U) /*!< Synchronized to schedule       */
+/**
+  * @}
+  */
+
+/** @defgroup Interrupt_Masks Interrupt masks
+  * @{
+  */
+#define FDCAN_IR_MASK ((uint32_t)0x3FCFFFFFU) /*!< FDCAN interrupts mask */
+#define CCU_IR_MASK   ((uint32_t)0xC0000000U) /*!< CCU interrupts mask   */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_flags FDCAN Flags
+  * @{
+  */
+#define FDCAN_FLAG_TX_COMPLETE             FDCAN_IR_TC             /*!< Transmission Completed                                */
+#define FDCAN_FLAG_TX_ABORT_COMPLETE       FDCAN_IR_TCF            /*!< Transmission Cancellation Finished                    */
+#define FDCAN_FLAG_TX_FIFO_EMPTY           FDCAN_IR_TFE            /*!< Tx FIFO Empty                                         */
+#define FDCAN_FLAG_RX_HIGH_PRIORITY_MSG    FDCAN_IR_HPM            /*!< High priority message received                        */
+#define FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE   FDCAN_IR_DRX            /*!< At least one received message stored into a Rx Buffer */
+#define FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST    FDCAN_IR_TEFL           /*!< Tx Event FIFO element lost                            */
+#define FDCAN_FLAG_TX_EVT_FIFO_FULL        FDCAN_IR_TEFF           /*!< Tx Event FIFO full                                    */
+#define FDCAN_FLAG_TX_EVT_FIFO_WATERMARK   FDCAN_IR_TEFW           /*!< Tx Event FIFO fill level reached watermark            */
+#define FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA    FDCAN_IR_TEFN           /*!< Tx Handler wrote Tx Event FIFO element                */
+#define FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST   FDCAN_IR_RF0L           /*!< Rx FIFO 0 message lost                                */
+#define FDCAN_FLAG_RX_FIFO0_FULL           FDCAN_IR_RF0F           /*!< Rx FIFO 0 full                                        */
+#define FDCAN_FLAG_RX_FIFO0_WATERMARK      FDCAN_IR_RF0W           /*!< Rx FIFO 0 fill level reached watermark                */
+#define FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE    FDCAN_IR_RF0N           /*!< New message written to Rx FIFO 0                      */
+#define FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST   FDCAN_IR_RF1L           /*!< Rx FIFO 1 message lost                                */
+#define FDCAN_FLAG_RX_FIFO1_FULL           FDCAN_IR_RF1F           /*!< Rx FIFO 1 full                                        */
+#define FDCAN_FLAG_RX_FIFO1_WATERMARK      FDCAN_IR_RF1W           /*!< Rx FIFO 1 fill level reached watermark                */
+#define FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE    FDCAN_IR_RF1N           /*!< New message written to Rx FIFO 1                      */
+#define FDCAN_FLAG_RAM_ACCESS_FAILURE      FDCAN_IR_MRAF           /*!< Message RAM access failure occurred                   */
+#define FDCAN_FLAG_ERROR_LOGGING_OVERFLOW  FDCAN_IR_ELO            /*!< Overflow of FDCAN Error Logging Counter occurred      */
+#define FDCAN_FLAG_ERROR_PASSIVE           FDCAN_IR_EP             /*!< Error_Passive status changed                          */
+#define FDCAN_FLAG_ERROR_WARNING           FDCAN_IR_EW             /*!< Error_Warning status changed                          */
+#define FDCAN_FLAG_BUS_OFF                 FDCAN_IR_BO             /*!< Bus_Off status changed                                */
+#define FDCAN_FLAG_RAM_WATCHDOG            FDCAN_IR_WDI            /*!< Message RAM Watchdog event due to missing READY       */
+#define FDCAN_FLAG_ARB_PROTOCOL_ERROR      FDCAN_IR_PEA            /*!< Protocol error in arbitration phase detected          */
+#define FDCAN_FLAG_DATA_PROTOCOL_ERROR     FDCAN_IR_PED            /*!< Protocol error in data phase detected                 */
+#define FDCAN_FLAG_RESERVED_ADDRESS_ACCESS FDCAN_IR_ARA            /*!< Access to reserved address occurred                   */
+#define FDCAN_FLAG_TIMESTAMP_WRAPAROUND    FDCAN_IR_TSW            /*!< Timestamp counter wrapped around                      */
+#define FDCAN_FLAG_TIMEOUT_OCCURRED        FDCAN_IR_TOO            /*!< Timeout reached                                       */
+#define FDCAN_FLAG_CALIB_STATE_CHANGED     (FDCANCCU_IR_CSC << 30) /*!< Clock calibration state changed                       */
+#define FDCAN_FLAG_CALIB_WATCHDOG_EVENT    (FDCANCCU_IR_CWE << 30) /*!< Clock calibration watchdog event occurred             */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Interrupts FDCAN Interrupts
+  * @{
+  */
+
+/** @defgroup FDCAN_Tx_Interrupts FDCAN Tx Interrupts
+  * @{
+  */
+#define FDCAN_IT_TX_COMPLETE           FDCAN_IE_TCE   /*!< Transmission Completed                                */
+#define FDCAN_IT_TX_ABORT_COMPLETE     FDCAN_IE_TCFE  /*!< Transmission Cancellation Finished                    */
+#define FDCAN_IT_TX_FIFO_EMPTY         FDCAN_IE_TFEE  /*!< Tx FIFO Empty                                         */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Rx_Interrupts FDCAN Rx Interrupts
+  * @{
+  */
+#define FDCAN_IT_RX_HIGH_PRIORITY_MSG  FDCAN_IE_HPME  /*!< High priority message received                        */
+#define FDCAN_IT_RX_BUFFER_NEW_MESSAGE FDCAN_IE_DRXE  /*!< At least one received message stored into a Rx Buffer */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Counter_Interrupts FDCAN Counter Interrupts
+  * @{
+  */
+#define FDCAN_IT_TIMESTAMP_WRAPAROUND  FDCAN_IE_TSWE  /*!< Timestamp counter wrapped around                      */
+#define FDCAN_IT_TIMEOUT_OCCURRED      FDCAN_IE_TOOE  /*!< Timeout reached                                       */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Clock_Calibration_Interrupts Clock Calibration Interrupts
+  * @{
+  */
+#define FDCAN_IT_CALIB_STATE_CHANGED  (FDCANCCU_IE_CSCE << 30) /*!< Clock calibration state changed           */
+#define FDCAN_IT_CALIB_WATCHDOG_EVENT (FDCANCCU_IE_CWEE << 30) /*!< Clock calibration watchdog event occurred */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Tx_Event_Fifo_Interrupts FDCAN Tx Event FIFO Interrupts
+  * @{
+  */
+#define FDCAN_IT_TX_EVT_FIFO_ELT_LOST  FDCAN_IE_TEFLE /*!< Tx Event FIFO element lost                 */
+#define FDCAN_IT_TX_EVT_FIFO_FULL      FDCAN_IE_TEFFE /*!< Tx Event FIFO full                         */
+#define FDCAN_IT_TX_EVT_FIFO_WATERMARK FDCAN_IE_TEFWE /*!< Tx Event FIFO fill level reached watermark */
+#define FDCAN_IT_TX_EVT_FIFO_NEW_DATA  FDCAN_IE_TEFNE /*!< Tx Handler wrote Tx Event FIFO element     */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Rx_Fifo0_Interrupts FDCAN Rx FIFO 0 Interrupts
+  * @{
+  */
+#define FDCAN_IT_RX_FIFO0_MESSAGE_LOST FDCAN_IE_RF0LE /*!< Rx FIFO 0 message lost                 */
+#define FDCAN_IT_RX_FIFO0_FULL         FDCAN_IE_RF0FE /*!< Rx FIFO 0 full                         */
+#define FDCAN_IT_RX_FIFO0_WATERMARK    FDCAN_IE_RF0WE /*!< Rx FIFO 0 fill level reached watermark */
+#define FDCAN_IT_RX_FIFO0_NEW_MESSAGE  FDCAN_IE_RF0NE /*!< New message written to Rx FIFO 0       */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Rx_Fifo1_Interrupts FDCAN Rx FIFO 1 Interrupts
+  * @{
+  */
+#define FDCAN_IT_RX_FIFO1_MESSAGE_LOST FDCAN_IE_RF1LE /*!< Rx FIFO 1 message lost                 */
+#define FDCAN_IT_RX_FIFO1_FULL         FDCAN_IE_RF1FE /*!< Rx FIFO 1 full                         */
+#define FDCAN_IT_RX_FIFO1_WATERMARK    FDCAN_IE_RF1WE /*!< Rx FIFO 1 fill level reached watermark */
+#define FDCAN_IT_RX_FIFO1_NEW_MESSAGE  FDCAN_IE_RF1NE /*!< New message written to Rx FIFO 1       */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Error_Interrupts FDCAN Error Interrupts
+  * @{
+  */
+#define FDCAN_IT_RAM_ACCESS_FAILURE      FDCAN_IE_MRAFE /*!< Message RAM access failure occurred              */
+#define FDCAN_IT_ERROR_LOGGING_OVERFLOW  FDCAN_IE_ELOE  /*!< Overflow of FDCAN Error Logging Counter occurred */
+#define FDCAN_IT_RAM_WATCHDOG            FDCAN_IE_WDIE  /*!< Message RAM Watchdog event due to missing READY  */
+#define FDCAN_IT_ARB_PROTOCOL_ERROR      FDCAN_IE_PEAE  /*!< Protocol error in arbitration phase detected     */
+#define FDCAN_IT_DATA_PROTOCOL_ERROR     FDCAN_IE_PEDE  /*!< Protocol error in data phase detected            */
+#define FDCAN_IT_RESERVED_ADDRESS_ACCESS FDCAN_IE_ARAE  /*!< Access to reserved address occurred              */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Error_Status_Interrupts FDCAN Error Status Interrupts
+  * @{
+  */
+#define FDCAN_IT_ERROR_PASSIVE FDCAN_IE_EPE /*!< Error_Passive status changed */
+#define FDCAN_IT_ERROR_WARNING FDCAN_IE_EWE /*!< Error_Warning status changed */
+#define FDCAN_IT_BUS_OFF       FDCAN_IE_BOE /*!< Bus_Off status changed       */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TTflags FDCAN TT Flags
+  * @{
+  */
+#define FDCAN_TT_FLAG_BASIC_CYCLE_START    FDCAN_TTIR_SBC  /*!< Start of Basic Cycle             */
+#define FDCAN_TT_FLAG_MATRIX_CYCLE_START   FDCAN_TTIR_SMC  /*!< Start of Matrix Cycle            */
+#define FDCAN_TT_FLAG_SYNC_MODE_CHANGE     FDCAN_TTIR_CSM  /*!< Change of Synchronization Mode   */
+#define FDCAN_TT_FLAG_START_OF_GAP         FDCAN_TTIR_SOG  /*!< Start of Gap                     */
+#define FDCAN_TT_FLAG_REG_TIME_MARK        FDCAN_TTIR_RTMI /*!< Register Time Mark Interrupt     */
+#define FDCAN_TT_FLAG_TRIG_TIME_MARK       FDCAN_TTIR_TTMI /*!< Trigger Time Mark Event Internal */
+#define FDCAN_TT_FLAG_STOP_WATCH           FDCAN_TTIR_SWE  /*!< Stop Watch Event                 */
+#define FDCAN_TT_FLAG_GLOBAL_TIME_WRAP     FDCAN_TTIR_GTW  /*!< Global Time Wrap                 */
+#define FDCAN_TT_FLAG_GLOBAL_TIME_DISC     FDCAN_TTIR_GTD  /*!< Global Time Discontinuity        */
+#define FDCAN_TT_FLAG_GLOBAL_TIME_ERROR    FDCAN_TTIR_GTE  /*!< Global Time Error                */
+#define FDCAN_TT_FLAG_TX_COUNT_UNDERFLOW   FDCAN_TTIR_TXU  /*!< Tx Count Underflow               */
+#define FDCAN_TT_FLAG_TX_COUNT_OVERFLOW    FDCAN_TTIR_TXO  /*!< Tx Count Overflow                */
+#define FDCAN_TT_FLAG_SCHEDULING_ERROR_1   FDCAN_TTIR_SE1  /*!< Scheduling Error 1               */
+#define FDCAN_TT_FLAG_SCHEDULING_ERROR_2   FDCAN_TTIR_SE2  /*!< Scheduling Error 2               */
+#define FDCAN_TT_FLAG_ERROR_LEVEL_CHANGE   FDCAN_TTIR_ELC  /*!< Error Level Changed              */
+#define FDCAN_TT_FLAG_INIT_WATCH_TRIGGER   FDCAN_TTIR_IWT  /*!< Initialization Watch Trigger     */
+#define FDCAN_TT_FLAG_WATCH_TRIGGER        FDCAN_TTIR_WT   /*!< Watch Trigger                    */
+#define FDCAN_TT_FLAG_APPLICATION_WATCHDOG FDCAN_TTIR_AW   /*!< Application Watchdog             */
+#define FDCAN_TT_FLAG_CONFIG_ERROR         FDCAN_TTIR_CER  /*!< Configuration Error              */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TTInterrupts FDCAN TT Interrupts
+  * @{
+  */
+
+/** @defgroup FDCAN_TTScheduleSynchronization_Interrupts FDCAN TT Schedule Synchronization Interrupts
+  * @{
+  */
+#define FDCAN_TT_IT_BASIC_CYCLE_START  FDCAN_TTIE_SBCE /*!< Start of Basic Cycle           */
+#define FDCAN_TT_IT_MATRIX_CYCLE_START FDCAN_TTIE_SMCE /*!< Start of Matrix Cycle          */
+#define FDCAN_TT_IT_SYNC_MODE_CHANGE   FDCAN_TTIE_CSME /*!< Change of Synchronization Mode */
+#define FDCAN_TT_IT_START_OF_GAP       FDCAN_TTIE_SOGE /*!< Start of Gap                   */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TTTimeMark_Interrupts FDCAN TT Time Mark Interrupts
+  * @{
+  */
+#define FDCAN_TT_IT_REG_TIME_MARK  FDCAN_TTIE_RTMIE /*!< Register Time Mark Interrupt     */
+#define FDCAN_TT_IT_TRIG_TIME_MARK FDCAN_TTIE_TTMIE /*!< Trigger Time Mark Event Internal */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TTStopWatch_Interrupt FDCAN TT Stop Watch Interrupt
+  * @{
+  */
+#define FDCAN_TT_IT_STOP_WATCH FDCAN_TTIE_SWEE /*!< Stop Watch Event */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TTGlobalTime_Interrupts FDCAN TT Global Time Interrupts
+  * @{
+  */
+#define FDCAN_TT_IT_GLOBAL_TIME_WRAP FDCAN_TTIE_GTWE  /*!< Global Time Wrap          */
+#define FDCAN_TT_IT_GLOBAL_TIME_DISC FDCAN_TTIE_GTDE  /*!< Global Time Discontinuity */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TTDisturbingError_Interrupts FDCAN TT Disturbing Error Interrupts
+  * @{
+  */
+#define FDCAN_TT_IT_GLOBAL_TIME_ERROR  FDCAN_TTIE_GTEE /*!< Global Time Error   */
+#define FDCAN_TT_IT_TX_COUNT_UNDERFLOW FDCAN_TTIE_TXUE /*!< Tx Count Underflow  */
+#define FDCAN_TT_IT_TX_COUNT_OVERFLOW  FDCAN_TTIE_TXOE /*!< Tx Count Overflow   */
+#define FDCAN_TT_IT_SCHEDULING_ERROR_1 FDCAN_TTIE_SE1E /*!< Scheduling Error 1  */
+#define FDCAN_TT_IT_SCHEDULING_ERROR_2 FDCAN_TTIE_SE2E /*!< Scheduling Error 2  */
+#define FDCAN_TT_IT_ERROR_LEVEL_CHANGE FDCAN_TTIE_ELCE /*!< Error Level Changed */
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_TTFatalError_Interrupts FDCAN TT Fatal Error Interrupts
+  * @{
+  */
+#define FDCAN_TT_IT_INIT_WATCH_TRIGGER   FDCAN_TTIE_IWTE /*!< Initialization Watch Trigger */
+#define FDCAN_TT_IT_WATCH_TRIGGER        FDCAN_TTIE_WTE  /*!< Watch Trigger                */
+#define FDCAN_TT_IT_APPLICATION_WATCHDOG FDCAN_TTIE_AWE  /*!< Application Watchdog         */
+#define FDCAN_TT_IT_CONFIG_ERROR         FDCAN_TTIE_CERE /*!< Configuration Error          */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup FDCAN_Exported_Macros FDCAN Exported Macros
+  * @{
+  */
+
+/** @brief  Reset FDCAN handle state.
+  * @param  __HANDLE__ FDCAN handle.
+  * @retval None
+  */
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) do{                                                \
+                                                      (__HANDLE__)->State = HAL_FDCAN_STATE_RESET;    \
+                                                      (__HANDLE__)->MspInitCallback = NULL;           \
+                                                      (__HANDLE__)->MspDeInitCallback = NULL;         \
+                                                     } while(0)
+#else
+#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FDCAN_STATE_RESET)
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+/**
+  * @brief  Enable the specified FDCAN interrupts.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ FDCAN interrupt.
+  *         This parameter can be any combination of @arg FDCAN_Interrupts
+  * @retval None
+  */
+#define __HAL_FDCAN_ENABLE_IT(__HANDLE__, __INTERRUPT__)             \
+  do{                                                                \
+    (__HANDLE__)->Instance->IE |= ((__INTERRUPT__) & FDCAN_IR_MASK); \
+    FDCAN_CCU->IE |= (((__INTERRUPT__) & CCU_IR_MASK) >> 30);        \
+  }while(0)
+
+
+/**
+  * @brief  Disable the specified FDCAN interrupts.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ FDCAN interrupt.
+  *         This parameter can be any combination of @arg FDCAN_Interrupts
+  * @retval None
+  */
+#define __HAL_FDCAN_DISABLE_IT(__HANDLE__, __INTERRUPT__)               \
+  do{                                                                   \
+    ((__HANDLE__)->Instance->IE) &= ~((__INTERRUPT__) & FDCAN_IR_MASK); \
+    FDCAN_CCU->IE &= ~(((__INTERRUPT__) & CCU_IR_MASK) >> 30);          \
+  }while(0)
+
+/**
+  * @brief  Check whether the specified FDCAN interrupt is set or not.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ FDCAN interrupt.
+  *         This parameter can be one of @arg FDCAN_Interrupts
+  * @retval ITStatus
+  */
+#define __HAL_FDCAN_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__INTERRUPT__)) : ((FDCAN_CCU->IR << 30) & (__INTERRUPT__)))
+
+/**
+  * @brief  Clear the specified FDCAN interrupts.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ specifies the interrupts to clear.
+  *         This parameter can be any combination of @arg FDCAN_Interrupts
+  * @retval None
+  */
+#define __HAL_FDCAN_CLEAR_IT(__HANDLE__, __INTERRUPT__)               \
+do{                                                                   \
+    ((__HANDLE__)->Instance->IR) = ((__INTERRUPT__) & FDCAN_IR_MASK); \
+    FDCAN_CCU->IR = (((__INTERRUPT__) & CCU_IR_MASK) >> 30);          \
+  }while(0)
+
+/**
+  * @brief  Check whether the specified FDCAN flag is set or not.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __FLAG__ FDCAN flag.
+  *         This parameter can be one of @arg FDCAN_flags
+  * @retval FlagStatus
+  */
+#define __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) < FDCAN_FLAG_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__FLAG__)) : ((FDCAN_CCU->IR << 30) & (__FLAG__)))
+
+/**
+  * @brief  Clear the specified FDCAN flags.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __FLAG__ specifies the flags to clear.
+  *         This parameter can be any combination of @arg FDCAN_flags
+  * @retval None
+  */
+#define __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__)             \
+do{                                                              \
+    ((__HANDLE__)->Instance->IR) = ((__FLAG__) & FDCAN_IR_MASK); \
+    FDCAN_CCU->IR = (((__FLAG__) & CCU_IR_MASK) >> 30);          \
+  }while(0)
+
+/** @brief  Check if the specified FDCAN interrupt source is enabled or disabled.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ specifies the FDCAN interrupt source to check.
+  *         This parameter can be a value of @arg FDCAN_Interrupts
+  * @retval ITStatus
+  */
+#define __HAL_FDCAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IE & (__INTERRUPT__)) : ((FDCAN_CCU->IE << 30) & (__INTERRUPT__)))
+
+/**
+  * @brief  Enable the specified FDCAN TT interrupts.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ FDCAN TT interrupt.
+  *         This parameter can be any combination of @arg FDCAN_TTInterrupts
+  * @retval None
+  */
+#define __HAL_FDCAN_TT_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the specified FDCAN TT interrupts.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ FDCAN TT interrupt.
+  *         This parameter can be any combination of @arg FDCAN_TTInterrupts
+  * @retval None
+  */
+#define __HAL_FDCAN_TT_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified FDCAN TT interrupt is set or not.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ FDCAN TT interrupt.
+  *         This parameter can be one of @arg FDCAN_TTInterrupts
+  * @retval ITStatus
+  */
+#define __HAL_FDCAN_TT_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) & (__INTERRUPT__))
+
+/**
+  * @brief  Clear the specified FDCAN TT interrupts.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ specifies the TT interrupts to clear.
+  *         This parameter can be any combination of @arg FDCAN_TTInterrupts
+  * @retval None
+  */
+#define __HAL_FDCAN_TT_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) = (__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified FDCAN TT flag is set or not.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __FLAG__ FDCAN TT flag.
+  *         This parameter can be one of @arg FDCAN_TTflags
+  * @retval FlagStatus
+  */
+#define __HAL_FDCAN_TT_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) & (__FLAG__))
+
+/**
+  * @brief  Clear the specified FDCAN TT flags.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __FLAG__ specifies the TT flags to clear.
+  *         This parameter can be any combination of @arg FDCAN_TTflags
+  * @retval None
+  */
+#define __HAL_FDCAN_TT_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) = (__FLAG__))
+
+/** @brief  Check if the specified FDCAN TT interrupt source is enabled or disabled.
+  * @param  __HANDLE__ FDCAN handle.
+  * @param  __INTERRUPT__ specifies the FDCAN TT interrupt source to check.
+  *         This parameter can be a value of @arg FDCAN_TTInterrupts
+  * @retval ITStatus
+  */
+#define __HAL_FDCAN_TT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) & (__INTERRUPT__))
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FDCAN_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup FDCAN_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan);
+void              HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan);
+void              HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+/* Callbacks Register/UnRegister functions  ***********************************/
+HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, pFDCAN_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID);
+HAL_StatusTypeDef HAL_FDCAN_RegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ClockCalibrationCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxEventFifoCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo0CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo1CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferCompleteCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferAbortCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ErrorStatusCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_ScheduleSyncCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_TimeMarkCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_StopWatchCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_GlobalTimeCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @addtogroup FDCAN_Exported_Functions_Group2
+  * @{
+  */
+/* Configuration functions ****************************************************/
+HAL_StatusTypeDef HAL_FDCAN_ConfigClockCalibration(FDCAN_HandleTypeDef *hfdcan, FDCAN_ClkCalUnitTypeDef *sCcuConfig);
+uint32_t          HAL_FDCAN_GetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ResetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan);
+uint32_t          HAL_FDCAN_GetClockCalibrationCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t Counter);
+HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig);
+HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd, uint32_t NonMatchingExt, uint32_t RejectRemoteStd, uint32_t RejectRemoteExt);
+HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask);
+HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode);
+HAL_StatusTypeDef HAL_FDCAN_ConfigFifoWatermark(FDCAN_HandleTypeDef *hfdcan, uint32_t FIFO, uint32_t Watermark);
+HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue);
+HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler);
+HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation);
+HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
+uint16_t          HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod);
+HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
+uint16_t          HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter);
+HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan);
+/**
+  * @}
+  */
+
+/** @addtogroup FDCAN_Exported_Functions_Group3
+  * @{
+  */
+/* Control functions **********************************************************/
+HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData);
+HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxBuffer(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex);
+HAL_StatusTypeDef HAL_FDCAN_EnableTxBufferRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex);
+uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex);
+HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData);
+HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent);
+HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus);
+HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus);
+HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters);
+uint32_t HAL_FDCAN_IsRxBufferMessageAvailable(FDCAN_HandleTypeDef *hfdcan, uint32_t RxBufferIndex);
+uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex);
+uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo);
+uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan);
+uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan);
+/**
+  * @}
+  */
+
+/** @addtogroup FDCAN_Exported_Functions_Group4
+  * @{
+  */
+/* TT Configuration and control functions**************************************/
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigOperation(FDCAN_HandleTypeDef *hfdcan, FDCAN_TT_ConfigTypeDef *pTTParams);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigReferenceMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t IdType, uint32_t Identifier, uint32_t Payload);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigTrigger(FDCAN_HandleTypeDef *hfdcan, FDCAN_TriggerTypeDef *sTriggerConfig);
+HAL_StatusTypeDef HAL_FDCAN_TT_SetGlobalTime(FDCAN_HandleTypeDef *hfdcan, uint32_t TimePreset);
+HAL_StatusTypeDef HAL_FDCAN_TT_SetClockSynchronization(FDCAN_HandleTypeDef *hfdcan, uint32_t NewTURNumerator);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigStopWatch(FDCAN_HandleTypeDef *hfdcan, uint32_t Source, uint32_t Polarity);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigRegisterTimeMark(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeMarkSource, uint32_t TimeMarkValue, uint32_t RepeatFactor, uint32_t StartCycle);
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_SetNextIsGap(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_SetEndOfGap(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigExternalSyncPhase(FDCAN_HandleTypeDef *hfdcan, uint32_t TargetPhase);
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_GetOperationStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_TTOperationStatusTypeDef *TTOpStatus);
+/**
+  * @}
+  */
+
+/** @addtogroup FDCAN_Exported_Functions_Group5
+  * @{
+  */
+/* Interrupts management ******************************************************/
+HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t TTITList, uint32_t InterruptLine);
+HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes);
+HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs);
+HAL_StatusTypeDef HAL_FDCAN_TT_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveTTITs);
+HAL_StatusTypeDef HAL_FDCAN_TT_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveTTITs);
+void              HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan);
+/**
+  * @}
+  */
+
+/** @addtogroup FDCAN_Exported_Functions_Group6
+  * @{
+  */
+/* Callback functions *********************************************************/
+void HAL_FDCAN_ClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs);
+void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs);
+void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs);
+void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs);
+void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);
+void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);
+void HAL_FDCAN_RxBufferNewMessageCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs);
+void HAL_FDCAN_TT_ScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs);
+void HAL_FDCAN_TT_TimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs);
+void HAL_FDCAN_TT_StopWatchCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount);
+void HAL_FDCAN_TT_GlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs);
+/**
+  * @}
+  */
+
+/** @addtogroup FDCAN_Exported_Functions_Group7
+  * @{
+  */
+/* Peripheral State functions *************************************************/
+uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan);
+HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup FDCAN_Private_Types FDCAN Private Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup FDCAN_Private_Variables FDCAN Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup FDCAN_Private_Constants FDCAN Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FDCAN_Private_Macros FDCAN Private Macros
+  * @{
+  */
+#define IS_FDCAN_FRAME_FORMAT(FORMAT) (((FORMAT) == FDCAN_FRAME_CLASSIC  ) || \
+                                       ((FORMAT) == FDCAN_FRAME_FD_NO_BRS) || \
+                                       ((FORMAT) == FDCAN_FRAME_FD_BRS   ))
+#define IS_FDCAN_MODE(MODE) (((MODE) == FDCAN_MODE_NORMAL              ) || \
+                             ((MODE) == FDCAN_MODE_RESTRICTED_OPERATION) || \
+                             ((MODE) == FDCAN_MODE_BUS_MONITORING      ) || \
+                             ((MODE) == FDCAN_MODE_INTERNAL_LOOPBACK   ) || \
+                             ((MODE) == FDCAN_MODE_EXTERNAL_LOOPBACK   ))
+
+#define IS_FDCAN_CLOCK_CALIBRATION(CALIBRATION) (((CALIBRATION) == FDCAN_CLOCK_CALIBRATION_DISABLE) || \
+                                                 ((CALIBRATION) == FDCAN_CLOCK_CALIBRATION_ENABLE ))
+
+#define IS_FDCAN_CKDIV(CKDIV) (((CKDIV) == FDCAN_CLOCK_DIV1 ) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV2 ) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV4 ) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV6 ) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV8 ) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV10) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV12) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV14) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV16) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV18) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV20) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV22) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV24) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV26) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV28) || \
+                               ((CKDIV) == FDCAN_CLOCK_DIV30))
+#define IS_FDCAN_NOMINAL_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 512U))
+#define IS_FDCAN_NOMINAL_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 128U))
+#define IS_FDCAN_NOMINAL_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 256U))
+#define IS_FDCAN_NOMINAL_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 128U))
+#define IS_FDCAN_DATA_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 32U))
+#define IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 16U))
+#define IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 32U))
+#define IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 16U))
+#define IS_FDCAN_MAX_VALUE(VALUE, MAX) ((VALUE) <= (MAX))
+#define IS_FDCAN_MIN_VALUE(VALUE, MIN) ((VALUE) >= (MIN))
+#define IS_FDCAN_DATA_SIZE(SIZE) (((SIZE) == FDCAN_DATA_BYTES_8 ) || \
+                                  ((SIZE) == FDCAN_DATA_BYTES_12) || \
+                                  ((SIZE) == FDCAN_DATA_BYTES_16) || \
+                                  ((SIZE) == FDCAN_DATA_BYTES_20) || \
+                                  ((SIZE) == FDCAN_DATA_BYTES_24) || \
+                                  ((SIZE) == FDCAN_DATA_BYTES_32) || \
+                                  ((SIZE) == FDCAN_DATA_BYTES_48) || \
+                                  ((SIZE) == FDCAN_DATA_BYTES_64))
+#define IS_FDCAN_TX_FIFO_QUEUE_MODE(MODE) (((MODE) == FDCAN_TX_FIFO_OPERATION ) || \
+                                           ((MODE) == FDCAN_TX_QUEUE_OPERATION))
+#define IS_FDCAN_ID_TYPE(ID_TYPE) (((ID_TYPE) == FDCAN_STANDARD_ID) || \
+                                   ((ID_TYPE) == FDCAN_EXTENDED_ID))
+#define IS_FDCAN_FILTER_CFG(CONFIG) (((CONFIG) == FDCAN_FILTER_DISABLE      ) || \
+                                     ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0   ) || \
+                                     ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1   ) || \
+                                     ((CONFIG) == FDCAN_FILTER_REJECT       ) || \
+                                     ((CONFIG) == FDCAN_FILTER_HP           ) || \
+                                     ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0_HP) || \
+                                     ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1_HP) || \
+                                     ((CONFIG) == FDCAN_FILTER_TO_RXBUFFER  ))
+#define IS_FDCAN_TX_LOCATION(LOCATION) (((LOCATION) == FDCAN_TX_BUFFER0 ) || ((LOCATION) == FDCAN_TX_BUFFER1 ) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER2 ) || ((LOCATION) == FDCAN_TX_BUFFER3 ) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER4 ) || ((LOCATION) == FDCAN_TX_BUFFER5 ) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER6 ) || ((LOCATION) == FDCAN_TX_BUFFER7 ) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER8 ) || ((LOCATION) == FDCAN_TX_BUFFER9 ) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER10) || ((LOCATION) == FDCAN_TX_BUFFER11) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER12) || ((LOCATION) == FDCAN_TX_BUFFER13) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER14) || ((LOCATION) == FDCAN_TX_BUFFER15) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER16) || ((LOCATION) == FDCAN_TX_BUFFER17) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER18) || ((LOCATION) == FDCAN_TX_BUFFER19) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER20) || ((LOCATION) == FDCAN_TX_BUFFER21) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER22) || ((LOCATION) == FDCAN_TX_BUFFER23) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER24) || ((LOCATION) == FDCAN_TX_BUFFER25) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER26) || ((LOCATION) == FDCAN_TX_BUFFER27) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER28) || ((LOCATION) == FDCAN_TX_BUFFER29) || \
+                                        ((LOCATION) == FDCAN_TX_BUFFER30) || ((LOCATION) == FDCAN_TX_BUFFER31))
+#define IS_FDCAN_RX_FIFO(FIFO) (((FIFO) == FDCAN_RX_FIFO0) || \
+                                ((FIFO) == FDCAN_RX_FIFO1))
+#define IS_FDCAN_RX_FIFO_MODE(MODE) (((MODE) == FDCAN_RX_FIFO_BLOCKING ) || \
+                                     ((MODE) == FDCAN_RX_FIFO_OVERWRITE))
+#define IS_FDCAN_STD_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE) || \
+                                        ((TYPE) == FDCAN_FILTER_DUAL ) || \
+                                        ((TYPE) == FDCAN_FILTER_MASK ))
+#define IS_FDCAN_EXT_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE        ) || \
+                                        ((TYPE) == FDCAN_FILTER_DUAL         ) || \
+                                        ((TYPE) == FDCAN_FILTER_MASK         ) || \
+                                        ((TYPE) == FDCAN_FILTER_RANGE_NO_EIDM))
+#define IS_FDCAN_FRAME_TYPE(TYPE) (((TYPE) == FDCAN_DATA_FRAME  ) || \
+                                   ((TYPE) == FDCAN_REMOTE_FRAME))
+#define IS_FDCAN_DLC(DLC) (((DLC) == FDCAN_DLC_BYTES_0 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_1 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_2 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_3 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_4 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_5 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_6 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_7 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_8 ) || \
+                           ((DLC) == FDCAN_DLC_BYTES_12) || \
+                           ((DLC) == FDCAN_DLC_BYTES_16) || \
+                           ((DLC) == FDCAN_DLC_BYTES_20) || \
+                           ((DLC) == FDCAN_DLC_BYTES_24) || \
+                           ((DLC) == FDCAN_DLC_BYTES_32) || \
+                           ((DLC) == FDCAN_DLC_BYTES_48) || \
+                           ((DLC) == FDCAN_DLC_BYTES_64))
+#define IS_FDCAN_ESI(ESI) (((ESI) == FDCAN_ESI_ACTIVE ) || \
+                           ((ESI) == FDCAN_ESI_PASSIVE))
+#define IS_FDCAN_BRS(BRS) (((BRS) == FDCAN_BRS_OFF) || \
+                           ((BRS) == FDCAN_BRS_ON ))
+#define IS_FDCAN_FDF(FDF) (((FDF) == FDCAN_CLASSIC_CAN) || \
+                           ((FDF) == FDCAN_FD_CAN     ))
+#define IS_FDCAN_EFC(EFC) (((EFC) == FDCAN_NO_TX_EVENTS   ) || \
+                           ((EFC) == FDCAN_STORE_TX_EVENTS))
+#define IS_FDCAN_IT(IT) (((IT) & ~(FDCAN_IR_MASK | CCU_IR_MASK)) == 0U)
+#define IS_FDCAN_TT_IT(IT) (((IT) & 0xFFF80000U) == 0U)
+#define IS_FDCAN_FIFO_WATERMARK(FIFO) (((FIFO) == FDCAN_CFG_TX_EVENT_FIFO) || \
+                                       ((FIFO) == FDCAN_CFG_RX_FIFO0     ) || \
+                                       ((FIFO) == FDCAN_CFG_RX_FIFO1     ))
+#define IS_FDCAN_NON_MATCHING(DESTINATION) (((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO0) || \
+                                            ((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO1) || \
+                                            ((DESTINATION) == FDCAN_REJECT            ))
+#define IS_FDCAN_REJECT_REMOTE(DESTINATION) (((DESTINATION) == FDCAN_FILTER_REMOTE) || \
+                                             ((DESTINATION) == FDCAN_REJECT_REMOTE))
+#define IS_FDCAN_IT_LINE(IT_LINE) (((IT_LINE) == FDCAN_INTERRUPT_LINE0) || \
+                                   ((IT_LINE) == FDCAN_INTERRUPT_LINE1))
+#define IS_FDCAN_TIMESTAMP(OPERATION) (((OPERATION) == FDCAN_TIMESTAMP_INTERNAL) || \
+                                       ((OPERATION) == FDCAN_TIMESTAMP_EXTERNAL))
+#define IS_FDCAN_TIMESTAMP_PRESCALER(PRESCALER) (((PRESCALER) == FDCAN_TIMESTAMP_PRESC_1 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_2 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_3 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_4 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_5 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_6 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_7 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_8 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_9 ) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_10) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_11) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_12) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_13) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_14) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_15) || \
+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_16))
+#define IS_FDCAN_TIMEOUT(OPERATION) (((OPERATION) == FDCAN_TIMEOUT_CONTINUOUS   ) || \
+                                     ((OPERATION) == FDCAN_TIMEOUT_TX_EVENT_FIFO) || \
+                                     ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO0     ) || \
+                                     ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO1     ))
+#define IS_FDCAN_CALIBRATION_FIELD_LENGTH(LENGTH) (((LENGTH) == FDCAN_CALIB_FIELD_LENGTH_32) || \
+                                                   ((LENGTH) == FDCAN_CALIB_FIELD_LENGTH_64))
+#define IS_FDCAN_CALIBRATION_COUNTER(COUNTER) (((COUNTER) == FDCAN_CALIB_TIME_QUANTA_COUNTER ) || \
+                                               ((COUNTER) == FDCAN_CALIB_CLOCK_PERIOD_COUNTER) || \
+                                               ((COUNTER) == FDCAN_CALIB_WATCHDOG_COUNTER    ))
+#define IS_FDCAN_TT_REFERENCE_MESSAGE_PAYLOAD(PAYLOAD) (((PAYLOAD) == FDCAN_TT_REF_MESSAGE_NO_PAYLOAD ) || \
+                                                        ((PAYLOAD) == FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD))
+#define IS_FDCAN_TT_REPEAT_FACTOR(FACTOR) (((FACTOR) == FDCAN_TT_REPEAT_EVERY_CYCLE     ) || \
+                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_2ND_CYCLE ) || \
+                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_4TH_CYCLE ) || \
+                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_8TH_CYCLE ) || \
+                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_16TH_CYCLE) || \
+                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_32ND_CYCLE) || \
+                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_64TH_CYCLE))
+#define IS_FDCAN_TT_TRIGGER_TYPE(TYPE) (((TYPE) == FDCAN_TT_TX_REF_TRIGGER        ) || \
+                                        ((TYPE) == FDCAN_TT_TX_REF_TRIGGER_GAP    ) || \
+                                        ((TYPE) == FDCAN_TT_TX_TRIGGER_SINGLE     ) || \
+                                        ((TYPE) == FDCAN_TT_TX_TRIGGER_CONTINUOUS ) || \
+                                        ((TYPE) == FDCAN_TT_TX_TRIGGER_ARBITRATION) || \
+                                        ((TYPE) == FDCAN_TT_TX_TRIGGER_MERGED     ) || \
+                                        ((TYPE) == FDCAN_TT_WATCH_TRIGGER         ) || \
+                                        ((TYPE) == FDCAN_TT_WATCH_TRIGGER_GAP     ) || \
+                                        ((TYPE) == FDCAN_TT_RX_TRIGGER            ) || \
+                                        ((TYPE) == FDCAN_TT_TIME_BASE_TRIGGER     ) || \
+                                        ((TYPE) == FDCAN_TT_END_OF_LIST           ))
+#define IS_FDCAN_TT_TM_EVENT_INTERNAL(EVENT) (((EVENT) == FDCAN_TT_TM_NO_INTERNAL_EVENT ) || \
+                                              ((EVENT) == FDCAN_TT_TM_GEN_INTERNAL_EVENT))
+#define IS_FDCAN_TT_TM_EVENT_EXTERNAL(EVENT) (((EVENT) == FDCAN_TT_TM_NO_EXTERNAL_EVENT ) || \
+                                              ((EVENT) == FDCAN_TT_TM_GEN_EXTERNAL_EVENT))
+#define IS_FDCAN_OPERATION_MODE(MODE) (((MODE) == FDCAN_TT_COMMUNICATION_LEVEL1 ) || \
+                                       ((MODE) == FDCAN_TT_COMMUNICATION_LEVEL2 ) || \
+                                       ((MODE) == FDCAN_TT_COMMUNICATION_LEVEL0 ))
+#define IS_FDCAN_TT_OPERATION(OPERATION) (((OPERATION) == FDCAN_STRICTLY_TT_OPERATION      ) || \
+                                          ((OPERATION) == FDCAN_EXT_EVT_SYNC_TT_OPERATION))
+#define IS_FDCAN_TT_TIME_MASTER(FUNCTION) (((FUNCTION) == FDCAN_TT_SLAVE           ) || \
+                                           ((FUNCTION) == FDCAN_TT_POTENTIAL_MASTER))
+#define IS_FDCAN_TT_EXTERNAL_CLK_SYNC(SYNC) (((SYNC) == FDCAN_TT_EXT_CLK_SYNC_DISABLE) || \
+                                             ((SYNC) == FDCAN_TT_EXT_CLK_SYNC_ENABLE ))
+#define IS_FDCAN_TT_GLOBAL_TIME_FILTERING(FILTERING) (((FILTERING) == FDCAN_TT_GLOB_TIME_FILT_DISABLE) || \
+                                                      ((FILTERING) == FDCAN_TT_GLOB_TIME_FILT_ENABLE ))
+#define IS_FDCAN_TT_AUTO_CLK_CALIBRATION(CALIBRATION) (((CALIBRATION) == FDCAN_TT_AUTO_CLK_CALIB_DISABLE) || \
+                                                       ((CALIBRATION) == FDCAN_TT_AUTO_CLK_CALIB_ENABLE ))
+#define IS_FDCAN_TT_EVENT_TRIGGER_POLARITY(POLARITY) (((POLARITY) == FDCAN_TT_EVT_TRIG_POL_RISING ) || \
+                                                      ((POLARITY) == FDCAN_TT_EVT_TRIG_POL_FALLING))
+#define IS_FDCAN_TT_BASIC_CYCLES_NUMBER(NUMBER) (((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_1 ) || \
+                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_2 ) || \
+                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_4 ) || \
+                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_8 ) || \
+                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_16) || \
+                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_32) || \
+                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_64))
+#define IS_FDCAN_TT_CYCLE_START_SYNC(SYNC) (((SYNC) == FDCAN_TT_NO_SYNC_PULSE         ) || \
+                                            ((SYNC) == FDCAN_TT_SYNC_BASIC_CYCLE_START) || \
+                                            ((SYNC) == FDCAN_TT_SYNC_MATRIX_START     ))
+#define IS_FDCAN_TT_TX_ENABLE_WINDOW(NTU) (((NTU) >= 1U) && ((NTU) <= 16U))
+#define IS_FDCAN_TT_TUR_NUMERATOR(NUMERATOR) (((NUMERATOR) >= 0x10000U) && ((NUMERATOR) <= 0x1FFFFU))
+#define IS_FDCAN_TT_TUR_DENOMINATOR(DENOMINATOR) (((DENOMINATOR) >= 0x0001U) && ((DENOMINATOR) <= 0x3FFFU))
+#define IS_FDCAN_TT_TUR_LEVEL_1(NC,DC) ((NC) >= (4U * (DC)))
+#define IS_FDCAN_TT_TUR_LEVEL_0_2(NC,DC) ((NC) >= (8U * (DC)))
+#define IS_FDCAN_TT_STOP_WATCH_TRIGGER(TRIGGER) (((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_0) || \
+                                                 ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_1) || \
+                                                 ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_2) || \
+                                                 ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_3))
+#define IS_FDCAN_TT_EVENT_TRIGGER(TRIGGER) (((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_0) || \
+                                            ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_1) || \
+                                            ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_2) || \
+                                            ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_3))
+#define IS_FDCAN_TT_TIME_PRESET(TIME) (((TIME) <= 0xFFFFU) && ((TIME) != 0x8000U))
+#define IS_FDCAN_TT_STOP_WATCH_SOURCE(SOURCE) (((SOURCE) == FDCAN_TT_STOP_WATCH_DISABLED   ) || \
+                                               ((SOURCE) == FDCAN_TT_STOP_WATCH_CYCLE_TIME ) || \
+                                               ((SOURCE) == FDCAN_TT_STOP_WATCH_LOCAL_TIME ) || \
+                                               ((SOURCE) == FDCAN_TT_STOP_WATCH_GLOBAL_TIME))
+#define IS_FDCAN_TT_STOP_WATCH_POLARITY(POLARITY) (((POLARITY) == FDCAN_TT_STOP_WATCH_RISING ) || \
+                                                   ((POLARITY) == FDCAN_TT_STOP_WATCH_FALLING))
+#define IS_FDCAN_TT_REGISTER_TIME_MARK_SOURCE(SOURCE) (((SOURCE) == FDCAN_TT_REG_TIMEMARK_DIABLED ) || \
+                                                       ((SOURCE) == FDCAN_TT_REG_TIMEMARK_CYC_TIME) || \
+                                                       ((SOURCE) == FDCAN_TT_REG_TIMEMARK_LOC_TIME) || \
+                                                       ((SOURCE) == FDCAN_TT_REG_TIMEMARK_GLO_TIME))
+/**
+  * @}
+  */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup FDCAN_Private_Functions_Prototypes FDCAN Private Functions Prototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup FDCAN_Private_Functions FDCAN Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_FDCAN_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h
new file mode 100644
index 00000000..6bda249e
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h
@@ -0,0 +1,829 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_flash.h
+  * @author  MCD Application Team
+  * @brief   Header file of FLASH HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_FLASH_H
+#define STM32H7xx_HAL_FLASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FLASH
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Types FLASH Exported Types
+  * @{
+  */
+
+/**
+  * @brief  FLASH Procedure structure definition
+  */
+typedef enum
+{
+  FLASH_PROC_NONE = 0U,
+  FLASH_PROC_SECTERASE_BANK1,
+  FLASH_PROC_MASSERASE_BANK1,
+  FLASH_PROC_PROGRAM_BANK1,
+  FLASH_PROC_SECTERASE_BANK2,
+  FLASH_PROC_MASSERASE_BANK2,
+  FLASH_PROC_PROGRAM_BANK2,
+  FLASH_PROC_ALLBANK_MASSERASE
+} FLASH_ProcedureTypeDef;
+
+
+/**
+  * @brief  FLASH handle Structure definition
+  */
+typedef struct
+{
+  __IO FLASH_ProcedureTypeDef ProcedureOnGoing;   /*!< Internal variable to indicate which procedure is ongoing or not in IT context */
+
+  __IO uint32_t               NbSectorsToErase;   /*!< Internal variable to save the remaining sectors to erase in IT context        */
+
+  __IO uint32_t               VoltageForErase;    /*!< Internal variable to provide voltage range selected by user in IT context     */
+
+  __IO uint32_t               Sector;             /*!< Internal variable to define the current sector which is erasing               */
+
+  __IO uint32_t               Address;            /*!< Internal variable to save address selected for program                        */
+
+  HAL_LockTypeDef             Lock;               /*!< FLASH locking object                                                          */
+
+  __IO uint32_t               ErrorCode;          /*!< FLASH error code                                                              */
+
+}FLASH_ProcessTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
+  * @{
+  */
+
+/** @defgroup FLASH_Error_Code FLASH Error Code
+  * @brief    FLASH Error Code
+  * @{
+  */
+#define HAL_FLASH_ERROR_NONE         0x00000000U               /*!< No error                              */
+
+#define HAL_FLASH_ERROR_WRP          FLASH_FLAG_WRPERR         /*!< Write Protection Error                */
+#define HAL_FLASH_ERROR_PGS          FLASH_FLAG_PGSERR         /*!< Program Sequence Error                */
+#define HAL_FLASH_ERROR_STRB         FLASH_FLAG_STRBERR        /*!< Strobe Error                          */
+#define HAL_FLASH_ERROR_INC          FLASH_FLAG_INCERR         /*!< Inconsistency Error                   */
+#if defined (FLASH_SR_OPERR)
+#define HAL_FLASH_ERROR_OPE          FLASH_FLAG_OPERR          /*!< Operation Error                       */
+#endif /* FLASH_SR_OPERR */
+#define HAL_FLASH_ERROR_RDP          FLASH_FLAG_RDPERR         /*!< Read Protection Error                 */
+#define HAL_FLASH_ERROR_RDS          FLASH_FLAG_RDSERR         /*!< Read Secured Error                    */
+#define HAL_FLASH_ERROR_SNECC        FLASH_FLAG_SNECCERR       /*!< ECC Single Correction Error           */
+#define HAL_FLASH_ERROR_DBECC        FLASH_FLAG_DBECCERR       /*!< ECC Double Detection Error            */
+#define HAL_FLASH_ERROR_CRCRD        FLASH_FLAG_CRCRDERR       /*!< CRC Read Error                        */
+
+#define HAL_FLASH_ERROR_WRP_BANK1    FLASH_FLAG_WRPERR_BANK1   /*!< Write Protection Error on Bank 1      */
+#define HAL_FLASH_ERROR_PGS_BANK1    FLASH_FLAG_PGSERR_BANK1   /*!< Program Sequence Error on Bank 1      */
+#define HAL_FLASH_ERROR_STRB_BANK1   FLASH_FLAG_STRBERR_BANK1  /*!< Strobe Error on Bank 1                */
+#define HAL_FLASH_ERROR_INC_BANK1    FLASH_FLAG_INCERR_BANK1   /*!< Inconsistency Error on Bank 1         */
+#if defined (FLASH_SR_OPERR)
+#define HAL_FLASH_ERROR_OPE_BANK1    FLASH_FLAG_OPERR_BANK1    /*!< Operation Error on Bank 1             */
+#endif /* FLASH_SR_OPERR */
+#define HAL_FLASH_ERROR_RDP_BANK1    FLASH_FLAG_RDPERR_BANK1   /*!< Read Protection Error on Bank 1       */
+#define HAL_FLASH_ERROR_RDS_BANK1    FLASH_FLAG_RDSERR_BANK1   /*!< Read Secured Error on Bank 1          */
+#define HAL_FLASH_ERROR_SNECC_BANK1  FLASH_FLAG_SNECCERR_BANK1 /*!< ECC Single Correction Error on Bank 1 */
+#define HAL_FLASH_ERROR_DBECC_BANK1  FLASH_FLAG_DBECCERR_BANK1 /*!< ECC Double Detection Error on Bank 1  */
+#define HAL_FLASH_ERROR_CRCRD_BANK1  FLASH_FLAG_CRCRDERR_BANK1 /*!< CRC Read Error on Bank1               */
+
+#define HAL_FLASH_ERROR_WRP_BANK2    FLASH_FLAG_WRPERR_BANK2    /*!< Write Protection Error on Bank 2      */
+#define HAL_FLASH_ERROR_PGS_BANK2    FLASH_FLAG_PGSERR_BANK2    /*!< Program Sequence Error on Bank 2      */
+#define HAL_FLASH_ERROR_STRB_BANK2   FLASH_FLAG_STRBERR_BANK2   /*!< Strobe Error on Bank 2                */
+#define HAL_FLASH_ERROR_INC_BANK2    FLASH_FLAG_INCERR_BANK2    /*!< Inconsistency Error on Bank 2         */
+#if defined (FLASH_SR_OPERR)
+#define HAL_FLASH_ERROR_OPE_BANK2    FLASH_FLAG_OPERR_BANK2     /*!< Operation Error on Bank 2             */
+#endif /* FLASH_SR_OPERR */
+#define HAL_FLASH_ERROR_RDP_BANK2    FLASH_FLAG_RDPERR_BANK2    /*!< Read Protection Error on Bank 2       */
+#define HAL_FLASH_ERROR_RDS_BANK2    FLASH_FLAG_RDSERR_BANK2    /*!< Read Secured Error on Bank 2          */
+#define HAL_FLASH_ERROR_SNECC_BANK2  FLASH_FLAG_SNECCERR_BANK2  /*!< ECC Single Correction Error on Bank 2 */
+#define HAL_FLASH_ERROR_DBECC_BANK2  FLASH_FLAG_DBECCERR_BANK2  /*!< ECC Double Detection Error on Bank 2  */
+#define HAL_FLASH_ERROR_CRCRD_BANK2  FLASH_FLAG_CRCRDERR_BANK2  /*!< CRC Read Error on Bank2               */
+
+#define HAL_FLASH_ERROR_OB_CHANGE    FLASH_OPTSR_OPTCHANGEERR   /*!< Option Byte Change Error              */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Type_Program FLASH Type Program
+  * @{
+  */
+#define FLASH_TYPEPROGRAM_FLASHWORD  0x01U        /*!< Program a flash word at a specified address */
+#if defined (FLASH_OPTCR_PG_OTP)
+#define FLASH_TYPEPROGRAM_OTPWORD    0x02U        /*!< Program an OTP word at a specified address  */
+#endif /* FLASH_OPTCR_PG_OTP */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Flag_definition FLASH Flag definition
+  * @brief Flag definition
+  * @{
+  */
+#define FLASH_FLAG_BSY                     FLASH_SR_BSY             /*!< FLASH Busy flag */
+#define FLASH_FLAG_WBNE                    FLASH_SR_WBNE            /*!< Write Buffer Not Empty flag */
+#define FLASH_FLAG_QW                      FLASH_SR_QW              /*!< Wait Queue on flag */
+#define FLASH_FLAG_CRC_BUSY                FLASH_SR_CRC_BUSY        /*!< CRC Busy flag */
+#define FLASH_FLAG_EOP                     FLASH_SR_EOP             /*!< End Of Program on flag */
+#define FLASH_FLAG_WRPERR                  FLASH_SR_WRPERR          /*!< Write Protection Error on flag */
+#define FLASH_FLAG_PGSERR                  FLASH_SR_PGSERR          /*!< Program Sequence Error on flag */
+#define FLASH_FLAG_STRBERR                 FLASH_SR_STRBERR         /*!< Strobe Error flag */
+#define FLASH_FLAG_INCERR                  FLASH_SR_INCERR          /*!< Inconsistency Error on flag */
+#if defined (FLASH_SR_OPERR)
+#define FLASH_FLAG_OPERR                   FLASH_SR_OPERR           /*!< Operation Error on flag */
+#endif /* FLASH_SR_OPERR */
+#define FLASH_FLAG_RDPERR                  FLASH_SR_RDPERR          /*!< Read Protection Error on flag */
+#define FLASH_FLAG_RDSERR                  FLASH_SR_RDSERR          /*!< Read Secured Error on flag */
+#define FLASH_FLAG_SNECCERR                FLASH_SR_SNECCERR        /*!< Single ECC Error Correction on flag */
+#define FLASH_FLAG_DBECCERR                FLASH_SR_DBECCERR        /*!< Double Detection ECC Error on flag */
+#define FLASH_FLAG_CRCEND                  FLASH_SR_CRCEND          /*!< CRC End of Calculation flag */
+#define FLASH_FLAG_CRCRDERR                FLASH_SR_CRCRDERR        /*!< CRC Read Error on bank flag */
+
+#define FLASH_FLAG_BSY_BANK1               FLASH_SR_BSY             /*!< FLASH Bank 1 Busy flag */
+#define FLASH_FLAG_WBNE_BANK1              FLASH_SR_WBNE            /*!< Write Buffer Not Empty on Bank 1 flag */
+#define FLASH_FLAG_QW_BANK1                FLASH_SR_QW              /*!< Wait Queue on Bank 1 flag */
+#define FLASH_FLAG_CRC_BUSY_BANK1          FLASH_SR_CRC_BUSY        /*!< CRC Busy on Bank 1 flag */
+#define FLASH_FLAG_EOP_BANK1               FLASH_SR_EOP             /*!< End Of Program on Bank 1 flag */
+#define FLASH_FLAG_WRPERR_BANK1            FLASH_SR_WRPERR          /*!< Write Protection Error on Bank 1 flag */
+#define FLASH_FLAG_PGSERR_BANK1            FLASH_SR_PGSERR          /*!< Program Sequence Error on Bank 1 flag */
+#define FLASH_FLAG_STRBERR_BANK1           FLASH_SR_STRBERR         /*!< Strobe Error on Bank 1 flag */
+#define FLASH_FLAG_INCERR_BANK1            FLASH_SR_INCERR          /*!< Inconsistency Error on Bank 1 flag */
+#if defined (FLASH_SR_OPERR)
+#define FLASH_FLAG_OPERR_BANK1             FLASH_SR_OPERR           /*!< Operation Error on Bank 1 flag */
+#endif /* FLASH_SR_OPERR */
+#define FLASH_FLAG_RDPERR_BANK1            FLASH_SR_RDPERR          /*!< Read Protection Error on Bank 1 flag */
+#define FLASH_FLAG_RDSERR_BANK1            FLASH_SR_RDSERR          /*!< Read Secured Error on Bank 1 flag */
+#define FLASH_FLAG_SNECCERR_BANK1          FLASH_SR_SNECCERR        /*!< Single ECC Error Correction on Bank 1 flag */
+#define FLASH_FLAG_DBECCERR_BANK1          FLASH_SR_DBECCERR        /*!< Double Detection ECC Error on Bank 1 flag */
+#define FLASH_FLAG_CRCEND_BANK1            FLASH_SR_CRCEND          /*!< CRC End of Calculation on Bank 1 flag */
+#define FLASH_FLAG_CRCRDERR_BANK1          FLASH_SR_CRCRDERR        /*!< CRC Read error on Bank 1 flag */
+
+#if defined (FLASH_SR_OPERR)
+#define FLASH_FLAG_ALL_ERRORS_BANK1       (FLASH_FLAG_WRPERR_BANK1   | FLASH_FLAG_PGSERR_BANK1   | \
+                                           FLASH_FLAG_STRBERR_BANK1  | FLASH_FLAG_INCERR_BANK1   | \
+                                           FLASH_FLAG_OPERR_BANK1    | FLASH_FLAG_RDPERR_BANK1   | \
+                                           FLASH_FLAG_RDSERR_BANK1   | FLASH_FLAG_SNECCERR_BANK1 | \
+                                           FLASH_FLAG_DBECCERR_BANK1 | FLASH_FLAG_CRCRDERR_BANK1) /*!< All Bank 1 error flags */
+#else
+#define FLASH_FLAG_ALL_ERRORS_BANK1       (FLASH_FLAG_WRPERR_BANK1   | FLASH_FLAG_PGSERR_BANK1   | \
+                                           FLASH_FLAG_STRBERR_BANK1  | FLASH_FLAG_INCERR_BANK1   | \
+                                           FLASH_FLAG_RDPERR_BANK1   | FLASH_FLAG_RDSERR_BANK1   | \
+                                           FLASH_FLAG_SNECCERR_BANK1 | FLASH_FLAG_DBECCERR_BANK1 | \
+                                           FLASH_FLAG_CRCRDERR_BANK1) /*!< All Bank 1 error flags */
+#endif /* FLASH_SR_OPERR */
+
+#define FLASH_FLAG_ALL_BANK1              (FLASH_FLAG_BSY_BANK1      | FLASH_FLAG_WBNE_BANK1     | \
+                                           FLASH_FLAG_QW_BANK1       | FLASH_FLAG_CRC_BUSY_BANK1 | \
+                                           FLASH_FLAG_EOP_BANK1      | FLASH_FLAG_CRCEND_BANK1   | \
+                                           FLASH_FLAG_ALL_ERRORS_BANK1) /*!< All Bank 1 flags */
+
+#define FLASH_FLAG_BSY_BANK2               (FLASH_SR_BSY      | 0x80000000U)        /*!< FLASH Bank 2 Busy flag */
+#define FLASH_FLAG_WBNE_BANK2              (FLASH_SR_WBNE     | 0x80000000U)        /*!< Write Buffer Not Empty on Bank 2 flag */
+#define FLASH_FLAG_QW_BANK2                (FLASH_SR_QW       | 0x80000000U)        /*!< Wait Queue on Bank 2 flag */
+#define FLASH_FLAG_CRC_BUSY_BANK2          (FLASH_SR_CRC_BUSY | 0x80000000U)        /*!< CRC Busy on Bank 2 flag */
+#define FLASH_FLAG_EOP_BANK2               (FLASH_SR_EOP      | 0x80000000U)        /*!< End Of Program on Bank 2 flag */
+#define FLASH_FLAG_WRPERR_BANK2            (FLASH_SR_WRPERR   | 0x80000000U)        /*!< Write Protection Error on Bank 2 flag */
+#define FLASH_FLAG_PGSERR_BANK2            (FLASH_SR_PGSERR   | 0x80000000U)        /*!< Program Sequence Error on Bank 2 flag */
+#define FLASH_FLAG_STRBERR_BANK2           (FLASH_SR_STRBERR  | 0x80000000U)        /*!< Strobe Error on Bank 2 flag */
+#define FLASH_FLAG_INCERR_BANK2            (FLASH_SR_INCERR   | 0x80000000U)        /*!< Inconsistency Error on Bank 2 flag */
+#if defined (FLASH_SR_OPERR)
+#define FLASH_FLAG_OPERR_BANK2             (FLASH_SR_OPERR    | 0x80000000U)        /*!< Operation Error on Bank 2 flag */
+#endif /* FLASH_SR_OPERR */
+#define FLASH_FLAG_RDPERR_BANK2            (FLASH_SR_RDPERR   | 0x80000000U)        /*!< Read Protection Error on Bank 2 flag */
+#define FLASH_FLAG_RDSERR_BANK2            (FLASH_SR_RDSERR   | 0x80000000U)        /*!< Read Secured Error on Bank 2 flag */
+#define FLASH_FLAG_SNECCERR_BANK2          (FLASH_SR_SNECCERR | 0x80000000U)        /*!< Single ECC Error Correction on Bank 2 flag */
+#define FLASH_FLAG_DBECCERR_BANK2          (FLASH_SR_DBECCERR | 0x80000000U)        /*!< Double Detection ECC Error on Bank 2 flag */
+#define FLASH_FLAG_CRCEND_BANK2            (FLASH_SR_CRCEND   | 0x80000000U)        /*!< CRC End of Calculation on Bank 2 flag */
+#define FLASH_FLAG_CRCRDERR_BANK2          (FLASH_SR_CRCRDERR | 0x80000000U)        /*!< CRC Read error on Bank 2 flag */
+
+#if defined (FLASH_SR_OPERR)
+#define FLASH_FLAG_ALL_ERRORS_BANK2       (FLASH_FLAG_WRPERR_BANK2   | FLASH_FLAG_PGSERR_BANK2   | \
+                                           FLASH_FLAG_STRBERR_BANK2  | FLASH_FLAG_INCERR_BANK2   | \
+                                           FLASH_FLAG_OPERR_BANK2    | FLASH_FLAG_RDPERR_BANK2   | \
+                                           FLASH_FLAG_RDSERR_BANK2   | FLASH_FLAG_SNECCERR_BANK2 | \
+                                           FLASH_FLAG_DBECCERR_BANK2 | FLASH_FLAG_CRCRDERR_BANK2) /*!< All Bank 2 error flags */
+#else
+#define FLASH_FLAG_ALL_ERRORS_BANK2       (FLASH_FLAG_WRPERR_BANK2   | FLASH_FLAG_PGSERR_BANK2   | \
+                                           FLASH_FLAG_STRBERR_BANK2  | FLASH_FLAG_INCERR_BANK2   | \
+                                           FLASH_FLAG_RDPERR_BANK2   | FLASH_FLAG_RDSERR_BANK2   | \
+                                           FLASH_FLAG_SNECCERR_BANK2 | FLASH_FLAG_DBECCERR_BANK2 | \
+                                           FLASH_FLAG_CRCRDERR_BANK2) /*!< All Bank 2 error flags */
+#endif /* FLASH_SR_OPERR */
+
+#define FLASH_FLAG_ALL_BANK2              (FLASH_FLAG_BSY_BANK2      | FLASH_FLAG_WBNE_BANK2     | \
+                                           FLASH_FLAG_QW_BANK2       | FLASH_FLAG_CRC_BUSY_BANK2 | \
+                                           FLASH_FLAG_EOP_BANK2      | FLASH_FLAG_CRCEND_BANK2   | \
+                                           FLASH_FLAG_ALL_ERRORS_BANK2) /*!< All Bank 2 flags */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition
+  * @brief FLASH Interrupt definition
+  * @{
+  */
+#define FLASH_IT_EOP_BANK1                  FLASH_CR_EOPIE       /*!< End of FLASH Bank 1 Operation Interrupt source */
+#define FLASH_IT_WRPERR_BANK1               FLASH_CR_WRPERRIE    /*!< Write Protection Error on Bank 1 Interrupt source */
+#define FLASH_IT_PGSERR_BANK1               FLASH_CR_PGSERRIE    /*!< Program Sequence Error on Bank 1 Interrupt source */
+#define FLASH_IT_STRBERR_BANK1              FLASH_CR_STRBERRIE   /*!< Strobe Error on Bank 1 Interrupt source */
+#define FLASH_IT_INCERR_BANK1               FLASH_CR_INCERRIE    /*!< Inconsistency Error on Bank 1 Interrupt source */
+#if defined (FLASH_CR_OPERRIE)
+#define FLASH_IT_OPERR_BANK1                FLASH_CR_OPERRIE     /*!< Operation Error on Bank 1 Interrupt source */
+#endif /* FLASH_CR_OPERRIE */
+#define FLASH_IT_RDPERR_BANK1               FLASH_CR_RDPERRIE    /*!< Read protection Error on Bank 1 Interrupt source */
+#define FLASH_IT_RDSERR_BANK1               FLASH_CR_RDSERRIE    /*!< Read Secured Error on Bank 1 Interrupt source */
+#define FLASH_IT_SNECCERR_BANK1             FLASH_CR_SNECCERRIE  /*!< Single ECC Error Correction on Bank 1 Interrupt source */
+#define FLASH_IT_DBECCERR_BANK1             FLASH_CR_DBECCERRIE  /*!< Double Detection ECC Error on Bank 1 Interrupt source */
+#define FLASH_IT_CRCEND_BANK1               FLASH_CR_CRCENDIE    /*!< CRC End on Bank 1 Interrupt source */
+#define FLASH_IT_CRCRDERR_BANK1             FLASH_CR_CRCRDERRIE  /*!< CRC Read error on Bank 1 Interrupt source */
+
+#if defined (FLASH_CR_OPERRIE)
+#define FLASH_IT_ALL_BANK1                 (FLASH_IT_EOP_BANK1       | FLASH_IT_WRPERR_BANK1    | \
+                                            FLASH_IT_PGSERR_BANK1    | FLASH_IT_STRBERR_BANK1   | \
+                                            FLASH_IT_INCERR_BANK1    | FLASH_IT_OPERR_BANK1     | \
+                                            FLASH_IT_RDPERR_BANK1    | FLASH_IT_RDSERR_BANK1    | \
+                                            FLASH_IT_SNECCERR_BANK1  | FLASH_IT_DBECCERR_BANK1  | \
+                                            FLASH_IT_CRCEND_BANK1    | FLASH_IT_CRCRDERR_BANK1) /*!< All Bank 1 Interrupt sources */
+#else
+#define FLASH_IT_ALL_BANK1                 (FLASH_IT_EOP_BANK1       | FLASH_IT_WRPERR_BANK1    | \
+                                            FLASH_IT_PGSERR_BANK1    | FLASH_IT_STRBERR_BANK1   | \
+                                            FLASH_IT_INCERR_BANK1    | FLASH_IT_RDPERR_BANK1    | \
+                                            FLASH_IT_RDSERR_BANK1    | FLASH_IT_SNECCERR_BANK1  | \
+                                            FLASH_IT_DBECCERR_BANK1  | FLASH_IT_CRCEND_BANK1    | \
+                                            FLASH_IT_CRCRDERR_BANK1) /*!< All Bank 1 Interrupt sources */
+#endif /* FLASH_CR_OPERRIE */
+
+#define FLASH_IT_EOP_BANK2                 (FLASH_CR_EOPIE      | 0x80000000U)  /*!< End of FLASH Bank 2 Operation Interrupt source */
+#define FLASH_IT_WRPERR_BANK2              (FLASH_CR_WRPERRIE   | 0x80000000U)  /*!< Write Protection Error on Bank 2 Interrupt source */
+#define FLASH_IT_PGSERR_BANK2              (FLASH_CR_PGSERRIE   | 0x80000000U)  /*!< Program Sequence Error on Bank 2 Interrupt source */
+#define FLASH_IT_STRBERR_BANK2             (FLASH_CR_STRBERRIE  | 0x80000000U)  /*!< Strobe Error on Bank 2 Interrupt source */
+#define FLASH_IT_INCERR_BANK2              (FLASH_CR_INCERRIE   | 0x80000000U)  /*!< Inconsistency Error on Bank 2 Interrupt source */
+#if defined (FLASH_CR_OPERRIE)
+#define FLASH_IT_OPERR_BANK2               (FLASH_CR_OPERRIE    | 0x80000000U)  /*!< Operation Error on Bank 2 Interrupt source */
+#endif /* FLASH_CR_OPERRIE */
+#define FLASH_IT_RDPERR_BANK2              (FLASH_CR_RDPERRIE   | 0x80000000U)  /*!< Read protection Error on Bank 2 Interrupt source */
+#define FLASH_IT_RDSERR_BANK2              (FLASH_CR_RDSERRIE   | 0x80000000U)  /*!< Read Secured Error on Bank 2 Interrupt source */
+#define FLASH_IT_SNECCERR_BANK2            (FLASH_CR_SNECCERRIE | 0x80000000U)  /*!< Single ECC Error Correction on Bank 2 Interrupt source */
+#define FLASH_IT_DBECCERR_BANK2            (FLASH_CR_DBECCERRIE | 0x80000000U)  /*!< Double Detection ECC Error on Bank 2 Interrupt source */
+#define FLASH_IT_CRCEND_BANK2              (FLASH_CR_CRCENDIE   | 0x80000000U)  /*!< CRC End on Bank 2 Interrupt source */
+#define FLASH_IT_CRCRDERR_BANK2            (FLASH_CR_CRCRDERRIE | 0x80000000U)  /*!< CRC Read Error on Bank 2 Interrupt source */
+
+#if defined (FLASH_CR_OPERRIE)
+#define FLASH_IT_ALL_BANK2                 (FLASH_IT_EOP_BANK2       | FLASH_IT_WRPERR_BANK2    | \
+                                            FLASH_IT_PGSERR_BANK2    | FLASH_IT_STRBERR_BANK2   | \
+                                            FLASH_IT_INCERR_BANK2    | FLASH_IT_OPERR_BANK2     | \
+                                            FLASH_IT_RDPERR_BANK2    | FLASH_IT_RDSERR_BANK2    | \
+                                            FLASH_IT_SNECCERR_BANK2  | FLASH_IT_DBECCERR_BANK2  | \
+                                            FLASH_IT_CRCEND_BANK2    | FLASH_IT_CRCRDERR_BANK2) /*!< All Bank 2 Interrupt sources */
+#else
+#define FLASH_IT_ALL_BANK2                 (FLASH_IT_EOP_BANK2       | FLASH_IT_WRPERR_BANK2    | \
+                                            FLASH_IT_PGSERR_BANK2    | FLASH_IT_STRBERR_BANK2   | \
+                                            FLASH_IT_INCERR_BANK2    | FLASH_IT_RDPERR_BANK2    | \
+                                            FLASH_IT_RDSERR_BANK2    | FLASH_IT_SNECCERR_BANK2  | \
+                                            FLASH_IT_DBECCERR_BANK2  | FLASH_IT_CRCEND_BANK2    | \
+                                            FLASH_IT_CRCRDERR_BANK2) /*!< All Bank 2 Interrupt sources */
+#endif /* FLASH_CR_OPERRIE */
+/**
+  * @}
+  */
+
+#if defined (FLASH_CR_PSIZE)
+/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism
+  * @{
+  */
+#define FLASH_PSIZE_BYTE           0x00000000U       /*!< Flash program/erase by 8 bits  */
+#define FLASH_PSIZE_HALF_WORD      FLASH_CR_PSIZE_0  /*!< Flash program/erase by 16 bits */
+#define FLASH_PSIZE_WORD           FLASH_CR_PSIZE_1  /*!< Flash program/erase by 32 bits */
+#define FLASH_PSIZE_DOUBLE_WORD    FLASH_CR_PSIZE    /*!< Flash program/erase by 64 bits */
+/**
+  * @}
+  */
+#endif /* FLASH_CR_PSIZE */
+
+
+/** @defgroup FLASH_Keys FLASH Keys
+  * @{
+  */
+#define FLASH_KEY1                 0x45670123U
+#define FLASH_KEY2                 0xCDEF89ABU
+#define FLASH_OPT_KEY1             0x08192A3BU
+#define FLASH_OPT_KEY2             0x4C5D6E7FU
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Sectors FLASH Sectors
+  * @{
+  */
+#define FLASH_SECTOR_0             0U       /*!< Sector Number 0   */
+#define FLASH_SECTOR_1             1U       /*!< Sector Number 1   */
+#define FLASH_SECTOR_2             2U       /*!< Sector Number 2   */
+#define FLASH_SECTOR_3             3U       /*!< Sector Number 3   */
+#define FLASH_SECTOR_4             4U       /*!< Sector Number 4   */
+#define FLASH_SECTOR_5             5U       /*!< Sector Number 5   */
+#define FLASH_SECTOR_6             6U       /*!< Sector Number 6   */
+#define FLASH_SECTOR_7             7U       /*!< Sector Number 7   */
+#if (FLASH_SECTOR_TOTAL == 128)
+#define FLASH_SECTOR_8             8U       /*!< Sector Number 8   */
+#define FLASH_SECTOR_9             9U       /*!< Sector Number 9   */
+#define FLASH_SECTOR_10            10U      /*!< Sector Number 10  */
+#define FLASH_SECTOR_11            11U      /*!< Sector Number 11  */
+#define FLASH_SECTOR_12            12U      /*!< Sector Number 12  */
+#define FLASH_SECTOR_13            13U      /*!< Sector Number 13  */
+#define FLASH_SECTOR_14            14U      /*!< Sector Number 14  */
+#define FLASH_SECTOR_15            15U      /*!< Sector Number 15  */
+#define FLASH_SECTOR_16            16U      /*!< Sector Number 16  */
+#define FLASH_SECTOR_17            17U      /*!< Sector Number 17  */
+#define FLASH_SECTOR_18            18U      /*!< Sector Number 18  */
+#define FLASH_SECTOR_19            19U      /*!< Sector Number 19  */
+#define FLASH_SECTOR_20            20U      /*!< Sector Number 20  */
+#define FLASH_SECTOR_21            21U      /*!< Sector Number 21  */
+#define FLASH_SECTOR_22            22U      /*!< Sector Number 22  */
+#define FLASH_SECTOR_23            23U      /*!< Sector Number 23  */
+#define FLASH_SECTOR_24            24U      /*!< Sector Number 24  */
+#define FLASH_SECTOR_25            25U      /*!< Sector Number 25  */
+#define FLASH_SECTOR_26            26U      /*!< Sector Number 26  */
+#define FLASH_SECTOR_27            27U      /*!< Sector Number 27  */
+#define FLASH_SECTOR_28            28U      /*!< Sector Number 28  */
+#define FLASH_SECTOR_29            29U      /*!< Sector Number 29  */
+#define FLASH_SECTOR_30            30U      /*!< Sector Number 30  */
+#define FLASH_SECTOR_31            31U      /*!< Sector Number 31  */
+#define FLASH_SECTOR_32            32U      /*!< Sector Number 32  */
+#define FLASH_SECTOR_33            33U      /*!< Sector Number 33  */
+#define FLASH_SECTOR_34            34U      /*!< Sector Number 34  */
+#define FLASH_SECTOR_35            35U      /*!< Sector Number 35  */
+#define FLASH_SECTOR_36            36U      /*!< Sector Number 36  */
+#define FLASH_SECTOR_37            37U      /*!< Sector Number 37  */
+#define FLASH_SECTOR_38            38U      /*!< Sector Number 38  */
+#define FLASH_SECTOR_39            39U      /*!< Sector Number 39  */
+#define FLASH_SECTOR_40            40U      /*!< Sector Number 40  */
+#define FLASH_SECTOR_41            41U      /*!< Sector Number 41  */
+#define FLASH_SECTOR_42            42U      /*!< Sector Number 42  */
+#define FLASH_SECTOR_43            43U      /*!< Sector Number 43  */
+#define FLASH_SECTOR_44            44U      /*!< Sector Number 44  */
+#define FLASH_SECTOR_45            45U      /*!< Sector Number 45  */
+#define FLASH_SECTOR_46            46U      /*!< Sector Number 46  */
+#define FLASH_SECTOR_47            47U      /*!< Sector Number 47  */
+#define FLASH_SECTOR_48            48U      /*!< Sector Number 48  */
+#define FLASH_SECTOR_49            49U      /*!< Sector Number 49  */
+#define FLASH_SECTOR_50            50U      /*!< Sector Number 50  */
+#define FLASH_SECTOR_51            51U      /*!< Sector Number 51  */
+#define FLASH_SECTOR_52            52U      /*!< Sector Number 52  */
+#define FLASH_SECTOR_53            53U      /*!< Sector Number 53  */
+#define FLASH_SECTOR_54            54U      /*!< Sector Number 54  */
+#define FLASH_SECTOR_55            55U      /*!< Sector Number 55  */
+#define FLASH_SECTOR_56            56U      /*!< Sector Number 56  */
+#define FLASH_SECTOR_57            57U      /*!< Sector Number 57  */
+#define FLASH_SECTOR_58            58U      /*!< Sector Number 58  */
+#define FLASH_SECTOR_59            59U      /*!< Sector Number 59  */
+#define FLASH_SECTOR_60            60U      /*!< Sector Number 60  */
+#define FLASH_SECTOR_61            61U      /*!< Sector Number 61  */
+#define FLASH_SECTOR_62            62U      /*!< Sector Number 62  */
+#define FLASH_SECTOR_63            63U      /*!< Sector Number 63  */
+#define FLASH_SECTOR_64            64U      /*!< Sector Number 64  */
+#define FLASH_SECTOR_65            65U      /*!< Sector Number 65  */
+#define FLASH_SECTOR_66            66U      /*!< Sector Number 66  */
+#define FLASH_SECTOR_67            67U      /*!< Sector Number 67  */
+#define FLASH_SECTOR_68            68U      /*!< Sector Number 68  */
+#define FLASH_SECTOR_69            69U      /*!< Sector Number 69  */
+#define FLASH_SECTOR_70            70U      /*!< Sector Number 70  */
+#define FLASH_SECTOR_71            71U      /*!< Sector Number 71  */
+#define FLASH_SECTOR_72            72U      /*!< Sector Number 72  */
+#define FLASH_SECTOR_73            73U      /*!< Sector Number 73  */
+#define FLASH_SECTOR_74            74U      /*!< Sector Number 74  */
+#define FLASH_SECTOR_75            75U      /*!< Sector Number 75  */
+#define FLASH_SECTOR_76            76U      /*!< Sector Number 76  */
+#define FLASH_SECTOR_77            77U      /*!< Sector Number 77  */
+#define FLASH_SECTOR_78            78U      /*!< Sector Number 78  */
+#define FLASH_SECTOR_79            79U      /*!< Sector Number 79  */
+#define FLASH_SECTOR_80            80U      /*!< Sector Number 80  */
+#define FLASH_SECTOR_81            81U      /*!< Sector Number 81  */
+#define FLASH_SECTOR_82            82U      /*!< Sector Number 82  */
+#define FLASH_SECTOR_83            83U      /*!< Sector Number 83  */
+#define FLASH_SECTOR_84            84U      /*!< Sector Number 84  */
+#define FLASH_SECTOR_85            85U      /*!< Sector Number 85  */
+#define FLASH_SECTOR_86            86U      /*!< Sector Number 86  */
+#define FLASH_SECTOR_87            87U      /*!< Sector Number 87  */
+#define FLASH_SECTOR_88            88U      /*!< Sector Number 88  */
+#define FLASH_SECTOR_89            89U      /*!< Sector Number 89  */
+#define FLASH_SECTOR_90            90U      /*!< Sector Number 90  */
+#define FLASH_SECTOR_91            91U      /*!< Sector Number 91  */
+#define FLASH_SECTOR_92            92U      /*!< Sector Number 92  */
+#define FLASH_SECTOR_93            93U      /*!< Sector Number 93  */
+#define FLASH_SECTOR_94            94U      /*!< Sector Number 94  */
+#define FLASH_SECTOR_95            95U      /*!< Sector Number 95  */
+#define FLASH_SECTOR_96            96U      /*!< Sector Number 96  */
+#define FLASH_SECTOR_97            97U      /*!< Sector Number 97  */
+#define FLASH_SECTOR_98            98U      /*!< Sector Number 98  */
+#define FLASH_SECTOR_99            99U      /*!< Sector Number 99  */
+#define FLASH_SECTOR_100           100U     /*!< Sector Number 100 */
+#define FLASH_SECTOR_101           101U     /*!< Sector Number 101 */
+#define FLASH_SECTOR_102           102U     /*!< Sector Number 102 */
+#define FLASH_SECTOR_103           103U     /*!< Sector Number 103 */
+#define FLASH_SECTOR_104           104U     /*!< Sector Number 104 */
+#define FLASH_SECTOR_105           105U     /*!< Sector Number 105 */
+#define FLASH_SECTOR_106           106U     /*!< Sector Number 106 */
+#define FLASH_SECTOR_107           107U     /*!< Sector Number 107 */
+#define FLASH_SECTOR_108           108U     /*!< Sector Number 108 */
+#define FLASH_SECTOR_109           109U     /*!< Sector Number 109 */
+#define FLASH_SECTOR_110           110U     /*!< Sector Number 110 */
+#define FLASH_SECTOR_111           111U     /*!< Sector Number 111 */
+#define FLASH_SECTOR_112           112U     /*!< Sector Number 112 */
+#define FLASH_SECTOR_113           113U     /*!< Sector Number 113 */
+#define FLASH_SECTOR_114           114U     /*!< Sector Number 114 */
+#define FLASH_SECTOR_115           115U     /*!< Sector Number 115 */
+#define FLASH_SECTOR_116           116U     /*!< Sector Number 116 */
+#define FLASH_SECTOR_117           117U     /*!< Sector Number 117 */
+#define FLASH_SECTOR_118           118U     /*!< Sector Number 118 */
+#define FLASH_SECTOR_119           119U     /*!< Sector Number 119 */
+#define FLASH_SECTOR_120           120U     /*!< Sector Number 120 */
+#define FLASH_SECTOR_121           121U     /*!< Sector Number 121 */
+#define FLASH_SECTOR_122           122U     /*!< Sector Number 122 */
+#define FLASH_SECTOR_123           123U     /*!< Sector Number 123 */
+#define FLASH_SECTOR_124           124U     /*!< Sector Number 124 */
+#define FLASH_SECTOR_125           125U     /*!< Sector Number 125 */
+#define FLASH_SECTOR_126           126U     /*!< Sector Number 126 */
+#define FLASH_SECTOR_127           127U     /*!< Sector Number 127 */
+#endif /* FLASH_SECTOR_TOTAL == 128 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
+  * @{
+  */
+/**
+  * @brief  Set the FLASH Latency.
+  * @param  __LATENCY__: FLASH Latency
+  *         The value of this parameter depend on device used within the same series
+  * @retval none
+  */
+#define __HAL_FLASH_SET_LATENCY(__LATENCY__) \
+                  MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__))
+
+/**
+  * @brief  Get the FLASH Latency.
+  * @retval FLASH Latency
+  *          The value of this parameter depend on device used within the same series
+  */
+#define __HAL_FLASH_GET_LATENCY()     (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
+
+/**
+  * @brief  Enable the specified FLASH interrupt.
+  * @param  __INTERRUPT__ : FLASH interrupt
+  *   In case of Bank 1 This parameter can be any combination of the following values:
+  *     @arg FLASH_IT_EOP_BANK1       : End of FLASH Bank 1 Operation Interrupt source
+  *     @arg FLASH_IT_WRPERR_BANK1    : Write Protection Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_PGSERR_BANK1    : Program Sequence Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_STRBERR_BANK1   : Strobe Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_INCERR_BANK1    : Inconsistency Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_OPERR_BANK1     : Operation Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_RDPERR_BANK1    : Read protection Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_RDSERR_BANK1    : Read secure Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_SNECCERR_BANK1  : Single ECC Error Correction on Bank 1 Interrupt source
+  *     @arg FLASH_IT_DBECCERR_BANK1  : Double Detection ECC Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_CRCEND_BANK1    : CRC End on Bank 1 Interrupt source
+  *     @arg FLASH_IT_CRCRDERR_BANK1  : CRC Read error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_ALL_BANK1       : All Bank 1 Interrupt sources
+  *
+  *   In case of Bank 2, this parameter can be any combination of the following values:
+  *     @arg FLASH_IT_EOP_BANK2       : End of FLASH Bank 2 Operation Interrupt source
+  *     @arg FLASH_IT_WRPERR_BANK2    : Write Protection Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_PGSERR_BANK2    : Program Sequence Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_STRBERR_BANK2   : Strobe Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_INCERR_BANK2    : Inconsistency Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_OPERR_BANK2     : Operation Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_RDPERR_BANK2    : Read protection Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_RDSERR_BANK2    : Read secure Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_SNECCERR_BANK2  : Single ECC Error Correction on Bank 2 Interrupt source
+  *     @arg FLASH_IT_DBECCERR_BANK2  : Double Detection ECC Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_CRCEND_BANK2    : CRC End on Bank 2 Interrupt source
+  *     @arg FLASH_IT_CRCRDERR_BANK2  : CRC Read error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_ALL_BANK2       : All Bank 2 Interrupt sources
+  * @retval none
+  */
+
+#define __HAL_FLASH_ENABLE_IT_BANK1(__INTERRUPT__)      (FLASH->CR1 |= (__INTERRUPT__))
+
+#define __HAL_FLASH_ENABLE_IT_BANK2(__INTERRUPT__)      (FLASH->CR2 |= ((__INTERRUPT__) & 0x7FFFFFFFU))
+
+#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)    (IS_FLASH_IT_BANK1(__INTERRUPT__) ? \
+                                                 __HAL_FLASH_ENABLE_IT_BANK1(__INTERRUPT__) : \
+                                                 __HAL_FLASH_ENABLE_IT_BANK2(__INTERRUPT__))
+
+
+/**
+  * @brief  Disable the specified FLASH interrupt.
+  * @param  __INTERRUPT__ : FLASH interrupt
+  *   In case of Bank 1 This parameter can be any combination of the following values:
+  *     @arg FLASH_IT_EOP_BANK1       : End of FLASH Bank 1 Operation Interrupt source
+  *     @arg FLASH_IT_WRPERR_BANK1    : Write Protection Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_PGSERR_BANK1    : Program Sequence Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_STRBERR_BANK1   : Strobe Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_INCERR_BANK1    : Inconsistency Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_OPERR_BANK1     : Operation Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_RDPERR_BANK1    : Read protection Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_RDSERR_BANK1    : Read secure Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_SNECCERR_BANK1  : Single ECC Error Correction on Bank 1 Interrupt source
+  *     @arg FLASH_IT_DBECCERR_BANK1  : Double Detection ECC Error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_CRCEND_BANK1    : CRC End on Bank 1 Interrupt source
+  *     @arg FLASH_IT_CRCRDERR_BANK1  : CRC Read error on Bank 1 Interrupt source
+  *     @arg FLASH_IT_ALL_BANK1       : All Bank 1 Interrupt sources
+  *
+  *   In case of Bank 2, this parameter can be any combination of the following values:
+  *     @arg FLASH_IT_EOP_BANK2       : End of FLASH Bank 2 Operation Interrupt source
+  *     @arg FLASH_IT_WRPERR_BANK2    : Write Protection Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_PGSERR_BANK2    : Program Sequence Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_STRBERR_BANK2   : Strobe Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_INCERR_BANK2    : Inconsistency Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_OPERR_BANK2     : Operation Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_RDPERR_BANK2    : Read protection Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_RDSERR_BANK2    : Read secure Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_SNECCERR_BANK2  : Single ECC Error Correction on Bank 2 Interrupt source
+  *     @arg FLASH_IT_DBECCERR_BANK2  : Double Detection ECC Error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_CRCEND_BANK2    : CRC End on Bank 2 Interrupt source
+  *     @arg FLASH_IT_CRCRDERR_BANK2  : CRC Read error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_ALL_BANK2       : All Bank 2 Interrupt sources
+  * @retval none
+  */
+
+#define __HAL_FLASH_DISABLE_IT_BANK1(__INTERRUPT__)  (FLASH->CR1 &= ~(uint32_t)(__INTERRUPT__))
+
+#define __HAL_FLASH_DISABLE_IT_BANK2(__INTERRUPT__)  (FLASH->CR2 &= ~(uint32_t)((__INTERRUPT__) & 0x7FFFFFFFU))
+
+#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)  (IS_FLASH_IT_BANK1(__INTERRUPT__) ? \
+                                                __HAL_FLASH_DISABLE_IT_BANK1(__INTERRUPT__) : \
+                                                __HAL_FLASH_DISABLE_IT_BANK2(__INTERRUPT__))
+
+
+/**
+  * @brief  Checks whether the specified FLASH flag is set or not.
+  * @param  __FLAG__: specifies the FLASH flag to check.
+  *   In case of Bank 1 This parameter can be one of the following values :
+  *     @arg FLASH_FLAG_BSY_BANK1      : FLASH Bank 1 Busy flag
+  *     @arg FLASH_FLAG_WBNE_BANK1     : Write Buffer Not Empty on Bank 1 flag
+  *     @arg FLASH_FLAG_QW_BANK1       : Wait Queue on Bank 1 flag
+  *     @arg FLASH_FLAG_CRC_BUSY_BANK1 : CRC module is working on Bank 1 flag
+  *     @arg FLASH_FLAG_EOP_BANK1      : End Of Program on Bank 1 flag
+  *     @arg FLASH_FLAG_WRPERR_BANK1   : Write Protection Error on Bank 1 flag
+  *     @arg FLASH_FLAG_PGSERR_BANK1   : Program Sequence Error on Bank 1 flag
+  *     @arg FLASH_FLAG_STRBER_BANK1   : Program Alignment Error on Bank 1 flag
+  *     @arg FLASH_FLAG_INCERR_BANK1   : Inconsistency Error on Bank 1 flag
+  *     @arg FLASH_FLAG_OPERR_BANK1    : Operation Error on Bank 1 flag
+  *     @arg FLASH_FLAG_RDPERR_BANK1   : Read Protection Error on Bank 1 flag
+  *     @arg FLASH_FLAG_RDSERR_BANK1   : Read secure  Error on Bank 1 flag
+  *     @arg FLASH_FLAG_SNECCE_BANK1   : Single ECC Error Correction on Bank 1 flag
+  *     @arg FLASH_FLAG_DBECCE_BANK1   : Double Detection ECC Error on Bank 1 flag
+  *     @arg FLASH_FLAG_CRCEND_BANK1   : CRC End on Bank 1 flag
+  *     @arg FLASH_FLAG_CRCRDERR_BANK1 : CRC Read error on Bank 1 flag
+  *
+  *   In case of Bank 2 This parameter can be one of the following values :
+  *     @arg FLASH_FLAG_BSY_BANK2      : FLASH Bank 2 Busy flag
+  *     @arg FLASH_FLAG_WBNE_BANK2     : Write Buffer Not Empty on Bank 2 flag
+  *     @arg FLASH_FLAG_QW_BANK2       : Wait Queue on Bank 2 flag
+  *     @arg FLASH_FLAG_CRC_BUSY_BANK2 : CRC module is working on Bank 2 flag
+  *     @arg FLASH_FLAG_EOP_BANK2      : End Of Program on Bank 2 flag
+  *     @arg FLASH_FLAG_WRPERR_BANK2   : Write Protection Error on Bank 2 flag
+  *     @arg FLASH_FLAG_PGSERR_BANK2   : Program Sequence Error on Bank 2 flag
+  *     @arg FLASH_FLAG_STRBER_BANK2   : Program Alignment Error on Bank 2 flag
+  *     @arg FLASH_FLAG_INCERR_BANK2   : Inconsistency Error on Bank 2 flag
+  *     @arg FLASH_FLAG_OPERR_BANK2    : Operation Error on Bank 2 flag
+  *     @arg FLASH_FLAG_RDPERR_BANK2   : Read Protection Error on Bank 2 flag
+  *     @arg FLASH_FLAG_RDSERR_BANK2   : Read secure  Error on Bank 2 flag
+  *     @arg FLASH_FLAG_SNECCE_BANK2   : Single ECC Error Correction on Bank 2 flag
+  *     @arg FLASH_FLAG_DBECCE_BANK2   : Double Detection ECC Error on Bank 2 flag
+  *     @arg FLASH_FLAG_CRCEND_BANK2   : CRC End on Bank 2 flag
+  *     @arg FLASH_FLAG_CRCRDERR_BANK2 : CRC Read error on Bank 2 flag
+  * @retval The new state of FLASH_FLAG (SET or RESET).
+  */
+#define __HAL_FLASH_GET_FLAG_BANK1(__FLAG__)     (READ_BIT(FLASH->SR1, (__FLAG__)) == (__FLAG__))
+
+#define __HAL_FLASH_GET_FLAG_BANK2(__FLAG__)     (READ_BIT(FLASH->SR2, ((__FLAG__) & 0x7FFFFFFFU)) == (((__FLAG__) & 0x7FFFFFFFU)))
+
+#define __HAL_FLASH_GET_FLAG(__FLAG__)           (IS_FLASH_FLAG_BANK1(__FLAG__) ?  __HAL_FLASH_GET_FLAG_BANK1(__FLAG__) : \
+                                                  __HAL_FLASH_GET_FLAG_BANK2(__FLAG__))
+
+
+/**
+  * @brief  Clear the specified FLASH flag.
+  * @param  __FLAG__: specifies the FLASH flags to clear.
+  *    In case of Bank 1, this parameter can be any combination of the following values:
+  *     @arg FLASH_FLAG_EOP_BANK1        : End Of Program on Bank 1 flag
+  *     @arg FLASH_FLAG_WRPERR_BANK1     : Write Protection Error on Bank 1 flag
+  *     @arg FLASH_FLAG_PGSERR_BANK1     : Program Sequence Error on Bank 1 flag
+  *     @arg FLASH_FLAG_STRBER_BANK1     : Program Alignment Error on Bank 1 flag
+  *     @arg FLASH_FLAG_INCERR_BANK1     : Inconsistency Error on Bank 1 flag
+  *     @arg FLASH_FLAG_OPERR_BANK1      : Operation Error on Bank 1 flag
+  *     @arg FLASH_FLAG_RDPERR_BANK1     : Read Protection Error on Bank 1 flag
+  *     @arg FLASH_FLAG_RDSERR_BANK1     : Read secure  Error on Bank 1 flag
+  *     @arg FLASH_FLAG_SNECCE_BANK1     : Single ECC Error Correction on Bank 1 flag
+  *     @arg FLASH_FLAG_DBECCE_BANK1     : Double Detection ECC Error on Bank 1 flag
+  *     @arg FLASH_FLAG_CRCEND_BANK1     : CRC End on Bank 1 flag
+  *     @arg FLASH_FLAG_CRCRDERR_BANK1   : CRC Read error on Bank 1 flag
+  *     @arg FLASH_FLAG_ALL_ERRORS_BANK1 : All Bank 1 error flags
+  *     @arg FLASH_FLAG_ALL_BANK1        : All Bank 1 flags
+  *
+  *   In case of Bank 2, this parameter can be any combination of the following values :
+  *     @arg FLASH_FLAG_EOP_BANK2        : End Of Program on Bank 2 flag
+  *     @arg FLASH_FLAG_WRPERR_BANK2     : Write Protection Error on Bank 2 flag
+  *     @arg FLASH_FLAG_PGSERR_BANK2     : Program Sequence Error on Bank 2 flag
+  *     @arg FLASH_FLAG_STRBER_BANK2     : Program Alignment Error on Bank 2 flag
+  *     @arg FLASH_FLAG_INCERR_BANK2     : Inconsistency Error on Bank 2 flag
+  *     @arg FLASH_FLAG_OPERR_BANK2      : Operation Error on Bank 2 flag
+  *     @arg FLASH_FLAG_RDPERR_BANK2     : Read Protection Error on Bank 2 flag
+  *     @arg FLASH_FLAG_RDSERR_BANK2     : Read secure  Error on Bank 2 flag
+  *     @arg FLASH_FLAG_SNECCE_BANK2     : Single ECC Error Correction on Bank 2 flag
+  *     @arg FLASH_FLAG_DBECCE_BANK2     : Double Detection ECC Error on Bank 2 flag
+  *     @arg FLASH_FLAG_CRCEND_BANK2     : CRC End on Bank 2 flag
+  *     @arg FLASH_FLAG_CRCRDERR_BANK2   : CRC Read error on Bank 2 flag
+  *     @arg FLASH_FLAG_ALL_ERRORS_BANK2 : All Bank 2 error flags
+  *     @arg FLASH_FLAG_ALL_BANK2        : All Bank 2 flags
+  * @retval none
+  */
+
+#define __HAL_FLASH_CLEAR_FLAG_BANK1(__FLAG__)    WRITE_REG(FLASH->CCR1, (__FLAG__))
+
+#define __HAL_FLASH_CLEAR_FLAG_BANK2(__FLAG__)    WRITE_REG(FLASH->CCR2, ((__FLAG__) & 0x7FFFFFFFU))
+
+#define __HAL_FLASH_CLEAR_FLAG(__FLAG__)         (IS_FLASH_FLAG_BANK1(__FLAG__) ?  __HAL_FLASH_CLEAR_FLAG_BANK1(__FLAG__) : \
+                                                   __HAL_FLASH_CLEAR_FLAG_BANK2(__FLAG__))
+
+/**
+  * @}
+  */
+
+/* Include FLASH HAL Extension module */
+#include "stm32h7xx_hal_flash_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASH_Exported_Functions
+  * @{
+  */
+/** @addtogroup FLASH_Exported_Functions_Group1
+  * @{
+  */
+/* Program operation functions  ***********************************************/
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress);
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress);
+/* FLASH IRQ handler method */
+void HAL_FLASH_IRQHandler(void);
+/* Callbacks in non blocking modes */
+void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
+void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
+/**
+  * @}
+  */
+
+/** @addtogroup FLASH_Exported_Functions_Group2
+  * @{
+  */
+/* Peripheral Control functions  **********************************************/
+HAL_StatusTypeDef HAL_FLASH_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_Lock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
+/* Option bytes control */
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
+/**
+  * @}
+  */
+
+/** @addtogroup FLASH_Exported_Functions_Group3
+  * @{
+  */
+/* Peripheral State functions  ************************************************/
+uint32_t HAL_FLASH_GetError(void);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup FLASH_Private_Variables FLASH Private Variables
+  * @{
+  */
+extern FLASH_ProcessTypeDef pFlash;
+/**
+  * @}
+  */
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup FLASH_Private_Constants FLASH Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FLASH_Private_Macros FLASH Private Macros
+  * @{
+  */
+
+#if defined (FLASH_OPTCR_PG_OTP)
+#define IS_FLASH_TYPEPROGRAM(VALUE)      (((VALUE) == FLASH_TYPEPROGRAM_FLASHWORD) || \
+                                          ((VALUE) == FLASH_TYPEPROGRAM_OTPWORD))
+#else
+#define IS_FLASH_TYPEPROGRAM(VALUE)      ((VALUE) == FLASH_TYPEPROGRAM_FLASHWORD)
+#endif /* FLASH_OPTCR_PG_OTP */
+
+#define IS_FLASH_IT_BANK1(IT)            (((IT) & FLASH_IT_ALL_BANK1) == (IT))
+
+#define IS_FLASH_IT_BANK2(IT)            (((IT) & FLASH_IT_ALL_BANK2) == (IT))
+
+#define IS_FLASH_FLAG_BANK1(FLAG)        (((FLAG) & FLASH_FLAG_ALL_BANK1) == (FLAG))
+
+#define IS_FLASH_FLAG_BANK2(FLAG)        (((FLAG) & FLASH_FLAG_ALL_BANK2) == (FLAG))
+
+#define IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) (((ADDRESS) >= FLASH_BANK1_BASE) && ((ADDRESS) < FLASH_BANK2_BASE))
+#define IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS) (((ADDRESS) >= FLASH_BANK2_BASE ) && ((ADDRESS) <= FLASH_END))
+
+#if defined (FLASH_OPTCR_PG_OTP)
+#define IS_FLASH_PROGRAM_ADDRESS_OTP(ADDRESS)   (((ADDRESS) >= 0x08FFF000U) && ((ADDRESS) <= 0x08FFF3FFU))
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS)       (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || \
+                                                 IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS) || \
+                                                 IS_FLASH_PROGRAM_ADDRESS_OTP(ADDRESS))
+#else
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS)       (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || \
+                                                 IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS))
+#endif /* FLASH_OPTCR_PG_OTP */
+
+#define IS_BOOT_ADDRESS(ADDRESS)           ((ADDRESS) <= (0x3FFF0000U))
+
+#define IS_FLASH_BANK(BANK)                (((BANK) == FLASH_BANK_1)  || \
+                                            ((BANK) == FLASH_BANK_2)  || \
+                                            ((BANK) == FLASH_BANK_BOTH))
+
+#define IS_FLASH_BANK_EXCLUSIVE(BANK)      (((BANK) == FLASH_BANK_1)  || \
+                                            ((BANK) == FLASH_BANK_2))
+
+
+/**
+  * @}
+  */
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup FLASH_Private_Functions FLASH Private functions
+  * @{
+  */
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout, uint32_t Bank);
+HAL_StatusTypeDef FLASH_OB_WaitForLastOperation(uint32_t Timeout);
+HAL_StatusTypeDef FLASH_CRC_WaitForLastOperation(uint32_t Timeout, uint32_t Bank);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_FLASH_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h
new file mode 100644
index 00000000..834c5d23
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h
@@ -0,0 +1,910 @@
+/**
+  ******************************************************************************
+  * @file    stm32H7xx_hal_flash_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of FLASH HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_FLASH_EX_H
+#define STM32H7xx_HAL_FLASH_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FLASHEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Types FLASH Exported Types
+  * @{
+  */
+
+/**
+  * @brief  FLASH Erase structure definition
+  */
+typedef struct
+{
+  uint32_t TypeErase;   /*!< Mass erase or sector Erase.
+                             This parameter can be a value of @ref FLASHEx_Type_Erase */
+
+  uint32_t Banks;       /*!< Select banks to erase when Mass erase is enabled.
+                             This parameter must be a value of @ref FLASHEx_Banks */
+
+  uint32_t Sector;      /*!< Initial FLASH sector to erase when Mass erase is disabled
+                             This parameter must be a value of @ref FLASH_Sectors */
+
+  uint32_t NbSectors;   /*!< Number of sectors to be erased.
+                             This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
+
+  uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism
+                             This parameter must be a value of @ref FLASHEx_Voltage_Range */
+
+} FLASH_EraseInitTypeDef;
+
+
+/**
+  * @brief  FLASH Option Bytes Program structure definition
+  */
+typedef struct
+{
+  uint32_t OptionType;     /*!< Option byte to be configured.
+                                This parameter can be a value of @ref FLASHEx_Option_Type */
+
+  uint32_t WRPState;       /*!< Write protection activation or deactivation.
+                                This parameter can be a value of @ref FLASHEx_WRP_State */
+
+  uint32_t WRPSector;      /*!< Specifies the sector(s) to be write protected.
+                                The value of this parameter depend on device used within the same series */
+
+  uint32_t RDPLevel;       /*!< Set the read protection level.
+                                This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
+
+  uint32_t BORLevel;       /*!< Set the BOR Level.
+                                This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */
+
+  uint32_t USERType;       /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER).
+                                This parameter can be a combination of @ref FLASHEx_OB_USER_Type */
+
+  uint32_t USERConfig;     /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY /
+                                IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / IO_HSLV / SWAP_BANK_OPT */
+
+  uint32_t Banks;          /*!< Select banks for WRP , PCROP and secure area config .
+                                This parameter must be a value of @ref FLASHEx_Banks */
+
+  uint32_t PCROPConfig;    /*!< specifies if the PCROP area shall be erased or not
+                                when RDP level decreased from Level 1 to Level 0 or during a mass erase.
+                                This parameter must be a value of @ref FLASHEx_OB_PCROP_RDP enumeration */
+
+  uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP).
+                                This parameter must be a value between begin and end of a bank */
+
+  uint32_t PCROPEndAddr;   /*!< PCROP End address (used for OPTIONBYTE_PCROP).
+                                This parameter must be a value between PCROP Start address and end of a bank */
+
+  uint32_t BootConfig;     /*!< Specifies if the Boot Address to be configured BOOT_ADD0, BOOT_ADD1
+                                or both. This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION enumeration */
+
+  uint32_t BootAddr0;      /*!< Boot Address 0.
+                                This parameter must be a value between begin and end of a bank */
+
+  uint32_t BootAddr1;      /*!< Boot Address 1.
+                                This parameter must be a value between begin and end of a bank */
+#if defined(DUAL_CORE)
+  uint32_t CM4BootConfig;  /*!< specifies if the CM4 boot Address to be configured BOOT_ADD0, BOOT_ADD1
+                                or both.
+                                This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION enumeration */
+
+  uint32_t CM4BootAddr0;   /*!< CM4 Boot Address 0.
+                                This parameter must be a value between begin and end of a bank */
+
+  uint32_t CM4BootAddr1;   /*!< CM4 Boot Address 1.
+                                This parameter must be a value between begin and end of a bank */
+#endif /*DUAL_CORE*/
+
+  uint32_t SecureAreaConfig;    /*!< specifies if the bank secured area shall be erased or not
+                                     when RDP level decreased from Level 1 to Level 0 or during a mass erase.
+                                     This parameter must be a value of @ref FLASHEx_OB_SECURE_RDP enumeration */
+
+  uint32_t SecureAreaStartAddr; /*!< Bank Secure area Start address.
+                                     This parameter must be a value between begin address and end address of bank1 */
+
+  uint32_t SecureAreaEndAddr;   /*!< Bank Secure area End address.
+                                     This parameter must be a value between Secure Area Start address and end address of a bank1 */
+
+#if defined (FLASH_OTPBL_LOCKBL)
+  uint32_t OTPBlockLock;   /*!< Specifies the OTP block(s) to be locked.
+                                This parameter must be a value of @ref FLASHEx_OTP_Blocks */
+#endif /* FLASH_OTPBL_LOCKBL */
+
+} FLASH_OBProgramInitTypeDef;
+
+/**
+  * @brief  FLASH Erase structure definition
+  */
+typedef struct
+{
+  uint32_t TypeCRC;      /*!< CRC Selection Type.
+                              This parameter can be a value of @ref FLASHEx_CRC_Selection_Type */
+
+  uint32_t BurstSize;    /*!< CRC Burst Size.
+                              This parameter can be a value of @ref FLASHEx_CRC_Burst_Size */
+
+  uint32_t Bank;         /*!< Select bank where CRC computation is enabled.
+                              This parameter must be FLASH_BANK_1 or FLASH_BANK_2 */
+
+  uint32_t Sector;       /*!< Initial FLASH sector from which starts the CRC computation
+                              This parameter must be a value of @ref FLASH_Sectors */
+
+  uint32_t NbSectors;    /*!< Number of sectors to be computed.
+                              This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
+
+  uint32_t CRCStartAddr; /*!< CRC Start address.
+                              This parameter must be a value between begin address and end address of a bank */
+
+  uint32_t CRCEndAddr;   /*!< CRC End address.
+                              This parameter must be a value between CRC Start address and end address of a bank */
+
+} FLASH_CRCInitTypeDef;
+
+/**
+  * @}
+  */
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants
+  * @{
+  */
+
+/** @defgroup FLASHEx_Type_Erase FLASH Type Erase
+  * @{
+  */
+#define FLASH_TYPEERASE_SECTORS      0x00U  /*!< Sectors erase only          */
+#define FLASH_TYPEERASE_MASSERASE    0x01U  /*!< Flash Mass erase activation */
+/**
+  * @}
+  */
+
+#if defined (FLASH_CR_PSIZE)
+/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range
+  * @{
+  */
+#define FLASH_VOLTAGE_RANGE_1        0x00000000U       /*!< Flash program/erase by 8 bits  */
+#define FLASH_VOLTAGE_RANGE_2        FLASH_CR_PSIZE_0  /*!< Flash program/erase by 16 bits */
+#define FLASH_VOLTAGE_RANGE_3        FLASH_CR_PSIZE_1  /*!< Flash program/erase by 32 bits */
+#define FLASH_VOLTAGE_RANGE_4        FLASH_CR_PSIZE    /*!< Flash program/erase by 64 bits */
+/**
+  * @}
+  */
+#endif /* FLASH_CR_PSIZE */
+
+/** @defgroup FLASHEx_WRP_State FLASH WRP State
+  * @{
+  */
+#define OB_WRPSTATE_DISABLE          0x00000000U  /*!< Disable the write protection of the desired bank 1 sectors */
+#define OB_WRPSTATE_ENABLE           0x00000001U  /*!< Enable the write protection of the desired bank 1 sectors  */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Option_Type FLASH Option Type
+  * @{
+  */
+#define OPTIONBYTE_WRP           0x01U  /*!< WRP option byte configuration  */
+#define OPTIONBYTE_RDP           0x02U  /*!< RDP option byte configuration  */
+#define OPTIONBYTE_USER          0x04U  /*!< USER option byte configuration */
+#define OPTIONBYTE_PCROP         0x08U  /*!< PCROP option byte configuration */
+#define OPTIONBYTE_BOR           0x10U  /*!< BOR option byte configuration */
+#define OPTIONBYTE_SECURE_AREA   0x20U  /*!< secure area option byte configuration */
+#if defined (DUAL_CORE)
+#define OPTIONBYTE_CM7_BOOTADD   0x40U  /*!< CM7 BOOT ADD option byte configuration */
+#define OPTIONBYTE_CM4_BOOTADD   0x80U  /*!< CM4 BOOT ADD option byte configuration */
+#define OPTIONBYTE_BOOTADD       OPTIONBYTE_CM7_BOOTADD  /*!< BOOT ADD option byte configuration */
+#else /* Single core */
+#define OPTIONBYTE_BOOTADD       0x40U  /*!< BOOT ADD option byte configuration */
+#endif /*DUAL_CORE*/
+#if defined (FLASH_OTPBL_LOCKBL)
+#define OPTIONBYTE_OTP_LOCK      0x80U  /*!< OTP Lock option byte configuration */
+#endif /* FLASH_OTPBL_LOCKBL */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection
+  * @{
+  */
+#define OB_RDP_LEVEL_0       0xAA00U
+#define OB_RDP_LEVEL_1       0x5500U
+#define OB_RDP_LEVEL_2       0xCC00U   /*!< Warning: When enabling read protection level 2
+                                            it s no more possible to go back to level 1 or 0 */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Option_Bytes_WWatchdog FLASH Option Bytes WWatchdog
+  * @{
+  */
+#define OB_WWDG_SW           0x10U  /*!< Software WWDG selected */
+#define OB_WWDG_HW           0x00U  /*!< Hardware WWDG selected */
+/**
+  * @}
+  */
+
+
+/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog
+  * @{
+  */
+#define OB_IWDG_SW           0x20U  /*!< Software IWDG selected */
+#define OB_IWDG_HW           0x00U  /*!< Hardware IWDG selected */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP
+  * @{
+  */
+#define OB_STOP_NO_RST       0x40U /*!< No reset generated when entering in STOP */
+#define OB_STOP_RST          0x00U /*!< Reset generated when entering in STOP    */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY
+  * @{
+  */
+#define OB_STDBY_NO_RST      0x80U /*!< No reset generated when entering in STANDBY */
+#define OB_STDBY_RST         0x00U /*!< Reset generated when entering in STANDBY    */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP
+  * @{
+  */
+#define OB_IWDG_STOP_FREEZE  0x00000000U /*!< Freeze IWDG counter in STOP mode */
+#define OB_IWDG_STOP_ACTIVE  FLASH_OPTSR_FZ_IWDG_STOP /*!< IWDG counter active in STOP mode */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY
+  * @{
+  */
+#define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Freeze IWDG counter in STANDBY mode */
+#define OB_IWDG_STDBY_ACTIVE FLASH_OPTSR_FZ_IWDG_SDBY  /*!< IWDG counter active in STANDBY mode */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level
+  * @{
+  */
+#define OB_BOR_LEVEL0        0x00000000U                /*!< Reset level threshold is set to 1.6V */
+#define OB_BOR_LEVEL1        FLASH_OPTSR_BOR_LEV_0      /*!< Reset level threshold is set to 2.1V */
+#define OB_BOR_LEVEL2        FLASH_OPTSR_BOR_LEV_1      /*!< Reset level threshold is set to 2.4V */
+#define OB_BOR_LEVEL3        (FLASH_OPTSR_BOR_LEV_1 | FLASH_OPTSR_BOR_LEV_0) /*!< Reset level threshold is set to 2.7V  */
+/**
+  * @}
+  */
+
+
+
+/** @defgroup FLASHEx_Boot_Address FLASH Boot Address
+  * @{
+  */
+#define OB_BOOTADDR_ITCM_RAM     0x0000U  /*!< Boot from ITCM RAM (0x00000000)                 */
+#define OB_BOOTADDR_SYSTEM       0x0040U  /*!< Boot from System memory bootloader (0x00100000) */
+#define OB_BOOTADDR_ITCM_FLASH   0x0080U  /*!< Boot from Flash on ITCM interface (0x00200000)  */
+#define OB_BOOTADDR_AXIM_FLASH   0x2000U  /*!< Boot from Flash on AXIM interface (0x08000000)  */
+#define OB_BOOTADDR_DTCM_RAM     0x8000U  /*!< Boot from DTCM RAM (0x20000000)                 */
+#define OB_BOOTADDR_SRAM1        0x8004U  /*!< Boot from SRAM1 (0x20010000)                    */
+#define OB_BOOTADDR_SRAM2        0x8013U  /*!< Boot from SRAM2 (0x2004C000)                    */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Latency FLASH Latency
+  * @{
+  */
+#define FLASH_LATENCY_0          FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero Latency cycle      */
+#define FLASH_LATENCY_1          FLASH_ACR_LATENCY_1WS   /*!< FLASH One Latency cycle       */
+#define FLASH_LATENCY_2          FLASH_ACR_LATENCY_2WS   /*!< FLASH Two Latency cycles      */
+#define FLASH_LATENCY_3          FLASH_ACR_LATENCY_3WS   /*!< FLASH Three Latency cycles    */
+#define FLASH_LATENCY_4          FLASH_ACR_LATENCY_4WS   /*!< FLASH Four Latency cycles     */
+#define FLASH_LATENCY_5          FLASH_ACR_LATENCY_5WS   /*!< FLASH Five Latency cycles     */
+#define FLASH_LATENCY_6          FLASH_ACR_LATENCY_6WS   /*!< FLASH Six Latency cycles      */
+#define FLASH_LATENCY_7          FLASH_ACR_LATENCY_7WS   /*!< FLASH Seven Latency cycles    */
+#define FLASH_LATENCY_8          FLASH_ACR_LATENCY_8WS   /*!< FLASH Eight Latency cycle     */
+#define FLASH_LATENCY_9          FLASH_ACR_LATENCY_9WS   /*!< FLASH Nine Latency cycle      */
+#define FLASH_LATENCY_10         FLASH_ACR_LATENCY_10WS  /*!< FLASH Ten Latency cycles      */
+#define FLASH_LATENCY_11         FLASH_ACR_LATENCY_11WS  /*!< FLASH Eleven Latency cycles   */
+#define FLASH_LATENCY_12         FLASH_ACR_LATENCY_12WS  /*!< FLASH Twelve Latency cycles   */
+#define FLASH_LATENCY_13         FLASH_ACR_LATENCY_13WS  /*!< FLASH Thirteen Latency cycles */
+#define FLASH_LATENCY_14         FLASH_ACR_LATENCY_14WS  /*!< FLASH Fourteen Latency cycles */
+#define FLASH_LATENCY_15         FLASH_ACR_LATENCY_15WS  /*!< FLASH Fifteen Latency cycles  */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Banks FLASH Banks
+  * @{
+  */
+#define FLASH_BANK_1             0x01U                         /*!< Bank 1   */
+#define FLASH_BANK_2             0x02U                         /*!< Bank 2   */
+#define FLASH_BANK_BOTH          (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2  */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_OB_PCROP_RDP  FLASHEx OB PCROP RDP
+  * @{
+  */
+#define OB_PCROP_RDP_NOT_ERASE   0x00000000U     /*!< PCROP area is not erased when the RDP level
+                                                      is decreased from Level 1 to Level 0 or during a mass erase */
+#define OB_PCROP_RDP_ERASE       FLASH_PRAR_DMEP /*!< PCROP area is erased when the RDP level is
+                                                      decreased from Level 1 to Level 0 (full mass erase) */
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
+  * @{
+  */
+#if (FLASH_SECTOR_TOTAL == 128)
+#define OB_WRP_SECTOR_0TO3       0x00000001U /*!< Write protection of Sector0  to Sector3    */
+#define OB_WRP_SECTOR_4TO7       0x00000002U /*!< Write protection of Sector4  to Sector7    */
+#define OB_WRP_SECTOR_8TO11      0x00000004U /*!< Write protection of Sector8  to Sector11   */
+#define OB_WRP_SECTOR_12TO15     0x00000008U /*!< Write protection of Sector12 to Sector15   */
+#define OB_WRP_SECTOR_16TO19     0x00000010U /*!< Write protection of Sector16 to Sector19   */
+#define OB_WRP_SECTOR_20TO23     0x00000020U /*!< Write protection of Sector20 to Sector23   */
+#define OB_WRP_SECTOR_24TO27     0x00000040U /*!< Write protection of Sector24 to Sector27   */
+#define OB_WRP_SECTOR_28TO31     0x00000080U /*!< Write protection of Sector28 to Sector31   */
+#define OB_WRP_SECTOR_32TO35     0x00000100U /*!< Write protection of Sector32 to Sector35   */
+#define OB_WRP_SECTOR_36TO39     0x00000200U /*!< Write protection of Sector36 to Sector39   */
+#define OB_WRP_SECTOR_40TO43     0x00000400U /*!< Write protection of Sector40 to Sector43   */
+#define OB_WRP_SECTOR_44TO47     0x00000800U /*!< Write protection of Sector44 to Sector47   */
+#define OB_WRP_SECTOR_48TO51     0x00001000U /*!< Write protection of Sector48 to Sector51   */
+#define OB_WRP_SECTOR_52TO55     0x00002000U /*!< Write protection of Sector52 to Sector55   */
+#define OB_WRP_SECTOR_56TO59     0x00004000U /*!< Write protection of Sector56 to Sector59   */
+#define OB_WRP_SECTOR_60TO63     0x00008000U /*!< Write protection of Sector60 to Sector63   */
+#define OB_WRP_SECTOR_64TO67     0x00010000U /*!< Write protection of Sector64 to Sector67   */
+#define OB_WRP_SECTOR_68TO71     0x00020000U /*!< Write protection of Sector68 to Sector71   */
+#define OB_WRP_SECTOR_72TO75     0x00040000U /*!< Write protection of Sector72 to Sector75   */
+#define OB_WRP_SECTOR_76TO79     0x00080000U /*!< Write protection of Sector76 to Sector79   */
+#define OB_WRP_SECTOR_80TO83     0x00100000U /*!< Write protection of Sector80 to Sector83   */
+#define OB_WRP_SECTOR_84TO87     0x00200000U /*!< Write protection of Sector84 to Sector87   */
+#define OB_WRP_SECTOR_88TO91     0x00400000U /*!< Write protection of Sector88 to Sector91   */
+#define OB_WRP_SECTOR_92TO95     0x00800000U /*!< Write protection of Sector92 to Sector95   */
+#define OB_WRP_SECTOR_96TO99     0x01000000U /*!< Write protection of Sector96  to Sector99  */
+#define OB_WRP_SECTOR_100TO103   0x02000000U /*!< Write protection of Sector100 to Sector103 */
+#define OB_WRP_SECTOR_104TO107   0x04000000U /*!< Write protection of Sector104 to Sector107 */
+#define OB_WRP_SECTOR_108TO111   0x08000000U /*!< Write protection of Sector108 to Sector111 */
+#define OB_WRP_SECTOR_112TO115   0x10000000U /*!< Write protection of Sector112 to Sector115 */
+#define OB_WRP_SECTOR_116TO119   0x20000000U /*!< Write protection of Sector116 to Sector119 */
+#define OB_WRP_SECTOR_120TO123   0x40000000U /*!< Write protection of Sector120 to Sector123 */
+#define OB_WRP_SECTOR_124TO127   0x80000000U /*!< Write protection of Sector124 to Sector127 */
+#define OB_WRP_SECTOR_ALL        0xFFFFFFFFU /*!< Write protection of all Sectors            */
+#else
+#define OB_WRP_SECTOR_0          0x00000001U /*!< Write protection of Sector0                */
+#define OB_WRP_SECTOR_1          0x00000002U /*!< Write protection of Sector1                */
+#define OB_WRP_SECTOR_2          0x00000004U /*!< Write protection of Sector2                */
+#define OB_WRP_SECTOR_3          0x00000008U /*!< Write protection of Sector3                */
+#define OB_WRP_SECTOR_4          0x00000010U /*!< Write protection of Sector4                */
+#define OB_WRP_SECTOR_5          0x00000020U /*!< Write protection of Sector5                */
+#define OB_WRP_SECTOR_6          0x00000040U /*!< Write protection of Sector6                */
+#define OB_WRP_SECTOR_7          0x00000080U /*!< Write protection of Sector7                */
+#define OB_WRP_SECTOR_ALL        0x000000FFU /*!< Write protection of all Sectors            */
+#endif /* FLASH_SECTOR_TOTAL == 128 */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_OB_SECURITY  FLASHEx OB SECURITY
+  * @{
+  */
+#define OB_SECURITY_DISABLE   0x00000000U             /*!< security enabled */
+#define OB_SECURITY_ENABLE    FLASH_OPTSR_SECURITY    /*!< security disabled */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_OB_ST_RAM_SIZE  FLASHEx OB ST RAM SIZE
+  * @{
+  */
+#define OB_ST_RAM_SIZE_2KB    0x00000000U               /*!< 2 Kbytes reserved to ST code */
+#define OB_ST_RAM_SIZE_4KB    FLASH_OPTSR_ST_RAM_SIZE_0 /*!< 4 Kbytes reserved to ST code */
+#define OB_ST_RAM_SIZE_8KB    FLASH_OPTSR_ST_RAM_SIZE_1 /*!< 8 Kbytes reserved to ST code */
+#define OB_ST_RAM_SIZE_16KB   FLASH_OPTSR_ST_RAM_SIZE   /*!< 16 Kbytes reserved to ST code */
+/**
+  * @}
+  */
+
+#if defined(DUAL_CORE)
+/** @defgroup FLASHEx_OB_BCM7  FLASHEx OB BCM7
+  * @{
+  */
+#define OB_BCM7_DISABLE       0x00000000U              /*!< CM7 Boot disabled */
+#define OB_BCM7_ENABLE        FLASH_OPTSR_BCM7         /*!< CM7 Boot enabled */
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_OB_BCM4  FLASHEx OB BCM4
+  * @{
+  */
+#define OB_BCM4_DISABLE       0x00000000U              /*!< CM4 Boot disabled */
+#define OB_BCM4_ENABLE        FLASH_OPTSR_BCM4         /*!< CM4 Boot enabled */
+/**
+  * @}
+  */
+#endif /* DUAL_CORE */
+
+/** @defgroup FLASHEx_OB_IWDG1_SW  FLASHEx OB IWDG1 SW
+  * @{
+  */
+#define OB_IWDG1_SW            FLASH_OPTSR_IWDG1_SW /*!< Hardware independent watchdog 1 */
+#define OB_IWDG1_HW            0x00000000U          /*!< Software independent watchdog 1 */
+/**
+  * @}
+  */
+
+#if defined(DUAL_CORE)
+/** @defgroup FLASHEx_OB_IWDG2_SW  FLASHEx OB IWDG2 SW
+  * @{
+  */
+#define OB_IWDG2_SW            FLASH_OPTSR_IWDG2_SW  /*!< Hardware independent watchdog 2*/
+#define OB_IWDG2_HW            0x00000000U           /*!< Software independent watchdog 2*/
+/**
+  * @}
+  */
+#endif
+
+/** @defgroup FLASHEx_OB_NRST_STOP_D1  FLASHEx OB NRST STOP D1
+  * @{
+  */
+#define OB_STOP_RST_D1         0x00000000U              /*!< Reset generated when entering the D1 to stop mode */
+#define OB_STOP_NO_RST_D1      FLASH_OPTSR_NRST_STOP_D1 /*!< No reset generated when entering the D1 to stop mode */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_OB_NRST_STDBY_D1  FLASHEx OB NRST STDBY D1
+  * @{
+  */
+#define OB_STDBY_RST_D1        0x00000000U              /*!< Reset generated when entering the D1 to standby mode */
+#define OB_STDBY_NO_RST_D1     FLASH_OPTSR_NRST_STBY_D1 /*!< No reset generated when entering the D1 to standby mode */
+/**
+  * @}
+  */
+
+#if defined (DUAL_CORE)
+/** @defgroup FLASHEx_OB_NRST_STOP_D2  FLASHEx OB NRST STOP D2
+  * @{
+  */
+#define OB_STOP_RST_D2         0x00000000U              /*!< Reset generated when entering the D2 to stop mode */
+#define OB_STOP_NO_RST_D2      FLASH_OPTSR_NRST_STOP_D2 /*!< No reset generated when entering the D2 to stop mode */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_OB_NRST_STDBY_D2  FLASHEx OB NRST STDBY D2
+  * @{
+  */
+#define OB_STDBY_RST_D2        0x00000000U              /*!< Reset generated when entering the D2 to standby mode */
+#define OB_STDBY_NO_RST_D2     FLASH_OPTSR_NRST_STBY_D2 /*!< No reset generated when entering the D2 to standby mode */
+/**
+  * @}
+  */
+#endif /* DUAL_CORE */
+
+/** @defgroup FLASHEx_OB_SWAP_BANK  FLASHEx OB SWAP BANK
+  * @{
+  */
+#define OB_SWAP_BANK_DISABLE   0x00000000U               /*!< Bank swap disabled */
+#define OB_SWAP_BANK_ENABLE    FLASH_OPTSR_SWAP_BANK_OPT /*!< Bank swap enabled */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_OB_IOHSLV FLASHEx OB IOHSLV
+  * @{
+  */
+#define OB_IOHSLV_DISABLE      0x00000000U         /*!< IOHSLV disabled */
+#define OB_IOHSLV_ENABLE       FLASH_OPTSR_IO_HSLV /*!< IOHSLV enabled */
+/**
+  * @}
+  */
+
+#if defined (FLASH_OPTSR_VDDMMC_HSLV)
+/** @defgroup FLASHEx_OB_VDDMMC_HSLV FLASHEx OB VDDMMC HSLV
+  * @{
+  */
+#define OB_VDDMMC_HSLV_DISABLE 0x00000000U             /*!< VDDMMC HSLV disabled */
+#define OB_VDDMMC_HSLV_ENABLE  FLASH_OPTSR_VDDMMC_HSLV /*!< VDDMMC HSLV enabled */
+/**
+  * @}
+  */
+#endif /* FLASH_OPTSR_VDDMMC_HSLV */
+
+/** @defgroup FLASHEx_OB_BOOT_OPTION  FLASHEx OB BOOT OPTION
+  * @{
+  */
+#define OB_BOOT_ADD0           0x01U       /*!< Select Boot Address 0 */
+#define OB_BOOT_ADD1           0x02U       /*!< Select Boot Address 1 */
+#define OB_BOOT_ADD_BOTH       0x03U       /*!< Select Boot Address 0 and 1 */
+/**
+  * @}
+  */
+
+ /** @defgroup FLASHEx_OB_USER_Type  FLASHEx OB USER Type
+  * @{
+  */
+#define OB_USER_IWDG1_SW          0x0001U /*!< Independent watchdog selection */
+#define OB_USER_NRST_STOP_D1      0x0002U /*!< Reset when entering Stop mode selection*/
+#define OB_USER_NRST_STDBY_D1     0x0004U /*!< Reset when entering standby mode selection*/
+#define OB_USER_IWDG_STOP         0x0008U /*!< Independent watchdog counter freeze in stop mode */
+#define OB_USER_IWDG_STDBY        0x0010U /*!< Independent watchdog counter freeze in standby mode */
+#define OB_USER_ST_RAM_SIZE       0x0020U /*!< dedicated DTCM Ram size selection */
+#define OB_USER_SECURITY          0x0040U /*!< security selection */
+#define OB_USER_IOHSLV            0x0080U /*!< IO HSLV selection */
+#define OB_USER_SWAP_BANK         0x0100U /*!< Bank swap selection */
+#if defined (FLASH_OPTSR_VDDMMC_HSLV)
+#define OB_USER_VDDMMC_HSLV       0x0200U /*!< VDDMMC HSLV selection */
+#endif /* FLASH_OPTSR_VDDMMC_HSLV */
+#if defined (DUAL_CORE)
+#define OB_USER_IWDG2_SW          0x0200U /*!< Window watchdog selection */
+#define OB_USER_BCM4              0x0400U /*!< CM4 boot selection */
+#define OB_USER_BCM7              0x0800U /*!< CM7 boot selection */
+#define OB_USER_NRST_STOP_D2      0x1000U /*!< Reset when entering Stop mode selection*/
+#define OB_USER_NRST_STDBY_D2     0x2000U /*!< Reset when entering standby mode selection*/
+#endif /*DUAL_CORE*/
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_OB_SECURE_RDP  FLASHEx OB SECURE RDP
+  * @{
+  */
+#define OB_SECURE_RDP_NOT_ERASE   0x00000000U     /*!< Secure area is not erased when the RDP level
+                                                       is decreased from Level 1 to Level 0 or during a mass erase */
+#define OB_SECURE_RDP_ERASE       FLASH_SCAR_DMES /*!< Secure area is erased when the RDP level is
+                                                       decreased from Level 1 to Level 0 (full mass erase) */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_CRC_Selection_Type FLASH CRC Selection Type
+  * @{
+  */
+#define FLASH_CRC_ADDR         0x00000000U              /*!< CRC selection type by address  */
+#define FLASH_CRC_SECTORS      FLASH_CRCCR_CRC_BY_SECT  /*!< CRC selection type by sectors  */
+#define FLASH_CRC_BANK         (FLASH_CRCCR_ALL_BANK | FLASH_CRCCR_CRC_BY_SECT) /*!< CRC selection type by bank */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_CRC_Burst_Size FLASH CRC Burst Size
+  * @{
+  */
+#define FLASH_CRC_BURST_SIZE_4    0x00000000U              /*!< Every burst has a size of 4 Flash words (256-bit)  */
+#define FLASH_CRC_BURST_SIZE_16   FLASH_CRCCR_CRC_BURST_0  /*!< Every burst has a size of 16 Flash words (256-bit)   */
+#define FLASH_CRC_BURST_SIZE_64   FLASH_CRCCR_CRC_BURST_1  /*!< Every burst has a size of 64 Flash words (256-bit)   */
+#define FLASH_CRC_BURST_SIZE_256  FLASH_CRCCR_CRC_BURST    /*!< Every burst has a size of 256 Flash words (256-bit) */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Programming_Delay FLASH Programming Delay
+  * @{
+  */
+#define FLASH_PROGRAMMING_DELAY_0   0x00000000U            /*!< programming delay set for Flash running at 70 MHz or below          */
+#define FLASH_PROGRAMMING_DELAY_1   FLASH_ACR_WRHIGHFREQ_0 /*!< programming delay set for Flash running between 70 MHz and 185 MHz  */
+#define FLASH_PROGRAMMING_DELAY_2   FLASH_ACR_WRHIGHFREQ_1 /*!< programming delay set for Flash running between 185 MHz and 225 MHz */
+#define FLASH_PROGRAMMING_DELAY_3   FLASH_ACR_WRHIGHFREQ   /*!< programming delay set for Flash at startup */
+/**
+  * @}
+  */
+
+#if defined (FLASH_OTPBL_LOCKBL)
+/** @defgroup FLASHEx_OTP_Blocks FLASH OTP blocks
+  * @{
+  */
+#define FLASH_OTP_BLOCK_0          0x00000001U /*!< OTP Block0     */
+#define FLASH_OTP_BLOCK_1          0x00000002U /*!< OTP Block1     */
+#define FLASH_OTP_BLOCK_2          0x00000004U /*!< OTP Block2     */
+#define FLASH_OTP_BLOCK_3          0x00000008U /*!< OTP Block3     */
+#define FLASH_OTP_BLOCK_4          0x00000010U /*!< OTP Block4     */
+#define FLASH_OTP_BLOCK_5          0x00000020U /*!< OTP Block5     */
+#define FLASH_OTP_BLOCK_6          0x00000040U /*!< OTP Block6     */
+#define FLASH_OTP_BLOCK_7          0x00000080U /*!< OTP Block7     */
+#define FLASH_OTP_BLOCK_8          0x00000100U /*!< OTP Block8     */
+#define FLASH_OTP_BLOCK_9          0x00000200U /*!< OTP Block9     */
+#define FLASH_OTP_BLOCK_10         0x00000400U /*!< OTP Block10    */
+#define FLASH_OTP_BLOCK_11         0x00000800U /*!< OTP Block11    */
+#define FLASH_OTP_BLOCK_12         0x00001000U /*!< OTP Block12    */
+#define FLASH_OTP_BLOCK_13         0x00002000U /*!< OTP Block13    */
+#define FLASH_OTP_BLOCK_14         0x00004000U /*!< OTP Block14    */
+#define FLASH_OTP_BLOCK_15         0x00008000U /*!< OTP Block15    */
+#define FLASH_OTP_BLOCK_ALL        0x0000FFFFU /*!< OTP All Blocks */
+/**
+  * @}
+  */
+#endif /* FLASH_OTPBL_LOCKBL */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Macros FLASH Exported Macros
+  * @{
+  */
+/**
+  * @brief  Calculate the FLASH Boot Base Adress (BOOT_ADD0 or BOOT_ADD1)
+  * @note   Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14].
+  * @param  __ADDRESS__: FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB)
+  * @retval The FLASH Boot Base Adress
+  */
+#define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14U)
+ /**
+  * @}
+  */
+
+#if defined (FLASH_CR_PSIZE)
+/**
+  * @brief  Set the FLASH Program/Erase parallelism.
+  * @param  __PSIZE__ FLASH Program/Erase parallelism
+  *         This parameter can be a value of @ref FLASH_Program_Parallelism
+  * @param  __BANK__: Flash bank (FLASH_BANK_1 or FLASH_BANK_2)
+  * @retval none
+  */
+#define __HAL_FLASH_SET_PSIZE(__PSIZE__, __BANK__) (((__BANK__) == FLASH_BANK_1)  ? \
+                              MODIFY_REG(FLASH->CR1, FLASH_CR_PSIZE, (__PSIZE__)) : \
+                              MODIFY_REG(FLASH->CR2, FLASH_CR_PSIZE, (__PSIZE__)))
+
+/**
+  * @brief  Get the FLASH Program/Erase parallelism.
+  * @param  __BANK__ Flash bank (FLASH_BANK_1 or FLASH_BANK_2)
+  * @retval FLASH Program/Erase parallelism
+  *         This return value can be a value of @ref FLASH_Program_Parallelism
+  */
+#define __HAL_FLASH_GET_PSIZE(__BANK__) (((__BANK__) == FLASH_BANK_1) ? \
+                              READ_BIT((FLASH->CR1), FLASH_CR_PSIZE)  : \
+                              READ_BIT((FLASH->CR2), FLASH_CR_PSIZE))
+#endif /* FLASH_CR_PSIZE */
+
+/**
+  * @brief  Set the FLASH Programming Delay.
+  * @param  __DELAY__ FLASH Programming Delay
+  *         This parameter can be a value of @ref FLASHEx_Programming_Delay
+  * @retval none
+  */
+#define __HAL_FLASH_SET_PROGRAM_DELAY(__DELAY__)  MODIFY_REG(FLASH->ACR, FLASH_ACR_WRHIGHFREQ, (__DELAY__))
+
+/**
+  * @brief  Get the FLASH Programming Delay.
+  * @retval FLASH Programming Delay
+  *         This return value can be a value of @ref FLASHEx_Programming_Delay
+  */
+#define __HAL_FLASH_GET_PROGRAM_DELAY()     READ_BIT(FLASH->ACR, FLASH_ACR_WRHIGHFREQ)
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASHEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup FLASHEx_Exported_Functions_Group1
+  * @{
+  */
+/* Extension Program operation functions  *************************************/
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError);
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
+void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
+
+HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank1(void);
+HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1(void);
+HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank2(void);
+HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank2(void);
+
+HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_t *CRC_Result);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros
+  * @{
+  */
+
+/** @defgroup FLASHEx_IS_FLASH_Definitions FLASHEx Private macros to check input parameters
+  * @{
+  */
+
+#define IS_FLASH_TYPEERASE(VALUE)        (((VALUE) == FLASH_TYPEERASE_SECTORS) || \
+                                          ((VALUE) == FLASH_TYPEERASE_MASSERASE))
+
+#if defined (FLASH_CR_PSIZE)
+#define IS_VOLTAGERANGE(RANGE)           (((RANGE) == FLASH_VOLTAGE_RANGE_1) || \
+                                          ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \
+                                          ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \
+                                          ((RANGE) == FLASH_VOLTAGE_RANGE_4))
+#endif /* FLASH_CR_PSIZE */
+
+#define IS_WRPSTATE(VALUE)               (((VALUE) == OB_WRPSTATE_DISABLE) || \
+                                          ((VALUE) == OB_WRPSTATE_ENABLE))
+
+#if defined (FLASH_OPTSR_VDDMMC_HSLV)
+#define IS_OPTIONBYTE(VALUE)             (((VALUE) <= 0x03FFU) && ((VALUE) != 0U))
+#elif defined (DUAL_CORE)
+#define IS_OPTIONBYTE(VALUE)             (((VALUE) <= 0x3FFFU) && ((VALUE) != 0U))
+#else
+#define IS_OPTIONBYTE(VALUE)             (((VALUE) <= 0x01FFU) && ((VALUE) != 0U))
+#endif /*DUAL_CORE*/
+
+#define IS_OB_BOOT_ADDRESS(ADDRESS)      ((ADDRESS) <= 0x8013U)
+
+#define IS_OB_RDP_LEVEL(LEVEL)           (((LEVEL) == OB_RDP_LEVEL_0)   ||\
+                                          ((LEVEL) == OB_RDP_LEVEL_1)   ||\
+                                          ((LEVEL) == OB_RDP_LEVEL_2))
+
+#define IS_OB_WWDG_SOURCE(SOURCE)        (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW))
+
+#define IS_OB_IWDG_SOURCE(SOURCE)        (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+
+#define IS_OB_STOP_SOURCE(SOURCE)        (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
+
+#define IS_OB_STDBY_SOURCE(SOURCE)       (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
+
+#define IS_OB_IWDG_STOP_FREEZE(FREEZE)   (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE))
+
+#define IS_OB_IWDG_STDBY_FREEZE(FREEZE)  (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE))
+
+#define IS_OB_BOR_LEVEL(LEVEL)           (((LEVEL) == OB_BOR_LEVEL0) || ((LEVEL) == OB_BOR_LEVEL1) || \
+                                          ((LEVEL) == OB_BOR_LEVEL2) || ((LEVEL) == OB_BOR_LEVEL3))
+
+#define IS_FLASH_LATENCY(LATENCY)        (((LATENCY) == FLASH_LATENCY_0)  || \
+                                          ((LATENCY) == FLASH_LATENCY_1)  || \
+                                          ((LATENCY) == FLASH_LATENCY_2)  || \
+                                          ((LATENCY) == FLASH_LATENCY_3)  || \
+                                          ((LATENCY) == FLASH_LATENCY_4)  || \
+                                          ((LATENCY) == FLASH_LATENCY_5)  || \
+                                          ((LATENCY) == FLASH_LATENCY_6)  || \
+                                          ((LATENCY) == FLASH_LATENCY_7)  || \
+                                          ((LATENCY) == FLASH_LATENCY_8)  || \
+                                          ((LATENCY) == FLASH_LATENCY_9)  || \
+                                          ((LATENCY) == FLASH_LATENCY_10) || \
+                                          ((LATENCY) == FLASH_LATENCY_11) || \
+                                          ((LATENCY) == FLASH_LATENCY_12) || \
+                                          ((LATENCY) == FLASH_LATENCY_13) || \
+                                          ((LATENCY) == FLASH_LATENCY_14) || \
+                                          ((LATENCY) == FLASH_LATENCY_15))
+
+#define IS_FLASH_SECTOR(SECTOR)          ((SECTOR) < FLASH_SECTOR_TOTAL)
+
+#if (FLASH_SECTOR_TOTAL == 8U)
+#define IS_OB_WRP_SECTOR(SECTOR)         ((((SECTOR) & 0xFFFFFF00U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
+#else
+#define IS_OB_WRP_SECTOR(SECTOR)         ((SECTOR) != 0x00000000U)
+#endif /* FLASH_SECTOR_TOTAL == 8U */
+
+#define IS_OB_PCROP_RDP(CONFIG)          (((CONFIG) == OB_PCROP_RDP_NOT_ERASE) || \
+                                          ((CONFIG) == OB_PCROP_RDP_ERASE))
+
+#define IS_OB_SECURE_RDP(CONFIG)         (((CONFIG) == OB_SECURE_RDP_NOT_ERASE) || \
+                                          ((CONFIG) == OB_SECURE_RDP_ERASE))
+
+#define IS_OB_USER_SWAP_BANK(VALUE)      (((VALUE) == OB_SWAP_BANK_DISABLE) || ((VALUE) == OB_SWAP_BANK_ENABLE))
+
+#define IS_OB_USER_IOHSLV(VALUE)         (((VALUE) == OB_IOHSLV_DISABLE) || ((VALUE) == OB_IOHSLV_ENABLE))
+
+#if defined (FLASH_OPTSR_VDDMMC_HSLV)
+#define IS_OB_USER_VDDMMC_HSLV(VALUE)    (((VALUE) == OB_VDDMMC_HSLV_DISABLE) || ((VALUE) == OB_VDDMMC_HSLV_ENABLE))
+#endif /* FLASH_OPTSR_VDDMMC_HSLV */
+
+#define IS_OB_IWDG1_SOURCE(SOURCE)       (((SOURCE) == OB_IWDG1_SW) || ((SOURCE) == OB_IWDG1_HW))
+#if defined (DUAL_CORE)
+#define IS_OB_IWDG2_SOURCE(SOURCE)       (((SOURCE) == OB_IWDG2_SW) || ((SOURCE) == OB_IWDG2_HW))
+#endif /* DUAL_CORE */
+#define IS_OB_STOP_D1_RESET(VALUE)       (((VALUE) == OB_STOP_NO_RST_D1) || ((VALUE) == OB_STOP_RST_D1))
+
+#define IS_OB_STDBY_D1_RESET(VALUE)      (((VALUE) == OB_STDBY_NO_RST_D1) || ((VALUE) == OB_STDBY_RST_D1))
+
+#define IS_OB_USER_IWDG_STOP(VALUE)      (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_ACTIVE))
+
+#define IS_OB_USER_IWDG_STDBY(VALUE)     (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_ACTIVE))
+
+#define IS_OB_USER_ST_RAM_SIZE(VALUE)    (((VALUE) == OB_ST_RAM_SIZE_2KB) || ((VALUE) == OB_ST_RAM_SIZE_4KB) || \
+                                          ((VALUE) == OB_ST_RAM_SIZE_8KB) || ((VALUE) == OB_ST_RAM_SIZE_16KB))
+
+#define IS_OB_USER_SECURITY(VALUE)       (((VALUE) == OB_SECURITY_ENABLE) || ((VALUE) == OB_SECURITY_DISABLE))
+
+#if defined (DUAL_CORE)
+#define IS_OB_USER_BCM4(VALUE)           (((VALUE) == OB_BCM4_DISABLE) || ((VALUE) == OB_BCM4_ENABLE))
+
+#define IS_OB_USER_BCM7(VALUE)           (((VALUE) == OB_BCM7_DISABLE) || ((VALUE) == OB_BCM7_ENABLE))
+
+#define IS_OB_STOP_D2_RESET(VALUE)       (((VALUE) == OB_STOP_NO_RST_D2) || ((VALUE) == OB_STOP_RST_D2))
+
+#define IS_OB_STDBY_D2_RESET(VALUE)      (((VALUE) == OB_STDBY_NO_RST_D2) || ((VALUE) == OB_STDBY_RST_D2))
+#endif /* DUAL_CORE */
+#if defined (DUAL_CORE)
+#define IS_OB_USER_TYPE(TYPE)            (((TYPE) <= (uint32_t)0x3FFFU) && ((TYPE) != 0U))
+#else
+#define IS_OB_USER_TYPE(TYPE)            (((TYPE) <= (uint32_t)0x73FU) && ((TYPE) != 0U))
+#endif /* DUAL_CORE */
+
+#define IS_OB_BOOT_ADD_OPTION(VALUE)     (((VALUE) == OB_BOOT_ADD0)  || \
+                                          ((VALUE) == OB_BOOT_ADD1)  || \
+                                          ((VALUE) == OB_BOOT_ADD_BOTH))
+
+#define IS_FLASH_TYPECRC(VALUE)          (((VALUE) == FLASH_CRC_ADDR)    || \
+                                          ((VALUE) == FLASH_CRC_SECTORS) || \
+                                          ((VALUE) == FLASH_CRC_BANK))
+
+#if defined (FLASH_OTPBL_LOCKBL)
+#define IS_OTP_BLOCK(VALUE)              ((((VALUE) & 0xFFFF0000U) == 0x00000000U) && ((VALUE) != 0x00000000U))
+#endif /* FLASH_OTPBL_LOCKBL */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
+  * @{
+  */
+void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_FLASH_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h
new file mode 100644
index 00000000..c1855665
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h
@@ -0,0 +1,346 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_gpio.h
+  * @author  MCD Application Team
+  * @brief   Header file of GPIO HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_GPIO_H
+#define STM32H7xx_HAL_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup GPIO
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Types GPIO Exported Types
+  * @{
+  */
+
+/**
+  * @brief   GPIO Init structure definition
+  */
+typedef struct
+{
+  uint32_t Pin;       /*!< Specifies the GPIO pins to be configured.
+                           This parameter can be any value of @ref GPIO_pins_define */
+
+  uint32_t Mode;      /*!< Specifies the operating mode for the selected pins.
+                           This parameter can be a value of @ref GPIO_mode_define */
+
+  uint32_t Pull;      /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
+                           This parameter can be a value of @ref GPIO_pull_define */
+
+  uint32_t Speed;     /*!< Specifies the speed for the selected pins.
+                           This parameter can be a value of @ref GPIO_speed_define */
+
+  uint32_t Alternate;  /*!< Peripheral to be connected to the selected pins.
+                            This parameter can be a value of @ref GPIO_Alternate_function_selection */
+} GPIO_InitTypeDef;
+
+/**
+  * @brief  GPIO Bit SET and Bit RESET enumeration
+  */
+typedef enum
+{
+  GPIO_PIN_RESET = 0U,
+  GPIO_PIN_SET
+} GPIO_PinState;
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Constants  GPIO Exported Constants
+  * @{
+  */
+
+/** @defgroup GPIO_pins_define  GPIO pins define
+  * @{
+  */
+#define GPIO_PIN_0                 ((uint16_t)0x0001)  /* Pin 0 selected    */
+#define GPIO_PIN_1                 ((uint16_t)0x0002)  /* Pin 1 selected    */
+#define GPIO_PIN_2                 ((uint16_t)0x0004)  /* Pin 2 selected    */
+#define GPIO_PIN_3                 ((uint16_t)0x0008)  /* Pin 3 selected    */
+#define GPIO_PIN_4                 ((uint16_t)0x0010)  /* Pin 4 selected    */
+#define GPIO_PIN_5                 ((uint16_t)0x0020)  /* Pin 5 selected    */
+#define GPIO_PIN_6                 ((uint16_t)0x0040)  /* Pin 6 selected    */
+#define GPIO_PIN_7                 ((uint16_t)0x0080)  /* Pin 7 selected    */
+#define GPIO_PIN_8                 ((uint16_t)0x0100)  /* Pin 8 selected    */
+#define GPIO_PIN_9                 ((uint16_t)0x0200)  /* Pin 9 selected    */
+#define GPIO_PIN_10                ((uint16_t)0x0400)  /* Pin 10 selected   */
+#define GPIO_PIN_11                ((uint16_t)0x0800)  /* Pin 11 selected   */
+#define GPIO_PIN_12                ((uint16_t)0x1000)  /* Pin 12 selected   */
+#define GPIO_PIN_13                ((uint16_t)0x2000)  /* Pin 13 selected   */
+#define GPIO_PIN_14                ((uint16_t)0x4000)  /* Pin 14 selected   */
+#define GPIO_PIN_15                ((uint16_t)0x8000)  /* Pin 15 selected   */
+#define GPIO_PIN_All               ((uint16_t)0xFFFF)  /* All pins selected */
+
+#define GPIO_PIN_MASK              (0x0000FFFFU) /* PIN mask for assert test */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_mode_define  GPIO mode define
+  * @brief GPIO Configuration Mode
+  *        Elements values convention: 0xX0yz00YZ
+  *           - X  : GPIO mode or EXTI Mode
+  *           - y  : External IT or Event trigger detection
+  *           - z  : IO configuration on External IT or Event
+  *           - Y  : Output type (Push Pull or Open Drain)
+  *           - Z  : IO Direction mode (Input, Output, Alternate or Analog)
+  * @{
+  */
+#define  GPIO_MODE_INPUT                        (0x00000000U)   /*!< Input Floating Mode                   */
+#define  GPIO_MODE_OUTPUT_PP                    (0x00000001U)   /*!< Output Push Pull Mode                 */
+#define  GPIO_MODE_OUTPUT_OD                    (0x00000011U)   /*!< Output Open Drain Mode                */
+#define  GPIO_MODE_AF_PP                        (0x00000002U)   /*!< Alternate Function Push Pull Mode     */
+#define  GPIO_MODE_AF_OD                        (0x00000012U)   /*!< Alternate Function Open Drain Mode    */
+
+#define  GPIO_MODE_ANALOG                       (0x00000003U)   /*!< Analog Mode  */
+
+#define  GPIO_MODE_IT_RISING                    (0x11110000U)   /*!< External Interrupt Mode with Rising edge trigger detection          */
+#define  GPIO_MODE_IT_FALLING                   (0x11210000U)   /*!< External Interrupt Mode with Falling edge trigger detection         */
+#define  GPIO_MODE_IT_RISING_FALLING            (0x11310000U)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */
+
+#define  GPIO_MODE_EVT_RISING                   (0x11120000U)   /*!< External Event Mode with Rising edge trigger detection               */
+#define  GPIO_MODE_EVT_FALLING                  (0x11220000U)   /*!< External Event Mode with Falling edge trigger detection              */
+#define  GPIO_MODE_EVT_RISING_FALLING           (0x11320000U)   /*!< External Event Mode with Rising/Falling edge trigger detection       */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_speed_define  GPIO speed define
+  * @brief GPIO Output Maximum frequency
+  * @{
+  */
+#define  GPIO_SPEED_FREQ_LOW         (0x00000000U)  /*!< Low speed     */
+#define  GPIO_SPEED_FREQ_MEDIUM      (0x00000001U)  /*!< Medium speed  */
+#define  GPIO_SPEED_FREQ_HIGH        (0x00000002U)  /*!< Fast speed    */
+#define  GPIO_SPEED_FREQ_VERY_HIGH   (0x00000003U)  /*!< High speed    */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_pull_define  GPIO pull define
+  * @brief GPIO Pull-Up or Pull-Down Activation
+  * @{
+  */
+#define  GPIO_NOPULL        (0x00000000U)   /*!< No Pull-up or Pull-down activation  */
+#define  GPIO_PULLUP        (0x00000001U)   /*!< Pull-up activation                  */
+#define  GPIO_PULLDOWN      (0x00000002U)   /*!< Pull-down activation                */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
+  * @{
+  */
+
+/**
+  * @brief  Checks whether the specified EXTI line flag is set or not.
+  * @param  __EXTI_LINE__: specifies the EXTI line flag to check.
+  *         This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval The new state of __EXTI_LINE__ (SET or RESET).
+  */
+#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
+
+/**
+  * @brief  Clears the EXTI's line pending flags.
+  * @param  __EXTI_LINE__: specifies the EXTI lines flags to clear.
+  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
+
+/**
+  * @brief  Checks whether the specified EXTI line is asserted or not.
+  * @param  __EXTI_LINE__: specifies the EXTI line to check.
+  *          This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval The new state of __EXTI_LINE__ (SET or RESET).
+  */
+#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
+
+/**
+  * @brief  Clears the EXTI's line pending bits.
+  * @param  __EXTI_LINE__: specifies the EXTI lines to clear.
+  *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Checks whether the specified EXTI line flag is set or not.
+  * @param  __EXTI_LINE__: specifies the EXTI line flag to check.
+  *         This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval The new state of __EXTI_LINE__ (SET or RESET).
+  */
+#define __HAL_GPIO_EXTID2_GET_FLAG(__EXTI_LINE__) (EXTI->C2PR1 & (__EXTI_LINE__))
+
+/**
+  * @brief  Clears the EXTI's line pending flags.
+  * @param  __EXTI_LINE__: specifies the EXTI lines flags to clear.
+  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTID2_CLEAR_FLAG(__EXTI_LINE__) (EXTI->C2PR1 = (__EXTI_LINE__))
+
+/**
+  * @brief  Checks whether the specified EXTI line is asserted or not.
+  * @param  __EXTI_LINE__: specifies the EXTI line to check.
+  *          This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval The new state of __EXTI_LINE__ (SET or RESET).
+  */
+#define __HAL_GPIO_EXTID2_GET_IT(__EXTI_LINE__) (EXTI->C2PR1 & (__EXTI_LINE__))
+
+/**
+  * @brief  Clears the EXTI's line pending bits.
+  * @param  __EXTI_LINE__: specifies the EXTI lines to clear.
+  *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTID2_CLEAR_IT(__EXTI_LINE__) (EXTI->C2PR1 = (__EXTI_LINE__))
+#endif
+
+/**
+  * @brief  Generates a Software interrupt on selected EXTI line.
+  * @param  __EXTI_LINE__: specifies the EXTI line to check.
+  *          This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__))
+/**
+  * @}
+  */
+
+/* Include GPIO HAL Extension module */
+#include "stm32h7xx_hal_gpio_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup GPIO_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup GPIO_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de-initialization functions *****************************/
+void  HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init);
+void  HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin);
+/**
+  * @}
+  */
+
+/** @addtogroup GPIO_Exported_Functions_Group2
+  * @{
+  */
+/* IO operation functions *****************************************************/
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
+void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup GPIO_Private_Constants GPIO Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup GPIO_Private_Macros GPIO Private Macros
+  * @{
+  */
+#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
+#define IS_GPIO_PIN(__PIN__)        ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
+                                     (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT)              ||\
+                            ((MODE) == GPIO_MODE_OUTPUT_PP)          ||\
+                            ((MODE) == GPIO_MODE_OUTPUT_OD)          ||\
+                            ((MODE) == GPIO_MODE_AF_PP)              ||\
+                            ((MODE) == GPIO_MODE_AF_OD)              ||\
+                            ((MODE) == GPIO_MODE_IT_RISING)          ||\
+                            ((MODE) == GPIO_MODE_IT_FALLING)         ||\
+                            ((MODE) == GPIO_MODE_IT_RISING_FALLING)  ||\
+                            ((MODE) == GPIO_MODE_EVT_RISING)         ||\
+                            ((MODE) == GPIO_MODE_EVT_FALLING)        ||\
+                            ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
+                            ((MODE) == GPIO_MODE_ANALOG))
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW)  || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \
+                              ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH))
+
+#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
+                            ((PULL) == GPIO_PULLDOWN))
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup GPIO_Private_Functions GPIO Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_GPIO_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h
new file mode 100644
index 00000000..ff2efb3c
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h
@@ -0,0 +1,428 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_gpio_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of GPIO HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_GPIO_EX_H
+#define STM32H7xx_HAL_GPIO_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup GPIOEx GPIOEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants
+  * @{
+  */
+
+/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection
+  * @{
+  */
+
+/**
+  * @brief   AF 0 selection
+  */
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                                                     */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping                                          */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping                                           */
+#define GPIO_AF0_LCDBIAS       ((uint8_t)0x00)  /* LCDBIAS Alternate Function mapping                                                      */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                                                        */
+#if defined (PWR_CPUCR_PDDS_D2) /* PWR D1 and D2 domains exists */
+#define GPIO_AF0_C1DSLEEP      ((uint8_t)0x00)  /* Cortex-M7 Deep Sleep Alternate Function mapping : available on STM32H7 Rev.B and above  */
+#define GPIO_AF0_C1SLEEP       ((uint8_t)0x00)  /* Cortex-M7 Sleep Alternate Function mapping : available on STM32H7 Rev.B and above       */
+#define GPIO_AF0_D1PWREN       ((uint8_t)0x00)  /* Domain 1 PWR enable Alternate Function mapping : available on STM32H7 Rev.B and above   */
+#define GPIO_AF0_D2PWREN       ((uint8_t)0x00)  /* Domain 2 PWR enable Alternate Function mapping : available on STM32H7 Rev.B and above   */
+#if defined(DUAL_CORE)
+#define GPIO_AF0_C2DSLEEP      ((uint8_t)0x00)  /* Cortex-M4 Deep Sleep Alternate Function mapping : available on STM32H7 Rev.B and above  */
+#define GPIO_AF0_C2SLEEP       ((uint8_t)0x00)  /* Cortex-M4 Sleep Alternate Function mapping : available on STM32H7 Rev.B and above       */
+#endif /* DUAL_CORE */
+#endif /* PWR_CPUCR_PDDS_D2 */
+
+/**
+  * @brief   AF 1 selection
+  */
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping   */
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping   */
+#define GPIO_AF1_TIM16         ((uint8_t)0x01)  /* TIM16 Alternate Function mapping  */
+#define GPIO_AF1_TIM17         ((uint8_t)0x01)  /* TIM17 Alternate Function mapping  */
+#define GPIO_AF1_LPTIM1        ((uint8_t)0x01)  /* LPTIM1 Alternate Function mapping */
+#if defined(HRTIM1)
+#define GPIO_AF1_HRTIM1        ((uint8_t)0x01)  /* HRTIM1 Alternate Function mapping */
+#endif /* HRTIM1 */
+
+/**
+  * @brief   AF 2 selection
+  */
+#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping   */
+#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping   */
+#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping   */
+#define GPIO_AF2_TIM12         ((uint8_t)0x02)  /* TIM12 Alternate Function mapping  */
+#define GPIO_AF2_SAI1          ((uint8_t)0x02)  /* SAI1 Alternate Function mapping   */
+#if defined(HRTIM1)
+#define GPIO_AF2_HRTIM1        ((uint8_t)0x02)  /* HRTIM1 Alternate Function mapping */
+#endif /* HRTIM1 */
+#define GPIO_AF2_TIM15         ((uint8_t)0x02)  /* TIM15 Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx */
+
+/**
+  * @brief   AF 3 selection
+  */
+#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping   */
+#define GPIO_AF3_LPTIM2        ((uint8_t)0x03)  /* LPTIM2 Alternate Function mapping */
+#define GPIO_AF3_DFSDM1        ((uint8_t)0x03)  /* DFSDM Alternate Function mapping  */
+#define GPIO_AF3_LPTIM3        ((uint8_t)0x03)  /* LPTIM3 Alternate Function mapping */
+#define GPIO_AF3_LPTIM4        ((uint8_t)0x03)  /* LPTIM4 Alternate Function mapping */
+#define GPIO_AF3_LPTIM5        ((uint8_t)0x03)  /* LPTIM5 Alternate Function mapping */
+#define GPIO_AF3_LPUART        ((uint8_t)0x03)  /* LPUART Alternate Function mapping */
+#if defined(OCTOSPIM)
+#define GPIO_AF3_OCTOSPIM_P1   ((uint8_t)0x03)  /* OCTOSPI Manager Port 1 Alternate Function mapping */
+#define GPIO_AF3_OCTOSPIM_P2   ((uint8_t)0x03)  /* OCTOSPI Manager Port 2 Alternate Function mapping */
+#endif /* OCTOSPIM */
+#if defined(HRTIM1)
+#define GPIO_AF3_HRTIM1        ((uint8_t)0x03)  /* HRTIM1 Alternate Function mapping */
+#endif /* HRTIM1 */
+
+/**
+  * @brief   AF 4 selection
+  */
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping   */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping   */
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping   */
+#define GPIO_AF4_I2C4          ((uint8_t)0x04)  /* I2C4 Alternate Function mapping   */
+#define GPIO_AF4_TIM15         ((uint8_t)0x04)  /* TIM15 Alternate Function mapping  */
+#define GPIO_AF4_CEC           ((uint8_t)0x04)  /* CEC Alternate Function mapping    */
+#define GPIO_AF4_LPTIM2        ((uint8_t)0x04)  /* LPTIM2 Alternate Function mapping */
+#define GPIO_AF4_USART1        ((uint8_t)0x04)  /* USART1 Alternate Function mapping */
+#define GPIO_AF4_DFSDM1        ((uint8_t)0x04)  /* DFSDM  Alternate Function mapping */
+#if defined(DFSDM2_BASE)
+#define GPIO_AF4_DFSDM2        ((uint8_t)0x04)  /* DFSDM2 Alternate Function mapping */
+#endif /* DFSDM2_BASE */
+#if defined(PSSI)
+#define GPIO_AF4_PSSI          ((uint8_t)0x04)  /* PSSI Alternate Function mapping   */
+#endif /* PSSI */
+
+/**
+  * @brief   AF 5 selection
+  */
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping   */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2 Alternate Function mapping   */
+#define GPIO_AF5_SPI3          ((uint8_t)0x05)  /* SPI3 Alternate Function mapping   */
+#define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4 Alternate Function mapping   */
+#define GPIO_AF5_SPI5          ((uint8_t)0x05)  /* SPI5 Alternate Function mapping   */
+#define GPIO_AF5_SPI6          ((uint8_t)0x05)  /* SPI6 Alternate Function mapping   */
+#define GPIO_AF5_CEC           ((uint8_t)0x05)  /* CEC  Alternate Function mapping   */
+
+/**
+  * @brief   AF 6 selection
+  */
+#define GPIO_AF6_SPI2          ((uint8_t)0x06)  /* SPI2 Alternate Function mapping   */
+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3 Alternate Function mapping   */
+#define GPIO_AF6_SAI1          ((uint8_t)0x06)  /* SAI1 Alternate Function mapping   */
+#define GPIO_AF6_I2C4          ((uint8_t)0x06)  /* I2C4 Alternate Function mapping   */
+#define GPIO_AF6_DFSDM1        ((uint8_t)0x06)  /* DFSDM Alternate Function mapping  */
+#define GPIO_AF6_UART4         ((uint8_t)0x06)  /* UART4 Alternate Function mapping  */
+#if defined(DFSDM2_BASE)
+#define GPIO_AF6_DFSDM2        ((uint8_t)0x06)  /* DFSDM2 Alternate Function mapping */
+#endif /* DFSDM2_BASE */
+#if defined(SAI3)
+#define GPIO_AF6_SAI3          ((uint8_t)0x06)  /* SAI3 Alternate Function mapping   */
+#endif /* SAI3 */
+#if defined(OCTOSPIM)
+#define GPIO_AF6_OCTOSPIM_P1   ((uint8_t)0x06)  /* OCTOSPI Manager Port 1 Alternate Function mapping */
+#endif /* OCTOSPIM */
+
+/**
+  * @brief   AF 7 selection
+  */
+#define GPIO_AF7_SPI2          ((uint8_t)0x07)  /* SPI2 Alternate Function mapping   */
+#define GPIO_AF7_SPI3          ((uint8_t)0x07)  /* SPI3 Alternate Function mapping   */
+#define GPIO_AF7_SPI6          ((uint8_t)0x07)  /* SPI6 Alternate Function mapping   */
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping */
+#define GPIO_AF7_USART6        ((uint8_t)0x07)  /* USART6 Alternate Function mapping */
+#define GPIO_AF7_UART7         ((uint8_t)0x07)  /* UART7 Alternate Function mapping  */
+#define GPIO_AF7_DFSDM1        ((uint8_t)0x07)  /* DFSDM Alternate Function mapping  */
+#define GPIO_AF7_SDMMC1        ((uint8_t)0x07)  /* SDMMC1 Alternate Function mapping */
+
+/**
+  * @brief   AF 8 selection
+  */
+#define GPIO_AF8_SPI6          ((uint8_t)0x08)  /* SPI6 Alternate Function mapping   */
+#define GPIO_AF8_SAI2          ((uint8_t)0x08)  /* SAI2 Alternate Function mapping   */
+#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */
+#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */
+#define GPIO_AF8_UART8         ((uint8_t)0x08)  /* UART8 Alternate Function mapping  */
+#define GPIO_AF8_SPDIF         ((uint8_t)0x08)  /* SPDIF Alternate Function mapping  */
+#define GPIO_AF8_LPUART        ((uint8_t)0x08)  /* LPUART Alternate Function mapping */
+#define GPIO_AF8_SDMMC1        ((uint8_t)0x08)  /* SDMMC1 Alternate Function mapping */
+#if defined(SAI4)
+#define GPIO_AF8_SAI4          ((uint8_t)0x08)  /* SAI4 Alternate Function mapping   */
+#endif /* SAI4 */
+
+/**
+  * @brief   AF 9 selection
+  */
+#define GPIO_AF9_FDCAN1        ((uint8_t)0x09)  /* FDCAN1 Alternate Function mapping   */
+#define GPIO_AF9_FDCAN2        ((uint8_t)0x09)  /* FDCAN2 Alternate Function mapping   */
+#define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping    */
+#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping    */
+#define GPIO_AF9_SDMMC2        ((uint8_t)0x09)  /* SDMMC2 Alternate Function mapping   */
+#define GPIO_AF9_LTDC          ((uint8_t)0x09)  /* LTDC Alternate Function mapping     */
+#define GPIO_AF9_SPDIF         ((uint8_t)0x09)  /* SPDIF Alternate Function mapping    */
+#define GPIO_AF9_FMC           ((uint8_t)0x09)  /* FMC Alternate Function mapping      */
+#if defined(QUADSPI)
+#define GPIO_AF9_QUADSPI       ((uint8_t)0x09)  /* QUADSPI Alternate Function mapping  */
+#endif /* QUADSPI */
+#if defined(SAI4)
+#define GPIO_AF9_SAI4          ((uint8_t)0x09)  /* SAI4 Alternate Function mapping     */
+#endif /* SAI4 */
+#if defined(OCTOSPIM)
+#define GPIO_AF9_OCTOSPIM_P1   ((uint8_t)0x09)  /* OCTOSPI Manager Port 1 Alternate Function mapping */
+#define GPIO_AF9_OCTOSPIM_P2   ((uint8_t)0x09)  /* OCTOSPI Manager Port 2 Alternate Function mapping */
+#endif /* OCTOSPIM */
+
+/**
+  * @brief   AF 10 selection
+  */
+#define GPIO_AF10_SAI2          ((uint8_t)0x0A)  /* SAI2 Alternate Function mapping                                             */
+#define GPIO_AF10_SDMMC2        ((uint8_t)0x0A)  /* SDMMC2 Alternate Function mapping                                           */
+#if defined(USB2_OTG_FS)
+#define GPIO_AF10_OTG2_FS       ((uint8_t)0x0A)  /* OTG2_FS Alternate Function mapping                                          */
+#endif /*USB2_OTG_FS*/
+#define GPIO_AF10_COMP1         ((uint8_t)0x0A)  /* COMP1 Alternate Function mapping                                            */
+#define GPIO_AF10_COMP2         ((uint8_t)0x0A)  /* COMP2 Alternate Function mapping                                            */
+#if defined(LTDC)
+#define GPIO_AF10_LTDC          ((uint8_t)0x0A)  /* LTDC Alternate Function mapping                                             */
+#endif /*LTDC*/
+#define GPIO_AF10_CRS_SYNC      ((uint8_t)0x0A)  /* CRS Sync Alternate Function mapping : available on STM32H7 Rev.B and above  */
+#if defined(QUADSPI)
+#define GPIO_AF10_QUADSPI       ((uint8_t)0x0A)  /* QUADSPI Alternate Function mapping                                          */
+#endif /* QUADSPI */
+#if defined(SAI4)
+#define GPIO_AF10_SAI4          ((uint8_t)0x0A)  /* SAI4 Alternate Function mapping                                             */
+#endif /* SAI4 */
+#if !defined(USB2_OTG_FS)
+#define GPIO_AF10_OTG1_FS       ((uint8_t)0x0A)  /* OTG1_FS Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx */
+#endif /* !USB2_OTG_FS */
+#define GPIO_AF10_OTG1_HS       ((uint8_t)0x0A)  /* OTG1_HS Alternate Function mapping                                          */
+#if defined(OCTOSPIM)
+#define GPIO_AF10_OCTOSPIM_P1   ((uint8_t)0x0A)  /* OCTOSPI Manager Port 1 Alternate Function mapping */
+#endif /* OCTOSPIM */
+#define GPIO_AF10_TIM8          ((uint8_t)0x0A)  /* TIM8 Alternate Function mapping                                             */
+
+/**
+  * @brief   AF 11 selection
+  */
+#define GPIO_AF11_SWP           ((uint8_t)0x0B)  /* SWP Alternate Function mapping     */
+#define GPIO_AF11_MDIOS         ((uint8_t)0x0B)  /* MDIOS Alternate Function mapping   */
+#define GPIO_AF11_UART7         ((uint8_t)0x0B)  /* UART7 Alternate Function mapping   */
+#define GPIO_AF11_SDMMC2        ((uint8_t)0x0B)  /* SDMMC2 Alternate Function mapping  */
+#define GPIO_AF11_DFSDM1        ((uint8_t)0x0B)  /* DFSDM1 Alternate Function mapping  */
+#define GPIO_AF11_COMP1         ((uint8_t)0x0B)  /* COMP1 Alternate Function mapping   */
+#define GPIO_AF11_COMP2         ((uint8_t)0x0B)  /* COMP2 Alternate Function mapping   */
+#define GPIO_AF11_TIM1          ((uint8_t)0x0B)  /* TIM1 Alternate Function mapping    */
+#define GPIO_AF11_TIM8          ((uint8_t)0x0B)  /* TIM8 Alternate Function mapping    */
+#define GPIO_AF11_I2C4          ((uint8_t)0x0B)  /* I2C4 Alternate Function mapping    */
+#if defined(DFSDM2_BASE)
+#define GPIO_AF11_DFSDM2        ((uint8_t)0x0B)  /* DFSDM2 Alternate Function mapping  */
+#endif /* DFSDM2_BASE */
+#if defined(USART10)
+#define GPIO_AF11_USART10       ((uint8_t)0x0B)  /* USART10 Alternate Function mapping */
+#endif /* USART10 */
+#if defined(UART9)
+#define GPIO_AF11_UART9         ((uint8_t)0x0B)  /* UART9 Alternate Function mapping   */
+#endif /* UART9 */
+#if defined(ETH)
+#define GPIO_AF11_ETH           ((uint8_t)0x0B)  /* ETH Alternate Function mapping     */
+#endif /* ETH */
+#if defined(LTDC)
+#define GPIO_AF11_LTDC          ((uint8_t)0x0B)  /* LTDC Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx  */
+#endif /*LTDC*/
+#if defined(OCTOSPIM)
+#define GPIO_AF11_OCTOSPIM_P1   ((uint8_t)0x0B)  /* OCTOSPI Manager Port 1 Alternate Function mapping */
+#endif /* OCTOSPIM */
+
+/**
+  * @brief   AF 12 selection
+  */
+#define GPIO_AF12_FMC           ((uint8_t)0x0C)  /* FMC Alternate Function mapping     */
+#define GPIO_AF12_SDMMC1        ((uint8_t)0x0C)  /* SDMMC1 Alternate Function mapping  */
+#define GPIO_AF12_MDIOS         ((uint8_t)0x0C)  /* MDIOS Alternate Function mapping   */
+#define GPIO_AF12_COMP1         ((uint8_t)0x0C)  /* COMP1 Alternate Function mapping   */
+#define GPIO_AF12_COMP2         ((uint8_t)0x0C)  /* COMP2 Alternate Function mapping   */
+#define GPIO_AF12_TIM1          ((uint8_t)0x0C)  /* TIM1 Alternate Function mapping    */
+#define GPIO_AF12_TIM8          ((uint8_t)0x0C)  /* TIM8 Alternate Function mapping    */
+#if defined(LTDC)
+#define GPIO_AF12_LTDC          ((uint8_t)0x0C)  /* LTDC Alternate Function mapping    */
+#endif /*LTDC*/
+#if defined(USB2_OTG_FS)
+#define GPIO_AF12_OTG1_FS       ((uint8_t)0x0C)  /* OTG1_FS Alternate Function mapping */
+#endif /* USB2_OTG_FS */
+
+/**
+  * @brief   AF 13 selection
+  */
+#define GPIO_AF13_DCMI          ((uint8_t)0x0D)   /* DCMI Alternate Function mapping  */
+#define GPIO_AF13_COMP1         ((uint8_t)0x0D)   /* COMP1 Alternate Function mapping */
+#define GPIO_AF13_COMP2         ((uint8_t)0x0D)   /* COMP2 Alternate Function mapping */
+#if defined(LTDC)
+#define GPIO_AF13_LTDC          ((uint8_t)0x0D)   /* LTDC Alternate Function mapping  */
+#endif /*LTDC*/
+#if defined(DSI)
+#define GPIO_AF13_DSI           ((uint8_t)0x0D)   /* DSI Alternate Function mapping   */
+#endif /* DSI */
+#if defined(PSSI)
+#define GPIO_AF13_PSSI          ((uint8_t)0x0D)   /* PSSI Alternate Function mapping  */
+#endif /* PSSI */
+#define GPIO_AF13_TIM1          ((uint8_t)0x0D)    /* TIM1 Alternate Function mapping */
+
+/**
+  * @brief   AF 14 selection
+  */
+#define GPIO_AF14_LTDC         ((uint8_t)0x0E)   /* LTDC Alternate Function mapping  */
+#define GPIO_AF14_UART5        ((uint8_t)0x0E)   /* UART5 Alternate Function mapping */
+
+/**
+  * @brief   AF 15 selection
+  */
+#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF)   ((AF) <= (uint8_t)0x0F)
+
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros
+  * @{
+  */
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions
+  * @{
+  */
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup GPIOEx_Private_Constants GPIO Private Constants
+  * @{
+  */
+
+/**
+  * @brief   GPIO pin available on the platform
+  */
+/* Defines the available pins per GPIOs */
+#define GPIOA_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOB_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOC_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOD_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOE_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOF_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOG_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOI_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOJ_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOH_PIN_AVAILABLE  GPIO_PIN_All
+#define GPIOK_PIN_AVAILABLE  (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | \
+                              GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7)
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup GPIOEx_Private_Macros GPIO Private Macros
+  * @{
+  */
+/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index
+  * @{
+  */
+#define GPIO_GET_INDEX(__GPIOx__)  (((__GPIOx__) == (GPIOA))? 0UL :\
+                                    ((__GPIOx__) == (GPIOB))? 1UL :\
+                                    ((__GPIOx__) == (GPIOC))? 2UL :\
+                                    ((__GPIOx__) == (GPIOD))? 3UL :\
+                                    ((__GPIOx__) == (GPIOE))? 4UL :\
+                                    ((__GPIOx__) == (GPIOF))? 5UL :\
+                                    ((__GPIOx__) == (GPIOG))? 6UL :\
+                                    ((__GPIOx__) == (GPIOH))? 7UL :\
+                                    ((__GPIOx__) == (GPIOI))? 8UL :\
+                                    ((__GPIOx__) == (GPIOJ))? 9UL : 10UL)
+/**
+  * @}
+  */
+
+/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function
+  * @{
+  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup GPIOEx_Private_Functions GPIO Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_GPIO_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h
new file mode 100644
index 00000000..1ef97f3d
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h
@@ -0,0 +1,214 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_hsem.h
+  * @author  MCD Application Team
+  * @brief   Header file of HSEM HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_HSEM_H
+#define STM32H7xx_HAL_HSEM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+   * @{
+   */
+
+/** @addtogroup HSEM
+   * @{
+   */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup HSEM_Exported_Macros HSEM Exported Macros
+  * @{
+  */
+
+/**
+  * @brief  SemID to mask helper Macro.
+  * @param  __SEMID__: semaphore ID from 0 to 31
+  * @retval Semaphore Mask.
+  */
+#define __HAL_HSEM_SEMID_TO_MASK(__SEMID__) (1 << (__SEMID__))
+
+/**
+  * @brief  Enables the specified HSEM interrupts.
+  * @param  __SEM_MASK__: semaphores Mask
+  * @retval None.
+  */
+#if defined(DUAL_CORE)
+#define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
+                                            (HSEM->C1IER |= (__SEM_MASK__)) : \
+                                            (HSEM->C2IER |= (__SEM_MASK__)))
+#else
+#define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) (HSEM->IER |= (__SEM_MASK__))
+#endif /* DUAL_CORE */
+/**
+  * @brief  Disables the specified HSEM interrupts.
+  * @param  __SEM_MASK__: semaphores Mask
+  * @retval None.
+  */
+#if defined(DUAL_CORE)
+#define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
+                                             (HSEM->C1IER &= ~(__SEM_MASK__)) :       \
+                                             (HSEM->C2IER &= ~(__SEM_MASK__)))
+#else
+#define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) (HSEM->IER &= ~(__SEM_MASK__))
+#endif /* DUAL_CORE */
+
+/**
+  * @brief  Checks whether interrupt has occurred or not for semaphores specified by a mask.
+  * @param  __SEM_MASK__: semaphores Mask
+  * @retval semaphores Mask : Semaphores where an interrupt occurred.
+  */
+#if defined(DUAL_CORE)
+#define __HAL_HSEM_GET_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
+                                         ((__SEM_MASK__) & HSEM->C1MISR) :        \
+                                         ((__SEM_MASK__) & HSEM->C2MISR1))
+#else
+#define __HAL_HSEM_GET_IT(__SEM_MASK__) ((__SEM_MASK__) & HSEM->MISR)
+#endif /* DUAL_CORE */
+
+/**
+  * @brief  Get the semaphores release status flags.
+  * @param  __SEM_MASK__: semaphores Mask
+  * @retval semaphores Mask : Semaphores where Release flags rise.
+  */
+#if defined(DUAL_CORE)
+#define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
+                                           (__SEM_MASK__) & HSEM->C1ISR :           \
+                                           (__SEM_MASK__) & HSEM->C2ISR)
+#else
+#define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((__SEM_MASK__) & HSEM->ISR)
+#endif /* DUAL_CORE */
+
+/**
+  * @brief  Clears the HSEM Interrupt flags.
+  * @param  __SEM_MASK__: semaphores Mask
+  * @retval None.
+  */
+#if defined(DUAL_CORE)
+#define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
+                                             (HSEM->C1ICR |= (__SEM_MASK__)) :        \
+                                             (HSEM->C2ICR |= (__SEM_MASK__)))
+#else
+#define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) (HSEM->ICR |= (__SEM_MASK__))
+#endif /* DUAL_CORE */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup HSEM_Exported_Functions HSEM Exported Functions
+  * @{
+  */
+
+/** @addtogroup HSEM_Exported_Functions_Group1 Take and Release functions
+  * @brief    HSEM Take and Release functions
+  * @{
+  */
+
+/* HSEM semaphore take (lock) using 2-Step  method ****************************/
+HAL_StatusTypeDef  HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID);
+/* HSEM semaphore fast take (lock) using 1-Step  method ***********************/
+HAL_StatusTypeDef  HAL_HSEM_FastTake(uint32_t SemID);
+/* HSEM Check semaphore state Taken or not   **********************************/
+uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID);
+/* HSEM Release  **************************************************************/
+void  HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID);
+/* HSEM Release All************************************************************/
+void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t CoreID);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HSEM_Exported_Functions_Group2 HSEM Set and Get Key functions
+  * @brief    HSEM Set and Get Key functions.
+  * @{
+  */
+/* HSEM Set Clear Key *********************************************************/
+void  HAL_HSEM_SetClearKey(uint32_t Key);
+/* HSEM Get Clear Key *********************************************************/
+uint32_t HAL_HSEM_GetClearKey(void);
+/**
+  * @}
+  */
+
+/** @addtogroup HSEM_Exported_Functions_Group3
+  * @brief   HSEM Notification functions
+  * @{
+  */
+/* HSEM Activate HSEM Notification (When a semaphore is released) ) *****************/
+void HAL_HSEM_ActivateNotification(uint32_t SemMask);
+/* HSEM Deactivate HSEM Notification (When a semaphore is released)  ****************/
+void HAL_HSEM_DeactivateNotification(uint32_t SemMask);
+/* HSEM Free Callback (When a semaphore is released)  *******************************/
+void HAL_HSEM_FreeCallback(uint32_t SemMask);
+/* HSEM IRQ Handler  **********************************************************/
+void HAL_HSEM_IRQHandler(void);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup HSEM_Private_Macros HSEM Private Macros
+  * @{
+  */
+
+#define IS_HSEM_SEMID(__SEMID__) ((__SEMID__) <= HSEM_SEMID_MAX )
+
+#define IS_HSEM_PROCESSID(__PROCESSID__) ((__PROCESSID__) <= HSEM_PROCESSID_MAX )
+
+#define IS_HSEM_KEY(__KEY__) ((__KEY__) <= HSEM_CLEAR_KEY_MAX )
+
+#if defined(DUAL_CORE)
+#define IS_HSEM_COREID(__COREID__) (((__COREID__) == HSEM_CPU1_COREID) || \
+                                    ((__COREID__) == HSEM_CPU2_COREID))
+#else
+#define IS_HSEM_COREID(__COREID__) ((__COREID__) == HSEM_CPU1_COREID)
+#endif
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_HSEM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h
new file mode 100644
index 00000000..ea2cd885
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h
@@ -0,0 +1,782 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_i2c.h
+  * @author  MCD Application Team
+  * @brief   Header file of I2C HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_I2C_H
+#define STM32H7xx_HAL_I2C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup I2C
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup I2C_Exported_Types I2C Exported Types
+  * @{
+  */
+
+/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
+  * @brief  I2C Configuration Structure definition
+  * @{
+  */
+typedef struct
+{
+  uint32_t Timing;              /*!< Specifies the I2C_TIMINGR_register value.
+                                  This parameter calculated by referring to I2C initialization
+                                         section in Reference manual */
+
+  uint32_t OwnAddress1;         /*!< Specifies the first device own address.
+                                  This parameter can be a 7-bit or 10-bit address. */
+
+  uint32_t AddressingMode;      /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
+                                  This parameter can be a value of @ref I2C_ADDRESSING_MODE */
+
+  uint32_t DualAddressMode;     /*!< Specifies if dual addressing mode is selected.
+                                  This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
+
+  uint32_t OwnAddress2;         /*!< Specifies the second device own address if dual addressing mode is selected
+                                  This parameter can be a 7-bit address. */
+
+  uint32_t OwnAddress2Masks;    /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
+                                  This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
+
+  uint32_t GeneralCallMode;     /*!< Specifies if general call mode is selected.
+                                  This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
+
+  uint32_t NoStretchMode;       /*!< Specifies if nostretch mode is selected.
+                                  This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
+
+} I2C_InitTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_state_structure_definition HAL state structure definition
+  * @brief  HAL State structure definition
+  * @note  HAL I2C State value coding follow below described bitmap :\n
+  *          b7-b6  Error information\n
+  *             00 : No Error\n
+  *             01 : Abort (Abort user request on going)\n
+  *             10 : Timeout\n
+  *             11 : Error\n
+  *          b5     Peripheral initialization status\n
+  *             0  : Reset (peripheral not initialized)\n
+  *             1  : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n
+  *          b4     (not used)\n
+  *             x  : Should be set to 0\n
+  *          b3\n
+  *             0  : Ready or Busy (No Listen mode ongoing)\n
+  *             1  : Listen (peripheral in Address Listen Mode)\n
+  *          b2     Intrinsic process state\n
+  *             0  : Ready\n
+  *             1  : Busy (peripheral busy with some configuration or internal operations)\n
+  *          b1     Rx state\n
+  *             0  : Ready (no Rx operation ongoing)\n
+  *             1  : Busy (Rx operation ongoing)\n
+  *          b0     Tx state\n
+  *             0  : Ready (no Tx operation ongoing)\n
+  *             1  : Busy (Tx operation ongoing)
+  * @{
+  */
+typedef enum
+{
+  HAL_I2C_STATE_RESET             = 0x00U,   /*!< Peripheral is not yet Initialized         */
+  HAL_I2C_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use  */
+  HAL_I2C_STATE_BUSY              = 0x24U,   /*!< An internal process is ongoing            */
+  HAL_I2C_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing      */
+  HAL_I2C_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing         */
+  HAL_I2C_STATE_LISTEN            = 0x28U,   /*!< Address Listen Mode is ongoing            */
+  HAL_I2C_STATE_BUSY_TX_LISTEN    = 0x29U,   /*!< Address Listen Mode and Data Transmission
+                                                 process is ongoing                         */
+  HAL_I2C_STATE_BUSY_RX_LISTEN    = 0x2AU,   /*!< Address Listen Mode and Data Reception
+                                                 process is ongoing                         */
+  HAL_I2C_STATE_ABORT             = 0x60U,   /*!< Abort user request ongoing                */
+  HAL_I2C_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state                             */
+  HAL_I2C_STATE_ERROR             = 0xE0U    /*!< Error                                     */
+
+} HAL_I2C_StateTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_mode_structure_definition HAL mode structure definition
+  * @brief  HAL Mode structure definition
+  * @note  HAL I2C Mode value coding follow below described bitmap :\n
+  *          b7     (not used)\n
+  *             x  : Should be set to 0\n
+  *          b6\n
+  *             0  : None\n
+  *             1  : Memory (HAL I2C communication is in Memory Mode)\n
+  *          b5\n
+  *             0  : None\n
+  *             1  : Slave (HAL I2C communication is in Slave Mode)\n
+  *          b4\n
+  *             0  : None\n
+  *             1  : Master (HAL I2C communication is in Master Mode)\n
+  *          b3-b2-b1-b0  (not used)\n
+  *             xxxx : Should be set to 0000
+  * @{
+  */
+typedef enum
+{
+  HAL_I2C_MODE_NONE               = 0x00U,   /*!< No I2C communication on going             */
+  HAL_I2C_MODE_MASTER             = 0x10U,   /*!< I2C communication is in Master Mode       */
+  HAL_I2C_MODE_SLAVE              = 0x20U,   /*!< I2C communication is in Slave Mode        */
+  HAL_I2C_MODE_MEM                = 0x40U    /*!< I2C communication is in Memory Mode       */
+
+} HAL_I2C_ModeTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Error_Code_definition I2C Error Code definition
+  * @brief  I2C Error Code definition
+  * @{
+  */
+#define HAL_I2C_ERROR_NONE      (0x00000000U)    /*!< No error              */
+#define HAL_I2C_ERROR_BERR      (0x00000001U)    /*!< BERR error            */
+#define HAL_I2C_ERROR_ARLO      (0x00000002U)    /*!< ARLO error            */
+#define HAL_I2C_ERROR_AF        (0x00000004U)    /*!< ACKF error            */
+#define HAL_I2C_ERROR_OVR       (0x00000008U)    /*!< OVR error             */
+#define HAL_I2C_ERROR_DMA       (0x00000010U)    /*!< DMA transfer error    */
+#define HAL_I2C_ERROR_TIMEOUT   (0x00000020U)    /*!< Timeout error         */
+#define HAL_I2C_ERROR_SIZE      (0x00000040U)    /*!< Size Management error */
+#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U)    /*!< DMA Parameter Error   */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+#define HAL_I2C_ERROR_INVALID_CALLBACK  (0x00000100U)    /*!< Invalid Callback error */
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+#define HAL_I2C_ERROR_INVALID_PARAM     (0x00000200U)    /*!< Invalid Parameters error  */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
+  * @brief  I2C handle Structure definition
+  * @{
+  */
+typedef struct __I2C_HandleTypeDef
+{
+  I2C_TypeDef                *Instance;      /*!< I2C registers base address                */
+
+  I2C_InitTypeDef            Init;           /*!< I2C communication parameters              */
+
+  uint8_t                    *pBuffPtr;      /*!< Pointer to I2C transfer buffer            */
+
+  uint16_t                   XferSize;       /*!< I2C transfer size                         */
+
+  __IO uint16_t              XferCount;      /*!< I2C transfer counter                      */
+
+  __IO uint32_t              XferOptions;    /*!< I2C sequantial transfer options, this parameter can
+                                                  be a value of @ref I2C_XFEROPTIONS */
+
+  __IO uint32_t              PreviousState;  /*!< I2C communication Previous state          */
+
+  HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);  /*!< I2C transfer IRQ handler function pointer */
+
+  DMA_HandleTypeDef          *hdmatx;        /*!< I2C Tx DMA handle parameters              */
+
+  DMA_HandleTypeDef          *hdmarx;        /*!< I2C Rx DMA handle parameters              */
+
+  HAL_LockTypeDef            Lock;           /*!< I2C locking object                        */
+
+  __IO HAL_I2C_StateTypeDef  State;          /*!< I2C communication state                   */
+
+  __IO HAL_I2C_ModeTypeDef   Mode;           /*!< I2C communication mode                    */
+
+  __IO uint32_t              ErrorCode;      /*!< I2C Error code                            */
+
+  __IO uint32_t              AddrEventCount; /*!< I2C Address Event counter                 */
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+  void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);           /*!< I2C Master Tx Transfer completed callback */
+  void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);           /*!< I2C Master Rx Transfer completed callback */
+  void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);            /*!< I2C Slave Tx Transfer completed callback  */
+  void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);            /*!< I2C Slave Rx Transfer completed callback  */
+  void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);             /*!< I2C Listen Complete callback              */
+  void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Memory Tx Transfer completed callback */
+  void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Memory Rx Transfer completed callback */
+  void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);                  /*!< I2C Error callback                        */
+  void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Abort callback                        */
+
+  void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);  /*!< I2C Slave Address Match callback */
+
+  void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);                /*!< I2C Msp Init callback                     */
+  void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Msp DeInit callback                   */
+
+#endif  /* USE_HAL_I2C_REGISTER_CALLBACKS */
+} I2C_HandleTypeDef;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL I2C Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_I2C_MASTER_TX_COMPLETE_CB_ID      = 0x00U,    /*!< I2C Master Tx Transfer completed callback ID  */
+  HAL_I2C_MASTER_RX_COMPLETE_CB_ID      = 0x01U,    /*!< I2C Master Rx Transfer completed callback ID  */
+  HAL_I2C_SLAVE_TX_COMPLETE_CB_ID       = 0x02U,    /*!< I2C Slave Tx Transfer completed callback ID   */
+  HAL_I2C_SLAVE_RX_COMPLETE_CB_ID       = 0x03U,    /*!< I2C Slave Rx Transfer completed callback ID   */
+  HAL_I2C_LISTEN_COMPLETE_CB_ID         = 0x04U,    /*!< I2C Listen Complete callback ID               */
+  HAL_I2C_MEM_TX_COMPLETE_CB_ID         = 0x05U,    /*!< I2C Memory Tx Transfer callback ID            */
+  HAL_I2C_MEM_RX_COMPLETE_CB_ID         = 0x06U,    /*!< I2C Memory Rx Transfer completed callback ID  */
+  HAL_I2C_ERROR_CB_ID                   = 0x07U,    /*!< I2C Error callback ID                         */
+  HAL_I2C_ABORT_CB_ID                   = 0x08U,    /*!< I2C Abort callback ID                         */
+
+  HAL_I2C_MSPINIT_CB_ID                 = 0x09U,    /*!< I2C Msp Init callback ID                      */
+  HAL_I2C_MSPDEINIT_CB_ID               = 0x0AU     /*!< I2C Msp DeInit callback ID                    */
+
+} HAL_I2C_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL I2C Callback pointer definition
+  */
+typedef  void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */
+typedef  void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */
+
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Constants I2C Exported Constants
+  * @{
+  */
+
+/** @defgroup I2C_XFEROPTIONS  I2C Sequential Transfer Options
+  * @{
+  */
+#define I2C_FIRST_FRAME                 ((uint32_t)I2C_SOFTEND_MODE)
+#define I2C_FIRST_AND_NEXT_FRAME        ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
+#define I2C_NEXT_FRAME                  ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
+#define I2C_FIRST_AND_LAST_FRAME        ((uint32_t)I2C_AUTOEND_MODE)
+#define I2C_LAST_FRAME                  ((uint32_t)I2C_AUTOEND_MODE)
+#define I2C_LAST_FRAME_NO_STOP          ((uint32_t)I2C_SOFTEND_MODE)
+
+/* List of XferOptions in usage of :
+ * 1- Restart condition in all use cases (direction change or not)
+ */
+#define  I2C_OTHER_FRAME                (0x000000AAU)
+#define  I2C_OTHER_AND_LAST_FRAME       (0x0000AA00U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
+  * @{
+  */
+#define I2C_ADDRESSINGMODE_7BIT         (0x00000001U)
+#define I2C_ADDRESSINGMODE_10BIT        (0x00000002U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
+  * @{
+  */
+#define I2C_DUALADDRESS_DISABLE         (0x00000000U)
+#define I2C_DUALADDRESS_ENABLE          I2C_OAR2_OA2EN
+/**
+  * @}
+  */
+
+/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
+  * @{
+  */
+#define I2C_OA2_NOMASK                  ((uint8_t)0x00U)
+#define I2C_OA2_MASK01                  ((uint8_t)0x01U)
+#define I2C_OA2_MASK02                  ((uint8_t)0x02U)
+#define I2C_OA2_MASK03                  ((uint8_t)0x03U)
+#define I2C_OA2_MASK04                  ((uint8_t)0x04U)
+#define I2C_OA2_MASK05                  ((uint8_t)0x05U)
+#define I2C_OA2_MASK06                  ((uint8_t)0x06U)
+#define I2C_OA2_MASK07                  ((uint8_t)0x07U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
+  * @{
+  */
+#define I2C_GENERALCALL_DISABLE         (0x00000000U)
+#define I2C_GENERALCALL_ENABLE          I2C_CR1_GCEN
+/**
+  * @}
+  */
+
+/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
+  * @{
+  */
+#define I2C_NOSTRETCH_DISABLE           (0x00000000U)
+#define I2C_NOSTRETCH_ENABLE            I2C_CR1_NOSTRETCH
+/**
+  * @}
+  */
+
+/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
+  * @{
+  */
+#define I2C_MEMADD_SIZE_8BIT            (0x00000001U)
+#define I2C_MEMADD_SIZE_16BIT           (0x00000002U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
+  * @{
+  */
+#define I2C_DIRECTION_TRANSMIT          (0x00000000U)
+#define I2C_DIRECTION_RECEIVE           (0x00000001U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
+  * @{
+  */
+#define  I2C_RELOAD_MODE                I2C_CR2_RELOAD
+#define  I2C_AUTOEND_MODE               I2C_CR2_AUTOEND
+#define  I2C_SOFTEND_MODE               (0x00000000U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
+  * @{
+  */
+#define  I2C_NO_STARTSTOP               (0x00000000U)
+#define  I2C_GENERATE_STOP              (uint32_t)(0x80000000U | I2C_CR2_STOP)
+#define  I2C_GENERATE_START_READ        (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
+#define  I2C_GENERATE_START_WRITE       (uint32_t)(0x80000000U | I2C_CR2_START)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
+  * @brief I2C Interrupt definition
+  *        Elements values convention: 0xXXXXXXXX
+  *           - XXXXXXXX  : Interrupt control mask
+  * @{
+  */
+#define I2C_IT_ERRI                     I2C_CR1_ERRIE
+#define I2C_IT_TCI                      I2C_CR1_TCIE
+#define I2C_IT_STOPI                    I2C_CR1_STOPIE
+#define I2C_IT_NACKI                    I2C_CR1_NACKIE
+#define I2C_IT_ADDRI                    I2C_CR1_ADDRIE
+#define I2C_IT_RXI                      I2C_CR1_RXIE
+#define I2C_IT_TXI                      I2C_CR1_TXIE
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Flag_definition I2C Flag definition
+  * @{
+  */
+#define I2C_FLAG_TXE                    I2C_ISR_TXE
+#define I2C_FLAG_TXIS                   I2C_ISR_TXIS
+#define I2C_FLAG_RXNE                   I2C_ISR_RXNE
+#define I2C_FLAG_ADDR                   I2C_ISR_ADDR
+#define I2C_FLAG_AF                     I2C_ISR_NACKF
+#define I2C_FLAG_STOPF                  I2C_ISR_STOPF
+#define I2C_FLAG_TC                     I2C_ISR_TC
+#define I2C_FLAG_TCR                    I2C_ISR_TCR
+#define I2C_FLAG_BERR                   I2C_ISR_BERR
+#define I2C_FLAG_ARLO                   I2C_ISR_ARLO
+#define I2C_FLAG_OVR                    I2C_ISR_OVR
+#define I2C_FLAG_PECERR                 I2C_ISR_PECERR
+#define I2C_FLAG_TIMEOUT                I2C_ISR_TIMEOUT
+#define I2C_FLAG_ALERT                  I2C_ISR_ALERT
+#define I2C_FLAG_BUSY                   I2C_ISR_BUSY
+#define I2C_FLAG_DIR                    I2C_ISR_DIR
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Macros I2C Exported Macros
+  * @{
+  */
+
+/** @brief Reset I2C handle state.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                do{                                                   \
+                                                                    (__HANDLE__)->State = HAL_I2C_STATE_RESET;       \
+                                                                    (__HANDLE__)->MspInitCallback = NULL;            \
+                                                                    (__HANDLE__)->MspDeInitCallback = NULL;          \
+                                                                  } while(0)
+#else
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
+#endif
+
+/** @brief  Enable the specified I2C interrupt.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __INTERRUPT__ specifies the interrupt source to enable.
+  *        This parameter can be one of the following values:
+  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
+  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
+  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
+  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
+  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
+  *            @arg @ref I2C_IT_RXI   RX interrupt enable
+  *            @arg @ref I2C_IT_TXI   TX interrupt enable
+  *
+  * @retval None
+  */
+#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)          ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
+
+/** @brief  Disable the specified I2C interrupt.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __INTERRUPT__ specifies the interrupt source to disable.
+  *        This parameter can be one of the following values:
+  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
+  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
+  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
+  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
+  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
+  *            @arg @ref I2C_IT_RXI   RX interrupt enable
+  *            @arg @ref I2C_IT_TXI   TX interrupt enable
+  *
+  * @retval None
+  */
+#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
+
+/** @brief  Check whether the specified I2C interrupt source is enabled or not.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __INTERRUPT__ specifies the I2C interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
+  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
+  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
+  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
+  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
+  *            @arg @ref I2C_IT_RXI   RX interrupt enable
+  *            @arg @ref I2C_IT_TXI   TX interrupt enable
+  *
+  * @retval The new state of __INTERRUPT__ (SET or RESET).
+  */
+#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)      ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief  Check whether the specified I2C flag is set or not.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg @ref I2C_FLAG_TXE     Transmit data register empty
+  *            @arg @ref I2C_FLAG_TXIS    Transmit interrupt status
+  *            @arg @ref I2C_FLAG_RXNE    Receive data register not empty
+  *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)
+  *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag
+  *            @arg @ref I2C_FLAG_STOPF   STOP detection flag
+  *            @arg @ref I2C_FLAG_TC      Transfer complete (master mode)
+  *            @arg @ref I2C_FLAG_TCR     Transfer complete reload
+  *            @arg @ref I2C_FLAG_BERR    Bus error
+  *            @arg @ref I2C_FLAG_ARLO    Arbitration lost
+  *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun
+  *            @arg @ref I2C_FLAG_PECERR  PEC error in reception
+  *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
+  *            @arg @ref I2C_FLAG_ALERT   SMBus alert
+  *            @arg @ref I2C_FLAG_BUSY    Bus busy
+  *            @arg @ref I2C_FLAG_DIR     Transfer direction (slave mode)
+  *
+  * @retval The new state of __FLAG__ (SET or RESET).
+  */
+#define I2C_FLAG_MASK  (0x0001FFFFU)
+#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+
+/** @brief  Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __FLAG__ specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg @ref I2C_FLAG_TXE     Transmit data register empty
+  *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)
+  *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag
+  *            @arg @ref I2C_FLAG_STOPF   STOP detection flag
+  *            @arg @ref I2C_FLAG_BERR    Bus error
+  *            @arg @ref I2C_FLAG_ARLO    Arbitration lost
+  *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun
+  *            @arg @ref I2C_FLAG_PECERR  PEC error in reception
+  *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
+  *            @arg @ref I2C_FLAG_ALERT   SMBus alert
+  *
+  * @retval None
+  */
+#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
+                                                                                 : ((__HANDLE__)->Instance->ICR = (__FLAG__)))
+
+/** @brief  Enable the specified I2C peripheral.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#define __HAL_I2C_ENABLE(__HANDLE__)                            (SET_BIT((__HANDLE__)->Instance->CR1,  I2C_CR1_PE))
+
+/** @brief  Disable the specified I2C peripheral.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#define __HAL_I2C_DISABLE(__HANDLE__)                           (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
+
+/** @brief  Generate a Non-Acknowledge I2C peripheral in Slave mode.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#define __HAL_I2C_GENERATE_NACK(__HANDLE__)                     (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
+/**
+  * @}
+  */
+
+/* Include I2C HAL Extended module */
+#include "stm32h7xx_hal_i2c_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2C_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+/* Initialization and de-initialization functions******************************/
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
+  * @{
+  */
+/* IO operation functions  ****************************************************/
+/******* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
+
+/******* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
+
+/******* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
+void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
+  * @{
+  */
+/* Peripheral State, Mode and Error functions  *********************************/
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
+HAL_I2C_ModeTypeDef  HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
+uint32_t             HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Constants I2C Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2C_Private_Macro I2C Private Macros
+  * @{
+  */
+
+#define IS_I2C_ADDRESSING_MODE(MODE)    (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
+                                         ((MODE) == I2C_ADDRESSINGMODE_10BIT))
+
+#define IS_I2C_DUAL_ADDRESS(ADDRESS)    (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
+                                         ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
+
+#define IS_I2C_OWN_ADDRESS2_MASK(MASK)  (((MASK) == I2C_OA2_NOMASK)  || \
+                                         ((MASK) == I2C_OA2_MASK01) || \
+                                         ((MASK) == I2C_OA2_MASK02) || \
+                                         ((MASK) == I2C_OA2_MASK03) || \
+                                         ((MASK) == I2C_OA2_MASK04) || \
+                                         ((MASK) == I2C_OA2_MASK05) || \
+                                         ((MASK) == I2C_OA2_MASK06) || \
+                                         ((MASK) == I2C_OA2_MASK07))
+
+#define IS_I2C_GENERAL_CALL(CALL)       (((CALL) == I2C_GENERALCALL_DISABLE) || \
+                                         ((CALL) == I2C_GENERALCALL_ENABLE))
+
+#define IS_I2C_NO_STRETCH(STRETCH)      (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
+                                         ((STRETCH) == I2C_NOSTRETCH_ENABLE))
+
+#define IS_I2C_MEMADD_SIZE(SIZE)        (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
+                                         ((SIZE) == I2C_MEMADD_SIZE_16BIT))
+
+#define IS_TRANSFER_MODE(MODE)          (((MODE) == I2C_RELOAD_MODE)   || \
+                                         ((MODE) == I2C_AUTOEND_MODE) || \
+                                         ((MODE) == I2C_SOFTEND_MODE))
+
+#define IS_TRANSFER_REQUEST(REQUEST)    (((REQUEST) == I2C_GENERATE_STOP)        || \
+                                         ((REQUEST) == I2C_GENERATE_START_READ)  || \
+                                         ((REQUEST) == I2C_GENERATE_START_WRITE) || \
+                                         ((REQUEST) == I2C_NO_STARTSTOP))
+
+#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)  (((REQUEST) == I2C_FIRST_FRAME)          || \
+                                                   ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
+                                                   ((REQUEST) == I2C_NEXT_FRAME)           || \
+                                                   ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
+                                                   ((REQUEST) == I2C_LAST_FRAME)           || \
+                                                   ((REQUEST) == I2C_LAST_FRAME_NO_STOP)   || \
+                                                   IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
+
+#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME)     || \
+                                                        ((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
+
+#define I2C_RESET_CR2(__HANDLE__)                 ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
+
+#define I2C_GET_ADDR_MATCH(__HANDLE__)            ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U))
+#define I2C_GET_DIR(__HANDLE__)                   ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U))
+#define I2C_GET_STOP_MODE(__HANDLE__)             ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
+#define I2C_GET_OWN_ADDRESS1(__HANDLE__)          ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
+#define I2C_GET_OWN_ADDRESS2(__HANDLE__)          ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
+
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1)             ((ADDRESS1) <= 0x000003FFU)
+#define IS_I2C_OWN_ADDRESS2(ADDRESS2)             ((ADDRESS2) <= (uint16_t)0x00FFU)
+
+#define I2C_MEM_ADD_MSB(__ADDRESS__)              ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
+#define I2C_MEM_ADD_LSB(__ADDRESS__)              ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
+
+#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
+                                                          (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
+
+#define I2C_CHECK_FLAG(__ISR__, __FLAG__)         ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
+#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__)      ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
+/**
+  * @}
+  */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Functions I2C Private Functions
+  * @{
+  */
+/* Private functions are defined in stm32h7xx_hal_i2c.c file */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32H7xx_HAL_I2C_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h
new file mode 100644
index 00000000..bf89420b
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h
@@ -0,0 +1,181 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_i2c_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of I2C HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_I2C_EX_H
+#define STM32H7xx_HAL_I2C_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup I2CEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
+  * @{
+  */
+
+/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
+  * @{
+  */
+#define I2C_ANALOGFILTER_ENABLE         0x00000000U
+#define I2C_ANALOGFILTER_DISABLE        I2C_CR1_ANFOFF
+/**
+  * @}
+  */
+
+/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
+  * @{
+  */
+#define I2C_FASTMODEPLUS_PB6            SYSCFG_PMCR_I2C_PB6_FMP                        /*!< Enable Fast Mode Plus on PB6       */
+#define I2C_FASTMODEPLUS_PB7            SYSCFG_PMCR_I2C_PB7_FMP                        /*!< Enable Fast Mode Plus on PB7       */
+#define I2C_FASTMODEPLUS_PB8            SYSCFG_PMCR_I2C_PB8_FMP                        /*!< Enable Fast Mode Plus on PB8       */
+#define I2C_FASTMODEPLUS_PB9            SYSCFG_PMCR_I2C_PB9_FMP                        /*!< Enable Fast Mode Plus on PB9       */
+#define I2C_FASTMODEPLUS_I2C1           SYSCFG_PMCR_I2C1_FMP                           /*!< Enable Fast Mode Plus on I2C1 pins */
+#define I2C_FASTMODEPLUS_I2C2           SYSCFG_PMCR_I2C2_FMP                           /*!< Enable Fast Mode Plus on I2C2 pins */
+#define I2C_FASTMODEPLUS_I2C3           SYSCFG_PMCR_I2C3_FMP                           /*!< Enable Fast Mode Plus on I2C3 pins */
+#define I2C_FASTMODEPLUS_I2C4           SYSCFG_PMCR_I2C4_FMP                           /*!< Enable Fast Mode Plus on I2C4 pins */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
+  * @{
+  */
+
+/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions
+  * @brief    Extended features functions
+  * @{
+  */
+
+/* Peripheral Control functions  ************************************************/
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
+HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
+void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
+void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
+  * @{
+  */
+#define IS_I2C_ANALOG_FILTER(FILTER)    (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
+                                          ((FILTER) == I2C_ANALOGFILTER_DISABLE))
+
+#define IS_I2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000FU)
+
+#if (defined(SYSCFG_PMCR_I2C1_FMP) && defined(SYSCFG_PMCR_I2C2_FMP) && defined(SYSCFG_PMCR_I2C3_FMP) && defined(SYSCFG_PMCR_I2C4_FMP))
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3) || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C4) == I2C_FASTMODEPLUS_I2C4))
+#elif defined(SYSCFG_PMCR_I2C1_FMP) && defined(SYSCFG_PMCR_I2C2_FMP) && defined(SYSCFG_PMCR_I2C3_FMP)
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3))
+#elif defined(SYSCFG_PMCR_I2C1_FMP) && defined(SYSCFG_PMCR_I2C2_FMP)
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2))
+#elif defined(SYSCFG_PMCR_I2C1_FMP)
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \
+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1))
+#endif /* SYSCFG_PMCR_I2C1_FMP && SYSCFG_PMCR_I2C2_FMP && SYSCFG_PMCR_I2C3_FMP && SYSCFG_PMCR_I2C4_FMP */
+
+
+
+/**
+  * @}
+  */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
+  * @{
+  */
+/* Private functions are defined in stm32h7xx_hal_i2c_ex.c file */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_I2C_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h
new file mode 100644
index 00000000..6c1d9b71
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h
@@ -0,0 +1,855 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_mdma.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMA HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_MDMA_H
+#define STM32H7xx_HAL_MDMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup MDMA
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup MDMA_Exported_Types MDMA Exported Types
+  * @brief    MDMA Exported Types
+  * @{
+  */
+
+/**
+  * @brief  MDMA Configuration Structure definition
+  */
+typedef struct
+{
+
+  uint32_t Request;                 /*!< Specifies the MDMA request.
+                                        This parameter can be a value of @ref MDMA_Request_selection*/
+
+  uint32_t TransferTriggerMode;     /*!< Specifies the Trigger Transfer mode : each request triggers a :
+                                         a buffer transfer, a block transfer, a repeated block transfer or a linked list transfer
+                                         This parameter can be a value of @ref MDMA_Transfer_TriggerMode  */
+
+  uint32_t Priority;                 /*!< Specifies the software priority for the MDMAy channelx.
+                                         This parameter can be a value of @ref MDMA_Priority_level */
+
+  uint32_t Endianness;                /*!< Specifies if the MDMA transactions preserve the Little endianness.
+                                         This parameter can be a value of @ref MDMA_Endianness */
+
+  uint32_t SourceInc;                /*!< Specifies if the Source increment mode .
+                                         This parameter can be a value of @ref MDMA_Source_increment_mode */
+
+  uint32_t DestinationInc;           /*!< Specifies if the Destination increment mode .
+                                         This parameter can be a value of @ref MDMA_Destination_increment_mode */
+
+  uint32_t SourceDataSize;           /*!< Specifies the source data size.
+                                         This parameter can be a value of @ref MDMA_Source_data_size */
+
+  uint32_t DestDataSize;             /*!< Specifies the destination data size.
+                                          This parameter can be a value of @ref MDMA_Destination_data_size */
+
+
+  uint32_t DataAlignment;            /*!< Specifies the source to destination Memory data packing/padding mode.
+                                            This parameter can be a value of @ref MDMA_data_Alignment */
+
+  uint32_t BufferTransferLength;      /*!< Specifies the buffer Transfer Length (number of bytes),
+                                          this is the number of bytes to be transferred in a single transfer (1 byte to 128 bytes)*/
+
+  uint32_t SourceBurst;              /*!< Specifies the Burst transfer configuration for the source memory transfers.
+                                         It specifies the amount of data to be transferred in a single non interruptable
+                                         transaction.
+                                         This parameter can be a value of @ref MDMA_Source_burst
+                                         @note : the burst may be FIXED/INCR based on SourceInc value ,
+                                         the BURST must be programmed as to ensure that the burst size will be lower than than
+                                         BufferTransferLength */
+
+  uint32_t DestBurst;                 /*!< Specifies the Burst transfer configuration for the destination memory transfers.
+                                           It specifies the amount of data to be transferred in a single non interruptable
+                                           transaction.
+                                           This parameter can be a value of @ref MDMA_Destination_burst
+                                           @note : the burst may be FIXED/INCR based on DestinationInc value ,
+                                           the BURST must be programmed as to ensure that the burst size will be lower than than
+                                           BufferTransferLength */
+
+  int32_t SourceBlockAddressOffset;   /*!< this field specifies the Next block source address offset
+                                           signed value : if > 0 then  increment the next block source Address by offset from where the last block ends
+                                                          if < 0 then  decrement the next block source Address by offset from where the last block ends
+                                                          if == 0, the next block source address starts from where the last block ends
+                                       */
+
+
+  int32_t DestBlockAddressOffset;      /*!< this field specifies the Next block destination address offset
+                                           signed value : if > 0 then  increment the next block destination Address by offset from where the last block ends
+                                                          if < 0 then  decrement the next block destination Address by offset from where the last block ends
+                                                          if == 0, the next block destination address starts from where the last block ends
+                                       */
+
+}MDMA_InitTypeDef;
+
+/**
+  * @brief  HAL MDMA linked list node structure definition
+  * @note   The Linked list node allows to define a new MDMA configuration
+  *         (CTCR ,CBNDTR ,CSAR ,CDAR ,CBRUR, CLAR, CTBR, CMAR and CMDR registers).
+  *         When CLAR register is configured to a non NULL value , each time a transfer ends,
+  *         a new configuration (linked list node) is automatically loaded from the address given in CLAR register.
+  */
+typedef struct
+{
+  __IO uint32_t CTCR;     /*!< New CTCR register configuration for the given MDMA linked list node   */
+  __IO uint32_t CBNDTR;   /*!< New CBNDTR register configuration for the given MDMA linked list node */
+  __IO uint32_t CSAR;     /*!< New CSAR register configuration for the given MDMA linked list node   */
+  __IO uint32_t CDAR;     /*!< New CDAR register configuration for the given MDMA linked list node   */
+  __IO uint32_t CBRUR;    /*!< New CBRUR register configuration for the given MDMA linked list node  */
+  __IO uint32_t CLAR;     /*!< New CLAR register configuration for the given MDMA linked list node   */
+  __IO uint32_t CTBR;     /*!< New CTBR register configuration for the given MDMA linked list node   */
+  __IO uint32_t Reserved; /*!< Reserved register                                                     */
+  __IO uint32_t CMAR;     /*!< New CMAR register configuration for the given MDMA linked list node   */
+  __IO uint32_t CMDR;     /*!< New CMDR register configuration for the given MDMA linked list node   */
+
+}MDMA_LinkNodeTypeDef;
+
+/**
+  * @brief  HAL MDMA linked list node configuration structure definition
+  * @note   used with HAL_MDMA_LinkedList_CreateNode function
+  */
+typedef struct
+{
+  MDMA_InitTypeDef Init;            /*!< configuration of the specified MDMA Linked List Node    */
+  uint32_t         SrcAddress;      /*!< The source memory address for the Linked list Node      */
+  uint32_t         DstAddress;      /*!< The destination memory address for the Linked list Node */
+  uint32_t         BlockDataLength; /*!< The data length of a block in bytes                     */
+  uint32_t         BlockCount;      /*!< The number of blocks to be transferred                  */
+
+  uint32_t PostRequestMaskAddress;  /*!< specifies the address to be updated (written) with PostRequestMaskData after a request is served.
+                                         PostRequestMaskAddress and PostRequestMaskData could be used to automatically clear a peripheral flag when the request is served  */
+
+  uint32_t PostRequestMaskData;     /*!< specifies the value to be written to PostRequestMaskAddress after a request is served.
+                                         PostRequestMaskAddress and PostRequestMaskData could be used to automatically clear a peripheral flag when the request is served  */
+
+
+}MDMA_LinkNodeConfTypeDef;
+
+
+/**
+  * @brief  HAL MDMA State structure definition
+  */
+typedef enum
+{
+  HAL_MDMA_STATE_RESET               = 0x00U,  /*!< MDMA not yet initialized or disabled */
+  HAL_MDMA_STATE_READY               = 0x01U,  /*!< MDMA initialized and ready for use   */
+  HAL_MDMA_STATE_BUSY                = 0x02U,  /*!< MDMA process is ongoing              */
+  HAL_MDMA_STATE_ERROR               = 0x03U,  /*!< MDMA error state                     */
+  HAL_MDMA_STATE_ABORT               = 0x04U,  /*!< MDMA Abort state                     */
+
+}HAL_MDMA_StateTypeDef;
+
+/**
+  * @brief  HAL MDMA Level Complete structure definition
+  */
+typedef enum
+{
+  HAL_MDMA_FULL_TRANSFER         = 0x00U,   /*!< Full transfer         */
+  HAL_MDMA_BUFFER_TRANSFER       = 0x01U,   /*!< Buffer Transfer       */
+  HAL_MDMA_BLOCK_TRANSFER        = 0x02U,   /*!< Block Transfer        */
+  HAL_MDMA_REPEAT_BLOCK_TRANSFER = 0x03U    /*!< repeat block Transfer */
+
+}HAL_MDMA_LevelCompleteTypeDef;
+
+/**
+  * @brief  HAL MDMA Callbacks IDs structure definition
+  */
+typedef enum
+{
+  HAL_MDMA_XFER_CPLT_CB_ID          = 0x00U,    /*!< Full transfer           */
+  HAL_MDMA_XFER_BUFFERCPLT_CB_ID    = 0x01U,    /*!< Buffer Transfer         */
+  HAL_MDMA_XFER_BLOCKCPLT_CB_ID     = 0x02U,    /*!< Block Transfer          */
+  HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID  = 0x03U,    /*!< Repeated Block Transfer */
+  HAL_MDMA_XFER_ERROR_CB_ID         = 0x04U,    /*!< Error                   */
+  HAL_MDMA_XFER_ABORT_CB_ID         = 0x05U,    /*!< Abort                   */
+  HAL_MDMA_XFER_ALL_CB_ID           = 0x06U     /*!< All                     */
+
+}HAL_MDMA_CallbackIDTypeDef;
+
+
+/**
+  * @brief  MDMA handle Structure definition
+  */
+typedef struct __MDMA_HandleTypeDef
+{
+  MDMA_Channel_TypeDef *Instance;                                                              /*!< Register base address                  */
+
+  MDMA_InitTypeDef      Init;                                                                  /*!< MDMA communication parameters          */
+
+  HAL_LockTypeDef       Lock;                                                                  /*!< MDMA locking object                    */
+
+  __IO HAL_MDMA_StateTypeDef  State;                                                           /*!< MDMA transfer state                    */
+
+  void                  *Parent;                                                               /*!< Parent object state                    */
+
+  void                  (* XferCpltCallback)( struct __MDMA_HandleTypeDef * hmdma);            /*!< MDMA transfer complete callback        */
+
+  void                  (* XferBufferCpltCallback)( struct __MDMA_HandleTypeDef * hmdma);      /*!< MDMA buffer transfer complete callback */
+
+  void                  (* XferBlockCpltCallback)( struct __MDMA_HandleTypeDef * hmdma);       /*!< MDMA block transfer complete callback  */
+
+  void                  (* XferRepeatBlockCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA block transfer repeat callback    */
+
+  void                  (* XferErrorCallback)( struct __MDMA_HandleTypeDef * hmdma);           /*!< MDMA transfer error callback           */
+
+  void                  (* XferAbortCallback)( struct __MDMA_HandleTypeDef * hmdma);           /*!< MDMA transfer Abort callback           */
+
+
+  MDMA_LinkNodeTypeDef *FirstLinkedListNodeAddress;                                             /*!< specifies the first node address of the transfer list
+                                                                                                     (after the initial node defined by the Init struct)
+                                                                                                     this parameter is used internally by the MDMA driver
+                                                                                                     to construct the linked list node
+                                                                                                */
+
+  MDMA_LinkNodeTypeDef *LastLinkedListNodeAddress;                                             /*!< specifies the last node address of the transfer list
+                                                                                                    this parameter is used internally by the MDMA driver
+                                                                                                    to construct the linked list node
+                                                                                                */
+  uint32_t LinkedListNodeCounter;                                                               /*!< Number of nodes in the MDMA linked list */
+
+  __IO uint32_t          ErrorCode;                                                            /*!< MDMA Error code                        */
+
+} MDMA_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup MDMA_Exported_Constants MDMA Exported Constants
+  * @brief    MDMA Exported constants
+  * @{
+  */
+
+/** @defgroup MDMA_Error_Codes MDMA Error Codes
+  * @brief    MDMA Error Codes
+  * @{
+  */
+#define HAL_MDMA_ERROR_NONE        ((uint32_t)0x00000000U)   /*!< No error                               */
+#define HAL_MDMA_ERROR_READ_XFER   ((uint32_t)0x00000001U)   /*!< Read Transfer error                    */
+#define HAL_MDMA_ERROR_WRITE_XFER  ((uint32_t)0x00000002U)   /*!< Write Transfer error                   */
+#define HAL_MDMA_ERROR_MASK_DATA   ((uint32_t)0x00000004U)   /*!< Error Mask Data error                  */
+#define HAL_MDMA_ERROR_LINKED_LIST ((uint32_t)0x00000008U)   /*!< Linked list Data error                 */
+#define HAL_MDMA_ERROR_ALIGNMENT   ((uint32_t)0x00000010U)   /*!< Address/Size alignment  error          */
+#define HAL_MDMA_ERROR_BLOCK_SIZE  ((uint32_t)0x00000020U)   /*!< Block Size error                       */
+#define HAL_MDMA_ERROR_TIMEOUT     ((uint32_t)0x00000040U)   /*!< Timeout error                          */
+#define HAL_MDMA_ERROR_NO_XFER     ((uint32_t)0x00000080U)   /*!< Abort or SW trigger requested with no Xfer ongoing   */
+#define HAL_MDMA_ERROR_BUSY        ((uint32_t)0x00000100U)   /*!< DeInit or SW trigger requested with Xfer ongoing   */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_Request_selection MDMA Request selection
+  * @brief    MDMA_Request_selection
+  * @{
+  */
+
+#define MDMA_REQUEST_DMA1_Stream0_TC      ((uint32_t)0x00000000U)  /*!< MDMA HW request is DMA1 Stream 0 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA1_Stream1_TC      ((uint32_t)0x00000001U)  /*!< MDMA HW request is DMA1 Stream 1 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA1_Stream2_TC      ((uint32_t)0x00000002U)  /*!< MDMA HW request is DMA1 Stream 2 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA1_Stream3_TC      ((uint32_t)0x00000003U)  /*!< MDMA HW request is DMA1 Stream 3 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA1_Stream4_TC      ((uint32_t)0x00000004U)  /*!< MDMA HW request is DMA1 Stream 4 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA1_Stream5_TC      ((uint32_t)0x00000005U)  /*!< MDMA HW request is DMA1 Stream 5 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA1_Stream6_TC      ((uint32_t)0x00000006U)  /*!< MDMA HW request is DMA1 Stream 6 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA1_Stream7_TC      ((uint32_t)0x00000007U)  /*!< MDMA HW request is DMA1 Stream 7 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA2_Stream0_TC      ((uint32_t)0x00000008U)  /*!< MDMA HW request is DMA2 Stream 0 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA2_Stream1_TC      ((uint32_t)0x00000009U)  /*!< MDMA HW request is DMA2 Stream 1 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA2_Stream2_TC      ((uint32_t)0x0000000AU)  /*!< MDMA HW request is DMA2 Stream 2 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA2_Stream3_TC      ((uint32_t)0x0000000BU)  /*!< MDMA HW request is DMA2 Stream 3 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA2_Stream4_TC      ((uint32_t)0x0000000CU)  /*!< MDMA HW request is DMA2 Stream 4 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA2_Stream5_TC      ((uint32_t)0x0000000DU)  /*!< MDMA HW request is DMA2 Stream 5 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA2_Stream6_TC      ((uint32_t)0x0000000EU)  /*!< MDMA HW request is DMA2 Stream 6 Transfer Complete Flag   */
+#define MDMA_REQUEST_DMA2_Stream7_TC      ((uint32_t)0x0000000FU)  /*!< MDMA HW request is DMA2 Stream 7 Transfer Complete Flag   */
+#if defined (LTDC)
+#define MDMA_REQUEST_LTDC_LINE_IT         ((uint32_t)0x00000010U)  /*!< MDMA HW request is LTDC Line interrupt Flag               */
+#endif /* LTDC */
+#if defined (JPEG)
+#define MDMA_REQUEST_JPEG_INFIFO_TH       ((uint32_t)0x00000011U)  /*!< MDMA HW request is JPEG Input FIFO threshold Flag         */
+#define MDMA_REQUEST_JPEG_INFIFO_NF       ((uint32_t)0x00000012U)  /*!< MDMA HW request is JPEG Input FIFO not full Flag          */
+#define MDMA_REQUEST_JPEG_OUTFIFO_TH      ((uint32_t)0x00000013U)  /*!< MDMA HW request is JPEG Output FIFO threshold Flag        */
+#define MDMA_REQUEST_JPEG_OUTFIFO_NE      ((uint32_t)0x00000014U)  /*!< MDMA HW request is JPEG Output FIFO not empty Flag        */
+#define MDMA_REQUEST_JPEG_END_CONVERSION  ((uint32_t)0x00000015U)  /*!< MDMA HW request is JPEG End of conversion Flag            */
+#endif /* JPEG */
+#if defined (OCTOSPI1)
+#define MDMA_REQUEST_OCTOSPI1_FIFO_TH     ((uint32_t)0x00000016U)  /*!< MDMA HW request is OCTOSPI1 FIFO threshold Flag           */
+#define MDMA_REQUEST_OCTOSPI1_TC          ((uint32_t)0x00000017U)  /*!< MDMA HW request is OCTOSPI1 Transfer complete Flag        */
+#endif /* OCTOSPI1 */
+#if defined (QUADSPI)
+#define MDMA_REQUEST_QUADSPI_FIFO_TH      ((uint32_t)0x00000016U)  /*!< MDMA HW request is QSPI FIFO threshold Flag               */
+#define MDMA_REQUEST_QUADSPI_TC           ((uint32_t)0x00000017U)  /*!< MDMA HW request is QSPI Transfer complete Flag            */
+#endif /* QUADSPI */
+#define MDMA_REQUEST_DMA2D_CLUT_TC        ((uint32_t)0x00000018U)  /*!< MDMA HW request is DMA2D CLUT Transfer Complete Flag      */
+#define MDMA_REQUEST_DMA2D_TC             ((uint32_t)0x00000019U)  /*!< MDMA HW request is DMA2D Transfer Complete Flag           */
+#define MDMA_REQUEST_DMA2D_TW             ((uint32_t)0x0000001AU)  /*!< MDMA HW request is DMA2D Transfer Watermark Flag          */
+
+#if defined (DSI)
+#define MDMA_REQUEST_DSI_TEARING_EFFECT   ((uint32_t)0x0000001BU)  /*!< MDMA HW request is DSI Tearing Effect Flag                */
+#define MDMA_REQUEST_DSI_END_REFRESH      ((uint32_t)0x0000001CU)  /*!< MDMA HW request is DSI End of refresh  Flag               */
+#endif /* DSI */
+
+#define MDMA_REQUEST_SDMMC1_END_DATA      ((uint32_t)0x0000001DU)  /*!< MDMA HW request is SDMMC1 End of Data Flag                */
+
+#define MDMA_REQUEST_SDMMC1_DMA_ENDBUFFER ((uint32_t)0x0000001EU)  /*!< MDMA HW request is SDMMC1 Internal DMA buffer End Flag    */
+#define MDMA_REQUEST_SDMMC1_COMMAND_END   ((uint32_t)0x0000001FU)  /*!< MDMA HW request is SDMMC1 Command End Flag                */
+
+#if defined (OCTOSPI2)
+#define MDMA_REQUEST_OCTOSPI2_FIFO_TH     ((uint32_t)0x00000020U)  /*!< MDMA HW request is OCTOSPI2 FIFO threshold Flag           */
+#define MDMA_REQUEST_OCTOSPI2_TC          ((uint32_t)0x00000021U)  /*!< MDMA HW request is OCTOSPI2 Transfer complete Flag        */
+#endif /* OCTOSPI2 */
+
+#define MDMA_REQUEST_SW                   ((uint32_t)0x40000000U) /*!< MDMA SW request                                            */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_Transfer_TriggerMode MDMA Transfer Trigger  Mode
+  * @brief    MDMA Transfer Trigger Mode
+  * @{
+  */
+#define MDMA_BUFFER_TRANSFER          ((uint32_t)0x00000000U)        /*!< Each MDMA request (SW or HW) triggers a buffer transfer                                */
+#define MDMA_BLOCK_TRANSFER           ((uint32_t)MDMA_CTCR_TRGM_0)   /*!< Each MDMA request (SW or HW) triggers a block transfer                                 */
+#define MDMA_REPEAT_BLOCK_TRANSFER    ((uint32_t)MDMA_CTCR_TRGM_1)   /*!< Each MDMA request (SW or HW) triggers a repeated block transfer                        */
+#define MDMA_FULL_TRANSFER            ((uint32_t)MDMA_CTCR_TRGM)     /*!< Each MDMA request (SW or HW) triggers a Full transfer or a linked list transfer if any */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_Priority_level MDMA Priority level
+  * @brief    MDMA Priority level
+  * @{
+  */
+#define MDMA_PRIORITY_LOW             ((uint32_t)0x00000000U)     /*!< Priority level: Low      */
+#define MDMA_PRIORITY_MEDIUM          ((uint32_t)MDMA_CCR_PL_0)  /*!< Priority level: Medium    */
+#define MDMA_PRIORITY_HIGH            ((uint32_t)MDMA_CCR_PL_1)  /*!< Priority level: High      */
+#define MDMA_PRIORITY_VERY_HIGH       ((uint32_t)MDMA_CCR_PL)    /*!< Priority level: Very High */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup MDMA_Endianness MDMA Endianness
+  * @brief    MDMA Endianness
+  * @{
+  */
+#define MDMA_LITTLE_ENDIANNESS_PRESERVE          ((uint32_t)0x00000000U)   /*!< little endianness preserve                                               */
+#define MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE     ((uint32_t)MDMA_CCR_BEX)  /*!< BYTEs endianness exchange when destination data size is > Byte           */
+#define MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_HEX)  /*!< HALF WORDs endianness exchange when destination data size is > HALF WORD */
+#define MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE     ((uint32_t)MDMA_CCR_WEX)  /*!< WORDs endianness exchange  when destination data size is > DOUBLE WORD   */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_Source_increment_mode MDMA Source increment mode
+  * @brief    MDMA Source increment mode
+  * @{
+  */
+#define MDMA_SRC_INC_DISABLE      ((uint32_t)0x00000000U)                                     /*!< Source address pointer is fixed                                   */
+#define MDMA_SRC_INC_BYTE         ((uint32_t)MDMA_CTCR_SINC_1)                                /*!< Source address pointer is incremented by a BYTE (8 bits)          */
+#define MDMA_SRC_INC_HALFWORD     ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits)    */
+#define MDMA_SRC_INC_WORD         ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits)         */
+#define MDMA_SRC_INC_DOUBLEWORD   ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS)   /*!< Source address pointer is incremented by a double Word (64 bits)) */
+#define MDMA_SRC_DEC_BYTE         ((uint32_t)MDMA_CTCR_SINC)                                  /*!< Source address pointer is decremented by a BYTE (8 bits)          */
+#define MDMA_SRC_DEC_HALFWORD     ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_0)   /*!< Source address pointer is decremented by a half Word (16 bits)    */
+#define MDMA_SRC_DEC_WORD         ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_1)   /*!< Source address pointer is decremented by a Word (32 bits)         */
+#define MDMA_SRC_DEC_DOUBLEWORD   ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS)     /*!< Source address pointer is decremented by a double Word (64 bits)) */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_Destination_increment_mode MDMA Destination increment mode
+  * @brief    MDMA Destination increment mode
+  * @{
+  */
+#define MDMA_DEST_INC_DISABLE      ((uint32_t)0x00000000U)                                     /*!< Source address pointer is fixed                                   */
+#define MDMA_DEST_INC_BYTE         ((uint32_t)MDMA_CTCR_DINC_1)                                /*!< Source address pointer is incremented by a BYTE (8 bits)          */
+#define MDMA_DEST_INC_HALFWORD     ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits)    */
+#define MDMA_DEST_INC_WORD         ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits)         */
+#define MDMA_DEST_INC_DOUBLEWORD   ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS)   /*!< Source address pointer is incremented by a double Word (64 bits)) */
+#define MDMA_DEST_DEC_BYTE         ((uint32_t)MDMA_CTCR_DINC)                                  /*!< Source address pointer is decremented by a BYTE (8 bits)          */
+#define MDMA_DEST_DEC_HALFWORD     ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_0)   /*!< Source address pointer is decremented by a half Word (16 bits)    */
+#define MDMA_DEST_DEC_WORD         ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_1)   /*!< Source address pointer is decremented by a Word (32 bits)         */
+#define MDMA_DEST_DEC_DOUBLEWORD   ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS)     /*!< Source address pointer is decremented by a double Word (64 bits)) */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_Source_data_size MDMA Source data size
+  * @brief    MDMA Source data size
+  * @{
+  */
+#define MDMA_SRC_DATASIZE_BYTE        ((uint32_t)0x00000000U)         /*!< Source data size is Byte        */
+#define MDMA_SRC_DATASIZE_HALFWORD    ((uint32_t)MDMA_CTCR_SSIZE_0)   /*!< Source data size is half word   */
+#define MDMA_SRC_DATASIZE_WORD        ((uint32_t)MDMA_CTCR_SSIZE_1)   /*!< Source data size is word        */
+#define MDMA_SRC_DATASIZE_DOUBLEWORD  ((uint32_t)MDMA_CTCR_SSIZE)     /*!< Source data size is double word */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_Destination_data_size MDMA Destination data size
+  * @brief    MDMA Destination data size
+  * @{
+  */
+#define MDMA_DEST_DATASIZE_BYTE        ((uint32_t)0x00000000U)         /*!< Destination data size is Byte        */
+#define MDMA_DEST_DATASIZE_HALFWORD    ((uint32_t)MDMA_CTCR_DSIZE_0)   /*!< Destination data size is half word   */
+#define MDMA_DEST_DATASIZE_WORD        ((uint32_t)MDMA_CTCR_DSIZE_1)   /*!< Destination data size is word        */
+#define MDMA_DEST_DATASIZE_DOUBLEWORD  ((uint32_t)MDMA_CTCR_DSIZE)     /*!< Destination data size is double word */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_data_Alignment MDMA data alignment
+  * @brief    MDMA data alignment
+  * @{
+  */
+#define MDMA_DATAALIGN_PACKENABLE        ((uint32_t)MDMA_CTCR_PKE)     /*!< The source data is packed/un-packed into the destination data size
+                                                                            All data are right aligned, in Little Endien mode.                                              */
+#define MDMA_DATAALIGN_RIGHT            ((uint32_t)0x00000000U)        /*!< Right Aligned, padded w/ 0s (default)                                                           */
+#define MDMA_DATAALIGN_RIGHT_SIGNED     ((uint32_t)MDMA_CTCR_PAM_0)    /*!< Right Aligned, Sign extended ,
+                                                                            Note : this mode is allowed only if the Source data size is smaller than Destination data size  */
+#define MDMA_DATAALIGN_LEFT             ((uint32_t)MDMA_CTCR_PAM_1)    /*!< Left Aligned (padded with 0s)                                                                   */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_Source_burst MDMA Source burst
+  * @brief    MDMA Source burst
+  * @{
+  */
+#define MDMA_SOURCE_BURST_SINGLE        ((uint32_t)0x00000000U)                                       /*!< single transfer */
+#define MDMA_SOURCE_BURST_2BEATS        ((uint32_t)MDMA_CTCR_SBURST_0)                                /*!< Burst 2 beats   */
+#define MDMA_SOURCE_BURST_4BEATS        ((uint32_t)MDMA_CTCR_SBURST_1)                                /*!< Burst 4 beats   */
+#define MDMA_SOURCE_BURST_8BEATS        ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_1) /*!< Burst 8 beats   */
+#define MDMA_SOURCE_BURST_16BEATS       ((uint32_t)MDMA_CTCR_SBURST_2)                                /*!< Burst 16 beats  */
+#define MDMA_SOURCE_BURST_32BEATS       ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 32 beats  */
+#define MDMA_SOURCE_BURST_64BEATS       ((uint32_t)MDMA_CTCR_SBURST_1 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 64 beats  */
+#define MDMA_SOURCE_BURST_128BEATS      ((uint32_t)MDMA_CTCR_SBURST)                                  /*!< Burst 128 beats */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_Destination_burst MDMA Destination burst
+  * @brief    MDMA Destination burst
+  * @{
+  */
+#define MDMA_DEST_BURST_SINGLE        ((uint32_t)0x00000000U)                                        /*!< single transfer */
+#define MDMA_DEST_BURST_2BEATS        ((uint32_t)MDMA_CTCR_DBURST_0)                                 /*!< Burst 2 beats   */
+#define MDMA_DEST_BURST_4BEATS        ((uint32_t)MDMA_CTCR_DBURST_1)                                 /*!< Burst 4 beats   */
+#define MDMA_DEST_BURST_8BEATS        ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_1)  /*!< Burst 8 beats   */
+#define MDMA_DEST_BURST_16BEATS       ((uint32_t)MDMA_CTCR_DBURST_2)                                 /*!< Burst 16 beats  */
+#define MDMA_DEST_BURST_32BEATS       ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_2)  /*!< Burst 32 beats  */
+#define MDMA_DEST_BURST_64BEATS       ((uint32_t)MDMA_CTCR_DBURST_1 | (uint32_t)MDMA_CTCR_DBURST_2)  /*!< Burst 64 beats  */
+#define MDMA_DEST_BURST_128BEATS      ((uint32_t)MDMA_CTCR_DBURST)                                   /*!< Burst 128 beats */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_interrupt_enable_definitions MDMA interrupt enable definitions
+  * @brief    MDMA interrupt enable definitions
+  * @{
+  */
+#define MDMA_IT_TE   ((uint32_t)MDMA_CCR_TEIE)   /*!< Transfer Error interrupt            */
+#define MDMA_IT_CTC  ((uint32_t)MDMA_CCR_CTCIE)  /*!< Channel Transfer Complete interrupt */
+#define MDMA_IT_BRT  ((uint32_t)MDMA_CCR_BRTIE)  /*!< Block Repeat Transfer interrupt     */
+#define MDMA_IT_BT   ((uint32_t)MDMA_CCR_BTIE)   /*!< Block Transfer interrupt            */
+#define MDMA_IT_BFTC ((uint32_t)MDMA_CCR_TCIE)   /*!< Buffer Transfer Complete interrupt  */
+
+/**
+  * @}
+  */
+
+/** @defgroup MDMA_flag_definitions MDMA flag definitions
+  * @brief    MDMA flag definitions
+  * @{
+  */
+#define MDMA_FLAG_TE    ((uint32_t)MDMA_CISR_TEIF)  /*!< Transfer Error flag                 */
+#define MDMA_FLAG_CTC   ((uint32_t)MDMA_CISR_CTCIF) /*!< Channel Transfer Complete flag      */
+#define MDMA_FLAG_BRT   ((uint32_t)MDMA_CISR_BRTIF) /*!< Block Repeat Transfer complete flag */
+#define MDMA_FLAG_BT    ((uint32_t)MDMA_CISR_BTIF)  /*!< Block Transfer complete flag        */
+#define MDMA_FLAG_BFTC  ((uint32_t)MDMA_CISR_TCIF)  /*!< BuFfer Transfer complete flag       */
+#define MDMA_FLAG_CRQA  ((uint32_t)MDMA_CISR_CRQA)  /*!< Channel ReQest Active flag          */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup MDMA_Exported_Macros MDMA Exported Macros
+  * @{
+  */
+
+/**
+  * @brief  Enable the specified MDMA Channel.
+  * @param  __HANDLE__: MDMA handle
+  * @retval None
+  */
+#define __HAL_MDMA_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CCR |=  MDMA_CCR_EN)
+
+/**
+  * @brief  Disable the specified MDMA Channel.
+  * @param  __HANDLE__: MDMA handle
+  * @retval None
+  */
+#define __HAL_MDMA_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CCR &=  ~MDMA_CCR_EN)
+
+/**
+  * @brief  Get the MDMA Channel pending flags.
+  * @param  __HANDLE__: MDMA handle
+  * @param  __FLAG__: Get the specified flag.
+  *          This parameter can be any combination of the following values:
+  *            @arg MDMA_FLAG_TE   : Transfer Error flag.
+  *            @arg MDMA_FLAG_CTC  : Channel Transfer Complete flag.
+  *            @arg MDMA_FLAG_BRT  : Block Repeat Transfer flag.
+  *            @arg MDMA_FLAG_BT   : Block Transfer complete flag.
+  *            @arg MDMA_FLAG_BFTC : BuFfer Transfer Complete flag.
+  *            @arg MDMA_FLAG_CRQA : Channel ReQest Active flag.
+  * @retval The state of FLAG (SET or RESET).
+  */
+#define __HAL_MDMA_GET_FLAG(__HANDLE__, __FLAG__)  ((__HANDLE__)->Instance->CISR & (__FLAG__))
+
+/**
+  * @brief  Clear the MDMA Stream pending flags.
+  * @param  __HANDLE__: MDMA handle
+  * @param  __FLAG__: specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg MDMA_FLAG_TE   : Transfer Error flag.
+  *            @arg MDMA_FLAG_CTC  : Channel Transfer Complete flag.
+  *            @arg MDMA_FLAG_BRT  : Block Repeat Transfer flag.
+  *            @arg MDMA_FLAG_BT   : Block Transfer complete flag.
+  *            @arg MDMA_FLAG_BFTC : BuFfer Transfer Complete flag.
+  * @retval None
+  */
+#define __HAL_MDMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CIFCR = (__FLAG__))
+
+/**
+  * @brief  Enables the specified MDMA Channel interrupts.
+  * @param  __HANDLE__: MDMA handle
+  * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg MDMA_IT_TE   :  Transfer Error interrupt mask
+  *            @arg MDMA_IT_CTC  :  Channel Transfer Complete interrupt mask
+  *            @arg MDMA_IT_BRT  :  Block Repeat Transfer interrupt mask
+  *            @arg MDMA_IT_BT   :  Block Transfer interrupt mask
+  *            @arg MDMA_IT_BFTC :  BuFfer Transfer Complete interrupt mask
+  * @retval None
+  */
+#define __HAL_MDMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
+
+/**
+  * @brief  Disables the specified MDMA Channel interrupts.
+  * @param  __HANDLE__: MDMA handle
+  * @param __INTERRUPT__: specifies the MDMA interrupt sources to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg MDMA_IT_TE   :  Transfer Error interrupt mask
+  *            @arg MDMA_IT_CTC  :  Channel Transfer Complete interrupt mask
+  *            @arg MDMA_IT_BRT  :  Block Repeat Transfer interrupt mask
+  *            @arg MDMA_IT_BT   :  Block Transfer interrupt mask
+  *            @arg MDMA_IT_BFTC :  BuFfer Transfer Complete interrupt mask
+  * @retval None
+  */
+#define __HAL_MDMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Checks whether the specified MDMA Channel interrupt is enabled or not.
+  * @param  __HANDLE__: DMA handle
+  * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
+  *            @arg MDMA_IT_TE   :  Transfer Error interrupt mask
+  *            @arg MDMA_IT_CTC  :  Channel Transfer Complete interrupt mask
+  *            @arg MDMA_IT_BRT  :  Block Repeat Transfer interrupt mask
+  *            @arg MDMA_IT_BT   :  Block Transfer interrupt mask
+  *            @arg MDMA_IT_BFTC :  BuFfer Transfer Complete interrupt mask
+  * @retval The state of MDMA_IT (SET or RESET).
+  */
+#define __HAL_MDMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup MDMA_Exported_Functions  MDMA Exported Functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions *****************************/
+/** @defgroup MDMA_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief   Initialization and de-initialization functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_MDMA_Init(MDMA_HandleTypeDef *hmdma);
+HAL_StatusTypeDef HAL_MDMA_DeInit (MDMA_HandleTypeDef *hmdma);
+HAL_StatusTypeDef HAL_MDMA_ConfigPostRequestMask(MDMA_HandleTypeDef *hmdma, uint32_t MaskAddress, uint32_t MaskData);
+
+HAL_StatusTypeDef HAL_MDMA_RegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID, void (* pCallback)(MDMA_HandleTypeDef *_hmdma));
+HAL_StatusTypeDef HAL_MDMA_UnRegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID);
+
+/**
+  * @}
+  */
+
+/* Linked list operation functions ********************************************/
+/** @defgroup MDMA_Exported_Functions_Group2 Linked List operation functions
+  * @brief   Linked list operation functions
+  * @{
+  */
+
+HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig);
+HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, MDMA_LinkNodeTypeDef *pPrevNode);
+HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNode);
+HAL_StatusTypeDef HAL_MDMA_LinkedList_EnableCircularMode(MDMA_HandleTypeDef *hmdma);
+HAL_StatusTypeDef HAL_MDMA_LinkedList_DisableCircularMode(MDMA_HandleTypeDef *hmdma);
+
+
+/**
+  * @}
+  */
+
+/* IO operation functions *****************************************************/
+/** @defgroup MDMA_Exported_Functions_Group3 I/O operation functions
+  * @brief   I/O operation functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_MDMA_Start (MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount);
+HAL_StatusTypeDef HAL_MDMA_Start_IT(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount);
+HAL_StatusTypeDef HAL_MDMA_Abort(MDMA_HandleTypeDef *hmdma);
+HAL_StatusTypeDef HAL_MDMA_Abort_IT(MDMA_HandleTypeDef *hmdma);
+HAL_StatusTypeDef HAL_MDMA_PollForTransfer(MDMA_HandleTypeDef *hmdma, HAL_MDMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
+HAL_StatusTypeDef HAL_MDMA_GenerateSWRequest(MDMA_HandleTypeDef *hmdma);
+void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma);
+
+/**
+  * @}
+  */
+
+/* Peripheral State and Error functions ***************************************/
+/** @defgroup MDMA_Exported_Functions_Group4 Peripheral State functions
+  * @brief    Peripheral State functions
+  * @{
+  */
+HAL_MDMA_StateTypeDef HAL_MDMA_GetState(MDMA_HandleTypeDef *hmdma);
+uint32_t              HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup MDMA_Private_Types MDMA Private Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup MDMA_Private_Defines MDMA Private Defines
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup MDMA_Private_Variables MDMA Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup MDMA_Private_Constants MDMA Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup MDMA_Private_Macros MDMA Private Macros
+  * @{
+  */
+
+#define IS_MDMA_LEVEL_COMPLETE(__LEVEL__) (((__LEVEL__) == HAL_MDMA_FULL_TRANSFER )  || \
+                                           ((__LEVEL__) == HAL_MDMA_BUFFER_TRANSFER )|| \
+                                           ((__LEVEL__) == HAL_MDMA_BLOCK_TRANSFER ) || \
+                                           ((__LEVEL__) == HAL_MDMA_REPEAT_BLOCK_TRANSFER ))
+
+
+#define IS_MDMA_PRIORITY(__PRIORITY__) (((__PRIORITY__) == MDMA_PRIORITY_LOW )   || \
+                                        ((__PRIORITY__) == MDMA_PRIORITY_MEDIUM) || \
+                                        ((__PRIORITY__) == MDMA_PRIORITY_HIGH)   || \
+                                        ((__PRIORITY__) == MDMA_PRIORITY_VERY_HIGH))
+
+#define IS_MDMA_ENDIANNESS_MODE(__ENDIANNESS__) (((__ENDIANNESS__) == MDMA_LITTLE_ENDIANNESS_PRESERVE )         || \
+                                                 ((__ENDIANNESS__) == MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE)     || \
+                                                 ((__ENDIANNESS__) == MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE) || \
+                                                 ((__ENDIANNESS__) == MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE))
+
+
+#if defined (OCTOSPI2)
+#define IS_MDMA_REQUEST(__REQUEST__) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_OCTOSPI2_TC))
+#else
+#define IS_MDMA_REQUEST(__REQUEST__) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_SDMMC1_COMMAND_END))
+#endif /* OCTOSPI2 */
+
+#define IS_MDMA_SOURCE_INC(__INC__) (((__INC__) == MDMA_SRC_INC_DISABLE )   || \
+                                     ((__INC__) == MDMA_SRC_INC_BYTE )      || \
+                                     ((__INC__) == MDMA_SRC_INC_HALFWORD )  || \
+                                     ((__INC__) == MDMA_SRC_INC_WORD )      || \
+                                     ((__INC__) == MDMA_SRC_INC_DOUBLEWORD) || \
+                                     ((__INC__) == MDMA_SRC_DEC_BYTE)       || \
+                                     ((__INC__) == MDMA_SRC_DEC_HALFWORD)   || \
+                                     ((__INC__) == MDMA_SRC_DEC_WORD)       || \
+                                     ((__INC__) == MDMA_SRC_DEC_DOUBLEWORD))
+
+#define IS_MDMA_DESTINATION_INC(__INC__) (((__INC__) == MDMA_DEST_INC_DISABLE )   || \
+                                          ((__INC__) == MDMA_DEST_INC_BYTE )      || \
+                                          ((__INC__) == MDMA_DEST_INC_HALFWORD )  || \
+                                          ((__INC__) == MDMA_DEST_INC_WORD )      || \
+                                          ((__INC__) == MDMA_DEST_INC_DOUBLEWORD) || \
+                                          ((__INC__) == MDMA_DEST_DEC_BYTE)       || \
+                                          ((__INC__) == MDMA_DEST_DEC_HALFWORD)   || \
+                                          ((__INC__) == MDMA_DEST_DEC_WORD)       || \
+                                          ((__INC__) == MDMA_DEST_DEC_DOUBLEWORD))
+
+#define IS_MDMA_SOURCE_DATASIZE(__SIZE__) (((__SIZE__) == MDMA_SRC_DATASIZE_BYTE )     || \
+                                           ((__SIZE__) == MDMA_SRC_DATASIZE_HALFWORD ) || \
+                                           ((__SIZE__) == MDMA_SRC_DATASIZE_WORD )     || \
+                                           ((__SIZE__) == MDMA_SRC_DATASIZE_DOUBLEWORD))
+
+#define IS_MDMA_DESTINATION_DATASIZE(__SIZE__) (((__SIZE__) == MDMA_DEST_DATASIZE_BYTE )     || \
+                                                ((__SIZE__) == MDMA_DEST_DATASIZE_HALFWORD ) || \
+                                                ((__SIZE__) == MDMA_DEST_DATASIZE_WORD )     || \
+                                                ((__SIZE__) == MDMA_DEST_DATASIZE_DOUBLEWORD))
+
+#define IS_MDMA_DATA_ALIGNMENT(__ALIGNMENT__) (((__ALIGNMENT__) == MDMA_DATAALIGN_PACKENABLE )    || \
+                                               ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT )         || \
+                                               ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT_SIGNED )  || \
+                                               ((__ALIGNMENT__) == MDMA_DATAALIGN_LEFT))
+
+
+#define IS_MDMA_SOURCE_BURST(__BURST__) (((__BURST__) == MDMA_SOURCE_BURST_SINGLE ) || \
+                                         ((__BURST__) == MDMA_SOURCE_BURST_2BEATS ) || \
+                                         ((__BURST__) == MDMA_SOURCE_BURST_4BEATS ) || \
+                                         ((__BURST__) == MDMA_SOURCE_BURST_8BEATS)  || \
+                                         ((__BURST__) == MDMA_SOURCE_BURST_16BEATS) || \
+                                         ((__BURST__) == MDMA_SOURCE_BURST_32BEATS) || \
+                                         ((__BURST__) == MDMA_SOURCE_BURST_64BEATS) || \
+                                         ((__BURST__) == MDMA_SOURCE_BURST_128BEATS))
+
+
+#define IS_MDMA_DESTINATION_BURST(__BURST__) (((__BURST__) == MDMA_DEST_BURST_SINGLE ) || \
+                                              ((__BURST__) == MDMA_DEST_BURST_2BEATS ) || \
+                                              ((__BURST__) == MDMA_DEST_BURST_4BEATS ) || \
+                                              ((__BURST__) == MDMA_DEST_BURST_8BEATS)  || \
+                                              ((__BURST__) == MDMA_DEST_BURST_16BEATS) || \
+                                              ((__BURST__) == MDMA_DEST_BURST_32BEATS) || \
+                                              ((__BURST__) == MDMA_DEST_BURST_64BEATS) || \
+                                              ((__BURST__) == MDMA_DEST_BURST_128BEATS))
+
+ #define IS_MDMA_TRANSFER_TRIGGER_MODE(__MODE__) (((__MODE__) == MDMA_BUFFER_TRANSFER )      || \
+                                                  ((__MODE__) == MDMA_BLOCK_TRANSFER )        || \
+                                                  ((__MODE__) == MDMA_REPEAT_BLOCK_TRANSFER ) || \
+                                                  ((__MODE__) == MDMA_FULL_TRANSFER))
+
+#define IS_MDMA_BUFFER_TRANSFER_LENGTH(__LENGTH__) (((__LENGTH__) >= 0x00000001U) && ((__LENGTH__) < 0x000000FFU))
+
+#define IS_MDMA_BLOCK_COUNT(__COUNT__) (((__COUNT__) > 0U ) && ((__COUNT__) <= 4096U))
+
+#define IS_MDMA_TRANSFER_LENGTH(SIZE) (((SIZE) > 0U) && ((SIZE) <= 65536U))
+
+#define IS_MDMA_BLOCK_ADDR_OFFSET(__BLOCK_ADD_OFFSET__) (((__BLOCK_ADD_OFFSET__) > (-65536)) && ((__BLOCK_ADD_OFFSET__) < 65536))
+
+/**
+  * @}
+  */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup MDMA_Private_Functions_Prototypes MDMA Private Functions Prototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup MDMA_Private_Functions MDMA Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_MDMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h
new file mode 100644
index 00000000..0d462402
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h
@@ -0,0 +1,774 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_pwr.h
+  * @author  MCD Application Team
+  * @brief   Header file of PWR HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_PWR_H
+#define STM32H7xx_HAL_PWR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup PWR
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Types PWR Exported Types
+  * @{
+  */
+
+/**
+  * @brief  PWR PVD configuration structure definition
+  */
+typedef struct
+{
+  uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. This
+                                    parameter can be a value of @ref
+                                    PWR_PVD_detection_level.
+                     */
+
+  uint32_t Mode;     /*!< Mode: Specifies the EXTI operating mode for the PVD
+                                event. This parameter can be a value of @ref
+                                PWR_PVD_Mode.
+                     */
+}PWR_PVDTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PWR_Exported_Constants PWR Exported Constants
+  * @{
+  */
+
+/** @defgroup PWR_PVD_detection_level PWR PVD detection level
+  * @{
+  */
+#define PWR_PVDLEVEL_0  PWR_CR1_PLS_LEV0  /*!< Programmable voltage detector
+                                               level 0 selection : 1V95       */
+#define PWR_PVDLEVEL_1  PWR_CR1_PLS_LEV1  /*!< Programmable voltage detector
+                                               level 1 selection : 2V1        */
+#define PWR_PVDLEVEL_2  PWR_CR1_PLS_LEV2  /*!< Programmable voltage detector
+                                               level 2 selection : 2V25       */
+#define PWR_PVDLEVEL_3  PWR_CR1_PLS_LEV3  /*!< Programmable voltage detector
+                                               level 3 selection : 2V4        */
+#define PWR_PVDLEVEL_4  PWR_CR1_PLS_LEV4  /*!< Programmable voltage detector
+                                               level 4 selection : 2V55       */
+#define PWR_PVDLEVEL_5  PWR_CR1_PLS_LEV5  /*!< Programmable voltage detector
+                                               level 5 selection : 2V7        */
+#define PWR_PVDLEVEL_6  PWR_CR1_PLS_LEV6  /*!< Programmable voltage detector
+                                               level 6 selection : 2V85       */
+#define PWR_PVDLEVEL_7  PWR_CR1_PLS_LEV7  /*!< External input analog voltage
+                                               (Compare internally to VREF)   */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_PVD_Mode PWR PVD Mode
+  * @{
+  */
+#define PWR_PVD_MODE_NORMAL               (0x00000000U) /*!< Basic mode is used                                        */
+#define PWR_PVD_MODE_IT_RISING            (0x00010001U) /*!< Interrupt Mode with Rising edge trigger detection         */
+#define PWR_PVD_MODE_IT_FALLING           (0x00010002U) /*!< Interrupt Mode with Falling edge trigger detection        */
+#define PWR_PVD_MODE_IT_RISING_FALLING    (0x00010003U) /*!< Interrupt Mode with Rising/Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING         (0x00020001U) /*!< Event Mode with Rising edge trigger detection             */
+#define PWR_PVD_MODE_EVENT_FALLING        (0x00020002U) /*!< Event Mode with Falling edge trigger detection            */
+#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection     */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
+  * @{
+  */
+#define PWR_MAINREGULATOR_ON      (0U)
+#define PWR_LOWPOWERREGULATOR_ON  PWR_CR1_LPDS
+/**
+  * @}
+  */
+
+/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
+  * @{
+  */
+#define PWR_SLEEPENTRY_WFI  (0x01U)
+#define PWR_SLEEPENTRY_WFE  (0x02U)
+/**
+  * @}
+  */
+
+/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
+  * @{
+  */
+#define PWR_STOPENTRY_WFI  (0x01U)
+#define PWR_STOPENTRY_WFE  (0x02U)
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale
+  * @{
+  */
+#if defined(PWR_SRDCR_VOS)
+#define PWR_REGULATOR_VOLTAGE_SCALE0  (PWR_SRDCR_VOS_1 | PWR_SRDCR_VOS_0)
+#define PWR_REGULATOR_VOLTAGE_SCALE1  (PWR_SRDCR_VOS_1)
+#define PWR_REGULATOR_VOLTAGE_SCALE2  (PWR_SRDCR_VOS_0)
+#define PWR_REGULATOR_VOLTAGE_SCALE3  (0U)
+#else
+#define PWR_REGULATOR_VOLTAGE_SCALE0  (0U)
+#define PWR_REGULATOR_VOLTAGE_SCALE1  (PWR_D3CR_VOS_1 | PWR_D3CR_VOS_0)
+#define PWR_REGULATOR_VOLTAGE_SCALE2  (PWR_D3CR_VOS_1)
+#define PWR_REGULATOR_VOLTAGE_SCALE3  (PWR_D3CR_VOS_0)
+#endif /* PWR_SRDCR_VOS */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Flag PWR Flag
+  * @{
+  */
+/* PWR CPU flag */
+#define PWR_FLAG_STOP       (0x01U)
+#if defined (PWR_CPUCR_SBF_D2)
+#define PWR_FLAG_SB_D1      (0x02U)
+#define PWR_FLAG_SB_D2      (0x03U)
+#endif /* defined (PWR_CPUCR_SBF_D2) */
+#define PWR_FLAG_SB         (0x04U)
+#if defined (DUAL_CORE)
+#define PWR_FLAG_CPU_HOLD   (0x05U)
+#define PWR_FLAG_CPU2_HOLD  (0x06U)
+#define PWR_FLAG2_STOP      (0x07U)
+#define PWR_FLAG2_SB_D1     (0x08U)
+#define PWR_FLAG2_SB_D2     (0x09U)
+#define PWR_FLAG2_SB        (0x0AU)
+#endif /* defined (DUAL_CORE) */
+#define PWR_FLAG_PVDO       (0x0BU)
+#define PWR_FLAG_AVDO       (0x0CU)
+#define PWR_FLAG_ACTVOSRDY  (0x0DU)
+#define PWR_FLAG_ACTVOS     (0x0EU)
+#define PWR_FLAG_BRR        (0x0FU)
+#define PWR_FLAG_VOSRDY     (0x10U)
+#if defined (SMPS)
+#define PWR_FLAG_SMPSEXTRDY (0x11U)
+#else
+#define PWR_FLAG_SCUEN      (0x11U)
+#endif /* defined (SMPS) */
+#if defined (PWR_CSR1_MMCVDO)
+#define PWR_FLAG_MMCVDO     (0x12U)
+#endif /* defined (PWR_CSR1_MMCVDO) */
+#define PWR_FLAG_USB33RDY   (0x13U)
+#define PWR_FLAG_TEMPH      (0x14U)
+#define PWR_FLAG_TEMPL      (0x15U)
+#define PWR_FLAG_VBATH      (0x16U)
+#define PWR_FLAG_VBATL      (0x17U)
+
+/* PWR Wake up flag */
+#define PWR_FLAG_WKUP1 PWR_WKUPCR_WKUPC1
+#define PWR_FLAG_WKUP2 PWR_WKUPCR_WKUPC2
+#define PWR_FLAG_WKUP3 PWR_WKUPCR_WKUPC3
+#define PWR_FLAG_WKUP4 PWR_WKUPCR_WKUPC4
+#define PWR_FLAG_WKUP5 PWR_WKUPCR_WKUPC5
+#define PWR_FLAG_WKUP6 PWR_WKUPCR_WKUPC6
+/**
+  * @}
+  */
+
+/** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask
+  * @{
+  */
+#define  PWR_EWUP_MASK  (0x0FFF3F3FU)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PWR_Exported_Macro PWR Exported Macro
+  * @{
+  */
+
+/** @brief  Configure the main internal regulator output voltage.
+  * @param  __REGULATOR__ : Specifies the regulator output voltage to achieve a
+  *                         trade-off between performance and power consumption
+  *                         when the device does not operate at the maximum
+  *                         frequency (refer to the datasheet for more details).
+  *          This parameter can be one of the following values:
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE0 : Regulator voltage output
+  *                                                Scale 0 mode.
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output
+  *                                                Scale 1 mode.
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output
+  *                                                Scale 2 mode.
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output
+  *                                                Scale 3 mode.
+  * @note   For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines,
+  *         configuring Voltage Scale 0 is only possible when Vcore is supplied
+  *         from LDO (Low DropOut). The SYSCFG Clock must be enabled through
+  *         __HAL_RCC_SYSCFG_CLK_ENABLE() macro before configuring Voltage Scale
+  *         0 using __HAL_PWR_VOLTAGESCALING_CONFIG().
+  *         Transition to Voltage Scale 0 is only possible when the system is
+  *         already in Voltage Scale 1.
+  *         Transition from Voltage Scale 0 is only possible to Voltage Scale 1
+  *         then once in Voltage Scale 1 it is possible to switch to another
+  *         voltage scale.
+  *         After each regulator voltage setting, wait on VOSRDY flag to be set
+  *         using macro __HAL_PWR_GET_FLAG().
+  *         To enter low power mode , and if current regulator voltage is
+  *         Voltage Scale 0 then first switch to Voltage Scale 1 before entering
+  *         low power mode.
+  * @retval None.
+  */
+#if defined(PWR_SRDCR_VOS) /* STM32H7Axxx and STM32H7Bxxx lines */
+#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__)                         \
+do {                                                                           \
+      __IO uint32_t tmpreg = 0x00;                                             \
+      MODIFY_REG(PWR->SRDCR, PWR_SRDCR_VOS, (__REGULATOR__));                  \
+      /* Delay after setting the voltage scaling */                            \
+      tmpreg = READ_BIT(PWR->SRDCR, PWR_SRDCR_VOS);                            \
+      UNUSED(tmpreg);                                                          \
+} while(0)
+#else /* All H7 lines except STM32H7Axxx and STM32H7Bxxx lines */
+#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__)                         \
+do {                                                                           \
+      __IO uint32_t tmpreg = 0x00;                                             \
+      /* Check the voltage scaling to be configured */                         \
+      if((__REGULATOR__) == PWR_REGULATOR_VOLTAGE_SCALE0)                      \
+      {                                                                        \
+        /* Configure the Voltage Scaling 1 */                                  \
+        MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);     \
+        /* Delay after setting the voltage scaling */                          \
+        tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS);                            \
+        /* Enable the PWR overdrive */                                         \
+        SET_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);                             \
+        /* Delay after setting the syscfg boost setting */                     \
+        tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);                   \
+      }                                                                        \
+      else                                                                     \
+      {                                                                        \
+        /* Disable the PWR overdrive */                                        \
+        CLEAR_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);                           \
+        /* Delay after setting the syscfg boost setting */                     \
+        tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);                   \
+        /* Configure the Voltage Scaling x */                                  \
+        MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__));                  \
+        /* Delay after setting the voltage scaling */                          \
+        tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS);                            \
+      }                                                                        \
+      UNUSED(tmpreg);                                                          \
+} while(0)
+#endif /* PWR_SRDCR_VOS */
+
+/** @brief  Check PWR flags are set or not.
+  * @param  __FLAG__ : Specifies the flag to check.
+  *           This parameter can be one of the following values:
+  *            @arg PWR_FLAG_PVDO : PVD Output. This flag is valid only if PVD
+  *                                 is enabled by the HAL_PWR_EnablePVD()
+  *                                 function.
+  *                                 The PVD is stopped by STANDBY mode. For this
+  *                                 reason, this bit is equal to 0 after STANDBY
+  *                                 or reset until the PVDE bit is set.
+  *            @arg PWR_FLAG_AVDO : AVD Output. This flag is valid only if AVD
+  *                                 is enabled by the HAL_PWREx_EnableAVD()
+  *                                 function. The AVD is stopped by STANDBY mode.
+  *                                 For this reason, this bit is equal to 0
+  *                                 after STANDBY or reset until the AVDE bit
+  *                                 is set.
+  *            @arg PWR_FLAG_ACTVOSRDY : This flag indicates that the Regulator
+  *                                      voltage scaling output selection is
+  *                                      ready.
+  *            @arg PWR_FLAG_BRR : Backup regulator ready flag. This bit is not
+  *                                reset when the device wakes up from STANDBY
+  *                                mode or by a system reset or power-on reset.
+  *            @arg PWR_FLAG_VOSRDY : This flag indicates that the Regulator
+  *                                   voltage scaling output selection is ready.
+  *                                mode or by a system reset or power-on reset.
+  *            @arg PWR_FLAG_USB33RDY : This flag indicates that the USB supply
+  *                                     from regulator is ready.
+  *            @arg PWR_FLAG_TEMPH : This flag indicates that the temperature
+  *                                  equal or above high threshold level.
+  *            @arg PWR_FLAG_TEMPL : This flag indicates that the temperature
+  *                                  equal or below low threshold level.
+  *            @arg PWR_FLAG_VBATH : This flag indicates that VBAT level equal
+  *                                  or above high threshold level.
+  *            @arg PWR_FLAG_VBATL : This flag indicates that VBAT level equal
+  *                                  or below low threshold level.
+  *            @arg PWR_FLAG_STOP : This flag indicates that the system entered
+  *                                 in STOP mode.
+  *            @arg PWR_FLAG_SB : This flag indicates that the system entered in
+  *                               STANDBY mode.
+  *            @arg PWR_FLAG_SB_D1 : This flag indicates that the D1 domain
+  *                                  entered in STANDBY mode.
+  *            @arg PWR_FLAG_SB_D2 : This flag indicates that the D2 domain
+  *                                  entered in STANDBY mode.
+  *            @arg PWR_FLAG2_STOP : This flag indicates that the system entered
+  *                                 in STOP mode.
+  *            @arg PWR_FLAG2_SB : This flag indicates that the system entered
+  *                                in STANDBY mode.
+  *            @arg PWR_FLAG2_SB_D1 : This flag indicates that the D1 domain
+  *                                   entered in STANDBY mode.
+  *            @arg PWR_FLAG2_SB_D2 : This flag indicates that the D2 domain
+  *                                   entered in STANDBY mode.
+  *            @arg PWR_FLAG_CPU_HOLD : This flag indicates that the CPU1 wakes
+  *                                     up with hold.
+  *            @arg PWR_FLAG_CPU2_HOLD : This flag indicates that the CPU2 wakes
+  *                                      up with hold.
+  *            @arg PWR_FLAG_SMPSEXTRDY : This flag indicates that the SMPS
+  *                                       External supply is sready.
+  *            @arg PWR_FLAG_SCUEN : This flag indicates that the supply
+  *                                  configuration update is enabled.
+  *            @arg PWR_FLAG_MMCVDO : This flag indicates that the VDDMMC is
+  *                                   above or equal to 1.2 V.
+  * @note   The PWR_FLAG_PVDO, PWR_FLAG_AVDO, PWR_FLAG_ACTVOSRDY, PWR_FLAG_BRR,
+  *         PWR_FLAG_VOSRDY, PWR_FLAG_USB33RDY, PWR_FLAG_TEMPH, PWR_FLAG_TEMPL,
+  *         PWR_FLAG_VBATH, PWR_FLAG_VBATL, PWR_FLAG_STOP and PWR_FLAG_SB flags
+  *         are used for all H7 family lines.
+  *         The PWR_FLAG2_STOP, PWR_FLAG2_SB, PWR_FLAG2_SB_D1, PWR_FLAG2_SB_D2,
+  *         PWR_FLAG_CPU_HOLD and PWR_FLAG_CPU2_HOLD flags are used only for H7
+  *         dual core lines.
+  *         The PWR_FLAG_SB_D1 and PWR_FLAG_SB_D2 flags are used for all H7
+  *         family except STM32H7Axxx and STM32H7Bxxx lines.
+  *         The PWR_FLAG_MMCVDO flag is used only for STM32H7Axxx and
+  *         STM32H7Bxxx lines.
+  *         The PWR_FLAG_SCUEN flag is used for STM32H743, STM32H753, STM32H742,
+  *         STM32H750, STM32H7Axx and STM32H7Bxx lines.
+  *         The PWR_FLAG_SMPSEXTRDY flag is used for dual core and STM32H7AxxQ,
+  *         STM32H7BxxQ lines.
+  * @retval The (__FLAG__) state (TRUE or FALSE).
+  */
+#if defined (DUAL_CORE) /* Dual core lines */
+#define __HAL_PWR_GET_FLAG(__FLAG__)                                                              \
+(((__FLAG__) == PWR_FLAG_PVDO)       ? ((PWR->CSR1 & PWR_CSR1_PVDO)       == PWR_CSR1_PVDO)      :\
+ ((__FLAG__) == PWR_FLAG_AVDO)       ? ((PWR->CSR1 & PWR_CSR1_AVDO)       == PWR_CSR1_AVDO)      :\
+ ((__FLAG__) == PWR_FLAG_ACTVOSRDY)  ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY)  == PWR_CSR1_ACTVOSRDY) :\
+ ((__FLAG__) == PWR_FLAG_VOSRDY)     ? ((PWR->D3CR & PWR_D3CR_VOSRDY)     == PWR_D3CR_VOSRDY)    :\
+ ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_CR3_SMPSEXTRDY)   == PWR_CR3_SMPSEXTRDY) :\
+ ((__FLAG__) == PWR_FLAG_BRR)        ? ((PWR->CR2 & PWR_CR2_BRRDY)        == PWR_CR2_BRRDY)      :\
+ ((__FLAG__) == PWR_FLAG_CPU_HOLD)   ? ((PWR->CPU2CR & PWR_CPU2CR_HOLD1F) == PWR_CPU2CR_HOLD1F)  :\
+ ((__FLAG__) == PWR_FLAG_CPU2_HOLD)  ? ((PWR->CPUCR & PWR_CPUCR_HOLD2F)   == PWR_CPUCR_HOLD2F)   :\
+ ((__FLAG__) == PWR_FLAG_SB)         ? ((PWR->CPUCR & PWR_CPUCR_SBF)      == PWR_CPUCR_SBF)      :\
+ ((__FLAG__) == PWR_FLAG2_SB)        ? ((PWR->CPU2CR & PWR_CPU2CR_SBF)    == PWR_CPU2CR_SBF)     :\
+ ((__FLAG__) == PWR_FLAG_STOP)       ? ((PWR->CPUCR & PWR_CPUCR_STOPF)    == PWR_CPUCR_STOPF)    :\
+ ((__FLAG__) == PWR_FLAG2_STOP)      ? ((PWR->CPU2CR & PWR_CPU2CR_STOPF)  == PWR_CPU2CR_STOPF)   :\
+ ((__FLAG__) == PWR_FLAG_SB_D1)      ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1)   == PWR_CPUCR_SBF_D1)   :\
+ ((__FLAG__) == PWR_FLAG2_SB_D1)     ? ((PWR->CPU2CR & PWR_CPU2CR_SBF_D1) == PWR_CPU2CR_SBF_D1)  :\
+ ((__FLAG__) == PWR_FLAG_SB_D2)      ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2)   == PWR_CPUCR_SBF_D2)   :\
+ ((__FLAG__) == PWR_FLAG2_SB_D2)     ? ((PWR->CPU2CR & PWR_CPU2CR_SBF_D2) == PWR_CPU2CR_SBF_D2)  :\
+ ((__FLAG__) == PWR_FLAG_USB33RDY)   ? ((PWR->CR3 & PWR_CR3_USB33RDY)     == PWR_CR3_USB33RDY)   :\
+ ((__FLAG__) == PWR_FLAG_TEMPH)      ? ((PWR->CR2 & PWR_CR2_TEMPH)        == PWR_CR2_TEMPH)      :\
+ ((__FLAG__) == PWR_FLAG_TEMPL)      ? ((PWR->CR2 & PWR_CR2_TEMPL)        == PWR_CR2_TEMPL)      :\
+ ((__FLAG__) == PWR_FLAG_VBATH)      ? ((PWR->CR2 & PWR_CR2_VBATH)        == PWR_CR2_VBATH)      :\
+ ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
+#else /* Single core lines */
+#if defined (PWR_CPUCR_SBF_D2) /* STM32H743, STM32H753, STM32H742 and STM32H750 lines */
+#define __HAL_PWR_GET_FLAG(__FLAG__)                                                            \
+(((__FLAG__) == PWR_FLAG_PVDO)      ? ((PWR->CSR1 & PWR_CSR1_PVDO)      == PWR_CSR1_PVDO)      :\
+ ((__FLAG__) == PWR_FLAG_AVDO)      ? ((PWR->CSR1 & PWR_CSR1_AVDO)      == PWR_CSR1_AVDO)      :\
+ ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
+ ((__FLAG__) == PWR_FLAG_VOSRDY)    ? ((PWR->D3CR & PWR_D3CR_VOSRDY)    == PWR_D3CR_VOSRDY)    :\
+ ((__FLAG__) == PWR_FLAG_SCUEN)     ? ((PWR->CR3 & PWR_CR3_SCUEN)       == PWR_CR3_SCUEN)      :\
+ ((__FLAG__) == PWR_FLAG_BRR)       ? ((PWR->CR2 & PWR_CR2_BRRDY)       == PWR_CR2_BRRDY)      :\
+ ((__FLAG__) == PWR_FLAG_SB)        ? ((PWR->CPUCR & PWR_CPUCR_SBF)     == PWR_CPUCR_SBF)      :\
+ ((__FLAG__) == PWR_FLAG_STOP)      ? ((PWR->CPUCR & PWR_CPUCR_STOPF)   == PWR_CPUCR_STOPF)    :\
+ ((__FLAG__) == PWR_FLAG_SB_D1)     ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1)  == PWR_CPUCR_SBF_D1)   :\
+ ((__FLAG__) == PWR_FLAG_SB_D2)     ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2)  == PWR_CPUCR_SBF_D2)   :\
+ ((__FLAG__) == PWR_FLAG_USB33RDY)  ? ((PWR->CR3 & PWR_CR3_USB33RDY)    == PWR_CR3_USB33RDY)   :\
+ ((__FLAG__) == PWR_FLAG_TEMPH)     ? ((PWR->CR2 & PWR_CR2_TEMPH)       == PWR_CR2_TEMPH)      :\
+ ((__FLAG__) == PWR_FLAG_TEMPL)     ? ((PWR->CR2 & PWR_CR2_TEMPL)       == PWR_CR2_TEMPL)      :\
+ ((__FLAG__) == PWR_FLAG_VBATH)     ? ((PWR->CR2 & PWR_CR2_VBATH)       == PWR_CR2_VBATH)      :\
+ ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
+#else /* STM32H7Axxx and STM32H7Bxxx lines */
+#if defined (SMPS) /* STM32H7AxxQ and STM32H7BxxQ SMPS lines */
+#define __HAL_PWR_GET_FLAG(__FLAG__)                                                            \
+(((__FLAG__) == PWR_FLAG_PVDO)       ? ((PWR->CSR1 & PWR_CSR1_PVDO)      == PWR_CSR1_PVDO)      :\
+ ((__FLAG__) == PWR_FLAG_AVDO)       ? ((PWR->CSR1 & PWR_CSR1_AVDO)      == PWR_CSR1_AVDO)      :\
+ ((__FLAG__) == PWR_FLAG_ACTVOSRDY)  ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
+ ((__FLAG__) == PWR_FLAG_BRR)        ? ((PWR->CR2 & PWR_CR2_BRRDY)       == PWR_CR2_BRRDY)      :\
+ ((__FLAG__) == PWR_FLAG_VOSRDY)     ? ((PWR->SRDCR & PWR_SRDCR_VOSRDY)  == PWR_SRDCR_VOSRDY)   :\
+ ((__FLAG__) == PWR_FLAG_STOP)       ? ((PWR->CPUCR & PWR_CPUCR_STOPF)   == PWR_CPUCR_STOPF)    :\
+ ((__FLAG__) == PWR_FLAG_SB)         ? ((PWR->CPUCR & PWR_CPUCR_SBF)     == PWR_CPUCR_SBF)      :\
+ ((__FLAG__) == PWR_FLAG_MMCVDO)     ? ((PWR->CSR1 & PWR_CSR1_MMCVDO)    == PWR_CSR1_MMCVDO)    :\
+ ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_CR3_SMPSEXTRDY)  == PWR_CR3_SMPSEXTRDY) :\
+ ((__FLAG__) == PWR_FLAG_USB33RDY)   ? ((PWR->CR3 & PWR_CR3_USB33RDY)    == PWR_CR3_USB33RDY)   :\
+ ((__FLAG__) == PWR_FLAG_TEMPH)      ? ((PWR->CR2 & PWR_CR2_TEMPH)       == PWR_CR2_TEMPH)      :\
+ ((__FLAG__) == PWR_FLAG_TEMPL)      ? ((PWR->CR2 & PWR_CR2_TEMPL)       == PWR_CR2_TEMPL)      :\
+ ((__FLAG__) == PWR_FLAG_VBATH)      ? ((PWR->CR2 & PWR_CR2_VBATH)       == PWR_CR2_VBATH)      :\
+ ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
+#else /* STM32H7Axx and STM32H7Bxx LDO lines */
+#define __HAL_PWR_GET_FLAG(__FLAG__)                                    \
+(((__FLAG__) == PWR_FLAG_PVDO)      ? ((PWR->CSR1 & PWR_CSR1_PVDO)      == PWR_CSR1_PVDO)      :\
+ ((__FLAG__) == PWR_FLAG_AVDO)      ? ((PWR->CSR1 & PWR_CSR1_AVDO)      == PWR_CSR1_AVDO)      :\
+ ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
+ ((__FLAG__) == PWR_FLAG_BRR)       ? ((PWR->CR2 & PWR_CR2_BRRDY)       == PWR_CR2_BRRDY)      :\
+ ((__FLAG__) == PWR_FLAG_VOSRDY)    ? ((PWR->SRDCR & PWR_SRDCR_VOSRDY)  == PWR_SRDCR_VOSRDY)   :\
+ ((__FLAG__) == PWR_FLAG_SCUEN)     ? ((PWR->CR3 & PWR_CR3_SCUEN)       == PWR_CR3_SCUEN)      :\
+ ((__FLAG__) == PWR_FLAG_STOP)      ? ((PWR->CPUCR & PWR_CPUCR_STOPF)   == PWR_CPUCR_STOPF)    :\
+ ((__FLAG__) == PWR_FLAG_SB)        ? ((PWR->CPUCR & PWR_CPUCR_SBF)     == PWR_CPUCR_SBF)      :\
+ ((__FLAG__) == PWR_FLAG_MMCVDO)    ? ((PWR->CSR1 & PWR_CSR1_MMCVDO)    == PWR_CSR1_MMCVDO)    :\
+ ((__FLAG__) == PWR_FLAG_USB33RDY)  ? ((PWR->CR3 & PWR_CR3_USB33RDY)    == PWR_CR3_USB33RDY)   :\
+ ((__FLAG__) == PWR_FLAG_TEMPH)     ? ((PWR->CR2 & PWR_CR2_TEMPH)       == PWR_CR2_TEMPH)      :\
+ ((__FLAG__) == PWR_FLAG_TEMPL)     ? ((PWR->CR2 & PWR_CR2_TEMPL)       == PWR_CR2_TEMPL)      :\
+ ((__FLAG__) == PWR_FLAG_VBATH)     ? ((PWR->CR2 & PWR_CR2_VBATH)       == PWR_CR2_VBATH)      :\
+ ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
+#endif /* SMPS */
+#endif /* PWR_CPUCR_SBF_D2 */
+#endif /* DUAL_CORE */
+
+/** @brief  Check PWR wake up flags are set or not.
+  * @param  __FLAG__: specifies the wake up flag to check.
+  *           This parameter can be one of the following values:
+  *            @arg PWR_FLAG_WKUP1 : This parameter clear Wake up line 1 flag.
+  *            @arg PWR_FLAG_WKUP2 : This parameter clear Wake up line 2 flag.
+  *            @arg PWR_FLAG_WKUP3 : This parameter clear Wake up line 3 flag.
+  *            @arg PWR_FLAG_WKUP4 : This parameter clear Wake up line 4 flag.
+  *            @arg PWR_FLAG_WKUP5 : This parameter clear Wake up line 5 flag.
+  *            @arg PWR_FLAG_WKUP6 : This parameter clear Wake up line 6 flag.
+  * @retval The (__FLAG__) state (TRUE or FALSE).
+  */
+#define __HAL_PWR_GET_WAKEUPFLAG(__FLAG__) ((PWR->WKUPFR & (__FLAG__)) ? 0 : 1)
+
+#if defined (DUAL_CORE)
+/** @brief  Clear CPU PWR flags.
+  * @param  __FLAG__ : Specifies the flag to clear.
+  * @note   This parameter is not used for the STM32H7 family and is kept as
+  *         parameter just to maintain compatibility with other families.
+  * @note   This macro clear all CPU flags STOPF, SBF, SBF_D1, and SBF_D2.
+  *           This parameter can be one of the following values :
+  *            @arg PWR_CPU_FLAGS : Clear HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2
+  *                                 CPU flags.
+  * @retval None.
+  */
+#define __HAL_PWR_CLEAR_FLAG(__FLAG__)      \
+do {                                        \
+     SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF);   \
+     SET_BIT(PWR->CPU2CR, PWR_CPU2CR_CSSF); \
+} while(0)
+#else
+/** @brief  Clear CPU PWR flags.
+  * @param  __FLAG__ : Specifies the flag to clear.
+  * @note   This parameter is not used for the STM32H7 family and is kept as
+  *         parameter just to maintain compatibility with other families.
+  * @note   This macro clear all CPU flags.
+  *         For STM32H7Axxx and STM32H7Bxxx lines CPU flags are STOPF and SBF.
+  *         For dual core lines flags are HOLDxF, STOPF, SBF and SBF_Dx.
+  * @retval None.
+  */
+#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF)
+#endif /* defined (DUAL_CORE) */
+
+/** @brief  Clear PWR wake up flags.
+  * @param  __FLAG__ : Specifies the wake up flag to be cleared.
+  *           This parameter can be one of the following values :
+  *            @arg PWR_FLAG_WKUP1 : This parameter clear Wake up line 1 flag.
+  *            @arg PWR_FLAG_WKUP2 : This parameter clear Wake up line 2 flag.
+  *            @arg PWR_FLAG_WKUP3 : This parameter clear Wake up line 3 flag.
+  *            @arg PWR_FLAG_WKUP4 : This parameter clear Wake up line 4 flag.
+  *            @arg PWR_FLAG_WKUP5 : This parameter clear Wake up line 5 flag.
+  *            @arg PWR_FLAG_WKUP6 : This parameter clear Wake up line 6 flag.
+  * @retval None.
+  */
+#define __HAL_PWR_CLEAR_WAKEUPFLAG(__FLAG__) SET_BIT(PWR->WKUPCR, (__FLAG__))
+
+/**
+  * @brief Enable the PVD EXTI Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Enable the PVD EXTI D2 Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief Disable the PVD EXTI Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Disable the PVD EXTI D2 Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief   Enable event on PVD EXTI Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Enable event on PVD EXTI D2 Line.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief   Disable event on PVD EXTI Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Disable event on PVD EXTI D2 Line.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief Enable the PVD Rising Interrupt Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Disable the PVD Rising Interrupt Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Enable the PVD Falling Interrupt Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Disable the PVD Falling Interrupt Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Enable the PVD Rising & Falling Interrupt Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
+do {                                                    \
+      __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();          \
+      __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();         \
+} while(0);
+
+/**
+  * @brief Disable the PVD Rising & Falling Interrupt Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
+do {                                                     \
+      __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();          \
+      __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();         \
+} while(0);
+
+/**
+  * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
+  * @retval EXTI PVD Line Status.
+  */
+#define __HAL_PWR_PVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Checks whether the specified PVD EXTI interrupt flag is set or not.
+  * @retval EXTI D2 PVD Line Status.
+  */
+#define __HAL_PWR_PVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief Clear the PVD EXTI flag.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Clear the PVD EXTI D2 flag.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief  Generates a Software interrupt on PVD EXTI line.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
+/**
+  * @}
+  */
+
+/* Include PWR HAL Extension module */
+#include "stm32h7xx_hal_pwr_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PWR_Exported_Functions PWR Exported Functions
+  * @{
+  */
+
+/** @addtogroup PWR_Exported_Functions_Group1 Initialization and De-Initialization functions
+  * @{
+  */
+/* Initialization and de-initialization functions *****************************/
+void HAL_PWR_DeInit(void);
+void HAL_PWR_EnableBkUpAccess(void);
+void HAL_PWR_DisableBkUpAccess(void);
+/**
+  * @}
+  */
+
+/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
+  * @{
+  */
+/* Peripheral Control functions  **********************************************/
+/* PVD configuration */
+void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
+void HAL_PWR_EnablePVD(void);
+void HAL_PWR_DisablePVD(void);
+
+/* WakeUp pins configuration */
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
+
+/* Low Power modes entry */
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
+void HAL_PWR_EnterSTANDBYMode(void);
+
+/* Power PVD IRQ Handler */
+void HAL_PWR_PVD_IRQHandler(void);
+void HAL_PWR_PVDCallback(void);
+
+/* Cortex System Control functions  *******************************************/
+void HAL_PWR_EnableSleepOnExit(void);
+void HAL_PWR_DisableSleepOnExit(void);
+void HAL_PWR_EnableSEVOnPend(void);
+void HAL_PWR_DisableSEVOnPend(void);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup PWR_Private_Constants PWR Private Constants
+  * @{
+  */
+
+/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line
+  * @{
+  */
+#define PWR_EXTI_LINE_PVD  EXTI_IMR1_IM16 /*!< External interrupt line 16
+                                               Connected to the PVD EXTI Line */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PWR_Private_Macros PWR Private Macros
+  * @{
+  */
+
+/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters
+  * @{
+  */
+/* Check PVD level parameter */
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) ||\
+                                 ((LEVEL) == PWR_PVDLEVEL_1) ||\
+                                 ((LEVEL) == PWR_PVDLEVEL_2) ||\
+                                 ((LEVEL) == PWR_PVDLEVEL_3) ||\
+                                 ((LEVEL) == PWR_PVDLEVEL_4) ||\
+                                 ((LEVEL) == PWR_PVDLEVEL_5) ||\
+                                 ((LEVEL) == PWR_PVDLEVEL_6) ||\
+                                 ((LEVEL) == PWR_PVDLEVEL_7))
+
+/* Check PVD mode parameter */
+#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)            ||\
+                               ((MODE) == PWR_PVD_MODE_IT_FALLING)           ||\
+                               ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING)    ||\
+                               ((MODE) == PWR_PVD_MODE_EVENT_RISING)         ||\
+                               ((MODE) == PWR_PVD_MODE_EVENT_FALLING)        ||\
+                               ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) ||\
+                               ((MODE) == PWR_PVD_MODE_NORMAL))
+
+/* Check low power regulator parameter */
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON)   ||\
+                                     ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
+
+/* Check low power mode entry parameter */
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) ||\
+                                   ((ENTRY) == PWR_SLEEPENTRY_WFE))
+
+/* Check low power mode entry parameter */
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) ||\
+                                  ((ENTRY) == PWR_STOPENTRY_WFE))
+
+/* Check voltage scale level parameter */
+#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE0) || \
+                                           ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
+                                           ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
+                                           ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* STM32H7xx_HAL_PWR_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h
new file mode 100644
index 00000000..ebad73c5
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h
@@ -0,0 +1,743 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_pwr_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of PWR HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_PWR_EX_H
+#define STM32H7xx_HAL_PWR_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup PWREx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup PWREx_Exported_Types PWREx Exported Types
+  * @{
+  */
+/**
+  * @brief  PWREx AVD configuration structure definition
+  */
+typedef struct
+{
+  uint32_t AVDLevel; /*!< AVDLevel : Specifies the AVD detection level. This
+                          parameter can be a value of @ref
+                          PWREx_AVD_detection_level
+                     */
+
+  uint32_t Mode;     /*!< Mode : Specifies the EXTI operating mode for the AVD
+                                 event. This parameter can be a value of @ref
+                                 PWREx_AVD_Mode.
+                     */
+}PWREx_AVDTypeDef;
+
+/**
+  * @brief  PWREx Wakeup pin configuration structure definition
+  */
+typedef struct
+{
+  uint32_t WakeUpPin;   /*!< WakeUpPin: Specifies the Wake-Up pin to be enabled.
+                                        This parameter can be a value of @ref
+                                        PWREx_WakeUp_Pins
+                        */
+
+  uint32_t PinPolarity; /*!< PinPolarity: Specifies the Wake-Up pin polarity.
+                                          This parameter can be a value of @ref
+                                          PWREx_PIN_Polarity
+                        */
+
+  uint32_t PinPull;     /*!< PinPull: Specifies the Wake-Up pin pull. This
+                                      parameter can be a value of @ref
+                                      PWREx_PIN_Pull
+                        */
+}PWREx_WakeupPinTypeDef;
+
+#if defined (PWR_CSR1_MMCVDO)
+/**
+  * @brief  PWR VDDMMC voltage level enum definition
+  */
+typedef enum
+{
+  PWR_MMC_VOLTAGE_BELOW_1V2,      /*!< VDDMMC is below 1V2          */
+  PWR_MMC_VOLTAGE_EQUAL_ABOVE_1V2 /*!< VDDMMC is above or equal 1V2 */
+} PWREx_MMC_VoltageLevel;
+#endif /* defined (PWR_CSR1_MMCVDO) */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PWREx_Exported_Constants PWREx Exported Constants
+  * @{
+  */
+/** @defgroup PWREx_WakeUp_Pins PWREx Wake-Up Pins
+  * @{
+  */
+/* High level and No pull (default configuration) */
+#define PWR_WAKEUP_PIN6      PWR_WKUPEPR_WKUPEN6
+#define PWR_WAKEUP_PIN5      PWR_WKUPEPR_WKUPEN5
+#define PWR_WAKEUP_PIN4      PWR_WKUPEPR_WKUPEN4
+#define PWR_WAKEUP_PIN3      PWR_WKUPEPR_WKUPEN3
+#define PWR_WAKEUP_PIN2      PWR_WKUPEPR_WKUPEN2
+#define PWR_WAKEUP_PIN1      PWR_WKUPEPR_WKUPEN1
+
+/* High level and No pull */
+#define PWR_WAKEUP_PIN6_HIGH PWR_WKUPEPR_WKUPEN6
+#define PWR_WAKEUP_PIN5_HIGH PWR_WKUPEPR_WKUPEN5
+#define PWR_WAKEUP_PIN4_HIGH PWR_WKUPEPR_WKUPEN4
+#define PWR_WAKEUP_PIN3_HIGH PWR_WKUPEPR_WKUPEN3
+#define PWR_WAKEUP_PIN2_HIGH PWR_WKUPEPR_WKUPEN2
+#define PWR_WAKEUP_PIN1_HIGH PWR_WKUPEPR_WKUPEN1
+
+/* Low level and No pull */
+#define PWR_WAKEUP_PIN6_LOW  (PWR_WKUPEPR_WKUPP6 | PWR_WKUPEPR_WKUPEN6)
+#define PWR_WAKEUP_PIN5_LOW  (PWR_WKUPEPR_WKUPP5 | PWR_WKUPEPR_WKUPEN5)
+#define PWR_WAKEUP_PIN4_LOW  (PWR_WKUPEPR_WKUPP4 | PWR_WKUPEPR_WKUPEN4)
+#define PWR_WAKEUP_PIN3_LOW  (PWR_WKUPEPR_WKUPP3 | PWR_WKUPEPR_WKUPEN3)
+#define PWR_WAKEUP_PIN2_LOW  (PWR_WKUPEPR_WKUPP2 | PWR_WKUPEPR_WKUPEN2)
+#define PWR_WAKEUP_PIN1_LOW  (PWR_WKUPEPR_WKUPP1 | PWR_WKUPEPR_WKUPEN1)
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_PIN_Polarity PWREx Pin Polarity configuration
+  * @{
+  */
+#define PWR_PIN_POLARITY_HIGH (0x00000000U)
+#define PWR_PIN_POLARITY_LOW  (0x00000001U)
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_PIN_Pull PWREx Pin Pull configuration
+  * @{
+  */
+#define PWR_PIN_NO_PULL   (0x00000000U)
+#define PWR_PIN_PULL_UP   (0x00000001U)
+#define PWR_PIN_PULL_DOWN (0x00000002U)
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_Wakeup_Pins_Flags PWREx Wakeup Pins Flags.
+  * @{
+  */
+#define PWR_WAKEUP_FLAG1 PWR_WKUPFR_WKUPF1 /*!< Wakeup flag on PA0  */
+#define PWR_WAKEUP_FLAG2 PWR_WKUPFR_WKUPF2 /*!< Wakeup flag on PA2  */
+#define PWR_WAKEUP_FLAG3 PWR_WKUPFR_WKUPF3 /*!< Wakeup flag on PI8  */
+#define PWR_WAKEUP_FLAG4 PWR_WKUPFR_WKUPF4 /*!< Wakeup flag on PC13 */
+#define PWR_WAKEUP_FLAG5 PWR_WKUPFR_WKUPF5 /*!< Wakeup flag on PI11 */
+#define PWR_WAKEUP_FLAG6 PWR_WKUPFR_WKUPF6 /*!< Wakeup flag on PC1  */
+#define PWR_WAKEUP_FLAG_ALL (PWR_WKUPFR_WKUPF1 | PWR_WKUPFR_WKUPF2 |\
+                             PWR_WKUPFR_WKUPF3 | PWR_WKUPFR_WKUPF4 |\
+                             PWR_WKUPFR_WKUPF5 | PWR_WKUPFR_WKUPF6)
+/**
+  * @}
+  */
+
+#if defined (DUAL_CORE)
+/** @defgroup PWREx_Core_Select PWREx Core definition
+  * @{
+  */
+#define PWR_CORE_CPU1 (0x00000000U)
+#define PWR_CORE_CPU2 (0x00000001U)
+/**
+  * @}
+  */
+#endif /* defined (DUAL_CORE) */
+
+/** @defgroup PWREx_Domains PWREx Domains definition
+  * @{
+  */
+#define PWR_D1_DOMAIN (0x00000000U)
+#if defined (PWR_CPUCR_PDDS_D2)
+#define PWR_D2_DOMAIN (0x00000001U)
+#endif /* defined (PWR_CPUCR_PDDS_D2) */
+#define PWR_D3_DOMAIN (0x00000002U)
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_Domain_Flags PWREx Domain Flags definition
+  * @{
+  */
+#if defined (DUAL_CORE)
+#define PWR_D1_DOMAIN_FLAGS  (0x00000000U)
+#define PWR_D2_DOMAIN_FLAGS  (0x00000001U)
+#define PWR_ALL_DOMAIN_FLAGS (0x00000002U)
+#else
+#define PWR_CPU_FLAGS       (0x00000000U)
+#endif /* defined (DUAL_CORE) */
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_D3_State PWREx D3 Domain State
+  * @{
+  */
+#define PWR_D3_DOMAIN_STOP (0x00000000U)
+#define PWR_D3_DOMAIN_RUN  (0x00000800U)
+
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_Supply_configuration PWREx Supply configuration
+  * @{
+  */
+#define PWR_LDO_SUPPLY                      PWR_CR3_LDOEN                                                               /*!< Core domains are suppplied from the LDO                                                                     */
+#if defined (SMPS)
+#define PWR_DIRECT_SMPS_SUPPLY              PWR_CR3_SMPSEN                                                              /*!< Core domains are suppplied from the SMPS only                                                               */
+#define PWR_SMPS_1V8_SUPPLIES_LDO           (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN    | PWR_CR3_LDOEN)                   /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains                                       */
+#define PWR_SMPS_2V5_SUPPLIES_LDO           (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN    | PWR_CR3_LDOEN)                   /*!< The SMPS 2.5V output supplies the LDO which supplies the Core domains                                       */
+#define PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO   (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)  /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */
+#define PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO   (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)  /*!< The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */
+#define PWR_SMPS_1V8_SUPPLIES_EXT           (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 1.8V output supplies an external source which supplies the Core domains                            */
+#define PWR_SMPS_2V5_SUPPLIES_EXT           (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 2.5V output supplies an external source which supplies the Core domains                            */
+#endif /* defined (SMPS) */
+#define PWR_EXTERNAL_SOURCE_SUPPLY          PWR_CR3_BYPASS                                                              /*!< The SMPS disabled and the LDO Bypass. The Core domains are supplied from an external source                 */
+
+#if defined (SMPS)
+#define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | \
+                                PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)
+#else
+#define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)
+#endif /* defined (SMPS) */
+/**
+  * @}
+  */
+
+
+/** @defgroup PWREx_AVD_detection_level PWREx AVD detection level
+  * @{
+  */
+#define PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0 /*!< Analog voltage detector level 0
+                                             selection : 1V7                 */
+#define PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1 /*!< Analog voltage detector level 1
+                                             selection : 2V1                 */
+#define PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2 /*!< Analog voltage detector level 2
+                                             selection : 2V5                 */
+#define PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3 /*!< Analog voltage detector level 3
+                                             selection : 2V8                 */
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_AVD_Mode PWREx AVD Mode
+  * @{
+  */
+#define PWR_AVD_MODE_NORMAL               (0x00000000U)   /*!< Basic mode is used                                                 */
+#define PWR_AVD_MODE_IT_RISING            (0x00010001U)   /*!< External Interrupt Mode with Rising edge trigger detection         */
+#define PWR_AVD_MODE_IT_FALLING           (0x00010002U)   /*!< External Interrupt Mode with Falling edge trigger detection        */
+#define PWR_AVD_MODE_IT_RISING_FALLING    (0x00010003U)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define PWR_AVD_MODE_EVENT_RISING         (0x00020001U)   /*!< Event Mode with Rising edge trigger detection                      */
+#define PWR_AVD_MODE_EVENT_FALLING        (0x00020002U)   /*!< Event Mode with Falling edge trigger detection                     */
+#define PWR_AVD_MODE_EVENT_RISING_FALLING (0x00020003U)   /*!< Event Mode with Rising/Falling edge trigger detection              */
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale
+  * @{
+  */
+#define PWR_REGULATOR_SVOS_SCALE5 (PWR_CR1_SVOS_0)
+#define PWR_REGULATOR_SVOS_SCALE4 (PWR_CR1_SVOS_1)
+#define PWR_REGULATOR_SVOS_SCALE3 (PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1)
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_VBAT_Battery_Charging_Resistor PWR battery charging resistor selection
+  * @{
+  */
+#define PWR_BATTERY_CHARGING_RESISTOR_5    (0x00000000U) /*!< VBAT charging through a 5 kOhms resistor   */
+#define PWR_BATTERY_CHARGING_RESISTOR_1_5  PWR_CR3_VBRS  /*!< VBAT charging through a 1.5 kOhms resistor */
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_VBAT_Thresholds PWREx VBAT Thresholds
+  * @{
+  */
+#define PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD  (0x00000000U)
+#define PWR_VBAT_BELOW_LOW_THRESHOLD         PWR_CR2_VBATL
+#define PWR_VBAT_ABOVE_HIGH_THRESHOLD        PWR_CR2_VBATH
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_TEMP_Thresholds PWREx Temperature Thresholds
+  * @{
+  */
+#define PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD  (0x00000000U)
+#define PWR_TEMP_BELOW_LOW_THRESHOLD         PWR_CR2_TEMPL
+#define PWR_TEMP_ABOVE_HIGH_THRESHOLD        PWR_CR2_TEMPH
+/**
+  * @}
+  */
+/** @defgroup PWREx_AVD_EXTI_Line PWREx AVD EXTI Line 16
+  * @{
+  */
+#define PWR_EXTI_LINE_AVD EXTI_IMR1_IM16 /*!< External interrupt line 16
+                                              Connected to the AVD EXTI Line */
+/**
+  * @}
+  */
+
+#if defined (PWR_CR1_SRDRAMSO)
+/** @defgroup PWREx_Memory_Shut_Off Memory shut-off block selection
+  * @{
+  */
+#define PWR_SRD_AHB_MEMORY_BLOCK        PWR_CR1_SRDRAMSO    /*!< SmartRun domain AHB memory shut-off in DStop/DStop2 low-power mode         */
+#define PWR_USB_FDCAN_MEMORY_BLOCK      PWR_CR1_HSITFSO     /*!< High-speed interfaces USB and FDCAN memories shut-off in DStop/DStop2 mode */
+#define PWR_GFXMMU_JPEG_MEMORY_BLOCK    PWR_CR1_GFXSO       /*!< GFXMMU and JPEG memories shut-off in DStop/DStop2 mode                     */
+#define PWR_TCM_ECM_MEMORY_BLOCK        PWR_CR1_ITCMSO      /*!< Instruction TCM and ETM memories shut-off in DStop/DStop2 mode             */
+#define PWR_RAM1_AHB_MEMORY_BLOCK       PWR_CR1_AHBRAM1SO   /*!< AHB RAM1 shut-off in DStop/DStop2 mode                                     */
+#define PWR_RAM2_AHB_MEMORY_BLOCK       PWR_CR1_AHBRAM2SO   /*!< AHB RAM2 shut-off in DStop/DStop2 mode                                     */
+#define PWR_RAM1_AXI_MEMORY_BLOCK       PWR_CR1_AXIRAM1SO   /*!< AXI RAM1 shut-off in DStop/DStop2 mode                                     */
+#define PWR_RAM2_AXI_MEMORY_BLOCK       PWR_CR1_AXIRAM2SO   /*!< AXI RAM2 shut-off in DStop/DStop2 mode                                     */
+#define PWR_RAM3_AXI_MEMORY_BLOCK       PWR_CR1_AXIRAM3SO   /*!< AXI RAM3 shut-off in DStop/DStop2 mode                                     */
+#define PWR_MEMORY_BLOCK_KEEP_ON        0U                  /*!< Memory content is kept in DStop or DStop2 mode                             */
+#define PWR_MEMORY_BLOCK_SHUT_OFF       1U                  /*!< Memory content is lost in DStop or DStop2 mode                             */
+/**
+  * @}
+  */
+#endif /* defined (PWR_CR1_SRDRAMSO) */
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup PWREx_Exported_Macro PWREx Exported Macro
+  *  @{
+  */
+
+/**
+  * @brief Enable the AVD EXTI Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Enable the AVD EXTI D2 Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief Disable the AVD EXTI Line 16
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Disable the AVD EXTI D2 Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief Enable event on AVD EXTI Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Enable event on AVD EXTI D2 Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief Disable event on AVD EXTI Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Disable event on AVD EXTI D2 Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief Enable the AVD Extended Interrupt Rising Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)
+
+/**
+  * @brief Disable the AVD Extended Interrupt Rising Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)
+
+/**
+  * @brief Enable the AVD Extended Interrupt Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)
+
+/**
+  * @brief Disable the AVD Extended Interrupt Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)
+
+/**
+  * @brief Enable the AVD Extended Interrupt Rising and Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
+do {                                                    \
+     __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE();           \
+     __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE();          \
+} while(0);
+
+/**
+  * @brief Disable the AVD Extended Interrupt Rising & Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
+do {                                                     \
+     __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE();           \
+     __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE();          \
+} while(0);
+
+/**
+  * @brief Check whether the specified AVD EXTI interrupt flag is set or not.
+  * @retval EXTI AVD Line Status.
+  */
+#define __HAL_PWR_AVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? 1UL : 0UL)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Check whether the specified AVD EXTI D2 interrupt flag is set or not.
+  * @retval EXTI D2 AVD Line Status.
+  */
+#define __HAL_PWR_AVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? 1UL : 0UL)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief  Clear the AVD EXTI flag.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD)
+
+#if defined (DUAL_CORE)
+/**
+  * @brief  Clear the AVD EXTI D2 flag.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD)
+#endif /* defined (DUAL_CORE) */
+
+/**
+  * @brief  Generates a Software interrupt on AVD EXTI line.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_AVD)
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions
+  * @{
+  */
+
+/** @addtogroup PWREx_Exported_Functions_Group1 Power Supply Control Functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource);
+uint32_t HAL_PWREx_GetSupplyConfig(void);
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
+uint32_t HAL_PWREx_GetVoltageRange(void);
+HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling(uint32_t VoltageScaling);
+uint32_t HAL_PWREx_GetStopModeVoltageRange(void);
+/**
+  * @}
+  */
+
+/** @addtogroup PWREx_Exported_Functions_Group2 Low Power Control Functions
+  * @{
+  */
+/* System low power control functions */
+#if defined (PWR_CPUCR_RETDS_CD)
+void HAL_PWREx_EnterSTOP2Mode(uint32_t Regulator, uint8_t STOPEntry);
+#endif /* defined (PWR_CPUCR_RETDS_CD) */
+void HAL_PWREx_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain);
+void HAL_PWREx_EnterSTANDBYMode(uint32_t Domain);
+void HAL_PWREx_ConfigD3Domain(uint32_t D3State);
+/* Clear Cortex-Mx pending flag */
+void HAL_PWREx_ClearPendingEvent(void);
+#if defined (DUAL_CORE)
+/* Clear domain flags */
+void HAL_PWREx_ClearDomainFlags(uint32_t DomainFlags);
+/* Core Hold/Release functions */
+HAL_StatusTypeDef HAL_PWREx_HoldCore(uint32_t CPU);
+void HAL_PWREx_ReleaseCore(uint32_t CPU);
+#endif /* defined (DUAL_CORE) */
+/* Flash low power control functions */
+void HAL_PWREx_EnableFlashPowerDown(void);
+void HAL_PWREx_DisableFlashPowerDown(void);
+#if defined (PWR_CR1_SRDRAMSO)
+/* Memory shut-off functions */
+void HAL_PWREx_EnableMemoryShutOff(uint32_t MemoryBlock);
+void HAL_PWREx_DisableMemoryShutOff(uint32_t MemoryBlock);
+#endif /* defined(PWR_CR1_SRDRAMSO) */
+/* Wakeup Pins control functions */
+void HAL_PWREx_EnableWakeUpPin(PWREx_WakeupPinTypeDef *sPinParams);
+void HAL_PWREx_DisableWakeUpPin(uint32_t WakeUpPin);
+uint32_t HAL_PWREx_GetWakeupFlag(uint32_t WakeUpFlag);
+HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag(uint32_t WakeUpFlag);
+/* Power Wakeup PIN IRQ Handler */
+void HAL_PWREx_WAKEUP_PIN_IRQHandler(void);
+void HAL_PWREx_WKUP1_Callback(void);
+void HAL_PWREx_WKUP2_Callback(void);
+void HAL_PWREx_WKUP3_Callback(void);
+void HAL_PWREx_WKUP4_Callback(void);
+void HAL_PWREx_WKUP5_Callback(void);
+void HAL_PWREx_WKUP6_Callback(void);
+/**
+  * @}
+  */
+
+/** @addtogroup PWREx_Exported_Functions_Group3 Peripherals Control Functions
+  * @{
+  */
+/* Backup regulator control functions */
+HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);
+HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void);
+/* USB regulator control functions */
+HAL_StatusTypeDef HAL_PWREx_EnableUSBReg(void);
+HAL_StatusTypeDef HAL_PWREx_DisableUSBReg(void);
+void HAL_PWREx_EnableUSBVoltageDetector(void);
+void HAL_PWREx_DisableUSBVoltageDetector(void);
+/* Battery control functions */
+void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorValue);
+void HAL_PWREx_DisableBatteryCharging(void);
+#if defined(PWR_CR1_BOOSTE)
+/* Analog Booster functions */
+void HAL_PWREx_EnableAnalogBooster(void);
+void HAL_PWREx_DisableAnalogBooster(void);
+#endif /* PWR_CR1_BOOSTE */
+/**
+  * @}
+  */
+
+/** @addtogroup PWREx_Exported_Functions_Group4 Power Monitoring functions
+  * @{
+  */
+/* Power VBAT/Temperature monitoring functions */
+void HAL_PWREx_EnableMonitoring(void);
+void HAL_PWREx_DisableMonitoring(void);
+uint32_t HAL_PWREx_GetTemperatureLevel(void);
+uint32_t HAL_PWREx_GetVBATLevel(void);
+#if defined(PWR_CSR1_MMCVDO)
+PWREx_MMC_VoltageLevel HAL_PWREx_GetMMCVoltage(void);
+#endif /* PWR_CSR1_MMCVDO */
+/* Power AVD configuration functions */
+void HAL_PWREx_ConfigAVD(PWREx_AVDTypeDef *sConfigAVD);
+void HAL_PWREx_EnableAVD(void);
+void HAL_PWREx_DisableAVD(void);
+/* Power PVD/AVD IRQ Handler */
+void HAL_PWREx_PVD_AVD_IRQHandler(void);
+void HAL_PWREx_AVDCallback(void);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PWREx_Private_Macros PWREx Private Macros
+  * @{
+  */
+
+/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters
+  * @{
+  */
+/* Check PWR regulator configuration parameter */
+#if defined (SMPS)
+#define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY)                    ||\
+                                   ((PWR_SOURCE) == PWR_DIRECT_SMPS_SUPPLY)            ||\
+                                   ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_LDO)         ||\
+                                   ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_LDO)         ||\
+                                   ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) ||\
+                                   ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) ||\
+                                   ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT)         ||\
+                                   ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT)         ||\
+                                   ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY))
+
+#else
+#define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) ||\
+                                   ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY))
+#endif /* defined (SMPS) */
+
+/* Check PWR regulator configuration in STOP mode parameter */
+#define IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE3)  ||\
+                                                     ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE4)  ||\
+                                                     ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE5))
+
+/* Check PWR domain parameter */
+#if defined (PWR_CPUCR_PDDS_D2)
+#define IS_PWR_DOMAIN(DOMAIN) (((DOMAIN) == PWR_D1_DOMAIN) ||\
+                               ((DOMAIN) == PWR_D2_DOMAIN) ||\
+                               ((DOMAIN) == PWR_D3_DOMAIN))
+#else
+#define IS_PWR_DOMAIN(DOMAIN) (((DOMAIN) == PWR_D1_DOMAIN) ||\
+                               ((DOMAIN) == PWR_D3_DOMAIN))
+#endif /* defined (PWR_CPUCR_PDDS_D2) */
+
+/* Check D3/SRD domain state parameter */
+#define IS_D3_STATE(STATE) (((STATE) == PWR_D3_DOMAIN_STOP) ||\
+                            ((STATE) == PWR_D3_DOMAIN_RUN))
+
+/* Check wake up pin parameter */
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1)      ||\
+                                ((PIN) == PWR_WAKEUP_PIN2)      ||\
+                                ((PIN) == PWR_WAKEUP_PIN3)      ||\
+                                ((PIN) == PWR_WAKEUP_PIN4)      ||\
+                                ((PIN) == PWR_WAKEUP_PIN5)      ||\
+                                ((PIN) == PWR_WAKEUP_PIN6)      ||\
+                                ((PIN) == PWR_WAKEUP_PIN1_HIGH) ||\
+                                ((PIN) == PWR_WAKEUP_PIN2_HIGH) ||\
+                                ((PIN) == PWR_WAKEUP_PIN3_HIGH) ||\
+                                ((PIN) == PWR_WAKEUP_PIN4_HIGH) ||\
+                                ((PIN) == PWR_WAKEUP_PIN5_HIGH) ||\
+                                ((PIN) == PWR_WAKEUP_PIN6_HIGH) ||\
+                                ((PIN) == PWR_WAKEUP_PIN1_LOW)  ||\
+                                ((PIN) == PWR_WAKEUP_PIN2_LOW)  ||\
+                                ((PIN) == PWR_WAKEUP_PIN3_LOW)  ||\
+                                ((PIN) == PWR_WAKEUP_PIN4_LOW)  ||\
+                                ((PIN) == PWR_WAKEUP_PIN5_LOW)  ||\
+                                ((PIN) == PWR_WAKEUP_PIN6_LOW))
+
+/* Check wake up pin polarity parameter */
+#define IS_PWR_WAKEUP_PIN_POLARITY(POLARITY) (((POLARITY) == PWR_PIN_POLARITY_HIGH) ||\
+                                              ((POLARITY) == PWR_PIN_POLARITY_LOW))
+
+/* Check wake up pin pull configuration parameter */
+#define IS_PWR_WAKEUP_PIN_PULL(PULL) (((PULL) == PWR_PIN_NO_PULL) ||\
+                                      ((PULL) == PWR_PIN_PULL_UP) ||\
+                                      ((PULL) == PWR_PIN_PULL_DOWN))
+
+/* Check wake up flag parameter */
+#define IS_PWR_WAKEUP_FLAG(FLAG) (((FLAG) == PWR_WAKEUP_FLAG1) ||\
+                                  ((FLAG) == PWR_WAKEUP_FLAG2) ||\
+                                  ((FLAG) == PWR_WAKEUP_FLAG3) ||\
+                                  ((FLAG) == PWR_WAKEUP_FLAG4) ||\
+                                  ((FLAG) == PWR_WAKEUP_FLAG5) ||\
+                                  ((FLAG) == PWR_WAKEUP_FLAG6) ||\
+                                  ((FLAG) == PWR_WAKEUP_FLAG_ALL))
+
+/* Check wake up flag parameter */
+#define IS_PWR_AVD_LEVEL(LEVEL) (((LEVEL) == PWR_AVDLEVEL_0) ||\
+                                 ((LEVEL) == PWR_AVDLEVEL_1) ||\
+                                 ((LEVEL) == PWR_AVDLEVEL_2) ||\
+                                 ((LEVEL) == PWR_AVDLEVEL_3))
+
+/* Check AVD mode parameter */
+#define IS_PWR_AVD_MODE(MODE) (((MODE) == PWR_AVD_MODE_IT_RISING)         ||\
+                               ((MODE) == PWR_AVD_MODE_IT_FALLING)        ||\
+                               ((MODE) == PWR_AVD_MODE_IT_RISING_FALLING) ||\
+                               ((MODE) == PWR_AVD_MODE_EVENT_RISING)      ||\
+                               ((MODE) == PWR_AVD_MODE_EVENT_FALLING)     ||\
+                               ((MODE) == PWR_AVD_MODE_NORMAL)            ||\
+                               ((MODE) == PWR_AVD_MODE_EVENT_RISING_FALLING))
+
+/* Check resistor battery parameter */
+#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
+                                                  ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
+/* Check D1/CD CPU ID parameter */
+#define IS_PWR_D1_CPU(CPU) ((CPU) == CM7_CPUID)
+
+#if defined (DUAL_CORE)
+/* Check CPU parameter */
+#define IS_PWR_CORE(CPU)  (((CPU) == PWR_CORE_CPU1) || ((CPU) == PWR_CORE_CPU2))
+
+/* Check D2 CPU ID parameter */
+#define IS_PWR_D2_CPU(CPU) ((CPU) == CM4_CPUID)
+
+/* Check PWR domain flag parameter */
+#define IS_PWR_DOMAIN_FLAG(FLAG)  (((FLAG) == PWR_D1_DOMAIN_FLAGS) || \
+                                   ((FLAG) == PWR_D2_DOMAIN_FLAGS) || \
+                                   ((FLAG) == PWR_ALL_DOMAIN_FLAGS))
+#endif /* defined (DUAL_CORE) */
+
+#if defined (PWR_CR1_SRDRAMSO)
+/* Check memory block parameter */
+#define IS_PWR_MEMORY_BLOCK(BLOCK) (((BLOCK) == PWR_SRD_AHB_MEMORY_BLOCK)     || \
+                                    ((BLOCK) == PWR_USB_FDCAN_MEMORY_BLOCK)   || \
+                                    ((BLOCK) == PWR_GFXMMU_JPEG_MEMORY_BLOCK) || \
+                                    ((BLOCK) == PWR_TCM_ECM_MEMORY_BLOCK)     || \
+                                    ((BLOCK) == PWR_RAM1_AHB_MEMORY_BLOCK)    || \
+                                    ((BLOCK) == PWR_RAM2_AHB_MEMORY_BLOCK)    || \
+                                    ((BLOCK) == PWR_RAM1_AXI_MEMORY_BLOCK)    || \
+                                    ((BLOCK) == PWR_RAM2_AXI_MEMORY_BLOCK)    || \
+                                    ((BLOCK) == PWR_RAM3_AXI_MEMORY_BLOCK))
+#endif /* defined (PWR_CR1_SRDRAMSO) */
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* STM32H7xx_HAL_PWR_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h
new file mode 100644
index 00000000..ceb86440
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h
@@ -0,0 +1,7973 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_rcc.h
+  * @author  MCD Application Team
+  * @brief   Header file of RCC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_RCC_H
+#define STM32H7xx_HAL_RCC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup RCC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Types RCC Exported Types
+  * @{
+  */
+
+/**
+  * @brief  RCC PLL configuration structure definition
+  */
+typedef struct
+{
+  uint32_t PLLState;   /*!< The new state of the PLL.
+                            This parameter can be a value of @ref RCC_PLL_Config                      */
+
+  uint32_t PLLSource;  /*!< RCC_PLLSource: PLL entry clock source.
+                            This parameter must be a value of @ref RCC_PLL_Clock_Source               */
+
+  uint32_t PLLM;       /*!< PLLM: Division factor for PLL VCO input clock.
+                            This parameter must be a number between Min_Data = 1 and Max_Data = 63    */
+
+  uint32_t PLLN;       /*!< PLLN: Multiplication factor for PLL VCO output clock.
+                            This parameter must be a number between Min_Data = 4 and Max_Data = 512 
+                            or between Min_Data = 8 and Max_Data = 420(*)
+                            (*) : For stm32h7a3xx and stm32h7b3xx family lines.                       */                        
+
+  uint32_t PLLP;       /*!< PLLP: Division factor for system clock.
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 128
+                          odd division factors are not allowed                                        */
+
+  uint32_t PLLQ;       /*!< PLLQ: Division factor for peripheral clocks.
+                            This parameter must be a number between Min_Data = 1 and Max_Data = 128   */
+
+  uint32_t PLLR;       /*!< PLLR: Division factor for peripheral clocks.
+                            This parameter must be a number between Min_Data = 1 and Max_Data = 128   */
+  uint32_t PLLRGE;     /*!<PLLRGE: PLL1 clock Input range
+                         This parameter must be a value of @ref RCC_PLL1_VCI_Range                    */
+  uint32_t PLLVCOSEL;  /*!<PLLVCOSEL: PLL1 clock Output range
+                         This parameter must be a value of @ref RCC_PLL1_VCO_Range                    */
+
+  uint32_t PLLFRACN;   /*!<PLLFRACN: Specifies Fractional Part Of The Multiplication Factor for
+                        PLL1 VCO It should be a value between 0 and 8191                              */
+
+}RCC_PLLInitTypeDef;
+
+/**
+  * @brief  RCC Internal/External Oscillator (HSE, HSI, CSI, LSE and LSI) configuration structure definition
+  */
+typedef struct
+{
+  uint32_t OscillatorType;       /*!< The oscillators to be configured.
+                                      This parameter can be a value of @ref RCC_Oscillator_Type                   */
+
+  uint32_t HSEState;             /*!< The new state of the HSE.
+                                      This parameter can be a value of @ref RCC_HSE_Config                        */
+
+  uint32_t LSEState;             /*!< The new state of the LSE.
+                                      This parameter can be a value of @ref RCC_LSE_Config                        */
+
+  uint32_t HSIState;             /*!< The new state of the HSI.
+                                      This parameter can be a value of @ref RCC_HSI_Config                        */
+
+  uint32_t HSICalibrationValue;  /*!< The calibration trimming value.
+                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F for STM32H7 rev.Y
+                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F for STM32H7 rev.B and above */
+
+  uint32_t LSIState;             /*!< The new state of the LSI.
+                                      This parameter can be a value of @ref RCC_LSI_Config                        */
+
+ uint32_t HSI48State;            /*!< The new state of the HSI48.
+                                      This parameter can be a value of @ref RCC_HSI48_Config                      */
+
+  uint32_t CSIState;             /*!< The new state of the CSI.
+                                      This parameter can be a value of @ref RCC_CSI_Config */
+
+  uint32_t CSICalibrationValue;  /*!< The calibration trimming value.
+                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F for STM32H7 rev.Y
+                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F for STM32H7 rev.B and above */
+
+  RCC_PLLInitTypeDef PLL;        /*!< PLL structure parameters                                                    */
+
+}RCC_OscInitTypeDef;
+
+/**
+  * @brief  RCC System, AHB and APB busses clock configuration structure definition
+  */
+typedef struct
+{
+  uint32_t ClockType;             /*!< The clock to be configured.
+                                       This parameter can be a value of @ref RCC_System_Clock_Type                          */
+
+  uint32_t SYSCLKSource;          /*!< The clock source (SYSCLKS) used as system clock.
+                                       This parameter can be a value of @ref RCC_System_Clock_Source                        */
+
+  uint32_t SYSCLKDivider;         /*!< The system clock  divider. This parameter can be
+                                       a value of @ref RCC_SYS_Clock_Source                                                 */
+
+  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
+                                       This parameter can be a value of @ref RCC_HCLK_Clock_Source                          */
+
+  uint32_t APB3CLKDivider;        /*!< The APB3 clock (D1PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_APB3_Clock_Source                        */
+
+  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_APB1_Clock_Source                        */
+  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_APB2_Clock_Source                        */
+  uint32_t APB4CLKDivider;      /*!< The APB4 clock (D3PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_APB4_Clock_Source                        */
+}RCC_ClkInitTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Constants RCC Exported Constants
+  * @{
+  */
+
+/** @defgroup RCC_Oscillator_Type  RCC Oscillator Type
+  * @{
+  */
+#define RCC_OSCILLATORTYPE_NONE        (0x00000000U)
+#define RCC_OSCILLATORTYPE_HSE         (0x00000001U)
+#define RCC_OSCILLATORTYPE_HSI         (0x00000002U)
+#define RCC_OSCILLATORTYPE_LSE         (0x00000004U)
+#define RCC_OSCILLATORTYPE_LSI         (0x00000008U)
+#define RCC_OSCILLATORTYPE_CSI         (0x00000010U)
+#define RCC_OSCILLATORTYPE_HSI48       (0x00000020U)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_HSE_Config  RCC HSE Config
+  * @{
+  */
+#define RCC_HSE_OFF                    (0x00000000U)
+#define RCC_HSE_ON                     RCC_CR_HSEON
+#define RCC_HSE_BYPASS                 ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
+#if defined(RCC_CR_HSEEXT)
+#define RCC_HSE_BYPASS_DIGITAL         ((uint32_t)(RCC_CR_HSEEXT | RCC_CR_HSEBYP | RCC_CR_HSEON))
+#endif /* RCC_CR_HSEEXT */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LSE_Config  RCC LSE Config
+  * @{
+  */
+#define RCC_LSE_OFF                    (0x00000000U)
+#define RCC_LSE_ON                     RCC_BDCR_LSEON
+#define RCC_LSE_BYPASS                 ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
+#if defined(RCC_BDCR_LSEEXT)
+#define RCC_LSE_BYPASS_DIGITAL         ((uint32_t)(RCC_BDCR_LSEEXT | RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
+#endif /* RCC_BDCR_LSEEXT */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_HSI_Config  RCC HSI Config
+  * @{
+  */
+#define RCC_HSI_OFF                      (0x00000000U)           /*!< HSI clock deactivation */
+#define RCC_HSI_ON                       RCC_CR_HSION                     /*!< HSI clock activation */
+
+#define RCC_HSI_DIV1                     (RCC_CR_HSIDIV_1 | RCC_CR_HSION) /*!< HSI_DIV1 clock activation */
+#define RCC_HSI_DIV2                     (RCC_CR_HSIDIV_2 | RCC_CR_HSION) /*!< HSI_DIV2 clock activation */
+#define RCC_HSI_DIV4                     (RCC_CR_HSIDIV_4 | RCC_CR_HSION) /*!< HSI_DIV4 clock activation */
+#define RCC_HSI_DIV8                     (RCC_CR_HSIDIV | RCC_CR_HSION)   /*!< HSI_DIV8 clock activation */
+
+
+#if defined(RCC_HSICFGR_HSITRIM_6)
+#define RCC_HSICALIBRATION_DEFAULT     (0x40U)         /* Default HSI calibration trimming value, for STM32H7 rev.V and above  */
+#else
+#define RCC_HSICALIBRATION_DEFAULT     (0x20U)         /* Default HSI calibration trimming value, for STM32H7 rev.Y */
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup RCC_HSI48_Config  RCC HSI48 Config
+  * @{
+  */
+#define RCC_HSI48_OFF                      ((uint8_t)0x00)
+#define RCC_HSI48_ON                       ((uint8_t)0x01)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LSI_Config  RCC LSI Config
+  * @{
+  */
+#define RCC_LSI_OFF                    (0x00000000U)
+#define RCC_LSI_ON                     RCC_CSR_LSION
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_CSI_Config  RCC CSI Config
+  * @{
+  */
+#define RCC_CSI_OFF                    (0x00000000U)
+#define RCC_CSI_ON                     RCC_CR_CSION
+
+#if defined(RCC_CSICFGR_CSITRIM_5)
+#define RCC_CSICALIBRATION_DEFAULT     (0x20U)         /* Default CSI calibration trimming value */
+#else
+#define RCC_CSICALIBRATION_DEFAULT     (0x10U)         /* Default CSI calibration trimming value */
+#endif /* RCC_CSICFGR_CSITRIM_5 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLL_Config  RCC PLL Config
+  * @{
+  */
+#define RCC_PLL_NONE                   (0x00000000U)
+#define RCC_PLL_OFF                    (0x00000001U)
+#define RCC_PLL_ON                     (0x00000002U)
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_PLL_Clock_Source  RCC PLL Clock Source
+  * @{
+  */
+#define RCC_PLLSOURCE_HSI              (0x00000000U)
+#define RCC_PLLSOURCE_CSI              (0x00000001U)
+#define RCC_PLLSOURCE_HSE              (0x00000002U)
+#define RCC_PLLSOURCE_NONE             (0x00000003U)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLL_Clock_Output  RCC PLL Clock Output
+  * @{
+  */
+#define RCC_PLL1_DIVP                RCC_PLLCFGR_DIVP1EN
+#define RCC_PLL1_DIVQ                RCC_PLLCFGR_DIVQ1EN
+#define RCC_PLL1_DIVR                RCC_PLLCFGR_DIVR1EN
+
+/**
+  * @}
+  */
+
+
+
+/** @defgroup RCC_PLL1_VCI_Range  RCC PLL1 VCI Range
+  * @{
+  */
+#define RCC_PLL1VCIRANGE_0                RCC_PLLCFGR_PLL1RGE_0       /*!< Clock range frequency between 1 and 2 MHz  */
+#define RCC_PLL1VCIRANGE_1                RCC_PLLCFGR_PLL1RGE_1       /*!< Clock range frequency between 2 and 4 MHz  */
+#define RCC_PLL1VCIRANGE_2                RCC_PLLCFGR_PLL1RGE_2       /*!< Clock range frequency between 4 and 8 MHz  */
+#define RCC_PLL1VCIRANGE_3                RCC_PLLCFGR_PLL1RGE_3       /*!< Clock range frequency between 8 and 16 MHz */
+
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_PLL1_VCO_Range  RCC PLL1 VCO Range
+  * @{
+  */
+#define RCC_PLL1VCOWIDE                 (0x00000000U)
+#define RCC_PLL1VCOMEDIUM               RCC_PLLCFGR_PLL1VCOSEL
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_System_Clock_Type  RCC System Clock Type
+  * @{
+  */
+#define RCC_CLOCKTYPE_SYSCLK           (0x00000001U)
+#define RCC_CLOCKTYPE_HCLK             (0x00000002U)
+#define RCC_CLOCKTYPE_D1PCLK1          (0x00000004U)
+#define RCC_CLOCKTYPE_PCLK1            (0x00000008U)
+#define RCC_CLOCKTYPE_PCLK2            (0x00000010U)
+#define RCC_CLOCKTYPE_D3PCLK1          (0x00000020U)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_System_Clock_Source  RCC System Clock Source
+  * @{
+  */
+#define RCC_SYSCLKSOURCE_CSI           RCC_CFGR_SW_CSI
+#define RCC_SYSCLKSOURCE_HSI           RCC_CFGR_SW_HSI
+#define RCC_SYSCLKSOURCE_HSE           RCC_CFGR_SW_HSE
+#define RCC_SYSCLKSOURCE_PLLCLK        RCC_CFGR_SW_PLL1
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
+  * @{
+  */
+#define RCC_SYSCLKSOURCE_STATUS_CSI    RCC_CFGR_SWS_CSI   /*!< CSI used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL1  /*!< PLL1 used as system clock */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_SYS_Clock_Source  RCC SYS Clock Source
+  * @{
+  */
+#if defined(RCC_D1CFGR_D1CPRE_DIV1)
+#define RCC_SYSCLK_DIV1                RCC_D1CFGR_D1CPRE_DIV1
+#define RCC_SYSCLK_DIV2                RCC_D1CFGR_D1CPRE_DIV2
+#define RCC_SYSCLK_DIV4                RCC_D1CFGR_D1CPRE_DIV4
+#define RCC_SYSCLK_DIV8                RCC_D1CFGR_D1CPRE_DIV8
+#define RCC_SYSCLK_DIV16               RCC_D1CFGR_D1CPRE_DIV16
+#define RCC_SYSCLK_DIV64               RCC_D1CFGR_D1CPRE_DIV64
+#define RCC_SYSCLK_DIV128              RCC_D1CFGR_D1CPRE_DIV128
+#define RCC_SYSCLK_DIV256              RCC_D1CFGR_D1CPRE_DIV256
+#define RCC_SYSCLK_DIV512              RCC_D1CFGR_D1CPRE_DIV512
+#else
+#define RCC_SYSCLK_DIV1                RCC_CDCFGR1_CDCPRE_DIV1
+#define RCC_SYSCLK_DIV2                RCC_CDCFGR1_CDCPRE_DIV2
+#define RCC_SYSCLK_DIV4                RCC_CDCFGR1_CDCPRE_DIV4
+#define RCC_SYSCLK_DIV8                RCC_CDCFGR1_CDCPRE_DIV8
+#define RCC_SYSCLK_DIV16               RCC_CDCFGR1_CDCPRE_DIV16
+#define RCC_SYSCLK_DIV64               RCC_CDCFGR1_CDCPRE_DIV64
+#define RCC_SYSCLK_DIV128              RCC_CDCFGR1_CDCPRE_DIV128
+#define RCC_SYSCLK_DIV256              RCC_CDCFGR1_CDCPRE_DIV256
+#define RCC_SYSCLK_DIV512              RCC_CDCFGR1_CDCPRE_DIV512
+#endif
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_HCLK_Clock_Source  RCC HCLK Clock Source
+  * @{
+  */
+#if defined(RCC_D1CFGR_HPRE_DIV1)
+#define RCC_HCLK_DIV1                RCC_D1CFGR_HPRE_DIV1
+#define RCC_HCLK_DIV2                RCC_D1CFGR_HPRE_DIV2
+#define RCC_HCLK_DIV4                RCC_D1CFGR_HPRE_DIV4
+#define RCC_HCLK_DIV8                RCC_D1CFGR_HPRE_DIV8
+#define RCC_HCLK_DIV16               RCC_D1CFGR_HPRE_DIV16
+#define RCC_HCLK_DIV64               RCC_D1CFGR_HPRE_DIV64
+#define RCC_HCLK_DIV128              RCC_D1CFGR_HPRE_DIV128
+#define RCC_HCLK_DIV256              RCC_D1CFGR_HPRE_DIV256
+#define RCC_HCLK_DIV512              RCC_D1CFGR_HPRE_DIV512
+#else
+#define RCC_HCLK_DIV1                RCC_CDCFGR1_HPRE_DIV1
+#define RCC_HCLK_DIV2                RCC_CDCFGR1_HPRE_DIV2
+#define RCC_HCLK_DIV4                RCC_CDCFGR1_HPRE_DIV4
+#define RCC_HCLK_DIV8                RCC_CDCFGR1_HPRE_DIV8
+#define RCC_HCLK_DIV16               RCC_CDCFGR1_HPRE_DIV16
+#define RCC_HCLK_DIV64               RCC_CDCFGR1_HPRE_DIV64
+#define RCC_HCLK_DIV128              RCC_CDCFGR1_HPRE_DIV128
+#define RCC_HCLK_DIV256              RCC_CDCFGR1_HPRE_DIV256
+#define RCC_HCLK_DIV512              RCC_CDCFGR1_HPRE_DIV512
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB3_Clock_Source  RCC APB3 Clock Source
+  * @{
+  */
+#if defined (RCC_D1CFGR_D1PPRE_DIV1)
+#define RCC_APB3_DIV1                  RCC_D1CFGR_D1PPRE_DIV1
+#define RCC_APB3_DIV2                  RCC_D1CFGR_D1PPRE_DIV2
+#define RCC_APB3_DIV4                  RCC_D1CFGR_D1PPRE_DIV4
+#define RCC_APB3_DIV8                  RCC_D1CFGR_D1PPRE_DIV8
+#define RCC_APB3_DIV16                 RCC_D1CFGR_D1PPRE_DIV16
+#else
+#define RCC_APB3_DIV1                  RCC_CDCFGR1_CDPPRE_DIV1
+#define RCC_APB3_DIV2                  RCC_CDCFGR1_CDPPRE_DIV2
+#define RCC_APB3_DIV4                  RCC_CDCFGR1_CDPPRE_DIV4
+#define RCC_APB3_DIV8                  RCC_CDCFGR1_CDPPRE_DIV8
+#define RCC_APB3_DIV16                 RCC_CDCFGR1_CDPPRE_DIV16
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB1_Clock_Source  RCC APB1 Clock Source
+  * @{
+  */
+#if defined (RCC_D2CFGR_D2PPRE1_DIV1)
+#define RCC_APB1_DIV1                  RCC_D2CFGR_D2PPRE1_DIV1
+#define RCC_APB1_DIV2                  RCC_D2CFGR_D2PPRE1_DIV2
+#define RCC_APB1_DIV4                  RCC_D2CFGR_D2PPRE1_DIV4
+#define RCC_APB1_DIV8                  RCC_D2CFGR_D2PPRE1_DIV8
+#define RCC_APB1_DIV16                 RCC_D2CFGR_D2PPRE1_DIV16
+#else
+#define RCC_APB1_DIV1                  RCC_CDCFGR2_CDPPRE1_DIV1
+#define RCC_APB1_DIV2                  RCC_CDCFGR2_CDPPRE1_DIV2
+#define RCC_APB1_DIV4                  RCC_CDCFGR2_CDPPRE1_DIV4
+#define RCC_APB1_DIV8                  RCC_CDCFGR2_CDPPRE1_DIV8
+#define RCC_APB1_DIV16                 RCC_CDCFGR2_CDPPRE1_DIV16
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB2_Clock_Source  RCC APB2 Clock Source
+  * @{
+  */
+#if defined (RCC_D2CFGR_D2PPRE2_DIV1)
+#define RCC_APB2_DIV1                  RCC_D2CFGR_D2PPRE2_DIV1
+#define RCC_APB2_DIV2                  RCC_D2CFGR_D2PPRE2_DIV2
+#define RCC_APB2_DIV4                  RCC_D2CFGR_D2PPRE2_DIV4
+#define RCC_APB2_DIV8                  RCC_D2CFGR_D2PPRE2_DIV8
+#define RCC_APB2_DIV16                 RCC_D2CFGR_D2PPRE2_DIV16
+#else
+#define RCC_APB2_DIV1                  RCC_CDCFGR2_CDPPRE2_DIV1
+#define RCC_APB2_DIV2                  RCC_CDCFGR2_CDPPRE2_DIV2
+#define RCC_APB2_DIV4                  RCC_CDCFGR2_CDPPRE2_DIV4
+#define RCC_APB2_DIV8                  RCC_CDCFGR2_CDPPRE2_DIV8
+#define RCC_APB2_DIV16                 RCC_CDCFGR2_CDPPRE2_DIV16
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB4_Clock_Source  RCC APB4 Clock Source
+  * @{
+  */
+#if defined(RCC_D3CFGR_D3PPRE_DIV1)
+#define RCC_APB4_DIV1                  RCC_D3CFGR_D3PPRE_DIV1
+#define RCC_APB4_DIV2                  RCC_D3CFGR_D3PPRE_DIV2
+#define RCC_APB4_DIV4                  RCC_D3CFGR_D3PPRE_DIV4
+#define RCC_APB4_DIV8                  RCC_D3CFGR_D3PPRE_DIV8
+#define RCC_APB4_DIV16                 RCC_D3CFGR_D3PPRE_DIV16
+#else
+#define RCC_APB4_DIV1                  RCC_SRDCFGR_SRDPPRE_DIV1
+#define RCC_APB4_DIV2                  RCC_SRDCFGR_SRDPPRE_DIV2
+#define RCC_APB4_DIV4                  RCC_SRDCFGR_SRDPPRE_DIV4
+#define RCC_APB4_DIV8                  RCC_SRDCFGR_SRDPPRE_DIV8
+#define RCC_APB4_DIV16                 RCC_SRDCFGR_SRDPPRE_DIV16
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup RCC_RTC_Clock_Source  RCC RTC Clock Source
+  * @{
+  */
+#define RCC_RTCCLKSOURCE_NO_CLK          (0x00000000U)
+#define RCC_RTCCLKSOURCE_LSE             (0x00000100U)
+#define RCC_RTCCLKSOURCE_LSI             (0x00000200U)
+#define RCC_RTCCLKSOURCE_HSE_DIV2        (0x00002300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV3        (0x00003300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV4        (0x00004300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV5        (0x00005300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV6        (0x00006300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV7        (0x00007300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV8        (0x00008300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV9        (0x00009300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV10       (0x0000A300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV11       (0x0000B300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV12       (0x0000C300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV13       (0x0000D300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV14       (0x0000E300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV15       (0x0000F300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV16       (0x00010300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV17       (0x00011300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV18       (0x00012300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV19       (0x00013300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV20       (0x00014300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV21       (0x00015300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV22       (0x00016300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV23       (0x00017300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV24       (0x00018300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV25       (0x00019300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV26       (0x0001A300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV27       (0x0001B300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV28       (0x0001C300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV29       (0x0001D300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV30       (0x0001E300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV31       (0x0001F300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV32       (0x00020300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV33       (0x00021300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV34       (0x00022300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV35       (0x00023300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV36       (0x00024300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV37       (0x00025300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV38       (0x00026300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV39       (0x00027300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV40       (0x00028300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV41       (0x00029300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV42       (0x0002A300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV43       (0x0002B300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV44       (0x0002C300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV45       (0x0002D300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV46       (0x0002E300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV47       (0x0002F300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV48       (0x00030300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV49       (0x00031300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV50       (0x00032300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV51       (0x00033300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV52       (0x00034300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV53       (0x00035300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV54       (0x00036300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV55       (0x00037300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV56       (0x00038300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV57       (0x00039300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV58       (0x0003A300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV59       (0x0003B300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV60       (0x0003C300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV61       (0x0003D300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV62       (0x0003E300U)
+#define RCC_RTCCLKSOURCE_HSE_DIV63       (0x0003F300U)
+
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_MCO_Index  RCC MCO Index
+  * @{
+  */
+#define RCC_MCO1                         (0x00000000U)
+#define RCC_MCO2                         (0x00000001U)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MCO1_Clock_Source  RCC MCO1 Clock Source
+  * @{
+  */
+#define RCC_MCO1SOURCE_HSI               (0x00000000U)
+#define RCC_MCO1SOURCE_LSE               RCC_CFGR_MCO1_0
+#define RCC_MCO1SOURCE_HSE               RCC_CFGR_MCO1_1
+#define RCC_MCO1SOURCE_PLL1QCLK          ((uint32_t)RCC_CFGR_MCO1_0 | RCC_CFGR_MCO1_1)
+#define RCC_MCO1SOURCE_HSI48              RCC_CFGR_MCO1_2
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MCO2_Clock_Source  RCC MCO2 Clock Source
+  * @{
+  */
+#define RCC_MCO2SOURCE_SYSCLK            (0x00000000U)
+#define RCC_MCO2SOURCE_PLL2PCLK          RCC_CFGR_MCO2_0
+#define RCC_MCO2SOURCE_HSE               RCC_CFGR_MCO2_1
+#define RCC_MCO2SOURCE_PLLCLK            ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_1)
+#define RCC_MCO2SOURCE_CSICLK            RCC_CFGR_MCO2_2
+#define RCC_MCO2SOURCE_LSICLK            ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_2)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MCOx_Clock_Prescaler  RCC MCOx Clock Prescaler
+  * @{
+  */
+#define RCC_MCODIV_1                    RCC_CFGR_MCO1PRE_0
+#define RCC_MCODIV_2                    RCC_CFGR_MCO1PRE_1
+#define RCC_MCODIV_3                    ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1)
+#define RCC_MCODIV_4                    RCC_CFGR_MCO1PRE_2
+#define RCC_MCODIV_5                    ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
+#define RCC_MCODIV_6                    ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
+#define RCC_MCODIV_7                    ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
+#define RCC_MCODIV_8                    RCC_CFGR_MCO1PRE_3
+#define RCC_MCODIV_9                    ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_3)
+#define RCC_MCODIV_10                   ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
+#define RCC_MCODIV_11                   ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
+#define RCC_MCODIV_12                   ((uint32_t)RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
+#define RCC_MCODIV_13                   ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
+#define RCC_MCODIV_14                   ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
+#define RCC_MCODIV_15                   RCC_CFGR_MCO1PRE
+
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Interrupt  RCC Interrupt
+  * @{
+  */
+#define RCC_IT_LSIRDY                  (0x00000001U)
+#define RCC_IT_LSERDY                  (0x00000002U)
+#define RCC_IT_HSIRDY                  (0x00000004U)
+#define RCC_IT_HSERDY                  (0x00000008U)
+#define RCC_IT_CSIRDY                  (0x00000010U)
+#define RCC_IT_HSI48RDY                (0x00000020U)
+#define RCC_IT_PLLRDY                  (0x00000040U)
+#define RCC_IT_PLL2RDY                 (0x00000080U)
+#define RCC_IT_PLL3RDY                 (0x00000100U)
+#define RCC_IT_LSECSS                  (0x00000200U)
+#define RCC_IT_CSS                     (0x00000400U)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Flag  RCC Flag
+  *        Elements values convention: XXXYYYYYb
+  *           - YYYYY  : Flag position in the register
+  *           - XXX  : Register index
+  *                 - 001: CR register
+  *                 - 010: BDCR register
+  *                 - 011: CSR register
+  *                 - 100: RSR register
+  * @{
+  */
+/* Flags in the CR register */
+#define RCC_FLAG_HSIRDY                ((uint8_t)0x22)
+#define RCC_FLAG_HSIDIV                ((uint8_t)0x25)
+#define RCC_FLAG_CSIRDY                ((uint8_t)0x28)
+#define RCC_FLAG_HSI48RDY              ((uint8_t)0x2D)
+#if defined(RCC_CR_D1CKRDY)
+#define RCC_FLAG_D1CKRDY               ((uint8_t)0x2E)
+#else
+#define RCC_FLAG_CPUCKRDY              ((uint8_t)0x2E)
+#define RCC_FLAG_D1CKRDY               RCC_FLAG_CPUCKRDY   /* alias */
+#endif /* RCC_CR_D1CKRDY */
+#if defined(RCC_CR_D2CKRDY)
+#define RCC_FLAG_D2CKRDY               ((uint8_t)0x2F)
+#else
+#define RCC_FLAG_CDCKRDY               ((uint8_t)0x2F)
+#define RCC_FLAG_D2CKRDY               RCC_FLAG_CDCKRDY    /* alias */
+#endif /* RCC_CR_D2CKRDY */
+#define RCC_FLAG_HSERDY                ((uint8_t)0x31)
+#define RCC_FLAG_PLLRDY                ((uint8_t)0x39)
+#define RCC_FLAG_PLL2RDY               ((uint8_t)0x3B)
+#define RCC_FLAG_PLL3RDY               ((uint8_t)0x3D)
+/* Flags in the BDCR register */
+#define RCC_FLAG_LSERDY                ((uint8_t)0x41)
+
+/* Flags in the CSR register */
+#define RCC_FLAG_LSIRDY                ((uint8_t)0x61)
+
+/* Flags in the RSR register */
+#if defined(RCC_RSR_CPURSTF)
+#define RCC_FLAG_CPURST                ((uint8_t)0x91)
+#endif /* RCC_RSR_CPURSTF */
+
+#if defined(RCC_RSR_D1RSTF)
+#define RCC_FLAG_D1RST                 ((uint8_t)0x93)
+#else
+#define RCC_FLAG_CDRST                 ((uint8_t)0x93)
+#endif /* RCC_RSR_D1RSTF */
+#if defined(RCC_RSR_D2RSTF)
+#define RCC_FLAG_D2RST                 ((uint8_t)0x94)
+#endif /* RCC_RSR_D2RSTF */
+#define RCC_FLAG_BORRST                ((uint8_t)0x95)
+#define RCC_FLAG_PINRST                ((uint8_t)0x96)
+#define RCC_FLAG_PORRST                ((uint8_t)0x97)
+#define RCC_FLAG_SFTRST                ((uint8_t)0x98)
+#define RCC_FLAG_IWDG1RST              ((uint8_t)0x9A)
+#define RCC_FLAG_WWDG1RST              ((uint8_t)0x9C)
+#define RCC_FLAG_LPWR1RST              ((uint8_t)0x9E)
+#define RCC_FLAG_LPWR2RST              ((uint8_t)0x9F)
+
+#if defined(DUAL_CORE)
+#define RCC_FLAG_C1RST                 (RCC_FLAG_CPURST)
+#define RCC_FLAG_C2RST                 ((uint8_t)0x92)
+#define RCC_FLAG_SFTR1ST               (RCC_FLAG_SFTRST)
+#define RCC_FLAG_SFTR2ST               ((uint8_t)0x99)
+#define RCC_FLAG_WWDG2RST              ((uint8_t)0x9D)
+#define RCC_FLAG_IWDG2RST              ((uint8_t)0x9B)
+#endif /*DUAL_CORE*/
+
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LSEDrive_Config LSE Drive Config
+  * @{
+  */
+#define RCC_LSEDRIVE_LOW                 (0x00000000U) /*!< LSE low drive capability */
+#define RCC_LSEDRIVE_MEDIUMLOW           RCC_BDCR_LSEDRV_0      /*!< LSE medium low drive capability */
+#define RCC_LSEDRIVE_MEDIUMHIGH          RCC_BDCR_LSEDRV_1      /*!< LSE medium high drive capability */
+#define RCC_LSEDRIVE_HIGH                RCC_BDCR_LSEDRV        /*!< LSE high drive capability */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Stop_WakeUpClock  RCC Stop WakeUpClock
+  * @{
+  */
+#define RCC_STOP_WAKEUPCLOCK_HSI       (0x00000000U)
+#define RCC_STOP_WAKEUPCLOCK_CSI       RCC_CFGR_STOPWUCK
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Stop_KernelWakeUpClock  RCC Stop KernelWakeUpClock
+  * @{
+  */
+#define RCC_STOP_KERWAKEUPCLOCK_HSI       (0x00000000U)
+#define RCC_STOP_KERWAKEUPCLOCK_CSI        RCC_CFGR_STOPKERWUCK
+
+
+/**
+  * @}
+  */
+
+#if defined(RCC_VER_X)
+#define HAL_RCC_REV_Y_HSITRIM_Pos  (12U)
+#define HAL_RCC_REV_Y_HSITRIM_Msk  (0x3F000U)
+#define HAL_RCC_REV_Y_CSITRIM_Pos  (26U)
+#define HAL_RCC_REV_Y_CSITRIM_Msk  (0x7C000000U)
+#endif /* RCC_VER_X */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Macros RCC Exported Macros
+  * @{
+  */
+
+/** @brief  Enable or disable the AHB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+#define __HAL_RCC_MDMA_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_DMA2D_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(JPEG)
+#define __HAL_RCC_JPGDECEN_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* JPEG */
+
+#define __HAL_RCC_FMC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* QUADSPI */
+#if defined(OCTOSPI1)
+#define __HAL_RCC_OSPI1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* OCTOSPI1 */
+#if defined(OCTOSPI2)
+#define __HAL_RCC_OSPI2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* OCTOSPI2 */
+#if defined(OCTOSPIM)
+#define __HAL_RCC_OCTOSPIM_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_IOMNGREN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_IOMNGREN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* OCTOSPIM */
+#if defined(OTFDEC1)
+#define __HAL_RCC_OTFDEC1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* OTFDEC1 */
+#if defined(OTFDEC2)
+#define __HAL_RCC_OTFDEC2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* OTFDEC2 */
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GFXMMUEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GFXMMUEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* GFXMMU */
+#define __HAL_RCC_SDMMC1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_MDMA_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN))
+#define __HAL_RCC_DMA2D_CLK_DISABLE()           (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN))
+#if defined(JPEG)
+#define __HAL_RCC_JPGDECEN_CLK_DISABLE()        (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN))
+#endif /* JPEG */
+#define __HAL_RCC_FMC_CLK_DISABLE()             (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))
+
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN))
+#endif /* QUADSPI */
+#if defined(OCTOSPI1)
+#define __HAL_RCC_OSPI1_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OSPI1EN))
+#endif /* OCTOSPII */
+#if defined(OCTOSPI2)
+#define __HAL_RCC_OSPI2_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OSPI2EN))
+#endif /* OCTOSPI2 */
+#define __HAL_RCC_SDMMC1_CLK_DISABLE()          (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN))
+#if defined(OCTOSPIM)
+#define __HAL_RCC_OCTOSPIM_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_IOMNGREN))
+#endif /* OCTOSPIM */
+#if defined(OTFDEC1)
+#define __HAL_RCC_OTFDEC1_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OTFDEC1EN))
+#endif /* OTOFDEC1 */
+#if defined(OTFDEC2)
+#define __HAL_RCC_OTFDEC2_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OTFDEC2EN))
+#endif /* OTOFDEC2 */
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_GFXMMUEN))
+#endif /* GFXMMU */
+
+/** @brief  Get the enable or disable status of the AHB3 peripheral clock
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_MDMA_IS_CLK_ENABLED()          ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN)   != 0U)
+#define __HAL_RCC_DMA2D_IS_CLK_ENABLED()         ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN)  != 0U)
+#if defined(JPEG)
+#define __HAL_RCC_JPGDECEN_IS_CLK_ENABLED()      ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) != 0U)
+#endif /* JPEG */
+#define __HAL_RCC_FMC_IS_CLK_ENABLED()           ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN)    != 0U)
+#if defined (QUADSPI)
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED()          ((RCC->AHB3ENR & RCC_AHB3ENR_QSPIEN)   != 0U)
+#endif /* QUADSPI */
+#if defined(OCTOSPI1)
+#define __HAL_RCC_OSPI1_IS_CLK_ENABLED()          ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI1EN)   != 0U)
+#endif /* OCTOSPII */
+#if defined(OCTOSPI2)
+#define __HAL_RCC_OSPI2_IS_CLK_ENABLED()          ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI2EN)   != 0U)
+#endif /* OCTOSPI2 */
+#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) != 0U)
+#if defined(OCTOSPIM)
+#define __HAL_RCC_OCTOSPIM_IS_CLK_ENABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_IOMNGREN) != 0U)
+#endif /* OCTOSPIM */
+#if defined(OTFDEC1)
+#define __HAL_RCC_OTFDEC1_IS_CLK_ENABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC1EN) != 0U)
+#endif /* OTOFDEC1 */
+#if defined(OTFDEC2)
+#define __HAL_RCC_OTFDEC2_IS_CLK_ENABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC2EN) != 0U)
+#endif /* OTOFDEC2 */
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_IS_CLK_ENABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_GFXMMUEN) != 0U)
+#endif /* GFXMMU */
+
+#define __HAL_RCC_MDMA_IS_CLK_DISABLED()         ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN)   == 0U)
+#define __HAL_RCC_DMA2D_IS_CLK_DISABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN)  == 0U)
+#if defined(JPEG)
+#define __HAL_RCC_JPGDECEN_IS_CLK_DISABLED()     ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) == 0U)
+#endif /* JPEG */
+#define __HAL_RCC_FMC_IS_CLK_DISABLED()          ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN)    == 0U)
+#if defined (QUADSPI)
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED()         ((RCC->AHB3ENR & RCC_AHB3ENR_QSPIEN)   == 0U)
+#endif /* QUADSPI */
+#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED()       ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) == 0U)
+#if defined(OCTOSPI1)
+#define __HAL_RCC_OSPI1_IS_CLK_DISABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI1EN) == 0U)
+#endif
+#if defined(OCTOSPI2)
+#define __HAL_RCC_OSPI2_IS_CLK_DISABLED()     ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI2EN) == 0U)
+#endif
+#if defined(OCTOSPIM)
+#define __HAL_RCC_OCTOSPIM_IS_CLK_DISABLED()     ((RCC->AHB3ENR & RCC_AHB3ENR_IOMNGREN) == 0U)
+#endif
+#if defined(OTFDEC1)
+#define __HAL_RCC_OTFDEC1_IS_CLK_DISABLED()      ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC1EN) == 0U)
+#endif
+#if defined(OTFDEC2)
+#define __HAL_RCC_OTFDEC2_IS_CLK_DISABLED()      ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC2EN) == 0U)
+#endif
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_IS_CLK_DISABLED()       ((RCC->AHB3ENR & RCC_AHB3ENR_GFXMMUEN) == 0U)
+#endif
+/** @brief  Enable or disable the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_DMA1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_DMA2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_ADC12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(DUAL_CORE)
+#define __HAL_RCC_ART_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ARTEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ARTEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /*DUAL_CORE*/
+
+#if defined(RCC_AHB1ENR_CRCEN)
+#define __HAL_RCC_CRC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif
+
+#if defined(ETH)
+#define __HAL_RCC_ETH1MAC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_ETH1TX_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_ETH1RX_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif
+
+#define __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(USB2_OTG_FS)
+#define __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif
+
+#define __HAL_RCC_DMA1_CLK_DISABLE()             (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN))
+#define __HAL_RCC_DMA2_CLK_DISABLE()             (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN))
+#define __HAL_RCC_ADC12_CLK_DISABLE()            (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN))
+#if defined(DUAL_CORE)
+#define __HAL_RCC_ART_CLK_DISABLE()              (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN))
+#endif /*DUAL_CORE*/
+#if defined(RCC_AHB1ENR_CRCEN)
+#define __HAL_RCC_CRC_CLK_DISABLE()              (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_CRCEN))
+#endif
+#if defined(ETH)
+#define __HAL_RCC_ETH1MAC_CLK_DISABLE()          (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN))
+#define __HAL_RCC_ETH1TX_CLK_DISABLE()           (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN))
+#define __HAL_RCC_ETH1RX_CLK_DISABLE()           (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN))
+#endif
+#define __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()      (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN))
+#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN))
+#if defined(USB2_OTG_FS)
+#define __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()      (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN))
+#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN))
+#endif /* USB2_OTG_FS */
+
+/** @brief  Get the enable or disable status of the AHB1 peripheral clock
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_DMA1_IS_CLK_ENABLED()              ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN)          != 0U)
+#define __HAL_RCC_DMA2_IS_CLK_ENABLED()              ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN)          != 0U)
+#define __HAL_RCC_ADC12_IS_CLK_ENABLED()             ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN)         != 0U)
+#if defined(DUAL_CORE)
+#define __HAL_RCC_ART_IS_CLK_ENABLED()               ((RCC->AHB1ENR & RCC_AHB1ENR_ARTEN)           != 0U)
+#endif /*DUAL_CORE*/
+#if defined(RCC_AHB1ENR_CRCEN)
+#define __HAL_RCC_CRC_IS_CLK_ENABLED()              ((RCC->AHB1ENR & RCC_AHB1ENR_CRCEN)       != 0U)
+#endif
+#if defined(ETH)
+#define __HAL_RCC_ETH1MAC_IS_CLK_ENABLED()           ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1MACEN)       != 0U)
+#define __HAL_RCC_ETH1TX_IS_CLK_ENABLED()            ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1TXEN)        != 0U)
+#define __HAL_RCC_ETH1RX_IS_CLK_ENABLED()            ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1RXEN)        != 0U)
+#endif
+#define __HAL_RCC_USB1_OTG_HS_IS_CLK_ENABLED()       ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN)     != 0U)
+#define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_ENABLED()  ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) != 0U)
+#if defined(USB2_OTG_FS)
+#define __HAL_RCC_USB2_OTG_FS_IS_CLK_ENABLED()       ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSEN)     != 0U)
+#define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_ENABLED()  ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSULPIEN) != 0U)
+#endif /* USB2_OTG_FS */
+
+#define __HAL_RCC_DMA1_IS_CLK_DISABLED()             ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN)          == 0U)
+#define __HAL_RCC_DMA2_IS_CLK_DISABLED()             ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN)          == 0U)
+#define __HAL_RCC_ADC12_IS_CLK_DISABLED()            ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN)         == 0U)
+#if defined(DUAL_CORE)
+#define __HAL_RCC_ART_IS_CLK_DISABLED()              ((RCC->AHB1ENR & RCC_AHB1ENR_ARTEN)           == 0U)
+#endif /*DUAL_CORE*/
+#if defined(RCC_AHB1ENR_CRCEN)
+#define __HAL_RCC_CRC_IS_CLK_DISABLED()              ((RCC->AHB1ENR & RCC_AHB1ENR_CRCEN)           == 0U)
+#endif
+#if defined(ETH)
+#define __HAL_RCC_ETH1MAC_IS_CLK_DISABLED()          ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1MACEN)       == 0U)
+#define __HAL_RCC_ETH1TX_IS_CLK_DISABLED()           ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1TXEN)        == 0U)
+#define __HAL_RCC_ETH1RX_IS_CLK_DISABLED()           ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1RXEN)        == 0U)
+#endif
+#define __HAL_RCC_USB1_OTG_HS_IS_CLK_DISABLED()      ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN)     == 0U)
+#define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) == 0U)
+#if defined(USB2_OTG_FS)
+#define __HAL_RCC_USB2_OTG_FS_IS_CLK_DISABLED()      ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSEN)     == 0U)
+#define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSULPIEN) == 0U)
+#endif /* USB2_OTG_FS */
+
+/** @brief  Enable or disable the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#if defined(DCMI) && defined(PSSI)
+#define __HAL_RCC_DCMI_PSSI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_DCMI_CLK_ENABLE()  __HAL_RCC_DCMI_PSSI_CLK_ENABLE()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_DCMI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* DCMI && PSSI */
+
+#if defined(CRYP)
+#define __HAL_RCC_CRYP_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* CRYP */
+
+#if defined(HASH)
+#define __HAL_RCC_HASH_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* HASH */
+
+#define __HAL_RCC_RNG_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_SDMMC2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(RCC_AHB2ENR_D2SRAM1EN)
+#define __HAL_RCC_D2SRAM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#else
+#define __HAL_RCC_AHBSRAM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* RCC_AHB2ENR_D2SRAM1EN */
+
+#if defined(RCC_AHB2ENR_D2SRAM2EN)
+#define __HAL_RCC_D2SRAM2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#else
+#define __HAL_RCC_AHBSRAM2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* RCC_AHB2ENR_D2SRAM2EN */
+
+#if defined(RCC_AHB2ENR_D2SRAM3EN)
+#define __HAL_RCC_D2SRAM3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif
+
+#if defined(RCC_AHB2ENR_HSEMEN)
+#define __HAL_RCC_HSEM_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* RCC_AHB2ENR_HSEMEN */
+
+#if defined(BDMA1)
+#define __HAL_RCC_BDMA1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_BDMA1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_BDMA1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* BDMA1 */
+
+#if defined(DCMI) && defined(PSSI)
+#define __HAL_RCC_DCMI_PSSI_CLK_DISABLE()         (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMI_PSSIEN))
+#define __HAL_RCC_DCMI_CLK_DISABLE()              __HAL_RCC_DCMI_PSSI_CLK_DISABLE()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_DCMI_CLK_DISABLE()             (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))
+#endif /* DCMI && PSSI */
+#if defined(CRYP)
+#define __HAL_RCC_CRYP_CLK_DISABLE()             (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_HASH_CLK_DISABLE()             (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))
+#endif /* HASH */
+#define __HAL_RCC_RNG_CLK_DISABLE()              (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))
+#define __HAL_RCC_SDMMC2_CLK_DISABLE()           (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))
+#if defined(RCC_AHB2ENR_D2SRAM1EN)
+#define __HAL_RCC_D2SRAM1_CLK_DISABLE()          (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN))
+#else
+#define __HAL_RCC_AHBSRAM1_CLK_DISABLE()         (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_AHBSRAM1EN))
+#endif /* RCC_AHB2ENR_D2SRAM1EN */
+#if defined(RCC_AHB2ENR_D2SRAM2EN)
+#define __HAL_RCC_D2SRAM2_CLK_DISABLE()          (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN))
+#else
+#define __HAL_RCC_AHBSRAM2_CLK_DISABLE()         (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_AHBSRAM2EN))
+#endif /* RCC_AHB2ENR_D2SRAM2EN */
+#if defined(RCC_AHB2ENR_D2SRAM3EN)
+#define __HAL_RCC_D2SRAM3_CLK_DISABLE()          (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN))
+#endif
+#if defined(RCC_AHB2ENR_HSEMEN)
+#define __HAL_RCC_HSEM_CLK_DISABLE()             (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HSEMEN))
+#endif
+#if defined(BDMA1)
+#define __HAL_RCC_BDMA1_CLK_DISABLE()            (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_BDMA1EN))
+#endif
+
+/** @brief  Get the enable or disable status of the AHB2 peripheral clock
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#if defined(DCMI) && defined(PSSI)
+#define __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED()         ((RCC->AHB2ENR & RCC_AHB2ENR_DCMI_PSSIEN)    != 0U)
+#define __HAL_RCC_DCMI_IS_CLK_ENABLED()              __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_DCMI_IS_CLK_ENABLED()              ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN)    != 0U)
+#endif /* DCMI && PSSI */
+#if defined(CRYP)
+#define __HAL_RCC_CRYP_IS_CLK_ENABLED()              ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN)    != 0U)
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_HASH_IS_CLK_ENABLED()              ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN)    != 0U)
+#endif /* HASH */
+#define __HAL_RCC_RNG_IS_CLK_ENABLED()               ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN)     != 0U)
+#define __HAL_RCC_SDMMC2_IS_CLK_ENABLED()            ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN)  != 0U)
+#if defined(RCC_AHB2ENR_D2SRAM1EN)
+#define __HAL_RCC_D2SRAM1_IS_CLK_ENABLED()           ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM1EN) != 0U)
+#else
+#define __HAL_RCC_AHBSRAM1_IS_CLK_ENABLED()          ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM1EN) != 0U)
+#endif /* RCC_AHB2ENR_D2SRAM1EN */
+#if defined(RCC_AHB2ENR_D2SRAM2EN)
+#define __HAL_RCC_D2SRAM2_IS_CLK_ENABLED()           ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM2EN) != 0U)
+#else
+#define __HAL_RCC_AHBSRAM2_IS_CLK_ENABLED()          ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM2EN) != 0U)
+#endif /* RCC_AHB2ENR_D2SRAM2EN */
+#if defined(RCC_AHB2ENR_D2SRAM3EN)
+#define __HAL_RCC_D2SRAM3_IS_CLK_ENABLED()           ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM3EN) != 0U)
+#endif
+#if defined(RCC_AHB2ENR_HSEMEN)
+#define __HAL_RCC_HSEM_IS_CLK_ENABLED()              ((RCC->AHB2ENR & RCC_AHB2ENR_HSEMEN)    != 0U)
+#endif
+#if defined(BDMA1)
+#define __HAL_RCC_BDMA1_IS_CLK_ENABLED()             ((RCC->AHB2ENR & RCC_AHB2ENR_BDMA1EN)  != 0U)
+#endif
+
+#if defined(DCMI) && defined(PSSI)
+#define __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED()        ((RCC->AHB2ENR & RCC_AHB2ENR_DCMI_PSSIEN)    == 0U)
+#define __HAL_RCC_DCMI_IS_CLK_DISABLED()             __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_DCMI_IS_CLK_DISABLED()             ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN)    == 0U)
+#endif /* DCMI && PSSI */
+#if defined(CRYP)
+#define __HAL_RCC_CRYP_IS_CLK_DISABLED()             ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN)    == 0U)
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_HASH_IS_CLK_DISABLED()             ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN)    == 0U)
+#endif /* HASH */
+#define __HAL_RCC_RNG_IS_CLK_DISABLED()              ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN)     == 0U)
+#define __HAL_RCC_SDMMC2_IS_CLK_DISABLED()           ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN)  == 0U)
+#if defined(RCC_AHB2ENR_D2SRAM1EN)
+#define __HAL_RCC_D2SRAM1_IS_CLK_DISABLED()          ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM1EN) == 0U)
+#else
+#define __HAL_RCC_AHBSRAM1_IS_CLK_DISABLED()         ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM1EN) == 0U)
+#endif /* RCC_AHB2ENR_D2SRAM1EN */
+#if defined(RCC_AHB2ENR_D2SRAM2EN)
+#define __HAL_RCC_D2SRAM2_IS_CLK_DISABLED()          ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM2EN) == 0U)
+#else
+#define __HAL_RCC_AHBSRAM2_IS_CLK_DISABLED()         ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM2EN) == 0U)
+#endif /* RCC_AHB2ENR_D2SRAM2EN */
+#if defined(RCC_AHB2ENR_D2SRAM3EN)
+#define __HAL_RCC_D2SRAM3_IS_CLK_DISABLED()          ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM3EN) == 0U)
+#endif
+#if defined(RCC_AHB2ENR_HSEMEN)
+#define __HAL_RCC_HSEM_IS_CLK_DISABLED()             ((RCC->AHB2ENR & RCC_AHB2ENR_HSEMEN)    == 0U)
+#endif
+#if defined(BDMA1)
+#define __HAL_RCC_BDMA1_IS_CLK_DISABLED()            ((RCC->AHB2ENR & RCC_AHB2ENR_BDMA1EN)   == 0U)
+#endif
+
+/** @brief  Enable or disable the AHB4 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_GPIOA_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_GPIOB_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_GPIOC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_GPIOF_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_GPIOG_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_GPIOH_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_GPIOI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_GPIOJ_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_GPIOK_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(RCC_AHB4ENR_CRCEN)
+#define __HAL_RCC_CRC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif
+
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMA2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMA2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_BDMA_CLK_ENABLE()  __HAL_RCC_BDMA2_CLK_ENABLE()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_BDMA_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif
+
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif
+
+#if defined(RCC_AHB4ENR_HSEMEN)
+#define __HAL_RCC_HSEM_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif
+
+#if defined(RCC_AHB4ENR_SRDSRAMEN)
+#define __HAL_RCC_SRDSRAM_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SRDSRAMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SRDSRAMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif
+
+#define __HAL_RCC_BKPRAM_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_GPIOA_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN)
+#define __HAL_RCC_GPIOB_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN)
+#define __HAL_RCC_GPIOC_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN)
+#define __HAL_RCC_GPIOD_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN)
+#define __HAL_RCC_GPIOE_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN)
+#define __HAL_RCC_GPIOF_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN)
+#define __HAL_RCC_GPIOG_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN)
+#define __HAL_RCC_GPIOH_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN)
+#define __HAL_RCC_GPIOI_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN)
+#define __HAL_RCC_GPIOJ_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN)
+#define __HAL_RCC_GPIOK_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN)
+#if defined(RCC_AHB4ENR_CRCEN)
+#define __HAL_RCC_CRC_CLK_DISABLE()             (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN)
+#endif
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMA2EN)
+#define __HAL_RCC_BDMA_CLK_DISABLE()            __HAL_RCC_BDMA2_CLK_DISABLE()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_BDMA_CLK_DISABLE()            (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN)
+#endif
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_CLK_DISABLE()            (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN)
+#endif
+#if defined(RCC_AHB4ENR_HSEMEN)
+#define __HAL_RCC_HSEM_CLK_DISABLE()            (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN)
+#endif
+#if defined(RCC_AHB4ENR_SRDSRAMEN)
+#define __HAL_RCC_SRDSRAM_CLK_DISABLE()         (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_SRDSRAMEN)
+#endif
+#define __HAL_RCC_BKPRAM_CLK_DISABLE()          (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN)
+
+
+/** @brief  Get the enable or disable status of the AHB4 peripheral clock
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_GPIOA_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN)  != 0U)
+#define __HAL_RCC_GPIOB_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN)  != 0U)
+#define __HAL_RCC_GPIOC_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN)  != 0U)
+#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN)  != 0U)
+#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN)  != 0U)
+#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN)  != 0U)
+#define __HAL_RCC_GPIOG_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN)  != 0U)
+#define __HAL_RCC_GPIOH_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN)  != 0U)
+#define __HAL_RCC_GPIOI_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN)  != 0U)
+#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN)  != 0U)
+#define __HAL_RCC_GPIOK_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN)  != 0U)
+#if defined(RCC_AHB4ENR_CRCEN)
+#define __HAL_RCC_CRC_IS_CLK_ENABLED()              ((RCC->AHB4ENR & RCC_AHB4ENR_CRCEN)    != 0U)
+#endif
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_BDMA2EN)   != 0U)
+#define __HAL_RCC_BDMA_IS_CLK_ENABLED()  __HAL_RCC_BDMA2_IS_CLK_ENABLED()            /* for API backward compatibility*/
+#else
+#define __HAL_RCC_BDMA_IS_CLK_ENABLED()             ((RCC->AHB4ENR & RCC_AHB4ENR_BDMAEN)   != 0U)
+#endif
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_IS_CLK_ENABLED()             ((RCC->AHB4ENR & RCC_AHB4ENR_ADC3EN)   != 0U)
+#endif
+#if defined(RCC_AHB4ENR_HSEMEN)
+#define __HAL_RCC_HSEM_IS_CLK_ENABLED()             ((RCC->AHB4ENR & RCC_AHB4ENR_HSEMEN)   != 0U)
+#endif
+#if defined(RCC_AHB4ENR_SRDSRAMEN)
+#define __HAL_RCC_SRDSRAM_IS_CLK_ENABLED()          ((RCC->AHB4ENR & RCC_AHB4ENR_SRDSRAMEN) != 0U)
+#endif
+#define __HAL_RCC_BKPRAM_IS_CLK_ENABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) != 0U)
+
+#define __HAL_RCC_GPIOA_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN)  == 0U)
+#define __HAL_RCC_GPIOB_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN)  == 0U)
+#define __HAL_RCC_GPIOC_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN)  == 0U)
+#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN)  == 0U)
+#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN)  == 0U)
+#define __HAL_RCC_GPIOF_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN)  == 0U)
+#define __HAL_RCC_GPIOG_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN)  == 0U)
+#define __HAL_RCC_GPIOH_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN)  == 0U)
+#define __HAL_RCC_GPIOI_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN)  == 0U)
+#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN)  == 0U)
+#define __HAL_RCC_GPIOK_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN)  == 0U)
+
+#if defined(RCC_AHB4ENR_CRCEN)
+#define __HAL_RCC_CRC_IS_CLK_DISABLED()             ((RCC->AHB4ENR & RCC_AHB4ENR_CRCEN)    == 0U)
+#endif
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_IS_CLK_DISABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_BDMA2EN)   == 0U)
+#define __HAL_RCC_BDMA_IS_CLK_DISABLED()  __HAL_RCC_BDMA2_IS_CLK_DISABLED()           /* for API backward compatibility*/
+#else
+#define __HAL_RCC_BDMA_IS_CLK_DISABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_BDMAEN)   == 0U)
+#endif
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_IS_CLK_DISABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_ADC3EN)   == 0U)
+#endif
+#if defined(RCC_AHB4ENR_HSEMEN)
+#define __HAL_RCC_HSEM_IS_CLK_DISABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_HSEMEN)   == 0U)
+#endif
+#if defined(RCC_AHB4ENR_SRDSRAMEN)
+#define __HAL_RCC_SRDSRAM_IS_CLK_DISABLED()         ((RCC->AHB4ENR & RCC_AHB4ENR_SRDSRAMEN)   == 0U)
+#endif
+#define __HAL_RCC_BKPRAM_IS_CLK_DISABLED()          ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) == 0U)
+
+
+/** @brief  Enable or disable the APB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LTDCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LTDCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* LTDC */
+
+#if defined(DSI)
+#define __HAL_RCC_DSI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB3ENR, RCC_APB3ENR_DSIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_DSIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /*DSI*/
+
+#define __HAL_RCC_WWDG1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_CLK_DISABLE()           (RCC->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN)
+#endif /* LTDC */
+#if defined(DSI)
+#define __HAL_RCC_DSI_CLK_DISABLE()            (RCC->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN)
+#endif /*DSI*/
+#define __HAL_RCC_WWDG1_CLK_DISABLE()          (RCC->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN)
+
+/** @brief  Get the enable or disable status of the APB3 peripheral clock
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_IS_CLK_ENABLED()            ((RCC->APB3ENR & RCC_APB3ENR_LTDCEN)  != 0U)
+#endif /* LTDC */
+#if defined(DSI)
+#define __HAL_RCC_DSI_IS_CLK_ENABLED()             ((RCC->APB3ENR & RCC_APB3ENR_DSIEN)   != 0U)
+#endif /*DSI*/
+#define __HAL_RCC_WWDG1_IS_CLK_ENABLED()           ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) != 0U)
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_IS_CLK_DISABLED()           ((RCC->APB3ENR & RCC_APB3ENR_LTDCEN)  == 0U)
+#endif /* LTDC */
+#if defined(DSI)
+#define __HAL_RCC_DSI_IS_CLK_DISABLED()            ((RCC->APB3ENR & RCC_APB3ENR_DSIEN)   == 0U)
+#endif /*DSI*/
+#define __HAL_RCC_WWDG1_IS_CLK_DISABLED()          ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) == 0U)
+
+
+/** @brief  Enable or disable the APB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_TIM2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM6_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM7_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM13_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM14_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_LPTIM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(DUAL_CORE)
+#define __HAL_RCC_WWDG2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDG2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDG2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /*DUAL_CORE*/
+
+#define __HAL_RCC_SPI2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_SPI3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_SPDIFRX_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_USART2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_USART3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_UART4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_UART5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_I2C1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_I2C2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_I2C3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_CEC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_DAC12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_UART7_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_UART8_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_CRS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_SWPMI1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_OPAMP_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_MDIOS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_FDCAN_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_TIM2_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN)
+#define __HAL_RCC_TIM3_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN)
+#define __HAL_RCC_TIM4_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN)
+#define __HAL_RCC_TIM5_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN)
+#define __HAL_RCC_TIM6_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN)
+#define __HAL_RCC_TIM7_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN)
+#define __HAL_RCC_TIM12_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN)
+#define __HAL_RCC_TIM13_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN)
+#define __HAL_RCC_TIM14_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN)
+#define __HAL_RCC_LPTIM1_CLK_DISABLE()         (RCC->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN)
+
+#if defined(DUAL_CORE)
+#define __HAL_RCC_WWDG2_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN)
+#endif /*DUAL_CORE*/
+
+#define __HAL_RCC_SPI2_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN)
+#define __HAL_RCC_SPI3_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN)
+#define __HAL_RCC_SPDIFRX_CLK_DISABLE()        (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN)
+#define __HAL_RCC_USART2_CLK_DISABLE()         (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN)
+#define __HAL_RCC_USART3_CLK_DISABLE()         (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN)
+#define __HAL_RCC_UART4_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN)
+#define __HAL_RCC_UART5_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN)
+#define __HAL_RCC_I2C1_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN)
+#define __HAL_RCC_I2C2_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN)
+#define __HAL_RCC_I2C3_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN)
+#define __HAL_RCC_CEC_CLK_DISABLE()            (RCC->APB1LENR) &= ~ (RCC_APB1LENR_CECEN)
+#define __HAL_RCC_DAC12_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN)
+#define __HAL_RCC_UART7_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN)
+#define __HAL_RCC_UART8_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN)
+#define __HAL_RCC_CRS_CLK_DISABLE()            (RCC->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN)
+#define __HAL_RCC_SWPMI1_CLK_DISABLE()          (RCC->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN)
+#define __HAL_RCC_OPAMP_CLK_DISABLE()          (RCC->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN)
+#define __HAL_RCC_MDIOS_CLK_DISABLE()          (RCC->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN)
+#define __HAL_RCC_FDCAN_CLK_DISABLE()          (RCC->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN)
+
+
+/** @brief  Get the enable or disable status of the APB1 peripheral clock
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_TIM2_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN)    != 0U)
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN)    != 0U)
+#define __HAL_RCC_TIM4_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN)    != 0U)
+#define __HAL_RCC_TIM5_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN)    != 0U)
+#define __HAL_RCC_TIM6_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN)    != 0U)
+#define __HAL_RCC_TIM7_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN)    != 0U)
+#define __HAL_RCC_TIM12_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN)   != 0U)
+#define __HAL_RCC_TIM13_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN)   != 0U)
+#define __HAL_RCC_TIM14_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN)   != 0U)
+#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED()          ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN)  != 0U)
+#if defined(DUAL_CORE)
+#define __HAL_RCC_WWDG2_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_WWDG2EN)   != 0U)
+#endif /*DUAL_CORE*/
+#define __HAL_RCC_SPI2_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN)    != 0U)
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN)    != 0U)
+#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED()         ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) != 0U)
+#define __HAL_RCC_USART2_IS_CLK_ENABLED()          ((RCC->APB1LENR & RCC_APB1LENR_USART2EN)  != 0U)
+#define __HAL_RCC_USART3_IS_CLK_ENABLED()          ((RCC->APB1LENR & RCC_APB1LENR_USART3EN)  != 0U)
+#define __HAL_RCC_UART4_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_UART4EN)   != 0U)
+#define __HAL_RCC_UART5_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_UART5EN)   != 0U)
+#define __HAL_RCC_I2C1_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN)    != 0U)
+#define __HAL_RCC_I2C2_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN)    != 0U)
+#define __HAL_RCC_I2C3_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN)    != 0U)
+#define __HAL_RCC_CEC_IS_CLK_ENABLED()             ((RCC->APB1LENR & RCC_APB1LENR_CECEN)     != 0U)
+#define __HAL_RCC_DAC12_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN)   != 0U)
+#define __HAL_RCC_UART7_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_UART7EN)   != 0U)
+#define __HAL_RCC_UART8_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_UART8EN)   != 0U)
+#define __HAL_RCC_CRS_IS_CLK_ENABLED()             ((RCC->APB1HENR & RCC_APB1HENR_CRSEN)     != 0U)
+#define __HAL_RCC_SWPMI1_IS_CLK_ENABLED()          ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN)   != 0U)
+#define __HAL_RCC_OPAMP_IS_CLK_ENABLED()           ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN)   != 0U)
+#define __HAL_RCC_MDIOS_IS_CLK_ENABLED()           ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN)   != 0U)
+#define __HAL_RCC_FDCAN_IS_CLK_ENABLED()           ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN)   != 0U)
+
+#define __HAL_RCC_TIM2_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN)    == 0U)
+#define __HAL_RCC_TIM3_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN)    == 0U)
+#define __HAL_RCC_TIM4_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN)    == 0U)
+#define __HAL_RCC_TIM5_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN)    == 0U)
+#define __HAL_RCC_TIM6_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN)    == 0U)
+#define __HAL_RCC_TIM7_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN)    == 0U)
+#define __HAL_RCC_TIM12_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN)   == 0U)
+#define __HAL_RCC_TIM13_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN)   == 0U)
+#define __HAL_RCC_TIM14_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN)   == 0U)
+#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED()         ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN)  == 0U)
+#if defined(DUAL_CORE)
+#define __HAL_RCC_WWDG2_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_WWDG2EN)   == 0U)
+#endif /*DUAL_CORE*/
+#define __HAL_RCC_SPI2_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN)    == 0U)
+#define __HAL_RCC_SPI3_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN)    == 0U)
+#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED()        ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) == 0U)
+#define __HAL_RCC_USART2_IS_CLK_DISABLED()         ((RCC->APB1LENR & RCC_APB1LENR_USART2EN)  == 0U)
+#define __HAL_RCC_USART3_IS_CLK_DISABLED()         ((RCC->APB1LENR & RCC_APB1LENR_USART3EN)  == 0U)
+#define __HAL_RCC_UART4_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_UART4EN)   == 0U)
+#define __HAL_RCC_UART5_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_UART5EN)   == 0U)
+#define __HAL_RCC_I2C1_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN)    == 0U)
+#define __HAL_RCC_I2C2_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN)    == 0U)
+#define __HAL_RCC_I2C3_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN)    == 0U)
+#define __HAL_RCC_CEC_IS_CLK_DISABLED()            ((RCC->APB1LENR & RCC_APB1LENR_CECEN)     == 0U)
+#define __HAL_RCC_DAC12_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN)   == 0U)
+#define __HAL_RCC_UART7_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_UART7EN)   == 0U)
+#define __HAL_RCC_UART8_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_UART8EN)   == 0U)
+#define __HAL_RCC_CRS_IS_CLK_DISABLED()            ((RCC->APB1HENR & RCC_APB1HENR_CRSEN)     == 0U)
+#define __HAL_RCC_SWPMI1_IS_CLK_DISABLED()         ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN)   == 0U)
+#define __HAL_RCC_OPAMP_IS_CLK_DISABLED()          ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN)   == 0U)
+#define __HAL_RCC_MDIOS_IS_CLK_DISABLED()          ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN)   == 0U)
+#define __HAL_RCC_FDCAN_IS_CLK_DISABLED()          ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN)   == 0U)
+
+
+/** @brief  Enable or disable the APB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_TIM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM8_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_USART1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_USART6_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(UART9)
+#define __HAL_RCC_UART9_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /*UART9*/
+
+#if defined(USART10)
+#define __HAL_RCC_USART10_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART10EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART10EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /*USART10*/
+
+#define __HAL_RCC_SPI1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_SPI4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM15_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM16_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_TIM17_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_SPI5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_SAI1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_SAI2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(SAI3)
+#define __HAL_RCC_SAI3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /*SAI3*/
+
+#define __HAL_RCC_DFSDM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /*HRTIM1*/
+
+#define __HAL_RCC_TIM1_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)
+#define __HAL_RCC_TIM8_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)
+#define __HAL_RCC_USART1_CLK_DISABLE()         (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)
+#define __HAL_RCC_USART6_CLK_DISABLE()         (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)
+#if defined(UART9)
+#define __HAL_RCC_UART9_CLK_DISABLE()          (RCC->APB2ENR) &= ~ (RCC_APB2ENR_UART9EN)
+#endif /*UART9*/
+#if defined(USART10)
+#define __HAL_RCC_USART10_CLK_DISABLE()        (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART10EN)
+#endif /*USART10*/
+#define __HAL_RCC_SPI1_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)
+#define __HAL_RCC_SPI4_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)
+#define __HAL_RCC_TIM15_CLK_DISABLE()          (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)
+#define __HAL_RCC_TIM16_CLK_DISABLE()          (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)
+#define __HAL_RCC_TIM17_CLK_DISABLE()          (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)
+#define __HAL_RCC_SPI5_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)
+#define __HAL_RCC_SAI1_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)
+#define __HAL_RCC_SAI2_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN)
+#if defined(SAI3)
+#define __HAL_RCC_SAI3_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN)
+#endif /*SAI3*/
+#define __HAL_RCC_DFSDM1_CLK_DISABLE()         (RCC->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_CLK_DISABLE()         (RCC->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN)
+#endif /*HRTIM*/
+
+/** @brief  Get the enable or disable status of the APB2 peripheral clock
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_TIM1_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN)   != 0U)
+#define __HAL_RCC_TIM8_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN)   != 0U)
+#define __HAL_RCC_USART1_IS_CLK_ENABLED()          ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) != 0U)
+#define __HAL_RCC_USART6_IS_CLK_ENABLED()          ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) != 0U)
+#if defined(UART9)
+#define __HAL_RCC_UART9_IS_CLK_ENABLED()           ((RCC->APB2ENR & RCC_APB2ENR_UART9EN) != 0U)
+#endif /*UART9*/
+#if defined(USART10)
+#define __HAL_RCC_USART10_IS_CLK_ENABLED()         ((RCC->APB2ENR & RCC_APB2ENR_USART10EN) != 0U)
+#endif /*USART10*/
+#define __HAL_RCC_SPI1_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN)   != 0U)
+#define __HAL_RCC_SPI4_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN)   != 0U)
+#define __HAL_RCC_TIM15_IS_CLK_ENABLED()           ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN)  != 0U)
+#define __HAL_RCC_TIM16_IS_CLK_ENABLED()           ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN)  != 0U)
+#define __HAL_RCC_TIM17_IS_CLK_ENABLED()           ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN)  != 0U)
+#define __HAL_RCC_SPI5_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN)   != 0U)
+#define __HAL_RCC_SAI1_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN)   != 0U)
+#define __HAL_RCC_SAI2_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN)   != 0U)
+#if defined(SAI3)
+#define __HAL_RCC_SAI3_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_SAI3EN)   != 0U)
+#endif /* SAI3 */
+#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED()          ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) != 0U)
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_IS_CLK_ENABLED()          ((RCC->APB2ENR & RCC_APB2ENR_HRTIMEN)  != 0U)
+#endif /*HRTIM1*/
+
+#define __HAL_RCC_TIM1_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN)   == 0U)
+#define __HAL_RCC_TIM8_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN)   == 0U)
+#define __HAL_RCC_USART1_IS_CLK_DISABLED()         ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) == 0U)
+#define __HAL_RCC_USART6_IS_CLK_DISABLED()         ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) == 0U)
+#if defined(UART9)
+#define __HAL_RCC_UART9_IS_CLK_DISABLED()         ((RCC->APB2ENR & RCC_APB2ENR_UART9EN) == 0U)
+#endif /*UART9*/
+#if defined(USART10)
+#define __HAL_RCC_USART10_IS_CLK_DISABLED()         ((RCC->APB2ENR & RCC_APB2ENR_USART10EN) == 0U)
+#endif /*USART10*/
+#define __HAL_RCC_SPI1_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN)   == 0U)
+#define __HAL_RCC_SPI4_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN)   == 0U)
+#define __HAL_RCC_TIM15_IS_CLK_DISABLED()          ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN)  == 0U)
+#define __HAL_RCC_TIM16_IS_CLK_DISABLED()          ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN)  == 0U)
+#define __HAL_RCC_TIM17_IS_CLK_DISABLED()          ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN)  == 0U)
+#define __HAL_RCC_SPI5_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN)   == 0U)
+#define __HAL_RCC_SAI1_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN)   == 0U)
+#define __HAL_RCC_SAI2_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN)   == 0U)
+#if defined(SAI3)
+#define __HAL_RCC_SAI3_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_SAI3EN)   == 0U)
+#endif /*SAI3*/
+#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED()         ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) == 0U)
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_IS_CLK_DISABLED()         ((RCC->APB2ENR & RCC_APB2ENR_HRTIMEN)  == 0U)
+#endif /*HRTIM1*/
+
+/** @brief  Enable or disable the APB4 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_SYSCFG_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_LPUART1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_SPI6_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_I2C4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_LPTIM2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_LPTIM3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* LPTIM4 */
+
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* LPTIM5 */
+
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DAC2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DAC2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /*  DAC2 */
+
+#define __HAL_RCC_COMP12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_VREF_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SAI4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SAI4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* SAI4 */
+
+#define __HAL_RCC_RTC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(DTS)
+#define __HAL_RCC_DTS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DTSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DTSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /*DTS*/
+
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DFSDM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DFSDM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /*DFSDM2*/
+
+#define __HAL_RCC_SYSCFG_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN)
+#define __HAL_RCC_LPUART1_CLK_DISABLE()          (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN)
+#define __HAL_RCC_SPI6_CLK_DISABLE()             (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN)
+#define __HAL_RCC_I2C4_CLK_DISABLE()             (RCC->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN)
+#define __HAL_RCC_LPTIM2_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN)
+#define __HAL_RCC_LPTIM3_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN)
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN)
+#endif /*LPTIM4*/
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN)
+#endif /*LPTIM5*/
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_CLK_DISABLE()             (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DAC2EN)
+#endif /*DAC2*/
+#define __HAL_RCC_COMP12_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN)
+#define __HAL_RCC_VREF_CLK_DISABLE()             (RCC->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN)
+#define __HAL_RCC_RTC_CLK_DISABLE()              (RCC->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN)
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_CLK_DISABLE()             (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN)
+#endif /*SAI4*/
+#if defined(DTS)
+#define __HAL_RCC_DTS_CLK_DISABLE()              (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DTSEN)
+#endif /*DTS*/
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DFSDM2EN)
+#endif /*DFSDM2*/
+
+/** @brief  Get the enable or disable status of the APB4 peripheral clock
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED()            ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN)  != 0U)
+#define __HAL_RCC_LPUART1_IS_CLK_ENABLED()           ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) != 0U)
+#define __HAL_RCC_SPI6_IS_CLK_ENABLED()              ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN)    != 0U)
+#define __HAL_RCC_I2C4_IS_CLK_ENABLED()              ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN)    != 0U)
+#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED()            ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN)  != 0U)
+#define __HAL_RCC_LPTIM3_IS_CLK_ENABLED()            ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN)  != 0U)
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_IS_CLK_ENABLED()            ((RCC->APB4ENR & RCC_APB4ENR_LPTIM4EN)  != 0U)
+#endif /*LPTIM4*/
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_IS_CLK_ENABLED()            ((RCC->APB4ENR & RCC_APB4ENR_LPTIM5EN)  != 0U)
+#endif /*LPTIM5*/
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_IS_CLK_ENABLED()              ((RCC->APB4ENR & RCC_APB4ENR_DAC2EN)  != 0U)
+#endif /*DAC2*/
+#define __HAL_RCC_COMP12_IS_CLK_ENABLED()            ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN)  != 0U)
+#define __HAL_RCC_VREF_IS_CLK_ENABLED()              ((RCC->APB4ENR & RCC_APB4ENR_VREFEN)    != 0U)
+#define __HAL_RCC_RTC_IS_CLK_ENABLED()               ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN)  != 0U)
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_IS_CLK_ENABLED()              ((RCC->APB4ENR & RCC_APB4ENR_SAI4EN)    != 0U)
+#endif /*SAI4*/
+#if defined(DTS)
+#define __HAL_RCC_DTS_IS_CLK_ENABLED()               ((RCC->APB4ENR & RCC_APB4ENR_DTSEN)    != 0U)
+#endif /*DTS*/
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_IS_CLK_ENABLED()              ((RCC->APB4ENR & RCC_APB4ENR_DFSDM2EN)    != 0U)
+#endif /*DFSDM2*/
+
+#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED()           ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN)  == 0U)
+#define __HAL_RCC_LPUART1_IS_CLK_DISABLED()          ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) == 0U)
+#define __HAL_RCC_SPI6_IS_CLK_DISABLED()             ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN)    == 0U)
+#define __HAL_RCC_I2C4_IS_CLK_DISABLED()             ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN)    == 0U)
+#define __HAL_RCC_LPTIM2_IS_CLK_DISABLED()           ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN)  == 0U)
+#define __HAL_RCC_LPTIM3_IS_CLK_DISABLED()           ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN)  == 0U)
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_IS_CLK_DISABLED()           ((RCC->APB4ENR & RCC_APB4ENR_LPTIM4EN)  == 0U)
+#endif /*LPTIM4*/
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_IS_CLK_DISABLED()           ((RCC->APB4ENR & RCC_APB4ENR_LPTIM5EN)  == 0U)
+#endif /*LPTIM5*/
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_IS_CLK_DISABLED()             ((RCC->APB4ENR & RCC_APB4ENR_DAC2EN)  == 0U)
+#endif /*DAC2*/
+#define __HAL_RCC_COMP12_IS_CLK_DISABLED()           ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN)  == 0U)
+#define __HAL_RCC_VREF_IS_CLK_DISABLED()             ((RCC->APB4ENR & RCC_APB4ENR_VREFEN)    == 0U)
+#define __HAL_RCC_RTC_IS_CLK_DISABLED()              ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN)  == 0U)
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_IS_CLK_DISABLED()             ((RCC->APB4ENR & RCC_APB4ENR_SAI4EN)    == 0U)
+#endif /*SAI4*/
+#if defined(DTS)
+#define __HAL_RCC_DTS_IS_CLK_DISABLED()              ((RCC->APB4ENR & RCC_APB4ENR_DTSEN)    == 0U)
+#endif /*DTS*/
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_IS_CLK_DISABLED()          ((RCC->APB4ENR & RCC_APB4ENR_DFSDM2EN)    == 0U)
+#endif /*DFSDM2*/
+
+#if defined(DUAL_CORE)
+
+/* Exported macros for RCC_C1 -------------------------------------------------*/
+
+/** @brief  Enable or disable the AHB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C1_MDMA_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_DMA2D_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_JPGDECEN_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_C1_FMC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_QSPI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SDMMC1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+
+
+#define __HAL_RCC_C1_MDMA_CLK_DISABLE()            (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN))
+#define __HAL_RCC_C1_DMA2D_CLK_DISABLE()           (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN))
+#define __HAL_RCC_C1_JPGDECEN_CLK_DISABLE()        (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN))
+#define __HAL_RCC_C1_FMC_CLK_DISABLE()             (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))
+#define __HAL_RCC_C1_QSPI_CLK_DISABLE()            (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN))
+#define __HAL_RCC_C1_SDMMC1_CLK_DISABLE()          (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN))
+
+
+
+
+/** @brief  Enable or disable the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C1_DMA1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_DMA2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_ADC12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_ART_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ARTEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ARTEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_ETH1MAC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_ETH1TX_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_ETH1RX_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_C1_USB1_OTG_HS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_USB2_OTG_FS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_DMA1_CLK_DISABLE()             (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN))
+#define __HAL_RCC_C1_DMA2_CLK_DISABLE()             (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN))
+#define __HAL_RCC_C1_ADC12_CLK_DISABLE()            (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN))
+#define __HAL_RCC_C1_ART_CLK_DISABLE()              (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN))
+#define __HAL_RCC_C1_ETH1MAC_CLK_DISABLE()          (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN))
+#define __HAL_RCC_C1_ETH1TX_CLK_DISABLE()           (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN))
+#define __HAL_RCC_C1_ETH1RX_CLK_DISABLE()           (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN))
+#define __HAL_RCC_C1_USB1_OTG_HS_CLK_DISABLE()      (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN))
+#define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN))
+#define __HAL_RCC_C1_USB2_OTG_FS_CLK_DISABLE()      (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN))
+#define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN))
+
+/** @brief  Enable or disable the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C1_DCMI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#if defined(CRYP)
+#define __HAL_RCC_C1_CRYP_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* CRYP */
+
+#if defined(HASH)
+#define __HAL_RCC_C1_HASH_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* HASH */
+
+#define __HAL_RCC_C1_RNG_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SDMMC2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_D2SRAM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_D2SRAM2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_D2SRAM3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_DCMI_CLK_DISABLE()             (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))
+#if defined(CRYP)
+#define __HAL_RCC_C1_CRYP_CLK_DISABLE()             (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_C1_HASH_CLK_DISABLE()             (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))
+#endif /* HASH */
+#define __HAL_RCC_C1_RNG_CLK_DISABLE()              (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))
+#define __HAL_RCC_C1_SDMMC2_CLK_DISABLE()           (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))
+#define __HAL_RCC_C1_D2SRAM1_CLK_DISABLE()          (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN))
+#define __HAL_RCC_C1_D2SRAM2_CLK_DISABLE()          (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN))
+#define __HAL_RCC_C1_D2SRAM3_CLK_DISABLE()          (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN))
+
+/** @brief  Enable or disable the AHB4 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C1_GPIOA_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_GPIOB_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_GPIOC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_GPIOD_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_GPIOE_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_GPIOF_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_GPIOG_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_GPIOH_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_GPIOI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_GPIOJ_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_GPIOK_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_CRC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_CRCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_CRCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_BDMA_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_ADC3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_HSEM_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_BKPRAM_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_C1_GPIOA_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN)
+#define __HAL_RCC_C1_GPIOB_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN)
+#define __HAL_RCC_C1_GPIOC_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN)
+#define __HAL_RCC_C1_GPIOD_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN)
+#define __HAL_RCC_C1_GPIOE_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN)
+#define __HAL_RCC_C1_GPIOF_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN)
+#define __HAL_RCC_C1_GPIOG_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN)
+#define __HAL_RCC_C1_GPIOH_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN)
+#define __HAL_RCC_C1_GPIOI_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN)
+#define __HAL_RCC_C1_GPIOJ_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN)
+#define __HAL_RCC_C1_GPIOK_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN)
+#define __HAL_RCC_C1_CRC_CLK_DISABLE()             (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN)
+#define __HAL_RCC_C1_BDMA_CLK_DISABLE()            (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN)
+#define __HAL_RCC_C1_ADC3_CLK_DISABLE()            (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN)
+#define __HAL_RCC_C1_HSEM_CLK_DISABLE()            (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN)
+#define __HAL_RCC_C1_BKPRAM_CLK_DISABLE()          (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN)
+
+
+/** @brief  Enable or disable the APB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C1_LTDC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_LTDCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_LTDCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_DSI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_DSIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_DSIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_WWDG1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_WWDG1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_WWDG1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_LTDC_CLK_DISABLE()           (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN)
+#define __HAL_RCC_C1_DSI_CLK_DISABLE()            (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN)
+#define __HAL_RCC_C1_WWDG1_CLK_DISABLE()          (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN)
+
+/** @brief  Enable or disable the APB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C1_TIM2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM6_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM6EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM6EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM7_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM7EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM7EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM13_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM13EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM13EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM14_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM14EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM14EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_LPTIM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_WWDG2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_WWDG2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_WWDG2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SPI2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SPI3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SPDIFRX_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_USART2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_USART3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_UART4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_UART5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_I2C1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_I2C2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_I2C3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_CEC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_CECEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_CECEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_DAC12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_DAC12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_DAC12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_UART7_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART7EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART7EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_UART8_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART8EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART8EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_CRS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_CRSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_CRSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SWPMI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_SWPMIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_SWPMIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_OPAMP_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_OPAMPEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_OPAMPEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_MDIOS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_MDIOSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_MDIOSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_FDCAN_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_FDCANEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_FDCANEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_C1_TIM2_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN)
+#define __HAL_RCC_C1_TIM3_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN)
+#define __HAL_RCC_C1_TIM4_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN)
+#define __HAL_RCC_C1_TIM5_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN)
+#define __HAL_RCC_C1_TIM6_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN)
+#define __HAL_RCC_C1_TIM7_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN)
+#define __HAL_RCC_C1_TIM12_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN)
+#define __HAL_RCC_C1_TIM13_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN)
+#define __HAL_RCC_C1_TIM14_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN)
+#define __HAL_RCC_C1_LPTIM1_CLK_DISABLE()         (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN)
+#define __HAL_RCC_C1_WWDG2_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN)
+#define __HAL_RCC_C1_SPI2_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN)
+#define __HAL_RCC_C1_SPI3_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN)
+#define __HAL_RCC_C1_SPDIFRX_CLK_DISABLE()        (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN)
+#define __HAL_RCC_C1_USART2_CLK_DISABLE()         (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN)
+#define __HAL_RCC_C1_USART3_CLK_DISABLE()         (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN)
+#define __HAL_RCC_C1_UART4_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN)
+#define __HAL_RCC_C1_UART5_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN)
+#define __HAL_RCC_C1_I2C1_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN)
+#define __HAL_RCC_C1_I2C2_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN)
+#define __HAL_RCC_C1_I2C3_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN)
+#define __HAL_RCC_C1_CEC_CLK_DISABLE()            (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_CECEN)
+#define __HAL_RCC_C1_DAC12_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN)
+#define __HAL_RCC_C1_UART7_CLK_DISABLE()         (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN)
+#define __HAL_RCC_C1_UART8_CLK_DISABLE()         (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN)
+#define __HAL_RCC_C1_CRS_CLK_DISABLE()            (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN)
+#define __HAL_RCC_C1_SWPMI_CLK_DISABLE()          (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN)
+#define __HAL_RCC_C1_OPAMP_CLK_DISABLE()          (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN)
+#define __HAL_RCC_C1_MDIOS_CLK_DISABLE()          (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN)
+#define __HAL_RCC_C1_FDCAN_CLK_DISABLE()          (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN)
+
+/** @brief  Enable or disable the APB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C1_TIM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM8_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM8EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM8EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_USART1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_USART6_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART6EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART6EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SPI1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SPI4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM15_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM15EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM15EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM16_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM16EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM16EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM17_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM17EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM17EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SPI5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SAI1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SAI2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SAI3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_DFSDM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_HRTIM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_HRTIMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_HRTIMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_TIM1_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)
+#define __HAL_RCC_C1_TIM8_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)
+#define __HAL_RCC_C1_USART1_CLK_DISABLE()         (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)
+#define __HAL_RCC_C1_USART6_CLK_DISABLE()         (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)
+#define __HAL_RCC_C1_SPI1_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)
+#define __HAL_RCC_C1_SPI4_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)
+#define __HAL_RCC_C1_TIM15_CLK_DISABLE()          (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)
+#define __HAL_RCC_C1_TIM16_CLK_DISABLE()          (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)
+#define __HAL_RCC_C1_TIM17_CLK_DISABLE()          (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)
+#define __HAL_RCC_C1_SPI5_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)
+#define __HAL_RCC_C1_SAI1_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)
+#define __HAL_RCC_C1_SAI2_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN)
+#define __HAL_RCC_C1_SAI3_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN)
+#define __HAL_RCC_C1_DFSDM1_CLK_DISABLE()         (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)
+#define __HAL_RCC_C1_HRTIM1_CLK_DISABLE()         (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN)
+
+/** @brief  Enable or disable the APB4 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C1_SYSCFG_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_LPUART1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPUART1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPUART1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SPI6_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SPI6EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SPI6EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_I2C4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_I2C4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_I2C4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_LPTIM2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_LPTIM3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_LPTIM4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_LPTIM5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_COMP12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_COMP12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_COMP12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_C1_VREF_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_VREFEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_VREFEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_RTC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C1_SAI4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SAI4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SAI4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_C1_SYSCFG_CLK_DISABLE()           (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN)
+#define __HAL_RCC_C1_LPUART1_CLK_DISABLE()          (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN)
+#define __HAL_RCC_C1_SPI6_CLK_DISABLE()             (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN)
+#define __HAL_RCC_C1_I2C4_CLK_DISABLE()             (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN)
+#define __HAL_RCC_C1_LPTIM2_CLK_DISABLE()           (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN)
+#define __HAL_RCC_C1_LPTIM3_CLK_DISABLE()           (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN)
+#define __HAL_RCC_C1_LPTIM4_CLK_DISABLE()           (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN)
+#define __HAL_RCC_C1_LPTIM5_CLK_DISABLE()           (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN)
+#define __HAL_RCC_C1_COMP12_CLK_DISABLE()           (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN)
+#define __HAL_RCC_C1_VREF_CLK_DISABLE()             (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN)
+#define __HAL_RCC_C1_RTC_CLK_DISABLE()              (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN)
+#define __HAL_RCC_C1_SAI4_CLK_DISABLE()             (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN)
+
+/* Exported macros for RCC_C2 -------------------------------------------------*/
+
+/** @brief  Enable or disable the AHB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+
+#define __HAL_RCC_C2_MDMA_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_DMA2D_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_JPGDECEN_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_FLASH_C2_ALLOCATE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FLASHEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FLASHEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_DTCM1_C2_ALLOCATE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_DTCM2_C2_ALLOCATE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_ITCM_C2_ALLOCATE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_ITCMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_ITCMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_D1SRAM1_C2_ALLOCATE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_AXISRAMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_AXISRAMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_FMC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_QSPI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SDMMC1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+
+
+#define __HAL_RCC_C2_MDMA_CLK_DISABLE()            (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN))
+#define __HAL_RCC_C2_DMA2D_CLK_DISABLE()           (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN))
+#define __HAL_RCC_C2_JPGDECEN_CLK_DISABLE()        (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN))
+#define __HAL_RCC_C2_FMC_CLK_DISABLE()             (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))
+#define __HAL_RCC_C2_QSPI_CLK_DISABLE()            (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN))
+#define __HAL_RCC_C2_SDMMC1_CLK_DISABLE()          (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN))
+#define __HAL_RCC_FLASH_C2_DEALLOCATE()            (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_FLASHEN))
+#define __HAL_RCC_DTCM1_C2_DEALLOCATE()            (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DTCM1EN))
+#define __HAL_RCC_DTCM2_C2_DEALLOCATE()            (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DTCM2EN))
+#define __HAL_RCC_ITCM_C2_DEALLOCATE()             (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_ITCMEN))
+#define __HAL_RCC_D1SRAM1_C2_DEALLOCATE()          (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_AXISRAMEN))
+
+/** @brief  Enable or disable the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C2_DMA1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_DMA2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_ADC12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_ART_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ARTEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ARTEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_ETH1MAC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_ETH1TX_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_ETH1RX_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_USB1_OTG_HS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_USB2_OTG_FS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_C2_DMA1_CLK_DISABLE()             (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN))
+#define __HAL_RCC_C2_DMA2_CLK_DISABLE()             (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN))
+#define __HAL_RCC_C2_ADC12_CLK_DISABLE()            (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN))
+#define __HAL_RCC_C2_ART_CLK_DISABLE()              (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN))
+#define __HAL_RCC_C2_ETH1MAC_CLK_DISABLE()          (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN))
+#define __HAL_RCC_C2_ETH1TX_CLK_DISABLE()           (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN))
+#define __HAL_RCC_C2_ETH1RX_CLK_DISABLE()           (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN))
+#define __HAL_RCC_C2_USB1_OTG_HS_CLK_DISABLE()      (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN))
+#define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN))
+#define __HAL_RCC_C2_USB2_OTG_FS_CLK_DISABLE()      (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN))
+#define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN))
+
+/** @brief  Enable or disable the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C2_DCMI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#if defined(CRYP)
+#define __HAL_RCC_C2_CRYP_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* CRYP */
+
+#if defined(HASH)
+#define __HAL_RCC_C2_HASH_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+#endif /* HASH */
+
+#define __HAL_RCC_C2_RNG_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SDMMC2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_D2SRAM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_D2SRAM2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_D2SRAM3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_DCMI_CLK_DISABLE()             (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))
+#if defined(CRYP)
+#define __HAL_RCC_C2_CRYP_CLK_DISABLE()             (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_C2_HASH_CLK_DISABLE()             (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))
+#endif /* HASH */
+#define __HAL_RCC_C2_RNG_CLK_DISABLE()              (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))
+#define __HAL_RCC_C2_SDMMC2_CLK_DISABLE()           (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))
+#define __HAL_RCC_C2_D2SRAM1_CLK_DISABLE()          (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN))
+#define __HAL_RCC_C2_D2SRAM2_CLK_DISABLE()          (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN))
+#define __HAL_RCC_C2_D2SRAM3_CLK_DISABLE()          (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN))
+
+/** @brief  Enable or disable the AHB4 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C2_GPIOA_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_GPIOB_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_GPIOC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_GPIOD_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_GPIOE_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_GPIOF_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_GPIOG_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_GPIOH_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_GPIOI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_GPIOJ_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_GPIOK_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_CRC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_CRCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_CRCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_BDMA_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_ADC3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_HSEM_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_BKPRAM_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_C2_GPIOA_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN)
+#define __HAL_RCC_C2_GPIOB_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN)
+#define __HAL_RCC_C2_GPIOC_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN)
+#define __HAL_RCC_C2_GPIOD_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN)
+#define __HAL_RCC_C2_GPIOE_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN)
+#define __HAL_RCC_C2_GPIOF_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN)
+#define __HAL_RCC_C2_GPIOG_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN)
+#define __HAL_RCC_C2_GPIOH_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN)
+#define __HAL_RCC_C2_GPIOI_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN)
+#define __HAL_RCC_C2_GPIOJ_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN)
+#define __HAL_RCC_C2_GPIOK_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN)
+#define __HAL_RCC_C2_CRC_CLK_DISABLE()             (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN)
+#define __HAL_RCC_C2_BDMA_CLK_DISABLE()            (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN)
+#define __HAL_RCC_C2_ADC3_CLK_DISABLE()            (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN)
+#define __HAL_RCC_C2_HSEM_CLK_DISABLE()            (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN)
+#define __HAL_RCC_C2_BKPRAM_CLK_DISABLE()          (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN)
+
+
+/** @brief  Enable or disable the APB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C2_LTDC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_LTDCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_LTDCEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_DSI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_DSIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_DSIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_WWDG1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_WWDG1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_WWDG1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_LTDC_CLK_DISABLE()           (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN)
+#define __HAL_RCC_C2_DSI_CLK_DISABLE()            (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN)
+#define __HAL_RCC_C2_WWDG1_CLK_DISABLE()          (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN)
+
+/** @brief  Enable or disable the APB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C2_TIM2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM6_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM6EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM6EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM7_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM7EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM7EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM13_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM13EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM13EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM14_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM14EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM14EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_LPTIM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_WWDG2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_WWDG2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_WWDG2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SPI2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SPI3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SPDIFRX_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_USART2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_USART3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_UART4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_UART5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_I2C1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_I2C2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_I2C3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_CEC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_CECEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_CECEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_DAC12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_DAC12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_DAC12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_UART7_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART7EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART7EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_UART8_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART8EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART8EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_CRS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_CRSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_CRSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SWPMI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_SWPMIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_SWPMIEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_OPAMP_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_OPAMPEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_OPAMPEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_MDIOS_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_MDIOSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_MDIOSEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_FDCAN_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_FDCANEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_FDCANEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+#define __HAL_RCC_C2_TIM2_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN)
+#define __HAL_RCC_C2_TIM3_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN)
+#define __HAL_RCC_C2_TIM4_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN)
+#define __HAL_RCC_C2_TIM5_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN)
+#define __HAL_RCC_C2_TIM6_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN)
+#define __HAL_RCC_C2_TIM7_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN)
+#define __HAL_RCC_C2_TIM12_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN)
+#define __HAL_RCC_C2_TIM13_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN)
+#define __HAL_RCC_C2_TIM14_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN)
+#define __HAL_RCC_C2_LPTIM1_CLK_DISABLE()         (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN)
+#define __HAL_RCC_C2_WWDG2_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN)
+#define __HAL_RCC_C2_SPI2_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN)
+#define __HAL_RCC_C2_SPI3_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN)
+#define __HAL_RCC_C2_SPDIFRX_CLK_DISABLE()        (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN)
+#define __HAL_RCC_C2_USART2_CLK_DISABLE()         (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN)
+#define __HAL_RCC_C2_USART3_CLK_DISABLE()         (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN)
+#define __HAL_RCC_C2_UART4_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN)
+#define __HAL_RCC_C2_UART5_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN)
+#define __HAL_RCC_C2_I2C1_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN)
+#define __HAL_RCC_C2_I2C2_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN)
+#define __HAL_RCC_C2_I2C3_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN)
+#define __HAL_RCC_C2_CEC_CLK_DISABLE()            (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_CECEN)
+#define __HAL_RCC_C2_DAC12_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN)
+#define __HAL_RCC_C2_UART7_CLK_DISABLE()         (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN)
+#define __HAL_RCC_C2_UART8_CLK_DISABLE()         (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN)
+#define __HAL_RCC_C2_CRS_CLK_DISABLE()            (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN)
+#define __HAL_RCC_C2_SWPMI_CLK_DISABLE()          (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN)
+#define __HAL_RCC_C2_OPAMP_CLK_DISABLE()          (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN)
+#define __HAL_RCC_C2_MDIOS_CLK_DISABLE()          (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN)
+#define __HAL_RCC_C2_FDCAN_CLK_DISABLE()          (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN)
+
+/** @brief  Enable or disable the APB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C2_TIM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM8_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM8EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM8EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_USART1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_USART6_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART6EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART6EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SPI1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SPI4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM15_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM15EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM15EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM16_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM16EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM16EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM17_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM17EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM17EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SPI5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SAI1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SAI2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SAI3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_DFSDM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_HRTIM1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_HRTIMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_HRTIMEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_TIM1_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)
+#define __HAL_RCC_C2_TIM8_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)
+#define __HAL_RCC_C2_USART1_CLK_DISABLE()         (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)
+#define __HAL_RCC_C2_USART6_CLK_DISABLE()         (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)
+#define __HAL_RCC_C2_SPI1_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)
+#define __HAL_RCC_C2_SPI4_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)
+#define __HAL_RCC_C2_TIM15_CLK_DISABLE()          (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)
+#define __HAL_RCC_C2_TIM16_CLK_DISABLE()          (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)
+#define __HAL_RCC_C2_TIM17_CLK_DISABLE()          (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)
+#define __HAL_RCC_C2_SPI5_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)
+#define __HAL_RCC_C2_SAI1_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)
+#define __HAL_RCC_C2_SAI2_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN)
+#define __HAL_RCC_C2_SAI3_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN)
+#define __HAL_RCC_C2_DFSDM1_CLK_DISABLE()         (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)
+#define __HAL_RCC_C2_HRTIM1_CLK_DISABLE()         (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN)
+
+/** @brief  Enable or disable the APB4 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  */
+
+#define __HAL_RCC_C2_SYSCFG_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_LPUART1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPUART1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPUART1EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SPI6_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SPI6EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SPI6EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_I2C4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_I2C4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_I2C4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_LPTIM2_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_LPTIM3_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_LPTIM4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_LPTIM5_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_COMP12_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_COMP12EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_COMP12EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_VREF_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_VREFEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_VREFEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_RTC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+#define __HAL_RCC_C2_SAI4_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SAI4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SAI4EN);\
+                                        UNUSED(tmpreg); \
+                                       } while(0)
+
+
+
+#define __HAL_RCC_C2_SYSCFG_CLK_DISABLE()           (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN)
+#define __HAL_RCC_C2_LPUART1_CLK_DISABLE()          (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN)
+#define __HAL_RCC_C2_SPI6_CLK_DISABLE()             (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN)
+#define __HAL_RCC_C2_I2C4_CLK_DISABLE()             (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN)
+#define __HAL_RCC_C2_LPTIM2_CLK_DISABLE()           (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN)
+#define __HAL_RCC_C2_LPTIM3_CLK_DISABLE()           (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN)
+#define __HAL_RCC_C2_LPTIM4_CLK_DISABLE()           (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN)
+#define __HAL_RCC_C2_LPTIM5_CLK_DISABLE()           (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN)
+#define __HAL_RCC_C2_COMP12_CLK_DISABLE()           (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN)
+#define __HAL_RCC_C2_VREF_CLK_DISABLE()             (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN)
+#define __HAL_RCC_C2_RTC_CLK_DISABLE()              (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN)
+#define __HAL_RCC_C2_SAI4_CLK_DISABLE()             (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN)
+
+#endif /*DUAL_CORE*/
+
+/** @brief  Enable or disable the AHB3 peripheral reset.
+  */
+
+#define __HAL_RCC_AHB3_FORCE_RESET()          (RCC->AHB3RSTR = 0x7FFFFFFFU)
+#define __HAL_RCC_MDMA_FORCE_RESET()          (RCC->AHB3RSTR |= (RCC_AHB3RSTR_MDMARST))
+#define __HAL_RCC_DMA2D_FORCE_RESET()         (RCC->AHB3RSTR |= (RCC_AHB3RSTR_DMA2DRST))
+#if defined(JPEG)
+#define __HAL_RCC_JPGDECRST_FORCE_RESET()     (RCC->AHB3RSTR |= (RCC_AHB3RSTR_JPGDECRST))
+#endif /* JPEG */
+#define __HAL_RCC_FMC_FORCE_RESET()           (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_FORCE_RESET()          (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
+#endif /*QUADSPI*/
+#if defined(OCTOSPI1)
+#define __HAL_RCC_OSPI1_FORCE_RESET()         (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OSPI1RST))
+#endif /*OCTOSPI1*/
+#define __HAL_RCC_SDMMC1_FORCE_RESET()        (RCC->AHB3RSTR |= (RCC_AHB3RSTR_SDMMC1RST))
+#if defined(OCTOSPI2)
+#define __HAL_RCC_OSPI2_FORCE_RESET()         (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OSPI2RST))
+#endif /*OCTOSPI2*/
+#if defined(OCTOSPIM)
+#define __HAL_RCC_IOMNGR_FORCE_RESET()      (RCC->AHB3RSTR |= (RCC_AHB3RSTR_IOMNGRRST))
+#endif /*OCTOSPIM*/
+#if defined(OTFDEC1)
+#define __HAL_RCC_OTFDEC1_FORCE_RESET()         (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OTFDEC1RST))
+#endif /*OTFDEC1*/
+#if defined(OTFDEC2)
+#define __HAL_RCC_OTFDEC2_FORCE_RESET()         (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OTFDEC2RST))
+#endif /*OTFDEC2*/
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_FORCE_RESET()        (RCC->AHB3RSTR |= (RCC_AHB3RSTR_GFXMMURST))
+#endif /*GFXMMU*/
+
+#define __HAL_RCC_AHB3_RELEASE_RESET()        (RCC->AHB3RSTR = 0x00)
+#define __HAL_RCC_MDMA_RELEASE_RESET()        (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_MDMARST))
+#define __HAL_RCC_DMA2D_RELEASE_RESET()       (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_DMA2DRST))
+#if defined(JPEG)
+#define __HAL_RCC_JPGDECRST_RELEASE_RESET()   (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_JPGDECRST))
+#endif /* JPEG */
+#define __HAL_RCC_FMC_RELEASE_RESET()         (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_FMCRST))
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_RELEASE_RESET()        (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_QSPIRST))
+#endif /*QUADSPI*/
+#if defined(OCTOSPI1)
+#define __HAL_RCC_OSPI1_RELEASE_RESET()       (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OSPI1RST))
+#endif /*OCTOSPI1*/
+#define __HAL_RCC_SDMMC1_RELEASE_RESET()      (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_SDMMC1RST))
+#if defined(OCTOSPI2)
+#define __HAL_RCC_OSPI2_RELEASE_RESET()       (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OSPI2RST))
+#endif /*OCTOSPI2*/
+#if defined(OCTOSPIM)
+#define __HAL_RCC_IOMNGR_RELEASE_RESET()      (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_IOMNGRRST))
+#endif /*OCTOSPIM*/
+#if defined(OTFDEC1)
+#define __HAL_RCC_OTFDEC1_RELEASE_RESET()       (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OTFDEC1RST))
+#endif /*OTFDEC1*/
+#if defined(OTFDEC2)
+#define __HAL_RCC_OTFDEC2_RELEASE_RESET()       (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OTFDEC2RST))
+#endif /*OTFDEC2*/
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_RELEASE_RESET()      (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_GFXMMURST))
+#endif /*GFXMMU*/
+
+
+
+/** @brief  Force or release the AHB1 peripheral reset.
+  */
+#define __HAL_RCC_AHB1_FORCE_RESET()             (RCC->AHB1RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_DMA1_FORCE_RESET()             (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
+#define __HAL_RCC_DMA2_FORCE_RESET()             (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
+#define __HAL_RCC_ADC12_FORCE_RESET()            (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ADC12RST))
+#if defined(DUAL_CORE)
+#define __HAL_RCC_ART_FORCE_RESET()              (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ARTRST))
+#endif /*DUAL_CORE*/
+#if defined(RCC_AHB1RSTR_CRCRST)
+#define __HAL_RCC_CRC_FORCE_RESET()            (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
+#endif
+#if defined(ETH)
+#define __HAL_RCC_ETH1MAC_FORCE_RESET()          (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETH1MACRST))
+#endif /*ETH*/
+#define __HAL_RCC_USB1_OTG_HS_FORCE_RESET()      (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB1OTGHSRST))
+#if defined(USB2_OTG_FS)
+#define __HAL_RCC_USB2_OTG_FS_FORCE_RESET()      (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB2OTGHSRST))
+#endif /*USB2_OTG_FS*/
+
+#define __HAL_RCC_AHB1_RELEASE_RESET()           (RCC->AHB1RSTR = 0x00U)
+#define __HAL_RCC_DMA1_RELEASE_RESET()             (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA1RST))
+#define __HAL_RCC_DMA2_RELEASE_RESET()             (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA2RST))
+#define __HAL_RCC_ADC12_RELEASE_RESET()            (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ADC12RST))
+#if defined(DUAL_CORE)
+#define __HAL_RCC_ART_RELEASE_RESET()              (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ARTRST))
+#endif /*DUAL_CORE*/
+#if defined(RCC_AHB1RSTR_CRCRST)
+#define __HAL_RCC_CRC_RELEASE_RESET()                (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_CRCRST))
+#endif
+#if defined(ETH)
+#define __HAL_RCC_ETH1MAC_RELEASE_RESET()          (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ETH1MACRST))
+#endif /*ETH*/
+#define __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()      (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB1OTGHSRST))
+#if defined(USB2_OTG_FS)
+#define __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()      (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB2OTGHSRST))
+#endif /*USB2_OTG_FS*/
+
+/** @brief  Force or release the AHB2 peripheral reset.
+  */
+#define __HAL_RCC_AHB2_FORCE_RESET()           (RCC->AHB2RSTR = 0xFFFFFFFFU)
+#if defined(DCMI) && defined(PSSI)
+#define __HAL_RCC_DCMI_PSSI_FORCE_RESET()        (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMI_PSSIRST))
+#define __HAL_RCC_DCMI_FORCE_RESET()             __HAL_RCC_DCMI_PSSI_FORCE_RESET()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_DCMI_FORCE_RESET()             (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
+#endif /* DCMI && PSSI */
+#if defined(CRYP)
+#define __HAL_RCC_CRYP_FORCE_RESET()             (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_HASH_FORCE_RESET()             (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
+#endif /* HASH */
+#define __HAL_RCC_RNG_FORCE_RESET()              (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
+#define __HAL_RCC_SDMMC2_FORCE_RESET()           (RCC->AHB2RSTR |= (RCC_AHB2RSTR_SDMMC2RST))
+#if defined(RCC_AHB2RSTR_HSEMRST)
+#define __HAL_RCC_HSEM_FORCE_RESET()             (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HSEMRST))
+#endif
+#if defined(BDMA1)
+#define __HAL_RCC_BDMA1_FORCE_RESET()           (RCC->AHB2RSTR |= (RCC_AHB2RSTR_BDMA1RST))
+#endif /*BDMA1*/
+
+#define __HAL_RCC_AHB2_RELEASE_RESET()           (RCC->AHB2RSTR = 0x00U)
+#if defined(DCMI) && defined(PSSI)
+#define __HAL_RCC_DCMI_PSSI_RELEASE_RESET()        (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMI_PSSIRST))
+#define __HAL_RCC_DCMI_RELEASE_RESET()             __HAL_RCC_DCMI_PSSI_RELEASE_RESET()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_DCMI_RELEASE_RESET()             (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMIRST))
+#endif /* DCMI && PSSI */
+#if defined(CRYP)
+#define __HAL_RCC_CRYP_RELEASE_RESET()             (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_CRYPRST))
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_HASH_RELEASE_RESET()             (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HASHRST))
+#endif /* HASH */
+#define __HAL_RCC_RNG_RELEASE_RESET()              (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_RNGRST))
+#define __HAL_RCC_SDMMC2_RELEASE_RESET()           (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_SDMMC2RST))
+#if defined(RCC_AHB2RSTR_HSEMRST)
+#define __HAL_RCC_HSEM_RELEASE_RESET()             (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HSEMRST))
+#endif
+#if defined(BDMA1)
+#define __HAL_RCC_BDMA1_RELEASE_RESET()           (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_BDMA1RST))
+#endif /*BDMA1*/
+
+
+/** @brief  Force or release the AHB4 peripheral reset.
+  */
+
+#define __HAL_RCC_AHB4_FORCE_RESET()            (RCC->AHB4RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_GPIOA_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOARST)
+#define __HAL_RCC_GPIOB_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOBRST)
+#define __HAL_RCC_GPIOC_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOCRST)
+#define __HAL_RCC_GPIOD_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIODRST)
+#define __HAL_RCC_GPIOE_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOERST)
+#define __HAL_RCC_GPIOF_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOFRST)
+#define __HAL_RCC_GPIOG_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOGRST)
+#define __HAL_RCC_GPIOH_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOHRST)
+#define __HAL_RCC_GPIOI_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOIRST)
+#define __HAL_RCC_GPIOJ_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOJRST)
+#define __HAL_RCC_GPIOK_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOKRST)
+#if defined(RCC_AHB4RSTR_CRCRST)
+#define __HAL_RCC_CRC_FORCE_RESET()             (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_CRCRST)
+#endif
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_BDMA2RST)
+#define __HAL_RCC_BDMA_FORCE_RESET()            __HAL_RCC_BDMA2_FORCE_RESET()         /* for API backward compatibility*/
+#else
+#define __HAL_RCC_BDMA_FORCE_RESET()            (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_BDMARST)
+#endif /*BDMA2*/
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_FORCE_RESET()            (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_ADC3RST)
+#endif /*ADC3*/
+#if defined(RCC_AHB4RSTR_HSEMRST)
+#define __HAL_RCC_HSEM_FORCE_RESET()            (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_HSEMRST)
+#endif
+
+#define __HAL_RCC_AHB4_RELEASE_RESET()          (RCC->AHB4RSTR = 0x00U)
+#define __HAL_RCC_GPIOA_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOARST)
+#define __HAL_RCC_GPIOB_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOBRST)
+#define __HAL_RCC_GPIOC_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOCRST)
+#define __HAL_RCC_GPIOD_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIODRST)
+#define __HAL_RCC_GPIOE_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOERST)
+#define __HAL_RCC_GPIOF_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOFRST)
+#define __HAL_RCC_GPIOG_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOGRST)
+#define __HAL_RCC_GPIOH_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOHRST)
+#define __HAL_RCC_GPIOI_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOIRST)
+#define __HAL_RCC_GPIOJ_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOJRST)
+#define __HAL_RCC_GPIOK_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOKRST)
+#if defined(RCC_AHB4RSTR_CRCRST)
+#define __HAL_RCC_CRC_RELEASE_RESET()             (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_CRCRST)
+#endif
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_RELEASE_RESET()            (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_BDMA2RST)
+#define __HAL_RCC_BDMA_RELEASE_RESET()   __HAL_RCC_BDMA2_RELEASE_RESET()      /* for API backward compatibility*/
+#else
+#define __HAL_RCC_BDMA_RELEASE_RESET()            (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_BDMARST)
+#endif /*BDMA2*/
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_RELEASE_RESET()            (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_ADC3RST)
+#endif /*ADC3*/
+#if defined(RCC_AHB4RSTR_HSEMRST)
+#define __HAL_RCC_HSEM_RELEASE_RESET()            (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_HSEMRST)
+#endif
+
+/** @brief  Force or release the APB3 peripheral reset.
+  */
+#define __HAL_RCC_APB3_FORCE_RESET()         (RCC->APB3RSTR = 0xFFFFFFFFU)
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_FORCE_RESET()           (RCC->APB3RSTR) |= (RCC_APB3RSTR_LTDCRST)
+#endif /* LTDC */
+#if defined(DSI)
+#define __HAL_RCC_DSI_FORCE_RESET()            (RCC->APB3RSTR) |= (RCC_APB3RSTR_DSIRST)
+#endif /*DSI*/
+
+#define __HAL_RCC_APB3_RELEASE_RESET()         (RCC->APB3RSTR = 0x00U)
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_RELEASE_RESET()           (RCC->APB3RSTR) &= ~ (RCC_APB3RSTR_LTDCRST)
+#endif /* LTDC */
+#if defined(DSI)
+#define __HAL_RCC_DSI_RELEASE_RESET()            (RCC->APB3RSTR) &= ~ (RCC_APB3RSTR_DSIRST)
+#endif /*DSI*/
+
+/** @brief  Force or release the APB1 peripheral reset.
+  */
+#define __HAL_RCC_APB1L_FORCE_RESET()        (RCC->APB1LRSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_APB1H_FORCE_RESET()        (RCC->APB1HRSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_TIM2_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM2RST)
+#define __HAL_RCC_TIM3_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM3RST)
+#define __HAL_RCC_TIM4_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM4RST)
+#define __HAL_RCC_TIM5_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM5RST)
+#define __HAL_RCC_TIM6_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM6RST)
+#define __HAL_RCC_TIM7_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM7RST)
+#define __HAL_RCC_TIM12_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM12RST)
+#define __HAL_RCC_TIM13_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM13RST)
+#define __HAL_RCC_TIM14_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM14RST)
+#define __HAL_RCC_LPTIM1_FORCE_RESET()         (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_LPTIM1RST)
+#define __HAL_RCC_SPI2_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI2RST)
+#define __HAL_RCC_SPI3_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI3RST)
+#define __HAL_RCC_SPDIFRX_FORCE_RESET()        (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPDIFRXRST)
+#define __HAL_RCC_USART2_FORCE_RESET()         (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART2RST)
+#define __HAL_RCC_USART3_FORCE_RESET()         (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART3RST)
+#define __HAL_RCC_UART4_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART4RST)
+#define __HAL_RCC_UART5_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART5RST)
+#define __HAL_RCC_I2C1_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C1RST)
+#define __HAL_RCC_I2C2_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C2RST)
+#define __HAL_RCC_I2C3_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C3RST)
+#define __HAL_RCC_CEC_FORCE_RESET()            (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_CECRST)
+#define __HAL_RCC_DAC12_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_DAC12RST)
+#define __HAL_RCC_UART7_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART7RST)
+#define __HAL_RCC_UART8_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART8RST)
+#define __HAL_RCC_CRS_FORCE_RESET()            (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_CRSRST)
+#define __HAL_RCC_SWPMI1_FORCE_RESET()          (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_SWPMIRST)
+#define __HAL_RCC_OPAMP_FORCE_RESET()          (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_OPAMPRST)
+#define __HAL_RCC_MDIOS_FORCE_RESET()          (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_MDIOSRST)
+#define __HAL_RCC_FDCAN_FORCE_RESET()          (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_FDCANRST)
+
+#define __HAL_RCC_APB1L_RELEASE_RESET()       (RCC->APB1LRSTR = 0x00U)
+#define __HAL_RCC_APB1H_RELEASE_RESET()       (RCC->APB1HRSTR = 0x00U)
+#define __HAL_RCC_TIM2_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM2RST)
+#define __HAL_RCC_TIM3_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM3RST)
+#define __HAL_RCC_TIM4_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM4RST)
+#define __HAL_RCC_TIM5_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM5RST)
+#define __HAL_RCC_TIM6_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM6RST)
+#define __HAL_RCC_TIM7_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM7RST)
+#define __HAL_RCC_TIM12_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM12RST)
+#define __HAL_RCC_TIM13_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM13RST)
+#define __HAL_RCC_TIM14_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM14RST)
+#define __HAL_RCC_LPTIM1_RELEASE_RESET()         (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_LPTIM1RST)
+#define __HAL_RCC_SPI2_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI2RST)
+#define __HAL_RCC_SPI3_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI3RST)
+#define __HAL_RCC_SPDIFRX_RELEASE_RESET()        (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPDIFRXRST)
+#define __HAL_RCC_USART2_RELEASE_RESET()         (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART2RST)
+#define __HAL_RCC_USART3_RELEASE_RESET()         (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART3RST)
+#define __HAL_RCC_UART4_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART4RST)
+#define __HAL_RCC_UART5_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART5RST)
+#define __HAL_RCC_I2C1_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C1RST)
+#define __HAL_RCC_I2C2_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C2RST)
+#define __HAL_RCC_I2C3_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C3RST)
+#define __HAL_RCC_CEC_RELEASE_RESET()            (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_CECRST)
+#define __HAL_RCC_DAC12_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_DAC12RST)
+#define __HAL_RCC_UART7_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART7RST)
+#define __HAL_RCC_UART8_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART8RST)
+#define __HAL_RCC_CRS_RELEASE_RESET()            (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_CRSRST)
+#define __HAL_RCC_SWPMI1_RELEASE_RESET()          (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_SWPMIRST)
+#define __HAL_RCC_OPAMP_RELEASE_RESET()          (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_OPAMPRST)
+#define __HAL_RCC_MDIOS_RELEASE_RESET()          (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_MDIOSRST)
+#define __HAL_RCC_FDCAN_RELEASE_RESET()          (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_FDCANRST)
+
+/** @brief  Force or release the APB2 peripheral reset.
+  */
+#define __HAL_RCC_APB2_FORCE_RESET()         (RCC->APB2RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_TIM1_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM1RST)
+#define __HAL_RCC_TIM8_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM8RST)
+#define __HAL_RCC_USART1_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART1RST)
+#define __HAL_RCC_USART6_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART6RST)
+#if defined(UART9)
+#define __HAL_RCC_UART9_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_UART9RST)
+#endif /*UART9*/
+#if defined(USART10)
+#define __HAL_RCC_USART10_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART10RST)
+#endif /*USART10*/
+#define __HAL_RCC_SPI1_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI1RST)
+#define __HAL_RCC_SPI4_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI4RST)
+#define __HAL_RCC_TIM15_FORCE_RESET()          (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM15RST)
+#define __HAL_RCC_TIM16_FORCE_RESET()          (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM16RST)
+#define __HAL_RCC_TIM17_FORCE_RESET()          (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM17RST)
+#define __HAL_RCC_SPI5_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI5RST)
+#define __HAL_RCC_SAI1_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI1RST)
+#define __HAL_RCC_SAI2_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI2RST)
+#if defined(SAI3)
+#define __HAL_RCC_SAI3_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI3RST)
+#endif /*SAI3*/
+#define __HAL_RCC_DFSDM1_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_DFSDM1RST)
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_HRTIMRST)
+#endif /*HRTIM1*/
+
+#define __HAL_RCC_APB2_RELEASE_RESET()         (RCC->APB2RSTR = 0x00U)
+#define __HAL_RCC_TIM1_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM1RST)
+#define __HAL_RCC_TIM8_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM8RST)
+#define __HAL_RCC_USART1_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART1RST)
+#define __HAL_RCC_USART6_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART6RST)
+#if defined(UART9)
+#define __HAL_RCC_UART9_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_UART9RST)
+#endif /*UART9*/
+#if defined(USART10)
+#define __HAL_RCC_USART10_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART10RST)
+#endif /*USART10*/
+#define __HAL_RCC_SPI1_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI1RST)
+#define __HAL_RCC_SPI4_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI4RST)
+#define __HAL_RCC_TIM15_RELEASE_RESET()          (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM15RST)
+#define __HAL_RCC_TIM16_RELEASE_RESET()          (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM16RST)
+#define __HAL_RCC_TIM17_RELEASE_RESET()          (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM17RST)
+#define __HAL_RCC_SPI5_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI5RST)
+#define __HAL_RCC_SAI1_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI1RST)
+#define __HAL_RCC_SAI2_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI2RST)
+#if defined(SAI3)
+#define __HAL_RCC_SAI3_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI3RST)
+#endif /*SAI3*/
+#define __HAL_RCC_DFSDM1_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_DFSDM1RST)
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_HRTIMRST)
+#endif /*HRTIM1*/
+
+/** @brief  Force or release the APB4 peripheral reset.
+  */
+
+#define __HAL_RCC_APB4_FORCE_RESET()           (RCC->APB4RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_SYSCFG_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_SYSCFGRST)
+#define __HAL_RCC_LPUART1_FORCE_RESET()          (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPUART1RST)
+#define __HAL_RCC_SPI6_FORCE_RESET()             (RCC->APB4RSTR) |= (RCC_APB4RSTR_SPI6RST)
+#define __HAL_RCC_I2C4_FORCE_RESET()             (RCC->APB4RSTR) |= (RCC_APB4RSTR_I2C4RST)
+#define __HAL_RCC_LPTIM2_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM2RST)
+#define __HAL_RCC_LPTIM3_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM3RST)
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM4RST)
+#endif /*LPTIM4*/
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM5RST)
+#endif /*LPTIM5*/
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_FORCE_RESET()             (RCC->APB4RSTR) |= (RCC_APB4RSTR_DAC2RST)
+#endif /*DAC2*/
+#define __HAL_RCC_COMP12_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_COMP12RST)
+#define __HAL_RCC_VREF_FORCE_RESET()             (RCC->APB4RSTR) |= (RCC_APB4RSTR_VREFRST)
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_FORCE_RESET()             (RCC->APB4RSTR) |= (RCC_APB4RSTR_SAI4RST)
+#endif /*SAI4*/
+#if defined(DTS)
+#define __HAL_RCC_DTS_FORCE_RESET()              (RCC->APB4RSTR) |= (RCC_APB4RSTR_DTSRST)
+#endif /*DTS*/
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_DFSDM2RST)
+#endif /*DFSDM2*/
+
+#define __HAL_RCC_APB4_RELEASE_RESET()           (RCC->APB4RSTR = 0x00U)
+#define __HAL_RCC_SYSCFG_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SYSCFGRST)
+#define __HAL_RCC_LPUART1_RELEASE_RESET()          (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPUART1RST)
+#define __HAL_RCC_SPI6_RELEASE_RESET()             (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SPI6RST)
+#define __HAL_RCC_I2C4_RELEASE_RESET()             (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_I2C4RST)
+#define __HAL_RCC_LPTIM2_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM2RST)
+#define __HAL_RCC_LPTIM3_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM3RST)
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM4RST)
+#endif /*LPTIM4*/
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM5RST)
+#endif /*LPTIM5*/
+#if defined(RCC_APB4RSTR_DAC2RST)
+#define __HAL_RCC_DAC2_RELEASE_RESET()             (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DAC2RST)
+#endif
+#define __HAL_RCC_COMP12_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_COMP12RST)
+#define __HAL_RCC_VREF_RELEASE_RESET()             (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_VREFRST)
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_RELEASE_RESET()             (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SAI4RST)
+#endif /*SAI4*/
+#if defined(DTS)
+#define __HAL_RCC_DTS_RELEASE_RESET()              (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DTSRST)
+#endif /*DTS*/
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DFSDM2RST)
+#endif /*DFSDM2*/
+
+/** @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+
+
+#define __HAL_RCC_MDMA_CLK_SLEEP_ENABLE()            (RCC->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN))
+#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE()           (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN))
+#if defined(JPEG)
+#define __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN))
+#endif /* JPEG */
+#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE()           (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN))
+#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE()             (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE()            (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
+#endif /*QUADSPI*/
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN))
+#if defined(OCTOSPI1)
+#define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OSPI1LPEN))
+#endif /*OCTOSPI1*/
+#if defined(OCTOSPI2)
+#define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OSPI2LPEN))
+#endif /*OCTOSPI2*/
+#if defined(OCTOSPIM)
+#define __HAL_RCC_IOMNGR_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_IOMNGRLPEN))
+#endif /*OCTOSPIM*/
+#if defined(OTFDEC1)
+#define __HAL_RCC_OTFDEC1_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OTFDEC1LPEN))
+#endif /*OTFDEC1*/
+#if defined(OTFDEC2)
+#define __HAL_RCC_OTFDEC2_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OTFDEC2LPEN))
+#endif /*OTFDEC2*/
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_GFXMMULPEN))
+#endif /*GFXMMU*/
+#if defined(CD_AXISRAM2_BASE)
+#define __HAL_RCC_AXISRAM2_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM2LPEN))
+#endif
+#if defined(CD_AXISRAM3_BASE)
+#define __HAL_RCC_AXISRAM3_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM3LPEN))
+#endif
+#define __HAL_RCC_DTCM1_CLK_SLEEP_ENABLE()           (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN))
+#define __HAL_RCC_DTCM2_CLK_SLEEP_ENABLE()           (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN))
+#define __HAL_RCC_ITCM_CLK_SLEEP_ENABLE()            (RCC->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN))
+#if defined(RCC_AHB3LPENR_AXISRAMLPEN)
+#define __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE()         (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN))
+#define __HAL_RCC_AXISRAM_CLK_SLEEP_ENABLE           __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE
+#else
+#define __HAL_RCC_AXISRAM1_CLK_SLEEP_ENABLE()        (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM1LPEN))
+#define __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE           __HAL_RCC_AXISRAM1_CLK_SLEEP_ENABLE  /* For backward compatibility */
+#endif /* RCC_AHB3LPENR_AXISRAMLPEN */
+
+#define __HAL_RCC_MDMA_CLK_SLEEP_DISABLE()            (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN))
+#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN))
+#if defined(JPEG)
+#define __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE()          (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN))
+#endif /* JPEG */
+#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN))
+#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE()             (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN))
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE()            (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN))
+#endif /*QUADSPI*/
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE()          (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN))
+#if defined(OCTOSPI1)
+#define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OSPI1LPEN))
+#endif /*OCTOSPI1*/
+#if defined(OCTOSPI2)
+#define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OSPI2LPEN))
+#endif /*OCTOSPI2*/
+#if defined(OCTOSPIM)
+#define __HAL_RCC_IOMNGR_CLK_SLEEP_DISABLE()          (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_IOMNGRLPEN))
+#endif /*OCTOSPIM*/
+#if defined(OTFDEC1)
+#define __HAL_RCC_OTFDEC1_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OTFDEC1LPEN))
+#endif /*OTFDEC1*/
+#if defined(OTFDEC2)
+#define __HAL_RCC_OTFDEC2_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OTFDEC2LPEN))
+#endif /*OTFDEC2*/
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_GFXMMULPEN))
+#endif /*GFXMMU*/
+#if defined(CD_AXISRAM2_BASE)
+#define __HAL_RCC_AXISRAM2_CLK_SLEEP_DISABLE()         (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM2LPEN))
+#endif
+#if defined(CD_AXISRAM3_BASE)
+#define __HAL_RCC_AXISRAM3_CLK_SLEEP_DISABLE()         (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM3LPEN))
+#endif
+#define __HAL_RCC_DTCM1_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN))
+#define __HAL_RCC_DTCM2_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN))
+#define __HAL_RCC_ITCM_CLK_SLEEP_DISABLE()            (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN))
+#if defined(RCC_AHB3LPENR_AXISRAMLPEN)
+#define __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE()         (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN))
+#define __HAL_RCC_AXISRAM_CLK_SLEEP_DISABLE           __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE
+#else
+#define __HAL_RCC_AXISRAM1_CLK_SLEEP_DISABLE()        (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM1LPEN))
+#define __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE          __HAL_RCC_AXISRAM1_CLK_SLEEP_DISABLE      /* For backward compatibility */
+#endif  /* RCC_AHB3LPENR_AXISRAMLPEN */
+
+/** @brief  Get the enable or disable status of the AHB3 peripheral clock during Low Poser (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+
+#define __HAL_RCC_MDMA_IS_CLK_SLEEP_ENABLED()             ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN)    != 0U)
+#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN)   != 0U)
+#if defined(JPEG)
+#define __HAL_RCC_JPGDEC_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_JPGDECLPEN)  != 0U)
+#endif /* JPEG */
+#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN)   != 0U)
+#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN)     != 0U)
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED()             ((RCC->AHB3LPENR & RCC_AHB3LPENR_QSPILPEN)    != 0U)
+#endif /*QUADSPI*/
+#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN)  != 0U)
+#if defined(OCTOSPI1)
+#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI1LPEN)    != 0U)
+#endif /*OCTOSPI1*/
+#if defined(OCTOSPI2)
+#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI2LPEN)    != 0U)
+#endif /*OCTOSPI2*/
+#if defined(OCTOSPIM)
+#define __HAL_RCC_IOMNGR_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_IOMNGRLPEN)   != 0U)
+#endif /*OCTOSPIM*/
+#if defined(OTFDEC1)
+#define __HAL_RCC_OTFDEC1_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC1LPEN) != 0U)
+#endif /*OTFDEC1*/
+#if defined(OTFDEC2)
+#define __HAL_RCC_OTFDEC2_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC2LPEN) != 0U)
+#endif /*OTFDEC2*/
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_GFXMMULPEN)    != 0U)
+#endif /*GFXMMU*/
+#if defined(CD_AXISRAM2_BASE)
+#define __HAL_RCC_AXISRAM2_IS_CLK_SLEEP_ENABLED()         ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM2LPEN)   != 0U)
+#endif
+#if defined(CD_AXISRAM3_BASE)
+#define __HAL_RCC_AXISRAM3_IS_CLK_SLEEP_ENABLED()         ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM3LPEN)   != 0U)
+#endif
+#define __HAL_RCC_DTCM1_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN)   != 0U)
+#define __HAL_RCC_DTCM2_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN)   != 0U)
+#define __HAL_RCC_ITCM_IS_CLK_SLEEP_ENABLED()             ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN)    != 0U)
+#if defined(RCC_AHB3LPENR_AXISRAMLPEN)
+#define __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_ENABLED()          ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAMLPEN) != 0U)
+#else
+#define __HAL_RCC_AXISRAM1_IS_CLK_SLEEP_ENABLED()         ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM1LPEN) != 0U)
+#endif
+
+#define __HAL_RCC_MDMA_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN)    == 0U)
+#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN)   == 0U)
+#if defined(JPEG)
+#define __HAL_RCC_JPGDEC_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB3LPENR & RCC_AHB3LPENR_JPGDECLPEN)  == 0U)
+#endif /* JPEG */
+#define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN)   == 0U)
+#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN)     == 0U)
+#if defined(QUADSPI)
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_QSPILPEN)    == 0U)
+#endif /*QUADSPI*/
+#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN)  == 0U)
+#if defined(OCTOSPI1)
+#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI1LPEN)  == 0U)
+#endif /*OCTOSPI1*/
+#if defined(OCTOSPI2)
+#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI2LPEN)  == 0U)
+#endif /*OCTOSPI2*/
+#if defined(OCTOSPIM)
+#define __HAL_RCC_IOMNGR_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_IOMNGRLPEN) == 0U)
+#endif /*OCTOSPIM*/
+#if defined(OTFDEC1)
+#define __HAL_RCC_OTFDEC1_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC1LPEN)  == 0U)
+#endif /*OTFDEC1*/
+#if defined(OTFDEC2)
+#define __HAL_RCC_OTFDEC2_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC2LPEN)  == 0U)
+#endif /*OTFDEC2*/
+#if defined(GFXMMU)
+#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_GFXMMULPEN)  == 0U)
+#endif /*GFXMMU*/
+#if defined(CD_AXISRAM2_BASE)
+#define __HAL_RCC_AXISRAM2_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM2LPEN)  == 0U)
+#endif
+#if defined(CD_AXISRAM3_BASE)
+#define __HAL_RCC_AXISRAM3_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM3LPEN)  == 0U)
+#endif
+#define __HAL_RCC_DTCM1_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN)   == 0U)
+#define __HAL_RCC_DTCM2_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN)   == 0U)
+#define __HAL_RCC_ITCM_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN)    == 0U)
+#if defined(RCC_AHB3LPENR_AXISRAMLPEN)
+#define __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAMLPEN) == 0U)
+#else
+#define __HAL_RCC_AXISRAM1_IS_CLK_SLEEP_DISABLED()        ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAML1PEN) == 0U)
+#endif /* RCC_AHB3LPENR_AXISRAMLPEN */
+
+/** @brief  ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE()             (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
+#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE()             (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
+#define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE()            (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN))
+#if defined(RCC_AHB1LPENR_CRCLPEN)
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()              (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
+#endif
+#if defined(ETH)
+#define __HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE()          (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN))
+#endif /*ETH*/
+#if defined(DUAL_CORE)
+#define __HAL_RCC_ART_CLK_SLEEP_ENABLE()              (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ARTLPEN))
+#endif /*DUAL_CORE*/
+#if defined(ETH)
+#define __HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE()           (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN))
+#define __HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE()           (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN))
+#endif /*ETH*/
+#define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN))
+#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
+#if defined(USB2_OTG_FS)
+#define __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN))
+#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
+#endif /* USB2_OTG_FS */
+
+#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE()             (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN))
+#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE()             (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN))
+#define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE()            (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN))
+#if defined(RCC_AHB1LPENR_CRCLPEN)
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()              (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_CRCLPEN))
+#endif
+#if defined(ETH)
+#define __HAL_RCC_ETH1MAC_CLK_SLEEP_DISABLE()          (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN))
+#endif  /*ETH*/
+#if defined(DUAL_CORE)
+#define __HAL_RCC_ART_CLK_SLEEP_DISABLE()              (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ARTLPEN))
+#endif /*DUAL_CORE*/
+#if defined(ETH)
+#define __HAL_RCC_ETH1TX_CLK_SLEEP_DISABLE()           (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN))
+#define __HAL_RCC_ETH1RX_CLK_SLEEP_DISABLE()           (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN))
+#endif  /*ETH*/
+#define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()      (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN))
+#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
+#if defined(USB2_OTG_FS)
+#define __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()      (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN))
+#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
+#endif /* USB2_OTG_FS */
+
+/** @brief  Get the enable or disable status of the AHB1 peripheral clock during Low Poser (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+
+#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN))          != 0U)
+#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN))          != 0U)
+#define __HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED()             ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN))         != 0U)
+#if defined(RCC_AHB1LPENR_CRCLPEN)
+#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED()                ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN))         != 0U)
+#endif
+#if defined(ETH)
+#define __HAL_RCC_ETH1MAC_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1MACLPEN))       != 0U)
+#endif  /*ETH*/
+#if defined(DUAL_CORE)
+#define __HAL_RCC_ART_IS_CLK_SLEEP_ENABLED()               ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ARTLPEN))       != 0U)
+#endif /*DUAL_CORE*/
+#if defined(ETH)
+#define __HAL_RCC_ETH1TX_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1TXLPEN))        != 0U)
+#define __HAL_RCC_ETH1RX_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1RXLPEN))        != 0U)
+#endif  /*ETH*/
+#define __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_ENABLED()       ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN))     != 0U)
+#define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED()  ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) != 0U)
+#if defined(USB2_OTG_FS)
+#define __HAL_RCC_USB2_OTG_FS_IS_CLK_SLEEP_ENABLED()       ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSLPEN))     != 0U)
+#define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_SLEEP_ENABLED()  ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) != 0U)
+#endif /* USB2_OTG_FS */
+
+#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN))          == 0U)
+#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN))          == 0U)
+#define __HAL_RCC_ADC12_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN))         == 0U)
+#if defined(RCC_AHB1LPENR_CRCLPEN)
+#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED()              ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN))           == 0U)
+#endif
+#if defined(ETH)
+#define __HAL_RCC_ETH1MAC_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1MACLPEN))       == 0U)
+#endif /* ETH */
+#if defined(DUAL_CORE)
+#define __HAL_RCC_ART_IS_CLK_SLEEP_DISABLED()              ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ARTLPEN))           == 0U)
+#endif /*DUAL_CORE*/
+#if defined(ETH)
+#define __HAL_RCC_ETH1TX_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1TXLPEN))        == 0U)
+#define __HAL_RCC_ETH1RX_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1RXLPEN))        == 0U)
+#endif /* ETH */
+#define __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_DISABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN))     == 0U)
+#define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) == 0U)
+#if defined(USB2_OTG_FS)
+#define __HAL_RCC_USB2_OTG_FS_IS_CLK_SLEEP_DISABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSLPEN))     == 0U)
+#define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) == 0U)
+#endif /* USB2_OTG_FS */
+
+
+/** @brief  ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#if defined(DCMI) && defined(PSSI)
+#define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE()        (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMI_PSSILPEN))
+#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE()             __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE()             (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
+#endif /* DCMI && PSSI */
+#if defined(CRYP)
+#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE()             (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE()             (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
+#endif /* HASH */
+#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()              (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
+#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE()           (RCC->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))
+#if defined(RCC_AHB2LPENR_DFSDMDMALPEN)
+#define __HAL_RCC_DFSDMDMA_CLK_SLEEP_ENABLE()         (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DFSDMDMALPEN))
+#endif
+#if defined(RCC_AHB2LPENR_D2SRAM1LPEN)
+#define __HAL_RCC_D2SRAM1_CLK_SLEEP_ENABLE()          (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN))
+#else
+#define __HAL_RCC_AHBSRAM1_CLK_SLEEP_ENABLE()         (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AHBSRAM1LPEN))
+#endif /* RCC_AHB2LPENR_D2SRAM1LPEN */
+#if defined(RCC_AHB2LPENR_D2SRAM2LPEN)
+#define __HAL_RCC_D2SRAM2_CLK_SLEEP_ENABLE()          (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN))
+#else
+#define __HAL_RCC_AHBSRAM2_CLK_SLEEP_ENABLE()         (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AHBSRAM2LPEN))
+#endif /* RCC_AHB2LPENR_D2SRAM2LPEN */
+#if defined(RCC_AHB2LPENR_D2SRAM3LPEN)
+#define __HAL_RCC_D2SRAM3_CLK_SLEEP_ENABLE()          (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN))
+#endif
+
+#if defined(DCMI) && defined(PSSI)
+#define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE()        (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMI_PSSILPEN))
+#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE()             __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE()             (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))
+#endif /* DCMI && PSSI */
+#if defined(CRYP)
+#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE()             (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE()             (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))
+#endif /* HASH */
+#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()              (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))
+#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE()           (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))
+#if defined(RCC_AHB2LPENR_DFSDMDMALPEN)
+#define __HAL_RCC_DFSDMDMA_CLK_SLEEP_DISABLE()         (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DFSDMDMALPEN))
+#endif
+#if defined(RCC_AHB2LPENR_D2SRAM1LPEN)
+#define __HAL_RCC_D2SRAM1_CLK_SLEEP_DISABLE()          (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN))
+#else
+#define __HAL_RCC_AHBSRAM1_CLK_SLEEP_DISABLE()         (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_AHBSRAM1LPEN))
+#endif /* RCC_AHB2LPENR_D2SRAM1LPEN */
+#if defined(RCC_AHB2LPENR_D2SRAM2LPEN)
+#define __HAL_RCC_D2SRAM2_CLK_SLEEP_DISABLE()          (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN))
+#else
+#define __HAL_RCC_AHBSRAM2_CLK_SLEEP_DISABLE()          (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_AHBSRAM2LPEN))
+#endif /* RCC_AHB2LPENR_D2SRAM2LPEN */
+#if defined(RCC_AHB2LPENR_D2SRAM3LPEN)
+#define __HAL_RCC_D2SRAM3_CLK_SLEEP_DISABLE()          (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN))
+#endif
+
+/** @brief  Get the enable or disable status of the AHB2 peripheral clock during Low Poser (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+
+#if defined(DCMI) && defined(PSSI)
+#define __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_ENABLED()         ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMI_PSSILPEN))    != 0U)
+#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED()              __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_ENABLED()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN))    != 0U)
+#endif /* DCMI && PSSI */
+#if defined(CRYP)
+#define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN))    != 0U)
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN))    != 0U)
+#endif /* HASH */
+#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED()               ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN))     != 0U)
+#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN))  != 0U)
+#if defined(RCC_AHB2LPENR_DFSDMDMALPEN)
+#define __HAL_RCC_DFSDMDMA_IS_CLK_SLEEP_ENABLED()          ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DFSDMDMALPEN)) != 0U)
+#endif
+#if defined(RCC_AHB2LPENR_D2SRAM1LPEN)
+#define __HAL_RCC_D2SRAM1_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM1LPEN)) != 0U)
+#else
+#define __HAL_RCC_AHBSRAM1_IS_CLK_SLEEP_ENABLED()          ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM1LPEN)) != 0U)
+#endif /* RCC_AHB2LPENR_D2SRAM1LPEN */
+#if defined(RCC_AHB2LPENR_D2SRAM2LPEN)
+#define __HAL_RCC_D2SRAM2_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM2LPEN)) != 0U)
+#else
+#define __HAL_RCC_AHBSRAM2_IS_CLK_SLEEP_ENABLED()          ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM2LPEN)) != 0U)
+#endif /* RCC_AHB2LPENR_D2SRAM2LPEN */
+#if defined(RCC_AHB2LPENR_D2SRAM3LPEN)
+#define __HAL_RCC_D2SRAM3_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM3LPEN)) != 0U)
+#endif /* RCC_AHB2LPENR_D2SRAM3LPEN */
+
+#if defined(DCMI) && defined(PSSI)
+#define __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_DISABLED()        ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMI_PSSILPEN))    == 0U)
+#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED()             __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_DISABLED()  /* for API backward compatibility*/
+#else
+#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN))    == 0U)
+#endif /* DCMI && PSSI */
+#if defined(CRYP)
+#define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN))    == 0U)
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN))    == 0U)
+#endif /* HASH */
+#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED()              ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN))     == 0U)
+#if defined(RCC_AHB2LPENR_DFSDMDMALPEN)
+#define __HAL_RCC_DFSDMDMA_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DFSDMDMALPEN)) == 0U)
+#endif
+#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN))  == 0U)
+#if defined(RCC_AHB2LPENR_D2SRAM1LPEN)
+#define __HAL_RCC_D2SRAM1_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM1LPEN)) == 0U)
+#else
+#define __HAL_RCC_AHBSRAM1_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM1LPEN)) == 0U)
+#endif /* RCC_AHB2LPENR_D2SRAM1LPEN */
+#if defined(RCC_AHB2LPENR_D2SRAM2LPEN)
+#define __HAL_RCC_D2SRAM2_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM2LPEN)) == 0U)
+#else
+#define __HAL_RCC_AHBSRAM2_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM2LPEN)) == 0U)
+#endif /* RCC_AHB2LPENR_D2SRAM2LPEN */
+#if defined(RCC_AHB2LPENR_D2SRAM3LPEN)
+#define __HAL_RCC_D2SRAM3_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM3LPEN)) == 0U)
+#endif /* RCC_AHB2LPENR_D2SRAM1LPEN*/
+
+
+/** @brief  ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN)
+#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN)
+#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN)
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN)
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN)
+#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN)
+#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN)
+#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN)
+#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN)
+#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN)
+#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN)
+#if defined(RCC_AHB4LPENR_CRCLPEN)
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()             (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN)
+#endif
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_CLK_SLEEP_ENABLE()            (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BDMA2LPEN)
+#define __HAL_RCC_BDMA_CLK_SLEEP_ENABLE  __HAL_RCC_BDMA2_CLK_SLEEP_ENABLE /* for API backward compatibility*/
+#else
+#define __HAL_RCC_BDMA_CLK_SLEEP_ENABLE()            (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN)
+#endif /* BDMA2 */
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE()            (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN)
+#endif /* ADC3 */
+#define __HAL_RCC_BKPRAM_CLK_SLEEP_ENABLE()          (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN)
+#if defined(RCC_AHB4LPENR_SRDSRAMLPEN)
+#define __HAL_RCC_SRDSRAM_CLK_SLEEP_ENABLE()         (RCC->AHB4LPENR  |= (RCC_AHB4LPENR_SRDSRAMLPEN))
+#define __HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE  __HAL_RCC_SRDSRAM_CLK_SLEEP_ENABLE /* for API backward compatibility*/
+#else
+#define __HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE()         (RCC->AHB4LPENR  |= (RCC_AHB4LPENR_D3SRAM1LPEN))
+#endif /* RCC_AHB4LPENR_SRDSRAMLPEN */
+
+#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN)
+#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN)
+#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN)
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN)
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN)
+#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN)
+#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN)
+#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN)
+#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN)
+#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN)
+#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN)
+#if defined(RCC_AHB4LPENR_CRCLPEN)
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()             (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN)
+#endif
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_CLK_SLEEP_DISABLE()            (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMA2LPEN)
+#define __HAL_RCC_BDMA_CLK_SLEEP_DISABLE  __HAL_RCC_BDMA2_CLK_SLEEP_DISABLE  /* For API backward compatibility*/
+#else
+#define __HAL_RCC_BDMA_CLK_SLEEP_DISABLE()            (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN)
+#endif /*BDMA2*/
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE()            (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN)
+#endif /*ADC3*/
+#define __HAL_RCC_BKPRAM_CLK_SLEEP_DISABLE()          (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN)
+#if defined(RCC_AHB4LPENR_SRDSRAMLPEN)
+#define __HAL_RCC_SRDSRAM_CLK_SLEEP_DISABLE()         (RCC->AHB4LPENR  &= ~ (RCC_AHB4LPENR_SRDSRAMLPEN))
+#define __HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE  __HAL_RCC_SRDSRAM_CLK_SLEEP_DISABLE
+#else
+#define __HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE()         (RCC->AHB4LPENR  &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN))
+#endif
+
+
+/** @brief  Get the enable or disable status of the AHB4 peripheral clock during Low Poser (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+
+#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN))   != 0U)
+#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN))   != 0U)
+#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN))   != 0U)
+#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN))   != 0U)
+#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN))   != 0U)
+#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN))   != 0U)
+#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN))   != 0U)
+#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN))   != 0U)
+#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN))   != 0U)
+#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN))   != 0U)
+#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN))   != 0U)
+#if defined(RCC_AHB4LPENR_CRCLPEN)
+#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB4LPENR & (RCC_AHB4LPENR_CRCLPEN))     != 0U)
+#endif
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMA2LPEN))    != 0U)
+#define __HAL_RCC_BDMA_IS_CLK_SLEEP_ENABLED __HAL_RCC_BDMA2_IS_CLK_SLEEP_ENABLED  /* For API backward compatibility*/
+#else
+#define __HAL_RCC_BDMA_IS_CLK_SLEEP_ENABLED()             ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMALPEN))    != 0U)
+#endif /*BDMA2*/
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED()             ((RCC->AHB4LPENR & (RCC_AHB4LPENR_ADC3LPEN))    != 0U)
+#endif /*ADC3*/
+#define __HAL_RCC_BKPRAM_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN))  != 0U)
+#if defined(RCC_AHB4LPENR_SRDSRAMLPEN)
+#define __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_ENABLED()          ((RCC->AHB4LPENR & (RCC_AHB4LPENR_SRDSRAMLPEN)) != 0U)
+#define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_ENABLED  __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_ENABLED  /* For API backward compatibility*/
+#else
+#define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_ENABLED()          ((RCC->AHB4LPENR & (RCC_AHB4LPENR_D3SRAM1LPEN)) != 0U)
+#endif
+
+#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN))   == 0U)
+#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN))   == 0U)
+#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN))   == 0U)
+#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN))   == 0U)
+#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN))   == 0U)
+#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN))   == 0U)
+#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN))   == 0U)
+#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN))   == 0U)
+#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN))   == 0U)
+#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN))   == 0U)
+#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN))   == 0U)
+#if defined(RCC_AHB4LPENR_CRCLPEN)
+#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB4LPENR & (RCC_AHB4LPENR_CRCLPEN))     == 0U)
+#endif
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMA2LPEN))  == 0U)
+#define __HAL_RCC_BDMA_IS_CLK_SLEEP_DISABLED __HAL_RCC_BDMA2_IS_CLK_SLEEP_DISABLED  /* For API backward compatibility*/
+#else
+#define __HAL_RCC_BDMA_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMALPEN))    == 0U)
+#endif /*BDMA2*/
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_ADC3LPEN))    == 0U)
+#endif /*ADC3*/
+#define __HAL_RCC_BKPRAM_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN))  == 0U)
+#if defined(RCC_AHB4LPENR_SRDSRAMLPEN)
+#define __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB4LPENR & (RCC_AHB4LPENR_SRDSRAMLPEN)) == 0U)
+#define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_DISABLED  __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_DISABLED  /* For API backward compatibility*/
+#else
+#define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB4LPENR & (RCC_AHB4LPENR_D3SRAM1LPEN)) == 0U)
+#endif
+
+
+/** @brief  ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE()           (RCC->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN)
+#endif /* LTDC */
+#if defined(DSI)
+#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE()            (RCC->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN)
+#endif /*DSI*/
+#define __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE()          (RCC->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN)
+
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE()           (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN)
+#endif /* LTDC */
+#if defined(DSI)
+#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE()            (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN)
+#endif /*DSI*/
+#define __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE()          (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN)
+
+
+/** @brief  Get the enable or disable status of the APB3 peripheral clock during Low Poser (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED()            ((RCC->APB3LPENR & (RCC_APB3LPENR_LTDCLPEN))  != 0U)
+#endif /* LTDC */
+#if defined(DSI)
+#define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED()             ((RCC->APB3LPENR & (RCC_APB3LPENR_DSILPEN))   != 0U)
+#endif /*DSI*/
+#define __HAL_RCC_WWDG1_IS_CLK_SLEEP_ENABLED()           ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) != 0U)
+
+#if defined(LTDC)
+#define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED()           ((RCC->APB3LPENR & (RCC_APB3LPENR_LTDCLPEN))  == 0U)
+#endif /* LTDC */
+#if defined(DSI)
+#define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED()            ((RCC->APB3LPENR & (RCC_APB3LPENR_DSILPEN))   == 0U)
+#endif /*DSI*/
+#define __HAL_RCC_WWDG1_IS_CLK_SLEEP_DISABLED()          ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) == 0U)
+
+
+/** @brief  ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN)
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN)
+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN)
+#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN)
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN)
+#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN)
+#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN)
+#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN)
+#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN)
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE()         (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN)
+
+#if defined(DUAL_CORE)
+#define __HAL_RCC_WWDG2_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN)
+#endif /*DUAL_CORE*/
+
+#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN)
+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN)
+#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE()        (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN)
+#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE()         (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN)
+#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()         (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN)
+#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN)
+#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN)
+#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN)
+#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN)
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN)
+#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE()            (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN)
+#define __HAL_RCC_DAC12_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN)
+#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN)
+#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN)
+#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE()            (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN)
+#define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE()          (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN)
+#define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE()          (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN)
+#define __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE()          (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN)
+#define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE()          (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN)
+
+
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN)
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN)
+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN)
+#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN)
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN)
+#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN)
+#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN)
+#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN)
+#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN)
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE()         (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN)
+
+#if defined(DUAL_CORE)
+#define __HAL_RCC_WWDG2_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN)
+#endif /*DUAL_CORE*/
+
+#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN)
+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN)
+#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()        (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN)
+#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE()         (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN)
+#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE()         (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN)
+#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN)
+#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN)
+#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN)
+#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN)
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN)
+#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE()            (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN)
+#define __HAL_RCC_DAC12_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN)
+#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN)
+#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN)
+#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE()            (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN)
+#define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE()          (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN)
+#define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE()          (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN)
+#define __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE()          (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN)
+#define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE()          (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN)
+
+
+/** @brief  Get the enable or disable status of the APB1 peripheral clock during Low Poser (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+
+#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN))    != 0U)
+#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN))    != 0U)
+#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN))    != 0U)
+#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN))    != 0U)
+#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN))    != 0U)
+#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN))    != 0U)
+#define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN))   != 0U)
+#define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN))   != 0U)
+#define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN))   != 0U)
+#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN))  != 0U)
+#if defined(DUAL_CORE)
+#define __HAL_RCC_WWDG2_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_WWDG2LPEN))   != 0U)
+#endif /*DUAL_CORE*/
+#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN))    != 0U)
+#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN))    != 0U)
+#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED()         ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) != 0U)
+#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN))  != 0U)
+#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN))  != 0U)
+#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN))   != 0U)
+#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN))   != 0U)
+#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN))    != 0U)
+#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN))    != 0U)
+#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN))    != 0U)
+#define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED()             ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN))     != 0U)
+#define __HAL_RCC_DAC12_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN))   != 0U)
+#define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN))   != 0U)
+#define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN))   != 0U)
+#define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED()             ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN))     != 0U)
+#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED()          ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN))   != 0U)
+#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN))   != 0U)
+#define __HAL_RCC_MDIOS_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN))   != 0U)
+#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN))   != 0U)
+
+#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN))    == 0U)
+#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN))    == 0U)
+#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN))    == 0U)
+#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN))    == 0U)
+#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN))    == 0U)
+#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN))    == 0U)
+#define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN))   == 0U)
+#define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN))   == 0U)
+#define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN))   == 0U)
+#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED()         ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN))  == 0U)
+#if defined(DUAL_CORE)
+#define __HAL_RCC_WWDG2_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_WWDG2LPEN))   == 0U)
+#endif /*DUAL_CORE*/
+#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN))    == 0U)
+#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN))    == 0U)
+#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED()        ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) == 0U)
+#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED()         ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN))  == 0U)
+#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED()         ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN))  == 0U)
+#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN))   == 0U)
+#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN))   == 0U)
+#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN))    == 0U)
+#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN))    == 0U)
+#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN))    == 0U)
+#define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN))     == 0U)
+#define __HAL_RCC_DAC12_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN))   == 0U)
+#define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN))   == 0U)
+#define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN))   == 0U)
+#define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED()            ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN))     == 0U)
+#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED()         ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN))   == 0U)
+#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN))   == 0U)
+#define __HAL_RCC_MDIOS_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN))   == 0U)
+#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN))   == 0U)
+
+
+/** @brief  ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN)
+#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN)
+#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE()         (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN)
+#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE()         (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN)
+#if defined(UART9)
+#define __HAL_RCC_UART9_CLK_SLEEP_ENABLE()          (RCC->APB2LPENR) |= (RCC_APB2LPENR_UART9LPEN)
+#endif /*UART9*/
+#if defined(USART10)
+#define __HAL_RCC_USART10_CLK_SLEEP_ENABLE()        (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART10LPEN)
+#endif /*USART10*/
+#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN)
+#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN)
+#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE()          (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN)
+#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE()          (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN)
+#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE()          (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN)
+#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN)
+#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN)
+#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN)
+#if defined(SAI3)
+#define __HAL_RCC_SAI3_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN)
+#endif /*SAI3*/
+#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE()         (RCC->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN)
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_CLK_SLEEP_ENABLE()         (RCC->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN)
+#endif /*HRTIM1*/
+
+#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN)
+#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN)
+#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE()         (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN)
+#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE()         (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN)
+#if defined(UART9)
+#define __HAL_RCC_UART9_CLK_SLEEP_DISABLE()          (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_UART9LPEN)
+#endif /*UART9*/
+#if defined(USART10)
+#define __HAL_RCC_USART10_CLK_SLEEP_DISABLE()         (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART10LPEN)
+#endif /*USART10*/
+#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN)
+#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN)
+#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE()          (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN)
+#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE()          (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN)
+#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE()          (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN)
+#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN)
+#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN)
+#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN)
+#if defined(SAI3)
+#define __HAL_RCC_SAI3_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN)
+#endif /*SAI3*/
+#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE()         (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN)
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_CLK_SLEEP_DISABLE()         (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN)
+#endif /*HRTIM1*/
+
+
+/** @brief  Get the enable or disable status of the APB2 peripheral clock during Low Poser (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+
+#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN))   != 0U)
+#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN))   != 0U)
+#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != 0U)
+#define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != 0U)
+#if defined(UART9)
+#define __HAL_RCC_UART9_IS_CLK_SLEEP_ENABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_UART9LPEN)) != 0U)
+#endif /*UART9*/
+#if defined(USART10)
+#define __HAL_RCC_USART10_IS_CLK_SLEEP_ENABLED()         ((RCC->APB2LPENR & (RCC_APB2LPENR_USART10LPEN)) != 0U)
+#endif /*USART10*/
+#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN))   != 0U)
+#define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN))   != 0U)
+#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN))  != 0U)
+#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN))  != 0U)
+#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN))  != 0U)
+#define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN))   != 0U)
+#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN))   != 0U)
+#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN))   != 0U)
+#if defined(SAI3)
+#define __HAL_RCC_SAI3_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI3LPEN))   != 0U)
+#endif /*SAI3*/
+#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != 0U)
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_ENABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_HRTIMLPEN))  != 0U)
+#endif /*HRTIM1*/
+
+#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN))   == 0U)
+#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN))   == 0U)
+#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED()         ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == 0U)
+#define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED()         ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == 0U)
+#if defined(UART9)
+#define __HAL_RCC_USART9_IS_CLK_SLEEP_DISABLED()         ((RCC->APB2LPENR & (RCC_APB2LPENR_USART9LPEN)) == 0U)
+#endif /*UART9*/
+#if defined(USART10)
+#define __HAL_RCC_USART10_IS_CLK_SLEEP_DISABLED()        ((RCC->APB2LPENR & (RCC_APB2LPENR_USART10LPEN)) == 0U)
+#endif /*USART10*/
+#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN))   == 0U)
+#define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN))   == 0U)
+#define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN))  == 0U)
+#define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN))  == 0U)
+#define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN))  == 0U)
+#define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN))   == 0U)
+#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN))   == 0U)
+#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN))   == 0U)
+#if defined(SAI3)
+#define __HAL_RCC_SAI3_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI3LPEN))   == 0U)
+#endif /*SAI3*/
+#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED()         ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == 0U)
+#if defined(HRTIM1)
+#define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_DISABLED()         ((RCC->APB2LPENR & (RCC_APB2LPENR_HRTIMLPEN))  == 0U)
+#endif /*HRTIM1*/
+
+/** @brief  ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN)
+#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE()          (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN)
+#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE()             (RCC->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN)
+#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE()             (RCC->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN)
+#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN)
+#define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN)
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN)
+#endif /*LPTIM4*/
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN)
+#endif /*LPTIM5*/
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_DAC2LPEN)
+#endif /*DAC2*/
+#define __HAL_RCC_COMP12_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN)
+#define __HAL_RCC_VREF_CLK_SLEEP_ENABLE()             (RCC->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN)
+#define __HAL_RCC_RTC_CLK_SLEEP_ENABLE()              (RCC->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN)
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_CLK_SLEEP_ENABLE()             (RCC->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN)
+#endif /*SAI4*/
+#if defined(DTS)
+#define __HAL_RCC_DTS_CLK_SLEEP_ENABLE()              (RCC->APB4LPENR) |= (RCC_APB4LPENR_DTSLPEN)
+#endif /*DTS*/
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_DFSDM2LPEN)
+#endif /*DFSDM2*/
+
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN)
+#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE()          (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN)
+#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE()             (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN)
+#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE()             (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN)
+#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN)
+#define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN)
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN)
+#endif /*LPTIM4*/
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN)
+#endif /*LPTIM5*/
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_CLK_SLEEP_DISABLE()             (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DAC2LPEN)
+#endif /*DAC2*/
+#define __HAL_RCC_COMP12_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN)
+#define __HAL_RCC_VREF_CLK_SLEEP_DISABLE()             (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN)
+#define __HAL_RCC_RTC_CLK_SLEEP_DISABLE()              (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN)
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_CLK_SLEEP_DISABLE()             (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN)
+#endif /*SAI4*/
+#if defined(DTS)
+#define __HAL_RCC_DTS_CLK_SLEEP_DISABLE()              (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DTSLPEN)
+#endif /*DTS*/
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_CLK_SLEEP_DISABLE()          (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DFSDM2LPEN)
+#endif /*DFSDM2*/
+
+
+/** @brief  Get the enable or disable status of the APB4 peripheral clock during Low Poser (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+
+#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN))  != 0U)
+#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) != 0U)
+#define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN))    != 0U)
+#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN))    != 0U)
+#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN))  != 0U)
+#define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN))  != 0U)
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM4LPEN))  != 0U)
+#endif /*LPTIM4*/
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM5LPEN))  != 0U)
+#endif /*LPTIM5*/
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_IS_CLK_SLEEP_ENABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_DAC2LPEN))  != 0U)
+#endif /*DAC2*/
+#define __HAL_RCC_COMP12_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN))  != 0U)
+#define __HAL_RCC_VREF_IS_CLK_SLEEP_ENABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN))    != 0U)
+#define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED()               ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN))  != 0U)
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_IS_CLK_SLEEP_ENABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_SAI4LPEN))    != 0U)
+#endif /*SAI4*/
+#if defined(DTS)
+#define __HAL_RCC_DTS_IS_CLK_SLEEP_ENABLED()               ((RCC->APB4LPENR & (RCC_APB4LPENR_DTSLPEN))    != 0U)
+#endif /*DTS*/
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_DFSDM2LPEN)) != 0U)
+#endif /*DFSDM2*/
+
+#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN))  == 0U)
+#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED()          ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) == 0U)
+#define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED()             ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN))    == 0U)
+#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED()             ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN))    == 0U)
+#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN))  == 0U)
+#define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN))  == 0U)
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM4LPEN))  == 0U)
+#endif /*LPTIM4*/
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM5LPEN))  == 0U)
+#endif /*LPTIM5*/
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_IS_CLK_SLEEP_DISABLED()             ((RCC->APB4LPENR & (RCC_APB4LPENR_DAC2LPEN))  == 0U)
+#endif /*DAC2*/
+#define __HAL_RCC_COMP12_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN))  == 0U)
+#define __HAL_RCC_VREF_IS_CLK_SLEEP_DISABLED()             ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN))    == 0U)
+#define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN))  == 0U)
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_IS_CLK_SLEEP_DISABLED()             ((RCC->APB4LPENR & (RCC_APB4LPENR_SAI4LPEN))    == 0U)
+#endif /*SAI4*/
+#if defined(DTS)
+#define __HAL_RCC_DTS_IS_CLK_SLEEP_DISABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_DTSLPEN))    == 0U)
+#endif /*DTS*/
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_DFSDM2LPEN)) == 0U)
+#endif /*DFSDM2*/
+
+
+#if defined(DUAL_CORE)
+
+/** @brief  Enable or disable the RCC_C1 AHB3 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+#define __HAL_RCC_C1_MDMA_CLK_SLEEP_ENABLE()            (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN))
+#define __HAL_RCC_C1_DMA2D_CLK_SLEEP_ENABLE()           (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN))
+#define __HAL_RCC_C1_JPGDEC_CLK_SLEEP_ENABLE()          (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN))
+#define __HAL_RCC_C1_FLASH_CLK_SLEEP_ENABLE()           (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN))
+#define __HAL_RCC_C1_FMC_CLK_SLEEP_ENABLE()             (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
+#define __HAL_RCC_C1_QSPI_CLK_SLEEP_ENABLE()            (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
+#define __HAL_RCC_C1_SDMMC1_CLK_SLEEP_ENABLE()          (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN))
+#define __HAL_RCC_C1_DTCM1_CLK_SLEEP_ENABLE()           (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN))
+#define __HAL_RCC_C1_DTCM2_CLK_SLEEP_ENABLE()           (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN))
+#define __HAL_RCC_C1_ITCM_CLK_SLEEP_ENABLE()            (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN))
+#define __HAL_RCC_C1_D1SRAM1_CLK_SLEEP_ENABLE()         (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN))
+
+
+#define __HAL_RCC_C1_MDMA_CLK_SLEEP_DISABLE()            (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN))
+#define __HAL_RCC_C1_DMA2D_CLK_SLEEP_DISABLE()           (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN))
+#define __HAL_RCC_C1_JPGDEC_CLK_SLEEP_DISABLE()          (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN))
+#define __HAL_RCC_C1_FLASH_CLK_SLEEP_DISABLE()           (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN))
+#define __HAL_RCC_C1_FMC_CLK_SLEEP_DISABLE()             (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN))
+#define __HAL_RCC_C1_QSPI_CLK_SLEEP_DISABLE()            (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN))
+#define __HAL_RCC_C1_SDMMC1_CLK_SLEEP_DISABLE()          (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN))
+#define __HAL_RCC_C1_DTCM1_CLK_SLEEP_DISABLE()           (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN))
+#define __HAL_RCC_C1_DTCM2_CLK_SLEEP_DISABLE()           (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN))
+#define __HAL_RCC_C1_ITCM_CLK_SLEEP_DISABLE()            (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN))
+#define __HAL_RCC_C1_D1SRAM1_CLK_SLEEP_DISABLE()         (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN))
+
+
+
+/** @brief  ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C1_DMA1_CLK_SLEEP_ENABLE()             (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
+#define __HAL_RCC_C1_DMA2_CLK_SLEEP_ENABLE()             (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
+#define __HAL_RCC_C1_ADC12_CLK_SLEEP_ENABLE()            (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN))
+#define __HAL_RCC_C1_ETH1MAC_CLK_SLEEP_ENABLE()          (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN))
+#define __HAL_RCC_C1_ETH1TX_CLK_SLEEP_ENABLE()           (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN))
+#define __HAL_RCC_C1_ETH1RX_CLK_SLEEP_ENABLE()           (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN))
+#define __HAL_RCC_C1_USB1_OTG_HS_CLK_SLEEP_ENABLE()      (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN))
+#define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
+#define __HAL_RCC_C1_USB2_OTG_FS_CLK_SLEEP_ENABLE()      (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN))
+#define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
+
+#define __HAL_RCC_C1_DMA1_CLK_SLEEP_DISABLE()             (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN))
+#define __HAL_RCC_C1_DMA2_CLK_SLEEP_DISABLE()             (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN))
+#define __HAL_RCC_C1_ADC12_CLK_SLEEP_DISABLE()            (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN))
+#define __HAL_RCC_C1_ETH1MAC_CLK_SLEEP_DISABLE()          (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN))
+#define __HAL_RCC_C1_ETH1TX_CLK_SLEEP_DISABLE()           (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN))
+#define __HAL_RCC_C1_ETH1RX_CLK_SLEEP_DISABLE()           (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN))
+#define __HAL_RCC_C1_USB1_OTG_HS_CLK_SLEEP_DISABLE()      (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN))
+#define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
+#define __HAL_RCC_C1_USB2_OTG_FS_CLK_SLEEP_DISABLE()      (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN))
+#define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
+
+/** @brief  ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C1_DCMI_CLK_SLEEP_ENABLE()             (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
+#if defined(CRYP)
+#define __HAL_RCC_C1_CRYP_CLK_SLEEP_ENABLE()             (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_C1_HASH_CLK_SLEEP_ENABLE()             (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
+#endif /* HASH */
+#define __HAL_RCC_C1_RNG_CLK_SLEEP_ENABLE()              (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
+#define __HAL_RCC_C1_SDMMC2_CLK_SLEEP_ENABLE()           (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))
+#define __HAL_RCC_C1_D2SRAM1_CLK_SLEEP_ENABLE()          (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN))
+#define __HAL_RCC_C1_D2SRAM2_CLK_SLEEP_ENABLE()          (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN))
+#define __HAL_RCC_C1_D2SRAM3_CLK_SLEEP_ENABLE()          (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN))
+
+#define __HAL_RCC_C1_DCMI_CLK_SLEEP_DISABLE()             (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))
+#if defined(CRYP)
+#define __HAL_RCC_C1_CRYP_CLK_SLEEP_DISABLE()             (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_C1_HASH_CLK_SLEEP_DISABLE()             (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))
+#endif /* HASH */
+#define __HAL_RCC_C1_RNG_CLK_SLEEP_DISABLE()              (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))
+#define __HAL_RCC_C1_SDMMC2_CLK_SLEEP_DISABLE()           (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))
+#define __HAL_RCC_C1_D2SRAM1_CLK_SLEEP_DISABLE()          (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN))
+#define __HAL_RCC_C1_D2SRAM2_CLK_SLEEP_DISABLE()          (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN))
+#define __HAL_RCC_C1_D2SRAM3_CLK_SLEEP_DISABLE()          (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN))
+
+/** @brief  ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C1_GPIOA_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN)
+#define __HAL_RCC_C1_GPIOB_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN)
+#define __HAL_RCC_C1_GPIOC_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN)
+#define __HAL_RCC_C1_GPIOD_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN)
+#define __HAL_RCC_C1_GPIOE_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN)
+#define __HAL_RCC_C1_GPIOF_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN)
+#define __HAL_RCC_C1_GPIOG_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN)
+#define __HAL_RCC_C1_GPIOH_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN)
+#define __HAL_RCC_C1_GPIOI_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN)
+#define __HAL_RCC_C1_GPIOJ_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN)
+#define __HAL_RCC_C1_GPIOK_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN)
+#define __HAL_RCC_C1_CRC_CLK_SLEEP_ENABLE()             (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN)
+#define __HAL_RCC_C1_BDMA_CLK_SLEEP_ENABLE()            (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN)
+#define __HAL_RCC_C1_ADC3_CLK_SLEEP_ENABLE()            (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN)
+#define __HAL_RCC_C1_BKPRAM_CLK_SLEEP_ENABLE()          (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN)
+#define __HAL_RCC_C1_D3SRAM1_CLK_SLEEP_ENABLE()         (RCC_C1->AHB4LPENR  |= (RCC_AHB4LPENR_D3SRAM1LPEN))
+
+#define __HAL_RCC_C1_GPIOA_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN)
+#define __HAL_RCC_C1_GPIOB_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN)
+#define __HAL_RCC_C1_GPIOC_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN)
+#define __HAL_RCC_C1_GPIOD_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN)
+#define __HAL_RCC_C1_GPIOE_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN)
+#define __HAL_RCC_C1_GPIOF_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN)
+#define __HAL_RCC_C1_GPIOG_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN)
+#define __HAL_RCC_C1_GPIOH_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN)
+#define __HAL_RCC_C1_GPIOI_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN)
+#define __HAL_RCC_C1_GPIOJ_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN)
+#define __HAL_RCC_C1_GPIOK_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN)
+#define __HAL_RCC_C1_CRC_CLK_SLEEP_DISABLE()             (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN)
+#define __HAL_RCC_C1_BDMA_CLK_SLEEP_DISABLE()            (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN)
+#define __HAL_RCC_C1_ADC3_CLK_SLEEP_DISABLE()            (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN)
+#define __HAL_RCC_C1_BKPRAM_CLK_SLEEP_DISABLE()          (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN)
+#define __HAL_RCC_C1_D3SRAM1_CLK_SLEEP_DISABLE()         (RCC_C1->AHB4LPENR  &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN))
+
+/** @brief  ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C1_LTDC_CLK_SLEEP_ENABLE()           (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN)
+#define __HAL_RCC_C1_DSI_CLK_SLEEP_ENABLE()            (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN)
+#define __HAL_RCC_C1_WWDG1_CLK_SLEEP_ENABLE()          (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN)
+
+#define __HAL_RCC_C1_LTDC_CLK_SLEEP_DISABLE()           (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN)
+#define __HAL_RCC_C1_DSI_CLK_SLEEP_DISABLE()            (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN)
+#define __HAL_RCC_C1_WWDG1_CLK_SLEEP_DISABLE()          (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN)
+
+/** @brief  ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C1_TIM2_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN)
+#define __HAL_RCC_C1_TIM3_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN)
+#define __HAL_RCC_C1_TIM4_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN)
+#define __HAL_RCC_C1_TIM5_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN)
+#define __HAL_RCC_C1_TIM6_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN)
+#define __HAL_RCC_C1_TIM7_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN)
+#define __HAL_RCC_C1_TIM12_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN)
+#define __HAL_RCC_C1_TIM13_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN)
+#define __HAL_RCC_C1_TIM14_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN)
+#define __HAL_RCC_C1_LPTIM1_CLK_SLEEP_ENABLE()         (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN)
+#define __HAL_RCC_C1_WWDG2_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN)
+#define __HAL_RCC_C1_SPI2_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN)
+#define __HAL_RCC_C1_SPI3_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN)
+#define __HAL_RCC_C1_SPDIFRX_CLK_SLEEP_ENABLE()        (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN)
+#define __HAL_RCC_C1_USART2_CLK_SLEEP_ENABLE()         (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN)
+#define __HAL_RCC_C1_USART3_CLK_SLEEP_ENABLE()         (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN)
+#define __HAL_RCC_C1_UART4_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN)
+#define __HAL_RCC_C1_UART5_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN)
+#define __HAL_RCC_C1_I2C1_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN)
+#define __HAL_RCC_C1_I2C2_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN)
+#define __HAL_RCC_C1_I2C3_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN)
+#define __HAL_RCC_C1_CEC_CLK_SLEEP_ENABLE()            (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN)
+#define __HAL_RCC_C1_DAC12_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN)
+#define __HAL_RCC_C1_UART7_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN)
+#define __HAL_RCC_C1_UART8_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN)
+#define __HAL_RCC_C1_CRS_CLK_SLEEP_ENABLE()            (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN)
+#define __HAL_RCC_C1_SWPMI_CLK_SLEEP_ENABLE()          (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN)
+#define __HAL_RCC_C1_OPAMP_CLK_SLEEP_ENABLE()          (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN)
+#define __HAL_RCC_C1_MDIOS_CLK_SLEEP_ENABLE()          (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN)
+#define __HAL_RCC_C1_FDCAN_CLK_SLEEP_ENABLE()          (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN)
+
+
+#define __HAL_RCC_C1_TIM2_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN)
+#define __HAL_RCC_C1_TIM3_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN)
+#define __HAL_RCC_C1_TIM4_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN)
+#define __HAL_RCC_C1_TIM5_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN)
+#define __HAL_RCC_C1_TIM6_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN)
+#define __HAL_RCC_C1_TIM7_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN)
+#define __HAL_RCC_C1_TIM12_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN)
+#define __HAL_RCC_C1_TIM13_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN)
+#define __HAL_RCC_C1_TIM14_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN)
+#define __HAL_RCC_C1_LPTIM1_CLK_SLEEP_DISABLE()         (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN)
+#define __HAL_RCC_C1_WWDG2_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN)
+#define __HAL_RCC_C1_SPI2_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN)
+#define __HAL_RCC_C1_SPI3_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN)
+#define __HAL_RCC_C1_SPDIFRX_CLK_SLEEP_DISABLE()        (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN)
+#define __HAL_RCC_C1_USART2_CLK_SLEEP_DISABLE()         (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN)
+#define __HAL_RCC_C1_USART3_CLK_SLEEP_DISABLE()         (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN)
+#define __HAL_RCC_C1_UART4_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN)
+#define __HAL_RCC_C1_UART5_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN)
+#define __HAL_RCC_C1_I2C1_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN)
+#define __HAL_RCC_C1_I2C2_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN)
+#define __HAL_RCC_C1_I2C3_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN)
+#define __HAL_RCC_C1_CEC_CLK_SLEEP_DISABLE()            (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN)
+#define __HAL_RCC_C1_DAC12_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN)
+#define __HAL_RCC_C1_UART7_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN)
+#define __HAL_RCC_C1_UART8_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN)
+#define __HAL_RCC_C1_CRS_CLK_SLEEP_DISABLE()            (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN)
+#define __HAL_RCC_C1_SWPMI_CLK_SLEEP_DISABLE()          (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN)
+#define __HAL_RCC_C1_OPAMP_CLK_SLEEP_DISABLE()          (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN)
+#define __HAL_RCC_C1_MDIOS_CLK_SLEEP_DISABLE()          (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN)
+#define __HAL_RCC_C1_FDCAN_CLK_SLEEP_DISABLE()          (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN)
+
+/** @brief  ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C1_TIM1_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN)
+#define __HAL_RCC_C1_TIM8_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN)
+#define __HAL_RCC_C1_USART1_CLK_SLEEP_ENABLE()         (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN)
+#define __HAL_RCC_C1_USART6_CLK_SLEEP_ENABLE()         (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN)
+#define __HAL_RCC_C1_SPI1_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN)
+#define __HAL_RCC_C1_SPI4_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN)
+#define __HAL_RCC_C1_TIM15_CLK_SLEEP_ENABLE()          (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN)
+#define __HAL_RCC_C1_TIM16_CLK_SLEEP_ENABLE()          (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN)
+#define __HAL_RCC_C1_TIM17_CLK_SLEEP_ENABLE()          (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN)
+#define __HAL_RCC_C1_SPI5_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN)
+#define __HAL_RCC_C1_SAI1_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN)
+#define __HAL_RCC_C1_SAI2_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN)
+#define __HAL_RCC_C1_SAI3_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN)
+#define __HAL_RCC_C1_DFSDM1_CLK_SLEEP_ENABLE()         (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN)
+#define __HAL_RCC_C1_HRTIM1_CLK_SLEEP_ENABLE()         (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN)
+
+#define __HAL_RCC_C1_TIM1_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN)
+#define __HAL_RCC_C1_TIM8_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN)
+#define __HAL_RCC_C1_USART1_CLK_SLEEP_DISABLE()         (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN)
+#define __HAL_RCC_C1_USART6_CLK_SLEEP_DISABLE()         (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN)
+#define __HAL_RCC_C1_SPI1_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN)
+#define __HAL_RCC_C1_SPI4_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN)
+#define __HAL_RCC_C1_TIM15_CLK_SLEEP_DISABLE()          (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN)
+#define __HAL_RCC_C1_TIM16_CLK_SLEEP_DISABLE()          (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN)
+#define __HAL_RCC_C1_TIM17_CLK_SLEEP_DISABLE()          (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN)
+#define __HAL_RCC_C1_SPI5_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN)
+#define __HAL_RCC_C1_SAI1_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN)
+#define __HAL_RCC_C1_SAI2_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN)
+#define __HAL_RCC_C1_SAI3_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN)
+#define __HAL_RCC_C1_DFSDM1_CLK_SLEEP_DISABLE()         (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN)
+#define __HAL_RCC_C1_HRTIM1_CLK_SLEEP_DISABLE()         (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN)
+
+/** @brief  ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C1_SYSCFG_CLK_SLEEP_ENABLE()           (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN)
+#define __HAL_RCC_C1_LPUART1_CLK_SLEEP_ENABLE()          (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN)
+#define __HAL_RCC_C1_SPI6_CLK_SLEEP_ENABLE()             (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN)
+#define __HAL_RCC_C1_I2C4_CLK_SLEEP_ENABLE()             (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN)
+#define __HAL_RCC_C1_LPTIM2_CLK_SLEEP_ENABLE()           (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN)
+#define __HAL_RCC_C1_LPTIM3_CLK_SLEEP_ENABLE()           (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN)
+#define __HAL_RCC_C1_LPTIM4_CLK_SLEEP_ENABLE()           (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN)
+#define __HAL_RCC_C1_LPTIM5_CLK_SLEEP_ENABLE()           (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN)
+#define __HAL_RCC_C1_COMP12_CLK_SLEEP_ENABLE()           (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN)
+#define __HAL_RCC_C1_VREF_CLK_SLEEP_ENABLE()             (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN)
+#define __HAL_RCC_C1_SAI4_CLK_SLEEP_ENABLE()             (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN)
+#define __HAL_RCC_C1_RTC_CLK_SLEEP_ENABLE()              (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN)
+
+
+#define __HAL_RCC_C1_SYSCFG_CLK_SLEEP_DISABLE()           (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN)
+#define __HAL_RCC_C1_LPUART1_CLK_SLEEP_DISABLE()          (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN)
+#define __HAL_RCC_C1_SPI6_CLK_SLEEP_DISABLE()             (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN)
+#define __HAL_RCC_C1_I2C4_CLK_SLEEP_DISABLE()             (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN)
+#define __HAL_RCC_C1_LPTIM2_CLK_SLEEP_DISABLE()           (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN)
+#define __HAL_RCC_C1_LPTIM3_CLK_SLEEP_DISABLE()           (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN)
+#define __HAL_RCC_C1_LPTIM4_CLK_SLEEP_DISABLE()           (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN)
+#define __HAL_RCC_C1_LPTIM5_CLK_SLEEP_DISABLE()           (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN)
+#define __HAL_RCC_C1_COMP12_CLK_SLEEP_DISABLE()           (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN)
+#define __HAL_RCC_C1_VREF_CLK_SLEEP_DISABLE()             (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN)
+#define __HAL_RCC_C1_SAI4_CLK_SLEEP_DISABLE()             (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN)
+#define __HAL_RCC_C1_RTC_CLK_SLEEP_DISABLE()              (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN)
+
+/** @brief  Enable or disable the RCC_C2 AHB3 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  */
+
+
+#define __HAL_RCC_C2_MDMA_CLK_SLEEP_ENABLE()            (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN))
+#define __HAL_RCC_C2_DMA2D_CLK_SLEEP_ENABLE()           (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN))
+#define __HAL_RCC_C2_JPGDEC_CLK_SLEEP_ENABLE()          (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN))
+#define __HAL_RCC_C2_FLASH_CLK_SLEEP_ENABLE()           (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN))
+#define __HAL_RCC_C2_FMC_CLK_SLEEP_ENABLE()             (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
+#define __HAL_RCC_C2_QSPI_CLK_SLEEP_ENABLE()            (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
+#define __HAL_RCC_C2_SDMMC1_CLK_SLEEP_ENABLE()          (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN))
+#define __HAL_RCC_C2_DTCM1_CLK_SLEEP_ENABLE()           (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN))
+#define __HAL_RCC_C2_DTCM2_CLK_SLEEP_ENABLE()           (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN))
+#define __HAL_RCC_C2_ITCM_CLK_SLEEP_ENABLE()            (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN))
+#define __HAL_RCC_C2_D1SRAM1_CLK_SLEEP_ENABLE()         (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN))
+
+
+#define __HAL_RCC_C2_MDMA_CLK_SLEEP_DISABLE()            (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN))
+#define __HAL_RCC_C2_DMA2D_CLK_SLEEP_DISABLE()           (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN))
+#define __HAL_RCC_C2_JPGDEC_CLK_SLEEP_DISABLE()          (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN))
+#define __HAL_RCC_C2_FLASH_CLK_SLEEP_DISABLE()           (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN))
+#define __HAL_RCC_C2_FMC_CLK_SLEEP_DISABLE()             (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN))
+#define __HAL_RCC_C2_QSPI_CLK_SLEEP_DISABLE()            (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN))
+#define __HAL_RCC_C2_SDMMC1_CLK_SLEEP_DISABLE()          (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN))
+#define __HAL_RCC_C2_DTCM1_CLK_SLEEP_DISABLE()           (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN))
+#define __HAL_RCC_C2_DTCM2_CLK_SLEEP_DISABLE()           (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN))
+#define __HAL_RCC_C2_ITCM_CLK_SLEEP_DISABLE()            (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN))
+#define __HAL_RCC_C2_D1SRAM1_CLK_SLEEP_DISABLE()         (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN))
+
+
+
+/** @brief  ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C2_DMA1_CLK_SLEEP_ENABLE()             (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
+#define __HAL_RCC_C2_DMA2_CLK_SLEEP_ENABLE()             (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
+#define __HAL_RCC_C2_ADC12_CLK_SLEEP_ENABLE()            (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN))
+#define __HAL_RCC_C2_ETH1MAC_CLK_SLEEP_ENABLE()          (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN))
+#define __HAL_RCC_C2_ETH1TX_CLK_SLEEP_ENABLE()           (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN))
+#define __HAL_RCC_C2_ETH1RX_CLK_SLEEP_ENABLE()           (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN))
+#define __HAL_RCC_C2_USB1_OTG_HS_CLK_SLEEP_ENABLE()      (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN))
+#define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
+#define __HAL_RCC_C2_USB2_OTG_FS_CLK_SLEEP_ENABLE()      (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN))
+#define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
+
+#define __HAL_RCC_C2_DMA1_CLK_SLEEP_DISABLE()             (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN))
+#define __HAL_RCC_C2_DMA2_CLK_SLEEP_DISABLE()             (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN))
+#define __HAL_RCC_C2_ADC12_CLK_SLEEP_DISABLE()            (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN))
+#define __HAL_RCC_C2_ETH1MAC_CLK_SLEEP_DISABLE()          (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN))
+#define __HAL_RCC_C2_ETH1TX_CLK_SLEEP_DISABLE()           (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN))
+#define __HAL_RCC_C2_ETH1RX_CLK_SLEEP_DISABLE()           (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN))
+#define __HAL_RCC_C2_USB1_OTG_HS_CLK_SLEEP_DISABLE()      (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN))
+#define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
+#define __HAL_RCC_C2_USB2_OTG_FS_CLK_SLEEP_DISABLE()      (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN))
+#define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
+
+/** @brief  ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C2_DCMI_CLK_SLEEP_ENABLE()             (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
+#if defined(CRYP)
+#define __HAL_RCC_C2_CRYP_CLK_SLEEP_ENABLE()             (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_C2_HASH_CLK_SLEEP_ENABLE()             (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
+#endif /* HASH */
+#define __HAL_RCC_C2_RNG_CLK_SLEEP_ENABLE()              (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
+#define __HAL_RCC_C2_SDMMC2_CLK_SLEEP_ENABLE()           (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))
+#define __HAL_RCC_C2_D2SRAM1_CLK_SLEEP_ENABLE()          (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN))
+#define __HAL_RCC_C2_D2SRAM2_CLK_SLEEP_ENABLE()          (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN))
+#define __HAL_RCC_C2_D2SRAM3_CLK_SLEEP_ENABLE()          (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN))
+
+#define __HAL_RCC_C2_DCMI_CLK_SLEEP_DISABLE()             (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))
+#if defined(CRYP)
+#define __HAL_RCC_C2_CRYP_CLK_SLEEP_DISABLE()             (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))
+#endif /* CRYP */
+#if defined(HASH)
+#define __HAL_RCC_C2_HASH_CLK_SLEEP_DISABLE()             (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))
+#endif /* HASH */
+#define __HAL_RCC_C2_RNG_CLK_SLEEP_DISABLE()              (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))
+#define __HAL_RCC_C2_SDMMC2_CLK_SLEEP_DISABLE()           (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))
+#define __HAL_RCC_C2_D2SRAM1_CLK_SLEEP_DISABLE()          (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN))
+#define __HAL_RCC_C2_D2SRAM2_CLK_SLEEP_DISABLE()          (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN))
+#define __HAL_RCC_C2_D2SRAM3_CLK_SLEEP_DISABLE()          (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN))
+
+/** @brief  ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C2_GPIOA_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN)
+#define __HAL_RCC_C2_GPIOB_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN)
+#define __HAL_RCC_C2_GPIOC_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN)
+#define __HAL_RCC_C2_GPIOD_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN)
+#define __HAL_RCC_C2_GPIOE_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN)
+#define __HAL_RCC_C2_GPIOF_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN)
+#define __HAL_RCC_C2_GPIOG_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN)
+#define __HAL_RCC_C2_GPIOH_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN)
+#define __HAL_RCC_C2_GPIOI_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN)
+#define __HAL_RCC_C2_GPIOJ_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN)
+#define __HAL_RCC_C2_GPIOK_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN)
+#define __HAL_RCC_C2_CRC_CLK_SLEEP_ENABLE()             (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN)
+#define __HAL_RCC_C2_BDMA_CLK_SLEEP_ENABLE()            (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN)
+#define __HAL_RCC_C2_ADC3_CLK_SLEEP_ENABLE()            (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN)
+#define __HAL_RCC_C2_BKPRAM_CLK_SLEEP_ENABLE()          (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN)
+#define __HAL_RCC_C2_D3SRAM1_CLK_SLEEP_ENABLE()         (RCC_C2->AHB4LPENR  |= (RCC_AHB4LPENR_D3SRAM1LPEN))
+
+#define __HAL_RCC_C2_GPIOA_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN)
+#define __HAL_RCC_C2_GPIOB_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN)
+#define __HAL_RCC_C2_GPIOC_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN)
+#define __HAL_RCC_C2_GPIOD_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN)
+#define __HAL_RCC_C2_GPIOE_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN)
+#define __HAL_RCC_C2_GPIOF_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN)
+#define __HAL_RCC_C2_GPIOG_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN)
+#define __HAL_RCC_C2_GPIOH_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN)
+#define __HAL_RCC_C2_GPIOI_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN)
+#define __HAL_RCC_C2_GPIOJ_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN)
+#define __HAL_RCC_C2_GPIOK_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN)
+#define __HAL_RCC_C2_CRC_CLK_SLEEP_DISABLE()             (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN)
+#define __HAL_RCC_C2_BDMA_CLK_SLEEP_DISABLE()            (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN)
+#define __HAL_RCC_C2_ADC3_CLK_SLEEP_DISABLE()            (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN)
+#define __HAL_RCC_C2_BKPRAM_CLK_SLEEP_DISABLE()          (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN)
+#define __HAL_RCC_C2_D3SRAM1_CLK_SLEEP_DISABLE()         (RCC_C2->AHB4LPENR  &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN))
+
+/** @brief  ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C2_LTDC_CLK_SLEEP_ENABLE()           (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN)
+#define __HAL_RCC_C2_DSI_CLK_SLEEP_ENABLE()            (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN)
+#define __HAL_RCC_C2_WWDG1_CLK_SLEEP_ENABLE()          (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN)
+
+#define __HAL_RCC_C2_LTDC_CLK_SLEEP_DISABLE()           (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN)
+#define __HAL_RCC_C2_DSI_CLK_SLEEP_DISABLE()            (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN)
+#define __HAL_RCC_C2_WWDG1_CLK_SLEEP_DISABLE()          (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN)
+
+/** @brief  ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C2_TIM2_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN)
+#define __HAL_RCC_C2_TIM3_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN)
+#define __HAL_RCC_C2_TIM4_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN)
+#define __HAL_RCC_C2_TIM5_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN)
+#define __HAL_RCC_C2_TIM6_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN)
+#define __HAL_RCC_C2_TIM7_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN)
+#define __HAL_RCC_C2_TIM12_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN)
+#define __HAL_RCC_C2_TIM13_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN)
+#define __HAL_RCC_C2_TIM14_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN)
+#define __HAL_RCC_C2_LPTIM1_CLK_SLEEP_ENABLE()         (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN)
+#define __HAL_RCC_C2_WWDG2_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN)
+#define __HAL_RCC_C2_SPI2_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN)
+#define __HAL_RCC_C2_SPI3_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN)
+#define __HAL_RCC_C2_SPDIFRX_CLK_SLEEP_ENABLE()        (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN)
+#define __HAL_RCC_C2_USART2_CLK_SLEEP_ENABLE()         (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN)
+#define __HAL_RCC_C2_USART3_CLK_SLEEP_ENABLE()         (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN)
+#define __HAL_RCC_C2_UART4_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN)
+#define __HAL_RCC_C2_UART5_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN)
+#define __HAL_RCC_C2_I2C1_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN)
+#define __HAL_RCC_C2_I2C2_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN)
+#define __HAL_RCC_C2_I2C3_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN)
+#define __HAL_RCC_C2_CEC_CLK_SLEEP_ENABLE()            (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN)
+#define __HAL_RCC_C2_DAC12_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN)
+#define __HAL_RCC_C2_UART7_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN)
+#define __HAL_RCC_C2_UART8_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN)
+#define __HAL_RCC_C2_CRS_CLK_SLEEP_ENABLE()            (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN)
+#define __HAL_RCC_C2_SWPMI_CLK_SLEEP_ENABLE()          (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN)
+#define __HAL_RCC_C2_OPAMP_CLK_SLEEP_ENABLE()          (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN)
+#define __HAL_RCC_C2_MDIOS_CLK_SLEEP_ENABLE()          (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN)
+#define __HAL_RCC_C2_FDCAN_CLK_SLEEP_ENABLE()          (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN)
+
+
+#define __HAL_RCC_C2_TIM2_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN)
+#define __HAL_RCC_C2_TIM3_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN)
+#define __HAL_RCC_C2_TIM4_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN)
+#define __HAL_RCC_C2_TIM5_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN)
+#define __HAL_RCC_C2_TIM6_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN)
+#define __HAL_RCC_C2_TIM7_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN)
+#define __HAL_RCC_C2_TIM12_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN)
+#define __HAL_RCC_C2_TIM13_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN)
+#define __HAL_RCC_C2_TIM14_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN)
+#define __HAL_RCC_C2_LPTIM1_CLK_SLEEP_DISABLE()         (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN)
+#define __HAL_RCC_C2_WWDG2_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN)
+#define __HAL_RCC_C2_SPI2_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN)
+#define __HAL_RCC_C2_SPI3_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN)
+#define __HAL_RCC_C2_SPDIFRX_CLK_SLEEP_DISABLE()        (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN)
+#define __HAL_RCC_C2_USART2_CLK_SLEEP_DISABLE()         (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN)
+#define __HAL_RCC_C2_USART3_CLK_SLEEP_DISABLE()         (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN)
+#define __HAL_RCC_C2_UART4_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN)
+#define __HAL_RCC_C2_UART5_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN)
+#define __HAL_RCC_C2_I2C1_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN)
+#define __HAL_RCC_C2_I2C2_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN)
+#define __HAL_RCC_C2_I2C3_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN)
+#define __HAL_RCC_C2_CEC_CLK_SLEEP_DISABLE()            (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN)
+#define __HAL_RCC_C2_DAC12_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN)
+#define __HAL_RCC_C2_UART7_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN)
+#define __HAL_RCC_C2_UART8_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN)
+#define __HAL_RCC_C2_CRS_CLK_SLEEP_DISABLE()            (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN)
+#define __HAL_RCC_C2_SWPMI_CLK_SLEEP_DISABLE()          (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN)
+#define __HAL_RCC_C2_OPAMP_CLK_SLEEP_DISABLE()          (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN)
+#define __HAL_RCC_C2_MDIOS_CLK_SLEEP_DISABLE()          (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN)
+#define __HAL_RCC_C2_FDCAN_CLK_SLEEP_DISABLE()          (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN)
+
+/** @brief  ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C2_TIM1_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN)
+#define __HAL_RCC_C2_TIM8_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN)
+#define __HAL_RCC_C2_USART1_CLK_SLEEP_ENABLE()         (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN)
+#define __HAL_RCC_C2_USART6_CLK_SLEEP_ENABLE()         (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN)
+#define __HAL_RCC_C2_SPI1_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN)
+#define __HAL_RCC_C2_SPI4_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN)
+#define __HAL_RCC_C2_TIM15_CLK_SLEEP_ENABLE()          (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN)
+#define __HAL_RCC_C2_TIM16_CLK_SLEEP_ENABLE()          (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN)
+#define __HAL_RCC_C2_TIM17_CLK_SLEEP_ENABLE()          (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN)
+#define __HAL_RCC_C2_SPI5_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN)
+#define __HAL_RCC_C2_SAI1_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN)
+#define __HAL_RCC_C2_SAI2_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN)
+#define __HAL_RCC_C2_SAI3_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN)
+#define __HAL_RCC_C2_DFSDM1_CLK_SLEEP_ENABLE()         (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN)
+#define __HAL_RCC_C2_HRTIM1_CLK_SLEEP_ENABLE()         (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN)
+
+#define __HAL_RCC_C2_TIM1_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN)
+#define __HAL_RCC_C2_TIM8_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN)
+#define __HAL_RCC_C2_USART1_CLK_SLEEP_DISABLE()         (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN)
+#define __HAL_RCC_C2_USART6_CLK_SLEEP_DISABLE()         (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN)
+#define __HAL_RCC_C2_SPI1_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN)
+#define __HAL_RCC_C2_SPI4_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN)
+#define __HAL_RCC_C2_TIM15_CLK_SLEEP_DISABLE()          (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN)
+#define __HAL_RCC_C2_TIM16_CLK_SLEEP_DISABLE()          (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN)
+#define __HAL_RCC_C2_TIM17_CLK_SLEEP_DISABLE()          (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN)
+#define __HAL_RCC_C2_SPI5_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN)
+#define __HAL_RCC_C2_SAI1_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN)
+#define __HAL_RCC_C2_SAI2_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN)
+#define __HAL_RCC_C2_SAI3_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN)
+#define __HAL_RCC_C2_DFSDM1_CLK_SLEEP_DISABLE()         (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN)
+#define __HAL_RCC_C2_HRTIM1_CLK_SLEEP_DISABLE()         (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN)
+
+/** @brief  ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.
+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.
+  */
+
+#define __HAL_RCC_C2_SYSCFG_CLK_SLEEP_ENABLE()           (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN)
+#define __HAL_RCC_C2_LPUART1_CLK_SLEEP_ENABLE()          (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN)
+#define __HAL_RCC_C2_SPI6_CLK_SLEEP_ENABLE()             (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN)
+#define __HAL_RCC_C2_I2C4_CLK_SLEEP_ENABLE()             (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN)
+#define __HAL_RCC_C2_LPTIM2_CLK_SLEEP_ENABLE()           (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN)
+#define __HAL_RCC_C2_LPTIM3_CLK_SLEEP_ENABLE()           (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN)
+#define __HAL_RCC_C2_LPTIM4_CLK_SLEEP_ENABLE()           (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN)
+#define __HAL_RCC_C2_LPTIM5_CLK_SLEEP_ENABLE()           (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN)
+#define __HAL_RCC_C2_COMP12_CLK_SLEEP_ENABLE()           (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN)
+#define __HAL_RCC_C2_VREF_CLK_SLEEP_ENABLE()             (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN)
+#define __HAL_RCC_C2_SAI4_CLK_SLEEP_ENABLE()             (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN)
+#define __HAL_RCC_C2_RTC_CLK_SLEEP_ENABLE()              (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN)
+
+#define __HAL_RCC_C2_SYSCFG_CLK_SLEEP_DISABLE()           (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN)
+#define __HAL_RCC_C2_LPUART1_CLK_SLEEP_DISABLE()          (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN)
+#define __HAL_RCC_C2_SPI6_CLK_SLEEP_DISABLE()             (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN)
+#define __HAL_RCC_C2_I2C4_CLK_SLEEP_DISABLE()             (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN)
+#define __HAL_RCC_C2_LPTIM2_CLK_SLEEP_DISABLE()           (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN)
+#define __HAL_RCC_C2_LPTIM3_CLK_SLEEP_DISABLE()           (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN)
+#define __HAL_RCC_C2_LPTIM4_CLK_SLEEP_DISABLE()           (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN)
+#define __HAL_RCC_C2_LPTIM5_CLK_SLEEP_DISABLE()           (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN)
+#define __HAL_RCC_C2_COMP12_CLK_SLEEP_DISABLE()           (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN)
+#define __HAL_RCC_C2_VREF_CLK_SLEEP_DISABLE()             (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN)
+#define __HAL_RCC_C2_SAI4_CLK_SLEEP_DISABLE()             (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN)
+#define __HAL_RCC_C2_RTC_CLK_SLEEP_DISABLE()              (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN)
+
+#endif /*DUAL_CORE*/
+
+#if defined(DUAL_CORE)
+/** @brief  Enable or disable peripheral bus clock  when D3 domain is in DRUN
+  * @note   After reset (default config), peripheral clock is disabled when both CPUs are in CSTOP
+  */
+#else
+/** @brief  Enable or disable peripheral bus clock  when D3 domain is in DRUN
+  * @note   After reset (default config), peripheral clock is disabled when CPU is in CSTOP
+  */
+#endif /*DUAL_CORE*/
+
+#if defined(RCC_D3AMR_BDMAAMEN)
+#define __HAL_RCC_BDMA_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_BDMAAMEN)
+#endif
+#if defined(RCC_D3AMR_LPUART1AMEN)
+#define __HAL_RCC_LPUART1_CLKAM_ENABLE()          (RCC->D3AMR) |= (RCC_D3AMR_LPUART1AMEN)
+#endif
+#if defined(RCC_D3AMR_SPI6AMEN)
+#define __HAL_RCC_SPI6_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_SPI6AMEN)
+#endif
+#if defined(RCC_D3AMR_I2C4AMEN)
+#define __HAL_RCC_I2C4_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_I2C4AMEN)
+#endif
+#if defined(RCC_D3AMR_LPTIM2AMEN)
+#define __HAL_RCC_LPTIM2_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_LPTIM2AMEN)
+#endif
+#if defined(RCC_D3AMR_LPTIM3AMEN)
+#define __HAL_RCC_LPTIM3_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_LPTIM3AMEN)
+#endif
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_LPTIM4AMEN)
+#endif
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_LPTIM5AMEN)
+#endif
+#if defined(RCC_D3AMR_COMP12AMEN)
+#define __HAL_RCC_COMP12_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_COMP12AMEN)
+#endif
+#if defined(RCC_D3AMR_VREFAMEN)
+#define __HAL_RCC_VREF_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_VREFAMEN)
+#endif
+#if defined(RCC_D3AMR_RTCAMEN)
+#define __HAL_RCC_RTC_CLKAM_ENABLE()              (RCC->D3AMR) |= (RCC_D3AMR_RTCAMEN)
+#endif
+#if defined(RCC_D3AMR_CRCAMEN)
+#define __HAL_RCC_CRC_CLKAM_ENABLE()              (RCC->D3AMR) |= (RCC_D3AMR_CRCAMEN)
+#endif
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_SAI4AMEN)
+#endif
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_ADC3AMEN)
+#endif
+#if defined(RCC_D3AMR_BKPRAMAMEN)
+#define __HAL_RCC_BKPRAM_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_BKPRAMAMEN)
+#endif
+#if defined(RCC_D3AMR_SRAM4AMEN)
+#define __HAL_RCC_D3SRAM1_CLKAM_ENABLE()          (RCC->D3AMR) |= (RCC_D3AMR_SRAM4AMEN)
+#endif
+
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_CLKAM_ENABLE()            (RCC->SRDAMR) |= (RCC_SRDAMR_BDMA2AMEN)
+#endif
+#if defined(RCC_SRDAMR_GPIOAMEN)
+#define __HAL_RCC_GPIO_CLKAM_ENABLE()             (RCC->SRDAMR) |= (RCC_SRDAMR_GPIOAMEN)
+#endif
+#if defined(RCC_SRDAMR_LPUART1AMEN)
+#define __HAL_RCC_LPUART1_CLKAM_ENABLE()          (RCC->SRDAMR) |= (RCC_SRDAMR_LPUART1AMEN)
+#endif
+#if defined(RCC_SRDAMR_SPI6AMEN)
+#define __HAL_RCC_SPI6_CLKAM_ENABLE()             (RCC->SRDAMR) |= (RCC_SRDAMR_SPI6AMEN)
+#endif
+#if defined(RCC_SRDAMR_I2C4AMEN)
+#define __HAL_RCC_I2C4_CLKAM_ENABLE()             (RCC->SRDAMR) |= (RCC_SRDAMR_I2C4AMEN)
+#endif
+#if defined(RCC_SRDAMR_LPTIM2AMEN)
+#define __HAL_RCC_LPTIM2_CLKAM_ENABLE()           (RCC->SRDAMR) |= (RCC_SRDAMR_LPTIM2AMEN)
+#endif
+#if defined(RCC_SRDAMR_LPTIM3AMEN)
+#define __HAL_RCC_LPTIM3_CLKAM_ENABLE()           (RCC->SRDAMR) |= (RCC_SRDAMR_LPTIM3AMEN)
+#endif
+#if defined(DAC2)
+#define __HAL_RCC_DAC2_CLKAM_ENABLE()             (RCC->SRDAMR) |= (RCC_SRDAMR_DAC2AMEN)
+#endif
+#if defined(RCC_SRDAMR_COMP12AMEN)
+#define __HAL_RCC_COMP12_CLKAM_ENABLE()           (RCC->SRDAMR) |= (RCC_SRDAMR_COMP12AMEN)
+#endif
+#if defined(RCC_SRDAMR_VREFAMEN)
+#define __HAL_RCC_VREF_CLKAM_ENABLE()             (RCC->SRDAMR) |= (RCC_SRDAMR_VREFAMEN)
+#endif
+#if defined(RCC_SRDAMR_RTCAMEN)
+#define __HAL_RCC_RTC_CLKAM_ENABLE()              (RCC->SRDAMR) |= (RCC_SRDAMR_RTCAMEN)
+#endif
+#if defined(RCC_SRDAMR_DTSAMEN)
+#define __HAL_RCC_DTS_CLKAM_ENABLE()              (RCC->SRDAMR) |= (RCC_SRDAMR_DTSAMEN)
+#endif
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_CLKAM_ENABLE()           (RCC->SRDAMR) |= (RCC_SRDAMR_DFSDM2AMEN)
+#endif
+#if defined(RCC_SRDAMR_BKPRAMAMEN)
+#define __HAL_RCC_BKPRAM_CLKAM_ENABLE()           (RCC->SRDAMR) |= (RCC_SRDAMR_BKPRAMAMEN)
+#endif
+#if defined(RCC_SRDAMR_SRDSRAMAMEN)
+#define __HAL_RCC_SRDSRAM_CLKAM_ENABLE()          (RCC->SRDAMR) |= (RCC_SRDAMR_SRDSRAMAMEN)
+#endif
+
+#if defined(RCC_D3AMR_BDMAAMEN)
+#define __HAL_RCC_BDMA_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_BDMAAMEN)
+#endif
+#if defined(RCC_D3AMR_LPUART1AMEN)
+#define __HAL_RCC_LPUART1_CLKAM_DISABLE()          (RCC->D3AMR) &= ~ (RCC_D3AMR_LPUART1AMEN)
+#endif
+#if defined(RCC_D3AMR_SPI6AMEN)
+#define __HAL_RCC_SPI6_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_SPI6AMEN)
+#endif
+#if defined(RCC_D3AMR_I2C4AMEN)
+#define __HAL_RCC_I2C4_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_I2C4AMEN)
+#endif
+#if defined(RCC_D3AMR_LPTIM2AMEN)
+#define __HAL_RCC_LPTIM2_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM2AMEN)
+#endif
+#if defined(RCC_D3AMR_LPTIM3AMEN)
+#define __HAL_RCC_LPTIM3_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM3AMEN)
+#endif
+#if defined(LPTIM4)
+#define __HAL_RCC_LPTIM4_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM4AMEN)
+#endif
+#if defined(LPTIM5)
+#define __HAL_RCC_LPTIM5_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM5AMEN)
+#endif
+#if defined(RCC_D3AMR_COMP12AMEN)
+#define __HAL_RCC_COMP12_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_COMP12AMEN)
+#endif
+#if defined(RCC_D3AMR_VREFAMEN)
+#define __HAL_RCC_VREF_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_VREFAMEN)
+#endif
+#if defined(RCC_D3AMR_RTCAMEN)
+#define __HAL_RCC_RTC_CLKAM_DISABLE()              (RCC->D3AMR) &= ~ (RCC_D3AMR_RTCAMEN)
+#endif
+#if defined(RCC_D3AMR_CRCAMEN)
+#define __HAL_RCC_CRC_CLKAM_DISABLE()              (RCC->D3AMR) &= ~ (RCC_D3AMR_CRCAMEN)
+#endif
+#if defined(SAI4)
+#define __HAL_RCC_SAI4_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_SAI4AMEN)
+#endif
+#if defined(ADC3)
+#define __HAL_RCC_ADC3_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_ADC3AMEN)
+#endif
+#if defined(RCC_D3AMR_BKPRAMAMEN)
+#define __HAL_RCC_BKPRAM_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_BKPRAMAMEN)
+#endif
+#if defined(RCC_D3AMR_SRAM4AMEN)
+#define __HAL_RCC_D3SRAM1_CLKAM_DISABLE()          (RCC->D3AMR)&= ~ (RCC_D3AMR_SRAM4AMEN)
+#endif
+
+#if defined(BDMA2)
+#define __HAL_RCC_BDMA2_CLKAM_DISABLE()            (RCC->SRDAMR) &= ~ (RCC_SRDAMR_BDMA2AMEN)
+#endif
+#if defined(RCC_SRDAMR_GPIOAMEN)
+#define __HAL_RCC_GPIO_CLKAM_DISABLE()             (RCC->SRDAMR) &= ~ (RCC_SRDAMR_GPIOAMEN)
+#endif
+#if defined(RCC_SRDAMR_LPUART1AMEN)
+#define __HAL_RCC_LPUART1_CLKAM_DISABLE()          (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPUART1AMEN)
+#endif
+#if defined(RCC_SRDAMR_SPI6AMEN)
+#define __HAL_RCC_SPI6_CLKAM_DISABLE()             (RCC->SRDAMR) &= ~ (RCC_SRDAMR_SPI6AMEN)
+#endif
+#if defined(RCC_SRDAMR_I2C4AMEN)
+#define __HAL_RCC_I2C4_CLKAM_DISABLE()             (RCC->SRDAMR) &= ~ (RCC_SRDAMR_I2C4AMEN)
+#endif
+#if defined(RCC_SRDAMR_LPTIM2AMEN)
+#define __HAL_RCC_LPTIM2_CLKAM_DISABLE()           (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPTIM2AMEN)
+#endif
+#if defined(RCC_SRDAMR_LPTIM3AMEN)
+#define __HAL_RCC_LPTIM3_CLKAM_DISABLE()           (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPTIM3AMEN)
+#endif
+#if defined(RCC_SRDAMR_DAC2AMEN)
+#define __HAL_RCC_DAC2_CLKAM_DISABLE()             (RCC->SRDAMR) &= ~ (RCC_SRDAMR_DAC2AMEN)
+#endif
+#if defined(RCC_SRDAMR_COMP12AMEN)
+#define __HAL_RCC_COMP12_CLKAM_DISABLE()           (RCC->SRDAMR) &= ~ (RCC_SRDAMR_COMP12AMEN)
+#endif
+#if defined(RCC_SRDAMR_VREFAMEN)
+#define __HAL_RCC_VREF_CLKAM_DISABLE()             (RCC->SRDAMR) &= ~ (RCC_SRDAMR_VREFAMEN)
+#endif
+#if defined(RCC_SRDAMR_RTCAMEN)
+#define __HAL_RCC_RTC_CLKAM_DISABLE()              (RCC->SRDAMR) &= ~(RCC_SRDAMR_RTCAMEN)
+#endif
+#if defined(RCC_SRDAMR_DTSAMEN)
+#define __HAL_RCC_DTS_CLKAM_DISABLE()              (RCC->SRDAMR) &= ~(RCC_SRDAMR_DTSAMEN)
+#endif
+#if defined(DFSDM2_BASE)
+#define __HAL_RCC_DFSDM2_CLKAM_DISABLE()           (RCC->SRDAMR) &= ~(RCC_SRDAMR_DFSDM2AMEN)
+#endif
+#if defined(RCC_SRDAMR_BKPRAMAMEN)
+#define __HAL_RCC_BKPRAM_CLKAM_DISABLE()           (RCC->SRDAMR) &= ~ (RCC_SRDAMR_BKPRAMAMEN)
+#endif
+#if defined(RCC_SRDAMR_SRDSRAMAMEN)
+#define __HAL_RCC_SRDSRAM_CLKAM_DISABLE()          (RCC->SRDAMR) &= ~ (RCC_SRDAMR_SRDSRAMAMEN)
+#endif
+
+
+#if defined(RCC_CKGAENR_AXICKG)
+    /** @brief  Macro to enable or disable the RCC_CKGAENR bits (AXI clocks gating enable register).
+  * @note
+  * @note
+  * @note
+  * @param
+  * @note
+  */
+
+#define __HAL_RCC_AXI_CLKGA_ENABLE()             (RCC->CKGAENR) |= (RCC_CKGAENR_AXICKG)
+#define __HAL_RCC_AHB_CLKGA_ENABLE()             (RCC->CKGAENR) |= (RCC_CKGAENR_AHBCKG)
+#define __HAL_RCC_CPU_CLKGA_ENABLE()             (RCC->CKGAENR) |= (RCC_CKGAENR_CPUCKG)
+#define __HAL_RCC_SDMMC_CLKGA_ENABLE()           (RCC->CKGAENR) |= (RCC_CKGAENR_SDMMCCKG)
+#define __HAL_RCC_MDMA_CLKGA_ENABLE()            (RCC->CKGAENR) |= (RCC_CKGAENR_MDMACKG)
+#define __HAL_RCC_DMA2D_CLKGA_ENABLE()           (RCC->CKGAENR) |= (RCC_CKGAENR_DMA2DCKG)
+#define __HAL_RCC_LTDC_CLKGA_ENABLE()            (RCC->CKGAENR) |= (RCC_CKGAENR_LTDCCKG)
+#define __HAL_RCC_GFXMMUM_CLKGA_ENABLE()         (RCC->CKGAENR) |= (RCC_CKGAENR_GFXMMUMCKG)
+#define __HAL_RCC_AHB12_CLKGA_ENABLE()           (RCC->CKGAENR) |= (RCC_CKGAENR_AHB12CKG)
+#define __HAL_RCC_AHB34_CLKGA_ENABLE()           (RCC->CKGAENR) |= (RCC_CKGAENR_AHB34CKG)
+#define __HAL_RCC_FLIFT_CLKGA_ENABLE()           (RCC->CKGAENR) |= (RCC_CKGAENR_FLIFTCKG)
+#define __HAL_RCC_OCTOSPI2_CLKGA_ENABLE()        (RCC->CKGAENR) |= (RCC_CKGAENR_OCTOSPI2CKG)
+#define __HAL_RCC_FMC_CLKGA_ENABLE()             (RCC->CKGAENR) |= (RCC_CKGAENR_FMCCKG)
+#define __HAL_RCC_OCTOSPI1_CLKGA_ENABLE()        (RCC->CKGAENR) |= (RCC_CKGAENR_OCTOSPI1CKG)
+#define __HAL_RCC_AXIRAM1_CLKGA_ENABLE()         (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM1CKG)
+#define __HAL_RCC_AXIRAM2_CLKGA_ENABLE()         (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM2CKG)
+#define __HAL_RCC_AXIRAM3_CLKGA_ENABLE()         (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM3CKG)
+#define __HAL_RCC_GFXMMUS_CLKGA_ENABLE()         (RCC->CKGAENR) |= (RCC_CKGAENR_GFXMMUSCKG)
+#define __HAL_RCC_ECCRAM_CLKGA_ENABLE()          (RCC->CKGAENR) |= (RCC_CKGAENR_ECCRAMCKG)
+#define __HAL_RCC_EXTI_CLKGA_ENABLE()            (RCC->CKGAENR) |= (RCC_CKGAENR_EXTICKG)
+#define __HAL_RCC_JTAG_CLKGA_ENABLE()            (RCC->CKGAENR) |= (RCC_CKGAENR_JTAGCKG)
+
+
+#define __HAL_RCC_AXI_CLKGA_DISABLE()             (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXICKG)
+#define __HAL_RCC_AHB_CLKGA_DISABLE()             (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHBCKG)
+#define __HAL_RCC_CPU_CLKGA_DISABLE()             (RCC->CKGAENR) &= ~ (RCC_CKGAENR_CPUCKG)
+#define __HAL_RCC_SDMMC_CLKGA_DISABLE()           (RCC->CKGAENR) &= ~ (RCC_CKGAENR_SDMMCCKG)
+#define __HAL_RCC_MDMA_CLKGA_DISABLE()            (RCC->CKGAENR) &= ~ (RCC_CKGAENR_MDMACKG)
+#define __HAL_RCC_DMA2D_CLKGA_DISABLE()           (RCC->CKGAENR) &= ~ (RCC_CKGAENR_DMA2DCKG)
+#define __HAL_RCC_LTDC_CLKGA_DISABLE()            (RCC->CKGAENR) &= ~ (RCC_CKGAENR_LTDCCKG)
+#define __HAL_RCC_GFXMMUM_CLKGA_DISABLE()         (RCC->CKGAENR) &= ~ (RCC_CKGAENR_GFXMMUMCKG)
+#define __HAL_RCC_AHB12_CLKGA_DISABLE()           (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHB12CKG)
+#define __HAL_RCC_AHB34_CLKGA_DISABLE()           (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHB34CKG)
+#define __HAL_RCC_FLIFT_CLKGA_DISABLE()           (RCC->CKGAENR) &= ~ (RCC_CKGAENR_FLIFTCKG)
+#define __HAL_RCC_OCTOSPI2_CLKGA_DISABLE()        (RCC->CKGAENR) &= ~ (RCC_CKGAENR_OCTOSPI2CKG)
+#define __HAL_RCC_FMC_CLKGA_DISABLE()             (RCC->CKGAENR) &= ~ (RCC_CKGAENR_FMCCKG)
+#define __HAL_RCC_OCTOSPI1_CLKGA_DISABLE()        (RCC->CKGAENR) &= ~ (RCC_CKGAENR_OCTOSPI1CKG)
+#define __HAL_RCC_AXIRAM1_CLKGA_DISABLE()         (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM1CKG)
+#define __HAL_RCC_AXIRAM2_CLKGA_DISABLE()         (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM2CKG)
+#define __HAL_RCC_AXIRAM3_CLKGA_DISABLE()         (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM3CKG)
+#define __HAL_RCC_GFXMMUS_CLKGA_DISABLE()         (RCC->CKGAENR) &= ~ (RCC_CKGAENR_GFXMMUSCKG)
+#define __HAL_RCC_ECCRAM_CLKGA_DISABLE()          (RCC->CKGAENR) &= ~ (RCC_CKGAENR_ECCRAMCKG)
+#define __HAL_RCC_EXTI_CLKGA_DISABLE()            (RCC->CKGAENR) &= ~ (RCC_CKGAENR_EXTICKG)
+#define __HAL_RCC_JTAG_CLKGA_DISABLE()            (RCC->CKGAENR) &= ~ (RCC_CKGAENR_JTAGCKG)
+
+#endif /* RCC_CKGAENR_AXICKG */
+
+
+
+
+/** @brief  Macro to enable or disable the Internal High Speed oscillator (HSI).
+  * @note     After enabling the HSI, the application software should wait on
+  *           HSIRDY flag to be set indicating that HSI clock is stable and can
+  *           be used to clock the PLL and/or system clock.
+  * @note     HSI can not be stopped if it is used directly or through the PLL
+  *           as system clock. In this case, you have to select another source
+  *           of the system clock then stop the HSI.
+  * @note     The HSI is stopped by hardware when entering STOP and STANDBY modes.
+  * @param    __STATE__ specifies the new state of the HSI.
+  *           This parameter can be one of the following values:
+  *            @arg RCC_HSI_OFF turn OFF the HSI oscillator
+  *            @arg RCC_HSI_ON turn ON the HSI oscillator
+  *            @arg RCC_HSI_DIV1 turn ON the HSI oscillator and divide it by 1 (default after reset)
+  *            @arg RCC_HSI_DIV2 turn ON the HSI oscillator and divide it by 2
+  *            @arg RCC_HSI_DIV4 turn ON the HSI oscillator and divide it by 4
+  *            @arg RCC_HSI_DIV8 turn ON the HSI oscillator and divide it by 8
+  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
+  *         clock cycles.
+  */
+#define __HAL_RCC_HSI_CONFIG(__STATE__) \
+                  MODIFY_REG(RCC->CR, RCC_CR_HSION | RCC_CR_HSIDIV , (uint32_t)(__STATE__))
+
+
+/** @brief  Macro to get the HSI divider.
+  * @retval The HSI divider. The returned value can be one
+  *         of the following:
+  *            - RCC_CR_HSIDIV_1  HSI oscillator divided by 1 (default after reset)
+  *            - RCC_CR_HSIDIV_2  HSI oscillator divided by 2
+  *            - RCC_CR_HSIDIV_4  HSI oscillator divided by 4
+  *            - RCC_CR_HSIDIV_8  HSI oscillator divided by 8
+  */
+#define __HAL_RCC_GET_HSI_DIVIDER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV)))
+
+/** @brief  Macros to enable or disable the Internal High Speed oscillator (HSI).
+  * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
+  *         It is used (enabled by hardware) as system clock source after start-up
+  *         from Reset, wakeup from STOP and STANDBY mode, or in case of failure
+  *         of the HSE used directly or indirectly as system clock (if the Clock
+  *         Security System CSS is enabled).
+  * @note   HSI can not be stopped if it is used as system clock source. In this case,
+  *         you have to select another source of the system clock then stop the HSI.
+  * @note   After enabling the HSI, the application software should wait on HSIRDY
+  *         flag to be set indicating that HSI clock is stable and can be used as
+  *         system clock source.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
+  *         clock cycles.
+  */
+#define __HAL_RCC_HSI_ENABLE()  SET_BIT(RCC->CR, RCC_CR_HSION)
+#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
+
+
+/** @brief  Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
+  * @note   The calibration is used to compensate for the variations in voltage
+  *         and temperature that influence the frequency of the internal HSI RC.
+  * @param  __HSICalibrationValue__: specifies the calibration trimming value.
+  *         This parameter must be a number between 0 and 0x7F (3F for Rev Y device).
+  */
+#if defined(RCC_VER_X)
+#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__)                                                                   \
+           do {                                                                                                                          \
+              if(HAL_GetREVID() <= REV_ID_Y)                                                                                             \
+             {                                                                                                                           \
+               MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk, (uint32_t)(__HSICalibrationValue__) << HAL_RCC_REV_Y_HSITRIM_Pos);    \
+             }                                                                                                                           \
+             else                                                                                                                        \
+             {                                                                                                                           \
+               MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_HSICFGR_HSITRIM_Pos);            \
+             }                                                                                                                           \
+           } while(0)
+
+#else
+#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__)                                                                   \
+               MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_HSICFGR_HSITRIM_Pos);
+#endif /*RCC_VER_X*/
+/**
+  * @brief    Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
+  *           in STOP mode to be quickly available as kernel clock for some peripherals.
+  * @note     Keeping the HSI ON in STOP mode allows to avoid slowing down the communication
+  *           speed because of the HSI start-up time.
+  * @note     The enable of this function has not effect on the HSION bit.
+  *           This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+#define __HAL_RCC_HSISTOP_ENABLE()     SET_BIT(RCC->CR, RCC_CR_HSIKERON)
+#define __HAL_RCC_HSISTOP_DISABLE()    CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
+
+
+/**
+  * @brief  Macro to enable or disable the Internal High Speed oscillator for USB (HSI48).
+  * @note   After enabling the HSI48, the application software should wait on
+  *         HSI48RDY flag to be set indicating that HSI48 clock is stable and can
+  *         be used to clock the USB.
+  * @note   The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
+  */
+#define __HAL_RCC_HSI48_ENABLE()    SET_BIT(RCC->CR, RCC_CR_HSI48ON);
+
+#define __HAL_RCC_HSI48_DISABLE()   CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON);
+
+/**
+  * @brief  Macros to enable or disable the Internal  oscillator (CSI).
+  * @note     The CSI is stopped by hardware when entering STOP and STANDBY modes.
+  *           It is used (enabled by hardware) as system clock source after
+  *           start-up from Reset, wakeup from STOP and STANDBY mode, or in case
+  *           of failure of the HSE used directly or indirectly as system clock
+  *           (if the Clock Security System CSS is enabled).
+  * @note     CSI can not be stopped if it is used as system clock source.
+  *           In this case, you have to select another source of the system
+  *           clock then stop the CSI.
+  * @note     After enabling the CSI, the application software should wait on
+  *           CSIRDY flag to be set indicating that CSI clock is stable and can
+  *           be used as system clock source.
+  * @note     When the CSI is stopped, CSIRDY flag goes low after 6 CSI oscillator
+  *           clock cycles.
+  */
+#define __HAL_RCC_CSI_ENABLE()  SET_BIT(RCC->CR, RCC_CR_CSION)
+#define __HAL_RCC_CSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSION)
+
+/** @brief  Macro Adjusts the Internal  oscillator (CSI) calibration value.
+  * @note   The calibration is used to compensate for the variations in voltage
+  *         and temperature that influence the frequency of the internal CSI RC.
+  * @param  __CSICalibrationValue__: specifies the calibration trimming value.
+  *         This parameter must be a number between 0 and 0x1F.
+  */
+#if defined(RCC_VER_X)
+#define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__)                                                                   \
+           do {                                                                                                                          \
+             if(HAL_GetREVID() <= REV_ID_Y)                                                                                              \
+             {                                                                                                                           \
+               MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk, (uint32_t)(__CSICalibrationValue__) << HAL_RCC_REV_Y_CSITRIM_Pos);    \
+             }                                                                                                                           \
+             else                                                                                                                        \
+             {                                                                                                                           \
+               MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, (uint32_t)(__CSICalibrationValue__) << RCC_CSICFGR_CSITRIM_Pos);            \
+             }                                                                                                                           \
+           } while(0)
+
+#else
+#define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__)                                                                   \
+           do {                                                                                                                          \
+               MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, (uint32_t)(__CSICalibrationValue__) << RCC_CSICFGR_CSITRIM_Pos);            \
+               } while(0)
+
+#endif /*RCC_VER_X*/
+/**
+  * @brief    Macros to enable or disable the force of the Low-power Internal oscillator (CSI)
+  *           in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
+  * @note     Keeping the CSI ON in STOP mode allows to avoid slowing down the communication
+  *           speed because of the CSI start-up time.
+  * @note     The enable of this function has not effect on the CSION bit.
+  *           This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+#define __HAL_RCC_CSISTOP_ENABLE()     SET_BIT(RCC->CR, RCC_CR_CSIKERON)
+#define __HAL_RCC_CSISTOP_DISABLE()    CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON)
+
+
+/** @brief  Macros to enable or disable the Internal Low Speed oscillator (LSI).
+  * @note   After enabling the LSI, the application software should wait on
+  *         LSIRDY flag to be set indicating that LSI clock is stable and can
+  *         be used to clock the IWDG and/or the RTC.
+  * @note   LSI can not be disabled if the IWDG is running.
+  * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
+  *         clock cycles.
+  */
+#define __HAL_RCC_LSI_ENABLE()         SET_BIT(RCC->CSR, RCC_CSR_LSION)
+#define __HAL_RCC_LSI_DISABLE()        CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
+
+/**
+  * @brief  Macro to configure the External High Speed oscillator (__HSE__).
+  * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
+  *         software should wait on HSERDY flag to be set indicating that HSE clock
+  *         is stable and can be used to clock the PLL and/or system clock.
+  * @note   HSE state can not be changed if it is used directly or through the
+  *         PLL as system clock. In this case, you have to select another source
+  *         of the system clock then change the HSE state (ex. disable it).
+  * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
+  * @note   This function reset the CSSON bit, so if the clock security system(CSS)
+  *         was previously enabled you have to enable it again after calling this
+  *         function.
+  * @param  __STATE__: specifies the new state of the HSE.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
+  *                              6 HSE oscillator clock cycles.
+  *            @arg RCC_HSE_ON: turn ON the HSE oscillator.
+  *            @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
+  */
+#if defined(RCC_CR_HSEEXT)
+#define __HAL_RCC_HSE_CONFIG(__STATE__)                                \
+                    do {                                               \
+                      if ((__STATE__) == RCC_HSE_ON)                   \
+                      {                                                \
+                        SET_BIT(RCC->CR, RCC_CR_HSEON);                \
+                      }                                                \
+                      else if ((__STATE__) == RCC_HSE_OFF)             \
+                      {                                                \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);              \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT);             \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);             \
+                      }                                                \
+                      else if ((__STATE__) == RCC_HSE_BYPASS)          \
+                      {                                                \
+                        SET_BIT(RCC->CR, RCC_CR_HSEBYP);               \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT);             \
+                        SET_BIT(RCC->CR, RCC_CR_HSEON);                \
+                      }                                                \
+                      else if((__STATE__) == RCC_HSE_BYPASS_DIGITAL)   \
+                      {                                                \
+                        SET_BIT(RCC->CR, RCC_CR_HSEBYP);               \
+                        SET_BIT(RCC->CR, RCC_CR_HSEEXT);               \
+                        SET_BIT(RCC->CR, RCC_CR_HSEON);                \
+                      }                                                \
+                      else                                             \
+                      {                                                \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);              \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);             \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT);             \
+                      }                                                \
+                    } while(0)
+#else
+#define __HAL_RCC_HSE_CONFIG(__STATE__)                         \
+                    do {                                        \
+                      if ((__STATE__) == RCC_HSE_ON)            \
+                      {                                         \
+                        SET_BIT(RCC->CR, RCC_CR_HSEON);         \
+                      }                                         \
+                      else if ((__STATE__) == RCC_HSE_OFF)      \
+                      {                                         \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);       \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);      \
+                      }                                         \
+                      else if ((__STATE__) == RCC_HSE_BYPASS)   \
+                      {                                         \
+                        SET_BIT(RCC->CR, RCC_CR_HSEBYP);        \
+                        SET_BIT(RCC->CR, RCC_CR_HSEON);         \
+                      }                                         \
+                      else                                      \
+                      {                                         \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);       \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);      \
+                      }                                         \
+                    } while(0)
+#endif /* RCC_CR_HSEEXT */
+
+/** @defgroup RCC_LSE_Configuration LSE Configuration
+  * @{
+  */
+
+/**
+  * @brief  Macro to configure the External Low Speed oscillator (LSE).
+  * @note   Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
+  *         User should request a transition to LSE Off first and then LSE On or LSE Bypass.
+  * @note   The external input clock can have a frequency up to 1 MHz and be low swing (analog) or digital(*).
+            A duty cycle close to 50% is recommended.
+  * @note   As the LSE is in the Backup domain and write access is denied to
+  *         this domain after reset, you have to enable write access using
+  *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE
+  *         (to be done once after reset).
+  * @note   After enabling the LSE (RCC_LSE_ON, RCC_LSE_BYPASS or RCC_LSE_BYPASS_DIGITAL*), the application
+  *         software should wait on LSERDY flag to be set indicating that LSE clock
+  *         is stable and can be used to clock the RTC.
+  * @note   If the RTC is used, the LSE bypass must not be configured in digital mode but in low swing analog mode (*)
+  * @param  __STATE__: specifies the new state of the LSE.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
+  *                              6 LSE oscillator clock cycles.
+  *            @arg RCC_LSE_ON: turn ON the LSE oscillator.
+  *            @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
+  *            @arg RCC_LSE_BYPASS_DIGITAL: LSE oscillator bypassed with external digital clock. (*)
+  *
+  *         (*) Available on some STM32H7 lines only.
+  */
+#if defined(RCC_BDCR_LSEEXT)
+#define __HAL_RCC_LSE_CONFIG(__STATE__) \
+                    do {                                               \
+                      if((__STATE__) == RCC_LSE_ON)                    \
+                      {                                                \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);            \
+                      }                                                \
+                      else if((__STATE__) == RCC_LSE_OFF)              \
+                      {                                                \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);          \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);         \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);         \
+                      }                                                \
+                      else if((__STATE__) == RCC_LSE_BYPASS)           \
+                      {                                                \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);           \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);         \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);            \
+                      }                                                \
+                      else if((__STATE__) == RCC_LSE_BYPASS_DIGITAL)   \
+                      {                                                \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);           \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);           \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);            \
+                      }                                                \
+                      else                                             \
+                      {                                                \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);          \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);         \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);         \
+                      }                                                \
+                    } while(0)
+#else
+
+#define __HAL_RCC_LSE_CONFIG(__STATE__) \
+                    do {                                       \
+                      if((__STATE__) == RCC_LSE_ON)            \
+                      {                                        \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \
+                      }                                        \
+                      else if((__STATE__) == RCC_LSE_OFF)      \
+                      {                                        \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);  \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
+                      }                                        \
+                      else if((__STATE__) == RCC_LSE_BYPASS)   \
+                      {                                        \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);   \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \
+                      }                                        \
+                      else                                     \
+                      {                                        \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);  \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
+                      }                                        \
+                    } while(0)
+
+#endif /* RCC_BDCR_LSEEXT */
+/**
+  * @}
+  */
+
+/** @brief  Macros to enable or disable the the RTC clock.
+  * @note   These macros must be used only after the RTC clock source was selected.
+  */
+#define __HAL_RCC_RTC_ENABLE()         SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
+#define __HAL_RCC_RTC_DISABLE()        CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
+
+/** @brief  Macros to configure the RTC clock (RTCCLK).
+  * @note   As the RTC clock configuration bits are in the Backup domain and write
+  *         access is denied to this domain after reset, you have to enable write
+  *         access using the Power Backup Access macro before to configure
+  *         the RTC clock source (to be done once after reset).
+  * @note   Once the RTC clock is configured it can't be changed unless the
+  *         Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
+  *         a Power On Reset (POR).
+  * @param  __RTCCLKSource__: specifies the RTC clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
+  *            @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
+  *            @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
+  *                                            as RTC clock, where x:[2,31]
+  * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
+  *         work in STOP and STANDBY modes, and can be used as wakeup source.
+  *         However, when the HSE clock is used as RTC clock source, the RTC
+  *         cannot be used in STOP and STANDBY modes.
+  * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as
+  *         RTC clock source).
+  */
+#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ?    \
+                                                 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, (((__RTCCLKSource__) & 0xFFFFCFFU) >> 4)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
+
+#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__);    \
+                                                    RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU);  \
+                                                   } while (0)
+
+#define  __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
+
+
+/** @brief  Macros to force or release the Backup domain reset.
+  * @note   This function resets the RTC peripheral (including the backup registers)
+  *         and the RTC clock source selection in RCC_BDCR register.
+  * @note   The BKPSRAM is not affected by this reset.
+  */
+#define __HAL_RCC_BACKUPRESET_FORCE()   SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
+#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
+
+/** @brief  Macros to enable or disable the main PLL.
+  * @note   After enabling the main PLL, the application software should wait on
+  *         PLLRDY flag to be set indicating that PLL clock is stable and can
+  *         be used as system clock source.
+  * @note   The main PLL can not be disabled if it is used as system clock source
+  * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.
+  */
+#define __HAL_RCC_PLL_ENABLE()         SET_BIT(RCC->CR, RCC_CR_PLL1ON)
+#define __HAL_RCC_PLL_DISABLE()        CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON)
+
+/**
+  * @brief  Enables or disables each clock output (PLL_P_CLK, PLL_Q_CLK, PLL_R_CLK)
+  * @note   Enabling/disabling  those Clocks can be done only when the PLL is disabled.
+  *         This is mainly used to save Power.
+  *        (The ck_pll_p of the System PLL cannot be stopped if used as System Clock).
+  * @param  __RCC_PLL1ClockOut__: specifies the PLL clock to be outputted
+  *          This parameter can be one of the following values:
+  *            @arg RCC_PLL1_DIVP: This clock is used to generate system clock up to 400MHZ or 280MHZ(*)
+  *            @arg RCC_PLL1_DIVQ: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
+  *            @arg RCC_PLL1_DIVR: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
+  *
+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  *
+  * @retval None
+  */
+#define __HAL_RCC_PLLCLKOUT_ENABLE(__RCC_PLL1ClockOut__)   SET_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__))
+
+#define __HAL_RCC_PLLCLKOUT_DISABLE(__RCC_PLL1ClockOut__)  CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__))
+
+
+/**
+  * @brief  Enables or disables Fractional Part Of The Multiplication Factor of PLL1 VCO
+  * @note   Enabling/disabling  Fractional Part can be any time  without the need to stop the PLL1
+  * @retval None
+  */
+#define __HAL_RCC_PLLFRACN_ENABLE()   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN)
+
+#define __HAL_RCC_PLLFRACN_DISABLE()  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN)
+
+
+/**
+  * @brief  Macro to configures the main PLL clock source, multiplication and division factors.
+  * @note   This function must be used only when the main PLL is disabled.
+  *
+  * @param  __RCC_PLLSOURCE__: specifies the PLL entry clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_PLLSOURCE_CSI: CSI oscillator clock selected as PLL clock entry
+  *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
+  *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
+  * @note   This clock source (__RCC_PLLSource__) is common for the main PLL1 (main PLL) and PLL2 & PLL3 .
+  *
+  * @param  __PLLM1__: specifies the division factor for PLL VCO input clock
+  *          This parameter must be a number between 1 and 63.
+  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
+  *         frequency ranges from 1 to 16 MHz.
+  *
+  * @param  __PLLN1__: specifies the multiplication factor for PLL VCO output clock
+  *          This parameter must be a number between 4 and 512 or between 8 and 420(*).
+  * @note   You have to set the PLLN parameter correctly to ensure that the VCO
+  *         output frequency is between 150 and 420 MHz (when in medium VCO range) or
+  *         between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range)
+  *
+  * @param  __PLLP1__: specifies the division factor for system  clock.
+  *          This parameter must be a number between 2 and 128 (where odd numbers are not allowed)
+  *
+  * @param  __PLLQ1__: specifies the division factor for peripheral kernel clocks
+  *          This parameter must be a number between 1 and 128
+  *
+  * @param  __PLLR1__: specifies the division factor for peripheral kernel clocks
+  *          This parameter must be a number between 1 and 128
+  *
+  * @note   To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR)
+  *         is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible 
+  *         value to  __PLL1P__, __PLL1Q__ or __PLL1R__ parameters.
+  * @retval None
+  *
+  *  (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  */
+
+
+#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLM1__, __PLLN1__, __PLLP1__, __PLLQ1__,__PLLR1__ ) \
+                  do{ MODIFY_REG(RCC->PLLCKSELR, (RCC_PLLCKSELR_PLLSRC | RCC_PLLCKSELR_DIVM1) , ((__RCC_PLLSOURCE__) | ( (__PLLM1__) <<4U)));  \
+                      WRITE_REG (RCC->PLL1DIVR , ( (((__PLLN1__) - 1U )& RCC_PLL1DIVR_N1) | ((((__PLLP1__) -1U ) << 9U) & RCC_PLL1DIVR_P1) | \
+                                ((((__PLLQ1__) -1U) << 16U)& RCC_PLL1DIVR_Q1) | ((((__PLLR1__) - 1U) << 24U)& RCC_PLL1DIVR_R1))); \
+                    } while(0)
+
+
+/** @brief  Macro to configure the PLLs clock source.
+  * @note   This function must be used only when all PLLs are disabled.
+  * @param  __PLLSOURCE__: specifies the PLLs entry clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PLLSOURCE_CSI: CSI oscillator clock selected as PLL clock entry
+  *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
+  *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
+  *
+  */
+#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, (__PLLSOURCE__))
+
+
+/**
+  * @brief  Macro to configures the main PLL clock Fractional Part Of The Multiplication Factor
+  *
+  * @note   These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO
+  *
+  * @param  __RCC_PLL1FRACN__: specifies Fractional Part Of The Multiplication Factor for PLL1 VCO
+  *                            It should be a value between 0 and 8191
+  * @note   Warning: The software has to set correctly these bits to insure that the VCO
+  *                  output frequency is between its valid frequency range, which is:
+  *                   192 to 836 MHz or 128 to 560 MHz(*) if PLL1VCOSEL = 0
+  *                   150 to 420 MHz if PLL1VCOSEL = 1.
+  *
+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  *
+  * @retval None
+  */
+ #define  __HAL_RCC_PLLFRACN_CONFIG(__RCC_PLL1FRACN__) MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, (uint32_t)(__RCC_PLL1FRACN__) << RCC_PLL1FRACR_FRACN1_Pos)
+
+
+/** @brief  Macro to select  the PLL1  reference frequency range.
+  * @param  __RCC_PLL1VCIRange__: specifies the PLL1 input frequency range
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PLL1VCIRANGE_0: Range frequency is between 1 and 2 MHz
+  *            @arg RCC_PLL1VCIRANGE_1: Range frequency is between 2 and 4 MHz
+  *            @arg RCC_PLL1VCIRANGE_2: Range frequency is between 4 and 8 MHz
+  *            @arg RCC_PLL1VCIRANGE_3: Range frequency is between 8 and 16 MHz
+  * @retval None
+  */
+#define __HAL_RCC_PLL_VCIRANGE(__RCC_PLL1VCIRange__) \
+                  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, (__RCC_PLL1VCIRange__))
+
+
+/** @brief  Macro to select  the PLL1  reference frequency range.
+  * @param  __RCC_PLL1VCORange__: specifies the PLL1 input frequency range
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PLL1VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*)
+  *            @arg RCC_PLL1VCOMEDIUM: Range frequency is between 150 and 420 MHz
+  *
+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  *
+  * @retval None
+  */
+#define __HAL_RCC_PLL_VCORANGE(__RCC_PLL1VCORange__) \
+                  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, (__RCC_PLL1VCORange__))
+
+
+
+/** @brief  Macro to get the clock source used as system clock.
+  * @retval The clock source used as system clock. The returned value can be one
+  *         of the following:
+  *              - RCC_CFGR_SWS_CSI: CSI used as system clock.
+  *              - RCC_CFGR_SWS_HSI: HSI used as system clock.
+  *              - RCC_CFGR_SWS_HSE: HSE used as system clock.
+  *              - RCC_CFGR_SWS_PLL: PLL used as system clock.
+  */
+#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
+
+
+/**
+  * @brief Macro to configure the system clock source.
+  * @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
+  * This parameter can be one of the following values:
+  *              - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
+  *              - RCC_SYSCLKSOURCE_CSI: CSI oscillator is used as system clock source.
+  *              - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
+  *              - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
+  */
+#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
+
+/** @brief  Macro to get the oscillator used as PLL clock source.
+  * @retval The oscillator used as PLL clock source. The returned value can be one
+  *         of the following:
+  *              - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.
+  *              - RCC_PLLSOURCE_CSI: CSI oscillator is used as PLL clock source.
+  *              - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
+  *              - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
+  */
+#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC))
+
+/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
+  * @{
+  */
+
+/** @brief  Macro to configure the MCO1 clock.
+  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_PLL1QCLK:  PLL1Q clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_HSI48: HSI48 (48MHZ) selected as MCO1 source
+  * @param  __MCODIV__ specifies the MCO clock prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCODIV_1 up to RCC_MCODIV_15  : divider applied to MCO1 clock
+  */
+#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
+                 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
+
+/** @brief  Macro to configure the MCO2 clock.
+  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_PLL2PCLK: PLL2P clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_PLLCLK:  PLL1P clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_CSICLK:  CSI clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_LSICLK:  LSI clock selected as MCO2 source
+  * @param  __MCODIV__ specifies the MCO clock prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCODIV_1 up to RCC_MCODIV_15  : divider applied to MCO2 clock
+  */
+#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
+    MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 7)));
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Macro to configure the External Low Speed oscillator (LSE) drive capability.
+  * @note   As the LSE is in the Backup domain and write access is denied to
+  *         this domain after reset, you have to enable write access using
+  *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE
+  *         (to be done once after reset).
+  * @note   On STM32H7 Rev.B and above devices this can't be updated while LSE is ON.
+  * @param  __LSEDRIVE__: specifies the new state of the LSE drive capability.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.
+  *            @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.
+  *            @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.
+  *            @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.
+  * @retval None
+  */
+#if defined(RCC_VER_X)
+#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
+           do{                                                                                                                                \
+             if((HAL_GetREVID() <= REV_ID_Y) && (((__LSEDRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || ((__LSEDRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH)))  \
+             {                                                                                                                                \
+              MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (~(uint32_t)(__LSEDRIVE__)) & RCC_BDCR_LSEDRV_Msk);                                      \
+             }                                                                                                                                \
+             else                                                                                                                             \
+             {                                                                                                                                \
+               MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__));                                                              \
+             }                                                                                                                                \
+           } while(0)
+#else
+#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
+               MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__));
+#endif /*RCC_VER_X*/
+/**
+  * @brief  Macro to configure the wake up from stop clock.
+  * @param  __RCC_STOPWUCLK__: specifies the clock source used after wake up from stop
+  *         This parameter can be one of the following values:
+  *            @arg RCC_STOP_WAKEUPCLOCK_CSI: CSI selected as system clock source
+  *            @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI selected as system clock source
+  * @retval None
+  */
+#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) \
+                  MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__RCC_STOPWUCLK__))
+
+/**
+  * @brief  Macro to configure the Kernel wake up from stop clock.
+  * @param  __RCC_STOPKERWUCLK__: specifies the Kernel clock source used after wake up from stop
+  *         This parameter can be one of the following values:
+  *            @arg RCC_STOP_KERWAKEUPCLOCK_CSI: CSI selected as Kernel clock source
+  *            @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI selected as Kernel clock source
+  * @retval None
+  */
+#define __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(__RCC_STOPKERWUCLK__) \
+                  MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, (__RCC_STOPKERWUCLK__))
+
+/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
+  * @brief macros to manage the specified RCC Flags and interrupts.
+  * @{
+  */
+/** @brief  Enable RCC interrupt.
+  * @param  __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
+  *         This parameter can be any combination of the following values:
+  *            @arg RCC_IT_LSIRDY: LSI ready interrupt
+  *            @arg RCC_IT_LSERDY: LSE ready interrupt
+  *            @arg RCC_IT_CSIRDY: HSI ready interrupt
+  *            @arg RCC_IT_HSIRDY: HSI ready interrupt
+  *            @arg RCC_IT_HSERDY: HSE ready interrupt
+  *            @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
+  *            @arg RCC_IT_PLLRDY: main PLL ready interrupt
+  *            @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
+  *            @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
+  *            @arg RCC_IT_LSECSS: Clock security system interrupt
+  */
+#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
+
+/** @brief Disable RCC interrupt
+  * @param  __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
+  *         This parameter can be any combination of the following values:
+  *            @arg RCC_IT_LSIRDY: LSI ready interrupt
+  *            @arg RCC_IT_LSERDY: LSE ready interrupt
+  *            @arg RCC_IT_CSIRDY: HSI ready interrupt
+  *            @arg RCC_IT_HSIRDY: HSI ready interrupt
+  *            @arg RCC_IT_HSERDY: HSE ready interrupt
+  *            @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
+  *            @arg RCC_IT_PLLRDY: main PLL ready interrupt
+  *            @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
+  *            @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
+  *            @arg RCC_IT_LSECSS: Clock security system interrupt
+  */
+#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
+
+/** @brief  Clear the RCC's interrupt pending bits
+  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
+  *         This parameter can be any combination of the following values:
+  *            @arg RCC_IT_LSIRDY: LSI ready interrupt
+  *            @arg RCC_IT_LSERDY: LSE ready interrupt
+  *            @arg RCC_IT_CSIRDY: CSI ready interrupt
+  *            @arg RCC_IT_HSIRDY: HSI ready interrupt
+  *            @arg RCC_IT_HSERDY: HSE ready interrupt
+  *            @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
+  *            @arg RCC_IT_PLLRDY: main PLL ready interrupt
+  *            @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
+  *            @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
+  *            @arg RCC_IT_HSECSS: HSE Clock Security interrupt
+  *            @arg RCC_IT_LSECSS: Clock security system interrupt
+  */
+#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
+
+/** @brief  Check the RCC's interrupt has occurred or not.
+  * @param  __INTERRUPT__: specifies the RCC interrupt source to check.
+  *         This parameter can be any combination of the following values:
+  *            @arg RCC_IT_LSIRDY: LSI ready interrupt
+  *            @arg RCC_IT_LSERDY: LSE ready interrupt
+  *            @arg RCC_IT_CSIRDY: CSI ready interrupt
+  *            @arg RCC_IT_HSIRDY: HSI ready interrupt
+  *            @arg RCC_IT_HSERDY: HSE ready interrupt
+  *            @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
+  *            @arg RCC_IT_PLLRDY: main PLL ready interrupt
+  *            @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
+  *            @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
+  *            @arg RCC_IT_HSECSS: HSE Clock Security interrupt
+  *            @arg RCC_IT_LSECSS: Clock security system interrupt
+  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+  */
+#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/** @brief Set RMVF bit to clear the reset flags.
+  */
+#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->RSR |= RCC_RSR_RMVF)
+
+#if defined(DUAL_CORE)
+#define __HAL_RCC_C1_CLEAR_RESET_FLAGS() (RCC_C1->RSR |= RCC_RSR_RMVF)
+
+#define __HAL_RCC_C2_CLEAR_RESET_FLAGS() (RCC_C2->RSR |= RCC_RSR_RMVF)
+#endif /*DUAL_CORE*/
+
+#if defined(DUAL_CORE)
+/** @brief  Check RCC flag is set or not.
+  * @param  __FLAG__: specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
+  *            @arg RCC_FLAG_HSIDIV: HSI divider flag
+  *            @arg RCC_FLAG_CSIRDY: CSI oscillator clock ready
+  *            @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready
+  *            @arg RCC_FLAG_HSERDY:  HSE oscillator clock ready
+  *            @arg RCC_FLAG_D1CKRDY:  Domain1 clock ready
+  *            @arg RCC_FLAG_D2CKRDY:  Domain2 clock ready
+  *            @arg RCC_FLAG_PLLRDY:  PLL1 clock ready
+  *            @arg RCC_FLAG_PLL2RDY: PLL2 clock ready
+  *            @arg RCC_FLAG_PLL3RDY: PLL3 clock ready
+  *            @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
+  *            @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
+  *            @arg RCC_FLAG_C1RST:  CPU reset flag
+  *            @arg RCC_FLAG_C2RST:  CPU2 reset flag
+  *            @arg RCC_FLAG_D1RST:  D1 domain power switch reset flag
+  *            @arg RCC_FLAG_D2RST:  D2 domain power switch reset flag
+  *            @arg RCC_FLAG_BORRST: BOR reset flag
+  *            @arg RCC_FLAG_PINRST: Pin reset
+  *            @arg RCC_FLAG_PORRST: POR/PDR  reset
+  *            @arg RCC_FLAG_SFTR1ST: System reset from CPU reset flag
+  *            @arg RCC_FLAG_SFTR2ST: System reset from CPU2 reset flag
+  *            @arg RCC_FLAG_BORRST:   D2 domain power switch reset flag
+  *            @arg RCC_FLAG_IWDG1RST: CPU Independent Watchdog reset
+  *            @arg RCC_FLAG_IWDG2RST: CPU2 Independent Watchdog reset
+  *            @arg RCC_FLAG_WWDG2RST: Window Watchdog2 reset
+  *            @arg RCC_FLAG_WWDG1RST: Window Watchdog1 reset
+  *            @arg RCC_FLAG_LPWR1RST: Reset due to illegal D1 DSTANDBY or CPU CSTOP flag
+  *            @arg RCC_FLAG_LPWR2RST: Reset due to illegal D2 DSTANDBY or CPU2 CSTOP flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define RCC_FLAG_MASK  ((uint8_t)0x1F)
+#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
+((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC->RSR :RCC->CIFR))))  & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
+
+#define __HAL_RCC_C1_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
+((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC_C1->RSR :RCC->CIFR))))  & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
+
+#define __HAL_RCC_C2_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
+((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC_C2->RSR :RCC->CIFR))))  & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
+
+#else
+
+/** @brief  Check RCC flag is set or not.
+  * @param  __FLAG__: specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
+  *            @arg RCC_FLAG_HSIDIV: HSI divider flag
+  *            @arg RCC_FLAG_CSIRDY: CSI oscillator clock ready
+  *            @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready
+  *            @arg RCC_FLAG_HSERDY:  HSE oscillator clock ready
+  *            @arg RCC_FLAG_D1CKRDY:  Domain1 clock ready (*)
+  *            @arg RCC_FLAG_D2CKRDY:  Domain2 clock ready (*)
+  *            @arg RCC_FLAG_CPUCKRDY: CPU Domain clock ready (CPU, APB3, bus matrix1 and related memories) (*)
+  *            @arg RCC_FLAG_CDCKRDY:  CPU Domain clock ready (*)
+  *            @arg RCC_FLAG_PLLRDY:  PLL1 clock ready
+  *            @arg RCC_FLAG_PLL2RDY: PLL2 clock ready
+  *            @arg RCC_FLAG_PLL3RDY: PLL3 clock ready
+  *            @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
+  *            @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
+  *            @arg RCC_FLAG_CPURST: CPU reset flag
+  *            @arg RCC_FLAG_D1RST:  D1 domain power switch reset flag (*)
+  *            @arg RCC_FLAG_D2RST:  D2 domain power switch reset flag (*)
+  *            @arg RCC_FLAG_CDRST:  CD domain power switch reset flag (*)
+  *            @arg RCC_FLAG_BORRST: BOR reset flag
+  *            @arg RCC_FLAG_PINRST: Pin reset
+  *            @arg RCC_FLAG_PORRST: POR/PDR  reset
+  *            @arg RCC_FLAG_SFTRST: System reset from CPU reset flag
+  *            @arg RCC_FLAG_BORRST:   D2 domain power switch reset flag
+  *            @arg RCC_FLAG_IWDG1RST: CPU Independent Watchdog reset
+  *            @arg RCC_FLAG_WWDG1RST: Window Watchdog1 reset
+  *            @arg RCC_FLAG_LPWR1RST: Reset due to illegal D1 DSTANDBY or CPU CSTOP flag
+  *            @arg RCC_FLAG_LPWR2RST: Reset due to illegal D2 DSTANDBY flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  *
+  *  (*) Available on some STM32H7 lines only.
+  */
+#define RCC_FLAG_MASK  ((uint8_t)0x1F)
+#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
+((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC->RSR :RCC->CIFR))))  & (1UL << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
+#endif /*DUAL_CORE*/
+
+/**
+  * @}
+  */
+
+#define RCC_GET_PLL_OSCSOURCE() ((RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC) >> RCC_PLLCKSELR_PLLSRC_Pos)
+
+/**
+  * @}
+  */
+
+/* Include RCC HAL Extension module */
+#include "stm32h7xx_hal_rcc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+ /** @addtogroup RCC_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup RCC_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de-initialization functions  ******************************/
+HAL_StatusTypeDef HAL_RCC_DeInit(void);
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
+
+/**
+  * @}
+  */
+
+/** @addtogroup RCC_Exported_Functions_Group2
+  * @{
+  */
+/* Peripheral Control functions  ************************************************/
+void     HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
+void     HAL_RCC_EnableCSS(void);
+void     HAL_RCC_DisableCSS(void);
+uint32_t HAL_RCC_GetSysClockFreq(void);
+uint32_t HAL_RCC_GetHCLKFreq(void);
+uint32_t HAL_RCC_GetPCLK1Freq(void);
+uint32_t HAL_RCC_GetPCLK2Freq(void);
+void     HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
+void     HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
+/* CSS NMI IRQ handler */
+void     HAL_RCC_NMI_IRQHandler(void);
+/* User Callbacks in non blocking mode (IT mode) */
+void     HAL_RCC_CCSCallback(void);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RCC_Private_Constants RCC Private Constants
+  * @{
+  */
+
+#define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT
+#define HSI_TIMEOUT_VALUE          (2U)    /* 2 ms */
+#define HSI48_TIMEOUT_VALUE        (2U)    /* 2 ms */
+#define CSI_TIMEOUT_VALUE          (2U)    /* 2 ms */
+#define LSI_TIMEOUT_VALUE          (2U)    /* 2 ms */
+#define PLL_TIMEOUT_VALUE          (2U)    /* 2 ms */
+#define CLOCKSWITCH_TIMEOUT_VALUE  (5000U) /* 5 s  */
+#define RCC_DBP_TIMEOUT_VALUE      (100U)
+#define RCC_LSE_TIMEOUT_VALUE      LSE_STARTUP_TIMEOUT
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RCC_Private_Macros RCC Private Macros
+  * @{
+  */
+
+/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
+  * @{
+  */
+
+#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE)                           || \
+                                           (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
+                                           (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
+                                           (((OSCILLATOR) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) || \
+                                           (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
+                                           (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \
+                                           (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48))
+
+#if defined(RCC_CR_HSEEXT)
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
+                         ((HSE) == RCC_HSE_BYPASS) || ((HSE) == RCC_HSE_BYPASS_DIGITAL))
+#else
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
+                         ((HSE) == RCC_HSE_BYPASS))
+#endif /* RCC_CR_HSEEXT */
+
+#if defined(RCC_BDCR_LSEEXT)
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
+                         ((LSE) == RCC_LSE_BYPASS) || ((LSE) == RCC_LSE_BYPASS_DIGITAL))
+#else
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
+                         ((LSE) == RCC_LSE_BYPASS))
+#endif /* RCC_BDCR_LSEEXT */
+
+#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON)    || \
+                         ((HSI) == RCC_HSI_DIV1) || ((HSI) == RCC_HSI_DIV2) || \
+                         ((HSI) == RCC_HSI_DIV4) || ((HSI) == RCC_HSI_DIV8))
+
+#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON))
+
+#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
+
+#define IS_RCC_CSI(CSI) (((CSI) == RCC_CSI_OFF) || ((CSI) == RCC_CSI_ON))
+
+#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || \
+                         ((PLL) == RCC_PLL_ON))
+
+#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_CSI)  || \
+                                  ((SOURCE) == RCC_PLLSOURCE_HSI)  || \
+                                  ((SOURCE) == RCC_PLLSOURCE_NONE) || \
+                                  ((SOURCE) == RCC_PLLSOURCE_HSE))
+#define IS_RCC_PLLM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))
+#if !defined(RCC_VER_2_0)
+#define IS_RCC_PLLN_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))
+#else
+#define IS_RCC_PLLN_VALUE(VALUE) ((8U <= (VALUE)) && ((VALUE) <= 420U))
+#endif /* !RCC_VER_2_0 */
+#define IS_RCC_PLLP_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
+#define IS_RCC_PLLQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
+#define IS_RCC_PLLR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
+
+#define IS_RCC_PLLCLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL1_DIVP) || \
+                                         ((VALUE) == RCC_PLL1_DIVQ) || \
+                                         ((VALUE) == RCC_PLL1_DIVR))
+
+#define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 0x3FU))
+
+#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_CSI) || \
+                                     ((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
+                                     ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
+                                     ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
+
+#define IS_RCC_SYSCLK(SYSCLK) (((SYSCLK) == RCC_SYSCLK_DIV1)   || ((SYSCLK) == RCC_SYSCLK_DIV2)   || \
+                               ((SYSCLK) == RCC_SYSCLK_DIV4)   || ((SYSCLK) == RCC_SYSCLK_DIV8)   || \
+                               ((SYSCLK) == RCC_SYSCLK_DIV16)  || ((SYSCLK) == RCC_SYSCLK_DIV64)  || \
+                               ((SYSCLK) == RCC_SYSCLK_DIV128) || ((SYSCLK) == RCC_SYSCLK_DIV256) || \
+                               ((SYSCLK) == RCC_SYSCLK_DIV512))
+
+
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_HCLK_DIV1)   || ((HCLK) == RCC_HCLK_DIV2)   || \
+                           ((HCLK) == RCC_HCLK_DIV4)   || ((HCLK) == RCC_HCLK_DIV8)   || \
+                           ((HCLK) == RCC_HCLK_DIV16)  || ((HCLK) == RCC_HCLK_DIV64)  || \
+                           ((HCLK) == RCC_HCLK_DIV128) || ((HCLK) == RCC_HCLK_DIV256) || \
+                           ((HCLK) == RCC_HCLK_DIV512))
+
+#define IS_RCC_CDPCLK1(CDPCLK1) (((CDPCLK1) == RCC_APB3_DIV1) || ((CDPCLK1) == RCC_APB3_DIV2) || \
+                                 ((CDPCLK1) == RCC_APB3_DIV4) || ((CDPCLK1) == RCC_APB3_DIV8) || \
+                                 ((CDPCLK1) == RCC_APB3_DIV16))
+
+#define IS_RCC_D1PCLK1 IS_RCC_CDPCLK1  /* for legacy compatibility between H7 lines */
+
+#define IS_RCC_PCLK1(PCLK1) (((PCLK1) == RCC_APB1_DIV1) || ((PCLK1) == RCC_APB1_DIV2) || \
+                             ((PCLK1) == RCC_APB1_DIV4) || ((PCLK1) == RCC_APB1_DIV8) || \
+                            ((PCLK1) == RCC_APB1_DIV16))
+
+#define IS_RCC_PCLK2(PCLK2) (((PCLK2) == RCC_APB2_DIV1) || ((PCLK2) == RCC_APB2_DIV2) || \
+                             ((PCLK2) == RCC_APB2_DIV4) || ((PCLK2) == RCC_APB2_DIV8) || \
+                             ((PCLK2) == RCC_APB2_DIV16))
+
+#define IS_RCC_SRDPCLK1(SRDPCLK1) (((SRDPCLK1) == RCC_APB4_DIV1) || ((SRDPCLK1) == RCC_APB4_DIV2) || \
+                                  ((SRDPCLK1) == RCC_APB4_DIV4)  || ((SRDPCLK1) == RCC_APB4_DIV8) || \
+                                  ((SRDPCLK1) == RCC_APB4_DIV16))
+
+#define IS_RCC_D3PCLK1 IS_RCC_SRDPCLK1 /* for legacy compatibility between H7 lines*/
+
+#define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE)       || ((SOURCE) == RCC_RTCCLKSOURCE_LSI)       || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2)  || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3)  || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4)  || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5)  || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6)  || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7)  || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8)  || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9)  || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV33) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV34) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV35) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV36) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV37) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV38) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV39) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV40) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV41) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV42) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV43) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV44) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV45) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV46) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV47) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV48) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV49) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV50) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV51) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV52) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV53) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV54) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV55) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV56) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV57) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV58) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV59) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV60) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV61) || \
+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV62) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV63))
+
+#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
+
+#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE)       || \
+                                   ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLL1QCLK)  || \
+                                   ((SOURCE) == RCC_MCO1SOURCE_HSI48))
+
+#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK)    || ((SOURCE) == RCC_MCO2SOURCE_PLL2PCLK) || \
+                                   ((SOURCE) == RCC_MCO2SOURCE_HSE)       || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK)   || \
+                                   ((SOURCE) == RCC_MCO2SOURCE_CSICLK)    || ((SOURCE) == RCC_MCO2SOURCE_LSICLK))
+
+#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1)  || ((DIV) == RCC_MCODIV_2)   || \
+                            ((DIV) == RCC_MCODIV_3)  || ((DIV) == RCC_MCODIV_4)   || \
+                            ((DIV) == RCC_MCODIV_5)  || ((DIV) == RCC_MCODIV_6)   || \
+                            ((DIV) == RCC_MCODIV_7)  || ((DIV) == RCC_MCODIV_8)   || \
+                            ((DIV) == RCC_MCODIV_9)  || ((DIV) == RCC_MCODIV_10)  || \
+                            ((DIV) == RCC_MCODIV_11) || ((DIV) == RCC_MCODIV_12)  || \
+                            ((DIV) == RCC_MCODIV_13) || ((DIV) == RCC_MCODIV_14)  || \
+                            ((DIV) == RCC_MCODIV_15))
+
+#if defined(DUAL_CORE)
+#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY)    || ((FLAG) == RCC_FLAG_CSIRDY)  || \
+                           ((FLAG) == RCC_FLAG_HSI48RDY)  || ((FLAG) == RCC_FLAG_HSERDY)  || \
+                           ((FLAG) == RCC_FLAG_D1CKRDY)   || ((FLAG) == RCC_FLAG_D2CKRDY) || \
+                           ((FLAG) == RCC_FLAG_PLLRDY)    || ((FLAG) == RCC_FLAG_PLL2RDY) || \
+                           ((FLAG) == RCC_FLAG_PLL3RDY)   || ((FLAG) == RCC_FLAG_LSERDY)  || \
+                           ((FLAG) == RCC_FLAG_LSIRDY)    || \
+                           ((FLAG) == RCC_FLAG_C1RST)     || ((FLAG) == RCC_FLAG_C2RST)   || \
+                           ((FLAG) == RCC_FLAG_SFTR2ST)   || ((FLAG) == RCC_FLAG_WWDG2RST)|| \
+                           ((FLAG) == RCC_FLAG_IWDG2RST)  || ((FLAG) == RCC_FLAG_D1RST)   || \
+                           ((FLAG) == RCC_FLAG_D2RST)     || ((FLAG) == RCC_FLAG_BORRST)  || \
+                           ((FLAG) == RCC_FLAG_PINRST)    || ((FLAG) == RCC_FLAG_PORRST)  || \
+                           ((FLAG) == RCC_FLAG_SFTR1ST)   || ((FLAG) == RCC_FLAG_IWDG1RST)|| \
+                           ((FLAG) == RCC_FLAG_WWDG1RST)  || ((FLAG) == RCC_FLAG_LPWR1RST)|| \
+                           ((FLAG) == RCC_FLAG_LPWR2RST)  || ((FLAG) == RCC_FLAG_HSIDIV))
+
+#else
+
+#if defined(RCC_CR_D2CKRDY)
+#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY)    || ((FLAG) == RCC_FLAG_CSIRDY)  || \
+                           ((FLAG) == RCC_FLAG_HSI48RDY)  || ((FLAG) == RCC_FLAG_HSERDY)  || \
+                           ((FLAG) == RCC_FLAG_D1CKRDY)   || ((FLAG) == RCC_FLAG_D2CKRDY) || \
+                           ((FLAG) == RCC_FLAG_PLLRDY)    || ((FLAG) == RCC_FLAG_PLL2RDY) || \
+                           ((FLAG) == RCC_FLAG_PLL3RDY)   || ((FLAG) == RCC_FLAG_LSERDY)  || \
+                           ((FLAG) == RCC_FLAG_LSIRDY)    || \
+                           ((FLAG) == RCC_FLAG_CPURST)    || ((FLAG) == RCC_FLAG_D1RST)   || \
+                           ((FLAG) == RCC_FLAG_D2RST)     || ((FLAG) == RCC_FLAG_BORRST)  || \
+                           ((FLAG) == RCC_FLAG_PINRST)    || ((FLAG) == RCC_FLAG_PORRST)  || \
+                           ((FLAG) == RCC_FLAG_SFTRST)    || ((FLAG) == RCC_FLAG_IWDG1RST)|| \
+                           ((FLAG) == RCC_FLAG_WWDG1RST)  || ((FLAG) == RCC_FLAG_LPWR1RST)|| \
+                           ((FLAG) == RCC_FLAG_LPWR2RST)  || ((FLAG) == RCC_FLAG_HSIDIV ))
+#else
+#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY)    || ((FLAG) == RCC_FLAG_CSIRDY)  || \
+                           ((FLAG) == RCC_FLAG_HSI48RDY)  || ((FLAG) == RCC_FLAG_HSERDY)  || \
+                           ((FLAG) == RCC_FLAG_CPUCKRDY)  || ((FLAG) == RCC_FLAG_CDCKRDY) || \
+                           ((FLAG) == RCC_FLAG_PLLRDY)    || ((FLAG) == RCC_FLAG_PLL2RDY) || \
+                           ((FLAG) == RCC_FLAG_PLL3RDY)   || ((FLAG) == RCC_FLAG_LSERDY)  || \
+                           ((FLAG) == RCC_FLAG_LSIRDY)    || \
+                           ((FLAG) == RCC_FLAG_CDRST)     || ((FLAG) == RCC_FLAG_BORRST)  || \
+                           ((FLAG) == RCC_FLAG_PINRST)    || ((FLAG) == RCC_FLAG_PORRST)  || \
+                           ((FLAG) == RCC_FLAG_SFTRST)    || ((FLAG) == RCC_FLAG_IWDG1RST)|| \
+                           ((FLAG) == RCC_FLAG_WWDG1RST)  || ((FLAG) == RCC_FLAG_LPWR1RST)|| \
+                           ((FLAG) == RCC_FLAG_LPWR2RST)  || ((FLAG) == RCC_FLAG_HSIDIV ))
+#endif /* RCC_CR_D2CKRDY */
+
+#endif /*DUAL_CORE*/
+
+#define IS_RCC_HSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7FU)
+#define IS_RCC_CSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x3FU)
+
+#define IS_RCC_STOP_WAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_WAKEUPCLOCK_CSI) || \
+                                         ((SOURCE) == RCC_STOP_WAKEUPCLOCK_HSI))
+
+#define IS_RCC_STOP_KERWAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_CSI) || \
+                                          ((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_HSI))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_RCC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h
new file mode 100644
index 00000000..42beccc8
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h
@@ -0,0 +1,4262 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_rcc_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of RCC HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_RCC_EX_H
+#define STM32H7xx_HAL_RCC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup RCCEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
+  * @{
+  */
+
+/**
+  * @brief  PLL2 Clock structure definition
+  */
+typedef struct
+{
+
+  uint32_t PLL2M;       /*!< PLL2M: Division factor for PLL2 VCO input clock.
+                             This parameter must be a number between Min_Data = 1 and Max_Data = 63    */
+
+  uint32_t PLL2N;       /*!< PLL2N: Multiplication factor for PLL2 VCO output clock.
+                             This parameter must be a number between Min_Data = 4 and Max_Data = 512
+                             or between Min_Data = 8 and Max_Data = 420(*)
+                             (*) : For stm32h7a3xx and stm32h7b3xx family lines.                       */   
+
+  uint32_t PLL2P;       /*!< PLL2P: Division factor for system clock.
+                             This parameter must be a number between Min_Data = 2 and Max_Data = 128
+                             odd division factors are not allowed                                      */
+
+  uint32_t PLL2Q;        /*!< PLL2Q: Division factor for peripheral clocks.
+                             This parameter must be a number between Min_Data = 1 and Max_Data = 128   */
+
+  uint32_t PLL2R;        /*!< PLL2R: Division factor for peripheral clocks.
+                             This parameter must be a number between Min_Data = 1 and Max_Data = 128   */
+  uint32_t PLL2RGE;      /*!<PLL2RGE: PLL2 clock Input range
+                          This parameter must be a value of @ref RCC_PLL2_VCI_Range                    */
+  uint32_t PLL2VCOSEL;   /*!<PLL2VCOSEL: PLL2 clock Output range
+                          This parameter must be a value of @ref RCC_PLL2_VCO_Range                    */
+
+  uint32_t PLL2FRACN;    /*!<PLL2FRACN: Specifies Fractional Part Of The Multiplication Factor for
+                            PLL2 VCO It should be a value between 0 and 8191                           */
+}RCC_PLL2InitTypeDef;
+
+/**
+  * @brief  PLL3 Clock structure definition
+  */
+typedef struct
+{
+
+  uint32_t PLL3M;       /*!< PLL3M: Division factor for PLL3 VCO input clock.
+                             This parameter must be a number between Min_Data = 1 and Max_Data = 63    */
+
+  uint32_t PLL3N;       /*!< PLL3N: Multiplication factor for PLL3 VCO output clock.
+                             This parameter must be a number between Min_Data = 4 and Max_Data = 512
+                             or between Min_Data = 8 and Max_Data = 420(*)
+                             (*) : For stm32h7a3xx and stm32h7b3xx family lines.                       */  
+
+  uint32_t PLL3P;       /*!< PLL3P: Division factor for system clock.
+                             This parameter must be a number between Min_Data = 2 and Max_Data = 128
+                             odd division factors are not allowed                                      */
+
+  uint32_t PLL3Q;        /*!< PLL3Q: Division factor for peripheral clocks.
+                             This parameter must be a number between Min_Data = 1 and Max_Data = 128   */
+
+  uint32_t PLL3R;        /*!< PLL3R: Division factor for peripheral clocks.
+                             This parameter must be a number between Min_Data = 1 and Max_Data = 128   */
+  uint32_t PLL3RGE;      /*!<PLL3RGE: PLL3 clock Input range
+                          This parameter must be a value of @ref RCC_PLL3_VCI_Range                    */
+  uint32_t PLL3VCOSEL;   /*!<PLL3VCOSEL: PLL3 clock Output range
+                          This parameter must be a value of @ref RCC_PLL3_VCO_Range                    */
+
+  uint32_t PLL3FRACN;    /*!<PLL3FRACN: Specifies Fractional Part Of The Multiplication Factor for
+                            PLL3 VCO It should be a value between 0 and 8191                           */
+}RCC_PLL3InitTypeDef;
+
+/**
+  * @brief  RCC PLL1 Clocks structure definition
+  */
+typedef struct
+{
+  uint32_t PLL1_P_Frequency;
+  uint32_t PLL1_Q_Frequency;
+  uint32_t PLL1_R_Frequency;
+}PLL1_ClocksTypeDef;
+
+/**
+  * @brief  RCC PLL2 Clocks structure definition
+  */
+typedef struct
+{
+  uint32_t PLL2_P_Frequency;
+  uint32_t PLL2_Q_Frequency;
+  uint32_t PLL2_R_Frequency;
+}PLL2_ClocksTypeDef;
+
+/**
+  * @brief  RCC PLL3 Clocks structure definition
+  */
+typedef struct
+{
+  uint32_t PLL3_P_Frequency;
+  uint32_t PLL3_Q_Frequency;
+  uint32_t PLL3_R_Frequency;
+}PLL3_ClocksTypeDef;
+
+
+/**
+  * @brief  RCC extended clocks structure definition
+  */
+typedef struct
+{
+  uint32_t PeriphClockSelection;   /*!< The Extended Clock to be configured.
+                                        This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+  RCC_PLL2InitTypeDef PLL2;        /*!< PLL2structure parameters.
+                                        This parameter will be used only when PLL2 is selected as kernel clock Source for some peripherals */
+
+  RCC_PLL3InitTypeDef PLL3;        /*!< PLL3 structure parameters.
+                                        This parameter will be used only when PLL2 is selected as kernel clock Source for some peripherals */
+
+  uint32_t FmcClockSelection;     /*!< Specifies FMC clock source
+                                        This parameter can be a value of @ref RCCEx_FMC_Clock_Source     */
+
+#if defined(QUADSPI)
+  uint32_t QspiClockSelection;    /*!< Specifies QSPI clock source
+                                        This parameter can be a value of @ref RCCEx_QSPI_Clock_Source    */
+#endif /* QUADSPI */
+
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+  uint32_t OspiClockSelection;    /*!< Specifies OSPI clock source
+                                        This parameter can be a value of @ref RCCEx_OSPI_Clock_Source    */
+#endif /*(OCTOSPI1) || (OCTOSPI2)*/
+
+
+#if defined(DSI)
+  uint32_t DsiClockSelection;     /*!< Specifies DSI clock source
+                                     This parameter can be a value of @ref RCCEx_DSI_Clock_Source        */
+#endif /* DSI */
+
+  uint32_t SdmmcClockSelection;    /*!< Specifies SDMMC clock source
+                                        This parameter can be a value of @ref RCCEx_SDMMC_Clock_Source   */
+
+  uint32_t CkperClockSelection;   /*!< Specifies CKPER clock source
+                                        This parameter can be a value of @ref RCCEx_CLKP_Clock_Source   */
+
+  uint32_t Sai1ClockSelection;     /*!< Specifies SAI1 clock source
+                                        This parameter can be a value of @ref RCCEx_SAI1_Clock_Source    */
+
+#if defined(SAI3)
+  uint32_t Sai23ClockSelection;     /*!< Specifies SAI2/3 clock source
+                                         This parameter can be a value of @ref RCCEx_SAI23_Clock_Source  */
+#endif /* SAI3 */
+
+#if defined(RCC_CDCCIP1R_SAI2ASEL)
+  uint32_t Sai2AClockSelection;     /*!< Specifies SAI2A clock source
+                                        This parameter can be a value of @ref RCCEx_SAI2A_Clock_Source  */
+#endif /* RCC_CDCCIP1R_SAI2ASEL */
+
+#if defined(RCC_CDCCIP1R_SAI2BSEL)
+  uint32_t Sai2BClockSelection;     /*!< Specifies SAI2B clock source
+                                         This parameter can be a value of @ref RCCEx_SAI2B_Clock_Source    */
+#endif /* RCC_CDCCIP1R_SAI2BSEL */
+
+  uint32_t Spi123ClockSelection;     /*!< Specifies SPI1/2/3 clock source
+                                          This parameter can be a value of @ref RCCEx_SPI123_Clock_Source    */
+
+  uint32_t Spi45ClockSelection;     /*!< Specifies SPI4/5 clock source
+                                         This parameter can be a value of @ref RCCEx_SPI45_Clock_Source    */
+
+  uint32_t SpdifrxClockSelection;   /*!< Specifies SPDIFRX Clock clock source
+                                        This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */
+
+  uint32_t Dfsdm1ClockSelection;    /*!< Specifies DFSDM1 Clock clock source
+                                        This parameter can be a value of @ref RCCEx_DFSDM1_Clock_Source  */
+
+#if defined(DFSDM2_BASE)
+  uint32_t Dfsdm2ClockSelection;    /*!< Specifies DFSDM2 Clock clock source
+                                        This parameter can be a value of @ref RCCEx_DFSDM2_Clock_Source  */
+#endif /* DFSDM2_BASE */
+
+#if defined(FDCAN1) || defined(FDCAN2)
+  uint32_t FdcanClockSelection;   /*!< Specifies FDCAN Clock clock source
+                                        This parameter can be a value of @ref RCCEx_FDCAN_Clock_Source   */
+#endif /*FDCAN1 || FDCAN2*/
+
+  uint32_t Swpmi1ClockSelection;   /*!< Specifies SWPMI1 Clock clock source
+                                        This parameter can be a value of @ref RCCEx_SWPMI1_Clock_Source  */
+
+  uint32_t Usart234578ClockSelection;   /*!< Specifies USART2/3/4/5/7/8 clock source
+                                             This parameter can be a value of @ref RCCEx_USART234578_Clock_Source  */
+
+  uint32_t Usart16ClockSelection;  /*!< Specifies USART1/6 clock source
+                                        This parameter can be a value of @ref RCCEx_USART16_Clock_Source  */
+
+   uint32_t RngClockSelection;      /*!< Specifies RNG clock source
+                                        This parameter can be a value of @ref RCCEx_RNG_Clock_Source     */
+
+   uint32_t I2c123ClockSelection;   /*!< Specifies I2C1/2/3 clock source
+                                        This parameter can be a value of @ref RCCEx_I2C123_Clock_Source    */
+
+  uint32_t UsbClockSelection;      /*!< Specifies USB clock source
+                                        This parameter can be a value of @ref RCCEx_USB_Clock_Source     */
+
+  uint32_t CecClockSelection;     /*!< Specifies CEC clock source
+                                        This parameter can be a value of @ref RCCEx_CEC_Clock_Source     */
+
+  uint32_t Lptim1ClockSelection;   /*!< Specifies LPTIM1 clock source
+                                        This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source  */
+
+  uint32_t Lpuart1ClockSelection;  /*!< Specifies LPUART1 clock source
+                                        This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
+
+  uint32_t I2c4ClockSelection;     /*!< Specifies I2C4 clock source
+                                        This parameter can be a value of @ref RCCEx_I2C4_Clock_Source    */
+
+  uint32_t Lptim2ClockSelection;   /*!< Specifies LPTIM2 clock source
+                                        This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source  */
+
+  uint32_t Lptim345ClockSelection;   /*!< Specifies LPTIM3/4/5 clock source
+                                          This parameter can be a value of @ref RCCEx_LPTIM345_Clock_Source  */
+
+  uint32_t AdcClockSelection;      /*!< Specifies ADC interface clock source
+                                        This parameter can be a value of @ref RCCEx_ADC_Clock_Source     */
+#if defined(SAI4)
+  uint32_t Sai4AClockSelection;     /*!< Specifies SAI4A clock source
+                                        This parameter can be a value of @ref RCCEx_SAI4A_Clock_Source   */
+
+  uint32_t Sai4BClockSelection;     /*!< Specifies SAI4B clock source
+                                        This parameter can be a value of @ref RCCEx_SAI4B_Clock_Source   */
+#endif /* SAI4 */
+
+  uint32_t Spi6ClockSelection;     /*!< Specifies SPI6 clock source
+                                        This parameter can be a value of @ref RCCEx_SPI6_Clock_Source    */
+
+  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock clock source
+                                        This parameter can be a value of @ref RCC_RTC_Clock_Source       */
+
+#if defined(HRTIM1)
+  uint32_t Hrtim1ClockSelection;      /*!< Specifies HRTIM1 Clock clock source
+                                        This parameter can be a value of @ref RCCEx_HRTIM1_Clock_Source   */
+#endif /* HRTIM1 */
+
+  uint32_t TIMPresSelection;       /*!< Specifies TIM Clock Prescalers Selection.
+                                       This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */
+}RCC_PeriphCLKInitTypeDef;
+
+
+/**
+  * @brief RCC_CRS Init structure definition
+  */
+typedef struct
+{
+  uint32_t Prescaler;             /*!< Specifies the division factor of the SYNC signal.
+                                     This parameter can be a value of @ref RCCEx_CRS_SynchroDivider  */
+
+  uint32_t Source;                /*!< Specifies the SYNC signal source.
+                                     This parameter can be a value of @ref RCCEx_CRS_SynchroSource   */
+
+  uint32_t Polarity;              /*!< Specifies the input polarity for the SYNC signal source.
+                                     This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
+
+  uint32_t ReloadValue;           /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
+                                      It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)
+                                     This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
+
+  uint32_t ErrorLimitValue;       /*!< Specifies the value to be used to evaluate the captured frequency error value.
+                                     This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
+
+  uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
+                                     This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
+
+}RCC_CRSInitTypeDef;
+
+/**
+  * @brief RCC_CRS Synchronization structure definition
+  */
+typedef struct
+{
+  uint32_t ReloadValue;           /*!< Specifies the value loaded in the Counter reload value.
+                                     This parameter must be a number between 0 and 0xFFFF */
+
+  uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
+                                     This parameter must be a number between 0 and 0x3F */
+
+  uint32_t FreqErrorCapture;      /*!< Specifies the value loaded in the .FECAP, the frequency error counter
+                                                                    value latched in the time of the last SYNC event.
+                                    This parameter must be a number between 0 and 0xFFFF */
+
+  uint32_t FreqErrorDirection;    /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
+                                                                    frequency error counter latched in the time of the last SYNC event.
+                                                                    It shows whether the actual frequency is below or above the target.
+                                    This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
+
+}RCC_CRSSynchroInfoTypeDef;
+
+/**
+  * @}
+  */
+
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Constants  RCCEx Exported Constants
+  * @{
+  */
+
+/** @defgroup RCCEx_Periph_Clock_Selection  RCCEx Periph Clock Selection
+  * @{
+  */
+
+#if defined(UART9) && defined(USART10)
+#define RCC_PERIPHCLK_USART16910       (0x00000001U)
+#define RCC_PERIPHCLK_USART1           RCC_PERIPHCLK_USART16910
+#define RCC_PERIPHCLK_USART6           RCC_PERIPHCLK_USART16910
+#define RCC_PERIPHCLK_UART9            RCC_PERIPHCLK_USART16910
+#define RCC_PERIPHCLK_USART10          RCC_PERIPHCLK_USART16910
+/*alias*/
+#define RCC_PERIPHCLK_USART16          RCC_PERIPHCLK_USART16910
+#else
+#define RCC_PERIPHCLK_USART16          (0x00000001U)
+#define RCC_PERIPHCLK_USART1           RCC_PERIPHCLK_USART16
+#define RCC_PERIPHCLK_USART6           RCC_PERIPHCLK_USART16
+/* alias */
+#define RCC_PERIPHCLK_USART16910       RCC_PERIPHCLK_USART16
+#endif /* UART9 && USART10*/
+#define RCC_PERIPHCLK_USART234578      (0x00000002U)
+#define RCC_PERIPHCLK_USART2           RCC_PERIPHCLK_USART234578
+#define RCC_PERIPHCLK_USART3           RCC_PERIPHCLK_USART234578
+#define RCC_PERIPHCLK_UART4            RCC_PERIPHCLK_USART234578
+#define RCC_PERIPHCLK_UART5            RCC_PERIPHCLK_USART234578
+#define RCC_PERIPHCLK_UART7            RCC_PERIPHCLK_USART234578
+#define RCC_PERIPHCLK_UART8            RCC_PERIPHCLK_USART234578
+#define RCC_PERIPHCLK_LPUART1          (0x00000004U)
+#define RCC_PERIPHCLK_I2C123           (0x00000008U)
+#define RCC_PERIPHCLK_I2C1             RCC_PERIPHCLK_I2C123
+#define RCC_PERIPHCLK_I2C2             RCC_PERIPHCLK_I2C123
+#define RCC_PERIPHCLK_I2C3             RCC_PERIPHCLK_I2C123
+#define RCC_PERIPHCLK_I2C4             (0x00000010U)
+#define RCC_PERIPHCLK_LPTIM1           (0x00000020U)
+#define RCC_PERIPHCLK_LPTIM2           (0x00000040U)
+#define RCC_PERIPHCLK_LPTIM345         (0x00000080U)
+#define RCC_PERIPHCLK_LPTIM3           RCC_PERIPHCLK_LPTIM345
+#if defined(LPTIM4)
+#define RCC_PERIPHCLK_LPTIM4           RCC_PERIPHCLK_LPTIM345
+#endif /*LPTIM4*/
+#if defined(LPTIM5)
+#define RCC_PERIPHCLK_LPTIM5           RCC_PERIPHCLK_LPTIM345
+#endif /*LPTIM5*/
+#define RCC_PERIPHCLK_SAI1             (0x00000100U)
+#if defined(SAI3)
+#define RCC_PERIPHCLK_SAI23            (0x00000200U)
+#define RCC_PERIPHCLK_SAI2             RCC_PERIPHCLK_SAI23
+#define RCC_PERIPHCLK_SAI3             RCC_PERIPHCLK_SAI23
+#endif /* SAI3 */
+#if defined(RCC_CDCCIP1R_SAI2ASEL_0)
+#define RCC_PERIPHCLK_SAI2A            (0x00000200U)
+#endif /* RCC_CDCCIP1R_SAI2ASEL_0 */
+#if defined(RCC_CDCCIP1R_SAI2BSEL_0)
+#define RCC_PERIPHCLK_SAI2B            (0x00000400U)
+#endif /* RCC_CDCCIP1R_SAI2BSEL_0 */
+#if defined(SAI4)
+#define RCC_PERIPHCLK_SAI4A            (0x00000400U)
+#define RCC_PERIPHCLK_SAI4B            (0x00000800U)
+#endif /* SAI4 */
+#define RCC_PERIPHCLK_SPI123           (0x00001000U)
+#define RCC_PERIPHCLK_SPI1             RCC_PERIPHCLK_SPI123
+#define RCC_PERIPHCLK_SPI2             RCC_PERIPHCLK_SPI123
+#define RCC_PERIPHCLK_SPI3             RCC_PERIPHCLK_SPI123
+#define RCC_PERIPHCLK_SPI45            (0x00002000U)
+#define RCC_PERIPHCLK_SPI4             RCC_PERIPHCLK_SPI45
+#define RCC_PERIPHCLK_SPI5             RCC_PERIPHCLK_SPI45
+#define RCC_PERIPHCLK_SPI6             (0x00004000U)
+#define RCC_PERIPHCLK_FDCAN            (0x00008000U)
+#define RCC_PERIPHCLK_SDMMC            (0x00010000U)
+#define RCC_PERIPHCLK_RNG              (0x00020000U)
+#define RCC_PERIPHCLK_USB              (0x00040000U)
+#define RCC_PERIPHCLK_ADC              (0x00080000U)
+#define RCC_PERIPHCLK_SWPMI1           (0x00100000U)
+#define RCC_PERIPHCLK_DFSDM1           (0x00200000U)
+#if defined(DFSDM2_BASE)
+#define RCC_PERIPHCLK_DFSDM2           (0x00000800U)
+#endif /* DFSDM2 */
+#define RCC_PERIPHCLK_RTC              (0x00400000U)
+#define RCC_PERIPHCLK_CEC              (0x00800000U)
+#define RCC_PERIPHCLK_FMC              (0x01000000U)
+#if defined(QUADSPI)
+#define RCC_PERIPHCLK_QSPI             (0x02000000U)
+#endif /* QUADSPI */
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+#define RCC_PERIPHCLK_OSPI             (0x02000000U)
+#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
+#define RCC_PERIPHCLK_DSI              (0x04000000U)
+#define RCC_PERIPHCLK_SPDIFRX          (0x08000000U)
+#if defined(HRTIM1)
+#define RCC_PERIPHCLK_HRTIM1           (0x10000000U)
+#endif /* HRTIM1 */
+#if defined(LTDC)
+#define RCC_PERIPHCLK_LTDC             (0x20000000U)
+#endif /* LTDC */
+#define RCC_PERIPHCLK_TIM              (0x40000000U)
+#define RCC_PERIPHCLK_CKPER            (0x80000000U)
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_PLL2_Clock_Output  RCC PLL2 Clock Output
+  * @{
+  */
+#define RCC_PLL2_DIVP                RCC_PLLCFGR_DIVP2EN
+#define RCC_PLL2_DIVQ                RCC_PLLCFGR_DIVQ2EN
+#define RCC_PLL2_DIVR                RCC_PLLCFGR_DIVR2EN
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLL3_Clock_Output  RCC PLL3 Clock Output
+  * @{
+  */
+#define RCC_PLL3_DIVP                RCC_PLLCFGR_DIVP3EN
+#define RCC_PLL3_DIVQ                RCC_PLLCFGR_DIVQ3EN
+#define RCC_PLL3_DIVR                RCC_PLLCFGR_DIVR3EN
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLL2_VCI_Range  RCC PLL2 VCI Range
+  * @{
+  */
+#define RCC_PLL2VCIRANGE_0                RCC_PLLCFGR_PLL2RGE_0        /*!< Clock range frequency between 1 and 2 MHz  */
+#define RCC_PLL2VCIRANGE_1                RCC_PLLCFGR_PLL2RGE_1        /*!< Clock range frequency between 2 and 4 MHz  */
+#define RCC_PLL2VCIRANGE_2                RCC_PLLCFGR_PLL2RGE_2        /*!< Clock range frequency between 4 and 8 MHz  */
+#define RCC_PLL2VCIRANGE_3                RCC_PLLCFGR_PLL2RGE_3        /*!< Clock range frequency between 8 and 16 MHz */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_PLL2_VCO_Range  RCC PLL2 VCO Range
+  * @{
+  */
+#define RCC_PLL2VCOWIDE                 (0x00000000U)
+#define RCC_PLL2VCOMEDIUM               RCC_PLLCFGR_PLL2VCOSEL
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLL3_VCI_Range  RCC PLL3 VCI Range
+  * @{
+  */
+#define RCC_PLL3VCIRANGE_0                RCC_PLLCFGR_PLL3RGE_0         /*!< Clock range frequency between 1 and 2 MHz  */
+#define RCC_PLL3VCIRANGE_1                RCC_PLLCFGR_PLL3RGE_1         /*!< Clock range frequency between 2 and 4 MHz  */
+#define RCC_PLL3VCIRANGE_2                RCC_PLLCFGR_PLL3RGE_2         /*!< Clock range frequency between 4 and 8 MHz  */
+#define RCC_PLL3VCIRANGE_3                RCC_PLLCFGR_PLL3RGE_3         /*!< Clock range frequency between 8 and 16 MHz */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RCC_PLL3_VCO_Range  RCC PLL3 VCO Range
+  * @{
+  */
+#define RCC_PLL3VCOWIDE                 (0x00000000U)
+#define RCC_PLL3VCOMEDIUM               RCC_PLLCFGR_PLL3VCOSEL
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_USART16_Clock_Source  RCCEx USART1/6 Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP2R_USART16SEL)
+#define RCC_USART16CLKSOURCE_D2PCLK2    (0x00000000U)
+/* alias */
+#define RCC_USART16CLKSOURCE_PCLK2        RCC_USART16CLKSOURCE_D2PCLK2
+#define RCC_USART16CLKSOURCE_PLL2         RCC_D2CCIP2R_USART16SEL_0
+#define RCC_USART16CLKSOURCE_PLL3         RCC_D2CCIP2R_USART16SEL_1
+#define RCC_USART16CLKSOURCE_HSI         (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_1)
+#define RCC_USART16CLKSOURCE_CSI          RCC_D2CCIP2R_USART16SEL_2
+#define RCC_USART16CLKSOURCE_LSE         (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_2)
+
+#else
+#define RCC_USART16910CLKSOURCE_CDPCLK2   (0x00000000U)
+/* alias */
+#define RCC_USART16910CLKSOURCE_D2PCLK2   RCC_USART16910CLKSOURCE_CDPCLK2
+#define RCC_USART16910CLKSOURCE_PLL2      RCC_CDCCIP2R_USART16910SEL_0
+#define RCC_USART16910CLKSOURCE_PLL3      RCC_CDCCIP2R_USART16910SEL_1
+#define RCC_USART16910CLKSOURCE_HSI      (RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_1)
+#define RCC_USART16910CLKSOURCE_CSI       RCC_CDCCIP2R_USART16910SEL_2
+#define RCC_USART16910CLKSOURCE_LSE      (RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_2)
+
+/*  Aliases */
+#define RCC_USART16CLKSOURCE_CDPCLK2     RCC_USART16910CLKSOURCE_CDPCLK2
+#define RCC_USART16CLKSOURCE_PCLK2       RCC_USART16CLKSOURCE_CDPCLK2
+#define RCC_USART16CLKSOURCE_D2PCLK2     RCC_USART16CLKSOURCE_CDPCLK2
+#define RCC_USART16CLKSOURCE_PLL2        RCC_USART16910CLKSOURCE_PLL2
+#define RCC_USART16CLKSOURCE_PLL3        RCC_USART16910CLKSOURCE_PLL3
+#define RCC_USART16CLKSOURCE_HSI         RCC_USART16910CLKSOURCE_HSI
+#define RCC_USART16CLKSOURCE_CSI         RCC_USART16910CLKSOURCE_CSI
+#define RCC_USART16CLKSOURCE_LSE         RCC_USART16910CLKSOURCE_LSE
+#endif /* RCC_D2CCIP2R_USART16SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_USART1_Clock_Source  RCCEx USART1 Clock Source
+  * @{
+  */
+#define RCC_USART1CLKSOURCE_D2PCLK2   RCC_USART16CLKSOURCE_D2PCLK2
+#define RCC_USART1CLKSOURCE_PLL2      RCC_USART16CLKSOURCE_PLL2
+#define RCC_USART1CLKSOURCE_PLL3      RCC_USART16CLKSOURCE_PLL3
+#define RCC_USART1CLKSOURCE_HSI       RCC_USART16CLKSOURCE_HSI
+#define RCC_USART1CLKSOURCE_CSI       RCC_USART16CLKSOURCE_CSI
+#define RCC_USART1CLKSOURCE_LSE       RCC_USART16CLKSOURCE_LSE
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_USART6_Clock_Source  RCCEx USART6 Clock Source
+  * @{
+  */
+#define RCC_USART6CLKSOURCE_D2PCLK2   RCC_USART16CLKSOURCE_D2PCLK2
+#define RCC_USART6CLKSOURCE_PLL2      RCC_USART16CLKSOURCE_PLL2
+#define RCC_USART6CLKSOURCE_PLL3      RCC_USART16CLKSOURCE_PLL3
+#define RCC_USART6CLKSOURCE_HSI       RCC_USART16CLKSOURCE_HSI
+#define RCC_USART6CLKSOURCE_CSI       RCC_USART16CLKSOURCE_CSI
+#define RCC_USART6CLKSOURCE_LSE       RCC_USART16CLKSOURCE_LSE
+
+/**
+  * @}
+  */
+
+#if defined(UART9)
+/** @defgroup RCCEx_UART9_Clock_Source  RCCEx UART9 Clock Source
+  * @{
+  */
+#define RCC_UART9CLKSOURCE_D2PCLK2   RCC_USART16CLKSOURCE_D2PCLK2
+#define RCC_UART9CLKSOURCE_PLL2      RCC_USART16CLKSOURCE_PLL2
+#define RCC_UART9CLKSOURCE_PLL3      RCC_USART16CLKSOURCE_PLL3
+#define RCC_UART9CLKSOURCE_HSI       RCC_USART16CLKSOURCE_HSI
+#define RCC_UART9CLKSOURCE_CSI       RCC_USART16CLKSOURCE_CSI
+#define RCC_UART9CLKSOURCE_LSE       RCC_USART16CLKSOURCE_LSE
+/**
+  * @}
+  */
+#endif /* UART9 */
+
+#if defined(USART10)
+/** @defgroup RCCEx_USART10_Clock_Source  RCCEx USART10 Clock Source
+  * @{
+  */
+#define RCC_USART10CLKSOURCE_D2PCLK2   RCC_USART16CLKSOURCE_D2PCLK2
+#define RCC_USART10CLKSOURCE_PLL2      RCC_USART16CLKSOURCE_PLL2
+#define RCC_USART10CLKSOURCE_PLL3      RCC_USART16CLKSOURCE_PLL3
+#define RCC_USART10CLKSOURCE_HSI       RCC_USART16CLKSOURCE_HSI
+#define RCC_USART10CLKSOURCE_CSI       RCC_USART16CLKSOURCE_CSI
+#define RCC_USART10CLKSOURCE_LSE       RCC_USART16CLKSOURCE_LSE
+/**
+  * @}
+  */
+#endif /* USART10 */
+
+/** @defgroup RCCEx_USART234578_Clock_Source  RCCEx USART2/3/4/5/7/8 Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP2R_USART28SEL)
+#define RCC_USART234578CLKSOURCE_D2PCLK1    (0x00000000U)
+/* alias */
+#define RCC_USART234578CLKSOURCE_PCLK1      RCC_USART234578CLKSOURCE_D2PCLK1
+#define RCC_USART234578CLKSOURCE_PLL2       RCC_D2CCIP2R_USART28SEL_0
+#define RCC_USART234578CLKSOURCE_PLL3       RCC_D2CCIP2R_USART28SEL_1
+#define RCC_USART234578CLKSOURCE_HSI        (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)
+#define RCC_USART234578CLKSOURCE_CSI        RCC_D2CCIP2R_USART28SEL_2
+#define RCC_USART234578CLKSOURCE_LSE        (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)
+#else
+#define RCC_USART234578CLKSOURCE_CDPCLK1   (0x00000000U)
+/* alias */
+#define RCC_USART234578CLKSOURCE_PCLK1     RCC_USART234578CLKSOURCE_CDPCLK1
+#define RCC_USART234578CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_CDPCLK1
+#define RCC_USART234578CLKSOURCE_PLL2      RCC_CDCCIP2R_USART234578SEL_0
+#define RCC_USART234578CLKSOURCE_PLL3      RCC_CDCCIP2R_USART234578SEL_1
+#define RCC_USART234578CLKSOURCE_HSI      (RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_1)
+#define RCC_USART234578CLKSOURCE_CSI       RCC_CDCCIP2R_USART234578SEL_2
+#define RCC_USART234578CLKSOURCE_LSE      (RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_2)
+#endif /* RCC_D2CCIP2R_USART28SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_USART2_Clock_Source  RCCEx USART2 Clock Source
+  * @{
+  */
+#define RCC_USART2CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1
+#define RCC_USART2CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2
+#define RCC_USART2CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3
+#define RCC_USART2CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI
+#define RCC_USART2CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI
+#define RCC_USART2CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_USART3_Clock_Source  RCCEx USART3 Clock Source
+  * @{
+  */
+#define RCC_USART3CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1
+#define RCC_USART3CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2
+#define RCC_USART3CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3
+#define RCC_USART3CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI
+#define RCC_USART3CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI
+#define RCC_USART3CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_UART4_Clock_Source  RCCEx UART4 Clock Source
+  * @{
+  */
+#define RCC_UART4CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1
+#define RCC_UART4CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2
+#define RCC_UART4CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3
+#define RCC_UART4CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI
+#define RCC_UART4CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI
+#define RCC_UART4CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_UART5_Clock_Source  RCCEx UART5 Clock Source
+  * @{
+  */
+#define RCC_UART5CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1
+#define RCC_UART5CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2
+#define RCC_UART5CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3
+#define RCC_UART5CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI
+#define RCC_UART5CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI
+#define RCC_UART5CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_UART7_Clock_Source  RCCEx UART7 Clock Source
+  * @{
+  */
+#define RCC_UART7CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1
+#define RCC_UART7CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2
+#define RCC_UART7CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3
+#define RCC_UART7CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI
+#define RCC_UART7CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI
+#define RCC_UART7CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_UART8_Clock_Source  RCCEx UART8 Clock Source
+  * @{
+  */
+#define RCC_UART8CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1
+#define RCC_UART8CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2
+#define RCC_UART8CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3
+#define RCC_UART8CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI
+#define RCC_UART8CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI
+#define RCC_UART8CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_LPUART1_Clock_Source  RCCEx LPUART1 Clock Source
+  * @{
+  */
+#if defined(RCC_D3CCIPR_LPUART1SEL)
+#define RCC_LPUART1CLKSOURCE_D3PCLK1    (0x00000000U)
+/* alias */
+#define RCC_LPUART1CLKSOURCE_PCLK4     RCC_LPUART1CLKSOURCE_D3PCLK1
+#define RCC_LPUART1CLKSOURCE_PLL2      RCC_D3CCIPR_LPUART1SEL_0
+#define RCC_LPUART1CLKSOURCE_PLL3      RCC_D3CCIPR_LPUART1SEL_1
+#define RCC_LPUART1CLKSOURCE_HSI       (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_1)
+#define RCC_LPUART1CLKSOURCE_CSI        RCC_D3CCIPR_LPUART1SEL_2
+#define RCC_LPUART1CLKSOURCE_LSE       (RCC_D3CCIPR_LPUART1SEL_2 | RCC_D3CCIPR_LPUART1SEL_0)
+#else
+#define RCC_LPUART1CLKSOURCE_SRDPCLK4   (0x00000000U)
+/* alias*/
+#define RCC_LPUART1CLKSOURCE_PCLK4     RCC_LPUART1CLKSOURCE_SRDPCLK4
+#define RCC_LPUART1CLKSOURCE_D3PCLK1   RCC_LPUART1CLKSOURCE_SRDPCLK4
+#define RCC_LPUART1CLKSOURCE_PLL2      RCC_SRDCCIPR_LPUART1SEL_0
+#define RCC_LPUART1CLKSOURCE_PLL3      RCC_SRDCCIPR_LPUART1SEL_1
+#define RCC_LPUART1CLKSOURCE_HSI       (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_1)
+#define RCC_LPUART1CLKSOURCE_CSI        RCC_SRDCCIPR_LPUART1SEL_2
+#define RCC_LPUART1CLKSOURCE_LSE       (RCC_SRDCCIPR_LPUART1SEL_2 | RCC_SRDCCIPR_LPUART1SEL_0)
+#endif /* RCC_D3CCIPR_LPUART1SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_I2C123_Clock_Source  RCCEx I2C1/2/3 Clock Source
+  * @{
+  */
+#if defined (RCC_D2CCIP2R_I2C123SEL)
+#define RCC_I2C123CLKSOURCE_D2PCLK1      (0x00000000U)
+#define RCC_I2C123CLKSOURCE_PLL3         RCC_D2CCIP2R_I2C123SEL_0
+#define RCC_I2C123CLKSOURCE_HSI          RCC_D2CCIP2R_I2C123SEL_1
+#define RCC_I2C123CLKSOURCE_CSI         (RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1)
+#else
+#define RCC_I2C123CLKSOURCE_CDPCLK1      (0x00000000U)
+/* alias */
+#define RCC_I2C123CLKSOURCE_D2PCLK1      RCC_I2C123CLKSOURCE_CDPCLK1
+#define RCC_I2C123CLKSOURCE_PLL3         RCC_CDCCIP2R_I2C123SEL_0
+#define RCC_I2C123CLKSOURCE_HSI          RCC_CDCCIP2R_I2C123SEL_1
+#define RCC_I2C123CLKSOURCE_CSI         (RCC_CDCCIP2R_I2C123SEL_0 | RCC_CDCCIP2R_I2C123SEL_1)
+#endif /* RCC_D2CCIP2R_I2C123SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_I2C1_Clock_Source  RCCEx I2C1 Clock Source
+  * @{
+  */
+#define RCC_I2C1CLKSOURCE_D2PCLK1     RCC_I2C123CLKSOURCE_D2PCLK1
+#define RCC_I2C1CLKSOURCE_PLL3        RCC_I2C123CLKSOURCE_PLL3
+#define RCC_I2C1CLKSOURCE_HSI         RCC_I2C123CLKSOURCE_HSI
+#define RCC_I2C1CLKSOURCE_CSI         RCC_I2C123CLKSOURCE_CSI
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_I2C2_Clock_Source  RCCEx I2C2 Clock Source
+  * @{
+  */
+#define RCC_I2C2CLKSOURCE_D2PCLK1     RCC_I2C123CLKSOURCE_D2PCLK1
+#define RCC_I2C2CLKSOURCE_PLL3        RCC_I2C123CLKSOURCE_PLL3
+#define RCC_I2C2CLKSOURCE_HSI         RCC_I2C123CLKSOURCE_HSI
+#define RCC_I2C2CLKSOURCE_CSI         RCC_I2C123CLKSOURCE_CSI
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_I2C3_Clock_Source  RCCEx I2C3 Clock Source
+  * @{
+  */
+#define RCC_I2C3CLKSOURCE_D2PCLK1     RCC_I2C123CLKSOURCE_D2PCLK1
+#define RCC_I2C3CLKSOURCE_PLL3        RCC_I2C123CLKSOURCE_PLL3
+#define RCC_I2C3CLKSOURCE_HSI         RCC_I2C123CLKSOURCE_HSI
+#define RCC_I2C3CLKSOURCE_CSI         RCC_I2C123CLKSOURCE_CSI
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_I2C4_Clock_Source  RCCEx I2C4 Clock Source
+  * @{
+  */
+#if defined(RCC_D3CCIPR_I2C4SEL)
+#define RCC_I2C4CLKSOURCE_D3PCLK1      (0x00000000U)
+#define RCC_I2C4CLKSOURCE_PLL3         RCC_D3CCIPR_I2C4SEL_0
+#define RCC_I2C4CLKSOURCE_HSI          RCC_D3CCIPR_I2C4SEL_1
+#define RCC_I2C4CLKSOURCE_CSI         (RCC_D3CCIPR_I2C4SEL_0 | RCC_D3CCIPR_I2C4SEL_1)
+#else
+#define RCC_I2C4CLKSOURCE_SRDPCLK4     (0x00000000U)
+/* alias */
+#define RCC_I2C4CLKSOURCE_D3PCLK1     RCC_I2C4CLKSOURCE_SRDPCLK4
+#define RCC_I2C4CLKSOURCE_PLL3         RCC_SRDCCIPR_I2C4SEL_0
+#define RCC_I2C4CLKSOURCE_HSI          RCC_SRDCCIPR_I2C4SEL_1
+#define RCC_I2C4CLKSOURCE_CSI         (RCC_SRDCCIPR_I2C4SEL_0 | RCC_SRDCCIPR_I2C4SEL_1)
+#endif /* RCC_D3CCIPR_I2C4SEL */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_RNG_Clock_Source  RCCEx RNG Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP2R_RNGSEL)
+#define RCC_RNGCLKSOURCE_HSI48        (0x00000000U)
+#define RCC_RNGCLKSOURCE_PLL           RCC_D2CCIP2R_RNGSEL_0
+#define RCC_RNGCLKSOURCE_LSE           RCC_D2CCIP2R_RNGSEL_1
+#define RCC_RNGCLKSOURCE_LSI           RCC_D2CCIP2R_RNGSEL
+#else
+#define RCC_RNGCLKSOURCE_HSI48        (0x00000000U)
+#define RCC_RNGCLKSOURCE_PLL           RCC_CDCCIP2R_RNGSEL_0
+#define RCC_RNGCLKSOURCE_LSE           RCC_CDCCIP2R_RNGSEL_1
+#define RCC_RNGCLKSOURCE_LSI           RCC_CDCCIP2R_RNGSEL
+#endif /* RCC_D2CCIP2R_RNGSEL */
+
+/**
+  * @}
+  */
+#if defined(HRTIM1)
+
+/** @defgroup RCCEx_HRTIM1_Clock_Source RCC Extended HRTIM1 Clock Source
+  * @{
+  */
+#define RCC_HRTIM1CLK_TIMCLK                (0x00000000U)
+#define RCC_HRTIM1CLK_CPUCLK                RCC_CFGR_HRTIMSEL
+
+/**
+  * @}
+  */
+#endif /*HRTIM1*/
+
+/** @defgroup RCCEx_USB_Clock_Source  RCCEx USB Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP2R_USBSEL)
+#define RCC_USBCLKSOURCE_PLL                  RCC_D2CCIP2R_USBSEL_0
+#define RCC_USBCLKSOURCE_PLL3                 RCC_D2CCIP2R_USBSEL_1
+#define RCC_USBCLKSOURCE_HSI48                RCC_D2CCIP2R_USBSEL
+#else
+#define RCC_USBCLKSOURCE_PLL                  RCC_CDCCIP2R_USBSEL_0
+#define RCC_USBCLKSOURCE_PLL3                 RCC_CDCCIP2R_USBSEL_1
+#define RCC_USBCLKSOURCE_HSI48                RCC_CDCCIP2R_USBSEL
+#endif /* RCC_D2CCIP2R_USBSEL */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_SAI1SEL)
+#define RCC_SAI1CLKSOURCE_PLL         (0x00000000U)
+#define RCC_SAI1CLKSOURCE_PLL2         RCC_D2CCIP1R_SAI1SEL_0
+#define RCC_SAI1CLKSOURCE_PLL3         RCC_D2CCIP1R_SAI1SEL_1
+#define RCC_SAI1CLKSOURCE_PIN         (RCC_D2CCIP1R_SAI1SEL_0 | RCC_D2CCIP1R_SAI1SEL_1)
+#define RCC_SAI1CLKSOURCE_CLKP         RCC_D2CCIP1R_SAI1SEL_2
+#else
+#define RCC_SAI1CLKSOURCE_PLL         (0x00000000U)
+#define RCC_SAI1CLKSOURCE_PLL2         RCC_CDCCIP1R_SAI1SEL_0
+#define RCC_SAI1CLKSOURCE_PLL3         RCC_CDCCIP1R_SAI1SEL_1
+#define RCC_SAI1CLKSOURCE_PIN         (RCC_CDCCIP1R_SAI1SEL_0 | RCC_CDCCIP1R_SAI1SEL_1)
+#define RCC_SAI1CLKSOURCE_CLKP         RCC_CDCCIP1R_SAI1SEL_2
+#endif /* RCC_D2CCIP1R_SAI1SEL */
+/**
+  * @}
+  */
+
+#if defined(SAI3)
+/** @defgroup RCCEx_SAI23_Clock_Source SAI2/3 Clock Source
+  * @{
+  */
+#define RCC_SAI23CLKSOURCE_PLL         (0x00000000U)
+#define RCC_SAI23CLKSOURCE_PLL2         RCC_D2CCIP1R_SAI23SEL_0
+#define RCC_SAI23CLKSOURCE_PLL3         RCC_D2CCIP1R_SAI23SEL_1
+#define RCC_SAI23CLKSOURCE_PIN         (RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1)
+#define RCC_SAI23CLKSOURCE_CLKP         RCC_D2CCIP1R_SAI23SEL_2
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source
+  * @{
+  */
+#define RCC_SAI2CLKSOURCE_PLL         RCC_SAI23CLKSOURCE_PLL
+#define RCC_SAI2CLKSOURCE_PLL2        RCC_SAI23CLKSOURCE_PLL2
+#define RCC_SAI2CLKSOURCE_PLL3        RCC_SAI23CLKSOURCE_PLL3
+#define RCC_SAI2CLKSOURCE_PIN         RCC_SAI23CLKSOURCE_PIN
+#define RCC_SAI2CLKSOURCE_CLKP        RCC_SAI23CLKSOURCE_CLKP
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SAI3_Clock_Source SAI3 Clock Source
+  * @{
+  */
+#define RCC_SAI3CLKSOURCE_PLL         RCC_SAI23CLKSOURCE_PLL
+#define RCC_SAI3CLKSOURCE_PLL2        RCC_SAI23CLKSOURCE_PLL2
+#define RCC_SAI3CLKSOURCE_PLL3        RCC_SAI23CLKSOURCE_PLL3
+#define RCC_SAI3CLKSOURCE_PIN         RCC_SAI23CLKSOURCE_PIN
+#define RCC_SAI3CLKSOURCE_CLKP        RCC_SAI23CLKSOURCE_CLKP
+/**
+  * @}
+  */
+#endif /* SAI3 */
+
+#if defined(RCC_CDCCIP1R_SAI2ASEL)
+/** @defgroup RCCEx_SAI2_Clock_A Source SAI2A Clock Source
+  * @{
+  */
+#define RCC_SAI2ACLKSOURCE_PLL         (0x00000000U)
+#define RCC_SAI2ACLKSOURCE_PLL2         RCC_CDCCIP1R_SAI2ASEL_0
+#define RCC_SAI2ACLKSOURCE_PLL3         RCC_CDCCIP1R_SAI2ASEL_1
+#define RCC_SAI2ACLKSOURCE_PIN         (RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_1)
+#define RCC_SAI2ACLKSOURCE_CLKP         RCC_CDCCIP1R_SAI2ASEL_2
+#define RCC_SAI2ACLKSOURCE_SPDIF       (RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_2)
+ /**
+  * @}
+  */
+#endif /* RCC_CDCCIP1R_SAI2ASEL */
+
+#if defined(RCC_CDCCIP1R_SAI2BSEL)
+/** @defgroup RCCEx_SAI2_Block_B Clock_Source SAI2B Clock Source
+  * @{
+  */
+#define RCC_SAI2BCLKSOURCE_PLL         (0x00000000U)
+#define RCC_SAI2BCLKSOURCE_PLL2         RCC_CDCCIP1R_SAI2BSEL_0
+#define RCC_SAI2BCLKSOURCE_PLL3         RCC_CDCCIP1R_SAI2BSEL_1
+#define RCC_SAI2BCLKSOURCE_PIN         (RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_1)
+#define RCC_SAI2BCLKSOURCE_CLKP         RCC_CDCCIP1R_SAI2BSEL_2
+#define RCC_SAI2BCLKSOURCE_SPDIF       (RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_2)
+/**
+  * @}
+  */
+#endif /* RCC_CDCCIP1R_SAI2BSEL */
+
+
+/** @defgroup RCCEx_SPI123_Clock_Source SPI1/2/3 Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_SPI123SEL)
+#define RCC_SPI123CLKSOURCE_PLL         (0x00000000U)
+#define RCC_SPI123CLKSOURCE_PLL2         RCC_D2CCIP1R_SPI123SEL_0
+#define RCC_SPI123CLKSOURCE_PLL3         RCC_D2CCIP1R_SPI123SEL_1
+#define RCC_SPI123CLKSOURCE_PIN         (RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1)
+#define RCC_SPI123CLKSOURCE_CLKP         RCC_D2CCIP1R_SPI123SEL_2
+#else
+#define RCC_SPI123CLKSOURCE_PLL         (0x00000000U)
+#define RCC_SPI123CLKSOURCE_PLL2         RCC_CDCCIP1R_SPI123SEL_0
+#define RCC_SPI123CLKSOURCE_PLL3         RCC_CDCCIP1R_SPI123SEL_1
+#define RCC_SPI123CLKSOURCE_PIN         (RCC_CDCCIP1R_SPI123SEL_0 | RCC_CDCCIP1R_SPI123SEL_1)
+#define RCC_SPI123CLKSOURCE_CLKP         RCC_CDCCIP1R_SPI123SEL_2
+#endif /* RCC_D2CCIP1R_SPI123SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SPI1_Clock_Source SPI1 Clock Source
+  * @{
+  */
+#define RCC_SPI1CLKSOURCE_PLL         RCC_SPI123CLKSOURCE_PLL
+#define RCC_SPI1CLKSOURCE_PLL2        RCC_SPI123CLKSOURCE_PLL2
+#define RCC_SPI1CLKSOURCE_PLL3        RCC_SPI123CLKSOURCE_PLL3
+#define RCC_SPI1CLKSOURCE_PIN         RCC_SPI123CLKSOURCE_PIN
+#define RCC_SPI1CLKSOURCE_CLKP        RCC_SPI123CLKSOURCE_CLKP
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SPI2_Clock_Source SPI2 Clock Source
+  * @{
+  */
+#define RCC_SPI2CLKSOURCE_PLL         RCC_SPI123CLKSOURCE_PLL
+#define RCC_SPI2CLKSOURCE_PLL2        RCC_SPI123CLKSOURCE_PLL2
+#define RCC_SPI2CLKSOURCE_PLL3        RCC_SPI123CLKSOURCE_PLL3
+#define RCC_SPI2CLKSOURCE_PIN         RCC_SPI123CLKSOURCE_PIN
+#define RCC_SPI2CLKSOURCE_CLKP        RCC_SPI123CLKSOURCE_CLKP
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SPI3_Clock_Source SPI3 Clock Source
+  * @{
+  */
+#define RCC_SPI3CLKSOURCE_PLL         RCC_SPI123CLKSOURCE_PLL
+#define RCC_SPI3CLKSOURCE_PLL2        RCC_SPI123CLKSOURCE_PLL2
+#define RCC_SPI3CLKSOURCE_PLL3        RCC_SPI123CLKSOURCE_PLL3
+#define RCC_SPI3CLKSOURCE_PIN         RCC_SPI123CLKSOURCE_PIN
+#define RCC_SPI3CLKSOURCE_CLKP        RCC_SPI123CLKSOURCE_CLKP
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SPI45_Clock_Source SPI4/5 Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_SPI45SEL)
+#define RCC_SPI45CLKSOURCE_D2PCLK1     (0x00000000U)
+#define RCC_SPI45CLKSOURCE_PCLK1        RCC_SPI45CLKSOURCE_D2PCLK1
+#define RCC_SPI45CLKSOURCE_PLL2         RCC_D2CCIP1R_SPI45SEL_0
+#define RCC_SPI45CLKSOURCE_PLL3         RCC_D2CCIP1R_SPI45SEL_1
+#define RCC_SPI45CLKSOURCE_HSI         (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_1)
+#define RCC_SPI45CLKSOURCE_CSI          RCC_D2CCIP1R_SPI45SEL_2
+#define RCC_SPI45CLKSOURCE_HSE         (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_2)
+#else
+#define RCC_SPI45CLKSOURCE_CDPCLK1     (0x00000000U)
+/* aliases */
+#define RCC_SPI45CLKSOURCE_D2PCLK1      RCC_SPI45CLKSOURCE_CDPCLK1  /* D2PCLK1 is used in STM32H74xxx, STM32H75xxx, STM32H72xxx and STM32H73xxx family lines */
+#define RCC_SPI45CLKSOURCE_PCLK1        RCC_SPI45CLKSOURCE_CDPCLK1
+#define RCC_SPI45CLKSOURCE_PLL2         RCC_CDCCIP1R_SPI45SEL_0
+#define RCC_SPI45CLKSOURCE_PLL3         RCC_CDCCIP1R_SPI45SEL_1
+#define RCC_SPI45CLKSOURCE_HSI         (RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_1)
+#define RCC_SPI45CLKSOURCE_CSI          RCC_CDCCIP1R_SPI45SEL_2
+#define RCC_SPI45CLKSOURCE_HSE         (RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_2)
+#endif /* RCC_D2CCIP1R_SPI45SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SPI4_Clock_Source SPI4 Clock Source
+  * @{
+  */
+#define RCC_SPI4CLKSOURCE_D2PCLK1     RCC_SPI45CLKSOURCE_D2PCLK1
+#define RCC_SPI4CLKSOURCE_PLL2        RCC_SPI45CLKSOURCE_PLL2
+#define RCC_SPI4CLKSOURCE_PLL3        RCC_SPI45CLKSOURCE_PLL3
+#define RCC_SPI4CLKSOURCE_HSI         RCC_SPI45CLKSOURCE_HSI
+#define RCC_SPI4CLKSOURCE_CSI         RCC_SPI45CLKSOURCE_CSI
+#define RCC_SPI4CLKSOURCE_HSE         RCC_SPI45CLKSOURCE_HSE
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SPI5_Clock_Source SPI5 Clock Source
+  * @{
+  */
+#define RCC_SPI5CLKSOURCE_D2PCLK1     RCC_SPI45CLKSOURCE_D2PCLK1
+#define RCC_SPI5CLKSOURCE_PLL2        RCC_SPI45CLKSOURCE_PLL2
+#define RCC_SPI5CLKSOURCE_PLL3        RCC_SPI45CLKSOURCE_PLL3
+#define RCC_SPI5CLKSOURCE_HSI         RCC_SPI45CLKSOURCE_HSI
+#define RCC_SPI5CLKSOURCE_CSI         RCC_SPI45CLKSOURCE_CSI
+#define RCC_SPI5CLKSOURCE_HSE         RCC_SPI45CLKSOURCE_HSE
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SPI6_Clock_Source SPI6 Clock Source
+  * @{
+  */
+#if defined(RCC_D3CCIPR_SPI6SEL)
+#define RCC_SPI6CLKSOURCE_D3PCLK1     (0x00000000U)
+#define RCC_SPI6CLKSOURCE_PCLK4        RCC_SPI6CLKSOURCE_D3PCLK1
+#define RCC_SPI6CLKSOURCE_PLL2         RCC_D3CCIPR_SPI6SEL_0
+#define RCC_SPI6CLKSOURCE_PLL3         RCC_D3CCIPR_SPI6SEL_1
+#define RCC_SPI6CLKSOURCE_HSI         (RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_1)
+#define RCC_SPI6CLKSOURCE_CSI          RCC_D3CCIPR_SPI6SEL_2
+#define RCC_SPI6CLKSOURCE_HSE         (RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_2)
+#else
+#define RCC_SPI6CLKSOURCE_SRDPCLK4    (0x00000000U)
+/* alias */
+#define RCC_SPI6CLKSOURCE_D3PCLK1      RCC_SPI6CLKSOURCE_SRDPCLK4  /* D3PCLK1 is used in STM32H74xxx, STM32H75xxx, STM32H72xxx and STM32H73xxx family lines */
+#define RCC_SPI6CLKSOURCE_PCLK4        RCC_SPI6CLKSOURCE_SRDPCLK4
+#define RCC_SPI6CLKSOURCE_PLL2         RCC_SRDCCIPR_SPI6SEL_0
+#define RCC_SPI6CLKSOURCE_PLL3         RCC_SRDCCIPR_SPI6SEL_1
+#define RCC_SPI6CLKSOURCE_HSI         (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_1)
+#define RCC_SPI6CLKSOURCE_CSI          RCC_SRDCCIPR_SPI6SEL_2
+#define RCC_SPI6CLKSOURCE_HSE         (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_2)
+#define RCC_SPI6CLKSOURCE_PIN         (RCC_SRDCCIPR_SPI6SEL_1 | RCC_SRDCCIPR_SPI6SEL_2)
+#endif /* RCC_D3CCIPR_SPI6SEL */
+
+/**
+  * @}
+  */
+
+
+#if defined(SAI4_Block_A)
+/** @defgroup RCCEx_SAI4A_Clock_Source SAI4A Clock Source
+  * @{
+  */
+#define RCC_SAI4ACLKSOURCE_PLL         (0x00000000U)
+#define RCC_SAI4ACLKSOURCE_PLL2         RCC_D3CCIPR_SAI4ASEL_0
+#define RCC_SAI4ACLKSOURCE_PLL3         RCC_D3CCIPR_SAI4ASEL_1
+#define RCC_SAI4ACLKSOURCE_PIN         (RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1)
+#define RCC_SAI4ACLKSOURCE_CLKP         RCC_D3CCIPR_SAI4ASEL_2
+
+/**
+  * @}
+  */
+#endif /* SAI4_Block_A */
+
+
+
+#if defined(SAI4_Block_B)
+/** @defgroup RCCEx_SAI4B_Clock_Source SAI4B Clock Source
+  * @{
+  */
+#define RCC_SAI4BCLKSOURCE_PLL         (0x00000000U)
+#define RCC_SAI4BCLKSOURCE_PLL2         RCC_D3CCIPR_SAI4BSEL_0
+#define RCC_SAI4BCLKSOURCE_PLL3         RCC_D3CCIPR_SAI4BSEL_1
+#define RCC_SAI4BCLKSOURCE_PIN         (RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1)
+#define RCC_SAI4BCLKSOURCE_CLKP         RCC_D3CCIPR_SAI4BSEL_2
+
+/**
+  * @}
+  */
+#endif /* SAI4_Block_B */
+
+
+/** @defgroup RCCEx_LPTIM1_Clock_Source  RCCEx LPTIM1 Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP2R_LPTIM1SEL)
+#define RCC_LPTIM1CLKSOURCE_D2PCLK1        (0x00000000U)
+/* alias */
+#define RCC_LPTIM1CLKSOURCE_PCLK1         RCC_LPTIM1CLKSOURCE_D2PCLK1
+#define RCC_LPTIM1CLKSOURCE_PLL2          RCC_D2CCIP2R_LPTIM1SEL_0
+#define RCC_LPTIM1CLKSOURCE_PLL3          RCC_D2CCIP2R_LPTIM1SEL_1
+#define RCC_LPTIM1CLKSOURCE_LSE          (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_1)
+#define RCC_LPTIM1CLKSOURCE_LSI           RCC_D2CCIP2R_LPTIM1SEL_2
+#define RCC_LPTIM1CLKSOURCE_CLKP         (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_2)
+#else
+#define RCC_LPTIM1CLKSOURCE_CDPCLK1        (0x00000000U)
+/* alias */
+#define RCC_LPTIM1CLKSOURCE_PCLK1         RCC_LPTIM1CLKSOURCE_CDPCLK1
+#define RCC_LPTIM1CLKSOURCE_D2PCLK1       RCC_LPTIM1CLKSOURCE_CDPCLK1
+#define RCC_LPTIM1CLKSOURCE_PLL2          RCC_CDCCIP2R_LPTIM1SEL_0
+#define RCC_LPTIM1CLKSOURCE_PLL3          RCC_CDCCIP2R_LPTIM1SEL_1
+#define RCC_LPTIM1CLKSOURCE_LSE          (RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_1)
+#define RCC_LPTIM1CLKSOURCE_LSI           RCC_CDCCIP2R_LPTIM1SEL_2
+#define RCC_LPTIM1CLKSOURCE_CLKP         (RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_2)
+#endif /* RCC_D2CCIP2R_LPTIM1SEL */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_LPTIM2_Clock_Source  RCCEx LPTIM2 Clock Source
+  * @{
+  */
+#if defined(RCC_D3CCIPR_LPTIM2SEL)
+#define RCC_LPTIM2CLKSOURCE_D3PCLK1       (0x00000000U)
+/* alias */
+#define RCC_LPTIM2CLKSOURCE_PCLK4         RCC_LPTIM2CLKSOURCE_D3PCLK1
+#define RCC_LPTIM2CLKSOURCE_PLL2          RCC_D3CCIPR_LPTIM2SEL_0
+#define RCC_LPTIM2CLKSOURCE_PLL3          RCC_D3CCIPR_LPTIM2SEL_1
+#define RCC_LPTIM2CLKSOURCE_LSE          (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_1)
+#define RCC_LPTIM2CLKSOURCE_LSI           RCC_D3CCIPR_LPTIM2SEL_2
+#define RCC_LPTIM2CLKSOURCE_CLKP         (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_2)
+#else
+#define RCC_LPTIM2CLKSOURCE_SRDPCLK4       (0x00000000U)
+/*alias*/
+#define RCC_LPTIM2CLKSOURCE_PCLK4         RCC_LPTIM2CLKSOURCE_SRDPCLK4
+#define RCC_LPTIM2CLKSOURCE_D3PCLK1       RCC_LPTIM2CLKSOURCE_SRDPCLK4
+#define RCC_LPTIM2CLKSOURCE_PLL2          RCC_SRDCCIPR_LPTIM2SEL_0
+#define RCC_LPTIM2CLKSOURCE_PLL3          RCC_SRDCCIPR_LPTIM2SEL_1
+#define RCC_LPTIM2CLKSOURCE_LSE          (RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_1)
+#define RCC_LPTIM2CLKSOURCE_LSI           RCC_SRDCCIPR_LPTIM2SEL_2
+#define RCC_LPTIM2CLKSOURCE_CLKP         (RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_2)
+#endif /* RCC_D3CCIPR_LPTIM2SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_LPTIM345_Clock_Source  RCCEx LPTIM3/4/5 Clock Source
+  * @{
+  */
+#if defined(RCC_D3CCIPR_LPTIM345SEL)
+#define RCC_LPTIM345CLKSOURCE_D3PCLK1        (0x00000000U)
+/* alias*/
+#define RCC_LPTIM345CLKSOURCE_PCLK4         RCC_LPTIM345CLKSOURCE_D3PCLK1
+#define RCC_LPTIM345CLKSOURCE_PLL2          RCC_D3CCIPR_LPTIM345SEL_0
+#define RCC_LPTIM345CLKSOURCE_PLL3          RCC_D3CCIPR_LPTIM345SEL_1
+#define RCC_LPTIM345CLKSOURCE_LSE          (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1)
+#define RCC_LPTIM345CLKSOURCE_LSI           RCC_D3CCIPR_LPTIM345SEL_2
+#define RCC_LPTIM345CLKSOURCE_CLKP         (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2)
+#else
+#define RCC_LPTIM345CLKSOURCE_SRDPCLK4      (0x00000000U)
+/* alias */
+#define RCC_LPTIM345CLKSOURCE_PCLK4         RCC_LPTIM345CLKSOURCE_SRDPCLK4
+#define RCC_LPTIM345CLKSOURCE_D3PCLK1       RCC_LPTIM345CLKSOURCE_SRDPCLK4
+#define RCC_LPTIM345CLKSOURCE_PLL2          RCC_SRDCCIPR_LPTIM3SEL_0
+#define RCC_LPTIM345CLKSOURCE_PLL3          RCC_SRDCCIPR_LPTIM3SEL_1
+#define RCC_LPTIM345CLKSOURCE_LSE          (RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_1)
+#define RCC_LPTIM345CLKSOURCE_LSI           RCC_SRDCCIPR_LPTIM3SEL_2
+#define RCC_LPTIM345CLKSOURCE_CLKP         (RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_2)
+#endif /* RCC_D3CCIPR_LPTIM345SEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_LPTIM3_Clock_Source  RCCEx LPTIM3 Clock Source
+  * @{
+  */
+#define RCC_LPTIM3CLKSOURCE_D3PCLK1       RCC_LPTIM345CLKSOURCE_D3PCLK1
+#define RCC_LPTIM3CLKSOURCE_PLL2          RCC_LPTIM345CLKSOURCE_PLL2
+#define RCC_LPTIM3CLKSOURCE_PLL3          RCC_LPTIM345CLKSOURCE_PLL3
+#define RCC_LPTIM3CLKSOURCE_LSE           RCC_LPTIM345CLKSOURCE_LSE
+#define RCC_LPTIM3CLKSOURCE_LSI           RCC_LPTIM345CLKSOURCE_LSI
+#define RCC_LPTIM3CLKSOURCE_CLKP          RCC_LPTIM345CLKSOURCE_CLKP
+
+/**
+  * @}
+  */
+#if defined(LPTIM4)
+/** @defgroup RCCEx_LPTIM4_Clock_Source  RCCEx LPTIM4 Clock Source
+  * @{
+  */
+#define RCC_LPTIM4CLKSOURCE_D3PCLK1       RCC_LPTIM345CLKSOURCE_D3PCLK1
+#define RCC_LPTIM4CLKSOURCE_PLL2          RCC_LPTIM345CLKSOURCE_PLL2
+#define RCC_LPTIM4CLKSOURCE_PLL3          RCC_LPTIM345CLKSOURCE_PLL3
+#define RCC_LPTIM4CLKSOURCE_LSE           RCC_LPTIM345CLKSOURCE_LSE
+#define RCC_LPTIM4CLKSOURCE_LSI           RCC_LPTIM345CLKSOURCE_LSI
+#define RCC_LPTIM4CLKSOURCE_CLKP          RCC_LPTIM345CLKSOURCE_CLKP
+/**
+  * @}
+  */
+#endif /* LPTIM4 */
+
+#if defined(LPTIM5)
+/** @defgroup RCCEx_LPTIM5_Clock_Source  RCCEx LPTIM5 Clock Source
+  * @{
+  */
+#define RCC_LPTIM5CLKSOURCE_D3PCLK1       RCC_LPTIM345CLKSOURCE_D3PCLK1
+#define RCC_LPTIM5CLKSOURCE_PLL2          RCC_LPTIM345CLKSOURCE_PLL2
+#define RCC_LPTIM5CLKSOURCE_PLL3          RCC_LPTIM345CLKSOURCE_PLL3
+#define RCC_LPTIM5CLKSOURCE_LSE           RCC_LPTIM345CLKSOURCE_LSE
+#define RCC_LPTIM5CLKSOURCE_LSI           RCC_LPTIM345CLKSOURCE_LSI
+#define RCC_LPTIM5CLKSOURCE_CLKP          RCC_LPTIM345CLKSOURCE_CLKP
+
+/**
+  * @}
+  */
+#endif /* LPTIM5 */
+
+#if defined(QUADSPI)
+/** @defgroup RCCEx_QSPI_Clock_Source  RCCEx QSPI Clock Source
+  * @{
+  */
+#define RCC_QSPICLKSOURCE_D1HCLK       (0x00000000U)
+#define RCC_QSPICLKSOURCE_PLL          RCC_D1CCIPR_QSPISEL_0
+#define RCC_QSPICLKSOURCE_PLL2         RCC_D1CCIPR_QSPISEL_1
+#define RCC_QSPICLKSOURCE_CLKP         RCC_D1CCIPR_QSPISEL
+
+/**
+  * @}
+  */
+#endif /* QUADSPI */
+
+
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+/** @defgroup RCCEx_OSPI_Clock_Source  RCCEx OSPI Clock Source
+  * @{
+  */
+#define RCC_OSPICLKSOURCE_CDHCLK       (0x00000000U)
+/*aliases*/
+#define RCC_OSPICLKSOURCE_D1HCLK       RCC_OSPICLKSOURCE_CDHCLK
+#define RCC_OSPICLKSOURCE_HCLK         RCC_OSPICLKSOURCE_CDHCLK
+#define RCC_OSPICLKSOURCE_PLL          RCC_CDCCIPR_OCTOSPISEL_0
+#define RCC_OSPICLKSOURCE_PLL2         RCC_CDCCIPR_OCTOSPISEL_1
+#define RCC_OSPICLKSOURCE_CLKP         RCC_CDCCIPR_OCTOSPISEL
+
+/**
+  * @}
+  */
+#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
+
+#if defined(DSI)
+/** @defgroup RCCEx_DSI_Clock_Source  RCCEx DSI Clock Source
+  * @{
+  */
+#define RCC_DSICLKSOURCE_PHY       (0x00000000U)
+#define RCC_DSICLKSOURCE_PLL2       RCC_D1CCIPR_DSISEL
+
+/**
+  * @}
+  */
+#endif /* DSI */
+
+/** @defgroup RCCEx_FMC_Clock_Source  RCCEx FMC Clock Source
+  * @{
+  */
+#if defined(RCC_D1CCIPR_FMCSEL)
+#define RCC_FMCCLKSOURCE_D1HCLK       (0x00000000U)
+#define RCC_FMCCLKSOURCE_HCLK         RCC_FMCCLKSOURCE_D1HCLK
+#define RCC_FMCCLKSOURCE_PLL          RCC_D1CCIPR_FMCSEL_0
+#define RCC_FMCCLKSOURCE_PLL2         RCC_D1CCIPR_FMCSEL_1
+#define RCC_FMCCLKSOURCE_CLKP         RCC_D1CCIPR_FMCSEL
+#else
+#define RCC_FMCCLKSOURCE_CDHCLK       (0x00000000U)
+#define RCC_FMCCLKSOURCE_HCLK         RCC_FMCCLKSOURCE_CDHCLK
+/*alias*/
+#define RCC_FMCCLKSOURCE_D1HCLK       RCC_FMCCLKSOURCE_CDHCLK
+#define RCC_FMCCLKSOURCE_PLL          RCC_CDCCIPR_FMCSEL_0
+#define RCC_FMCCLKSOURCE_PLL2         RCC_CDCCIPR_FMCSEL_1
+#define RCC_FMCCLKSOURCE_CLKP         RCC_CDCCIPR_FMCSEL
+#endif /* RCC_D1CCIPR_FMCSEL */
+/**
+  * @}
+  */
+
+#if defined(FDCAN1) || defined(FDCAN2)
+/** @defgroup RCCEx_FDCAN_Clock_Source  RCCEx FDCAN Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_FDCANSEL)
+#define RCC_FDCANCLKSOURCE_HSE         (0x00000000U)
+#define RCC_FDCANCLKSOURCE_PLL          RCC_D2CCIP1R_FDCANSEL_0
+#define RCC_FDCANCLKSOURCE_PLL2         RCC_D2CCIP1R_FDCANSEL_1
+#else
+#define RCC_FDCANCLKSOURCE_HSE         (0x00000000U)
+#define RCC_FDCANCLKSOURCE_PLL          RCC_CDCCIP1R_FDCANSEL_0
+#define RCC_FDCANCLKSOURCE_PLL2         RCC_CDCCIP1R_FDCANSEL_1
+#endif /* D3_SRAM_BASE */
+/**
+  * @}
+  */
+#endif /*FDCAN1 || FDCAN2*/
+
+
+/** @defgroup RCCEx_SDMMC_Clock_Source  RCCEx SDMMC Clock Source
+  * @{
+  */
+#if defined(RCC_D1CCIPR_SDMMCSEL)
+#define RCC_SDMMCCLKSOURCE_PLL           (0x00000000U)
+#define RCC_SDMMCCLKSOURCE_PLL2           RCC_D1CCIPR_SDMMCSEL
+#else
+#define RCC_SDMMCCLKSOURCE_PLL           (0x00000000U)
+#define RCC_SDMMCCLKSOURCE_PLL2           RCC_CDCCIPR_SDMMCSEL
+#endif /* RCC_D1CCIPR_SDMMCSEL */
+/**
+  * @}
+  */
+
+
+/** @defgroup RCCEx_ADC_Clock_Source  RCCEx ADC Clock Source
+  * @{
+  */
+#if defined(RCC_D3CCIPR_ADCSEL_0)
+#define RCC_ADCCLKSOURCE_PLL2       (0x00000000U)
+#define RCC_ADCCLKSOURCE_PLL3       RCC_D3CCIPR_ADCSEL_0
+#define RCC_ADCCLKSOURCE_CLKP       RCC_D3CCIPR_ADCSEL_1
+#else
+#define RCC_ADCCLKSOURCE_PLL2       (0x00000000U)
+#define RCC_ADCCLKSOURCE_PLL3       RCC_SRDCCIPR_ADCSEL_0
+#define RCC_ADCCLKSOURCE_CLKP       RCC_SRDCCIPR_ADCSEL_1
+#endif /* RCC_D3CCIPR_ADCSEL_0  */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SWPMI1_Clock_Source  RCCEx SWPMI1 Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_SWPSEL)
+#define RCC_SWPMI1CLKSOURCE_D2PCLK1       (0x00000000U)
+#define RCC_SWPMI1CLKSOURCE_HSI            RCC_D2CCIP1R_SWPSEL
+#else
+#define RCC_SWPMI1CLKSOURCE_CDPCLK1       (0x00000000U)
+/* alias */
+#define RCC_SWPMI1CLKSOURCE_D2PCLK1        RCC_SWPMI1CLKSOURCE_CDPCLK1
+#define RCC_SWPMI1CLKSOURCE_HSI            RCC_CDCCIP1R_SWPSEL
+#endif /* RCC_D2CCIP1R_SWPSEL */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_DFSDM1_Clock_Source  RCCEx DFSDM1 Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_DFSDM1SEL)
+#define RCC_DFSDM1CLKSOURCE_D2PCLK1        (0x00000000U)
+#define RCC_DFSDM1CLKSOURCE_SYS            RCC_D2CCIP1R_DFSDM1SEL
+#else
+#define RCC_DFSDM1CLKSOURCE_CDPCLK1        (0x00000000U)
+/* alias */
+#define RCC_DFSDM1CLKSOURCE_D2PCLK1        RCC_DFSDM1CLKSOURCE_CDPCLK1
+#define RCC_DFSDM1CLKSOURCE_SYS            RCC_CDCCIP1R_DFSDM1SEL
+#endif /* RCC_D2CCIP1R_DFSDM1SEL */
+/**
+  * @}
+  */
+
+#if defined(DFSDM2_BASE)
+/** @defgroup RCCEx_DFSDM2_Clock_Source  RCCEx DFSDM2 Clock Source
+  * @{
+  */
+#define RCC_DFSDM2CLKSOURCE_SRDPCLK4       (0x00000000U)
+/* alias */
+#define RCC_DFSDM2CLKSOURCE_SRDPCLK1       RCC_DFSDM2CLKSOURCE_SRDPCLK4
+#define RCC_DFSDM2CLKSOURCE_SYS            RCC_SRDCCIPR_DFSDM2SEL
+/**
+  * @}
+  */
+#endif /* DFSDM2 */
+
+/** @defgroup RCCEx_SPDIFRX_Clock_Source  RCCEx SPDIFRX Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP1R_SPDIFSEL_0)
+#define RCC_SPDIFRXCLKSOURCE_PLL        (0x00000000U)
+#define RCC_SPDIFRXCLKSOURCE_PLL2       RCC_D2CCIP1R_SPDIFSEL_0
+#define RCC_SPDIFRXCLKSOURCE_PLL3       RCC_D2CCIP1R_SPDIFSEL_1
+#define RCC_SPDIFRXCLKSOURCE_HSI        RCC_D2CCIP1R_SPDIFSEL
+#else
+#define RCC_SPDIFRXCLKSOURCE_PLL        (0x00000000U)
+#define RCC_SPDIFRXCLKSOURCE_PLL2       RCC_CDCCIP1R_SPDIFSEL_0
+#define RCC_SPDIFRXCLKSOURCE_PLL3       RCC_CDCCIP1R_SPDIFSEL_1
+#define RCC_SPDIFRXCLKSOURCE_HSI        RCC_CDCCIP1R_SPDIFSEL
+#endif /* RCC_D2CCIP1R_SPDIFSEL_0 */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CEC_Clock_Source  RCCEx CEC Clock Source
+  * @{
+  */
+#if defined(RCC_D2CCIP2R_CECSEL_0)
+#define RCC_CECCLKSOURCE_LSE        (0x00000000U)
+#define RCC_CECCLKSOURCE_LSI         RCC_D2CCIP2R_CECSEL_0
+#define RCC_CECCLKSOURCE_CSI         RCC_D2CCIP2R_CECSEL_1
+#else
+#define RCC_CECCLKSOURCE_LSE        (0x00000000U)
+#define RCC_CECCLKSOURCE_LSI         RCC_CDCCIP2R_CECSEL_0
+#define RCC_CECCLKSOURCE_CSI         RCC_CDCCIP2R_CECSEL_1
+#endif /* RCC_D2CCIP2R_CECSEL_0 */
+/**
+  * @}
+  */
+
+
+/** @defgroup RCCEx_CLKP_Clock_Source  RCCEx CLKP Clock Source
+  * @{
+  */
+#if defined(RCC_D1CCIPR_CKPERSEL_0)
+#define RCC_CLKPSOURCE_HSI        (0x00000000U)
+#define RCC_CLKPSOURCE_CSI         RCC_D1CCIPR_CKPERSEL_0
+#define RCC_CLKPSOURCE_HSE         RCC_D1CCIPR_CKPERSEL_1
+#else
+#define RCC_CLKPSOURCE_HSI        (0x00000000U)
+#define RCC_CLKPSOURCE_CSI         RCC_CDCCIPR_CKPERSEL_0
+#define RCC_CLKPSOURCE_HSE         RCC_CDCCIPR_CKPERSEL_1
+#endif /* RCC_D1CCIPR_CKPERSEL_0 */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection
+  * @{
+  */
+#define RCC_TIMPRES_DESACTIVATED        (0x00000000U)
+#define RCC_TIMPRES_ACTIVATED            RCC_CFGR_TIMPRE
+
+/**
+  * @}
+  */
+
+#if defined(DUAL_CORE)
+
+/** @defgroup RCCEx_RCC_BootCx RCCEx RCC BootCx
+  * @{
+  */
+#define RCC_BOOT_C1        RCC_GCR_BOOT_C1
+#define RCC_BOOT_C2        RCC_GCR_BOOT_C2
+
+/**
+  * @}
+  */
+#endif /*DUAL_CORE*/
+
+#if defined(DUAL_CORE)
+/** @defgroup RCCEx_RCC_WWDGx  RCCEx RCC WWDGx
+  * @{
+  */
+#define RCC_WWDG1        RCC_GCR_WW1RSC
+#define RCC_WWDG2        RCC_GCR_WW2RSC
+
+/**
+  * @}
+  */
+
+#else
+
+/** @defgroup RCCEx_RCC_WWDGx  RCCEx RCC WWDGx
+  * @{
+  */
+#define RCC_WWDG1        RCC_GCR_WW1RSC
+
+/**
+  * @}
+  */
+
+#endif /*DUAL_CORE*/
+
+/** @defgroup RCCEx_EXTI_LINE_LSECSS  RCC LSE CSS external interrupt line
+  * @{
+  */
+#define RCC_EXTI_LINE_LSECSS           EXTI_IMR1_IM18        /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_Status RCCEx CRS Status
+  * @{
+  */
+#define RCC_CRS_NONE                   (0x00000000U)
+#define RCC_CRS_TIMEOUT                (0x00000001U)
+#define RCC_CRS_SYNCOK                 (0x00000002U)
+#define RCC_CRS_SYNCWARN               (0x00000004U)
+#define RCC_CRS_SYNCERR                (0x00000008U)
+#define RCC_CRS_SYNCMISS               (0x00000010U)
+#define RCC_CRS_TRIMOVF                (0x00000020U)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
+  * @{
+  */
+#define RCC_CRS_SYNC_SOURCE_PIN       (0x00000000U)                            /*!< Synchro Signal source external pin, Available on STM32H7 Rev.B and above devices only */
+#define RCC_CRS_SYNC_SOURCE_LSE        CRS_CFGR_SYNCSRC_0                      /*!< Synchro Signal source LSE */
+#define RCC_CRS_SYNC_SOURCE_USB1       CRS_CFGR_SYNCSRC_1                      /*!< Synchro Signal source USB1 SOF (default) */
+#define RCC_CRS_SYNC_SOURCE_USB2      (CRS_CFGR_SYNCSRC_1|CRS_CFGR_SYNCSRC_0)  /*!< Synchro Signal source USB2 SOF */
+
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider
+  * @{
+  */
+#define RCC_CRS_SYNC_DIV1        (0x00000000U)           /*!< Synchro Signal not divided (default) */
+#define RCC_CRS_SYNC_DIV2        CRS_CFGR_SYNCDIV_0                         /*!< Synchro Signal divided by 2 */
+#define RCC_CRS_SYNC_DIV4        CRS_CFGR_SYNCDIV_1                         /*!< Synchro Signal divided by 4 */
+#define RCC_CRS_SYNC_DIV8        (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0)  /*!< Synchro Signal divided by 8 */
+#define RCC_CRS_SYNC_DIV16       CRS_CFGR_SYNCDIV_2                        /*!< Synchro Signal divided by 16 */
+#define RCC_CRS_SYNC_DIV32       (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
+#define RCC_CRS_SYNC_DIV64       (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
+#define RCC_CRS_SYNC_DIV128      CRS_CFGR_SYNCDIV                         /*!< Synchro Signal divided by 128 */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity
+  * @{
+  */
+#define RCC_CRS_SYNC_POLARITY_RISING   (0x00000000U) /*!< Synchro Active on rising edge (default) */
+#define RCC_CRS_SYNC_POLARITY_FALLING  CRS_CFGR_SYNCPOL        /*!< Synchro Active on falling edge */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault
+  * @{
+  */
+#define RCC_CRS_RELOADVALUE_DEFAULT    (0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds
+                                                                    to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault
+  * @{
+  */
+#define RCC_CRS_ERRORLIMIT_DEFAULT     (0x00000022U) /*!< Default Frequency error limit */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault
+  * @{
+  */
+#define RCC_CRS_HSI48CALIBRATION_DEFAULT (0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
+                                                                      The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
+                                                                      corresponds to a higher output frequency */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection
+  * @{
+  */
+#define RCC_CRS_FREQERRORDIR_UP        (0x00000000U)   /*!< Upcounting direction, the actual frequency is above the target */
+#define RCC_CRS_FREQERRORDIR_DOWN      (CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
+  * @{
+  */
+#define RCC_CRS_IT_SYNCOK              CRS_CR_SYNCOKIE       /*!< SYNC event OK */
+#define RCC_CRS_IT_SYNCWARN            CRS_CR_SYNCWARNIE     /*!< SYNC warning */
+#define RCC_CRS_IT_ERR                 CRS_CR_ERRIE          /*!< Error */
+#define RCC_CRS_IT_ESYNC               CRS_CR_ESYNCIE        /*!< Expected SYNC */
+#define RCC_CRS_IT_SYNCERR             CRS_CR_ERRIE          /*!< SYNC error */
+#define RCC_CRS_IT_SYNCMISS            CRS_CR_ERRIE          /*!< SYNC missed */
+#define RCC_CRS_IT_TRIMOVF             CRS_CR_ERRIE          /*!< Trimming overflow or underflow */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
+  * @{
+  */
+#define RCC_CRS_FLAG_SYNCOK            CRS_ISR_SYNCOKF       /*!< SYNC event OK flag     */
+#define RCC_CRS_FLAG_SYNCWARN          CRS_ISR_SYNCWARNF     /*!< SYNC warning flag      */
+#define RCC_CRS_FLAG_ERR               CRS_ISR_ERRF          /*!< Error flag        */
+#define RCC_CRS_FLAG_ESYNC             CRS_ISR_ESYNCF        /*!< Expected SYNC flag     */
+#define RCC_CRS_FLAG_SYNCERR           CRS_ISR_SYNCERR       /*!< SYNC error */
+#define RCC_CRS_FLAG_SYNCMISS          CRS_ISR_SYNCMISS      /*!< SYNC missed*/
+#define RCC_CRS_FLAG_TRIMOVF           CRS_ISR_TRIMOVF       /*!< Trimming overflow or underflow */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
+  * @{
+  */
+
+/** @brief  Macros to enable or disable PLL2.
+  * @note   After enabling PLL2, the application software should wait on
+  *         PLL2RDY flag to be set indicating that PLL2 clock is stable and can
+  *         be used as kernel clock source.
+  * @note   PLL2 is disabled by hardware when entering STOP and STANDBY modes.
+  */
+#define __HAL_RCC_PLL2_ENABLE()         SET_BIT(RCC->CR, RCC_CR_PLL2ON)
+#define __HAL_RCC_PLL2_DISABLE()        CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON)
+
+/**
+  * @brief  Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK)
+  * @note   Enabling/disabling  those Clocks can be done only when the PLL2 is disabled,
+  *         This is mainly used to save Power.
+  * @param  __RCC_PLL2ClockOut__ Specifies the PLL2 clock to be outputted
+  *          This parameter can be one of the following values:
+  *            @arg RCC_PLL2_DIVP: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
+  *            @arg RCC_PLL2_DIVQ: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
+  *            @arg RCC_PLL2_DIVR: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
+  *
+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  *
+  * @retval None
+  */
+#define __HAL_RCC_PLL2CLKOUT_ENABLE(__RCC_PLL2ClockOut__)   SET_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))
+
+#define __HAL_RCC_PLL2CLKOUT_DISABLE(__RCC_PLL2ClockOut__)  CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))
+
+/**
+  * @brief  Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO
+  * @note   Enabling/disabling  Fractional Part can be any time  without the need to stop the PLL2
+  * @retval None
+  */
+#define __HAL_RCC_PLL2FRACN_ENABLE()   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)
+
+#define __HAL_RCC_PLL2FRACN_DISABLE()  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)
+
+/**
+  * @brief  Macro to configures the PLL2  multiplication and division factors.
+  * @note   This function must be used only when PLL2 is disabled.
+  *
+  * @param  __PLL2M__ specifies the division factor for PLL2 VCO input clock
+  *          This parameter must be a number between 1 and 63.
+  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
+  *         frequency ranges from 1 to 16 MHz.
+  *
+  * @param  __PLL2N__ specifies the multiplication factor for PLL2 VCO output clock
+  *          This parameter must be a number between 4 and 512 or between 8 and 420(*).
+  * @note   You have to set the PLL2N parameter correctly to ensure that the VCO
+  *         output frequency is between 150 and 420 MHz (when in medium VCO range) or
+  *         between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range)
+  *
+  * @param  __PLL2P__ specifies the division factor for peripheral kernel clocks
+  *          This parameter must be a number between 1 and 128.
+  *
+  * @param  __PLL2Q__ specifies the division factor for peripheral kernel clocks
+  *          This parameter must be a number between 1 and 128.
+  *
+  * @param  __PLL2R__ specifies the division factor for peripheral kernel clocks
+  *          This parameter must be a number between 1 and 128.
+  *
+  * @note   To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR)
+  *         is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible
+  *         value to  __PLL2P__, __PLL2Q__ or __PLL2R__ parameters.
+  * @retval None
+  *
+  *  (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  */
+
+#define __HAL_RCC_PLL2_CONFIG(__PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__,__PLL2R__ ) \
+                  do{ \
+                       MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM2) , ( (__PLL2M__) <<12U));  \
+                       WRITE_REG (RCC->PLL2DIVR , ( (((__PLL2N__) - 1U ) & RCC_PLL2DIVR_N2) | ((((__PLL2P__) -1U ) << 9U) & RCC_PLL2DIVR_P2) | \
+                       ((((__PLL2Q__) -1U) << 16U) & RCC_PLL2DIVR_Q2) | ((((__PLL2R__)- 1U) << 24U) & RCC_PLL2DIVR_R2))); \
+                    } while(0)
+
+/**
+  * @brief  Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor
+  *
+  * @note   These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO
+  *
+  * @param  __RCC_PLL2FRACN__ Specifies Fractional Part Of The Multiplication factor for PLL2 VCO
+  *                           It should be a value between 0 and 8191
+  * @note   Warning: the software has to set correctly these bits to insure that the VCO
+  *                  output frequency is between its valid frequency range, which is:
+  *                  192 to 836 MHz or 128 to 560 MHz(*) if PLL2VCOSEL = 0
+  *                  150 to 420 MHz if PLL2VCOSEL = 1.
+  *
+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  *
+  * @retval None
+  */
+#define  __HAL_RCC_PLL2FRACN_CONFIG(__RCC_PLL2FRACN__) \
+                 MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2,((uint32_t)(__RCC_PLL2FRACN__) << RCC_PLL2FRACR_FRACN2_Pos))
+
+/** @brief  Macro to select  the PLL2  reference frequency range.
+  * @param  __RCC_PLL2VCIRange__ specifies the PLL2 input frequency range
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PLL2VCIRANGE_0: Range frequency is between 1 and 2 MHz
+  *            @arg RCC_PLL2VCIRANGE_1: Range frequency is between 2 and 4 MHz
+  *            @arg RCC_PLL2VCIRANGE_2: Range frequency is between 4 and 8 MHz
+  *            @arg RCC_PLL2VCIRANGE_3: Range frequency is between 8 and 16 MHz
+  * @retval None
+  */
+#define __HAL_RCC_PLL2_VCIRANGE(__RCC_PLL2VCIRange__) \
+                  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, (__RCC_PLL2VCIRange__))
+
+
+/** @brief  Macro to select  the PLL2  reference frequency range.
+  * @param  __RCC_PLL2VCORange__ Specifies the PLL2 input frequency range
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PLL2VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*)
+  *            @arg RCC_PLL2VCOMEDIUM: Range frequency is between 150 and 420 MHz
+  *
+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  *
+  * @retval None
+  */
+#define __HAL_RCC_PLL2_VCORANGE(__RCC_PLL2VCORange__) \
+                  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, (__RCC_PLL2VCORange__))
+
+/** @brief  Macros to enable or disable the main PLL3.
+  * @note   After enabling  PLL3, the application software should wait on
+  *         PLL3RDY flag to be set indicating that PLL3 clock is stable and can
+  *         be used as kernel clock source.
+  * @note   PLL3 is disabled by hardware when entering STOP and STANDBY modes.
+  */
+#define __HAL_RCC_PLL3_ENABLE()         SET_BIT(RCC->CR, RCC_CR_PLL3ON)
+#define __HAL_RCC_PLL3_DISABLE()        CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON)
+
+/**
+  * @brief  Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO
+  * @note   Enabling/disabling  Fractional Part can be any time  without the need to stop the PLL3
+  * @retval None
+  */
+#define __HAL_RCC_PLL3FRACN_ENABLE()   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)
+
+#define __HAL_RCC_PLL3FRACN_DISABLE()  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)
+
+/**
+  * @brief  Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK)
+  * @note   Enabling/disabling  those Clocks can be done only when the PLL3 is disabled,
+  *         This is mainly used to save Power.
+  * @param  __RCC_PLL3ClockOut__ specifies the PLL3 clock to be outputted
+  *          This parameter can be one of the following values:
+  *            @arg RCC_PLL3_DIVP: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
+  *            @arg RCC_PLL3_DIVQ: This clock is used to generate peripherals clock  up to 400MHZ or 280MHZ(*)
+  *            @arg RCC_PLL3_DIVR: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)
+  *
+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  *
+  * @retval None
+  */
+#define __HAL_RCC_PLL3CLKOUT_ENABLE(__RCC_PLL3ClockOut__)   SET_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))
+
+#define __HAL_RCC_PLL3CLKOUT_DISABLE(__RCC_PLL3ClockOut__)  CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))
+
+/**
+  * @brief  Macro to configures the PLL3  multiplication and division factors.
+  * @note   This function must be used only when PLL3 is disabled.
+  *
+  * @param  __PLL3M__ specifies the division factor for PLL3 VCO input clock
+  *          This parameter must be a number between 1 and 63.
+  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
+  *         frequency ranges from 1 to 16 MHz.
+  *
+  * @param  __PLL3N__ specifies the multiplication factor for PLL3 VCO output clock
+  *          This parameter must be a number between 4 and 512.
+  * @note   You have to set the PLL3N parameter correctly to ensure that the VCO
+  *         output frequency is between 150 and 420 MHz (when in medium VCO range) or
+  *         between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range)
+  *
+  * @param  __PLL3P__ specifies the division factor for peripheral kernel clocks
+  *          This parameter must be a number between 2 and 128 (where odd numbers not allowed)
+  *
+  * @param  __PLL3Q__ specifies the division factor for peripheral kernel clocks
+  *          This parameter must be a number between 1 and 128
+  *
+  * @param  __PLL3R__ specifies the division factor for peripheral kernel clocks
+  *          This parameter must be a number between 1 and 128
+  *
+  * @note   To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR)
+  *         is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible
+  *         value to  __PLL3P__, __PLL3Q__ or __PLL3R__ parameters.
+  * @retval None
+  *
+  *  (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  */
+
+#define __HAL_RCC_PLL3_CONFIG(__PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__,__PLL3R__ ) \
+                  do{ MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM3) , ( (__PLL3M__) <<20U));  \
+                         WRITE_REG (RCC->PLL3DIVR , ( (((__PLL3N__) - 1U ) & RCC_PLL3DIVR_N3) | ((((__PLL3P__) -1U ) << 9U) & RCC_PLL3DIVR_P3) | \
+                                   ((((__PLL3Q__) -1U) << 16U) & RCC_PLL3DIVR_Q3) | ((((__PLL3R__) - 1U) << 24U) & RCC_PLL3DIVR_R3))); \
+                       } while(0)
+
+
+
+/**
+  * @brief  Macro to configures  PLL3 clock Fractional Part of The Multiplication Factor
+  *
+  * @note   These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO
+  *
+  * @param  __RCC_PLL3FRACN__ specifies Fractional Part Of The Multiplication Factor for PLL3 VCO
+  *                            It should be a value between 0 and 8191
+  * @note   Warning: the software has to set correctly these bits to insure that the VCO
+  *                  output frequency is between its valid frequency range, which is:
+  *                  192 to 836 MHz or 128 to 560 MHz(*) if PLL3VCOSEL = 0
+  *                  150 to 420 MHz if PLL3VCOSEL = 1.
+  *
+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  *
+  * @retval None
+  */
+ #define  __HAL_RCC_PLL3FRACN_CONFIG(__RCC_PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << RCC_PLL3FRACR_FRACN3_Pos)
+
+/** @brief  Macro to select  the PLL3  reference frequency range.
+  * @param  __RCC_PLL3VCIRange__ specifies the PLL1 input frequency range
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PLL3VCIRANGE_0: Range frequency is between 1 and 2 MHz
+  *            @arg RCC_PLL3VCIRANGE_1: Range frequency is between 2 and 4 MHz
+  *            @arg RCC_PLL3VCIRANGE_2: Range frequency is between 4 and 8 MHz
+  *            @arg RCC_PLL3VCIRANGE_3: Range frequency is between 8 and 16 MHz
+  * @retval None
+  */
+#define __HAL_RCC_PLL3_VCIRANGE(__RCC_PLL3VCIRange__) \
+                  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, (__RCC_PLL3VCIRange__))
+
+
+/** @brief  Macro to select  the PLL3  reference frequency range.
+  * @param  __RCC_PLL3VCORange__ specifies the PLL1 input frequency range
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PLL3VCOWIDE: Range frequency is between 192 and 836 MHz  or between 128 to 560 MHz(*)
+  *            @arg RCC_PLL3VCOMEDIUM: Range frequency is between 150 and 420 MHz
+  *
+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
+  *
+  * @retval None
+  */
+#define __HAL_RCC_PLL3_VCORANGE(__RCC_PLL3VCORange__) \
+                  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__))
+/**
+  * @brief  Macro to Configure the SAI1 clock source.
+  * @param  __RCC_SAI1CLKSource__ defines the SAI1 clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL
+  *             @arg RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2
+  *             @arg RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3
+  *             @arg RCC_SAI1CLKSOURCE_OSC: SAI1 clock  = OSC
+  *             @arg RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock
+  * @retval None
+  */
+#if defined(RCC_D2CCIP1R_SAI1SEL)
+#define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__ )\
+                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__))
+#else
+#define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__ )\
+                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__))
+#endif /* RCC_D2CCIP1R_SAI1SEL */
+
+/** @brief  Macro to get the SAI1 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL
+  *             @arg RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2
+  *             @arg RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3
+  *             @arg RCC_SAI1CLKSOURCE_CLKP: SAI1 clock  = CLKP
+  *             @arg RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock
+  */
+#if defined(RCC_D2CCIP1R_SAI1SEL)
+#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL)))
+#else
+#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL)))
+#endif /* RCC_D2CCIP1R_SAI1SEL */
+
+/**
+  * @brief  Macro to Configure the SPDIFRX clock source.
+  * @param  __RCC_SPDIFCLKSource__ defines the SPDIFRX clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3,  or internal OSC clock
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SPDIFRXCLKSOURCE_PLL:  SPDIFRX clock = PLL
+  *             @arg RCC_SPDIFRXCLKSOURCE_PLL2: SPDIFRX clock = PLL2
+  *             @arg RCC_SPDIFRXCLKSOURCE_PLL3: SPDIFRX clock = PLL3
+  *             @arg RCC_SPDIFRXCLKSOURCE_HSI:  SPDIFRX clock  = HSI
+  * @retval None
+  */
+#if defined(RCC_D2CCIP1R_SPDIFSEL)
+#define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__ )\
+                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__))
+#else
+#define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__ )\
+                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__))
+#endif /* RCC_D2CCIP1R_SPDIFSEL */
+
+/**
+  * @brief  Macro to get the SPDIFRX clock source.
+  * @retval None
+  */
+#if defined(RCC_D2CCIP1R_SPDIFSEL)
+#define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL)))
+#else
+#define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL)))
+#endif /* RCC_D2CCIP1R_SPDIFSEL */
+
+#if defined(SAI3)
+/**
+  * @brief  Macro to Configure the SAI2/3 clock source.
+  * @param  __RCC_SAI23CLKSource__ defines the SAI2/3 clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SAI23CLKSOURCE_PLL: SAI2/3 clock = PLL
+  *             @arg RCC_SAI23CLKSOURCE_PLL2: SAI2/3 clock = PLL2
+  *             @arg RCC_SAI23CLKSOURCE_PLL3: SAI2/3 clock = PLL3
+  *             @arg RCC_SAI23CLKSOURCE_CLKP: SAI2/3 clock  = CLKP
+  *             @arg RCC_SAI23CLKSOURCE_PIN: SAI2/3 clock = External Clock
+  * @retval None
+  */
+#define __HAL_RCC_SAI23_CONFIG(__RCC_SAI23CLKSource__ )\
+                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL, (__RCC_SAI23CLKSource__))
+
+/** @brief  Macro to get the SAI2/3 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SAI23CLKSOURCE_PLL: SAI2/3 clock = PLL
+  *             @arg RCC_SAI23CLKSOURCE_PLL2: SAI2/3 clock = PLL2
+  *             @arg RCC_SAI23CLKSOURCE_PLL3: SAI2/3 clock = PLL3
+  *             @arg RCC_SAI23CLKSOURCE_CLKP: SAI2/3 clock  = CLKP
+  *             @arg RCC_SAI23CLKSOURCE_PIN: SAI2/3 clock = External Clock
+  */
+#define __HAL_RCC_GET_SAI23_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL)))
+
+/**
+  * @brief  Macro to Configure the SAI2 clock source.
+  * @param  __RCC_SAI2CLKSource__ defines the SAI2 clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SAI2CLKSOURCE_PLL: SAI2 clock = PLL
+  *             @arg RCC_SAI2CLKSOURCE_PLL2: SAI2 clock = PLL2
+  *             @arg RCC_SAI2CLKSOURCE_PLL3: SAI2 clock = PLL3
+  *             @arg RCC_SAI2CLKSOURCE_CLKP: SAI2 clock  = CLKP
+  *             @arg RCC_SAI2CLKSOURCE_PIN: SAI2 clock = External Clock
+  * @retval None
+  */
+#define __HAL_RCC_SAI2_CONFIG  __HAL_RCC_SAI23_CONFIG
+
+/** @brief  Macro to get the SAI2 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SAI2CLKSOURCE_PLL: SAI2 clock = PLL
+  *             @arg RCC_SAI2CLKSOURCE_PLL2: SAI2 clock = PLL2
+  *             @arg RCC_SAI2CLKSOURCE_PLL3: SAI2 clock = PLL3
+  *             @arg RCC_SAI2CLKSOURCE_CLKP: SAI2 clock  = CLKP
+  *             @arg RCC_SAI2CLKSOURCE_PIN: SAI2 clock = External Clock
+  */
+#define __HAL_RCC_GET_SAI2_SOURCE  __HAL_RCC_GET_SAI23_SOURCE
+
+/**
+  * @brief  Macro to Configure the SAI3 clock source.
+  * @param  __RCC_SAI3CLKSource__ defines the SAI3 clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SAI3CLKSOURCE_PLL: SAI3 clock = PLL
+  *             @arg RCC_SAI3CLKSOURCE_PLL2: SAI3 clock = PLL2
+  *             @arg RCC_SAI3CLKSOURCE_PLL3: SAI3 clock = PLL3
+  *             @arg RCC_SAI3CLKSOURCE_CLKP: SAI3 clock  = CLKP
+  *             @arg RCC_SAI3CLKSOURCE_PIN: SAI3 clock = External Clock
+  * @retval None
+  */
+#define __HAL_RCC_SAI3_CONFIG __HAL_RCC_SAI23_CONFIG
+
+/** @brief  Macro to get the SAI3 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SAI3CLKSOURCE_PLL: SAI3 clock = PLL
+  *             @arg RCC_SAI3CLKSOURCE_PLL2: SAI3 clock = PLL2
+  *             @arg RCC_SAI3CLKSOURCE_PLL3: SAI3 clock = PLL3
+  *             @arg RCC_SAI3CLKSOURCE_CLKP: SAI3 clock  = CLKP
+  *             @arg RCC_SAI3CLKSOURCE_PIN: SAI3 clock = External Clock
+  */
+#define __HAL_RCC_GET_SAI3_SOURCE  __HAL_RCC_GET_SAI23_SOURCE
+#endif /* SAI3 */
+
+#if defined(RCC_CDCCIP1R_SAI2ASEL)
+/**
+  * @brief  Macro to Configure the SAI2A clock source.
+  * @param  __RCC_SAI2ACLKSource__ defines the SAI2A clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SAI2ACLKSOURCE_PLL: SAI2A clock = PLL
+  *             @arg RCC_SAI2ACLKSOURCE_PLL2: SAI2A clock = PLL2
+  *             @arg RCC_SAI2ACLKSOURCE_PLL3: SAI2A clock = PLL3
+  *             @arg RCC_SAI2ACLKSOURCE_CLKP: SAI2A clock  = CLKP
+  *             @arg RCC_SAI2ACLKSOURCE_PIN: SAI2A clock = External Clock
+  *             @arg RCC_SAI2ACLKSOURCE_SPDIF: SAI2A clock = SPDIF Clock
+  * @retval None
+  */
+#define __HAL_RCC_SAI2A_CONFIG(__RCC_SAI2ACLKSource__ )\
+                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2ASEL, (__RCC_SAI2ACLKSource__))
+
+/** @brief  Macro to get the SAI2A clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SAI2CLKSOURCE_PLL: SAI2A clock = PLL
+  *             @arg RCC_SAI2CLKSOURCE_PLL2: SAI2A clock = PLL2
+  *             @arg RCC_SAI2CLKSOURCE_PLL3: SAI2A clock = PLL3
+  *             @arg RCC_SAI2CLKSOURCE_CLKP: SAI2A clock  = CLKP
+  *             @arg RCC_SAI2CLKSOURCE_PIN: SAI2A clock = External Clock
+  *             @arg RCC_SAI2ACLKSOURCE_SPDIF: SAI2A clock = SPDIF Clock
+  */
+#define __HAL_RCC_GET_SAI2A_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2ASEL)))
+#endif /* defined(RCC_CDCCIP1R_SAI2ASEL) */
+
+#if defined(RCC_CDCCIP1R_SAI2BSEL)
+/**
+  * @brief  Macro to Configure the SAI2B clock source.
+  * @param  __RCC_SAI2BCLKSource__ defines the SAI2B clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SAI2BCLKSOURCE_PLL: SAI2B clock = PLL
+  *             @arg RCC_SAI2BCLKSOURCE_PLL2: SAI2B clock = PLL2
+  *             @arg RCC_SAI2BCLKSOURCE_PLL3: SAI2B clock = PLL3
+  *             @arg RCC_SAI2BCLKSOURCE_CLKP: SAI2B clock  = CLKP
+  *             @arg RCC_SAI2BCLKSOURCE_PIN: SAI2B clock = External Clock
+  *             @arg RCC_SAI2BCLKSOURCE_SPDIF: SAI2B clock = SPDIF Clock
+  * @retval None
+  */
+#define __HAL_RCC_SAI2B_CONFIG(__RCC_SAI2BCLKSource__ )\
+                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2BSEL, (__RCC_SAI2BCLKSource__))
+
+/** @brief  Macro to get the SAI2B clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SAI2BCLKSOURCE_PLL: SAI2B clock = PLL
+  *             @arg RCC_SAI2BCLKSOURCE_PLL2: SAI2B clock = PLL2
+  *             @arg RCC_SAI2BCLKSOURCE_PLL3: SAI2B clock = PLL3
+  *             @arg RCC_SAI2BCLKSOURCE_CLKP: SAI2B clock  = CLKP
+  *             @arg RCC_SAI2BCLKSOURCE_PIN: SAI2B clock = External Clock
+  *             @arg RCC_SAI2BCLKSOURCE_SPDIF: SAI2B clock = SPDIF Clock
+  */
+#define __HAL_RCC_GET_SAI2B_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2BSEL)))
+#endif /* defined(RCC_CDCCIP1R_SAI2BSEL) */
+
+
+#if defined(SAI4_Block_A)
+/**
+  * @brief  Macro to Configure the SAI4A clock source.
+  * @param  __RCC_SAI4ACLKSource__ defines the SAI4A clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SAI4ACLKSOURCE_PLL: SAI4A clock = PLL
+  *             @arg RCC_SAI4ACLKSOURCE_PLL2: SAI4A clock = PLL2
+  *             @arg RCC_SAI4ACLKSOURCE_PLL3: SAI4A clock = PLL3
+  *             @arg RCC_SAI4ACLKSOURCE_CLKP: SAI4A clock  = CLKP
+  *             @arg RCC_SAI4ACLKSOURCE_PIN: SAI4A clock = External Clock
+  * @retval None
+  */
+#define __HAL_RCC_SAI4A_CONFIG(__RCC_SAI4ACLKSource__ )\
+                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL, (__RCC_SAI4ACLKSource__))
+
+/** @brief  Macro to get the SAI4A clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SAI4ACLKSOURCE_PLL: SAI4B clock = PLL
+  *             @arg RCC_SAI4ACLKSOURCE_PLL2: SAI4B clock = PLL2
+  *             @arg RCC_SAI4ACLKSOURCE_PLL3: SAI4B clock = PLL3
+  *             @arg RCC_SAI4ACLKSOURCE_CLKP: SAI4B clock  = CLKP
+  *             @arg RCC_SAI4ACLKSOURCE_PIN: SAI4B clock = External Clock
+  */
+#define __HAL_RCC_GET_SAI4A_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL)))
+#endif /* SAI4_Block_A */
+
+#if defined(SAI4_Block_B)
+/**
+  * @brief  Macro to Configure the SAI4B clock source.
+  * @param  __RCC_SAI4BCLKSource__ defines the SAI4B clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SAI4BCLKSOURCE_PLL: SAI4B clock = PLL
+  *             @arg RCC_SAI4BCLKSOURCE_PLL2: SAI4B clock = PLL2
+  *             @arg RCC_SAI4BCLKSOURCE_PLL3: SAI4B clock = PLL3
+  *             @arg RCC_SAI4BCLKSOURCE_CLKP: SAI4B clock  = CLKP
+  *             @arg RCC_SAI4BCLKSOURCE_PIN: SAI4B clock = External Clock
+  * @retval None
+  */
+#define __HAL_RCC_SAI4B_CONFIG(__RCC_SAI4BCLKSource__ )\
+                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL, (__RCC_SAI4BCLKSource__))
+
+/** @brief  Macro to get the SAI4B clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SAI4BCLKSOURCE_PLL: SAI4B clock = PLL
+  *             @arg RCC_SAI4BCLKSOURCE_PLL2: SAI4B clock = PLL2
+  *             @arg RCC_SAI4BCLKSOURCE_PLL3: SAI4B clock = PLL3
+  *             @arg RCC_SAI4BCLKSOURCE_CLKP: SAI4B clock  = CLKP
+  *             @arg RCC_SAI4BCLKSOURCE_PIN: SAI4B clock = External Clock
+  */
+#define __HAL_RCC_GET_SAI4B_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL)))
+#endif /* SAI4_Block_B */
+
+/** @brief macro to configure the I2C1/2/3 clock (I2C123CLK).
+  *
+  * @param  __I2C123CLKSource__ specifies the I2C1/2/3 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3 clock
+  *            @arg RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3 clock
+  *            @arg RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3 clock
+  *            @arg RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3 clock
+  */
+#if defined(RCC_D2CCIP2R_I2C123SEL)
+#define __HAL_RCC_I2C123_CONFIG(__I2C123CLKSource__) \
+                  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C123CLKSource__))
+#else
+#define __HAL_RCC_I2C123_CONFIG(__I2C123CLKSource__) \
+                  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_I2C123SEL, (uint32_t)(__I2C123CLKSource__))
+#endif /* RCC_D2CCIP2R_I2C123SEL */
+
+/** @brief  macro to get the I2C1/2/3 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3 clock
+  *            @arg RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3 clock
+  *            @arg RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3 clock
+  *            @arg RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3 clock
+  */
+#if defined(RCC_D2CCIP2R_I2C123SEL)
+#define __HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL)))
+#else
+#define __HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_I2C123SEL)))
+#endif /* RCC_D2CCIP2R_I2C123SEL */
+
+/** @brief macro to configure the I2C1 clock (I2C1CLK).
+  *
+  * @param  __I2C1CLKSource__ specifies the I2C1 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock
+  *            @arg RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock
+  *            @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
+  *            @arg RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock
+  */
+#define __HAL_RCC_I2C1_CONFIG  __HAL_RCC_I2C123_CONFIG
+
+/** @brief  macro to get the I2C1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock
+  *            @arg RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock
+  *            @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
+  *            @arg RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock
+  */
+#define __HAL_RCC_GET_I2C1_SOURCE __HAL_RCC_GET_I2C123_SOURCE
+
+/** @brief macro to configure the I2C2 clock (I2C2CLK).
+  *
+  * @param  __I2C2CLKSource__ specifies the I2C2 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock
+  *            @arg RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock
+  *            @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
+  *            @arg RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock
+  */
+#define __HAL_RCC_I2C2_CONFIG __HAL_RCC_I2C123_CONFIG
+
+/** @brief  macro to get the I2C2 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock
+  *            @arg RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock
+  *            @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
+  *            @arg RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock
+  */
+#define __HAL_RCC_GET_I2C2_SOURCE __HAL_RCC_GET_I2C123_SOURCE
+
+/** @brief macro to configure the I2C3 clock (I2C3CLK).
+  *
+  * @param  __I2C3CLKSource__ specifies the I2C3 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock
+  *            @arg RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock
+  *            @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
+  *            @arg RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock
+  */
+#define __HAL_RCC_I2C3_CONFIG __HAL_RCC_I2C123_CONFIG
+
+/** @brief  macro to get the I2C3 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock
+  *            @arg RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock
+  *            @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
+  *            @arg RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock
+  */
+#define __HAL_RCC_GET_I2C3_SOURCE __HAL_RCC_GET_I2C123_SOURCE
+
+/** @brief macro to configure the I2C4 clock (I2C4CLK).
+  *
+  * @param  __I2C4CLKSource__ specifies the I2C4 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock
+  *            @arg RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock
+  *            @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
+  *            @arg RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock
+  */
+#if defined(RCC_D3CCIPR_I2C4SEL)
+#define __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) \
+                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__))
+#else
+#define __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) \
+                  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__))
+#endif /* RCC_D3CCIPR_I2C4SEL */
+
+/** @brief  macro to get the I2C4 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock
+  *            @arg RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock
+  *            @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
+  *            @arg RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock
+  */
+#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL)))
+
+/** @brief macro to configure the USART1/6/9* /10* clock (USART16CLK).
+  *
+  * @param  __USART16CLKSource__ specifies the USART1/6/9* /10* clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6/9* /10* clock
+  *            @arg RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6/9* /10* clock
+  *            @arg RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6/9* /10* clock
+  *            @arg RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6/9* /10* clock
+  *            @arg RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6/9* /10* clock
+  *            @arg RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6/9* /10* clock
+  *
+  * (*) : Available on some STM32H7 lines only.
+  */
+#if defined(RCC_D2CCIP2R_USART16SEL)
+#define __HAL_RCC_USART16_CONFIG(__USART16CLKSource__) \
+                  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART16CLKSource__))
+#else
+#define __HAL_RCC_USART16910_CONFIG(__USART16910CLKSource__) \
+                  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART16910SEL, (uint32_t)(__USART16910CLKSource__))
+/* alias */
+#define __HAL_RCC_USART16_CONFIG  __HAL_RCC_USART16910_CONFIG
+#endif /* RCC_D2CCIP2R_USART16SEL */
+
+/** @brief  macro to get the USART1/6/9* /10* clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6/9* /10* clock
+  *            @arg RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6/9* /10* clock
+  *            @arg RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6/9* /10* clock
+  *            @arg RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6/9* /10* clock
+  *            @arg RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6/9* /10* clock
+  *            @arg RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6/9* /10* clock
+  *
+  * (*) : Available on some STM32H7 lines only.
+  */
+#if defined(RCC_D2CCIP2R_USART16SEL)
+#define __HAL_RCC_GET_USART16_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL)))
+#else
+#define __HAL_RCC_GET_USART16910_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART16910SEL)))
+/* alias*/
+#define  __HAL_RCC_GET_USART16_SOURCE  __HAL_RCC_GET_USART16910_SOURCE
+#endif /* RCC_D2CCIP2R_USART16SEL */
+
+/** @brief macro to configure the USART234578 clock (USART234578CLK).
+  *
+  * @param  __USART234578CLKSource__ specifies the USART2/3/4/5/7/8 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock
+  *            @arg RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock
+  *            @arg RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock
+  *            @arg RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock
+  *            @arg RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock
+  *            @arg RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock
+  */
+#if defined(RCC_D2CCIP2R_USART28SEL)
+#define __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) \
+                  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART234578CLKSource__))
+#else
+#define __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) \
+                  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL, (uint32_t)(__USART234578CLKSource__))
+#endif /* RCC_D2CCIP2R_USART28SEL */
+
+/** @brief  macro to get the USART2/3/4/5/7/8 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock
+  *            @arg RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock
+  *            @arg RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock
+  *            @arg RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock
+  *            @arg RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock
+  *            @arg RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock
+  */
+#if defined(RCC_D2CCIP2R_USART28SEL)
+#define __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
+#else
+#define __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL)))
+#endif /* RCC_D2CCIP2R_USART28SEL */
+
+/** @brief macro to configure the USART1 clock (USART1CLK).
+  *
+  * @param  __USART1CLKSource__ specifies the USART1 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
+  */
+#define __HAL_RCC_USART1_CONFIG  __HAL_RCC_USART16_CONFIG
+
+/** @brief  macro to get the USART1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock
+  *            @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
+  */
+#define __HAL_RCC_GET_USART1_SOURCE  __HAL_RCC_GET_USART16_SOURCE
+
+/** @brief macro to configure the USART2 clock (USART2CLK).
+  *
+  * @param  __USART2CLKSource__ specifies the USART2 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
+  */
+#define __HAL_RCC_USART2_CONFIG  __HAL_RCC_USART234578_CONFIG
+
+/** @brief  macro to get the USART2 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock
+  *            @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
+  */
+#define __HAL_RCC_GET_USART2_SOURCE __HAL_RCC_GET_USART234578_SOURCE
+
+/** @brief macro to configure the USART3 clock (USART3CLK).
+  *
+  * @param  __USART3CLKSource__ specifies the USART3 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_USART3CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
+  */
+#define __HAL_RCC_USART3_CONFIG  __HAL_RCC_USART234578_CONFIG
+
+/** @brief  macro to get the USART3 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock
+  *            @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
+  */
+#define __HAL_RCC_GET_USART3_SOURCE  __HAL_RCC_GET_USART234578_SOURCE
+
+/** @brief macro to configure the UART4 clock (UART4CLK).
+  *
+  * @param  __UART4CLKSource__ specifies the UART4 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
+  */
+#define __HAL_RCC_UART4_CONFIG  __HAL_RCC_USART234578_CONFIG
+
+/** @brief  macro to get the UART4 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock
+  *            @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
+  */
+#define __HAL_RCC_GET_UART4_SOURCE  __HAL_RCC_GET_USART234578_SOURCE
+
+/** @brief macro to configure the UART5 clock (UART5CLK).
+  *
+  * @param  __UART5CLKSource__ specifies the UART5 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
+  */
+#define __HAL_RCC_UART5_CONFIG  __HAL_RCC_USART234578_CONFIG
+
+/** @brief  macro to get the UART5 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock
+  *            @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
+  */
+#define __HAL_RCC_GET_UART5_SOURCE  __HAL_RCC_GET_USART234578_SOURCE
+
+/** @brief macro to configure the USART6 clock (USART6CLK).
+  *
+  * @param  __USART6CLKSource__ specifies the USART6 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
+  */
+#define __HAL_RCC_USART6_CONFIG  __HAL_RCC_USART16_CONFIG
+
+/** @brief  macro to get the USART6 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock
+  *            @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
+  */
+#define __HAL_RCC_GET_USART6_SOURCE  __HAL_RCC_GET_USART16_SOURCE
+
+/** @brief macro to configure the UART5 clock (UART7CLK).
+  *
+  * @param  __UART7CLKSource__ specifies the UART7 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
+  */
+#define __HAL_RCC_UART7_CONFIG  __HAL_RCC_USART234578_CONFIG
+
+/** @brief  macro to get the UART7 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock
+  *            @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
+  */
+#define __HAL_RCC_GET_UART7_SOURCE  __HAL_RCC_GET_USART234578_SOURCE
+
+/** @brief macro to configure the UART8 clock (UART8CLK).
+  *
+  * @param  __UART8CLKSource__ specifies the UART8 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
+  */
+#define __HAL_RCC_UART8_CONFIG  __HAL_RCC_USART234578_CONFIG
+
+/** @brief  macro to get the UART8 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock
+  *            @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
+  */
+#define __HAL_RCC_GET_UART8_SOURCE  __HAL_RCC_GET_USART234578_SOURCE
+
+#if defined(UART9)
+/** @brief macro to configure the UART9 clock (UART9CLK).
+  *
+  * @param  __UART8CLKSource__ specifies the UART8 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_UART9CLKSOURCE_D2PCLK1: APB1 Clock selected as UART9 clock
+  *            @arg RCC_UART9CLKSOURCE_PLL2: PLL2_Q Clock selected as UART9 clock
+  *            @arg RCC_UART9CLKSOURCE_PLL3: PLL3_Q Clock selected as UART9 clock
+  *            @arg RCC_UART9CLKSOURCE_HSI: HSI selected as UART9 clock
+  *            @arg RCC_UART9CLKSOURCE_CSI: CSI Clock selected as UART9 clock
+  *            @arg RCC_UART9CLKSOURCE_LSE: LSE selected as UART9 clock
+  */
+#define __HAL_RCC_UART9_CONFIG  __HAL_RCC_USART16_CONFIG
+
+/** @brief  macro to get the UART9 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_UART9CLKSOURCE_D2PCLK1: APB1 Clock selected as UART99 clock
+  *            @arg RCC_UART9CLKSOURCE_PLL2: PLL2_Q Clock selected as UART99 clock
+  *            @arg RCC_UART9CLKSOURCE_PLL3: PLL3_Q Clock selected as UART99 clock
+  *            @arg RCC_UART9CLKSOURCE_HSI: HSI selected as UART9 clock
+  *            @arg RCC_UART9CLKSOURCE_CSI: CSI Clock selected as UART9 clock
+  *            @arg RCC_UART9CLKSOURCE_LSE: LSE selected as UART9 clock
+  */
+#define __HAL_RCC_GET_UART9_SOURCE  __HAL_RCC_GET_USART16_SOURCE
+#endif /* UART9 */
+
+#if defined(USART10)
+/** @brief macro to configure the USART10 clock (USART10CLK).
+  *
+  * @param  __UART8CLKSource__ specifies the UART8 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_USART10CLKSOURCE_D2PCLK1: APB1 Clock selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_PLL2: PLL2_Q Clock selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_PLL3: PLL3_Q Clock selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_HSI: HSI selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_CSI: CSI Clock selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_LSE: LSE selected as USART10 clock
+  */
+#define __HAL_RCC_USART10_CONFIG  __HAL_RCC_USART16_CONFIG
+
+/** @brief  macro to get the USART10 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_USART10CLKSOURCE_D2PCLK1: APB1 Clock selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_PLL2: PLL2_Q Clock selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_PLL3: PLL3_Q Clock selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_HSI: HSI selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_CSI: CSI Clock selected as USART10 clock
+  *            @arg RCC_USART10CLKSOURCE_LSE: LSE selected as USART10 clock
+  */
+#define __HAL_RCC_GET_USART10_SOURCE  __HAL_RCC_GET_USART16_SOURCE
+#endif /* USART10 */
+
+/** @brief macro to configure the LPUART1 clock (LPUART1CLK).
+  *
+  * @param  __LPUART1CLKSource__ specifies the LPUART1 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock
+  */
+#if defined (RCC_D3CCIPR_LPUART1SEL)
+#define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \
+                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))
+#else
+#define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \
+                  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))
+#endif /* RCC_D3CCIPR_LPUART1SEL */
+
+/** @brief  macro to get the LPUART1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock
+  *            @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock
+  */
+#if defined (RCC_D3CCIPR_LPUART1SEL)
+#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL)))
+#else
+#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL)))
+#endif /* RCC_D3CCIPR_LPUART1SEL */
+
+/** @brief  macro to configure the LPTIM1 clock source.
+  *
+  * @param  __LPTIM1CLKSource__ specifies the LPTIM1 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock
+  */
+#if defined(RCC_D2CCIP2R_LPTIM1SEL)
+#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \
+                  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))
+#else
+#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \
+                  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))
+#endif /* RCC_D2CCIP2R_LPTIM1SEL */
+
+/** @brief  macro to get the LPTIM1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock
+  */
+#if defined(RCC_D2CCIP2R_LPTIM1SEL)
+#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL)))
+#else
+#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL)))
+#endif /* RCC_D2CCIP2R_LPTIM1SEL */
+
+/** @brief  macro to configure the LPTIM2 clock source.
+  *
+  * @param  __LPTIM2CLKSource__ specifies the LPTIM2 clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock
+  */
+#if defined(RCC_D3CCIPR_LPTIM2SEL)
+#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) \
+                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__))
+#else
+#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) \
+                  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__))
+#endif /* RCC_D3CCIPR_LPTIM2SEL */
+
+/** @brief  macro to get the LPTIM2 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock
+  *            @arg RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock
+  */
+#if defined(RCC_D3CCIPR_LPTIM2SEL)
+#define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL)))
+#else
+#define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL)))
+#endif /* RCC_D3CCIPR_LPTIM2SEL */
+
+/** @brief  macro to configure the LPTIM3/4/5 clock source.
+  *
+  * @param  __LPTIM345CLKSource__ specifies the LPTIM3/4/5 clock source.
+  *            @arg RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock
+  *            @arg RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock
+  *            @arg RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock
+  *            @arg RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock
+  *            @arg RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock
+  *            @arg RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock
+  */
+#if defined(RCC_D3CCIPR_LPTIM345SEL)
+#define __HAL_RCC_LPTIM345_CONFIG(__LPTIM345CLKSource__) \
+                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM345CLKSource__))
+#else
+#define __HAL_RCC_LPTIM345_CONFIG(__LPTIM3CLKSource__) \
+                  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL, (uint32_t)(__LPTIM3CLKSource__))
+#endif /* RCC_D3CCIPR_LPTIM345SEL */
+
+/** @brief  macro to get the LPTIM3/4/5 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock
+  *            @arg RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock
+  *            @arg RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock
+  *            @arg RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock
+  *            @arg RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock
+  *            @arg RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock
+  */
+#if defined(RCC_D3CCIPR_LPTIM345SEL)
+#define __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL)))
+#else
+#define __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL)))
+#endif /* RCC_D3CCIPR_LPTIM345SEL */
+
+/** @brief  macro to configure the LPTIM3 clock source.
+  *
+  * @param  __LPTIM3CLKSource__ specifies the LPTIM3 clock source.
+  *            @arg RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock
+  */
+#define __HAL_RCC_LPTIM3_CONFIG  __HAL_RCC_LPTIM345_CONFIG
+
+/** @brief  macro to get the LPTIM3 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock
+  *            @arg RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock
+  */
+#define __HAL_RCC_GET_LPTIM3_SOURCE  __HAL_RCC_GET_LPTIM345_SOURCE
+
+#if defined(LPTIM4)
+/** @brief  macro to configure the LPTIM4 clock source.
+  *
+  * @param  __LPTIM4CLKSource__ specifies the LPTIM4 clock source.
+  *            @arg RCC_LPTIM4CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_LSE: LSE selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_LSI: LSI Clock selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_CLKP: CLKP selected as LPTIM4 clock
+  */
+#define __HAL_RCC_LPTIM4_CONFIG  __HAL_RCC_LPTIM345_CONFIG
+
+
+/** @brief  macro to get the LPTIM4 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_LPTIM4CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_LSE: LSE selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_LSI: LSI Clock selected as LPTIM4 clock
+  *            @arg RCC_LPTIM4CLKSOURCE_CLKP: CLKP selected as LPTIM4 clock
+  */
+#define __HAL_RCC_GET_LPTIM4_SOURCE  __HAL_RCC_GET_LPTIM345_SOURCE
+#endif /* LPTIM4 */
+
+#if defined(LPTIM5)
+/** @brief  macro to configure the LPTIM5 clock source.
+  *
+  * @param  __LPTIM5CLKSource__ specifies the LPTIM5 clock source.
+  *            @arg RCC_LPTIM5CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_LSE: LSE selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_LSI: LSI Clock selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_CLKP: CLKP selected as LPTIM5 clock
+  */
+#define __HAL_RCC_LPTIM5_CONFIG  __HAL_RCC_LPTIM345_CONFIG
+
+
+/** @brief  macro to get the LPTIM5 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_LPTIM5CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_LSE: LSE selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_LSI: LSI Clock selected as LPTIM5 clock
+  *            @arg RCC_LPTIM5CLKSOURCE_CLKP: CLKP selected as LPTIM5 clock
+  */
+#define __HAL_RCC_GET_LPTIM5_SOURCE  __HAL_RCC_GET_LPTIM345_SOURCE
+#endif /* LPTIM5 */
+
+#if defined(QUADSPI)
+/** @brief  macro to configure the QSPI clock source.
+  *
+  * @param  __QSPICLKSource__ specifies the QSPI clock source.
+  *            @arg RCC_RCC_QSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as QSPI clock
+  *            @arg RCC_RCC_QSPICLKSOURCE_PLL   : PLL1_Q Clock selected as QSPI clock
+  *            @arg RCC_RCC_QSPICLKSOURCE_PLL2  : PLL2_R Clock selected as QSPI clock
+  *            @arg RCC_RCC_QSPICLKSOURCE_CLKP    CLKP selected as QSPI clock
+  */
+#define __HAL_RCC_QSPI_CONFIG(__QSPICLKSource__) \
+                  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL, (uint32_t)(__QSPICLKSource__))
+
+
+/** @brief  macro to get the QSPI clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_RCC_QSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as QSPI clock
+  *            @arg RCC_RCC_QSPICLKSOURCE_PLL   : PLL1_Q Clock selected as QSPI clock
+  *            @arg RCC_RCC_QSPICLKSOURCE_PLL2  : PLL2_R Clock selected as QSPI clock
+  *            @arg RCC_RCC_QSPICLKSOURCE_CLKP    CLKP selected as QSPI clock
+  */
+#define __HAL_RCC_GET_QSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL)))
+#endif /* QUADSPI */
+
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+/** @brief  macro to configure the OSPI clock source.
+  *
+  * @param  __OSPICLKSource__ specifies the OSPI clock source.
+  *            @arg RCC_RCC_OSPICLKSOURCE_CDHCLK: Domain1 HCLK Clock selected as OSPI clock
+  *            @arg RCC_RCC_OSPICLKSOURCE_PLL   : PLL1_Q Clock selected as OSPI clock
+  *            @arg RCC_RCC_OSPICLKSOURCE_PLL2  : PLL2_R Clock selected as OSPI clock
+  *            @arg RCC_RCC_OSPICLKSOURCE_CLKP    CLKP selected as OSPI clock
+  */
+#define __HAL_RCC_OSPI_CONFIG(__OSPICLKSource__) \
+                  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL, (uint32_t)(__OSPICLKSource__))
+
+
+/** @brief  macro to get the OSPI clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_RCC_OSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as OSPI clock
+  *            @arg RCC_RCC_OSPICLKSOURCE_PLL   : PLL1_Q Clock selected as OSPI clock
+  *            @arg RCC_RCC_OSPICLKSOURCE_PLL2  : PLL2_R Clock selected as OSPI clock
+  *            @arg RCC_RCC_OSPICLKSOURCE_CLKP    CLKP selected as OSPI clock
+  */
+#define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL)))
+#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
+
+
+#if defined(DSI)
+/** @brief  macro to configure the DSI clock source.
+  *
+  * @param  __DSICLKSource__ specifies the DSI clock source.
+  *            @arg RCC_RCC_DSICLKSOURCE_PHY:DSI clock from PHY is selected as DSI byte lane clock
+  *            @arg RCC_RCC_DSICLKSOURCE_PLL2   : PLL2_Q Clock clock is selected as DSI byte lane clock
+  */
+#define __HAL_RCC_DSI_CONFIG(__DSICLKSource__) \
+                  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL, (uint32_t)(__DSICLKSource__))
+
+
+/** @brief  macro to get the DSI clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_RCC_DSICLKSOURCE_PHY: DSI clock from PHY is selected as DSI byte lane clock
+  *            @arg RCC_RCC_DSICLKSOURCE_PLL2: PLL2_Q Clock clock is selected as DSI byte lane clock
+  */
+#define __HAL_RCC_GET_DSI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL)))
+#endif /*DSI*/
+
+/** @brief  macro to configure the FMC clock source.
+  *
+  * @param  __FMCCLKSource__ specifies the FMC clock source.
+  *            @arg RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock
+  *            @arg RCC_RCC_FMCCLKSOURCE_PLL   : PLL1_Q Clock selected as FMC clock
+  *            @arg RCC_RCC_FMCCLKSOURCE_PLL2  : PLL2_R Clock selected as FMC clock
+  *            @arg RCC_RCC_FMCCLKSOURCE_CLKP    CLKP selected as FMC clock
+  */
+#if defined(RCC_D1CCIPR_FMCSEL)
+#define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) \
+                  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__))
+#else
+#define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) \
+                  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__))
+#endif /* RCC_D1CCIPR_FMCSEL */
+
+/** @brief  macro to get the FMC clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock
+  *            @arg RCC_RCC_FMCCLKSOURCE_PLL   : PLL1_Q Clock selected as FMC clock
+  *            @arg RCC_RCC_FMCCLKSOURCE_PLL2  : PLL2_R Clock selected as FMC clock
+  *            @arg RCC_RCC_FMCCLKSOURCE_CLKP    CLKP selected as FMC clock
+  */
+#if defined(RCC_D1CCIPR_FMCSEL)
+#define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL)))
+#else
+#define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL)))
+#endif /* RCC_D1CCIPR_FMCSEL */
+
+/** @brief  Macro to configure the USB clock (USBCLK).
+  * @param  __USBCLKSource__ specifies the USB clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_USBCLKSOURCE_PLL:   PLL1Q selected as USB clock
+  *            @arg RCC_USBCLKSOURCE_PLL3:  PLL3Q Clock selected as USB clock
+  *            @arg RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock
+  */
+#if defined(RCC_D2CCIP2R_USBSEL)
+#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
+                  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, (uint32_t)(__USBCLKSource__))
+#else
+#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
+                  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL, (uint32_t)(__USBCLKSource__))
+#endif /* RCC_D2CCIP2R_USBSEL */
+
+/** @brief  Macro to get the USB clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_USBCLKSOURCE_PLL:   PLL1Q selected as USB clock
+  *            @arg RCC_USBCLKSOURCE_PLL3:  PLL3Q Clock selected as USB clock
+  *            @arg RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock
+  */
+#if defined(RCC_D2CCIP2R_USBSEL)
+#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL)))
+#else
+#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL)))
+#endif /* RCC_D2CCIP2R_USBSEL */
+
+/** @brief  Macro to configure the ADC clock
+  * @param  __ADCCLKSource__ specifies the ADC digital interface clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock
+  *            @arg RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock
+  *            @arg RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock
+  */
+#if defined(RCC_D3CCIPR_ADCSEL)
+#define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \
+                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__))
+#else
+#define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \
+                  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__))
+#endif /* RCC_D3CCIPR_ADCSEL */
+
+/** @brief  Macro to get the ADC clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock
+  *            @arg RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock
+  *            @arg RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock
+  */
+#if defined(RCC_D3CCIPR_ADCSEL)
+#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL)))
+#else
+#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL)))
+#endif /* RCC_D3CCIPR_ADCSEL */
+
+ /** @brief  Macro to configure the SWPMI1 clock
+  * @param  __SWPMI1CLKSource__ specifies the SWPMI1  clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_SWPMI1CLKSOURCE_D2PCLK1:  D2PCLK1 Clock selected as SWPMI1 clock
+  *            @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock
+  */
+#if defined(RCC_D2CCIP1R_SWPSEL)
+#define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) \
+                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__))
+#else
+#define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) \
+                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__))
+#endif /* RCC_D2CCIP1R_SWPSEL */
+
+/** @brief  Macro to get the SWPMI1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_SWPMI1CLKSOURCE_D2PCLK1:  D2PCLK1 Clock selected as SWPMI1 clock
+  *            @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock
+  */
+#if defined(RCC_D2CCIP1R_SWPSEL)
+#define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL)))
+#else
+#define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL)))
+#endif /* RCC_D2CCIP1R_SWPSEL */
+
+ /** @brief  Macro to configure the DFSDM1 clock
+  * @param  __DFSDM1CLKSource__ specifies the DFSDM1  clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_DFSDM1CLKSOURCE_D2PCLK:  D2PCLK Clock selected as DFSDM1 clock
+  *            @arg RCC_DFSDM1CLKSOURCE_SYS:     System Clock selected as DFSDM1 clock
+  */
+#if defined(RCC_D2CCIP1R_DFSDM1SEL)
+#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) \
+                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__))
+#else
+#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) \
+                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__))
+#endif /* RCC_D2CCIP1R_DFSDM1SEL */
+
+/** @brief  Macro to get the DFSDM1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_DFSDM1CLKSOURCE_D2PCLK:  D2PCLK Clock selected as DFSDM1 clock
+  *            @arg RCC_DFSDM1CLKSOURCE_SYS:   System Clock selected as DFSDM1 clock
+  */
+#if defined (RCC_D2CCIP1R_DFSDM1SEL)
+#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL)))
+#else
+#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL)))
+#endif /* RCC_D2CCIP1R_DFSDM1SEL */
+
+#if defined(DFSDM2_BASE)
+ /** @brief  Macro to configure the DFSDM2 clock
+  * @param  __DFSDM2CLKSource__ specifies the DFSDM2  clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_DFSDM2CLKSOURCE_SRDPCLK1:  SRDPCLK1 (APB4) selected as DFSDM2 clock
+  *            @arg RCC_DFSDM2CLKSOURCE_SYS:   System Clock selected as DFSDM2 clock
+  */
+#define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2CLKSource__) \
+                  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL, (uint32_t)(__DFSDM2CLKSource__))
+
+/** @brief  Macro to get the DFSDM2 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_DFSDM2CLKSOURCE_SRDPCLK1:  SRDPCLK1 (APB4) Clock selected as DFSDM2 clock
+  *            @arg RCC_DFSDM2CLKSOURCE_SYS:   System Clock selected as DFSDM2 clock
+  */
+#define __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL)))
+#endif /* DFSDM2 */
+
+/** @brief macro to configure the CEC clock (CECCLK).
+  *
+  * @param  __CECCLKSource__ specifies the CEC clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
+  *            @arg RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock
+  *            @arg RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock
+  */
+#if defined(RCC_D2CCIP2R_CECSEL)
+#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
+                  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, (uint32_t)(__CECCLKSource__))
+#else
+#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
+                  MODIFY_REG(RCC->D2CCIP2R, RCC_CDCCIP2R_CECSEL, (uint32_t)(__CECCLKSource__))
+#endif /* RCC_D2CCIP2R_CECSEL */
+
+/** @brief  macro to get the CEC clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
+  *            @arg RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock
+  *            @arg RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock
+  */
+#if defined(RCC_D2CCIP2R_CECSEL)
+#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL)))
+#else
+#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL)))
+#endif /* RCC_D2CCIP2R_CECSEL */
+
+/** @brief  Macro to configure the CLKP : Oscillator clock for peripheral
+  * @param  __CLKPSource__ specifies Oscillator clock for peripheral
+  *         This parameter can be one of the following values:
+  *            @arg RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral
+  *            @arg RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral
+  *            @arg RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral
+  */
+#if defined(RCC_D1CCIPR_CKPERSEL)
+#define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \
+                  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, (uint32_t)(__CLKPSource__))
+#else
+#define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \
+                  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL, (uint32_t)(__CLKPSource__))
+#endif /* RCC_D1CCIPR_CKPERSEL */
+
+/** @brief  Macro to get the Oscillator clock for peripheral  source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral
+  *            @arg RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral
+  *            @arg RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral
+  */
+#if defined(RCC_D1CCIPR_CKPERSEL)
+#define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL)))
+#else
+#define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL)))
+#endif /* RCC_D1CCIPR_CKPERSEL */
+
+#if defined(FDCAN1) || defined(FDCAN2)
+/** @brief  Macro to configure the FDCAN clock
+  * @param  __FDCANCLKSource__ specifies  clock source  for FDCAN
+  *         This parameter can be one of the following values:
+  *            @arg RCC_FDCANCLKSOURCE_HSE: HSE selected as FDCAN clock
+  *            @arg RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock
+  *            @arg RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock
+  */
+#if defined(RCC_D2CCIP1R_FDCANSEL)
+#define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) \
+                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__))
+#else
+#define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) \
+                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__))
+#endif /* RCC_D2CCIP1R_FDCANSEL */
+
+/** @brief  Macro to get the FDCAN clock
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_FDCANCLKSOURCE_HSE: HSE selected as FDCAN clock
+  *            @arg RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock
+  *            @arg RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock
+  */
+#if defined(RCC_D2CCIP1R_FDCANSEL)
+#define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL)))
+#else
+#define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL)))
+#endif /* RCC_D2CCIP1R_FDCANSEL */
+
+#endif /*FDCAN1 || FDCAN2*/
+
+/**
+  * @brief  Macro to Configure the SPI1/2/3 clock source.
+  * @param  __RCC_SPI123CLKSource__ defines the SPI1/2/3 clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL
+  *             @arg RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2
+  *             @arg RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3
+  *             @arg RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock  = CLKP
+  *             @arg RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock
+  * @retval None
+  */
+#if defined(RCC_D2CCIP1R_SPI123SEL)
+#define __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__ )\
+                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__))
+#else
+#define __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__ )\
+                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__))
+#endif /* RCC_D2CCIP1R_SPI123SEL */
+
+/** @brief  Macro to get the SPI1/2/3 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL
+  *             @arg RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2
+  *             @arg RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3
+  *             @arg RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock  = CLKP
+  *             @arg RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock
+  */
+#if defined(RCC_D2CCIP1R_SPI123SEL)
+#define __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL)))
+#else
+#define __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL)))
+#endif /* RCC_D2CCIP1R_SPI123SEL */
+
+/**
+  * @brief  Macro to Configure the SPI1 clock source.
+  * @param  __RCC_SPI1CLKSource__ defines the SPI1 clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL
+  *             @arg RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2
+  *             @arg RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3
+  *             @arg RCC_SPI1CLKSOURCE_CLKP: SPI1 clock  = CLKP
+  *             @arg RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock
+  * @retval None
+  */
+#define __HAL_RCC_SPI1_CONFIG  __HAL_RCC_SPI123_CONFIG
+
+/** @brief  Macro to get the SPI1 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL
+  *             @arg RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2
+  *             @arg RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3
+  *             @arg RCC_SPI1CLKSOURCE_CLKP: SPI1 clock  = CLKP
+  *             @arg RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock
+  */
+#define __HAL_RCC_GET_SPI1_SOURCE  __HAL_RCC_GET_SPI123_SOURCE
+
+/**
+  * @brief  Macro to Configure the SPI2 clock source.
+  * @param  __RCC_SPI2CLKSource__ defines the SPI2 clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL
+  *             @arg RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2
+  *             @arg RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3
+  *             @arg RCC_SPI2CLKSOURCE_CLKP: SPI2 clock  = CLKP
+  *             @arg RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock
+  * @retval None
+  */
+#define __HAL_RCC_SPI2_CONFIG  __HAL_RCC_SPI123_CONFIG
+
+/** @brief  Macro to get the SPI2 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL
+  *             @arg RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2
+  *             @arg RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3
+  *             @arg RCC_SPI2CLKSOURCE_CLKP: SPI2 clock  = CLKP
+  *             @arg RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock
+  */
+#define __HAL_RCC_GET_SPI2_SOURCE  __HAL_RCC_GET_SPI123_SOURCE
+
+/**
+  * @brief  Macro to Configure the SPI3 clock source.
+  * @param  __RCC_SPI3CLKSource__ defines the SPI3 clock source. This clock is derived
+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL
+  *             @arg RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2
+  *             @arg RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3
+  *             @arg RCC_SPI3CLKSOURCE_CLKP: SPI3 clock  = CLKP
+  *             @arg RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock
+  * @retval None
+  */
+#define __HAL_RCC_SPI3_CONFIG  __HAL_RCC_SPI123_CONFIG
+
+/** @brief  Macro to get the SPI3 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL
+  *             @arg RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2
+  *             @arg RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3
+  *             @arg RCC_SPI3CLKSOURCE_CLKP: SPI3 clock  = CLKP
+  *             @arg RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock
+  */
+#define __HAL_RCC_GET_SPI3_SOURCE  __HAL_RCC_GET_SPI123_SOURCE
+
+/**
+  * @brief  Macro to Configure the SPI4/5 clock source.
+  * @param  __RCC_SPI45CLKSource__ defines the SPI4/5 clock source. This clock is derived
+  *         from system PCLK, PLL2, PLL3, OSC
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SPI45CLKSOURCE_D2PCLK1:SPI4/5 clock = D2PCLK1
+  *             @arg RCC_SPI45CLKSOURCE_PLL2:   SPI4/5 clock = PLL2
+  *             @arg RCC_SPI45CLKSOURCE_PLL3:   SPI4/5 clock = PLL3
+  *             @arg RCC_SPI45CLKSOURCE_HSI:    SPI4/5 clock = HSI
+  *             @arg RCC_SPI45CLKSOURCE_CSI:    SPI4/5 clock = CSI
+  *             @arg RCC_SPI45CLKSOURCE_HSE:    SPI4/5 clock = HSE
+  * @retval None
+  */
+#if defined(RCC_D2CCIP1R_SPI45SEL)
+#define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__ )\
+                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__))
+#else
+#define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__ )\
+                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__))
+#endif /* RCC_D2CCIP1R_SPI45SEL */
+
+/** @brief  Macro to get the SPI4/5 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SPI45CLKSOURCE_D2PCLK1:SPI4/5 clock = D2PCLK1
+  *             @arg RCC_SPI45CLKSOURCE_PLL2:   SPI4/5 clock = PLL2
+  *             @arg RCC_SPI45CLKSOURCE_PLL3:   SPI4/5 clock = PLL3
+  *             @arg RCC_SPI45CLKSOURCE_HSI:    SPI4/5 clock = HSI
+  *             @arg RCC_SPI45CLKSOURCE_CSI:    SPI4/5 clock = CSI
+  *             @arg RCC_SPI45CLKSOURCE_HSE:    SPI4/5 clock = HSE
+*/
+#if defined(RCC_D2CCIP1R_SPI45SEL)
+#define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL)))
+#else
+#define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL)))
+#endif /* RCC_D2CCIP1R_SPI45SEL */
+
+/**
+  * @brief  Macro to Configure the SPI4 clock source.
+  * @param  __RCC_SPI4CLKSource__ defines the SPI4 clock source. This clock is derived
+  *         from system PCLK, PLL2, PLL3, OSC
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1
+  *             @arg RCC_SPI4CLKSOURCE_PLL2:   SPI4 clock = PLL2
+  *             @arg RCC_SPI4CLKSOURCE_PLL3:   SPI4 clock = PLL3
+  *             @arg RCC_SPI4CLKSOURCE_HSI:    SPI4 clock = HSI
+  *             @arg RCC_SPI4CLKSOURCE_CSI:    SPI4 clock = CSI
+  *             @arg RCC_SPI4CLKSOURCE_HSE:    SPI4 clock = HSE
+  * @retval None
+  */
+#define __HAL_RCC_SPI4_CONFIG  __HAL_RCC_SPI45_CONFIG
+
+/** @brief  Macro to get the SPI4 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1
+  *             @arg RCC_SPI4CLKSOURCE_PLL2:   SPI4 clock = PLL2
+  *             @arg RCC_SPI4CLKSOURCE_PLL3:   SPI4 clock = PLL3
+  *             @arg RCC_SPI4CLKSOURCE_HSI:    SPI4 clock = HSI
+  *             @arg RCC_SPI4CLKSOURCE_CSI:    SPI4 clock = CSI
+  *             @arg RCC_SPI4CLKSOURCE_HSE:    SPI4 clock = HSE
+*/
+#define __HAL_RCC_GET_SPI4_SOURCE  __HAL_RCC_GET_SPI45_SOURCE
+
+/**
+  * @brief  Macro to Configure the SPI5 clock source.
+  * @param  __RCC_SPI5CLKSource__ defines the SPI5 clock source. This clock is derived
+  *         from system PCLK, PLL2, PLL3, OSC
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1
+  *             @arg RCC_SPI5CLKSOURCE_PLL2:   SPI5 clock = PLL2
+  *             @arg RCC_SPI5CLKSOURCE_PLL3:   SPI5 clock = PLL3
+  *             @arg RCC_SPI5CLKSOURCE_HSI:    SPI5 clock = HSI
+  *             @arg RCC_SPI5CLKSOURCE_CSI:    SPI5 clock = CSI
+  *             @arg RCC_SPI5CLKSOURCE_HSE:    SPI5 clock = HSE
+  * @retval None
+  */
+#define __HAL_RCC_SPI5_CONFIG  __HAL_RCC_SPI45_CONFIG
+
+/** @brief  Macro to get the SPI5 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1
+  *             @arg RCC_SPI5CLKSOURCE_PLL2:   SPI5 clock = PLL2
+  *             @arg RCC_SPI5CLKSOURCE_PLL3:   SPI5 clock = PLL3
+  *             @arg RCC_SPI5CLKSOURCE_HSI:    SPI5 clock = HSI
+  *             @arg RCC_SPI5CLKSOURCE_CSI:    SPI5 clock = CSI
+  *             @arg RCC_SPI5CLKSOURCE_HSE:    SPI5 clock = HSE
+*/
+#define __HAL_RCC_GET_SPI5_SOURCE  __HAL_RCC_GET_SPI45_SOURCE
+
+/**
+  * @brief  Macro to Configure the SPI6 clock source.
+  * @param  __RCC_SPI6CLKSource__ defines the SPI6 clock source. This clock is derived
+  *         from system PCLK, PLL2, PLL3, OSC
+  *          This parameter can be one of the following values:
+  *             @arg RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1
+  *             @arg RCC_SPI6CLKSOURCE_PLL2:   SPI6 clock = PLL2
+  *             @arg RCC_SPI6CLKSOURCE_PLL3:   SPI6 clock = PLL3
+  *             @arg RCC_SPI6CLKSOURCE_HSI:    SPI6 clock = HSI
+  *             @arg RCC_SPI6CLKSOURCE_CSI:    SPI6 clock = CSI
+  *             @arg RCC_SPI6CLKSOURCE_HSE:    SPI6 clock = HSE
+  *             @arg RCC_SPI6CLKSOURCE_PIN:    SPI6 clock = I2S_CKIN (*)
+  *
+  * @retval None
+  *
+  * (*) : Available on stm32h7a3xx and stm32h7b3xx family lines.
+  *
+  */
+#if defined(RCC_D3CCIPR_SPI6SEL)
+#define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__ )\
+                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL, (__RCC_SPI6CLKSource__))
+#else
+#define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__ )\
+                  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL, (__RCC_SPI6CLKSource__))
+#endif /* RCC_D3CCIPR_SPI6SEL */
+
+/** @brief  Macro to get the SPI6 clock source.
+  * @retval The clock source can be one of the following values:
+  *             @arg RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1
+  *             @arg RCC_SPI6CLKSOURCE_PLL2:   SPI6 clock = PLL2
+  *             @arg RCC_SPI6CLKSOURCE_PLL3:   SPI6 clock = PLL3
+  *             @arg RCC_SPI6CLKSOURCE_HSI:    SPI6 clock = HSI
+  *             @arg RCC_SPI6CLKSOURCE_CSI:    SPI6 clock = CSI
+  *             @arg RCC_SPI6CLKSOURCE_HSE:    SPI6 clock = HSE
+  *                @arg RCC_SPI6CLKSOURCE_PIN:    SPI6 clock = I2S_CKIN
+*/
+#if defined(RCC_D3CCIPR_SPI6SEL)
+#define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL)))
+#else
+#define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL)))
+#endif /* RCC_D3CCIPR_SPI6SEL */
+
+/** @brief  Macro to configure the SDMMC clock
+  * @param  __SDMMCCLKSource__ specifies  clock source  for SDMMC
+  *         This parameter can be one of the following values:
+  *            @arg RCC_SDMMCCLKSOURCE_PLL:  PLLQ selected as SDMMC clock
+  *            @arg RCC_SDMMCCLKSOURCE_PLL2: PLL2R selected as SDMMC clock
+  */
+#if defined(RCC_D1CCIPR_SDMMCSEL)
+#define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) \
+                  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__))
+#else
+#define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) \
+                  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__))
+#endif /* RCC_D1CCIPR_SDMMCSEL */
+
+/** @brief  Macro to get the SDMMC clock
+  */
+#if defined(RCC_D1CCIPR_SDMMCSEL)
+#define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL)))
+#else
+#define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL)))
+#endif /* RCC_D1CCIPR_SDMMCSEL */
+
+/** @brief macro to configure the RNG clock (RNGCLK).
+  *
+  * @param  __RNGCLKSource__ specifies the RNG clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
+  *            @arg RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock
+  *            @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock
+  *            @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock
+  */
+#if defined(RCC_D2CCIP2R_RNGSEL)
+#define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \
+                  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__))
+#else
+#define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \
+                  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__))
+#endif /* RCC_D2CCIP2R_RNGSEL */
+
+/** @brief  macro to get the RNG clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
+  *            @arg RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock
+  *            @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock
+  *            @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock
+  */
+#if defined(RCC_D2CCIP2R_RNGSEL)
+#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL)))
+#else
+#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL)))
+#endif /* RCC_D2CCIP2R_RNGSEL */
+
+#if defined(HRTIM1)
+/** @defgroup RCCEx_HRTIMx_Clock_Config RCC Extended HRTIMx Clock Config
+  * @{
+  */
+/** @brief  Macro to configure the HRTIM1 prescaler clock source.
+  * @param  __HRTIM1CLKSource__ specifies the HRTIM1 prescaler clock source.
+  *         This parameter can be one of the following values:
+  *            @arg @ref RCC_HRTIM1CLK_TIMCLK    Timers  clock  selected as HRTIM1 prescaler clock
+  *            @arg @ref RCC_HRTIM1CLK_CPUCLK CPU Clock selected as HRTIM1 clock
+  */
+#define __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) \
+                  MODIFY_REG(RCC->CFGR, RCC_CFGR_HRTIMSEL, (uint32_t)(__HRTIM1CLKSource__))
+
+/** @brief  Macro to get the HRTIM1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg @ref RCC_HRTIM1CLK_TIMCLK   Timers  clock  selected as HRTIM1 prescaler clock
+  *            @arg @ref RCC_HRTIM1CLK_CPUCLK CPU Clock selected as HRTIM1 clock
+  */
+#define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HRTIMSEL)))
+#endif /* HRTIM1 */
+
+/** @brief  Macro to configure the Timers clocks prescalers
+  * @param  __PRESC__  specifies the Timers clocks prescalers selection
+  *         This parameter can be one of the following values:
+  *            @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
+  *                 equal to rcc_hclk1 if D2PPREx is corresponding to division by 1 or 2,
+  *                 else it is equal to 2 x Frcc_pclkx_d2 (default after reset)
+  *            @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
+  *                 equal to rcc_hclk1 if D2PPREx is corresponding to division by 1, 2 or 4,
+  *                 else it is equal to 4 x Frcc_pclkx_d2
+  */
+#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->CFGR &= ~(RCC_CFGR_TIMPRE);\
+                                                 RCC->CFGR |= (__PRESC__);       \
+                                                }while(0)
+
+/**
+  * @}
+  */
+    
+/**
+  * @brief Enable the RCC LSE CSS Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT()      SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Disable the RCC LSE CSS Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT()     CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Enable the RCC LSE CSS Event Line.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Disable the RCC LSE CSS Event Line.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
+
+#if defined(DUAL_CORE)
+/**
+  * @brief Enable the RCC LSE CSS Extended Interrupt Line for CM4.
+  * @retval None
+  */
+#define __HAL_RCC_C2_LSECSS_EXTI_ENABLE_IT()       SET_BIT(EXTI->C2IMR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Disable the RCC LSE CSS Extended Interrupt Line for CM4.
+  * @retval None
+  */
+#define __HAL_RCC_C2_LSECSS_EXTI_DISABLE_IT()      CLEAR_BIT(EXTI->C2IMR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Enable the RCC LSE CSS Event Line for CM4.
+  * @retval None.
+  */
+#define __HAL_RCC_C2_LSECSS_EXTI_ENABLE_EVENT()    SET_BIT(EXTI->C2EMR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Disable the RCC LSE CSS Event Line for CM4.
+  * @retval None.
+  */
+#define __HAL_RCC_C2_LSECSS_EXTI_DISABLE_EVENT()   CLEAR_BIT(EXTI->C2EMR1, RCC_EXTI_LINE_LSECSS)
+#endif /* DUAL_CORE */
+
+/**
+  * @brief  Enable the RCC LSE CSS Extended Interrupt Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE()  SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
+
+
+/**
+  * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
+
+
+/**
+  * @brief  Enable the RCC LSE CSS Extended Interrupt Rising Trigger.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE()  \
+  do {                                                      \
+    __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();             \
+    __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE();            \
+  } while(0)
+
+/**
+  * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE()  \
+  do {                                                       \
+    __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE();             \
+    __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE();            \
+  } while(0)
+
+/**
+  * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
+  * @retval EXTI RCC LSE CSS Line Status.
+  */
+#define __HAL_RCC_LSECSS_EXTI_GET_FLAG()       (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Clear the RCC LSE CSS EXTI flag.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG()     WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS)
+
+#if defined(DUAL_CORE)
+/**
+  * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not for CM4.
+  * @retval EXTI RCC LSE CSS Line Status.
+  */
+#define __HAL_RCC_C2_LSECSS_EXTI_GET_FLAG()       (READ_BIT(EXTI->C2PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Clear the RCC LSE CSS EXTI flag or not for CM4.
+  * @retval None.
+  */
+#define __HAL_RCC_C2_LSECSS_EXTI_CLEAR_FLAG()     WRITE_REG(EXTI->C2PR1, RCC_EXTI_LINE_LSECSS)
+#endif /* DUAL_CORE */
+/**
+  * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT()  SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS)
+ 
+/**
+  * @brief  Enable the specified CRS interrupts.
+  * @param  __INTERRUPT__ specifies the CRS interrupt sources to be enabled.
+  *          This parameter can be any combination of the following values:
+  *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
+  *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
+  *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
+  *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
+  * @retval None
+  */
+#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__)   SET_BIT(CRS->CR, (__INTERRUPT__))
+
+/**
+  * @brief  Disable the specified CRS interrupts.
+  * @param  __INTERRUPT__ specifies the CRS interrupt sources to be disabled.
+  *          This parameter can be any combination of the following values:
+  *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
+  *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
+  *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
+  *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
+  * @retval None
+  */
+#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__)  CLEAR_BIT(CRS->CR, (__INTERRUPT__))
+
+/** @brief  Check whether the CRS interrupt has occurred or not.
+  * @param  __INTERRUPT__ specifies the CRS interrupt source to check.
+  *         This parameter can be one of the following values:
+  *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
+  *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
+  *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
+  *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
+  * @retval The new state of __INTERRUPT__ (SET or RESET).
+  */
+#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__)  ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET)
+
+/** @brief  Clear the CRS interrupt pending bits
+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
+  *         This parameter can be any combination of the following values:
+  *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt
+  *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt
+  *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt
+  *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt
+  *              @arg @ref RCC_CRS_IT_TRIMOVF  Trimming overflow or underflow interrupt
+  *              @arg @ref RCC_CRS_IT_SYNCERR  SYNC error interrupt
+  *              @arg @ref RCC_CRS_IT_SYNCMISS  SYNC missed interrupt
+  */
+/* CRS IT Error Mask */
+#define  RCC_CRS_IT_ERROR_MASK                 ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))
+
+#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__)  do { \
+                                                 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \
+                                                 { \
+                                                   WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
+                                                 } \
+                                                 else \
+                                                 { \
+                                                   WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
+                                                 } \
+                                               } while(0)
+
+/**
+  * @brief  Check whether the specified CRS flag is set or not.
+  * @param  __FLAG__ specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *              @arg @ref RCC_CRS_FLAG_SYNCOK  SYNC event OK
+  *              @arg @ref RCC_CRS_FLAG_SYNCWARN  SYNC warning
+  *              @arg @ref RCC_CRS_FLAG_ERR  Error
+  *              @arg @ref RCC_CRS_FLAG_ESYNC  Expected SYNC
+  *              @arg @ref RCC_CRS_FLAG_TRIMOVF  Trimming overflow or underflow
+  *              @arg @ref RCC_CRS_FLAG_SYNCERR  SYNC error
+  *              @arg @ref RCC_CRS_FLAG_SYNCMISS  SYNC missed
+  * @retval The new state of _FLAG_ (TRUE or FALSE).
+  */
+#define __HAL_RCC_CRS_GET_FLAG(__FLAG__)  (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
+
+/**
+  * @brief  Clear the CRS specified FLAG.
+  * @param __FLAG__ specifies the flag to clear.
+  *          This parameter can be one of the following values:
+  *              @arg @ref RCC_CRS_FLAG_SYNCOK  SYNC event OK
+  *              @arg @ref RCC_CRS_FLAG_SYNCWARN  SYNC warning
+  *              @arg @ref RCC_CRS_FLAG_ERR  Error
+  *              @arg @ref RCC_CRS_FLAG_ESYNC  Expected SYNC
+  *              @arg @ref RCC_CRS_FLAG_TRIMOVF  Trimming overflow or underflow
+  *              @arg @ref RCC_CRS_FLAG_SYNCERR  SYNC error
+  *              @arg @ref RCC_CRS_FLAG_SYNCMISS  SYNC missed
+  * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR
+  * @retval None
+  */
+
+/* CRS Flag Error Mask */
+#define RCC_CRS_FLAG_ERROR_MASK                ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))
+
+#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__)     do { \
+                                                 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \
+                                                 { \
+                                                   WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
+                                                 } \
+                                                 else \
+                                                 { \
+                                                   WRITE_REG(CRS->ICR, (__FLAG__)); \
+                                                 } \
+                                               } while(0)
+
+ /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
+  * @{
+  */
+/**
+  * @brief  Enable the oscillator clock for frequency error counter.
+  * @note   when the CEN bit is set the CRS_CFGR register becomes write-protected.
+  * @retval None
+  */
+#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE()  SET_BIT(CRS->CR, CRS_CR_CEN)
+
+/**
+  * @brief  Disable the oscillator clock for frequency error counter.
+  * @retval None
+  */
+#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
+
+/**
+  * @brief  Enable the automatic hardware adjustment of TRIM bits.
+  * @note   When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
+  * @retval None
+  */
+#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE()     SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
+
+/**
+  * @brief  Enable or disable the automatic hardware adjustment of TRIM bits.
+  * @retval None
+  */
+#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE()    CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
+
+/**
+  * @brief  Macro to calculate reload value to be set in CRS register according to target and sync frequencies
+  * @note   The RELOAD value should be selected according to the ratio between the target frequency and the frequency
+  *             of the synchronization source after pre-scaling. It is then decreased by one in order to
+  *             reach the expected synchronization on the zero value. The formula is the following:
+  *             RELOAD = (fTARGET / fSYNC) -1
+  * @param  __FTARGET__ Target frequency (value in Hz)
+  * @param  __FSYNC__ Synchronization signal frequency (value in Hz)
+  * @retval None
+  */
+#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)  (((__FTARGET__) / (__FSYNC__)) - 1U)
+
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCCEx_Exported_Functions_Group1
+  * @{
+  */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
+uint32_t HAL_RCCEx_GetD1PCLK1Freq(void);
+uint32_t HAL_RCCEx_GetD3PCLK1Freq(void);
+uint32_t HAL_RCCEx_GetD1SysClockFreq(void);
+void     HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef* PLL1_Clocks);
+void     HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef* PLL2_Clocks);
+void     HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef* PLL3_Clocks);
+/**
+  * @}
+  */
+
+/** @addtogroup RCCEx_Exported_Functions_Group2
+  * @{
+  */
+void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk);
+void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk);
+void HAL_RCCEx_EnableLSECSS(void);
+void HAL_RCCEx_DisableLSECSS(void);
+void HAL_RCCEx_EnableLSECSS_IT(void);
+void HAL_RCCEx_LSECSS_IRQHandler(void);
+void HAL_RCCEx_LSECSS_Callback(void);
+#if defined(DUAL_CORE)
+void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx);
+#endif /*DUAL_CORE*/
+#if defined(RCC_GCR_WW1RSC)
+void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx);
+#endif /*RCC_GCR_WW1RSC*/
+/**
+  * @}
+  */
+
+
+/** @addtogroup RCCEx_Exported_Functions_Group3
+  * @{
+  */
+
+void     HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
+void     HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
+void     HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
+uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
+void     HAL_RCCEx_CRS_IRQHandler(void);
+void     HAL_RCCEx_CRS_SyncOkCallback(void);
+void     HAL_RCCEx_CRS_SyncWarnCallback(void);
+void     HAL_RCCEx_CRS_ExpectedSyncCallback(void);
+void     HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
+
+/**
+  * @}
+  */
+
+ /* Private macros ------------------------------------------------------------*/
+/** @addtogroup RCCEx_Private_Macros RCCEx Private Macros
+  * @{
+  */
+/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
+  * @{
+  */
+
+#define IS_RCC_PLL2CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL2_DIVP) || \
+                                         ((VALUE) == RCC_PLL2_DIVQ)  || \
+                                         ((VALUE) == RCC_PLL2_DIVR))
+
+#define IS_RCC_PLL3CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL3_DIVP) || \
+                                          ((VALUE) == RCC_PLL3_DIVQ) || \
+                                          ((VALUE) == RCC_PLL3_DIVR))
+
+#if defined(RCC_D2CCIP2R_USART16SEL)
+#define IS_RCC_USART16CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART16CLKSOURCE_D2PCLK2)|| \
+                                         ((SOURCE) == RCC_USART16CLKSOURCE_PLL2)   || \
+                                         ((SOURCE) == RCC_USART16CLKSOURCE_PLL3)   || \
+                                         ((SOURCE) == RCC_USART16CLKSOURCE_CSI)    || \
+                                         ((SOURCE) == RCC_USART16CLKSOURCE_LSE)    || \
+                                         ((SOURCE) == RCC_USART16CLKSOURCE_HSI))
+#else
+#define IS_RCC_USART16CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART16CLKSOURCE_D2PCLK2)|| \
+                                         ((SOURCE) == RCC_USART16CLKSOURCE_CDPCLK2)|| \
+                                         ((SOURCE) == RCC_USART16CLKSOURCE_PLL2)   || \
+                                         ((SOURCE) == RCC_USART16CLKSOURCE_PLL3)   || \
+                                         ((SOURCE) == RCC_USART16CLKSOURCE_CSI)    || \
+                                         ((SOURCE) == RCC_USART16CLKSOURCE_LSE)    || \
+                                         ((SOURCE) == RCC_USART16CLKSOURCE_HSI))
+/* alias*/
+#define IS_RCC_USART16910CLKSOURCE    IS_RCC_USART16CLKSOURCE
+#endif /* RCC_D2CCIP2R_USART16SEL */
+
+#if defined(RCC_D2CCIP2R_USART28SEL)
+#define IS_RCC_USART234578CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART234578CLKSOURCE_D2PCLK1)|| \
+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_PLL2)   || \
+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_PLL3)   || \
+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_CSI)    || \
+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_LSE)    || \
+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_HSI))
+#else
+#define IS_RCC_USART234578CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART234578CLKSOURCE_D2PCLK1)|| \
+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_CDPCLK1)|| \
+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_PLL2)   || \
+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_PLL3)   || \
+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_CSI)    || \
+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_LSE)    || \
+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_HSI))
+#endif /* RCC_D2CCIP2R_USART28SEL */
+
+#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_D2PCLK2)|| \
+                                        ((SOURCE) == RCC_USART1CLKSOURCE_PLL2)   || \
+                                        ((SOURCE) == RCC_USART1CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_USART1CLKSOURCE_CSI)    || \
+                                        ((SOURCE) == RCC_USART1CLKSOURCE_LSE)    || \
+                                        ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
+
+#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_D2PCLK1)|| \
+                                        ((SOURCE) == RCC_USART2CLKSOURCE_PLL2)   || \
+                                        ((SOURCE) == RCC_USART2CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_USART2CLKSOURCE_CSI)    || \
+                                        ((SOURCE) == RCC_USART2CLKSOURCE_LSE)    || \
+                                        ((SOURCE) == RCC_USART2CLKSOURCE_HSI))
+
+#define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_D2PCLK1)|| \
+                                        ((SOURCE) == RCC_USART3CLKSOURCE_PLL2)   || \
+                                        ((SOURCE) == RCC_USART3CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_USART3CLKSOURCE_CSI)    || \
+                                        ((SOURCE) == RCC_USART3CLKSOURCE_LSE)    || \
+                                        ((SOURCE) == RCC_USART3CLKSOURCE_HSI))
+
+#define IS_RCC_UART4CLKSOURCE(SOURCE)  (((SOURCE) == RCC_UART4CLKSOURCE_D2PCLK1) || \
+                                        ((SOURCE) == RCC_UART4CLKSOURCE_PLL2)    || \
+                                        ((SOURCE) == RCC_UART4CLKSOURCE_PLL3)    || \
+                                        ((SOURCE) == RCC_UART4CLKSOURCE_CSI)     || \
+                                        ((SOURCE) == RCC_UART4CLKSOURCE_LSE)     || \
+                                        ((SOURCE) == RCC_UART4CLKSOURCE_HSI))
+
+#define IS_RCC_UART5CLKSOURCE(SOURCE)  (((SOURCE) == RCC_UART5CLKSOURCE_D2PCLK1) || \
+                                        ((SOURCE) == RCC_UART5CLKSOURCE_PLL2)    || \
+                                        ((SOURCE) == RCC_UART5CLKSOURCE_PLL3)    || \
+                                        ((SOURCE) == RCC_UART5CLKSOURCE_CSI)     || \
+                                        ((SOURCE) == RCC_UART5CLKSOURCE_LSE)     || \
+                                        ((SOURCE) == RCC_UART5CLKSOURCE_HSI))
+
+#define IS_RCC_USART6CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART6CLKSOURCE_D2PCLK2)|| \
+                                        ((SOURCE) == RCC_USART6CLKSOURCE_PLL2)   || \
+                                        ((SOURCE) == RCC_USART6CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_USART6CLKSOURCE_CSI)    || \
+                                        ((SOURCE) == RCC_USART6CLKSOURCE_LSE)    || \
+                                        ((SOURCE) == RCC_USART6CLKSOURCE_HSI))
+
+#define IS_RCC_UART7CLKSOURCE(SOURCE)  (((SOURCE) == RCC_UART7CLKSOURCE_D2PCLK1) || \
+                                        ((SOURCE) == RCC_UART7CLKSOURCE_PLL2)    || \
+                                        ((SOURCE) == RCC_UART7CLKSOURCE_PLL3)    || \
+                                        ((SOURCE) == RCC_UART7CLKSOURCE_CSI)     || \
+                                        ((SOURCE) == RCC_UART7CLKSOURCE_LSE)     || \
+                                        ((SOURCE) == RCC_UART7CLKSOURCE_HSI))
+
+#define IS_RCC_UART8CLKSOURCE(SOURCE)  (((SOURCE) == RCC_UART8CLKSOURCE_D2PCLK1) || \
+                                        ((SOURCE) == RCC_UART8CLKSOURCE_PLL2)    || \
+                                        ((SOURCE) == RCC_UART8CLKSOURCE_PLL3)    || \
+                                        ((SOURCE) == RCC_UART8CLKSOURCE_CSI)     || \
+                                        ((SOURCE) == RCC_UART8CLKSOURCE_LSE)     || \
+                                        ((SOURCE) == RCC_UART8CLKSOURCE_HSI))
+
+#if defined(UART9)
+#define IS_RCC_UART9CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART9CLKSOURCE_D2PCLK2)|| \
+                                        ((SOURCE) == RCC_UART9CLKSOURCE_PLL2)  || \
+                                        ((SOURCE) == RCC_UART9CLKSOURCE_PLL3)  || \
+                                        ((SOURCE) == RCC_UART9CLKSOURCE_CSI)   || \
+                                        ((SOURCE) == RCC_UART9CLKSOURCE_LSE)   || \
+                                        ((SOURCE) == RCC_UART9CLKSOURCE_HSI))
+#endif
+
+#if defined(USART10)
+#define IS_RCC_USART10CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART10CLKSOURCE_D2PCLK2)|| \
+                                        ((SOURCE) == RCC_USART10CLKSOURCE_PLL2)    || \
+                                        ((SOURCE) == RCC_USART10CLKSOURCE_PLL3)    || \
+                                        ((SOURCE) == RCC_USART10CLKSOURCE_CSI)     || \
+                                        ((SOURCE) == RCC_USART10CLKSOURCE_LSE)     || \
+                                        ((SOURCE) == RCC_USART10CLKSOURCE_HSI))
+#endif
+
+#define IS_RCC_LPUART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPUART1CLKSOURCE_D3PCLK1) || \
+                                         ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL2)    || \
+                                         ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL3)    || \
+                                         ((SOURCE) == RCC_LPUART1CLKSOURCE_CSI)     || \
+                                         ((SOURCE) == RCC_LPUART1CLKSOURCE_LSE)     || \
+                                         ((SOURCE) == RCC_LPUART1CLKSOURCE_HSI))
+
+#define IS_RCC_I2C123CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C123CLKSOURCE_PLL3)   || \
+                                          ((SOURCE) == RCC_I2C123CLKSOURCE_HSI)    || \
+                                          ((SOURCE) == RCC_I2C123CLKSOURCE_D2PCLK1)|| \
+                                          ((SOURCE) == RCC_I2C123CLKSOURCE_CSI))
+
+#define IS_RCC_I2C1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C1CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_I2C1CLKSOURCE_HSI)    || \
+                                        ((SOURCE) == RCC_I2C1CLKSOURCE_D2PCLK1)|| \
+                                        ((SOURCE) == RCC_I2C1CLKSOURCE_CSI))
+
+#define IS_RCC_I2C2CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C2CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_I2C2CLKSOURCE_HSI)    || \
+                                        ((SOURCE) == RCC_I2C2CLKSOURCE_D2PCLK1)|| \
+                                        ((SOURCE) == RCC_I2C2CLKSOURCE_CSI))
+
+#define IS_RCC_I2C3CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C3CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_I2C3CLKSOURCE_HSI)    || \
+                                        ((SOURCE) == RCC_I2C3CLKSOURCE_D2PCLK1)|| \
+                                        ((SOURCE) == RCC_I2C3CLKSOURCE_CSI))
+
+#define IS_RCC_I2C4CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C4CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_I2C4CLKSOURCE_HSI)    || \
+                                        ((SOURCE) == RCC_I2C4CLKSOURCE_D3PCLK1)|| \
+                                        ((SOURCE) == RCC_I2C3CLKSOURCE_CSI))
+
+#define IS_RCC_RNGCLKSOURCE(SOURCE)    (((SOURCE) == RCC_RNGCLKSOURCE_HSI48)|| \
+                                        ((SOURCE) == RCC_RNGCLKSOURCE_PLL)  || \
+                                        ((SOURCE) == RCC_RNGCLKSOURCE_LSE)  || \
+                                        ((SOURCE) == RCC_RNGCLKSOURCE_LSI))
+
+#if defined(HRTIM1)
+#define IS_RCC_HRTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_HRTIM1CLK_TIMCLK) || \
+                                        ((SOURCE) == RCC_HRTIM1CLK_CPUCLK))
+#endif
+
+#define IS_RCC_USBCLKSOURCE(SOURCE)    (((SOURCE) == RCC_USBCLKSOURCE_PLL)  || \
+                                        ((SOURCE) == RCC_USBCLKSOURCE_PLL3) || \
+                                        ((SOURCE) == RCC_USBCLKSOURCE_HSI48))
+
+#define IS_RCC_SAI1CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SAI1CLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))
+
+#if defined(SAI3)
+#define IS_RCC_SAI23CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SAI23CLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SAI23CLKSOURCE_PIN))
+
+#define IS_RCC_SAI2CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SAI2CLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN))
+
+
+#define IS_RCC_SAI3CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SAI3CLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SAI3CLKSOURCE_PIN))
+#endif
+
+#if defined(RCC_CDCCIP1R_SAI2ASEL)
+#define IS_RCC_SAI2ACLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SAI2ACLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PIN) || \
+                ((__SOURCE__) == RCC_SAI2ACLKSOURCE_SPDIF))
+#endif
+
+#if defined(RCC_CDCCIP1R_SAI2BSEL)
+#define IS_RCC_SAI2BCLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SAI2BCLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PIN) || \
+                ((__SOURCE__) == RCC_SAI2BCLKSOURCE_SPDIF))
+#endif
+
+#define IS_RCC_SPI123CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SPI123CLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SPI123CLKSOURCE_PIN))
+
+#define IS_RCC_SPI1CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SPI1CLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SPI1CLKSOURCE_PIN))
+
+#define IS_RCC_SPI2CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SPI2CLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SPI2CLKSOURCE_PIN))
+
+#define IS_RCC_SPI3CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SPI3CLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SPI3CLKSOURCE_PIN))
+
+#define IS_RCC_SPI45CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SPI45CLKSOURCE_D2PCLK1)  || \
+                ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL2)     || \
+                ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL3)     || \
+                ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSI)      || \
+                ((__SOURCE__) == RCC_SPI45CLKSOURCE_CSI)      || \
+                ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSE))
+
+#define IS_RCC_SPI4CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SPI4CLKSOURCE_D2PCLK1)  || \
+                ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL2)     || \
+                ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL3)     || \
+                ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSI)      || \
+                ((__SOURCE__) == RCC_SPI4CLKSOURCE_CSI)      || \
+                ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSE))
+
+#define IS_RCC_SPI5CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SPI5CLKSOURCE_D2PCLK1)|| \
+                ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL2)   || \
+                ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL3)   || \
+                ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSI)    || \
+                ((__SOURCE__) == RCC_SPI5CLKSOURCE_CSI)    || \
+                ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSE))
+
+#if defined(RCC_D3CCIPR_SPI6SEL)
+#define IS_RCC_SPI6CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) || \
+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2)    || \
+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3)    || \
+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI)     || \
+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI)     || \
+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE))
+#else
+#define IS_RCC_SPI6CLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) || \
+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2)    || \
+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3)    || \
+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI)     || \
+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI)     || \
+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE)     || \
+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_PIN))
+#endif /* RCC_D3CCIPR_SPI6SEL */
+
+#if defined(SAI4)
+#define IS_RCC_SAI4ACLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SAI4ACLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PIN))
+
+#define IS_RCC_SAI4BCLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL2) || \
+                ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL3) || \
+                ((__SOURCE__) == RCC_SAI4BCLKSOURCE_CLKP) || \
+                ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PIN))
+#endif /*SAI4*/
+
+#define IS_RCC_PLL3M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))
+#define IS_RCC_PLL3N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))
+#define IS_RCC_PLL3P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
+#define IS_RCC_PLL3Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
+#define IS_RCC_PLL3R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
+
+#define IS_RCC_PLL2M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))
+#define IS_RCC_PLL2N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))
+#define IS_RCC_PLL2P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
+#define IS_RCC_PLL2Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
+#define IS_RCC_PLL2R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
+
+#define IS_RCC_PLL2RGE_VALUE(VALUE) (((VALUE) == RCC_PLL2VCIRANGE_0)  || \
+                                    ((VALUE) == RCC_PLL2VCIRANGE_1)   || \
+                                    ((VALUE) == RCC_PLL2VCIRANGE_2)   || \
+                                    ((VALUE) == RCC_PLL2VCIRANGE_3))
+
+#define IS_RCC_PLL3RGE_VALUE(VALUE) (((VALUE) == RCC_PLL3VCIRANGE_0)  || \
+                                    ((VALUE) == RCC_PLL3VCIRANGE_1)   || \
+                                    ((VALUE) == RCC_PLL3VCIRANGE_2)   || \
+                                    ((VALUE) == RCC_PLL3VCIRANGE_3))
+
+#define IS_RCC_PLL2VCO_VALUE(VALUE) (((VALUE) == RCC_PLL2VCOWIDE)  || \
+                                    ((VALUE) == RCC_PLL2VCOMEDIUM))
+
+#define IS_RCC_PLL3VCO_VALUE(VALUE) (((VALUE) == RCC_PLL3VCOWIDE)  || \
+                                    ((VALUE) == RCC_PLL3VCOMEDIUM))
+
+#define IS_RCC_PLLFRACN_VALUE(VALUE) ((VALUE) <=8191U)
+
+#define IS_RCC_LPTIM1CLK(SOURCE)       (((SOURCE) == RCC_LPTIM1CLKSOURCE_D2PCLK1)|| \
+                                        ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL2)   || \
+                                        ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)    || \
+                                        ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI)    || \
+                                        ((SOURCE) == RCC_LPTIM1CLKSOURCE_CLKP))
+
+#define IS_RCC_LPTIM2CLK(SOURCE)       (((SOURCE) == RCC_LPTIM2CLKSOURCE_D3PCLK1)|| \
+                                        ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL2)   || \
+                                        ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSE)    || \
+                                        ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSI)    || \
+                                        ((SOURCE) == RCC_LPTIM2CLKSOURCE_CLKP))
+
+#define IS_RCC_LPTIM345CLK(SOURCE)     (((SOURCE) == RCC_LPTIM345CLKSOURCE_D3PCLK1)|| \
+                                        ((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL2)   || \
+                                        ((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_LPTIM345CLKSOURCE_LSE)    || \
+                                        ((SOURCE) == RCC_LPTIM345CLKSOURCE_LSI)    || \
+                                        ((SOURCE) == RCC_LPTIM345CLKSOURCE_CLKP))
+
+#define IS_RCC_LPTIM3CLK(SOURCE)       (((SOURCE) == RCC_LPTIM3CLKSOURCE_D3PCLK1)  || \
+                                        ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL2)     || \
+                                        ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL3)     || \
+                                        ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSE)      || \
+                                        ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSI)      || \
+                                        ((SOURCE) == RCC_LPTIM3CLKSOURCE_CLKP))
+
+#if defined(LPTIM4)
+#define IS_RCC_LPTIM4CLK(SOURCE)       (((SOURCE) == RCC_LPTIM4CLKSOURCE_D3PCLK1)|| \
+                                        ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL2)   || \
+                                        ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSE)    || \
+                                        ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSI)    || \
+                                        ((SOURCE) == RCC_LPTIM4CLKSOURCE_CLKP))
+#endif /* LPTIM4*/
+
+#if defined(LPTIM5)
+#define IS_RCC_LPTIM5CLK(SOURCE)       (((SOURCE) == RCC_LPTIM5CLKSOURCE_D3PCLK1)|| \
+                                        ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL2)   || \
+                                        ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL3)   || \
+                                        ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSE)    || \
+                                        ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSI)    || \
+                                        ((SOURCE) == RCC_LPTIM5CLKSOURCE_CLKP))
+#endif /*LPTIM5*/
+
+#if defined(QUADSPI)
+#define IS_RCC_QSPICLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_QSPICLKSOURCE_D1HCLK)  || \
+                ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL)     || \
+                ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL2)    || \
+                ((__SOURCE__) == RCC_QSPICLKSOURCE_CLKP))
+#endif /*QUADSPI*/
+
+#if defined(OCTOSPI1) || defined(OCTOSPI1)
+#define IS_RCC_OSPICLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_OSPICLKSOURCE_D1HCLK)  || \
+                ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL)     || \
+                ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL2)    || \
+                ((__SOURCE__) == RCC_OSPICLKSOURCE_CLKP))
+#endif /*OCTOSPI1 || OCTOSPI1*/
+
+#if defined(DSI)
+#define IS_RCC_DSICLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_DSICLKSOURCE_PHY)  || \
+                ((__SOURCE__) == RCC_DSICLKSOURCE_PLL2))
+#endif /*DSI*/
+
+#define IS_RCC_FMCCLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_FMCCLKSOURCE_D1HCLK)  || \
+                ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL)     || \
+                ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL2)    || \
+                ((__SOURCE__) == RCC_FMCCLKSOURCE_CLKP))
+
+#if defined(FDCAN1) || defined(FDCAN2)
+#define IS_RCC_FDCANCLK(__SOURCE__)   \
+               (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE)  || \
+                ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL2))
+#endif /*FDCAN1 || FDCAN2*/
+
+#define IS_RCC_SDMMC(__SOURCE__)   \
+                (((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL)  || \
+                ((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL2))
+
+#define IS_RCC_ADCCLKSOURCE(SOURCE)    (((SOURCE) == RCC_ADCCLKSOURCE_PLL2) || \
+                                        ((SOURCE) == RCC_ADCCLKSOURCE_PLL3) || \
+                                        ((SOURCE) == RCC_ADCCLKSOURCE_CLKP))
+
+#define IS_RCC_SWPMI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SWPMI1CLKSOURCE_D2PCLK1) || \
+                                        ((SOURCE) == RCC_SWPMI1CLKSOURCE_HSI))
+
+#define IS_RCC_DFSDM1CLKSOURCE(SOURCE)  (((SOURCE) == RCC_DFSDM1CLKSOURCE_D2PCLK1) || \
+                                         ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYS))
+
+#if defined(DFSDM2_BASE)
+#define IS_RCC_DFSDM2CLKSOURCE(SOURCE)  (((SOURCE) == RCC_DFSDM2CLKSOURCE_SRDPCLK1) || \
+                                        ((SOURCE) == RCC_DFSDM2CLKSOURCE_SYS))
+#endif /*DFSDM2*/
+
+#define IS_RCC_SPDIFRXCLKSOURCE(SOURCE)(((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL)  || \
+                                        ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL2) || \
+                                        ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL3) || \
+                                        ((SOURCE) == RCC_SPDIFRXCLKSOURCE_HSI))
+
+#define IS_RCC_CECCLKSOURCE(SOURCE)  (((SOURCE) == RCC_CECCLKSOURCE_LSE) || \
+                                      ((SOURCE) == RCC_CECCLKSOURCE_LSI) || \
+                                      ((SOURCE) == RCC_CECCLKSOURCE_CSI))
+
+#define IS_RCC_CLKPSOURCE(SOURCE)   (((SOURCE) == RCC_CLKPSOURCE_HSI)  || \
+                                      ((SOURCE) == RCC_CLKPSOURCE_CSI) || \
+                                      ((SOURCE) == RCC_CLKPSOURCE_HSE))
+#define IS_RCC_TIMPRES(VALUE)  \
+               (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \
+                ((VALUE) == RCC_TIMPRES_ACTIVATED))
+
+#if defined(DUAL_CORE)
+#define IS_RCC_BOOT_CORE(CORE)   (((CORE) == RCC_BOOT_C1)  || \
+                                  ((CORE) == RCC_BOOT_C2))
+#endif /*DUAL_CORE*/
+
+#if defined(DUAL_CORE)
+#define IS_RCC_SCOPE_WWDG(WWDG)   (((WWDG) == RCC_WWDG1)  || \
+                                  ((WWDG) == RCC_WWDG2))
+#else
+#define IS_RCC_SCOPE_WWDG(WWDG)   ((WWDG) == RCC_WWDG1)
+
+#endif /*DUAL_CORE*/
+
+#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB2) || \
+                                            ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE)  || \
+                                            ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB1) || \
+                                            ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_PIN))
+
+#define IS_RCC_CRS_SYNC_DIV(__DIV__)       (((__DIV__) == RCC_CRS_SYNC_DIV1)  || ((__DIV__) == RCC_CRS_SYNC_DIV2)  || \
+                                            ((__DIV__) == RCC_CRS_SYNC_DIV4)  || ((__DIV__) == RCC_CRS_SYNC_DIV8)  || \
+                                            ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
+                                            ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))
+
+#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
+                                                ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
+
+#define IS_RCC_CRS_RELOADVALUE(__VALUE__)  (((__VALUE__) <= 0xFFFFU))
+
+#define IS_RCC_CRS_ERRORLIMIT(__VALUE__)   (((__VALUE__) <= 0xFFU))
+
+#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))
+
+#define IS_RCC_CRS_FREQERRORDIR(__DIR__)   (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
+                                            ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_RCC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h
new file mode 100644
index 00000000..37a7ada8
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h
@@ -0,0 +1,2285 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_tim.h
+  * @author  MCD Application Team
+  * @brief   Header file of TIM HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_TIM_H
+#define STM32H7xx_HAL_TIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup TIM
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TIM_Exported_Types TIM Exported Types
+  * @{
+  */
+
+/**
+  * @brief  TIM Time base Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
+                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+  uint32_t CounterMode;       /*!< Specifies the counter mode.
+                                   This parameter can be a value of @ref TIM_Counter_Mode */
+
+  uint32_t Period;            /*!< Specifies the period value to be loaded into the active
+                                   Auto-Reload Register at the next update event.
+                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.  */
+
+  uint32_t ClockDivision;     /*!< Specifies the clock division.
+                                   This parameter can be a value of @ref TIM_ClockDivision */
+
+  uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
+                                    reaches zero, an update event is generated and counting restarts
+                                    from the RCR value (N).
+                                    This means in PWM mode that (N+1) corresponds to:
+                                        - the number of PWM periods in edge-aligned mode
+                                        - the number of half PWM period in center-aligned mode
+                                     GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+                                     Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+  uint32_t AutoReloadPreload;  /*!< Specifies the auto-reload preload.
+                                   This parameter can be a value of @ref TIM_AutoReloadPreload */
+} TIM_Base_InitTypeDef;
+
+/**
+  * @brief  TIM Output Compare Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t OCMode;        /*!< Specifies the TIM mode.
+                               This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+  uint32_t OCPolarity;    /*!< Specifies the output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t OCFastMode;    /*!< Specifies the Fast mode state.
+                               This parameter can be a value of @ref TIM_Output_Fast_State
+                               @note This parameter is valid only in PWM1 and PWM2 mode. */
+
+
+  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+                               @note This parameter is valid only for timer instances supporting break feature. */
+} TIM_OC_InitTypeDef;
+
+/**
+  * @brief  TIM One Pulse Mode Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t OCMode;        /*!< Specifies the TIM mode.
+                               This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+  uint32_t OCPolarity;    /*!< Specifies the output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint32_t ICSelection;   /*!< Specifies the input.
+                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t ICFilter;      /*!< Specifies the input capture filter.
+                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_OnePulse_InitTypeDef;
+
+/**
+  * @brief  TIM Input Capture Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t  ICPolarity;  /*!< Specifies the active edge of the input signal.
+                              This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint32_t ICSelection;  /*!< Specifies the input.
+                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
+                              This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t ICFilter;     /*!< Specifies the input capture filter.
+                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_IC_InitTypeDef;
+
+/**
+  * @brief  TIM Encoder Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t EncoderMode;   /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Encoder_Mode */
+
+  uint32_t IC1Polarity;   /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
+
+  uint32_t IC1Selection;  /*!< Specifies the input.
+                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t IC1Prescaler;  /*!< Specifies the Input Capture Prescaler.
+                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t IC1Filter;     /*!< Specifies the input capture filter.
+                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+  uint32_t IC2Polarity;   /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
+
+  uint32_t IC2Selection;  /*!< Specifies the input.
+                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t IC2Prescaler;  /*!< Specifies the Input Capture Prescaler.
+                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t IC2Filter;     /*!< Specifies the input capture filter.
+                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_Encoder_InitTypeDef;
+
+/**
+  * @brief  Clock Configuration Handle Structure definition
+  */
+typedef struct
+{
+  uint32_t ClockSource;     /*!< TIM clock sources
+                                 This parameter can be a value of @ref TIM_Clock_Source */
+  uint32_t ClockPolarity;   /*!< TIM clock polarity
+                                 This parameter can be a value of @ref TIM_Clock_Polarity */
+  uint32_t ClockPrescaler;  /*!< TIM clock prescaler
+                                 This parameter can be a value of @ref TIM_Clock_Prescaler */
+  uint32_t ClockFilter;     /*!< TIM clock filter
+                                 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_ClockConfigTypeDef;
+
+/**
+  * @brief  TIM Clear Input Configuration Handle Structure definition
+  */
+typedef struct
+{
+  uint32_t ClearInputState;      /*!< TIM clear Input state
+                                      This parameter can be ENABLE or DISABLE */
+  uint32_t ClearInputSource;     /*!< TIM clear Input sources
+                                      This parameter can be a value of @ref TIM_ClearInput_Source */
+  uint32_t ClearInputPolarity;   /*!< TIM Clear Input polarity
+                                      This parameter can be a value of @ref TIM_ClearInput_Polarity */
+  uint32_t ClearInputPrescaler;  /*!< TIM Clear Input prescaler
+                                      This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */
+  uint32_t ClearInputFilter;     /*!< TIM Clear Input filter
+                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_ClearInputConfigTypeDef;
+
+/**
+  * @brief  TIM Master configuration Structure definition
+  * @note   Advanced timers provide TRGO2 internal line which is redirected
+  *         to the ADC
+  */
+typedef struct
+{
+  uint32_t  MasterOutputTrigger;   /*!< Trigger output (TRGO) selection
+                                        This parameter can be a value of @ref TIM_Master_Mode_Selection */
+  uint32_t  MasterOutputTrigger2;  /*!< Trigger output2 (TRGO2) selection
+                                        This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */
+  uint32_t  MasterSlaveMode;       /*!< Master/slave mode selection
+                                        This parameter can be a value of @ref TIM_Master_Slave_Mode
+                                        @note When the Master/slave mode is enabled, the effect of
+                                        an event on the trigger input (TRGI) is delayed to allow a
+                                        perfect synchronization between the current timer and its
+                                        slaves (through TRGO). It is not mandatory in case of timer
+                                        synchronization mode. */
+} TIM_MasterConfigTypeDef;
+
+/**
+  * @brief  TIM Slave configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t  SlaveMode;         /*!< Slave mode selection
+                                    This parameter can be a value of @ref TIM_Slave_Mode */
+  uint32_t  InputTrigger;      /*!< Input Trigger source
+                                    This parameter can be a value of @ref TIM_Trigger_Selection */
+  uint32_t  TriggerPolarity;   /*!< Input Trigger polarity
+                                    This parameter can be a value of @ref TIM_Trigger_Polarity */
+  uint32_t  TriggerPrescaler;  /*!< Input trigger prescaler
+                                    This parameter can be a value of @ref TIM_Trigger_Prescaler */
+  uint32_t  TriggerFilter;     /*!< Input trigger filter
+                                    This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF  */
+
+} TIM_SlaveConfigTypeDef;
+
+/**
+  * @brief  TIM Break input(s) and Dead time configuration Structure definition
+  * @note   2 break inputs can be configured (BKIN and BKIN2) with configurable
+  *        filter and polarity.
+  */
+typedef struct
+{
+  uint32_t OffStateRunMode;      /*!< TIM off state in run mode
+                                      This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
+  uint32_t OffStateIDLEMode;     /*!< TIM off state in IDLE mode
+                                      This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
+  uint32_t LockLevel;            /*!< TIM Lock level
+                                      This parameter can be a value of @ref TIM_Lock_level */
+  uint32_t DeadTime;             /*!< TIM dead Time
+                                      This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+  uint32_t BreakState;           /*!< TIM Break State
+                                      This parameter can be a value of @ref TIM_Break_Input_enable_disable */
+  uint32_t BreakPolarity;        /*!< TIM Break input polarity
+                                      This parameter can be a value of @ref TIM_Break_Polarity */
+  uint32_t BreakFilter;          /*!< Specifies the break input filter.
+                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+  uint32_t Break2State;          /*!< TIM Break2 State
+                                      This parameter can be a value of @ref TIM_Break2_Input_enable_disable */
+  uint32_t Break2Polarity;       /*!< TIM Break2 input polarity
+                                      This parameter can be a value of @ref TIM_Break2_Polarity */
+  uint32_t Break2Filter;         /*!< TIM break2 input filter.
+                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+  uint32_t AutomaticOutput;      /*!< TIM Automatic Output Enable state
+                                      This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+} TIM_BreakDeadTimeConfigTypeDef;
+
+/**
+  * @brief  HAL State structures definition
+  */
+typedef enum
+{
+  HAL_TIM_STATE_RESET             = 0x00U,    /*!< Peripheral not yet initialized or disabled  */
+  HAL_TIM_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */
+  HAL_TIM_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */
+  HAL_TIM_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */
+  HAL_TIM_STATE_ERROR             = 0x04U     /*!< Reception process is ongoing                */
+} HAL_TIM_StateTypeDef;
+
+/**
+  * @brief  HAL Active channel structures definition
+  */
+typedef enum
+{
+  HAL_TIM_ACTIVE_CHANNEL_1        = 0x01U,    /*!< The active channel is 1     */
+  HAL_TIM_ACTIVE_CHANNEL_2        = 0x02U,    /*!< The active channel is 2     */
+  HAL_TIM_ACTIVE_CHANNEL_3        = 0x04U,    /*!< The active channel is 3     */
+  HAL_TIM_ACTIVE_CHANNEL_4        = 0x08U,    /*!< The active channel is 4     */
+  HAL_TIM_ACTIVE_CHANNEL_5        = 0x10U,    /*!< The active channel is 5     */
+  HAL_TIM_ACTIVE_CHANNEL_6        = 0x20U,    /*!< The active channel is 6     */
+  HAL_TIM_ACTIVE_CHANNEL_CLEARED  = 0x00U     /*!< All active channels cleared */
+} HAL_TIM_ActiveChannel;
+
+/**
+  * @brief  TIM Time Base Handle Structure definition
+  */
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+typedef struct __TIM_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+{
+  TIM_TypeDef                 *Instance;     /*!< Register base address             */
+  TIM_Base_InitTypeDef        Init;          /*!< TIM Time Base required parameters */
+  HAL_TIM_ActiveChannel       Channel;       /*!< Active channel                    */
+  DMA_HandleTypeDef           *hdma[7];      /*!< DMA Handlers array
+                                                  This array is accessed by a @ref DMA_Handle_index */
+  HAL_LockTypeDef             Lock;          /*!< Locking object                    */
+  __IO HAL_TIM_StateTypeDef   State;         /*!< TIM operation state               */
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM Base Msp Init Callback                              */
+  void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);            /*!< TIM Base Msp DeInit Callback                            */
+  void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM IC Msp Init Callback                                */
+  void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM IC Msp DeInit Callback                              */
+  void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM OC Msp Init Callback                                */
+  void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM OC Msp DeInit Callback                              */
+  void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM PWM Msp Init Callback                               */
+  void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM PWM Msp DeInit Callback                             */
+  void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim);          /*!< TIM One Pulse Msp Init Callback                         */
+  void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM One Pulse Msp DeInit Callback                       */
+  void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Encoder Msp Init Callback                           */
+  void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM Encoder Msp DeInit Callback                         */
+  void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Hall Sensor Msp Init Callback                       */
+  void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);      /*!< TIM Hall Sensor Msp DeInit Callback                     */
+  void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM Period Elapsed Callback                             */
+  void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);     /*!< TIM Period Elapsed half complete Callback               */
+  void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim);                   /*!< TIM Trigger Callback                                    */
+  void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Trigger half complete Callback                      */
+  void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM Input Capture Callback                              */
+  void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Input Capture half complete Callback                */
+  void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Output Compare Delay Elapsed Callback               */
+  void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM PWM Pulse Finished Callback                         */
+  void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback           */
+  void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Error Callback                                      */
+  void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM Commutation Callback                                */
+  void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);       /*!< TIM Commutation half complete Callback                  */
+  void (* BreakCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Break Callback                                      */
+  void (* Break2Callback)(struct __TIM_HandleTypeDef *htim);                    /*!< TIM Break2 Callback                                     */
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+} TIM_HandleTypeDef;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL TIM Callback ID enumeration definition
+  */
+typedef enum
+{
+   HAL_TIM_BASE_MSPINIT_CB_ID            = 0x00U    /*!< TIM Base MspInit Callback ID                              */
+  ,HAL_TIM_BASE_MSPDEINIT_CB_ID          = 0x01U    /*!< TIM Base MspDeInit Callback ID                            */
+  ,HAL_TIM_IC_MSPINIT_CB_ID              = 0x02U    /*!< TIM IC MspInit Callback ID                                */
+  ,HAL_TIM_IC_MSPDEINIT_CB_ID            = 0x03U    /*!< TIM IC MspDeInit Callback ID                              */
+  ,HAL_TIM_OC_MSPINIT_CB_ID              = 0x04U    /*!< TIM OC MspInit Callback ID                                */
+  ,HAL_TIM_OC_MSPDEINIT_CB_ID            = 0x05U    /*!< TIM OC MspDeInit Callback ID                              */
+  ,HAL_TIM_PWM_MSPINIT_CB_ID             = 0x06U    /*!< TIM PWM MspInit Callback ID                               */
+  ,HAL_TIM_PWM_MSPDEINIT_CB_ID           = 0x07U    /*!< TIM PWM MspDeInit Callback ID                             */
+  ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID       = 0x08U    /*!< TIM One Pulse MspInit Callback ID                         */
+  ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID     = 0x09U    /*!< TIM One Pulse MspDeInit Callback ID                       */
+  ,HAL_TIM_ENCODER_MSPINIT_CB_ID         = 0x0AU    /*!< TIM Encoder MspInit Callback ID                           */
+  ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID       = 0x0BU    /*!< TIM Encoder MspDeInit Callback ID                         */
+  ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID     = 0x0CU    /*!< TIM Hall Sensor MspDeInit Callback ID                     */
+  ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID   = 0x0DU    /*!< TIM Hall Sensor MspDeInit Callback ID                     */
+  ,HAL_TIM_PERIOD_ELAPSED_CB_ID          = 0x0EU    /*!< TIM Period Elapsed Callback ID                             */
+  ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID     = 0x0FU    /*!< TIM Period Elapsed half complete Callback ID               */
+  ,HAL_TIM_TRIGGER_CB_ID                 = 0x10U    /*!< TIM Trigger Callback ID                                    */
+  ,HAL_TIM_TRIGGER_HALF_CB_ID            = 0x11U    /*!< TIM Trigger half complete Callback ID                      */
+
+  ,HAL_TIM_IC_CAPTURE_CB_ID              = 0x12U    /*!< TIM Input Capture Callback ID                              */
+  ,HAL_TIM_IC_CAPTURE_HALF_CB_ID         = 0x13U    /*!< TIM Input Capture half complete Callback ID                */
+  ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID        = 0x14U    /*!< TIM Output Compare Delay Elapsed Callback ID               */
+  ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID      = 0x15U    /*!< TIM PWM Pulse Finished Callback ID           */
+  ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U    /*!< TIM PWM Pulse Finished half complete Callback ID           */
+  ,HAL_TIM_ERROR_CB_ID                   = 0x17U    /*!< TIM Error Callback ID                                      */
+  ,HAL_TIM_COMMUTATION_CB_ID             = 0x18U    /*!< TIM Commutation Callback ID                                */
+  ,HAL_TIM_COMMUTATION_HALF_CB_ID        = 0x19U    /*!< TIM Commutation half complete Callback ID                  */
+  ,HAL_TIM_BREAK_CB_ID                   = 0x1AU    /*!< TIM Break Callback ID                                      */
+  ,HAL_TIM_BREAK2_CB_ID                  = 0x1BU    /*!< TIM Break2 Callback ID                                     */
+} HAL_TIM_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL TIM Callback pointer definition
+  */
+typedef  void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);  /*!< pointer to the TIM callback function */
+
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+/* End of exported types -----------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIM_Exported_Constants TIM Exported Constants
+  * @{
+  */
+
+/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
+  * @{
+  */
+#define TIM_CLEARINPUTSOURCE_NONE           0x00000000U   /*!< OCREF_CLR is disabled */
+#define TIM_CLEARINPUTSOURCE_ETR            0x00000001U   /*!< OCREF_CLR is connected to ETRF input */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
+  * @{
+  */
+#define TIM_DMABASE_CR1                    0x00000000U
+#define TIM_DMABASE_CR2                    0x00000001U
+#define TIM_DMABASE_SMCR                   0x00000002U
+#define TIM_DMABASE_DIER                   0x00000003U
+#define TIM_DMABASE_SR                     0x00000004U
+#define TIM_DMABASE_EGR                    0x00000005U
+#define TIM_DMABASE_CCMR1                  0x00000006U
+#define TIM_DMABASE_CCMR2                  0x00000007U
+#define TIM_DMABASE_CCER                   0x00000008U
+#define TIM_DMABASE_CNT                    0x00000009U
+#define TIM_DMABASE_PSC                    0x0000000AU
+#define TIM_DMABASE_ARR                    0x0000000BU
+#define TIM_DMABASE_RCR                    0x0000000CU
+#define TIM_DMABASE_CCR1                   0x0000000DU
+#define TIM_DMABASE_CCR2                   0x0000000EU
+#define TIM_DMABASE_CCR3                   0x0000000FU
+#define TIM_DMABASE_CCR4                   0x00000010U
+#define TIM_DMABASE_BDTR                   0x00000011U
+#define TIM_DMABASE_DCR                    0x00000012U
+#define TIM_DMABASE_DMAR                   0x00000013U
+#define TIM_DMABASE_CCMR3                  0x00000015U
+#define TIM_DMABASE_CCR5                   0x00000016U
+#define TIM_DMABASE_CCR6                   0x00000017U
+#if   defined(TIM_BREAK_INPUT_SUPPORT)
+#define TIM_DMABASE_AF1                    0x00000018U
+#define TIM_DMABASE_AF2                    0x00000019U
+#endif /* TIM_BREAK_INPUT_SUPPORT */
+#define TIM_DMABASE_TISEL                  0x0000001AU
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Event_Source TIM Event Source
+  * @{
+  */
+#define TIM_EVENTSOURCE_UPDATE              TIM_EGR_UG     /*!< Reinitialize the counter and generates an update of the registers */
+#define TIM_EVENTSOURCE_CC1                 TIM_EGR_CC1G   /*!< A capture/compare event is generated on channel 1 */
+#define TIM_EVENTSOURCE_CC2                 TIM_EGR_CC2G   /*!< A capture/compare event is generated on channel 2 */
+#define TIM_EVENTSOURCE_CC3                 TIM_EGR_CC3G   /*!< A capture/compare event is generated on channel 3 */
+#define TIM_EVENTSOURCE_CC4                 TIM_EGR_CC4G   /*!< A capture/compare event is generated on channel 4 */
+#define TIM_EVENTSOURCE_COM                 TIM_EGR_COMG   /*!< A commutation event is generated */
+#define TIM_EVENTSOURCE_TRIGGER             TIM_EGR_TG     /*!< A trigger event is generated */
+#define TIM_EVENTSOURCE_BREAK               TIM_EGR_BG     /*!< A break event is generated */
+#define TIM_EVENTSOURCE_BREAK2              TIM_EGR_B2G    /*!< A break 2 event is generated */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
+  * @{
+  */
+#define  TIM_INPUTCHANNELPOLARITY_RISING      0x00000000U                       /*!< Polarity for TIx source */
+#define  TIM_INPUTCHANNELPOLARITY_FALLING     TIM_CCER_CC1P                     /*!< Polarity for TIx source */
+#define  TIM_INPUTCHANNELPOLARITY_BOTHEDGE    (TIM_CCER_CC1P | TIM_CCER_CC1NP)  /*!< Polarity for TIx source */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
+  * @{
+  */
+#define TIM_ETRPOLARITY_INVERTED              TIM_SMCR_ETP                      /*!< Polarity for ETR source */
+#define TIM_ETRPOLARITY_NONINVERTED           0x00000000U                       /*!< Polarity for ETR source */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
+  * @{
+  */
+#define TIM_ETRPRESCALER_DIV1                 0x00000000U                       /*!< No prescaler is used */
+#define TIM_ETRPRESCALER_DIV2                 TIM_SMCR_ETPS_0                   /*!< ETR input source is divided by 2 */
+#define TIM_ETRPRESCALER_DIV4                 TIM_SMCR_ETPS_1                   /*!< ETR input source is divided by 4 */
+#define TIM_ETRPRESCALER_DIV8                 TIM_SMCR_ETPS                     /*!< ETR input source is divided by 8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Counter_Mode TIM Counter Mode
+  * @{
+  */
+#define TIM_COUNTERMODE_UP                 0x00000000U                          /*!< Counter used as up-counter   */
+#define TIM_COUNTERMODE_DOWN               TIM_CR1_DIR                          /*!< Counter used as down-counter */
+#define TIM_COUNTERMODE_CENTERALIGNED1     TIM_CR1_CMS_0                        /*!< Center-aligned mode 1        */
+#define TIM_COUNTERMODE_CENTERALIGNED2     TIM_CR1_CMS_1                        /*!< Center-aligned mode 2        */
+#define TIM_COUNTERMODE_CENTERALIGNED3     TIM_CR1_CMS                          /*!< Center-aligned mode 3        */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap
+  * @{
+  */
+#define TIM_UIFREMAP_DISABLE               0x00000000U                          /*!< Update interrupt flag remap disabled */
+#define TIM_UIFREMAP_ENABLE                TIM_CR1_UIFREMAP                     /*!< Update interrupt flag remap enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ClockDivision TIM Clock Division
+  * @{
+  */
+#define TIM_CLOCKDIVISION_DIV1             0x00000000U                          /*!< Clock division: tDTS=tCK_INT   */
+#define TIM_CLOCKDIVISION_DIV2             TIM_CR1_CKD_0                        /*!< Clock division: tDTS=2*tCK_INT */
+#define TIM_CLOCKDIVISION_DIV4             TIM_CR1_CKD_1                        /*!< Clock division: tDTS=4*tCK_INT */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_State TIM Output Compare State
+  * @{
+  */
+#define TIM_OUTPUTSTATE_DISABLE            0x00000000U                          /*!< Capture/Compare 1 output disabled */
+#define TIM_OUTPUTSTATE_ENABLE             TIM_CCER_CC1E                        /*!< Capture/Compare 1 output enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
+  * @{
+  */
+#define TIM_AUTORELOAD_PRELOAD_DISABLE                0x00000000U               /*!< TIMx_ARR register is not buffered */
+#define TIM_AUTORELOAD_PRELOAD_ENABLE                 TIM_CR1_ARPE              /*!< TIMx_ARR register is buffered */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Fast_State TIM Output Fast State
+  * @{
+  */
+#define TIM_OCFAST_DISABLE                 0x00000000U                          /*!< Output Compare fast disable */
+#define TIM_OCFAST_ENABLE                  TIM_CCMR1_OC1FE                      /*!< Output Compare fast enable  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
+  * @{
+  */
+#define TIM_OUTPUTNSTATE_DISABLE           0x00000000U                          /*!< OCxN is disabled  */
+#define TIM_OUTPUTNSTATE_ENABLE            TIM_CCER_CC1NE                       /*!< OCxN is enabled   */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
+  * @{
+  */
+#define TIM_OCPOLARITY_HIGH                0x00000000U                          /*!< Capture/Compare output polarity  */
+#define TIM_OCPOLARITY_LOW                 TIM_CCER_CC1P                        /*!< Capture/Compare output polarity  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
+  * @{
+  */
+#define TIM_OCNPOLARITY_HIGH               0x00000000U                          /*!< Capture/Compare complementary output polarity */
+#define TIM_OCNPOLARITY_LOW                TIM_CCER_CC1NP                       /*!< Capture/Compare complementary output polarity */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
+  * @{
+  */
+#define TIM_OCIDLESTATE_SET                TIM_CR2_OIS1                         /*!< Output Idle state: OCx=1 when MOE=0 */
+#define TIM_OCIDLESTATE_RESET              0x00000000U                          /*!< Output Idle state: OCx=0 when MOE=0 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
+  * @{
+  */
+#define TIM_OCNIDLESTATE_SET               TIM_CR2_OIS1N                        /*!< Complementary output Idle state: OCxN=1 when MOE=0 */
+#define TIM_OCNIDLESTATE_RESET             0x00000000U                          /*!< Complementary output Idle state: OCxN=0 when MOE=0 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
+  * @{
+  */
+#define  TIM_ICPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING      /*!< Capture triggered by rising edge on timer input                  */
+#define  TIM_ICPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Capture triggered by falling edge on timer input                 */
+#define  TIM_ICPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE    /*!< Capture triggered by both rising and falling edges on timer input*/
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
+  * @{
+  */
+#define  TIM_ENCODERINPUTPOLARITY_RISING   TIM_INPUTCHANNELPOLARITY_RISING      /*!< Encoder input with rising edge polarity  */
+#define  TIM_ENCODERINPUTPOLARITY_FALLING  TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Encoder input with falling edge polarity */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
+  * @{
+  */
+#define TIM_ICSELECTION_DIRECTTI           TIM_CCMR1_CC1S_0                     /*!< TIM Input 1, 2, 3 or 4 is selected to be
+                                                                                     connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSELECTION_INDIRECTTI         TIM_CCMR1_CC1S_1                     /*!< TIM Input 1, 2, 3 or 4 is selected to be
+                                                                                     connected to IC2, IC1, IC4 or IC3, respectively */
+#define TIM_ICSELECTION_TRC                TIM_CCMR1_CC1S                       /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
+  * @{
+  */
+#define TIM_ICPSC_DIV1                     0x00000000U                          /*!< Capture performed each time an edge is detected on the capture input */
+#define TIM_ICPSC_DIV2                     TIM_CCMR1_IC1PSC_0                   /*!< Capture performed once every 2 events                                */
+#define TIM_ICPSC_DIV4                     TIM_CCMR1_IC1PSC_1                   /*!< Capture performed once every 4 events                                */
+#define TIM_ICPSC_DIV8                     TIM_CCMR1_IC1PSC                     /*!< Capture performed once every 8 events                                */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
+  * @{
+  */
+#define TIM_OPMODE_SINGLE                  TIM_CR1_OPM                          /*!< Counter stops counting at the next update event */
+#define TIM_OPMODE_REPETITIVE              0x00000000U                          /*!< Counter is not stopped at update event          */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
+  * @{
+  */
+#define TIM_ENCODERMODE_TI1                      TIM_SMCR_SMS_0                                                      /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level  */
+#define TIM_ENCODERMODE_TI2                      TIM_SMCR_SMS_1                                                      /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */
+#define TIM_ENCODERMODE_TI12                     (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                                   /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
+  * @{
+  */
+#define TIM_IT_UPDATE                      TIM_DIER_UIE                         /*!< Update interrupt            */
+#define TIM_IT_CC1                         TIM_DIER_CC1IE                       /*!< Capture/Compare 1 interrupt */
+#define TIM_IT_CC2                         TIM_DIER_CC2IE                       /*!< Capture/Compare 2 interrupt */
+#define TIM_IT_CC3                         TIM_DIER_CC3IE                       /*!< Capture/Compare 3 interrupt */
+#define TIM_IT_CC4                         TIM_DIER_CC4IE                       /*!< Capture/Compare 4 interrupt */
+#define TIM_IT_COM                         TIM_DIER_COMIE                       /*!< Commutation interrupt       */
+#define TIM_IT_TRIGGER                     TIM_DIER_TIE                         /*!< Trigger interrupt           */
+#define TIM_IT_BREAK                       TIM_DIER_BIE                         /*!< Break interrupt             */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Commutation_Source  TIM Commutation Source
+  * @{
+  */
+#define TIM_COMMUTATION_TRGI              TIM_CR2_CCUS                          /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */
+#define TIM_COMMUTATION_SOFTWARE          0x00000000U                           /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_DMA_sources TIM DMA Sources
+  * @{
+  */
+#define TIM_DMA_UPDATE                     TIM_DIER_UDE                         /*!< DMA request is triggered by the update event */
+#define TIM_DMA_CC1                        TIM_DIER_CC1DE                       /*!< DMA request is triggered by the capture/compare macth 1 event */
+#define TIM_DMA_CC2                        TIM_DIER_CC2DE                       /*!< DMA request is triggered by the capture/compare macth 2 event event */
+#define TIM_DMA_CC3                        TIM_DIER_CC3DE                       /*!< DMA request is triggered by the capture/compare macth 3 event event */
+#define TIM_DMA_CC4                        TIM_DIER_CC4DE                       /*!< DMA request is triggered by the capture/compare macth 4 event event */
+#define TIM_DMA_COM                        TIM_DIER_COMDE                       /*!< DMA request is triggered by the commutation event */
+#define TIM_DMA_TRIGGER                    TIM_DIER_TDE                         /*!< DMA request is triggered by the trigger event */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Flag_definition TIM Flag Definition
+  * @{
+  */
+#define TIM_FLAG_UPDATE                    TIM_SR_UIF                           /*!< Update interrupt flag         */
+#define TIM_FLAG_CC1                       TIM_SR_CC1IF                         /*!< Capture/Compare 1 interrupt flag */
+#define TIM_FLAG_CC2                       TIM_SR_CC2IF                         /*!< Capture/Compare 2 interrupt flag */
+#define TIM_FLAG_CC3                       TIM_SR_CC3IF                         /*!< Capture/Compare 3 interrupt flag */
+#define TIM_FLAG_CC4                       TIM_SR_CC4IF                         /*!< Capture/Compare 4 interrupt flag */
+#define TIM_FLAG_CC5                       TIM_SR_CC5IF                         /*!< Capture/Compare 5 interrupt flag */
+#define TIM_FLAG_CC6                       TIM_SR_CC6IF                         /*!< Capture/Compare 6 interrupt flag */
+#define TIM_FLAG_COM                       TIM_SR_COMIF                         /*!< Commutation interrupt flag    */
+#define TIM_FLAG_TRIGGER                   TIM_SR_TIF                           /*!< Trigger interrupt flag        */
+#define TIM_FLAG_BREAK                     TIM_SR_BIF                           /*!< Break interrupt flag          */
+#define TIM_FLAG_BREAK2                    TIM_SR_B2IF                          /*!< Break 2 interrupt flag        */
+#define TIM_FLAG_SYSTEM_BREAK              TIM_SR_SBIF                          /*!< System Break interrupt flag   */
+#define TIM_FLAG_CC1OF                     TIM_SR_CC1OF                         /*!< Capture 1 overcapture flag    */
+#define TIM_FLAG_CC2OF                     TIM_SR_CC2OF                         /*!< Capture 2 overcapture flag    */
+#define TIM_FLAG_CC3OF                     TIM_SR_CC3OF                         /*!< Capture 3 overcapture flag    */
+#define TIM_FLAG_CC4OF                     TIM_SR_CC4OF                         /*!< Capture 4 overcapture flag    */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Channel TIM Channel
+  * @{
+  */
+#define TIM_CHANNEL_1                      0x00000000U                          /*!< Capture/compare channel 1 identifier      */
+#define TIM_CHANNEL_2                      0x00000004U                          /*!< Capture/compare channel 2 identifier      */
+#define TIM_CHANNEL_3                      0x00000008U                          /*!< Capture/compare channel 3 identifier      */
+#define TIM_CHANNEL_4                      0x0000000CU                          /*!< Capture/compare channel 4 identifier      */
+#define TIM_CHANNEL_5                      0x00000010U                          /*!< Compare channel 5 identifier              */
+#define TIM_CHANNEL_6                      0x00000014U                          /*!< Compare channel 6 identifier              */
+#define TIM_CHANNEL_ALL                    0x0000003CU                          /*!< Global Capture/compare channel identifier  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Clock_Source TIM Clock Source
+  * @{
+  */
+#define TIM_CLOCKSOURCE_ETRMODE2    TIM_SMCR_ETPS_1      /*!< External clock source mode 2                          */
+#define TIM_CLOCKSOURCE_INTERNAL    TIM_SMCR_ETPS_0      /*!< Internal clock source                                 */
+#define TIM_CLOCKSOURCE_ITR0        TIM_TS_ITR0          /*!< External clock source mode 1 (ITR0)                   */
+#define TIM_CLOCKSOURCE_ITR1        TIM_TS_ITR1          /*!< External clock source mode 1 (ITR1)                   */
+#define TIM_CLOCKSOURCE_ITR2        TIM_TS_ITR2          /*!< External clock source mode 1 (ITR2)                   */
+#define TIM_CLOCKSOURCE_ITR3        TIM_TS_ITR3          /*!< External clock source mode 1 (ITR3)                   */
+#define TIM_CLOCKSOURCE_TI1ED       TIM_TS_TI1F_ED       /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
+#define TIM_CLOCKSOURCE_TI1         TIM_TS_TI1FP1        /*!< External clock source mode 1 (TTI1FP1)                */
+#define TIM_CLOCKSOURCE_TI2         TIM_TS_TI2FP2        /*!< External clock source mode 1 (TTI2FP2)                */
+#define TIM_CLOCKSOURCE_ETRMODE1    TIM_TS_ETRF          /*!< External clock source mode 1 (ETRF)                   */
+#define TIM_CLOCKSOURCE_ITR4        TIM_TS_ITR4          /*!< External clock source mode 1 (ITR4)                   */
+#define TIM_CLOCKSOURCE_ITR5        TIM_TS_ITR5          /*!< External clock source mode 1 (ITR5)                   */
+#define TIM_CLOCKSOURCE_ITR6        TIM_TS_ITR6          /*!< External clock source mode 1 (ITR6)                   */
+#define TIM_CLOCKSOURCE_ITR7        TIM_TS_ITR7          /*!< External clock source mode 1 (ITR7)                   */
+#define TIM_CLOCKSOURCE_ITR8        TIM_TS_ITR8          /*!< External clock source mode 1 (ITR8)                   */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
+  * @{
+  */
+#define TIM_CLOCKPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED           /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED        /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING    /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING   /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE  /*!< Polarity for TIx clock sources */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
+  * @{
+  */
+#define TIM_CLOCKPRESCALER_DIV1                 TIM_ETRPRESCALER_DIV1           /*!< No prescaler is used                                                     */
+#define TIM_CLOCKPRESCALER_DIV2                 TIM_ETRPRESCALER_DIV2           /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
+#define TIM_CLOCKPRESCALER_DIV4                 TIM_ETRPRESCALER_DIV4           /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
+#define TIM_CLOCKPRESCALER_DIV8                 TIM_ETRPRESCALER_DIV8           /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
+  * @{
+  */
+#define TIM_CLEARINPUTPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED      /*!< Polarity for ETRx pin */
+#define TIM_CLEARINPUTPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED   /*!< Polarity for ETRx pin */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
+  * @{
+  */
+#define TIM_CLEARINPUTPRESCALER_DIV1              TIM_ETRPRESCALER_DIV1         /*!< No prescaler is used                                                   */
+#define TIM_CLEARINPUTPRESCALER_DIV2              TIM_ETRPRESCALER_DIV2         /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV4              TIM_ETRPRESCALER_DIV4         /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV8              TIM_ETRPRESCALER_DIV8         /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
+  * @{
+  */
+#define TIM_OSSR_ENABLE                          TIM_BDTR_OSSR                  /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer)           */
+#define TIM_OSSR_DISABLE                         0x00000000U                    /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
+  * @{
+  */
+#define TIM_OSSI_ENABLE                          TIM_BDTR_OSSI                  /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer)           */
+#define TIM_OSSI_DISABLE                         0x00000000U                    /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
+/**
+  * @}
+  */
+/** @defgroup TIM_Lock_level  TIM Lock level
+  * @{
+  */
+#define TIM_LOCKLEVEL_OFF                  0x00000000U                          /*!< LOCK OFF     */
+#define TIM_LOCKLEVEL_1                    TIM_BDTR_LOCK_0                      /*!< LOCK Level 1 */
+#define TIM_LOCKLEVEL_2                    TIM_BDTR_LOCK_1                      /*!< LOCK Level 2 */
+#define TIM_LOCKLEVEL_3                    TIM_BDTR_LOCK                        /*!< LOCK Level 3 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
+  * @{
+  */
+#define TIM_BREAK_ENABLE                   TIM_BDTR_BKE                         /*!< Break input BRK is enabled  */
+#define TIM_BREAK_DISABLE                  0x00000000U                          /*!< Break input BRK is disabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
+  * @{
+  */
+#define TIM_BREAKPOLARITY_LOW              0x00000000U                          /*!< Break input BRK is active low  */
+#define TIM_BREAKPOLARITY_HIGH             TIM_BDTR_BKP                         /*!< Break input BRK is active high */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable
+  * @{
+  */
+#define TIM_BREAK2_DISABLE                 0x00000000U                          /*!< Break input BRK2 is disabled  */
+#define TIM_BREAK2_ENABLE                  TIM_BDTR_BK2E                        /*!< Break input BRK2 is enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity
+  * @{
+  */
+#define TIM_BREAK2POLARITY_LOW             0x00000000U                          /*!< Break input BRK2 is active low   */
+#define TIM_BREAK2POLARITY_HIGH            TIM_BDTR_BK2P                        /*!< Break input BRK2 is active high  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
+  * @{
+  */
+#define TIM_AUTOMATICOUTPUT_DISABLE        0x00000000U                          /*!< MOE can be set only by software */
+#define TIM_AUTOMATICOUTPUT_ENABLE         TIM_BDTR_AOE                         /*!< MOE can be set by software or automatically at the next update event 
+                                                                                    (if none of the break inputs BRK and BRK2 is active) */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3
+  * @{
+  */
+#define TIM_GROUPCH5_NONE                  0x00000000U                          /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
+#define TIM_GROUPCH5_OC1REFC               TIM_CCR5_GC5C1                       /* !< OC1REFC is the logical AND of OC1REFC and OC5REF    */
+#define TIM_GROUPCH5_OC2REFC               TIM_CCR5_GC5C2                       /* !< OC2REFC is the logical AND of OC2REFC and OC5REF    */
+#define TIM_GROUPCH5_OC3REFC               TIM_CCR5_GC5C3                       /* !< OC3REFC is the logical AND of OC3REFC and OC5REF    */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
+  * @{
+  */
+#define TIM_TRGO_RESET            0x00000000U                                      /*!< TIMx_EGR.UG bit is used as trigger output (TRGO)              */
+#define TIM_TRGO_ENABLE           TIM_CR2_MMS_0                                    /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO)             */
+#define TIM_TRGO_UPDATE           TIM_CR2_MMS_1                                    /*!< Update event is used as trigger output (TRGO)                 */
+#define TIM_TRGO_OC1              (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                  /*!< Capture or a compare match 1 is used as trigger output (TRGO) */
+#define TIM_TRGO_OC1REF           TIM_CR2_MMS_2                                    /*!< OC1REF signal is used as trigger output (TRGO)                */
+#define TIM_TRGO_OC2REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                  /*!< OC2REF signal is used as trigger output(TRGO)                 */
+#define TIM_TRGO_OC3REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                  /*!< OC3REF signal is used as trigger output(TRGO)                 */
+#define TIM_TRGO_OC4REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)  /*!< OC4REF signal is used as trigger output(TRGO)                 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2)
+  * @{
+  */
+#define TIM_TRGO2_RESET                          0x00000000U                                                         /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2)              */
+#define TIM_TRGO2_ENABLE                         TIM_CR2_MMS2_0                                                      /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2)             */
+#define TIM_TRGO2_UPDATE                         TIM_CR2_MMS2_1                                                      /*!< Update event is used as trigger output (TRGO2)                 */
+#define TIM_TRGO2_OC1                            (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                                   /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */
+#define TIM_TRGO2_OC1REF                         TIM_CR2_MMS2_2                                                      /*!< OC1REF signal is used as trigger output (TRGO2)                */
+#define TIM_TRGO2_OC2REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                                   /*!< OC2REF signal is used as trigger output (TRGO2)                */
+#define TIM_TRGO2_OC3REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)                                   /*!< OC3REF signal is used as trigger output (TRGO2)                */
+#define TIM_TRGO2_OC4REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC4REF signal is used as trigger output (TRGO2)                */
+#define TIM_TRGO2_OC5REF                         TIM_CR2_MMS2_3                                                      /*!< OC5REF signal is used as trigger output (TRGO2)                */
+#define TIM_TRGO2_OC6REF                         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)                                   /*!< OC6REF signal is used as trigger output (TRGO2)                */
+#define TIM_TRGO2_OC4REF_RISINGFALLING           (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)                                   /*!< OC4REF rising or falling edges generate pulses on TRGO2        */
+#define TIM_TRGO2_OC6REF_RISINGFALLING           (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC6REF rising or falling edges generate pulses on TRGO2        */
+#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)                                   /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2         */
+#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING   (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                  /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */
+#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)                   /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2         */
+#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING   (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2         */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
+  * @{
+  */
+#define TIM_MASTERSLAVEMODE_ENABLE         TIM_SMCR_MSM                         /*!< No action */
+#define TIM_MASTERSLAVEMODE_DISABLE        0x00000000U                          /*!< Master/slave mode is selected */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Slave_Mode TIM Slave mode
+  * @{
+  */
+#define TIM_SLAVEMODE_DISABLE                0x00000000U                                        /*!< Slave mode disabled           */
+#define TIM_SLAVEMODE_RESET                  TIM_SMCR_SMS_2                                     /*!< Reset Mode                    */
+#define TIM_SLAVEMODE_GATED                  (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)                  /*!< Gated Mode                    */
+#define TIM_SLAVEMODE_TRIGGER                (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)                  /*!< Trigger Mode                  */
+#define TIM_SLAVEMODE_EXTERNAL1              (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1         */
+#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER  TIM_SMCR_SMS_3                                     /*!< Combined reset + trigger mode */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
+  * @{
+  */
+#define TIM_OCMODE_TIMING                   0x00000000U                                              /*!< Frozen                                 */
+#define TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!< Set channel to active level on match   */
+#define TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!< Set channel to inactive level on match */
+#define TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!< Toggle                                 */
+#define TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!< PWM mode 1                             */
+#define TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2                             */
+#define TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!< Force active level                     */
+#define TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                         /*!< Force inactive level                   */
+#define TIM_OCMODE_RETRIGERRABLE_OPM1      TIM_CCMR1_OC1M_3                                          /*!< Retrigerrable OPM mode 1               */
+#define TIM_OCMODE_RETRIGERRABLE_OPM2      (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)                     /*!< Retrigerrable OPM mode 2               */
+#define TIM_OCMODE_COMBINED_PWM1           (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)                     /*!< Combined PWM mode 1                    */
+#define TIM_OCMODE_COMBINED_PWM2           (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)  /*!< Combined PWM mode 2                    */
+#define TIM_OCMODE_ASSYMETRIC_PWM1         (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)  /*!< Asymmetric PWM mode 1                  */
+#define TIM_OCMODE_ASSYMETRIC_PWM2         TIM_CCMR1_OC1M                                            /*!< Asymmetric PWM mode 2                  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
+  * @{
+  */
+#define TIM_TS_ITR0          0x00000000U                                                       /*!< Internal Trigger 0 (ITR0)              */
+#define TIM_TS_ITR1          TIM_SMCR_TS_0                                                     /*!< Internal Trigger 1 (ITR1)              */
+#define TIM_TS_ITR2          TIM_SMCR_TS_1                                                     /*!< Internal Trigger 2 (ITR2)              */
+#define TIM_TS_ITR3          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                   /*!< Internal Trigger 3 (ITR3)              */
+#define TIM_TS_TI1F_ED       TIM_SMCR_TS_2                                                     /*!< TI1 Edge Detector (TI1F_ED)            */
+#define TIM_TS_TI1FP1        (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 1 (TI1FP1)        */
+#define TIM_TS_TI2FP2        (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 2 (TI2FP2)        */
+#define TIM_TS_ETRF          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                   /*!< Filtered External Trigger input (ETRF) */
+#define TIM_TS_ITR4          (TIM_SMCR_TS_3)                                                   /*!< Internal Trigger 4 (ITR4)              */
+#define TIM_TS_ITR5          (TIM_SMCR_TS_0 | TIM_SMCR_TS_3)                                   /*!< Internal Trigger 5 (ITR5)              */
+#define TIM_TS_ITR6          (TIM_SMCR_TS_1 | TIM_SMCR_TS_3)                                   /*!< Internal Trigger 6 (ITR6)              */
+#define TIM_TS_ITR7          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3)                   /*!< Internal Trigger 7 (ITR7)              */
+#define TIM_TS_ITR8          (TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                                   /*!< Internal Trigger 8 (ITR8)              */
+#define TIM_TS_ITR9          (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                   /*!< Internal Trigger 9 (ITR9)              */
+#define TIM_TS_ITR10         (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                   /*!< Internal Trigger 10 (ITR10)            */
+#define TIM_TS_ITR11         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)   /*!< Internal Trigger 11 (ITR11)            */
+#define TIM_TS_ITR12         (TIM_SMCR_TS_4)                                                   /*!< Internal Trigger 12 (ITR12)            */
+#define TIM_TS_ITR13         (TIM_SMCR_TS_0 | TIM_SMCR_TS_4)                                   /*!< Internal Trigger 13 (ITR13)            */
+#define TIM_TS_NONE          0x0000FFFFU                                                       /*!< No trigger selected                    */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
+  * @{
+  */
+#define TIM_TRIGGERPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED               /*!< Polarity for ETRx trigger sources             */
+#define TIM_TRIGGERPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED            /*!< Polarity for ETRx trigger sources             */
+#define TIM_TRIGGERPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING        /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING       /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE      /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
+  * @{
+  */
+#define TIM_TRIGGERPRESCALER_DIV1             TIM_ETRPRESCALER_DIV1             /*!< No prescaler is used                                                       */
+#define TIM_TRIGGERPRESCALER_DIV2             TIM_ETRPRESCALER_DIV2             /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
+#define TIM_TRIGGERPRESCALER_DIV4             TIM_ETRPRESCALER_DIV4             /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
+#define TIM_TRIGGERPRESCALER_DIV8             TIM_ETRPRESCALER_DIV8             /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
+  * @{
+  */
+#define TIM_TI1SELECTION_CH1               0x00000000U                          /*!< The TIMx_CH1 pin is connected to TI1 input */
+#define TIM_TI1SELECTION_XORCOMBINATION    TIM_CR2_TI1S                         /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
+  * @{
+  */
+#define TIM_DMABURSTLENGTH_1TRANSFER       0x00000000U                          /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA   */
+#define TIM_DMABURSTLENGTH_2TRANSFERS      0x00000100U                          /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_3TRANSFERS      0x00000200U                          /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_4TRANSFERS      0x00000300U                          /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_5TRANSFERS      0x00000400U                          /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_6TRANSFERS      0x00000500U                          /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_7TRANSFERS      0x00000600U                          /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_8TRANSFERS      0x00000700U                          /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_9TRANSFERS      0x00000800U                          /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_10TRANSFERS     0x00000900U                          /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_11TRANSFERS     0x00000A00U                          /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_12TRANSFERS     0x00000B00U                          /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_13TRANSFERS     0x00000C00U                          /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_14TRANSFERS     0x00000D00U                          /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_15TRANSFERS     0x00000E00U                          /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_16TRANSFERS     0x00000F00U                          /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_17TRANSFERS     0x00001000U                          /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_18TRANSFERS     0x00001100U                          /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Handle_index TIM DMA Handle Index
+  * @{
+  */
+#define TIM_DMA_ID_UPDATE                ((uint16_t) 0x0000)       /*!< Index of the DMA handle used for Update DMA requests */
+#define TIM_DMA_ID_CC1                   ((uint16_t) 0x0001)       /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
+#define TIM_DMA_ID_CC2                   ((uint16_t) 0x0002)       /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
+#define TIM_DMA_ID_CC3                   ((uint16_t) 0x0003)       /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
+#define TIM_DMA_ID_CC4                   ((uint16_t) 0x0004)       /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
+#define TIM_DMA_ID_COMMUTATION           ((uint16_t) 0x0005)       /*!< Index of the DMA handle used for Commutation DMA requests */
+#define TIM_DMA_ID_TRIGGER               ((uint16_t) 0x0006)       /*!< Index of the DMA handle used for Trigger DMA requests */
+/**
+  * @}
+  */
+
+/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
+  * @{
+  */
+#define TIM_CCx_ENABLE                   0x00000001U                            /*!< Input or output channel is enabled */
+#define TIM_CCx_DISABLE                  0x00000000U                            /*!< Input or output channel is disabled */
+#define TIM_CCxN_ENABLE                  0x00000004U                            /*!< Complementary output channel is enabled */
+#define TIM_CCxN_DISABLE                 0x00000000U                            /*!< Complementary output channel is enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Break_System TIM Break System
+  * @{
+  */
+#define TIM_BREAK_SYSTEM_ECC                 SYSCFG_CFGR2_ECCL   /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */
+#define TIM_BREAK_SYSTEM_PVD                 SYSCFG_CFGR2_PVDL   /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */
+#define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR   SYSCFG_CFGR2_SPL    /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17 */
+#define TIM_BREAK_SYSTEM_LOCKUP              SYSCFG_CFGR2_CLL    /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported constants -------------------------------------------------*/
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup TIM_Exported_Macros TIM Exported Macros
+  * @{
+  */
+
+/** @brief  Reset TIM handle state.
+  * @param  __HANDLE__ TIM handle.
+  * @retval None
+  */
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                        \
+                                                      (__HANDLE__)->State             = HAL_TIM_STATE_RESET; \
+                                                      (__HANDLE__)->Base_MspInitCallback         = NULL;     \
+                                                      (__HANDLE__)->Base_MspDeInitCallback       = NULL;     \
+                                                      (__HANDLE__)->IC_MspInitCallback           = NULL;     \
+                                                      (__HANDLE__)->IC_MspDeInitCallback         = NULL;     \
+                                                      (__HANDLE__)->OC_MspInitCallback           = NULL;     \
+                                                      (__HANDLE__)->OC_MspDeInitCallback         = NULL;     \
+                                                      (__HANDLE__)->PWM_MspInitCallback          = NULL;     \
+                                                      (__HANDLE__)->PWM_MspDeInitCallback        = NULL;     \
+                                                      (__HANDLE__)->OnePulse_MspInitCallback     = NULL;     \
+                                                      (__HANDLE__)->OnePulse_MspDeInitCallback   = NULL;     \
+                                                      (__HANDLE__)->Encoder_MspInitCallback      = NULL;     \
+                                                      (__HANDLE__)->Encoder_MspDeInitCallback    = NULL;     \
+                                                      (__HANDLE__)->HallSensor_MspInitCallback   = NULL;     \
+                                                      (__HANDLE__)->HallSensor_MspDeInitCallback = NULL;     \
+                                                     } while(0)
+#else
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @brief  Enable the TIM peripheral.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
+
+/**
+  * @brief  Enable the TIM main Output.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  */
+#define __HAL_TIM_MOE_ENABLE(__HANDLE__)             ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
+
+/**
+  * @brief  Disable the TIM peripheral.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE(__HANDLE__) \
+  do { \
+    if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
+    { \
+      if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
+      { \
+        (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
+      } \
+    } \
+  } while(0)
+
+/**
+  * @brief  Disable the TIM main Output.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
+  */
+#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
+  do { \
+    if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
+    { \
+      if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
+      { \
+        (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
+      } \
+    } \
+  } while(0)
+
+/**
+  * @brief  Disable the TIM main Output.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  * @note The Main Output Enable of a timer instance is disabled unconditionally
+  */
+#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__)  (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
+
+/** @brief  Enable the specified TIM interrupt.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __INTERRUPT__ specifies the TIM interrupt source to enable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_COM:   Commutation interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  *            @arg TIM_IT_BREAK: Break interrupt
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
+
+/** @brief  Disable the specified TIM interrupt.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __INTERRUPT__ specifies the TIM interrupt source to disable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_COM:   Commutation interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  *            @arg TIM_IT_BREAK: Break interrupt
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
+
+/** @brief  Enable the specified DMA request.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __DMA__ specifies the TIM DMA request to enable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: Update DMA request
+  *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
+  *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
+  *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
+  *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
+  *            @arg TIM_DMA_COM:   Commutation DMA request
+  *            @arg TIM_DMA_TRIGGER: Trigger DMA request
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__)         ((__HANDLE__)->Instance->DIER |= (__DMA__))
+
+/** @brief  Disable the specified DMA request.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __DMA__ specifies the TIM DMA request to disable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: Update DMA request
+  *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
+  *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
+  *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
+  *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
+  *            @arg TIM_DMA_COM:   Commutation DMA request
+  *            @arg TIM_DMA_TRIGGER: Trigger DMA request
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__)        ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
+
+/** @brief  Check whether the specified TIM interrupt flag is set or not.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __FLAG__ specifies the TIM interrupt flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg TIM_FLAG_UPDATE: Update interrupt flag
+  *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
+  *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
+  *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
+  *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
+  *            @arg TIM_FLAG_CC5: Compare 5 interrupt flag
+  *            @arg TIM_FLAG_CC6: Compare 6 interrupt flag
+  *            @arg TIM_FLAG_COM:  Commutation interrupt flag
+  *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
+  *            @arg TIM_FLAG_BREAK: Break interrupt flag
+  *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
+  *            @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
+  *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
+  *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
+  *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
+  *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
+
+/** @brief  Clear the specified TIM interrupt flag.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __FLAG__ specifies the TIM interrupt flag to clear.
+  *        This parameter can be one of the following values:
+  *            @arg TIM_FLAG_UPDATE: Update interrupt flag
+  *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
+  *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
+  *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
+  *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
+  *            @arg TIM_FLAG_CC5: Compare 5 interrupt flag
+  *            @arg TIM_FLAG_CC6: Compare 6 interrupt flag
+  *            @arg TIM_FLAG_COM:  Commutation interrupt flag
+  *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
+  *            @arg TIM_FLAG_BREAK: Break interrupt flag
+  *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
+  *            @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
+  *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
+  *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
+  *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
+  *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->SR = ~(__FLAG__))
+
+/**
+  * @brief  Check whether the specified TIM interrupt source is enabled or not.
+  * @param  __HANDLE__ TIM handle
+  * @param  __INTERRUPT__ specifies the TIM interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_COM:   Commutation interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  *            @arg TIM_IT_BREAK: Break interrupt
+  * @retval The state of TIM_IT (SET or RESET).
+  */
+#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
+                                                             == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Clear the TIM interrupt pending bits.
+  * @param  __HANDLE__ TIM handle
+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_COM:   Commutation interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  *            @arg TIM_IT_BREAK: Break interrupt
+  * @retval None
+  */
+#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
+
+/**
+  * @brief  Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
+  * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
+  * @param  __HANDLE__ TIM handle.
+  * @retval None
+mode.
+  */
+#define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__)    (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP))
+
+/**
+  * @brief  Disable update interrupt flag (UIF) remapping.
+  * @param  __HANDLE__ TIM handle.
+  * @retval None
+mode.
+  */
+#define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__)    (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP))
+
+/**
+  * @brief  Get update interrupt flag (UIF) copy status.
+  * @param  __COUNTER__ Counter value.
+  * @retval The state of UIFCPY (TRUE or FALSE).
+mode.
+  */
+#define __HAL_TIM_GET_UIFCPY(__COUNTER__)    (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY))
+
+/**
+  * @brief  Indicates whether or not the TIM Counter is used as downcounter.
+  * @param  __HANDLE__ TIM handle.
+  * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
+  * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
+mode.
+  */
+#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__)    (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
+
+/**
+  * @brief  Set the TIM Prescaler on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __PRESC__ specifies the Prescaler new value.
+  * @retval None
+  */
+#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__)       ((__HANDLE__)->Instance->PSC = (__PRESC__))
+
+/**
+  * @brief  Set the TIM Counter Register value on runtime.
+  * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in case of 32 bits counter TIM instance.
+  *      Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __COUNTER__ specifies the Counter register new value.
+  * @retval None
+  */
+#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__)  ((__HANDLE__)->Instance->CNT = (__COUNTER__))
+
+/**
+  * @brief  Get the TIM Counter Register value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
+  */
+#define __HAL_TIM_GET_COUNTER(__HANDLE__)  ((__HANDLE__)->Instance->CNT)
+
+/**
+  * @brief  Set the TIM Autoreload Register value on runtime without calling another time any Init function.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __AUTORELOAD__ specifies the Counter register new value.
+  * @retval None
+  */
+#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
+  do{                                                    \
+    (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
+    (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
+  } while(0)
+
+/**
+  * @brief  Get the TIM Autoreload Register value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
+  */
+#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__)  ((__HANDLE__)->Instance->ARR)
+
+/**
+  * @brief  Set the TIM Clock Division value on runtime without calling another time any Init function.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CKD__ specifies the clock division value.
+  *          This parameter can be one of the following value:
+  *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
+  * @retval None
+  */
+#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
+  do{                                                   \
+    (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD);  \
+    (__HANDLE__)->Instance->CR1 |= (__CKD__);       \
+    (__HANDLE__)->Init.ClockDivision = (__CKD__);   \
+  } while(0)
+
+/**
+  * @brief  Get the TIM Clock Division value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @retval The clock division can be one of the following values:
+  *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
+  */
+#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__)  ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
+
+/**
+  * @brief  Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  __ICPSC__ specifies the Input Capture4 prescaler new value.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPSC_DIV1: no prescaler
+  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+  * @retval None
+  */
+#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
+  do{                                                    \
+    TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \
+    TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
+  } while(0)
+
+/**
+  * @brief  Get the TIM Input Capture prescaler on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: get input capture 1 prescaler value
+  *            @arg TIM_CHANNEL_2: get input capture 2 prescaler value
+  *            @arg TIM_CHANNEL_3: get input capture 3 prescaler value
+  *            @arg TIM_CHANNEL_4: get input capture 4 prescaler value
+  * @retval The input capture prescaler can be one of the following values:
+  *            @arg TIM_ICPSC_DIV1: no prescaler
+  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+  */
+#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)  \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
+   (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
+
+/**
+  * @brief  Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @param  __COMPARE__ specifies the Capture Compare register new value.
+  * @retval None
+  */
+#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
+   ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
+
+/**
+  * @brief  Get the TIM Capture Compare Register value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channel associated with the capture compare register
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: get capture/compare 1 register value
+  *            @arg TIM_CHANNEL_2: get capture/compare 2 register value
+  *            @arg TIM_CHANNEL_3: get capture/compare 3 register value
+  *            @arg TIM_CHANNEL_4: get capture/compare 4 register value
+  *            @arg TIM_CHANNEL_5: get capture/compare 5 register value
+  *            @arg TIM_CHANNEL_6: get capture/compare 6 register value
+  * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
+  */
+#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
+   ((__HANDLE__)->Instance->CCR6))
+
+/**
+  * @brief  Set the TIM Output compare preload.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
+   ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))
+
+/**
+  * @brief  Reset the TIM Output compare preload.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\
+   ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE))
+
+/**
+  * @brief  Enable fast mode for a given channel.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @note  When fast mode is enabled an active edge on the trigger input acts
+  *        like a compare match on CCx output. Delay to sample the trigger
+  *        input and to activate CCx output is reduced to 3 clock cycles.
+  * @note  Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\
+   ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE))
+
+/**
+  * @brief  Disable fast mode for a given channel.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @note  When fast mode is disabled CCx output behaves normally depending
+  *        on counter and CCRx values even when the trigger is ON. The minimum
+  *        delay to activate CCx output when an active edge occurs on the
+  *        trigger input is 5 clock cycles.
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\
+   ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE))
+
+/**
+  * @brief  Set the Update Request Source (URS) bit of the TIMx_CR1 register.
+  * @param  __HANDLE__ TIM handle.
+  * @note  When the URS bit of the TIMx_CR1 register is set, only counter
+  *        overflow/underflow generates an update interrupt or DMA request (if
+  *        enabled)
+  * @retval None
+  */
+#define __HAL_TIM_URS_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
+
+/**
+  * @brief  Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
+  * @param  __HANDLE__ TIM handle.
+  * @note  When the URS bit of the TIMx_CR1 register is reset, any of the
+  *        following events generate an update interrupt or DMA request (if
+  *        enabled):
+  *           _ Counter overflow underflow
+  *           _ Setting the UG bit
+  *           _ Update generation through the slave mode controller
+  * @retval None
+  */
+#define __HAL_TIM_URS_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
+
+/**
+  * @brief  Set the TIM Capture x input polarity on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  __POLARITY__ Polarity for TIx source
+  *            @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
+  *            @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
+  *            @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
+  * @retval None
+  */
+#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)    \
+  do{                                                                     \
+    TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \
+    TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
+  }while(0)
+
+/**
+  * @}
+  */
+/* End of exported macros ----------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup TIM_Private_Constants TIM Private Constants
+  * @{
+  */
+/* The counter of a timer instance is disabled only if all the CCx and CCxN
+   channels have been disabled */
+#define TIM_CCER_CCxE_MASK  ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
+#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
+/**
+  * @}
+  */
+/* End of private constants --------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TIM_Private_Macros TIM Private Macros
+  * @{
+  */
+#define IS_TIM_CLEARINPUT_SOURCE(__MODE__)  (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)      || \
+                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))
+
+#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1)   || \
+                                   ((__BASE__) == TIM_DMABASE_CR2)   || \
+                                   ((__BASE__) == TIM_DMABASE_SMCR)  || \
+                                   ((__BASE__) == TIM_DMABASE_DIER)  || \
+                                   ((__BASE__) == TIM_DMABASE_SR)    || \
+                                   ((__BASE__) == TIM_DMABASE_EGR)   || \
+                                   ((__BASE__) == TIM_DMABASE_CCMR1) || \
+                                   ((__BASE__) == TIM_DMABASE_CCMR2) || \
+                                   ((__BASE__) == TIM_DMABASE_CCER)  || \
+                                   ((__BASE__) == TIM_DMABASE_CNT)   || \
+                                   ((__BASE__) == TIM_DMABASE_PSC)   || \
+                                   ((__BASE__) == TIM_DMABASE_ARR)   || \
+                                   ((__BASE__) == TIM_DMABASE_RCR)   || \
+                                   ((__BASE__) == TIM_DMABASE_CCR1)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCR2)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCR3)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCR4)  || \
+                                   ((__BASE__) == TIM_DMABASE_BDTR)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCMR3) || \
+                                   ((__BASE__) == TIM_DMABASE_CCR5)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCR6)  || \
+                                   ((__BASE__) == TIM_DMABASE_AF1)   || \
+                                   ((__BASE__) == TIM_DMABASE_AF2)   || \
+                                   ((__BASE__) == TIM_DMABASE_TISEL))
+
+
+#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
+
+#define IS_TIM_COUNTER_MODE(__MODE__)      (((__MODE__) == TIM_COUNTERMODE_UP)              || \
+                                            ((__MODE__) == TIM_COUNTERMODE_DOWN)            || \
+                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
+                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
+                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
+
+#define IS_TIM_UIFREMAP_MODE(__MODE__)     (((__MODE__) == TIM_UIFREMAP_DISABLE) || \
+                                            ((__MODE__) == TIM_UIFREMAP_ENALE))
+
+#define IS_TIM_CLOCKDIVISION_DIV(__DIV__)  (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
+                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
+                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
+
+#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
+                                            ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
+
+#define IS_TIM_FAST_STATE(__STATE__)       (((__STATE__) == TIM_OCFAST_DISABLE) || \
+                                            ((__STATE__) == TIM_OCFAST_ENABLE))
+
+#define IS_TIM_OC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
+                                            ((__POLARITY__) == TIM_OCPOLARITY_LOW))
+
+#define IS_TIM_OCN_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
+                                            ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
+
+#define IS_TIM_OCIDLE_STATE(__STATE__)     (((__STATE__) == TIM_OCIDLESTATE_SET) || \
+                                            ((__STATE__) == TIM_OCIDLESTATE_RESET))
+
+#define IS_TIM_OCNIDLE_STATE(__STATE__)    (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
+                                            ((__STATE__) == TIM_OCNIDLESTATE_RESET))
+
+#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING)   || \
+                                                      ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
+
+#define IS_TIM_IC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ICPOLARITY_RISING)   || \
+                                            ((__POLARITY__) == TIM_ICPOLARITY_FALLING)  || \
+                                            ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
+
+#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
+                                            ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
+                                            ((__SELECTION__) == TIM_ICSELECTION_TRC))
+
+#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
+                                            ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
+                                            ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
+                                            ((__PRESCALER__) == TIM_ICPSC_DIV8))
+
+#define IS_TIM_OPM_MODE(__MODE__)          (((__MODE__) == TIM_OPMODE_SINGLE) || \
+                                            ((__MODE__) == TIM_OPMODE_REPETITIVE))
+
+#define IS_TIM_ENCODER_MODE(__MODE__)      (((__MODE__) == TIM_ENCODERMODE_TI1) || \
+                                            ((__MODE__) == TIM_ENCODERMODE_TI2) || \
+                                            ((__MODE__) == TIM_ENCODERMODE_TI12))
+
+#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
+
+#define IS_TIM_CHANNELS(__CHANNEL__)       (((__CHANNEL__) == TIM_CHANNEL_1) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_2) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_3) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_4) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_5) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_6) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_ALL))
+
+#define IS_TIM_OPM_CHANNELS(__CHANNEL__)   (((__CHANNEL__) == TIM_CHANNEL_1) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_2))
+
+#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
+                                                    ((__CHANNEL__) == TIM_CHANNEL_2) || \
+                                                    ((__CHANNEL__) == TIM_CHANNEL_3))
+
+#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
+
+#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED)    || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING)      || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING)     || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
+
+#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
+                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
+                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
+                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
+
+#define IS_TIM_CLOCKFILTER(__ICFILTER__)      ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
+                                                  ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
+
+#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
+                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
+                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
+                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
+
+#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_OSSR_STATE(__STATE__)       (((__STATE__) == TIM_OSSR_ENABLE) || \
+                                            ((__STATE__) == TIM_OSSR_DISABLE))
+
+#define IS_TIM_OSSI_STATE(__STATE__)       (((__STATE__) == TIM_OSSI_ENABLE) || \
+                                            ((__STATE__) == TIM_OSSI_DISABLE))
+
+#define IS_TIM_LOCK_LEVEL(__LEVEL__)       (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
+                                            ((__LEVEL__) == TIM_LOCKLEVEL_1)   || \
+                                            ((__LEVEL__) == TIM_LOCKLEVEL_2)   || \
+                                            ((__LEVEL__) == TIM_LOCKLEVEL_3))
+
+#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
+
+
+#define IS_TIM_BREAK_STATE(__STATE__)      (((__STATE__) == TIM_BREAK_ENABLE) || \
+                                            ((__STATE__) == TIM_BREAK_DISABLE))
+
+#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
+                                             ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
+
+#define IS_TIM_BREAK2_STATE(__STATE__)     (((__STATE__) == TIM_BREAK2_ENABLE) || \
+                                            ((__STATE__) == TIM_BREAK2_DISABLE))
+
+#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
+                                              ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
+
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
+                                                  ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
+
+#define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))
+
+#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET)  || \
+                                        ((__SOURCE__) == TIM_TRGO_ENABLE) || \
+                                        ((__SOURCE__) == TIM_TRGO_UPDATE) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC1)    || \
+                                        ((__SOURCE__) == TIM_TRGO_OC1REF) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC2REF) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC3REF) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC4REF))
+
+#define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET)                        || \
+                                         ((__SOURCE__) == TIM_TRGO2_ENABLE)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_UPDATE)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC1)                          || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC1REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC2REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC4REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC5REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC6REF)                       || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING)         || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING)         || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING)  || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING)  || \
+                                         ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
+
+#define IS_TIM_MSM_STATE(__STATE__)      (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
+                                          ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
+
+#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE)   || \
+                                     ((__MODE__) == TIM_SLAVEMODE_RESET)     || \
+                                     ((__MODE__) == TIM_SLAVEMODE_GATED)     || \
+                                     ((__MODE__) == TIM_SLAVEMODE_TRIGGER)   || \
+                                     ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \
+                                     ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
+
+#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1)               || \
+                                   ((__MODE__) == TIM_OCMODE_PWM2)               || \
+                                   ((__MODE__) == TIM_OCMODE_COMBINED_PWM1)      || \
+                                   ((__MODE__) == TIM_OCMODE_COMBINED_PWM2)      || \
+                                   ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1)    || \
+                                   ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))
+
+#define IS_TIM_OC_MODE(__MODE__)  (((__MODE__) == TIM_OCMODE_TIMING)             || \
+                                   ((__MODE__) == TIM_OCMODE_ACTIVE)             || \
+                                   ((__MODE__) == TIM_OCMODE_INACTIVE)           || \
+                                   ((__MODE__) == TIM_OCMODE_TOGGLE)             || \
+                                   ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE)      || \
+                                   ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)    || \
+                                   ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
+                                   ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2))
+
+#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR1) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR2) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR3) || \
+                                                 ((__SELECTION__) == TIM_TS_TI1F_ED) || \
+                                                 ((__SELECTION__) == TIM_TS_TI1FP1) || \
+                                                 ((__SELECTION__) == TIM_TS_TI2FP2) || \
+                                                 ((__SELECTION__) == TIM_TS_ETRF) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR4) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR5) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR6) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR7) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR8) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR12) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR13))
+
+#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR1) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR2) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR3) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR4) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR5) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR6) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR7) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR8) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR12) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR13) || \
+                                                               ((__SELECTION__) == TIM_TS_NONE))
+
+#define IS_TIM_TRIGGERPOLARITY(__POLARITY__)   (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING     ) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING    ) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))
+
+#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
+                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
+                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
+                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
+
+#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_TI1SELECTION(__TI1SELECTION__)  (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
+                                                ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
+
+#define IS_TIM_DMA_LENGTH(__LENGTH__)      (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
+
+#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
+
+#define IS_TIM_IC_FILTER(__ICFILTER__)   ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_DEADTIME(__DEADTIME__)    ((__DEADTIME__) <= 0xFFU)
+
+#define IS_TIM_BREAK_SYSTEM(__CONFIG__)    (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC)                  || \
+                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD)                  || \
+                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR)    || \
+                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))
+
+#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \
+                                                       ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
+
+#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
+   ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
+
+#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
+   ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
+
+#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
+   ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
+
+#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
+   ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
+
+/**
+  * @}
+  */
+/* End of private macros -----------------------------------------------------*/
+
+/* Include TIM HAL Extended module */
+#include "stm32h7xx_hal_tim_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIM_Exported_Functions TIM Exported Functions
+  * @{
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
+  *  @brief   Time Base functions
+  * @{
+  */
+/* Time Base functions ********************************************************/
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
+  *  @brief   TIM Output Compare functions
+  * @{
+  */
+/* Timer Output Compare functions *********************************************/
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
+  *  @brief   TIM PWM functions
+  * @{
+  */
+/* Timer PWM functions ********************************************************/
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
+  *  @brief   TIM Input Capture functions
+  * @{
+  */
+/* Timer Input Capture functions **********************************************/
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
+  *  @brief   TIM One Pulse functions
+  * @{
+  */
+/* Timer One Pulse functions **************************************************/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
+  *  @brief   TIM Encoder functions
+  * @{
+  */
+/* Timer Encoder functions ****************************************************/
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef *sConfig);
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
+                                            uint32_t *pData2, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
+  *  @brief   IRQ handler management
+  * @{
+  */
+/* Interrupt Handler functions  ***********************************************/
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
+  *  @brief   Peripheral Control functions
+  * @{
+  */
+/* Control functions  *********************************************************/
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
+                                                 uint32_t OutputChannel,  uint32_t InputChannel);
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,
+                                           uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                              uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                                   uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
+                                                   uint32_t DataLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                             uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                                  uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength,
+                                                  uint32_t  DataLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
+  *  @brief   TIM Callbacks functions
+  * @{
+  */
+/* Callback in non blocking modes (Interrupt and DMA) *************************/
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
+                                           pTIM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
+  *  @brief  Peripheral State functions
+  * @{
+  */
+/* Peripheral State functions  ************************************************/
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private functions----------------------------------------------------------*/
+/** @defgroup TIM_Private_Functions TIM Private Functions
+  * @{
+  */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
+                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
+
+void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMAError(DMA_HandleTypeDef *hdma);
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
+void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+void TIM_ResetCallback(TIM_HandleTypeDef *htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+/* End of private functions --------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_TIM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h
new file mode 100644
index 00000000..0a7ef48a
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h
@@ -0,0 +1,529 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_tim_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of TIM HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_TIM_EX_H
+#define STM32H7xx_HAL_TIM_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup TIMEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
+  * @{
+  */
+
+/**
+  * @brief  TIM Hall sensor Configuration Structure definition
+  */
+
+typedef struct
+{
+  uint32_t IC1Polarity;         /*!< Specifies the active edge of the input signal.
+                                     This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint32_t IC1Prescaler;        /*!< Specifies the Input Capture Prescaler.
+                                     This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t IC1Filter;           /*!< Specifies the input capture filter.
+                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+  uint32_t Commutation_Delay;   /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+                                     This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+} TIM_HallSensor_InitTypeDef;
+#if defined(TIM_BREAK_INPUT_SUPPORT)
+
+/**
+  * @brief  TIM Break/Break2 input configuration
+  */
+typedef struct
+{
+  uint32_t Source;         /*!< Specifies the source of the timer break input.
+                                This parameter can be a value of @ref TIMEx_Break_Input_Source */
+  uint32_t Enable;         /*!< Specifies whether or not the break input source is enabled.
+                                This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */
+  uint32_t Polarity;       /*!< Specifies the break input source polarity.
+                                This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity
+                                Not relevant when analog watchdog output of the DFSDM1 used as break input source */
+}
+TIMEx_BreakInputConfigTypeDef;
+
+#endif /* TIM_BREAK_INPUT_SUPPORT */
+/**
+  * @}
+  */
+/* End of exported types -----------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
+  * @{
+  */
+
+/** @defgroup TIMEx_Remap TIM Extended Remapping
+  * @{
+  */
+#define TIM_TIM1_ETR_GPIO        0x00000000U                                                 /* !< TIM1_ETR is connected to GPIO */
+#define TIM_TIM1_ETR_COMP1       TIM1_AF1_ETRSEL_0                                           /* !< TIM1_ETR is connected to COMP1 OUT */
+#define TIM_TIM1_ETR_COMP2       TIM1_AF1_ETRSEL_1                                           /* !< TIM1_ETR is connected to COMP2 OUT */
+#define TIM_TIM1_ETR_ADC1_AWD1   (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                     /* !< TIM1_ETR is connected to ADC1 AWD1 */
+#define TIM_TIM1_ETR_ADC1_AWD2   (TIM1_AF1_ETRSEL_2)                                         /* !< TIM1_ETR is connected to ADC1 AWD2 */
+#define TIM_TIM1_ETR_ADC1_AWD3   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                     /* !< TIM1_ETR is connected to ADC1 AWD3 */
+#define TIM_TIM1_ETR_ADC3_AWD1   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                     /* !< TIM1_ETR is connected to ADC3 AWD1 */
+#define TIM_TIM1_ETR_ADC3_AWD2   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC3 AWD2 */
+#define TIM_TIM1_ETR_ADC3_AWD3   TIM1_AF1_ETRSEL_3                                           /* !< TIM1_ETR is connected to ADC3 AWD3 */
+
+#define TIM_TIM8_ETR_GPIO        0x00000000U                                                 /* !< TIM8_ETR is connected to GPIO */
+#define TIM_TIM8_ETR_COMP1       TIM8_AF1_ETRSEL_0                                           /* !< TIM8_ETR is connected to COMP1 OUT */
+#define TIM_TIM8_ETR_COMP2       TIM8_AF1_ETRSEL_1                                           /* !< TIM8_ETR is connected to COMP2 OUT */
+#define TIM_TIM8_ETR_ADC2_AWD1   (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)                     /* !< TIM8_ETR is connected to ADC2 AWD1 */
+#define TIM_TIM8_ETR_ADC2_AWD2   (TIM8_AF1_ETRSEL_2)                                         /* !< TIM8_ETR is connected to ADC2 AWD2 */
+#define TIM_TIM8_ETR_ADC2_AWD3   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0)                     /* !< TIM8_ETR is connected to ADC2 AWD3 */
+#define TIM_TIM8_ETR_ADC3_AWD1   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1)                     /* !< TIM8_ETR is connected to ADC3 AWD1 */
+#define TIM_TIM8_ETR_ADC3_AWD2   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC3 AWD2 */
+#define TIM_TIM8_ETR_ADC3_AWD3   TIM8_AF1_ETRSEL_3                                           /* !< TIM8_ETR is connected to ADC3 AWD3 */
+
+#define TIM_TIM2_ETR_GPIO        0x00000000U                             /* !< TIM2_ETR is connected to GPIO */
+#define TIM_TIM2_ETR_COMP1       (TIM2_AF1_ETRSEL_0)                     /* !< TIM2_ETR is connected to COMP1 OUT */
+#define TIM_TIM2_ETR_COMP2       (TIM2_AF1_ETRSEL_1)                     /* !< TIM2_ETR is connected to COMP2 OUT */
+#define TIM_TIM2_ETR_RCC_LSE     (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to RCC LSE */
+#define TIM_TIM2_ETR_SAI1_FSA    TIM2_AF1_ETRSEL_2                       /* !< TIM2_ETR is connected to SAI1 FS_A */
+#define TIM_TIM2_ETR_SAI1_FSB    (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to SAI1 FS_B */
+
+#define TIM_TIM3_ETR_GPIO        0x00000000U          /* !< TIM3_ETR is connected to GPIO */
+#define TIM_TIM3_ETR_COMP1       TIM3_AF1_ETRSEL_0    /* !< TIM3_ETR is connected to COMP1 OUT */
+
+#define TIM_TIM5_ETR_GPIO        0x00000000U          /* !< TIM5_ETR is connected to GPIO */
+#define TIM_TIM5_ETR_SAI2_FSA    TIM5_AF1_ETRSEL_0    /* !< TIM5_ETR is connected to SAI2 FS_A */
+#define TIM_TIM5_ETR_SAI2_FSB    TIM5_AF1_ETRSEL_1    /* !< TIM5_ETR is connected to SAI2 FS_B */
+#define TIM_TIM5_ETR_SAI4_FSA    TIM5_AF1_ETRSEL_0    /* !< TIM5_ETR is connected to SAI4 FS_A */
+#define TIM_TIM5_ETR_SAI4_FSB    TIM5_AF1_ETRSEL_1    /* !< TIM5_ETR is connected to SAI4 FS_B */
+
+#define TIM_TIM23_ETR_GPIO       0x00000000U          /* !< TIM23_ETR is connected to GPIO */
+#define TIM_TIM23_ETR_COMP1      (TIM2_AF1_ETRSEL_0)  /* !< TIM23_ETR is connected to COMP1 OUT */
+#define TIM_TIM23_ETR_COMP2      (TIM2_AF1_ETRSEL_1)  /* !< TIM23_ETR is connected to COMP2 OUT */
+
+#define TIM_TIM24_ETR_GPIO        0x00000000U                                /* !< TIM24_ETR is connected to GPIO */
+#define TIM_TIM24_ETR_SAI4_FSA    TIM5_AF1_ETRSEL_0                          /* !< TIM24_ETR is connected to SAI4 FS_A */
+#define TIM_TIM24_ETR_SAI4_FSB    TIM5_AF1_ETRSEL_1                          /* !< TIM24_ETR is connected to SAI4 FS_B */
+#define TIM_TIM24_ETR_SAI1_FSA    (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)    /* !< TIM24_ETR is connected to SAI1 FS_A */
+#define TIM_TIM24_ETR_SAI1_FSB    TIM2_AF1_ETRSEL_2                          /* !< TIM24_ETR is connected to SAI1 FS_B */
+/**
+  * @}
+  */
+#if defined(TIM_BREAK_INPUT_SUPPORT)
+
+/** @defgroup TIMEx_Break_Input TIM Extended Break input
+  * @{
+  */
+#define TIM_BREAKINPUT_BRK     0x00000001U                                      /* !< Timer break input  */
+#define TIM_BREAKINPUT_BRK2    0x00000002U                                      /* !< Timer break2 input */
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source
+  * @{
+  */
+#define TIM_BREAKINPUTSOURCE_BKIN     0x00000001U                               /* !< An external source (GPIO) is connected to the BKIN pin  */
+#define TIM_BREAKINPUTSOURCE_COMP1    0x00000002U                               /* !< The COMP1 output is connected to the break input */
+#define TIM_BREAKINPUTSOURCE_COMP2    0x00000004U                               /* !< The COMP2 output is connected to the break input */
+#define TIM_BREAKINPUTSOURCE_DFSDM1   0x00000008U                               /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling
+  * @{
+  */
+#define TIM_BREAKINPUTSOURCE_DISABLE     0x00000000U                            /* !< Break input source is disabled */
+#define TIM_BREAKINPUTSOURCE_ENABLE      0x00000001U                            /* !< Break input source is enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity
+  * @{
+  */
+#define TIM_BREAKINPUTSOURCE_POLARITY_LOW     0x00000001U                       /* !< Break input source is active low */
+#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH    0x00000000U                       /* !< Break input source is active_high */
+/**
+  * @}
+  */
+#endif /* TIM_BREAK_INPUT_SUPPORT */
+
+/** @defgroup TIMEx_Timer_Input_Selection TIM Extended Timer input selection
+  * @{
+  */
+#define TIM_TIM1_TI1_GPIO                          0x00000000U                               /* !< TIM1_TI1 is connected to GPIO */
+#define TIM_TIM1_TI1_COMP1                         TIM_TISEL_TI1SEL_0                        /* !< TIM1_TI1 is connected to COMP1 OUT */
+
+#define TIM_TIM8_TI1_GPIO                          0x00000000U                               /* !< TIM8_TI1 is connected to GPIO */
+#define TIM_TIM8_TI1_COMP2                         TIM_TISEL_TI1SEL_0                        /* !< TIM8_TI1 is connected to COMP2 OUT */
+
+#define TIM_TIM2_TI4_GPIO                          0x00000000U                               /* !< TIM2_TI4 is connected to GPIO */
+#define TIM_TIM2_TI4_COMP1                         TIM_TISEL_TI4SEL_0                        /* !< TIM2_TI4 is connected to COMP1 OUT */
+#define TIM_TIM2_TI4_COMP2                         TIM_TISEL_TI4SEL_1                        /* !< TIM2_TI4 is connected to COMP2 OUT */
+#define TIM_TIM2_TI4_COMP1_COMP2                   (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM2_TI4 is connected to COMP2 OUT OR COMP2 OUT */
+
+#define TIM_TIM3_TI1_GPIO                          0x00000000U                               /* !< TIM3_TI1 is connected to GPIO */
+#define TIM_TIM3_TI1_COMP1                         TIM_TISEL_TI1SEL_0                        /* !< TIM3_TI1 is connected to COMP1 OUT */
+#define TIM_TIM3_TI1_COMP2                         TIM_TISEL_TI1SEL_1                        /* !< TIM3_TI1 is connected to COMP2 OUT */
+#define TIM_TIM3_TI1_COMP1_COMP2                   (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM3_TI1 is connected to COMP1 OUT or COMP2 OUT */
+
+#define TIM_TIM5_TI1_GPIO                          0x00000000U                               /* !< TIM5_TI1 is connected to GPIO */
+#define TIM_TIM5_TI1_CAN_TMP                       TIM_TISEL_TI1SEL_0                        /* !< TIM5_TI1 is connected to CAN TMP */
+#define TIM_TIM5_TI1_CAN_RTP                       TIM_TISEL_TI1SEL_1                        /* !< TIM5_TI1 is connected to CAN RTP */
+
+#define TIM_TIM12_TI1_GPIO                         0x00000000U                               /* !< TIM12 TI1 is connected to GPIO */
+#define TIM_TIM12_TI1_SPDIF_FS                     TIM_TISEL_TI1SEL_0                        /* !< TIM12 TI1 is connected to SPDIF FS */
+
+#define TIM_TIM15_TI1_GPIO                         0x00000000U                               /* !< TIM15_TI1 is connected to GPIO */
+#define TIM_TIM15_TI1_TIM2_CH1                     TIM_TISEL_TI1SEL_0                        /* !< TIM15_TI1 is connected to TIM2 CH1 */
+#define TIM_TIM15_TI1_TIM3_CH1                     TIM_TISEL_TI1SEL_1                        /* !< TIM15_TI1 is connected to TIM3 CH1 */
+#define TIM_TIM15_TI1_TIM4_CH1                     (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM15_TI1 is connected to TIM4 CH1 */
+#define TIM_TIM15_TI1_RCC_LSE                      (TIM_TISEL_TI1SEL_2)                      /* !< TIM15_TI1 is connected to RCC LSE  */
+#define TIM_TIM15_TI1_RCC_CSI                      (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /* !< TIM15_TI1 is connected to RCC CSI  */
+#define TIM_TIM15_TI1_RCC_MCO2                     (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /* !< TIM15_TI1 is connected to RCC MCO2 */
+
+#define TIM_TIM15_TI2_GPIO                         0x00000000U                               /* !< TIM15_TI2 is connected to GPIO */
+#define TIM_TIM15_TI2_TIM2_CH2                     (TIM_TISEL_TI2SEL_0)                      /* !< TIM15_TI2 is connected to TIM2 CH2 */
+#define TIM_TIM15_TI2_TIM3_CH2                     (TIM_TISEL_TI2SEL_1)                      /* !< TIM15_TI2 is connected to TIM3 CH2 */
+#define TIM_TIM15_TI2_TIM4_CH2                     (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1) /* !< TIM15_TI2 is connected to TIM4 CH2 */
+
+#define TIM_TIM16_TI1_GPIO                         0x00000000U                               /* !< TIM16 TI1 is connected to GPIO */
+#define TIM_TIM16_TI1_RCC_LSI                      TIM_TISEL_TI1SEL_0                        /* !< TIM16 TI1 is connected to RCC LSI */
+#define TIM_TIM16_TI1_RCC_LSE                      TIM_TISEL_TI1SEL_1                        /* !< TIM16 TI1 is connected to RCC LSE */
+#define TIM_TIM16_TI1_WKUP_IT                      (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM16 TI1 is connected to WKUP_IT */
+
+#define TIM_TIM17_TI1_GPIO                         0x00000000U                               /* !< TIM17 TI1 is connected to GPIO */
+#define TIM_TIM17_TI1_SPDIF_FS                     TIM_TISEL_TI1SEL_0                        /* !< TIM17 TI1 is connected to SPDIF FS */
+#define TIM_TIM17_TI1_RCC_HSE1MHZ                  TIM_TISEL_TI1SEL_1                        /* !< TIM17 TI1 is connected to RCC HSE 1Mhz */
+#define TIM_TIM17_TI1_RCC_MCO1                     (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM17 TI1 is connected to RCC MCO1 */
+
+#define TIM_TIM23_TI4_GPIO                         0x00000000U                               /* !< TIM23_TI4 is connected to GPIO */
+#define TIM_TIM23_TI4_COMP1                        TIM_TISEL_TI4SEL_0                        /* !< TIM23_TI4 is connected to COMP1 OUT */
+#define TIM_TIM23_TI4_COMP2                        TIM_TISEL_TI4SEL_1                        /* !< TIM23_TI4 is connected to COMP2 OUT */
+#define TIM_TIM23_TI4_COMP1_COMP2                  (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM23_TI4 is connected to COMP1 OUT or COMP2 OUT */
+
+#define TIM_TIM24_TI1_GPIO                         0x00000000U                               /* !< TIM24_TI1 is connected to GPIO */
+#define TIM_TIM24_TI1_CAN_TMP                      TIM_TISEL_TI1SEL_0                        /* !< TIM24_TI1 is connected to CAN TMP  */
+#define TIM_TIM24_TI1_CAN_RTP                      TIM_TISEL_TI1SEL_1                        /* !< TIM24_TI1 is connected to CAN RTP  */
+#define TIM_TIM24_TI1_CAN_SOC                      (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM24_TI1 is connected to CAN SOC */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported constants -------------------------------------------------*/
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+/* End of exported macro -----------------------------------------------------*/
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
+  * @{
+  */
+#define IS_TIM_BREAKINPUT(__BREAKINPUT__)  (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK)  || \
+                                            ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
+
+#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__)  (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)  || \
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM1))
+
+#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__)  (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE)  || \
+                                                   ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
+
+#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW)  || \
+                                                         ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
+
+#define IS_TIM_TISEL(__TISEL__)  (((__TISEL__) == TIM_TIM1_TI1_GPIO)         ||\
+                                  ((__TISEL__) == TIM_TIM1_TI1_COMP1)        ||\
+                                  ((__TISEL__) == TIM_TIM8_TI1_GPIO)         ||\
+                                  ((__TISEL__) == TIM_TIM8_TI1_COMP2)        ||\
+                                  ((__TISEL__) == TIM_TIM2_TI4_GPIO)         ||\
+                                  ((__TISEL__) == TIM_TIM2_TI4_COMP1)        ||\
+                                  ((__TISEL__) == TIM_TIM2_TI4_COMP2)        ||\
+                                  ((__TISEL__) == TIM_TIM2_TI4_COMP1_COMP2)  ||\
+                                  ((__TISEL__) == TIM_TIM3_TI1_GPIO)         ||\
+                                  ((__TISEL__) == TIM_TIM3_TI1_COMP1)        ||\
+                                  ((__TISEL__) == TIM_TIM3_TI1_COMP2)        ||\
+                                  ((__TISEL__) == TIM_TIM3_TI1_COMP1_COMP2)  ||\
+                                  ((__TISEL__) == TIM_TIM5_TI1_GPIO)         ||\
+                                  ((__TISEL__) == TIM_TIM5_TI1_CAN_TMP)      ||\
+                                  ((__TISEL__) == TIM_TIM5_TI1_CAN_RTP)      ||\
+                                  ((__TISEL__) == TIM_TIM12_TI1_SPDIF_FS)    ||\
+                                  ((__TISEL__) == TIM_TIM12_TI1_GPIO)        ||\
+                                  ((__TISEL__) == TIM_TIM15_TI1_GPIO)        ||\
+                                  ((__TISEL__) == TIM_TIM15_TI1_TIM2_CH1)    ||\
+                                  ((__TISEL__) == TIM_TIM15_TI1_TIM3_CH1)    ||\
+                                  ((__TISEL__) == TIM_TIM15_TI1_TIM4_CH1)    ||\
+                                  ((__TISEL__) == TIM_TIM15_TI1_RCC_LSE)     ||\
+                                  ((__TISEL__) == TIM_TIM15_TI1_RCC_CSI)     ||\
+                                  ((__TISEL__) == TIM_TIM15_TI1_RCC_MCO2)    ||\
+                                  ((__TISEL__) == TIM_TIM15_TI2_GPIO)        ||\
+                                  ((__TISEL__) == TIM_TIM15_TI2_TIM2_CH2)    ||\
+                                  ((__TISEL__) == TIM_TIM15_TI2_TIM3_CH2)    ||\
+                                  ((__TISEL__) == TIM_TIM15_TI2_TIM4_CH2)    ||\
+                                  ((__TISEL__) == TIM_TIM16_TI1_GPIO)        ||\
+                                  ((__TISEL__) == TIM_TIM16_TI1_RCC_LSI)     ||\
+                                  ((__TISEL__) == TIM_TIM16_TI1_RCC_LSE)     ||\
+                                  ((__TISEL__) == TIM_TIM16_TI1_WKUP_IT)     ||\
+                                  ((__TISEL__) == TIM_TIM17_TI1_GPIO)        ||\
+                                  ((__TISEL__) == TIM_TIM17_TI1_SPDIF_FS)    ||\
+                                  ((__TISEL__) == TIM_TIM17_TI1_RCC_HSE1MHZ) ||\
+                                  ((__TISEL__) == TIM_TIM17_TI1_RCC_MCO1)    ||\
+                                  ((__TISEL__) == TIM_TIM23_TI4_GPIO)        ||\
+                                  ((__TISEL__) == TIM_TIM23_TI4_COMP1)       ||\
+                                  ((__TISEL__) == TIM_TIM23_TI4_COMP2)       ||\
+                                  ((__TISEL__) == TIM_TIM23_TI4_COMP1_COMP2) ||\
+                                  ((__TISEL__) == TIM_TIM24_TI1_GPIO)        ||\
+                                  ((__TISEL__) == TIM_TIM24_TI1_CAN_TMP)     ||\
+                                  ((__TISEL__) == TIM_TIM24_TI1_CAN_RTP)     ||\
+                                  ((__TISEL__) == TIM_TIM24_TI1_CAN_SOC))
+
+#define IS_TIM_REMAP(__RREMAP__)     (((__RREMAP__) == TIM_TIM1_ETR_GPIO)      ||\
+                                      ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD1) ||\
+                                      ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD2) ||\
+                                      ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD3) ||\
+                                      ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD1) ||\
+                                      ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD2) ||\
+                                      ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD3) ||\
+                                      ((__RREMAP__) == TIM_TIM1_ETR_COMP1)     ||\
+                                      ((__RREMAP__) == TIM_TIM1_ETR_COMP2)     ||\
+                                      ((__RREMAP__) == TIM_TIM8_ETR_GPIO)      ||\
+                                      ((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD1) ||\
+                                      ((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD2) ||\
+                                      ((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD3) ||\
+                                      ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD1) ||\
+                                      ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD2) ||\
+                                      ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD3) ||\
+                                      ((__RREMAP__) == TIM_TIM8_ETR_COMP1)     ||\
+                                      ((__RREMAP__) == TIM_TIM8_ETR_COMP2)     ||\
+                                      ((__RREMAP__) == TIM_TIM2_ETR_GPIO)      ||\
+                                      ((__RREMAP__) == TIM_TIM2_ETR_COMP1)     ||\
+                                      ((__RREMAP__) == TIM_TIM2_ETR_COMP2)     ||\
+                                      ((__RREMAP__) == TIM_TIM2_ETR_RCC_LSE)   ||\
+                                      ((__RREMAP__) == TIM_TIM2_ETR_SAI1_FSA)  ||\
+                                      ((__RREMAP__) == TIM_TIM2_ETR_SAI1_FSB)  ||\
+                                      ((__RREMAP__) == TIM_TIM3_ETR_GPIO)      ||\
+                                      ((__RREMAP__) == TIM_TIM3_ETR_COMP1)     ||\
+                                      ((__RREMAP__) == TIM_TIM5_ETR_GPIO)      ||\
+                                      ((__RREMAP__) == TIM_TIM5_ETR_SAI2_FSA)  ||\
+                                      ((__RREMAP__) == TIM_TIM5_ETR_SAI2_FSB)  ||\
+                                      ((__RREMAP__) == TIM_TIM23_ETR_GPIO)     ||\
+                                      ((__RREMAP__) == TIM_TIM23_ETR_COMP1)    ||\
+                                      ((__RREMAP__) == TIM_TIM23_ETR_COMP2)    ||\
+                                      ((__RREMAP__) == TIM_TIM24_ETR_GPIO)     ||\
+                                      ((__RREMAP__) == TIM_TIM24_ETR_SAI4_FSA) ||\
+                                      ((__RREMAP__) == TIM_TIM24_ETR_SAI4_FSB) ||\
+                                      ((__RREMAP__) == TIM_TIM24_ETR_SAI1_FSA) ||\
+                                      ((__RREMAP__) == TIM_TIM24_ETR_SAI1_FSB))
+
+/**
+  * @}
+  */
+/* End of private macro ------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
+  * @{
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
+  *  @brief    Timer Hall Sensor functions
+  * @{
+  */
+/*  Timer Hall Sensor functions  **********************************************/
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
+
+void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
+
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
+  *  @brief   Timer Complementary Output Compare functions
+  * @{
+  */
+/*  Timer Complementary Output Compare functions  *****************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
+  *  @brief    Timer Complementary PWM functions
+  * @{
+  */
+/*  Timer Complementary PWM functions  ****************************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
+  *  @brief    Timer Complementary One Pulse functions
+  * @{
+  */
+/*  Timer Complementary One Pulse functions  **********************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
+  *  @brief    Peripheral Control functions
+  * @{
+  */
+/* Extended Control functions  ************************************************/
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                              uint32_t  CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                                 uint32_t  CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                                  uint32_t  CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+                                                        TIM_MasterConfigTypeDef *sMasterConfig);
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
+                                                TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
+#if defined(TIM_BREAK_INPUT_SUPPORT)
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput,
+                                             TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
+#endif /* TIM_BREAK_INPUT_SUPPORT */
+HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
+HAL_StatusTypeDef  HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
+  * @brief    Extended Callbacks functions
+  * @{
+  */
+/* Extended Callback **********************************************************/
+void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
+  * @brief    Extended Peripheral State functions
+  * @{
+  */
+/* Extended Peripheral State functions  ***************************************/
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private functions----------------------------------------------------------*/
+/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions
+  * @{
+  */
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
+void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+/* End of private functions --------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32H7xx_HAL_TIM_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h
new file mode 100644
index 00000000..48eb8db3
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h
@@ -0,0 +1,1649 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_uart.h
+  * @author  MCD Application Team
+  * @brief   Header file of UART HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_UART_H
+#define STM32H7xx_HAL_UART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup UART
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UART_Exported_Types UART Exported Types
+  * @{
+  */
+
+/**
+  * @brief UART Init Structure definition
+  */
+typedef struct
+{
+  uint32_t BaudRate;                  /*!< This member configures the UART communication baud rate.
+                                           The baud rate register is computed using the following formula:
+                                           LPUART:
+                                           =======
+                                              Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate)))
+                                           where lpuart_ker_ck_pres is the UART input clock divided by a prescaler
+                                           UART:
+                                           =====
+                                           - If oversampling is 16 or in LIN mode,
+                                              Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate)))
+                                           - If oversampling is 8,
+                                              Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[15:4]
+                                              Baud Rate Register[3] =  0
+                                              Baud Rate Register[2:0] =  (((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[3:0]) >> 1
+                                           where uart_ker_ck_pres is the UART input clock divided by a prescaler */
+
+  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter can be a value of @ref UARTEx_Word_Length. */
+
+  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
+                                           This parameter can be a value of @ref UART_Stop_Bits. */
+
+  uint32_t Parity;                    /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref UART_Parity
+                                           @note When parity is enabled, the computed parity is inserted
+                                                 at the MSB position of the transmitted data (9th bit when
+                                                 the word length is set to 9 data bits; 8th bit when the
+                                                 word length is set to 8 data bits). */
+
+  uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref UART_Mode. */
+
+  uint32_t HwFlowCtl;                 /*!< Specifies whether the hardware flow control mode is enabled
+                                           or disabled.
+                                           This parameter can be a value of @ref UART_Hardware_Flow_Control. */
+
+  uint32_t OverSampling;              /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8).
+                                           This parameter can be a value of @ref UART_Over_Sampling. */
+
+  uint32_t OneBitSampling;            /*!< Specifies whether a single sample or three samples' majority vote is selected.
+                                           Selecting the single sample method increases the receiver tolerance to clock
+                                           deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */
+
+  uint32_t ClockPrescaler;            /*!< Specifies the prescaler value used to divide the UART clock source.
+                                           This parameter can be a value of @ref UART_ClockPrescaler. */
+
+} UART_InitTypeDef;
+
+/**
+  * @brief  UART Advanced Features initialization structure definition
+  */
+typedef struct
+{
+  uint32_t AdvFeatureInit;        /*!< Specifies which advanced UART features is initialized. Several
+                                       Advanced Features may be initialized at the same time .
+                                       This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type. */
+
+  uint32_t TxPinLevelInvert;      /*!< Specifies whether the TX pin active level is inverted.
+                                       This parameter can be a value of @ref UART_Tx_Inv. */
+
+  uint32_t RxPinLevelInvert;      /*!< Specifies whether the RX pin active level is inverted.
+                                       This parameter can be a value of @ref UART_Rx_Inv. */
+
+  uint32_t DataInvert;            /*!< Specifies whether data are inverted (positive/direct logic
+                                       vs negative/inverted logic).
+                                       This parameter can be a value of @ref UART_Data_Inv. */
+
+  uint32_t Swap;                  /*!< Specifies whether TX and RX pins are swapped.
+                                       This parameter can be a value of @ref UART_Rx_Tx_Swap. */
+
+  uint32_t OverrunDisable;        /*!< Specifies whether the reception overrun detection is disabled.
+                                       This parameter can be a value of @ref UART_Overrun_Disable. */
+
+  uint32_t DMADisableonRxError;   /*!< Specifies whether the DMA is disabled in case of reception error.
+                                       This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */
+
+  uint32_t AutoBaudRateEnable;    /*!< Specifies whether auto Baud rate detection is enabled.
+                                       This parameter can be a value of @ref UART_AutoBaudRate_Enable. */
+
+  uint32_t AutoBaudRateMode;      /*!< If auto Baud rate detection is enabled, specifies how the rate
+                                       detection is carried out.
+                                       This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */
+
+  uint32_t MSBFirst;              /*!< Specifies whether MSB is sent first on UART line.
+                                       This parameter can be a value of @ref UART_MSB_First. */
+} UART_AdvFeatureInitTypeDef;
+
+/**
+  * @brief HAL UART State definition
+  * @note  HAL UART State value is a combination of 2 different substates: gState and RxState (see @ref UART_State_Definition).
+  *        - gState contains UART state information related to global Handle management
+  *          and also information related to Tx operations.
+  *          gState value coding follow below described bitmap :
+  *          b7-b6  Error information
+  *             00 : No Error
+  *             01 : (Not Used)
+  *             10 : Timeout
+  *             11 : Error
+  *          b5     Peripheral initialization status
+  *             0  : Reset (Peripheral not initialized)
+  *             1  : Init done (Peripheral not initialized. HAL UART Init function already called)
+  *          b4-b3  (not used)
+  *             xx : Should be set to 00
+  *          b2     Intrinsic process state
+  *             0  : Ready
+  *             1  : Busy (Peripheral busy with some configuration or internal operations)
+  *          b1     (not used)
+  *             x  : Should be set to 0
+  *          b0     Tx state
+  *             0  : Ready (no Tx operation ongoing)
+  *             1  : Busy (Tx operation ongoing)
+  *        - RxState contains information related to Rx operations.
+  *          RxState value coding follow below described bitmap :
+  *          b7-b6  (not used)
+  *             xx : Should be set to 00
+  *          b5     Peripheral initialization status
+  *             0  : Reset (Peripheral not initialized)
+  *             1  : Init done (Peripheral not initialized)
+  *          b4-b2  (not used)
+  *            xxx : Should be set to 000
+  *          b1     Rx state
+  *             0  : Ready (no Rx operation ongoing)
+  *             1  : Busy (Rx operation ongoing)
+  *          b0     (not used)
+  *             x  : Should be set to 0.
+  */
+typedef uint32_t HAL_UART_StateTypeDef;
+
+/**
+  * @brief UART clock sources definition
+  */
+typedef enum
+{
+  UART_CLOCKSOURCE_D2PCLK1    = 0x00U,    /*!< Domain2 PCLK1 clock source */
+  UART_CLOCKSOURCE_D2PCLK2    = 0x01U,    /*!< Domain2 PCLK2 clock source */
+  UART_CLOCKSOURCE_D3PCLK1    = 0x02U,    /*!< Domain3 PCLK1 clock source */
+  UART_CLOCKSOURCE_PLL2       = 0x04U,    /*!< PLL2Q clock source         */
+  UART_CLOCKSOURCE_PLL3       = 0x08U,    /*!< PLL3Q clock source         */
+  UART_CLOCKSOURCE_HSI        = 0x10U,    /*!< HSI clock source           */
+  UART_CLOCKSOURCE_CSI        = 0x20U,    /*!< CSI clock source           */
+  UART_CLOCKSOURCE_LSE        = 0x40U,    /*!< LSE clock source           */
+  UART_CLOCKSOURCE_UNDEFINED  = 0x80U     /*!< Undefined clock source     */
+} UART_ClockSourceTypeDef;
+
+/**
+  * @brief  UART handle Structure definition
+  */
+typedef struct __UART_HandleTypeDef
+{
+  USART_TypeDef            *Instance;                /*!< UART registers base address        */
+
+  UART_InitTypeDef         Init;                     /*!< UART communication parameters      */
+
+  UART_AdvFeatureInitTypeDef AdvancedInit;           /*!< UART Advanced Features initialization parameters */
+
+  uint8_t                  *pTxBuffPtr;              /*!< Pointer to UART Tx transfer Buffer */
+
+  uint16_t                 TxXferSize;               /*!< UART Tx Transfer size              */
+
+  __IO uint16_t            TxXferCount;              /*!< UART Tx Transfer Counter           */
+
+  uint8_t                  *pRxBuffPtr;              /*!< Pointer to UART Rx transfer Buffer */
+
+  uint16_t                 RxXferSize;               /*!< UART Rx Transfer size              */
+
+  __IO uint16_t            RxXferCount;              /*!< UART Rx Transfer Counter           */
+
+  uint16_t                 Mask;                     /*!< UART Rx RDR register mask          */
+
+  uint32_t                 FifoMode;                 /*!< Specifies if the FIFO mode is being used.
+                                                          This parameter can be a value of @ref UARTEx_FIFO_mode. */
+
+  uint16_t                 NbRxDataToProcess;        /*!< Number of data to process during RX ISR execution */
+
+  uint16_t                 NbTxDataToProcess;        /*!< Number of data to process during TX ISR execution */
+
+  void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
+
+  void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */
+
+  DMA_HandleTypeDef        *hdmatx;                  /*!< UART Tx DMA Handle parameters      */
+
+  DMA_HandleTypeDef        *hdmarx;                  /*!< UART Rx DMA Handle parameters      */
+
+  HAL_LockTypeDef           Lock;                    /*!< Locking object                     */
+
+  __IO HAL_UART_StateTypeDef    gState;              /*!< UART state information related to global Handle management
+                                                          and also related to Tx operations.
+                                                          This parameter can be a value of @ref HAL_UART_StateTypeDef */
+
+  __IO HAL_UART_StateTypeDef    RxState;             /*!< UART state information related to Rx operations.
+                                                          This parameter can be a value of @ref HAL_UART_StateTypeDef */
+
+  __IO uint32_t                 ErrorCode;           /*!< UART Error code                    */
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Tx Half Complete Callback        */
+  void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Tx Complete Callback             */
+  void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Rx Half Complete Callback        */
+  void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Rx Complete Callback             */
+  void (* ErrorCallback)(struct __UART_HandleTypeDef *huart);             /*!< UART Error Callback                   */
+  void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart);         /*!< UART Abort Complete Callback          */
+  void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */
+  void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart);  /*!< UART Abort Receive Complete Callback  */
+  void (* WakeupCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Wakeup Callback                  */
+  void (* RxFifoFullCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Rx Fifo Full Callback            */
+  void (* TxFifoEmptyCallback)(struct __UART_HandleTypeDef *huart);       /*!< UART Tx Fifo Empty Callback           */
+
+  void (* MspInitCallback)(struct __UART_HandleTypeDef *huart);           /*!< UART Msp Init callback                */
+  void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart);         /*!< UART Msp DeInit callback              */
+#endif  /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+} UART_HandleTypeDef;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL UART Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_UART_TX_HALFCOMPLETE_CB_ID         = 0x00U,    /*!< UART Tx Half Complete Callback ID        */
+  HAL_UART_TX_COMPLETE_CB_ID             = 0x01U,    /*!< UART Tx Complete Callback ID             */
+  HAL_UART_RX_HALFCOMPLETE_CB_ID         = 0x02U,    /*!< UART Rx Half Complete Callback ID        */
+  HAL_UART_RX_COMPLETE_CB_ID             = 0x03U,    /*!< UART Rx Complete Callback ID             */
+  HAL_UART_ERROR_CB_ID                   = 0x04U,    /*!< UART Error Callback ID                   */
+  HAL_UART_ABORT_COMPLETE_CB_ID          = 0x05U,    /*!< UART Abort Complete Callback ID          */
+  HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U,    /*!< UART Abort Transmit Complete Callback ID */
+  HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID  = 0x07U,    /*!< UART Abort Receive Complete Callback ID  */
+  HAL_UART_WAKEUP_CB_ID                  = 0x08U,    /*!< UART Wakeup Callback ID                  */
+  HAL_UART_RX_FIFO_FULL_CB_ID            = 0x09U,    /*!< UART Rx Fifo Full Callback ID            */
+  HAL_UART_TX_FIFO_EMPTY_CB_ID           = 0x0AU,    /*!< UART Tx Fifo Empty Callback ID           */
+
+  HAL_UART_MSPINIT_CB_ID                 = 0x0BU,    /*!< UART MspInit callback ID                 */
+  HAL_UART_MSPDEINIT_CB_ID               = 0x0CU     /*!< UART MspDeInit callback ID               */
+
+} HAL_UART_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL UART Callback pointer definition
+  */
+typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart);  /*!< pointer to an UART callback function */
+
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UART_Exported_Constants UART Exported Constants
+  * @{
+  */
+
+/** @defgroup UART_State_Definition UART State Code Definition
+  * @{
+  */
+#define  HAL_UART_STATE_RESET         0x00000000U    /*!< Peripheral is not initialized
+                                                          Value is allowed for gState and RxState */
+#define  HAL_UART_STATE_READY         0x00000020U    /*!< Peripheral Initialized and ready for use
+                                                          Value is allowed for gState and RxState */
+#define  HAL_UART_STATE_BUSY          0x00000024U    /*!< an internal process is ongoing
+                                                          Value is allowed for gState only */
+#define  HAL_UART_STATE_BUSY_TX       0x00000021U    /*!< Data Transmission process is ongoing
+                                                          Value is allowed for gState only */
+#define  HAL_UART_STATE_BUSY_RX       0x00000022U    /*!< Data Reception process is ongoing
+                                                          Value is allowed for RxState only */
+#define  HAL_UART_STATE_BUSY_TX_RX    0x00000023U    /*!< Data Transmission and Reception process is ongoing
+                                                          Not to be used for neither gState nor RxState.
+                                                          Value is result of combination (Or) between gState and RxState values */
+#define  HAL_UART_STATE_TIMEOUT       0x000000A0U    /*!< Timeout state
+                                                          Value is allowed for gState only */
+#define  HAL_UART_STATE_ERROR         0x000000E0U    /*!< Error
+                                                          Value is allowed for gState only */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Error_Definition   UART Error Definition
+  * @{
+  */
+#define  HAL_UART_ERROR_NONE             ((uint32_t)0x00000000U)    /*!< No error                */
+#define  HAL_UART_ERROR_PE               ((uint32_t)0x00000001U)    /*!< Parity error            */
+#define  HAL_UART_ERROR_NE               ((uint32_t)0x00000002U)    /*!< Noise error             */
+#define  HAL_UART_ERROR_FE               ((uint32_t)0x00000004U)    /*!< Frame error             */
+#define  HAL_UART_ERROR_ORE              ((uint32_t)0x00000008U)    /*!< Overrun error           */
+#define  HAL_UART_ERROR_DMA              ((uint32_t)0x00000010U)    /*!< DMA transfer error      */
+#define  HAL_UART_ERROR_RTO              ((uint32_t)0x00000020U)    /*!< Receiver Timeout error  */
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+#define  HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U)    /*!< Invalid Callback error  */
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Stop_Bits   UART Number of Stop Bits
+  * @{
+  */
+#define UART_STOPBITS_0_5                    USART_CR2_STOP_0                     /*!< UART frame with 0.5 stop bit  */
+#define UART_STOPBITS_1                     0x00000000U                           /*!< UART frame with 1 stop bit    */
+#define UART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */
+#define UART_STOPBITS_2                      USART_CR2_STOP_1                     /*!< UART frame with 2 stop bits   */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Parity  UART Parity
+  * @{
+  */
+#define UART_PARITY_NONE                    0x00000000U                        /*!< No parity   */
+#define UART_PARITY_EVEN                    USART_CR1_PCE                      /*!< Even parity */
+#define UART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)     /*!< Odd parity  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
+  * @{
+  */
+#define UART_HWCONTROL_NONE                  0x00000000U                          /*!< No hardware control       */
+#define UART_HWCONTROL_RTS                   USART_CR3_RTSE                       /*!< Request To Send           */
+#define UART_HWCONTROL_CTS                   USART_CR3_CTSE                       /*!< Clear To Send             */
+#define UART_HWCONTROL_RTS_CTS               (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< Request and Clear To Send */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Mode UART Transfer Mode
+  * @{
+  */
+#define UART_MODE_RX                        USART_CR1_RE                    /*!< RX mode        */
+#define UART_MODE_TX                        USART_CR1_TE                    /*!< TX mode        */
+#define UART_MODE_TX_RX                     (USART_CR1_TE |USART_CR1_RE)    /*!< RX and TX mode */
+/**
+  * @}
+  */
+
+/** @defgroup UART_State  UART State
+  * @{
+  */
+#define UART_STATE_DISABLE                  0x00000000U         /*!< UART disabled  */
+#define UART_STATE_ENABLE                   USART_CR1_UE        /*!< UART enabled   */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Over_Sampling UART Over Sampling
+  * @{
+  */
+#define UART_OVERSAMPLING_16                0x00000000U         /*!< Oversampling by 16 */
+#define UART_OVERSAMPLING_8                 USART_CR1_OVER8     /*!< Oversampling by 8  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method
+  * @{
+  */
+#define UART_ONE_BIT_SAMPLE_DISABLE         0x00000000U         /*!< One-bit sampling disable */
+#define UART_ONE_BIT_SAMPLE_ENABLE          USART_CR3_ONEBIT    /*!< One-bit sampling enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_ClockPrescaler  UART Clock Prescaler
+  * @{
+  */
+#define UART_PRESCALER_DIV1    0x00000000U  /*!< fclk_pres = fclk     */
+#define UART_PRESCALER_DIV2    0x00000001U  /*!< fclk_pres = fclk/2   */
+#define UART_PRESCALER_DIV4    0x00000002U  /*!< fclk_pres = fclk/4   */
+#define UART_PRESCALER_DIV6    0x00000003U  /*!< fclk_pres = fclk/6   */
+#define UART_PRESCALER_DIV8    0x00000004U  /*!< fclk_pres = fclk/8   */
+#define UART_PRESCALER_DIV10   0x00000005U  /*!< fclk_pres = fclk/10  */
+#define UART_PRESCALER_DIV12   0x00000006U  /*!< fclk_pres = fclk/12  */
+#define UART_PRESCALER_DIV16   0x00000007U  /*!< fclk_pres = fclk/16  */
+#define UART_PRESCALER_DIV32   0x00000008U  /*!< fclk_pres = fclk/32  */
+#define UART_PRESCALER_DIV64   0x00000009U  /*!< fclk_pres = fclk/64  */
+#define UART_PRESCALER_DIV128  0x0000000AU  /*!< fclk_pres = fclk/128 */
+#define UART_PRESCALER_DIV256  0x0000000BU  /*!< fclk_pres = fclk/256 */
+/**
+  * @}
+  */
+
+/** @defgroup UART_AutoBaud_Rate_Mode    UART Advanced Feature AutoBaud Rate Mode
+  * @{
+  */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT    0x00000000U           /*!< Auto Baud rate detection on start bit            */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0   /*!< Auto Baud rate detection on falling edge         */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME   USART_CR2_ABRMODE_1   /*!< Auto Baud rate detection on 0x7F frame detection */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME   USART_CR2_ABRMODE     /*!< Auto Baud rate detection on 0x55 frame detection */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Receiver_Timeout UART Receiver Timeout
+  * @{
+  */
+#define UART_RECEIVER_TIMEOUT_DISABLE       0x00000000U                /*!< UART Receiver Timeout disable */
+#define UART_RECEIVER_TIMEOUT_ENABLE        USART_CR2_RTOEN            /*!< UART Receiver Timeout enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_LIN    UART Local Interconnection Network mode
+  * @{
+  */
+#define UART_LIN_DISABLE                    0x00000000U                /*!< Local Interconnect Network disable */
+#define UART_LIN_ENABLE                     USART_CR2_LINEN            /*!< Local Interconnect Network enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_LIN_Break_Detection  UART LIN Break Detection
+  * @{
+  */
+#define UART_LINBREAKDETECTLENGTH_10B       0x00000000U                /*!< LIN 10-bit break detection length */
+#define UART_LINBREAKDETECTLENGTH_11B       USART_CR2_LBDL             /*!< LIN 11-bit break detection length  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_DMA_Tx    UART DMA Tx
+  * @{
+  */
+#define UART_DMA_TX_DISABLE                 0x00000000U                /*!< UART DMA TX disabled */
+#define UART_DMA_TX_ENABLE                  USART_CR3_DMAT             /*!< UART DMA TX enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_DMA_Rx   UART DMA Rx
+  * @{
+  */
+#define UART_DMA_RX_DISABLE                 0x00000000U                 /*!< UART DMA RX disabled */
+#define UART_DMA_RX_ENABLE                  USART_CR3_DMAR              /*!< UART DMA RX enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Half_Duplex_Selection  UART Half Duplex Selection
+  * @{
+  */
+#define UART_HALF_DUPLEX_DISABLE            0x00000000U                 /*!< UART half-duplex disabled */
+#define UART_HALF_DUPLEX_ENABLE             USART_CR3_HDSEL             /*!< UART half-duplex enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_WakeUp_Methods   UART WakeUp Methods
+  * @{
+  */
+#define UART_WAKEUPMETHOD_IDLELINE          0x00000000U                 /*!< UART wake-up on idle line    */
+#define UART_WAKEUPMETHOD_ADDRESSMARK       USART_CR1_WAKE              /*!< UART wake-up on address mark */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Request_Parameters UART Request Parameters
+  * @{
+  */
+#define UART_AUTOBAUD_REQUEST               USART_RQR_ABRRQ        /*!< Auto-Baud Rate Request      */
+#define UART_SENDBREAK_REQUEST              USART_RQR_SBKRQ        /*!< Send Break Request          */
+#define UART_MUTE_MODE_REQUEST              USART_RQR_MMRQ         /*!< Mute Mode Request           */
+#define UART_RXDATA_FLUSH_REQUEST           USART_RQR_RXFRQ        /*!< Receive Data flush Request  */
+#define UART_TXDATA_FLUSH_REQUEST           USART_RQR_TXFRQ        /*!< Transmit data flush Request */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Advanced_Features_Initialization_Type  UART Advanced Feature Initialization Type
+  * @{
+  */
+#define UART_ADVFEATURE_NO_INIT                 0x00000000U          /*!< No advanced feature initialization       */
+#define UART_ADVFEATURE_TXINVERT_INIT           0x00000001U          /*!< TX pin active level inversion            */
+#define UART_ADVFEATURE_RXINVERT_INIT           0x00000002U          /*!< RX pin active level inversion            */
+#define UART_ADVFEATURE_DATAINVERT_INIT         0x00000004U          /*!< Binary data inversion                    */
+#define UART_ADVFEATURE_SWAP_INIT               0x00000008U          /*!< TX/RX pins swap                          */
+#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT   0x00000010U          /*!< RX overrun disable                       */
+#define UART_ADVFEATURE_DMADISABLEONERROR_INIT  0x00000020U          /*!< DMA disable on Reception Error           */
+#define UART_ADVFEATURE_AUTOBAUDRATE_INIT       0x00000040U          /*!< Auto Baud rate detection initialization  */
+#define UART_ADVFEATURE_MSBFIRST_INIT           0x00000080U          /*!< Most significant bit sent/received first */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion
+  * @{
+  */
+#define UART_ADVFEATURE_TXINV_DISABLE       0x00000000U             /*!< TX pin active level inversion disable */
+#define UART_ADVFEATURE_TXINV_ENABLE        USART_CR2_TXINV         /*!< TX pin active level inversion enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion
+  * @{
+  */
+#define UART_ADVFEATURE_RXINV_DISABLE       0x00000000U             /*!< RX pin active level inversion disable */
+#define UART_ADVFEATURE_RXINV_ENABLE        USART_CR2_RXINV         /*!< RX pin active level inversion enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Data_Inv  UART Advanced Feature Binary Data Inversion
+  * @{
+  */
+#define UART_ADVFEATURE_DATAINV_DISABLE     0x00000000U             /*!< Binary data inversion disable */
+#define UART_ADVFEATURE_DATAINV_ENABLE      USART_CR2_DATAINV       /*!< Binary data inversion enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap
+  * @{
+  */
+#define UART_ADVFEATURE_SWAP_DISABLE        0x00000000U             /*!< TX/RX pins swap disable */
+#define UART_ADVFEATURE_SWAP_ENABLE         USART_CR2_SWAP          /*!< TX/RX pins swap enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Overrun_Disable  UART Advanced Feature Overrun Disable
+  * @{
+  */
+#define UART_ADVFEATURE_OVERRUN_ENABLE      0x00000000U             /*!< RX overrun enable  */
+#define UART_ADVFEATURE_OVERRUN_DISABLE     USART_CR3_OVRDIS        /*!< RX overrun disable */
+/**
+  * @}
+  */
+
+/** @defgroup UART_AutoBaudRate_Enable  UART Advanced Feature Auto BaudRate Enable
+  * @{
+  */
+#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE   0x00000000U          /*!< RX Auto Baud rate detection enable  */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE    USART_CR2_ABREN      /*!< RX Auto Baud rate detection disable */
+/**
+  * @}
+  */
+
+/** @defgroup UART_DMA_Disable_on_Rx_Error   UART Advanced Feature DMA Disable On Rx Error
+  * @{
+  */
+#define UART_ADVFEATURE_DMA_ENABLEONRXERROR    0x00000000U          /*!< DMA enable on Reception Error  */
+#define UART_ADVFEATURE_DMA_DISABLEONRXERROR   USART_CR3_DDRE       /*!< DMA disable on Reception Error */
+/**
+  * @}
+  */
+
+/** @defgroup UART_MSB_First   UART Advanced Feature MSB First
+  * @{
+  */
+#define UART_ADVFEATURE_MSBFIRST_DISABLE    0x00000000U             /*!< Most significant bit sent/received first disable */
+#define UART_ADVFEATURE_MSBFIRST_ENABLE     USART_CR2_MSBFIRST      /*!< Most significant bit sent/received first enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Stop_Mode_Enable   UART Advanced Feature Stop Mode Enable
+  * @{
+  */
+#define UART_ADVFEATURE_STOPMODE_DISABLE    0x00000000U             /*!< UART stop mode disable */
+#define UART_ADVFEATURE_STOPMODE_ENABLE     USART_CR1_UESM          /*!< UART stop mode enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Mute_Mode   UART Advanced Feature Mute Mode Enable
+  * @{
+  */
+#define UART_ADVFEATURE_MUTEMODE_DISABLE    0x00000000U             /*!< UART mute mode disable */
+#define UART_ADVFEATURE_MUTEMODE_ENABLE     USART_CR1_MME           /*!< UART mute mode enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_CR2_ADDRESS_LSB_POS    UART Address-matching LSB Position In CR2 Register
+  * @{
+  */
+#define UART_CR2_ADDRESS_LSB_POS             24U                                /*!< UART address-matching LSB position in CR2 register */
+/**
+  * @}
+  */
+
+/** @defgroup UART_WakeUp_from_Stop_Selection   UART WakeUp From Stop Selection
+  * @{
+  */
+#define UART_WAKEUP_ON_ADDRESS              0x00000000U             /*!< UART wake-up on address                         */
+#define UART_WAKEUP_ON_STARTBIT             USART_CR3_WUS_1         /*!< UART wake-up on start bit                       */
+#define UART_WAKEUP_ON_READDATA_NONEMPTY    USART_CR3_WUS           /*!< UART wake-up on receive data register not empty or RXFIFO is not empty */
+/**
+  * @}
+  */
+
+/** @defgroup UART_DriverEnable_Polarity      UART DriverEnable Polarity
+  * @{
+  */
+#define UART_DE_POLARITY_HIGH               0x00000000U             /*!< Driver enable signal is active high */
+#define UART_DE_POLARITY_LOW                USART_CR3_DEP           /*!< Driver enable signal is active low  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS    UART Driver Enable Assertion Time LSB Position In CR1 Register
+  * @{
+  */
+#define UART_CR1_DEAT_ADDRESS_LSB_POS       21U      /*!< UART Driver Enable assertion time LSB position in CR1 register */
+/**
+  * @}
+  */
+
+/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS    UART Driver Enable DeAssertion Time LSB Position In CR1 Register
+  * @{
+  */
+#define UART_CR1_DEDT_ADDRESS_LSB_POS       16U      /*!< UART Driver Enable de-assertion time LSB position in CR1 register */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Interruption_Mask    UART Interruptions Flag Mask
+  * @{
+  */
+#define UART_IT_MASK                        0x001FU  /*!< UART interruptions flags mask */
+/**
+  * @}
+  */
+
+/** @defgroup UART_TimeOut_Value    UART polling-based communications time-out value
+  * @{
+  */
+#define HAL_UART_TIMEOUT_VALUE              0x1FFFFFFU  /*!< UART polling-based communications time-out value */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Flags     UART Status Flags
+  *        Elements values convention: 0xXXXX
+  *           - 0xXXXX  : Flag mask in the ISR register
+  * @{
+  */
+#define UART_FLAG_TXFT                      USART_ISR_TXFT          /*!< UART TXFIFO threshold flag                */
+#define UART_FLAG_RXFT                      USART_ISR_RXFT          /*!< UART RXFIFO threshold flag                */
+#define UART_FLAG_RXFF                      USART_ISR_RXFF          /*!< UART RXFIFO Full flag                     */
+#define UART_FLAG_TXFE                      USART_ISR_TXFE          /*!< UART TXFIFO Empty flag                    */
+#define UART_FLAG_REACK                     USART_ISR_REACK         /*!< UART receive enable acknowledge flag      */
+#define UART_FLAG_TEACK                     USART_ISR_TEACK         /*!< UART transmit enable acknowledge flag     */
+#define UART_FLAG_WUF                       USART_ISR_WUF           /*!< UART wake-up from stop mode flag          */
+#define UART_FLAG_RWU                       USART_ISR_RWU           /*!< UART receiver wake-up from mute mode flag */
+#define UART_FLAG_SBKF                      USART_ISR_SBKF          /*!< UART send break flag                      */
+#define UART_FLAG_CMF                       USART_ISR_CMF           /*!< UART character match flag                 */
+#define UART_FLAG_BUSY                      USART_ISR_BUSY          /*!< UART busy flag                            */
+#define UART_FLAG_ABRF                      USART_ISR_ABRF          /*!< UART auto Baud rate flag                  */
+#define UART_FLAG_ABRE                      USART_ISR_ABRE          /*!< UART auto Baud rate error                 */
+#define UART_FLAG_RTOF                      USART_ISR_RTOF          /*!< UART receiver timeout flag                */
+#define UART_FLAG_CTS                       USART_ISR_CTS           /*!< UART clear to send flag                   */
+#define UART_FLAG_CTSIF                     USART_ISR_CTSIF         /*!< UART clear to send interrupt flag         */
+#define UART_FLAG_LBDF                      USART_ISR_LBDF          /*!< UART LIN break detection flag             */
+#define UART_FLAG_TXE                       USART_ISR_TXE_TXFNF     /*!< UART transmit data register empty         */
+#define UART_FLAG_TXFNF                     USART_ISR_TXE_TXFNF     /*!< UART TXFIFO not full                      */
+#define UART_FLAG_TC                        USART_ISR_TC            /*!< UART transmission complete                */
+#define UART_FLAG_RXNE                      USART_ISR_RXNE_RXFNE    /*!< UART read data register not empty         */
+#define UART_FLAG_RXFNE                     USART_ISR_RXNE_RXFNE    /*!< UART RXFIFO not empty                     */
+#define UART_FLAG_IDLE                      USART_ISR_IDLE          /*!< UART idle flag                            */
+#define UART_FLAG_ORE                       USART_ISR_ORE           /*!< UART overrun error                        */
+#define UART_FLAG_NE                        USART_ISR_NE            /*!< UART noise error                          */
+#define UART_FLAG_FE                        USART_ISR_FE            /*!< UART frame error                          */
+#define UART_FLAG_PE                        USART_ISR_PE            /*!< UART parity error                         */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Interrupt_definition   UART Interrupts Definition
+  *        Elements values convention: 000ZZZZZ0XXYYYYYb
+  *           - YYYYY  : Interrupt source position in the XX register (5bits)
+  *           - XX  : Interrupt source register (2bits)
+  *                 - 01: CR1 register
+  *                 - 10: CR2 register
+  *                 - 11: CR3 register
+  *           - ZZZZZ  : Flag position in the ISR register(5bits)
+  *        Elements values convention: 000000000XXYYYYYb
+  *           - YYYYY  : Interrupt source position in the XX register (5bits)
+  *           - XX  : Interrupt source register (2bits)
+  *                 - 01: CR1 register
+  *                 - 10: CR2 register
+  *                 - 11: CR3 register
+  *        Elements values convention: 0000ZZZZ00000000b
+  *           - ZZZZ  : Flag position in the ISR register(4bits)
+  * @{
+  */
+#define UART_IT_PE                          0x0028U                  /*!< UART parity error interruption                 */
+#define UART_IT_TXE                         0x0727U                  /*!< UART transmit data register empty interruption */
+#define UART_IT_TXFNF                       0x0727U                  /*!< UART TX FIFO not full interruption             */
+#define UART_IT_TC                          0x0626U                  /*!< UART transmission complete interruption        */
+#define UART_IT_RXNE                        0x0525U                  /*!< UART read data register not empty interruption */
+#define UART_IT_RXFNE                       0x0525U                  /*!< UART RXFIFO not empty interruption             */
+#define UART_IT_IDLE                        0x0424U                  /*!< UART idle interruption                         */
+#define UART_IT_LBD                         0x0846U                  /*!< UART LIN break detection interruption          */
+#define UART_IT_CTS                         0x096AU                  /*!< UART CTS interruption                          */
+#define UART_IT_CM                          0x112EU                  /*!< UART character match interruption              */
+#define UART_IT_WUF                         0x1476U                  /*!< UART wake-up from stop mode interruption       */
+#define UART_IT_RXFF                        0x183FU                  /*!< UART RXFIFO full interruption                  */
+#define UART_IT_TXFE                        0x173EU                  /*!< UART TXFIFO empty interruption                 */
+#define UART_IT_RXFT                        0x1A7CU                  /*!< UART RXFIFO threshold reached interruption     */
+#define UART_IT_TXFT                        0x1B77U                  /*!< UART TXFIFO threshold reached interruption     */
+#define UART_IT_RTO                         0x0B3AU                  /*!< UART receiver timeout interruption             */
+
+#define UART_IT_ERR                         0x0060U                  /*!< UART error interruption         */
+
+#define UART_IT_ORE                         0x0300U                  /*!< UART overrun error interruption */
+#define UART_IT_NE                          0x0200U                  /*!< UART noise error interruption   */
+#define UART_IT_FE                          0x0100U                  /*!< UART frame error interruption   */
+/**
+  * @}
+  */
+
+/** @defgroup UART_IT_CLEAR_Flags  UART Interruption Clear Flags
+  * @{
+  */
+#define UART_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag           */
+#define UART_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag          */
+#define UART_CLEAR_NEF                       USART_ICR_NECF            /*!< Noise Error detected Clear Flag   */
+#define UART_CLEAR_OREF                      USART_ICR_ORECF           /*!< Overrun Error Clear Flag          */
+#define UART_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag     */
+#define UART_CLEAR_TXFECF                    USART_ICR_TXFECF          /*!< TXFIFO empty clear flag           */
+#define UART_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag  */
+#define UART_CLEAR_LBDF                      USART_ICR_LBDCF           /*!< LIN Break Detection Clear Flag    */
+#define UART_CLEAR_CTSF                      USART_ICR_CTSCF           /*!< CTS Interrupt Clear Flag          */
+#define UART_CLEAR_CMF                       USART_ICR_CMCF            /*!< Character Match Clear Flag        */
+#define UART_CLEAR_WUF                       USART_ICR_WUCF            /*!< Wake Up from stop mode Clear Flag */
+#define UART_CLEAR_RTOF                      USART_ICR_RTOCF           /*!< UART receiver timeout clear flag  */
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup UART_Exported_Macros UART Exported Macros
+  * @{
+  */
+
+/** @brief  Reset UART handle states.
+  * @param  __HANDLE__ UART handle.
+  * @retval None
+  */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
+                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
+                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
+                                                       (__HANDLE__)->MspInitCallback = NULL;             \
+                                                       (__HANDLE__)->MspDeInitCallback = NULL;           \
+                                                     } while(0U)
+#else
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
+                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
+                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
+                                                     } while(0U)
+#endif /*USE_HAL_UART_REGISTER_CALLBACKS */
+
+/** @brief  Flush the UART Data registers.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__)  \
+  do{                \
+    SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
+    SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
+  }  while(0U)
+
+/** @brief  Clear the specified UART pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg @ref UART_CLEAR_PEF      Parity Error Clear Flag
+  *            @arg @ref UART_CLEAR_FEF      Framing Error Clear Flag
+  *            @arg @ref UART_CLEAR_NEF      Noise detected Clear Flag
+  *            @arg @ref UART_CLEAR_OREF     Overrun Error Clear Flag
+  *            @arg @ref UART_CLEAR_IDLEF    IDLE line detected Clear Flag
+  *            @arg @ref UART_CLEAR_TXFECF   TXFIFO empty clear Flag
+  *            @arg @ref UART_CLEAR_TCF      Transmission Complete Clear Flag
+  *            @arg @ref UART_CLEAR_RTOF     Receiver Timeout clear flag
+  *            @arg @ref UART_CLEAR_LBDF     LIN Break Detection Clear Flag
+  *            @arg @ref UART_CLEAR_CTSF     CTS Interrupt Clear Flag
+  *            @arg @ref UART_CLEAR_CMF      Character Match Clear Flag
+  *            @arg @ref UART_CLEAR_WUF      Wake Up from stop mode Clear Flag
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief  Clear the UART PE pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
+
+/** @brief  Clear the UART FE pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
+
+/** @brief  Clear the UART NE pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__)  __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
+
+/** @brief  Clear the UART ORE pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
+
+/** @brief  Clear the UART IDLE pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
+
+/** @brief  Clear the UART TX FIFO empty clear flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_TXFECF(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF)
+
+/** @brief  Check whether the specified UART flag is set or not.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg @ref UART_FLAG_TXFT  TXFIFO threshold flag
+  *            @arg @ref UART_FLAG_RXFT  RXFIFO threshold flag
+  *            @arg @ref UART_FLAG_RXFF  RXFIFO Full flag
+  *            @arg @ref UART_FLAG_TXFE  TXFIFO Empty flag
+  *            @arg @ref UART_FLAG_REACK Receive enable acknowledge flag
+  *            @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag
+  *            @arg @ref UART_FLAG_WUF   Wake up from stop mode flag
+  *            @arg @ref UART_FLAG_RWU   Receiver wake up flag (if the UART in mute mode)
+  *            @arg @ref UART_FLAG_SBKF  Send Break flag
+  *            @arg @ref UART_FLAG_CMF   Character match flag
+  *            @arg @ref UART_FLAG_BUSY  Busy flag
+  *            @arg @ref UART_FLAG_ABRF  Auto Baud rate detection flag
+  *            @arg @ref UART_FLAG_ABRE  Auto Baud rate detection error flag
+  *            @arg @ref UART_FLAG_CTS   CTS Change flag
+  *            @arg @ref UART_FLAG_LBDF  LIN Break detection flag
+  *            @arg @ref UART_FLAG_TXE   Transmit data register empty flag
+  *            @arg @ref UART_FLAG_TXFNF UART TXFIFO not full flag
+  *            @arg @ref UART_FLAG_TC    Transmission Complete flag
+  *            @arg @ref UART_FLAG_RXNE  Receive data register not empty flag
+  *            @arg @ref UART_FLAG_RXFNE UART RXFIFO not empty flag
+  *            @arg @ref UART_FLAG_RTOF  Receiver Timeout flag
+  *            @arg @ref UART_FLAG_IDLE  Idle Line detection flag
+  *            @arg @ref UART_FLAG_ORE   Overrun Error flag
+  *            @arg @ref UART_FLAG_NE    Noise Error flag
+  *            @arg @ref UART_FLAG_FE    Framing Error flag
+  *            @arg @ref UART_FLAG_PE    Parity Error flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Enable the specified UART interrupt.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __INTERRUPT__ specifies the UART interrupt source to enable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt
+  *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt
+  *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt
+  *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt
+  *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt
+  *            @arg @ref UART_IT_CM    Character match interrupt
+  *            @arg @ref UART_IT_CTS   CTS change interrupt
+  *            @arg @ref UART_IT_LBD   LIN Break detection interrupt
+  *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt
+  *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
+  *            @arg @ref UART_IT_TC    Transmission complete interrupt
+  *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
+  *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
+  *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
+  *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
+  *            @arg @ref UART_IT_PE    Parity Error interrupt
+  *            @arg @ref UART_IT_ERR   Error interrupt (frame error, noise error, overrun error)
+  * @retval None
+  */
+#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
+                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
+                                                           ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))))
+
+
+/** @brief  Disable the specified UART interrupt.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __INTERRUPT__ specifies the UART interrupt source to disable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt
+  *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt
+  *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt
+  *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt
+  *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt
+  *            @arg @ref UART_IT_CM    Character match interrupt
+  *            @arg @ref UART_IT_CTS   CTS change interrupt
+  *            @arg @ref UART_IT_LBD   LIN Break detection interrupt
+  *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt
+  *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
+  *            @arg @ref UART_IT_TC    Transmission complete interrupt
+  *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
+  *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
+  *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
+  *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
+  *            @arg @ref UART_IT_PE    Parity Error interrupt
+  *            @arg @ref UART_IT_ERR   Error interrupt (Frame error, noise error, overrun error)
+  * @retval None
+  */
+#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
+                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
+                                                           ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))
+
+/** @brief  Check whether the specified UART interrupt has occurred or not.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __INTERRUPT__ specifies the UART interrupt to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt
+  *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt
+  *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt
+  *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt
+  *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt
+  *            @arg @ref UART_IT_CM    Character match interrupt
+  *            @arg @ref UART_IT_CTS   CTS change interrupt
+  *            @arg @ref UART_IT_LBD   LIN Break detection interrupt
+  *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt
+  *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
+  *            @arg @ref UART_IT_TC    Transmission complete interrupt
+  *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
+  *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
+  *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
+  *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
+  *            @arg @ref UART_IT_PE    Parity Error interrupt
+  *            @arg @ref UART_IT_ERR   Error interrupt (Frame error, noise error, overrun error)
+  * @retval The new state of __INTERRUPT__ (SET or RESET).
+  */
+#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
+                                                        & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET)
+
+/** @brief  Check whether the specified UART interrupt source is enabled or not.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __INTERRUPT__ specifies the UART interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt
+  *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt
+  *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt
+  *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt
+  *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt
+  *            @arg @ref UART_IT_CM    Character match interrupt
+  *            @arg @ref UART_IT_CTS   CTS change interrupt
+  *            @arg @ref UART_IT_LBD   LIN Break detection interrupt
+  *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt
+  *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
+  *            @arg @ref UART_IT_TC    Transmission complete interrupt
+  *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
+  *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
+  *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
+  *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
+  *            @arg @ref UART_IT_PE    Parity Error interrupt
+  *            @arg @ref UART_IT_ERR   Error interrupt (Frame error, noise error, overrun error)
+  * @retval The new state of __INTERRUPT__ (SET or RESET).
+  */
+#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ? (__HANDLE__)->Instance->CR1 : \
+                                                                (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \
+                                                                 (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK)))  != RESET) ? SET : RESET)
+
+/** @brief  Clear the specified UART ISR flag, in setting the proper ICR register flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
+  *                       to clear the corresponding interrupt
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_CLEAR_PEF    Parity Error Clear Flag
+  *            @arg @ref UART_CLEAR_FEF    Framing Error Clear Flag
+  *            @arg @ref UART_CLEAR_NEF    Noise detected Clear Flag
+  *            @arg @ref UART_CLEAR_OREF   Overrun Error Clear Flag
+  *            @arg @ref UART_CLEAR_IDLEF  IDLE line detected Clear Flag
+  *            @arg @ref UART_CLEAR_RTOF   Receiver timeout clear flag
+  *            @arg @ref UART_CLEAR_TXFECF TXFIFO empty Clear Flag
+  *            @arg @ref UART_CLEAR_TCF    Transmission Complete Clear Flag
+  *            @arg @ref UART_CLEAR_LBDF   LIN Break Detection Clear Flag
+  *            @arg @ref UART_CLEAR_CTSF   CTS Interrupt Clear Flag
+  *            @arg @ref UART_CLEAR_CMF    Character Match Clear Flag
+  *            @arg @ref UART_CLEAR_WUF    Wake Up from stop mode Clear Flag
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
+
+/** @brief  Set a specific UART request flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __REQ__ specifies the request flag to set
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request
+  *            @arg @ref UART_SENDBREAK_REQUEST Send Break Request
+  *            @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request
+  *            @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request
+  *            @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request
+  * @retval None
+  */
+#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
+
+/** @brief  Enable the UART one bit sample method.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief  Disable the UART one bit sample method.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
+
+/** @brief  Enable UART.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+
+/** @brief  Disable UART.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+
+/** @brief  Enable CTS flow control.
+  * @note   This macro allows to enable CTS hardware flow control for a given UART instance,
+  *         without need to call HAL_UART_Init() function.
+  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+  * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
+  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
+  *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
+  *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)        \
+  do{                                                      \
+    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \
+    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;        \
+  } while(0U)
+
+/** @brief  Disable CTS flow control.
+  * @note   This macro allows to disable CTS hardware flow control for a given UART instance,
+  *         without need to call HAL_UART_Init() function.
+  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+  * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
+  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
+  *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
+  *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)        \
+  do{                                                       \
+    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
+    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);      \
+  } while(0U)
+
+/** @brief  Enable RTS flow control.
+  * @note   This macro allows to enable RTS hardware flow control for a given UART instance,
+  *         without need to call HAL_UART_Init() function.
+  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+  * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
+  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
+  *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
+  *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)       \
+  do{                                                     \
+    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
+    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;       \
+  } while(0U)
+
+/** @brief  Disable RTS flow control.
+  * @note   This macro allows to disable RTS hardware flow control for a given UART instance,
+  *         without need to call HAL_UART_Init() function.
+  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+  * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
+  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
+  *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
+  *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)       \
+  do{                                                      \
+    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
+    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);     \
+  } while(0U)
+/**
+  * @}
+  */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup UART_Private_Macros   UART Private Macros
+  * @{
+  */
+/** @brief  Get UART clok division factor from clock prescaler value.
+  * @param  __CLOCKPRESCALER__ UART prescaler value.
+  * @retval UART clock division factor
+  */
+#define UART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \
+  (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1)   ? 1U :       \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2)   ? 2U :       \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4)   ? 4U :       \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6)   ? 6U :       \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8)   ? 8U :       \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10)  ? 10U :      \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12)  ? 12U :      \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16)  ? 16U :      \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32)  ? 32U :      \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64)  ? 64U :      \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U :     \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U)
+
+/** @brief  BRR division operation to set BRR register with LPUART.
+  * @param  __PCLK__ LPUART clock.
+  * @param  __BAUD__ Baud rate set by the user.
+  * @param  __CLOCKPRESCALER__ UART prescaler value.
+  * @retval Division result
+  */
+#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__)      ((uint32_t)(((((uint64_t)(__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*256U)\
+                                                                      + (uint32_t)((__BAUD__)/2U)) / (__BAUD__)))
+
+/** @brief  BRR division operation to set BRR register in 8-bit oversampling mode.
+  * @param  __PCLK__ UART clock.
+  * @param  __BAUD__ Baud rate set by the user.
+  * @param  __CLOCKPRESCALER__ UART prescaler value.
+  * @retval Division result
+  */
+#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)   (((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*2U)\
+                                                                       + ((__BAUD__)/2U)) / (__BAUD__))
+
+/** @brief  BRR division operation to set BRR register in 16-bit oversampling mode.
+  * @param  __PCLK__ UART clock.
+  * @param  __BAUD__ Baud rate set by the user.
+  * @param  __CLOCKPRESCALER__ UART prescaler value.
+  * @retval Division result
+  */
+#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__)  ((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))\
+                                                                       + ((__BAUD__)/2U)) / (__BAUD__))
+
+/** @brief  Check whether or not UART instance is Low Power UART.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval SET (instance is LPUART) or RESET (instance isn't LPUART)
+  */
+#define UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE((__HANDLE__)->Instance))
+
+/** @brief  Check UART Baud rate.
+  * @param  __BAUDRATE__ Baudrate specified by the user.
+  *         The maximum Baud Rate is derived from the maximum clock on H7 (i.e. 100 MHz)
+  *         divided by the smallest oversampling used on the USART (i.e. 8)
+  * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)
+  */
+#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 12500001U)
+
+/** @brief  Check UART assertion time.
+  * @param  __TIME__ 5-bit value assertion time.
+  * @retval Test result (TRUE or FALSE).
+  */
+#define IS_UART_ASSERTIONTIME(__TIME__)    ((__TIME__) <= 0x1FU)
+
+/** @brief  Check UART deassertion time.
+  * @param  __TIME__ 5-bit value deassertion time.
+  * @retval Test result (TRUE or FALSE).
+  */
+#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
+
+/**
+  * @brief Ensure that UART frame number of stop bits is valid.
+  * @param __STOPBITS__ UART frame number of stop bits.
+  * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
+  */
+#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \
+                                        ((__STOPBITS__) == UART_STOPBITS_1)   || \
+                                        ((__STOPBITS__) == UART_STOPBITS_1_5) || \
+                                        ((__STOPBITS__) == UART_STOPBITS_2))
+
+/**
+  * @brief Ensure that LPUART frame number of stop bits is valid.
+  * @param __STOPBITS__ LPUART frame number of stop bits.
+  * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
+  */
+#define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \
+                                          ((__STOPBITS__) == UART_STOPBITS_2))
+
+/**
+  * @brief Ensure that UART frame parity is valid.
+  * @param __PARITY__ UART frame parity.
+  * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
+  */
+#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \
+                                    ((__PARITY__) == UART_PARITY_EVEN) || \
+                                    ((__PARITY__) == UART_PARITY_ODD))
+
+/**
+  * @brief Ensure that UART hardware flow control is valid.
+  * @param __CONTROL__ UART hardware flow control.
+  * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)
+  */
+#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\
+  (((__CONTROL__) == UART_HWCONTROL_NONE) || \
+   ((__CONTROL__) == UART_HWCONTROL_RTS)  || \
+   ((__CONTROL__) == UART_HWCONTROL_CTS)  || \
+   ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))
+
+/**
+  * @brief Ensure that UART communication mode is valid.
+  * @param __MODE__ UART communication mode.
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */
+#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
+
+/**
+  * @brief Ensure that UART state is valid.
+  * @param __STATE__ UART state.
+  * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
+  */
+#define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \
+                                  ((__STATE__) == UART_STATE_ENABLE))
+
+/**
+  * @brief Ensure that UART oversampling is valid.
+  * @param __SAMPLING__ UART oversampling.
+  * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
+  */
+#define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \
+                                            ((__SAMPLING__) == UART_OVERSAMPLING_8))
+
+/**
+  * @brief Ensure that UART frame sampling is valid.
+  * @param __ONEBIT__ UART frame sampling.
+  * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
+  */
+#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \
+                                            ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE))
+
+/**
+  * @brief Ensure that UART auto Baud rate detection mode is valid.
+  * @param __MODE__ UART auto Baud rate detection mode.
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__)  (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT)    || \
+                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \
+                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME)   || \
+                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))
+
+/**
+  * @brief Ensure that UART receiver timeout setting is valid.
+  * @param __TIMEOUT__ UART receiver timeout setting.
+  * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
+  */
+#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__)  (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
+                                                ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))
+
+/** @brief  Check the receiver timeout value.
+  * @note   The maximum UART receiver timeout value is 0xFFFFFF.
+  * @param  __TIMEOUTVALUE__ receiver timeout value.
+  * @retval Test result (TRUE or FALSE)
+  */
+#define IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__)  ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
+
+/**
+  * @brief Ensure that UART LIN state is valid.
+  * @param __LIN__ UART LIN state.
+  * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid)
+  */
+#define IS_UART_LIN(__LIN__)        (((__LIN__) == UART_LIN_DISABLE) || \
+                                     ((__LIN__) == UART_LIN_ENABLE))
+
+/**
+  * @brief Ensure that UART LIN break detection length is valid.
+  * @param __LENGTH__ UART LIN break detection length.
+  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+  */
+#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \
+                                                     ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))
+
+/**
+  * @brief Ensure that UART DMA TX state is valid.
+  * @param __DMATX__ UART DMA TX state.
+  * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
+  */
+#define IS_UART_DMA_TX(__DMATX__)     (((__DMATX__) == UART_DMA_TX_DISABLE) || \
+                                       ((__DMATX__) == UART_DMA_TX_ENABLE))
+
+/**
+  * @brief Ensure that UART DMA RX state is valid.
+  * @param __DMARX__ UART DMA RX state.
+  * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
+  */
+#define IS_UART_DMA_RX(__DMARX__)     (((__DMARX__) == UART_DMA_RX_DISABLE) || \
+                                       ((__DMARX__) == UART_DMA_RX_ENABLE))
+
+/**
+  * @brief Ensure that UART half-duplex state is valid.
+  * @param __HDSEL__ UART half-duplex state.
+  * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid)
+  */
+#define IS_UART_HALF_DUPLEX(__HDSEL__)     (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \
+                                            ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE))
+
+/**
+  * @brief Ensure that UART wake-up method is valid.
+  * @param __WAKEUP__ UART wake-up method .
+  * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid)
+  */
+#define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \
+                                          ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK))
+
+/**
+  * @brief Ensure that UART request parameter is valid.
+  * @param __PARAM__ UART request parameter.
+  * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
+  */
+#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST)     || \
+                                              ((__PARAM__) == UART_SENDBREAK_REQUEST)    || \
+                                              ((__PARAM__) == UART_MUTE_MODE_REQUEST)    || \
+                                              ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \
+                                              ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))
+
+/**
+  * @brief Ensure that UART advanced features initialization is valid.
+  * @param __INIT__ UART advanced features initialization.
+  * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_INIT(__INIT__)   ((__INIT__) <= (UART_ADVFEATURE_NO_INIT                | \
+                                                            UART_ADVFEATURE_TXINVERT_INIT          | \
+                                                            UART_ADVFEATURE_RXINVERT_INIT          | \
+                                                            UART_ADVFEATURE_DATAINVERT_INIT        | \
+                                                            UART_ADVFEATURE_SWAP_INIT              | \
+                                                            UART_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \
+                                                            UART_ADVFEATURE_DMADISABLEONERROR_INIT | \
+                                                            UART_ADVFEATURE_AUTOBAUDRATE_INIT      | \
+                                                            UART_ADVFEATURE_MSBFIRST_INIT))
+
+/**
+  * @brief Ensure that UART frame TX inversion setting is valid.
+  * @param __TXINV__ UART frame TX inversion setting.
+  * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \
+                                             ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE))
+
+/**
+  * @brief Ensure that UART frame RX inversion setting is valid.
+  * @param __RXINV__ UART frame RX inversion setting.
+  * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \
+                                             ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE))
+
+/**
+  * @brief Ensure that UART frame data inversion setting is valid.
+  * @param __DATAINV__ UART frame data inversion setting.
+  * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \
+                                                 ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE))
+
+/**
+  * @brief Ensure that UART frame RX/TX pins swap setting is valid.
+  * @param __SWAP__ UART frame RX/TX pins swap setting.
+  * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \
+                                           ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE))
+
+/**
+  * @brief Ensure that UART frame overrun setting is valid.
+  * @param __OVERRUN__ UART frame overrun setting.
+  * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
+  */
+#define IS_UART_OVERRUN(__OVERRUN__)     (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \
+                                          ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE))
+
+/**
+  * @brief Ensure that UART auto Baud rate state is valid.
+  * @param __AUTOBAUDRATE__ UART auto Baud rate state.
+  * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__)  (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
+                                                            ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
+
+/**
+  * @brief Ensure that UART DMA enabling or disabling on error setting is valid.
+  * @param __DMA__ UART DMA enabling or disabling on error setting.
+  * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__)  (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
+                                                   ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))
+
+/**
+  * @brief Ensure that UART frame MSB first setting is valid.
+  * @param __MSBFIRST__ UART frame MSB first setting.
+  * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
+                                                   ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))
+
+/**
+  * @brief Ensure that UART stop mode state is valid.
+  * @param __STOPMODE__ UART stop mode state.
+  * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \
+                                                   ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))
+
+/**
+  * @brief Ensure that UART mute mode state is valid.
+  * @param __MUTE__ UART mute mode state.
+  * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid)
+  */
+#define IS_UART_MUTE_MODE(__MUTE__)       (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
+                                           ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))
+
+/**
+  * @brief Ensure that UART wake-up selection is valid.
+  * @param __WAKE__ UART wake-up selection.
+  * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)
+  */
+#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS)           || \
+                                            ((__WAKE__) == UART_WAKEUP_ON_STARTBIT)          || \
+                                            ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY))
+
+/**
+  * @brief Ensure that UART driver enable polarity is valid.
+  * @param __POLARITY__ UART driver enable polarity.
+  * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)
+  */
+#define IS_UART_DE_POLARITY(__POLARITY__)    (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \
+                                              ((__POLARITY__) == UART_DE_POLARITY_LOW))
+
+/**
+  * @brief Ensure that UART Prescaler is valid.
+  * @param __CLOCKPRESCALER__ UART Prescaler value.
+  * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
+  */
+#define IS_UART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1)   || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2)   || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4)   || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6)   || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8)   || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10)  || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12)  || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16)  || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32)  || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64)  || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256))
+
+/**
+  * @}
+  */
+
+/* Include UART HAL Extended module */
+#include "stm32h7xx_hal_uart_ex.h"
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UART_Exported_Functions UART Exported Functions
+  * @{
+  */
+
+/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
+HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart);
+void HAL_UART_MspInit(UART_HandleTypeDef *huart);
+void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
+                                            pUART_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @addtogroup UART_Exported_Functions_Group2 IO operation functions
+  * @{
+  */
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);
+
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
+void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);
+
+/**
+  * @}
+  */
+
+/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions
+  * @{
+  */
+
+/* Peripheral Control functions  ************************************************/
+void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue);
+HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart);
+
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);
+void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
+
+/**
+  * @}
+  */
+
+/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions
+  * @{
+  */
+
+/* Peripheral State and Errors functions  **************************************************/
+HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
+uint32_t              HAL_UART_GetError(UART_HandleTypeDef *huart);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions -----------------------------------------------------------*/
+/** @addtogroup UART_Private_Functions UART Private Functions
+  * @{
+  */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
+                                              uint32_t Tickstart, uint32_t Timeout);
+void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_UART_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
new file mode 100644
index 00000000..bad4a667
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
@@ -0,0 +1,864 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_uart_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of UART HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_UART_EX_H
+#define STM32H7xx_HAL_UART_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup UARTEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UARTEx_Exported_Types UARTEx Exported Types
+  * @{
+  */
+
+/**
+  * @brief  UART wake up from stop mode parameters
+  */
+typedef struct
+{
+  uint32_t WakeUpEvent;        /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF).
+                                    This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.
+                                    If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must
+                                    be filled up. */
+
+  uint16_t AddressLength;      /*!< Specifies whether the address is 4 or 7-bit long.
+                                    This parameter can be a value of @ref UARTEx_WakeUp_Address_Length.  */
+
+  uint8_t Address;             /*!< UART/USART node address (7-bit long max). */
+} UART_WakeUpTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
+  * @{
+  */
+
+/** @defgroup UARTEx_Word_Length UARTEx Word Length
+  * @{
+  */
+#define UART_WORDLENGTH_7B          USART_CR1_M1   /*!< 7-bit long UART frame */
+#define UART_WORDLENGTH_8B          0x00000000U    /*!< 8-bit long UART frame */
+#define UART_WORDLENGTH_9B          USART_CR1_M0   /*!< 9-bit long UART frame */
+/**
+  * @}
+  */
+
+/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length
+  * @{
+  */
+#define UART_ADDRESS_DETECT_4B      0x00000000U      /*!< 4-bit long wake-up address */
+#define UART_ADDRESS_DETECT_7B      USART_CR2_ADDM7  /*!< 7-bit long wake-up address */
+/**
+  * @}
+  */
+
+/** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode
+  * @brief    UART FIFO mode
+  * @{
+  */
+#define UART_FIFOMODE_DISABLE       0x00000000U       /*!< FIFO mode disable */
+#define UART_FIFOMODE_ENABLE        USART_CR1_FIFOEN  /*!< FIFO mode enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level
+  * @brief    UART TXFIFO threshold level
+  * @{
+  */
+#define UART_TXFIFO_THRESHOLD_1_8   0x00000000U                               /*!< TXFIFO reaches 1/8 of its depth */
+#define UART_TXFIFO_THRESHOLD_1_4   USART_CR3_TXFTCFG_0                       /*!< TXFIFO reaches 1/4 of its depth */
+#define UART_TXFIFO_THRESHOLD_1_2   USART_CR3_TXFTCFG_1                       /*!< TXFIFO reaches 1/2 of its depth */
+#define UART_TXFIFO_THRESHOLD_3_4   (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */
+#define UART_TXFIFO_THRESHOLD_7_8   USART_CR3_TXFTCFG_2                       /*!< TXFIFO reaches 7/8 of its depth */
+#define UART_TXFIFO_THRESHOLD_8_8   (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty            */
+/**
+  * @}
+  */
+
+/** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level
+  * @brief    UART RXFIFO threshold level
+  * @{
+  */
+#define UART_RXFIFO_THRESHOLD_1_8   0x00000000U                               /*!< RXFIFO FIFO reaches 1/8 of its depth */
+#define UART_RXFIFO_THRESHOLD_1_4   USART_CR3_RXFTCFG_0                       /*!< RXFIFO FIFO reaches 1/4 of its depth */
+#define UART_RXFIFO_THRESHOLD_1_2   USART_CR3_RXFTCFG_1                       /*!< RXFIFO FIFO reaches 1/2 of its depth */
+#define UART_RXFIFO_THRESHOLD_3_4   (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */
+#define UART_RXFIFO_THRESHOLD_7_8   USART_CR3_RXFTCFG_2                       /*!< RXFIFO FIFO reaches 7/8 of its depth */
+#define UART_RXFIFO_THRESHOLD_8_8   (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full             */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UARTEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup UARTEx_Exported_Functions_Group1
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
+                                   uint32_t DeassertionTime);
+
+/**
+  * @}
+  */
+
+/** @addtogroup UARTEx_Exported_Functions_Group2
+  * @{
+  */
+
+void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
+
+void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart);
+void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart);
+
+/**
+  * @}
+  */
+
+/** @addtogroup UARTEx_Exported_Functions_Group3
+  * @{
+  */
+
+/* Peripheral Control functions  **********************************************/
+HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
+HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
+
+HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
+
+HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
+HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup UARTEx_Private_Macros UARTEx Private Macros
+  * @{
+  */
+
+/** @brief  Report the UART clock source.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __CLOCKSOURCE__ output variable.
+  * @retval UART clocking source, written in __CLOCKSOURCE__.
+  */
+#if defined(UART9) && defined(USART10)
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                        \
+    if((__HANDLE__)->Instance == USART1)                      \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART1_SOURCE())                   \
+      {                                                       \
+        case RCC_USART1CLKSOURCE_D2PCLK2:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2;       \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_PLL2:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_PLL3:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_CSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART2)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART2_SOURCE())                   \
+      {                                                       \
+        case RCC_USART2CLKSOURCE_D2PCLK1:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_PLL2:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_PLL3:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_CSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART3)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART3_SOURCE())                   \
+      {                                                       \
+        case RCC_USART3CLKSOURCE_D2PCLK1:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_PLL2:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_PLL3:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_CSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == UART4)                  \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART4_SOURCE())                    \
+      {                                                       \
+        case RCC_UART4CLKSOURCE_D2PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_PLL2:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_PLL3:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if ((__HANDLE__)->Instance == UART5)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART5_SOURCE())                    \
+      {                                                       \
+        case RCC_UART5CLKSOURCE_D2PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_PLL2:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_PLL3:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART6)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART6_SOURCE())                   \
+      {                                                       \
+        case RCC_USART6CLKSOURCE_D2PCLK2:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2;       \
+          break;                                              \
+        case RCC_USART6CLKSOURCE_PLL2:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_USART6CLKSOURCE_PLL3:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_USART6CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART6CLKSOURCE_CSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_USART6CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == UART7)                  \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART7_SOURCE())                    \
+      {                                                       \
+        case RCC_UART7CLKSOURCE_D2PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_UART7CLKSOURCE_PLL2:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_UART7CLKSOURCE_PLL3:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_UART7CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART7CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_UART7CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == UART8)                  \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART8_SOURCE())                    \
+      {                                                       \
+        case RCC_UART8CLKSOURCE_D2PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_UART8CLKSOURCE_PLL2:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_UART8CLKSOURCE_PLL3:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_UART8CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART8CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_UART8CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == UART9)                  \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART9_SOURCE())                    \
+      {                                                       \
+        case RCC_UART9CLKSOURCE_D2PCLK2:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2;       \
+          break;                                              \
+        case RCC_UART9CLKSOURCE_PLL2:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_UART9CLKSOURCE_PLL3:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_UART9CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART9CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_UART9CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART10)                \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART10_SOURCE())                  \
+      {                                                       \
+        case RCC_USART10CLKSOURCE_D2PCLK2:                    \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2;       \
+          break;                                              \
+        case RCC_USART10CLKSOURCE_PLL2:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_USART10CLKSOURCE_PLL3:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_USART10CLKSOURCE_HSI:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART10CLKSOURCE_CSI:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_USART10CLKSOURCE_LSE:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == LPUART1)                \
+    {                                                         \
+      switch(__HAL_RCC_GET_LPUART1_SOURCE())                  \
+      {                                                       \
+        case RCC_LPUART1CLKSOURCE_D3PCLK1:                    \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D3PCLK1;       \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_PLL2:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_PLL3:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_HSI:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_CSI:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_LSE:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else                                                      \
+    {                                                         \
+      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \
+    }                                                         \
+  } while(0U)
+#else
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                        \
+    if((__HANDLE__)->Instance == USART1)                      \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART1_SOURCE())                   \
+      {                                                       \
+        case RCC_USART1CLKSOURCE_D2PCLK2:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2;       \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_PLL2:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_PLL3:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_CSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART2)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART2_SOURCE())                   \
+      {                                                       \
+        case RCC_USART2CLKSOURCE_D2PCLK1:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_PLL2:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_PLL3:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_CSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART3)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART3_SOURCE())                   \
+      {                                                       \
+        case RCC_USART3CLKSOURCE_D2PCLK1:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_PLL2:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_PLL3:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_CSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == UART4)                  \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART4_SOURCE())                    \
+      {                                                       \
+        case RCC_UART4CLKSOURCE_D2PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_PLL2:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_PLL3:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if ((__HANDLE__)->Instance == UART5)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART5_SOURCE())                    \
+      {                                                       \
+        case RCC_UART5CLKSOURCE_D2PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_PLL2:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_PLL3:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART6)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART6_SOURCE())                   \
+      {                                                       \
+        case RCC_USART6CLKSOURCE_D2PCLK2:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2;       \
+          break;                                              \
+        case RCC_USART6CLKSOURCE_PLL2:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_USART6CLKSOURCE_PLL3:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_USART6CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART6CLKSOURCE_CSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_USART6CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == UART7)                  \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART7_SOURCE())                    \
+      {                                                       \
+        case RCC_UART7CLKSOURCE_D2PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_UART7CLKSOURCE_PLL2:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_UART7CLKSOURCE_PLL3:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_UART7CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART7CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_UART7CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == UART8)                  \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART8_SOURCE())                    \
+      {                                                       \
+        case RCC_UART8CLKSOURCE_D2PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_UART8CLKSOURCE_PLL2:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_UART8CLKSOURCE_PLL3:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_UART8CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART8CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_UART8CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == LPUART1)                \
+    {                                                         \
+      switch(__HAL_RCC_GET_LPUART1_SOURCE())                  \
+      {                                                       \
+        case RCC_LPUART1CLKSOURCE_D3PCLK1:                    \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D3PCLK1;       \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_PLL2:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_PLL3:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_HSI:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_CSI:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_LSE:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else                                                      \
+    {                                                         \
+      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \
+    }                                                         \
+  } while(0U)
+#endif  /* UART9 && USART10 */
+
+/** @brief  Report the UART mask to apply to retrieve the received data
+  *         according to the word length and to the parity bits activation.
+  * @note   If PCE = 1, the parity bit is not included in the data extracted
+  *         by the reception API().
+  *         This masking operation is not carried out in the case of
+  *         DMA transfers.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.
+  */
+#define UART_MASK_COMPUTATION(__HANDLE__)                             \
+  do {                                                                \
+    if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B)          \
+    {                                                                 \
+      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x01FFU ;                                \
+      }                                                               \
+      else                                                            \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x00FFU ;                                \
+      }                                                               \
+    }                                                                 \
+    else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B)     \
+    {                                                                 \
+      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x00FFU ;                                \
+      }                                                               \
+      else                                                            \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x007FU ;                                \
+      }                                                               \
+    }                                                                 \
+    else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B)     \
+    {                                                                 \
+      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x007FU ;                                \
+      }                                                               \
+      else                                                            \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x003FU ;                                \
+      }                                                               \
+    }                                                                 \
+    else                                                              \
+    {                                                                 \
+      (__HANDLE__)->Mask = 0x0000U;                                   \
+    }                                                                 \
+  } while(0U)
+
+/**
+  * @brief Ensure that UART frame length is valid.
+  * @param __LENGTH__ UART frame length.
+  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+  */
+#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \
+                                         ((__LENGTH__) == UART_WORDLENGTH_8B) || \
+                                         ((__LENGTH__) == UART_WORDLENGTH_9B))
+
+/**
+  * @brief Ensure that UART wake-up address length is valid.
+  * @param __ADDRESS__ UART wake-up address length.
+  * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
+  */
+#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
+                                                   ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
+
+/**
+  * @brief Ensure that UART TXFIFO threshold level is valid.
+  * @param __THRESHOLD__ UART TXFIFO threshold level.
+  * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
+  */
+#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \
+                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \
+                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \
+                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \
+                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \
+                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8))
+
+/**
+  * @brief Ensure that UART RXFIFO threshold level is valid.
+  * @param __THRESHOLD__ UART RXFIFO threshold level.
+  * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
+  */
+#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \
+                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \
+                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \
+                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \
+                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \
+                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8))
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_UART_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c
new file mode 100644
index 00000000..3e92312e
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c
@@ -0,0 +1,1276 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal.c
+  * @author  MCD Application Team
+  * @brief   HAL module driver.
+  *          This is the common part of the HAL initialization
+  *
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The common HAL driver contains a set of generic and common APIs that can be
+    used by the PPP peripheral drivers and the user to start using the HAL.
+    [..]
+    The HAL contains two APIs' categories:
+         (+) Common HAL APIs
+         (+) Services HAL APIs
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup HAL  HAL
+  * @brief HAL module driver.
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/**
+ * @brief STM32H7xx HAL Driver version number V1.8.0
+   */
+#define __STM32H7xx_HAL_VERSION_MAIN   (0x01UL) /*!< [31:24] main version */
+#define __STM32H7xx_HAL_VERSION_SUB1   (0x08UL) /*!< [23:16] sub1 version */
+#define __STM32H7xx_HAL_VERSION_SUB2   (0x00UL) /*!< [15:8]  sub2 version */
+#define __STM32H7xx_HAL_VERSION_RC     (0x00UL) /*!< [7:0]  release candidate */
+#define __STM32H7xx_HAL_VERSION         ((__STM32H7xx_HAL_VERSION_MAIN << 24)\
+                                        |(__STM32H7xx_HAL_VERSION_SUB1 << 16)\
+                                        |(__STM32H7xx_HAL_VERSION_SUB2 << 8 )\
+                                        |(__STM32H7xx_HAL_VERSION_RC))
+
+#define IDCODE_DEVID_MASK    ((uint32_t)0x00000FFF)
+#define VREFBUF_TIMEOUT_VALUE     (uint32_t)10   /* 10 ms  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Exported variables --------------------------------------------------------*/
+
+/** @defgroup HAL_Exported_Variables HAL Exported Variables
+  * @{
+  */
+__IO uint32_t uwTick;
+uint32_t uwTickPrio   = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
+HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT;  /* 1KHz */
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup HAL_Private_Functions  HAL Private Functions
+  * @{
+  */
+
+/** @defgroup HAL_Group1 Initialization and de-initialization Functions
+ *  @brief    Initialization and de-initialization functions
+ *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initializes the Flash interface the NVIC allocation and initial clock
+          configuration. It initializes the systick also when timeout is needed
+          and the backup domain when enabled.
+      (+) De-Initializes common part of the HAL.
+      (+) Configure The time base source to have 1ms time base with a dedicated
+          Tick interrupt priority.
+        (++) SysTick timer is used by default as source of time base, but user
+             can eventually implement his proper time base source (a general purpose
+             timer for example or other time source), keeping in mind that Time base
+             duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
+             handled in milliseconds basis.
+        (++) Time base configuration function (HAL_InitTick ()) is called automatically
+             at the beginning of the program after reset by HAL_Init() or at any time
+             when clock is configured, by HAL_RCC_ClockConfig().
+        (++) Source of time base is configured  to generate interrupts at regular
+             time intervals. Care must be taken if HAL_Delay() is called from a
+             peripheral ISR process, the Tick interrupt line must have higher priority
+            (numerically lower) than the peripheral interrupt. Otherwise the caller
+            ISR process will be blocked.
+       (++) functions affecting time base configurations are declared as __weak
+             to make  override possible  in case of other  implementations in user file.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function is used to initialize the HAL Library; it must be the first
+  *         instruction to be executed in the main program (before to call any other
+  *         HAL function), it performs the following:
+  *           Configures the SysTick to generate an interrupt each 1 millisecond,
+  *           which is clocked by the HSI (at this stage, the clock is not yet
+  *           configured and thus the system is running from the internal HSI at 16 MHz).
+  *           Set NVIC Group Priority to 4.
+  *           Calls the HAL_MspInit() callback function defined in user file
+  *           "stm32h7xx_hal_msp.c" to do the global low level hardware initialization
+  *
+  * @note   SysTick is used as time base for the HAL_Delay() function, the application
+  *         need to ensure that the SysTick time base is always set to 1 millisecond
+  *         to have correct HAL operation.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_Init(void)
+{
+
+uint32_t common_system_clock;
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+   /* Configure Cortex-M4 Instruction cache through ART accelerator */
+   __HAL_RCC_ART_CLK_ENABLE();                   /* Enable the Cortex-M4 ART Clock */
+   __HAL_ART_CONFIG_BASE_ADDRESS(0x08100000UL);  /* Configure the Cortex-M4 ART Base address to the Flash Bank 2 : */
+   __HAL_ART_ENABLE();                           /* Enable the Cortex-M4 ART */
+#endif /* DUAL_CORE &&  CORE_CM4 */
+
+  /* Set Interrupt Group Priority */
+  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+  /* Update the SystemCoreClock global variable */
+#if defined(RCC_D1CFGR_D1CPRE)
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
+#else
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
+#endif
+
+  /* Update the SystemD2Clock global variable */
+#if defined(RCC_D1CFGR_HPRE)
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+#else
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+#endif
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  SystemCoreClock = SystemD2Clock;
+#else
+  SystemCoreClock = common_system_clock;
+#endif /* DUAL_CORE && CORE_CM4 */
+
+  /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
+  if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Init the low level hardware */
+  HAL_MspInit();
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function de-Initializes common part of the HAL and stops the systick.
+  *         This function is optional.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DeInit(void)
+{
+  /* Reset of all peripherals */
+  __HAL_RCC_AHB3_FORCE_RESET();
+  __HAL_RCC_AHB3_RELEASE_RESET();
+
+  __HAL_RCC_AHB1_FORCE_RESET();
+  __HAL_RCC_AHB1_RELEASE_RESET();
+
+  __HAL_RCC_AHB2_FORCE_RESET();
+  __HAL_RCC_AHB2_RELEASE_RESET();
+
+  __HAL_RCC_AHB4_FORCE_RESET();
+ __HAL_RCC_AHB4_RELEASE_RESET();
+
+  __HAL_RCC_APB3_FORCE_RESET();
+  __HAL_RCC_APB3_RELEASE_RESET();
+
+  __HAL_RCC_APB1L_FORCE_RESET();
+  __HAL_RCC_APB1L_RELEASE_RESET();
+
+  __HAL_RCC_APB1H_FORCE_RESET();
+  __HAL_RCC_APB1H_RELEASE_RESET();
+
+   __HAL_RCC_APB2_FORCE_RESET();
+   __HAL_RCC_APB2_RELEASE_RESET();
+
+  __HAL_RCC_APB4_FORCE_RESET();
+  __HAL_RCC_APB4_RELEASE_RESET();
+
+  /* De-Init the low level hardware */
+  HAL_MspDeInit();
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the MSP.
+  * @retval None
+  */
+__weak void HAL_MspInit(void)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes the MSP.
+  * @retval None
+  */
+__weak void HAL_MspDeInit(void)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief This function configures the source of the time base.
+  *        The time source is configured  to have 1ms time base with a dedicated
+  *        Tick interrupt priority.
+  * @note This function is called  automatically at the beginning of program after
+  *       reset by HAL_Init() or at any time when clock is reconfigured  by HAL_RCC_ClockConfig().
+  * @note In the default implementation, SysTick timer is the source of time base.
+  *       It is used to generate interrupts at regular time intervals.
+  *       Care must be taken if HAL_Delay() is called from a peripheral ISR process,
+  *       The the SysTick interrupt must have higher priority (numerically lower)
+  *       than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+  *       The function is declared as __weak  to be overwritten  in case of other
+  *       implementation  in user file.
+  * @param TickPriority: Tick interrupt priority.
+  * @retval HAL status
+  */
+__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+  /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/
+  if((uint32_t)uwTickFreq == 0UL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Configure the SysTick to have interrupt in 1ms time basis*/
+  if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Configure the SysTick IRQ priority */
+  if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+  {
+    HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
+    uwTickPrio = TickPriority;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Group2 HAL Control functions
+ *  @brief    HAL Control functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### HAL Control functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Provide a tick value in millisecond
+      (+) Provide a blocking delay in millisecond
+      (+) Suspend the time base source interrupt
+      (+) Resume the time base source interrupt
+      (+) Get the HAL API driver version
+      (+) Get the device identifier
+      (+) Get the device revision identifier
+      (+) Enable/Disable Debug module during SLEEP mode
+      (+) Enable/Disable Debug module during STOP mode
+      (+) Enable/Disable Debug module during STANDBY mode
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief This function is called to increment  a global variable "uwTick"
+  *        used as application time base.
+  * @note In the default implementation, this variable is incremented each 1ms
+  *       in Systick ISR.
+ * @note This function is declared as __weak to be overwritten in case of other
+  *      implementations in user file.
+  * @retval None
+  */
+__weak void HAL_IncTick(void)
+{
+  uwTick += (uint32_t)uwTickFreq;
+}
+
+/**
+  * @brief Provides a tick value in millisecond.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @retval tick value
+  */
+__weak uint32_t HAL_GetTick(void)
+{
+  return uwTick;
+}
+
+/**
+  * @brief This function returns a tick priority.
+  * @retval tick priority
+  */
+uint32_t HAL_GetTickPrio(void)
+{
+  return uwTickPrio;
+}
+
+/**
+  * @brief Set new tick Freq.
+  * @retval Status
+  */
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
+{
+  HAL_StatusTypeDef status  = HAL_OK;
+  HAL_TickFreqTypeDef prevTickFreq;
+
+  assert_param(IS_TICKFREQ(Freq));
+
+  if (uwTickFreq != Freq)
+  {
+
+    /* Back up uwTickFreq frequency */
+    prevTickFreq = uwTickFreq;
+
+    /* Update uwTickFreq global variable used by HAL_InitTick() */
+    uwTickFreq = Freq;
+
+    /* Apply the new tick Freq  */
+    status = HAL_InitTick(uwTickPrio);
+    if (status != HAL_OK)
+    {
+      /* Restore previous tick frequency */
+      uwTickFreq = prevTickFreq;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief Return tick frequency.
+  * @retval tick period in Hz
+  */
+HAL_TickFreqTypeDef HAL_GetTickFreq(void)
+{
+  return uwTickFreq;
+}
+
+/**
+  * @brief This function provides minimum delay (in milliseconds) based
+  *        on variable incremented.
+  * @note In the default implementation , SysTick timer is the source of time base.
+  *       It is used to generate interrupts at regular time intervals where uwTick
+  *       is incremented.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @param Delay  specifies the delay time length, in milliseconds.
+  * @retval None
+  */
+__weak void HAL_Delay(uint32_t Delay)
+{
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t wait = Delay;
+
+  /* Add a freq to guarantee minimum wait */
+  if (wait < HAL_MAX_DELAY)
+  {
+    wait += (uint32_t)(uwTickFreq);
+  }
+
+  while ((HAL_GetTick() - tickstart) < wait)
+  {
+  }
+}
+
+/**
+  * @brief Suspend Tick increment.
+  * @note In the default implementation , SysTick timer is the source of time base. It is
+  *       used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
+  *       is called, the the SysTick interrupt will be disabled and so Tick increment
+  *       is suspended.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @retval None
+  */
+__weak void HAL_SuspendTick(void)
+{
+  /* Disable SysTick Interrupt */
+  SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
+}
+
+/**
+  * @brief Resume Tick increment.
+  * @note In the default implementation , SysTick timer is the source of time base. It is
+  *       used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
+  *       is called, the the SysTick interrupt will be enabled and so Tick increment
+  *       is resumed.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @retval None
+  */
+__weak void HAL_ResumeTick(void)
+{
+  /* Enable SysTick Interrupt */
+  SysTick->CTRL  |= SysTick_CTRL_TICKINT_Msk;
+}
+
+/**
+  * @brief  Returns the HAL revision
+  * @retval version : 0xXYZR (8bits for each decimal, R for RC)
+  */
+uint32_t HAL_GetHalVersion(void)
+{
+ return __STM32H7xx_HAL_VERSION;
+}
+
+/**
+  * @brief  Returns the device revision identifier.
+  * @retval Device revision identifier
+  */
+uint32_t HAL_GetREVID(void)
+{
+   return((DBGMCU->IDCODE) >> 16);
+}
+
+/**
+  * @brief  Returns the device identifier.
+  * @retval Device identifier
+  */
+uint32_t HAL_GetDEVID(void)
+{
+   return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
+}
+
+/**
+  * @brief  Return the first word of the unique device identifier (UID based on 96 bits)
+  * @retval Device identifier
+  */
+uint32_t HAL_GetUIDw0(void)
+{
+  return(READ_REG(*((uint32_t *)UID_BASE)));
+}
+
+/**
+  * @brief  Return the second word of the unique device identifier (UID based on 96 bits)
+  * @retval Device identifier
+  */
+uint32_t HAL_GetUIDw1(void)
+{
+  return(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
+}
+
+/**
+  * @brief  Return the third word of the unique device identifier (UID based on 96 bits)
+  * @retval Device identifier
+  */
+uint32_t HAL_GetUIDw2(void)
+{
+  return(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
+}
+
+/**
+  * @brief Configure the internal voltage reference buffer voltage scale.
+  * @param VoltageScaling  specifies the output voltage to achieve
+  *          This parameter can be one of the following values:
+  *            @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 2.048 V.
+  *                                                This requires VDDA equal to or higher than 2.4 V.
+  *            @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT2 around 2.5 V.
+  *                                                This requires VDDA equal to or higher than 2.8 V.
+  *            @arg SYSCFG_VREFBUF_VOLTAGE_SCALE2: VREF_OUT3 around 1.5 V.
+  *                                                This requires VDDA equal to or higher than 1.8 V.
+  *            @arg SYSCFG_VREFBUF_VOLTAGE_SCALE3: VREF_OUT4 around 1.8 V.
+  *                                                This requires VDDA equal to or higher than 2.1 V.
+  * @retval None
+  */
+void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling));
+
+  MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling);
+}
+
+/**
+  * @brief Configure the internal voltage reference buffer high impedance mode.
+  * @param Mode  specifies the high impedance mode
+  *          This parameter can be one of the following values:
+  *            @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output.
+  *            @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance.
+  * @retval None
+  */
+void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode));
+
+  MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode);
+}
+
+/**
+  * @brief  Tune the Internal Voltage Reference buffer (VREFBUF).
+  * @retval None
+  */
+void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue));
+
+  MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue);
+}
+
+/**
+  * @brief  Enable the Internal Voltage Reference buffer (VREFBUF).
+  * @retval HAL_OK/HAL_TIMEOUT
+  */
+HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void)
+{
+  uint32_t  tickstart;
+
+  SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
+
+  /* Get Start Tick*/
+  tickstart = HAL_GetTick();
+
+  /* Wait for VRR bit  */
+  while(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0UL)
+  {
+    if((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the Internal Voltage Reference buffer (VREFBUF).
+  *
+  * @retval None
+  */
+void HAL_SYSCFG_DisableVREFBUF(void)
+{
+  CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
+}
+
+#if defined(SYSCFG_PMCR_EPIS_SEL)
+/**
+  * @brief  Ethernet PHY Interface Selection either MII or RMII
+  * @param  SYSCFG_ETHInterface: Selects the Ethernet PHY interface
+  *   This parameter can be one of the following values:
+  *   @arg SYSCFG_ETH_MII : Select the Media Independent Interface
+  *   @arg SYSCFG_ETH_RMII: Select the Reduced Media Independent Interface
+  * @retval None
+  */
+void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface)
+{
+  /* Check the parameter */
+  assert_param(IS_SYSCFG_ETHERNET_CONFIG(SYSCFG_ETHInterface));
+
+  MODIFY_REG(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL, (uint32_t)(SYSCFG_ETHInterface));
+}
+#endif /* SYSCFG_PMCR_EPIS_SEL */
+
+/**
+  * @brief  Analog Switch control for dual analog pads.
+  * @param  SYSCFG_AnalogSwitch: Selects the analog pad
+  *   This parameter can be one or a combination of the following values:
+  *   @arg SYSCFG_SWITCH_PA0 : Select PA0 analog switch
+  *   @arg SYSCFG_SWITCH_PA1:  Select PA1 analog switch
+  *   @arg SYSCFG_SWITCH_PC2 : Select PC2 analog switch
+  *   @arg SYSCFG_SWITCH_PC3:  Select PC3 analog switch
+  * @param  SYSCFG_SwitchState: Open or Close the analog switch between dual pads (PXn and PXn_C)
+  *   This parameter can be one or a combination of the following values:
+  *   @arg SYSCFG_SWITCH_PA0_OPEN
+  *   @arg SYSCFG_SWITCH_PA0_CLOSE
+  *   @arg SYSCFG_SWITCH_PA1_OPEN
+  *   @arg SYSCFG_SWITCH_PA1_CLOSE
+  *   @arg SYSCFG_SWITCH_PC2_OPEN
+  *   @arg SYSCFG_SWITCH_PC2_CLOSE
+  *   @arg SYSCFG_SWITCH_PC3_OPEN
+  *   @arg SYSCFG_SWITCH_PC3_CLOSE
+  * @retval None
+  */
+
+void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState )
+{
+  /* Check the parameter */
+  assert_param(IS_SYSCFG_ANALOG_SWITCH(SYSCFG_AnalogSwitch));
+  assert_param(IS_SYSCFG_SWITCH_STATE(SYSCFG_SwitchState));
+
+  MODIFY_REG(SYSCFG->PMCR, (uint32_t) SYSCFG_AnalogSwitch, (uint32_t)(SYSCFG_SwitchState));
+}
+
+#if defined(SYSCFG_PMCR_BOOSTEN)
+/**
+  * @brief  Enables the booster to reduce the total harmonic distortion of the analog
+  *         switch when the supply voltage is lower than 2.7 V.
+  * @note   Activating the booster allows to guaranty the analog switch AC performance
+  *         when the supply voltage is below 2.7 V: in this case, the analog switch
+  *         performance is the same on the full voltage range
+  * @retval None
+  */
+void HAL_SYSCFG_EnableBOOST(void)
+{
+ SET_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
+}
+
+/**
+  * @brief  Disables the booster
+  * @note   Activating the booster allows to guaranty the analog switch AC performance
+  *         when the supply voltage is below 2.7 V: in this case, the analog switch
+  *         performance is the same on the full voltage range
+  * @retval None
+  */
+void HAL_SYSCFG_DisableBOOST(void)
+{
+ CLEAR_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
+}
+#endif /* SYSCFG_PMCR_BOOSTEN */
+
+#if defined (SYSCFG_UR2_BOOT_ADD0) ||  defined (SYSCFG_UR2_BCM7_ADD0)
+/**
+  * @brief  BootCM7 address 0 configuration
+  * @param  BootRegister :Specifies the Boot Address register (Address0 or Address1)
+  *   This parameter can be one of the following values:
+  *   @arg SYSCFG_BOOT_ADDR0 : Select the boot address0
+  *   @arg SYSCFG_BOOT_ADDR1:  Select the boot address1
+  * @param  BootAddress :Specifies the CM7 Boot Address to be loaded in Address0 or Address1
+  * @retval None
+  */
+void HAL_SYSCFG_CM7BootAddConfig(uint32_t BootRegister, uint32_t BootAddress)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_BOOT_REGISTER(BootRegister));
+  assert_param(IS_SYSCFG_BOOT_ADDRESS(BootAddress));
+  if ( BootRegister == SYSCFG_BOOT_ADDR0 )
+  {
+    /* Configure CM7 BOOT ADD0 */
+#if defined(DUAL_CORE)
+    MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0, ((BootAddress >> 16) << SYSCFG_UR2_BCM7_ADD0_Pos));
+#else
+    MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0, ((BootAddress >> 16) << SYSCFG_UR2_BOOT_ADD0_Pos));
+#endif /*DUAL_CORE*/
+  }
+  else
+  {
+    /* Configure CM7 BOOT ADD1 */
+#if defined(DUAL_CORE)
+    MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1, (BootAddress >> 16));
+#else
+    MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1, (BootAddress >> 16));
+#endif /*DUAL_CORE*/
+  }
+}
+#endif /* SYSCFG_UR2_BOOT_ADD0 || SYSCFG_UR2_BCM7_ADD0 */
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  BootCM4 address 0 configuration
+  * @param  BootRegister :Specifies the Boot Address register (Address0 or Address1)
+  *   This parameter can be one of the following values:
+  *   @arg SYSCFG_BOOT_ADDR0 : Select the boot address0
+  *   @arg SYSCFG_BOOT_ADDR1:  Select the boot address1
+  * @param  BootAddress :Specifies the CM4 Boot Address to be loaded in Address0 or Address1
+  * @retval None
+  */
+void HAL_SYSCFG_CM4BootAddConfig(uint32_t BootRegister, uint32_t BootAddress)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_BOOT_REGISTER(BootRegister));
+  assert_param(IS_SYSCFG_BOOT_ADDRESS(BootAddress));
+
+  if ( BootRegister == SYSCFG_BOOT_ADDR0 )
+  {
+    /* Configure CM4 BOOT ADD0 */
+    MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0, ((BootAddress >> 16)<< SYSCFG_UR3_BCM4_ADD0_Pos));
+  }
+
+  else
+  {
+    /* Configure CM4 BOOT ADD1 */
+    MODIFY_REG(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1, (BootAddress >> 16));
+  }
+}
+
+/**
+  * @brief  Enables the Cortex-M7 boot
+  * @retval None
+  */
+void HAL_SYSCFG_EnableCM7BOOT(void)
+{
+ SET_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM7);
+}
+
+/**
+  * @brief  Disables the Cortex-M7 boot
+  * @note   Disabling the boot will gate the CPU clock
+  * @retval None
+  */
+void HAL_SYSCFG_DisableCM7BOOT(void)
+{
+ CLEAR_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM7) ;
+}
+
+/**
+  * @brief  Enables the Cortex-M4 boot
+  * @retval None
+  */
+void HAL_SYSCFG_EnableCM4BOOT(void)
+{
+ SET_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4);
+}
+
+/**
+  * @brief  Disables the Cortex-M4 boot
+  * @note   Disabling the boot will gate the CPU clock
+  * @retval None
+  */
+void HAL_SYSCFG_DisableCM4BOOT(void)
+{
+  CLEAR_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4);
+}
+#endif /*DUAL_CORE*/
+/**
+  * @brief  Enables the I/O Compensation Cell.
+  * @note   The I/O compensation cell can be used only when the device supply
+  *         voltage ranges from 2.4 to 3.6 V.
+  * @retval None
+  */
+void HAL_EnableCompensationCell(void)
+{
+  SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN) ;
+}
+
+/**
+  * @brief  Power-down the I/O Compensation Cell.
+  * @note   The I/O compensation cell can be used only when the device supply
+  *         voltage ranges from 2.4 to 3.6 V.
+  * @retval None
+  */
+void HAL_DisableCompensationCell(void)
+{
+  CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN);
+}
+
+
+/**
+  * @brief  To Enable optimize the I/O speed when the product voltage is low.
+  * @note   This bit is active only if PRODUCT_BELOW_25V user option bit is set. It must be
+  *         used only if the product supply voltage is below 2.5 V. Setting this bit when VDD is
+  *         higher than 2.5 V might be destructive.
+  * @retval None
+  */
+void HAL_SYSCFG_EnableIOSpeedOptimize(void)
+{
+#if defined(SYSCFG_CCCSR_HSLV)
+  SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);
+#else
+  SET_BIT(SYSCFG->CCCSR, (SYSCFG_CCCSR_HSLV0| SYSCFG_CCCSR_HSLV1 | SYSCFG_CCCSR_HSLV2  | SYSCFG_CCCSR_HSLV3));
+#endif   /* SYSCFG_CCCSR_HSLV */
+}
+
+/**
+  * @brief  To Disable optimize the I/O speed when the product voltage is low.
+  * @note   This bit is active only if PRODUCT_BELOW_25V user option bit is set. It must be
+  *         used only if the product supply voltage is below 2.5 V. Setting this bit when VDD is
+  *         higher than 2.5 V might be destructive.
+  * @retval None
+  */
+void HAL_SYSCFG_DisableIOSpeedOptimize(void)
+{
+#if defined(SYSCFG_CCCSR_HSLV)
+  CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);
+#else
+  CLEAR_BIT(SYSCFG->CCCSR, (SYSCFG_CCCSR_HSLV0| SYSCFG_CCCSR_HSLV1 | SYSCFG_CCCSR_HSLV2  | SYSCFG_CCCSR_HSLV3));
+#endif   /* SYSCFG_CCCSR_HSLV */
+}
+
+/**
+  * @brief  Code selection for the I/O Compensation cell
+  * @param  SYSCFG_CompCode: Selects the code to be applied for the I/O compensation cell
+  *   This parameter can be one of the following values:
+  *   @arg SYSCFG_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR)
+  *   @arg SYSCFG_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR)
+  * @retval None
+  */
+void HAL_SYSCFG_CompensationCodeSelect(uint32_t SYSCFG_CompCode)
+{
+  /* Check the parameter */
+  assert_param(IS_SYSCFG_CODE_SELECT(SYSCFG_CompCode));
+  MODIFY_REG(SYSCFG->CCCSR, SYSCFG_CCCSR_CS, (uint32_t)(SYSCFG_CompCode));
+}
+
+/**
+  * @brief  Code selection for the I/O Compensation cell
+  * @param  SYSCFG_PMOSCode: PMOS compensation code
+  *         This code is applied to the I/O compensation cell when the CS bit of the
+  *          SYSCFG_CMPCR is set
+  * @param  SYSCFG_NMOSCode: NMOS compensation code
+  *         This code is applied to the I/O compensation cell when the CS bit of the
+  *          SYSCFG_CMPCR is set
+  * @retval None
+  */
+void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode )
+{
+  /* Check the parameter */
+  assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_PMOSCode));
+  assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_NMOSCode));
+  MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC|SYSCFG_CCCR_PCC, (((uint32_t)(SYSCFG_PMOSCode)<< 4)|(uint32_t)(SYSCFG_NMOSCode)) );
+}
+
+#if defined(SYSCFG_CCCR_NCC_MMC)
+/**
+  * @brief  Code selection for the I/O Compensation cell
+  * @param  SYSCFG_PMOSCode: VDDMMC PMOS compensation code
+  *         This code is applied to the I/O compensation cell when the CS bit of the
+  *          SYSCFG_CMPCR is set
+  * @param  SYSCFG_NMOSCode: VDDMMC NMOS compensation code
+  *         This code is applied to the I/O compensation cell when the CS bit of the
+  *          SYSCFG_CMPCR is set
+  * @retval None
+  */
+void HAL_SYSCFG_VDDMMC_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode )
+{
+  /* Check the parameter */
+  assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_PMOSCode));
+  assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_NMOSCode));
+  MODIFY_REG(SYSCFG->CCCR, (SYSCFG_CCCR_NCC_MMC | SYSCFG_CCCR_PCC_MMC), (((uint32_t)(SYSCFG_PMOSCode)<< 4)|(uint32_t)(SYSCFG_NMOSCode)) );
+}
+#endif /* SYSCFG_CCCR_NCC_MMC */
+
+/**
+  * @brief  Enable the Debug Module during Domain1/CDomain SLEEP mode
+  * @retval None
+  */
+void HAL_EnableDBGSleepMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
+}
+
+/**
+  * @brief  Disable the Debug Module during Domain1/CDomain SLEEP mode
+  * @retval None
+  */
+void HAL_DisableDBGSleepMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
+}
+
+
+/**
+  * @brief  Enable the Debug Module during Domain1/CDomain STOP mode
+  * @retval None
+  */
+void HAL_EnableDBGStopMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
+}
+
+/**
+  * @brief  Disable the Debug Module during Domain1/CDomain STOP mode
+  * @retval None
+  */
+void HAL_DisableDBGStopMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
+}
+
+/**
+  * @brief  Enable the Debug Module during Domain1/CDomain STANDBY mode
+  * @retval None
+  */
+void HAL_EnableDBGStandbyMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
+}
+
+/**
+  * @brief  Disable the Debug Module during Domain1/CDomain STANDBY mode
+  * @retval None
+  */
+void HAL_DisableDBGStandbyMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Enable the Debug Module during Domain1 SLEEP mode
+  * @retval None
+  */
+void HAL_EnableDomain2DBGSleepMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2);
+}
+
+/**
+  * @brief  Disable the Debug Module during Domain2 SLEEP mode
+  * @retval None
+  */
+void HAL_DisableDomain2DBGSleepMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2);
+}
+
+/**
+  * @brief  Enable the Debug Module during Domain2 STOP mode
+  * @retval None
+  */
+void HAL_EnableDomain2DBGStopMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2);
+}
+
+/**
+  * @brief  Disable the Debug Module during Domain2 STOP mode
+  * @retval None
+  */
+void HAL_DisableDomain2DBGStopMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2);
+}
+
+/**
+  * @brief  Enable the Debug Module during Domain2 STANDBY mode
+  * @retval None
+  */
+void HAL_EnableDomain2DBGStandbyMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2);
+}
+
+/**
+  * @brief  Disable the Debug Module during Domain2 STANDBY mode
+  * @retval None
+  */
+void HAL_DisableDomain2DBGStandbyMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2);
+}
+#endif /*DUAL_CORE*/
+
+/**
+  * @brief  Enable the Debug Module during Domain3/SRDomain STOP mode
+  * @retval None
+  */
+void HAL_EnableDomain3DBGStopMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
+}
+/**
+  * @brief  Disable the Debug Module during Domain3/SRDomain STOP mode
+  * @retval None
+  */
+void HAL_DisableDomain3DBGStopMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
+}
+
+/**
+  * @brief  Enable the Debug Module during Domain3/SRDomain STANDBY mode
+  * @retval None
+  */
+void HAL_EnableDomain3DBGStandbyMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
+}
+
+/**
+  * @brief  Disable the Debug Module during Domain3/SRDomain STANDBY mode
+  * @retval None
+  */
+void HAL_DisableDomain3DBGStandbyMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
+}
+
+/**
+  * @brief  Set the FMC Memory Mapping Swapping config.
+  * @param  BankMapConfig: Defines the FMC Bank mapping configuration. This parameter can be
+            FMC_SWAPBMAP_DISABLE, FMC_SWAPBMAP_SDRAM_SRAM, FMC_SWAPBMAP_SDRAMB2
+  * @retval HAL state
+  */
+void HAL_SetFMCMemorySwappingConfig(uint32_t BankMapConfig)
+{
+  /* Check the parameter */
+  assert_param(IS_FMC_SWAPBMAP_MODE(BankMapConfig));
+  MODIFY_REG(FMC_Bank1_R->BTCR[0], FMC_BCR1_BMAP, BankMapConfig);
+}
+
+/**
+  * @brief  Get FMC Bank mapping mode.
+  * @retval The FMC Bank mapping mode. This parameter can be
+            FMC_SWAPBMAP_DISABLE, FMC_SWAPBMAP_SDRAM_SRAM, FMC_SWAPBMAP_SDRAMB2
+*/
+uint32_t HAL_GetFMCMemorySwappingConfig(void)
+{
+  return READ_BIT(FMC_Bank1_R->BTCR[0], FMC_BCR1_BMAP);
+}
+
+/**
+  * @brief  Configure the EXTI input event line edge
+  * @note    No edge configuration for direct lines but for configurable lines:(EXTI_LINE0..EXTI_LINE21),
+  *          EXTI_LINE49,EXTI_LINE51,EXTI_LINE82,EXTI_LINE84,EXTI_LINE85 and EXTI_LINE86.
+  * @param   EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
+  *         (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
+  * @param   EXTI_Edge: Specifies  EXTI line Edge used.
+  *          This parameter can be one of the following values :
+  *   @arg EXTI_RISING_EDGE : Configurable line, with Rising edge trigger detection
+  *   @arg EXTI_FALLING_EDGE: Configurable line, with Falling edge trigger detection
+  * @retval None
+  */
+void HAL_EXTI_EdgeConfig(uint32_t EXTI_Line , uint32_t EXTI_Edge )
+{
+  /* Check the parameter */
+  assert_param(IS_HAL_EXTI_CONFIG_LINE(EXTI_Line));
+  assert_param(IS_EXTI_EDGE_LINE(EXTI_Edge));
+
+  /* Clear Rising Falling edge configuration */
+  CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+  CLEAR_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+
+  if( (EXTI_Edge & EXTI_RISING_EDGE) == EXTI_RISING_EDGE)
+  {
+   SET_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+  }
+  if( (EXTI_Edge & EXTI_FALLING_EDGE) == EXTI_FALLING_EDGE)
+  {
+   SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+  }
+}
+
+/**
+  * @brief  Generates a Software interrupt on selected EXTI line.
+  * @param   EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
+  *          (EXTI_LINE0..EXTI_LINE21),EXTI_LINE49,EXTI_LINE51,EXTI_LINE82,EXTI_LINE84,EXTI_LINE85 and EXTI_LINE86.
+  * @retval None
+  */
+void HAL_EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
+{
+  /* Check the parameters */
+  assert_param(IS_HAL_EXTI_CONFIG_LINE(EXTI_Line));
+
+  SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->SWIER1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+}
+
+
+/**
+  * @brief  Clears the EXTI's line pending flags for Domain D1
+  * @param   EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
+  *         (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
+  * @retval None
+  */
+void HAL_EXTI_D1_ClearFlag(uint32_t EXTI_Line)
+{
+  /* Check the parameters */
+ assert_param(IS_EXTI_D1_LINE(EXTI_Line));
+ WRITE_REG(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->PR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Clears the EXTI's line pending flags for Domain D2
+  * @param   EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
+  *         (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
+  * @retval None
+  */
+void HAL_EXTI_D2_ClearFlag(uint32_t EXTI_Line)
+{
+  /* Check the parameters */
+ assert_param(IS_EXTI_D2_LINE(EXTI_Line));
+ WRITE_REG(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->PR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+}
+
+#endif /*DUAL_CORE*/
+/**
+  * @brief  Configure the EXTI input event line for Domain D1
+  * @param   EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
+  *         (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
+  * @param   EXTI_Mode: Specifies which EXTI line is used as interrupt or an event.
+  *          This parameter can be one or a combination of the following values :
+  *   @arg EXTI_MODE_IT :  Interrupt Mode selected
+  *   @arg EXTI_MODE_EVT : Event Mode selected
+  * @param   EXTI_LineCmd controls (Enable/Disable) the EXTI line.
+
+  * @retval None
+  */
+void HAL_EXTI_D1_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode,  uint32_t EXTI_LineCmd )
+{
+  /* Check the parameter */
+  assert_param(IS_EXTI_D1_LINE(EXTI_Line));
+  assert_param(IS_EXTI_MODE_LINE(EXTI_Mode));
+
+  if( (EXTI_Mode & EXTI_MODE_IT) == EXTI_MODE_IT)
+  {
+     if( EXTI_LineCmd == 0UL)
+     {
+       /* Clear EXTI line configuration */
+        CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)),(uint32_t)(1UL << (EXTI_Line & 0x1FUL)) );
+     }
+     else
+     {
+        SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+     }
+  }
+
+  if( (EXTI_Mode & EXTI_MODE_EVT) == EXTI_MODE_EVT)
+  {
+    if( EXTI_LineCmd == 0UL)
+    {
+      /* Clear EXTI line configuration */
+      CLEAR_BIT(  *(__IO uint32_t *) (((uint32_t) &(EXTI_D1->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+    }
+    else
+    {
+      SET_BIT(  *(__IO uint32_t *) (((uint32_t) &(EXTI_D1->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+    }
+  }
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Configure the EXTI input event line for Domain D2
+  * @param   EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
+  *         (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
+  * @param   EXTI_Mode: Specifies which EXTI line is used as interrupt or an event.
+  *          This parameter can be one or a combination of the following values :
+  *   @arg EXTI_MODE_IT :  Interrupt Mode selected
+  *   @arg EXTI_MODE_EVT : Event Mode selected
+  * @param   EXTI_LineCmd controls (Enable/Disable) the EXTI line.
+
+  * @retval None
+  */
+void HAL_EXTI_D2_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode,  uint32_t EXTI_LineCmd )
+{
+  /* Check the parameter */
+  assert_param(IS_EXTI_D2_LINE(EXTI_Line));
+  assert_param(IS_EXTI_MODE_LINE(EXTI_Mode));
+
+  if( (EXTI_Mode & EXTI_MODE_IT) == EXTI_MODE_IT)
+  {
+    if( EXTI_LineCmd == 0UL)
+    {
+    /* Clear EXTI line configuration */
+     CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)),(uint32_t)(1UL << (EXTI_Line & 0x1FUL)) );
+    }
+    else
+    {
+     SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+    }
+  }
+
+  if( (EXTI_Mode & EXTI_MODE_EVT) == EXTI_MODE_EVT)
+  {
+    if( EXTI_LineCmd == 0UL)
+    {
+      /* Clear EXTI line configuration */
+      CLEAR_BIT(  *(__IO uint32_t *) (((uint32_t) &(EXTI_D2->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+    }
+    else
+    {
+      SET_BIT(  *(__IO uint32_t *) (((uint32_t) &(EXTI_D2->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+    }
+  }
+}
+#endif /*DUAL_CORE*/
+
+/**
+  * @brief  Configure the EXTI input event line for Domain D3
+  * @param   EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
+  *         (EXTI_LINE0...EXTI_LINE15),(EXTI_LINE19...EXTI_LINE21),EXTI_LINE25, EXTI_LINE34,
+  *          EXTI_LINE35,EXTI_LINE41,(EXTI_LINE48...EXTI_LINE53)
+  * @param   EXTI_LineCmd controls (Enable/Disable) the EXTI line.
+  * @param   EXTI_ClearSrc: Specifies the clear source of D3 pending event.
+  *          This parameter can be one of the following values :
+  *   @arg BDMA_CH6_CLEAR : BDMA ch6 event selected as D3 domain pendclear source
+  *   @arg BDMA_CH7_CLEAR : BDMA ch7 event selected as D3 domain pendclear source
+  *   @arg LPTIM4_OUT_CLEAR : LPTIM4 out selected as D3 domain pendclear source
+  *   @arg LPTIM5_OUT_CLEAR : LPTIM5 out selected as D3 domain pendclear source
+  * @retval None
+  */
+void HAL_EXTI_D3_EventInputConfig(uint32_t EXTI_Line, uint32_t EXTI_LineCmd , uint32_t EXTI_ClearSrc  )
+{
+  __IO uint32_t *pRegv;
+
+  /* Check the parameter */
+  assert_param(IS_EXTI_D3_LINE(EXTI_Line));
+  assert_param(IS_EXTI_D3_CLEAR(EXTI_ClearSrc));
+
+  if( EXTI_LineCmd == 0UL)
+  {
+    /* Clear EXTI line configuration */
+    CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->D3PMR1)) + ((EXTI_Line >> 5 ) * 0x20UL)),(uint32_t)(1UL << (EXTI_Line & 0x1FUL)) );
+  }
+  else
+  {
+    SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->D3PMR1)) +((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
+  }
+
+  if(((EXTI_Line>>4)%2UL) == 0UL)
+  {
+    pRegv = (__IO uint32_t *) (((uint32_t) &(EXTI->D3PCR1L)) + ((EXTI_Line >> 5 ) * 0x20UL));
+  }
+  else
+  {
+    pRegv = (__IO uint32_t *) (((uint32_t) &(EXTI->D3PCR1H)) + ((EXTI_Line >> 5 ) * 0x20UL));
+  }
+  MODIFY_REG(*pRegv, (uint32_t)(3UL << ((EXTI_Line*2UL) & 0x1FUL)), (uint32_t)(EXTI_ClearSrc << ((EXTI_Line*2UL) & 0x1FUL)));
+
+}
+
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c
new file mode 100644
index 00000000..631f432f
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c
@@ -0,0 +1,533 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_cortex.c
+  * @author  MCD Application Team
+  * @brief   CORTEX HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the CORTEX:
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions
+  *
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+
+    [..]
+    *** How to configure Interrupts using CORTEX HAL driver ***
+    ===========================================================
+    [..]
+    This section provides functions allowing to configure the NVIC interrupts (IRQ).
+    The Cortex-M exceptions are managed by CMSIS functions.
+
+    (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
+        function according to the following table.
+    (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
+    (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
+    (#) please refer to programming manual for details in how to configure priority.
+
+     -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
+         The pending IRQ priority will be managed only by the sub priority.
+
+     -@- IRQ priority order (sorted by highest to lowest priority):
+        (+@) Lowest preemption priority
+        (+@) Lowest sub priority
+        (+@) Lowest hardware priority (IRQ number)
+
+    [..]
+    *** How to configure Systick using CORTEX HAL driver ***
+    ========================================================
+    [..]
+    Setup SysTick Timer for time base.
+
+   (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
+       is a CMSIS function that:
+        (++) Configures the SysTick Reload register with value passed as function parameter.
+        (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
+        (++) Resets the SysTick Counter register.
+        (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
+        (++) Enables the SysTick Interrupt.
+        (++) Starts the SysTick Counter.
+
+   (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
+       HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
+       HAL_SYSTICK_Config() function call. The HAL_SYSTICK_CLKSourceConfig() macro is defined
+       inside the stm32h7xx_hal_cortex.h file.
+
+   (+) You can change the SysTick IRQ priority by calling the
+       HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
+       call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
+
+   (+) To adjust the SysTick time base, use the following formula:
+
+       Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
+       (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
+       (++) Reload Value should not exceed 0xFFFFFF
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup CORTEX CORTEX
+  * @brief CORTEX HAL module driver
+  * @{
+  */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
+  * @{
+  */
+
+
+/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+  ==============================================================================
+              ##### Initialization and de-initialization functions #####
+  ==============================================================================
+    [..]
+      This section provides the CORTEX HAL driver functions allowing to configure Interrupts
+      Systick functionalities
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Sets the priority grouping field (preemption priority and subpriority)
+  *         using the required unlock sequence.
+  * @param  PriorityGroup The priority grouping bits length.
+  *         This parameter can be one of the following values:
+  *         @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
+  *                                    4 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
+  *                                    3 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
+  *                                    2 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
+  *                                    1 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
+  *                                    0 bits for subpriority
+  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
+  *         The pending IRQ priority will be managed only by the subpriority.
+  * @retval None
+  */
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+
+  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
+  NVIC_SetPriorityGrouping(PriorityGroup);
+}
+
+/**
+  * @brief  Sets the priority of an interrupt.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
+  * @param  PreemptPriority The preemption priority for the IRQn channel.
+  *         This parameter can be a value between 0 and 15
+  *         A lower priority value indicates a higher priority
+  * @param  SubPriority the subpriority level for the IRQ channel.
+  *         This parameter can be a value between 0 and 15
+  *         A lower priority value indicates a higher priority.
+  * @retval None
+  */
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t prioritygroup;
+
+  /* Check the parameters */
+  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
+  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
+
+  prioritygroup = NVIC_GetPriorityGrouping();
+
+  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
+}
+
+/**
+  * @brief  Enables a device specific interrupt in the NVIC interrupt controller.
+  * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
+  *         function should be called before.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+  /* Enable interrupt */
+  NVIC_EnableIRQ(IRQn);
+}
+
+/**
+  * @brief  Disables a device specific interrupt in the NVIC interrupt controller.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+  /* Disable interrupt */
+  NVIC_DisableIRQ(IRQn);
+}
+
+/**
+  * @brief  Initiates a system reset request to reset the MCU.
+  * @retval None
+  */
+void HAL_NVIC_SystemReset(void)
+{
+  /* System Reset */
+  NVIC_SystemReset();
+}
+
+/**
+  * @brief  Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+  *         Counter is in free running mode to generate periodic interrupts.
+  * @param  TicksNumb Specifies the ticks Number of ticks between two interrupts.
+  * @retval status   - 0  Function succeeded.
+  *                  - 1  Function failed.
+  */
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
+{
+   return SysTick_Config(TicksNumb);
+}
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
+ *  @brief   Cortex control functions
+ *
+@verbatim
+  ==============================================================================
+                      ##### Peripheral Control functions #####
+  ==============================================================================
+    [..]
+      This subsection provides a set of functions allowing to control the CORTEX
+      (NVIC, SYSTICK, MPU) functionalities.
+
+
+@endverbatim
+  * @{
+  */
+#if (__MPU_PRESENT == 1)
+/**
+  * @brief  Disables the MPU
+  * @retval None
+  */
+void HAL_MPU_Disable(void)
+{
+  /* Make sure outstanding transfers are done */
+  __DMB();
+
+  /* Disable fault exceptions */
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+
+  /* Disable the MPU and clear the control register*/
+  MPU->CTRL = 0;
+}
+
+/**
+  * @brief  Enables the MPU
+  * @param  MPU_Control Specifies the control mode of the MPU during hard fault,
+  *         NMI, FAULTMASK and privileged access to the default memory
+  *         This parameter can be one of the following values:
+  *            @arg MPU_HFNMI_PRIVDEF_NONE
+  *            @arg MPU_HARDFAULT_NMI
+  *            @arg MPU_PRIVILEGED_DEFAULT
+  *            @arg MPU_HFNMI_PRIVDEF
+  * @retval None
+  */
+void HAL_MPU_Enable(uint32_t MPU_Control)
+{
+  /* Enable the MPU */
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+
+  /* Enable fault exceptions */
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+
+  /* Ensure MPU setting take effects */
+  __DSB();
+  __ISB();
+}
+/**
+  * @brief  Initializes and configures the Region and the memory to be protected.
+  * @param  MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
+  *                  the initialization and configuration information.
+  * @retval None
+  */
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
+{
+  /* Check the parameters */
+  assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
+  assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
+
+  /* Set the Region number */
+  MPU->RNR = MPU_Init->Number;
+
+  if ((MPU_Init->Enable) != 0UL)
+  {
+    /* Check the parameters */
+    assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
+    assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
+    assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
+    assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
+    assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
+    assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
+    assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
+    assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
+
+    MPU->RBAR = MPU_Init->BaseAddress;
+    MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
+                ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
+                ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
+                ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
+                ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
+                ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
+                ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
+                ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
+                ((uint32_t)MPU_Init->Enable                  << MPU_RASR_ENABLE_Pos);
+  }
+  else
+  {
+    MPU->RBAR = 0x00;
+    MPU->RASR = 0x00;
+  }
+}
+#endif /* __MPU_PRESENT */
+
+/**
+  * @brief  Gets the priority grouping field from the NVIC Interrupt Controller.
+  * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
+  */
+uint32_t HAL_NVIC_GetPriorityGrouping(void)
+{
+  /* Get the PRIGROUP[10:8] field value */
+  return NVIC_GetPriorityGrouping();
+}
+
+/**
+  * @brief  Gets the priority of an interrupt.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
+  * @param   PriorityGroup the priority grouping bits length.
+  *         This parameter can be one of the following values:
+  *           @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
+  *                                      4 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
+  *                                      3 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
+  *                                      2 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
+  *                                      1 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
+  *                                      0 bits for subpriority
+  * @param  pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
+  * @param  pSubPriority Pointer on the Subpriority value (starting from 0).
+  * @retval None
+  */
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+ /* Get priority for Cortex-M system or device specific interrupts */
+  NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
+}
+
+/**
+  * @brief  Sets Pending bit of an external interrupt.
+  * @param  IRQn External interrupt number
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+  /* Set interrupt pending */
+  NVIC_SetPendingIRQ(IRQn);
+}
+
+/**
+  * @brief  Gets Pending Interrupt (reads the pending register in the NVIC
+  *         and returns the pending bit for the specified interrupt).
+  * @param  IRQn External interrupt number.
+  *          This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
+  * @retval status  - 0  Interrupt status is not pending.
+  *                 - 1  Interrupt status is pending.
+  */
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+  /* Return 1 if pending else 0 */
+  return NVIC_GetPendingIRQ(IRQn);
+}
+
+/**
+  * @brief  Clears the pending bit of an external interrupt.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+  /* Clear pending interrupt */
+  NVIC_ClearPendingIRQ(IRQn);
+}
+
+/**
+  * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
+  * @param IRQn External interrupt number
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
+  * @retval status  - 0  Interrupt status is not pending.
+  *                 - 1  Interrupt status is pending.
+  */
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+  /* Return 1 if active else 0 */
+  return NVIC_GetActive(IRQn);
+}
+
+/**
+  * @brief  Configures the SysTick clock source.
+  * @param  CLKSource specifies the SysTick clock source.
+  *         This parameter can be one of the following values:
+  *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
+  *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
+  * @retval None
+  */
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
+  if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
+  {
+    SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
+  }
+  else
+  {
+    SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
+  }
+}
+
+/**
+  * @brief  This function handles SYSTICK interrupt request.
+  * @retval None
+  */
+void HAL_SYSTICK_IRQHandler(void)
+{
+  HAL_SYSTICK_Callback();
+}
+
+/**
+  * @brief  SYSTICK callback.
+  * @retval None
+  */
+__weak void HAL_SYSTICK_Callback(void)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SYSTICK_Callback could be implemented in the user file
+   */
+}
+
+#if defined(DUAL_CORE)
+
+/**
+  * @brief  Returns the current CPU ID.
+  * @retval CPU identifier
+  */
+uint32_t HAL_GetCurrentCPUID(void)
+{
+  if (((SCB->CPUID & 0x000000F0U) >> 4 )== 0x7U)
+  {
+    return  CM7_CPUID;
+  }
+  else
+  {
+    return CM4_CPUID;
+  }
+}
+
+#else
+
+/**
+* @brief  Returns the current CPU ID.
+* @retval CPU identifier
+*/
+uint32_t HAL_GetCurrentCPUID(void)
+{
+  return  CM7_CPUID;
+}
+
+#endif /*DUAL_CORE*/
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c
new file mode 100644
index 00000000..e2bbea73
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c
@@ -0,0 +1,2055 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_dma.c
+  * @author  MCD Application Team
+  * @brief   DMA HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Direct Memory Access (DMA) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral State and errors functions
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+   (#) Enable and configure the peripheral to be connected to the DMA Stream
+       (except for internal SRAM/FLASH memories: no initialization is
+       necessary) please refer to Reference manual for connection between peripherals
+       and DMA requests .
+
+   (#) For a given Stream, program the required configuration through the following parameters:
+       Transfer Direction, Source and Destination data formats,
+       Circular, Normal or peripheral flow control mode, Stream Priority level,
+       Source and Destination Increment mode, FIFO mode and its Threshold (if needed),
+       Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.
+
+     *** Polling mode IO operation ***
+     =================================
+    [..]
+          (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
+              address and destination address and the Length of data to be transferred
+          (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
+              case a fixed Timeout can be configured by User depending from his application.
+
+     *** Interrupt mode IO operation ***
+     ===================================
+    [..]
+          (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
+          (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
+          (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
+              Source address and destination address and the Length of data to be transferred. In this
+              case the DMA interrupt is configured
+          (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
+          (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
+              add his own function by customization of function pointer XferCpltCallback and
+              XferErrorCallback (i.e a member of DMA handle structure).
+    [..]
+     (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
+         detection.
+
+     (#) Use HAL_DMA_Abort() function to abort the current transfer
+
+     -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.
+
+     -@-   The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is
+           possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set
+           Half-Word data size for the peripheral to access its data register and set Word data size
+           for the Memory to gain in access time. Each two half words will be packed and written in
+           a single access to a Word in the Memory).
+
+     -@-   When FIFO is disabled, it is not allowed to configure different Data Sizes for Source
+           and Destination. In this case the Peripheral Data Size will be applied to both Source
+           and Destination.
+
+     *** DMA HAL driver macros list ***
+     =============================================
+     [..]
+       Below the list of most used macros in DMA HAL driver.
+
+      (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.
+      (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.
+      (+) __HAL_DMA_GET_FS: Return the current DMA Stream FIFO filled level.
+      (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Stream interrupts.
+      (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts.
+      (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not.
+
+     [..]
+      (@) You can refer to the DMA HAL driver header file for more useful macros.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup DMA DMA
+  * @brief DMA HAL module driver
+  * @{
+  */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+typedef struct
+{
+  __IO uint32_t ISR;   /*!< DMA interrupt status register */
+  __IO uint32_t Reserved0;
+  __IO uint32_t IFCR;  /*!< DMA interrupt flag clear register */
+} DMA_Base_Registers;
+
+typedef struct
+{
+  __IO uint32_t ISR;   /*!< BDMA interrupt status register */
+  __IO uint32_t IFCR;  /*!< BDMA interrupt flag clear register */
+} BDMA_Base_Registers;
+
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup DMA_Private_Constants
+ * @{
+ */
+#define HAL_TIMEOUT_DMA_ABORT         (5U)  /* 5 ms */
+
+#define BDMA_PERIPH_TO_MEMORY         (0x00000000U)                /*!< Peripheral to memory direction */
+#define BDMA_MEMORY_TO_PERIPH         ((uint32_t)BDMA_CCR_DIR)     /*!< Memory to peripheral direction */
+#define BDMA_MEMORY_TO_MEMORY         ((uint32_t)BDMA_CCR_MEM2MEM) /*!< Memory to memory direction     */
+
+/* DMA to BDMA conversion */
+#define DMA_TO_BDMA_DIRECTION(__DMA_DIRECTION__) (((__DMA_DIRECTION__) == DMA_MEMORY_TO_PERIPH)? BDMA_MEMORY_TO_PERIPH: \
+                                                  ((__DMA_DIRECTION__) == DMA_MEMORY_TO_MEMORY)? BDMA_MEMORY_TO_MEMORY: \
+                                                  BDMA_PERIPH_TO_MEMORY)
+
+#define DMA_TO_BDMA_PERIPHERAL_INC(__DMA_PERIPHERAL_INC__) ((__DMA_PERIPHERAL_INC__) >> 3U)
+#define DMA_TO_BDMA_MEMORY_INC(__DMA_MEMORY_INC__) ((__DMA_MEMORY_INC__) >> 3U)
+
+#define DMA_TO_BDMA_PDATA_SIZE(__DMA_PDATA_SIZE__) ((__DMA_PDATA_SIZE__) >> 3U)
+#define DMA_TO_BDMA_MDATA_SIZE(__DMA_MDATA_SIZE__) ((__DMA_MDATA_SIZE__) >> 3U)
+
+#define DMA_TO_BDMA_MODE(__DMA_MODE__) ((__DMA_MODE__) >> 3U)
+
+#define DMA_TO_BDMA_PRIORITY(__DMA_PRIORITY__) ((__DMA_PRIORITY__) >> 4U)
+
+#if defined(UART9)
+#define IS_DMA_UART_USART_REQUEST(__REQUEST__) ((((__REQUEST__) >= DMA_REQUEST_USART1_RX)  &&  ((__REQUEST__) <= DMA_REQUEST_USART3_TX)) || \
+                                                 (((__REQUEST__) >= DMA_REQUEST_UART4_RX)  &&  ((__REQUEST__) <= DMA_REQUEST_UART5_TX )) || \
+                                                 (((__REQUEST__) >= DMA_REQUEST_USART6_RX) &&  ((__REQUEST__) <= DMA_REQUEST_USART6_TX)) || \
+                                                 (((__REQUEST__) >= DMA_REQUEST_UART7_RX)  &&  ((__REQUEST__) <= DMA_REQUEST_UART8_TX )) || \
+                                                 (((__REQUEST__) >= DMA_REQUEST_UART9_RX)  &&  ((__REQUEST__) <= DMA_REQUEST_USART10_TX )))
+#else
+#define IS_DMA_UART_USART_REQUEST(__REQUEST__) ((((__REQUEST__) >= DMA_REQUEST_USART1_RX)  &&  ((__REQUEST__) <= DMA_REQUEST_USART3_TX)) || \
+                                                 (((__REQUEST__) >= DMA_REQUEST_UART4_RX)  &&  ((__REQUEST__) <= DMA_REQUEST_UART5_TX )) || \
+                                                 (((__REQUEST__) >= DMA_REQUEST_USART6_RX) &&  ((__REQUEST__) <= DMA_REQUEST_USART6_TX)) || \
+                                                 (((__REQUEST__) >= DMA_REQUEST_UART7_RX)  &&  ((__REQUEST__) <= DMA_REQUEST_UART8_TX )))
+
+#endif
+/**
+  * @}
+  */
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup DMA_Private_Functions
+  * @{
+  */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma);
+static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma);
+static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma);
+
+/**
+  * @}
+  */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @addtogroup DMA_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group1
+  *
+@verbatim
+ ===============================================================================
+             ##### Initialization and de-initialization functions  #####
+ ===============================================================================
+    [..]
+    This section provides functions allowing to initialize the DMA Stream source
+    and destination incrementation and data sizes, transfer direction,
+    circular/normal mode selection, memory-to-memory mode selection and Stream priority value.
+    [..]
+    The HAL_DMA_Init() function follows the DMA configuration procedures as described in
+    reference manual.
+    The HAL_DMA_DeInit function allows to deinitialize the DMA stream.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the DMA according to the specified
+  *         parameters in the DMA_InitTypeDef and create the associated handle.
+  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
+{
+  uint32_t registerValue;
+  uint32_t tickstart = HAL_GetTick();
+  DMA_Base_Registers *regs_dma;
+  BDMA_Base_Registers *regs_bdma;
+
+  /* Check the DMA peripheral handle */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+  assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
+  assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
+  assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
+  assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
+  assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
+  assert_param(IS_DMA_MODE(hdma->Init.Mode));
+  assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
+
+  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+  {
+    assert_param(IS_DMA_REQUEST(hdma->Init.Request));
+    assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode));
+    /* Check the memory burst, peripheral burst and FIFO threshold parameters only
+       when FIFO mode is enabled */
+    if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE)
+    {
+      assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold));
+      assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
+      assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
+    }
+
+    /* Allocate lock resource */
+    __HAL_UNLOCK(hdma);
+
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+
+    /* Disable the peripheral */
+    __HAL_DMA_DISABLE(hdma);
+
+    /* Check if the DMA Stream is effectively disabled */
+    while((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U)
+    {
+      /* Check for the Timeout */
+      if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
+      {
+        /* Update error code */
+        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+
+        /* Change the DMA state */
+        hdma->State = HAL_DMA_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+    }
+
+    /* Get the CR register value */
+    registerValue = ((DMA_Stream_TypeDef   *)hdma->Instance)->CR;
+
+    /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
+    registerValue &= ((uint32_t)~(DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
+                        DMA_SxCR_PL    | DMA_SxCR_MSIZE  | DMA_SxCR_PSIZE  | \
+                        DMA_SxCR_MINC  | DMA_SxCR_PINC   | DMA_SxCR_CIRC   | \
+                        DMA_SxCR_DIR   | DMA_SxCR_CT     | DMA_SxCR_DBM));
+
+    /* Prepare the DMA Stream configuration */
+    registerValue |=  hdma->Init.Direction           |
+            hdma->Init.PeriphInc           | hdma->Init.MemInc           |
+            hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
+            hdma->Init.Mode                | hdma->Init.Priority;
+
+    /* the Memory burst and peripheral burst are not used when the FIFO is disabled */
+    if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
+    {
+      /* Get memory burst and peripheral burst */
+      registerValue |=  hdma->Init.MemBurst | hdma->Init.PeriphBurst;
+    }
+
+    /* Work around for Errata 2.22: UART/USART- DMA transfer lock: DMA stream could be
+                                    lock when transfering data to/from USART/UART */
+#if (STM32H7_DEV_ID == 0x450UL)
+    if((DBGMCU->IDCODE & 0xFFFF0000U) >= 0x20000000U)
+    {
+#endif /* STM32H7_DEV_ID == 0x450UL */
+      if(IS_DMA_UART_USART_REQUEST(hdma->Init.Request) != 0U)
+      {
+        registerValue |= DMA_SxCR_TRBUFF;
+      }
+#if (STM32H7_DEV_ID == 0x450UL)
+    }
+#endif /* STM32H7_DEV_ID == 0x450UL */
+
+    /* Write to DMA Stream CR register */
+    ((DMA_Stream_TypeDef   *)hdma->Instance)->CR = registerValue;
+
+    /* Get the FCR register value */
+    registerValue = ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR;
+
+    /* Clear Direct mode and FIFO threshold bits */
+    registerValue &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
+
+    /* Prepare the DMA Stream FIFO configuration */
+    registerValue |= hdma->Init.FIFOMode;
+
+    /* the FIFO threshold is not used when the FIFO mode is disabled */
+    if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
+    {
+      /* Get the FIFO threshold */
+      registerValue |= hdma->Init.FIFOThreshold;
+
+      /* Check compatibility between FIFO threshold level and size of the memory burst */
+      /* for INCR4, INCR8, INCR16 */
+      if(hdma->Init.MemBurst != DMA_MBURST_SINGLE)
+      {
+        if (DMA_CheckFifoParam(hdma) != HAL_OK)
+        {
+          /* Update error code */
+          hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
+
+          /* Change the DMA state */
+          hdma->State = HAL_DMA_STATE_READY;
+
+          return HAL_ERROR;
+        }
+      }
+    }
+
+    /* Write to DMA Stream FCR */
+    ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR = registerValue;
+
+    /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
+       DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
+    regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
+
+    /* Clear all interrupt flags */
+    regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
+  }
+  else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */
+  {
+    if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U)
+    {
+      /* Check the request parameter */
+      assert_param(IS_BDMA_REQUEST(hdma->Init.Request));
+    }
+
+    /* Allocate lock resource */
+    __HAL_UNLOCK(hdma);
+
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+
+    /* Get the CR register value */
+    registerValue = ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR;
+
+    /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, MEM2MEM, DBM and CT bits */
+    registerValue &= ((uint32_t)~(BDMA_CCR_PL    | BDMA_CCR_MSIZE   | BDMA_CCR_PSIZE  | \
+                                  BDMA_CCR_MINC  | BDMA_CCR_PINC    | BDMA_CCR_CIRC   | \
+                                  BDMA_CCR_DIR   | BDMA_CCR_MEM2MEM | BDMA_CCR_DBM    | \
+                                  BDMA_CCR_CT));
+
+    /* Prepare the DMA Channel configuration */
+    registerValue |=  DMA_TO_BDMA_DIRECTION(hdma->Init.Direction)            |
+                      DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc)       |
+                      DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc)              |
+                      DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) |
+                      DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment)    |
+                      DMA_TO_BDMA_MODE(hdma->Init.Mode)                      |
+                      DMA_TO_BDMA_PRIORITY(hdma->Init.Priority);
+
+    /* Write to DMA Channel CR register */
+    ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR = registerValue;
+
+    /* calculation of the channel index */
+    hdma->StreamIndex = (((uint32_t)((uint32_t*)hdma->Instance) - (uint32_t)BDMA_Channel0) / ((uint32_t)BDMA_Channel1 - (uint32_t)BDMA_Channel0)) << 2U;
+
+    /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
+    DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
+    regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
+
+    /* Clear all interrupt flags */
+    regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
+  }
+  else
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
+    hdma->State     = HAL_DMA_STATE_ERROR;
+
+    return HAL_ERROR;
+  }
+
+  if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+  {
+    /* Initialize parameters for DMAMUX channel :
+    DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask
+    */
+    DMA_CalcDMAMUXChannelBaseAndMask(hdma);
+
+    if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
+    {
+      /* if memory to memory force the request to 0*/
+      hdma->Init.Request = DMA_REQUEST_MEM2MEM;
+    }
+
+    /* Set peripheral request  to DMAMUX channel */
+    hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);
+
+    /* Clear the DMAMUX synchro overrun flag */
+    hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+    /* Initialize parameters for DMAMUX request generator :
+    if the DMA request is DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR7
+    */
+    if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7))
+    {
+      /* Initialize parameters for DMAMUX request generator :
+      DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */
+      DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
+
+      /* Reset the DMAMUX request generator register */
+      hdma->DMAmuxRequestGen->RGCR = 0U;
+
+      /* Clear the DMAMUX request generator overrun flag */
+      hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+    }
+    else
+    {
+      hdma->DMAmuxRequestGen = 0U;
+      hdma->DMAmuxRequestGenStatus = 0U;
+      hdma->DMAmuxRequestGenStatusMask = 0U;
+    }
+  }
+
+  /* Initialize the error code */
+  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+  /* Initialize the DMA state */
+  hdma->State = HAL_DMA_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the DMA peripheral
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
+{
+  DMA_Base_Registers *regs_dma;
+  BDMA_Base_Registers *regs_bdma;
+
+  /* Check the DMA peripheral handle */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Disable the selected DMA Streamx */
+  __HAL_DMA_DISABLE(hdma);
+
+  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+  {
+    /* Reset DMA Streamx control register */
+    ((DMA_Stream_TypeDef   *)hdma->Instance)->CR   = 0U;
+
+    /* Reset DMA Streamx number of data to transfer register */
+    ((DMA_Stream_TypeDef   *)hdma->Instance)->NDTR = 0U;
+
+    /* Reset DMA Streamx peripheral address register */
+    ((DMA_Stream_TypeDef   *)hdma->Instance)->PAR  = 0U;
+
+    /* Reset DMA Streamx memory 0 address register */
+    ((DMA_Stream_TypeDef   *)hdma->Instance)->M0AR = 0U;
+
+    /* Reset DMA Streamx memory 1 address register */
+    ((DMA_Stream_TypeDef   *)hdma->Instance)->M1AR = 0U;
+
+    /* Reset DMA Streamx FIFO control register */
+    ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR  = (uint32_t)0x00000021U;
+
+    /* Get DMA steam Base Address */
+    regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
+
+    /* Clear all interrupt flags at correct offset within the register */
+    regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
+  }
+  else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */
+  {
+    /* Reset DMA Channel control register */
+    ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR  = 0U;
+
+    /* Reset DMA Channel Number of Data to Transfer register */
+    ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = 0U;
+
+    /* Reset DMA Channel peripheral address register */
+    ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR  = 0U;
+
+    /* Reset DMA Channel memory 0 address register */
+    ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = 0U;
+
+    /* Reset DMA Channel memory 1 address register */
+    ((BDMA_Channel_TypeDef *)hdma->Instance)->CM1AR = 0U;
+
+    /* Get DMA steam Base Address */
+    regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
+
+    /* Clear all interrupt flags at correct offset within the register */
+    regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
+  }
+  else
+  {
+    /* Return error status */
+    return HAL_ERROR;
+  }
+
+  if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+  {
+    /* Initialize parameters for DMAMUX channel :
+    DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */
+    DMA_CalcDMAMUXChannelBaseAndMask(hdma);
+
+    if(hdma->DMAmuxChannel != 0U)
+    {
+      /* Resett he DMAMUX channel that corresponds to the DMA stream */
+      hdma->DMAmuxChannel->CCR = 0U;
+
+      /* Clear the DMAMUX synchro overrun flag */
+      hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+    }
+
+    if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7))
+    {
+      /* Initialize parameters for DMAMUX request generator :
+      DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */
+      DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
+
+      /* Reset the DMAMUX request generator register */
+      hdma->DMAmuxRequestGen->RGCR = 0U;
+
+      /* Clear the DMAMUX request generator overrun flag */
+      hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+    }
+
+    hdma->DMAmuxRequestGen = 0U;
+    hdma->DMAmuxRequestGenStatus = 0U;
+    hdma->DMAmuxRequestGenStatusMask = 0U;
+  }
+
+
+  /* Clean callbacks */
+  hdma->XferCpltCallback       = NULL;
+  hdma->XferHalfCpltCallback   = NULL;
+  hdma->XferM1CpltCallback     = NULL;
+  hdma->XferM1HalfCpltCallback = NULL;
+  hdma->XferErrorCallback      = NULL;
+  hdma->XferAbortCallback      = NULL;
+
+  /* Initialize the error code */
+  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+  /* Initialize the DMA state */
+  hdma->State = HAL_DMA_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdma);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group2
+  *
+@verbatim
+ ===============================================================================
+                      #####  IO operation functions  #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure the source, destination address and data length and Start DMA transfer
+      (+) Configure the source, destination address and data length and
+          Start DMA transfer with interrupt
+      (+) Register and Unregister DMA callbacks
+      (+) Abort DMA transfer
+      (+) Poll for transfer complete
+      (+) Handle DMA interrupt request
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the DMA Transfer.
+  * @param  hdma      : pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @param  SrcAddress: The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  DataLength: The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+  /* Check the DMA peripheral handle */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hdma);
+
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+
+    /* Initialize the error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+    /* Disable the peripheral */
+    __HAL_DMA_DISABLE(hdma);
+
+    /* Configure the source, destination address and the data length */
+    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+    /* Enable the Peripheral */
+    __HAL_DMA_ENABLE(hdma);
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hdma);
+
+    /* Set the error code to busy */
+    hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  return status;
+}
+
+/**
+  * @brief  Start the DMA Transfer with interrupt enabled.
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @param  SrcAddress: The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  DataLength: The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+  /* Check the DMA peripheral handle */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hdma);
+
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+
+    /* Initialize the error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+    /* Disable the peripheral */
+    __HAL_DMA_DISABLE(hdma);
+
+    /* Configure the source, destination address and the data length */
+    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+    {
+      /* Enable Common interrupts*/
+      MODIFY_REG(((DMA_Stream_TypeDef   *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME));
+
+      if(hdma->XferHalfCpltCallback != NULL)
+      {
+        /* Enable Half Transfer IT if corresponding Callback is set */
+        ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  |= DMA_IT_HT;
+      }
+    }
+    else /* BDMA channel */
+    {
+      /* Enable Common interrupts */
+      MODIFY_REG(((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR, (BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE), (BDMA_CCR_TCIE | BDMA_CCR_TEIE));
+
+      if(hdma->XferHalfCpltCallback != NULL)
+      {
+        /*Enable Half Transfer IT if corresponding Callback is set */
+        ((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR  |= BDMA_CCR_HTIE;
+      }
+    }
+
+    if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+    {
+      /* Check if DMAMUX Synchronization is enabled */
+      if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
+      {
+        /* Enable DMAMUX sync overrun IT*/
+        hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
+      }
+
+      if(hdma->DMAmuxRequestGen != 0U)
+      {
+        /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
+        /* enable the request gen overrun IT */
+        hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
+      }
+    }
+
+    /* Enable the Peripheral */
+    __HAL_DMA_ENABLE(hdma);
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hdma);
+
+    /* Set the error code to busy */
+    hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Aborts the DMA Transfer.
+  * @param  hdma  : pointer to a DMA_HandleTypeDef structure that contains
+  *                 the configuration information for the specified DMA Stream.
+  *
+  * @note  After disabling a DMA Stream, a check for wait until the DMA Stream is
+  *        effectively disabled is added. If a Stream is disabled
+  *        while a data transfer is ongoing, the current data will be transferred
+  *        and the Stream will be effectively disabled only after the transfer of
+  *        this single data is finished.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
+{
+  /* calculate DMA base and stream number */
+  DMA_Base_Registers *regs_dma;
+  BDMA_Base_Registers *regs_bdma;
+  const __IO uint32_t *enableRegister;
+
+  uint32_t tickstart = HAL_GetTick();
+
+ /* Check the DMA peripheral handle */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the DMA peripheral state */
+  if(hdma->State != HAL_DMA_STATE_BUSY)
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Disable all the transfer interrupts */
+    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+    {
+       /* Disable DMA All Interrupts  */
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT);
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR &= ~(DMA_IT_FE);
+
+      enableRegister = (__IO uint32_t *)(&(((DMA_Stream_TypeDef   *)hdma->Instance)->CR));
+    }
+    else /* BDMA channel */
+    {
+      /* Disable DMA All Interrupts */
+      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR  &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE);
+
+      enableRegister = (__IO uint32_t *)(&(((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR));
+    }
+
+    if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+    {
+      /* disable the DMAMUX sync overrun IT */
+      hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
+    }
+
+    /* Disable the stream */
+    __HAL_DMA_DISABLE(hdma);
+
+    /* Check if the DMA Stream is effectively disabled */
+    while(((*enableRegister) & DMA_SxCR_EN) != 0U)
+    {
+      /* Check for the Timeout */
+      if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
+      {
+        /* Update error code */
+        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdma);
+
+        /* Change the DMA state */
+        hdma->State = HAL_DMA_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+    }
+
+    /* Clear all interrupt flags at correct offset within the register */
+    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+    {
+      regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+      regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
+    }
+    else /* BDMA channel */
+    {
+      regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
+      regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
+    }
+
+    if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+    {
+      /* Clear the DMAMUX synchro overrun flag */
+      hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+      if(hdma->DMAmuxRequestGen != 0U)
+      {
+        /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT */
+        /* disable the request gen overrun IT */
+        hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
+
+        /* Clear the DMAMUX request generator overrun flag */
+        hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+      }
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+
+    /* Change the DMA state */
+    hdma->State = HAL_DMA_STATE_READY;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Aborts the DMA Transfer in Interrupt mode.
+  * @param  hdma  : pointer to a DMA_HandleTypeDef structure that contains
+  *                 the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
+{
+  BDMA_Base_Registers *regs_bdma;
+
+  /* Check the DMA peripheral handle */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if(hdma->State != HAL_DMA_STATE_BUSY)
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+    return HAL_ERROR;
+  }
+  else
+  {
+    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+    {
+      /* Set Abort State  */
+      hdma->State = HAL_DMA_STATE_ABORT;
+
+      /* Disable the stream */
+      __HAL_DMA_DISABLE(hdma);
+    }
+    else /* BDMA channel */
+    {
+      /* Disable DMA All Interrupts  */
+      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR  &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE);
+
+      /* Disable the channel */
+      __HAL_DMA_DISABLE(hdma);
+
+      if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+      {
+        /* disable the DMAMUX sync overrun IT */
+        hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
+
+        /* Clear all flags */
+        regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
+        regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
+
+        /* Clear the DMAMUX synchro overrun flag */
+        hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+        if(hdma->DMAmuxRequestGen != 0U)
+        {
+          /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
+          /* disable the request gen overrun IT */
+          hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
+
+          /* Clear the DMAMUX request generator overrun flag */
+          hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+        }
+      }
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma);
+
+      /* Change the DMA state */
+      hdma->State = HAL_DMA_STATE_READY;
+
+      /* Call User Abort callback */
+      if(hdma->XferAbortCallback != NULL)
+      {
+        hdma->XferAbortCallback(hdma);
+      }
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Polling for transfer complete.
+  * @param  hdma:          pointer to a DMA_HandleTypeDef structure that contains
+  *                        the configuration information for the specified DMA Stream.
+  * @param  CompleteLevel: Specifies the DMA level complete.
+  * @note   The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead.
+  *         This model could be used for debug purpose.
+  * @note   The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode).
+  * @param  Timeout:       Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t cpltlevel_mask;
+  uint32_t tickstart = HAL_GetTick();
+
+  /* IT status register */
+  __IO uint32_t *isr_reg;
+  /* IT clear flag register */
+  __IO uint32_t *ifcr_reg;
+
+  /* Check the DMA peripheral handle */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if(HAL_DMA_STATE_BUSY != hdma->State)
+  {
+    /* No transfer ongoing */
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+    __HAL_UNLOCK(hdma);
+
+    return HAL_ERROR;
+  }
+
+  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+  {
+    /* Polling mode not supported in circular mode and double buffering mode */
+    if ((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CIRC) != 0U)
+    {
+      hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+      return HAL_ERROR;
+    }
+
+    /* Get the level transfer complete flag */
+    if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
+    {
+      /* Transfer Complete flag */
+      cpltlevel_mask = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU);
+    }
+    else
+    {
+      /* Half Transfer Complete flag */
+      cpltlevel_mask = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU);
+    }
+
+    isr_reg  = &(((DMA_Base_Registers *)hdma->StreamBaseAddress)->ISR);
+    ifcr_reg = &(((DMA_Base_Registers *)hdma->StreamBaseAddress)->IFCR);
+  }
+  else /* BDMA channel */
+  {
+    /* Polling mode not supported in circular mode */
+    if ((((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR & BDMA_CCR_CIRC) != 0U)
+    {
+      hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+      return HAL_ERROR;
+    }
+
+    /* Get the level transfer complete flag */
+    if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
+    {
+      /* Transfer Complete flag */
+      cpltlevel_mask = BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU);
+    }
+    else
+    {
+      /* Half Transfer Complete flag */
+      cpltlevel_mask = BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU);
+    }
+
+    isr_reg  = &(((BDMA_Base_Registers *)hdma->StreamBaseAddress)->ISR);
+    ifcr_reg = &(((BDMA_Base_Registers *)hdma->StreamBaseAddress)->IFCR);
+  }
+
+  while(((*isr_reg) & cpltlevel_mask) == 0U)
+  {
+    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+    {
+      if(((*isr_reg) & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
+      {
+        /* Update error code */
+        hdma->ErrorCode |= HAL_DMA_ERROR_FE;
+
+        /* Clear the FIFO error flag */
+        (*ifcr_reg) = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU);
+      }
+
+      if(((*isr_reg) & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
+      {
+        /* Update error code */
+        hdma->ErrorCode |= HAL_DMA_ERROR_DME;
+
+        /* Clear the Direct Mode error flag */
+        (*ifcr_reg) = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU);
+      }
+
+      if(((*isr_reg) & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
+      {
+        /* Update error code */
+        hdma->ErrorCode |= HAL_DMA_ERROR_TE;
+
+        /* Clear the transfer error flag */
+        (*ifcr_reg) = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU);
+
+        /* Change the DMA state */
+        hdma->State = HAL_DMA_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdma);
+
+        return HAL_ERROR;
+      }
+    }
+    else /* BDMA channel */
+    {
+      if(((*isr_reg) & (BDMA_FLAG_TE0 << (hdma->StreamIndex & 0x1FU))) != 0U)
+      {
+        /* When a DMA transfer error occurs */
+        /* A hardware clear of its EN bits is performed */
+        /* Clear all flags */
+        (*isr_reg) = ((BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU));
+
+        /* Update error code */
+        hdma->ErrorCode = HAL_DMA_ERROR_TE;
+
+        /* Change the DMA state */
+        hdma->State = HAL_DMA_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdma);
+
+        return HAL_ERROR;
+      }
+    }
+
+    /* Check for the Timeout (Not applicable in circular mode)*/
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
+      {
+        /* Update error code */
+        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+
+        /* if timeout then abort the current transfer */
+        /* No need to check return value: as in this case we will return HAL_ERROR with HAL_DMA_ERROR_TIMEOUT error code  */
+        (void) HAL_DMA_Abort(hdma);
+          /*
+            Note that the Abort function will
+              - Clear the transfer error flags
+              - Unlock
+              - Set the State
+          */
+
+        return HAL_ERROR;
+      }
+    }
+
+    if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+    {
+      /* Check for DMAMUX Request generator (if used) overrun status */
+      if(hdma->DMAmuxRequestGen != 0U)
+      {
+        /* if using DMAMUX request generator Check for DMAMUX request generator overrun */
+        if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
+        {
+          /* Clear the DMAMUX request generator overrun flag */
+          hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+
+          /* Update error code */
+          hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
+        }
+      }
+
+      /* Check for DMAMUX Synchronization overrun */
+      if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
+      {
+        /* Clear the DMAMUX synchro overrun flag */
+        hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+        /* Update error code */
+        hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
+      }
+    }
+  }
+
+
+  /* Get the level transfer complete flag */
+  if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
+  {
+    /* Clear the half transfer and transfer complete flags */
+    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+    {
+      (*ifcr_reg) = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << (hdma->StreamIndex & 0x1FU);
+    }
+    else /* BDMA channel */
+    {
+      (*ifcr_reg) = (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU));
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+
+    hdma->State = HAL_DMA_STATE_READY;
+  }
+  else /*CompleteLevel = HAL_DMA_HALF_TRANSFER*/
+  {
+    /* Clear the half transfer and transfer complete flags */
+    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+    {
+      (*ifcr_reg) = (DMA_FLAG_HTIF0_4) << (hdma->StreamIndex & 0x1FU);
+    }
+    else /* BDMA channel */
+    {
+      (*ifcr_reg) = (BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU));
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Handles DMA interrupt request.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Stream.
+  * @retval None
+  */
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
+{
+  uint32_t tmpisr_dma, tmpisr_bdma;
+  uint32_t ccr_reg;
+  __IO uint32_t count = 0U;
+  uint32_t timeout = SystemCoreClock / 9600U;
+
+  /* calculate DMA base and stream number */
+  DMA_Base_Registers  *regs_dma  = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+  BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
+
+  tmpisr_dma  = regs_dma->ISR;
+  tmpisr_bdma = regs_bdma->ISR;
+
+  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U)  /* DMA1 or DMA2 instance */
+  {
+    /* Transfer Error Interrupt management ***************************************/
+    if ((tmpisr_dma & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
+    {
+      if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != 0U)
+      {
+        /* Disable the transfer error interrupt */
+        ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_TE);
+
+        /* Clear the transfer error flag */
+        regs_dma->IFCR = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU);
+
+        /* Update error code */
+        hdma->ErrorCode |= HAL_DMA_ERROR_TE;
+      }
+    }
+    /* FIFO Error Interrupt management ******************************************/
+    if ((tmpisr_dma & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
+    {
+      if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != 0U)
+      {
+        /* Clear the FIFO error flag */
+        regs_dma->IFCR = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU);
+
+        /* Update error code */
+        hdma->ErrorCode |= HAL_DMA_ERROR_FE;
+      }
+    }
+    /* Direct Mode Error Interrupt management ***********************************/
+    if ((tmpisr_dma & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
+    {
+      if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != 0U)
+      {
+        /* Clear the direct mode error flag */
+        regs_dma->IFCR = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU);
+
+        /* Update error code */
+        hdma->ErrorCode |= HAL_DMA_ERROR_DME;
+      }
+    }
+    /* Half Transfer Complete Interrupt management ******************************/
+    if ((tmpisr_dma & (DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
+    {
+      if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U)
+      {
+        /* Clear the half transfer complete flag */
+        regs_dma->IFCR = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU);
+
+        /* Multi_Buffering mode enabled */
+        if(((((DMA_Stream_TypeDef   *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U)
+        {
+          /* Current memory buffer used is Memory 0 */
+          if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U)
+          {
+            if(hdma->XferHalfCpltCallback != NULL)
+            {
+              /* Half transfer callback */
+              hdma->XferHalfCpltCallback(hdma);
+            }
+          }
+          /* Current memory buffer used is Memory 1 */
+          else
+          {
+            if(hdma->XferM1HalfCpltCallback != NULL)
+            {
+              /* Half transfer callback */
+              hdma->XferM1HalfCpltCallback(hdma);
+            }
+          }
+        }
+        else
+        {
+          /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
+          if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U)
+          {
+            /* Disable the half transfer interrupt */
+            ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_HT);
+          }
+
+          if(hdma->XferHalfCpltCallback != NULL)
+          {
+            /* Half transfer callback */
+            hdma->XferHalfCpltCallback(hdma);
+          }
+        }
+      }
+    }
+    /* Transfer Complete Interrupt management ***********************************/
+    if ((tmpisr_dma & (DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
+    {
+      if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U)
+      {
+        /* Clear the transfer complete flag */
+        regs_dma->IFCR = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU);
+
+        if(HAL_DMA_STATE_ABORT == hdma->State)
+        {
+          /* Disable all the transfer interrupts */
+          ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
+          ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR &= ~(DMA_IT_FE);
+
+          if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
+          {
+            ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_HT);
+          }
+
+          /* Clear all interrupt flags at correct offset within the register */
+          regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hdma);
+
+          /* Change the DMA state */
+          hdma->State = HAL_DMA_STATE_READY;
+
+          if(hdma->XferAbortCallback != NULL)
+          {
+            hdma->XferAbortCallback(hdma);
+          }
+          return;
+        }
+
+        if(((((DMA_Stream_TypeDef   *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U)
+        {
+          /* Current memory buffer used is Memory 0 */
+          if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U)
+          {
+            if(hdma->XferM1CpltCallback != NULL)
+            {
+              /* Transfer complete Callback for memory1 */
+              hdma->XferM1CpltCallback(hdma);
+            }
+          }
+          /* Current memory buffer used is Memory 1 */
+          else
+          {
+            if(hdma->XferCpltCallback != NULL)
+            {
+              /* Transfer complete Callback for memory0 */
+              hdma->XferCpltCallback(hdma);
+            }
+          }
+        }
+        /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
+        else
+        {
+          if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U)
+          {
+            /* Disable the transfer complete interrupt */
+            ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_TC);
+
+            /* Process Unlocked */
+            __HAL_UNLOCK(hdma);
+
+            /* Change the DMA state */
+            hdma->State = HAL_DMA_STATE_READY;
+          }
+
+          if(hdma->XferCpltCallback != NULL)
+          {
+            /* Transfer complete callback */
+            hdma->XferCpltCallback(hdma);
+          }
+        }
+      }
+    }
+
+    /* manage error case */
+    if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
+    {
+      if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != 0U)
+      {
+        hdma->State = HAL_DMA_STATE_ABORT;
+
+        /* Disable the stream */
+        __HAL_DMA_DISABLE(hdma);
+
+        do
+        {
+          if (++count > timeout)
+          {
+            break;
+          }
+        }
+        while((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U);
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdma);
+
+        if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U)
+        {
+          /* Change the DMA state to error if DMA disable fails */
+          hdma->State = HAL_DMA_STATE_ERROR;
+        }
+        else
+        {
+          /* Change the DMA state to Ready if DMA disable success */
+          hdma->State = HAL_DMA_STATE_READY;
+        }
+      }
+
+      if(hdma->XferErrorCallback != NULL)
+      {
+        /* Transfer error callback */
+        hdma->XferErrorCallback(hdma);
+      }
+    }
+  }
+  else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U)  /* BDMA instance(s) */
+  {
+    ccr_reg = (((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR);
+
+    /* Half Transfer Complete Interrupt management ******************************/
+    if (((tmpisr_bdma & (BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_HTIE) != 0U))
+    {
+      /* Clear the half transfer complete flag */
+      regs_bdma->IFCR = (BDMA_ISR_HTIF0 << (hdma->StreamIndex & 0x1FU));
+
+      /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */
+      if((ccr_reg & BDMA_CCR_DBM) != 0U)
+      {
+        /* Current memory buffer used is Memory 0 */
+        if((ccr_reg & BDMA_CCR_CT) == 0U)
+        {
+          if(hdma->XferM1HalfCpltCallback != NULL)
+          {
+            /* Half transfer Callback for Memory 1 */
+            hdma->XferM1HalfCpltCallback(hdma);
+          }
+        }
+        /* Current memory buffer used is Memory 1 */
+        else
+        {
+          if(hdma->XferHalfCpltCallback != NULL)
+          {
+            /* Half transfer Callback for Memory 0 */
+            hdma->XferHalfCpltCallback(hdma);
+          }
+        }
+      }
+      else
+      {
+        if((ccr_reg & BDMA_CCR_CIRC) == 0U)
+        {
+          /* Disable the half transfer interrupt */
+          __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
+        }
+
+        /* DMA peripheral state is not updated in Half Transfer */
+        /* but in Transfer Complete case */
+
+       if(hdma->XferHalfCpltCallback != NULL)
+        {
+          /* Half transfer callback */
+          hdma->XferHalfCpltCallback(hdma);
+        }
+      }
+    }
+
+    /* Transfer Complete Interrupt management ***********************************/
+    else if (((tmpisr_bdma & (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TCIE) != 0U))
+    {
+      /* Clear the transfer complete flag */
+      regs_bdma->IFCR = (BDMA_ISR_TCIF0) << (hdma->StreamIndex & 0x1FU);
+
+      /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */
+      if((ccr_reg & BDMA_CCR_DBM) != 0U)
+      {
+        /* Current memory buffer used is Memory 0 */
+        if((ccr_reg & BDMA_CCR_CT) == 0U)
+        {
+          if(hdma->XferM1CpltCallback != NULL)
+          {
+            /* Transfer complete Callback for Memory 1 */
+            hdma->XferM1CpltCallback(hdma);
+          }
+        }
+        /* Current memory buffer used is Memory 1 */
+        else
+        {
+          if(hdma->XferCpltCallback != NULL)
+          {
+            /* Transfer complete Callback for Memory 0 */
+            hdma->XferCpltCallback(hdma);
+          }
+        }
+      }
+      else
+      {
+        if((ccr_reg & BDMA_CCR_CIRC) == 0U)
+        {
+          /* Disable the transfer complete and error interrupt, if the DMA mode is not CIRCULAR */
+          __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hdma);
+
+          /* Change the DMA state */
+          hdma->State = HAL_DMA_STATE_READY;
+        }
+
+        if(hdma->XferCpltCallback != NULL)
+        {
+          /* Transfer complete callback */
+          hdma->XferCpltCallback(hdma);
+        }
+      }
+    }
+    /* Transfer Error Interrupt management **************************************/
+    else if (((tmpisr_bdma & (BDMA_FLAG_TE0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TEIE) != 0U))
+    {
+      /* When a DMA transfer error occurs */
+      /* A hardware clear of its EN bits is performed */
+      /* Disable ALL DMA IT */
+      __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+
+      /* Clear all flags */
+      regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);
+
+      /* Update error code */
+      hdma->ErrorCode = HAL_DMA_ERROR_TE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma);
+
+      /* Change the DMA state */
+      hdma->State = HAL_DMA_STATE_READY;
+
+      if (hdma->XferErrorCallback != NULL)
+      {
+        /* Transfer error callback */
+        hdma->XferErrorCallback(hdma);
+      }
+    }
+    else
+    {
+      /* Nothing To Do */
+    }
+  }
+  else
+  {
+    /* Nothing To Do */
+  }
+}
+
+/**
+  * @brief  Register callbacks
+  * @param  hdma:                 pointer to a DMA_HandleTypeDef structure that contains
+  *                               the configuration information for the specified DMA Stream.
+  * @param  CallbackID:           User Callback identifier
+  *                               a DMA_HandleTypeDef structure as parameter.
+  * @param  pCallback:            pointer to private callback function which has pointer to
+  *                               a DMA_HandleTypeDef structure as parameter.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))
+{
+
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the DMA peripheral handle */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hdma);
+
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    switch (CallbackID)
+    {
+    case  HAL_DMA_XFER_CPLT_CB_ID:
+      hdma->XferCpltCallback = pCallback;
+      break;
+
+    case  HAL_DMA_XFER_HALFCPLT_CB_ID:
+      hdma->XferHalfCpltCallback = pCallback;
+      break;
+
+    case  HAL_DMA_XFER_M1CPLT_CB_ID:
+      hdma->XferM1CpltCallback = pCallback;
+      break;
+
+    case  HAL_DMA_XFER_M1HALFCPLT_CB_ID:
+      hdma->XferM1HalfCpltCallback = pCallback;
+      break;
+
+    case  HAL_DMA_XFER_ERROR_CB_ID:
+      hdma->XferErrorCallback = pCallback;
+      break;
+
+    case  HAL_DMA_XFER_ABORT_CB_ID:
+      hdma->XferAbortCallback = pCallback;
+      break;
+
+    default:
+      break;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdma);
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister callbacks
+  * @param  hdma:                 pointer to a DMA_HandleTypeDef structure that contains
+  *                               the configuration information for the specified DMA Stream.
+  * @param  CallbackID:           User Callback identifier
+  *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the DMA peripheral handle */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hdma);
+
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    switch (CallbackID)
+    {
+    case  HAL_DMA_XFER_CPLT_CB_ID:
+      hdma->XferCpltCallback = NULL;
+      break;
+
+    case  HAL_DMA_XFER_HALFCPLT_CB_ID:
+      hdma->XferHalfCpltCallback = NULL;
+      break;
+
+    case  HAL_DMA_XFER_M1CPLT_CB_ID:
+      hdma->XferM1CpltCallback = NULL;
+      break;
+
+    case  HAL_DMA_XFER_M1HALFCPLT_CB_ID:
+      hdma->XferM1HalfCpltCallback = NULL;
+      break;
+
+    case  HAL_DMA_XFER_ERROR_CB_ID:
+      hdma->XferErrorCallback = NULL;
+      break;
+
+    case  HAL_DMA_XFER_ABORT_CB_ID:
+      hdma->XferAbortCallback = NULL;
+      break;
+
+    case   HAL_DMA_XFER_ALL_CB_ID:
+      hdma->XferCpltCallback = NULL;
+      hdma->XferHalfCpltCallback = NULL;
+      hdma->XferM1CpltCallback = NULL;
+      hdma->XferM1HalfCpltCallback = NULL;
+      hdma->XferErrorCallback = NULL;
+      hdma->XferAbortCallback = NULL;
+      break;
+
+    default:
+      status = HAL_ERROR;
+      break;
+    }
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdma);
+
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group3
+  *
+@verbatim
+ ===============================================================================
+                    ##### State and Errors functions #####
+ ===============================================================================
+    [..]
+    This subsection provides functions allowing to
+      (+) Check the DMA state
+      (+) Get error code
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the DMA state.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Stream.
+  * @retval HAL state
+  */
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
+{
+  return hdma->State;
+}
+
+/**
+  * @brief  Return the DMA error code
+  * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA Stream.
+  * @retval DMA Error Code
+  */
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
+{
+  return hdma->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMA_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Sets the DMA Transfer parameter.
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @param  SrcAddress: The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  DataLength: The length of data to be transferred from source to destination
+  * @retval None
+  */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+  /* calculate DMA base and stream number */
+  DMA_Base_Registers  *regs_dma  = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+  BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
+
+  if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+  {
+    /* Clear the DMAMUX synchro overrun flag */
+    hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+    if(hdma->DMAmuxRequestGen != 0U)
+    {
+      /* Clear the DMAMUX request generator overrun flag */
+      hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+    }
+  }
+
+  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+  {
+    /* Clear all interrupt flags at correct offset within the register */
+    regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
+
+    /* Clear DBM bit */
+    ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= (uint32_t)(~DMA_SxCR_DBM);
+
+    /* Configure DMA Stream data length */
+    ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = DataLength;
+
+    /* Peripheral to Memory */
+    if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+    {
+      /* Configure DMA Stream destination address */
+      ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = DstAddress;
+
+      /* Configure DMA Stream source address */
+      ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = SrcAddress;
+    }
+    /* Memory to Peripheral */
+    else
+    {
+      /* Configure DMA Stream source address */
+      ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = SrcAddress;
+
+      /* Configure DMA Stream destination address */
+      ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = DstAddress;
+    }
+  }
+  else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */
+  {
+    /* Clear all flags */
+    regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);
+
+    /* Configure DMA Channel data length */
+    ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = DataLength;
+
+    /* Peripheral to Memory */
+    if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+    {
+      /* Configure DMA Channel destination address */
+      ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = DstAddress;
+
+      /* Configure DMA Channel source address */
+      ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = SrcAddress;
+    }
+    /* Memory to Peripheral */
+    else
+    {
+      /* Configure DMA Channel source address */
+      ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = SrcAddress;
+
+      /* Configure DMA Channel destination address */
+      ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = DstAddress;
+    }
+  }
+  else
+  {
+    /* Nothing To Do */
+  }
+}
+
+/**
+  * @brief  Returns the DMA Stream base address depending on stream number
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @retval Stream base address
+  */
+static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
+{
+  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+  {
+    uint32_t stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U;
+
+    /* lookup table for necessary bitshift of flags within status registers */
+    static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};
+    hdma->StreamIndex = flagBitshiftOffset[stream_number & 0x7U];
+
+    if (stream_number > 3U)
+    {
+      /* return pointer to HISR and HIFCR */
+      hdma->StreamBaseAddress = (((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)) + 4U);
+    }
+    else
+    {
+      /* return pointer to LISR and LIFCR */
+      hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU));
+    }
+  }
+  else /* BDMA instance(s) */
+  {
+    /* return pointer to ISR and IFCR */
+    hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0xFFU));
+  }
+
+  return hdma->StreamBaseAddress;
+}
+
+/**
+  * @brief  Check compatibility between FIFO threshold level and size of the memory burst
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Memory Data size equal to Byte */
+  if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)
+  {
+    switch (hdma->Init.FIFOThreshold)
+    {
+      case DMA_FIFO_THRESHOLD_1QUARTERFULL:
+      case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
+
+        if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+        {
+          status = HAL_ERROR;
+        }
+        break;
+
+      case DMA_FIFO_THRESHOLD_HALFFULL:
+        if (hdma->Init.MemBurst == DMA_MBURST_INC16)
+        {
+          status = HAL_ERROR;
+        }
+        break;
+
+      case DMA_FIFO_THRESHOLD_FULL:
+        break;
+
+      default:
+        break;
+    }
+  }
+
+  /* Memory Data size equal to Half-Word */
+  else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
+  {
+    switch (hdma->Init.FIFOThreshold)
+    {
+      case DMA_FIFO_THRESHOLD_1QUARTERFULL:
+      case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
+        status = HAL_ERROR;
+        break;
+
+      case DMA_FIFO_THRESHOLD_HALFFULL:
+        if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+        {
+          status = HAL_ERROR;
+        }
+        break;
+
+      case DMA_FIFO_THRESHOLD_FULL:
+        if (hdma->Init.MemBurst == DMA_MBURST_INC16)
+        {
+          status = HAL_ERROR;
+        }
+        break;
+
+      default:
+        break;
+    }
+  }
+
+  /* Memory Data size equal to Word */
+  else
+  {
+    switch (hdma->Init.FIFOThreshold)
+    {
+      case DMA_FIFO_THRESHOLD_1QUARTERFULL:
+      case DMA_FIFO_THRESHOLD_HALFFULL:
+      case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
+        status = HAL_ERROR;
+        break;
+
+      case DMA_FIFO_THRESHOLD_FULL:
+        if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+        {
+          status = HAL_ERROR;
+        }
+    break;
+
+      default:
+        break;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Updates the DMA handle with the DMAMUX  channel and status mask depending on stream number
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)
+{
+  uint32_t stream_number;
+  uint32_t stream_baseaddress = (uint32_t)((uint32_t*)hdma->Instance);
+
+  if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U)
+  {
+    /* BDMA Channels are connected to DMAMUX2 channels */
+    stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 8U) / 20U;
+    hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_Channel0) + (stream_number * 4U)));
+    hdma->DMAmuxChannelStatus = DMAMUX2_ChannelStatus;
+    hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU);
+  }
+  else
+  {
+    /* DMA1/DMA2 Streams are connected to DMAMUX1 channels */
+    stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U;
+
+    if((stream_baseaddress <= ((uint32_t)DMA2_Stream7) ) && \
+       (stream_baseaddress >= ((uint32_t)DMA2_Stream0)))
+    {
+      stream_number += 8U;
+    }
+    hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U)));
+    hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
+    hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU);
+  }
+}
+
+/**
+  * @brief  Updates the DMA handle with the DMAMUX  request generator params
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma)
+{
+  uint32_t request =  hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID;
+
+  if((request >= DMA_REQUEST_GENERATOR0) && (request <= DMA_REQUEST_GENERATOR7))
+  {
+    if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U)
+    {
+      /* BDMA Channels are connected to DMAMUX2 request generator blocks */
+      hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_RequestGenerator0) + ((request - 1U) * 4U)));
+
+      hdma->DMAmuxRequestGenStatus = DMAMUX2_RequestGenStatus;
+    }
+    else
+    {
+      /* DMA1 and DMA2 Streams use DMAMUX1 request generator blocks */
+      hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U)));
+
+      hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
+    }
+
+    hdma->DMAmuxRequestGenStatusMask = 1UL << (request - 1U);
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c
new file mode 100644
index 00000000..6a48d942
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c
@@ -0,0 +1,714 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_dma_ex.c
+  * @author  MCD Application Team
+  * @brief   DMA Extension HAL module driver
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the DMA Extension peripheral:
+  *           + Extended features functions
+  *
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+  The DMA Extension HAL driver can be used as follows:
+   (+) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function
+       for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.
+
+   (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
+   (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
+       Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
+       to respectively enable/disable the request generator.
+
+   (+) To handle the DMAMUX Interrupts, the function  HAL_DMAEx_MUX_IRQHandler should be called from
+       the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler or DMAMUX2_OVR_IRQHandler .
+       As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMA_MUX_IRQHandler should be
+       called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project
+      (exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator)
+
+     -@-  In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.
+     -@-  When Multi (Double) Buffer mode is enabled, the transfer is circular by default.
+     -@-  In Multi (Double) buffer mode, it is possible to update the base address for
+          the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.
+     -@-  Multi (Double) buffer mode is possible with DMA and BDMA instances.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup DMAEx DMAEx
+  * @brief DMA Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private Constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup DMAEx_Private_Functions
+  * @{
+  */
+
+static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+
+/**
+  * @}
+  */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @addtogroup DMAEx_Exported_Functions
+  * @{
+  */
+
+
+/** @addtogroup DMAEx_Exported_Functions_Group1
+  *
+@verbatim
+ ===============================================================================
+                #####  Extended features functions  #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure the source, destination address and data length and
+          Start MultiBuffer DMA transfer
+      (+) Configure the source, destination address and data length and
+          Start MultiBuffer DMA transfer with interrupt
+      (+) Change on the fly the memory0 or memory1 address.
+      (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
+      (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
+      (+) Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
+          to respectively enable/disable the request generator.
+      (+) Handle DMAMUX interrupts using HAL_DMAEx_MUX_IRQHandler : should be called from
+          the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler or DMAMUX2_OVR_IRQHandler
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Starts the multi_buffer DMA Transfer.
+  * @param  hdma      : pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @param  SrcAddress: The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer
+  * @param  DataLength: The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  __IO uint32_t *ifcRegister_Base; /* DMA Stream Interrupt Clear register */
+
+  /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+
+  /* Memory-to-memory transfer not supported in double buffering mode */
+  if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Process Locked */
+    __HAL_LOCK(hdma);
+
+    if(HAL_DMA_STATE_READY == hdma->State)
+    {
+      /* Change DMA peripheral state */
+      hdma->State = HAL_DMA_STATE_BUSY;
+
+      /* Initialize the error code */
+      hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+      if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+      {
+        /* Enable the Double buffer mode */
+        ((DMA_Stream_TypeDef   *)hdma->Instance)->CR |= DMA_SxCR_DBM;
+
+        /* Configure DMA Stream destination address */
+        ((DMA_Stream_TypeDef   *)hdma->Instance)->M1AR = SecondMemAddress;
+
+        /* Calculate the interrupt clear flag register (IFCR) base address  */
+        ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 8U));
+
+        /* Clear all flags */
+        *ifcRegister_Base = 0x3FUL << (hdma->StreamIndex & 0x1FU);
+      }
+      else /* BDMA instance(s) */
+      {
+        /* Enable the Double buffer mode */
+        ((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR |= (BDMA_CCR_DBM | BDMA_CCR_CIRC);
+
+        /* Configure DMA Stream destination address */
+        ((BDMA_Channel_TypeDef   *)hdma->Instance)->CM1AR = SecondMemAddress;
+
+        /* Calculate the interrupt clear flag register (IFCR) base address  */
+        ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 4U));
+
+        /* Clear all flags */
+        *ifcRegister_Base = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);
+      }
+
+      if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+      {
+        /* Configure the source, destination address and the data length */
+        DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+        /* Clear the DMAMUX synchro overrun flag */
+        hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+        if(hdma->DMAmuxRequestGen != 0U)
+        {
+          /* Clear the DMAMUX request generator overrun flag */
+          hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+        }
+      }
+
+      /* Enable the peripheral */
+      __HAL_DMA_ENABLE(hdma);
+    }
+    else
+    {
+      /* Set the error code to busy */
+      hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+      /* Return error status */
+      status = HAL_ERROR;
+    }
+  }
+  return status;
+}
+
+/**
+  * @brief  Starts the multi_buffer DMA Transfer with interrupt enabled.
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @param  SrcAddress: The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer
+  * @param  DataLength: The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  __IO uint32_t *ifcRegister_Base; /* DMA Stream Interrupt Clear register */
+
+  /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+
+  /* Memory-to-memory transfer not supported in double buffering mode */
+  if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hdma);
+
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+
+    /* Initialize the error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+    {
+      /* Enable the Double buffer mode */
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->CR |= DMA_SxCR_DBM;
+
+      /* Configure DMA Stream destination address */
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->M1AR = SecondMemAddress;
+
+      /* Calculate the interrupt clear flag register (IFCR) base address  */
+      ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 8U));
+
+      /* Clear all flags */
+      *ifcRegister_Base = 0x3FUL << (hdma->StreamIndex & 0x1FU);
+    }
+    else /* BDMA instance(s) */
+    {
+      /* Enable the Double buffer mode */
+      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR |= (BDMA_CCR_DBM | BDMA_CCR_CIRC);
+
+      /* Configure DMA Stream destination address */
+      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CM1AR = SecondMemAddress;
+
+      /* Calculate the interrupt clear flag register (IFCR) base address  */
+      ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 4U));
+
+      /* Clear all flags */
+      *ifcRegister_Base = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);
+    }
+
+    /* Configure the source, destination address and the data length */
+    DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+    if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+    {
+      /* Clear the DMAMUX synchro overrun flag */
+      hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+      if(hdma->DMAmuxRequestGen != 0U)
+      {
+        /* Clear the DMAMUX request generator overrun flag */
+        hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+      }
+    }
+
+    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+    {
+      /* Enable Common interrupts*/
+      MODIFY_REG(((DMA_Stream_TypeDef   *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME));
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR |= DMA_IT_FE;
+
+      if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
+      {
+        /*Enable Half Transfer IT if corresponding Callback is set*/
+        ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  |= DMA_IT_HT;
+      }
+    }
+    else /* BDMA instance(s) */
+    {
+      /* Enable Common interrupts*/
+      MODIFY_REG(((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR, (BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE), (BDMA_CCR_TCIE | BDMA_CCR_TEIE));
+
+      if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
+      {
+        /*Enable Half Transfer IT if corresponding Callback is set*/
+        ((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR  |= BDMA_CCR_HTIE;
+      }
+    }
+
+    if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+    {
+      /* Check if DMAMUX Synchronization is enabled*/
+      if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
+      {
+        /* Enable DMAMUX sync overrun IT*/
+        hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
+      }
+
+      if(hdma->DMAmuxRequestGen != 0U)
+      {
+        /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
+        /* enable the request gen overrun IT*/
+        hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
+      }
+    }
+
+    /* Enable the peripheral */
+    __HAL_DMA_ENABLE(hdma);
+  }
+  else
+  {
+    /* Set the error code to busy */
+    hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+  return status;
+}
+
+/**
+  * @brief  Change the memory0 or memory1 address on the fly.
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @param  Address:    The new address
+  * @param  memory:     the memory to be changed, This parameter can be one of
+  *                     the following values:
+  *                      MEMORY0 /
+  *                      MEMORY1
+  * @note   The MEMORY0 address can be changed only when the current transfer use
+  *         MEMORY1 and the MEMORY1 address can be changed only when the current
+  *         transfer use MEMORY0.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)
+{
+  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+  {
+    if(memory == MEMORY0)
+    {
+      /* change the memory0 address */
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->M0AR = Address;
+    }
+    else
+    {
+      /* change the memory1 address */
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->M1AR = Address;
+    }
+  }
+  else /* BDMA instance(s) */
+  {
+    if(memory == MEMORY0)
+    {
+      /* change the memory0 address */
+      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CM0AR = Address;
+    }
+    else
+    {
+      /* change the memory1 address */
+      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CM1AR = Address;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the DMAMUX synchronization parameters for a given DMA stream (instance).
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @param  pSyncConfig : pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the DMAMUX synchronization parameters
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)
+{
+  uint32_t syncSignalID = 0;
+  uint32_t syncPolarity = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));
+  assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable));
+  assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable));
+  assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber));
+
+  if(pSyncConfig->SyncEnable == ENABLE)
+  {
+    assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig->SyncPolarity));
+
+    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+    {
+      assert_param(IS_DMA_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));
+    }
+    else
+    {
+      assert_param(IS_BDMA_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));
+    }
+    syncSignalID = pSyncConfig->SyncSignalID;
+    syncPolarity = pSyncConfig->SyncPolarity;
+  }
+
+  /*Check if the DMA state is ready */
+  if(hdma->State == HAL_DMA_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hdma);
+
+    /* Disable the synchronization and event generation before applying a new config */
+    CLEAR_BIT(hdma->DMAmuxChannel->CCR,(DMAMUX_CxCR_SE | DMAMUX_CxCR_EGE));
+
+    /* Set the new synchronization parameters (and keep the request ID filled during the Init)*/
+    MODIFY_REG( hdma->DMAmuxChannel->CCR, \
+               (~DMAMUX_CxCR_DMAREQ_ID) , \
+               (syncSignalID << DMAMUX_CxCR_SYNC_ID_Pos)       | \
+               ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \
+               syncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos)    | \
+               ((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos));
+
+      /* Process Locked */
+    __HAL_UNLOCK(hdma);
+
+    return HAL_OK;
+  }
+  else
+  {
+    /* Set the error code to busy */
+    hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+    /* Return error status */
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the DMAMUX request generator block used by the given DMA stream (instance).
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @param  pRequestGeneratorConfig : pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef :
+  *         contains the request generator parameters.
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
+{
+  HAL_StatusTypeDef status;
+  HAL_DMA_StateTypeDef temp_state = hdma->State;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));
+
+  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+  {
+    assert_param(IS_DMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));
+  }
+  else
+  {
+    assert_param(IS_BDMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));
+  }
+
+
+  assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity));
+  assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber));
+
+  /* check if the DMA state is ready
+     and DMA is using a DMAMUX request generator block
+  */
+  if(hdma->DMAmuxRequestGen == 0U)
+  {
+    /* Set the error code to busy */
+    hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
+
+    /* error status */
+    status = HAL_ERROR;
+  }
+  else if(((hdma->DMAmuxRequestGen->RGCR & DMAMUX_RGxCR_GE) == 0U) && (temp_state == HAL_DMA_STATE_READY))
+  {
+    /* RequestGenerator must be disable prior to the configuration i.e GE bit is 0 */
+
+    /* Process Locked */
+    __HAL_LOCK(hdma);
+
+    /* Set the request generator new parameters */
+    hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \
+                                  ((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GNBREQ_Pos)| \
+                                  pRequestGeneratorConfig->Polarity;
+    /* Process Locked */
+    __HAL_UNLOCK(hdma);
+
+    return HAL_OK;
+  }
+  else
+  {
+    /* Set the error code to busy */
+    hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+    /* error status */
+    status = HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Enable the DMAMUX request generator block used by the given DMA stream (instance).
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));
+
+  /* check if the DMA state is ready
+     and DMA is using a DMAMUX request generator block */
+  if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0U))
+  {
+    /* Enable the request generator*/
+    hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE;
+
+   return HAL_OK;
+ }
+ else
+ {
+   return HAL_ERROR;
+ }
+}
+
+/**
+  * @brief  Disable the DMAMUX request generator block used by the given DMA stream (instance).
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));
+
+  /* check if the DMA state is ready
+     and DMA is using a DMAMUX request generator block */
+  if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0U))
+  {
+    /* Disable the request generator*/
+    hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE;
+
+   return HAL_OK;
+ }
+ else
+ {
+   return HAL_ERROR;
+ }
+}
+
+/**
+  * @brief  Handles DMAMUX interrupt request.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Stream.
+  * @retval None
+  */
+void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma)
+{
+  /* Check for DMAMUX Synchronization overrun */
+  if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
+  {
+    /* Disable the synchro overrun interrupt */
+    hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
+
+    /* Clear the DMAMUX synchro overrun flag */
+    hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+    /* Update error code */
+    hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
+
+    if(hdma->XferErrorCallback != NULL)
+    {
+      /* Transfer error callback */
+      hdma->XferErrorCallback(hdma);
+    }
+  }
+
+  if(hdma->DMAmuxRequestGen != 0)
+  {
+   /* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */
+    if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
+    {
+      /* Disable the request gen overrun interrupt */
+      hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
+
+      /* Clear the DMAMUX request generator overrun flag */
+      hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+
+      /* Update error code */
+      hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
+
+      if(hdma->XferErrorCallback != NULL)
+      {
+        /* Transfer error callback */
+        hdma->XferErrorCallback(hdma);
+      }
+    }
+  }
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMAEx_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Set the DMA Transfer parameter.
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @param  SrcAddress: The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  DataLength: The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+  {
+    /* Configure DMA Stream data length */
+    ((DMA_Stream_TypeDef   *)hdma->Instance)->NDTR = DataLength;
+
+    /* Peripheral to Memory */
+    if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+    {
+      /* Configure DMA Stream destination address */
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->PAR = DstAddress;
+
+      /* Configure DMA Stream source address */
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->M0AR = SrcAddress;
+    }
+    /* Memory to Peripheral */
+    else
+    {
+      /* Configure DMA Stream source address */
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->PAR = SrcAddress;
+
+      /* Configure DMA Stream destination address */
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->M0AR = DstAddress;
+    }
+  }
+  else /* BDMA instance(s) */
+  {
+    /* Configure DMA Stream data length */
+    ((BDMA_Channel_TypeDef   *)hdma->Instance)->CNDTR = DataLength;
+
+    /* Peripheral to Memory */
+    if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+    {
+      /* Configure DMA Stream destination address */
+      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CPAR = DstAddress;
+
+      /* Configure DMA Stream source address */
+      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CM0AR = SrcAddress;
+    }
+    /* Memory to Peripheral */
+    else
+    {
+      /* Configure DMA Stream source address */
+      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CPAR = SrcAddress;
+
+      /* Configure DMA Stream destination address */
+      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CM0AR = DstAddress;
+    }
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c
new file mode 100644
index 00000000..ffb5deef
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c
@@ -0,0 +1,877 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_exti.c
+  * @author  MCD Application Team
+  * @brief   EXTI HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the General Purpose Input/Output (EXTI) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *
+  @verbatim
+  ==============================================================================
+                    ##### EXTI Peripheral features #####
+  ==============================================================================
+  [..]
+    (+) Each Exti line can be configured within this driver.
+
+    (+) Exti line can be configured in 3 different modes
+        (++) Interrupt (CORE1 or CORE2 in case of dual core line )
+        (++) Event (CORE1 or CORE2 in case of dual core line )
+        (++) a combination of the previous
+
+    (+) Configurable Exti lines can be configured with 3 different triggers
+        (++) Rising
+        (++) Falling
+        (++) Both of them
+
+    (+) When set in interrupt mode, configurable Exti lines have two diffenrents
+        interrupt pending registers which allow to distinguish which transition
+        occurs:
+        (++) Rising edge pending interrupt
+        (++) Falling
+
+    (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
+        be selected throught multiplexer.
+
+    (+) PendClearSource used to set the D3 Smart Run Domain autoamtic pend clear soure.
+        It is applicable for line with wkaeup target is Any (CPU1 , CPU2 and D3 smart run domain).
+        Value can be one of the following:
+        (++)  EXTI_D3_PENDCLR_SRC_NONE : no pend clear source is selcted :
+              In this case corresponding bit of D2PMRx register is set to 0
+                (+++) On a configurable Line : the D3 domain wakeup signal is
+                      automatically cleared after after the Delay + Rising Edge detect
+                (+++) On a direct Line : the D3 domain wakeup signal is
+                      cleared after the direct event input signal is cleared
+
+        (++)  EXTI_D3_PENDCLR_SRC_DMACH6 : no pend clear source is selcted :
+              In this case corresponding bit of D2PMRx register is set to 1
+              and corresponding bits(2) of D3PCRxL/H is set to b00 :
+                DMA ch6 event selected as D3 domain pendclear source
+
+        (++)  EXTI_D3_PENDCLR_SRC_DMACH7 : no pend clear source is selcted :
+              In this case corresponding bit of D2PMRx register is set to 1
+              and corresponding bits(2) of D3PCRxL/H is set to b01 :
+                DMA ch7 event selected as D3 domain pendclear source
+
+        (++)  EXTI_D3_PENDCLR_SRC_LPTIM4 : no pend clear source is selcted :
+              In this case corresponding bit of D2PMRx register is set to 1
+              and corresponding bits(2) of D3PCRxL/H is set to b10 :
+                LPTIM4 out selected as D3 domain pendclear source
+
+        (++)  EXTI_D3_PENDCLR_SRC_LPTIM5 : no pend clear source is selcted :
+              In this case corresponding bit of D2PMRx register is set to 1
+              and corresponding bits(2) of D3PCRxL/H is set to b11 :
+                LPTIM5 out selected as D3 domain pendclear source
+
+
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+
+    (#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
+        (++) Choose the interrupt line number by setting "Line" member from
+             EXTI_ConfigTypeDef structure.
+        (++) Configure the interrupt and/or event mode using "Mode" member from
+             EXTI_ConfigTypeDef structure.
+        (++) For configurable lines, configure rising and/or falling trigger
+             "Trigger" member from EXTI_ConfigTypeDef structure.
+        (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
+             member from GPIO_InitTypeDef structure.
+        (++) For Exti lines with wkaeup target is Any (CPU1 , CPU2 and D3 smart run domain),
+             choose gpio D3 PendClearSource using PendClearSource
+             member from EXTI_PendClear_Source structure.
+
+    (#) Get current Exti configuration of a dedicated line using
+        HAL_EXTI_GetConfigLine().
+        (++) Provide exiting handle as parameter.
+        (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
+
+    (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
+        (++) Provide exiting handle as parameter.
+
+    (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
+        (++) Provide exiting handle as first parameter.
+        (++) Provide which callback will be registered using one value from
+             EXTI_CallbackIDTypeDef.
+        (++) Provide callback function pointer.
+
+    (#) Get interrupt pending bit using HAL_EXTI_GetPending().
+
+    (#) Clear interrupt pending bit using HAL_EXTI_GetPending().
+
+    (#) Generate software interrupt using HAL_EXTI_GenerateSWI().
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup EXTI
+  * @{
+  */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines ------------------------------------------------------------*/
+/** @defgroup EXTI_Private_Constants EXTI Private Constants
+  * @{
+  */
+#define EXTI_MODE_OFFSET                    0x04U   /* 0x10: offset between CPU IMR/EMR registers */
+#define EXTI_CONFIG_OFFSET                  0x08U   /* 0x20: offset between CPU Rising/Falling configuration registers */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup EXTI_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup EXTI_Exported_Functions_Group1
+ *  @brief    Configuration functions
+ *
+@verbatim
+ ===============================================================================
+              ##### Configuration functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Set configuration of a dedicated Exti line.
+  * @param  hexti Exti handle.
+  * @param  pExtiConfig Pointer on EXTI configuration to be set.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
+{
+  __IO uint32_t *regaddr;
+  uint32_t regval;
+  uint32_t linepos;
+  uint32_t maskline;
+  uint32_t offset;
+  uint32_t pcrlinepos;
+
+  /* Check null pointer */
+  if ((hexti == NULL) || (pExtiConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(pExtiConfig->Line));
+  assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
+
+  /* Assign line number to handle */
+  hexti->Line = pExtiConfig->Line;
+
+  /* compute line register offset and line mask */
+  offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
+  maskline = (1UL << linepos);
+
+  /* Configure triggers for configurable lines */
+  if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00U)
+  {
+    assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
+
+    /* Configure rising trigger */
+    regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = *regaddr;
+
+    /* Mask or set line */
+    if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00U)
+    {
+      regval |= maskline;
+    }
+    else
+    {
+      regval &= ~maskline;
+    }
+
+    /* Store rising trigger mode */
+    *regaddr = regval;
+
+    /* Configure falling trigger */
+    regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = *regaddr;
+
+    /* Mask or set line */
+    if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00U)
+    {
+      regval |= maskline;
+    }
+    else
+    {
+      regval &= ~maskline;
+    }
+
+    /* Store falling trigger mode */
+    *regaddr = regval;
+
+    /* Configure gpio port selection in case of gpio exti line */
+    if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
+    {
+      assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
+      assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+      regval = SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL];
+      regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03U)));
+      regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03U)));
+      SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL] = regval;
+    }
+  }
+
+  /* Configure interrupt mode : read current mode */
+  regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = *regaddr;
+
+  /* Mask or set line */
+  if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00U)
+  {
+    regval |= maskline;
+  }
+  else
+  {
+    regval &= ~maskline;
+  }
+
+  /* Store interrupt mode */
+  *regaddr = regval;
+
+  /* The event mode cannot be configured if the line does not support it */
+  assert_param(((pExtiConfig->Line & EXTI_EVENT) == EXTI_EVENT) || ((pExtiConfig->Mode & EXTI_MODE_EVENT) != EXTI_MODE_EVENT));
+
+  /* Configure event mode : read current mode */
+  regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = *regaddr;
+
+  /* Mask or set line */
+  if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00U)
+  {
+    regval |= maskline;
+  }
+  else
+  {
+    regval &= ~maskline;
+  }
+
+  /* Store event mode */
+  *regaddr = regval;
+
+#if defined (DUAL_CORE)
+  /* Configure interrupt mode for Core2 : read current mode */
+  regaddr = (__IO uint32_t *)(&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = *regaddr;
+
+  /* Mask or set line */
+  if ((pExtiConfig->Mode & EXTI_MODE_CORE2_INTERRUPT) != 0x00U)
+  {
+    regval |= maskline;
+  }
+  else
+  {
+    regval &= ~maskline;
+  }
+
+  /* Store interrupt mode */
+  *regaddr = regval;
+
+  /* The event mode cannot be configured if the line does not support it */
+  assert_param(((pExtiConfig->Line & EXTI_EVENT) == EXTI_EVENT) || ((pExtiConfig->Mode & EXTI_MODE_CORE2_EVENT) != EXTI_MODE_CORE2_EVENT));
+
+  /* Configure event mode : read current mode */
+  regaddr = (__IO uint32_t *)(&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = *regaddr;
+
+  /* Mask or set line */
+  if ((pExtiConfig->Mode & EXTI_MODE_CORE2_EVENT) != 0x00U)
+  {
+    regval |= maskline;
+  }
+  else
+  {
+    regval &= ~maskline;
+  }
+
+  /* Store event mode */
+  *regaddr = regval;
+#endif /* DUAL_CORE */
+
+  /* Configure the D3 PendClear source in case of Wakeup target is Any */
+  if ((pExtiConfig->Line & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL)
+  {
+    assert_param(IS_EXTI_D3_PENDCLR_SRC(pExtiConfig->PendClearSource));
+
+    /*Calc the PMR register address for the given line */
+    regaddr = (__IO uint32_t *)(&EXTI->D3PMR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = *regaddr;
+
+    if(pExtiConfig->PendClearSource == EXTI_D3_PENDCLR_SRC_NONE)
+    {
+      /* Clear D3PMRx register for the given line */
+      regval &= ~maskline;
+      /* Store D3PMRx register value */
+      *regaddr = regval;
+    }
+    else
+    {
+      /* Set D3PMRx register to 1 for the given line */
+      regval |= maskline;
+      /* Store D3PMRx register value */
+      *regaddr = regval;
+
+      if(linepos < 16UL)
+      {
+        regaddr = (__IO uint32_t *)(&EXTI->D3PCR1L + (EXTI_CONFIG_OFFSET * offset));
+        pcrlinepos = 1UL << linepos;
+      }
+      else
+      {
+        regaddr = (__IO uint32_t *)(&EXTI->D3PCR1H + (EXTI_CONFIG_OFFSET * offset));
+        pcrlinepos = 1UL << (linepos - 16UL);
+      }
+
+      regval = (*regaddr & (~(pcrlinepos * pcrlinepos * 3UL))) | (pcrlinepos * pcrlinepos * (pExtiConfig->PendClearSource - 1UL));
+      *regaddr = regval;
+    }
+  }
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Get configuration of a dedicated Exti line.
+  * @param  hexti Exti handle.
+  * @param  pExtiConfig Pointer on structure to store Exti configuration.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
+{
+  __IO uint32_t *regaddr;
+  uint32_t regval;
+  uint32_t linepos;
+  uint32_t maskline;
+  uint32_t offset;
+  uint32_t pcrlinepos;
+
+  /* Check null pointer */
+  if ((hexti == NULL) || (pExtiConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameter */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+
+  /* Store handle line number to configuration structure */
+  pExtiConfig->Line = hexti->Line;
+
+  /* compute line register offset and line mask */
+  offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
+  maskline = (1UL << linepos);
+
+  /* 1] Get core mode : interrupt */
+  regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = *regaddr;
+
+  pExtiConfig->Mode = EXTI_MODE_NONE;
+
+  /* Check if selected line is enable */
+  if ((regval & maskline) != 0x00U)
+  {
+    pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
+  }
+
+  /* Get event mode */
+  regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = *regaddr;
+
+  /* Check if selected line is enable */
+  if ((regval & maskline) != 0x00U)
+  {
+    pExtiConfig->Mode |= EXTI_MODE_EVENT;
+  }
+#if defined (DUAL_CORE)
+  regaddr = (__IO uint32_t *)(&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = *regaddr;
+
+  /* Check if selected line is enable */
+  if ((regval & maskline) != 0x00U)
+  {
+    pExtiConfig->Mode = EXTI_MODE_CORE2_INTERRUPT;
+  }
+
+  /* Get event mode */
+  regaddr = (__IO uint32_t *)(&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = *regaddr;
+
+  /* Check if selected line is enable */
+  if ((regval & maskline) != 0x00U)
+  {
+    pExtiConfig->Mode |= EXTI_MODE_CORE2_EVENT;
+  }
+#endif /*DUAL_CORE*/
+
+  /* 2] Get trigger for configurable lines : rising */
+  if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00U)
+  {
+    regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = *regaddr;
+
+    /* Check if configuration of selected line is enable */
+    if ((regval & maskline) != 0x00U)
+    {
+      pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
+    }
+    else
+    {
+      pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
+    }
+
+    /* Get falling configuration */
+    regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = *regaddr;
+
+    /* Check if configuration of selected line is enable */
+    if ((regval & maskline) != 0x00U)
+    {
+      pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
+    }
+
+    /* Get Gpio port selection for gpio lines */
+    if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
+    {
+      assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+      regval = SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL];
+      pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3UL - (linepos & 0x03UL)))) >> 24U);
+    }
+    else
+    {
+      pExtiConfig->GPIOSel = 0x00U;
+    }
+  }
+  else
+  {
+    pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
+    pExtiConfig->GPIOSel = 0x00U;
+  }
+
+  /* 3] Get D3 Pend Clear source */
+  if ((pExtiConfig->Line & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL)
+  {
+    regaddr = (__IO uint32_t *)(&EXTI->D3PMR1 + (EXTI_CONFIG_OFFSET * offset));
+    if(((*regaddr) & linepos) == 0UL)
+    {
+      /* if PMR unset, then no pend clear source is used */
+      pExtiConfig->PendClearSource = EXTI_D3_PENDCLR_SRC_NONE;
+    }
+    else
+    {
+      /* if wakeup target is any and PMR set, the read pend clear source from  D3PCRxL/H */
+      if(linepos < 16UL)
+      {
+        regaddr = (__IO uint32_t *)(&EXTI->D3PCR1L + (EXTI_CONFIG_OFFSET * offset));
+        pcrlinepos = 1UL << linepos;
+      }
+      else
+      {
+        regaddr = (__IO uint32_t *)(&EXTI->D3PCR1H + (EXTI_CONFIG_OFFSET * offset));
+        pcrlinepos = 1UL << (linepos - 16UL);
+      }
+
+      pExtiConfig->PendClearSource = 1UL + ((*regaddr & (pcrlinepos * pcrlinepos * 3UL)) / (pcrlinepos * pcrlinepos));
+    }
+  }
+  else
+  {
+    /* if line wakeup target is not any, then no pend clear source is used  */
+    pExtiConfig->PendClearSource = EXTI_D3_PENDCLR_SRC_NONE;
+  }
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Clear whole configuration of a dedicated Exti line.
+  * @param  hexti Exti handle.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
+{
+  __IO uint32_t *regaddr;
+  uint32_t regval;
+  uint32_t linepos;
+  uint32_t maskline;
+  uint32_t offset;
+  uint32_t pcrlinepos;
+
+  /* Check null pointer */
+  if (hexti == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameter */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+
+  /* compute line register offset and line mask */
+  offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  linepos = (hexti->Line & EXTI_PIN_MASK);
+  maskline = (1UL << linepos);
+
+  /* 1] Clear interrupt mode */
+  regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = (*regaddr & ~maskline);
+  *regaddr = regval;
+
+  /* 2] Clear event mode */
+  regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = (*regaddr & ~maskline);
+  *regaddr = regval;
+
+#if defined (DUAL_CORE)
+    /* 1] Clear CM4 interrupt mode */
+  regaddr = (__IO uint32_t *)(&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = (*regaddr & ~maskline);
+  *regaddr = regval;
+
+  /* 2] Clear CM4 event mode */
+  regaddr = (__IO uint32_t *)(&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = (*regaddr & ~maskline);
+  *regaddr = regval;
+#endif /* DUAL_CORE */
+
+  /* 3] Clear triggers in case of configurable lines */
+  if ((hexti->Line & EXTI_CONFIG) != 0x00U)
+  {
+    regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = (*regaddr & ~maskline);
+    *regaddr = regval;
+
+    regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = (*regaddr & ~maskline);
+    *regaddr = regval;
+
+    /* Get Gpio port selection for gpio lines */
+    if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
+    {
+      assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+      regval = SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL];
+      regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03UL)));
+      SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL] = regval;
+    }
+  }
+
+  /* 4] Clear D3 Config lines */
+  if ((hexti->Line & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL)
+  {
+    regaddr = (__IO uint32_t *)(&EXTI->D3PMR1 + (EXTI_CONFIG_OFFSET * offset));
+    *regaddr = (*regaddr & ~maskline);
+
+    if(linepos < 16UL)
+    {
+      regaddr = (__IO uint32_t *)(&EXTI->D3PCR1L + (EXTI_CONFIG_OFFSET * offset));
+      pcrlinepos = 1UL << linepos;
+    }
+    else
+    {
+      regaddr = (__IO uint32_t *)(&EXTI->D3PCR1H + (EXTI_CONFIG_OFFSET * offset));
+      pcrlinepos = 1UL << (linepos - 16UL);
+    }
+
+    /*Clear D3 PendClear source */
+    *regaddr &= (~(pcrlinepos * pcrlinepos * 3UL));
+  }
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Register callback for a dedicated Exti line.
+  * @param  hexti Exti handle.
+  * @param  CallbackID User callback identifier.
+  *         This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
+  * @param  pPendingCbfn function pointer to be stored as callback.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check null pointer */
+  if (hexti == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  switch (CallbackID)
+  {
+    case  HAL_EXTI_COMMON_CB_ID:
+      hexti->PendingCallback = pPendingCbfn;
+      break;
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  return status;
+}
+
+
+/**
+  * @brief  Store line number as handle private field.
+  * @param  hexti Exti handle.
+  * @param  ExtiLine Exti line number.
+  *         This parameter can be from 0 to @ref EXTI_LINE_NB.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
+{
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(ExtiLine));
+
+  /* Check null pointer */
+  if (hexti == NULL)
+  {
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Store line number as handle private field */
+    hexti->Line = ExtiLine;
+
+    return HAL_OK;
+  }
+}
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup EXTI_Exported_Functions_Group2
+ *  @brief EXTI IO functions.
+ *
+@verbatim
+ ===============================================================================
+                       ##### IO operation functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Handle EXTI interrupt request.
+  * @param  hexti Exti handle.
+  * @retval none.
+  */
+void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
+{
+  __IO uint32_t *regaddr;
+  uint32_t regval;
+  uint32_t maskline;
+  uint32_t offset;
+
+  /* Compute line register offset and line mask */
+  offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  maskline = (1UL << (hexti->Line & EXTI_PIN_MASK));
+
+#if defined(DUAL_CORE)
+  if (HAL_GetCurrentCPUID() == CM7_CPUID)
+  {
+    /* Get pending register address */
+    regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
+  }
+  else /* Cortex-M4*/
+  {
+    /* Get pending register address */
+    regaddr = (__IO uint32_t *)(&EXTI->C2PR1 + (EXTI_MODE_OFFSET * offset));
+  }
+#else
+  regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
+#endif /* DUAL_CORE */
+
+  /* Get pending bit  */
+  regval = (*regaddr & maskline);
+
+  if (regval != 0x00U)
+  {
+    /* Clear pending bit */
+    *regaddr = maskline;
+
+    /* Call callback */
+    if (hexti->PendingCallback != NULL)
+    {
+      hexti->PendingCallback();
+    }
+  }
+}
+
+
+/**
+  * @brief  Get interrupt pending bit of a dedicated line.
+  * @param  hexti Exti handle.
+  * @param  Edge Specify which pending edge as to be checked.
+  *         This parameter can be one of the following values:
+  *           @arg @ref EXTI_TRIGGER_RISING_FALLING
+  *         This parameter is kept for compatibility with other series.
+  * @retval 1 if interrupt is pending else 0.
+  */
+uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
+{
+  __IO uint32_t *regaddr;
+  uint32_t regval;
+  uint32_t linepos;
+  uint32_t maskline;
+  uint32_t offset;
+
+  /* Check parameters */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+  assert_param(IS_EXTI_PENDING_EDGE(Edge));
+
+  /* compute line register offset and line mask */
+  offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  linepos = (hexti->Line & EXTI_PIN_MASK);
+  maskline = (1UL << linepos);
+
+#if defined(DUAL_CORE)
+  if (HAL_GetCurrentCPUID() == CM7_CPUID)
+  {
+    /* Get pending register address */
+    regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
+  }
+  else /* Cortex-M4 */
+  {
+    /* Get pending register address */
+    regaddr = (__IO uint32_t *)(&EXTI->C2PR1 + (EXTI_MODE_OFFSET * offset));
+  }
+#else
+  regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
+#endif /* DUAL_CORE */
+
+  /* return 1 if bit is set else 0 */
+  regval = ((*regaddr & maskline) >> linepos);
+  return regval;
+}
+
+
+/**
+  * @brief  Clear interrupt pending bit of a dedicated line.
+  * @param  hexti Exti handle.
+  * @param  Edge Specify which pending edge as to be clear.
+  *         This parameter can be one of the following values:
+  *           @arg @ref EXTI_TRIGGER_RISING_FALLING
+  *         This parameter is kept for compatibility with other series.
+  * @retval None.
+  */
+void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
+{
+  __IO uint32_t *regaddr;
+  uint32_t maskline;
+  uint32_t offset;
+
+  /* Check parameters */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+  assert_param(IS_EXTI_PENDING_EDGE(Edge));
+
+  /* compute line register offset and line mask */
+  offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  maskline = (1UL << (hexti->Line & EXTI_PIN_MASK));
+
+#if defined(DUAL_CORE)
+  if (HAL_GetCurrentCPUID() == CM7_CPUID)
+  {
+    /* Get pending register address */
+    regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
+  }
+  else /* Cortex-M4 */
+  {
+    /* Get pending register address */
+    regaddr = (__IO uint32_t *)(&EXTI->C2PR1 + (EXTI_MODE_OFFSET * offset));
+  }
+#else
+  regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
+#endif /* DUAL_CORE */
+
+  /* Clear Pending bit */
+  *regaddr =  maskline;
+}
+
+/**
+  * @brief  Generate a software interrupt for a dedicated line.
+  * @param  hexti Exti handle.
+  * @retval None.
+  */
+void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
+{
+  __IO uint32_t *regaddr;
+  uint32_t maskline;
+  uint32_t offset;
+
+  /* Check parameters */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+
+  /* compute line register offset and line mask */
+  offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  maskline = (1UL << (hexti->Line & EXTI_PIN_MASK));
+
+  regaddr = (__IO uint32_t *)(&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset));
+  *regaddr = maskline;
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_EXTI_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c
new file mode 100644
index 00000000..7505fd5a
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c
@@ -0,0 +1,6169 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_fdcan.c
+  * @author  MCD Application Team
+  * @brief   FDCAN HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Flexible DataRate Controller Area Network
+  *          (FDCAN) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Configuration and Control functions
+  *           + Peripheral State and Error functions
+  *
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      (#) Initialize the FDCAN peripheral using HAL_FDCAN_Init function.
+
+      (#) If needed , configure the reception filters and optional features using
+          the following configuration functions:
+            (++) HAL_FDCAN_ConfigClockCalibration
+            (++) HAL_FDCAN_ConfigFilter
+            (++) HAL_FDCAN_ConfigGlobalFilter
+            (++) HAL_FDCAN_ConfigExtendedIdMask
+            (++) HAL_FDCAN_ConfigRxFifoOverwrite
+            (++) HAL_FDCAN_ConfigFifoWatermark
+            (++) HAL_FDCAN_ConfigRamWatchdog
+            (++) HAL_FDCAN_ConfigTimestampCounter
+            (++) HAL_FDCAN_EnableTimestampCounter
+            (++) HAL_FDCAN_DisableTimestampCounter
+            (++) HAL_FDCAN_ConfigTimeoutCounter
+            (++) HAL_FDCAN_EnableTimeoutCounter
+            (++) HAL_FDCAN_DisableTimeoutCounter
+            (++) HAL_FDCAN_ConfigTxDelayCompensation
+            (++) HAL_FDCAN_EnableTxDelayCompensation
+            (++) HAL_FDCAN_DisableTxDelayCompensation
+            (++) HAL_FDCAN_EnableISOMode
+            (++) HAL_FDCAN_DisableISOMode
+            (++) HAL_FDCAN_EnableEdgeFiltering
+            (++) HAL_FDCAN_DisableEdgeFiltering
+            (++) HAL_FDCAN_TT_ConfigOperation
+            (++) HAL_FDCAN_TT_ConfigReferenceMessage
+            (++) HAL_FDCAN_TT_ConfigTrigger
+
+      (#) Start the FDCAN module using HAL_FDCAN_Start function. At this level
+          the node is active on the bus: it can send and receive messages.
+
+      (#) The following Tx control functions can only be called when the FDCAN
+          module is started:
+            (++) HAL_FDCAN_AddMessageToTxFifoQ
+            (++) HAL_FDCAN_EnableTxBufferRequest
+            (++) HAL_FDCAN_AbortTxRequest
+
+      (#) After having submitted a Tx request in Tx Fifo or Queue, it is possible to
+          get Tx buffer location used to place the Tx request thanks to
+          HAL_FDCAN_GetLatestTxFifoQRequestBuffer API.
+          It is then possible to abort later on the corresponding Tx Request using
+          HAL_FDCAN_AbortTxRequest API.
+
+      (#) When a message is received into the FDCAN message RAM, it can be
+          retrieved using the HAL_FDCAN_GetRxMessage function.
+
+      (#) Calling the HAL_FDCAN_Stop function stops the FDCAN module by entering
+          it to initialization mode and re-enabling access to configuration
+          registers through the configuration functions listed here above.
+
+      (#) All other control functions can be called any time after initialization
+          phase, no matter if the FDCAN module is started or stoped.
+
+      *** Polling mode operation ***
+      ==============================
+
+    [..]
+        (#) Reception and transmission states can be monitored via the following
+            functions:
+              (++) HAL_FDCAN_IsRxBufferMessageAvailable
+              (++) HAL_FDCAN_IsTxBufferMessagePending
+              (++) HAL_FDCAN_GetRxFifoFillLevel
+              (++) HAL_FDCAN_GetTxFifoFreeLevel
+
+      *** Interrupt mode operation ***
+      ================================
+      [..]
+        (#) There are two interrupt lines: line 0 and 1.
+            By default, all interrupts are assigned to line 0. Interrupt lines
+            can be configured using HAL_FDCAN_ConfigInterruptLines function.
+
+        (#) Notifications are activated using HAL_FDCAN_ActivateNotification
+            function. Then, the process can be controlled through one of the
+            available user callbacks: HAL_FDCAN_xxxCallback.
+
+  *** Callback registration ***
+  =============================================
+
+  The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS when set to 1
+  allows the user to configure dynamically the driver callbacks.
+  Use Function @ref HAL_FDCAN_RegisterCallback() or HAL_FDCAN_RegisterXXXCallback()
+  to register an interrupt callback.
+
+  Function @ref HAL_FDCAN_RegisterCallback() allows to register following callbacks:
+    (+) TxFifoEmptyCallback          : Tx Fifo Empty Callback.
+    (+) RxBufferNewMessageCallback   : Rx Buffer New Message Callback.
+    (+) HighPriorityMessageCallback  : High Priority Message Callback.
+    (+) TimestampWraparoundCallback  : Timestamp Wraparound Callback.
+    (+) TimeoutOccurredCallback      : Timeout Occurred Callback.
+    (+) ErrorCallback                : Error Callback.
+    (+) MspInitCallback              : FDCAN MspInit.
+    (+) MspDeInitCallback            : FDCAN MspDeInit.
+  This function takes as parameters the HAL peripheral handle, the Callback ID
+  and a pointer to the user callback function.
+
+  For specific callbacks ClockCalibrationCallback, TxEventFifoCallback, RxFifo0Callback, RxFifo1Callback,
+  TxBufferCompleteCallback, TxBufferAbortCallback, ErrorStatusCallback, TT_ScheduleSyncCallback, TT_TimeMarkCallback,
+  TT_StopWatchCallback and TT_GlobalTimeCallback, use dedicated register callbacks :
+  respectively @ref HAL_FDCAN_RegisterClockCalibrationCallback(), @ref HAL_FDCAN_RegisterTxEventFifoCallback(),
+  @ref HAL_FDCAN_RegisterRxFifo0Callback(), @ref HAL_FDCAN_RegisterRxFifo1Callback(),
+  @ref HAL_FDCAN_RegisterTxBufferCompleCallback(), @ref HAL_FDCAN_RegisterTxBufferAbortCallback(),
+  @ref HAL_FDCAN_RegisterErrorStatusCallback(), @ref HAL_FDCAN_TT_RegisterScheduleSyncCallback(),
+  @ref HAL_FDCAN_TT_RegisterTimeMarkCallback(), @ref HAL_FDCAN_TT_RegisterStopWatchCallback() and
+  @ref HAL_FDCAN_TT_RegisterGlobalTimeCallback().
+
+  Use function @ref HAL_FDCAN_UnRegisterCallback() to reset a callback to the default
+  weak function.
+  @ref HAL_FDCAN_UnRegisterCallback takes as parameters the HAL peripheral handle,
+  and the Callback ID.
+  This function allows to reset following callbacks:
+    (+) TxFifoEmptyCallback          : Tx Fifo Empty Callback.
+    (+) RxBufferNewMessageCallback   : Rx Buffer New Message Callback.
+    (+) HighPriorityMessageCallback  : High Priority Message Callback.
+    (+) TimestampWraparoundCallback  : Timestamp Wraparound Callback.
+    (+) TimeoutOccurredCallback      : Timeout Occurred Callback.
+    (+) ErrorCallback                : Error Callback.
+    (+) MspInitCallback              : FDCAN MspInit.
+    (+) MspDeInitCallback            : FDCAN MspDeInit.
+
+  For specific callbacks ClockCalibrationCallback, TxEventFifoCallback, RxFifo0Callback,
+  RxFifo1Callback, TxBufferCompleteCallback, TxBufferAbortCallback, TT_ScheduleSyncCallback,
+  TT_TimeMarkCallback, TT_StopWatchCallback and TT_GlobalTimeCallback, use dedicated
+  register callbacks : respectively @ref HAL_FDCAN_UnRegisterClockCalibrationCallback(),
+  @ref HAL_FDCAN_UnRegisterTxEventFifoCallback(), @ref HAL_FDCAN_UnRegisterRxFifo0Callback(),
+  @ref HAL_FDCAN_UnRegisterRxFifo1Callback(), @ref HAL_FDCAN_UnRegisterTxBufferCompleCallback(),
+  @ref HAL_FDCAN_UnRegisterTxBufferAbortCallback(), @ref HAL_FDCAN_UnRegisterErrorStatusCallback(),
+  @ref HAL_FDCAN_TT_UnRegisterScheduleSyncCallback(), @ref HAL_FDCAN_TT_UnRegisterTimeMarkCallback(),
+  @ref HAL_FDCAN_TT_UnRegisterStopWatchCallback() and @ref HAL_FDCAN_TT_UnRegisterGlobalTimeCallback().
+
+  By default, after the @ref HAL_FDCAN_Init() and when the state is HAL_FDCAN_STATE_RESET,
+  all callbacks are set to the corresponding weak functions:
+  examples @ref HAL_FDCAN_ErrorCallback().
+  Exception done for MspInit and MspDeInit functions that are
+  reset to the legacy weak function in the @ref HAL_FDCAN_Init()/ @ref HAL_FDCAN_DeInit() only when
+  these callbacks are null (not registered beforehand).
+  if not, MspInit or MspDeInit are not null, the @ref HAL_FDCAN_Init()/ @ref HAL_FDCAN_DeInit()
+  keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+  Callbacks can be registered/unregistered in HAL_FDCAN_STATE_READY state only.
+  Exception done MspInit/MspDeInit that can be registered/unregistered
+  in HAL_FDCAN_STATE_READY or HAL_FDCAN_STATE_RESET state,
+  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+  In that case first register the MspInit/MspDeInit user callbacks
+  using @ref HAL_FDCAN_RegisterCallback() before calling @ref HAL_FDCAN_DeInit()
+  or @ref HAL_FDCAN_Init() function.
+
+  When The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS is set to 0 or
+  not defined, the callback registration feature is not available and all callbacks
+  are set to the corresponding weak functions.
+
+  @endverbatim
+
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup FDCAN FDCAN
+  * @brief FDCAN HAL module driver
+  * @{
+  */
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup FDCAN_Private_Constants
+  * @{
+  */
+#define FDCAN_TIMEOUT_VALUE 10U
+
+#define FDCAN_TX_EVENT_FIFO_MASK (FDCAN_IR_TEFL | FDCAN_IR_TEFF | FDCAN_IR_TEFW | FDCAN_IR_TEFN)
+#define FDCAN_RX_FIFO0_MASK (FDCAN_IR_RF0L | FDCAN_IR_RF0F | FDCAN_IR_RF0W | FDCAN_IR_RF0N)
+#define FDCAN_RX_FIFO1_MASK (FDCAN_IR_RF1L | FDCAN_IR_RF1F | FDCAN_IR_RF1W | FDCAN_IR_RF1N)
+#define FDCAN_ERROR_MASK (FDCAN_IR_ELO | FDCAN_IR_WDI | FDCAN_IR_PEA | FDCAN_IR_PED | FDCAN_IR_ARA)
+#define FDCAN_ERROR_STATUS_MASK (FDCAN_IR_EP | FDCAN_IR_EW | FDCAN_IR_BO)
+#define FDCAN_TT_SCHEDULE_SYNC_MASK (FDCAN_TTIR_SBC | FDCAN_TTIR_SMC | FDCAN_TTIR_CSM | FDCAN_TTIR_SOG)
+#define FDCAN_TT_TIME_MARK_MASK (FDCAN_TTIR_RTMI | FDCAN_TTIR_TTMI)
+#define FDCAN_TT_GLOBAL_TIME_MASK (FDCAN_TTIR_GTW | FDCAN_TTIR_GTD)
+#define FDCAN_TT_DISTURBING_ERROR_MASK (FDCAN_TTIR_GTE | FDCAN_TTIR_TXU | FDCAN_TTIR_TXO | \
+                                        FDCAN_TTIR_SE1 | FDCAN_TTIR_SE2 | FDCAN_TTIR_ELC)
+#define FDCAN_TT_FATAL_ERROR_MASK (FDCAN_TTIR_IWT | FDCAN_TTIR_WT | FDCAN_TTIR_AW | FDCAN_TTIR_CER)
+
+#define FDCAN_ELEMENT_MASK_STDID ((uint32_t)0x1FFC0000U) /* Standard Identifier         */
+#define FDCAN_ELEMENT_MASK_EXTID ((uint32_t)0x1FFFFFFFU) /* Extended Identifier         */
+#define FDCAN_ELEMENT_MASK_RTR   ((uint32_t)0x20000000U) /* Remote Transmission Request */
+#define FDCAN_ELEMENT_MASK_XTD   ((uint32_t)0x40000000U) /* Extended Identifier         */
+#define FDCAN_ELEMENT_MASK_ESI   ((uint32_t)0x80000000U) /* Error State Indicator       */
+#define FDCAN_ELEMENT_MASK_TS    ((uint32_t)0x0000FFFFU) /* Timestamp                   */
+#define FDCAN_ELEMENT_MASK_DLC   ((uint32_t)0x000F0000U) /* Data Length Code            */
+#define FDCAN_ELEMENT_MASK_BRS   ((uint32_t)0x00100000U) /* Bit Rate Switch             */
+#define FDCAN_ELEMENT_MASK_FDF   ((uint32_t)0x00200000U) /* FD Format                   */
+#define FDCAN_ELEMENT_MASK_EFC   ((uint32_t)0x00800000U) /* Event FIFO Control          */
+#define FDCAN_ELEMENT_MASK_MM    ((uint32_t)0xFF000000U) /* Message Marker              */
+#define FDCAN_ELEMENT_MASK_FIDX  ((uint32_t)0x7F000000U) /* Filter Index                */
+#define FDCAN_ELEMENT_MASK_ANMF  ((uint32_t)0x80000000U) /* Accepted Non-matching Frame */
+#define FDCAN_ELEMENT_MASK_ET    ((uint32_t)0x00C00000U) /* Event type                  */
+
+#define FDCAN_MESSAGE_RAM_SIZE 0x2800U
+#define FDCAN_MESSAGE_RAM_END_ADDRESS (SRAMCAN_BASE + FDCAN_MESSAGE_RAM_SIZE - 0x4U) /* The Message RAM has a width of 4 Bytes */
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+static const uint8_t DLCtoBytes[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64};
+
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup FDCAN_Private_Functions_Prototypes
+  * @{
+  */
+static HAL_StatusTypeDef FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan);
+static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup FDCAN_Exported_Functions FDCAN Exported Functions
+  * @{
+  */
+
+/** @defgroup FDCAN_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+  ==============================================================================
+              ##### Initialization and de-initialization functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize and configure the FDCAN.
+      (+) De-initialize the FDCAN.
+      (+) Enter FDCAN peripheral in power down mode.
+      (+) Exit power down mode.
+      (+) Register callbacks.
+      (+) Unregister callbacks.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the FDCAN peripheral according to the specified
+  *         parameters in the FDCAN_InitTypeDef structure.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t tickstart;
+  HAL_StatusTypeDef status;
+  const uint32_t CvtEltSize[] = {0, 0, 0, 0, 0, 1, 2, 3, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0, 7};
+
+  /* Check FDCAN handle */
+  if (hfdcan == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check FDCAN instance */
+  if (hfdcan->Instance == FDCAN1)
+  {
+    hfdcan->ttcan = (TTCAN_TypeDef *)((uint32_t)hfdcan->Instance + 0x100U);
+  }
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_FRAME_FORMAT(hfdcan->Init.FrameFormat));
+  assert_param(IS_FDCAN_MODE(hfdcan->Init.Mode));
+  assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.AutoRetransmission));
+  assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.TransmitPause));
+  assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.ProtocolException));
+  assert_param(IS_FDCAN_NOMINAL_PRESCALER(hfdcan->Init.NominalPrescaler));
+  assert_param(IS_FDCAN_NOMINAL_SJW(hfdcan->Init.NominalSyncJumpWidth));
+  assert_param(IS_FDCAN_NOMINAL_TSEG1(hfdcan->Init.NominalTimeSeg1));
+  assert_param(IS_FDCAN_NOMINAL_TSEG2(hfdcan->Init.NominalTimeSeg2));
+  if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS)
+  {
+    assert_param(IS_FDCAN_DATA_PRESCALER(hfdcan->Init.DataPrescaler));
+    assert_param(IS_FDCAN_DATA_SJW(hfdcan->Init.DataSyncJumpWidth));
+    assert_param(IS_FDCAN_DATA_TSEG1(hfdcan->Init.DataTimeSeg1));
+    assert_param(IS_FDCAN_DATA_TSEG2(hfdcan->Init.DataTimeSeg2));
+  }
+  assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.StdFiltersNbr, 128U));
+  assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.ExtFiltersNbr, 64U));
+  assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.RxFifo0ElmtsNbr, 64U));
+  if (hfdcan->Init.RxFifo0ElmtsNbr > 0U)
+  {
+    assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.RxFifo0ElmtSize));
+  }
+  assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.RxFifo1ElmtsNbr, 64U));
+  if (hfdcan->Init.RxFifo1ElmtsNbr > 0U)
+  {
+    assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.RxFifo1ElmtSize));
+  }
+  assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.RxBuffersNbr, 64U));
+  if (hfdcan->Init.RxBuffersNbr > 0U)
+  {
+    assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.RxBufferSize));
+  }
+  assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.TxEventsNbr, 32U));
+  assert_param(IS_FDCAN_MAX_VALUE((hfdcan->Init.TxBuffersNbr + hfdcan->Init.TxFifoQueueElmtsNbr), 32U));
+  if (hfdcan->Init.TxFifoQueueElmtsNbr > 0U)
+  {
+    assert_param(IS_FDCAN_TX_FIFO_QUEUE_MODE(hfdcan->Init.TxFifoQueueMode));
+  }
+  if ((hfdcan->Init.TxBuffersNbr + hfdcan->Init.TxFifoQueueElmtsNbr) > 0U)
+  {
+    assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.TxElmtSize));
+  }
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+  if (hfdcan->State == HAL_FDCAN_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hfdcan->Lock = HAL_UNLOCKED;
+
+    /* Reset callbacks to legacy functions */
+    hfdcan->ClockCalibrationCallback    = HAL_FDCAN_ClockCalibrationCallback;    /* Legacy weak ClockCalibrationCallback    */
+    hfdcan->TxEventFifoCallback         = HAL_FDCAN_TxEventFifoCallback;         /* Legacy weak TxEventFifoCallback         */
+    hfdcan->RxFifo0Callback             = HAL_FDCAN_RxFifo0Callback;             /* Legacy weak RxFifo0Callback             */
+    hfdcan->RxFifo1Callback             = HAL_FDCAN_RxFifo1Callback;             /* Legacy weak RxFifo1Callback             */
+    hfdcan->TxFifoEmptyCallback         = HAL_FDCAN_TxFifoEmptyCallback;         /* Legacy weak TxFifoEmptyCallback         */
+    hfdcan->TxBufferCompleteCallback    = HAL_FDCAN_TxBufferCompleteCallback;    /* Legacy weak TxBufferCompleteCallback    */
+    hfdcan->TxBufferAbortCallback       = HAL_FDCAN_TxBufferAbortCallback;       /* Legacy weak TxBufferAbortCallback       */
+    hfdcan->RxBufferNewMessageCallback  = HAL_FDCAN_RxBufferNewMessageCallback;  /* Legacy weak RxBufferNewMessageCallback  */
+    hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback; /* Legacy weak HighPriorityMessageCallback */
+    hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback; /* Legacy weak TimestampWraparoundCallback */
+    hfdcan->TimeoutOccurredCallback     = HAL_FDCAN_TimeoutOccurredCallback;     /* Legacy weak TimeoutOccurredCallback     */
+    hfdcan->ErrorCallback               = HAL_FDCAN_ErrorCallback;               /* Legacy weak ErrorCallback               */
+    hfdcan->ErrorStatusCallback         = HAL_FDCAN_ErrorStatusCallback;         /* Legacy weak ErrorStatusCallback         */
+    hfdcan->TT_ScheduleSyncCallback     = HAL_FDCAN_TT_ScheduleSyncCallback;     /* Legacy weak TT_ScheduleSyncCallback     */
+    hfdcan->TT_TimeMarkCallback         = HAL_FDCAN_TT_TimeMarkCallback;         /* Legacy weak TT_TimeMarkCallback         */
+    hfdcan->TT_StopWatchCallback        = HAL_FDCAN_TT_StopWatchCallback;        /* Legacy weak TT_StopWatchCallback        */
+    hfdcan->TT_GlobalTimeCallback       = HAL_FDCAN_TT_GlobalTimeCallback;       /* Legacy weak TT_GlobalTimeCallback       */
+
+    if (hfdcan->MspInitCallback == NULL)
+    {
+      hfdcan->MspInitCallback = HAL_FDCAN_MspInit;  /* Legacy weak MspInit */
+    }
+
+    /* Init the low level hardware: CLOCK, NVIC */
+    hfdcan->MspInitCallback(hfdcan);
+  }
+#else
+  if (hfdcan->State == HAL_FDCAN_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hfdcan->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware: CLOCK, NVIC */
+    HAL_FDCAN_MspInit(hfdcan);
+  }
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+  /* Exit from Sleep mode */
+  CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Check Sleep mode acknowledge */
+  while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
+  {
+    if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+      /* Change FDCAN state */
+      hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+      return HAL_ERROR;
+    }
+  }
+
+  /* Request initialisation */
+  SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait until the INIT bit into CCCR register is set */
+  while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U)
+  {
+    /* Check for the Timeout */
+    if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+      /* Change FDCAN state */
+      hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+      return HAL_ERROR;
+    }
+  }
+
+  /* Enable configuration change */
+  SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE);
+
+  /* Set the no automatic retransmission */
+  if (hfdcan->Init.AutoRetransmission == ENABLE)
+  {
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR);
+  }
+  else
+  {
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR);
+  }
+
+  /* Set the transmit pause feature */
+  if (hfdcan->Init.TransmitPause == ENABLE)
+  {
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP);
+  }
+  else
+  {
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP);
+  }
+
+  /* Set the Protocol Exception Handling */
+  if (hfdcan->Init.ProtocolException == ENABLE)
+  {
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD);
+  }
+  else
+  {
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD);
+  }
+
+  /* Set FDCAN Frame Format */
+  MODIFY_REG(hfdcan->Instance->CCCR, FDCAN_FRAME_FD_BRS, hfdcan->Init.FrameFormat);
+
+  /* Reset FDCAN Operation Mode */
+  CLEAR_BIT(hfdcan->Instance->CCCR, (FDCAN_CCCR_TEST | FDCAN_CCCR_MON | FDCAN_CCCR_ASM));
+  CLEAR_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK);
+
+  /* Set FDCAN Operating Mode:
+               | Normal | Restricted |    Bus     | Internal | External
+               |        | Operation  | Monitoring | LoopBack | LoopBack
+     CCCR.TEST |   0    |     0      |     0      |    1     |    1
+     CCCR.MON  |   0    |     0      |     1      |    1     |    0
+     TEST.LBCK |   0    |     0      |     0      |    1     |    1
+     CCCR.ASM  |   0    |     1      |     0      |    0     |    0
+  */
+  if (hfdcan->Init.Mode == FDCAN_MODE_RESTRICTED_OPERATION)
+  {
+    /* Enable Restricted Operation mode */
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM);
+  }
+  else if (hfdcan->Init.Mode != FDCAN_MODE_NORMAL)
+  {
+    if (hfdcan->Init.Mode != FDCAN_MODE_BUS_MONITORING)
+    {
+      /* Enable write access to TEST register */
+      SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TEST);
+
+      /* Enable LoopBack mode */
+      SET_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK);
+
+      if (hfdcan->Init.Mode == FDCAN_MODE_INTERNAL_LOOPBACK)
+      {
+        SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON);
+      }
+    }
+    else
+    {
+      /* Enable bus monitoring mode */
+      SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON);
+    }
+  }
+  else
+  {
+    /* Nothing to do: normal mode */
+  }
+
+  /* Set the nominal bit timing register */
+  hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U) << FDCAN_NBTP_NSJW_Pos) | \
+                            (((uint32_t)hfdcan->Init.NominalTimeSeg1 - 1U) << FDCAN_NBTP_NTSEG1_Pos)    | \
+                            (((uint32_t)hfdcan->Init.NominalTimeSeg2 - 1U) << FDCAN_NBTP_NTSEG2_Pos)    | \
+                            (((uint32_t)hfdcan->Init.NominalPrescaler - 1U) << FDCAN_NBTP_NBRP_Pos));
+
+  /* If FD operation with BRS is selected, set the data bit timing register */
+  if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS)
+  {
+    hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos) | \
+                              (((uint32_t)hfdcan->Init.DataTimeSeg1 - 1U) << FDCAN_DBTP_DTSEG1_Pos)    | \
+                              (((uint32_t)hfdcan->Init.DataTimeSeg2 - 1U) << FDCAN_DBTP_DTSEG2_Pos)    | \
+                              (((uint32_t)hfdcan->Init.DataPrescaler - 1U) << FDCAN_DBTP_DBRP_Pos));
+  }
+
+  if (hfdcan->Init.TxFifoQueueElmtsNbr > 0U)
+  {
+    /* Select between Tx FIFO and Tx Queue operation modes */
+    SET_BIT(hfdcan->Instance->TXBC, hfdcan->Init.TxFifoQueueMode);
+  }
+
+  /* Configure Tx element size */
+  if ((hfdcan->Init.TxBuffersNbr + hfdcan->Init.TxFifoQueueElmtsNbr) > 0U)
+  {
+    MODIFY_REG(hfdcan->Instance->TXESC, FDCAN_TXESC_TBDS, CvtEltSize[hfdcan->Init.TxElmtSize]);
+  }
+
+  /* Configure Rx FIFO 0 element size */
+  if (hfdcan->Init.RxFifo0ElmtsNbr > 0U)
+  {
+    MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_F0DS, (CvtEltSize[hfdcan->Init.RxFifo0ElmtSize] << FDCAN_RXESC_F0DS_Pos));
+  }
+
+  /* Configure Rx FIFO 1 element size */
+  if (hfdcan->Init.RxFifo1ElmtsNbr > 0U)
+  {
+    MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_F1DS, (CvtEltSize[hfdcan->Init.RxFifo1ElmtSize] << FDCAN_RXESC_F1DS_Pos));
+  }
+
+  /* Configure Rx buffer element size */
+  if (hfdcan->Init.RxBuffersNbr > 0U)
+  {
+    MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_RBDS, (CvtEltSize[hfdcan->Init.RxBufferSize] << FDCAN_RXESC_RBDS_Pos));
+  }
+
+  /* By default operation mode is set to Event-driven communication.
+     If Time-triggered communication is needed, user should call the
+     HAL_FDCAN_TT_ConfigOperation function just after the HAL_FDCAN_Init */
+  if (hfdcan->Instance == FDCAN1)
+  {
+    CLEAR_BIT(hfdcan->ttcan->TTOCF, FDCAN_TTOCF_OM);
+  }
+
+  /* Initialize the Latest Tx FIFO/Queue request buffer index */
+  hfdcan->LatestTxFifoQRequest = 0U;
+
+  /* Initialize the error code */
+  hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
+
+  /* Initialize the FDCAN state */
+  hfdcan->State = HAL_FDCAN_STATE_READY;
+
+  /* Calculate each RAM block address */
+  status = FDCAN_CalcultateRamBlockAddresses(hfdcan);
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Deinitializes the FDCAN peripheral registers to their default reset values.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Check FDCAN handle */
+  if (hfdcan == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance));
+
+  /* Stop the FDCAN module: return value is voluntary ignored */
+  (void)HAL_FDCAN_Stop(hfdcan);
+
+  /* Disable Interrupt lines */
+  CLEAR_BIT(hfdcan->Instance->ILE, (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1));
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+  if (hfdcan->MspDeInitCallback == NULL)
+  {
+    hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit; /* Legacy weak MspDeInit */
+  }
+
+  /* DeInit the low level hardware: CLOCK, NVIC */
+  hfdcan->MspDeInitCallback(hfdcan);
+#else
+  /* DeInit the low level hardware: CLOCK, NVIC */
+  HAL_FDCAN_MspDeInit(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+  /* Reset the FDCAN ErrorCode */
+  hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
+
+  /* Change FDCAN state */
+  hfdcan->State = HAL_FDCAN_STATE_RESET;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the FDCAN MSP.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes the FDCAN MSP.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Enter FDCAN peripheral in sleep mode.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t tickstart;
+
+  /* Request clock stop */
+  SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait until FDCAN is ready for power down */
+  while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+      /* Change FDCAN state */
+      hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+      return HAL_ERROR;
+    }
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Exit power down mode.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t tickstart;
+
+  /* Reset clock stop request */
+  CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait until FDCAN exits sleep mode */
+  while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
+  {
+    if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+      /* Change FDCAN state */
+      hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+      return HAL_ERROR;
+    }
+  }
+
+  /* Enter normal operation */
+  CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+/**
+  * @brief  Register a FDCAN CallBack.
+  *         To be used instead of the weak predefined callback
+  * @param  hfdcan pointer to a FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for FDCAN module
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_FDCAN_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty callback ID
+  *           @arg @ref HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID Rx buffer new message callback ID
+  *           @arg @ref HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID High priority message callback ID
+  *           @arg @ref HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID Timestamp wraparound callback ID
+  *           @arg @ref HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID Timeout occurred callback ID
+  *           @arg @ref HAL_FDCAN_ERROR_CALLBACK_CB_ID Error callback ID
+  *           @arg @ref HAL_FDCAN_MSPINIT_CB_ID MspInit callback ID
+  *           @arg @ref HAL_FDCAN_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, void (* pCallback)(FDCAN_HandleTypeDef *_hFDCAN))
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_FDCAN_TX_FIFO_EMPTY_CB_ID :
+        hfdcan->TxFifoEmptyCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID :
+        hfdcan->RxBufferNewMessageCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID :
+        hfdcan->HighPriorityMessageCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID :
+        hfdcan->TimestampWraparoundCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID :
+        hfdcan->TimeoutOccurredCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_ERROR_CALLBACK_CB_ID :
+        hfdcan->ErrorCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_MSPINIT_CB_ID :
+        hfdcan->MspInitCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_MSPDEINIT_CB_ID :
+        hfdcan->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hfdcan->State == HAL_FDCAN_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_FDCAN_MSPINIT_CB_ID :
+        hfdcan->MspInitCallback = pCallback;
+        break;
+
+      case HAL_FDCAN_MSPDEINIT_CB_ID :
+        hfdcan->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a FDCAN CallBack.
+  *         FDCAN callback is redirected to the weak predefined callback
+  * @param  hfdcan pointer to a FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for FDCAN module
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_FDCAN_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty callback ID
+  *           @arg @ref HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID Rx buffer new message callback ID
+  *           @arg @ref HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID High priority message callback ID
+  *           @arg @ref HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID Timestamp wraparound callback ID
+  *           @arg @ref HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID Timeout occurred callback ID
+  *           @arg @ref HAL_FDCAN_ERROR_CALLBACK_CB_ID Error callback ID
+  *           @arg @ref HAL_FDCAN_MSPINIT_CB_ID MspInit callback ID
+  *           @arg @ref HAL_FDCAN_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_FDCAN_TX_FIFO_EMPTY_CB_ID :
+        hfdcan->TxFifoEmptyCallback = HAL_FDCAN_TxFifoEmptyCallback;
+        break;
+
+      case HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID :
+        hfdcan->RxBufferNewMessageCallback = HAL_FDCAN_RxBufferNewMessageCallback;
+        break;
+
+      case HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID :
+        hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback;
+        break;
+
+      case HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID :
+        hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback;
+        break;
+
+      case HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID :
+        hfdcan->TimeoutOccurredCallback = HAL_FDCAN_TimeoutOccurredCallback;
+        break;
+
+      case HAL_FDCAN_ERROR_CALLBACK_CB_ID :
+        hfdcan->ErrorCallback = HAL_FDCAN_ErrorCallback;
+        break;
+
+      case HAL_FDCAN_MSPINIT_CB_ID :
+        hfdcan->MspInitCallback = HAL_FDCAN_MspInit;
+        break;
+
+      case HAL_FDCAN_MSPDEINIT_CB_ID :
+        hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hfdcan->State == HAL_FDCAN_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_FDCAN_MSPINIT_CB_ID :
+        hfdcan->MspInitCallback = HAL_FDCAN_MspInit;
+        break;
+
+      case HAL_FDCAN_MSPDEINIT_CB_ID :
+        hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register Clock Calibration FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_ClockCalibrationCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the Clock Calibration Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ClockCalibrationCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->ClockCalibrationCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Clock Calibration FDCAN Callback
+  *         Clock Calibration FDCAN Callback is redirected to the weak HAL_FDCAN_ClockCalibrationCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->ClockCalibrationCallback = HAL_FDCAN_ClockCalibrationCallback; /* Legacy weak ClockCalibrationCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register Tx Event Fifo FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_TxEventFifoCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the Tx Event Fifo Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxEventFifoCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TxEventFifoCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Tx Event Fifo FDCAN Callback
+  *         Tx Event Fifo FDCAN Callback is redirected to the weak HAL_FDCAN_TxEventFifoCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TxEventFifoCallback = HAL_FDCAN_TxEventFifoCallback; /* Legacy weak TxEventFifoCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register Rx Fifo 0 FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_RxFifo0Callback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the Rx Fifo 0 Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo0CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->RxFifo0Callback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Rx Fifo 0 FDCAN Callback
+  *         Rx Fifo 0 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo0Callback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->RxFifo0Callback = HAL_FDCAN_RxFifo0Callback; /* Legacy weak RxFifo0Callback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register Rx Fifo 1 FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_RxFifo1Callback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the Rx Fifo 1 Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo1CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->RxFifo1Callback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Rx Fifo 1 FDCAN Callback
+  *         Rx Fifo 1 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo1Callback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->RxFifo1Callback = HAL_FDCAN_RxFifo1Callback; /* Legacy weak RxFifo1Callback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register Tx Buffer Complete FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the Tx Buffer Complete Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferCompleteCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TxBufferCompleteCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Tx Buffer Complete FDCAN Callback
+  *         Tx Buffer Complete FDCAN Callback is redirected to the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TxBufferCompleteCallback = HAL_FDCAN_TxBufferCompleteCallback; /* Legacy weak TxBufferCompleteCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register Tx Buffer Abort FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the Tx Buffer Abort Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferAbortCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TxBufferAbortCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Tx Buffer Abort FDCAN Callback
+  *         Tx Buffer Abort FDCAN Callback is redirected to the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TxBufferAbortCallback = HAL_FDCAN_TxBufferAbortCallback; /* Legacy weak TxBufferAbortCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register Error Status FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_ErrorStatusCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the Error Status Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ErrorStatusCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->ErrorStatusCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Error Status FDCAN Callback
+  *         Error Status FDCAN Callback is redirected to the weak HAL_FDCAN_ErrorStatusCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->ErrorStatusCallback = HAL_FDCAN_ErrorStatusCallback; /* Legacy weak ErrorStatusCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register TT Schedule Synchronization FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_TT_ScheduleSyncCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the TT Schedule Synchronization Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_ScheduleSyncCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_ScheduleSyncCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the TT Schedule Synchronization FDCAN Callback
+  *         TT Schedule Synchronization Callback is redirected to the weak HAL_FDCAN_TT_ScheduleSyncCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_ScheduleSyncCallback = HAL_FDCAN_TT_ScheduleSyncCallback; /* Legacy weak TT_ScheduleSyncCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register TT Time Mark FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_TT_TimeMarkCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the TT Time Mark Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_TimeMarkCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_TimeMarkCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the TT Time Mark FDCAN Callback
+  *         TT Time Mark Callback is redirected to the weak HAL_FDCAN_TT_TimeMarkCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_TimeMarkCallback = HAL_FDCAN_TT_TimeMarkCallback; /* Legacy weak TT_TimeMarkCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register TT Stop Watch FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_TT_StopWatchCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the TT Stop Watch Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_StopWatchCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_StopWatchCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the TT Stop Watch FDCAN Callback
+  *         TT Stop Watch Callback is redirected to the weak HAL_FDCAN_TT_StopWatchCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_StopWatchCallback = HAL_FDCAN_TT_StopWatchCallback; /* Legacy weak TT_StopWatchCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register TT Global Time FDCAN Callback
+  *         To be used instead of the weak HAL_FDCAN_TT_GlobalTimeCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @param  pCallback pointer to the TT Global Time Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_GlobalTimeCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_GlobalTimeCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the TT Global Time FDCAN Callback
+  *         TT Global Time Callback is redirected to the weak HAL_FDCAN_TT_GlobalTimeCallback() predefined callback
+  * @param  hfdcan FDCAN handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    hfdcan->TT_GlobalTimeCallback = HAL_FDCAN_TT_GlobalTimeCallback; /* Legacy weak TT_GlobalTimeCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Exported_Functions_Group2 Configuration functions
+ *  @brief    FDCAN Configuration functions.
+ *
+@verbatim
+  ==============================================================================
+              ##### Configuration functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) HAL_FDCAN_ConfigClockCalibration        : Configure the FDCAN clock calibration unit
+        (+) HAL_FDCAN_GetClockCalibrationState      : Get the clock calibration state
+        (+) HAL_FDCAN_ResetClockCalibrationState    : Reset the clock calibration state
+        (+) HAL_FDCAN_GetClockCalibrationCounter    : Get the clock calibration counters values
+      (+) HAL_FDCAN_ConfigFilter                  : Configure the FDCAN reception filters
+      (+) HAL_FDCAN_ConfigGlobalFilter            : Configure the FDCAN global filter
+      (+) HAL_FDCAN_ConfigExtendedIdMask          : Configure the extended ID mask
+      (+) HAL_FDCAN_ConfigRxFifoOverwrite         : Configure the Rx FIFO operation mode
+      (+) HAL_FDCAN_ConfigFifoWatermark           : Configure the FIFO watermark
+      (+) HAL_FDCAN_ConfigRamWatchdog             : Configure the RAM watchdog
+      (+) HAL_FDCAN_ConfigTimestampCounter        : Configure the timestamp counter
+        (+) HAL_FDCAN_EnableTimestampCounter        : Enable the timestamp counter
+        (+) HAL_FDCAN_DisableTimestampCounter       : Disable the timestamp counter
+        (+) HAL_FDCAN_GetTimestampCounter           : Get the timestamp counter value
+        (+) HAL_FDCAN_ResetTimestampCounter         : Reset the timestamp counter to zero
+      (+) HAL_FDCAN_ConfigTimeoutCounter          : Configure the timeout counter
+        (+) HAL_FDCAN_EnableTimeoutCounter          : Enable the timeout counter
+        (+) HAL_FDCAN_DisableTimeoutCounter         : Disable the timeout counter
+        (+) HAL_FDCAN_GetTimeoutCounter             : Get the timeout counter value
+        (+) HAL_FDCAN_ResetTimeoutCounter           : Reset the timeout counter to its start value
+      (+) HAL_FDCAN_ConfigTxDelayCompensation     : Configure the transmitter delay compensation
+        (+) HAL_FDCAN_EnableTxDelayCompensation     : Enable the transmitter delay compensation
+        (+) HAL_FDCAN_DisableTxDelayCompensation    : Disable the transmitter delay compensation
+      (+) HAL_FDCAN_EnableISOMode                 : Enable ISO 11898-1 protocol mode
+      (+) HAL_FDCAN_DisableISOMode                : Disable ISO 11898-1 protocol mode
+      (+) HAL_FDCAN_EnableEdgeFiltering           : Enable edge filtering during bus integration
+      (+) HAL_FDCAN_DisableEdgeFiltering          : Disable edge filtering during bus integration
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the FDCAN clock calibration unit according to the specified
+  *         parameters in the FDCAN_ClkCalUnitTypeDef structure.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  sCcuConfig pointer to an FDCAN_ClkCalUnitTypeDef structure that
+  *         contains the clock calibration information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigClockCalibration(FDCAN_HandleTypeDef *hfdcan, FDCAN_ClkCalUnitTypeDef *sCcuConfig)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_CLOCK_CALIBRATION(sCcuConfig->ClockCalibration));
+  if (sCcuConfig->ClockCalibration == FDCAN_CLOCK_CALIBRATION_DISABLE)
+  {
+    assert_param(IS_FDCAN_CKDIV(sCcuConfig->ClockDivider));
+  }
+  else
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(sCcuConfig->MinOscClkPeriods, 0xFFU));
+    assert_param(IS_FDCAN_CALIBRATION_FIELD_LENGTH(sCcuConfig->CalFieldLength));
+    assert_param(IS_FDCAN_MIN_VALUE(sCcuConfig->TimeQuantaPerBitTime, 4U));
+    assert_param(IS_FDCAN_MAX_VALUE(sCcuConfig->TimeQuantaPerBitTime, 0x25U));
+    assert_param(IS_FDCAN_MAX_VALUE(sCcuConfig->WatchdogStartValue, 0xFFFFU));
+  }
+
+  /* FDCAN1 should be initialized in order to use clock calibration */
+  if (hfdcan->Instance != FDCAN1)
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    if (sCcuConfig->ClockCalibration == FDCAN_CLOCK_CALIBRATION_DISABLE)
+    {
+      /* Bypass clock calibration */
+      SET_BIT(FDCAN_CCU->CCFG, FDCANCCU_CCFG_BCC);
+
+      /* Configure clock divider */
+      MODIFY_REG(FDCAN_CCU->CCFG, FDCANCCU_CCFG_CDIV, sCcuConfig->ClockDivider);
+    }
+    else /* sCcuConfig->ClockCalibration == ENABLE */
+    {
+      /* Clock calibration unit generates time quanta clock */
+      CLEAR_BIT(FDCAN_CCU->CCFG, FDCANCCU_CCFG_BCC);
+
+      /* Configure clock calibration unit */
+      MODIFY_REG(FDCAN_CCU->CCFG,
+                 (FDCANCCU_CCFG_TQBT | FDCANCCU_CCFG_CFL | FDCANCCU_CCFG_OCPM),
+                 ((sCcuConfig->TimeQuantaPerBitTime << FDCANCCU_CCFG_TQBT_Pos) | sCcuConfig->CalFieldLength | (sCcuConfig->MinOscClkPeriods << FDCANCCU_CCFG_OCPM_Pos)));
+
+      /* Configure the start value of the calibration watchdog counter */
+      MODIFY_REG(FDCAN_CCU->CWD, FDCANCCU_CWD_WDC, sCcuConfig->WatchdogStartValue);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get the clock calibration state.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval State clock calibration state (can be a value of @arg FDCAN_calibration_state)
+  */
+uint32_t HAL_FDCAN_GetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  return (FDCAN_CCU->CSTAT & FDCANCCU_CSTAT_CALS);
+}
+
+/**
+  * @brief  Reset the clock calibration state.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ResetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* FDCAN1 should be initialized in order to use clock calibration */
+  if (hfdcan->Instance != FDCAN1)
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+    return HAL_ERROR;
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Calibration software reset */
+    SET_BIT(FDCAN_CCU->CCFG, FDCANCCU_CCFG_SWR);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get the clock calibration counter value.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  Counter clock calibration counter.
+  *         This parameter can be a value of @arg FDCAN_calibration_counter.
+  * @retval Value clock calibration counter value
+  */
+uint32_t HAL_FDCAN_GetClockCalibrationCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t Counter)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_CALIBRATION_COUNTER(Counter));
+
+  if (Counter == FDCAN_CALIB_TIME_QUANTA_COUNTER)
+  {
+    return ((FDCAN_CCU->CSTAT & FDCANCCU_CSTAT_TQC) >> FDCANCCU_CSTAT_TQC_Pos);
+  }
+  else if (Counter == FDCAN_CALIB_CLOCK_PERIOD_COUNTER)
+  {
+    return (FDCAN_CCU->CSTAT & FDCANCCU_CSTAT_OCPC);
+  }
+  else /* Counter == FDCAN_CALIB_WATCHDOG_COUNTER */
+  {
+    return ((FDCAN_CCU->CWD & FDCANCCU_CWD_WDV) >> FDCANCCU_CWD_WDV_Pos);
+  }
+}
+
+/**
+  * @brief  Configure the FDCAN reception filter according to the specified
+  *         parameters in the FDCAN_FilterTypeDef structure.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  sFilterConfig pointer to an FDCAN_FilterTypeDef structure that
+  *         contains the filter configuration information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig)
+{
+  uint32_t FilterElementW1;
+  uint32_t FilterElementW2;
+  uint32_t *FilterAddress;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Check function parameters */
+    assert_param(IS_FDCAN_ID_TYPE(sFilterConfig->IdType));
+    assert_param(IS_FDCAN_FILTER_CFG(sFilterConfig->FilterConfig));
+    if (sFilterConfig->FilterConfig == FDCAN_FILTER_TO_RXBUFFER)
+    {
+      assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->RxBufferIndex, 63U));
+      assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->IsCalibrationMsg, 1U));
+    }
+
+    if (sFilterConfig->IdType == FDCAN_STANDARD_ID)
+    {
+      /* Check function parameters */
+      assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.StdFiltersNbr - 1U)));
+      assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x7FFU));
+      if (sFilterConfig->FilterConfig != FDCAN_FILTER_TO_RXBUFFER)
+      {
+        assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x7FFU));
+        assert_param(IS_FDCAN_STD_FILTER_TYPE(sFilterConfig->FilterType));
+      }
+
+      /* Build filter element */
+      if (sFilterConfig->FilterConfig == FDCAN_FILTER_TO_RXBUFFER)
+      {
+        FilterElementW1 = ((FDCAN_FILTER_TO_RXBUFFER << 27U)       |
+                           (sFilterConfig->FilterID1 << 16U)       |
+                           (sFilterConfig->IsCalibrationMsg << 8U) |
+                           sFilterConfig->RxBufferIndex);
+      }
+      else
+      {
+        FilterElementW1 = ((sFilterConfig->FilterType << 30U)   |
+                           (sFilterConfig->FilterConfig << 27U) |
+                           (sFilterConfig->FilterID1 << 16U)    |
+                           sFilterConfig->FilterID2);
+      }
+
+      /* Calculate filter address */
+      FilterAddress = (uint32_t *)(hfdcan->msgRam.StandardFilterSA + (sFilterConfig->FilterIndex * 4U));
+
+      /* Write filter element to the message RAM */
+      *FilterAddress = FilterElementW1;
+    }
+    else /* sFilterConfig->IdType == FDCAN_EXTENDED_ID */
+    {
+      /* Check function parameters */
+      assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.ExtFiltersNbr - 1U)));
+      assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x1FFFFFFFU));
+      if (sFilterConfig->FilterConfig != FDCAN_FILTER_TO_RXBUFFER)
+      {
+        assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x1FFFFFFFU));
+        assert_param(IS_FDCAN_EXT_FILTER_TYPE(sFilterConfig->FilterType));
+      }
+
+      /* Build first word of filter element */
+      FilterElementW1 = ((sFilterConfig->FilterConfig << 29U) | sFilterConfig->FilterID1);
+
+      /* Build second word of filter element */
+      if (sFilterConfig->FilterConfig == FDCAN_FILTER_TO_RXBUFFER)
+      {
+        FilterElementW2 = sFilterConfig->RxBufferIndex;
+      }
+      else
+      {
+        FilterElementW2 = ((sFilterConfig->FilterType << 30U) | sFilterConfig->FilterID2);
+      }
+
+      /* Calculate filter address */
+      FilterAddress = (uint32_t *)(hfdcan->msgRam.ExtendedFilterSA + (sFilterConfig->FilterIndex * 4U * 2U));
+
+      /* Write filter element to the message RAM */
+      *FilterAddress = FilterElementW1;
+      FilterAddress++;
+      *FilterAddress = FilterElementW2;
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the FDCAN global filter.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  NonMatchingStd Defines how received messages with 11-bit IDs that
+  *         do not match any element of the filter list are treated.
+  *         This parameter can be a value of @arg FDCAN_Non_Matching_Frames.
+  * @param  NonMatchingExt Defines how received messages with 29-bit IDs that
+  *         do not match any element of the filter list are treated.
+  *         This parameter can be a value of @arg FDCAN_Non_Matching_Frames.
+  * @param  RejectRemoteStd Filter or reject all the remote 11-bit IDs frames.
+  *         This parameter can be a value of @arg FDCAN_Reject_Remote_Frames.
+  * @param  RejectRemoteExt Filter or reject all the remote 29-bit IDs frames.
+  *         This parameter can be a value of @arg FDCAN_Reject_Remote_Frames.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan,
+                                               uint32_t NonMatchingStd,
+                                               uint32_t NonMatchingExt,
+                                               uint32_t RejectRemoteStd,
+                                               uint32_t RejectRemoteExt)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_NON_MATCHING(NonMatchingStd));
+  assert_param(IS_FDCAN_NON_MATCHING(NonMatchingExt));
+  assert_param(IS_FDCAN_REJECT_REMOTE(RejectRemoteStd));
+  assert_param(IS_FDCAN_REJECT_REMOTE(RejectRemoteExt));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Configure global filter */
+    hfdcan->Instance->GFC = ((NonMatchingStd << FDCAN_GFC_ANFS_Pos)  |
+                             (NonMatchingExt << FDCAN_GFC_ANFE_Pos)  |
+                             (RejectRemoteStd << FDCAN_GFC_RRFS_Pos) |
+                             (RejectRemoteExt << FDCAN_GFC_RRFE_Pos));
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the extended ID mask.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  Mask Extended ID Mask.
+  *         This parameter must be a number between 0 and 0x1FFFFFFF
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_MAX_VALUE(Mask, 0x1FFFFFFFU));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Configure the extended ID mask */
+    hfdcan->Instance->XIDAM = Mask;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the Rx FIFO operation mode.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  RxFifo Rx FIFO.
+  *         This parameter can be one of the following values:
+  *           @arg FDCAN_RX_FIFO0: Rx FIFO 0
+  *           @arg FDCAN_RX_FIFO1: Rx FIFO 1
+  * @param  OperationMode operation mode.
+  *         This parameter can be a value of @arg FDCAN_Rx_FIFO_operation_mode.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_RX_FIFO(RxFifo));
+  assert_param(IS_FDCAN_RX_FIFO_MODE(OperationMode));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    if (RxFifo == FDCAN_RX_FIFO0)
+    {
+      /* Select FIFO 0 Operation Mode */
+      MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0OM, OperationMode);
+    }
+    else /* RxFifo == FDCAN_RX_FIFO1 */
+    {
+      /* Select FIFO 1 Operation Mode */
+      MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1OM, OperationMode);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the FIFO watermark.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  FIFO select the FIFO to be configured.
+  *         This parameter can be a value of @arg FDCAN_FIFO_watermark.
+  * @param  Watermark level for FIFO watermark interrupt.
+  *         This parameter must be a number between:
+  *           - 0 and 32, if FIFO is FDCAN_CFG_TX_EVENT_FIFO
+  *           - 0 and 64, if FIFO is FDCAN_CFG_RX_FIFO0 or FDCAN_CFG_RX_FIFO1
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigFifoWatermark(FDCAN_HandleTypeDef *hfdcan, uint32_t FIFO, uint32_t Watermark)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_FIFO_WATERMARK(FIFO));
+  if (FIFO == FDCAN_CFG_TX_EVENT_FIFO)
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(Watermark, 32U));
+  }
+  else /* (FIFO == FDCAN_CFG_RX_FIFO0) || (FIFO == FDCAN_CFG_RX_FIFO1) */
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(Watermark, 64U));
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Set the level for FIFO watermark interrupt */
+    if (FIFO == FDCAN_CFG_TX_EVENT_FIFO)
+    {
+      MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFWM, (Watermark << FDCAN_TXEFC_EFWM_Pos));
+    }
+    else if (FIFO == FDCAN_CFG_RX_FIFO0)
+    {
+      MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0WM, (Watermark << FDCAN_RXF0C_F0WM_Pos));
+    }
+    else /* FIFO == FDCAN_CFG_RX_FIFO1 */
+    {
+      MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1WM, (Watermark << FDCAN_RXF1C_F1WM_Pos));
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the RAM watchdog.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  CounterStartValue Start value of the Message RAM Watchdog Counter,
+  *         This parameter must be a number between 0x00 and 0xFF,
+  *         with the reset value of 0x00 the counter is disabled.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_MAX_VALUE(CounterStartValue, 0xFFU));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Configure the RAM watchdog counter start value */
+    MODIFY_REG(hfdcan->Instance->RWD, FDCAN_RWD_WDC, CounterStartValue);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the timestamp counter.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TimestampPrescaler Timestamp Counter Prescaler.
+  *         This parameter can be a value of @arg FDCAN_Timestamp_Prescaler.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TIMESTAMP_PRESCALER(TimestampPrescaler));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Configure prescaler */
+    MODIFY_REG(hfdcan->Instance->TSCC, FDCAN_TSCC_TCP, TimestampPrescaler);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable the timestamp counter.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TimestampOperation Timestamp counter operation.
+  *         This parameter can be a value of @arg FDCAN_Timestamp.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TIMESTAMP(TimestampOperation));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Enable timestamp counter */
+    MODIFY_REG(hfdcan->Instance->TSCC, FDCAN_TSCC_TSS, TimestampOperation);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable the timestamp counter.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Disable timestamp counter */
+    CLEAR_BIT(hfdcan->Instance->TSCC, FDCAN_TSCC_TSS);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get the timestamp counter value.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval Value Timestamp counter value
+  */
+uint16_t HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+  return (uint16_t)(hfdcan->Instance->TSCV);
+}
+
+/**
+  * @brief  Reset the timestamp counter to zero.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+  if ((hfdcan->Instance->TSCC & FDCAN_TSCC_TSS) != FDCAN_TIMESTAMP_EXTERNAL)
+  {
+    /* Reset timestamp counter.
+       Actually any write operation to TSCV clears the counter */
+    CLEAR_REG(hfdcan->Instance->TSCV);
+  }
+  else
+  {
+    /* Update error code.
+       Unable to reset external counter */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+    return HAL_ERROR;
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the timeout counter.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TimeoutOperation Timeout counter operation.
+  *         This parameter can be a value of @arg FDCAN_Timeout_Operation.
+  * @param  TimeoutPeriod Start value of the timeout down-counter.
+  *         This parameter must be a number between 0x0000 and 0xFFFF
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TIMEOUT(TimeoutOperation));
+  assert_param(IS_FDCAN_MAX_VALUE(TimeoutPeriod, 0xFFFFU));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Select timeout operation and configure period */
+    MODIFY_REG(hfdcan->Instance->TOCC, (FDCAN_TOCC_TOS | FDCAN_TOCC_TOP), (TimeoutOperation | (TimeoutPeriod << FDCAN_TOCC_TOP_Pos)));
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable the timeout counter.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Enable timeout counter */
+    SET_BIT(hfdcan->Instance->TOCC, FDCAN_TOCC_ETOC);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable the timeout counter.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Disable timeout counter */
+    CLEAR_BIT(hfdcan->Instance->TOCC, FDCAN_TOCC_ETOC);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get the timeout counter value.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval Value Timeout counter value
+  */
+uint16_t HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+  return (uint16_t)(hfdcan->Instance->TOCV);
+}
+
+/**
+  * @brief  Reset the timeout counter to its start value.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+  if ((hfdcan->Instance->TOCC & FDCAN_TOCC_TOS) == FDCAN_TIMEOUT_CONTINUOUS)
+  {
+    /* Reset timeout counter to start value */
+    CLEAR_REG(hfdcan->Instance->TOCV);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code.
+       Unable to reset counter: controlled only by FIFO empty state */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the transmitter delay compensation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TdcOffset Transmitter Delay Compensation Offset.
+  *         This parameter must be a number between 0x00 and 0x7F.
+  * @param  TdcFilter Transmitter Delay Compensation Filter Window Length.
+  *         This parameter must be a number between 0x00 and 0x7F.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_MAX_VALUE(TdcOffset, 0x7FU));
+  assert_param(IS_FDCAN_MAX_VALUE(TdcFilter, 0x7FU));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Configure TDC offset and filter window */
+    hfdcan->Instance->TDCR = ((TdcFilter << FDCAN_TDCR_TDCF_Pos) | (TdcOffset << FDCAN_TDCR_TDCO_Pos));
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable the transmitter delay compensation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Enable transmitter delay compensation */
+    SET_BIT(hfdcan->Instance->DBTP, FDCAN_DBTP_TDC);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable the transmitter delay compensation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Disable transmitter delay compensation */
+    CLEAR_BIT(hfdcan->Instance->DBTP, FDCAN_DBTP_TDC);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable ISO 11898-1 protocol mode.
+  *         CAN FD frame format is according to ISO 11898-1 standard.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Disable Non ISO protocol mode */
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_NISO);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable ISO 11898-1 protocol mode.
+  *         CAN FD frame format is according to Bosch CAN FD specification V1.0.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Enable Non ISO protocol mode */
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_NISO);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable edge filtering during bus integration.
+  *         Two consecutive dominant tq are required to detect an edge for hard synchronization.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Enable edge filtering */
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_EFBI);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable edge filtering during bus integration.
+  *         One dominant tq is required to detect an edge for hard synchronization.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Disable edge filtering */
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_EFBI);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Exported_Functions_Group3 Control functions
+ *  @brief    Control functions
+ *
+@verbatim
+  ==============================================================================
+                          ##### Control functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) HAL_FDCAN_Start                         : Start the FDCAN module
+      (+) HAL_FDCAN_Stop                          : Stop the FDCAN module and enable access to configuration registers
+      (+) HAL_FDCAN_AddMessageToTxFifoQ           : Add a message to the Tx FIFO/Queue and activate the corresponding transmission request
+      (+) HAL_FDCAN_AddMessageToTxBuffer          : Add a message to a dedicated Tx buffer
+      (+) HAL_FDCAN_EnableTxBufferRequest         : Enable transmission request
+      (+) HAL_FDCAN_GetLatestTxFifoQRequestBuffer : Get Tx buffer index of latest Tx FIFO/Queue request
+      (+) HAL_FDCAN_AbortTxRequest                : Abort transmission request
+      (+) HAL_FDCAN_GetRxMessage                  : Get an FDCAN frame from the Rx Buffer/FIFO zone into the message RAM
+      (+) HAL_FDCAN_GetTxEvent                    : Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM
+      (+) HAL_FDCAN_GetHighPriorityMessageStatus  : Get high priority message status
+      (+) HAL_FDCAN_GetProtocolStatus             : Get protocol status
+      (+) HAL_FDCAN_GetErrorCounters              : Get error counter values
+      (+) HAL_FDCAN_IsRxBufferMessageAvailable    : Check if a new message is received in the selected Rx buffer
+      (+) HAL_FDCAN_IsTxBufferMessagePending      : Check if a transmission request is pending on the selected Tx buffer
+      (+) HAL_FDCAN_GetRxFifoFillLevel            : Return Rx FIFO fill level
+      (+) HAL_FDCAN_GetTxFifoFreeLevel            : Return Tx FIFO free level
+      (+) HAL_FDCAN_IsRestrictedOperationMode     : Check if the FDCAN peripheral entered Restricted Operation Mode
+      (+) HAL_FDCAN_ExitRestrictedOperationMode   : Exit Restricted Operation Mode
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Start the FDCAN module.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Change FDCAN peripheral state */
+    hfdcan->State = HAL_FDCAN_STATE_BUSY;
+
+    /* Request leave initialisation */
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
+
+    /* Reset the FDCAN ErrorCode */
+    hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Stop the FDCAN module and enable access to configuration registers.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+
+  if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
+  {
+    /* Request initialisation */
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
+
+    /* Wait until the INIT bit into CCCR register is set */
+    while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Reset counter */
+    Counter = 0U;
+
+    /* Exit from Sleep mode */
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
+
+    /* Wait until FDCAN exits sleep mode */
+    while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Enable configuration change */
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE);
+
+    /* Reset Latest Tx FIFO/Queue Request Buffer Index */
+    hfdcan->LatestTxFifoQRequest = 0U;
+
+    /* Change FDCAN peripheral state */
+    hfdcan->State = HAL_FDCAN_STATE_READY;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Add a message to the Tx FIFO/Queue and activate the corresponding transmission request
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure.
+  * @param  pTxData pointer to a buffer containing the payload of the Tx frame.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData)
+{
+  uint32_t PutIndex;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_ID_TYPE(pTxHeader->IdType));
+  if (pTxHeader->IdType == FDCAN_STANDARD_ID)
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x7FFU));
+  }
+  else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x1FFFFFFFU));
+  }
+  assert_param(IS_FDCAN_FRAME_TYPE(pTxHeader->TxFrameType));
+  assert_param(IS_FDCAN_DLC(pTxHeader->DataLength));
+  assert_param(IS_FDCAN_ESI(pTxHeader->ErrorStateIndicator));
+  assert_param(IS_FDCAN_BRS(pTxHeader->BitRateSwitch));
+  assert_param(IS_FDCAN_FDF(pTxHeader->FDFormat));
+  assert_param(IS_FDCAN_EFC(pTxHeader->TxEventFifoControl));
+  assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->MessageMarker, 0xFFU));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
+  {
+    /* Check that the Tx FIFO/Queue has an allocated area into the RAM */
+    if ((hfdcan->Instance->TXBC & FDCAN_TXBC_TFQS) == 0U)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+      return HAL_ERROR;
+    }
+
+    /* Check that the Tx FIFO/Queue is not full */
+    if ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQF) != 0U)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_FULL;
+
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Retrieve the Tx FIFO PutIndex */
+      PutIndex = ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQPI) >> FDCAN_TXFQS_TFQPI_Pos);
+
+      /* Add the message to the Tx FIFO/Queue */
+      FDCAN_CopyMessageToRAM(hfdcan, pTxHeader, pTxData, PutIndex);
+
+      /* Activate the corresponding transmission request */
+      hfdcan->Instance->TXBAR = ((uint32_t)1 << PutIndex);
+
+      /* Store the Latest Tx FIFO/Queue Request Buffer Index */
+      hfdcan->LatestTxFifoQRequest = ((uint32_t)1 << PutIndex);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Add a message to a dedicated Tx buffer
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure.
+  * @param  pTxData pointer to a buffer containing the payload of the Tx frame.
+  * @param  BufferIndex index of the buffer to be configured.
+  *         This parameter can be a value of @arg FDCAN_Tx_location.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxBuffer(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex)
+{
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_ID_TYPE(pTxHeader->IdType));
+  if (pTxHeader->IdType == FDCAN_STANDARD_ID)
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x7FFU));
+  }
+  else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x1FFFFFFFU));
+  }
+  assert_param(IS_FDCAN_FRAME_TYPE(pTxHeader->TxFrameType));
+  assert_param(IS_FDCAN_DLC(pTxHeader->DataLength));
+  assert_param(IS_FDCAN_ESI(pTxHeader->ErrorStateIndicator));
+  assert_param(IS_FDCAN_BRS(pTxHeader->BitRateSwitch));
+  assert_param(IS_FDCAN_FDF(pTxHeader->FDFormat));
+  assert_param(IS_FDCAN_EFC(pTxHeader->TxEventFifoControl));
+  assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->MessageMarker, 0xFFU));
+  assert_param(IS_FDCAN_TX_LOCATION(BufferIndex));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Check that the selected buffer has an allocated area into the RAM */
+    if (POSITION_VAL(BufferIndex) >= ((hfdcan->Instance->TXBC & FDCAN_TXBC_NDTB) >> FDCAN_TXBC_NDTB_Pos))
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+      return HAL_ERROR;
+    }
+
+    /* Check that there is no transmittion request pending for the selected buffer */
+    if ((hfdcan->Instance->TXBRP & BufferIndex) != 0U)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING;
+
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Add the message to the Tx buffer */
+      FDCAN_CopyMessageToRAM(hfdcan, pTxHeader, pTxData, POSITION_VAL(BufferIndex));
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable transmission request.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  BufferIndex buffer index.
+  *         This parameter can be any combination of @arg FDCAN_Tx_location.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_EnableTxBufferRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
+  {
+    /* Add transmission request */
+    hfdcan->Instance->TXBAR = BufferIndex;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get Tx buffer index of latest Tx FIFO/Queue request
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval Tx buffer index of last Tx FIFO/Queue request
+  *          - Any value of @arg FDCAN_Tx_location if Tx request has been submitted.
+  *          - 0 if no Tx FIFO/Queue request have been submitted.
+  */
+uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Return Last Tx FIFO/Queue Request Buffer */
+  return hfdcan->LatestTxFifoQRequest;
+}
+
+/**
+  * @brief  Abort transmission request
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  BufferIndex buffer index.
+  *         This parameter can be any combination of @arg FDCAN_Tx_location.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex)
+{
+  if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
+  {
+    /* Add cancellation request */
+    hfdcan->Instance->TXBCR = BufferIndex;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get an FDCAN frame from the Rx Buffer/FIFO zone into the message RAM.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  RxLocation Location of the received message to be read.
+  *         This parameter can be a value of @arg FDCAN_Rx_location.
+  * @param  pRxHeader pointer to a FDCAN_RxHeaderTypeDef structure.
+  * @param  pRxData pointer to a buffer where the payload of the Rx frame will be stored.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData)
+{
+  uint32_t *RxAddress;
+  uint8_t  *pData;
+  uint32_t ByteCounter;
+  uint32_t GetIndex = 0;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  if (state == HAL_FDCAN_STATE_BUSY)
+  {
+    if (RxLocation == FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */
+    {
+      /* Check that the Rx FIFO 0 has an allocated area into the RAM */
+      if ((hfdcan->Instance->RXF0C & FDCAN_RXF0C_F0S) == 0U)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+        return HAL_ERROR;
+      }
+
+      /* Check that the Rx FIFO 0 is not empty */
+      if ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0FL) == 0U)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
+
+        return HAL_ERROR;
+      }
+      else
+      {
+        /* Calculate Rx FIFO 0 element address */
+        GetIndex = ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0GI) >> FDCAN_RXF0S_F0GI_Pos);
+        RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO0SA + (GetIndex * hfdcan->Init.RxFifo0ElmtSize * 4U));
+      }
+    }
+    else if (RxLocation == FDCAN_RX_FIFO1) /* Rx element is assigned to the Rx FIFO 1 */
+    {
+      /* Check that the Rx FIFO 1 has an allocated area into the RAM */
+      if ((hfdcan->Instance->RXF1C & FDCAN_RXF1C_F1S) == 0U)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+        return HAL_ERROR;
+      }
+
+      /* Check that the Rx FIFO 0 is not empty */
+      if ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL) == 0U)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
+
+        return HAL_ERROR;
+      }
+      else
+      {
+        /* Calculate Rx FIFO 1 element address */
+        GetIndex = ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1GI) >> FDCAN_RXF1S_F1GI_Pos);
+        RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO1SA + (GetIndex * hfdcan->Init.RxFifo1ElmtSize * 4U));
+      }
+    }
+    else /* Rx element is assigned to a dedicated Rx buffer */
+    {
+      /* Check that the selected buffer has an allocated area into the RAM */
+      if (RxLocation >= hfdcan->Init.RxBuffersNbr)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+        return HAL_ERROR;
+      }
+      else
+      {
+        /* Calculate Rx buffer address */
+        RxAddress = (uint32_t *)(hfdcan->msgRam.RxBufferSA + (RxLocation * hfdcan->Init.RxBufferSize * 4U));
+      }
+    }
+
+    /* Retrieve IdType */
+    pRxHeader->IdType = *RxAddress & FDCAN_ELEMENT_MASK_XTD;
+
+    /* Retrieve Identifier */
+    if (pRxHeader->IdType == FDCAN_STANDARD_ID) /* Standard ID element */
+    {
+      pRxHeader->Identifier = ((*RxAddress & FDCAN_ELEMENT_MASK_STDID) >> 18);
+    }
+    else /* Extended ID element */
+    {
+      pRxHeader->Identifier = (*RxAddress & FDCAN_ELEMENT_MASK_EXTID);
+    }
+
+    /* Retrieve RxFrameType */
+    pRxHeader->RxFrameType = (*RxAddress & FDCAN_ELEMENT_MASK_RTR);
+
+    /* Retrieve ErrorStateIndicator */
+    pRxHeader->ErrorStateIndicator = (*RxAddress & FDCAN_ELEMENT_MASK_ESI);
+
+    /* Increment RxAddress pointer to second word of Rx FIFO element */
+    RxAddress++;
+
+    /* Retrieve RxTimestamp */
+    pRxHeader->RxTimestamp = (*RxAddress & FDCAN_ELEMENT_MASK_TS);
+
+    /* Retrieve DataLength */
+    pRxHeader->DataLength = (*RxAddress & FDCAN_ELEMENT_MASK_DLC);
+
+    /* Retrieve BitRateSwitch */
+    pRxHeader->BitRateSwitch = (*RxAddress & FDCAN_ELEMENT_MASK_BRS);
+
+    /* Retrieve FDFormat */
+    pRxHeader->FDFormat = (*RxAddress & FDCAN_ELEMENT_MASK_FDF);
+
+    /* Retrieve FilterIndex */
+    pRxHeader->FilterIndex = ((*RxAddress & FDCAN_ELEMENT_MASK_FIDX) >> 24);
+
+    /* Retrieve NonMatchingFrame */
+    pRxHeader->IsFilterMatchingFrame = ((*RxAddress & FDCAN_ELEMENT_MASK_ANMF) >> 31);
+
+    /* Increment RxAddress pointer to payload of Rx FIFO element */
+    RxAddress++;
+
+    /* Retrieve Rx payload */
+    pData = (uint8_t *)RxAddress;
+    for (ByteCounter = 0; ByteCounter < DLCtoBytes[pRxHeader->DataLength >> 16]; ByteCounter++)
+    {
+      pRxData[ByteCounter] = pData[ByteCounter];
+    }
+
+    if (RxLocation == FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */
+    {
+      /* Acknowledge the Rx FIFO 0 that the oldest element is read so that it increments the GetIndex */
+      hfdcan->Instance->RXF0A = GetIndex;
+    }
+    else if (RxLocation == FDCAN_RX_FIFO1) /* Rx element is assigned to the Rx FIFO 1 */
+    {
+      /* Acknowledge the Rx FIFO 1 that the oldest element is read so that it increments the GetIndex */
+      hfdcan->Instance->RXF1A = GetIndex;
+    }
+    else /* Rx element is assigned to a dedicated Rx buffer */
+    {
+      /* Clear the New Data flag of the current Rx buffer */
+      if (RxLocation < FDCAN_RX_BUFFER32)
+      {
+        hfdcan->Instance->NDAT1 = ((uint32_t)1 << RxLocation);
+      }
+      else /* FDCAN_RX_BUFFER32 <= RxLocation <= FDCAN_RX_BUFFER63 */
+      {
+        hfdcan->Instance->NDAT2 = ((uint32_t)1 << (RxLocation & 0x1FU));
+      }
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  pTxEvent pointer to a FDCAN_TxEventFifoTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent)
+{
+  uint32_t *TxEventAddress;
+  uint32_t GetIndex;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_MIN_VALUE(hfdcan->Init.TxEventsNbr, 1U));
+
+  if (state == HAL_FDCAN_STATE_BUSY)
+  {
+    /* Check that the Tx Event FIFO has an allocated area into the RAM */
+    if ((hfdcan->Instance->TXEFC & FDCAN_TXEFC_EFS) == 0U)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+      return HAL_ERROR;
+    }
+
+    /* Check that the Tx event FIFO is not empty */
+    if ((hfdcan->Instance->TXEFS & FDCAN_TXEFS_EFFL) == 0U)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
+
+      return HAL_ERROR;
+    }
+
+    /* Calculate Tx event FIFO element address */
+    GetIndex = ((hfdcan->Instance->TXEFS & FDCAN_TXEFS_EFGI) >> FDCAN_TXEFS_EFGI_Pos);
+    TxEventAddress = (uint32_t *)(hfdcan->msgRam.TxEventFIFOSA + (GetIndex * 2U * 4U));
+
+    /* Retrieve IdType */
+    pTxEvent->IdType = *TxEventAddress & FDCAN_ELEMENT_MASK_XTD;
+
+    /* Retrieve Identifier */
+    if (pTxEvent->IdType == FDCAN_STANDARD_ID) /* Standard ID element */
+    {
+      pTxEvent->Identifier = ((*TxEventAddress & FDCAN_ELEMENT_MASK_STDID) >> 18U);
+    }
+    else /* Extended ID element */
+    {
+      pTxEvent->Identifier = (*TxEventAddress & FDCAN_ELEMENT_MASK_EXTID);
+    }
+
+    /* Retrieve RxFrameType */
+    pTxEvent->TxFrameType = (*TxEventAddress & FDCAN_ELEMENT_MASK_RTR);
+
+    /* Retrieve ErrorStateIndicator */
+    pTxEvent->ErrorStateIndicator = (*TxEventAddress & FDCAN_ELEMENT_MASK_ESI);
+
+    /* Increment TxEventAddress pointer to second word of Tx Event FIFO element */
+    TxEventAddress++;
+
+    /* Retrieve RxTimestamp */
+    pTxEvent->TxTimestamp = (*TxEventAddress & FDCAN_ELEMENT_MASK_TS);
+
+    /* Retrieve DataLength */
+    pTxEvent->DataLength = (*TxEventAddress & FDCAN_ELEMENT_MASK_DLC);
+
+    /* Retrieve BitRateSwitch */
+    pTxEvent->BitRateSwitch = (*TxEventAddress & FDCAN_ELEMENT_MASK_BRS);
+
+    /* Retrieve FDFormat */
+    pTxEvent->FDFormat = (*TxEventAddress & FDCAN_ELEMENT_MASK_FDF);
+
+    /* Retrieve EventType */
+    pTxEvent->EventType = (*TxEventAddress & FDCAN_ELEMENT_MASK_ET);
+
+    /* Retrieve MessageMarker */
+    pTxEvent->MessageMarker = ((*TxEventAddress & FDCAN_ELEMENT_MASK_MM) >> 24);
+
+    /* Acknowledge the Tx Event FIFO that the oldest element is read so that it increments the GetIndex */
+    hfdcan->Instance->TXEFA = GetIndex;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get high priority message status.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  HpMsgStatus pointer to an FDCAN_HpMsgStatusTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus)
+{
+  HpMsgStatus->FilterList = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FLST) >> FDCAN_HPMS_FLST_Pos);
+  HpMsgStatus->FilterIndex = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FIDX) >> FDCAN_HPMS_FIDX_Pos);
+  HpMsgStatus->MessageStorage = (hfdcan->Instance->HPMS & FDCAN_HPMS_MSI);
+  HpMsgStatus->MessageIndex = (hfdcan->Instance->HPMS & FDCAN_HPMS_BIDX);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get protocol status.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  ProtocolStatus pointer to an FDCAN_ProtocolStatusTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus)
+{
+  uint32_t StatusReg;
+
+  /* Read the protocol status register */
+  StatusReg = READ_REG(hfdcan->Instance->PSR);
+
+  /* Fill the protocol status structure */
+  ProtocolStatus->LastErrorCode = (StatusReg & FDCAN_PSR_LEC);
+  ProtocolStatus->DataLastErrorCode = ((StatusReg & FDCAN_PSR_DLEC) >> FDCAN_PSR_DLEC_Pos);
+  ProtocolStatus->Activity = (StatusReg & FDCAN_PSR_ACT);
+  ProtocolStatus->ErrorPassive = ((StatusReg & FDCAN_PSR_EP) >> FDCAN_PSR_EP_Pos);
+  ProtocolStatus->Warning = ((StatusReg & FDCAN_PSR_EW) >> FDCAN_PSR_EW_Pos);
+  ProtocolStatus->BusOff = ((StatusReg & FDCAN_PSR_BO) >> FDCAN_PSR_BO_Pos);
+  ProtocolStatus->RxESIflag = ((StatusReg & FDCAN_PSR_RESI) >> FDCAN_PSR_RESI_Pos);
+  ProtocolStatus->RxBRSflag = ((StatusReg & FDCAN_PSR_RBRS) >> FDCAN_PSR_RBRS_Pos);
+  ProtocolStatus->RxFDFflag = ((StatusReg & FDCAN_PSR_REDL) >> FDCAN_PSR_REDL_Pos);
+  ProtocolStatus->ProtocolException = ((StatusReg & FDCAN_PSR_PXE) >> FDCAN_PSR_PXE_Pos);
+  ProtocolStatus->TDCvalue = ((StatusReg & FDCAN_PSR_TDCV) >> FDCAN_PSR_TDCV_Pos);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get error counter values.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  ErrorCounters pointer to an FDCAN_ErrorCountersTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters)
+{
+  uint32_t CountersReg;
+
+  /* Read the error counters register */
+  CountersReg = READ_REG(hfdcan->Instance->ECR);
+
+  /* Fill the error counters structure */
+  ErrorCounters->TxErrorCnt = ((CountersReg & FDCAN_ECR_TEC) >> FDCAN_ECR_TEC_Pos);
+  ErrorCounters->RxErrorCnt = ((CountersReg & FDCAN_ECR_REC) >> FDCAN_ECR_REC_Pos);
+  ErrorCounters->RxErrorPassive = ((CountersReg & FDCAN_ECR_RP) >> FDCAN_ECR_RP_Pos);
+  ErrorCounters->ErrorLogging = ((CountersReg & FDCAN_ECR_CEL) >> FDCAN_ECR_CEL_Pos);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Check if a new message is received in the selected Rx buffer.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  RxBufferIndex Rx buffer index.
+  *         This parameter must be a number between 0 and 63.
+  * @retval Status
+  *          - 0 : No new message on RxBufferIndex.
+  *          - 1 : New message received on RxBufferIndex.
+  */
+uint32_t HAL_FDCAN_IsRxBufferMessageAvailable(FDCAN_HandleTypeDef *hfdcan, uint32_t RxBufferIndex)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_MAX_VALUE(RxBufferIndex, 63U));
+  uint32_t NewData1 = hfdcan->Instance->NDAT1;
+  uint32_t NewData2 = hfdcan->Instance->NDAT2;
+
+  /* Check new message reception on the selected buffer */
+  if (((RxBufferIndex < 32U) && ((NewData1 & (uint32_t)((uint32_t)1 << RxBufferIndex)) == 0U)) ||
+      ((RxBufferIndex >= 32U) && ((NewData2 & (uint32_t)((uint32_t)1 << (RxBufferIndex & 0x1FU))) == 0U)))
+  {
+    return 0;
+  }
+
+  /* Clear the New Data flag of the current Rx buffer */
+  if (RxBufferIndex < 32U)
+  {
+    hfdcan->Instance->NDAT1 = ((uint32_t)1 << RxBufferIndex);
+  }
+  else /* 32 <= RxBufferIndex <= 63 */
+  {
+    hfdcan->Instance->NDAT2 = ((uint32_t)1 << (RxBufferIndex & 0x1FU));
+  }
+
+  return 1;
+}
+
+/**
+  * @brief  Check if a transmission request is pending on the selected Tx buffer.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TxBufferIndex Tx buffer index.
+  *         This parameter can be any combination of @arg FDCAN_Tx_location.
+  * @retval Status
+  *          - 0 : No pending transmission request on TxBufferIndex.
+  *          - 1 : Pending transmission request on TxBufferIndex.
+  */
+uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex)
+{
+  /* Check pending transmittion request on the selected buffer */
+  if ((hfdcan->Instance->TXBRP & TxBufferIndex) == 0U)
+  {
+    return 0;
+  }
+  return 1;
+}
+
+/**
+  * @brief  Return Rx FIFO fill level.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  RxFifo Rx FIFO.
+  *         This parameter can be one of the following values:
+  *           @arg FDCAN_RX_FIFO0: Rx FIFO 0
+  *           @arg FDCAN_RX_FIFO1: Rx FIFO 1
+  * @retval Level Rx FIFO fill level.
+  */
+uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo)
+{
+  uint32_t FillLevel;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_RX_FIFO(RxFifo));
+
+  if (RxFifo == FDCAN_RX_FIFO0)
+  {
+    FillLevel = hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0FL;
+  }
+  else /* RxFifo == FDCAN_RX_FIFO1 */
+  {
+    FillLevel = hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL;
+  }
+
+  /* Return Rx FIFO fill level */
+  return FillLevel;
+}
+
+/**
+  * @brief  Return Tx FIFO free level: number of consecutive free Tx FIFO
+  *         elements starting from Tx FIFO GetIndex.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval Level Tx FIFO free level.
+  */
+uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t FreeLevel;
+
+  FreeLevel = hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFFL;
+
+  /* Return Tx FIFO free level */
+  return FreeLevel;
+}
+
+/**
+  * @brief  Check if the FDCAN peripheral entered Restricted Operation Mode.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval Status
+  *          - 0 : Normal FDCAN operation.
+  *          - 1 : Restricted Operation Mode active.
+  */
+uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t OperationMode;
+
+  /* Get Operation Mode */
+  OperationMode = ((hfdcan->Instance->CCCR & FDCAN_CCCR_ASM) >> FDCAN_CCCR_ASM_Pos);
+
+  return OperationMode;
+}
+
+/**
+  * @brief  Exit Restricted Operation Mode.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan)
+{
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Exit Restricted Operation mode */
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Exported_Functions_Group4 TT Configuration and control functions
+ *  @brief    TT Configuration and control functions
+ *
+@verbatim
+  ==============================================================================
+              ##### TT Configuration and control functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) HAL_FDCAN_TT_ConfigOperation                  : Initialize TT operation parameters
+      (+) HAL_FDCAN_TT_ConfigReferenceMessage           : Configure the reference message
+      (+) HAL_FDCAN_TT_ConfigTrigger                    : Configure the FDCAN trigger
+      (+) HAL_FDCAN_TT_SetGlobalTime                    : Schedule global time adjustment
+      (+) HAL_FDCAN_TT_SetClockSynchronization          : Schedule TUR numerator update
+      (+) HAL_FDCAN_TT_ConfigStopWatch                  : Configure stop watch source and polarity
+      (+) HAL_FDCAN_TT_ConfigRegisterTimeMark           : Configure register time mark pulse generation
+        (+) HAL_FDCAN_TT_EnableRegisterTimeMarkPulse      : Enable register time mark pulse generation
+        (+) HAL_FDCAN_TT_DisableRegisterTimeMarkPulse     : Disable register time mark pulse generation
+      (+) HAL_FDCAN_TT_EnableTriggerTimeMarkPulse       : Enable trigger time mark pulse generation
+      (+) HAL_FDCAN_TT_DisableTriggerTimeMarkPulse      : Disable trigger time mark pulse generation
+      (+) HAL_FDCAN_TT_EnableHardwareGapControl         : Enable gap control by input pin fdcan1_evt
+      (+) HAL_FDCAN_TT_DisableHardwareGapControl        : Disable gap control by input pin fdcan1_evt
+      (+) HAL_FDCAN_TT_EnableTimeMarkGapControl         : Enable gap control (finish only) by register time mark interrupt
+      (+) HAL_FDCAN_TT_DisableTimeMarkGapControl        : Disable gap control by register time mark interrupt
+      (+) HAL_FDCAN_TT_SetNextIsGap                     : Transmit next reference message with Next_is_Gap = "1"
+      (+) HAL_FDCAN_TT_SetEndOfGap                      : Finish a Gap by requesting start of reference message
+      (+) HAL_FDCAN_TT_ConfigExternalSyncPhase          : Configure target phase used for external synchronization
+        (+) HAL_FDCAN_TT_EnableExternalSynchronization    : Synchronize the phase of the FDCAN schedule to an external schedule
+        (+) HAL_FDCAN_TT_DisableExternalSynchronization   : Disable external schedule synchronization
+      (+) HAL_FDCAN_TT_GetOperationStatus               : Get TT operation status
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize TT operation parameters.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  pTTParams pointer to a FDCAN_TT_ConfigTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigOperation(FDCAN_HandleTypeDef *hfdcan, FDCAN_TT_ConfigTypeDef *pTTParams)
+{
+  uint32_t tickstart;
+  uint32_t RAMcounter;
+  uint32_t StartAddress;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_TUR_NUMERATOR(pTTParams->TURNumerator));
+  assert_param(IS_FDCAN_TT_TUR_DENOMINATOR(pTTParams->TURDenominator));
+  assert_param(IS_FDCAN_TT_TIME_MASTER(pTTParams->TimeMaster));
+  assert_param(IS_FDCAN_MAX_VALUE(pTTParams->SyncDevLimit, 7U));
+  assert_param(IS_FDCAN_MAX_VALUE(pTTParams->InitRefTrigOffset, 127U));
+  assert_param(IS_FDCAN_MAX_VALUE(pTTParams->TriggerMemoryNbr, 64U));
+  assert_param(IS_FDCAN_TT_CYCLE_START_SYNC(pTTParams->CycleStartSync));
+  assert_param(IS_FDCAN_TT_STOP_WATCH_TRIGGER(pTTParams->StopWatchTrigSel));
+  assert_param(IS_FDCAN_TT_EVENT_TRIGGER(pTTParams->EventTrigSel));
+  if (pTTParams->TimeMaster == FDCAN_TT_POTENTIAL_MASTER)
+  {
+    assert_param(IS_FDCAN_TT_BASIC_CYCLES_NUMBER(pTTParams->BasicCyclesNbr));
+  }
+  if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL0)
+  {
+    assert_param(IS_FDCAN_TT_OPERATION(pTTParams->GapEnable));
+    assert_param(IS_FDCAN_MAX_VALUE(pTTParams->AppWdgLimit, 255U));
+    assert_param(IS_FDCAN_TT_EVENT_TRIGGER_POLARITY(pTTParams->EvtTrigPolarity));
+    assert_param(IS_FDCAN_TT_TX_ENABLE_WINDOW(pTTParams->TxEnableWindow));
+    assert_param(IS_FDCAN_MAX_VALUE(pTTParams->ExpTxTrigNbr, 4095U));
+  }
+  if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL1)
+  {
+    assert_param(IS_FDCAN_TT_TUR_LEVEL_0_2(pTTParams->TURNumerator, pTTParams->TURDenominator));
+    assert_param(IS_FDCAN_TT_EXTERNAL_CLK_SYNC(pTTParams->ExternalClkSync));
+    assert_param(IS_FDCAN_TT_GLOBAL_TIME_FILTERING(pTTParams->GlobalTimeFilter));
+    assert_param(IS_FDCAN_TT_AUTO_CLK_CALIBRATION(pTTParams->ClockCalibration));
+  }
+  else
+  {
+    assert_param(IS_FDCAN_TT_TUR_LEVEL_1(pTTParams->TURNumerator, pTTParams->TURDenominator));
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Stop local time in order to enable write access to the other bits of TURCF register */
+    CLEAR_BIT(hfdcan->ttcan->TURCF, FDCAN_TURCF_ELT);
+
+    /* Get tick */
+    tickstart = HAL_GetTick();
+
+    /* Wait until the ELT bit into TURCF register is reset */
+    while ((hfdcan->ttcan->TURCF & FDCAN_TURCF_ELT) != 0U)
+    {
+      /* Check for the Timeout */
+      if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+    }
+
+    /* Configure TUR (Time Unit Ratio) */
+    MODIFY_REG(hfdcan->ttcan->TURCF,
+               (FDCAN_TURCF_NCL | FDCAN_TURCF_DC),
+               (((pTTParams->TURNumerator - 0x10000U) << FDCAN_TURCF_NCL_Pos) | (pTTParams->TURDenominator << FDCAN_TURCF_DC_Pos)));
+
+    /* Enable local time */
+    SET_BIT(hfdcan->ttcan->TURCF, FDCAN_TURCF_ELT);
+
+    /* Configure TT operation */
+    MODIFY_REG(hfdcan->ttcan->TTOCF,
+               (FDCAN_TTOCF_OM | FDCAN_TTOCF_TM | FDCAN_TTOCF_LDSDL | FDCAN_TTOCF_IRTO),
+               (pTTParams->OperationMode                           | \
+                pTTParams->TimeMaster                              | \
+                (pTTParams->SyncDevLimit << FDCAN_TTOCF_LDSDL_Pos) | \
+                (pTTParams->InitRefTrigOffset << FDCAN_TTOCF_IRTO_Pos)));
+    if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      MODIFY_REG(hfdcan->ttcan->TTOCF,
+                 (FDCAN_TTOCF_GEN | FDCAN_TTOCF_AWL | FDCAN_TTOCF_EVTP),
+                 (pTTParams->GapEnable                            | \
+                  (pTTParams->AppWdgLimit << FDCAN_TTOCF_AWL_Pos) | \
+                  pTTParams->EvtTrigPolarity));
+    }
+    if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL1)
+    {
+      MODIFY_REG(hfdcan->ttcan->TTOCF,
+                 (FDCAN_TTOCF_EECS | FDCAN_TTOCF_EGTF | FDCAN_TTOCF_ECC),
+                 (pTTParams->ExternalClkSync  | \
+                  pTTParams->GlobalTimeFilter | \
+                  pTTParams->ClockCalibration));
+    }
+
+    /* Configure system matrix limits */
+    MODIFY_REG(hfdcan->ttcan->TTMLM, FDCAN_TTMLM_CSS, pTTParams->CycleStartSync);
+    if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      MODIFY_REG(hfdcan->ttcan->TTMLM,
+                 (FDCAN_TTMLM_TXEW | FDCAN_TTMLM_ENTT),
+                 (((pTTParams->TxEnableWindow - 1U) << FDCAN_TTMLM_TXEW_Pos) | (pTTParams->ExpTxTrigNbr << FDCAN_TTMLM_ENTT_Pos)));
+    }
+    if (pTTParams->TimeMaster == FDCAN_TT_POTENTIAL_MASTER)
+    {
+      MODIFY_REG(hfdcan->ttcan->TTMLM, FDCAN_TTMLM_CCM, pTTParams->BasicCyclesNbr);
+    }
+
+    /* Configure input triggers: Stop watch and Event */
+    MODIFY_REG(hfdcan->ttcan->TTTS,
+               (FDCAN_TTTS_SWTSEL | FDCAN_TTTS_EVTSEL),
+               (pTTParams->StopWatchTrigSel | pTTParams->EventTrigSel));
+
+    /* Configure trigger memory start address */
+    StartAddress = (hfdcan->msgRam.EndAddress - SRAMCAN_BASE) / 4U;
+    MODIFY_REG(hfdcan->ttcan->TTTMC, FDCAN_TTTMC_TMSA, (StartAddress << FDCAN_TTTMC_TMSA_Pos));
+
+    /* Trigger memory elements number */
+    MODIFY_REG(hfdcan->ttcan->TTTMC, FDCAN_TTTMC_TME, (pTTParams->TriggerMemoryNbr << FDCAN_TTTMC_TME_Pos));
+
+    /* Recalculate End Address */
+    hfdcan->msgRam.TTMemorySA = hfdcan->msgRam.EndAddress;
+    hfdcan->msgRam.EndAddress = hfdcan->msgRam.TTMemorySA + (pTTParams->TriggerMemoryNbr * 2U * 4U);
+
+    if (hfdcan->msgRam.EndAddress > FDCAN_MESSAGE_RAM_END_ADDRESS) /* Last address of the Message RAM */
+    {
+      /* Update error code.
+         Message RAM overflow */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Flush the allocated Message RAM area */
+      for (RAMcounter = hfdcan->msgRam.TTMemorySA; RAMcounter < hfdcan->msgRam.EndAddress; RAMcounter += 4U)
+      {
+        *(uint32_t *)(RAMcounter) = 0x00000000;
+      }
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the reference message.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  IdType Identifier Type.
+  *         This parameter can be a value of @arg FDCAN_id_type.
+  * @param  Identifier Reference Identifier.
+  *         This parameter must be a number between:
+  *           - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+  *           - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID
+  * @param  Payload Enable or disable the additional payload.
+  *         This parameter can be a value of @arg FDCAN_TT_Reference_Message_Payload.
+  *         This parameter is ignored in case of time slaves.
+  *         If this parameter is set to FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD, the
+  *         following elements are taken from Tx Buffer 0:
+  *          - MessageMarker
+  *          - TxEventFifoControl
+  *          - DataLength
+  *          - Data Bytes (payload):
+  *             - bytes 2-8, for Level 1
+  *             - bytes 5-8, for Level 0 and Level 2
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigReferenceMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t IdType, uint32_t Identifier, uint32_t Payload)
+{
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_ID_TYPE(IdType));
+  if (IdType == FDCAN_STANDARD_ID)
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(Identifier, 0x7FFU));
+  }
+  else /* IdType == FDCAN_EXTENDED_ID */
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(Identifier, 0x1FFFFFFFU));
+  }
+  assert_param(IS_FDCAN_TT_REFERENCE_MESSAGE_PAYLOAD(Payload));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Configure reference message identifier type, identifier and payload */
+    if (IdType == FDCAN_EXTENDED_ID)
+    {
+      MODIFY_REG(hfdcan->ttcan->TTRMC, (FDCAN_TTRMC_RID | FDCAN_TTRMC_XTD | FDCAN_TTRMC_RMPS), (Payload | IdType | Identifier));
+    }
+    else /* IdType == FDCAN_STANDARD_ID */
+    {
+      MODIFY_REG(hfdcan->ttcan->TTRMC, (FDCAN_TTRMC_RID | FDCAN_TTRMC_XTD | FDCAN_TTRMC_RMPS), (Payload | IdType | (Identifier << 18)));
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the FDCAN trigger according to the specified
+  *         parameters in the FDCAN_TriggerTypeDef structure.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  sTriggerConfig pointer to an FDCAN_TriggerTypeDef structure that
+  *         contains the trigger configuration information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigTrigger(FDCAN_HandleTypeDef *hfdcan, FDCAN_TriggerTypeDef *sTriggerConfig)
+{
+  uint32_t CycleCode;
+  uint32_t MessageNumber;
+  uint32_t TriggerElementW1;
+  uint32_t TriggerElementW2;
+  uint32_t *TriggerAddress;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->TriggerIndex, 63U));
+  assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->TimeMark, 0xFFFFU));
+  assert_param(IS_FDCAN_TT_REPEAT_FACTOR(sTriggerConfig->RepeatFactor));
+  if (sTriggerConfig->RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE)
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->StartCycle, (sTriggerConfig->RepeatFactor - 1U)));
+  }
+  assert_param(IS_FDCAN_TT_TM_EVENT_INTERNAL(sTriggerConfig->TmEventInt));
+  assert_param(IS_FDCAN_TT_TM_EVENT_EXTERNAL(sTriggerConfig->TmEventExt));
+  assert_param(IS_FDCAN_TT_TRIGGER_TYPE(sTriggerConfig->TriggerType));
+  assert_param(IS_FDCAN_ID_TYPE(sTriggerConfig->FilterType));
+  if ((sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_SINGLE) ||
+      (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_CONTINUOUS) ||
+      (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_ARBITRATION) ||
+      (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_MERGED))
+  {
+    assert_param(IS_FDCAN_TX_LOCATION(sTriggerConfig->TxBufferIndex));
+  }
+  if (sTriggerConfig->TriggerType == FDCAN_TT_RX_TRIGGER)
+  {
+    if (sTriggerConfig->FilterType == FDCAN_STANDARD_ID)
+    {
+      assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->FilterIndex, 63U));
+    }
+    else /* sTriggerConfig->FilterType == FDCAN_EXTENDED_ID */
+    {
+      assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->FilterIndex, 127U));
+    }
+  }
+
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+  {
+    /* Calculate cycle code */
+    if (sTriggerConfig->RepeatFactor == FDCAN_TT_REPEAT_EVERY_CYCLE)
+    {
+      CycleCode = FDCAN_TT_REPEAT_EVERY_CYCLE;
+    }
+    else /* sTriggerConfig->RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE */
+    {
+      CycleCode = sTriggerConfig->RepeatFactor + sTriggerConfig->StartCycle;
+    }
+
+    /* Build first word of trigger element */
+    TriggerElementW1 = ((sTriggerConfig->TimeMark << 16) | \
+                        (CycleCode << 8)                 | \
+                        sTriggerConfig->TmEventInt       | \
+                        sTriggerConfig->TmEventExt       | \
+                        sTriggerConfig->TriggerType);
+
+    /* Select message number depending on trigger type (transmission or reception) */
+    if (sTriggerConfig->TriggerType == FDCAN_TT_RX_TRIGGER)
+    {
+      MessageNumber = sTriggerConfig->FilterIndex;
+    }
+    else if ((sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_SINGLE) ||
+             (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_CONTINUOUS) ||
+             (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_ARBITRATION) ||
+             (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_MERGED))
+    {
+      MessageNumber = POSITION_VAL(sTriggerConfig->TxBufferIndex);
+    }
+    else
+    {
+      MessageNumber = 0U;
+    }
+
+    /* Build second word of trigger element */
+    TriggerElementW2 = ((sTriggerConfig->FilterType >> 7) | (MessageNumber << 16));
+
+    /* Calculate trigger address */
+    TriggerAddress = (uint32_t *)(hfdcan->msgRam.TTMemorySA + (sTriggerConfig->TriggerIndex * 4U * 2U));
+
+    /* Write trigger element to the message RAM */
+    *TriggerAddress = TriggerElementW1;
+    TriggerAddress++;
+    *TriggerAddress = TriggerElementW2;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Schedule global time adjustment for the next reference message.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TimePreset time preset value.
+  *         This parameter must be a number between:
+  *           - 0x0000 and 0x7FFF, Next_Master_Ref_Mark = Current_Master_Ref_Mark + TimePreset
+  *           or
+  *           - 0x8001 and 0xFFFF, Next_Master_Ref_Mark = Current_Master_Ref_Mark - (0x10000 - TimePreset)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_SetGlobalTime(FDCAN_HandleTypeDef *hfdcan, uint32_t TimePreset)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_TIME_PRESET(TimePreset));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Check that the external clock synchronization is enabled */
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_EECS) != FDCAN_TTOCF_EECS)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+
+    /* Check that no global time preset is pending */
+    if ((hfdcan->ttcan->TTOST & FDCAN_TTOST_WGTD) == FDCAN_TTOST_WGTD)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING;
+
+      return HAL_ERROR;
+    }
+
+    /* Configure time preset */
+    MODIFY_REG(hfdcan->ttcan->TTGTP, FDCAN_TTGTP_TP, (TimePreset << FDCAN_TTGTP_TP_Pos));
+
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Schedule time preset to take effect by the next reference message */
+    SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_SGT);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Schedule TUR numerator update for the next reference message.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  NewTURNumerator new value of the TUR numerator.
+  *         This parameter must be a number between 0x10000 and 0x1FFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_SetClockSynchronization(FDCAN_HandleTypeDef *hfdcan, uint32_t NewTURNumerator)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_TUR_NUMERATOR(NewTURNumerator));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Check that the external clock synchronization is enabled */
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_EECS) != FDCAN_TTOCF_EECS)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+
+    /* Check that no external clock synchronization is pending */
+    if ((hfdcan->ttcan->TTOST & FDCAN_TTOST_WECS) == FDCAN_TTOST_WECS)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING;
+
+      return HAL_ERROR;
+    }
+
+    /* Configure new TUR numerator */
+    MODIFY_REG(hfdcan->ttcan->TURCF, FDCAN_TURCF_NCL, (NewTURNumerator - 0x10000U));
+
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Schedule TUR numerator update by the next reference message */
+    SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_ECS);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure stop watch source and polarity.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  Source stop watch source.
+  *         This parameter can be a value of @arg FDCAN_TT_stop_watch_source.
+  * @param  Polarity stop watch polarity.
+  *         This parameter can be a value of @arg FDCAN_TT_stop_watch_polarity.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigStopWatch(FDCAN_HandleTypeDef *hfdcan, uint32_t Source, uint32_t Polarity)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_STOP_WATCH_SOURCE(Source));
+  assert_param(IS_FDCAN_TT_STOP_WATCH_POLARITY(Polarity));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Select stop watch source and polarity */
+    MODIFY_REG(hfdcan->ttcan->TTOCN, (FDCAN_TTOCN_SWS | FDCAN_TTOCN_SWP), (Source | Polarity));
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure register time mark pulse generation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TimeMarkSource time mark source.
+  *         This parameter can be a value of @arg FDCAN_TT_time_mark_source.
+  * @param  TimeMarkValue time mark value (reference).
+  *         This parameter must be a number between 0 and 0xFFFF.
+  * @param  RepeatFactor repeat factor of the cycle for which the time mark is valid.
+  *         This parameter can be a value of @arg FDCAN_TT_Repeat_Factor.
+  * @param  StartCycle index of the first cycle in which the time mark becomes valid.
+  *         This parameter is ignored if RepeatFactor is set to FDCAN_TT_REPEAT_EVERY_CYCLE.
+  *         This parameter must be a number between 0 and RepeatFactor.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigRegisterTimeMark(FDCAN_HandleTypeDef *hfdcan,
+                                                      uint32_t TimeMarkSource, uint32_t TimeMarkValue,
+                                                      uint32_t RepeatFactor, uint32_t StartCycle)
+{
+  uint32_t Counter = 0U;
+  uint32_t CycleCode;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_REGISTER_TIME_MARK_SOURCE(TimeMarkSource));
+  assert_param(IS_FDCAN_MAX_VALUE(TimeMarkValue, 0xFFFFU));
+  assert_param(IS_FDCAN_TT_REPEAT_FACTOR(RepeatFactor));
+  if (RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE)
+  {
+    assert_param(IS_FDCAN_MAX_VALUE(StartCycle, (RepeatFactor - 1U)));
+  }
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Disable the time mark compare function */
+    CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMC);
+
+    if (TimeMarkSource != FDCAN_TT_REG_TIMEMARK_DIABLED)
+    {
+      /* Calculate cycle code */
+      if (RepeatFactor == FDCAN_TT_REPEAT_EVERY_CYCLE)
+      {
+        CycleCode = FDCAN_TT_REPEAT_EVERY_CYCLE;
+      }
+      else /* RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE */
+      {
+        CycleCode = RepeatFactor + StartCycle;
+      }
+
+      Counter = 0U;
+
+      /* Wait until the LCKM bit into TTTMK register is reset */
+      while ((hfdcan->ttcan->TTTMK & FDCAN_TTTMK_LCKM) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_VALUE)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Configure time mark value and cycle code */
+      hfdcan->ttcan->TTTMK = ((TimeMarkValue << FDCAN_TTTMK_TM_Pos) | (CycleCode << FDCAN_TTTMK_TICC_Pos));
+
+      Counter = 0U;
+
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_VALUE)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Update the register time mark compare source */
+      MODIFY_REG(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMC, TimeMarkSource);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable register time mark pulse generation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Enable Register Time Mark Interrupt output on fdcan1_rtp */
+    SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_RTIE);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable register time mark pulse generation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Disable Register Time Mark Interrupt output on fdcan1_rtp */
+    CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_RTIE);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable trigger time mark pulse generation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_VALUE)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Enable Trigger Time Mark Interrupt output on fdcan1_tmp */
+      SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TTIE);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable trigger time mark pulse generation.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_VALUE)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Disable Trigger Time Mark Interrupt output on fdcan1_rtp */
+      CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TTIE);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable gap control by input pin fdcan1_evt.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_VALUE)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Enable gap control by pin fdcan1_evt */
+      SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_GCS);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable gap control by input pin fdcan1_evt.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_VALUE)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Disable gap control by pin fdcan1_evt */
+      CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_GCS);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable gap control (finish only) by register time mark interrupt.
+  *         The next register time mark interrupt (TTIR.RTMI = "1") will finish
+  *         the Gap and start the reference message.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_VALUE)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Enable gap control by register time mark interrupt */
+      SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMG);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable gap control by register time mark interrupt.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_VALUE)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Disable gap control by register time mark interrupt */
+      CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMG);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Transmit next reference message with Next_is_Gap = "1".
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_SetNextIsGap(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Check that the node is configured for external event-synchronized TT operation */
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_GEN) != FDCAN_TTOCF_GEN)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_VALUE)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Set Next is Gap */
+      SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_NIG);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Finish a Gap by requesting start of reference message.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_SetEndOfGap(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Check that the node is configured for external event-synchronized TT operation */
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_GEN) != FDCAN_TTOCF_GEN)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+    {
+      /* Wait until the LCKC bit into TTOCN register is reset */
+      while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+      {
+        /* Check for the Timeout */
+        if (Counter > FDCAN_TIMEOUT_VALUE)
+        {
+          /* Update error code */
+          hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+          /* Change FDCAN state */
+          hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+          return HAL_ERROR;
+        }
+
+        /* Increment counter */
+        Counter++;
+      }
+
+      /* Set Finish Gap */
+      SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_FGP);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code.
+         Feature not supported for TT Level 0 */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure target phase used for external synchronization by event
+  *         trigger input pin fdcan1_evt.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TargetPhase defines target value of cycle time when a rising edge
+  *         of fdcan1_evt is expected.
+  *         This parameter must be a number between 0 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigExternalSyncPhase(FDCAN_HandleTypeDef *hfdcan, uint32_t TargetPhase)
+{
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_MAX_VALUE(TargetPhase, 0xFFFFU));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Check that no external schedule synchronization is pending */
+    if ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_ESCN) == FDCAN_TTOCN_ESCN)
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING;
+
+      return HAL_ERROR;
+    }
+
+    /* Configure cycle time target phase */
+    MODIFY_REG(hfdcan->ttcan->TTGTP, FDCAN_TTGTP_CTP, (TargetPhase << FDCAN_TTGTP_CTP_Pos));
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Synchronize the phase of the FDCAN schedule to an external schedule
+  *         using event trigger input pin fdcan1_evt.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Enable external synchronization */
+    SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_ESCN);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable external schedule synchronization.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t Counter = 0U;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Wait until the LCKC bit into TTOCN register is reset */
+    while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+    {
+      /* Check for the Timeout */
+      if (Counter > FDCAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+        /* Change FDCAN state */
+        hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+
+      /* Increment counter */
+      Counter++;
+    }
+
+    /* Disable external synchronization */
+    CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_ESCN);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get TT operation status.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TTOpStatus pointer to an FDCAN_TTOperationStatusTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_GetOperationStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_TTOperationStatusTypeDef *TTOpStatus)
+{
+  uint32_t TTStatusReg;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+  /* Read the TT operation status register */
+  TTStatusReg = READ_REG(hfdcan->ttcan->TTOST);
+
+  /* Fill the TT operation status structure */
+  TTOpStatus->ErrorLevel = (TTStatusReg & FDCAN_TTOST_EL);
+  TTOpStatus->MasterState = (TTStatusReg & FDCAN_TTOST_MS);
+  TTOpStatus->SyncState = (TTStatusReg & FDCAN_TTOST_SYS);
+  TTOpStatus->GTimeQuality = ((TTStatusReg & FDCAN_TTOST_QGTP) >> FDCAN_TTOST_QGTP_Pos);
+  TTOpStatus->ClockQuality = ((TTStatusReg & FDCAN_TTOST_QCS) >> FDCAN_TTOST_QCS_Pos);
+  TTOpStatus->RefTrigOffset = ((TTStatusReg & FDCAN_TTOST_RTO) >> FDCAN_TTOST_RTO_Pos);
+  TTOpStatus->GTimeDiscPending = ((TTStatusReg & FDCAN_TTOST_WGTD) >> FDCAN_TTOST_WGTD_Pos);
+  TTOpStatus->GapFinished = ((TTStatusReg & FDCAN_TTOST_GFI) >> FDCAN_TTOST_GFI_Pos);
+  TTOpStatus->MasterPriority = ((TTStatusReg & FDCAN_TTOST_TMP) >> FDCAN_TTOST_TMP_Pos);
+  TTOpStatus->GapStarted = ((TTStatusReg & FDCAN_TTOST_GSI) >> FDCAN_TTOST_GSI_Pos);
+  TTOpStatus->WaitForEvt = ((TTStatusReg & FDCAN_TTOST_WFE) >> FDCAN_TTOST_WFE_Pos);
+  TTOpStatus->AppWdgEvt = ((TTStatusReg & FDCAN_TTOST_AWE) >> FDCAN_TTOST_AWE_Pos);
+  TTOpStatus->ECSPending = ((TTStatusReg & FDCAN_TTOST_WECS) >> FDCAN_TTOST_WECS_Pos);
+  TTOpStatus->PhaseLock = ((TTStatusReg & FDCAN_TTOST_SPL) >> FDCAN_TTOST_SPL_Pos);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Exported_Functions_Group5 Interrupts management
+ *  @brief    Interrupts management
+ *
+@verbatim
+  ==============================================================================
+                       ##### Interrupts management #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) HAL_FDCAN_ConfigInterruptLines      : Assign interrupts to either Interrupt line 0 or 1
+      (+) HAL_FDCAN_TT_ConfigInterruptLines   : Assign TT interrupts to either Interrupt line 0 or 1
+      (+) HAL_FDCAN_ActivateNotification      : Enable interrupts
+      (+) HAL_FDCAN_DeactivateNotification    : Disable interrupts
+      (+) HAL_FDCAN_TT_ActivateNotification   : Enable TT interrupts
+      (+) HAL_FDCAN_TT_DeactivateNotification : Disable TT interrupts
+      (+) HAL_FDCAN_IRQHandler                : Handles FDCAN interrupt request
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Assign interrupts to either Interrupt line 0 or 1.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  ITList indicates which interrupts will be assigned to the selected interrupt line.
+  *         This parameter can be any combination of @arg FDCAN_Interrupts.
+  * @param  InterruptLine Interrupt line.
+  *         This parameter can be a value of @arg FDCAN_Interrupt_Line.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine)
+{
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_IT(ITList));
+  assert_param(IS_FDCAN_IT_LINE(InterruptLine));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Assign list of interrupts to the selected line */
+    if (InterruptLine == FDCAN_INTERRUPT_LINE0)
+    {
+      CLEAR_BIT(hfdcan->Instance->ILS, ITList);
+    }
+    else /* InterruptLine == FDCAN_INTERRUPT_LINE1 */
+    {
+      SET_BIT(hfdcan->Instance->ILS, ITList);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Assign TT interrupts to either Interrupt line 0 or 1.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TTITList indicates which interrupts will be assigned to the selected interrupt line.
+  *         This parameter can be any combination of @arg FDCAN_TTInterrupts.
+  * @param  InterruptLine Interrupt line.
+  *         This parameter can be a value of @arg FDCAN_Interrupt_Line.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t TTITList, uint32_t InterruptLine)
+{
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_IT(TTITList));
+  assert_param(IS_FDCAN_IT_LINE(InterruptLine));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Assign list of interrupts to the selected line */
+    if (InterruptLine == FDCAN_INTERRUPT_LINE0)
+    {
+      CLEAR_BIT(hfdcan->ttcan->TTILS, TTITList);
+    }
+    else /* InterruptLine == FDCAN_INTERRUPT_LINE1 */
+    {
+      SET_BIT(hfdcan->ttcan->TTILS, TTITList);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable interrupts.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  ActiveITs indicates which interrupts will be enabled.
+  *         This parameter can be any combination of @arg FDCAN_Interrupts.
+  * @param  BufferIndexes Tx Buffer Indexes.
+  *         This parameter can be any combination of @arg FDCAN_Tx_location.
+  *         This parameter is ignored if ActiveITs does not include one of the following:
+  *           - FDCAN_IT_TX_COMPLETE
+  *           - FDCAN_IT_TX_ABORT_COMPLETE
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes)
+{
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_IT(ActiveITs));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Enable Interrupt lines */
+    if ((ActiveITs & hfdcan->Instance->ILS) == 0U)
+    {
+      /* Enable Interrupt line 0 */
+      SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
+    }
+    else if ((ActiveITs & hfdcan->Instance->ILS) == ActiveITs)
+    {
+      /* Enable Interrupt line 1 */
+      SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
+    }
+    else
+    {
+      /* Enable Interrupt lines 0 and 1 */
+      hfdcan->Instance->ILE = (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1);
+    }
+
+    if ((ActiveITs & FDCAN_IT_TX_COMPLETE) != 0U)
+    {
+      /* Enable Tx Buffer Transmission Interrupt to set TC flag in IR register,
+         but interrupt will only occure if TC is enabled in IE register */
+      SET_BIT(hfdcan->Instance->TXBTIE, BufferIndexes);
+    }
+
+    if ((ActiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != 0U)
+    {
+      /* Enable Tx Buffer Cancellation Finished Interrupt to set TCF flag in IR register,
+         but interrupt will only occure if TCF is enabled in IE register */
+      SET_BIT(hfdcan->Instance->TXBCIE, BufferIndexes);
+    }
+
+    /* Enable the selected interrupts */
+    __HAL_FDCAN_ENABLE_IT(hfdcan, ActiveITs);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable interrupts.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  InactiveITs indicates which interrupts will be disabled.
+  *         This parameter can be any combination of @arg FDCAN_Interrupts.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs)
+{
+  uint32_t ITLineSelection;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_IT(InactiveITs));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Disable the selected interrupts */
+    __HAL_FDCAN_DISABLE_IT(hfdcan, InactiveITs);
+
+    if ((InactiveITs & FDCAN_IT_TX_COMPLETE) != 0U)
+    {
+      /* Disable Tx Buffer Transmission Interrupts */
+      CLEAR_REG(hfdcan->Instance->TXBTIE);
+    }
+
+    if ((InactiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != 0U)
+    {
+      /* Disable Tx Buffer Cancellation Finished Interrupt */
+      CLEAR_REG(hfdcan->Instance->TXBCIE);
+    }
+
+    ITLineSelection = hfdcan->Instance->ILS;
+
+    if ((hfdcan->Instance->IE | ITLineSelection) == ITLineSelection)
+    {
+      /* Disable Interrupt line 0 */
+      CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
+    }
+
+    if ((hfdcan->Instance->IE & ITLineSelection) == 0U)
+    {
+      /* Disable Interrupt line 1 */
+      CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable TT interrupts.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  ActiveTTITs indicates which TT interrupts will be enabled.
+  *         This parameter can be any combination of @arg FDCAN_TTInterrupts.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveTTITs)
+{
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_IT(ActiveTTITs));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Enable Interrupt lines */
+    if ((ActiveTTITs & hfdcan->ttcan->TTILS) == 0U)
+    {
+      /* Enable Interrupt line 0 */
+      SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
+    }
+    else if ((ActiveTTITs & hfdcan->ttcan->TTILS) == ActiveTTITs)
+    {
+      /* Enable Interrupt line 1 */
+      SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
+    }
+    else
+    {
+      /* Enable Interrupt lines 0 and 1 */
+      hfdcan->Instance->ILE = (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1);
+    }
+
+    /* Enable the selected TT interrupts */
+    __HAL_FDCAN_TT_ENABLE_IT(hfdcan, ActiveTTITs);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable TT interrupts.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  InactiveTTITs indicates which TT interrupts will be disabled.
+  *         This parameter can be any combination of @arg FDCAN_TTInterrupts.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_TT_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveTTITs)
+{
+  uint32_t ITLineSelection;
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+  assert_param(IS_FDCAN_TT_IT(InactiveTTITs));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+  {
+    /* Disable the selected TT interrupts */
+    __HAL_FDCAN_TT_DISABLE_IT(hfdcan, InactiveTTITs);
+
+    ITLineSelection = hfdcan->ttcan->TTILS;
+
+    if ((hfdcan->ttcan->TTIE | ITLineSelection) == ITLineSelection)
+    {
+      /* Disable Interrupt line 0 */
+      CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
+    }
+
+    if ((hfdcan->ttcan->TTIE & ITLineSelection) == 0U)
+    {
+      /* Disable Interrupt line 1 */
+      CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Handles FDCAN interrupt request.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t ClkCalibrationITs;
+  uint32_t TxEventFifoITs;
+  uint32_t RxFifo0ITs;
+  uint32_t RxFifo1ITs;
+  uint32_t Errors;
+  uint32_t ErrorStatusITs;
+  uint32_t TransmittedBuffers;
+  uint32_t AbortedBuffers;
+  uint32_t TTSchedSyncITs;
+  uint32_t TTTimeMarkITs;
+  uint32_t TTGlobTimeITs;
+  uint32_t TTDistErrors;
+  uint32_t TTFatalErrors;
+  uint32_t SWTime;
+  uint32_t SWCycleCount;
+
+  ClkCalibrationITs = (FDCAN_CCU->IR << 30);
+  ClkCalibrationITs &= (FDCAN_CCU->IE << 30);
+  TxEventFifoITs = hfdcan->Instance->IR & FDCAN_TX_EVENT_FIFO_MASK;
+  TxEventFifoITs &= hfdcan->Instance->IE;
+  RxFifo0ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO0_MASK;
+  RxFifo0ITs &= hfdcan->Instance->IE;
+  RxFifo1ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO1_MASK;
+  RxFifo1ITs &= hfdcan->Instance->IE;
+  Errors = hfdcan->Instance->IR & FDCAN_ERROR_MASK;
+  Errors &= hfdcan->Instance->IE;
+  ErrorStatusITs = hfdcan->Instance->IR & FDCAN_ERROR_STATUS_MASK;
+  ErrorStatusITs &= hfdcan->Instance->IE;
+
+  /* High Priority Message interrupt management *******************************/
+  if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RX_HIGH_PRIORITY_MSG) != 0U)
+  {
+    if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG) != 0U)
+    {
+      /* Clear the High Priority Message flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->HighPriorityMessageCallback(hfdcan);
+#else
+      /* High Priority Message Callback */
+      HAL_FDCAN_HighPriorityMessageCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Transmission Abort interrupt management **********************************/
+  if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_ABORT_COMPLETE) != 0U)
+  {
+    if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE) != 0U)
+    {
+      /* List of aborted monitored buffers */
+      AbortedBuffers = hfdcan->Instance->TXBCF;
+      AbortedBuffers &= hfdcan->Instance->TXBCIE;
+
+      /* Clear the Transmission Cancellation flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->TxBufferAbortCallback(hfdcan, AbortedBuffers);
+#else
+      /* Transmission Cancellation Callback */
+      HAL_FDCAN_TxBufferAbortCallback(hfdcan, AbortedBuffers);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Clock calibration unit interrupts management *****************************/
+  if (ClkCalibrationITs != 0U)
+  {
+    /* Clear the Clock Calibration flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, ClkCalibrationITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->ClockCalibrationCallback(hfdcan, ClkCalibrationITs);
+#else
+    /* Clock Calibration Callback */
+    HAL_FDCAN_ClockCalibrationCallback(hfdcan, ClkCalibrationITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+
+  /* Tx event FIFO interrupts management **************************************/
+  if (TxEventFifoITs != 0U)
+  {
+    /* Clear the Tx Event FIFO flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, TxEventFifoITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->TxEventFifoCallback(hfdcan, TxEventFifoITs);
+#else
+    /* Tx Event FIFO Callback */
+    HAL_FDCAN_TxEventFifoCallback(hfdcan, TxEventFifoITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+
+  /* Rx FIFO 0 interrupts management ******************************************/
+  if (RxFifo0ITs != 0U)
+  {
+    /* Clear the Rx FIFO 0 flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo0ITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->RxFifo0Callback(hfdcan, RxFifo0ITs);
+#else
+    /* Rx FIFO 0 Callback */
+    HAL_FDCAN_RxFifo0Callback(hfdcan, RxFifo0ITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+
+  /* Rx FIFO 1 interrupts management ******************************************/
+  if (RxFifo1ITs != 0U)
+  {
+    /* Clear the Rx FIFO 1 flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo1ITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->RxFifo1Callback(hfdcan, RxFifo1ITs);
+#else
+    /* Rx FIFO 1 Callback */
+    HAL_FDCAN_RxFifo1Callback(hfdcan, RxFifo1ITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+
+  /* Tx FIFO empty interrupt management ***************************************/
+  if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_FIFO_EMPTY) != 0U)
+  {
+    if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY) != 0U)
+    {
+      /* Clear the Tx FIFO empty flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->TxFifoEmptyCallback(hfdcan);
+#else
+      /* Tx FIFO empty Callback */
+      HAL_FDCAN_TxFifoEmptyCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Transmission Complete interrupt management *******************************/
+  if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_COMPLETE) != 0U)
+  {
+    if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_COMPLETE) != 0U)
+    {
+      /* List of transmitted monitored buffers */
+      TransmittedBuffers = hfdcan->Instance->TXBTO;
+      TransmittedBuffers &= hfdcan->Instance->TXBTIE;
+
+      /* Clear the Transmission Complete flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_COMPLETE);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->TxBufferCompleteCallback(hfdcan, TransmittedBuffers);
+#else
+      /* Transmission Complete Callback */
+      HAL_FDCAN_TxBufferCompleteCallback(hfdcan, TransmittedBuffers);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Rx Buffer New Message interrupt management *******************************/
+  if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RX_BUFFER_NEW_MESSAGE) != 0U)
+  {
+    if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE) != 0U)
+    {
+      /* Clear the Rx Buffer New Message flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->RxBufferNewMessageCallback(hfdcan);
+#else
+      /* Rx Buffer New Message Callback */
+      HAL_FDCAN_RxBufferNewMessageCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Timestamp Wraparound interrupt management ********************************/
+  if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TIMESTAMP_WRAPAROUND) != 0U)
+  {
+    if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND) != 0U)
+    {
+      /* Clear the Timestamp Wraparound flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->TimestampWraparoundCallback(hfdcan);
+#else
+      /* Timestamp Wraparound Callback */
+      HAL_FDCAN_TimestampWraparoundCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Timeout Occurred interrupt management ************************************/
+  if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TIMEOUT_OCCURRED) != 0U)
+  {
+    if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED) != 0U)
+    {
+      /* Clear the Timeout Occurred flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->TimeoutOccurredCallback(hfdcan);
+#else
+      /* Timeout Occurred Callback */
+      HAL_FDCAN_TimeoutOccurredCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Message RAM access failure interrupt management **************************/
+  if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RAM_ACCESS_FAILURE) != 0U)
+  {
+    if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE) != 0U)
+    {
+      /* Clear the Message RAM access failure flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE);
+
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_RAM_ACCESS;
+    }
+  }
+
+  /* Error Status interrupts management ***************************************/
+  if (ErrorStatusITs != 0U)
+  {
+    /* Clear the Error flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, ErrorStatusITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->ErrorStatusCallback(hfdcan, ErrorStatusITs);
+#else
+    /* Error Status Callback */
+    HAL_FDCAN_ErrorStatusCallback(hfdcan, ErrorStatusITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+
+  /* Error interrupts management **********************************************/
+  if (Errors != 0U)
+  {
+    /* Clear the Error flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, Errors);
+
+    /* Update error code */
+    hfdcan->ErrorCode |= Errors;
+  }
+
+  if (hfdcan->Instance == FDCAN1)
+  {
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != 0U)
+    {
+      TTSchedSyncITs = hfdcan->ttcan->TTIR & FDCAN_TT_SCHEDULE_SYNC_MASK;
+      TTSchedSyncITs &= hfdcan->ttcan->TTIE;
+      TTTimeMarkITs = hfdcan->ttcan->TTIR & FDCAN_TT_TIME_MARK_MASK;
+      TTTimeMarkITs &= hfdcan->ttcan->TTIE;
+      TTGlobTimeITs = hfdcan->ttcan->TTIR & FDCAN_TT_GLOBAL_TIME_MASK;
+      TTGlobTimeITs &= hfdcan->ttcan->TTIE;
+      TTDistErrors = hfdcan->ttcan->TTIR & FDCAN_TT_DISTURBING_ERROR_MASK;
+      TTDistErrors &= hfdcan->ttcan->TTIE;
+      TTFatalErrors = hfdcan->ttcan->TTIR & FDCAN_TT_FATAL_ERROR_MASK;
+      TTFatalErrors &= hfdcan->ttcan->TTIE;
+
+      /* TT Schedule Synchronization interrupts management **********************/
+      if (TTSchedSyncITs != 0U)
+      {
+        /* Clear the TT Schedule Synchronization flags */
+        __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTSchedSyncITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+        /* Call registered callback*/
+        hfdcan->TT_ScheduleSyncCallback(hfdcan, TTSchedSyncITs);
+#else
+        /* TT Schedule Synchronization Callback */
+        HAL_FDCAN_TT_ScheduleSyncCallback(hfdcan, TTSchedSyncITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+      }
+
+      /* TT Time Mark interrupts management *************************************/
+      if (TTTimeMarkITs != 0U)
+      {
+        /* Clear the TT Time Mark flags */
+        __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTTimeMarkITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+        /* Call registered callback*/
+        hfdcan->TT_TimeMarkCallback(hfdcan, TTTimeMarkITs);
+#else
+        /* TT Time Mark Callback */
+        HAL_FDCAN_TT_TimeMarkCallback(hfdcan, TTTimeMarkITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+      }
+
+      /* TT Stop Watch interrupt management *************************************/
+      if (__HAL_FDCAN_TT_GET_IT_SOURCE(hfdcan, FDCAN_TT_IT_STOP_WATCH) != 0U)
+      {
+        if (__HAL_FDCAN_TT_GET_FLAG(hfdcan, FDCAN_TT_FLAG_STOP_WATCH) != 0U)
+        {
+          /* Retrieve Stop watch Time and Cycle count */
+          SWTime = ((hfdcan->ttcan->TTCPT & FDCAN_TTCPT_SWV) >> FDCAN_TTCPT_SWV_Pos);
+          SWCycleCount = ((hfdcan->ttcan->TTCPT & FDCAN_TTCPT_CCV) >> FDCAN_TTCPT_CCV_Pos);
+
+          /* Clear the TT Stop Watch flag */
+          __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, FDCAN_TT_FLAG_STOP_WATCH);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+          /* Call registered callback*/
+          hfdcan->TT_StopWatchCallback(hfdcan, SWTime, SWCycleCount);
+#else
+          /* TT Stop Watch Callback */
+          HAL_FDCAN_TT_StopWatchCallback(hfdcan, SWTime, SWCycleCount);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+        }
+      }
+
+      /* TT Global Time interrupts management ***********************************/
+      if (TTGlobTimeITs != 0U)
+      {
+        /* Clear the TT Global Time flags */
+        __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTGlobTimeITs);
+
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+        /* Call registered callback*/
+        hfdcan->TT_GlobalTimeCallback(hfdcan, TTGlobTimeITs);
+#else
+        /* TT Global Time Callback */
+        HAL_FDCAN_TT_GlobalTimeCallback(hfdcan, TTGlobTimeITs);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+      }
+
+      /* TT Disturbing Error interrupts management ******************************/
+      if (TTDistErrors != 0U)
+      {
+        /* Clear the TT Disturbing Error flags */
+        __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTDistErrors);
+
+        /* Update error code */
+        hfdcan->ErrorCode |= TTDistErrors;
+      }
+
+      /* TT Fatal Error interrupts management ***********************************/
+      if (TTFatalErrors != 0U)
+      {
+        /* Clear the TT Fatal Error flags */
+        __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTFatalErrors);
+
+        /* Update error code */
+        hfdcan->ErrorCode |= TTFatalErrors;
+      }
+    }
+  }
+
+  if (hfdcan->ErrorCode != HAL_FDCAN_ERROR_NONE)
+  {
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->ErrorCallback(hfdcan);
+#else
+    /* Error Callback */
+    HAL_FDCAN_ErrorCallback(hfdcan);
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Exported_Functions_Group6 Callback functions
+ *  @brief   FDCAN Callback functions
+ *
+@verbatim
+  ==============================================================================
+                          ##### Callback functions #####
+  ==============================================================================
+    [..]
+    This subsection provides the following callback functions:
+      (+) HAL_FDCAN_ClockCalibrationCallback
+      (+) HAL_FDCAN_TxEventFifoCallback
+      (+) HAL_FDCAN_RxFifo0Callback
+      (+) HAL_FDCAN_RxFifo1Callback
+      (+) HAL_FDCAN_TxFifoEmptyCallback
+      (+) HAL_FDCAN_TxBufferCompleteCallback
+      (+) HAL_FDCAN_TxBufferAbortCallback
+      (+) HAL_FDCAN_RxBufferNewMessageCallback
+      (+) HAL_FDCAN_HighPriorityMessageCallback
+      (+) HAL_FDCAN_TimestampWraparoundCallback
+      (+) HAL_FDCAN_TimeoutOccurredCallback
+      (+) HAL_FDCAN_ErrorCallback
+      (+) HAL_FDCAN_ErrorStatusCallback
+      (+) HAL_FDCAN_TT_ScheduleSyncCallback
+      (+) HAL_FDCAN_TT_TimeMarkCallback
+      (+) HAL_FDCAN_TT_StopWatchCallback
+      (+) HAL_FDCAN_TT_GlobalTimeCallback
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Clock Calibration callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  ClkCalibrationITs indicates which Clock Calibration interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_Clock_Calibration_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_ClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(ClkCalibrationITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_ClockCalibrationCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Tx Event callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TxEventFifoITs indicates which Tx Event FIFO interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_Tx_Event_Fifo_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(TxEventFifoITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TxEventFifoCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Rx FIFO 0 callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  RxFifo0ITs indicates which Rx FIFO 0 interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_Rx_Fifo0_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(RxFifo0ITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_RxFifo0Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Rx FIFO 1 callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  RxFifo1ITs indicates which Rx FIFO 1 interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_Rx_Fifo1_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(RxFifo1ITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_RxFifo1Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Tx FIFO Empty callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TxFifoEmptyCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Transmission Complete callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  BufferIndexes Indexes of the transmitted buffers.
+  *         This parameter can be any combination of @arg FDCAN_Tx_location.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(BufferIndexes);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TxBufferCompleteCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Transmission Cancellation callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  BufferIndexes Indexes of the aborted buffers.
+  *         This parameter can be any combination of @arg FDCAN_Tx_location.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(BufferIndexes);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TxBufferAbortCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Rx Buffer New Message callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_RxBufferNewMessageCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_RxBufferNewMessageCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Timestamp Wraparound callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TimestampWraparoundCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Timeout Occurred callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TimeoutOccurredCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  High Priority Message callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_HighPriorityMessageCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Error callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Error status callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  ErrorStatusITs indicates which Error Status interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_Error_Status_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(ErrorStatusITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_ErrorStatusCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  TT Schedule Synchronization callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TTSchedSyncITs indicates which TT Schedule Synchronization interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_TTScheduleSynchronization_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TT_ScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(TTSchedSyncITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TT_ScheduleSyncCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  TT Time Mark callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TTTimeMarkITs indicates which TT Schedule Synchronization interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_TTTimeMark_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TT_TimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(TTTimeMarkITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TT_TimeMarkCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  TT Stop Watch callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  SWTime Time Value captured at the Stop Watch Trigger pin (fdcan1_swt) falling/rising
+  *         edge (as configured via HAL_FDCAN_TTConfigStopWatch).
+  *         This parameter is a number between 0 and 0xFFFF.
+  * @param  SWCycleCount Cycle count value captured together with SWTime.
+  *         This parameter is a number between 0 and 0x3F.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TT_StopWatchCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(SWTime);
+  UNUSED(SWCycleCount);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TT_StopWatchCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  TT Global Time callback.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  TTGlobTimeITs indicates which TT Global Time interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_TTGlobalTime_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TT_GlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hfdcan);
+  UNUSED(TTGlobTimeITs);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TT_GlobalTimeCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FDCAN_Exported_Functions_Group7 Peripheral State functions
+ *  @brief   FDCAN Peripheral State functions
+ *
+@verbatim
+  ==============================================================================
+                      ##### Peripheral State functions #####
+  ==============================================================================
+    [..]
+    This subsection provides functions allowing to :
+      (+) HAL_FDCAN_GetState()  : Return the FDCAN state.
+      (+) HAL_FDCAN_GetError()  : Return the FDCAN error code if any.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Return the FDCAN state
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL state
+  */
+HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Return FDCAN state */
+  return hfdcan->State;
+}
+
+/**
+  * @brief  Return the FDCAN error code
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval FDCAN Error Code
+  */
+uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan)
+{
+  /* Return FDCAN error code */
+  return hfdcan->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup FDCAN_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Calculate each RAM block start address and size
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+ */
+static HAL_StatusTypeDef FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan)
+{
+  uint32_t RAMcounter;
+  uint32_t StartAddress;
+
+  StartAddress = hfdcan->Init.MessageRAMOffset;
+
+  /* Standard filter list start address */
+  MODIFY_REG(hfdcan->Instance->SIDFC, FDCAN_SIDFC_FLSSA, (StartAddress << FDCAN_SIDFC_FLSSA_Pos));
+
+  /* Standard filter elements number */
+  MODIFY_REG(hfdcan->Instance->SIDFC, FDCAN_SIDFC_LSS, (hfdcan->Init.StdFiltersNbr << FDCAN_SIDFC_LSS_Pos));
+
+  /* Extended filter list start address */
+  StartAddress += hfdcan->Init.StdFiltersNbr;
+  MODIFY_REG(hfdcan->Instance->XIDFC, FDCAN_XIDFC_FLESA, (StartAddress << FDCAN_XIDFC_FLESA_Pos));
+
+  /* Extended filter elements number */
+  MODIFY_REG(hfdcan->Instance->XIDFC, FDCAN_XIDFC_LSE, (hfdcan->Init.ExtFiltersNbr << FDCAN_XIDFC_LSE_Pos));
+
+  /* Rx FIFO 0 start address */
+  StartAddress += (hfdcan->Init.ExtFiltersNbr * 2U);
+  MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0SA, (StartAddress << FDCAN_RXF0C_F0SA_Pos));
+
+  /* Rx FIFO 0 elements number */
+  MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0S, (hfdcan->Init.RxFifo0ElmtsNbr << FDCAN_RXF0C_F0S_Pos));
+
+  /* Rx FIFO 1 start address */
+  StartAddress += (hfdcan->Init.RxFifo0ElmtsNbr * hfdcan->Init.RxFifo0ElmtSize);
+  MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1SA, (StartAddress << FDCAN_RXF1C_F1SA_Pos));
+
+  /* Rx FIFO 1 elements number */
+  MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1S, (hfdcan->Init.RxFifo1ElmtsNbr << FDCAN_RXF1C_F1S_Pos));
+
+  /* Rx buffer list start address */
+  StartAddress += (hfdcan->Init.RxFifo1ElmtsNbr * hfdcan->Init.RxFifo1ElmtSize);
+  MODIFY_REG(hfdcan->Instance->RXBC, FDCAN_RXBC_RBSA, (StartAddress << FDCAN_RXBC_RBSA_Pos));
+
+  /* Tx event FIFO start address */
+  StartAddress += (hfdcan->Init.RxBuffersNbr * hfdcan->Init.RxBufferSize);
+  MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFSA, (StartAddress << FDCAN_TXEFC_EFSA_Pos));
+
+  /* Tx event FIFO elements number */
+  MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFS, (hfdcan->Init.TxEventsNbr << FDCAN_TXEFC_EFS_Pos));
+
+  /* Tx buffer list start address */
+  StartAddress += (hfdcan->Init.TxEventsNbr * 2U);
+  MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_TBSA, (StartAddress << FDCAN_TXBC_TBSA_Pos));
+
+  /* Dedicated Tx buffers number */
+  MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_NDTB, (hfdcan->Init.TxBuffersNbr << FDCAN_TXBC_NDTB_Pos));
+
+  /* Tx FIFO/queue elements number */
+  MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_TFQS, (hfdcan->Init.TxFifoQueueElmtsNbr << FDCAN_TXBC_TFQS_Pos));
+
+  hfdcan->msgRam.StandardFilterSA = SRAMCAN_BASE + (hfdcan->Init.MessageRAMOffset * 4U);
+  hfdcan->msgRam.ExtendedFilterSA = hfdcan->msgRam.StandardFilterSA + (hfdcan->Init.StdFiltersNbr * 4U);
+  hfdcan->msgRam.RxFIFO0SA = hfdcan->msgRam.ExtendedFilterSA + (hfdcan->Init.ExtFiltersNbr * 2U * 4U);
+  hfdcan->msgRam.RxFIFO1SA = hfdcan->msgRam.RxFIFO0SA + (hfdcan->Init.RxFifo0ElmtsNbr * hfdcan->Init.RxFifo0ElmtSize * 4U);
+  hfdcan->msgRam.RxBufferSA = hfdcan->msgRam.RxFIFO1SA + (hfdcan->Init.RxFifo1ElmtsNbr * hfdcan->Init.RxFifo1ElmtSize * 4U);
+  hfdcan->msgRam.TxEventFIFOSA = hfdcan->msgRam.RxBufferSA + (hfdcan->Init.RxBuffersNbr * hfdcan->Init.RxBufferSize * 4U);
+  hfdcan->msgRam.TxBufferSA = hfdcan->msgRam.TxEventFIFOSA + (hfdcan->Init.TxEventsNbr * 2U * 4U);
+  hfdcan->msgRam.TxFIFOQSA = hfdcan->msgRam.TxBufferSA + (hfdcan->Init.TxBuffersNbr * hfdcan->Init.TxElmtSize * 4U);
+
+  hfdcan->msgRam.EndAddress = hfdcan->msgRam.TxFIFOQSA + (hfdcan->Init.TxFifoQueueElmtsNbr * hfdcan->Init.TxElmtSize * 4U);
+
+  if (hfdcan->msgRam.EndAddress > FDCAN_MESSAGE_RAM_END_ADDRESS) /* Last address of the Message RAM */
+  {
+    /* Update error code.
+       Message RAM overflow */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+    /* Change FDCAN state */
+    hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Flush the allocated Message RAM area */
+    for (RAMcounter = hfdcan->msgRam.StandardFilterSA; RAMcounter < hfdcan->msgRam.EndAddress; RAMcounter += 4U)
+    {
+      *(uint32_t *)(RAMcounter) = 0x00000000;
+    }
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Copy Tx message to the message RAM.
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @param  pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure.
+  * @param  pTxData pointer to a buffer containing the payload of the Tx frame.
+  * @param  BufferIndex index of the buffer to be configured.
+  * @retval HAL status
+ */
+static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex)
+{
+  uint32_t TxElementW1;
+  uint32_t TxElementW2;
+  uint32_t *TxAddress;
+  uint32_t ByteCounter;
+
+  /* Build first word of Tx header element */
+  if (pTxHeader->IdType == FDCAN_STANDARD_ID)
+  {
+    TxElementW1 = (pTxHeader->ErrorStateIndicator |
+                   FDCAN_STANDARD_ID |
+                   pTxHeader->TxFrameType |
+                   (pTxHeader->Identifier << 18));
+  }
+  else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
+  {
+    TxElementW1 = (pTxHeader->ErrorStateIndicator |
+                   FDCAN_EXTENDED_ID |
+                   pTxHeader->TxFrameType |
+                   pTxHeader->Identifier);
+  }
+
+  /* Build second word of Tx header element */
+  TxElementW2 = ((pTxHeader->MessageMarker << 24) |
+                 pTxHeader->TxEventFifoControl |
+                 pTxHeader->FDFormat |
+                 pTxHeader->BitRateSwitch |
+                 pTxHeader->DataLength);
+
+  /* Calculate Tx element address */
+  TxAddress = (uint32_t *)(hfdcan->msgRam.TxBufferSA + (BufferIndex * hfdcan->Init.TxElmtSize * 4U));
+
+  /* Write Tx element header to the message RAM */
+  *TxAddress = TxElementW1;
+  TxAddress++;
+  *TxAddress = TxElementW2;
+  TxAddress++;
+
+  /* Write Tx payload to the message RAM */
+  for (ByteCounter = 0; ByteCounter < DLCtoBytes[pTxHeader->DataLength >> 16]; ByteCounter += 4U)
+  {
+    *TxAddress = (((uint32_t)pTxData[ByteCounter + 3U] << 24) |
+                  ((uint32_t)pTxData[ByteCounter + 2U] << 16) |
+                  ((uint32_t)pTxData[ByteCounter + 1U] << 8) |
+                  (uint32_t)pTxData[ByteCounter]);
+    TxAddress++;
+  }
+}
+
+/**
+  * @}
+  */
+#endif /* HAL_FDCAN_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c
new file mode 100644
index 00000000..3a6b651f
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c
@@ -0,0 +1,1099 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_flash.c
+  * @author  MCD Application Team
+  * @brief   FLASH HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the internal FLASH memory:
+  *           + Program operations functions
+  *           + Memory Control functions
+  *           + Peripheral Errors functions
+  *
+ @verbatim
+  ==============================================================================
+                        ##### FLASH peripheral features #####
+  ==============================================================================
+
+  [..] The Flash memory interface manages CPU AXI I-Code and D-Code accesses
+       to the Flash memory. It implements the erase and program Flash memory operations
+       and the read and write protection mechanisms.
+
+  [..] The FLASH main features are:
+      (+) Flash memory read operations
+      (+) Flash memory program/erase operations
+      (+) Read / write protections
+      (+) Option bytes programming
+      (+) Error code correction (ECC) : Data in flash are 266-bits word
+          (10 bits added per flash word)
+
+                        ##### How to use this driver #####
+ ==============================================================================
+    [..]
+      This driver provides functions and macros to configure and program the FLASH
+      memory of all STM32H7xx devices.
+
+      (#) FLASH Memory IO Programming functions:
+           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
+                HAL_FLASH_Lock() functions
+           (++) Program functions: 256-bit word only
+           (++) There Two modes of programming :
+            (+++) Polling mode using HAL_FLASH_Program() function
+            (+++) Interrupt mode using HAL_FLASH_Program_IT() function
+
+      (#) Interrupts and flags management functions :
+           (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
+           (++) Callback functions are called when the flash operations are finished :
+                HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise
+                HAL_FLASH_OperationErrorCallback()
+           (++) Get error flag status by calling HAL_FLASH_GetError()
+
+      (#) Option bytes management functions :
+           (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and
+                HAL_FLASH_OB_Lock() functions
+           (++) Launch the reload of the option bytes using HAL_FLASH_OB_Launch() function.
+                In this case, a reset is generated
+    [..]
+      In addition to these functions, this driver includes a set of macros allowing
+      to handle the following operations:
+       (+) Set the latency
+       (+) Enable/Disable the FLASH interrupts
+       (+) Monitor the FLASH flags status
+     [..]
+    (@) For any Flash memory program operation (erase or program), the CPU clock frequency
+        (HCLK) must be at least 1MHz.
+    (@) The contents of the Flash memory are not guaranteed if a device reset occurs during
+        a Flash memory operation.
+    (@) The application can simultaneously request a read and a write operation through each AXI
+        interface.
+        As the Flash memory is divided into two independent banks, the embedded Flash
+        memory interface can drive different operations at the same time on each bank. For
+        example a read, write or erase operation can be executed on bank 1 while another read,
+        write or erase operation is executed on bank 2.
+
+ @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup FLASH FLASH
+  * @brief FLASH HAL module driver
+  * @{
+  */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup FLASH_Private_Constants
+  * @{
+  */
+#define FLASH_TIMEOUT_VALUE              50000U /* 50 s */
+
+/**
+  * @}
+  */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+FLASH_ProcessTypeDef pFlash;
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup FLASH_Exported_Functions FLASH Exported functions
+  * @{
+  */
+
+/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
+ *  @brief   Programming operation functions
+ *
+@verbatim
+ ===============================================================================
+                  ##### Programming operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the FLASH
+    program operations.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Program flash word at a specified address
+  * @param  TypeProgram Indicate the way to program at a specified address.
+  *         This parameter can be a value of @ref FLASH_Type_Program
+  * @param  FlashAddress specifies the address to be programmed.
+  * @param  DataAddress specifies the address of data to be programmed
+  *
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress)
+{
+  HAL_StatusTypeDef status;
+  __IO uint32_t *dest_addr = (__IO uint32_t *)FlashAddress;
+  __IO uint32_t *src_addr = (__IO uint32_t*)DataAddress;
+  uint32_t bank;
+  uint8_t row_index = FLASH_NB_32BITWORD_IN_FLASHWORD;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+  assert_param(IS_FLASH_PROGRAM_ADDRESS(FlashAddress));
+
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+#if defined (FLASH_OPTCR_PG_OTP)
+  if((IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress)) || (IS_FLASH_PROGRAM_ADDRESS_OTP(FlashAddress)))
+#else
+  if(IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress))
+#endif /* FLASH_OPTCR_PG_OTP */
+  {
+    bank = FLASH_BANK_1;
+  }
+  else
+  {
+    bank = FLASH_BANK_2;
+  }
+
+  /* Reset error code */
+  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, bank);
+
+  if(status == HAL_OK)
+  {
+    if(bank == FLASH_BANK_1)
+    {
+#if defined (FLASH_OPTCR_PG_OTP)
+      if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD)
+      {
+        /* Set OTP_PG bit */
+        SET_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP);
+      }
+      else
+#endif /* FLASH_OPTCR_PG_OTP */
+      {
+        /* Set PG bit */
+        SET_BIT(FLASH->CR1, FLASH_CR_PG);
+      }
+    }
+    else
+    {
+      /* Set PG bit */
+      SET_BIT(FLASH->CR2, FLASH_CR_PG);
+    }
+
+    __ISB();
+    __DSB();
+
+#if defined (FLASH_OPTCR_PG_OTP)
+    if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD)
+    {
+      /* Program an OTP word (16 bits) */
+      *(__IO uint16_t *)FlashAddress = *(__IO uint16_t*)DataAddress;
+    }
+    else
+#endif /* FLASH_OPTCR_PG_OTP */
+    {
+      /* Program the flash word */
+      do
+      {
+        *dest_addr = *src_addr;
+        dest_addr++;
+        src_addr++;
+        row_index--;
+     } while (row_index != 0U);
+    }
+
+    __ISB();
+    __DSB();
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, bank);
+
+#if defined (FLASH_OPTCR_PG_OTP)
+    if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD)
+    {
+      /* If the program operation is completed, disable the OTP_PG */
+      CLEAR_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP);
+    }
+    else
+#endif /* FLASH_OPTCR_PG_OTP */
+    {
+      if(bank == FLASH_BANK_1)
+      {
+        /* If the program operation is completed, disable the PG */
+        CLEAR_BIT(FLASH->CR1, FLASH_CR_PG);
+      }
+      else
+      {
+        /* If the program operation is completed, disable the PG */
+        CLEAR_BIT(FLASH->CR2, FLASH_CR_PG);
+      }
+    }
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(&pFlash);
+
+  return status;
+}
+
+/**
+  * @brief  Program flash words of 256 bits at a specified address with interrupt enabled.
+  * @param  TypeProgram Indicate the way to program at a specified address.
+  *                      This parameter can be a value of @ref FLASH_Type_Program
+  * @param  FlashAddress specifies the address to be programmed.
+  * @param  DataAddress specifies the address of data (256 bits) to be programmed
+  *
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress)
+{
+  HAL_StatusTypeDef status;
+  __IO uint32_t *dest_addr = (__IO uint32_t*)FlashAddress;
+  __IO uint32_t *src_addr = (__IO uint32_t*)DataAddress;
+  uint32_t bank;
+  uint8_t row_index = FLASH_NB_32BITWORD_IN_FLASHWORD;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+  assert_param(IS_FLASH_PROGRAM_ADDRESS(FlashAddress));
+
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Reset error code */
+  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+#if defined (FLASH_OPTCR_PG_OTP)
+  if((IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress)) || (IS_FLASH_PROGRAM_ADDRESS_OTP(FlashAddress)))
+#else
+  if(IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress))
+#endif /* FLASH_OPTCR_PG_OTP */
+  {
+    bank = FLASH_BANK_1;
+  }
+  else
+  {
+    bank = FLASH_BANK_2;
+  }
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, bank);
+
+  if (status != HAL_OK)
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(&pFlash);
+  }
+  else
+  {
+    pFlash.Address = FlashAddress;
+
+    if(bank == FLASH_BANK_1)
+    {
+      /* Set internal variables used by the IRQ handler */
+      pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_BANK1;
+
+#if defined (FLASH_OPTCR_PG_OTP)
+      if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD)
+      {
+        /* Set OTP_PG bit */
+        SET_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP);
+      }
+      else
+#endif /* FLASH_OPTCR_PG_OTP */
+      {
+        /* Set PG bit */
+        SET_BIT(FLASH->CR1, FLASH_CR_PG);
+      }
+
+      /* Enable End of Operation and Error interrupts for Bank 1 */
+#if defined (FLASH_CR_OPERRIE)
+      __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1     | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
+                                  FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1);
+#else
+      __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1     | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
+                                  FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1);
+#endif /* FLASH_CR_OPERRIE */
+    }
+    else
+    {
+      /* Set internal variables used by the IRQ handler */
+      pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_BANK2;
+
+      /* Set PG bit */
+      SET_BIT(FLASH->CR2, FLASH_CR_PG);
+
+      /* Enable End of Operation and Error interrupts for Bank2 */
+#if defined (FLASH_CR_OPERRIE)
+      __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2     | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
+                                  FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2);
+#else
+      __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2     | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
+                                  FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2);
+#endif /* FLASH_CR_OPERRIE */
+    }
+
+    __ISB();
+    __DSB();
+
+#if defined (FLASH_OPTCR_PG_OTP)
+    if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD)
+    {
+      /* Program an OTP word (16 bits) */
+      *(__IO uint16_t *)FlashAddress = *(__IO uint16_t*)DataAddress;
+    }
+    else
+#endif /* FLASH_OPTCR_PG_OTP */
+    {
+      /* Program the flash word */
+      do
+      {
+        *dest_addr = *src_addr;
+        dest_addr++;
+        src_addr++;
+        row_index--;
+      } while (row_index != 0U);
+    }
+
+    __ISB();
+    __DSB();
+  }
+
+  return status;
+}
+
+/**
+  * @brief This function handles FLASH interrupt request.
+  * @retval None
+  */
+void HAL_FLASH_IRQHandler(void)
+{
+  uint32_t temp;
+  uint32_t errorflag;
+  FLASH_ProcedureTypeDef procedure;
+
+  /* Check FLASH Bank1 End of Operation flag  */
+  if(__HAL_FLASH_GET_FLAG_BANK1(FLASH_SR_EOP) != RESET)
+  {
+    if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE_BANK1)
+    {
+      /* Nb of sector to erased can be decreased */
+      pFlash.NbSectorsToErase--;
+
+      /* Check if there are still sectors to erase */
+      if(pFlash.NbSectorsToErase != 0U)
+      {
+        /* Indicate user which sector has been erased */
+        HAL_FLASH_EndOfOperationCallback(pFlash.Sector);
+
+        /* Clear bank 1 End of Operation pending bit */
+        __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1);
+
+        /* Increment sector number */
+        pFlash.Sector++;
+        temp = pFlash.Sector;
+        FLASH_Erase_Sector(temp, FLASH_BANK_1, pFlash.VoltageForErase);
+      }
+      else
+      {
+        /* No more sectors to Erase, user callback can be called */
+        /* Reset Sector and stop Erase sectors procedure */
+        pFlash.Sector = 0xFFFFFFFFU;
+        pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+
+        /* FLASH EOP interrupt user callback */
+        HAL_FLASH_EndOfOperationCallback(pFlash.Sector);
+
+        /* Clear FLASH End of Operation pending bit */
+        __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1);
+      }
+    }
+    else
+    {
+      procedure = pFlash.ProcedureOnGoing;
+
+      if((procedure == FLASH_PROC_MASSERASE_BANK1) || (procedure == FLASH_PROC_ALLBANK_MASSERASE))
+      {
+        /* MassErase ended. Return the selected bank */
+        /* FLASH EOP interrupt user callback */
+        HAL_FLASH_EndOfOperationCallback(FLASH_BANK_1);
+      }
+      else if(procedure == FLASH_PROC_PROGRAM_BANK1)
+      {
+        /* Program ended. Return the selected address */
+        /* FLASH EOP interrupt user callback */
+        HAL_FLASH_EndOfOperationCallback(pFlash.Address);
+      }
+      else
+      {
+        /* Nothing to do */
+      }
+
+      if((procedure != FLASH_PROC_SECTERASE_BANK2) && \
+         (procedure != FLASH_PROC_MASSERASE_BANK2) && \
+         (procedure != FLASH_PROC_PROGRAM_BANK2))
+      {
+        pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+        /* Clear FLASH End of Operation pending bit */
+        __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1);
+      }
+    }
+  }
+
+  /* Check FLASH Bank2 End of Operation flag  */
+  if(__HAL_FLASH_GET_FLAG_BANK2(FLASH_SR_EOP) != RESET)
+  {
+    if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE_BANK2)
+    {
+      /*Nb of sector to erased can be decreased*/
+      pFlash.NbSectorsToErase--;
+
+      /* Check if there are still sectors to erase*/
+      if(pFlash.NbSectorsToErase != 0U)
+      {
+        /*Indicate user which sector has been erased*/
+        HAL_FLASH_EndOfOperationCallback(pFlash.Sector);
+
+        /* Clear bank 2 End of Operation pending bit */
+        __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2);
+
+        /*Increment sector number*/
+        pFlash.Sector++;
+        temp = pFlash.Sector;
+        FLASH_Erase_Sector(temp, FLASH_BANK_2, pFlash.VoltageForErase);
+      }
+      else
+      {
+        /* No more sectors to Erase, user callback can be called */
+        /* Reset Sector and stop Erase sectors procedure */
+        pFlash.Sector = 0xFFFFFFFFU;
+        pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+
+        /* FLASH EOP interrupt user callback */
+        HAL_FLASH_EndOfOperationCallback(pFlash.Sector);
+
+        /* Clear FLASH End of Operation pending bit */
+        __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2);
+      }
+    }
+    else
+    {
+      procedure = pFlash.ProcedureOnGoing;
+
+      if((procedure == FLASH_PROC_MASSERASE_BANK2) || (procedure == FLASH_PROC_ALLBANK_MASSERASE))
+      {
+        /*MassErase ended. Return the selected bank*/
+        /* FLASH EOP interrupt user callback */
+        HAL_FLASH_EndOfOperationCallback(FLASH_BANK_2);
+      }
+      else if(procedure == FLASH_PROC_PROGRAM_BANK2)
+      {
+        /* Program ended. Return the selected address */
+        /* FLASH EOP interrupt user callback */
+        HAL_FLASH_EndOfOperationCallback(pFlash.Address);
+      }
+      else
+      {
+        /* Nothing to do */
+      }
+
+      if((procedure != FLASH_PROC_SECTERASE_BANK1) && \
+         (procedure != FLASH_PROC_MASSERASE_BANK1) && \
+         (procedure != FLASH_PROC_PROGRAM_BANK1))
+      {
+        pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+        /* Clear FLASH End of Operation pending bit */
+        __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2);
+      }
+    }
+  }
+
+  /* Check FLASH Bank1 operation error flags */
+#if defined (FLASH_SR_OPERR)
+  errorflag = FLASH->SR1 & (FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | FLASH_FLAG_STRBERR_BANK1 | \
+                            FLASH_FLAG_INCERR_BANK1 | FLASH_FLAG_OPERR_BANK1);
+#else
+  errorflag = FLASH->SR1 & (FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | FLASH_FLAG_STRBERR_BANK1 | \
+                            FLASH_FLAG_INCERR_BANK1);
+#endif /* FLASH_SR_OPERR */
+
+  if(errorflag != 0U)
+  {
+    /* Save the error code */
+    pFlash.ErrorCode |= errorflag;
+
+    /* Clear error programming flags */
+    __HAL_FLASH_CLEAR_FLAG_BANK1(errorflag);
+
+    procedure = pFlash.ProcedureOnGoing;
+
+    if(procedure == FLASH_PROC_SECTERASE_BANK1)
+    {
+      /* Return the faulty sector */
+      temp = pFlash.Sector;
+      pFlash.Sector = 0xFFFFFFFFU;
+    }
+    else if((procedure == FLASH_PROC_MASSERASE_BANK1) || (procedure == FLASH_PROC_ALLBANK_MASSERASE))
+    {
+      /* Return the faulty bank */
+      temp = FLASH_BANK_1;
+    }
+    else
+    {
+      /* Return the faulty address */
+      temp = pFlash.Address;
+    }
+
+    /* Stop the procedure ongoing*/
+    pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+
+    /* FLASH error interrupt user callback */
+    HAL_FLASH_OperationErrorCallback(temp);
+  }
+
+  /* Check FLASH Bank2 operation error flags */
+#if defined (FLASH_SR_OPERR)
+  errorflag = FLASH->SR2 & ((FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | FLASH_FLAG_STRBERR_BANK2 | \
+                             FLASH_FLAG_INCERR_BANK2 | FLASH_FLAG_OPERR_BANK2) & 0x7FFFFFFFU);
+#else
+  errorflag = FLASH->SR2 & ((FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | FLASH_FLAG_STRBERR_BANK2 | \
+                             FLASH_FLAG_INCERR_BANK2) & 0x7FFFFFFFU);
+#endif /* FLASH_SR_OPERR */
+
+  if(errorflag != 0U)
+  {
+    /* Save the error code */
+    pFlash.ErrorCode |= (errorflag | 0x80000000U);
+
+    /* Clear error programming flags */
+    __HAL_FLASH_CLEAR_FLAG_BANK2(errorflag);
+
+    procedure = pFlash.ProcedureOnGoing;
+
+    if(procedure== FLASH_PROC_SECTERASE_BANK2)
+    {
+      /*return the faulty sector*/
+      temp = pFlash.Sector;
+      pFlash.Sector = 0xFFFFFFFFU;
+    }
+    else if((procedure == FLASH_PROC_MASSERASE_BANK2) || (procedure == FLASH_PROC_ALLBANK_MASSERASE))
+    {
+      /*return the faulty bank*/
+      temp = FLASH_BANK_2;
+    }
+    else
+    {
+      /*return the faulty address*/
+      temp = pFlash.Address;
+    }
+
+    /*Stop the procedure ongoing*/
+    pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+
+    /* FLASH error interrupt user callback */
+    HAL_FLASH_OperationErrorCallback(temp);
+  }
+
+  if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
+  {
+#if defined (FLASH_CR_OPERRIE)
+    /* Disable Bank1 Operation and Error source interrupt */
+    __HAL_FLASH_DISABLE_IT_BANK1(FLASH_IT_EOP_BANK1    | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
+                                 FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1);
+
+    /* Disable Bank2 Operation and Error source interrupt */
+    __HAL_FLASH_DISABLE_IT_BANK2(FLASH_IT_EOP_BANK2    | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
+                                 FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2);
+#else
+    /* Disable Bank1 Operation and Error source interrupt */
+    __HAL_FLASH_DISABLE_IT_BANK1(FLASH_IT_EOP_BANK1    | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
+                                 FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1);
+
+    /* Disable Bank2 Operation and Error source interrupt */
+    __HAL_FLASH_DISABLE_IT_BANK2(FLASH_IT_EOP_BANK2    | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
+                                 FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2);
+#endif /* FLASH_CR_OPERRIE */
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(&pFlash);
+  }
+}
+
+/**
+  * @brief  FLASH end of operation interrupt callback
+  * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure
+  *                  Mass Erase: Bank number which has been requested to erase
+  *                  Sectors Erase: Sector which has been erased
+  *                    (if 0xFFFFFFFF, it means that all the selected sectors have been erased)
+  *                  Program: Address which was selected for data program
+  * @retval None
+  */
+__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(ReturnValue);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  FLASH operation error interrupt callback
+  * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure
+  *                 Mass Erase: Bank number which has been requested to erase
+  *                 Sectors Erase: Sector number which returned an error
+  *                 Program: Address which was selected for data program
+  * @retval None
+  */
+__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(ReturnValue);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FLASH_OperationErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
+ *  @brief   Management functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the FLASH
+    memory operations.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Unlock the FLASH control registers access
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Unlock(void)
+{
+  if(READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != 0U)
+  {
+    /* Authorize the FLASH Bank1 Registers access */
+    WRITE_REG(FLASH->KEYR1, FLASH_KEY1);
+    WRITE_REG(FLASH->KEYR1, FLASH_KEY2);
+
+    /* Verify Flash Bank1 is unlocked */
+    if (READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != 0U)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  if(READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != 0U)
+  {
+    /* Authorize the FLASH Bank2 Registers access */
+    WRITE_REG(FLASH->KEYR2, FLASH_KEY1);
+    WRITE_REG(FLASH->KEYR2, FLASH_KEY2);
+
+    /* Verify Flash Bank2 is unlocked */
+    if (READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != 0U)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Locks the FLASH control registers access
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Lock(void)
+{
+  /* Set the LOCK Bit to lock the FLASH Bank1 Control Register access */
+  SET_BIT(FLASH->CR1, FLASH_CR_LOCK);
+
+  /* Verify Flash Bank1 is locked */
+  if (READ_BIT(FLASH->CR1, FLASH_CR_LOCK) == 0U)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the LOCK Bit to lock the FLASH Bank2 Control Register access */
+  SET_BIT(FLASH->CR2, FLASH_CR_LOCK);
+
+  /* Verify Flash Bank2 is locked */
+  if (READ_BIT(FLASH->CR2, FLASH_CR_LOCK) == 0U)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Unlock the FLASH Option Control Registers access.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
+{
+  if(READ_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK) != 0U)
+  {
+    /* Authorizes the Option Byte registers programming */
+    WRITE_REG(FLASH->OPTKEYR, FLASH_OPT_KEY1);
+    WRITE_REG(FLASH->OPTKEYR, FLASH_OPT_KEY2);
+
+    /* Verify that the Option Bytes are unlocked */
+    if (READ_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK) != 0U)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Lock the FLASH Option Control Registers access.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
+{
+  /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
+  SET_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK);
+
+  /* Verify that the Option Bytes are locked */
+  if (READ_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK) == 0U)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Launch the option bytes loading.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
+{
+  HAL_StatusTypeDef status;
+
+  /* Wait for CRC computation to be completed */
+  if (FLASH_CRC_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK)
+  {
+    status = HAL_ERROR;
+  }
+  else if (FLASH_CRC_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    status = HAL_OK;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Set OPTSTRT Bit */
+    SET_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTSTART);
+
+    /* Wait for OB change operation to be completed */
+    status = FLASH_OB_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+  }
+
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions
+ *  @brief   Peripheral Errors functions
+ *
+@verbatim
+ ===============================================================================
+                ##### Peripheral Errors functions #####
+ ===============================================================================
+    [..]
+    This subsection permits to get in run-time Errors of the FLASH peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Get the specific FLASH error flag.
+  * @retval HAL_FLASH_ERRORCode The returned value can be:
+  *            @arg HAL_FLASH_ERROR_NONE       : No error set
+  *
+  *            @arg HAL_FLASH_ERROR_WRP_BANK1  : Write Protection Error on Bank 1
+  *            @arg HAL_FLASH_ERROR_PGS_BANK1  : Program Sequence Error on Bank 1
+  *            @arg HAL_FLASH_ERROR_STRB_BANK1 : Strobe Error on Bank 1
+  *            @arg HAL_FLASH_ERROR_INC_BANK1  : Inconsistency Error on Bank 1
+  *            @arg HAL_FLASH_ERROR_OPE_BANK1  : Operation Error on Bank 1
+  *            @arg HAL_FLASH_ERROR_RDP_BANK1  : Read Protection Error on Bank 1
+  *            @arg HAL_FLASH_ERROR_RDS_BANK1  : Read Secured Error on Bank 1
+  *            @arg HAL_FLASH_ERROR_SNECC_BANK1: ECC Single Correction Error on Bank 1
+  *            @arg HAL_FLASH_ERROR_DBECC_BANK1: ECC Double Detection Error on Bank 1
+  *            @arg HAL_FLASH_ERROR_CRCRD_BANK1: CRC Read Error on Bank 1
+  *
+  *            @arg HAL_FLASH_ERROR_WRP_BANK2  : Write Protection Error on Bank 2
+  *            @arg HAL_FLASH_ERROR_PGS_BANK2  : Program Sequence Error on Bank 2
+  *            @arg HAL_FLASH_ERROR_STRB_BANK2 : Strobe Error on Bank 2
+  *            @arg HAL_FLASH_ERROR_INC_BANK2  : Inconsistency Error on Bank 2
+  *            @arg HAL_FLASH_ERROR_OPE_BANK2  : Operation Error on Bank 2
+  *            @arg HAL_FLASH_ERROR_RDP_BANK2  : Read Protection Error on Bank 2
+  *            @arg HAL_FLASH_ERROR_RDS_BANK2  : Read Secured Error on Bank 2
+  *            @arg HAL_FLASH_ERROR_SNECC_BANK2: SNECC Error on Bank 2
+  *            @arg HAL_FLASH_ERROR_DBECC_BANK2: Double Detection ECC on Bank 2
+  *            @arg HAL_FLASH_ERROR_CRCRD_BANK2: CRC Read Error on Bank 2
+*/
+
+uint32_t HAL_FLASH_GetError(void)
+{
+   return pFlash.ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @addtogroup FLASH_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Wait for a FLASH operation to complete.
+  * @param  Timeout maximum flash operation timeout
+  * @param  Bank flash FLASH_BANK_1 or FLASH_BANK_2
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout, uint32_t Bank)
+{
+  /* Wait for the FLASH operation to complete by polling on QW flag to be reset.
+     Even if the FLASH operation fails, the QW flag will be reset and an error
+     flag will be set */
+
+  uint32_t bsyflag, errorflag;
+  uint32_t tickstart = HAL_GetTick();
+
+  assert_param(IS_FLASH_BANK_EXCLUSIVE(Bank));
+
+  /* Select bsyflag depending on Bank */
+  if(Bank == FLASH_BANK_1)
+  {
+    bsyflag = FLASH_FLAG_QW_BANK1;
+  }
+  else
+  {
+    bsyflag = FLASH_FLAG_QW_BANK2;
+  }
+
+  while(__HAL_FLASH_GET_FLAG(bsyflag))
+  {
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  /* Get Error Flags */
+  if (Bank == FLASH_BANK_1)
+  {
+    errorflag = FLASH->SR1 & FLASH_FLAG_ALL_ERRORS_BANK1;
+  }
+  else
+  {
+    errorflag = (FLASH->SR2 & FLASH_FLAG_ALL_ERRORS_BANK2) | 0x80000000U;
+  }
+
+  /* In case of error reported in Flash SR1 or SR2 registers (ECCC not managed as an error) */
+  if((errorflag & 0x7DFFFFFFU) != 0U)
+  {
+    /*Save the error code*/
+    pFlash.ErrorCode |= errorflag;
+
+    /* Clear error programming flags */
+    __HAL_FLASH_CLEAR_FLAG(errorflag);
+
+    return HAL_ERROR;
+  }
+
+  /* Check FLASH End of Operation flag  */
+  if(Bank == FLASH_BANK_1)
+  {
+    if (__HAL_FLASH_GET_FLAG_BANK1(FLASH_FLAG_EOP_BANK1))
+    {
+      /* Clear FLASH End of Operation pending bit */
+      __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1);
+    }
+  }
+  else
+  {
+    if (__HAL_FLASH_GET_FLAG_BANK2(FLASH_FLAG_EOP_BANK2))
+    {
+      /* Clear FLASH End of Operation pending bit */
+      __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2);
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Wait for a FLASH Option Bytes change operation to complete.
+  * @param  Timeout maximum flash operation timeout
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef FLASH_OB_WaitForLastOperation(uint32_t Timeout)
+{
+  /* Get timeout */
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Wait for the FLASH Option Bytes change operation to complete by polling on OPT_BUSY flag to be reset */
+  while(READ_BIT(FLASH->OPTSR_CUR, FLASH_OPTSR_OPT_BUSY) != 0U)
+  {
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  /* Check option byte change error */
+  if(READ_BIT(FLASH->OPTSR_CUR, FLASH_OPTSR_OPTCHANGEERR) != 0U)
+  {
+    /* Save the error code */
+    pFlash.ErrorCode |= HAL_FLASH_ERROR_OB_CHANGE;
+
+    /* Clear the OB error flag */
+    FLASH->OPTCCR |= FLASH_OPTCCR_CLR_OPTCHANGEERR;
+
+    return HAL_ERROR;
+  }
+
+  /* If there is no error flag set */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Wait for a FLASH CRC computation to complete.
+  * @param  Timeout maximum flash operation timeout
+  * @param  Bank flash FLASH_BANK_1 or FLASH_BANK_2
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef FLASH_CRC_WaitForLastOperation(uint32_t Timeout, uint32_t Bank)
+{
+  uint32_t bsyflag;
+  uint32_t tickstart = HAL_GetTick();
+
+  assert_param(IS_FLASH_BANK_EXCLUSIVE(Bank));
+
+  /* Select bsyflag depending on Bank */
+  if(Bank == FLASH_BANK_1)
+  {
+    bsyflag = FLASH_FLAG_CRC_BUSY_BANK1;
+  }
+  else
+  {
+    bsyflag = FLASH_FLAG_CRC_BUSY_BANK2;
+  }
+
+  /* Wait for the FLASH CRC computation to complete by polling on CRC_BUSY flag to be reset */
+  while(__HAL_FLASH_GET_FLAG(bsyflag))
+  {
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  /* Check FLASH CRC read error flag  */
+  if(Bank == FLASH_BANK_1)
+  {
+    if (__HAL_FLASH_GET_FLAG_BANK1(FLASH_FLAG_CRCRDERR_BANK1))
+    {
+      /* Save the error code */
+      pFlash.ErrorCode |= HAL_FLASH_ERROR_CRCRD_BANK1;
+
+      /* Clear FLASH CRC read error pending bit */
+      __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_CRCRDERR_BANK1);
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    if (__HAL_FLASH_GET_FLAG_BANK2(FLASH_FLAG_CRCRDERR_BANK2))
+    {
+      /* Save the error code */
+      pFlash.ErrorCode |= HAL_FLASH_ERROR_CRCRD_BANK2;
+
+      /* Clear FLASH CRC read error pending bit */
+      __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_CRCRDERR_BANK2);
+
+      return HAL_ERROR;
+    }
+  }
+
+  /* If there is no error flag set */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c
new file mode 100644
index 00000000..77b809f7
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c
@@ -0,0 +1,1709 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_flash_ex.c
+  * @author  MCD Application Team
+  * @brief   Extended FLASH HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the FLASH extension peripheral:
+  *           + Extended programming operations functions
+  *
+ @verbatim
+ ==============================================================================
+                   ##### Flash Extension features #####
+  ==============================================================================
+
+  [..] Comparing to other previous devices, the FLASH interface for STM32H7xx
+       devices contains the following additional features
+
+       (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
+           capability (RWW)
+       (+) Dual bank memory organization
+       (+) PCROP protection for all banks
+       (+) Global readout protection (RDP)
+       (+) Write protection
+       (+) Secure access only protection
+       (+) Bank / register swapping
+       (+) Cyclic Redundancy Check (CRC)
+
+                        ##### How to use this driver #####
+ ==============================================================================
+  [..] This driver provides functions to configure and program the FLASH memory
+       of all STM32H7xx devices. It includes
+      (#) FLASH Memory Erase functions:
+           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
+                HAL_FLASH_Lock() functions
+           (++) Erase function: Sector erase, bank erase and dual-bank mass erase
+           (++) There are two modes of erase :
+             (+++) Polling Mode using HAL_FLASHEx_Erase()
+             (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
+
+      (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to:
+        (++) Set/Reset the write protection per bank
+        (++) Set the Read protection Level
+        (++) Set the BOR level
+        (++) Program the user Option Bytes
+        (++) PCROP protection configuration and control per bank
+        (++) Secure area configuration and control per bank
+        (++) Core Boot address configuration
+
+      (#) FLASH Memory Lock and unlock per Bank: HAL_FLASHEx_Lock_Bank1(), HAL_FLASHEx_Unlock_Bank1(),
+          HAL_FLASHEx_Lock_Bank2() and HAL_FLASHEx_Unlock_Bank2() functions
+
+      (#) FLASH CRC computation function: Use HAL_FLASHEx_ComputeCRC() to:
+          (++) Enable CRC feature
+          (++) Program the desired burst size
+          (++) Define the user Flash Area on which the CRC has be computed
+          (++) Perform the CRC computation
+          (++) Disable CRC feature
+
+ @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup FLASHEx  FLASHEx
+  * @brief FLASH HAL Extension module driver
+  * @{
+  */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup FLASHEx_Private_Constants
+  * @{
+  */
+#define FLASH_TIMEOUT_VALUE       50000U /* 50 s */
+
+/**
+  * @}
+  */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
+  * @{
+  */
+static void FLASH_MassErase(uint32_t VoltageRange, uint32_t Banks);
+static void FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks);
+static void FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Bank);
+static void FLASH_OB_GetWRP(uint32_t *WRPState, uint32_t *WRPSector, uint32_t Bank);
+static void FLASH_OB_RDPConfig(uint32_t RDPLevel);
+static uint32_t FLASH_OB_GetRDP(void);
+static void FLASH_OB_PCROPConfig(uint32_t PCROConfigRDP, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr, uint32_t Banks);
+static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROPStartAddr,uint32_t *PCROPEndAddr, uint32_t Bank);
+static void FLASH_OB_BOR_LevelConfig(uint32_t Level);
+static uint32_t FLASH_OB_GetBOR(void);
+static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig);
+static uint32_t FLASH_OB_GetUser(void);
+static void FLASH_OB_BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1);
+static void FLASH_OB_GetBootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1);
+static void FLASH_OB_SecureAreaConfig(uint32_t SecureAreaConfig, uint32_t SecureAreaStartAddr, uint32_t SecureAreaEndAddr, uint32_t Banks);
+static void FLASH_OB_GetSecureArea(uint32_t *SecureAreaConfig, uint32_t *SecureAreaStartAddr, uint32_t *SecureAreaEndAddr, uint32_t Bank);
+static void FLASH_CRC_AddSector(uint32_t Sector, uint32_t Bank);
+static void FLASH_CRC_SelectAddress(uint32_t CRCStartAddr, uint32_t CRCEndAddr, uint32_t Bank);
+
+#if defined (DUAL_CORE)
+static void FLASH_OB_CM4BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1);
+static void FLASH_OB_GetCM4BootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1);
+#endif /* DUAL_CORE */
+
+#if defined (FLASH_OTPBL_LOCKBL)
+static void FLASH_OB_OTP_LockConfig(uint32_t OTP_Block);
+static uint32_t FLASH_OB_OTP_GetLock(void);
+#endif /* FLASH_OTPBL_LOCKBL */
+/**
+  * @}
+  */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
+  * @{
+  */
+
+/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
+ *  @brief   Extended IO operation functions
+ *
+@verbatim
+ ===============================================================================
+                ##### Extended programming operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the Extension FLASH
+    programming operations Operations.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Perform a mass erase or erase the specified FLASH memory sectors
+  * @param[in]  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
+  *         contains the configuration information for the erasing.
+  *
+  * @param[out]  SectorError pointer to variable  that contains the configuration
+  *          information on faulty sector in case of error (0xFFFFFFFF means that all
+  *          the sectors have been correctly erased)
+  *
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t sector_index;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
+  assert_param(IS_FLASH_BANK(pEraseInit->Banks));
+
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Reset error code */
+  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+  /* Wait for last operation to be completed on Bank1 */
+  if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
+  {
+    if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK)
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  /* Wait for last operation to be completed on Bank2 */
+  if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
+  {
+    if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK)
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  if(status == HAL_OK)
+  {
+    if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
+    {
+      /* Mass erase to be done */
+      FLASH_MassErase(pEraseInit->VoltageRange, pEraseInit->Banks);
+
+      /* Wait for last operation to be completed */
+      if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
+      {
+        if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK)
+        {
+          status = HAL_ERROR;
+        }
+        /* if the erase operation is completed, disable the Bank1 BER Bit */
+        FLASH->CR1 &= (~FLASH_CR_BER);
+      }
+      if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
+      {
+        if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK)
+        {
+          status = HAL_ERROR;
+        }
+        /* if the erase operation is completed, disable the Bank2 BER Bit */
+        FLASH->CR2 &= (~FLASH_CR_BER);
+      }
+    }
+    else
+    {
+      /*Initialization of SectorError variable*/
+      *SectorError = 0xFFFFFFFFU;
+
+      /* Erase by sector by sector to be done*/
+      for(sector_index = pEraseInit->Sector; sector_index < (pEraseInit->NbSectors + pEraseInit->Sector); sector_index++)
+      {
+        FLASH_Erase_Sector(sector_index, pEraseInit->Banks, pEraseInit->VoltageRange);
+
+        if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
+        {
+          /* Wait for last operation to be completed */
+          status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
+
+          /* If the erase operation is completed, disable the SER Bit */
+          FLASH->CR1 &= (~(FLASH_CR_SER | FLASH_CR_SNB));
+        }
+        if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
+        {
+          /* Wait for last operation to be completed */
+          status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
+
+          /* If the erase operation is completed, disable the SER Bit */
+          FLASH->CR2 &= (~(FLASH_CR_SER | FLASH_CR_SNB));
+        }
+
+        if(status != HAL_OK)
+        {
+          /* In case of error, stop erase procedure and return the faulty sector */
+          *SectorError = sector_index;
+          break;
+        }
+      }
+    }
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(&pFlash);
+
+  return status;
+}
+
+/**
+  * @brief  Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled
+  * @param  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
+  *         contains the configuration information for the erasing.
+  *
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
+  assert_param(IS_FLASH_BANK(pEraseInit->Banks));
+
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Reset error code */
+  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+  /* Wait for last operation to be completed */
+  if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
+  {
+    if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK)
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
+  {
+    if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK)
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  if (status != HAL_OK)
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(&pFlash);
+  }
+  else
+  {
+    if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
+    {
+      /* Enable End of Operation and Error interrupts for Bank 1 */
+#if defined (FLASH_CR_OPERRIE)
+      __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1     | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
+                                  FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1);
+#else
+      __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1     | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
+                                  FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1);
+#endif /* FLASH_CR_OPERRIE */
+    }
+    if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
+    {
+      /* Enable End of Operation and Error interrupts for Bank 2 */
+#if defined (FLASH_CR_OPERRIE)
+      __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2     | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
+                                  FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2);
+#else
+      __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2     | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
+                                  FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2);
+#endif /* FLASH_CR_OPERRIE */
+    }
+
+    if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
+    {
+      /*Mass erase to be done*/
+      if(pEraseInit->Banks == FLASH_BANK_1)
+      {
+        pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE_BANK1;
+      }
+      else if(pEraseInit->Banks == FLASH_BANK_2)
+      {
+        pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE_BANK2;
+      }
+      else
+      {
+        pFlash.ProcedureOnGoing = FLASH_PROC_ALLBANK_MASSERASE;
+      }
+
+      FLASH_MassErase(pEraseInit->VoltageRange, pEraseInit->Banks);
+    }
+    else
+    {
+      /* Erase by sector to be done */
+      if(pEraseInit->Banks == FLASH_BANK_1)
+      {
+        pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE_BANK1;
+      }
+      else
+      {
+        pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE_BANK2;
+      }
+
+      pFlash.NbSectorsToErase = pEraseInit->NbSectors;
+      pFlash.Sector = pEraseInit->Sector;
+      pFlash.VoltageForErase = pEraseInit->VoltageRange;
+
+      /* Erase first sector and wait for IT */
+      FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->Banks, pEraseInit->VoltageRange);
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Program option bytes
+  * @param  pOBInit pointer to an FLASH_OBInitStruct structure that
+  *         contains the configuration information for the programming.
+  *
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check the parameters */
+  assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
+
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Reset Error Code */
+  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+  /* Wait for last operation to be completed */
+  if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK)
+  {
+    status = HAL_ERROR;
+  }
+  else if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    status = HAL_OK;
+  }
+
+  if(status == HAL_OK)
+  {
+    /*Write protection configuration*/
+    if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
+    {
+      assert_param(IS_WRPSTATE(pOBInit->WRPState));
+
+      if(pOBInit->WRPState == OB_WRPSTATE_ENABLE)
+      {
+        /*Enable of Write protection on the selected Sector*/
+        FLASH_OB_EnableWRP(pOBInit->WRPSector,pOBInit->Banks);
+      }
+      else
+      {
+        /*Disable of Write protection on the selected Sector*/
+        FLASH_OB_DisableWRP(pOBInit->WRPSector, pOBInit->Banks);
+      }
+    }
+
+    /* Read protection configuration */
+    if((pOBInit->OptionType & OPTIONBYTE_RDP) != 0U)
+    {
+      /* Configure the Read protection level */
+      FLASH_OB_RDPConfig(pOBInit->RDPLevel);
+    }
+
+    /* User Configuration */
+    if((pOBInit->OptionType & OPTIONBYTE_USER) != 0U)
+    {
+      /* Configure the user option bytes */
+      FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig);
+    }
+
+    /* PCROP Configuration */
+    if((pOBInit->OptionType & OPTIONBYTE_PCROP) != 0U)
+    {
+      assert_param(IS_FLASH_BANK(pOBInit->Banks));
+
+      /*Configure the Proprietary code readout protection */
+      FLASH_OB_PCROPConfig(pOBInit->PCROPConfig, pOBInit->PCROPStartAddr, pOBInit->PCROPEndAddr, pOBInit->Banks);
+    }
+
+    /* BOR Level configuration */
+    if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR)
+    {
+      FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel);
+    }
+
+#if defined(DUAL_CORE)
+    /* CM7 Boot Address  configuration */
+    if((pOBInit->OptionType & OPTIONBYTE_CM7_BOOTADD) == OPTIONBYTE_CM7_BOOTADD)
+    {
+      FLASH_OB_BootAddConfig(pOBInit->BootConfig, pOBInit->BootAddr0, pOBInit->BootAddr1);
+    }
+
+    /* CM4 Boot Address  configuration */
+    if((pOBInit->OptionType & OPTIONBYTE_CM4_BOOTADD) == OPTIONBYTE_CM4_BOOTADD)
+    {
+      FLASH_OB_CM4BootAddConfig(pOBInit->CM4BootConfig, pOBInit->CM4BootAddr0, pOBInit->CM4BootAddr1);
+    }
+#else /* Single Core*/
+    /* Boot Address  configuration */
+    if((pOBInit->OptionType & OPTIONBYTE_BOOTADD) == OPTIONBYTE_BOOTADD)
+    {
+      FLASH_OB_BootAddConfig(pOBInit->BootConfig, pOBInit->BootAddr0, pOBInit->BootAddr1);
+    }
+#endif /*DUAL_CORE*/
+
+    /* Secure area configuration */
+    if((pOBInit->OptionType & OPTIONBYTE_SECURE_AREA) == OPTIONBYTE_SECURE_AREA)
+    {
+      FLASH_OB_SecureAreaConfig(pOBInit->SecureAreaConfig, pOBInit->SecureAreaStartAddr, pOBInit->SecureAreaEndAddr,pOBInit->Banks);
+    }
+
+#if defined(FLASH_OTPBL_LOCKBL)
+    /* OTP Block Lock configuration */
+    if((pOBInit->OptionType & OPTIONBYTE_OTP_LOCK) == OPTIONBYTE_OTP_LOCK)
+    {
+      FLASH_OB_OTP_LockConfig(pOBInit->OTPBlockLock);
+    }
+#endif /* FLASH_OTPBL_LOCKBL */
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(&pFlash);
+
+  return status;
+}
+
+/**
+  * @brief Get the Option byte configuration
+  * @param  pOBInit pointer to an FLASH_OBInitStruct structure that
+  *         contains the configuration information for the programming.
+  * @note   The parameter Banks of the pOBInit structure must be set exclusively to FLASH_BANK_1 or FLASH_BANK_2,
+  *         as this parameter is use to get the given Bank WRP, PCROP and secured area configuration.
+  *
+  * @retval None
+  */
+void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
+{
+  pOBInit->OptionType = (OPTIONBYTE_USER | OPTIONBYTE_RDP | OPTIONBYTE_BOR);
+
+  /* Get Read protection level */
+  pOBInit->RDPLevel = FLASH_OB_GetRDP();
+
+  /* Get the user option bytes */
+  pOBInit->USERConfig = FLASH_OB_GetUser();
+
+  /*Get BOR Level*/
+  pOBInit->BORLevel = FLASH_OB_GetBOR();
+
+  if ((pOBInit->Banks == FLASH_BANK_1) || (pOBInit->Banks == FLASH_BANK_2))
+  {
+    pOBInit->OptionType |= (OPTIONBYTE_WRP | OPTIONBYTE_PCROP | OPTIONBYTE_SECURE_AREA);
+
+    /* Get write protection on the selected area */
+    FLASH_OB_GetWRP(&(pOBInit->WRPState), &(pOBInit->WRPSector), pOBInit->Banks);
+
+    /* Get the Proprietary code readout protection */
+    FLASH_OB_GetPCROP(&(pOBInit->PCROPConfig), &(pOBInit->PCROPStartAddr), &(pOBInit->PCROPEndAddr), pOBInit->Banks);
+
+    /*Get Bank Secure area*/
+    FLASH_OB_GetSecureArea(&(pOBInit->SecureAreaConfig), &(pOBInit->SecureAreaStartAddr), &(pOBInit->SecureAreaEndAddr), pOBInit->Banks);
+  }
+
+  /*Get Boot Address*/
+  FLASH_OB_GetBootAdd(&(pOBInit->BootAddr0), &(pOBInit->BootAddr1));
+#if defined(DUAL_CORE)
+  pOBInit->OptionType |= OPTIONBYTE_CM7_BOOTADD | OPTIONBYTE_CM4_BOOTADD;
+
+  /*Get CM4 Boot Address*/
+  FLASH_OB_GetCM4BootAdd(&(pOBInit->CM4BootAddr0), &(pOBInit->CM4BootAddr1));
+#else
+  pOBInit->OptionType |= OPTIONBYTE_BOOTADD;
+#endif /*DUAL_CORE*/
+
+#if defined (FLASH_OTPBL_LOCKBL)
+  pOBInit->OptionType |= OPTIONBYTE_OTP_LOCK;
+
+  /* Get OTP Block Lock */
+  pOBInit->OTPBlockLock = FLASH_OB_OTP_GetLock();
+#endif /* FLASH_OTPBL_LOCKBL */
+}
+
+/**
+  * @brief  Unlock the FLASH Bank1 control registers access
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank1(void)
+{
+  if(READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != 0U)
+  {
+    /* Authorize the FLASH Bank1 Registers access */
+    WRITE_REG(FLASH->KEYR1, FLASH_KEY1);
+    WRITE_REG(FLASH->KEYR1, FLASH_KEY2);
+
+    /* Verify Flash Bank1 is unlocked */
+    if (READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != 0U)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Locks the FLASH Bank1 control registers access
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1(void)
+{
+  /* Set the LOCK Bit to lock the FLASH Bank1 Registers access */
+  SET_BIT(FLASH->CR1, FLASH_CR_LOCK);
+  return HAL_OK;
+}
+
+/**
+  * @brief  Unlock the FLASH Bank2 control registers access
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank2(void)
+{
+  if(READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != 0U)
+  {
+    /* Authorize the FLASH Bank2 Registers access */
+    WRITE_REG(FLASH->KEYR2, FLASH_KEY1);
+    WRITE_REG(FLASH->KEYR2, FLASH_KEY2);
+
+    /* Verify Flash Bank1 is unlocked */
+    if (READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != 0U)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Locks the FLASH Bank2 control registers access
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank2(void)
+{
+  /* Set the LOCK Bit to lock the FLASH Bank2 Registers access */
+  SET_BIT(FLASH->CR2, FLASH_CR_LOCK);
+  return HAL_OK;
+}
+
+/*
+  * @brief  Perform a CRC computation on the specified FLASH memory area
+  * @param  pCRCInit pointer to an FLASH_CRCInitTypeDef structure that
+  *         contains the configuration information for the CRC computation.
+  * @note   CRC computation uses CRC-32 (Ethernet) polynomial 0x4C11DB7
+  * @note   The application should avoid running a CRC on PCROP or secure-only
+  *         user Flash memory area since it may alter the expected CRC value.
+  *         A special error flag (CRC read error: CRCRDERR) can be used to
+  *         detect such a case.
+  * @retval HAL Status
+*/
+HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_t *CRC_Result)
+{
+  HAL_StatusTypeDef status;
+  uint32_t sector_index;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_BANK_EXCLUSIVE(pCRCInit->Bank));
+  assert_param(IS_FLASH_TYPECRC(pCRCInit->TypeCRC));
+
+  /* Wait for OB change operation to be completed */
+  status = FLASH_OB_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if (status == HAL_OK)
+  {
+    if (pCRCInit->Bank == FLASH_BANK_1)
+    {
+      /* Enable CRC feature */
+      FLASH->CR1 |= FLASH_CR_CRC_EN;
+
+      /* Clear CRC flags in Status Register: CRC end of calculation and CRC read error */
+      FLASH->CCR1 |= (FLASH_CCR_CLR_CRCEND | FLASH_CCR_CLR_CRCRDERR);
+
+      /* Clear current CRC result, program burst size and define memory area on which CRC has to be computed */
+      FLASH->CRCCR1 |= FLASH_CRCCR_CLEAN_CRC | pCRCInit->BurstSize | pCRCInit->TypeCRC;
+
+      if (pCRCInit->TypeCRC == FLASH_CRC_SECTORS)
+      {
+        /* Clear sectors list */
+        FLASH->CRCCR1 |= FLASH_CRCCR_CLEAN_SECT;
+
+        /* Select CRC sectors */
+        for(sector_index = pCRCInit->Sector; sector_index < (pCRCInit->NbSectors + pCRCInit->Sector); sector_index++)
+        {
+          FLASH_CRC_AddSector(sector_index, FLASH_BANK_1);
+        }
+      }
+      else if (pCRCInit->TypeCRC == FLASH_CRC_BANK)
+      {
+        /* Enable Bank 1 CRC select bit */
+        FLASH->CRCCR1 |= FLASH_CRCCR_ALL_BANK;
+      }
+      else
+      {
+        /* Select CRC start and end addresses */
+        FLASH_CRC_SelectAddress(pCRCInit->CRCStartAddr, pCRCInit->CRCEndAddr, FLASH_BANK_1);
+      }
+
+      /* Start the CRC calculation */
+      FLASH->CRCCR1 |= FLASH_CRCCR_START_CRC;
+
+      /* Wait on CRC busy flag */
+      status = FLASH_CRC_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
+
+      /* Return CRC result */
+      (*CRC_Result) = FLASH->CRCDATA;
+
+      /* Disable CRC feature */
+      FLASH->CR1 &= (~FLASH_CR_CRC_EN);
+
+      /* Clear CRC flags */
+      __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_CRCEND_BANK1 | FLASH_FLAG_CRCRDERR_BANK1);
+    }
+    else
+    {
+      /* Enable CRC feature */
+      FLASH->CR2 |= FLASH_CR_CRC_EN;
+
+      /* Clear CRC flags in Status Register: CRC end of calculation and CRC read error */
+      FLASH->CCR2 |= (FLASH_CCR_CLR_CRCEND | FLASH_CCR_CLR_CRCRDERR);
+
+      /* Clear current CRC result, program burst size and define memory area on which CRC has to be computed */
+      FLASH->CRCCR2 |= FLASH_CRCCR_CLEAN_CRC | pCRCInit->BurstSize | pCRCInit->TypeCRC;
+
+      if (pCRCInit->TypeCRC == FLASH_CRC_SECTORS)
+      {
+        /* Clear sectors list */
+        FLASH->CRCCR2 |= FLASH_CRCCR_CLEAN_SECT;
+
+        /* Add CRC sectors */
+        for(sector_index = pCRCInit->Sector; sector_index < (pCRCInit->NbSectors + pCRCInit->Sector); sector_index++)
+        {
+          FLASH_CRC_AddSector(sector_index, FLASH_BANK_2);
+        }
+      }
+      else if (pCRCInit->TypeCRC == FLASH_CRC_BANK)
+      {
+        /* Enable Bank 2 CRC select bit */
+        FLASH->CRCCR2 |= FLASH_CRCCR_ALL_BANK;
+      }
+      else
+      {
+        /* Select CRC start and end addresses */
+        FLASH_CRC_SelectAddress(pCRCInit->CRCStartAddr, pCRCInit->CRCEndAddr, FLASH_BANK_2);
+      }
+
+      /* Start the CRC calculation */
+      FLASH->CRCCR2 |= FLASH_CRCCR_START_CRC;
+
+      /* Wait on CRC busy flag */
+      status = FLASH_CRC_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
+
+      /* Return CRC result */
+      (*CRC_Result) = FLASH->CRCDATA;
+
+      /* Disable CRC feature */
+      FLASH->CR2 &= (~FLASH_CR_CRC_EN);
+
+      /* Clear CRC flags */
+      __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_CRCEND_BANK2 | FLASH_FLAG_CRCRDERR_BANK2);
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @addtogroup FLASHEx_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Mass erase of FLASH memory
+  * @param  VoltageRange The device program/erase parallelism.
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_VOLTAGE_RANGE_1 : Flash program/erase by 8 bits
+  *            @arg FLASH_VOLTAGE_RANGE_2 : Flash program/erase by 16 bits
+  *            @arg FLASH_VOLTAGE_RANGE_3 : Flash program/erase by 32 bits
+  *            @arg FLASH_VOLTAGE_RANGE_4 : Flash program/erase by 64 bits
+  *
+  * @param  Banks Banks to be erased
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: Bank1 to be erased
+  *            @arg FLASH_BANK_2: Bank2 to be erased
+  *            @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
+  *
+  * @retval HAL Status
+  */
+static void FLASH_MassErase(uint32_t VoltageRange, uint32_t Banks)
+{
+  /* Check the parameters */
+#if defined (FLASH_CR_PSIZE)
+  assert_param(IS_VOLTAGERANGE(VoltageRange));
+#else
+  UNUSED(VoltageRange);
+#endif /* FLASH_CR_PSIZE */
+  assert_param(IS_FLASH_BANK(Banks));
+
+  /* Flash Mass Erase */
+  if((Banks & FLASH_BANK_BOTH) == FLASH_BANK_BOTH)
+  {
+#if defined (FLASH_CR_PSIZE)
+    /* Reset Program/erase VoltageRange for Bank1 and Bank2 */
+    FLASH->CR1 &= (~FLASH_CR_PSIZE);
+    FLASH->CR2 &= (~FLASH_CR_PSIZE);
+
+    /* Set voltage range */
+    FLASH->CR1 |= VoltageRange;
+    FLASH->CR2 |= VoltageRange;
+#endif /* FLASH_CR_PSIZE */
+
+    /* Set Mass Erase Bit */
+    FLASH->OPTCR |= FLASH_OPTCR_MER;
+  }
+  else
+  {
+    /* Proceed to erase Flash Bank  */
+    if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
+    {
+#if defined (FLASH_CR_PSIZE)
+      /* Set Program/erase VoltageRange for Bank1 */
+      FLASH->CR1 &= (~FLASH_CR_PSIZE);
+      FLASH->CR1 |=  VoltageRange;
+#endif /* FLASH_CR_PSIZE */
+
+      /* Erase Bank1 */
+      FLASH->CR1 |= (FLASH_CR_BER | FLASH_CR_START);
+    }
+    if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
+    {
+#if defined (FLASH_CR_PSIZE)
+      /* Set Program/erase VoltageRange for Bank2 */
+      FLASH->CR2 &= (~FLASH_CR_PSIZE);
+      FLASH->CR2 |= VoltageRange;
+#endif /* FLASH_CR_PSIZE */
+
+      /* Erase Bank2 */
+      FLASH->CR2 |= (FLASH_CR_BER | FLASH_CR_START);
+    }
+  }
+}
+
+/**
+  * @brief  Erase the specified FLASH memory sector
+  * @param  Sector FLASH sector to erase
+  *          This parameter can be a value of @ref FLASH_Sectors
+  * @param  Banks Banks to be erased
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: Bank1 to be erased
+  *            @arg FLASH_BANK_2: Bank2 to be erased
+  *            @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
+  * @param  VoltageRange The device program/erase parallelism.
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_VOLTAGE_RANGE_1 : Flash program/erase by 8 bits
+  *            @arg FLASH_VOLTAGE_RANGE_2 : Flash program/erase by 16 bits
+  *            @arg FLASH_VOLTAGE_RANGE_3 : Flash program/erase by 32 bits
+  *            @arg FLASH_VOLTAGE_RANGE_4 : Flash program/erase by 64 bits
+  *
+  * @retval None
+  */
+void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange)
+{
+  assert_param(IS_FLASH_SECTOR(Sector));
+  assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks));
+#if defined (FLASH_CR_PSIZE)
+  assert_param(IS_VOLTAGERANGE(VoltageRange));
+#else
+  UNUSED(VoltageRange);
+#endif /* FLASH_CR_PSIZE */
+
+  if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
+  {
+#if defined (FLASH_CR_PSIZE)
+    /* Reset Program/erase VoltageRange and Sector Number for Bank1 */
+    FLASH->CR1 &= ~(FLASH_CR_PSIZE | FLASH_CR_SNB);
+
+    FLASH->CR1 |= (FLASH_CR_SER | VoltageRange | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START);
+#else
+    /* Reset Sector Number for Bank1 */
+    FLASH->CR1 &= ~(FLASH_CR_SNB);
+
+    FLASH->CR1 |= (FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START);
+#endif /* FLASH_CR_PSIZE */
+  }
+
+  if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
+  {
+#if defined (FLASH_CR_PSIZE)
+    /* Reset Program/erase VoltageRange and Sector Number for Bank2 */
+    FLASH->CR2 &= ~(FLASH_CR_PSIZE | FLASH_CR_SNB);
+
+    FLASH->CR2 |= (FLASH_CR_SER | VoltageRange  | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START);
+#else
+    /* Reset Sector Number for Bank2 */
+    FLASH->CR2 &= ~(FLASH_CR_SNB);
+
+    FLASH->CR2 |= (FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START);
+#endif /* FLASH_CR_PSIZE */
+  }
+}
+
+/**
+  * @brief  Enable the write protection of the desired bank1 or bank 2 sectors
+  * @param  WRPSector specifies the sector(s) to be write protected.
+  *          This parameter can be one of the following values:
+  *            @arg WRPSector:  A combination of OB_WRP_SECTOR_0 to OB_WRP_SECTOR_7 or OB_WRP_SECTOR_All
+  *
+  * @param  Banks the specific bank to apply WRP sectors
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: enable WRP on specified bank1 sectors
+  *            @arg FLASH_BANK_2: enable WRP on specified bank2 sectors
+  *            @arg FLASH_BANK_BOTH: enable WRP on both bank1 and bank2 specified sectors
+  *
+  * @retval HAL FLASH State
+  */
+static void FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
+{
+  /* Check the parameters */
+  assert_param(IS_OB_WRP_SECTOR(WRPSector));
+  assert_param(IS_FLASH_BANK(Banks));
+
+  if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
+  {
+    /* Enable Write Protection for bank 1 */
+    FLASH->WPSN_PRG1 &= (~(WRPSector & FLASH_WPSN_WRPSN));
+  }
+
+  if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
+  {
+    /* Enable Write Protection for bank 2 */
+    FLASH->WPSN_PRG2 &= (~(WRPSector & FLASH_WPSN_WRPSN));
+  }
+}
+
+/**
+  * @brief  Disable the write protection of the desired bank1 or bank 2 sectors
+  * @param  WRPSector specifies the sector(s) to disable write protection.
+  *          This parameter can be one of the following values:
+  *            @arg WRPSector:  A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_All
+  *
+  * @param  Banks the specific bank to apply WRP sectors
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: disable WRP on specified bank1 sectors
+  *            @arg FLASH_BANK_2: disable WRP on specified bank2 sectors
+  *            @arg FLASH_BANK_BOTH: disable WRP on both bank1 and bank2 specified sectors
+  *
+  * @retval HAL FLASH State
+  */
+static void FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)
+{
+  /* Check the parameters */
+  assert_param(IS_OB_WRP_SECTOR(WRPSector));
+  assert_param(IS_FLASH_BANK(Banks));
+
+  if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
+  {
+    /* Disable Write Protection for bank 1 */
+    FLASH->WPSN_PRG1 |= (WRPSector & FLASH_WPSN_WRPSN);
+  }
+
+  if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
+  {
+    /* Disable Write Protection for bank 2 */
+    FLASH->WPSN_PRG2 |= (WRPSector & FLASH_WPSN_WRPSN);
+  }
+}
+
+/**
+  * @brief  Get the write protection of the given bank 1 or bank 2 sectors
+  * @param  WRPState gives the write protection state on the given bank.
+  *          This parameter can be one of the following values:
+  *          @arg WRPState: OB_WRPSTATE_DISABLE or OB_WRPSTATE_ENABLE
+
+  * @param  WRPSector gives the write protected sector(s) on the given bank .
+  *          This parameter can be one of the following values:
+  *          @arg WRPSector: A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_All
+  *
+  * @param  Bank the specific bank to apply WRP sectors
+  *          This parameter can be exclusively one of the following values:
+  *            @arg FLASH_BANK_1: Get bank1 WRP sectors
+  *            @arg FLASH_BANK_2: Get bank2 WRP sectors
+  *            @arg FLASH_BANK_BOTH: note allowed in this functions
+  *
+  * @retval HAL FLASH State
+  */
+static void FLASH_OB_GetWRP(uint32_t *WRPState, uint32_t *WRPSector, uint32_t Bank)
+{
+  uint32_t regvalue = 0U;
+
+  if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_1)
+  {
+    regvalue = FLASH->WPSN_CUR1;
+  }
+
+  if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_2)
+  {
+    regvalue = FLASH->WPSN_CUR2;
+  }
+
+  (*WRPSector) = (~regvalue) & FLASH_WPSN_WRPSN;
+
+  if(*WRPSector == 0U)
+  {
+    (*WRPState) = OB_WRPSTATE_DISABLE;
+  }
+  else
+  {
+    (*WRPState) = OB_WRPSTATE_ENABLE;
+  }
+}
+
+/**
+  * @brief  Set the read protection level.
+  *
+  * @note   To configure the RDP level, the option lock bit OPTLOCK must be
+  *         cleared with the call of the HAL_FLASH_OB_Unlock() function.
+  * @note   To validate the RDP level, the option bytes must be reloaded
+  *         through the call of the HAL_FLASH_OB_Launch() function.
+  * @note   !!! Warning : When enabling OB_RDP level 2 it's no more possible
+  *         to go back to level 1 or 0 !!!
+  *
+  * @param  RDPLevel specifies the read protection level.
+  *         This parameter can be one of the following values:
+  *            @arg OB_RDP_LEVEL_0: No protection
+  *            @arg OB_RDP_LEVEL_1: Read protection of the memory
+  *            @arg OB_RDP_LEVEL_2: Full chip protection
+  *
+  * @retval HAL status
+  */
+static void FLASH_OB_RDPConfig(uint32_t RDPLevel)
+{
+  /* Check the parameters */
+  assert_param(IS_OB_RDP_LEVEL(RDPLevel));
+
+  /* Configure the RDP level in the option bytes register */
+  MODIFY_REG(FLASH->OPTSR_PRG, FLASH_OPTSR_RDP, RDPLevel);
+}
+
+/**
+  * @brief  Get the read protection level.
+  * @retval RDPLevel specifies the read protection level.
+  *         This return value can be one of the following values:
+  *            @arg OB_RDP_LEVEL_0: No protection
+  *            @arg OB_RDP_LEVEL_1: Read protection of the memory
+  *            @arg OB_RDP_LEVEL_2: Full chip protection
+  */
+static uint32_t FLASH_OB_GetRDP(void)
+{
+  uint32_t rdp_level = READ_BIT(FLASH->OPTSR_CUR, FLASH_OPTSR_RDP);
+  
+  if ((rdp_level != OB_RDP_LEVEL_0) && (rdp_level != OB_RDP_LEVEL_2))
+  {
+    return (OB_RDP_LEVEL_1);
+  }
+  else
+  {
+    return rdp_level;
+  }
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Program the FLASH User Option Byte.
+  *
+  * @note   To configure the user option bytes, the option lock bit OPTLOCK must
+  *         be cleared with the call of the HAL_FLASH_OB_Unlock() function.
+  *
+  * @note   To validate the user option bytes, the option bytes must be reloaded
+  *         through the call of the HAL_FLASH_OB_Launch() function.
+  *
+  * @param  UserType The FLASH User Option Bytes to be modified :
+  *                   a combination of @ref FLASHEx_OB_USER_Type
+  *
+  * @param  UserConfig The FLASH User Option Bytes values:
+  *         IWDG1_SW(Bit4), IWDG2_SW(Bit 5), nRST_STOP_D1(Bit 6), nRST_STDY_D1(Bit 7),
+  *         FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]),
+  *         SECURITY(Bit 21), BCM4(Bit 22), BCM7(Bit 23), nRST_STOP_D2(Bit 24),
+  *         nRST_STDY_D2(Bit 25), IO_HSLV (Bit 29) and SWAP_BANK_OPT(Bit 31).
+  *
+  * @retval HAL status
+  */
+#else
+/**
+  * @brief  Program the FLASH User Option Byte.
+  *
+  * @note   To configure the user option bytes, the option lock bit OPTLOCK must
+  *         be cleared with the call of the HAL_FLASH_OB_Unlock() function.
+  *
+  * @note   To validate the user option bytes, the option bytes must be reloaded
+  *         through the call of the HAL_FLASH_OB_Launch() function.
+  *
+  * @param  UserType The FLASH User Option Bytes to be modified :
+  *                   a combination of @arg FLASHEx_OB_USER_Type
+  *
+  * @param  UserConfig The FLASH User Option Bytes values:
+  *         IWDG_SW(Bit4), nRST_STOP_D1(Bit 6), nRST_STDY_D1(Bit 7),
+  *         FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]),
+  *         SECURITY(Bit 21), IO_HSLV (Bit 29) and SWAP_BANK_OPT(Bit 31).
+  *
+  * @retval HAL status
+  */
+#endif /*DUAL_CORE*/
+static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig)
+{
+  uint32_t optr_reg_val = 0;
+  uint32_t optr_reg_mask = 0;
+
+  /* Check the parameters */
+  assert_param(IS_OB_USER_TYPE(UserType));
+
+  if((UserType & OB_USER_IWDG1_SW) != 0U)
+  {
+    /* IWDG_HW option byte should be modified */
+    assert_param(IS_OB_IWDG1_SOURCE(UserConfig & FLASH_OPTSR_IWDG1_SW));
+
+    /* Set value and mask for IWDG_HW option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_IWDG1_SW);
+    optr_reg_mask |= FLASH_OPTSR_IWDG1_SW;
+  }
+#if defined(DUAL_CORE)
+  if((UserType & OB_USER_IWDG2_SW) != 0U)
+  {
+    /* IWDG2_SW option byte should be modified */
+    assert_param(IS_OB_IWDG2_SOURCE(UserConfig & FLASH_OPTSR_IWDG2_SW));
+
+    /* Set value and mask for IWDG2_SW option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_IWDG2_SW);
+    optr_reg_mask |= FLASH_OPTSR_IWDG2_SW;
+  }
+#endif /*DUAL_CORE*/
+  if((UserType & OB_USER_NRST_STOP_D1) != 0U)
+  {
+    /* NRST_STOP option byte should be modified */
+    assert_param(IS_OB_STOP_D1_RESET(UserConfig & FLASH_OPTSR_NRST_STOP_D1));
+
+    /* Set value and mask for NRST_STOP option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STOP_D1);
+    optr_reg_mask |= FLASH_OPTSR_NRST_STOP_D1;
+  }
+
+  if((UserType & OB_USER_NRST_STDBY_D1) != 0U)
+  {
+    /* NRST_STDBY option byte should be modified */
+    assert_param(IS_OB_STDBY_D1_RESET(UserConfig & FLASH_OPTSR_NRST_STBY_D1));
+
+    /* Set value and mask for NRST_STDBY option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STBY_D1);
+    optr_reg_mask |= FLASH_OPTSR_NRST_STBY_D1;
+  }
+
+  if((UserType & OB_USER_IWDG_STOP) != 0U)
+  {
+    /* IWDG_STOP option byte should be modified */
+    assert_param(IS_OB_USER_IWDG_STOP(UserConfig & FLASH_OPTSR_FZ_IWDG_STOP));
+
+    /* Set value and mask for IWDG_STOP option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_FZ_IWDG_STOP);
+    optr_reg_mask |= FLASH_OPTSR_FZ_IWDG_STOP;
+  }
+
+  if((UserType & OB_USER_IWDG_STDBY) != 0U)
+  {
+    /* IWDG_STDBY option byte should be modified */
+    assert_param(IS_OB_USER_IWDG_STDBY(UserConfig & FLASH_OPTSR_FZ_IWDG_SDBY));
+
+    /* Set value and mask for IWDG_STDBY option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_FZ_IWDG_SDBY);
+    optr_reg_mask |= FLASH_OPTSR_FZ_IWDG_SDBY;
+  }
+
+  if((UserType & OB_USER_ST_RAM_SIZE) != 0U)
+  {
+    /* ST_RAM_SIZE option byte should be modified */
+    assert_param(IS_OB_USER_ST_RAM_SIZE(UserConfig & FLASH_OPTSR_ST_RAM_SIZE));
+
+    /* Set value and mask for ST_RAM_SIZE option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_ST_RAM_SIZE);
+    optr_reg_mask |= FLASH_OPTSR_ST_RAM_SIZE;
+  }
+
+  if((UserType & OB_USER_SECURITY) != 0U)
+  {
+    /* SECURITY option byte should be modified */
+    assert_param(IS_OB_USER_SECURITY(UserConfig & FLASH_OPTSR_SECURITY));
+
+    /* Set value and mask for SECURITY option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_SECURITY);
+    optr_reg_mask |= FLASH_OPTSR_SECURITY;
+  }
+
+#if defined(DUAL_CORE)
+  if((UserType & OB_USER_BCM4) != 0U)
+  {
+    /* BCM4 option byte should be modified */
+    assert_param(IS_OB_USER_BCM4(UserConfig & FLASH_OPTSR_BCM4));
+
+    /* Set value and mask for BCM4 option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_BCM4);
+    optr_reg_mask |= FLASH_OPTSR_BCM4;
+  }
+
+  if((UserType & OB_USER_BCM7) != 0U)
+  {
+    /* BCM7 option byte should be modified */
+    assert_param(IS_OB_USER_BCM7(UserConfig & FLASH_OPTSR_BCM7));
+
+    /* Set value and mask for BCM7 option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_BCM7);
+    optr_reg_mask |= FLASH_OPTSR_BCM7;
+  }
+
+  if((UserType & OB_USER_NRST_STOP_D2) != 0U)
+  {
+    /* NRST_STOP option byte should be modified */
+    assert_param(IS_OB_STOP_D2_RESET(UserConfig & FLASH_OPTSR_NRST_STOP_D2));
+
+    /* Set value and mask for NRST_STOP option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STOP_D2);
+    optr_reg_mask |= FLASH_OPTSR_NRST_STOP_D2;
+  }
+
+  if((UserType & OB_USER_NRST_STDBY_D2) != 0U)
+  {
+    /* NRST_STDBY option byte should be modified */
+    assert_param(IS_OB_STDBY_D2_RESET(UserConfig & FLASH_OPTSR_NRST_STBY_D2));
+
+    /* Set value and mask for NRST_STDBY option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STBY_D2);
+    optr_reg_mask |= FLASH_OPTSR_NRST_STBY_D2;
+  }
+#endif /* DUAL_CORE */
+  if((UserType & OB_USER_SWAP_BANK) != 0U)
+  {
+    /* SWAP_BANK_OPT option byte should be modified */
+    assert_param(IS_OB_USER_SWAP_BANK(UserConfig & FLASH_OPTSR_SWAP_BANK_OPT));
+
+    /* Set value and mask for SWAP_BANK_OPT option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_SWAP_BANK_OPT);
+    optr_reg_mask |= FLASH_OPTSR_SWAP_BANK_OPT;
+  }
+
+  if((UserType & OB_USER_IOHSLV) != 0U)
+  {
+    /* IOHSLV_OPT option byte should be modified */
+    assert_param(IS_OB_USER_IOHSLV(UserConfig & FLASH_OPTSR_IO_HSLV));
+
+    /* Set value and mask for IOHSLV_OPT option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_IO_HSLV);
+    optr_reg_mask |= FLASH_OPTSR_IO_HSLV;
+  }
+
+#if defined (FLASH_OPTSR_VDDMMC_HSLV)
+  if((UserType & OB_USER_VDDMMC_HSLV) != 0U)
+  {
+    /* VDDMMC_HSLV option byte should be modified */
+    assert_param(IS_OB_USER_VDDMMC_HSLV(UserConfig & FLASH_OPTSR_VDDMMC_HSLV));
+
+    /* Set value and mask for VDDMMC_HSLV option byte */
+    optr_reg_val |= (UserConfig & FLASH_OPTSR_VDDMMC_HSLV);
+    optr_reg_mask |= FLASH_OPTSR_VDDMMC_HSLV;
+  }
+#endif /* FLASH_OPTSR_VDDMMC_HSLV */
+
+  /* Configure the option bytes register */
+  MODIFY_REG(FLASH->OPTSR_PRG, optr_reg_mask, optr_reg_val);
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Return the FLASH User Option Byte value.
+  * @retval The FLASH User Option Bytes values
+  *         IWDG1_SW(Bit4), IWDG2_SW(Bit 5), nRST_STOP_D1(Bit 6), nRST_STDY_D1(Bit 7),
+  *         FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]),
+  *         SECURITY(Bit 21), BCM4(Bit 22), BCM7(Bit 23), nRST_STOP_D2(Bit 24),
+  *         nRST_STDY_D2(Bit 25), IO_HSLV (Bit 29) and SWAP_BANK_OPT(Bit 31).
+  */
+#else
+/**
+  * @brief  Return the FLASH User Option Byte value.
+  * @retval The FLASH User Option Bytes values
+  *         IWDG_SW(Bit4), nRST_STOP_D1(Bit 6), nRST_STDY_D1(Bit 7),
+  *         FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]),
+  *         SECURITY(Bit 21), IO_HSLV (Bit 29) and SWAP_BANK_OPT(Bit 31).
+  */
+#endif /*DUAL_CORE*/
+static uint32_t FLASH_OB_GetUser(void)
+{
+  uint32_t userConfig = READ_REG(FLASH->OPTSR_CUR);
+  userConfig &= (~(FLASH_OPTSR_BOR_LEV | FLASH_OPTSR_RDP));
+
+  return userConfig;
+}
+
+/**
+  * @brief  Configure the Proprietary code readout protection of the desired addresses
+  *
+  * @note   To configure the PCROP options, the option lock bit OPTLOCK must be
+  *         cleared with the call of the HAL_FLASH_OB_Unlock() function.
+  * @note   To validate the PCROP options, the option bytes must be reloaded
+  *         through the call of the HAL_FLASH_OB_Launch() function.
+  *
+  * @param  PCROPConfig specifies if the PCROP area for the given Bank shall be erased or not
+  *         when RDP level decreased from Level 1 to Level 0, or after a bank erase with protection removal
+  *         This parameter must be a value of @arg FLASHEx_OB_PCROP_RDP enumeration
+  *
+  * @param  PCROPStartAddr specifies the start address of the Proprietary code readout protection
+  *          This parameter can be an address between begin and end of the bank
+  *
+  * @param  PCROPEndAddr specifies the end address of the Proprietary code readout protection
+  *          This parameter can be an address between PCROPStartAddr and end of the bank
+  *
+  * @param  Banks the specific bank to apply PCROP protection
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: PCROP on specified bank1 area
+  *            @arg FLASH_BANK_2: PCROP on specified bank2 area
+  *            @arg FLASH_BANK_BOTH: PCROP on specified bank1 and bank2 area (same config will be applied on both banks)
+  *
+  * @retval None
+  */
+static void FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr, uint32_t Banks)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_BANK(Banks));
+  assert_param(IS_OB_PCROP_RDP(PCROPConfig));
+
+  if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
+  {
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(PCROPStartAddr));
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(PCROPEndAddr));
+
+    /* Configure the Proprietary code readout protection */
+    FLASH->PRAR_PRG1 = ((PCROPStartAddr - FLASH_BANK1_BASE) >> 8)                                 | \
+                       (((PCROPEndAddr - FLASH_BANK1_BASE) >> 8) << FLASH_PRAR_PROT_AREA_END_Pos) | \
+                       PCROPConfig;
+  }
+
+  if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
+  {
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(PCROPStartAddr));
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(PCROPEndAddr));
+
+    /* Configure the Proprietary code readout protection */
+    FLASH->PRAR_PRG2 = ((PCROPStartAddr - FLASH_BANK2_BASE) >> 8)                                 | \
+                       (((PCROPEndAddr - FLASH_BANK2_BASE) >> 8) << FLASH_PRAR_PROT_AREA_END_Pos) | \
+                       PCROPConfig;
+  }
+}
+
+/**
+  * @brief  Get the Proprietary code readout protection configuration on a given Bank
+  *
+  * @param  PCROPConfig indicates if the PCROP area for the given Bank shall be erased or not
+  *         when RDP level decreased from Level 1 to Level 0 or after a bank erase with protection removal
+  *
+  * @param  PCROPStartAddr gives the start address of the Proprietary code readout protection of the bank
+  *
+  * @param  PCROPEndAddr gives the end address of the Proprietary code readout protection of the bank
+  *
+  * @param  Bank the specific bank to apply PCROP protection
+  *          This parameter can be exclusively one of the following values:
+  *            @arg FLASH_BANK_1: PCROP on specified bank1 area
+  *            @arg FLASH_BANK_2: PCROP on specified bank2 area
+  *            @arg FLASH_BANK_BOTH: is  not allowed here
+  *
+  * @retval None
+  */
+static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROPStartAddr, uint32_t *PCROPEndAddr, uint32_t Bank)
+{
+  uint32_t regvalue = 0;
+  uint32_t bankBase = 0;
+
+  if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_1)
+  {
+    regvalue = FLASH->PRAR_CUR1;
+    bankBase = FLASH_BANK1_BASE;
+  }
+
+  if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_2)
+  {
+    regvalue = FLASH->PRAR_CUR2;
+    bankBase = FLASH_BANK2_BASE;
+  }
+
+  (*PCROPConfig) =  (regvalue & FLASH_PRAR_DMEP);
+
+  (*PCROPStartAddr) = ((regvalue & FLASH_PRAR_PROT_AREA_START) << 8) + bankBase;
+  (*PCROPEndAddr) = (regvalue & FLASH_PRAR_PROT_AREA_END) >> FLASH_PRAR_PROT_AREA_END_Pos;
+  (*PCROPEndAddr) = ((*PCROPEndAddr) << 8) + bankBase;
+}
+
+/**
+  * @brief  Set the BOR Level.
+  * @param  Level specifies the Option Bytes BOR Reset Level.
+  *          This parameter can be one of the following values:
+  *            @arg OB_BOR_LEVEL0: Reset level threshold is set to 1.6V
+  *            @arg OB_BOR_LEVEL1: Reset level threshold is set to 2.1V
+  *            @arg OB_BOR_LEVEL2: Reset level threshold is set to 2.4V
+  *            @arg OB_BOR_LEVEL3: Reset level threshold is set to 2.7V
+  * @retval None
+  */
+static void FLASH_OB_BOR_LevelConfig(uint32_t Level)
+{
+  assert_param(IS_OB_BOR_LEVEL(Level));
+
+  /* Configure BOR_LEV option byte */
+  MODIFY_REG(FLASH->OPTSR_PRG, FLASH_OPTSR_BOR_LEV, Level);
+}
+
+/**
+  * @brief  Get the BOR Level.
+  * @retval The Option Bytes BOR Reset Level.
+  *            This parameter can be one of the following values:
+  *            @arg OB_BOR_LEVEL0: Reset level threshold is set to 1.6V
+  *            @arg OB_BOR_LEVEL1: Reset level threshold is set to 2.1V
+  *            @arg OB_BOR_LEVEL2: Reset level threshold is set to 2.4V
+  *            @arg OB_BOR_LEVEL3: Reset level threshold is set to 2.7V
+  */
+static uint32_t FLASH_OB_GetBOR(void)
+{
+  return (FLASH->OPTSR_CUR & FLASH_OPTSR_BOR_LEV);
+}
+
+/**
+  * @brief  Set Boot address
+  * @param  BootOption Boot address option byte to be programmed,
+  *                     This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION
+                        (OB_BOOT_ADD0, OB_BOOT_ADD1 or OB_BOOT_ADD_BOTH)
+  *
+  * @param  BootAddress0 Specifies the Boot Address 0
+  * @param  BootAddress1 Specifies the Boot Address 1
+  * @retval HAL Status
+  */
+static void FLASH_OB_BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1)
+{
+  /* Check the parameters */
+  assert_param(IS_OB_BOOT_ADD_OPTION(BootOption));
+
+  if((BootOption & OB_BOOT_ADD0) == OB_BOOT_ADD0)
+  {
+    /* Check the parameters */
+    assert_param(IS_BOOT_ADDRESS(BootAddress0));
+
+    /* Configure CM7 BOOT ADD0 */
+#if defined(DUAL_CORE)
+    MODIFY_REG(FLASH->BOOT7_PRG, FLASH_BOOT7_BCM7_ADD0, (BootAddress0 >> 16));
+#else /* Single Core*/
+    MODIFY_REG(FLASH->BOOT_PRG, FLASH_BOOT_ADD0, (BootAddress0 >> 16));
+#endif /* DUAL_CORE */
+  }
+
+  if((BootOption & OB_BOOT_ADD1) == OB_BOOT_ADD1)
+  {
+    /* Check the parameters */
+    assert_param(IS_BOOT_ADDRESS(BootAddress1));
+
+    /* Configure CM7 BOOT ADD1 */
+#if defined(DUAL_CORE)
+    MODIFY_REG(FLASH->BOOT7_PRG, FLASH_BOOT7_BCM7_ADD1, BootAddress1);
+#else /* Single Core*/
+    MODIFY_REG(FLASH->BOOT_PRG, FLASH_BOOT_ADD1, BootAddress1);
+#endif /* DUAL_CORE */
+  }
+}
+
+/**
+  * @brief  Get Boot address
+  * @param  BootAddress0 Specifies the Boot Address 0.
+  * @param  BootAddress1 Specifies the Boot Address 1.
+  * @retval HAL Status
+  */
+static void FLASH_OB_GetBootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1)
+{
+  uint32_t regvalue;
+
+#if defined(DUAL_CORE)
+  regvalue = FLASH->BOOT7_CUR;
+
+  (*BootAddress0) = (regvalue & FLASH_BOOT7_BCM7_ADD0) << 16;
+  (*BootAddress1) = (regvalue & FLASH_BOOT7_BCM7_ADD1);
+#else /* Single Core */
+  regvalue = FLASH->BOOT_CUR;
+
+  (*BootAddress0) = (regvalue & FLASH_BOOT_ADD0) << 16;
+  (*BootAddress1) = (regvalue & FLASH_BOOT_ADD1);
+#endif /* DUAL_CORE */
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Set CM4 Boot address
+  * @param  BootOption Boot address option byte to be programmed,
+  *                     This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION
+                        (OB_BOOT_ADD0, OB_BOOT_ADD1 or OB_BOOT_ADD_BOTH)
+  *
+  * @param  BootAddress0 Specifies the CM4 Boot Address 0.
+  * @param  BootAddress1 Specifies the CM4 Boot Address 1.
+  * @retval HAL Status
+  */
+static void FLASH_OB_CM4BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1)
+{
+  /* Check the parameters */
+  assert_param(IS_OB_BOOT_ADD_OPTION(BootOption));
+
+  if((BootOption & OB_BOOT_ADD0) == OB_BOOT_ADD0)
+  {
+    /* Check the parameters */
+    assert_param(IS_BOOT_ADDRESS(BootAddress0));
+
+    /* Configure CM4 BOOT ADD0 */
+    MODIFY_REG(FLASH->BOOT4_PRG, FLASH_BOOT4_BCM4_ADD0, (BootAddress0 >> 16));
+
+  }
+
+  if((BootOption & OB_BOOT_ADD1) == OB_BOOT_ADD1)
+  {
+    /* Check the parameters */
+    assert_param(IS_BOOT_ADDRESS(BootAddress1));
+
+    /* Configure CM4 BOOT ADD1 */
+    MODIFY_REG(FLASH->BOOT4_PRG, FLASH_BOOT4_BCM4_ADD1, BootAddress1);
+  }
+}
+
+/**
+  * @brief  Get CM4 Boot address
+  * @param  BootAddress0 Specifies the CM4 Boot Address 0.
+  * @param  BootAddress1 Specifies the CM4 Boot Address 1.
+  * @retval HAL Status
+  */
+static void FLASH_OB_GetCM4BootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1)
+{
+  uint32_t regvalue;
+
+  regvalue = FLASH->BOOT4_CUR;
+
+  (*BootAddress0) = (regvalue & FLASH_BOOT4_BCM4_ADD0) << 16;
+  (*BootAddress1) = (regvalue & FLASH_BOOT4_BCM4_ADD1);
+}
+#endif /*DUAL_CORE*/
+
+/**
+  * @brief  Set secure area configuration
+  * @param  SecureAreaConfig specify if the secure area will be deleted or not
+  *         when RDP level decreased from Level 1 to Level 0 or during a mass erase.
+  *
+  * @param  SecureAreaStartAddr Specifies the secure area start address
+  * @param  SecureAreaEndAddr Specifies the secure area end address
+  * @param  Banks the specific bank to apply Security protection
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: Secure area on specified bank1 area
+  *            @arg FLASH_BANK_2: Secure area on specified bank2 area
+  *            @arg FLASH_BANK_BOTH: Secure area on specified bank1 and bank2 area (same config will be applied on both banks)
+  * @retval None
+  */
+static void FLASH_OB_SecureAreaConfig(uint32_t SecureAreaConfig, uint32_t SecureAreaStartAddr, uint32_t SecureAreaEndAddr, uint32_t Banks)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_BANK(Banks));
+  assert_param(IS_OB_SECURE_RDP(SecureAreaConfig));
+
+  if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
+  {
+    /* Check the parameters */
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(SecureAreaStartAddr));
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(SecureAreaEndAddr));
+
+    /* Configure the secure area */
+    FLASH->SCAR_PRG1 = ((SecureAreaStartAddr - FLASH_BANK1_BASE) >> 8)                                | \
+                       (((SecureAreaEndAddr - FLASH_BANK1_BASE) >> 8) << FLASH_SCAR_SEC_AREA_END_Pos) | \
+                       (SecureAreaConfig & FLASH_SCAR_DMES);
+  }
+
+  if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
+  {
+    /* Check the parameters */
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(SecureAreaStartAddr));
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(SecureAreaEndAddr));
+
+    /* Configure the secure area */
+    FLASH->SCAR_PRG2 = ((SecureAreaStartAddr - FLASH_BANK2_BASE) >> 8)                                | \
+                       (((SecureAreaEndAddr - FLASH_BANK2_BASE) >> 8) << FLASH_SCAR_SEC_AREA_END_Pos) | \
+                       (SecureAreaConfig & FLASH_SCAR_DMES);
+  }
+}
+
+/**
+  * @brief  Get secure area configuration
+  * @param  SecureAreaConfig indicates if the secure area will be deleted or not
+  *         when RDP level decreased from Level 1 to Level 0 or during a mass erase.
+  * @param  SecureAreaStartAddr gives the secure area start address
+  * @param  SecureAreaEndAddr gives the secure area end address
+  * @param  Bank Specifies the Bank
+  * @retval None
+  */
+static void FLASH_OB_GetSecureArea(uint32_t *SecureAreaConfig, uint32_t *SecureAreaStartAddr, uint32_t *SecureAreaEndAddr, uint32_t Bank)
+{
+  uint32_t regvalue = 0;
+  uint32_t bankBase = 0;
+
+  /* Check Bank parameter value */
+  if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_1)
+  {
+    regvalue = FLASH->SCAR_CUR1;
+    bankBase = FLASH_BANK1_BASE;
+  }
+
+  if((Bank & FLASH_BANK_BOTH) == FLASH_BANK_2)
+  {
+    regvalue = FLASH->SCAR_CUR2;
+    bankBase = FLASH_BANK2_BASE;
+  }
+
+  /* Get the secure area settings */
+  (*SecureAreaConfig) = (regvalue & FLASH_SCAR_DMES);
+  (*SecureAreaStartAddr) = ((regvalue & FLASH_SCAR_SEC_AREA_START) << 8) + bankBase;
+  (*SecureAreaEndAddr) = (regvalue & FLASH_SCAR_SEC_AREA_END) >> FLASH_SCAR_SEC_AREA_END_Pos;
+  (*SecureAreaEndAddr) = ((*SecureAreaEndAddr) << 8) + bankBase;
+}
+
+/**
+  * @brief  Add a CRC sector to the list of sectors on which the CRC will be calculated
+  * @param  Sector Specifies the CRC sector number
+  * @param  Bank Specifies the Bank
+  * @retval None
+  */
+static void FLASH_CRC_AddSector(uint32_t Sector, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_SECTOR(Sector));
+
+  if (Bank == FLASH_BANK_1)
+  {
+    /* Clear CRC sector */
+    FLASH->CRCCR1 &= (~FLASH_CRCCR_CRC_SECT);
+
+    /* Select CRC Sector and activate ADD_SECT bit */
+    FLASH->CRCCR1 |= Sector | FLASH_CRCCR_ADD_SECT;
+  }
+  else
+  {
+    /* Clear CRC sector */
+    FLASH->CRCCR2 &= (~FLASH_CRCCR_CRC_SECT);
+
+    /* Select CRC Sector and activate ADD_SECT bit */
+    FLASH->CRCCR2 |= Sector | FLASH_CRCCR_ADD_SECT;
+  }
+}
+
+/**
+  * @brief  Select CRC start and end memory addresses on which the CRC will be calculated
+  * @param  CRCStartAddr Specifies the CRC start address
+  * @param  CRCEndAddr Specifies the CRC end address
+  * @param  Bank Specifies the Bank
+  * @retval None
+  */
+static void FLASH_CRC_SelectAddress(uint32_t CRCStartAddr, uint32_t CRCEndAddr, uint32_t Bank)
+{
+  if (Bank == FLASH_BANK_1)
+  {
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(CRCStartAddr));
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(CRCEndAddr));
+
+    /* Write CRC Start and End addresses */
+    FLASH->CRCSADD1 = CRCStartAddr;
+    FLASH->CRCEADD1 = CRCEndAddr;
+  }
+  else
+  {
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(CRCStartAddr));
+    assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(CRCEndAddr));
+
+    /* Write CRC Start and End addresses */
+    FLASH->CRCSADD2 = CRCStartAddr;
+    FLASH->CRCEADD2 = CRCEndAddr;
+  }
+}
+/**
+  * @}
+  */
+
+#if defined (FLASH_OTPBL_LOCKBL)
+/**
+  * @brief  Configure the OTP Block Lock.
+  * @param  OTP_Block specifies the OTP Block to lock.
+  *         This parameter can be a value of @ref FLASHEx_OTP_Blocks
+  * @retval None
+  */
+static void FLASH_OB_OTP_LockConfig(uint32_t OTP_Block)
+{
+  /* Check the parameters */
+  assert_param(IS_OTP_BLOCK(OTP_Block));
+
+  /* Configure the OTP Block lock in the option bytes register */
+  FLASH->OTPBL_PRG |= (OTP_Block & FLASH_OTPBL_LOCKBL);
+}
+
+/**
+  * @brief  Get the OTP Block Lock.
+  * @retval OTP_Block specifies the OTP Block to lock.
+  *         This return value can be a value of @ref FLASHEx_OTP_Blocks
+  */
+static uint32_t FLASH_OB_OTP_GetLock(void)
+{
+  return (FLASH->OTPBL_CUR);
+}
+#endif /* FLASH_OTPBL_LOCKBL */
+
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c
new file mode 100644
index 00000000..13dcc40d
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c
@@ -0,0 +1,560 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_gpio.c
+  * @author  MCD Application Team
+  * @brief   GPIO HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *
+  @verbatim
+  ==============================================================================
+                    ##### GPIO Peripheral features #####
+  ==============================================================================
+  [..]
+    (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
+        configured by software in several modes:
+        (++) Input mode
+        (++) Analog mode
+        (++) Output mode
+        (++) Alternate function mode
+        (++) External interrupt/event lines
+
+    (+) During and just after reset, the alternate functions and external interrupt
+        lines are not active and the I/O ports are configured in input floating mode.
+
+    (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
+        activated or not.
+
+    (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
+        type and the IO speed can be selected depending on the VDD value.
+
+    (+) The microcontroller IO pins are connected to onboard peripherals/modules through a
+        multiplexer that allows only one peripheral alternate function (AF) connected
+       to an IO pin at a time. In this way, there can be no conflict between peripherals
+       sharing the same IO pin.
+
+    (+) All ports have external interrupt/event capability. To use external interrupt
+        lines, the port must be configured in input mode. All available GPIO pins are
+        connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
+
+  The external interrupt/event controller consists of up to 23 edge detectors
+        (16 lines are connected to GPIO) for generating event/interrupt requests (each
+        input line can be independently configured to select the type (interrupt or event)
+        and the corresponding trigger event (rising or falling or both). Each line can
+        also be masked independently.
+
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
+
+    (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
+        (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
+        (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
+             structure.
+        (++) In case of Output or alternate function mode selection: the speed is
+             configured through "Speed" member from GPIO_InitTypeDef structure.
+        (++) In alternate mode is selection, the alternate function connected to the IO
+             is configured through "Alternate" member from GPIO_InitTypeDef structure.
+        (++) Analog mode is required when a pin is to be used as ADC channel
+             or DAC output.
+        (++) In case of external interrupt/event selection the "Mode" member from
+             GPIO_InitTypeDef structure select the type (interrupt or event) and
+             the corresponding trigger event (rising or falling or both).
+
+    (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
+        mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
+        HAL_NVIC_EnableIRQ().
+
+    (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
+
+    (#) To set/reset the level of a pin configured in output mode use
+        HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
+
+   (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
+
+
+    (#) During and just after reset, the alternate functions are not
+        active and the GPIO pins are configured in input floating mode (except JTAG
+        pins).
+
+    (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
+        (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
+        priority over the GPIO function.
+
+    (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
+        general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
+        The HSE has priority over the GPIO function.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup GPIO  GPIO
+  * @brief GPIO HAL module driver
+  * @{
+  */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines ------------------------------------------------------------*/
+/** @addtogroup GPIO_Private_Constants GPIO Private Constants
+  * @{
+  */
+#define GPIO_MODE             (0x00000003U)
+#define ANALOG_MODE           (0x00000008U)
+#define EXTI_MODE             (0x10000000U)
+#define GPIO_MODE_IT          (0x00010000U)
+#define GPIO_MODE_EVT         (0x00020000U)
+#define RISING_EDGE           (0x00100000U)
+#define FALLING_EDGE          (0x00200000U)
+#define GPIO_OUTPUT_TYPE      (0x00000010U)
+
+#if defined(DUAL_CORE)
+#define EXTI_CPU1             (0x01000000U)
+#define EXTI_CPU2             (0x02000000U)
+#endif /*DUAL_CORE*/
+#define GPIO_NUMBER           (16U)
+/**
+  * @}
+  */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
+  * @{
+  */
+
+/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+  [..]
+    This section provides functions allowing to initialize and de-initialize the GPIOs
+    to be ready for use.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
+  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral.
+  * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
+  *         the configuration information for the specified GPIO peripheral.
+  * @retval None
+  */
+void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
+{
+  uint32_t position = 0x00U;
+  uint32_t iocurrent;
+  uint32_t temp;
+  EXTI_Core_TypeDef *EXTI_CurrentCPU;
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */
+#else
+  EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */
+#endif
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
+  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
+  assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
+
+  /* Configure the port pins */
+  while (((GPIO_Init->Pin) >> position) != 0x00U)
+  {
+    /* Get current io position */
+    iocurrent = (GPIO_Init->Pin) & (1UL << position);
+
+    if (iocurrent != 0x00U)
+    {
+      /*--------------------- GPIO Mode Configuration ------------------------*/
+      /* In case of Output or Alternate function mode selection */
+      if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
+          (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+      {
+        /* Check the Speed parameter */
+        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+        /* Configure the IO Speed */
+        temp = GPIOx->OSPEEDR;
+        temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
+        temp |= (GPIO_Init->Speed << (position * 2U));
+        GPIOx->OSPEEDR = temp;
+
+        /* Configure the IO Output Type */
+        temp = GPIOx->OTYPER;
+        temp &= ~(GPIO_OTYPER_OT0 << position) ;
+        temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
+        GPIOx->OTYPER = temp;
+      }
+
+      /* Activate the Pull-up or Pull down resistor for the current IO */
+      temp = GPIOx->PUPDR;
+      temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
+      temp |= ((GPIO_Init->Pull) << (position * 2U));
+      GPIOx->PUPDR = temp;
+
+      /* In case of Alternate function mode selection */
+      if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+      {
+        /* Check the Alternate function parameters */
+        assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
+        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
+
+        /* Configure Alternate function mapped with the current IO */
+        temp = GPIOx->AFR[position >> 3U];
+        temp &= ~(0xFU << ((position & 0x07U) * 4U));
+        temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
+        GPIOx->AFR[position >> 3U] = temp;
+      }
+
+      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+      temp = GPIOx->MODER;
+      temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
+      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
+      GPIOx->MODER = temp;
+
+      /*--------------------- EXTI Mode Configuration ------------------------*/
+      /* Configure the External Interrupt or event for the current IO */
+      if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
+      {
+        /* Enable SYSCFG Clock */
+        __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+        temp = SYSCFG->EXTICR[position >> 2U];
+        temp &= ~(0x0FUL << (4U * (position & 0x03U)));
+        temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
+        SYSCFG->EXTICR[position >> 2U] = temp;
+
+        /* Clear EXTI line configuration */
+        temp = EXTI_CurrentCPU->IMR1;
+        temp &= ~(iocurrent);
+        if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
+        {
+          temp |= iocurrent;
+        }
+        EXTI_CurrentCPU->IMR1 = temp;
+
+        temp = EXTI_CurrentCPU->EMR1;
+        temp &= ~(iocurrent);
+        if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
+        {
+          temp |= iocurrent;
+        }
+        EXTI_CurrentCPU->EMR1 = temp;
+
+        /* Clear Rising Falling edge configuration */
+        temp = EXTI->RTSR1;
+        temp &= ~(iocurrent);
+        if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
+        {
+          temp |= iocurrent;
+        }
+        EXTI->RTSR1 = temp;
+
+        temp = EXTI->FTSR1;
+        temp &= ~(iocurrent);
+        if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
+        {
+          temp |= iocurrent;
+        }
+        EXTI->FTSR1 = temp;
+      }
+    }
+
+    position++;
+  }
+}
+
+/**
+  * @brief  De-initializes the GPIOx peripheral registers to their default reset values.
+  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bit to be written.
+  *          This parameter can be one of GPIO_PIN_x where x can be (0..15).
+  * @retval None
+  */
+void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
+{
+  uint32_t position = 0x00U;
+  uint32_t iocurrent;
+  uint32_t tmp;
+  EXTI_Core_TypeDef *EXTI_CurrentCPU;
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */
+#else
+  EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */
+#endif
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  /* Configure the port pins */
+  while ((GPIO_Pin >> position) != 0x00U)
+  {
+    /* Get current io position */
+    iocurrent = GPIO_Pin & (1UL << position) ;
+
+    if (iocurrent != 0x00U)
+    {
+      /*------------------------- EXTI Mode Configuration --------------------*/
+      /* Clear the External Interrupt or Event for the current IO */
+      tmp = SYSCFG->EXTICR[position >> 2U];
+      tmp &= (0x0FUL << (4U * (position & 0x03U)));
+      if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
+      {
+        /* Clear EXTI line configuration for Current CPU */
+        EXTI_CurrentCPU->IMR1 &= ~(iocurrent);
+        EXTI_CurrentCPU->EMR1 &= ~(iocurrent);
+
+        /* Clear Rising Falling edge configuration */
+        EXTI->RTSR1 &= ~(iocurrent);
+        EXTI->FTSR1 &= ~(iocurrent);
+
+        tmp = 0x0FUL << (4U * (position & 0x03U));
+        SYSCFG->EXTICR[position >> 2U] &= ~tmp;
+      }
+
+      /*------------------------- GPIO Mode Configuration --------------------*/
+      /* Configure IO in Analog Mode */
+      GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2U));
+
+      /* Configure the default Alternate Function in current IO */
+      GPIOx->AFR[position >> 3U] &= ~(0xFU << ((position & 0x07U) * 4U)) ;
+
+      /* Deactivate the Pull-up and Pull-down resistor for the current IO */
+      GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
+
+      /* Configure the default value IO Output Type */
+      GPIOx->OTYPER  &= ~(GPIO_OTYPER_OT0 << position) ;
+
+      /* Configure the default value for IO Speed */
+      GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
+    }
+
+    position++;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
+ *  @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
+ *
+@verbatim
+ ===============================================================================
+                       ##### IO operation functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Reads the specified input port pin.
+  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bit to read.
+  *         This parameter can be GPIO_PIN_x where x can be (0..15).
+  * @retval The input port pin value.
+  */
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+  GPIO_PinState bitstatus;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  if ((GPIOx->IDR & GPIO_Pin) != 0x00U)
+  {
+    bitstatus = GPIO_PIN_SET;
+  }
+  else
+  {
+    bitstatus = GPIO_PIN_RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Sets or clears the selected data port bit.
+  *
+  * @note   This function uses GPIOx_BSRR register to allow atomic read/modify
+  *         accesses. In this way, there is no risk of an IRQ occurring between
+  *         the read and the modify access.
+  *
+  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bit to be written.
+  *          This parameter can be one of GPIO_PIN_x where x can be (0..15).
+  * @param  PinState: specifies the value to be written to the selected bit.
+  *          This parameter can be one of the GPIO_PinState enum values:
+  *            @arg GPIO_PIN_RESET: to clear the port pin
+  *            @arg GPIO_PIN_SET: to set the port pin
+  * @retval None
+  */
+void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+  assert_param(IS_GPIO_PIN_ACTION(PinState));
+
+  if (PinState != GPIO_PIN_RESET)
+  {
+    GPIOx->BSRR = GPIO_Pin;
+  }
+  else
+  {
+    GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
+  }
+}
+
+/**
+  * @brief  Toggles the specified GPIO pins.
+  * @param  GPIOx: Where x can be (A..K) to select the GPIO peripheral.
+  * @param  GPIO_Pin: Specifies the pins to be toggled.
+  * @retval None
+  */
+void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  if ((GPIOx->ODR & GPIO_Pin) == GPIO_Pin)
+  {
+    GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
+  }
+  else
+  {
+    GPIOx->BSRR = GPIO_Pin;
+  }
+}
+
+/**
+  * @brief  Locks GPIO Pins configuration registers.
+  * @note   The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
+  *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
+  * @note   The configuration of the locked GPIO pins can no longer be modified
+  *         until the next reset.
+  * @param  GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32H7 family
+  * @param  GPIO_Pin: specifies the port bit to be locked.
+  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+  __IO uint32_t tmp = GPIO_LCKR_LCKK;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  /* Apply lock key write sequence */
+  tmp |= GPIO_Pin;
+  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+  GPIOx->LCKR = tmp;
+  /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
+  GPIOx->LCKR = GPIO_Pin;
+  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+  GPIOx->LCKR = tmp;
+  /* Read LCKK register. This read is mandatory to complete key lock sequence*/
+  tmp = GPIOx->LCKR;
+
+  /* read again in order to confirm lock is active */
+  if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00U)
+  {
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Handle EXTI interrupt request.
+  * @param  GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
+  * @retval None
+  */
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
+{
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  if (__HAL_GPIO_EXTID2_GET_IT(GPIO_Pin) != 0x00U)
+  {
+    __HAL_GPIO_EXTID2_CLEAR_IT(GPIO_Pin);
+    HAL_GPIO_EXTI_Callback(GPIO_Pin);
+  }
+#else
+  /* EXTI line interrupt detected */
+  if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00U)
+  {
+    __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
+    HAL_GPIO_EXTI_Callback(GPIO_Pin);
+  }
+#endif
+}
+
+/**
+  * @brief  EXTI line detection callback.
+  * @param  GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
+  * @retval None
+  */
+__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(GPIO_Pin);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+           the HAL_GPIO_EXTI_Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+#endif /* HAL_GPIO_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c
new file mode 100644
index 00000000..1fab0cef
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c
@@ -0,0 +1,441 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_hsem.c
+  * @author  MCD Application Team
+  * @brief   HSEM HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the semaphore peripheral:
+  *           + Semaphore Take function (2-Step Procedure) , non blocking
+  *           + Semaphore FastTake function (1-Step Procedure) , non blocking
+  *           + Semaphore Status check
+  *           + Semaphore Clear Key Set and Get
+  *           + Release and release all functions
+  *           + Semaphore notification enabling and disabling and callnack functions
+  *           + IRQ handler management
+  *
+  *
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+      (#)Take a semaphore In 2-Step mode Using function HAL_HSEM_Take. This function takes as parameters :
+           (++) the semaphore ID from 0 to 31
+           (++) the process ID from 0 to 255
+      (#) Fast Take semaphore In 1-Step mode Using function HAL_HSEM_FastTake. This function takes as parameter :
+           (++) the semaphore ID from 0_ID to 31. Note that the process ID value is implicitly assumed as zero
+      (#) Check if a semaphore is Taken using function HAL_HSEM_IsSemTaken. This function takes as parameter :
+          (++) the semaphore ID from 0_ID to 31
+          (++) It returns 1 if the given semaphore is taken otherwise (Free) zero
+      (#)Release a semaphore using function with HAL_HSEM_Release. This function takes as parameters :
+           (++) the semaphore ID from 0 to 31
+           (++) the process ID from 0 to 255:
+           (++) Note: If ProcessID and MasterID match, semaphore is freed, and an interrupt
+         may be generated when enabled (notification activated). If ProcessID or MasterID does not match,
+         semaphore remains taken (locked)
+
+      (#)Release all semaphores at once taken by a given Master using function HAL_HSEM_Release_All
+          This function takes as parameters :
+           (++) the Release Key (value from 0 to 0xFFFF) can be Set or Get respectively by
+              HAL_HSEM_SetClearKey() or HAL_HSEM_GetClearKey functions
+           (++) the Master ID:
+           (++) Note: If the Key and MasterID match, all semaphores taken by the given CPU that corresponds
+           to MasterID  will be freed, and an interrupt may be generated when enabled (notification activated). If the
+           Key or the MasterID doesn't match, semaphores remains taken (locked)
+
+      (#)Semaphores Release all key functions:
+         (++)  HAL_HSEM_SetClearKey() to set semaphore release all Key
+         (++)  HAL_HSEM_GetClearKey() to get release all Key
+      (#)Semaphores notification functions :
+         (++)  HAL_HSEM_ActivateNotification to activate a notification callback on
+               a given semaphores Mask (bitfield). When one or more semaphores defined by the mask are released
+               the callback HAL_HSEM_FreeCallback will be asserted giving as parameters a mask of the released
+               semaphores (bitfield).
+
+         (++)  HAL_HSEM_DeactivateNotification to deactivate the notification of a given semaphores Mask (bitfield).
+         (++) See the description of the macro __HAL_HSEM_SEMID_TO_MASK to check how to calculate a semaphore mask
+                Used by the notification functions
+     *** HSEM HAL driver macros list ***
+     =============================================
+     [..] Below the list of most used macros in HSEM HAL driver.
+
+      (+) __HAL_HSEM_SEMID_TO_MASK: Helper macro to convert a Semaphore ID to a Mask.
+      [..] Example of use :
+      [..] mask = __HAL_HSEM_SEMID_TO_MASK(8)  |  __HAL_HSEM_SEMID_TO_MASK(21) | __HAL_HSEM_SEMID_TO_MASK(25).
+      [..] All next macros take as parameter a semaphore Mask (bitfiled) that can be constructed using  __HAL_HSEM_SEMID_TO_MASK as the above example.
+      (+) __HAL_HSEM_ENABLE_IT: Enable the specified semaphores Mask interrupts.
+      (+) __HAL_HSEM_DISABLE_IT: Disable the specified semaphores Mask interrupts.
+      (+) __HAL_HSEM_GET_IT: Checks whether the specified semaphore interrupt has occurred or not.
+      (+) __HAL_HSEM_GET_FLAG: Get the semaphores status release flags.
+      (+) __HAL_HSEM_CLEAR_FLAG: Clear the semaphores status release flags.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup HSEM HSEM
+  * @brief HSEM HAL module driver
+  * @{
+  */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#if defined(DUAL_CORE)
+#ifndef HSEM_R_MASTERID
+#define HSEM_R_MASTERID HSEM_R_COREID
+#endif
+
+#ifndef HSEM_RLR_MASTERID
+#define HSEM_RLR_MASTERID HSEM_RLR_COREID
+#endif
+
+#ifndef HSEM_CR_MASTERID
+#define HSEM_CR_MASTERID HSEM_CR_COREID
+#endif
+#endif /* DUAL_CORE */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup HSEM_Exported_Functions  HSEM Exported Functions
+  * @{
+  */
+
+/** @defgroup HSEM_Exported_Functions_Group1 Take and Release functions
+  *  @brief    HSEM Take and Release functions
+  *
+@verbatim
+ ==============================================================================
+              ##### HSEM Take and Release functions #####
+ ==============================================================================
+[..] This section provides functions allowing to:
+      (+) Take a semaphore with 2 Step method
+      (+) Fast Take a semaphore with 1 Step method
+      (+) Check semaphore state Taken or not
+      (+) Release a semaphore
+      (+) Release all semaphore at once
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Take a semaphore in 2 Step mode.
+  * @param  SemID: semaphore ID from 0 to 31
+  * @param  ProcessID: Process ID from 0 to 255
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID)
+{
+  /* Check the parameters */
+  assert_param(IS_HSEM_SEMID(SemID));
+  assert_param(IS_HSEM_PROCESSID(ProcessID));
+
+#if  USE_MULTI_CORE_SHARED_CODE != 0U
+  /* First step  write R register with MasterID, processID and take bit=1*/
+  HSEM->R[SemID] = ((ProcessID & HSEM_R_PROCID) | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID) | HSEM_R_LOCK);
+
+  /* second step : read the R register . Take achieved if MasterID and processID match and take bit set to 1 */
+  if (HSEM->R[SemID] == ((ProcessID & HSEM_R_PROCID) | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID) | HSEM_R_LOCK))
+  {
+    /*take success when MasterID and ProcessID match and take bit set*/
+    return HAL_OK;
+  }
+#else
+  /* First step  write R register with MasterID, processID and take bit=1*/
+  HSEM->R[SemID] = (ProcessID | HSEM_CR_COREID_CURRENT | HSEM_R_LOCK);
+
+  /* second step : read the R register . Take achieved if MasterID and processID match and take bit set to 1 */
+  if (HSEM->R[SemID] == (ProcessID | HSEM_CR_COREID_CURRENT | HSEM_R_LOCK))
+  {
+    /*take success when MasterID and ProcessID match and take bit set*/
+    return HAL_OK;
+  }
+#endif
+
+  /* Semaphore take fails*/
+  return HAL_ERROR;
+}
+
+/**
+  * @brief  Fast Take a semaphore with 1 Step mode.
+  * @param  SemID: semaphore ID from 0 to 31
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HSEM_FastTake(uint32_t SemID)
+{
+  /* Check the parameters */
+  assert_param(IS_HSEM_SEMID(SemID));
+
+#if  USE_MULTI_CORE_SHARED_CODE != 0U
+  /* Read the RLR register to take the semaphore */
+  if (HSEM->RLR[SemID] == (((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_RLR_MASTERID) | HSEM_RLR_LOCK))
+  {
+    /*take success when MasterID match and take bit set*/
+    return HAL_OK;
+  }
+#else
+  /* Read the RLR register to take the semaphore */
+  if (HSEM->RLR[SemID] == (HSEM_CR_COREID_CURRENT | HSEM_RLR_LOCK))
+  {
+    /*take success when MasterID match and take bit set*/
+    return HAL_OK;
+  }
+#endif
+
+  /* Semaphore take fails */
+  return HAL_ERROR;
+}
+/**
+  * @brief  Check semaphore state Taken or not.
+  * @param  SemID: semaphore ID
+  * @retval HAL HSEM state
+  */
+uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID)
+{
+  return (((HSEM->R[SemID] & HSEM_R_LOCK) != 0U) ? 1UL : 0UL);
+}
+
+
+/**
+  * @brief  Release a semaphore.
+  * @param  SemID: semaphore ID from 0 to 31
+  * @param  ProcessID: Process ID from 0 to 255
+  * @retval None
+  */
+void  HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID)
+{
+  /* Check the parameters */
+  assert_param(IS_HSEM_SEMID(SemID));
+  assert_param(IS_HSEM_PROCESSID(ProcessID));
+
+  /* Clear the semaphore by writing to the R register : the MasterID , the processID and take bit = 0  */
+#if  USE_MULTI_CORE_SHARED_CODE != 0U
+  HSEM->R[SemID] = (ProcessID | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID));
+#else
+  HSEM->R[SemID] = (ProcessID | HSEM_CR_COREID_CURRENT);
+#endif
+
+}
+
+/**
+  * @brief  Release All semaphore used by a given Master .
+  * @param  Key: Semaphore Key , value from 0 to 0xFFFF
+  * @param  CoreID: CoreID of the CPU that is using semaphores to be released
+  * @retval None
+  */
+void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t CoreID)
+{
+  assert_param(IS_HSEM_KEY(Key));
+  assert_param(IS_HSEM_COREID(CoreID));
+
+  HSEM->CR = ((Key << HSEM_CR_KEY_Pos) | (CoreID << HSEM_CR_COREID_Pos));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HSEM_Exported_Functions_Group2 HSEM Set and Get Key functions
+  *  @brief    HSEM Set and Get Key functions.
+  *
+@verbatim
+  ==============================================================================
+              ##### HSEM Set and Get Key functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Set semaphore Key
+      (+) Get semaphore Key
+@endverbatim
+
+  * @{
+  */
+
+/**
+  * @brief  Set semaphore Key .
+  * @param  Key: Semaphore Key , value from 0 to 0xFFFF
+  * @retval None
+  */
+void  HAL_HSEM_SetClearKey(uint32_t Key)
+{
+  assert_param(IS_HSEM_KEY(Key));
+
+  MODIFY_REG(HSEM->KEYR, HSEM_KEYR_KEY, (Key << HSEM_KEYR_KEY_Pos));
+
+}
+
+/**
+  * @brief  Get semaphore Key .
+  * @retval Semaphore Key , value from 0 to 0xFFFF
+  */
+uint32_t HAL_HSEM_GetClearKey(void)
+{
+  return (HSEM->KEYR >> HSEM_KEYR_KEY_Pos);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HSEM_Exported_Functions_Group3 HSEM IRQ handler management
+  *  @brief    HSEM Notification functions.
+  *
+@verbatim
+  ==============================================================================
+      ##### HSEM IRQ handler management and Notification functions #####
+  ==============================================================================
+[..]  This section provides HSEM IRQ handler and Notification function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Activate Semaphore release Notification for a given Semaphores Mask .
+  * @param  SemMask: Mask of Released semaphores
+  * @retval Semaphore Key
+  */
+void HAL_HSEM_ActivateNotification(uint32_t SemMask)
+{
+#if  USE_MULTI_CORE_SHARED_CODE != 0U
+  /*enable the semaphore mask interrupts */
+  if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID)
+  {
+    /*Use interrupt line 0 for CPU1 Master */
+    HSEM->C1IER |= SemMask;
+  }
+  else /* HSEM_CPU2_COREID */
+  {
+    /*Use interrupt line 1 for CPU2 Master*/
+    HSEM->C2IER |= SemMask;
+  }
+#else
+  HSEM_COMMON->IER |= SemMask;
+#endif
+}
+
+/**
+  * @brief  Deactivate Semaphore release Notification for a given Semaphores Mask .
+  * @param  SemMask: Mask of Released semaphores
+  * @retval Semaphore Key
+  */
+void HAL_HSEM_DeactivateNotification(uint32_t SemMask)
+{
+#if  USE_MULTI_CORE_SHARED_CODE != 0U
+  /*enable the semaphore mask interrupts */
+  if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID)
+  {
+    /*Use interrupt line 0 for CPU1 Master */
+    HSEM->C1IER &= ~SemMask;
+  }
+  else /* HSEM_CPU2_COREID */
+  {
+    /*Use interrupt line 1 for CPU2 Master*/
+    HSEM->C2IER &= ~SemMask;
+  }
+#else
+  HSEM_COMMON->IER &= ~SemMask;
+#endif
+}
+
+/**
+  * @brief  This function handles HSEM interrupt request
+  * @retval None
+  */
+void HAL_HSEM_IRQHandler(void)
+{
+  uint32_t statusreg;
+#if  USE_MULTI_CORE_SHARED_CODE != 0U
+  if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID)
+  {
+    /* Get the list of masked freed semaphores*/
+    statusreg = HSEM->C1MISR; /*Use interrupt line 0 for CPU1 Master*/
+
+    /*Disable Interrupts*/
+    HSEM->C1IER &= ~((uint32_t)statusreg);
+
+    /*Clear Flags*/
+    HSEM->C1ICR = ((uint32_t)statusreg);
+  }
+  else /* HSEM_CPU2_COREID */
+  {
+    /* Get the list of masked freed semaphores*/
+    statusreg = HSEM->C2MISR;/*Use interrupt line 1 for CPU2 Master*/
+
+    /*Disable Interrupts*/
+    HSEM->C2IER &= ~((uint32_t)statusreg);
+
+    /*Clear Flags*/
+    HSEM->C2ICR = ((uint32_t)statusreg);
+  }
+#else
+  /* Get the list of masked freed semaphores*/
+  statusreg = HSEM_COMMON->MISR;
+
+  /*Disable Interrupts*/
+  HSEM_COMMON->IER &= ~((uint32_t)statusreg);
+
+  /*Clear Flags*/
+  HSEM_COMMON->ICR = ((uint32_t)statusreg);
+
+#endif
+  /* Call FreeCallback */
+  HAL_HSEM_FreeCallback(statusreg);
+}
+
+/**
+  * @brief Semaphore Released Callback.
+  * @param SemMask: Mask of Released semaphores
+  * @retval None
+  */
+__weak void HAL_HSEM_FreeCallback(uint32_t SemMask)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(SemMask);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+  the HAL_HSEM_FreeCallback can be implemented in the user file
+    */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_HSEM_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c
new file mode 100644
index 00000000..7c05d16f
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c
@@ -0,0 +1,6635 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_i2c.c
+  * @author  MCD Application Team
+  * @brief   I2C HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Inter Integrated Circuit (I2C) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral State and Errors functions
+  *
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The I2C HAL driver can be used as follows:
+
+    (#) Declare a I2C_HandleTypeDef handle structure, for example:
+        I2C_HandleTypeDef  hi2c;
+
+    (#)Initialize the I2C low level resources by implementing the @ref HAL_I2C_MspInit() API:
+        (##) Enable the I2Cx interface clock
+        (##) I2C pins configuration
+            (+++) Enable the clock for the I2C GPIOs
+            (+++) Configure I2C pins as alternate function open-drain
+        (##) NVIC configuration if you need to use interrupt process
+            (+++) Configure the I2Cx interrupt priority
+            (+++) Enable the NVIC I2C IRQ Channel
+        (##) DMA Configuration if you need to use DMA process
+            (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream or channel depends on Instance
+            (+++) Enable the DMAx interface clock using
+            (+++) Configure the DMA handle parameters
+            (+++) Configure the DMA Tx or Rx stream or channel depends on Instance
+            (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
+            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
+                  the DMA Tx or Rx stream or channel depends on Instance
+
+    (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
+        Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
+
+    (#) Initialize the I2C registers by calling the @ref HAL_I2C_Init(), configures also the low level Hardware
+        (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_I2C_MspInit(&hi2c) API.
+
+    (#) To check if target device is ready for communication, use the function @ref HAL_I2C_IsDeviceReady()
+
+    (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
+
+    *** Polling mode IO operation ***
+    =================================
+    [..]
+      (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Transmit()
+      (+) Receive in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Receive()
+      (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Transmit()
+      (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Receive()
+
+    *** Polling mode IO MEM operation ***
+    =====================================
+    [..]
+      (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_I2C_Mem_Write()
+      (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_I2C_Mem_Read()
+
+
+    *** Interrupt mode IO operation ***
+    ===================================
+    [..]
+      (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Transmit_IT()
+      (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
+      (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Receive_IT()
+      (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
+      (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Transmit_IT()
+      (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
+      (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Receive_IT()
+      (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
+      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
+      (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
+      (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
+      (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.
+           This action will inform Master to generate a Stop condition to discard the communication.
+
+
+    *** Interrupt mode or DMA mode IO sequential operation ***
+    ==========================================================
+    [..]
+      (@) These interfaces allow to manage a sequential transfer with a repeated start condition
+          when a direction change during transfer
+    [..]
+      (+) A specific option field manage the different steps of a sequential transfer
+      (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:
+      (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
+      (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
+                            and data to transfer without a final stop condition
+      (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
+                            and data to transfer without a final stop condition, an then permit a call the same master sequential interface
+                            several times (like @ref HAL_I2C_Master_Seq_Transmit_IT() then @ref HAL_I2C_Master_Seq_Transmit_IT()
+                            or @ref HAL_I2C_Master_Seq_Transmit_DMA() then @ref HAL_I2C_Master_Seq_Transmit_DMA())
+      (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
+                            and with new data to transfer if the direction change or manage only the new data to transfer
+                            if no direction change and without a final stop condition in both cases
+      (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
+                            and with new data to transfer if the direction change or manage only the new data to transfer
+                            if no direction change and with a final stop condition in both cases
+      (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential
+                            interface several times (link with option I2C_FIRST_AND_NEXT_FRAME).
+                            Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
+                              or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
+                              or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
+                              or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME).
+                            Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit
+                              without stopping the communication and so generate a restart condition.
+      (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential
+                            interface.
+                            Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
+                              or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
+                              or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
+                              or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME).
+                            Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition.
+
+      (+) Differents sequential I2C interfaces are listed below:
+      (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT()
+            or using @ref HAL_I2C_Master_Seq_Transmit_DMA()
+      (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
+      (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Receive_IT()
+            or using @ref HAL_I2C_Master_Seq_Receive_DMA()
+      (+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
+      (++) Abort a master IT or DMA I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
+      (+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
+      (++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen_IT() @ref HAL_I2C_DisableListen_IT()
+      (+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and user can
+           add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
+      (+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback()
+      (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Transmit_IT()
+            or using @ref HAL_I2C_Slave_Seq_Transmit_DMA()
+      (+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
+      (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Receive_IT()
+            or using @ref HAL_I2C_Slave_Seq_Receive_DMA()
+      (+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
+      (++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
+      (++) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.
+           This action will inform Master to generate a Stop condition to discard the communication.
+
+    *** Interrupt mode IO MEM operation ***
+    =======================================
+    [..]
+      (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
+          @ref HAL_I2C_Mem_Write_IT()
+      (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()
+      (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
+          @ref HAL_I2C_Mem_Read_IT()
+      (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()
+      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
+
+    *** DMA mode IO operation ***
+    ==============================
+    [..]
+      (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
+          @ref HAL_I2C_Master_Transmit_DMA()
+      (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
+      (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
+          @ref HAL_I2C_Master_Receive_DMA()
+      (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
+      (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
+          @ref HAL_I2C_Slave_Transmit_DMA()
+      (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
+      (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
+          @ref HAL_I2C_Slave_Receive_DMA()
+      (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
+      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
+      (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
+      (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
+      (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.
+           This action will inform Master to generate a Stop condition to discard the communication.
+
+    *** DMA mode IO MEM operation ***
+    =================================
+    [..]
+      (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
+          @ref HAL_I2C_Mem_Write_DMA()
+      (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()
+      (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
+          @ref HAL_I2C_Mem_Read_DMA()
+      (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()
+      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
+
+
+     *** I2C HAL driver macros list ***
+     ==================================
+     [..]
+       Below the list of most used macros in I2C HAL driver.
+
+      (+) @ref __HAL_I2C_ENABLE: Enable the I2C peripheral
+      (+) @ref __HAL_I2C_DISABLE: Disable the I2C peripheral
+      (+) @ref __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
+      (+) @ref __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
+      (+) @ref __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
+      (+) @ref __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
+      (+) @ref __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
+
+     *** Callback registration ***
+     =============================================
+    [..]
+     The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
+     allows the user to configure dynamically the driver callbacks.
+     Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback()
+     to register an interrupt callback.
+    [..]
+     Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks:
+       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+       (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
+       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
+       (+) ListenCpltCallback   : callback for end of listen mode.
+       (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.
+       (+) MemRxCpltCallback    : callback for Memory reception end of transfer.
+       (+) ErrorCallback        : callback for error detection.
+       (+) AbortCpltCallback    : callback for abort completion process.
+       (+) MspInitCallback      : callback for Msp Init.
+       (+) MspDeInitCallback    : callback for Msp DeInit.
+     This function takes as parameters the HAL peripheral handle, the Callback ID
+     and a pointer to the user callback function.
+    [..]
+     For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback().
+    [..]
+     Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default
+     weak function.
+     @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
+     and the Callback ID.
+     This function allows to reset following callbacks:
+       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+       (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
+       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
+       (+) ListenCpltCallback   : callback for end of listen mode.
+       (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.
+       (+) MemRxCpltCallback    : callback for Memory reception end of transfer.
+       (+) ErrorCallback        : callback for error detection.
+       (+) AbortCpltCallback    : callback for abort completion process.
+       (+) MspInitCallback      : callback for Msp Init.
+       (+) MspDeInitCallback    : callback for Msp DeInit.
+    [..]
+     For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback().
+    [..]
+     By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET
+     all callbacks are set to the corresponding weak functions:
+     examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback().
+     Exception done for MspInit and MspDeInit functions that are
+     reset to the legacy weak functions in the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() only when
+     these callbacks are null (not registered beforehand).
+     If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit()
+     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+    [..]
+     Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.
+     Exception done MspInit/MspDeInit functions that can be registered/unregistered
+     in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,
+     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+     Then, the user first registers the MspInit/MspDeInit user callbacks
+     using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit()
+     or @ref HAL_I2C_Init() function.
+    [..]
+     When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
+     not defined, the callback registration feature is not available and all callbacks
+     are set to the corresponding weak functions.
+
+     [..]
+       (@) You can refer to the I2C HAL driver header file for more useful macros
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup I2C I2C
+  * @brief I2C HAL module driver
+  * @{
+  */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup I2C_Private_Define I2C Private Define
+  * @{
+  */
+#define TIMING_CLEAR_MASK   (0xF0FFFFFFU)  /*!< I2C TIMING clear register Mask */
+#define I2C_TIMEOUT_ADDR    (10000U)       /*!< 10 s  */
+#define I2C_TIMEOUT_BUSY    (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_DIR     (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_RXNE    (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_STOPF   (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_TC      (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_TCR     (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_TXIS    (25U)          /*!< 25 ms */
+#define I2C_TIMEOUT_FLAG    (25U)          /*!< 25 ms */
+
+#define MAX_NBYTE_SIZE      255U
+#define SlaveAddr_SHIFT     7U
+#define SlaveAddr_MSK       0x06U
+
+/* Private define for @ref PreviousState usage */
+#define I2C_STATE_MSK             ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits            */
+#define I2C_STATE_NONE            ((uint32_t)(HAL_I2C_MODE_NONE))                                                        /*!< Default Value                                          */
+#define I2C_STATE_MASTER_BUSY_TX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER))            /*!< Master Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MASTER_BUSY_RX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER))            /*!< Master Busy RX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_SLAVE_BUSY_TX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE))             /*!< Slave Busy TX, combinaison of State LSB and Mode enum  */
+#define I2C_STATE_SLAVE_BUSY_RX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE))             /*!< Slave Busy RX, combinaison of State LSB and Mode enum  */
+#define I2C_STATE_MEM_BUSY_TX     ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM))               /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MEM_BUSY_RX     ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM))               /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
+
+
+/* Private define to centralize the enable/disable of Interrupts */
+#define I2C_XFER_TX_IT          (uint16_t)(0x0001U)   /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */
+#define I2C_XFER_RX_IT          (uint16_t)(0x0002U)   /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */
+#define I2C_XFER_LISTEN_IT      (uint16_t)(0x8000U)   /* Bit field can be combinated with @ref I2C_XFER_TX_IT and @ref I2C_XFER_RX_IT */
+
+#define I2C_XFER_ERROR_IT       (uint16_t)(0x0010U)   /* Bit definition to manage addition of global Error and NACK treatment */
+#define I2C_XFER_CPLT_IT        (uint16_t)(0x0020U)   /* Bit definition to manage only STOP evenement */
+#define I2C_XFER_RELOAD_IT      (uint16_t)(0x0040U)   /* Bit definition to manage only Reload of NBYTE */
+
+/* Private define Sequential Transfer Options default/reset value */
+#define I2C_NO_OPTION_FRAME     (0xFFFF0000U)
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/** @defgroup I2C_Private_Functions I2C Private Functions
+  * @{
+  */
+/* Private functions to handle DMA transfer */
+static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
+static void I2C_DMAError(DMA_HandleTypeDef *hdma);
+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
+
+/* Private functions to handle IT transfer */
+static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c);
+static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c);
+static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
+
+/* Private functions to handle IT transfer */
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
+
+/* Private functions for I2C transfer IRQ handler */
+static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
+
+/* Private functions to handle flags during polling transfer */
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+
+/* Private functions to centralize the enable/disable of Interrupts */
+static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
+static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
+
+/* Private function to treat different error callback */
+static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c);
+
+/* Private function to flush TXDR register */
+static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
+
+/* Private function to handle  start, restart or stop a transfer */
+static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
+
+/* Private function to Convert Specific options */
+static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Functions I2C Exported Functions
+  * @{
+  */
+
+/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This subsection provides a set of functions allowing to initialize and
+          deinitialize the I2Cx peripheral:
+
+      (+) User must Implement HAL_I2C_MspInit() function in which he configures
+          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+      (+) Call the function HAL_I2C_Init() to configure the selected device with
+          the selected configuration:
+        (++) Clock Timing
+        (++) Own Address 1
+        (++) Addressing mode (Master, Slave)
+        (++) Dual Addressing mode
+        (++) Own Address 2
+        (++) Own Address 2 Mask
+        (++) General call mode
+        (++) Nostretch mode
+
+      (+) Call the function HAL_I2C_DeInit() to restore the default configuration
+          of the selected I2Cx peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the I2C according to the specified parameters
+  *         in the I2C_InitTypeDef and initialize the associated handle.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
+{
+  /* Check the I2C handle allocation */
+  if (hi2c == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
+  assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
+  assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
+  assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
+  assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
+  assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
+  assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
+
+  if (hi2c->State == HAL_I2C_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hi2c->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    /* Init the I2C Callback settings */
+    hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
+    hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
+    hi2c->SlaveTxCpltCallback  = HAL_I2C_SlaveTxCpltCallback;  /* Legacy weak SlaveTxCpltCallback  */
+    hi2c->SlaveRxCpltCallback  = HAL_I2C_SlaveRxCpltCallback;  /* Legacy weak SlaveRxCpltCallback  */
+    hi2c->ListenCpltCallback   = HAL_I2C_ListenCpltCallback;   /* Legacy weak ListenCpltCallback   */
+    hi2c->MemTxCpltCallback    = HAL_I2C_MemTxCpltCallback;    /* Legacy weak MemTxCpltCallback    */
+    hi2c->MemRxCpltCallback    = HAL_I2C_MemRxCpltCallback;    /* Legacy weak MemRxCpltCallback    */
+    hi2c->ErrorCallback        = HAL_I2C_ErrorCallback;        /* Legacy weak ErrorCallback        */
+    hi2c->AbortCpltCallback    = HAL_I2C_AbortCpltCallback;    /* Legacy weak AbortCpltCallback    */
+    hi2c->AddrCallback         = HAL_I2C_AddrCallback;         /* Legacy weak AddrCallback         */
+
+    if (hi2c->MspInitCallback == NULL)
+    {
+      hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit  */
+    }
+
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+    hi2c->MspInitCallback(hi2c);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+    HAL_I2C_MspInit(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+
+  hi2c->State = HAL_I2C_STATE_BUSY;
+
+  /* Disable the selected I2C peripheral */
+  __HAL_I2C_DISABLE(hi2c);
+
+  /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
+  /* Configure I2Cx: Frequency range */
+  hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
+
+  /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
+  /* Disable Own Address1 before set the Own Address1 configuration */
+  hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
+
+  /* Configure I2Cx: Own Address1 and ack own address1 mode */
+  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
+  {
+    hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
+  }
+  else /* I2C_ADDRESSINGMODE_10BIT */
+  {
+    hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
+  }
+
+  /*---------------------------- I2Cx CR2 Configuration ----------------------*/
+  /* Configure I2Cx: Addressing Master mode */
+  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+  {
+    hi2c->Instance->CR2 = (I2C_CR2_ADD10);
+  }
+  /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
+  hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
+
+  /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
+  /* Disable Own Address2 before set the Own Address2 configuration */
+  hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
+
+  /* Configure I2Cx: Dual mode and Own Address2 */
+  hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));
+
+  /*---------------------------- I2Cx CR1 Configuration ----------------------*/
+  /* Configure I2Cx: Generalcall and NoStretch mode */
+  hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
+
+  /* Enable the selected I2C peripheral */
+  __HAL_I2C_ENABLE(hi2c);
+
+  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+  hi2c->State = HAL_I2C_STATE_READY;
+  hi2c->PreviousState = I2C_STATE_NONE;
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the I2C peripheral.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
+{
+  /* Check the I2C handle allocation */
+  if (hi2c == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+
+  hi2c->State = HAL_I2C_STATE_BUSY;
+
+  /* Disable the I2C Peripheral Clock */
+  __HAL_I2C_DISABLE(hi2c);
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+  if (hi2c->MspDeInitCallback == NULL)
+  {
+    hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit  */
+  }
+
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  hi2c->MspDeInitCallback(hi2c);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_I2C_MspDeInit(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+
+  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+  hi2c->State = HAL_I2C_STATE_RESET;
+  hi2c->PreviousState = I2C_STATE_NONE;
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Initialize the I2C MSP.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief DeInitialize the I2C MSP.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MspDeInit could be implemented in the user file
+   */
+}
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User I2C Callback
+  *         To be used instead of the weak predefined callback
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+  *          @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
+  *          @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
+  *          @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
+  *          @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hi2c);
+
+  if (HAL_I2C_STATE_READY == hi2c->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
+        hi2c->MasterTxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
+        hi2c->MasterRxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
+        hi2c->SlaveTxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
+        hi2c->SlaveRxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_LISTEN_COMPLETE_CB_ID :
+        hi2c->ListenCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
+        hi2c->MemTxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
+        hi2c->MemRxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_ERROR_CB_ID :
+        hi2c->ErrorCallback = pCallback;
+        break;
+
+      case HAL_I2C_ABORT_CB_ID :
+        hi2c->AbortCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_MSPINIT_CB_ID :
+        hi2c->MspInitCallback = pCallback;
+        break;
+
+      case HAL_I2C_MSPDEINIT_CB_ID :
+        hi2c->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_I2C_STATE_RESET == hi2c->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_I2C_MSPINIT_CB_ID :
+        hi2c->MspInitCallback = pCallback;
+        break;
+
+      case HAL_I2C_MSPDEINIT_CB_ID :
+        hi2c->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hi2c);
+  return status;
+}
+
+/**
+  * @brief  Unregister an I2C Callback
+  *         I2C callback is redirected to the weak predefined callback
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+  *          @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
+  *          @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
+  *          @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
+  *          @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hi2c);
+
+  if (HAL_I2C_STATE_READY == hi2c->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
+        hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
+        break;
+
+      case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
+        hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
+        break;
+
+      case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
+        hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback;   /* Legacy weak SlaveTxCpltCallback  */
+        break;
+
+      case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
+        hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback;   /* Legacy weak SlaveRxCpltCallback  */
+        break;
+
+      case HAL_I2C_LISTEN_COMPLETE_CB_ID :
+        hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback;     /* Legacy weak ListenCpltCallback   */
+        break;
+
+      case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
+        hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback;       /* Legacy weak MemTxCpltCallback    */
+        break;
+
+      case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
+        hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback;       /* Legacy weak MemRxCpltCallback    */
+        break;
+
+      case HAL_I2C_ERROR_CB_ID :
+        hi2c->ErrorCallback = HAL_I2C_ErrorCallback;               /* Legacy weak ErrorCallback        */
+        break;
+
+      case HAL_I2C_ABORT_CB_ID :
+        hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback;       /* Legacy weak AbortCpltCallback    */
+        break;
+
+      case HAL_I2C_MSPINIT_CB_ID :
+        hi2c->MspInitCallback = HAL_I2C_MspInit;                   /* Legacy weak MspInit              */
+        break;
+
+      case HAL_I2C_MSPDEINIT_CB_ID :
+        hi2c->MspDeInitCallback = HAL_I2C_MspDeInit;               /* Legacy weak MspDeInit            */
+        break;
+
+      default :
+        /* Update the error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_I2C_STATE_RESET == hi2c->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_I2C_MSPINIT_CB_ID :
+        hi2c->MspInitCallback = HAL_I2C_MspInit;                   /* Legacy weak MspInit              */
+        break;
+
+      case HAL_I2C_MSPDEINIT_CB_ID :
+        hi2c->MspDeInitCallback = HAL_I2C_MspDeInit;               /* Legacy weak MspDeInit            */
+        break;
+
+      default :
+        /* Update the error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hi2c);
+  return status;
+}
+
+/**
+  * @brief  Register the Slave Address Match I2C Callback
+  *         To be used instead of the weak HAL_I2C_AddrCallback() predefined callback
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pCallback pointer to the Address Match Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hi2c);
+
+  if (HAL_I2C_STATE_READY == hi2c->State)
+  {
+    hi2c->AddrCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hi2c);
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Slave Address Match I2C Callback
+  *         Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hi2c);
+
+  if (HAL_I2C_STATE_READY == hi2c->State)
+  {
+    hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hi2c);
+  return status;
+}
+
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
+ *  @brief   Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the I2C data
+    transfers.
+
+    (#) There are two modes of transfer:
+       (++) Blocking mode : The communication is performed in the polling mode.
+            The status of all data processing is returned by the same function
+            after finishing transfer.
+       (++) No-Blocking mode : The communication is performed using Interrupts
+            or DMA. These functions return the status of the transfer startup.
+            The end of the data processing will be indicated through the
+            dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
+            using DMA mode.
+
+    (#) Blocking mode functions are :
+        (++) HAL_I2C_Master_Transmit()
+        (++) HAL_I2C_Master_Receive()
+        (++) HAL_I2C_Slave_Transmit()
+        (++) HAL_I2C_Slave_Receive()
+        (++) HAL_I2C_Mem_Write()
+        (++) HAL_I2C_Mem_Read()
+        (++) HAL_I2C_IsDeviceReady()
+
+    (#) No-Blocking mode functions with Interrupt are :
+        (++) HAL_I2C_Master_Transmit_IT()
+        (++) HAL_I2C_Master_Receive_IT()
+        (++) HAL_I2C_Slave_Transmit_IT()
+        (++) HAL_I2C_Slave_Receive_IT()
+        (++) HAL_I2C_Mem_Write_IT()
+        (++) HAL_I2C_Mem_Read_IT()
+        (++) HAL_I2C_Master_Seq_Transmit_IT()
+        (++) HAL_I2C_Master_Seq_Receive_IT()
+        (++) HAL_I2C_Slave_Seq_Transmit_IT()
+        (++) HAL_I2C_Slave_Seq_Receive_IT()
+        (++) HAL_I2C_EnableListen_IT()
+        (++) HAL_I2C_DisableListen_IT()
+        (++) HAL_I2C_Master_Abort_IT()
+
+    (#) No-Blocking mode functions with DMA are :
+        (++) HAL_I2C_Master_Transmit_DMA()
+        (++) HAL_I2C_Master_Receive_DMA()
+        (++) HAL_I2C_Slave_Transmit_DMA()
+        (++) HAL_I2C_Slave_Receive_DMA()
+        (++) HAL_I2C_Mem_Write_DMA()
+        (++) HAL_I2C_Mem_Read_DMA()
+        (++) HAL_I2C_Master_Seq_Transmit_DMA()
+        (++) HAL_I2C_Master_Seq_Receive_DMA()
+        (++) HAL_I2C_Slave_Seq_Transmit_DMA()
+        (++) HAL_I2C_Slave_Seq_Receive_DMA()
+
+    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+        (++) HAL_I2C_MasterTxCpltCallback()
+        (++) HAL_I2C_MasterRxCpltCallback()
+        (++) HAL_I2C_SlaveTxCpltCallback()
+        (++) HAL_I2C_SlaveRxCpltCallback()
+        (++) HAL_I2C_MemTxCpltCallback()
+        (++) HAL_I2C_MemRxCpltCallback()
+        (++) HAL_I2C_AddrCallback()
+        (++) HAL_I2C_ListenCpltCallback()
+        (++) HAL_I2C_ErrorCallback()
+        (++) HAL_I2C_AbortCpltCallback()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Transmits in master mode an amount of data in blocking mode.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferISR   = NULL;
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
+    }
+
+    while (hi2c->XferCount > 0U)
+    {
+      /* Wait until TXIS flag is set */
+      if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+
+      if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+      {
+        /* Wait until TCR flag is set */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        if (hi2c->XferCount > MAX_NBYTE_SIZE)
+        {
+          hi2c->XferSize = MAX_NBYTE_SIZE;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+        }
+        else
+        {
+          hi2c->XferSize = hi2c->XferCount;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+        }
+      }
+    }
+
+    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+    /* Wait until STOPF flag is set */
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Clear STOP Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Clear Configuration Register 2 */
+    I2C_RESET_CR2(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receives in master mode an amount of data in blocking mode.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferISR   = NULL;
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+    }
+
+    while (hi2c->XferCount > 0U)
+    {
+      /* Wait until RXNE flag is set */
+      if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Read data from RXDR */
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+
+      if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+      {
+        /* Wait until TCR flag is set */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        if (hi2c->XferCount > MAX_NBYTE_SIZE)
+        {
+          hi2c->XferSize = MAX_NBYTE_SIZE;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+        }
+        else
+        {
+          hi2c->XferSize = hi2c->XferCount;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+        }
+      }
+    }
+
+    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+    /* Wait until STOPF flag is set */
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Clear STOP Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Clear Configuration Register 2 */
+    I2C_RESET_CR2(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmits in slave mode an amount of data in blocking mode.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferISR   = NULL;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Wait until ADDR flag is set */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+
+    /* If 10bit addressing mode is selected */
+    if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+    {
+      /* Wait until ADDR flag is set */
+      if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+      {
+        /* Disable Address Acknowledge */
+        hi2c->Instance->CR2 |= I2C_CR2_NACK;
+        return HAL_ERROR;
+      }
+
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+    }
+
+    /* Wait until DIR flag is set Transmitter mode */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    while (hi2c->XferCount > 0U)
+    {
+      /* Wait until TXIS flag is set */
+      if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        /* Disable Address Acknowledge */
+        hi2c->Instance->CR2 |= I2C_CR2_NACK;
+        return HAL_ERROR;
+      }
+
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+    }
+
+    /* Wait until STOP flag is set */
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      {
+        /* Normal use case for Transmitter mode */
+        /* A NACK is generated to confirm the end of transfer */
+        hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+      }
+      else
+      {
+        return HAL_ERROR;
+      }
+    }
+
+    /* Clear STOP flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Wait until BUSY flag is reset */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    /* Disable Address Acknowledge */
+    hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in slave mode an amount of data in blocking mode
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferISR   = NULL;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Wait until ADDR flag is set */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+
+    /* Wait until DIR flag is reset Receiver mode */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    while (hi2c->XferCount > 0U)
+    {
+      /* Wait until RXNE flag is set */
+      if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        /* Disable Address Acknowledge */
+        hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+        /* Store Last receive data if any */
+        if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+        {
+          /* Read data from RXDR */
+          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+          /* Increment Buffer pointer */
+          hi2c->pBuffPtr++;
+
+          hi2c->XferCount--;
+        }
+
+        return HAL_ERROR;
+      }
+
+      /* Read data from RXDR */
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+    }
+
+    /* Wait until STOP flag is set */
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    /* Clear STOP flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Wait until BUSY flag is reset */
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
+    {
+      /* Disable Address Acknowledge */
+      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+      return HAL_ERROR;
+    }
+
+    /* Disable Address Acknowledge */
+    hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit in master mode an amount of data in non-blocking mode with Interrupt
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+  uint32_t xfermode;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_IT;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in master mode an amount of data in non-blocking mode with Interrupt
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+  uint32_t xfermode;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_IT;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit in slave mode an amount of data in non-blocking mode with Interrupt
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Slave_ISR_IT;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in slave mode an amount of data in non-blocking mode with Interrupt
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Slave_ISR_IT;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit in master mode an amount of data in non-blocking mode with DMA
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+  uint32_t xfermode;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_DMA;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    if (hi2c->XferSize > 0U)
+    {
+      if (hi2c->hdmatx != NULL)
+      {
+        /* Set the I2C DMA transfer complete callback */
+        hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+
+        /* Set the DMA error callback */
+        hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hi2c->hdmatx->XferHalfCpltCallback = NULL;
+        hi2c->hdmatx->XferAbortCallback = NULL;
+
+        /* Enable the DMA stream or channel depends on Instance */
+        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+
+      if (dmaxferstatus == HAL_OK)
+      {
+        /* Send Slave Address */
+        /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
+
+        /* Update XferCount value */
+        hi2c->XferCount -= hi2c->XferSize;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Note : The I2C interrupts must be enabled after unlocking current process
+                  to avoid the risk of I2C interrupt handle execution before current
+                  process unlock */
+        /* Enable ERR and NACK interrupts */
+        I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+        /* Enable DMA Request */
+        hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Update Transfer ISR function pointer */
+      hi2c->XferISR = I2C_Master_ISR_IT;
+
+      /* Send Slave Address */
+      /* Set NBYTES to write and generate START condition */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+      /* possible to enable all of these */
+      /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in master mode an amount of data in non-blocking mode with DMA
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+{
+  uint32_t xfermode;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_DMA;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    if (hi2c->XferSize > 0U)
+    {
+      if (hi2c->hdmarx != NULL)
+      {
+        /* Set the I2C DMA transfer complete callback */
+        hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+
+        /* Set the DMA error callback */
+        hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hi2c->hdmarx->XferHalfCpltCallback = NULL;
+        hi2c->hdmarx->XferAbortCallback = NULL;
+
+        /* Enable the DMA stream or channel depends on Instance */
+        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+
+      if (dmaxferstatus == HAL_OK)
+      {
+        /* Send Slave Address */
+        /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+
+        /* Update XferCount value */
+        hi2c->XferCount -= hi2c->XferSize;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Note : The I2C interrupts must be enabled after unlocking current process
+                  to avoid the risk of I2C interrupt handle execution before current
+                  process unlock */
+        /* Enable ERR and NACK interrupts */
+        I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+        /* Enable DMA Request */
+        hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Update Transfer ISR function pointer */
+      hi2c->XferISR = I2C_Master_ISR_IT;
+
+      /* Send Slave Address */
+      /* Set NBYTES to read and generate START condition */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+      /* possible to enable all of these */
+      /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Transmit in slave mode an amount of data in non-blocking mode with DMA
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef dmaxferstatus;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Slave_ISR_DMA;
+
+    if (hi2c->hdmatx != NULL)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmatx->XferHalfCpltCallback = NULL;
+      hi2c->hdmatx->XferAbortCallback = NULL;
+
+      /* Enable the DMA stream or channel depends on Instance */
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Enable Address Acknowledge */
+      hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, STOP, NACK, ADDR interrupts */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+      /* Enable DMA Request */
+      hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive in slave mode an amount of data in non-blocking mode with DMA
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef dmaxferstatus;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Slave_ISR_DMA;
+
+    if (hi2c->hdmarx != NULL)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmarx->XferHalfCpltCallback = NULL;
+      hi2c->hdmarx->XferAbortCallback = NULL;
+
+      /* Enable the DMA stream or channel depends on Instance */
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Enable Address Acknowledge */
+      hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, STOP, NACK, ADDR interrupts */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+      /* Enable DMA Request */
+      hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+/**
+  * @brief  Write an amount of data in blocking mode to a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferISR   = NULL;
+
+    /* Send Slave Address and Memory Address */
+    if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+      return HAL_ERROR;
+    }
+
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+    }
+
+    do
+    {
+      /* Wait until TXIS flag is set */
+      if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+
+      if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+      {
+        /* Wait until TCR flag is set */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        if (hi2c->XferCount > MAX_NBYTE_SIZE)
+        {
+          hi2c->XferSize = MAX_NBYTE_SIZE;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+        }
+        else
+        {
+          hi2c->XferSize = hi2c->XferCount;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+        }
+      }
+
+    }
+    while (hi2c->XferCount > 0U);
+
+    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+    /* Wait until STOPF flag is reset */
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Clear STOP Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Clear Configuration Register 2 */
+    I2C_RESET_CR2(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Read an amount of data in blocking mode from a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr  = pData;
+    hi2c->XferCount = Size;
+    hi2c->XferISR   = NULL;
+
+    /* Send Slave Address and Memory Address */
+    if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+      return HAL_ERROR;
+    }
+
+    /* Send Slave Address */
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+    }
+
+    do
+    {
+      /* Wait until RXNE flag is set */
+      if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Read data from RXDR */
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+
+      if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+      {
+        /* Wait until TCR flag is set */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        if (hi2c->XferCount > MAX_NBYTE_SIZE)
+        {
+          hi2c->XferSize = MAX_NBYTE_SIZE;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+        }
+        else
+        {
+          hi2c->XferSize = hi2c->XferCount;
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+        }
+      }
+    }
+    while (hi2c->XferCount > 0U);
+
+    /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+    /* Wait until STOPF flag is reset */
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Clear STOP Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Clear Configuration Register 2 */
+    I2C_RESET_CR2(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode  = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+/**
+  * @brief  Write an amount of data in non-blocking mode with Interrupt to a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+  uint32_t tickstart;
+  uint32_t xfermode;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_IT;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    /* Send Slave Address and Memory Address */
+    if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+      return HAL_ERROR;
+    }
+
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Read an amount of data in non-blocking mode with Interrupt from a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+  uint32_t tickstart;
+  uint32_t xfermode;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_IT;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    /* Send Slave Address and Memory Address */
+    if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+      return HAL_ERROR;
+    }
+
+    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+/**
+  * @brief  Write an amount of data in non-blocking mode with DMA to a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+  uint32_t tickstart;
+  uint32_t xfermode;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_DMA;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    /* Send Slave Address and Memory Address */
+    if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+      return HAL_ERROR;
+    }
+
+
+    if (hi2c->hdmatx != NULL)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmatx->XferHalfCpltCallback = NULL;
+      hi2c->hdmatx->XferAbortCallback = NULL;
+
+      /* Enable the DMA stream or channel depends on Instance */
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_READY;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Send Slave Address */
+      /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+
+      /* Update XferCount value */
+      hi2c->XferCount -= hi2c->XferSize;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR and NACK interrupts */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+      /* Enable DMA Request */
+      hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_READY;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Reads an amount of data in non-blocking mode with DMA from a specific memory address.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be read
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+{
+  uint32_t tickstart;
+  uint32_t xfermode;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Init tickstart for timeout management*/
+    tickstart = HAL_GetTick();
+
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->XferISR     = I2C_Master_ISR_DMA;
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    /* Send Slave Address and Memory Address */
+    if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+      return HAL_ERROR;
+    }
+
+    if (hi2c->hdmarx != NULL)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmarx->XferHalfCpltCallback = NULL;
+      hi2c->hdmarx->XferAbortCallback = NULL;
+
+      /* Enable the DMA stream or channel depends on Instance */
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_READY;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+
+      /* Update XferCount value */
+      hi2c->XferCount -= hi2c->XferSize;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR and NACK interrupts */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+      /* Enable DMA Request */
+      hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_READY;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Checks if target device is ready for communication.
+  * @note   This function is used with Memory devices
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  Trials Number of trials
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  __IO uint32_t I2C_Trials = 0UL;
+
+  FlagStatus tmp1;
+  FlagStatus tmp2;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+    {
+      return HAL_BUSY;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    do
+    {
+      /* Generate Start */
+      hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress);
+
+      /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
+      /* Wait until STOPF flag is set or a NACK flag is set*/
+      tickstart = HAL_GetTick();
+
+      tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
+      tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
+
+      while ((tmp1 == RESET) && (tmp2 == RESET))
+      {
+        if (Timeout != HAL_MAX_DELAY)
+        {
+          if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+          {
+            /* Update I2C state */
+            hi2c->State = HAL_I2C_STATE_READY;
+
+            /* Update I2C error code */
+            hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+
+            /* Process Unlocked */
+            __HAL_UNLOCK(hi2c);
+
+            return HAL_ERROR;
+          }
+        }
+
+        tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
+        tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
+      }
+
+      /* Check if the NACKF flag has not been set */
+      if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
+      {
+        /* Wait until STOPF flag is reset */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        /* Clear STOP Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+        /* Device is ready */
+        hi2c->State = HAL_I2C_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_OK;
+      }
+      else
+      {
+        /* Wait until STOPF flag is reset */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        /* Clear NACK Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+        /* Clear STOP Flag, auto generated with autoend*/
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+      }
+
+      /* Check if the maximum allowed number of trials has been reached */
+      if (I2C_Trials == Trials)
+      {
+        /* Generate Stop */
+        hi2c->Instance->CR2 |= I2C_CR2_STOP;
+
+        /* Wait until STOPF flag is reset */
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        /* Clear STOP Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+      }
+
+      /* Increment Trials */
+      I2C_Trials++;
+    }
+    while (I2C_Trials < Trials);
+
+    /* Update I2C state */
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Update I2C error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_ERROR;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  uint32_t xfermode;
+  uint32_t xferrequest = I2C_GENERATE_START_WRITE;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Master_ISR_IT;
+
+    /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = hi2c->XferOptions;
+    }
+
+    /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+    /* Mean Previous state is same as current state */
+    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+    {
+      xferrequest = I2C_NO_STARTSTOP;
+    }
+    else
+    {
+      /* Convert OTHER_xxx XferOptions if any */
+      I2C_ConvertOtherXferOptions(hi2c);
+
+      /* Update xfermode accordingly if no reload is necessary */
+      if (hi2c->XferCount < MAX_NBYTE_SIZE)
+      {
+        xfermode = hi2c->XferOptions;
+      }
+    }
+
+    /* Send Slave Address and set NBYTES to write */
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  uint32_t xfermode;
+  uint32_t xferrequest = I2C_GENERATE_START_WRITE;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Master_ISR_DMA;
+
+    /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = hi2c->XferOptions;
+    }
+
+    /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+    /* Mean Previous state is same as current state */
+    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+    {
+      xferrequest = I2C_NO_STARTSTOP;
+    }
+    else
+    {
+      /* Convert OTHER_xxx XferOptions if any */
+      I2C_ConvertOtherXferOptions(hi2c);
+
+      /* Update xfermode accordingly if no reload is necessary */
+      if (hi2c->XferCount < MAX_NBYTE_SIZE)
+      {
+        xfermode = hi2c->XferOptions;
+      }
+    }
+
+    if (hi2c->XferSize > 0U)
+    {
+      if (hi2c->hdmatx != NULL)
+      {
+        /* Set the I2C DMA transfer complete callback */
+        hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+
+        /* Set the DMA error callback */
+        hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hi2c->hdmatx->XferHalfCpltCallback = NULL;
+        hi2c->hdmatx->XferAbortCallback = NULL;
+
+        /* Enable the DMA stream or channel depends on Instance */
+        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+
+      if (dmaxferstatus == HAL_OK)
+      {
+        /* Send Slave Address and set NBYTES to write */
+        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+
+        /* Update XferCount value */
+        hi2c->XferCount -= hi2c->XferSize;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Note : The I2C interrupts must be enabled after unlocking current process
+                  to avoid the risk of I2C interrupt handle execution before current
+                  process unlock */
+        /* Enable ERR and NACK interrupts */
+        I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+        /* Enable DMA Request */
+        hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Update Transfer ISR function pointer */
+      hi2c->XferISR = I2C_Master_ISR_IT;
+
+      /* Send Slave Address */
+      /* Set NBYTES to write and generate START condition */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+      /* possible to enable all of these */
+      /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  uint32_t xfermode;
+  uint32_t xferrequest = I2C_GENERATE_START_READ;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Master_ISR_IT;
+
+    /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = hi2c->XferOptions;
+    }
+
+    /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+    /* Mean Previous state is same as current state */
+    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+    {
+      xferrequest = I2C_NO_STARTSTOP;
+    }
+    else
+    {
+      /* Convert OTHER_xxx XferOptions if any */
+      I2C_ConvertOtherXferOptions(hi2c);
+
+      /* Update xfermode accordingly if no reload is necessary */
+      if (hi2c->XferCount < MAX_NBYTE_SIZE)
+      {
+        xfermode = hi2c->XferOptions;
+      }
+    }
+
+    /* Send Slave Address and set NBYTES to read */
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  uint32_t xfermode;
+  uint32_t xferrequest = I2C_GENERATE_START_READ;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Master_ISR_DMA;
+
+    /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+      xfermode = I2C_RELOAD_MODE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+      xfermode = hi2c->XferOptions;
+    }
+
+    /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+    /* Mean Previous state is same as current state */
+    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+    {
+      xferrequest = I2C_NO_STARTSTOP;
+    }
+    else
+    {
+      /* Convert OTHER_xxx XferOptions if any */
+      I2C_ConvertOtherXferOptions(hi2c);
+
+      /* Update xfermode accordingly if no reload is necessary */
+      if (hi2c->XferCount < MAX_NBYTE_SIZE)
+      {
+        xfermode = hi2c->XferOptions;
+      }
+    }
+
+    if (hi2c->XferSize > 0U)
+    {
+      if (hi2c->hdmarx != NULL)
+      {
+        /* Set the I2C DMA transfer complete callback */
+        hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+
+        /* Set the DMA error callback */
+        hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hi2c->hdmarx->XferHalfCpltCallback = NULL;
+        hi2c->hdmarx->XferAbortCallback = NULL;
+
+        /* Enable the DMA stream or channel depends on Instance */
+        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+
+      if (dmaxferstatus == HAL_OK)
+      {
+        /* Send Slave Address and set NBYTES to read */
+        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+
+        /* Update XferCount value */
+        hi2c->XferCount -= hi2c->XferSize;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Note : The I2C interrupts must be enabled after unlocking current process
+                  to avoid the risk of I2C interrupt handle execution before current
+                  process unlock */
+        /* Enable ERR and NACK interrupts */
+        I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+        /* Enable DMA Request */
+        hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Update Transfer ISR function pointer */
+      hi2c->XferISR = I2C_Master_ISR_IT;
+
+      /* Send Slave Address */
+      /* Set NBYTES to read and generate START condition */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+                to avoid the risk of I2C interrupt handle execution before current
+                process unlock */
+      /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+      /* possible to enable all of these */
+      /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+    /* and then toggle the HAL slave RX state to TX state */
+    if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+    {
+      /* Disable associated Interrupts */
+      I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+      /* Abort DMA Xfer if any */
+      if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+      {
+        hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+        if (hi2c->hdmarx != NULL)
+        {
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA RX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+          }
+        }
+      }
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Slave_ISR_IT;
+
+    if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+    {
+      /* Clear ADDR flag after prepare the transfer parameters */
+      /* This action will generate an acknowledge to the Master */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
+    /* REnable ADDR interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+
+    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+    /* and then toggle the HAL slave RX state to TX state */
+    if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+    {
+      /* Disable associated Interrupts */
+      I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+      if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+      {
+        /* Abort DMA Xfer if any */
+        if (hi2c->hdmarx != NULL)
+        {
+          hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA RX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+          }
+        }
+      }
+    }
+    else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+    {
+      if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+      {
+        hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+        /* Abort DMA Xfer if any */
+        if (hi2c->hdmatx != NULL)
+        {
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA TX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+          }
+        }
+      }
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Slave_ISR_DMA;
+
+    if (hi2c->hdmatx != NULL)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmatx->XferHalfCpltCallback = NULL;
+      hi2c->hdmatx->XferAbortCallback = NULL;
+
+      /* Enable the DMA stream or channel depends on Instance */
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Update XferCount value */
+      hi2c->XferCount -= hi2c->XferSize;
+
+      /* Reset XferSize */
+      hi2c->XferSize = 0;
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+    {
+      /* Clear ADDR flag after prepare the transfer parameters */
+      /* This action will generate an acknowledge to the Master */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
+    /* Enable ERR, STOP, NACK, ADDR interrupts */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+    /* Enable DMA Request */
+    hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+    /* and then toggle the HAL slave TX state to RX state */
+    if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+    {
+      /* Disable associated Interrupts */
+      I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+      if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+      {
+        hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+        /* Abort DMA Xfer if any */
+        if (hi2c->hdmatx != NULL)
+        {
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA TX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+          }
+        }
+      }
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Slave_ISR_IT;
+
+    if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
+    {
+      /* Clear ADDR flag after prepare the transfer parameters */
+      /* This action will generate an acknowledge to the Master */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
+    /* REnable ADDR interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+      return  HAL_ERROR;
+    }
+
+    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+    /* and then toggle the HAL slave TX state to RX state */
+    if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+    {
+      /* Disable associated Interrupts */
+      I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+      if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+      {
+        /* Abort DMA Xfer if any */
+        if (hi2c->hdmatx != NULL)
+        {
+          hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA TX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+          }
+        }
+      }
+    }
+    else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+    {
+      if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+      {
+        hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+        /* Abort DMA Xfer if any */
+        if (hi2c->hdmarx != NULL)
+        {
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA RX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+          }
+        }
+      }
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Enable Address Acknowledge */
+    hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+    hi2c->XferISR     = I2C_Slave_ISR_DMA;
+
+    if (hi2c->hdmarx != NULL)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmarx->XferHalfCpltCallback = NULL;
+      hi2c->hdmarx->XferAbortCallback = NULL;
+
+      /* Enable the DMA stream or channel depends on Instance */
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Update XferCount value */
+      hi2c->XferCount -= hi2c->XferSize;
+
+      /* Reset XferSize */
+      hi2c->XferSize = 0;
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_LISTEN;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+
+    if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
+    {
+      /* Clear ADDR flag after prepare the transfer parameters */
+      /* This action will generate an acknowledge to the Master */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
+    /* REnable ADDR interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
+
+    /* Enable DMA Request */
+    hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable the Address listen mode with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
+{
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    hi2c->State = HAL_I2C_STATE_LISTEN;
+    hi2c->XferISR = I2C_Slave_ISR_IT;
+
+    /* Enable the Address Match interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Disable the Address listen mode with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
+{
+  /* Declaration of tmp to prevent undefined behavior of volatile usage */
+  uint32_t tmp;
+
+  /* Disable Address listen mode only if a transfer is not ongoing */
+  if (hi2c->State == HAL_I2C_STATE_LISTEN)
+  {
+    tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
+    hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode = HAL_I2C_MODE_NONE;
+    hi2c->XferISR = NULL;
+
+    /* Disable the Address Match interrupt */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Abort a master I2C IT or DMA process communication with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
+{
+  if (hi2c->Mode == HAL_I2C_MODE_MASTER)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Disable Interrupts and Store Previous state */
+    if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+    {
+      I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+      hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+    }
+    else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+    {
+      I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+      hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+    }
+    else
+    {
+      /* Do nothing */
+    }
+
+    /* Set State at HAL_I2C_STATE_ABORT */
+    hi2c->State = HAL_I2C_STATE_ABORT;
+
+    /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
+    /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
+    I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    /* Wrong usage of abort function */
+    /* This function should be used only in case of abort monitored by master device */
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+
+/**
+  * @brief  This function handles I2C event interrupt request.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
+{
+  /* Get current IT Flags and IT sources value */
+  uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
+  uint32_t itsources = READ_REG(hi2c->Instance->CR1);
+
+  /* I2C events treatment -------------------------------------*/
+  if (hi2c->XferISR != NULL)
+  {
+    hi2c->XferISR(hi2c, itflags, itsources);
+  }
+}
+
+/**
+  * @brief  This function handles I2C error interrupt request.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
+{
+  uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
+  uint32_t itsources = READ_REG(hi2c->Instance->CR1);
+  uint32_t tmperror;
+
+  /* I2C Bus error interrupt occurred ------------------------------------*/
+  if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+  {
+    hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
+
+    /* Clear BERR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
+  }
+
+  /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
+  if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+  {
+    hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
+
+    /* Clear OVR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
+  }
+
+  /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
+  if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+  {
+    hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
+
+    /* Clear ARLO flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
+  }
+
+  /* Store current volatile hi2c->ErrorCode, misra rule */
+  tmperror = hi2c->ErrorCode;
+
+  /* Call the Error Callback in case of Error detected */
+  if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) !=  HAL_I2C_ERROR_NONE)
+  {
+    I2C_ITError(hi2c, tmperror);
+  }
+}
+
+/**
+  * @brief  Master Tx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Master Rx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
+   */
+}
+
+/** @brief  Slave Tx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Slave Rx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Slave Address Match callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
+  * @param  AddrMatchCode Address Match Code
+  * @retval None
+  */
+__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+  UNUSED(TransferDirection);
+  UNUSED(AddrMatchCode);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_AddrCallback() could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Listen Complete callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_ListenCpltCallback() could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Memory Tx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MemTxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Memory Rx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MemRxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  I2C error callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  I2C abort callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_AbortCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
+ *  @brief   Peripheral State, Mode and Error functions
+ *
+@verbatim
+ ===============================================================================
+            ##### Peripheral State, Mode and Error functions #####
+ ===============================================================================
+    [..]
+    This subsection permit to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the I2C handle state.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL state
+  */
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
+{
+  /* Return I2C handle state */
+  return hi2c->State;
+}
+
+/**
+  * @brief  Returns the I2C Master, Slave, Memory or no mode.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval HAL mode
+  */
+HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
+{
+  return hi2c->Mode;
+}
+
+/**
+* @brief  Return the I2C error code.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *              the configuration information for the specified I2C.
+* @retval I2C Error Code
+*/
+uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
+{
+  return hi2c->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  ITFlags Interrupt flags to handle.
+  * @param  ITSources Interrupt sources enabled.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
+{
+  uint16_t devaddress;
+  uint32_t tmpITFlags = ITFlags;
+
+  /* Process Locked */
+  __HAL_LOCK(hi2c);
+
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+  {
+    /* Clear NACK Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    /* Set corresponding Error Code */
+    /* No need to generate STOP, it is automatically done */
+    /* Error callback will be send during stop flag treatment */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+    /* Flush TX register */
+    I2C_Flush_TXDR(hi2c);
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+  {
+    /* Remove RXNE flag on temporary variable as read done */
+    tmpITFlags &= ~I2C_FLAG_RXNE;
+
+    /* Read data from RXDR */
+    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    hi2c->XferSize--;
+    hi2c->XferCount--;
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+  {
+    /* Write data to TXDR */
+    hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    hi2c->XferSize--;
+    hi2c->XferCount--;
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+  {
+    if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+    {
+      devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
+
+      if (hi2c->XferCount > MAX_NBYTE_SIZE)
+      {
+        hi2c->XferSize = MAX_NBYTE_SIZE;
+        I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+      }
+      else
+      {
+        hi2c->XferSize = hi2c->XferCount;
+        if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+        {
+          I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP);
+        }
+        else
+        {
+          I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+        }
+      }
+    }
+    else
+    {
+      /* Call TxCpltCallback() if no stop mode is set */
+      if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+      {
+        /* Call I2C Master Sequential complete process */
+        I2C_ITMasterSeqCplt(hi2c);
+      }
+      else
+      {
+        /* Wrong size Status regarding TCR flag event */
+        /* Call the corresponding callback to inform upper layer of End of Transfer */
+        I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+      }
+    }
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+  {
+    if (hi2c->XferCount == 0U)
+    {
+      if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+      {
+        /* Generate a stop condition in case of no transfer option */
+        if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
+        {
+          /* Generate Stop */
+          hi2c->Instance->CR2 |= I2C_CR2_STOP;
+        }
+        else
+        {
+          /* Call I2C Master Sequential complete process */
+          I2C_ITMasterSeqCplt(hi2c);
+        }
+      }
+    }
+    else
+    {
+      /* Wrong size Status regarding TC flag event */
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+      I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+    }
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+  {
+    /* Call I2C Master complete process */
+    I2C_ITMasterCplt(hi2c, tmpITFlags);
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  ITFlags Interrupt flags to handle.
+  * @param  ITSources Interrupt sources enabled.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
+{
+  uint32_t tmpoptions = hi2c->XferOptions;
+  uint32_t tmpITFlags = ITFlags;
+
+  /* Process locked */
+  __HAL_LOCK(hi2c);
+
+  /* Check if STOPF is set */
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+  {
+    /* Call I2C Slave complete process */
+    I2C_ITSlaveCplt(hi2c, tmpITFlags);
+  }
+
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+  {
+    /* Check that I2C transfer finished */
+    /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+    /* Mean XferCount == 0*/
+    /* So clear Flag NACKF only */
+    if (hi2c->XferCount == 0U)
+    {
+      if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */
+      {
+        /* Call I2C Listen complete process */
+        I2C_ITListenCplt(hi2c, tmpITFlags);
+      }
+      else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
+      {
+        /* Clear NACK Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+        /* Flush TX register */
+        I2C_Flush_TXDR(hi2c);
+
+        /* Last Byte is Transmitted */
+        /* Call I2C Slave Sequential complete process */
+        I2C_ITSlaveSeqCplt(hi2c);
+      }
+      else
+      {
+        /* Clear NACK Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+      }
+    }
+    else
+    {
+      /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
+      /* Clear NACK Flag */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+      /* Set ErrorCode corresponding to a Non-Acknowledge */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+      if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
+      {
+        /* Call the corresponding callback to inform upper layer of End of Transfer */
+        I2C_ITError(hi2c, hi2c->ErrorCode);
+      }
+    }
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+  {
+    if (hi2c->XferCount > 0U)
+    {
+      /* Read data from RXDR */
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+    }
+
+    if ((hi2c->XferCount == 0U) && \
+        (tmpoptions != I2C_NO_OPTION_FRAME))
+    {
+      /* Call I2C Slave Sequential complete process */
+      I2C_ITSlaveSeqCplt(hi2c);
+    }
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
+  {
+    I2C_ITAddrCplt(hi2c, tmpITFlags);
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+  {
+    /* Write data to TXDR only if XferCount not reach "0" */
+    /* A TXIS flag can be set, during STOP treatment      */
+    /* Check if all Datas have already been sent */
+    /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
+    if (hi2c->XferCount > 0U)
+    {
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+    }
+    else
+    {
+      if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
+      {
+        /* Last Byte is Transmitted */
+        /* Call I2C Slave Sequential complete process */
+        I2C_ITSlaveSeqCplt(hi2c);
+      }
+    }
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  ITFlags Interrupt flags to handle.
+  * @param  ITSources Interrupt sources enabled.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
+{
+  uint16_t devaddress;
+  uint32_t xfermode;
+
+  /* Process Locked */
+  __HAL_LOCK(hi2c);
+
+  if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+  {
+    /* Clear NACK Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    /* Set corresponding Error Code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+    /* No need to generate STOP, it is automatically done */
+    /* But enable STOP interrupt, to treat it */
+    /* Error callback will be send during stop flag treatment */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+
+    /* Flush TX register */
+    I2C_Flush_TXDR(hi2c);
+  }
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+  {
+    /* Disable TC interrupt */
+    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
+
+    if (hi2c->XferCount != 0U)
+    {
+      /* Recover Slave address */
+      devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
+
+      /* Prepare the new XferSize to transfer */
+      if (hi2c->XferCount > MAX_NBYTE_SIZE)
+      {
+        hi2c->XferSize = MAX_NBYTE_SIZE;
+        xfermode = I2C_RELOAD_MODE;
+      }
+      else
+      {
+        hi2c->XferSize = hi2c->XferCount;
+        if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+        {
+          xfermode = hi2c->XferOptions;
+        }
+        else
+        {
+          xfermode = I2C_AUTOEND_MODE;
+        }
+      }
+
+      /* Set the new XferSize in Nbytes register */
+      I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+
+      /* Update XferCount value */
+      hi2c->XferCount -= hi2c->XferSize;
+
+      /* Enable DMA Request */
+      if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+      {
+        hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+      }
+      else
+      {
+        hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+      }
+    }
+    else
+    {
+      /* Call TxCpltCallback() if no stop mode is set */
+      if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+      {
+        /* Call I2C Master Sequential complete process */
+        I2C_ITMasterSeqCplt(hi2c);
+      }
+      else
+      {
+        /* Wrong size Status regarding TCR flag event */
+        /* Call the corresponding callback to inform upper layer of End of Transfer */
+        I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+      }
+    }
+  }
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+  {
+    if (hi2c->XferCount == 0U)
+    {
+      if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+      {
+        /* Generate a stop condition in case of no transfer option */
+        if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
+        {
+          /* Generate Stop */
+          hi2c->Instance->CR2 |= I2C_CR2_STOP;
+        }
+        else
+        {
+          /* Call I2C Master Sequential complete process */
+          I2C_ITMasterSeqCplt(hi2c);
+        }
+      }
+    }
+    else
+    {
+      /* Wrong size Status regarding TC flag event */
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+      I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+    }
+  }
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+  {
+    /* Call I2C Master complete process */
+    I2C_ITMasterCplt(hi2c, ITFlags);
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  ITFlags Interrupt flags to handle.
+  * @param  ITSources Interrupt sources enabled.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
+{
+  uint32_t tmpoptions = hi2c->XferOptions;
+  uint32_t treatdmanack = 0U;
+  HAL_I2C_StateTypeDef tmpstate;
+
+  /* Process locked */
+  __HAL_LOCK(hi2c);
+
+  /* Check if STOPF is set */
+  if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+  {
+    /* Call I2C Slave complete process */
+    I2C_ITSlaveCplt(hi2c, ITFlags);
+  }
+
+  if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+  {
+    /* Check that I2C transfer finished */
+    /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+    /* Mean XferCount == 0 */
+    /* So clear Flag NACKF only */
+    if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
+        (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))
+    {
+      /* Split check of hdmarx, for MISRA compliance */
+      if (hi2c->hdmarx != NULL)
+      {
+        if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)
+        {
+          if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U)
+          {
+            treatdmanack = 1U;
+          }
+        }
+      }
+
+      /* Split check of hdmatx, for MISRA compliance  */
+      if (hi2c->hdmatx != NULL)
+      {
+        if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)
+        {
+          if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U)
+          {
+            treatdmanack = 1U;
+          }
+        }
+      }
+
+      if (treatdmanack == 1U)
+      {
+        if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */
+        {
+          /* Call I2C Listen complete process */
+          I2C_ITListenCplt(hi2c, ITFlags);
+        }
+        else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
+        {
+          /* Clear NACK Flag */
+          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+          /* Flush TX register */
+          I2C_Flush_TXDR(hi2c);
+
+          /* Last Byte is Transmitted */
+          /* Call I2C Slave Sequential complete process */
+          I2C_ITSlaveSeqCplt(hi2c);
+        }
+        else
+        {
+          /* Clear NACK Flag */
+          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+        }
+      }
+      else
+      {
+        /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
+        /* Clear NACK Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+        /* Set ErrorCode corresponding to a Non-Acknowledge */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+        /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */
+        tmpstate = hi2c->State;
+
+        if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
+        {
+          if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
+          {
+            hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+          }
+          else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+          {
+            hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+          }
+          else
+          {
+            /* Do nothing */
+          }
+
+          /* Call the corresponding callback to inform upper layer of End of Transfer */
+          I2C_ITError(hi2c, hi2c->ErrorCode);
+        }
+      }
+    }
+    else
+    {
+      /* Only Clear NACK Flag, no DMA treatment is pending */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+    }
+  }
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
+  {
+    I2C_ITAddrCplt(hi2c, ITFlags);
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Master sends target device address followed by internal memory address for write request.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
+{
+  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
+
+  /* Wait until TXIS flag is set */
+  if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* If Memory address size is 8Bit */
+  if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
+  {
+    /* Send Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+  }
+  /* If Memory address size is 16Bit */
+  else
+  {
+    /* Send MSB of Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+
+    /* Wait until TXIS flag is set */
+    if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Send LSB of Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+  }
+
+  /* Wait until TCR flag is set */
+  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Master sends target device address followed by internal memory address for read request.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
+{
+  I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
+
+  /* Wait until TXIS flag is set */
+  if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* If Memory address size is 8Bit */
+  if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
+  {
+    /* Send Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+  }
+  /* If Memory address size is 16Bit */
+  else
+  {
+    /* Send MSB of Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+
+    /* Wait until TXIS flag is set */
+    if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Send LSB of Memory Address */
+    hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+  }
+
+  /* Wait until TC flag is set */
+  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  I2C Address complete process callback.
+  * @param  hi2c I2C handle.
+  * @param  ITFlags Interrupt flags to handle.
+  * @retval None
+  */
+static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+  uint8_t transferdirection;
+  uint16_t slaveaddrcode;
+  uint16_t ownadd1code;
+  uint16_t ownadd2code;
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(ITFlags);
+
+  /* In case of Listen state, need to inform upper layer of address match code event */
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    transferdirection = I2C_GET_DIR(hi2c);
+    slaveaddrcode     = I2C_GET_ADDR_MATCH(hi2c);
+    ownadd1code       = I2C_GET_OWN_ADDRESS1(hi2c);
+    ownadd2code       = I2C_GET_OWN_ADDRESS2(hi2c);
+
+    /* If 10bits addressing mode is selected */
+    if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+    {
+      if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK))
+      {
+        slaveaddrcode = ownadd1code;
+        hi2c->AddrEventCount++;
+        if (hi2c->AddrEventCount == 2U)
+        {
+          /* Reset Address Event counter */
+          hi2c->AddrEventCount = 0U;
+
+          /* Clear ADDR flag */
+          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2c);
+
+          /* Call Slave Addr callback */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+          hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#else
+          HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+        }
+      }
+      else
+      {
+        slaveaddrcode = ownadd2code;
+
+        /* Disable ADDR Interrupts */
+        I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Call Slave Addr callback */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+        hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#else
+        HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+      }
+    }
+    /* else 7 bits addressing mode is selected */
+    else
+    {
+      /* Disable ADDR Interrupts */
+      I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Call Slave Addr callback */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#else
+      HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+  }
+  /* Else clear address flag only */
+  else
+  {
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+  }
+}
+
+/**
+  * @brief  I2C Master sequential complete process.
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c)
+{
+  /* Reset I2C handle mode */
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+
+  /* No Generate Stop, to permit restart mode */
+  /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
+  if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+  {
+    hi2c->State         = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+    hi2c->XferISR       = NULL;
+
+    /* Disable Interrupts */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->MasterTxCpltCallback(hi2c);
+#else
+    HAL_I2C_MasterTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+  /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
+  else
+  {
+    hi2c->State         = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+    hi2c->XferISR       = NULL;
+
+    /* Disable Interrupts */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->MasterRxCpltCallback(hi2c);
+#else
+    HAL_I2C_MasterRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief  I2C Slave sequential complete process.
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
+{
+  uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
+
+  /* Reset I2C handle mode */
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+
+  /* If a DMA is ongoing, Update handle size context */
+  if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+  }
+  else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+  }
+  else
+  {
+    /* Do nothing */
+  }
+
+  if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+  {
+    /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
+    hi2c->State         = HAL_I2C_STATE_LISTEN;
+    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+
+    /* Disable Interrupts */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->SlaveTxCpltCallback(hi2c);
+#else
+    HAL_I2C_SlaveTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+
+  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+  {
+    /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
+    hi2c->State         = HAL_I2C_STATE_LISTEN;
+    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+
+    /* Disable Interrupts */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->SlaveRxCpltCallback(hi2c);
+#else
+    HAL_I2C_SlaveRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+}
+
+/**
+  * @brief  I2C Master complete process.
+  * @param  hi2c I2C handle.
+  * @param  ITFlags Interrupt flags to handle.
+  * @retval None
+  */
+static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+  uint32_t tmperror;
+  uint32_t tmpITFlags = ITFlags;
+  uint32_t tmp;
+
+  /* Clear STOP Flag */
+  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+  /* Disable Interrupts and Store Previous state */
+  if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+  {
+    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+    hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+  }
+  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+  {
+    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+    hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+  }
+  else
+  {
+    /* Do nothing */
+  }
+
+  /* Clear Configuration Register 2 */
+  I2C_RESET_CR2(hi2c);
+
+  /* Reset handle parameters */
+  hi2c->XferISR       = NULL;
+  hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
+
+  if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET)
+  {
+    /* Clear NACK Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    /* Set acknowledge error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+  }
+
+  /* Fetch Last receive data if any */
+  if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET))
+  {
+    /* Read data from RXDR */
+    tmp = (uint8_t)hi2c->Instance->RXDR;
+
+    UNUSED(tmp);
+  }
+
+  /* Flush TX register */
+  I2C_Flush_TXDR(hi2c);
+
+  /* Store current volatile hi2c->ErrorCode, misra rule */
+  tmperror = hi2c->ErrorCode;
+
+  /* Call the corresponding callback to inform upper layer of End of Transfer */
+  if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE))
+  {
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    I2C_ITError(hi2c, hi2c->ErrorCode);
+  }
+  /* hi2c->State == HAL_I2C_STATE_BUSY_TX */
+  else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    if (hi2c->Mode == HAL_I2C_MODE_MEM)
+    {
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->MemTxCpltCallback(hi2c);
+#else
+      HAL_I2C_MemTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+    else
+    {
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->MasterTxCpltCallback(hi2c);
+#else
+      HAL_I2C_MasterTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+  }
+  /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
+  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    if (hi2c->Mode == HAL_I2C_MODE_MEM)
+    {
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->MemRxCpltCallback(hi2c);
+#else
+      HAL_I2C_MemRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+    else
+    {
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->MasterRxCpltCallback(hi2c);
+#else
+      HAL_I2C_MasterRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+}
+
+/**
+  * @brief  I2C Slave complete process.
+  * @param  hi2c I2C handle.
+  * @param  ITFlags Interrupt flags to handle.
+  * @retval None
+  */
+static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+  uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
+  uint32_t tmpITFlags = ITFlags;
+  HAL_I2C_StateTypeDef tmpstate = hi2c->State;
+
+  /* Clear STOP Flag */
+  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+  /* Disable Interrupts and Store Previous state */
+  if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
+  {
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+  }
+  else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+  {
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
+    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+  }
+  else
+  {
+    /* Do nothing */
+  }
+
+  /* Disable Address Acknowledge */
+  hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+  /* Clear Configuration Register 2 */
+  I2C_RESET_CR2(hi2c);
+
+  /* Flush TX register */
+  I2C_Flush_TXDR(hi2c);
+
+  /* If a DMA is ongoing, Update handle size context */
+  if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+    if (hi2c->hdmatx != NULL)
+    {
+      hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx);
+    }
+  }
+  else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+    if (hi2c->hdmarx != NULL)
+    {
+      hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx);
+    }
+  }
+  else
+  {
+    /* Do nothing */
+  }
+
+  /* Store Last receive data if any */
+  if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)
+  {
+    /* Remove RXNE flag on temporary variable as read done */
+    tmpITFlags &= ~I2C_FLAG_RXNE;
+
+    /* Read data from RXDR */
+    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    if ((hi2c->XferSize > 0U))
+    {
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+    }
+  }
+
+  /* All data are not transferred, so set error code accordingly */
+  if (hi2c->XferCount != 0U)
+  {
+    /* Set ErrorCode corresponding to a Non-Acknowledge */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+  }
+
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+  hi2c->XferISR = NULL;
+
+  if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+  {
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    I2C_ITError(hi2c, hi2c->ErrorCode);
+
+    /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+    if (hi2c->State == HAL_I2C_STATE_LISTEN)
+    {
+      /* Call I2C Listen complete process */
+      I2C_ITListenCplt(hi2c, tmpITFlags);
+    }
+  }
+  else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+  {
+    /* Call the Sequential Complete callback, to inform upper layer of the end of Tranfer */
+    I2C_ITSlaveSeqCplt(hi2c);
+
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->ListenCpltCallback(hi2c);
+#else
+    HAL_I2C_ListenCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+  /* Call the corresponding callback to inform upper layer of End of Transfer */
+  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->SlaveRxCpltCallback(hi2c);
+#else
+    HAL_I2C_SlaveRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->SlaveTxCpltCallback(hi2c);
+#else
+    HAL_I2C_SlaveTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief  I2C Listen complete process.
+  * @param  hi2c I2C handle.
+  * @param  ITFlags Interrupt flags to handle.
+  * @retval None
+  */
+static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+  /* Reset handle parameters */
+  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+  hi2c->PreviousState = I2C_STATE_NONE;
+  hi2c->State = HAL_I2C_STATE_READY;
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+  hi2c->XferISR = NULL;
+
+  /* Store Last receive data if any */
+  if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET)
+  {
+    /* Read data from RXDR */
+    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    if ((hi2c->XferSize > 0U))
+    {
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+
+      /* Set ErrorCode corresponding to a Non-Acknowledge */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+    }
+  }
+
+  /* Disable all Interrupts*/
+  I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
+
+  /* Clear NACK Flag */
+  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+  hi2c->ListenCpltCallback(hi2c);
+#else
+  HAL_I2C_ListenCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  I2C interrupts error process.
+  * @param  hi2c I2C handle.
+  * @param  ErrorCode Error code to handle.
+  * @retval None
+  */
+static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
+{
+  HAL_I2C_StateTypeDef tmpstate = hi2c->State;
+  uint32_t tmppreviousstate;
+
+  /* Reset handle parameters */
+  hi2c->Mode          = HAL_I2C_MODE_NONE;
+  hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
+  hi2c->XferCount     = 0U;
+
+  /* Set new error code */
+  hi2c->ErrorCode |= ErrorCode;
+
+  /* Disable Interrupts */
+  if ((tmpstate == HAL_I2C_STATE_LISTEN)         ||
+      (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
+      (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+  {
+    /* Disable all interrupts, except interrupts related to LISTEN state */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
+
+    /* keep HAL_I2C_STATE_LISTEN if set */
+    hi2c->State         = HAL_I2C_STATE_LISTEN;
+    hi2c->XferISR       = I2C_Slave_ISR_IT;
+  }
+  else
+  {
+    /* Disable all interrupts */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
+
+    /* If state is an abort treatment on goind, don't change state */
+    /* This change will be do later */
+    if (hi2c->State != HAL_I2C_STATE_ABORT)
+    {
+      /* Set HAL_I2C_STATE_READY */
+      hi2c->State         = HAL_I2C_STATE_READY;
+    }
+    hi2c->XferISR       = NULL;
+  }
+
+  /* Abort DMA TX transfer if any */
+  tmppreviousstate = hi2c->PreviousState;
+  if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
+  {
+    if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+    {
+      hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+    }
+
+    if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
+    {
+      /* Set the I2C DMA Abort callback :
+       will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+      hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Abort DMA TX */
+      if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+      {
+        /* Call Directly XferAbortCallback function in case of error */
+        hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+      }
+    }
+    else
+    {
+      I2C_TreatErrorCallback(hi2c);
+    }
+  }
+  /* Abort DMA RX transfer if any */
+  else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
+  {
+    if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+    {
+      hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+    }
+
+    if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
+    {
+      /* Set the I2C DMA Abort callback :
+        will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+      hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Abort DMA RX */
+      if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+      {
+        /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
+        hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+      }
+    }
+    else
+    {
+      I2C_TreatErrorCallback(hi2c);
+    }
+  }
+  else
+  {
+    I2C_TreatErrorCallback(hi2c);
+  }
+}
+
+/**
+  * @brief  I2C Error callback treatment.
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c)
+{
+  if (hi2c->State == HAL_I2C_STATE_ABORT)
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->AbortCpltCallback(hi2c);
+#else
+    HAL_I2C_AbortCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    hi2c->PreviousState = I2C_STATE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->ErrorCallback(hi2c);
+#else
+    HAL_I2C_ErrorCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief  I2C Tx data register flush process.
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
+{
+  /* If a pending TXIS flag is set */
+  /* Write a dummy data in TXDR to clear it */
+  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
+  {
+    hi2c->Instance->TXDR = 0x00U;
+  }
+
+  /* Flush TX register if not empty */
+  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
+  {
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
+  }
+}
+
+/**
+  * @brief  DMA I2C master transmit process complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+
+  /* Disable DMA Request */
+  hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+  /* If last transfer, enable STOP interrupt */
+  if (hi2c->XferCount == 0U)
+  {
+    /* Enable STOP interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+  }
+  /* else prepare a new DMA transfer and enable TCReload interrupt */
+  else
+  {
+    /* Update Buffer pointer */
+    hi2c->pBuffPtr += hi2c->XferSize;
+
+    /* Set the XferSize to transfer */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+    }
+
+    /* Enable the DMA stream or channel depends on Instance */
+    if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize) != HAL_OK)
+    {
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+      I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+    }
+    else
+    {
+      /* Enable TC interrupts */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
+    }
+  }
+}
+
+/**
+  * @brief  DMA I2C slave transmit process complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+  uint32_t tmpoptions = hi2c->XferOptions;
+
+  if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+    /* Last Byte is Transmitted */
+    /* Call I2C Slave Sequential complete process */
+    I2C_ITSlaveSeqCplt(hi2c);
+  }
+  else
+  {
+    /* No specific action, Master fully manage the generation of STOP condition */
+    /* Mean that this generation can arrive at any time, at the end or during DMA process */
+    /* So STOP condition should be manage through Interrupt treatment */
+  }
+}
+
+/**
+  * @brief DMA I2C master receive process complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+
+  /* Disable DMA Request */
+  hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+  /* If last transfer, enable STOP interrupt */
+  if (hi2c->XferCount == 0U)
+  {
+    /* Enable STOP interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+  }
+  /* else prepare a new DMA transfer and enable TCReload interrupt */
+  else
+  {
+    /* Update Buffer pointer */
+    hi2c->pBuffPtr += hi2c->XferSize;
+
+    /* Set the XferSize to transfer */
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+    }
+
+    /* Enable the DMA stream or channel depends on Instance */
+    if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize) != HAL_OK)
+    {
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+      I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+    }
+    else
+    {
+      /* Enable TC interrupts */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
+    }
+  }
+}
+
+/**
+  * @brief  DMA I2C slave receive process complete callback.
+  * @param  hdma DMA handle
+  * @retval None
+  */
+static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+  uint32_t tmpoptions = hi2c->XferOptions;
+
+  if ((__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) && \
+      (tmpoptions != I2C_NO_OPTION_FRAME))
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+    /* Call I2C Slave Sequential complete process */
+    I2C_ITSlaveSeqCplt(hi2c);
+  }
+  else
+  {
+    /* No specific action, Master fully manage the generation of STOP condition */
+    /* Mean that this generation can arrive at any time, at the end or during DMA process */
+    /* So STOP condition should be manage through Interrupt treatment */
+  }
+}
+
+/**
+  * @brief  DMA I2C communication error callback.
+  * @param hdma DMA handle
+  * @retval None
+  */
+static void I2C_DMAError(DMA_HandleTypeDef *hdma)
+{
+  uint32_t treatdmaerror = 0U;
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+
+  if (hi2c->hdmatx != NULL)
+  {
+    if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U)
+    {
+      treatdmaerror = 1U;
+    }
+  }
+
+  if (hi2c->hdmarx != NULL)
+  {
+    if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U)
+    {
+      treatdmaerror = 1U;
+    }
+  }
+
+  /* Check if a FIFO error is detected, if true normal use case, so no specific action to perform */
+  if (!((HAL_DMA_GetError(hdma) == HAL_DMA_ERROR_FE)) && (treatdmaerror != 0U))
+  {
+    /* Disable Acknowledge */
+    hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+  }
+}
+
+/**
+  * @brief DMA I2C communication abort callback
+  *        (To be called at end of DMA Abort procedure).
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
+{
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+
+  /* Reset AbortCpltCallback */
+  if (hi2c->hdmatx != NULL)
+  {
+    hi2c->hdmatx->XferAbortCallback = NULL;
+  }
+  if (hi2c->hdmarx != NULL)
+  {
+    hi2c->hdmarx->XferAbortCallback = NULL;
+  }
+
+  I2C_TreatErrorCallback(hi2c);
+}
+
+/**
+  * @brief  This function handles I2C Communication Timeout.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Flag Specifies the I2C flag to check.
+  * @param  Status The new Flag status (SET or RESET).
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
+{
+  while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
+  {
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+      {
+        hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+        hi2c->State = HAL_I2C_STATE_READY;
+        hi2c->Mode = HAL_I2C_MODE_NONE;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+        return HAL_ERROR;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles I2C Communication Timeout for specific usage of TXIS flag.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+{
+  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
+  {
+    /* Check if a NACK is detected */
+    if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+      {
+        hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+        hi2c->State = HAL_I2C_STATE_READY;
+        hi2c->Mode = HAL_I2C_MODE_NONE;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles I2C Communication Timeout for specific usage of STOP flag.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+{
+  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+  {
+    /* Check if a NACK is detected */
+    if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Check for the Timeout */
+    if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+    {
+      hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+      hi2c->State = HAL_I2C_STATE_READY;
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles I2C Communication Timeout for specific usage of RXNE flag.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+{
+  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
+  {
+    /* Check if a NACK is detected */
+    if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Check if a STOPF is detected */
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
+    {
+      /* Check if an RXNE is pending */
+      /* Store Last receive data if any */
+      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U))
+      {
+        /* Return HAL_OK */
+        /* The Reading of data from RXDR will be done in caller function */
+        return HAL_OK;
+      }
+      else
+      {
+        /* Clear STOP Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+        /* Clear Configuration Register 2 */
+        I2C_RESET_CR2(hi2c);
+
+        hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+        hi2c->State = HAL_I2C_STATE_READY;
+        hi2c->Mode = HAL_I2C_MODE_NONE;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+
+    /* Check for the Timeout */
+    if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+    {
+      hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+      hi2c->State = HAL_I2C_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles Acknowledge failed detection during an I2C Communication.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+{
+  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+  {
+    /* Wait until STOP Flag is reset */
+    /* AutoEnd should be initiate after AF */
+    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+    {
+      /* Check for the Timeout */
+      if (Timeout != HAL_MAX_DELAY)
+      {
+        if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+        {
+          hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+          hi2c->State = HAL_I2C_STATE_READY;
+          hi2c->Mode = HAL_I2C_MODE_NONE;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2c);
+
+          return HAL_ERROR;
+        }
+      }
+    }
+
+    /* Clear NACKF Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    /* Clear STOP Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+    /* Flush TX register */
+    I2C_Flush_TXDR(hi2c);
+
+    /* Clear Configuration Register 2 */
+    I2C_RESET_CR2(hi2c);
+
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode = HAL_I2C_MODE_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_ERROR;
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
+  * @param  hi2c I2C handle.
+  * @param  DevAddress Specifies the slave address to be programmed.
+  * @param  Size Specifies the number of bytes to be programmed.
+  *   This parameter must be a value between 0 and 255.
+  * @param  Mode New state of the I2C START condition generation.
+  *   This parameter can be one of the following values:
+  *     @arg @ref I2C_RELOAD_MODE Enable Reload mode .
+  *     @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.
+  *     @arg @ref I2C_SOFTEND_MODE Enable Software end mode.
+  * @param  Request New state of the I2C START condition generation.
+  *   This parameter can be one of the following values:
+  *     @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.
+  *     @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
+  *     @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
+  *     @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
+  * @retval None
+  */
+static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  assert_param(IS_TRANSFER_MODE(Mode));
+  assert_param(IS_TRANSFER_REQUEST(Request));
+
+  /* update CR2 register */
+  MODIFY_REG(hi2c->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \
+             (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
+}
+
+/**
+  * @brief  Manage the enabling of Interrupts.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
+  * @retval None
+  */
+static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
+{
+  uint32_t tmpisr = 0U;
+
+  if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \
+      (hi2c->XferISR == I2C_Slave_ISR_DMA))
+  {
+    if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+    {
+      /* Enable ERR, STOP, NACK and ADDR interrupts */
+      tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+    }
+
+    if (InterruptRequest == I2C_XFER_ERROR_IT)
+    {
+      /* Enable ERR and NACK interrupts */
+      tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
+    }
+
+    if (InterruptRequest == I2C_XFER_CPLT_IT)
+    {
+      /* Enable STOP interrupts */
+      tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
+    }
+
+    if (InterruptRequest == I2C_XFER_RELOAD_IT)
+    {
+      /* Enable TC interrupts */
+      tmpisr |= I2C_IT_TCI;
+    }
+  }
+  else
+  {
+    if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+    {
+      /* Enable ERR, STOP, NACK, and ADDR interrupts */
+      tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+    }
+
+    if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
+    {
+      /* Enable ERR, TC, STOP, NACK and RXI interrupts */
+      tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
+    }
+
+    if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
+    {
+      /* Enable ERR, TC, STOP, NACK and TXI interrupts */
+      tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
+    }
+
+    if (InterruptRequest == I2C_XFER_CPLT_IT)
+    {
+      /* Enable STOP interrupts */
+      tmpisr |= I2C_IT_STOPI;
+    }
+  }
+
+  /* Enable interrupts only at the end */
+  /* to avoid the risk of I2C interrupt handle execution before */
+  /* all interrupts requested done */
+  __HAL_I2C_ENABLE_IT(hi2c, tmpisr);
+}
+
+/**
+  * @brief  Manage the disabling of Interrupts.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
+  * @retval None
+  */
+static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
+{
+  uint32_t tmpisr = 0U;
+
+  if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
+  {
+    /* Disable TC and TXI interrupts */
+    tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
+
+    if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
+    {
+      /* Disable NACK and STOP interrupts */
+      tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+    }
+  }
+
+  if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
+  {
+    /* Disable TC and RXI interrupts */
+    tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
+
+    if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
+    {
+      /* Disable NACK and STOP interrupts */
+      tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+    }
+  }
+
+  if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+  {
+    /* Disable ADDR, NACK and STOP interrupts */
+    tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+  }
+
+  if (InterruptRequest == I2C_XFER_ERROR_IT)
+  {
+    /* Enable ERR and NACK interrupts */
+    tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
+  }
+
+  if (InterruptRequest == I2C_XFER_CPLT_IT)
+  {
+    /* Enable STOP interrupts */
+    tmpisr |= I2C_IT_STOPI;
+  }
+
+  if (InterruptRequest == I2C_XFER_RELOAD_IT)
+  {
+    /* Enable TC interrupts */
+    tmpisr |= I2C_IT_TCI;
+  }
+
+  /* Disable interrupts only at the end */
+  /* to avoid a breaking situation like at "t" time */
+  /* all disable interrupts request are not done */
+  __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
+}
+
+/**
+  * @brief  Convert I2Cx OTHER_xxx XferOptions to functionnal XferOptions.
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
+{
+  /* if user set XferOptions to I2C_OTHER_FRAME            */
+  /* it request implicitly to generate a restart condition */
+  /* set XferOptions to I2C_FIRST_FRAME                    */
+  if (hi2c->XferOptions == I2C_OTHER_FRAME)
+  {
+    hi2c->XferOptions = I2C_FIRST_FRAME;
+  }
+  /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
+  /* it request implicitly to generate a restart condition    */
+  /* then generate a stop condition at the end of transfer    */
+  /* set XferOptions to I2C_FIRST_AND_LAST_FRAME              */
+  else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
+  {
+    hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_I2C_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c
new file mode 100644
index 00000000..ea50ce31
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c
@@ -0,0 +1,339 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_i2c_ex.c
+  * @author  MCD Application Team
+  * @brief   I2C Extended HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of I2C Extended peripheral:
+  *           + Extended features functions
+  *
+  @verbatim
+  ==============================================================================
+               ##### I2C peripheral Extended features  #####
+  ==============================================================================
+
+  [..] Comparing to other previous devices, the I2C interface for STM32H7xx
+       devices contains the following additional features
+
+       (+) Possibility to disable or enable Analog Noise Filter
+       (+) Use of a configured Digital Noise Filter
+       (+) Disable or enable wakeup from Stop mode(s)
+       (+) Disable or enable Fast Mode Plus
+
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..] This driver provides functions to configure Noise Filter and Wake Up Feature
+    (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
+    (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
+    (#) Configure the enable or disable of I2C Wake Up Mode using the functions :
+          (++) HAL_I2CEx_EnableWakeUp()
+          (++) HAL_I2CEx_DisableWakeUp()
+    (#) Configure the enable or disable of fast mode plus driving capability using the functions :
+          (++) HAL_I2CEx_EnableFastModePlus()
+          (++) HAL_I2CEx_DisableFastModePlus()
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup I2CEx I2CEx
+  * @brief I2C Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions
+  * @brief    Extended features functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### Extended features functions #####
+ ===============================================================================
+    [..] This section provides functions allowing to:
+      (+) Configure Noise Filters
+      (+) Configure Wake Up Feature
+      (+) Configure Fast Mode Plus
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure I2C Analog noise filter.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2Cx peripheral.
+  * @param  AnalogFilter New state of the Analog filter.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+
+    /* Disable the selected I2C peripheral */
+    __HAL_I2C_DISABLE(hi2c);
+
+    /* Reset I2Cx ANOFF bit */
+    hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
+
+    /* Set analog filter bit*/
+    hi2c->Instance->CR1 |= AnalogFilter;
+
+    __HAL_I2C_ENABLE(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Configure I2C Digital noise filter.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2Cx peripheral.
+  * @param  DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
+{
+  uint32_t tmpreg;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+
+    /* Disable the selected I2C peripheral */
+    __HAL_I2C_DISABLE(hi2c);
+
+    /* Get the old register value */
+    tmpreg = hi2c->Instance->CR1;
+
+    /* Reset I2Cx DNF bits [11:8] */
+    tmpreg &= ~(I2C_CR1_DNF);
+
+    /* Set I2Cx DNF coefficient */
+    tmpreg |= DigitalFilter << 8U;
+
+    /* Store the new register value */
+    hi2c->Instance->CR1 = tmpreg;
+
+    __HAL_I2C_ENABLE(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Enable I2C wakeup from Stop mode(s).
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2Cx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+
+    /* Disable the selected I2C peripheral */
+    __HAL_I2C_DISABLE(hi2c);
+
+    /* Enable wakeup from stop mode */
+    hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
+
+    __HAL_I2C_ENABLE(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Disable I2C wakeup from Stop mode(s).
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2Cx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+
+    /* Disable the selected I2C peripheral */
+    __HAL_I2C_DISABLE(hi2c);
+
+    /* Enable wakeup from stop mode */
+    hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
+
+    __HAL_I2C_ENABLE(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Enable the I2C fast mode plus driving capability.
+  * @param ConfigFastModePlus Selects the pin.
+  *   This parameter can be one of the @ref I2CEx_FastModePlus values
+  * @note  For I2C1, fast mode plus driving capability can be enabled on all selected
+  *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
+  *        on each one of the following pins PB6, PB7, PB8 and PB9.
+  * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
+  *        can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
+  * @note  For all I2C2 pins fast mode plus driving capability can be enabled
+  *        only by using I2C_FASTMODEPLUS_I2C2 parameter.
+  * @note  For all I2C3 pins fast mode plus driving capability can be enabled
+  *        only by using I2C_FASTMODEPLUS_I2C3 parameter.
+  * @note  For all I2C4 pins fast mode plus driving capability can be enabled
+  *        only by using I2C_FASTMODEPLUS_I2C4 parameter.
+  * @retval None
+  */
+void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
+{
+  /* Check the parameter */
+  assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
+
+  /* Enable SYSCFG clock */
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+  /* Enable fast mode plus driving capability for selected pin */
+  SET_BIT(SYSCFG->PMCR, (uint32_t)ConfigFastModePlus);
+}
+
+/**
+  * @brief Disable the I2C fast mode plus driving capability.
+  * @param ConfigFastModePlus Selects the pin.
+  *   This parameter can be one of the @ref I2CEx_FastModePlus values
+  * @note  For I2C1, fast mode plus driving capability can be disabled on all selected
+  *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
+  *        on each one of the following pins PB6, PB7, PB8 and PB9.
+  * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
+  *        can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
+  * @note  For all I2C2 pins fast mode plus driving capability can be disabled
+  *        only by using I2C_FASTMODEPLUS_I2C2 parameter.
+  * @note  For all I2C3 pins fast mode plus driving capability can be disabled
+  *        only by using I2C_FASTMODEPLUS_I2C3 parameter.
+  * @note  For all I2C4 pins fast mode plus driving capability can be disabled
+  *        only by using I2C_FASTMODEPLUS_I2C4 parameter.
+  * @retval None
+  */
+void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
+{
+  /* Check the parameter */
+  assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
+
+  /* Enable SYSCFG clock */
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+  /* Disable fast mode plus driving capability for selected pin */
+  CLEAR_BIT(SYSCFG->PMCR, (uint32_t)ConfigFastModePlus);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_I2C_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c
new file mode 100644
index 00000000..08498c46
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c
@@ -0,0 +1,1901 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_mdma.c
+  * @author  MCD Application Team
+  * @brief  This file provides firmware functions to manage the following
+  *         functionalities of the Master Direct Memory Access (MDMA) peripheral:
+  *           + Initialization/de-initialization functions
+  *           + I/O operation functions
+  *           + Peripheral State and errors functions
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+   (#) Enable and configure the peripheral to be connected to the MDMA Channel
+       (except for internal SRAM/FLASH memories: no initialization is
+       necessary) please refer to Reference manual for connection between peripherals
+       and MDMA requests.
+
+   (#)
+       For a given Channel use HAL_MDMA_Init function to program the required configuration through the following parameters:
+       transfer request , channel priority, data endianness, Source increment, destination increment ,
+       source data size, destination data size, data alignment, source Burst, destination Burst ,
+       buffer Transfer Length, Transfer Trigger Mode (buffer transfer, block transfer, repeated block transfer
+       or full transfer) source and destination block address offset, mask address and data.
+
+       If using the MDMA in linked list mode then use function HAL_MDMA_LinkedList_CreateNode to fill a transfer node.
+       Note that parameters given to the function HAL_MDMA_Init corresponds always to the node zero.
+       Use function HAL_MDMA_LinkedList_AddNode to connect the created node to the linked list at a given position.
+       User can make a linked list circular using function HAL_MDMA_LinkedList_EnableCircularMode , this function will automatically connect the
+       last node of the list to the first one in order to make the list circular.
+       In this case the linked list will loop on node 1 : first node connected after the initial transfer defined by the HAL_MDMA_Init
+
+      -@-   The initial transfer itself (node 0 corresponding to the Init).
+            User can disable the circular mode using function HAL_MDMA_LinkedList_DisableCircularMode, this function will then remove
+            the connection between last node and first one.
+
+       Function HAL_MDMA_LinkedList_RemoveNode can be used to remove (disconnect) a node from the transfer linked list.
+       When a linked list is circular (last node connected to first one), if removing node1  (node where the linked list loops),
+       the linked list remains circular and node 2 becomes the first one.
+       Note that if the linked list is made circular the transfer will loop infinitely (or until aborted by the user).
+
+    [..]
+       (+) User can select the transfer trigger mode (parameter TransferTriggerMode) to define the amount of data to be
+           transfer upon a request :
+             (++) MDMA_BUFFER_TRANSFER : each request triggers a transfer of BufferTransferLength data
+               with BufferTransferLength defined within the HAL_MDMA_Init.
+             (++) MDMA_BLOCK_TRANSFER : each request triggers a transfer of a block
+               with block size defined within the function HAL_MDMA_Start/HAL_MDMA_Start_IT
+               or within the current linked list node parameters.
+             (++) MDMA_REPEAT_BLOCK_TRANSFER : each request triggers a transfer of a number of blocks
+               with block size and number of blocks defined within the function HAL_MDMA_Start/HAL_MDMA_Start_IT
+               or within the current linked list node parameters.
+             (++) MDMA_FULL_TRANSFER : each request triggers a full transfer
+              all blocks and all nodes(if a linked list has been created using HAL_MDMA_LinkedList_CreateNode \ HAL_MDMA_LinkedList_AddNode).
+
+     *** Polling mode IO operation ***
+     =================================
+    [..]
+          (+) Use HAL_MDMA_Start() to start MDMA transfer after the configuration of Source
+              address and destination address and the Length of data to be transferred.
+          (+) Use HAL_MDMA_PollForTransfer() to poll for the end of current transfer or a transfer level
+             In this case a fixed Timeout can be configured by User depending from his application.
+          (+) Use HAL_MDMA_Abort() function to abort the current transfer : blocking method this API returns
+              when the abort ends or timeout (should not be called from an interrupt service routine).
+
+     *** Interrupt mode IO operation ***
+     ===================================
+    [..]
+          (+) Configure the MDMA interrupt priority using HAL_NVIC_SetPriority()
+          (+) Enable the MDMA IRQ handler using HAL_NVIC_EnableIRQ()
+          (+) Use HAL_MDMA_Start_IT() to start MDMA transfer after the configuration of
+              Source address and destination address and the Length of data to be transferred. In this
+              case the MDMA interrupt is configured.
+          (+) Use HAL_MDMA_IRQHandler() called under MDMA_IRQHandler() Interrupt subroutine
+          (+) At the end of data transfer HAL_MDMA_IRQHandler() function is executed and user can
+              add his own function by customization of function pointer XferCpltCallback and
+              XferErrorCallback (i.e a member of MDMA handle structure).
+
+          (+) Use HAL_MDMA_Abort_IT() function to abort the current transfer : non-blocking method. This API will finish the execution immediately
+              then the callback XferAbortCallback (if specified  by the user) is asserted once the MDMA channel has effectively aborted.
+              (could be called from an interrupt service routine).
+
+          (+) Use functions HAL_MDMA_RegisterCallback and HAL_MDMA_UnRegisterCallback respectevely to register unregister user callbacks
+              from the following list :
+              (++) XferCpltCallback            : transfer complete callback.
+              (++) XferBufferCpltCallback      : buffer transfer complete callback.
+              (++) XferBlockCpltCallback       : block transfer complete callback.
+              (++) XferRepeatBlockCpltCallback : repeated block transfer complete callback.
+              (++) XferErrorCallback           : transfer error callback.
+              (++) XferAbortCallback           : transfer abort complete callback.
+
+    [..]
+         (+)  If the transfer Request corresponds to SW request (MDMA_REQUEST_SW) User can use function HAL_MDMA_GenerateSWRequest to
+              trigger requests manually. Function HAL_MDMA_GenerateSWRequest must be used with the following precautions:
+              (++) This function returns an error if used while the Transfer has ended or not started.
+              (++) If used while the current request has not been served yet (current request transfer on going)
+                this function returns an error and the new request is ignored.
+
+              Generally this function should be used in conjunctions with the MDMA callbacks:
+              (++) example 1:
+                 (+++) Configure a transfer with request set to MDMA_REQUEST_SW and trigger mode set to MDMA_BUFFER_TRANSFER
+                 (+++) Register a callback for buffer transfer complete (using callback ID set to HAL_MDMA_XFER_BUFFERCPLT_CB_ID)
+                 (+++) After calling HAL_MDMA_Start_IT the MDMA will issue the transfer of a first BufferTransferLength data.
+                 (+++) When the buffer transfer complete callback is asserted first buffer has been transferred and user can ask for a new buffer transfer
+                   request using HAL_MDMA_GenerateSWRequest.
+
+              (++) example 2:
+                 (+++) Configure a transfer with request set to MDMA_REQUEST_SW and trigger mode set to MDMA_BLOCK_TRANSFER
+                 (+++) Register a callback for block transfer complete (using callback ID HAL_MDMA_XFER_BLOCKCPLT_CB_ID)
+                 (+++) After calling HAL_MDMA_Start_IT the MDMA will issue the transfer of a first block of data.
+                 (+++) When the block transfer complete callback is asserted the first block has been transferred and user can ask
+                   for a new block transfer request using HAL_MDMA_GenerateSWRequest.
+
+    [..]  Use HAL_MDMA_GetState() function to return the MDMA state and HAL_MDMA_GetError() in case of error detection.
+
+     *** MDMA HAL driver macros list ***
+     =============================================
+     [..]
+       Below the list of most used macros in MDMA HAL driver.
+
+      (+) __HAL_MDMA_ENABLE: Enable the specified MDMA Channel.
+      (+) __HAL_MDMA_DISABLE: Disable the specified MDMA Channel.
+      (+) __HAL_MDMA_GET_FLAG: Get the MDMA Channel pending flags.
+      (+) __HAL_MDMA_CLEAR_FLAG: Clear the MDMA Channel pending flags.
+      (+) __HAL_MDMA_ENABLE_IT: Enable the specified MDMA Channel interrupts.
+      (+) __HAL_MDMA_DISABLE_IT: Disable the specified MDMA Channel interrupts.
+      (+) __HAL_MDMA_GET_IT_SOURCE: Check whether the specified MDMA Channel interrupt has occurred or not.
+
+     [..]
+      (@) You can refer to the header file of the MDMA HAL driver for more useful macros.
+
+    [..]
+
+    @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup MDMA  MDMA
+  * @brief MDMA HAL module driver
+  * @{
+  */
+
+#ifdef HAL_MDMA_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup MDMA_Private_Constants
+ * @{
+ */
+#define HAL_TIMEOUT_MDMA_ABORT    5U    /* 5 ms */
+#define HAL_MDMA_CHANNEL_SIZE     0x40U /* an MDMA instance channel size is 64 byte  */
+/**
+  * @}
+  */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup MDMA_Private_Functions_Prototypes
+  * @{
+  */
+static void MDMA_SetConfig(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount);
+static void MDMA_Init(MDMA_HandleTypeDef *hmdma);
+
+/**
+  * @}
+  */
+
+/** @addtogroup MDMA_Exported_Functions MDMA Exported Functions
+  * @{
+  */
+
+/** @addtogroup MDMA_Exported_Functions_Group1
+  *
+@verbatim
+ ===============================================================================
+             ##### Initialization and de-initialization functions  #####
+ ===============================================================================
+    [..]
+    This section provides functions allowing to :
+      Initialize and de-initialize the MDMA channel.
+      Register and Unregister MDMA callbacks
+    [..]
+    The HAL_MDMA_Init() function follows the MDMA channel configuration procedures as described in
+    reference manual.
+    The HAL_MDMA_DeInit function allows to deinitialize the MDMA channel.
+    HAL_MDMA_RegisterCallback and  HAL_MDMA_UnRegisterCallback functions allows
+    respectevely to register/unregister an MDMA callback function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the MDMA according to the specified
+  *         parameters in the MDMA_InitTypeDef and create the associated handle.
+  * @param  hmdma: Pointer to a MDMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified MDMA Channel.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_Init(MDMA_HandleTypeDef *hmdma)
+{
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_MDMA_STREAM_ALL_INSTANCE(hmdma->Instance));
+  assert_param(IS_MDMA_PRIORITY(hmdma->Init.Priority));
+  assert_param(IS_MDMA_ENDIANNESS_MODE(hmdma->Init.Endianness));
+  assert_param(IS_MDMA_REQUEST(hmdma->Init.Request));
+  assert_param(IS_MDMA_SOURCE_INC(hmdma->Init.SourceInc));
+  assert_param(IS_MDMA_DESTINATION_INC(hmdma->Init.DestinationInc));
+  assert_param(IS_MDMA_SOURCE_DATASIZE(hmdma->Init.SourceDataSize));
+  assert_param(IS_MDMA_DESTINATION_DATASIZE(hmdma->Init.DestDataSize));
+  assert_param(IS_MDMA_DATA_ALIGNMENT(hmdma->Init.DataAlignment));
+  assert_param(IS_MDMA_SOURCE_BURST(hmdma->Init.SourceBurst));
+  assert_param(IS_MDMA_DESTINATION_BURST(hmdma->Init.DestBurst));
+  assert_param(IS_MDMA_BUFFER_TRANSFER_LENGTH(hmdma->Init.BufferTransferLength));
+  assert_param(IS_MDMA_TRANSFER_TRIGGER_MODE(hmdma->Init.TransferTriggerMode));
+  assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(hmdma->Init.SourceBlockAddressOffset));
+  assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(hmdma->Init.DestBlockAddressOffset));
+
+
+  /* Allocate lock resource */
+  __HAL_UNLOCK(hmdma);
+
+  /* Change MDMA peripheral state */
+  hmdma->State = HAL_MDMA_STATE_BUSY;
+
+  /* Disable the MDMA channel */
+  __HAL_MDMA_DISABLE(hmdma);
+
+  /* Check if the MDMA channel is effectively disabled */
+  while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U)
+  {
+    /* Check for the Timeout */
+    if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_MDMA_ABORT)
+    {
+      /* Update error code */
+      hmdma->ErrorCode = HAL_MDMA_ERROR_TIMEOUT;
+
+      /* Change the MDMA state */
+      hmdma->State = HAL_MDMA_STATE_ERROR;
+
+      return HAL_ERROR;
+    }
+  }
+
+  /* Initialize the MDMA channel registers */
+  MDMA_Init(hmdma);
+
+  /* Reset the MDMA first/last linkedlist node addresses and node counter */
+  hmdma->FirstLinkedListNodeAddress  = 0;
+  hmdma->LastLinkedListNodeAddress   = 0;
+  hmdma->LinkedListNodeCounter  = 0;
+
+  /* Initialize the error code */
+  hmdma->ErrorCode = HAL_MDMA_ERROR_NONE;
+
+  /* Initialize the MDMA state */
+  hmdma->State = HAL_MDMA_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the MDMA peripheral
+  * @param  hmdma: pointer to a MDMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified MDMA Channel.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_DeInit(MDMA_HandleTypeDef *hmdma)
+{
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Disable the selected MDMA Channelx */
+  __HAL_MDMA_DISABLE(hmdma);
+
+  /* Reset MDMA Channel control register */
+  hmdma->Instance->CCR  = 0;
+  hmdma->Instance->CTCR = 0;
+  hmdma->Instance->CBNDTR = 0;
+  hmdma->Instance->CSAR = 0;
+  hmdma->Instance->CDAR = 0;
+  hmdma->Instance->CBRUR = 0;
+  hmdma->Instance->CLAR = 0;
+  hmdma->Instance->CTBR = 0;
+  hmdma->Instance->CMAR = 0;
+  hmdma->Instance->CMDR = 0;
+
+  /* Clear all flags */
+  __HAL_MDMA_CLEAR_FLAG(hmdma,(MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_FLAG_BRT | MDMA_FLAG_BT | MDMA_FLAG_BFTC));
+
+  /* Reset the  MDMA first/last linkedlist node addresses and node counter */
+  hmdma->FirstLinkedListNodeAddress  = 0;
+  hmdma->LastLinkedListNodeAddress   = 0;
+  hmdma->LinkedListNodeCounter  = 0;
+
+  /* Initialize the error code */
+  hmdma->ErrorCode = HAL_MDMA_ERROR_NONE;
+
+  /* Initialize the MDMA state */
+  hmdma->State = HAL_MDMA_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hmdma);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Config the Post request Mask address and Mask data
+  * @param  hmdma      : pointer to a MDMA_HandleTypeDef structure that contains
+  *                               the configuration information for the specified MDMA Channel.
+  * @param  MaskAddress: specifies the address to be updated (written) with MaskData after a request is served.
+  * @param  MaskData:    specifies the value to be written to MaskAddress after a request is served.
+  *                      MaskAddress and MaskData could be used to automatically clear a peripheral flag when the request is served.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_ConfigPostRequestMask(MDMA_HandleTypeDef *hmdma, uint32_t MaskAddress, uint32_t MaskData)
+{
+  HAL_StatusTypeDef  status = HAL_OK;
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hmdma);
+
+  if(HAL_MDMA_STATE_READY == hmdma->State)
+  {
+    /* if HW request set Post Request MaskAddress and MaskData,  */
+    if((hmdma->Instance->CTCR & MDMA_CTCR_SWRM) == 0U)
+    {
+      /* Set the HW request clear Mask and Data */
+      hmdma->Instance->CMAR = MaskAddress;
+      hmdma->Instance->CMDR = MaskData;
+
+      /*
+      -If the request is done by SW : BWM could be set to 1 or 0.
+      -If the request is done by a peripheral :
+         If mask address not set (0) => BWM must be set to 0
+         If mask address set (different than 0) => BWM could be set to 1 or 0
+      */
+      if(MaskAddress == 0U)
+      {
+        hmdma->Instance->CTCR &=  ~MDMA_CTCR_BWM;
+      }
+      else
+      {
+        hmdma->Instance->CTCR |=  MDMA_CTCR_BWM;
+      }
+    }
+    else
+    {
+      /* Return error status */
+      status =  HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+  /* Release Lock */
+  __HAL_UNLOCK(hmdma);
+
+  return status;
+}
+
+/**
+  * @brief  Register callbacks
+  * @param  hmdma:                pointer to a MDMA_HandleTypeDef structure that contains
+  *                               the configuration information for the specified MDMA Channel.
+  * @param  CallbackID:           User Callback identifier
+  * @param  pCallback:            pointer to callbacsk function.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_RegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID, void (* pCallback)(MDMA_HandleTypeDef *_hmdma))
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hmdma);
+
+  if(HAL_MDMA_STATE_READY == hmdma->State)
+  {
+    switch (CallbackID)
+    {
+    case  HAL_MDMA_XFER_CPLT_CB_ID:
+      hmdma->XferCpltCallback = pCallback;
+      break;
+
+    case  HAL_MDMA_XFER_BUFFERCPLT_CB_ID:
+      hmdma->XferBufferCpltCallback = pCallback;
+      break;
+
+    case  HAL_MDMA_XFER_BLOCKCPLT_CB_ID:
+      hmdma->XferBlockCpltCallback = pCallback;
+      break;
+
+    case  HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID:
+      hmdma->XferRepeatBlockCpltCallback = pCallback;
+      break;
+
+    case  HAL_MDMA_XFER_ERROR_CB_ID:
+      hmdma->XferErrorCallback = pCallback;
+      break;
+
+    case  HAL_MDMA_XFER_ABORT_CB_ID:
+      hmdma->XferAbortCallback = pCallback;
+      break;
+
+    default:
+      break;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hmdma);
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister callbacks
+  * @param  hmdma:                 pointer to a MDMA_HandleTypeDef structure that contains
+  *                               the configuration information for the specified MDMA Channel.
+  * @param  CallbackID:           User Callback identifier
+  *                               a HAL_MDMA_CallbackIDTypeDef ENUM as parameter.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_UnRegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hmdma);
+
+  if(HAL_MDMA_STATE_READY == hmdma->State)
+  {
+    switch (CallbackID)
+    {
+    case  HAL_MDMA_XFER_CPLT_CB_ID:
+      hmdma->XferCpltCallback = NULL;
+      break;
+
+    case  HAL_MDMA_XFER_BUFFERCPLT_CB_ID:
+      hmdma->XferBufferCpltCallback = NULL;
+      break;
+
+    case  HAL_MDMA_XFER_BLOCKCPLT_CB_ID:
+      hmdma->XferBlockCpltCallback = NULL;
+      break;
+
+    case  HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID:
+      hmdma->XferRepeatBlockCpltCallback = NULL;
+      break;
+
+    case  HAL_MDMA_XFER_ERROR_CB_ID:
+      hmdma->XferErrorCallback = NULL;
+      break;
+
+    case  HAL_MDMA_XFER_ABORT_CB_ID:
+      hmdma->XferAbortCallback = NULL;
+      break;
+
+    case   HAL_MDMA_XFER_ALL_CB_ID:
+      hmdma->XferCpltCallback = NULL;
+      hmdma->XferBufferCpltCallback = NULL;
+      hmdma->XferBlockCpltCallback = NULL;
+      hmdma->XferRepeatBlockCpltCallback = NULL;
+      hmdma->XferErrorCallback = NULL;
+      hmdma->XferAbortCallback = NULL;
+      break;
+
+    default:
+      status = HAL_ERROR;
+      break;
+    }
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hmdma);
+
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup MDMA_Exported_Functions_Group2
+ *
+@verbatim
+ ===============================================================================
+                      #####  Linked list operation functions  #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Create a linked list node
+      (+) Add a node to the MDMA linked list
+      (+) Remove a node from the MDMA linked list
+      (+) Enable/Disable linked list circular mode
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes an MDMA Link Node according to the specified
+  *         parameters in the pMDMA_LinkedListNodeConfig .
+  * @param  pNode: Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node
+  *         registers configurations.
+  * @param  pNodeConfig: Pointer to a MDMA_LinkNodeConfTypeDef structure that contains
+  *               the configuration information for the specified MDMA Linked List Node.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig)
+{
+  uint32_t addressMask;
+  uint32_t blockoffset;
+
+  /* Check the MDMA peripheral state */
+  if((pNode == NULL) || (pNodeConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_MDMA_PRIORITY(pNodeConfig->Init.Priority));
+  assert_param(IS_MDMA_ENDIANNESS_MODE(pNodeConfig->Init.Endianness));
+  assert_param(IS_MDMA_REQUEST(pNodeConfig->Init.Request));
+  assert_param(IS_MDMA_SOURCE_INC(pNodeConfig->Init.SourceInc));
+  assert_param(IS_MDMA_DESTINATION_INC(pNodeConfig->Init.DestinationInc));
+  assert_param(IS_MDMA_SOURCE_DATASIZE(pNodeConfig->Init.SourceDataSize));
+  assert_param(IS_MDMA_DESTINATION_DATASIZE(pNodeConfig->Init.DestDataSize));
+  assert_param(IS_MDMA_DATA_ALIGNMENT(pNodeConfig->Init.DataAlignment));
+  assert_param(IS_MDMA_SOURCE_BURST(pNodeConfig->Init.SourceBurst));
+  assert_param(IS_MDMA_DESTINATION_BURST(pNodeConfig->Init.DestBurst));
+  assert_param(IS_MDMA_BUFFER_TRANSFER_LENGTH(pNodeConfig->Init.BufferTransferLength));
+  assert_param(IS_MDMA_TRANSFER_TRIGGER_MODE(pNodeConfig->Init.TransferTriggerMode));
+  assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(pNodeConfig->Init.SourceBlockAddressOffset));
+  assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(pNodeConfig->Init.DestBlockAddressOffset));
+
+  assert_param(IS_MDMA_TRANSFER_LENGTH(pNodeConfig->BlockDataLength));
+  assert_param(IS_MDMA_BLOCK_COUNT(pNodeConfig->BlockCount));
+
+
+  /* Configure next Link node Address Register to zero */
+  pNode->CLAR =  0;
+
+  /* Configure the Link Node registers*/
+  pNode->CTBR   = 0;
+  pNode->CMAR   = 0;
+  pNode->CMDR   = 0;
+  pNode->Reserved = 0;
+
+  /* Write new CTCR Register value */
+  pNode->CTCR =  pNodeConfig->Init.SourceInc | pNodeConfig->Init.DestinationInc | \
+    pNodeConfig->Init.SourceDataSize | pNodeConfig->Init.DestDataSize           | \
+      pNodeConfig->Init.DataAlignment| pNodeConfig->Init.SourceBurst            | \
+        pNodeConfig->Init.DestBurst                                             | \
+          ((pNodeConfig->Init.BufferTransferLength - 1U) << MDMA_CTCR_TLEN_Pos) | \
+            pNodeConfig->Init.TransferTriggerMode;
+
+  /* If SW request set the CTCR register to SW Request Mode*/
+  if(pNodeConfig->Init.Request == MDMA_REQUEST_SW)
+  {
+    pNode->CTCR |= MDMA_CTCR_SWRM;
+  }
+
+  /*
+  -If the request is done by SW : BWM could be set to 1 or 0.
+  -If the request is done by a peripheral :
+     If mask address not set (0) => BWM must be set to 0
+     If mask address set (different than 0) => BWM could be set to 1 or 0
+  */
+  if((pNodeConfig->Init.Request == MDMA_REQUEST_SW) || (pNodeConfig->PostRequestMaskAddress != 0U))
+  {
+    pNode->CTCR |=  MDMA_CTCR_BWM;
+  }
+
+  /* Set the new CBNDTR Register value */
+  pNode->CBNDTR = ((pNodeConfig->BlockCount - 1U) << MDMA_CBNDTR_BRC_Pos) & MDMA_CBNDTR_BRC;
+
+  /* if block source address offset is negative set the Block Repeat Source address Update Mode to decrement */
+  if(pNodeConfig->Init.SourceBlockAddressOffset < 0)
+  {
+    pNode->CBNDTR |= MDMA_CBNDTR_BRSUM;
+    /*write new CBRUR Register value : source repeat block offset */
+    blockoffset = (uint32_t)(- pNodeConfig->Init.SourceBlockAddressOffset);
+    pNode->CBRUR = blockoffset & 0x0000FFFFU;
+  }
+  else
+  {
+    /*write new CBRUR Register value : source repeat block offset */
+    pNode->CBRUR = (((uint32_t) pNodeConfig->Init.SourceBlockAddressOffset) & 0x0000FFFFU);
+  }
+
+  /* if block destination address offset is negative set the Block Repeat destination address Update Mode to decrement */
+  if(pNodeConfig->Init.DestBlockAddressOffset < 0)
+  {
+    pNode->CBNDTR |= MDMA_CBNDTR_BRDUM;
+    /*write new CBRUR Register value : destination repeat block offset */
+    blockoffset = (uint32_t)(- pNodeConfig->Init.DestBlockAddressOffset);
+    pNode->CBRUR |= ((blockoffset & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos);
+  }
+  else
+  {
+    /*write new CBRUR Register value : destination repeat block offset */
+    pNode->CBRUR |= ((((uint32_t)pNodeConfig->Init.DestBlockAddressOffset) & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos);
+  }
+
+  /* Configure MDMA Link Node data length */
+  pNode->CBNDTR |=  pNodeConfig->BlockDataLength;
+
+  /* Configure MDMA Link Node destination address */
+  pNode->CDAR = pNodeConfig->DstAddress;
+
+  /* Configure MDMA Link Node Source address */
+  pNode->CSAR = pNodeConfig->SrcAddress;
+
+  /* if HW request set the HW request and the requet CleraMask and ClearData MaskData,  */
+  if(pNodeConfig->Init.Request != MDMA_REQUEST_SW)
+  {
+    /* Set the HW request in CTBR register  */
+    pNode->CTBR = pNodeConfig->Init.Request & MDMA_CTBR_TSEL;
+    /* Set the HW request clear Mask and Data */
+    pNode->CMAR = pNodeConfig->PostRequestMaskAddress;
+    pNode->CMDR = pNodeConfig->PostRequestMaskData;
+  }
+
+  addressMask = pNodeConfig->SrcAddress & 0xFF000000U;
+  if((addressMask == 0x20000000U) || (addressMask == 0x00000000U))
+  {
+    /*The AHBSbus is used as source (read operation) on channel x */
+    pNode->CTBR |= MDMA_CTBR_SBUS;
+  }
+
+  addressMask = pNodeConfig->DstAddress & 0xFF000000U;
+  if((addressMask == 0x20000000U) || (addressMask == 0x00000000U))
+  {
+    /*The AHB bus is used as destination (write operation) on channel x */
+    pNode->CTBR |= MDMA_CTBR_DBUS;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Connect a node to the linked list.
+  * @param  hmdma    : Pointer to a MDMA_HandleTypeDef structure that contains
+  *                    the configuration information for the specified MDMA Channel.
+  * @param  pNewNode : Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node
+  *                    to be add to the list.
+  * @param pPrevNode : Pointer to the new node position in the linked list or zero to insert the new node
+  *                    at the end of the list
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, MDMA_LinkNodeTypeDef *pPrevNode)
+{
+  MDMA_LinkNodeTypeDef *pNode;
+  uint32_t counter = 0, nodeInserted = 0;
+  HAL_StatusTypeDef hal_status = HAL_OK;
+
+  /* Check the MDMA peripheral handle */
+  if((hmdma == NULL) || (pNewNode == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hmdma);
+
+  if(HAL_MDMA_STATE_READY == hmdma->State)
+  {
+    /* Change MDMA peripheral state */
+    hmdma->State = HAL_MDMA_STATE_BUSY;
+
+    /* Check if this is the first node (after the Inititlization node) */
+    if((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U)
+    {
+      if(pPrevNode == NULL)
+      {
+        /* if this is the first node after the initialization
+        connect this node to the node 0 by updating
+        the MDMA channel CLAR register to this node address */
+        hmdma->Instance->CLAR = (uint32_t)pNewNode;
+        /* Set the MDMA handle First linked List node*/
+        hmdma->FirstLinkedListNodeAddress = pNewNode;
+
+        /*reset New node link */
+        pNewNode->CLAR = 0;
+
+        /* Update the Handle last node address */
+        hmdma->LastLinkedListNodeAddress = pNewNode;
+
+        hmdma->LinkedListNodeCounter = 1;
+      }
+      else
+      {
+        hal_status = HAL_ERROR;
+      }
+    }
+    else if(hmdma->FirstLinkedListNodeAddress != pNewNode)
+    {
+      /* Check if the node to insert already exists*/
+      pNode = hmdma->FirstLinkedListNodeAddress;
+      while((counter < hmdma->LinkedListNodeCounter) && (hal_status == HAL_OK))
+      {
+        if(pNode->CLAR == (uint32_t)pNewNode)
+        {
+          hal_status = HAL_ERROR; /* error this node already exist in the linked list and it is not first node */
+        }
+        pNode = (MDMA_LinkNodeTypeDef *)pNode->CLAR;
+        counter++;
+      }
+
+      if(hal_status == HAL_OK)
+      {
+        /* Check if the previous node is the last one in the current list or zero */
+        if((pPrevNode == hmdma->LastLinkedListNodeAddress) || (pPrevNode == NULL))
+        {
+          /* insert the new node at the end of the list */
+          pNewNode->CLAR = hmdma->LastLinkedListNodeAddress->CLAR;
+          hmdma->LastLinkedListNodeAddress->CLAR = (uint32_t)pNewNode;
+          /* Update the Handle last node address */
+          hmdma->LastLinkedListNodeAddress = pNewNode;
+          /* Increment the linked list node counter */
+          hmdma->LinkedListNodeCounter++;
+        }
+        else
+        {
+          /*insert the new node after the pPreviousNode node */
+          pNode = hmdma->FirstLinkedListNodeAddress;
+          counter = 0;
+          while((counter < hmdma->LinkedListNodeCounter) && (nodeInserted == 0U))
+          {
+            counter++;
+            if(pNode == pPrevNode)
+            {
+              /*Insert the new node after the previous one */
+              pNewNode->CLAR = pNode->CLAR;
+              pNode->CLAR = (uint32_t)pNewNode;
+              /* Increment the linked list node counter */
+              hmdma->LinkedListNodeCounter++;
+              nodeInserted = 1;
+            }
+            else
+            {
+              pNode = (MDMA_LinkNodeTypeDef *)pNode->CLAR;
+            }
+          }
+
+          if(nodeInserted == 0U)
+          {
+            hal_status = HAL_ERROR;
+          }
+        }
+      }
+    }
+    else
+    {
+      hal_status = HAL_ERROR;
+    }
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hmdma);
+
+    hmdma->State = HAL_MDMA_STATE_READY;
+
+    return hal_status;
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hmdma);
+
+    /* Return error status */
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Disconnect/Remove a node from the transfer linked list.
+  * @param  hmdma : Pointer to a MDMA_HandleTypeDef structure that contains
+  *                 the configuration information for the specified MDMA Channel.
+  * @param  pNode : Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node
+  *                 to be removed from the list.
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNode)
+{
+  MDMA_LinkNodeTypeDef *ptmpNode;
+  uint32_t counter = 0, nodeDeleted = 0;
+  HAL_StatusTypeDef hal_status = HAL_OK;
+
+  /* Check the MDMA peripheral handle */
+  if((hmdma == NULL) || (pNode == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hmdma);
+
+  if(HAL_MDMA_STATE_READY == hmdma->State)
+  {
+    /* Change MDMA peripheral state */
+    hmdma->State = HAL_MDMA_STATE_BUSY;
+
+    /* If first and last node are null (no nodes in the list) : return error*/
+    if(((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U) || ((uint32_t)hmdma->LastLinkedListNodeAddress == 0U) || (hmdma->LinkedListNodeCounter == 0U))
+    {
+      hal_status = HAL_ERROR;
+    }
+    else if(hmdma->FirstLinkedListNodeAddress == pNode) /* Deleting first node */
+    {
+      /* Delete 1st node */
+      if(hmdma->LastLinkedListNodeAddress == pNode)
+      {
+        /*if the last node is at the same time the first one (1 single node after the init node 0)
+        then update the last node too */
+
+        hmdma->FirstLinkedListNodeAddress = 0;
+        hmdma->LastLinkedListNodeAddress  = 0;
+        hmdma->LinkedListNodeCounter = 0;
+
+        hmdma->Instance->CLAR = 0;
+      }
+      else
+      {
+        if((uint32_t)hmdma->FirstLinkedListNodeAddress == hmdma->LastLinkedListNodeAddress->CLAR)
+        {
+          /* if last node is looping to first (circular list) one update the last node connection */
+          hmdma->LastLinkedListNodeAddress->CLAR = pNode->CLAR;
+        }
+
+        /* if deleting the first node after the initialization
+        connect the next node to the node 0 by updating
+        the MDMA channel CLAR register to this node address */
+        hmdma->Instance->CLAR = pNode->CLAR;
+        hmdma->FirstLinkedListNodeAddress = (MDMA_LinkNodeTypeDef *)hmdma->Instance->CLAR;
+        /* Update the Handle node counter */
+        hmdma->LinkedListNodeCounter--;
+      }
+    }
+    else /* Deleting any other node */
+    {
+      /*Deleted node is not the first one : find it  */
+      ptmpNode = hmdma->FirstLinkedListNodeAddress;
+      while((counter < hmdma->LinkedListNodeCounter) && (nodeDeleted == 0U))
+      {
+        counter++;
+        if(ptmpNode->CLAR == ((uint32_t)pNode))
+        {
+          /* if deleting the last node */
+          if(pNode == hmdma->LastLinkedListNodeAddress)
+          {
+            /*Update the linked list last node address in the handle*/
+            hmdma->LastLinkedListNodeAddress = ptmpNode;
+          }
+          /* update the next node link after deleting pMDMA_LinkedListNode */
+          ptmpNode->CLAR = pNode->CLAR;
+          nodeDeleted = 1;
+          /* Update the Handle node counter */
+          hmdma->LinkedListNodeCounter--;
+        }
+        else
+        {
+          ptmpNode = (MDMA_LinkNodeTypeDef *)ptmpNode->CLAR;
+        }
+      }
+
+      if(nodeDeleted == 0U)
+      {
+        /* last node reashed without finding the node to delete : return error */
+        hal_status = HAL_ERROR;
+      }
+    }
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hmdma);
+
+    hmdma->State = HAL_MDMA_STATE_READY;
+
+    return hal_status;
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hmdma);
+
+    /* Return error status */
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Make the linked list circular by connecting the last node to the first.
+  * @param  hmdma : Pointer to a MDMA_HandleTypeDef structure that contains
+  *                 the configuration information for the specified MDMA Channel.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_LinkedList_EnableCircularMode(MDMA_HandleTypeDef *hmdma)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hmdma);
+
+  if(HAL_MDMA_STATE_READY == hmdma->State)
+  {
+    /* Change MDMA peripheral state */
+    hmdma->State = HAL_MDMA_STATE_BUSY;
+
+    /* If first and last node are null (no nodes in the list) : return error*/
+    if(((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U) || ((uint32_t)hmdma->LastLinkedListNodeAddress == 0U) || (hmdma->LinkedListNodeCounter == 0U))
+    {
+      hal_status = HAL_ERROR;
+    }
+    else
+    {
+      /* to enable circular mode Last Node should be connected to first node */
+      hmdma->LastLinkedListNodeAddress->CLAR = (uint32_t)hmdma->FirstLinkedListNodeAddress;
+    }
+
+  }
+  /* Process unlocked */
+  __HAL_UNLOCK(hmdma);
+
+  hmdma->State = HAL_MDMA_STATE_READY;
+
+  return hal_status;
+}
+
+/**
+  * @brief  Disable the linked list circular mode by setting the last node connection to null
+  * @param  hmdma : Pointer to a MDMA_HandleTypeDef structure that contains
+  *                 the configuration information for the specified MDMA Channel.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_LinkedList_DisableCircularMode(MDMA_HandleTypeDef *hmdma)
+{
+  HAL_StatusTypeDef hal_status = HAL_OK;
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hmdma);
+
+  if(HAL_MDMA_STATE_READY == hmdma->State)
+  {
+    /* Change MDMA peripheral state */
+    hmdma->State = HAL_MDMA_STATE_BUSY;
+
+    /* If first and last node are null (no nodes in the list) : return error*/
+    if(((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U) || ((uint32_t)hmdma->LastLinkedListNodeAddress == 0U) || (hmdma->LinkedListNodeCounter == 0U))
+    {
+      hal_status = HAL_ERROR;
+    }
+    else
+    {
+      /* to disable circular mode Last Node should be connected to NULL */
+      hmdma->LastLinkedListNodeAddress->CLAR = 0;
+    }
+
+  }
+  /* Process unlocked */
+  __HAL_UNLOCK(hmdma);
+
+  hmdma->State = HAL_MDMA_STATE_READY;
+
+  return hal_status;
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup MDMA_Exported_Functions_Group3
+ *
+@verbatim
+ ===============================================================================
+                      #####  IO operation functions  #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure the source, destination address and data length and Start MDMA transfer
+      (+) Configure the source, destination address and data length and
+          Start MDMA transfer with interrupt
+      (+) Abort MDMA transfer
+      (+) Poll for transfer complete
+      (+) Generate a SW request (when Request is set to MDMA_REQUEST_SW)
+      (+) Handle MDMA interrupt request
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the MDMA Transfer.
+  * @param  hmdma           : pointer to a MDMA_HandleTypeDef structure that contains
+  *                           the configuration information for the specified MDMA Channel.
+  * @param  SrcAddress      : The source memory Buffer address
+  * @param  DstAddress      : The destination memory Buffer address
+  * @param  BlockDataLength : The length of a block transfer in bytes
+  * @param  BlockCount      : The number of a blocks to be transfer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_Start(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
+{
+  /* Check the parameters */
+  assert_param(IS_MDMA_TRANSFER_LENGTH(BlockDataLength));
+  assert_param(IS_MDMA_BLOCK_COUNT(BlockCount));
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hmdma);
+
+  if(HAL_MDMA_STATE_READY == hmdma->State)
+  {
+    /* Change MDMA peripheral state */
+    hmdma->State = HAL_MDMA_STATE_BUSY;
+
+    /* Initialize the error code */
+    hmdma->ErrorCode = HAL_MDMA_ERROR_NONE;
+
+    /* Disable the peripheral */
+    __HAL_MDMA_DISABLE(hmdma);
+
+    /* Configure the source, destination address and the data length */
+    MDMA_SetConfig(hmdma, SrcAddress, DstAddress, BlockDataLength, BlockCount);
+
+    /* Enable the Peripheral */
+    __HAL_MDMA_ENABLE(hmdma);
+
+    if(hmdma->Init.Request == MDMA_REQUEST_SW)
+    {
+      /* activate If SW request mode*/
+      hmdma->Instance->CCR |=  MDMA_CCR_SWRQ;
+    }
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hmdma);
+
+    /* Return error status */
+    return HAL_BUSY;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the MDMA Transfer with interrupts enabled.
+  * @param  hmdma           : pointer to a MDMA_HandleTypeDef structure that contains
+  *                           the configuration information for the specified MDMA Channel.
+  * @param  SrcAddress      : The source memory Buffer address
+  * @param  DstAddress      : The destination memory Buffer address
+  * @param  BlockDataLength : The length of a block transfer in bytes
+  * @param  BlockCount      : The number of a blocks to be transfer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_Start_IT(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
+{
+  /* Check the parameters */
+  assert_param(IS_MDMA_TRANSFER_LENGTH(BlockDataLength));
+  assert_param(IS_MDMA_BLOCK_COUNT(BlockCount));
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hmdma);
+
+  if(HAL_MDMA_STATE_READY == hmdma->State)
+  {
+    /* Change MDMA peripheral state */
+    hmdma->State = HAL_MDMA_STATE_BUSY;
+
+    /* Initialize the error code */
+    hmdma->ErrorCode = HAL_MDMA_ERROR_NONE;
+
+    /* Disable the peripheral */
+    __HAL_MDMA_DISABLE(hmdma);
+
+    /* Configure the source, destination address and the data length */
+    MDMA_SetConfig(hmdma, SrcAddress, DstAddress, BlockDataLength, BlockCount);
+
+    /* Enable Common interrupts i.e Transfer Error IT and Channel Transfer Complete IT*/
+    __HAL_MDMA_ENABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC));
+
+    if(hmdma->XferBlockCpltCallback != NULL)
+    {
+      /* if Block transfer complete Callback is set enable the corresponding IT*/
+      __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BT);
+    }
+
+    if(hmdma->XferRepeatBlockCpltCallback != NULL)
+    {
+      /* if Repeated Block transfer complete Callback is set enable the corresponding IT*/
+      __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BRT);
+    }
+
+    if(hmdma->XferBufferCpltCallback != NULL)
+    {
+      /* if buffer transfer complete Callback is set enable the corresponding IT*/
+      __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BFTC);
+    }
+
+    /* Enable the Peripheral */
+    __HAL_MDMA_ENABLE(hmdma);
+
+    if(hmdma->Init.Request == MDMA_REQUEST_SW)
+    {
+      /* activate If SW request mode*/
+      hmdma->Instance->CCR |=  MDMA_CCR_SWRQ;
+    }
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hmdma);
+
+    /* Return error status */
+    return HAL_BUSY;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Aborts the MDMA Transfer.
+  * @param  hmdma  : pointer to a MDMA_HandleTypeDef structure that contains
+  *                 the configuration information for the specified MDMA Channel.
+  *
+  * @note  After disabling a MDMA Channel, a check for wait until the MDMA Channel is
+  *        effectively disabled is added. If a Channel is disabled
+  *        while a data transfer is ongoing, the current data will be transferred
+  *        and the Channel will be effectively disabled only after the transfer of
+  *        this single data is finished.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_Abort(MDMA_HandleTypeDef *hmdma)
+{
+  uint32_t tickstart =  HAL_GetTick();
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if(HAL_MDMA_STATE_BUSY != hmdma->State)
+  {
+    hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hmdma);
+
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Disable all the transfer interrupts */
+    __HAL_MDMA_DISABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC | MDMA_IT_BT | MDMA_IT_BRT | MDMA_IT_BFTC));
+
+    /* Disable the channel */
+    __HAL_MDMA_DISABLE(hmdma);
+
+    /* Check if the MDMA Channel is effectively disabled */
+    while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U)
+    {
+      /* Check for the Timeout */
+      if( (HAL_GetTick()  - tickstart ) > HAL_TIMEOUT_MDMA_ABORT)
+      {
+        /* Update error code */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_TIMEOUT;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hmdma);
+
+        /* Change the MDMA state */
+        hmdma->State = HAL_MDMA_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+    }
+
+    /* Clear all interrupt flags */
+    __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_FLAG_BT | MDMA_FLAG_BRT | MDMA_FLAG_BFTC));
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hmdma);
+
+    /* Change the MDMA state*/
+    hmdma->State = HAL_MDMA_STATE_READY;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Aborts the MDMA Transfer in Interrupt mode.
+  * @param  hmdma  : pointer to a MDMA_HandleTypeDef structure that contains
+  *                 the configuration information for the specified MDMA Channel.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_Abort_IT(MDMA_HandleTypeDef *hmdma)
+{
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if(HAL_MDMA_STATE_BUSY != hmdma->State)
+  {
+    /* No transfer ongoing */
+    hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER;
+
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Set Abort State  */
+    hmdma->State = HAL_MDMA_STATE_ABORT;
+
+    /* Disable the stream */
+    __HAL_MDMA_DISABLE(hmdma);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Polling for transfer complete.
+  * @param  hmdma:          pointer to a MDMA_HandleTypeDef structure that contains
+  *                        the configuration information for the specified MDMA Channel.
+  * @param  CompleteLevel: Specifies the MDMA level complete.
+  * @param  Timeout:       Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_PollForTransfer(MDMA_HandleTypeDef *hmdma, HAL_MDMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
+{
+  uint32_t levelFlag, errorFlag;
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param(IS_MDMA_LEVEL_COMPLETE(CompleteLevel));
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if(HAL_MDMA_STATE_BUSY != hmdma->State)
+  {
+    /* No transfer ongoing */
+    hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER;
+
+    return HAL_ERROR;
+  }
+
+  /* Get the level transfer complete flag */
+  levelFlag = ((CompleteLevel == HAL_MDMA_FULL_TRANSFER)  ? MDMA_FLAG_CTC  : \
+               (CompleteLevel == HAL_MDMA_BUFFER_TRANSFER)? MDMA_FLAG_BFTC : \
+               (CompleteLevel == HAL_MDMA_BLOCK_TRANSFER) ? MDMA_FLAG_BT   : \
+               MDMA_FLAG_BRT);
+
+
+  /* Get timeout */
+  tickstart = HAL_GetTick();
+
+  while(__HAL_MDMA_GET_FLAG(hmdma, levelFlag) == 0U)
+  {
+    if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_TE) != 0U))
+    {
+      /* Get the transfer error source flag */
+      errorFlag = hmdma->Instance->CESR;
+
+      if((errorFlag & MDMA_CESR_TED) == 0U)
+      {
+        /* Update error code : Read Transfer error  */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_READ_XFER;
+      }
+      else
+      {
+        /* Update error code : Write Transfer error */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_WRITE_XFER;
+      }
+
+      if((errorFlag & MDMA_CESR_TEMD) != 0U)
+      {
+        /* Update error code : Error Mask Data */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_MASK_DATA;
+      }
+
+      if((errorFlag & MDMA_CESR_TELD) != 0U)
+      {
+        /* Update error code : Error Linked list */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_LINKED_LIST;
+      }
+
+      if((errorFlag & MDMA_CESR_ASE) != 0U)
+      {
+        /* Update error code : Address/Size alignment error */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_ALIGNMENT;
+      }
+
+      if((errorFlag & MDMA_CESR_BSE) != 0U)
+      {
+        /* Update error code : Block Size error */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_BLOCK_SIZE;
+      }
+
+      (void) HAL_MDMA_Abort(hmdma); /* if error then abort the current transfer */
+
+      /*
+        Note that the Abort function will
+          - Clear all transfer flags
+          - Unlock
+          - Set the State
+      */
+
+      return HAL_ERROR;
+
+    }
+
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(((HAL_GetTick() - tickstart ) > Timeout) || (Timeout == 0U))
+      {
+        /* Update error code */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_TIMEOUT;
+
+        (void) HAL_MDMA_Abort(hmdma); /* if timeout then abort the current transfer */
+
+        /*
+          Note that the Abort function will
+            - Clear all transfer flags
+            - Unlock
+            - Set the State
+        */
+
+        return HAL_ERROR;
+      }
+    }
+  }
+
+  /* Clear the transfer level flag */
+  if(CompleteLevel == HAL_MDMA_BUFFER_TRANSFER)
+  {
+    __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BFTC);
+
+  }
+  else if(CompleteLevel == HAL_MDMA_BLOCK_TRANSFER)
+  {
+    __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BFTC | MDMA_FLAG_BT));
+
+  }
+  else if(CompleteLevel == HAL_MDMA_REPEAT_BLOCK_TRANSFER)
+  {
+    __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BFTC | MDMA_FLAG_BT | MDMA_FLAG_BRT));
+  }
+  else if(CompleteLevel == HAL_MDMA_FULL_TRANSFER)
+  {
+    __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BRT | MDMA_FLAG_BT | MDMA_FLAG_BFTC | MDMA_FLAG_CTC));
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hmdma);
+
+    hmdma->State = HAL_MDMA_STATE_READY;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Generate an MDMA SW request trigger to activate the request on the given Channel.
+  * @param  hmdma:       pointer to a MDMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified MDMA Stream.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_GenerateSWRequest(MDMA_HandleTypeDef *hmdma)
+{
+  uint32_t request_mode;
+
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Get the softawre request mode */
+  request_mode = hmdma->Instance->CTCR & MDMA_CTCR_SWRM;
+
+  if((hmdma->Instance->CCR &  MDMA_CCR_EN) == 0U)
+  {
+    /* if no Transfer on going (MDMA enable bit not set) retrun error */
+    hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER;
+
+    return HAL_ERROR;
+  }
+  else if(((hmdma->Instance->CISR &  MDMA_CISR_CRQA) != 0U) || (request_mode == 0U))
+  {
+    /* if an MDMA ongoing request has not yet end or if request mode is not SW request retrun error */
+    hmdma->ErrorCode = HAL_MDMA_ERROR_BUSY;
+
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Set the SW request bit to activate the request on the Channel */
+    hmdma->Instance->CCR |= MDMA_CCR_SWRQ;
+
+    return HAL_OK;
+  }
+}
+
+/**
+  * @brief  Handles MDMA interrupt request.
+  * @param  hmdma: pointer to a MDMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified MDMA Channel.
+  * @retval None
+  */
+void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma)
+{
+  __IO uint32_t count = 0;
+  uint32_t timeout = SystemCoreClock / 9600U;
+
+  uint32_t generalIntFlag, errorFlag;
+
+  /* General Interrupt Flag management ****************************************/
+  generalIntFlag =  1UL << ((((uint32_t)hmdma->Instance - (uint32_t)(MDMA_Channel0))/HAL_MDMA_CHANNEL_SIZE) & 0x1FU);
+  if((MDMA->GISR0 & generalIntFlag) == 0U)
+  {
+    return; /* the  General interrupt flag for the current channel is down , nothing to do */
+  }
+
+  /* Transfer Error Interrupt management ***************************************/
+  if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_TE) != 0U))
+  {
+    if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_TE) != 0U)
+    {
+      /* Disable the transfer error interrupt */
+      __HAL_MDMA_DISABLE_IT(hmdma, MDMA_IT_TE);
+
+      /* Get the transfer error source flag */
+      errorFlag = hmdma->Instance->CESR;
+
+      if((errorFlag & MDMA_CESR_TED) == 0U)
+      {
+        /* Update error code : Read Transfer error  */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_READ_XFER;
+      }
+      else
+      {
+        /* Update error code : Write Transfer error */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_WRITE_XFER;
+      }
+
+      if((errorFlag & MDMA_CESR_TEMD) != 0U)
+      {
+        /* Update error code : Error Mask Data */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_MASK_DATA;
+      }
+
+      if((errorFlag & MDMA_CESR_TELD) != 0U)
+      {
+        /* Update error code : Error Linked list */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_LINKED_LIST;
+      }
+
+      if((errorFlag & MDMA_CESR_ASE) != 0U)
+      {
+        /* Update error code : Address/Size alignment error */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_ALIGNMENT;
+      }
+
+      if((errorFlag & MDMA_CESR_BSE) != 0U)
+      {
+        /* Update error code : Block Size error error */
+        hmdma->ErrorCode |= HAL_MDMA_ERROR_BLOCK_SIZE;
+      }
+
+      /* Clear the transfer error flags */
+      __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_TE);
+    }
+  }
+
+  /* Buffer Transfer Complete Interrupt management ******************************/
+  if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BFTC) != 0U))
+  {
+    if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BFTC) != 0U)
+    {
+      /* Clear the buffer transfer complete flag */
+      __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BFTC);
+
+      if(hmdma->XferBufferCpltCallback != NULL)
+      {
+        /* Buffer transfer callback */
+        hmdma->XferBufferCpltCallback(hmdma);
+      }
+    }
+  }
+
+  /* Block Transfer Complete Interrupt management ******************************/
+  if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BT) != 0U))
+  {
+    if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BT) != 0U)
+    {
+      /* Clear the block transfer complete flag */
+      __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BT);
+
+      if(hmdma->XferBlockCpltCallback != NULL)
+      {
+        /* Block transfer callback */
+        hmdma->XferBlockCpltCallback(hmdma);
+      }
+    }
+  }
+
+  /* Repeated Block Transfer Complete Interrupt management ******************************/
+  if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BRT) != 0U))
+  {
+    if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BRT) != 0U)
+    {
+      /* Clear the repeat block transfer complete flag */
+      __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BRT);
+
+      if(hmdma->XferRepeatBlockCpltCallback != NULL)
+      {
+        /* Repeated Block transfer callback */
+        hmdma->XferRepeatBlockCpltCallback(hmdma);
+      }
+    }
+  }
+
+  /* Channel Transfer Complete Interrupt management ***********************************/
+  if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_CTC) != 0U))
+  {
+    if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_CTC) != 0U)
+    {
+      /* Disable all the transfer interrupts */
+      __HAL_MDMA_DISABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC | MDMA_IT_BT | MDMA_IT_BRT | MDMA_IT_BFTC));
+
+      if(HAL_MDMA_STATE_ABORT == hmdma->State)
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hmdma);
+
+        /* Change the DMA state */
+        hmdma->State = HAL_MDMA_STATE_READY;
+
+        if(hmdma->XferAbortCallback != NULL)
+        {
+          hmdma->XferAbortCallback(hmdma);
+        }
+        return;
+      }
+
+      /* Clear the Channel Transfer Complete flag */
+      __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_CTC);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hmdma);
+
+      /* Change MDMA peripheral state */
+      hmdma->State = HAL_MDMA_STATE_READY;
+
+      if(hmdma->XferCpltCallback != NULL)
+      {
+        /* Channel Transfer Complete callback */
+        hmdma->XferCpltCallback(hmdma);
+      }
+    }
+  }
+
+  /* manage error case */
+  if(hmdma->ErrorCode != HAL_MDMA_ERROR_NONE)
+  {
+    hmdma->State = HAL_MDMA_STATE_ABORT;
+
+    /* Disable the channel */
+    __HAL_MDMA_DISABLE(hmdma);
+
+    do
+    {
+      if (++count > timeout)
+      {
+        break;
+      }
+    }
+    while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hmdma);
+
+    if((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U)
+    {
+      /* Change the MDMA state to error if MDMA disable fails */
+      hmdma->State = HAL_MDMA_STATE_ERROR;
+    }
+    else
+    {
+      /* Change the MDMA state to Ready if MDMA disable success */
+      hmdma->State = HAL_MDMA_STATE_READY;
+    }
+
+
+    if (hmdma->XferErrorCallback != NULL)
+    {
+      /* Transfer error callback */
+      hmdma->XferErrorCallback(hmdma);
+    }
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup MDMA_Exported_Functions_Group4
+ *
+@verbatim
+ ===============================================================================
+                    ##### State and Errors functions #####
+ ===============================================================================
+    [..]
+    This subsection provides functions allowing to
+      (+) Check the MDMA state
+      (+) Get error code
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the MDMA state.
+  * @param  hmdma: pointer to a MDMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified MDMA Channel.
+  * @retval HAL state
+  */
+HAL_MDMA_StateTypeDef HAL_MDMA_GetState(MDMA_HandleTypeDef *hmdma)
+{
+  return hmdma->State;
+}
+
+/**
+  * @brief  Return the MDMA error code
+  * @param  hmdma : pointer to a MDMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified MDMA Channel.
+  * @retval MDMA Error Code
+  */
+uint32_t HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma)
+{
+  return hmdma->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup MDMA_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Sets the MDMA Transfer parameter.
+  * @param  hmdma:       pointer to a MDMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified MDMA Channel.
+  * @param  SrcAddress: The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  BlockDataLength : The length of a block transfer in bytes
+  * @param  BlockCount: The number of blocks to be transfered
+  * @retval HAL status
+  */
+static void MDMA_SetConfig(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
+{
+  uint32_t addressMask;
+
+  /* Configure the MDMA Channel data length */
+  MODIFY_REG(hmdma->Instance->CBNDTR ,MDMA_CBNDTR_BNDT, (BlockDataLength & MDMA_CBNDTR_BNDT));
+
+  /* Configure the MDMA block repeat count */
+  MODIFY_REG(hmdma->Instance->CBNDTR , MDMA_CBNDTR_BRC , ((BlockCount - 1U) << MDMA_CBNDTR_BRC_Pos) & MDMA_CBNDTR_BRC);
+
+  /* Clear all interrupt flags */
+  __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_CISR_BRTIF | MDMA_CISR_BTIF | MDMA_CISR_TCIF);
+
+  /* Configure MDMA Channel destination address */
+  hmdma->Instance->CDAR = DstAddress;
+
+  /* Configure MDMA Channel Source address */
+  hmdma->Instance->CSAR = SrcAddress;
+
+  addressMask = SrcAddress & 0xFF000000U;
+  if((addressMask == 0x20000000U) || (addressMask == 0x00000000U))
+  {
+    /*The AHBSbus is used as source (read operation) on channel x */
+    hmdma->Instance->CTBR |= MDMA_CTBR_SBUS;
+  }
+  else
+  {
+    /*The AXI bus is used as source (read operation) on channel x */
+    hmdma->Instance->CTBR &= (~MDMA_CTBR_SBUS);
+  }
+
+  addressMask = DstAddress & 0xFF000000U;
+  if((addressMask == 0x20000000U) || (addressMask == 0x00000000U))
+  {
+    /*The AHB bus is used as destination (write operation) on channel x */
+    hmdma->Instance->CTBR |= MDMA_CTBR_DBUS;
+  }
+  else
+  {
+    /*The AXI bus is used as destination (write operation) on channel x */
+    hmdma->Instance->CTBR &= (~MDMA_CTBR_DBUS);
+  }
+
+  /* Set the linked list register to the first node of the list */
+  hmdma->Instance->CLAR = (uint32_t)hmdma->FirstLinkedListNodeAddress;
+}
+
+/**
+  * @brief  Initializes the MDMA handle according to the specified
+  *         parameters in the MDMA_InitTypeDef
+  * @param  hmdma:       pointer to a MDMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified MDMA Channel.
+  * @retval None
+  */
+static void MDMA_Init(MDMA_HandleTypeDef *hmdma)
+{
+  uint32_t blockoffset;
+
+  /* Prepare the MDMA Channel configuration */
+  hmdma->Instance->CCR = hmdma->Init.Priority  | hmdma->Init.Endianness;
+
+  /* Write new CTCR Register value */
+  hmdma->Instance->CTCR =  hmdma->Init.SourceInc      | hmdma->Init.DestinationInc | \
+                           hmdma->Init.SourceDataSize | hmdma->Init.DestDataSize   | \
+                           hmdma->Init.DataAlignment  | hmdma->Init.SourceBurst    | \
+                           hmdma->Init.DestBurst                                   | \
+                           ((hmdma->Init.BufferTransferLength - 1U) << MDMA_CTCR_TLEN_Pos) | \
+                           hmdma->Init.TransferTriggerMode;
+
+  /* If SW request set the CTCR register to SW Request Mode */
+  if(hmdma->Init.Request == MDMA_REQUEST_SW)
+  {
+    /*
+    -If the request is done by SW : BWM could be set to 1 or 0.
+    -If the request is done by a peripheral :
+    If mask address not set (0) => BWM must be set to 0
+    If mask address set (different than 0) => BWM could be set to 1 or 0
+    */
+    hmdma->Instance->CTCR |= (MDMA_CTCR_SWRM | MDMA_CTCR_BWM);
+  }
+
+  /* Reset CBNDTR Register */
+  hmdma->Instance->CBNDTR = 0;
+
+  /* if block source address offset is negative set the Block Repeat Source address Update Mode to decrement */
+  if(hmdma->Init.SourceBlockAddressOffset < 0)
+  {
+    hmdma->Instance->CBNDTR |= MDMA_CBNDTR_BRSUM;
+    /* Write new CBRUR Register value : source repeat block offset */
+    blockoffset = (uint32_t)(- hmdma->Init.SourceBlockAddressOffset);
+    hmdma->Instance->CBRUR = (blockoffset & 0x0000FFFFU);
+  }
+  else
+  {
+    /* Write new CBRUR Register value : source repeat block offset */
+    hmdma->Instance->CBRUR = (((uint32_t)hmdma->Init.SourceBlockAddressOffset) & 0x0000FFFFU);
+  }
+
+  /* If block destination address offset is negative set the Block Repeat destination address Update Mode to decrement */
+  if(hmdma->Init.DestBlockAddressOffset < 0)
+  {
+    hmdma->Instance->CBNDTR |= MDMA_CBNDTR_BRDUM;
+    /* Write new CBRUR Register value : destination repeat block offset */
+    blockoffset = (uint32_t)(- hmdma->Init.DestBlockAddressOffset);
+    hmdma->Instance->CBRUR |= ((blockoffset & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos);
+  }
+  else
+  {
+    /*write new CBRUR Register value : destination repeat block offset */
+    hmdma->Instance->CBRUR |= ((((uint32_t)hmdma->Init.DestBlockAddressOffset) & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos);
+  }
+
+  /* if HW request set the HW request and the requet CleraMask and ClearData MaskData, */
+  if(hmdma->Init.Request != MDMA_REQUEST_SW)
+  {
+    /* Set the HW request in CTRB register  */
+    hmdma->Instance->CTBR = hmdma->Init.Request & MDMA_CTBR_TSEL;
+  }
+  else /* SW request : reset the CTBR register */
+  {
+    hmdma->Instance->CTBR = 0;
+  }
+
+  /* Write Link Address Register */
+  hmdma->Instance->CLAR =  0;
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_MDMA_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c
new file mode 100644
index 00000000..43d9052a
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c
@@ -0,0 +1,868 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_pwr.c
+  * @author  MCD Application Team
+  * @brief   PWR HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Power Controller (PWR) peripheral:
+  *           + Initialization and de-initialization functions.
+  *           + Peripheral Control functions.
+  *           + Interrupt Handling functions.
+  @verbatim
+  ==============================================================================
+                        ##### PWR peripheral overview #####
+  ==============================================================================
+  [..]
+   (#) The Power control (PWR) provides an overview of the supply architecture
+       for the different power domains and of the supply configuration
+       controller.
+       In the H7 family, the number of power domains is different between
+       device lines. This difference is due to characteristics of each device.
+
+   (#) Domain architecture overview for the different H7 lines:
+      (+) Dual core lines are STM32H745, STM32H747, STM32H755 and STM32H757.
+          These devices have 3 power domains (D1, D2 and D3).
+          The domain D1 contains a CPU (Cortex-M7), a Flash memory and some
+          peripherals. The D2 domain contains peripherals and a CPU
+          (Cortex-M4). The D3 domain contains the system control, I/O logic
+          and low-power peripherals.
+      (+) STM32H743, STM32H753, STM32H742 and STM32H750 devices have 3 power
+          domains (D1, D2 and D3).
+          The domain D1 contains a CPU (Cortex-M7), a Flash memory and some
+          peripherals. The D2 domain contains peripherals. The D3 domains
+          contains the system control, I/O logic and low-power peripherals.
+      (+) STM32H7AxxQ, STM32H7BxxQ, STM32H7Axxx and STM32H7Bxxx devices have 2
+          power domains (CD and SRD).
+          The core domain (CD) contains a CPU (Cortex-M7), a Flash
+          memory and peripherals. The SmartRun domain contains the system
+          control, I/O logic and low-power peripherals.
+
+   (#) Every entity have low power mode as decribed below :
+   (#) The CPU low power modes are :
+      (+) CPU CRUN.
+      (+) CPU CSLEEP.
+      (+) CPU CSTOP.
+   (#) The domain low power modes are :
+      (+) DRUN.
+      (+) DSTOP.
+      (+) DSTANDBY.
+   (#) The SYSTEM low power modes are :
+      (+) RUN* : The Run* mode is entered after a POR reset and a wakeup from
+                 Standby. In Run* mode, the performance is limited and the
+                 system supply configuration shall be programmed. The system
+                 enters Run mode only when the ACTVOSRDY bit in PWR control
+                 status register 1 (PWR_CSR1) is set to 1.
+      (+) RUN.
+      (+) STOP.
+      (+) STANDBY.
+
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+   (#) Power management peripheral is active by default at startup level in
+       STM32h7xx lines.
+
+   (#) Call HAL_PWR_EnableBkUpAccess() and HAL_PWR_DisableBkUpAccess() functions
+       to enable/disable access to the backup domain (RTC registers, RTC backup
+       data registers and backup SRAM).
+
+   (#) Call HAL_PWR_ConfigPVD() after setting parameters to be configured (event
+       mode and voltage threshold) in order to set up the Power Voltage Detector,
+       then use HAL_PWR_EnablePVD() and  HAL_PWR_DisablePVD() functions to start
+       and stop the PVD detection.
+       (+) PVD level could be one of the following values :
+             (++) 1V95
+             (++) 2V1
+             (++) 2V25
+             (++) 2V4
+             (++) 2V55
+             (++) 2V7
+             (++) 2V85
+             (++) External voltage level
+
+   (#) Call HAL_PWR_EnableWakeUpPin() and HAL_PWR_DisableWakeUpPin() functions
+       with the right parameter to configure the wake up pin polarity (Low or
+       High) and to enable and disable it.
+
+   (#) Call HAL_PWR_EnterSLEEPMode() function to enter the current Core in SLEEP
+       mode. Wake-up from SLEEP mode could be following to an event or an
+       interrupt according to low power mode intrinsic request called (__WFI()
+       or __WFE()).
+       Please ensure to clear all CPU pending events by calling
+       HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx
+       in SLEEP mode with __WFE() entry.
+
+   (#) Call HAL_PWR_EnterSTOPMode() function to enter the whole system to Stop 0
+       mode for single core devices. For dual core devices, this API will enter
+       the domain (containing Cortex-Mx that executing this function) in DSTOP
+       mode. According to the used parameter, user could select the regulator to
+       be kept actif in low power mode and wake-up event type.
+       Please ensure to clear all CPU pending events by calling
+       HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx
+       in CSTOP mode with __WFE() entry.
+
+   (#) Call HAL_PWR_EnterSTANDBYMode() function to enter the whole system in
+       STANDBY mode for single core devices. For dual core devices, this API
+       will enter the domain (containing Cortex-Mx that executing this function)
+       in DSTANDBY mode.
+
+   (#) Call HAL_PWR_EnableSleepOnExit() and HAL_PWR_DisableSleepOnExit() APIs to
+       enable and disable the Cortex-Mx re-entring in SLEEP mode after an
+       interruption handling is over.
+
+   (#) Call HAL_PWR_EnableSEVOnPend() and HAL_PWR_DisableSEVOnPend() functions
+       to configure the Cortex-Mx to wake-up after any pending event / interrupt
+       even if it's disabled or has insufficient priority to cause exception
+       entry.
+
+   (#) Call HAL_PWR_PVD_IRQHandler() function to handle the PWR PVD interrupt
+       request.
+
+     *** PWR HAL driver macros list ***
+     =============================================
+     [..]
+       Below the list of most used macros in PWR HAL driver.
+
+      (+) __HAL_PWR_VOLTAGESCALING_CONFIG() : Configure the main internal
+                                              regulator output voltage.
+      (+) __HAL_PWR_GET_FLAG()              : Get the PWR pending flags.
+      (+) __HAL_PWR_CLEAR_FLAG()            : Clear the PWR pending flags.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup PWR PWR
+  * @brief PWR HAL module driver
+  * @{
+  */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @addtogroup PWR_Private_Constants PWR Private Constants
+  * @{
+  */
+
+/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
+  * @{
+  */
+#if !defined (DUAL_CORE)
+#define PVD_MODE_IT              (0x00010000U)
+#define PVD_MODE_EVT             (0x00020000U)
+#endif /* !defined (DUAL_CORE) */
+
+#define PVD_RISING_EDGE          (0x00000001U)
+#define PVD_FALLING_EDGE         (0x00000002U)
+#define PVD_RISING_FALLING_EDGE  (0x00000003U)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Functions PWR Exported Functions
+  * @{
+  */
+
+/** @defgroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions
+  * @brief    Initialization and De-Initialization functions
+  *
+@verbatim
+ ===============================================================================
+              ##### Initialization and De-Initialization Functions #####
+ ===============================================================================
+    [..]
+      This section provides functions allowing to deinitialize power peripheral.
+
+    [..]
+      After system reset, the backup domain (RTC registers, RTC backup data
+      registers and backup SRAM) is protected against possible unwanted write
+      accesses.
+      The HAL_PWR_EnableBkUpAccess() function enables the access to the backup
+      domain.
+      The HAL_PWR_DisableBkUpAccess() function disables the access to the backup
+      domain.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitialize the HAL PWR peripheral registers to their default reset
+  *         values.
+  * @note   This functionality is not available in this product.
+  *         The prototype is kept just to maintain compatibility with other
+  *         products.
+  * @retval None.
+  */
+void HAL_PWR_DeInit (void)
+{
+}
+
+/**
+  * @brief  Enable access to the backup domain (RTC registers, RTC backup data
+  *         registers and backup SRAM).
+  * @note   If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
+  *         Backup Domain Access should be kept enabled.
+  * @retval None.
+  */
+void HAL_PWR_EnableBkUpAccess (void)
+{
+  /* Enable access to RTC and backup registers */
+  SET_BIT (PWR->CR1, PWR_CR1_DBP);
+}
+
+/**
+  * @brief  Disable access to the backup domain (RTC registers, RTC backup data
+  *         registers and backup SRAM).
+  * @note   If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
+  *         Backup Domain Access should be kept enabled.
+  * @retval None.
+  */
+void HAL_PWR_DisableBkUpAccess (void)
+{
+  /* Disable access to RTC and backup registers */
+  CLEAR_BIT (PWR->CR1, PWR_CR1_DBP);
+}
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control Functions
+  *  @brief   Power Control functions
+  *
+@verbatim
+ ===============================================================================
+                 ##### Peripheral Control Functions #####
+ ===============================================================================
+    [..]
+      This section provides functions allowing to control power peripheral.
+
+    *** PVD configuration ***
+    =========================
+    [..]
+      (+) The PVD is used to monitor the VDD power supply by comparing it to a
+          threshold selected by the PVD Level (PLS[7:0] bits in the PWR_CR1
+          register).
+
+      (+) A PVDO flag is available to indicate if VDD is higher or lower
+          than the PVD threshold. This event is internally connected to the EXTI
+          line 16 to generate an interrupt if enabled.
+          It is configurable through __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
+
+      (+) The PVD is stopped in STANDBY mode.
+
+    *** Wake-up pin configuration ***
+    =================================
+    [..]
+      (+) Wake-up pin is used to wake up the system from STANDBY mode.
+          The pin pull is configurable through the WKUPEPR register to be in
+          No-pull, Pull-up and Pull-down.
+          The pin polarity is configurable through the WKUPEPR register to be
+          active on rising or falling edges.
+
+      (+) There are up to six Wake-up pin in the STM32H7 devices family.
+
+    *** Low Power modes configuration ***
+    =====================================
+    [..]
+     The device present 3 principles low-power modes features:
+      (+) SLEEP mode   : Cortex-Mx is stopped and all PWR domains are remaining
+                         active (Powered and Clocked).
+
+      (+) STOP mode    : Cortex-Mx is stopped, clocks are stopped and the
+                         regulator is running. The Main regulator or the LP
+                         regulator could be selected.
+
+      (+) STANDBY mode : All PWR domains enter DSTANDBY mode and the VCORE
+                         supply regulator is powered off.
+
+   *** SLEEP mode ***
+   ==================
+    [..]
+      (+) Entry:
+        The SLEEP mode is entered by using the HAL_PWR_EnterSLEEPMode(Regulator,
+        SLEEPEntry) function.
+
+          (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction.
+          (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction.
+
+      -@@- The Regulator parameter is not used for the STM32H7 family
+              and is kept as parameter just to maintain compatibility with the
+              lower power families (STM32L).
+
+      (+) Exit:
+        Any peripheral interrupt acknowledged by the nested vectored interrupt
+        controller (NVIC) can wake up the device from SLEEP mode.
+
+   *** STOP mode ***
+   =================
+    [..]
+      In system STOP mode, all clocks in the 1.2V domain are stopped, the PLL,
+      the HSI, and the HSE RC oscillators are disabled. Internal SRAM and
+      register contents are preserved.
+      The voltage regulator can be configured either in normal or low-power mode.
+      To minimize the consumption in STOP mode, FLASH can be powered off before
+      entering the STOP mode using the HAL_PWREx_EnableFlashPowerDown() function.
+      It can be switched on again by software after exiting the STOP mode using
+      the HAL_PWREx_DisableFlashPowerDown() function.
+
+      (+) Entry:
+         The STOP mode is entered using the HAL_PWR_EnterSTOPMode(Regulator,
+         STOPEntry) function with:
+
+         (++) Regulator:
+          (+++) PWR_MAINREGULATOR_ON: Main regulator ON.
+          (+++) PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON.
+
+         (++) STOPEntry:
+          (+++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction.
+          (+++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction.
+
+      (+) Exit:
+         Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
+
+   *** STANDBY mode ***
+   ====================
+    [..]
+    (+)
+      The system STANDBY mode allows to achieve the lowest power consumption.
+      It is based on the Cortex-Mx deep SLEEP mode, with the voltage regulator
+      disabled. The system is consequently powered off. The PLL, the HSI
+      oscillator and the HSE oscillator are also switched off. SRAM and register
+      contents are lost except for the RTC registers, RTC backup registers,
+      backup SRAM and standby circuitry.
+
+    [..]
+      The voltage regulator is OFF.
+
+      (++) Entry:
+        (+++) The STANDBY mode is entered using the HAL_PWR_EnterSTANDBYMode()
+              function.
+
+      (++) Exit:
+        (+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B),
+              RTC wakeup, tamper event, time stamp event, external reset in NRST
+              pin, IWDG reset.
+
+   *** Auto-wakeup (AWU) from low-power mode ***
+   =============================================
+    [..]
+     (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an
+         RTC Wakeup event, a tamper event or a time-stamp event, without
+         depending on an external interrupt (Auto-wakeup mode).
+
+     (+) RTC auto-wakeup (AWU) from the STOP and STANDBY modes
+
+       (++) To wake up from the STOP mode with an RTC alarm event, it is
+            necessary to configure the RTC to generate the RTC alarm using the
+            HAL_RTC_SetAlarm_IT() function.
+
+       (++) To wake up from the STOP mode with an RTC Tamper or time stamp event,
+            it is necessary to configure the RTC to detect the tamper or time
+            stamp event using the HAL_RTCEx_SetTimeStamp_IT() or
+            HAL_RTCEx_SetTamper_IT() functions.
+
+       (++) To wake up from the STOP mode with an RTC WakeUp event, it is
+            necessary to configure the RTC to generate the RTC WakeUp event
+            using the HAL_RTCEx_SetWakeUpTimer_IT() function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the event mode and the voltage threshold detected by the
+  *         Programmable Voltage Detector(PVD).
+  * @param  sConfigPVD : Pointer to an PWR_PVDTypeDef structure that contains
+  *                      the configuration information for the PVD.
+  * @note   Refer to the electrical characteristics of your device datasheet for
+  *         more details about the voltage threshold corresponding to each
+  *         detection level.
+  * @note   For dual core devices, please ensure to configure the EXTI lines for
+  *         the different Cortex-Mx through PWR_Exported_Macro provided by this
+  *         driver. All combination are allowed: wake up only Cortex-M7, wake up
+  *         only Cortex-M4 or wake up Cortex-M7 and Cortex-M4.
+  * @retval None.
+  */
+void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD)
+{
+  /* Check the PVD configuration parameter */
+  if (sConfigPVD == NULL)
+  {
+    return;
+  }
+
+  /* Check the parameters */
+  assert_param (IS_PWR_PVD_LEVEL (sConfigPVD->PVDLevel));
+  assert_param (IS_PWR_PVD_MODE (sConfigPVD->Mode));
+
+  /* Set PLS[7:5] bits according to PVDLevel value */
+  MODIFY_REG (PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel);
+
+  /* Clear previous config */
+#if !defined (DUAL_CORE)
+  __HAL_PWR_PVD_EXTI_DISABLE_EVENT ();
+  __HAL_PWR_PVD_EXTI_DISABLE_IT ();
+#endif /* !defined (DUAL_CORE) */
+
+  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE ();
+  __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE ();
+
+#if !defined (DUAL_CORE)
+  /* Interrupt mode configuration */
+  if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
+  {
+    __HAL_PWR_PVD_EXTI_ENABLE_IT ();
+  }
+
+  /* Event mode configuration */
+  if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
+  {
+    __HAL_PWR_PVD_EXTI_ENABLE_EVENT ();
+  }
+#endif /* !defined (DUAL_CORE) */
+
+  /* Rising edge configuration */
+  if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
+  {
+    __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE ();
+  }
+
+  /* Falling edge configuration */
+  if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
+  {
+    __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE ();
+  }
+}
+
+/**
+  * @brief Enable the Programmable Voltage Detector (PVD).
+  * @retval None.
+  */
+void HAL_PWR_EnablePVD (void)
+{
+  /* Enable the power voltage detector */
+  SET_BIT (PWR->CR1, PWR_CR1_PVDEN);
+}
+
+/**
+  * @brief Disable the Programmable Voltage Detector (PVD).
+  * @retval None.
+  */
+void HAL_PWR_DisablePVD (void)
+{
+  /* Disable the power voltage detector */
+  CLEAR_BIT (PWR->CR1, PWR_CR1_PVDEN);
+}
+
+/**
+  * @brief  Enable the WakeUp PINx functionality.
+  * @param  WakeUpPinPolarity : Specifies which Wake-Up pin to enable.
+  *          This parameter can be one of the following legacy values, which
+  *          sets the default (rising edge):
+  *            @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3,
+  *                 PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6.
+  *          or one of the following values where the user can explicitly states
+  *          the enabled pin and the chosen polarity:
+  *            @arg PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW,
+  *                 PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW,
+  *                 PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW,
+  *                 PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW,
+  *                 PWR_WAKEUP_PIN5_HIGH, PWR_WAKEUP_PIN5_LOW,
+  *                 PWR_WAKEUP_PIN6_HIGH, PWR_WAKEUP_PIN6_LOW.
+  * @note   PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
+  * @retval None.
+  */
+void HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity)
+{
+  /* Check the parameters */
+  assert_param (IS_PWR_WAKEUP_PIN (WakeUpPinPolarity));
+
+  /*
+     Enable and Specify the Wake-Up pin polarity and the pull configuration
+     for the event detection (rising or falling edge).
+  */
+  MODIFY_REG (PWR->WKUPEPR, PWR_EWUP_MASK, WakeUpPinPolarity);
+}
+
+/**
+  * @brief  Disable the WakeUp PINx functionality.
+  * @param  WakeUpPinx : Specifies the Power Wake-Up pin to disable.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3,
+  *                 PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6,
+  *                 PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW,
+  *                 PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW,
+  *                 PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW,
+  *                 PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW,
+  *                 PWR_WAKEUP_PIN5_HIGH, PWR_WAKEUP_PIN5_LOW,
+  *                 PWR_WAKEUP_PIN6_HIGH, PWR_WAKEUP_PIN6_LOW.
+  * @retval None.
+  */
+void HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx)
+{
+  /* Check the parameters */
+  assert_param (IS_PWR_WAKEUP_PIN (WakeUpPinx));
+
+  /* Disable the wake up pin selected */
+  CLEAR_BIT (PWR->WKUPEPR, (PWR_WKUPEPR_WKUPEN & WakeUpPinx));
+}
+
+/**
+  * @brief  Enter the current core in SLEEP mode (CSLEEP).
+  * @param  Regulator : Specifies the regulator state in SLEEP mode.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_MAINREGULATOR_ON     : SLEEP mode with regulator ON.
+  *            @arg PWR_LOWPOWERREGULATOR_ON : SLEEP mode with low power
+  *                                           regulator ON.
+  * @note   This parameter is not used for the STM32H7 family and is kept as
+  *         parameter just to maintain compatibility with the lower power
+  *         families.
+  * @param  SLEEPEntry : Specifies if SLEEP mode is entered with WFI or WFE
+  *                      intrinsic instruction.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_SLEEPENTRY_WFI : enter SLEEP mode with WFI instruction.
+  *            @arg PWR_SLEEPENTRY_WFE : enter SLEEP mode with WFE instruction.
+  * @note   Ensure to clear pending events before calling this API through
+  *         HAL_PWREx_ClearPendingEvent() when the SLEEP entry is WFE.
+  * @retval None.
+  */
+void HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry)
+{
+  /* Check the parameters */
+  assert_param (IS_PWR_REGULATOR (Regulator));
+  assert_param (IS_PWR_SLEEP_ENTRY (SLEEPEntry));
+
+  /* Clear SLEEPDEEP bit of Cortex System Control Register */
+  CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+
+  /* Select SLEEP mode entry */
+  if (SLEEPEntry == PWR_SLEEPENTRY_WFI)
+  {
+    /* Request Wait For Interrupt */
+    __WFI ();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __WFE ();
+  }
+}
+
+/**
+  * @brief  Enter STOP mode.
+  * @note   For single core devices, this API will enter the system in STOP mode
+  *         with all domains in DSTOP, if RUN_D3/RUN_SRD bit in CPUCR regiter is
+  *         cleared.
+  *         For dual core devices, this API will enter the domain (containing
+  *         Cortex-Mx that executing this function) in DSTOP mode. If all
+  *         Cortex-Mx domains are in DSTOP and RUN_D3 bit in CPUCR register is
+  *         cleared, all the system will enter in STOP mode.
+  * @param  Regulator : Specifies the regulator state in STOP mode.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_MAINREGULATOR_ON     : STOP mode with regulator ON.
+  *            @arg PWR_LOWPOWERREGULATOR_ON : STOP mode with low power
+  *                                            regulator ON.
+  * @param  STOPEntry : Specifies if STOP mode in entered with WFI or WFE
+  *                     intrinsic instruction.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction.
+  *            @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction.
+  * @note   In System STOP mode, all I/O pins keep the same state as in Run mode.
+  * @note   When exiting System STOP mode by issuing an interrupt or a wakeup
+  *         event, the HSI RC oscillator is selected as default system wakeup
+  *         clock.
+  * @note   In System STOP mode, when the voltage regulator operates in low
+  *         power mode, an additional startup delay is incurred when the system
+  *         is waking up. By keeping the internal regulator ON during STOP mode,
+  *         the consumption is higher although the startup time is reduced.
+  * @retval None.
+  */
+void HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry)
+{
+  /* Check the parameters */
+  assert_param (IS_PWR_REGULATOR (Regulator));
+  assert_param (IS_PWR_STOP_ENTRY (STOPEntry));
+
+  /* Select the regulator state in STOP mode */
+  MODIFY_REG (PWR->CR1, PWR_CR1_LPDS, Regulator);
+
+  /* Configure the PWR mode for the different Domains */
+#if defined (DUAL_CORE)
+  /* Check CPU ID */
+  if (HAL_GetCurrentCPUID () == CM7_CPUID)
+  {
+    /* Keep DSTOP mode when Cortex-M7 enters DEEP-SLEEP */
+    CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
+  }
+  else
+  {
+    /* Keep DSTOP mode when Cortex-M4 enters DEEP-SLEEP */
+    CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D2 | PWR_CPUCR_PDDS_D3));
+  }
+#else /* Single core devices */
+  /* Keep DSTOP mode when Cortex-M7 enter in DEEP-SLEEP */
+  CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
+
+#if defined (PWR_CPUCR_PDDS_D2)
+  /* Keep DSTOP mode when Cortex-M7 enter in DEEP-SLEEP */
+  CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2);
+#endif /* PWR_CPUCR_PDDS_D2 */
+#endif /* defined (DUAL_CORE) */
+
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+
+  /* Ensure that all instructions are done before entering STOP mode */
+  __DSB ();
+  __ISB ();
+
+  /* Select STOP mode entry */
+  if (STOPEntry == PWR_STOPENTRY_WFI)
+  {
+    /* Request Wait For Interrupt */
+    __WFI ();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __WFE ();
+  }
+
+  /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */
+  CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+}
+
+/**
+  * @brief  Enter STANDBY mode.
+  * @note   For single core devices, this API will enter the system in STANDBY
+  *         mode with all domains in DSTANDBY, if RUN_D3/RUN_SRD bit in CPUCR
+  *         regiter is cleared.
+  *         For dual core devices, this API will enter the domain (containing
+  *         Cortex-Mx that executing this function) in DSTANDBY mode. If all
+  *         Cortex-Mx domains are in DSTANDBY and RUN_D3 bit in CPUCR register
+  *         is cleared, all the system will enter in STANDBY mode.
+  * @note   The system enters Standby mode only when all domains are in DSTANDBY.
+  * @note   When the System exit STANDBY mode by issuing an interrupt or a
+  *         wakeup event, the HSI RC oscillator is selected as system clock.
+  * @retval None.
+  */
+void HAL_PWR_EnterSTANDBYMode (void)
+{
+  /* Configure the PWR mode for the different Domains */
+#if defined (DUAL_CORE)
+  /* Check CPU ID */
+  if (HAL_GetCurrentCPUID () == CM7_CPUID)
+  {
+    /* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */
+    SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
+    SET_BIT (PWR->CPU2CR, (PWR_CPU2CR_PDDS_D1 | PWR_CPU2CR_PDDS_D3));
+  }
+  else
+  {
+    /* Enter DSTANDBY mode when Cortex-M4 enters DEEP-SLEEP */
+    SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D2 | PWR_CPUCR_PDDS_D3));
+    SET_BIT (PWR->CPU2CR, (PWR_CPU2CR_PDDS_D2 | PWR_CPU2CR_PDDS_D3));
+  }
+#else /* Single core devices */
+  /* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */
+  SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3));
+
+#if defined (PWR_CPUCR_PDDS_D2)
+  /* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */
+  SET_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2);
+#endif /* PWR_CPUCR_PDDS_D2 */
+#endif /* defined (DUAL_CORE) */
+
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+
+  /* Ensure that all instructions are done before entering STOP mode */
+  __DSB ();
+  __ISB ();
+
+  /* This option is used to ensure that store operations are completed */
+#if defined (__CC_ARM)
+  __force_stores();
+#endif /* defined (__CC_ARM) */
+
+  /* Request Wait For Interrupt */
+  __WFI ();
+}
+
+/**
+  * @brief  Indicate Sleep-On-Exit feature when returning from Handler mode to
+  *         Thread mode.
+  * @note   Set SLEEPONEXIT bit of SCR register. When this bit is set, the
+  *         processor re-enters SLEEP mode when an interruption handling is over.
+  *         Setting this bit is useful when the processor is expected to run
+  *         only on interruptions handling.
+  * @retval None.
+  */
+void HAL_PWR_EnableSleepOnExit (void)
+{
+  /* Set SLEEPONEXIT bit of Cortex-Mx System Control Register */
+  SET_BIT (SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
+}
+
+/**
+  * @brief  Disable Sleep-On-Exit feature when returning from Handler mode to
+  *         Thread mode.
+  * @note   Clears SLEEPONEXIT bit of SCR register. When this bit is set, the
+  *         processor re-enters SLEEP mode when an interruption handling is over.
+  * @retval None
+  */
+void HAL_PWR_DisableSleepOnExit (void)
+{
+  /* Clear SLEEPONEXIT bit of Cortex-Mx System Control Register */
+  CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
+}
+
+/**
+  * @brief  Enable CORTEX SEVONPEND feature.
+  * @note   Sets SEVONPEND bit of SCR register. When this bit is set, any
+  *         pending event / interrupt even if it's disabled or has insufficient
+  *         priority to cause exception entry wakes up the Cortex-Mx.
+  * @retval None.
+  */
+void HAL_PWR_EnableSEVOnPend (void)
+{
+  /* Set SEVONPEND bit of Cortex-Mx System Control Register */
+  SET_BIT (SCB->SCR, SCB_SCR_SEVONPEND_Msk);
+}
+
+/**
+  * @brief  Disable CORTEX SEVONPEND feature.
+  * @note   Resets SEVONPEND bit of SCR register. When this bit is reset, only
+  *         enabled pending causes exception entry wakes up the Cortex-Mx.
+  * @retval None.
+  */
+void HAL_PWR_DisableSEVOnPend (void)
+{
+  /* Clear SEVONPEND bit of Cortex System Control Register */
+  CLEAR_BIT (SCB->SCR, SCB_SCR_SEVONPEND_Msk);
+}
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Exported_Functions_Group3 Interrupt Handling Functions
+  *  @brief   Interrupt Handling functions
+  *
+@verbatim
+ ===============================================================================
+                    ##### Interrupt Handling Functions #####
+ ===============================================================================
+    [..]
+    This section provides functions allowing to handle the PVD pending
+    interrupts.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function handles the PWR PVD interrupt request.
+  * @note   This API should be called under the PVD_AVD_IRQHandler().
+  * @retval None.
+  */
+void HAL_PWR_PVD_IRQHandler (void)
+{
+#if defined (DUAL_CORE)
+  /* Check Cortex-Mx ID */
+  if (HAL_GetCurrentCPUID () == CM7_CPUID)
+  {
+    /* Check PWR EXTI D1 flag */
+    if(__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U)
+    {
+      /* Clear PWR EXTI D1 pending bit */
+      __HAL_PWR_PVD_EXTI_CLEAR_FLAG ();
+
+      /* PWR PVD interrupt user callback */
+      HAL_PWR_PVDCallback ();
+    }
+  }
+  else
+  {
+    /* Check PWR EXTI D2 flag */
+    if (__HAL_PWR_PVD_EXTID2_GET_FLAG () != 0U)
+    {
+      /* Clear PWR EXTI D2 pending bit */
+      __HAL_PWR_PVD_EXTID2_CLEAR_FLAG ();
+
+      /* PWR PVD interrupt user callback */
+      HAL_PWR_PVDCallback ();
+    }
+  }
+#else /* Single core devices */
+  /* PVD EXTI line interrupt detected */
+  if (__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U)
+  {
+    /* Clear PWR EXTI pending bit */
+    __HAL_PWR_PVD_EXTI_CLEAR_FLAG ();
+
+    /* PWR PVD interrupt user callback */
+    HAL_PWR_PVDCallback ();
+  }
+#endif /* defined (DUAL_CORE) */
+}
+
+/**
+  * @brief  PWR PVD interrupt callback.
+  * @retval None.
+  */
+__weak void HAL_PWR_PVDCallback (void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PWR_PVDCallback can be implemented in the user file
+  */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_PWR_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c
new file mode 100644
index 00000000..82288f9e
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c
@@ -0,0 +1,2100 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_pwr_ex.c
+  * @author  MCD Application Team
+  * @brief   Extended PWR HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of PWR extension peripheral:
+  *           + Peripheral Extended features functions
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+   (#) Call HAL_PWREx_ConfigSupply() function to configure the regulator supply
+       with the following different setups according to hardware (support SMPS):
+       (+) PWR_DIRECT_SMPS_SUPPLY
+       (+) PWR_SMPS_1V8_SUPPLIES_LDO
+       (+) PWR_SMPS_2V5_SUPPLIES_LDO
+       (+) PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO
+       (+) PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO
+       (+) PWR_SMPS_1V8_SUPPLIES_EXT
+       (+) PWR_SMPS_2V5_SUPPLIES_EXT
+       (+) PWR_LDO_SUPPLY
+       (+) PWR_EXTERNAL_SOURCE_SUPPLY
+
+   (#) Call HAL_PWREx_GetSupplyConfig() function to get the current supply setup.
+
+   (#) Call HAL_PWREx_ControlVoltageScaling() function to configure the main
+       internal regulator output voltage. The voltage scaling could be one of
+       the following scales :
+       (+) PWR_REGULATOR_VOLTAGE_SCALE0
+       (+) PWR_REGULATOR_VOLTAGE_SCALE1
+       (+) PWR_REGULATOR_VOLTAGE_SCALE2
+       (+) PWR_REGULATOR_VOLTAGE_SCALE3
+
+   (#) Call HAL_PWREx_GetVoltageRange() function to get the current output
+       voltage applied to the main regulator.
+
+   (#) Call HAL_PWREx_ControlStopModeVoltageScaling() function to configure the
+       main internal regulator output voltage in STOP mode. The voltage scaling
+       in STOP mode could be one of the following scales :
+       (+) PWR_REGULATOR_SVOS_SCALE3
+       (+) PWR_REGULATOR_SVOS_SCALE4
+       (+) PWR_REGULATOR_SVOS_SCALE5
+
+   (#) Call HAL_PWREx_GetStopModeVoltageRange() function to get the current
+       output voltage applied to the main regulator in STOP mode.
+
+   (#) Call HAL_PWREx_EnterSTOP2Mode() function to enter the system in STOP mode
+       with core domain in D2STOP mode. This API is used only for STM32H7Axxx
+       and STM32H7Bxxx devices.
+       Please ensure to clear all CPU pending events by calling
+       HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx
+       in DEEP-SLEEP mode with __WFE() entry.
+
+   (#) Call HAL_PWREx_EnterSTOPMode() function to enter the selected domain in
+       DSTOP mode. Call this API with all available power domains to enter the
+       system in STOP mode.
+       Please ensure to clear all CPU pending events by calling
+       HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx
+       in DEEP-SLEEP mode with __WFE() entry.
+
+   (#) Call HAL_PWREx_ClearPendingEvent() function always before entring the
+       Cortex-Mx in any low power mode (SLEEP/DEEP-SLEEP) using WFE entry.
+
+   (#) Call HAL_PWREx_EnterSTANDBYMode() function to enter the selected domain
+       in DSTANDBY mode. Call this API with all available power domains to enter
+       the system in STANDBY mode.
+
+   (#) Call HAL_PWREx_ConfigD3Domain() function to setup the D3/SRD domain state
+       (RUN/STOP) when the system enter to low power mode.
+
+   (#) Call HAL_PWREx_ClearDomainFlags() function to clear the CPU flags for the
+       selected power domain. This API is used only for dual core devices.
+
+   (#) Call HAL_PWREx_HoldCore() and HAL_PWREx_ReleaseCore() functions to hold
+       and release the selected CPU and and their domain peripherals when
+       exiting STOP mode. These APIs are used only for dual core devices.
+
+   (#) Call HAL_PWREx_EnableFlashPowerDown() and
+       HAL_PWREx_DisableFlashPowerDown() functions to enable and disable the
+       Flash Power Down in STOP mode.
+
+   (#) Call HAL_PWREx_EnableMemoryShutOff() and
+       HAL_PWREx_DisableMemoryShutOff() functions to enable and disable the
+       memory block shut-off in DStop or DStop2. These APIs are used only for
+       STM32H7Axxx and STM32H7Bxxx lines.
+
+   (#) Call HAL_PWREx_EnableWakeUpPin() and HAL_PWREx_DisableWakeUpPin()
+       functions to enable and disable the Wake-up pin functionality for
+       the selected pin.
+
+   (#) Call HAL_PWREx_GetWakeupFlag() and HAL_PWREx_ClearWakeupFlag()
+       functions to manage wake-up flag for the selected pin.
+
+   (#) Call HAL_PWREx_WAKEUP_PIN_IRQHandler() function to handle all wake-up
+       pins interrupts.
+
+   (#) Call HAL_PWREx_EnableBkUpReg() and HAL_PWREx_DisableBkUpReg() functions
+       to enable and disable the backup domain regulator.
+
+   (#) Call HAL_PWREx_EnableUSBReg(), HAL_PWREx_DisableUSBReg(),
+       HAL_PWREx_EnableUSBVoltageDetector() and
+       HAL_PWREx_DisableUSBVoltageDetector() functions to manage USB power
+       regulation functionnalities.
+
+   (#) Call HAL_PWREx_EnableBatteryCharging() and
+       HAL_PWREx_DisableBatteryCharging() functions to enable and disable the
+       battery charging feature with the selected resistor.
+
+   (#) Call HAL_PWREx_EnableAnalogBooster() and
+       HAL_PWREx_DisableAnalogBooster() functions to enable and disable the
+       AVD boost feature when the VDD supply voltage is below 2V7.
+
+   (#) Call HAL_PWREx_EnableMonitoring() and HAL_PWREx_DisableMonitoring()
+       functions to enable and disable the VBAT and Temperature monitoring.
+       When VBAT and Temperature monitoring feature is enables, use
+       HAL_PWREx_GetTemperatureLevel() and HAL_PWREx_GetVBATLevel() to get
+       respectively the Temperature level and VBAT level.
+
+   (#) Call HAL_PWREx_GetMMCVoltage() and HAL_PWREx_DisableMonitoring()
+       function to get VDDMMC voltage level. This API is used only for
+       STM32H7AxxQ, STM32H7BxxQ, STM32H7Axxx and STM32H7Bxxx lines
+
+   (#) Call HAL_PWREx_ConfigAVD() after setting parameter to be configured
+       (event mode and voltage threshold) in order to set up the Analog Voltage
+       Detector then use HAL_PWREx_EnableAVD() and  HAL_PWREx_DisableAVD()
+       functions to start and stop the AVD detection.
+       (+) AVD level could be one of the following values :
+             (++) 1V7
+             (++) 2V1
+             (++) 2V5
+             (++) 2V8
+
+   (#) Call HAL_PWREx_PVD_AVD_IRQHandler() function to handle the PWR PVD and
+       AVD interrupt request.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup PWREx PWREx
+  * @brief PWR Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @addtogroup PWREx_Private_Constants
+  * @{
+  */
+
+/** @defgroup PWREx_AVD_Mode_Mask PWR Extended AVD Mode Mask
+  * @{
+  */
+#define AVD_MODE_IT              (0x00010000U)
+#define AVD_MODE_EVT             (0x00020000U)
+#define AVD_RISING_EDGE          (0x00000001U)
+#define AVD_FALLING_EDGE         (0x00000002U)
+#define AVD_RISING_FALLING_EDGE  (0x00000003U)
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_REG_SET_TIMEOUT PWR Extended Flag Setting Time Out Value
+  * @{
+  */
+#define PWR_FLAG_SETTING_DELAY   (1000U)
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_WakeUp_Pins_Offsets PWREx Wake-Up Pins masks and offsets
+  * @{
+  */
+/* Wake-Up Pins EXTI register mask */
+#define PWR_EXTI_WAKEUP_PINS_MASK  (EXTI_IMR2_IM55 | EXTI_IMR2_IM56 |\
+                                    EXTI_IMR2_IM57 | EXTI_IMR2_IM58 |\
+                                    EXTI_IMR2_IM59 | EXTI_IMR2_IM60)
+
+/* Wake-Up Pins PWR Pin Pull shift offsets */
+#define PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET (2U)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup PWREx_Exported_Functions PWREx Exported Functions
+  * @{
+  */
+
+/** @defgroup PWREx_Exported_Functions_Group1 Power Supply Control Functions
+  * @brief    Power supply control functions
+  *
+@verbatim
+ ===============================================================================
+                  ##### Power supply control functions #####
+ ===============================================================================
+    [..]
+   (#) When the system is powered on, the POR monitors VDD supply. Once VDD is
+       above the POR threshold level, the voltage regulator is enabled in the
+       default supply configuration:
+      (+) The Voltage converter output level is set at 1V0 in accordance with
+          the VOS3 level configured in PWR (D3/SRD) domain control register
+          (PWR_D3CR/PWR_SRDCR).
+      (+) The system is kept in reset mode as long as VCORE is not ok.
+      (+) Once VCORE is ok, the system is taken out of reset and the HSI
+          oscillator is enabled.
+      (+) Once the oscillator is stable, the system is initialized: Flash memory
+          and option bytes are loaded and the CPU starts in Run* mode.
+      (+) The software shall then initialize the system including supply
+          configuration programming using the HAL_PWREx_ConfigSupply().
+      (+) Once the supply configuration has been configured, the
+          HAL_PWREx_ConfigSupply() function checks the ACTVOSRDY bit in PWR
+          control status register 1 (PWR_CSR1) to guarantee a valid voltage
+          levels:
+       (++) As long as ACTVOSRDY indicates that voltage levels are invalid, the
+            system is in limited Run* mode, write accesses to the RAMs are not
+            permitted and VOS shall not be changed.
+       (++) Once ACTVOSRDY indicates that voltage levels are valid, the system
+            is in normal Run mode, write accesses to RAMs are allowed and VOS
+            can be changed.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Configure the system Power Supply.
+  * @param  SupplySource : Specifies the Power Supply source to set after a
+  *                        system startup.
+  *         This parameter can be one of the following values :
+  *            @arg PWR_DIRECT_SMPS_SUPPLY : The SMPS supplies the Vcore Power
+  *                                          Domains. The LDO is Bypassed.
+  *            @arg PWR_SMPS_1V8_SUPPLIES_LDO : The SMPS 1.8V output supplies
+  *                                             the LDO. The Vcore Power Domains
+  *                                             are supplied from the LDO.
+  *            @arg PWR_SMPS_2V5_SUPPLIES_LDO : The SMPS 2.5V output supplies
+  *                                             the LDO. The Vcore Power Domains
+  *                                             are supplied from the LDO.
+  *            @arg PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO : The SMPS 1.8V output
+  *                                                     supplies external
+  *                                                     circuits and the LDO.
+  *                                                     The Vcore Power Domains
+  *                                                     are supplied from the
+  *                                                     LDO.
+  *            @arg PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO : The SMPS 2.5V output
+  *                                                     supplies external
+  *                                                     circuits and the LDO.
+  *                                                     The Vcore Power Domains
+  *                                                     are supplied from the
+  *                                                     LDO.
+  *            @arg PWR_SMPS_1V8_SUPPLIES_EXT : The SMPS 1.8V output supplies
+  *                                             external circuits. The LDO is
+  *                                             Bypassed. The Vcore Power
+  *                                             Domains are supplied from
+  *                                             external source.
+  *            @arg PWR_SMPS_2V5_SUPPLIES_EXT : The SMPS 2.5V output supplies
+  *                                             external circuits. The LDO is
+  *                                             Bypassed. The Vcore Power
+  *                                             Domains are supplied from
+  *                                             external source.
+  *            @arg PWR_LDO_SUPPLY : The LDO regulator supplies the Vcore Power
+  *                                  Domains. The SMPS regulator is Bypassed.
+  *            @arg PWR_EXTERNAL_SOURCE_SUPPLY : The SMPS and the LDO are
+  *                                              Bypassed. The Vcore Power
+  *                                              Domains are supplied from
+  *                                              external source.
+  * @note   The PWR_LDO_SUPPLY and PWR_EXTERNAL_SOURCE_SUPPLY are used by all
+  *         H7 lines.
+  *         The PWR_DIRECT_SMPS_SUPPLY, PWR_SMPS_1V8_SUPPLIES_LDO,
+  *         PWR_SMPS_2V5_SUPPLIES_LDO, PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO,
+  *         PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO, PWR_SMPS_1V8_SUPPLIES_EXT and
+  *         PWR_SMPS_2V5_SUPPLIES_EXT are used only for lines that supports SMPS
+  *         regulator.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource)
+{
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param (IS_PWR_SUPPLY (SupplySource));
+
+  /* Check if supply source was configured */
+#if defined (PWR_FLAG_SCUEN)
+  if (__HAL_PWR_GET_FLAG (PWR_FLAG_SCUEN) == 0U)
+#else
+  if ((PWR->CR3 & (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)) != (PWR_CR3_SMPSEN | PWR_CR3_LDOEN))
+#endif /* defined (PWR_FLAG_SCUEN) */
+  {
+    /* Check supply configuration */
+    if ((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource)
+    {
+      /* Supply configuration update locked, can't apply a new supply config */
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Supply configuration update locked, but new supply configuration
+         matches with old supply configuration : nothing to do
+      */
+      return HAL_OK;
+    }
+  }
+
+  /* Set the power supply configuration */
+  MODIFY_REG (PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource);
+
+  /* Get tick */
+  tickstart = HAL_GetTick ();
+
+  /* Wait till voltage level flag is set */
+  while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
+  {
+    if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+#if defined (SMPS)
+  /* When the SMPS supplies external circuits verify that SDEXTRDY flag is set */
+  if ((SupplySource == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) ||
+      (SupplySource == PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) ||
+      (SupplySource == PWR_SMPS_1V8_SUPPLIES_EXT)         ||
+      (SupplySource == PWR_SMPS_2V5_SUPPLIES_EXT))
+  {
+    /* Get the current tick number */
+    tickstart = HAL_GetTick ();
+
+    /* Wait till SMPS external supply ready flag is set */
+    while (__HAL_PWR_GET_FLAG (PWR_FLAG_SMPSEXTRDY) == 0U)
+    {
+      if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY)
+      {
+        return HAL_ERROR;
+      }
+    }
+  }
+#endif /* defined (SMPS) */
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Get the power supply configuration.
+  * @retval The supply configuration.
+  */
+uint32_t HAL_PWREx_GetSupplyConfig (void)
+{
+  return (PWR->CR3 & PWR_SUPPLY_CONFIG_MASK);
+}
+
+/**
+  * @brief Configure the main internal regulator output voltage.
+  * @note   For STM32H7x3, STM32H7x5, STM32H7x7, STM32H742 and STM32H750 lines,
+  *         configuring Voltage Scale 0 is only possible when Vcore is supplied
+  *         from LDO (Low DropOut). The SYSCFG Clock must be enabled through
+  *         __HAL_RCC_SYSCFG_CLK_ENABLE() macro before configuring Voltage
+  *         Scale 0.
+  * @param  VoltageScaling : Specifies the regulator output voltage to achieve
+  *                          a tradeoff between performance and power
+  *                          consumption.
+  *          This parameter can be one of the following values :
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE0 : Regulator voltage output
+  *                                                Scale 0 mode.
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output
+  *                                                range 1 mode.
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output
+  *                                                range 2 mode.
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output
+  *                                                range 3 mode.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling)
+{
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param (IS_PWR_REGULATOR_VOLTAGE (VoltageScaling));
+
+  /* Get the voltage scaling  */
+  if ((PWR->CSR1 & PWR_CSR1_ACTVOS) == VoltageScaling)
+  {
+    /* Old and new voltage scaling configuration match : nothing to do */
+    return HAL_OK;
+  }
+
+#if defined (PWR_SRDCR_VOS)
+  /* Set the voltage range */
+  MODIFY_REG (PWR->SRDCR, PWR_SRDCR_VOS, VoltageScaling);
+#else
+  if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE0)
+  {
+    if ((PWR->CR3 & PWR_CR3_LDOEN) == PWR_CR3_LDOEN)
+    {
+      /* Set the voltage range */
+      MODIFY_REG (PWR->D3CR, PWR_D3CR_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
+
+      /* Get tick */
+      tickstart = HAL_GetTick ();
+
+      /* Wait till voltage level flag is set */
+      while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
+      {
+        if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY)
+        {
+          return HAL_ERROR;
+        }
+      }
+
+      /* Enable the PWR overdrive */
+      SET_BIT (SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);
+    }
+    else
+    {
+      /* The voltage scale 0 is only possible when LDO regulator is enabled */
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    if ((PWR->CSR1 & PWR_CSR1_ACTVOS) == PWR_REGULATOR_VOLTAGE_SCALE1)
+    {
+      if ((SYSCFG->PWRCR & SYSCFG_PWRCR_ODEN) != 0U)
+      {
+        /* Disable the PWR overdrive */
+        CLEAR_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);
+
+        /* Get tick */
+        tickstart = HAL_GetTick ();
+
+        /* Wait till voltage level flag is set */
+        while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
+        {
+          if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY)
+          {
+            return HAL_ERROR;
+          }
+        }
+      }
+    }
+
+    /* Set the voltage range */
+    MODIFY_REG (PWR->D3CR, PWR_D3CR_VOS, VoltageScaling);
+  }
+#endif /* defined (PWR_SRDCR_VOS) */
+
+  /* Get tick */
+  tickstart = HAL_GetTick ();
+
+  /* Wait till voltage level flag is set */
+  while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > PWR_FLAG_SETTING_DELAY)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Get the main internal regulator output voltage. Reflecting the last
+  *        VOS value applied to the PMU.
+  * @retval The current applied VOS selection.
+  */
+uint32_t HAL_PWREx_GetVoltageRange (void)
+{
+  /* Get the active voltage scaling */
+  return (PWR->CSR1 & PWR_CSR1_ACTVOS);
+}
+
+/**
+  * @brief Configure the main internal regulator output voltage in STOP mode.
+  * @param  VoltageScaling : Specifies the regulator output voltage when the
+  *         system enters Stop mode to achieve a tradeoff between performance
+  *         and power consumption.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_REGULATOR_SVOS_SCALE3 : Regulator voltage output range
+  *                                             3 mode.
+  *            @arg PWR_REGULATOR_SVOS_SCALE4 : Regulator voltage output range
+  *                                             4 mode.
+  *            @arg PWR_REGULATOR_SVOS_SCALE5 : Regulator voltage output range
+  *                                             5 mode.
+  * @note   The Stop mode voltage scaling for SVOS4 and SVOS5 sets the voltage
+  *         regulator in Low-power (LP) mode to further reduce power consumption.
+  *         When preselecting SVOS3, the use of the voltage regulator low-power
+  *         mode (LP) can be selected by LPDS register bit.
+  * @note   The selected SVOS4 and SVOS5 levels add an additional startup delay
+  *         when exiting from system Stop mode.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling (uint32_t VoltageScaling)
+{
+  /* Check the parameters */
+  assert_param (IS_PWR_STOP_MODE_REGULATOR_VOLTAGE (VoltageScaling));
+
+  /* Return the stop mode voltage range */
+  MODIFY_REG (PWR->CR1, PWR_CR1_SVOS, VoltageScaling);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Get the main internal regulator output voltage in STOP mode.
+  * @retval The actual applied VOS selection.
+  */
+uint32_t HAL_PWREx_GetStopModeVoltageRange (void)
+{
+  /* Return the stop voltage scaling */
+  return (PWR->CR1 & PWR_CR1_SVOS);
+}
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_Exported_Functions_Group2 Low Power Control Functions
+  * @brief    Low power control functions
+  *
+@verbatim
+ ===============================================================================
+                     ##### Low power control functions #####
+ ===============================================================================
+
+    *** Domains Low Power modes configuration ***
+    =============================================
+    [..]
+      This section provides the extended low power mode control APIs.
+      The system presents 3 principles domains (D1, D2 and D3) that can be
+      operated in low-power modes (DSTOP or DSTANDBY mode):
+
+      (+) DSTOP mode to enters a domain to STOP mode:
+       (++) D1 domain and/or D2 domain enters DSTOP mode only when the CPU
+            subsystem is in CSTOP mode and has allocated peripheral in the
+            domain.
+            In DSTOP mode the domain bus matrix clock is stopped.
+       (++) The system enters STOP mode using one of the following scenarios:
+        (+++) D1 domain enters DSTANDBY mode (powered off) and D2, D3 domains
+              enter DSTOP mode.
+        (+++) D2 domain enters DSTANDBY mode (powered off) and D1, D3 domains
+              enter DSTOP mode.
+        (+++) D3 domain enters DSTANDBY mode (powered off) and D1, D2 domains
+              enter DSTOP mode.
+        (+++) D1 and D2 domains enter DSTANDBY mode (powered off) and D3 domain
+              enters DSTOP mode.
+        (+++) D1 and D3 domains enter DSTANDBY mode (powered off) and D2 domain
+              enters DSTOP mode.
+        (+++) D2 and D3 domains enter DSTANDBY mode (powered off) and D1 domain
+              enters DSTOP mode.
+        (+++) D1, D2 and D3 domains enter DSTOP mode.
+       (++) When the system enters STOP mode, the clocks are stopped and the
+            regulator is running in main or low power mode.
+       (++) D3 domain can be kept in Run mode regardless of the CPU status when
+            enter STOP mode by using HAL_PWREx_ConfigD3Domain(D3State) function.
+
+      (+) DSTANDBY mode to enters a domain to STANDBY mode:
+       (++) The DSTANDBY mode is entered when the PDDS_Dn bit in PWR CPU control
+            register (PWR_CPUCR) for the Dn domain selects Standby mode.
+       (++) The system enters STANDBY mode only when D1, D2 and D3 domains enter
+            DSTANDBY mode. Consequently the VCORE supply regulator is powered
+            off.
+
+   *** DSTOP mode ***
+   ==================
+    [..]
+      In DStop mode the domain bus matrix clock is stopped.
+      The Flash memory can enter low-power Stop mode when it is enabled through
+      FLPS in PWR_CR1 register. This allows a trade-off between domain DStop
+      restart time and low power consumption.
+    [..]
+      In DStop mode domain peripherals using the LSI or LSE clock and
+      peripherals having a kernel clock request are still able to operate.
+    [..]
+      Before entering DSTOP mode it is recommended to call SCB_CleanDCache
+      function in order to clean the D-Cache and guarantee the data integrity
+      for the SRAM memories.
+
+      (+) Entry:
+         The DSTOP mode is entered using the HAL_PWREx_EnterSTOPMode(Regulator,
+         STOPEntry, Domain) function with:
+         (++) Regulator:
+          (+++) PWR_MAINREGULATOR_ON     : Main regulator ON.
+          (+++) PWR_LOWPOWERREGULATOR_ON : Low Power regulator ON.
+         (++) STOPEntry:
+          (+++) PWR_STOPENTRY_WFI : enter STOP mode with WFI instruction
+          (+++) PWR_STOPENTRY_WFE : enter STOP mode with WFE instruction
+         (++) Domain:
+          (+++) PWR_D1_DOMAIN : Enters D1 domain to DSTOP mode.
+          (+++) PWR_D2_DOMAIN : Enters D2 domain to DSTOP mode.
+          (+++) PWR_D3_DOMAIN : Enters D3 domain to DSTOP mode.
+
+      (+) Exit:
+        Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
+
+   *** DSTANDBY mode ***
+   =====================
+    [..]
+      In DStandby mode:
+        (+) The domain bus matrix clock is stopped.
+        (+) The domain is powered down and the domain RAM and register contents
+            are lost.
+    [..]
+      Before entering DSTANDBY mode it is recommended to call SCB_CleanDCache
+      function in order to clean the D-Cache and guarantee the data integrity
+      for the SRAM memories.
+
+      (+) Entry:
+         The DSTANDBY mode is entered using the HAL_PWREx_EnterSTANDBYMode
+         (Domain) function with:
+       (++) Domain:
+        (+++) PWR_D1_DOMAIN : Enters D1 domain to DSTANDBY mode.
+        (+++) PWR_D2_DOMAIN : Enters D2 domain to DSTANDBY mode.
+        (+++) PWR_D3_DOMAIN : Enters D3 domain to DSTANDBY mode.
+
+      (+) Exit:
+        WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC
+        wakeup, tamper event, time stamp event, external reset in NRST pin,
+        IWDG reset.
+
+   *** Keep D3/SRD in RUN mode ***
+   ===============================
+    [..]
+      D3/SRD domain can be kept in Run mode regardless of the CPU status when
+      entering STOP mode by using HAL_PWREx_ConfigD3Domain(D3State) function
+      with :
+       (+) D3State:
+        (++) PWR_D3_DOMAIN_STOP : D3/SDR domain follows the CPU sub-system
+                                  mode.
+        (++) PWR_D3_DOMAIN_RUN : D3/SRD domain remains in Run mode regardless
+                                 of CPU subsystem mode.
+
+    *** FLASH Power Down configuration ****
+    =======================================
+    [..]
+      By setting the FLPS bit in the PWR_CR1 register using the
+      HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters
+      power down mode when the device enters STOP mode. When the Flash memory is
+      in power down mode, an additional startup delay is incurred when waking up
+      from STOP mode.
+
+    *** Wakeup Pins configuration ****
+    ===================================
+    [..]
+      Wakeup pins allow the system to exit from Standby mode. The configuration
+      of wakeup pins is done with the HAL_PWREx_EnableWakeUpPin(sPinParams)
+      function with:
+       (+) sPinParams: structure to enable and configure a wakeup pin:
+        (++) WakeUpPin: Wakeup pin to be enabled.
+        (++) PinPolarity: Wakeup pin polarity (rising or falling edge).
+        (++) PinPull: Wakeup pin pull (no pull, pull-up or pull-down).
+    [..]
+      The wakeup pins are internally connected to the EXTI lines [55-60] to
+      generate an interrupt if enabled. The EXTI lines configuration is done by
+      the HAL_EXTI_Dx_EventInputConfig() functions defined in the stm32h7xxhal.c
+      file.
+    [..]
+      When a wakeup pin event is received the HAL_PWREx_WAKEUP_PIN_IRQHandler is
+      called and the appropriate flag is set in the PWR_WKUPFR register. Then in
+      the HAL_PWREx_WAKEUP_PIN_IRQHandler function the wakeup pin flag will be
+      cleared and the appropriate user callback will be called. The user can add
+      his own code by customization of function pointer HAL_PWREx_WKUPx_Callback.
+
+@endverbatim
+  * @{
+  */
+
+#if defined (PWR_CPUCR_RETDS_CD)
+/**
+  * @brief Enter the system to STOP mode with main domain in DSTOP2.
+  * @note   In STOP mode, the domain bus matrix clock is stalled.
+  * @note   In STOP mode, memories and registers are maintained and peripherals
+  *         in CPU domain are no longer operational.
+  * @note   All clocks in the VCORE domain are stopped, the PLL, the HSI and the
+  *         HSE oscillators are disabled. Only Peripherals that have wakeup
+  *         capability can switch on the HSI to receive a frame, and switch off
+  *         the HSI after receiving the frame if it is not a wakeup frame. In
+  *         this case the HSI clock is propagated only to the peripheral
+  *         requesting it.
+  * @note   When exiting STOP mode by issuing an interrupt or a wakeup event,
+  *         the HSI RC oscillator is selected as system clock if STOPWUCK bit in
+  *         RCC_CFGR register is set.
+  * @param  Regulator : Specifies the regulator state in STOP mode.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_MAINREGULATOR_ON     : STOP mode with regulator ON.
+  *            @arg PWR_LOWPOWERREGULATOR_ON : STOP mode with low power
+  *                                            regulator ON.
+  * @param  STOPEntry : Specifies if STOP mode in entered with WFI or WFE
+  *                     intrinsic instruction.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction.
+  *            @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction.
+  * @retval None.
+  */
+void HAL_PWREx_EnterSTOP2Mode (uint32_t Regulator, uint8_t STOPEntry)
+{
+  /* Check the parameters */
+  assert_param (IS_PWR_REGULATOR (Regulator));
+  assert_param (IS_PWR_STOP_ENTRY (STOPEntry));
+
+  /* Select the regulator state in Stop mode */
+  MODIFY_REG (PWR->CR1, PWR_CR1_LPDS, Regulator);
+
+  /* Go to DStop2 mode (deep retention) when CPU domain enters Deepsleep */
+  SET_BIT (PWR->CPUCR, PWR_CPUCR_RETDS_CD);
+
+  /* Keep DSTOP mode when SmartRun domain enters Deepsleep */
+  CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_SRD);
+
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+
+  /* Ensure that all instructions are done before entering STOP mode */
+  __ISB ();
+  __DSB ();
+
+  /* Select Stop mode entry */
+  if (STOPEntry == PWR_STOPENTRY_WFI)
+  {
+    /* Request Wait For Interrupt */
+    __WFI ();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __WFE ();
+  }
+
+  /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */
+  CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+}
+#endif /* defined (PWR_CPUCR_RETDS_CD) */
+
+/**
+  * @brief Enter a Domain to DSTOP mode.
+  * @note   This API gives flexibility to manage independently each domain STOP
+  *         mode. For dual core lines, this API should be executed with the
+  *         corresponding Cortex-Mx to enter domain to DSTOP mode. When it is
+  *         executed by all available Cortex-Mx, the system enter to STOP mode.
+  *         For single core lines, calling this API with domain parameter set to
+  *         PWR_D1_DOMAIN (D1/CD), the whole system will enter in STOP mode
+  *         independently of PWR_CPUCR_PDDS_Dx bits values if RUN_D3 bit in the
+  *         CPUCR_RUN_D3 is cleared.
+  * @note   In DStop mode the domain bus matrix clock is stopped.
+  * @note   The system D3/SRD domain enter Stop mode only when the CPU subsystem
+  *         is in CStop mode, the EXTI wakeup sources are inactive and at least
+  *         one PDDS_Dn bit in PWR CPU control register (PWR_CPUCR) for
+  *         any domain request Stop.
+  * @note   Before entering DSTOP mode it is recommended to call SCB_CleanDCache
+  *         function in order to clean the D-Cache and guarantee the data
+  *         integrity for the SRAM memories.
+  * @note   In System Stop mode, the domain peripherals that use the LSI or LSE
+  *         clock, and the peripherals that have a kernel clock request to
+  *         select HSI or CSI as source, are still able to operate.
+  * @param  Regulator : Specifies the regulator state in STOP mode.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_MAINREGULATOR_ON     : STOP mode with regulator ON.
+  *            @arg PWR_LOWPOWERREGULATOR_ON : STOP mode with low power
+  *                                            regulator ON.
+  * @param  STOPEntry : Specifies if STOP mode in entered with WFI or WFE
+  *                     intrinsic instruction.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction.
+  *            @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction.
+  * @param  Domain : Specifies the Domain to enter in DSTOP mode.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_D1_DOMAIN : Enter D1/CD Domain to DSTOP mode.
+  *            @arg PWR_D2_DOMAIN : Enter D2 Domain to DSTOP mode.
+  *            @arg PWR_D3_DOMAIN : Enter D3/SRD Domain to DSTOP mode.
+  * @retval None.
+  */
+void HAL_PWREx_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain)
+{
+  /* Check the parameters */
+  assert_param (IS_PWR_REGULATOR (Regulator));
+  assert_param (IS_PWR_STOP_ENTRY (STOPEntry));
+  assert_param (IS_PWR_DOMAIN (Domain));
+
+  /* Select the regulator state in Stop mode */
+  MODIFY_REG (PWR->CR1, PWR_CR1_LPDS, Regulator);
+
+  /* Select the domain Power Down DeepSleep */
+  if (Domain == PWR_D1_DOMAIN)
+  {
+#if defined (DUAL_CORE)
+    /* Check current core */
+    if (HAL_GetCurrentCPUID () != CM7_CPUID)
+    {
+      /*
+         When the domain selected and the cortex-mx don't match, entering stop
+         mode will not be performed
+      */
+      return;
+    }
+#endif /* defined (DUAL_CORE) */
+
+    /* Keep DSTOP mode when D1/CD domain enters Deepsleep */
+    CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D1);
+
+    /* Set SLEEPDEEP bit of Cortex System Control Register */
+    SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+
+    /* Ensure that all instructions are done before entering STOP mode */
+    __DSB ();
+    __ISB ();
+
+    /* Select Stop mode entry */
+    if (STOPEntry == PWR_STOPENTRY_WFI)
+    {
+      /* Request Wait For Interrupt */
+      __WFI ();
+    }
+    else
+    {
+      /* Request Wait For Event */
+      __WFE ();
+    }
+
+    /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */
+    CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+  }
+#if defined (PWR_CPUCR_PDDS_D2)
+  else if (Domain == PWR_D2_DOMAIN)
+  {
+    /* Keep DSTOP mode when D2 domain enters Deepsleep */
+    CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2);
+
+#if defined (DUAL_CORE)
+    /* Check current core */
+    if (HAL_GetCurrentCPUID () != CM4_CPUID)
+    {
+      /*
+         When the domain selected and the cortex-mx don't match, entering stop
+         mode will not be performed
+      */
+      return;
+    }
+
+    /* Set SLEEPDEEP bit of Cortex System Control Register */
+    SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+
+    /* Ensure that all instructions are done before entering STOP mode */
+    __DSB ();
+    __ISB ();
+
+    /* Select Stop mode entry */
+    if (STOPEntry == PWR_STOPENTRY_WFI)
+    {
+      /* Request Wait For Interrupt */
+      __WFI ();
+    }
+    else
+    {
+      /* Request Wait For Event */
+      __WFE ();
+    }
+
+    /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */
+    CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+#endif /* defined (DUAL_CORE) */
+  }
+#endif /* defined (PWR_CPUCR_PDDS_D2) */
+  else
+  {
+    /* Keep DSTOP mode when D3/SRD domain enters Deepsleep */
+    CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D3);
+  }
+}
+
+/**
+  * @brief Clear pending event.
+  * @note   This API clears the pending event in order to enter a given CPU
+  *         to CSLEEP or CSTOP. It should be called just before APIs performing
+  *         enter low power mode using Wait For Event request.
+  * @retval None.
+  */
+void HAL_PWREx_ClearPendingEvent (void)
+{
+#if defined (DUAL_CORE)
+  /* Check the current Core */
+  if (HAL_GetCurrentCPUID () == CM7_CPUID)
+  {
+    __WFE ();
+  }
+  else
+  {
+    __SEV ();
+    __WFE ();
+  }
+#else
+  __WFE ();
+#endif /* defined (DUAL_CORE) */
+}
+
+/**
+  * @brief Enter a Domain to DSTANDBY mode.
+  * @note   This API gives flexibility to manage independently each domain
+  *         STANDBY mode. For dual core lines, this API should be executed with
+  *         the corresponding Cortex-Mx to enter domain to DSTANDBY mode. When
+  *         it is executed by all available Cortex-Mx, the system enter STANDBY
+  *         mode.
+  *         For single core lines, calling this API with D1/SRD the selected
+  *         domain will enter the whole system in STOP if PWR_CPUCR_PDDS_D3 = 0
+  *         and enter the whole system in STANDBY if PWR_CPUCR_PDDS_D3 = 1.
+  * @note   The DStandby mode is entered when all PDDS_Dn bits in PWR_CPUCR for
+  *         the Dn domain select Standby mode. When the system enters Standby
+  *         mode, the voltage regulator is disabled.
+  * @note   When D2 or D3 domain is in DStandby mode and the CPU sets the
+  *         domain PDDS_Dn bit to select Stop mode, the domain remains in
+  *         DStandby mode. The domain will only exit DStandby when the CPU
+  *         allocates a peripheral in the domain.
+  * @note   The system D3/SRD domain enters Standby mode only when the D1 and D2
+  *         domain are in DStandby.
+  * @note   Before entering DSTANDBY mode it is recommended to call
+  *         SCB_CleanDCache function in order to clean the D-Cache and guarantee
+  *         the data integrity for the SRAM memories.
+  * @param  Domain : Specifies the Domain to enter to STANDBY mode.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_D1_DOMAIN: Enter D1/CD Domain to DSTANDBY mode.
+  *            @arg PWR_D2_DOMAIN: Enter D2 Domain to DSTANDBY mode.
+  *            @arg PWR_D3_DOMAIN: Enter D3/SRD Domain to DSTANDBY mode.
+  * @retval None
+  */
+void HAL_PWREx_EnterSTANDBYMode (uint32_t Domain)
+{
+  /* Check the parameters */
+  assert_param (IS_PWR_DOMAIN (Domain));
+
+  /* Select the domain Power Down DeepSleep */
+  if (Domain == PWR_D1_DOMAIN)
+  {
+#if defined (DUAL_CORE)
+    /* Check current core */
+    if (HAL_GetCurrentCPUID () != CM7_CPUID)
+    {
+      /*
+         When the domain selected and the cortex-mx don't match, entering
+         standby mode will not be performed
+      */
+      return;
+    }
+#endif /* defined (DUAL_CORE) */
+
+    /* Allow DSTANDBY mode when D1/CD domain enters Deepsleep */
+    SET_BIT (PWR-> CPUCR, PWR_CPUCR_PDDS_D1);
+
+#if defined (DUAL_CORE)
+    /* Allow DSTANDBY mode when D1/CD domain enters Deepsleep */
+    SET_BIT (PWR-> CPU2CR, PWR_CPU2CR_PDDS_D1);
+#endif /*DUAL_CORE*/
+
+    /* Set SLEEPDEEP bit of Cortex System Control Register */
+    SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+
+    /* This option is used to ensure that store operations are completed */
+#if defined (__CC_ARM)
+    __force_stores ();
+#endif /* defined (__CC_ARM) */
+
+    /* Request Wait For Interrupt */
+    __WFI ();
+  }
+#if defined (PWR_CPUCR_PDDS_D2)
+  else if (Domain == PWR_D2_DOMAIN)
+  {
+    /* Allow DSTANDBY mode when D2 domain enters Deepsleep */
+    SET_BIT (PWR-> CPUCR, PWR_CPUCR_PDDS_D2);
+
+#if defined (DUAL_CORE)
+    /* Check current core */
+    if (HAL_GetCurrentCPUID () != CM4_CPUID)
+    {
+      /*
+         When the domain selected and the cortex-mx don't match, entering
+         standby mode will not be performed
+      */
+      return;
+    }
+
+    /* Allow DSTANDBY mode when D2 domain enters Deepsleep */
+    SET_BIT (PWR-> CPU2CR, PWR_CPU2CR_PDDS_D2);
+
+    /* Set SLEEPDEEP bit of Cortex System Control Register */
+    SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+
+    /* This option is used to ensure that store operations are completed */
+#if defined (__CC_ARM)
+    __force_stores ();
+#endif /* defined (__CC_ARM) */
+
+    /* Request Wait For Interrupt */
+    __WFI ();
+#endif /* defined (DUAL_CORE) */
+  }
+#endif /* defined (PWR_CPUCR_PDDS_D2) */
+  else
+  {
+    /* Allow DSTANDBY mode when D3/SRD domain enters Deepsleep */
+    SET_BIT (PWR-> CPUCR, PWR_CPUCR_PDDS_D3);
+
+#if defined (DUAL_CORE)
+    /* Allow DSTANDBY mode when D3/SRD domain enters Deepsleep */
+    SET_BIT (PWR-> CPU2CR, PWR_CPU2CR_PDDS_D3);
+#endif /* defined (DUAL_CORE) */
+  }
+}
+
+/**
+  * @brief Configure the D3/SRD Domain state when the System in low power mode.
+  * @param  D3State : Specifies the D3/SRD state.
+  *          This parameter can be one of the following values :
+  *            @arg PWR_D3_DOMAIN_STOP : D3/SRD domain will follow the most deep
+  *                                      CPU sub-system low power mode.
+  *            @arg PWR_D3_DOMAIN_RUN : D3/SRD domain will stay in RUN mode
+  *                                     regardless of the CPU sub-system low
+  *                                     power mode.
+  * @retval None
+  */
+void HAL_PWREx_ConfigD3Domain (uint32_t D3State)
+{
+  /* Check the parameter */
+  assert_param (IS_D3_STATE (D3State));
+
+  /* Keep D3/SRD in run mode */
+  MODIFY_REG (PWR->CPUCR, PWR_CPUCR_RUN_D3, D3State);
+}
+
+#if defined (DUAL_CORE)
+/**
+  * @brief Clear HOLD2F, HOLD1F, STOPF, SBF, SBF_D1, and SBF_D2 flags for a
+  *        given domain.
+  * @param  DomainFlags : Specifies the Domain flags to be cleared.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_D1_DOMAIN_FLAGS : Clear D1 Domain flags.
+  *            @arg PWR_D2_DOMAIN_FLAGS : Clear D2 Domain flags.
+  *            @arg PWR_ALL_DOMAIN_FLAGS : Clear D1 and D2 Domain flags.
+  * @retval None.
+  */
+void HAL_PWREx_ClearDomainFlags (uint32_t DomainFlags)
+{
+  /* Check the parameter */
+  assert_param (IS_PWR_DOMAIN_FLAG (DomainFlags));
+
+  /* D1 CPU flags */
+  if (DomainFlags == PWR_D1_DOMAIN_FLAGS)
+  {
+    /* Clear D1 domain flags (HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2) */
+    SET_BIT (PWR->CPUCR, PWR_CPUCR_CSSF);
+  }
+  /* D2 CPU flags */
+  else if (DomainFlags == PWR_D2_DOMAIN_FLAGS)
+  {
+    /* Clear D2 domain flags (HOLD1F, STOPF, SBF, SBF_D1, and SBF_D2) */
+    SET_BIT (PWR->CPU2CR, PWR_CPU2CR_CSSF);
+  }
+  else
+  {
+    /* Clear D1 domain flags (HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2) */
+    SET_BIT (PWR->CPUCR, PWR_CPUCR_CSSF);
+    /* Clear D2 domain flags (HOLD1F, STOPF, SBF, SBF_D1, and SBF_D2) */
+    SET_BIT (PWR->CPU2CR, PWR_CPU2CR_CSSF);
+  }
+}
+
+/**
+  * @brief Hold the CPU and their domain peripherals when exiting STOP mode.
+  * @param  CPU : Specifies the core to be held.
+  *         This parameter can be one of the following values:
+  *             @arg PWR_CORE_CPU1: Hold CPU1 and set CPU2 as master.
+  *             @arg PWR_CORE_CPU2: Hold CPU2 and set CPU1 as master.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PWREx_HoldCore (uint32_t CPU)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param (IS_PWR_CORE (CPU));
+
+  /* Check CPU index */
+  if (CPU == PWR_CORE_CPU2)
+  {
+    /* If CPU1 is not held */
+    if ((PWR->CPU2CR & PWR_CPU2CR_HOLD1) != PWR_CPU2CR_HOLD1)
+    {
+      /* Set HOLD2 bit */
+      SET_BIT (PWR->CPUCR, PWR_CPUCR_HOLD2);
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* If CPU2 is not held */
+    if ((PWR->CPUCR & PWR_CPUCR_HOLD2) != PWR_CPUCR_HOLD2)
+    {
+      /* Set HOLD1 bit */
+      SET_BIT (PWR->CPU2CR, PWR_CPU2CR_HOLD1);
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief Release the CPU and their domain peripherals after a wake-up from
+  *        STOP mode.
+  * @param  CPU: Specifies the core to be released.
+  *         This parameter can be one of the following values:
+  *             @arg  PWR_CORE_CPU1: Release the CPU1 and their domain
+  *                   peripherals from holding.
+  *             @arg  PWR_CORE_CPU2: Release the CPU2 and their domain
+  *                   peripherals from holding.
+  * @retval None
+  */
+void HAL_PWREx_ReleaseCore (uint32_t CPU)
+{
+  /* Check the parameters */
+  assert_param (IS_PWR_CORE (CPU));
+
+  /* Check CPU index */
+  if (CPU == PWR_CORE_CPU2)
+  {
+    /* Reset HOLD2 bit */
+    CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_HOLD2);
+  }
+  else
+  {
+    /* Reset HOLD1 bit */
+    CLEAR_BIT (PWR->CPU2CR, PWR_CPU2CR_HOLD1);
+  }
+}
+#endif /* defined (DUAL_CORE) */
+
+
+/**
+  * @brief Enable the Flash Power Down in Stop mode.
+  * @note   When Flash Power Down is enabled  the Flash memory enters low-power
+  *         mode when D1/SRD domain is in DStop mode. This feature allows to
+  *         obtain the best trade-off between low-power consumption and restart
+  *         time when exiting from DStop mode.
+  * @retval None.
+  */
+void HAL_PWREx_EnableFlashPowerDown (void)
+{
+  /* Enable the Flash Power Down */
+  SET_BIT (PWR->CR1, PWR_CR1_FLPS);
+}
+
+/**
+  * @brief Disable the Flash Power Down in Stop mode.
+  * @note   When Flash Power Down is disabled  the Flash memory is kept on
+  *         normal mode when D1/SRD domain is in DStop mode. This feature allows
+  *         to obtain the best trade-off between low-power consumption and
+  *         restart time when exiting from DStop mode.
+  * @retval None.
+  */
+void HAL_PWREx_DisableFlashPowerDown (void)
+{
+  /* Disable the Flash Power Down */
+  CLEAR_BIT (PWR->CR1, PWR_CR1_FLPS);
+}
+
+#if defined (PWR_CR1_SRDRAMSO)
+/**
+  * @brief Enable memory block shut-off in DStop or DStop2 modes
+  * @note   In DStop or DStop2 mode, the content of the memory blocks is
+  *         maintained. Further power optimization can be obtained by switching
+  *         off some memory blocks. This optimization implies loss of the memory
+  *         content. The user can select which memory is discarded during STOP
+  *         mode by means of xxSO bits.
+  * @param  MemoryBlock : Specifies the memory block to shut-off during DStop or
+  *                       DStop2 mode.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_SRD_AHB_MEMORY_BLOCK : SmartRun domain AHB memory.
+  *            @arg PWR_USB_FDCAN_MEMORY_BLOCK : High-speed interfaces USB and
+  *                                              FDCAN memories.
+  *            @arg PWR_GFXMMU_JPEG_MEMORY_BLOCK : GFXMMU and JPEG memories.
+  *            @arg PWR_TCM_ECM_MEMORY_BLOCK : Instruction TCM and ETM memories.
+  *            @arg PWR_RAM1_AHB_MEMORY_BLOCK : AHB RAM1 memory.
+  *            @arg PWR_RAM2_AHB_MEMORY_BLOCK : AHB RAM2 memory.
+  *            @arg PWR_RAM1_AXI_MEMORY_BLOCK : AXI RAM1 memory.
+  *            @arg PWR_RAM2_AXI_MEMORY_BLOCK : AXI RAM2 memory.
+  *            @arg PWR_RAM3_AXI_MEMORY_BLOCK : AXI RAM3 memory.
+  * @retval None.
+  */
+void HAL_PWREx_EnableMemoryShutOff (uint32_t MemoryBlock)
+{
+  /* Check the parameter */
+  assert_param (IS_PWR_MEMORY_BLOCK (MemoryBlock));
+
+  /* Enable memory block shut-off */
+  SET_BIT (PWR->CR1, MemoryBlock);
+}
+
+/**
+  * @brief Disable memory block shut-off in DStop or DStop2 modes
+  * @param  MemoryBlock : Specifies the memory block to keep content during
+  *                       DStop or DStop2 mode.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_SRD_AHB_MEMORY_BLOCK : SmartRun domain AHB memory.
+  *            @arg PWR_USB_FDCAN_MEMORY_BLOCK : High-speed interfaces USB and
+  *                                              FDCAN memories.
+  *            @arg PWR_GFXMMU_JPEG_MEMORY_BLOCK : GFXMMU and JPEG memories.
+  *            @arg PWR_TCM_ECM_MEMORY_BLOCK : Instruction TCM and ETM memories.
+  *            @arg PWR_RAM1_AHB_MEMORY_BLOCK : AHB RAM1 memory.
+  *            @arg PWR_RAM2_AHB_MEMORY_BLOCK : AHB RAM2 memory.
+  *            @arg PWR_RAM1_AXI_MEMORY_BLOCK : AXI RAM1 memory.
+  *            @arg PWR_RAM2_AXI_MEMORY_BLOCK : AXI RAM2 memory.
+  *            @arg PWR_RAM3_AXI_MEMORY_BLOCK : AXI RAM3 memory.
+  * @retval None.
+  */
+void HAL_PWREx_DisableMemoryShutOff (uint32_t MemoryBlock)
+{
+  /* Check the parameter */
+  assert_param (IS_PWR_MEMORY_BLOCK (MemoryBlock));
+
+  /* Disable memory block shut-off */
+  CLEAR_BIT (PWR->CR1, MemoryBlock);
+}
+#endif /* defined (PWR_CR1_SRDRAMSO) */
+
+/**
+  * @brief Enable the Wake-up PINx functionality.
+  * @param  sPinParams : Pointer to a PWREx_WakeupPinTypeDef structure that
+  *                      contains the configuration information for the wake-up
+  *                      Pin.
+  * @note   For dual core devices, please ensure to configure the EXTI lines for
+  *         the different Cortex-Mx. All combination are allowed: wake up only
+  *         Cortex-M7, wake up only Cortex-M4 and wake up Cortex-M7 and
+  *         Cortex-M4.
+  * @retval None.
+  */
+void HAL_PWREx_EnableWakeUpPin (PWREx_WakeupPinTypeDef *sPinParams)
+{
+  uint32_t pinConfig;
+  uint32_t regMask;
+  const uint32_t pullMask = PWR_WKUPEPR_WKUPPUPD1;
+
+  /* Check the parameters */
+  assert_param (IS_PWR_WAKEUP_PIN (sPinParams->WakeUpPin));
+  assert_param (IS_PWR_WAKEUP_PIN_POLARITY (sPinParams->PinPolarity));
+  assert_param (IS_PWR_WAKEUP_PIN_PULL (sPinParams->PinPull));
+
+  pinConfig = sPinParams->WakeUpPin | \
+              (sPinParams->PinPolarity << ((POSITION_VAL(sPinParams->WakeUpPin) + PWR_WKUPEPR_WKUPP1_Pos) & 0x1FU)) | \
+              (sPinParams->PinPull << (((POSITION_VAL(sPinParams->WakeUpPin) * PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET) + PWR_WKUPEPR_WKUPPUPD1_Pos) & 0x1FU));
+
+  regMask   = sPinParams->WakeUpPin | \
+              (PWR_WKUPEPR_WKUPP1 << (POSITION_VAL(sPinParams->WakeUpPin) & 0x1FU)) | \
+              (pullMask << ((POSITION_VAL(sPinParams->WakeUpPin) * PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET) & 0x1FU));
+
+  /* Enable and Specify the Wake-Up pin polarity and the pull configuration
+     for the event detection (rising or falling edge) */
+  MODIFY_REG (PWR->WKUPEPR, regMask, pinConfig);
+#ifndef DUAL_CORE
+  /* Configure the Wakeup Pin EXTI Line */
+  MODIFY_REG (EXTI->IMR2, PWR_EXTI_WAKEUP_PINS_MASK, (sPinParams->WakeUpPin << EXTI_IMR2_IM55_Pos));
+#endif /* !DUAL_CORE */
+}
+
+/**
+  * @brief Disable the Wake-up PINx functionality.
+  * @param  WakeUpPin : Specifies the Wake-Up pin to be disabled.
+  *          This parameter can be one of the following values:
+  *           @arg PWR_WAKEUP_PIN1 : Disable PA0  wake-up PIN.
+  *           @arg PWR_WAKEUP_PIN2 : Disable PA2  wake-up PIN.
+  *           @arg PWR_WAKEUP_PIN3 : Disable PI8  wake-up PIN.
+  *           @arg PWR_WAKEUP_PIN4 : Disable PC13 wake-up PIN.
+  *           @arg PWR_WAKEUP_PIN5 : Disable PI11 wake-up PIN.
+  *           @arg PWR_WAKEUP_PIN6 : Disable PC1  wake-up PIN.
+  * @retval None
+  */
+void HAL_PWREx_DisableWakeUpPin (uint32_t WakeUpPin)
+{
+  /* Check the parameter */
+  assert_param (IS_PWR_WAKEUP_PIN (WakeUpPin));
+
+  /* Disable the WakeUpPin */
+  CLEAR_BIT (PWR->WKUPEPR, WakeUpPin);
+}
+
+/**
+  * @brief Get the Wake-Up Pin pending flags.
+  * @param  WakeUpFlag : Specifies the Wake-Up PIN flag to be checked.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_WAKEUP_FLAG1    : Get wakeup event received from PA0.
+  *            @arg PWR_WAKEUP_FLAG2    : Get wakeup event received from PA2.
+  *            @arg PWR_WAKEUP_FLAG3    : Get wakeup event received from PI8.
+  *            @arg PWR_WAKEUP_FLAG4    : Get wakeup event received from PC13.
+  *            @arg PWR_WAKEUP_FLAG5    : Get wakeup event received from PI11.
+  *            @arg PWR_WAKEUP_FLAG6    : Get wakeup event received from PC1.
+  *            @arg PWR_WAKEUP_FLAG_ALL : Get Wakeup event received from all
+  *                                      wake up pins.
+  * @retval The Wake-Up pin flag.
+  */
+uint32_t HAL_PWREx_GetWakeupFlag (uint32_t WakeUpFlag)
+{
+  /* Check the parameters */
+  assert_param (IS_PWR_WAKEUP_FLAG (WakeUpFlag));
+
+  /* Return the wake up pin flag */
+  return (PWR->WKUPFR & WakeUpFlag);
+}
+
+/**
+  * @brief Clear the Wake-Up pin pending flag.
+  * @param  WakeUpFlag: Specifies the Wake-Up PIN flag to clear.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_WAKEUP_FLAG1 : Clear the wakeup event received from PA0.
+  *            @arg PWR_WAKEUP_FLAG2 : Clear the wakeup event received from PA2.
+  *            @arg PWR_WAKEUP_FLAG3 : Clear the wakeup event received from PI8.
+  *            @arg PWR_WAKEUP_FLAG4 : Clear the wakeup event received from PC13.
+  *            @arg PWR_WAKEUP_FLAG5 : Clear the wakeup event received from PI11.
+  *            @arg PWR_WAKEUP_FLAG6 : Clear the wakeup event received from PC1.
+  *            @arg PWR_WAKEUP_FLAG_ALL : Clear the wakeup events received from
+  *                                      all wake up pins.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag (uint32_t WakeUpFlag)
+{
+  /* Check the parameter */
+  assert_param (IS_PWR_WAKEUP_FLAG (WakeUpFlag));
+
+  /* Clear the wake up event received from wake up pin x */
+  SET_BIT (PWR->WKUPCR, WakeUpFlag);
+
+  /* Check if the wake up event is well cleared */
+  if ((PWR->WKUPFR & WakeUpFlag) != 0U)
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief This function handles the PWR WAKEUP PIN interrupt request.
+  * @note   This API should be called under the WAKEUP_PIN_IRQHandler().
+  * @retval None.
+  */
+void HAL_PWREx_WAKEUP_PIN_IRQHandler (void)
+{
+  /* Wakeup pin EXTI line interrupt detected */
+  if (READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF1) != 0U)
+  {
+    /* Clear PWR WKUPF1 flag */
+    __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP1);
+
+    /* PWR WKUP1 interrupt user callback */
+    HAL_PWREx_WKUP1_Callback ();
+  }
+  else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF2) != 0U)
+  {
+    /* Clear PWR WKUPF2 flag */
+    __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP2);
+
+    /* PWR WKUP2 interrupt user callback */
+    HAL_PWREx_WKUP2_Callback ();
+  }
+  else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF3) != 0U)
+  {
+    /* Clear PWR WKUPF3 flag */
+    __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP3);
+
+    /* PWR WKUP3 interrupt user callback */
+    HAL_PWREx_WKUP3_Callback ();
+  }
+  else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF4) != 0U)
+  {
+    /* Clear PWR WKUPF4 flag */
+    __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP4);
+
+    /* PWR WKUP4 interrupt user callback */
+    HAL_PWREx_WKUP4_Callback ();
+  }
+  else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF5) != 0U)
+  {
+    /* Clear PWR WKUPF5 flag */
+    __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP5);
+
+    /* PWR WKUP5 interrupt user callback */
+    HAL_PWREx_WKUP5_Callback ();
+  }
+  else
+  {
+    /* Clear PWR WKUPF6 flag */
+    __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP6);
+
+    /* PWR WKUP6 interrupt user callback */
+    HAL_PWREx_WKUP6_Callback ();
+  }
+}
+
+/**
+  * @brief PWR WKUP1 interrupt callback.
+  * @retval None.
+  */
+__weak void HAL_PWREx_WKUP1_Callback (void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PWREx_WKUP1Callback can be implemented in the user file
+  */
+}
+
+/**
+  * @brief PWR WKUP2 interrupt callback.
+  * @retval None.
+  */
+__weak void HAL_PWREx_WKUP2_Callback (void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PWREx_WKUP2Callback can be implemented in the user file
+  */
+}
+
+/**
+  * @brief PWR WKUP3 interrupt callback.
+  * @retval None.
+  */
+__weak void HAL_PWREx_WKUP3_Callback (void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PWREx_WKUP3Callback can be implemented in the user file
+  */
+}
+
+/**
+  * @brief PWR WKUP4 interrupt callback.
+  * @retval None.
+  */
+__weak void HAL_PWREx_WKUP4_Callback (void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PWREx_WKUP4Callback can be implemented in the user file
+  */
+}
+
+/**
+  * @brief PWR WKUP5 interrupt callback.
+  * @retval None.
+  */
+__weak void HAL_PWREx_WKUP5_Callback (void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PWREx_WKUP5Callback can be implemented in the user file
+  */
+}
+
+/**
+  * @brief PWR WKUP6 interrupt callback.
+  * @retval None.
+  */
+__weak void HAL_PWREx_WKUP6_Callback (void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PWREx_WKUP6Callback can be implemented in the user file
+  */
+}
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_Exported_Functions_Group3 Peripherals control functions
+  * @brief    Peripherals control functions
+  *
+@verbatim
+ ===============================================================================
+                 ##### Peripherals control functions #####
+ ===============================================================================
+
+    *** Main and Backup Regulators configuration ***
+    ================================================
+    [..]
+      (+) The backup domain includes 4 Kbytes of backup SRAM accessible only
+          from the CPU, and addressed in 32-bit, 16-bit or 8-bit mode. Its
+          content is retained even in Standby or VBAT mode when the low power
+          backup regulator is enabled. It can be considered as an internal
+          EEPROM when VBAT is always present. You can use the
+          HAL_PWREx_EnableBkUpReg() function to enable the low power backup
+          regulator.
+      (+) When the backup domain is supplied by VDD (analog switch connected to
+          VDD) the backup SRAM is powered from VDD which replaces the VBAT power
+          supply to save battery life.
+      (+) The backup SRAM is not mass erased by a tamper event. It is read
+          protected to prevent confidential data, such as cryptographic private
+          key, from being accessed. The backup SRAM can be erased only through
+          the Flash interface when a protection level change from level 1 to
+          level 0 is requested.
+      -@- Refer to the description of Read protection (RDP) in the Flash
+          programming manual.
+      (+) The main internal regulator can be configured to have a tradeoff
+          between performance and power consumption when the device does not
+          operate at the maximum frequency. This is done through
+          HAL_PWREx_ControlVoltageScaling(VOS) function which configure the VOS
+          bit in PWR_D3CR register.
+      (+) The main internal regulator can be configured to operate in Low Power
+          mode when the system enters STOP mode to further reduce power
+          consumption.
+          This is done through HAL_PWREx_ControlStopModeVoltageScaling(SVOS)
+          function which configure the SVOS bit in PWR_CR1 register.
+          The selected SVOS4 and SVOS5 levels add an additional startup delay
+          when exiting from system Stop mode.
+    -@- Refer to the product datasheets for more details.
+
+    *** USB Regulator configuration ***
+    ===================================
+    [..]
+      (+) The USB transceivers are supplied from a dedicated VDD33USB supply
+          that can be provided either by the integrated USB regulator, or by an
+          external USB supply.
+      (+) The USB regulator is enabled by HAL_PWREx_EnableUSBReg() function, the
+          VDD33USB is then provided from the USB regulator.
+      (+) When the USB regulator is enabled, the VDD33USB supply level detector
+          shall be enabled through  HAL_PWREx_EnableUSBVoltageDetector()
+          function.
+      (+) The USB regulator is disabled through HAL_PWREx_DisableUSBReg()
+          function and VDD33USB can be provided from an external supply. In this
+          case VDD33USB and VDD50USB shall be connected together.
+
+    *** VBAT battery charging ***
+    =============================
+    [..]
+      (+) When VDD is present, the external battery connected to VBAT can be
+          charged through an internal resistance. VBAT charging can be performed
+          either through a 5 KOhm resistor or through a 1.5 KOhm resistor.
+      (+) VBAT charging is enabled by HAL_PWREx_EnableBatteryCharging
+          (ResistorValue) function with:
+       (++) ResistorValue:
+        (+++) PWR_BATTERY_CHARGING_RESISTOR_5: 5 KOhm resistor.
+        (+++) PWR_BATTERY_CHARGING_RESISTOR_1_5: 1.5 KOhm resistor.
+      (+) VBAT charging is disabled by HAL_PWREx_DisableBatteryCharging()
+          function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Enable the Backup Regulator.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg (void)
+{
+  uint32_t tickstart;
+
+  /* Enable the Backup regulator */
+  SET_BIT (PWR->CR2, PWR_CR2_BREN);
+
+  /* Get tick */
+  tickstart = HAL_GetTick ();
+
+  /* Wait till Backup regulator ready flag is set */
+  while (__HAL_PWR_GET_FLAG (PWR_FLAG_BRR) == 0U)
+  {
+    if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Disable the Backup Regulator.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg (void)
+{
+  uint32_t tickstart;
+
+  /* Disable the Backup regulator */
+  CLEAR_BIT (PWR->CR2, PWR_CR2_BREN);
+
+  /* Get tick */
+  tickstart = HAL_GetTick ();
+
+  /* Wait till Backup regulator ready flag is reset */
+  while (__HAL_PWR_GET_FLAG (PWR_FLAG_BRR) != 0U)
+  {
+    if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Enable the USB Regulator.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_PWREx_EnableUSBReg (void)
+{
+  uint32_t tickstart;
+
+  /* Enable the USB regulator */
+  SET_BIT (PWR->CR3, PWR_CR3_USBREGEN);
+
+  /* Get tick */
+  tickstart = HAL_GetTick ();
+
+  /* Wait till the USB regulator ready flag is set */
+  while (__HAL_PWR_GET_FLAG (PWR_FLAG_USB33RDY) == 0U)
+  {
+    if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Disable the USB Regulator.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_PWREx_DisableUSBReg (void)
+{
+  uint32_t tickstart;
+
+  /* Disable the USB regulator */
+  CLEAR_BIT (PWR->CR3, PWR_CR3_USBREGEN);
+
+  /* Get tick */
+  tickstart = HAL_GetTick ();
+
+  /* Wait till the USB regulator ready flag is reset */
+  while(__HAL_PWR_GET_FLAG (PWR_FLAG_USB33RDY) != 0U)
+  {
+    if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Enable the USB voltage level detector.
+  * @retval None.
+  */
+void HAL_PWREx_EnableUSBVoltageDetector (void)
+{
+  /* Enable the USB voltage detector */
+  SET_BIT (PWR->CR3, PWR_CR3_USB33DEN);
+}
+
+/**
+  * @brief Disable the USB voltage level detector.
+  * @retval None.
+  */
+void HAL_PWREx_DisableUSBVoltageDetector (void)
+{
+  /* Disable the USB voltage detector */
+  CLEAR_BIT (PWR->CR3, PWR_CR3_USB33DEN);
+}
+
+/**
+  * @brief Enable the Battery charging.
+  * @note   When VDD is present, charge the external battery through an internal
+  *         resistor.
+  * @param  ResistorValue : Specifies the charging resistor.
+  *          This parameter can be one of the following values :
+  *            @arg PWR_BATTERY_CHARGING_RESISTOR_5 : 5 KOhm resistor.
+  *            @arg PWR_BATTERY_CHARGING_RESISTOR_1_5 : 1.5 KOhm resistor.
+  * @retval None.
+  */
+void HAL_PWREx_EnableBatteryCharging (uint32_t ResistorValue)
+{
+  /* Check the parameter */
+  assert_param (IS_PWR_BATTERY_RESISTOR_SELECT (ResistorValue));
+
+  /* Specify the charging resistor */
+  MODIFY_REG (PWR->CR3, PWR_CR3_VBRS, ResistorValue);
+
+  /* Enable the Battery charging */
+  SET_BIT (PWR->CR3, PWR_CR3_VBE);
+}
+
+/**
+  * @brief Disable the Battery charging.
+  * @retval None.
+  */
+void HAL_PWREx_DisableBatteryCharging (void)
+{
+  /* Disable the Battery charging */
+  CLEAR_BIT (PWR->CR3, PWR_CR3_VBE);
+}
+
+#if defined (PWR_CR1_BOOSTE)
+/**
+  * @brief Enable the booster to guarantee the analog switch AC performance when
+  *        the VDD supply voltage is below 2V7.
+  * @note   The VDD supply voltage can be monitored through the PVD and the PLS
+  *         field bits.
+  * @retval None.
+  */
+void HAL_PWREx_EnableAnalogBooster (void)
+{
+  /* Enable the Analog voltage */
+  SET_BIT (PWR->CR1, PWR_CR1_AVD_READY);
+
+  /* Enable VDDA booster */
+  SET_BIT (PWR->CR1, PWR_CR1_BOOSTE);
+}
+
+/**
+  * @brief Disable the analog booster.
+  * @retval None.
+  */
+void HAL_PWREx_DisableAnalogBooster (void)
+{
+  /* Disable VDDA booster */
+  CLEAR_BIT (PWR->CR1, PWR_CR1_BOOSTE);
+
+  /* Disable the Analog voltage */
+  CLEAR_BIT (PWR->CR1, PWR_CR1_AVD_READY);
+}
+#endif /* defined (PWR_CR1_BOOSTE) */
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_Exported_Functions_Group4 Power Monitoring functions
+  * @brief    Power Monitoring functions
+  *
+@verbatim
+ ===============================================================================
+                 ##### Power Monitoring functions #####
+ ===============================================================================
+
+    *** VBAT and Temperature supervision ***
+    ========================================
+    [..]
+      (+) The VBAT battery voltage supply can be monitored by comparing it with
+          two threshold levels: VBAThigh and VBATlow. VBATH flag and VBATL flags
+          in the PWR control register 2 (PWR_CR2), indicate if VBAT is higher or
+          lower than the threshold.
+      (+) The temperature can be monitored by comparing it with two threshold
+          levels, TEMPhigh and TEMPlow. TEMPH and TEMPL flags, in the PWR
+          control register 2 (PWR_CR2), indicate whether the device temperature
+          is higher or lower than the threshold.
+      (+) The VBAT and the temperature monitoring is enabled by
+          HAL_PWREx_EnableMonitoring() function and disabled by
+          HAL_PWREx_DisableMonitoring() function.
+      (+) The HAL_PWREx_GetVBATLevel() function returns the VBAT level which can
+          be : PWR_VBAT_BELOW_LOW_THRESHOLD or PWR_VBAT_ABOVE_HIGH_THRESHOLD or
+          PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD.
+      (+) The HAL_PWREx_GetTemperatureLevel() function returns the Temperature
+          level which can be :
+          PWR_TEMP_BELOW_LOW_THRESHOLD or PWR_TEMP_ABOVE_HIGH_THRESHOLD or
+          PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD.
+
+    *** AVD configuration ***
+    =========================
+    [..]
+      (+) The AVD is used to monitor the VDDA power supply by comparing it to a
+          threshold selected by the AVD Level (ALS[3:0] bits in the PWR_CR1
+          register).
+      (+) A AVDO flag is available to indicate if VDDA is higher or lower
+          than the AVD threshold. This event is internally connected to the EXTI
+          line 16 to generate an interrupt if enabled.
+          It is configurable through __HAL_PWR_AVD_EXTI_ENABLE_IT() macro.
+      (+) The AVD is stopped in System Standby mode.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Enable the VBAT and temperature monitoring.
+  * @retval HAL status.
+  */
+void HAL_PWREx_EnableMonitoring (void)
+{
+  /* Enable the VBAT and Temperature monitoring */
+  SET_BIT (PWR->CR2, PWR_CR2_MONEN);
+}
+
+/**
+  * @brief Disable the VBAT and temperature monitoring.
+  * @retval HAL status.
+  */
+void HAL_PWREx_DisableMonitoring (void)
+{
+  /* Disable the VBAT and Temperature monitoring */
+  CLEAR_BIT (PWR->CR2, PWR_CR2_MONEN);
+}
+
+/**
+  * @brief Indicate whether the junction temperature is between, above or below
+  *        the thresholds.
+  * @retval Temperature level.
+  */
+uint32_t HAL_PWREx_GetTemperatureLevel (void)
+{
+  uint32_t tempLevel, regValue;
+
+  /* Read the temperature flags */
+  regValue = READ_BIT (PWR->CR2, (PWR_CR2_TEMPH | PWR_CR2_TEMPL));
+
+  /* Check if the temperature is below the threshold */
+  if (regValue == PWR_CR2_TEMPL)
+  {
+    tempLevel = PWR_TEMP_BELOW_LOW_THRESHOLD;
+  }
+  /* Check if the temperature is above the threshold */
+  else if (regValue == PWR_CR2_TEMPH)
+  {
+    tempLevel = PWR_TEMP_ABOVE_HIGH_THRESHOLD;
+  }
+  /* The temperature is between the thresholds */
+  else
+  {
+    tempLevel = PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD;
+  }
+
+  return tempLevel;
+}
+
+/**
+  * @brief Indicate whether the Battery voltage level is between, above or below
+  *        the thresholds.
+  * @retval VBAT level.
+  */
+uint32_t HAL_PWREx_GetVBATLevel (void)
+{
+  uint32_t VBATLevel, regValue;
+
+  /* Read the VBAT flags */
+  regValue = READ_BIT (PWR->CR2, (PWR_CR2_VBATH | PWR_CR2_VBATL));
+
+  /* Check if the VBAT is below the threshold */
+  if (regValue == PWR_CR2_VBATL)
+  {
+    VBATLevel = PWR_VBAT_BELOW_LOW_THRESHOLD;
+  }
+  /* Check if the VBAT is above the threshold */
+  else if (regValue == PWR_CR2_VBATH)
+  {
+    VBATLevel = PWR_VBAT_ABOVE_HIGH_THRESHOLD;
+  }
+  /* The VBAT is between the thresholds */
+  else
+  {
+    VBATLevel = PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD;
+  }
+
+  return VBATLevel;
+}
+
+#if defined (PWR_CSR1_MMCVDO)
+/**
+  * @brief Get the VDDMMC voltage level.
+  * @retval The VDDMMC voltage level.
+  */
+PWREx_MMC_VoltageLevel HAL_PWREx_GetMMCVoltage (void)
+{
+  PWREx_MMC_VoltageLevel mmc_voltage;
+
+  /* Check voltage detector output on VDDMMC value */
+  if ((PWR->CSR1 & PWR_CSR1_MMCVDO_Msk) == 0U)
+  {
+    mmc_voltage = PWR_MMC_VOLTAGE_BELOW_1V2;
+  }
+  else
+  {
+    mmc_voltage = PWR_MMC_VOLTAGE_EQUAL_ABOVE_1V2;
+  }
+
+  return mmc_voltage;
+}
+#endif /* defined (PWR_CSR1_MMCVDO) */
+
+/**
+  * @brief  Configure the event mode and the voltage threshold detected by the
+  *         Analog Voltage Detector (AVD).
+  * @param  sConfigAVD : Pointer to an PWREx_AVDTypeDef structure that contains
+  *                      the configuration information for the AVD.
+  * @note   Refer to the electrical characteristics of your device datasheet for
+  *         more details about the voltage threshold corresponding to each
+  *         detection level.
+  * @note   For dual core devices, please ensure to configure the EXTI lines for
+  *         the different Cortex-Mx through PWR_Exported_Macro provided by this
+  *         driver. All combination are allowed: wake up only Cortex-M7, wake up
+  *         only Cortex-M4 and wake up Cortex-M7 and Cortex-M4.
+  * @retval None.
+  */
+void HAL_PWREx_ConfigAVD (PWREx_AVDTypeDef *sConfigAVD)
+{
+  /* Check the parameters */
+  assert_param (IS_PWR_AVD_LEVEL (sConfigAVD->AVDLevel));
+  assert_param (IS_PWR_AVD_MODE (sConfigAVD->Mode));
+
+  /* Set the ALS[18:17] bits according to AVDLevel value */
+  MODIFY_REG (PWR->CR1, PWR_CR1_ALS, sConfigAVD->AVDLevel);
+
+  /* Clear any previous config */
+#if !defined (DUAL_CORE)
+  __HAL_PWR_AVD_EXTI_DISABLE_EVENT ();
+  __HAL_PWR_AVD_EXTI_DISABLE_IT ();
+#endif /* !defined (DUAL_CORE) */
+
+  __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE ();
+  __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE ();
+
+#if !defined (DUAL_CORE)
+  /* Configure the interrupt mode */
+  if ((sConfigAVD->Mode & AVD_MODE_IT) == AVD_MODE_IT)
+  {
+    __HAL_PWR_AVD_EXTI_ENABLE_IT ();
+  }
+
+  /* Configure the event mode */
+  if ((sConfigAVD->Mode & AVD_MODE_EVT) == AVD_MODE_EVT)
+  {
+    __HAL_PWR_AVD_EXTI_ENABLE_EVENT ();
+  }
+#endif /* !defined (DUAL_CORE) */
+
+  /* Rising edge configuration */
+  if ((sConfigAVD->Mode & AVD_RISING_EDGE) == AVD_RISING_EDGE)
+  {
+    __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE ();
+  }
+
+  /* Falling edge configuration */
+  if ((sConfigAVD->Mode & AVD_FALLING_EDGE) == AVD_FALLING_EDGE)
+  {
+    __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE ();
+  }
+}
+
+/**
+  * @brief Enable the Analog Voltage Detector (AVD).
+  * @retval None.
+  */
+void HAL_PWREx_EnableAVD (void)
+{
+  /* Enable the Analog Voltage Detector */
+  SET_BIT (PWR->CR1, PWR_CR1_AVDEN);
+}
+
+/**
+  * @brief Disable the Analog Voltage Detector(AVD).
+  * @retval None.
+  */
+void HAL_PWREx_DisableAVD (void)
+{
+  /* Disable the Analog Voltage Detector */
+  CLEAR_BIT (PWR->CR1, PWR_CR1_AVDEN);
+}
+
+/**
+  * @brief  This function handles the PWR PVD/AVD interrupt request.
+  * @note   This API should be called under the PVD_AVD_IRQHandler().
+  * @retval None
+  */
+void HAL_PWREx_PVD_AVD_IRQHandler (void)
+{
+  /* Check if the Programmable Voltage Detector is enabled (PVD) */
+  if(READ_BIT (PWR->CR1, PWR_CR1_PVDEN) != 0U)
+  {
+#if defined (DUAL_CORE)
+    if (HAL_GetCurrentCPUID () == CM7_CPUID)
+#endif /* defined (DUAL_CORE) */
+    {
+      /* Check PWR D1/CD EXTI flag */
+      if(__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U)
+      {
+        /* PWR PVD interrupt user callback */
+        HAL_PWR_PVDCallback ();
+
+        /* Clear PWR EXTI D1/CD pending bit */
+        __HAL_PWR_PVD_EXTI_CLEAR_FLAG ();
+      }
+    }
+#if defined (DUAL_CORE)
+    else
+    {
+      /* Check PWR EXTI D2 flag */
+      if (__HAL_PWR_PVD_EXTID2_GET_FLAG () != 0U)
+      {
+        /* PWR PVD interrupt user callback */
+        HAL_PWR_PVDCallback ();
+
+        /* Clear PWR EXTI D2 pending bit */
+        __HAL_PWR_PVD_EXTID2_CLEAR_FLAG();
+      }
+    }
+#endif /* defined (DUAL_CORE) */
+  }
+
+  /* Check if the Analog Voltage Detector is enabled (AVD) */
+  if (READ_BIT (PWR->CR1, PWR_CR1_AVDEN) != 0U)
+  {
+#if defined (DUAL_CORE)
+    if (HAL_GetCurrentCPUID () == CM7_CPUID)
+#endif /* defined (DUAL_CORE) */
+    {
+      /* Check PWR EXTI D1/CD flag */
+      if (__HAL_PWR_AVD_EXTI_GET_FLAG () != 0U)
+      {
+        /* PWR AVD interrupt user callback */
+        HAL_PWREx_AVDCallback ();
+
+        /* Clear PWR EXTI D1/CD pending bit */
+        __HAL_PWR_AVD_EXTI_CLEAR_FLAG ();
+      }
+    }
+#if defined (DUAL_CORE)
+    else
+    {
+      /* Check PWR EXTI D2 flag */
+      if (__HAL_PWR_AVD_EXTID2_GET_FLAG () != 0U)
+      {
+        /* PWR AVD interrupt user callback */
+        HAL_PWREx_AVDCallback ();
+
+        /* Clear PWR EXTI D2 pending bit */
+        __HAL_PWR_AVD_EXTID2_CLEAR_FLAG ();
+      }
+    }
+#endif /* defined (DUAL_CORE) */
+  }
+}
+
+/**
+  * @brief PWR AVD interrupt callback.
+  * @retval None.
+  */
+__weak void HAL_PWREx_AVDCallback (void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PWR_AVDCallback can be implemented in the user file
+  */
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c
new file mode 100644
index 00000000..7d73fa57
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c
@@ -0,0 +1,1775 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_rcc.c
+  * @author  MCD Application Team
+  * @brief   RCC HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Reset and Clock Control (RCC) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions
+  *
+  @verbatim
+  ==============================================================================
+                      ##### RCC specific features #####
+  ==============================================================================
+    [..]
+      After reset the device is running from Internal High Speed oscillator
+      (HSI 64MHz) with Flash 0 wait state,and all peripherals are off except
+      internal SRAM, Flash, JTAG and PWR
+      (+) There is no pre-scaler on High speed (AHB) and Low speed (APB) buses;
+          all peripherals mapped on these buses are running at HSI speed.
+      (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
+      (+) All GPIOs are in analogue mode , except the JTAG pins which
+          are assigned to be used for debug purpose.
+
+    [..]
+      Once the device started from reset, the user application has to:
+      (+) Configure the clock source to be used to drive the System clock
+          (if the application needs higher frequency/performance)
+      (+) Configure the System clock frequency and Flash settings
+      (+) Configure the AHB and APB buses pre-scalers
+      (+) Enable the clock for the peripheral(s) to be used
+      (+) Configure the clock kernel source(s) for peripherals which clocks are not
+          derived from the System clock through :RCC_D1CCIPR,RCC_D2CCIP1R,RCC_D2CCIP2R
+          and RCC_D3CCIPR registers
+
+                      ##### RCC Limitations #####
+  ==============================================================================
+    [..]
+      A delay between an RCC peripheral clock enable and the effective peripheral
+      enabling should be taken into account in order to manage the peripheral read/write
+      from/to registers.
+      (+) This delay depends on the peripheral mapping.
+      (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
+          after the clock enable bit is set on the hardware register
+      (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
+          after the clock enable bit is set on the hardware register
+
+    [..]
+      Implemented Workaround:
+      (+) For AHB & APB peripherals, a dummy read to the peripheral register has been
+          inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
+
+  @endverbatim
+ ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup RCC  RCC
+  * @brief RCC HAL module driver
+  * @{
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup RCC_Private_Macros RCC Private Macros
+  * @{
+  */
+#define MCO1_CLK_ENABLE()     __HAL_RCC_GPIOA_CLK_ENABLE()
+#define MCO1_GPIO_PORT        GPIOA
+#define MCO1_PIN              GPIO_PIN_8
+
+#define MCO2_CLK_ENABLE()      __HAL_RCC_GPIOC_CLK_ENABLE()
+#define MCO2_GPIO_PORT         GPIOC
+#define MCO2_PIN               GPIO_PIN_9
+
+/**
+  * @}
+  */
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup RCC_Private_Variables RCC Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Functions RCC Exported Functions
+  * @{
+  */
+
+/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+           ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]
+      This section provides functions allowing to configure the internal/external oscillators
+      (HSE, HSI, LSE,CSI, LSI,HSI48, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB3, AHB1
+       AHB2,AHB4,APB3, APB1L, APB1H, APB2, and APB4).
+
+    [..] Internal/external clock and PLL configuration
+         (#) HSI (high-speed internal), 64 MHz factory-trimmed RC used directly or through
+             the PLL as System clock source.
+         (#) CSI is a low-power RC oscillator which can be used directly as system clock, peripheral
+             clock, or PLL input.But even with frequency calibration, is less accurate than an
+             external crystal oscillator or ceramic resonator.
+         (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
+             clock source.
+
+         (#) HSE (high-speed external), 4 to 48 MHz crystal oscillator used directly or
+             through the PLL as System clock source. Can be used also as RTC clock source.
+
+         (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
+
+         (#) PLL , The RCC features three independent PLLs (clocked by HSI , HSE or CSI),
+             featuring three different output clocks and able  to work either in integer or Fractional mode.
+           (++) A main PLL, PLL1, which is generally used to provide clocks to the CPU
+                and to some peripherals.
+           (++) Two dedicated PLLs, PLL2 and PLL3, which are used to generate the kernel clock for peripherals.
+
+
+         (#) CSS (Clock security system), once enabled and if a HSE clock failure occurs
+            (HSE used directly or through PLL as System clock source), the System clock
+             is automatically switched to HSI and an interrupt is generated if enabled.
+             The interrupt is linked to the Cortex-M NMI (Non-Mask-able Interrupt)
+             exception vector.
+
+         (#) MCO1 (micro controller clock output), used to output HSI, LSE, HSE, PLL1(PLL1_Q)
+             or HSI48 clock (through a configurable pre-scaler) on PA8 pin.
+
+         (#) MCO2 (micro controller clock output), used to output HSE, PLL2(PLL2_P), SYSCLK,
+             LSI, CSI, or PLL1(PLL1_P) clock (through a configurable pre-scaler) on PC9 pin.
+
+    [..] System, AHB and APB buses clocks configuration
+         (#) Several clock sources can be used to drive the System clock (SYSCLK): CSI,HSI,
+             HSE and PLL.
+             The AHB clock (HCLK) is derived from System core clock through configurable
+             pre-scaler and used to clock the CPU, memory and peripherals mapped
+             on AHB and APB bus of the 3 Domains (D1, D2, D3)* through configurable pre-scalers
+             and used to clock the peripherals mapped on these buses. You can use
+             "HAL_RCC_GetSysClockFreq()" function to retrieve system clock frequency.
+
+         -@- All the peripheral clocks are derived from the System clock (SYSCLK) except those
+             with dual clock domain where kernel source clock could be selected through
+             RCC_D1CCIPR,RCC_D2CCIP1R,RCC_D2CCIP2R and RCC_D3CCIPR registers.
+
+     (*) : 2 Domains (CD and SRD) for stm32h7a3xx and stm32h7b3xx family lines.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Resets the RCC clock configuration to the default reset state.
+  * @note   The default reset state of the clock configuration is given below:
+  *            - HSI ON and used as system clock source
+  *            - HSE, PLL1, PLL2 and PLL3 OFF
+  *            - AHB, APB Bus pre-scaler set to 1.
+  *            - CSS, MCO1 and MCO2 OFF
+  *            - All interrupts disabled
+  * @note   This function doesn't modify the configuration of the
+  *            - Peripheral clocks
+  *            - LSI, LSE and RTC clocks
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCC_DeInit(void)
+{
+  uint32_t tickstart;
+
+        /* Increasing the CPU frequency */
+  if(FLASH_LATENCY_DEFAULT  > __HAL_FLASH_GET_LATENCY())
+  {
+    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+    __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT);
+
+    /* Check that the new number of wait states is taken into account to access the Flash
+    memory by reading the FLASH_ACR register */
+    if(__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT)
+    {
+      return HAL_ERROR;
+    }
+
+  }
+
+
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Set HSION bit */
+  SET_BIT(RCC->CR, RCC_CR_HSION);
+
+  /* Wait till HSI is ready */
+  while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Set HSITRIM[6:0] bits to the reset value */
+  SET_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM_6);
+
+  /* Reset CFGR register */
+  CLEAR_REG(RCC->CFGR);
+
+  /* Update the SystemCoreClock and SystemD2Clock global variables */
+  SystemCoreClock = HSI_VALUE;
+  SystemD2Clock = HSI_VALUE;
+
+  /* Adapt Systick interrupt period */
+  if(HAL_InitTick(uwTickPrio) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait till clock switch is ready */
+  while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Reset CSION, CSIKERON, HSEON, HSI48ON, HSECSSON, HSIDIV bits */
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSIKERON| RCC_CR_HSIDIV| RCC_CR_HSIDIVF| RCC_CR_CSION | RCC_CR_CSIKERON  \
+  | RCC_CR_HSI48ON | RCC_CR_CSSHSEON);
+
+  /* Wait till HSE is disabled */
+  while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Clear PLLON bit */
+  CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON);
+
+  /* Wait till PLL is disabled */
+  while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) != 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Reset PLL2ON bit */
+  CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
+
+  /* Wait till PLL2 is disabled */
+  while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Reset PLL3 bit */
+  CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
+
+  /* Wait till PLL3 is disabled */
+  while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+#if defined(RCC_D1CFGR_HPRE)
+  /* Reset D1CFGR register */
+  CLEAR_REG(RCC->D1CFGR);
+
+  /* Reset D2CFGR register */
+  CLEAR_REG(RCC->D2CFGR);
+
+  /* Reset D3CFGR register */
+  CLEAR_REG(RCC->D3CFGR);
+#else
+  /* Reset CDCFGR1 register */
+  CLEAR_REG(RCC->CDCFGR1);
+
+  /* Reset CDCFGR2 register */
+  CLEAR_REG(RCC->CDCFGR2);
+
+  /* Reset SRDCFGR register */
+  CLEAR_REG(RCC->SRDCFGR);
+#endif
+
+  /* Reset PLLCKSELR register to default value */
+  RCC->PLLCKSELR= RCC_PLLCKSELR_DIVM1_5|RCC_PLLCKSELR_DIVM2_5|RCC_PLLCKSELR_DIVM3_5;
+
+  /* Reset PLLCFGR register to default value */
+  WRITE_REG(RCC->PLLCFGR, 0x01FF0000U);
+
+  /* Reset PLL1DIVR register to default value */
+  WRITE_REG(RCC->PLL1DIVR,0x01010280U);
+
+  /* Reset PLL1FRACR register */
+  CLEAR_REG(RCC->PLL1FRACR);
+
+  /* Reset PLL2DIVR register to default value */
+  WRITE_REG(RCC->PLL2DIVR,0x01010280U);
+
+  /* Reset PLL2FRACR register */
+  CLEAR_REG(RCC->PLL2FRACR);
+
+  /* Reset PLL3DIVR register to default value */
+  WRITE_REG(RCC->PLL3DIVR,0x01010280U);
+
+  /* Reset PLL3FRACR register */
+  CLEAR_REG(RCC->PLL3FRACR);
+
+  /* Reset HSEBYP bit */
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
+
+  /* Disable all interrupts */
+  CLEAR_REG(RCC->CIER);
+
+  /* Clear all interrupts flags */
+  WRITE_REG(RCC->CICR,0xFFFFFFFFU);
+
+  /* Reset all RSR flags */
+  SET_BIT(RCC->RSR, RCC_RSR_RMVF);
+
+      /* Decreasing the number of wait states because of lower CPU frequency */
+  if(FLASH_LATENCY_DEFAULT  < __HAL_FLASH_GET_LATENCY())
+  {
+    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+    __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT);
+
+    /* Check that the new number of wait states is taken into account to access the Flash
+    memory by reading the FLASH_ACR register */
+    if(__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT)
+    {
+      return HAL_ERROR;
+    }
+
+}
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the RCC Oscillators according to the specified parameters in the
+  *         RCC_OscInitTypeDef.
+  * @param  RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
+  *         contains the configuration information for the RCC Oscillators.
+  * @note   The PLL is not disabled when used as system clock.
+  * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
+  *         supported by this function. User should request a transition to LSE Off
+  *         first and then LSE On or LSE Bypass.
+  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
+  *         supported by this function. User should request a transition to HSE Off
+  *         first and then HSE On or HSE Bypass.
+  * @retval HAL status
+  */
+__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
+{
+  uint32_t tickstart;
+  uint32_t temp1_pllckcfg, temp2_pllckcfg;
+
+    /* Check Null pointer */
+  if(RCC_OscInitStruct == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
+  /*------------------------------- HSE Configuration ------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
+
+    const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
+    const uint32_t temp_pllckselr = RCC->PLLCKSELR;
+    /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
+    if((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE)))
+    {
+      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
+      {
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Set the new HSE configuration ---------------------------------------*/
+      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
+
+      /* Check the HSE State */
+      if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
+      {
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSE is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
+        {
+          if((uint32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+      else
+      {
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSE is disabled */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
+        {
+          if((uint32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+  }
+  /*----------------------------- HSI Configuration --------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
+    assert_param(IS_RCC_HSICALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
+
+    /* When the HSI is used as system clock it will not be disabled */
+    const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
+    const uint32_t temp_pllckselr = RCC->PLLCKSELR;
+    if((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI)))
+    {
+      /* When HSI is used as system clock it will not be disabled */
+      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
+      {
+        return HAL_ERROR;
+      }
+      /* Otherwise, just the calibration is allowed */
+      else
+      {
+        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+      }
+    }
+
+    else
+    {
+      /* Check the HSI State */
+      if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
+      {
+     /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */
+        __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSI is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
+        {
+          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+
+        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+      }
+      else
+      {
+        /* Disable the Internal High Speed oscillator (HSI). */
+        __HAL_RCC_HSI_DISABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSI is disabled */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
+        {
+          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+  }
+  /*----------------------------- CSI Configuration --------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState));
+    assert_param(IS_RCC_CSICALIBRATION_VALUE(RCC_OscInitStruct->CSICalibrationValue));
+
+    /* When the CSI is used as system clock it will not disabled */
+    const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
+    const uint32_t temp_pllckselr = RCC->PLLCKSELR;
+    if((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI)))
+    {
+      /* When CSI is used as system clock it will not disabled */
+      if((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON))
+      {
+        return HAL_ERROR;
+      }
+      /* Otherwise, just the calibration is allowed */
+      else
+      {
+        /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/
+        __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
+      }
+    }
+    else
+    {
+      /* Check the CSI State */
+      if((RCC_OscInitStruct->CSIState)!= RCC_CSI_OFF)
+      {
+        /* Enable the Internal High Speed oscillator (CSI). */
+        __HAL_RCC_CSI_ENABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till CSI is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)
+        {
+          if((HAL_GetTick() - tickstart ) > CSI_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+
+        /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/
+        __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
+      }
+      else
+      {
+        /* Disable the Internal High Speed oscillator (CSI). */
+        __HAL_RCC_CSI_DISABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till CSI is disabled */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U)
+        {
+          if((HAL_GetTick() - tickstart ) > CSI_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+  }
+  /*------------------------------ LSI Configuration -------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
+
+    /* Check the LSI State */
+    if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
+    {
+      /* Enable the Internal Low Speed oscillator (LSI). */
+      __HAL_RCC_LSI_ENABLE();
+
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSI is ready */
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
+      {
+        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    else
+    {
+      /* Disable the Internal Low Speed oscillator (LSI). */
+      __HAL_RCC_LSI_DISABLE();
+
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSI is ready */
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
+      {
+        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /*------------------------------ HSI48 Configuration -------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
+
+    /* Check the HSI48 State */
+    if((RCC_OscInitStruct->HSI48State)!= RCC_HSI48_OFF)
+    {
+      /* Enable the Internal Low Speed oscillator (HSI48). */
+      __HAL_RCC_HSI48_ENABLE();
+
+      /* Get time-out */
+      tickstart = HAL_GetTick();
+
+      /* Wait till HSI48 is ready */
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U)
+      {
+        if((HAL_GetTick() - tickstart ) > HSI48_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    else
+    {
+      /* Disable the Internal Low Speed oscillator (HSI48). */
+      __HAL_RCC_HSI48_DISABLE();
+
+      /* Get time-out */
+      tickstart = HAL_GetTick();
+
+      /* Wait till HSI48 is ready */
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U)
+      {
+        if((HAL_GetTick() - tickstart ) > HSI48_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  /*------------------------------ LSE Configuration -------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
+
+    /* Enable write access to Backup domain */
+    PWR->CR1 |= PWR_CR1_DBP;
+
+    /* Wait for Backup domain Write protection disable */
+    tickstart = HAL_GetTick();
+
+    while((PWR->CR1 & PWR_CR1_DBP) == 0U)
+    {
+      if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Set the new LSE configuration -----------------------------------------*/
+    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
+    /* Check the LSE State */
+    if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
+    {
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSE is ready */
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
+      {
+        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    else
+    {
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSE is disabled */
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
+      {
+        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  /*-------------------------------- PLL Configuration -----------------------*/
+  /* Check the parameters */
+  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
+  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
+  {
+    /* Check if the PLL is used as system clock or not */
+    if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1)
+    {
+      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
+      {
+        /* Check the parameters */
+        assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
+        assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
+        assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
+        assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
+        assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
+        assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
+        assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN));
+
+        /* Disable the main PLL. */
+        __HAL_RCC_PLL_DISABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till PLL is disabled */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
+        {
+          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+
+        /* Configure the main PLL clock source, multiplication and division factors. */
+        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
+                             RCC_OscInitStruct->PLL.PLLM,
+                             RCC_OscInitStruct->PLL.PLLN,
+                             RCC_OscInitStruct->PLL.PLLP,
+                             RCC_OscInitStruct->PLL.PLLQ,
+                             RCC_OscInitStruct->PLL.PLLR);
+
+         /* Disable PLLFRACN . */
+         __HAL_RCC_PLLFRACN_DISABLE();
+
+         /* Configure PLL PLL1FRACN */
+         __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN);
+
+        /* Select PLL1 input reference frequency range: VCI */
+        __HAL_RCC_PLL_VCIRANGE(RCC_OscInitStruct->PLL.PLLRGE) ;
+
+        /* Select PLL1 output frequency range : VCO */
+        __HAL_RCC_PLL_VCORANGE(RCC_OscInitStruct->PLL.PLLVCOSEL) ;
+
+        /* Enable PLL System Clock output. */
+         __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
+
+        /* Enable PLL1Q Clock output. */
+         __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+        /* Enable PLL1R  Clock output. */
+         __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR);
+
+        /* Enable PLL1FRACN . */
+         __HAL_RCC_PLLFRACN_ENABLE();
+
+        /* Enable the main PLL. */
+        __HAL_RCC_PLL_ENABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till PLL is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
+        {
+          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+      else
+      {
+        /* Disable the main PLL. */
+        __HAL_RCC_PLL_DISABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till PLL is disabled */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
+        {
+          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+    else
+    {
+      /* Do not return HAL_ERROR if request repeats the current configuration */
+      temp1_pllckcfg = RCC->PLLCKSELR;
+      temp2_pllckcfg = RCC->PLL1DIVR;
+      if(((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
+	 (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
+         ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) ||
+         (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) ||
+         ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) ||
+         ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) ||
+         ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U)))
+      {
+        return HAL_ERROR;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CPU, AHB and APB buses clocks according to the specified
+  *         parameters in the RCC_ClkInitStruct.
+  * @param  RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
+  *         contains the configuration information for the RCC peripheral.
+  * @param  FLatency: FLASH Latency, this parameter depend on device selected
+  *
+  * @note   The SystemCoreClock CMSIS variable is used to store System Core Clock Frequency
+  *         and updated by HAL_InitTick() function called within this function
+  *
+  * @note   The HSI is used (enabled by hardware) as system clock source after
+  *         start-up from Reset, wake-up from STOP and STANDBY mode, or in case
+  *         of failure of the HSE used directly or indirectly as system clock
+  *         (if the Clock Security System CSS is enabled).
+  *
+  * @note   A switch from one clock source to another occurs only if the target
+  *         clock source is ready (clock stable after start-up delay or PLL locked).
+  *         If a clock source which is not yet ready is selected, the switch will
+  *         occur when the clock source will be ready.
+  *         You can use HAL_RCC_GetClockConfig() function to know which clock is
+  *         currently used as system clock source.
+  * @note   Depending on the device voltage range, the software has to set correctly
+  *         D1CPRE[3:0] bits to ensure that  Domain1 core clock not exceed the maximum allowed frequency
+  *         (for more details refer to section above "Initialization/de-initialization functions")
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
+{
+  HAL_StatusTypeDef halstatus;
+  uint32_t tickstart;
+  uint32_t common_system_clock;
+
+   /* Check Null pointer */
+  if(RCC_ClkInitStruct == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
+  assert_param(IS_FLASH_LATENCY(FLatency));
+
+  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
+    must be correctly programmed according to the frequency of the CPU clock
+    (HCLK) and the supply voltage of the device. */
+
+  /* Increasing the CPU frequency */
+  if(FLatency > __HAL_FLASH_GET_LATENCY())
+  {
+    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+    __HAL_FLASH_SET_LATENCY(FLatency);
+
+    /* Check that the new number of wait states is taken into account to access the Flash
+    memory by reading the FLASH_ACR register */
+    if(__HAL_FLASH_GET_LATENCY() != FLatency)
+    {
+      return HAL_ERROR;
+    }
+
+  }
+
+  /* Increasing the BUS frequency divider */
+  /*-------------------------- D1PCLK1/CDPCLK1 Configuration ---------------------------*/
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1)
+  {
+#if defined (RCC_D1CFGR_D1PPRE)
+    if((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_D1PPRE))
+    {
+      assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider));
+      MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider);
+    }
+#else
+    if((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE))
+    {
+      assert_param(IS_RCC_CDPCLK1(RCC_ClkInitStruct->APB3CLKDivider));
+      MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, RCC_ClkInitStruct->APB3CLKDivider);
+    }
+#endif
+  }
+
+  /*-------------------------- PCLK1 Configuration ---------------------------*/
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+  {
+#if defined (RCC_D2CFGR_D2PPRE1)
+    if((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1))
+    {
+      assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
+      MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
+    }
+#else
+    if((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1))
+    {
+      assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
+      MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
+  }
+#endif
+    }
+  /*-------------------------- PCLK2 Configuration ---------------------------*/
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+  {
+#if defined(RCC_D2CFGR_D2PPRE2)
+    if((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2))
+    {
+      assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
+      MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
+    }
+#else
+     if((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2))
+    {
+      assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
+      MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
+    }
+#endif
+  }
+
+  /*-------------------------- D3PCLK1 Configuration ---------------------------*/
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1)
+  {
+#if defined(RCC_D3CFGR_D3PPRE)
+    if((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->D3CFGR & RCC_D3CFGR_D3PPRE))
+    {
+      assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider));
+      MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider) );
+    }
+#else
+    if((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE))
+    {
+      assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider));
+      MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, (RCC_ClkInitStruct->APB4CLKDivider) );
+    }
+#endif
+  }
+
+   /*-------------------------- HCLK Configuration --------------------------*/
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+  {
+#if defined (RCC_D1CFGR_HPRE)
+    if((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_HPRE))
+    {
+      /* Set the new HCLK clock divider */
+      assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+      MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+    }
+#else
+        if((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->CDCFGR1 & RCC_CDCFGR1_HPRE))
+    {
+      /* Set the new HCLK clock divider */
+      assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+      MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+    }
+#endif
+  }
+
+    /*------------------------- SYSCLK Configuration -------------------------*/
+    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
+    {
+      assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider));
+      assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
+#if defined(RCC_D1CFGR_D1CPRE)
+      MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider);
+#else
+      MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, RCC_ClkInitStruct->SYSCLKDivider);
+#endif
+      /* HSE is selected as System Clock Source */
+      if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+      {
+        /* Check the HSE ready flag */
+        if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
+        {
+          return HAL_ERROR;
+        }
+      }
+      /* PLL is selected as System Clock Source */
+      else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+      {
+        /* Check the PLL ready flag */
+        if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
+        {
+          return HAL_ERROR;
+        }
+      }
+      /* CSI is selected as System Clock Source */
+      else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI)
+      {
+        /* Check the PLL ready flag */
+        if(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)
+        {
+          return HAL_ERROR;
+        }
+      }
+      /* HSI is selected as System Clock Source */
+      else
+      {
+        /* Check the HSI ready flag */
+        if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
+        {
+          return HAL_ERROR;
+        }
+      }
+      MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
+
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+        while (__HAL_RCC_GET_SYSCLK_SOURCE() !=  (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
+        {
+          if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+
+    }
+
+    /* Decreasing the BUS frequency divider */
+   /*-------------------------- HCLK Configuration --------------------------*/
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+  {
+#if defined(RCC_D1CFGR_HPRE)
+    if((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_HPRE))
+    {
+      /* Set the new HCLK clock divider */
+      assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+      MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+    }
+#else
+    if((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->CDCFGR1 & RCC_CDCFGR1_HPRE))
+    {
+      /* Set the new HCLK clock divider */
+      assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+      MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+    }
+#endif
+  }
+
+  /* Decreasing the number of wait states because of lower CPU frequency */
+  if(FLatency < __HAL_FLASH_GET_LATENCY())
+  {
+    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+    __HAL_FLASH_SET_LATENCY(FLatency);
+
+    /* Check that the new number of wait states is taken into account to access the Flash
+    memory by reading the FLASH_ACR register */
+    if(__HAL_FLASH_GET_LATENCY() != FLatency)
+    {
+      return HAL_ERROR;
+    }
+ }
+
+  /*-------------------------- D1PCLK1/CDPCLK Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1)
+ {
+#if defined(RCC_D1CFGR_D1PPRE)
+   if((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_D1PPRE))
+   {
+     assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider));
+     MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider);
+   }
+#else
+   if((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE))
+   {
+     assert_param(IS_RCC_CDPCLK1(RCC_ClkInitStruct->APB3CLKDivider));
+     MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, RCC_ClkInitStruct->APB3CLKDivider);
+   }
+#endif
+ }
+
+  /*-------------------------- PCLK1 Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ {
+#if defined(RCC_D2CFGR_D2PPRE1)
+   if((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1))
+   {
+     assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
+     MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
+   }
+#else
+   if((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1))
+   {
+     assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
+     MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
+   }
+#endif
+ }
+
+  /*-------------------------- PCLK2 Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+ {
+#if defined (RCC_D2CFGR_D2PPRE2)
+   if((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2))
+   {
+     assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
+     MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
+   }
+#else
+   if((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2))
+   {
+     assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
+     MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
+   }
+#endif
+ }
+
+  /*-------------------------- D3PCLK1/SRDPCLK1 Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1)
+ {
+#if defined(RCC_D3CFGR_D3PPRE)
+   if((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->D3CFGR & RCC_D3CFGR_D3PPRE))
+   {
+     assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider));
+     MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider) );
+   }
+#else
+   if((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE))
+   {
+     assert_param(IS_RCC_SRDPCLK1(RCC_ClkInitStruct->APB4CLKDivider));
+     MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, (RCC_ClkInitStruct->APB4CLKDivider) );
+   }
+#endif
+ }
+
+  /* Update the SystemCoreClock global variable */
+#if defined(RCC_D1CFGR_D1CPRE)
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
+#else
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
+#endif
+
+#if defined(RCC_D1CFGR_HPRE)
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+#else
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+#endif
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  SystemCoreClock = SystemD2Clock;
+#else
+  SystemCoreClock = common_system_clock;
+#endif /* DUAL_CORE && CORE_CM4 */
+
+  /* Configure the source of time base considering new system clocks settings*/
+  halstatus = HAL_InitTick (uwTickPrio);
+
+  return halstatus;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Group2 Peripheral Control functions
+ *  @brief   RCC clocks control functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the RCC Clocks
+    frequencies.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
+  * @note   PA8/PC9 should be configured in alternate function mode.
+  * @param  RCC_MCOx: specifies the output direction for the clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
+  *            @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
+  * @param  RCC_MCOSource: specifies the clock source to output.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_PLL1QCLK:  PLL1Q clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_HSI48: HSI48 (48MHZ) selected as MCO1 source
+  *            @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_PLL2PCLK: PLL2P clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_PLLCLK:  PLL1P clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_CSICLK:  CSI clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_LSICLK:  LSI clock selected as MCO2 source
+  * @param  RCC_MCODiv: specifies the MCOx pre-scaler.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCODIV_1 up to RCC_MCODIV_15  : divider applied to MCOx clock
+  * @retval None
+  */
+void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
+{
+  GPIO_InitTypeDef GPIO_InitStruct;
+  /* Check the parameters */
+  assert_param(IS_RCC_MCO(RCC_MCOx));
+  assert_param(IS_RCC_MCODIV(RCC_MCODiv));
+  /* RCC_MCO1 */
+  if(RCC_MCOx == RCC_MCO1)
+  {
+    assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
+
+    /* MCO1 Clock Enable */
+    MCO1_CLK_ENABLE();
+
+    /* Configure the MCO1 pin in alternate function mode */
+    GPIO_InitStruct.Pin = MCO1_PIN;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
+    HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
+
+    /* Mask MCO1 and MCO1PRE[3:0] bits then Select MCO1 clock source and pre-scaler */
+    MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
+  }
+  else
+  {
+    assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
+
+    /* MCO2 Clock Enable */
+    MCO2_CLK_ENABLE();
+
+    /* Configure the MCO2 pin in alternate function mode */
+    GPIO_InitStruct.Pin = MCO2_PIN;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
+    HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
+
+    /* Mask MCO2 and MCO2PRE[3:0] bits then Select MCO2 clock source and pre-scaler */
+    MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 7U)));
+  }
+}
+
+/**
+  * @brief  Enables the Clock Security System.
+  * @note   If a failure is detected on the HSE oscillator clock, this oscillator
+  *         is automatically disabled and an interrupt is generated to inform the
+  *         software about the failure (Clock Security System Interrupt, CSSI),
+  *         allowing the MCU to perform rescue operations. The CSSI is linked to
+  *         the Cortex-M NMI (Non-Mask-able Interrupt) exception vector.
+  * @retval None
+  */
+void HAL_RCC_EnableCSS(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_CSSHSEON) ;
+}
+
+/**
+  * @brief  Disables the Clock Security System.
+  * @retval None
+  */
+void HAL_RCC_DisableCSS(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_CSSHSEON);
+}
+
+/**
+  * @brief  Returns the SYSCLK frequency
+  *
+  * @note   The system frequency computed by this function is not the real
+  *         frequency in the chip. It is calculated based on the predefined
+  *         constant and the selected clock source:
+  * @note     If SYSCLK source is CSI, function returns values based on CSI_VALUE(*)
+  * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
+  * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
+  * @note     If SYSCLK source is PLL, function returns values based on CSI_VALUE(*),
+  *           HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
+  * @note     (*) CSI_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value
+  *               4 MHz) but the real value may vary depending on the variations
+  *               in voltage and temperature.
+  * @note     (**) HSI_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value
+  *               64 MHz) but the real value may vary depending on the variations
+  *               in voltage and temperature.
+  * @note     (***) HSE_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value
+  *                25 MHz), user has to ensure that HSE_VALUE is same as the real
+  *                frequency of the crystal used. Otherwise, this function may
+  *                have wrong result.
+  *
+  * @note   The result of this function could be not correct when using fractional
+  *         value for HSE crystal.
+  *
+  * @note   This function can be used by the user application to compute the
+  *         baud rate for the communication peripherals or configure other parameters.
+  *
+  * @note   Each time SYSCLK changes, this function must be called to update the
+  *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
+  *
+  *
+  * @retval SYSCLK frequency
+  */
+uint32_t HAL_RCC_GetSysClockFreq(void)
+{
+  uint32_t pllp, pllsource, pllm, pllfracen, hsivalue;
+  float_t fracn1, pllvco;
+  uint32_t sysclockfreq;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+  case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */
+
+   if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+      {
+        sysclockfreq = (uint32_t) (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
+      }
+      else
+      {
+        sysclockfreq = (uint32_t) HSI_VALUE;
+      }
+
+    break;
+
+  case RCC_CFGR_SWS_CSI:  /* CSI used as system clock  source */
+    sysclockfreq = CSI_VALUE;
+    break;
+
+  case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
+    sysclockfreq = HSE_VALUE;
+    break;
+
+  case RCC_CFGR_SWS_PLL1:  /* PLL1 used as system clock  source */
+
+    /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
+    SYSCLK = PLL_VCO / PLLR
+    */
+    pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+    pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4)  ;
+    pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
+    fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
+
+    if (pllm != 0U)
+    {
+      switch (pllsource)
+      {
+      case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
+
+       if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+        {
+          hsivalue= (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
+          pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+        }
+        else
+        {
+          pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+        }
+        break;
+
+      case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
+        pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+        break;
+
+      case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
+        pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+        break;
+
+      default:
+        pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+        break;
+      }
+      pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
+      sysclockfreq =  (uint32_t)(float_t)(pllvco/(float_t)pllp);
+    }
+    else
+    {
+      sysclockfreq = 0U;
+    }
+    break;
+
+  default:
+    sysclockfreq = CSI_VALUE;
+    break;
+  }
+
+  return sysclockfreq;
+}
+
+
+/**
+  * @brief  Returns the HCLK frequency
+  * @note   Each time HCLK changes, this function must be called to update the
+  *         right HCLK value. Otherwise, any configuration based on this function will be incorrect.
+  *
+  * @note   The SystemD2Clock CMSIS variable is used to store System domain2 Clock Frequency
+  *         and updated within this function
+  * @retval HCLK frequency
+  */
+uint32_t HAL_RCC_GetHCLKFreq(void)
+{
+uint32_t common_system_clock;
+
+#if defined(RCC_D1CFGR_D1CPRE)
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
+#else
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU);
+#endif
+
+#if defined(RCC_D1CFGR_HPRE)
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+#else
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+#endif
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  SystemCoreClock = SystemD2Clock;
+#else
+  SystemCoreClock = common_system_clock;
+#endif /* DUAL_CORE && CORE_CM4 */
+
+  return SystemD2Clock;
+}
+
+
+/**
+  * @brief  Returns the PCLK1 frequency
+  * @note   Each time PCLK1 changes, this function must be called to update the
+  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
+  * @retval PCLK1 frequency
+  */
+uint32_t HAL_RCC_GetPCLK1Freq(void)
+{
+#if defined (RCC_D2CFGR_D2PPRE1)
+  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)>> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU));
+#else
+ /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1)>> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU));
+#endif
+}
+
+
+/**
+  * @brief  Returns the PCLK2 frequency
+  * @note   Each time PCLK2 changes, this function must be called to update the
+  *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
+  * @retval PCLK1 frequency
+  */
+uint32_t HAL_RCC_GetPCLK2Freq(void)
+{
+  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
+#if defined(RCC_D2CFGR_D2PPRE2)
+  return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)>> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU));
+#else
+  return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2)>> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU));
+#endif
+}
+
+/**
+  * @brief  Configures the RCC_OscInitStruct according to the internal
+  * RCC configuration registers.
+  * @param  RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
+  * will be configured.
+  * @retval None
+  */
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
+{
+  /* Set all possible values for the Oscillator type parameter ---------------*/
+  RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_CSI | \
+                                      RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI| RCC_OSCILLATORTYPE_HSI48;
+
+  /* Get the HSE configuration -----------------------------------------------*/
+#if defined(RCC_CR_HSEEXT)
+  if((RCC->CR &(RCC_CR_HSEBYP | RCC_CR_HSEEXT)) == RCC_CR_HSEBYP)
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
+  }
+  else if((RCC->CR &(RCC_CR_HSEBYP | RCC_CR_HSEEXT)) == (RCC_CR_HSEBYP | RCC_CR_HSEEXT))
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS_DIGITAL;
+  }
+  else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
+  }
+#else
+  if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
+  }
+  else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
+  }
+#endif /* RCC_CR_HSEEXT */
+
+   /* Get the CSI configuration -----------------------------------------------*/
+  if((RCC->CR &RCC_CR_CSION) == RCC_CR_CSION)
+  {
+    RCC_OscInitStruct->CSIState = RCC_CSI_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->CSIState = RCC_CSI_OFF;
+  }
+
+#if defined(RCC_VER_X)
+  if(HAL_GetREVID() <= REV_ID_Y)
+  {
+    RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk) >> HAL_RCC_REV_Y_CSITRIM_Pos);
+  }
+  else
+  {
+    RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
+  }
+#else
+ RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
+#endif /*RCC_VER_X*/
+
+  /* Get the HSI configuration -----------------------------------------------*/
+  if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
+  {
+    RCC_OscInitStruct->HSIState = RCC_HSI_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
+  }
+
+#if defined(RCC_VER_X)
+  if(HAL_GetREVID() <= REV_ID_Y)
+  {
+    RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk) >> HAL_RCC_REV_Y_HSITRIM_Pos);
+  }
+  else
+  {
+    RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
+  }
+#else
+    RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
+#endif /*RCC_VER_X*/
+
+  /* Get the LSE configuration -----------------------------------------------*/
+#if defined(RCC_BDCR_LSEEXT)
+  if((RCC->BDCR &(RCC_BDCR_LSEBYP|RCC_BDCR_LSEEXT)) == RCC_BDCR_LSEBYP)
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
+  }
+  else if((RCC->BDCR &(RCC_BDCR_LSEBYP|RCC_BDCR_LSEEXT)) == (RCC_BDCR_LSEBYP|RCC_BDCR_LSEEXT))
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS_DIGITAL;
+  }
+  else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
+  }
+#else
+  if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
+  }
+  else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
+  }
+#endif /* RCC_BDCR_LSEEXT */
+
+  /* Get the LSI configuration -----------------------------------------------*/
+  if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
+  {
+    RCC_OscInitStruct->LSIState = RCC_LSI_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
+  }
+
+  /* Get the HSI48 configuration ---------------------------------------------*/
+  if((RCC->CR & RCC_CR_HSI48ON) == RCC_CR_HSI48ON)
+  {
+    RCC_OscInitStruct->HSI48State = RCC_HSI48_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF;
+  }
+
+  /* Get the PLL configuration -----------------------------------------------*/
+  if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
+  {
+    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
+  }
+  RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+  RCC_OscInitStruct->PLL.PLLM = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> RCC_PLLCKSELR_DIVM1_Pos);
+  RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) >> RCC_PLL1DIVR_N1_Pos)+ 1U;
+  RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos)+ 1U;
+  RCC_OscInitStruct->PLL.PLLP = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos)+ 1U;
+  RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos)+ 1U;
+  RCC_OscInitStruct->PLL.PLLRGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL1RGE));
+  RCC_OscInitStruct->PLL.PLLVCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL1VCOSEL) >> RCC_PLLCFGR_PLL1VCOSEL_Pos);
+  RCC_OscInitStruct->PLL.PLLFRACN = (uint32_t)(((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos));
+}
+
+/**
+  * @brief  Configures the RCC_ClkInitStruct according to the internal
+  * RCC configuration registers.
+  * @param  RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
+  * will be configured.
+  * @param  pFLatency: Pointer on the Flash Latency.
+  * @retval None
+  */
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
+{
+  /* Set all possible values for the Clock type parameter --------------------*/
+  RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 |
+                                 RCC_CLOCKTYPE_PCLK2 |  RCC_CLOCKTYPE_D3PCLK1  ;
+
+  /* Get the SYSCLK configuration --------------------------------------------*/
+  RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
+
+#if defined(RCC_D1CFGR_D1CPRE)
+  /* Get the SYSCLK configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1CPRE);
+
+  /* Get the D1HCLK configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_HPRE);
+
+  /* Get the APB3 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1PPRE);
+
+  /* Get the APB1 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1);
+
+  /* Get the APB2 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2);
+
+  /* Get the APB4 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->D3CFGR & RCC_D3CFGR_D3PPRE);
+#else
+  /* Get the SYSCLK configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE);
+
+  /* Get the D1HCLK configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE);
+
+  /* Get the APB3 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE);
+
+  /* Get the APB1 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1);
+
+  /* Get the APB2 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2);
+
+  /* Get the APB4 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE);
+#endif
+
+  /* Get the Flash Wait State (Latency) configuration ------------------------*/
+  *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
+}
+
+/**
+  * @brief This function handles the RCC CSS interrupt request.
+  * @note This API should be called under the NMI_Handler().
+  * @retval None
+  */
+void HAL_RCC_NMI_IRQHandler(void)
+{
+  /* Check RCC CSSF flag  */
+  if(__HAL_RCC_GET_IT(RCC_IT_CSS))
+  {
+    /* RCC Clock Security System interrupt user callback */
+    HAL_RCC_CCSCallback();
+
+    /* Clear RCC CSS pending bit */
+    __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
+  }
+}
+
+/**
+  * @brief  RCC Clock Security System interrupt callback
+  * @retval none
+  */
+__weak void HAL_RCC_CCSCallback(void)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_RCC_CCSCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_RCC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c
new file mode 100644
index 00000000..fa08e692
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c
@@ -0,0 +1,3437 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_rcc_ex.c
+  * @author  MCD Application Team
+  * @brief   Extended RCC HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities RCC extension peripheral:
+  *           + Extended Peripheral Control functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup RCCEx  RCCEx
+  * @brief RCC HAL module driver
+  * @{
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup RCCEx_Private_defines Private Defines
+ * @{
+ */
+#define PLL2_TIMEOUT_VALUE         PLL_TIMEOUT_VALUE    /* 2 ms */
+#define PLL3_TIMEOUT_VALUE         PLL_TIMEOUT_VALUE    /* 2 ms */
+
+#define DIVIDER_P_UPDATE          0U
+#define DIVIDER_Q_UPDATE          1U
+#define DIVIDER_R_UPDATE          2U
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider);
+static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider);
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Functions Exported Functions
+  * @{
+  */
+
+/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
+ *  @brief  Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+                ##### Extended Peripheral Control functions  #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the RCC Clocks
+    frequencies.
+    [..]
+    (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
+        select the RTC clock source; in this case the Backup domain will be reset in
+        order to modify the RTC Clock source, as consequence RTC registers (including
+        the backup registers) and RCC_BDCR register are set to their reset values.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the RCC extended peripherals clocks according to the specified
+  *         parameters in the RCC_PeriphCLKInitTypeDef.
+  * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
+  *         contains the configuration information for the Extended Peripherals
+  *         clocks (SDMMC, CKPER, FMC, QSPI*, OSPI*, DSI, SPI45, SPDIF, DFSDM1, DFSDM2*, FDCAN, SWPMI, SAI23*,SAI2A*, SAI2B*, SAI1, SPI123,
+  *         USART234578, USART16 (USART16910*), RNG, HRTIM1*, I2C123, USB, CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC,
+  *         SAI4A*, SAI4B*, SPI6, RTC).
+  * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
+  *         the RTC clock source; in this case the Backup domain will be reset in
+  *         order to modify the RTC Clock source, as consequence RTC registers (including
+  *         the backup registers) are set to their reset values.
+  *
+  * (*) : Available on some STM32H7 lines only.
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  uint32_t tmpreg;
+  uint32_t tickstart;
+  HAL_StatusTypeDef ret = HAL_OK;      /* Intermediate status */
+  HAL_StatusTypeDef status = HAL_OK;   /* Final status */
+
+  /*---------------------------- SPDIFRX configuration -------------------------------*/
+
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
+  {
+
+    switch(PeriphClkInit->SpdifrxClockSelection)
+    {
+    case RCC_SPDIFRXCLKSOURCE_PLL:      /* PLL is used as clock source for SPDIFRX*/
+      /* Enable PLL1Q Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* SPDIFRX clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPDIFRXCLKSOURCE_PLL2: /* PLL2 is used as clock source for SPDIFRX*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
+
+      /* SPDIFRX clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPDIFRXCLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPDIFRX*/
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
+
+      /* SPDIFRX clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPDIFRXCLKSOURCE_HSI:
+      /* Internal OSC clock is used as source of SPDIFRX clock*/
+      /* SPDIFRX clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SPDIFRX clock*/
+      __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+  /*---------------------------- SAI1 configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
+  {
+    switch(PeriphClkInit->Sai1ClockSelection)
+    {
+    case RCC_SAI1CLKSOURCE_PLL:      /* PLL is used as clock source for SAI1*/
+      /* Enable SAI Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* SAI1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+
+      /* SAI1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI1CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI1*/
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
+
+      /* SAI1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI1CLKSOURCE_PIN:
+      /* External clock is used as source of SAI1 clock*/
+      /* SAI1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI1CLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */
+      /* SAI1 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SAI1 clock*/
+      __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+#if defined(SAI3)
+  /*---------------------------- SAI2/3 configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23)
+  {
+    switch(PeriphClkInit->Sai23ClockSelection)
+    {
+    case RCC_SAI23CLKSOURCE_PLL:      /* PLL is used as clock source for SAI2/3 */
+      /* Enable SAI Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* SAI2/3 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2/3 */
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+
+      /* SAI2/3 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI23CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2/3 */
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
+
+      /* SAI2/3 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI23CLKSOURCE_PIN:
+      /* External clock is used as source of SAI2/3 clock*/
+      /* SAI2/3 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI23CLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of SAI2/3 clock */
+      /* SAI2/3 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SAI2/3 clock*/
+      __HAL_RCC_SAI23_CONFIG(PeriphClkInit->Sai23ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+#endif /* SAI3 */
+
+#if defined(RCC_CDCCIP1R_SAI2ASEL)
+  /*---------------------------- SAI2A configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2A) == RCC_PERIPHCLK_SAI2A)
+  {
+    switch(PeriphClkInit->Sai2AClockSelection)
+    {
+    case RCC_SAI2ACLKSOURCE_PLL:      /* PLL is used as clock source for SAI2A */
+      /* Enable SAI2A Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* SAI2A clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI2ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2A */
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+
+      /* SAI2A clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI2ACLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2A */
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
+
+      /* SAI2A clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI2ACLKSOURCE_PIN:
+      /* External clock is used as source of SAI2A clock*/
+      /* SAI2A clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI2ACLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of SAI2A clock */
+      /* SAI2A clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI2ACLKSOURCE_SPDIF:
+      /* SPDIF clock is used as source of SAI2A clock */
+      /* SAI2A clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SAI2A clock*/
+      __HAL_RCC_SAI2A_CONFIG(PeriphClkInit->Sai2AClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+#endif  /*SAI2A*/
+
+#if defined(RCC_CDCCIP1R_SAI2BSEL)
+
+  /*---------------------------- SAI2B configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2B) == RCC_PERIPHCLK_SAI2B)
+  {
+    switch(PeriphClkInit->Sai2BClockSelection)
+    {
+    case RCC_SAI2BCLKSOURCE_PLL:      /* PLL is used as clock source for SAI2B */
+      /* Enable SAI Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* SAI2B clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI2BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2B */
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+
+      /* SAI2B clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI2BCLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2B */
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
+
+      /* SAI2B clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI2BCLKSOURCE_PIN:
+      /* External clock is used as source of SAI2B clock*/
+      /* SAI2B clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI2BCLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of SAI2B clock */
+      /* SAI2B clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI2BCLKSOURCE_SPDIF:
+      /* SPDIF clock is used as source of SAI2B clock */
+      /* SAI2B clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SAI2B clock*/
+      __HAL_RCC_SAI2B_CONFIG(PeriphClkInit->Sai2BClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+#endif  /*SAI2B*/
+
+#if defined(SAI4)
+  /*---------------------------- SAI4A configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A)
+  {
+    switch(PeriphClkInit->Sai4AClockSelection)
+    {
+    case RCC_SAI4ACLKSOURCE_PLL:      /* PLL is used as clock source for SAI2*/
+      /* Enable SAI Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* SAI1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI4ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+
+      /* SAI2 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI4ACLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2*/
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
+
+      /* SAI1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI4ACLKSOURCE_PIN:
+      /* External clock is used as source of SAI2 clock*/
+      /* SAI2 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI4ACLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */
+      /* SAI1 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SAI4A clock*/
+      __HAL_RCC_SAI4A_CONFIG(PeriphClkInit->Sai4AClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+  /*---------------------------- SAI4B configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B)
+  {
+    switch(PeriphClkInit->Sai4BClockSelection)
+    {
+    case RCC_SAI4BCLKSOURCE_PLL:      /* PLL is used as clock source for SAI2*/
+      /* Enable SAI Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* SAI1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI4BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+
+      /* SAI2 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI4BCLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2*/
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
+
+      /* SAI1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI4BCLKSOURCE_PIN:
+      /* External clock is used as source of SAI2 clock*/
+      /* SAI2 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SAI4BCLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */
+      /* SAI1 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SAI4B clock*/
+      __HAL_RCC_SAI4B_CONFIG(PeriphClkInit->Sai4BClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+#endif  /*SAI4*/
+
+#if defined(QUADSPI)
+  /*---------------------------- QSPI configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI)
+  {
+    switch(PeriphClkInit->QspiClockSelection)
+    {
+    case RCC_QSPICLKSOURCE_PLL:      /* PLL is used as clock source for QSPI*/
+      /* Enable QSPI Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* QSPI clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_QSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for QSPI*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
+
+      /* QSPI clock source configuration done later after clock selection check */
+      break;
+
+
+    case RCC_QSPICLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of QSPI clock */
+      /* QSPI clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_QSPICLKSOURCE_D1HCLK:
+      /* Domain1 HCLK  clock selected as QSPI kernel peripheral clock */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of QSPI clock*/
+      __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+#endif  /*QUADSPI*/
+
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+  /*---------------------------- OCTOSPI configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI)
+  {
+    switch(PeriphClkInit->OspiClockSelection)
+    {
+    case RCC_OSPICLKSOURCE_PLL:      /* PLL is used as clock source for OSPI*/
+      /* Enable OSPI Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* OSPI clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_OSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for OSPI*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
+
+      /* OSPI clock source configuration done later after clock selection check */
+      break;
+
+
+    case RCC_OSPICLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of OSPI clock */
+      /* OSPI clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_OSPICLKSOURCE_HCLK:
+      /* HCLK clock selected as OSPI kernel peripheral clock */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of OSPI clock*/
+      __HAL_RCC_OSPI_CONFIG(PeriphClkInit->OspiClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+#endif  /*OCTOSPI*/
+
+  /*---------------------------- SPI1/2/3 configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123)
+  {
+    switch(PeriphClkInit->Spi123ClockSelection)
+    {
+    case RCC_SPI123CLKSOURCE_PLL:      /* PLL is used as clock source for SPI1/2/3 */
+      /* Enable SPI Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* SPI1/2/3 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI1/2/3 */
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+
+      /* SPI1/2/3 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI123CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPI1/2/3 */
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
+
+      /* SPI1/2/3 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI123CLKSOURCE_PIN:
+      /* External clock is used as source of SPI1/2/3 clock*/
+      /* SPI1/2/3 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI123CLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of SPI1/2/3 clock */
+      /* SPI1/2/3 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SPI1/2/3 clock*/
+      __HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+  /*---------------------------- SPI4/5 configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45)
+  {
+    switch(PeriphClkInit->Spi45ClockSelection)
+    {
+    case RCC_SPI45CLKSOURCE_PCLK1:      /* CD/D2 PCLK1 as clock source for SPI4/5 */
+      /* SPI4/5 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI4/5 */
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
+
+      /* SPI4/5 clock source configuration done later after clock selection check */
+      break;
+    case RCC_SPI45CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPI4/5 */
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
+      /* SPI4/5 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI45CLKSOURCE_HSI:
+      /* HSI oscillator clock is used as source of SPI4/5 clock*/
+      /* SPI4/5 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI45CLKSOURCE_CSI:
+      /*  CSI oscillator clock is used as source of SPI4/5 clock */
+      /* SPI4/5 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI45CLKSOURCE_HSE:
+      /* HSE,  oscillator is used as source of SPI4/5 clock */
+      /* SPI4/5 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SPI4/5 clock*/
+      __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+  /*---------------------------- SPI6 configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6)
+  {
+    switch(PeriphClkInit->Spi6ClockSelection)
+    {
+    case RCC_SPI6CLKSOURCE_PCLK4:      /* SRD/D3 PCLK1 (PCLK4) as clock source for SPI6*/
+      /* SPI6 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI6*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
+
+      /* SPI6 clock source configuration done later after clock selection check */
+      break;
+    case RCC_SPI6CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPI6*/
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
+      /* SPI6 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI6CLKSOURCE_HSI:
+      /* HSI oscillator clock is used as source of SPI6 clock*/
+      /* SPI6 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI6CLKSOURCE_CSI:
+      /*  CSI oscillator clock is used as source of SPI6 clock */
+      /* SPI6 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SPI6CLKSOURCE_HSE:
+      /* HSE,  oscillator is used as source of SPI6 clock */
+      /* SPI6 clock source configuration done later after clock selection check */
+      break;
+#if defined(RCC_SPI6CLKSOURCE_PIN)
+    case RCC_SPI6CLKSOURCE_PIN:
+      /* 2S_CKIN is used as source of SPI6 clock */
+      /* SPI6 clock source configuration done later after clock selection check */
+      break;
+#endif
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SPI6 clock*/
+      __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+#if defined(DSI)
+  /*---------------------------- DSI configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI)
+  {
+    switch(PeriphClkInit->DsiClockSelection)
+    {
+
+    case RCC_DSICLKSOURCE_PLL2: /* PLL2 is used as clock source for DSI*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
+
+      /* DSI clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_DSICLKSOURCE_PHY:
+      /* PHY is used as clock source for DSI*/
+      /* DSI clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of DSI clock*/
+      __HAL_RCC_DSI_CONFIG(PeriphClkInit->DsiClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+#endif /*DSI*/
+
+#if defined(FDCAN1) || defined(FDCAN2)
+  /*---------------------------- FDCAN configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
+  {
+    switch(PeriphClkInit->FdcanClockSelection)
+    {
+    case RCC_FDCANCLKSOURCE_PLL:      /* PLL is used as clock source for FDCAN*/
+      /* Enable FDCAN Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* FDCAN clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
+
+      /* FDCAN clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_FDCANCLKSOURCE_HSE:
+      /* HSE is used as clock source for FDCAN*/
+      /* FDCAN clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of FDCAN clock*/
+      __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+#endif /*FDCAN1 || FDCAN2*/
+
+  /*---------------------------- FMC configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC)
+  {
+    switch(PeriphClkInit->FmcClockSelection)
+    {
+    case RCC_FMCCLKSOURCE_PLL:      /* PLL is used as clock source for FMC*/
+      /* Enable FMC Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* FMC clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_FMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for FMC*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
+
+      /* FMC clock source configuration done later after clock selection check */
+      break;
+
+
+    case RCC_FMCCLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of FMC clock */
+      /* FMC clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_FMCCLKSOURCE_HCLK:
+      /* D1/CD HCLK  clock selected as FMC kernel peripheral clock */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of FMC clock*/
+      __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+  /*---------------------------- RTC configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
+  {
+    /* check for RTC Parameters used to output RTCCLK */
+    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+
+    /* Enable write access to Backup domain */
+    SET_BIT(PWR->CR1, PWR_CR1_DBP);
+
+    /* Wait for Backup domain Write protection disable */
+    tickstart = HAL_GetTick();
+
+    while((PWR->CR1 & PWR_CR1_DBP) == 0U)
+    {
+      if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+      {
+        ret = HAL_TIMEOUT;
+        break;
+      }
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Reset the Backup domain only if the RTC Clock source selection is modified */
+      if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
+      {
+        /* Store the content of BDCR register before the reset of Backup Domain */
+        tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+        /* RTC Clock selection can be changed only if the Backup Domain is reset */
+        __HAL_RCC_BACKUPRESET_FORCE();
+        __HAL_RCC_BACKUPRESET_RELEASE();
+        /* Restore the Content of BDCR register */
+        RCC->BDCR = tmpreg;
+      }
+
+      /* If LSE is selected as RTC clock source (and enabled prior to Backup Domain reset), wait for LSE reactivation */
+      if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
+      {
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till LSE is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
+        {
+          if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
+          {
+            ret = HAL_TIMEOUT;
+            break;
+          }
+        }
+      }
+
+      if(ret == HAL_OK)
+      {
+        __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+      }
+      else
+      {
+        /* set overall return value */
+        status = ret;
+      }
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+
+  /*-------------------------- USART1/6 configuration --------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16)
+  {
+    switch(PeriphClkInit->Usart16ClockSelection)
+    {
+    case RCC_USART16CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for USART1/6 */
+      /* USART1/6 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USART16CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART1/6 */
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
+      /* USART1/6 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USART16CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1/6 */
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
+      /* USART1/6 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USART16CLKSOURCE_HSI:
+      /* HSI oscillator clock is used as source of USART1/6 clock */
+      /* USART1/6 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USART16CLKSOURCE_CSI:
+      /* CSI oscillator clock is used as source of USART1/6 clock */
+      /* USART1/6 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USART16CLKSOURCE_LSE:
+      /* LSE,  oscillator is used as source of USART1/6 clock */
+      /* USART1/6 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of USART1/6 clock */
+      __HAL_RCC_USART16_CONFIG(PeriphClkInit->Usart16ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+  /*-------------------------- USART2/3/4/5/7/8 Configuration --------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578)
+  {
+    switch(PeriphClkInit->Usart234578ClockSelection)
+    {
+    case RCC_USART234578CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for USART2/3/4/5/7/8 */
+      /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USART234578CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART2/3/4/5/7/8 */
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
+      /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USART234578CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART2/3/4/5/7/8 */
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
+      /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USART234578CLKSOURCE_HSI:
+      /* HSI oscillator clock is used as source of USART2/3/4/5/7/8 clock */
+      /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USART234578CLKSOURCE_CSI:
+      /* CSI oscillator clock is used as source of USART2/3/4/5/7/8 clock */
+      /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USART234578CLKSOURCE_LSE:
+      /* LSE,  oscillator is used as source of USART2/3/4/5/7/8 clock */
+      /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of USART2/3/4/5/7/8 clock */
+      __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+  /*-------------------------- LPUART1 Configuration -------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
+  {
+    switch(PeriphClkInit->Lpuart1ClockSelection)
+    {
+    case RCC_LPUART1CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPUART1 */
+      /* LPUART1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPUART1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPUART1 */
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
+      /* LPUART1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPUART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPUART1 */
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
+      /* LPUART1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPUART1CLKSOURCE_HSI:
+      /* HSI oscillator clock is used as source of LPUART1 clock */
+      /* LPUART1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPUART1CLKSOURCE_CSI:
+      /* CSI oscillator clock is used as source of LPUART1 clock */
+      /* LPUART1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPUART1CLKSOURCE_LSE:
+      /* LSE,  oscillator is used as source of LPUART1 clock */
+      /* LPUART1 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of LPUART1 clock */
+      __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+  /*---------------------------- LPTIM1 configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
+  {
+    switch(PeriphClkInit->Lptim1ClockSelection)
+    {
+    case RCC_LPTIM1CLKSOURCE_PCLK1:      /* CD/D2 PCLK1 as clock source for LPTIM1*/
+      /* LPTIM1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM1*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+
+      /* LPTIM1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM1CLKSOURCE_PLL3:  /* PLL3 is used as clock source for LPTIM1*/
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
+
+      /* LPTIM1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM1CLKSOURCE_LSE:
+      /* External low speed OSC clock is used as source of LPTIM1 clock*/
+      /* LPTIM1 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM1CLKSOURCE_LSI:
+      /* Internal  low speed OSC clock is used  as source of LPTIM1 clock*/
+      /* LPTIM1 clock source configuration done later after clock selection check */
+      break;
+    case RCC_LPTIM1CLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of LPTIM1 clock */
+      /* LPTIM1 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of LPTIM1 clock*/
+      __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+  /*---------------------------- LPTIM2 configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2)
+  {
+    switch(PeriphClkInit->Lptim2ClockSelection)
+    {
+    case RCC_LPTIM2CLKSOURCE_PCLK4:      /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM2*/
+      /* LPTIM2 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM2CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM2*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+
+      /* LPTIM2 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM2CLKSOURCE_PLL3:  /* PLL3 is used as clock source for LPTIM2*/
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
+
+      /* LPTIM2 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM2CLKSOURCE_LSE:
+      /* External low speed OSC clock is used as source of LPTIM2 clock*/
+      /* LPTIM2 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM2CLKSOURCE_LSI:
+      /* Internal  low speed OSC clock is used  as source of LPTIM2 clock*/
+      /* LPTIM2 clock source configuration done later after clock selection check */
+      break;
+    case RCC_LPTIM2CLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */
+      /* LPTIM2 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of LPTIM2 clock*/
+      __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+  /*---------------------------- LPTIM345 configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345)
+  {
+    switch(PeriphClkInit->Lptim345ClockSelection)
+    {
+
+    case RCC_LPTIM345CLKSOURCE_PCLK4:      /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM3/4/5 */
+      /* LPTIM3/4/5 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM345CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM3/4/5 */
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+
+      /* LPTIM3/4/5 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM345CLKSOURCE_PLL3:  /* PLL3 is used as clock source for LPTIM3/4/5 */
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
+
+      /* LPTIM3/4/5 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM345CLKSOURCE_LSE:
+      /* External low speed OSC clock is used as source of LPTIM3/4/5 clock */
+      /* LPTIM3/4/5 clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_LPTIM345CLKSOURCE_LSI:
+      /* Internal  low speed OSC clock is used  as source of LPTIM3/4/5 clock */
+      /* LPTIM3/4/5 clock source configuration done later after clock selection check */
+      break;
+    case RCC_LPTIM345CLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of LPTIM3/4/5 clock */
+      /* LPTIM3/4/5 clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of LPTIM3/4/5 clock */
+      __HAL_RCC_LPTIM345_CONFIG(PeriphClkInit->Lptim345ClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+  /*------------------------------ I2C1/2/3 Configuration ------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2C123CLKSOURCE(PeriphClkInit->I2c123ClockSelection));
+
+    if ((PeriphClkInit->I2c123ClockSelection )== RCC_I2C123CLKSOURCE_PLL3 )
+    {
+        if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!= HAL_OK)
+        {
+          status = HAL_ERROR;
+        }
+    }
+
+      __HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection);
+
+  }
+
+  /*------------------------------ I2C4 Configuration ------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
+
+    if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3 )
+    {
+      if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!= HAL_OK)
+      {
+        status = HAL_ERROR;
+      }
+    }
+
+      __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
+
+  }
+
+  /*---------------------------- ADC configuration -------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
+  {
+    switch(PeriphClkInit->AdcClockSelection)
+    {
+
+    case RCC_ADCCLKSOURCE_PLL2: /* PLL2 is used as clock source for ADC*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+
+      /* ADC clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_ADCCLKSOURCE_PLL3:  /* PLL3 is used as clock source for ADC*/
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
+
+      /* ADC clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_ADCCLKSOURCE_CLKP:
+      /* HSI, HSE, or CSI oscillator is used as source of ADC clock */
+      /* ADC clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of ADC clock*/
+      __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+  /*------------------------------ USB Configuration -------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
+  {
+
+    switch(PeriphClkInit->UsbClockSelection)
+    {
+    case RCC_USBCLKSOURCE_PLL:      /* PLL is used as clock source for USB*/
+      /* Enable USB Clock output generated form System USB . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* USB clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USBCLKSOURCE_PLL3: /* PLL3 is used as clock source for USB*/
+
+      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
+
+      /* USB clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_USBCLKSOURCE_HSI48:
+      /* HSI48 oscillator is used as source of USB clock */
+      /* USB clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of USB clock*/
+      __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+
+  }
+
+  /*------------------------------------- SDMMC Configuration ------------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SDMMC(PeriphClkInit->SdmmcClockSelection));
+
+    switch(PeriphClkInit->SdmmcClockSelection)
+    {
+    case RCC_SDMMCCLKSOURCE_PLL:      /* PLL is used as clock source for SDMMC*/
+      /* Enable SDMMC Clock output generated form System PLL . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* SDMMC clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for SDMMC*/
+
+      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
+
+      /* SDMMC clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of SDMMC clock*/
+      __HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+
+#if defined(LTDC)
+  /*-------------------------------------- LTDC Configuration -----------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
+  {
+    if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!=HAL_OK)
+    {
+      status=HAL_ERROR;
+    }
+  }
+#endif /* LTDC */
+
+  /*------------------------------ RNG Configuration -------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG)
+  {
+
+    switch(PeriphClkInit->RngClockSelection)
+    {
+    case RCC_RNGCLKSOURCE_PLL:     /* PLL is used as clock source for RNG*/
+      /* Enable RNG Clock output generated form System RNG . */
+      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+
+      /* RNG clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_RNGCLKSOURCE_LSE: /* LSE is used as clock source for RNG*/
+
+      /* RNG clock source configuration done later after clock selection check */
+      break;
+
+    case RCC_RNGCLKSOURCE_LSI: /* LSI is used as clock source for RNG*/
+
+      /* RNG clock source configuration done later after clock selection check */
+      break;
+    case RCC_RNGCLKSOURCE_HSI48:
+      /* HSI48 oscillator is used as source of RNG clock */
+      /* RNG clock source configuration done later after clock selection check */
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
+    }
+
+    if(ret == HAL_OK)
+    {
+      /* Set the source of RNG clock*/
+      __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+
+  }
+
+  /*------------------------------ SWPMI1 Configuration ------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection));
+
+    /* Configure the SWPMI1 interface clock source */
+    __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);
+  }
+#if defined(HRTIM)
+  /*------------------------------ HRTIM1 clock Configuration ----------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection));
+
+    /* Configure the HRTIM1 clock source */
+    __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection);
+  }
+#endif  /*HRTIM*/
+  /*------------------------------ DFSDM1 Configuration ------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
+
+    /* Configure the DFSDM1 interface clock source */
+    __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
+  }
+
+#if defined(DFSDM2_BASE)
+  /*------------------------------ DFSDM2 Configuration ------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2) == RCC_PERIPHCLK_DFSDM2)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_DFSDM2CLKSOURCE(PeriphClkInit->Dfsdm2ClockSelection));
+
+    /* Configure the DFSDM2 interface clock source */
+    __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection);
+  }
+#endif  /* DFSDM2 */
+
+  /*------------------------------------ TIM configuration --------------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
+
+    /* Configure Timer Prescaler */
+    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
+  }
+
+  /*------------------------------------ CKPER configuration --------------------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_CLKPSOURCE(PeriphClkInit->CkperClockSelection));
+
+    /* Configure the CKPER clock source */
+    __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection);
+  }
+
+  if (status == HAL_OK)
+  {
+    return HAL_OK;
+  }
+  return HAL_ERROR;
+}
+
+/**
+  * @brief  Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
+  * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
+  *         returns the configuration information for the Extended Peripherals clocks :
+  *         (SDMMC, CKPER, FMC, QSPI*, OSPI*, DSI*, SPI45, SPDIF, DFSDM1, DFSDM2*, FDCAN, SWPMI, SAI23*, SAI1, SPI123,
+  *         USART234578, USART16, RNG, HRTIM1*, I2C123, USB, CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC.
+  *         SAI4A*, SAI4B*, SPI6, RTC, TIM).
+  * @retval None
+  *
+  *   (*) : Available on some STM32H7 lines only.
+  */
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  /* Set all possible values for the extended clock type parameter------------*/
+  PeriphClkInit->PeriphClockSelection =
+                 RCC_PERIPHCLK_USART16 | RCC_PERIPHCLK_USART234578 | RCC_PERIPHCLK_LPUART1 |
+                 RCC_PERIPHCLK_I2C4    | RCC_PERIPHCLK_LPTIM1      | RCC_PERIPHCLK_LPTIM2  | RCC_PERIPHCLK_LPTIM345 |
+                 RCC_PERIPHCLK_SAI1    | RCC_PERIPHCLK_SPI123      | RCC_PERIPHCLK_SPI45   | RCC_PERIPHCLK_SPI6     |
+	         RCC_PERIPHCLK_FDCAN   | RCC_PERIPHCLK_SDMMC       | RCC_PERIPHCLK_RNG     | RCC_PERIPHCLK_USB      |
+	         RCC_PERIPHCLK_ADC     | RCC_PERIPHCLK_SWPMI1      | RCC_PERIPHCLK_DFSDM1  | RCC_PERIPHCLK_RTC      |
+	         RCC_PERIPHCLK_CEC     | RCC_PERIPHCLK_FMC         | RCC_PERIPHCLK_SPDIFRX | RCC_PERIPHCLK_TIM      |
+	         RCC_PERIPHCLK_CKPER;
+
+PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C123;
+#if defined(RCC_CDCCIP1R_SAI2ASEL)
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI2A;
+#endif /* RCC_CDCCIP1R_SAI2ASEL */
+#if defined(RCC_CDCCIP1R_SAI2BSEL)
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI2B;
+#endif /* RCC_CDCCIP1R_SAI2BSEL */
+#if defined(SAI3)
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI23;
+#endif /* SAI3 */
+#if defined(SAI4)
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI4A;
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI4B;
+#endif /* SAI4 */
+#if defined(DFSDM2_BASE)
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_DFSDM2;
+#endif /* DFSDM2 */
+#if defined(QUADSPI)
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_QSPI;
+#endif /* QUADSPI */
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_OSPI;
+#endif /* OCTOSPI1 || OCTOSPI2 */
+#if defined(HRTIM)
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_HRTIM1;
+#endif /* HRTIM */
+#if defined(LTDC)
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LTDC;
+#endif /* LTDC */
+#if defined(DSI)
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_DSI;
+#endif /* DSI */
+
+  /* Get the PLL3 Clock configuration -----------------------------------------------*/
+  PeriphClkInit->PLL3.PLL3M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3)>> RCC_PLLCKSELR_DIVM3_Pos);
+  PeriphClkInit->PLL3.PLL3N = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_N3) >> RCC_PLL3DIVR_N3_Pos)+ 1U;
+  PeriphClkInit->PLL3.PLL3R = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> RCC_PLL3DIVR_R3_Pos)+ 1U;
+  PeriphClkInit->PLL3.PLL3P = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> RCC_PLL3DIVR_P3_Pos)+ 1U;
+  PeriphClkInit->PLL3.PLL3Q = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> RCC_PLL3DIVR_Q3_Pos)+ 1U;
+  PeriphClkInit->PLL3.PLL3RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3RGE) >> RCC_PLLCFGR_PLL3RGE_Pos);
+  PeriphClkInit->PLL3.PLL3VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3VCOSEL) >> RCC_PLLCFGR_PLL3VCOSEL_Pos);
+
+  /* Get the PLL2 Clock configuration -----------------------------------------------*/
+  PeriphClkInit->PLL2.PLL2M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2)>> RCC_PLLCKSELR_DIVM2_Pos);
+  PeriphClkInit->PLL2.PLL2N = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_N2) >> RCC_PLL2DIVR_N2_Pos)+ 1U;
+  PeriphClkInit->PLL2.PLL2R = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> RCC_PLL2DIVR_R2_Pos)+ 1U;
+  PeriphClkInit->PLL2.PLL2P = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> RCC_PLL2DIVR_P2_Pos)+ 1U;
+  PeriphClkInit->PLL2.PLL2Q = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> RCC_PLL2DIVR_Q2_Pos)+ 1U;
+  PeriphClkInit->PLL2.PLL2RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2RGE) >> RCC_PLLCFGR_PLL2RGE_Pos);
+  PeriphClkInit->PLL2.PLL2VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2VCOSEL) >> RCC_PLLCFGR_PLL2VCOSEL_Pos);
+
+  /* Get the USART1 configuration --------------------------------------------*/
+  PeriphClkInit->Usart16ClockSelection      = __HAL_RCC_GET_USART16_SOURCE();
+  /* Get the USART2/3/4/5/7/8 clock source -----------------------------------*/
+  PeriphClkInit->Usart234578ClockSelection  = __HAL_RCC_GET_USART234578_SOURCE();
+  /* Get the LPUART1 clock source --------------------------------------------*/
+  PeriphClkInit->Lpuart1ClockSelection      = __HAL_RCC_GET_LPUART1_SOURCE();
+  /* Get the I2C1/2/3 clock source -------------------------------------------*/
+  PeriphClkInit->I2c123ClockSelection       = __HAL_RCC_GET_I2C1_SOURCE();
+  /* Get the LPTIM1 clock source ---------------------------------------------*/
+  PeriphClkInit->Lptim1ClockSelection       = __HAL_RCC_GET_LPTIM1_SOURCE();
+  /* Get the LPTIM2 clock source ---------------------------------------------*/
+  PeriphClkInit->Lptim2ClockSelection       = __HAL_RCC_GET_LPTIM2_SOURCE();
+  /* Get the LPTIM3/4/5 clock source -----------------------------------------*/
+  PeriphClkInit->Lptim345ClockSelection     = __HAL_RCC_GET_LPTIM345_SOURCE();
+  /* Get the SAI1 clock source -----------------------------------------------*/
+  PeriphClkInit->Sai1ClockSelection         = __HAL_RCC_GET_SAI1_SOURCE();
+#if defined(SAI3)
+  /* Get the SAI2/3 clock source ---------------------------------------------*/
+  PeriphClkInit->Sai23ClockSelection        = __HAL_RCC_GET_SAI23_SOURCE();
+#endif  /*SAI3*/
+#if defined(RCC_CDCCIP1R_SAI2ASEL_0)
+  /* Get the SAI2A clock source ---------------------------------------------*/
+  PeriphClkInit->Sai2AClockSelection        = __HAL_RCC_GET_SAI2A_SOURCE();
+#endif  /*SAI2A*/
+#if defined(RCC_CDCCIP1R_SAI2BSEL_0)
+  /* Get the SAI2B clock source ---------------------------------------------*/
+  PeriphClkInit->Sai2BClockSelection        = __HAL_RCC_GET_SAI2B_SOURCE();
+#endif  /*SAI2B*/
+#if defined(SAI4)
+  /* Get the SAI4A clock source ----------------------------------------------*/
+  PeriphClkInit->Sai4AClockSelection        = __HAL_RCC_GET_SAI4A_SOURCE();
+  /* Get the SAI4B clock source ----------------------------------------------*/
+  PeriphClkInit->Sai4BClockSelection        = __HAL_RCC_GET_SAI4B_SOURCE();
+#endif  /*SAI4*/
+  /* Get the RTC clock source ------------------------------------------------*/
+  PeriphClkInit->RTCClockSelection          = __HAL_RCC_GET_RTC_SOURCE();
+  /* Get the USB clock source ------------------------------------------------*/
+  PeriphClkInit->UsbClockSelection          = __HAL_RCC_GET_USB_SOURCE();
+  /* Get the SDMMC clock source ----------------------------------------------*/
+  PeriphClkInit->SdmmcClockSelection        = __HAL_RCC_GET_SDMMC_SOURCE();
+  /* Get the RNG clock source ------------------------------------------------*/
+  PeriphClkInit->RngClockSelection          = __HAL_RCC_GET_RNG_SOURCE();
+#if defined(HRTIM1)
+  /* Get the HRTIM1 clock source ---------------------------------------------*/
+  PeriphClkInit->Hrtim1ClockSelection       = __HAL_RCC_GET_HRTIM1_SOURCE();
+#endif /* HRTIM1 */
+  /* Get the ADC clock source ------------------------------------------------*/
+  PeriphClkInit->AdcClockSelection          = __HAL_RCC_GET_ADC_SOURCE();
+  /* Get the SWPMI1 clock source ---------------------------------------------*/
+  PeriphClkInit->Swpmi1ClockSelection       = __HAL_RCC_GET_SWPMI1_SOURCE();
+  /* Get the DFSDM1 clock source ---------------------------------------------*/
+  PeriphClkInit->Dfsdm1ClockSelection       = __HAL_RCC_GET_DFSDM1_SOURCE();
+#if defined(DFSDM2_BASE)
+  /* Get the DFSDM2 clock source ---------------------------------------------*/
+  PeriphClkInit->Dfsdm2ClockSelection       = __HAL_RCC_GET_DFSDM2_SOURCE();
+#endif /* DFSDM2 */
+  /* Get the SPDIFRX clock source --------------------------------------------*/
+  PeriphClkInit->SpdifrxClockSelection      = __HAL_RCC_GET_SPDIFRX_SOURCE();
+  /* Get the SPI1/2/3 clock source -------------------------------------------*/
+  PeriphClkInit->Spi123ClockSelection       = __HAL_RCC_GET_SPI123_SOURCE();
+  /* Get the SPI4/5 clock source ---------------------------------------------*/
+  PeriphClkInit->Spi45ClockSelection        = __HAL_RCC_GET_SPI45_SOURCE();
+  /* Get the SPI6 clock source -----------------------------------------------*/
+  PeriphClkInit->Spi6ClockSelection         = __HAL_RCC_GET_SPI6_SOURCE();
+  /* Get the FDCAN clock source ----------------------------------------------*/
+  PeriphClkInit->FdcanClockSelection        = __HAL_RCC_GET_FDCAN_SOURCE();
+  /* Get the CEC clock source ------------------------------------------------*/
+  PeriphClkInit->CecClockSelection          = __HAL_RCC_GET_CEC_SOURCE();
+  /* Get the FMC clock source ------------------------------------------------*/
+  PeriphClkInit->FmcClockSelection          = __HAL_RCC_GET_FMC_SOURCE();
+#if defined(QUADSPI)
+  /* Get the QSPI clock source -----------------------------------------------*/
+  PeriphClkInit->QspiClockSelection         = __HAL_RCC_GET_QSPI_SOURCE();
+#endif /* QUADSPI */
+#if defined(OCTOSPI1) || defined(OCTOSPI2)
+  /* Get the OSPI clock source -----------------------------------------------*/
+  PeriphClkInit->OspiClockSelection         = __HAL_RCC_GET_OSPI_SOURCE();
+#endif /* OCTOSPI1 || OCTOSPI2 */
+
+#if defined(DSI)
+  /* Get the DSI clock source ------------------------------------------------*/
+  PeriphClkInit->DsiClockSelection          = __HAL_RCC_GET_DSI_SOURCE();
+#endif /*DSI*/
+
+  /* Get the CKPER clock source ----------------------------------------------*/
+  PeriphClkInit->CkperClockSelection        = __HAL_RCC_GET_CLKP_SOURCE();
+
+  /* Get the TIM Prescaler configuration -------------------------------------*/
+  if ((RCC->CFGR & RCC_CFGR_TIMPRE) == 0U)
+  {
+    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
+  }
+  else
+  {
+    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
+  }
+}
+
+/**
+  * @brief  Return the peripheral clock frequency for a given peripheral(SAI..)
+  * @note   Return 0 if peripheral clock identifier not managed by this API
+  * @param  PeriphClk: Peripheral clock identifier
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PERIPHCLK_SAI1  : SAI1 peripheral clock
+  *            @arg RCC_PERIPHCLK_SAI23 : SAI2/3  peripheral clock (*)
+  *            @arg RCC_PERIPHCLK_SAI2A : SAI2A peripheral clock (*)
+  *            @arg RCC_PERIPHCLK_SAI2B : SAI2B peripheral clock (*)
+  *            @arg RCC_PERIPHCLK_SAI4A : SAI4A peripheral clock (*)
+  *            @arg RCC_PERIPHCLK_SAI4B : SAI4B peripheral clock (*)
+  *            @arg RCC_PERIPHCLK_SPI123: SPI1/2/3 peripheral clock
+  *            @arg RCC_PERIPHCLK_ADC   : ADC peripheral clock
+  *            @arg RCC_PERIPHCLK_SDMMC : SDMMC peripheral clock
+  *            @arg RCC_PERIPHCLK_SPI6  : SPI6 peripheral clock
+  * @retval Frequency in KHz
+  *
+  *  (*) : Available on some STM32H7 lines only.
+  */
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
+{
+  PLL1_ClocksTypeDef pll1_clocks;
+  PLL2_ClocksTypeDef pll2_clocks;
+  PLL3_ClocksTypeDef pll3_clocks;
+
+  /* This variable is used to store the SAI clock frequency (value in Hz) */
+  uint32_t frequency;
+  /* This variable is used to store the SAI and CKP clock source */
+  uint32_t saiclocksource;
+  uint32_t ckpclocksource;
+  uint32_t srcclk;
+
+  if (PeriphClk == RCC_PERIPHCLK_SAI1)
+    {
+
+      saiclocksource= __HAL_RCC_GET_SAI1_SOURCE();
+
+      switch (saiclocksource)
+      {
+      case RCC_SAI1CLKSOURCE_PLL: /* PLL1 is the clock source for SAI1 */
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+          break;
+        }
+      case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI1 */
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_P_Frequency;
+          break;
+        }
+
+      case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI1 */
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+          frequency = pll3_clocks.PLL3_P_Frequency;
+          break;
+        }
+
+      case RCC_SAI1CLKSOURCE_CLKP: /* CKPER is the clock source for SAI1*/
+        {
+
+          ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
+
+          if(ckpclocksource== RCC_CLKPSOURCE_HSI)
+          {
+            /* In Case the CKPER Source is HSI */
+            frequency = HSI_VALUE;
+          }
+
+          else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
+          {
+            /* In Case the CKPER Source is CSI */
+            frequency = CSI_VALUE;
+          }
+
+          else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
+          {
+            /* In Case the CKPER Source is HSE */
+            frequency = HSE_VALUE;
+          }
+
+          else
+          {
+            /* In Case the CKPER is disabled*/
+            frequency = 0;
+          }
+
+          break;
+        }
+
+      case (RCC_SAI1CLKSOURCE_PIN): /* External clock is the clock source for SAI1 */
+        {
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+      default :
+        {
+          frequency = 0;
+          break;
+        }
+      }
+    }
+
+#if defined(SAI3)
+  else if (PeriphClk == RCC_PERIPHCLK_SAI23)
+    {
+
+      saiclocksource= __HAL_RCC_GET_SAI23_SOURCE();
+
+      switch (saiclocksource)
+      {
+      case 0: /* PLL1 is the clock source for SAI2/3 */
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+          break;
+        }
+      case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI2/3 */
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_P_Frequency;
+          break;
+        }
+
+      case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI2/3 */
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+          frequency = pll3_clocks.PLL3_P_Frequency;
+          break;
+        }
+
+      case RCC_SAI23CLKSOURCE_CLKP: /* CKPER is the clock source for SAI2/3 */
+        {
+
+          ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
+
+          if(ckpclocksource== RCC_CLKPSOURCE_HSI)
+          {
+            /* In Case the CKPER Source is HSI */
+            frequency = HSI_VALUE;
+          }
+
+          else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
+          {
+            /* In Case the CKPER Source is CSI */
+            frequency = CSI_VALUE;
+          }
+
+          else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
+          {
+            /* In Case the CKPER Source is HSE */
+            frequency = HSE_VALUE;
+          }
+
+          else
+          {
+            /* In Case the CKPER is disabled*/
+            frequency = 0;
+          }
+
+          break;
+        }
+
+      case (RCC_SAI23CLKSOURCE_PIN): /* External clock is the clock source for SAI2/3 */
+        {
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+      default :
+        {
+          frequency = 0;
+          break;
+        }
+      }
+    }
+#endif /* SAI3 */
+
+#if  defined(RCC_CDCCIP1R_SAI2ASEL)
+
+    else if (PeriphClk == RCC_PERIPHCLK_SAI2A)
+    {
+      saiclocksource= __HAL_RCC_GET_SAI2A_SOURCE();
+
+      switch (saiclocksource)
+      {
+      case 0: /* PLL1 is the clock source for SAI2A */
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+          break;
+        }
+      case RCC_SAI2ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI2A */
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_P_Frequency;
+          break;
+        }
+
+      case RCC_SAI2ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI2A  */
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+          frequency = pll3_clocks.PLL3_P_Frequency;
+          break;
+        }
+
+      case RCC_SAI2ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI2A  */
+        {
+
+          ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
+
+          if(ckpclocksource== RCC_CLKPSOURCE_HSI)
+          {
+            /* In Case the CKPER Source is HSI */
+            frequency = HSI_VALUE;
+          }
+
+          else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
+          {
+            /* In Case the CKPER Source is CSI */
+            frequency = CSI_VALUE;
+          }
+
+          else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
+          {
+            /* In Case the CKPER Source is HSE */
+            frequency = HSE_VALUE;
+          }
+
+          else
+          {
+            /* In Case the CKPER is disabled*/
+            frequency = 0;
+          }
+
+          break;
+        }
+
+      case (RCC_SAI2ACLKSOURCE_PIN): /* External clock is the clock source for SAI2A */
+        {
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+
+      default :
+        {
+          frequency = 0;
+          break;
+        }
+      }
+
+    }
+#endif
+
+#if  defined(RCC_CDCCIP1R_SAI2BSEL_0)
+  else if (PeriphClk == RCC_PERIPHCLK_SAI2B)
+    {
+
+      saiclocksource= __HAL_RCC_GET_SAI2B_SOURCE();
+
+      switch (saiclocksource)
+      {
+      case 0: /* PLL1 is the clock source for SAI2B */
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+          break;
+        }
+      case RCC_SAI2BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI2B */
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_P_Frequency;
+          break;
+        }
+
+      case RCC_SAI2BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI2B */
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+          frequency = pll3_clocks.PLL3_P_Frequency;
+          break;
+        }
+
+      case RCC_SAI2BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI2B*/
+        {
+
+          ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
+
+          if(ckpclocksource== RCC_CLKPSOURCE_HSI)
+          {
+            /* In Case the CKPER Source is HSI */
+            frequency = HSI_VALUE;
+          }
+
+          else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
+          {
+            /* In Case the CKPER Source is CSI */
+            frequency = CSI_VALUE;
+          }
+
+          else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
+          {
+            /* In Case the CKPER Source is HSE */
+            frequency = HSE_VALUE;
+          }
+
+          else
+          {
+            /* In Case the CKPER is disabled*/
+            frequency = 0;
+          }
+          break;
+        }
+
+      case (RCC_SAI2BCLKSOURCE_PIN): /* External clock is the clock source for SAI2B */
+        {
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+
+      default :
+        {
+          frequency = 0;
+          break;
+        }
+      }
+    }
+#endif
+
+#if defined(SAI4)
+  else if (PeriphClk == RCC_PERIPHCLK_SAI4A)
+    {
+
+      saiclocksource= __HAL_RCC_GET_SAI4A_SOURCE();
+
+      switch (saiclocksource)
+      {
+      case 0: /* PLL1 is the clock source for SAI4A */
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+          break;
+        }
+      case RCC_D3CCIPR_SAI4ASEL_0: /* PLLI2 is the clock source for SAI4A */
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_P_Frequency;
+          break;
+        }
+
+      case RCC_D3CCIPR_SAI4ASEL_1: /* PLLI3 is the clock source for SAI4A */
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+          frequency = pll3_clocks.PLL3_P_Frequency;
+          break;
+        }
+
+      case RCC_D3CCIPR_SAI4ASEL_2: /* CKPER is the clock source for SAI4A*/
+        {
+
+          ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
+
+          if(ckpclocksource== RCC_CLKPSOURCE_HSI)
+          {
+            /* In Case the CKPER Source is HSI */
+            frequency = HSI_VALUE;
+          }
+
+          else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
+          {
+            /* In Case the CKPER Source is CSI */
+            frequency = CSI_VALUE;
+          }
+
+          else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
+          {
+            /* In Case the CKPER Source is HSE */
+            frequency = HSE_VALUE;
+          }
+
+          else
+          {
+            /* In Case the CKPER is disabled*/
+            frequency = 0;
+          }
+
+          break;
+        }
+
+      case (RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1 ): /* External clock is the clock source for SAI4A */
+        {
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+
+      default :
+        {
+          frequency = 0;
+          break;
+        }
+      }
+    }
+
+  else if (PeriphClk == RCC_PERIPHCLK_SAI4B)
+    {
+
+      saiclocksource= __HAL_RCC_GET_SAI4B_SOURCE();
+
+      switch (saiclocksource)
+      {
+      case 0: /* PLL1 is the clock source for SAI4B */
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+          break;
+        }
+      case RCC_D3CCIPR_SAI4BSEL_0: /* PLLI2 is the clock source for SAI4B */
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_P_Frequency;
+          break;
+        }
+
+      case RCC_D3CCIPR_SAI4BSEL_1: /* PLLI3 is the clock source for SAI4B */
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+          frequency = pll3_clocks.PLL3_P_Frequency;
+          break;
+        }
+
+      case RCC_D3CCIPR_SAI4BSEL_2: /* CKPER is the clock source for SAI4B*/
+        {
+
+          ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
+
+          if(ckpclocksource== RCC_CLKPSOURCE_HSI)
+          {
+            /* In Case the CKPER Source is HSI */
+            frequency = HSI_VALUE;
+          }
+
+          else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
+          {
+            /* In Case the CKPER Source is CSI */
+            frequency = CSI_VALUE;
+          }
+
+          else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
+          {
+            /* In Case the CKPER Source is HSE */
+            frequency = HSE_VALUE;
+          }
+
+          else
+          {
+            /* In Case the CKPER is disabled*/
+            frequency = 0;
+          }
+
+          break;
+        }
+
+      case (RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1 ): /* External clock is the clock source for SAI4B */
+        {
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+
+      default :
+        {
+          frequency = 0;
+          break;
+        }
+      }
+    }
+#endif /*SAI4*/
+  else if (PeriphClk == RCC_PERIPHCLK_SPI123)
+    {
+      /* Get SPI1/2/3 clock source */
+      srcclk= __HAL_RCC_GET_SPI123_SOURCE();
+
+      switch (srcclk)
+      {
+      case RCC_SPI123CLKSOURCE_PLL: /* PLL1 is the clock source for I2S */
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+          break;
+        }
+      case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is the clock source for I2S */
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_P_Frequency;
+          break;
+        }
+
+      case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is the clock source for I2S */
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+          frequency = pll3_clocks.PLL3_P_Frequency;
+          break;
+        }
+
+      case RCC_SPI123CLKSOURCE_CLKP: /* CKPER is the clock source for I2S */
+        {
+
+          ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
+
+          if(ckpclocksource== RCC_CLKPSOURCE_HSI)
+          {
+            /* In Case the CKPER Source is HSI */
+            frequency = HSI_VALUE;
+          }
+
+          else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
+          {
+            /* In Case the CKPER Source is CSI */
+            frequency = CSI_VALUE;
+          }
+
+          else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
+          {
+            /* In Case the CKPER Source is HSE */
+            frequency = HSE_VALUE;
+          }
+
+          else
+          {
+            /* In Case the CKPER is disabled*/
+            frequency = 0;
+          }
+
+          break;
+        }
+
+      case (RCC_SPI123CLKSOURCE_PIN): /* External clock is the clock source for I2S */
+        {
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+      default :
+        {
+          frequency = 0;
+          break;
+        }
+      }
+    }
+  else if (PeriphClk == RCC_PERIPHCLK_ADC)
+    {
+      /* Get ADC clock source */
+      srcclk= __HAL_RCC_GET_ADC_SOURCE();
+
+      switch (srcclk)
+      {
+      case RCC_ADCCLKSOURCE_PLL2:
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_P_Frequency;
+          break;
+        }
+      case RCC_ADCCLKSOURCE_PLL3:
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+          frequency = pll3_clocks.PLL3_R_Frequency;
+          break;
+        }
+
+      case RCC_ADCCLKSOURCE_CLKP:
+        {
+
+          ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
+
+          if(ckpclocksource== RCC_CLKPSOURCE_HSI)
+          {
+            /* In Case the CKPER Source is HSI */
+            frequency = HSI_VALUE;
+          }
+
+          else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
+          {
+            /* In Case the CKPER Source is CSI */
+            frequency = CSI_VALUE;
+          }
+
+          else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
+          {
+            /* In Case the CKPER Source is HSE */
+            frequency = HSE_VALUE;
+          }
+
+          else
+          {
+            /* In Case the CKPER is disabled*/
+            frequency = 0;
+          }
+
+          break;
+        }
+
+      default :
+        {
+          frequency = 0;
+          break;
+        }
+      }
+    }
+  else if (PeriphClk == RCC_PERIPHCLK_SDMMC)
+    {
+      /* Get SDMMC clock source */
+      srcclk= __HAL_RCC_GET_SDMMC_SOURCE();
+
+      switch (srcclk)
+      {
+      case RCC_SDMMCCLKSOURCE_PLL: /* PLL1 is the clock source for SDMMC */
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+          break;
+        }
+      case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is the clock source for SDMMC */
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_R_Frequency;
+          break;
+        }
+
+      default :
+        {
+          frequency = 0;
+          break;
+        }
+      }
+    }
+  else if (PeriphClk == RCC_PERIPHCLK_SPI6)
+    {
+      /* Get SPI6 clock source */
+      srcclk= __HAL_RCC_GET_SPI6_SOURCE();
+
+      switch (srcclk)
+      {
+      case RCC_SPI6CLKSOURCE_D3PCLK1: /* D3PCLK1 (PCLK4) is the clock source for SPI6 */
+        {
+          frequency = HAL_RCCEx_GetD3PCLK1Freq();
+          break;
+        }
+      case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI6 */
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_Q_Frequency;
+          break;
+        }
+      case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI6 */
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+          frequency = pll3_clocks.PLL3_Q_Frequency;
+          break;
+        }
+      case RCC_SPI6CLKSOURCE_HSI: /* HSI is the clock source for SPI6 */
+        {
+          frequency = HSI_VALUE;
+          break;
+        }
+      case RCC_SPI6CLKSOURCE_CSI: /* CSI is the clock source for SPI6 */
+        {
+          frequency = CSI_VALUE;
+          break;
+        }
+      case RCC_SPI6CLKSOURCE_HSE: /* HSE is the clock source for SPI6 */
+        {
+          frequency = HSE_VALUE;
+          break;
+        }
+#if defined(RCC_SPI6CLKSOURCE_PIN)
+      case RCC_SPI6CLKSOURCE_PIN: /* External clock is the clock source for SPI6 */
+        {
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+#endif /* RCC_SPI6CLKSOURCE_PIN */
+      default :
+        {
+          frequency = 0;
+          break;
+        }
+      }
+    }
+  else
+    {
+      frequency = 0;
+    }
+
+  return frequency;
+}
+
+
+/**
+  * @brief  Returns the D1PCLK1 frequency
+  * @note   Each time D1PCLK1 changes, this function must be called to update the
+  *         right D1PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
+  * @retval D1PCLK1 frequency
+  */
+uint32_t HAL_RCCEx_GetD1PCLK1Freq(void)
+{
+#if defined(RCC_D1CFGR_D1PPRE)
+  /* Get HCLK source and Compute D1PCLK1 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1PPRE)>> RCC_D1CFGR_D1PPRE_Pos] & 0x1FU));
+#else
+/* Get HCLK source and Compute D1PCLK1 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE)>> RCC_CDCFGR1_CDPPRE_Pos] & 0x1FU));
+#endif
+}
+
+/**
+  * @brief  Returns the D3PCLK1 frequency
+  * @note   Each time D3PCLK1 changes, this function must be called to update the
+  *         right D3PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
+  * @retval D3PCLK1 frequency
+  */
+uint32_t HAL_RCCEx_GetD3PCLK1Freq(void)
+{
+#if defined(RCC_D3CFGR_D3PPRE)
+  /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE)>> RCC_D3CFGR_D3PPRE_Pos] & 0x1FU));
+#else
+  /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE)>> RCC_SRDCFGR_SRDPPRE_Pos] & 0x1FU));
+#endif
+}
+/**
+* @brief  Returns the PLL2 clock frequencies :PLL2_P_Frequency,PLL2_R_Frequency and PLL2_Q_Frequency
+  * @note   The PLL2 clock frequencies computed by this function is not the real
+  *         frequency in the chip. It is calculated based on the predefined
+  *         constant and the selected clock source:
+  * @note     The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors.
+  * @note   This function can be used by the user application to compute the
+  *         baud-rate for the communication peripherals or configure other parameters.
+  *
+  * @note   Each time PLL2CLK changes, this function must be called to update the
+  *         right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect.
+  * @param  PLL2_Clocks structure.
+  * @retval None
+  */
+void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef* PLL2_Clocks)
+{
+  uint32_t  pllsource, pll2m,  pll2fracen, hsivalue;
+  float_t fracn2, pll2vco;
+
+  /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL2M) * PLL2N
+     PLL2xCLK = PLL2_VCO / PLL2x
+  */
+  pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+  pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2)>> 12);
+  pll2fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) >> RCC_PLLCFGR_PLL2FRACEN_Pos;
+  fracn2 =(float_t)(uint32_t)(pll2fracen* ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2)>> 3));
+
+  if (pll2m != 0U)
+  {
+    switch (pllsource)
+    {
+
+    case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
+
+      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+      {
+        hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
+        pll2vco = ( (float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );
+      }
+      else
+      {
+        pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );
+      }
+      break;
+
+    case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
+      pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );
+      break;
+
+    case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
+      pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );
+      break;
+
+    default:
+      pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );
+      break;
+    }
+    PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >>9)  + (float_t)1 )) ;
+    PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >>16) + (float_t)1 )) ;
+    PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >>24) + (float_t)1 )) ;
+  }
+  else
+  {
+    PLL2_Clocks->PLL2_P_Frequency = 0U;
+    PLL2_Clocks->PLL2_Q_Frequency = 0U;
+    PLL2_Clocks->PLL2_R_Frequency = 0U;
+  }
+}
+
+/**
+* @brief  Returns the PLL3 clock frequencies :PLL3_P_Frequency,PLL3_R_Frequency and PLL3_Q_Frequency
+  * @note   The PLL3 clock frequencies computed by this function is not the real
+  *         frequency in the chip. It is calculated based on the predefined
+  *         constant and the selected clock source:
+  * @note     The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors.
+  * @note   This function can be used by the user application to compute the
+  *         baud-rate for the communication peripherals or configure other parameters.
+  *
+  * @note   Each time PLL3CLK changes, this function must be called to update the
+  *         right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect.
+  * @param  PLL3_Clocks structure.
+  * @retval None
+  */
+void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef* PLL3_Clocks)
+{
+  uint32_t pllsource, pll3m, pll3fracen, hsivalue;
+  float_t fracn3, pll3vco;
+
+  /* PLL3_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL3M) * PLL3N
+     PLL3xCLK = PLL3_VCO / PLLxR
+  */
+  pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+  pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3)>> 20)  ;
+  pll3fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) >> RCC_PLLCFGR_PLL3FRACEN_Pos;
+  fracn3 = (float_t)(uint32_t)(pll3fracen* ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3)>> 3));
+
+  if (pll3m != 0U)
+  {
+    switch (pllsource)
+    {
+    case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
+
+      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+      {
+        hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
+        pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );
+      }
+      else
+      {
+        pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );
+      }
+      break;
+    case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
+      pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );
+      break;
+
+    case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
+      pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );
+      break;
+
+    default:
+      pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );
+      break;
+    }
+    PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >>9)  + (float_t)1 )) ;
+    PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >>16) + (float_t)1 )) ;
+    PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >>24) + (float_t)1 )) ;
+  }
+  else
+  {
+    PLL3_Clocks->PLL3_P_Frequency = 0U;
+    PLL3_Clocks->PLL3_Q_Frequency = 0U;
+    PLL3_Clocks->PLL3_R_Frequency = 0U;
+  }
+
+}
+
+/**
+* @brief  Returns the PLL1 clock frequencies :PLL1_P_Frequency,PLL1_R_Frequency and PLL1_Q_Frequency
+  * @note   The PLL1 clock frequencies computed by this function is not the real
+  *         frequency in the chip. It is calculated based on the predefined
+  *         constant and the selected clock source:
+  * @note     The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors.
+  * @note   This function can be used by the user application to compute the
+  *         baud-rate for the communication peripherals or configure other parameters.
+  *
+  * @note   Each time PLL1CLK changes, this function must be called to update the
+  *         right PLL1CLK value. Otherwise, any configuration based on this function will be incorrect.
+  * @param  PLL1_Clocks structure.
+  * @retval None
+  */
+void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef* PLL1_Clocks)
+{
+  uint32_t pllsource, pll1m, pll1fracen, hsivalue;
+  float_t fracn1, pll1vco;
+
+  pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+  pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4);
+  pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN;
+  fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
+
+  if (pll1m != 0U)
+  {
+    switch (pllsource)
+    {
+
+    case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
+
+      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+      {
+        hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
+        pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+      }
+      else
+      {
+        pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+      }
+      break;
+    case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
+      pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+      break;
+
+    case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
+      pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+      break;
+
+    default:
+      pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+      break;
+    }
+
+    PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9)  + (float_t)1 )) ;
+    PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >>16) + (float_t)1 )) ;
+    PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >>24) + (float_t)1 )) ;
+  }
+  else
+  {
+    PLL1_Clocks->PLL1_P_Frequency = 0U;
+    PLL1_Clocks->PLL1_Q_Frequency = 0U;
+    PLL1_Clocks->PLL1_R_Frequency = 0U;
+  }
+
+}
+
+/**
+  * @brief  Returns the main System frequency
+  * @note   Each time System clock changes, this function must be called to update the
+  *         right core clock value. Otherwise, any configuration based on this function will be incorrect.
+  * @note   The SystemCoreClock CMSIS variable is used to store System current Core Clock Frequency
+  *         and updated within this function
+  * @retval HCLK frequency
+  */
+uint32_t HAL_RCCEx_GetD1SysClockFreq(void)
+{
+uint32_t common_system_clock;
+
+#if defined(RCC_D1CFGR_D1CPRE)
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
+#else
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU);
+#endif
+
+  /* Update the SystemD2Clock global variable */
+#if defined(RCC_D1CFGR_HPRE)
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+#else
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+#endif
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  SystemCoreClock = SystemD2Clock;
+#else
+  SystemCoreClock = common_system_clock;
+#endif /* DUAL_CORE && CORE_CM4 */
+
+  return common_system_clock;
+}
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_Exported_Functions_Group2 Extended System Control functions
+ *  @brief  Extended Peripheral Control functions
+  * @{
+  */
+/**
+  * @brief  Enables the LSE Clock Security System.
+  * @note   Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled
+  *         with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC
+  *         clock with HAL_RCCEx_PeriphCLKConfig().
+  * @retval None
+  */
+void HAL_RCCEx_EnableLSECSS(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
+}
+
+/**
+  * @brief  Disables the LSE Clock Security System.
+  * @note   LSE Clock Security System can only be disabled after a LSE failure detection.
+  * @retval None
+  */
+void HAL_RCCEx_DisableLSECSS(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
+  /* Disable LSE CSS IT if any */
+  __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS);
+}
+
+/**
+  * @brief  Enable the LSE Clock Security System Interrupt & corresponding EXTI line.
+  * @note   LSE Clock Security System Interrupt is mapped on EXTI line 18
+  * @retval None
+  */
+void HAL_RCCEx_EnableLSECSS_IT(void)
+{
+  /* Enable LSE CSS */
+  SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
+
+  /* Enable LSE CSS IT */
+  __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS);
+
+  /* Enable IT on EXTI Line 18 */
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  __HAL_RCC_C2_LSECSS_EXTI_ENABLE_IT();
+#else
+  __HAL_RCC_LSECSS_EXTI_ENABLE_IT();
+#endif /* DUAL_CORE && CORE_CM4 */
+  __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();
+}
+
+/**
+  * @brief  Configure the oscillator clock source for wakeup from Stop and CSS backup clock
+  * @param  WakeUpClk: Wakeup clock
+  *         This parameter can be one of the following values:
+  *            @arg RCC_STOP_WAKEUPCLOCK_CSI: CSI oscillator selection
+  *            @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI oscillator selection
+  * @note   This function shall not be called after the Clock Security System on HSE has been
+  *         enabled.
+  * @retval None
+  */
+void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)
+{
+  assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk));
+
+  __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk);
+}
+
+/**
+  * @brief  Configure the oscillator Kernel clock source for wakeup from Stop
+  * @param  WakeUpClk: Kernel Wakeup clock
+  *         This parameter can be one of the following values:
+  *            @arg RCC_STOP_KERWAKEUPCLOCK_CSI: CSI oscillator selection
+  *            @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI oscillator selection
+  * @retval None
+  */
+void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk)
+{
+  assert_param(IS_RCC_STOP_KERWAKEUPCLOCK(WakeUpClk));
+
+  __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(WakeUpClk);
+}
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Enable COREx boot independently of CMx_B option byte value
+  * @param  RCC_BootCx: Boot Core to be enabled
+  *         This parameter can be one of the following values:
+  *            @arg RCC_BOOT_C1: CM7 core selection
+  *            @arg RCC_BOOT_C2: CM4 core selection
+  * @note   This bit can be set by software but is cleared by hardware after a system reset or STANDBY
+  *
+  * @retval None
+  */
+void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx)
+{
+  assert_param(IS_RCC_BOOT_CORE(RCC_BootCx));
+  SET_BIT(RCC->GCR, RCC_BootCx) ;
+}
+
+#endif /*DUAL_CORE*/
+
+#if defined(DUAL_CORE)
+/**
+  * @brief  Configure WWDGx to generate a system reset not only CPUx reset(default) when a time-out occurs
+  * @param  RCC_WWDGx: WWDGx to be configured
+  *         This parameter can be one of the following values:
+  *            @arg RCC_WWDG1: WWDG1 generates system reset
+  *            @arg RCC_WWDG2: WWDG2 generates system reset
+  * @note   This bit can be set by software but is cleared by hardware during a system reset
+  *
+  * @retval None
+  */
+void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx)
+{
+  assert_param(IS_RCC_SCOPE_WWDG(RCC_WWDGx));
+  SET_BIT(RCC->GCR, RCC_WWDGx) ;
+}
+
+#else
+#if defined(RCC_GCR_WW1RSC)
+/**
+  * @brief  Configure WWDG1 to generate a system reset not only CPU reset(default) when a time-out occurs
+  * @param  RCC_WWDGx: WWDGx to be configured
+  *         This parameter can be one of the following values:
+  *            @arg RCC_WWDG1: WWDG1 generates system reset
+  * @note   This bit can be set by software but is cleared by hardware during a system reset
+  *
+  * @retval None
+  */
+void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx)
+{
+  assert_param(IS_RCC_SCOPE_WWDG(RCC_WWDGx));
+  SET_BIT(RCC->GCR, RCC_WWDGx) ;
+}
+#endif
+#endif /*DUAL_CORE*/
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions
+ *  @brief  Extended Clock Recovery System Control functions
+ *
+@verbatim
+ ===============================================================================
+                ##### Extended Clock Recovery System Control functions  #####
+ ===============================================================================
+    [..]
+      For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows:
+
+      (#) In System clock config, HSI48 needs to be enabled
+
+      (#) Enable CRS clock in IP MSP init which will use CRS functions
+
+      (#) Call CRS functions as follows:
+          (##) Prepare synchronization configuration necessary for HSI48 calibration
+              (+++) Default values can be set for frequency Error Measurement (reload and error limit)
+                        and also HSI48 oscillator smooth trimming.
+              (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
+                        directly reload value with target and synchronization frequencies values
+          (##) Call function HAL_RCCEx_CRSConfig which
+              (+++) Resets CRS registers to their default values.
+              (+++) Configures CRS registers with synchronization configuration
+              (+++) Enables automatic calibration and frequency error counter feature
+           Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the
+           periodic USB SOF will not be generated by the host. No SYNC signal will therefore be
+           provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock
+           precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs
+           should be used as SYNC signal.
+
+          (##) A polling function is provided to wait for complete synchronization
+              (+++) Call function HAL_RCCEx_CRSWaitSynchronization()
+              (+++) According to CRS status, user can decide to adjust again the calibration or continue
+                        application if synchronization is OK
+
+      (#) User can retrieve information related to synchronization in calling function
+            HAL_RCCEx_CRSGetSynchronizationInfo()
+
+      (#) Regarding synchronization status and synchronization information, user can try a new calibration
+           in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
+           Note: When the SYNC event is detected during the down-counting phase (before reaching the zero value),
+           it means that the actual frequency is lower than the target (and so, that the TRIM value should be
+           incremented), while when it is detected during the up-counting phase it means that the actual frequency
+           is higher (and that the TRIM value should be decremented).
+
+      (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go
+          through CRS Handler (CRS_IRQn/CRS_IRQHandler)
+              (++) Call function HAL_RCCEx_CRSConfig()
+              (++) Enable CRS_IRQn (thanks to NVIC functions)
+              (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT)
+              (++) Implement CRS status management in the following user callbacks called from
+                   HAL_RCCEx_CRS_IRQHandler():
+                   (+++) HAL_RCCEx_CRS_SyncOkCallback()
+                   (+++) HAL_RCCEx_CRS_SyncWarnCallback()
+                   (+++) HAL_RCCEx_CRS_ExpectedSyncCallback()
+                   (+++) HAL_RCCEx_CRS_ErrorCallback()
+
+      (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate().
+          This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler)
+
+@endverbatim
+ * @{
+ */
+
+/**
+  * @brief  Start automatic synchronization for polling mode
+  * @param  pInit Pointer on RCC_CRSInitTypeDef structure
+  * @retval None
+  */
+void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
+{
+  uint32_t value;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));
+  assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));
+  assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));
+  assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));
+  assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));
+  assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));
+
+  /* CONFIGURATION */
+
+  /* Before configuration, reset CRS registers to their default values*/
+  __HAL_RCC_CRS_FORCE_RESET();
+  __HAL_RCC_CRS_RELEASE_RESET();
+
+  /* Set the SYNCDIV[2:0] bits according to Pre-scaler value */
+  /* Set the SYNCSRC[1:0] bits according to Source value */
+  /* Set the SYNCSPOL bit according to Polarity value */
+  if ((HAL_GetREVID() <= REV_ID_Y) && (pInit->Source == RCC_CRS_SYNC_SOURCE_USB2))
+  {
+    /* Use Rev.Y value of USB2 */
+    value = (pInit->Prescaler | RCC_CRS_SYNC_SOURCE_PIN | pInit->Polarity);
+  }
+  else
+  {
+    value = (pInit->Prescaler | pInit->Source | pInit->Polarity);
+  }
+  /* Set the RELOAD[15:0] bits according to ReloadValue value */
+  value |= pInit->ReloadValue;
+  /* Set the FELIM[7:0] bits according to ErrorLimitValue value */
+  value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos);
+  WRITE_REG(CRS->CFGR, value);
+
+  /* Adjust HSI48 oscillator smooth trimming */
+  /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */
+  MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos));
+
+  /* START AUTOMATIC SYNCHRONIZATION*/
+
+  /* Enable Automatic trimming & Frequency error counter */
+  SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN);
+}
+
+/**
+  * @brief  Generate the software synchronization event
+  * @retval None
+  */
+void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
+{
+  SET_BIT(CRS->CR, CRS_CR_SWSYNC);
+}
+
+/**
+  * @brief  Return synchronization info
+  * @param  pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
+  * @retval None
+  */
+void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
+{
+  /* Check the parameter */
+  assert_param(pSynchroInfo != (void *)NULL);
+
+  /* Get the reload value */
+  pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
+
+  /* Get HSI48 oscillator smooth trimming */
+  pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
+
+  /* Get Frequency error capture */
+  pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
+
+  /* Get Frequency error direction */
+  pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
+}
+
+/**
+* @brief Wait for CRS Synchronization status.
+* @param Timeout  Duration of the time-out
+* @note  Timeout is based on the maximum time to receive a SYNC event based on synchronization
+*        frequency.
+* @note    If Time-out set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
+* @retval Combination of Synchronization status
+*          This parameter can be a combination of the following values:
+*            @arg @ref RCC_CRS_TIMEOUT
+*            @arg @ref RCC_CRS_SYNCOK
+*            @arg @ref RCC_CRS_SYNCWARN
+*            @arg @ref RCC_CRS_SYNCERR
+*            @arg @ref RCC_CRS_SYNCMISS
+*            @arg @ref RCC_CRS_TRIMOVF
+*/
+uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
+{
+  uint32_t crsstatus = RCC_CRS_NONE;
+  uint32_t tickstart;
+
+  /* Get time-out */
+  tickstart = HAL_GetTick();
+
+  /* Wait for CRS flag or time-out detection */
+  do
+  {
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+      {
+        crsstatus = RCC_CRS_TIMEOUT;
+      }
+    }
+    /* Check CRS SYNCOK flag  */
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))
+    {
+      /* CRS SYNC event OK */
+      crsstatus |= RCC_CRS_SYNCOK;
+
+      /* Clear CRS SYNC event OK bit */
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);
+    }
+
+    /* Check CRS SYNCWARN flag  */
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))
+    {
+      /* CRS SYNC warning */
+      crsstatus |= RCC_CRS_SYNCWARN;
+
+      /* Clear CRS SYNCWARN bit */
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);
+    }
+
+    /* Check CRS TRIM overflow flag  */
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))
+    {
+      /* CRS SYNC Error */
+      crsstatus |= RCC_CRS_TRIMOVF;
+
+      /* Clear CRS Error bit */
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);
+    }
+
+    /* Check CRS Error flag  */
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))
+    {
+      /* CRS SYNC Error */
+      crsstatus |= RCC_CRS_SYNCERR;
+
+      /* Clear CRS Error bit */
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);
+    }
+
+    /* Check CRS SYNC Missed flag  */
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))
+    {
+      /* CRS SYNC Missed */
+      crsstatus |= RCC_CRS_SYNCMISS;
+
+      /* Clear CRS SYNC Missed bit */
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);
+    }
+
+    /* Check CRS Expected SYNC flag  */
+    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))
+    {
+      /* frequency error counter reached a zero value */
+      __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
+    }
+  } while(RCC_CRS_NONE == crsstatus);
+
+  return crsstatus;
+}
+
+/**
+  * @brief Handle the Clock Recovery System interrupt request.
+  * @retval None
+  */
+void HAL_RCCEx_CRS_IRQHandler(void)
+{
+  uint32_t crserror = RCC_CRS_NONE;
+  /* Get current IT flags and IT sources values */
+  uint32_t itflags = READ_REG(CRS->ISR);
+  uint32_t itsources = READ_REG(CRS->CR);
+
+  /* Check CRS SYNCOK flag  */
+  if(((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U))
+  {
+    /* Clear CRS SYNC event OK flag */
+    WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
+
+    /* user callback */
+    HAL_RCCEx_CRS_SyncOkCallback();
+  }
+  /* Check CRS SYNCWARN flag  */
+  else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U))
+  {
+    /* Clear CRS SYNCWARN flag */
+    WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
+
+    /* user callback */
+    HAL_RCCEx_CRS_SyncWarnCallback();
+  }
+  /* Check CRS Expected SYNC flag  */
+  else if(((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U))
+  {
+    /* frequency error counter reached a zero value */
+    WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
+
+    /* user callback */
+    HAL_RCCEx_CRS_ExpectedSyncCallback();
+  }
+  /* Check CRS Error flags  */
+  else
+  {
+    if(((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U))
+    {
+      if((itflags & RCC_CRS_FLAG_SYNCERR) != 0U)
+      {
+        crserror |= RCC_CRS_SYNCERR;
+      }
+      if((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U)
+      {
+        crserror |= RCC_CRS_SYNCMISS;
+      }
+      if((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U)
+      {
+        crserror |= RCC_CRS_TRIMOVF;
+      }
+
+      /* Clear CRS Error flags */
+      WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
+
+      /* user error callback */
+      HAL_RCCEx_CRS_ErrorCallback(crserror);
+    }
+  }
+}
+
+/**
+  * @brief  RCCEx Clock Recovery System SYNCOK interrupt callback.
+  * @retval none
+  */
+__weak void HAL_RCCEx_CRS_SyncOkCallback(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file
+   */
+}
+
+/**
+  * @brief  RCCEx Clock Recovery System SYNCWARN interrupt callback.
+  * @retval none
+  */
+__weak void HAL_RCCEx_CRS_SyncWarnCallback(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file
+   */
+}
+
+/**
+  * @brief  RCCEx Clock Recovery System Expected SYNC interrupt callback.
+  * @retval none
+  */
+__weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file
+   */
+}
+
+/**
+  * @brief  RCCEx Clock Recovery System Error interrupt callback.
+  * @param  Error Combination of Error status.
+  *         This parameter can be a combination of the following values:
+  *           @arg @ref RCC_CRS_SYNCERR
+  *           @arg @ref RCC_CRS_SYNCMISS
+  *           @arg @ref RCC_CRS_TRIMOVF
+  * @retval none
+  */
+__weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(Error);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file
+   */
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_Private_functions Private Functions
+ * @{
+ */
+/**
+  * @brief  Configure the PLL2 VCI,VCO ranges, multiplication and division factors and enable it
+  * @param  pll2: Pointer to an RCC_PLL2InitTypeDef structure that
+  *         contains the configuration parameters  as well as VCI, VCO clock ranges.
+  * @param  Divider  divider parameter to be updated
+  * @note   PLL2 is temporary disabled to apply new parameters
+  *
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider)
+{
+
+  uint32_t tickstart;
+  HAL_StatusTypeDef status = HAL_OK;
+  assert_param(IS_RCC_PLL2M_VALUE(pll2->PLL2M));
+  assert_param(IS_RCC_PLL2N_VALUE(pll2->PLL2N));
+  assert_param(IS_RCC_PLL2P_VALUE(pll2->PLL2P));
+  assert_param(IS_RCC_PLL2R_VALUE(pll2->PLL2R));
+  assert_param(IS_RCC_PLL2Q_VALUE(pll2->PLL2Q));
+  assert_param(IS_RCC_PLL2RGE_VALUE(pll2->PLL2RGE));
+  assert_param(IS_RCC_PLL2VCO_VALUE(pll2->PLL2VCOSEL));
+  assert_param(IS_RCC_PLLFRACN_VALUE(pll2->PLL2FRACN));
+
+  /* Check that PLL2 OSC clock source is already set */
+  if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
+  {
+    return HAL_ERROR;
+  }
+
+
+  else
+  {
+    /* Disable  PLL2. */
+    __HAL_RCC_PLL2_DISABLE();
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+
+    /* Wait till PLL is disabled */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U)
+    {
+      if( (HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Configure PLL2 multiplication and division factors. */
+    __HAL_RCC_PLL2_CONFIG(pll2->PLL2M,
+                          pll2->PLL2N,
+                          pll2->PLL2P,
+                          pll2->PLL2Q,
+                          pll2->PLL2R);
+
+    /* Select PLL2 input reference frequency range: VCI */
+    __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE) ;
+
+    /* Select PLL2 output frequency range : VCO */
+    __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ;
+
+    /* Disable PLL2FRACN . */
+    __HAL_RCC_PLL2FRACN_DISABLE();
+
+    /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */
+    __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN);
+
+    /* Enable PLL2FRACN . */
+    __HAL_RCC_PLL2FRACN_ENABLE();
+
+    /* Enable the PLL2 clock output */
+    if(Divider == DIVIDER_P_UPDATE)
+    {
+      __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP);
+    }
+    else if(Divider == DIVIDER_Q_UPDATE)
+    {
+      __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ);
+    }
+    else
+    {
+      __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR);
+    }
+
+    /* Enable  PLL2. */
+    __HAL_RCC_PLL2_ENABLE();
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+
+    /* Wait till PLL2 is ready */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U)
+    {
+      if( (HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+
+  }
+
+
+  return status;
+}
+
+
+/**
+  * @brief  Configure the PLL3 VCI,VCO ranges, multiplication and division factors and enable it
+  * @param  pll3: Pointer to an RCC_PLL3InitTypeDef structure that
+  *         contains the configuration parameters  as well as VCI, VCO clock ranges.
+  * @param  Divider  divider parameter to be updated
+  * @note   PLL3 is temporary disabled to apply new parameters
+  *
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider)
+{
+  uint32_t tickstart;
+  HAL_StatusTypeDef status = HAL_OK;
+  assert_param(IS_RCC_PLL3M_VALUE(pll3->PLL3M));
+  assert_param(IS_RCC_PLL3N_VALUE(pll3->PLL3N));
+  assert_param(IS_RCC_PLL3P_VALUE(pll3->PLL3P));
+  assert_param(IS_RCC_PLL3R_VALUE(pll3->PLL3R));
+  assert_param(IS_RCC_PLL3Q_VALUE(pll3->PLL3Q));
+  assert_param(IS_RCC_PLL3RGE_VALUE(pll3->PLL3RGE));
+  assert_param(IS_RCC_PLL3VCO_VALUE(pll3->PLL3VCOSEL));
+  assert_param(IS_RCC_PLLFRACN_VALUE(pll3->PLL3FRACN));
+
+  /* Check that PLL3 OSC clock source is already set */
+  if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
+  {
+    return HAL_ERROR;
+  }
+
+
+  else
+  {
+    /* Disable  PLL3. */
+    __HAL_RCC_PLL3_DISABLE();
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+    /* Wait till PLL3 is ready */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U)
+    {
+      if( (HAL_GetTick() - tickstart ) > PLL3_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Configure the PLL3  multiplication and division factors. */
+    __HAL_RCC_PLL3_CONFIG(pll3->PLL3M,
+                          pll3->PLL3N,
+                          pll3->PLL3P,
+                          pll3->PLL3Q,
+                          pll3->PLL3R);
+
+    /* Select PLL3 input reference frequency range: VCI */
+    __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ;
+
+    /* Select PLL3 output frequency range : VCO */
+    __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ;
+
+    /* Disable PLL3FRACN . */
+    __HAL_RCC_PLL3FRACN_DISABLE();
+
+    /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */
+    __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN);
+
+    /* Enable PLL3FRACN . */
+    __HAL_RCC_PLL3FRACN_ENABLE();
+
+    /* Enable the PLL3 clock output */
+    if(Divider == DIVIDER_P_UPDATE)
+    {
+      __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP);
+    }
+    else if(Divider == DIVIDER_Q_UPDATE)
+    {
+      __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
+    }
+    else
+    {
+      __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
+    }
+
+    /* Enable  PLL3. */
+    __HAL_RCC_PLL3_ENABLE();
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+
+    /* Wait till PLL3 is ready */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U)
+    {
+      if( (HAL_GetTick() - tickstart ) > PLL3_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+
+  }
+
+
+  return status;
+}
+
+/**
+  * @brief Handle the RCC LSE Clock Security System interrupt request.
+  * @retval None
+  */
+void HAL_RCCEx_LSECSS_IRQHandler(void)
+{
+  /* Check RCC LSE CSSF flag  */
+  if(__HAL_RCC_GET_IT(RCC_IT_LSECSS))
+  {
+
+    /* Clear RCC LSE CSS pending bit */
+    __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS);
+
+    /* RCC LSE Clock Security System interrupt user callback */
+    HAL_RCCEx_LSECSS_Callback();
+
+  }
+}
+
+/**
+  * @brief  RCCEx LSE Clock Security System interrupt callback.
+  * @retval none
+  */
+__weak void HAL_RCCEx_LSECSS_Callback(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file
+   */
+}
+
+
+
+/**
+  * @}
+  */
+
+#endif /* HAL_RCC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c
new file mode 100644
index 00000000..1885d04b
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c
@@ -0,0 +1,7047 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_tim.c
+  * @author  MCD Application Team
+  * @brief   TIM HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Timer (TIM) peripheral:
+  *           + TIM Time Base Initialization
+  *           + TIM Time Base Start
+  *           + TIM Time Base Start Interruption
+  *           + TIM Time Base Start DMA
+  *           + TIM Output Compare/PWM Initialization
+  *           + TIM Output Compare/PWM Channel Configuration
+  *           + TIM Output Compare/PWM  Start
+  *           + TIM Output Compare/PWM  Start Interruption
+  *           + TIM Output Compare/PWM Start DMA
+  *           + TIM Input Capture Initialization
+  *           + TIM Input Capture Channel Configuration
+  *           + TIM Input Capture Start
+  *           + TIM Input Capture Start Interruption
+  *           + TIM Input Capture Start DMA
+  *           + TIM One Pulse Initialization
+  *           + TIM One Pulse Channel Configuration
+  *           + TIM One Pulse Start
+  *           + TIM Encoder Interface Initialization
+  *           + TIM Encoder Interface Start
+  *           + TIM Encoder Interface Start Interruption
+  *           + TIM Encoder Interface Start DMA
+  *           + Commutation Event configuration with Interruption and DMA
+  *           + TIM OCRef clear configuration
+  *           + TIM External Clock configuration
+  @verbatim
+  ==============================================================================
+                      ##### TIMER Generic features #####
+  ==============================================================================
+  [..] The Timer features include:
+       (#) 16-bit up, down, up/down auto-reload counter.
+       (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
+           counter clock frequency either by any factor between 1 and 65536.
+       (#) Up to 4 independent channels for:
+           (++) Input Capture
+           (++) Output Compare
+           (++) PWM generation (Edge and Center-aligned Mode)
+           (++) One-pulse mode output
+       (#) Synchronization circuit to control the timer with external signals and to interconnect
+            several timers together.
+       (#) Supports incremental encoder for positioning purposes
+
+            ##### How to use this driver #####
+  ==============================================================================
+    [..]
+     (#) Initialize the TIM low level resources by implementing the following functions
+         depending on the selected feature:
+           (++) Time Base : HAL_TIM_Base_MspInit()
+           (++) Input Capture : HAL_TIM_IC_MspInit()
+           (++) Output Compare : HAL_TIM_OC_MspInit()
+           (++) PWM generation : HAL_TIM_PWM_MspInit()
+           (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
+           (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
+
+     (#) Initialize the TIM low level resources :
+        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
+        (##) TIM pins configuration
+            (+++) Enable the clock for the TIM GPIOs using the following function:
+             __HAL_RCC_GPIOx_CLK_ENABLE();
+            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
+
+     (#) The external Clock can be configured, if needed (the default clock is the
+         internal clock from the APBx), using the following function:
+         HAL_TIM_ConfigClockSource, the clock configuration should be done before
+         any start function.
+
+     (#) Configure the TIM in the desired functioning mode using one of the
+       Initialization function of this driver:
+       (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
+       (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
+            Output Compare signal.
+       (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
+            PWM signal.
+       (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
+            external signal.
+       (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
+            in One Pulse Mode.
+       (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
+
+     (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
+           (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
+           (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
+           (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
+           (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
+           (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
+           (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
+
+     (#) The DMA Burst is managed with the two following functions:
+         HAL_TIM_DMABurst_WriteStart()
+         HAL_TIM_DMABurst_ReadStart()
+
+    *** Callback registration ***
+  =============================================
+
+  [..]
+  The compilation define  USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
+  allows the user to configure dynamically the driver callbacks.
+
+  [..]
+  Use Function @ref HAL_TIM_RegisterCallback() to register a callback.
+  @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
+  the Callback ID and a pointer to the user callback function.
+
+  [..]
+  Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default
+  weak function.
+  @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
+  and the Callback ID.
+
+  [..]
+  These functions allow to register/unregister following callbacks:
+    (+) Base_MspInitCallback              : TIM Base Msp Init Callback.
+    (+) Base_MspDeInitCallback            : TIM Base Msp DeInit Callback.
+    (+) IC_MspInitCallback                : TIM IC Msp Init Callback.
+    (+) IC_MspDeInitCallback              : TIM IC Msp DeInit Callback.
+    (+) OC_MspInitCallback                : TIM OC Msp Init Callback.
+    (+) OC_MspDeInitCallback              : TIM OC Msp DeInit Callback.
+    (+) PWM_MspInitCallback               : TIM PWM Msp Init Callback.
+    (+) PWM_MspDeInitCallback             : TIM PWM Msp DeInit Callback.
+    (+) OnePulse_MspInitCallback          : TIM One Pulse Msp Init Callback.
+    (+) OnePulse_MspDeInitCallback        : TIM One Pulse Msp DeInit Callback.
+    (+) Encoder_MspInitCallback           : TIM Encoder Msp Init Callback.
+    (+) Encoder_MspDeInitCallback         : TIM Encoder Msp DeInit Callback.
+    (+) HallSensor_MspInitCallback        : TIM Hall Sensor Msp Init Callback.
+    (+) HallSensor_MspDeInitCallback      : TIM Hall Sensor Msp DeInit Callback.
+    (+) PeriodElapsedCallback             : TIM Period Elapsed Callback.
+    (+) PeriodElapsedHalfCpltCallback     : TIM Period Elapsed half complete Callback.
+    (+) TriggerCallback                   : TIM Trigger Callback.
+    (+) TriggerHalfCpltCallback           : TIM Trigger half complete Callback.
+    (+) IC_CaptureCallback                : TIM Input Capture Callback.
+    (+) IC_CaptureHalfCpltCallback        : TIM Input Capture half complete Callback.
+    (+) OC_DelayElapsedCallback           : TIM Output Compare Delay Elapsed Callback.
+    (+) PWM_PulseFinishedCallback         : TIM PWM Pulse Finished Callback.
+    (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
+    (+) ErrorCallback                     : TIM Error Callback.
+    (+) CommutationCallback               : TIM Commutation Callback.
+    (+) CommutationHalfCpltCallback       : TIM Commutation half complete Callback.
+    (+) BreakCallback                     : TIM Break Callback.
+    (+) Break2Callback                    : TIM Break2 Callback.
+
+  [..]
+By default, after the Init and when the state is HAL_TIM_STATE_RESET
+all interrupt callbacks are set to the corresponding weak functions:
+  examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().
+
+  [..]
+  Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
+  functionalities in the Init / DeInit only when these callbacks are null
+  (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
+    keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
+
+  [..]
+    Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
+    Exception done MspInit / MspDeInit that can be registered / unregistered
+    in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
+    thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
+  In that case first register the MspInit/MspDeInit user callbacks
+      using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.
+
+  [..]
+      When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
+      not defined, the callback registration feature is not available and all callbacks
+      are set to the corresponding weak functions.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup TIM TIM
+  * @brief TIM HAL module driver
+  * @{
+  */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup TIM_Private_Functions
+  * @{
+  */
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter);
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter);
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter);
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+                                                  TIM_SlaveConfigTypeDef *sSlaveConfig);
+/**
+  * @}
+  */
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup TIM_Exported_Functions TIM Exported Functions
+  * @{
+  */
+
+/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
+  *  @brief    Time Base functions
+  *
+@verbatim
+  ==============================================================================
+              ##### Time Base functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM base.
+    (+) De-initialize the TIM base.
+    (+) Start the Time Base.
+    (+) Stop the Time Base.
+    (+) Start the Time Base and enable interrupt.
+    (+) Stop the Time Base and disable interrupt.
+    (+) Start the Time Base and enable DMA transfer.
+    (+) Stop the Time Base and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Time base Unit according to the specified
+  *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->Base_MspInitCallback == NULL)
+    {
+      htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->Base_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    HAL_TIM_Base_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Set the Time Base configuration */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM Base peripheral
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->Base_MspDeInitCallback == NULL)
+  {
+    htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->Base_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIM_Base_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Base MSP.
+  * @param  htim TIM Base handle
+  * @retval None
+  */
+__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_Base_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Base MSP.
+  * @param  htim TIM Base handle
+  * @retval None
+  */
+__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_Base_MspDeInit could be implemented in the user file
+   */
+}
+
+
+/**
+  * @brief  Starts the TIM Base generation.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Change the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Base generation.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Base generation in interrupt mode.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  /* Enable the TIM Update interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Base generation in interrupt mode.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  /* Disable the TIM Update interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Base generation in DMA mode.
+  * @param  htim TIM Base handle
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if ((pData == NULL) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+  /* Set the DMA Period elapsed callbacks */
+  htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+  htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+
+  /* Set the DMA error callback */
+  htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+  /* Enable the DMA stream */
+  if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Enable the TIM Update DMA request */
+  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Base generation in DMA mode.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+
+  /* Disable the TIM Update DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
+
+  (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
+  *  @brief    TIM Output Compare functions
+  *
+@verbatim
+  ==============================================================================
+                  ##### TIM Output Compare functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM Output Compare.
+    (+) De-initialize the TIM Output Compare.
+    (+) Start the TIM Output Compare.
+    (+) Stop the TIM Output Compare.
+    (+) Start the TIM Output Compare and enable interrupt.
+    (+) Stop the TIM Output Compare and disable interrupt.
+    (+) Start the TIM Output Compare and enable DMA transfer.
+    (+) Stop the TIM Output Compare and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Output Compare according to the specified
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
+  * @param  htim TIM Output Compare handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->OC_MspInitCallback == NULL)
+    {
+      htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->OC_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_OC_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Init the base time for the Output Compare */
+  TIM_Base_SetConfig(htim->Instance,  &htim->Init);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM peripheral
+  * @param  htim TIM Output Compare handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->OC_MspDeInitCallback == NULL)
+  {
+    htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->OC_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+  HAL_TIM_OC_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Output Compare MSP.
+  * @param  htim TIM Output Compare handle
+  * @retval None
+  */
+__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OC_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Output Compare MSP.
+  * @param  htim TIM Output Compare handle
+  * @retval None
+  */
+__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OC_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Enable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in interrupt mode.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Enable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Enable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in interrupt mode.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Disable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in DMA mode.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if ((pData == NULL) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Enable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 4 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Enable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in DMA mode.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Disable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
+  *  @brief    TIM PWM functions
+  *
+@verbatim
+  ==============================================================================
+                          ##### TIM PWM functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM PWM.
+    (+) De-initialize the TIM PWM.
+    (+) Start the TIM PWM.
+    (+) Stop the TIM PWM.
+    (+) Start the TIM PWM and enable interrupt.
+    (+) Stop the TIM PWM and disable interrupt.
+    (+) Start the TIM PWM and enable DMA transfer.
+    (+) Stop the TIM PWM and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM PWM Time Base according to the specified
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
+  * @param  htim TIM PWM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->PWM_MspInitCallback == NULL)
+    {
+      htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->PWM_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_PWM_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Init the base time for the PWM */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM peripheral
+  * @param  htim TIM PWM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->PWM_MspDeInitCallback == NULL)
+  {
+    htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->PWM_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+  HAL_TIM_PWM_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM PWM MSP.
+  * @param  htim TIM PWM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM PWM MSP.
+  * @param  htim TIM PWM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the PWM signal generation.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Enable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the PWM signal generation.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the PWM signal generation in interrupt mode.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Enable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Enable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the PWM signal generation in interrupt mode.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Disable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM PWM signal generation in DMA mode.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if ((pData == NULL) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Output Capture/Compare 3 request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 4 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Enable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM PWM signal generation in DMA mode.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Disable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
+  *  @brief    TIM Input Capture functions
+  *
+@verbatim
+  ==============================================================================
+              ##### TIM Input Capture functions #####
+  ==============================================================================
+ [..]
+   This section provides functions allowing to:
+   (+) Initialize and configure the TIM Input Capture.
+   (+) De-initialize the TIM Input Capture.
+   (+) Start the TIM Input Capture.
+   (+) Stop the TIM Input Capture.
+   (+) Start the TIM Input Capture and enable interrupt.
+   (+) Stop the TIM Input Capture and disable interrupt.
+   (+) Start the TIM Input Capture and enable DMA transfer.
+   (+) Stop the TIM Input Capture and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Input Capture Time base according to the specified
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
+  * @param  htim TIM Input Capture handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->IC_MspInitCallback == NULL)
+    {
+      htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->IC_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_IC_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Init the base time for the input capture */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM peripheral
+  * @param  htim TIM Input Capture handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->IC_MspDeInitCallback == NULL)
+  {
+    htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->IC_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+  HAL_TIM_IC_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Input Capture MSP.
+  * @param  htim TIM Input Capture handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Input Capture MSP.
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Input Capture measurement.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Enable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Input Capture measurement.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Input Capture measurement in interrupt mode.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Enable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      break;
+  }
+  /* Enable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Input Capture measurement in interrupt mode.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Disable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Input Capture measurement in DMA mode.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  pData The destination Buffer address.
+  * @param  Length The length of data to be transferred from TIM peripheral to memory.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if ((pData == NULL) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 2  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 3  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 4  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Enable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Input Capture measurement in DMA mode.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3  DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4  DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Disable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
+  *  @brief    TIM One Pulse functions
+  *
+@verbatim
+  ==============================================================================
+                        ##### TIM One Pulse functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM One Pulse.
+    (+) De-initialize the TIM One Pulse.
+    (+) Start the TIM One Pulse.
+    (+) Stop the TIM One Pulse.
+    (+) Start the TIM One Pulse and enable interrupt.
+    (+) Stop the TIM One Pulse and disable interrupt.
+    (+) Start the TIM One Pulse and enable DMA transfer.
+    (+) Stop the TIM One Pulse and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM One Pulse Time Base according to the specified
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
+  * @param  htim TIM One Pulse handle
+  * @param  OnePulseMode Select the One pulse mode.
+  *         This parameter can be one of the following values:
+  *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
+  *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_OPM_MODE(OnePulseMode));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->OnePulse_MspInitCallback == NULL)
+    {
+      htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->OnePulse_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_OnePulse_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Configure the Time base in the One Pulse Mode */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Reset the OPM Bit */
+  htim->Instance->CR1 &= ~TIM_CR1_OPM;
+
+  /* Configure the OPM Mode */
+  htim->Instance->CR1 |= OnePulseMode;
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM One Pulse
+  * @param  htim TIM One Pulse handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->OnePulse_MspDeInitCallback == NULL)
+  {
+    htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->OnePulse_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIM_OnePulse_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM One Pulse MSP.
+  * @param  htim TIM One Pulse handle
+  * @retval None
+  */
+__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OnePulse_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM One Pulse MSP.
+  * @param  htim TIM One Pulse handle
+  * @retval None
+  */
+__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation.
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Enable the Capture compare and the Input Capture channels
+    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+    in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+
+    No need to enable the counter, it's enabled automatically by hardware
+    (the counter starts in response to a stimulus and generate a pulse */
+
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM One Pulse signal generation.
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channels to be disable
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Disable the Capture compare and the Input Capture channels
+  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+  in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation in interrupt mode.
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Enable the Capture compare and the Input Capture channels
+    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+    in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+
+    No need to enable the counter, it's enabled automatically by hardware
+    (the counter starts in response to a stimulus and generate a pulse */
+
+  /* Enable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+  /* Enable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Enable the main output */
+    __HAL_TIM_MOE_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM One Pulse signal generation in interrupt mode.
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Disable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+  /* Disable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+
+  /* Disable the Capture compare and the Input Capture channels
+  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+  in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  {
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
+  *  @brief    TIM Encoder functions
+  *
+@verbatim
+  ==============================================================================
+                          ##### TIM Encoder functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM Encoder.
+    (+) De-initialize the TIM Encoder.
+    (+) Start the TIM Encoder.
+    (+) Stop the TIM Encoder.
+    (+) Start the TIM Encoder and enable interrupt.
+    (+) Stop the TIM Encoder and disable interrupt.
+    (+) Start the TIM Encoder and enable DMA transfer.
+    (+) Stop the TIM Encoder and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Encoder Interface and initialize the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
+  * @note   Encoder mode and External clock mode 2 are not compatible and must not be selected together
+  *         Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
+  *         using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
+  * @param  htim TIM Encoder Interface handle
+  * @param  sConfig TIM Encoder Interface configuration structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef *sConfig)
+{
+  uint32_t tmpsmcr;
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+  assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
+  assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
+  assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
+  assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
+  assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
+  assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+  assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->Encoder_MspInitCallback == NULL)
+    {
+      htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->Encoder_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_Encoder_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Reset the SMS and ECE bits */
+  htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
+
+  /* Configure the Time base in the Encoder Mode */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = htim->Instance->SMCR;
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmr1 = htim->Instance->CCMR1;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = htim->Instance->CCER;
+
+  /* Set the encoder Mode */
+  tmpsmcr |= sConfig->EncoderMode;
+
+  /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+  tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
+  tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
+
+  /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
+  tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
+  tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
+  tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
+  tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
+
+  /* Set the TI1 and the TI2 Polarities */
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
+  tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
+  tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
+
+  /* Write to TIMx SMCR */
+  htim->Instance->SMCR = tmpsmcr;
+
+  /* Write to TIMx CCMR1 */
+  htim->Instance->CCMR1 = tmpccmr1;
+
+  /* Write to TIMx CCER */
+  htim->Instance->CCER = tmpccer;
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  DeInitializes the TIM Encoder interface
+  * @param  htim TIM Encoder Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->Encoder_MspDeInitCallback == NULL)
+  {
+    htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->Encoder_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIM_Encoder_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Encoder Interface MSP.
+  * @param  htim TIM Encoder Interface handle
+  * @retval None
+  */
+__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_Encoder_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Encoder Interface MSP.
+  * @param  htim TIM Encoder Interface handle
+  * @retval None
+  */
+__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Encoder Interface.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Enable the encoder interface channels */
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      break;
+    }
+
+    default :
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      break;
+    }
+  }
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Encoder Interface.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channels 1 and 2
+    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+      break;
+    }
+
+    default :
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+      break;
+    }
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Encoder Interface in interrupt mode.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Enable the encoder interface channels */
+  /* Enable the capture compare Interrupts 1 and/or 2 */
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    default :
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+  }
+
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Encoder Interface in interrupt mode.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channels 1 and 2
+    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+  if (Channel == TIM_CHANNEL_1)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare Interrupts 1 */
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare Interrupts 2 */
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+  }
+  else
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare Interrupts 1 and 2 */
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Encoder Interface in DMA mode.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @param  pData1 The destination Buffer address for IC1.
+  * @param  pData2 The destination Buffer address for IC2.
+  * @param  Length The length of data to be transferred from TIM peripheral to memory.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
+                                            uint32_t *pData2, uint16_t Length)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Input Capture DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+
+      /* Enable the Peripheral */
+      __HAL_TIM_ENABLE(htim);
+
+      /* Enable the Capture compare channel */
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Input Capture  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+
+      /* Enable the Peripheral */
+      __HAL_TIM_ENABLE(htim);
+
+      /* Enable the Capture compare channel */
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      break;
+    }
+
+    case TIM_CHANNEL_ALL:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the Peripheral */
+      __HAL_TIM_ENABLE(htim);
+
+      /* Enable the Capture compare channel */
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+      /* Enable the TIM Input Capture  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      /* Enable the TIM Input Capture  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    default:
+      break;
+  }
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Encoder Interface in DMA mode.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channels 1 and 2
+    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+  if (Channel == TIM_CHANNEL_1)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare DMA Request 1 */
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare DMA Request 2 */
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+  }
+  else
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare DMA Request 1 and 2 */
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
+  *  @brief    TIM IRQ handler management
+  *
+@verbatim
+  ==============================================================================
+                        ##### IRQ handler management #####
+  ==============================================================================
+  [..]
+    This section provides Timer IRQ handler function.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  This function handles TIM interrupts requests.
+  * @param  htim TIM  handle
+  * @retval None
+  */
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
+{
+  /* Capture compare 1 event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
+    {
+      {
+        __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
+        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+        /* Input capture event */
+        if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
+        {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+          htim->IC_CaptureCallback(htim);
+#else
+          HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+        }
+        /* Output compare event */
+        else
+        {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+          htim->OC_DelayElapsedCallback(htim);
+          htim->PWM_PulseFinishedCallback(htim);
+#else
+          HAL_TIM_OC_DelayElapsedCallback(htim);
+          HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+        }
+        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+      }
+    }
+  }
+  /* Capture compare 2 event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+      /* Input capture event */
+      if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->IC_CaptureCallback(htim);
+#else
+        HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      /* Output compare event */
+      else
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->OC_DelayElapsedCallback(htim);
+        htim->PWM_PulseFinishedCallback(htim);
+#else
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+    }
+  }
+  /* Capture compare 3 event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+      /* Input capture event */
+      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->IC_CaptureCallback(htim);
+#else
+        HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      /* Output compare event */
+      else
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->OC_DelayElapsedCallback(htim);
+        htim->PWM_PulseFinishedCallback(htim);
+#else
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+    }
+  }
+  /* Capture compare 4 event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+      /* Input capture event */
+      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->IC_CaptureCallback(htim);
+#else
+        HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      /* Output compare event */
+      else
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->OC_DelayElapsedCallback(htim);
+        htim->PWM_PulseFinishedCallback(htim);
+#else
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+    }
+  }
+  /* TIM Update event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->PeriodElapsedCallback(htim);
+#else
+      HAL_TIM_PeriodElapsedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM Break input event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->BreakCallback(htim);
+#else
+      HAL_TIMEx_BreakCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM Break2 input event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->Break2Callback(htim);
+#else
+      HAL_TIMEx_Break2Callback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM Trigger detection event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->TriggerCallback(htim);
+#else
+      HAL_TIM_TriggerCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM commutation event */
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
+  {
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
+    {
+      __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->CommutationCallback(htim);
+#else
+      HAL_TIMEx_CommutCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
+  *  @brief    TIM Peripheral Control functions
+  *
+@verbatim
+  ==============================================================================
+                   ##### Peripheral Control functions #####
+  ==============================================================================
+ [..]
+   This section provides functions allowing to:
+      (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
+      (+) Configure External Clock source.
+      (+) Configure Complementary channels, break features and dead time.
+      (+) Configure Master and the Slave synchronization.
+      (+) Configure the DMA Burst Mode.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the TIM Output Compare Channels according to the specified
+  *         parameters in the TIM_OC_InitTypeDef.
+  * @param  htim TIM Output Compare handle
+  * @param  sConfig TIM Output Compare configuration structure
+  * @param  Channel TIM Channels to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
+                                           TIM_OC_InitTypeDef *sConfig,
+                                           uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CHANNELS(Channel));
+  assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
+  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 1 in Output Compare */
+      TIM_OC1_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 2 in Output Compare */
+      TIM_OC2_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 3 in Output Compare */
+      TIM_OC3_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 4 in Output Compare */
+      TIM_OC4_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    case TIM_CHANNEL_5:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 5 in Output Compare */
+      TIM_OC5_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    case TIM_CHANNEL_6:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 6 in Output Compare */
+      TIM_OC6_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Input Capture Channels according to the specified
+  *         parameters in the TIM_IC_InitTypeDef.
+  * @param  htim TIM IC handle
+  * @param  sConfig TIM Input Capture configuration structure
+  * @param  Channel TIM Channel to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
+  assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
+  assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  if (Channel == TIM_CHANNEL_1)
+  {
+    /* TI1 Configuration */
+    TIM_TI1_SetConfig(htim->Instance,
+                      sConfig->ICPolarity,
+                      sConfig->ICSelection,
+                      sConfig->ICFilter);
+
+    /* Reset the IC1PSC Bits */
+    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+
+    /* Set the IC1PSC value */
+    htim->Instance->CCMR1 |= sConfig->ICPrescaler;
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    /* TI2 Configuration */
+    assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+    TIM_TI2_SetConfig(htim->Instance,
+                      sConfig->ICPolarity,
+                      sConfig->ICSelection,
+                      sConfig->ICFilter);
+
+    /* Reset the IC2PSC Bits */
+    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+    /* Set the IC2PSC value */
+    htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
+  }
+  else if (Channel == TIM_CHANNEL_3)
+  {
+    /* TI3 Configuration */
+    assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+    TIM_TI3_SetConfig(htim->Instance,
+                      sConfig->ICPolarity,
+                      sConfig->ICSelection,
+                      sConfig->ICFilter);
+
+    /* Reset the IC3PSC Bits */
+    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
+
+    /* Set the IC3PSC value */
+    htim->Instance->CCMR2 |= sConfig->ICPrescaler;
+  }
+  else
+  {
+    /* TI4 Configuration */
+    assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+    TIM_TI4_SetConfig(htim->Instance,
+                      sConfig->ICPolarity,
+                      sConfig->ICSelection,
+                      sConfig->ICFilter);
+
+    /* Reset the IC4PSC Bits */
+    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
+
+    /* Set the IC4PSC value */
+    htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
+  }
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM PWM  channels according to the specified
+  *         parameters in the TIM_OC_InitTypeDef.
+  * @param  htim TIM PWM handle
+  * @param  sConfig TIM PWM configuration structure
+  * @param  Channel TIM Channels to be configured
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
+                                            TIM_OC_InitTypeDef *sConfig,
+                                            uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CHANNELS(Channel));
+  assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
+  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+  assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 1 in PWM mode */
+      TIM_OC1_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel1 */
+      htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
+      htim->Instance->CCMR1 |= sConfig->OCFastMode;
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 2 in PWM mode */
+      TIM_OC2_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel2 */
+      htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
+      htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 3 in PWM mode */
+      TIM_OC3_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel3 */
+      htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
+      htim->Instance->CCMR2 |= sConfig->OCFastMode;
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 4 in PWM mode */
+      TIM_OC4_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel4 */
+      htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
+      htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
+      break;
+    }
+
+    case TIM_CHANNEL_5:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 5 in PWM mode */
+      TIM_OC5_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel5*/
+      htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
+      htim->Instance->CCMR3 |= sConfig->OCFastMode;
+      break;
+    }
+
+    case TIM_CHANNEL_6:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 6 in PWM mode */
+      TIM_OC6_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel6 */
+      htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
+      htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM One Pulse Channels according to the specified
+  *         parameters in the TIM_OnePulse_InitTypeDef.
+  * @param  htim TIM One Pulse handle
+  * @param  sConfig TIM One Pulse configuration structure
+  * @param  OutputChannel TIM output channel to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @param  InputChannel TIM input Channel to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @note  To output a waveform with a minimum delay user can enable the fast
+  *        mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
+  *        output is forced in response to the edge detection on TIx input,
+  *        without taking in account the comparison.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef *sConfig,
+                                                 uint32_t OutputChannel,  uint32_t InputChannel)
+{
+  TIM_OC_InitTypeDef temp1;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
+  assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
+
+  if (OutputChannel != InputChannel)
+  {
+    /* Process Locked */
+    __HAL_LOCK(htim);
+
+    htim->State = HAL_TIM_STATE_BUSY;
+
+    /* Extract the Output compare configuration from sConfig structure */
+    temp1.OCMode = sConfig->OCMode;
+    temp1.Pulse = sConfig->Pulse;
+    temp1.OCPolarity = sConfig->OCPolarity;
+    temp1.OCNPolarity = sConfig->OCNPolarity;
+    temp1.OCIdleState = sConfig->OCIdleState;
+    temp1.OCNIdleState = sConfig->OCNIdleState;
+
+    switch (OutputChannel)
+    {
+      case TIM_CHANNEL_1:
+      {
+        assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+        TIM_OC1_SetConfig(htim->Instance, &temp1);
+        break;
+      }
+      case TIM_CHANNEL_2:
+      {
+        assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+        TIM_OC2_SetConfig(htim->Instance, &temp1);
+        break;
+      }
+      default:
+        break;
+    }
+
+    switch (InputChannel)
+    {
+      case TIM_CHANNEL_1:
+      {
+        assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+        TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
+                          sConfig->ICSelection, sConfig->ICFilter);
+
+        /* Reset the IC1PSC Bits */
+        htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+
+        /* Select the Trigger source */
+        htim->Instance->SMCR &= ~TIM_SMCR_TS;
+        htim->Instance->SMCR |= TIM_TS_TI1FP1;
+
+        /* Select the Slave Mode */
+        htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+        htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+        break;
+      }
+      case TIM_CHANNEL_2:
+      {
+        assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+        TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
+                          sConfig->ICSelection, sConfig->ICFilter);
+
+        /* Reset the IC2PSC Bits */
+        htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+        /* Select the Trigger source */
+        htim->Instance->SMCR &= ~TIM_SMCR_TS;
+        htim->Instance->SMCR |= TIM_TS_TI2FP2;
+
+        /* Select the Slave Mode */
+        htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+        htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+        break;
+      }
+
+      default:
+        break;
+    }
+
+    htim->State = HAL_TIM_STATE_READY;
+
+    __HAL_UNLOCK(htim);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data write
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMABASE_CR1
+  *            @arg TIM_DMABASE_CR2
+  *            @arg TIM_DMABASE_SMCR
+  *            @arg TIM_DMABASE_DIER
+  *            @arg TIM_DMABASE_SR
+  *            @arg TIM_DMABASE_EGR
+  *            @arg TIM_DMABASE_CCMR1
+  *            @arg TIM_DMABASE_CCMR2
+  *            @arg TIM_DMABASE_CCER
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
+  *            @arg TIM_DMABASE_ARR
+  *            @arg TIM_DMABASE_RCR
+  *            @arg TIM_DMABASE_CCR1
+  *            @arg TIM_DMABASE_CCR2
+  *            @arg TIM_DMABASE_CCR3
+  *            @arg TIM_DMABASE_CCR4
+  *            @arg TIM_DMABASE_BDTR
+  *            @arg TIM_DMABASE_CCMR3 
+  *            @arg TIM_DMABASE_CCR5 
+  *            @arg TIM_DMABASE_CCR6 
+  *            @arg TIM_DMABASE_AF1  
+  *            @arg TIM_DMABASE_AF2  
+  *            @arg TIM_DMABASE_TISEL
+  *         
+  * @param  BurstRequestSrc TIM DMA Request sources
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+  * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                              uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t  BurstLength)
+{
+  return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+                                          ((BurstLength) >> 8U) + 1U);
+}
+
+/**
+  * @brief  Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA will start the Data write
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMABASE_CR1
+  *            @arg TIM_DMABASE_CR2
+  *            @arg TIM_DMABASE_SMCR
+  *            @arg TIM_DMABASE_DIER
+  *            @arg TIM_DMABASE_SR
+  *            @arg TIM_DMABASE_EGR
+  *            @arg TIM_DMABASE_CCMR1
+  *            @arg TIM_DMABASE_CCMR2
+  *            @arg TIM_DMABASE_CCER
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
+  *            @arg TIM_DMABASE_ARR
+  *            @arg TIM_DMABASE_RCR
+  *            @arg TIM_DMABASE_CCR1
+  *            @arg TIM_DMABASE_CCR2
+  *            @arg TIM_DMABASE_CCR3
+  *            @arg TIM_DMABASE_CCR4
+  *            @arg TIM_DMABASE_BDTR
+  *            @arg TIM_DMABASE_CCMR3 
+  *            @arg TIM_DMABASE_CCR5 
+  *            @arg TIM_DMABASE_CCR6 
+  *            @arg TIM_DMABASE_AF1  
+  *            @arg TIM_DMABASE_AF2  
+  *            @arg TIM_DMABASE_TISEL
+  *         
+  * @param  BurstRequestSrc TIM DMA Request sources
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+  * @param  DataLength Data length. This parameter can be one value
+  *         between 1 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                                   uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
+                                                   uint32_t  BurstLength,  uint32_t  DataLength)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+  assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+  assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if ((BurstBuffer == NULL) && (BurstLength > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+  switch (BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      /* Set the DMA Period elapsed callbacks */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC4:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_COM:
+    {
+      /* Set the DMA commutation callbacks */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_TRIGGER:
+    {
+      /* Set the DMA trigger callbacks */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    default:
+      break;
+  }
+
+  /* Configure the DMA Burst Mode */
+  htim->Instance->DCR = (BurstBaseAddress | BurstLength);
+  /* Enable the TIM DMA Request */
+  __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM DMA Burst mode
+  * @param  htim TIM handle
+  * @param  BurstRequestSrc TIM DMA Request sources to disable
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+
+  /* Abort the DMA transfer (at least disable the DMA stream) */
+  switch (BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+      break;
+    }
+    case TIM_DMA_CC1:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+    case TIM_DMA_CC2:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+    case TIM_DMA_CC3:
+    {
+      status =  HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+    case TIM_DMA_CC4:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+    case TIM_DMA_COM:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+      break;
+    }
+    case TIM_DMA_TRIGGER:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+      break;
+    }
+    default:
+      break;
+  }
+
+  if (HAL_OK == status)
+  {
+    /* Disable the TIM Update DMA request */
+    __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMABASE_CR1
+  *            @arg TIM_DMABASE_CR2
+  *            @arg TIM_DMABASE_SMCR
+  *            @arg TIM_DMABASE_DIER
+  *            @arg TIM_DMABASE_SR
+  *            @arg TIM_DMABASE_EGR
+  *            @arg TIM_DMABASE_CCMR1
+  *            @arg TIM_DMABASE_CCMR2
+  *            @arg TIM_DMABASE_CCER
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
+  *            @arg TIM_DMABASE_ARR
+  *            @arg TIM_DMABASE_RCR
+  *            @arg TIM_DMABASE_CCR1
+  *            @arg TIM_DMABASE_CCR2
+  *            @arg TIM_DMABASE_CCR3
+  *            @arg TIM_DMABASE_CCR4
+  *            @arg TIM_DMABASE_BDTR
+  *            @arg TIM_DMABASE_CCMR3 
+  *            @arg TIM_DMABASE_CCR5 
+  *            @arg TIM_DMABASE_CCR6 
+  *            @arg TIM_DMABASE_AF1  
+  *            @arg TIM_DMABASE_AF2  
+  *            @arg TIM_DMABASE_TISEL
+  *         
+  * @param  BurstRequestSrc TIM DMA Request sources
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+  * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                             uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength)
+{
+  return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+                                         ((BurstLength) >> 8U) + 1U);
+}
+
+/**
+  * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMABASE_CR1
+  *            @arg TIM_DMABASE_CR2
+  *            @arg TIM_DMABASE_SMCR
+  *            @arg TIM_DMABASE_DIER
+  *            @arg TIM_DMABASE_SR
+  *            @arg TIM_DMABASE_EGR
+  *            @arg TIM_DMABASE_CCMR1
+  *            @arg TIM_DMABASE_CCMR2
+  *            @arg TIM_DMABASE_CCER
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
+  *            @arg TIM_DMABASE_ARR
+  *            @arg TIM_DMABASE_RCR
+  *            @arg TIM_DMABASE_CCR1
+  *            @arg TIM_DMABASE_CCR2
+  *            @arg TIM_DMABASE_CCR3
+  *            @arg TIM_DMABASE_CCR4
+  *            @arg TIM_DMABASE_BDTR
+  *            @arg TIM_DMABASE_CCMR3 
+  *            @arg TIM_DMABASE_CCR5 
+  *            @arg TIM_DMABASE_CCR6 
+  *            @arg TIM_DMABASE_AF1  
+  *            @arg TIM_DMABASE_AF2  
+  *            @arg TIM_DMABASE_TISEL
+  *         
+  * @param  BurstRequestSrc TIM DMA Request sources
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+  * @param  DataLength Data length. This parameter can be one value
+  *         between 1 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                                  uint32_t BurstRequestSrc, uint32_t  *BurstBuffer,
+                                                  uint32_t  BurstLength, uint32_t  DataLength)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+  assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+  assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if ((BurstBuffer == NULL) && (BurstLength > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+  switch (BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      /* Set the DMA Period elapsed callbacks */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC1:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC2:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC3:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC4:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_COM:
+    {
+      /* Set the DMA commutation callbacks */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_TRIGGER:
+    {
+      /* Set the DMA trigger callbacks */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
+    }
+    default:
+      break;
+  }
+
+  /* Configure the DMA Burst Mode */
+  htim->Instance->DCR = (BurstBaseAddress | BurstLength);
+
+  /* Enable the TIM DMA Request */
+  __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the DMA burst reading
+  * @param  htim TIM handle
+  * @param  BurstRequestSrc TIM DMA Request sources to disable.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+
+  /* Abort the DMA transfer (at least disable the DMA stream) */
+  switch (BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+      break;
+    }
+    case TIM_DMA_CC1:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+    case TIM_DMA_CC2:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+    case TIM_DMA_CC3:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+    case TIM_DMA_CC4:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+    case TIM_DMA_COM:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+      break;
+    }
+    case TIM_DMA_TRIGGER:
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+      break;
+    }
+    default:
+      break;
+  }
+
+  if (HAL_OK == status)
+  {
+    /* Disable the TIM Update DMA request */
+    __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Generate a software event
+  * @param  htim TIM handle
+  * @param  EventSource specifies the event source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
+  *            @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
+  *            @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
+  *            @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
+  *            @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
+  *            @arg TIM_EVENTSOURCE_COM: Timer COM event source
+  *            @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
+  *            @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
+  *            @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
+  * @note   Basic timers can only generate an update event.
+  * @note   TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
+  * @note   TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant
+  *         only for timer instances supporting break input(s).
+  * @retval HAL status
+  */
+
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_EVENT_SOURCE(EventSource));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  /* Change the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Set the event sources */
+  htim->Instance->EGR = EventSource;
+
+  /* Change the TIM state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the OCRef clear feature
+  * @param  htim TIM handle
+  * @param  sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
+  *         contains the OCREF clear feature and parameters for the TIM peripheral.
+  * @param  Channel specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1
+  *            @arg TIM_CHANNEL_2: TIM Channel 2
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  *            @arg TIM_CHANNEL_4: TIM Channel 4
+  *            @arg TIM_CHANNEL_5: TIM Channel 5
+  *            @arg TIM_CHANNEL_6: TIM Channel 6
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
+                                           TIM_ClearInputConfigTypeDef *sClearInputConfig,
+                                           uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  switch (sClearInputConfig->ClearInputSource)
+  {
+    case TIM_CLEARINPUTSOURCE_NONE:
+    {
+      /* Clear the OCREF clear selection bit and the the ETR Bits */
+      CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
+      break;
+    }
+
+    case TIM_CLEARINPUTSOURCE_ETR:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
+      assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
+      assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
+
+      /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
+      if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
+      {
+        htim->State = HAL_TIM_STATE_READY;
+        __HAL_UNLOCK(htim);
+        return HAL_ERROR;
+      }
+
+      TIM_ETR_SetConfig(htim->Instance,
+                        sClearInputConfig->ClearInputPrescaler,
+                        sClearInputConfig->ClearInputPolarity,
+                        sClearInputConfig->ClearInputFilter);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+      {
+        /* Enable the OCREF clear feature for Channel 1 */
+        SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
+      }
+      else
+      {
+        /* Disable the OCREF clear feature for Channel 1 */
+        CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
+      }
+      break;
+    }
+    case TIM_CHANNEL_2:
+    {
+      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+      {
+        /* Enable the OCREF clear feature for Channel 2 */
+        SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
+      }
+      else
+      {
+        /* Disable the OCREF clear feature for Channel 2 */
+        CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
+      }
+      break;
+    }
+    case TIM_CHANNEL_3:
+    {
+      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+      {
+        /* Enable the OCREF clear feature for Channel 3 */
+        SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
+      }
+      else
+      {
+        /* Disable the OCREF clear feature for Channel 3 */
+        CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
+      }
+      break;
+    }
+    case TIM_CHANNEL_4:
+    {
+      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+      {
+        /* Enable the OCREF clear feature for Channel 4 */
+        SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
+      }
+      else
+      {
+        /* Disable the OCREF clear feature for Channel 4 */
+        CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
+      }
+      break;
+    }
+    case TIM_CHANNEL_5:
+    {
+      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+      {
+        /* Enable the OCREF clear feature for Channel 5 */
+        SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
+      }
+      else
+      {
+        /* Disable the OCREF clear feature for Channel 5 */
+        CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
+      }
+      break;
+    }
+    case TIM_CHANNEL_6:
+    {
+      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+      {
+        /* Enable the OCREF clear feature for Channel 6 */
+        SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
+      }
+      else
+      {
+        /* Disable the OCREF clear feature for Channel 6 */
+        CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
+      }
+      break;
+    }
+    default:
+      break;
+  }
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief   Configures the clock source to be used
+  * @param  htim TIM handle
+  * @param  sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
+  *         contains the clock source information for the TIM peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
+{
+  uint32_t tmpsmcr;
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
+
+  /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
+  tmpsmcr = htim->Instance->SMCR;
+  tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+  htim->Instance->SMCR = tmpsmcr;
+
+  switch (sClockSourceConfig->ClockSource)
+  {
+    case TIM_CLOCKSOURCE_INTERNAL:
+    {
+      assert_param(IS_TIM_INSTANCE(htim->Instance));
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_ETRMODE1:
+    {
+      /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
+      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
+
+      /* Check ETR input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      /* Configure the ETR Clock source */
+      TIM_ETR_SetConfig(htim->Instance,
+                        sClockSourceConfig->ClockPrescaler,
+                        sClockSourceConfig->ClockPolarity,
+                        sClockSourceConfig->ClockFilter);
+
+      /* Select the External clock mode1 and the ETRF trigger */
+      tmpsmcr = htim->Instance->SMCR;
+      tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
+      /* Write to TIMx SMCR */
+      htim->Instance->SMCR = tmpsmcr;
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_ETRMODE2:
+    {
+      /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
+      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
+
+      /* Check ETR input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      /* Configure the ETR Clock source */
+      TIM_ETR_SetConfig(htim->Instance,
+                        sClockSourceConfig->ClockPrescaler,
+                        sClockSourceConfig->ClockPolarity,
+                        sClockSourceConfig->ClockFilter);
+      /* Enable the External clock mode2 */
+      htim->Instance->SMCR |= TIM_SMCR_ECE;
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_TI1:
+    {
+      /* Check whether or not the timer instance supports external clock mode 1 */
+      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+      /* Check TI1 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI1_ConfigInputStage(htim->Instance,
+                               sClockSourceConfig->ClockPolarity,
+                               sClockSourceConfig->ClockFilter);
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_TI2:
+    {
+      /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
+      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+      /* Check TI2 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI2_ConfigInputStage(htim->Instance,
+                               sClockSourceConfig->ClockPolarity,
+                               sClockSourceConfig->ClockFilter);
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_TI1ED:
+    {
+      /* Check whether or not the timer instance supports external clock mode 1 */
+      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+      /* Check TI1 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI1_ConfigInputStage(htim->Instance,
+                               sClockSourceConfig->ClockPolarity,
+                               sClockSourceConfig->ClockFilter);
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_ITR0:
+    case TIM_CLOCKSOURCE_ITR1:
+    case TIM_CLOCKSOURCE_ITR2:
+    case TIM_CLOCKSOURCE_ITR3:
+    case TIM_CLOCKSOURCE_ITR4:
+    case TIM_CLOCKSOURCE_ITR5:
+    case TIM_CLOCKSOURCE_ITR6:
+    case TIM_CLOCKSOURCE_ITR7:
+    case TIM_CLOCKSOURCE_ITR8:
+    {
+      /* Check whether or not the timer instance supports internal trigger input */
+      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
+
+      TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
+      break;
+    }
+
+    default:
+      break;
+  }
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Selects the signal connected to the TI1 input: direct from CH1_input
+  *         or a XOR combination between CH1_input, CH2_input & CH3_input
+  * @param  htim TIM handle.
+  * @param  TI1_Selection Indicate whether or not channel 1 is connected to the
+  *         output of a XOR gate.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
+  *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
+  *            pins are connected to the TI1 input (XOR combination)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
+{
+  uint32_t tmpcr2;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = htim->Instance->CR2;
+
+  /* Reset the TI1 selection */
+  tmpcr2 &= ~TIM_CR2_TI1S;
+
+  /* Set the TI1 selection */
+  tmpcr2 |= TI1_Selection;
+
+  /* Write to TIMxCR2 */
+  htim->Instance->CR2 = tmpcr2;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the TIM in Slave mode
+  * @param  htim TIM handle.
+  * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
+  *         contains the selected trigger (internal trigger input, filtered
+  *         timer input or external trigger input) and the Slave mode
+  *         (Disable, Reset, Gated, Trigger, External clock mode 1).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+  assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
+  {
+    htim->State = HAL_TIM_STATE_READY;
+    __HAL_UNLOCK(htim);
+    return HAL_ERROR;
+  }
+
+  /* Disable Trigger Interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
+
+  /* Disable Trigger DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the TIM in Slave mode in interrupt mode
+  * @param  htim TIM handle.
+  * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
+  *         contains the selected trigger (internal trigger input, filtered
+  *         timer input or external trigger input) and the Slave mode
+  *         (Disable, Reset, Gated, Trigger, External clock mode 1).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
+                                                TIM_SlaveConfigTypeDef *sSlaveConfig)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+  assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
+  {
+    htim->State = HAL_TIM_STATE_READY;
+    __HAL_UNLOCK(htim);
+    return HAL_ERROR;
+  }
+
+  /* Enable Trigger Interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
+
+  /* Disable Trigger DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Read the captured value from Capture Compare unit
+  * @param  htim TIM handle.
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval Captured value
+  */
+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpreg = 0U;
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+      /* Return the capture 1 value */
+      tmpreg =  htim->Instance->CCR1;
+
+      break;
+    }
+    case TIM_CHANNEL_2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+      /* Return the capture 2 value */
+      tmpreg =   htim->Instance->CCR2;
+
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+      /* Return the capture 3 value */
+      tmpreg =   htim->Instance->CCR3;
+
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+      /* Return the capture 4 value */
+      tmpreg =   htim->Instance->CCR4;
+
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  return tmpreg;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
+  *  @brief    TIM Callbacks functions
+  *
+@verbatim
+  ==============================================================================
+                        ##### TIM Callbacks functions #####
+  ==============================================================================
+ [..]
+   This section provides TIM callback functions:
+   (+) TIM Period elapsed callback
+   (+) TIM Output Compare callback
+   (+) TIM Input capture callback
+   (+) TIM Trigger callback
+   (+) TIM Error callback
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Period elapsed callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Period elapsed half complete callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Output Compare callback in non-blocking mode
+  * @param  htim TIM OC handle
+  * @retval None
+  */
+__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Input Capture callback in non-blocking mode
+  * @param  htim TIM IC handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_CaptureCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Input Capture half complete callback in non-blocking mode
+  * @param  htim TIM IC handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  PWM Pulse finished callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  PWM Pulse finished half complete callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Hall Trigger detection callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_TriggerCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Hall Trigger detection half complete callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Timer error callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_ErrorCallback could be implemented in the user file
+   */
+}
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User TIM callback to be used instead of the weak predefined callback
+  * @param htim tim handle
+  * @param CallbackID ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
+  *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
+  *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
+  *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
+  *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
+  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
+  *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
+  *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
+  *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
+  *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
+  *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
+  *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
+  *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
+  *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
+  *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
+  *          @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
+  *          @param pCallback pointer to the callback function
+  *          @retval status
+  */
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
+                                           pTIM_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(htim);
+
+  if (htim->State == HAL_TIM_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_TIM_BASE_MSPINIT_CB_ID :
+        htim->Base_MspInitCallback                 = pCallback;
+        break;
+
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+        htim->Base_MspDeInitCallback               = pCallback;
+        break;
+
+      case HAL_TIM_IC_MSPINIT_CB_ID :
+        htim->IC_MspInitCallback                   = pCallback;
+        break;
+
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :
+        htim->IC_MspDeInitCallback                 = pCallback;
+        break;
+
+      case HAL_TIM_OC_MSPINIT_CB_ID :
+        htim->OC_MspInitCallback                   = pCallback;
+        break;
+
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :
+        htim->OC_MspDeInitCallback                 = pCallback;
+        break;
+
+      case HAL_TIM_PWM_MSPINIT_CB_ID :
+        htim->PWM_MspInitCallback                  = pCallback;
+        break;
+
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+        htim->PWM_MspDeInitCallback                = pCallback;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+        htim->OnePulse_MspInitCallback             = pCallback;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+        htim->OnePulse_MspDeInitCallback           = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+        htim->Encoder_MspInitCallback              = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+        htim->Encoder_MspDeInitCallback            = pCallback;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+        htim->HallSensor_MspInitCallback           = pCallback;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+        htim->HallSensor_MspDeInitCallback         = pCallback;
+        break;
+
+      case HAL_TIM_PERIOD_ELAPSED_CB_ID :
+        htim->PeriodElapsedCallback                = pCallback;
+        break;
+
+      case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
+        htim->PeriodElapsedHalfCpltCallback        = pCallback;
+        break;
+
+      case HAL_TIM_TRIGGER_CB_ID :
+        htim->TriggerCallback                      = pCallback;
+        break;
+
+      case HAL_TIM_TRIGGER_HALF_CB_ID :
+        htim->TriggerHalfCpltCallback              = pCallback;
+        break;
+
+      case HAL_TIM_IC_CAPTURE_CB_ID :
+        htim->IC_CaptureCallback                   = pCallback;
+        break;
+
+      case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
+        htim->IC_CaptureHalfCpltCallback           = pCallback;
+        break;
+
+      case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
+        htim->OC_DelayElapsedCallback              = pCallback;
+        break;
+
+      case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
+        htim->PWM_PulseFinishedCallback            = pCallback;
+        break;
+
+      case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
+        htim->PWM_PulseFinishedHalfCpltCallback    = pCallback;
+        break;
+
+      case HAL_TIM_ERROR_CB_ID :
+        htim->ErrorCallback                        = pCallback;
+        break;
+
+      case HAL_TIM_COMMUTATION_CB_ID :
+        htim->CommutationCallback                  = pCallback;
+        break;
+
+      case HAL_TIM_COMMUTATION_HALF_CB_ID :
+        htim->CommutationHalfCpltCallback          = pCallback;
+        break;
+
+      case HAL_TIM_BREAK_CB_ID :
+        htim->BreakCallback                        = pCallback;
+        break;
+
+      case HAL_TIM_BREAK2_CB_ID :
+        htim->Break2Callback                       = pCallback;
+        break;
+
+      default :
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_TIM_BASE_MSPINIT_CB_ID :
+        htim->Base_MspInitCallback         = pCallback;
+        break;
+
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+        htim->Base_MspDeInitCallback       = pCallback;
+        break;
+
+      case HAL_TIM_IC_MSPINIT_CB_ID :
+        htim->IC_MspInitCallback           = pCallback;
+        break;
+
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :
+        htim->IC_MspDeInitCallback         = pCallback;
+        break;
+
+      case HAL_TIM_OC_MSPINIT_CB_ID :
+        htim->OC_MspInitCallback           = pCallback;
+        break;
+
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :
+        htim->OC_MspDeInitCallback         = pCallback;
+        break;
+
+      case HAL_TIM_PWM_MSPINIT_CB_ID :
+        htim->PWM_MspInitCallback          = pCallback;
+        break;
+
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+        htim->PWM_MspDeInitCallback        = pCallback;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+        htim->OnePulse_MspInitCallback     = pCallback;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+        htim->OnePulse_MspDeInitCallback   = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+        htim->Encoder_MspInitCallback      = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+        htim->Encoder_MspDeInitCallback    = pCallback;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+        htim->HallSensor_MspInitCallback   = pCallback;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+        htim->HallSensor_MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a TIM callback
+  *         TIM callback is redirected to the weak predefined callback
+  * @param htim tim handle
+  * @param CallbackID ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
+  *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
+  *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
+  *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
+  *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
+  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
+  *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
+  *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
+  *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
+  *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
+  *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
+  *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
+  *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
+  *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
+  *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
+  *          @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
+  *          @retval status
+  */
+HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(htim);
+
+  if (htim->State == HAL_TIM_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_TIM_BASE_MSPINIT_CB_ID :
+        htim->Base_MspInitCallback              = HAL_TIM_Base_MspInit;                      /* Legacy weak Base MspInit Callback */
+        break;
+
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+        htim->Base_MspDeInitCallback            = HAL_TIM_Base_MspDeInit;                    /* Legacy weak Base Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_IC_MSPINIT_CB_ID :
+        htim->IC_MspInitCallback                = HAL_TIM_IC_MspInit;                        /* Legacy weak IC Msp Init Callback */
+        break;
+
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :
+        htim->IC_MspDeInitCallback              = HAL_TIM_IC_MspDeInit;                      /* Legacy weak IC Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_OC_MSPINIT_CB_ID :
+        htim->OC_MspInitCallback                = HAL_TIM_OC_MspInit;                        /* Legacy weak OC Msp Init Callback */
+        break;
+
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :
+        htim->OC_MspDeInitCallback              = HAL_TIM_OC_MspDeInit;                      /* Legacy weak OC Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_PWM_MSPINIT_CB_ID :
+        htim->PWM_MspInitCallback               = HAL_TIM_PWM_MspInit;                       /* Legacy weak PWM Msp Init Callback */
+        break;
+
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+        htim->PWM_MspDeInitCallback             = HAL_TIM_PWM_MspDeInit;                     /* Legacy weak PWM Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+        htim->OnePulse_MspInitCallback          = HAL_TIM_OnePulse_MspInit;                  /* Legacy weak One Pulse Msp Init Callback */
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+        htim->OnePulse_MspDeInitCallback        = HAL_TIM_OnePulse_MspDeInit;                /* Legacy weak One Pulse Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+        htim->Encoder_MspInitCallback           = HAL_TIM_Encoder_MspInit;                   /* Legacy weak Encoder Msp Init Callback */
+        break;
+
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+        htim->Encoder_MspDeInitCallback         = HAL_TIM_Encoder_MspDeInit;                 /* Legacy weak Encoder Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+        htim->HallSensor_MspInitCallback        = HAL_TIMEx_HallSensor_MspInit;              /* Legacy weak Hall Sensor Msp Init Callback */
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+        htim->HallSensor_MspDeInitCallback      = HAL_TIMEx_HallSensor_MspDeInit;            /* Legacy weak Hall Sensor Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_PERIOD_ELAPSED_CB_ID :
+        htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;             /* Legacy weak Period Elapsed Callback */
+        break;
+
+      case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
+        htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;     /* Legacy weak Period Elapsed half complete Callback */
+        break;
+
+      case HAL_TIM_TRIGGER_CB_ID :
+        htim->TriggerCallback                   = HAL_TIM_TriggerCallback;                   /* Legacy weak Trigger Callback */
+        break;
+
+      case HAL_TIM_TRIGGER_HALF_CB_ID :
+        htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;           /* Legacy weak Trigger half complete Callback */
+        break;
+
+      case HAL_TIM_IC_CAPTURE_CB_ID :
+        htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;                /* Legacy weak IC Capture Callback */
+        break;
+
+      case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
+        htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;        /* Legacy weak IC Capture half complete Callback */
+        break;
+
+      case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
+        htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;           /* Legacy weak OC Delay Elapsed Callback */
+        break;
+
+      case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
+        htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;         /* Legacy weak PWM Pulse Finished Callback */
+        break;
+
+      case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
+        htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */
+        break;
+
+      case HAL_TIM_ERROR_CB_ID :
+        htim->ErrorCallback                     = HAL_TIM_ErrorCallback;                     /* Legacy weak Error Callback */
+        break;
+
+      case HAL_TIM_COMMUTATION_CB_ID :
+        htim->CommutationCallback               = HAL_TIMEx_CommutCallback;                  /* Legacy weak Commutation Callback */
+        break;
+
+      case HAL_TIM_COMMUTATION_HALF_CB_ID :
+        htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;          /* Legacy weak Commutation half complete Callback */
+        break;
+
+      case HAL_TIM_BREAK_CB_ID :
+        htim->BreakCallback                     = HAL_TIMEx_BreakCallback;                   /* Legacy weak Break Callback */
+        break;
+
+      case HAL_TIM_BREAK2_CB_ID :
+        htim->Break2Callback                    = HAL_TIMEx_Break2Callback;                  /* Legacy weak Break2 Callback */
+        break;
+
+      default :
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_TIM_BASE_MSPINIT_CB_ID :
+        htim->Base_MspInitCallback         = HAL_TIM_Base_MspInit;              /* Legacy weak Base MspInit Callback */
+        break;
+
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+        htim->Base_MspDeInitCallback       = HAL_TIM_Base_MspDeInit;            /* Legacy weak Base Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_IC_MSPINIT_CB_ID :
+        htim->IC_MspInitCallback           = HAL_TIM_IC_MspInit;                /* Legacy weak IC Msp Init Callback */
+        break;
+
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :
+        htim->IC_MspDeInitCallback         = HAL_TIM_IC_MspDeInit;              /* Legacy weak IC Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_OC_MSPINIT_CB_ID :
+        htim->OC_MspInitCallback           = HAL_TIM_OC_MspInit;                /* Legacy weak OC Msp Init Callback */
+        break;
+
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :
+        htim->OC_MspDeInitCallback         = HAL_TIM_OC_MspDeInit;              /* Legacy weak OC Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_PWM_MSPINIT_CB_ID :
+        htim->PWM_MspInitCallback          = HAL_TIM_PWM_MspInit;               /* Legacy weak PWM Msp Init Callback */
+        break;
+
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+        htim->PWM_MspDeInitCallback        = HAL_TIM_PWM_MspDeInit;             /* Legacy weak PWM Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+        htim->OnePulse_MspInitCallback     = HAL_TIM_OnePulse_MspInit;          /* Legacy weak One Pulse Msp Init Callback */
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+        htim->OnePulse_MspDeInitCallback   = HAL_TIM_OnePulse_MspDeInit;        /* Legacy weak One Pulse Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+        htim->Encoder_MspInitCallback      = HAL_TIM_Encoder_MspInit;           /* Legacy weak Encoder Msp Init Callback */
+        break;
+
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+        htim->Encoder_MspDeInitCallback    = HAL_TIM_Encoder_MspDeInit;         /* Legacy weak Encoder Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+        htim->HallSensor_MspInitCallback   = HAL_TIMEx_HallSensor_MspInit;      /* Legacy weak Hall Sensor Msp Init Callback */
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+        htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;    /* Legacy weak Hall Sensor Msp DeInit Callback */
+        break;
+
+      default :
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
+  *  @brief   TIM Peripheral State functions
+  *
+@verbatim
+  ==============================================================================
+                        ##### Peripheral State functions #####
+  ==============================================================================
+    [..]
+    This subsection permits to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the TIM Base handle state.
+  * @param  htim TIM Base handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM OC handle state.
+  * @param  htim TIM Output Compare handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM PWM handle state.
+  * @param  htim TIM handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM Input Capture handle state.
+  * @param  htim TIM IC handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM One Pulse Mode handle state.
+  * @param  htim TIM OPM handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM Encoder Mode handle state.
+  * @param  htim TIM Encoder Interface handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Private_Functions TIM Private Functions
+  * @{
+  */
+
+/**
+  * @brief  TIM DMA error callback
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMAError(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->ErrorCallback(htim);
+#else
+  HAL_TIM_ErrorCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Delay Pulse complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PWM_PulseFinishedCallback(htim);
+#else
+  HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Delay Pulse half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PWM_PulseFinishedHalfCpltCallback(htim);
+#else
+  HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Capture complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->IC_CaptureCallback(htim);
+#else
+  HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Capture half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->IC_CaptureHalfCpltCallback(htim);
+#else
+  HAL_TIM_IC_CaptureHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Period Elapse complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PeriodElapsedCallback(htim);
+#else
+  HAL_TIM_PeriodElapsedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Period Elapse half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PeriodElapsedHalfCpltCallback(htim);
+#else
+  HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Trigger callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->TriggerCallback(htim);
+#else
+  HAL_TIM_TriggerCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Trigger half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->TriggerHalfCpltCallback(htim);
+#else
+  HAL_TIM_TriggerHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  Time Base configuration
+  * @param  TIMx TIM peripheral
+  * @param  Structure TIM Base configuration structure
+  * @retval None
+  */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
+{
+  uint32_t tmpcr1;
+  tmpcr1 = TIMx->CR1;
+
+  /* Set TIM Time Base Unit parameters ---------------------------------------*/
+  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
+  {
+    /* Select the Counter Mode */
+    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
+    tmpcr1 |= Structure->CounterMode;
+  }
+
+  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
+  {
+    /* Set the clock division */
+    tmpcr1 &= ~TIM_CR1_CKD;
+    tmpcr1 |= (uint32_t)Structure->ClockDivision;
+  }
+
+  /* Set the auto-reload preload */
+  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
+
+  TIMx->CR1 = tmpcr1;
+
+  /* Set the Autoreload value */
+  TIMx->ARR = (uint32_t)Structure->Period ;
+
+  /* Set the Prescaler value */
+  TIMx->PSC = Structure->Prescaler;
+
+  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
+  {
+    /* Set the Repetition Counter value */
+    TIMx->RCR = Structure->RepetitionCounter;
+  }
+
+  /* Generate an update event to reload the Prescaler
+     and the repetition counter (only for advanced timer) value immediately */
+  TIMx->EGR = TIM_EGR_UG;
+}
+
+/**
+  * @brief  Timer Output Compare 1 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The ouput configuration structure
+  * @retval None
+  */
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR1;
+
+  /* Reset the Output Compare Mode Bits */
+  tmpccmrx &= ~TIM_CCMR1_OC1M;
+  tmpccmrx &= ~TIM_CCMR1_CC1S;
+  /* Select the Output Compare Mode */
+  tmpccmrx |= OC_Config->OCMode;
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC1P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= OC_Config->OCPolarity;
+
+  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+    /* Reset the Output N Polarity level */
+    tmpccer &= ~TIM_CCER_CC1NP;
+    /* Set the Output N Polarity */
+    tmpccer |= OC_Config->OCNPolarity;
+    /* Reset the Output N State */
+    tmpccer &= ~TIM_CCER_CC1NE;
+  }
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS1;
+    tmpcr2 &= ~TIM_CR2_OIS1N;
+    /* Set the Output Idle state */
+    tmpcr2 |= OC_Config->OCIdleState;
+    /* Set the Output N Idle state */
+    tmpcr2 |= OC_Config->OCNIdleState;
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR1 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Output Compare 2 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The ouput configuration structure
+  * @retval None
+  */
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR1;
+
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= ~TIM_CCMR1_OC2M;
+  tmpccmrx &= ~TIM_CCMR1_CC2S;
+
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (OC_Config->OCMode << 8U);
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC2P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 4U);
+
+  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
+  {
+    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+    /* Reset the Output N Polarity level */
+    tmpccer &= ~TIM_CCER_CC2NP;
+    /* Set the Output N Polarity */
+    tmpccer |= (OC_Config->OCNPolarity << 4U);
+    /* Reset the Output N State */
+    tmpccer &= ~TIM_CCER_CC2NE;
+
+  }
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS2;
+    tmpcr2 &= ~TIM_CR2_OIS2N;
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 2U);
+    /* Set the Output N Idle state */
+    tmpcr2 |= (OC_Config->OCNIdleState << 2U);
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR2 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Output Compare 3 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The ouput configuration structure
+  * @retval None
+  */
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Disable the Channel 3: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC3E;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+
+  /* Get the TIMx CCMR2 register value */
+  tmpccmrx = TIMx->CCMR2;
+
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= ~TIM_CCMR2_OC3M;
+  tmpccmrx &= ~TIM_CCMR2_CC3S;
+  /* Select the Output Compare Mode */
+  tmpccmrx |= OC_Config->OCMode;
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC3P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 8U);
+
+  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
+  {
+    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+    /* Reset the Output N Polarity level */
+    tmpccer &= ~TIM_CCER_CC3NP;
+    /* Set the Output N Polarity */
+    tmpccer |= (OC_Config->OCNPolarity << 8U);
+    /* Reset the Output N State */
+    tmpccer &= ~TIM_CCER_CC3NE;
+  }
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS3;
+    tmpcr2 &= ~TIM_CR2_OIS3N;
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 4U);
+    /* Set the Output N Idle state */
+    tmpcr2 |= (OC_Config->OCNIdleState << 4U);
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR2 */
+  TIMx->CCMR2 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR3 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Output Compare 4 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The ouput configuration structure
+  * @retval None
+  */
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Disable the Channel 4: Reset the CC4E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC4E;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+
+  /* Get the TIMx CCMR2 register value */
+  tmpccmrx = TIMx->CCMR2;
+
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= ~TIM_CCMR2_OC4M;
+  tmpccmrx &= ~TIM_CCMR2_CC4S;
+
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (OC_Config->OCMode << 8U);
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC4P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 12U);
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+    /* Reset the Output Compare IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS4;
+
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 6U);
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR2 */
+  TIMx->CCMR2 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR4 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Output Compare 5 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The ouput configuration structure
+  * @retval None
+  */
+static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
+                              TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Disable the output: Reset the CCxE Bit */
+  TIMx->CCER &= ~TIM_CCER_CC5E;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR3;
+
+  /* Reset the Output Compare Mode Bits */
+  tmpccmrx &= ~(TIM_CCMR3_OC5M);
+  /* Select the Output Compare Mode */
+  tmpccmrx |= OC_Config->OCMode;
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC5P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 16U);
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Reset the Output Compare IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS5;
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 8U);
+  }
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR3 */
+  TIMx->CCMR3 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR5 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Output Compare 6 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The ouput configuration structure
+  * @retval None
+  */
+static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
+                              TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Disable the output: Reset the CCxE Bit */
+  TIMx->CCER &= ~TIM_CCER_CC6E;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR3;
+
+  /* Reset the Output Compare Mode Bits */
+  tmpccmrx &= ~(TIM_CCMR3_OC6M);
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (OC_Config->OCMode << 8U);
+
+  /* Reset the Output Polarity level */
+  tmpccer &= (uint32_t)~TIM_CCER_CC6P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 20U);
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Reset the Output Compare IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS6;
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 10U);
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR3 */
+  TIMx->CCMR3 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR6 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Slave Timer configuration function
+  * @param  htim TIM handle
+  * @param  sSlaveConfig Slave timer configuration
+  * @retval None
+  */
+static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+                                                  TIM_SlaveConfigTypeDef *sSlaveConfig)
+{
+  uint32_t tmpsmcr;
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = htim->Instance->SMCR;
+
+  /* Reset the Trigger Selection Bits */
+  tmpsmcr &= ~TIM_SMCR_TS;
+  /* Set the Input Trigger source */
+  tmpsmcr |= sSlaveConfig->InputTrigger;
+
+  /* Reset the slave mode Bits */
+  tmpsmcr &= ~TIM_SMCR_SMS;
+  /* Set the slave mode */
+  tmpsmcr |= sSlaveConfig->SlaveMode;
+
+  /* Write to TIMx SMCR */
+  htim->Instance->SMCR = tmpsmcr;
+
+  /* Configure the trigger prescaler, filter, and polarity */
+  switch (sSlaveConfig->InputTrigger)
+  {
+    case TIM_TS_ETRF:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
+      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+      /* Configure the ETR Trigger source */
+      TIM_ETR_SetConfig(htim->Instance,
+                        sSlaveConfig->TriggerPrescaler,
+                        sSlaveConfig->TriggerPolarity,
+                        sSlaveConfig->TriggerFilter);
+      break;
+    }
+
+    case TIM_TS_TI1F_ED:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+      if(sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Disable the Channel 1: Reset the CC1E Bit */
+      tmpccer = htim->Instance->CCER;
+      htim->Instance->CCER &= ~TIM_CCER_CC1E;
+      tmpccmr1 = htim->Instance->CCMR1;
+
+      /* Set the filter */
+      tmpccmr1 &= ~TIM_CCMR1_IC1F;
+      tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
+
+      /* Write to TIMx CCMR1 and CCER registers */
+      htim->Instance->CCMR1 = tmpccmr1;
+      htim->Instance->CCER = tmpccer;
+      break;
+    }
+
+    case TIM_TS_TI1FP1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+      /* Configure TI1 Filter and Polarity */
+      TIM_TI1_ConfigInputStage(htim->Instance,
+                               sSlaveConfig->TriggerPolarity,
+                               sSlaveConfig->TriggerFilter);
+      break;
+    }
+
+    case TIM_TS_TI2FP2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+      /* Configure TI2 Filter and Polarity */
+      TIM_TI2_ConfigInputStage(htim->Instance,
+                               sSlaveConfig->TriggerPolarity,
+                               sSlaveConfig->TriggerFilter);
+      break;
+    }
+
+    case TIM_TS_ITR0:
+    case TIM_TS_ITR1:
+    case TIM_TS_ITR2:
+    case TIM_TS_ITR3:
+    case TIM_TS_ITR4:
+    case TIM_TS_ITR5:
+    case TIM_TS_ITR6:
+    case TIM_TS_ITR7:
+    case TIM_TS_ITR8:
+    case TIM_TS_ITR9:
+    case TIM_TS_ITR10:
+    case TIM_TS_ITR11:
+    case TIM_TS_ITR12:
+    case TIM_TS_ITR13:
+    {
+      /* Check the parameter */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+      break;
+    }
+
+    default:
+      break;
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the TI1 as Input.
+  * @param  TIMx to select the TIM peripheral.
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICSelection specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
+  *       (on channel2 path) is used as the input signal. Therefore CCMR1 must be
+  *        protected against un-initialized filter and polarity values.
+  */
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                       uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+  tmpccmr1 = TIMx->CCMR1;
+  tmpccer = TIMx->CCER;
+
+  /* Select the Input */
+  if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
+  {
+    tmpccmr1 &= ~TIM_CCMR1_CC1S;
+    tmpccmr1 |= TIM_ICSelection;
+  }
+  else
+  {
+    tmpccmr1 |= TIM_CCMR1_CC1S_0;
+  }
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC1F;
+  tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
+
+  /* Select the Polarity and set the CC1E Bit */
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+  tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the Polarity and Filter for TI1.
+  * @param  TIMx to select the TIM peripheral.
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  tmpccer = TIMx->CCER;
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC1F;
+  tmpccmr1 |= (TIM_ICFilter << 4U);
+
+  /* Select the Polarity and set the CC1E Bit */
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+  tmpccer |= TIM_ICPolarity;
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI2 as Input.
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICSelection specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
+  *       (on channel1 path) is used as the input signal. Therefore CCMR1 must be
+  *        protected against un-initialized filter and polarity values.
+  */
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+  tmpccmr1 = TIMx->CCMR1;
+  tmpccer = TIMx->CCER;
+
+  /* Select the Input */
+  tmpccmr1 &= ~TIM_CCMR1_CC2S;
+  tmpccmr1 |= (TIM_ICSelection << 8U);
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC2F;
+  tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
+
+  /* Select the Polarity and set the CC2E Bit */
+  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+  tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1 ;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the Polarity and Filter for TI2.
+  * @param  TIMx to select the TIM peripheral.
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+  tmpccmr1 = TIMx->CCMR1;
+  tmpccer = TIMx->CCER;
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC2F;
+  tmpccmr1 |= (TIM_ICFilter << 12U);
+
+  /* Select the Polarity and set the CC2E Bit */
+  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+  tmpccer |= (TIM_ICPolarity << 4U);
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1 ;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI3 as Input.
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICSelection specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
+  *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+  *        protected against un-initialized filter and polarity values.
+  */
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr2;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 3: Reset the CC3E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC3E;
+  tmpccmr2 = TIMx->CCMR2;
+  tmpccer = TIMx->CCER;
+
+  /* Select the Input */
+  tmpccmr2 &= ~TIM_CCMR2_CC3S;
+  tmpccmr2 |= TIM_ICSelection;
+
+  /* Set the filter */
+  tmpccmr2 &= ~TIM_CCMR2_IC3F;
+  tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
+
+  /* Select the Polarity and set the CC3E Bit */
+  tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
+  tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
+
+  /* Write to TIMx CCMR2 and CCER registers */
+  TIMx->CCMR2 = tmpccmr2;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI4 as Input.
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICSelection specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
+  *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+  *        protected against un-initialized filter and polarity values.
+  * @retval None
+  */
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr2;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 4: Reset the CC4E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC4E;
+  tmpccmr2 = TIMx->CCMR2;
+  tmpccer = TIMx->CCER;
+
+  /* Select the Input */
+  tmpccmr2 &= ~TIM_CCMR2_CC4S;
+  tmpccmr2 |= (TIM_ICSelection << 8U);
+
+  /* Set the filter */
+  tmpccmr2 &= ~TIM_CCMR2_IC4F;
+  tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
+
+  /* Select the Polarity and set the CC4E Bit */
+  tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
+  tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
+
+  /* Write to TIMx CCMR2 and CCER registers */
+  TIMx->CCMR2 = tmpccmr2;
+  TIMx->CCER = tmpccer ;
+}
+
+/**
+  * @brief  Selects the Input Trigger source
+  * @param  TIMx to select the TIM peripheral
+  * @param  InputTriggerSource The Input Trigger source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal Trigger 0
+  *            @arg TIM_TS_ITR1: Internal Trigger 1
+  *            @arg TIM_TS_ITR2: Internal Trigger 2
+  *            @arg TIM_TS_ITR3: Internal Trigger 3
+  *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
+  *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
+  *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
+  *            @arg TIM_TS_ETRF: External Trigger input
+  *            @arg TIM_TS_ITR4: Internal Trigger 4  (*)
+  *            @arg TIM_TS_ITR5: Internal Trigger 5
+  *            @arg TIM_TS_ITR6: Internal Trigger 6
+  *            @arg TIM_TS_ITR7: Internal Trigger 7
+  *            @arg TIM_TS_ITR8: Internal Trigger 8  (*)
+  *            @arg TIM_TS_ITR9: Internal Trigger 9  (*)
+  *            @arg TIM_TS_ITR10: Internal Trigger 10 (*)
+  *            @arg TIM_TS_ITR11: Internal Trigger 11 (*)
+  *            @arg TIM_TS_ITR12: Internal Trigger 12 (*)
+  *            @arg TIM_TS_ITR13: Internal Trigger 13 (*)
+  *
+  *       (*)  Value not defined in all devices.
+  *
+  * @retval None
+  */
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
+{
+  uint32_t tmpsmcr;
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = TIMx->SMCR;
+  /* Reset the TS Bits */
+  tmpsmcr &= ~TIM_SMCR_TS;
+  /* Set the Input Trigger source and the slave mode*/
+  tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+}
+/**
+  * @brief  Configures the TIMx External Trigger (ETR).
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ExtTRGPrescaler The external Trigger Prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
+  *            @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
+  *            @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
+  *            @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
+  * @param  TIM_ExtTRGPolarity The external Trigger Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
+  *            @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
+  * @param  ExtTRGFilter External Trigger Filter.
+  *          This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
+                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
+{
+  uint32_t tmpsmcr;
+
+  tmpsmcr = TIMx->SMCR;
+
+  /* Reset the ETR Bits */
+  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+
+  /* Set the Prescaler, the Filter value and the Polarity */
+  tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
+
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+}
+
+/**
+  * @brief  Enables or disables the TIM Capture Compare Channel x.
+  * @param  TIMx to select the TIM peripheral
+  * @param  Channel specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1
+  *            @arg TIM_CHANNEL_2: TIM Channel 2
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  *            @arg TIM_CHANNEL_4: TIM Channel 4
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @param  ChannelState specifies the TIM Channel CCxE bit new state.
+  *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
+  * @retval None
+  */
+void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
+{
+  uint32_t tmp;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+  assert_param(IS_TIM_CHANNELS(Channel));
+
+  tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
+
+  /* Reset the CCxE Bit */
+  TIMx->CCER &= ~tmp;
+
+  /* Set or reset the CCxE Bit */
+  TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
+}
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Reset interrupt callbacks to the legacy weak callbacks.
+  * @param  htim pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval None
+  */
+void TIM_ResetCallback(TIM_HandleTypeDef *htim)
+{
+  /* Reset the TIM callback to the legacy weak callbacks */
+  htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;             /* Legacy weak PeriodElapsedCallback             */
+  htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;     /* Legacy weak PeriodElapsedHalfCpltCallback     */
+  htim->TriggerCallback                   = HAL_TIM_TriggerCallback;                   /* Legacy weak TriggerCallback                   */
+  htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;           /* Legacy weak TriggerHalfCpltCallback           */
+  htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;                /* Legacy weak IC_CaptureCallback                */
+  htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;        /* Legacy weak IC_CaptureHalfCpltCallback        */
+  htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;           /* Legacy weak OC_DelayElapsedCallback           */
+  htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;         /* Legacy weak PWM_PulseFinishedCallback         */
+  htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */
+  htim->ErrorCallback                     = HAL_TIM_ErrorCallback;                     /* Legacy weak ErrorCallback                     */
+  htim->CommutationCallback               = HAL_TIMEx_CommutCallback;                  /* Legacy weak CommutationCallback               */
+  htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;          /* Legacy weak CommutationHalfCpltCallback       */
+  htim->BreakCallback                     = HAL_TIMEx_BreakCallback;                   /* Legacy weak BreakCallback                     */
+  htim->Break2Callback                    = HAL_TIMEx_Break2Callback;                  /* Legacy weak Break2Callback                    */
+}
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_TIM_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c
new file mode 100644
index 00000000..1dcd7704
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c
@@ -0,0 +1,2324 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_tim_ex.c
+  * @author  MCD Application Team
+  * @brief   TIM HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Timer Extended peripheral:
+  *           + Time Hall Sensor Interface Initialization
+  *           + Time Hall Sensor Interface Start
+  *           + Time Complementary signal break and dead time configuration
+  *           + Time Master and Slave synchronization configuration
+  *           + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
+  *           + Timer remapping capabilities configuration
+  @verbatim
+  ==============================================================================
+                      ##### TIMER Extended features #####
+  ==============================================================================
+  [..]
+    The Timer Extended features include:
+    (#) Complementary outputs with programmable dead-time for :
+        (++) Output Compare
+        (++) PWM generation (Edge and Center-aligned Mode)
+        (++) One-pulse mode output
+    (#) Synchronization circuit to control the timer with external signals and to
+        interconnect several timers together.
+    (#) Break input to put the timer output signals in reset state or in a known state.
+    (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
+        positioning purposes
+
+            ##### How to use this driver #####
+  ==============================================================================
+    [..]
+     (#) Initialize the TIM low level resources by implementing the following functions
+         depending on the selected feature:
+           (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
+
+     (#) Initialize the TIM low level resources :
+        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
+        (##) TIM pins configuration
+            (+++) Enable the clock for the TIM GPIOs using the following function:
+              __HAL_RCC_GPIOx_CLK_ENABLE();
+            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
+
+     (#) The external Clock can be configured, if needed (the default clock is the
+         internal clock from the APBx), using the following function:
+         HAL_TIM_ConfigClockSource, the clock configuration should be done before
+         any start function.
+
+     (#) Configure the TIM in the desired functioning mode using one of the
+         initialization function of this driver:
+          (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the
+               Timer Hall Sensor Interface and the commutation event with the corresponding
+               Interrupt and DMA request if needed (Note that One Timer is used to interface
+               with the Hall sensor Interface and another Timer should be used to use
+               the commutation event).
+
+     (#) Activate the TIM peripheral using one of the start functions:
+           (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()
+           (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
+           (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
+           (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup TIMEx TIMEx
+  * @brief TIM Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
+  * @brief    Timer Hall Sensor functions
+  *
+@verbatim
+  ==============================================================================
+                      ##### Timer Hall Sensor functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure TIM HAL Sensor.
+    (+) De-initialize TIM HAL Sensor.
+    (+) Start the Hall Sensor Interface.
+    (+) Stop the Hall Sensor Interface.
+    (+) Start the Hall Sensor Interface and enable interrupts.
+    (+) Stop the Hall Sensor Interface and disable interrupts.
+    (+) Start the Hall Sensor Interface and enable DMA transfers.
+    (+) Stop the Hall Sensor Interface and disable DMA transfers.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Hall Sensor Interface and initialize the associated handle.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @param  sConfig TIM Hall Sensor configuration structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
+{
+  TIM_OC_InitTypeDef OC_Config;
+
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+  assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+  assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy week callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->HallSensor_MspInitCallback == NULL)
+    {
+      htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->HallSensor_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIMEx_HallSensor_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Configure the Time base in the Encoder Mode */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the  Hall sensor */
+  TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
+
+  /* Reset the IC1PSC Bits */
+  htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+  /* Set the IC1PSC value */
+  htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
+
+  /* Enable the Hall sensor interface (XOR function of the three inputs) */
+  htim->Instance->CR2 |= TIM_CR2_TI1S;
+
+  /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
+  htim->Instance->SMCR &= ~TIM_SMCR_TS;
+  htim->Instance->SMCR |= TIM_TS_TI1F_ED;
+
+  /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
+  htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+  htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
+
+  /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
+  OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
+  OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
+  OC_Config.OCMode = TIM_OCMODE_PWM2;
+  OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
+  OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
+  OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
+  OC_Config.Pulse = sConfig->Commutation_Delay;
+
+  TIM_OC2_SetConfig(htim->Instance, &OC_Config);
+
+  /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
+    register to 101 */
+  htim->Instance->CR2 &= ~TIM_CR2_MMS;
+  htim->Instance->CR2 |= TIM_TRGO_OC2REF;
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM Hall Sensor interface
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->HallSensor_MspDeInitCallback == NULL)
+  {
+    htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->HallSensor_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIMEx_HallSensor_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Hall Sensor MSP.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Hall Sensor MSP.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Hall Sensor Interface.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Enable the Input Capture channel 1
+    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Hall sensor Interface.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channels 1, 2 and 3
+    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Hall Sensor Interface in interrupt mode.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Enable the capture compare Interrupts 1 event */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+  /* Enable the Input Capture channel 1
+    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Hall Sensor Interface in interrupt mode.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channel 1
+    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+  /* Disable the capture compare Interrupts event */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Hall Sensor Interface in DMA mode.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @param  pData The destination Buffer address.
+  * @param  Length The length of data to be transferred from TIM peripheral to memory.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if (((uint32_t)pData == 0U) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+  /* Enable the Input Capture channel 1
+    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+  /* Set the DMA Input Capture 1 Callbacks */
+  htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+  htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+  /* Set the DMA error callback */
+  htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+  /* Enable the DMA stream for Capture 1*/
+  if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  /* Enable the capture compare 1 Interrupt */
+  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Hall Sensor Interface in DMA mode.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channel 1
+    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+
+  /* Disable the capture compare Interrupts 1 event */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+
+  (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
+  *  @brief   Timer Complementary Output Compare functions
+  *
+@verbatim
+  ==============================================================================
+              ##### Timer Complementary Output Compare functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Start the Complementary Output Compare/PWM.
+    (+) Stop the Complementary Output Compare/PWM.
+    (+) Start the Complementary Output Compare/PWM and enable interrupts.
+    (+) Stop the Complementary Output Compare/PWM and disable interrupts.
+    (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
+    (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation on the complementary
+  *         output.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Enable the Capture compare channel N */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation on the complementary
+  *         output.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the Capture compare channel N */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in interrupt mode
+  *         on the complementary output.
+  * @param  htim TIM OC handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Output Compare interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Output Compare interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Output Compare interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+
+    default:
+      break;
+  }
+
+  /* Enable the TIM Break interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+
+  /* Enable the Capture compare channel N */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in interrupt mode
+  *         on the complementary output.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpccer;
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Output Compare interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Output Compare interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Output Compare interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Disable the Capture compare channel N */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+  /* Disable the TIM Break interrupt (only if no more channel is active) */
+  tmpccer = htim->Instance->CCER;
+  if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
+  {
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+  }
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in DMA mode
+  *         on the complementary output.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if (((uint32_t)pData == 0U) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do  */
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Output Compare DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Output Compare DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Output Compare DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Enable the Capture compare channel N */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in DMA mode
+  *         on the complementary output.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Output Compare DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Output Compare DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Output Compare DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Disable the Capture compare channel N */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
+  * @brief    Timer Complementary PWM functions
+  *
+@verbatim
+  ==============================================================================
+                 ##### Timer Complementary PWM functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Start the Complementary PWM.
+    (+) Stop the Complementary PWM.
+    (+) Start the Complementary PWM and enable interrupts.
+    (+) Stop the Complementary PWM and disable interrupts.
+    (+) Start the Complementary PWM and enable DMA transfers.
+    (+) Stop the Complementary PWM and disable DMA transfers.
+    (+) Start the Complementary Input Capture measurement.
+    (+) Stop the Complementary Input Capture.
+    (+) Start the Complementary Input Capture and enable interrupts.
+    (+) Stop the Complementary Input Capture and disable interrupts.
+    (+) Start the Complementary Input Capture and enable DMA transfers.
+    (+) Stop the Complementary Input Capture and disable DMA transfers.
+    (+) Start the Complementary One Pulse generation.
+    (+) Stop the Complementary One Pulse.
+    (+) Start the Complementary One Pulse and enable interrupts.
+    (+) Stop the Complementary One Pulse and disable interrupts.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the PWM signal generation on the complementary output.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Enable the complementary PWM output  */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the PWM signal generation on the complementary output.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the complementary PWM output  */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the PWM signal generation in interrupt mode on the
+  *         complementary output.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Enable the TIM Break interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+
+  /* Enable the complementary PWM output  */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the PWM signal generation in interrupt mode on the
+  *         complementary output.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpccer;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Disable the complementary PWM output  */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+  /* Disable the TIM Break interrupt (only if no more channel is active) */
+  tmpccer = htim->Instance->CCER;
+  if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
+  {
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+  }
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM PWM signal generation in DMA mode on the
+  *         complementary output
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if (((uint32_t)pData == 0U) && (Length > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Enable the complementary PWM output  */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM PWM signal generation in DMA mode on the complementary
+  *         output
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Disable the complementary PWM output */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
+  * @brief    Timer Complementary One Pulse functions
+  *
+@verbatim
+  ==============================================================================
+                ##### Timer Complementary One Pulse functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Start the Complementary One Pulse generation.
+    (+) Stop the Complementary One Pulse.
+    (+) Start the Complementary One Pulse and enable interrupts.
+    (+) Stop the Complementary One Pulse and disable interrupts.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation on the complementary
+  *         output.
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+  /* Enable the complementary One Pulse output */
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM One Pulse signal generation on the complementary
+  *         output.
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+  /* Disable the complementary One Pulse output */
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation in interrupt mode on the
+  *         complementary channel.
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+  /* Enable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+  /* Enable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+
+  /* Enable the complementary One Pulse output */
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+
+  /* Enable the Main Output */
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM One Pulse signal generation in interrupt mode on the
+  *         complementary channel.
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+  /* Disable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+  /* Disable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+
+  /* Disable the complementary One Pulse output */
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+
+  /* Disable the Main Output */
+  __HAL_TIM_MOE_DISABLE(htim);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
+  * @brief    Peripheral Control functions
+  *
+@verbatim
+  ==============================================================================
+                    ##### Peripheral Control functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+      (+) Configure the commutation event in case of use of the Hall sensor interface.
+      (+) Configure Output channels for OC and PWM mode.
+
+      (+) Configure Complementary channels, break features and dead time.
+      (+) Configure Master synchronization.
+      (+) Configure timer remapping capabilities.
+      (+) Select timer input source.
+      (+) Enable or disable channel grouping.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the TIM commutation event sequence.
+  * @note  This function is mandatory to use the commutation event in order to
+  *        update the configuration at each commutation detection on the TRGI input of the Timer,
+  *        the typical use of this feature is with the use of another Timer(interface Timer)
+  *        configured in Hall sensor interface, this interface Timer will generate the
+  *        commutation at its TRGO output (connected to Timer used in this function) each time
+  *        the TI1 of the Interface Timer detect a commutation at its input TI1.
+  * @param  htim TIM handle
+  * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal trigger 0 selected
+  *            @arg TIM_TS_ITR1: Internal trigger 1 selected
+  *            @arg TIM_TS_ITR2: Internal trigger 2 selected
+  *            @arg TIM_TS_ITR3: Internal trigger 3 selected
+  *            @arg TIM_TS_ITR12: Internal trigger 12 selected (*)
+  *            @arg TIM_TS_ITR13: Internal trigger 13 selected (*)
+  *            @arg TIM_TS_NONE: No trigger is needed
+  * @param  CommutationSource the Commutation Event source
+  *          This parameter can be one of the following values:
+  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                              uint32_t  CommutationSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
+      (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
+      (InputTrigger == TIM_TS_ITR12)  || (InputTrigger == TIM_TS_ITR13))
+  {
+    /* Select the Input trigger */
+    htim->Instance->SMCR &= ~TIM_SMCR_TS;
+    htim->Instance->SMCR |= InputTrigger;
+  }
+
+  /* Select the Capture Compare preload feature */
+  htim->Instance->CR2 |= TIM_CR2_CCPC;
+  /* Select the Commutation event source */
+  htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+  htim->Instance->CR2 |= CommutationSource;
+
+  /* Disable Commutation Interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
+
+  /* Disable Commutation DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the TIM commutation event sequence with interrupt.
+  * @note  This function is mandatory to use the commutation event in order to
+  *        update the configuration at each commutation detection on the TRGI input of the Timer,
+  *        the typical use of this feature is with the use of another Timer(interface Timer)
+  *        configured in Hall sensor interface, this interface Timer will generate the
+  *        commutation at its TRGO output (connected to Timer used in this function) each time
+  *        the TI1 of the Interface Timer detect a commutation at its input TI1.
+  * @param  htim TIM handle
+  * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal trigger 0 selected
+  *            @arg TIM_TS_ITR1: Internal trigger 1 selected
+  *            @arg TIM_TS_ITR2: Internal trigger 2 selected
+  *            @arg TIM_TS_ITR3: Internal trigger 3 selected
+  *            @arg TIM_TS_ITR2: Internal trigger 12 selected (*)
+  *            @arg TIM_TS_ITR3: Internal trigger 13 selected (*)
+  *            @arg TIM_TS_NONE: No trigger is needed
+  * @param  CommutationSource the Commutation Event source
+  *          This parameter can be one of the following values:
+  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                                 uint32_t  CommutationSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
+      (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
+      (InputTrigger == TIM_TS_ITR12)  || (InputTrigger == TIM_TS_ITR13))
+  {
+    /* Select the Input trigger */
+    htim->Instance->SMCR &= ~TIM_SMCR_TS;
+    htim->Instance->SMCR |= InputTrigger;
+  }
+
+  /* Select the Capture Compare preload feature */
+  htim->Instance->CR2 |= TIM_CR2_CCPC;
+  /* Select the Commutation event source */
+  htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+  htim->Instance->CR2 |= CommutationSource;
+
+  /* Disable Commutation DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
+
+  /* Enable the Commutation Interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the TIM commutation event sequence with DMA.
+  * @note  This function is mandatory to use the commutation event in order to
+  *        update the configuration at each commutation detection on the TRGI input of the Timer,
+  *        the typical use of this feature is with the use of another Timer(interface Timer)
+  *        configured in Hall sensor interface, this interface Timer will generate the
+  *        commutation at its TRGO output (connected to Timer used in this function) each time
+  *        the TI1 of the Interface Timer detect a commutation at its input TI1.
+  * @note  The user should configure the DMA in his own software, in This function only the COMDE bit is set
+  * @param  htim TIM handle
+  * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal trigger 0 selected
+  *            @arg TIM_TS_ITR1: Internal trigger 1 selected
+  *            @arg TIM_TS_ITR2: Internal trigger 2 selected
+  *            @arg TIM_TS_ITR3: Internal trigger 3 selected
+  *            @arg TIM_TS_ITR2: Internal trigger 12 selected (*)
+  *            @arg TIM_TS_ITR3: Internal trigger 13 selected (*)
+  *            @arg TIM_TS_NONE: No trigger is needed
+  *
+  *         (*)  Value not defined in all devices.
+  *
+  * @param  CommutationSource the Commutation Event source
+  *          This parameter can be one of the following values:
+  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                                  uint32_t  CommutationSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  if ((InputTrigger == TIM_TS_ITR0)  || (InputTrigger == TIM_TS_ITR1) ||
+      (InputTrigger == TIM_TS_ITR2)  || (InputTrigger == TIM_TS_ITR3) ||
+      (InputTrigger == TIM_TS_ITR12)  || (InputTrigger == TIM_TS_ITR13))
+  {
+    /* Select the Input trigger */
+    htim->Instance->SMCR &= ~TIM_SMCR_TS;
+    htim->Instance->SMCR |= InputTrigger;
+  }
+
+  /* Select the Capture Compare preload feature */
+  htim->Instance->CR2 |= TIM_CR2_CCPC;
+  /* Select the Commutation event source */
+  htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+  htim->Instance->CR2 |= CommutationSource;
+
+  /* Enable the Commutation DMA Request */
+  /* Set the DMA Commutation Callback */
+  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
+  /* Set the DMA error callback */
+  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
+
+  /* Disable Commutation Interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
+
+  /* Enable the Commutation DMA Request */
+  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the TIM in master mode.
+  * @param  htim TIM handle.
+  * @param  sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
+  *         contains the selected trigger output (TRGO) and the Master/Slave
+  *         mode.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+                                                        TIM_MasterConfigTypeDef *sMasterConfig)
+{
+  uint32_t tmpcr2;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
+  assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
+
+  /* Check input state */
+  __HAL_LOCK(htim);
+
+  /* Change the handler state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = htim->Instance->CR2;
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = htim->Instance->SMCR;
+
+  /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
+  if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
+  {
+    /* Check the parameters */
+    assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
+
+    /* Clear the MMS2 bits */
+    tmpcr2 &= ~TIM_CR2_MMS2;
+    /* Select the TRGO2 source*/
+    tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
+  }
+
+  /* Reset the MMS Bits */
+  tmpcr2 &= ~TIM_CR2_MMS;
+  /* Select the TRGO source */
+  tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
+
+  /* Update TIMx CR2 */
+  htim->Instance->CR2 = tmpcr2;
+
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    /* Reset the MSM Bit */
+    tmpsmcr &= ~TIM_SMCR_MSM;
+    /* Set master mode */
+    tmpsmcr |= sMasterConfig->MasterSlaveMode;
+
+    /* Update TIMx SMCR */
+    htim->Instance->SMCR = tmpsmcr;
+  }
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the Break feature, dead time, Lock level, OSSI/OSSR State
+  *         and the AOE(automatic output enable).
+  * @param  htim TIM handle
+  * @param  sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
+  *         contains the BDTR Register configuration  information for the TIM peripheral.
+  * @note   Interrupts can be generated when an active level is detected on the
+  *         break input, the break 2 input or the system break input. Break
+  *         interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
+                                                TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
+{
+  /* Keep this variable initialized to 0 as it is used to configure BDTR register */
+  uint32_t tmpbdtr = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
+  assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
+  assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
+  assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
+  assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
+  assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
+  assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
+  assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
+
+  /* Check input state */
+  __HAL_LOCK(htim);
+
+  /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
+     the OSSI State, the dead time value and the Automatic Output Enable Bit */
+
+  /* Set the BDTR bits */
+  MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
+
+  if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
+  {
+    /* Check the parameters */
+    assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
+    assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
+    assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
+
+    /* Set the BREAK2 input related BDTR bits */
+    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
+    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
+    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
+  }
+
+  /* Set TIMx_BDTR */
+  htim->Instance->BDTR = tmpbdtr;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+#if defined(TIM_BREAK_INPUT_SUPPORT)
+
+/**
+  * @brief  Configures the break input source.
+  * @param  htim TIM handle.
+  * @param  BreakInput Break input to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_BREAKINPUT_BRK: Timer break input
+  *            @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
+  * @param  sBreakInputConfig Break input source configuration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
+                                             uint32_t BreakInput,
+                                             TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
+
+{
+  uint32_t tmporx;
+  uint32_t bkin_enable_mask;
+  uint32_t bkin_polarity_mask;
+  uint32_t bkin_enable_bitpos;
+  uint32_t bkin_polarity_bitpos;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_BREAKINPUT(BreakInput));
+  assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
+  assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
+  if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
+  {
+    assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
+  }
+
+  /* Check input state */
+  __HAL_LOCK(htim);
+
+  switch (sBreakInputConfig->Source)
+  {
+    case TIM_BREAKINPUTSOURCE_BKIN:
+    {
+      bkin_enable_mask = TIM1_AF1_BKINE;
+      bkin_enable_bitpos = TIM1_AF1_BKINE_Pos;
+      bkin_polarity_mask = TIM1_AF1_BKINP;
+      bkin_polarity_bitpos = TIM1_AF1_BKINP_Pos;
+      break;
+    }
+    case TIM_BREAKINPUTSOURCE_COMP1:
+    {
+      bkin_enable_mask = TIM1_AF1_BKCMP1E;
+      bkin_enable_bitpos = TIM1_AF1_BKCMP1E_Pos;
+      bkin_polarity_mask = TIM1_AF1_BKCMP1P;
+      bkin_polarity_bitpos = TIM1_AF1_BKCMP1P_Pos;
+      break;
+    }
+    case TIM_BREAKINPUTSOURCE_COMP2:
+    {
+      bkin_enable_mask = TIM1_AF1_BKCMP2E;
+      bkin_enable_bitpos = TIM1_AF1_BKCMP2E_Pos;
+      bkin_polarity_mask = TIM1_AF1_BKCMP2P;
+      bkin_polarity_bitpos = TIM1_AF1_BKCMP2P_Pos;
+      break;
+    }
+    case TIM_BREAKINPUTSOURCE_DFSDM1:
+    {
+      bkin_enable_mask = TIM1_AF1_BKDF1BK0E;
+      bkin_enable_bitpos = 8U;
+      bkin_polarity_mask = 0U;
+      bkin_polarity_bitpos = 0U;
+      break;
+    }
+
+    default:
+    {
+      bkin_enable_mask = 0U;
+      bkin_polarity_mask = 0U;
+      bkin_enable_bitpos = 0U;
+      bkin_polarity_bitpos = 0U;
+      break;
+    }
+  }
+
+  switch (BreakInput)
+  {
+    case TIM_BREAKINPUT_BRK:
+    {
+      /* Get the TIMx_AF1 register value */
+      tmporx = htim->Instance->AF1;
+
+      /* Enable the break input */
+      tmporx &= ~bkin_enable_mask;
+      tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
+
+      /* Set the break input polarity */
+      if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
+      {
+        tmporx &= ~bkin_polarity_mask;
+        tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
+      }
+
+      /* Set TIMx_AF1 */
+      htim->Instance->AF1 = tmporx;
+      break;
+    }
+    case TIM_BREAKINPUT_BRK2:
+    {
+      /* Get the TIMx_AF2 register value */
+      tmporx = htim->Instance->AF2;
+
+      /* Enable the break input */
+      tmporx &= ~bkin_enable_mask;
+      tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
+
+      /* Set the break input polarity */
+      if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
+      {
+        tmporx &= ~bkin_polarity_mask;
+        tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
+      }
+
+      /* Set TIMx_AF2 */
+      htim->Instance->AF2 = tmporx;
+      break;
+    }
+    default:
+      break;
+  }
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+#endif /*TIM_BREAK_INPUT_SUPPORT */
+
+/**
+  * @brief  Configures the TIMx Remapping input capabilities.
+  * @param  htim TIM handle.
+  * @param  Remap specifies the TIM remapping source.
+  *         For TIM1, the parameter is one of the following values:
+  *            @arg TIM_TIM1_ETR_GPIO:               TIM1_ETR is connected to GPIO
+  *            @arg TIM_TIM1_ETR_COMP1:              TIM1_ETR is connected to COMP1 output
+  *            @arg TIM_TIM1_ETR_COMP2:              TIM1_ETR is connected to COMP2 output
+  *            @arg TIM_TIM1_ETR_ADC1_AWD1:          TIM1_ETR is connected to ADC1 AWD1
+  *            @arg TIM_TIM1_ETR_ADC1_AWD2:          TIM1_ETR is connected to ADC1 AWD2
+  *            @arg TIM_TIM1_ETR_ADC1_AWD3:          TIM1_ETR is connected to ADC1 AWD3
+  *            @arg TIM_TIM1_ETR_ADC3_AWD1:          TIM1_ETR is connected to ADC3 AWD1
+  *            @arg TIM_TIM1_ETR_ADC3_AWD2:          TIM1_ETR is connected to ADC3 AWD2
+  *            @arg TIM_TIM1_ETR_ADC3_AWD3:          TIM1_ETR is connected to ADC3 AWD3
+  *
+  *         For TIM2, the parameter is one of the following values:
+  *            @arg TIM_TIM2_ETR_GPIO:               TIM2_ETR is connected to GPIO
+  *            @arg TIM_TIM2_ETR_COMP1:              TIM2_ETR is connected to COMP1 output
+  *            @arg TIM_TIM2_ETR_COMP2:              TIM2_ETR is connected to COMP2 output
+  *            @arg TIM_TIM2_ETR_LSE:                TIM2_ETR is connected to LSE
+  *            @arg TIM_TIM2_ETR_SAI1_FSA:           TIM2_ETR is connected to SAI1 FS_A
+  *            @arg TIM_TIM2_ETR_SAI1_FSB:           TIM2_ETR is connected to SAI1 FS_B
+  *
+  *         For TIM3, the parameter is one of the following values:
+  *            @arg TIM_TIM3_ETR_GPIO:               TIM3_ETR is connected to GPIO
+  *            @arg TIM_TIM3_ETR_COMP1:              TIM3_ETR is connected to COMP1 output
+  *
+  *         For TIM5, the parameter is one of the following values:
+  *            @arg TIM_TIM5_ETR_GPIO:               TIM5_ETR is connected to GPIO
+  *            @arg TIM_TIM5_ETR_SAI2_FSA:           TIM5_ETR is connected to SAI2 FS_A (*)
+  *            @arg TIM_TIM5_ETR_SAI2_FSB:           TIM5_ETR is connected to SAI2 FS_B (*)
+  *            @arg TIM_TIM5_ETR_SAI4_FSA:           TIM5_ETR is connected to SAI2 FS_A (*)
+  *            @arg TIM_TIM5_ETR_SAI4_FSB:           TIM5_ETR is connected to SAI2 FS_B (*)
+  *
+  *         For TIM8, the parameter is one of the following values:
+  *            @arg TIM_TIM8_ETR_GPIO:               TIM8_ETR is connected to GPIO
+  *            @arg TIM_TIM8_ETR_COMP1:              TIM8_ETR is connected to COMP1 output
+  *            @arg TIM_TIM8_ETR_COMP2:              TIM8_ETR is connected to COMP2 output
+  *            @arg TIM_TIM8_ETR_ADC2_AWD1:          TIM8_ETR is connected to ADC2 AWD1
+  *            @arg TIM_TIM8_ETR_ADC2_AWD2:          TIM8_ETR is connected to ADC2 AWD2
+  *            @arg TIM_TIM8_ETR_ADC2_AWD3:          TIM8_ETR is connected to ADC2 AWD3
+  *            @arg TIM_TIM8_ETR_ADC3_AWD1:          TIM8_ETR is connected to ADC3 AWD1
+  *            @arg TIM_TIM8_ETR_ADC3_AWD2:          TIM8_ETR is connected to ADC3 AWD2
+  *            @arg TIM_TIM8_ETR_ADC3_AWD3:          TIM8_ETR is connected to ADC3 AWD3
+  *
+  *         For TIM23, the parameter is one of the following values: (*)
+  *            @arg TIM_TIM23_ETR_GPIO               TIM23_ETR is connected to GPIO
+  *            @arg TIM_TIM23_ETR_COMP1              TIM23_ETR is connected to COMP1 output
+  *            @arg TIM_TIM23_ETR_COMP2              TIM23_ETR is connected to COMP2 output
+  *
+  *         For TIM24, the parameter is one of the following values: (*)
+  *           @arg TIM_TIM24_ETR_GPIO                TIM24_ETR is connected to GPIO
+  *           @arg TIM_TIM24_ETR_SAI4_FSA            TIM24_ETR is connected to SAI4 FS_A
+  *           @arg TIM_TIM24_ETR_SAI4_FSB            TIM24_ETR is connected to SAI4 FS_B
+  *           @arg TIM_TIM24_ETR_SAI1_FSA            TIM24_ETR is connected to SAI1 FS_A
+  *           @arg TIM_TIM24_ETR_SAI1_FSB            TIM24_ETR is connected to SAI1 FS_B
+  *
+  *         (*)  Value not defined in all devices.
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
+{
+  /* Check parameters */
+  assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_REMAP(Remap));
+
+  __HAL_LOCK(htim);
+
+  MODIFY_REG(htim->Instance->AF1, TIM1_AF1_ETRSEL_Msk, Remap);
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Select the timer input source
+  * @param  htim TIM handle.
+  * @param  Channel specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TI1 input channel
+  *            @arg TIM_CHANNEL_2: TI2 input channel
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  *            @arg TIM_CHANNEL_4: TIM Channel 4
+  * @param  TISelection parameter of the TIM_TISelectionStruct structure is detailed as follows:
+  *         For TIM1, the parameter is one of the following values:
+  *            @arg TIM_TIM1_TI1_GPIO:                TIM1 TI1 is connected to GPIO
+  *            @arg TIM_TIM1_TI1_COMP1:               TIM1 TI1 is connected to COMP1 output
+  *
+  *         For TIM2, the parameter is one of the following values:
+  *            @arg TIM_TIM2_TI4_GPIO:                TIM2 TI4 is connected to GPIO
+  *            @arg TIM_TIM2_TI4_COMP1:               TIM2 TI4 is connected to COMP1 output
+  *            @arg TIM_TIM2_TI4_COMP2:               TIM2 TI4 is connected to COMP2 output
+  *            @arg TIM_TIM2_TI4_COMP1_COMP2:         TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output
+  *
+  *         For TIM3, the parameter is one of the following values:
+  *            @arg TIM_TIM3_TI1_GPIO:                TIM3 TI1 is connected to GPIO
+  *            @arg TIM_TIM3_TI1_COMP1:               TIM3 TI1 is connected to COMP1 output
+  *            @arg TIM_TIM3_TI1_COMP2:               TIM3 TI1 is connected to COMP2 output
+  *            @arg TIM_TIM3_TI1_COMP1_COMP2:         TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output
+  *
+  *         For TIM5, the parameter is one of the following values:
+  *            @arg TIM_TIM5_TI1_GPIO:                TIM5 TI1 is connected to GPIO
+  *            @arg TIM_TIM5_TI1_CAN_TMP:             TIM5 TI1 is connected to CAN TMP
+  *            @arg TIM_TIM5_TI1_CAN_RTP:             TIM5 TI1 is connected to CAN RTP
+  *
+  *         For TIM8, the parameter is one of the following values:
+  *            @arg TIM_TIM8_TI1_GPIO:               TIM8 TI1 is connected to GPIO
+  *            @arg TIM_TIM8_TI1_COMP2:              TIM8 TI1 is connected to COMP2 output
+  *
+  *         For TIM12, the parameter can have the following values: (*)
+  *            @arg TIM_TIM12_TI1_GPIO:              TIM12 TI1 is connected to GPIO
+  *            @arg TIM_TIM12_TI1_SPDIF_FS:          TIM12 TI1 is connected to SPDIF FS
+  *
+  *         For TIM15, the parameter is one of the following values:
+  *            @arg TIM_TIM15_TI1_GPIO:              TIM15 TI1 is connected to GPIO
+  *            @arg TIM_TIM15_TI1_TIM2:              TIM15 TI1 is connected to TIM2 CH1
+  *            @arg TIM_TIM15_TI1_TIM3:              TIM15 TI1 is connected to TIM3 CH1
+  *            @arg TIM_TIM15_TI1_TIM4:              TIM15 TI1 is connected to TIM4 CH1
+  *            @arg TIM_TIM15_TI1_LSE:               TIM15 TI1 is connected to LSE
+  *            @arg TIM_TIM15_TI1_CSI:               TIM15 TI1 is connected to CSI
+  *            @arg TIM_TIM15_TI1_MCO2:              TIM15 TI1 is connected to MCO2
+  *            @arg TIM_TIM15_TI2_GPIO:              TIM15 TI2 is connected to GPIO
+  *            @arg TIM_TIM15_TI2_TIM2:              TIM15 TI2 is connected to TIM2 CH2
+  *            @arg TIM_TIM15_TI2_TIM3:              TIM15 TI2 is connected to TIM3 CH2
+  *            @arg TIM_TIM15_TI2_TIM4:              TIM15 TI2 is connected to TIM4 CH2
+  *
+  *         For TIM16, the parameter can have the following values:
+  *            @arg TIM_TIM16_TI1_GPIO:              TIM16 TI1 is connected to GPIO
+  *            @arg TIM_TIM16_TI1_LSI:               TIM16 TI1 is connected to LSI
+  *            @arg TIM_TIM16_TI1_LSE:               TIM16 TI1 is connected to LSE
+  *            @arg TIM_TIM16_TI1_RTC:               TIM16 TI1 is connected to RTC wakeup interrupt
+  *
+  *         For TIM17, the parameter can have the following values:
+  *            @arg TIM_TIM17_TI1_GPIO:              TIM17 TI1 is connected to GPIO
+  *            @arg TIM_TIM17_TI1_SPDIF_FS:          TIM17 TI1 is connected to SPDIF FS (*)
+  *            @arg TIM_TIM17_TI1_HSE_1MHZ:          TIM17 TI1 is connected to HSE 1MHz
+  *            @arg TIM_TIM17_TI1_MCO1:              TIM17 TI1 is connected to MCO1
+  *
+  *         For TIM23, the parameter can have the following values: (*)
+  *            @arg TIM_TIM23_TI4_GPIO               TIM23_TI4 is connected to GPIO
+  *            @arg TIM_TIM23_TI4_COMP1              TIM23_TI4 is connected to COMP1 output
+  *            @arg TIM_TIM23_TI4_COMP2              TIM23_TI4 is connected to COMP2 output
+  *            @arg TIM_TIM23_TI4_COMP1_COMP2        TIM23_TI4 is connected to COMP2 output
+  *
+  *         For TIM24, the parameter can have the following values: (*)
+  *            @arg TIM_TIM24_TI1_GPIO               TIM24_TI1 is connected to GPIO
+  *            @arg TIM_TIM24_TI1_CAN_TMP            TIM24_TI1 is connected to CAN_TMP
+  *            @arg TIM_TIM24_TI1_CAN_RTP            TIM24_TI1 is connected to CAN_RTP
+  *            @arg TIM_TIM24_TI1_CAN_SOC            TIM24_TI1 is connected to CAN_SOC
+  *
+  *         (*)  Value not defined in all devices. \n
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  assert_param(IS_TIM_TISEL_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_TISEL(TISelection));
+
+  __HAL_LOCK(htim);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+      MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI1SEL, TISelection);
+      break;
+    case TIM_CHANNEL_2:
+      MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI2SEL, TISelection);
+      break;
+    case TIM_CHANNEL_3:
+      MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI3SEL, TISelection);
+      break;
+    case TIM_CHANNEL_4:
+      MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI4SEL, TISelection);
+      break;
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+
+/**
+  * @brief  Group channel 5 and channel 1, 2 or 3
+  * @param  htim TIM handle.
+  * @param  Channels specifies the reference signal(s) the OC5REF is combined with.
+  *         This parameter can be any combination of the following values:
+  *         TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
+  *         TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
+  *         TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
+  *         TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)
+{
+  /* Check parameters */
+  assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_GROUPCH5(Channels));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Clear GC5Cx bit fields */
+  htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1);
+
+  /* Set GC5Cx bit fields */
+  htim->Instance->CCR5 |= Channels;
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
+  * @brief    Extended Callbacks functions
+  *
+@verbatim
+  ==============================================================================
+                    ##### Extended Callbacks functions #####
+  ==============================================================================
+  [..]
+    This section provides Extended TIM callback functions:
+    (+) Timer Commutation callback
+    (+) Timer Break callback
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Hall commutation changed callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_CommutCallback could be implemented in the user file
+   */
+}
+/**
+  * @brief  Hall commutation changed half complete callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Hall Break detection callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_BreakCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Hall Break2 detection callback in non blocking mode
+  * @param  htim: TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_TIMEx_Break2Callback could be implemented in the user file
+   */
+}
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
+  * @brief    Extended Peripheral State functions
+  *
+@verbatim
+  ==============================================================================
+                ##### Extended Peripheral State functions #####
+  ==============================================================================
+  [..]
+    This subsection permits to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the TIM Hall Sensor interface handle state.
+  * @param  htim TIM Hall Sensor handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
+  * @{
+  */
+
+/**
+  * @brief  TIM DMA Commutation callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->CommutationCallback(htim);
+#else
+  HAL_TIMEx_CommutCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Commutation half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->CommutationHalfCpltCallback(htim);
+#else
+  HAL_TIMEx_CommutHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+
+/**
+  * @brief  Enables or disables the TIM Capture Compare Channel xN.
+  * @param  TIMx to select the TIM peripheral
+  * @param  Channel specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1
+  *            @arg TIM_CHANNEL_2: TIM Channel 2
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  * @param  ChannelNState specifies the TIM Channel CCxNE bit new state.
+  *          This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
+  * @retval None
+  */
+static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
+{
+  uint32_t tmp;
+
+  tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
+
+  /* Reset the CCxNE Bit */
+  TIMx->CCER &=  ~tmp;
+
+  /* Set or reset the CCxNE Bit */
+  TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
+}
+/**
+  * @}
+  */
+
+#endif /* HAL_TIM_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c
new file mode 100644
index 00000000..85a0b6e8
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c
@@ -0,0 +1,4115 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_uart.c
+  * @author  MCD Application Team
+  * @brief   UART HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *
+  *
+  @verbatim
+ ===============================================================================
+                        ##### How to use this driver #####
+ ===============================================================================
+  [..]
+    The UART HAL driver can be used as follows:
+
+    (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).
+    (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
+        (++) Enable the USARTx interface clock.
+        (++) UART pins configuration:
+            (+++) Enable the clock for the UART GPIOs.
+            (+++) Configure these UART pins as alternate function pull-up.
+        (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
+             and HAL_UART_Receive_IT() APIs):
+            (+++) Configure the USARTx interrupt priority.
+            (+++) Enable the NVIC USART IRQ handle.
+        (++) UART interrupts handling:
+              -@@-  The specific UART interrupts (Transmission complete interrupt,
+                RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts)
+                are managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT()
+                inside the transmit and receive processes.
+        (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
+             and HAL_UART_Receive_DMA() APIs):
+            (+++) Declare a DMA handle structure for the Tx/Rx channel.
+            (+++) Enable the DMAx interface clock.
+            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+            (+++) Configure the DMA Tx/Rx channel.
+            (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
+            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
+
+    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Prescaler value , Hardware
+        flow control and Mode (Receiver/Transmitter) in the huart handle Init structure.
+
+    (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...)
+        in the huart handle AdvancedInit structure.
+
+    (#) For the UART asynchronous mode, initialize the UART registers by calling
+        the HAL_UART_Init() API.
+
+    (#) For the UART Half duplex mode, initialize the UART registers by calling
+        the HAL_HalfDuplex_Init() API.
+
+    (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers
+        by calling the HAL_LIN_Init() API.
+
+    (#) For the UART Multiprocessor mode, initialize the UART registers
+        by calling the HAL_MultiProcessor_Init() API.
+
+    (#) For the UART RS485 Driver Enabled mode, initialize the UART registers
+        by calling the HAL_RS485Ex_Init() API.
+
+    [..]
+    (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(),
+        also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by
+        calling the customized HAL_UART_MspInit() API.
+
+    ##### Callback registration #####
+    ==================================
+
+    [..]
+    The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1
+    allows the user to configure dynamically the driver callbacks.
+
+    [..]
+    Use Function @ref HAL_UART_RegisterCallback() to register a user callback.
+    Function @ref HAL_UART_RegisterCallback() allows to register following callbacks:
+    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
+    (+) TxCpltCallback            : Tx Complete Callback.
+    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
+    (+) RxCpltCallback            : Rx Complete Callback.
+    (+) ErrorCallback             : Error Callback.
+    (+) AbortCpltCallback         : Abort Complete Callback.
+    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
+    (+) WakeupCallback            : Wakeup Callback.
+    (+) RxFifoFullCallback        : Rx Fifo Full Callback.
+    (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
+    (+) MspInitCallback           : UART MspInit.
+    (+) MspDeInitCallback         : UART MspDeInit.
+    This function takes as parameters the HAL peripheral handle, the Callback ID
+    and a pointer to the user callback function.
+
+    [..]
+    Use function @ref HAL_UART_UnRegisterCallback() to reset a callback to the default
+    weak (surcharged) function.
+    @ref HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+    and the Callback ID.
+    This function allows to reset following callbacks:
+    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
+    (+) TxCpltCallback            : Tx Complete Callback.
+    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
+    (+) RxCpltCallback            : Rx Complete Callback.
+    (+) ErrorCallback             : Error Callback.
+    (+) AbortCpltCallback         : Abort Complete Callback.
+    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
+    (+) WakeupCallback            : Wakeup Callback.
+    (+) RxFifoFullCallback        : Rx Fifo Full Callback.
+    (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
+    (+) MspInitCallback           : UART MspInit.
+    (+) MspDeInitCallback         : UART MspDeInit.
+
+    [..]
+    By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET
+    all callbacks are set to the corresponding weak (surcharged) functions:
+    examples @ref HAL_UART_TxCpltCallback(), @ref HAL_UART_RxHalfCpltCallback().
+    Exception done for MspInit and MspDeInit functions that are respectively
+    reset to the legacy weak (surcharged) functions in the @ref HAL_UART_Init()
+    and @ref HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).
+    If not, MspInit or MspDeInit are not null, the @ref HAL_UART_Init() and @ref HAL_UART_DeInit()
+    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+    [..]
+    Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only.
+    Exception done MspInit/MspDeInit that can be registered/unregistered
+    in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user)
+    MspInit/DeInit callbacks can be used during the Init/DeInit.
+    In that case first register the MspInit/MspDeInit user callbacks
+    using @ref HAL_UART_RegisterCallback() before calling @ref HAL_UART_DeInit()
+    or @ref HAL_UART_Init() function.
+
+    [..]
+    When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or
+    not defined, the callback registration feature is not available
+    and weak (surcharged) callbacks are used.
+
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup UART UART
+  * @brief HAL UART module driver
+  * @{
+  */
+
+#ifdef HAL_UART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup UART_Private_Constants UART Private Constants
+  * @{
+  */
+#define USART_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
+                                      USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \
+                                      USART_CR1_FIFOEN ))                      /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */
+
+#define USART_CR3_FIELDS  ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT| \
+                                      USART_CR3_TXFTCFG | USART_CR3_RXFTCFG ))  /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */
+
+#define LPUART_BRR_MIN  0x00000300U  /* LPUART BRR minimum authorized value */
+#define LPUART_BRR_MAX  0x000FFFFFU  /* LPUART BRR maximum authorized value */
+
+#define UART_BRR_MIN    0x10U        /* UART BRR minimum authorized value */
+#define UART_BRR_MAX    0x0000FFFFU  /* UART BRR maximum authorized value */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup UART_Private_Functions
+  * @{
+  */
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMAError(DMA_HandleTypeDef *hdma);
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_TxISR_8BIT(UART_HandleTypeDef *huart);
+static void UART_TxISR_16BIT(UART_HandleTypeDef *huart);
+static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart);
+static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart);
+static void UART_EndTransmit_IT(UART_HandleTypeDef *huart);
+static void UART_RxISR_8BIT(UART_HandleTypeDef *huart);
+static void UART_RxISR_16BIT(UART_HandleTypeDef *huart);
+static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart);
+static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup UART_Exported_Functions UART Exported Functions
+  * @{
+  */
+
+/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
+    in asynchronous mode.
+      (+) For the asynchronous mode the parameters below can be configured:
+        (++) Baud Rate
+        (++) Word Length
+        (++) Stop Bit
+        (++) Parity: If the parity is enabled, then the MSB bit of the data written
+             in the data register is transmitted but is changed by the parity bit.
+        (++) Hardware flow control
+        (++) Receiver/transmitter modes
+        (++) Over Sampling Method
+        (++) One-Bit Sampling Method
+      (+) For the asynchronous mode, the following advanced features can be configured as well:
+        (++) TX and/or RX pin level inversion
+        (++) data logical level inversion
+        (++) RX and TX pins swap
+        (++) RX overrun detection disabling
+        (++) DMA disabling on RX error
+        (++) MSB first on communication line
+        (++) auto Baud rate detection
+    [..]
+    The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API
+    follow respectively the UART asynchronous, UART Half duplex, UART LIN mode
+    and UART multiprocessor mode configuration procedures (details for the procedures
+    are available in reference manual).
+
+@endverbatim
+
+  Depending on the frame length defined by the M1 and M0 bits (7-bit,
+  8-bit or 9-bit), the possible UART formats are listed in the
+  following table.
+
+  Table 1. UART frame format.
+    +-----------------------------------------------------------------------+
+    |  M1 bit |  M0 bit |  PCE bit  |             UART frame                |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
+    +-----------------------------------------------------------------------+
+
+  * @{
+  */
+
+/**
+  * @brief Initialize the UART mode according to the specified
+  *        parameters in the UART_InitTypeDef and initialize the associated handle.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
+  {
+    /* Check the parameters */
+    assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
+  }
+  else
+  {
+    /* Check the parameters */
+    assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
+  }
+
+  if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    UART_InitCallbacksToDefault(huart);
+
+    if (huart->MspInitCallback == NULL)
+    {
+      huart->MspInitCallback = HAL_UART_MspInit;
+    }
+
+    /* Init the low level hardware */
+    huart->MspInitCallback(huart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the UART Communication parameters */
+  if (UART_SetConfig(huart) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+  {
+    UART_AdvFeatureConfig(huart);
+  }
+
+  /* In asynchronous mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
+  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+
+  __HAL_UART_ENABLE(huart);
+
+  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+  return (UART_CheckIdleState(huart));
+}
+
+/**
+  * @brief Initialize the half-duplex mode according to the specified
+  *        parameters in the UART_InitTypeDef and creates the associated handle.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check UART instance */
+  assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));
+
+  if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    UART_InitCallbacksToDefault(huart);
+
+    if (huart->MspInitCallback == NULL)
+    {
+      huart->MspInitCallback = HAL_UART_MspInit;
+    }
+
+    /* Init the low level hardware */
+    huart->MspInitCallback(huart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the UART Communication parameters */
+  if (UART_SetConfig(huart) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+  {
+    UART_AdvFeatureConfig(huart);
+  }
+
+  /* In half-duplex mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - SCEN and IREN bits in the USART_CR3 register.*/
+  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));
+
+  /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
+  SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
+
+  __HAL_UART_ENABLE(huart);
+
+  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+  return (UART_CheckIdleState(huart));
+}
+
+
+/**
+  * @brief Initialize the LIN mode according to the specified
+  *        parameters in the UART_InitTypeDef and creates the associated handle.
+  * @param huart             UART handle.
+  * @param BreakDetectLength Specifies the LIN break detection length.
+  *        This parameter can be one of the following values:
+  *          @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection
+  *          @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the LIN UART instance */
+  assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
+  /* Check the Break detection length parameter */
+  assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
+
+  /* LIN mode limited to 16-bit oversampling only */
+  if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
+  {
+    return HAL_ERROR;
+  }
+  /* LIN mode limited to 8-bit data length */
+  if (huart->Init.WordLength != UART_WORDLENGTH_8B)
+  {
+    return HAL_ERROR;
+  }
+
+  if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    UART_InitCallbacksToDefault(huart);
+
+    if (huart->MspInitCallback == NULL)
+    {
+      huart->MspInitCallback = HAL_UART_MspInit;
+    }
+
+    /* Init the low level hardware */
+    huart->MspInitCallback(huart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the UART Communication parameters */
+  if (UART_SetConfig(huart) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+  {
+    UART_AdvFeatureConfig(huart);
+  }
+
+  /* In LIN mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - SCEN and IREN bits in the USART_CR3 register.*/
+  CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));
+
+  /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
+  SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);
+
+  /* Set the USART LIN Break detection length. */
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);
+
+  __HAL_UART_ENABLE(huart);
+
+  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+  return (UART_CheckIdleState(huart));
+}
+
+
+/**
+  * @brief Initialize the multiprocessor mode according to the specified
+  *        parameters in the UART_InitTypeDef and initialize the associated handle.
+  * @param huart        UART handle.
+  * @param Address      UART node address (4-, 6-, 7- or 8-bit long).
+  * @param WakeUpMethod Specifies the UART wakeup method.
+  *        This parameter can be one of the following values:
+  *          @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection
+  *          @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark
+  * @note  If the user resorts to idle line detection wake up, the Address parameter
+  *        is useless and ignored by the initialization function.
+  * @note  If the user resorts to address mark wake up, the address length detection
+  *        is configured by default to 4 bits only. For the UART to be able to
+  *        manage 6-, 7- or 8-bit long addresses detection, the API
+  *        HAL_MultiProcessorEx_AddressLength_Set() must be called after
+  *        HAL_MultiProcessor_Init().
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the wake up method parameter */
+  assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
+
+  if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    UART_InitCallbacksToDefault(huart);
+
+    if (huart->MspInitCallback == NULL)
+    {
+      huart->MspInitCallback = HAL_UART_MspInit;
+    }
+
+    /* Init the low level hardware */
+    huart->MspInitCallback(huart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the UART Communication parameters */
+  if (UART_SetConfig(huart) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+  {
+    UART_AdvFeatureConfig(huart);
+  }
+
+  /* In multiprocessor mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - SCEN, HDSEL and IREN  bits in the USART_CR3 register. */
+  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+
+  if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK)
+  {
+    /* If address mark wake up method is chosen, set the USART address node */
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS));
+  }
+
+  /* Set the wake up method by setting the WAKE bit in the CR1 register */
+  MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);
+
+  __HAL_UART_ENABLE(huart);
+
+  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+  return (UART_CheckIdleState(huart));
+}
+
+
+/**
+  * @brief DeInitialize the UART peripheral.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  __HAL_UART_DISABLE(huart);
+
+  huart->Instance->CR1 = 0x0U;
+  huart->Instance->CR2 = 0x0U;
+  huart->Instance->CR3 = 0x0U;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  if (huart->MspDeInitCallback == NULL)
+  {
+    huart->MspDeInitCallback = HAL_UART_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  huart->MspDeInitCallback(huart);
+#else
+  /* DeInit the low level hardware */
+  HAL_UART_MspDeInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+  huart->gState = HAL_UART_STATE_RESET;
+  huart->RxState = HAL_UART_STATE_RESET;
+
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Initialize the UART MSP.
+  * @param huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_MspInit can be implemented in the user file
+   */
+}
+
+/**
+  * @brief DeInitialize the UART MSP.
+  * @param huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_MspDeInit can be implemented in the user file
+   */
+}
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User UART Callback
+  *         To be used instead of the weak predefined callback
+  * @param  huart uart handle
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+  *           @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+  *           @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+  *           @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+  *           @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
+  *           @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+  *           @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+  *           @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+  *           @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
+  *           @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
+  *           @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
+  *           @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
+  *           @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
+                                            pUART_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  __HAL_LOCK(huart);
+
+  if (huart->gState == HAL_UART_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_UART_TX_HALFCOMPLETE_CB_ID :
+        huart->TxHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_TX_COMPLETE_CB_ID :
+        huart->TxCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_RX_HALFCOMPLETE_CB_ID :
+        huart->RxHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_RX_COMPLETE_CB_ID :
+        huart->RxCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_ERROR_CB_ID :
+        huart->ErrorCallback = pCallback;
+        break;
+
+      case HAL_UART_ABORT_COMPLETE_CB_ID :
+        huart->AbortCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
+        huart->AbortTransmitCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
+        huart->AbortReceiveCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_WAKEUP_CB_ID :
+        huart->WakeupCallback = pCallback;
+        break;
+
+      case HAL_UART_RX_FIFO_FULL_CB_ID :
+        huart->RxFifoFullCallback = pCallback;
+        break;
+
+      case HAL_UART_TX_FIFO_EMPTY_CB_ID :
+        huart->TxFifoEmptyCallback = pCallback;
+        break;
+
+      case HAL_UART_MSPINIT_CB_ID :
+        huart->MspInitCallback = pCallback;
+        break;
+
+      case HAL_UART_MSPDEINIT_CB_ID :
+        huart->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_UART_MSPINIT_CB_ID :
+        huart->MspInitCallback = pCallback;
+        break;
+
+      case HAL_UART_MSPDEINIT_CB_ID :
+        huart->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+    status =  HAL_ERROR;
+  }
+
+  __HAL_UNLOCK(huart);
+
+  return status;
+}
+
+/**
+  * @brief  Unregister an UART Callback
+  *         UART callaback is redirected to the weak predefined callback
+  * @param  huart uart handle
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+  *           @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+  *           @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+  *           @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+  *           @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
+  *           @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+  *           @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+  *           @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+  *           @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
+  *           @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
+  *           @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
+  *           @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
+  *           @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  __HAL_LOCK(huart);
+
+  if (HAL_UART_STATE_READY == huart->gState)
+  {
+    switch (CallbackID)
+    {
+      case HAL_UART_TX_HALFCOMPLETE_CB_ID :
+        huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback;               /* Legacy weak  TxHalfCpltCallback       */
+        break;
+
+      case HAL_UART_TX_COMPLETE_CB_ID :
+        huart->TxCpltCallback = HAL_UART_TxCpltCallback;                       /* Legacy weak TxCpltCallback            */
+        break;
+
+      case HAL_UART_RX_HALFCOMPLETE_CB_ID :
+        huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback;               /* Legacy weak RxHalfCpltCallback        */
+        break;
+
+      case HAL_UART_RX_COMPLETE_CB_ID :
+        huart->RxCpltCallback = HAL_UART_RxCpltCallback;                       /* Legacy weak RxCpltCallback            */
+        break;
+
+      case HAL_UART_ERROR_CB_ID :
+        huart->ErrorCallback = HAL_UART_ErrorCallback;                         /* Legacy weak ErrorCallback             */
+        break;
+
+      case HAL_UART_ABORT_COMPLETE_CB_ID :
+        huart->AbortCpltCallback = HAL_UART_AbortCpltCallback;                 /* Legacy weak AbortCpltCallback         */
+        break;
+
+      case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
+        huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+        break;
+
+      case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
+        huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback;   /* Legacy weak AbortReceiveCpltCallback  */
+        break;
+
+      case HAL_UART_WAKEUP_CB_ID :
+        huart->WakeupCallback = HAL_UARTEx_WakeupCallback;                     /* Legacy weak WakeupCallback            */
+        break;
+
+      case HAL_UART_RX_FIFO_FULL_CB_ID :
+        huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback;             /* Legacy weak RxFifoFullCallback        */
+        break;
+
+      case HAL_UART_TX_FIFO_EMPTY_CB_ID :
+        huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback;           /* Legacy weak TxFifoEmptyCallback       */
+        break;
+
+      case HAL_UART_MSPINIT_CB_ID :
+        huart->MspInitCallback = HAL_UART_MspInit;                             /* Legacy weak MspInitCallback           */
+        break;
+
+      case HAL_UART_MSPDEINIT_CB_ID :
+        huart->MspDeInitCallback = HAL_UART_MspDeInit;                         /* Legacy weak MspDeInitCallback         */
+        break;
+
+      default :
+        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_UART_STATE_RESET == huart->gState)
+  {
+    switch (CallbackID)
+    {
+      case HAL_UART_MSPINIT_CB_ID :
+        huart->MspInitCallback = HAL_UART_MspInit;
+        break;
+
+      case HAL_UART_MSPDEINIT_CB_ID :
+        huart->MspDeInitCallback = HAL_UART_MspDeInit;
+        break;
+
+      default :
+        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+    status =  HAL_ERROR;
+  }
+
+  __HAL_UNLOCK(huart);
+
+  return status;
+}
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup UART_Exported_Functions_Group2 IO operation functions
+  * @brief UART Transmit/Receive functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    This subsection provides a set of functions allowing to manage the UART asynchronous
+    and Half duplex data transfers.
+
+    (#) There are two mode of transfer:
+       (+) Blocking mode: The communication is performed in polling mode.
+           The HAL status of all data processing is returned by the same function
+           after finishing transfer.
+       (+) Non-Blocking mode: The communication is performed using Interrupts
+           or DMA, These API's return the HAL status.
+           The end of the data processing will be indicated through the
+           dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
+           using DMA mode.
+           The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
+           will be executed respectively at the end of the transmit or Receive process
+           The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected
+
+    (#) Blocking mode API's are :
+        (+) HAL_UART_Transmit()
+        (+) HAL_UART_Receive()
+
+    (#) Non-Blocking mode API's with Interrupt are :
+        (+) HAL_UART_Transmit_IT()
+        (+) HAL_UART_Receive_IT()
+        (+) HAL_UART_IRQHandler()
+
+    (#) Non-Blocking mode API's with DMA are :
+        (+) HAL_UART_Transmit_DMA()
+        (+) HAL_UART_Receive_DMA()
+        (+) HAL_UART_DMAPause()
+        (+) HAL_UART_DMAResume()
+        (+) HAL_UART_DMAStop()
+
+    (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
+        (+) HAL_UART_TxHalfCpltCallback()
+        (+) HAL_UART_TxCpltCallback()
+        (+) HAL_UART_RxHalfCpltCallback()
+        (+) HAL_UART_RxCpltCallback()
+        (+) HAL_UART_ErrorCallback()
+
+    (#) Non-Blocking mode transfers could be aborted using Abort API's :
+        (+) HAL_UART_Abort()
+        (+) HAL_UART_AbortTransmit()
+        (+) HAL_UART_AbortReceive()
+        (+) HAL_UART_Abort_IT()
+        (+) HAL_UART_AbortTransmit_IT()
+        (+) HAL_UART_AbortReceive_IT()
+
+    (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
+        (+) HAL_UART_AbortCpltCallback()
+        (+) HAL_UART_AbortTransmitCpltCallback()
+        (+) HAL_UART_AbortReceiveCpltCallback()
+
+    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+        Errors are handled as follows :
+       (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+           to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
+           Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+           and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side.
+           If user wants to abort it, Abort services should be called by user.
+       (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+           This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
+           Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed.
+
+    -@- In the Half duplex communication, it is forbidden to run the transmit
+        and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Send an amount of data in blocking mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 provided through pData.
+  * @note When FIFO mode is enabled, writing a data in the TDR register adds one
+  *       data to the TXFIFO. Write operations to the TDR register are performed
+  *       when TXFNF flag is set. From hardware perspective, TXFNF flag and
+  *       TXE are mapped on the same bit-field.
+  * @param huart   UART handle.
+  * @param pData   Pointer to data buffer (u8 or u16 data elements).
+  * @param Size    Amount of data elements (u8 or u16) to be sent.
+  * @param Timeout Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint8_t  *pdata8bits;
+  uint16_t *pdata16bits;
+  uint32_t tickstart;
+
+  /* Check that a Tx process is not already ongoing */
+  if (huart->gState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    __HAL_LOCK(huart);
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->gState = HAL_UART_STATE_BUSY_TX;
+
+    /* Init tickstart for timeout managment*/
+    tickstart = HAL_GetTick();
+
+    huart->TxXferSize  = Size;
+    huart->TxXferCount = Size;
+
+    /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+    {
+      pdata8bits  = NULL;
+      pdata16bits = (uint16_t *) pData;
+    }
+    else
+    {
+      pdata8bits  = pData;
+      pdata16bits = NULL;
+    }
+
+    while (huart->TxXferCount > 0U)
+    {
+      if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+      if (pdata8bits == NULL)
+      {
+        huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
+        pdata16bits++;
+      }
+      else
+      {
+        huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
+        pdata8bits++;
+      }
+      huart->TxXferCount--;
+    }
+
+    if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    /* At end of Tx process, restore huart->gState to Ready */
+    huart->gState = HAL_UART_STATE_READY;
+
+    __HAL_UNLOCK(huart);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in blocking mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the received data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 available through pData.
+  * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO
+  *       is not empty. Read operations from the RDR register are performed when
+  *       RXFNE flag is set. From hardware perspective, RXFNE flag and
+  *       RXNE are mapped on the same bit-field.
+  * @param huart   UART handle.
+  * @param pData   Pointer to data buffer (u8 or u16 data elements).
+  * @param Size    Amount of data elements (u8 or u16) to be received.
+  * @param Timeout Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint8_t  *pdata8bits;
+  uint16_t *pdata16bits;
+  uint16_t uhMask;
+  uint32_t tickstart;
+
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    __HAL_LOCK(huart);
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+    /* Init tickstart for timeout managment*/
+    tickstart = HAL_GetTick();
+
+    huart->RxXferSize  = Size;
+    huart->RxXferCount = Size;
+
+    /* Computation of UART mask to apply to RDR register */
+    UART_MASK_COMPUTATION(huart);
+    uhMask = huart->Mask;
+
+    /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+    {
+      pdata8bits  = NULL;
+      pdata16bits = (uint16_t *) pData;
+    }
+    else
+    {
+      pdata8bits  = pData;
+      pdata16bits = NULL;
+    }
+
+    /* as long as data have to be received */
+    while (huart->RxXferCount > 0U)
+    {
+      if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+      if (pdata8bits == NULL)
+      {
+        *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);
+        pdata16bits++;
+      }
+      else
+      {
+        *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
+        pdata8bits++;
+      }
+      huart->RxXferCount--;
+    }
+
+    /* At end of Rx process, restore huart->RxState to Ready */
+    huart->RxState = HAL_UART_STATE_READY;
+
+    __HAL_UNLOCK(huart);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Send an amount of data in interrupt mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 provided through pData.
+  * @param huart UART handle.
+  * @param pData Pointer to data buffer (u8 or u16 data elements).
+  * @param Size  Amount of data elements (u8 or u16) to be sent.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Tx process is not already ongoing */
+  if (huart->gState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    __HAL_LOCK(huart);
+
+    huart->pTxBuffPtr  = pData;
+    huart->TxXferSize  = Size;
+    huart->TxXferCount = Size;
+    huart->TxISR       = NULL;
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->gState = HAL_UART_STATE_BUSY_TX;
+
+    /* Configure Tx interrupt processing */
+    if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+    {
+      /* Set the Tx ISR function pointer according to the data word length */
+      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+      {
+        huart->TxISR = UART_TxISR_16BIT_FIFOEN;
+      }
+      else
+      {
+        huart->TxISR = UART_TxISR_8BIT_FIFOEN;
+      }
+
+      __HAL_UNLOCK(huart);
+
+      /* Enable the TX FIFO threshold interrupt */
+      SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+    }
+    else
+    {
+      /* Set the Tx ISR function pointer according to the data word length */
+      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+      {
+        huart->TxISR = UART_TxISR_16BIT;
+      }
+      else
+      {
+        huart->TxISR = UART_TxISR_8BIT;
+      }
+
+      __HAL_UNLOCK(huart);
+
+      /* Enable the Transmit Data Register Empty interrupt */
+      SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in interrupt mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the received data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 available through pData.
+  * @param huart UART handle.
+  * @param pData Pointer to data buffer (u8 or u16 data elements).
+  * @param Size  Amount of data elements (u8 or u16) to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    __HAL_LOCK(huart);
+
+    huart->pRxBuffPtr  = pData;
+    huart->RxXferSize  = Size;
+    huart->RxXferCount = Size;
+    huart->RxISR       = NULL;
+
+    /* Computation of UART mask to apply to RDR register */
+    UART_MASK_COMPUTATION(huart);
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+    /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+    SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+    /* Configure Rx interrupt processing*/
+    if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess))
+    {
+      /* Set the Rx ISR function pointer according to the data word length */
+      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+      {
+        huart->RxISR = UART_RxISR_16BIT_FIFOEN;
+      }
+      else
+      {
+        huart->RxISR = UART_RxISR_8BIT_FIFOEN;
+      }
+
+      __HAL_UNLOCK(huart);
+
+      /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */
+      SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+      SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+    }
+    else
+    {
+      /* Set the Rx ISR function pointer according to the data word length */
+      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+      {
+        huart->RxISR = UART_RxISR_16BIT;
+      }
+      else
+      {
+        huart->RxISR = UART_RxISR_8BIT;
+      }
+
+      __HAL_UNLOCK(huart);
+
+      /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
+      SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Send an amount of data in DMA mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 provided through pData.
+  * @param huart UART handle.
+  * @param pData Pointer to data buffer (u8 or u16 data elements).
+  * @param Size  Amount of data elements (u8 or u16) to be sent.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Tx process is not already ongoing */
+  if (huart->gState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    __HAL_LOCK(huart);
+
+    huart->pTxBuffPtr  = pData;
+    huart->TxXferSize  = Size;
+    huart->TxXferCount = Size;
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->gState = HAL_UART_STATE_BUSY_TX;
+
+    if (huart->hdmatx != NULL)
+    {
+      /* Set the UART DMA transfer complete callback */
+      huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
+
+      /* Set the UART DMA Half transfer complete callback */
+      huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
+
+      /* Set the DMA error callback */
+      huart->hdmatx->XferErrorCallback = UART_DMAError;
+
+      /* Set the DMA abort callback */
+      huart->hdmatx->XferAbortCallback = NULL;
+
+      /* Enable the UART transmit DMA channel */
+      if (HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size) != HAL_OK)
+      {
+        /* Set error code to DMA */
+        huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+        __HAL_UNLOCK(huart);
+
+        /* Restore huart->gState to ready */
+        huart->gState = HAL_UART_STATE_READY;
+
+        return HAL_ERROR;
+      }
+    }
+    /* Clear the TC flag in the ICR register */
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
+
+    __HAL_UNLOCK(huart);
+
+    /* Enable the DMA transfer for transmit request by setting the DMAT bit
+    in the UART CR3 register */
+    SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in DMA mode.
+  * @note   When the UART parity is enabled (PCE = 1), the received data contain
+  *         the parity bit (MSB position).
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the received data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 available through pData.
+  * @param huart UART handle.
+  * @param pData Pointer to data buffer (u8 or u16 data elements).
+  * @param Size  Amount of data elements (u8 or u16) to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    __HAL_LOCK(huart);
+
+    huart->pRxBuffPtr = pData;
+    huart->RxXferSize = Size;
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+    if (huart->hdmarx != NULL)
+    {
+      /* Set the UART DMA transfer complete callback */
+      huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
+
+      /* Set the UART DMA Half transfer complete callback */
+      huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
+
+      /* Set the DMA error callback */
+      huart->hdmarx->XferErrorCallback = UART_DMAError;
+
+      /* Set the DMA abort callback */
+      huart->hdmarx->XferAbortCallback = NULL;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK)
+      {
+        /* Set error code to DMA */
+        huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+        __HAL_UNLOCK(huart);
+
+        /* Restore huart->gState to ready */
+        huart->gState = HAL_UART_STATE_READY;
+
+        return HAL_ERROR;
+      }
+    }
+    __HAL_UNLOCK(huart);
+
+    /* Enable the UART Parity Error Interrupt */
+    SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+
+    /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+    SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+    /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+    in the UART CR3 register */
+    SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Pause the DMA Transfer.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
+{
+  const HAL_UART_StateTypeDef gstate = huart->gState;
+  const HAL_UART_StateTypeDef rxstate = huart->RxState;
+
+  __HAL_LOCK(huart);
+
+  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
+      (gstate == HAL_UART_STATE_BUSY_TX))
+  {
+    /* Disable the UART DMA Tx request */
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+  }
+  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
+      (rxstate == HAL_UART_STATE_BUSY_RX))
+  {
+    /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+    CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+    /* Disable the UART DMA Rx request */
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+  }
+
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Resume the DMA Transfer.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
+{
+  __HAL_LOCK(huart);
+
+  if (huart->gState == HAL_UART_STATE_BUSY_TX)
+  {
+    /* Enable the UART DMA Tx request */
+    SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+  }
+  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+  {
+    /* Clear the Overrun flag before resuming the Rx transfer */
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+
+    /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
+    SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+    SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+    /* Enable the UART DMA Rx request */
+    SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+  }
+
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Stop the DMA Transfer.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
+{
+  /* The Lock is not implemented on this API to allow the user application
+     to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() /
+     HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback:
+     indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
+     interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
+     the stream and the corresponding call back is executed. */
+
+  const HAL_UART_StateTypeDef gstate = huart->gState;
+  const HAL_UART_StateTypeDef rxstate = huart->RxState;
+
+  /* Stop UART DMA Tx request if ongoing */
+  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
+      (gstate == HAL_UART_STATE_BUSY_TX))
+  {
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx channel */
+    if (huart->hdmatx != NULL)
+    {
+      if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+
+    UART_EndTxTransfer(huart);
+  }
+
+  /* Stop UART DMA Rx request if ongoing */
+  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
+      (rxstate == HAL_UART_STATE_BUSY_RX))
+  {
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx channel */
+    if (huart->hdmarx != NULL)
+    {
+      if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+
+    UART_EndRxTransfer(huart);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing transfers (blocking mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Tx and Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
+{
+  /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE);
+
+  /* Disable the UART DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+  {
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
+    if (huart->hdmatx != NULL)
+    {
+      /* Set the UART DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      huart->hdmatx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /* Disable the UART DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
+    if (huart->hdmarx != NULL)
+    {
+      /* Set the UART DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      huart->hdmarx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /* Reset Tx and Rx transfer counters */
+  huart->TxXferCount = 0U;
+  huart->RxXferCount = 0U;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+  /* Flush the whole TX FIFO (if needed) */
+  if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+  {
+    __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+  }
+
+  /* Discard the received data */
+  __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+  /* Restore huart->gState and huart->RxState to Ready */
+  huart->gState  = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Transmit transfer (blocking mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Tx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
+{
+  /* Disable TCIE, TXEIE and TXFTIE interrupts */
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
+  CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+
+  /* Disable the UART DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+  {
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
+    if (huart->hdmatx != NULL)
+    {
+      /* Set the UART DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      huart->hdmatx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /* Reset Tx transfer counter */
+  huart->TxXferCount = 0U;
+
+  /* Flush the whole TX FIFO (if needed) */
+  if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+  {
+    __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+  }
+
+  /* Restore huart->gState to Ready */
+  huart->gState = HAL_UART_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Receive transfer (blocking mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
+{
+  /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
+  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE);
+
+  /* Disable the UART DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
+    if (huart->hdmarx != NULL)
+    {
+      /* Set the UART DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      huart->hdmarx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /* Reset Rx transfer counter */
+  huart->RxXferCount = 0U;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+  /* Discard the received data */
+  __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+  /* Restore huart->RxState to Ready */
+  huart->RxState = HAL_UART_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing transfers (Interrupt mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Tx and Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
+{
+  uint32_t abortcplt = 1U;
+
+  /* Disable interrupts */
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE | USART_CR1_TXEIE_TXFNFIE));
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
+
+  /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
+     before any call to DMA Abort functions */
+  /* DMA Tx Handle is valid */
+  if (huart->hdmatx != NULL)
+  {
+    /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
+       Otherwise, set it to NULL */
+    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+    {
+      huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback;
+    }
+    else
+    {
+      huart->hdmatx->XferAbortCallback = NULL;
+    }
+  }
+  /* DMA Rx Handle is valid */
+  if (huart->hdmarx != NULL)
+  {
+    /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
+       Otherwise, set it to NULL */
+    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+    {
+      huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback;
+    }
+    else
+    {
+      huart->hdmarx->XferAbortCallback = NULL;
+    }
+  }
+
+  /* Disable the UART DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+  {
+    /* Disable DMA Tx at UART level */
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
+    if (huart->hdmatx != NULL)
+    {
+      /* UART Tx DMA Abort callback has already been initialised :
+         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA TX */
+      if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
+      {
+        huart->hdmatx->XferAbortCallback = NULL;
+      }
+      else
+      {
+        abortcplt = 0U;
+      }
+    }
+  }
+
+  /* Disable the UART DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
+    if (huart->hdmarx != NULL)
+    {
+      /* UART Rx DMA Abort callback has already been initialised :
+         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA RX */
+      if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+      {
+        huart->hdmarx->XferAbortCallback = NULL;
+        abortcplt = 1U;
+      }
+      else
+      {
+        abortcplt = 0U;
+      }
+    }
+  }
+
+  /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+  if (abortcplt == 1U)
+  {
+    /* Reset Tx and Rx transfer counters */
+    huart->TxXferCount = 0U;
+    huart->RxXferCount = 0U;
+
+    /* Clear ISR function pointers */
+    huart->RxISR = NULL;
+    huart->TxISR = NULL;
+
+    /* Reset errorCode */
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+    /* Clear the Error flags in the ICR register */
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+    /* Flush the whole TX FIFO (if needed) */
+    if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+    {
+      __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+    }
+
+    /* Discard the received data */
+    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+    /* Restore huart->gState and huart->RxState to Ready */
+    huart->gState  = HAL_UART_STATE_READY;
+    huart->RxState = HAL_UART_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Abort complete callback */
+    huart->AbortCpltCallback(huart);
+#else
+    /* Call legacy weak Abort complete callback */
+    HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Transmit transfer (Interrupt mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Tx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
+{
+  /* Disable interrupts */
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
+  CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+
+  /* Disable the UART DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+  {
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
+    if (huart->hdmatx != NULL)
+    {
+      /* Set the UART DMA Abort callback :
+         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+      huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback;
+
+      /* Abort DMA TX */
+      if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
+      {
+        /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */
+        huart->hdmatx->XferAbortCallback(huart->hdmatx);
+      }
+    }
+    else
+    {
+      /* Reset Tx transfer counter */
+      huart->TxXferCount = 0U;
+
+      /* Clear TxISR function pointers */
+      huart->TxISR = NULL;
+
+      /* Restore huart->gState to Ready */
+      huart->gState = HAL_UART_STATE_READY;
+
+      /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+      /* Call registered Abort Transmit Complete Callback */
+      huart->AbortTransmitCpltCallback(huart);
+#else
+      /* Call legacy weak Abort Transmit Complete Callback */
+      HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+    }
+  }
+  else
+  {
+    /* Reset Tx transfer counter */
+    huart->TxXferCount = 0U;
+
+    /* Clear TxISR function pointers */
+    huart->TxISR = NULL;
+
+    /* Flush the whole TX FIFO (if needed) */
+    if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+    {
+      __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+    }
+
+    /* Restore huart->gState to Ready */
+    huart->gState = HAL_UART_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Abort Transmit Complete Callback */
+    huart->AbortTransmitCpltCallback(huart);
+#else
+    /* Call legacy weak Abort Transmit Complete Callback */
+    HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Receive transfer (Interrupt mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
+{
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+  /* Disable the UART DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
+    if (huart->hdmarx != NULL)
+    {
+      /* Set the UART DMA Abort callback :
+         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+      huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;
+
+      /* Abort DMA RX */
+      if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+      {
+        /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
+        huart->hdmarx->XferAbortCallback(huart->hdmarx);
+      }
+    }
+    else
+    {
+      /* Reset Rx transfer counter */
+      huart->RxXferCount = 0U;
+
+      /* Clear RxISR function pointer */
+      huart->pRxBuffPtr = NULL;
+
+      /* Clear the Error flags in the ICR register */
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+      /* Discard the received data */
+      __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+      /* Restore huart->RxState to Ready */
+      huart->RxState = HAL_UART_STATE_READY;
+
+      /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+      /* Call registered Abort Receive Complete Callback */
+      huart->AbortReceiveCpltCallback(huart);
+#else
+      /* Call legacy weak Abort Receive Complete Callback */
+      HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+    }
+  }
+  else
+  {
+    /* Reset Rx transfer counter */
+    huart->RxXferCount = 0U;
+
+    /* Clear RxISR function pointer */
+    huart->pRxBuffPtr = NULL;
+
+    /* Clear the Error flags in the ICR register */
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+    /* Restore huart->RxState to Ready */
+    huart->RxState = HAL_UART_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Abort Receive Complete Callback */
+    huart->AbortReceiveCpltCallback(huart);
+#else
+    /* Call legacy weak Abort Receive Complete Callback */
+    HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Handle UART interrupt request.
+  * @param huart UART handle.
+  * @retval None
+  */
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
+{
+  uint32_t isrflags   = READ_REG(huart->Instance->ISR);
+  uint32_t cr1its     = READ_REG(huart->Instance->CR1);
+  uint32_t cr3its     = READ_REG(huart->Instance->CR3);
+
+  uint32_t errorflags;
+  uint32_t errorcode;
+
+  /* If no error occurs */
+  errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
+  if (errorflags == 0U)
+  {
+    /* UART in mode Receiver ---------------------------------------------------*/
+    if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
+        && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+            || ((cr3its & USART_CR3_RXFTIE) != 0U)))
+    {
+      if (huart->RxISR != NULL)
+      {
+        huart->RxISR(huart);
+      }
+      return;
+    }
+  }
+
+  /* If some errors occur */
+  if ((errorflags != 0U)
+      && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
+           || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))))
+  {
+    /* UART parity error interrupt occurred -------------------------------------*/
+    if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+    {
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
+
+      huart->ErrorCode |= HAL_UART_ERROR_PE;
+    }
+
+    /* UART frame error interrupt occurred --------------------------------------*/
+    if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+    {
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
+
+      huart->ErrorCode |= HAL_UART_ERROR_FE;
+    }
+
+    /* UART noise error interrupt occurred --------------------------------------*/
+    if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+    {
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
+
+      huart->ErrorCode |= HAL_UART_ERROR_NE;
+    }
+
+    /* UART Over-Run interrupt occurred -----------------------------------------*/
+    if (((isrflags & USART_ISR_ORE) != 0U)
+        && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
+            ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)))
+    {
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+
+      huart->ErrorCode |= HAL_UART_ERROR_ORE;
+    }
+
+    /* UART Receiver Timeout interrupt occurred ---------------------------------*/
+    if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
+    {
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
+
+      huart->ErrorCode |= HAL_UART_ERROR_RTO;
+    }
+
+    /* Call UART Error Call back function if need be ----------------------------*/
+    if (huart->ErrorCode != HAL_UART_ERROR_NONE)
+    {
+      /* UART in mode Receiver --------------------------------------------------*/
+      if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
+          && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+              || ((cr3its & USART_CR3_RXFTIE) != 0U)))
+      {
+        if (huart->RxISR != NULL)
+        {
+          huart->RxISR(huart);
+        }
+      }
+
+      /* If Error is to be considered as blocking :
+          - Receiver Timeout error in Reception
+          - Overrun error in Reception
+          - any error occurs in DMA mode reception
+      */
+      errorcode = huart->ErrorCode;
+      if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
+          ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
+      {
+        /* Blocking error : transfer is aborted
+           Set the UART state ready to be able to start again the process,
+           Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+        UART_EndRxTransfer(huart);
+
+        /* Disable the UART DMA Rx request if enabled */
+        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+        {
+          CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+          /* Abort the UART DMA Rx channel */
+          if (huart->hdmarx != NULL)
+          {
+            /* Set the UART DMA Abort callback :
+               will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
+            huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
+
+            /* Abort DMA RX */
+            if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+            {
+              /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
+              huart->hdmarx->XferAbortCallback(huart->hdmarx);
+            }
+          }
+          else
+          {
+            /* Call user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+            /*Call registered error callback*/
+            huart->ErrorCallback(huart);
+#else
+            /*Call legacy weak error callback*/
+            HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+          }
+        }
+        else
+        {
+          /* Call user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+          /*Call registered error callback*/
+          huart->ErrorCallback(huart);
+#else
+          /*Call legacy weak error callback*/
+          HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+        }
+      }
+      else
+      {
+        /* Non Blocking error : transfer could go on.
+           Error is notified to user through user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered error callback*/
+        huart->ErrorCallback(huart);
+#else
+        /*Call legacy weak error callback*/
+        HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+        huart->ErrorCode = HAL_UART_ERROR_NONE;
+      }
+    }
+    return;
+
+  } /* End if some error occurs */
+
+  /* UART wakeup from Stop mode interrupt occurred ---------------------------*/
+  if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
+  {
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
+
+    /* UART Rx state is not reset as a reception process might be ongoing.
+       If UART handle state fields need to be reset to READY, this could be done in Wakeup callback */
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Wakeup Callback */
+    huart->WakeupCallback(huart);
+#else
+    /* Call legacy weak Wakeup Callback */
+    HAL_UARTEx_WakeupCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+    return;
+  }
+
+  /* UART in mode Transmitter ------------------------------------------------*/
+  if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
+      && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
+          || ((cr3its & USART_CR3_TXFTIE) != 0U)))
+  {
+    if (huart->TxISR != NULL)
+    {
+      huart->TxISR(huart);
+    }
+    return;
+  }
+
+  /* UART in mode Transmitter (transmission end) -----------------------------*/
+  if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
+  {
+    UART_EndTransmit_IT(huart);
+    return;
+  }
+
+  /* UART TX Fifo Empty occurred ----------------------------------------------*/
+  if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))
+  {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Tx Fifo Empty Callback */
+    huart->TxFifoEmptyCallback(huart);
+#else
+    /* Call legacy weak Tx Fifo Empty Callback */
+    HAL_UARTEx_TxFifoEmptyCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+    return;
+  }
+
+  /* UART RX Fifo Full occurred ----------------------------------------------*/
+  if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))
+  {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Rx Fifo Full Callback */
+    huart->RxFifoFullCallback(huart);
+#else
+    /* Call legacy weak Rx Fifo Full Callback */
+    HAL_UARTEx_RxFifoFullCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+    return;
+  }
+}
+
+/**
+  * @brief Tx Transfer completed callback.
+  * @param huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_TxCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Tx Half Transfer completed callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_UART_TxHalfCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Rx Transfer completed callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_RxCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Rx Half Transfer completed callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_UART_RxHalfCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  UART error callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_ErrorCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  UART Abort Complete callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_AbortCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  UART Abort Complete callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  UART Abort Receive Complete callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
+  *  @brief   UART control functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the UART.
+     (+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver timeout value on the fly
+     (+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout feature
+     (+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout feature
+     (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
+     (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
+     (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
+     (+) UART_SetConfig() API configures the UART peripheral
+     (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features
+     (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization
+     (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter
+     (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver
+     (+) HAL_LIN_SendBreak() API transmits the break characters
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Update on the fly the receiver timeout value in RTOR register.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *                    the configuration information for the specified UART module.
+  * @param  TimeoutValue receiver timeout value in number of baud blocks. The timeout
+  *                     value must be less or equal to 0x0FFFFFFFF.
+  * @retval None
+  */
+void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue)
+{
+  if (!(IS_LPUART_INSTANCE(huart->Instance)))
+  {
+    assert_param(IS_UART_RECEIVER_TIMEOUT_VALUE(TimeoutValue));
+    MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue);
+  }
+}
+
+/**
+  * @brief  Enable the UART receiver timeout feature.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *                    the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart)
+{
+  if (!(IS_LPUART_INSTANCE(huart->Instance)))
+  {
+    if (huart->gState == HAL_UART_STATE_READY)
+    {
+      /* Process Locked */
+      __HAL_LOCK(huart);
+
+      huart->gState = HAL_UART_STATE_BUSY;
+
+      /* Set the USART RTOEN bit */
+      SET_BIT(huart->Instance->CR2, USART_CR2_RTOEN);
+
+      huart->gState = HAL_UART_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(huart);
+
+      return HAL_OK;
+    }
+    else
+    {
+      return HAL_BUSY;
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable the UART receiver timeout feature.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *                    the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart)
+{
+  if (!(IS_LPUART_INSTANCE(huart->Instance)))
+  {
+    if (huart->gState == HAL_UART_STATE_READY)
+    {
+      /* Process Locked */
+      __HAL_LOCK(huart);
+
+      huart->gState = HAL_UART_STATE_BUSY;
+
+      /* Clear the USART RTOEN bit */
+      CLEAR_BIT(huart->Instance->CR2, USART_CR2_RTOEN);
+
+      huart->gState = HAL_UART_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(huart);
+
+      return HAL_OK;
+    }
+    else
+    {
+      return HAL_BUSY;
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable UART in mute mode (does not mean UART enters mute mode;
+  *         to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
+  * @param  huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)
+{
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Enable USART mute mode by setting the MME bit in the CR1 register */
+  SET_BIT(huart->Instance->CR1, USART_CR1_MME);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  return (UART_CheckIdleState(huart));
+}
+
+/**
+  * @brief  Disable UART mute mode (does not mean the UART actually exits mute mode
+  *         as it may not have been in mute mode at this very moment).
+  * @param  huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)
+{
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Disable USART mute mode by clearing the MME bit in the CR1 register */
+  CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  return (UART_CheckIdleState(huart));
+}
+
+/**
+  * @brief Enter UART mute mode (means UART actually enters mute mode).
+  * @note  To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.
+  * @param huart UART handle.
+  * @retval None
+  */
+void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
+{
+  __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST);
+}
+
+/**
+  * @brief  Enable the UART transmitter and disable the UART receiver.
+  * @param  huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
+{
+  __HAL_LOCK(huart);
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Clear TE and RE bits */
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
+
+  /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
+  SET_BIT(huart->Instance->CR1, USART_CR1_TE);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the UART receiver and disable the UART transmitter.
+  * @param  huart UART handle.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
+{
+  __HAL_LOCK(huart);
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Clear TE and RE bits */
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
+
+  /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
+  SET_BIT(huart->Instance->CR1, USART_CR1_RE);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Transmit break characters.
+  * @param  huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
+{
+  /* Check the parameters */
+  assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
+
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Send break characters */
+  __HAL_UART_SEND_REQ(huart, UART_SENDBREAK_REQUEST);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions
+  *  @brief   UART Peripheral State functions
+  *
+@verbatim
+  ==============================================================================
+            ##### Peripheral State and Error functions #####
+  ==============================================================================
+    [..]
+    This subsection provides functions allowing to :
+      (+) Return the UART handle state.
+      (+) Return the UART handle error code
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Return the UART handle state.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART.
+  * @retval HAL state
+  */
+HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
+{
+  uint32_t temp1;
+  uint32_t temp2;
+  temp1 = huart->gState;
+  temp2 = huart->RxState;
+
+  return (HAL_UART_StateTypeDef)(temp1 | temp2);
+}
+
+/**
+  * @brief  Return the UART handle error code.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART.
+  * @retval UART Error Code
+  */
+uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
+{
+  return huart->ErrorCode;
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup UART_Private_Functions UART Private Functions
+  * @{
+  */
+
+/**
+  * @brief  Initialize the callbacks to their default values.
+  * @param  huart UART handle.
+  * @retval none
+  */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart)
+{
+  /* Init the UART Callback settings */
+  huart->TxHalfCpltCallback        = HAL_UART_TxHalfCpltCallback;        /* Legacy weak TxHalfCpltCallback        */
+  huart->TxCpltCallback            = HAL_UART_TxCpltCallback;            /* Legacy weak TxCpltCallback            */
+  huart->RxHalfCpltCallback        = HAL_UART_RxHalfCpltCallback;        /* Legacy weak RxHalfCpltCallback        */
+  huart->RxCpltCallback            = HAL_UART_RxCpltCallback;            /* Legacy weak RxCpltCallback            */
+  huart->ErrorCallback             = HAL_UART_ErrorCallback;             /* Legacy weak ErrorCallback             */
+  huart->AbortCpltCallback         = HAL_UART_AbortCpltCallback;         /* Legacy weak AbortCpltCallback         */
+  huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+  huart->AbortReceiveCpltCallback  = HAL_UART_AbortReceiveCpltCallback;  /* Legacy weak AbortReceiveCpltCallback  */
+  huart->WakeupCallback            = HAL_UARTEx_WakeupCallback;          /* Legacy weak WakeupCallback            */
+  huart->RxFifoFullCallback        = HAL_UARTEx_RxFifoFullCallback;      /* Legacy weak RxFifoFullCallback        */
+  huart->TxFifoEmptyCallback       = HAL_UARTEx_TxFifoEmptyCallback;     /* Legacy weak TxFifoEmptyCallback       */
+
+}
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+  * @brief Configure the UART peripheral.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
+{
+  uint32_t tmpreg;
+  uint16_t brrtemp;
+  UART_ClockSourceTypeDef clocksource;
+  uint32_t usartdiv                   = 0x00000000U;
+  HAL_StatusTypeDef ret               = HAL_OK;
+  uint32_t lpuart_ker_ck_pres         = 0x00000000U;
+  PLL2_ClocksTypeDef pll2_clocks;
+  PLL3_ClocksTypeDef pll3_clocks;
+  uint32_t pclk;
+
+  /* Check the parameters */
+  assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
+  assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
+  if (UART_INSTANCE_LOWPOWER(huart))
+  {
+    assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits));
+  }
+  else
+  {
+    assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
+    assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));
+  }
+
+  assert_param(IS_UART_PARITY(huart->Init.Parity));
+  assert_param(IS_UART_MODE(huart->Init.Mode));
+  assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
+  assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
+  assert_param(IS_UART_PRESCALER(huart->Init.ClockPrescaler));
+
+  /*-------------------------- USART CR1 Configuration -----------------------*/
+  /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure
+  *  the UART Word Length, Parity, Mode and oversampling:
+  *  set the M bits according to huart->Init.WordLength value
+  *  set PCE and PS bits according to huart->Init.Parity value
+  *  set TE and RE bits according to huart->Init.Mode value
+  *  set OVER8 bit according to huart->Init.OverSampling value */
+  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
+  tmpreg |= (uint32_t)huart->FifoMode;
+  MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+
+  /*-------------------------- USART CR2 Configuration -----------------------*/
+  /* Configure the UART Stop Bits: Set STOP[13:12] bits according
+  * to huart->Init.StopBits value */
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
+
+  /*-------------------------- USART CR3 Configuration -----------------------*/
+  /* Configure
+  * - UART HardWare Flow Control: set CTSE and RTSE bits according
+  *   to huart->Init.HwFlowCtl value
+  * - one-bit sampling method versus three samples' majority rule according
+  *   to huart->Init.OneBitSampling (not applicable to LPUART) */
+  tmpreg = (uint32_t)huart->Init.HwFlowCtl;
+
+  if (!(UART_INSTANCE_LOWPOWER(huart)))
+  {
+    tmpreg |= huart->Init.OneBitSampling;
+  }
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
+
+  /*-------------------------- USART PRESC Configuration -----------------------*/
+  /* Configure
+  * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
+  MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
+
+  /*-------------------------- USART BRR Configuration -----------------------*/
+  UART_GETCLOCKSOURCE(huart, clocksource);
+
+  /* Check LPUART instance */
+  if (UART_INSTANCE_LOWPOWER(huart))
+  {
+    /* Retrieve frequency clock */
+    switch (clocksource)
+    {
+      case UART_CLOCKSOURCE_D3PCLK1:
+        lpuart_ker_ck_pres = (HAL_RCCEx_GetD3PCLK1Freq() / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
+        break;
+      case UART_CLOCKSOURCE_PLL2:
+        HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+        lpuart_ker_ck_pres = (pll2_clocks.PLL2_Q_Frequency / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
+        break;
+      case UART_CLOCKSOURCE_PLL3:
+        HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+        lpuart_ker_ck_pres = (pll3_clocks.PLL3_Q_Frequency / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
+        break;
+      case UART_CLOCKSOURCE_HSI:
+        if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+        {
+          lpuart_ker_ck_pres = ((uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)) / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
+        }
+        else
+        {
+          lpuart_ker_ck_pres = ((uint32_t) HSI_VALUE / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
+        }
+        break;
+      case UART_CLOCKSOURCE_CSI:
+        lpuart_ker_ck_pres = ((uint32_t)CSI_VALUE / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
+        break;
+      case UART_CLOCKSOURCE_LSE:
+        lpuart_ker_ck_pres = ((uint32_t)LSE_VALUE / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
+        break;
+      default:
+        ret = HAL_ERROR;
+        break;
+    }
+
+    /* if proper clock source reported */
+    if (lpuart_ker_ck_pres != 0U)
+    {
+      /* ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
+      if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
+          (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate)))
+      {
+        ret = HAL_ERROR;
+      }
+      else
+      {
+        switch (clocksource)
+        {
+          case UART_CLOCKSOURCE_D3PCLK1:
+            pclk = HAL_RCCEx_GetD3PCLK1Freq();
+            usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+            break;
+          case UART_CLOCKSOURCE_PLL2:
+            HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+            usartdiv = (uint32_t)(UART_DIV_LPUART(pll2_clocks.PLL2_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+            break;
+          case UART_CLOCKSOURCE_PLL3:
+            HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+            usartdiv = (uint32_t)(UART_DIV_LPUART(pll3_clocks.PLL3_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+            break;
+          case UART_CLOCKSOURCE_HSI:
+            if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+            {
+              usartdiv = (uint32_t)(UART_DIV_LPUART((uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)), huart->Init.BaudRate, huart->Init.ClockPrescaler));
+            }
+            else
+            {
+              usartdiv = (uint32_t)(UART_DIV_LPUART(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+            }
+            break;
+          case UART_CLOCKSOURCE_CSI:
+            usartdiv = (uint32_t)(UART_DIV_LPUART(CSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+            break;
+          case UART_CLOCKSOURCE_LSE:
+            usartdiv = (uint32_t)(UART_DIV_LPUART(LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+            break;
+          default:
+            ret = HAL_ERROR;
+            break;
+        }
+
+        /* It is forbidden to write values lower than 0x300 in the LPUART_BRR register */
+        if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
+        {
+          huart->Instance->BRR = usartdiv;
+        }
+        else
+        {
+          ret = HAL_ERROR;
+        }
+      } /*   if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
+    } /* if (lpuart_ker_ck_pres != 0) */
+  }
+  /* Check UART Over Sampling to set Baud Rate Register */
+  else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
+  {
+    switch (clocksource)
+    {
+      case UART_CLOCKSOURCE_D2PCLK1:
+        pclk = HAL_RCC_GetPCLK1Freq();
+        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+        break;
+      case UART_CLOCKSOURCE_D2PCLK2:
+        pclk = HAL_RCC_GetPCLK2Freq();
+        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+        break;
+      case UART_CLOCKSOURCE_PLL2:
+        HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pll2_clocks.PLL2_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+        break;
+      case UART_CLOCKSOURCE_PLL3:
+        HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pll3_clocks.PLL3_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+        break;
+      case UART_CLOCKSOURCE_HSI:
+        if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+        {
+          usartdiv = (uint16_t)(UART_DIV_SAMPLING8((HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)), huart->Init.BaudRate, huart->Init.ClockPrescaler));
+        }
+        else
+        {
+          usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+        }
+        break;
+      case UART_CLOCKSOURCE_CSI:
+        usartdiv = (uint16_t)(UART_DIV_SAMPLING8(CSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+        break;
+      case UART_CLOCKSOURCE_LSE:
+        usartdiv = (uint16_t)(UART_DIV_SAMPLING8((uint32_t)LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+        break;
+      default:
+        ret = HAL_ERROR;
+        break;
+    }
+
+    /* USARTDIV must be greater than or equal to 0d16 */
+    if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+    {
+      brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
+      brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+      huart->Instance->BRR = brrtemp;
+    }
+    else
+    {
+      ret = HAL_ERROR;
+    }
+  }
+  else
+  {
+    switch (clocksource)
+    {
+      case UART_CLOCKSOURCE_D2PCLK1:
+        pclk = HAL_RCC_GetPCLK1Freq();
+        usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+        break;
+      case UART_CLOCKSOURCE_D2PCLK2:
+        pclk = HAL_RCC_GetPCLK2Freq();
+        usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+        break;
+      case UART_CLOCKSOURCE_PLL2:
+        HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+        usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pll2_clocks.PLL2_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+        break;
+      case UART_CLOCKSOURCE_PLL3:
+        HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+        usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pll3_clocks.PLL3_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+        break;
+      case UART_CLOCKSOURCE_HSI:
+        if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+        {
+          usartdiv = (uint16_t)(UART_DIV_SAMPLING16((HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)), huart->Init.BaudRate, huart->Init.ClockPrescaler));
+        }
+        else
+        {
+          usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+        }
+        break;
+      case UART_CLOCKSOURCE_CSI:
+        usartdiv = (uint16_t)(UART_DIV_SAMPLING16(CSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+        break;
+      case UART_CLOCKSOURCE_LSE:
+        usartdiv = (uint16_t)(UART_DIV_SAMPLING16((uint32_t)LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+        break;
+      default:
+        ret = HAL_ERROR;
+        break;
+    }
+
+    /* USARTDIV must be greater than or equal to 0d16 */
+    if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+    {
+      huart->Instance->BRR = usartdiv;
+    }
+    else
+    {
+      ret = HAL_ERROR;
+    }
+  }
+
+  /* Initialize the number of data to process during RX/TX ISR execution */
+  huart->NbTxDataToProcess = 1;
+  huart->NbRxDataToProcess = 1;
+
+  /* Clear ISR function pointers */
+  huart->RxISR = NULL;
+  huart->TxISR = NULL;
+
+  return ret;
+}
+
+/**
+  * @brief Configure the UART peripheral advanced features.
+  * @param huart UART handle.
+  * @retval None
+  */
+void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
+{
+  /* Check whether the set of advanced features to configure is properly set */
+  assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
+
+  /* if required, configure TX pin active level inversion */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
+  {
+    assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
+  }
+
+  /* if required, configure RX pin active level inversion */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
+  {
+    assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
+  }
+
+  /* if required, configure data inversion */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
+  {
+    assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
+  }
+
+  /* if required, configure RX/TX pins swap */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
+  {
+    assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
+  }
+
+  /* if required, configure RX overrun detection disabling */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
+  {
+    assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
+    MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
+  }
+
+  /* if required, configure DMA disabling on reception error */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
+  {
+    assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
+    MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
+  }
+
+  /* if required, configure auto Baud rate detection scheme */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
+  {
+    assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
+    assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
+    /* set auto Baudrate detection parameters if detection is enabled */
+    if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
+    {
+      assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
+      MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
+    }
+  }
+
+  /* if required, configure MSB first on communication line */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
+  {
+    assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
+  }
+}
+
+/**
+  * @brief Check the UART Idle State.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
+{
+  uint32_t tickstart;
+
+  /* Initialize the UART ErrorCode */
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+  /* Init tickstart for timeout managment*/
+  tickstart = HAL_GetTick();
+
+  /* Check if the Transmitter is enabled */
+  if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+  {
+    /* Wait until TEACK flag is set */
+    if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+    {
+      /* Timeout occurred */
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Check if the Receiver is enabled */
+  if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+  {
+    /* Wait until REACK flag is set */
+    if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+    {
+      /* Timeout occurred */
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Initialize the UART State */
+  huart->gState = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle UART Communication Timeout.
+  * @param huart     UART handle.
+  * @param Flag      Specifies the UART flag to check
+  * @param Status    Flag status (SET or RESET)
+  * @param Tickstart Tick start value
+  * @param Timeout   Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
+                                              uint32_t Tickstart, uint32_t Timeout)
+{
+  /* Wait until flag is set */
+  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
+  {
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+      {
+        /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+        CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
+        CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+        huart->gState = HAL_UART_STATE_READY;
+        huart->RxState = HAL_UART_STATE_READY;
+
+        __HAL_UNLOCK(huart);
+
+        return HAL_TIMEOUT;
+      }
+
+      if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
+      {
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
+        {
+          /* Clear Receiver Timeout flag*/
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
+          
+          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+          CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
+          CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+          huart->gState = HAL_UART_STATE_READY;
+          huart->RxState = HAL_UART_STATE_READY;
+          huart->ErrorCode = HAL_UART_ERROR_RTO;
+          
+          /* Process Unlocked */
+          __HAL_UNLOCK(huart);
+          
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
+  * @param  huart UART handle.
+  * @retval None
+  */
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
+{
+  /* Disable TXEIE, TCIE, TXFT interrupts */
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE));
+
+  /* At end of Tx process, restore huart->gState to Ready */
+  huart->gState = HAL_UART_STATE_READY;
+}
+
+
+/**
+  * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
+  * @param  huart UART handle.
+  * @retval None
+  */
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
+{
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+  /* At end of Rx process, restore huart->RxState to Ready */
+  huart->RxState = HAL_UART_STATE_READY;
+
+  /* Reset RxIsr function pointer */
+  huart->RxISR = NULL;
+}
+
+
+/**
+  * @brief DMA UART transmit process complete callback.
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+  /* DMA Normal mode */
+  if (hdma->Init.Mode != DMA_CIRCULAR)
+  {
+    huart->TxXferCount = 0U;
+
+    /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+       in the UART CR3 register */
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Enable the UART Transmit Complete Interrupt */
+    SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+  }
+  /* DMA Circular mode */
+  else
+  {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /*Call registered Tx complete callback*/
+    huart->TxCpltCallback(huart);
+#else
+    /*Call legacy weak Tx complete callback*/
+    HAL_UART_TxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief DMA UART transmit process half complete callback.
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered Tx Half complete callback*/
+  huart->TxHalfCpltCallback(huart);
+#else
+  /*Call legacy weak Tx Half complete callback*/
+  HAL_UART_TxHalfCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief DMA UART receive process complete callback.
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+  /* DMA Normal mode */
+  if (hdma->Init.Mode != DMA_CIRCULAR)
+  {
+    huart->RxXferCount = 0U;
+
+    /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+    CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+    /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+       in the UART CR3 register */
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* At end of Rx process, restore huart->RxState to Ready */
+    huart->RxState = HAL_UART_STATE_READY;
+  }
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered Rx complete callback*/
+  huart->RxCpltCallback(huart);
+#else
+  /*Call legacy weak Rx complete callback*/
+  HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief DMA UART receive process half complete callback.
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered Rx Half complete callback*/
+  huart->RxHalfCpltCallback(huart);
+#else
+  /*Call legacy weak Rx Half complete callback*/
+  HAL_UART_RxHalfCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief DMA UART communication error callback.
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMAError(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+  const HAL_UART_StateTypeDef gstate = huart->gState;
+  const HAL_UART_StateTypeDef rxstate = huart->RxState;
+
+  /* Stop UART DMA Tx request if ongoing */
+  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
+      (gstate == HAL_UART_STATE_BUSY_TX))
+  {
+    huart->TxXferCount = 0U;
+    UART_EndTxTransfer(huart);
+  }
+
+  /* Stop UART DMA Rx request if ongoing */
+  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
+      (rxstate == HAL_UART_STATE_BUSY_RX))
+  {
+    huart->RxXferCount = 0U;
+    UART_EndRxTransfer(huart);
+  }
+
+  huart->ErrorCode |= HAL_UART_ERROR_DMA;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered error callback*/
+  huart->ErrorCallback(huart);
+#else
+  /*Call legacy weak error callback*/
+  HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA UART communication abort callback, when initiated by HAL services on Error
+  *         (To be called at end of DMA Abort procedure following error occurrence).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+  huart->RxXferCount = 0U;
+  huart->TxXferCount = 0U;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered error callback*/
+  huart->ErrorCallback(huart);
+#else
+  /*Call legacy weak error callback*/
+  HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA UART Tx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Tx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Rx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+  huart->hdmatx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if (huart->hdmarx != NULL)
+  {
+    if (huart->hdmarx->XferAbortCallback != NULL)
+    {
+      return;
+    }
+  }
+
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  huart->TxXferCount = 0U;
+  huart->RxXferCount = 0U;
+
+  /* Reset errorCode */
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+  /* Flush the whole TX FIFO (if needed) */
+  if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+  {
+    __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+  }
+
+  /* Restore huart->gState and huart->RxState to Ready */
+  huart->gState  = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort complete callback */
+  huart->AbortCpltCallback(huart);
+#else
+  /* Call legacy weak Abort complete callback */
+  HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+
+/**
+  * @brief  DMA UART Rx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Rx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Tx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+  huart->hdmarx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if (huart->hdmatx != NULL)
+  {
+    if (huart->hdmatx->XferAbortCallback != NULL)
+    {
+      return;
+    }
+  }
+
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  huart->TxXferCount = 0U;
+  huart->RxXferCount = 0U;
+
+  /* Reset errorCode */
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+  /* Discard the received data */
+  __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+  /* Restore huart->gState and huart->RxState to Ready */
+  huart->gState  = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort complete callback */
+  huart->AbortCpltCallback(huart);
+#else
+  /* Call legacy weak Abort complete callback */
+  HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+
+/**
+  * @brief  DMA UART Tx communication abort callback, when initiated by user by a call to
+  *         HAL_UART_AbortTransmit_IT API (Abort only Tx transfer)
+  *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
+  *         and leads to user Tx Abort Complete callback execution).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+  huart->TxXferCount = 0U;
+
+  /* Flush the whole TX FIFO (if needed) */
+  if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+  {
+    __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+  }
+
+  /* Restore huart->gState to Ready */
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort Transmit Complete Callback */
+  huart->AbortTransmitCpltCallback(huart);
+#else
+  /* Call legacy weak Abort Transmit Complete Callback */
+  HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA UART Rx communication abort callback, when initiated by user by a call to
+  *         HAL_UART_AbortReceive_IT API (Abort only Rx transfer)
+  *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
+  *         and leads to user Rx Abort Complete callback execution).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  huart->RxXferCount = 0U;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+  /* Discard the received data */
+  __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+  /* Restore huart->RxState to Ready */
+  huart->RxState = HAL_UART_STATE_READY;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort Receive Complete Callback */
+  huart->AbortReceiveCpltCallback(huart);
+#else
+  /* Call legacy weak Abort Receive Complete Callback */
+  HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief TX interrrupt handler for 7 or 8 bits data word length .
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_UART_Transmit_IT().
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_TxISR_8BIT(UART_HandleTypeDef *huart)
+{
+  /* Check that a Tx process is ongoing */
+  if (huart->gState == HAL_UART_STATE_BUSY_TX)
+  {
+    if (huart->TxXferCount == 0U)
+    {
+      /* Disable the UART Transmit Data Register Empty Interrupt */
+      CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+
+      /* Enable the UART Transmit Complete Interrupt */
+      SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+    }
+    else
+    {
+      huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
+      huart->pTxBuffPtr++;
+      huart->TxXferCount--;
+    }
+  }
+}
+
+/**
+  * @brief TX interrrupt handler for 9 bits data word length.
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_UART_Transmit_IT().
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_TxISR_16BIT(UART_HandleTypeDef *huart)
+{
+  uint16_t *tmp;
+
+  /* Check that a Tx process is ongoing */
+  if (huart->gState == HAL_UART_STATE_BUSY_TX)
+  {
+    if (huart->TxXferCount == 0U)
+    {
+      /* Disable the UART Transmit Data Register Empty Interrupt */
+      CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+
+      /* Enable the UART Transmit Complete Interrupt */
+      SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+    }
+    else
+    {
+      tmp = (uint16_t *) huart->pTxBuffPtr;
+      huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
+      huart->pTxBuffPtr += 2U;
+      huart->TxXferCount--;
+    }
+  }
+}
+
+/**
+  * @brief TX interrrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_UART_Transmit_IT().
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
+{
+  uint16_t  nb_tx_data;
+
+  /* Check that a Tx process is ongoing */
+  if (huart->gState == HAL_UART_STATE_BUSY_TX)
+  {
+    for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
+    {
+      if (huart->TxXferCount == 0U)
+      {
+        /* Disable the TX FIFO threshold interrupt */
+        CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+
+        /* Enable the UART Transmit Complete Interrupt */
+        SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+
+        break; /* force exit loop */
+      }
+      else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
+      {
+        huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
+        huart->pTxBuffPtr++;
+        huart->TxXferCount--;
+      }
+      else
+      {
+        /* Nothing to do */
+      }
+    }
+  }
+}
+
+/**
+  * @brief TX interrrupt handler for 9 bits data word length and FIFO mode is enabled.
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_UART_Transmit_IT().
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
+{
+  uint16_t *tmp;
+  uint16_t  nb_tx_data;
+
+  /* Check that a Tx process is ongoing */
+  if (huart->gState == HAL_UART_STATE_BUSY_TX)
+  {
+    for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
+    {
+      if (huart->TxXferCount == 0U)
+      {
+        /* Disable the TX FIFO threshold interrupt */
+        CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+
+        /* Enable the UART Transmit Complete Interrupt */
+        SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+
+        break; /* force exit loop */
+      }
+      else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
+      {
+        tmp = (uint16_t *) huart->pTxBuffPtr;
+        huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
+        huart->pTxBuffPtr += 2U;
+        huart->TxXferCount--;
+      }
+      else
+      {
+        /* Nothing to do */
+      }
+    }
+  }
+}
+
+/**
+  * @brief  Wrap up transmission in non-blocking mode.
+  * @param  huart pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval None
+  */
+static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
+{
+  /* Disable the UART Transmit Complete Interrupt */
+  CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+
+  /* Tx process is ended, restore huart->gState to Ready */
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Cleat TxISR function pointer */
+  huart->TxISR = NULL;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered Tx complete callback*/
+  huart->TxCpltCallback(huart);
+#else
+  /*Call legacy weak Tx complete callback*/
+  HAL_UART_TxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief RX interrrupt handler for 7 or 8 bits data word length .
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
+{
+  uint16_t uhMask = huart->Mask;
+  uint16_t  uhdata;
+
+  /* Check that a Rx process is ongoing */
+  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+  {
+    uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+    *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
+    huart->pRxBuffPtr++;
+    huart->RxXferCount--;
+
+    if (huart->RxXferCount == 0U)
+    {
+      /* Disable the UART Parity Error Interrupt and RXNE interrupts */
+      CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+
+      /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+      CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+      /* Rx process is completed, restore huart->RxState to Ready */
+      huart->RxState = HAL_UART_STATE_READY;
+
+      /* Clear RxISR function pointer */
+      huart->RxISR = NULL;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+      /*Call registered Rx complete callback*/
+      huart->RxCpltCallback(huart);
+#else
+      /*Call legacy weak Rx complete callback*/
+      HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+    }
+  }
+  else
+  {
+    /* Clear RXNE interrupt flag */
+    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+  }
+}
+
+/**
+  * @brief RX interrrupt handler for 9 bits data word length .
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_UART_Receive_IT()
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
+{
+  uint16_t *tmp;
+  uint16_t uhMask = huart->Mask;
+  uint16_t  uhdata;
+
+  /* Check that a Rx process is ongoing */
+  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+  {
+    uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+    tmp = (uint16_t *) huart->pRxBuffPtr ;
+    *tmp = (uint16_t)(uhdata & uhMask);
+    huart->pRxBuffPtr += 2U;
+    huart->RxXferCount--;
+
+    if (huart->RxXferCount == 0U)
+    {
+      /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
+      CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+
+      /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+      CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+      /* Rx process is completed, restore huart->RxState to Ready */
+      huart->RxState = HAL_UART_STATE_READY;
+
+      /* Clear RxISR function pointer */
+      huart->RxISR = NULL;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+      /*Call registered Rx complete callback*/
+      huart->RxCpltCallback(huart);
+#else
+      /*Call legacy weak Rx complete callback*/
+      HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+    }
+  }
+  else
+  {
+    /* Clear RXNE interrupt flag */
+    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+  }
+}
+
+/**
+  * @brief RX interrrupt handler for 7 or 8  bits data word length and FIFO mode is enabled.
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_UART_Receive_IT()
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
+{
+  uint16_t  uhMask = huart->Mask;
+  uint16_t  uhdata;
+  uint16_t   nb_rx_data;
+  uint16_t  rxdatacount;
+
+  /* Check that a Rx process is ongoing */
+  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+  {
+    for (nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)
+    {
+      uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+      *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
+      huart->pRxBuffPtr++;
+      huart->RxXferCount--;
+
+      if (huart->RxXferCount == 0U)
+      {
+        /* Disable the UART Parity Error Interrupt and RXFT interrupt*/
+        CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+
+        /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
+        CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+        /* Rx process is completed, restore huart->RxState to Ready */
+        huart->RxState = HAL_UART_STATE_READY;
+
+        /* Clear RxISR function pointer */
+        huart->RxISR = NULL;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered Rx complete callback*/
+        huart->RxCpltCallback(huart);
+#else
+        /*Call legacy weak Rx complete callback*/
+        HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+      }
+    }
+
+    /* When remaining number of bytes to receive is less than the RX FIFO
+    threshold, next incoming frames are processed as if FIFO mode was
+    disabled (i.e. one interrupt per received frame).
+    */
+    rxdatacount = huart->RxXferCount;
+    if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
+    {
+      /* Disable the UART RXFT interrupt*/
+      CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+
+      /* Update the RxISR function pointer */
+      huart->RxISR = UART_RxISR_8BIT;
+
+      /* Enable the UART Data Register Not Empty interrupt */
+      SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+    }
+  }
+  else
+  {
+    /* Clear RXNE interrupt flag */
+    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+  }
+}
+
+/**
+  * @brief RX interrrupt handler for 9 bits data word length and FIFO mode is enabled.
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_UART_Receive_IT()
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
+{
+  uint16_t *tmp;
+  uint16_t  uhMask = huart->Mask;
+  uint16_t  uhdata;
+  uint16_t   nb_rx_data;
+  uint16_t  rxdatacount;
+
+  /* Check that a Rx process is ongoing */
+  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+  {
+    for (nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)
+    {
+      uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+      tmp = (uint16_t *) huart->pRxBuffPtr ;
+      *tmp = (uint16_t)(uhdata & uhMask);
+      huart->pRxBuffPtr += 2U;
+      huart->RxXferCount--;
+
+      if (huart->RxXferCount == 0U)
+      {
+        /* Disable the UART Parity Error Interrupt and RXFT interrupt*/
+        CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+
+        /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
+        CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+        /* Rx process is completed, restore huart->RxState to Ready */
+        huart->RxState = HAL_UART_STATE_READY;
+
+        /* Clear RxISR function pointer */
+        huart->RxISR = NULL;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered Rx complete callback*/
+        huart->RxCpltCallback(huart);
+#else
+        /*Call legacy weak Rx complete callback*/
+        HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+      }
+    }
+
+    /* When remaining number of bytes to receive is less than the RX FIFO
+    threshold, next incoming frames are processed as if FIFO mode was
+    disabled (i.e. one interrupt per received frame).
+    */
+    rxdatacount = huart->RxXferCount;
+    if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
+    {
+      /* Disable the UART RXFT interrupt*/
+      CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+
+      /* Update the RxISR function pointer */
+      huart->RxISR = UART_RxISR_16BIT;
+
+      /* Enable the UART Data Register Not Empty interrupt */
+      SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+    }
+  }
+  else
+  {
+    /* Clear RXNE interrupt flag */
+    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_UART_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c
new file mode 100644
index 00000000..94920852
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c
@@ -0,0 +1,729 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_uart_ex.c
+  * @author  MCD Application Team
+  * @brief   Extended UART HAL module driver.
+  *          This file provides firmware functions to manage the following extended
+  *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions
+  *
+  *
+  @verbatim
+  ==============================================================================
+               ##### UART peripheral extended features  #####
+  ==============================================================================
+
+    (#) Declare a UART_HandleTypeDef handle structure.
+
+    (#) For the UART RS485 Driver Enable mode, initialize the UART registers
+        by calling the HAL_RS485Ex_Init() API.
+
+    (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.
+
+        -@- When UART operates in FIFO mode, FIFO mode must be enabled prior
+            starting RX/TX transfers. Also RX/TX FIFO thresholds must be
+            configured prior starting RX/TX transfers.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup UARTEx UARTEx
+  * @brief UART Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_UART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup UARTEX_Private_Constants UARTEx Private Constants
+  * @{
+  */
+/* UART RX FIFO depth */
+#define RX_FIFO_DEPTH 8U
+
+/* UART TX FIFO depth */
+#define TX_FIFO_DEPTH 8U
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup UARTEx_Private_Functions UARTEx Private Functions
+  * @{
+  */
+static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
+static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup UARTEx_Exported_Functions  UARTEx Exported Functions
+  * @{
+  */
+
+/** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief    Extended Initialization and Configuration Functions
+  *
+@verbatim
+===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
+    in asynchronous mode.
+      (+) For the asynchronous mode the parameters below can be configured:
+        (++) Baud Rate
+        (++) Word Length
+        (++) Stop Bit
+        (++) Parity: If the parity is enabled, then the MSB bit of the data written
+             in the data register is transmitted but is changed by the parity bit.
+        (++) Hardware flow control
+        (++) Receiver/transmitter modes
+        (++) Over Sampling Method
+        (++) One-Bit Sampling Method
+      (+) For the asynchronous mode, the following advanced features can be configured as well:
+        (++) TX and/or RX pin level inversion
+        (++) data logical level inversion
+        (++) RX and TX pins swap
+        (++) RX overrun detection disabling
+        (++) DMA disabling on RX error
+        (++) MSB first on communication line
+        (++) auto Baud rate detection
+    [..]
+    The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration
+     procedures (details for the procedures are available in reference manual).
+
+@endverbatim
+
+  Depending on the frame length defined by the M1 and M0 bits (7-bit,
+  8-bit or 9-bit), the possible UART formats are listed in the
+  following table.
+
+    Table 1. UART frame format.
+    +-----------------------------------------------------------------------+
+    |  M1 bit |  M0 bit |  PCE bit  |             UART frame                |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
+    +-----------------------------------------------------------------------+
+
+  * @{
+  */
+
+/**
+  * @brief Initialize the RS485 Driver enable feature according to the specified
+  *         parameters in the UART_InitTypeDef and creates the associated handle.
+  * @param huart            UART handle.
+  * @param Polarity         Select the driver enable polarity.
+  *          This parameter can be one of the following values:
+  *          @arg @ref UART_DE_POLARITY_HIGH DE signal is active high
+  *          @arg @ref UART_DE_POLARITY_LOW  DE signal is active low
+  * @param AssertionTime    Driver Enable assertion time:
+  *       5-bit value defining the time between the activation of the DE (Driver Enable)
+  *       signal and the beginning of the start bit. It is expressed in sample time
+  *       units (1/8 or 1/16 bit time, depending on the oversampling rate)
+  * @param DeassertionTime  Driver Enable deassertion time:
+  *       5-bit value defining the time between the end of the last stop bit, in a
+  *       transmitted message, and the de-activation of the DE (Driver Enable) signal.
+  *       It is expressed in sample time units (1/8 or 1/16 bit time, depending on the
+  *       oversampling rate).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
+                                   uint32_t DeassertionTime)
+{
+  uint32_t temp;
+
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+  /* Check the Driver Enable UART instance */
+  assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));
+
+  /* Check the Driver Enable polarity */
+  assert_param(IS_UART_DE_POLARITY(Polarity));
+
+  /* Check the Driver Enable assertion time */
+  assert_param(IS_UART_ASSERTIONTIME(AssertionTime));
+
+  /* Check the Driver Enable deassertion time */
+  assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));
+
+  if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    UART_InitCallbacksToDefault(huart);
+
+    if (huart->MspInitCallback == NULL)
+    {
+      huart->MspInitCallback = HAL_UART_MspInit;
+    }
+
+    /* Init the low level hardware */
+    huart->MspInitCallback(huart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX */
+    HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the UART Communication parameters */
+  if (UART_SetConfig(huart) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+  {
+    UART_AdvFeatureConfig(huart);
+  }
+
+  /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
+  SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
+
+  /* Set the Driver Enable polarity */
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
+
+  /* Set the Driver Enable assertion and deassertion times */
+  temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
+  temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
+  MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp);
+
+  /* Enable the Peripheral */
+  __HAL_UART_ENABLE(huart);
+
+  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+  return (UART_CheckIdleState(huart));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions
+  *  @brief Extended functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    This subsection provides a set of Wakeup and FIFO mode related callback functions.
+
+    (#) Wakeup from Stop mode Callback:
+        (+) HAL_UARTEx_WakeupCallback()
+
+    (#) TX/RX Fifos Callbacks:
+        (+) HAL_UARTEx_RxFifoFullCallback()
+        (+) HAL_UARTEx_TxFifoEmptyCallback()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief UART wakeup from Stop mode callback.
+  * @param huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UARTEx_WakeupCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  UART RX Fifo full callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  UART TX Fifo empty callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions
+  * @brief    Extended Peripheral Control functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..] This section provides the following functions:
+     (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
+         detection length to more than 4 bits for multiprocessor address mark wake up.
+     (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode
+         trigger: address match, Start Bit detection or RXNE bit status.
+     (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode
+     (+) HAL_UARTEx_DisableStopMode() API disables the above functionality
+     (+) HAL_UARTEx_EnableFifoMode() API enables the FIFO mode
+     (+) HAL_UARTEx_DisableFifoMode() API disables the FIFO mode
+     (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold
+     (+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief By default in multiprocessor mode, when the wake up method is set
+  *        to address mark, the UART handles only 4-bit long addresses detection;
+  *        this API allows to enable longer addresses detection (6-, 7- or 8-bit
+  *        long).
+  * @note  Addresses detection lengths are: 6-bit address detection in 7-bit data mode,
+  *        7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
+  * @param huart         UART handle.
+  * @param AddressLength This parameter can be one of the following values:
+  *          @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address
+  *          @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the address length parameter */
+  assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the address length */
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);
+
+  /* Enable the Peripheral */
+  __HAL_UART_ENABLE(huart);
+
+  /* TEACK and/or REACK to check before moving huart->gState to Ready */
+  return (UART_CheckIdleState(huart));
+}
+
+/**
+  * @brief Set Wakeup from Stop mode interrupt flag selection.
+  * @note It is the application responsibility to enable the interrupt used as
+  *       usart_wkup interrupt source before entering low-power mode.
+  * @param huart           UART handle.
+  * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status.
+  *          This parameter can be one of the following values:
+  *          @arg @ref UART_WAKEUP_ON_ADDRESS
+  *          @arg @ref UART_WAKEUP_ON_STARTBIT
+  *          @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tickstart;
+
+  /* check the wake-up from stop mode UART instance */
+  assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
+  /* check the wake-up selection parameter */
+  assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the wake-up selection scheme */
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent);
+
+  if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS)
+  {
+    UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection);
+  }
+
+  /* Enable the Peripheral */
+  __HAL_UART_ENABLE(huart);
+
+  /* Init tickstart for timeout managment*/
+  tickstart = HAL_GetTick();
+
+  /* Wait until REACK flag is set */
+  if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+  {
+    status = HAL_TIMEOUT;
+  }
+  else
+  {
+    /* Initialize the UART State */
+    huart->gState = HAL_UART_STATE_READY;
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return status;
+}
+
+/**
+  * @brief Enable UART Stop Mode.
+  * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)
+{
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  /* Set UESM bit */
+  SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Disable UART Stop Mode.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
+{
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  /* Clear UESM bit */
+  CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the FIFO mode.
+  * @param huart      UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart)
+{
+  uint32_t tmpcr1;
+
+  /* Check parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Save actual UART configuration */
+  tmpcr1 = READ_REG(huart->Instance->CR1);
+
+  /* Disable UART */
+  __HAL_UART_DISABLE(huart);
+
+  /* Enable FIFO mode */
+  SET_BIT(tmpcr1, USART_CR1_FIFOEN);
+  huart->FifoMode = UART_FIFOMODE_ENABLE;
+
+  /* Restore UART configuration */
+  WRITE_REG(huart->Instance->CR1, tmpcr1);
+
+  /* Determine the number of data to process during RX/TX ISR execution */
+  UARTEx_SetNbDataToProcess(huart);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the FIFO mode.
+  * @param huart      UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart)
+{
+  uint32_t tmpcr1;
+
+  /* Check parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Save actual UART configuration */
+  tmpcr1 = READ_REG(huart->Instance->CR1);
+
+  /* Disable UART */
+  __HAL_UART_DISABLE(huart);
+
+  /* Enable FIFO mode */
+  CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
+  huart->FifoMode = UART_FIFOMODE_DISABLE;
+
+  /* Restore UART configuration */
+  WRITE_REG(huart->Instance->CR1, tmpcr1);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the TXFIFO threshold.
+  * @param huart      UART handle.
+  * @param Threshold  TX FIFO threshold value
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_TXFIFO_THRESHOLD_1_8
+  *            @arg @ref UART_TXFIFO_THRESHOLD_1_4
+  *            @arg @ref UART_TXFIFO_THRESHOLD_1_2
+  *            @arg @ref UART_TXFIFO_THRESHOLD_3_4
+  *            @arg @ref UART_TXFIFO_THRESHOLD_7_8
+  *            @arg @ref UART_TXFIFO_THRESHOLD_8_8
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
+{
+  uint32_t tmpcr1;
+
+  /* Check parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+  assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Save actual UART configuration */
+  tmpcr1 = READ_REG(huart->Instance->CR1);
+
+  /* Disable UART */
+  __HAL_UART_DISABLE(huart);
+
+  /* Update TX threshold configuration */
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
+
+  /* Determine the number of data to process during RX/TX ISR execution */
+  UARTEx_SetNbDataToProcess(huart);
+
+  /* Restore UART configuration */
+  WRITE_REG(huart->Instance->CR1, tmpcr1);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the RXFIFO threshold.
+  * @param huart      UART handle.
+  * @param Threshold  RX FIFO threshold value
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_RXFIFO_THRESHOLD_1_8
+  *            @arg @ref UART_RXFIFO_THRESHOLD_1_4
+  *            @arg @ref UART_RXFIFO_THRESHOLD_1_2
+  *            @arg @ref UART_RXFIFO_THRESHOLD_3_4
+  *            @arg @ref UART_RXFIFO_THRESHOLD_7_8
+  *            @arg @ref UART_RXFIFO_THRESHOLD_8_8
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
+{
+  uint32_t tmpcr1;
+
+  /* Check the parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+  assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Save actual UART configuration */
+  tmpcr1 = READ_REG(huart->Instance->CR1);
+
+  /* Disable UART */
+  __HAL_UART_DISABLE(huart);
+
+  /* Update RX threshold configuration */
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
+
+  /* Determine the number of data to process during RX/TX ISR execution */
+  UARTEx_SetNbDataToProcess(huart);
+
+  /* Restore UART configuration */
+  WRITE_REG(huart->Instance->CR1, tmpcr1);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup UARTEx_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection.
+  * @param huart           UART handle.
+  * @param WakeUpSelection UART wake up from stop mode parameters.
+  * @retval None
+  */
+static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
+{
+  assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength));
+
+  /* Set the USART address length */
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength);
+
+  /* Set the USART address node */
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS));
+}
+
+/**
+  * @brief Calculate the number of data to process in RX/TX ISR.
+  * @note The RX FIFO depth and the TX FIFO depth is extracted from
+  *       the UART configuration registers.
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart)
+{
+  uint8_t rx_fifo_depth;
+  uint8_t tx_fifo_depth;
+  uint8_t rx_fifo_threshold;
+  uint8_t tx_fifo_threshold;
+  uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
+  uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
+
+  if (huart->FifoMode == UART_FIFOMODE_DISABLE)
+  {
+    huart->NbTxDataToProcess = 1U;
+    huart->NbRxDataToProcess = 1U;
+  }
+  else
+  {
+    rx_fifo_depth = RX_FIFO_DEPTH;
+    tx_fifo_depth = TX_FIFO_DEPTH;
+    rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
+    tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
+    huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold];
+    huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold];
+  }
+}
+/**
+  * @}
+  */
+
+#endif /* HAL_UART_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/stm32h7xx_hal_conf.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/stm32h7xx_hal_conf.h
new file mode 100644
index 00000000..ed47e1b5
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/stm32h7xx_hal_conf.h
@@ -0,0 +1,493 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32H7xx_HAL_CONF_H
+#define __STM32H7xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver 
+  */
+#define HAL_MODULE_ENABLED  
+
+  /* #define HAL_ADC_MODULE_ENABLED   */
+#define HAL_FDCAN_MODULE_ENABLED
+/* #define HAL_CEC_MODULE_ENABLED   */
+/* #define HAL_COMP_MODULE_ENABLED   */
+/* #define HAL_CRC_MODULE_ENABLED   */
+/* #define HAL_CRYP_MODULE_ENABLED   */
+/* #define HAL_DAC_MODULE_ENABLED   */
+/* #define HAL_DCMI_MODULE_ENABLED   */
+/* #define HAL_DMA2D_MODULE_ENABLED   */
+/* #define HAL_ETH_MODULE_ENABLED   */
+/* #define HAL_NAND_MODULE_ENABLED   */
+/* #define HAL_NOR_MODULE_ENABLED   */
+/* #define HAL_OTFDEC_MODULE_ENABLED   */
+/* #define HAL_SRAM_MODULE_ENABLED   */
+/* #define HAL_SDRAM_MODULE_ENABLED   */
+/* #define HAL_HASH_MODULE_ENABLED   */
+/* #define HAL_HRTIM_MODULE_ENABLED   */
+/* #define HAL_HSEM_MODULE_ENABLED   */
+/* #define HAL_GFXMMU_MODULE_ENABLED   */
+/* #define HAL_JPEG_MODULE_ENABLED   */
+/* #define HAL_OPAMP_MODULE_ENABLED   */
+/* #define HAL_OSPI_MODULE_ENABLED   */
+/* #define HAL_OSPI_MODULE_ENABLED   */
+/* #define HAL_I2S_MODULE_ENABLED   */
+/* #define HAL_SMBUS_MODULE_ENABLED   */
+/* #define HAL_IWDG_MODULE_ENABLED   */
+/* #define HAL_LPTIM_MODULE_ENABLED   */
+/* #define HAL_LTDC_MODULE_ENABLED   */
+/* #define HAL_QSPI_MODULE_ENABLED   */
+/* #define HAL_RNG_MODULE_ENABLED   */
+/* #define HAL_RTC_MODULE_ENABLED   */
+/* #define HAL_SAI_MODULE_ENABLED   */
+/* #define HAL_SD_MODULE_ENABLED   */
+/* #define HAL_MMC_MODULE_ENABLED   */
+/* #define HAL_SPDIFRX_MODULE_ENABLED   */
+/* #define HAL_SPI_MODULE_ENABLED   */
+/* #define HAL_SWPMI_MODULE_ENABLED   */
+/* #define HAL_TIM_MODULE_ENABLED   */
+#define HAL_UART_MODULE_ENABLED
+/* #define HAL_USART_MODULE_ENABLED   */
+/* #define HAL_IRDA_MODULE_ENABLED   */
+/* #define HAL_SMARTCARD_MODULE_ENABLED   */
+/* #define HAL_WWDG_MODULE_ENABLED   */
+/* #define HAL_PCD_MODULE_ENABLED   */
+/* #define HAL_HCD_MODULE_ENABLED   */
+/* #define HAL_DFSDM_MODULE_ENABLED   */
+/* #define HAL_DSI_MODULE_ENABLED   */
+/* #define HAL_JPEG_MODULE_ENABLED   */
+/* #define HAL_MDIOS_MODULE_ENABLED   */
+/* #define HAL_PSSI_MODULE_ENABLED   */
+/* #define HAL_DTS_MODULE_ENABLED   */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_MDMA_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_HSEM_MODULE_ENABLED
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).  
+  */
+#if !defined  (HSE_VALUE) 
+#define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal  oscillator (CSI) default value.
+  *        This value is the default CSI value after Reset.
+  */
+#if !defined  (CSI_VALUE)
+  #define CSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* CSI_VALUE */
+   
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL). 
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for I2S peripheral
+  *        This value is used by the I2S HAL module to compute the I2S clock source 
+  *        frequency, this source is inserted directly through I2S_CKIN pad. 
+  */
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+  #define EXTERNAL_CLOCK_VALUE    12288000U /*!< Value of the External clock in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+#define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            ((uint32_t)0U) /*!< tick interrupt priority */
+#define  USE_RTOS                     0U
+#define  USE_SD_TRANSCEIVER           0U               /*!< use uSD Transceiver */
+
+#define  USE_HAL_ADC_REGISTER_CALLBACKS     0U /* ADC register callback disabled     */
+#define  USE_HAL_CEC_REGISTER_CALLBACKS     0U /* CEC register callback disabled     */
+#define  USE_HAL_COMP_REGISTER_CALLBACKS    0U /* COMP register callback disabled    */
+#define  USE_HAL_CRYP_REGISTER_CALLBACKS    0U /* CRYP register callback disabled    */
+#define  USE_HAL_DAC_REGISTER_CALLBACKS     0U /* DAC register callback disabled     */
+#define  USE_HAL_DCMI_REGISTER_CALLBACKS    0U /* DCMI register callback disabled    */
+#define  USE_HAL_DFSDM_REGISTER_CALLBACKS   0U /* DFSDM register callback disabled   */
+#define  USE_HAL_DMA2D_REGISTER_CALLBACKS   0U /* DMA2D register callback disabled   */
+#define  USE_HAL_DSI_REGISTER_CALLBACKS     0U /* DSI register callback disabled     */
+#define  USE_HAL_DTS_REGISTER_CALLBACKS     0U /* DTS register callback disabled     */
+#define  USE_HAL_ETH_REGISTER_CALLBACKS     0U /* ETH register callback disabled     */
+#define  USE_HAL_FDCAN_REGISTER_CALLBACKS   0U /* FDCAN register callback disabled   */
+#define  USE_HAL_NAND_REGISTER_CALLBACKS    0U /* NAND register callback disabled    */
+#define  USE_HAL_NOR_REGISTER_CALLBACKS     0U /* NOR register callback disabled     */
+#define  USE_HAL_SDRAM_REGISTER_CALLBACKS   0U /* SDRAM register callback disabled   */
+#define  USE_HAL_SRAM_REGISTER_CALLBACKS    0U /* SRAM register callback disabled    */
+#define  USE_HAL_HASH_REGISTER_CALLBACKS    0U /* HASH register callback disabled    */
+#define  USE_HAL_HCD_REGISTER_CALLBACKS     0U /* HCD register callback disabled     */
+#define  USE_HAL_GFXMMU_REGISTER_CALLBACKS  0U /* GFXMMU register callback disabled  */
+#define  USE_HAL_HRTIM_REGISTER_CALLBACKS   0U /* HRTIM register callback disabled   */
+#define  USE_HAL_I2C_REGISTER_CALLBACKS     0U /* I2C register callback disabled     */
+#define  USE_HAL_I2S_REGISTER_CALLBACKS     0U /* I2S register callback disabled     */
+#define  USE_HAL_IRDA_REGISTER_CALLBACKS    0U /* IRDA register callback disabled    */
+#define  USE_HAL_JPEG_REGISTER_CALLBACKS    0U /* JPEG register callback disabled    */
+#define  USE_HAL_LPTIM_REGISTER_CALLBACKS   0U /* LPTIM register callback disabled   */
+#define  USE_HAL_LTDC_REGISTER_CALLBACKS    0U /* LTDC register callback disabled    */
+#define  USE_HAL_MDIOS_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */
+#define  USE_HAL_MMC_REGISTER_CALLBACKS     0U /* MMC register callback disabled     */
+#define  USE_HAL_OPAMP_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */
+#define  USE_HAL_OSPI_REGISTER_CALLBACKS    0U /* OSPI register callback disabled    */
+#define  USE_HAL_OTFDEC_REGISTER_CALLBACKS  0U /* OTFDEC register callback disabled  */
+#define  USE_HAL_PCD_REGISTER_CALLBACKS     0U /* PCD register callback disabled     */
+#define  USE_HAL_QSPI_REGISTER_CALLBACKS    0U /* QSPI register callback disabled    */
+#define  USE_HAL_RNG_REGISTER_CALLBACKS     0U /* RNG register callback disabled     */
+#define  USE_HAL_RTC_REGISTER_CALLBACKS     0U /* RTC register callback disabled     */
+#define  USE_HAL_SAI_REGISTER_CALLBACKS     0U /* SAI register callback disabled     */
+#define  USE_HAL_SD_REGISTER_CALLBACKS      0U /* SD register callback disabled      */
+#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS  0U /* SMARTCARD register callback disabled */
+#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */
+#define  USE_HAL_SMBUS_REGISTER_CALLBACKS   0U /* SMBUS register callback disabled   */
+#define  USE_HAL_SPI_REGISTER_CALLBACKS     0U /* SPI register callback disabled     */
+#define  USE_HAL_SWPMI_REGISTER_CALLBACKS   0U /* SWPMI register callback disabled   */
+#define  USE_HAL_TIM_REGISTER_CALLBACKS     0U /* TIM register callback disabled     */
+#define  USE_HAL_UART_REGISTER_CALLBACKS    0U /* UART register callback disabled    */
+#define  USE_HAL_USART_REGISTER_CALLBACKS   0U /* USART register callback disabled   */
+#define  USE_HAL_WWDG_REGISTER_CALLBACKS    0U /* WWDG register callback disabled    */
+
+/* ########################### Ethernet Configuration ######################### */
+#define ETH_TX_DESC_CNT         4  /* number of Ethernet Tx DMA descriptors */
+#define ETH_RX_DESC_CNT         4  /* number of Ethernet Rx DMA descriptors */
+
+#define ETH_MAC_ADDR0    ((uint8_t)0x02)
+#define ETH_MAC_ADDR1    ((uint8_t)0x00)
+#define ETH_MAC_ADDR2    ((uint8_t)0x00)
+#define ETH_MAC_ADDR3    ((uint8_t)0x00)
+#define ETH_MAC_ADDR4    ((uint8_t)0x00)
+#define ETH_MAC_ADDR5    ((uint8_t)0x00)
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */ 
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file 
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32h7xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32h7xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32h7xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_MDMA_MODULE_ENABLED
+ #include "stm32h7xx_hal_mdma.h"
+#endif /* HAL_MDMA_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+  #include "stm32h7xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+  #include "stm32h7xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+  #include "stm32h7xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DSI_MODULE_ENABLED
+  #include "stm32h7xx_hal_dsi.h"
+#endif /* HAL_DSI_MODULE_ENABLED */
+
+#ifdef HAL_DFSDM_MODULE_ENABLED
+  #include "stm32h7xx_hal_dfsdm.h"
+#endif /* HAL_DFSDM_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+  #include "stm32h7xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32h7xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32h7xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32h7xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+  #include "stm32h7xx_hal_fdcan.h"
+#endif /* HAL_FDCAN_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+  #include "stm32h7xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32h7xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32h7xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32h7xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+  #include "stm32h7xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32h7xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GFXMMU_MODULE_ENABLED
+  #include "stm32h7xx_hal_gfxmmu.h"
+#endif /* HAL_GFXMMU_MODULE_ENABLED */
+
+#ifdef HAL_HRTIM_MODULE_ENABLED
+  #include "stm32h7xx_hal_hrtim.h"
+#endif /* HAL_HRTIM_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32h7xx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+  #include "stm32h7xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+  #include "stm32h7xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+  #include "stm32h7xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32h7xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32h7xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32h7xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_JPEG_MODULE_ENABLED
+ #include "stm32h7xx_hal_jpeg.h"
+#endif /* HAL_JPEG_MODULE_ENABLED */
+
+#ifdef HAL_MDIOS_MODULE_ENABLED
+ #include "stm32h7xx_hal_mdios.h"
+#endif /* HAL_MDIOS_MODULE_ENABLED */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+ #include "stm32h7xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+#include "stm32h7xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+#include "stm32h7xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_OPAMP_MODULE_ENABLED
+#include "stm32h7xx_hal_opamp.h"
+#endif /* HAL_OPAMP_MODULE_ENABLED */
+
+#ifdef HAL_OSPI_MODULE_ENABLED
+  #include "stm32h7xx_hal_ospi.h"
+#endif /* HAL_OSPI_MODULE_ENABLED */
+   
+#ifdef HAL_OTFDEC_MODULE_ENABLED
+#include "stm32h7xx_hal_otfdec.h"
+#endif /* HAL_OTFDEC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32h7xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32h7xx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RAMECC_MODULE_ENABLED
+ #include "stm32h7xx_hal_ramecc.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32h7xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32h7xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32h7xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32h7xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+ #include "stm32h7xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32h7xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_SPDIFRX_MODULE_ENABLED
+ #include "stm32h7xx_hal_spdifrx.h"
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */
+
+#ifdef HAL_SWPMI_MODULE_ENABLED
+ #include "stm32h7xx_hal_swpmi.h"
+#endif /* HAL_SWPMI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32h7xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32h7xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32h7xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32h7xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32h7xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32h7xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32h7xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32h7xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32h7xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_PSSI_MODULE_ENABLED
+  #include "stm32h7xx_hal_pssi.h"
+#endif /* HAL_PSSI_MODULE_ENABLED */
+
+#ifdef HAL_DTS_MODULE_ENABLED
+  #include "stm32h7xx_hal_dts.h"
+#endif /* HAL_DTS_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed. 
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32H7xx_HAL_CONF_H */
+ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/system_stm32h7xx.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/system_stm32h7xx.c
new file mode 100644
index 00000000..58da4c83
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/lib/system_stm32h7xx.c
@@ -0,0 +1,399 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32h7xx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-Mx Device Peripheral Access Layer System Source File.
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32h7xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock, it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32h7xx_system
+  * @{
+  */
+
+/** @addtogroup STM32H7xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32h7xx.h"
+#include <math.h>
+#if !defined  (HSE_VALUE)
+#define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (CSI_VALUE)
+  #define CSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* CSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Private_Defines
+  * @{
+  */
+
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to use initialized data in D2 domain SRAM (AHB SRAM) */
+/* #define DATA_IN_D2_SRAM */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00000000UL /*!< Vector Table base offset field.
+                                      This value must be a multiple of 0x200. */
+/******************************************************************************/
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Private_Variables
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock = 64000000;
+  uint32_t SystemD2Clock = 64000000;
+  const  uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the FPU setting and  vector table location
+  *         configuration.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+#if defined (DATA_IN_D2_SRAM)
+ __IO uint32_t tmpreg;
+#endif /* DATA_IN_D2_SRAM */
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2)));  /* set CP10 and CP11 Full Access */
+  #endif
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set HSION bit */
+  RCC->CR |= RCC_CR_HSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00000000;
+
+  /* Reset HSEON, CSSON , CSION,RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */
+  RCC->CR &= 0xEAF6ED7FU;
+
+#if defined(D3_SRAM_BASE)
+  /* Reset D1CFGR register */
+  RCC->D1CFGR = 0x00000000;
+
+  /* Reset D2CFGR register */
+  RCC->D2CFGR = 0x00000000;
+
+  /* Reset D3CFGR register */
+  RCC->D3CFGR = 0x00000000;
+#else
+  /* Reset CDCFGR1 register */
+  RCC->CDCFGR1 = 0x00000000;
+
+  /* Reset CDCFGR2 register */
+  RCC->CDCFGR2 = 0x00000000;
+
+  /* Reset SRDCFGR register */
+  RCC->SRDCFGR = 0x00000000;
+#endif
+  /* Reset PLLCKSELR register */
+  RCC->PLLCKSELR = 0x00000000;
+
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x00000000;
+  /* Reset PLL1DIVR register */
+  RCC->PLL1DIVR = 0x00000000;
+  /* Reset PLL1FRACR register */
+  RCC->PLL1FRACR = 0x00000000;
+
+  /* Reset PLL2DIVR register */
+  RCC->PLL2DIVR = 0x00000000;
+
+  /* Reset PLL2FRACR register */
+
+  RCC->PLL2FRACR = 0x00000000;
+  /* Reset PLL3DIVR register */
+  RCC->PLL3DIVR = 0x00000000;
+
+  /* Reset PLL3FRACR register */
+  RCC->PLL3FRACR = 0x00000000;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+
+#if (STM32H7_DEV_ID == 0x450UL)
+  /* dual core CM7 or single core line */
+  if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
+  {
+    /* if stm32h7 revY*/
+    /* Change  the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
+    *((__IO uint32_t*)0x51008108) = 0x000000001U;
+  }
+#endif
+
+#if defined (DATA_IN_D2_SRAM)
+  /* in case of initialized data in D2 SRAM (AHB SRAM) , enable the D2 SRAM clock (AHB SRAM clock) */
+#if defined(RCC_AHB2ENR_D2SRAM3EN)
+  RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);
+#elif defined(RCC_AHB2ENR_D2SRAM2EN)
+  RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN);
+#else
+  RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN);
+#endif /* RCC_AHB2ENR_D2SRAM3EN */
+
+  tmpreg = RCC->AHB2ENR;
+  (void) tmpreg;
+#endif /* DATA_IN_D2_SRAM */
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  /* Configure the Vector Table location add offset address for cortex-M4 ------------------*/
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = D2_AHBSRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+  SCB->VTOR = FLASH_BANK2_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif /* VECT_TAB_SRAM */
+
+#else
+
+  /* Configure the Vector Table location add offset address for cortex-M7 ------------------*/
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = D1_AXISRAM_BASE  | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal AXI-RAM */
+#else
+  SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+#endif /*DUAL_CORE && CORE_CM4*/
+
+}
+
+/**
+   * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock , it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*),
+  *             HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
+  *
+  *         (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *         (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+  *             64 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+  *              25 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
+  uint32_t common_system_clock;
+  float_t fracn1, pllvco;
+
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+  case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */
+    common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
+    break;
+
+  case RCC_CFGR_SWS_CSI:  /* CSI used as system clock  source */
+    common_system_clock = CSI_VALUE;
+    break;
+
+  case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
+    common_system_clock = HSE_VALUE;
+    break;
+
+  case RCC_CFGR_SWS_PLL1:  /* PLL1 used as system clock  source */
+
+    /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
+    SYSCLK = PLL_VCO / PLLR
+    */
+    pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+    pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4)  ;
+    pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
+    fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
+
+    if (pllm != 0U)
+    {
+      switch (pllsource)
+      {
+        case RCC_PLLCKSELR_PLLSRC_HSI:  /* HSI used as PLL clock source */
+
+        hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
+        pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+
+        break;
+
+        case RCC_PLLCKSELR_PLLSRC_CSI:  /* CSI used as PLL clock source */
+          pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+        break;
+
+        case RCC_PLLCKSELR_PLLSRC_HSE:  /* HSE used as PLL clock source */
+          pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+        break;
+
+      default:
+          pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+        break;
+      }
+      pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
+      common_system_clock =  (uint32_t)(float_t)(pllvco/(float_t)pllp);
+    }
+    else
+    {
+      common_system_clock = 0U;
+    }
+    break;
+
+  default:
+    common_system_clock = CSI_VALUE;
+    break;
+  }
+
+  /* Compute SystemClock frequency --------------------------------------------------*/
+#if defined (RCC_D1CFGR_D1CPRE)
+  tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];
+
+  /* common_system_clock frequency : CM7 CPU frequency  */
+  common_system_clock >>= tmp;
+
+  /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency  */
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+
+#else
+  tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos];
+
+  /* common_system_clock frequency : CM7 CPU frequency  */
+  common_system_clock >>= tmp;
+
+  /* SystemD2Clock frequency : AXI and AHBs Clock frequency  */
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+
+#endif
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  SystemCoreClock = SystemD2Clock;
+#else
+  SystemCoreClock = common_system_clock;
+#endif /* DUAL_CORE && CORE_CM4 */
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/main.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/main.c
new file mode 100644
index 00000000..7ee1d179
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/main.c
@@ -0,0 +1,280 @@
+/************************************************************************************//**
+* \file         Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/main.c
+* \brief        Demo program application source file.
+* \ingroup      Prog_ARMCM7_STM32H7_Nucleo_H743ZI_Keil
+* \internal
+*----------------------------------------------------------------------------------------
+*                          C O P Y R I G H T
+*----------------------------------------------------------------------------------------
+*   Copyright (c) 2020  by Feaser    http://www.feaser.com    All rights reserved
+*
+*----------------------------------------------------------------------------------------
+*                            L I C E N S E
+*----------------------------------------------------------------------------------------
+* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as published by the Free
+* Software Foundation, either version 3 of the License, or (at your option) any later
+* version.
+*
+* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+* PURPOSE. See the GNU General Public License for more details.
+*
+* You have received a copy of the GNU General Public License along with OpenBLT. It
+* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
+*
+* \endinternal
+****************************************************************************************/
+
+/****************************************************************************************
+* Include files
+****************************************************************************************/
+#include "header.h"                                    /* generic header               */
+
+
+/****************************************************************************************
+* Function prototypes
+****************************************************************************************/
+static void Init(void);
+static void SystemClock_Config(void);
+static void VectorBase_Config(void);
+
+
+/************************************************************************************//**
+** \brief     This is the entry point for the bootloader application and is called
+**            by the reset interrupt vector after the C-startup routines executed.
+** \return    Program exit code.
+**
+****************************************************************************************/
+int main(void)
+{
+  /* Initialize the microcontroller */
+  Init();
+  /* Initialize the bootloader interface */
+  BootComInit();
+
+  /* start the infinite program loop */
+  while (1)
+  {
+    /* Toggle LED with a fixed frequency. */
+    LedToggle();
+    /* Check for bootloader activation request. */
+    BootComCheckActivationRequest();
+  }
+  /* Set program exit code. note that the program should never get here. */
+  return 0;
+} /*** end of main ***/
+
+
+/************************************************************************************//**
+** \brief     Initializes the microcontroller.
+** \return    none.
+**
+****************************************************************************************/
+static void Init(void)
+{
+  /* Configure the vector table base address. */
+  VectorBase_Config();
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+  /* Configure the system clock. */
+  SystemClock_Config();
+  /* Initialize the timer driver. */
+  TimerInit();
+  /* Initialize the led driver. */
+  LedInit();
+} /*** end of Init ***/
+
+
+/************************************************************************************//**
+** \brief     Vector base address configuration. It should no longer be at the start of
+**            flash memory but moved forward because the first part of flash is
+**            reserved for the bootloader. Note that this is already done by the
+**            bootloader before starting this program. Unfortunately, function
+**            SystemInit() overwrites this change again. 
+** \return    none.
+**
+****************************************************************************************/
+static void VectorBase_Config(void)
+{
+  /* The constant array with vectors of the vector table is declared externally in the
+   * c-startup code.
+   */
+  extern const unsigned long __Vectors[];
+
+  /* Remap the vector table to where the vector table is located for this program. */
+  SCB->VTOR = (unsigned long)&__Vectors[0];
+} /*** end of VectorBase_Config ***/
+
+
+/************************************************************************************//**
+** \brief     System Clock Configuration. This code was created by CubeMX and configures
+**            the system clock.
+** \return    none.
+**
+****************************************************************************************/
+static void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
+
+  /* Supply configuration update enable. */
+  HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
+  /* Configure the main internal regulator output voltage. */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
+  while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY))
+  {
+    ;
+  }
+
+  /* Initializes the CPU, AHB and APB busses clocks. */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM = 4;
+  RCC_OscInitStruct.PLL.PLLN = 480;
+  RCC_OscInitStruct.PLL.PLLP = 2;
+  RCC_OscInitStruct.PLL.PLLQ = 4;
+  RCC_OscInitStruct.PLL.PLLR = 2;
+  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_1;
+  RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
+  RCC_OscInitStruct.PLL.PLLFRACN = 0;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    /* Clock configuration incorrect or hardware failure. Hang the system to prevent
+     * damage.
+     */
+    while (1);
+  }
+
+  /* Initializes the CPU, AHB and APB busses clocks. */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |
+                                RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 |
+                                RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
+  RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
+  RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
+  {
+    /* Clock configuration incorrect or hardware failure. Hang the system to prevent
+     * damage.
+     */
+    while (1);
+  }
+} /*** end of SystemClock_Config ***/
+
+
+/************************************************************************************//**
+** \brief     Initializes the Global MSP. This function is called from HAL_Init()
+**            function to perform system level initialization (GPIOs, clock, DMA,
+**            interrupt).
+** \return    none.
+**
+****************************************************************************************/
+void HAL_MspInit(void)
+{
+  GPIO_InitTypeDef GPIO_InitStruct;
+
+  /* SYSCFG clock enable. */
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+  /* GPIO ports clock enable. */
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+#if (BOOT_COM_RS232_ENABLE > 0)
+  /* Peripheral clock enable. */
+  __HAL_RCC_USART3_CLK_ENABLE();
+#endif /* BOOT_COM_RS232_ENABLE > 0 */
+#if (BOOT_COM_CAN_ENABLE > 0)
+  /* Peripheral clock enable. */
+  __HAL_RCC_FDCAN_CLK_ENABLE();
+#endif /* BOOT_COM_CAN_ENABLE > 0 */
+
+  /* Set priority grouping. */
+  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+  /* MemoryManagement_IRQn interrupt configuration. */
+  HAL_NVIC_SetPriority(MemoryManagement_IRQn, 0, 0);
+  /* BusFault_IRQn interrupt configuration. */
+  HAL_NVIC_SetPriority(BusFault_IRQn, 0, 0);
+  /* UsageFault_IRQn interrupt configuration. */
+  HAL_NVIC_SetPriority(UsageFault_IRQn, 0, 0);
+  /* SVCall_IRQn interrupt configuration. */
+  HAL_NVIC_SetPriority(SVCall_IRQn, 0, 0);
+  /* DebugMonitor_IRQn interrupt configuration. */
+  HAL_NVIC_SetPriority(DebugMonitor_IRQn, 0, 0);
+  /* PendSV_IRQn interrupt configuration. */
+  HAL_NVIC_SetPriority(PendSV_IRQn, 0, 0);
+  /* SysTick_IRQn interrupt configuration. */
+  HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0);
+
+  /* Configure the LED GPIO pin. */
+  GPIO_InitStruct.Pin = GPIO_PIN_7;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+#if (BOOT_COM_RS232_ENABLE > 0)
+  /* UART TX and RX GPIO pin configuration. */
+  GPIO_InitStruct.Pin = GPIO_PIN_8 | GPIO_PIN_9;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.Alternate = GPIO_AF7_USART3;
+  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+#endif /* BOOT_COM_RS232_ENABLE > 0 */
+#if (BOOT_COM_CAN_ENABLE > 0)
+  /* CAN TX and RX GPIO pin configuration. */
+  GPIO_InitStruct.Pin = GPIO_PIN_8 | GPIO_PIN_9;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN1;
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+#endif /* BOOT_COM_CAN_ENABLE > 0 */
+} /*** end of HAL_MspInit ***/
+
+
+/************************************************************************************//**
+** \brief     Deinitializes the Global MSP. This function is called from HAL_DeInit()
+**            function to perform system level Deinitialization (GPIOs, clock, DMA,
+**            interrupt).
+** \return    none.
+**
+****************************************************************************************/
+void HAL_MspDeInit(void)
+{
+#if (BOOT_COM_CAN_ENABLE > 0)
+  /* Reset CAN GPIO pin configuration. */
+  HAL_GPIO_DeInit(GPIOB, GPIO_PIN_8 | GPIO_PIN_9);
+#endif /* BOOT_COM_CAN_ENABLE > 0 */
+#if (BOOT_COM_RS232_ENABLE > 0)
+  /* Reset UART GPIO pin configuration. */
+  HAL_GPIO_DeInit(GPIOD, GPIO_PIN_8 | GPIO_PIN_9);
+#endif /* BOOT_COM_RS232_ENABLE > 0 */
+  /* Deconfigure GPIO pin for the LED. */
+  HAL_GPIO_WritePin(GPIOB, GPIO_PIN_7, GPIO_PIN_RESET);
+  HAL_GPIO_DeInit(GPIOB, GPIO_PIN_7);
+
+#if (BOOT_COM_CAN_ENABLE > 0)
+  /* Peripheral clock enable. */
+  __HAL_RCC_FDCAN_CLK_DISABLE();
+#endif /* BOOT_COM_CAN_ENABLE > 0 */
+#if (BOOT_COM_RS232_ENABLE > 0)
+  /* Peripheral clock disable. */
+  __HAL_RCC_USART3_CLK_DISABLE();
+#endif /* BOOT_COM_RS232_ENABLE > 0 */
+  /* GPIO ports clock disable. */
+  __HAL_RCC_GPIOD_CLK_DISABLE();
+  __HAL_RCC_GPIOC_CLK_DISABLE();
+  __HAL_RCC_GPIOB_CLK_DISABLE();
+  /* SYSCFG clock disable. */
+  __HAL_RCC_SYSCFG_CLK_DISABLE();
+} /*** end of HAL_MspDeInit ***/
+
+
+/*********************************** end of main.c *************************************/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/prog.dox b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/prog.dox
new file mode 100644
index 00000000..18cb5444
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/prog.dox
@@ -0,0 +1,16 @@
+/**
+\defgroup   Prog_ARMCM7_STM32H7_Nucleo_H743ZI_Keil User Program
+\ingroup    ARMCM7_STM32H7_Nucleo_H743ZI_Keil
+\brief      User Program. 
+\details    The intention of the demo user program is two-fold. (1) To test the 
+            bootloader, you need some sort of firmware to see if you can perform a
+            firmware update with the bootloader. This program can be used for this
+            purpose. (2) To make firmware programmable by the bootloader, a few 
+            adjustments to the firmware are required. The demo user program serves as an 
+            example for how these adjustments can be implemented. Additional details on
+            this subject can be found in the port specifics documentation, which is
+            available at: 
+            https://www.feaser.com/openblt/doku.php?id=manual:ports:armcm7_stm32h7.
+*/
+
+
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/startup_stm32h743xx.s b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/startup_stm32h743xx.s
new file mode 100644
index 00000000..0a2ea64e
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/startup_stm32h743xx.s
@@ -0,0 +1,614 @@
+;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;* File Name          : startup_stm32h743xx.s
+;* @author  MCD Application Team
+;* Description        : STM32H7xx devices vector table for MDK-ARM toolchain. 
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp                      ; Top of Stack
+                DCD     Reset_Handler                     ; Reset Handler
+                DCD     NMI_Handler                       ; NMI Handler
+                DCD     HardFault_Handler                 ; Hard Fault Handler
+                DCD     MemManage_Handler                 ; MPU Fault Handler
+                DCD     BusFault_Handler                  ; Bus Fault Handler
+                DCD     UsageFault_Handler                ; Usage Fault Handler
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     SVC_Handler                       ; SVCall Handler
+                DCD     DebugMon_Handler                  ; Debug Monitor Handler
+                DCD     0                                 ; Reserved
+                DCD     PendSV_Handler                    ; PendSV Handler
+                DCD     SysTick_Handler                   ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog interrupt ( wwdg1_it)                                         
+                DCD     PVD_AVD_IRQHandler                ; PVD/AVD through EXTI Line detection                        
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line            
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line                       
+                DCD     FLASH_IRQHandler                  ; FLASH                                           
+                DCD     RCC_IRQHandler                    ; RCC                                             
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0                                             
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1                                             
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2                                             
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3                                             
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4 
+                DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0
+                DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1                                   
+                DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2                                   
+                DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3                                   
+                DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4                                   
+                DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5                                   
+                DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6  
+                DCD     ADC_IRQHandler                    ; ADC1, ADC2                             
+                DCD     FDCAN1_IT0_IRQHandler             ; FDCAN1 interrupt line 0                        
+                DCD     FDCAN2_IT0_IRQHandler             ; FDCAN2 interrupt line 0                               
+                DCD     FDCAN1_IT1_IRQHandler             ; FDCAN1 interrupt line 1                        
+                DCD     FDCAN2_IT1_IRQHandler             ; FDCAN2 interrupt line 1                                               
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s                                    
+                DCD     TIM1_BRK_IRQHandler               ; TIM1 Break interrupt                   
+                DCD     TIM1_UP_IRQHandler                ; TIM1 Update Interrupt                 
+                DCD     TIM1_TRG_COM_IRQHandler           ; TIM1 Trigger and Commutation Interrupt 
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare                                   
+                DCD     TIM2_IRQHandler                   ; TIM2                                            
+                DCD     TIM3_IRQHandler                   ; TIM3                                            
+                DCD     TIM4_IRQHandler                   ; TIM4                                            
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event                                             
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error                                             
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event                                             
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error                                               
+                DCD     SPI1_IRQHandler                   ; SPI1                                            
+                DCD     SPI2_IRQHandler                   ; SPI2                                            
+                DCD     USART1_IRQHandler                 ; USART1                                          
+                DCD     USART2_IRQHandler                 ; USART2                                          
+                DCD     USART3_IRQHandler                 ; USART3                                          
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]  
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+                DCD     0                                 ; Reserved                                          
+                DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break Interrupt and TIM12 global interrupt                 
+                DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update Interrupt and TIM13 global interrupt
+                DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt
+                DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7                                           
+                DCD     FMC_IRQHandler                    ; FMC                             
+                DCD     SDMMC1_IRQHandler                 ; SDMMC1                            
+                DCD     TIM5_IRQHandler                   ; TIM5                            
+                DCD     SPI3_IRQHandler                   ; SPI3                            
+                DCD     UART4_IRQHandler                  ; UART4                           
+                DCD     UART5_IRQHandler                  ; UART5                           
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors           
+                DCD     TIM7_IRQHandler                   ; TIM7           
+                DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0                   
+                DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1                   
+                DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2                   
+                DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3                   
+                DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4                   
+                DCD     ETH_IRQHandler                    ; Ethernet                        
+                DCD     ETH_WKUP_IRQHandler               ; Ethernet Wakeup through EXTI line              
+                DCD     FDCAN_CAL_IRQHandler              ; FDCAN calibration unit interrupt                        
+                DCD     0                                 ; Reserved                              
+                DCD     0                                 ; Reserved 
+                DCD     0                                 ; Reserved 
+                DCD     0                                 ; Reserved                      
+                DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5                   
+                DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6                   
+                DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7                   
+                DCD     USART6_IRQHandler                 ; USART6                           
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event                             
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error                             
+                DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out                      
+                DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In                       
+                DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI                         
+                DCD     OTG_HS_IRQHandler                 ; USB OTG HS                    
+                DCD     DCMI_IRQHandler                   ; DCMI                            
+                DCD     0                                 ; Reserved                                     
+                DCD     RNG_IRQHandler                    ; Rng
+                DCD     FPU_IRQHandler                    ; FPU
+                DCD     UART7_IRQHandler                  ; UART7
+                DCD     UART8_IRQHandler                  ; UART8
+                DCD     SPI4_IRQHandler                   ; SPI4
+                DCD     SPI5_IRQHandler                   ; SPI5
+                DCD     SPI6_IRQHandler                   ; SPI6
+                DCD     SAI1_IRQHandler                   ; SAI1
+                DCD     LTDC_IRQHandler                   ; LTDC
+                DCD     LTDC_ER_IRQHandler                ; LTDC error
+                DCD     DMA2D_IRQHandler                  ; DMA2D
+                DCD     SAI2_IRQHandler                   ; SAI2
+                DCD     QUADSPI_IRQHandler                ; QUADSPI
+                DCD     LPTIM1_IRQHandler                 ; LPTIM1
+                DCD     CEC_IRQHandler                    ; HDMI_CEC
+                DCD     I2C4_EV_IRQHandler                ; I2C4 Event                             
+                DCD     I2C4_ER_IRQHandler                ; I2C4 Error 
+                DCD     SPDIF_RX_IRQHandler               ; SPDIF_RX
+                DCD     OTG_FS_EP1_OUT_IRQHandler         ; USB OTG FS End Point 1 Out                      
+                DCD     OTG_FS_EP1_IN_IRQHandler          ; USB OTG FS End Point 1 In                       
+                DCD     OTG_FS_WKUP_IRQHandler            ; USB OTG FS Wakeup through EXTI                         
+                DCD     OTG_FS_IRQHandler                 ; USB OTG FS                 
+                DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX1 Overrun interrupt  
+                DCD     HRTIM1_Master_IRQHandler          ; HRTIM Master Timer global Interrupts                              
+                DCD     HRTIM1_TIMA_IRQHandler            ; HRTIM Timer A global Interrupt                                    
+                DCD     HRTIM1_TIMB_IRQHandler            ; HRTIM Timer B global Interrupt                                    
+                DCD     HRTIM1_TIMC_IRQHandler            ; HRTIM Timer C global Interrupt                                    
+                DCD     HRTIM1_TIMD_IRQHandler            ; HRTIM Timer D global Interrupt                                    
+                DCD     HRTIM1_TIME_IRQHandler            ; HRTIM Timer E global Interrupt                                    
+                DCD     HRTIM1_FLT_IRQHandler             ; HRTIM Fault global Interrupt 
+                DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM Filter0 Interrupt   
+                DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM Filter1 Interrupt                                            
+                DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM Filter2 Interrupt                                            
+                DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM Filter3 Interrupt                                                                                    
+                DCD     SAI3_IRQHandler                   ; SAI3 global Interrupt                                             
+                DCD     SWPMI1_IRQHandler                 ; Serial Wire Interface 1 global interrupt                          
+                DCD     TIM15_IRQHandler                  ; TIM15 global Interrupt                                            
+                DCD     TIM16_IRQHandler                  ; TIM16 global Interrupt                                            
+                DCD     TIM17_IRQHandler                  ; TIM17 global Interrupt                                            
+                DCD     MDIOS_WKUP_IRQHandler             ; MDIOS Wakeup  Interrupt                                           
+                DCD     MDIOS_IRQHandler                  ; MDIOS global Interrupt                                            
+                DCD     JPEG_IRQHandler                   ; JPEG global Interrupt                                             
+                DCD     MDMA_IRQHandler                   ; MDMA global Interrupt                                             
+                DCD     0                                 ; Reserved                                               
+                DCD     SDMMC2_IRQHandler                 ; SDMMC2 global Interrupt                                           
+                DCD     HSEM1_IRQHandler                  ; HSEM1 global Interrupt                                             
+                DCD     0                                 ; Reserved                                              
+                DCD     ADC3_IRQHandler                   ; ADC3 global Interrupt                                              
+                DCD     DMAMUX2_OVR_IRQHandler            ; DMAMUX Overrun interrupt                                           
+                DCD     BDMA_Channel0_IRQHandler          ; BDMA Channel 0 global Interrupt                                    
+                DCD     BDMA_Channel1_IRQHandler          ; BDMA Channel 1 global Interrupt                                    
+                DCD     BDMA_Channel2_IRQHandler          ; BDMA Channel 2 global Interrupt                                    
+                DCD     BDMA_Channel3_IRQHandler          ; BDMA Channel 3 global Interrupt                                    
+                DCD     BDMA_Channel4_IRQHandler          ; BDMA Channel 4 global Interrupt                                    
+                DCD     BDMA_Channel5_IRQHandler          ; BDMA Channel 5 global Interrupt                                    
+                DCD     BDMA_Channel6_IRQHandler          ; BDMA Channel 6 global Interrupt                                    
+                DCD     BDMA_Channel7_IRQHandler          ; BDMA Channel 7 global Interrupt                                    
+                DCD     COMP1_IRQHandler                  ; COMP1 global Interrupt                                            
+                DCD     LPTIM2_IRQHandler                 ; LP TIM2 global interrupt                                          
+                DCD     LPTIM3_IRQHandler                 ; LP TIM3 global interrupt                                          
+                DCD     LPTIM4_IRQHandler                 ; LP TIM4 global interrupt                                          
+                DCD     LPTIM5_IRQHandler                 ; LP TIM5 global interrupt                                          
+                DCD     LPUART1_IRQHandler                ; LP UART1 interrupt                                                
+                DCD     0                                 ; Reserved                                                                              
+                DCD     CRS_IRQHandler                    ; Clock Recovery Global Interrupt                                   
+                DCD     ECC_IRQHandler                    ; ECC diagnostic Global Interrupt                                              
+                DCD     SAI4_IRQHandler                   ; SAI4 global interrupt                                                
+                DCD     0                                 ; Reserved                                 
+                DCD     0                                 ; Reserved                                    
+                DCD     WAKEUP_PIN_IRQHandler             ; Interrupt for all 6 wake-up pins 
+                DCD     0x55AA11EE                        ; Reserved for OpenBLT checksum
+                
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                    [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =__initial_sp
+                 MOV     SP, R0
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                      [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler                [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler                [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler                 [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler               [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                      [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler                  [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                    [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                   [WEAK]
+                B       .
+                ENDP                                     
+                                                          
+Default_Handler PROC                                      
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]                                       
+                EXPORT  PVD_AVD_IRQHandler                [WEAK]                         
+                EXPORT  TAMP_STAMP_IRQHandler             [WEAK]   
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]             
+                EXPORT  FLASH_IRQHandler                  [WEAK]                                        
+                EXPORT  RCC_IRQHandler                    [WEAK]                                          
+                EXPORT  EXTI0_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI1_IRQHandler                  [WEAK]                                           
+                EXPORT  EXTI2_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI3_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Stream0_IRQHandler           [WEAK] 
+                EXPORT  DMA1_Stream1_IRQHandler           [WEAK]                        
+                EXPORT  DMA1_Stream2_IRQHandler           [WEAK]                     
+                EXPORT  DMA1_Stream3_IRQHandler           [WEAK]                    
+                EXPORT  DMA1_Stream4_IRQHandler           [WEAK]                        
+                EXPORT  DMA1_Stream5_IRQHandler           [WEAK]                          
+                EXPORT  DMA1_Stream6_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream7_IRQHandler           [WEAK]
+                EXPORT  ADC_IRQHandler                    [WEAK]                          
+                EXPORT  FDCAN1_IT0_IRQHandler             [WEAK]                                            
+                EXPORT  FDCAN2_IT0_IRQHandler             [WEAK] 
+                EXPORT  FDCAN1_IT1_IRQHandler             [WEAK]                                            
+                EXPORT  FDCAN2_IT1_IRQHandler             [WEAK]   
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]                                    
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]                  
+                EXPORT  TIM1_UP_IRQHandler                [WEAK]                
+                EXPORT  TIM1_TRG_COM_IRQHandler           [WEAK] 
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]                                   
+                EXPORT  TIM2_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM3_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM4_IRQHandler                   [WEAK]                                            
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]                                             
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]                                             
+                EXPORT  I2C2_EV_IRQHandler                [WEAK]                                            
+                EXPORT  I2C2_ER_IRQHandler                [WEAK]                                               
+                EXPORT  SPI1_IRQHandler                   [WEAK]                                           
+                EXPORT  SPI2_IRQHandler                   [WEAK]                                            
+                EXPORT  USART1_IRQHandler                 [WEAK]                                          
+                EXPORT  USART2_IRQHandler                 [WEAK]                                          
+                EXPORT  USART3_IRQHandler                 [WEAK]                                         
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]                                  
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]                                       
+                EXPORT  TIM8_BRK_TIM12_IRQHandler         [WEAK]                 
+                EXPORT  TIM8_UP_TIM13_IRQHandler          [WEAK]                 
+                EXPORT  TIM8_TRG_COM_TIM14_IRQHandler     [WEAK] 
+                EXPORT  TIM8_CC_IRQHandler                [WEAK]                                   
+                EXPORT  DMA1_Stream7_IRQHandler           [WEAK]                                          
+                EXPORT  FMC_IRQHandler                    [WEAK]                                             
+                EXPORT  SDMMC1_IRQHandler                 [WEAK]                                             
+                EXPORT  TIM5_IRQHandler                   [WEAK]                                             
+                EXPORT  SPI3_IRQHandler                   [WEAK]                                             
+                EXPORT  UART4_IRQHandler                  [WEAK]                                            
+                EXPORT  UART5_IRQHandler                  [WEAK]                                            
+                EXPORT  TIM6_DAC_IRQHandler               [WEAK]                   
+                EXPORT  TIM7_IRQHandler                   [WEAK]                    
+                EXPORT  DMA2_Stream0_IRQHandler           [WEAK]                                  
+                EXPORT  DMA2_Stream1_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream2_IRQHandler           [WEAK]                                    
+                EXPORT  DMA2_Stream3_IRQHandler           [WEAK]                                    
+                EXPORT  DMA2_Stream4_IRQHandler           [WEAK]                                 
+                EXPORT  ETH_IRQHandler                    [WEAK]                                         
+                EXPORT  ETH_WKUP_IRQHandler               [WEAK]                     
+                EXPORT  FDCAN_CAL_IRQHandler              [WEAK]                                                                                                                                                                              
+                EXPORT  DMA2_Stream5_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream6_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream7_IRQHandler           [WEAK]                                   
+                EXPORT  USART6_IRQHandler                 [WEAK]                                           
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]                                              
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]                                              
+                EXPORT  OTG_HS_EP1_OUT_IRQHandler         [WEAK]                      
+                EXPORT  OTG_HS_EP1_IN_IRQHandler          [WEAK]                      
+                EXPORT  OTG_HS_WKUP_IRQHandler            [WEAK]                        
+                EXPORT  OTG_HS_IRQHandler                 [WEAK]                                      
+                EXPORT  DCMI_IRQHandler                   [WEAK]                                             
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  UART7_IRQHandler                  [WEAK]
+                EXPORT  UART8_IRQHandler                  [WEAK]
+                EXPORT  SPI4_IRQHandler                   [WEAK]
+                EXPORT  SPI5_IRQHandler                   [WEAK]
+                EXPORT  SPI6_IRQHandler                   [WEAK]
+                EXPORT  SAI1_IRQHandler                   [WEAK]
+                EXPORT  LTDC_IRQHandler                   [WEAK]
+                EXPORT  LTDC_ER_IRQHandler                [WEAK]
+                EXPORT  DMA2D_IRQHandler                  [WEAK]
+                EXPORT  SAI2_IRQHandler                   [WEAK]   
+                EXPORT  QUADSPI_IRQHandler                [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  CEC_IRQHandler                    [WEAK]   
+                EXPORT  I2C4_EV_IRQHandler                [WEAK]
+                EXPORT  I2C4_ER_IRQHandler                [WEAK] 
+                EXPORT  SPDIF_RX_IRQHandler               [WEAK]
+                EXPORT  OTG_FS_EP1_OUT_IRQHandler         [WEAK]
+                EXPORT  OTG_FS_EP1_IN_IRQHandler          [WEAK]                      
+                EXPORT  OTG_FS_WKUP_IRQHandler            [WEAK]                      
+                EXPORT  OTG_FS_IRQHandler                 [WEAK]                        
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+                EXPORT  HRTIM1_Master_IRQHandler          [WEAK] 
+                EXPORT  HRTIM1_TIMA_IRQHandler            [WEAK]                                      
+                EXPORT  HRTIM1_TIMB_IRQHandler            [WEAK]                                      
+                EXPORT  HRTIM1_TIMC_IRQHandler            [WEAK]                                      
+                EXPORT  HRTIM1_TIMD_IRQHandler            [WEAK]                                      
+                EXPORT  HRTIM1_TIME_IRQHandler            [WEAK]                                      
+                EXPORT  HRTIM1_FLT_IRQHandler             [WEAK]
+                EXPORT  DFSDM1_FLT0_IRQHandler            [WEAK] 
+                EXPORT  DFSDM1_FLT1_IRQHandler            [WEAK]                                             
+                EXPORT  DFSDM1_FLT2_IRQHandler            [WEAK]                                             
+                EXPORT  DFSDM1_FLT3_IRQHandler            [WEAK]                                                                                        
+                EXPORT  SAI3_IRQHandler                   [WEAK]                                             
+                EXPORT  SWPMI1_IRQHandler                 [WEAK]                            
+                EXPORT  TIM15_IRQHandler                  [WEAK]                                             
+                EXPORT  TIM16_IRQHandler                  [WEAK]                                              
+                EXPORT  TIM17_IRQHandler                  [WEAK]                                            
+                EXPORT  MDIOS_WKUP_IRQHandler             [WEAK]                                             
+                EXPORT  MDIOS_IRQHandler                  [WEAK]                                              
+                EXPORT  JPEG_IRQHandler                   [WEAK]                                               
+                EXPORT  MDMA_IRQHandler                   [WEAK]                                                                                             
+                EXPORT  SDMMC2_IRQHandler                 [WEAK]                                             
+                EXPORT  HSEM1_IRQHandler                  [WEAK]                                                                                                             
+                EXPORT  ADC3_IRQHandler                   [WEAK]                                                
+                EXPORT  DMAMUX2_OVR_IRQHandler            [WEAK]                                            
+                EXPORT  BDMA_Channel0_IRQHandler          [WEAK]                                      
+                EXPORT  BDMA_Channel1_IRQHandler          [WEAK]                                      
+                EXPORT  BDMA_Channel2_IRQHandler          [WEAK]                                      
+                EXPORT  BDMA_Channel3_IRQHandler          [WEAK]                                      
+                EXPORT  BDMA_Channel4_IRQHandler          [WEAK]                                     
+                EXPORT  BDMA_Channel5_IRQHandler          [WEAK]                                      
+                EXPORT  BDMA_Channel6_IRQHandler          [WEAK]                                      
+                EXPORT  BDMA_Channel7_IRQHandler          [WEAK]                                     
+                EXPORT  COMP1_IRQHandler                  [WEAK]                                              
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]                                           
+                EXPORT  LPTIM3_IRQHandler                 [WEAK]                                            
+                EXPORT  LPTIM4_IRQHandler                 [WEAK]                                            
+                EXPORT  LPTIM5_IRQHandler                 [WEAK]                                            
+                EXPORT  LPUART1_IRQHandler                [WEAK]                                                  
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  ECC_IRQHandler                    [WEAK] 				
+                EXPORT  SAI4_IRQHandler                   [WEAK]                                                                                     
+                EXPORT  WAKEUP_PIN_IRQHandler             [WEAK] 
+
+
+WWDG_IRQHandler                                                          
+PVD_AVD_IRQHandler                                             
+TAMP_STAMP_IRQHandler                
+RTC_WKUP_IRQHandler                            
+FLASH_IRQHandler                                                          
+RCC_IRQHandler                                                              
+EXTI0_IRQHandler                                                              
+EXTI1_IRQHandler                                                             
+EXTI2_IRQHandler                                                              
+EXTI3_IRQHandler                                                              
+EXTI4_IRQHandler 
+DMA1_Stream0_IRQHandler
+DMA1_Stream1_IRQHandler                                  
+DMA1_Stream2_IRQHandler                               
+DMA1_Stream3_IRQHandler                              
+DMA1_Stream4_IRQHandler                                  
+DMA1_Stream5_IRQHandler                                    
+DMA1_Stream6_IRQHandler                   
+ADC_IRQHandler                                           
+FDCAN1_IT0_IRQHandler
+FDCAN2_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
+FDCAN2_IT1_IRQHandler
+EXTI9_5_IRQHandler                                                
+TIM1_BRK_IRQHandler                        
+TIM1_UP_IRQHandler                      
+TIM1_TRG_COM_IRQHandler  
+TIM1_CC_IRQHandler                                               
+TIM2_IRQHandler                                                           
+TIM3_IRQHandler                                                           
+TIM4_IRQHandler                                                           
+I2C1_EV_IRQHandler                                                         
+I2C1_ER_IRQHandler                                                         
+I2C2_EV_IRQHandler                                                        
+I2C2_ER_IRQHandler                                                           
+SPI1_IRQHandler                                                          
+SPI2_IRQHandler                                                           
+USART1_IRQHandler                                                       
+USART2_IRQHandler                                                       
+USART3_IRQHandler                                                      
+EXTI15_10_IRQHandler                                            
+RTC_Alarm_IRQHandler                                                           
+TIM8_BRK_TIM12_IRQHandler                      
+TIM8_UP_TIM13_IRQHandler                       
+TIM8_TRG_COM_TIM14_IRQHandler  
+TIM8_CC_IRQHandler                                               
+DMA1_Stream7_IRQHandler                                                 
+FMC_IRQHandler                                                            
+SDMMC1_IRQHandler                                                            
+TIM5_IRQHandler                                                            
+SPI3_IRQHandler                                                            
+UART4_IRQHandler                                                          
+UART5_IRQHandler                                                          
+TIM6_DAC_IRQHandler                            
+TIM7_IRQHandler                              
+DMA2_Stream0_IRQHandler                                         
+DMA2_Stream1_IRQHandler                                          
+DMA2_Stream2_IRQHandler                                           
+DMA2_Stream3_IRQHandler                                           
+DMA2_Stream4_IRQHandler                                        
+ETH_IRQHandler                                                         
+ETH_WKUP_IRQHandler                                
+FDCAN_CAL_IRQHandler                                                                                                                                                                                                                            
+DMA2_Stream5_IRQHandler                                          
+DMA2_Stream6_IRQHandler                                          
+DMA2_Stream7_IRQHandler                                          
+USART6_IRQHandler                                                        
+I2C3_EV_IRQHandler                                                          
+I2C3_ER_IRQHandler                                                          
+OTG_HS_EP1_OUT_IRQHandler 
+OTG_HS_EP1_IN_IRQHandler 
+OTG_HS_WKUP_IRQHandler   
+OTG_HS_IRQHandler        
+DCMI_IRQHandler                                                            
+RNG_IRQHandler
+FPU_IRQHandler  
+UART7_IRQHandler                  
+UART8_IRQHandler                  
+SPI4_IRQHandler                   
+SPI5_IRQHandler                   
+SPI6_IRQHandler                   
+SAI1_IRQHandler                   
+LTDC_IRQHandler                   
+LTDC_ER_IRQHandler                 
+DMA2D_IRQHandler   
+SAI2_IRQHandler        
+QUADSPI_IRQHandler
+LPTIM1_IRQHandler
+CEC_IRQHandler
+I2C4_EV_IRQHandler
+I2C4_ER_IRQHandler
+SPDIF_RX_IRQHandler
+OTG_FS_EP1_OUT_IRQHandler
+OTG_FS_EP1_IN_IRQHandler 
+OTG_FS_WKUP_IRQHandler   
+OTG_FS_IRQHandler        
+DMAMUX1_OVR_IRQHandler
+HRTIM1_Master_IRQHandler               
+HRTIM1_TIMA_IRQHandler                                                      
+HRTIM1_TIMB_IRQHandler                                                      
+HRTIM1_TIMC_IRQHandler                                                      
+HRTIM1_TIMD_IRQHandler                                                      
+HRTIM1_TIME_IRQHandler                                                      
+HRTIM1_FLT_IRQHandler 
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler                                                                
+DFSDM1_FLT2_IRQHandler                                                                
+DFSDM1_FLT3_IRQHandler                                                                                                                                
+SAI3_IRQHandler                                                                    
+SWPMI1_IRQHandler                                                 
+TIM15_IRQHandler                                                                   
+TIM16_IRQHandler                                                                    
+TIM17_IRQHandler                                                                  
+MDIOS_WKUP_IRQHandler                                                              
+MDIOS_IRQHandler                                                                    
+JPEG_IRQHandler                                                                      
+MDMA_IRQHandler                                                                                                                                            
+SDMMC2_IRQHandler                                                                  
+HSEM1_IRQHandler                                                                                                                                       
+ADC3_IRQHandler                                                                       
+DMAMUX2_OVR_IRQHandler                                                            
+BDMA_Channel0_IRQHandler                                                     
+BDMA_Channel1_IRQHandler                                                     
+BDMA_Channel2_IRQHandler                                                     
+BDMA_Channel3_IRQHandler                                                     
+BDMA_Channel4_IRQHandler                                                    
+BDMA_Channel5_IRQHandler                                                     
+BDMA_Channel6_IRQHandler                                                     
+BDMA_Channel7_IRQHandler                                                    
+COMP1_IRQHandler                                                                    
+LPTIM2_IRQHandler                                                                
+LPTIM3_IRQHandler                                                                 
+LPTIM4_IRQHandler                                                                 
+LPTIM5_IRQHandler                                                                 
+LPUART1_IRQHandler                                                                                                                         
+CRS_IRQHandler
+ECC_IRQHandler                                                            
+SAI4_IRQHandler      
+WAKEUP_PIN_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/stm32h743.sct b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/stm32h743.sct
new file mode 100644
index 00000000..812ce89f
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/stm32h743.sct
@@ -0,0 +1,19 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08020000 0x001E0000  {    ; load region size_region
+  ER_IROM1 0x08020000 0x001E0000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+   .ANY (+XO)
+  }
+  RW_IRAM1 0x20000000 0x00020000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_IRAM2 0x24000000 0x00080000  {
+   .ANY (+RW +ZI)
+  }
+}
+
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/timer.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/timer.c
new file mode 100644
index 00000000..6c170885
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/timer.c
@@ -0,0 +1,79 @@
+/************************************************************************************//**
+* \file         Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/timer.c
+* \brief        Timer driver source file.
+* \ingroup      Prog_ARMCM7_STM32H7_Nucleo_H743ZI_Keil
+* \internal
+*----------------------------------------------------------------------------------------
+*                          C O P Y R I G H T
+*----------------------------------------------------------------------------------------
+*   Copyright (c) 2020  by Feaser    http://www.feaser.com    All rights reserved
+*
+*----------------------------------------------------------------------------------------
+*                            L I C E N S E
+*----------------------------------------------------------------------------------------
+* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as published by the Free
+* Software Foundation, either version 3 of the License, or (at your option) any later
+* version.
+*
+* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+* PURPOSE. See the GNU General Public License for more details.
+*
+* You have received a copy of the GNU General Public License along with OpenBLT. It
+* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
+*
+* \endinternal
+****************************************************************************************/
+
+/****************************************************************************************
+* Include files
+****************************************************************************************/
+#include "header.h"                                    /* generic header               */
+
+
+/************************************************************************************//**
+** \brief     Initializes the timer.
+** \return    none.
+**
+****************************************************************************************/
+void TimerInit(void)
+{
+  /* Update the  system core clock variable. */
+  SystemCoreClockUpdate();
+  /* Configure the Systick interrupt time for 1 millisecond. */
+  HAL_SYSTICK_Config(SystemCoreClock/1000);
+  /* Configure the Systick. */
+  HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
+  /* SysTick_IRQn interrupt configuration. */
+  HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0);
+} /*** end of TimerInit ***/
+
+
+/************************************************************************************//**
+** \brief     Obtains the counter value of the millisecond timer.
+** \return    Current value of the millisecond timer.
+**
+****************************************************************************************/
+unsigned long TimerGet(void)
+{
+  /* Read and return the tick counter value. */
+  return HAL_GetTick();
+} /*** end of TimerGet ***/
+
+
+/************************************************************************************//**
+** \brief     Interrupt service routine of the timer.
+** \return    none.
+**
+****************************************************************************************/
+void SysTick_Handler(void)
+{
+  /* Increment the tick counter. */
+  HAL_IncTick();
+  /* Invoke the system tick handler. */
+  HAL_SYSTICK_IRQHandler();
+} /*** end of TimerISRHandler ***/
+
+
+/*********************************** end of timer.c ************************************/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/timer.h b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/timer.h
new file mode 100644
index 00000000..d92ab833
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/timer.h
@@ -0,0 +1,38 @@
+/************************************************************************************//**
+* \file         Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/Prog/timer.h
+* \brief        Timer driver header file.
+* \ingroup      Prog_ARMCM7_STM32H7_Nucleo_H743ZI_Keil
+* \internal
+*----------------------------------------------------------------------------------------
+*                          C O P Y R I G H T
+*----------------------------------------------------------------------------------------
+*   Copyright (c) 2020  by Feaser    http://www.feaser.com    All rights reserved
+*
+*----------------------------------------------------------------------------------------
+*                            L I C E N S E
+*----------------------------------------------------------------------------------------
+* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as published by the Free
+* Software Foundation, either version 3 of the License, or (at your option) any later
+* version.
+*
+* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+* PURPOSE. See the GNU General Public License for more details.
+*
+* You have received a copy of the GNU General Public License along with OpenBLT. It
+* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
+*
+* \endinternal
+****************************************************************************************/
+#ifndef TIMER_H
+#define TIMER_H
+
+/****************************************************************************************
+* Function prototypes
+****************************************************************************************/
+void          TimerInit(void);
+unsigned long TimerGet(void);
+
+#endif /* TIMER_H */
+/*********************************** end of timer.h ************************************/
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/demo.dox b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/demo.dox
new file mode 100644
index 00000000..e18d6149
--- /dev/null
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_Keil/demo.dox
@@ -0,0 +1,9 @@
+/**
+\defgroup   ARMCM7_STM32H7_Nucleo_H743ZI_Keil Demo for Nucleo-H743ZI/Keil
+\ingroup    Demos
+\brief      Preconfigured programs for the Nucleo-H743ZI board and the Keil MDK for ARM IDE.
+\details    For detailed getting started instructions, refer to:
+            https://www.feaser.com/openblt/doku.php?id=manual:demos:nucleo_h743zi_keil.
+*/
+
+
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_TrueStudio/Boot/.settings/language.settings.xml b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_TrueStudio/Boot/.settings/language.settings.xml
index 81fdf805..23de469e 100644
--- a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_TrueStudio/Boot/.settings/language.settings.xml
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_TrueStudio/Boot/.settings/language.settings.xml
@@ -4,7 +4,7 @@
 		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
 			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
 			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
-			<provider class="com.atollic.truestudio.mbs.GCCSpecsDetectorAtollicArm" console="false" env-hash="286472261513826467" id="com.atollic.truestudio.mbs.provider" keep-relative-paths="false" name="Atollic ARM Tools Language Settings" parameter="${COMMAND} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+			<provider class="com.atollic.truestudio.mbs.GCCSpecsDetectorAtollicArm" console="false" env-hash="131041188512206230" id="com.atollic.truestudio.mbs.provider" keep-relative-paths="false" name="Atollic ARM Tools Language Settings" parameter="${COMMAND} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
 				<language-scope id="org.eclipse.cdt.core.gcc"/>
 				<language-scope id="org.eclipse.cdt.core.g++"/>
 			</provider>
@@ -14,7 +14,7 @@
 		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
 			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
 			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
-			<provider class="com.atollic.truestudio.mbs.GCCSpecsDetectorAtollicArm" console="false" env-hash="286472261513826467" id="com.atollic.truestudio.mbs.provider" keep-relative-paths="false" name="Atollic ARM Tools Language Settings" parameter="${COMMAND} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+			<provider class="com.atollic.truestudio.mbs.GCCSpecsDetectorAtollicArm" console="false" env-hash="131041188512206230" id="com.atollic.truestudio.mbs.provider" keep-relative-paths="false" name="Atollic ARM Tools Language Settings" parameter="${COMMAND} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
 				<language-scope id="org.eclipse.cdt.core.gcc"/>
 				<language-scope id="org.eclipse.cdt.core.g++"/>
 			</provider>
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_TrueStudio/Boot/Debug/openblt_stm32h743.elf b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_TrueStudio/Boot/Debug/openblt_stm32h743.elf
index ddb20d07..57500ef8 100644
Binary files a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_TrueStudio/Boot/Debug/openblt_stm32h743.elf and b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_TrueStudio/Boot/Debug/openblt_stm32h743.elf differ
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_TrueStudio/Boot/Debug/openblt_stm32h743.srec b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_TrueStudio/Boot/Debug/openblt_stm32h743.srec
index b64b9a2c..ac32875b 100644
--- a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_TrueStudio/Boot/Debug/openblt_stm32h743.srec
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_TrueStudio/Boot/Debug/openblt_stm32h743.srec
@@ -1,50 +1,50 @@
 S01900006F70656E626C745F73746D3332683734332E73726563F9
-S3150800000000000220F157000841580008415800082E
-S3150800001041580008415800084158000800000000EF
-S315080000200000000000000000000000004158000821
-S31508000030415800080000000041580008790B0008E4
-S31508000040415800084158000841580008415800081E
-S31508000050415800084158000841580008415800080E
-S3150800006041580008415800084158000841580008FE
-S3150800007041580008415800084158000841580008EE
-S3150800008041580008415800084158000841580008DE
-S3150800009041580008415800084158000841580008CE
-S315080000A041580008415800084158000841580008BE
-S315080000B041580008415800084158000841580008AE
-S315080000C0415800084158000841580008415800089E
-S315080000D0415800084158000841580008415800088E
-S315080000E0415800084158000800000000415800081F
-S315080000F0415800084158000841580008415800086E
-S31508000100415800084158000841580008415800085D
-S31508000110415800084158000841580008415800084D
-S31508000120415800084158000841580008415800083D
-S31508000130415800084158000841580008415800082D
+S31508000000000002200D5800085D5800085D580008D9
+S315080000105D5800085D5800085D580008000000009B
+S315080000200000000000000000000000005D58000805
+S315080000305D580008000000005D5800088D0B000898
+S315080000405D5800085D5800085D5800085D580008AE
+S315080000505D5800085D5800085D5800085D5800089E
+S315080000605D5800085D5800085D5800085D5800088E
+S315080000705D5800085D5800085D5800085D5800087E
+S315080000805D5800085D5800085D5800085D5800086E
+S315080000905D5800085D5800085D5800085D5800085E
+S315080000A05D5800085D5800085D5800085D5800084E
+S315080000B05D5800085D5800085D5800085D5800083E
+S315080000C05D5800085D5800085D5800085D5800082E
+S315080000D05D5800085D5800085D5800085D5800081E
+S315080000E05D5800085D580008000000005D580008CB
+S315080000F05D5800085D5800085D5800085D580008FE
+S315080001005D5800085D5800085D5800085D580008ED
+S315080001105D5800085D5800085D5800085D580008DD
+S315080001205D5800085D5800085D5800085D580008CD
+S315080001305D5800085D5800085D5800085D580008BD
 S3150800014000000000000000000000000000000000A1
-S31508000150415800084158000841580008415800080D
-S3150800016041580008415800084158000841580008FD
-S31508000170415800084158000841580008000000008E
-S3150800018041580008415800084158000841580008DD
-S3150800019041580008415800084158000841580008CD
-S315080001A041580008415800084158000841580008BD
-S315080001B041580008415800084158000841580008AD
-S315080001C0415800084158000841580008415800089D
-S315080001D0415800084158000841580008415800088D
-S315080001E0415800084158000841580008415800087D
-S315080001F0415800084158000841580008415800086D
-S31508000200415800084158000841580008415800085C
-S31508000210415800084158000841580008415800084C
-S3150800022041580008415800084158000800000000DD
-S3150800023041580008415800080000000041580008CD
-S31508000240415800084158000841580008415800081C
-S31508000250415800084158000841580008415800080C
-S3150800026041580008415800084158000841580008FC
-S31508000270415800084158000841580008000000008D
-S31508000280415800084158000841580008000000007D
-S30D080002900000000041580008B7
+S315080001505D5800085D5800085D5800085D5800089D
+S315080001605D5800085D5800085D5800085D5800088D
+S315080001705D5800085D5800085D580008000000003A
+S315080001805D5800085D5800085D5800085D5800086D
+S315080001905D5800085D5800085D5800085D5800085D
+S315080001A05D5800085D5800085D5800085D5800084D
+S315080001B05D5800085D5800085D5800085D5800083D
+S315080001C05D5800085D5800085D5800085D5800082D
+S315080001D05D5800085D5800085D5800085D5800081D
+S315080001E05D5800085D5800085D5800085D5800080D
+S315080001F05D5800085D5800085D5800085D580008FD
+S315080002005D5800085D5800085D5800085D580008EC
+S315080002105D5800085D5800085D5800085D580008DC
+S315080002205D5800085D5800085D5800080000000089
+S315080002305D5800085D580008000000005D58000879
+S315080002405D5800085D5800085D5800085D580008AC
+S315080002505D5800085D5800085D5800085D5800089C
+S315080002605D5800085D5800085D5800085D5800088C
+S315080002705D5800085D5800085D5800080000000039
+S315080002805D5800085D5800085D5800080000000029
+S30D08000290000000005D5800089B
 S3150800029810B5054C237833B9044B13B10448AFF3AA
 S315080002A800800123237010BDC40000200000000050
-S315080002B82C5D000808B5034B1BB103490348AFF387
-S315080002C8008008BD00000000C80000202C5D00085A
+S315080002B8485D000808B5034B1BB103490348AFF36B
+S315080002C8008008BD00000000C8000020485D00083E
 S315080002D872B6704762B67047F0B5184D2C6D24F0A3
 S315080002E840542C65002401E00134E4B2112C23D8CB
 S315080002F8134D15F8146005EB44056F78F51905FBD9
@@ -52,1498 +52,1500 @@ S3150800030800054FF4FA5EBEFBF5FE05FB0EF5B5F5DE
 S31508000318FA5FE9D135463D4405FB000E4FF4FA5518
 S31508000328B5FBFEF50D80013DADB2B5F5007FDBD214
 S3150800033816701F700120F0BD0020F0BD0044025859
-S31508000348B85D000870B58AB00022ADF826208DF889
-S3150800035825200AAB03F8042D0DF125020DF1260117
-S315080003684FF4FA70FFF7B8FF00283CD0204C214B11
+S31508000348D45D000870B58CB00022ADF82E208DF863
+S315080003582D200CAB03F8042D0DF12D020DF12E01FD
+S315080003684FF4FA70FFF7B8FF002842D0234C244B05
 S3150800037823600025A560E560012626746574A574C2
-S31508000388BDF826306361A6619DF82530E3619DF8BE
-S31508000398243023626662A662E66226636563A663FC
-S315080003A8E563256404236364A564E36426656365D5
-S315080003B8A565E66525666566A366204601F03CFBE5
-S315080003C80195029503960723049340F267630593FC
-S315080003D80693079501A9204601F078FC204601F006
-S315080003E8B8FC0AB070BDB821034800F0A9FDBDE7FE
-S315080003F8E000002000A00040905D000810B58AB013
-S3150800040840F2E173019300230293039309040491CC
-S3150800041805930693079308935223099301230246E3
-S3150800042801A90E4801F0AFFC08B10AB010BD0121B8
-S315080004380A4801F0DEFC0028F7D100F08DFB00F130
-S3150800044832040121054801F0DCFD0028EDD000F052
-S3150800045881FE00F081FB8442F3D2E6E7E000002043
-S3150800046830B58BB004460D460021104801F0A2FDB0
-S3150800047860B90120B0B940F26763009A9A420CD075
-S31508000488002080B19DF80E302B700CE023466A4692
-S315080004980021064801F0C0FCECE7019B002BF0D1CF
-S315080004A80120EEE700200BB030BD00BFE0000020B9
-S315080004B808B5FFF70DFF08BD10B500F057FA00B9E3
-S315080004C810BD01F047F80028FAD000F0EDFD00F05D
-S315080004D81BFB01F093F800F04DFA054B0340054A5B
-S315080004E8936000F047FA4468FFF7F4FEA047E7E789
-S315080004F880FFFF1F00ED00E070B508E0461C4D1CA4
-S315080005080B78037000F026FE304629462246531E0D
-S315080005189CB2002AF2D170BD38B50546002401E020
-S315080005280134E4B20E2C12D800F014FE04EB44028F
-S315080005389300084AD358AB42F2D804EB4402910018
-S31508000548044A0A44526813449D42E9D200E0FF244B
-S31508000558204638BDDC5D000810B5C1F309031BB990
-S3150800056801241CB9204610BD0024FAE703689942FD
-S31508000578F8D040F8041B4FF48062FFF7BDFFF1E797
-S315080005882DE9F04107460068FFF7C6FFFF2807D0A0
-S315080005984FF00108B8F1000F05D14046BDE8F081D3
-S315080005A84FF00008F6E701F035FD002605E04FF0A4
-S315080005B80008B8F1000F1DD001361F2E1AD83D685D
-S315080005C8740125443C44043400F0C4FD22462946F7
-S315080005D8012001F0E9FD58B900231F2BE9D8E95C89
-S315080005E8C9B2E25CD2B29142E1D10133DBB2F4E797
-S315080005F84FF0000801F03CFDCFE7000070B50E4645
-S315080006080E4B984208D004460D4B994207D0FFF77F
-S31508000618B7FF70B1254604E00A4D2C4601E0074DA0
-S315080006282C4625B131462046FFF796FF18B12846CD
-S3150800063870BD0025F5E70025F9E700BF8405002009
-S3150800064800000208800100202DE9F84306460C46FA
-S3150800065817461D46DFF88C8001EA08080368B3F1D7
-S31508000668FF3F0AD04FF00109B9F1010F0ED0B9F1D1
-S31508000678010F18D04846BDE8F8834146FFF76CFFD6
-S3150800068881460028F0D04FF00109EDE73368984510
-S31508000698EDD041463046FFF7B1FF06460028E6D1B9
-S315080006A84FF00009E3E73368E41A3444043405E0F4
-S315080006B817F8013B04F8013B013DDBD000F04AFD81
-S315080006C8331DE31AB3F5806FF2D308F58061304617
-S315080006D8FFF794FF064608B1041DE9E74FF000093D
-S315080006E8C8E700BF00FCFFFF70B586B004460D4694
-S315080006F800230093884205D801262EB946B9304604
-S3150800070806B070BD0026F8E70E2DF7D90026F5E7DE
-S3150800071801F080FCAC4227D800F01CFD154963009F
-S3150800072823449A008B188A585B68002B18BFB2F1C5
-S31508000738FF3F18D000230193202305930A46630038
-S315080007481819810008461144497A02910244137A15
-S31508000758039301230493694601A801F0EFFD30B914
-S315080007680134E4B2D6E7002601F082FCC7E7002682
-S31508000778FAE700BFDC5D00084FF0FF33024A136052
-S31508000788024A1360704700BF8001002084050020D4
-S31508000798F8B505460E4617464A1E184B1B1A9A42BE
-S315080007A806D80124012C05D0012C12D02046F8BD04
-S315080007B80024F7E72846FFF7AFFEFF2807D0701989
-S315080007C80138FFF7A9FEFF28EED10024ECE700243C
-S315080007D8EAE70B4B2B400B4A934207D033463A4677
-S315080007E829460948FFF730FF0446DFE733463A4605
-S315080007F829460648FFF728FF0446D7E7FFFF1F08DC
-S3150800080800FCFFFF00000208800100208405002084
-S31508000818F8B506460D464A1E114B1B1A9A4208D8C1
-S315080008280124012C07D0FF210F46012C12D020469F
-S31508000838F8BD0024F5E73046FFF76EFE0746A81907
-S315080008480138FFF769FE0146FF2818BFFF2FECD1CC
-S315080008580024EAE73846FFF747FF0446E7E700BFFC
-S31508000868FFFF1F08104B1B68B3F1FF3F1AD000B5EE
-S3150800087883B00D4A536891680B44D1680B441169D3
-S315080008880B4451690B4491690B44D26913445B4282
-S3150800089802AA42F8043D04210448FFF779FF03B089
-S315080008A85DF804FB012070478405002098020208B9
-S315080008B80D4B1B680D4A126813440D4A12681344F7
-S315080008C80C4A126813440C4A126813440B4A1268F5
-S315080008D813440B4A126813440A4A1268D34201D0D1
-S315080008E8002070470120704700000208040002082B
-S315080008F8080002080C000208100002081400020882
-S31508000908180002089802020810B50E4B1B68B3F1C6
-S31508000918FF3F06D00B48FFF733FE044610B1012403
-S3150800092800E00124012C01D0204610BD064B1B68A7
-S31508000938B3F1FF3FF8D00448FFF722FE0028F3D1A9
-S315080009480446F1E784050020800100200048704726
-S315080009580000020808B5FFF70FFF08BD08B5FFF73E
-S3150800096817FF08BD08B5FFF753FF08BD08B5FFF719
-S315080009789FFF08BD08B5FFF7E9FF08BD08B5FFF7EB
-S3150800098871FF034608B9184608BDFFF7BDFF0346B9
-S31508000998F9E70000074BDB6913F0200F06D001239F
-S315080009A833B1044B5B6A0370012070470023F7E7ED
-S315080009B8002070470048004010B50B4B986200F0BD
-S315080009C8CBF800F10A0407E0012363B900F0C2FB7B
-S315080009D800F0C2F8844206D3034BDB6913F0800F94
-S315080009E8F2D10023F1E710BD0048004010B588B0E1
-S315080009F8002300934FF461420192029303930493F0
-S31508000A080C22059206930793054C6946204603F07F
-S31508000A188BF9236843F00103236008B010BD00BFB3
-S31508000A280048004070B506460D46402904D82846B1
-S31508000A38FFF7C2FF00240BE08221074800F080FA7E
-S31508000A48F5E700F087FB305DFFF7B6FF0134A4B27F
-S31508000A58ABB29C42F5D370BD905E000870B5254BC5
-S31508000A681C78BCB92448FFF795FF012801D0204611
-S31508000A7870BD214B1B78013BDBB23F2BF7D800F042
-S31508000A886BF81E4B186000221D4B1A700122194B71
-S31508000A981A70ECE706460D46194B1B7801331648BB
-S31508000AA81844FFF777FF044601280AD000F054F8DF
-S31508000AB8124B1B686433984219D900240D4B1C70D5
-S31508000AC8D5E70F4B1A780132D2B21A700A4B1B783F
-S31508000AD89A4201D00024CAE70A493046FFF70CFDB6
-S31508000AE80022044B1A70064B1B782B70BFE70024AC
-S31508000AF8BDE700BFC909002088090020CC090020E5
-S31508000B08CA090020890900200022014B1A6070478B
-S31508000B1810E000E008B5FFF7F7FF054B054A5A60ED
-S31508000B2800229A6005211960034B1A6008BD00BFA8
-S31508000B3810E000E0FF520700D0090020044B1B68AC
-S31508000B4813F4803F03D0034A1368013313607047D0
-S31508000B5810E000E0D009002008B5FFF7EFFF014BC9
-S31508000B68186808BDD009002008B5FFF7F5FF08BDC5
-S31508000B7870470000094B03F11801002232B19A7434
-S31508000B8800225A61054A064B1A6070479A745961D9
-S31508000B98183318310132D2B2F0E700BF140A002020
-S31508000BA8440A00200A4B1B6883B110B45C69084ADA
-S31508000BB8146019749860D86000225A74186001394C
-S31508000BC808445860987C5DF8044B7047FF207047C6
-S31508000BD8440A002038B504460D46012804D94FF4BE
-S31508000BE8E171124800F0ACF962002244D100104BBA
-S31508000BF80B445A7C1B7C9A4213D00D4B0B44DA687B
-S31508000C0815705A7C01325A74DA680132DA605B6800
-S31508000C189A4208D9064A084651580244D160012022
-S31508000C2838BD002038BD012038BD00BFBC5E0008AD
-S31508000C38140A002008B50146024B1878FFF7CAFFC0
-S31508000C4808BD00BF480A002038B504460D460128E5
-S31508000C5804D94FF4F271134800F072F904EB44030F
-S31508000C68DA00114B13445B7CBBB162002244D10005
-S31508000C780D4B0B449A6812782A705A7C013A5A74B2
-S31508000C889A6801329A605B689A4208D9064A084601
-S31508000C98515802449160012038BD002038BD012012
-S31508000CA838BD00BFBC5E0008140A002008B5014616
-S31508000CB8024B1878FFF7C8FF08BD00BF8C0A00204A
-S31508000CC810B50446012804D94FF40171044800F008
-S31508000CD837F904EB4404E200024B1344587C10BD70
-S31508000CE8BC5E0008140A002038B5FFF743FF1B4C02
-S31508000CF84021601CFFF756FF2070194D4021681CDB
-S31508000D08FFF750FF28702378FF2B1DD0FF281BD02C
-S31508000D18144C00221449204603F02AFE134920469B
-S31508000D2803F04FFE012000F030FC204603F050FE89
-S31508000D3802F0E2F9D4F8C00202F00AF800F02CF939
-S31508000D48B0F5FA6F05D338BD8521094800F0F8F8DB
-S31508000D58DEE74FF4FA6000F019F9F4E7480A0020CC
-S31508000D688C0A0020D00A00207400002010000020F9
-S31508000D78BC5E000810B5064CD4F8C00202F006F8A6
-S31508000D88204603F00CFE002000F0FFFB10BD00BF54
-S31508000D98D00A002070B506460D463F290AD82846C7
-S31508000DA8FFF748FF012803D0BF210E4800F0C8F80E
-S31508000DB8002406E0BB210B4800F0C2F8EFE701342F
-S31508000DC8A4B2ABB29C420BD200F0C4F9305DFFF76F
-S31508000DD831FF0128F3D0C821024800F0B1F8EEE740
-S31508000DE870BD00BFBC5E000870B506460D461F4BB1
-S31508000DF8D3F8C00201F038FD1D4B1C789CB91D4874
-S31508000E08FFF754FF012801D0204670BD194B1B78FF
-S31508000E18013BDBB23E2BF7D80122154B1A7000228C
-S31508000E28154B1A70F0E7144B1B7801331148184410
-S31508000E38FFF73CFF0446012801D00024E4E70E4BDF
-S31508000E481A780132D2B21A700A4B1B789A4201D024
-S31508000E580024D9E709493046FFF74EFB0022044B20
-S31508000E681A70054B1B782B70CEE700BFD00A0020F6
-S31508000E78D40D0020940D0020D50D0020950D0020D6
-S31508000E8830B583B0144B1878FFF71AFF08B3054630
-S31508000E98402800D94025002405E09DF807200F4B77
-S31508000EA81A550134E4B2A5420DD90DF107010A4BCA
-S31508000EB81878FFF7C9FE0128EFD04FF4A47108483F
-S31508000EC800F03EF8E9E7ABB2044A8121054804F088
-S31508000ED858FE03B030BD00BF480A0020D4090020D8
-S31508000EE8BC5E0008D00A002070B5044604F01CFD54
-S31508000EF8064621460F4804F0F2FD85B2002401E0B3
-S31508000F080134A4B2AC420CD2315D0B4B1878FFF70A
-S31508000F1861FE0128F4D04FF4B571084800F010F8BE
-S31508000F28EEE704F001FD402302460121014804F0DA
-S31508000F3830FE70BDD00A00208C0A0020BC5E00086E
-S31508000F4808B500F007F9FCE708B500F0F7F8012836
-S31508000F5803D00B4B1B78012B00D008BDFFF7FCFD0F
-S31508000F68084B1B68084A1268134403F5FA73984233
-S31508000F78F3D30022024B1A70FFF79EFAEDE700BF7B
-S31508000F88DC0D0020D80D0020E00D0020014B18606C
-S31508000F98704700BFD80D0020014B1868704700BF7E
-S31508000FA8D80D002008B5054B1B78012B00D008BDC5
-S31508000FB8FFF7D2FD024B1860F9E700BFDC0D0020E9
-S31508000FC8E00D002008B50122034B1A70FFF7EAFF67
-S31508000FD8FFF7BAFF08BD00BFDC0D002008B5FFF70C
-S31508000FE867FA00F0B3F8FFF795FDFFF7B3FC00F0D2
-S31508000FF80DF8FFF7E7FF08BD08B500F0ABF8FFF7EF
-S315080010089DFD00F017F8FFF79FFF08BD10B500F023
-S315080010180FFAFFF797F9064C01232370FFF7E6FC4A
-S3150800102800232370FFF760FE0223237010BD00BF5C
-S315080010380000002000B583B00DF107011848FFF736
-S315080010480FFA012810D00DF107011548FFF706FD1C
-S31508001058012812D00DF107011148FFF7C5FE01282E
-S3150800106814D003B05DF804FB01220E4B1A709DF8E4
-S3150800107807100B4800F0FCF9E5E70022094B1A703F
-S315080010889DF80710064800F0F3F9E3E70222054B36
-S315080010981A709DF80710024800F0EAF9E1E700BF60
-S315080010A8E40D00200000002008B5FFF763FE08BD20
-S315080010B838B504460D460E4B1B78012B09D00C4B48
-S315080010C81B7853B10A4B1B78022B0BD000F0C8F9D2
-S315080010D838BDC9B2FFF792F9F1E7E9B22046FFF73A
-S315080010E8A1FCEFE7E9B22046FFF754FEEEE700BF9A
-S315080010F800000020074B1B78022B05D0032B05D0D0
-S31508001108012B05D0402070473F20704700207047C4
-S315080011180820704700000020074B1B78022B05D0D3
-S31508001128032B05D0012B05D0402070473F20704778
-S3150800113800207047082070470000002008B500F016
-S3150800114885F9034600B10123184608BD08B500F01D
-S3150800115813FA08BD08B500F014FA08BD0022014BB9
-S315080011685A707047240E0020034BFE22DA70187155
-S315080011780222A3F844207047240E002010B5054C17
-S3150800118800232370FFF7EAFFFF23E3700123A4F87F
-S31508001198443010BD240E0020064BFF22DA700022C8
-S315080011A81A71597859719A71DA711A720622A3F85E
-S315080011B844207047240E002008B50020FFF7D4FF06
-S315080011C808BD0000074BFF22DA70074A9A64002216
-S315080011D81A715A719A710722C3F807200822A3F8C8
-S315080011E844207047240E0020E45E0008044BFF22C2
-S315080011F8DA7042689A640122A3F84420704700BF4F
-S31508001208240E002008B53120FFF7AEFF08BD000000
-S3150800121838B5084CFF23E370002525716571FFF77B
-S3150800122869FFA071E571257265720723A4F8443031
-S3150800123838BD00BF240E002038B5FFF78FFF0E4CC7
-S3150800124801252570FF23E37010232371002363719A
-S31508001258FFF750FFA071FFF75FFFE071FFF75CFF2C
-S31508001268C0F3072020726572A5720823A4F84430D3
-S31508001278FFF770FB38BD00BF240E002038B50546B9
-S315080012884478FFF737FF0138844210DC0A4C6A783D
-S31508001298A16C201DFFF730F9FF23E3706A78A36C69
-S315080012A81344A3646B780133A4F8443038BD22206C
-S315080012B8FFF75AFF38BD00BF240E002038B504468C
-S315080012C84578FFF717FF0138854211DC61680A4D32
-S315080012D8A9646278281DFFF70FF9FF23EB70627877
-S315080012E8AB6C1344AB6463780133A5F8443038BD56
-S315080012F82220FFF739FF38BD240E0020F8B5054629
-S315080013081746002406E015F8013B1C44E4B2FFF72B
-S3150800131821FF31464E1E0029F5D13C600120F8BD53
-S3150800132810B5084CFF23E370E21D4168A06CFFF76F
-S31508001338E5FF207100236371A3710823A4F84430DC
-S3150800134810BD00BF240E002038B505460D4B9C6C11
-S31508001358FFF7D0FE6A1C411E2046FFF7FFFA60B168
-S31508001368084CFF23E370FFF7C5FE0138A36C034456
-S31508001378A3640123A4F8443038BD3120FFF7F4FEEE
-S3150800138838BD00BF240E002038B504464578FFF757
-S31508001398B1FE023885420EDC114BFF22DA700122B3
-S315080013A8A3F84420617851B9FFF7E8FA90B93120D3
-S315080013B8FFF7DAFE38BD2220FFF7D6FE38BDA21C95
-S315080013C8074B986CFFF7CAFA28B16178044A936CF8
-S315080013D80B44936438BD3120FFF7C6FE38BD00BFFD
-S315080013E8240E002008B54168074B986CFFF7BAFA2F
-S315080013F830B1054BFF22DA700122A3F8442008BD54
-S315080014083120FFF7B1FE08BD240E002008B5FFF706
-S3150800141853F8034BFF22DA700122A3F8442008BDCB
-S31508001428240E002008B589B2FFF742FE08BD000061
-S31508001438054B00221A709A6483F84320A3F84420BF
-S315080014489A705A70704700BF240E0020034B1B7809
-S315080014580BB1012070470020704700BF240E0020FA
-S315080014680022024B83F84320704700BF240E002051
-S3150800147808B50378FF2B04D0354A1278012A14D008
-S3150800148808BDFFF7D9FE324B93F84330012B5AD0E3
-S315080014982F4BB3F944100029F2DD1846012380F8CA
-S315080014A843300330FFF7BEFFEAE7C93B352B46D87A
-S315080014B8DFE803F03345454245453F363C3945455F
-S315080014C845454545454545454545454545454545B6
-S315080014D84545454545454545454545454545241EEE
-S315080014E81B2145454527452A2D30FFF7C7FECAE77C
-S315080014F8FFF7E4FEC7E7FFF779FEC4E7FFF710FF33
-S31508001508C1E7FFF75FFEBEE7FFF756FEBBE7FFF743
-S3150800151843FEB8E7FFF732FEB5E7FFF715FFB2E770
-S31508001528FFF732FFAFE7FFF773FEACE7FFF75AFF9F
-S31508001538A9E7FFF76BFFA6E7FFF764FEA3E72020F6
-S31508001548FFF712FE9FE71020FFF70EFEA0E700BF81
-S31508001558240E002008B5074B1B6913F4005F03D057
-S3150800156801231BB1002008BD0023FAE700F03EF866
-S31508001578012008BD0008025808B5642000F008F8DC
-S3150800158808BD08B500F00AF808BD704770477047E7
-S31508001598014B1880704700BF700E002008B5FFF78A
-S315080015A8DBFA0E4B1B6898420FD30D4B1B786BB9A9
-S315080015B801220B4B1A7080220A4B9A61FFF7CCFA64
-S315080015C8094B1B881844054B186008BD0022044BB4
-S315080015D81A704FF40002034B9A61EFE7740E002065
-S315080015E8720E002000040258700E00204FF4000204
-S315080015F8014B9A61704700BF0004025810B5164B94
-S315080016086FF00042DA670024DC674FF0FF32C3F850
-S315080016188020C3F88040C3F88420C3F88440C3F800
-S315080016288820C3F88840C3F88C20C3F88C40C3F8D0
-S315080016389020C3F89040C3F89420C3F89440C3F8A0
-S315080016489820C3F89840C3F89C20C3F89C4004F037
-S315080016587BF8204610BD00BF00440258104B1B7883
-S315080016680BB90120704710B504464FF47A70B0FBE1
-S31508001678F3F30C4A1068B0FBF3F000F09BF868B96E
-S315080016880F2C01D9012010BD002221464FF0FF304A
-S3150800169800F060F8044B1C60002010BD012010BD46
-S315080016A801000020080000200400002010B50320CF
-S315080016B800F03EF801F028FD0F498B69C3F30323B0
-S315080016C80E4AD35C03F01F03D8408B6903F00F0357
-S315080016D8D35C03F01F0320FA03F3094A1360094B86
-S315080016E818600020FFF7BAFF10B10124204610BD84
-S315080016F8044603F079FFF9E7004402583C5F0008FE
-S315080017080C0000200800002038B50446FFF72CFA1C
-S315080017180546B4F1FF3F02D0044B1B781C44FFF77B
-S3150800172823FA401B8442FAD838BD00BF01000020BE
-S315080017380649CB6823F4E0631B041B0C000200F47B
-S31508001748E0600343024A1A43CA60704700ED00E0A6
-S315080017580000FA0530B4144BDB68C3F30223C3F15F
-S315080017680704042C28BF04241D1D062D13D9033B82
-S31508001778012505FA04F4013C2140994005FA03F3CA
-S31508001788013B13401943002807DB0901C9B2074B77
-S31508001798195430BC70470023EAE700F00F00090126
-S315080017A8C9B2034B1954F4E700ED00E000E400E081
-S315080017B814ED00E00138B0F1807F0AD2064B586074
-S315080017C8F021064A82F823100020986007221A603A
-S315080017D870470120704700BF10E000E000ED00E008
-S315080017E830B4436B0468D4F884106F4A114041EA50
-S315080017F88301C4F884100468D4F8841021F47F019E
-S31508001808856B41EA0541C4F88410816B0B4404686A
-S31508001818D4F88810114041EA8301C4F8881004688E
-S31508001828D4F8881021F4FE01C56B41EA0541C4F8CD
-S315080018388810C16B03EB41030468D4F8A010114063
-S3150800184841EA8301C4F8A0100468D4F8A01021F46A
-S31508001858FE01056C41EA0541C4F8A010046C416C08
-S3150800186801FB04340368D3F8B010114041EA840137
-S31508001878C3F8B0100368D3F8B01021F4FE01856CDC
-S3150800188841EA0541C3F8B010836CC16C01FB0344F7
-S315080018980368D3F8AC10114041EA8401C3F8AC10C8
-S315080018A8036D416D01FB03430468D4F8F010114039
-S315080018B841EA8301C4F8F0100468D4F8F01021F45A
-S315080018C87C11856D41EA0541C4F8F010816D03EB7A
-S315080018D841030468D4F8C0100A4042EA8303C4F8EE
-S315080018E8C0300268D2F8C03023F47C13C16D43EACD
-S315080018F80143C2F8C0300268D2F8C03023F07C53DE
-S31508001908016E43EA0163C2F8C030426B274B1344A1
-S315080019189B00C366826B03EB82020267C16B02EB0C
-S31508001928C1024267046C416C01FB04F102EB8102B7
-S315080019388267846CC16C01FB04F102EB8102C26701
-S31508001948046D416D01FB04F102EB8102C0F88020A9
-S31508001958816D02EBC102C0F88420C46D856E05FB53
-S3150800196804F402EB8402C0F88820016E01FB05F135
-S3150800197802EB8102C0F890200D498A420DD9D0F8A9
-S315080019889C3043F02003C0F89C30032380F8983035
-S31508001998012007E0002243F8042BD0F89020934250
-S315080019A8F8D3002030BC70470300FFFF002B001057
-S315080019B8FCD30040F0B44C68E4B90E698C68264339
-S315080019C80C6846EA84460D6ACC6944EA05648D695A
-S315080019D82C434D692C43CD682C43D0F88470806E0F
-S315080019E803FB00F307EB830547F823606C600835AB
-S315080019F8002015E00C698E6826430C68264346F0D5
-S31508001A088046E0E71418E678A3781B0443EA0663D9
-S31508001A18647843EA0423145C234345F8043B0430FA
-S31508001A28CB89034CE35C9842ECD3F0BC704700BF03
-S31508001A38EC5E00087047000030B595B004464C22A5
-S31508001A48A04901A804F062F9002C00F0388123683F
-S31508001A589D4A934220D094F898300BB3226893692C
-S31508001A6823F010039361FFF77FF8054623689A6900
-S31508001A7812F0080F1AD0FFF777F8401B0A28F5D98D
-S31508001A88D4F89C3043F00103C4F89C30032384F847
-S31508001A989830012015B030BD03F580736360DAE726
-S31508001AA884F899302046FFF7C5FFD7E79A6942F0C8
-S31508001AB801029A61FFF758F8054623689A6912F0F1
-S31508001AC8010F0FD1FFF750F8401B0A28F5D9D4F8AB
-S31508001AD89C3043F00103C4F89C30032384F89830FB
-S31508001AE80120D7E79A6942F002029A61237C012B02
-S31508001AF840D02268936943F040039361637C012BC5
-S31508001B083ED02268936923F480439361A37C012B12
-S31508001B183CD02268936943F4805393612268936999
-S31508001B2823F44073A1680B4393612268936923F0F1
-S31508001B38A40393612268136923F010031361E36809
-S31508001B48012B29D0002B2CD0022B00F09B80226871
-S31508001B58936943F0800393612268136943F010037D
-S31508001B681361E368032B1CD12268936943F02003A9
-S31508001B78936116E02268936923F040039361BDE7F1
-S31508001B882268936943F480439361BFE7226893699F
-S31508001B9823F480539361C1E72268936943F00403E9
-S31508001BA893612268A369591EE369013B1B0243EA4C
-S31508001BB84163216A01390B436169013943EA0143E3
-S31508001BC8D361A368B3F5407F62D0236E33B1226828
-S31508001BD8D2F8C030616E0B43C2F8C030E36D226E8E
-S31508001BE8D3420DD02168D1F8C83023F00703A26E76
-S31508001BF814A800EB820252F84C2C1343C1F8C830DB
-S31508001C08236C6BB12168D1F8BC3023F00703626CEA
-S31508001C1814A800EB820252F84C2C1343C1F8BC30C6
-S31508001C28A36C73B12168D1F8BC3023F07003E26C59
-S31508001C3814A800EB820252F84C2C43EA0213C1F8A6
-S31508001C48BC30236D73B12168D1F8BC3023F4E06346
-S31508001C58626D14A800EB820252F84C2C43EA022360
-S31508001C68C1F8BC302268184B9A4222D00023C4F81F
-S31508001C789430C4F89C30012384F898302046FFF73E
-S31508001C88AFFD07E72268936943F02003936188E765
-S31508001C982168A36A013BE26A013A43EA0223226BF6
-S31508001CA8013A43EA0213626A013A43EA0243CB60FD
-S31508001CB88BE76268936823F003039360D6E70120ED
-S31508001CC8E8E600BF445D000800A0004090F8983098
-S31508001CD8013BDBB2012B07D9D0F89C3043F002034D
-S31508001CE8C0F89C3001207047CB680A68D2B9072B20
-S31508001CF80ED08A68DB0643EA82730A6943EA024316
-S31508001D084A691343C26E496842F821300020704771
-S31508001D180A69CB691B0243EA02438A69134343F0FB
-S31508001D286053EFE710B40A6942EA4372072B0ED0EC
-S31508001D388C684B6943EA8473006F496800EBC104F1
-S31508001D4840F83120636000205DF8044B70478B69C2
-S31508001D58F2E790F89830DBB2012B07D0D0F89C3020
-S31508001D6843F00403C0F89C3001207047022380F82A
-S31508001D7898300268936923F0010393610023C0F839
-S31508001D889C301846704770B590F89840013CE4B204
-S31508001D98012C07D9D0F89C3043F00203C0F89C30D0
-S31508001DA8012070BD93FAA3F5B5FA85F50668D6F845
-S31508001DB8C040C4F30544A5420BD2D6F8CC4023420A
-S31508001DC80FD0D0F89C3043F04003C0F89C3001206F
-S31508001DD870BDD0F89C3043F02003C0F89C30012031
-S31508001DE870BD93FAA3F3B3FA83F3FFF7E3FD002074
-S31508001DF870BD90F89830DBB2022B07D0D0F89C302B
-S31508001E0843F00803C0F89C30012070470368C3F8FC
-S31508001E18D010002070470000F0B590F89840E4B25A
-S31508001E28022C07D0D0F89C3043F00803C0F89C3041
-S31508001E380120F0BD402937D041295BD0046DA14265
-S31508001E487ED2C46F456D05FB01F504EB85044FF09A
-S31508001E58000E256805F080455560002D78D125685F
-S31508001E68C5F38A451560256805F000559560256807
-S31508001E7805F000451561A588D561656805F47025DE
-S31508001E88D560656805F480155561656805F400151B
-S31508001E989561E57905F07F0515626568ED0F556268
-S31508001EA804F1080500245BE00468D4F8A05015F48A
-S31508001EB8FE0F0FD0D4F8A45015F07F0F12D0D4F81F
-S31508001EC8A440C4F3052E446F456C05FB0EF504EBD8
-S31508001ED88504BEE7D0F89C3043F02003C0F89C3050
-S31508001EE80120F0BDD0F89C3043F48073C0F89C30CC
-S31508001EF80120F0BD0468D4F8B05015F4FE0F0FD0D1
-S31508001F08D4F8B45015F07F0F12D0D4F8B440C4F3FF
-S31508001F18052E846FC56C05FB0EF504EB850498E75A
+S31508000388BDF82E306361A6619DF82D30E3619DF8AE
+S315080003982C3023626662A662E66226636563A663F4
+S315080003A8E563266404236364A564E36425656365D5
+S315080003B8A565E66525666566A366204601F046FBDB
+S315080003C8039504950596069640F26763079308937E
+S315080003D8099503A9204601F083FC009633460222B4
+S315080003E81146204601F0BFFC204601F0D8FC0CB0A7
+S315080003F870BDB821034800F0ADFDB7E7E00000205E
+S3150800040800A00040AC5D000810B58AB040F2E17360
+S315080004180193002302930393090404910593069311
+S3150800042807930893522309930123024601A90E4804
+S3150800043801F0CFFC08B10AB010BD01210A4801F045
+S31508000448FEFC0028F7D100F091FB00F132040121E7
+S31508000458054801F0D5FD0028EDD000F085FE00F02E
+S3150800046885FB8442F3D2E6E7E000002030B58BB07E
+S3150800047804460D464021104801F0CBFD60B901201D
+S31508000488B0B940F26763009A9A420CD0002080B14E
+S315080004989DF80E302B700CE023466A464021064824
+S315080004A801F0E0FCECE7019B002BF0D10120EEE718
+S315080004B800200BB030BD00BFE000002008B5FFF7EC
+S315080004C807FF08BD10B500F055FA00B910BD01F0D0
+S315080004D84BF80028FAD000F0F1FD01F099F800F081
+S315080004E81BFB00F04BFA054B0340054A936000F0E6
+S315080004F845FA4468FFF7EEFEA047E7E780FFFF1FC7
+S3150800050800ED00E070B508E0461C4D1C0B7803703A
+S3150800051800F02AFE304629462246531E9CB2002A77
+S31508000528F2D170BD38B50546002401E00134E4B2BD
+S315080005380E2C12D800F018FE04EB44029300084A61
+S31508000548D358AB42F2D804EB44029100044A0A4451
+S31508000558526813449D42E9D200E0FF24204638BD7C
+S31508000568F85D000810B5C1F309031BB901241CB9C5
+S31508000578204610BD0024FAE703689942F8D040F8E7
+S31508000588041B4FF48062FFF7BDFFF1E72DE9F04140
+S3150800059807460068FFF7C6FFFF2807D04FF001088F
+S315080005A8B8F1000F05D14046BDE8F0814FF00008C4
+S315080005B8F6E701F03DFD002605E04FF00008B8F122
+S315080005C8000F1CD001361F2E19D83D687401254422
+S315080005D83C44043400F0C8FD22462946012001F0AF
+S315080005E8F1FD50B900231F2BE9D8E95CE25CD2B2C9
+S315080005F89142E2D10133DBB2F5E74FF0000801F08A
+S3150800060845FDD0E770B50E460E4B984208D004460D
+S315080006180D4B994207D0FFF7B9FF70B1254604E09C
+S315080006280A4D2C4601E0074D2C4625B13146204691
+S31508000638FFF798FF18B1284670BD0025F5E700258D
+S31508000648F9E700BF840500200000020880010020A1
+S315080006582DE9F84306460C4617461D46DFF88C80F2
+S3150800066801EA08080368B3F1FF3F0AD04FF0010909
+S31508000678B9F1010F0ED0B9F1010F18D04846BDE8F7
+S31508000688F8834146FFF76EFF81460028F0D04FF001
+S315080006980109EDE733689845EDD041463046FFF73E
+S315080006A8B1FF06460028E6D14FF00009E3E73368AC
+S315080006B8E41A3444043405E017F8013B04F8013B0E
+S315080006C8013DDBD000F050FD331DE31AB3F5806F0A
+S315080006D8F2D308F580613046FFF794FF064608B15D
+S315080006E8041DE9E74FF00009C8E700BF00FCFFFF53
+S315080006F870B586B004460D4600230093884205D88F
+S3150800070801262EB946B9304606B070BD0026F8E768
+S315080007180E2DF7D90026F5E701F08AFCAC4227D852
+S3150800072800F022FD1549630023449A008B188A585D
+S315080007385B68002B18BFB2F1FF3F18D0002301935E
+S31508000748202305930A4663001819810008461144B0
+S31508000758497A02910244137A03930123049369465A
+S3150800076801A801F0F9FD30B90134E4B2D6E700264C
+S3150800077801F08CFCC7E70026FAE700BFF85D000819
+S315080007884FF0FF33024A1360024A1360704700BFEE
+S315080007988001002084050020F8B505460E46174650
+S315080007A84A1E184B1B1A9A4206D80124012C05D052
+S315080007B8012C12D02046F8BD0024F7E72846FFF793
+S315080007C8B1FEFF2807D070190138FFF7ABFEFF28DE
+S315080007D8EED10024ECE70024EAE70B4B2B400B4A42
+S315080007E8934207D033463A4629460948FFF730FF69
+S315080007F80446DFE733463A4629460648FFF728FF00
+S315080008080446D7E7FFFF1F0800FCFFFF00000208A1
+S315080008188001002084050020F8B506460D464A1EC4
+S31508000828114B1B1A9A4208D80124012C07D0FF211C
+S315080008380F46012C12D02046F8BD0024F5E73046AD
+S31508000848FFF770FE0746A8190138FFF76BFE014641
+S31508000858FF2818BFFF2FECD10024EAE73846FFF730
+S3150800086847FF0446E7E700BFFFFF1F08104B1B6852
+S31508000878B3F1FF3F1AD000B583B00D4A53689168A3
+S315080008880B44D1680B4411690B4451690B449169AF
+S315080008980B44D26913445B4202AA42F8043D042178
+S315080008A80448FFF779FF03B05DF804FB0120704799
+S315080008B884050020980202080D4B1B680D4A126829
+S315080008C813440D4A126813440C4A126813440C4A16
+S315080008D8126813440B4A126813440B4A12681344E5
+S315080008E80A4A1268D34201D000207047012070478F
+S315080008F80000020804000208080002080C000208A2
+S3150800090810000208140002081800020898020208D3
+S3150800091810B50E4B1B68B3F1FF3F06D00B48FFF71F
+S3150800092835FE044610B1012400E00124012C01D04B
+S31508000938204610BD064B1B68B3F1FF3FF8D00448A4
+S31508000948FFF724FE0028F3D10446F1E784050020C2
+S3150800095880010020004870470000020808B5FFF724
+S315080009680FFF08BD08B5FFF717FF08BD08B5FFF75D
+S3150800097853FF08BD08B5FFF79FFF08BD08B5FFF781
+S31508000988E9FF08BD08B5FFF771FF034608B9184619
+S3150800099808BDFFF7BDFF0346F9E70000074BDB690B
+S315080009A813F0200F06D0012333B1044B5B6A03709A
+S315080009B8012070470023F7E70020704700480040E9
+S315080009C810B50B4B986200F0D1F800F10A0407E05D
+S315080009D8012363B900F0C8FB00F0C8F8844206D3BF
+S315080009E8034BDB6913F0800FF2D10023F1E710BD42
+S315080009F80048004010B588B00D4C236823F0010361
+S31508000A082360002300934FF46142019202930393F3
+S31508000A1804930C220592069307936946204603F029
+S31508000A2891F9236843F00103236008B010BD00BF9D
+S31508000A380048004070B506460D46402904D82846A1
+S31508000A48FFF7BEFF00240BE08421074800F082FA6E
+S31508000A58F5E700F089FB305DFFF7B2FF0134A4B271
+S31508000A68ABB29C42F5D370BDAC5E000870B5254B99
+S31508000A781C78BCB92448FFF791FF012801D0204605
+S31508000A8870BD214B1B78013BDBB23F2BF7D800F032
+S31508000A986DF81E4B186000221D4B1A700122194B5F
+S31508000AA81A70ECE706460D46194B1B7801331648AB
+S31508000AB81844FFF773FF044601280AD000F056F8D1
+S31508000AC8124B1B686433984219D900240D4B1C70C5
+S31508000AD8D5E70F4B1A780132D2B21A700A4B1B782F
+S31508000AE89A4201D00024CAE70A493046FFF70AFDA8
+S31508000AF80022044B1A70064B1B782B70BFE700249C
+S31508000B08BDE700BFC909002088090020CC090020D4
+S31508000B18CA09002089090020024B00221A605A6077
+S31508000B289A60704710E000E008B5FFF7F5FF054B37
+S31508000B38054A5A6000229A6005211960034B1A6013
+S31508000B4808BD00BF10E000E0FF520700D0090020EA
+S31508000B58044B1B6813F4803F03D0034A1368013318
+S31508000B681360704710E000E0D009002008B5FFF7C9
+S31508000B78EFFF014B186808BDD009002008B5FFF734
+S31508000B88F5FF08BD70470000094B03F1180100225C
+S31508000B9832B19A7400225A61054A064B1A607047A0
+S31508000BA89A745961183318310132D2B2F0E700BF86
+S31508000BB8140A0020440A00200A4B1B6883B110B4A3
+S31508000BC85C69084A146019749860D86000225A74D7
+S31508000BD81860013908445860987C5DF8044B7047DA
+S31508000BE8FF207047440A002038B504460D460128F8
+S31508000BF804D94FF4E171124800F0ACF962002244B6
+S31508000C08D100104B0B445A7C1B7C9A4213D00D4BCF
+S31508000C180B44DA6815705A7C01325A74DA6801325C
+S31508000C28DA605B689A4208D9064A08465158024467
+S31508000C38D160012038BD002038BD012038BD00BF6D
+S31508000C48D85E0008140A002008B50146024B187831
+S31508000C58FFF7CAFF08BD00BF480A002038B5044692
+S31508000C680D46012804D94FF4F271134800F072F9B9
+S31508000C7804EB4403DA00114B13445B7CBBB16200F6
+S31508000C882244D1000D4B0B449A6812782A705A7C74
+S31508000C98013A5A749A6801329A605B689A4208D986
+S31508000CA8064A0846515802449160012038BD00207A
+S31508000CB838BD012038BD00BFD85E0008140A0020D8
+S31508000CC808B50146024B1878FFF7C8FF08BD00BFEC
+S31508000CD88C0A002010B50446012804D94FF401717E
+S31508000CE8044800F037F904EB4404E200024B1344C5
+S31508000CF8587C10BDD85E0008140A002038B5FFF7DE
+S31508000D0843FF1B4C4021601CFFF756FF2070194D06
+S31508000D184021681CFFF750FF28702378FF2B1DD049
+S31508000D28FF281BD0144C00221449204603F02EFE37
+S31508000D381349204603F053FE012000F030FC2046F4
+S31508000D4803F054FE02F0E6F9D4F8C00202F00EF8F1
+S31508000D5800F02CF9B0F5FA6F05D338BD8521094896
+S31508000D6800F0F8F8DEE74FF4FA6000F019F9F4E74E
+S31508000D78480A00208C0A0020D00A002074000020A7
+S31508000D8810000020D85E000810B5064CD4F8C0023A
+S31508000D9802F00AF8204603F010FE002000F0FFFBD8
+S31508000DA810BD00BFD00A002070B506460D463F297B
+S31508000DB80AD82846FFF748FF012803D0BF210E485E
+S31508000DC800F0C8F8002406E0BB210B4800F0C2F87A
+S31508000DD8EFE70134A4B2ABB29C420BD200F0C4F9D7
+S31508000DE8305DFFF731FF0128F3D0C821024800F02B
+S31508000DF8B1F8EEE770BD00BFD85E000870B50646C4
+S31508000E080D461F4BD3F8C00201F03CFD1D4B1C785C
+S31508000E189CB91D48FFF754FF012801D0204670BD2C
+S31508000E28194B1B78013BDBB23E2BF7D80122154B31
+S31508000E381A700022154B1A70F0E7144B1B78013309
+S31508000E4811481844FFF73CFF0446012801D000243E
+S31508000E58E4E70E4B1A780132D2B21A700A4B1B789D
+S31508000E689A4201D00024D9E709493046FFF74AFBD8
+S31508000E780022044B1A70054B1B782B70CEE700BF6F
+S31508000E88D00A0020D40D0020940D0020D50D00208E
+S31508000E98950D002030B583B0144B1878FFF71AFF64
+S31508000EA808B30546402800D94025002405E09DF8E2
+S31508000EB807200F4B1A550134E4B2A5420DD90DF196
+S31508000EC807010A4B1878FFF7C9FE0128EFD04FF437
+S31508000ED8A471084800F03EF8E9E7ABB2044A812154
+S31508000EE8054804F05CFE03B030BD00BF480A002080
+S31508000EF8D4090020D85E0008D00A002070B5044638
+S31508000F0804F020FD064621460F4804F0F6FD85B292
+S31508000F18002401E00134A4B2AC420CD2315D0B4B7B
+S31508000F281878FFF761FE0128F4D04FF4B571084820
+S31508000F3800F010F8EEE704F005FD4023024601210B
+S31508000F48014804F034FE70BDD00A00208C0A00203F
+S31508000F58D85E000808B500F007F9FCE708B500F000
+S31508000F68F7F8012803D00B4B1B78012B00D008BDD6
+S31508000F78FFF7FCFD084B1B68084A1268134403F57B
+S31508000F88FA739842F3D30022024B1A70FFF79AFABB
+S31508000F98EDE700BFDC0D0020D80D0020E00D00208D
+S31508000FA8014B1860704700BFD80D0020014B186820
+S31508000FB8704700BFD80D002008B5054B1B78012BD4
+S31508000FC800D008BDFFF7D2FD024B1860F9E700BF4D
+S31508000FD8DC0D0020E00D002008B50122034B1A702D
+S31508000FE8FFF7EAFFFFF7BAFF08BD00BFDC0D0020D0
+S31508000FF808B5FFF763FA00F0B3F8FFF795FDFFF7B2
+S31508001008ADFC00F00DF8FFF7E7FF08BD08B500F0DE
+S31508001018ABF8FFF79DFD00F017F8FFF79FFF08BD2F
+S3150800102810B500F00FFAFFF78DF9064C0123237067
+S31508001038FFF7E0FC00232370FFF760FE0223237006
+S3150800104810BD00BF0000002000B583B00DF10701F0
+S315080010581848FFF70BFA012810D00DF107011548B3
+S31508001068FFF704FD012812D00DF107011148FFF713
+S31508001078C5FE012814D003B05DF804FB01220E4B07
+S315080010881A709DF807100B4800F0FCF9E5E70022EE
+S31508001098094B1A709DF80710064800F0F3F9E3E7BC
+S315080010A80222054B1A709DF80710024800F0EAF963
+S315080010B8E1E700BFE40D00200000002008B5FFF7AF
+S315080010C863FE08BD38B504460D460E4B1B78012B42
+S315080010D809D00C4B1B7853B10A4B1B78022B0BD043
+S315080010E800F0C8F938BDC9B2FFF78EF9F1E7E9B2D9
+S315080010F82046FFF79FFCEFE7E9B22046FFF754FEC4
+S31508001108EEE700BF00000020074B1B78022B05D02E
+S31508001118032B05D0012B05D0402070473F20704788
+S31508001128002070470820704700000020074B1B78EE
+S31508001138022B05D0032B05D0012B05D0402070477C
+S315080011483F2070470020704708207047000000209D
+S3150800115808B500F085F9034600B10123184608BD0D
+S3150800116808B500F013FA08BD08B500F014FA08BD6A
+S315080011780022014B5A707047240E0020034BFE22AA
+S31508001188DA7018710222A3F844207047240E00204A
+S3150800119810B5054C00232370FFF7EAFFFF23E37019
+S315080011A80123A4F8443010BD240E0020064BFF2264
+S315080011B8DA7000221A71597859719A71DA711A72A5
+S315080011C80622A3F844207047240E002008B50020FC
+S315080011D8FFF7D4FF08BD0000074BFF22DA70074A5D
+S315080011E89A6400221A715A719A710722C3F807205D
+S315080011F80822A3F844207047240E0020005F000840
+S31508001208044BFF22DA7042689A640122A3F8442044
+S31508001218704700BF240E002008B53120FFF7AEFF3F
+S3150800122808BD000038B5084CFF23E3700025257172
+S315080012386571FFF769FFA071E57125726572072365
+S31508001248A4F8443038BD00BF240E002038B5FFF78F
+S315080012588FFF0E4C01252570FF23E3701023237199
+S3150800126800236371FFF750FFA071FFF75FFFE07176
+S31508001278FFF75CFFC0F3072020726572A572082382
+S31508001288A4F84430FFF76AFB38BD00BF240E0020D7
+S3150800129838B505464478FFF737FF0138844210DC2D
+S315080012A80A4C6A78A16C201DFFF72CF9FF23E37016
+S315080012B86A78A36C1344A3646B780133A4F84430A2
+S315080012C838BD2220FFF75AFF38BD00BF240E00207C
+S315080012D838B504464578FFF717FF0138854211DC0B
+S315080012E861680A4DA9646278281DFFF70BF9FF2380
+S315080012F8EB706278AB6C1344AB6463780133A5F87A
+S31508001308443038BD2220FFF739FF38BD240E0020A7
+S31508001318F8B505461746002406E015F8013B1C44AF
+S31508001328E4B2FFF721FF31464E1E0029F5D13C608D
+S315080013380120F8BD10B5084CFF23E370E21D41688B
+S31508001348A06CFFF7E5FF207100236371A3710823DA
+S31508001358A4F8443010BD00BF240E002038B5054651
+S315080013680D4B9C6CFFF7D0FE6A1C411E2046FFF702
+S31508001378F9FA60B1084CFF23E370FFF7C5FE013898
+S31508001388A36C0344A3640123A4F8443038BD312070
+S31508001398FFF7F4FE38BD00BF240E002038B5044612
+S315080013A84578FFF7B1FE023885420EDC114BFF225D
+S315080013B8DA700122A3F84420617851B9FFF7E2FAF6
+S315080013C890B93120FFF7DAFE38BD2220FFF7D6FE9E
+S315080013D838BDA21C074B986CFFF7C4FA28B1617888
+S315080013E8044A936C0B44936438BD3120FFF7C6FE54
+S315080013F838BD00BF240E002008B54168074B986C15
+S31508001408FFF7B4FA30B1054BFF22DA700122A3F8C8
+S31508001418442008BD3120FFF7B1FE08BD240E002080
+S3150800142808B5FFF74FF8034BFF22DA700122A3F835
+S31508001438442008BD240E002008B589B2FFF742FEED
+S3150800144808BD0000054B00221A709A6483F84320E9
+S31508001458A3F844209A705A70704700BF240E0020DB
+S31508001468034B1B780BB1012070470020704700BF5B
+S31508001478240E00200022024B83F84320704700BF41
+S31508001488240E002008B50378FF2B04D0354A1278B5
+S31508001498012A14D008BDFFF7D9FE324B93F843301A
+S315080014A8012B5AD02F4BB3F944100029F2DD184600
+S315080014B8012380F843300330FFF7BEFFEAE7C93B4C
+S315080014C8352B46D8DFE803F03345454245453F36D0
+S315080014D83C394545454545454545454545454545BB
+S315080014E84545454545454545454545454545454596
+S315080014F84545241E1B2145454527452A2D30FFF716
+S31508001508C7FECAE7FFF7E4FEC7E7FFF779FEC4E7B1
+S31508001518FFF710FFC1E7FFF75FFEBEE7FFF756FEC6
+S31508001528BBE7FFF743FEB8E7FFF732FEB5E7FFF775
+S3150800153815FFB2E7FFF732FFAFE7FFF773FEACE731
+S31508001548FFF75AFFA9E7FFF76BFFA6E7FFF764FE61
+S31508001558A3E72020FFF712FE9FE71020FFF70EFEED
+S31508001568A0E700BF240E002008B5074B1B6913F433
+S31508001578005F03D001231BB1002008BD0023FAE74A
+S3150800158800F03EF8012008BD0008025808B5642096
+S3150800159800F008F808BD08B500F00AF808BD704755
+S315080015A870477047014B1880704700BF700E0020BF
+S315080015B808B5FFF7DBFA0E4B1B6898420FD30D4B9D
+S315080015C81B786BB901220B4B1A7080220A4B9A6159
+S315080015D8FFF7CCFA094B1B881844054B186008BD59
+S315080015E80022044B1A704FF40002034B9A61EFE786
+S315080015F8740E0020720E002000040258700E002097
+S315080016084FF40002014B9A61704700BF0004025864
+S3150800161810B5164B6FF00042DA670024DC674FF006
+S31508001628FF32C3F88020C3F88040C3F88420C3F883
+S315080016388440C3F88820C3F88840C3F88C20C3F8C8
+S315080016488C40C3F89020C3F89040C3F89420C3F898
+S315080016589440C3F89820C3F89840C3F89C20C3F868
+S315080016689C4004F07FF8204610BD00BF004402588D
+S31508001678104B1B780BB90120704710B504464FF478
+S315080016887A70B0FBF3F30C4A1068B0FBF3F000F07D
+S315080016989BF868B90F2C01D9012010BD00222146F4
+S315080016A84FF0FF3000F060F8044B1C60002010BDB6
+S315080016B8012010BD010000200800002004000020B9
+S315080016C810B5032000F03EF801F02CFD0F498B6990
+S315080016D8C3F303230E4AD35C03F01F03D8408B6970
+S315080016E803F00F03D35C03F01F0320FA03F3094A38
+S315080016F81360094B18600020FFF7BAFF10B10124E0
+S31508001708204610BD044603F07DFFF9E70044025859
+S31508001718585F00080C0000200800002038B5044669
+S31508001728FFF72CFA0546B4F1FF3F02D0044B1B78A5
+S315080017381C44FFF723FA401B8442FAD838BD00BF79
+S31508001748010000200649CB6823F4E0631B041B0C40
+S31508001758000200F4E0600343024A1A43CA6070476D
+S3150800176800ED00E00000FA0530B4144BDB68C3F35B
+S315080017780223C3F10704042C28BF04241D1D062DC3
+S3150800178813D9033B012505FA04F4013C2140994085
+S3150800179805FA03F3013B13401943002807DB09013F
+S315080017A8C9B2074B195430BC70470023EAE700F062
+S315080017B80F000901C9B2034B1954F4E700ED00E01C
+S315080017C800E400E014ED00E00138B0F1807F0AD2A9
+S315080017D8064B5860F021064A82F8231000209860C4
+S315080017E807221A6070470120704700BF10E000E022
+S315080017F800ED00E030B4436B0468D4F884106F4AEF
+S31508001808114041EA8301C4F884100468D4F88410A6
+S3150800181821F47F01856B41EA0541C4F88410816B80
+S315080018280B440468D4F88810114041EA8301C4F8C7
+S3150800183888100468D4F8881021F4FE01C56B41EABB
+S315080018480541C4F88810C16B03EB41030468D4F852
+S31508001858A010114041EA8301C4F8A0100468D4F81E
+S31508001868A01021F4FE01056C41EA0541C4F8A01050
+S31508001878046C416C01FB04340368D3F8B0101140BA
+S3150800188841EA8401C3F8B0100368D3F8B01021F40C
+S31508001898FE01856C41EA0541C3F8B010836CC16C3A
+S315080018A801FB03440368D3F8AC10114041EA8401EC
+S315080018B8C3F8AC10036D416D01FB03430468D4F803
+S315080018C8F010114041EA8301C4F8F0100468D4F80E
+S315080018D8F01021F47C11856D41EA0541C4F8F01031
+S315080018E8816D03EB41030468D4F8C0100A4042EA44
+S315080018F88303C4F8C0300268D2F8C03023F47C13D6
+S31508001908C16D43EA0143C2F8C0300268D2F8C03054
+S3150800191823F07C53016E43EA0163C2F8C030426B78
+S31508001928274B13449B00C366826B03EB820202674C
+S31508001938C16B02EBC1024267046C416C01FB04F1FE
+S3150800194802EB81028267846CC16C01FB04F102EB2D
+S315080019588102C267046D416D01FB04F102EB810245
+S31508001968C0F88020816D02EBC102C0F88420C46DDE
+S31508001978856E05FB04F402EB8402C0F88820016E24
+S3150800198801FB05F102EB8102C0F890200D498A4255
+S315080019980DD9D0F89C3043F02003C0F89C300323B7
+S315080019A880F89830012007E0002243F8042BD0F885
+S315080019B890209342F8D3002030BC70470300FFFFFD
+S315080019C8002B0010FCD30040F0B44C68E4B90E694B
+S315080019D88C6826430C6846EA84460D6ACC6944EA4C
+S315080019E805648D692C434D692C43CD682C43D0F882
+S315080019F88470806E03FB00F307EB830547F82360C2
+S31508001A086C600835002015E00C698E6826430C685A
+S31508001A18264346F08046E0E71418E678A3781B04C0
+S31508001A2843EA0663647843EA0423145C234345F8C7
+S31508001A38043B0430CB89034CE35C9842ECD3F0BCF6
+S31508001A48704700BF085F00087047000030B595B0BA
+S31508001A5804464C22A04901A804F066F9002C00F0B7
+S31508001A68388123689D4A934220D094F898300BB35E
+S31508001A782268936923F010039361FFF77FF80546F8
+S31508001A8823689A6912F0080F1AD0FFF777F8401BEF
+S31508001A980A28F5D9D4F89C3043F00103C4F89C30D9
+S31508001AA8032384F89830012015B030BD03F58073F8
+S31508001AB86360DAE784F899302046FFF7C5FFD7E769
+S31508001AC89A6942F001029A61FFF758F805462368B1
+S31508001AD89A6912F0010F0FD1FFF750F8401B0A2830
+S31508001AE8F5D9D4F89C3043F00103C4F89C30032395
+S31508001AF884F898300120D7E79A6942F002029A6179
+S31508001B08237C012B40D02268936943F040039361F4
+S31508001B18637C012B3ED02268936923F48043936142
+S31508001B28A37C012B3CD02268936943F480539361C4
+S31508001B382268936923F44073A1680B43936122686A
+S31508001B48936923F0A40393612268136923F01003A9
+S31508001B581361E368012B29D0002B2CD0022B00F047
+S31508001B689B802268936943F080039361226813690E
+S31508001B7843F010031361E368032B1CD122689369A9
+S31508001B8843F02003936116E02268936923F0400323
+S31508001B989361BDE72268936943F480439361BFE77D
+S31508001BA82268936923F480539361C1E7226893698D
+S31508001BB843F0040393612268A369591EE369013B4C
+S31508001BC81B0243EA4163216A01390B4361690139FA
+S31508001BD843EA0143D361A368B3F5407F62D0236E15
+S31508001BE833B12268D2F8C030616E0B43C2F8C030F0
+S31508001BF8E36D226ED3420DD02168D1F8C83023F0A0
+S31508001C080703A26E14A800EB820252F84C2C134361
+S31508001C18C1F8C830236C6BB12168D1F8BC3023F001
+S31508001C280703626C14A800EB820252F84C2C134383
+S31508001C38C1F8BC30A36C73B12168D1F8BC3023F065
+S31508001C487003E26C14A800EB820252F84C2C43EAA3
+S31508001C580213C1F8BC30236D73B12168D1F8BC30C2
+S31508001C6823F4E063626D14A800EB820252F84C2C48
+S31508001C7843EA0223C1F8BC302268184B9A4222D09C
+S31508001C880023C4F89430C4F89C30012384F89830AB
+S31508001C982046FFF7AFFD07E72268936943F020035C
+S31508001CA8936188E72168A36A013BE26A013A43EA35
+S31508001CB80223226B013A43EA0213626A013A43EAAB
+S31508001CC80243CB608BE76268936823F0030393604B
+S31508001CD8D6E70120E8E600BF605D000800A00040DE
+S31508001CE890F89830013BDBB2012B07D9D0F89C3025
+S31508001CF843F00203C0F89C3001207047CB680A6895
+S31508001D08D2B9072B0ED08A68DB0643EA82730A69BA
+S31508001D1843EA02434A691343C26E496842F82130C6
+S31508001D28002070470A69CB691B0243EA02438A699D
+S31508001D38134343F06053EFE710B40A6942EA437263
+S31508001D48072B0ED08C684B6943EA8473006F496881
+S31508001D5800EBC10440F83120636000205DF8044BAD
+S31508001D6870478B69F2E710B490F89840E4B2012CF2
+S31508001D7809D0D0F89C3043F00403C0F89C30012001
+S31508001D885DF8044B70470068920042EA011141EA7F
+S31508001D984303019A1343C0F880300020F0E790F80F
+S31508001DA89830DBB2012B07D0D0F89C3043F00403F7
+S31508001DB8C0F89C3001207047022380F898300268E2
+S31508001DC8936923F0010393610023C0F89C301846F1
+S31508001DD8704770B590F89840013CE4B2012C07D9D1
+S31508001DE8D0F89C3043F00203C0F89C30012070BD3F
+S31508001DF893FAA3F5B5FA85F50668D6F8C040C4F38C
+S31508001E080544A5420BD2D6F8CC4023420FD0D0F8C9
+S31508001E189C3043F04003C0F89C30012070BDD0F8D0
+S31508001E289C3043F02003C0F89C30012070BD93FA1B
+S31508001E38A3F3B3FA83F3FFF7C7FD002070BD90F844
+S31508001E489830DBB2022B07D0D0F89C3043F0080351
+S31508001E58C0F89C30012070470368C3F8D0100020EA
+S31508001E6870470000F0B590F89840E4B2022C07D005
+S31508001E78D0F89C3043F00803C0F89C300120F0BD28
+S31508001E88402937D041295BD0046DA1427ED2C46F60
+S31508001E98456D05FB01F504EB85044FF0000E256832
+S31508001EA805F080455560002D78D12568C5F38A4523
+S31508001EB81560256805F000559560256805F0004504
+S31508001EC81561A588D561656805F47025D5606568C6
+S31508001ED805F480155561656805F400159561E57979
+S31508001EE805F07F0515626568ED0F556204F108056A
+S31508001EF800245BE00468D4F8A05015F4FE0F0FD050
+S31508001F08D4F8A45015F07F0F12D0D4F8A440C4F31F
+S31508001F18052E446F456C05FB0EF504EB8504BEE7F4
 S31508001F28D0F89C3043F02003C0F89C300120F0BD5F
 S31508001F38D0F89C3043F48073C0F89C300120F0BD7B
-S31508001F48D0F89C3043F02003C0F89C300120F0BD3F
-S31508001F58256825F06045156085E72E5D1E55013410
-S31508001F68D689134FBE5DB442F7D340290BD0412911
-S31508001F780ED01F2911D80268012303FA01F1C2F805
-S31508001F8898100020F0BD0368C3F8A8E00020F0BD4B
-S31508001F980368C3F8B8E00020F0BD026801F01F0125
-S31508001FA8012303FA01F1C2F89C100020F0BD00BF16
-S31508001FB8EC5E00080368D3F89820D3F89C001F291C
-S31508001FC803D8CA4012F0010F17D01F2905D901F006
-S31508001FD81F02D04010F0010F11D01F2907D901F0B0
-S31508001FE81F01012000FA01F1C3F89C10704701206F
-S31508001FF800FA01F1C3F898107047002070470020CE
-S3150800200870470368D3F8CC300B4201D001207047DB
-S3150800201800207047144BDB6813F0010F09D0124BE8
-S31508002028124A5A6002F188325A60DB6813F0010FC7
-S3150800203816D10D4BD3F80C3113F0010F12D00A4BF9
-S315080020480A4AC3F8042102F18832C3F80421D3F8EE
-S315080020580C3113F0010F01D1002070470120704799
-S315080020680120704700207047002000522301674569
-S315080020780D4BDA6842F00102DA60DB6813F0010FEB
-S315080020880FD0094BD3F80C2142F00102C3F80C21F2
-S31508002098D3F80C3113F0010F01D000207047012046
-S315080020A870470120704700BF00200052F8B5054662
-S315080020B80E46FEF759FD0746012E09D0374C14E09F
-S315080020C8FEF752FDC01B854261D375B90320F8BDDA
-S315080020D804240AE0324B1B6934EA03030CBF0123C4
-S315080020E8002383B1B5F1FF3FEAD134F00403F1D0F8
-S315080020F82B4BD3F8103124EA030333F000430CBF03
-S3150800210801230023EDE7012E1AD0254BD3F8103109
-S3150800211823F0684323F480135B0C5B0443F0004305
-S3150800212833F0024219D01F498A691A438A61002B7B
-S315080021380FDA23F000431A4AC2F814310120F8BD11
-S31508002148174B1B6923F0684323F480135B0C5B0465
-S31508002158E6E7134A53610120F8BD012E0CD0104B4F
-S31508002168D3F8103113F4803F15D04FF480320C4B56
-S31508002178C3F814210020F8BD094B1B6913F4803FE6
-S3150800218807D04FF48032064B5A610020F8BD032069
-S31508002198F8BD0020F8BD0020F8BD00BF0400008087
-S315080021A800200052800E00202C4B1B7D012B51D09D
-S315080021B870B50C4615460122284B1A7501F1784167
-S315080021C8B1F5801F38D216460022244B9A6131464B
-S315080021D84CF25030FFF76AFF034640BB012E2DD05C
-S315080021E81F4AD2F80C3143F00203C2F80C31BFF388
-S315080021F86F8FBFF34F8F082355F8042B44F8042B29
-S31508002208013B13F0FF03F7D1BFF36F8FBFF34F8F6F
-S3150800221831464CF25030FFF749FF0346012E13D0DA
-S315080022280F49D1F80C2122F00202C1F80C2100212D
-S315080022380A4A1175184670BD0226C5E7084AD368C2
-S3150800224843F00203D360D2E70549CA6822F00202BE
-S31508002258CA60ECE702231846704700BF800E0020C4
-S315080022680020005201F00303032B24D011F0010FBC
-S315080022780BD01D4BDA6822F03002DA60DA680243BE
-S31508002288DA60DA6842F08802DA6011F0020F11D0D3
-S31508002298154BD3F80C2122F03002C3F80C21D3F8D9
-S315080022A80C211043C3F80C01D3F80C2142F088021C
-S315080022B8C3F80C2170470C4BDA6822F03002DA6052
-S315080022C8D3F80C2122F03002C3F80C21DA6802434D
-S315080022D8DA60D3F80C211043C3F80C019A6942F066
-S315080022E810029A61704700BF0020005230B411F0FE
-S315080022F8010F0BD0104CE36823F4E663E360E36848
-S3150800230842EA00252B4343F08403E36011F0020FE9
-S315080023180FD00949D1F80C3123F4E663C1F80C311A
-S31508002328D1F80C3142EA00221A4342F08402C1F875
-S315080023380C2130BC704700BF00200052F8B5484B46
-S315080023481B7D012B00F089800F460446444B012269
-S315080023581A7500229A61436813F0010F0ED10026F8
-S31508002368636813F0020F13D1002E71D12368012B6D
-S3150800237817D04FF0FF333B60A56848E001214CF2BF
-S315080023885030FFF793FE06460028E9D00126E7E70E
-S3150800239802214CF25030FFF789FE0028E4D00126C6
-S315080023A8E2E761682069FFF75DFF636813F0010FCC
-S315080023B812D1636813F0020F4AD002214CF250304A
-S315080023C8FFF774FE00B10126264AD2F80C3123F02D
-S315080023D80803C2F80C313BE001214CF25030FFF7F4
-S315080023E865FE00B101261F4AD36823F00803D360A7
-S315080023F8DFE701214CF25030FFF758FE0646194A26
-S31508002408D168194B0B40D3600FE006BB0135E3686A
-S31508002418A26813449D421BD2226961682846FFF7C1
-S3150800242865FF636813F0010FE3D1636813F0020FC1
-S31508002438EBD002214CF25030FFF738FE0646094A1F
-S31508002448D2F80C11084B0B40C2F80C31DDE73D6099
-S315080024580022034B1A753046F8BD0226FBE700BF73
-S31508002468800E002000200052FBF8FFFF2DE9F047F8
-S3150800247882B0D0F80080CA00521A930003445A6DF5
-S315080024881B6D9A4255D8C1469B1AC1EBC104A200D6
-S315080024980244526C934200D81A460C46074602F183
-S315080024A8030A4FEA9A0A15E006F1030A4FEA9A0A56
-S315080024B8E3001B1B9D003D44A96C3B7C0093B3B20B
-S315080024C8E2B2404601F0FEFFAB6C3344AB646B6D79
-S315080024D81E446E6509EB441303F510639B699BB2AA
-S315080024E89A4512D8E3001B1B9A003A44516D136D9E
-S315080024F899420AD24BB15B1AC4EBC4018A003A4422
-S31508002508566CB342D0D81E46CEE7E3001B1B98008C
-S3150800251807443A6D7B6D9A420FD804F00F040123DD
-S31508002528A340D8F8344824EA0304C8F834480020F5
-S3150800253800E0012002B0BDE8F0870020FAE77047FE
-S31508002548F0B58BB0002800F091800446056890F82D
-S31508002558BD3323B3032384F8BD33EB6B13F4807FB1
-S3150800256801D100232361206801F070FD254655F83E
-S31508002578107B6E460FCD0FC60FCD0FC695E8030024
-S3150800258886E80300231D0ECB384601F09DFC58B19A
-S31508002598022384F8BD33012528460BB0F0BD80F820
-S315080025A8BC33FFF7CCFFD5E70021206801F054FDBE
-S315080025B8002315E0D900C81A82002244012082F8AF
-S315080025C83D0082F83C30A2F84230002082F83F00ED
-S315080025D850649064CA1A9100214408650133DBB235
-S315080025E86568AB42E6D3002315E0D800C11A8A000D
-S315080025F82244002182F8FD1182F8FC3182F8FF1185
-S31508002608C2F80412C2F80812C21A90002044C0F888
-S3150800261810120133DBB29D42E7D8254655F8107BE0
-S315080026286E460FCD0FC60FCD0FC695E8030086E890
-S315080026380300231D0ECB384601F054FD054660B944
-S31508002648002384F83830012384F8BD33636A012BE4
-S3150800265808D0206802F005F99EE7022384F8BD33FE
-S31508002668012599E7204600F031FDF2E7012593E7B1
-S315080026787047026890F8BC33012B19D010B50123AE
-S3150800268880F8BC33836A012B0AD00446006802F036
-S31508002698DCF8206801F0D4FC002084F8BC0310BDDF
-S315080026A88369012BF1D0936B43F480339363ECE78A
-S315080026B80220704738B590F8BC33012B02D10225A1
-S315080026C8284638BD0446012380F8BC33006801F063
-S315080026D8BDFC206802F085F8054620B1002384F879
-S315080026E8BC330125ECE7206802F0BBF8002384F820
-S315080026F8BC33E5E768B110B50446032380F8BD3353
-S31508002708FFF7D8FF2046FFF7B3FF002084F8BD037C
-S3150800271810BD01207047000070B504460D460068D4
-S31508002728066C00EB411303F5306399682269012AA0
-S3150800273811D0374A964254D03DB9C5EBC502930025
-S315080027482344D3F81032002B5CD0E9B2204603F0B4
-S31508002758F7F8002070BD11F0080F09D02D4A9642E7
-S31508002768F7D911F4004FF4D04FF400429A60F0E715
-S3150800277811F0200F28D111F0280FEAD1254A9642E0
-S3150800278802D911F4004F22D1E900491B8A002244D4
-S31508002798D2F804121B69C3F31203C91AC2F8141231
-S315080027A8D2F80412D2F808320B44C2F8083235B9FE
-S315080027B8C5EBC50293002344D3F810325BB1E9B2DE
-S315080027C8204603F0BDF8C4E720229A60C1E74FF413
-S315080027D800429A60BDE704F57172012102F092F889
-S315080027E8EDE711F4004F09D111F0200F01D020228E
-S315080027F89A60E9B2204603F0A3F8AAE74FF4004224
-S315080028089A60A6E704F57172002102F07BF89CE746
-S315080028180A31544F0A30544F38B5044603681D6CBC
-S3150800282803EB4111D1F8082B0E4B9D4207D901F548
-S31508002838306112F4004F02D04FF400438B602046F3
-S3150800284803F076F8074B9D4202D92369012B01D07C
-S31508002858002038BD04F571720121206802F052F88B
-S31508002868F6E700BF0A30544F2DE9F84F04460568C5
-S31508002878284602F032F808B1BDE8F88F2F46064612
-S31508002888206801F0FAFF0028F6D0206801F0F5FF65
-S3150800289810F0020F04D02268536903F0020353614B
-S315080028A8206801F0EAFF10F0100F15D02268936926
-S315080028B823F010039361D5F8208008F00F09C8F3B0
-S315080028C84343022B00F08580062B00F0A58022687A
-S315080028D8936943F010039361206801F0CEFF10F462
-S315080028E8002F40F0AD80206801F0C7FF10F4802F54
-S315080028F840F0F180206801F0C0FF0028C0F25F812F
-S31508002908206801F0BAFF10F4006F0AD0D5F8083825
-S3150800291813F0010F40F06D812268536903F40063D0
-S315080029285361206801F0A9FF10F0006F15D02268DE
-S31508002938536903F00063536194F8F433002B40F0AD
-S315080029485C81012184F8F41323685B6DC3F3830360
-S31508002958C4F8F833204600F0CDFB206801F08DFF57
-S3150800296810F4805F40F04D81206801F086FF10F46E
-S31508002978005F40F0AB81206801F07FFF10F0080F78
-S3150800298840F0BC81206801F078FF10F4801F40F001
-S31508002998BE81206801F071FF10F4001F40F0C18164
-S315080029A8206801F06AFF10F0804F40F0C481206863
-S315080029B801F063FF10F0040F3FF45EAF23685D680B
-S315080029C815F0040F40F0C08123685A6815435D6006
-S315080029D852E747F6F07318EA030F3FF478AF4FEA61
-S315080029E8C90BABEB09034FEA830AA2444FEA181846
-S315080029F8C8F30A02DAF80812284601F083FEC8F373
-S31508002A080A08DAF808324344CAF80832DAF81432F7
-S31508002A184344CAF814325AE7082204F5717128465D
-S31508002A2801F070FEC8F30A184FEAC903A3EB0901B7
-S31508002A388A002244D2F814324344C2F8143246E7CC
-S31508002A48206801F01EFF8046B14617E007EB4913D8
-S31508002A580122C3F8082B49462046FFF75DFE1DE00C
-S31508002A6807EB49130822C3F8082B49462046FFF7FF
-S31508002A78D3FE16E009F101094FEA5808B8F1000F24
-S31508002A883FF431AF18F0010FF4D05FFA89F12068E6
-S31508002A9801F007FF824610F0010FD7D11AF0080F88
-S31508002AA8DED11AF0100F04D007EB49131022C3F829
-S31508002AB8082B1AF0200F04D007EB49132022C3F875
-S31508002AC8082B1AF4005FD5D007EB49134FF40052C8
-S31508002AD8C3F8082BCEE7206801F0DBFE8046B1462E
-S31508002AE82AE05946204602F037FF1AF0080F04D0A4
-S31508002AF807EB49130822C3F808291AF0100F04D05F
-S31508002B0807EB49131022C3F808291AF0400F04D016
-S31508002B1807EB49134022C3F808291AF0020F04D014
-S31508002B2807EB49130222C3F808291AF0800F41D186
-S31508002B3809F101094FEA5808B8F1000F3FF4DAAE6F
-S31508002B4818F0010FF4D05FFA89FB5946206801F09E
-S31508002B58B1FE824610F0010FC7D009F00F03012114
-S31508002B6801FA03F2D7F8343823EA0203C7F83438E7
-S31508002B7807EB4913C3F8081923698B42B1D14FEA01
-S31508002B88C902A2EB090293002344596C9A6C0A44B9
-S31508002B989A64B9F1000FA4D1C9EBC902930023447A
-S31508002BA81B6D002B9DD104F571720121206801F077
-S31508002BB8A9FE96E749462046FFF758FCB8E7D5F830
-S31508002BC8043823F00103C5F8043894F8F433012BC4
-S31508002BD808D0204602F006FF2268536903F000432E
-S31508002BE853618DE6002184F8F413204600F082FA32
-S31508002BF8F2E7204602F0DCFE8EE6204602F0D8FE12
-S31508002C08ABE605F50068D8F8043023F00103C8F8E0
-S31508002C1804301021206801F037FA20E007EB461344
-S31508002C284FF67F31C3F80819D3F8002922F40012A1
-S31508002C38C3F80029D3F8002942F00062C3F800292E
-S31508002C48C3F8081BD3F8002B22F40012C3F8002B8C
-S31508002C58D3F8002B42F00062C3F8002B01366368EC
-S31508002C689E42DBD3D8F81C3043F00113C8F81C3051
-S31508002C78236BEBB1D8F8843043F00B03C8F88430DB
-S31508002C88D8F8443043F00B03C8F84430D5F8003870
-S31508002C9823F4FE63C5F8003804F57172217C2068B0
-S31508002CA801F030FE2268536903F4805353615BE6EA
-S31508002CB8D8F8142042F22B031343C8F81430D8F86E
-S31508002CC8103043F00B03C8F81030DFE7206801F02E
-S31508002CD809FE206801F0CAFAE060256800F00CFBD6
-S31508002CE8227B0146284601F035F9204602F046FEC1
-S31508002CF82268536903F4005353613CE6204602F000
-S31508002D0836FE2268536903F0080353613AE6002140
-S31508002D18204602F076FE2268536903F4801353614D
-S31508002D2837E60021204602F066FE2268536903F456
-S31508002D380013536134E6204602F069FE2268536997
-S31508002D4803F08043536132E6204602F06AFE3BE60A
-S31508002D58026890F8BC33012B16D010B5012380F809
-S31508002D68BC33836A012B07D00446006801F06DFD61
-S31508002D78002084F8BC0310BD8369012BF4D0936B3B
-S31508002D8843F480339363EFE70220704790F8BC3327
-S31508002D98012B01D10220704710B50446012380F89B
-S31508002DA8BC33006801F05DFD002084F8BC0310BD43
-S31508002DB890F8BC33012B01D10220704710B50446A0
-S31508002DC8012380F8BC3380F83810006801F02DFD1F
-S31508002DD8002084F8BC0310BDF8B511F0800F1ED189
-S31508002DE801F00F06F500AF1BBC00274604F5FC7476
-S31508002DF8044404343E460644002586F8FD5101F08D
-S31508002E080F012170A260E370627802B1E180022B9B
-S31508002E1814D090F8BC33012B13D10220F8BD01F069
-S31508002E280F06F500AF1BBC002746383404440434A3
-S31508002E383E460644012586F83D50E0E700232371FF
-S31508002E48E7E70546012380F8BC332146006801F008
-S31508002E581DFA002085F8BC03F8BD38B511F0800FB7
-S31508002E6817D101F00F04E200151BAB001D4603F548
-S31508002E78FC73034404332C460444002284F8FD21D9
-S31508002E8801F00F01197090F8BC23012A10D102200D
-S31508002E9838BD01F00F04E200151BAB001D46383398
-S31508002EA8034404332C460444012284F83D20E7E70A
-S31508002EB80446012280F8BC231946006801F02EFA58
-S31508002EC8002084F8BC0338BD70B501F00F05EE0084
-S31508002ED8711B8C0004F5FC740444211D761BB40090
-S31508002EE80444C4F80822C4F810320023C4F814327B
-S31508002EF884F8FD3184F8FC510369012B06D065B1C5
-S31508002F08DAB2006801F0F2FA002070BDC5EBC50612
-S31508002F18B4000444C4F80C22F1E7DAB2006801F0F8
-S31508002F2845FAF1E701F00F01C1EBC1018B0018441E
-S31508002F38D0F81402704770B501F00F05EE00711B42
-S31508002F488C0038340444211D761BB4000444A2645A
-S31508002F58236500236365012384F83D3084F83C50D3
-S31508002F680369012B06D05DB1DAB2006801F0BEFA32
-S31508002F78002070BDC5EBC506B4000444E264F2E758
-S31508002F88DAB2006801F012FAF2E738B501F00F056F
-S31508002F9843689D4238D811F0800F15D1CA00541AD3
-S31508002FA8A3001C4603F5FC73034404332246024473
-S31508002FB8002182F8FD1101229A701D7090F8BC2331
-S31508002FC8012A0DD1022038BDEA00511B8B0019468B
-S31508002FD83833034404330144012281F83D20EAE7E3
-S31508002FE80446012280F8BC231946006801F09EFBB6
-S31508002FF81DB1002084F8BC0338BD04F57172217C24
-S31508003008206801F07FFCF4E7012038BD01F00F03C2
-S31508003018426893422FD810B511F0800F14D1DA0000
-S31508003028D41AA1000C4601F5FC7101440431044484
-S31508003038002284F8FD2100228A700B7090F8BC33B0
-S31508003048012B0DD1022010BDDA00D41AA1000C46B6
-S315080030583831014404310444012284F83D20EAE762
-S315080030680446012380F8BC33006801F08CFB002075
-S3150800307884F8BC0310BD0120704730B40468606A40
-S3150800308829B10D46A36A00EB134000230CE040EA79
-S315080030980240A06212E003F1400104EB810149688D
-S315080030A800EB11400133DBB2691E8B42F3D340EAC9
-S315080030B8024005F13F0104EB81014860002030BC5D
-S315080030C87047036859620020704700000246036883
-S315080030D80121C0F8FC13002082F8F4039A6942F02B
-S315080030E800629A61596D024A0A435A65704700BFD9
-S315080030F80300001070470000024AD36843F0807343
-S31508003108D360704700480258734B1B6903F03803AD
-S31508003118102B00F0DF80182B11D00BB16F487047C1
-S315080031286D4B1B6813F0200F01D16D4870476A4B29
-S315080031381868C0F3C1006A4B23FA00F0704710B448
-S31508003148654A916A01F00301906AC0F30510D46ACA
-S3150800315804F00104536BC3F3CC0303FB04F307EE33
-S31508003168903AF8EE677A002800F09480012966D02C
-S31508003178F9B1022900F0918007EE100AF8EE476ABD
-S315080031889FED586A86EE267A534B1B6BC3F30803E2
-S3150800319806EE903AF8EE666A9FED536A67EE867A07
-S315080031A876EEA77AF7EE006A77EEA67A27EE277AFA
-S315080031B861E0494B1B6813F0200F23D046490A687B
-S315080031C8C2F3C102464BD34007EE103AF8EE476AF7
-S315080031D807EE100AB8EE476A86EE867A0B6BC3F3D3
-S315080031E8080306EE903AF8EE666A9FED3F6A67EEC0
-S315080031F8867A76EEA77AF7EE006A77EEA67A27EE4B
-S31508003208277A38E007EE100AF8EE476A9FED376A1C
-S3150800321886EE267A304B1B6BC3F3080306EE903A04
-S31508003228F8EE666A9FED306A67EE867A76EEA77AD2
-S31508003238F7EE006A77EEA67A27EE277A1BE007EEFE
-S31508003248100AF8EE476A9FED276A86EE267A224B19
-S315080032581B6BC3F3080306EE903AF8EE666A9FED11
-S31508003268226A67EE867A76EEA77AF7EE006A77EE2E
-S31508003278A67A27EE277A184B1B6BC3F34623013326
-S3150800328807EE903AF8EE677AC7EE276AFCEEE67A12
-S3150800329817EE900A5DF8044B704707EE100AF8EE29
-S315080032A8476A9FED136A86EE267A0B4B1B6BC3F3A8
-S315080032B8080306EE903AF8EE666A9FED0B6A67EE23
-S315080032C8867A76EEA77AF7EE006A77EEA67A27EE7A
-S315080032D8277AD0E7074870470044025800093D0096
-S315080032E80090D0030024744A000000390024744C66
-S315080032F80024F44A00127A0008B5FFF705FF0B4ABE
-S315080033089369C3F303230A49CB5C03F01F0320FA26
-S3150800331803F3926902F00F02885C00F01F0023FA93
-S3150800332800F0044A1060044A136008BD00440258B5
-S315080033383C5F00080C000020080000206A4B9842F1
-S3150800334822D06A4B98422FD0694B98423CD0694B99
-S31508003358984249D0684B984256D0684B984263D0F1
-S31508003368674B984270D0674B98427DD0664B984217
-S3150800337800F08A80654B984200F09680644B984224
-S3150800338800F0A2800120704703F58843D3F8882007
-S3150800339842F00102C3F88820D3F8882022F00102F7
-S315080033A8C3F888200020704703F58043D3F888209F
-S315080033B842F00202C3F88820D3F8882022F00202D5
-S315080033C8C3F888200020704703F57053D3F888207F
-S315080033D842F00402C3F88820D3F8882022F00402B1
-S315080033E8C3F888200020704703F56053D3F888206F
-S315080033F842F00802C3F88820D3F8882022F0080289
-S31508003408C3F888200020704703F55053D3F888205E
-S3150800341842F01002C3F88820D3F8882022F0100258
-S31508003428C3F888200020704703F54053D3F888204E
-S3150800343842F02002C3F88820D3F8882022F0200218
-S31508003448C3F888200020704703F53053D3F888203E
-S3150800345842F04002C3F88820D3F8882022F04002B8
-S31508003468C3F888200020704703F52053D3F888202E
-S3150800347842F08002C3F88820D3F8882022F0800218
-S31508003488C3F888200020704703F51053D3F888201E
-S3150800349842F48072C3F88820D3F8882022F4807210
-S315080034A8C3F888200020704703F50053D3F888200E
-S315080034B842F40072C3F88820D3F8882022F40072F0
-S315080034C8C3F888200020704703F5E053D3F888200E
-S315080034D842F48062C3F88820D3F8882022F48062F0
-S315080034E8C3F88820002070470000025800040258D4
-S315080034F800080258000C0258001002580014025816
-S3150800350800180258001C02580020025800240258C5
-S3150800351800280258F0B40C6894FAA4F4B4FA84F4AF
-S315080035282EE08E68826803FB03F505EB450722EA59
-S31508003538070205FB06F52A4382600E68CD684268CD
-S3150800354822EA060205FB06F52A43426024E0466A93
-S315080035581B0A03FB03F707FB03F707FB03F3C3EB96
-S31508003568031726EA07074E6903FB06F33B4343623C
-S315080035784B680668324005FB03F3134303600134BE
-S315080035880B6833FA04F227D00122A2401340F6D07A
-S315080035984A68013A012AC4D90F69C66803FB03F5C4
-S315080035A805EB4502D243164005FB07F73E43C660BE
-S315080035B84E68022EDCD1FF2BC9D8066A05FB03F72D
-S315080035C807FB03F3C3EB031726EA07074E6903FB52
-S315080035D806F33B430362CBE70020F0BC70470000C4
-S315080035E82A4A136843F001031360284B1B6813F033
-S315080035F8040F1AD10023002BF7D0244B00221A6196
-S315080036081968234A0A401A60204B1B6813F0007F82
-S315080036180DD00123002BF7D11C4B1B6813F0006F44
-S3150800362807D00123002BF7D107E00123E3E700239E
-S31508003638F0E70023F6E7002333B1144B1B6813F0B1
-S31508003648005FF8D00123F7E7104B00229A61DA6188
-S315080036581A62104999621049D962104919635A635E
-S315080036689963DA6319645A64196821F48021196020
-S315080036781A66996E40F2FF720A439A66D3F8D02002
-S3150800368842F48032C3F8D020704700BF004402587D
-S3150800369845EDF6EA000202020000FF018002010178
-S315080036A807EE900AF8EE676A07EE901AF8EE677A58
-S315080036B886EEA77A07EE902AF8EE677A06EE903A2B
-S315080036C8F8EE666A9FED096A66EE866A77EEA67A66
-S315080036D827EE277ADDED007AF8EE677AC7EE276ACD
-S315080036E8FCEEE67A17EE900A704700BF000000392C
-S315080036F82DE9F04182B04E4B9B6A03F00303012B78
-S3150800370870D0002B5ED0022B77D0002600230360EA
-S3150800371843608360464B9D6AC5F305151A6BC2F369
-S315080037280802541CDB6A13F0010F77D00123002B1B
-S3150800373876D03F4B5F6BC7F3CC07002D3FD03C4B89
-S31508003748DB6A13F4803F6DD0012380466BB1384B92
-S315080037581B6BC3F34623013300933B46224629468F
-S315080037683046FFF79DFFC8F80000314BDB6A13F4B3
-S31508003778003F59D001236BB12D4B1B6BC3F306438E
-S31508003788013300933B46224629463046FFF788FF11
-S31508003798C8F80400264BDB6A13F4802F46D00123A9
-S315080037A86BB1234B1B6BC3F30663013300933B468C
-S315080037B8224629463046FFF773FFC8F8080002B0C4
-S315080037C8BDE8F0811A4B1B6813F0040F08D00123D3
-S315080037D8F3B1174B1B68C3F3C103164EDE4095E7D2
-S315080037E80023F5E7124B1B6813F4807F03D00123E7
-S315080037F883B900268AE70023FAE70D4B1B6813F4FA
-S31508003808003F03D001233BB900267FE70023FAE7E8
-S3150800381800267BE7084E79E7084E77E7002386E710
-S3150800382800278AE7002390E70023A4E70023B7E7E1
-S31508003838004402580090D00300093D0000127A009F
-S315080038482DE9F04182B04E4B9B6A03F00303012B26
-S3150800385870D0002B5ED0022B77D000260023036099
-S3150800386843608360464B9D6AC5F305359A6BC2F378
-S315080038780802541CDB6A13F0100F77D00123002BBB
-S3150800388876D03F4BDF6BC7F3CC07002D3FD03C4BB8
-S31508003898DB6A13F4002F6DD0012380466BB1384BD1
-S315080038A89B6BC3F34623013300933B4622462946BE
-S315080038B83046FFF7F5FEC8F80000314BDB6A13F40B
-S315080038C8801F59D001236BB12D4B9B6BC3F306435D
-S315080038D8013300933B46224629463046FFF7E0FE69
-S315080038E8C8F80400264BDB6A13F4001F46D00123E8
-S315080038F86BB1234B9B6BC3F30663013300933B46BB
-S31508003908224629463046FFF7CBFEC8F8080002B01B
-S31508003918BDE8F0811A4B1B6813F0040F08D0012381
-S31508003928F3B1174B1B68C3F3C103164EDE4095E780
-S315080039380023F5E7124B1B6813F4807F03D0012395
-S3150800394883B900268AE70023FAE70D4B1B6813F4A8
-S31508003958003F03D001233BB900267FE70023FAE797
-S3150800396800267BE7084E79E7084E77E7002386E7BF
-S3150800397800278AE7002390E70023A4E70023B7E790
-S31508003988004402580090D00300093D0000127A004E
-S315080039982DE9F04182B04F4B9B6A03F00303012BD4
-S315080039A872D0002B60D0022B79D000260023036042
-S315080039B843608360474B9D6AC5F305551A6CC2F385
-S315080039C80802541CDB6A13F4807F79D00123002B84
-S315080039D878D0404B5F6CC7F3CC07002D18BF002E74
-S315080039E83FD03C4BDB6A13F4800F6DD00123804629
-S315080039F86BB1384B1B6CC3F34623013300933B4624
-S31508003A08224629463046FFF74BFEC8F80000314BD8
-S31508003A18DB6A13F4000F59D001236BB12D4B1B6CCD
-S31508003A28C3F30643013300933B46224629463046EC
-S31508003A38FFF736FEC8F80400264BDB6A13F0807FCA
-S31508003A4846D001236BB1234B1B6CC3F306630133C2
-S31508003A5800933B46224629463046FFF721FEC8F81A
-S31508003A68080002B0BDE8F0811A4B1B6813F0040F72
-S31508003A7808D00123F3B1174B1B68C3F3C103164ECD
-S31508003A88DE4093E70023F5E7124B1B6813F4807FA3
-S31508003A9803D0012383B9002688E70023FAE70D4BEC
-S31508003AA81B6813F4003F03D001233BB900267DE7C2
-S31508003AB80023FAE7002679E7084E77E7084E75E700
-S31508003AC8002384E7002788E7002390E70023A4E774
-S31508003AD80023B7E7004402580090D00300093D00C8
-S31508003AE800127A00154B1B6903F03803182B0ED8F9
-S31508003AF8DFE803F00F0D0D0D0D0D0D0D210D0D0D44
-S31508003B080D0D0D0D160D0D0D0D0D0D0D18000020C2
-S31508003B1870470A4B1B68C3F3C1030948D840704766
-S31508003B280848704700B585B001A8FFF7E1FD019878
-S31508003B3805B05DF804FB0448704700BF0044025806
-S31508003B480090D00300127A0000093D00044B9B69D7
-S31508003B5803F00F03034AD35C03F01F03D8407047EA
-S31508003B6800440258FC5E0008044BDB69C3F30213E1
+S31508001F480468D4F8B05015F4FE0F0FD0D4F8B4507E
+S31508001F5815F07F0F12D0D4F8B440C4F3052E846F59
+S31508001F68C56C05FB0EF504EB850498E7D0F89C309C
+S31508001F7843F02003C0F89C300120F0BDD0F89C300F
+S31508001F8843F48073C0F89C300120F0BDD0F89C302B
+S31508001F9843F02003C0F89C300120F0BD256825F0E1
+S31508001FA86045156085E72E5D1E550134D689134FA1
+S31508001FB8BE5DB442F7D340290BD041290ED01F295C
+S31508001FC811D80268012303FA01F1C2F89810002013
+S31508001FD8F0BD0368C3F8A8E00020F0BD0368C3F89D
+S31508001FE8B8E00020F0BD026801F01F01012303FADA
+S31508001FF801F1C2F89C100020F0BD00BF085F000878
+S315080020080368D3F8CC300B4201D001207047002072
+S315080020187047402905D00368D3F8B40000F07F005C
+S3150800202870470368D3F8A40000F07F0070470000E3
+S31508002038144BDB6813F0010F09D0124B124A5A6089
+S3150800204802F188325A60DB6813F0010F16D10D4B7E
+S31508002058D3F80C3113F0010F12D00A4B0A4AC3F809
+S31508002068042102F18832C3F80421D3F80C3113F09D
+S31508002078010F01D1002070470120704701207047E1
+S315080020880020704700200052230167450D4BDA6887
+S3150800209842F00102DA60DB6813F0010F0FD0094B32
+S315080020A8D3F80C2142F00102C3F80C21D3F80C31FD
+S315080020B813F0010F01D00020704701207047012056
+S315080020C8704700BF00200052F8B505460E46FEF7D1
+S315080020D855FD0746012E09D0374C14E0FEF74EFD8C
+S315080020E8C01B854261D375B90320F8BD04240AE0EC
+S315080020F8324B1B6934EA03030CBF0123002383B15F
+S31508002108B5F1FF3FEAD134F00403F1D02B4BD3F8ED
+S31508002118103124EA030333F000430CBF01230023DC
+S31508002128EDE7012E1AD0254BD3F8103123F0684372
+S3150800213823F480135B0C5B0443F0004333F002423C
+S3150800214819D01F498A691A438A61002B0FDA23F0C6
+S3150800215800431A4AC2F814310120F8BD174B1B6907
+S3150800216823F0684323F480135B0C5B04E6E7134A01
+S3150800217853610120F8BD012E0CD0104BD3F810314D
+S3150800218813F4803F15D04FF480320C4BC3F8142152
+S315080021980020F8BD094B1B6913F4803F07D04FF49C
+S315080021A88032064B5A610020F8BD0320F8BD00208E
+S315080021B8F8BD0020F8BD00BF0400008000200052CA
+S315080021C8800E00202C4B1B7D012B51D070B50C4678
+S315080021D815460122284B1A7501F17841B1F5801F79
+S315080021E838D216460022244B9A6131464CF25030B2
+S315080021F8FFF76AFF034640BB012E2DD01F4AD2F8C7
+S315080022080C3143F00203C2F80C31BFF36F8FBFF3EA
+S315080022184F8F082355F8042B44F8042B013B13F079
+S31508002228FF03F7D1BFF36F8FBFF34F8F31464CF2D9
+S315080022385030FFF749FF0346012E13D00F49D1F84E
+S315080022480C2122F00202C1F80C2100210A4A117554
+S31508002258184670BD0226C5E7084AD36843F0020344
+S31508002268D360D2E70549CA6822F00202CA60ECE7D9
+S3150800227802231846704700BF800E0020002000522F
+S3150800228801F00303032B24D011F0010F0BD01D4BCB
+S31508002298DA6822F03002DA60DA680243DA60DA6865
+S315080022A842F08802DA6011F0020F11D0154BD3F804
+S315080022B80C2122F03002C3F80C21D3F80C21104364
+S315080022C8C3F80C01D3F80C2142F08802C3F80C2194
+S315080022D870470C4BDA6822F03002DA60D3F80C2122
+S315080022E822F03002C3F80C21DA680243DA60D3F820
+S315080022F80C211043C3F80C019A6942F010029A613E
+S31508002308704700BF0020005230B411F0010F0BD0FF
+S31508002318104CE36823F4E663E360E36842EA0025C1
+S315080023282B4343F08403E36011F0020F0FD00949E9
+S31508002338D1F80C3123F4E663C1F80C31D1F80C3125
+S3150800234842EA00221A4342F08402C1F80C2130BC42
+S31508002358704700BF00200052F8B5484B1B7D012B7B
+S3150800236800F089800F460446444B01221A7500225C
+S315080023789A61436813F0010F0ED10026636813F0BB
+S31508002388020F13D1002E71D12368012B17D04FF0F5
+S31508002398FF333B60A56848E001214CF25030FFF74F
+S315080023A893FE06460028E9D00126E7E702214CF203
+S315080023B85030FFF789FE0028E4D00126E2E7616875
+S315080023C82069FFF75DFF636813F0010F12D1636890
+S315080023D813F0020F4AD002214CF25030FFF774FE70
+S315080023E800B10126264AD2F80C3123F00803C2F8B0
+S315080023F80C313BE001214CF25030FFF765FE00B185
+S3150800240801261F4AD36823F00803D360DFE70121B2
+S315080024184CF25030FFF758FE0646194AD168194B50
+S315080024280B40D3600FE006BB0135E368A268134486
+S315080024389D421BD2226961682846FFF765FF6368D3
+S3150800244813F0010FE3D1636813F0020FEBD00221F2
+S315080024584CF25030FFF738FE0646094AD2F80C11F6
+S31508002468084B0B40C2F80C31DDE73D600022034BF0
+S315080024781A753046F8BD0226FBE700BF800E002015
+S3150800248800200052FBF8FFFF2DE9F04782B0D0F88C
+S315080024980080CA00521A930003445A6D1B6D9A426B
+S315080024A855D8C1469B1AC1EBC104A2000244526C16
+S315080024B8934200D81A460C46074602F1030A4FEA21
+S315080024C89A0A15E006F1030A4FEA9A0AE3001B1B63
+S315080024D89D003D44A96C3B7C0093B3B2E2B24046EA
+S315080024E801F0FEFFAB6C3344AB646B6D1E446E653E
+S315080024F809EB441303F510639B699BB29A4512D8F6
+S31508002508E3001B1B9A003A44516D136D99420AD28F
+S315080025184BB15B1AC4EBC4018A003A44566CB34201
+S31508002528D0D81E46CEE7E3001B1B980007443A6D31
+S315080025387B6D9A420FD804F00F040123A340D8F8FC
+S31508002548344824EA0304C8F83448002000E0012087
+S3150800255802B0BDE8F0870020FAE77047F0B58BB0FF
+S31508002568002800F091800446056890F8BD3323B327
+S31508002578032384F8BD33EB6B13F4807F01D1002362
+S315080025882361206801F070FD254655F8107B6E46D4
+S315080025980FCD0FC60FCD0FC695E8030086E80300D2
+S315080025A8231D0ECB384601F09DFC58B1022384F84A
+S315080025B8BD33012528460BB0F0BD80F8BC33FFF7BC
+S315080025C8CCFFD5E70021206801F054FD002315E06B
+S315080025D8D900C81A82002244012082F83D0082F8F0
+S315080025E83C30A2F84230002082F83F0050649064DC
+S315080025F8CA1A9100214408650133DBB26568AB4203
+S31508002608E6D3002315E0D800C11A8A00224400211F
+S3150800261882F8FD1182F8FC3182F8FF11C2F804121B
+S31508002628C2F80812C21A90002044C0F810120133E2
+S31508002638DBB29D42E7D8254655F8107B6E460FCD86
+S315080026480FC60FCD0FC695E8030086E80300231DBD
+S315080026580ECB384601F054FD054660B9002384F8C8
+S315080026683830012384F8BD33636A012B08D0206803
+S3150800267802F005F99EE7022384F8BD33012599E798
+S31508002688204600F031FDF2E7012593E77047026816
+S3150800269890F8BC33012B19D010B5012380F8BC3348
+S315080026A8836A012B0AD00446006802F0DCF8206821
+S315080026B801F0D4FC002084F8BC0310BD8369012B03
+S315080026C8F1D0936B43F480339363ECE702207047A9
+S315080026D838B590F8BC33012B02D10225284638BDF7
+S315080026E80446012380F8BC33006801F0BDFC206865
+S315080026F802F085F8054620B1002384F8BC33012585
+S31508002708ECE7206802F0BBF8002384F8BC33E5E759
+S3150800271868B110B50446032380F8BD33FFF7D8FF20
+S315080027282046FFF7B3FF002084F8BD0310BD01203B
+S315080027387047000070B504460D460068066C00EB45
+S31508002748411303F5306399682269012A11D0374A7B
+S31508002758964254D03DB9C5EBC50293002344D3F835
+S315080027681032002B5CD0E9B2204603F0F7F80020B7
+S3150800277870BD11F0080F09D02D4A9642F7D911F401
+S31508002788004FF4D04FF400429A60F0E711F0200F9A
+S3150800279828D111F0280FEAD1254A964202D911F410
+S315080027A8004F22D1E900491B8A002244D2F80412B4
+S315080027B81B69C3F31203C91AC2F81412D2F8041211
+S315080027C8D2F808320B44C2F8083235B9C5EBC50247
+S315080027D893002344D3F810325BB1E9B2204603F0DC
+S315080027E8BDF8C4E720229A60C1E74FF400429A6010
+S315080027F8BDE704F57172012102F092F8EDE711F4CC
+S31508002808004F09D111F0200F01D020229A60E9B2B1
+S31508002818204603F0A3F8AAE74FF400429A60A6E711
+S3150800282804F57172002102F07BF89CE70A31544FCF
+S315080028380A30544F38B5044603681D6C03EB41113A
+S31508002848D1F8082B0E4B9D4207D901F5306112F4D1
+S31508002858004F02D04FF400438B60204603F076F809
+S31508002868074B9D4202D92369012B01D0002038BDA8
+S3150800287804F571720121206802F052F8F6E700BFE4
+S315080028880A30544F2DE9F84F04460568284602F0E1
+S3150800289832F808B1BDE8F88F2F460646206801F0D9
+S315080028A8FAFF0028F6D0206801F0F5FF10F0020FAD
+S315080028B804D02268536903F002035361206801F0C3
+S315080028C8EAFF10F0100F15D02268936923F0100359
+S315080028D89361D5F8208008F00F09C8F34343022B03
+S315080028E800F08580062B00F0A5802268936943F0DE
+S315080028F810039361206801F0CEFF10F4002F40F012
+S31508002908AD80206801F0C7FF10F4802F40F0F180F1
+S31508002918206801F0C0FF0028C0F25F81206801F036
+S31508002928BAFF10F4006F0AD0D5F8083813F0010F6B
+S3150800293840F06D812268536903F400635361206887
+S3150800294801F0A9FF10F0006F15D02268536903F04B
+S315080029580063536194F8F433002B40F05C8101213D
+S3150800296884F8F41323685B6DC3F38303C4F8F83358
+S31508002978204600F0CDFB206801F08DFF10F4805F3B
+S3150800298840F04D81206801F086FF10F4005F40F0A2
+S31508002998AB81206801F07FFF10F0080F40F0BC817A
+S315080029A8206801F078FF10F4801F40F0BE81206887
+S315080029B801F071FF10F4001F40F0C181206801F092
+S315080029C86AFF10F0804F40F0C481206801F063FF69
+S315080029D810F0040F3FF45EAF23685D6815F0040F26
+S315080029E840F0C08123685A6815435D6052E747F688
+S315080029F8F07318EA030F3FF478AF4FEAC90BABEB4D
+S31508002A0809034FEA830AA2444FEA1818C8F30A02C8
+S31508002A18DAF80812284601F083FEC8F30A08DAF835
+S31508002A2808324344CAF80832DAF814324344CAF872
+S31508002A3814325AE7082204F57171284601F070FE27
+S31508002A48C8F30A184FEAC903A3EB09018A00224406
+S31508002A58D2F814324344C2F8143246E7206801F023
+S31508002A681EFF8046B14617E007EB49130122C3F853
+S31508002A78082B49462046FFF75DFE1DE007EB49137C
+S31508002A880822C3F8082B49462046FFF7D3FE16E066
+S31508002A9809F101094FEA5808B8F1000F3FF431AFB8
+S31508002AA818F0010FF4D05FFA89F1206801F007FFE2
+S31508002AB8824610F0010FD7D11AF0080FDED11AF0A6
+S31508002AC8100F04D007EB49131022C3F8082B1AF085
+S31508002AD8200F04D007EB49132022C3F8082B1AF451
+S31508002AE8005FD5D007EB49134FF40052C3F8082BFB
+S31508002AF8CEE7206801F0DBFE8046B1462AE0594653
+S31508002B08204602F037FF1AF0080F04D007EB4913DE
+S31508002B180822C3F808291AF0100F04D007EB49133E
+S31508002B281022C3F808291AF0400F04D007EB4913F6
+S31508002B384022C3F808291AF0020F04D007EB4913F4
+S31508002B480222C3F808291AF0800F41D109F10109B0
+S31508002B584FEA5808B8F1000F3FF4DAAE18F0010F3B
+S31508002B68F4D05FFA89FB5946206801F0B1FE82461F
+S31508002B7810F0010FC7D009F00F03012101FA03F27B
+S31508002B88D7F8343823EA0203C7F8343807EB491369
+S31508002B98C3F8081923698B42B1D14FEAC902A2EBD7
+S31508002BA8090293002344596C9A6C0A449A64B9F149
+S31508002BB8000FA4D1C9EBC902930023441B6D002B4F
+S31508002BC89DD104F571720121206801F0A9FE96E7E6
+S31508002BD849462046FFF758FCB8E7D5F8043823F0E5
+S31508002BE80103C5F8043894F8F433012B08D02046B5
+S31508002BF802F006FF2268536903F0004353618DE625
+S31508002C08002184F8F413204600F082FAF2E72046F9
+S31508002C1802F0DCFE8EE6204602F0D8FEABE605F5A5
+S31508002C280068D8F8043023F00103C8F804301021E6
+S31508002C38206801F037FA20E007EB46134FF67F3194
+S31508002C48C3F80819D3F8002922F40012C3F8002992
+S31508002C58D3F8002942F00062C3F80029C3F8081B14
+S31508002C68D3F8002B22F40012C3F8002BD3F8002B54
+S31508002C7842F00062C3F8002B013663689E42DBD334
+S31508002C88D8F81C3043F00113C8F81C30236BEBB195
+S31508002C98D8F8843043F00B03C8F88430D8F84430A1
+S31508002CA843F00B03C8F84430D5F8003823F4FE631C
+S31508002CB8C5F8003804F57172217C206801F030FEE9
+S31508002CC82268536903F4805353615BE6D8F81420E5
+S31508002CD842F22B031343C8F81430D8F8103043F0DF
+S31508002CE80B03C8F81030DFE7206801F009FE2068F2
+S31508002CF801F0CAFAE060256800F00CFB227B014661
+S31508002D08284601F035F9204602F046FE226853693E
+S31508002D1803F4005353613CE6204602F036FE226867
+S31508002D28536903F0080353613AE60021204602F086
+S31508002D3876FE2268536903F48013536137E6002147
+S31508002D48204602F066FE2268536903F400135361AD
+S31508002D5834E6204602F069FE2268536903F0804388
+S31508002D68536132E6204602F06AFE3BE6026890F8AE
+S31508002D78BC33012B16D010B5012380F8BC33836AFF
+S31508002D88012B07D00446006801F06DFD002084F881
+S31508002D98BC0310BD8369012BF4D0936B43F48033CD
+S31508002DA89363EFE70220704790F8BC33012B01D1F3
+S31508002DB80220704710B50446012380F8BC33006822
+S31508002DC801F05DFD002084F8BC0310BD90F8BC3303
+S31508002DD8012B01D10220704710B50446012380F85B
+S31508002DE8BC3380F83810006801F02DFD002084F8FF
+S31508002DF8BC0310BDF8B511F0800F1ED101F00F06FF
+S31508002E08F500AF1BBC00274604F5FC7404440434DB
+S31508002E183E460644002586F8FD5101F00F0121704B
+S31508002E28A260E370627802B1E180022B14D090F8B0
+S31508002E38BC33012B13D10220F8BD01F00F06F500AB
+S31508002E48AF1BBC0027463834044404343E460644BF
+S31508002E58012586F83D50E0E700232371E7E7054694
+S31508002E68012380F8BC332146006801F01DFA0020CA
+S31508002E7885F8BC03F8BD38B511F0800F17D101F0F5
+S31508002E880F04E200151BAB001D4603F5FC7303444B
+S31508002E9804332C460444002284F8FD2101F00F016E
+S31508002EA8197090F8BC23012A10D1022038BD01F008
+S31508002EB80F04E200151BAB001D46383303440433E0
+S31508002EC82C460444012284F83D20E7E704460122FB
+S31508002ED880F8BC231946006801F02EFA002084F809
+S31508002EE8BC0338BD70B501F00F05EE00711B8C00E8
+S31508002EF804F5FC740444211D761BB4000444C4F884
+S31508002F080822C4F810320023C4F8143284F8FD31B4
+S31508002F1884F8FC510369012B06D065B1DAB200685A
+S31508002F2801F0F2FA002070BDC5EBC506B4000444EA
+S31508002F38C4F80C22F1E7DAB2006801F045FAF1E7BD
+S31508002F4801F00F01C1EBC1018B001844D0F8140237
+S31508002F58704770B501F00F05EE00711B8C00383408
+S31508002F680444211D761BB4000444A2642365002387
+S31508002F786365012384F83D3084F83C500369012BC6
+S31508002F8806D05DB1DAB2006801F0BEFA002070BD5D
+S31508002F98C5EBC506B4000444E264F2E7DAB2006891
+S31508002FA801F012FAF2E738B501F00F0543689D42B9
+S31508002FB838D811F0800F15D1CA00541AA3001C4638
+S31508002FC803F5FC730344043322460244002182F8BD
+S31508002FD8FD1101229A701D7090F8BC23012A0DD1A3
+S31508002FE8022038BDEA00511B8B00194638330344C2
+S31508002FF804330144012281F83D20EAE70446012208
+S3150800300880F8BC231946006801F09EFB1DB1002014
+S3150800301884F8BC0338BD04F57172217C206801F078
+S315080030287FFCF4E7012038BD01F00F03426893429C
+S315080030382FD810B511F0800F14D1DA00D41AA100D0
+S315080030480C4601F5FC71014404310444002284F855
+S31508003058FD2100228A700B7090F8BC33012B0DD124
+S31508003068022010BDDA00D41AA1000C4638310144F2
+S3150800307804310444012284F83D20EAE70446012382
+S3150800308880F8BC33006801F08CFB002084F8BC0388
+S3150800309810BD0120704730B40468606A29B10D462E
+S315080030A8A36A00EB134000230CE040EA0240A06242
+S315080030B812E003F1400104EB8101496800EB114075
+S315080030C80133DBB2691E8B42F3D340EA024005F1AD
+S315080030D83F0104EB81014860002030BC7047036853
+S315080030E85962002070470000024603680121C0F8AB
+S315080030F8FC13002082F8F4039A6942F000629A6188
+S31508003108596D024A0A435A65704700BF0300001002
+S3150800311870470000024AD36843F08073D36070474B
+S3150800312800480258734B1B6903F03803102B00F04C
+S31508003138DF80182B11D00BB16F4870476D4B1B6891
+S3150800314813F0200F01D16D4870476A4B1868C0F311
+S31508003158C1006A4B23FA00F0704710B4654A916AB1
+S3150800316801F00301906AC0F30510D46A04F001045B
+S31508003178536BC3F3CC0303FB04F307EE903AF8EE5C
+S31508003188677A002800F09480012966D0F9B10229E7
+S3150800319800F0918007EE100AF8EE476A9FED586A24
+S315080031A886EE267A534B1B6BC3F3080306EE903A52
+S315080031B8F8EE666A9FED536A67EE867A76EEA77A20
+S315080031C8F7EE006A77EEA67A27EE277A61E0494B8A
+S315080031D81B6813F0200F23D046490A68C2F3C102B8
+S315080031E8464BD34007EE103AF8EE476A07EE100A40
+S315080031F8B8EE476A86EE867A0B6BC3F3080306EEC3
+S31508003208903AF8EE666A9FED3F6A67EE867A76EE3A
+S31508003218A77AF7EE006A77EEA67A27EE277A38E0D5
+S3150800322807EE100AF8EE476A9FED376A86EE267AA1
+S31508003238304B1B6BC3F3080306EE903AF8EE666A42
+S315080032489FED306A67EE867A76EEA77AF7EE006A19
+S3150800325877EEA67A27EE277A1BE007EE100AF8EE2D
+S31508003268476A9FED276A86EE267A224B1B6BC3F3BD
+S31508003278080306EE903AF8EE666A9FED226A67EE4C
+S31508003288867A76EEA77AF7EE006A77EEA67A27EEBA
+S31508003298277A184B1B6BC3F34623013307EE903A7C
+S315080032A8F8EE677AC7EE276AFCEEE67A17EE900A12
+S315080032B85DF8044B704707EE100AF8EE476A9FED6B
+S315080032C8136A86EE267A0B4B1B6BC3F3080306EEC6
+S315080032D8903AF8EE666A9FED0B6A67EE867A76EE9E
+S315080032E8A77AF7EE006A77EEA67A27EE277AD0E766
+S315080032F8074870470044025800093D000090D0036B
+S315080033080024744A000000390024744C0024F44A46
+S3150800331800127A0008B5FFF705FF0B4A9369C3F34D
+S3150800332803230A49CB5C03F01F0320FA03F39269C7
+S3150800333802F00F02885C00F01F0023FA00F0044A26
+S315080033481060044A136008BD00440258585F000814
+S315080033580C000020080000206A4B984222D06A4BCD
+S3150800336898422FD0694B98423CD0694B984249D02D
+S31508003378684B984256D0684B984263D0674B984238
+S3150800338870D0674B98427DD0664B984200F08A8089
+S31508003398654B984200F09680644B984200F0A280EC
+S315080033A80120704703F58843D3F8882042F00102C4
+S315080033B8C3F88820D3F8882022F00102C3F88820A9
+S315080033C80020704703F58043D3F8882042F00202AC
+S315080033D8C3F88820D3F8882022F00202C3F8882088
+S315080033E80020704703F57053D3F8882042F004028A
+S315080033F8C3F88820D3F8882022F00402C3F8882066
+S315080034080020704703F56053D3F8882042F0080275
+S31508003418C3F88820D3F8882022F00802C3F8882041
+S315080034280020704703F55053D3F8882042F010025D
+S31508003438C3F88820D3F8882022F01002C3F8882019
+S315080034480020704703F54053D3F8882042F020023D
+S31508003458C3F88820D3F8882022F02002C3F88820E9
+S315080034680020704703F53053D3F8882042F040020D
+S31508003478C3F88820D3F8882022F04002C3F88820A9
+S315080034880020704703F52053D3F8882042F08002BD
+S31508003498C3F88820D3F8882022F08002C3F8882049
+S315080034A80020704703F51053D3F8882042F4807239
+S315080034B8C3F88820D3F8882022F48072C3F88820B5
+S315080034C80020704703F50053D3F8882042F40072A9
+S315080034D8C3F88820D3F8882022F40072C3F8882015
+S315080034E80020704703F5E053D3F8882042F4806239
+S315080034F8C3F88820D3F8882022F48062C3F8882085
+S3150800350800207047000002580004025800080258B4
+S31508003518000C0258001002580014025800180258E5
+S31508003528001C025800200258002402580028025895
+S31508003538F0B40C6894FAA4F4B4FA84F42EE08E680D
+S31508003548826803FB03F505EB450722EA070205FB34
+S3150800355806F52A4382600E68CD68426822EA0602A2
+S3150800356805FB06F52A43426024E0466A1B0A03FB64
+S3150800357803F707FB03F707FB03F3C3EB031726EA6F
+S3150800358807074E6903FB06F33B4343624B68066825
+S31508003598324005FB03F31343036001340B6833FA1F
+S315080035A804F227D00122A2401340F6D04A68013A0D
+S315080035B8012AC4D90F69C66803FB03F505EB45025A
+S315080035C8D243164005FB07F73E43C6604E68022EEF
+S315080035D8DCD1FF2BC9D8066A05FB03F707FB03F3FB
+S315080035E8C3EB031726EA07074E6903FB06F33B43B3
+S315080035F80362CBE70020F0BC704700002A4A13682C
+S3150800360843F001031360284B1B6813F0040F1AD103
+S315080036180023002BF7D0244B00221A611968234A85
+S315080036280A401A60204B1B6813F0007F0DD001234F
+S31508003638002BF7D11C4B1B6813F0006F07D001232A
+S31508003648002BF7D107E00123E3E70023F0E700237F
+S31508003658F6E7002333B1144B1B6813F0005FF8D064
+S315080036680123F7E7104B00229A61DA611A621049BA
+S3150800367899621049D962104919635A639963DA63DA
+S3150800368819645A64196821F4802119601A66996EB2
+S3150800369840F2FF720A439A66D3F8D02042F4803281
+S315080036A8C3F8D020704700BF0044025845EDF6EA33
+S315080036B8000202020000FF018002010107EE900ADB
+S315080036C8F8EE676A07EE901AF8EE677A86EEA77A32
+S315080036D807EE902AF8EE677A06EE903AF8EE666AEA
+S315080036E89FED096A66EE866A77EEA67A27EE277A46
+S315080036F8DDED007AF8EE677AC7EE276AFCEEE67A19
+S3150800370817EE900A704700BF000000392DE9F0410E
+S3150800371882B04E4B9B6A03F00303012B70D0002B33
+S315080037285ED0022B77D000260023036043608360AF
+S31508003738464B9D6AC5F305151A6BC2F30802541C55
+S31508003748DB6A13F0010F77D00123002B76D03F4BA5
+S315080037585F6BC7F3CC07002D3FD03C4BDB6A13F4ED
+S31508003768803F6DD0012380466BB1384B1B6BC3F382
+S315080037784623013300933B46224629463046FFF73F
+S315080037889DFFC8F80000314BDB6A13F4003F59D097
+S3150800379801236BB12D4B1B6BC3F30643013300930F
+S315080037A83B46224629463046FFF788FFC8F80400F4
+S315080037B8264BDB6A13F4802F46D001236BB1234BC3
+S315080037C81B6BC3F30663013300933B46224629461F
+S315080037D83046FFF773FFC8F8080002B0BDE8F08165
+S315080037E81A4B1B6813F0040F08D00123F3B1174BC3
+S315080037F81B68C3F3C103164EDE4095E70023F5E7B9
+S31508003808124B1B6813F4807F03D0012383B9002663
+S315080038188AE70023FAE70D4B1B6813F4003F03D029
+S3150800382801233BB900267FE70023FAE700267BE752
+S31508003838084E79E7084E77E7002386E700278AE7E0
+S31508003848002390E70023A4E70023B7E700440258BB
+S315080038580090D00300093D0000127A002DE9F041D6
+S3150800386882B04E4B9B6A03F00303012B70D0002BE2
+S315080038785ED0022B77D0002600230360436083605E
+S31508003888464B9D6AC5F305359A6BC2F30802541C64
+S31508003898DB6A13F0100F77D00123002B76D03F4B45
+S315080038A8DF6BC7F3CC07002D3FD03C4BDB6A13F41C
+S315080038B8002F6DD0012380466BB1384B9B6BC3F341
+S315080038C84623013300933B46224629463046FFF7EE
+S315080038D8F5FEC8F80000314BDB6A13F4801F59D08F
+S315080038E801236BB12D4B9B6BC3F30643013300933E
+S315080038F83B46224629463046FFF7E0FEC8F804004C
+S31508003908264BDB6A13F4001F46D001236BB1234B01
+S315080039189B6BC3F30663013300933B46224629464D
+S315080039283046FFF7CBFEC8F8080002B0BDE8F081BC
+S315080039381A4B1B6813F0040F08D00123F3B1174B71
+S315080039481B68C3F3C103164EDE4095E70023F5E767
+S31508003958124B1B6813F4807F03D0012383B9002612
+S315080039688AE70023FAE70D4B1B6813F4003F03D0D8
+S3150800397801233BB900267FE70023FAE700267BE701
+S31508003988084E79E7084E77E7002386E700278AE78F
+S31508003998002390E70023A4E70023B7E7004402586A
+S315080039A80090D00300093D0000127A002DE9F04185
+S315080039B882B04F4B9B6A03F00303012B72D0002B8E
+S315080039C860D0022B79D00026002303604360836009
+S315080039D8474B9D6AC5F305551A6CC2F30802541C71
+S315080039E8DB6A13F4807F79D00123002B78D0404B0B
+S315080039F85F6CC7F3CC07002D18BF002E3FD03C4B91
+S31508003A08DB6A13F4800F6DD0012380466BB1384BFF
+S31508003A181B6CC3F34623013300933B4622462946CB
+S31508003A283046FFF74BFEC8F80000314BDB6A13F443
+S31508003A38000F59D001236BB12D4B1B6CC3F30643FA
+S31508003A48013300933B46224629463046FFF736FEA1
+S31508003A58C8F80400264BDB6A13F0807F46D001239A
+S31508003A686BB1234B1B6CC3F30663013300933B46C8
+S31508003A78224629463046FFF721FEC8F8080002B054
+S31508003A88BDE8F0811A4B1B6813F0040F08D0012310
+S31508003A98F3B1174B1B68C3F3C103164EDE4093E711
+S31508003AA80023F5E7124B1B6813F4807F03D0012324
+S31508003AB883B9002688E70023FAE70D4B1B6813F439
+S31508003AC8003F03D001233BB900267DE70023FAE728
+S31508003AD8002679E7084E77E7084E75E7002384E756
+S31508003AE8002788E7002390E70023A4E70023B7E721
+S31508003AF8004402580090D00300093D0000127A00DD
+S31508003B08154B1B6903F03803182B0ED8DFE803F0AA
+S31508003B180F0D0D0D0D0D0D0D210D0D0D0D0D0D0DA9
+S31508003B28160D0D0D0D0D0D0D1800002070470A4BCA
+S31508003B381B68C3F3C1030948D8407047084870474B
+S31508003B4800B585B001A8FFF7E1FD019805B05DF855
+S31508003B5804FB0448704700BF004402580090D0038D
+S31508003B6800127A0000093D00044B9B6903F00F0315
 S31508003B78034AD35C03F01F03D84070470044025831
-S31508003B88FC5E0008044BDB69C3F30223034AD35CD3
-S31508003B9803F01F03D840704700440258FC5E00082B
-S31508003BA800B585B0C2B2574BD358020EC0F30421EC
-S31508003BB88A401340CB4040EA0340534B984228D0EA
-S31508003BC831D8A3F58133A3F58073984263D019D801
-S31508003BD8A3F5803398424ED003F54073984231D105
-S31508003BE8FFF780FF494B9B69C3F30323484AD35C15
-S31508003BF803F01F03D840FFF7A9FFFFF7C3FF05B077
-S31508003C085DF804FB434B984245D003F57D4398423B
-S31508003C1818D13E4B1B6813F0005F4CD00123002BCC
-S31508003C284BD10020EBE73C4B98424DD00CD93B4B87
-S31508003C38984256D003F54073984252D0A3F580337C
-S31508003C48984241D00020DAE7A3F58033984203D09A
-S31508003C5803F540739842F5D12C4B1B6813F0040FF3
-S31508003C6830D00123002B4AD0284B1B68C3F3C10365
-S31508003C782B48D840C3E7FFF735FF244B9B69C3F3A6
-S31508003C880323234AD35C03F01F03D840FFF75EFFDC
-S31508003C98FFF76AFFB3E71D4B1B6813F0006F03D0E5
-S31508003CA801231BB90020AAE70023FAE701A8FFF7B2
-S31508003CB8C7FD0298A3E70023B1E701A8FFF768FE46
-S31508003CC802989CE70023CDE7104B1B6813F4807F06
-S31508003CD803D001231BB1134891E70023FAE7002014
-S31508003CE88DE70A4B1B6F13F0020F04D0012323B18B
-S31508003CF84FF4004083E70023F9E700207FE7002018
-S31508003D087DE700BF4C4402580803020700440258DE
-S31508003D18FC5E0008080301070800040708000507F1
-S31508003D280090D00300093D0038B5036813F0010F69
-S31508003D383CD00123002B40F08E800D4604460368CC
-S31508003D48464A1A408B6809690B4369690B43E9694E
-S31508003D580B4313430360EB68426822F4405213434B
-S31508003D684360AB69826822F44072134383603C4B14
-S31508003D7898421DD03B4B98421ED03B4B98421FD0C9
-S31508003D883A4B984220D03A4B984221D0394B984220
-S31508003D9822D0394B984223D0384B984224D0002059
-S31508003DA800284ED06A681ABB01204BE00023C1E7F9
-S31508003DB83348FFF7F5FEF3E73248FFF7F1FEEFE77A
-S31508003DC83048FFF7EDFEEBE72E48FFF7E9FEE7E791
-S31508003DD82C48FFF7E5FEE3E72948FFF7E1FEDFE7AA
-S31508003DE82848FFF7DDFEDBE72648FFF7D9FED7E7C1
-S31508003DF82B68E9690B2B2CD8B1F5004F0DD0DBB22F
-S31508003E08214951F82330B0FBF3F303EB5203B3FB14
-S31508003E18F2F39BB2E360002014E0DBB21A4951F8CA
-S31508003E282330B0FBF3F0530803EB4000B0FBF2F382
-S31508003E384FF6F0721A40C3F342031343E3600020B7
-S31508003E4800E00120E26A22F00F022B881343E3629E
-S31508003E5838BD0020F6E7012038BD00BFF369FFEF3B
-S31508003E68001001400044004000480040004C004053
-S31508003E78005000400014014000780040007C0040D3
-S31508003E8808030007080000070C5F00080023013331
-S31508003E980C4A934211D80269002AF8DA036943F0F2
-S31508003EA80103036100230133064A934207D80269CE
-S31508003EB812F0010FF7D1002070470320704703203E
-S31508003EC8704700BF400D030084B010B5044603A828
-S31508003ED880E80E00089B012B0DD0E36843F04003E9
-S31508003EE8E3602046FFF7D2FF0C9B13BBA36B43F492
-S31508003EF88033A36311E0A36B23F48033A363E268DA
-S31508003F08134B1340E360E36823F44013E3600F9B05
-S31508003F18012B09D02046FFF7B9FF069B012B0DD0C8
-S31508003F28BDE8104004B07047E36843F48013E360C3
-S31508003F38F0E7A36B23F48033A363EEE7A36843F0A3
-S31508003F480603A360A36843F02003A360E8E700BF5D
-S31508003F58BFFFBDFF022A0AD00921C26822F470529F
-S31508003F68C260C36843EA8123C36000207047274BB1
-S31508003F780B44274A934239D9264B0B44264A93427F
-S31508003F8836D9264B0B44264A934233D9254B0B443C
-S31508003F9802F5C332A03293422ED9234B0B44234A47
-S31508003FA893422BD9224B0B4402F5922202F57872DA
-S31508003FB8934225D91F4B0B4402F5C32202F52072FA
-S31508003FC893421FD91C4B0B4402F5B71202F55872D7
-S31508003FD8934219D9194B0B4402F5122202F5F862D5
-S31508003FE8934201D90621B8E70721B6E70F21B4E7B6
-S31508003FF80E21B2E70D21B0E70C21AEE70B21ACE79D
-S315080040080A21AAE70921A8E70821A6E7405327FFB6
-S31508004018FF340C00401E1BFF3F420F0000DC0BFF5D
-S315080040287F4F1200808CF9FE60B6E5FE5FE3160046
-S3150800403800D3CEFEC05BB3FE00CA91FEE05459FE1B
-S31508004048836843F00103836000207047836823F080
-S31508004058010383600020704708B5C36823F0C0438E
-S31508004068C360012909D069B9C36843F08043C360AE
-S315080040783220FDF749FB002008BDC36843F000530A
-S31508004088C360F5E7012008BD890141F020010161F7
-S3150800409800230133054A934205D8026912F0200F16
-S315080040A8F7D1002070470320704700BF400D030072
-S315080040B81023036100230133054A934205D8026990
-S315080040C812F0100FF7D1002070470320704700BF81
-S315080040D8400D0300D0F800381943C0F8001800202E
-S315080040E87047000084B02DE9F041044607A880E827
-S315080040F80E002546002306E003F1400204EB82027F
-S315080041080021516001330E2BF6D9119BA3BBD4F8B5
-S31508004118043843F00203C4F80438A36B23F40013E5
-S31508004128A363236843F040032360236843F08003AE
-S3150800413823600023C4F8003E04F50066D4F8003866
-S31508004148C4F800380C9B012B1BD003212046FFF727
-S31508004158C1FF10212046FFF797FF804608B14FF0A8
-S3150800416801082046FFF7A4FF08B14FF0010800230D
-S3150800417833617361F3611BE0A36B43F40013A36314
-S31508004188D7E7099B23B900212046FFF7A3FFE0E7F5
-S3150800419801212046FFF79EFFDBE7C3B94FF0006011
-S315080041A8C2F8000900220A614FF67F328A60013395
-S315080041B807998B4210D205EB431202F51061D2F823
-S315080041C800090028E9DB0020C2F80009EAE74FF0F1
-S315080041D89040C2F80009E5E700230AE0BBB14FF0B2
-S315080041E89047C2F8007B002202614FF67F32826050
-S315080041F801338B4210D205EB431202F53060D2F830
-S31508004208007B002FEADB0027C2F8007BEBE74FF0BC
-S315080042180067C2F8007BE6E7336923F480733361E5
-S315080042280023A3616FF0804363610A9B1BB9A369E6
-S3150800423843F01003A361A2690A4B1343A3610D9BBC
-S315080042481BB1A36943F00803A361119B012B04D092
-S315080042584046BDE8F04104B07047A269024B1343D3
-S31508004268A361F5E700383C8004000040D0F8083818
-S3150800427813F0060305D0062B18BF022B03D102201C
-S315080042887047002070470F207047000070B40B78FD
-S315080042984A78012A20D0D0F81C2803F00F060124F2
-S315080042A8B44042EA0442C0F81C2800EB4310D0F890
-S315080042B8003B13F4004F0CD1D0F8002B8B68C3F3DE
-S315080042C80A03C97843EA81431343134A1A43C0F8D1
-S315080042D8002B002070BC7047D0F81C4803F00F0666
-S315080042E8B24092B22243C0F81C2800EB4310D0F81B
-S315080042F8002912F4004FECD1D0F800498A68C2F3B5
-S315080043080A02C97842EA814242EA83532343024AA7
-S315080043181A43C0F80029DCE70080001070B40C784E
-S315080043284B78012B1FD0D0F83C5804F00F06012211
-S3150800433802FA06F625EA0645C0F83C58D0F81C588D
-S31508004348097801F00F018A4025EA0242C0F81C28BC
-S3150800435800EB4410D0F8002B124B1340C0F8003B72
-S31508004368002070BC7047D0F83C6804F00F0203FAC6
-S3150800437802F292B226EA0202C0F83C28D0F81C28B3
-S31508004388097801F00F018B409BB222EA0303C0F8B3
-S315080043981C3800EB4410D0F80029034B1340C0F82A
-S315080043A80039DDE70078F3EF007833EC70B40B7862
-S315080043B84C78012C24D000EB431000F530631D69B6
-S315080043C83E4C2C401C611D693D4C2C401C614C69B7
-S315080043D80CB18C684C611C6944F400241C611C6986
-S315080043E88D68C5F312052C431C61012A61D0D0F8E3
-S315080043F8003B43F00443C0F8003B002070BC7047FC
-S315080044084C695CBB00EB4314D4F810692C4D354055
-S31508004418C4F81059D4F8105945F40025C4F81059A9
-S31508004428D4F81069254D3540C4F81059012A31D0F9
-S3150800443800EB4313D3F8002942F00442C3F80029D5
-S315080044484B69002BD9D0D0F83428097801F00F0425
-S315080044580121A1400A43C0F83428CEE700EB4314EB
-S3150800446804F510642669154D354025612669144DED
-S31508004478354025614E698D68AE4200D94D6125697A
-S3150800448845F40025256125694E69C6F312063543A4
-S315080044982561CBE70A691AB100EB4311C1F814295B
-S315080044A800EB4310D0F8002942F00442C0F800296E
-S315080044B8A3E7CA68002A9AD05A6198E70000F8FF65
-S315080044C8FFFF07E070B49DF80C4064B903339E08F3
-S315080044D807E000EB023303F5805351F8045B1D60CF
-S315080044E80134B442F5D3002070BC7047F0B583B0E8
-S315080044F80C784B78012B29D000EB441404F530636B
-S315080045081E697D4D35401D611E697C4D35401D610E
-S315080045184D69002D40F0C1801D698E68C6F31206E4
-S3150800452835431D611D6945F400251D61012A00F002
-S31508004538C980CB78012B00F0CB80D4F8003B43F038
-S315080045480443C4F8003B002003B0F0BD4B6973BBB5
-S3150800455800EB4413D3F81069684D3540C3F8105971
-S31508004568D3F8105945F40025C3F81059D3F810693B
-S31508004578614D3540C3F81059012A4AD000EB441456
-S31508004588D4F8003943F00443C4F80039CB78012B32
-S3150800459868D04B69002BD6D0D0F834380A7802F0A0
-S315080045A80F0101228A401343C0F83438CBE700EBE1
-S315080045B84413D3F81069504D3540C3F81059D3F849
-S315080045C810694E4D3540C3F81059D3F810694D692E
-S315080045D88F683D44013DB5FBF7F5494F07EAC545E0
-S315080045E83543C3F81059D3F810594E69C6F312065D
-S315080045F83543C3F8105903F51063CD78012DBBD19F
-S315080046081D6925F0C0451D611D6945F000551D61E8
-S31508004618B2E70B691BB100EB4412C2F81439CB7820
-S31508004628012B08D000EB4414D4F8003943F00443AE
-S31508004638C4F8003987E7D0F8083813F4807F08D11A
-S3150800464800EB4412D2F8003943F00053C2F8003997
-S31508004658E8E700EB4412D2F8003943F08053C2F871
-S315080046680039DFE7D0F8083813F4807F0ED1D4F87C
-S31508004678003943F00053C4F8003914460B46C96894
-S315080046881A789B8A0094FFF71DFF5CE7D4F800396F
-S3150800469843F08053C4F80039EFE78E683544013D86
-S315080046A8B5FBF6F51E69164F07EAC5473E431E6170
-S315080046B81F698E68ADB206FB05F5C5F312053D43BD
-S315080046C81D6133E7CA68002A3FF433AF5A6130E7F9
-S315080046D8D0F8083813F4807F06D1D4F8003B43F0A5
-S315080046E80053C4F8003B28E7D4F8003B43F080534E
-S315080046F8C4F8003B21E700BF0000F8FFFFFF07E00A
-S315080047080000F81F03329208002393420CD210B413
-S3150800471800F58054246841F8044B01339342F7D3D3
-S3150800472808465DF8044B7047084670470B784A7880
-S31508004738012A14D000EB4310D0F8002B002A06DB18
-S315080047482BB1D0F8003B23F08043C0F8003BD0F8E3
-S31508004758003B43F40013C0F8003B0020704700EB09
-S315080047684310D0F80029002A06DB2BB1D0F8003907
-S3150800477823F08043C0F80039D0F8003943F4001311
-S31508004788C0F80039E9E70B784A78012A0ED000EB19
-S315080047984310D0F8003B23F40013C0F8003BCB784D
-S315080047A8023BDBB2012B15D90020704700EB4310FA
-S315080047B8D0F8003923F40013C0F80039CB78023B47
-S315080047C8DBB2012BF0D8D0F8003943F08053C0F893
-S315080047D80039E9E7D0F8003B43F08053C0F8003BBE
-S315080047E8E2E738B505460446002208E004EB42131A
-S315080047F84FF67F31C3F80819C3F8081B01320E2A89
-S31508004808F4D90022C5F81028C5F81428C5F81C28B4
-S315080048182846FFF74DFC034608B1184638BD10214F
-S315080048282846FFF731FC0346F7E7D0F8003823F4A3
-S31508004838FE63C0F80038D0F80038090101F4FE61B3
-S315080048480B43C0F800380020704708B5D0F804387C
-S3150800485823F00203C0F804380320FCF755FF0020AC
-S3150800486808BD08B5D0F8043843F00203C0F8043880
-S315080048780320FCF749FF002008BD426980691040FB
-S315080048887047D0F8183800F50060C0691840000C61
-S315080048987047D0F8183800F50060C069184080B22B
-S315080048A8704700EB4111D1F8082B00F50060406904
-S315080048B81040704710B4D0F81028D0F8343801F0F2
-S315080048C80F04E340DB01DBB2134300EB4111D1F8D7
-S315080048D8080918405DF8044B7047406900F0010064
-S315080048E870470000D0F80029054B1340C0F8003976
-S315080048F8D0F8043843F48073C0F8043800207047A9
-S3150800490800F8FFFF10B4046C154B9C4203D9D0F885
-S31508004918003B002B16DB0024C0F8104BD0F8104BD0
-S3150800492844F40024C0F8104BD0F8104B44F018048F
-S31508004938C0F8104BD0F8104B44F0C044C0F8104BE0
-S31508004948012903D000205DF8044B7047C0F8142BE2
-S31508004958D0F8003B43F08023C0F8003BF2E700BFDD
-S315080049680A30544F014B1860704700BF08000020F2
-S3150800497898B108B50346D0F8B40210B10020C3F8B8
-S31508004988B40209B1C3F8B0121846012380F89C325C
-S31508004998027001F051F8002008BD0220704710B5D2
-S315080049A80446012380F89C32D0F8B4325B68017952
-S315080049B89847204601F0B2F8204601F09FF80020F3
-S315080049C810BD19B1C0F8B41200207047022070470C
-S315080049D808B501F09BF8002008BD08B5D0F8B43230
-S315080049E823B11B68984718B1022008BD022008BDE4
-S315080049F8002008BD08B5D0F8B4325B68984700208F
-S31508004A0808BD38B5044600F52A75284600F04EF95B
-S31508004A180123C4F89432B4F8AE32C4F8983294F83C
-S31508004A28A81201F01F03012B0ED03BB1022B10D0A0
-S31508004A3801F08001204601F08CF803E0294620465B
-S31508004A4800F001FB002038BD2946204600F02FFB60
-S31508004A58F8E72946204600F05AFBF3E738B5044636
-S31508004A68A9BB1046D4F89432032B03D0052B25D0BE
-S31508004A78002038BDD4F86031D4F8642193420DD9A2
-S31508004A889B1AC4F860319A4206D99AB2014620465A
-S31508004A9800F07AFC002038BD92B2F7E7D4F8B432B1
-S31508004AA81B691BB194F89C22032A04D0204600F0FF
-S31508004AB873FC002038BD20469847F7E70025C4F858
-S31508004AC894522946204601F044F8284638BD0A4635
-S31508004AD8D0F8B4329B694BB190F89C12032901D0DF
-S31508004AE8022038BD11469847002038BD022038BD37
-S31508004AF810B50446002956D11046D4F89432022B2C
-S31508004B0809D0002B18BF042B44D094F8A032012BE7
-S31508004B1845D0002010BD236A626A93421BD8E16912
-S31508004B28B1FBF2F302FB13132BB98A4203D8D4F864
-S31508004B38983299421DD3D4F8B432DB681BB194F87D
-S31508004B489C22032A23D08021204601F002F8204619
-S31508004B5800F02DFCD9E79A1A226292B2014620463D
-S31508004B6800F00AFC00231A461946204601F011F8F7
-S31508004B78CBE700221146204600F0FEFB0021C4F8C8
-S31508004B8898120B460A46204601F003F8BDE7204668
-S31508004B989847D8E78021204600F0DBFFB5E70020D4
-S31508004BA884F8A00210BD0A46D0F8B4325B694BB146
-S31508004BB890F89C12032901D0022010BD1146984787
-S31508004BC8002010BD022010BD70B5044640230022FF
-S31508004BD8114600F0ABFF0125C4F858514026C4F821
-S31508004BE86461334600228021204600F09FFFA561B4
-S31508004BF8666284F89C520023C4F894326360C4F849
-S31508004C08A432D4F8B8322BB1D4F8B4325B68002190
-S31508004C1820469847002070BD01740020704790F818
-S31508004C289C3280F89D32042380F89C320020704715
-S31508004C3890F89C32042B01D00020704790F89D32DA
-S31508004C4880F89C32F8E708B590F89C32032B01D017
-S31508004C58002008BDD0F8B432DB69002BF8D0984795
-S31508004C68F6E700207047002070470020704708B50F
-S31508004C78012280F89C22D0F8B4225268017990471C
-S31508004C88002008BD002302E00133DBB201300278B8
-S31508004C98002AF9D11846704708B54B88012B00D069
-S31508004CA808BDC0F8A43200F077FBF9E70B78037063
-S31508004CB84B7843708B78CA7803EB022343800B79C9
-S31508004CC84A7903EB022383808B79CA7903EB02239B
-S31508004CD8C380704710B50446802100F03AFF0021CA
-S31508004CE8204600F036FF10BD30B583B005460C46A1
-S31508004CF80023ADF806304A88130A013B062B00F252
-S31508004D08C280DFE803F0041A30C0C09EAE00D0F8AF
-S31508004D18B0321B680DF10601007C9847002353B989
-S31508004D28BDF806201AB1E388002B40F0B280E38864
-S31508004D38002B00F0B88003B030BD037C4BB9D0F81F
-S31508004D48B4329B6A0DF10600984702234370002384
-S31508004D58E5E7D0F8B432DB6A0DF106009847022376
-S31508004D6843700023DBE7D2B2052A64D8DFE802F0ED
-S31508004D78031323334353D0F8B0325B682BB10DF1D4
-S31508004D880601007C98470023C9E72146FFF7A2FFDA
-S31508004D9801230020C3E7D0F8B0329B682BB10DF188
-S31508004DA80601007C98470023B9E72146FFF792FFDA
-S31508004DB801230020B3E7D0F8B032DB682BB10DF138
-S31508004DC80601007C98470023A9E72146FFF782FFDA
-S31508004DD801230020A3E7D0F8B0321B692BB10DF1E7
-S31508004DE80601007C9847002399E72146FFF772FFDA
-S31508004DF80123002093E7D0F8B0325B692BB10DF197
-S31508004E080601007C9847002389E72146FFF762FFD9
-S31508004E180123002083E7D0F8B0329B692BB10DF146
-S31508004E280601007C9847002379E72146FFF752FFD9
-S31508004E380123002073E72146FFF74CFF01230020D2
-S31508004E486DE7037C3BB9D0F8B4325B6B0DF106000D
-S31508004E589847002363E72146FFF73CFF0123002014
-S31508004E685DE7037C4BB9D0F8B4321B6B0DF106002D
-S31508004E78984707234370002351E72146FFF72AFF7F
-S31508004E88012300204BE72146FFF724FF01230020D2
-S31508004E9845E79A4228BF1A46ADF80620014628462D
-S31508004EA800F05DFA43E7284600F076FA43E738B596
-S31508004EB804468B88F3B9CB88E3B94B887F2B19D876
-S31508004EC803F07F0590F89C32032B0CD080F89E528D
-S31508004ED8294600F04EFE204600F05EFA35B1022358
-S31508004EE884F89C3238BDFFF7F5FE38BD012384F8EF
-S31508004EF89C3238BD2046FFF7EDFE38BD38B5044666
-S31508004F080D468978284B197001290ED890F89C32D5
-S31508004F18022B0ED0032B21D02946FFF7DBFE224BA6
-S31508004F2819782046FFF766FD38BD2946FFF7D2FEF1
-S31508004F3838BD81B14160032380F89C32FFF74DFDE7
-S31508004F48022803D0204600F027FA38BD294620460D
-S31508004F58FFF7C0FE38BD00F01FFA38BD89B14368AF
-S31508004F6899421DD0D9B2FFF745FD0F4B19786160F4
-S31508004F782046FFF732FD02280DD0204600F00CFA2D
-S31508004F8838BD022380F89C324160FFF733FD20467E
-S31508004F9800F002FA38BD29462046FFF79BFE38BDC1
-S31508004FA800F0FAF938BD00BF780E002008B5CB889E
-S31508004FB8012B0BD190F89C329BB1022B09D9032BF4
-S31508004FC80FD10122011D00F0CAF908BDFFF782FEBC
-S31508004FD808BD0146002341F8083F012200F0BFF941
-S31508004FE808BDFFF777FE08BD08B590F89C32013B67
-S31508004FF8022B12D8CB88022B0CD10123C360D0F818
-S31508005008A4320BB10323C360022200F10C0100F09D
-S31508005018A6F908BDFFF75EFE08BDFFF75BFE08BDEB
-S3150800502808B590F89C32013B022B09D84B88012B0E
-S3150800503800D008BD0023C0F8A43200F0ADF908BDB9
-S31508005048FFF748FEF5E708B50B7803F06003202B51
-S3150800505805D0402B03D043B1FFF73CFE03E0D0F858
-S31508005068B4329B689847002008BD4B78092B1BD893
-S31508005078DFE803F011171A141A08051A0E0BFFF7BA
-S3150800508833FEF0E7FFF713FFEDE7FFF737FFEAE729
-S31508005098FFF78CFFE7E7FFF7A7FFE4E7FFF7FCFD55
-S315080050A8E1E7FFF7BDFFDEE7FFF714FEDBE738B5F4
-S315080050B805460C460B7803F06003202B05D0402BD9
-S315080050C803D013B1FFF706FE0BE095F89C32013BB7
-S315080050D8022B17D82379012B05D921462846FFF72D
-S315080050E8F9FD002038BDD5F8B4329B682146284614
-S315080050F89847E388002BF4D10028F2D1284600F017
-S315080051084BF9EEE721462846FFF7E4FDE9E738B507
-S3150800511804468A880B7803F06003202B08D0D0B29F
-S31508005128402B05D05BB12046FFF7D4FD002038BDDB
-S31508005138D4F8B4329B6820469847002038BD202BFF
-S3150800514812D04B78012B3AD0002B67D0032B40F0AE
-S31508005158E38094F89C32022B0CD0032B1DD02046F2
-S31508005168FFF7B8FD002038BDD4F8B4329B6820464E
-S31508005178984738BD002818BF802809D00146204618
-S3150800518800F0E7FC8021204600F0E3FC002038BD4B
-S315080051982046FFF79FFD002038BD4B882BB900280D
-S315080051A818BF802801D0CB8823B1204600F0F4F830
-S315080051B8002038BD0146204600F0CBFCF5E794F8F8
-S315080051C89C32022B06D0032B17D02046FFF782FD08
-S315080051D8002038BD002818BF802809D00146204677
-S315080051E800F0B7FC8021204600F0B3FC002038BD4B
-S315080051F82046FFF76FFD002038BD4B88002B40F08E
-S31508005208908010F07F0F04D1204600F0C5F80020E2
-S3150800521838BD0146204600F0A4FCF5E794F89C3210
-S31508005228022B06D0032B2BD02046FFF753FD002070
-S3150800523838BD002818BF802813D112F0800F15D161
-S3150800524800F07F0000EB8000830003F5A871214475
-S31508005258043100250D600222204600F080F8284611
-S3150800526838BD2046FFF736FD002038BD00F07F0020
-S3150800527800EB8000830003F1100121440431E8E7BC
-S3150800528852B2002A20DB00F00F0303EB83039D00CC
-S315080052982544D5F858312BB3002A28DB00F07F02BD
-S315080052A802EB8202930003F5A87525440435802885
-S315080052B818BF002825D100232B600222294620463C
-S315080052C800F04DF8002038BD00F00F0303EB830308
-S315080052D89D002544AB69002BDED12046FFF7FAFC72
-S315080052E8002038BD2046FFF7F5FC002038BD00F041
-S315080052F87F0202EB8202930003F110052544043568
-S31508005308D5E70146204600F0D3FB10B101232B60F0
-S31508005318D3E700232B60D0E72046FFF7DBFC002005
-S3150800532838BD002038BDC8B170B50D4616460446C6
-S31508005338FFF7A8FC013040003080287003236B7003
-S31508005348022307E05A1CD2B20134E9540233DBB20D
-S315080053580021A95421780029F4D170BD704710B5E9
-S3150800536813460222C0F89422C36103620A46002142
-S3150800537800F007FC002010BD08B513460A460021B0
-S3150800538800F0FFFB002008BD08B513460A460021B1
-S3150800539800F0FFFB002008BD08B50423C0F89432C6
-S315080053A800231A46194600F0ECFB002008BD08B58C
-S315080053B80523C0F8943200231A46194600F0E9FB7B
-S315080053C8002008BD184AD2F8883043F47003C2F89A
-S315080053D88830164B1A6842F001021A6000221A61D0
-S315080053E818681349014019609A61DA611A629A6263
-S315080053F8DA621A635A639A63DA631A645A6419682A
-S3150800540821F4802119601A660A4B1A680A4B134058
-S31508005418B3F1005F02D20122084B1A604FF000620E
-S31508005428014B9A60704700BF00ED00E0004402583F
-S315080054387FEDF6EA0010005C0000FFFF08810051C6
-S3150800544808B55B4A136823F00F0343F00403136097
-S31508005458136803F00F03042B03D067215548FBF79D
-S315080054686FFD554AD36823F0070343F00203D36058
-S31508005478936943F440439361504B1A6842F4802277
-S315080054881A601A6842F480321A604C4B1B6813F487
-S31508005498003F40F089800023002BF6D0474B9A6AD4
-S315080054A822F0030242F002029A62DA6A42F4803271
-S315080054B8DA62DA6A42F40032DA62DA6A22F00C024E
-S315080054C842F00402DA62DA6A22F00202DA629A6AB8
-S315080054D822F47C7242F040029A621A6B38491140EB
-S315080054E840F2DF120A431A631A6B22F47E4242F428
-S315080054F800721A631A6B22F4FE0242F498121A63AF
-S315080055081A6B22F0FE4242F080721A631A6842F059
-S3150800551880721A60294B1B6813F0007F46D1002356
-S31508005528002BF7D0254B9A6922F00F0242F00802A1
-S315080055389A611A6922F0070242F003021A619A6907
-S3150800554822F470629A619A6922F00F0242F0080200
-S315080055589A61DA6922F0700242F04002DA61DA6981
-S3150800556822F4E06242F48062DA619A6922F07002F3
-S3150800557842F040029A611A6A22F0700242F040022A
-S315080055881A6210490A6822F007020A601A6D22F0A0
-S3150800559840521A655A6D22F4401242F480125A652E
-S315080055A80948FFF7DFF908BD012375E70123B7E7BF
-S315080055B8002000524C5F0008004802580044025870
-S315080055C800FEFFFF5444025800389C1C08B5FCF737
-S315080055D86DF8FFF735FF08BD08B5FFF7F7FFFBF7C6
-S315080055E8FDFCFBF709FDFCE72DE9F0418EB0514CAF
-S315080055F8D4F8F43043F00203C4F8F430D4F8F4309D
-S3150800560803F002030793079BD4F8E03043F001033D
-S31508005618C4F8E030D4F8E03003F001030693069B9B
-S31508005628D4F8E03043F00203C4F8E030D4F8E030A8
-S3150800563803F002030593059BD4F8E03043F004030E
-S31508005648C4F8E030D4F8E03003F004030493049B6C
-S31508005658D4F8E03043F00803C4F8E030D4F8E03072
-S3150800566803F008030393039BD4F8E83043F4802334
-S31508005678C4F8E830D4F8E83003F480230293029B90
-S31508005688D4F8EC3043F48073C4F8EC30D4F8EC3032
-S3150800569803F480730193019B8023089301230993DC
-S315080056A800250A950B950C95234F08A93846FDF74A
-S315080056B831FF4FF40053089309950C9508A91F481C
-S315080056C8FDF728FF4FF44078CDF820800226099682
-S315080056D80A950B950C9507230D9308A91848FDF705
-S315080056E819FFCDF8208009960A960B950C9509237B
-S315080056F80D9308A93846FDF70DFF4FF4C0530893D4
-S31508005708099603230A930B950C950A230D9308A962
-S315080057180C48FDF7FFFED4F8D83043F00063C4F808
-S31508005728D830D4F8D83003F000630093009B0EB045
-S31508005738BDE8F081004402580004025800080258DF
-S31508005748000C02580000025810B5FDF749FF214C15
-S315080057584FF40003A3612048FDF7F0FD1F48FDF745
-S31508005768EDFD2046FDF7EAFD1D48FDF7E7FD1D4B53
-S31508005778D3F8D82022F00062C3F8D820D3F8EC2052
-S3150800578822F48072C3F8EC20D3F8E82022F48022A9
-S31508005798C3F8E820D3F8E02022F00802C3F8E0208E
-S315080057A8D3F8E02022F00402C3F8E020D3F8E0207A
-S315080057B822F00202C3F8E020D3F8E02022F0010222
-S315080057C8C3F8E020D3F8F42022F00202C3F8F42044
-S315080057D810BD00BF00040258000C02580008025801
-S315080057E80000025800440258DFF834D0002103E0CC
-S315080057F80C4B5B58435004310B480C4B42189A42E1
-S31508005808F6D30B4A02E0002342F8043B094B9A42B6
-S31508005818F9D3FFF7D7FD00F055FAFFF7DDFE704715
-S3150800582800000220B45F000800000020C400002021
-S31508005838C4000020E4140020FEE7000020230380AB
-S3150800584800487047480000200A230380004870472C
-S315080058586800002008B590F89C32032B01D0002078
-S3150800586808BDFBF70DFBFAE708B5FBF709FB0020AF
-S3150800587808BD08B50846FBF737FB002008BD000039
-S3150800588808B50B7813F0600F06D14B780A2B14D09D
-S315080058980B2B17D0062B01D0002008BD4B881B0AF6
-S315080058A8212B04D00B491722FFF759FDF4E7CA88BC
-S315080058B8172A28BF17220849F6E701220749FFF7DA
-S315080058C84EFDE9E78B7813B9044A1360E4E7FFF756
-S315080058D801FAE1E7510000205A0000207C0E00205A
-S315080058E810B50446812100F02CF90121204600F064
-S315080058F828F9002010BD000010B5044640230222EE
-S31508005908812100F013F9402302220121204600F0E4
-S315080059180DF94023034A0121204600F03AF90020F0
-S3150800592810BD00BF9C0E0020004870479C0E002042
-S3150800593808B500F57171D0F80404FFF762F808BDD8
-S3150800594808B5C1EBC10293000344D3F80822D0F87E
-S315080059580404FFF783F808BD08B5C1EBC102930034
-S3150800596803449A6CD0F80404FFF7C2F808BD08B5D2
-S31508005978D0F80404FFF767F908BD000010B5044617
-S31508005988C3683BB1022B0FD091210848FBF7D8FA18
-S31508005998012100E00021D4F80404FFF73DF9D4F802
-S315080059A80404FFF711F910BD0121F4E7585F000850
-S315080059B810B50446D0F80404FFF731F92268D2F87E
-S315080059C8003E43F00103C2F8003E236A23B1044AA5
-S315080059D8136943F006031361FBF7D8FD10BD00BF32
-S315080059E800ED00E010B50446FBF7D1FDD4F8040431
-S315080059F8FFF71EF910BD08B5D0F80404FFF733F908
-S31508005A0808BD08B5D0F80404FFF72BF908BD10B58A
-S31508005A1804460120FBF7B9FDD4F80404FFF725F975
-S31508005A2810BD10B504460020FBF7AFFDD4F80404F2
-S31508005A38FFF71DF910BD000003780BB10020704769
-S31508005A4810B503461748C0F80434C3F8C002164B05
-S31508005A580360092343600222C2600023036182614E
-S31508005A680122C261036243628362C3620363FCF76D
-S31508005A7867FD80B90B4C80212046FDF722FB4022A2
-S31508005A8800212046FDF7F9FA802201212046FDF774
-S31508005A98F4FA002010BD4FF493710448FBF750FA46
-S31508005AA8E8E700BFDC0E002000000840585F000841
-S31508005AB8D0F8C03211F0800F08D101F07F01C1EB90
-S31508005AC8C1018A00134493F8FE01704701F07F016B
-S31508005AD8C1EBC1018A00134493F83E00704708B524
-S31508005AE8D0F8C002FDF71EFA08BD18B1022803D07F
-S31508005AF802207047002070470120704708B5D0F883
-S31508005B08C002FCF7F7FDFFF7F0FF08BD08B5D0F8A7
-S31508005B18C002FCF7AEFDFFF7E8FF08BD08B5D0F8E8
-S31508005B28C002FCF7C7FDFFF7E0FF08BD10B51C4625
-S31508005B3813462246D0F8C002FDF74EF9FFF7D5FFFF
-S31508005B4810BD08B5D0F8C002FDF787F9FFF7CDFFF5
-S31508005B5808BD08B5D0F8C002FDF717FAFFF7C5FF64
-S31508005B6808BD08B5D0F8C002FDF750FAFFF7BDFF23
-S31508005B7808BD08B5D0F8C002FDF71AF9FFF7B5FF52
-S31508005B8808BD08B5D0F8C002FDF7D5F9FFF7ADFF8F
-S31508005B9808BD08B5D0F8C002FDF796F9FFF7A5FFC6
-S31508005BA808BD000012230B800048704790000020AB
-S31508005BB804230B8000487047A40000200023934262
-S31508005BC816D230B40BE0373401F8134000015C00F4
-S31508005BD8013400250D550133DBB2934206D2040F72
-S31508005BE8092CF0D8303401F81340EFE730BC704779
-S31508005BF87047000038B50A4B186804331C68043324
-S31508005C081B68C01800D138BD064D0822A91CFFF725
-S31508005C18D5FF042205F112012046FFF7CFFFF2E768
-S31508005C2800E8F11FA800002008B51A230B80FFF723
-S31508005C38E1FF014808BD00BFA800002008B50A46CC
-S31508005C4828B105490548FFF76EFB034808BD024910
-S31508005C580248FFF768FBF8E7E4120020985F000897
-S31508005C6810B5044C0A4621460348FFF75CFB204654
-S31508005C7810BD00BFE4120020885F000808B50A4670
-S31508005C8828B105490548FFF74EFB034808BD0249F0
-S31508005C980248FFF748FBF8E7E4120020685F0008A7
-S31508005CA808B50A4628B105490548FFF73CFB0348E5
-S31508005CB808BD02490248FFF736FBF8E7E412002058
-S31508005CC8705F000870B50D4E0D4CA41BA410002576
-S31508005CD8A54209D10B4E0C4C00F024F8A41BA410BD
-S31508005CE80025A54205D170BD56F8253098470135D7
-S31508005CF8EEE756F8253098470135F2E7AC5F000815
-S31508005D08AC5F0008AC5F0008B05F000810B5431E1A
-S31508005D180A44914200D110BD11F8014B03F8014F0E
-S31508005D28F7E70000F8B500BFF8BC08BC9E46704700
-S31108005D38F8B500BFF8BC08BC9E467047D2
-S31508005D440000000000000000000000000000000041
-S31508005D54000000000100000002000000030000002B
-S31508005D640400000000000000050000000000000018
-S31508005D74000000000000000006000000000000000B
-S31508005D840000000000000000070000002E2E5C2E14
-S31508005D942E5C2E2E5C2E2E5C536F757263655C41E9
-S31508005DA4524D434D375F53544D333248375C636124
-S31508005DB46E2E630005020602060307030803090399
-S31508005DC409040A040B040C040C050D050E050F053D
-S31508005DD40F0610061007100800000208000002004B
-S31508005DE4010100000000040800000200020100008E
-S31508005DF4000006080000020003010000000008086D
-S31508005E04000002000401000000000A080000020065
-S31508005E140501000000000C0800000200060100004D
-S31508005E2400000E0800000200070100000000100828
-S31508005E340000020000020000000012080000020030
-S31508005E44010200000000140800000200020200001B
-S31508005E5400001608000002000302000000001808EB
-S31508005E64000002000402000000001A0800000200F4
-S31508005E740502000000001C080000020006020000DB
-S31508005E8400001E0800000200070200002E2E5C2EE9
-S31508005E942E5C2E2E5C2E2E5C536F757263655C41E8
-S31508005EA4524D434D375F53544D333248375C727302
-S31508005EB43233322E630000002E2E5C2E2E5C2E2EDC
-S31508005EC45C2E2E5C536F757263655C41524D434D6F
-S31508005ED4375F53544D333248375C7573622E63000B
-S31508005EE44F70656E424C5400000102030405060710
-S31508005EF4080C1014182030400000000001020304A6
-S31508005F040102030406070809010000000200000054
-S31508005F140400000006000000080000000A00000053
-S31508005F240C000000100000002000000040000000E3
-S31508005F3480000000000100000000000001020304C4
-S31508005F4401020304060708092E2E5C6D61696E2E8C
-S31508005F54630000002E2E5C757362645F636F6E6661
-S31508005F642E63000044656661756C740057696E5546
-S31508005F7453422042756C6B20496E74657266616380
-S31508005F84650000004F70656E424C54205573657267
-S31508005F940000000057696E5553422042756C6B2009
-S30D08005FA4446576696365000097
-S30908005FACBD0200081C
-S30908005FB0990200083C
-S31508005FB404010000100000000090D0030090D003F4
-S31508005FC401590008E958000889580008000000002B
-S31508005FD400000000715800087B5800085D58000846
-S31508005FE400000000000000000000000045580008FA
-S31508005FF4000000005158000809022000010100C0F1
-S31508006004320904000002FF0000000705810240006F
-S31508006014FF070501024000FF0A06000200000040CF
-S3150800602401000000AD5B0008B95B0008695C000864
-S31508006034455C0008315C0008855C0008A95C00081A
-S315080060441201000200000040501DAC60000201026B
-S3150800605403010000040309041A03000000000000F9
-S31508006064000000000000000000000000000000001E
-S30908006074000000001A
-S705080057F1AA
+S31508003B88185F0008044BDB69C3F30213034AD35CC6
+S31508003B9803F01F03D840704700440258185F00080E
+S31508003BA8044BDB69C3F30223034AD35C03F01F0300
+S31508003BB8D840704700440258185F000800B585B019
+S31508003BC8C2B2574BD358020EC0F304218A40134099
+S31508003BD8CB4040EA0340534B984228D031D8A3F546
+S31508003BE88133A3F58073984263D019D8A3F5803337
+S31508003BF898424ED003F54073984231D1FFF780FFBB
+S31508003C08494B9B69C3F30323484AD35C03F01F0354
+S31508003C18D840FFF7A9FFFFF7C3FF05B05DF804FB17
+S31508003C28434B984245D003F57D43984218D13E4BFD
+S31508003C381B6813F0005F4CD00123002B4BD10020E2
+S31508003C48EBE73C4B98424DD00CD93B4B984256D0A3
+S31508003C5803F54073984252D0A3F58033984241D071
+S31508003C680020DAE7A3F58033984203D003F54073BA
+S31508003C789842F5D12C4B1B6813F0040F30D001235A
+S31508003C88002B4AD0284B1B68C3F3C1032B48D840DE
+S31508003C98C3E7FFF735FF244B9B69C3F30323234A7E
+S31508003CA8D35C03F01F03D840FFF75EFFFFF76AFFF0
+S31508003CB8B3E71D4B1B6813F0006F03D001231BB92C
+S31508003CC80020AAE70023FAE701A8FFF7C7FD02982C
+S31508003CD8A3E70023B1E701A8FFF768FE02989CE767
+S31508003CE80023CDE7104B1B6813F4807F03D001230C
+S31508003CF81BB1134891E70023FAE700208DE70A4B22
+S31508003D081B6F13F0020F04D0012323B14FF40040B0
+S31508003D1883E70023F9E700207FE700207DE700BF57
+S31508003D284C4402580803020700440258185F000862
+S31508003D380803010708000407080005070090D003D0
+S31508003D4800093D0038B5036813F0010F3CD001237C
+S31508003D58002B40F08E800D4604460368464A1A40F2
+S31508003D688B6809690B4369690B43E9690B43134374
+S31508003D780360EB68426822F4405213434360AB6918
+S31508003D88826822F44072134383603C4B98421DD0E4
+S31508003D983B4B98421ED03B4B98421FD03A4B984211
+S31508003DA820D03A4B984221D0394B984222D0394BE9
+S31508003DB8984223D0384B984224D0002000284ED069
+S31508003DC86A681ABB01204BE00023C1E73348FFF7AE
+S31508003DD8F5FEF3E73248FFF7F1FEEFE73048FFF75D
+S31508003DE8EDFEEBE72E48FFF7E9FEE7E72C48FFF775
+S31508003DF8E5FEE3E72948FFF7E1FEDFE72848FFF78E
+S31508003E08DDFEDBE72648FFF7D9FED7E72B68E96921
+S31508003E180B2B2CD8B1F5004F0DD0DBB2214951F840
+S31508003E282330B0FBF3F303EB5203B3FBF2F39BB275
+S31508003E38E360002014E0DBB21A4951F82330B0FBDE
+S31508003E48F3F0530803EB4000B0FBF2F34FF6F072B9
+S31508003E581A40C3F342031343E360002000E001203D
+S31508003E68E26A22F00F022B881343E36238BD00206A
+S31508003E78F6E7012038BD00BFF369FFEF00100140DF
+S31508003E880044004000480040004C004000500040F4
+S31508003E980014014000780040007C00400803000731
+S31508003EA808000007285F0008002301330C4A9342DC
+S31508003EB811D80269002AF8DA036943F00103036195
+S31508003EC800230133064A934207D8026912F0010F04
+S31508003ED8F7D100207047032070470320704700BFBA
+S31508003EE8400D030084B010B5044603A880E80E0008
+S31508003EF8089B012B0DD0E36843F04003E360204696
+S31508003F08FFF7D2FF0C9B13BBA36B43F48033A36361
+S31508003F1811E0A36B23F48033A363E268134B1340C1
+S31508003F28E360E36823F44013E3600F9B012B09D091
+S31508003F382046FFF7B9FF069B012B0DD0BDE81040B8
+S31508003F4804B07047E36843F48013E360F0E7A36BB3
+S31508003F5823F48033A363EEE7A36843F00603A3605C
+S31508003F68A36843F02003A360E8E700BFBFFFBDFFCF
+S31508003F78022A0AD00921C26822F47052C260C368AC
+S31508003F8843EA8123C36000207047274B0B44274A1E
+S31508003F98934239D9264B0B44264A934236D9264B9F
+S31508003FA80B44264A934233D9254B0B4402F5C332B0
+S31508003FB8A03293422ED9234B0B44234A93422BD93A
+S31508003FC8224B0B4402F5922202F57872934225D9C0
+S31508003FD81F4B0B4402F5C32202F5207293421FD9E0
+S31508003FE81C4B0B4402F5B71202F55872934219D9BD
+S31508003FF8194B0B4402F5122202F5F862934201D9CD
+S315080040080621B8E70721B6E70F21B4E70E21B2E77C
+S315080040180D21B0E70C21AEE70B21ACE70A21AAE788
+S315080040280921A8E70821A6E7405327FFFF340C0013
+S31508004038401E1BFF3F420F0000DC0BFF7F4F12009C
+S31508004048808CF9FE60B6E5FE5FE3160000D3CEFE67
+S31508004058C05BB3FE00CA91FEE05459FE836843F07C
+S315080040680103836000207047836823F00103836097
+S315080040780020704708B5C36823F0C043C360012908
+S3150800408809D069B9C36843F08043C3603220FDF795
+S3150800409845FB002008BDC36843F00053C360F5E735
+S315080040A8012008BD890141F020010161002301337F
+S315080040B8054A934205D8026912F0200FF7D1002065
+S315080040C870470320704700BF400D030010230361A3
+S315080040D800230133054A934205D8026912F0100FE6
+S315080040E8F7D1002070470320704700BF400D030032
+S315080040F8D0F800381943C0F80018002070470000A7
+S3150800410884B02DE9F041044607A880E80E00254644
+S31508004118002306E003F1400204EB82020021516005
+S3150800412801330E2BF6D9119BA3BBD4F8043843F0F8
+S315080041380203C4F80438A36B23F40013A3632368A3
+S3150800414843F040032360236843F080032360002379
+S31508004158C4F8003E04F50066D4F80038C4F80038F8
+S315080041680C9B012B1BD003212046FFF7C1FF10210A
+S315080041782046FFF797FF804608B14FF0010820460A
+S31508004188FFF7A4FF08B14FF00108002333617361F4
+S31508004198F3611BE0A36B43F40013A363D7E7099BFA
+S315080041A823B900212046FFF7A3FFE0E701212046AF
+S315080041B8FFF79EFFDBE7C3B94FF00060C2F80009B6
+S315080041C800220A614FF67F328A60013307998B42CB
+S315080041D810D205EB431202F51061D2F8000900283F
+S315080041E8E9DB0020C2F80009EAE74FF09040C2F878
+S315080041F80009E5E700230AE0BBB14FF09047C2F88B
+S31508004208007B002202614FF67F32826001338B42BF
+S3150800421810D205EB431202F53060D2F8007B002F66
+S31508004228EADB0027C2F8007BEBE74FF00067C2F825
+S31508004238007BE6E7336923F4807333610023A361BF
+S315080042486FF0804363610A9B1BB9A36943F01003A7
+S31508004258A361A2690A4B1343A3610D9B1BB1A3690A
+S3150800426843F00803A361119B012B04D04046BDE81F
+S31508004278F04104B07047A269024B1343A361F5E7FE
+S3150800428800383C8004000040D0F8083813F00603CC
+S3150800429805D0062B18BF022B03D102207047002031
+S315080042A870470F207047000070B40B784A78012AC7
+S315080042B820D0D0F81C2803F00F060124B44042EA9F
+S315080042C80442C0F81C2800EB4310D0F8003B13F44E
+S315080042D8004F0CD1D0F8002B8B68C3F30A03C978B2
+S315080042E843EA81431343134A1A43C0F8002B0020B4
+S315080042F870BC7047D0F81C4803F00F06B24092B25B
+S315080043082243C0F81C2800EB4310D0F8002912F401
+S31508004318004FECD1D0F800498A68C2F30A02C97876
+S3150800432842EA814242EA83532343024A1A43C0F8BF
+S315080043380029DCE70080001070B40C784B78012B54
+S315080043481FD0D0F83C5804F00F06012202FA06F6E8
+S3150800435825EA0645C0F83C58D0F81C58097801F0F3
+S315080043680F018A4025EA0242C0F81C2800EB4410CF
+S31508004378D0F8002B124B1340C0F8003B002070BC45
+S315080043887047D0F83C6804F00F0203FA02F292B2BA
+S3150800439826EA0202C0F83C28D0F81C28097801F059
+S315080043A80F018B409BB222EA0303C0F81C3800EBC6
+S315080043B84410D0F80029034B1340C0F80039DDE74C
+S315080043C80078F3EF007833EC70B40B784C78012C4E
+S315080043D824D000EB431000F530631D693E4C2C4091
+S315080043E81C611D693D4C2C401C614C690CB18C68DC
+S315080043F84C611C6944F400241C611C698D68C5F36A
+S3150800440812052C431C61012A61D0D0F8003B43F001
+S315080044180443C0F8003B002070BC70474C695CBB7D
+S3150800442800EB4314D4F810692C4D3540C4F81059DC
+S31508004438D4F8105945F40025C4F81059D4F8106969
+S31508004448254D3540C4F81059012A31D000EB4313DD
+S31508004458D3F8002942F00442C3F800294B69002B17
+S31508004468D9D0D0F83428097801F00F040121A140E1
+S315080044780A43C0F83428CEE700EB431404F5106461
+S315080044882669154D354025612669144D354025613F
+S315080044984E698D68AE4200D94D61256945F40025F7
+S315080044A8256125694E69C6F3120635432561CBE7AA
+S315080044B80A691AB100EB4311C1F8142900EB431035
+S315080044C8D0F8002942F00442C0F80029A3E7CA68D0
+S315080044D8002A9AD05A6198E70000F8FFFFFF07E01C
+S315080044E870B49DF80C4064B903339E0807E000EBE6
+S315080044F8023303F5805351F8045B1D600134B44256
+S31508004508F5D3002070BC7047F0B583B00C784B78AB
+S31508004518012B29D000EB441404F530631E697D4D40
+S3150800452835401D611E697C4D35401D614D69002D5C
+S3150800453840F0C1801D698E68C6F3120635431D61B1
+S315080045481D6945F400251D61012A00F0C980CB784C
+S31508004558012B00F0CB80D4F8003B43F00443C4F8A1
+S31508004568003B002003B0F0BD4B6973BB00EB441356
+S31508004578D3F81069684D3540C3F81059D3F810595F
+S3150800458845F40025C3F81059D3F81069614D35402C
+S31508004598C3F81059012A4AD000EB4414D4F8003954
+S315080045A843F00443C4F80039CB78012B68D04B692B
+S315080045B8002BD6D0D0F834380A7802F00F01012239
+S315080045C88A401343C0F83438CBE700EB4413D3F8D2
+S315080045D81069504D3540C3F81059D3F810694E4D37
+S315080045E83540C3F81059D3F810694D698F683D44AA
+S315080045F8013DB5FBF7F5494F07EAC5453543C3F805
+S315080046081059D3F810594E69C6F312063543C3F83C
+S31508004618105903F51063CD78012DBBD11D6925F016
+S31508004628C0451D611D6945F000551D61B2E70B6956
+S315080046381BB100EB4412C2F81439CB78012B08D009
+S3150800464800EB4414D4F8003943F00443C4F800399D
+S3150800465887E7D0F8083813F4807F08D100EB4412AE
+S31508004668D2F8003943F00053C2F80039E8E700EBFE
+S315080046784412D2F8003943F08053C2F80039DFE70C
+S31508004688D0F8083813F4807F0ED1D4F8003943F0EF
+S315080046980053C4F8003914460B46C9681A789B8A29
+S315080046A80094FFF71DFF5CE7D4F8003943F0805300
+S315080046B8C4F80039EFE78E683544013DB5FBF6F5D1
+S315080046C81E69164F07EAC5473E431E611F698E686D
+S315080046D8ADB206FB05F5C5F312053D431D6133E783
+S315080046E8CA68002A3FF433AF5A6130E7D0F8083869
+S315080046F813F4807F06D1D4F8003B43F00053C4F87E
+S31508004708003B28E7D4F8003B43F08053C4F8003B45
+S3150800471821E700BF0000F8FFFFFF07E00000F81FC9
+S3150800472803329208002393420CD210B400F5805441
+S31508004738246841F8044B01339342F7D308465DF8D9
+S31508004748044B7047084670470B784A78012A14D0F4
+S3150800475800EB4310D0F8002B002A06DB2BB1D0F863
+S31508004768003B23F08043C0F8003BD0F8003B43F4F5
+S315080047780013C0F8003B0020704700EB4310D0F840
+S315080047880029002A06DB2BB1D0F8003923F080432C
+S31508004798C0F80039D0F8003943F40013C0F80039D6
+S315080047A8E9E70B784A78012A0ED000EB4310D0F8CF
+S315080047B8003B23F40013C0F8003BCB78023BDBB27E
+S315080047C8012B15D90020704700EB4310D0F80039A3
+S315080047D823F40013C0F80039CB78023BDBB2012B6F
+S315080047E8F0D8D0F8003943F08053C0F80039E9E723
+S315080047F8D0F8003B43F08053C0F8003BE2E738B5F1
+S3150800480805460446002208E004EB42134FF67F31BA
+S31508004818C3F80819C3F8081B01320E2AF4D900226E
+S31508004828C5F81028C5F81428C5F81C282846FFF71F
+S315080048384DFC034608B1184638BD10212846FFF72F
+S3150800484831FC0346F7E7D0F8003823F4FE63C0F8CE
+S315080048580038D0F80038090101F4FE610B43C0F8A6
+S3150800486800380020704708B5D0F8043823F002034A
+S31508004878C0F804380320FCF751FF002008BD08B526
+S31508004888D0F8043843F00203C0F804380320FCF7CC
+S3150800489845FF002008BD4269806910407047D0F876
+S315080048A8183800F50060C0691840000C7047D0F841
+S315080048B8183800F50060C069184080B2704700EBE8
+S315080048C84111D1F8082B00F500604069104070477F
+S315080048D810B4D0F81028D0F8343801F00F04E340A3
+S315080048E8DB01DBB2134300EB4111D1F80809184084
+S315080048F85DF8044B7047406900F0010070470000F6
+S31508004908D0F80029054B1340C0F80039D0F8043808
+S3150800491843F48073C0F804380020704700F8FFFF96
+S3150800492810B4046C154B9C4203D9D0F8003B002BF5
+S3150800493816DB0024C0F8104BD0F8104B44F40024BA
+S31508004948C0F8104BD0F8104B44F01804C0F8104BB8
+S31508004958D0F8104B44F0C044C0F8104B012903D0D6
+S3150800496800205DF8044B7047C0F8142BD0F8003BBC
+S3150800497843F08023C0F8003BF2E700BF0A30544FE3
+S31508004988014B1860704700BF0800002098B108B5A9
+S315080049980346D0F8B40210B10020C3F8B40209B12E
+S315080049A8C3F8B0121846012380F89C32027001F049
+S315080049B851F8002008BD0220704710B504460123A7
+S315080049C880F89C32D0F8B4325B680179984720465B
+S315080049D801F0B2F8204601F09FF8002010BD19B181
+S315080049E8C0F8B412002070470220704708B501F0D5
+S315080049F89BF8002008BD08B5D0F8B43223B11B6867
+S31508004A08984718B1022008BD022008BD002008BD35
+S31508004A1808B5D0F8B4325B689847002008BD38B5A1
+S31508004A28044600F52A75284600F04EF90123C4F80D
+S31508004A389432B4F8AE32C4F8983294F8A81201F051
+S31508004A481F03012B0ED03BB1022B10D001F08001B9
+S31508004A58204601F08CF803E02946204600F001FBC1
+S31508004A68002038BD2946204600F02FFBF8E72946DE
+S31508004A78204600F05AFBF3E738B50446A9BB1046AA
+S31508004A88D4F89432032B03D0052B25D0002038BD43
+S31508004A98D4F86031D4F8642193420DD99B1AC4F826
+S31508004AA860319A4206D99AB20146204600F07AFC45
+S31508004AB8002038BD92B2F7E7D4F8B4321B691BB1A7
+S31508004AC894F89C22032A04D0204600F073FC0020A0
+S31508004AD838BD20469847F7E70025C4F89452294672
+S31508004AE8204601F044F8284638BD0A46D0F8B432BC
+S31508004AF89B694BB190F89C12032901D0022038BD56
+S31508004B0811469847002038BD022038BD10B504461E
+S31508004B18002956D11046D4F89432022B09D0002B16
+S31508004B2818BF042B44D094F8A032012B45D0002096
+S31508004B3810BD236A626A93421BD8E169B1FBF2F396
+S31508004B4802FB13132BB98A4203D8D4F89832994230
+S31508004B581DD3D4F8B432DB681BB194F89C22032A17
+S31508004B6823D08021204601F002F8204600F02DFCCB
+S31508004B78D9E79A1A226292B20146204600F00AFC40
+S31508004B8800231A461946204601F011F8CBE70022F9
+S31508004B981146204600F0FEFB0021C4F898120B4681
+S31508004BA80A46204601F003F8BDE720469847D8E7A5
+S31508004BB88021204600F0DBFFB5E7002084F8A00234
+S31508004BC810BD0A46D0F8B4325B694BB190F89C120E
+S31508004BD8032901D0022010BD11469847002010BDB0
+S31508004BE8022010BD70B5044640230022114600F085
+S31508004BF8ABFF0125C4F858514026C4F8646133460A
+S31508004C0800228021204600F09FFFA561666284F88D
+S31508004C189C520023C4F894326360C4F8A432D4F8CA
+S31508004C28B8322BB1D4F8B4325B68002120469847CD
+S31508004C38002070BD01740020704790F89C3280F8F7
+S31508004C489D32042380F89C320020704790F89C32E5
+S31508004C58042B01D00020704790F89D3280F89C32CA
+S31508004C68F8E708B590F89C32032B01D0002008BD58
+S31508004C78D0F8B432DB69002BF8D09847F6E700205D
+S31508004C887047002070470020704708B5012280F851
+S31508004C989C22D0F8B422526801799047002008BDB2
+S31508004CA8002302E00133DBB201300278002AF9D189
+S31508004CB81846704708B54B88012B00D008BDC0F8C0
+S31508004CC8A43200F077FBF9E70B7803704B7843704A
+S31508004CD88B78CA7803EB022343800B794A7903EB6E
+S31508004CE8022383808B79CA7903EB0223C380704732
+S31508004CF810B50446802100F03AFF0021204600F04E
+S31508004D0836FF10BD30B583B005460C460023ADF80E
+S31508004D1806304A88130A013B062B00F2C280DFE8F0
+S31508004D2803F0041A30C0C09EAE00D0F8B0321B6833
+S31508004D380DF10601007C9847002353B9BDF80620F3
+S31508004D481AB1E388002B40F0B280E388002B00F004
+S31508004D58B88003B030BD037C4BB9D0F8B4329B6A2F
+S31508004D680DF106009847022343700023E5E7D0F8BB
+S31508004D78B432DB6A0DF10600984702234370002314
+S31508004D88DBE7D2B2052A64D8DFE802F00313233337
+S31508004D984353D0F8B0325B682BB10DF10601007C9D
+S31508004DA898470023C9E72146FFF7A2FF01230020F9
+S31508004DB8C3E7D0F8B0329B682BB10DF10601007C29
+S31508004DC898470023B9E72146FFF792FF01230020F9
+S31508004DD8B3E7D0F8B032DB682BB10DF10601007CD9
+S31508004DE898470023A9E72146FFF782FF01230020F9
+S31508004DF8A3E7D0F8B0321B692BB10DF10601007C88
+S31508004E089847002399E72146FFF772FF01230020F8
+S31508004E1893E7D0F8B0325B692BB10DF10601007C37
+S31508004E289847002389E72146FFF762FF01230020F8
+S31508004E3883E7D0F8B0329B692BB10DF10601007CE7
+S31508004E489847002379E72146FFF752FF01230020F8
+S31508004E5873E72146FFF74CFF012300206DE7037C23
+S31508004E683BB9D0F8B4325B6B0DF1060098470023BE
+S31508004E7863E72146FFF73CFF012300205DE7037C33
+S31508004E884BB9D0F8B4321B6B0DF1060098470723C7
+S31508004E984370002351E72146FFF72AFF0123002024
+S31508004EA84BE72146FFF724FF0123002045E79A42EE
+S31508004EB828BF1A46ADF806200146284600F05DFACE
+S31508004EC843E7284600F076FA43E738B504468B8860
+S31508004ED8F3B9CB88E3B94B887F2B19D803F07F053C
+S31508004EE890F89C32032B0CD080F89E52294600F085
+S31508004EF84EFE204600F05EFA35B1022384F89C324D
+S31508004F0838BDFFF7F5FE38BD012384F89C3238BD55
+S31508004F182046FFF7EDFE38BD38B504460D468978B4
+S31508004F28284B197001290ED890F89C32022B0ED0FE
+S31508004F38032B21D02946FFF7DBFE224B197820469A
+S31508004F48FFF766FD38BD2946FFF7D2FE38BD81B1A1
+S31508004F584160032380F89C32FFF74DFD022803D0F1
+S31508004F68204600F027FA38BD29462046FFF7C0FE36
+S31508004F7838BD00F01FFA38BD89B1436899421DD07B
+S31508004F88D9B2FFF745FD0F4B197861602046FFF740
+S31508004F9832FD02280DD0204600F00CFA38BD02234F
+S31508004FA880F89C324160FFF733FD204600F002FA8C
+S31508004FB838BD29462046FFF79BFE38BD00F0FAF9AA
+S31508004FC838BD00BF780E002008B5CB88012B0BD159
+S31508004FD890F89C329BB1022B09D9032B0FD10122D9
+S31508004FE8011D00F0CAF908BDFFF782FE08BD014693
+S31508004FF8002341F8083F012200F0BFF908BDFFF772
+S3150800500877FE08BD08B590F89C32013B022B12D8EA
+S31508005018CB88022B0CD10123C360D0F8A4320BB17C
+S315080050280323C360022200F10C0100F0A6F908BDAB
+S31508005038FFF75EFE08BDFFF75BFE08BD08B590F8EA
+S315080050489C32013B022B09D84B88012B00D008BD9E
+S315080050580023C0F8A43200F0ADF908BDFFF748FEF2
+S31508005068F5E708B50B7803F06003202B05D0402B2D
+S3150800507803D043B1FFF73CFE03E0D0F8B4329B688F
+S315080050889847002008BD4B78092B1BD8DFE803F0A2
+S3150800509811171A141A08051A0E0BFFF733FEF0E74C
+S315080050A8FFF713FFEDE7FFF737FFEAE7FFF78CFF90
+S315080050B8E7E7FFF7A7FFE4E7FFF7FCFDE1E7FFF7F8
+S315080050C8BDFFDEE7FFF714FEDBE738B505460C46F5
+S315080050D80B7803F06003202B05D0402B03D013B1BF
+S315080050E8FFF706FE0BE095F89C32013B022B17D812
+S315080050F82379012B05D921462846FFF7F9FD002013
+S3150800510838BDD5F8B4329B68214628469847E388BF
+S31508005118002BF4D10028F2D1284600F04BF9EEE727
+S3150800512821462846FFF7E4FDE9E738B504468A88A4
+S315080051380B7803F06003202B08D0D0B2402B05D09B
+S315080051485BB12046FFF7D4FD002038BDD4F8B43249
+S315080051589B6820469847002038BD202B12D04B78EC
+S31508005168012B3AD0002B67D0032B40F0E38094F844
+S315080051789C32022B0CD0032B1DD02046FFF7B8FD16
+S31508005188002038BDD4F8B4329B682046984738BD05
+S31508005198002818BF802809D00146204600F0E7FCF9
+S315080051A88021204600F0E3FC002038BD2046FFF7A2
+S315080051B89FFD002038BD4B882BB9002818BF8028CA
+S315080051C801D0CB8823B1204600F0F4F8002038BD7A
+S315080051D80146204600F0CBFCF5E794F89C32022BF2
+S315080051E806D0032B17D02046FFF782FD002038BDCE
+S315080051F8002818BF802809D00146204600F0B7FCC9
+S315080052088021204600F0B3FC002038BD2046FFF771
+S315080052186FFD002038BD4B88002B40F0908010F0B9
+S315080052287F0F04D1204600F0C5F8002038BD014696
+S31508005238204600F0A4FCF5E794F89C32022B06D029
+S31508005248032B2BD02046FFF753FD002038BD002836
+S3150800525818BF802813D112F0800F15D100F07F00EF
+S3150800526800EB8000830003F5A8712144043100256A
+S315080052780D600222204600F080F8284638BD2046F0
+S31508005288FFF736FD002038BD00F07F0000EB8000F0
+S31508005298830003F1100121440431E8E752B2002AD9
+S315080052A820DB00F00F0303EB83039D002544D5F8A4
+S315080052B858312BB3002A28DB00F07F0202EB820262
+S315080052C8930003F5A87525440435802818BF0028D7
+S315080052D825D100232B6002222946204600F04DF8E6
+S315080052E8002038BD00F00F0303EB83039D00254417
+S315080052F8AB69002BDED12046FFF7FAFC002038BD43
+S315080053082046FFF7F5FC002038BD00F07F0202EBC7
+S315080053188202930003F1100525440435D5E70146B2
+S31508005328204600F0D3FB10B101232B60D3E70023F6
+S315080053382B60D0E72046FFF7DBFC002038BD0020AD
+S3150800534838BDC8B170B50D4616460446FFF7A8FC21
+S31508005358013040003080287003236B70022307E071
+S315080053685A1CD2B20134E9540233DBB20021A954DB
+S3150800537821780029F4D170BD704710B5134602226A
+S31508005388C0F89422C36103620A46002100F007FCAC
+S31508005398002010BD08B513460A46002100F0FFFB99
+S315080053A8002008BD08B513460A46002100F0FFFB91
+S315080053B8002008BD08B50423C0F8943200231A460D
+S315080053C8194600F0ECFB002008BD08B50523C0F80F
+S315080053D8943200231A46194600F0E9FB002008BD56
+S315080053E8184AD2F8883043F47003C2F88830164B46
+S315080053F81A6842F001021A6000221A6118681349ED
+S31508005408014019609A61DA611A629A62DA621A6365
+S315080054185A639A63DA631A645A64196821F480210C
+S3150800542819601A660A4B1A680A4B1340B3F1005FEB
+S3150800543802D20122084B1A604FF00062014B9A60AB
+S31508005448704700BF00ED00E0004402587FEDF6EA19
+S315080054580010005C0000FFFF0881005108B55B4A90
+S31508005468136823F00F0343F004031360136803F06B
+S315080054780F03042B03D067215548FBF76BFD554AE4
+S31508005488D36823F0070343F00203D360936943F410
+S3150800549840439361504B1A6842F480221A601A688E
+S315080054A842F480321A604C4B1B6813F4003F40F0F4
+S315080054B889800023002BF6D0474B9A6A22F003020C
+S315080054C842F002029A62DA6A42F48032DA62DA6AE8
+S315080054D842F40032DA62DA6A22F00C0242F0040276
+S315080054E8DA62DA6A22F00202DA629A6A22F47C72CC
+S315080054F842F040029A621A6B3849114040F2DF12AC
+S315080055080A431A631A6B22F47E4242F400721A633B
+S315080055181A6B22F4FE0242F498121A631A6B22F0E6
+S31508005528FE4242F080721A631A6842F080721A6064
+S31508005538294B1B6813F0007F46D10023002BF7D0B0
+S31508005548254B9A6922F00F0242F008029A611A69F5
+S3150800555822F0070242F003021A619A6922F470627D
+S315080055689A619A6922F00F0242F008029A61DA698A
+S3150800557822F0700242F04002DA61DA6922F4E06247
+S3150800558842F48062DA619A6922F0700242F04002B7
+S315080055989A611A6A22F0700242F040021A621049A9
+S315080055A80A6822F007020A601A6D22F040521A6544
+S315080055B85A6D22F4401242F480125A650948FFF7D8
+S315080055C8DFF908BD012375E70123B7E70020005274
+S315080055D8685F0008004802580044025800FEFFFFAA
+S315080055E85444025800389C1C08B5FCF769F8FFF7BC
+S315080055F835FF08BD08B5FFF7F7FFFBF7F9FCFBF71A
+S3150800560805FDFCE72DE9F0418EB0514CD4F8F4308D
+S3150800561843F00203C4F8F430D4F8F43003F0020374
+S315080056280793079BD4F8E03043F00103C4F8E03049
+S31508005638D4F8E03003F001030693069BD4F8E0306B
+S3150800564843F00203C4F8E030D4F8E03003F002036C
+S315080056580593059BD4F8E03043F00403C4F8E0301A
+S31508005668D4F8E03003F004030493049BD4F8E0303C
+S3150800567843F00803C4F8E030D4F8E03003F0080330
+S315080056880393039BD4F8E83043F48023C4F8E8303E
+S31508005698D4F8E83003F480230293029BD4F8EC305C
+S315080056A843F48073C4F8EC30D4F8EC3003F4807310
+S315080056B80193019B802308930123099300250A95E2
+S315080056C80B950C95234F08A93846FDF731FF4FF47B
+S315080056D80053089309950C9508A91F48FDF728FF54
+S315080056E84FF44078CDF82080022609960A950B953E
+S315080056F80C9507230D9308A91848FDF719FFCDF847
+S31508005708208009960A960B950C9509230D9308A9E6
+S315080057183846FDF70DFF4FF4C0530893099603233F
+S315080057280A930B950C950A230D9308A90C48FDF7BF
+S31508005738FFFED4F8D83043F00063C4F8D830D4F85C
+S31508005748D83003F000630093009B0EB0BDE8F081E3
+S31508005758004402580004025800080258000C02586F
+S315080057680000025810B5FDF749FF214C4FF4000315
+S31508005778A3612048FDF7F0FD1F48FDF7EDFD20461B
+S31508005788FDF7EAFD1D48FDF7E7FD1D4BD3F8D820C0
+S3150800579822F00062C3F8D820D3F8EC2022F48072ED
+S315080057A8C3F8EC20D3F8E82022F48022C3F8E820CE
+S315080057B8D3F8E02022F00802C3F8E020D3F8E02066
+S315080057C822F00402C3F8E020D3F8E02022F002020F
+S315080057D8C3F8E020D3F8E02022F00102C3F8E0205D
+S315080057E8D3F8F42022F00202C3F8F42010BD00BF53
+S315080057F800040258000C0258000802580000025813
+S3150800580800440258DFF834D0002103E00C4B5B58FB
+S31508005818435004310B480C4B42189A42F6D30B4AAC
+S3150800582802E0002342F8043B094B9A42F9D3FFF7F2
+S31508005838D7FD00F055FAFFF7DDFE70470000022095
+S31508005848D05F000800000020C4000020C400002023
+S31508005858E4140020FEE70000202303800048704770
+S31508005868480000200A230380004870476800002083
+S3150800587808B590F89C32032B01D0002008BDFBF729
+S3150800588809FBFAE708B5FBF705FB002008BD08B5CC
+S315080058980846FBF733FB002008BD000008B50B785F
+S315080058A813F0600F06D14B780A2B14D00B2B17D0A0
+S315080058B8062B01D0002008BD4B881B0A212B04D0D3
+S315080058C80B491722FFF759FDF4E7CA88172A28BF94
+S315080058D817220849F6E701220749FFF74EFDE9E7C7
+S315080058E88B7813B9044A1360E4E7FFF701FAE1E78E
+S315080058F8510000205A0000207C0E002010B50446EE
+S31508005908812100F02CF90121204600F028F9002011
+S3150800591810BD000010B5044640230222812100F07C
+S3150800592813F9402302220121204600F00DF94023ED
+S31508005938034A0121204600F03AF9002010BD00BFAD
+S315080059489C0E0020004870479C0E002008B500F5FC
+S315080059587171D0F80404FFF762F808BD08B5C1EB01
+S31508005968C10293000344D3F80822D0F80404FFF7C9
+S3150800597883F808BD08B5C1EBC102930003449A6CC5
+S31508005988D0F80404FFF7C2F808BD08B5D0F804042F
+S31508005998FFF767F908BD000010B50446C3683BB1B0
+S315080059A8022B0FD091210848FBF7D4FA012100E011
+S315080059B80021D4F80404FFF73DF9D4F80404FFF7E6
+S315080059C811F910BD0121F4E7745F000810B5044603
+S315080059D8D0F80404FFF731F92268D2F8003E43F0FC
+S315080059E80103C2F8003E236A23B1044A136943F047
+S315080059F806031361FBF7D4FD10BD00BF00ED00E0F8
+S31508005A0810B50446FBF7CDFDD4F80404FFF71EF9D4
+S31508005A1810BD08B5D0F80404FFF733F908BD08B572
+S31508005A28D0F80404FFF72BF908BD10B50446012081
+S31508005A38FBF7B5FDD4F80404FFF725F910BD10B532
+S31508005A4804460020FBF7ABFDD4F80404FFF71DF95C
+S31508005A5810BD000003780BB10020704710B5034647
+S31508005A681748C0F80434C3F8C002164B0360092364
+S31508005A7843600222C2600023036182610122C26177
+S31508005A88036243628362C3620363FCF767FD80B9F6
+S31508005A980B4C80212046FDF722FB40220021204698
+S31508005AA8FDF7F9FA802201212046FDF7F4FA0020CD
+S31508005AB810BD4FF493710448FBF74CFAE8E700BFAA
+S31508005AC8DC0E002000000840745F0008D0F8C032D9
+S31508005AD811F0800F08D101F07F01C1EBC1018A00DE
+S31508005AE8134493F8FE01704701F07F01C1EBC10129
+S31508005AF88A00134493F83E00704708B5D0F8C002E8
+S31508005B08FDF71EFA08BD18B1022803D0022070470F
+S31508005B18002070470120704708B5D0F8C002FCF786
+S31508005B28F7FDFFF7F0FF08BD08B5D0F8C002FCF787
+S31508005B38AEFDFFF7E8FF08BD08B5D0F8C002FCF7C8
+S31508005B48C7FDFFF7E0FF08BD10B51C4613462246F9
+S31508005B58D0F8C002FDF74EF9FFF7D5FF10BD08B516
+S31508005B68D0F8C002FDF787F9FFF7CDFF08BD08B5DD
+S31508005B78D0F8C002FDF717FAFFF7C5FF08BD08B544
+S31508005B88D0F8C002FDF750FAFFF7BDFF08BD08B503
+S31508005B98D0F8C002FDF71AF9FFF7B5FF08BD08B532
+S31508005BA8D0F8C002FDF7D5F9FFF7ADFF08BD08B56F
+S31508005BB8D0F8C002FDF796F9FFF7A5FF08BD000063
+S31508005BC812230B80004870479000002004230B809E
+S31508005BD800487047A40000200023934216D230B428
+S31508005BE80BE0373401F8134000015C000134002546
+S31508005BF80D550133DBB2934206D2040F092CF0D8AF
+S31508005C08303401F81340EFE730BC7047704700009E
+S31508005C1838B50A4B186804331C6804331B68C0185F
+S31508005C2800D138BD064D0822A91CFFF7D5FF042266
+S31508005C3805F112012046FFF7CFFFF2E700E8F11F4A
+S31508005C48A800002008B51A230B80FFF7E1FF0148D2
+S31508005C5808BD00BFA800002008B50A4628B10549AE
+S31508005C680548FFF76EFB034808BD02490248FFF7D7
+S31508005C7868FBF8E7E4120020B45F000810B5044C86
+S31508005C880A4621460348FFF75CFB204610BD00BFBD
+S31508005C98E4120020A45F000808B50A4628B1054999
+S31508005CA80548FFF74EFB034808BD02490248FFF7B7
+S31508005CB848FBF8E7E4120020845F000808B50A469E
+S31508005CC828B105490548FFF73CFB034808BD0249C2
+S31508005CD80248FFF736FBF8E7E41200208C5F000855
+S31508005CE870B50D4E0D4CA41BA4100025A54209D16C
+S31508005CF80B4E0C4C00F024F8A41BA4100025A54252
+S31508005D0805D170BD56F8253098470135EEE756F89F
+S31508005D18253098470135F2E7C85F0008C85F0008CC
+S31508005D28C85F0008CC5F000810B5431E0A449142B4
+S31508005D3800D110BD11F8014B03F8014FF7E7000031
+S31508005D48F8B500BFF8BC08BC9E467047F8B500BF52
+S30D08005D58F8BC08BC9E46704722
+S31508005D600000000000000000000000000000000025
+S31508005D70000000000100000002000000030000000F
+S31508005D8004000000000000000500000000000000FC
+S31508005D9000000000000000000600000000000000EF
+S31508005DA00000000000000000070000002E2E5C2EF8
+S31508005DB02E5C2E2E5C2E2E5C536F757263655C41CD
+S31508005DC0524D434D375F53544D333248375C636108
+S31508005DD06E2E63000502060206030703080309037D
+S31508005DE009040A040B040C040C050D050E050F0521
+S31508005DF00F0610061007100800000208000002002F
+S31508005E000101000000000408000002000201000071
+S31508005E100000060800000200030100000000080850
+S31508005E20000002000401000000000A080000020049
+S31508005E300501000000000C08000002000601000031
+S31508005E4000000E080000020007010000000010080C
+S31508005E500000020000020000000012080000020014
+S31508005E6001020000000014080000020002020000FF
+S31508005E7000001608000002000302000000001808CF
+S31508005E80000002000402000000001A0800000200D8
+S31508005E900502000000001C080000020006020000BF
+S31508005EA000001E0800000200070200002E2E5C2ECD
+S31508005EB02E5C2E2E5C2E2E5C536F757263655C41CC
+S31508005EC0524D434D375F53544D333248375C7273E6
+S31508005ED03233322E630000002E2E5C2E2E5C2E2EC0
+S31508005EE05C2E2E5C536F757263655C41524D434D53
+S31508005EF0375F53544D333248375C7573622E6300EF
+S31508005F004F70656E424C54000001020304050607F3
+S31508005F10080C101418203040000000000102030489
+S31508005F200102030406070809010000000200000038
+S31508005F300400000006000000080000000A00000037
+S31508005F400C000000100000002000000040000000C7
+S31508005F5080000000000100000000000001020304A8
+S31508005F6001020304060708092E2E5C6D61696E2E70
+S31508005F70630000002E2E5C757362645F636F6E6645
+S31508005F802E63000044656661756C740057696E552A
+S31508005F9053422042756C6B20496E74657266616364
+S31508005FA0650000004F70656E424C5420557365724B
+S31508005FB00000000057696E5553422042756C6B20ED
+S30D08005FC044657669636500007B
+S30908005FC8BD02000800
+S30908005FCC9902000820
+S31508005FD004010000100000000090D0030090D003D8
+S31508005FE01D59000805590008A558000800000000BA
+S31508005FF0000000008D5800089758000879580008D6
+S3150800600000000000000000000000000061580008C1
+S31508006010000000006D58000809022000010100C0B8
+S31508006020320904000002FF00000007058102400053
+S31508006030FF070501024000FF0A06000200000040B3
+S3150800604001000000C95B0008D55B0008855C0008F4
+S31508006050615C00084D5C0008A15C0008C55C00088E
+S315080060601201000200000040501DAC60000201024F
+S3150800607003010000040309041A03000000000000DD
+S315080060800000000000000000000000000000000002
+S3090800609000000000FE
+S7050800580D8D
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_TrueStudio/Prog/.settings/language.settings.xml b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_TrueStudio/Prog/.settings/language.settings.xml
index 81fdf805..23de469e 100644
--- a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_TrueStudio/Prog/.settings/language.settings.xml
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_TrueStudio/Prog/.settings/language.settings.xml
@@ -4,7 +4,7 @@
 		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
 			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
 			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
-			<provider class="com.atollic.truestudio.mbs.GCCSpecsDetectorAtollicArm" console="false" env-hash="286472261513826467" id="com.atollic.truestudio.mbs.provider" keep-relative-paths="false" name="Atollic ARM Tools Language Settings" parameter="${COMMAND} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+			<provider class="com.atollic.truestudio.mbs.GCCSpecsDetectorAtollicArm" console="false" env-hash="131041188512206230" id="com.atollic.truestudio.mbs.provider" keep-relative-paths="false" name="Atollic ARM Tools Language Settings" parameter="${COMMAND} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
 				<language-scope id="org.eclipse.cdt.core.gcc"/>
 				<language-scope id="org.eclipse.cdt.core.g++"/>
 			</provider>
@@ -14,7 +14,7 @@
 		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
 			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
 			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
-			<provider class="com.atollic.truestudio.mbs.GCCSpecsDetectorAtollicArm" console="false" env-hash="286472261513826467" id="com.atollic.truestudio.mbs.provider" keep-relative-paths="false" name="Atollic ARM Tools Language Settings" parameter="${COMMAND} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+			<provider class="com.atollic.truestudio.mbs.GCCSpecsDetectorAtollicArm" console="false" env-hash="131041188512206230" id="com.atollic.truestudio.mbs.provider" keep-relative-paths="false" name="Atollic ARM Tools Language Settings" parameter="${COMMAND} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
 				<language-scope id="org.eclipse.cdt.core.gcc"/>
 				<language-scope id="org.eclipse.cdt.core.g++"/>
 			</provider>
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_TrueStudio/Prog/Debug/demoprog_stm32h743.elf b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_TrueStudio/Prog/Debug/demoprog_stm32h743.elf
index 27741436..210a32bb 100644
Binary files a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_TrueStudio/Prog/Debug/demoprog_stm32h743.elf and b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_TrueStudio/Prog/Debug/demoprog_stm32h743.elf differ
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_TrueStudio/Prog/Debug/demoprog_stm32h743.srec b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_TrueStudio/Prog/Debug/demoprog_stm32h743.srec
index d7ea2f12..c9d1f2a0 100644
--- a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_TrueStudio/Prog/Debug/demoprog_stm32h743.srec
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_TrueStudio/Prog/Debug/demoprog_stm32h743.srec
@@ -1,50 +1,50 @@
 S01A000064656D6F70726F675F73746D3332683734332E737265638F
-S315080200000000022095410208E5410208E54102087E
-S31508020010E5410208E5410208E54102080000000040
-S31508020020000000000000000000000000E541020890
-S31508020030E541020800000000E541020825420208DF
-S31508020040E5410208E5410208E5410208E5410208E0
-S31508020050E5410208E5410208E5410208E5410208D0
-S31508020060E5410208E5410208E5410208E5410208C0
-S31508020070E5410208E5410208E5410208E5410208B0
-S31508020080E5410208E5410208E5410208E5410208A0
-S31508020090E5410208E5410208E5410208E541020890
-S315080200A0E5410208E5410208E5410208E541020880
-S315080200B0E5410208E5410208E5410208E541020870
-S315080200C0E5410208E5410208E5410208E541020860
-S315080200D0E5410208E5410208E5410208E541020850
-S315080200E0E5410208E541020800000000E541020870
-S315080200F0E5410208E5410208E5410208E541020830
-S31508020100E5410208E5410208E5410208E54102081F
-S31508020110E5410208E5410208E5410208E54102080F
-S31508020120E5410208E5410208E5410208E5410208FF
-S31508020130E5410208E5410208E5410208E5410208EF
+S3150802000000000220A5410208F5410208F54102084E
+S31508020010F5410208F5410208F54102080000000010
+S31508020020000000000000000000000000F541020880
+S31508020030F541020800000000F541020835420208AF
+S31508020040F5410208F5410208F5410208F5410208A0
+S31508020050F5410208F5410208F5410208F541020890
+S31508020060F5410208F5410208F5410208F541020880
+S31508020070F5410208F5410208F5410208F541020870
+S31508020080F5410208F5410208F5410208F541020860
+S31508020090F5410208F5410208F5410208F541020850
+S315080200A0F5410208F5410208F5410208F541020840
+S315080200B0F5410208F5410208F5410208F541020830
+S315080200C0F5410208F5410208F5410208F541020820
+S315080200D0F5410208F5410208F5410208F541020810
+S315080200E0F5410208F541020800000000F541020840
+S315080200F0F5410208F5410208F5410208F5410208F0
+S31508020100F5410208F5410208F5410208F5410208DF
+S31508020110F5410208F5410208F5410208F5410208CF
+S31508020120F5410208F5410208F5410208F5410208BF
+S31508020130F5410208F5410208F5410208F5410208AF
 S31508020140000000000000000000000000000000009F
-S31508020150E5410208E5410208E5410208E5410208CF
-S31508020160E5410208E5410208E5410208E5410208BF
-S31508020170E5410208E5410208E541020800000000DF
-S31508020180E5410208E5410208E5410208E54102089F
-S31508020190E5410208E5410208E5410208E54102088F
-S315080201A0E5410208E5410208E5410208E54102087F
-S315080201B0E5410208E5410208E5410208E54102086F
-S315080201C0E5410208E5410208E5410208E54102085F
-S315080201D0E5410208E5410208E5410208E54102084F
-S315080201E0E5410208E5410208E5410208E54102083F
-S315080201F0E5410208E5410208E5410208E54102082F
-S31508020200E5410208E5410208E5410208E54102081E
-S31508020210E5410208E5410208E5410208E54102080E
-S31508020220E5410208E5410208E5410208000000002E
-S31508020230E5410208E541020800000000E54102081E
-S31508020240E5410208E5410208E5410208E5410208DE
-S31508020250E5410208E5410208E5410208E5410208CE
-S31508020260E5410208E5410208E5410208E5410208BE
-S31508020270E5410208E5410208E541020800000000DE
-S31508020280E5410208E5410208E541020800000000CE
-S3110802029000000000E5410208EE11AA5524
+S31508020150F5410208F5410208F5410208F54102088F
+S31508020160F5410208F5410208F5410208F54102087F
+S31508020170F5410208F5410208F541020800000000AF
+S31508020180F5410208F5410208F5410208F54102085F
+S31508020190F5410208F5410208F5410208F54102084F
+S315080201A0F5410208F5410208F5410208F54102083F
+S315080201B0F5410208F5410208F5410208F54102082F
+S315080201C0F5410208F5410208F5410208F54102081F
+S315080201D0F5410208F5410208F5410208F54102080F
+S315080201E0F5410208F5410208F5410208F5410208FF
+S315080201F0F5410208F5410208F5410208F5410208EF
+S31508020200F5410208F5410208F5410208F5410208DE
+S31508020210F5410208F5410208F5410208F5410208CE
+S31508020220F5410208F5410208F541020800000000FE
+S31508020230F5410208F541020800000000F5410208EE
+S31508020240F5410208F5410208F5410208F54102089E
+S31508020250F5410208F5410208F5410208F54102088E
+S31508020260F5410208F5410208F5410208F54102087E
+S31508020270F5410208F5410208F541020800000000AE
+S31508020280F5410208F5410208F5410208000000009E
+S3110802029000000000F5410208EE11AA5514
 S315080202A010B5054C237833B9044B13B10448AFF3A0
 S315080202B000800123237010BD1000002000000000FA
-S315080202C0A042020808B5034B1BB103490348AFF322
-S315080202D0008008BD0000000014000020A0420208A9
+S315080202C0B042020808B5034B1BB103490348AFF312
+S315080202D0008008BD0000000014000020B042020899
 S315080202E053B94AB9002908BF00281CBF4FF0FF318D
 S315080202F04FF0FF3000F07AB9ADF1080C6DE904CE83
 S3150802030000F006F8DDF804E0DDE9022304B07047E0
@@ -99,985 +99,986 @@ S3150802060015F8147005EB440595F801E007EB0E069C
 S3150802061006FB00064FF4FA55B5FBF6F506FB05F59B
 S31508020620B5F5FA5FE7D1B5FBF6F60E80013EB6B22E
 S31508020630B6F5007FDFD2177083F800E00120F0BD1F
-S315080206400020F0BD0443020808B50948094B0360B7
+S315080206400020F0BD1443020808B50948094B0360A7
 S315080206504FF46143436000238360C36003610C2245
-S3150802066042618361C3610362836203F01BFB08BDB7
-S31508020670CC0000200048004070B58AB00025ADF8CD
-S3150802068026508DF825500AAB03F8045D0DF12502B4
-S315080206900DF126014FF4FA70FFF7AAFF1D4C1E4B07
+S3150802066042618361C3610362836203F023FB08BDAF
+S31508020670CC0000200048004070B58CB00025ADF8CB
+S315080206802E508DF82D500CAB03F8045D0DF12D029A
+S315080206900DF12E014FF4FA70FFF7AAFF204C214BF9
 S315080206A02360A560E560012626746574A574BDF805
-S315080206B026306361A6619DF82530E3619DF82430F2
+S315080206B02E306361A6619DF82D30E3619DF82C30DA
 S315080206C023626662A662E66226636563A663E563DB
-S315080206D0256404236364A564E36426656365A565E6
-S315080206E0E56525666566A366204600F0B3FA0195B8
-S315080206F0029503960723049340F2676305930693CC
-S31508020700079501A9204600F0EFFB204600F02FFCD2
-S315080207100AB070BD2C00002000A0004008B50023D6
-S3150802072001220146034803F0F3F908B1002008BD87
-S31508020730012008BDCC00002008B5FFF785FFFFF7AA
-S315080207409BFF08BDBFF34F8F0549CA6802F4E062F2
-S31508020750044B1343CB60BFF34F8F00BFFDE700BFC7
-S3150802076000ED00E00400FA0508B5214B1B78B3B981
-S315080207702048FFF7D3FF012800D008BD1D4B1B7880
-S31508020780013BDBB23F2BF8D803F048FD1A4B186041
-S315080207900122174B1A700022184B1A7008BD174B04
-S315080207A01B78013313481844FFF7B8FF01280AD00B
-S315080207B003F034FD104B1B6864339842DDD90022DE
-S315080207C00B4B1A70D9E70D4A13780133DBB2137053
-S315080207D0084A12789342D0D10021054A1170054A77
-S315080207E05278FF2AC9D1022BC7D1FFF7ABFF00BF48
-S315080207F099010020580100209C0100209A0100203E
-S3150802080000B58DB00021134800F09AFC58B90120B2
-S3150802081030B940F26763029A9A420BD000237BB939
-S315080208200DB05DF804FB6B4602AA0021094800F0E8
-S31508020830B9FBEDE7039B0BB10023F0E70123EEE7D3
-S315080208409DF816209DF80030FF2BE9D1022AE7D140
-S31508020850FFF778FF2C00002008B5FFF785FFFFF7A2
-S31508020860CFFF08BD08B500228021024800F088FDA6
-S3150802087008BD00BF0004025810B503F0CFFC0E4BAA
-S315080208801B68C31AB3F5FA7F0CD304460B4B1B78C5
-S315080208904BB90122094B1A708021094800F070FDF4
-S315080208A0054B1C6010BD0022044B1A7080210448B7
-S315080208B000F066FDF4E700BFA4010020A0010020B5
-S315080208C000040258104B1B780BB90120704710B56B
-S315080208D004464FF47A70B0FBF3F30C4A1068B0FB87
-S315080208E0F3F000F09FF868B90F2C01D9012010BD6A
-S315080208F0002221464FF0FF3000F064F8044B1C60DA
-S31508020900002010BD012010BD0000002008000020B4
-S315080209100400002010B5032000F042F801F058F850
-S315080209200F498B69C3F303230E4AD35C03F01F03F3
-S31508020930D8408B6903F00F03D35C03F01F0320FA38
-S3150802094003F3094A1360094B18600020FFF7BAFF40
-S3150802095010B10124204610BD044603F077FBF9E7DF
-S3150802096000440258384302080C0000200800002000
-S31508020970034B1B78034A11680B441360704700BF88
-S3150802098000000020A8010020014B1868704700BF2C
-S31508020990A8010020014B1868000C70470010005C83
-S315080209A00649CB6823F4E0631B041B0C000200F41F
-S315080209B0E0600343024A1A43CA60704700ED00E04A
-S315080209C00000FA0530B4144BDB68C3F30223C3F103
-S315080209D00704042C28BF04241D1D062D13D9033B26
-S315080209E0012505FA04F4013C2140994005FA03F36E
-S315080209F0013B13401943002807DB0901C9B2074B1B
-S31508020A00195430BC70470023EAE700F00F000901C9
-S31508020A10C9B2034B1954F4E700ED00E000E400E024
-S31508020A2014ED00E00138B0F1807F0AD2064B586017
-S31508020A30F021064A82F823100020986007221A60DD
-S31508020A4070470120704700BF10E000E000ED00E0AB
-S31508020A50042805D0054A136823F004031360704777
-S31508020A60024A136843F004031360704710E000E07B
-S31508020A70704708B5FFF7FCFF08BD000030B4436BAA
-S31508020A800468D4F884106F4A114041EA8301C4F815
-S31508020A9084100468D4F8841021F47F01856B41EA36
-S31508020AA00541C4F88410816B0B440468D4F8881095
-S31508020AB0114041EA8301C4F888100468D4F8881002
-S31508020AC021F4FE01C56B41EA0541C4F88810C16BE1
-S31508020AD003EB41030468D4F8A010114041EA8301EC
-S31508020AE0C4F8A0100468D4F8A01021F4FE01056C1D
-S31508020AF041EA0541C4F8A010046C416C01FB0434B8
-S31508020B000368D3F8B010114041EA8401C3F8B01063
-S31508020B100368D3F8B01021F4FE01856C41EA054159
-S31508020B20C3F8B010836CC16C01FB03440368D3F8A5
-S31508020B30AC10114041EA8401C3F8AC10036D416D53
-S31508020B4001FB03430468D4F8F010114041EA83011B
-S31508020B50C4F8F0100468D4F8F01021F47C11856DFD
-S31508020B6041EA0541C4F8F010816D03EB41030468BC
-S31508020B70D4F8C0100A4042EA8303C4F8C0300268B7
-S31508020B80D2F8C03023F47C13C16D43EA0143C2F89C
-S31508020B90C0300268D2F8C03023F07C53016E43EAB3
-S31508020BA00163C2F8C030426B274B13449B00C366ED
-S31508020BB0826B03EB82020267C16B02EBC1024267D8
-S31508020BC0046C416C01FB04F102EB81028267846CBE
-S31508020BD0C16C01FB04F102EB8102C267046D416D2F
-S31508020BE001FB04F102EB8102C0F88020816D02EB61
-S31508020BF0C102C0F88420C46D856E05FB04F402EBBD
-S31508020C008402C0F88820016E01FB05F102EB81021D
-S31508020C10C0F890200D498A420DD9D0F89C3043F08D
-S31508020C202003C0F89C30032380F89830012007E09F
-S31508020C30002243F8042BD0F890209342F8D30020E0
-S31508020C4030BC70470300FFFF002B0010FCD30040A6
-S31508020C507047000030B595B004464C22A04901A859
-S31508020C6003F00AFB002C00F0388123689D4A934260
-S31508020C7020D094F898300BB32268936923F01003B6
-S31508020C809361FFF781FE054623689A6912F0080FF9
-S31508020C901AD0FFF779FE401B0A28F5D9D4F89C30FA
-S31508020CA043F00103C4F89C30032384F898300120EA
-S31508020CB015B030BD03F580736360DAE784F89930BE
-S31508020CC02046FFF7C5FFD7E79A6942F001029A6103
-S31508020CD0FFF75AFE054623689A6912F0010F0FD1EB
-S31508020CE0FFF752FE401B0A28F5D9D4F89C3043F088
-S31508020CF00103C4F89C30032384F898300120D7E70F
-S31508020D009A6942F002029A61237C012B40D022683A
-S31508020D10936943F040039361637C012B3ED02268BA
-S31508020D20936923F480439361A37C012B3CD0226808
-S31508020D30936943F4805393612268936923F4407359
-S31508020D40A1680B4393612268936923F0A403936114
-S31508020D502268136923F010031361E368012B29D073
-S31508020D60002B2CD0022B00F09B802268936943F05B
-S31508020D70800393612268136943F010031361E368E1
-S31508020D80032B1CD12268936943F02003936116E072
-S31508020D902268936923F040039361BDE72268936949
-S31508020DA043F480439361BFE72268936923F480532F
-S31508020DB09361C1E72268936943F004039361226849
-S31508020DC0A369591EE369013B1B0243EA4163216A8F
-S31508020DD001390B436169013943EA0143D361A368C7
-S31508020DE0B3F5407F62D0236E33B12268D2F8C030A1
-S31508020DF0616E0B43C2F8C030E36D226ED3420DD04A
-S31508020E002168D1F8C83023F00703A26E14A800EBB4
-S31508020E10820252F84C2C1343C1F8C830236C6BB1CA
-S31508020E202168D1F8BC3023F00703626C14A800EBE2
-S31508020E30820252F84C2C1343C1F8BC30A36C73B12E
-S31508020E402168D1F8BC3023F07003E26C14A800EBD9
-S31508020E50820252F84C2C43EA0213C1F8BC30236DC5
-S31508020E6073B12168D1F8BC3023F4E063626D14A82B
-S31508020E7000EB820252F84C2C43EA0223C1F8BC303A
-S31508020E802268184B9A4222D00023C4F89430C4F838
-S31508020E909C30012384F898302046FFF7EFFD07E7D8
-S31508020EA02268936943F02003936188E72168A36A5D
-S31508020EB0013BE26A013A43EA0223226B013A43EA18
-S31508020EC00213626A013A43EA0243CB608BE762681D
-S31508020ED0936823F003039360D6E70120E8E600BF90
-S31508020EE0B842020800A0004090F89830013BDBB2F5
-S31508020EF0012B07D9D0F89C3043F00203C0F89C3086
-S31508020F0001207047CB680A68D2B9072B0ED08A68C7
-S31508020F10DB0643EA82730A6943EA02434A691343D0
-S31508020F20C26E496842F82130002070470A69CB69C7
-S31508020F301B0243EA02438A69134343F06053EFE70D
-S31508020F4010B40A6942EA4372072B0ED08C684B69C1
-S31508020F5043EA8473006F496800EBC10440F8312004
-S31508020F60636000205DF8044B70478B69F2E790F8DE
-S31508020F709830DBB2012B07D0D0F89C3043F004033B
-S31508020F80C0F89C3001207047022380F89830026826
-S31508020F90936923F0010393610023C0F89C30184635
-S31508020FA070470000F0B590F89840E4B2022C07D0DA
-S31508020FB0D0F89C3043F00803C0F89C300120F0BDFD
-S31508020FC0402937D041295BD0046DA1427ED2C46F35
-S31508020FD0456D05FB01F504EB85044FF0000E256807
-S31508020FE005F080455560002D78D12568C5F38A45F8
-S31508020FF01560256805F000559560256805F00045D9
-S315080210001561A588D561656805F47025D56065689A
-S3150802101005F480155561656805F400159561E5794D
-S3150802102005F07F0515626568ED0F556204F108053E
-S3150802103000245BE00468D4F8A05015F4FE0F0FD024
-S31508021040D4F8A45015F07F0F12D0D4F8A440C4F3F4
-S31508021050052E446F456C05FB0EF504EB8504BEE7C9
-S31508021060D0F89C3043F02003C0F89C300120F0BD34
-S31508021070D0F89C3043F48073C0F89C300120F0BD50
-S315080210800468D4F8B05015F4FE0F0FD0D4F8B45053
-S3150802109015F07F0F12D0D4F8B440C4F3052E846F2E
-S315080210A0C56C05FB0EF504EB850498E7D0F89C3071
-S315080210B043F02003C0F89C300120F0BDD0F89C30E4
-S315080210C043F48073C0F89C300120F0BDD0F89C3000
-S315080210D043F02003C0F89C300120F0BD256825F0B6
-S315080210E06045156085E72E5D1E550134D689134F76
-S315080210F0BE5DB442F7D340290BD041290ED01F2931
-S3150802110011D80268012303FA01F1C2F898100020E7
-S31508021110F0BD0368C3F8A8E00020F0BD0368C3F871
-S31508021120B8E00020F0BD026801F01F01012303FAAE
-S3150802113001F1C2F89C100020F0BD00BF2843020846
-S315080211400368D3F89820D3F89C001F2903D8CA400D
-S3150802115012F0010F17D01F2905D901F01F02D0403E
-S3150802116010F0010F11D01F2907D901F01F01012024
-S3150802117000FA01F1C3F89C107047012000FA01F148
-S31508021180C3F8981070470020704700207047000087
-S31508021190F0B583B000233BE0092600E0002606FAF4
-S315080211A00EF635430234714E46F82450704C2568C3
-S315080211B0D44305EA04064F6817F4803F01D042EA91
-S315080211C005066B4D2E606E6804EA06054F6817F42D
-S315080211D0003F01D042EA0605654E75604FF0B045FC
-S315080211E02D6804EA05064F6817F4801F01D042EA03
-S315080211F005064FF0B0452E606D682C404E6816F411
-S31508021200001F01D042EA05044FF0B0425460013390
-S315080212100A6832FA03F400F0A78001249C402240AF
-S31508021220F5D04D686E1E112D18BF012E01D9122D4B
-S3150802123015D185684FEA430E032707FA0EF725EA02
-S315080212400705CE6806FA0EF635438560456825EA2F
-S3150802125004044D68C5F300159D402C434460C668D6
-S315080212605F000324BC40E44326408D68BD402E43FC
-S31508021270C6604D68122D18BF022D14D14FEAD30C41
-S315080212800CF1080C50F82C5003F0070E4FEA8E0E9C
-S315080212900F2606FA0EF625EA06050E6906FA0EF670
-S315080212A0354340F82C5005682C404D6805F0030577
-S315080212B0BD402C4304604C6814F0805FA7D02D4CC7
-S315080212C0D4F8F45045F00205C4F8F450D4F8F440C2
-S315080212D004F002040194019C9C08A61C234D55F8AF
-S315080212E0265003F003064FEA860E0F2606FA0EF676
-S315080212F025EA0605204FB8423FF450AF1F4EB042CA
-S3150802130022D006F58066B04220D006F58066B04245
-S315080213101ED006F58066B0421CD006F58066B0423D
-S315080213201AD006F58066B04218D006F58066B04235
-S3150802133016D006F58066B04214D006F58066B0422D
-S315080213403FF42AAF0A262AE7012628E7022626E7D5
-S31508021350032624E7042622E7052620E706261EE7B3
-S3150802136007261CE708261AE703B0F0BD0004005852
-S31508021370800000580044025800000258000402582F
-S3150802138012B909048161704781617047134BDB68A2
-S3150802139013F0040F07D1114BDB6803F007038342EE
-S315080213A01AD00120704710B50C4AD36823F00703F8
-S315080213B01843D060FFF7E8FA0446084B5B6813F453
-S315080213C0005F07D1FFF7E0FA001BB0F57A7FF4D980
-S315080213D0012010BD002010BD0020704700480258A9
-S315080213E0002800F0E88238B50446036813F0010FB6
-S315080213F036D0AA4A136903F03803926A102B26D00C
-S31508021400182B20D06368B3F5803F4ED0002B52D1FB
-S31508021410A24B1A6822F480321A601A6822F48022D1
-S315080214201A606368002B5DD0FFF7AEFA05469B4B40
-S315080214301B6813F4003F13D1FFF7A6FA401B642872
-S31508021440F5D9032038BD02F00302022ADAD1934BFA
-S315080214501B6813F4003F03D06368002B00F0AD82CB
-S31508021460236813F0020F66D08C4A1369926A13F046
-S31508021470380349D0182B44D0E368002B00F0A1802A
-S3150802148086490A6822F0190213430B60FFF77CFAB1
-S315080214900546824B1B6813F0040F7AD1FFF774FADC
-S315080214A0401B0228F5D9032038BD7C4A136843F449
-S315080214B080331360B5E7B3F5A02F09D0774B1A68C6
-S315080214C022F480321A601A6822F480221A60A8E787
-S315080214D0724B1A6842F480221A601A6842F4803201
-S315080214E01A609EE7FFF750FA05466C4B1B6813F421
-S315080214F0003FB5D0FFF748FA401B6428F5D9032008
-S3150802150038BD12F0030FB7D1644B1B6813F0040FF2
-S3150802151003D0E368002B00F05282FFF73BFA41F250
-S31508021520030398422CD85D4A536823F47C33216915
-S3150802153043EA01335360236813F0100F71D0574AF8
-S31508021540136903F03803926A082B52D0182B4CD031
-S31508021550E369002B00F0A480504A136843F0800325
-S315080215601360FFF711FA05464C4B1B6813F4807F8C
-S315080215707BD1FFF709FA401B0228F5D9032038BDAB
-S31508021580464A536823F0FE43216943EA01635360DE
-S31508021590D1E7FFF7FFF941F20303984208D83F4A19
-S315080215A0536823F47C33216943EA01335360C2E763
-S315080215B03A4A536823F0FE43216943EA01635360BA
-S315080215C0B9E7364A136823F001031360FFF7DCF91B
-S315080215D00546324B1B6813F0040FACD0FFF7D4F95B
-S315080215E0401B0228F5D9032038BD02F00302012A5E
-S315080215F0AED12A4B1B6813F4807F04D0E369802B93
-S3150802160001D0012038BDFFF7C5F941F2030398421C
-S3150802161022D8224A536823F0F843216A43EA8163AF
-S315080216205360236813F0080F62D06369002B4BD00E
-S315080216301A4A536F43F001035367FFF7A5F90546A4
-S31508021640164B5B6F13F0020F52D1FFF79DF9401B41
-S315080216500228F5D9032038BD104AD36823F07C53F3
-S31508021660216A43EA0163D360DBE7FFF793F941F2A4
-S315080216700303984208D8094A536823F0F843216AB3
-S3150802168043EA81635360CCE7044AD36823F07C5368
-S31508021690216A43EA0163D360C3E700BF00440258E4
-S315080216A0AD4A136823F080031360FFF76DF9054608
-S315080216B0A94B1B6813F4807FB3D0FFF765F9401B6B
-S315080216C00228F5D9032038BDA34A536F23F0010334
-S315080216D05367FFF759F905469F4B5B6F13F0020FE5
-S315080216E006D0FFF751F9401B0228F5D9032038BD69
-S315080216F0236813F0200F29D0A3699BB1964A136871
-S3150802170043F480531360FFF73FF90546924B1B6873
-S3150802171013F4005F1AD1FFF737F9401B0228F5D9EF
-S31508021720032038BD8C4A136823F480531360FFF7ED
-S315080217302BF90546884B1B6813F4005F06D0FFF7A2
-S3150802174023F9401B0228F5D9032038BD236813F074
-S31508021750040F21D1636A002B00F033817E4A126995
-S3150802176002F03802182A00F0EA80022B75D07A4A6B
-S31508021770136823F080731360FFF706F90446764B65
-S315080217801B6813F0007F00F0D880FFF7FDF8001BF6
-S315080217900228F4D9032038BD704A136843F48073CB
-S315080217A01360FFF7F1F805466C4B1B6813F4807F4C
-S315080217B006D1FFF7E9F8401B6428F5D9032038BD9E
-S315080217C0A368012B1CD00BBB634B1A6F22F00102D4
-S315080217D01A671A6F22F004021A67A36863B3FFF73F
-S315080217E0D3F805465C4B1B6F13F0020FB2D1FFF715
-S315080217F0CBF8401B41F288339842F3D9032038BD0F
-S31508021800554A136F43F001031367E6E7052B09D020
-S31508021810514B1A6F22F001021A671A6F22F004025C
-S315080218201A67DAE74C4B1A6F42F004021A671A6F04
-S3150802183042F001021A67D0E7FFF7A6F80546464BBB
-S315080218401B6F13F0020F85D0FFF79EF8401B41F27B
-S3150802185088339842F3D9032038BD3F4A136823F0E8
-S3150802186080731360FFF790F805463B4B1B6813F02D
-S31508021870007F06D0FFF788F8401B0228F5D9032017
-S3150802188038BD354B996A364A0A40A16AE06A41EA86
-S3150802189000110A439A62226B013AC2F30802616B8B
-S315080218A00139490289B20A43A16B0139090401F4D3
-S315080218B0FE010A43E16B0139090601F0FE410A43BA
-S315080218C01A63DA6A22F00102DA62596B254A0A4079
-S315080218D0A16C42EAC1025A63DA6A22F00C02216C4E
-S315080218E00A43DA62DA6A22F00202616C0A43DA62AF
-S315080218F0DA6A42F48032DA62DA6A42F40032DA6288
-S31508021900DA6A42F48022DA62DA6A42F00102DA62BA
-S315080219101A6842F080721A60FFF736F804460E4BD0
-S315080219201B6813F0007F06D1FFF72EF8001B02286A
-S31508021930F5D9032038BD002038BD002038BD064A37
-S31508021940916A106B012B3ED001F00303A26A9342FF
-S315080219500AD0012038BD00BF004402580048025888
-S315080219600CFCFFFF0700FFFFC1F30511E36A99426A
-S3150802197001D0012038BDC0F30802236B013B9A420D
-S3150802198001D0012038BDC0F34622636B013B9A425F
-S3150802199001D0012038BDC0F30642A36B013B9A422F
-S315080219A001D0012038BDC0F30660E36B013B9842C3
-S315080219B00BD0012038BD01207047012038BD012017
-S315080219C038BD002038BD012038BD002038BD00BF13
-S315080219D0734B1B6903F03803102B00F0DF80182BBA
-S315080219E011D00BB16F4870476D4B1B6813F0200F6F
-S315080219F001D16D4870476A4B1868C0F3C1006A4B3B
-S31508021A0023FA00F0704710B4654A916A01F003019F
-S31508021A10906AC0F30510D46A04F00104536BC3F349
-S31508021A20CC0303FB04F307EE903AF8EE677A002834
-S31508021A3000F09480012966D0F9B1022900F091805C
-S31508021A4007EE100AF8EE476A9FED586A86EE267A7E
-S31508021A50534B1B6BC3F3080306EE903AF8EE666A1D
-S31508021A609FED536A67EE867A76EEA77AF7EE006AF4
-S31508021A7077EEA67A27EE277A61E0494B1B6813F0C0
-S31508021A80200F23D046490A68C2F3C102464BD34007
-S31508021A9007EE103AF8EE476A07EE100AB8EE476AFA
-S31508021AA086EE867A0B6BC3F3080306EE903AF8EED7
-S31508021AB0666A9FED3F6A67EE867A76EEA77AF7EE52
-S31508021AC0006A77EEA67A27EE277A38E007EE100A3A
-S31508021AD0F8EE476A9FED376A86EE267A304B1B6B1D
-S31508021AE0C3F3080306EE903AF8EE666A9FED306A8B
-S31508021AF067EE867A76EEA77AF7EE006A77EEA67A28
-S31508021B0027EE277A1BE007EE100AF8EE476A9FEDE2
-S31508021B10276A86EE267A224B1B6BC3F3080306EE68
-S31508021B20903AF8EE666A9FED226A67EE867A76EE54
-S31508021B30A77AF7EE006A77EEA67A27EE277A184B87
-S31508021B401B6BC3F34623013307EE903AF8EE677A26
-S31508021B50C7EE276AFCEEE67A17EE900A5DF8044BA2
-S31508021B60704707EE100AF8EE476A9FED136A86EE8B
-S31508021B70267A0B4B1B6BC3F3080306EE903AF8EE74
-S31508021B80666A9FED0B6A67EE867A76EEA77AF7EEB5
-S31508021B90006A77EEA67A27EE277AD0E707487047D3
-S31508021BA00044025800093D000090D0030024744AFC
-S31508021BB0000000390024744C0024F44A00127A000A
-S31508021BC0002800F0358170B504469B4B1B6803F06C
-S31508021BD00F038B420CD2984A136823F00F030B4368
-S31508021BE01360136803F00F03994201D0012070BDF8
-S31508021BF0236813F0040F0CD02269904B9B6903F0FB
-S31508021C0070039A4205D98D48836923F070031A43F3
-S31508021C108261236813F0080F0CD06269874BDB696F
-S31508021C2003F070039A4205D98448C36923F0700306
-S31508021C301A43C261236813F0100F0CD0A2697F4BB6
-S31508021C40DB6903F4E0639A4205D97C48C36923F445
-S31508021C50E0631A43C261236813F0200F0CD0E269CD
-S31508021C60764B1B6A03F070039A4205D97348036AD6
-S31508021C7023F070031A430262236813F0020F0CD092
-S31508021C80E2686E4B9B6903F00F039A4205D96B48CB
-S31508021C90836923F00F031A4382610D46236813F002
-S31508021CA0010F41D0654A936923F47063A1680B4317
-S31508021CB093616368022B23D0032B27D0012B2CD0E8
-S31508021CC05E4A126812F0040F00F0B4805B490A6992
-S31508021CD022F0070213430B61FEF756FE0646574BE0
-S31508021CE01B6903F038036268B3EBC20F1CD0FEF718
-S31508021CF04BFE801B41F288339842F0D9032070BD0F
-S31508021D00126812F4003FE1D1012070BD4B4A1268F5
-S31508021D1012F0007FDAD1012070BD484A126812F427
-S31508021D20807FD3D1012070BD236813F0020F0CD037
-S31508021D30E268424B9B6903F00F039A4205D23F4978
-S31508021D408B6923F00F031A438A613B4B1B6803F026
-S31508021D500F039D420CD2384A136823F00F032B4314
-S31508021D601360136803F00F039D4201D0012070BD72
-S31508021D70236813F0040F0CD02269304B9B6903F0D9
-S31508021D8070039A4205D22D498B6923F070031A43D0
-S31508021D908A61236813F0080F0CD06269274BDB6946
-S31508021DA003F070039A4205D22449CB6923F07003E3
-S31508021DB01A43CA61236813F0100F0CD0A2691F4B8D
-S31508021DC0DB6903F4E0639A4205D21C49CB6923F422
-S31508021DD0E0631A43CA61236813F0200F0CD0E26944
-S31508021DE0164B1B6A03F070039A4205D213490B6A13
-S31508021DF023F070031A430A62FFF7EAFD0F498B695B
-S31508021E00C3F303230E4AD35C03F01F03D8408B693E
-S31508021E1003F00F03D35C03F01F0320FA03F3094A06
-S31508021E201360094B1860094B1868FEF74BFD70BD25
-S31508021E3001207047012070BD00200052004402585C
-S31508021E40384302080C000020080000200400002085
-S31508021E5008B5FFF7BDFD0B4A9369C3F303230A4985
-S31508021E60CB5C03F01F0320FA03F3926902F00F0218
-S31508021E70885C00F01F0023FA00F0044A1060044A46
-S31508021E80136008BD00440258384302080C000020BB
-S31508021E900800002008B5FFF7DBFF054BDB69C3F333
-S31508021EA00213044AD35C03F01F03D84008BD00BFDF
-S31508021EB0004402583843020808B5FFF7C9FF054B24
-S31508021EC0DB69C3F30223044AD35C03F01F03D84039
-S31508021ED008BD00BF004402583843020808B5FFF798
-S31508021EE0B7FF054B1B6AC3F30213044AD35C03F01C
-S31508021EF01F03D84008BD00BF0044025838430208F1
-S31508021F0030B477498C6A8A6AC2F30532CD6AC5F358
-S31508021F100015CB6BC3F3CC0303FB05F3002A00F0D1
-S31508021F20DA8004F0030407EE903AF8EE677A012C99
-S31508021F3066D0FCB1022C00F0B18007EE102AB8EE8A
-S31508021F40477A9FED686AC6EE076A654B9B6BC3F3D1
-S31508021F50080307EE103AB8EE477A9FED636A67EE12
-S31508021F60867A77EE277AB7EE007A77EE877A66EE82
-S31508021F70A76A61E05A4B1B6813F0200F23D0584C0E
-S31508021F802168C1F3C101594BCB4007EE103AB8EEAE
-S31508021F90477A06EE902AB8EE666AC7EE066AA36B19
-S31508021FA0C3F3080307EE103AB8EE477A9FED4E6A76
-S31508021FB067EE867A77EE277AB7EE007A77EE877A31
-S31508021FC066EEA76A38E007EE102AB8EE477A9FED62
-S31508021FD0486AC6EE076A424B9B6BC3F3080307EED1
-S31508021FE0103AB8EE477A9FED406A67EE867A77EE40
-S31508021FF0277AB7EE007A77EE877A66EEA76A1BE04B
-S3150802200007EE102AB8EE477A9FED366AC6EE076AD9
-S31508022010334B9B6BC3F3080307EE103AB8EE477AC5
-S315080220209FED316A67EE867A77EE277AB7EE007AFF
-S3150802203077EE877A66EEA76A294A936BC3F3462335
-S3150802204007EE103AB8EE477AB7EE006A37EE067A26
-S31508022050C6EE877AFCEEE77AC0ED007A936BC3F395
-S31508022060064307EE103AB8EE477A37EE067AC6EE18
-S31508022070877AFCEEE77AC0ED017A936BC3F30663BF
-S3150802208007EE903AF8EE677A77EE867A86EEA77AC0
-S31508022090BCEEC77A80ED027A30BC704707EE102A8A
-S315080220A0B8EE477A9FED136AC6EE076A0C4B9B6B2E
-S315080220B0C3F3080307EE103AB8EE477A9FED0A6AA9
-S315080220C067EE867A77EE277AB7EE007A77EE877A20
-S315080220D066EEA76AB0E70023036043608360DBE726
-S315080220E0004402580024744A000000390090D003C4
-S315080220F00024744C0024F44A30B477498C6A8A6AFC
-S31508022100C2F30552CD6AC5F300254B6CC3F3CC0363
-S3150802211003FB05F3002A00F0DA8004F0030407EE55
-S31508022120903AF8EE677A012C66D0FCB1022C00F0E0
-S31508022130B18007EE102AB8EE477A9FED686AC6EEB6
-S31508022140076A654B1B6CC3F3080307EE103AB8EE31
-S31508022150477A9FED636A67EE867A77EE277AB7EE55
-S31508022160007A77EE877A66EEA76A61E05A4B1B68B1
-S3150802217013F0200F23D0584C2168C1F3C101594BE3
-S31508022180CB4007EE103AB8EE477A06EE902AB8EE3A
-S31508022190666AC7EE066A236CC3F3080307EE103AAB
-S315080221A0B8EE477A9FED4E6A67EE867A77EE277A19
-S315080221B0B7EE007A77EE877A66EEA76A38E007EE18
-S315080221C0102AB8EE477A9FED486AC6EE076A424B6E
-S315080221D01B6CC3F3080307EE103AB8EE477A9FED75
-S315080221E0406A67EE867A77EE277AB7EE007A77EE56
-S315080221F0877A66EEA76A1BE007EE102AB8EE477AD8
-S315080222009FED366AC6EE076A334B1B6CC3F30803A7
-S3150802221007EE103AB8EE477A9FED316A67EE867A8C
-S3150802222077EE277AB7EE007A77EE877A66EEA76AAE
-S31508022230294A136CC3F3462307EE103AB8EE477AD7
-S31508022240B7EE006A37EE067AC6EE877AFCEEE77ACA
-S31508022250C0ED007A136CC3F3064307EE103AB8EEE4
-S31508022260477A37EE067AC6EE877AFCEEE77AC0ED4B
-S31508022270017A136CC3F3066307EE903AF8EE677AAF
-S3150802228077EE867A86EEA77ABCEEC77A80ED027A70
-S3150802229030BC704707EE102AB8EE477A9FED136AEC
-S315080222A0C6EE076A0C4B1B6CC3F3080307EE103A1B
-S315080222B0B8EE477A9FED0A6A67EE867A77EE277A4C
-S315080222C0B7EE007A77EE877A66EEA76AB0E700235A
-S315080222D0036043608360DBE7004402580024744AC3
-S315080222E0000000390090D0030024744C0024F44AFC
-S315080222F070470000000000002DE9F04B86B0044646
-S31508022300016883680269134342691343C269134326
-S31508022310426E134308688B4A024013430B602268D5
-S31508022320536823F44053E1680B435360A369226858
-S3150802233085498A4201D0216A0B4390688349014044
-S315080223400B4393602268D36A23F00F03616A0B4337
-S31508022350D36223687E4A93426FD07E4A934200F044
-S31508022360A9807D4A934200F0BF807C4A934200F0DE
-S31508022370D2807B4A934200F0FD807A4A934200F06B
-S315080223801081794A934200F03581784A934200F0E7
-S3150802239048816D4A934200F05B8180256A4A9342DE
-S315080223A000F08081E369B3F5004F00F01386402DF3
-S315080223B001F2C582DFE815F08D080409C30AC30ACB
-S315080223C04209C30AC30AC30A8209C30AC30AC30A59
-S315080223D0C30AC30AC30AC30AC209C30AC30AC30A87
-S315080223E0C30AC30AC30AC30AC30AC30AC30AC30A75
-S315080223F0C30AC30AC30AC30A420AC30AC30AC30AE6
-S31508022400C30AC30AC30AC30AC30AC30AC30AC30A54
+S315080206D0266404236364A564E36425656365A565E6
+S315080206E0E56525666566A366204600F0B9FA0395B0
+S315080206F004950596069640F267630793089309954B
+S3150802070003A9204600F0F6FB00963346022211465C
+S31508020710204600F032FC204600F04BFC0CB070BDBF
+S315080207202C00002000A0004008B500230122014643
+S31508020730034803F0F5F908B1002008BD012008BDF9
+S31508020740CC00002008B5FFF77FFFFFF795FF08BD2D
+S31508020750BFF34F8F0549CA6802F4E062044B13439C
+S31508020760CB60BFF34F8F00BFFDE700BF00ED00E08F
+S315080207700400FA0508B5214B1B78B3B92048FFF7E0
+S31508020780D3FF012800D008BD1D4B1B78013BDBB205
+S315080207903F2BF8D803F04AFD1A4B18600122174B73
+S315080207A01A700022184B1A7008BD174B1B780133B2
+S315080207B013481844FFF7B8FF01280AD003F036FD9C
+S315080207C0104B1B6864339842DDD900220B4B1A7012
+S315080207D0D9E70D4A13780133DBB21370084A127847
+S315080207E09342D0D10021054A1170054A5278FF2A50
+S315080207F0C9D1022BC7D1FFF7ABFF00BF9901002071
+S31508020800580100209C0100209A01002000B58DB0F5
+S315080208104021134800F0B6FC58B9012030B940F21D
+S315080208206763029A9A420BD000237BB90DB05DF832
+S3150802083004FB6B4602AA4021094800F0D5FBEDE706
+S31508020840039B0BB10023F0E70123EEE79DF8162080
+S315080208509DF80030FF2BE9D1022AE7D1FFF778FF8E
+S315080208602C00002008B5FFF785FFFFF7CFFF08BD6C
+S3150802087008B500228021024800F08AFD08BD00BFA3
+S315080208800004025810B503F0D1FC0E4B1B68C31ABC
+S31508020890B3F5FA7F0CD304460B4B1B784BB90122EE
+S315080208A0094B1A708021094800F072FD054B1C603D
+S315080208B010BD0022044B1A708021044800F068FD1E
+S315080208C0F4E700BFA4010020A0010020000402589A
+S315080208D0104B1B780BB90120704710B504464FF42C
+S315080208E07A70B0FBF3F30C4A1068B0FBF3F000F031
+S315080208F09FF868B90F2C01D9012010BD00222146A4
+S315080209004FF0FF3000F064F8044B1C60002010BD65
+S31508020910012010BD0000002008000020040000206D
+S3150802092010B5032000F042F801F05AF80F498B6916
+S31508020930C3F303230E4AD35C03F01F03D8408B6923
+S3150802094003F00F03D35C03F01F0320FA03F3094AEB
+S315080209501360094B18600020FFF7BAFF10B1012493
+S31508020960204610BD044603F079FBF9E70044025815
+S31508020970484302080C00002008000020034B1B789D
+S31508020980034A11680B441360704700BF0000002039
+S31508020990A8010020014B1868704700BFA801002073
+S315080209A0014B1868000C70470010005C0649CB68BA
+S315080209B023F4E0631B041B0C000200F4E06003430B
+S315080209C0024A1A43CA60704700ED00E00000FA05C1
+S315080209D030B4144BDB68C3F30223C3F10704042CB7
+S315080209E028BF04241D1D062D13D9033B012505FA2C
+S315080209F004F4013C2140994005FA03F3013B1340F4
+S31508020A001943002807DB0901C9B2074B195430BC40
+S31508020A1070470023EAE700F00F000901C9B2034B49
+S31508020A201954F4E700ED00E000E400E014ED00E0FC
+S31508020A300138B0F1807F0AD2064B5860F021064A87
+S31508020A4082F823100020986007221A607047012056
+S31508020A50704700BF10E000E000ED00E0042805D072
+S31508020A60054A136823F0040313607047024A1368A1
+S31508020A7043F004031360704710E000E0704708B5BE
+S31508020A80FFF7FCFF08BD000030B4436B0468D4F8D6
+S31508020A9084106F4A114041EA8301C4F8841004683D
+S31508020AA0D4F8841021F47F01856B41EA0541C4F824
+S31508020AB08410816B0B440468D4F88810114041EA0B
+S31508020AC08301C4F888100468D4F8881021F4FE015A
+S31508020AD0C56B41EA0541C4F88810C16B03EB4103B3
+S31508020AE00468D4F8A010114041EA8301C4F8A010A2
+S31508020AF00468D4F8A01021F4FE01056C41EA054108
+S31508020B00C4F8A010046C416C01FB04340368D3F8E2
+S31508020B10B010114041EA8401C3F8B0100368D3F853
+S31508020B20B01021F4FE01856C41EA0541C3F8B01004
+S31508020B30836CC16C01FB03440368D3F8AC10114003
+S31508020B4041EA8401C3F8AC10036D416D01FB03430E
+S31508020B500468D4F8F010114041EA8301C4F8F01091
+S31508020B600468D4F8F01021F47C11856D41EA054138
+S31508020B70C4F8F010816D03EB41030468D4F8C01081
+S31508020B800A4042EA8303C4F8C0300268D2F8C03089
+S31508020B9023F47C13C16D43EA0143C2F8C0300268EC
+S31508020BA0D2F8C03023F07C53016E43EA0163C2F8DF
+S31508020BB0C030426B274B13449B00C366826B03EB20
+S31508020BC082020267C16B02EBC1024267046C416C86
+S31508020BD001FB04F102EB81028267846CC16C01FBA2
+S31508020BE004F102EB8102C267046D416D01FB04F157
+S31508020BF002EB8102C0F88020816D02EBC102C0F8C7
+S31508020C008420C46D856E05FB04F402EB8402C0F8E9
+S31508020C108820016E01FB05F102EB8102C0F89020E3
+S31508020C200D498A420DD9D0F89C3043F02003C0F80A
+S31508020C309C30032380F89830012007E0002243F80D
+S31508020C40042BD0F890209342F8D3002030BC70478A
+S31508020C500300FFFF002B0010FCD300407047000082
+S31508020C6030B595B004464C22A04901A803F00CFB06
+S31508020C70002C00F0388123689D4A934220D094F8CC
+S31508020C8098300BB32268936923F010039361FFF738
+S31508020C9081FE054623689A6912F0080F1AD0FFF7F3
+S31508020CA079FE401B0A28F5D9D4F89C3043F0010393
+S31508020CB0C4F89C30032384F89830012015B030BD5F
+S31508020CC003F580736360DAE784F899302046FFF704
+S31508020CD0C5FFD7E79A6942F001029A61FFF75AFE01
+S31508020CE0054623689A6912F0010F0FD1FFF752FEE3
+S31508020CF0401B0A28F5D9D4F89C3043F00103C4F8FE
+S31508020D009C30032384F898300120D7E79A6942F089
+S31508020D1002029A61237C012B40D02268936943F030
+S31508020D2040039361637C012B3ED02268936923F4C6
+S31508020D3080439361A37C012B3CD02268936943F4D8
+S31508020D40805393612268936923F44073A1680B4325
+S31508020D5093612268936923F0A40393612268136955
+S31508020D6023F010031361E368012B29D0002B2CD042
+S31508020D70022B00F09B802268936943F080039361FB
+S31508020D802268136943F010031361E368032B1CD12D
+S31508020D902268936943F02003936116E022689369F7
+S31508020DA023F040039361BDE72268936943F48043C5
+S31508020DB09361BFE72268936923F480539361C1E77D
+S31508020DC02268936943F0040393612268A369591E52
+S31508020DD0E369013B1B0243EA4163216A01390B437A
+S31508020DE06169013943EA0143D361A368B3F5407FD8
+S31508020DF062D0236E33B12268D2F8C030616E0B43DB
+S31508020E00C2F8C030E36D226ED3420DD02168D1F804
+S31508020E10C83023F00703A26E14A800EB820252F828
+S31508020E204C2C1343C1F8C830236C6BB12168D1F836
+S31508020E30BC3023F00703626C14A800EB820252F856
+S31508020E404C2C1343C1F8BC30A36C73B12168D1F89A
+S31508020E50BC3023F07003E26C14A800EB820252F84D
+S31508020E604C2C43EA0213C1F8BC30236D73B12168D6
+S31508020E70D1F8BC3023F4E063626D14A800EB820259
+S31508020E8052F84C2C43EA0223C1F8BC302268184BAC
+S31508020E909A4222D00023C4F89430C4F89C30012325
+S31508020EA084F898302046FFF7EFFD07E72268936932
+S31508020EB043F02003936188E72168A36A013BE26A4B
+S31508020EC0013A43EA0223226B013A43EA0213626AAF
+S31508020ED0013A43EA0243CB608BE76268936823F0E0
+S31508020EE003039360D6E70120E8E600BFC84202087A
+S31508020EF000A0004090F89830013BDBB2012B07D9DD
+S31508020F00D0F89C3043F00203C0F89C3001207047A9
+S31508020F10CB680A68D2B9072B0ED08A68DB0643EA81
+S31508020F2082730A6943EA02434A691343C26E4968ED
+S31508020F3042F82130002070470A69CB691B0243EA4E
+S31508020F4002438A69134343F06053EFE710B40A6910
+S31508020F5042EA4372072B0ED08C684B6943EA8473C4
+S31508020F60006F496800EBC10440F831206360002035
+S31508020F705DF8044B70478B69F2E710B490F8984015
+S31508020F80E4B2012C09D0D0F89C3043F00403C0F82F
+S31508020F909C3001205DF8044B70470068920042EAD3
+S31508020FA0011141EA4303019A1343C0F88030002035
+S31508020FB0F0E790F89830DBB2012B07D0D0F89C30D6
+S31508020FC043F00403C0F89C3001207047022380F8DE
+S31508020FD098300268936923F0010393610023C0F8ED
+S31508020FE09C30184670470000F0B590F89840E4B275
+S31508020FF0022C07D0D0F89C3043F00803C0F89C3086
+S315080210000120F0BD402937D041295BD0046DA142A9
+S315080210107ED2C46F456D05FB01F504EB85044FF0DE
+S31508021020000E256805F080455560002D78D12568A3
+S31508021030C5F38A451560256805F00055956025684B
+S3150802104005F000451561A588D561656805F4702522
+S31508021050D560656805F480155561656805F400155F
+S315080210609561E57905F07F0515626568ED0F5562AC
+S3150802107004F1080500245BE00468D4F8A05015F4CE
+S31508021080FE0F0FD0D4F8A45015F07F0F12D0D4F863
+S31508021090A440C4F3052E446F456C05FB0EF504EB1C
+S315080210A08504BEE7D0F89C3043F02003C0F89C3094
+S315080210B00120F0BDD0F89C3043F48073C0F89C3010
+S315080210C00120F0BD0468D4F8B05015F4FE0F0FD015
+S315080210D0D4F8B45015F07F0F12D0D4F8B440C4F344
+S315080210E0052E846FC56C05FB0EF504EB850498E79F
+S315080210F0D0F89C3043F02003C0F89C300120F0BDA4
+S31508021100D0F89C3043F48073C0F89C300120F0BDBF
+S31508021110D0F89C3043F02003C0F89C300120F0BD83
+S31508021120256825F06045156085E72E5D1E55013454
+S31508021130D689134FBE5DB442F7D340290BD0412955
+S315080211400ED01F2911D80268012303FA01F1C2F849
+S3150802115098100020F0BD0368C3F8A8E00020F0BD8F
+S315080211600368C3F8B8E00020F0BD026801F01F0169
+S31508021170012303FA01F1C2F89C100020F0BD00BF5A
+S3150802118038430208402905D00368D3F8B40000F0B2
+S315080211907F0070470368D3F8A40000F07F00704709
+S315080211A0F0B583B000233BE0092600E0002606FAE4
+S315080211B00EF635430234714E46F82450704C2568B3
+S315080211C0D44305EA04064F6817F4803F01D042EA81
+S315080211D005066B4D2E606E6804EA06054F6817F41D
+S315080211E0003F01D042EA0605654E75604FF0B045EC
+S315080211F02D6804EA05064F6817F4801F01D042EAF3
+S3150802120005064FF0B0452E606D682C404E6816F400
+S31508021210001F01D042EA05044FF0B0425460013380
+S315080212200A6832FA03F400F0A78001249C4022409F
+S31508021230F5D04D686E1E112D18BF012E01D9122D3B
+S3150802124015D185684FEA430E032707FA0EF725EAF2
+S315080212500705CE6806FA0EF635438560456825EA1F
+S3150802126004044D68C5F300159D402C434460C668C6
+S315080212705F000324BC40E44326408D68BD402E43EC
+S31508021280C6604D68122D18BF022D14D14FEAD30C31
+S315080212900CF1080C50F82C5003F0070E4FEA8E0E8C
+S315080212A00F2606FA0EF625EA06050E6906FA0EF660
+S315080212B0354340F82C5005682C404D6805F0030567
+S315080212C0BD402C4304604C6814F0805FA7D02D4CB7
+S315080212D0D4F8F45045F00205C4F8F450D4F8F440B2
+S315080212E004F002040194019C9C08A61C234D55F89F
+S315080212F0265003F003064FEA860E0F2606FA0EF666
+S3150802130025EA0605204FB8423FF450AF1F4EB042B9
+S3150802131022D006F58066B04220D006F58066B04235
+S315080213201ED006F58066B0421CD006F58066B0422D
+S315080213301AD006F58066B04218D006F58066B04225
+S3150802134016D006F58066B04214D006F58066B0421D
+S315080213503FF42AAF0A262AE7012628E7022626E7C5
+S31508021360032624E7042622E7052620E706261EE7A3
+S3150802137007261CE708261AE703B0F0BD0004005842
+S31508021380800000580044025800000258000402581F
+S3150802139012B909048161704781617047134BDB6892
+S315080213A013F0040F07D1114BDB6803F007038342DE
+S315080213B01AD00120704710B50C4AD36823F00703E8
+S315080213C01843D060FFF7E6FA0446084B5B6813F445
+S315080213D0005F07D1FFF7DEFA001BB0F57A7FF4D972
+S315080213E0012010BD002010BD002070470048025899
+S315080213F0002800F0E88238B50446036813F0010FA6
+S3150802140036D0AA4A136903F03803926A102B26D0FB
+S31508021410182B20D06368B3F5803F4ED0002B52D1EB
+S31508021420A24B1A6822F480321A601A6822F48022C1
+S315080214301A606368002B5DD0FFF7ACFA05469B4B32
+S315080214401B6813F4003F13D1FFF7A4FA401B642864
+S31508021450F5D9032038BD02F00302022ADAD1934BEA
+S315080214601B6813F4003F03D06368002B00F0AD82BB
+S31508021470236813F0020F66D08C4A1369926A13F036
+S31508021480380349D0182B44D0E368002B00F0A1801A
+S3150802149086490A6822F0190213430B60FFF77AFAA3
+S315080214A00546824B1B6813F0040F7AD1FFF772FACE
+S315080214B0401B0228F5D9032038BD7C4A136843F439
+S315080214C080331360B5E7B3F5A02F09D0774B1A68B6
+S315080214D022F480321A601A6822F480221A60A8E777
+S315080214E0724B1A6842F480221A601A6842F48032F1
+S315080214F01A609EE7FFF74EFA05466C4B1B6813F413
+S31508021500003FB5D0FFF746FA401B6428F5D90320F9
+S3150802151038BD12F0030FB7D1644B1B6813F0040FE2
+S3150802152003D0E368002B00F05282FFF739FA41F242
+S31508021530030398422CD85D4A536823F47C33216905
+S3150802154043EA01335360236813F0100F71D0574AE8
+S31508021550136903F03803926A082B52D0182B4CD021
+S31508021560E369002B00F0A480504A136843F0800315
+S315080215701360FFF70FFA05464C4B1B6813F4807F7E
+S315080215807BD1FFF707FA401B0228F5D9032038BD9D
+S31508021590464A536823F0FE43216943EA01635360CE
+S315080215A0D1E7FFF7FDF941F20303984208D83F4A0B
+S315080215B0536823F47C33216943EA01335360C2E753
+S315080215C03A4A536823F0FE43216943EA01635360AA
+S315080215D0B9E7364A136823F001031360FFF7DAF90D
+S315080215E00546324B1B6813F0040FACD0FFF7D2F94D
+S315080215F0401B0228F5D9032038BD02F00302012A4E
+S31508021600AED12A4B1B6813F4807F04D0E369802B82
+S3150802161001D0012038BDFFF7C3F941F2030398420E
+S3150802162022D8224A536823F0F843216A43EA81639F
+S315080216305360236813F0080F62D06369002B4BD0FE
+S315080216401A4A536F43F001035367FFF7A3F9054696
+S31508021650164B5B6F13F0020F52D1FFF79BF9401B33
+S315080216600228F5D9032038BD104AD36823F07C53E3
+S31508021670216A43EA0163D360DBE7FFF791F941F296
+S315080216800303984208D8094A536823F0F843216AA3
+S3150802169043EA81635360CCE7044AD36823F07C5358
+S315080216A0216A43EA0163D360C3E700BF00440258D4
+S315080216B0AD4A136823F080031360FFF76BF90546FA
+S315080216C0A94B1B6813F4807FB3D0FFF763F9401B5D
+S315080216D00228F5D9032038BDA34A536F23F0010324
+S315080216E05367FFF757F905469F4B5B6F13F0020FD7
+S315080216F006D0FFF74FF9401B0228F5D9032038BD5B
+S31508021700236813F0200F29D0A3699BB1964A136860
+S3150802171043F480531360FFF73DF90546924B1B6865
+S3150802172013F4005F1AD1FFF735F9401B0228F5D9E1
+S31508021730032038BD8C4A136823F480531360FFF7DD
+S3150802174029F90546884B1B6813F4005F06D0FFF794
+S3150802175021F9401B0228F5D9032038BD236813F066
+S31508021760040F21D1636A002B00F033817E4A126985
+S3150802177002F03802182A00F0EA80022B75D07A4A5B
+S31508021780136823F080731360FFF704F90446764B57
+S315080217901B6813F0007F00F0D880FFF7FBF8001BE8
+S315080217A00228F4D9032038BD704A136843F48073BB
+S315080217B01360FFF7EFF805466C4B1B6813F4807F3E
+S315080217C006D1FFF7E7F8401B6428F5D9032038BD90
+S315080217D0A368012B1CD00BBB634B1A6F22F00102C4
+S315080217E01A671A6F22F004021A67A36863B3FFF72F
+S315080217F0D1F805465C4B1B6F13F0020FB2D1FFF707
+S31508021800C9F8401B41F288339842F3D9032038BD00
+S31508021810554A136F43F001031367E6E7052B09D010
+S31508021820514B1A6F22F001021A671A6F22F004024C
+S315080218301A67DAE74C4B1A6F42F004021A671A6FF4
+S3150802184042F001021A67D0E7FFF7A4F80546464BAD
+S315080218501B6F13F0020F85D0FFF79CF8401B41F26D
+S3150802186088339842F3D9032038BD3F4A136823F0D8
+S3150802187080731360FFF78EF805463B4B1B6813F01F
+S31508021880007F06D0FFF786F8401B0228F5D9032009
+S3150802189038BD354B996A364A0A40A16AE06A41EA76
+S315080218A000110A439A62226B013AC2F30802616B7B
+S315080218B00139490289B20A43A16B0139090401F4C3
+S315080218C0FE010A43E16B0139090601F0FE410A43AA
+S315080218D01A63DA6A22F00102DA62596B254A0A4069
+S315080218E0A16C42EAC1025A63DA6A22F00C02216C3E
+S315080218F00A43DA62DA6A22F00202616C0A43DA629F
+S31508021900DA6A42F48032DA62DA6A42F40032DA6277
+S31508021910DA6A42F48022DA62DA6A42F00102DA62AA
+S315080219201A6842F080721A60FFF734F804460E4BC2
+S315080219301B6813F0007F06D1FFF72CF8001B02285C
+S31508021940F5D9032038BD002038BD002038BD064A27
+S31508021950916A106B012B3ED001F00303A26A9342EF
+S315080219600AD0012038BD00BF004402580048025878
+S315080219700CFCFFFF0700FFFFC1F30511E36A99425A
+S3150802198001D0012038BDC0F30802236B013B9A42FD
+S3150802199001D0012038BDC0F34622636B013B9A424F
+S315080219A001D0012038BDC0F30642A36B013B9A421F
+S315080219B001D0012038BDC0F30660E36B013B9842B3
+S315080219C00BD0012038BD01207047012038BD012007
+S315080219D038BD002038BD012038BD002038BD00BF03
+S315080219E0734B1B6903F03803102B00F0DF80182BAA
+S315080219F011D00BB16F4870476D4B1B6813F0200F5F
+S31508021A0001D16D4870476A4B1868C0F3C1006A4B2A
+S31508021A1023FA00F0704710B4654A916A01F003018F
+S31508021A20906AC0F30510D46A04F00104536BC3F339
+S31508021A30CC0303FB04F307EE903AF8EE677A002824
+S31508021A4000F09480012966D0F9B1022900F091804C
+S31508021A5007EE100AF8EE476A9FED586A86EE267A6E
+S31508021A60534B1B6BC3F3080306EE903AF8EE666A0D
+S31508021A709FED536A67EE867A76EEA77AF7EE006AE4
+S31508021A8077EEA67A27EE277A61E0494B1B6813F0B0
+S31508021A90200F23D046490A68C2F3C102464BD340F7
+S31508021AA007EE103AF8EE476A07EE100AB8EE476AEA
+S31508021AB086EE867A0B6BC3F3080306EE903AF8EEC7
+S31508021AC0666A9FED3F6A67EE867A76EEA77AF7EE42
+S31508021AD0006A77EEA67A27EE277A38E007EE100A2A
+S31508021AE0F8EE476A9FED376A86EE267A304B1B6B0D
+S31508021AF0C3F3080306EE903AF8EE666A9FED306A7B
+S31508021B0067EE867A76EEA77AF7EE006A77EEA67A17
+S31508021B1027EE277A1BE007EE100AF8EE476A9FEDD2
+S31508021B20276A86EE267A224B1B6BC3F3080306EE58
+S31508021B30903AF8EE666A9FED226A67EE867A76EE44
+S31508021B40A77AF7EE006A77EEA67A27EE277A184B77
+S31508021B501B6BC3F34623013307EE903AF8EE677A16
+S31508021B60C7EE276AFCEEE67A17EE900A5DF8044B92
+S31508021B70704707EE100AF8EE476A9FED136A86EE7B
+S31508021B80267A0B4B1B6BC3F3080306EE903AF8EE64
+S31508021B90666A9FED0B6A67EE867A76EEA77AF7EEA5
+S31508021BA0006A77EEA67A27EE277AD0E707487047C3
+S31508021BB00044025800093D000090D0030024744AEC
+S31508021BC0000000390024744C0024F44A00127A00FA
+S31508021BD0002800F0358170B504469B4B1B6803F05C
+S31508021BE00F038B420CD2984A136823F00F030B4358
+S31508021BF01360136803F00F03994201D0012070BDE8
+S31508021C00236813F0040F0CD02269904B9B6903F0EA
+S31508021C1070039A4205D98D48836923F070031A43E3
+S31508021C208261236813F0080F0CD06269874BDB695F
+S31508021C3003F070039A4205D98448C36923F07003F6
+S31508021C401A43C261236813F0100F0CD0A2697F4BA6
+S31508021C50DB6903F4E0639A4205D97C48C36923F435
+S31508021C60E0631A43C261236813F0200F0CD0E269BD
+S31508021C70764B1B6A03F070039A4205D97348036AC6
+S31508021C8023F070031A430262236813F0020F0CD082
+S31508021C90E2686E4B9B6903F00F039A4205D96B48BB
+S31508021CA0836923F00F031A4382610D46236813F0F2
+S31508021CB0010F41D0654A936923F47063A1680B4307
+S31508021CC093616368022B23D0032B27D0012B2CD0D8
+S31508021CD05E4A126812F0040F00F0B4805B490A6982
+S31508021CE022F0070213430B61FEF754FE0646574BD2
+S31508021CF01B6903F038036268B3EBC20F1CD0FEF708
+S31508021D0049FE801B41F288339842F0D9032070BD00
+S31508021D10126812F4003FE1D1012070BD4B4A1268E5
+S31508021D2012F0007FDAD1012070BD484A126812F417
+S31508021D30807FD3D1012070BD236813F0020F0CD027
+S31508021D40E268424B9B6903F00F039A4205D23F4968
+S31508021D508B6923F00F031A438A613B4B1B6803F016
+S31508021D600F039D420CD2384A136823F00F032B4304
+S31508021D701360136803F00F039D4201D0012070BD62
+S31508021D80236813F0040F0CD02269304B9B6903F0C9
+S31508021D9070039A4205D22D498B6923F070031A43C0
+S31508021DA08A61236813F0080F0CD06269274BDB6936
+S31508021DB003F070039A4205D22449CB6923F07003D3
+S31508021DC01A43CA61236813F0100F0CD0A2691F4B7D
+S31508021DD0DB6903F4E0639A4205D21C49CB6923F412
+S31508021DE0E0631A43CA61236813F0200F0CD0E26934
+S31508021DF0164B1B6A03F070039A4205D213490B6A03
+S31508021E0023F070031A430A62FFF7EAFD0F498B694A
+S31508021E10C3F303230E4AD35C03F01F03D8408B692E
+S31508021E2003F00F03D35C03F01F0320FA03F3094AF6
+S31508021E301360094B1860094B1868FEF749FD70BD17
+S31508021E4001207047012070BD00200052004402584C
+S31508021E50484302080C000020080000200400002065
+S31508021E6008B5FFF7BDFD0B4A9369C3F303230A4975
+S31508021E70CB5C03F01F0320FA03F3926902F00F0208
+S31508021E80885C00F01F0023FA00F0044A1060044A36
+S31508021E90136008BD00440258484302080C0000209B
+S31508021EA00800002008B5FFF7DBFF054BDB69C3F323
+S31508021EB00213044AD35C03F01F03D84008BD00BFCF
+S31508021EC0004402584843020808B5FFF7C9FF054B04
+S31508021ED0DB69C3F30223044AD35C03F01F03D84029
+S31508021EE008BD00BF004402584843020808B5FFF778
+S31508021EF0B7FF054B1B6AC3F30213044AD35C03F00C
+S31508021F001F03D84008BD00BF0044025848430208D0
+S31508021F1030B477498C6A8A6AC2F30532CD6AC5F348
+S31508021F200015CB6BC3F3CC0303FB05F3002A00F0C1
+S31508021F30DA8004F0030407EE903AF8EE677A012C89
+S31508021F4066D0FCB1022C00F0B18007EE102AB8EE7A
+S31508021F50477A9FED686AC6EE076A654B9B6BC3F3C1
+S31508021F60080307EE103AB8EE477A9FED636A67EE02
+S31508021F70867A77EE277AB7EE007A77EE877A66EE72
+S31508021F80A76A61E05A4B1B6813F0200F23D0584CFE
+S31508021F902168C1F3C101594BCB4007EE103AB8EE9E
+S31508021FA0477A06EE902AB8EE666AC7EE066AA36B09
+S31508021FB0C3F3080307EE103AB8EE477A9FED4E6A66
+S31508021FC067EE867A77EE277AB7EE007A77EE877A21
+S31508021FD066EEA76A38E007EE102AB8EE477A9FED52
+S31508021FE0486AC6EE076A424B9B6BC3F3080307EEC1
+S31508021FF0103AB8EE477A9FED406A67EE867A77EE30
+S31508022000277AB7EE007A77EE877A66EEA76A1BE03A
+S3150802201007EE102AB8EE477A9FED366AC6EE076AC9
+S31508022020334B9B6BC3F3080307EE103AB8EE477AB5
+S315080220309FED316A67EE867A77EE277AB7EE007AEF
+S3150802204077EE877A66EEA76A294A936BC3F3462325
+S3150802205007EE103AB8EE477AB7EE006A37EE067A16
+S31508022060C6EE877AFCEEE77AC0ED007A936BC3F385
+S31508022070064307EE103AB8EE477A37EE067AC6EE08
+S31508022080877AFCEEE77AC0ED017A936BC3F30663AF
+S3150802209007EE903AF8EE677A77EE867A86EEA77AB0
+S315080220A0BCEEC77A80ED027A30BC704707EE102A7A
+S315080220B0B8EE477A9FED136AC6EE076A0C4B9B6B1E
+S315080220C0C3F3080307EE103AB8EE477A9FED0A6A99
+S315080220D067EE867A77EE277AB7EE007A77EE877A10
+S315080220E066EEA76AB0E70023036043608360DBE716
+S315080220F0004402580024744A000000390090D003B4
+S315080221000024744C0024F44A30B477498C6A8A6AEB
+S31508022110C2F30552CD6AC5F300254B6CC3F3CC0353
+S3150802212003FB05F3002A00F0DA8004F0030407EE45
+S31508022130903AF8EE677A012C66D0FCB1022C00F0D0
+S31508022140B18007EE102AB8EE477A9FED686AC6EEA6
+S31508022150076A654B1B6CC3F3080307EE103AB8EE21
+S31508022160477A9FED636A67EE867A77EE277AB7EE45
+S31508022170007A77EE877A66EEA76A61E05A4B1B68A1
+S3150802218013F0200F23D0584C2168C1F3C101594BD3
+S31508022190CB4007EE103AB8EE477A06EE902AB8EE2A
+S315080221A0666AC7EE066A236CC3F3080307EE103A9B
+S315080221B0B8EE477A9FED4E6A67EE867A77EE277A09
+S315080221C0B7EE007A77EE877A66EEA76A38E007EE08
+S315080221D0102AB8EE477A9FED486AC6EE076A424B5E
+S315080221E01B6CC3F3080307EE103AB8EE477A9FED65
+S315080221F0406A67EE867A77EE277AB7EE007A77EE46
+S31508022200877A66EEA76A1BE007EE102AB8EE477AC7
+S315080222109FED366AC6EE076A334B1B6CC3F3080397
+S3150802222007EE103AB8EE477A9FED316A67EE867A7C
+S3150802223077EE277AB7EE007A77EE877A66EEA76A9E
+S31508022240294A136CC3F3462307EE103AB8EE477AC7
+S31508022250B7EE006A37EE067AC6EE877AFCEEE77ABA
+S31508022260C0ED007A136CC3F3064307EE103AB8EED4
+S31508022270477A37EE067AC6EE877AFCEEE77AC0ED3B
+S31508022280017A136CC3F3066307EE903AF8EE677A9F
+S3150802229077EE867A86EEA77ABCEEC77A80ED027A60
+S315080222A030BC704707EE102AB8EE477A9FED136ADC
+S315080222B0C6EE076A0C4B1B6CC3F3080307EE103A0B
+S315080222C0B8EE477A9FED0A6A67EE867A77EE277A3C
+S315080222D0B7EE007A77EE877A66EEA76AB0E700234A
+S315080222E0036043608360DBE7004402580024744AB3
+S315080222F0000000390090D0030024744C0024F44AEC
+S3150802230070470000000000002DE9F04B86B0044635
+S31508022310016883680269134342691343C269134316
+S31508022320426E134308688B4A024013430B602268C5
+S31508022330536823F44053E1680B435360A369226848
+S3150802234085498A4201D0216A0B4390688349014034
+S315080223500B4393602268D36A23F00F03616A0B4327
+S31508022360D36223687E4A93426FD07E4A934200F034
+S31508022370A9807D4A934200F0BF807C4A934200F0CE
+S31508022380D2807B4A934200F0FD807A4A934200F05B
+S315080223901081794A934200F03581784A934200F0D7
+S315080223A048816D4A934200F05B8180256A4A9342CE
+S315080223B000F08081E369B3F5004F00F01386402DE3
+S315080223C001F2C582DFE815F08D080409C30AC30ABB
+S315080223D04209C30AC30AC30A8209C30AC30AC30A49
+S315080223E0C30AC30AC30AC30AC209C30AC30AC30A77
+S315080223F0C30AC30AC30AC30AC30AC30AC30AC30A65
+S31508022400C30AC30AC30AC30A420AC30AC30AC30AD5
 S31508022410C30AC30AC30AC30AC30AC30AC30AC30A44
 S31508022420C30AC30AC30AC30AC30AC30AC30AC30A34
-S31508022430C30AC30AC30AC30A7E0A4D4A526D02F088
-S315080224403802282A34D8DFE812F02900330033008C
-S31508022450330033003300330033001B0133003300EB
-S31508022460330033003300330033002B0033003300CC
-S31508022470330033003300330033002D0033003300BA
-S31508022480330033003300330033002F0033003300A8
-S3150802249033003300330033003300310001257DE772
-S315080224A008257BE7102579E7202577E7402575E794
-S315080224B0802573E72E4A526D02F00702052A11D8C3
-S315080224C0DFE812F00600E00008000A000C000E0021
-S315080224D0002563E7082561E710255FE720255DE704
-S315080224E040255BE7802559E7214A526D02F007022B
-S315080224F0052A0ED8DFE802F003C80507090B0025EE
-S315080225004CE708254AE7102548E7202546E74025EF
-S3150802251044E7802542E7164A526D02F00702052A69
-S315080225200ED8DFE802F003B30507090B002535E7E5
-S31508022530082533E7102531E720252FE740252DE723
-S3150802254080252BE7F369FFCF000C0058FFF4FF1133
-S31508022550001001400044004000480040004C004082
-S31508022560005000400014014000780040007C004002
-S31508022570004402588E4A526D02F00702052A0ED806
-S31508022580DFE802F003860507090B002506E708259A
-S3150802259004E7102502E7202500E74025FEE6802508
-S315080225A0FCE6834A526D02F03802282A20D8DFE870
-S315080225B002F0151F1F1F1F1F1F1F711F1F1F1F1F1F
-S315080225C01F1F171F1F1F1F1F1F1F191F1F1F1F1F19
-S315080225D01F1F1B1F1F1F1F1F1F1F1D000125DDE6B3
-S315080225E00825DBE61025D9E62025D7E64025D5E6D7
-S315080225F08025D3E66E4A526D02F00702052A0ED8E6
-S31508022600DFE802F0034A0507090B0025C6E6082596
-S31508022610C4E61025C2E62025C0E64025BEE680258A
-S31508022620BCE6634A526D02F00702052A0ED8DFE8B5
-S3150802263002F003350507090B0025AFE60825ADE6C6
-S315080226401025ABE62025A9E64025A7E68025A5E6BE
-S3150802265002F50E32926D02F00702052A0ED8DFE85D
-S3150802266002F0031F0507090B022597E6082595E6DA
-S31508022670102593E6202591E640258FE680258DE6EE
-S3150802268004258BE6042589E6042587E6042585E6DE
-S31508022690042583E6042581E604257FE604257DE6EE
-S315080226A004257BE6082D00F0A3800BD9202D00F027
-S315080226B03681402D00F05381102D00F0D380002082
-S315080226C0012645E0022D20D0042DF8D103A8FFF7F4
-S315080226D017FC0498636A002B71D0012B74D0022B65
-S315080226E074D0032B74D0042B74D0052B74D0062B0C
-S315080226F074D0072B74D0082B74D0092B74D00A2BEC
-S3150802270074D00B2B58D001235AE0FFF7E7FB636A14
-S31508022710D3B1012B3AD0022B3AD0032B3AD0042B51
-S315080227203AD0052B3AD0062B3AD0072B3AD0082BAB
-S315080227303AD0092B3AD00A2B3CD00B2B01D00123D5
-S3150802274003E04FF4807300E00123B0FBF3F00026A8
-S31508022750002800F0F086676807EB47039842C1F045
-S31508022760F180B0EB073F01F2EF80082D00F0768288
-S3150802277040F28881202D00F09383402D00F0D98302
-S31508022780102D00F0C3820126002006E20223DCE7B0
-S315080227900423DAE70623D8E70823D6E70A23D4E789
-S315080227A00C23D2E71023D0E72023CEE74023CCE739
-S315080227B0004402588023C8E74FF4807300E00123DF
-S315080227C0B0FBF3F00026C3E70223F9E70423F7E791
-S315080227D00623F5E70823F3E70A23F1E70C23EFE7D5
-S315080227E01023EDE72023EBE74023E9E78023E7E719
-S315080227F06846FFF781FC0198636AD3B1012B1DD0A5
-S31508022800022B1DD0032B1DD0042B1DD0052B1DD04A
-S31508022810062B1DD0072B1DD0082B1DD0092B1DD02A
-S315080228200A2B1DD00B2B01D0012303E04FF4807332
-S3150802283000E00123B0FBF3F0002689E70223F9E75B
-S315080228400423F7E70623F5E70823F3E70A23F1E764
-S315080228500C23EFE71023EDE72023EBE74023E9E714
-S315080228608023E7E7A04B1B6813F0200F3BD09E4B53
-S315080228701B68C3F3C1039D48D840636AC3B1012BE1
-S315080228801BD0022B1BD0032B1BD0042B1BD0052BD2
-S315080228901BD0062B1BD0072B1BD0082B1BD0092BB2
-S315080228A01BD00A2B1BD00B2B1BD14FF4807300E0D5
-S315080228B00123B0FBF3F000264AE70223F9E70423D3
-S315080228C0F7E70623F5E70823F3E70A23F1E70C23DC
-S315080228D0EFE71023EDE72023EBE74023E9E7802320
-S315080228E0E7E70123E5E7636A002B58D0012B59D0A5
-S315080228F0022B5AD0032B5BD0042B5CD0052B5DD060
-S31508022900062B5ED0072B5FD0082B60D0092B61D02F
-S315080229100A2B62D00B2B63D17548002618E7636A27
-S31508022920002B60D0012B61D0022B62D0032B63D01F
-S31508022930042B64D0052B65D0062B66D0072B67D0EF
-S31508022940082B68D0092B69D00A2B6BD00B2B02D027
-S3150802295068480026FCE643F609500026F8E6636A4C
-S31508022960002B63D0012B65D0022B67D0032B69D0CD
-S31508022970042B6BD0052B6DD0062B6FD0072B71D08D
-S31508022980082B73D0092B75D00A2B77D00B2B03D0C3
-S315080229904FF400400026DBE680200026D8E653489E
-S315080229A00026D5E654480026D2E654480026CFE645
-S315080229B053480026CCE653480026C9E65248002664
-S315080229C0C6E652480026C3E64A480026C0E65048EC
-S315080229D00026BDE64F480026BAE64F480026B7E667
-S315080229E042480026B4E643480026B1E6484800268F
-S315080229F0AEE648480026ABE648480026A8E646481A
-S31508022A000026A5E646480026A2E6464800269FE690
-S31508022A10374800269CE64448002699E64FF22440A9
-S31508022A20002695E647F61220002691E64FF4004066
-S31508022A3000268DE64FF48040002689E64FF40050C2
-S31508022A40002685E641F25550002681E64FF480506D
-S31508022A5000267DE640F6CC40002679E640F6AA2016
-S31508022A60002675E64FF40060002671E64FF4806092
-S31508022A7000266DE64FF40070002669E64FF4807072
-S31508022A80002665E6022D51D0042D7FF47CAE03A8FC
-S31508022A90FFF736FA0498636A002B00F0AA80012B26
-S31508022AA000F0BE80022B00F0BE80032B00F0BE8031
-S31508022AB0042B00F0BE80052B00F0BE80062B00F02A
-S31508022AC0BE80072B00F0BE80082B00F0BE80092BC3
-S31508022AD000F0BE800A2B00F0BE800B2B00F085802A
-S31508022AE00122002387E000BF004402580090D00369
-S31508022AF090D0030000093D000048E8010024F400D4
-S31508022B00AAC2A20000127A0000A86100556151000B
-S31508022B1080841E0040420F0020A107002A2C0A00CA
-S31508022B20801A06001516050048E80100FFF7D6F9CF
-S31508022B30636AE3B1012B3AD0022B3BD0032B3CD07C
-S31508022B40042B3DD0052B3ED0062B3FD0072B40D079
-S31508022B50082B41D0092B42D00A2B43D00B2B02D08B
-S31508022B600122002305E04FF48072002301E00122CE
-S31508022B7000230021FDF7B4FB4FEA012949EA10694F
-S31508022B804FEA002862685008002318EB000B49F147
-S31508022B90000C58466146FDF7A3FBA0F54072B44BFC
-S31508022BA09A4200F2D3862368D86000F0C4BC022297
-S31508022BB00023DEE704220023DBE706220023D8E708
-S31508022BC008220023D5E70A220023D2E70C22002393
-S31508022BD0CFE710220023CCE720220023C9E74022B0
-S31508022BE00023C6E780220023C3E74FF4807200233E
-S31508022BF001E0012200230021FDF772FB4FEA0129B9
-S31508022C0049EA10694FEA002862685008002318EB5F
-S31508022C10000B49F1000C58466146FDF761FBBCE71B
-S31508022C2002220023E7E704220023E4E70622002320
-S31508022C30E1E708220023DEE70A220023DBE70C226B
-S31508022C400023D8E710220023D5E720220023D2E763
-S31508022C5040220023CFE780220023CCE76846FFF70D
-S31508022C604BFA0198636AE3B1012B31D0022B32D0B9
-S31508022C70032B33D0042B34D0052B35D0062B36D074
-S31508022C80072B37D0082B38D0092B39D00A2B3AD044
-S31508022C900B2B02D00122002305E04FF48072002399
-S31508022CA001E0012200230021FDF71AFB4FEA012960
-S31508022CB049EA10694FEA002862685008002318EBAF
-S31508022CC0000B49F1000C58466146FDF709FB64E71B
-S31508022CD002220023E7E704220023E4E70622002370
-S31508022CE0E1E708220023DEE70A220023DBE70C22BB
-S31508022CF00023D8E710220023D5E720220023D2E7B3
-S31508022D0040220023CFE780220023CCE7594B1B68D9
-S31508022D1013F0200F59D0574B1B68C3F3C10356480B
-S31508022D20D840636ACBB1012B2ED0022B2FD0032BAE
-S31508022D3030D0042B31D0052B32D0062B33D0072BBB
-S31508022D4034D0082B35D0092B36D00A2B37D00B2B8B
-S31508022D5038D14FF48072002301E0012200230021BA
-S31508022D60FDF7BEFA4FEA012949EA10694FEA002837
-S31508022D7078083A46002318EB000B49F1000C58462E
-S31508022D806146FDF7ADFA08E702220023E7E70422C7
-S31508022D900023E4E706220023E1E708220023DEE710
-S31508022DA00A220023DBE70C220023D8E7102200239D
-S31508022DB0D5E720220023D2E740220023CFE780224C
-S31508022DC00023CCE701220023C9E7636AC3B1012BBA
-S31508022DD021D0022B22D0032B23D0042B25D0052B5E
-S31508022DE026D0062B27D0072B29D0082B2AD0092B29
-S31508022DF02BD00A2B2CD00B2B2DD11F48002101E0FA
-S31508022E001E4803217D083A460023401941F1000174
-S31508022E10FDF766FAC1E61A480121F3E719480021C7
-S31508022E20F0E70FA1D1E90001ECE717480021E9E72D
-S31508022E3016480021E6E70CA1D1E90001E2E71448A9
-S31508022E400021DFE713480021DCE713480021D9E710
-S31508022E5012480021D6E709480321D3E7AFF30080D9
-S31508022E6000AAC2A20000000000556151000000003D
-S31508022E70FFFC0F00004402580090D003000090D0D7
-S31508022E80000048E8000024F40000127A0000A86155
-S31508022E900000093D0080841E0040420F0020A10761
-S31508022EA0636ADBB1012B24D0022B25D0032B26D053
-S31508022EB0042B28D0052B29D0062B2AD0072B2CD059
-S31508022EC0082B2DD0092B2ED00A2B2FD00B2B02D054
-S31508022ED09F48002104E09F48002101E09C48002108
-S31508022EE07D083A460023401941F10001FDF7F8F939
-S31508022EF053E699480021F3E798480021F0E790A1A4
-S31508022F00D1E90001ECE796480021E9E79548002156
-S31508022F10E6E78DA1D1E90001E2E793480021DFE760
-S31508022F2092480021DCE792480021D9E7914800211E
-S31508022F30D6E7636AEBB1012B27D0022B29D0032BE4
-S31508022F402BD0042B2CD0052B2ED0062B2FD0072BBB
-S31508022F5030D0082B32D0092B34D00A2B36D00B2B83
-S31508022F6003D04FF40000002106E04FF40040002190
-S31508022F7002E04FF4000000217D083A46002340197A
-S31508022F8041F10001FDF7ACF907E64FF48000002194
-S31508022F90F2E74FF400100021EEE777480021EBE74D
-S31508022FA04FF480100021E7E774480021E4E77448EB
-S31508022FB00021E1E74FF400200021DDE74FF48020ED
-S31508022FC00021D9E74FF400300021D5E74FF48030CD
-S31508022FD00021D1E7402D00F27982DFE815F04100A1
-S31508022FE08F0077027702F3007702770277023401BD
-S31508022FF077027702770277027702770277027501FC
-S3150802300077027702770277027702770277027702E8
-S315080230107702770277027702770277027702F6015A
-S3150802302077027702770277027702770277027702C8
+S31508022430C30AC30AC30AC30AC30AC30AC30AC30A24
+S31508022440C30AC30AC30AC30A7E0A4D4A526D02F078
+S315080224503802282A34D8DFE812F02900330033007C
+S31508022460330033003300330033001B0133003300DB
+S31508022470330033003300330033002B0033003300BC
+S31508022480330033003300330033002D0033003300AA
+S31508022490330033003300330033002F003300330098
+S315080224A033003300330033003300310001257DE762
+S315080224B008257BE7102579E7202577E7402575E784
+S315080224C0802573E72E4A526D02F00702052A11D8B3
+S315080224D0DFE812F00600E00008000A000C000E0011
+S315080224E0002563E7082561E710255FE720255DE7F4
+S315080224F040255BE7802559E7214A526D02F007021B
+S31508022500052A0ED8DFE802F003C80507090B0025DD
+S315080225104CE708254AE7102548E7202546E74025DF
+S3150802252044E7802542E7164A526D02F00702052A59
+S315080225300ED8DFE802F003B30507090B002535E7D5
+S31508022540082533E7102531E720252FE740252DE713
+S3150802255080252BE7F369FFCF000C0058FFF4FF1123
+S31508022560001001400044004000480040004C004072
+S31508022570005000400014014000780040007C0040F2
+S31508022580004402588E4A526D02F00702052A0ED8F6
+S31508022590DFE802F003860507090B002506E708258A
+S315080225A004E7102502E7202500E74025FEE68025F8
+S315080225B0FCE6834A526D02F03802282A20D8DFE860
+S315080225C002F0151F1F1F1F1F1F1F711F1F1F1F1F0F
+S315080225D01F1F171F1F1F1F1F1F1F191F1F1F1F1F09
+S315080225E01F1F1B1F1F1F1F1F1F1F1D000125DDE6A3
+S315080225F00825DBE61025D9E62025D7E64025D5E6C7
+S315080226008025D3E66E4A526D02F00702052A0ED8D5
+S31508022610DFE802F0034A0507090B0025C6E6082586
+S31508022620C4E61025C2E62025C0E64025BEE680257A
+S31508022630BCE6634A526D02F00702052A0ED8DFE8A5
+S3150802264002F003350507090B0025AFE60825ADE6B6
+S315080226501025ABE62025A9E64025A7E68025A5E6AE
+S3150802266002F50E32926D02F00702052A0ED8DFE84D
+S3150802267002F0031F0507090B022597E6082595E6CA
+S31508022680102593E6202591E640258FE680258DE6DE
+S3150802269004258BE6042589E6042587E6042585E6CE
+S315080226A0042583E6042581E604257FE604257DE6DE
+S315080226B004257BE6082D00F0A3800BD9202D00F017
+S315080226C03681402D00F05381102D00F0D380002072
+S315080226D0012645E0022D20D0042DF8D103A8FFF7E4
+S315080226E017FC0498636A002B71D0012B74D0022B55
+S315080226F074D0032B74D0042B74D0052B74D0062BFC
+S3150802270074D0072B74D0082B74D0092B74D00A2BDB
+S3150802271074D00B2B58D001235AE0FFF7E7FB636A04
+S31508022720D3B1012B3AD0022B3AD0032B3AD0042B41
+S315080227303AD0052B3AD0062B3AD0072B3AD0082B9B
+S315080227403AD0092B3AD00A2B3CD00B2B01D00123C5
+S3150802275003E04FF4807300E00123B0FBF3F0002698
+S31508022760002800F0F086676807EB47039842C1F035
+S31508022770F180B0EB073F01F2EF80082D00F0768278
+S3150802278040F28881202D00F09383402D00F0D983F2
+S31508022790102D00F0C3820126002006E20223DCE7A0
+S315080227A00423DAE70623D8E70823D6E70A23D4E779
+S315080227B00C23D2E71023D0E72023CEE74023CCE729
+S315080227C0004402588023C8E74FF4807300E00123CF
+S315080227D0B0FBF3F00026C3E70223F9E70423F7E781
+S315080227E00623F5E70823F3E70A23F1E70C23EFE7C5
+S315080227F01023EDE72023EBE74023E9E78023E7E709
+S315080228006846FFF781FC0198636AD3B1012B1DD094
+S31508022810022B1DD0032B1DD0042B1DD0052B1DD03A
+S31508022820062B1DD0072B1DD0082B1DD0092B1DD01A
+S315080228300A2B1DD00B2B01D0012303E04FF4807322
+S3150802284000E00123B0FBF3F0002689E70223F9E74B
+S315080228500423F7E70623F5E70823F3E70A23F1E754
+S315080228600C23EFE71023EDE72023EBE74023E9E704
+S315080228708023E7E7A04B1B6813F0200F3BD09E4B43
+S315080228801B68C3F3C1039D48D840636AC3B1012BD1
+S315080228901BD0022B1BD0032B1BD0042B1BD0052BC2
+S315080228A01BD0062B1BD0072B1BD0082B1BD0092BA2
+S315080228B01BD00A2B1BD00B2B1BD14FF4807300E0C5
+S315080228C00123B0FBF3F000264AE70223F9E70423C3
+S315080228D0F7E70623F5E70823F3E70A23F1E70C23CC
+S315080228E0EFE71023EDE72023EBE74023E9E7802310
+S315080228F0E7E70123E5E7636A002B58D0012B59D095
+S31508022900022B5AD0032B5BD0042B5CD0052B5DD04F
+S31508022910062B5ED0072B5FD0082B60D0092B61D01F
+S315080229200A2B62D00B2B63D17548002618E7636A17
+S31508022930002B60D0012B61D0022B62D0032B63D00F
+S31508022940042B64D0052B65D0062B66D0072B67D0DF
+S31508022950082B68D0092B69D00A2B6BD00B2B02D017
+S3150802296068480026FCE643F609500026F8E6636A3C
+S31508022970002B63D0012B65D0022B67D0032B69D0BD
+S31508022980042B6BD0052B6DD0062B6FD0072B71D07D
+S31508022990082B73D0092B75D00A2B77D00B2B03D0B3
+S315080229A04FF400400026DBE680200026D8E653488E
+S315080229B00026D5E654480026D2E654480026CFE635
+S315080229C053480026CCE653480026C9E65248002654
+S315080229D0C6E652480026C3E64A480026C0E65048DC
+S315080229E00026BDE64F480026BAE64F480026B7E657
+S315080229F042480026B4E643480026B1E6484800267F
+S31508022A00AEE648480026ABE648480026A8E6464809
+S31508022A100026A5E646480026A2E6464800269FE680
+S31508022A20374800269CE64448002699E64FF2244099
+S31508022A30002695E647F61220002691E64FF4004056
+S31508022A4000268DE64FF48040002689E64FF40050B2
+S31508022A50002685E641F25550002681E64FF480505D
+S31508022A6000267DE640F6CC40002679E640F6AA2006
+S31508022A70002675E64FF40060002671E64FF4806082
+S31508022A8000266DE64FF40070002669E64FF4807062
+S31508022A90002665E6022D51D0042D7FF47CAE03A8EC
+S31508022AA0FFF736FA0498636A002B00F0AA80012B16
+S31508022AB000F0BE80022B00F0BE80032B00F0BE8021
+S31508022AC0042B00F0BE80052B00F0BE80062B00F01A
+S31508022AD0BE80072B00F0BE80082B00F0BE80092BB3
+S31508022AE000F0BE800A2B00F0BE800B2B00F085801A
+S31508022AF00122002387E000BF004402580090D00359
+S31508022B0090D0030000093D000048E8010024F400C3
+S31508022B10AAC2A20000127A0000A8610055615100FB
+S31508022B2080841E0040420F0020A107002A2C0A00BA
+S31508022B30801A06001516050048E80100FFF7D6F9BF
+S31508022B40636AE3B1012B3AD0022B3BD0032B3CD06C
+S31508022B50042B3DD0052B3ED0062B3FD0072B40D069
+S31508022B60082B41D0092B42D00A2B43D00B2B02D07B
+S31508022B700122002305E04FF48072002301E00122BE
+S31508022B8000230021FDF7ACFB4FEA012949EA106947
+S31508022B904FEA002862685008002318EB000B49F137
+S31508022BA0000C58466146FDF79BFBA0F54072B44BF4
+S31508022BB09A4200F2D3862368D86000F0C4BC022287
+S31508022BC00023DEE704220023DBE706220023D8E7F8
+S31508022BD008220023D5E70A220023D2E70C22002383
+S31508022BE0CFE710220023CCE720220023C9E74022A0
+S31508022BF00023C6E780220023C3E74FF4807200232E
+S31508022C0001E0012200230021FDF76AFB4FEA0129B0
+S31508022C1049EA10694FEA002862685008002318EB4F
+S31508022C20000B49F1000C58466146FDF759FBBCE713
+S31508022C3002220023E7E704220023E4E70622002310
+S31508022C40E1E708220023DEE70A220023DBE70C225B
+S31508022C500023D8E710220023D5E720220023D2E753
+S31508022C6040220023CFE780220023CCE76846FFF7FD
+S31508022C704BFA0198636AE3B1012B31D0022B32D0A9
+S31508022C80032B33D0042B34D0052B35D0062B36D064
+S31508022C90072B37D0082B38D0092B39D00A2B3AD034
+S31508022CA00B2B02D00122002305E04FF48072002389
+S31508022CB001E0012200230021FDF712FB4FEA012958
+S31508022CC049EA10694FEA002862685008002318EB9F
+S31508022CD0000B49F1000C58466146FDF701FB64E713
+S31508022CE002220023E7E704220023E4E70622002360
+S31508022CF0E1E708220023DEE70A220023DBE70C22AB
+S31508022D000023D8E710220023D5E720220023D2E7A2
+S31508022D1040220023CFE780220023CCE7594B1B68C9
+S31508022D2013F0200F59D0574B1B68C3F3C1035648FB
+S31508022D30D840636ACBB1012B2ED0022B2FD0032B9E
+S31508022D4030D0042B31D0052B32D0062B33D0072BAB
+S31508022D5034D0082B35D0092B36D00A2B37D00B2B7B
+S31508022D6038D14FF48072002301E0012200230021AA
+S31508022D70FDF7B6FA4FEA012949EA10694FEA00282F
+S31508022D8078083A46002318EB000B49F1000C58461E
+S31508022D906146FDF7A5FA08E702220023E7E70422BF
+S31508022DA00023E4E706220023E1E708220023DEE700
+S31508022DB00A220023DBE70C220023D8E7102200238D
+S31508022DC0D5E720220023D2E740220023CFE780223C
+S31508022DD00023CCE701220023C9E7636AC3B1012BAA
+S31508022DE021D0022B22D0032B23D0042B25D0052B4E
+S31508022DF026D0062B27D0072B29D0082B2AD0092B19
+S31508022E002BD00A2B2CD00B2B2DD11F48002101E0E9
+S31508022E101E4803217D083A460023401941F1000164
+S31508022E20FDF75EFAC1E61A480121F3E719480021BF
+S31508022E30F0E70FA1D1E90001ECE717480021E9E71D
+S31508022E4016480021E6E70CA1D1E90001E2E7144899
+S31508022E500021DFE713480021DCE713480021D9E700
+S31508022E6012480021D6E709480321D3E7AFF30080C9
+S31508022E7000AAC2A20000000000556151000000002D
+S31508022E80FFFC0F00004402580090D003000090D0C7
+S31508022E90000048E8000024F40000127A0000A86145
+S31508022EA00000093D0080841E0040420F0020A10751
+S31508022EB0636ADBB1012B24D0022B25D0032B26D043
+S31508022EC0042B28D0052B29D0062B2AD0072B2CD049
+S31508022ED0082B2DD0092B2ED00A2B2FD00B2B02D044
+S31508022EE09F48002104E09F48002101E09C480021F8
+S31508022EF07D083A460023401941F10001FDF7F0F931
+S31508022F0053E699480021F3E798480021F0E790A193
+S31508022F10D1E90001ECE796480021E9E79548002146
+S31508022F20E6E78DA1D1E90001E2E793480021DFE750
+S31508022F3092480021DCE792480021D9E7914800210E
+S31508022F40D6E7636AEBB1012B27D0022B29D0032BD4
+S31508022F502BD0042B2CD0052B2ED0062B2FD0072BAB
+S31508022F6030D0082B32D0092B34D00A2B36D00B2B73
+S31508022F7003D04FF40000002106E04FF40040002180
+S31508022F8002E04FF4000000217D083A46002340196A
+S31508022F9041F10001FDF7A4F907E64FF4800000218C
+S31508022FA0F2E74FF400100021EEE777480021EBE73D
+S31508022FB04FF480100021E7E774480021E4E77448DB
+S31508022FC00021E1E74FF400200021DDE74FF48020DD
+S31508022FD00021D9E74FF400300021D5E74FF48030BD
+S31508022FE00021D1E7402D00F27982DFE815F0410091
+S31508022FF08F0077027702F3007702770277023401AD
+S3150802300077027702770277027702770277027501EB
+S3150802301077027702770277027702770277027702D8
+S315080230207702770277027702770277027702F6014A
 S3150802303077027702770277027702770277027702B8
 S3150802304077027702770277027702770277027702A8
-S3150802305077027702770277027702770277023102DE
-S31508023060FEF718FF636AD3B1012B33D0022B33D094
-S31508023070032B33D0042B33D0052B33D0062B33D076
-S31508023080072B33D0082B33D0092B33D00A2B33D056
-S315080230900B2B01D0012303E04FF4807300E00123D8
-S315080230A0B0FBF3F06268530803EB4003B3FBF2F399
-S315080230B09BB20026A3F110014FF6EF72914200F27D
-S315080230C047849AB222F00F02C3F3420313432268DB
-S315080230D0D36030E20223E3E70423E1E70623DFE7CE
-S315080230E00823DDE70A23DBE70C23D9E71023D7E712
-S315080230F02023D5E74023D3E78023D1E7FEF7DCFE7A
-S31508023100636A002B3ED0012B48D0022B48D0032BF2
-S3150802311048D0042B48D0052B48D0062B48D0072B7D
-S3150802312048D0082B48D0092B48D00A2B48D00B2B5D
-S3150802313001D0012327E04FF4807324E0AFF3008027
-S31508023140002A2C0A000000000015160500000000DF
-S315080231500000093D00093D000080841E0040420F20
-S315080231600020A10700801A060090D0030048E80153
-S315080231700024F40000127A000055150000CC0C0059
-S3150802318000AA0A000123B0FBF3F06268530803EBB6
-S315080231904003B3FBF2F39BB200268BE70223F2E766
-S315080231A00423F0E70623EEE70823ECE70A23EAE717
-S315080231B00C23E8E71023E6E72023E4E74023E2E7C7
-S315080231C08023E0E703A8FEF79BFE049B626AD2B15E
-S315080231D0012A24D0022A24D0032A24D0042A24D05D
-S315080231E0052A24D0062A24D0072A24D0082A24D03D
-S315080231F0092A24D00A2A24D00B2A01D0012203E064
-S315080232004FF4807200E00122B3FBF2F261684B08C8
-S3150802321003EB4203B3FBF1F39BB200264AE7022211
-S31508023220F2E70422F0E70622EEE70822ECE70A2292
-S31508023230EAE70C22E8E71022E6E72022E4E7402242
-S31508023240E2E78022E0E76846FEF756FF019B626ADC
-S31508023250D2B1012A24D0022A24D0032A24D0042A4D
-S3150802326024D0052A24D0062A24D0072A24D0082ABC
-S3150802327024D0092A24D00A2A24D00B2A01D00122D2
-S3150802328003E04FF4807200E00122B3FBF2F26168B8
-S315080232904B0803EB4203B3FBF1F39BB2002609E7A3
-S315080232A00222F2E70422F0E70622EEE70822ECE71A
-S315080232B00A22EAE70C22E8E71022E6E72022E4E7F8
-S315080232C04022E2E78022E0E7A34B1B6813F0200FB7
-S315080232D042D0A14B1A68C2F3C102A04BD340626A1C
-S315080232E0D2B1012A24D0022A24D0032A24D0042ABD
-S315080232F024D0052A24D0062A24D0072A24D0082A2C
-S3150802330024D0092A24D00A2A24D00B2A01D0012241
-S3150802331003E04FF4807200E00122B3FBF2F2616827
-S315080233204B0803EB4203B3FBF1F39BB20026C1E65B
-S315080233300222F2E70422F0E70622EEE70822ECE789
-S315080233400A22EAE70C22E8E71022E6E72022E4E767
-S315080233504022E2E78022E0E7636ACBB1012B20D064
-S31508023360022B20D0032B20D0042B20D0052B20D0D3
-S31508023370062B20D0072B20D0082B20D0092B20D0B3
-S315080233800A2B20D00B2B01D0754B02E0754B00E0BF
-S31508023390734B626803EB5203B3FBF2F39BB200264C
-S315080233A088E66E4BF5E7704BF3E7704BF1E7704B27
-S315080233B0EFE7704BEDE7704BEBE7704BE9E7704BC5
-S315080233C0E7E7704BE5E7704BE3E7636AD3B1012B96
-S315080233D021D0022B21D0032B21D0042B21D0052B5F
-S315080233E021D0062B21D0072B21D0082B21D0092B3F
-S315080233F021D00A2B21D00B2B01D0604B03E047F6D4
-S31508023400122300E05D4B626803EB5203B3FBF2F34F
-S315080234109BB200264EE65A4BF5E75A4BF3E75B4B4F
-S31508023420F1E7594BEFE75A4BEDE75A4BEBE74D4BB2
-S31508023430E9E7594BE7E7594BE5E74FF22443E2E759
-S31508023440636ADBB1012B23D0022B24D0032B25D0B0
-S31508023450042B26D0052B27D0062B28D0072B29D0BC
-S31508023460082B2AD0092B2BD00A2B2CD00B2B02D0B7
-S315080234704FF4803304E04FF4807301E04FF4803355
-S31508023480626803EB5203B3FBF2F39BB2002611E622
-S315080234904FF40043F4E74FF48043F1E742F6AA23D8
-S315080234A0EEE74FF40053EBE741F69813E8E741F2EB
-S315080234B05453E5E74FF48053E2E74FF40063DFE73E
-S315080234C04FF48063DCE74FF40073D9E70126002343
-S315080234D0F0E5FEF7DFFC636AD3B1012B37D0022B86
-S315080234E037D0032B5CD0042B5CD0052B5CD0062B83
-S315080234F05CD0072B5CD0082B5CD0092B5CD00A2B3E
-S315080235005CD00B2B01D0012303E04FF4807300E05B
-S315080235100123B0FBF3F3626803EB5203B3FBF2F346
-S315080235209BB20026A3F110014FF6EF72914200F208
-S3150802353011822268D3600123A4F86A30A4F868309D
-S315080235400023E3662367304606B0BDE8F08B022304
-S31508023550DFE70423DDE700BF004402580090D003EA
-S315080235600020A10720A107000048E801548545016B
-S315080235700024F4000050C300AAC2A20000127A0076
-S3150802358000093D0080841E0040420F005458140072
-S3150802359000350C002A2C0A0090D0030048E80100E6
-S315080235A00623B6E70823B4E70A23B2E70C23B0E7F3
-S315080235B01023AEE72023ACE74023AAE78023A8E737
-S315080235C0FEF77AFC636AD3B1012B23D0022B23D0F0
-S315080235D0032B23D0042B23D0052B23D0062B23D051
-S315080235E0072B23D0082B23D0092B23D00A2B23D031
-S315080235F00B2B01D0012303E04FF4807300E0012373
-S31508023600B0FBF3F3626803EB5203B3FBF2F39BB22C
-S31508023610002687E70223F3E70423F1E70623EFE709
-S315080236200823EDE70A23EBE70C23E9E71023E7E78C
-S315080236302023E5E74023E3E78023E1E703A8FEF733
-S315080236405FFC049B626AD2B1012A23D0022A23D0E4
-S31508023650032A23D0042A23D0052A23D0062A23D0D4
-S31508023660072A23D0082A23D0092A23D00A2A23D0B4
-S315080236700B2A01D0012203E04FF4807200E00122F6
-S31508023680B3FBF2F3626803EB5203B3FBF2F39BB2AA
-S31508023690002647E70222F3E70422F1E70622EFE7CC
-S315080236A00822EDE70A22EBE70C22E9E71022E7E710
-S315080236B02022E5E74022E3E78022E1E76846FEF7B3
-S315080236C01BFD019B626AD2B1012A23D0022A23D0AA
-S315080236D0032A23D0042A23D0052A23D0062A23D054
-S315080236E0072A23D0082A23D0092A23D00A2A23D034
-S315080236F00B2A01D0012203E04FF4807200E0012276
-S31508023700B3FBF2F3626803EB5203B3FBF2F39BB229
-S31508023710002607E70222F3E70422F1E70622EFE78B
-S315080237200822EDE70A22EBE70C22E9E71022E7E78F
-S315080237302022E5E74022E3E78022E1E7864B1B6881
-S3150802374013F0200F41D0844B1A68C2F3C102834B8F
-S31508023750D340626AD2B1012A23D0022A23D0032A8D
-S3150802376023D0042A23D0052A23D0062A23D0072ABF
-S3150802377023D0082A23D0092A23D00A2A23D00B2A9F
-S3150802378001D0012203E04FF4807200E00122B3FB6C
-S31508023790F2F3626803EB5203B3FBF2F39BB2002621
-S315080237A0C0E60222F3E70422F1E70622EFE708223F
-S315080237B0EDE70A22EBE70C22E9E71022E7E72022E7
-S315080237C0E5E74022E3E78022E1E7636ACBB1012B12
-S315080237D020D0022B20D0032B20D0042B20D0052B5F
-S315080237E020D0062B20D0072B20D0082B20D0092B3F
-S315080237F020D00A2B20D00B2B01D0584B02E0584B75
-S3150802380000E0564B626803EB5203B3FBF2F39BB23A
-S31508023810002687E6534BF5E7534BF3E7534BF1E79D
-S31508023820534BEFE7534BEDE7534BEBE7534BE9E7C4
-S31508023830534BE7E7534BE5E7534BE3E7636AD3B1E9
-S31508023840012B21D0022B21D0032B21D0042B21D0EE
-S31508023850052B21D0062B21D0072B21D0082B21D0CE
-S31508023860092B21D00A2B22D00B2B01D0434B03E084
-S3150802387043F6095300E0414B626803EB5203B3FB7C
-S31508023880F2F39BB200264DE63D4BF5E73D4BF3E7D7
-S315080238903E4BF1E73C4BEFE73D4BEDE73D4BEBE7A4
-S315080238A02F4BE9E73C4BE7E74FF22443E4E747F6B9
-S315080238B01223E1E7636AD3B1012B22D0022B23D06C
-S315080238C0032B24D0042B25D0052B26D0062B27D054
-S315080238D0072B28D0082B29D0092B2AD00A2B2BD024
-S315080238E00B2B02D04FF4004303E0802301E04FF490
-S315080238F00043626803EB5203B3FBF2F39BB2002662
-S3150802390010E64FF48043F4E74FF40053F1E741F22F
-S315080239105553EEE74FF48053EBE740F6CC43E8E71E
-S3150802392040F6AA23E5E74FF40063E2E74FF4806323
-S31508023930DFE74FF40073DCE74FF48073D9E701261B
-S315080239400023EFE50126F6E50126F4E50126F2E570
-S315080239500126F0E50126EEE5004402580090D00360
-S3150802396090D003000048E8010024F400AAC2A2008D
-S3150802397000127A0000A861005561510000093D0055
-S3150802398080841E0040420F0020A107002A2C0A004C
-S31508023990801A06001516050048E80100836A13F026
-S315080239A0010F06D00268536823F40033C16A0B4339
-S315080239B05360836A13F0020F06D00268536823F431
-S315080239C08033016B0B435360836A13F0040F06D0EE
-S315080239D00268536823F48023416B0B435360836A5E
-S315080239E013F0080F06D00268536823F40043816B6C
-S315080239F00B435360836A13F0100F06D0026893686C
-S31508023A0023F48053C16B0B439360836A13F0200F30
-S31508023A1006D00268936823F40053016C0B43936043
-S31508023A20836A13F0400F0AD00268536823F480139E
-S31508023A30416C0B435360436CB3F5801F0BD0836A0A
-S31508023A4013F0800F06D00268536823F40023C16C72
-S31508023A500B43536070470268536823F4C003816CB2
-S31508023A600B435360EBE72DE9F04104460F46164631
-S31508023A709846069D2368DB6937EA03030CBF0123D0
-S31508023A800023B34241D1B5F1FF3FF3D0FCF77CFFE7
-S31508023A90A0EB0800854223D315B323681A6812F0EF
-S31508023AA0040FE7D0DA6912F4006FE3D04FF400622C
-S31508023AB01A622268136823F4D07313602268936823
-S31508023AC023F0010393602023C4F88030C4F88430BD
-S31508023AD0C4F88830002384F87C300320BDE8F081DE
-S31508023AE02268136823F4D07313602268936823F05C
-S31508023AF0010393602023C4F88030C4F8843000237D
-S31508023B0084F87C300320BDE8F0810020BDE8F0810E
-S31508023B102DE9F04383B01E46D0F88430202B03D01B
-S31508023B20022003B0BDE8F08304460D469046002AFB
-S31508023B3018BF002979D090F87C30012B01D10220D8
-S31508023B40EFE7012380F87C300023C0F8883022236F
-S31508023B50C0F88430FCF718FF0746A4F85C80A4F87E
-S31508023B605E80A368B3F5805F06D0A3B9226972B9ED
-S31508023B70FF22A4F8602014E0226922B940F2FF125B
-S31508023B80A4F860200DE0FF22A4F8602009E07F2255
-S31508023B90A4F8602005E0B3F1805F0AD00022A4F8F9
-S31508023BA06020B4F86080B3F5805F0CD04FF000094E
-S31508023BB01EE022691AB97F22A4F86020F1E73F22A3
-S31508023BC0A4F86020EDE7236913B14FF000090FE06E
-S31508023BD0A94600250CE023685B6A08EA030329F86C
-S31508023BE0023BB4F85E309BB2013B9BB2A4F85E304E
-S31508023BF0B4F85E309BB28BB100963B460022202178
-S31508023C002046FFF730FF90B9002DE4D023685A6AA0
-S31508023C105FFA88F3134005F8013BE2E72023C4F86C
-S31508023C208430002084F87C007BE7012079E70320B2
-S31508023C3077E730B583B004460023C0F88830FCF72E
-S31508023C40A3FE054623681B6813F0080F0ED12368E6
-S31508023C501B6813F0040F17D12023C4F88030C4F868
-S31508023C608430002084F87C0003B030BD6FF07E43B8
-S31508023C700093034600224FF400112046FFF7F3FE95
-S31508023C800028E4D00320EFE76FF07E4300932B462B
-S31508023C9000224FF480012046FFF7E5FE0028DBD01C
-S31508023CA00320E1E778B310B50446D0F880300BB3A9
-S31508023CB02423C4F880302268136823F001031360B2
-S31508023CC02046FEF719FB01281FD0A36ABBB9226852
-S31508023CD0536823F4904353602268936823F02A03B7
-S31508023CE093602268136843F0010313602046FFF7C6
-S31508023CF0A0FF10BD80F87C30FEF7FAFAD8E7204616
-S31508023D00FFF74CFEE3E70120704710BD184AD2F8C8
-S31508023D10883043F47003C2F88830164B1A6842F0AA
-S31508023D2001021A6000221A611868134901401960D3
-S31508023D309A61DA611A629A62DA621A635A639A6352
-S31508023D40DA631A645A64196821F4802119601A66BA
-S31508023D500A4B1A680A4B1340B3F1005F02D20122DA
-S31508023D60084B1A604FF00062014B9A60704700BF19
-S31508023D7000ED00E0004402587FEDF6EA0010005C10
-S31508023D800000FFFF0881005110B4674B1B6903F05E
-S31508023D903803102B00F0C580182B1ED0B3B1634A26
-S31508023DA061488369C3F303236149CB5CDA408369BB
-S31508023DB003F00F03CB5C03F01F0322FA03F35D49FA
-S31508023DC00B605D4B1A605DF8044B7047564B1B68D7
-S31508023DD0C3F3C103594ADA40E2E75349886A00F055
-S31508023DE003008A6AC2F30512CC6A04F001044B6B1B
-S31508023DF0C3F3CC0303FB04F307EE903AF8EE677AB3
-S31508023E00002ACDD0012852D0F0B102286CD007EE94
-S31508023E10102AF8EE476A9FED4A6A86EE267A424BE0
-S31508023E201B6BC3F3080306EE903AF8EE666A9FED3B
-S31508023E30456A67EE867A76EEA77AF7EE006A77EE35
-S31508023E40A67A27EE277A22E037480168C1F3C1012C
-S31508023E503A4BCB4007EE103AF8EE476A07EE102ABD
-S31508023E60B8EE476A86EE867A036BC3F3080306EE54
-S31508023E70903AF8EE666A9FED336A67EE867A76EED0
-S31508023E80A77AF7EE006A77EEA67A27EE277A264B06
-S31508023E901B6BC3F34623013307EE903AF8EE677AB3
-S31508023EA0C7EE276AFCEEE67A17EE902A78E707EE5F
-S31508023EB0102AF8EE476A9FED226A86EE267A1A4B90
-S31508023EC01B6BC3F3080306EE903AF8EE666A9FED9B
-S31508023ED01D6A67EE867A76EEA77AF7EE006A77EEBD
-S31508023EE0A67A27EE277AD2E707EE102AF8EE476A6D
-S31508023EF09FED156A86EE267A0B4B1B6BC3F30803F6
-S31508023F0006EE903AF8EE666A9FED0E6A67EE867AD4
-S31508023F1076EEA77AF7EE006A77EEA67A27EE277A82
-S31508023F20B5E70A4A3CE700BF0044025800093D00CB
-S31508023F30384302080C000020080000200090D00335
-S31508023F400024744A000000390024F44A00127A0058
-S31508023F50014B024A9A60704700ED00E00000020831
-S31508023F6000B59DB04C22002109A800F090F9202244
-S31508023F70002101A800F08BF90220FDF707FA0023B9
-S31508023F800093254B9A6942F440429A619B6903F46D
-S31508023F9040430093214BDA6A42F00102DA62DB6A95
-S31508023FA003F001030093009B1B4B9B6913F4005F0C
-S31508023FB0FAD0012309934FF4A0230A9302231293FA
-S31508023FC01393042214924FF4F071159116931792D3
-S31508023FD01893199200231A931B9309A8FDF700FA5E
-S31508023FE000B1FEE73F2301930323029300230393C1
-S31508023FF0082304934023059306934FF4806207929D
-S31508024000089304210DEB0100FDF7DAFD00B1FEE786
-S315080240101DB05DF804FB00BF0048025800040058B2
-S3150802402008B5FFF795FFFCF775FCFFF799FF00F057
-S31508024030DBF8FCF717FC08BD08B5FFF7F1FFFCF73C
-S315080240407BFBFCF719FCFCF707FCFAE7F0B58DB029
-S315080240504D4BD3F8F42042F00202C3F8F420D3F809
-S31508024060F42002F002020192019AD3F8E02042F00B
-S315080240700202C3F8E020D3F8E02002F0020202921C
-S31508024080029AD3F8E02042F00402C3F8E020D3F8FB
-S31508024090E02002F004020392039AD3F8E02042F0E9
-S315080240A00802C3F8E020D3F8E02002F008020492DE
-S315080240B0049AD3F8E82042F48022C3F8E820D3F819
-S315080240C0E82002F480220592059AD3F8EC2042F4FD
-S315080240D08072C3F8EC20D3F8EC3003F480730693AD
-S315080240E0069B0320FCF75CFC002211466FF00B00CE
-S315080240F0FCF768FC002211466FF00A00FCF762FC26
-S31508024100002211466FF00900FCF75CFC00221146FA
-S315080241106FF00400FCF756FC002211466FF003000C
-S31508024120FCF750FC002211466FF00100FCF74AFC2E
-S31508024130002211464FF0FF30FCF744FC8023079318
-S3150802414001230893002409940A94104D07A92846C6
-S31508024150FDF71EF84FF4407707970226089609944A
-S315080241600A9407230B9307A90948FDF711F807973D
-S31508024170089609940A9409230B9307A92846FDF77A
-S3150802418007F80DB0F0BD00BF0044025800040258FB
-S31508024190000C0258DFF834D0002103E00C4B5B58C0
-S315080241A0435004310B480C4B42189A42F6D30B4A39
-S315080241B002E0002342F8043B094B9A42F9D3FFF77F
-S315080241C0A5FD00F035F8FFF737FF7047000002201B
-S315080241D058430208000000201000002010000020AA
-S315080241E0AC010020FEE7000008B5FFF7CDFD094B3C
-S315080241F01868094BA3FB00308009FCF713FC04205E
-S31508024200FCF726FC002211464FF0FF30FCF7DAFBDA
-S3150802421008BD00BF08000020D34D621008B5FCF7A0
-S31508024220B3FB08BD08B5FCF7A3FBFCF722FC08BDE7
-S3150802423070B50D4E0D4CA41BA4100025A54209D13C
-S315080242400B4E0C4C00F02CF8A41BA4100025A5421A
-S3150802425005D170BD56F8253098470135EEE756F870
-S31508024260253098470135F2E75043020850430208C1
-S31508024270504302085443020810B5431E0A449142A9
-S3150802428000D110BD11F8014B03F8014FF7E70244BC
-S315080242900346934200D1704703F8011BF9E7000071
-S315080242A0F8B500BFF8BC08BC9E467047F8B500BF13
-S30D080242B0F8BC08BC9E467047E3
-S315080242B800000000000000000000000000000000E6
-S315080242C800000000010000000200000003000000D0
-S315080242D804000000000000000500000000000000BD
-S315080242E800000000000000000600000000000000B0
-S315080242F80000000000000000070000000502060290
-S31508024308060307030803090309040A040B040C0431
-S315080243180C050D050E050F050F06100610071008E1
-S315080243280001020304050607080C10141820304079
-S315080243380000000001020304010203040607080933
-S30D08024348C8BFFF7F0100000057
-S30908024350C502020888
-S30908024354A1020208A8
-S3150802435801000000100000000090D0030090D0036E
-S705080241951A
+S315080230507702770277027702770277027702770298
+S3150802306077027702770277027702770277023102CE
+S31508023070FEF718FF636AD3B1012B33D0022B33D084
+S31508023080032B33D0042B33D0052B33D0062B33D066
+S31508023090072B33D0082B33D0092B33D00A2B33D046
+S315080230A00B2B01D0012303E04FF4807300E00123C8
+S315080230B0B0FBF3F06268530803EB4003B3FBF2F389
+S315080230C09BB20026A3F110014FF6EF72914200F26D
+S315080230D047849AB222F00F02C3F3420313432268CB
+S315080230E0D36030E20223E3E70423E1E70623DFE7BE
+S315080230F00823DDE70A23DBE70C23D9E71023D7E702
+S315080231002023D5E74023D3E78023D1E7FEF7DCFE69
+S31508023110636A002B3ED0012B48D0022B48D0032BE2
+S3150802312048D0042B48D0052B48D0062B48D0072B6D
+S3150802313048D0082B48D0092B48D00A2B48D00B2B4D
+S3150802314001D0012327E04FF4807324E0AFF3008017
+S31508023150002A2C0A000000000015160500000000CF
+S315080231600000093D00093D000080841E0040420F10
+S315080231700020A10700801A060090D0030048E80143
+S315080231800024F40000127A000055150000CC0C0049
+S3150802319000AA0A000123B0FBF3F06268530803EBA6
+S315080231A04003B3FBF2F39BB200268BE70223F2E756
+S315080231B00423F0E70623EEE70823ECE70A23EAE707
+S315080231C00C23E8E71023E6E72023E4E74023E2E7B7
+S315080231D08023E0E703A8FEF79BFE049B626AD2B14E
+S315080231E0012A24D0022A24D0032A24D0042A24D04D
+S315080231F0052A24D0062A24D0072A24D0082A24D02D
+S31508023200092A24D00A2A24D00B2A01D0012203E053
+S315080232104FF4807200E00122B3FBF2F261684B08B8
+S3150802322003EB4203B3FBF1F39BB200264AE7022201
+S31508023230F2E70422F0E70622EEE70822ECE70A2282
+S31508023240EAE70C22E8E71022E6E72022E4E7402232
+S31508023250E2E78022E0E76846FEF756FF019B626ACC
+S31508023260D2B1012A24D0022A24D0032A24D0042A3D
+S3150802327024D0052A24D0062A24D0072A24D0082AAC
+S3150802328024D0092A24D00A2A24D00B2A01D00122C2
+S3150802329003E04FF4807200E00122B3FBF2F26168A8
+S315080232A04B0803EB4203B3FBF1F39BB2002609E793
+S315080232B00222F2E70422F0E70622EEE70822ECE70A
+S315080232C00A22EAE70C22E8E71022E6E72022E4E7E8
+S315080232D04022E2E78022E0E7A34B1B6813F0200FA7
+S315080232E042D0A14B1A68C2F3C102A04BD340626A0C
+S315080232F0D2B1012A24D0022A24D0032A24D0042AAD
+S3150802330024D0052A24D0062A24D0072A24D0082A1B
+S3150802331024D0092A24D00A2A24D00B2A01D0012231
+S3150802332003E04FF4807200E00122B3FBF2F2616817
+S315080233304B0803EB4203B3FBF1F39BB20026C1E64B
+S315080233400222F2E70422F0E70622EEE70822ECE779
+S315080233500A22EAE70C22E8E71022E6E72022E4E757
+S315080233604022E2E78022E0E7636ACBB1012B20D054
+S31508023370022B20D0032B20D0042B20D0052B20D0C3
+S31508023380062B20D0072B20D0082B20D0092B20D0A3
+S315080233900A2B20D00B2B01D0754B02E0754B00E0AF
+S315080233A0734B626803EB5203B3FBF2F39BB200263C
+S315080233B088E66E4BF5E7704BF3E7704BF1E7704B17
+S315080233C0EFE7704BEDE7704BEBE7704BE9E7704BB5
+S315080233D0E7E7704BE5E7704BE3E7636AD3B1012B86
+S315080233E021D0022B21D0032B21D0042B21D0052B4F
+S315080233F021D0062B21D0072B21D0082B21D0092B2F
+S3150802340021D00A2B21D00B2B01D0604B03E047F6C3
+S31508023410122300E05D4B626803EB5203B3FBF2F33F
+S315080234209BB200264EE65A4BF5E75A4BF3E75B4B3F
+S31508023430F1E7594BEFE75A4BEDE75A4BEBE74D4BA2
+S31508023440E9E7594BE7E7594BE5E74FF22443E2E749
+S31508023450636ADBB1012B23D0022B24D0032B25D0A0
+S31508023460042B26D0052B27D0062B28D0072B29D0AC
+S31508023470082B2AD0092B2BD00A2B2CD00B2B02D0A7
+S315080234804FF4803304E04FF4807301E04FF4803345
+S31508023490626803EB5203B3FBF2F39BB2002611E612
+S315080234A04FF40043F4E74FF48043F1E742F6AA23C8
+S315080234B0EEE74FF40053EBE741F69813E8E741F2DB
+S315080234C05453E5E74FF48053E2E74FF40063DFE72E
+S315080234D04FF48063DCE74FF40073D9E70126002333
+S315080234E0F0E5FEF7DFFC636AD3B1012B37D0022B76
+S315080234F037D0032B5CD0042B5CD0052B5CD0062B73
+S315080235005CD0072B5CD0082B5CD0092B5CD00A2B2D
+S315080235105CD00B2B01D0012303E04FF4807300E04B
+S315080235200123B0FBF3F3626803EB5203B3FBF2F336
+S315080235309BB20026A3F110014FF6EF72914200F2F8
+S3150802354011822268D3600123A4F86A30A4F868308D
+S315080235500023E3662367304606B0BDE8F08B0223F4
+S31508023560DFE70423DDE700BF004402580090D003DA
+S315080235700020A10720A107000048E801548545015B
+S315080235800024F4000050C300AAC2A20000127A0066
+S3150802359000093D0080841E0040420F005458140062
+S315080235A000350C002A2C0A0090D0030048E80100D6
+S315080235B00623B6E70823B4E70A23B2E70C23B0E7E3
+S315080235C01023AEE72023ACE74023AAE78023A8E727
+S315080235D0FEF77AFC636AD3B1012B23D0022B23D0E0
+S315080235E0032B23D0042B23D0052B23D0062B23D041
+S315080235F0072B23D0082B23D0092B23D00A2B23D021
+S315080236000B2B01D0012303E04FF4807300E0012362
+S31508023610B0FBF3F3626803EB5203B3FBF2F39BB21C
+S31508023620002687E70223F3E70423F1E70623EFE7F9
+S315080236300823EDE70A23EBE70C23E9E71023E7E77C
+S315080236402023E5E74023E3E78023E1E703A8FEF723
+S315080236505FFC049B626AD2B1012A23D0022A23D0D4
+S31508023660032A23D0042A23D0052A23D0062A23D0C4
+S31508023670072A23D0082A23D0092A23D00A2A23D0A4
+S315080236800B2A01D0012203E04FF4807200E00122E6
+S31508023690B3FBF2F3626803EB5203B3FBF2F39BB29A
+S315080236A0002647E70222F3E70422F1E70622EFE7BC
+S315080236B00822EDE70A22EBE70C22E9E71022E7E700
+S315080236C02022E5E74022E3E78022E1E76846FEF7A3
+S315080236D01BFD019B626AD2B1012A23D0022A23D09A
+S315080236E0032A23D0042A23D0052A23D0062A23D044
+S315080236F0072A23D0082A23D0092A23D00A2A23D024
+S315080237000B2A01D0012203E04FF4807200E0012265
+S31508023710B3FBF2F3626803EB5203B3FBF2F39BB219
+S31508023720002607E70222F3E70422F1E70622EFE77B
+S315080237300822EDE70A22EBE70C22E9E71022E7E77F
+S315080237402022E5E74022E3E78022E1E7864B1B6871
+S3150802375013F0200F41D0844B1A68C2F3C102834B7F
+S31508023760D340626AD2B1012A23D0022A23D0032A7D
+S3150802377023D0042A23D0052A23D0062A23D0072AAF
+S3150802378023D0082A23D0092A23D00A2A23D00B2A8F
+S3150802379001D0012203E04FF4807200E00122B3FB5C
+S315080237A0F2F3626803EB5203B3FBF2F39BB2002611
+S315080237B0C0E60222F3E70422F1E70622EFE708222F
+S315080237C0EDE70A22EBE70C22E9E71022E7E72022D7
+S315080237D0E5E74022E3E78022E1E7636ACBB1012B02
+S315080237E020D0022B20D0032B20D0042B20D0052B4F
+S315080237F020D0062B20D0072B20D0082B20D0092B2F
+S3150802380020D00A2B20D00B2B01D0584B02E0584B64
+S3150802381000E0564B626803EB5203B3FBF2F39BB22A
+S31508023820002687E6534BF5E7534BF3E7534BF1E78D
+S31508023830534BEFE7534BEDE7534BEBE7534BE9E7B4
+S31508023840534BE7E7534BE5E7534BE3E7636AD3B1D9
+S31508023850012B21D0022B21D0032B21D0042B21D0DE
+S31508023860052B21D0062B21D0072B21D0082B21D0BE
+S31508023870092B21D00A2B22D00B2B01D0434B03E074
+S3150802388043F6095300E0414B626803EB5203B3FB6C
+S31508023890F2F39BB200264DE63D4BF5E73D4BF3E7C7
+S315080238A03E4BF1E73C4BEFE73D4BEDE73D4BEBE794
+S315080238B02F4BE9E73C4BE7E74FF22443E4E747F6A9
+S315080238C01223E1E7636AD3B1012B22D0022B23D05C
+S315080238D0032B24D0042B25D0052B26D0062B27D044
+S315080238E0072B28D0082B29D0092B2AD00A2B2BD014
+S315080238F00B2B02D04FF4004303E0802301E04FF480
+S315080239000043626803EB5203B3FBF2F39BB2002651
+S3150802391010E64FF48043F4E74FF40053F1E741F21F
+S315080239205553EEE74FF48053EBE740F6CC43E8E70E
+S3150802393040F6AA23E5E74FF40063E2E74FF4806313
+S31508023940DFE74FF40073DCE74FF48073D9E701260B
+S315080239500023EFE50126F6E50126F4E50126F2E560
+S315080239600126F0E50126EEE5004402580090D00350
+S3150802397090D003000048E8010024F400AAC2A2007D
+S3150802398000127A0000A861005561510000093D0045
+S3150802399080841E0040420F0020A107002A2C0A003C
+S315080239A0801A06001516050048E80100836A13F016
+S315080239B0010F06D00268536823F40033C16A0B4329
+S315080239C05360836A13F0020F06D00268536823F421
+S315080239D08033016B0B435360836A13F0040F06D0DE
+S315080239E00268536823F48023416B0B435360836A4E
+S315080239F013F0080F06D00268536823F40043816B5C
+S31508023A000B435360836A13F0100F06D0026893685B
+S31508023A1023F48053C16B0B439360836A13F0200F20
+S31508023A2006D00268936823F40053016C0B43936033
+S31508023A30836A13F0400F0AD00268536823F480138E
+S31508023A40416C0B435360436CB3F5801F0BD0836AFA
+S31508023A5013F0800F06D00268536823F40023C16C62
+S31508023A600B43536070470268536823F4C003816CA2
+S31508023A700B435360EBE72DE9F04104460F46164621
+S31508023A809846069D2368DB6937EA03030CBF0123C0
+S31508023A900023B34241D1B5F1FF3FF3D0FCF77AFFD9
+S31508023AA0A0EB0800854223D315B323681A6812F0DF
+S31508023AB0040FE7D0DA6912F4006FE3D04FF400621C
+S31508023AC01A622268136823F4D07313602268936813
+S31508023AD023F0010393602023C4F88030C4F88430AD
+S31508023AE0C4F88830002384F87C300320BDE8F081CE
+S31508023AF02268136823F4D07313602268936823F04C
+S31508023B00010393602023C4F88030C4F8843000236C
+S31508023B1084F87C300320BDE8F0810020BDE8F081FE
+S31508023B202DE9F04383B01E46D0F88430202B03D00B
+S31508023B30022003B0BDE8F08304460D469046002AEB
+S31508023B4018BF002979D090F87C30012B01D10220C8
+S31508023B50EFE7012380F87C300023C0F8883022235F
+S31508023B60C0F88430FCF716FF0746A4F85C80A4F870
+S31508023B705E80A368B3F5805F06D0A3B9226972B9DD
+S31508023B80FF22A4F8602014E0226922B940F2FF124B
+S31508023B90A4F860200DE0FF22A4F8602009E07F2245
+S31508023BA0A4F8602005E0B3F1805F0AD00022A4F8E9
+S31508023BB06020B4F86080B3F5805F0CD04FF000093E
+S31508023BC01EE022691AB97F22A4F86020F1E73F2293
+S31508023BD0A4F86020EDE7236913B14FF000090FE05E
+S31508023BE0A94600250CE023685B6A08EA030329F85C
+S31508023BF0023BB4F85E309BB2013B9BB2A4F85E303E
+S31508023C00B4F85E309BB28BB100963B460022202167
+S31508023C102046FFF730FF90B9002DE4D023685A6A90
+S31508023C205FFA88F3134005F8013BE2E72023C4F85C
+S31508023C308430002084F87C007BE7012079E70320A2
+S31508023C4077E730B583B004460023C0F88830FCF71E
+S31508023C50A1FE054623681B6813F0080F0ED12368D8
+S31508023C601B6813F0040F17D12023C4F88030C4F858
+S31508023C708430002084F87C0003B030BD6FF07E43A8
+S31508023C800093034600224FF400112046FFF7F3FE85
+S31508023C900028E4D00320EFE76FF07E4300932B461B
+S31508023CA000224FF480012046FFF7E5FE0028DBD00C
+S31508023CB00320E1E778B310B50446D0F880300BB399
+S31508023CC02423C4F880302268136823F001031360A2
+S31508023CD02046FEF719FB01281FD0A36ABBB9226842
+S31508023CE0536823F4904353602268936823F02A03A7
+S31508023CF093602268136843F0010313602046FFF7B6
+S31508023D00A0FF10BD80F87C30FEF7FAFAD8E7204605
+S31508023D10FFF74CFEE3E70120704710BD184AD2F8B8
+S31508023D20883043F47003C2F88830164B1A6842F09A
+S31508023D3001021A6000221A611868134901401960C3
+S31508023D409A61DA611A629A62DA621A635A639A6342
+S31508023D50DA631A645A64196821F4802119601A66AA
+S31508023D600A4B1A680A4B1340B3F1005F02D20122CA
+S31508023D70084B1A604FF00062014B9A60704700BF09
+S31508023D8000ED00E0004402587FEDF6EA0010005C00
+S31508023D900000FFFF0881005110B4674B1B6903F04E
+S31508023DA03803102B00F0C580182B1ED0B3B1634A16
+S31508023DB061488369C3F303236149CB5CDA408369AB
+S31508023DC003F00F03CB5C03F01F0322FA03F35D49EA
+S31508023DD00B605D4B1A605DF8044B7047564B1B68C7
+S31508023DE0C3F3C103594ADA40E2E75349886A00F045
+S31508023DF003008A6AC2F30512CC6A04F001044B6B0B
+S31508023E00C3F3CC0303FB04F307EE903AF8EE677AA2
+S31508023E10002ACDD0012852D0F0B102286CD007EE84
+S31508023E20102AF8EE476A9FED4A6A86EE267A424BD0
+S31508023E301B6BC3F3080306EE903AF8EE666A9FED2B
+S31508023E40456A67EE867A76EEA77AF7EE006A77EE25
+S31508023E50A67A27EE277A22E037480168C1F3C1011C
+S31508023E603A4BCB4007EE103AF8EE476A07EE102AAD
+S31508023E70B8EE476A86EE867A036BC3F3080306EE44
+S31508023E80903AF8EE666A9FED336A67EE867A76EEC0
+S31508023E90A77AF7EE006A77EEA67A27EE277A264BF6
+S31508023EA01B6BC3F34623013307EE903AF8EE677AA3
+S31508023EB0C7EE276AFCEEE67A17EE902A78E707EE4F
+S31508023EC0102AF8EE476A9FED226A86EE267A1A4B80
+S31508023ED01B6BC3F3080306EE903AF8EE666A9FED8B
+S31508023EE01D6A67EE867A76EEA77AF7EE006A77EEAD
+S31508023EF0A67A27EE277AD2E707EE102AF8EE476A5D
+S31508023F009FED156A86EE267A0B4B1B6BC3F30803E5
+S31508023F1006EE903AF8EE666A9FED0E6A67EE867AC4
+S31508023F2076EEA77AF7EE006A77EEA67A27EE277A72
+S31508023F30B5E70A4A3CE700BF0044025800093D00BB
+S31508023F40484302080C000020080000200090D00315
+S31508023F500024744A000000390024F44A00127A0048
+S31508023F60014B024A9A60704700ED00E00000020821
+S31508023F7000B59DB04C22002109A800F090F9202234
+S31508023F80002101A800F08BF90220FDF707FA0023A9
+S31508023F900093254B9A6942F440429A619B6903F45D
+S31508023FA040430093214BDA6A42F00102DA62DB6A85
+S31508023FB003F001030093009B1B4B9B6913F4005FFC
+S31508023FC0FAD0012309934FF4A0230A9302231293EA
+S31508023FD01393042214924FF4F071159116931792C3
+S31508023FE01893199200231A931B9309A8FDF700FA4E
+S31508023FF000B1FEE73F2301930323029300230393B1
+S31508024000082304934023059306934FF4806207928C
+S31508024010089304210DEB0100FDF7DAFD00B1FEE776
+S315080240201DB05DF804FB00BF0048025800040058A2
+S3150802403008B5FFF795FFFCF773FCFFF799FF00F049
+S31508024040DBF8FCF715FC08BD08B5FFF7F1FFFCF72E
+S3150802405079FBFCF717FCFCF705FCFAE7F0B58DB01F
+S315080240604D4BD3F8F42042F00202C3F8F420D3F8F9
+S31508024070F42002F002020192019AD3F8E02042F0FB
+S315080240800202C3F8E020D3F8E02002F0020202920C
+S31508024090029AD3F8E02042F00402C3F8E020D3F8EB
+S315080240A0E02002F004020392039AD3F8E02042F0D9
+S315080240B00802C3F8E020D3F8E02002F008020492CE
+S315080240C0049AD3F8E82042F48022C3F8E820D3F809
+S315080240D0E82002F480220592059AD3F8EC2042F4ED
+S315080240E08072C3F8EC20D3F8EC3003F4807306939D
+S315080240F0069B0320FCF75AFC002211466FF00B00C0
+S31508024100FCF766FC002211466FF00A00FCF760FC19
+S31508024110002211466FF00900FCF75AFC00221146EC
+S315080241206FF00400FCF754FC002211466FF00300FE
+S31508024130FCF74EFC002211466FF00100FCF748FC22
+S31508024140002211464FF0FF30FCF742FC802307930A
+S3150802415001230893002409940A94104D07A92846B6
+S31508024160FDF71EF84FF4407707970226089609943A
+S315080241700A9407230B9307A90948FDF711F807972D
+S31508024180089609940A9409230B9307A92846FDF76A
+S3150802419007F80DB0F0BD00BF0044025800040258EB
+S315080241A0000C0258DFF834D0002103E00C4B5B58B0
+S315080241B0435004310B480C4B42189A42F6D30B4A29
+S315080241C002E0002342F8043B094B9A42F9D3FFF76F
+S315080241D0A5FD00F035F8FFF737FF7047000002200B
+S315080241E0684302080000002010000020100000208A
+S315080241F0AC010020FEE7000008B5FFF7CDFD094B2C
+S315080242001868094BA3FB00308009FCF711FC04204F
+S31508024210FCF724FC002211464FF0FF30FCF7D8FBCE
+S3150802422008BD00BF08000020D34D621008B5FCF790
+S31508024230B1FB08BD08B5FCF7A1FBFCF720FC08BDDD
+S3150802424070B50D4E0D4CA41BA4100025A54209D12C
+S315080242500B4E0C4C00F02CF8A41BA4100025A5420A
+S3150802426005D170BD56F8253098470135EEE756F860
+S31508024270253098470135F2E7604302086043020891
+S31508024280604302086443020810B5431E0A44914279
+S3150802429000D110BD11F8014B03F8014FF7E70244AC
+S315080242A00346934200D1704703F8011BF9E7000061
+S315080242B0F8B500BFF8BC08BC9E467047F8B500BF03
+S30D080242C0F8BC08BC9E467047D3
+S315080242C800000000000000000000000000000000D6
+S315080242D800000000010000000200000003000000C0
+S315080242E804000000000000000500000000000000AD
+S315080242F800000000000000000600000000000000A0
+S31508024308000000000000000007000000050206027F
+S31508024318060307030803090309040A040B040C0421
+S315080243280C050D050E050F050F06100610071008D1
+S315080243380001020304050607080C10141820304069
+S315080243480000000001020304010203040607080923
+S30D08024358B8BFFF7F0100000057
+S30908024360C502020878
+S30908024364A102020898
+S3150802436801000000100000000090D0030090D0035E
+S705080241A50A
diff --git a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_TrueStudio/Prog/boot.c b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_TrueStudio/Prog/boot.c
index 194de0e1..c7cf91bb 100644
--- a/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_TrueStudio/Prog/boot.c
+++ b/Target/Demo/ARMCM7_STM32H7_Nucleo_H743ZI_TrueStudio/Prog/boot.c
@@ -376,12 +376,12 @@ static void BootComCanInit(void)
     canHandle.Init.StdFiltersNbr = 0;
     canHandle.Init.ExtFiltersNbr = 1;
   }
-  /* only one reception buffer is needed. reception FIFO 0 and 1 are not used. */
-  canHandle.Init.RxFifo0ElmtsNbr = 0;
+  /* only reception FIFO 0 is used. */
+  canHandle.Init.RxFifo0ElmtsNbr = 1;
   canHandle.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_8;
   canHandle.Init.RxFifo1ElmtsNbr = 0;
   canHandle.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_8;
-  canHandle.Init.RxBuffersNbr = 1;
+  canHandle.Init.RxBuffersNbr = 0;
   canHandle.Init.RxBufferSize = FDCAN_DATA_BYTES_8;
   /* no transmit buffer is needed. transmit FIFO is not used. */
   canHandle.Init.TxEventsNbr = 0;
@@ -411,12 +411,16 @@ static void BootComCanInit(void)
   }
   filterConfig.FilterIndex = 0;
   filterConfig.FilterType = FDCAN_FILTER_DUAL;
-  filterConfig.FilterConfig = FDCAN_FILTER_TO_RXBUFFER;
+  filterConfig.FilterConfig = FDCAN_FILTER_TO_RXFIFO0;
   filterConfig.FilterID1 = rxMsgId;
   filterConfig.FilterID2 = rxMsgId;
   filterConfig.RxBufferIndex = 0;
   (void)HAL_FDCAN_ConfigFilter(&canHandle, &filterConfig);
 
+  /* configure global filter to reject all non-matching frames. */
+  HAL_FDCAN_ConfigGlobalFilter(&canHandle, FDCAN_REJECT, FDCAN_REJECT, 
+                               FDCAN_REJECT_REMOTE, FDCAN_REJECT_REMOTE);
+  
   /* start the CAN peripheral. no need to evaluate the return value as there is nothing
    * we can do about a faulty CAN controller. */
   (void)HAL_FDCAN_Start(&canHandle);
@@ -440,10 +444,10 @@ static void BootComCanCheckActivationRequest(void)
 
 
   /* poll for received CAN messages that await processing. */
-  if (HAL_FDCAN_IsRxBufferMessageAvailable(&canHandle, FDCAN_RX_BUFFER0) > 0)
+  if (HAL_FDCAN_GetRxFifoFillLevel(&canHandle, FDCAN_RX_FIFO0) > 0)
   {
     /* attempt to read the newly received CAN message from its buffer. */
-    rxStatus = HAL_FDCAN_GetRxMessage(&canHandle, FDCAN_RX_BUFFER0, &rxMsgHeader,
+    rxStatus = HAL_FDCAN_GetRxMessage(&canHandle, FDCAN_RX_FIFO0, &rxMsgHeader,
                                       rxMsgData);
   }
 
diff --git a/Target/Source/ARMCM7_STM32H7/can.c b/Target/Source/ARMCM7_STM32H7/can.c
index ade1b001..be24d0ec 100644
--- a/Target/Source/ARMCM7_STM32H7/can.c
+++ b/Target/Source/ARMCM7_STM32H7/can.c
@@ -212,12 +212,12 @@ void CanInit(void)
     canHandle.Init.StdFiltersNbr = 0;
     canHandle.Init.ExtFiltersNbr = 1;
   }
-  /* only one reception buffer is needed. reception FIFO 0 and 1 are not used. */
-  canHandle.Init.RxFifo0ElmtsNbr = 0;
+  /* only reception FIFO 0 is used. */
+  canHandle.Init.RxFifo0ElmtsNbr = 1;
   canHandle.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_8;
   canHandle.Init.RxFifo1ElmtsNbr = 0;
   canHandle.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_8;
-  canHandle.Init.RxBuffersNbr = 1;
+  canHandle.Init.RxBuffersNbr = 0;
   canHandle.Init.RxBufferSize = FDCAN_DATA_BYTES_8;
   /* only one transmit buffer is needed. transmit FIFO is not used. */
   canHandle.Init.TxEventsNbr = 0;
@@ -247,12 +247,16 @@ void CanInit(void)
   }
   filterConfig.FilterIndex = 0;
   filterConfig.FilterType = FDCAN_FILTER_DUAL;
-  filterConfig.FilterConfig = FDCAN_FILTER_TO_RXBUFFER;
+  filterConfig.FilterConfig = FDCAN_FILTER_TO_RXFIFO0;
   filterConfig.FilterID1 = rxMsgId;
   filterConfig.FilterID2 = rxMsgId;
   filterConfig.RxBufferIndex = 0;
   (void)HAL_FDCAN_ConfigFilter(&canHandle, &filterConfig);
 
+  /* configure global filter to reject all non-matching frames. */
+  HAL_FDCAN_ConfigGlobalFilter(&canHandle, FDCAN_REJECT, FDCAN_REJECT, 
+                               FDCAN_REJECT_REMOTE, FDCAN_REJECT_REMOTE);
+  
   /* start the CAN peripheral. no need to evaluate the return value as there is nothing
    * we can do about a faulty CAN controller. */
   (void)HAL_FDCAN_Start(&canHandle);
@@ -344,10 +348,10 @@ blt_bool CanReceivePacket(blt_int8u *data, blt_int8u *len)
   HAL_StatusTypeDef     rxStatus = HAL_ERROR;
 
   /* check if the expected CAN message was received? */
-  if (HAL_FDCAN_IsRxBufferMessageAvailable(&canHandle, FDCAN_RX_BUFFER0) > 0)
+  if (HAL_FDCAN_GetRxFifoFillLevel(&canHandle, FDCAN_RX_FIFO0) > 0)
   {
     /* attempt to read the newly received CAN message from its buffer. */
-    rxStatus = HAL_FDCAN_GetRxMessage(&canHandle, FDCAN_RX_BUFFER0, &rxMsgHeader, data);
+    rxStatus = HAL_FDCAN_GetRxMessage(&canHandle, FDCAN_RX_FIFO0, &rxMsgHeader, data);
   }
 
   /* only continue processing the CAN message if something was received. */